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+TACCR +TACCTL +TACLR +TACTL +TBCTRL +TBLPTRH +TBLPTRL +TBLPTRU +TBLPTRUH +TBLPTRUL +TBQP +TBSY +tcclks +TCCR +TCKPS +TCLK +TCMR +TCOMP +TDES +TDESMOD +TDMI +TDRE +TEOF +TFLG +TFMR +TGRA +THALT +TIAO +TICKISR +TIMFRZ +TIMSK +TIOA +TIOB +tmcsr +TMCSR +TMIF +TMKAEN +TMKAIF +TMKAMK +TMMK +TMPR +TMRLR +TNCR +TNPR +TOSU +TOVF +TPCS +TPFR +TRAPA +TRGEN +TRGSEL +TSHR +tstfsz +TSTP +TSTR +TTGR +TUND +TUNDR +TWCK +TXBUFE +TXCOMP +TXDIS +TXEMPTY +TXEN +TXENA +TXERR +TXIE +TXIF +TXPKTRDY +TXRDY +TXSYN +TXTEN +TXUBR +TXVC +TXVDIS +UBTI +UDCP +UNACKED +uncrustify +UNDADD +unpadded +Unpadded +UNPADDED +unprotect +Unprotect +Unprotected +UNRE +UNSUB +UNSUBACK +unsubscriptions +unsuspended +unupdated +UPAC +URAD +URAT +URSTEN +URSTIEN +URSTS +Usart +USART +USPRG +USRIO +utest +utilises +utilising +vcsr +VDDCORE +vect +Vect +VECT +VECTACTIVE +VECTKEY +visualisation +vldmdbeq +vldmia +vldmiaeq +vlenb +VMSRNE +vpop +VPOPNE +vpush +VPUSHNE +VRPM +Vrtc +vsetvl +vstmdbeq +vstmiaeq +VTOR +W +WAVESEL +wavsel +Wcolor +Wconversion +WDCR +WDDBGHLT +WDDIS +WDERR +WDFIEN +WDIDLEHLT +WDMR +WDRPROC +WDRSTEN +WDRSTT +WDSR +WDTC +wdtcon +WDUNF +Werror +WESTAT +Weverything +Wextra +winmm +WIZC +Wpedantic +wrdsp +WREG +Wunused +XEXC +XPAR +xparameters +XPSR +XRAM +xtal +XTENSA diff --git a/.github/CODEOWNERS b/.github/CODEOWNERS new file mode 100644 index 000000000..771aee37d --- /dev/null +++ b/.github/CODEOWNERS @@ -0,0 +1,37 @@ +# Each line is a file pattern followed by one or more owners. + +# These owners will be the default owners for everything in +# the repo. Unless a later match takes precedence, +# @global-owner1 and @global-owner2 will be requested for +# review when someone opens a pull request. +* @FreeRTOS/pr-bar-raisers + +# Order is important; the last matching pattern takes the most +# precedence. When someone opens a pull request that only +# modifies JS files, only @js-owner and not the global +# owner(s) will be requested for a review. +# *.c FreeRTOS/pr-bar-raiser + +# You can also use email addresses if you prefer. They'll be +# used to look up users just like we do for commit author +# emails. +# *.go docs@example.com + +# In this example, @doctocat owns any files in the build/logs +# directory at the root of the repository and any of its +# subdirectories. +# /build/logs/ @doctocat + +# The `docs/*` pattern will match files like +# `docs/getting-started.md` but not further nested files like +# `docs/build-app/troubleshooting.md`. +# docs/* docs@example.com + +# In this example, @octocat owns any file in an apps directory +# anywhere in your repository. +# apps/ @octocat + +# In this example, @doctocat owns any file in the `/docs` +# directory in the root of your repository and any of its +# subdirectories. +# /docs/ @doctocat diff --git a/.github/CONTRIBUTING.md b/.github/CONTRIBUTING.md new file mode 100644 index 000000000..39d075d55 --- /dev/null +++ b/.github/CONTRIBUTING.md @@ -0,0 +1,70 @@ +# Contribution guidelines + +Thank you for your interest in contributing to our project. Whether it's a bug report, new feature, code, or +documentation, we welcome our community to be involved in this project. + +Please read through this document before submitting any issues or pull requests to ensure we are able to help you and all members of the community as effectively as possible. + +## Code of conduct +This project has adopted the [Amazon Open Source Code of Conduct](https://aws.github.io/code-of-conduct). +For more information see the [Code of Conduct FAQ](https://aws.github.io/code-of-conduct-faq) or contact +opensource-codeofconduct@amazon.com with any additional questions or comments. + + +## Security issue notifications +If you discover a potential security issue in this project we ask that you notify AWS/Amazon Security via our [vulnerability reporting page](https://aws.amazon.com/security/vulnerability-reporting/). Please do **not** create a public github issue. + + +## Submitting a bugs/feature request +Have a bug to report or feature to request? Follow these steps: +1. Search on the [FreeRTOS Community Support Forums](https://forums.freertos.org/) and [GitHub issue tracker](https://github.com/FreeRTOS/FreeRTOS/issues?utf8=%E2%9C%93&q=is%3Aissue) to be sure this hasn't been already reported or discussed. +2. If your search turns up empty, create a new topic in the [forums](https://forums.freertos.org/) and work with the community to help clarify issues or refine the idea. Include as many of the details listed below. +3. Once the community has had time to discuss and digest, we welcome you to create an [issue](https://github.com/FreeRTOS/FreeRTOS/issues) to report bugs or suggest features. + +When creating a new topic on the forums or filing an issue, please include as many relevant details as possible. Examples include: + +* A clear description of the situation - what you observe, what you expect, and your view on how the two differ. +* A reproducible test case or sequence of steps. +* The version of our code being used. +* Any modifications you've made relevant to the bug. +* Details of your environment or deployment. Highlight anything unusual. + + +## Contributing via pull request +Contributions via pull requests are much appreciated. Before sending us a pull request, please ensure that: + +1. You are working against the latest source on the *main* branch. +2. You check existing open, and recently merged, pull requests to make sure someone else hasn't addressed the problem already. +3. You open an issue to discuss any significant work - we would hate for your time to be wasted. + +To send us a pull request, please: + +1. Fork the repository. +2. Modify the source; focus on the specific change you are contributing. If you also reformat all the code, it will be hard for us to focus on your change. +3. Follow the [coding style guide](https://www.FreeRTOS.org/FreeRTOS-Coding-Standard-and-Style-Guide.html). +4. Commit to your fork using clear commit messages. +5. Send us a pull request, answering any default questions in the pull request interface. + NOTE: Please make sure the default option (Allow edits from maintainers) is left checked. +6. Pay attention to any automated CI failures reported in the pull request, and stay involved in the conversation. + +GitHub provides additional document on [forking a repository](https://help.github.com/articles/fork-a-repo/) and +[creating a pull request](https://help.github.com/articles/creating-a-pull-request/). + +## Coding style +* Please ensure that your code complies to the [FreeRTOS coding style guidelines](https://www.FreeRTOS.org/FreeRTOS-Coding-Standard-and-Style-Guide.html). + + +## Getting your pull request merged +All pull requests must be approved by our review team before it can be merged in. We appreciate your patience while pull requests are reviewed. The time it takes to review will depend on complexity and consideration of wider implications. For more information on the pull request process, please see the documentation [here](pull_request_process.md). + + +## Finding contributions to work on +Looking at the existing issues is a great way to find something to contribute on. As our projects, by default, use the default GitHub issue labels (enhancement/bug/duplicate/help wanted/invalid/question/wontfix), tackling open 'help wanted' issues is a great place to start. + + +## Licensing +The FreeRTOS kernel is released under the MIT open source license, the text of which can be found [here](https://github.com/FreeRTOS/FreeRTOS/blob/main/FreeRTOS/License/license.txt) + +Additional license files can be found in the folders containing any supplementary libraries licensed by their respective copyright owners where applicable. + +We may ask you to sign a [Contributor License Agreement (CLA)](https://en.wikipedia.org/wiki/Contributor_License_Agreement) for larger changes. diff --git a/.github/ISSUE_TEMPLATE/bug-report.md b/.github/ISSUE_TEMPLATE/bug-report.md new file mode 100644 index 000000000..96f3595f3 --- /dev/null +++ b/.github/ISSUE_TEMPLATE/bug-report.md @@ -0,0 +1,40 @@ +--- +name: Bug report +about: Create a report to help us improve FreeRTOS. This should only be used for confirmed + bugs. If you suspect something it is best to first discuss it on the FreeRTOS community + support forums linked below. +title: "[BUG]" +labels: bug +assignees: '' + +--- + +**Describe the bug** +A concise description of what the bug is. + +**Target** +- Development board: [e.g. HiFive11 RevB] +- Instruction Set Architecture: [e.g. RV32IMAC] +- IDE and version: [e.g. Freedom Studio 4.12.0.2019-08-2] +- Toolchain and version: [e.g. riscv64-unknown-elf-gcc-8.3.0-2019.08.0] + +**Host** +- Host OS: [e.g. MacOS] +- Version: [e.g. Mojave 10.14.6] + +**To Reproduce** +- Use project ... and configure with ... +- Run on ... and could observe ... + +**Expected behavior** +A concise description of what you expected to happen. + +**Screenshots** +If applicable, add screenshots to help explain your problem. + +**Additional context** +Add any other context about the problem here. +e.g. code snippet to reproduce the issue. +e.g. stack trace, memory dump, debugger log, and many etc. + + diff --git a/.github/ISSUE_TEMPLATE/config.yml b/.github/ISSUE_TEMPLATE/config.yml new file mode 100644 index 000000000..61f729c92 --- /dev/null +++ b/.github/ISSUE_TEMPLATE/config.yml @@ -0,0 +1,5 @@ +blank_issues_enabled: false +contact_links: + - name: FreeRTOS Community Support Forum + url: https://forums.freertos.org/ + about: Please ask and answer questions about FreeRTOS here. diff --git a/.github/ISSUE_TEMPLATE/documentation-issue.md b/.github/ISSUE_TEMPLATE/documentation-issue.md new file mode 100644 index 000000000..e5c1a192c --- /dev/null +++ b/.github/ISSUE_TEMPLATE/documentation-issue.md @@ -0,0 +1,23 @@ +--- +name: Documentation issue +about: Create a report to help us improve our documentation. +title: "[DOC]" +labels: documentation +assignees: '' + +--- + +**Describe the issue** +Please describe the issue and expected clarification in concise language. + +**Reference** +Please attach the URL at which you are experiencing the issue. + +**Screenshot** +If applicable, please attach screenshot. + +**Browser** +- Browser: [e.g. Chrome] +- Version: [e.g. 80.0.3987.132] + + diff --git a/.github/ISSUE_TEMPLATE/feature_request.md b/.github/ISSUE_TEMPLATE/feature_request.md new file mode 100644 index 000000000..645f68480 --- /dev/null +++ b/.github/ISSUE_TEMPLATE/feature_request.md @@ -0,0 +1,30 @@ +--- +name: Feature request +about: Suggest a new feature for this project +title: "[Feature Request] " +labels: enhancement +assignees: '' + +--- + +**Is your feature request related to a problem? Please describe.** +A clear and concise description of what the problem is. Ex. I'm always frustrated when [...] + +**Describe the solution you'd like** +A clear and concise description of what you want to happen. + +**Describe alternatives you've considered** +A clear and concise description of any alternative solutions or features you've considered. + +**How many devices will this feature impact?** +Expected volume for your product. + +**What are your project timelines?** +Timeline for milestones such as design completion, testing and validation, and production. + +**Additional context** +Add any other context or screenshots about the feature request here. + + +If you have the same (or similar) feature request, please upvote this issue with thumbs up 👍 +and use the comments section to provide answers to the questions above. diff --git a/.github/SECURITY.md b/.github/SECURITY.md new file mode 100644 index 000000000..1472c0c86 --- /dev/null +++ b/.github/SECURITY.md @@ -0,0 +1,5 @@ +## Reporting a Vulnerability + +If you discover a potential security issue in this project we ask that you notify AWS/Amazon Security +via our [vulnerability reporting page](https://aws.amazon.com/security/vulnerability-reporting/) or directly via email to aws-security@amazon.com. +Please do **not** create a public github issue. diff --git a/.github/allowed_urls.txt b/.github/allowed_urls.txt new file mode 100644 index 000000000..fc6d21152 --- /dev/null +++ b/.github/allowed_urls.txt @@ -0,0 +1,5 @@ +https://www.renesas.com/us/en/document/mah/rh850f1k-group-users-manual-hardware?r=1170166 +https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rh850-automotive-mcus +https://www.renesas.com/us/en/software-tool/c-compiler-package-rh850-family#downloads +https://www.microchip.com +https://www.microchip.com/support diff --git a/.github/media/pr_process.png b/.github/media/pr_process.png new file mode 100644 index 000000000..0d964c128 Binary files /dev/null and b/.github/media/pr_process.png differ diff --git a/.github/pull_request_process.md b/.github/pull_request_process.md new file mode 100644 index 000000000..5b8556df9 --- /dev/null +++ b/.github/pull_request_process.md @@ -0,0 +1,115 @@ +# Pull Request Process + +This document explains the stages that a Pull Request (PR) goes through when a pull request is submitted to a git repository in the FreeRTOS organization in Github. Before you start a PR, please read and familiarize yourself with [CONTRIBUTING.md](CONTRIBUTING.md) + +## ****Terminologies**** + +**FreeRTOS Partner Contributors**: These are selected developers and experts from community. + +**FreeRTOS Team**: The FreeRTOS team consists of “AWS employees”. + +**CODEOWNERS**: For all the FreeRTOS repositories, “FreeRTOS Team” and/or “FreeRTOS Partner contributors” will be CODEOWNER. + +**Contributor**: The Contributor is the person who submitted the pull request. + +**Assignee**: The Assignee is an AWS Employee who is responsible for identifying reviewers and managing the PR. They track the progress of pull requests and ensure that they are reviewed and merged in a timely manner. + +**Reviewer**: Reviewers are responsible for reviewing pull requests and providing feedback to the contributor. Two approving reviews, one of which must be from the CODEOWNER of the reposiroty, are required for a PR to be merged. + + +## ****Pull Request Life-Cycle**** + +Once a pull request (PR) is submitted, it goes through the following stages: + +1. Open + 1. The PR is created. + 2. All the GitHub Actions pass and the PR is ready to be reviewed. +2. Triage + 1. The PR is assigned to an assignee. + 2. The assignee assigns a reviewer from the FreeRTOS Team to the PR. +3. Review + 1. The reviewer provides feedback and discusses open questions with the contributor, if needed. + 2. If the contributor and the reviewer conclude, after discussion, that the PR will not be merged, then the PR is closed. + 3. The PR contributor addresses the feedback and makes changes to the PR, if needed. + 4. The reviewer approves the PR and assigns a second reviewer. +4. Second Review + 1. The second reviewer reviews the PR and provides feedback, if needed. + 2. The PR contributor addresses the feedback and makes changes to the PR, if needed. + 3. The second reviewer approves the PR. +5. Testing + 1. One of the reviewers tests the PR to ensure that it works correctly. +6. Ready to Merge + A PR becomes Ready to Merge when all the branch protection rules are satisfied. We have branch protection rules which require the following: + 1. At least 2 reviews. + 2. One review from the CODEOWNER of the given repository. + 3. All PR checks must pass. +7. Merge + 1. The PR is merged. + +
+ +The status of a PR is indicated through GitHub labels added by Reviewers/Assignees. The following are the most common status indicators: Triaged, Reviewer Assigned, Concept ACK/NACK, First Code Review In Progress, First Code Review Complete, Second Code Review In Progress, Second Code Review Complete, Testing In Progress and Testing Complete. + +Please note that we may decide to skip some stages depending on the type of PR. For example, a PR with a simple doc update will likely not go through all the above stages, however every PR is required to get approvals from 2 reviewers. + +The pictorial representation of our PR process is shown below. + +![PR Process](media/pr_process.png) + + +
+ +## **Turnaround Times** + +The length of time required to review a PR is unpredictable and varies from PR to PR since it depends on the complexity of the changes, availability of reviewers, and overall workload of the team. We generally attempt to resolve each PR in accordance with the timeframes below, excluding weekends and public holidays: + +* Triage: < 24 hours +* Concept ACK/NACK: 1-2 weeks +* Code Review: 1-2 weeks +* Testing: 1-2 weeks + + +## **Addressing the changes requested by reviewers** + +The author should address any review comments in 4 weeks or less. If the author is unable to address the comments in that time, we will do one of the following: + +* Make the required changes ourselves and merge the pull request. +* Close the pull request. + +
+ +### **Best Practices for Faster Reviews** + +Here are some best practices to follow so that your PR gets reviewed quickly. + +1. If you plan to contribute a new feature to FreeRTOS, please get confirmation beforehand that the FreeRTOS team and community want, and will accept, this feature. This is true especially when you plan to make large or significant changes. To get confirmation and feedback from FreeRTOS Team and community, create a post in the FreeRTOS forums. +2. Smaller is better. Small, focused PR’s are reviewed more quickly and thoroughly, are simpler to rollback, and involve less wasted effort if rejected. Avoid opening pull requests that span the whole repository. +3. Don’t mix refactoring, bug fixes and feature development into a single PR. Lets say you are developing feature-x and you come across poorly named variables or incomplete/incorrect comments. You should consider fixing those, but in a separate PR, not in the same PR as feature-x. +4. Comments matter. The code you develop will need to be maintained for a long time. Well placed comments provide context to your reviewers, maintainers and users, and also prevent them from misunderstanding the purpose of the code. However, DO NOT add comments to explain things which are obvious by just glancing at the code. [Good Read: https://stackoverflow.blog/2021/12/23/best-practices-for-writing-code-comments/] +5. Test your PR. In your PR, please accompany your changes with suitable unit tests and any other tests that will be helpful, and include descriptions of how to perform any manual tests. Instructions for unit tests can be found at [freertos.org](https://freertos.org/FreeRTOS-Coding-Standard-and-Style-Guide.html#Testing) and [Github](https://github.com/FreeRTOS/FreeRTOS/blob/main/FreeRTOS/Test/CMock/Readme.md) + + +**Push Back its ok:** +Sometimes reviewers make mistakes. If a reviewer has requested you to make changes and you feel strongly about doing it a certain way, you are free to debate the merits of the requested change with the reviewer, while still following the code of conduct. You might be overruled, but you might also prevail. + +**Be Pragmatic** +Put a bit of thought into how your PR can be made easier to review and merge. No document can replace common sense and good taste. The best practices shared here and the contribution guidelines, if followed, will help you get your code reviewed and merged with less friction. + +
+ +### **Why is my PR closed?** + +Pull requests older than 120 days or not in-line with scope of the project will be closed. Exceptions can be made for pull requests that have active review comments, or that are awaiting other dependent pull requests. Closed pull requests are easy to recreate, and little work is lost by closing a pull request that is subsequently reopened. We want to limit the total number of pull requests in flight to: + +* Maintain a clean project +* Remove old pull requests that would be difficult to rebase since the underlying code has changed over time +* Encourage code velocity + +### **Why is my PR not getting reviewed/merged?** + +* It may be because of a feature freeze due to an upcoming release. During this time, only bug fixes are taken into consideration. If your pull request is a new feature, it will not be prioritised until after the release. Wait for the release. +* It could be related to best practices (see contributing.md) not being followed. One common issue is that the pull request is too big to review. Let’s say you’ve touched 21 files and have 9347 insertions. When your would-be reviewers pull up the diffs, they run away - this pull request is going to take a few hours to review and they don’t have a few hours right now. They’ll get to it later, just as soon as they have more free time (ha!). +* If you think the above two situations are not the reason, and you are not getting some pull request love, please drop a couple of reminders on the PR comments. If everything else fails, please create a post on FreeRTOS forums with link to PR. + + + diff --git a/.github/pull_request_template.md b/.github/pull_request_template.md new file mode 100644 index 000000000..a39aa2bfa --- /dev/null +++ b/.github/pull_request_template.md @@ -0,0 +1,23 @@ + + +Description +----------- + + +Test Steps +----------- + + +Checklist: +---------- + + +- [ ] I have tested my changes. No regression in existing tests. +- [ ] I have modified and/or added unit-tests to cover the code changes in this Pull Request. + +Related Issue +----------- + + + +By submitting this pull request, I confirm that you can use, modify, copy, and redistribute this contribution, under the terms of your choice. diff --git a/.github/scripts/find_replace.sh b/.github/scripts/find_replace.sh new file mode 100755 index 000000000..ee94ea120 --- /dev/null +++ b/.github/scripts/find_replace.sh @@ -0,0 +1,6 @@ +#!/bin/bash +old_text=$1 +new_text=$2 +echo "Old text: ${old_text}" +echo "New text: ${new_text}" +grep -rl "${old_text}" . | xargs gsed -i -e '1h;2,$H;$!d;g' -e "s/${old_text}/${new_text}/g" diff --git a/.github/scripts/kernel_checker.py b/.github/scripts/kernel_checker.py new file mode 100755 index 000000000..6627edc4d --- /dev/null +++ b/.github/scripts/kernel_checker.py @@ -0,0 +1,261 @@ +#!/usr/bin/env python3 +#/* +# * FreeRTOS Kernel +# * Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# * +# * SPDX-License-Identifier: MIT +# * +# * Permission is hereby granted, free of charge, to any person obtaining a copy of +# * this software and associated documentation files (the "Software"), to deal in +# * the Software without restriction, including without limitation the rights to +# * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +# * the Software, and to permit persons to whom the Software is furnished to do so, +# * subject to the following conditions: +# * +# * The above copyright notice and this permission notice shall be included in all +# * copies or substantial portions of the Software. +# * +# * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +# * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +# * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +# * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +# * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# * +# * https://www.FreeRTOS.org +# * https://github.com/FreeRTOS +# * +# */ + +import os +import re +from common.header_checker import HeaderChecker + +#-------------------------------------------------------------------------------------------------- +# CONFIG +#-------------------------------------------------------------------------------------------------- +KERNEL_IGNORED_FILES = [ + 'FreeRTOS-openocd.c', + 'Makefile', + '.DS_Store', + 'cspell.config.yaml', + '.clang-format' +] + +KERNEL_IGNORED_EXTENSIONS = [ + '.yml', + '.css', + '.idx', + '.md', + '.url', + '.sty', + '.0-rc2', + '.s82', + '.js', + '.out', + '.pack', + '.2', + '.1-kernel-only', + '.0-kernel-only', + '.0-rc1', + '.readme', + '.tex', + '.png', + '.bat', + '.sh', + '.txt', + '.cmake', + '.config' +] + +KERNEL_ASM_EXTENSIONS = [ + '.s', + '.S', + '.src', + '.inc', + '.s26', + '.s43', + '.s79', + '.s85', + '.s87', + '.s90', + '.asm', + '.h' +] + +KERNEL_PY_EXTENSIONS = [ + '.py' +] + +KERNEL_IGNORED_PATTERNS = [ + r'.*\.git.*', + r'.*portable/IAR/AtmelSAM7S64/.*AT91SAM7.*', + r'.*portable/GCC/ARM7_AT91SAM7S/.*', + r'.*portable/MPLAB/PIC18F/stdio.h', + r'.*portable/ThirdParty/xClang/XCOREAI/*', + r'.*IAR/ARM_C*', + r'.*IAR/78K0R/*', + r'.*CCS/MSP430X/*', + r'.*portable/template/*', + r'.*template_configuration/*' +] + +KERNEL_THIRD_PARTY_PATTERNS = [ + r'.*portable/ThirdParty/GCC/Posix/port*', + r'.*portable/ThirdParty/*', + r'.*portable/IAR/AVR32_UC3/.*', + r'.*portable/GCC/AVR32_UC3/.*', +] + +KERNEL_ARM_COLLAB_FILES_PATTERNS = [ + r'.*portable/ARMv8M/*', + r'.*portable/.*/ARM_CM23*', + r'.*portable/.*/ARM_CM33*', + r'.*portable/.*/ARM_CM35*', + r'.*portable/.*/ARM_CM52*', + r'.*portable/.*/ARM_CM55*', + r'.*portable/.*/ARM_CM85*', + r'.*portable/.*/ARM_CM0*', + r'.*portable/.*/ARM_CM3_MPU*', + r'.*portable/.*/ARM_CM4_MPU*', + r'.*portable/.*/ARM_CM4F_MPU*', + r'.*portable/.*/ARM_CR82*', + r'.*portable/.*/ARM_STAR_MC3*', + r'.*include/task\.h$', + r'.*tasks\.c$', +] + +KERNEL_HEADER = [ + '/*\n', + ' * FreeRTOS Kernel \n', + ' * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.\n', + ' *\n', + ' * SPDX-License-Identifier: MIT\n', + ' *\n', + ' * Permission is hereby granted, free of charge, to any person obtaining a copy of\n', + ' * this software and associated documentation files (the "Software"), to deal in\n', + ' * the Software without restriction, including without limitation the rights to\n', + ' * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n', + ' * the Software, and to permit persons to whom the Software is furnished to do so,\n', + ' * subject to the following conditions:\n', + ' *\n', + ' * The above copyright notice and this permission notice shall be included in all\n', + ' * copies or substantial portions of the Software.\n', + ' *\n', + ' * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n', + ' * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n', + ' * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n', + ' * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n', + ' * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n', + ' * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n', + ' *\n', + ' * https://www.FreeRTOS.org\n', + ' * https://github.com/FreeRTOS\n', + ' *\n', + ' */\n', +] + + +FREERTOS_COPYRIGHT_REGEX = r"^(;|#)?( *(\/\*|\*|#|\/\/))? Copyright \(C\) 20\d\d Amazon.com, Inc. or its affiliates. All Rights Reserved\.( \*\/)?$" + +FREERTOS_ARM_COLLAB_COPYRIGHT_REGEX = r"(^(;|#)?( *(\/\*|\*|#|\/\/))? Copyright \(C\) 20\d\d Amazon.com, Inc. or its affiliates. All Rights Reserved\.( \*\/)?$)|" + \ + r"(^(;|#)?( *(\/\*|\*|#|\/\/))? Copyright 20\d\d(-20\d\d)? Arm Limited and/or its affiliates( +)?( \*\/)?$)|" + \ + r"(^(;|#)?( *(\/\*|\*|#|\/\/))? Copyright \(c\) 20\d\d(-20\d\d)? Arm Technology \(China\) Co., Ltd.All Rights Reserved\.( \*\/)?$)|" + \ + r"(^(;|#)?( *(\/\*|\*|#|\/\/))? ( \*\/)?$)" + + +class KernelHeaderChecker(HeaderChecker): + def __init__( + self, + header, + padding=1000, + ignored_files=None, + ignored_ext=None, + ignored_patterns=None, + py_ext=None, + asm_ext=None, + third_party_patterns=None, + copyright_regex = None + ): + super().__init__(header, padding, ignored_files, ignored_ext, ignored_patterns, + py_ext, asm_ext, third_party_patterns, copyright_regex) + + self.armCollabRegex = re.compile(FREERTOS_ARM_COLLAB_COPYRIGHT_REGEX) + + self.armCollabFilesPatternList = [] + for pattern in KERNEL_ARM_COLLAB_FILES_PATTERNS: + self.armCollabFilesPatternList.append(re.compile(pattern)) + + def isArmCollabFile(self, path): + for pattern in self.armCollabFilesPatternList: + if pattern.match(path): + return True + return False + + def checkArmCollabFile(self, path): + isValid = False + file_ext = os.path.splitext(path)[-1] + + with open(path, encoding="utf-8", errors="ignore") as file: + chunk = file.read(len("".join(self.header)) + self.padding) + lines = [("%s\n" % line) for line in chunk.strip().splitlines()][ + : len(self.header) + 2 + ] + if (len(lines) > 0) and (lines[0].find("#!") == 0): + lines.remove(lines[0]) + if (len(lines) > 0) and (len(lines[-1].strip()) == 0): + lines.remove(lines[-1]) + + # Split lines in sections. + headers = dict() + headers["text"] = [] + headers["copyright"] = [] + headers["spdx"] = [] + for line in lines: + if self.armCollabRegex.match(line): + headers["copyright"].append(line) + elif "SPDX-License-Identifier:" in line: + headers["spdx"].append(line) + else: + headers["text"].append(line) + + text_equal = self.isValidHeaderSection(file_ext, "text", headers["text"]) + spdx_equal = self.isValidHeaderSection(file_ext, "spdx", headers["spdx"]) + + if text_equal and spdx_equal: + # Some files do not have "open-source-office@arm.com" line. + if len(headers["copyright"]) == 3 or len(headers["copyright"]) == 2: + isValid = True + + return isValid + + def customCheck(self, path): + isValid = False + if self.isArmCollabFile(path): + isValid = self.checkArmCollabFile(path) + return isValid + + +def main(): + parser = HeaderChecker.configArgParser() + args = parser.parse_args() + + # Configure the checks then run + checker = KernelHeaderChecker(KERNEL_HEADER, + copyright_regex=FREERTOS_COPYRIGHT_REGEX, + ignored_files=KERNEL_IGNORED_FILES, + ignored_ext=KERNEL_IGNORED_EXTENSIONS, + ignored_patterns=KERNEL_IGNORED_PATTERNS, + third_party_patterns=KERNEL_THIRD_PARTY_PATTERNS, + py_ext=KERNEL_PY_EXTENSIONS, + asm_ext=KERNEL_ASM_EXTENSIONS) + checker.ignoreFile(os.path.split(__file__)[-1]) + + rc = checker.processArgs(args) + if rc: + checker.showHelp(__file__) + + return rc + +if __name__ == '__main__': + exit(main()) diff --git a/.github/scripts/manifest_updater.py b/.github/scripts/manifest_updater.py new file mode 100755 index 000000000..fc2343da3 --- /dev/null +++ b/.github/scripts/manifest_updater.py @@ -0,0 +1,32 @@ +#!/usr/bin/env python3 +import os +import argparse + +THIS_FILE_PATH = os.path.dirname(os.path.abspath(__file__)) +MANIFEST_FILE = os.path.join(THIS_FILE_PATH, '..', '..', 'manifest.yml') + +def update_manifest_file(new_version_number): + updated_lines = [] + with open(MANIFEST_FILE, 'r') as f: + for line in f: + line = line.strip() + if line.startswith('version'): + updated_lines.append(f'version: "V{new_version_number}"\n') + else: + updated_lines.append(f'{line}\n') + + with open(MANIFEST_FILE, 'w') as f: + f.writelines(updated_lines) + +def parse_args(): + parser = argparse.ArgumentParser() + parser.add_argument('-v', '--version', required=True, help='New version number.') + args = parser.parse_args() + return args + +def main(): + args = parse_args() + update_manifest_file(args.version) + +if __name__ == '__main__': + main() diff --git a/.github/third_party_tools.md b/.github/third_party_tools.md new file mode 100644 index 000000000..09bd6d62c --- /dev/null +++ b/.github/third_party_tools.md @@ -0,0 +1,14 @@ +Note that these tools are provided by different vendors and not by the FreeRTOS +team. + +## Tracing Tools +| Tool | Website | Getting Started | +|------|---------|-----------------| +| Tracelyzer | [Link](https://percepio.com/tracealyzer/freertostrace/) | [Link](https://percepio.com/getstarted/latest/html/freertos.html) | +| SystemView | [Link](https://www.segger.com/products/development-tools/systemview/) | [Link](https://wiki.segger.com/FreeRTOS_with_SystemView) | + +## Static Code Analysis Tools +| Tool | Website | Getting Started | +|------|---------|-----------------| +| Code Sonar | [Link](https://codesecure.com/our-products/codesonar/) | [Link](https://github.com/CodeSecure-SE/FreeRTOS-Kernel/blob/main/examples/codesonar/README.md) | +| Coverity | [Link](https://www.blackduck.com/static-analysis-tools-sast/coverity.html) | [Link](../examples/coverity/README.md) | diff --git a/.github/uncrustify.cfg b/.github/uncrustify.cfg new file mode 100644 index 000000000..3f4c40cab --- /dev/null +++ b/.github/uncrustify.cfg @@ -0,0 +1,673 @@ +# Uncrustify-0.69.0 + +newlines = auto # lf/crlf/cr/auto +input_tab_size = 4 # unsigned number +output_tab_size = 4 # unsigned number +string_escape_char = 92 # unsigned number +string_escape_char2 = 0 # unsigned number +string_replace_tab_chars = false # true/false +tok_split_gte = false # true/false +disable_processing_cmt = " *INDENT-OFF*" # string +enable_processing_cmt = " *INDENT-ON*" # string +enable_digraphs = false # true/false +utf8_bom = ignore # ignore/add/remove/force +utf8_byte = false # true/false +utf8_force = false # true/false +sp_arith = force # ignore/add/remove/force +sp_arith_additive = ignore # ignore/add/remove/force +sp_assign = force # ignore/add/remove/force +sp_cpp_lambda_assign = ignore # ignore/add/remove/force +sp_cpp_lambda_paren = ignore # ignore/add/remove/force +sp_assign_default = force # ignore/add/remove/force +sp_before_assign = force # ignore/add/remove/force +sp_after_assign = force # ignore/add/remove/force +sp_enum_paren = ignore # ignore/add/remove/force +sp_enum_assign = force # ignore/add/remove/force +sp_enum_before_assign = force # ignore/add/remove/force +sp_enum_after_assign = force # ignore/add/remove/force +sp_enum_colon = ignore # ignore/add/remove/force +sp_pp_concat = add # ignore/add/remove/force +sp_pp_stringify = add # ignore/add/remove/force +sp_before_pp_stringify = ignore # ignore/add/remove/force +sp_bool = force # ignore/add/remove/force +sp_compare = force # ignore/add/remove/force +sp_inside_paren = force # ignore/add/remove/force +sp_paren_paren = force # ignore/add/remove/force +sp_cparen_oparen = ignore # ignore/add/remove/force +sp_balance_nested_parens = false # true/false +sp_paren_brace = force # ignore/add/remove/force +sp_brace_brace = ignore # ignore/add/remove/force +sp_before_ptr_star = force # ignore/add/remove/force +sp_before_unnamed_ptr_star = force # ignore/add/remove/force +sp_between_ptr_star = remove # ignore/add/remove/force +sp_after_ptr_star = force # ignore/add/remove/force +sp_after_ptr_block_caret = ignore # ignore/add/remove/force +sp_after_ptr_star_qualifier = ignore # ignore/add/remove/force +sp_after_ptr_star_func = ignore # ignore/add/remove/force +sp_ptr_star_paren = ignore # ignore/add/remove/force +sp_before_ptr_star_func = ignore # ignore/add/remove/force +sp_before_byref = force # ignore/add/remove/force +sp_before_unnamed_byref = ignore # ignore/add/remove/force +sp_after_byref = remove # ignore/add/remove/force +sp_after_byref_func = remove # ignore/add/remove/force +sp_before_byref_func = ignore # ignore/add/remove/force +sp_after_type = force # ignore/add/remove/force +sp_after_decltype = ignore # ignore/add/remove/force +sp_before_template_paren = ignore # ignore/add/remove/force +sp_template_angle = ignore # ignore/add/remove/force +sp_before_angle = remove # ignore/add/remove/force +sp_inside_angle = remove # ignore/add/remove/force +sp_inside_angle_empty = ignore # ignore/add/remove/force +sp_angle_colon = ignore # ignore/add/remove/force +sp_after_angle = force # ignore/add/remove/force +sp_angle_paren = ignore # ignore/add/remove/force +sp_angle_paren_empty = ignore # ignore/add/remove/force +sp_angle_word = ignore # ignore/add/remove/force +sp_angle_shift = add # ignore/add/remove/force +sp_permit_cpp11_shift = false # true/false +sp_before_sparen = remove # ignore/add/remove/force +sp_inside_sparen = force # ignore/add/remove/force +sp_inside_sparen_open = ignore # ignore/add/remove/force +sp_inside_sparen_close = ignore # ignore/add/remove/force +sp_after_sparen = force # ignore/add/remove/force +sp_sparen_brace = force # ignore/add/remove/force +sp_invariant_paren = ignore # ignore/add/remove/force +sp_after_invariant_paren = ignore # ignore/add/remove/force +sp_special_semi = ignore # ignore/add/remove/force +sp_before_semi = remove # ignore/add/remove/force +sp_before_semi_for = remove # ignore/add/remove/force +sp_before_semi_for_empty = add # ignore/add/remove/force +sp_after_semi = add # ignore/add/remove/force +sp_after_semi_for = force # ignore/add/remove/force +sp_after_semi_for_empty = force # ignore/add/remove/force +sp_before_square = remove # ignore/add/remove/force +sp_before_squares = remove # ignore/add/remove/force +sp_cpp_before_struct_binding = ignore # ignore/add/remove/force +sp_inside_square = force # ignore/add/remove/force +sp_inside_square_oc_array = ignore # ignore/add/remove/force +sp_after_comma = force # ignore/add/remove/force +sp_before_comma = remove # ignore/add/remove/force +sp_after_mdatype_commas = ignore # ignore/add/remove/force +sp_before_mdatype_commas = ignore # ignore/add/remove/force +sp_between_mdatype_commas = ignore # ignore/add/remove/force +sp_paren_comma = force # ignore/add/remove/force +sp_before_ellipsis = ignore # ignore/add/remove/force +sp_type_ellipsis = ignore # ignore/add/remove/force +sp_type_question = ignore # ignore/add/remove/force +sp_paren_ellipsis = ignore # ignore/add/remove/force +sp_paren_qualifier = ignore # ignore/add/remove/force +sp_paren_noexcept = ignore # ignore/add/remove/force +sp_after_class_colon = ignore # ignore/add/remove/force +sp_before_class_colon = ignore # ignore/add/remove/force +sp_after_constr_colon = ignore # ignore/add/remove/force +sp_before_constr_colon = ignore # ignore/add/remove/force +sp_before_case_colon = remove # ignore/add/remove/force +sp_after_operator = ignore # ignore/add/remove/force +sp_after_operator_sym = ignore # ignore/add/remove/force +sp_after_operator_sym_empty = ignore # ignore/add/remove/force +sp_after_cast = force # ignore/add/remove/force +sp_inside_paren_cast = force # ignore/add/remove/force +sp_cpp_cast_paren = ignore # ignore/add/remove/force +sp_sizeof_paren = remove # ignore/add/remove/force +sp_sizeof_ellipsis = ignore # ignore/add/remove/force +sp_sizeof_ellipsis_paren = ignore # ignore/add/remove/force +sp_decltype_paren = ignore # ignore/add/remove/force +sp_after_tag = ignore # ignore/add/remove/force +sp_inside_braces_enum = force # ignore/add/remove/force +sp_inside_braces_struct = force # ignore/add/remove/force +sp_inside_braces_oc_dict = ignore # ignore/add/remove/force +sp_after_type_brace_init_lst_open = ignore # ignore/add/remove/force +sp_before_type_brace_init_lst_close = ignore # ignore/add/remove/force +sp_inside_type_brace_init_lst = ignore # ignore/add/remove/force +sp_inside_braces = force # ignore/add/remove/force +sp_inside_braces_empty = remove # ignore/add/remove/force +sp_type_func = force # ignore/add/remove/force +sp_type_brace_init_lst = ignore # ignore/add/remove/force +sp_func_proto_paren = remove # ignore/add/remove/force +sp_func_proto_paren_empty = ignore # ignore/add/remove/force +sp_func_def_paren = remove # ignore/add/remove/force +sp_func_def_paren_empty = ignore # ignore/add/remove/force +sp_inside_fparens = remove # ignore/add/remove/force +sp_inside_fparen = force # ignore/add/remove/force +sp_inside_tparen = ignore # ignore/add/remove/force +sp_after_tparen_close = ignore # ignore/add/remove/force +sp_square_fparen = ignore # ignore/add/remove/force +sp_fparen_brace = add # ignore/add/remove/force +sp_fparen_brace_initializer = ignore # ignore/add/remove/force +sp_fparen_dbrace = ignore # ignore/add/remove/force +sp_func_call_paren = remove # ignore/add/remove/force +sp_func_call_paren_empty = ignore # ignore/add/remove/force +sp_func_call_user_paren = ignore # ignore/add/remove/force +sp_func_call_user_inside_fparen = ignore # ignore/add/remove/force +sp_func_call_user_paren_paren = ignore # ignore/add/remove/force +sp_func_class_paren = remove # ignore/add/remove/force +sp_func_class_paren_empty = ignore # ignore/add/remove/force +sp_return_paren = remove # ignore/add/remove/force +sp_return_brace = ignore # ignore/add/remove/force +sp_attribute_paren = remove # ignore/add/remove/force +sp_defined_paren = remove # ignore/add/remove/force +sp_throw_paren = ignore # ignore/add/remove/force +sp_after_throw = ignore # ignore/add/remove/force +sp_catch_paren = ignore # ignore/add/remove/force +sp_oc_catch_paren = ignore # ignore/add/remove/force +sp_oc_classname_paren = ignore # ignore/add/remove/force +sp_version_paren = ignore # ignore/add/remove/force +sp_scope_paren = ignore # ignore/add/remove/force +sp_super_paren = remove # ignore/add/remove/force +sp_this_paren = remove # ignore/add/remove/force +sp_macro = force # ignore/add/remove/force +sp_macro_func = force # ignore/add/remove/force +sp_else_brace = ignore # ignore/add/remove/force +sp_brace_else = ignore # ignore/add/remove/force +sp_brace_typedef = force # ignore/add/remove/force +sp_catch_brace = ignore # ignore/add/remove/force +sp_oc_catch_brace = ignore # ignore/add/remove/force +sp_brace_catch = ignore # ignore/add/remove/force +sp_oc_brace_catch = ignore # ignore/add/remove/force +sp_finally_brace = ignore # ignore/add/remove/force +sp_brace_finally = ignore # ignore/add/remove/force +sp_try_brace = ignore # ignore/add/remove/force +sp_getset_brace = ignore # ignore/add/remove/force +sp_word_brace = add # ignore/add/remove/force +sp_word_brace_ns = add # ignore/add/remove/force +sp_before_dc = remove # ignore/add/remove/force +sp_after_dc = remove # ignore/add/remove/force +sp_d_array_colon = ignore # ignore/add/remove/force +sp_not = remove # ignore/add/remove/force +sp_inv = remove # ignore/add/remove/force +sp_addr = remove # ignore/add/remove/force +sp_member = remove # ignore/add/remove/force +sp_deref = remove # ignore/add/remove/force +sp_sign = remove # ignore/add/remove/force +sp_incdec = remove # ignore/add/remove/force +sp_before_nl_cont = add # ignore/add/remove/force +sp_after_oc_scope = ignore # ignore/add/remove/force +sp_after_oc_colon = ignore # ignore/add/remove/force +sp_before_oc_colon = ignore # ignore/add/remove/force +sp_after_oc_dict_colon = ignore # ignore/add/remove/force +sp_before_oc_dict_colon = ignore # ignore/add/remove/force +sp_after_send_oc_colon = ignore # ignore/add/remove/force +sp_before_send_oc_colon = ignore # ignore/add/remove/force +sp_after_oc_type = ignore # ignore/add/remove/force +sp_after_oc_return_type = ignore # ignore/add/remove/force +sp_after_oc_at_sel = ignore # ignore/add/remove/force +sp_after_oc_at_sel_parens = ignore # ignore/add/remove/force +sp_inside_oc_at_sel_parens = ignore # ignore/add/remove/force +sp_before_oc_block_caret = ignore # ignore/add/remove/force +sp_after_oc_block_caret = ignore # ignore/add/remove/force +sp_after_oc_msg_receiver = ignore # ignore/add/remove/force +sp_after_oc_property = ignore # ignore/add/remove/force +sp_after_oc_synchronized = ignore # ignore/add/remove/force +sp_cond_colon = force # ignore/add/remove/force +sp_cond_colon_before = ignore # ignore/add/remove/force +sp_cond_colon_after = ignore # ignore/add/remove/force +sp_cond_question = force # ignore/add/remove/force +sp_cond_question_before = ignore # ignore/add/remove/force +sp_cond_question_after = ignore # ignore/add/remove/force +sp_cond_ternary_short = ignore # ignore/add/remove/force +sp_case_label = force # ignore/add/remove/force +sp_range = ignore # ignore/add/remove/force +sp_after_for_colon = ignore # ignore/add/remove/force +sp_before_for_colon = ignore # ignore/add/remove/force +sp_extern_paren = ignore # ignore/add/remove/force +sp_cmt_cpp_start = ignore # ignore/add/remove/force +sp_cmt_cpp_doxygen = false # true/false +sp_cmt_cpp_qttr = false # true/false +sp_endif_cmt = force # ignore/add/remove/force +sp_after_new = ignore # ignore/add/remove/force +sp_between_new_paren = ignore # ignore/add/remove/force +sp_after_newop_paren = ignore # ignore/add/remove/force +sp_inside_newop_paren = ignore # ignore/add/remove/force +sp_inside_newop_paren_open = ignore # ignore/add/remove/force +sp_inside_newop_paren_close = ignore # ignore/add/remove/force +sp_before_tr_emb_cmt = force # ignore/add/remove/force +sp_num_before_tr_emb_cmt = 1 # unsigned number +sp_annotation_paren = ignore # ignore/add/remove/force +sp_skip_vbrace_tokens = false # true/false +sp_after_noexcept = ignore # ignore/add/remove/force +sp_vala_after_translation = ignore # ignore/add/remove/force +force_tab_after_define = false # true/false +indent_columns = 4 # unsigned number +indent_continue = 0 # number +indent_continue_class_head = 0 # unsigned number +indent_single_newlines = false # true/false +indent_param = 0 # unsigned number +indent_with_tabs = 0 # unsigned number +indent_cmt_with_tabs = false # true/false +indent_align_string = true # true/false +indent_xml_string = 0 # unsigned number +indent_brace = 0 # unsigned number +indent_braces = false # true/false +indent_braces_no_func = false # true/false +indent_braces_no_class = false # true/false +indent_braces_no_struct = false # true/false +indent_brace_parent = false # true/false +indent_paren_open_brace = false # true/false +indent_cs_delegate_brace = false # true/false +indent_cs_delegate_body = false # true/false +indent_namespace = false # true/false +indent_namespace_single_indent = false # true/false +indent_namespace_level = 0 # unsigned number +indent_namespace_limit = 0 # unsigned number +indent_extern = false # true/false +indent_class = true # true/false +indent_class_colon = true # true/false +indent_class_on_colon = false # true/false +indent_constr_colon = false # true/false +indent_ctor_init_leading = 2 # unsigned number +indent_ctor_init = 0 # number +indent_else_if = false # true/false +indent_var_def_blk = 0 # number +indent_var_def_cont = false # true/false +indent_shift = false # true/false +indent_func_def_force_col1 = false # true/false +indent_func_call_param = false # true/false +indent_func_def_param = false # true/false +indent_func_proto_param = false # true/false +indent_func_class_param = false # true/false +indent_func_ctor_var_param = false # true/false +indent_template_param = false # true/false +indent_func_param_double = false # true/false +indent_func_const = 0 # unsigned number +indent_func_throw = 0 # unsigned number +indent_member = 3 # unsigned number +indent_member_single = false # true/false +indent_sing_line_comments = 0 # unsigned number +indent_relative_single_line_comments = false # true/false +indent_switch_case = 4 # unsigned number +indent_switch_pp = true # true/false +indent_case_shift = 0 # unsigned number +indent_case_brace = 3 # number +indent_col1_comment = false # true/false +indent_col1_multi_string_literal = false # true/false +indent_label = 1 # number +indent_access_spec = 1 # number +indent_access_spec_body = false # true/false +indent_paren_nl = false # true/false +indent_paren_close = 0 # unsigned number +indent_paren_after_func_def = false # true/false +indent_paren_after_func_decl = false # true/false +indent_paren_after_func_call = false # true/false +indent_comma_paren = false # true/false +indent_bool_paren = false # true/false +indent_semicolon_for_paren = false # true/false +indent_first_bool_expr = false # true/false +indent_first_for_expr = false # true/false +indent_square_nl = false # true/false +indent_preserve_sql = false # true/false +indent_align_assign = true # true/false +indent_align_paren = true # true/false +indent_oc_block = false # true/false +indent_oc_block_msg = 0 # unsigned number +indent_oc_msg_colon = 0 # unsigned number +indent_oc_msg_prioritize_first_colon = true # true/false +indent_oc_block_msg_xcode_style = false # true/false +indent_oc_block_msg_from_keyword = false # true/false +indent_oc_block_msg_from_colon = false # true/false +indent_oc_block_msg_from_caret = false # true/false +indent_oc_block_msg_from_brace = false # true/false +indent_min_vbrace_open = 0 # unsigned number +indent_vbrace_open_on_tabstop = false # true/false +indent_token_after_brace = true # true/false +indent_cpp_lambda_body = false # true/false +indent_using_block = true # true/false +indent_ternary_operator = 0 # unsigned number +indent_off_after_return_new = false # true/false +indent_single_after_return = false # true/false +indent_ignore_asm_block = false # true/false +nl_collapse_empty_body = false # true/false +nl_assign_leave_one_liners = true # true/false +nl_class_leave_one_liners = true # true/false +nl_enum_leave_one_liners = false # true/false +nl_getset_leave_one_liners = false # true/false +nl_cs_property_leave_one_liners = false # true/false +nl_func_leave_one_liners = false # true/false +nl_cpp_lambda_leave_one_liners = false # true/false +nl_if_leave_one_liners = false # true/false +nl_while_leave_one_liners = false # true/false +nl_for_leave_one_liners = false # true/false +nl_oc_msg_leave_one_liner = false # true/false +nl_oc_mdef_brace = ignore # ignore/add/remove/force +nl_oc_block_brace = ignore # ignore/add/remove/force +nl_oc_interface_brace = ignore # ignore/add/remove/force +nl_oc_implementation_brace = ignore # ignore/add/remove/force +nl_start_of_file = remove # ignore/add/remove/force +nl_start_of_file_min = 0 # unsigned number +nl_end_of_file = force # ignore/add/remove/force +nl_end_of_file_min = 1 # unsigned number +nl_assign_brace = add # ignore/add/remove/force +nl_assign_square = ignore # ignore/add/remove/force +nl_tsquare_brace = ignore # ignore/add/remove/force +nl_after_square_assign = ignore # ignore/add/remove/force +nl_fcall_brace = add # ignore/add/remove/force +nl_enum_brace = force # ignore/add/remove/force +nl_enum_class = ignore # ignore/add/remove/force +nl_enum_class_identifier = ignore # ignore/add/remove/force +nl_enum_identifier_colon = ignore # ignore/add/remove/force +nl_enum_colon_type = ignore # ignore/add/remove/force +nl_struct_brace = force # ignore/add/remove/force +nl_union_brace = force # ignore/add/remove/force +nl_if_brace = add # ignore/add/remove/force +nl_brace_else = add # ignore/add/remove/force +nl_elseif_brace = ignore # ignore/add/remove/force +nl_else_brace = add # ignore/add/remove/force +nl_else_if = ignore # ignore/add/remove/force +nl_before_if_closing_paren = ignore # ignore/add/remove/force +nl_brace_finally = ignore # ignore/add/remove/force +nl_finally_brace = ignore # ignore/add/remove/force +nl_try_brace = ignore # ignore/add/remove/force +nl_getset_brace = force # ignore/add/remove/force +nl_for_brace = add # ignore/add/remove/force +nl_catch_brace = ignore # ignore/add/remove/force +nl_oc_catch_brace = ignore # ignore/add/remove/force +nl_brace_catch = ignore # ignore/add/remove/force +nl_oc_brace_catch = ignore # ignore/add/remove/force +nl_brace_square = ignore # ignore/add/remove/force +nl_brace_fparen = ignore # ignore/add/remove/force +nl_while_brace = add # ignore/add/remove/force +nl_scope_brace = ignore # ignore/add/remove/force +nl_unittest_brace = ignore # ignore/add/remove/force +nl_version_brace = ignore # ignore/add/remove/force +nl_using_brace = ignore # ignore/add/remove/force +nl_brace_brace = ignore # ignore/add/remove/force +nl_do_brace = add # ignore/add/remove/force +nl_brace_while = ignore # ignore/add/remove/force +nl_switch_brace = add # ignore/add/remove/force +nl_synchronized_brace = ignore # ignore/add/remove/force +nl_multi_line_cond = false # true/false +nl_multi_line_define = true # true/false +nl_before_case = true # true/false +nl_after_case = true # true/false +nl_case_colon_brace = ignore # ignore/add/remove/force +nl_before_throw = ignore # ignore/add/remove/force +nl_namespace_brace = ignore # ignore/add/remove/force +nl_template_class = ignore # ignore/add/remove/force +nl_class_brace = ignore # ignore/add/remove/force +nl_class_init_args = ignore # ignore/add/remove/force +nl_constr_init_args = ignore # ignore/add/remove/force +nl_enum_own_lines = ignore # ignore/add/remove/force +nl_func_type_name = remove # ignore/add/remove/force +nl_func_type_name_class = ignore # ignore/add/remove/force +nl_func_class_scope = ignore # ignore/add/remove/force +nl_func_scope_name = ignore # ignore/add/remove/force +nl_func_proto_type_name = remove # ignore/add/remove/force +nl_func_paren = remove # ignore/add/remove/force +nl_func_paren_empty = ignore # ignore/add/remove/force +nl_func_def_paren = remove # ignore/add/remove/force +nl_func_def_paren_empty = ignore # ignore/add/remove/force +nl_func_call_paren = ignore # ignore/add/remove/force +nl_func_call_paren_empty = ignore # ignore/add/remove/force +nl_func_decl_start = remove # ignore/add/remove/force +nl_func_def_start = remove # ignore/add/remove/force +nl_func_decl_start_single = ignore # ignore/add/remove/force +nl_func_def_start_single = ignore # ignore/add/remove/force +nl_func_decl_start_multi_line = false # true/false +nl_func_def_start_multi_line = false # true/false +nl_func_decl_args = add # ignore/add/remove/force +nl_func_def_args = add # ignore/add/remove/force +nl_func_decl_args_multi_line = false # true/false +nl_func_def_args_multi_line = false # true/false +nl_func_decl_end = remove # ignore/add/remove/force +nl_func_def_end = remove # ignore/add/remove/force +nl_func_decl_end_single = ignore # ignore/add/remove/force +nl_func_def_end_single = ignore # ignore/add/remove/force +nl_func_decl_end_multi_line = false # true/false +nl_func_def_end_multi_line = false # true/false +nl_func_decl_empty = ignore # ignore/add/remove/force +nl_func_def_empty = ignore # ignore/add/remove/force +nl_func_call_empty = ignore # ignore/add/remove/force +nl_func_call_start = ignore # ignore/add/remove/force +nl_func_call_start_multi_line = false # true/false +nl_func_call_args_multi_line = false # true/false +nl_func_call_end_multi_line = false # true/false +nl_oc_msg_args = false # true/false +nl_fdef_brace = add # ignore/add/remove/force +nl_fdef_brace_cond = ignore # ignore/add/remove/force +nl_cpp_ldef_brace = ignore # ignore/add/remove/force +nl_return_expr = ignore # ignore/add/remove/force +nl_after_semicolon = true # true/false +nl_paren_dbrace_open = ignore # ignore/add/remove/force +nl_type_brace_init_lst = ignore # ignore/add/remove/force +nl_type_brace_init_lst_open = ignore # ignore/add/remove/force +nl_type_brace_init_lst_close = ignore # ignore/add/remove/force +nl_after_brace_open = true # true/false +nl_after_brace_open_cmt = false # true/false +nl_after_vbrace_open = false # true/false +nl_after_vbrace_open_empty = false # true/false +nl_after_brace_close = true # true/false +nl_after_vbrace_close = false # true/false +nl_brace_struct_var = ignore # ignore/add/remove/force +nl_define_macro = false # true/false +nl_squeeze_paren_close = false # true/false +nl_squeeze_ifdef = true # true/false +nl_squeeze_ifdef_top_level = false # true/false +nl_before_if = force # ignore/add/remove/force +nl_after_if = force # ignore/add/remove/force +nl_before_for = force # ignore/add/remove/force +nl_after_for = force # ignore/add/remove/force +nl_before_while = force # ignore/add/remove/force +nl_after_while = force # ignore/add/remove/force +nl_before_switch = force # ignore/add/remove/force +nl_after_switch = force # ignore/add/remove/force +nl_before_synchronized = ignore # ignore/add/remove/force +nl_after_synchronized = ignore # ignore/add/remove/force +nl_before_do = force # ignore/add/remove/force +nl_after_do = force # ignore/add/remove/force +nl_before_return = false # true/false +nl_after_return = true # true/false +nl_ds_struct_enum_cmt = false # true/false +nl_ds_struct_enum_close_brace = false # true/false +nl_class_colon = ignore # ignore/add/remove/force +nl_constr_colon = ignore # ignore/add/remove/force +nl_namespace_two_to_one_liner = false # true/false +nl_create_if_one_liner = false # true/false +nl_create_for_one_liner = false # true/false +nl_create_while_one_liner = false # true/false +nl_create_func_def_one_liner = false # true/false +nl_split_if_one_liner = false # true/false +nl_split_for_one_liner = false # true/false +nl_split_while_one_liner = false # true/false +nl_max = 4 # unsigned number +nl_max_blank_in_func = 0 # unsigned number +nl_before_func_body_proto = 0 # unsigned number +nl_before_func_body_def = 0 # unsigned number +nl_before_func_class_proto = 0 # unsigned number +nl_before_func_class_def = 0 # unsigned number +nl_after_func_proto = 0 # unsigned number +nl_after_func_proto_group = 1 # unsigned number +nl_after_func_class_proto = 0 # unsigned number +nl_after_func_class_proto_group = 0 # unsigned number +nl_class_leave_one_liner_groups = false # true/false +nl_after_func_body = 0 # unsigned number +nl_after_func_body_class = 2 # unsigned number +nl_after_func_body_one_liner = 0 # unsigned number +nl_func_var_def_blk = 1 # unsigned number +nl_typedef_blk_start = 0 # unsigned number +nl_typedef_blk_end = 0 # unsigned number +nl_typedef_blk_in = 0 # unsigned number +nl_var_def_blk_start = 0 # unsigned number +nl_var_def_blk_end = 0 # unsigned number +nl_var_def_blk_in = 0 # unsigned number +nl_before_block_comment = 2 # unsigned number +nl_before_c_comment = 0 # unsigned number +nl_before_cpp_comment = 0 # unsigned number +nl_after_multiline_comment = false # true/false +nl_after_label_colon = false # true/false +nl_after_struct = 0 # unsigned number +nl_before_class = 0 # unsigned number +nl_after_class = 0 # unsigned number +nl_before_access_spec = 0 # unsigned number +nl_after_access_spec = 0 # unsigned number +nl_comment_func_def = 0 # unsigned number +nl_after_try_catch_finally = 0 # unsigned number +nl_around_cs_property = 0 # unsigned number +nl_between_get_set = 0 # unsigned number +nl_property_brace = ignore # ignore/add/remove/force +nl_inside_namespace = 0 # unsigned number +eat_blanks_after_open_brace = true # true/false +eat_blanks_before_close_brace = true # true/false +nl_remove_extra_newlines = 0 # unsigned number +nl_after_annotation = ignore # ignore/add/remove/force +nl_between_annotation = ignore # ignore/add/remove/force +pos_arith = ignore # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force +pos_assign = ignore # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force +pos_bool = trail # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force +pos_compare = ignore # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force +pos_conditional = ignore # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force +pos_comma = ignore # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force +pos_enum_comma = ignore # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force +pos_class_comma = ignore # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force +pos_constr_comma = ignore # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force +pos_class_colon = ignore # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force +pos_constr_colon = ignore # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force +code_width = 0 # unsigned number +ls_for_split_full = false # true/false +ls_func_split_full = false # true/false +ls_code_width = false # true/false +align_keep_tabs = false # true/false +align_with_tabs = false # true/false +align_on_tabstop = false # true/false +align_number_right = false # true/false +align_keep_extra_space = false # true/false +align_func_params = false # true/false +align_func_params_span = 0 # unsigned number +align_func_params_thresh = 0 # number +align_func_params_gap = 0 # unsigned number +align_constr_value_span = 0 # unsigned number +align_constr_value_thresh = 0 # number +align_constr_value_gap = 0 # unsigned number +align_same_func_call_params = false # true/false +align_same_func_call_params_span = 0 # unsigned number +align_same_func_call_params_thresh = 0 # number +align_var_def_span = 0 # unsigned number +align_var_def_star_style = 0 # unsigned number +align_var_def_amp_style = 1 # unsigned number +align_var_def_thresh = 16 # number +align_var_def_gap = 0 # unsigned number +align_var_def_colon = false # true/false +align_var_def_colon_gap = 0 # unsigned number +align_var_def_attribute = false # true/false +align_var_def_inline = false # true/false +align_assign_span = 0 # unsigned number +align_assign_func_proto_span = 0 # unsigned number +align_assign_thresh = 12 # number +align_assign_decl_func = 0 # unsigned number +align_enum_equ_span = 0 # unsigned number +align_enum_equ_thresh = 0 # number +align_var_class_span = 0 # unsigned number +align_var_class_thresh = 0 # number +align_var_class_gap = 0 # unsigned number +align_var_struct_span = 0 # unsigned number +align_var_struct_thresh = 0 # number +align_var_struct_gap = 0 # unsigned number +align_struct_init_span = 3 # unsigned number +align_typedef_span = 5 # unsigned number +align_typedef_gap = 3 # unsigned number +align_typedef_func = 0 # unsigned number +align_typedef_star_style = 1 # unsigned number +align_typedef_amp_style = 1 # unsigned number +align_right_cmt_span = 3 # unsigned number +align_right_cmt_gap = 0 # unsigned number +align_right_cmt_mix = false # true/false +align_right_cmt_same_level = false # true/false +align_right_cmt_at_col = 0 # unsigned number +align_func_proto_span = 0 # unsigned number +align_func_proto_thresh = 0 # number +align_func_proto_gap = 0 # unsigned number +align_on_operator = false # true/false +align_mix_var_proto = false # true/false +align_single_line_func = false # true/false +align_single_line_brace = false # true/false +align_single_line_brace_gap = 0 # unsigned number +align_oc_msg_spec_span = 0 # unsigned number +align_nl_cont = true # true/false +align_pp_define_together = false # true/false +align_pp_define_span = 3 # unsigned number +align_pp_define_gap = 4 # unsigned number +align_left_shift = true # true/false +align_asm_colon = false # true/false +align_oc_msg_colon_span = 0 # unsigned number +align_oc_msg_colon_first = false # true/false +align_oc_decl_colon = false # true/false +cmt_width = 0 # unsigned number +cmt_reflow_mode = 0 # unsigned number +cmt_convert_tab_to_spaces = false # true/false +cmt_indent_multi = true # true/false +cmt_c_group = false # true/false +cmt_c_nl_start = false # true/false +cmt_c_nl_end = false # true/false +cmt_cpp_to_c = true # true/false +cmt_cpp_group = false # true/false +cmt_cpp_nl_start = false # true/false +cmt_cpp_nl_end = false # true/false +cmt_star_cont = true # true/false +cmt_sp_before_star_cont = 0 # unsigned number +cmt_sp_after_star_cont = 0 # unsigned number +cmt_multi_check_last = true # true/false +cmt_multi_first_len_minimum = 4 # unsigned number +cmt_insert_file_header = "" # string +cmt_insert_file_footer = "" # string +cmt_insert_func_header = "" # string +cmt_insert_class_header = "" # string +cmt_insert_oc_msg_header = "" # string +cmt_insert_before_preproc = false # true/false +cmt_insert_before_inlines = true # true/false +cmt_insert_before_ctor_dtor = false # true/false +mod_full_brace_do = add # ignore/add/remove/force +mod_full_brace_for = add # ignore/add/remove/force +mod_full_brace_function = ignore # ignore/add/remove/force +mod_full_brace_if = add # ignore/add/remove/force +mod_full_brace_if_chain = false # true/false +mod_full_brace_if_chain_only = false # true/false +mod_full_brace_while = add # ignore/add/remove/force +mod_full_brace_using = ignore # ignore/add/remove/force +mod_full_brace_nl = 0 # unsigned number +mod_full_brace_nl_block_rem_mlcond = false # true/false +mod_paren_on_return = ignore # ignore/add/remove/force +mod_pawn_semicolon = false # true/false +mod_full_paren_if_bool = true # true/false +mod_remove_extra_semicolon = true # true/false +mod_add_long_function_closebrace_comment = 0 # unsigned number +mod_add_long_namespace_closebrace_comment = 0 # unsigned number +mod_add_long_class_closebrace_comment = 0 # unsigned number +mod_add_long_switch_closebrace_comment = 0 # unsigned number +mod_add_long_ifdef_endif_comment = 10 # unsigned number +mod_add_long_ifdef_else_comment = 10 # unsigned number +mod_sort_import = false # true/false +mod_sort_using = false # true/false +mod_sort_include = false # true/false +mod_move_case_break = false # true/false +mod_case_brace = remove # ignore/add/remove/force +mod_remove_empty_return = true # true/false +mod_enum_last_comma = ignore # ignore/add/remove/force +mod_sort_oc_properties = false # true/false +mod_sort_oc_property_class_weight = 0 # number +mod_sort_oc_property_thread_safe_weight = 0 # number +mod_sort_oc_property_readwrite_weight = 0 # number +mod_sort_oc_property_reference_weight = 0 # number +mod_sort_oc_property_getter_weight = 0 # number +mod_sort_oc_property_setter_weight = 0 # number +mod_sort_oc_property_nullability_weight = 0 # number +pp_indent = force # ignore/add/remove/force +pp_indent_at_level = true # true/false +pp_indent_count = 4 # unsigned number +pp_space = remove # ignore/add/remove/force +pp_space_count = 0 # unsigned number +pp_indent_region = 0 # number +pp_region_indent_code = false # true/false +pp_indent_if = 0 # number +pp_if_indent_code = true # true/false +pp_define_at_level = false # true/false +pp_ignore_define_body = false # true/false +pp_indent_case = true # true/false +pp_indent_func_def = true # true/false +pp_indent_extern = true # true/false +pp_indent_brace = false # true/false +include_category_0 = "" # string +include_category_1 = "" # string +include_category_2 = "" # string +use_indent_func_call_param = true # true/false +use_indent_continue_only_once = false # true/false +indent_cpp_lambda_only_once = false # true/false +use_options_overriding_for_qt_macros = true # true/false +warn_level_tabs_found_in_verbatim_string_literals = 2 # unsigned number diff --git a/.github/workflows/auto-release.yml b/.github/workflows/auto-release.yml new file mode 100644 index 000000000..2cd6fde6e --- /dev/null +++ b/.github/workflows/auto-release.yml @@ -0,0 +1,136 @@ +name: Kernel-Auto-Release + +on: + workflow_dispatch: + inputs: + commit_id: + description: 'Commit ID' + required: true + default: 'HEAD' + version_number: + description: 'Version Number (Ex. 10.4.4)' + required: true + default: '10.4.4' + main_br_version: + description: "Version String for task.h on main branch (leave empty to leave as-is)." + required: false + default: '' + +jobs: + release-packager: + permissions: + id-token: write + name: Release Packager + runs-on: ubuntu-latest + steps: + # Install python 3 + - name: Tool Setup + uses: actions/setup-python@v2 + with: + architecture: x64 + env: + GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} + + # Currently FreeRTOS/.github/scripts houses the release script. Download it for upcoming usage + - name: Checkout FreeRTOS Release Tools + uses: actions/checkout@v4.1.1 + with: + repository: FreeRTOS/FreeRTOS + path: tools + + # Simpler git auth if we use checkout action and forward the repo to release script + - name: Checkout FreeRTOS Kernel + uses: actions/checkout@v4.1.1 + with: + path: local_kernel + fetch-depth: 0 + + - name: Configure git identity + env: + ACTOR: ${{ github.actor }} + run: | + git config --global user.name "$ACTOR" + git config --global user.email "$ACTOR"@users.noreply.github.com + + - name: create a new branch that references commit id + env: + VERSION_NUMBER: ${{ github.event.inputs.version_number }} + COMMIT_ID: ${{ github.event.inputs.commit_id }} + working-directory: ./local_kernel + run: | + git checkout -b "$VERSION_NUMBER" "$COMMIT_ID" + echo "COMMIT_SHA_1=$(git rev-parse HEAD)" >> $GITHUB_ENV + + - name: Update source files with version info + env: + VERSION_NUMBER: ${{ github.event.inputs.version_number }} + MAIN_BR_VERSION_NUMBER: ${{ github.event.inputs.main_br_version }} + COMMIT_SHA_1: ${{ env.COMMIT_SHA_1 }} + GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} + run: | + # Install deps and run + pip install -r ./tools/.github/scripts/release-requirements.txt + ./tools/.github/scripts/update_src_version.py FreeRTOS --kernel-repo-path=local_kernel --kernel-commit="$COMMIT_SHA_1" --new-kernel-version="$VERSION_NUMBER" --new-kernel-main-br-version="$MAIN_BR_VERSION_NUMBER" + exit $? + + - name : Update version number in manifest.yml + env: + VERSION_NUMBER: ${{ github.event.inputs.version_number }} + working-directory: ./local_kernel + run: | + ./.github/scripts/manifest_updater.py -v "$VERSION_NUMBER" + exit $? + + - name : Commit version number change in manifest.yml + env: + VERSION_NUMBER: ${{ github.event.inputs.version_number }} + working-directory: ./local_kernel + run: | + git add . + git commit -m '[AUTO][RELEASE]: Update version number in manifest.yml' + git push -u origin "$VERSION_NUMBER" + + - name: Generate SBOM + uses: FreeRTOS/CI-CD-Github-Actions/sbom-generator@main + with: + repo_path: ./local_kernel + source_path: ./ + + - name: commit SBOM file + env: + VERSION_NUMBER: ${{ github.event.inputs.version_number }} + working-directory: ./local_kernel + run: | + git add . + git commit -m '[AUTO][RELEASE]: Update SBOM' + git push -u origin "$VERSION_NUMBER" + echo "COMMIT_SHA_2=$(git rev-parse HEAD)" >> $GITHUB_ENV + + - name: Release + env: + VERSION_NUMBER: ${{ github.event.inputs.version_number }} + MAIN_BR_VERSION_NUMBER: ${{ github.event.inputs.main_br_version }} + COMMIT_SHA_2: ${{ env.COMMIT_SHA_2 }} + REPO_OWNER: ${{ github.repository_owner }} + GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} + run: | + # Install deps and run + pip install -r ./tools/.github/scripts/release-requirements.txt + ./tools/.github/scripts/release.py "$REPO_OWNER" --kernel-repo-path=local_kernel --kernel-commit="$COMMIT_SHA_2" --new-kernel-version="$VERSION_NUMBER" --new-kernel-main-br-version="$MAIN_BR_VERSION_NUMBER" + exit $? + + - name: Backup Release Asset + uses: FreeRTOS/CI-CD-Github-Actions/artifact-backup@main + with: + # This is dependent on the release script putting this zip file + # in this exact location. + artifact_path: ./FreeRTOS-KernelV${{ github.event.inputs.version_number }}.zip + release_tag: ${{ github.event.inputs.version_number }} + + - name: Cleanup + env: + VERSION_NUMBER: ${{ github.event.inputs.version_number }} + working-directory: ./local_kernel + run: | + # Delete the branch created for Tag by SBOM generator + git push -u origin --delete "$VERSION_NUMBER" diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml new file mode 100644 index 000000000..2765466be --- /dev/null +++ b/.github/workflows/ci.yml @@ -0,0 +1,51 @@ +name: CI Checks +on: + push: + branches: ["**"] + pull_request: + branches: [main] + workflow_dispatch: +jobs: + formatting: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4.1.1 + - name: Check Formatting of FreeRTOS-Kernel Files + uses: FreeRTOS/CI-CD-Github-Actions/formatting@main + with: + exclude-dirs: portable + + spell-check: + runs-on: ubuntu-latest + steps: + - name: Clone This Repo + uses: actions/checkout@v4.1.1 + - name: Run spellings check + uses: FreeRTOS/CI-CD-Github-Actions/spellings@main + with: + path: ./ + exclude-files: History.txt + + link-verifier: + runs-on: ubuntu-latest + steps: + - name: Clone This Repo + uses: actions/checkout@v4.1.1 + - name: Link Verification + uses: FreeRTOS/CI-CD-Github-Actions/link-verifier@main + with: + allowlist-file: '.github/allowed_urls.txt' + + verify-manifest: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4.1.1 + with: + submodules: true + fetch-depth: 0 + + - name: Run manifest verifier + uses: FreeRTOS/CI-CD-GitHub-Actions/manifest-verifier@main + with: + path: ./ + fail-on-incorrect-version: true diff --git a/.github/workflows/coverity_scan.yml b/.github/workflows/coverity_scan.yml new file mode 100644 index 000000000..0afc8e2e1 --- /dev/null +++ b/.github/workflows/coverity_scan.yml @@ -0,0 +1,138 @@ +name: Coverity Scan +on: + # Run on every commit to mainline + push: + branches: main + # Allow manual running of the scan + workflow_dispatch: + +env: + bashPass: \033[32;1mPASSED - + bashInfo: \033[33;1mINFO - + bashFail: \033[31;1mFAILED - + bashEnd: \033[0m + +jobs: + Coverity-Scan: + if: ( github.repository == 'FreeRTOS/FreeRTOS-Kernel' ) + name: Coverity Scan + runs-on: ubuntu-latest + steps: + - name: Checkout the Repository + uses: actions/checkout@v4.1.1 + + - env: + stepName: Install Build Essentials + shell: bash + run: | + # ${{ env.stepName }} + echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}" + + sudo apt-get -y update + sudo apt-get -y install build-essential + + echo "::endgroup::" + echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }}" + + - env: + stepName: Install Coverity Build + COVERITY_TOKEN: ${{ secrets.COVERITY_SCAN_TOKEN }} + shell: bash + run: | + # ${{ env.stepName }} + echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}" + + wget -nv -q -O "$HOME/cov-analysis.tar.gz" https://scan.coverity.com/download/linux64 --post-data="token=${COVERITY_TOKEN}&project=FreeRTOS-Kernel" + + EXPECTED_MD5="e4418004b073140d67390cffba79c3b2" + GENERATED_MD5=$(md5sum "$HOME/cov-analysis.tar.gz" | awk '{print $1}') + + if [ "$GENERATED_MD5" = "$EXPECTED_MD5" ]; then + tar -zxf "$HOME/cov-analysis.tar.gz" --one-top-level=cov_scan -C "$HOME" + echo "cov_scan_path=$HOME/cov_scan/bin" >> $GITHUB_ENV + sudo rm -f "$HOME/cov-analysis.tar.gz" + echo "::endgroup::" + echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }} " + else + echo -e "${{ env.bashFail }} MD5 checksum verification failed for cov-analysis.tar.gz ${{ env.bashEnd }}" + echo -e "${{ env.bashFail }} ${{ env.stepName }} ${{ env.bashEnd }}" + exit -1 + fi + + - env: + stepName: Coverity Build + COVERITY_TOKEN: ${{ secrets.COVERITY_SCAN_TOKEN }} + COVERITY_EMAIL: ${{ secrets.COVERITY_SCAN_EMAIL }} + shell: bash + run: | + # ${{ env.stepName }} + echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}" + + export PATH="$PATH:${{env.cov_scan_path}}" + cmake -S ./examples/cmake_example/ -B build + cd build + cov-build --dir cov-int make -j + # Move the report out of the build directory + tar czvf ../gcc_freertos_kernel_sample_build.tgz cov-int + + echo "::endgroup::" + echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }} " + + - env: + stepName: Upload Coverity Report for Scan + COVERITY_TOKEN: ${{ secrets.COVERITY_SCAN_TOKEN }} + COVERITY_EMAIL: ${{ secrets.COVERITY_SCAN_EMAIL }} + shell: bash + run: | + # ${{ env.stepName }} + echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}" + + COV_SCAN_UPLOAD_STATUS=$(curl --form token=${COVERITY_TOKEN} \ + --form email=${COVERITY_EMAIL} \ + --form file=@gcc_freertos_kernel_sample_build.tgz \ + --form version="Mainline" \ + --form description="FreeRTOS Kernel Commit Scan" \ + https://scan.coverity.com/builds?project=FreeRTOS-Kernel) + + echo "::endgroup::" + echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }} " + echo "${COV_SCAN_UPLOAD_STATUS}" | grep -q -e 'Build successfully submitted' || echo >&2 "Error submitting build for analysis: ${COV_SCAN_UPLOAD_STATUS}" + + - env: + stepName: Coverity Build for SMP FreeRTOS + COVERITY_TOKEN: ${{ secrets.COVERITY_SCAN_TOKEN }} + COVERITY_EMAIL: ${{ secrets.COVERITY_SCAN_EMAIL }} + shell: bash + run: | + # ${{ env.stepName }} + echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}" + + export PATH="$PATH:${{env.cov_scan_path}}" + cmake -S ./examples/cmake_example/ -B build -DFREERTOS_SMP_EXAMPLE=1 + cd build + cov-build --dir cov-int make -j + # Move the report out of the build directory + tar czvf ../gcc_freertos_kernel_smp_sample_build.tgz cov-int + + echo "::endgroup::" + echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }} " + + - env: + stepName: Upload FreeRTOS SMP Coverity Report for Scan + COVERITY_TOKEN: ${{ secrets.COVERITY_SCAN_TOKEN }} + COVERITY_EMAIL: ${{ secrets.COVERITY_SCAN_EMAIL }} + shell: bash + run: | + # ${{ env.stepName }} + echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}" + + COV_SCAN_UPLOAD_STATUS=$(curl --form token=${COVERITY_TOKEN} \ + --form email=${COVERITY_EMAIL} \ + --form file=@gcc_freertos_kernel_smp_sample_build.tgz \ + --form version="Mainline" \ + --form description="FreeRTOS Kernel SMP Commit Scan" \ + https://scan.coverity.com/builds?project=FreeRTOS-Kernel) + + echo "::endgroup::" + echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }} " + echo "${COV_SCAN_UPLOAD_STATUS}" | grep -q -e 'Build successfully submitted' || echo >&2 "Error submitting build for analysis: ${COV_SCAN_UPLOAD_STATUS}" diff --git a/.github/workflows/git-secrets.yml b/.github/workflows/git-secrets.yml new file mode 100644 index 000000000..81b929cd3 --- /dev/null +++ b/.github/workflows/git-secrets.yml @@ -0,0 +1,24 @@ +name: git-secrets Check +on: + push: + pull_request: + workflow_dispatch: +jobs: + git-secrets: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4.1.1 + with: + submodules: recursive + - name: Checkout awslabs/git-secrets + uses: actions/checkout@v4.1.1 + with: + repository: awslabs/git-secrets + ref: master + path: git-secrets + - name: Install git-secrets + run: cd git-secrets && sudo make install && cd .. + - name: Run git-secrets + run: | + git-secrets --register-aws + git-secrets --scan diff --git a/.github/workflows/kernel-checks.yml b/.github/workflows/kernel-checks.yml new file mode 100644 index 000000000..05443458c --- /dev/null +++ b/.github/workflows/kernel-checks.yml @@ -0,0 +1,69 @@ +name: Kernel-Checker + +on: [push, pull_request] + +jobs: + kernel-checker: + name: FreeRTOS Kernel Header Checks + runs-on: ubuntu-latest + steps: + # Install python 3 + - name: Tool Setup + uses: actions/setup-python@v3 + env: + GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} + + # There is shared code, hosted by FreeRTOS/FreeRTOS, with deps needed by header checker + - name: Checkout FreeRTOS Tools + uses: actions/checkout@v4.1.1 + with: + repository: FreeRTOS/FreeRTOS + sparse-checkout: '.github' + ref: main + path: tools + + # Checkout user pull request changes + - name: Checkout Pull Request + uses: actions/checkout@v4.1.1 + with: + path: inspect + + # Collect all affected files + - name: Collecting changed files + uses: lots0logs/gh-action-get-changed-files@2.2.2 + with: + token: ${{ secrets.GITHUB_TOKEN }} + + # Run checks + - env: + bashPass: \033[32;1mPASSED - + bashInfo: \033[33;1mINFO - + bashFail: \033[31;1mFAILED - + bashEnd: \033[0m + stepName: Check File Headers + name: ${{ env.stepName }} + shell: bash + run: | + # ${{ env.stepName }} + echo -e "::group::${{ env.bashInfo }} Install Dependencies ${{ env.bashEnd }}" + + # Copy the common tools from the FreeRTOS/FreeRTOS repo. + mv tools/.github/scripts/common inspect/.github/scripts + + # Install the necessary python dependencies + pip install -r inspect/.github/scripts/common/requirements.txt + cd inspect + + echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}" + + # Use the python script to check the copyright header of modified files. + .github/scripts/kernel_checker.py --json ${HOME}/files_modified.json ${HOME}/files_added.json ${HOME}/files_renamed.json + exitStatus=$? + echo -e "::endgroup::" + + if [ $exitStatus -eq 0 ]; then + echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }}" + else + echo -e "${{ env.bashFail }} ${{ env.stepName }} ${{ env.bashEnd }}" + fi + exit $exitStatus diff --git a/.github/workflows/kernel-demos.yml b/.github/workflows/kernel-demos.yml new file mode 100644 index 000000000..9371e9cea --- /dev/null +++ b/.github/workflows/kernel-demos.yml @@ -0,0 +1,342 @@ +name: FreeRTOS-Kernel Demos +on: [push, pull_request] + +env: + # The bash escape character is \033 + bashPass: \033[32;1mPASSED - + bashInfo: \033[33;1mINFO - + bashFail: \033[31;1mFAILED - + bashEnd: \033[0m + +jobs: + WIN32-MSVC: + name: WIN32 MSVC + runs-on: windows-latest + steps: + - name: Checkout the FreeRTOS/FreeRTOS Repository + uses: actions/checkout@v4.1.1 + with: + ref: main + repository: FreeRTOS/FreeRTOS + submodules: 'recursive' + fetch-depth: 1 + + # Checkout user pull request changes + - name: Checkout Pull Request + uses: actions/checkout@v4.1.1 + with: + path: ./FreeRTOS/Source + + - name: Add msbuild to PATH + uses: microsoft/setup-msbuild@v1.1 + + - name: Build WIN32-MSVC Demo + working-directory: FreeRTOS/Demo/WIN32-MSVC + run: msbuild WIN32.sln -t:rebuild + + - name: Build WIN32-MSVC-Static-Allocation-Only Demo + working-directory: FreeRTOS/Demo/WIN32-MSVC-Static-Allocation-Only + run: msbuild WIN32.sln -t:rebuild + + WIN32-MingW: + name: WIN32 MingW + runs-on: windows-latest + steps: + - name: Checkout the FreeRTOS/FreeRTOS Repository + uses: actions/checkout@v4.1.1 + with: + ref: main + repository: FreeRTOS/FreeRTOS + submodules: 'recursive' + fetch-depth: 1 + + # Checkout user pull request changes + - name: Checkout Pull Request + uses: actions/checkout@v4.1.1 + with: + path: ./FreeRTOS/Source + + - name: Build WIN32-MingW Demo + working-directory: FreeRTOS/Demo/WIN32-MingW + run: | + gcc --version + make --version + make + + POSIX-GCC: + name: Native GCC + strategy: + fail-fast: false + matrix: + os: + - macos-latest + - ubuntu-latest + runs-on: ${{ matrix.os }} + steps: + - name: Checkout the FreeRTOS/FreeRTOS Repository + uses: actions/checkout@v4.1.1 + with: + ref: main + repository: FreeRTOS/FreeRTOS + submodules: 'recursive' + fetch-depth: 1 + + # Checkout user pull request changes + - name: Checkout Pull Request + uses: actions/checkout@v4.1.1 + with: + path: ./FreeRTOS/Source + + - name: Install GCC + shell: bash + if: matrix.os == 'ubuntu-latest' + run: | + sudo apt-get -y update + sudo apt-get -y install build-essential + + - name: Build Posix_GCC Demo + shell: bash + working-directory: FreeRTOS/Demo/Posix_GCC + run: make -j + + - name: Build Posix_GCC Demo for Coverage Test + shell: bash + working-directory: FreeRTOS/Demo/Posix_GCC + run: make -j COVERAGE_TEST=1 + + CMake-Example: + name: CMake Example with Native GCC + runs-on: ubuntu-latest + steps: + # Checkout user pull request changes + - name: Checkout Repository + uses: actions/checkout@v4.1.1 + + - name: Install GCC + shell: bash + run: | + sudo apt-get -y update + sudo apt-get -y install build-essential + + - name: Build CMake Example Demo + shell: bash + working-directory: examples/cmake_example + run: | + cmake -S . -B build + cmake --build build + + - name: Build CMake SMP Example Demo + shell: bash + working-directory: examples/cmake_example + run: | + cmake -S . -B build -DFREERTOS_SMP_EXAMPLE=1 + cmake --build build + + MSP430-GCC: + name: GNU MSP430 Toolchain + runs-on: ubuntu-latest + steps: + - name: Checkout the FreeRTOS/FreeRTOS Repository + uses: actions/checkout@v4.1.1 + with: + ref: main + repository: FreeRTOS/FreeRTOS + submodules: 'recursive' + fetch-depth: 1 + + # Checkout user pull request changes + - name: Checkout Pull Request + uses: actions/checkout@v4.1.1 + with: + path: ./FreeRTOS/Source + + - env: + stepName: Install MSP430 Toolchain + shell: bash + run: | + # ${{ env.stepName }} + echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}" + sudo apt update -y + sudo apt install -y p7zip-full + pushd $HOME + curl -L -o msp430-gcc-full-linux-x64-installer-9.3.1.2.7z https://dr-download.ti.com/software-development/ide-configuration-compiler-or-debugger/MD-LlCjWuAbzH/9.3.1.2/msp430-gcc-full-linux-x64-installer-9.3.1.2.7z + + EXPECTED_MD5="2db2f99b4cd5c541ca0389ee20c67527" + GENERATED_MD5=$(md5sum msp430-gcc-full-linux-x64-installer-9.3.1.2.7z | awk '{print $1}') + + if [ "$GENERATED_MD5" = "$EXPECTED_MD5" ]; then + 7z x ./msp430-gcc-full-linux-x64-installer-9.3.1.2.7z + chmod +x ./msp430-gcc-full-linux-x64-installer-9.3.1.2.run + sudo ./msp430-gcc-full-linux-x64-installer-9.3.1.2.run --prefix /usr/bin/msp430-gcc --mode unattended + echo "::endgroup::" + popd + echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }}" + else + popd + echo -e "${{ env.bashFail }} MD5 checksum verification failed for msp430-gcc-full-linux-x64-installer-9.3.1.2.7z ${{ env.bashEnd }}" + echo -e "${{ env.bashFail }} ${{ env.stepName }} ${{ env.bashEnd }}" + exit -1 + fi + + - name: Build msp430_GCC Demo + shell: bash + working-directory: FreeRTOS/Demo/msp430_GCC + run: make -j CC=/usr/bin/msp430-gcc/bin/msp430-elf-gcc OPT="-Os -I/usr/bin/msp430-gcc/include -L/usr/bin/msp430-gcc/include" + + MicroBlaze-GCC: + name: GCC MicroBlaze Toolchain + runs-on: ubuntu-latest + steps: + - name: Checkout the FreeRTOS/FreeRTOS Repository + uses: actions/checkout@v4.1.1 + with: + ref: main + repository: FreeRTOS/FreeRTOS + fetch-depth: 1 + + - env: + stepName: Fetch Community-Supported-Demos Submodule + shell: bash + run: | + # ${{ env.stepName }} + echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}" + git submodule update --checkout --init --depth 1 FreeRTOS/Demo/ThirdParty/Community-Supported-Demos + # This repository contains the microblaze_instructions.h header file + git clone https://github.com/Xilinx/embeddedsw.git --branch xilinx_v2023.1 + echo "::endgroup::" + echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }}" + + # Checkout user pull request changes + - name: Checkout Pull Request + uses: actions/checkout@v4.1.1 + with: + path: ./FreeRTOS/Source + + - env: + stepName: Install Dependancies + shell: bash + run: | + # ${{ env.stepName }} + echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}" + sudo apt update -y + sudo apt upgrade -y + sudo apt install -y build-essential m4 debhelper bison texinfo dejagnu flex + sudo apt install -y autogen gawk libgmp-dev libmpc-dev libmpfr-dev + sudo apt install -y patchutils sharutils zlib1g-dev autoconf2.64 + + pushd $HOME + # Download the mb-gcc toolchain from github + curl -L -o binutils-microblaze.deb https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/binutils-microblaze_2.35-2021-0623+1_amd64.deb; + curl -L -o gcc-microblaze.deb https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/gcc-microblaze_10.2.0-2021-0623+2_amd64.deb; + curl -L -o libnewlib-microblaze-dev.deb https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/libnewlib-microblaze-dev_3.3.0-2021-0623+3_all.deb; + curl -L -o libnewlib-microblaze-doc.deb https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/libnewlib-microblaze-doc_3.3.0-2021-0623+3_all.deb; + curl -L -o libnewlib-microblaze.deb https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/libnewlib-microblaze_3.3.0-2021-0623+3_all.deb; + curl -L -o newlib-source.deb https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/newlib-source_3.3.0-2021-0623+3_all.deb; + popd + + # Install the packages for the toolchain + sudo apt install -y $HOME/binutils-microblaze.deb; + sudo apt install -y $HOME/gcc-microblaze.deb; + sudo apt install -y $HOME/libnewlib-microblaze-dev.deb; + sudo apt install -y $HOME/libnewlib-microblaze-doc.deb; + sudo apt install -y $HOME/libnewlib-microblaze.deb; + sudo apt install -y $HOME/newlib-source.deb; + + # Validate that the toolchain is in the path and can be called + which mb-gcc + mb-gcc --version + + echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }}" + + - env: + stepName: Compile Microblaze Port + shell: bash + run: | + # ${{ env.stepName }} + echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}" + # Compile MicroBlazeV9 Port files to validate they build + mb-gcc -mcpu=v9.5 -c \ + FreeRTOS/Source/portable/GCC/MicroBlazeV9/port.c \ + FreeRTOS/Source/portable/GCC/MicroBlazeV9/portasm.S \ + FreeRTOS/Source/portable/GCC/MicroBlazeV9/port_exceptions.c \ + FreeRTOS/Source/tasks.c \ + FreeRTOS/Source/list.c \ + -I embeddedsw/lib/bsp/standalone/src/microblaze \ + -I FreeRTOS/Source/portable/GCC/MicroBlazeV9/ \ + -I FreeRTOS/Source/include \ + -I FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src \ + -I FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src \ + -I FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/include \ + -I FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_5/src + echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }}" + + + ARM-GCC: + name: GNU ARM Toolchain + runs-on: ubuntu-latest + steps: + - name: Checkout the FreeRTOS/FreeRTOS Repository + uses: actions/checkout@v4.1.1 + with: + ref: main + repository: FreeRTOS/FreeRTOS + fetch-depth: 1 + + - env: + stepName: Fetch Dependencies + shell: bash + run: | + # ${{ env.stepName }} + echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}" + git submodule update --checkout --init --depth 1 FreeRTOS/Demo/ThirdParty/Community-Supported-Demos FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace + echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }}" + + # Checkout user pull request changes + - name: Checkout Pull Request + uses: actions/checkout@v4.1.1 + with: + path: ./FreeRTOS/Source + + - name: Install GNU ARM Toolchain + shell: bash + run: | + sudo apt-get -y update + sudo apt-get -y install gcc-arm-none-eabi build-essential cmake git ninja-build python3-minimal + + - name: Build CORTEX_MPU_M3_MPS2_QEMU_GCC Demo + shell: bash + working-directory: FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC + run: make -j + + - name: Build CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC Demo + shell: bash + working-directory: FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC + run: cmake -S . -B build && make -j -C build all + + - name: Build CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC Demo + shell: bash + working-directory: FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC + run: cmake -S . -B build && make -j -C build all + + - name: Build CORTEX_LM3S102_GCC Demo + shell: bash + working-directory: FreeRTOS/Demo/CORTEX_LM3S102_GCC + run: make -j + + - name: Build CORTEX_LM3S811_GCC Demo + shell: bash + working-directory: FreeRTOS/Demo/CORTEX_LM3S811_GCC + run: make -j + + - name: Build CORTEX_M0+_RP2040 Demos + shell: bash + working-directory: FreeRTOS/Demo/ThirdParty/Community-Supported-Demos/CORTEX_M0+_RP2040 + run: | + git clone https://github.com/raspberrypi/pico-sdk.git + cmake -B build -DPICO_SDK_PATH=pico-sdk -GNinja + ninja -C build --verbose + + - name: Build CORTEX_MPS2_QEMU_IAR_GCC Demo + shell: bash + working-directory: FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC + run: make -C build/gcc -j diff --git a/.github/workflows/unit-tests.yml b/.github/workflows/unit-tests.yml new file mode 100644 index 000000000..bc8aaf69c --- /dev/null +++ b/.github/workflows/unit-tests.yml @@ -0,0 +1,56 @@ +name: CMock Unit Tests +on: [push, pull_request] + +jobs: + run: + runs-on: ubuntu-latest + steps: + - name: Checkout Parent Repository + uses: actions/checkout@v4.1.1 + with: + ref: main + repository: FreeRTOS/FreeRTOS + submodules: 'recursive' + fetch-depth: 1 + + # Checkout user pull request changes + - name: Checkout Pull Request + uses: actions/checkout@v4.1.1 + with: + path: ./FreeRTOS/Source + + - name: Setup Python + uses: actions/setup-python@master + with: + python-version: 3.8 + + - name: Install packages + run: | + sudo apt-get install lcov cflow ruby doxygen build-essential unifdef + - name: Run Unit Tests with ENABLE_SANITIZER=1 + run: | + make -C FreeRTOS/Test/CMock clean + make -C FreeRTOS/Test/CMock ENABLE_SANITIZER=1 run_col_formatted + - name: Run Unit Tests for coverage + run: | + make -C FreeRTOS/Test/CMock clean + make -C FreeRTOS/Test/CMock lcovhtml + lcov --config-file FreeRTOS/Test/CMock/lcovrc --summary FreeRTOS/Test/CMock/build/cmock_test.info > FreeRTOS/Test/CMock/build/cmock_test_summary.txt + - name: Upload coverage to Codecov + uses: codecov/codecov-action@v3.1.0 + with: + files: ${{ github.workspace }}/FreeRTOS/Test/CMock/build/cmock_test.info + root_dir: ${{ github.workspace }}/FreeRTOS/Source + flags: unittests + fail_ci_if_error: false + verbose: false + - name: Archive code coverage data + uses: actions/upload-artifact@v4 + with: + name: coverage-data + path: FreeRTOS/Test/CMock/build/cmock_test* + - name: Archive code coverage html report + uses: actions/upload-artifact@v4 + with: + name: coverage-report + path: FreeRTOS/Test/CMock/build/coverage diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 000000000..aaa2390a6 --- /dev/null +++ b/.gitmodules @@ -0,0 +1,6 @@ +[submodule "ThirdParty/FreeRTOS-Kernel-Partner-Supported-Ports"] + path = portable/ThirdParty/Partner-Supported-Ports + url = https://github.com/FreeRTOS/FreeRTOS-Kernel-Partner-Supported-Ports +[submodule "ThirdParty/FreeRTOS-Kernel-Community-Supported-Ports"] + path = portable/ThirdParty/Community-Supported-Ports + url = https://github.com/FreeRTOS/FreeRTOS-Kernel-Community-Supported-Ports diff --git a/CMakeLists.txt b/CMakeLists.txt new file mode 100644 index 000000000..914333746 --- /dev/null +++ b/CMakeLists.txt @@ -0,0 +1,289 @@ +cmake_minimum_required(VERSION 3.15) + +# User is responsible to one mandatory option: +# FREERTOS_PORT, if not specified and native port detected, uses the native compile. +# +# User is responsible for one library target: +# freertos_config ,typically an INTERFACE library +# +# DEPRECATED: FREERTOS_CONFIG_FILE_DIRECTORY - but still supported if no freertos_config defined for now. +# May be removed at some point in the future. +# +# User can choose which heap implementation to use (either the implementations +# included with FreeRTOS [1..5] or a custom implementation) by providing the +# option FREERTOS_HEAP. When dynamic allocation is used, the user must specify a +# heap implementation. If the option is not set, the cmake will use no heap +# implementation (e.g. when only static allocation is used). + +# `freertos_config` target defines the path to FreeRTOSConfig.h and optionally other freertos based config files +if(NOT TARGET freertos_config ) + if (NOT DEFINED FREERTOS_CONFIG_FILE_DIRECTORY ) + + message(FATAL_ERROR " freertos_config target not specified. Please specify a cmake target that defines the include directory for FreeRTOSConfig.h:\n" + " add_library(freertos_config INTERFACE)\n" + " target_include_directories(freertos_config SYSTEM\n" + " INTERFACE\n" + " include) # The config file directory\n" + " target_compile_definitions(freertos_config\n" + " PUBLIC\n" + " projCOVERAGE_TEST=0)\n") + else() + message(WARNING " Using deprecated 'FREERTOS_CONFIG_FILE_DIRECTORY' - please update your project CMakeLists.txt file:\n" + " add_library(freertos_config INTERFACE)\n" + " target_include_directories(freertos_config SYSTEM\n" + " INTERFACE\n" + " include) # The config file directory\n" + " target_compile_definitions(freertos_config\n" + " PUBLIC\n" + " projCOVERAGE_TEST=0)\n") + endif() +endif() + +# FreeRTOS port option +if(NOT FREERTOS_PORT) + message(WARNING " FREERTOS_PORT is not set. Please specify it from top-level CMake file (example):\n" + " set(FREERTOS_PORT GCC_ARM_CM4F CACHE STRING \"\")\n" + " or from CMake command line option:\n" + " -DFREERTOS_PORT=GCC_ARM_CM4F\n" + " \n" + " Available port options:\n" + " A_CUSTOM_PORT - Compiler: User Defined Target: User Defined\n" + " BCC_16BIT_DOS_FLSH186 - Compiler: BCC Target: 16 bit DOS Flsh186\n" + " BCC_16BIT_DOS_PC - Compiler: BCC Target: 16 bit DOS PC\n" + " CCS_ARM_CM3 - Compiler: CCS Target: ARM Cortex-M3\n" + " CCS_ARM_CM4F - Compiler: CCS Target: ARM Cortex-M4 with FPU\n" + " CCS_ARM_CR4 - Compiler: CCS Target: ARM Cortex-R4\n" + " CCS_MSP430X - Compiler: CCS Target: MSP430X\n" + " CODEWARRIOR_COLDFIRE_V1 - Compiler: CoreWarrior Target: ColdFire V1\n" + " CODEWARRIOR_COLDFIRE_V2 - Compiler: CoreWarrior Target: ColdFire V2\n" + " CODEWARRIOR_HCS12 - Compiler: CoreWarrior Target: HCS12\n" + " GCC_ARM_CA9 - Compiler: GCC Target: ARM Cortex-A9\n" + " GCC_ARM_AARCH64 - Compiler: GCC Target: ARM v8-A\n" + " GCC_ARM_AARCH64_SRE - Compiler: GCC Target: ARM v8-A SRE\n" + " GCC_ARM_CM0 - Compiler: GCC Target: ARM Cortex-M0\n" + " GCC_ARM_CM3 - Compiler: GCC Target: ARM Cortex-M3\n" + " GCC_ARM_CM3_MPU - Compiler: GCC Target: ARM Cortex-M3 with MPU\n" + " GCC_ARM_CM4_MPU - Compiler: GCC Target: ARM Cortex-M4 with MPU\n" + " GCC_ARM_CM4F - Compiler: GCC Target: ARM Cortex-M4 with FPU\n" + " GCC_ARM_CM7 - Compiler: GCC Target: ARM Cortex-M7\n" + " GCC_ARM_CM23_NONSECURE - Compiler: GCC Target: ARM Cortex-M23 non-secure\n" + " GCC_ARM_CM23_SECURE - Compiler: GCC Target: ARM Cortex-M23 secure\n" + " GCC_ARM_CM23_NTZ_NONSECURE - Compiler: GCC Target: ARM Cortex-M23 non-trustzone non-secure\n" + " GCC_ARM_CM33_NONSECURE - Compiler: GCC Target: ARM Cortex-M33 non-secure\n" + " GCC_ARM_CM33_SECURE - Compiler: GCC Target: ARM Cortex-M33 secure\n" + " GCC_ARM_CM33_NTZ_NONSECURE - Compiler: GCC Target: ARM Cortex-M33 non-trustzone non-secure\n" + " GCC_ARM_CM33_TFM - Compiler: GCC Target: ARM Cortex-M33 non-secure for TF-M\n" + " GCC_ARM_CM35P_NONSECURE - Compiler: GCC Target: ARM Cortex-M35P non-secure\n" + " GCC_ARM_CM35P_SECURE - Compiler: GCC Target: ARM Cortex-M35P secure\n" + " GCC_ARM_CM35P_NTZ_NONSECURE - Compiler: GCC Target: ARM Cortex-M35P non-trustzone non-secure\n" + " GCC_ARM_CM52_NONSECURE - Compiler: GCC Target: ARM Cortex-M52 non-secure\n" + " GCC_ARM_CM52_SECURE - Compiler: GCC Target: ARM Cortex-M52 secure\n" + " GCC_ARM_CM52_NTZ_NONSECURE - Compiler: GCC Target: ARM Cortex-M52 non-trustzone non-secure\n" + " GCC_ARM_CM52_TFM - Compiler: GCC Target: ARM Cortex-M52 non-secure for TF-M\n" + " GCC_ARM_CM55_NONSECURE - Compiler: GCC Target: ARM Cortex-M55 non-secure\n" + " GCC_ARM_CM55_SECURE - Compiler: GCC Target: ARM Cortex-M55 secure\n" + " GCC_ARM_CM55_NTZ_NONSECURE - Compiler: GCC Target: ARM Cortex-M55 non-trustzone non-secure\n" + " GCC_ARM_CM55_TFM - Compiler: GCC Target: ARM Cortex-M55 non-secure for TF-M\n" + " GCC_ARM_CM85_NONSECURE - Compiler: GCC Target: ARM Cortex-M85 non-secure\n" + " GCC_ARM_CM85_SECURE - Compiler: GCC Target: ARM Cortex-M85 secure\n" + " GCC_ARM_CM85_NTZ_NONSECURE - Compiler: GCC Target: ARM Cortex-M85 non-trustzone non-secure\n" + " GCC_ARM_CM85_TFM - Compiler: GCC Target: ARM Cortex-M85 non-secure for TF-M\n" + " GCC_ARM_STAR_MC3_NONSECURE - Compiler: GCC Target: Arm China STAR-MC3 non-secure\n" + " GCC_ARM_STAR_MC3_SECURE - Compiler: GCC Target: Arm China STAR-MC3 secure\n" + " GCC_ARM_STAR_MC3_NTZ_NONSECURE - Compiler: GCC Target: Arm China STAR-MC3 non-trustzone non-secure\n" + " GCC_ARM_STAR_MC3_TFM - Compiler: GCC Target: Arm China STAR-MC3 non-secure for TF-M\n" + " GCC_ARM_CR5 - Compiler: GCC Target: ARM Cortex-R5\n" + " GCC_ARM_CRX_MPU - Compiler: GCC Target: ARM Cortex-Rx with MPU\n" + " GCC_ARM_CRX_NOGIC - Compiler: GCC Target: ARM Cortex-Rx no GIC\n" + " GCC_ARM_CR82 - Compiler: GCC Target: ARM Cortex-R82\n" + " GCC_ARM7_AT91FR40008 - Compiler: GCC Target: ARM7 Atmel AT91R40008\n" + " GCC_ARM7_AT91SAM7S - Compiler: GCC Target: ARM7 Atmel AT91SAM7S\n" + " GCC_ARM7_LPC2000 - Compiler: GCC Target: ARM7 LPC2000\n" + " GCC_ARM7_LPC23XX - Compiler: GCC Target: ARM7 LPC23xx\n" + " GCC_ATMEGA323 - Compiler: GCC Target: ATMega323\n" + " GCC_AVR32_UC3 - Compiler: GCC Target: AVR32 UC3\n" + " GCC_COLDFIRE_V2 - Compiler: GCC Target: ColdFire V2\n" + " GCC_CORTUS_APS3 - Compiler: GCC Target: CORTUS APS3\n" + " GCC_H8S2329 - Compiler: GCC Target: H8S2329\n" + " GCC_HCS12 - Compiler: GCC Target: HCS12\n" + " GCC_IA32_FLAT - Compiler: GCC Target: IA32 flat\n" + " GCC_MICROBLAZE - Compiler: GCC Target: MicroBlaze\n" + " GCC_MICROBLAZE_V8 - Compiler: GCC Target: MicroBlaze V8\n" + " GCC_MICROBLAZE_V9 - Compiler: GCC Target: MicroBlaze V9\n" + " GCC_MSP430F449 - Compiler: GCC Target: MSP430F449\n" + " GCC_NIOSII - Compiler: GCC Target: NiosII\n" + " GCC_PPC405_XILINX - Compiler: GCC Target: Xilinx PPC405\n" + " GCC_PPC440_XILINX - Compiler: GCC Target: Xilinx PPC440\n" + " GCC_RISC_V - Compiler: GCC Target: RISC-V\n" + " GCC_RISC_V_PULPINO_VEGA_RV32M1RM - Compiler: GCC Target: RISC-V Pulpino Vega RV32M1RM\n" + " GCC_RISC_V_GENERIC - Compiler: GCC Target: RISC-V with FREERTOS_RISCV_EXTENSION\n" + " GCC_RL78 - Compiler: GCC Target: Renesas RL78\n" + " GCC_RX100 - Compiler: GCC Target: Renesas RX100\n" + " GCC_RX200 - Compiler: GCC Target: Renesas RX200\n" + " GCC_RX600 - Compiler: GCC Target: Renesas RX600\n" + " GCC_RX600_V2 - Compiler: GCC Target: Renesas RX600 v2\n" + " GCC_RX700_V3_DPFPU - Compiler: GCC Target: Renesas RX700 v3 with DPFPU\n" + " GCC_STR75X - Compiler: GCC Target: STR75x\n" + " GCC_TRICORE_1782 - Compiler: GCC Target: TriCore 1782\n" + " GCC_ARC_EM_HS - Compiler: GCC Target: DesignWare ARC EM HS\n" + " GCC_ARC_V1 - Compiler: GCC Target: DesignWare ARC v1\n" + " GCC_ATMEGA - Compiler: GCC Target: ATmega\n" + " GCC_POSIX - Compiler: GCC Target: Posix\n" + " GCC_RP2040 - Compiler: GCC Target: RP2040 ARM Cortex-M0+\n" + " GCC_XTENSA_ESP32 - Compiler: GCC Target: Xtensa ESP32\n" + " GCC_AVRDX - Compiler: GCC Target: AVRDx\n" + " GCC_AVR_MEGA0 - Compiler: GCC Target: AVR Mega0\n" + " IAR_78K0K - Compiler: IAR Target: Renesas 78K0K\n" + " IAR_ARM_CA5_NOGIC - Compiler: IAR Target: ARM Cortex-A5 no GIC\n" + " IAR_ARM_CA9 - Compiler: IAR Target: ARM Cortex-A9\n" + " IAR_ARM_CM0 - Compiler: IAR Target: ARM Cortex-M0\n" + " IAR_ARM_CM3 - Compiler: IAR Target: ARM Cortex-M3\n" + " IAR_ARM_CM4F - Compiler: IAR Target: ARM Cortex-M4 with FPU\n" + " IAR_ARM_CM4F_MPU - Compiler: IAR Target: ARM Cortex-M4 with FPU and MPU\n" + " IAR_ARM_CM7 - Compiler: IAR Target: ARM Cortex-M7\n" + " IAR_ARM_CM23_NONSECURE - Compiler: IAR Target: ARM Cortex-M23 non-secure\n" + " IAR_ARM_CM23_SECURE - Compiler: IAR Target: ARM Cortex-M23 secure\n" + " IAR_ARM_CM23_NTZ_NONSECURE - Compiler: IAR Target: ARM Cortex-M23 non-trustzone non-secure\n" + " IAR_ARM_CM33_NONSECURE - Compiler: IAR Target: ARM Cortex-M33 non-secure\n" + " IAR_ARM_CM33_SECURE - Compiler: IAR Target: ARM Cortex-M33 secure\n" + " IAR_ARM_CM33_NTZ_NONSECURE - Compiler: IAR Target: ARM Cortex-M33 non-trustzone non-secure\n" + " IAR_ARM_CM33_TFM - Compiler: IAR Target: ARM Cortex-M33 non-secure for TF-M\n" + " IAR_ARM_CM35P_NONSECURE - Compiler: IAR Target: ARM Cortex-M35P non-secure\n" + " IAR_ARM_CM35P_SECURE - Compiler: IAR Target: ARM Cortex-M35P secure\n" + " IAR_ARM_CM35P_NTZ_NONSECURE - Compiler: IAR Target: ARM Cortex-M35P non-trustzone non-secure\n" + " IAR_ARM_CM52_NONSECURE - Compiler: IAR Target: ARM Cortex-M52 non-secure\n" + " IAR_ARM_CM52_SECURE - Compiler: IAR Target: ARM Cortex-M52 secure\n" + " IAR_ARM_CM52_NTZ_NONSECURE - Compiler: IAR Target: ARM Cortex-M52 non-trustzone non-secure\n" + " IAR_ARM_CM52_TFM - Compiler: IAR Target: ARM Cortex-M52 non-secure for TF-M\n" + " IAR_ARM_CM55_NONSECURE - Compiler: IAR Target: ARM Cortex-M55 non-secure\n" + " IAR_ARM_CM55_SECURE - Compiler: IAR Target: ARM Cortex-M55 secure\n" + " IAR_ARM_CM55_NTZ_NONSECURE - Compiler: IAR Target: ARM Cortex-M55 non-trustzone non-secure\n" + " IAR_ARM_CM55_TFM - Compiler: IAR Target: ARM Cortex-M55 non-secure for TF-M\n" + " IAR_ARM_CM85_NONSECURE - Compiler: IAR Target: ARM Cortex-M85 non-secure\n" + " IAR_ARM_CM85_SECURE - Compiler: IAR Target: ARM Cortex-M85 secure\n" + " IAR_ARM_CM85_NTZ_NONSECURE - Compiler: IAR Target: ARM Cortex-M85 non-trustzone non-secure\n" + " IAR_ARM_CM85_TFM - Compiler: IAR Target: ARM Cortex-M85 non-secure for TF-M\n" + " IAR_ARM_STAR_MC3_NONSECURE - Compiler: IAR Target: Arm China STAR-MC3 non-secure\n" + " IAR_ARM_STAR_MC3_SECURE - Compiler: IAR Target: Arm China STAR-MC3 secure\n" + " IAR_ARM_STAR_MC3_NTZ_NONSECURE - Compiler: IAR Target: Arm China STAR-MC3 non-trustzone non-secure\n" + " IAR_ARM_STAR_MC3_TFM - Compiler: IAR Target: Arm China STAR-MC3 non-secure for TF-M\n" + " IAR_ARM_CRX_NOGIC - Compiler: IAR Target: ARM Cortex-Rx no GIC\n" + " IAR_ATMEGA323 - Compiler: IAR Target: ATMega323\n" + " IAR_ATMEL_SAM7S64 - Compiler: IAR Target: Atmel SAM7S64\n" + " IAR_ATMEL_SAM9XE - Compiler: IAR Target: Atmel SAM9XE\n" + " IAR_AVR_AVRDX - Compiler: IAR Target: AVRDx\n" + " IAR_AVR_MEGA0 - Compiler: IAR Target: AVR Mega0\n" + " IAR_AVR32_UC3 - Compiler: IAR Target: AVR32 UC3\n" + " IAR_LPC2000 - Compiler: IAR Target: LPC2000\n" + " IAR_MSP430 - Compiler: IAR Target: MSP430\n" + " IAR_MSP430X - Compiler: IAR Target: MSP430X\n" + " IAR_RISC_V - Compiler: IAR Target: RISC-V\n" + " IAR_RISC_V_GENERIC - Compiler: IAR Target: RISC-V with FREERTOS_RISCV_EXTENSION\n" + " IAR_RL78 - Compiler: IAR Target: Renesas RL78\n" + " IAR_RX100 - Compiler: IAR Target: Renesas RX100\n" + " IAR_RX600 - Compiler: IAR Target: Renesas RX600\n" + " IAR_RX700_V3_DPFPU - Compiler: IAR Target: Renesas RX700 v3 with DPFPU\n" + " IAR_RX_V2 - Compiler: IAR Target: Renesas RX v2\n" + " IAR_STR71X - Compiler: IAR Target: STR71x\n" + " IAR_STR75X - Compiler: IAR Target: STR75x\n" + " IAR_STR91X - Compiler: IAR Target: STR91x\n" + " IAR_V850ES_FX3 - Compiler: IAR Target: Renesas V850ES/Fx3\n" + " IAR_V850ES_HX3 - Compiler: IAR Target: Renesas V850ES/Hx3\n" + " MIKROC_ARM_CM4F - Compiler: MikroC Target: ARM Cortex-M4 with FPU\n" + " MPLAB_PIC18F - Compiler: MPLAB Target: PIC18F\n" + " MPLAB_PIC24 - Compiler: MPLAB Target: PIC24\n" + " MPLAB_PIC32MEC14XX - Compiler: MPLAB Target: PIC32MEC14xx\n" + " MPLAB_PIC32MX - Compiler: MPLAB Target: PIC32MX\n" + " MPLAB_PIC32MZ - Compiler: MPLAB Target: PIC32MZ\n" + " MSVC_MINGW - Compiler: MSVC or MinGW Target: x86\n" + " OWATCOM_16BIT_DOS_FLSH186 - Compiler: Open Watcom Target: 16 bit DOS Flsh186\n" + " OWATCOM_16BIT_DOS_PC - Compiler: Open Watcom Target: 16 bit DOS PC\n" + " PARADIGM_TERN_EE_LARGE - Compiler: Paradigm Target: Tern EE large\n" + " PARADIGM_TERN_EE_SMALL - Compiler: Paradigm Target: Tern EE small\n" + " RENESAS_RX100 - Compiler: Renesas Target: RX100\n" + " RENESAS_RX200 - Compiler: Renesas Target: RX200\n" + " RENESAS_RX600 - Compiler: Renesas Target: RX600\n" + " RENESAS_RX600_V2 - Compiler: Renesas Target: RX600 v2\n" + " RENESAS_RX700_V3_DPFPU - Compiler: Renesas Target: RX700 v3 with DPFPU\n" + " RENESAS_SH2A_FPU - Compiler: Renesas Target: SH2A with FPU\n" + " ROWLEY_MSP430F449 - Compiler: Rowley Target: MSP430F449\n" + " RVDS_ARM_CA9 - Compiler: RVDS Target: ARM Cortex-A9\n" + " RVDS_ARM_CM0 - Compiler: RVDS Target: ARM Cortex-M0\n" + " RVDS_ARM_CM3 - Compiler: RVDS Target: ARM Cortex-M3\n" + " RVDS_ARM_CM4_MPU - Compiler: RVDS Target: ARM Cortex-M4 with MPU\n" + " RVDS_ARM_CM4F - Compiler: RVDS Target: ARM Cortex-M4 with FPU\n" + " RVDS_ARM_CM7 - Compiler: RVDS Target: ARM Cortex-M7\n" + " RVDS_ARM7_LPC21XX - Compiler: RVDS Target: ARM7 LPC21xx\n" + " SDCC_CYGNAL - Compiler: SDCC Target: Cygnal\n" + " SOFTUNE_MB91460 - Compiler: Softune Target: MB91460\n" + " SOFTUNE_MB96340 - Compiler: Softune Target: MB96340\n" + " TASKING_ARM_CM4F - Compiler: Tasking Target: ARM Cortex-M4 with FPU\n" + " TEMPLATE - Compiler: HOST Target: None\n" + " CDK_THEAD_CK802 - Compiler: CDK Target: T-head CK802\n" + " XCC_XTENSA - Compiler: XCC Target: Xtensa\n" + " WIZC_PIC18 - Compiler: WizC Target: PIC18") + # Native FREERTOS_PORT for Linux and Windows MINGW builds + if(UNIX) + message(STATUS " Auto-Detected Unix, setting FREERTOS_PORT=GCC_POSIX") + set(FREERTOS_PORT GCC_POSIX CACHE STRING "FreeRTOS port name") + elseif(MINGW) + message(STATUS " Auto-Detected MINGW, setting FREERTOS_PORT=MSVC_MINGW") + set(FREERTOS_PORT MSVC_MINGW CACHE STRING "FreeRTOS port name") + endif() +elseif((FREERTOS_PORT STREQUAL "A_CUSTOM_PORT") AND (NOT TARGET freertos_kernel_port) ) + message(FATAL_ERROR " FREERTOS_PORT is set to A_CUSTOM_PORT. Please specify the custom port target with all necessary files. For example:\n" + " Assuming a directory of:\n" + " FreeRTOSCustomPort/\n" + " CMakeLists.txt\n" + " port.c\n" + " portmacro.h\n" + " Where FreeRTOSCustomPort/CMakeLists.txt is a modified version of:\n" + " add_library(freertos_kernel_port OBJECT)\n" + " target_sources(freertos_kernel_port\n" + " PRIVATE\n" + " port.c\n" + " portmacro.h)\n" + " add_library(freertos_kernel_port_headers INTERFACE)\n" + " target_include_directories(freertos_kernel_port_headers INTERFACE \n" + " .)\n" + " target_link_libraries(freertos_kernel_port\n" + " PRIVATE\n" + " freertos_kernel_port_headers\n" + " freertos_kernel_include)") +endif() + +add_library(freertos_kernel STATIC) + +######################################################################## +add_subdirectory(include) +add_subdirectory(portable) + +target_sources(freertos_kernel PRIVATE + croutine.c + event_groups.c + list.c + queue.c + stream_buffer.c + tasks.c + timers.c +) + +if (DEFINED FREERTOS_HEAP ) + # User specified a heap implementation add heap implementation to freertos_kernel. + target_sources(freertos_kernel PRIVATE + # If FREERTOS_HEAP is digit between 1 .. 5 - it is heap number, otherwise - it is path to custom heap source file + $>,${FREERTOS_HEAP},portable/MemMang/heap_${FREERTOS_HEAP}.c> + ) +endif() + + +target_link_libraries(freertos_kernel + PUBLIC + freertos_kernel_include + freertos_kernel_port_headers + PRIVATE + freertos_kernel_port + +) + +######################################################################## diff --git a/Demo/ARM7_AT91FR40008_GCC/AT91R40008.h b/Demo/ARM7_AT91FR40008_GCC/AT91R40008.h deleted file mode 100644 index e99ef0503..000000000 --- a/Demo/ARM7_AT91FR40008_GCC/AT91R40008.h +++ /dev/null @@ -1,707 +0,0 @@ -// ---------------------------------------------------------------------------- -// ATMEL Microcontroller Software Support - ROUSSET - -// ---------------------------------------------------------------------------- -// The software is delivered "AS IS" without warranty or condition of any -// kind, either express, implied or statutory. This includes without -// limitation any warranty or condition with respect to merchantability or -// fitness for any particular purpose, or against the infringements of -// intellectual property rights of others. -// ---------------------------------------------------------------------------- -// File Name : AT91R40008.h -// Object : AT91R40008 definitions -// Generated : AT91 SW Application Group 02/19/2003 (11:13:31) -// -// CVS Reference : /AT91R40008.pl/1.3/Tue Nov 12 16:01:52 2002// -// CVS Reference : /AIC_1246F.pl/1.4/Mon Nov 04 17:51:00 2002// -// CVS Reference : /WD_1241B.pl/1.1/Mon Nov 04 17:51:00 2002// -// CVS Reference : /PS_x40.pl/1.2/Tue Nov 12 16:01:52 2002// -// CVS Reference : /PIO_1321C.pl/1.5/Tue Oct 29 15:50:24 2002// -// CVS Reference : /TC_1243B.pl/1.4/Tue Nov 05 12:43:10 2002// -// CVS Reference : /PDC_1363D.pl/1.3/Wed Oct 23 14:49:48 2002// -// CVS Reference : /US_1242E.pl/1.5/Thu Nov 21 13:37:56 2002// -// CVS Reference : /SF_x40.pl/1.1/Tue Nov 12 13:27:20 2002// -// CVS Reference : /EBI_x40.pl/1.5/Wed Feb 19 09:25:22 2003// -// ---------------------------------------------------------------------------- - -#ifndef AT91R40008_H -#define AT91R40008_H - -/* AT91 Register type */ -typedef volatile unsigned int AT91_REG; // Hardware register definition -typedef volatile unsigned int at91_reg; - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// ***************************************************************************** -typedef struct _AT91S_AIC { - AT91_REG AIC_SMR[32]; // Source Mode egister - AT91_REG AIC_SVR[32]; // Source Vector egister - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command egister - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register -} AT91S_AIC, *AT91PS_AIC; - -// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level -#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level -#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level -#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type -#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive -#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered -#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered -// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status -#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Watchdog Timer Interface -// ***************************************************************************** -typedef struct _AT91S_WD { - AT91_REG WD_OMR; // Overflow Mode Register - AT91_REG WD_CMR; // Clock Mode Register - AT91_REG WD_CR; // Control Register - AT91_REG WD_SR; // Status Register -} AT91S_WD, *AT91PS_WD; - -// -------- WD_OMR : (WD Offset: 0x0) Overflow Mode Register -------- -#define AT91C_WD_WDEN ((unsigned int) 0x1 << 0) // (WD) Watchdog Enable -#define AT91C_WD_RSTEN ((unsigned int) 0x1 << 1) // (WD) Reset Enable -#define AT91C_WD_IRQEN ((unsigned int) 0x1 << 2) // (WD) Interrupt Enable -#define AT91C_WD_EXTEN ((unsigned int) 0x1 << 3) // (WD) External Signal Enable -#define AT91C_WD_OKEY ((unsigned int) 0xFFF << 4) // (WD) Watchdog Enable -// -------- WD_CMR : (WD Offset: 0x4) Clock Mode Register -------- -#define AT91C_WD_WDCLKS ((unsigned int) 0x3 << 0) // (WD) Clock Selection -#define AT91C_WD_WDCLKS_MCK32 ((unsigned int) 0x0) // (WD) Master Clock divided by 32 -#define AT91C_WD_WDCLKS_MCK128 ((unsigned int) 0x1) // (WD) Master Clock divided by 128 -#define AT91C_WD_WDCLKS_MCK1024 ((unsigned int) 0x2) // (WD) Master Clock divided by 1024 -#define AT91C_WD_WDCLKS_MCK4096 ((unsigned int) 0x3) // (WD) Master Clock divided by 4096 -#define AT91C_WD_HPCV ((unsigned int) 0xF << 2) // (WD) High Pre-load Counter Value -#define AT91C_WD_CKEY ((unsigned int) 0x1FF << 7) // (WD) Clock Access Key -// -------- WD_CR : (WD Offset: 0x8) Control Register -------- -#define AT91C_WD_RSTKEY ((unsigned int) 0xFFFF << 0) // (WD) Restart Key -// -------- WD_SR : (WD Offset: 0xc) Status Register -------- -#define AT91C_WD_WDOVF ((unsigned int) 0x1 << 0) // (WD) Watchdog Overflow - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Power Saving Controler -// ***************************************************************************** -typedef struct _AT91S_PS { - AT91_REG PS_CR; // Control Register - AT91_REG PS_PCER; // Peripheral Clock Enable Register - AT91_REG PS_PCDR; // Peripheral Clock Disable Register - AT91_REG PS_PCSR; // Peripheral Clock Status Register -} AT91S_PS, *AT91PS_PS; - -// -------- PS_PCER : (PS Offset: 0x4) Peripheral Clock Enable Register -------- -#define AT91C_PS_US0 ((unsigned int) 0x1 << 2) // (PS) Usart 0 Clock -#define AT91C_PS_US1 ((unsigned int) 0x1 << 3) // (PS) Usart 1 Clock -#define AT91C_PS_TC0 ((unsigned int) 0x1 << 4) // (PS) Timer Counter 0 Clock -#define AT91C_PS_TC1 ((unsigned int) 0x1 << 5) // (PS) Timer Counter 1 Clock -#define AT91C_PS_TC2 ((unsigned int) 0x1 << 6) // (PS) Timer Counter 2 Clock -#define AT91C_PS_PIO ((unsigned int) 0x1 << 8) // (PS) PIO Clock -// -------- PS_PCDR : (PS Offset: 0x8) Peripheral Clock Disable Register -------- -// -------- PS_PCSR : (PS Offset: 0xc) Peripheral Clock Satus Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// ***************************************************************************** -typedef struct _AT91S_PIO { - AT91_REG PIO_PER; // PIO Enable Register - AT91_REG PIO_PDR; // PIO Disable Register - AT91_REG PIO_PSR; // PIO Status Register - AT91_REG Reserved0[1]; // - AT91_REG PIO_OER; // Output Enable Register - AT91_REG PIO_ODR; // Output Disable Registerr - AT91_REG PIO_OSR; // Output Status Register - AT91_REG Reserved1[1]; // - AT91_REG PIO_IFER; // Input Filter Enable Register - AT91_REG PIO_IFDR; // Input Filter Disable Register - AT91_REG PIO_IFSR; // Input Filter Status Register - AT91_REG Reserved2[1]; // - AT91_REG PIO_SODR; // Set Output Data Register - AT91_REG PIO_CODR; // Clear Output Data Register - AT91_REG PIO_ODSR; // Output Data Status Register - AT91_REG PIO_PDSR; // Pin Data Status Register - AT91_REG PIO_IER; // Interrupt Enable Register - AT91_REG PIO_IDR; // Interrupt Disable Register - AT91_REG PIO_IMR; // Interrupt Mask Register - AT91_REG PIO_ISR; // Interrupt Status Register - AT91_REG PIO_MDER; // Multi-driver Enable Register - AT91_REG PIO_MDDR; // Multi-driver Disable Register - AT91_REG PIO_MDSR; // Multi-driver Status Register -} AT91S_PIO, *AT91PS_PIO; - - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// ***************************************************************************** -typedef struct _AT91S_TC { - AT91_REG TC_CCR; // Channel Control Register - AT91_REG TC_CMR; // Channel Mode Register - AT91_REG Reserved0[2]; // - AT91_REG TC_CV; // Counter Value - AT91_REG TC_RA; // Register A - AT91_REG TC_RB; // Register B - AT91_REG TC_RC; // Register C - AT91_REG TC_SR; // Status Register - AT91_REG TC_IER; // Interrupt Enable Register - AT91_REG TC_IDR; // Interrupt Disable Register - AT91_REG TC_IMR; // Interrupt Mask Register -} AT91S_TC, *AT91PS_TC; - -// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command -#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command -#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command -// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare -#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare -#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection -#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None -#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection -#define AT91C_TC_EEVT_NONE ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input -#define AT91C_TC_EEVT_RISING ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output -#define AT91C_TC_EEVT_FALLING ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output -#define AT91C_TC_EEVT_BOTH ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output -#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable -#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection -#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x1 << 13) // (TC) UP mode with automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x2 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare -#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable -#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) -#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA -#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none -#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set -#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear -#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle -#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA -#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none -#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set -#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear -#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle -#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA -#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none -#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set -#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear -#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle -#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA -#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none -#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set -#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear -#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle -#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB -#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none -#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set -#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear -#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle -#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB -#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none -#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set -#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear -#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle -#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB -#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none -#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set -#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear -#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle -#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB -#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none -#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set -#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear -#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle -// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow -#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun -#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare -#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare -#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare -#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading -#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading -#define AT91C_TC_ETRCS ((unsigned int) 0x1 << 7) // (TC) External Trigger -#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 16) // (TC) Clock Enabling -#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror -#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror -// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Interface -// ***************************************************************************** -typedef struct _AT91S_TCB { - AT91S_TC TCB_TC0; // TC Channel 0 - AT91_REG Reserved0[4]; // - AT91S_TC TCB_TC1; // TC Channel 1 - AT91_REG Reserved1[4]; // - AT91S_TC TCB_TC2; // TC Channel 2 - AT91_REG Reserved2[4]; // - AT91_REG TCB_BCR; // TC Block Control Register - AT91_REG TCB_BMR; // TC Block Mode Register -} AT91S_TCB, *AT91PS_TCB; - -// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command -// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -#define AT91C_TCB_TC0XC0S ((unsigned int) 0x1 << 0) // (TCB) External Clock Signal 0 Selection -#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 -#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 -#define AT91C_TCB_TC1XC1S ((unsigned int) 0x1 << 2) // (TCB) External Clock Signal 1 Selection -#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 -#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 -#define AT91C_TCB_TC2XC2S ((unsigned int) 0x1 << 4) // (TCB) External Clock Signal 2 Selection -#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 -#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA2 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Peripheral Data Controller -// ***************************************************************************** -typedef struct _AT91S_PDC { - AT91_REG PDC_RPR; // Receive Pointer Register - AT91_REG PDC_RCR; // Receive Counter Register - AT91_REG PDC_TPR; // Transmit Pointer Register - AT91_REG PDC_TCR; // Transmit Counter Register -} AT91S_PDC, *AT91PS_PDC; - - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Usart -// ***************************************************************************** -typedef struct _AT91S_USART { - AT91_REG US_CR; // Control Register - AT91_REG US_MR; // Mode Register - AT91_REG US_IER; // Interrupt Enable Register - AT91_REG US_IDR; // Interrupt Disable Register - AT91_REG US_IMR; // Interrupt Mask Register - AT91_REG US_CSR; // Channel Status Register - AT91_REG US_RHR; // Receiver Holding Register - AT91_REG US_THR; // Transmitter Holding Register - AT91_REG US_BRGR; // Baud Rate Generator Register - AT91_REG US_RTOR; // Receiver Time-out Register - AT91_REG US_TTGR; // Transmitter Time-guard Register - AT91_REG Reserved0[1]; // - AT91_REG US_RPR; // Receive Pointer Register - AT91_REG US_RCR; // Receive Counter Register - AT91_REG US_TPR; // Transmit Pointer Register - AT91_REG US_TCR; // Transmit Counter Register -} AT91S_USART, *AT91PS_USART; - -// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (USART) Reset Receiver -#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (USART) Reset Transmitter -#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (USART) Receiver Enable -#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (USART) Receiver Disable -#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (USART) Transmitter Enable -#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (USART) Transmitter Disable -#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (USART) Reset Status Bits -#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break -#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break -#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out -#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address -// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock -#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 -#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) -#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) -#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits -#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits -#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits -#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits -#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select -#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (USART) Parity type -#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (USART) Even Parity -#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (USART) Odd Parity -#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (USART) Parity forced to 0 (Space) -#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (USART) Parity forced to 1 (Mark) -#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (USART) No Parity -#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (USART) Multi-drop mode -#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits -#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit -#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits -#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (USART) Channel Mode -#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (USART) Normal Mode: The USART channel operates as an RX/TX USART. -#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (USART) Automatic Echo: Receiver Data Input is connected to the TXD pin. -#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (USART) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (USART) Remote Loopback: RXD pin is internally connected to TXD pin. -#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length -#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select -// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (USART) RXRDY Interrupt -#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (USART) TXRDY Interrupt -#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break -#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (USART) End of Receive Transfer Interrupt -#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (USART) End of Transmit Interrupt -#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (USART) Overrun Interrupt -#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (USART) Framing Error Interrupt -#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (USART) Parity Error Interrupt -#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out -#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (USART) TXEMPTY Interrupt -// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Special Function Interface -// ***************************************************************************** -typedef struct _AT91S_SF { - AT91_REG SF_CIDR; // Chip ID Register - AT91_REG SF_EXID; // Chip ID Extension Register - AT91_REG SF_RSR; // Reset Status Register - AT91_REG SF_MMR; // Memory Mode Register - AT91_REG Reserved0[2]; // - AT91_REG SF_PMR; // Protect Mode Register -} AT91S_SF, *AT91PS_SF; - -// -------- SF_CIDR : (SF Offset: 0x0) Chip ID Register -------- -#define AT91C_SF_VERSION ((unsigned int) 0x1F << 0) // (SF) Version of the chip -#define AT91C_SF_BIT5 ((unsigned int) 0x1 << 5) // (SF) Hardwired at 0 -#define AT91C_SF_BIT6 ((unsigned int) 0x1 << 6) // (SF) Hardwired at 1 -#define AT91C_SF_BIT7 ((unsigned int) 0x1 << 7) // (SF) Hardwired at 0 -#define AT91C_SF_NVPSIZ ((unsigned int) 0xF << 8) // (SF) Nonvolatile Program Memory Size -#define AT91C_SF_NVPSIZ_NONE ((unsigned int) 0x0 << 8) // (SF) None -#define AT91C_SF_NVPSIZ_32K ((unsigned int) 0x3 << 8) // (SF) 32K Bytes -#define AT91C_SF_NVPSIZ_64K ((unsigned int) 0x5 << 8) // (SF) 64K Bytes -#define AT91C_SF_NVPSIZ_128K ((unsigned int) 0x7 << 8) // (SF) 128K Bytes -#define AT91C_SF_NVPSIZ_256K ((unsigned int) 0x11 << 8) // (SF) 256K Bytes -#define AT91C_SF_NVDSIZ ((unsigned int) 0xF << 12) // (SF) Nonvolatile Data Memory Size -#define AT91C_SF_NVDSIZ_NONE ((unsigned int) 0x0 << 12) // (SF) None -#define AT91C_SF_VDSIZ ((unsigned int) 0xF << 16) // (SF) Volatile Data Memory Size -#define AT91C_SF_VDSIZ_NONE ((unsigned int) 0x0 << 16) // (SF) None -#define AT91C_SF_VDSIZ_1K ((unsigned int) 0x3 << 16) // (SF) 1K Bytes -#define AT91C_SF_VDSIZ_2K ((unsigned int) 0x5 << 16) // (SF) 2K Bytes -#define AT91C_SF_VDSIZ_4K ((unsigned int) 0x7 << 16) // (SF) 4K Bytes -#define AT91C_SF_VDSIZ_8K ((unsigned int) 0x11 << 16) // (SF) 8K Bytes -#define AT91C_SF_ARCH ((unsigned int) 0xFF << 20) // (SF) Chip Architecture -#define AT91C_SF_ARCH_AT91x40 ((unsigned int) 0x28 << 20) // (SF) AT91x40yyy -#define AT91C_SF_ARCH_AT91x55 ((unsigned int) 0x37 << 20) // (SF) AT91x55yyy -#define AT91C_SF_ARCH_AT91x63 ((unsigned int) 0x3F << 20) // (SF) AT91x63yyy -#define AT91C_SF_NVPTYP ((unsigned int) 0x7 << 28) // (SF) Nonvolatile Program Memory Type -#define AT91C_SF_NVPTYP_NVPTYP_M ((unsigned int) 0x1 << 28) // (SF) 'M' Series or 'F' Series -#define AT91C_SF_NVPTYP_NVPTYP_R ((unsigned int) 0x4 << 28) // (SF) 'R' Series -#define AT91C_SF_EXT ((unsigned int) 0x1 << 31) // (SF) Extension Flag -// -------- SF_RSR : (SF Offset: 0x8) Reset Status Information -------- -#define AT91C_SF_RESET ((unsigned int) 0xFF << 0) // (SF) Cause of Reset -#define AT91C_SF_RESET_WD ((unsigned int) 0x35) // (SF) Internal Watchdog -#define AT91C_SF_RESET_EXT ((unsigned int) 0x6C) // (SF) External Pin -// -------- SF_MMR : (SF Offset: 0xc) Memory Mode Register -------- -#define AT91C_SF_RAMWU ((unsigned int) 0x1 << 0) // (SF) Internal Extended RAM Write Detection -// -------- SF_PMR : (SF Offset: 0x18) Protection Mode Register -------- -#define AT91C_SF_AIC ((unsigned int) 0x1 << 5) // (SF) AIC Protect Mode Enable -#define AT91C_SF_PMRKEY ((unsigned int) 0xFFFF << 16) // (SF) Protect Mode Register Key - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR External Bus Interface -// ***************************************************************************** -typedef struct _AT91S_EBI { - AT91_REG EBI_CSR[8]; // Chip-select Register - AT91_REG EBI_RCR; // Remap Control Register - AT91_REG EBI_MCR; // Memory Control Register -} AT91S_EBI, *AT91PS_EBI; - -// -------- EBI_CSR : (EBI Offset: 0x0) Chip Select Register -------- -#define AT91C_EBI_DBW ((unsigned int) 0x3 << 0) // (EBI) Data Bus Width -#define AT91C_EBI_DBW_16 ((unsigned int) 0x1) // (EBI) 16-bit data bus width -#define AT91C_EBI_DBW_8 ((unsigned int) 0x2) // (EBI) 8-bit data bus width -#define AT91C_EBI_NWS ((unsigned int) 0x7 << 2) // (EBI) Number of wait states -#define AT91C_EBI_NWS_1 ((unsigned int) 0x0 << 2) // (EBI) 1 wait state -#define AT91C_EBI_NWS_2 ((unsigned int) 0x1 << 2) // (EBI) 2 wait state -#define AT91C_EBI_NWS_3 ((unsigned int) 0x2 << 2) // (EBI) 3 wait state -#define AT91C_EBI_NWS_4 ((unsigned int) 0x3 << 2) // (EBI) 4 wait state -#define AT91C_EBI_NWS_5 ((unsigned int) 0x4 << 2) // (EBI) 5 wait state -#define AT91C_EBI_NWS_6 ((unsigned int) 0x5 << 2) // (EBI) 6 wait state -#define AT91C_EBI_NWS_7 ((unsigned int) 0x6 << 2) // (EBI) 7 wait state -#define AT91C_EBI_NWS_8 ((unsigned int) 0x7 << 2) // (EBI) 8 wait state -#define AT91C_EBI_WSE ((unsigned int) 0x1 << 5) // (EBI) Wait State Enable -#define AT91C_EBI_PAGES ((unsigned int) 0x3 << 7) // (EBI) Pages Size -#define AT91C_EBI_PAGES_1M ((unsigned int) 0x0 << 7) // (EBI) 1M Byte -#define AT91C_EBI_PAGES_4M ((unsigned int) 0x1 << 7) // (EBI) 4M Byte -#define AT91C_EBI_PAGES_16M ((unsigned int) 0x2 << 7) // (EBI) 16M Byte -#define AT91C_EBI_PAGES_64M ((unsigned int) 0x3 << 7) // (EBI) 64M Byte -#define AT91C_EBI_TDF ((unsigned int) 0x7 << 9) // (EBI) Data Float Output Time -#define AT91C_EBI_TDF_0 ((unsigned int) 0x0 << 9) // (EBI) 1 TDF -#define AT91C_EBI_TDF_1 ((unsigned int) 0x1 << 9) // (EBI) 2 TDF -#define AT91C_EBI_TDF_2 ((unsigned int) 0x2 << 9) // (EBI) 3 TDF -#define AT91C_EBI_TDF_3 ((unsigned int) 0x3 << 9) // (EBI) 4 TDF -#define AT91C_EBI_TDF_4 ((unsigned int) 0x4 << 9) // (EBI) 5 TDF -#define AT91C_EBI_TDF_5 ((unsigned int) 0x5 << 9) // (EBI) 6 TDF -#define AT91C_EBI_TDF_6 ((unsigned int) 0x6 << 9) // (EBI) 7 TDF -#define AT91C_EBI_TDF_7 ((unsigned int) 0x7 << 9) // (EBI) 8 TDF -#define AT91C_EBI_BAT ((unsigned int) 0x1 << 12) // (EBI) Byte Access Type -#define AT91C_EBI_CSEN ((unsigned int) 0x1 << 13) // (EBI) Chip Select Enable -#define AT91C_EBI_BA ((unsigned int) 0xFFF << 20) // (EBI) Base Address -// -------- EBI_RCR : (EBI Offset: 0x20) Remap Control Register -------- -#define AT91C_EBI_RCB ((unsigned int) 0x1 << 0) // (EBI) 0 = No effect. 1 = Cancels the remapping (performed at reset) of the page zero memory devices. -// -------- EBI_MCR : (EBI Offset: 0x24) Memory Control Register -------- -#define AT91C_EBI_ALE ((unsigned int) 0x7 << 0) // (EBI) Address Line Enable -#define AT91C_EBI_ALE_16M ((unsigned int) 0x0) // (EBI) Valid Address Bits = A20, A21, A22, A23 Max Addressable Space = 16M Bytes Valid Chip Select=None -#define AT91C_EBI_ALE_8M ((unsigned int) 0x4) // (EBI) Valid Address Bits = A20, A21, A22 Max Addressable Space = 8M Bytes Valid Chip Select = CS4 -#define AT91C_EBI_ALE_4M ((unsigned int) 0x5) // (EBI) Valid Address Bits = A20, A21 Max Addressable Space = 4M Bytes Valid Chip Select = CS4, CS5 -#define AT91C_EBI_ALE_2M ((unsigned int) 0x6) // (EBI) Valid Address Bits = A20 Max Addressable Space = 2M Bytes Valid Chip Select = CS4, CS5, CS6 -#define AT91C_EBI_ALE_1M ((unsigned int) 0x7) // (EBI) Valid Address Bits = None Max Addressable Space = 1M Byte Valid Chip Select = CS4, CS5, CS6, CS7 -#define AT91C_EBI_DRP ((unsigned int) 0x1 << 4) // (EBI) - -// ***************************************************************************** -// REGISTER ADDRESS DEFINITION FOR AT91R40008 -// ***************************************************************************** -// ========== Register definition for AIC peripheral ========== -#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register -#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register -#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register -#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector egister -#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode egister -#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register -#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register -#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register -#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register -#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register -#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register -#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register -#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register -#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command egister -// ========== Register definition for WD peripheral ========== -#define AT91C_WD_SR ((AT91_REG *) 0xFFFF800C) // (WD) Status Register -#define AT91C_WD_CMR ((AT91_REG *) 0xFFFF8004) // (WD) Clock Mode Register -#define AT91C_WD_CR ((AT91_REG *) 0xFFFF8008) // (WD) Control Register -#define AT91C_WD_OMR ((AT91_REG *) 0xFFFF8000) // (WD) Overflow Mode Register -// ========== Register definition for PS peripheral ========== -#define AT91C_PS_PCDR ((AT91_REG *) 0xFFFF4008) // (PS) Peripheral Clock Disable Register -#define AT91C_PS_CR ((AT91_REG *) 0xFFFF4000) // (PS) Control Register -#define AT91C_PS_PCSR ((AT91_REG *) 0xFFFF400C) // (PS) Peripheral Clock Status Register -#define AT91C_PS_PCER ((AT91_REG *) 0xFFFF4004) // (PS) Peripheral Clock Enable Register -// ========== Register definition for PIO peripheral ========== -#define AT91C_PIO_MDSR ((AT91_REG *) 0xFFFF0058) // (PIO) Multi-driver Status Register -#define AT91C_PIO_IFSR ((AT91_REG *) 0xFFFF0028) // (PIO) Input Filter Status Register -#define AT91C_PIO_IFER ((AT91_REG *) 0xFFFF0020) // (PIO) Input Filter Enable Register -#define AT91C_PIO_OSR ((AT91_REG *) 0xFFFF0018) // (PIO) Output Status Register -#define AT91C_PIO_OER ((AT91_REG *) 0xFFFF0010) // (PIO) Output Enable Register -#define AT91C_PIO_PSR ((AT91_REG *) 0xFFFF0008) // (PIO) PIO Status Register -#define AT91C_PIO_PDSR ((AT91_REG *) 0xFFFF003C) // (PIO) Pin Data Status Register -#define AT91C_PIO_CODR ((AT91_REG *) 0xFFFF0034) // (PIO) Clear Output Data Register -#define AT91C_PIO_IFDR ((AT91_REG *) 0xFFFF0024) // (PIO) Input Filter Disable Register -#define AT91C_PIO_MDER ((AT91_REG *) 0xFFFF0050) // (PIO) Multi-driver Enable Register -#define AT91C_PIO_IMR ((AT91_REG *) 0xFFFF0048) // (PIO) Interrupt Mask Register -#define AT91C_PIO_IER ((AT91_REG *) 0xFFFF0040) // (PIO) Interrupt Enable Register -#define AT91C_PIO_ODSR ((AT91_REG *) 0xFFFF0038) // (PIO) Output Data Status Register -#define AT91C_PIO_SODR ((AT91_REG *) 0xFFFF0030) // (PIO) Set Output Data Register -#define AT91C_PIO_PER ((AT91_REG *) 0xFFFF0000) // (PIO) PIO Enable Register -#define AT91C_PIO_MDDR ((AT91_REG *) 0xFFFF0054) // (PIO) Multi-driver Disable Register -#define AT91C_PIO_ISR ((AT91_REG *) 0xFFFF004C) // (PIO) Interrupt Status Register -#define AT91C_PIO_IDR ((AT91_REG *) 0xFFFF0044) // (PIO) Interrupt Disable Register -#define AT91C_PIO_PDR ((AT91_REG *) 0xFFFF0004) // (PIO) PIO Disable Register -#define AT91C_PIO_ODR ((AT91_REG *) 0xFFFF0014) // (PIO) Output Disable Registerr -// ========== Register definition for TC2 peripheral ========== -#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFE00A8) // (TC2) Interrupt Disable Register -#define AT91C_TC2_SR ((AT91_REG *) 0xFFFE00A0) // (TC2) Status Register -#define AT91C_TC2_RB ((AT91_REG *) 0xFFFE0098) // (TC2) Register B -#define AT91C_TC2_CV ((AT91_REG *) 0xFFFE0090) // (TC2) Counter Value -#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFE0080) // (TC2) Channel Control Register -#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFE00AC) // (TC2) Interrupt Mask Register -#define AT91C_TC2_IER ((AT91_REG *) 0xFFFE00A4) // (TC2) Interrupt Enable Register -#define AT91C_TC2_RC ((AT91_REG *) 0xFFFE009C) // (TC2) Register C -#define AT91C_TC2_RA ((AT91_REG *) 0xFFFE0094) // (TC2) Register A -#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFE0084) // (TC2) Channel Mode Register -// ========== Register definition for TC1 peripheral ========== -#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFE0068) // (TC1) Interrupt Disable Register -#define AT91C_TC1_SR ((AT91_REG *) 0xFFFE0060) // (TC1) Status Register -#define AT91C_TC1_RB ((AT91_REG *) 0xFFFE0058) // (TC1) Register B -#define AT91C_TC1_CV ((AT91_REG *) 0xFFFE0050) // (TC1) Counter Value -#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFE0040) // (TC1) Channel Control Register -#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFE006C) // (TC1) Interrupt Mask Register -#define AT91C_TC1_IER ((AT91_REG *) 0xFFFE0064) // (TC1) Interrupt Enable Register -#define AT91C_TC1_RC ((AT91_REG *) 0xFFFE005C) // (TC1) Register C -#define AT91C_TC1_RA ((AT91_REG *) 0xFFFE0054) // (TC1) Register A -#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFE0044) // (TC1) Channel Mode Register -// ========== Register definition for TC0 peripheral ========== -#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFE0028) // (TC0) Interrupt Disable Register -#define AT91C_TC0_SR ((AT91_REG *) 0xFFFE0020) // (TC0) Status Register -#define AT91C_TC0_RB ((AT91_REG *) 0xFFFE0018) // (TC0) Register B -#define AT91C_TC0_CV ((AT91_REG *) 0xFFFE0010) // (TC0) Counter Value -#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFE0000) // (TC0) Channel Control Register -#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFE002C) // (TC0) Interrupt Mask Register -#define AT91C_TC0_IER ((AT91_REG *) 0xFFFE0024) // (TC0) Interrupt Enable Register -#define AT91C_TC0_RC ((AT91_REG *) 0xFFFE001C) // (TC0) Register C -#define AT91C_TC0_RA ((AT91_REG *) 0xFFFE0014) // (TC0) Register A -#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFE0004) // (TC0) Channel Mode Register -// ========== Register definition for TCB0 peripheral ========== -#define AT91C_TCB0_BCR ((AT91_REG *) 0xFFFE00C0) // (TCB0) TC Block Control Register -#define AT91C_TCB0_BMR ((AT91_REG *) 0xFFFE00C4) // (TCB0) TC Block Mode Register -// ========== Register definition for PDC_US1 peripheral ========== -#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4038) // (PDC_US1) Transmit Pointer Register -#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4030) // (PDC_US1) Receive Pointer Register -#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC403C) // (PDC_US1) Transmit Counter Register -#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4034) // (PDC_US1) Receive Counter Register -// ========== Register definition for US1 peripheral ========== -#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFCC024) // (US1) Receiver Time-out Register -#define AT91C_US1_THR ((AT91_REG *) 0xFFFCC01C) // (US1) Transmitter Holding Register -#define AT91C_US1_CSR ((AT91_REG *) 0xFFFCC014) // (US1) Channel Status Register -#define AT91C_US1_IDR ((AT91_REG *) 0xFFFCC00C) // (US1) Interrupt Disable Register -#define AT91C_US1_MR ((AT91_REG *) 0xFFFCC004) // (US1) Mode Register -#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFCC028) // (US1) Transmitter Time-guard Register -#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFCC020) // (US1) Baud Rate Generator Register -#define AT91C_US1_RHR ((AT91_REG *) 0xFFFCC018) // (US1) Receiver Holding Register -#define AT91C_US1_IMR ((AT91_REG *) 0xFFFCC010) // (US1) Interrupt Mask Register -#define AT91C_US1_IER ((AT91_REG *) 0xFFFCC008) // (US1) Interrupt Enable Register -#define AT91C_US1_CR ((AT91_REG *) 0xFFFCC000) // (US1) Control Register -// ========== Register definition for PDC_US0 peripheral ========== -#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0038) // (PDC_US0) Transmit Pointer Register -#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0030) // (PDC_US0) Receive Pointer Register -#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC003C) // (PDC_US0) Transmit Counter Register -#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0034) // (PDC_US0) Receive Counter Register -// ========== Register definition for US0 peripheral ========== -#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFD0024) // (US0) Receiver Time-out Register -#define AT91C_US0_THR ((AT91_REG *) 0xFFFD001C) // (US0) Transmitter Holding Register -#define AT91C_US0_CSR ((AT91_REG *) 0xFFFD0014) // (US0) Channel Status Register -#define AT91C_US0_IDR ((AT91_REG *) 0xFFFD000C) // (US0) Interrupt Disable Register -#define AT91C_US0_MR ((AT91_REG *) 0xFFFD0004) // (US0) Mode Register -#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFD0028) // (US0) Transmitter Time-guard Register -#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFD0020) // (US0) Baud Rate Generator Register -#define AT91C_US0_RHR ((AT91_REG *) 0xFFFD0018) // (US0) Receiver Holding Register -#define AT91C_US0_IMR ((AT91_REG *) 0xFFFD0010) // (US0) Interrupt Mask Register -#define AT91C_US0_IER ((AT91_REG *) 0xFFFD0008) // (US0) Interrupt Enable Register -#define AT91C_US0_CR ((AT91_REG *) 0xFFFD0000) // (US0) Control Register -// ========== Register definition for SF peripheral ========== -#define AT91C_SF_PMR ((AT91_REG *) 0xFFF00018) // (SF) Protect Mode Register -#define AT91C_SF_RSR ((AT91_REG *) 0xFFF00008) // (SF) Reset Status Register -#define AT91C_SF_CIDR ((AT91_REG *) 0xFFF00000) // (SF) Chip ID Register -#define AT91C_SF_MMR ((AT91_REG *) 0xFFF0000C) // (SF) Memory Mode Register -#define AT91C_SF_EXID ((AT91_REG *) 0xFFF00004) // (SF) Chip ID Extension Register -// ========== Register definition for EBI peripheral ========== -#define AT91C_EBI_RCR ((AT91_REG *) 0xFFE00020) // (EBI) Remap Control Register -#define AT91C_EBI_CSR ((AT91_REG *) 0xFFE00000) // (EBI) Chip-select Register -#define AT91C_EBI_MCR ((AT91_REG *) 0xFFE00024) // (EBI) Memory Control Register - -// ***************************************************************************** -// PIO DEFINITIONS FOR AT91R40008 -// ***************************************************************************** -#define AT91C_PIO_P0 ((unsigned int) 1 << 0) // Pin Controlled by P0 -#define AT91C_P0_TCLK0 ((unsigned int) AT91C_PIO_P0) // Timer 0 Clock signal -#define AT91C_PIO_P1 ((unsigned int) 1 << 1) // Pin Controlled by P1 -#define AT91C_P1_TIOA0 ((unsigned int) AT91C_PIO_P1) // Timer 0 Signal A -#define AT91C_PIO_P10 ((unsigned int) 1 << 10) // Pin Controlled by P10 -#define AT91C_P10_IRQ1 ((unsigned int) AT91C_PIO_P10) // External Interrupt 1 -#define AT91C_PIO_P11 ((unsigned int) 1 << 11) // Pin Controlled by P11 -#define AT91C_P11_IRQ2 ((unsigned int) AT91C_PIO_P11) // External Interrupt 2 -#define AT91C_PIO_P12 ((unsigned int) 1 << 12) // Pin Controlled by P12 -#define AT91C_P12_FIQ ((unsigned int) AT91C_PIO_P12) // Fast External Interrupt -#define AT91C_PIO_P13 ((unsigned int) 1 << 13) // Pin Controlled by P13 -#define AT91C_P13_SCK0 ((unsigned int) AT91C_PIO_P13) // USART 0 Serial Clock -#define AT91C_PIO_P14 ((unsigned int) 1 << 14) // Pin Controlled by P14 -#define AT91C_P14_TXD0 ((unsigned int) AT91C_PIO_P14) // USART 0 Transmit Data -#define AT91C_PIO_P15 ((unsigned int) 1 << 15) // Pin Controlled by P15 -#define AT91C_P15_RXD0 ((unsigned int) AT91C_PIO_P15) // USART 0 Receive Data -#define AT91C_PIO_P16 ((unsigned int) 1 << 16) // Pin Controlled by P16 -#define AT91C_PIO_P17 ((unsigned int) 1 << 17) // Pin Controlled by P17 -#define AT91C_PIO_P18 ((unsigned int) 1 << 18) // Pin Controlled by P18 -#define AT91C_PIO_P19 ((unsigned int) 1 << 19) // Pin Controlled by P19 -#define AT91C_PIO_P2 ((unsigned int) 1 << 2) // Pin Controlled by P2 -#define AT91C_P2_TIOB0 ((unsigned int) AT91C_PIO_P2) // Timer 0 Signal B -#define AT91C_PIO_P20 ((unsigned int) 1 << 20) // Pin Controlled by P20 -#define AT91C_P20_SCK1 ((unsigned int) AT91C_PIO_P20) // USART 1 Serial Clock -#define AT91C_PIO_P21 ((unsigned int) 1 << 21) // Pin Controlled by P21 -#define AT91C_P21_TXD1 ((unsigned int) AT91C_PIO_P21) // USART 1 Transmit Data -#define AT91C_P21_NTRI ((unsigned int) AT91C_PIO_P21) // Tri-state Mode -#define AT91C_PIO_P22 ((unsigned int) 1 << 22) // Pin Controlled by P22 -#define AT91C_P22_RXD1 ((unsigned int) AT91C_PIO_P22) // USART 1 Receive Data -#define AT91C_PIO_P23 ((unsigned int) 1 << 23) // Pin Controlled by P23 -#define AT91C_PIO_P24 ((unsigned int) 1 << 24) // Pin Controlled by P24 -#define AT91C_P24_BMS ((unsigned int) AT91C_PIO_P24) // Boot Mode Select -#define AT91C_PIO_P25 ((unsigned int) 1 << 25) // Pin Controlled by P25 -#define AT91C_P25_MCKO ((unsigned int) AT91C_PIO_P25) // Master Clock Out -#define AT91C_PIO_P26 ((unsigned int) 1 << 26) // Pin Controlled by P26 -#define AT91C_P26_NCS2 ((unsigned int) AT91C_PIO_P26) // Chip Select 2 -#define AT91C_PIO_P27 ((unsigned int) 1 << 27) // Pin Controlled by P27 -#define AT91C_P27_NCS3 ((unsigned int) AT91C_PIO_P27) // Chip Select 3 -#define AT91C_PIO_P28 ((unsigned int) 1 << 28) // Pin Controlled by P28 -#define AT91C_P28_A20 ((unsigned int) AT91C_PIO_P28) // Address line A20 -#define AT91C_P28_NCS7 ((unsigned int) AT91C_PIO_P28) // Chip Select 7 -#define AT91C_PIO_P29 ((unsigned int) 1 << 29) // Pin Controlled by P29 -#define AT91C_P29_A21 ((unsigned int) AT91C_PIO_P29) // Address line A21 -#define AT91C_P29_NCS6 ((unsigned int) AT91C_PIO_P29) // Chip Select 6 -#define AT91C_PIO_P3 ((unsigned int) 1 << 3) // Pin Controlled by P3 -#define AT91C_P3_TCLK1 ((unsigned int) AT91C_PIO_P3) // Timer 1 Clock signal -#define AT91C_PIO_P30 ((unsigned int) 1 << 30) // Pin Controlled by P30 -#define AT91C_P30_A22 ((unsigned int) AT91C_PIO_P30) // Address line A22 -#define AT91C_P30_NCS5 ((unsigned int) AT91C_PIO_P30) // Chip Select 5 -#define AT91C_PIO_P31 ((unsigned int) 1 << 31) // Pin Controlled by P31 -#define AT91C_P31_A23 ((unsigned int) AT91C_PIO_P31) // Address line A23 -#define AT91C_P31_NCS4 ((unsigned int) AT91C_PIO_P31) // Chip Select 4 -#define AT91C_PIO_P4 ((unsigned int) 1 << 4) // Pin Controlled by P4 -#define AT91C_P4_TIOA1 ((unsigned int) AT91C_PIO_P4) // Timer 1 Signal A -#define AT91C_PIO_P5 ((unsigned int) 1 << 5) // Pin Controlled by P5 -#define AT91C_P5_TIOB1 ((unsigned int) AT91C_PIO_P5) // Timer 1 Signal B -#define AT91C_PIO_P6 ((unsigned int) 1 << 6) // Pin Controlled by P6 -#define AT91C_P6_TCLK2 ((unsigned int) AT91C_PIO_P6) // Timer 2 Clock signal -#define AT91C_PIO_P7 ((unsigned int) 1 << 7) // Pin Controlled by P7 -#define AT91C_P7_TIOA2 ((unsigned int) AT91C_PIO_P7) // Timer 2 Signal A -#define AT91C_PIO_P8 ((unsigned int) 1 << 8) // Pin Controlled by P8 -#define AT91C_P8_TIOB2 ((unsigned int) AT91C_PIO_P8) // Timer 2 Signal B -#define AT91C_PIO_P9 ((unsigned int) 1 << 9) // Pin Controlled by P9 -#define AT91C_P9_IRQ0 ((unsigned int) AT91C_PIO_P9) // External Interrupt 0 - -// ***************************************************************************** -// PERIPHERAL ID DEFINITIONS FOR AT91R40008 -// ***************************************************************************** -#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) -#define AT91C_ID_SYS ((unsigned int) 1) // SWI -#define AT91C_ID_US0 ((unsigned int) 2) // USART 0 -#define AT91C_ID_US1 ((unsigned int) 3) // USART 1 -#define AT91C_ID_TC0 ((unsigned int) 4) // Timer Counter 0 -#define AT91C_ID_TC1 ((unsigned int) 5) // Timer Counter 1 -#define AT91C_ID_TC2 ((unsigned int) 6) // Timer Counter 2 -#define AT91C_ID_WD ((unsigned int) 7) // Watchdog Timer -#define AT91C_ID_PIO ((unsigned int) 8) // Parallel IO Controller -#define AT91C_ID_IRQ0 ((unsigned int) 16) // Advanced Interrupt Controller (IRQ0) -#define AT91C_ID_IRQ1 ((unsigned int) 17) // Advanced Interrupt Controller (IRQ1) -#define AT91C_ID_IRQ2 ((unsigned int) 18) // Advanced Interrupt Controller (IRQ2) - -// ***************************************************************************** -// BASE ADDRESS DEFINITIONS FOR AT91R40008 -// ***************************************************************************** -#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address -#define AT91C_BASE_WD ((AT91PS_WD) 0xFFFF8000) // (WD) Base Address -#define AT91C_BASE_PS ((AT91PS_PS) 0xFFFF4000) // (PS) Base Address -#define AT91C_BASE_PIO ((AT91PS_PIO) 0xFFFF0000) // (PIO) Base Address -#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFE0080) // (TC2) Base Address -#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFE0040) // (TC1) Base Address -#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFE0000) // (TC0) Base Address -#define AT91C_BASE_TCB0 ((AT91PS_TCB) 0xFFFE0000) // (TCB0) Base Address -#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4030) // (PDC_US1) Base Address -#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFCC000) // (US1) Base Address -#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0030) // (PDC_US0) Base Address -#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFD0000) // (US0) Base Address -#define AT91C_BASE_SF ((AT91PS_SF) 0xFFF00000) // (SF) Base Address -#define AT91C_BASE_EBI ((AT91PS_EBI) 0xFFE00000) // (EBI) Base Address - -// ***************************************************************************** -// MEMORY MAPPING DEFINITIONS FOR AT91R40008 -// ***************************************************************************** -#define AT91C_SRAM_BEFORE_REMAP ((char *) 0x00300000) // Internal SRAM before remap base address -#define AT91C_SRAM_BEFORE_REMAP_SIZE ((unsigned int) 0x00040000) // Internal SRAM before remap size in byte (256 Kbyte) -#define AT91C_SRAM_AFTER_REMAP ((char *) 0x00000000) // Internal SRAM after remap base address -#define AT91C_SRAM_AFTER_REMAP_SIZE ((unsigned int) 0x00040000) // Internal SRAM after remap size in byte (256 Kbyte) - -#endif diff --git a/Demo/ARM7_AT91FR40008_GCC/ATEB40x.cfg b/Demo/ARM7_AT91FR40008_GCC/ATEB40x.cfg deleted file mode 100644 index 756339f29..000000000 --- a/Demo/ARM7_AT91FR40008_GCC/ATEB40x.cfg +++ /dev/null @@ -1,24 +0,0 @@ -[SETUP] -CpuVendor=Atmel -CpuChip=AT91R40807 -FlashVendor=Atmel -FlashChip=AT49BV/F1614A -RamAddress=$00000000 -RamSupport=1 -FlashAddress=$01000000 -FlashWidth=16 -FlashChipsPerSector=1 -LittleEndian=0 -SectStart=0 -SectEnd=38 -AutoErase=0 -AutoVerify=1 -CpuEndian=LITTLE -SimCount=3 -MemoryCount=0 -ProgramFile=E:\temp\embesttest\Demo\ARM7_AT91R40008_GCC_Embest\rtosdemo.hex -UploadFile=c:\EB40_Lower.bin -Format=Intel Hex -Sim3=EBI_RCR:$00000001 -Sim2=EBI_CSR1:$02002122 -Sim1=EBI_CSR0:$01002539 diff --git a/Demo/ARM7_AT91FR40008_GCC/FreeRTOSConfig.h b/Demo/ARM7_AT91FR40008_GCC/FreeRTOSConfig.h deleted file mode 100644 index 1744f473f..000000000 --- a/Demo/ARM7_AT91FR40008_GCC/FreeRTOSConfig.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -#include - -#define configFLASH_SPEED_NSEC 100 /* External flash access speed (for ROM builds) */ - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 66000000 ) /* = 66.000MHz clk gen */ -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 25 * 1024 ) ) -#define configMAX_TASK_NAME_LEN ( 16 ) -#define configUSE_TRACE_FACILITY 0 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 1 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/ARM7_AT91FR40008_GCC/Makefile b/Demo/ARM7_AT91FR40008_GCC/Makefile deleted file mode 100644 index 5070e5172..000000000 --- a/Demo/ARM7_AT91FR40008_GCC/Makefile +++ /dev/null @@ -1,99 +0,0 @@ -# FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. -# -# This file is part of the FreeRTOS.org distribution. -# -# FreeRTOS.org is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# FreeRTOS.org is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with FreeRTOS.org; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -# -# A special exception to the GPL can be applied should you wish to distribute -# a combined work that includes FreeRTOS.org, without being obliged to provide -# the source code for any proprietary components. See the licensing section -# of http://www.FreeRTOS.org for full details of how and when the exception -# can be applied. -# -# *************************************************************************** -# See http://www.FreeRTOS.org for documentation, latest information, license -# and contact details. Please ensure to read the configuration and relevant -# port sections of the online documentation. -# *************************************************************************** - -CC=arm-elf-gcc -OBJCOPY=arm-elf-objcopy -ARCH=arm-elf-ar -CRT0=boot.s - -# -# CFLAGS common to both the THUMB and ARM mode builds -# -CFLAGS=-Wall -D $(RUN_MODE) -D GCC_AT91FR40008 -I. -I../../Source/include \ - -I../Common/include $(DEBUG) -mcpu=arm7tdmi -T$(LDSCRIPT) \ - -Wcast-align $(OPTIM) -fomit-frame-pointer - -ifeq ($(USE_THUMB_MODE),YES) - CFLAGS += -mthumb-interwork -D THUMB_INTERWORK - THUMB_FLAGS=-mthumb -endif - - -LINKER_FLAGS=-Xlinker -ortosdemo.elf -Xlinker -M -Xlinker -Map=rtosdemo.map - -# -# Source files that can be built to THUMB mode. -# -THUMB_SRC = \ -main.c \ -serial/serial.c \ -ParTest/ParTest.c \ -../Common/Minimal/integer.c \ -../Common/Minimal/flash.c \ -../Common/Minimal/PollQ.c \ -../Common/Minimal/comtest.c \ -../Common/Minimal/flop.c \ -../Common/Minimal/semtest.c \ -../Common/Minimal/dynamic.c \ -../Common/Minimal/BlockQ.c \ -../../Source/tasks.c \ -../../Source/queue.c \ -../../Source/list.c \ -../../Source/portable/MemMang/heap_2.c \ -../../Source/portable/GCC/ARM7_AT91FR40008/port.c - -# -# Source files that must be built to ARM mode. -# -ARM_SRC = \ -../../Source/portable/GCC/ARM7_AT91FR40008/portISR.c \ -serial/serialISR.c - -# -# Define all object files. -# -ARM_OBJ = $(ARM_SRC:.c=.o) -THUMB_OBJ = $(THUMB_SRC:.c=.o) - -rtosdemo.hex : rtosdemo.elf - $(OBJCOPY) rtosdemo.elf -O ihex rtosdemo.hex - -rtosdemo.elf : $(ARM_OBJ) $(THUMB_OBJ) $(CRT0) Makefile - $(CC) $(CFLAGS) $(ARM_OBJ) $(THUMB_OBJ) -nostartfiles $(CRT0) $(LINKER_FLAGS) - -$(THUMB_OBJ) : %.o : %.c $(LDSCRIPT) Makefile - $(CC) -c $(THUMB_FLAGS) $(CFLAGS) $< -o $@ - -$(ARM_OBJ) : %.o : %.c $(LDSCRIPT) Makefile - $(CC) -c $(CFLAGS) $< -o $@ - -clean : - touch Makefile - diff --git a/Demo/ARM7_AT91FR40008_GCC/ParTest/ParTest.c b/Demo/ARM7_AT91FR40008_GCC/ParTest/ParTest.c deleted file mode 100644 index 60d7b208e..000000000 --- a/Demo/ARM7_AT91FR40008_GCC/ParTest/ParTest.c +++ /dev/null @@ -1,120 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "portable.h" - -/* Demo app includes. */ -#include "partest.h" - -/* Hardware specific definitions. */ -#include "AT91R40008.h" -#include "pio.h" -#include "aic.h" - -#define partstNUM_LEDS ( 8 ) -#define partstALL_OUTPUTS_OFF ( ( unsigned portLONG ) ~(0xFFFFFFFF << partstNUM_LEDS) ) - -static unsigned portLONG ulLEDReg; - -/*----------------------------------------------------------- - * Simple parallel port IO routines. - *-----------------------------------------------------------*/ - -static void SetLeds (unsigned int leds) -{ -unsigned portLONG ulPIOSetReg, ulPIOClearReg; - - /* LEDs are grouped in different port bits: P3-P6 and P16-P19. - A port bit set to '0' turns an LED on, '1' turns it off. */ - - ulPIOSetReg = ( (leds & 0xF) << 16 ) | ( (leds & 0xF0) >> 1 ); - ulPIOClearReg = (~ulPIOSetReg) & 0x000F0078; - - AT91C_BASE_PIO->PIO_SODR = ulPIOSetReg; - AT91C_BASE_PIO->PIO_CODR = ulPIOClearReg; -} -/*-----------------------------------------------------------*/ - -void vParTestInitialise( void ) -{ - /* This is performed from main() as the io bits are shared with other setup - functions. Ensure the outputs are off to start. */ - ulLEDReg = partstALL_OUTPUTS_OFF; - - /* Enable clock to PIO... */ - AT91C_BASE_PS->PS_PCER = AT91C_PS_PIO; - - /* Enable all 8 LEDs and the four switches to be controlled by PIO... */ - AT91C_BASE_PIO->PIO_PER = P3 | P4 | P5 | P6 | P16 | P17 | P18 | P19 | P1 | P2 | P9 | P12; - - /* Configure all LED PIO lines for output... */ - AT91C_BASE_PIO->PIO_OER = P3 | P4 | P5 | P6 | P16 | P17 | P18 | P19; - - /* Configure all switch PIO lines for input... */ - AT91C_BASE_PIO->PIO_ODR = P1 | P2 | P9 | P12; - - /* Set initial state of LEDs. */ - SetLeds( ulLEDReg ); -} -/*-----------------------------------------------------------*/ - -void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) -{ - /* Switch an LED on or off as requested. */ - if (uxLED < partstNUM_LEDS) - { - if( xValue ) - { - ulLEDReg &= ~(1 << uxLED); - } - else - { - ulLEDReg |= (1 << uxLED); - } - - SetLeds( ulLEDReg ); - } -} -/*-----------------------------------------------------------*/ - -void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) -{ - /* Toggle the state of the requested LED. */ - if (uxLED < partstNUM_LEDS) - { - ulLEDReg ^= ( 1 << uxLED ); - SetLeds( ulLEDReg ); - } -} - diff --git a/Demo/ARM7_AT91FR40008_GCC/aic.h b/Demo/ARM7_AT91FR40008_GCC/aic.h deleted file mode 100644 index 82df09078..000000000 --- a/Demo/ARM7_AT91FR40008_GCC/aic.h +++ /dev/null @@ -1,81 +0,0 @@ -//*---------------------------------------------------------------------------- -//* ATMEL Microcontroller Software Support - ROUSSET - -//*---------------------------------------------------------------------------- -//* The software is delivered "AS IS" without warranty or condition of any -//* kind, either express, implied or statutory. This includes without -//* limitation any warranty or condition with respect to merchantability or -//* fitness for any particular purpose, or against the infringements of -//* intellectual property rights of others. -//*---------------------------------------------------------------------------- -//* File Name : aic.h -//* Object : Advanced Interrupt Controller Definition File. -//* -//* 1.0 01/04/00 JCZ : Creation -//*---------------------------------------------------------------------------- - -#ifndef aic_h -#define aic_h - -//#include "periph/stdc/std_c.h" - -/*-----------------------------------------*/ -/* AIC User Interface Structure Definition */ -/*-----------------------------------------*/ - -typedef struct -{ - at91_reg AIC_SMR[32] ; /* Source Mode Register */ - at91_reg AIC_SVR[32] ; /* Source Vector Register */ - at91_reg AIC_IVR ; /* IRQ Vector Register */ - at91_reg AIC_FVR ; /* FIQ Vector Register */ - at91_reg AIC_ISR ; /* Interrupt Status Register */ - at91_reg AIC_IPR ; /* Interrupt Pending Register */ - at91_reg AIC_IMR ; /* Interrupt Mask Register */ - at91_reg AIC_CISR ; /* Core Interrupt Status Register */ - at91_reg reserved0 ; - at91_reg reserved1 ; - at91_reg AIC_IECR ; /* Interrupt Enable Command Register */ - at91_reg AIC_IDCR ; /* Interrupt Disable Command Register */ - at91_reg AIC_ICCR ; /* Interrupt Clear Command Register */ - at91_reg AIC_ISCR ; /* Interrupt Set Command Register */ - at91_reg AIC_EOICR ; /* End of Interrupt Command Register */ - at91_reg AIC_SPU ; /* Spurious Vector Register */ -} StructAIC ; - -/*--------------------------------------------*/ -/* AIC_SMR[]: Interrupt Source Mode Registers */ -/*--------------------------------------------*/ - -#define AIC_PRIOR 0x07 /* Priority */ - -#define AIC_SRCTYPE 0x60 /* Source Type Definition */ - -/* Internal Interrupts */ -#define AIC_SRCTYPE_INT_LEVEL_SENSITIVE 0x00 /* Level Sensitive */ -#define AIC_SRCTYPE_INT_EDGE_TRIGGERED 0x20 /* Edge Triggered */ - -/* External Interrupts */ -#define AIC_SRCTYPE_EXT_LOW_LEVEL 0x00 /* Low Level */ -#define AIC_SRCTYPE_EXT_NEGATIVE_EDGE 0x20 /* Negative Edge */ -#define AIC_SRCTYPE_EXT_HIGH_LEVEL 0x40 /* High Level */ -#define AIC_SRCTYPE_EXT_POSITIVE_EDGE 0x60 /* Positive Edge */ - -/*------------------------------------*/ -/* AIC_ISR: Interrupt Status Register */ -/*------------------------------------*/ - -#define AIC_IRQID 0x1F /* Current source interrupt */ - -/*------------------------------------------*/ -/* AIC_CISR: Interrupt Core Status Register */ -/*------------------------------------------*/ - -#define AIC_NFIQ 0x01 /* Core FIQ Status */ -#define AIC_NIRQ 0x02 /* Core IRQ Status */ - -/*-------------------------------*/ -/* Advanced Interrupt Controller */ -/*-------------------------------*/ -#define AIC_BASE ((StructAIC *)0xFFFFF000) - -#endif /* aic_h */ diff --git a/Demo/ARM7_AT91FR40008_GCC/atmel-ram.ld b/Demo/ARM7_AT91FR40008_GCC/atmel-ram.ld deleted file mode 100644 index 692202661..000000000 --- a/Demo/ARM7_AT91FR40008_GCC/atmel-ram.ld +++ /dev/null @@ -1,48 +0,0 @@ -MEMORY -{ - ram : ORIGIN = 0x00000000, LENGTH = 256K -} - -__stack_end__ = 0x00000000 + 256K - 4; - -SECTIONS -{ - . = 0; - startup : { *(.startup)} >ram - - prog : - { - *(.text) - *(.rodata) - *(.rodata*) - *(.glue_7) - *(.glue_7t) - } >ram - - __end_of_text__ = .; - - .data : - { - __data_beg__ = .; - __data_beg_src__ = __end_of_text__; - *(.data) - __data_end__ = .; - } >ram - - .bss : - { - __bss_beg__ = .; - *(.bss) - } >ram - - /* Align here to ensure that the .bss section occupies space up to - _end. Align after .bss to ensure correct alignment even if the - .bss section disappears because there are no input sections. */ - . = ALIGN(32 / 8); -} - . = ALIGN(32 / 8); - _end = .; - _bss_end__ = . ; __bss_end__ = . ; __end__ = . ; - PROVIDE (end = .); - - diff --git a/Demo/ARM7_AT91FR40008_GCC/atmel-rom.ld b/Demo/ARM7_AT91FR40008_GCC/atmel-rom.ld deleted file mode 100644 index 35578fd96..000000000 --- a/Demo/ARM7_AT91FR40008_GCC/atmel-rom.ld +++ /dev/null @@ -1,49 +0,0 @@ -MEMORY -{ - flash : ORIGIN = 0x00000000, LENGTH = 2048K - ram : ORIGIN = 0x00300000, LENGTH = 256K -} - -__stack_end__ = 0x00300000 + 256K - 4; - -SECTIONS -{ - . = 0; - startup : { *(.startup)} >flash - - prog : - { - *(.text) - *(.rodata) - *(.rodata*) - *(.glue_7) - *(.glue_7t) - } >flash - - __end_of_text__ = .; - - .data : - { - __data_beg__ = .; - __data_beg_src__ = __end_of_text__; - *(.data) - __data_end__ = .; - } >ram AT>flash - - .bss : - { - __bss_beg__ = .; - *(.bss) - } >ram - - /* Align here to ensure that the .bss section occupies space up to - _end. Align after .bss to ensure correct alignment even if the - .bss section disappears because there are no input sections. */ - . = ALIGN(32 / 8); -} - . = ALIGN(32 / 8); - _end = .; - _bss_end__ = . ; __bss_end__ = . ; __end__ = . ; - PROVIDE (end = .); - - diff --git a/Demo/ARM7_AT91FR40008_GCC/boot.s b/Demo/ARM7_AT91FR40008_GCC/boot.s deleted file mode 100644 index 5947d158f..000000000 --- a/Demo/ARM7_AT91FR40008_GCC/boot.s +++ /dev/null @@ -1,157 +0,0 @@ - /* Sample initialization file */ - - .extern main - .extern exit - - .text - .code 32 - - - .align 0 - - .extern __bss_beg__ - .extern __bss_end__ - .extern __stack_end__ - .extern __data_beg__ - .extern __data_end__ - .extern __data+beg_src__ - - .global start - .global endless_loop - - /* Stack Sizes */ - .set UND_STACK_SIZE, 0x00000004 - .set ABT_STACK_SIZE, 0x00000004 - .set FIQ_STACK_SIZE, 0x00000004 - .set IRQ_STACK_SIZE, 0X00000400 - .set SVC_STACK_SIZE, 0x00000400 - - /* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */ - .set MODE_USR, 0x10 /* User Mode */ - .set MODE_FIQ, 0x11 /* FIQ Mode */ - .set MODE_IRQ, 0x12 /* IRQ Mode */ - .set MODE_SVC, 0x13 /* Supervisor Mode */ - .set MODE_ABT, 0x17 /* Abort Mode */ - .set MODE_UND, 0x1B /* Undefined Mode */ - .set MODE_SYS, 0x1F /* System Mode */ - - .equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */ - .equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */ - - -start: -_start: -_mainCRTStartup: - - /* Setup a stack for each mode - note that this only sets up a usable stack - for system/user, SWI and IRQ modes. Also each mode is setup with - interrupts initially disabled. */ - ldr r0, .LC6 - msr CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode */ - mov sp, r0 - sub r0, r0, #UND_STACK_SIZE - msr CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */ - mov sp, r0 - sub r0, r0, #ABT_STACK_SIZE - msr CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */ - mov sp, r0 - sub r0, r0, #FIQ_STACK_SIZE - msr CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */ - mov sp, r0 - sub r0, r0, #IRQ_STACK_SIZE - msr CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */ - mov sp, r0 - sub r0, r0, #SVC_STACK_SIZE - msr CPSR_c, #MODE_SYS|I_BIT|F_BIT /* System Mode */ - mov sp, r0 - - /* We want to start in supervisor mode. Operation will switch to system - mode when the first task starts. */ - msr CPSR_c, #MODE_SVC|I_BIT|F_BIT - - /* Clear BSS. */ - - mov a2, #0 /* Fill value */ - mov fp, a2 /* Null frame pointer */ - mov r7, a2 /* Null frame pointer for Thumb */ - - ldr r1, .LC1 /* Start of memory block */ - ldr r3, .LC2 /* End of memory block */ - subs r3, r3, r1 /* Length of block */ - beq .end_clear_loop - mov r2, #0 - -.clear_loop: - strb r2, [r1], #1 - subs r3, r3, #1 - bgt .clear_loop - -.end_clear_loop: - - /* Initialise data. */ - - ldr r1, .LC3 /* Start of memory block */ - ldr r2, .LC4 /* End of memory block */ - ldr r3, .LC5 - subs r3, r3, r1 /* Length of block */ - beq .end_set_loop - -.set_loop: - ldrb r4, [r2], #1 - strb r4, [r1], #1 - subs r3, r3, #1 - bgt .set_loop - -.end_set_loop: - - mov r0, #0 /* no arguments */ - mov r1, #0 /* no argv either */ - - bl main - -endless_loop: - b endless_loop - - - .align 0 - - .LC1: - .word __bss_beg__ - .LC2: - .word __bss_end__ - .LC3: - .word __data_beg__ - .LC4: - .word __data_beg_src__ - .LC5: - .word __data_end__ - .LC6: - .word __stack_end__ - - - /* Setup vector table. Note that undf, pabt, dabt, fiq just execute - a null loop. */ - -.section .startup,"ax" - .code 32 - .align 0 - - b _start /* reset - _start */ - ldr pc, _undf /* undefined - _undf */ - ldr pc, _swi /* SWI - _swi */ - ldr pc, _pabt /* program abort - _pabt */ - ldr pc, _dabt /* data abort - _dabt */ - nop /* reserved */ - ldr pc, [pc,#-0xF20] /* IRQ - read the AIC */ - ldr pc, _fiq /* FIQ - _fiq */ - -_undf: .word __undf /* undefined */ -_swi: .word vPortYieldProcessor /* SWI */ -_pabt: .word __pabt /* program abort */ -_dabt: .word __dabt /* data abort */ -_fiq: .word __fiq /* FIQ */ - -__undf: b . /* undefined */ -__pabt: b . /* program abort */ -__dabt: b . /* data abort */ -__fiq: b . /* FIQ */ diff --git a/Demo/ARM7_AT91FR40008_GCC/ebi.h b/Demo/ARM7_AT91FR40008_GCC/ebi.h deleted file mode 100644 index 62c36f0ad..000000000 --- a/Demo/ARM7_AT91FR40008_GCC/ebi.h +++ /dev/null @@ -1,121 +0,0 @@ -//*----------------------------------------------------------------------------- -//* ATMEL Microcontroller Software Support - ROUSSET - -//*----------------------------------------------------------------------------- -//* The software is delivered "AS IS" without warranty or condition of any -//* kind, either express, implied or statutory. This includes without -//* limitation any warranty or condition with respect to merchantability or -//* fitness for any particular purpose, or against the infringements of -//* intellectual property rights of others. -//*----------------------------------------------------------------------------- -//* File Name : ebi.h -//* Object : External Bus Interface Definition File -//* Translator : ARM Software Development Toolkit V2.11a -//* -//* 1.0 03/11/97 JCZ : Creation -//* 2.0 21/10/98 JCZ : Clean up -//*----------------------------------------------------------------------------- - -#ifndef ebi_h -#define ebi_h - -/*----------------------------------------*/ -/* Memory Controller Interface Definition */ -/*----------------------------------------*/ - -typedef struct -{ - at91_reg EBI_CSR[8] ; /* Chip Select Register */ - at91_reg EBI_RCR ; /* Remap Control Register */ - at91_reg EBI_MCR ; /* Memory Control Register */ -} StructEBI ; - -/*-----------------------*/ -/* Chip Select Registers */ -/*-----------------------*/ - -/* Data Bus Width */ -#define DataBus16 (1<<0) -#define DataBus8 (2<<0) -#define DBW (3<<0) - -/* Number of Wait States */ -#define B_NWS 2 -#define WaitState1 (0< -#include - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Demo application includes. */ -#include "partest.h" -#include "flash.h" -#include "integer.h" -#include "PollQ.h" -#include "comtest2.h" -#include "semtest.h" -#include "flop.h" -#include "dynamic.h" -#include "BlockQ.h" -#include "serial.h" - -/* Hardware specific definitions. */ -#include "aic.h" -#include "ebi.h" - -/*-----------------------------------------------------------*/ - -/* Constants for the ComTest tasks. */ -#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 115200 ) -#define mainCOM_TEST_LED ( 5 ) - -/* Priorities for the demo application tasks. */ -#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) - -/* The rate at which the on board LED will toggle when there is/is not an -error. */ -#define mainNO_ERROR_FLASH_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS ) -#define mainERROR_FLASH_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS ) -#define mainON_BOARD_LED_BIT ( ( unsigned portLONG ) 7 ) - -/* Constants used by the vMemCheckTask() task. */ -#define mainCOUNT_INITIAL_VALUE ( ( unsigned portLONG ) 0 ) -#define mainNO_TASK ( 0 ) - -/* The size of the memory blocks allocated by the vMemCheckTask() task. */ -#define mainMEM_CHECK_SIZE_1 ( ( size_t ) 51 ) -#define mainMEM_CHECK_SIZE_2 ( ( size_t ) 52 ) -#define mainMEM_CHECK_SIZE_3 ( ( size_t ) 151 ) - -#define MAX_WAIT_STATES 8 -static const unsigned portLONG ululCSRWaitValues[ MAX_WAIT_STATES + 1 ] = -{ - WaitState1,/* There is no "zero wait state" value, so use one wait state */ - WaitState1, - WaitState2, - WaitState3, - WaitState4, - WaitState5, - WaitState6, - WaitState7, - WaitState8 -}; -/*-----------------------------------------------------------*/ - -/* - * Checks that all the demo application tasks are still executing without error - * - as described at the top of the file. - */ -static portLONG prvCheckOtherTasksAreStillRunning( unsigned portLONG ulMemCheckTaskCount ); - -/* - * The task that executes at the highest priority and calls - * prvCheckOtherTasksAreStillRunning(). See the description at the top - * of the file. - */ -static void vErrorChecks( void *pvParameters ); - -/* - * Dynamically created and deleted during each cycle of the vErrorChecks() - * task. This is done to check the operation of the memory allocator. - * See the top of vErrorChecks for more details. - */ -static void vMemCheckTask( void *pvParameters ); - -/* - * Configure the processor for use with the Olimex demo board. This includes - * setup for the I/O, system clock, and access timings. - */ -static void prvSetupHardware( void ); - -/*-----------------------------------------------------------*/ - -/* - * Starts all the other tasks, then starts the scheduler. - */ -int main( void ) -{ - /* Setup the hardware for use with the Olimex demo board. */ - prvSetupHardware(); - - /* Start the demo/test application tasks. */ - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); - vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartMathTasks( tskIDLE_PRIORITY ); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartDynamicPriorityTasks(); - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - - /* Start the check task - which is defined in this file. */ - xTaskCreate( vErrorChecks, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - - /* Now all the tasks have been started - start the scheduler. - - NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. - The processor MUST be in supervisor mode when vTaskStartScheduler is - called. The demo applications included in the FreeRTOS.org download switch - to supervisor mode prior to main being called. If you are not using one of - these demo application projects then ensure Supervisor mode is used here. */ - vTaskStartScheduler(); - - /* Should never reach here! */ - return 0; -} -/*-----------------------------------------------------------*/ - -static void vErrorChecks( void *pvParameters ) -{ -portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD; -unsigned portLONG ulMemCheckTaskRunningCount; -xTaskHandle xCreatedTask; - - /* Cycle for ever, delaying then checking all the other tasks are still - operating without error. If an error is detected then the delay period - is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so - the on board LED flash rate will increase. - - In addition to the standard tests the memory allocator is tested through - the dynamic creation and deletion of a task each cycle. Each time the - task is created memory must be allocated for its stack. When the task is - deleted this memory is returned to the heap. If the task cannot be created - then it is likely that the memory allocation failed. */ - - for( ;; ) - { - /* Reset xCreatedTask. This is modified by the task about to be - created so we can tell if it is executing correctly or not. */ - xCreatedTask = mainNO_TASK; - - /* Dynamically create a task - passing ulMemCheckTaskRunningCount as a - parameter. */ - ulMemCheckTaskRunningCount = mainCOUNT_INITIAL_VALUE; - if( xTaskCreate( vMemCheckTask, ( signed portCHAR * ) "MEM_CHECK", configMINIMAL_STACK_SIZE, ( void * ) &ulMemCheckTaskRunningCount, tskIDLE_PRIORITY, &xCreatedTask ) != pdPASS ) - { - /* Could not create the task - we have probably run out of heap. */ - xDelayPeriod = mainERROR_FLASH_PERIOD; - } - - /* Delay until it is time to execute again. */ - vTaskDelay( xDelayPeriod ); - - /* Delete the dynamically created task. */ - if( xCreatedTask != mainNO_TASK ) - { - vTaskDelete( xCreatedTask ); - } - - /* Check all the standard demo application tasks are executing without - error. ulMemCheckTaskRunningCount is checked to ensure it was - modified by the task just deleted. */ - if( prvCheckOtherTasksAreStillRunning( ulMemCheckTaskRunningCount ) != pdPASS ) - { - /* An error has been detected in one of the tasks - flash faster. */ - xDelayPeriod = mainERROR_FLASH_PERIOD; - } - - /* The toggle rate of the LED depends on how long this task delays for. - An error reduces the delay period and so increases the toggle rate. */ - vParTestToggleLED( mainON_BOARD_LED_BIT ); - } -} -/*-----------------------------------------------------------*/ - -static void prvSetupHardware( void ) -{ -portLONG lCount; - - #ifdef RUN_FROM_ROM - { - portFLOAT nsecsPerClockTick; - portLONG lNumWaitStates; - unsigned portLONG ulCSRWaitValue; - - /* We are compiling to run from ROM (either on-chip or off-chip flash). - Leave the RAM/flash mapped the way they are on reset - (flash @ 0x00000000, RAM @ 0x00300000), and set up the - proper flash wait states (starts out at the maximum number - of wait states on reset, so we should be able to reduce it). - Most of this code will probably get removed by the compiler - if optimization is enabled, since these calculations are - based on constants. But the compiler should still produce - a correct wait state register value. */ - nsecsPerClockTick = ( portFLOAT ) 1000000000 / configCPU_CLOCK_HZ; - lNumWaitStates = ( portLONG )( ( configFLASH_SPEED_NSEC / nsecsPerClockTick ) + 0.5 ) - 1; - - if( lNumWaitStates < 0 ) - { - lNumWaitStates = 0; - } - - if( lNumWaitStates > MAX_WAIT_STATES ) - { - lNumWaitStates = MAX_WAIT_STATES; - } - - ulCSRWaitValue = ululCSRWaitValues[ lNumWaitStates ]; - ulCSRWaitValue = WaitState5; - - AT91C_BASE_EBI->EBI_CSR[ 0 ] = ulCSRWaitValue | DataBus16 | WaitStateEnable - | PageSize1M | tDF_0cycle - | ByteWriteAccessType | CSEnable - | 0x00000000 /* Base Address */; - } - #else /* else we are compiling to run from on-chip RAM */ - { - /* If compiling to run from RAM, we expect the on-chip RAM to already - be mapped at 0x00000000. This is typically done with an initialization - script for the JTAG emulator you are using to download and run the - demo application. So there is nothing to do here in this case. */ - } - #endif - - /* Disable all interrupts at the AIC level initially... */ - AT91C_BASE_AIC->AIC_IDCR = 0xFFFFFFFF; - - /* Set all SVR and SMR entries to default values (start with a clean slate)... */ - for( lCount = 0; lCount < 32; lCount++ ) - { - AT91C_BASE_AIC->AIC_SVR[ lCount ] = (unsigned long) 0; - AT91C_BASE_AIC->AIC_SMR[ lCount ] = AIC_SRCTYPE_INT_EDGE_TRIGGERED; - } - - /* Disable clocks to all peripherals initially... */ - AT91C_BASE_PS->PS_PCDR = 0xFFFFFFFF; - - /* Clear all interrupts at the AIC level initially... */ - AT91C_BASE_AIC->AIC_ICCR = 0xFFFFFFFF; - - /* Perform 8 "End Of Interrupt" cmds to make sure AIC will not Lock out - nIRQ */ - for( lCount = 0; lCount < 8; lCount++ ) - { - AT91C_BASE_AIC->AIC_EOICR = 0; - } - - /* Initialise LED outputs. */ - vParTestInitialise(); -} -/*-----------------------------------------------------------*/ - -static portLONG prvCheckOtherTasksAreStillRunning( unsigned portLONG ulMemCheckTaskCount ) -{ -portLONG lReturn = ( portLONG ) pdPASS; - - /* Check all the demo tasks (other than the flash tasks) to ensure - that they are all still running, and that none of them have detected - an error. */ - - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - lReturn = ( portLONG ) pdFAIL; - } - - if( xAreComTestTasksStillRunning() != pdTRUE ) - { - lReturn = ( portLONG ) pdFAIL; - } - - if( xArePollingQueuesStillRunning() != pdTRUE ) - { - lReturn = ( portLONG ) pdFAIL; - } - - if( xAreMathsTaskStillRunning() != pdTRUE ) - { - lReturn = ( portLONG ) pdFAIL; - } - - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - lReturn = ( portLONG ) pdFAIL; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - lReturn = ( portLONG ) pdFAIL; - } - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - lReturn = ( portLONG ) pdFAIL; - } - - if( ulMemCheckTaskCount == mainCOUNT_INITIAL_VALUE ) - { - /* The vMemCheckTask did not increment the counter - it must - have failed. */ - lReturn = ( portLONG ) pdFAIL; - } - - return lReturn; -} -/*-----------------------------------------------------------*/ - -static void vMemCheckTask( void *pvParameters ) -{ -unsigned portLONG *pulMemCheckTaskRunningCounter; -void *pvMem1, *pvMem2, *pvMem3; -static portLONG lErrorOccurred = pdFALSE; - - /* This task is dynamically created then deleted during each cycle of the - vErrorChecks task to check the operation of the memory allocator. Each time - the task is created memory is allocated for the stack and TCB. Each time - the task is deleted this memory is returned to the heap. This task itself - exercises the allocator by allocating and freeing blocks. - - The task executes at the idle priority so does not require a delay. - - pulMemCheckTaskRunningCounter is incremented each cycle to indicate to the - vErrorChecks() task that this task is still executing without error. */ - - pulMemCheckTaskRunningCounter = ( unsigned portLONG * ) pvParameters; - - for( ;; ) - { - if( lErrorOccurred == pdFALSE ) - { - /* We have never seen an error so increment the counter. */ - ( *pulMemCheckTaskRunningCounter )++; - } - else - { - /* There has been an error so reset the counter so the check task - can tell that an error occurred. */ - *pulMemCheckTaskRunningCounter = mainCOUNT_INITIAL_VALUE; - } - - /* Allocate some memory - just to give the allocator some extra - exercise. This has to be in a critical section to ensure the - task does not get deleted while it has memory allocated. */ - vTaskSuspendAll(); - { - pvMem1 = pvPortMalloc( mainMEM_CHECK_SIZE_1 ); - if( pvMem1 == NULL ) - { - lErrorOccurred = pdTRUE; - } - else - { - memset( pvMem1, 0xaa, mainMEM_CHECK_SIZE_1 ); - vPortFree( pvMem1 ); - } - } - xTaskResumeAll(); - - /* Again - with a different size block. */ - vTaskSuspendAll(); - { - pvMem2 = pvPortMalloc( mainMEM_CHECK_SIZE_2 ); - if( pvMem2 == NULL ) - { - lErrorOccurred = pdTRUE; - } - else - { - memset( pvMem2, 0xaa, mainMEM_CHECK_SIZE_2 ); - vPortFree( pvMem2 ); - } - } - xTaskResumeAll(); - - /* Again - with a different size block. */ - vTaskSuspendAll(); - { - pvMem3 = pvPortMalloc( mainMEM_CHECK_SIZE_3 ); - if( pvMem3 == NULL ) - { - lErrorOccurred = pdTRUE; - } - else - { - memset( pvMem3, 0xaa, mainMEM_CHECK_SIZE_3 ); - vPortFree( pvMem3 ); - } - } - xTaskResumeAll(); - } -} - diff --git a/Demo/ARM7_AT91FR40008_GCC/pio.h b/Demo/ARM7_AT91FR40008_GCC/pio.h deleted file mode 100644 index a65d138fc..000000000 --- a/Demo/ARM7_AT91FR40008_GCC/pio.h +++ /dev/null @@ -1,149 +0,0 @@ -//*--------------------------------------------------------------------------- -//* ATMEL Microcontroller Software Support - ROUSSET - -//*--------------------------------------------------------------------------- -//* The software is delivered "AS IS" without warranty or condition of any -//* kind, either express, implied or statutory. This includes without -//* limitation any warranty or condition with respect to merchantability or -//* fitness for any particular purpose, or against the infringements of -//* intellectual property rights of others. -//*----------------------------------------------------------------------------- -//* File Name : pio.h -//* Object : Parallel I/O Definition File -//* Translator : ARM Software Development Toolkit V2.11a -//* -//* 1.0 20/10/97 JCZ : Creation -//* 2.0 21/10/98 JCZ : Clean up -//*--------------------------------------------------------------------------- - -#ifndef pio_h -#define pio_h - -/*---------------------------------------------*/ -/* Parallel I/O Interface Structure Definition */ -/*---------------------------------------------*/ - -typedef struct -{ - at91_reg PIO_PER ; /* PIO Enable Register */ - at91_reg PIO_PDR ; /* PIO Disable Register */ - at91_reg PIO_PSR ; /* PIO Status Register */ - at91_reg Reserved0 ; - at91_reg PIO_OER ; /* Output Enable Register */ - at91_reg PIO_ODR ; /* Output Disable Register */ - at91_reg PIO_OSR ; /* Output Status Register */ - at91_reg Reserved1 ; - at91_reg PIO_IFER ; /* Input Filter Enable Register */ - at91_reg PIO_IFDR ; /* Input Filter Disable Register */ - at91_reg PIO_IFSR ; /* Input Filter Status Register */ - at91_reg Reserved2 ; - at91_reg PIO_SODR ; /* Set Output Data Register */ - at91_reg PIO_CODR ; /* Clear Output Data Register */ - at91_reg PIO_ODSR ; /* Output Data Status Register */ - at91_reg PIO_PDSR ; /* Pin Data Status Register */ - at91_reg PIO_IER ; /* Interrupt Enable Register */ - at91_reg PIO_IDR ; /* Interrupt Disable Register */ - at91_reg PIO_IMR ; /* Interrupt Mask Register */ - at91_reg PIO_ISR ; /* Interrupt Status Register */ -} StructPIO ; - -/*-----------------------------*/ -/* PIO Handler type definition */ -/*-----------------------------*/ - -//typedef void (*TypePIOHandler) ( StructPIO *pio_pt, u_int pio_mask ) ; - -/*--------------------------------*/ -/* Device Dependancies Definition */ -/*--------------------------------*/ - -/* Number of PIO Controller */ -#define NB_PIO_CTRL 1 -/* Base Address */ -#define PIO_BASE ((StructPIO *) 0xFFFF0000 ) -/* Number of PIO Lines */ -#define NB_PIO 32 - -/* Parallel I/O Bits Definition */ -#define P0 (1<<0) -#define P1 (1<<1) -#define P2 (1<<2) -#define P3 (1<<3) -#define P4 (1<<4) -#define P5 (1<<5) -#define P6 (1<<6) -#define P7 (1<<7) -#define P8 (1<<8) -#define P9 (1<<9) -#define P10 (1<<10) -#define P11 (1<<11) -#define P12 (1<<12) -#define P13 (1<<13) -#define P14 (1<<14) -#define P15 (1<<15) -#define P16 (1<<16) -#define P17 (1<<17) -#define P18 (1<<18) -#define P19 (1<<19) -#define P20 (1<<20) -#define P21 (1<<21) -#define P22 (1<<22) -#define P23 (1<<23) -#define P24 (1<<24) -#define P25 (1<<25) -#define P26 (1<<26) -#define P27 (1<<27) -#define P28 (1<<28) -#define P29 (1<<29) -#define P30 (1<<30) -#define P31 (1<<31) - -/* PIO Multiplexing Definition */ - -/* There is only one PIO Controller */ -#define PIO_CTRL 0 - -#define PIO_TC0 PIO_CTRL -#define TCLK0 P0 -#define TIOA0 P1 -#define TIOB0 P2 -#define PIN_TC0 (TIOA0|TIOB0|TCLK0) - -#define PIO_TC1 PIO_CTRL -#define TCLK1 P3 -#define TIOA1 P4 -#define TIOB1 P5 -#define PIN_TC1 (TIOA1|TIOB1|TCLK1) - -#define PIO_TC2 PIO_CTRL -#define TCLK2 P6 -#define TIOA2 P7 -#define TIOB2 P8 -#define PIN_TC2 (TIOA2|TIOB2|TCLK2) - -#define PIO_EXT_IRQ PIO_CTRL -#define PIN_IRQ0 P9 -#define PIN_IRQ1 P10 -#define PIN_IRQ2 P11 -#define PIN_FIQ P12 - -#define PIO_USART0 PIO_CTRL -#define SCK0 P13 -#define TXD0 P14 -#define RXD0 P15 -#define PIN_USART0 (SCK0|TXD0|RXD0) - -#define PIO_USART1 PIO_CTRL -#define SCK1 P20 -#define TXD1 P21 -#define RXD1 P22 -#define PIN_USART1 (SCK1|TXD1|RXD1) - -#define MCKO P25 -#define CS2 P26 -#define CS3 P27 -#define CS4 P31 -#define CS5 P30 -#define CS6 P29 -#define CS7 P28 - -#endif /* pio_h */ diff --git a/Demo/ARM7_AT91FR40008_GCC/ram_arm.bat b/Demo/ARM7_AT91FR40008_GCC/ram_arm.bat deleted file mode 100644 index 355bb5ec2..000000000 --- a/Demo/ARM7_AT91FR40008_GCC/ram_arm.bat +++ /dev/null @@ -1,6 +0,0 @@ -set USE_THUMB_MODE=NO -set DEBUG=-g -set OPTIM=-O0 -set RUN_MODE=RUN_FROM_RAM -set LDSCRIPT=atmel-ram.ld -make diff --git a/Demo/ARM7_AT91FR40008_GCC/ram_thumb.bat b/Demo/ARM7_AT91FR40008_GCC/ram_thumb.bat deleted file mode 100644 index 4d5b84593..000000000 --- a/Demo/ARM7_AT91FR40008_GCC/ram_thumb.bat +++ /dev/null @@ -1,6 +0,0 @@ -set USE_THUMB_MODE=YES -set DEBUG=-g -set OPTIM=-O0 -set RUN_MODE=RUN_FROM_RAM -set LDSCRIPT=atmel-ram.ld -make diff --git a/Demo/ARM7_AT91FR40008_GCC/rom_arm.bat b/Demo/ARM7_AT91FR40008_GCC/rom_arm.bat deleted file mode 100644 index 0499bdbc9..000000000 --- a/Demo/ARM7_AT91FR40008_GCC/rom_arm.bat +++ /dev/null @@ -1,6 +0,0 @@ -set USE_THUMB_MODE=NO -set DEBUG=-g -set OPTIM=-O2 -set RUN_MODE=RUN_FROM_ROM -set LDSCRIPT=atmel-rom.ld -make diff --git a/Demo/ARM7_AT91FR40008_GCC/rom_thumb.bat b/Demo/ARM7_AT91FR40008_GCC/rom_thumb.bat deleted file mode 100644 index 9c36b6cfe..000000000 --- a/Demo/ARM7_AT91FR40008_GCC/rom_thumb.bat +++ /dev/null @@ -1,6 +0,0 @@ -set USE_THUMB_MODE=YES -set DEBUG=-g -set OPTIM=-O2 -set RUN_MODE=RUN_FROM_ROM -set LDSCRIPT=atmel-rom.ld -make diff --git a/Demo/ARM7_AT91FR40008_GCC/serial/serial.c b/Demo/ARM7_AT91FR40008_GCC/serial/serial.c deleted file mode 100644 index 6596c5fd6..000000000 --- a/Demo/ARM7_AT91FR40008_GCC/serial/serial.c +++ /dev/null @@ -1,228 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR USART0. - - This file contains all the serial port components that can be compiled to - either ARM or THUMB mode. Components that must be compiled to ARM mode are - contained in serialISR.c. -*/ - -/* Standard includes. */ -#include - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "queue.h" -#include "task.h" - -/* Demo application includes. */ -#include "serial.h" -#include "AT91R40008.h" -#include "usart.h" -#include "pio.h" -#include "aic.h" - -/*-----------------------------------------------------------*/ - -/* Constants to setup and access the UART. */ -#define portUSART0_AIC_CHANNEL ( ( unsigned portLONG ) 2 ) - -#define serINVALID_QUEUE ( ( xQueueHandle ) 0 ) -#define serHANDLE ( ( xComPortHandle ) 1 ) -#define serNO_BLOCK ( ( portTickType ) 0 ) - -/*-----------------------------------------------------------*/ - -/* Queues used to hold received characters, and characters waiting to be -transmitted. */ -static xQueueHandle xRxedChars; -static xQueueHandle xCharsForTx; - -/*-----------------------------------------------------------*/ - -/* - * The queues are created in serialISR.c as they are used from the ISR. - * Obtain references to the queues and THRE Empty flag. - */ -extern void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, xQueueHandle *pxCharsForTx ); - -/*-----------------------------------------------------------*/ - -xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) -{ -unsigned portLONG ulSpeed; -unsigned portLONG ulCD; -xComPortHandle xReturn = serHANDLE; -extern void ( vUART_ISR )( void ); - - /* The queues are used in the serial ISR routine, so are created from - serialISR.c (which is always compiled to ARM mode. */ - vSerialISRCreateQueues( uxQueueLength, &xRxedChars, &xCharsForTx ); - - if( - ( xRxedChars != serINVALID_QUEUE ) && - ( xCharsForTx != serINVALID_QUEUE ) && - ( ulWantedBaud != ( unsigned portLONG ) 0 ) - ) - { - portENTER_CRITICAL(); - { - /* Enable clock to USART0... */ - AT91C_BASE_PS->PS_PCER = AT91C_PS_US0; - - /* Disable all USART0 interrupt sources to begin... */ - AT91C_BASE_US0->US_IDR = 0xFFFFFFFF; - - /* Reset various status bits (just in case)... */ - AT91C_BASE_US0->US_CR = US_RSTSTA; - - AT91C_BASE_PIO->PIO_PDR = TXD0 | RXD0; /* Enable RXD and TXD pins */ - AT91C_BASE_US0->US_CR = US_RSTRX | US_RSTTX | US_RXDIS | US_TXDIS; - - /* Clear Transmit and Receive Counters */ - AT91C_BASE_US0->US_RCR = 0; - AT91C_BASE_US0->US_TCR = 0; - - /* Input clock to baud rate generator is MCK */ - ulSpeed = configCPU_CLOCK_HZ * 10; - ulSpeed = ulSpeed / 16; - ulSpeed = ulSpeed / ulWantedBaud; - - /* compute the error */ - ulCD = ulSpeed / 10; - if ((ulSpeed - (ulCD * 10)) >= 5) - ulCD++; - - /* Define the baud rate divisor register */ - AT91C_BASE_US0->US_BRGR = ulCD; - - /* Define the USART mode */ - AT91C_BASE_US0->US_MR = US_CLKS_MCK | US_CHRL_8 | US_PAR_NO | US_NBSTOP_1 | US_CHMODE_NORMAL; - - /* Write the Timeguard Register */ - AT91C_BASE_US0->US_TTGR = 0; - - /* Setup the interrupt for USART0. - - Store interrupt handler function address in USART0 vector register... */ - AT91C_BASE_AIC->AIC_SVR[ portUSART0_AIC_CHANNEL ] = (unsigned long)vUART_ISR; - - /* USART0 interrupt level-sensitive, priority 1... */ - AT91C_BASE_AIC->AIC_SMR[ portUSART0_AIC_CHANNEL ] = AIC_SRCTYPE_INT_LEVEL_SENSITIVE | 1; - - /* Clear some pending USART0 interrupts (just in case)... */ - AT91C_BASE_US0->US_CR = US_RSTSTA; - - /* Enable USART0 interrupt sources (but not Tx for now)... */ - AT91C_BASE_US0->US_IER = US_RXRDY; - - /* Enable USART0 interrupts in the AIC... */ - AT91C_BASE_AIC->AIC_IECR = ( 1 << portUSART0_AIC_CHANNEL ); - - /* Enable receiver and transmitter... */ - AT91C_BASE_US0->US_CR = US_RXEN | US_TXEN; - } - portEXIT_CRITICAL(); - } - else - { - xReturn = ( xComPortHandle ) 0; - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) -{ - /* The port handle is not required as this driver only supports UART0. */ - ( void ) pxPort; - - /* Get the next character from the buffer. Return false if no characters - are available, or arrive before xBlockTime expires. */ - if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) - { - return pdTRUE; - } - else - { - return pdFALSE; - } -} -/*-----------------------------------------------------------*/ - -void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength ) -{ -signed portCHAR *pxNext; - - /* NOTE: This implementation does not handle the queue being full as no - block time is used! */ - - /* The port handle is not required as this driver only supports UART0. */ - ( void ) pxPort; - - /* Send each character in the string, one at a time. */ - pxNext = ( signed portCHAR * ) pcString; - while( *pxNext ) - { - xSerialPutChar( pxPort, *pxNext, serNO_BLOCK ); - pxNext++; - } -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) -{ - /* Place the character in the queue of characters to be transmitted. */ - if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) - { - return pdFAIL; - } - - /* Turn on the Tx interrupt so the ISR will remove the character from the - queue and send it. This does not need to be in a critical section as - if the interrupt has already removed the character the next interrupt - will simply turn off the Tx interrupt again. */ - AT91C_BASE_US0->US_IER = US_TXRDY; - - return pdPASS; -} -/*-----------------------------------------------------------*/ - -void vSerialClose( xComPortHandle xPort ) -{ - /* Not supported as not required by the demo application. */ -} -/*-----------------------------------------------------------*/ - diff --git a/Demo/ARM7_AT91FR40008_GCC/serial/serialISR.c b/Demo/ARM7_AT91FR40008_GCC/serial/serialISR.c deleted file mode 100644 index 8b1605437..000000000 --- a/Demo/ARM7_AT91FR40008_GCC/serial/serialISR.c +++ /dev/null @@ -1,144 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/* - BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR USART0. - - This file contains all the serial port components that must be compiled - to ARM mode. The components that can be compiled to either ARM or THUMB - mode are contained in serial.c. - -*/ - -/* Standard includes. */ -#include - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "queue.h" -#include "task.h" - -/* Demo application includes. */ -#include "serial.h" -#include "AT91R40008.h" -#include "usart.h" - -/*-----------------------------------------------------------*/ - -/* Constant to access the AIC. */ -#define serCLEAR_AIC_INTERRUPT ( ( unsigned portLONG ) 0 ) - -/* Constants to determine the ISR source. */ -#define serSOURCE_THRE ( ( unsigned portCHAR ) 0x02 ) -#define serSOURCE_RX_TIMEOUT ( ( unsigned portCHAR ) 0x0c ) -#define serSOURCE_ERROR ( ( unsigned portCHAR ) 0x06 ) -#define serSOURCE_RX ( ( unsigned portCHAR ) 0x04 ) -#define serINTERRUPT_SOURCE_MASK ( ( unsigned portLONG ) (US_RXRDY | US_TXRDY | US_RXBRK | US_OVRE | US_FRAME | US_PARE) ) - -/* Queues used to hold received characters, and characters waiting to be -transmitted. */ -static xQueueHandle xRxedChars; -static xQueueHandle xCharsForTx; - -/*-----------------------------------------------------------*/ - -/* UART0 interrupt service routine. This can cause a context switch so MUST -be declared "naked". */ -void vUART_ISR( void ) __attribute__ ((naked)); - -/*-----------------------------------------------------------*/ -void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, xQueueHandle *pxCharsForTx ) -{ - /* Create the queues used to hold Rx and Tx characters. */ - xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); - xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); - - /* Pass back a reference to the queues so the serial API file can - post/receive characters. */ - *pxRxedChars = xRxedChars; - *pxCharsForTx = xCharsForTx; -} -/*-----------------------------------------------------------*/ - -void vUART_ISR( void ) -{ - /* This ISR can cause a context switch, so the first statement must be a - call to the portENTER_SWITCHING_ISR() macro. This must be BEFORE any - variable declarations. */ - portENTER_SWITCHING_ISR(); - - /* Now we can declare the local variables. */ - signed portCHAR cChar; - portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByRx = pdFALSE; - unsigned portLONG ulStatus; - - /* What caused the interrupt? */ - ulStatus = AT91C_BASE_US0->US_CSR & AT91C_BASE_US0->US_IMR; - - if (ulStatus & US_TXRDY) - { - /* The interrupt was caused by the THR becoming empty. Are there any - more characters to transmit? */ - if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE ) - { - /* A character was retrieved from the queue so can be sent to the - THR now. */ - AT91C_BASE_US0->US_THR = cChar; - } - else - { - /* Queue empty, nothing to send so turn off the Tx interrupt. */ - AT91C_BASE_US0->US_IDR = US_TXRDY; - } - } - - if (ulStatus & US_RXRDY) - { - /* The interrupt was caused by the receiver getting data. */ - cChar = AT91C_BASE_US0->US_RHR; - - if (xQueueSendFromISR(xRxedChars, &cChar, pdFALSE)) - { - xTaskWokenByRx = pdTRUE; - } - } - - // Acknowledge the interrupt at AIC level... - AT91C_BASE_AIC->AIC_EOICR = serCLEAR_AIC_INTERRUPT; - - /* Exit the ISR. If a task was woken by either a character being received - or transmitted then a context switch will occur. */ - portEXIT_SWITCHING_ISR( ( xTaskWokenByTx || xTaskWokenByRx ) ); -} -/*-----------------------------------------------------------*/ - diff --git a/Demo/ARM7_AT91FR40008_GCC/tc.h b/Demo/ARM7_AT91FR40008_GCC/tc.h deleted file mode 100644 index 518220e47..000000000 --- a/Demo/ARM7_AT91FR40008_GCC/tc.h +++ /dev/null @@ -1,301 +0,0 @@ -//*---------------------------------------------------------------------------- -//* ATMEL Microcontroller Software Support - ROUSSET - -//*---------------------------------------------------------------------------- -//* The software is delivered "AS IS" without warranty or condition of any -//* kind, either express, implied or statutory. This includes without -//* limitation any warranty or condition with respect to merchantability or -//* fitness for any particular purpose, or against the infringements of -//* intellectual property rights of others. -//*----------------------------------------------------------------------------- -//* File Name : tc.h -//* Object : Timer Counter Header File -//* -//* 1.0 01/04/00 JCZ : Creation -//* 1.0 01/09/00 JPP : modification TC_BEEVT, TC_BEEVT_SET_OUTPUT, -//* TC_BEEVT_CLEAR_OUTPUT, TC_BEEVT_TOGGLE_OUTPUT -//*----------------------------------------------------------------------------- - -#ifndef tc_h -#define tc_h - -//#include "periph/stdc/std_c.h" -//#include "periph/pio/lib_pio.h" - -/*-------------------------------------------*/ -/* Timer User Interface Structure Definition */ -/*-------------------------------------------*/ - -typedef struct -{ - at91_reg TC_CCR ; /* Control Register */ - at91_reg TC_CMR ; /* Mode Register */ - at91_reg Reserved0 ; - at91_reg Reserved1 ; - at91_reg TC_CV ; /* Counter value */ - at91_reg TC_RA ; /* Register A */ - at91_reg TC_RB ; /* Register B */ - at91_reg TC_RC ; /* Register C */ - at91_reg TC_SR ; /* Status Register */ - at91_reg TC_IER ; /* Interrupt Enable Register */ - at91_reg TC_IDR ; /* Interrupt Disable Register */ - at91_reg TC_IMR ; /* Interrupt Mask Register */ - at91_reg Reserved2 ; - at91_reg Reserved3 ; - at91_reg Reserved4 ; - at91_reg Reserved5 ; -} StructTC ; - -#define NB_TC_CHANNEL 3 - -typedef struct -{ - StructTC TC[NB_TC_CHANNEL] ; - at91_reg TC_BCR ; /* Block Control Register */ - at91_reg TC_BMR ; /* Block Mode Register */ -} StructTCBlock ; - -/*--------------------------------------------------------*/ -/* TC_CCR: Timer Counter Control Register Bits Definition */ -/*--------------------------------------------------------*/ -#define TC_CLKEN 0x1 -#define TC_CLKDIS 0x2 -#define TC_SWTRG 0x4 - -/*---------------------------------------------------------------*/ -/* TC_CMR: Timer Counter Channel Mode Register Bits Definition */ -/*---------------------------------------------------------------*/ - -/*-----------------*/ -/* Clock Selection */ -/*-----------------*/ -#define TC_CLKS 0x7 -#define TC_CLKS_MCK2 0x0 -#define TC_CLKS_MCK8 0x1 -#define TC_CLKS_MCK32 0x2 -#define TC_CLKS_MCK128 0x3 -#define TC_CLKS_MCK1024 0x4 - -#define TC_CLKS_SLCK 0x4 - -#define TC_CLKS_XC0 0x5 -#define TC_CLKS_XC1 0x6 -#define TC_CLKS_XC2 0x7 - - -/*-----------------*/ -/* Clock Inversion */ -/*-----------------*/ -#define TC_CLKI 0x8 - -/*------------------------*/ -/* Burst Signal Selection */ -/*------------------------*/ -#define TC_BURST 0x30 -#define TC_BURST_NONE 0x0 -#define TC_BUSRT_XC0 0x10 -#define TC_BURST_XC1 0x20 -#define TC_BURST_XC2 0x30 - -/*------------------------------------------------------*/ -/* Capture Mode : Counter Clock Stopped with RB Loading */ -/*------------------------------------------------------*/ -#define TC_LDBSTOP 0x40 - -/*-------------------------------------------------------*/ -/* Waveform Mode : Counter Clock Stopped with RC Compare */ -/*-------------------------------------------------------*/ -#define TC_CPCSTOP 0x40 - -/*-------------------------------------------------------*/ -/* Capture Mode : Counter Clock Disabled with RB Loading */ -/*--------------------------------------------------------*/ -#define TC_LDBDIS 0x80 - -/*--------------------------------------------------------*/ -/* Waveform Mode : Counter Clock Disabled with RC Compare */ -/*--------------------------------------------------------*/ -#define TC_CPCDIS 0x80 - -/*------------------------------------------------*/ -/* Capture Mode : External Trigger Edge Selection */ -/*------------------------------------------------*/ -#define TC_ETRGEDG 0x300 -#define TC_ETRGEDG_EDGE_NONE 0x0 -#define TC_ETRGEDG_RISING_EDGE 0x100 -#define TC_ETRGEDG_FALLING_EDGE 0x200 -#define TC_ETRGEDG_BOTH_EDGE 0x300 - -/*-----------------------------------------------*/ -/* Waveform Mode : External Event Edge Selection */ -/*-----------------------------------------------*/ -#define TC_EEVTEDG 0x300 -#define TC_EEVTEDG_EDGE_NONE 0x0 -#define TC_EEVTEDG_RISING_EDGE 0x100 -#define TC_EEVTEDG_FALLING_EDGE 0x200 -#define TC_EEVTEDG_BOTH_EDGE 0x300 - -/*--------------------------------------------------------*/ -/* Capture Mode : TIOA or TIOB External Trigger Selection */ -/*--------------------------------------------------------*/ -#define TC_ABETRG 0x400 -#define TC_ABETRG_TIOB 0x0 -#define TC_ABETRG_TIOA 0x400 - -/*------------------------------------------*/ -/* Waveform Mode : External Event Selection */ -/*------------------------------------------*/ -#define TC_EEVT 0xC00 -#define TC_EEVT_TIOB 0x0 -#define TC_EEVT_XC0 0x400 -#define TC_EEVT_XC1 0x800 -#define TC_EEVT_XC2 0xC00 - -/*--------------------------------------------------*/ -/* Waveform Mode : Enable Trigger on External Event */ -/*--------------------------------------------------*/ -#define TC_ENETRG 0x1000 - -/*----------------------------------*/ -/* RC Compare Enable Trigger Enable */ -/*----------------------------------*/ -#define TC_CPCTRG 0x4000 - -/*----------------*/ -/* Mode Selection */ -/*----------------*/ -#define TC_WAVE 0x8000 -#define TC_CAPT 0x0 - -/*-------------------------------------*/ -/* Capture Mode : RA Loading Selection */ -/*-------------------------------------*/ -#define TC_LDRA 0x30000 -#define TC_LDRA_EDGE_NONE 0x0 -#define TC_LDRA_RISING_EDGE 0x10000 -#define TC_LDRA_FALLING_EDGE 0x20000 -#define TC_LDRA_BOTH_EDGE 0x30000 - -/*-------------------------------------------*/ -/* Waveform Mode : RA Compare Effect on TIOA */ -/*-------------------------------------------*/ -#define TC_ACPA 0x30000 -#define TC_ACPA_OUTPUT_NONE 0x0 -#define TC_ACPA_SET_OUTPUT 0x10000 -#define TC_ACPA_CLEAR_OUTPUT 0x20000 -#define TC_ACPA_TOGGLE_OUTPUT 0x30000 - -/*-------------------------------------*/ -/* Capture Mode : RB Loading Selection */ -/*-------------------------------------*/ -#define TC_LDRB 0xC0000 -#define TC_LDRB_EDGE_NONE 0x0 -#define TC_LDRB_RISING_EDGE 0x40000 -#define TC_LDRB_FALLING_EDGE 0x80000 -#define TC_LDRB_BOTH_EDGE 0xC0000 - -/*-------------------------------------------*/ -/* Waveform Mode : RC Compare Effect on TIOA */ -/*-------------------------------------------*/ -#define TC_ACPC 0xC0000 -#define TC_ACPC_OUTPUT_NONE 0x0 -#define TC_ACPC_SET_OUTPUT 0x40000 -#define TC_ACPC_CLEAR_OUTPUT 0x80000 -#define TC_ACPC_TOGGLE_OUTPUT 0xC0000 - -/*-----------------------------------------------*/ -/* Waveform Mode : External Event Effect on TIOA */ -/*-----------------------------------------------*/ -#define TC_AEEVT 0x300000 -#define TC_AEEVT_OUTPUT_NONE 0x0 -#define TC_AEEVT_SET_OUTPUT 0x100000 -#define TC_AEEVT_CLEAR_OUTPUT 0x200000 -#define TC_AEEVT_TOGGLE_OUTPUT 0x300000 - -/*-------------------------------------------------*/ -/* Waveform Mode : Software Trigger Effect on TIOA */ -/*-------------------------------------------------*/ -#define TC_ASWTRG 0xC00000 -#define TC_ASWTRG_OUTPUT_NONE 0x0 -#define TC_ASWTRG_SET_OUTPUT 0x400000 -#define TC_ASWTRG_CLEAR_OUTPUT 0x800000 -#define TC_ASWTRG_TOGGLE_OUTPUT 0xC00000 - -/*-------------------------------------------*/ -/* Waveform Mode : RB Compare Effect on TIOB */ -/*-------------------------------------------*/ -#define TC_BCPB 0x1000000 -#define TC_BCPB_OUTPUT_NONE 0x0 -#define TC_BCPB_SET_OUTPUT 0x1000000 -#define TC_BCPB_CLEAR_OUTPUT 0x2000000 -#define TC_BCPB_TOGGLE_OUTPUT 0x3000000 - -/*-------------------------------------------*/ -/* Waveform Mode : RC Compare Effect on TIOB */ -/*-------------------------------------------*/ -#define TC_BCPC 0xC000000 -#define TC_BCPC_OUTPUT_NONE 0x0 -#define TC_BCPC_SET_OUTPUT 0x4000000 -#define TC_BCPC_CLEAR_OUTPUT 0x8000000 -#define TC_BCPC_TOGGLE_OUTPUT 0xC000000 - -/*-----------------------------------------------*/ -/* Waveform Mode : External Event Effect on TIOB */ -/*-----------------------------------------------*/ -#define TC_BEEVT 0x30000000 //* bit 29-28 -#define TC_BEEVT_OUTPUT_NONE 0x0 -#define TC_BEEVT_SET_OUTPUT 0x10000000 //* bit 29-28 01 -#define TC_BEEVT_CLEAR_OUTPUT 0x20000000 //* bit 29-28 10 -#define TC_BEEVT_TOGGLE_OUTPUT 0x30000000 //* bit 29-28 11 - -/*- -----------------------------------------------*/ -/* Waveform Mode : Software Trigger Effect on TIOB */ -/*-------------------------------------------------*/ -#define TC_BSWTRG 0xC0000000 -#define TC_BSWTRG_OUTPUT_NONE 0x0 -#define TC_BSWTRG_SET_OUTPUT 0x40000000 -#define TC_BSWTRG_CLEAR_OUTPUT 0x80000000 -#define TC_BSWTRG_TOGGLE_OUTPUT 0xC0000000 - -/*------------------------------------------------------*/ -/* TC_SR: Timer Counter Status Register Bits Definition */ -/*------------------------------------------------------*/ -#define TC_COVFS 0x1 /* Counter Overflow Status */ -#define TC_LOVRS 0x2 /* Load Overrun Status */ -#define TC_CPAS 0x4 /* RA Compare Status */ -#define TC_CPBS 0x8 /* RB Compare Status */ -#define TC_CPCS 0x10 /* RC Compare Status */ -#define TC_LDRAS 0x20 /* RA Loading Status */ -#define TC_LDRBS 0x40 /* RB Loading Status */ -#define TC_ETRGS 0x80 /* External Trigger Status */ -#define TC_CLKSTA 0x10000 /* Clock Status */ -#define TC_MTIOA 0x20000 /* TIOA Mirror */ -#define TC_MTIOB 0x40000 /* TIOB Status */ - -/*--------------------------------------------------------------*/ -/* TC_BCR: Timer Counter Block Control Register Bits Definition */ -/*--------------------------------------------------------------*/ -#define TC_SYNC 0x1 /* Synchronisation Trigger */ - -/*------------------------------------------------------------*/ -/* TC_BMR: Timer Counter Block Mode Register Bits Definition */ -/*------------------------------------------------------------*/ -#define TC_TC0XC0S 0x3 /* External Clock Signal 0 Selection */ -#define TC_TCLK0XC0 0x0 -#define TC_NONEXC0 0x1 -#define TC_TIOA1XC0 0x2 -#define TC_TIOA2XC0 0x3 - -#define TC_TC1XC1S 0xC /* External Clock Signal 1 Selection */ -#define TC_TCLK1XC1 0x0 -#define TC_NONEXC1 0x4 -#define TC_TIOA0XC1 0x8 -#define TC_TIOA2XC1 0xC - -#define TC_TC2XC2S 0x30 /* External Clock Signal 2 Selection */ -#define TC_TCLK2XC2 0x0 -#define TC_NONEXC2 0x10 -#define TC_TIOA0XC2 0x20 -#define TC_TIOA1XC2 0x30 - -#endif /* tc_h */ - diff --git a/Demo/ARM7_AT91FR40008_GCC/usart.h b/Demo/ARM7_AT91FR40008_GCC/usart.h deleted file mode 100644 index ad36ef504..000000000 --- a/Demo/ARM7_AT91FR40008_GCC/usart.h +++ /dev/null @@ -1,151 +0,0 @@ -//*---------------------------------------------------------------------------- -//* ATMEL Microcontroller Software Support - ROUSSET - -//*---------------------------------------------------------------------------- -//* The software is delivered "AS IS" without warranty or condition of any -//* kind, either express, implied or statutory. This includes without -//* limitation any warranty or condition with respect to merchantability or -//* fitness for any particular purpose, or against the infringements of -//* intellectual property rights of others. -//*----------------------------------------------------------------------------- -//* File Name : usart.h -//* Object : USART Header File. -//* -//* 1.0 01/04/00 JCZ : Creation -//*---------------------------------------------------------------------------- - -#ifndef usart_h -#define usart_h - -//#include "periph/stdc/std_c.h" -//#include "periph/pio/lib_pio.h" - -/*-------------------------------------------*/ -/* USART User Interface Structure Definition */ -/*-------------------------------------------*/ - -typedef struct -{ - at91_reg US_CR ; /* Control Register */ - at91_reg US_MR ; /* Mode Register */ - at91_reg US_IER ; /* Interrupt Enable Register */ - at91_reg US_IDR ; /* Interrupt Disable Register */ - at91_reg US_IMR ; /* Interrupt Mask Register */ - at91_reg US_CSR ; /* Channel Status Register */ - at91_reg US_RHR ; /* Receive Holding Register */ - at91_reg US_THR ; /* Transmit Holding Register */ - at91_reg US_BRGR ; /* Baud Rate Generator Register */ - at91_reg US_RTOR ; /* Receiver Timeout Register */ - at91_reg US_TTGR ; /* Transmitter Time-guard Register */ - at91_reg Reserved ; - at91_reg US_RPR ; /* Receiver Pointer Register */ - at91_reg US_RCR ; /* Receiver Counter Register */ - at91_reg US_TPR ; /* Transmitter Pointer Register */ - at91_reg US_TCR ; /* Transmitter Counter Register */ -} StructUSART ; - -/*--------------------------*/ -/* US_CR : Control Register */ -/*--------------------------*/ - -#define US_RSTRX 0x0004 /* Reset Receiver */ -#define US_RSTTX 0x0008 /* Reset Transmitter */ -#define US_RXEN 0x0010 /* Receiver Enable */ -#define US_RXDIS 0x0020 /* Receiver Disable */ -#define US_TXEN 0x0040 /* Transmitter Enable */ -#define US_TXDIS 0x0080 /* Transmitter Disable */ -#define US_RSTSTA 0x0100 /* Reset Status Bits */ -#define US_STTBRK 0x0200 /* Start Break */ -#define US_STPBRK 0x0400 /* Stop Break */ -#define US_STTTO 0x0800 /* Start Time-out */ -#define US_SENDA 0x1000 /* Send Address */ - -/*-----------------------*/ -/* US_MR : Mode Register */ -/*-----------------------*/ - -#define US_CLKS 0x0030 /* Clock Selection */ -#define US_CLKS_MCK 0x00 /* Master Clock */ -#define US_CLKS_MCK8 0x10 /* Master Clock divided by 8 */ -#define US_CLKS_SCK 0x20 /* External Clock */ -#define US_CLKS_SLCK 0x30 /* Slow Clock */ - -#define US_CHRL 0x00C0 /* Byte Length */ -#define US_CHRL_5 0x00 /* 5 bits */ -#define US_CHRL_6 0x40 /* 6 bits */ -#define US_CHRL_7 0x80 /* 7 bits */ -#define US_CHRL_8 0xC0 /* 8 bits */ - -#define US_SYNC 0x0100 /* Synchronous Mode Enable */ - -#define US_PAR 0x0E00 /* Parity Mode */ -#define US_PAR_EVEN 0x00 /* Even Parity */ -#define US_PAR_ODD 0x200 /* Odd Parity */ -#define US_PAR_SPACE 0x400 /* Space Parity to 0 */ -#define US_PAR_MARK 0x600 /* Marked Parity to 1 */ -#define US_PAR_NO 0x800 /* No Parity */ -#define US_PAR_MULTIDROP 0xC00 /* Multi-drop Mode */ - -#define US_NBSTOP 0x3000 /* Stop Bit Number */ -#define US_NBSTOP_1 0x0000 /* 1 Stop Bit */ -#define US_NBSTOP_1_5 0x1000 /* 1.5 Stop Bits */ -#define US_NBSTOP_2 0x2000 /* 2 Stop Bits */ - -#define US_CHMODE 0xC000 /* Channel Mode */ -#define US_CHMODE_NORMAL 0x0000 /* Normal Mode */ -#define US_CHMODE_AUTOMATIC_ECHO 0x4000 /* Automatic Echo */ -#define US_CHMODE_LOCAL_LOOPBACK 0x8000 /* Local Loopback */ -#define US_CHMODE_REMOTE_LOOPBACK 0xC000 /* Remote Loopback */ - -#define US_MODE9 0x20000 /* 9 Bit Mode */ - -#define US_CLKO 0x40000 /* Baud Rate Output Enable */ - -/* Mode Register model */ - -/* Standard Asynchronous Mode : 8 bits , 1 stop , no parity */ -#define US_ASYNC_MODE ( US_CHMODE_NORMAL + \ - US_NBSTOP_1 + \ - US_PAR_NO + \ - US_CHRL_8 + \ - US_CLKS_MCK ) - -/* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity */ -#define US_ASYNC_SCK_MODE ( US_CHMODE_NORMAL + \ - US_NBSTOP_1 + \ - US_PAR_NO + \ - US_CHRL_8 + \ - US_CLKS_SCK ) - -/* Standard Synchronous Mode : 8 bits , 1 stop , no parity */ -#define US_SYNC_MODE ( US_SYNC + \ - US_CHMODE_NORMAL + \ - US_NBSTOP_1 + \ - US_PAR_NO + \ - US_CHRL_8 + \ - US_CLKS_MCK ) - -/* SCK used Label */ -#define SCK_USED (US_CLKO | US_CLKS_SCK) - -/*---------------------------------------------------------------*/ -/* US_IER, US_IDR, US_IMR, US_IMR: Status and Interrupt Register */ -/*---------------------------------------------------------------*/ - -#define US_RXRDY 0x1 /* Receiver Ready */ -#define US_TXRDY 0x2 /* Transmitter Ready */ -#define US_RXBRK 0x4 /* Receiver Break */ -#define US_ENDRX 0x8 /* End of Receiver PDC Transfer */ -#define US_ENDTX 0x10 /* End of Transmitter PDC Transfer */ -#define US_OVRE 0x20 /* Overrun Error */ -#define US_FRAME 0x40 /* Framing Error */ -#define US_PARE 0x80 /* Parity Error */ -#define US_TIMEOUT 0x100 /* Receiver Timeout */ -#define US_TXEMPTY 0x200 /* Transmitter Empty */ - -#define US_MASK_IRQ_TX (US_TXRDY | US_ENDTX | US_TXEMPTY) -#define US_MASK_IRQ_RX (US_RXRDY | US_ENDRX | US_TIMEOUT) -#define US_MASK_IRQ_ERROR (US_PARE | US_FRAME | US_OVRE | US_RXBRK) - - - -#endif /* usart_h */ diff --git a/Demo/ARM7_AT91SAM7S64_IAR/FreeRTOSConfig.h b/Demo/ARM7_AT91SAM7S64_IAR/FreeRTOSConfig.h deleted file mode 100644 index dc685d11f..000000000 --- a/Demo/ARM7_AT91SAM7S64_IAR/FreeRTOSConfig.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -#include -#include "Board.h" - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 47923200 ) -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 100 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) 14200 ) -#define configMAX_TASK_NAME_LEN ( 16 ) -#define configUSE_TRACE_FACILITY 0 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 1 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 0 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/ARM7_AT91SAM7S64_IAR/ParTest/ParTest.c b/Demo/ARM7_AT91SAM7S64_IAR/ParTest/ParTest.c deleted file mode 100644 index afb8d0e2d..000000000 --- a/Demo/ARM7_AT91SAM7S64_IAR/ParTest/ParTest.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#include "FreeRTOS.h" -#include "partest.h" -#include "board.h" - -/*----------------------------------------------------------- - * Simple parallel port IO routines for the LED's. - *-----------------------------------------------------------*/ - -const unsigned portLONG led_mask[ NB_LED ]= { LED1, LED2, LED3, LED4 }; - -void vParTestInitialise( void ) -{ - /* Start with all LED's off. */ - AT91F_PIO_SetOutput( AT91C_BASE_PIOA, LED_MASK ); -} -/*-----------------------------------------------------------*/ - -void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) -{ - if( uxLED < ( portBASE_TYPE ) NB_LED ) - { - if( xValue ) - { - AT91F_PIO_SetOutput( AT91C_BASE_PIOA, led_mask[ uxLED ] ); - } - else - { - AT91F_PIO_ClearOutput( AT91C_BASE_PIOA, led_mask[ uxLED ]); - } - } -} -/*-----------------------------------------------------------*/ - -void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) -{ - if( uxLED < ( portBASE_TYPE ) NB_LED ) - { - if( AT91F_PIO_GetInput( AT91C_BASE_PIOA ) & led_mask[ uxLED ] ) - { - AT91F_PIO_ClearOutput( AT91C_BASE_PIOA, led_mask[ uxLED ]); - } - else - { - AT91F_PIO_SetOutput( AT91C_BASE_PIOA, led_mask[ uxLED ] ); - } - } -} - - diff --git a/Demo/ARM7_AT91SAM7S64_IAR/SrcIAR/Board.h b/Demo/ARM7_AT91SAM7S64_IAR/SrcIAR/Board.h deleted file mode 100644 index f6da8060c..000000000 --- a/Demo/ARM7_AT91SAM7S64_IAR/SrcIAR/Board.h +++ /dev/null @@ -1,89 +0,0 @@ -/*---------------------------------------------------------------------------- -* ATMEL Microcontroller Software Support - ROUSSET - -*---------------------------------------------------------------------------- -* The software is delivered "AS IS" without warranty or condition of any -* kind, either express, implied or statutory. This includes without -* limitation any warranty or condition with respect to merchantability or -* fitness for any particular purpose, or against the infringements of -* intellectual property rights of others. -*---------------------------------------------------------------------------- -* File Name : Board.h -* Object : AT91SAM7S Evaluation Board Features Definition File. -* -* Creation : JPP 16/Jun/2004 -*---------------------------------------------------------------------------- -*/ -#ifndef Board_h -#define Board_h - -#include "AT91SAM7S64.h" -#define __inline inline -#include "lib_AT91SAM7S64.h" - -#define true -1 -#define false 0 - -/*-------------------------------*/ -/* SAM7Board Memories Definition */ -/*-------------------------------*/ -// The AT91SAM7S64 embeds a 16-Kbyte SRAM bank, and 64 K-Byte Flash - -#define INT_SARM 0x00200000 -#define INT_SARM_REMAP 0x00000000 - -#define INT_FLASH 0x00000000 -#define INT_FLASH_REMAP 0x01000000 - -#define FLASH_PAGE_NB 512 -#define FLASH_PAGE_SIZE 128 - -/*-----------------*/ -/* Leds Definition */ -/*-----------------*/ -/* PIO Flash PA PB PIN */ -#define LED1 (1<<0) /* PA0 / PGMEN0 & PWM0 TIOA0 48 */ -#define LED2 (1<<1) /* PA1 / PGMEN1 & PWM1 TIOB0 47 */ -#define LED3 (1<<2) /* PA2 & PWM2 SCK0 44 */ -#define LED4 (1<<3) /* PA3 & TWD NPCS3 43 */ -#define NB_LED 4 - -#define LED_MASK (LED1|LED2|LED3|LED4) - -/*-------------------------*/ -/* Push Buttons Definition */ -/*-------------------------*/ -/* PIO Flash PA PB PIN */ -#define SW1_MASK (1<<19) /* PA19 / PGMD7 & RK FIQ 13 */ -#define SW2_MASK (1<<20) /* PA20 / PGMD8 & RF IRQ0 16 */ -#define SW3_MASK (1<<15) /* PA15 / PGM3 & TF TIOA1 20 */ -#define SW4_MASK (1<<14) /* PA14 / PGMD2 & SPCK PWM3 21 */ -#define SW_MASK (SW1_MASK|SW2_MASK|SW3_MASK|SW4_MASK) - - -#define SW1 (1<<19) // PA19 -#define SW2 (1<<20) // PA20 -#define SW3 (1<<15) // PA15 -#define SW4 (1<<14) // PA14 - -/*------------------*/ -/* USART Definition */ -/*------------------*/ -/* SUB-D 9 points J3 DBGU*/ -#define DBGU_RXD AT91C_PA9_DRXD /* JP11 must be close */ -#define DBGU_TXD AT91C_PA10_DTXD /* JP12 must be close */ -#define AT91C_DBGU_BAUD 115200 // Baud rate - -#define US_RXD_PIN AT91C_PA5_RXD0 /* JP9 must be close */ -#define US_TXD_PIN AT91C_PA6_TXD0 /* JP7 must be close */ -#define US_RTS_PIN AT91C_PA7_RTS0 /* JP8 must be close */ -#define US_CTS_PIN AT91C_PA8_CTS0 /* JP6 must be close */ - -/*--------------*/ -/* Master Clock */ -/*--------------*/ - -#define EXT_OC 18432000 // Exetrnal ocilator MAINCK -#define MCK 47923200 // MCK (PLLRC div by 2) -#define MCKKHz (MCK/1000) // - -#endif /* Board_h */ diff --git a/Demo/ARM7_AT91SAM7S64_IAR/SrcIAR/Cstartup.s79 b/Demo/ARM7_AT91SAM7S64_IAR/SrcIAR/Cstartup.s79 deleted file mode 100644 index 966f6f243..000000000 --- a/Demo/ARM7_AT91SAM7S64_IAR/SrcIAR/Cstartup.s79 +++ /dev/null @@ -1,223 +0,0 @@ -;------------------------------------------------------------------------------ -;- ATMEL Microcontroller Software Support - ROUSSET - -;------------------------------------------------------------------------------ -; The software is delivered "AS IS" without warranty or condition of any -; kind, either express, implied or statutory. This includes without -; limitation any warranty or condition with respect to merchantability or -; fitness for any particular purpose, or against the infringements of -; intellectual property rights of others. -;----------------------------------------------------------------------------- -;- File source : Cstartup.s79 -;- Object : Generic CStartup for IAR No Use REMAP -;- Compilation flag : None -;- -;- 1.0 15/Jun/04 JPP : Creation -;------------------------------------------------------------------------------ - -#include "AT91SAM7S64_inc.h" - -;------------------------------------------------------------------------------ -;- Area Definition -;------------------------------------------------------------------------------ - -;--------------------------------------------------------------- -; ?RESET -; Reset Vector. -; Normally, segment INTVEC is linked at address 0. -; For debugging purposes, INTVEC may be placed at other -; addresses. -; A debugger that honors the entry point will start the -; program in a normal way even if INTVEC is not at address 0. -;------------------------------------------------------------- - - PROGRAM ?RESET - RSEG INTRAMSTART_REMAP - RSEG INTRAMEND_REMAP - - EXTERN vPortYieldProcessor - - RSEG ICODE:CODE:ROOT(2) - CODE32 ; Always ARM mode after reset - org 0 -reset -;------------------------------------------------------------------------------ -;- Exception vectors -;-------------------- -;- These vectors can be read at address 0 or at RAM address -;- They ABSOLUTELY requires to be in relative addresssing mode in order to -;- guarantee a valid jump. For the moment, all are just looping. -;- If an exception occurs before remap, this would result in an infinite loop. -;- To ensure if a exeption occurs before start application to infinite loop. -;------------------------------------------------------------------------------ - - B InitReset ; 0x00 Reset handler -undefvec: - B undefvec ; 0x04 Undefined Instruction -swivec: - B vPortYieldProcessor ; 0x08 Software Interrupt -pabtvec: - B pabtvec ; 0x0C Prefetch Abort -dabtvec: - B dabtvec ; 0x10 Data Abort -rsvdvec: - B rsvdvec ; 0x14 reserved -irqvec: - LDR PC, [PC, #-0xF20] ; Jump directly to the address given by the AIC - -fiqvec: ; 0x1c FIQ - -;------------------------------------------------------------------------------ -;- Function : FIQ_Handler_Entry -;- Treatments : FIQ Controller Interrupt Handler. -;- Called Functions : AIC_FVR[interrupt] -;------------------------------------------------------------------------------ - -FIQ_Handler_Entry: - -;- Switch in SVC/User Mode to allow User Stack access for C code -; because the FIQ is not yet acknowledged - -;- Save and r0 in FIQ_Register - mov r9,r0 - ldr r0 , [r8, #AIC_FVR] - msr CPSR_c,#I_BIT | F_BIT | ARM_MODE_SVC - -;- Save scratch/used registers and LR in User Stack - stmfd sp!, { r1-r3, r12, lr} - -;- Branch to the routine pointed by the AIC_FVR - mov r14, pc - bx r0 - -;- Restore scratch/used registers and LR from User Stack - ldmia sp!, { r1-r3, r12, lr} - -;- Leave Interrupts disabled and switch back in FIQ mode - msr CPSR_c, #I_BIT | F_BIT | ARM_MODE_FIQ - -;- Restore the R0 ARM_MODE_SVC register - mov r0,r9 - -;- Restore the Program Counter using the LR_fiq directly in the PC - subs pc,lr,#4 - -InitReset: -;------------------------------------------------------------------------------ -;- Low level Init (PMC, AIC, ? ....) by C function AT91F_LowLevelInit -;------------------------------------------------------------------------------ - EXTERN AT91F_LowLevelInit - -#define __iramend SFB(INTRAMEND_REMAP) - -;- minumum C initialization -;- call AT91F_LowLevelInit( void) - - ldr r13,=__iramend ; temporary stack in internal RAM -;--Call Low level init function in ABSOLUTE through the Interworking - ldr r0,=AT91F_LowLevelInit - mov lr, pc - bx r0 -;------------------------------------------------------------------------------ -;- Stack Sizes Definition -;------------------------ -;- Interrupt Stack requires 2 words x 8 priority level x 4 bytes when using -;- the vectoring. This assume that the IRQ management. -;- The Interrupt Stack must be adjusted depending on the interrupt handlers. -;- Fast Interrupt not requires stack If in your application it required you must -;- be definehere. -;- The System stack size is not defined and is limited by the free internal -;- SRAM. -;------------------------------------------------------------------------------ - -;------------------------------------------------------------------------------ -;- Top of Stack Definition -;------------------------- -;- Interrupt and Supervisor Stack are located at the top of internal memory in -;- order to speed the exception handling context saving and restoring. -;- ARM_MODE_SVC (Application, C) Stack is located at the top of the external memory. -;------------------------------------------------------------------------------ - -IRQ_STACK_SIZE EQU 300 - -ARM_MODE_FIQ EQU 0x11 -ARM_MODE_IRQ EQU 0x12 -ARM_MODE_SVC EQU 0x13 - -I_BIT EQU 0x80 -F_BIT EQU 0x40 - -;------------------------------------------------------------------------------ -;- Setup the stack for each mode -;------------------------------- - ldr r0, =__iramend - -;- Set up Fast Interrupt Mode and set FIQ Mode Stack - msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT -;- Init the FIQ register - ldr r8, =AT91C_BASE_AIC - -;- Set up Interrupt Mode and set IRQ Mode Stack - msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT - mov r13, r0 ; Init stack IRQ - sub r0, r0, #IRQ_STACK_SIZE - -;- Enable interrupt & Set up Supervisor Mode and set Supervisor Mode Stack - msr CPSR_c, #ARM_MODE_SVC - mov r13, r0 - - -;--------------------------------------------------------------- -; ?CSTARTUP -;--------------------------------------------------------------- - EXTERN __segment_init - EXTERN main -; Initialize segments. -; __segment_init is assumed to use -; instruction set and to be reachable by BL from the ICODE segment -; (it is safest to link them in segment ICODE). - ldr r0,=__segment_init - mov lr, pc - bx r0 - - PUBLIC __main -?jump_to_main: - ldr lr,=?call_exit - ldr r0,=main -__main: - bx r0 - -;------------------------------------------------------------------------------ -;- Loop for ever -;--------------- -;- End of application. Normally, never occur. -;- Could jump on Software Reset ( B 0x0 ). -;------------------------------------------------------------------------------ -?call_exit: -End - b End - - - -;--------------------------------------------------------------- -; ?EXEPTION_VECTOR -; This module is only linked if needed for closing files. -;--------------------------------------------------------------- - PUBLIC AT91F_Default_FIQ_handler - PUBLIC AT91F_Default_IRQ_handler - PUBLIC AT91F_Spurious_handler - - CODE32 ; Always ARM mode after exeption - -AT91F_Default_FIQ_handler - b AT91F_Default_FIQ_handler - -AT91F_Default_IRQ_handler - b AT91F_Default_IRQ_handler - -AT91F_Spurious_handler - b AT91F_Spurious_handler - - ENDMOD - - END - diff --git a/Demo/ARM7_AT91SAM7S64_IAR/SrcIAR/Cstartup_SAM7.c b/Demo/ARM7_AT91SAM7S64_IAR/SrcIAR/Cstartup_SAM7.c deleted file mode 100644 index 90b3982b8..000000000 --- a/Demo/ARM7_AT91SAM7S64_IAR/SrcIAR/Cstartup_SAM7.c +++ /dev/null @@ -1,84 +0,0 @@ -//*---------------------------------------------------------------------------- -//* ATMEL Microcontroller Software Support - ROUSSET - -//*---------------------------------------------------------------------------- -//* The software is delivered "AS IS" without warranty or condition of any -//* kind, either express, implied or statutory. This includes without -//* limitation any warranty or condition with respect to merchantability or -//* fitness for any particular purpose, or against the infringements of -//* intellectual property rights of others. -//*---------------------------------------------------------------------------- -//* File Name : Cstartup_SAM7.c -//* Object : Low level initializations written in C for IAR -//* tools -//* Creation : 12/Jun/04 -//* -//*---------------------------------------------------------------------------- - - -// Include the board file description -#include "Board.h" - -// The following functions must be write in ARM mode this function called directly -// by exception vector -extern void AT91F_Spurious_handler(void); -extern void AT91F_Default_IRQ_handler(void); -extern void AT91F_Default_FIQ_handler(void); - -//*---------------------------------------------------------------------------- -//* \fn AT91F_LowLevelInit -//* \brief This function performs very low level HW initialization -//* this function can be use a Stack, depending the compilation -//* optimization mode -//*---------------------------------------------------------------------------- -void AT91F_LowLevelInit( void ); -void AT91F_LowLevelInit( void) @ "ICODE" -{ - int i; - AT91PS_PMC pPMC = AT91C_BASE_PMC; - //* Set Flash Waite sate - // Single Cycle Access at Up to 30 MHz, or 40 - // if MCK = 47923200 I have 50 Cycle for 1 useconde ( flied MC_FMR->FMCN - AT91C_BASE_MC->MC_FMR = ((AT91C_MC_FMCN)&(50 <<16)) | AT91C_MC_FWS_1FWS ; - - //* Watchdog Disable - AT91C_BASE_WDTC->WDTC_WDMR= AT91C_SYSC_WDDIS; - - //* Set MCK at 47 923 200 - // 1 Enabling the Main Oscillator: - // SCK = 1/32768 = 30.51 uSeconde - // Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms - pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | AT91C_CKGR_MOSCEN )); - // Wait the startup time - while(!(pPMC->PMC_SR & AT91C_PMC_MOSCS)); - // 2 Checking the Main Oscillator Frequency (Optional) - // 3 Setting PLL and divider: - // - div by 5 Fin = 3,6864 =(18,432 / 5) - // - Mul 25+1: Fout = 95,8464 =(3,6864 *26) - // for 96 MHz the erroe is 0.16% - // Field out NOT USED = 0 - // PLLCOUNT pll startup time esrtimate at : 0.844 ms - // PLLCOUNT 28 = 0.000844 /(1/32768) - pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x05) | - (AT91C_CKGR_PLLCOUNT & (28<<8)) | - (AT91C_CKGR_MUL & (25<<16))); - - // Wait the startup time - while(!(pPMC->PMC_SR & AT91C_PMC_LOCK)); - // 4. Selection of Master Clock and Processor Clock - // select the PLL clock divided by 2 - pPMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | AT91C_PMC_PRES_CLK_2 ; - - // Enable User Reset and set its minimal assertion to 960 us - AT91C_BASE_RSTC->RSTC_RMR = AT91C_SYSC_URSTEN | (0x4<<8) | (unsigned int) (0xA5<<24); - - - // Set up the default interrupts handler vectors - AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler ; - for (i=1;i < 31; i++) - { - AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler ; - } - AT91C_BASE_AIC->AIC_SPU = (int) AT91F_Spurious_handler ; - -} - diff --git a/Demo/ARM7_AT91SAM7S64_IAR/USB/USBSample.c b/Demo/ARM7_AT91SAM7S64_IAR/USB/USBSample.c deleted file mode 100644 index 5f1901823..000000000 --- a/Demo/ARM7_AT91SAM7S64_IAR/USB/USBSample.c +++ /dev/null @@ -1,1273 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - Sample interrupt driven USB device driver. This is a minimal implementation - for demonstration only. Although functional, it is not a full and compliant - implementation. - - The USB device enumerates as a simple 3 axis joystick, and once configured - transmits 3 axis of data which can be viewed from the USB host machine. - - This file implements the USB interrupt service routine, and a demo FreeRTOS - task. The interrupt service routine handles the USB hardware - taking a - snapshot of the USB status at the point of the interrupt. The task receives - the status information from the interrupt for processing at the task level. - - See the FreeRTOS.org WEB documentation for more information. -*/ - -/* - Changes from V2.5.5 - - + Descriptors that have a length that is an exact multiple of usbFIFO_LENGTH - can now be transmitted. To this end an extra parameter has been - added to the prvSendControlData() function, and the state - eSENDING_EVEN_DESCRIPTOR has been introduced. Thanks to Scott Miller for - assisting with this contribution. - - Changes from V2.6.0 - - + Replaced the duplicated RX_DATA_BK0 in the interrupt mask with the - RX_DATA_BK1. -*/ - -/* Standard includes. */ -#include - -/* Demo board includes. */ -#include "board.h" - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" - - -/* Descriptor type definitions. */ -#define usbDESCRIPTOR_TYPE_DEVICE ( 0x01 ) -#define usbDESCRIPTOR_TYPE_CONFIGURATION ( 0x02 ) -#define usbDESCRIPTOR_TYPE_STRING ( 0x03 ) - -/* USB request type definitions. */ -#define usbGET_REPORT_REQUEST ( 0x01 ) -#define usbGET_IDLE_REQUEST ( 0x02 ) -#define usbGET_PROTOCOL_REQUEST ( 0x03 ) -#define usbSET_REPORT_REQUEST ( 0x09 ) -#define usbSET_IDLE_REQUEST ( 0x0A ) -#define usbSET_PROTOCOL_REQUEST ( 0x0B ) -#define usbGET_CONFIGURATION_REQUEST ( 0x08 ) -#define usbGET_STATUS_REQUEST ( 0x00 ) -#define usbCLEAR_FEATURE_REQUEST ( 0x01 ) -#define usbSET_FEATURE_REQUEST ( 0x03 ) -#define usbSET_ADDRESS_REQUEST ( 0x05 ) -#define usbGET_DESCRIPTOR_REQUEST ( 0x06 ) -#define usbSET_CONFIGURATION_REQUEST ( 0x09 ) -#define usbGET_INTERFACE_REQUEST ( 0x0A ) -#define usbSET_INTERFACE_REQUEST ( 0x0B ) - - -/* Misc USB definitions. */ -#define usbDEVICE_CLASS_VENDOR_SPECIFIC ( 0xFF ) -#define usbBUS_POWERED ( 0x80 ) -#define usbHID_REPORT_DESCRIPTOR ( 0x22 ) -#define AT91C_UDP_TRANSCEIVER_ENABLE ( *( ( unsigned long * ) 0xfffb0074 ) ) - -/* Index to the various string. */ -#define usbLANGUAGE_STRING ( 0 ) -#define usbMANUFACTURER_STRING ( 1 ) -#define usbPRODUCT_STRING ( 2 ) -#define usbCONFIGURATION_STRING ( 3 ) -#define usbINTERFACE_STRING ( 4 ) - -/* Data indexes for reading the request from the xISRStatus.ucFifoData[] -into xUSB_REQUEST. The data order is designed for speed - so looks a -little odd. */ -#define usbREQUEST_TYPE_INDEX ( 7 ) -#define usbREQUEST_INDEX ( 6 ) -#define usbVALUE_HIGH_BYTE ( 4 ) -#define usbVALUE_LOW_BYTE ( 5 ) -#define usbINDEX_HIGH_BYTE ( 2 ) -#define usbINDEX_LOW_BYTE ( 3 ) -#define usbLENGTH_HIGH_BYTE ( 0 ) -#define usbLENGTH_LOW_BYTE ( 1 ) - -/* Misc application definitions. */ -#define usbINTERRUPT_PRIORITY ( 3 ) -#define usbQUEUE_LENGTH ( 0x3 ) /* Must have all bits set! */ -#define usbFIFO_LENGTH ( ( unsigned portLONG ) 8 ) -#define usbEND_POINT_0 ( 0 ) -#define usbEND_POINT_1 ( 1 ) -#define usbXUP ( 1 ) -#define usbXDOWN ( 2 ) -#define usbYUP ( 3 ) -#define usbYDOWN ( 4 ) -#define usbMAX_COORD ( 120 ) -#define usbMAX_TX_MESSAGE_SIZE ( 128 ) -#define usbRX_COUNT_MASK ( ( unsigned portLONG ) 0x7ff ) -#define AT91C_UDP_STALLSENT AT91C_UDP_ISOERROR -#define usbSHORTEST_DELAY ( ( portTickType ) 1 ) -#define usbINIT_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS ) -#define usbSHORT_DELAY ( ( portTickType ) 50 / portTICK_RATE_MS ) -#define usbEND_POINT_RESET_MASK ( ( unsigned portLONG ) 0x0f ) -#define usbDATA_INC ( ( portCHAR ) 5 ) -#define usbEXPECTED_NUMBER_OF_BYTES ( ( unsigned portLONG ) 8 ) - -/* Control request types. */ -#define usbSTANDARD_DEVICE_REQUEST ( 0 ) -#define usbSTANDARD_INTERFACE_REQUEST ( 1 ) -#define usbSTANDARD_END_POINT_REQUEST ( 2 ) -#define usbCLASS_INTERFACE_REQUEST ( 5 ) - -/*-----------------------------------------------------------*/ - -/* Structure used to take a snapshot of the USB status from within the ISR. */ -typedef struct X_ISR_STATUS -{ - unsigned portLONG ulISR; - unsigned portLONG ulCSR0; - unsigned portCHAR ucFifoData[ 8 ]; -} xISRStatus; - -/* Structure used to hold the received requests. */ -typedef struct -{ - unsigned portCHAR ucReqType; - unsigned portCHAR ucRequest; - unsigned portSHORT usValue; - unsigned portSHORT usIndex; - unsigned portSHORT usLength; -} xUSB_REQUEST; - -typedef enum -{ - eNOTHING, - eJUST_RESET, - eJUST_GOT_CONFIG, - eJUST_GOT_ADDRESS, - eSENDING_EVEN_DESCRIPTOR, - eREADY_TO_SEND -} eDRIVER_STATE; - -/* Structure used to control the data being sent to the host. */ -typedef struct -{ - unsigned portCHAR ucTxBuffer[ usbMAX_TX_MESSAGE_SIZE ]; - unsigned portLONG ulNextCharIndex; - unsigned portLONG ulTotalDataLength; -} xTX_MESSAGE; - -/*-----------------------------------------------------------*/ - -/* - * The USB interrupt service routine. This takes a snapshot of the USB - * device at the time of the interrupt, clears the interrupts, and posts - * the data to the USB processing task. - */ -__arm void vUSB_ISR( void ); - -/* - * Called after the bus reset interrupt - this function readies all the - * end points for communication. - */ -static void prvResetEndPoints( void ); - -/* - * Setup the USB hardware, install the interrupt service routine and - * initialise all the state variables. - */ -static void vInitUSBInterface( void ); - -/* - * Decode and act upon an interrupt generated by the control end point. - */ -static void prvProcessEndPoint0Interrupt( xISRStatus *pxMessage ); - -/* - * For simplicity requests are separated into device, interface, class - * interface and end point requests. - * - * Decode and handle standard device requests originating on the control - * end point. - */ -static void prvHandleStandardDeviceRequest( xUSB_REQUEST *pxRequest ); - -/* - * For simplicity requests are separated into device, interface, class - * interface and end point requests. - * - * Decode and handle standard interface requests originating on the control - * end point. - */ -static void prvHandleStandardInterfaceRequest( xUSB_REQUEST *pxRequest ); - -/* - * For simplicity requests are separated into device, interface, class - * interface and end point requests. - * - * Decode and handle standard end point requests originating on the control - * end point. - */ -static void prvHandleStandardEndPointRequest( xUSB_REQUEST *pxRequest ); - -/* - * For simplicity requests are separated into device, interface, class - * interface and end point requests. - * - * Decode and handle the class interface requests. - */ -static void prvHandleClassInterfaceRequest( xUSB_REQUEST *pxRequest ); - -/* - * Setup the Tx buffer to send data in response to a control request. - * - * The data to be transmitted is buffered, the state variables are updated, - * then prvSendNextSegment() is called to start the transmission off. Once - * the first segment has been sent the remaining segments are transmitted - * in response to TXCOMP interrupts until the entire buffer has been - * sent. - */ -static void prvSendControlData( unsigned portCHAR *pucData, unsigned portSHORT usRequestedLength, unsigned portLONG ulLengthLeftToSend, portLONG lSendingDescriptor ); - -/* - * Examine the Tx buffer to see if there is any more data to be transmitted. - * - * If there is data to be transmitted then send the next segment. A segment - * can have a maximum of 8 bytes (this is defined as the maximum for the end - * point by the descriptor). The final segment may be less than 8 bytes if - * the total data length was not an exact multiple of 8. - */ -static void prvSendNextSegment( void ); - -/* - * A stall condition is forced each time the host makes a request that is not - * supported by this minimal implementation. - * - * A stall is forced by setting the appropriate bit in the end points control - * and status register. - */ -static void prvSendStall( void ); - -/* - * A NULL (or zero length packet) is transmitted in acknowledge the reception - * of certain events from the host. - */ -static void prvUSBTransmitNull( void ); - -/* - * When the host requests a descriptor this function is called to determine - * which descriptor is being requested and start its transmission. - */ -static void prvGetStandardInterfaceDescriptor( xUSB_REQUEST *pxRequest ); - -/* - * This demo USB device enumerates as a simple 3 axis joystick. Once - * configured this function is periodically called to generate some sample - * joystick data. - * - * The x and y axis are made to move in a square. The z axis is made to - * repeatedly increment up to its maximum. - */ -static void prvTransmitSampleValues( void ); - -/* - * The created task to handle the USB demo functionality. - */ -void vUSBDemoTask( void *pvParameters ); - -/*-----------------------------------------------------------*/ - -/* - - DESCRIPTOR DEFINITIONS - -*/ - -/* String descriptors used during the enumeration process. -These take the form: - -{ - Length of descriptor, - Descriptor type, - Data -} -*/ -const portCHAR pxLanguageStringDescriptor[] = -{ - 4, - usbDESCRIPTOR_TYPE_STRING, - 0x09, 0x04 -}; - -const portCHAR pxManufacturerStringDescriptor[] = -{ - 18, - usbDESCRIPTOR_TYPE_STRING, - - 'F', 0x00, - 'r', 0x00, - 'e', 0x00, - 'e', 0x00, - 'R', 0x00, - 'T', 0x00, - 'O', 0x00, - 'S', 0x00 -}; - -const portCHAR pxProductStringDescriptor[] = -{ - 44, - usbDESCRIPTOR_TYPE_STRING, - - 'F', 0x00, - 'r', 0x00, - 'e', 0x00, - 'e', 0x00, - 'R', 0x00, - 'T', 0x00, - 'O', 0x00, - 'S', 0x00, - '.', 0x00, - 'o', 0x00, - 'r', 0x00, - 'g', 0x00, - ' ', 0x00, - 'J', 0x00, - 'o', 0x00, - 'y', 0x00, - 's', 0x00, - 't', 0x00, - 'i', 0x00, - 'c', 0x00, - 'k', 0x00 -}; - -const portCHAR pxConfigurationStringDescriptor[] = -{ - 38, - usbDESCRIPTOR_TYPE_STRING, - - 'C', 0x00, - 'o', 0x00, - 'n', 0x00, - 'f', 0x00, - 'i', 0x00, - 'g', 0x00, - 'u', 0x00, - 'r', 0x00, - 'a', 0x00, - 't', 0x00, - 'i', 0x00, - 'o', 0x00, - 'n', 0x00, - ' ', 0x00, - 'N', 0x00, - 'a', 0x00, - 'm', 0x00, - 'e', 0x00 -}; - -const portCHAR pxInterfaceStringDescriptor[] = -{ - 30, - usbDESCRIPTOR_TYPE_STRING, - - 'I', 0x00, - 'n', 0x00, - 't', 0x00, - 'e', 0x00, - 'r', 0x00, - 'f', 0x00, - 'a', 0x00, - 'c', 0x00, - 'e', 0x00, - ' ', 0x00, - 'N', 0x00, - 'a', 0x00, - 'm', 0x00, - 'e', 0x00 -}; - -/* Enumeration descriptors. */ -const portCHAR pxReportDescriptor[] = -{ - 0x05, 0x01, /* USAGE_PAGE (Generic Desktop) */ - 0x09, 0x04, /* USAGE (Joystick) */ - 0xa1, 0x01, /* COLLECTION (Application) */ - 0x05, 0x01, /* USAGE_PAGE (Generic Desktop) */ - 0x09, 0x01, /* USAGE (Pointer) */ - 0xa1, 0x00, /* COLLECTION (Physical) */ - 0x09, 0x30, /* USAGE (X) */ - 0x09, 0x31, /* USAGE (Y) */ - 0x09, 0x32, /* USAGE (Z) */ - 0x15, 0x81, /* LOGICAL_MINIMUM (-127) */ - 0x25, 0x7f, /* LOGICAL_MAXIMUM (127) */ - 0x75, 0x08, /* REPORT_SIZE (8) */ - 0x95, 0x03, /* REPORT_COUNT (3) */ - 0x81, 0x02, /* INPUT (Data,Var,Abs) */ - 0xc0, /* END_COLLECTION */ - 0xc0 /* END_COLLECTION */ -}; - -const char pxDeviceDescriptor[] = -{ - /* Device descriptor */ - 0x12, /* bLength */ - 0x01, /* bDescriptorType */ - 0x10, 0x01, /* bcdUSBL */ - usbDEVICE_CLASS_VENDOR_SPECIFIC, /* bDeviceClass: */ - 0x00, /* bDeviceSubclass: */ - 0x00, /* bDeviceProtocol: */ - 0x08, /* bMaxPacketSize0 */ - 0xFF, 0xFF, /* idVendorL */ - 0x01, 0x00, /* idProductL */ - 0x00, 0x01, /* bcdDeviceL */ - usbMANUFACTURER_STRING, /* iManufacturer */ - usbPRODUCT_STRING, /* iProduct */ - 0x00, /* SerialNumber */ - 0x01 /* bNumConfigs */ -}; - -const char pxConfigDescriptor[] = { - /* Configuration 1 descriptor */ - 0x09, /* CbLength */ - 0x02, /* CbDescriptorType */ - 0x22, 0x00, /* CwTotalLength 2 EP + Control */ - 0x01, /* CbNumInterfaces */ - 0x01, /* CbConfigurationValue */ - usbCONFIGURATION_STRING,/* CiConfiguration */ - usbBUS_POWERED, /* CbmAttributes Bus powered + Remote Wakeup*/ - 0x32, /* CMaxPower: 100mA */ - - /* Joystick Interface Descriptor Requirement */ - 0x09, /* bLength */ - 0x04, /* bDescriptorType */ - 0x00, /* bInterfaceNumber */ - 0x00, /* bAlternateSetting */ - 0x01, /* bNumEndpoints */ - 0x03, /* bInterfaceClass: HID code */ - 0x00, /* bInterfaceSubclass */ - 0x00, /* bInterfaceProtocol */ - usbINTERFACE_STRING,/* iInterface */ - - /* HID Descriptor */ - 0x09, /* bLength */ - 0x21, /* bDescriptor type: HID Descriptor Type */ - 0x00, 0x01, /* bcdHID */ - 0x00, /* bCountryCode */ - 0x01, /* bNumDescriptors */ - usbHID_REPORT_DESCRIPTOR, /* bDescriptorType */ - sizeof( pxReportDescriptor ), 0x00, /* wItemLength */ - - /* Endpoint 1 descriptor */ - 0x07, /* bLength */ - 0x05, /* bDescriptorType */ - 0x81, /* bEndpointAddress, Endpoint 01 - IN */ - 0x03, /* bmAttributes INT */ - 0x03, 0x00, /* wMaxPacketSize: 3 bytes (x, y, z) */ - 0x0A /* bInterval */ -}; - -/*-----------------------------------------------------------*/ - -/* File scope state variables. */ -static unsigned portCHAR ucUSBConfig = ( unsigned portCHAR ) 0; -static unsigned portLONG ulReceivedAddress = ( unsigned portLONG ) 0; -static eDRIVER_STATE eDriverState = eNOTHING; - -/* Array in which the USB interrupt status is passed between the ISR and task. */ -static xISRStatus xISRMessages[ usbQUEUE_LENGTH + 1 ]; - -/* Structure used to control the characters being sent to the host. */ -static xTX_MESSAGE pxCharsForTx; - -/* Queue used to pass messages between the ISR and the task. */ -static xQueueHandle xUSBInterruptQueue; - -/* ISR entry has to be written in the asm file as we want a context switch -to occur from within the ISR. See the port documentation on the FreeRTOS.org -WEB site for more information. */ -extern void vUSBISREntry( void ); - -/*-----------------------------------------------------------*/ - -/* Macros to manipulate the control and status registers. These registers -cannot be accessed using a direct read modify write operation outside of the -ISR as some bits are left unchanged by writing with a 0, and some are left -unchanged by writing with a 1. */ - -#define usbINT_CLEAR_MASK (AT91C_UDP_TXCOMP | AT91C_UDP_STALLSENT | AT91C_UDP_RXSETUP | AT91C_UDP_RX_DATA_BK0 | AT91C_UDP_RX_DATA_BK1 ) - -#define usbCSR_SET_BIT( pulValueNow, ulBit ) \ -{ \ - /* Set TXCOMP, RX_DATA_BK0, RXSETUP, */ \ - /* STALLSENT and RX_DATA_BK1 to 1 so the */ \ - /* write has no effect. */ \ - ( * ( ( unsigned portLONG * ) pulValueNow ) ) |= ( unsigned portLONG ) 0x4f; \ - \ - /* Clear the FORCE_STALL and TXPKTRDY bits */ \ - /* so the write has no effect. */ \ - ( * ( ( unsigned portLONG * ) pulValueNow ) ) &= ( unsigned portLONG ) 0xffffffcf; \ - \ - /* Set whichever bit we want set. */ \ - ( * ( ( unsigned portLONG * ) pulValueNow ) ) |= ( ulBit ); \ -} - -#define usbCSR_CLEAR_BIT( pulValueNow, ulBit ) \ -{ \ - /* Set TXCOMP, RX_DATA_BK0, RXSETUP, */ \ - /* STALLSENT and RX_DATA_BK1 to 1 so the */ \ - /* write has no effect. */ \ - ( * ( ( unsigned portLONG * ) pulValueNow ) ) |= ( unsigned portLONG ) 0x4f; \ - \ - /* Clear the FORCE_STALL and TXPKTRDY bits */ \ - /* so the write has no effect. */ \ - ( * ( ( unsigned portLONG * ) pulValueNow ) ) &= ( unsigned portLONG ) 0xffffffcf; \ - \ - /* Clear whichever bit we want clear. */ \ - ( * ( ( unsigned portLONG * ) pulValueNow ) ) &= ( ~ulBit ); \ -} - -/*-----------------------------------------------------------*/ - -__arm void vUSB_ISR( void ) -{ -portBASE_TYPE xTaskWokenByPost = pdFALSE; -static volatile unsigned portLONG ulNextMessage = 0; -xISRStatus *pxMessage; -unsigned portLONG ulTemp, ulRxBytes; - - /* Take the next message from the queue. Note that usbQUEUE_LENGTH *must* - be all 1's, as in 0x01, 0x03, 0x07, etc. */ - pxMessage = &( xISRMessages[ ( ulNextMessage & usbQUEUE_LENGTH ) ] ); - ulNextMessage++; - - /* Take a snapshot of the current USB state for processing at the task - level. */ - pxMessage->ulISR = AT91C_BASE_UDP->UDP_ISR; - pxMessage->ulCSR0 = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ]; - - /* Clear the interrupts from the ICR register. The bus end interrupt is - cleared separately as it does not appear in the mask register. */ - AT91C_BASE_UDP->UDP_ICR = AT91C_BASE_UDP->UDP_IMR | AT91C_UDP_ENDBUSRES; - - /* If there are bytes in the FIFO then we have to retrieve them here. - Ideally this would be done at the task level. However we need to clear the - RXSETUP interrupt before leaving the ISR, and this may cause the data in - the FIFO to be overwritten. Also the DIR bit has to be changed before the - RXSETUP bit is cleared (as per the SAM7 manual). */ - ulTemp = pxMessage->ulCSR0; - - /* Are there any bytes in the FIFO? */ - ulRxBytes = ulTemp >> 16; - ulRxBytes &= usbRX_COUNT_MASK; - - /* With this minimal implementation we are only interested in receiving - setup bytes on the control end point. */ - if( ( ulRxBytes > 0 ) && ( ulTemp & AT91C_UDP_RXSETUP ) ) - { - /* Take off 1 for a zero based index. */ - while( ulRxBytes > 0 ) - { - ulRxBytes--; - pxMessage->ucFifoData[ ulRxBytes ] = AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_0 ]; - } - - /* The direction must be changed first. */ - usbCSR_SET_BIT( &ulTemp, ( AT91C_UDP_DIR ) ); - AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulTemp; - } - - /* Must write zero's to TXCOMP, STALLSENT, RXSETUP, and the RX DATA - registers to clear the interrupts in the CSR register. */ - usbCSR_CLEAR_BIT( &ulTemp, usbINT_CLEAR_MASK ); - AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulTemp; - - /* Also clear the interrupts in the CSR1 register. */ - ulTemp = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ]; - usbCSR_CLEAR_BIT( &ulTemp, usbINT_CLEAR_MASK ); - AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] = ulTemp; - - /* The message now contains the entire state and optional data from - the USB interrupt. This can now be posted on the Rx queue ready for - processing at the task level. */ - xTaskWokenByPost = xQueueSendFromISR( xUSBInterruptQueue, &pxMessage, xTaskWokenByPost ); - - /* We may want to switch to the USB task, if this message has made - it the highest priority task that is ready to execute. */ - portEND_SWITCHING_ISR( xTaskWokenByPost ); - - /* Clear the AIC ready for the next interrupt. */ - AT91C_BASE_AIC->AIC_EOICR = 0; -} -/*-----------------------------------------------------------*/ - -void vUSBDemoTask( void *pvParameters ) -{ -xISRStatus *pxMessage; - - /* The parameters are not used in this task. */ - ( void ) pvParameters; - - /* Init USB device */ - portENTER_CRITICAL(); - vInitUSBInterface(); - portEXIT_CRITICAL(); - - /* Process interrupts as they arrive. The ISR takes a snapshot of the - interrupt status then posts the information on this queue for processing - at the task level. This simple demo implementation only processes - a few interrupt sources. */ - for( ;; ) - { - if( xQueueReceive( xUSBInterruptQueue, &pxMessage, usbSHORT_DELAY ) ) - { - if( pxMessage->ulISR & AT91C_UDP_EPINT0 ) - { - /* Process end point 0 interrupt. */ - prvProcessEndPoint0Interrupt( pxMessage ); - } - - if( pxMessage->ulISR & AT91C_UDP_ENDBUSRES ) - { - /* Process an end of bus reset interrupt. */ - prvResetEndPoints(); - } - } - else - { - /* The ISR did not post any data for us to process on the queue, so - just generate and send some sample data. */ - if( eDriverState == eREADY_TO_SEND ) - { - prvTransmitSampleValues(); - } - } - } -} -/*-----------------------------------------------------------*/ - -static void prvTransmitSampleValues( void ) -{ -unsigned portLONG ulStatus; -static portLONG lState = usbXUP; - -/* Variables to hold dummy x, y and z joystick axis data. */ -static signed portCHAR x = 0, y = 0, z = 0; - - /* Generate some sample data in the x and y axis - draw a square. */ - switch( lState ) - { - case usbXUP : x += usbDATA_INC; - if( x >= usbMAX_COORD ) - { - lState = usbYUP; - } - break; - - case usbXDOWN : x -= usbDATA_INC; - if( x <= -usbMAX_COORD ) - { - lState = usbYDOWN; - } - break; - - case usbYUP : y += usbDATA_INC; - if( y >= usbMAX_COORD ) - { - lState = usbXDOWN; - } - break; - - case usbYDOWN : y -= usbDATA_INC; - if( y <= -usbMAX_COORD ) - { - lState = usbXUP; - } - break; - } - - /* Just make the z axis go up and down. */ - z += usbDATA_INC; - - /* Can we place data in the fifo? */ - if( !( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] & AT91C_UDP_TXPKTRDY ) ) - { - /* Write our sample data to the fifo. */ - AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_1 ] = x; - AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_1 ] = y; - AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_1 ] = z; - - /* Send the data. */ - portENTER_CRITICAL(); - { - ulStatus = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ]; - usbCSR_SET_BIT( &ulStatus, ( AT91C_UDP_TXPKTRDY ) ); - AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] = ulStatus; - } - portEXIT_CRITICAL(); - } -} -/*-----------------------------------------------------------*/ - -static void prvUSBTransmitNull( void ) -{ -unsigned portLONG ulStatus; - - /* Wait until the FIFO is free - even though we are not going to use it. - THERE IS NO TIMEOUT HERE! */ - while( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] & AT91C_UDP_TXPKTRDY ) - { - vTaskDelay( usbSHORTEST_DELAY ); - } - - portENTER_CRITICAL(); - { - /* Set the length of data to send to equal the index of the next byte - to send. This will prevent the ACK to this NULL packet causing any - further data transmissions. */ - pxCharsForTx.ulTotalDataLength = pxCharsForTx.ulNextCharIndex; - - /* Set the TXPKTRDY bit to cause a transmission with no data. */ - ulStatus = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ]; - usbCSR_SET_BIT( &ulStatus, ( AT91C_UDP_TXPKTRDY ) ); - AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulStatus; - } - portEXIT_CRITICAL(); -} -/*-----------------------------------------------------------*/ - -static void prvSendStall( void ) -{ -unsigned portLONG ulStatus; - - portENTER_CRITICAL(); - { - /* Force a stall by simply setting the FORCESTALL bit in the CSR. */ - ulStatus = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ]; - usbCSR_SET_BIT( &ulStatus, AT91C_UDP_FORCESTALL ); - AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulStatus; - } - portEXIT_CRITICAL(); -} -/*-----------------------------------------------------------*/ - -static void prvResetEndPoints( void ) -{ -unsigned portLONG ulTemp; - - eDriverState = eJUST_RESET; - - /* Reset all the end points. */ - AT91C_BASE_UDP->UDP_RSTEP = usbEND_POINT_RESET_MASK; - AT91C_BASE_UDP->UDP_RSTEP = ( unsigned portLONG ) 0x00; - - /* Enable data to be sent and received. */ - AT91C_BASE_UDP->UDP_FADDR = AT91C_UDP_FEN; - - /* Repair the configuration end point. */ - portENTER_CRITICAL(); - { - ulTemp = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ]; - usbCSR_SET_BIT( &ulTemp, ( ( unsigned portLONG ) ( AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_CTRL ) ) ); - AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulTemp; - AT91F_UDP_EnableIt( AT91C_BASE_UDP, AT91C_UDP_EPINT0 ); - } - portEXIT_CRITICAL(); -} -/*-----------------------------------------------------------*/ - -static void prvProcessEndPoint0Interrupt( xISRStatus *pxMessage ) -{ - if( pxMessage->ulCSR0 & AT91C_UDP_RX_DATA_BK0 ) - { - /* We only expect to receive zero length data here as ACK's. - Set the data pointer to the end of the current Tx packet to - ensure we don't send out any more data. */ - pxCharsForTx.ulNextCharIndex = pxCharsForTx.ulTotalDataLength; - } - - if( pxMessage->ulCSR0 & AT91C_UDP_TXCOMP ) - { - /* We received a TX complete interrupt. What we do depends on - what we sent to get this interrupt. */ - - if( eDriverState == eJUST_GOT_CONFIG ) - { - /* We sent an acknowledgement of a SET_CONFIG request. We - are now at the end of the enumeration. */ - AT91C_BASE_UDP->UDP_GLBSTATE = AT91C_UDP_CONFG; - - /* Read the end point for data transfer. */ - portENTER_CRITICAL(); - { - unsigned portLONG ulTemp; - - ulTemp = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ]; - usbCSR_SET_BIT( &ulTemp, AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_INT_IN ); - AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] = ulTemp; - AT91F_UDP_EnableIt( AT91C_BASE_UDP, AT91C_UDP_EPINT1 ); - } - portEXIT_CRITICAL(); - - eDriverState = eREADY_TO_SEND; - } - else if( eDriverState == eJUST_GOT_ADDRESS ) - { - /* We sent an acknowledgement of a SET_ADDRESS request. Move - to the addressed state. */ - if( ulReceivedAddress != ( unsigned portLONG ) 0 ) - { - AT91C_BASE_UDP->UDP_GLBSTATE = AT91C_UDP_FADDEN; - } - else - { - AT91C_BASE_UDP->UDP_GLBSTATE = 0; - } - - AT91C_BASE_UDP->UDP_FADDR = ( AT91C_UDP_FEN | ulReceivedAddress ); - eDriverState = eNOTHING; - } - else - { - /* The TXCOMP was not for any special type of transmission. See - if there is any more data to send. */ - prvSendNextSegment(); - } - } - - if( pxMessage->ulCSR0 & AT91C_UDP_RXSETUP ) - { - xUSB_REQUEST xRequest; - unsigned portCHAR ucRequest; - unsigned portLONG ulRxBytes; - - /* A data packet is available. */ - ulRxBytes = pxMessage->ulCSR0 >> 16; - ulRxBytes &= usbRX_COUNT_MASK; - - if( ulRxBytes >= usbEXPECTED_NUMBER_OF_BYTES ) - { - /* Create an xUSB_REQUEST variable from the raw bytes array. */ - - xRequest.ucReqType = pxMessage->ucFifoData[ usbREQUEST_TYPE_INDEX ]; - xRequest.ucRequest = pxMessage->ucFifoData[ usbREQUEST_INDEX ]; - - /* NOT PORTABLE CODE! */ - xRequest.usValue = pxMessage->ucFifoData[ usbVALUE_HIGH_BYTE ]; - xRequest.usValue <<= 8; - xRequest.usValue |= pxMessage->ucFifoData[ usbVALUE_LOW_BYTE ]; - - xRequest.usIndex = pxMessage->ucFifoData[ usbINDEX_HIGH_BYTE ]; - xRequest.usIndex <<= 8; - xRequest.usIndex |= pxMessage->ucFifoData[ usbINDEX_LOW_BYTE ]; - - xRequest.usLength = pxMessage->ucFifoData[ usbLENGTH_HIGH_BYTE ]; - xRequest.usLength <<= 8; - xRequest.usLength |= pxMessage->ucFifoData[ usbLENGTH_LOW_BYTE ]; - - /* Manipulate the ucRequestType and the ucRequest parameters to - generate a zero based request selection. This is just done to - break up the requests into subsections for clarity. The - alternative would be to have more huge switch statement that would - be difficult to optimise. */ - ucRequest = ( ( xRequest.ucReqType & 0x60 ) >> 3 ); - ucRequest |= ( xRequest.ucReqType & 0x03 ); - - switch( ucRequest ) - { - case usbSTANDARD_DEVICE_REQUEST: - /* Standard Device request */ - prvHandleStandardDeviceRequest( &xRequest ); - break; - - case usbSTANDARD_INTERFACE_REQUEST: - /* Standard Interface request */ - prvHandleStandardInterfaceRequest( &xRequest ); - break; - - case usbSTANDARD_END_POINT_REQUEST: - /* Standard Endpoint request */ - prvHandleStandardEndPointRequest( &xRequest ); - break; - - case usbCLASS_INTERFACE_REQUEST: - /* Class Interface request */ - prvHandleClassInterfaceRequest( &xRequest ); - break; - - default: /* This is not something we want to respond to. */ - prvSendStall(); - } - } - } -} -/*-----------------------------------------------------------*/ - -static void prvGetStandardDeviceDescriptor( xUSB_REQUEST *pxRequest ) -{ - /* The type is in the high byte. Return whatever has been requested. */ - switch( ( pxRequest->usValue & 0xff00 ) >> 8 ) - { - case usbDESCRIPTOR_TYPE_DEVICE: - prvSendControlData( ( unsigned portCHAR * ) &pxDeviceDescriptor, pxRequest->usLength, sizeof( pxDeviceDescriptor ), pdTRUE ); - break; - - case usbDESCRIPTOR_TYPE_CONFIGURATION: - prvSendControlData( ( unsigned portCHAR * ) &( pxConfigDescriptor ), pxRequest->usLength, sizeof( pxConfigDescriptor ), pdTRUE ); - break; - - case usbDESCRIPTOR_TYPE_STRING: - - /* The index to the string descriptor is the lower byte. */ - switch( pxRequest->usValue & 0xff ) - { - case usbLANGUAGE_STRING: - prvSendControlData( ( unsigned portCHAR * ) &pxLanguageStringDescriptor, pxRequest->usLength, sizeof(pxLanguageStringDescriptor), pdTRUE ); - break; - - case usbMANUFACTURER_STRING: - prvSendControlData( ( unsigned portCHAR * ) &pxManufacturerStringDescriptor, pxRequest->usLength, sizeof( pxManufacturerStringDescriptor ), pdTRUE ); - break; - - case usbPRODUCT_STRING: - prvSendControlData( ( unsigned portCHAR * ) &pxProductStringDescriptor, pxRequest->usLength, sizeof( pxProductStringDescriptor ), pdTRUE ); - break; - - case usbCONFIGURATION_STRING: - prvSendControlData( ( unsigned portCHAR * ) &pxConfigurationStringDescriptor, pxRequest->usLength, sizeof( pxConfigurationStringDescriptor ), pdTRUE ); - break; - - case usbINTERFACE_STRING: - prvSendControlData( ( unsigned portCHAR * ) &pxInterfaceStringDescriptor, pxRequest->usLength, sizeof( pxInterfaceStringDescriptor ), pdTRUE ); - break; - - default: - /* Don't know what this string is. */ - prvSendStall(); - break; - } - - break; - - default: - /* We are not responding to anything else. */ - prvSendStall(); - break; - } -} -/*-----------------------------------------------------------*/ - -static void prvHandleStandardDeviceRequest( xUSB_REQUEST *pxRequest ) -{ -unsigned portSHORT usStatus = 0; - - switch( pxRequest->ucRequest ) - { - case usbGET_STATUS_REQUEST: - /* Just send two byte dummy status. */ - prvSendControlData( ( unsigned portCHAR * ) &usStatus, sizeof( usStatus ), sizeof( usStatus ), pdFALSE ); - break; - - case usbGET_DESCRIPTOR_REQUEST: - /* Send device descriptor */ - prvGetStandardDeviceDescriptor( pxRequest ); - break; - - case usbGET_CONFIGURATION_REQUEST: - /* Send selected device configuration */ - prvSendControlData( ( unsigned portCHAR * ) &ucUSBConfig, sizeof( ucUSBConfig ), sizeof( ucUSBConfig ), pdFALSE ); - break; - - case usbSET_FEATURE_REQUEST: - prvUSBTransmitNull(); - break; - - case usbSET_ADDRESS_REQUEST: - - /* Acknowledge the SET_ADDRESS, but (according to the manual) we - cannot actually move to the addressed state until we get a TXCOMP - interrupt from this NULL packet. Therefore we just remember the - address and set our state so we know we have received the address. */ - prvUSBTransmitNull(); - eDriverState = eJUST_GOT_ADDRESS; - ulReceivedAddress = ( unsigned portLONG ) pxRequest->usValue; - break; - - case usbSET_CONFIGURATION_REQUEST: - - /* Acknowledge the SET_CONFIGURATION, but (according to the manual) - we cannot actually move to the configured state until we get a - TXCOMP interrupt from this NULL packet. Therefore we just remember the - config and set our state so we know we have received the go ahead. */ - ucUSBConfig = ( unsigned portCHAR ) ( pxRequest->usValue & 0xff ); - eDriverState = eJUST_GOT_CONFIG; - prvUSBTransmitNull(); - break; - - default: - - /* We don't answer to anything else. */ - prvSendStall(); - break; - } -} -/*-----------------------------------------------------------*/ - -static void prvHandleClassInterfaceRequest( xUSB_REQUEST *pxRequest ) -{ - switch( pxRequest->ucRequest ) - { - case usbSET_IDLE_REQUEST: - prvUSBTransmitNull(); - break; - - /* This minimal implementation ignores these. */ - case usbGET_REPORT_REQUEST: - case usbGET_IDLE_REQUEST: - case usbGET_PROTOCOL_REQUEST: - case usbSET_REPORT_REQUEST: - case usbSET_PROTOCOL_REQUEST: - default: - - prvSendStall(); - break; - } -} -/*-----------------------------------------------------------*/ - -static void prvGetStandardInterfaceDescriptor( xUSB_REQUEST *pxRequest ) -{ - switch( ( pxRequest->usValue & ( unsigned portSHORT ) 0xff00 ) >> 8 ) - { - case usbHID_REPORT_DESCRIPTOR: - prvSendControlData( ( unsigned portCHAR * ) pxReportDescriptor, pxRequest->usLength, sizeof( pxReportDescriptor ), pdTRUE ); - break; - - default: - - /* Don't expect to send any others. */ - prvSendStall(); - break; - } -} -/*-----------------------------------------------------------*/ - -static void prvHandleStandardInterfaceRequest( xUSB_REQUEST *pxRequest ) -{ -unsigned portSHORT usStatus = 0; - - switch( pxRequest->ucRequest ) - { - case usbGET_STATUS_REQUEST: - /* Send dummy 2 bytes. */ - prvSendControlData( ( unsigned portCHAR * ) &usStatus, sizeof( usStatus ), sizeof( usStatus ), pdFALSE ); - break; - - case usbGET_DESCRIPTOR_REQUEST: - prvGetStandardInterfaceDescriptor( pxRequest ); - break; - - /* This minimal implementation does not respond to these. */ - case usbGET_INTERFACE_REQUEST: - case usbSET_FEATURE_REQUEST: - case usbSET_INTERFACE_REQUEST: - - default: - prvSendStall(); - break; - } -} -/*-----------------------------------------------------------*/ - -static void prvHandleStandardEndPointRequest( xUSB_REQUEST *pxRequest ) -{ - switch( pxRequest->ucRequest ) - { - /* This minimal implementation does not expect to respond to these. */ - case usbGET_STATUS_REQUEST: - case usbCLEAR_FEATURE_REQUEST: - case usbSET_FEATURE_REQUEST: - - default: - prvSendStall(); - break; - } -} -/*-----------------------------------------------------------*/ - -static void vInitUSBInterface( void ) -{ -volatile unsigned portLONG ulTemp; - - /* Create the queue used to communicate between the USB ISR and task. */ - xUSBInterruptQueue = xQueueCreate( usbQUEUE_LENGTH + 1, sizeof( xISRStatus * ) ); - - /* Initialise a few state variables. */ - pxCharsForTx.ulNextCharIndex = ( unsigned portLONG ) 0; - ucUSBConfig = ( unsigned portCHAR ) 0; - eDriverState = eNOTHING; - - /* HARDWARE SETUP */ - - /* Set the PLL USB Divider */ - AT91C_BASE_CKGR->CKGR_PLLR |= AT91C_CKGR_USBDIV_1; - - /* Enables the 48MHz USB clock UDPCK and System Peripheral USB Clock. */ - AT91C_BASE_PMC->PMC_SCER = AT91C_PMC_UDP; - AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_UDP); - - /* Setup the PIO for the USB pull up resistor. */ - AT91F_PIO_CfgOutput(AT91C_BASE_PIOA,AT91C_PIO_PA16); - - /* Start without the pullup - this will get set at the end of this - function. */ - AT91F_PIO_SetOutput( AT91C_BASE_PIOA, AT91C_PIO_PA16 ); - - /* When using the USB debugger the peripheral registers do not always get - set to the correct default values. To make sure set the relevant registers - manually here. */ - AT91C_BASE_UDP->UDP_IDR = ( unsigned portLONG ) 0xffffffff; - AT91C_BASE_UDP->UDP_ICR = ( unsigned portLONG ) 0xffffffff; - AT91C_BASE_UDP->UDP_CSR[ 0 ] = ( unsigned portLONG ) 0x00; - AT91C_BASE_UDP->UDP_CSR[ 1 ] = ( unsigned portLONG ) 0x00; - AT91C_BASE_UDP->UDP_GLBSTATE = 0; - AT91C_BASE_UDP->UDP_FADDR = 0; - - /* Enable the transceiver. */ - AT91C_UDP_TRANSCEIVER_ENABLE = 0; - - /* Enable the USB interrupts - other interrupts get enabled as the - enumeration process progresses. */ - AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_UDP, usbINTERRUPT_PRIORITY, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, ( void (*)( void ) ) vUSBISREntry ); - AT91F_AIC_EnableIt( AT91C_BASE_AIC, AT91C_ID_UDP ); - - /* Wait a short while before making our presence known. */ - vTaskDelay( usbINIT_DELAY ); - AT91F_PIO_ClearOutput(AT91C_BASE_PIOA, AT91C_PIO_PA16 ); -} -/*-----------------------------------------------------------*/ - -static void prvSendControlData( unsigned portCHAR *pucData, unsigned portSHORT usRequestedLength, unsigned portLONG ulLengthToSend, portLONG lSendingDescriptor ) -{ - if( ( ( unsigned portLONG ) usRequestedLength < ulLengthToSend ) ) - { - /* Cap the data length to that requested. */ - ulLengthToSend = ( unsigned portSHORT ) usRequestedLength; - } - else if( ( ulLengthToSend < ( unsigned portLONG ) usRequestedLength ) && lSendingDescriptor ) - { - /* We are sending a descriptor. If the descriptor is an exact - multiple of the FIFO length then it will have to be terminated - with a NULL packet. Set the state to indicate this if - necessary. */ - if( ( ulLengthToSend % usbFIFO_LENGTH ) == 0 ) - { - eDriverState = eSENDING_EVEN_DESCRIPTOR; - } - } - - /* Here we assume that the previous message has been sent. THERE IS NO - BUFFER OVERFLOW PROTECTION HERE. - - Copy the data to send into the buffer as we cannot send it all at once - (if it is greater than 8 bytes in length). */ - memcpy( pxCharsForTx.ucTxBuffer, pucData, ulLengthToSend ); - - /* Reinitialise the buffer index so we start sending from the start of - the data. */ - pxCharsForTx.ulTotalDataLength = ulLengthToSend; - pxCharsForTx.ulNextCharIndex = ( unsigned portLONG ) 0; - - /* Send the first 8 bytes now. The rest will get sent in response to - TXCOMP interrupts. */ - prvSendNextSegment(); -} -/*-----------------------------------------------------------*/ - -static void prvSendNextSegment( void ) -{ -volatile unsigned portLONG ulNextLength, ulStatus, ulLengthLeftToSend; - - /* Is there any data to send? */ - if( pxCharsForTx.ulTotalDataLength > pxCharsForTx.ulNextCharIndex ) - { - ulLengthLeftToSend = pxCharsForTx.ulTotalDataLength - pxCharsForTx.ulNextCharIndex; - - /* We can only send 8 bytes to the fifo at a time. */ - if( ulLengthLeftToSend > usbFIFO_LENGTH ) - { - ulNextLength = usbFIFO_LENGTH; - } - else - { - ulNextLength = ulLengthLeftToSend; - } - - /* Wait until we can place data in the fifo. THERE IS NO TIMEOUT - HERE! */ - while( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] & AT91C_UDP_TXPKTRDY ) - { - vTaskDelay( usbSHORTEST_DELAY ); - } - - /* Write the data to the FIFO. */ - while( ulNextLength > ( unsigned portLONG ) 0 ) - { - AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_0 ] = pxCharsForTx.ucTxBuffer[ pxCharsForTx.ulNextCharIndex ]; - - ulNextLength--; - pxCharsForTx.ulNextCharIndex++; - } - - /* Start the transmission. */ - portENTER_CRITICAL(); - { - ulStatus = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ]; - usbCSR_SET_BIT( &ulStatus, ( ( unsigned portLONG ) 0x10 ) ); - AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulStatus; - } - portEXIT_CRITICAL(); - } - else - { - /* There is no data to send. If we were sending a descriptor and the - descriptor was an exact multiple of the max packet size then we need - to send a null to terminate the transmission. */ - if( eDriverState == eSENDING_EVEN_DESCRIPTOR ) - { - prvUSBTransmitNull(); - eDriverState = eNOTHING; - } - } -} - - - diff --git a/Demo/ARM7_AT91SAM7S64_IAR/USB/USBSample.h b/Demo/ARM7_AT91SAM7S64_IAR/USB/USBSample.h deleted file mode 100644 index add756985..000000000 --- a/Demo/ARM7_AT91SAM7S64_IAR/USB/USBSample.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef USB_DEMO_H -#define USB_DEMO_H - -void vUSBDemoTask( void *pvParameters ); - - -#endif - diff --git a/Demo/ARM7_AT91SAM7S64_IAR/USB/USB_ISR.s79 b/Demo/ARM7_AT91SAM7S64_IAR/USB/USB_ISR.s79 deleted file mode 100644 index 8263f71ff..000000000 --- a/Demo/ARM7_AT91SAM7S64_IAR/USB/USB_ISR.s79 +++ /dev/null @@ -1,24 +0,0 @@ - RSEG ICODE:CODE - CODE32 - - EXTERN vUSB_ISR - PUBLIC vUSBISREntry - -; Wrapper for the USB interrupt service routine. This can cause a -; context switch so requires an assembly wrapper. - -; Defines the portSAVE_CONTEXT and portRESTORE_CONTEXT macros. -#include "ISR_Support.h" - -vUSBISREntry: - - portSAVE_CONTEXT ; Save the context of the current task. - - bl vUSB_ISR ; Call the ISR routine. - - portRESTORE_CONTEXT ; Restore the context of the current task - - ; which may be different to the task that - ; was interrupted. - - END - diff --git a/Demo/ARM7_AT91SAM7S64_IAR/main.c b/Demo/ARM7_AT91SAM7S64_IAR/main.c deleted file mode 100644 index 29c975c84..000000000 --- a/Demo/ARM7_AT91SAM7S64_IAR/main.c +++ /dev/null @@ -1,252 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. - The processor MUST be in supervisor mode when vTaskStartScheduler is - called. The demo applications included in the FreeRTOS.org download switch - to supervisor mode prior to main being called. If you are not using one of - these demo application projects then ensure Supervisor mode is used. -*/ - -/* - * Creates all the demo application tasks, then starts the scheduler. The WEB - * documentation provides more details of the demo application tasks. The SAM7 - * includes a sample USB that emulates a Joystick input to a USB host. - * - * Main.c also creates a task called "Check". This only executes every three - * seconds but has the highest priority so is guaranteed to get processor time. - * Its main function is to check that all the other tasks are still operational. - * Each task (other than the "flash" tasks) maintains a unique count that is - * incremented each time the task successfully completes its function. Should - * any error occur within such a task the count is permanently halted. The - * check task inspects the count of each task to ensure it has changed since - * the last time the check task executed. If all the count variables have - * changed all the tasks are still executing error free, and the check task - * toggles the onboard LED. Should any task contain an error at any time - * the LED toggle rate will change from 3 seconds to 500ms. - * - */ - -/* Standard includes. */ -#include - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Demo application includes. */ -#include "flash.h" -#include "integer.h" -#include "PollQ.h" -#include "BlockQ.h" -#include "semtest.h" -#include "dynamic.h" -#include "partest.h" -#include "comtest2.h" -#include "USB/USBSample.h" - -/* Priorities for the demo application tasks. */ -#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainUSB_PRIORITY ( tskIDLE_PRIORITY + 2 ) - -/* Constants required by the 'Check' task. */ -#define mainNO_ERROR_FLASH_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS ) -#define mainERROR_FLASH_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS ) -#define mainCHECK_TASK_LED ( 3 ) - -/* Constants for the ComTest tasks. */ -#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 115200 ) -#define mainCOM_TEST_LED ( 4 ) /* Off the board. */ - -/* - * The task that executes at the highest priority and calls - * prvCheckOtherTasksAreStillRunning(). See the description at the top - * of the file. - */ -static void vErrorChecks( void *pvParameters ); - -/* - * Configure the processor for use with the Atmel demo board. Setup is minimal - * as the low level init function (called from the startup asm file) takes care - * of most things. - */ -static void prvSetupHardware( void ); - -/* - * Checks that all the demo application tasks are still executing without error - * - as described at the top of the file. - */ -static portLONG prvCheckOtherTasksAreStillRunning( void ); - - -/*-----------------------------------------------------------*/ - -/* - * Starts all the other tasks, then starts the scheduler. - */ -void main( void ) -{ - /* Setup any hardware that has not already been configured by the low - level init routines. */ - prvSetupHardware(); - - /* Initialise the LED outputs for use by the demo application tasks. */ - vParTestInitialise(); - - /* Start all the standard demo application tasks. */ - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - vStartDynamicPriorityTasks(); - vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); - - /* Also start the USB demo which is just for the SAM7. */ - xTaskCreate( vUSBDemoTask, "USB", configMINIMAL_STACK_SIZE, NULL, mainUSB_PRIORITY, NULL ); - - /* Start the check task - which is defined in this file. */ - xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - - /* Start the scheduler. - - NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. - The processor MUST be in supervisor mode when vTaskStartScheduler is - called. The demo applications included in the FreeRTOS.org download switch - to supervisor mode prior to main being called. If you are not using one of - these demo application projects then ensure Supervisor mode is used here. */ - - vTaskStartScheduler(); - - /* We should never get here as control is now taken by the scheduler. */ - return; -} -/*-----------------------------------------------------------*/ - -static void prvSetupHardware( void ) -{ - /* When using the JTAG debugger the hardware is not always initialised to - the correct default state. This line just ensures that this does not - cause all interrupts to be masked at the start. */ - AT91C_BASE_AIC->AIC_EOICR = 0; - - /* Most setup is performed by the low level init function called from the - startup asm file. */ - - /* Configure the PIO Lines corresponding to LED1 to LED4 to be outputs as - well as the UART Tx line. */ - AT91F_PIO_CfgOutput( AT91C_BASE_PIOA, LED_MASK ); - - /* Enable the peripheral clock. */ - AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, 1 << AT91C_ID_PIOA ); -} -/*-----------------------------------------------------------*/ - -static void vErrorChecks( void *pvParameters ) -{ -portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD; - - /* The parameters are not used in this task. */ - ( void ) pvParameters; - - /* Cycle for ever, delaying then checking all the other tasks are still - operating without error. If an error is detected then the delay period - is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so - the on board LED flash rate will increase. */ - - for( ;; ) - { - /* Delay until it is time to execute again. */ - vTaskDelay( xDelayPeriod ); - - /* Check all the standard demo application tasks are executing without - error. */ - if( prvCheckOtherTasksAreStillRunning() != pdPASS ) - { - /* An error has been detected in one of the tasks - flash faster. */ - xDelayPeriod = mainERROR_FLASH_PERIOD; - } - - vParTestToggleLED( mainCHECK_TASK_LED ); - } -} -/*-----------------------------------------------------------*/ - -static portLONG prvCheckOtherTasksAreStillRunning( void ) -{ -portLONG lReturn = ( portLONG ) pdPASS; - - /* Check all the demo tasks (other than the flash tasks) to ensure - that they are all still running, and that none of them have detected - an error. */ - - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - lReturn = ( portLONG ) pdFAIL; - } - - if( xArePollingQueuesStillRunning() != pdTRUE ) - { - lReturn = ( portLONG ) pdFAIL; - } - - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - lReturn = ( portLONG ) pdFAIL; - } - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - lReturn = ( portLONG ) pdFAIL; - } - - if( xAreComTestTasksStillRunning() != pdTRUE ) - { - lReturn = ( portLONG ) pdFAIL; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - lReturn = ( portLONG ) pdFAIL; - } - - return lReturn; -} -/*-----------------------------------------------------------*/ - - diff --git a/Demo/ARM7_AT91SAM7S64_IAR/resource/SAM7.mac b/Demo/ARM7_AT91SAM7S64_IAR/resource/SAM7.mac deleted file mode 100644 index b1c753dc3..000000000 --- a/Demo/ARM7_AT91SAM7S64_IAR/resource/SAM7.mac +++ /dev/null @@ -1,180 +0,0 @@ -// --------------------------------------------------------- -// ATMEL Microcontroller Software Support - ROUSSET - -// --------------------------------------------------------- -// The software is delivered "AS IS" without warranty or -// condition of any kind, either express, implied or -// statutory. This includes without limitation any warranty -// or condition with respect to merchantability or fitness -// for any particular purpose, or against the infringements of -// intellectual property rights of others. -// --------------------------------------------------------- -// File: SAM7.mac -// -// User setup file for CSPY debugger to simulate interrupt -// driven Fibonacchi data input. -// 1.1 16/Jun/04 JPP : Creation -// -// $Revision: 1.3 $ -// -// --------------------------------------------------------- - -__var i; -__var pt; - -execUserPreload() -{ -//* Set the RAM memory at 0x0020 0000 for code AT 0 flash area - CheckRemap(); -//* Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R - i=__readMemory32(0xFFFFF240,"Memory"); - __message " ---------------------------------------- Chip ID 0x",i:%X; - i=__readMemory32(0xFFFFF244,"Memory"); - __message " ---------------------------------------- Extention 0x",i:%X; -//* Get the chip status - -//* Init AIC - AIC(); -//* Watchdog Disable - Watchdog(); - -} - - -//----------------------------------------------------------------------------- -// Watchdog -//------------------------------- -// Normally, the Watchdog is enable at the reset for load it's preferable to -// Disable. -//----------------------------------------------------------------------------- -Watchdog() -{ -//* Watchdog Disable -// AT91C_BASE_WDTC->WDTC_WDMR= AT91C_SYSC_WDDIS; - __writeMemory32(0x00008000,0xFFFFFD44,"Memory"); - __message "------------------------------- Watchdog Disable ----------------------------------------"; -} - - -//----------------------------------------------------------------------------- -// Check Remap -//------------- -//----------------------------------------------------------------------------- -CheckRemap() -{ -//* Read the value at 0x0 - i=__readMemory32(0x00000000,"Memory"); - i=i+1; - __writeMemory32(i,0x00,"Memory"); - pt=__readMemory32(0x00000000,"Memory"); - - if (i == pt) - { - __message "------------------------------- The Remap is done ----------------------------------------"; -//* Toggel RESET The remap - __writeMemory32(0x00000001,0xFFFFFF00,"Memory"); - - } else { - __message "------------------------------- The Remap is NOT -----------------------------------------"; - } - -} - - -execUserSetup() -{ - ini(); - __message "-------------------------------Set PC ----------------------------------------"; - __writeMemory32(0x00000000,0xB4,"Register"); -} - - - -//----------------------------------------------------------------------------- -// Reset the Interrupt Controller -//------------------------------- -// Normally, the code is executed only if a reset has been actually performed. -// So, the AIC initialization resumes at setting up the default vectors. -//----------------------------------------------------------------------------- -AIC() -{ -// Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF; - __writeMemory32(0xFFFFFFFF,0xFFFFF124,"Memory"); - - for (i=0;i < 8; i++) - { - // AT91C_BASE_AIC->AIC_EOICR - pt = __readMemory32(0xFFFFF130,"Memory"); - - } - __message "------------------------------- AIC INIT ---------------------------------------------"; -} - -ini() -{ -__writeMemory32(0x0,0x00,"Register"); -__writeMemory32(0x0,0x04,"Register"); -__writeMemory32(0x0,0x08,"Register"); -__writeMemory32(0x0,0x0C,"Register"); -__writeMemory32(0x0,0x10,"Register"); -__writeMemory32(0x0,0x14,"Register"); -__writeMemory32(0x0,0x18,"Register"); -__writeMemory32(0x0,0x1C,"Register"); -__writeMemory32(0x0,0x20,"Register"); -__writeMemory32(0x0,0x24,"Register"); -__writeMemory32(0x0,0x28,"Register"); -__writeMemory32(0x0,0x2C,"Register"); -__writeMemory32(0x0,0x30,"Register"); -__writeMemory32(0x0,0x34,"Register"); -__writeMemory32(0x0,0x38,"Register"); - -// Set CPSR -__writeMemory32(0x0D3,0x98,"Register"); - - -} - -RG() -{ - -i=__readMemory32(0x00,"Register"); __message "R00 0x",i:%X; -i=__readMemory32(0x04,"Register"); __message "R01 0x",i:%X; -i=__readMemory32(0x08,"Register"); __message "R02 0x",i:%X; -i=__readMemory32(0x0C,"Register"); __message "R03 0x",i:%X; -i=__readMemory32(0x10,"Register"); __message "R04 0x",i:%X; -i=__readMemory32(0x14,"Register"); __message "R05 0x",i:%X; -i=__readMemory32(0x18,"Register"); __message "R06 0x",i:%X; -i=__readMemory32(0x1C,"Register"); __message "R07 0x",i:%X; -i=__readMemory32(0x20,"Register"); __message "R08 0x",i:%X; -i=__readMemory32(0x24,"Register"); __message "R09 0x",i:%X; -i=__readMemory32(0x28,"Register"); __message "R10 0x",i:%X; -i=__readMemory32(0x2C,"Register"); __message "R11 0x",i:%X; -i=__readMemory32(0x30,"Register"); __message "R12 0x",i:%X; -i=__readMemory32(0x34,"Register"); __message "R13 0x",i:%X; -i=__readMemory32(0x38,"Register"); __message "R14 0x",i:%X; -i=__readMemory32(0x3C,"Register"); __message "R13 SVC 0x",i:%X; -i=__readMemory32(0x40,"Register"); __message "R14 SVC 0x",i:%X; -i=__readMemory32(0x44,"Register"); __message "R13 ABT 0x",i:%X; -i=__readMemory32(0x48,"Register"); __message "R14 ABT 0x",i:%X; -i=__readMemory32(0x4C,"Register"); __message "R13 UND 0x",i:%X; -i=__readMemory32(0x50,"Register"); __message "R14 UND 0x",i:%X; -i=__readMemory32(0x54,"Register"); __message "R13 IRQ 0x",i:%X; -i=__readMemory32(0x58,"Register"); __message "R14 IRQ 0x",i:%X; -i=__readMemory32(0x5C,"Register"); __message "R08 FIQ 0x",i:%X; -i=__readMemory32(0x60,"Register"); __message "R09 FIQ 0x",i:%X; -i=__readMemory32(0x64,"Register"); __message "R10 FIQ 0x",i:%X; -i=__readMemory32(0x68,"Register"); __message "R11 FIQ 0x",i:%X; -i=__readMemory32(0x6C,"Register"); __message "R12 FIQ 0x",i:%X; -i=__readMemory32(0x70,"Register"); __message "R13 FIQ 0x",i:%X; -i=__readMemory32(0x74,"Register"); __message "R14 FIQ0x",i:%X; -i=__readMemory32(0x98,"Register"); __message "CPSR ",i:%X; -i=__readMemory32(0x94,"Register"); __message "SPSR ",i:%X; -i=__readMemory32(0x9C,"Register"); __message "SPSR ABT ",i:%X; -i=__readMemory32(0xA0,"Register"); __message "SPSR ABT ",i:%X; -i=__readMemory32(0xA4,"Register"); __message "SPSR UND ",i:%X; -i=__readMemory32(0xA8,"Register"); __message "SPSR IRQ ",i:%X; -i=__readMemory32(0xAC,"Register"); __message "SPSR FIQ ",i:%X; - -i=__readMemory32(0xB4,"Register"); __message "PC 0x",i:%X; - -} - diff --git a/Demo/ARM7_AT91SAM7S64_IAR/resource/SAM7_RAM.mac b/Demo/ARM7_AT91SAM7S64_IAR/resource/SAM7_RAM.mac deleted file mode 100644 index 7471d73b7..000000000 --- a/Demo/ARM7_AT91SAM7S64_IAR/resource/SAM7_RAM.mac +++ /dev/null @@ -1,211 +0,0 @@ -// --------------------------------------------------------- -// ATMEL Microcontroller Software Support - ROUSSET - -// --------------------------------------------------------- -// The software is delivered "AS IS" without warranty or -// condition of any kind, either express, implied or -// statutory. This includes without limitation any warranty -// or condition with respect to merchantability or fitness -// for any particular purpose, or against the infringements of -// intellectual property rights of others. -// --------------------------------------------------------- -// File: SAM7_RAM.mac -// -// User setup file for CSPY debugger to simulate interrupt -// driven Fibonacchi data input. -// 1.1 16/Jun/04 JPP : Creation -// 1.2 27/Aug/04 JPP : PLL setting -// -// $Revision: 1.3 $ -// -// --------------------------------------------------------- - -__var i; -__var pt; - -execUserPreload() -{ -//* - PllSetting(); -//* Set the RAM memory at 0x0020 0000 for code AT 0 flash area - CheckNoRemap(); -//* Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R - i=__readMemory32(0xFFFFF240,"Memory"); - __message " ---------------------------------------- Chip ID 0x",i:%X; - i=__readMemory32(0xFFFFF244,"Memory"); - __message " ---------------------------------------- Extention 0x",i:%X; - i=__readMemory32(0xFFFFFF6C,"Memory"); - __message " ---------------------------------------- Flash Version 0x",i:%X; -//* Get the chip status - -//* Init AIC - AIC(); -//* Watchdog Disable - Watchdog(); -} -//----------------------------------------------------------------------------- -// PllSetting -//------------------------------- -// Set PLL -//----------------------------------------------------------------------------- -PllSetting() -{ -// -1- Enabling the Main Oscillator: -//*#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register -//*#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register -//*#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register - -//*pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | //0x0000 0600 -// AT91C_CKGR_MOSCEN )); //0x0000 0001 -__writeMemory32(0x00000601,0xFFFFFC20,"Memory"); - -// -2- Wait -// -3- Setting PLL and divider: -// - div by 5 Fin = 3,6864 =(18,432 / 5) -// - Mul 25+1: Fout = 95,8464 =(3,6864 *26) -// for 96 MHz the erroe is 0.16% -// Field out NOT USED = 0 -// PLLCOUNT pll startup time esrtimate at : 0.844 ms -// PLLCOUNT 28 = 0.000844 /(1/32768) -// pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x05) | //0x0000 0005 -// (AT91C_CKGR_PLLCOUNT & (28<<8)) //0x0000 1C00 -// (AT91C_CKGR_MUL & (25<<16))); //0x0019 0000 -__writeMemory32(0x00191C05,0xFFFFFC2C,"Memory"); -// -2- Wait -// -5- Selection of Master Clock and Processor Clock -// select the PLL clock divided by 2 -// pPMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | //0x0000 0003 -// AT91C_PMC_PRES_CLK_2 ; //0x0000 0004 -__writeMemory32(0x00000007,0xFFFFFC30,"Memory"); - - __message "------------------------------- PLL Enable ----------------------------------------"; -} - -//----------------------------------------------------------------------------- -// Watchdog -//------------------------------- -// Normally, the Watchdog is enable at the reset for load it's preferable to -// Disable. -//----------------------------------------------------------------------------- -Watchdog() -{ -//* Watchdog Disable -// AT91C_BASE_WDTC->WDTC_WDMR= AT91C_SYSC_WDDIS; - __writeMemory32(0x00008000,0xFFFFFD44,"Memory"); - __message "------------------------------- Watchdog Disable ----------------------------------------"; -} - -CheckNoRemap() -{ -//* Read the value at 0x0 - i=__readMemory32(0x00000000,"Memory"); - i=i+1; - __writeMemory32(i,0x00,"Memory"); - pt=__readMemory32(0x00000000,"Memory"); - - if (i == pt) - { - __message "------------------------------- The Remap is done ----------------------------------------"; - - } else { - __message "------------------------------- The Remap is NOT -----------------------------------------"; -//* Toggel RESET The remap - __writeMemory32(0x00000001,0xFFFFFF00,"Memory"); - } - -} - -execUserSetup() -{ - ini(); - __message "-------------------------------Set PC ----------------------------------------"; - __writeMemory32(0x00000000,0xB4,"Register"); -} - -//----------------------------------------------------------------------------- -// Reset the Interrupt Controller -//------------------------------- -// Normally, the code is executed only if a reset has been actually performed. -// So, the AIC initialization resumes at setting up the default vectors. -//----------------------------------------------------------------------------- -AIC() -{ -// Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF; - __writeMemory32(0xFFFFFFFF,0xFFFFF124,"Memory"); - - for (i=0;i < 8; i++) - { - // AT91C_BASE_AIC->AIC_EOICR - pt = __readMemory32(0xFFFFF130,"Memory"); - - } - __message "------------------------------- AIC INIT ---------------------------------------------"; -} - -ini() -{ -__writeMemory32(0x0,0x00,"Register"); -__writeMemory32(0x0,0x04,"Register"); -__writeMemory32(0x0,0x08,"Register"); -__writeMemory32(0x0,0x0C,"Register"); -__writeMemory32(0x0,0x10,"Register"); -__writeMemory32(0x0,0x14,"Register"); -__writeMemory32(0x0,0x18,"Register"); -__writeMemory32(0x0,0x1C,"Register"); -__writeMemory32(0x0,0x20,"Register"); -__writeMemory32(0x0,0x24,"Register"); -__writeMemory32(0x0,0x28,"Register"); -__writeMemory32(0x0,0x2C,"Register"); -__writeMemory32(0x0,0x30,"Register"); -__writeMemory32(0x0,0x34,"Register"); -__writeMemory32(0x0,0x38,"Register"); - -// Set CPSR -__writeMemory32(0x0D3,0x98,"Register"); - -} - -RG() -{ - -i=__readMemory32(0x00,"Register"); __message "R00 0x",i:%X; -i=__readMemory32(0x04,"Register"); __message "R01 0x",i:%X; -i=__readMemory32(0x08,"Register"); __message "R02 0x",i:%X; -i=__readMemory32(0x0C,"Register"); __message "R03 0x",i:%X; -i=__readMemory32(0x10,"Register"); __message "R04 0x",i:%X; -i=__readMemory32(0x14,"Register"); __message "R05 0x",i:%X; -i=__readMemory32(0x18,"Register"); __message "R06 0x",i:%X; -i=__readMemory32(0x1C,"Register"); __message "R07 0x",i:%X; -i=__readMemory32(0x20,"Register"); __message "R08 0x",i:%X; -i=__readMemory32(0x24,"Register"); __message "R09 0x",i:%X; -i=__readMemory32(0x28,"Register"); __message "R10 0x",i:%X; -i=__readMemory32(0x2C,"Register"); __message "R11 0x",i:%X; -i=__readMemory32(0x30,"Register"); __message "R12 0x",i:%X; -i=__readMemory32(0x34,"Register"); __message "R13 0x",i:%X; -i=__readMemory32(0x38,"Register"); __message "R14 0x",i:%X; -i=__readMemory32(0x3C,"Register"); __message "R13 SVC 0x",i:%X; -i=__readMemory32(0x40,"Register"); __message "R14 SVC 0x",i:%X; -i=__readMemory32(0x44,"Register"); __message "R13 ABT 0x",i:%X; -i=__readMemory32(0x48,"Register"); __message "R14 ABT 0x",i:%X; -i=__readMemory32(0x4C,"Register"); __message "R13 UND 0x",i:%X; -i=__readMemory32(0x50,"Register"); __message "R14 UND 0x",i:%X; -i=__readMemory32(0x54,"Register"); __message "R13 IRQ 0x",i:%X; -i=__readMemory32(0x58,"Register"); __message "R14 IRQ 0x",i:%X; -i=__readMemory32(0x5C,"Register"); __message "R08 FIQ 0x",i:%X; -i=__readMemory32(0x60,"Register"); __message "R09 FIQ 0x",i:%X; -i=__readMemory32(0x64,"Register"); __message "R10 FIQ 0x",i:%X; -i=__readMemory32(0x68,"Register"); __message "R11 FIQ 0x",i:%X; -i=__readMemory32(0x6C,"Register"); __message "R12 FIQ 0x",i:%X; -i=__readMemory32(0x70,"Register"); __message "R13 FIQ 0x",i:%X; -i=__readMemory32(0x74,"Register"); __message "R14 FIQ0x",i:%X; -i=__readMemory32(0x98,"Register"); __message "CPSR ",i:%X; -i=__readMemory32(0x94,"Register"); __message "SPSR ",i:%X; -i=__readMemory32(0x9C,"Register"); __message "SPSR ABT ",i:%X; -i=__readMemory32(0xA0,"Register"); __message "SPSR ABT ",i:%X; -i=__readMemory32(0xA4,"Register"); __message "SPSR UND ",i:%X; -i=__readMemory32(0xA8,"Register"); __message "SPSR IRQ ",i:%X; -i=__readMemory32(0xAC,"Register"); __message "SPSR FIQ ",i:%X; - -i=__readMemory32(0xB4,"Register"); __message "PC 0x",i:%X; - -} - diff --git a/Demo/ARM7_AT91SAM7S64_IAR/resource/at91SAM7S64_16KRAM.xcl b/Demo/ARM7_AT91SAM7S64_IAR/resource/at91SAM7S64_16KRAM.xcl deleted file mode 100644 index 6f304e4f0..000000000 --- a/Demo/ARM7_AT91SAM7S64_IAR/resource/at91SAM7S64_16KRAM.xcl +++ /dev/null @@ -1,135 +0,0 @@ -// --------------------------------------------------------- -// ATMEL Microcontroller Software Support - ROUSSET - -// --------------------------------------------------------- -// The software is delivered "AS IS" without warranty or -// condition of any kind, either express, implied or -// statutory. This includes without limitation any warranty -// or condition with respect to merchantability or fitness -// for any particular purpose, or against the infringements of -// intellectual property rights of others. -// --------------------------------------------------------- -// File: at91SAM7S64_16KRAM.xlc -// -// 1.1 16/Jun/04 JPP : Creation for 4.11A -// -// $Revision: 1.1.1.1 $ -// -// --------------------------------------------------------- - -//************************************************************************* -// XLINK command file template for EWARM/ICCARM -// -// Usage: xlink -f lnkarm -// -s -// -// $Revision: 1.1.1.1 $ -//************************************************************************* - -//************************************************ -// Inform the linker about the CPU family used. -// AT91SAM7S64 Memory mapping -// No remap -// ROMSTART -// Start address 0x0000 0000 -// Size 64 Kbo 0x0001 0000 -// RAMSTART -// Start address 0x0020 0000 -// Size 16 Kbo 0x0000 4000 -// Remap done -// RAMSTART -// Start address 0x0000 0000 -// Size 16 Kbo 0x0000 4000 -// ROMSTART -// Start address 0x0010 0000 -// Size 64 Kbo 0x0001 0000 - -//************************************************ --carm - -//************************************************************************* -// Internal Ram segments mapped AFTER REMAP 16 K. -//************************************************************************* -// Use these addresses for the . --Z(CONST)INTRAMSTART_REMAP=00000000 --Z(CONST)INTRAMEND_REMAP=00003FFF - -//************************************************************************* -// Read-only segments mapped to Flash 64 K. -//************************************************************************* --DROMSTART=00000000 --DROMEND=0000FFFF -//************************************************************************* -// Read/write segments mapped to RAM. -//************************************************************************* --DRAMSTART=00000000 --DRAMEND=00003FFF - -//************************************************ -// Address range for reset and exception -// vectors (INTVEC). -// The vector area is 32 bytes, -// an additional 32 bytes is allocated for the -// constant table used by ldr PC in cstartup.s79. -//************************************************ --Z(CODE)INTVEC=00-3F - -//************************************************ -// Startup code and exception routines (ICODE). -//************************************************ --Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND --Z(CODE)SWITAB=ROMSTART-ROMEND - -//************************************************ -// Code segments may be placed anywhere. -//************************************************ --Z(CODE)CODE=ROMSTART-ROMEND - -//************************************************ -// Various constants and initializers. -//************************************************ --Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND --Z(CONST)CHECKSUM=ROMSTART-ROMEND - -//************************************************ -// Data segments. -//************************************************ --Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND - -//************************************************ -// __ramfunc code copied to and executed from RAM. -//************************************************ --Z(DATA)CODE_I=RAMSTART-RAMEND - -//************************************************ -// ICCARM produces code for __ramfunc functions in -// CODE_I segments. The -Q XLINK command line -// option redirects XLINK to emit the code in the -// debug information associated with the CODE_I -// segment, where the code will execute. -//************************************************ - -//************************************************************************* -// Stack and heap segments. -//************************************************************************* --D_CSTACK_SIZE=(100*4) --D_IRQ_STACK_SIZE=(2*8*4) - --Z(DATA)CSTACK+_CSTACK_SIZE=RAMSTART-RAMEND --Z(DATA)IRQ_STACK+_IRQ_STACK_SIZE=RAMSTART-RAMEND - -//************************************************************************* -// ELF/DWARF support. -// -// Uncomment the line "-Felf" below to generate ELF/DWARF output. -// Available format specifiers are: -// -// "-yn": Suppress DWARF debug output -// "-yp": Multiple ELF program sections -// "-yas": Format suitable for debuggers from ARM Ltd (also sets -p flag) -// -// "-Felf" and the format specifiers can also be supplied directly as -// command line options, or selected from the Xlink Output tab in the -// IAR Embedded Workbench. -//************************************************************************* - -// -Felf diff --git a/Demo/ARM7_AT91SAM7S64_IAR/resource/at91SAM7S64_NoRemap.xcl b/Demo/ARM7_AT91SAM7S64_IAR/resource/at91SAM7S64_NoRemap.xcl deleted file mode 100644 index 4fa63442a..000000000 --- a/Demo/ARM7_AT91SAM7S64_IAR/resource/at91SAM7S64_NoRemap.xcl +++ /dev/null @@ -1,136 +0,0 @@ -// --------------------------------------------------------- -// ATMEL Microcontroller Software Support - ROUSSET - -// --------------------------------------------------------- -// The software is delivered "AS IS" without warranty or -// condition of any kind, either express, implied or -// statutory. This includes without limitation any warranty -// or condition with respect to merchantability or fitness -// for any particular purpose, or against the infringements of -// intellectual property rights of others. -// --------------------------------------------------------- -// File: at91SAM7S64_NoRemap.xlc -// -// 1.1 16/Jun/04 JPP : Creation for 4.11A -// -// $Revision: 1.1.1.1 $ -// -// --------------------------------------------------------- - -//************************************************************************* -// XLINK command file template for EWARM/ICCARM -// -// Usage: xlink -f lnkarm -// -s -// -// $Revision: 1.1.1.1 $ -//************************************************************************* - -//************************************************ -// Inform the linker about the CPU family used. -// AT91SAM7S64 Memory mapping -// No remap -// ROMSTART -// Start address 0x0000 0000 -// Size 64 Kbo 0x0001 0000 -// RAMSTART -// Start address 0x0020 0000 -// Size 16 Kbo 0x0000 4000 -// Remap done -// RAMSTART -// Start address 0x0000 0000 -// Size 16 Kbo 0x0000 4000 -// ROMSTART -// Start address 0x0010 0000 -// Size 64 Kbo 0x0001 0000 - -//************************************************ --carm - -//************************************************************************* -// Internal Ram segments mapped AFTER REMAP 16 K. -//************************************************************************* -// Use these addresses for the . --Z(CONST)INTRAMSTART_REMAP=00200000 --Z(CONST)INTRAMEND_REMAP=00203FFF - -//************************************************************************* -// Read-only segments mapped to Flash 64 K. -//************************************************************************* --DROMSTART=00000000 --DROMEND=0000FFFF -//************************************************************************* -// Read/write segments mapped to RAM. -//************************************************************************* --DRAMSTART=00200000 --DRAMEND=002003FFF - -//************************************************ -// Address range for reset and exception -// vectors (INTVEC). -// The vector area is 32 bytes, -// an additional 32 bytes is allocated for the -// constant table used by ldr PC in cstartup.s79. -//************************************************ --Z(CODE)INTVEC=00-3F - -//************************************************ -// Startup code and exception routines (ICODE). -//************************************************ --Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND --Z(CODE)SWITAB=ROMSTART-ROMEND - -//************************************************ -// Code segments may be placed anywhere. -//************************************************ --Z(CODE)CODE=ROMSTART-ROMEND - -//************************************************ -// Various constants and initializers. -//************************************************ --Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND --Z(CONST)CHECKSUM=ROMSTART-ROMEND - - -//************************************************ -// Data segments. -//************************************************ --Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND - -//************************************************ -// __ramfunc code copied to and executed from RAM. -//************************************************ --Z(DATA)CODE_I=RAMSTART-RAMEND - -//************************************************ -// ICCARM produces code for __ramfunc functions in -// CODE_I segments. The -Q XLINK command line -// option redirects XLINK to emit the code in the -// debug information associated with the CODE_I -// segment, where the code will execute. -//************************************************ - -//************************************************************************* -// Stack and heap segments. -//************************************************************************* -//-D_CSTACK_SIZE=(100*4) -//-D_IRQ_STACK_SIZE=(2*8*4) - -//-Z(DATA)CSTACK+_CSTACK_SIZE=RAMSTART-RAMEND -//-Z(DATA)IRQ_STACK+_IRQ_STACK_SIZE=RAMSTART-RAMEND - -//************************************************************************* -// ELF/DWARF support. -// -// Uncomment the line "-Felf" below to generate ELF/DWARF output. -// Available format specifiers are: -// -// "-yn": Suppress DWARF debug output -// "-yp": Multiple ELF program sections -// "-yas": Format suitable for debuggers from ARM Ltd (also sets -p flag) -// -// "-Felf" and the format specifiers can also be supplied directly as -// command line options, or selected from the Xlink Output tab in the -// IAR Embedded Workbench. -//************************************************************************* - -// -Felf diff --git a/Demo/ARM7_AT91SAM7S64_IAR/rtosdemo.ewd b/Demo/ARM7_AT91SAM7S64_IAR/rtosdemo.ewd deleted file mode 100644 index 44815edc8..000000000 --- a/Demo/ARM7_AT91SAM7S64_IAR/rtosdemo.ewd +++ /dev/null @@ -1,905 +0,0 @@ - - - - 1 - - Flash Debug - - ARM - - 1 - - C-SPY - 2 - - 13 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - ARMSIM_ID - 2 - - 0 - 1 - 1 - - - - - ANGEL_ID - 2 - - 0 - 1 - 1 - - - - - - - - - - - - IARROM_ID - 2 - - 0 - 1 - 1 - - - - - - - - - - JLINK_ID - 2 - - 2 - 1 - 1 - - - - - - - - - - - - - - - - - - - MACRAIGOR_ID - 2 - - 1 - 1 - 1 - - - - - - - - - - - - - - - - - - RDI_ID - 2 - - 1 - 1 - 1 - - - - - - - - - - - - - - - - - THIRDPARTY_ID - 2 - - 0 - 1 - 1 - - - - - - - - - $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin - 1 - - - $EW_DIR$\common\plugins\Orti\Orti.ewplugin - 0 - - - $EW_DIR$\common\plugins\Profiling\Profiling.ewplugin - 1 - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin - 0 - - - - - Flash Bin - - ARM - - 1 - - C-SPY - 2 - - 13 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - ARMSIM_ID - 2 - - 0 - 1 - 1 - - - - - ANGEL_ID - 2 - - 0 - 1 - 1 - - - - - - - - - - - - IARROM_ID - 2 - - 0 - 1 - 1 - - - - - - - - - - JLINK_ID - 2 - - 2 - 1 - 1 - - - - - - - - - - - - - - - - - - - MACRAIGOR_ID - 2 - - 1 - 1 - 1 - - - - - - - - - - - - - - - - - - RDI_ID - 2 - - 1 - 1 - 1 - - - - - - - - - - - - - - - - - THIRDPARTY_ID - 2 - - 0 - 1 - 1 - - - - - - - - - $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin - 1 - - - $EW_DIR$\common\plugins\Orti\Orti.ewplugin - 0 - - - $EW_DIR$\common\plugins\Profiling\Profiling.ewplugin - 1 - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin - 0 - - - - - - diff --git a/Demo/ARM7_AT91SAM7S64_IAR/rtosdemo.ewp b/Demo/ARM7_AT91SAM7S64_IAR/rtosdemo.ewp deleted file mode 100644 index 63e626910..000000000 --- a/Demo/ARM7_AT91SAM7S64_IAR/rtosdemo.ewp +++ /dev/null @@ -1,1738 +0,0 @@ - - - - 1 - - Flash Debug - - ARM - - 1 - - General - 2 - - 9 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 13 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 6 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - XLINK - 2 - - 17 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - XAR - 2 - - 0 - 1 - 1 - - - - - - - BILINK - 0 - - - - - Flash Bin - - ARM - - 1 - - General - 2 - - 9 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 13 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 6 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - XLINK - 2 - - 17 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - XAR - 2 - - 0 - 1 - 1 - - - - - - - BILINK - 0 - - - - - Demo Source - - $PROJ_DIR$\..\Common\Minimal\BlockQ.c - - - $PROJ_DIR$\..\Common\Minimal\comtest.c - - - $PROJ_DIR$\..\Common\Minimal\dynamic.c - - - $PROJ_DIR$\..\Common\Minimal\flash.c - - - $PROJ_DIR$\..\..\Source\portable\MemMang\heap_1.c - - - $PROJ_DIR$\..\Common\Minimal\integer.c - - - $PROJ_DIR$\main.c - - - $PROJ_DIR$\ParTest\ParTest.c - - - $PROJ_DIR$\..\Common\Minimal\PollQ.c - - - $PROJ_DIR$\..\Common\Minimal\semtest.c - - - $PROJ_DIR$\serial\serial.c - - - $PROJ_DIR$\serial\serialISR.s79 - - - $PROJ_DIR$\USB\USB_ISR.s79 - - - $PROJ_DIR$\USB\USBSample.c - - - - Scheduler Source - - $PROJ_DIR$\..\..\Source\list.c - - - $PROJ_DIR$\..\..\Source\portable\IAR\AtmelSAM7S64\port.c - - - $PROJ_DIR$\..\..\Source\portable\IAR\AtmelSAM7S64\portasm.s79 - - - $PROJ_DIR$\..\..\Source\queue.c - - - $PROJ_DIR$\..\..\Source\tasks.c - - - - System Files - - $PROJ_DIR$\SrcIAR\Cstartup.s79 - - - $PROJ_DIR$\SrcIAR\Cstartup_SAM7.c - - - - - diff --git a/Demo/ARM7_AT91SAM7S64_IAR/rtosdemo.eww b/Demo/ARM7_AT91SAM7S64_IAR/rtosdemo.eww deleted file mode 100644 index 2294aacb5..000000000 --- a/Demo/ARM7_AT91SAM7S64_IAR/rtosdemo.eww +++ /dev/null @@ -1,10 +0,0 @@ - - - - - $WS_DIR$\rtosdemo.ewp - - - - - diff --git a/Demo/ARM7_AT91SAM7S64_IAR/serial/serial.c b/Demo/ARM7_AT91SAM7S64_IAR/serial/serial.c deleted file mode 100644 index 57081367d..000000000 --- a/Demo/ARM7_AT91SAM7S64_IAR/serial/serial.c +++ /dev/null @@ -1,246 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0. -*/ - -/* Standard includes. */ -#include - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "queue.h" - -/* Demo application includes. */ -#include "serial.h" - -/*-----------------------------------------------------------*/ - -/* Location of the COM0 registers. */ -#define serCOM0 ( ( AT91PS_USART ) AT91C_BASE_US0 ) - -/* Interrupt control macros. */ -#define serINTERRUPT_LEVEL ( 5 ) -#define vInterruptOn() AT91F_US_EnableIt( serCOM0, AT91C_US_TXRDY | AT91C_US_RXRDY ) -#define vInterruptOff() AT91F_US_DisableIt( serCOM0, AT91C_US_TXRDY ) - -/* Misc constants. */ -#define serINVALID_QUEUE ( ( xQueueHandle ) 0 ) -#define serHANDLE ( ( xComPortHandle ) 1 ) -#define serNO_BLOCK ( ( portTickType ) 0 ) -#define serNO_TIMEGUARD ( ( unsigned portLONG ) 0 ) -#define serNO_PERIPHERAL_B_SETUP ( ( unsigned portLONG ) 0 ) - - -/* Queues used to hold received characters, and characters waiting to be -transmitted. */ -static xQueueHandle xRxedChars; -static xQueueHandle xCharsForTx; - -/*-----------------------------------------------------------*/ - -/* Interrupt entry point written in the assembler file serialISR.s79. */ -extern void vSerialISREntry( void ); - -/* The interrupt service routine - called from the assembly entry point. */ -__arm void vSerialISR( void ); - -/*-----------------------------------------------------------*/ - -/* - * See the serial2.h header file. - */ -xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) -{ -xComPortHandle xReturn = serHANDLE; -extern void ( vUART_ISR )( void ); - - /* Create the queues used to hold Rx and Tx characters. */ - xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); - xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); - - /* If the queues were created correctly then setup the serial port - hardware. */ - if( ( xRxedChars != serINVALID_QUEUE ) && ( xCharsForTx != serINVALID_QUEUE ) ) - { - portENTER_CRITICAL(); - { - /* Enable the USART clock. */ - AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, 1 << AT91C_ID_US0 ); - - AT91F_PIO_CfgPeriph( AT91C_BASE_PIOA, ( ( unsigned portLONG ) AT91C_PA5_RXD0 ) | ( ( unsigned portLONG ) AT91C_PA6_TXD0 ), serNO_PERIPHERAL_B_SETUP ); - - /* Set the required protocol. */ - AT91F_US_Configure( serCOM0, configCPU_CLOCK_HZ, AT91C_US_ASYNC_MODE, ulWantedBaud, serNO_TIMEGUARD ); - - /* Enable Rx and Tx. */ - serCOM0->US_CR = AT91C_US_RXEN | AT91C_US_TXEN; - - /* Enable the Rx interrupts. The Tx interrupts are not enabled - until there are characters to be transmitted. */ - AT91F_US_EnableIt( serCOM0, AT91C_US_RXRDY ); - - /* Enable the interrupts in the AIC. */ - AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_US0, serINTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, ( void (*)( void ) ) vSerialISREntry ); - AT91F_AIC_EnableIt( AT91C_BASE_AIC, AT91C_ID_US0 ); - } - portEXIT_CRITICAL(); - } - else - { - xReturn = ( xComPortHandle ) 0; - } - - /* This demo file only supports a single port but we have to return - something to comply with the standard demo header file. */ - return xReturn; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) -{ - /* The port handle is not required as this driver only supports one port. */ - ( void ) pxPort; - - /* Get the next character from the buffer. Return false if no characters - are available, or arrive before xBlockTime expires. */ - if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) - { - return pdTRUE; - } - else - { - return pdFALSE; - } -} -/*-----------------------------------------------------------*/ - -void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength ) -{ -signed portCHAR *pxNext; - - /* A couple of parameters that this port does not use. */ - ( void ) usStringLength; - ( void ) pxPort; - - /* NOTE: This implementation does not handle the queue being full as no - block time is used! */ - - /* The port handle is not required as this driver only supports UART0. */ - ( void ) pxPort; - - /* Send each character in the string, one at a time. */ - pxNext = ( signed portCHAR * ) pcString; - while( *pxNext ) - { - xSerialPutChar( pxPort, *pxNext, serNO_BLOCK ); - pxNext++; - } -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) -{ - /* Place the character in the queue of characters to be transmitted. */ - if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) - { - return pdFAIL; - } - - /* Turn on the Tx interrupt so the ISR will remove the character from the - queue and send it. This does not need to be in a critical section as - if the interrupt has already removed the character the next interrupt - will simply turn off the Tx interrupt again. */ - vInterruptOn(); - - return pdPASS; -} -/*-----------------------------------------------------------*/ - -void vSerialClose( xComPortHandle xPort ) -{ - /* Not supported as not required by the demo application. */ -} -/*-----------------------------------------------------------*/ - -/* Serial port ISR. This can cause a context switch so is not defined as a -standard ISR using the __irq keyword. Instead a wrapper function is defined -within serialISR.s79 which in turn calls this function. See the port -documentation on the FreeRTOS.org website for more information. */ -__arm void vSerialISR( void ) -{ -unsigned portLONG ulStatus; -signed portCHAR cChar; -portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByPost = pdFALSE; - - /* What caused the interrupt? */ - ulStatus = serCOM0->US_CSR &= serCOM0->US_IMR; - - if( ulStatus & AT91C_US_TXRDY ) - { - /* The interrupt was caused by the THR becoming empty. Are there any - more characters to transmit? */ - if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE ) - { - /* A character was retrieved from the queue so can be sent to the - THR now. */ - serCOM0->US_THR = cChar; - } - else - { - /* Queue empty, nothing to send so turn off the Tx interrupt. */ - vInterruptOff(); - } - } - - if( ulStatus & AT91C_US_RXRDY ) - { - /* The interrupt was caused by a character being received. Grab the - character from the RHR and place it in the queue or received - characters. */ - cChar = serCOM0->US_RHR; - xTaskWokenByPost = xQueueSendFromISR( xRxedChars, &cChar, xTaskWokenByPost ); - } - - /* If a task was woken by either a character being received or a character - being transmitted then we may need to switch to another task. */ - portEND_SWITCHING_ISR( ( xTaskWokenByPost || xTaskWokenByTx ) ); - - /* End the interrupt in the AIC. */ - AT91C_BASE_AIC->AIC_EOICR = 0; -} - - - - - diff --git a/Demo/ARM7_AT91SAM7S64_IAR/serial/serialISR.s79 b/Demo/ARM7_AT91SAM7S64_IAR/serial/serialISR.s79 deleted file mode 100644 index da0a0bd17..000000000 --- a/Demo/ARM7_AT91SAM7S64_IAR/serial/serialISR.s79 +++ /dev/null @@ -1,24 +0,0 @@ - RSEG ICODE:CODE - CODE32 - - EXTERN vSerialISR - PUBLIC vSerialISREntry - -; Wrapper for the serial port interrupt service routine. This can cause a -; context switch so requires an assembly wrapper. - -; Defines the portSAVE_CONTEXT and portRESTORE_CONTEXT macros. -#include "ISR_Support.h" - -vSerialISREntry: - - portSAVE_CONTEXT ; Save the context of the current task. - - bl vSerialISR ; Call the ISR routine. - - portRESTORE_CONTEXT ; Restore the context of the current task - - ; which may be different to the task that - ; was interrupted. - - END - diff --git a/Demo/ARM7_AT91SAM7S64_IAR/settings/Basic.dbgdt b/Demo/ARM7_AT91SAM7S64_IAR/settings/Basic.dbgdt deleted file mode 100644 index 5085f2cdb..000000000 --- a/Demo/ARM7_AT91SAM7S64_IAR/settings/Basic.dbgdt +++ /dev/null @@ -1,71 +0,0 @@ - - - - - - - - - - - 1892727 - - - - - - 200100 - - - 200188171100100010 - - - - - TabID-23416-30482 - Workspace - Workspace - - - rtosdemo - - - - 0 - - - - - TabID-12145-30489 - Debug Log - Debug-Log - - - - TabID-22894-30492 - Build - Build - - - - - 1 - TabID-18780-12821MemoryMemory2097764209776410000TabID-23506-14575WatchWatchpxCurrentTCBulCriticalNesting01761001001000TabID-4859-22480DisassemblyDisassembly0TabID-154-22568RegisterRegister0001CPSR0 - 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- - - - - - IarIdePM1-2-2866306-2-248483000042895192500775692-2-22061602-2-2160420810025001858803000042895 - - - - diff --git a/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo.dbgdt b/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo.dbgdt deleted file mode 100644 index cfa227533..000000000 --- a/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo.dbgdt +++ /dev/null @@ -1,62 +0,0 @@ - - - - - - - - - - - 1912727 - - - - - - 200100 - 300Build - 300Debug-Log - - - - - - - 200 - - 161100100100300010 - - - - - - - - TabID-22256-14845 - Workspace - Workspace - - - rtosdemortosdemo/USBSample.c - - - - 0 - - - - - - TextEditorE:\Dev\FreeRTOS\source\portable\iar\AtmelSAM7S64\lib_AT91SAM7S64.h06152480624806TextEditorE:\Dev\FreeRTOS\Demo\ARM7_AT91SAM7S64_IAR\USB\USBSample.c02891049810498TextEditorE:\Dev\FreeRTOS\Demo\ARM7_AT91SAM7S64_IAR\main.c014164206420TextEditorE:\Dev\FreeRTOS\Source\portable\IAR\AtmelSAM7S64\port.c011754935493TextEditorE:\Dev\FreeRTOS\Demo\ARM7_AT91SAM7S64_IAR\serial\serial.c013255475547TextEditorE:\Dev\FreeRTOS\Source\portable\MemMang\heap_1.c08236503650TextEditorE:\Dev\FreeRTOS\Demo\ARM7_AT91SAM7S64_IAR\SrcIAR\Cstartup.s7902722262226TextEditorE:\Dev\FreeRTOS\Demo\Common\Minimal\integer.c07740244024TextEditorE:\Dev\FreeRTOS\Source\tasks.c08232928929289TextEditorE:\Dev\FreeRTOS\Source\portable\IAR\AtmelSAM7S64\portasm.s7900519519TextEditorE:\Dev\FreeRTOS\Source\portable\IAR\AtmelSAM7S64\portmacro.h05700TextEditorE:\Dev\FreeRTOS\Demo\ARM7_AT91SAM7S64_IAR\FreeRTOSConfig.h02400TextEditorE:\Dev\FreeRTOS\Demo\Common\Minimal\semtest.c016678567856120100000010000001 - - - - - - - IarIdePM1DebuggerGui1-2-21072265-2-20000166875959785 - - - - diff --git a/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo.dni b/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo.dni deleted file mode 100644 index fc509a42a..000000000 --- a/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo.dni +++ /dev/null @@ -1,22 +0,0 @@ -[DisAssemblyWindow] -NumStates=_ 1 -State 1=_ 1 -[JLinkDriver] -WatchVectorCatch=_ 0 -WatchCond=_ 0 -Watch0=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 -Watch1=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 -[Low Level] -Pipeline mode=1 -Initialized=0 -[Log file] -LoggingEnabled=_ 0 -LogFile=_ "" -Category=_ 0 -[TermIOLog] -LoggingEnabled=_ 0 -LogFile=_ "" -[Disassemble mode] -mode=0 -[Breakpoints] -Count=0 diff --git a/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo.wsdt b/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo.wsdt deleted file mode 100644 index 2910d9720..000000000 --- a/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo.wsdt +++ /dev/null @@ -1,76 +0,0 @@ - - - - - - rtosdemo/Flash Debug - - - - - - - - 221272727 - - 18115530877 - - - - - - - - - - - 100010 - - - - - - - TabID-17425-14382 - Workspace - Workspace - - - rtosdemortosdemo/Demo Sourcertosdemo/Scheduler Sourcertosdemo/System Files - - - - 0 - - - TabID-4084-16269 - Build - Build - - - - TabID-25581-16276 - Debug Log - Debug-Log - - - - - 0 - - - - - - TextEditorE:\Dev\FreeRTOS\Demo\ARM7_AT91SAM7S64_IAR\FreeRTOSConfig.h01800TextEditorE:\Dev\FreeRTOS\Demo\ARM7_AT91SAM7S64_IAR\SrcIAR\Board.h00952969TextEditorE:\Dev\FreeRTOS\Demo\ARM7_AT91SAM7S64_IAR\SrcIAR\Cstartup.s7901426503651720100000010000001 - - - - - - - iaridepm1-2-2659295-2-230301875026809185625590705-2-24131602-2-2160441510025003708661875026809 - - - - diff --git a/Demo/ARM7_LPC2106_GCC/FreeRTOSConfig.h b/Demo/ARM7_LPC2106_GCC/FreeRTOSConfig.h deleted file mode 100644 index 98d323d9d..000000000 --- a/Demo/ARM7_LPC2106_GCC/FreeRTOSConfig.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -#include - - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 58982400 ) /* =14.7456MHz xtal multiplied by 4 using the PLL. */ -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 23 * 1024 ) ) -#define configMAX_TASK_NAME_LEN ( 16 ) -#define configUSE_TRACE_FACILITY 0 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 1 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/ARM7_LPC2106_GCC/Makefile b/Demo/ARM7_LPC2106_GCC/Makefile deleted file mode 100644 index 2cd10c94b..000000000 --- a/Demo/ARM7_LPC2106_GCC/Makefile +++ /dev/null @@ -1,118 +0,0 @@ -# FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. -# -# This file is part of the FreeRTOS.org distribution. -# -# FreeRTOS.org is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# FreeRTOS.org is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with FreeRTOS.org; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -# -# A special exception to the GPL can be applied should you wish to distribute -# a combined work that includes FreeRTOS.org, without being obliged to provide -# the source code for any proprietary components. See the licensing section -# of http://www.FreeRTOS.org for full details of how and when the exception -# can be applied. -# -# *************************************************************************** -# See http://www.FreeRTOS.org for documentation, latest information, license -# and contact details. Please ensure to read the configuration and relevant -# port sections of the online documentation. -# *************************************************************************** - -# Changes from V2.4.2 -# -# + Replaced source/portable/gcc/arm7/portheap.c with source/portable/memmang/heap_2.c. - -CC=arm-elf-gcc -OBJCOPY=arm-elf-objcopy -ARCH=arm-elf-ar -CRT0=boot.s -WARNINGS=-Wall -Wextra -Wshadow -Wpointer-arith -Wbad-function-cast -Wcast-align -Wsign-compare \ - -Waggregate-return -Wstrict-prototypes -Wmissing-prototypes -Wmissing-declarations -Wunused - -# -# CFLAGS common to both the THUMB and ARM mode builds -# -CFLAGS=$(WARNINGS) -D $(RUN_MODE) -D GCC_ARM7 -I. -I../../Source/include \ - -I../Common/include $(DEBUG) -mcpu=arm7tdmi -T$(LDSCRIPT) \ - $(OPTIM) -fomit-frame-pointer - -ifeq ($(USE_THUMB_MODE),YES) - CFLAGS += -mthumb-interwork -D THUMB_INTERWORK - THUMB_FLAGS=-mthumb -endif - - -LINKER_FLAGS=-Xlinker -ortosdemo.elf -Xlinker -M -Xlinker -Map=rtosdemo.map - -RTOS_SOURCE_DIR=../../Source -DEMO_SOURCE_DIR=../Common/Minimal -# -# Source files that can be built to THUMB mode. -# -THUMB_SRC = \ -main.c \ -serial/serial.c \ -ParTest/ParTest.c \ -$(DEMO_SOURCE_DIR)/integer.c \ -$(DEMO_SOURCE_DIR)/flash.c \ -$(DEMO_SOURCE_DIR)/PollQ.c \ -$(DEMO_SOURCE_DIR)/comtest.c \ -$(DEMO_SOURCE_DIR)/flop.c \ -$(DEMO_SOURCE_DIR)/semtest.c \ -$(DEMO_SOURCE_DIR)/dynamic.c \ -$(DEMO_SOURCE_DIR)/BlockQ.c \ -$(RTOS_SOURCE_DIR)/tasks.c \ -$(RTOS_SOURCE_DIR)/queue.c \ -$(RTOS_SOURCE_DIR)/list.c \ -$(RTOS_SOURCE_DIR)/portable/MemMang/heap_2.c \ -$(RTOS_SOURCE_DIR)/portable/GCC/ARM7_LPC2000/port.c - -# -# Source files that must be built to ARM mode. -# -ARM_SRC = \ -$(RTOS_SOURCE_DIR)/portable/GCC/ARM7_LPC2000/portISR.c \ -serial/serialISR.c - -# -# Define all object files. -# -ARM_OBJ = $(ARM_SRC:.c=.o) -THUMB_OBJ = $(THUMB_SRC:.c=.o) - -rtosdemo.hex : rtosdemo.elf - $(OBJCOPY) rtosdemo.elf -O ihex rtosdemo.hex - -rtosdemo.elf : $(ARM_OBJ) $(THUMB_OBJ) $(CRT0) Makefile - $(CC) $(CFLAGS) $(ARM_OBJ) $(THUMB_OBJ) -nostartfiles $(CRT0) $(LINKER_FLAGS) - -$(THUMB_OBJ) : %.o : %.c $(LDSCRIPT) Makefile - $(CC) -c $(THUMB_FLAGS) $(CFLAGS) $< -o $@ - -$(ARM_OBJ) : %.o : %.c $(LDSCRIPT) Makefile - $(CC) -c $(CFLAGS) $< -o $@ - -clean : - touch Makefile - - - - - - - - - - - - diff --git a/Demo/ARM7_LPC2106_GCC/ParTest/ParTest.c b/Demo/ARM7_LPC2106_GCC/ParTest/ParTest.c deleted file mode 100644 index f0648c039..000000000 --- a/Demo/ARM7_LPC2106_GCC/ParTest/ParTest.c +++ /dev/null @@ -1,106 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - Changes from V2.5.2 - - + All LED's are turned off to start. -*/ - - -#include "FreeRTOS.h" -#include "partest.h" - -#define partstFIRST_IO ( ( unsigned portLONG ) 0x400 ) -#define partstNUM_LEDS ( 4 ) -#define partstALL_OUTPUTS_OFF ( ( unsigned portLONG ) 0xffffffff ) - -/*----------------------------------------------------------- - * Simple parallel port IO routines. - *-----------------------------------------------------------*/ - -void vParTestInitialise( void ) -{ - /* This is performed from main() as the io bits are shared with other setup - functions. */ - - /* Turn all outputs off. */ - GPIO_IOSET = partstALL_OUTPUTS_OFF; -} -/*-----------------------------------------------------------*/ - -void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) -{ -unsigned portLONG ulLED = partstFIRST_IO; - - if( uxLED < partstNUM_LEDS ) - { - /* Rotate to the wanted bit of port 0. Only P10 to P13 have an LED - attached. */ - ulLED <<= ( unsigned portLONG ) uxLED; - - /* Set of clear the output. */ - if( xValue ) - { - GPIO_IOCLR = ulLED; - } - else - { - GPIO_IOSET = ulLED; - } - } -} -/*-----------------------------------------------------------*/ - -void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) -{ -unsigned portLONG ulLED = partstFIRST_IO, ulCurrentState; - - if( uxLED < partstNUM_LEDS ) - { - /* Rotate to the wanted bit of port 0. Only P10 to P13 have an LED - attached. */ - ulLED <<= ( unsigned portLONG ) uxLED; - - /* If this bit is already set, clear it, and visa versa. */ - ulCurrentState = GPIO0_IOPIN; - if( ulCurrentState & ulLED ) - { - GPIO_IOCLR = ulLED; - } - else - { - GPIO_IOSET = ulLED; - } - } -} - diff --git a/Demo/ARM7_LPC2106_GCC/boot.s b/Demo/ARM7_LPC2106_GCC/boot.s deleted file mode 100644 index 33e5226eb..000000000 --- a/Demo/ARM7_LPC2106_GCC/boot.s +++ /dev/null @@ -1,157 +0,0 @@ - /* Sample initialization file */ - - .extern main - .extern exit - - .text - .code 32 - - - .align 0 - - .extern __bss_beg__ - .extern __bss_end__ - .extern __stack_end__ - .extern __data_beg__ - .extern __data_end__ - .extern __data+beg_src__ - - .global start - .global endless_loop - - /* Stack Sizes */ - .set UND_STACK_SIZE, 0x00000004 - .set ABT_STACK_SIZE, 0x00000004 - .set FIQ_STACK_SIZE, 0x00000004 - .set IRQ_STACK_SIZE, 0X00000400 - .set SVC_STACK_SIZE, 0x00000400 - - /* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */ - .set MODE_USR, 0x10 /* User Mode */ - .set MODE_FIQ, 0x11 /* FIQ Mode */ - .set MODE_IRQ, 0x12 /* IRQ Mode */ - .set MODE_SVC, 0x13 /* Supervisor Mode */ - .set MODE_ABT, 0x17 /* Abort Mode */ - .set MODE_UND, 0x1B /* Undefined Mode */ - .set MODE_SYS, 0x1F /* System Mode */ - - .equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */ - .equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */ - - -start: -_start: -_mainCRTStartup: - - /* Setup a stack for each mode - note that this only sets up a usable stack - for system/user, SWI and IRQ modes. Also each mode is setup with - interrupts initially disabled. */ - ldr r0, .LC6 - msr CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode - mov sp, r0 - sub r0, r0, #UND_STACK_SIZE - msr CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */ - mov sp, r0 - sub r0, r0, #ABT_STACK_SIZE - msr CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */ - mov sp, r0 - sub r0, r0, #FIQ_STACK_SIZE - msr CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */ - mov sp, r0 - sub r0, r0, #IRQ_STACK_SIZE - msr CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */ - mov sp, r0 - sub r0, r0, #SVC_STACK_SIZE - msr CPSR_c, #MODE_SYS|I_BIT|F_BIT /* System Mode */ - mov sp, r0 - - /* We want to start in supervisor mode. Operation will switch to system - mode when the first task starts. */ - msr CPSR_c, #MODE_SVC|I_BIT|F_BIT - - /* Clear BSS. */ - - mov a2, #0 /* Fill value */ - mov fp, a2 /* Null frame pointer */ - mov r7, a2 /* Null frame pointer for Thumb */ - - ldr r1, .LC1 /* Start of memory block */ - ldr r3, .LC2 /* End of memory block */ - subs r3, r3, r1 /* Length of block */ - beq .end_clear_loop - mov r2, #0 - -.clear_loop: - strb r2, [r1], #1 - subs r3, r3, #1 - bgt .clear_loop - -.end_clear_loop: - - /* Initialise data. */ - - ldr r1, .LC3 /* Start of memory block */ - ldr r2, .LC4 /* End of memory block */ - ldr r3, .LC5 - subs r3, r3, r1 /* Length of block */ - beq .end_set_loop - -.set_loop: - ldrb r4, [r2], #1 - strb r4, [r1], #1 - subs r3, r3, #1 - bgt .set_loop - -.end_set_loop: - - mov r0, #0 /* no arguments */ - mov r1, #0 /* no argv either */ - - bl main - -endless_loop: - b endless_loop - - - .align 0 - - .LC1: - .word __bss_beg__ - .LC2: - .word __bss_end__ - .LC3: - .word __data_beg__ - .LC4: - .word __data_beg_src__ - .LC5: - .word __data_end__ - .LC6: - .word __stack_end__ - - - /* Setup vector table. Note that undf, pabt, dabt, fiq just execute - a null loop. */ - -.section .startup,"ax" - .code 32 - .align 0 - - b _start /* reset - _start */ - ldr pc, _undf /* undefined - _undf */ - ldr pc, _swi /* SWI - _swi */ - ldr pc, _pabt /* program abort - _pabt */ - ldr pc, _dabt /* data abort - _dabt */ - nop /* reserved */ - ldr pc, [pc,#-0xFF0] /* IRQ - read the VIC */ - ldr pc, _fiq /* FIQ - _fiq */ - -_undf: .word __undf /* undefined */ -_swi: .word vPortYieldProcessor /* SWI */ -_pabt: .word __pabt /* program abort */ -_dabt: .word __dabt /* data abort */ -_fiq: .word __fiq /* FIQ */ - -__undf: b . /* undefined */ -__pabt: b . /* program abort */ -__dabt: b . /* data abort */ -__fiq: b . /* FIQ */ diff --git a/Demo/ARM7_LPC2106_GCC/lpc2106-ram.ld b/Demo/ARM7_LPC2106_GCC/lpc2106-ram.ld deleted file mode 100644 index c54802c2f..000000000 --- a/Demo/ARM7_LPC2106_GCC/lpc2106-ram.ld +++ /dev/null @@ -1,49 +0,0 @@ -MEMORY -{ - flash : ORIGIN = 0, LENGTH = 120K - ram : ORIGIN = 0x40000000, LENGTH = 64K -} - -__stack_end__ = 0x40000000 + 64K - 4; - -SECTIONS -{ - . = 0; - startup : { *(.startup)} >ram - - prog : - { - *(.text) - *(.rodata) - *(.rodata*) - *(.glue_7) - *(.glue_7t) - } >ram - - __end_of_text__ = .; - - .data : - { - __data_beg__ = .; - __data_beg_src__ = __end_of_text__; - *(.data) - __data_end__ = .; - } >ram - - .bss : - { - __bss_beg__ = .; - *(.bss) - } >ram - - /* Align here to ensure that the .bss section occupies space up to - _end. Align after .bss to ensure correct alignment even if the - .bss section disappears because there are no input sections. */ - . = ALIGN(32 / 8); -} - . = ALIGN(32 / 8); - _end = .; - _bss_end__ = . ; __bss_end__ = . ; __end__ = . ; - PROVIDE (end = .); - - diff --git a/Demo/ARM7_LPC2106_GCC/lpc2106-rom.ld b/Demo/ARM7_LPC2106_GCC/lpc2106-rom.ld deleted file mode 100644 index e7cf25a22..000000000 --- a/Demo/ARM7_LPC2106_GCC/lpc2106-rom.ld +++ /dev/null @@ -1,49 +0,0 @@ -MEMORY -{ - flash : ORIGIN = 0, LENGTH = 120K - ram : ORIGIN = 0x40000000, LENGTH = 64K -} - -__stack_end__ = 0x40000000 + 64K - 4; - -SECTIONS -{ - . = 0; - startup : { *(.startup)} >flash - - prog : - { - *(.text) - *(.rodata) - *(.rodata*) - *(.glue_7) - *(.glue_7t) - } >flash - - __end_of_text__ = .; - - .data : - { - __data_beg__ = .; - __data_beg_src__ = __end_of_text__; - *(.data) - __data_end__ = .; - } >ram AT>flash - - .bss : - { - __bss_beg__ = .; - *(.bss) - } >ram - - /* Align here to ensure that the .bss section occupies space up to - _end. Align after .bss to ensure correct alignment even if the - .bss section disappears because there are no input sections. */ - . = ALIGN(32 / 8); -} - . = ALIGN(32 / 8); - _end = .; - _bss_end__ = . ; __bss_end__ = . ; __end__ = . ; - PROVIDE (end = .); - - diff --git a/Demo/ARM7_LPC2106_GCC/lpc210x.h b/Demo/ARM7_LPC2106_GCC/lpc210x.h deleted file mode 100644 index 3f1e3042d..000000000 --- a/Demo/ARM7_LPC2106_GCC/lpc210x.h +++ /dev/null @@ -1,321 +0,0 @@ -#ifndef lpc210x_h -#define lpc210x_h -/******************************************************************************* -lpc210x.h - Register defs for Philips LPC210X: LPC2104, LPC2105 and LPC2106 - - -THE SOFTWARE IS DELIVERED "AS IS" WITHOUT WARRANTY OR CONDITION OF ANY KIND, -EITHER EXPRESS, IMPLIED OR STATUTORY. THIS INCLUDES WITHOUT LIMITATION ANY -WARRANTY OR CONDITION WITH RESPECT TO MERCHANTABILITY OR FITNESS FOR ANY -PARTICULAR PURPOSE, OR AGAINST THE INFRINGEMENTS OF INTELLECTUAL PROPERTY RIGHTS -OF OTHERS. - -This file may be freely used for commercial and non-commercial applications, -including being redistributed with any tools. - -If you find a problem with the file, please report it so that it can be fixed. - -Created by Sten Larsson (sten_larsson at yahoo com) - -Edited by Richard Barry. -*******************************************************************************/ - -#define REG8 (volatile unsigned char*) -#define REG16 (volatile unsigned short*) -#define REG32 (volatile unsigned int*) - - -/*############################################################################## -## MISC -##############################################################################*/ - - /* Constants for data to put in IRQ/FIQ Exception Vectors */ -#define VECTDATA_IRQ 0xE51FFFF0 /* LDR PC,[PC,#-0xFF0] */ -#define VECTDATA_FIQ /* __TODO */ - - -/*############################################################################## -## VECTORED INTERRUPT CONTROLLER -##############################################################################*/ - -#define VICIRQStatus (*(REG32 (0xFFFFF000))) -#define VICFIQStatus (*(REG32 (0xFFFFF004))) -#define VICRawIntr (*(REG32 (0xFFFFF008))) -#define VICIntSelect (*(REG32 (0xFFFFF00C))) -#define VICIntEnable (*(REG32 (0xFFFFF010))) -#define VICIntEnClear (*(REG32 (0xFFFFF014))) -#define VICSoftInt (*(REG32 (0xFFFFF018))) -#define VICSoftIntClear (*(REG32 (0xFFFFF01C))) -#define VICProtection (*(REG32 (0xFFFFF020))) -#define VICVectAddr (*(REG32 (0xFFFFF030))) -#define VICDefVectAddr (*(REG32 (0xFFFFF034))) - -#define VICVectAddr0 (*(REG32 (0xFFFFF100))) -#define VICVectAddr1 (*(REG32 (0xFFFFF104))) -#define VICVectAddr2 (*(REG32 (0xFFFFF108))) -#define VICVectAddr3 (*(REG32 (0xFFFFF10C))) -#define VICVectAddr4 (*(REG32 (0xFFFFF110))) -#define VICVectAddr5 (*(REG32 (0xFFFFF114))) -#define VICVectAddr6 (*(REG32 (0xFFFFF118))) -#define VICVectAddr7 (*(REG32 (0xFFFFF11C))) -#define VICVectAddr8 (*(REG32 (0xFFFFF120))) -#define VICVectAddr9 (*(REG32 (0xFFFFF124))) -#define VICVectAddr10 (*(REG32 (0xFFFFF128))) -#define VICVectAddr11 (*(REG32 (0xFFFFF12C))) -#define VICVectAddr12 (*(REG32 (0xFFFFF130))) -#define VICVectAddr13 (*(REG32 (0xFFFFF134))) -#define VICVectAddr14 (*(REG32 (0xFFFFF138))) -#define VICVectAddr15 (*(REG32 (0xFFFFF13C))) - -#define VICVectCntl0 (*(REG32 (0xFFFFF200))) -#define VICVectCntl1 (*(REG32 (0xFFFFF204))) -#define VICVectCntl2 (*(REG32 (0xFFFFF208))) -#define VICVectCntl3 (*(REG32 (0xFFFFF20C))) -#define VICVectCntl4 (*(REG32 (0xFFFFF210))) -#define VICVectCntl5 (*(REG32 (0xFFFFF214))) -#define VICVectCntl6 (*(REG32 (0xFFFFF218))) -#define VICVectCntl7 (*(REG32 (0xFFFFF21C))) -#define VICVectCntl8 (*(REG32 (0xFFFFF220))) -#define VICVectCntl9 (*(REG32 (0xFFFFF224))) -#define VICVectCntl10 (*(REG32 (0xFFFFF228))) -#define VICVectCntl11 (*(REG32 (0xFFFFF22C))) -#define VICVectCntl12 (*(REG32 (0xFFFFF230))) -#define VICVectCntl13 (*(REG32 (0xFFFFF234))) -#define VICVectCntl14 (*(REG32 (0xFFFFF238))) -#define VICVectCntl15 (*(REG32 (0xFFFFF23C))) - -#define VICITCR (*(REG32 (0xFFFFF300))) -#define VICITIP1 (*(REG32 (0xFFFFF304))) -#define VICITIP2 (*(REG32 (0xFFFFF308))) -#define VICITOP1 (*(REG32 (0xFFFFF30C))) -#define VICITOP2 (*(REG32 (0xFFFFF310))) -#define VICPeriphID0 (*(REG32 (0xFFFFFFE0))) -#define VICPeriphID1 (*(REG32 (0xFFFFFFE4))) -#define VICPeriphID2 (*(REG32 (0xFFFFFFE8))) -#define VICPeriphID3 (*(REG32 (0xFFFFFFEC))) - -#define VICIntEnClr VICIntEnClear -#define VICSoftIntClr VICSoftIntClear - - -/*############################################################################## -## PCB - Pin Connect Block -##############################################################################*/ - -#define PCB_PINSEL0 (*(REG32 (0xE002C000))) -#define PCB_PINSEL1 (*(REG32 (0xE002C004))) - - -/*############################################################################## -## GPIO - General Purpose I/O -##############################################################################*/ - -#define GPIO_IOPIN (*(REG32 (0xE0028000))) /* ALTERNATE NAME GPIO = GPIO0 */ -#define GPIO_IOSET (*(REG32 (0xE0028004))) -#define GPIO_IODIR (*(REG32 (0xE0028008))) -#define GPIO_IOCLR (*(REG32 (0xE002800C))) - -#define GPIO0_IOPIN (*(REG32 (0xE0028000))) /* ALTERNATE NAME GPIO = GPIO0 */ -#define GPIO0_IOSET (*(REG32 (0xE0028004))) -#define GPIO0_IODIR (*(REG32 (0xE0028008))) -#define GPIO0_IOCLR (*(REG32 (0xE002800C))) - - -/*############################################################################## -## UART0 / UART1 -##############################################################################*/ - -/* ---- UART 0 --------------------------------------------- */ -#define UART0_RBR (*(REG32 (0xE000C000))) -#define UART0_THR (*(REG32 (0xE000C000))) -#define UART0_IER (*(REG32 (0xE000C004))) -#define UART0_IIR (*(REG32 (0xE000C008))) -#define UART0_FCR (*(REG32 (0xE000C008))) -#define UART0_LCR (*(REG32 (0xE000C00C))) -#define UART0_LSR (*(REG32 (0xE000C014))) -#define UART0_SCR (*(REG32 (0xE000C01C))) -#define UART0_DLL (*(REG32 (0xE000C000))) -#define UART0_DLM (*(REG32 (0xE000C004))) - -/* ---- UART 1 --------------------------------------------- */ -#define UART1_RBR (*(REG32 (0xE0010000))) -#define UART1_THR (*(REG32 (0xE0010000))) -#define UART1_IER (*(REG32 (0xE0010004))) -#define UART1_IIR (*(REG32 (0xE0010008))) -#define UART1_FCR (*(REG32 (0xE0010008))) -#define UART1_LCR (*(REG32 (0xE001000C))) -#define UART1_LSR (*(REG32 (0xE0010014))) -#define UART1_SCR (*(REG32 (0xE001001C))) -#define UART1_DLL (*(REG32 (0xE0010000))) -#define UART1_DLM (*(REG32 (0xE0010004))) -#define UART1_MCR (*(REG32 (0xE0010010))) -#define UART1_MSR (*(REG32 (0xE0010018))) - - -/*############################################################################## -## I2C -##############################################################################*/ - -#define I2C_I2CONSET (*(REG32 (0xE001C000))) -#define I2C_I2STAT (*(REG32 (0xE001C004))) -#define I2C_I2DAT (*(REG32 (0xE001C008))) -#define I2C_I2ADR (*(REG32 (0xE001C00C))) -#define I2C_I2SCLH (*(REG32 (0xE001C010))) -#define I2C_I2SCLL (*(REG32 (0xE001C014))) -#define I2C_I2CONCLR (*(REG32 (0xE001C018))) - - -/*############################################################################## -## SPI - Serial Peripheral Interface -##############################################################################*/ - -#define SPI_SPCR (*(REG32 (0xE0020000))) -#define SPI_SPSR (*(REG32 (0xE0020004))) -#define SPI_SPDR (*(REG32 (0xE0020008))) -#define SPI_SPCCR (*(REG32 (0xE002000C))) -#define SPI_SPTCR (*(REG32 (0xE0020010))) -#define SPI_SPTSR (*(REG32 (0xE0020014))) -#define SPI_SPTOR (*(REG32 (0xE0020018))) -#define SPI_SPINT (*(REG32 (0xE002001C))) - - -/*############################################################################## -## Timer 0 and Timer 1 -##############################################################################*/ - -/* ---- Timer 0 -------------------------------------------- */ -#define T0_IR (*(REG32 (0xE0004000))) -#define T0_TCR (*(REG32 (0xE0004004))) -#define T0_TC (*(REG32 (0xE0004008))) -#define T0_PR (*(REG32 (0xE000400C))) -#define T0_PC (*(REG32 (0xE0004010))) -#define T0_MCR (*(REG32 (0xE0004014))) -#define T0_MR0 (*(REG32 (0xE0004018))) -#define T0_MR1 (*(REG32 (0xE000401C))) -#define T0_MR2 (*(REG32 (0xE0004020))) -#define T0_MR3 (*(REG32 (0xE0004024))) -#define T0_CCR (*(REG32 (0xE0004028))) -#define T0_CR0 (*(REG32 (0xE000402C))) -#define T0_CR1 (*(REG32 (0xE0004030))) -#define T0_CR2 (*(REG32 (0xE0004034))) -#define T0_CR3 (*(REG32 (0xE0004038))) -#define T0_EMR (*(REG32 (0xE000403C))) - -/* ---- Timer 1 -------------------------------------------- */ -#define T1_IR (*(REG32 (0xE0008000))) -#define T1_TCR (*(REG32 (0xE0008004))) -#define T1_TC (*(REG32 (0xE0008008))) -#define T1_PR (*(REG32 (0xE000800C))) -#define T1_PC (*(REG32 (0xE0008010))) -#define T1_MCR (*(REG32 (0xE0008014))) -#define T1_MR0 (*(REG32 (0xE0008018))) -#define T1_MR1 (*(REG32 (0xE000801C))) -#define T1_MR2 (*(REG32 (0xE0008020))) -#define T1_MR3 (*(REG32 (0xE0008024))) -#define T1_CCR (*(REG32 (0xE0008028))) -#define T1_CR0 (*(REG32 (0xE000802C))) -#define T1_CR1 (*(REG32 (0xE0008030))) -#define T1_CR2 (*(REG32 (0xE0008034))) -#define T1_CR3 (*(REG32 (0xE0008038))) -#define T1_EMR (*(REG32 (0xE000803C))) - - -/*############################################################################## -## PWM -##############################################################################*/ - -#define PWM_IR (*(REG32 (0xE0014000))) -#define PWM_TCR (*(REG32 (0xE0014004))) -#define PWM_TC (*(REG32 (0xE0014008))) -#define PWM_PR (*(REG32 (0xE001400C))) -#define PWM_PC (*(REG32 (0xE0014010))) -#define PWM_MCR (*(REG32 (0xE0014014))) -#define PWM_MR0 (*(REG32 (0xE0014018))) -#define PWM_MR1 (*(REG32 (0xE001401C))) -#define PWM_MR2 (*(REG32 (0xE0014020))) -#define PWM_MR3 (*(REG32 (0xE0014024))) -#define PWM_MR4 (*(REG32 (0xE0014040))) -#define PWM_MR5 (*(REG32 (0xE0014044))) -#define PWM_MR6 (*(REG32 (0xE0014048))) -#define PWM_EMR (*(REG32 (0xE001403C))) -#define PWM_PCR (*(REG32 (0xE001404C))) -#define PWM_LER (*(REG32 (0xE0014050))) -#define PWM_CCR (*(REG32 (0xE0014028))) -#define PWM_CR0 (*(REG32 (0xE001402C))) -#define PWM_CR1 (*(REG32 (0xE0014030))) -#define PWM_CR2 (*(REG32 (0xE0014034))) -#define PWM_CR3 (*(REG32 (0xE0014038))) - -/*############################################################################## -## RTC -##############################################################################*/ - -/* ---- RTC: Miscellaneous Register Group ------------------ */ -#define RTC_ILR (*(REG32 (0xE0024000))) -#define RTC_CTC (*(REG32 (0xE0024004))) -#define RTC_CCR (*(REG32 (0xE0024008))) -#define RTC_CIIR (*(REG32 (0xE002400C))) -#define RTC_AMR (*(REG32 (0xE0024010))) -#define RTC_CTIME0 (*(REG32 (0xE0024014))) -#define RTC_CTIME1 (*(REG32 (0xE0024018))) -#define RTC_CTIME2 (*(REG32 (0xE002401C))) - -/* ---- RTC: Timer Control Group --------------------------- */ -#define RTC_SEC (*(REG32 (0xE0024020))) -#define RTC_MIN (*(REG32 (0xE0024024))) -#define RTC_HOUR (*(REG32 (0xE0024028))) -#define RTC_DOM (*(REG32 (0xE002402C))) -#define RTC_DOW (*(REG32 (0xE0024030))) -#define RTC_DOY (*(REG32 (0xE0024034))) -#define RTC_MONTH (*(REG32 (0xE0024038))) -#define RTC_YEAR (*(REG32 (0xE002403C))) - -/* ---- RTC: Alarm Control Group --------------------------- */ -#define RTC_ALSEC (*(REG32 (0xE0024060))) -#define RTC_ALMIN (*(REG32 (0xE0024064))) -#define RTC_ALHOUR (*(REG32 (0xE0024068))) -#define RTC_ALDOM (*(REG32 (0xE002406C))) -#define RTC_ALDOW (*(REG32 (0xE0024070))) -#define RTC_ALDOY (*(REG32 (0xE0024074))) -#define RTC_ALMON (*(REG32 (0xE0024078))) -#define RTC_ALYEAR (*(REG32 (0xE002407C))) - -/* ---- RTC: Reference Clock Divider Group ----------------- */ -#define RTC_PREINT (*(REG32 (0xE0024080))) -#define RTC_PREFRAC (*(REG32 (0xE0024084))) - - -/*############################################################################## -## WD - Watchdog -##############################################################################*/ - -#define WD_WDMOD (*(REG32 (0xE0000000))) -#define WD_WDTC (*(REG32 (0xE0000004))) -#define WD_WDFEED (*(REG32 (0xE0000008))) -#define WD_WDTV (*(REG32 (0xE000000C))) - - -/*############################################################################## -## System Control Block -##############################################################################*/ - -#define SCB_EXTINT (*(REG32 (0xE01FC140))) -#define SCB_EXTWAKE (*(REG32 (0xE01FC144))) -#define SCB_MEMMAP (*(REG32 (0xE01FC040))) -#define SCB_PLLCON (*(REG32 (0xE01FC080))) -#define SCB_PLLCFG (*(REG32 (0xE01FC084))) -#define SCB_PLLSTAT (*(REG32 (0xE01FC088))) -#define SCB_PLLFEED (*(REG32 (0xE01FC08C))) -#define SCB_PCON (*(REG32 (0xE01FC0C0))) -#define SCB_PCONP (*(REG32 (0xE01FC0C4))) -#define SCB_VPBDIV (*(REG32 (0xE01FC100))) - -/*############################################################################## -## Memory Accelerator Module (MAM) -##############################################################################*/ - -#define MAM_TIM (*(REG32 (0xE01FC004))) -#define MAM_CR (*(REG32 (0xE01FC000))) - -#endif /* lpc210x_h */ - diff --git a/Demo/ARM7_LPC2106_GCC/lpc221x.h b/Demo/ARM7_LPC2106_GCC/lpc221x.h deleted file mode 100644 index 170bb435f..000000000 --- a/Demo/ARM7_LPC2106_GCC/lpc221x.h +++ /dev/null @@ -1 +0,0 @@ -#include "lpc2114.h" \ No newline at end of file diff --git a/Demo/ARM7_LPC2106_GCC/main.c b/Demo/ARM7_LPC2106_GCC/main.c deleted file mode 100644 index 8da209d29..000000000 --- a/Demo/ARM7_LPC2106_GCC/main.c +++ /dev/null @@ -1,474 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. - The processor MUST be in supervisor mode when vTaskStartScheduler is - called. The demo applications included in the FreeRTOS.org download switch - to supervisor mode prior to main being called. If you are not using one of - these demo application projects then ensure Supervisor mode is used. -*/ - - -/* - * Creates all the demo application tasks, then starts the scheduler. The WEB - * documentation provides more details of the demo application tasks. - * - * Main.c also creates a task called "Check". This only executes every three - * seconds but has the highest priority so is guaranteed to get processor time. - * Its main function is to check that all the other tasks are still operational. - * Each task (other than the "flash" tasks) maintains a unique count that is - * incremented each time the task successfully completes its function. Should - * any error occur within such a task the count is permanently halted. The - * check task inspects the count of each task to ensure it has changed since - * the last time the check task executed. If all the count variables have - * changed all the tasks are still executing error free, and the check task - * toggles the onboard LED. Should any task contain an error at any time - * the LED toggle rate will change from 3 seconds to 500ms. - * - * To check the operation of the memory allocator the check task also - * dynamically creates a task before delaying, and deletes it again when it - * wakes. If memory cannot be allocated for the new task the call to xTaskCreate - * will fail and an error is signalled. The dynamically created task itself - * allocates and frees memory just to give the allocator a bit more exercise. - * - */ - -/* - Changes from V2.4.2 - - + The vErrorChecks() task now dynamically creates then deletes a task each - cycle. This tests the operation of the memory allocator. - - Changes from V2.5.2 - - + vParTestInitialise() is called during initialisation to ensure all the - LED's start off. -*/ - - -/* Standard includes. */ -#include -#include - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Demo application includes. */ -#include "partest.h" -#include "flash.h" -#include "integer.h" -#include "PollQ.h" -#include "comtest2.h" -#include "semtest.h" -#include "flop.h" -#include "dynamic.h" -#include "BlockQ.h" -#include "serial.h" - -/*-----------------------------------------------------------*/ - -/* Constants to setup I/O. */ -#define mainTX_ENABLE ( ( unsigned portLONG ) 0x0001 ) -#define mainRX_ENABLE ( ( unsigned portLONG ) 0x0004 ) -#define mainP0_14 ( ( unsigned portLONG ) 0x4000 ) -#define mainJTAG_PORT ( ( unsigned portLONG ) 0x3E0000UL ) - -/* Constants to setup the PLL. */ -#define mainPLL_MUL_4 ( ( unsigned portCHAR ) 0x0003 ) -#define mainPLL_DIV_1 ( ( unsigned portCHAR ) 0x0000 ) -#define mainPLL_ENABLE ( ( unsigned portCHAR ) 0x0001 ) -#define mainPLL_CONNECT ( ( unsigned portCHAR ) 0x0003 ) -#define mainPLL_FEED_BYTE1 ( ( unsigned portCHAR ) 0xaa ) -#define mainPLL_FEED_BYTE2 ( ( unsigned portCHAR ) 0x55 ) -#define mainPLL_LOCK ( ( unsigned portLONG ) 0x0400 ) - -/* Constants to setup the MAM. */ -#define mainMAM_TIM_3 ( ( unsigned portCHAR ) 0x03 ) -#define mainMAM_MODE_FULL ( ( unsigned portCHAR ) 0x02 ) - -/* Constants to setup the peripheral bus. */ -#define mainBUS_CLK_FULL ( ( unsigned portCHAR ) 0x01 ) - -/* Constants for the ComTest tasks. */ -#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 115200 ) -#define mainCOM_TEST_LED ( 3 ) - -/* Priorities for the demo application tasks. */ -#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) - -/* The rate at which the on board LED will toggle when there is/is not an -error. */ -#define mainNO_ERROR_FLASH_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS ) -#define mainERROR_FLASH_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS ) -#define mainON_BOARD_LED_BIT ( ( unsigned portLONG ) 0x80 ) - -/* Constants used by the vMemCheckTask() task. */ -#define mainCOUNT_INITIAL_VALUE ( ( unsigned portLONG ) 0 ) -#define mainNO_TASK ( 0 ) - -/* The size of the memory blocks allocated by the vMemCheckTask() task. */ -#define mainMEM_CHECK_SIZE_1 ( ( size_t ) 51 ) -#define mainMEM_CHECK_SIZE_2 ( ( size_t ) 52 ) -#define mainMEM_CHECK_SIZE_3 ( ( size_t ) 151 ) - -/*-----------------------------------------------------------*/ - -/* - * The Olimex demo board has a single built in LED. This function simply - * toggles its state. - */ -void prvToggleOnBoardLED( void ); - -/* - * Checks that all the demo application tasks are still executing without error - * - as described at the top of the file. - */ -static portLONG prvCheckOtherTasksAreStillRunning( unsigned portLONG ulMemCheckTaskCount ); - -/* - * The task that executes at the highest priority and calls - * prvCheckOtherTasksAreStillRunning(). See the description at the top - * of the file. - */ -static void vErrorChecks( void *pvParameters ); - -/* - * Dynamically created and deleted during each cycle of the vErrorChecks() - * task. This is done to check the operation of the memory allocator. - * See the top of vErrorChecks for more details. - */ -static void vMemCheckTask( void *pvParameters ); - -/* - * Configure the processor for use with the Olimex demo board. This includes - * setup for the I/O, system clock, and access timings. - */ -static void prvSetupHardware( void ); - -/*-----------------------------------------------------------*/ - -/* - * Starts all the other tasks, then starts the scheduler. - */ -int main( void ) -{ - /* Setup the hardware for use with the Olimex demo board. */ - prvSetupHardware(); - - /* Start the demo/test application tasks. */ - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); - vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartMathTasks( tskIDLE_PRIORITY ); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartDynamicPriorityTasks(); - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - - /* Start the check task - which is defined in this file. */ - xTaskCreate( vErrorChecks, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - - /* Now all the tasks have been started - start the scheduler. - - NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. - The processor MUST be in supervisor mode when vTaskStartScheduler is - called. The demo applications included in the FreeRTOS.org download switch - to supervisor mode prior to main being called. If you are not using one of - these demo application projects then ensure Supervisor mode is used here. */ - vTaskStartScheduler(); - - /* Should never reach here! */ - return 0; -} -/*-----------------------------------------------------------*/ - -static void vErrorChecks( void *pvParameters ) -{ -portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD; -unsigned portLONG ulMemCheckTaskRunningCount; -xTaskHandle xCreatedTask; - - /* The parameters are not used in this function. */ - ( void ) pvParameters; - - /* Cycle for ever, delaying then checking all the other tasks are still - operating without error. If an error is detected then the delay period - is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so - the on board LED flash rate will increase. - - In addition to the standard tests the memory allocator is tested through - the dynamic creation and deletion of a task each cycle. Each time the - task is created memory must be allocated for its stack. When the task is - deleted this memory is returned to the heap. If the task cannot be created - then it is likely that the memory allocation failed. */ - - for( ;; ) - { - /* Dynamically create a task - passing ulMemCheckTaskRunningCount as a - parameter. */ - ulMemCheckTaskRunningCount = mainCOUNT_INITIAL_VALUE; - xCreatedTask = mainNO_TASK; - if( xTaskCreate( vMemCheckTask, ( signed portCHAR * ) "MEM_CHECK", configMINIMAL_STACK_SIZE, ( void * ) &ulMemCheckTaskRunningCount, tskIDLE_PRIORITY, &xCreatedTask ) != pdPASS ) - { - /* Could not create the task - we have probably run out of heap. */ - xDelayPeriod = mainERROR_FLASH_PERIOD; - } - - /* Delay until it is time to execute again. */ - vTaskDelay( xDelayPeriod ); - - /* Delete the dynamically created task. */ - if( xCreatedTask != mainNO_TASK ) - { - vTaskDelete( xCreatedTask ); - } - - /* Check all the standard demo application tasks are executing without - error. ulMemCheckTaskRunningCount is checked to ensure it was - modified by the task just deleted. */ - if( prvCheckOtherTasksAreStillRunning( ulMemCheckTaskRunningCount ) != pdPASS ) - { - /* An error has been detected in one of the tasks - flash faster. */ - xDelayPeriod = mainERROR_FLASH_PERIOD; - } - - prvToggleOnBoardLED(); - } -} -/*-----------------------------------------------------------*/ - -static void prvSetupHardware( void ) -{ - #ifdef RUN_FROM_RAM - /* Remap the interrupt vectors to RAM if we are are running from RAM. */ - SCB_MEMMAP = 2; - #endif - - /* Configure the RS2332 pins. All other pins remain at their default of 0. */ - PCB_PINSEL0 |= mainTX_ENABLE; - PCB_PINSEL0 |= mainRX_ENABLE; - - /* Set all GPIO to output other than the P0.14 (BSL), and the JTAG pins. - The JTAG pins are left as input as I'm not sure what will happen if the - Wiggler is connected after powerup - not that it would be a good idea to - do that anyway. */ - GPIO_IODIR = ~( mainP0_14 + mainJTAG_PORT ); - - /* Setup the PLL to multiply the XTAL input by 4. */ - SCB_PLLCFG = ( mainPLL_MUL_4 | mainPLL_DIV_1 ); - - /* Activate the PLL by turning it on then feeding the correct sequence of - bytes. */ - SCB_PLLCON = mainPLL_ENABLE; - SCB_PLLFEED = mainPLL_FEED_BYTE1; - SCB_PLLFEED = mainPLL_FEED_BYTE2; - - /* Wait for the PLL to lock... */ - while( !( SCB_PLLSTAT & mainPLL_LOCK ) ); - - /* ...before connecting it using the feed sequence again. */ - SCB_PLLCON = mainPLL_CONNECT; - SCB_PLLFEED = mainPLL_FEED_BYTE1; - SCB_PLLFEED = mainPLL_FEED_BYTE2; - - /* Setup and turn on the MAM. Three cycle access is used due to the fast - PLL used. It is possible faster overall performance could be obtained by - tuning the MAM and PLL settings. */ - MAM_TIM = mainMAM_TIM_3; - MAM_CR = mainMAM_MODE_FULL; - - /* Setup the peripheral bus to be the same as the PLL output. */ - SCB_VPBDIV = mainBUS_CLK_FULL; - - /* Initialise LED outputs. */ - vParTestInitialise(); -} -/*-----------------------------------------------------------*/ - -void prvToggleOnBoardLED( void ) -{ -unsigned portLONG ulState; - - ulState = GPIO0_IOPIN; - if( ulState & mainON_BOARD_LED_BIT ) - { - GPIO_IOCLR = mainON_BOARD_LED_BIT; - } - else - { - GPIO_IOSET = mainON_BOARD_LED_BIT; - } -} -/*-----------------------------------------------------------*/ - -static portLONG prvCheckOtherTasksAreStillRunning( unsigned portLONG ulMemCheckTaskCount ) -{ -portLONG lReturn = ( portLONG ) pdPASS; - - /* Check all the demo tasks (other than the flash tasks) to ensure - that they are all still running, and that none of them have detected - an error. */ - - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - lReturn = ( portLONG ) pdFAIL; - } - - if( xAreComTestTasksStillRunning() != pdTRUE ) - { - lReturn = ( portLONG ) pdFAIL; - } - - if( xArePollingQueuesStillRunning() != pdTRUE ) - { - lReturn = ( portLONG ) pdFAIL; - } - - if( xAreMathsTaskStillRunning() != pdTRUE ) - { - lReturn = ( portLONG ) pdFAIL; - } - - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - lReturn = ( portLONG ) pdFAIL; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - lReturn = ( portLONG ) pdFAIL; - } - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - lReturn = ( portLONG ) pdFAIL; - } - - if( ulMemCheckTaskCount == mainCOUNT_INITIAL_VALUE ) - { - /* The vMemCheckTask did not increment the counter - it must - have failed. */ - lReturn = ( portLONG ) pdFAIL; - } - - return lReturn; -} -/*-----------------------------------------------------------*/ - -static void vMemCheckTask( void *pvParameters ) -{ -unsigned portLONG *pulMemCheckTaskRunningCounter; -void *pvMem1, *pvMem2, *pvMem3; -static portLONG lErrorOccurred = pdFALSE; - - /* This task is dynamically created then deleted during each cycle of the - vErrorChecks task to check the operation of the memory allocator. Each time - the task is created memory is allocated for the stack and TCB. Each time - the task is deleted this memory is returned to the heap. This task itself - exercises the allocator by allocating and freeing blocks. - - The task executes at the idle priority so does not require a delay. - - pulMemCheckTaskRunningCounter is incremented each cycle to indicate to the - vErrorChecks() task that this task is still executing without error. */ - - pulMemCheckTaskRunningCounter = ( unsigned portLONG * ) pvParameters; - - for( ;; ) - { - if( lErrorOccurred == pdFALSE ) - { - /* We have never seen an error so increment the counter. */ - ( *pulMemCheckTaskRunningCounter )++; - } - - /* Allocate some memory - just to give the allocator some extra - exercise. This has to be in a critical section to ensure the - task does not get deleted while it has memory allocated. */ - vTaskSuspendAll(); - { - pvMem1 = pvPortMalloc( mainMEM_CHECK_SIZE_1 ); - if( pvMem1 == NULL ) - { - lErrorOccurred = pdTRUE; - } - else - { - memset( pvMem1, 0xaa, mainMEM_CHECK_SIZE_1 ); - vPortFree( pvMem1 ); - } - } - xTaskResumeAll(); - - /* Again - with a different size block. */ - vTaskSuspendAll(); - { - pvMem2 = pvPortMalloc( mainMEM_CHECK_SIZE_2 ); - if( pvMem2 == NULL ) - { - lErrorOccurred = pdTRUE; - } - else - { - memset( pvMem2, 0xaa, mainMEM_CHECK_SIZE_2 ); - vPortFree( pvMem2 ); - } - } - xTaskResumeAll(); - - /* Again - with a different size block. */ - vTaskSuspendAll(); - { - pvMem3 = pvPortMalloc( mainMEM_CHECK_SIZE_3 ); - if( pvMem3 == NULL ) - { - lErrorOccurred = pdTRUE; - } - else - { - memset( pvMem3, 0xaa, mainMEM_CHECK_SIZE_3 ); - vPortFree( pvMem3 ); - } - } - xTaskResumeAll(); - } -} - - - diff --git a/Demo/ARM7_LPC2106_GCC/ram_arm.bat b/Demo/ARM7_LPC2106_GCC/ram_arm.bat deleted file mode 100644 index 1f3c5da0a..000000000 --- a/Demo/ARM7_LPC2106_GCC/ram_arm.bat +++ /dev/null @@ -1,6 +0,0 @@ -set USE_THUMB_MODE=NO -set DEBUG=-g -set OPTIM=-O0 -set RUN_MODE=RUN_FROM_RAM -set LDSCRIPT=lpc2106-ram.ld -make diff --git a/Demo/ARM7_LPC2106_GCC/ram_thumb.bat b/Demo/ARM7_LPC2106_GCC/ram_thumb.bat deleted file mode 100644 index 414a3a6b6..000000000 --- a/Demo/ARM7_LPC2106_GCC/ram_thumb.bat +++ /dev/null @@ -1,6 +0,0 @@ -set USE_THUMB_MODE=YES -set DEBUG=-g -set OPTIM=-O0 -set RUN_MODE=RUN_FROM_RAM -set LDSCRIPT=lpc2106-ram.ld -make diff --git a/Demo/ARM7_LPC2106_GCC/readme.txt b/Demo/ARM7_LPC2106_GCC/readme.txt deleted file mode 100644 index af4856965..000000000 --- a/Demo/ARM7_LPC2106_GCC/readme.txt +++ /dev/null @@ -1,18 +0,0 @@ -Use one of the following four batch files to build the demo application: - -+ rom_arm.bat - -Creates an ARM mode release build suitable for programming into flash. - -+ ram_arm.bat - -Creates an ARM mode debug build suitable for running from RAM. - -+ rom_thumb.bat - -Creates a THUMB mode release build suitable for programming into flash. - -+ ram_thumb.bat - -Creates a THUMB mode debug build suitable for running from RAM. - diff --git a/Demo/ARM7_LPC2106_GCC/rom_arm.bat b/Demo/ARM7_LPC2106_GCC/rom_arm.bat deleted file mode 100644 index 7f7d88333..000000000 --- a/Demo/ARM7_LPC2106_GCC/rom_arm.bat +++ /dev/null @@ -1,6 +0,0 @@ -set USE_THUMB_MODE=NO -set DEBUG= -set OPTIM=-O3 -set RUN_MODE=RUN_FROM_ROM -set LDSCRIPT=lpc2106-rom.ld -make diff --git a/Demo/ARM7_LPC2106_GCC/rom_thumb.bat b/Demo/ARM7_LPC2106_GCC/rom_thumb.bat deleted file mode 100644 index ea9920402..000000000 --- a/Demo/ARM7_LPC2106_GCC/rom_thumb.bat +++ /dev/null @@ -1,6 +0,0 @@ -set USE_THUMB_MODE=YES -set DEBUG= -set OPTIM=-O3 -set RUN_MODE=RUN_FROM_ROM -set LDSCRIPT=lpc2106-rom.ld -make diff --git a/Demo/ARM7_LPC2106_GCC/serial/serial.c b/Demo/ARM7_LPC2106_GCC/serial/serial.c deleted file mode 100644 index de476bb06..000000000 --- a/Demo/ARM7_LPC2106_GCC/serial/serial.c +++ /dev/null @@ -1,263 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - Changes from V2.4.0 - - + Made serial ISR handling more complete and robust. - - Changes from V2.4.1 - - + Split serial.c into serial.c and serialISR.c. serial.c can be - compiled using ARM or THUMB modes. serialISR.c must always be - compiled in ARM mode. - + Another small change to cSerialPutChar(). - - Changed from V2.5.1 - - + In cSerialPutChar() an extra check is made to ensure the post to - the queue was successful if then attempting to retrieve the posted - character. - -*/ - -/* - BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0. - - This file contains all the serial port components that can be compiled to - either ARM or THUMB mode. Components that must be compiled to ARM mode are - contained in serialISR.c. -*/ - -/* Standard includes. */ -#include - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "queue.h" -#include "task.h" - -/* Demo application includes. */ -#include "serial.h" - -/*-----------------------------------------------------------*/ - -/* Constants to setup and access the UART. */ -#define serDLAB ( ( unsigned portCHAR ) 0x80 ) -#define serENABLE_INTERRUPTS ( ( unsigned portCHAR ) 0x03 ) -#define serNO_PARITY ( ( unsigned portCHAR ) 0x00 ) -#define ser1_STOP_BIT ( ( unsigned portCHAR ) 0x00 ) -#define ser8_BIT_CHARS ( ( unsigned portCHAR ) 0x03 ) -#define serFIFO_ON ( ( unsigned portCHAR ) 0x01 ) -#define serCLEAR_FIFO ( ( unsigned portCHAR ) 0x06 ) -#define serWANTED_CLOCK_SCALING ( ( unsigned portLONG ) 16 ) - -/* Constants to setup and access the VIC. */ -#define serUART0_VIC_CHANNEL ( ( unsigned portLONG ) 0x0006 ) -#define serUART0_VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x0040 ) -#define serUART0_VIC_ENABLE ( ( unsigned portLONG ) 0x0020 ) -#define serCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 ) - -#define serINVALID_QUEUE ( ( xQueueHandle ) 0 ) -#define serHANDLE ( ( xComPortHandle ) 1 ) -#define serNO_BLOCK ( ( portTickType ) 0 ) - -/*-----------------------------------------------------------*/ - -/* Queues used to hold received characters, and characters waiting to be -transmitted. */ -static xQueueHandle xRxedChars; -static xQueueHandle xCharsForTx; - -/*-----------------------------------------------------------*/ - -/* Communication flag between the interrupt service routine and serial API. */ -static volatile portLONG *plTHREEmpty; - -/* - * The queues are created in serialISR.c as they are used from the ISR. - * Obtain references to the queues and THRE Empty flag. - */ -extern void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, xQueueHandle *pxCharsForTx, portLONG volatile **pplTHREEmptyFlag ); - -/*-----------------------------------------------------------*/ - -xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) -{ -unsigned portLONG ulDivisor, ulWantedClock; -xComPortHandle xReturn = serHANDLE; -extern void ( vUART_ISR )( void ); - - /* The queues are used in the serial ISR routine, so are created from - serialISR.c (which is always compiled to ARM mode. */ - vSerialISRCreateQueues( uxQueueLength, &xRxedChars, &xCharsForTx, &plTHREEmpty ); - - if( - ( xRxedChars != serINVALID_QUEUE ) && - ( xCharsForTx != serINVALID_QUEUE ) && - ( ulWantedBaud != ( unsigned portLONG ) 0 ) - ) - { - portENTER_CRITICAL(); - { - /* Setup the baud rate: Calculate the divisor value. */ - ulWantedClock = ulWantedBaud * serWANTED_CLOCK_SCALING; - ulDivisor = configCPU_CLOCK_HZ / ulWantedClock; - - /* Set the DLAB bit so we can access the divisor. */ - UART0_LCR |= serDLAB; - - /* Setup the divisor. */ - UART0_DLL = ( unsigned portCHAR ) ( ulDivisor & ( unsigned portLONG ) 0xff ); - ulDivisor >>= 8; - UART0_DLM = ( unsigned portCHAR ) ( ulDivisor & ( unsigned portLONG ) 0xff ); - - /* Turn on the FIFO's and clear the buffers. */ - UART0_FCR = ( serFIFO_ON | serCLEAR_FIFO ); - - /* Setup transmission format. */ - UART0_LCR = serNO_PARITY | ser1_STOP_BIT | ser8_BIT_CHARS; - - /* Setup the VIC for the UART. */ - VICIntSelect &= ~( serUART0_VIC_CHANNEL_BIT ); - VICIntEnable |= serUART0_VIC_CHANNEL_BIT; - VICVectAddr1 = ( portLONG ) vUART_ISR; - VICVectCntl1 = serUART0_VIC_CHANNEL | serUART0_VIC_ENABLE; - - /* Enable UART0 interrupts. */ - UART0_IER |= serENABLE_INTERRUPTS; - } - portEXIT_CRITICAL(); - } - else - { - xReturn = ( xComPortHandle ) 0; - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) -{ - /* The port handle is not required as this driver only supports UART0. */ - ( void ) pxPort; - - /* Get the next character from the buffer. Return false if no characters - are available, or arrive before xBlockTime expires. */ - if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) - { - return pdTRUE; - } - else - { - return pdFALSE; - } -} -/*-----------------------------------------------------------*/ - -void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength ) -{ -signed portCHAR *pxNext; - - /* NOTE: This implementation does not handle the queue being full as no - block time is used! */ - - /* The port handle is not required as this driver only supports UART0. */ - ( void ) pxPort; - ( void ) usStringLength; - - /* Send each character in the string, one at a time. */ - pxNext = ( signed portCHAR * ) pcString; - while( *pxNext ) - { - xSerialPutChar( pxPort, *pxNext, serNO_BLOCK ); - pxNext++; - } -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) -{ -signed portBASE_TYPE xReturn; - - /* This demo driver only supports one port so the parameter is not used. */ - ( void ) pxPort; - - portENTER_CRITICAL(); - { - /* Is there space to write directly to the UART? */ - if( *plTHREEmpty == ( portLONG ) pdTRUE ) - { - /* We wrote the character directly to the UART, so was - successful. */ - *plTHREEmpty = pdFALSE; - UART0_THR = cOutChar; - xReturn = pdPASS; - } - else - { - /* We cannot write directly to the UART, so queue the character. - Block for a maximum of xBlockTime if there is no space in the - queue. */ - xReturn = xQueueSend( xCharsForTx, &cOutChar, xBlockTime ); - - /* Depending on queue sizing and task prioritisation: While we - were blocked waiting to post interrupts were not disabled. It is - possible that the serial ISR has emptied the Tx queue, in which - case we need to start the Tx off again. */ - if( ( *plTHREEmpty == ( portLONG ) pdTRUE ) && ( xReturn == pdPASS ) ) - { - xQueueReceive( xCharsForTx, &cOutChar, serNO_BLOCK ); - *plTHREEmpty = pdFALSE; - UART0_THR = cOutChar; - } - } - } - portEXIT_CRITICAL(); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -void vSerialClose( xComPortHandle xPort ) -{ - /* Not supported as not required by the demo application. */ - ( void ) xPort; -} -/*-----------------------------------------------------------*/ - - - - - - diff --git a/Demo/ARM7_LPC2106_GCC/serial/serialISR.c b/Demo/ARM7_LPC2106_GCC/serial/serialISR.c deleted file mode 100644 index 78486523d..000000000 --- a/Demo/ARM7_LPC2106_GCC/serial/serialISR.c +++ /dev/null @@ -1,163 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/* - BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0. - - This file contains all the serial port components that must be compiled - to ARM mode. The components that can be compiled to either ARM or THUMB - mode are contained in serial.c. - -*/ - -/* Standard includes. */ -#include - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "queue.h" -#include "task.h" - -/* Demo application includes. */ -#include "serial.h" - -/*-----------------------------------------------------------*/ - -/* Constant to access the VIC. */ -#define serCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 ) - -/* Constants to determine the ISR source. */ -#define serSOURCE_THRE ( ( unsigned portCHAR ) 0x02 ) -#define serSOURCE_RX_TIMEOUT ( ( unsigned portCHAR ) 0x0c ) -#define serSOURCE_ERROR ( ( unsigned portCHAR ) 0x06 ) -#define serSOURCE_RX ( ( unsigned portCHAR ) 0x04 ) -#define serINTERRUPT_SOURCE_MASK ( ( unsigned portCHAR ) 0x0f ) - -/* Queues used to hold received characters, and characters waiting to be -transmitted. */ -static xQueueHandle xRxedChars; -static xQueueHandle xCharsForTx; -static volatile portLONG lTHREEmpty; - -/*-----------------------------------------------------------*/ - -/* - * The queues are created in serialISR.c as they are used from the ISR. - * Obtain references to the queues and THRE Empty flag. - */ -void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, xQueueHandle *pxCharsForTx, portLONG volatile **pplTHREEmptyFlag ); - -/* UART0 interrupt service routine. This can cause a context switch so MUST -be declared "naked". */ -void vUART_ISR( void ) __attribute__ ((naked)); - -/*-----------------------------------------------------------*/ -void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, - xQueueHandle *pxCharsForTx, portLONG volatile **pplTHREEmptyFlag ) -{ - /* Create the queues used to hold Rx and Tx characters. */ - xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); - xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); - - /* Pass back a reference to the queues so the serial API file can - post/receive characters. */ - *pxRxedChars = xRxedChars; - *pxCharsForTx = xCharsForTx; - - /* Initialise the THRE empty flag - and pass back a reference. */ - lTHREEmpty = ( portLONG ) pdTRUE; - *pplTHREEmptyFlag = &lTHREEmpty; -} -/*-----------------------------------------------------------*/ - -void vUART_ISR( void ) -{ - /* This ISR can cause a context switch, so the first statement must be a - call to the portENTER_SWITCHING_ISR() macro. This must be BEFORE any - variable declarations. */ - portENTER_SWITCHING_ISR(); - - /* Now we can declare the local variables. */ - signed portCHAR cChar; - portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByRx = pdFALSE; - - /* What caused the interrupt? */ - switch( UART0_IIR & serINTERRUPT_SOURCE_MASK ) - { - case serSOURCE_ERROR : /* Not handling this, but clear the interrupt. */ - cChar = UART0_LSR; - break; - - case serSOURCE_THRE : /* The THRE is empty. If there is another - character in the Tx queue, send it now. */ - if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE ) - { - UART0_THR = cChar; - } - else - { - /* There are no further characters - queued to send so we can indicate - that the THRE is available. */ - lTHREEmpty = pdTRUE; - } - break; - - case serSOURCE_RX_TIMEOUT : - case serSOURCE_RX : /* A character was received. Place it in - the queue of received characters. */ - cChar = UART0_RBR; - if( xQueueSendFromISR( xRxedChars, &cChar, ( portBASE_TYPE ) pdFALSE ) ) - { - xTaskWokenByRx = pdTRUE; - } - break; - - default : /* There is nothing to do, leave the ISR. */ - break; - } - - /* Clear the ISR in the VIC. */ - VICVectAddr = serCLEAR_VIC_INTERRUPT; - - /* Exit the ISR. If a task was woken by either a character being received - or transmitted then a context switch will occur. */ - portEXIT_SWITCHING_ISR( ( xTaskWokenByTx || xTaskWokenByRx ) ); -} -/*-----------------------------------------------------------*/ - - - - - - diff --git a/Demo/ARM7_LPC2129_IAR/FreeRTOSConfig.h b/Demo/ARM7_LPC2129_IAR/FreeRTOSConfig.h deleted file mode 100644 index 8b52d6064..000000000 --- a/Demo/ARM7_LPC2129_IAR/FreeRTOSConfig.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/* Hardware specifics. */ -#include - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 60000000 ) /* =12.0MHz xtal multiplied by 5 using the PLL. */ -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 100 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) 14200 ) -#define configMAX_TASK_NAME_LEN ( 16 ) -#define configUSE_TRACE_FACILITY 0 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 1 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 0 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/ARM7_LPC2129_IAR/ParTest/ParTest.c b/Demo/ARM7_LPC2129_IAR/ParTest/ParTest.c deleted file mode 100644 index 2ec45de9c..000000000 --- a/Demo/ARM7_LPC2129_IAR/ParTest/ParTest.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/*----------------------------------------------------------- - * Simple parallel port IO routines for the LED's. - *-----------------------------------------------------------*/ - - -/* Scheduler includes. */ -#include "FreeRTOS.h" - -/* Demo application includes. */ -#include "partest.h" - -/* Board specific defines. */ -#define partstFIRST_IO ( ( unsigned portLONG ) 0x10000 ) -#define partstNUM_LEDS ( 8 ) - -/*-----------------------------------------------------------*/ - -void vParTestInitialise( void ) -{ - /* The ports are setup within prvInitialiseHardware(), called by main(). */ -} -/*-----------------------------------------------------------*/ - -void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) -{ -unsigned portLONG ulLED = partstFIRST_IO; - - if( uxLED < partstNUM_LEDS ) - { - /* Rotate to the wanted bit of port 1. Only P16 to P23 have an LED - attached. */ - ulLED <<= ( unsigned portLONG ) uxLED; - - /* Set or clear the output. */ - if( xValue ) - { - IO1SET = ulLED; - } - else - { - IO1CLR = ulLED; - } - } -} -/*-----------------------------------------------------------*/ - -void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) -{ -unsigned portLONG ulLED = partstFIRST_IO, ulCurrentState; - - if( uxLED < partstNUM_LEDS ) - { - /* Rotate to the wanted bit of port 1. Only P10 to P13 have an LED - attached. */ - ulLED <<= ( unsigned portLONG ) uxLED; - - /* If this bit is already set, clear it, and visa versa. */ - ulCurrentState = IO1PIN; - if( ulCurrentState & ulLED ) - { - IO1CLR = ulLED; - } - else - { - IO1SET = ulLED; - } - } -} - - diff --git a/Demo/ARM7_LPC2129_IAR/SrcIAR/cstartup.s79 b/Demo/ARM7_LPC2129_IAR/SrcIAR/cstartup.s79 deleted file mode 100644 index c920a210a..000000000 --- a/Demo/ARM7_LPC2129_IAR/SrcIAR/cstartup.s79 +++ /dev/null @@ -1,173 +0,0 @@ -;----------------------------------------------------------------------------- -; This file contains the startup code used by the ICCARM C compiler. -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; All code in the modules (except ?RESET) will be placed in the ICODE segment. -; -; $Revision: 1.56 $ -; -;----------------------------------------------------------------------------- - -; -; Naming covention of labels in this file: -; -; ?xxx - External labels only accessed from assembler. -; __xxx - External labels accessed from or defined in C. -; xxx - Labels local to one module (note: this file contains -; several modules). -; main - The starting point of the user program. -; - -;--------------------------------------------------------------- -; Macros and definitions for the whole file -;--------------------------------------------------------------- - -; Mode, correspords to bits 0-5 in CPSR -MODE_BITS DEFINE 0x1F ; Bit mask for mode bits in CPSR -USR_MODE DEFINE 0x10 ; User mode -FIQ_MODE DEFINE 0x11 ; Fast Interrupt Request mode -IRQ_MODE DEFINE 0x12 ; Interrupt Request mode -SVC_MODE DEFINE 0x13 ; Supervisor mode -ABT_MODE DEFINE 0x17 ; Abort mode -UND_MODE DEFINE 0x1B ; Undefined Instruction mode -SYS_MODE DEFINE 0x1F ; System mode - -I_Bit DEFINE 0x80 ; IRQ Disable Bit -F_Bit DEFINE 0x40 ; FIQ Disable Bit - -;--------------------------------------------------------------- -; ?RESET -; Reset Vector. -; Normally, segment INTVEC is linked at address 0. -; For debugging purposes, INTVEC may be placed at other -; addresses. -; A debugger that honors the entry point will start the -; program in a normal way even if INTVEC is not at address 0. -;--------------------------------------------------------------- - - MODULE ?RESET - COMMON INTVEC:CODE:NOROOT(2) - PUBLIC __program_start - EXTERN ?cstartup - EXTERN undef_handler, swi_handler, prefetch_handler - EXTERN data_handler, irq_handler, fiq_handler - EXTERN vPortYieldProcessor - - CODE32 ; Always ARM mode after reset - -__program_start - - org 0x00 - - B InitReset ; 0x00 Reset handler - undefvec: - B undefvec ; 0x04 Undefined Instruction - swivec: - B vPortYieldProcessor ; 0x08 Software Interrupt - pabtvec: - B pabtvec ; 0x0C Prefetch Abort - dabtvec: - B dabtvec ; 0x10 Data Abort - rsvdvec: - B rsvdvec ; 0x14 reserved - irqvec: - LDR PC, [PC, #-0xFF0] ; Jump directly to the address given by the AIC - - fiqvec: ; 0x1c FIQ - - -;--------------------------------------------------------------- -; ?CSTARTUP -;--------------------------------------------------------------- - - RSEG IRQ_STACK:DATA(2) - RSEG SVC_STACK:DATA:NOROOT(2) - RSEG CSTACK:DATA(2) - RSEG ICODE:CODE:NOROOT(2) - EXTERN ?main - -; Execution starts here. -; After a reset, the mode is ARM, Supervisor, interrupts disabled. - - - CODE32 - -InitReset - -; Add initialization needed before setup of stackpointers here - - -; Initialize the stack pointers. -; The pattern below can be used for any of the exception stacks: -; FIQ, IRQ, SVC, ABT, UND, SYS. -; The USR mode uses the same stack as SYS. -; The stack segments must be defined in the linker command file, -; and be declared above. - mrs r0,cpsr ; Original PSR value - bic r0,r0,#MODE_BITS ; Clear the mode bits - orr r0,r0,#IRQ_MODE ; Set IRQ mode bits - msr cpsr_c,r0 ; Change the mode - ldr sp,=SFE(IRQ_STACK) & 0xFFFFFFF8 ; End of IRQ_STACK - - bic r0,r0,#MODE_BITS ; Clear the mode bits - orr r0,r0,#SYS_MODE ; Set System mode bits - msr cpsr_c,r0 ; Change the mode - ldr sp,=SFE(CSTACK) & 0xFFFFFFF8 ; End of CSTACK - - bic r0,r0,#MODE_BITS ; Clear the mode bits - orr r0,r0,#SVC_MODE ; Set System mode bits - msr cpsr_c,r0 ; Change the mode - ldr sp,=SFE(SVC_STACK) & 0xFFFFFFF8 ; End of CSTACK - -; Must start in supervisor mode. - MSR CPSR_c, #SVC_MODE|I_Bit|F_Bit - - -; Add more initialization here - - -; Continue to ?main for more IAR specific system startup - - ldr r0,=?main - bx r0 - - - - -;--------------------------------------------------------------- -; ?EXEPTION_VECTOR -; This module is only linked if needed for closing files. -;--------------------------------------------------------------- - PUBLIC AT91F_Default_FIQ_handler - PUBLIC AT91F_Default_IRQ_handler - PUBLIC AT91F_Spurious_handler - - CODE32 ; Always ARM mode after exeption - -AT91F_Default_FIQ_handler - b AT91F_Default_FIQ_handler - -AT91F_Default_IRQ_handler - b AT91F_Default_IRQ_handler - -AT91F_Spurious_handler - b AT91F_Spurious_handler - - ENDMOD - - END - - - - - ENDMOD - END - - - - diff --git a/Demo/ARM7_LPC2129_IAR/main.c b/Demo/ARM7_LPC2129_IAR/main.c deleted file mode 100644 index 542321c55..000000000 --- a/Demo/ARM7_LPC2129_IAR/main.c +++ /dev/null @@ -1,284 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/* - NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. - The processor MUST be in supervisor mode when vTaskStartScheduler is - called. The demo applications included in the FreeRTOS.org download switch - to supervisor mode prior to main being called. If you are not using one of - these demo application projects then ensure Supervisor mode is used. -*/ - - -/* - * Creates all the demo application tasks, then starts the scheduler. The WEB - * documentation provides more details of the demo application tasks. - * - * Main.c also creates a task called "Check". This only executes every three - * seconds but has the highest priority so is guaranteed to get processor time. - * Its main function is to check that all the other tasks are still operational. - * Each task (other than the "flash" tasks) maintains a unique count that is - * incremented each time the task successfully completes its function. Should - * any error occur within such a task the count is permanently halted. The - * check task inspects the count of each task to ensure it has changed since - * the last time the check task executed. If all the count variables have - * changed all the tasks are still executing error free, and the check task - * toggles the onboard LED. Should any task contain an error at any time - * the LED toggle rate will change from 3 seconds to 500ms. - * - */ - -/* Standard includes. */ -#include - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Demo application includes. */ -#include "flash.h" -#include "integer.h" -#include "PollQ.h" -#include "BlockQ.h" -#include "semtest.h" -#include "dynamic.h" -#include "partest.h" -#include "comtest2.h" - -/* Priorities for the demo application tasks. */ -#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) - -/* Constants required by the 'Check' task. */ -#define mainNO_ERROR_FLASH_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS ) -#define mainERROR_FLASH_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS ) -#define mainCHECK_TASK_LED ( 7 ) - -/* Constants for the ComTest tasks. */ -#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 115200 ) -#define mainCOM_TEST_LED ( 4 ) -#define mainTX_ENABLE ( ( unsigned portLONG ) 0x0001 ) -#define mainRX_ENABLE ( ( unsigned portLONG ) 0x0004 ) - -/* Constants to setup the PLL. */ -#define mainPLL_MUL_4 ( ( unsigned portCHAR ) 0x0003 ) -#define mainPLL_DIV_1 ( ( unsigned portCHAR ) 0x0000 ) -#define mainPLL_ENABLE ( ( unsigned portCHAR ) 0x0001 ) -#define mainPLL_CONNECT ( ( unsigned portCHAR ) 0x0003 ) -#define mainPLL_FEED_BYTE1 ( ( unsigned portCHAR ) 0xaa ) -#define mainPLL_FEED_BYTE2 ( ( unsigned portCHAR ) 0x55 ) -#define mainPLL_LOCK ( ( unsigned portLONG ) 0x0400 ) - -/* Constants to setup the MAM. */ -#define mainMAM_TIM_3 ( ( unsigned portCHAR ) 0x03 ) -#define mainMAM_MODE_FULL ( ( unsigned portCHAR ) 0x02 ) - -/* Constants to setup the peripheral bus. */ -#define mainBUS_CLK_FULL ( ( unsigned portCHAR ) 0x01 ) - -/* And finally, constant to setup the port for the LED's. */ -#define mainLED_TO_OUTPUT ( ( unsigned portLONG ) 0xff0000 ) - -/* - * The task that executes at the highest priority and calls - * prvCheckOtherTasksAreStillRunning(). See the description at the top - * of the file. - */ -static void vErrorChecks( void *pvParameters ); - -/* - * Configures the processor for use with this demo. - */ -static void prvSetupHardware( void ); - -/* - * Checks that all the demo application tasks are still executing without error - * - as described at the top of the file. - */ -static portLONG prvCheckOtherTasksAreStillRunning( void ); - - -/*-----------------------------------------------------------*/ - -/* - * Starts all the other tasks, then starts the scheduler. - */ -void main( void ) -{ - /* Setup the processor. */ - prvSetupHardware(); - - /* Start all the standard demo application tasks. */ - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - vStartDynamicPriorityTasks(); - vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); - - /* Start the check task - which is defined in this file. */ - xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - - /* Start the scheduler. - - NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. - The processor MUST be in supervisor mode when vTaskStartScheduler is - called. The demo applications included in the FreeRTOS.org download switch - to supervisor mode prior to main being called. If you are not using one of - these demo application projects then ensure Supervisor mode is used here. - */ - vTaskStartScheduler(); - - /* We should never get here as control is now taken by the scheduler. */ - return; -} -/*-----------------------------------------------------------*/ - -static void prvSetupHardware( void ) -{ - /* Setup the PLL to multiply the XTAL input by 4. */ - PLLCFG = ( mainPLL_MUL_4 | mainPLL_DIV_1 ); - - /* Activate the PLL by turning it on then feeding the correct sequence of - bytes. */ - PLLCON = mainPLL_ENABLE; - PLLFEED = mainPLL_FEED_BYTE1; - PLLFEED = mainPLL_FEED_BYTE2; - - /* Wait for the PLL to lock... */ - while( !( PLLSTAT & mainPLL_LOCK ) ); - - /* ...before connecting it using the feed sequence again. */ - PLLCON = mainPLL_CONNECT; - PLLFEED = mainPLL_FEED_BYTE1; - PLLFEED = mainPLL_FEED_BYTE2; - - /* Setup and turn on the MAM. Three cycle access is used due to the fast - PLL used. It is possible faster overall performance could be obtained by - tuning the MAM and PLL settings. */ - MAMTIM = mainMAM_TIM_3; - MAMCR = mainMAM_MODE_FULL; - - /* Setup the peripheral bus to be the same as the PLL output. */ - VPBDIV = mainBUS_CLK_FULL; - - /* Configure the RS2332 pins. All other pins remain at their default of 0. */ - PINSEL0 |= mainTX_ENABLE; - PINSEL0 |= mainRX_ENABLE; - - /* LED pins need to be output. */ - IO1DIR = mainLED_TO_OUTPUT; - - /* Setup the peripheral bus to be the same as the PLL output. */ - VPBDIV = mainBUS_CLK_FULL; -} -/*-----------------------------------------------------------*/ - -static void vErrorChecks( void *pvParameters ) -{ -portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD; - - /* The parameters are not used in this task. */ - ( void ) pvParameters; - - /* Cycle for ever, delaying then checking all the other tasks are still - operating without error. If an error is detected then the delay period - is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so - the on board LED flash rate will increase. */ - - for( ;; ) - { - /* Delay until it is time to execute again. */ - vTaskDelay( xDelayPeriod ); - - /* Check all the standard demo application tasks are executing without - error. */ - if( prvCheckOtherTasksAreStillRunning() != pdPASS ) - { - /* An error has been detected in one of the tasks - flash faster. */ - xDelayPeriod = mainERROR_FLASH_PERIOD; - } - - vParTestToggleLED( mainCHECK_TASK_LED ); - } -} -/*-----------------------------------------------------------*/ - -static portLONG prvCheckOtherTasksAreStillRunning( void ) -{ -portLONG lReturn = ( portLONG ) pdPASS; - - /* Check all the demo tasks (other than the flash tasks) to ensure - that they are all still running, and that none of them have detected - an error. */ - - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - lReturn = ( portLONG ) pdFAIL; - } - - if( xArePollingQueuesStillRunning() != pdTRUE ) - { - lReturn = ( portLONG ) pdFAIL; - } - - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - lReturn = ( portLONG ) pdFAIL; - } - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - lReturn = ( portLONG ) pdFAIL; - } - - if( xAreComTestTasksStillRunning() != pdTRUE ) - { - lReturn = ( portLONG ) pdFAIL; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - lReturn = ( portLONG ) pdFAIL; - } - - return lReturn; -} -/*-----------------------------------------------------------*/ - - diff --git a/Demo/ARM7_LPC2129_IAR/resource/lpc212x.xcl b/Demo/ARM7_LPC2129_IAR/resource/lpc212x.xcl deleted file mode 100644 index 5d427ec66..000000000 --- a/Demo/ARM7_LPC2129_IAR/resource/lpc212x.xcl +++ /dev/null @@ -1,190 +0,0 @@ -//************************************************************************* -// XLINK command file template for EWARM/ICCARM -// -// Usage: xlink -f lnkarm -// -s -// -// $Revision: 1.1 $ -//************************************************************************* - -//************************************************************************* -// -// ------------- -// Code segments - may be placed anywhere in memory. -// ------------- -// -// INTVEC -- Exception vector table. -// SWITAB -- Software interrupt vector table. -// ICODE -- Startup (cstartup) and exception code. -// DIFUNCT -- Dynamic initialization vectors used by C++. -// CODE -- Compiler generated code. -// CODE_I -- Compiler generated code declared __ramfunc (executes in RAM) -// CODE_ID -- Initializer for CODE_I (ROM). -// -// ------------- -// Data segments - may be placed anywhere in memory. -// ------------- -// -// CSTACK -- The stack used by C/C++ programs (system and user mode). -// IRQ_STACK -- The stack used by IRQ service routines. -// SVC_STACK -- The stack used in supervisor mode -// (Define other exception stacks as needed for -// FIQ, ABT, UND). -// HEAP -- The heap used by malloc and free in C and new and -// delete in C++. -// INITTAB -- Table containing addresses and sizes of segments that -// need to be initialized at startup (by cstartup). -// CHECKSUM -- The linker places checksum byte(s) in this segment, -// when the -J linker command line option is used. -// DATA_y -- Data objects. -// -// Where _y can be one of: -// -// _AN -- Holds uninitialized located objects, i.e. objects with -// an absolute location given by the @ operator or the -// #pragma location directive. Since these segments -// contain objects which already have a fixed address, -// they should not be mentioned in this linker command -// file. -// _C -- Constants (ROM). -// _I -- Initialized data (RAM). -// _ID -- The original content of _I (copied to _I by cstartup) (ROM). -// _N -- Uninitialized data (RAM). -// _Z -- Zero initialized data (RAM). -// -// Note: Be sure to use end values for the defined address ranges. -// Otherwise, the linker may allocate space outside the -// intended memory range. -//************************************************************************* - - -//************************************************ -// Inform the linker about the CPU family used. -//************************************************ - --carm - -//************************************************************************* -// Segment placement - General information -// -// All numbers in the segment placement command lines below are interpreted -// as hexadecimal unless they are immediately preceded by a '.', which -// denotes decimal notation. -// -// When specifying the segment placement using the -P instead of the -Z -// option, the linker is free to split each segment into its segment parts -// and randomly place these parts within the given ranges in order to -// achieve a more efficient memory usage. One disadvantage, however, is -// that it is not possible to find the start or end address (using -// the assembler operators .sfb./.sfe.) of a segment which has been split -// and reformed. -// -// When generating an output file which is to be used for programming -// external ROM/Flash devices, the -M linker option is very useful -// (see xlink.pdf for details). -//************************************************************************* - - -//************************************************************************* -// Read-only segments mapped to ROM. -//************************************************************************* - --DROMSTART=00000000 --DROMEND=00001ffff - -//************************************************ -// Address range for reset and exception -// vectors (INTVEC). -// The vector area is 32 bytes, -// an additional 32 bytes is allocated for the -// constant table used by ldr PC in cstartup.s79. -//************************************************ - --Z(CODE)INTVEC=00000000-0000003f - -//************************************************ -// Startup code and exception routines (ICODE). -//************************************************ - --Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND --Z(CODE)SWITAB=ROMSTART-ROMEND - -//************************************************ -// Code segments may be placed anywhere. -//************************************************ - --Z(CODE)CODE=ROMSTART-ROMEND - -//************************************************ -// Original ROM location for __ramfunc code copied -// to and executed from RAM. -//************************************************ - --Z(CONST)CODE_ID=ROMSTART-ROMEND - -//************************************************ -// Various constants and initializers. -//************************************************ - --Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND --Z(CONST)CHECKSUM=ROMSTART-ROMEND - -//************************************************************************* -// Read/write segments mapped to RAM. -//************************************************************************* - --DRAMSTART=40000000 --DRAMEND=40003fff - -//************************************************ -// Data segments. -//************************************************ - --Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND - -//************************************************ -// __ramfunc code copied to and executed from RAM. -//************************************************ - --Z(DATA)CODE_I=RAMSTART-RAMEND - -//************************************************ -// ICCARM produces code for __ramfunc functions in -// CODE_I segments. The -Q XLINK command line -// option redirects XLINK to emit the code in the -// CODE_ID segment instead, but to keep symbol and -// debug information associated with the CODE_I -// segment, where the code will execute. -//************************************************ - --QCODE_I=CODE_ID - -//************************************************************************* -// Stack and heap segments. -//************************************************************************* - --D_CSTACK_SIZE=200 --D_SVC_STACK_SIZE=190 --D_IRQ_STACK_SIZE=190 --D_HEAP_SIZE=4 - --Z(DATA)CSTACK+_CSTACK_SIZE=RAMSTART-RAMEND --Z(DATA)SVC_STACK+_SVC_STACK_SIZE=RAMSTART-RAMEND --Z(DATA)IRQ_STACK+_IRQ_STACK_SIZE,HEAP+_HEAP_SIZE=RAMSTART-RAMEND - -//************************************************************************* -// ELF/DWARF support. -// -// Uncomment the line "-Felf" below to generate ELF/DWARF output. -// Available format specifiers are: -// -// "-yn": Suppress DWARF debug output -// "-yp": Multiple ELF program sections -// "-yas": Format suitable for debuggers from ARM Ltd (also sets -p flag) -// -// "-Felf" and the format specifiers can also be supplied directly as -// command line options, or selected from the Xlink Output tab in the -// IAR Embedded Workbench. -//************************************************************************* - -// -Felf diff --git a/Demo/ARM7_LPC2129_IAR/rtosdemo.ewd b/Demo/ARM7_LPC2129_IAR/rtosdemo.ewd deleted file mode 100644 index 41a42a723..000000000 --- a/Demo/ARM7_LPC2129_IAR/rtosdemo.ewd +++ /dev/null @@ -1,913 +0,0 @@ - - - - 1 - - Flash Debug - - ARM - - 1 - - C-SPY - 2 - - 13 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - ARMSIM_ID - 2 - - 0 - 1 - 1 - - - - - ANGEL_ID - 2 - - 0 - 1 - 1 - - - - - - - - - - - - IARROM_ID - 2 - - 0 - 1 - 1 - - - - - - - - - - JLINK_ID - 2 - - 2 - 1 - 1 - - - - - - - - - - - - - - - - - - - MACRAIGOR_ID - 2 - - 1 - 1 - 1 - - - - - - - - - - - - - - - - - - RDI_ID - 2 - - 1 - 1 - 1 - - - - - - - - - - - - - - - - - THIRDPARTY_ID - 2 - - 0 - 1 - 1 - - - - - - - - - $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin - 1 - - - $EW_DIR$\common\plugins\Profiling\Profiling.ewplugin - 1 - - - $EW_DIR$\common\plugins\Trace\Trace.ewplugin - 1 - - - $EW_DIR$\common\plugins\Orti\Orti.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin - 0 - - - - - Flash Bin - - ARM - - 0 - - C-SPY - 2 - - 13 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - ARMSIM_ID - 2 - - 0 - 1 - 0 - - - - - ANGEL_ID - 2 - - 0 - 1 - 0 - - - - - - - - - - - - IARROM_ID - 2 - - 0 - 1 - 0 - - - - - - - - - - JLINK_ID - 2 - - 2 - 1 - 0 - - - - - - - - - - - - - - - - - - - MACRAIGOR_ID - 2 - - 1 - 1 - 0 - - - - - - - - - - - - - - - - - - RDI_ID - 2 - - 1 - 1 - 0 - - - - - - - - - - - - - - - - - THIRDPARTY_ID - 2 - - 0 - 1 - 0 - - - - - - - - - $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin - 1 - - - $EW_DIR$\common\plugins\Profiling\Profiling.ewplugin - 1 - - - $EW_DIR$\common\plugins\Trace\Trace.ewplugin - 1 - - - $EW_DIR$\common\plugins\Orti\Orti.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin - 0 - - - - - - diff --git a/Demo/ARM7_LPC2129_IAR/rtosdemo.ewp b/Demo/ARM7_LPC2129_IAR/rtosdemo.ewp deleted file mode 100644 index 9d363c963..000000000 --- a/Demo/ARM7_LPC2129_IAR/rtosdemo.ewp +++ /dev/null @@ -1,1732 +0,0 @@ - - - - 1 - - Flash Debug - - ARM - - 1 - - General - 2 - - 9 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 13 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 6 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - XLINK - 2 - - 17 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - XAR - 2 - - 0 - 1 - 1 - - - - - - - BILINK - 0 - - - - - Flash Bin - - ARM - - 0 - - General - 2 - - 9 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 13 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 6 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - XLINK - 2 - - 17 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - XAR - 2 - - 0 - 1 - 0 - - - - - - - BILINK - 0 - - - - - Demo Source - - $PROJ_DIR$\..\Common\Minimal\BlockQ.c - - - $PROJ_DIR$\..\Common\Minimal\comtest.c - - - $PROJ_DIR$\..\Common\Minimal\dynamic.c - - - $PROJ_DIR$\..\Common\Minimal\flash.c - - - $PROJ_DIR$\..\..\Source\portable\MemMang\heap_1.c - - - $PROJ_DIR$\..\Common\Minimal\integer.c - - - $PROJ_DIR$\main.c - - - $PROJ_DIR$\ParTest\ParTest.c - - - $PROJ_DIR$\..\Common\Minimal\PollQ.c - - - $PROJ_DIR$\..\Common\Minimal\semtest.c - - - $PROJ_DIR$\serial\serial.c - - - $PROJ_DIR$\serial\serialISR.s79 - - - - Scheduler Source - - $PROJ_DIR$\..\..\Source\list.c - - - $PROJ_DIR$\..\..\Source\portable\IAR\LPC2000\port.c - - - $PROJ_DIR$\..\..\Source\portable\IAR\LPC2000\portasm.s79 - - - $PROJ_DIR$\..\..\Source\queue.c - - - $PROJ_DIR$\..\..\Source\tasks.c - - - - System Files - - $PROJ_DIR$\SrcIAR\cstartup.s79 - - - - - diff --git a/Demo/ARM7_LPC2129_IAR/rtosdemo.eww b/Demo/ARM7_LPC2129_IAR/rtosdemo.eww deleted file mode 100644 index 2294aacb5..000000000 --- a/Demo/ARM7_LPC2129_IAR/rtosdemo.eww +++ /dev/null @@ -1,10 +0,0 @@ - - - - - $WS_DIR$\rtosdemo.ewp - - - - - diff --git a/Demo/ARM7_LPC2129_IAR/serial/serial.c b/Demo/ARM7_LPC2129_IAR/serial/serial.c deleted file mode 100644 index 138b1a812..000000000 --- a/Demo/ARM7_LPC2129_IAR/serial/serial.c +++ /dev/null @@ -1,288 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/* - BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0. -*/ - -/* Standard includes. */ -#include - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "queue.h" -#include "task.h" - -/* Demo application includes. */ -#include "serial.h" - -/*-----------------------------------------------------------*/ - -/* Constants to setup and access the UART. */ -#define serDLAB ( ( unsigned portCHAR ) 0x80 ) -#define serENABLE_INTERRUPTS ( ( unsigned portCHAR ) 0x03 ) -#define serNO_PARITY ( ( unsigned portCHAR ) 0x00 ) -#define ser1_STOP_BIT ( ( unsigned portCHAR ) 0x00 ) -#define ser8_BIT_CHARS ( ( unsigned portCHAR ) 0x03 ) -#define serFIFO_ON ( ( unsigned portCHAR ) 0x01 ) -#define serCLEAR_FIFO ( ( unsigned portCHAR ) 0x06 ) -#define serWANTED_CLOCK_SCALING ( ( unsigned portLONG ) 16 ) - -/* Constants to setup and access the VIC. */ -#define serU0VIC_CHANNEL ( ( unsigned portLONG ) 0x0006 ) -#define serU0VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x0040 ) -#define serU0VIC_ENABLE ( ( unsigned portLONG ) 0x0020 ) -#define serCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 ) - -/* Constants to determine the ISR source. */ -#define serSOURCE_THRE ( ( unsigned portCHAR ) 0x02 ) -#define serSOURCE_RX_TIMEOUT ( ( unsigned portCHAR ) 0x0c ) -#define serSOURCE_ERROR ( ( unsigned portCHAR ) 0x06 ) -#define serSOURCE_RX ( ( unsigned portCHAR ) 0x04 ) -#define serINTERRUPT_SOURCE_MASK ( ( unsigned portCHAR ) 0x0f ) - -/* Misc. */ -#define serINVALID_QUEUE ( ( xQueueHandle ) 0 ) -#define serHANDLE ( ( xComPortHandle ) 1 ) -#define serNO_BLOCK ( ( portTickType ) 0 ) - -/*-----------------------------------------------------------*/ - -/* Queues used to hold received characters, and characters waiting to be -transmitted. */ -static xQueueHandle xRxedChars; -static xQueueHandle xCharsForTx; -static volatile portLONG lTHREEmpty = pdFALSE; - -/*-----------------------------------------------------------*/ - -/* The ISR. Note that this is called by a wrapper written in the file -SerialISR.s79. See the WEB documentation for this port for further -information. */ -__arm void vSerialISR( void ); - -/*-----------------------------------------------------------*/ - -xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) -{ -unsigned portLONG ulDivisor, ulWantedClock; -xComPortHandle xReturn = serHANDLE; -extern void ( vSerialISREntry) ( void ); - - /* Create the queues used to hold Rx and Tx characters. */ - xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); - xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); - - /* Initialise the THRE empty flag. */ - lTHREEmpty = pdTRUE; - - if( - ( xRxedChars != serINVALID_QUEUE ) && - ( xCharsForTx != serINVALID_QUEUE ) && - ( ulWantedBaud != ( unsigned portLONG ) 0 ) - ) - { - portENTER_CRITICAL(); - { - /* Setup the baud rate: Calculate the divisor value. */ - ulWantedClock = ulWantedBaud * serWANTED_CLOCK_SCALING; - ulDivisor = configCPU_CLOCK_HZ / ulWantedClock; - - /* Set the DLAB bit so we can access the divisor. */ - U0LCR |= serDLAB; - - /* Setup the divisor. */ - U0DLL = ( unsigned portCHAR ) ( ulDivisor & ( unsigned portLONG ) 0xff ); - ulDivisor >>= 8; - U0DLM = ( unsigned portCHAR ) ( ulDivisor & ( unsigned portLONG ) 0xff ); - - /* Turn on the FIFO's and clear the buffers. */ - U0FCR = ( serFIFO_ON | serCLEAR_FIFO ); - - /* Setup transmission format. */ - U0LCR = serNO_PARITY | ser1_STOP_BIT | ser8_BIT_CHARS; - - /* Setup the VIC for the UART. */ - VICIntSelect &= ~( serU0VIC_CHANNEL_BIT ); - VICIntEnable |= serU0VIC_CHANNEL_BIT; - VICVectAddr1 = ( unsigned portLONG ) vSerialISREntry; - VICVectCntl1 = serU0VIC_CHANNEL | serU0VIC_ENABLE; - - /* Enable UART0 interrupts. */ - U0IER |= serENABLE_INTERRUPTS; - } - portEXIT_CRITICAL(); - - xReturn = ( xComPortHandle ) 1; - } - else - { - xReturn = ( xComPortHandle ) 0; - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) -{ - /* The port handle is not required as this driver only supports UART0. */ - ( void ) pxPort; - - /* Get the next character from the buffer. Return false if no characters - are available, or arrive before xBlockTime expires. */ - if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) - { - return pdTRUE; - } - else - { - return pdFALSE; - } -} -/*-----------------------------------------------------------*/ - -void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength ) -{ -signed portCHAR *pxNext; - - /* NOTE: This implementation does not handle the queue being full as no - block time is used! */ - - /* The port handle is not required as this driver only supports UART0. */ - ( void ) pxPort; - ( void ) usStringLength; - - /* Send each character in the string, one at a time. */ - pxNext = ( signed portCHAR * ) pcString; - while( *pxNext ) - { - xSerialPutChar( pxPort, *pxNext, serNO_BLOCK ); - pxNext++; - } -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) -{ -signed portBASE_TYPE xReturn; - - /* The port handle is not required as this driver only supports UART0. */ - ( void ) pxPort; - - portENTER_CRITICAL(); - { - /* Is there space to write directly to the UART? */ - if( lTHREEmpty == ( portLONG ) pdTRUE ) - { - /* We wrote the character directly to the UART, so was - successful. */ - lTHREEmpty = pdFALSE; - U0THR = cOutChar; - xReturn = pdPASS; - } - else - { - /* We cannot write directly to the UART, so queue the character. - Block for a maximum of xBlockTime if there is no space in the - queue. It is ok to block within a critical section as each - task has it's own critical section management. */ - xReturn = xQueueSend( xCharsForTx, &cOutChar, xBlockTime ); - - /* Depending on queue sizing and task prioritisation: While we - were blocked waiting to post interrupts were not disabled. It is - possible that the serial ISR has emptied the Tx queue, in which - case we need to start the Tx off again. */ - if( lTHREEmpty == ( portLONG ) pdTRUE ) - { - xQueueReceive( xCharsForTx, &cOutChar, serNO_BLOCK ); - lTHREEmpty = pdFALSE; - U0THR = cOutChar; - } - } - } - portEXIT_CRITICAL(); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -__arm void vSerialISR( void ) -{ -signed portCHAR cChar; -portBASE_TYPE xTaskWokenByRx = pdFALSE, xTaskWokenByTx = pdFALSE; - - /* What caused the interrupt? */ - switch( U0IIR & serINTERRUPT_SOURCE_MASK ) - { - case serSOURCE_ERROR : /* Not handling this, but clear the interrupt. */ - cChar = U0LSR; - break; - - case serSOURCE_THRE : /* The THRE is empty. If there is another - character in the Tx queue, send it now. */ - if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE ) - { - U0THR = cChar; - } - else - { - /* There are no further characters - queued to send so we can indicate - that the THRE is available. */ - lTHREEmpty = pdTRUE; - } - break; - - case serSOURCE_RX_TIMEOUT : - case serSOURCE_RX : /* A character was received. Place it in - the queue of received characters. */ - cChar = U0RBR; - if( xQueueSendFromISR( xRxedChars, &cChar, pdFALSE ) ) - { - xTaskWokenByRx = pdTRUE; - } - break; - - default : /* There is nothing to do, leave the ISR. */ - break; - } - - /* Exit the ISR. If a task was woken by either a character being received - or transmitted then a context switch will occur. */ - portEND_SWITCHING_ISR( ( xTaskWokenByTx || xTaskWokenByRx ) ); - - /* Clear the ISR in the VIC. */ - VICVectAddr = serCLEAR_VIC_INTERRUPT; -} -/*-----------------------------------------------------------*/ diff --git a/Demo/ARM7_LPC2129_IAR/serial/serialISR.s79 b/Demo/ARM7_LPC2129_IAR/serial/serialISR.s79 deleted file mode 100644 index da0a0bd17..000000000 --- a/Demo/ARM7_LPC2129_IAR/serial/serialISR.s79 +++ /dev/null @@ -1,24 +0,0 @@ - RSEG ICODE:CODE - CODE32 - - EXTERN vSerialISR - PUBLIC vSerialISREntry - -; Wrapper for the serial port interrupt service routine. This can cause a -; context switch so requires an assembly wrapper. - -; Defines the portSAVE_CONTEXT and portRESTORE_CONTEXT macros. -#include "ISR_Support.h" - -vSerialISREntry: - - portSAVE_CONTEXT ; Save the context of the current task. - - bl vSerialISR ; Call the ISR routine. - - portRESTORE_CONTEXT ; Restore the context of the current task - - ; which may be different to the task that - ; was interrupted. - - END - diff --git a/Demo/ARM7_LPC2129_IAR/settings/Basic.dbgdt b/Demo/ARM7_LPC2129_IAR/settings/Basic.dbgdt deleted file mode 100644 index 5085f2cdb..000000000 --- a/Demo/ARM7_LPC2129_IAR/settings/Basic.dbgdt +++ /dev/null @@ -1,71 +0,0 @@ - - - - - - - - - - - 1892727 - - - - - - 200100 - - - 200188171100100010 - - - - - TabID-23416-30482 - Workspace - Workspace - - - rtosdemo - - - - 0 - - - - - TabID-12145-30489 - Debug Log - Debug-Log - - - - TabID-22894-30492 - Build - Build - - - - - 1 - TabID-18780-12821MemoryMemory2097764209776410000TabID-23506-14575WatchWatchpxCurrentTCBulCriticalNesting01761001001000TabID-4859-22480DisassemblyDisassembly0TabID-154-22568RegisterRegister0001CPSR0 - - - - - - TextEditorE:\Dev\FreeRTOS\Demo\ARM7_Ateml_IAR\main.c010378378TextEditorE:\Dev\FreeRTOS\source\include\task.h07782428324283TextEditorE:\Dev\FreeRTOS\Source\tasks.c09393051130511TextEditorE:\Dev\FreeRTOS\Demo\ARM7_Ateml_IAR\SrcIAR\Cstartup.s7904822262226TextEditorE:\Dev\FreeRTOS\Demo\Common\Minimal\flash.c09840254025TextEditorE:\Dev\FreeRTOS\Source\portable\IAR\AtmelSAM7\portasm.s7904110571079TextEditorE:\Dev\FreeRTOS\Demo\ARM7_Ateml_IAR\srciar\lib_AT91SAM7S64.h02778108450108450TextEditorE:\Dev\FreeRTOS\Source\portable\IAR\AtmelSAM7\port.c0136532653267TextEditorE:\Dev\FreeRTOS\Demo\ARM7_Ateml_IAR\ParTest\ParTest.c03600TextEditorE:\Dev\FreeRTOS\Source\portable\IAR\AtmelSAM7\portmacro.h067000100000010000001 - - - - - - - IarIdePM1DebuggerGui1-2-2715263-2-215315395625136729165625640750-2-2715647-2-2190190118750169794405625640750-26457151025645-2190190118750169794237500640750-2-21511602-2-21604153100250013672995625136729149-2333669-21496711844193751644321143751635381496673331602667149935184584375164432115000598748 - - - - diff --git a/Demo/ARM7_LPC2129_IAR/settings/Basic.dni b/Demo/ARM7_LPC2129_IAR/settings/Basic.dni deleted file mode 100644 index 9b68f65a8..000000000 --- a/Demo/ARM7_LPC2129_IAR/settings/Basic.dni +++ /dev/null @@ -1,23 +0,0 @@ -[DisAssemblyWindow] -NumStates=_ 1 -State 1=_ 1 -[JLinkDriver] -WatchVectorCatch=_ 0 -WatchCond=_ 0 -Watch0=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 -Watch1=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 -[Log file] -LoggingEnabled=_ 0 -LogFile=_ "" -Category=_ 0 -[TermIOLog] -LoggingEnabled=_ 0 -LogFile=_ "" -[Disassemble mode] -mode=0 -[Breakpoints] -Bp0=_ "Code" "{E:\Dev\FreeRTOS\Source\portable\IAR\AtmelSAM7\port.c}.141.1@1" 1 0 0 0 "" 0 "" -Count=1 -[Low Level] -Pipeline mode=0 -Initialized=0 diff --git a/Demo/ARM7_LPC2129_IAR/settings/rtosdemo.dbgdt b/Demo/ARM7_LPC2129_IAR/settings/rtosdemo.dbgdt deleted file mode 100644 index cee08cd82..000000000 --- a/Demo/ARM7_LPC2129_IAR/settings/rtosdemo.dbgdt +++ /dev/null @@ -1,62 +0,0 @@ - - - - - - - - - - - 138272727 - - - - - - 200100 - 300Build - 300Debug-Log - - - - - - - 200 - - 161100100100300010300300200100100100100200100100100100 - - - - - - - - TabID-22256-14845 - Workspace - Workspace - - - rtosdemortosdemo/Demo Sourcertosdemo/Scheduler Sourcertosdemo/System Filesrtosdemo/USBSample.c - - - - 0TabID-32269-5949Debug LogDebug-LogTabID-30271-4373BreakpointsBreakpoints0 - - - - - - TextEditorE:\Dev\FreeRTOS\Source\list.c015964866613TextEditorE:\Dev\FreeRTOS\Source\include\list.h0000TextEditorE:\Dev\FreeRTOS\Source\tasks.c017269426959TextEditorE:\Dev\FreeRTOS\Source\include\task.h05022822291TextEditorE:\Dev\FreeRTOS\Demo\ARM7_LPC2129_IAR\serial\serialISR.s790000TextEditorE:\Dev\FreeRTOS\Source\portable\IAR\LPC2000\ISR_Support.h0000TextEditorE:\Dev\FreeRTOS\Source\portable\IAR\LPC2000\portmacro.h05225222531TextEditorE:\Dev\FreeRTOS\Source\queue.c014875937593TextEditorE:\Dev\FreeRTOS\Demo\ARM7_LPC2129_IAR\main.c016671727172TextEditorE:\Dev\FreeRTOS\Source\portable\MemMang\heap_1.c0752927293890100000010000001 - - - - - - - iaridepm1debuggergui1-2-2739212-2-20000133750662198-2-23331602-2-21604335100250029937492500132260 - - - - diff --git a/Demo/ARM7_LPC2129_IAR/settings/rtosdemo.dni b/Demo/ARM7_LPC2129_IAR/settings/rtosdemo.dni deleted file mode 100644 index b3fefed21..000000000 --- a/Demo/ARM7_LPC2129_IAR/settings/rtosdemo.dni +++ /dev/null @@ -1,33 +0,0 @@ -[DisAssemblyWindow] -NumStates=_ 1 -State 1=_ 1 -[JLinkDriver] -WatchVectorCatch=_ 0 -WatchCond=_ 0 -Watch0=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 -Watch1=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 -[Low Level] -Pipeline mode=1 -Initialized=0 -[Log file] -LoggingEnabled=_ 0 -LogFile=_ "" -Category=_ 0 -[TermIOLog] -LoggingEnabled=_ 0 -LogFile=_ "" -[Disassemble mode] -mode=0 -[Breakpoints] -Bp0=_ "Code" "{E:\Dev\FreeRTOS\Source\queue.c}.179.3@1" 1 0 0 0 "" 0 "" -Count=1 -[Interrupts] -Enabled=1 -[MemoryMap] -Enabled=0 -TypeVolition=1 -UnspecRange=1 -ActionState=1 -[TraceHelper] -Enabled=0 -ShowSource=1 diff --git a/Demo/ARM7_LPC2129_IAR/settings/rtosdemo.wsdt b/Demo/ARM7_LPC2129_IAR/settings/rtosdemo.wsdt deleted file mode 100644 index 90d8027fe..000000000 --- a/Demo/ARM7_LPC2129_IAR/settings/rtosdemo.wsdt +++ /dev/null @@ -1,60 +0,0 @@ - - - - - - rtosdemo/Flash Debug - - - - - - - - 229272727 - - 18115530877 - - - - - - - - - - - 10001055278946 - - - - - - - TabID-17425-14382 - Workspace - Workspace - - - rtosdemortosdemo/Scheduler Sourcertosdemo/System Files - - - - 0TabID-22109-27077BuildBuildTabID-12074-10873BreakpointsBreakpointsTabID-18349-15872Debug LogDebug-LogTabID-30013-18825Find in FilesFind-in-Files0 - - - - - - TextEditorE:\Dev\FreeRTOS\Source\list.c015964866613TextEditorE:\Dev\FreeRTOS\Source\include\list.h0000TextEditorE:\Dev\FreeRTOS\Source\tasks.c017269426959TextEditorE:\Dev\FreeRTOS\Source\include\task.h05022822291TextEditorE:\Dev\FreeRTOS\Demo\ARM7_LPC2129_IAR\serial\serialISR.s790000TextEditorE:\Dev\FreeRTOS\Source\portable\IAR\LPC2000\ISR_Support.h0000TextEditorE:\Dev\FreeRTOS\Source\portable\IAR\LPC2000\portmacro.h05225222531TextEditorE:\Dev\FreeRTOS\Source\queue.c014875937593TextEditorE:\Dev\FreeRTOS\Demo\ARM7_LPC2129_IAR\main.c016671727172TextEditorE:\Dev\FreeRTOS\Source\portable\MemMang\heap_1.c0752927293890100000010000001 - - - - - - - iaridepm1-2-2944303-2-20000190625845397-2-21281602-2-2160413010025001161755500078641 - - - - diff --git a/Demo/ARM7_LPC2129_IAR/settings/rtosdemo_lnk.par b/Demo/ARM7_LPC2129_IAR/settings/rtosdemo_lnk.par deleted file mode 100644 index 738732e18..000000000 --- a/Demo/ARM7_LPC2129_IAR/settings/rtosdemo_lnk.par +++ /dev/null @@ -1,17 +0,0 @@ -// IAR XLINK Setup -// Autogenerated file - do not edit -% -setrangelist($evec_ADR,[0-3F]); -setrangelist($internal_ROM,[8000-FFFFF]); -setrangelist($external_ROM,[]); -setrangelist($internal_RAM,[100000-7FFFFF]); -setrangelist($external_RAM,[]); -$CSTACK_SIZE=200; -$IRQSTACK_SIZE=400; -$HEAP_SIZE=4; -$COMMANDS=""; -$STACK_LOCATION="Internal RAM"; -$IRQSTACK_LOCATION="Internal RAM"; -$HEAP_LOCATION="Internal RAM"; -$iar_saved_xclfilename="E:\Dev\FreeRTOS\Demo\ARM7_LPC2129_IAR\resource\rtosdemo_lnk.xcl"; -% \ No newline at end of file diff --git a/Demo/ARM7_LPC2129_Keil/FreeRTOSConfig.h b/Demo/ARM7_LPC2129_Keil/FreeRTOSConfig.h deleted file mode 100644 index e6926e81c..000000000 --- a/Demo/ARM7_LPC2129_Keil/FreeRTOSConfig.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -#include - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 60000000 ) /* =12.0MHz xtal multiplied by 5 using the PLL. */ -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 100 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) 14250 ) -#define configMAX_TASK_NAME_LEN ( 16 ) -#define configUSE_TRACE_FACILITY 0 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 1 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 - - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/ARM7_LPC2129_Keil/ParTest/ParTest.c b/Demo/ARM7_LPC2129_Keil/ParTest/ParTest.c deleted file mode 100644 index 5fc0363ff..000000000 --- a/Demo/ARM7_LPC2129_Keil/ParTest/ParTest.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -#include "FreeRTOS.h" -#include "portable.h" -#include "partest.h" - -#define partstFIRST_IO ( ( unsigned portLONG ) 0x10000 ) -#define partstNUM_LEDS ( 8 ) - -/*----------------------------------------------------------- - * Simple parallel port IO routines. - *-----------------------------------------------------------*/ - -void vParTestInitialise( void ) -{ - /* This is performed from main() as the io bits are shared with other setup - functions. */ -} -/*-----------------------------------------------------------*/ - -void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) -{ -unsigned portLONG ulLED = partstFIRST_IO; - - if( uxLED < partstNUM_LEDS ) - { - /* Rotate to the wanted bit of port 0. Only P16 to P23 have an LED - attached. */ - ulLED <<= ( unsigned portLONG ) uxLED; - - /* Set or clear the output. */ - if( xValue ) - { - IOSET1 = ulLED; - } - else - { - IOCLR1 = ulLED; - } - } -} -/*-----------------------------------------------------------*/ - -void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) -{ -unsigned portLONG ulLED = partstFIRST_IO, ulCurrentState; - - if( uxLED < partstNUM_LEDS ) - { - /* Rotate to the wanted bit of port 0. Only P10 to P13 have an LED - attached. */ - ulLED <<= ( unsigned portLONG ) uxLED; - - /* If this bit is already set, clear it, and visa versa. */ - ulCurrentState = IOPIN1; - if( ulCurrentState & ulLED ) - { - IOCLR1 = ulLED; - } - else - { - IOSET1 = ulLED; - } - } -} - diff --git a/Demo/ARM7_LPC2129_Keil/RTOSDemoSignal.UVL b/Demo/ARM7_LPC2129_Keil/RTOSDemoSignal.UVL deleted file mode 100644 index 7df396ed8..000000000 --- a/Demo/ARM7_LPC2129_Keil/RTOSDemoSignal.UVL +++ /dev/null @@ -1,40 +0,0 @@ -[Signal 1] -DispName=Port1 -PlotType=1 -Color=16711935 -MinDec=0 -MinVal=0. -MaxDec=0 -MaxVal=-1. -Mask=65536 -Offset=16 -[Signal 2] -DispName=Port1 -PlotType=1 -Color=255 -MinDec=0 -MinVal=0. -MaxDec=0 -MaxVal=-1. -Mask=131072 -Offset=17 -[Signal 3] -DispName=Port1 -PlotType=1 -Color=32768 -MinDec=0 -MinVal=0. -MaxDec=0 -MaxVal=-1. -Mask=262144 -Offset=18 -[Signal 4] -DispName=Port1 -PlotType=1 -Color=16711680 -MinDec=0 -MinVal=0. -MaxDec=0 -MaxVal=-1. -Mask=524288 -Offset=19 diff --git a/Demo/ARM7_LPC2129_Keil/Startup.s b/Demo/ARM7_LPC2129_Keil/Startup.s deleted file mode 100644 index 769ed7890..000000000 --- a/Demo/ARM7_LPC2129_Keil/Startup.s +++ /dev/null @@ -1,379 +0,0 @@ -/***********************************************************************/ -/* This file is part of the uVision/ARM development tools */ -/* Copyright KEIL ELEKTRONIK GmbH 2002-2004 */ -/***********************************************************************/ -/* */ -/* STARTUP.S: Startup file for Philips LPC2000 device series */ -/* */ -/***********************************************************************/ - - -/* -//*** <<< Use Configuration Wizard in Context Menu >>> *** -*/ - - -// *** Startup Code (executed after Reset) *** - - -// Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs - - Mode_USR EQU 0x10 - Mode_FIQ EQU 0x11 - Mode_IRQ EQU 0x12 - Mode_SVC EQU 0x13 - Mode_ABT EQU 0x17 - Mode_UND EQU 0x1B - Mode_SYS EQU 0x1F - - I_Bit EQU 0x80 /* when I bit is set, IRQ is disabled */ - F_Bit EQU 0x40 /* when F bit is set, FIQ is disabled */ - - -/* -// Stack Configuration (Stack Sizes in Bytes) -// Undefined Mode <0x0-0xFFFFFFFF> -// Supervisor Mode <0x0-0xFFFFFFFF> -// Abort Mode <0x0-0xFFFFFFFF> -// Fast Interrupt Mode <0x0-0xFFFFFFFF> -// Interrupt Mode <0x0-0xFFFFFFFF> -// User/System Mode <0x0-0xFFFFFFFF> -// -*/ - UND_Stack_Size EQU 0x00000004 - SVC_Stack_Size EQU 0x00000100 - ABT_Stack_Size EQU 0x00000004 - FIQ_Stack_Size EQU 0x00000004 - IRQ_Stack_Size EQU 0x00000300 - USR_Stack_Size EQU 0x00000200 - -AREA STACK, DATA, READWRITE, ALIGN=2 - DS (USR_Stack_Size+3)&~3 ; Stack for User/System Mode - DS (IRQ_Stack_Size+3)&~3 ; Stack for Interrupt Mode - DS (FIQ_Stack_Size+3)&~3 ; Stack for Fast Interrupt Mode - DS (ABT_Stack_Size+3)&~3 ; Stack for Abort Mode - DS (SVC_Stack_Size+3)&~3 ; Stack for Supervisor Mode - DS (UND_Stack_Size+3)&~3 ; Stack for Undefined Mode -Top_Stack: - - -// Phase Locked Loop (PLL) definitions - PLL_BASE EQU 0xE01FC080 /* PLL Base Address */ - PLLCON_OFS EQU 0x00 /* PLL Control Offset*/ - PLLCFG_OFS EQU 0x04 /* PLL Configuration Offset */ - PLLSTAT_OFS EQU 0x08 /* PLL Status Offset */ - PLLFEED_OFS EQU 0x0C /* PLL Feed Offset */ - PLLCON_PLLE EQU (1<<0) /* PLL Enable */ - PLLCON_PLLC EQU (1<<1) /* PLL Connect */ - PLLCFG_MSEL EQU (0x1F<<0) /* PLL Multiplier */ - PLLCFG_PSEL EQU (0x03<<5) /* PLL Divider */ - PLLSTAT_PLOCK EQU (1<<10) /* PLL Lock Status */ - -/* -// PLL Setup -// Phase Locked Loop -// MSEL: PLL Multiplier Selection -// <1-32><#-1> -// M Value -// PSEL: PLL Divider Selection -// <0=> 1 <1=> 2 <2=> 4 <3=> 8 -// P Value -// -*/ - PLL_SETUP EQU 1 - PLLCFG_Val EQU 0x00000024 - - -// Memory Accelerator Module (MAM) definitions - MAM_BASE EQU 0xE01FC000 /* MAM Base Address */ - MAMCR_OFS EQU 0x00 /* MAM Control Offset*/ - MAMTIM_OFS EQU 0x04 /* MAM Timing Offset */ - -/* -// MAM Setup -// Memory Accelerator Module -// MAM Control -// <0=> Disabled -// <1=> Partially Enabled -// <2=> Fully Enabled -// Mode -// MAM Timing -// <0=> Reserved <1=> 1 <2=> 2 <3=> 3 -// <4=> 4 <5=> 5 <6=> 6 <7=> 7 -// Fetch Cycles -// -*/ - MAM_SETUP EQU 1 - MAMCR_Val EQU 0x00000002 - MAMTIM_Val EQU 0x00000003 - - -// External Memory Controller (EMC) definitions - EMC_BASE EQU 0xFFE00000 /* EMC Base Address */ - BCFG0_OFS EQU 0x00 /* BCFG0 Offset */ - BCFG1_OFS EQU 0x04 /* BCFG1 Offset */ - BCFG2_OFS EQU 0x08 /* BCFG2 Offset */ - BCFG3_OFS EQU 0x0C /* BCFG3 Offset */ - -/* -// External Memory Controller (EMC) -*/ - EMC_SETUP EQU 0 - -/* -// Bank Configuration 0 (BCFG0) -// IDCY: Idle Cycles <0-15> -// WST1: Wait States 1 <0-31> -// WST2: Wait States 2 <0-31> -// RBLE: Read Byte Lane Enable -// WP: Write Protect -// BM: Burst ROM -// MW: Memory Width <0=> 8-bit <1=> 16-bit -// <2=> 32-bit <3=> Reserved -// -*/ - BCFG0_SETUP EQU 0 - BCFG0_Val EQU 0x0000FBEF - -/* -// Bank Configuration 1 (BCFG1) -// IDCY: Idle Cycles <0-15> -// WST1: Wait States 1 <0-31> -// WST2: Wait States 2 <0-31> -// RBLE: Read Byte Lane Enable -// WP: Write Protect -// BM: Burst ROM -// MW: Memory Width <0=> 8-bit <1=> 16-bit -// <2=> 32-bit <3=> Reserved -// -*/ - BCFG1_SETUP EQU 0 - BCFG1_Val EQU 0x0000FBEF - -/* -// Bank Configuration 0 (BCFG2) -// IDCY: Idle Cycles <0-15> -// WST1: Wait States 1 <0-31> -// WST2: Wait States 2 <0-31> -// RBLE: Read Byte Lane Enable -// WP: Write Protect -// BM: Burst ROM -// MW: Memory Width <0=> 8-bit <1=> 16-bit -// <2=> 32-bit <3=> Reserved -// -*/ - BCFG2_SETUP EQU 0 - BCFG2_Val EQU 0x0000FBEF - -/* -// Bank Configuration 3 (BCFG3) -// IDCY: Idle Cycles <0-15> -// WST1: Wait States 1 <0-31> -// WST2: Wait States 2 <0-31> -// RBLE: Read Byte Lane Enable -// WP: Write Protect -// BM: Burst ROM -// MW: Memory Width <0=> 8-bit <1=> 16-bit -// <2=> 32-bit <3=> Reserved -// -*/ - BCFG3_SETUP EQU 0 - BCFG3_Val EQU 0x0000FBEF - -/* -// End of EMC -*/ - - -// External Memory Pins definitions - PINSEL2 EQU 0xE002C014 /* PINSEL2 Address */ - PINSEL2_Val EQU 0x0E6149E4 /* CS0..3, OE, WE, BLS0..3, - D0..31, A2..23, JTAG Pins */ - - -// Starupt Code must be linked first at Address at which it expects to run. - -$IF (EXTERNAL_MODE) - CODE_BASE EQU 0x80000000 -$ELSE - CODE_BASE EQU 0x00000000 -$ENDIF - -AREA STARTUPCODE, CODE, AT CODE_BASE // READONLY, ALIGN=4 - PUBLIC __startup - - EXTERN CODE32 (?C?INIT) - -__startup PROC CODE32 - -// Pre-defined interrupt handlers that may be directly -// overwritten by C interrupt functions -EXTERN CODE32 (Undef_Handler?A) -EXTERN CODE32 (vPortYieldProcessor?A) -EXTERN CODE32 (PAbt_Handler?A) -EXTERN CODE32 (DAbt_Handler?A) -EXTERN CODE32 (IRQ_Handler?A) -EXTERN CODE32 (FIQ_Handler?A) - -// Exception Vectors -// Mapped to Address 0. -// Absolute addressing mode must be used. - -Vectors: LDR PC,Reset_Addr - LDR PC,Undef_Addr - LDR PC,SWI_Addr - LDR PC,PAbt_Addr - LDR PC,DAbt_Addr - NOP /* Reserved Vector */ -; LDR PC,IRQ_Addr - LDR PC,[PC, #-0x0FF0] /* Vector from VicVectAddr */ - LDR PC,FIQ_Addr - -Reset_Addr: DD Reset_Handler -Undef_Addr: DD Undef_Handler?A -SWI_Addr: DD vPortYieldProcessor?A -PAbt_Addr: DD PAbt_Handler?A -DAbt_Addr: DD DAbt_Handler?A - DD 0 /* Reserved Address */ -IRQ_Addr: DD IRQ_Handler?A -FIQ_Addr: DD FIQ_Handler?A - - -// Reset Handler - -Reset_Handler: - - -$IF (EXTERNAL_MODE) - LDR R0, =PINSEL2 - LDR R1, =PINSEL2_Val - STR R1, [R0] -$ENDIF - - -IF (EMC_SETUP != 0) - LDR R0, =EMC_BASE - -IF (BCFG0_SETUP != 0) - LDR R1, =BCFG0_Val - STR R1, [R0, #BCFG0_OFS] -ENDIF - -IF (BCFG1_SETUP != 0) - LDR R1, =BCFG1_Val - STR R1, [R0, #BCFG1_OFS] -ENDIF - -IF (BCFG2_SETUP != 0) - LDR R1, =BCFG2_Val - STR R1, [R0, #BCFG2_OFS] -ENDIF - -IF (BCFG3_SETUP != 0) - LDR R1, =BCFG3_Val - STR R1, [R0, #BCFG3_OFS] -ENDIF - -ENDIF - - -IF (PLL_SETUP != 0) - LDR R0, =PLL_BASE - MOV R1, #0xAA - MOV R2, #0x55 - -// Configure and Enable PLL - MOV R3, #PLLCFG_Val - STR R3, [R0, #PLLCFG_OFS] - MOV R3, #PLLCON_PLLE - STR R3, [R0, #PLLCON_OFS] - STR R1, [R0, #PLLFEED_OFS] - STR R2, [R0, #PLLFEED_OFS] - -// Wait until PLL Locked -PLL_Loop: LDR R3, [R0, #PLLSTAT_OFS] - ANDS R3, R3, #PLLSTAT_PLOCK - BEQ PLL_Loop - -// Switch to PLL Clock - MOV R3, #(PLLCON_PLLE | PLLCON_PLLC) - STR R3, [R0, #PLLCON_OFS] - STR R1, [R0, #PLLFEED_OFS] - STR R2, [R0, #PLLFEED_OFS] -ENDIF - - -IF (MAM_SETUP != 0) - LDR R0, =MAM_BASE - MOV R1, #MAMTIM_Val - STR R1, [R0, #MAMTIM_OFS] - MOV R1, #MAMCR_Val - STR R1, [R0, #MAMCR_OFS] -ENDIF - - -// Memory Mapping (when Interrupt Vectors are in RAM) - MEMMAP EQU 0xE01FC040 /* Memory Mapping Control */ - -$IF (RAM_INTVEC) - LDR R0, =MEMMAP - MOV R1, #2 - STR R1, [R0] -$ENDIF - - -// Setup Stack for each mode - LDR R0, =Top_Stack - -// Enter Undefined Instruction Mode and set its Stack Pointer - MSR CPSR_c, #Mode_UND|I_Bit|F_Bit - MOV SP, R0 - SUB R0, R0, #UND_Stack_Size - -// Enter Abort Mode and set its Stack Pointer - MSR CPSR_c, #Mode_ABT|I_Bit|F_Bit - MOV SP, R0 - SUB R0, R0, #ABT_Stack_Size - -// Enter FIQ Mode and set its Stack Pointer - MSR CPSR_c, #Mode_FIQ|I_Bit|F_Bit - MOV SP, R0 - SUB R0, R0, #FIQ_Stack_Size - -// Enter IRQ Mode and set its Stack Pointer - MSR CPSR_c, #Mode_IRQ|I_Bit|F_Bit - MOV SP, R0 - SUB R0, R0, #IRQ_Stack_Size - -// Enter Supervisor Mode and set its Stack Pointer - MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit - MOV SP, R0 - SUB R0, R0, #SVC_Stack_Size - -// Enter S Mode and set its Stack Pointer - MSR CPSR_c, #Mode_SYS - MOV SP, R0 - -// Start in supervisor mode - MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit - -// Enter the C code - LDR R0,=?C?INIT - TST R0,#1 ; Bit-0 set: INIT is Thumb - LDREQ LR,=exit?A ; ARM Mode - LDRNE LR,=exit?T ; Thumb Mode - BX R0 - ENDP - -PUBLIC exit?A -exit?A PROC CODE32 - B exit?A - ENDP - -PUBLIC exit?T -exit?T PROC CODE16 -exit: B exit?T - ENDP - - - END diff --git a/Demo/ARM7_LPC2129_Keil/main.c b/Demo/ARM7_LPC2129_Keil/main.c deleted file mode 100644 index bc11bfd51..000000000 --- a/Demo/ARM7_LPC2129_Keil/main.c +++ /dev/null @@ -1,282 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. - The processor MUST be in supervisor mode when vTaskStartScheduler is - called. The demo applications included in the FreeRTOS.org download switch - to supervisor mode prior to main being called. If you are not using one of - these demo application projects then ensure Supervisor mode is used. -*/ - - -/* - * Creates all the demo application tasks, then starts the scheduler. The WEB - * documentation provides more details of the demo application tasks. - * - * Main.c also creates a task called "Check". This only executes every three - * seconds but has the highest priority so is guaranteed to get processor time. - * Its main function is to check that all the other tasks are still operational. - * Each task (other than the "flash" tasks) maintains a unique count that is - * incremented each time the task successfully completes its function. Should - * any error occur within such a task the count is permanently halted. The - * check task inspects the count of each task to ensure it has changed since - * the last time the check task executed. If all the count variables have - * changed all the tasks are still executing error free, and the check task - * toggles the onboard LED. Should any task contain an error at any time - * the LED toggle rate will change from 3 seconds to 500ms. - * - */ - -/* Standard includes. */ -#include - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Demo application includes. */ -#include "partest.h" -#include "flash.h" -#include "integer.h" -#include "comtest2.h" -#include "serial.h" - -#ifdef KEIL_THUMB_INTERWORK - /* - THUMB mode allows more tasks to be created without the executable - binary exceeding the limits allowed by the evaluation version of - uVision3. - */ - #include "PollQ.h" - #include "BlockQ.h" - #include "semtest.h" - #include "dynamic.h" - -#endif - -/*-----------------------------------------------------------*/ - -/* Constants to setup I/O and processor. */ -#define mainTX_ENABLE ( ( unsigned portLONG ) 0x0001 ) -#define mainRX_ENABLE ( ( unsigned portLONG ) 0x0004 ) -#define mainBUS_CLK_FULL ( ( unsigned portCHAR ) 0x01 ) -#define mainLED_TO_OUTPUT ( ( unsigned portLONG ) 0xff0000 ) - -/* Constants for the ComTest demo application tasks. */ -#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 115200 ) -#define mainCOM_TEST_LED ( 3 ) - -/* Priorities for the demo application tasks. */ -#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) - -/* Constants used by the "check" task. As described at the head of this file -the check task toggles an LED. The rate at which the LED flashes is used to -indicate whether an error has been detected or not. If the LED toggles every -3 seconds then no errors have been detected. If the rate increases to 500ms -then an error has been detected in at least one of the demo application tasks. */ -#define mainCHECK_LED ( 7 ) -#define mainNO_ERROR_FLASH_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS ) -#define mainERROR_FLASH_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS ) - -/*-----------------------------------------------------------*/ - -/* - * Checks that all the demo application tasks are still executing without error - * - as described at the top of the file. - */ -static portLONG prvCheckOtherTasksAreStillRunning( void ); - -/* - * The task that executes at the highest priority and calls - * prvCheckOtherTasksAreStillRunning(). See the description at the top - * of the file. - */ -static void vErrorChecks( void *pvParameters ); - -/* - * Configure the processor for use with the Keil demo board. This is very - * minimal as most of the setup is managed by the settings in the project - * file. - */ -static void prvSetupHardware( void ); - -/*-----------------------------------------------------------*/ - - - -/* - * Application entry point: - * Starts all the other tasks, then starts the scheduler. - */ -int main( void ) -{ - /* Setup the hardware for use with the Keil demo board. */ - prvSetupHardware(); - - /* Start the demo/test application tasks. */ - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); - vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); - - #ifdef KEIL_THUMB_INTERWORK - /* When using THUMB mode we can start more tasks without the executable - exceeding the size limit imposed by the evaluation version of uVision3. */ - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartDynamicPriorityTasks(); - #endif - - /* Start the check task - which is defined in this file. This is the task - that periodically checks to see that all the other tasks are executing - without error. */ - xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - - /* Now all the tasks have been started - start the scheduler. - - NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. - The processor MUST be in supervisor mode when vTaskStartScheduler is - called. The demo applications included in the FreeRTOS.org download switch - to supervisor mode prior to main being called. If you are not using one of - these demo application projects then ensure Supervisor mode is used here. */ - vTaskStartScheduler(); - - /* Should never reach here! */ - return 0; -} -/*-----------------------------------------------------------*/ - -static void vErrorChecks( void *pvParameters ) -{ -portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD; - - /* Parameters are not used. */ - ( void ) pvParameters; - - /* Cycle for ever, delaying then checking all the other tasks are still - operating without error. If an error is detected then the delay period - is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so - the on board LED flash rate will increase. - - This task runs at the highest priority. */ - - for( ;; ) - { - /* The period of the delay depends on whether an error has been - detected or not. If an error has been detected then the period - is reduced to increase the LED flash rate. */ - vTaskDelay( xDelayPeriod ); - - if( prvCheckOtherTasksAreStillRunning() != pdPASS ) - { - /* An error has been detected in one of the tasks - flash faster. */ - xDelayPeriod = mainERROR_FLASH_PERIOD; - } - - /* Toggle the LED before going back to wait for the next cycle. */ - vParTestToggleLED( mainCHECK_LED ); - } -} -/*-----------------------------------------------------------*/ - -static void prvSetupHardware( void ) -{ - /* Perform the hardware setup required. This is minimal as most of the - setup is managed by the settings in the project file. */ - - /* Configure the RS2332 pins. All other pins remain at their default of 0. */ - PINSEL0 |= mainTX_ENABLE; - PINSEL0 |= mainRX_ENABLE; - - /* LED pins need to be output. */ - IODIR1 = mainLED_TO_OUTPUT; - - /* Setup the peripheral bus to be the same as the PLL output. */ - VPBDIV = mainBUS_CLK_FULL; -} -/*-----------------------------------------------------------*/ - -static portLONG prvCheckOtherTasksAreStillRunning( void ) -{ -portLONG lReturn = pdPASS; - - /* Check all the demo tasks (other than the flash tasks) to ensure - that they are all still running, and that none of them have detected - an error. */ - if( xAreIntegerMathsTaskStillRunning() != pdPASS ) - { - lReturn = pdFAIL; - } - - if( xAreComTestTasksStillRunning() != pdPASS ) - { - lReturn = pdFAIL; - } - - #ifdef KEIL_THUMB_INTERWORK - - /* When using THUMB mode we can start more tasks without the executable - exceeding the size limit imposed by the evaluation version of uVision3. */ - - if( xArePollingQueuesStillRunning() != pdTRUE ) - { - lReturn = pdFAIL; - } - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - lReturn = pdFAIL; - } - - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - lReturn = pdFAIL; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - lReturn = pdFAIL; - } - - #endif - - return lReturn; -} -/*-----------------------------------------------------------*/ - - diff --git a/Demo/ARM7_LPC2129_Keil/rtosdemo_ARM.Opt b/Demo/ARM7_LPC2129_Keil/rtosdemo_ARM.Opt deleted file mode 100644 index 268345f18..000000000 --- a/Demo/ARM7_LPC2129_Keil/rtosdemo_ARM.Opt +++ /dev/null @@ -1,58 +0,0 @@ -### uVision2 Project, (C) Keil Software -### Do not modify ! - - cExt (*.c) - aExt (*.s*; *.src; *.a*) - oExt (*.obj) - lExt (*.lib) - tExt (*.txt; *.h; *.inc) - pExt (*.plm) - CppX (*.cpp) - DaveTm { 0,0,0,0,0,0,0,0 } - -Target (FreeRTOS), 0x0005 // Tools: '' -GRPOPT 1,(ARM_DEMO),1,0,0 - -OPTFFF 1,1,1,2,0,127,137,0,<.\main.c> { 44,0,0,0,2,0,0,0,3,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,228,255,255,255,27,0,0,0,27,0,0,0,41,4,0,0,102,2,0,0 } -OPTFFF 1,2,2,0,0,0,0,0,<.\Startup.s> -OPTFFF 1,3,1,0,0,0,0,0,<.\ParTest\ParTest.c> -OPTFFF 1,4,1,0,0,0,0,0,<.\serial\serial.c> -OPTFFF 1,5,1,0,0,0,0,0,<.\serial\serialISR.c> -OPTFFF 1,6,1,0,0,0,0,0,<..\..\Source\tasks.c> -OPTFFF 1,7,1,0,0,0,0,0,<..\..\Source\queue.c> -OPTFFF 1,8,1,0,0,0,0,0,<..\..\Source\list.c> -OPTFFF 1,9,1,0,0,0,0,0,<..\..\Source\portable\Keil\ARM7\port.c> -OPTFFF 1,10,1,0,0,0,0,0,<..\..\Source\portable\Keil\ARM7\portISR.c> -OPTFFF 1,11,1,0,0,0,0,0,<..\Common\Minimal\flash.c> -OPTFFF 1,12,1,16777216,0,0,0,0,<..\Common\Minimal\comtest.c> -OPTFFF 1,13,1,0,0,0,0,0,<..\Common\Minimal\integer.c> -OPTFFF 1,14,1,0,0,0,0,0,<..\..\Source\portable\MemMang\heap_2.c> - - -TARGOPT 1, (FreeRTOS) - KACLK=12000000 - OPTTT 1,1,1,0 - OPTHX 0,65535,0,0,0 - OPTLX 120,65,8,<.\> - OPTOX 16 - OPTLT 1,1,1,0,1,1,0,1,0,0,0,0 - OPTXL 1,1,1,1,1,1,1,0,0 - OPTFL 1,0,1 - OPTBL 0,(Data Sheet) - OPTBL 1,(User Manual) - OPTDL (SARM.DLL)(-cLPC2100)(DARMP.DLL)(-pLPC21x9)(SARM.DLL)()(TARMP.DLL)(-pLPC21x9) - OPTDBG 44029,-1,()()()()()()()()()() (BIN\UL2ARM.DLL)()()() - OPTKEY 0,(DLGTARM)((134=-1,-1,-1,-1,0)(135=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(108=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(80=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(112=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0)(117=-1,-1,-1,-1,0)(118=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(119=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(115=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0)) - OPTKEY 0,(UL2ARM)(-U174073036 -O7 -S0 -C0 -N00("ARM7TDMI-S Core") -D00(4F1F0F0F) -L00(4) -FO7 -FD40000000 -FC800 -FN1 -FF0LPC_IAP_256 -FS00 -FL03E000) - OPTKEY 0,(DLGDARM)((134=-1,-1,-1,-1,0)(135=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(108=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(80=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(112=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0)(117=-1,-1,-1,-1,0)(118=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(119=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(115=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0)) - OPTKEY 0,(ARMDBGFLAGS)(-T5F) - OPTMM 1,0,(0x40001800) - OPTDF 0x1000080 - OPTLE <> - OPTLC <> - OPTLA 0,((Port1 & 0x10000) >> 16)(FF00FF000000000000000000000000000000F0BF010000006400000000E8764817000000506F72743100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000020370000) - OPTLA 1,((Port1 & 0x20000) >> 17)(FF0000000000000000000000000000000000F0BF010000006400000000E8764817000000506F72743100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000020370000) - OPTLA 2,((Port1 & 0x40000) >> 18)(008000000000000000000000000000000000F0BF010000006400000000E8764817000000506F72743100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000020370000) - OPTLA 3,((Port1 & 0x80000) >> 19)(0000FF000000000000000000000000000000F0BF010000006400000000E8764817000000506F72743100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000020370000) -EndOpt - diff --git a/Demo/ARM7_LPC2129_Keil/rtosdemo_ARM.Uv2 b/Demo/ARM7_LPC2129_Keil/rtosdemo_ARM.Uv2 deleted file mode 100644 index 2b4655ff1..000000000 --- a/Demo/ARM7_LPC2129_Keil/rtosdemo_ARM.Uv2 +++ /dev/null @@ -1,106 +0,0 @@ -### uVision2 Project, (C) Keil Software -### Do not modify ! - -Target (FreeRTOS), 0x0005 // Tools: '' - -Group (ARM_DEMO) - -File 1,1,<.\main.c> 0x4162D96A -File 1,2,<.\Startup.s> 0x415AF382 -File 1,1,<.\ParTest\ParTest.c> 0x415AF50E -File 1,1,<.\serial\serial.c> 0x4162D488 -File 1,1,<.\serial\serialISR.c> 0x4162D404 -File 1,1,<..\..\Source\tasks.c> 0x4162D9E6 -File 1,1,<..\..\Source\queue.c> 0x411B5F14 -File 1,1,<..\..\Source\list.c> 0x411B5F24 -File 1,1,<..\..\Source\portable\Keil\ARM7\port.c> 0x4162D434 -File 1,1,<..\..\Source\portable\Keil\ARM7\portISR.c> 0x415A85E0 -File 1,1,<..\Common\Minimal\flash.c> 0x411B5F8E -File 1,1,<..\Common\Minimal\comtest.c> 0x413335E6 -File 1,1,<..\Common\Minimal\integer.c> 0x415FB7EE -File 1,1,<..\..\Source\portable\MemMang\heap_2.c> 0x0 - - -Options 1,0,0 // Target 'FreeRTOS' - Device (LPC2129) - Vendor (Philips) - Cpu (IRAM(0x40000000-0x40003FFF) IROM(0-0x3FFFF) CLOCK(12000000) CPUTYPE(ARM7TDMI)) - FlashUt (LPC210x_ISP.EXE ("#H" ^X $D COM1: 9600 1)) - StupF ("STARTUP\Philips\Startup.s" ("Philips LPC2100 Startup Code")) - FlashDR (UL2ARM(-U40296420 -O7 -C0 -FO7 -FD40000000 -FC800 -FN1 -FF0LPC_IAP_256 -FS00 -FL03E000)) - Rgf (LPC21xx.H) - Mem () - C () - A () - RL () - OH () - DBC_IFX () - DBC_CMS () - DBC_AMS () - DBC_LMS () - UseEnv=0 - EnvBin (D:\DevTools\Keil\arm\ARM\BIN\) - EnvInc () - EnvLib () - EnvReg (˙Philips\) - OrgReg (˙Philips\) - TgStat=16 - OutDir (.\) - OutName (rtosdemo_ARM) - GenApp=1 - GenLib=0 - GenHex=0 - Debug=1 - Browse=0 - LstDir (.\) - HexSel=0 - MG32K=0 - TGMORE=0 - RunUsr 0 0 <> - RunUsr 1 0 <> - BrunUsr 0 0 <> - BrunUsr 1 0 <> - SVCSID <> - KACPU (ARM7TDMI) - TKAFL { 0,27,183,0,0,15,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - KIROM { 1,0,0,0,0,0,0,4,0 } - KIRAM { 0,0,0,0,64,0,64,0,0 } - KXRAM { 0,0,0,0,0,0,0,0,0 } - KAOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - KCAFLG { 197,132,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - KCAMSC (INTERWORK) - KCADEF (KEIL_ARM7) - KCAUDF () - KCAINC (..\Common\include\;..\..\Source\include\;..\..\Source\portable\Keil\ARM7\) - KAAFLG { 20,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - KAAMSC () - KAASET () - KAARST () - KAAINC () - PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - IncBld=1 - AlwaysBuild=0 - GenAsm=0 - AsmAsm=0 - PublicsOnly=0 - StopCode=3 - CustArgs () - LibMods () - KLAFLG { 44,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - KLAMSC () - KLADWN (25) - KLACFI () - KLAASN () - KLARES () - KLACCL () - KLAUCL () - KLACSC () - KLAUCS () - OPTDL (SARM.DLL)(-cLPC2100)(DARMP.DLL)(-pLPC21x9)(SARM.DLL)()(TARMP.DLL)(-pLPC21x9) - OPTDBG 44029,-1,()()()()()()()()()() (BIN\UL2ARM.DLL)()()() - FLASH1 { 1,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - FLASH2 (BIN\UL2ARM.DLL) - FLASH3 ("LPC210x_ISP.EXE" ("#H" ^X $D COM1: 9600 1)) - FLASH4 () -EndOpt - diff --git a/Demo/ARM7_LPC2129_Keil/rtosdemo_THUMB.Opt b/Demo/ARM7_LPC2129_Keil/rtosdemo_THUMB.Opt deleted file mode 100644 index 39909fa34..000000000 --- a/Demo/ARM7_LPC2129_Keil/rtosdemo_THUMB.Opt +++ /dev/null @@ -1,63 +0,0 @@ -### uVision2 Project, (C) Keil Software -### Do not modify ! - - cExt (*.c) - aExt (*.s*; *.src; *.a*) - oExt (*.obj) - lExt (*.lib) - tExt (*.txt; *.h; *.inc) - pExt (*.plm) - CppX (*.cpp) - DaveTm { 0,0,0,0,0,0,0,0 } - -Target (FreeRTOS), 0x0005 // Tools: '' -GRPOPT 1,(THUMB_DEMO),1,0,0 - -OPTFFF 1,1,1,1,0,121,137,0,<.\main.c> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,228,255,255,255,0,0,0,0,0,0,0,0,14,4,0,0,75,2,0,0 } -OPTFFF 1,2,2,0,0,0,0,0,<.\Startup.s> -OPTFFF 1,3,1,1040187392,0,0,0,0,<.\ParTest\ParTest.c> -OPTFFF 1,4,1,0,0,0,0,0,<.\serial\serial.c> -OPTFFF 1,5,1,0,0,0,0,0,<.\serial\serialISR.c> -OPTFFF 1,6,1,0,0,0,0,0,<..\..\Source\tasks.c> -OPTFFF 1,7,1,0,0,0,0,0,<..\..\Source\queue.c> -OPTFFF 1,8,1,0,0,0,0,0,<..\..\Source\list.c> -OPTFFF 1,9,1,553648128,0,0,0,0,<..\..\Source\portable\Keil\ARM7\port.c> -OPTFFF 1,10,1,0,0,0,0,0,<..\..\Source\portable\Keil\ARM7\portISR.c> -OPTFFF 1,11,1,0,0,0,0,0,<..\Common\Minimal\BlockQ.c> -OPTFFF 1,12,1,402653184,0,0,0,0,<..\Common\Minimal\semtest.c> -OPTFFF 1,13,1,0,0,0,0,0,<..\Common\Minimal\PollQ.c> -OPTFFF 1,14,1,0,0,0,0,0,<..\Common\Minimal\flash.c> -OPTFFF 1,15,1,0,0,0,0,0,<..\Common\Minimal\comtest.c> -OPTFFF 1,16,1,0,0,0,0,0,<..\Common\Minimal\integer.c> -OPTFFF 1,17,1,0,0,0,0,0,<..\..\Source\portable\MemMang\heap_2.c> -OPTFFF 1,18,1,0,0,0,0,0,<..\Common\Minimal\dynamic.c> - -ExtF <..\..\SOURCE\PORTABLE\KEIL\ARM7\PORTMACRO.H> 127,127,0,{ 44,0,0,0,2,0,0,0,3,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,228,255,255,255,27,0,0,0,27,0,0,0,72,4,0,0,33,2,0,0 } - -TARGOPT 1, (FreeRTOS) - KACLK=12000000 - OPTTT 1,1,1,0 - OPTHX 0,65535,0,0,0 - OPTLX 120,65,8,<.\> - OPTOX 16 - OPTLT 1,1,1,0,1,1,0,1,0,0,0,0 - OPTXL 1,1,1,1,1,1,1,0,0 - OPTFL 1,0,1 - OPTBL 0,(Data Sheet) - OPTBL 1,(User Manual) - OPTDL (SARM.DLL)(-cLPC2100)(DARMP.DLL)(-pLPC21x9)(SARM.DLL)()(TARMP.DLL)(-pLPC21x9) - OPTDBG 44029,-1,()()()()()()()()()() (BIN\UL2ARM.DLL)()()() - OPTKEY 0,(DLGTARM)((134=-1,-1,-1,-1,0)(135=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(108=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(80=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(112=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0)(117=-1,-1,-1,-1,0)(118=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(119=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(115=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0)) - OPTKEY 0,(UL2ARM)(-U170927308 -O7 -S0 -C0 -N00("ARM7TDMI-S Core") -D00(4F1F0F0F) -L00(4) -FO7 -FD40000000 -FC800 -FN1 -FF0LPC_IAP_256 -FS00 -FL03E000) - OPTKEY 0,(DLGDARM)((134=-1,-1,-1,-1,0)(135=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(108=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(80=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(112=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0)(117=-1,-1,-1,-1,0)(118=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(119=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(115=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0)) - OPTKEY 0,(ARMDBGFLAGS)(-T5F) - OPTMM 1,0,(0x40000840) - OPTDF 0x1000086 - OPTLE <> - OPTLC <> - OPTLA 0,((Port1 & 0x10000) >> 16)(0000FF000000000000000000000000000000F0BF010000006400000000743BA40B000000506F7274310000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000001C030000) - OPTLA 1,((Port1 & 0x20000) >> 17)(0000FF000000000000000000000000000000F0BF010000006400000000743BA40B000000506F7274310000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000001C030000) - OPTLA 2,((Port1 & 0x40000) >> 18)(0000FF000000000000000000000000000000F0BF010000006400000000743BA40B000000506F7274310000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000001C030000) - OPTLA 3,((Port1 & 0x80000) >> 19)(0000FF000000000000000000000000000000F0BF010000006400000000743BA40B000000506F7274310000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000001C030000) -EndOpt - diff --git a/Demo/ARM7_LPC2129_Keil/rtosdemo_THUMB.Uv2 b/Demo/ARM7_LPC2129_Keil/rtosdemo_THUMB.Uv2 deleted file mode 100644 index 8e6cb20e7..000000000 --- a/Demo/ARM7_LPC2129_Keil/rtosdemo_THUMB.Uv2 +++ /dev/null @@ -1,110 +0,0 @@ -### uVision2 Project, (C) Keil Software -### Do not modify ! - -Target (FreeRTOS), 0x0005 // Tools: '' - -Group (THUMB_DEMO) - -File 1,1,<.\main.c> 0x4162D96A -File 1,2,<.\Startup.s> 0x415AF382 -File 1,1,<.\ParTest\ParTest.c> 0x415AF50E -File 1,1,<.\serial\serial.c> 0x4162D488 -File 1,1,<.\serial\serialISR.c> 0x4162D404 -File 1,1,<..\..\Source\tasks.c> 0x4162D9E6 -File 1,1,<..\..\Source\queue.c> 0x411B5F14 -File 1,1,<..\..\Source\list.c> 0x411B5F24 -File 1,1,<..\..\Source\portable\Keil\ARM7\port.c> 0x4162D434 -File 1,1,<..\..\Source\portable\Keil\ARM7\portISR.c> 0x415A85E0 -File 1,1,<..\Common\Minimal\BlockQ.c> 0x411B5F8C -File 1,1,<..\Common\Minimal\semtest.c> 0x411B5F8C -File 1,1,<..\Common\Minimal\PollQ.c> 0x411B5F8E -File 1,1,<..\Common\Minimal\flash.c> 0x411B5F8E -File 1,1,<..\Common\Minimal\comtest.c> 0x413335E6 -File 1,1,<..\Common\Minimal\integer.c> 0x415FB7EE -File 1,1,<..\..\Source\portable\MemMang\heap_2.c> 0x0 -File 1,1,<..\Common\Minimal\dynamic.c> 0x0 - - -Options 1,0,0 // Target 'FreeRTOS' - Device (LPC2129) - Vendor (Philips) - Cpu (IRAM(0x40000000-0x40003FFF) IROM(0-0x3FFFF) CLOCK(12000000) CPUTYPE(ARM7TDMI)) - FlashUt (LPC210x_ISP.EXE ("#H" ^X $D COM1: 9600 1)) - StupF ("STARTUP\Philips\Startup.s" ("Philips LPC2100 Startup Code")) - FlashDR (UL2ARM(-U40296420 -O7 -C0 -FO7 -FD40000000 -FC800 -FN1 -FF0LPC_IAP_256 -FS00 -FL03E000)) - Rgf (LPC21xx.H) - Mem () - C () - A () - RL () - OH () - DBC_IFX () - DBC_CMS () - DBC_AMS () - DBC_LMS () - UseEnv=0 - EnvBin (D:\DevTools\Keil\arm\ARM\BIN\) - EnvInc () - EnvLib () - EnvReg (˙Philips\) - OrgReg (˙Philips\) - TgStat=16 - OutDir (.\) - OutName (rtosdemo_THUMB) - GenApp=1 - GenLib=0 - GenHex=0 - Debug=1 - Browse=0 - LstDir (.\) - HexSel=0 - MG32K=0 - TGMORE=0 - RunUsr 0 0 <> - RunUsr 1 0 <> - BrunUsr 0 0 <> - BrunUsr 1 0 <> - SVCSID <> - KACPU (ARM7TDMI) - TKAFL { 0,27,183,0,0,15,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - KIROM { 1,0,0,0,0,0,0,4,0 } - KIRAM { 0,0,0,0,64,0,64,0,0 } - KXRAM { 0,0,0,0,0,0,0,0,0 } - KAOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - KCAFLG { 197,156,20,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - KCAMSC (INTERWORK) - KCADEF (KEIL_ARM7 KEIL_THUMB_INTERWORK) - KCAUDF () - KCAINC (..\Common\include\;..\..\Source\include\;..\..\Source\portable\Keil\ARM7\) - KAAFLG { 20,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - KAAMSC () - KAASET () - KAARST () - KAAINC () - PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - IncBld=1 - AlwaysBuild=0 - GenAsm=0 - AsmAsm=0 - PublicsOnly=0 - StopCode=3 - CustArgs () - LibMods () - KLAFLG { 44,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - KLAMSC () - KLADWN (25) - KLACFI () - KLAASN () - KLARES () - KLACCL () - KLAUCL () - KLACSC () - KLAUCS () - OPTDL (SARM.DLL)(-cLPC2100)(DARMP.DLL)(-pLPC21x9)(SARM.DLL)()(TARMP.DLL)(-pLPC21x9) - OPTDBG 44029,-1,()()()()()()()()()() (BIN\UL2ARM.DLL)()()() - FLASH1 { 1,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - FLASH2 (BIN\UL2ARM.DLL) - FLASH3 ("LPC210x_ISP.EXE" ("#H" ^X $D COM1: 9600 1)) - FLASH4 () -EndOpt - diff --git a/Demo/ARM7_LPC2129_Keil/serial/serial.c b/Demo/ARM7_LPC2129_Keil/serial/serial.c deleted file mode 100644 index 93be94c41..000000000 --- a/Demo/ARM7_LPC2129_Keil/serial/serial.c +++ /dev/null @@ -1,247 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/* - BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0. - - This file contains all the serial port components that can be compiled to - either ARM or THUMB mode. Components that must be compiled to ARM mode are - contained in serialISR.c. -*/ - -/* Standard includes. */ -#include - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "queue.h" -#include "task.h" - -/* Demo application includes. */ -#include "serial.h" - -/*-----------------------------------------------------------*/ - -/* Constants to setup and access the UART. */ -#define serDLAB ( ( unsigned portCHAR ) 0x80 ) -#define serENABLE_INTERRUPTS ( ( unsigned portCHAR ) 0x03 ) -#define serNO_PARITY ( ( unsigned portCHAR ) 0x00 ) -#define ser1_STOP_BIT ( ( unsigned portCHAR ) 0x00 ) -#define ser8_BIT_CHARS ( ( unsigned portCHAR ) 0x03 ) -#define serFIFO_ON ( ( unsigned portCHAR ) 0x01 ) -#define serCLEAR_FIFO ( ( unsigned portCHAR ) 0x06 ) -#define serWANTED_CLOCK_SCALING ( ( unsigned portLONG ) 16 ) - -/* Constants to setup and access the VIC. */ -#define serU0VIC_CHANNEL ( ( unsigned portLONG ) 0x0006 ) -#define serU0VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x0040 ) -#define serU0VIC_ENABLE ( ( unsigned portLONG ) 0x0020 ) - -/* Misc. */ -#define serINVALID_QUEUE ( ( xQueueHandle ) 0 ) -#define serHANDLE ( ( xComPortHandle ) 1 ) -#define serNO_BLOCK ( ( portTickType ) 0 ) - -/*-----------------------------------------------------------*/ - -/* Queues used to hold received characters, and characters waiting to be -transmitted. */ -static xQueueHandle xRxedChars; -static xQueueHandle xCharsForTx; - -/*-----------------------------------------------------------*/ - -/* Communication flag between the interrupt service routine and serial API. */ -static volatile portLONG *plTHREEmpty; - -/* - * The queues are created in serialISR.c as they are used from the ISR. - * Obtain references to the queues and THRE Empty flag. - */ -extern void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, xQueueHandle *pxCharsForTx, portLONG volatile **pplTHREEmptyFlag ); - -/*-----------------------------------------------------------*/ - -xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) -{ -unsigned portLONG ulDivisor, ulWantedClock; -xComPortHandle xReturn = serHANDLE; - - /* The queues are used in the serial ISR routine, so are created from - serialISR.c (which is always compiled to ARM mode). */ - vSerialISRCreateQueues( uxQueueLength, &xRxedChars, &xCharsForTx, &plTHREEmpty ); - - if( - ( xRxedChars != serINVALID_QUEUE ) && - ( xCharsForTx != serINVALID_QUEUE ) && - ( ulWantedBaud != ( unsigned portLONG ) 0 ) - ) - { - portENTER_CRITICAL(); - { - /* The reference to the ISR function is required to load into the - interrupt controller. The prototype is slightly different - depending on whether in ARM or THUMB mode. */ - #ifdef KEIL_THUMB_INTERWORK - extern void ( vUART_ISR )( void ) __arm __task; - #else - extern void ( vUART_ISR )( void ) __task; - #endif - - /* Setup the baud rate: Calculate the divisor value. */ - ulWantedClock = ulWantedBaud * serWANTED_CLOCK_SCALING; - ulDivisor = configCPU_CLOCK_HZ / ulWantedClock; - - /* Set the DLAB bit so we can access the divisor. */ - U0LCR |= serDLAB; - - /* Setup the divisor. */ - U0DLL = ( unsigned portCHAR ) ( ulDivisor & ( unsigned portLONG ) 0xff ); - ulDivisor >>= 8; - U0DLM = ( unsigned portCHAR ) ( ulDivisor & ( unsigned portLONG ) 0xff ); - - /* Turn on the FIFO's and clear the buffers. */ - U0FCR = ( serFIFO_ON | serCLEAR_FIFO ); - - /* Setup transmission format. */ - U0LCR = serNO_PARITY | ser1_STOP_BIT | ser8_BIT_CHARS; - - /* Setup the VIC for the UART. */ - VICIntSelect &= ~( serU0VIC_CHANNEL_BIT ); - VICIntEnable |= serU0VIC_CHANNEL_BIT; - VICVectAddr1 = ( unsigned portLONG ) vUART_ISR; - VICVectCntl1 = serU0VIC_CHANNEL | serU0VIC_ENABLE; - - /* Enable UART0 interrupts. */ - U0IER |= serENABLE_INTERRUPTS; - } - portEXIT_CRITICAL(); - } - else - { - xReturn = ( xComPortHandle ) 0; - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) -{ - /* The port handle is not required as this driver only supports UART0. */ - ( void ) pxPort; - - /* Get the next character from the buffer. Return false if no characters - are available, or arrive before xBlockTime expires. */ - if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) - { - return pdTRUE; - } - else - { - return pdFALSE; - } -} -/*-----------------------------------------------------------*/ - -void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength ) -{ -signed portCHAR *pxNext; - - /* NOTE: This implementation does not handle the queue being full as no - block time is used! */ - - /* The port handle is not required as this driver only supports UART0. */ - ( void ) pxPort; - ( void ) usStringLength; - - /* Send each character in the string, one at a time. */ - pxNext = ( signed portCHAR * ) pcString; - while( *pxNext ) - { - xSerialPutChar( pxPort, *pxNext, serNO_BLOCK ); - pxNext++; - } -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) -{ -signed portBASE_TYPE xReturn; - - /* The port handle is not required as this driver only supports UART0. */ - ( void ) pxPort; - - portENTER_CRITICAL(); - { - /* Is there space to write directly to the UART? */ - if( *plTHREEmpty == ( portLONG ) pdTRUE ) - { - /* We wrote the character directly to the UART, so was - successful. */ - *plTHREEmpty = pdFALSE; - U0THR = cOutChar; - xReturn = pdPASS; - } - else - { - /* We cannot write directly to the UART, so queue the character. - Block for a maximum of xBlockTime if there is no space in the - queue. It is ok to block within a critical section as each - task has it's own critical section management. */ - xReturn = xQueueSend( xCharsForTx, &cOutChar, xBlockTime ); - - /* Depending on queue sizing and task prioritisation: While we - were blocked waiting to post interrupts were not disabled. It is - possible that the serial ISR has emptied the Tx queue, in which - case we need to start the Tx off again. */ - if( *plTHREEmpty == ( portLONG ) pdTRUE ) - { - xQueueReceive( xCharsForTx, &cOutChar, serNO_BLOCK ); - *plTHREEmpty = pdFALSE; - U0THR = cOutChar; - } - } - } - portEXIT_CRITICAL(); - - return xReturn; -} -/*-----------------------------------------------------------*/ - - - - - - - diff --git a/Demo/ARM7_LPC2129_Keil/serial/serialISR.c b/Demo/ARM7_LPC2129_Keil/serial/serialISR.c deleted file mode 100644 index 8816a127d..000000000 --- a/Demo/ARM7_LPC2129_Keil/serial/serialISR.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/* - BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0. - - This file contains all the serial port components that must be compiled - to ARM mode. The components that can be compiled to either ARM or THUMB - mode are contained in serial.c. -*/ - -/* This file must always be compiled to ARM mode as it contains ISR -definitions. */ -#pragma ARM - -/* Standard includes. */ -#include - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "queue.h" -#include "task.h" - -/* Demo application includes. */ -#include "serial.h" - -/*-----------------------------------------------------------*/ - -/* Constant to access the VIC. */ -#define serCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 ) - -/* Constants to determine the ISR source. */ -#define serSOURCE_THRE ( ( unsigned portCHAR ) 0x02 ) -#define serSOURCE_RX_TIMEOUT ( ( unsigned portCHAR ) 0x0c ) -#define serSOURCE_ERROR ( ( unsigned portCHAR ) 0x06 ) -#define serSOURCE_RX ( ( unsigned portCHAR ) 0x04 ) -#define serINTERRUPT_SOURCE_MASK ( ( unsigned portCHAR ) 0x0f ) - -/* Queues used to hold received characters, and characters waiting to be -transmitted. */ -static xQueueHandle xRxedChars; -static xQueueHandle xCharsForTx; -static volatile portLONG lTHREEmpty; - -/*-----------------------------------------------------------*/ - -/* UART0 interrupt service routine. This can cause a context switch so MUST -be declared "naked". */ -void vUART_ISR( void ); - -/*-----------------------------------------------------------*/ -void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, - xQueueHandle *pxCharsForTx, portLONG volatile **pplTHREEmptyFlag ) -{ - /* Create the queues used to hold Rx and Tx characters. */ - xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); - xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); - - /* Pass back a reference to the queues so the serial API file can - post/receive characters. */ - *pxRxedChars = xRxedChars; - *pxCharsForTx = xCharsForTx; - - /* Initialise the THRE empty flag - and pass back a reference. */ - lTHREEmpty = pdTRUE; - *pplTHREEmptyFlag = &lTHREEmpty; -} -/*-----------------------------------------------------------*/ - -void vUART_ISR( void ) __task -{ - portENTER_SWITCHING_ISR() - - /* Now we can declare the local variables. */ - static signed portCHAR cChar; - static portBASE_TYPE xTaskWokenByRx, xTaskWokenByTx; - - xTaskWokenByTx = pdFALSE; - xTaskWokenByRx = pdFALSE; - - /* What caused the interrupt? */ - switch( U0IIR & serINTERRUPT_SOURCE_MASK ) - { - case serSOURCE_ERROR : /* Not handling this, but clear the interrupt. */ - cChar = U0LSR; - break; - - case serSOURCE_THRE : /* The THRE is empty. If there is another - character in the Tx queue, send it now. */ - if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE ) - { - U0THR = cChar; - } - else - { - /* There are no further characters - queued to send so we can indicate - that the THRE is available. */ - lTHREEmpty = pdTRUE; - } - break; - - case serSOURCE_RX_TIMEOUT : - case serSOURCE_RX : /* A character was received. Place it in - the queue of received characters. */ - cChar = U0RBR; - if( xQueueSendFromISR( xRxedChars, &cChar, pdFALSE ) ) - { - xTaskWokenByRx = pdTRUE; - } - break; - - default : /* There is nothing to do, leave the ISR. */ - break; - } - - /* Clear the ISR in the VIC. */ - VICVectAddr = serCLEAR_VIC_INTERRUPT; - - /* Exit the ISR. If a task was woken by either a character being received - or transmitted then a context switch will occur. */ - portEXIT_SWITCHING_ISR( ( xTaskWokenByTx || xTaskWokenByRx ) ); -} -/*-----------------------------------------------------------*/ - - - - - - diff --git a/Demo/ARM7_LPC2138_Rowley/FreeRTOSConfig.h b/Demo/ARM7_LPC2138_Rowley/FreeRTOSConfig.h deleted file mode 100644 index 8c887eb61..000000000 --- a/Demo/ARM7_LPC2138_Rowley/FreeRTOSConfig.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -#include -#define vPortYieldProcessor swi_handler - -/* For compatability with the LPC2106 header. */ -#define T0_IR T0IR -#define T0_PR T0PR -#define T0_MR0 T0MR0 -#define T0_MCR T0MCR -#define T0_TCR T0TCR - - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -/* In this case configCPU_CLOCK_HZ is actually set to the pclk frequency, not -the CPU frequency. */ -#define configCPU_CLOCK_HZ ( 58982400UL ) /* =14.7456MHz xtal multiplied by 4 using the PLL. */ -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 6 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 18 * 1024 ) ) -#define configMAX_TASK_NAME_LEN ( 15 ) -#define configUSE_TRACE_FACILITY 1 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 1 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/ARM7_LPC2138_Rowley/RTOSDemo.hzp b/Demo/ARM7_LPC2138_Rowley/RTOSDemo.hzp deleted file mode 100644 index 92c2bdc0f..000000000 --- a/Demo/ARM7_LPC2138_Rowley/RTOSDemo.hzp +++ /dev/null @@ -1,55 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Demo/ARM7_LPC2138_Rowley/RTOSDemo.hzs b/Demo/ARM7_LPC2138_Rowley/RTOSDemo.hzs deleted file mode 100644 index 0d0ff0a1d..000000000 --- a/Demo/ARM7_LPC2138_Rowley/RTOSDemo.hzs +++ /dev/null @@ -1,74 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Demo/ARM7_LPC2138_Rowley/main.c b/Demo/ARM7_LPC2138_Rowley/main.c deleted file mode 100644 index 058eac1cd..000000000 --- a/Demo/ARM7_LPC2138_Rowley/main.c +++ /dev/null @@ -1,330 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * This file contains a demo created to execute on the Rowley Associates - * LPC2138 CrossFire development board. - * - * main() creates all the demo application tasks, then starts the scheduler. - * The WEB documentation provides more details of the standard demo application - * tasks. - * - * Main.c also creates a task called "Check". This only executes every few - * seconds but has a high priority so is guaranteed to get processor time. - * Its function is to check that all the other tasks are still operational. - * Each standard demo task maintains a unique count that is incremented each - * time the task successfully completes its function. Should any error occur - * within such a task the count is permanently halted. The check task inspects - * the count of each task to ensure it has changed since the last time the - * check task executed. If all the count variables have changed all the tasks - * are still executing error free, and the check task writes "PASS" to the - * CrossStudio terminal IO window. Should any task contain an error at any time - * the error is latched and "FAIL" written to the terminal IO window. - * - * Finally, main() sets up an interrupt service routine and task to handle - * pushes of the button that is built into the CrossFire board. When the button - * is pushed the ISR wakes the button task - which generates a table of task - * status information which is also displayed on the terminal IO window. - * - * A print task is defined to ensure exclusive and consistent access to the - * terminal IO. This is the only task that is allowed to access the terminal. - * The check and button task therefore do not access the terminal directly but - * instead pass a pointer to the message they wish to display to the print task. - */ - -/* Standard includes. */ -#include <__cross_studio_io.h> - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "Task.h" -#include "queue.h" -#include "semphr.h" - -/* Demo app includes. */ -#include "BlockQ.h" -#include "death.h" -#include "dynamic.h" -#include "integer.h" -#include "PollQ.h" -#include "blocktim.h" - -/* Hardware configuration definitions. */ -#define mainBUS_CLK_FULL ( ( unsigned portCHAR ) 0x01 ) -#define mainLED_BIT 0x80000000 -#define mainP0_14__EINT_1 ( 2 << 28 ) -#define mainEINT_1_EDGE_SENSITIVE 2 -#define mainEINT_1_FALLING_EDGE_SENSITIVE 0 -#define mainEINT_1_CHANNEL 15 -#define mainEINT_1_VIC_CHANNEL_BIT ( 1 << mainEINT_1_CHANNEL ) -#define mainEINT_1_ENABLE_BIT ( 1 << 5 ) - -/* Demo application definitions. */ -#define mainQUEUE_SIZE ( 3 ) -#define mainLED_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS ) -#define mainCHECK_DELAY ( ( portTickType ) 5000 / portTICK_RATE_MS ) -#define mainLIST_BUFFER_SIZE 2048 - -/* Task priorities. */ -#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainPRINT_TASK_PRIORITY ( tskIDLE_PRIORITY + 0 ) - -/*-----------------------------------------------------------*/ - -/* The semaphore used to wake the button task from within the external interrupt -handler. */ -xSemaphoreHandle xButtonSemaphore; - -/* The queue that is used to send message to vPrintTask for display in the -terminal output window. */ -xQueueHandle xPrintQueue; - -/*-----------------------------------------------------------*/ - -/* - * Simply flashes the on board LED every mainLED_DELAY milliseconds. - */ -static void vLEDTask( void *pvParameters ); - -/* - * Checks the status of all the demo tasks then prints a message to the - * CrossStudio terminal IO windows. The message will be either PASS or FAIL - * depending on the status of the demo applications tasks. A FAIL status will - * be latched. - * - * Messages are not written directly to the terminal, but passed to vPrintTask - * via a queue. - */ -static void vCheckTask( void *pvParameters ); - -/* - * Controls all terminal output. If a task wants to send a message to the - * terminal IO it posts a pointer to the text to vPrintTask via a queue. This - * ensures serial access to the terminal IO. - */ -static void vPrintTask( void *pvParameter ); - -/* - * Simply waits for an interrupt to be generated from the built in button, then - * generates a table of tasks states that is then written by vPrintTask to the - * terminal output window within CrossStudio. - */ -static void vButtonHandlerTask( void *pvParameters ); - -/*-----------------------------------------------------------*/ - -int main( void ) -{ - /* Setup the peripheral bus to be the same as the PLL output. */ - VPBDIV = mainBUS_CLK_FULL; - - /* Create the queue used to pass message to vPrintTask. */ - xPrintQueue = xQueueCreate( mainQUEUE_SIZE, sizeof( portCHAR * ) ); - - /* Create the semaphore used to wake vButtonHandlerTask(). */ - vSemaphoreCreateBinary( xButtonSemaphore ); - xSemaphoreTake( xButtonSemaphore, 0 ); - - /* Start the standard demo tasks. */ - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartDynamicPriorityTasks(); - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - vCreateBlockTimeTasks(); - - /* Start the tasks defined within this file. */ - xTaskCreate( vLEDTask, "LED", configMINIMAL_STACK_SIZE, NULL, mainLED_TASK_PRIORITY, NULL ); - xTaskCreate( vCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - xTaskCreate( vPrintTask, "Print", configMINIMAL_STACK_SIZE, NULL, mainPRINT_TASK_PRIORITY, NULL ); - xTaskCreate( vButtonHandlerTask, "Button", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - - /* Start the scheduler. */ - vTaskStartScheduler(); - - /* The scheduler should now running, so we will only ever reach here if we - ran out of heap space. */ - - return 0; -} -/*-----------------------------------------------------------*/ - -static void vLEDTask( void *pvParameters ) -{ - /* Configure IO. */ - IO0DIR |= mainLED_BIT; - IO0SET = mainLED_BIT; - - for( ;; ) - { - /* Not very exiting - just delay... */ - vTaskDelay( mainLED_DELAY ); - - /* ...set the IO ... */ - IO0CLR = mainLED_BIT; - - /* ...delay again... */ - vTaskDelay( mainLED_DELAY ); - - /* ...then clear the IO. */ - IO0SET = mainLED_BIT; - } -} -/*-----------------------------------------------------------*/ - -static void vCheckTask( void *pvParameters ) -{ -portBASE_TYPE xErrorOccurred = pdFALSE; -portTickType xLastExecutionTime; -const portCHAR * const pcPassMessage = "PASS\n"; -const portCHAR * const pcFailMessage = "FAIL\n"; - - /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() - works correctly. */ - xLastExecutionTime = xTaskGetTickCount(); - - for( ;; ) - { - /* Perform this check every mainCHECK_DELAY milliseconds. */ - vTaskDelayUntil( &xLastExecutionTime, mainCHECK_DELAY ); - - /* Has an error been found in any task? */ - - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - xErrorOccurred = pdTRUE; - } - - if( xArePollingQueuesStillRunning() != pdTRUE ) - { - xErrorOccurred = pdTRUE; - } - - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - xErrorOccurred = pdTRUE; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - xErrorOccurred = pdTRUE; - } - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - xErrorOccurred = pdTRUE; - } - - if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) - { - xErrorOccurred = pdTRUE; - } - - /* Send either a pass or fail message. If an error is found it is - never cleared again. */ - if( xErrorOccurred == pdTRUE ) - { - xQueueSend( xPrintQueue, &pcFailMessage, portMAX_DELAY ); - } - else - { - xQueueSend( xPrintQueue, &pcPassMessage, portMAX_DELAY ); - } - } -} -/*-----------------------------------------------------------*/ - -static void vPrintTask( void *pvParameters ) -{ -portCHAR *pcMessage; - - for( ;; ) - { - /* Wait for a message to arrive. */ - while( xQueueReceive( xPrintQueue, &pcMessage, portMAX_DELAY ) != pdPASS ); - - /* Write the message to the terminal IO. */ - debug_printf( "%s", pcMessage ); - } -} -/*-----------------------------------------------------------*/ - -static void vButtonHandlerTask( void *pvParameters ) -{ -static portCHAR cListBuffer[ mainLIST_BUFFER_SIZE ]; -const portCHAR *pcList = &( cListBuffer[ 0 ] ); -const portCHAR * const pcHeader = "\nTask State Priority Stack #\n************************************************"; -extern void (vButtonISR) ( void ); - - /* Configure the interrupt. */ - portENTER_CRITICAL(); - { - /* Configure P0.14 to generate interrupts. */ - PINSEL0 |= mainP0_14__EINT_1; - EXTMODE = mainEINT_1_EDGE_SENSITIVE; - EXTPOLAR = mainEINT_1_FALLING_EDGE_SENSITIVE; - - /* Setup the VIC for EINT 1. */ - VICIntSelect &= ~mainEINT_1_VIC_CHANNEL_BIT; - VICIntEnable |= mainEINT_1_VIC_CHANNEL_BIT; - VICVectAddr1 = ( portLONG ) vButtonISR; - VICVectCntl1 = mainEINT_1_ENABLE_BIT | mainEINT_1_CHANNEL; - } - portEXIT_CRITICAL(); - - for( ;; ) - { - /* Wait for an interrupt. */ - while( xSemaphoreTake( xButtonSemaphore, portMAX_DELAY ) != pdPASS ); - - /* Send the column headers to the print task for display. */ - xQueueSend( xPrintQueue, &pcHeader, portMAX_DELAY ); - - /* Create the list of task states. */ - vTaskList( cListBuffer ); - - /* Send the task status information to the print task for display. */ - xQueueSend( xPrintQueue, &pcList, portMAX_DELAY ); - } -} -/*-----------------------------------------------------------*/ - - - - - - - diff --git a/Demo/ARM7_LPC2138_Rowley/mainISR.c b/Demo/ARM7_LPC2138_Rowley/mainISR.c deleted file mode 100644 index 40fa11672..000000000 --- a/Demo/ARM7_LPC2138_Rowley/mainISR.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ -#include "FreeRTOS.h" -#include "semphr.h" - -#define isrCLEAR_EINT_1 2 - -/* - * Interrupt routine that simply wakes vButtonHandlerTask on each interrupt - * generated by a push of the built in button. - */ -void vButtonISR( void ) __attribute__ ((naked)); -extern xSemaphoreHandle xButtonSemaphore; - -void vButtonISR( void ) -{ - portENTER_SWITCHING_ISR(); - xSemaphoreGiveFromISR( xButtonSemaphore, pdFALSE ); - EXTINT = isrCLEAR_EINT_1; - VICVectAddr = 0; - portEXIT_SWITCHING_ISR( pdTRUE ); -} - - - diff --git a/Demo/ARM7_LPC2138_Rowley/threads.js b/Demo/ARM7_LPC2138_Rowley/threads.js deleted file mode 100644 index 819d7c6bc..000000000 --- a/Demo/ARM7_LPC2138_Rowley/threads.js +++ /dev/null @@ -1,118 +0,0 @@ -function decode_stack(sp) -{ - var i; - var a = new Array(); - - var current_task; - - current_task = Debug.evaluate("pxCurrentTCB"); - - if( current_task == 0 ) - return; - - sp += 4; /* skip stored ulCriticalNesting */ - a[16] = Debug.evaluate("*(unsigned long*)" + sp); - - for (i = 0; i <= 15; i++) - { - sp += 4; - a[i] = Debug.evaluate("*(unsigned long*)" + sp); - } - - return a; -} - -function add_task(task, state) -{ - var tcb, task_name; - - var current_task; - - current_task = Debug.evaluate("pxCurrentTCB"); - - if( current_task == 0 ) - return; - - tcb = Debug.evaluate("*(tskTCB *)" + task); - task_name = Debug.evaluate("(char*)&(*(tskTCB *)" + task + ").pcTaskName[0]"); - Threads.add("#" + tcb.uxTCBNumber + " \"" + task_name + "\"", tcb.uxPriority, state, decode_stack(tcb.pxTopOfStack)); -} - -function add_list(list, state, current_task) -{ - var i, index, item, end; - var current_task; - - current_task = Debug.evaluate("pxCurrentTCB"); - - if( current_task == 0 ) - return; - - if (list.uxNumberOfItems) - { - index = list.pxIndex; - end = list.xListEnd; - for (i = 0; i < list.uxNumberOfItems + 1; i++) - { - item = Debug.evaluate("*(xListItem *)" + index); - if (index != end) - { - task = item.pvOwner; - if (task) add_task(task, (task == current_task) ? "executing" : state); - } - index = item.pxNext; - } - } -} - -function update() -{ - var i, current_task, list, lists, max_priority; - - Threads.clear(); - - current_task = Debug.evaluate("pxCurrentTCB"); - - if( current_task == 0 ) - return; - - Threads.newqueue("Ready"); - lists = Debug.evaluate("pxReadyTasksLists"); - if (lists) - { - max_priority = Debug.evaluate("uxTopUsedPriority"); - max_priority = Debug.evaluate("*(long *)" + max_priority); - - for (i = 0; i <= max_priority; i++) - { - list = Debug.evaluate("((xList*)" + lists + ")[" + (max_priority - i) + "]"); - add_list(list, "ready", current_task); - } - } - - Threads.newqueue("Blocked"); - - list = Debug.evaluate("pxDelayedTaskList"); - if (list) - { - list = Debug.evaluate("**(xList **)" + list); - add_list(list, "blocked"); - } - - list = Debug.evaluate("pxOverflowDelayedTaskList"); - if (list) - { - list = Debug.evaluate("**(xList **)" + list); - add_list(list, "blocked"); - } - - Threads.newqueue("Suspended"); - - list = Debug.evaluate("xSuspendedTaskList"); - if (list) - { - list = Debug.evaluate("*(xList *)" + list); - add_list(list, "suspended"); - } -} - diff --git a/Demo/ARM7_STR71x_IAR/FreeRTOSConfig.h b/Demo/ARM7_STR71x_IAR/FreeRTOSConfig.h deleted file mode 100644 index 61ee4ae16..000000000 --- a/Demo/ARM7_STR71x_IAR/FreeRTOSConfig.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 48000000 ) -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 100 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) 20480 ) -#define configMAX_TASK_NAME_LEN ( 16 ) -#define configUSE_TRACE_FACILITY 0 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 1 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 0 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/ARM7_STR71x_IAR/Library/71x_lib.c b/Demo/ARM7_STR71x_IAR/Library/71x_lib.c deleted file mode 100644 index 53af3c5f0..000000000 --- a/Demo/ARM7_STR71x_IAR/Library/71x_lib.c +++ /dev/null @@ -1,157 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : 71x_lib.c -* Author : MCD Application Team -* Date First Issued : 05/16/2003 -* Description : Peripherals pointers initialization -******************************************************************************** -* History: -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#define EXT - -#include "71x_map.h" - -#ifdef DEBUG - -extern u32 T0TIMI_Addr; - -/******************************************************************************* -* Function Name : debug -* Description : Initialize the pointers to peripherals -* Input : none -* Output : none -* Return : none -*******************************************************************************/ -void debug(void) -{ - #ifdef _ADC12 - ADC12 = (ADC12_TypeDef *)ADC12_BASE; - #endif - - #ifdef _APB - #ifdef _APB1 - APB1 = (APB_TypeDef *)APB1_BASE; - #endif - #ifdef _APB2 - APB2 = (APB_TypeDef *)APB2_BASE; - #endif - #endif - - #ifdef _BSPI - #ifdef _BSPI0 - BSPI0 = (BSPI_TypeDef *)BSPI0_BASE; - #endif - #ifdef _BSPI1 - BSPI1 = (BSPI_TypeDef *)BSPI1_BASE; - #endif - #endif - - #ifdef _CAN - CAN = (CAN_TypeDef *)CAN_BASE; - #endif - - #ifdef _EIC - EIC = (EIC_TypeDef *)EIC_BASE; - #endif - - #ifdef _EMI - EMI = (EMI_TypeDef *)EMI_BASE; - #endif - - #ifdef _FLASH - FLASHR = (FLASHR_TypeDef *)FLASHR_BASE; - FLASHPR = (FLASHPR_TypeDef *)FLASHPR_BASE; - #endif - - #ifdef _GPIO - #ifdef _GPIO0 - GPIO0 = (GPIO_TypeDef *)GPIO0_BASE; - #endif - #ifdef _GPIO1 - GPIO1 = (GPIO_TypeDef *)GPIO1_BASE; - #endif - #ifdef _GPIO2 - GPIO2 = (GPIO_TypeDef *)GPIO2_BASE; - #endif - #endif - - #ifdef _I2C - #ifdef _I2C0 - I2C0 = (I2C_TypeDef *)I2C0_BASE; - #endif - #ifdef _I2C1 - I2C1 = (I2C_TypeDef *)I2C1_BASE; - #endif - #endif - - #ifdef _PCU - PCU = (PCU_TypeDef *)PCU_BASE; - #endif - - #ifdef _RCCU - RCCU = (RCCU_TypeDef *)RCCU_BASE; - #endif - - #ifdef _RTC - RTC = (RTC_TypeDef *)RTC_BASE; - #endif - - #ifdef _TIM - #ifdef _TIM0 - TIM0 = (TIM_TypeDef *)TIM0_BASE; - #endif - #ifdef _TIM1 - TIM1 = (TIM_TypeDef *)TIM1_BASE; - #endif - #ifdef _TIM2 - TIM2 = (TIM_TypeDef *)TIM2_BASE; - #endif - #ifdef _TIM3 - TIM3 = (TIM_TypeDef *)TIM3_BASE; - #endif - #endif - - #ifdef _UART - #ifdef _UART0 - UART0 = (UART_TypeDef *)UART0_BASE; - #endif - #ifdef _UART1 - UART1 = (UART_TypeDef *)UART1_BASE; - #endif - #ifdef _UART2 - UART2 = (UART_TypeDef *)UART2_BASE; - #endif - #ifdef _UART3 - UART3 = (UART_TypeDef *)UART3_BASE; - #endif - #endif - - #ifdef _USB - USB = (USB_TypeDef *)USB_BASE; - #endif - - #ifdef _WDG - WDG = (WDG_TypeDef *)WDG_BASE; - #endif - - #ifdef _XTI - XTI = (XTI_TypeDef *)XTI_BASE; - #endif - - #ifdef _IRQVectors - IRQVectors = (IRQVectors_TypeDef *)&T0TIMI_Addr; - #endif -} - -#endif /* DEBUG */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR71x_IAR/Library/gpio.c b/Demo/ARM7_STR71x_IAR/Library/gpio.c deleted file mode 100644 index 7c1bbb119..000000000 --- a/Demo/ARM7_STR71x_IAR/Library/gpio.c +++ /dev/null @@ -1,114 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : gpio.c -* Author : MCD Application Team -* Date First Issued : 06/08/2003 -* Description : This file provides all the GPIO software functions -******************************************************************************** -* History: -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#include "gpio.h" - -/******************************************************************************* -* Function Name : GPIO_Config -* Description : Configure the GPIO port pins -* Input 1 : GPIOx (x can be 0,1 or 2) the desired port -* Input 2 : Port_Pins : pins placements -* Input 3 : Pins Mode -* Output : None -* Return : None -*******************************************************************************/ -void GPIO_Config (GPIO_TypeDef *GPIOx, u16 Port_Pins, GpioPinMode_TypeDef GPIO_Mode) -{ - switch (GPIO_Mode) - { - case GPIO_HI_AIN_TRI: - GPIOx->PC0&=~Port_Pins; - GPIOx->PC1&=~Port_Pins; - GPIOx->PC2&=~Port_Pins; - break; - - case GPIO_IN_TRI_TTL: - GPIOx->PC0|=Port_Pins; - GPIOx->PC1&=~Port_Pins; - GPIOx->PC2&=~Port_Pins; - break; - - case GPIO_IN_TRI_CMOS: - GPIOx->PC0&=~Port_Pins; - GPIOx->PC1|=Port_Pins; - GPIOx->PC2&=~Port_Pins; - break; - - case GPIO_IPUPD_WP: - GPIOx->PC0|=Port_Pins; - GPIOx->PC1|=Port_Pins; - GPIOx->PC2&=~Port_Pins; - break; - - case GPIO_OUT_OD: - GPIOx->PC0&=~Port_Pins; - GPIOx->PC1&=~Port_Pins; - GPIOx->PC2|=Port_Pins; - break; - - case GPIO_OUT_PP: - GPIOx->PC0|=Port_Pins; - GPIOx->PC1&=~Port_Pins; - GPIOx->PC2|=Port_Pins; - break; - - case GPIO_AF_OD: - GPIOx->PC0&=~Port_Pins; - GPIOx->PC1|=Port_Pins; - GPIOx->PC2|=Port_Pins; - break; - - case GPIO_AF_PP: - GPIOx->PC0|=Port_Pins; - GPIOx->PC1|=Port_Pins; - GPIOx->PC2|=Port_Pins; - break; - } -} - -/******************************************************************************* -* Function Name : GPIO_BitWrite -* Description : Set or reset the selected port pin -* Input 1 : Selected GPIO port -* Input 2 : Pin number -* Input 3 : bit value -* Output : None -* Return : None -*******************************************************************************/ -void GPIO_BitWrite(GPIO_TypeDef *GPIOx, u8 Port_Pin, u8 Port_Val) -{ - if (Port_Val&0x01) GPIOx->PD |= 1<PD &= ~(1<PD = Port_Byte ? (GPIOx->PD&0x00FF) | ((u16)Port_Val<<8) - : (GPIOx->PD&0xFF00) | Port_Val; -} - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR71x_IAR/Library/include/71x_conf.h b/Demo/ARM7_STR71x_IAR/Library/include/71x_conf.h deleted file mode 100644 index 26e5383a3..000000000 --- a/Demo/ARM7_STR71x_IAR/Library/include/71x_conf.h +++ /dev/null @@ -1,91 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : 71x_conf.h -* Author : MCD Application Team -* Date First Issued : 16/05/2003 -* Description : Library configuration for the ADC12 example -******************************************************************************** -* History: -* 16/05/2003 : Created -* 30/11/2004 : V2.0 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef __71x_CONF_H -#define __71x_CONF_H - - -/* Comment the line below to put the library in release mode */ -//#define DEBUG - -//#define inline inline - -//#define USE_SERIAL_PORT -//#define USE_UART0 - -// Main Oscillator Frequency value = 4 Mhz -#define RCCU_Main_Osc 4000000 - -/* Comment the lines below corresponding to unwanted peripherals */ -//#define _ADC12 - -//#define _APB -//#define _APB1 -//#define _APB2 - -//#define _BSPI -//#define _BSPI0 -//#define _BSPI1 - -//#define _CAN - -//#define _EIC - -//#define _EMI - -//#define _FLASH - -#define _GPIO -#define _GPIO0 -#define _GPIO1 -#define _GPIO2 - -//#define _I2C -//#define _I2C0 -//#define _I2C1 - -#define _PCU - -#define _RCCU - -//#define _RTC - -#define _TIM -#define _TIM0 -//#define _TIM1 -//#define _TIM2 -//#define _TIM3 - -//#define _UART -//#define _UART0 -//#define _UART1 -//#define _UART2 -//#define _UART3 - -//#define _USB - -//#define _WDG - -//#define _XTI - - -//#define _IRQVectors - - -#endif /* __71x_CONF_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR71x_IAR/Library/include/71x_it.h b/Demo/ARM7_STR71x_IAR/Library/include/71x_it.h deleted file mode 100644 index ebfc97296..000000000 --- a/Demo/ARM7_STR71x_IAR/Library/include/71x_it.h +++ /dev/null @@ -1,61 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : 71x_it.h -* Author : MCD Application Team -* Date First Issued : 05/16/2003 -* Description : Interrupt handlers -******************************************************************************** -* History: -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#ifndef _71x_IT_H -#define _71x_IT_H - -#include "71x_lib.h" - - -void Undefined_Handler (void); -void FIQ_Handler (void); -void SWI_Handler (void); -void Prefetch_Handler (void); -void Abort_Handler (void); -void T0TIMI_IRQHandler (void); -void FLASH_IRQHandler (void); -void RCCU_IRQHandler (void); -void RTC_IRQHandler (void); -void WDG_IRQHandler (void); -void XTI_IRQHandler (void); -void USBHP_IRQHandler (void); -void I2C0ITERR_IRQHandler(void); -void I2C1ITERR_IRQHandler(void); -void UART0_IRQHandler (void); -void UART1_IRQHandler (void); -void UART2_IRQHandler (void); -void UART3_IRQHandler (void); -void BSPI0_IRQHandler (void); -void BSPI1_IRQHandler (void); -void I2C0_IRQHandler (void); -void I2C1_IRQHandler (void); -void CAN_IRQHandler (void); -void ADC12_IRQHandler (void); -void T1TIMI_IRQHandler (void); -void T2TIMI_IRQHandler (void); -void T3TIMI_IRQHandler (void); -void HDLC_IRQHandler (void); -void USBLP_IRQHandler (void); -void T0TOI_IRQHandler (void); -void T0OC1_IRQHandler (void); -void T0OC2_IRQHandler (void); - -#endif /* _71x_IT_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR71x_IAR/Library/include/71x_lib.h b/Demo/ARM7_STR71x_IAR/Library/include/71x_lib.h deleted file mode 100644 index 8da0d658c..000000000 --- a/Demo/ARM7_STR71x_IAR/Library/include/71x_lib.h +++ /dev/null @@ -1,99 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : 71x_lib.h -* Author : MCD Application Team -* Date First Issued : 05/16/2003 -* Description : Global include for all peripherals -******************************************************************************** -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef __71x_LIB_H -#define __71x_LIB_H - -#include "71x_map.h" -#include "71x_conf.h" - - -#ifdef _ADC12 - #include "adc12.h" -#endif - -#ifdef _APB - #include "apb.h" -#endif - -#ifdef _BSPI - #include "bspi.h" -#endif - -#ifdef _CAN - #include "can.h" -#endif - -#ifdef _EIC - #include "eic.h" -#endif - -#ifdef _EMI - #include "emi.h" -#endif - -#ifdef _FLASH - #include "flash.h" -#endif - -#ifdef _GPIO - #include "gpio.h" -#endif - -#ifdef _I2C - #include "i2c.h" -#endif - -#ifdef _PCU - #include "pcu.h" -#endif - -#ifdef _RCCU - #include "rccu.h" -#endif - -#ifdef _RTC - #include "rtc.h" -#endif - -#ifdef _TIM - #include "tim.h" -#endif - -#ifdef _UART - #include "uart.h" -#endif - -#ifdef _USB -#endif - -#ifdef _WDG - #include "wdg.h" -#endif - -#ifdef _XTI - #include "xti.h" -#endif - - -#ifdef DEBUG - void debug(void); -#endif - -#endif /* __71x_LIB_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR71x_IAR/Library/include/71x_map.h b/Demo/ARM7_STR71x_IAR/Library/include/71x_map.h deleted file mode 100644 index fe1089ece..000000000 --- a/Demo/ARM7_STR71x_IAR/Library/include/71x_map.h +++ /dev/null @@ -1,610 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : 71x_map.h -* Author : MCD Application Team -* Date First Issued : 05/16/2003 -* Description : Peripherals memory mapping and registers structures -******************************************************************************** -* History: -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#ifndef __71x_map_H -#define __71x_map_H - -#ifndef EXT - #define EXT extern -#endif - -#include "71x_conf.h" -#include "71x_type.h" - - -/* IP registers structures */ - -typedef volatile struct -{ - vu16 DATA0; - vu16 EMPTY1[3]; - vu16 DATA1; - vu16 EMPTY2[3]; - vu16 DATA2; - vu16 EMPTY3[3]; - vu16 DATA3; - vu16 EMPTY4[3]; - vu16 CSR; - vu16 EMPTY5[7]; - vu16 CPR; -} ADC12_TypeDef; - -typedef volatile struct -{ - vu32 CKDIS; - vu32 SWRES; -} APB_TypeDef; - -typedef volatile struct -{ - vu16 RXR; - vu16 EMPTY1; - vu16 TXR; - vu16 EMPTY2; - vu16 CSR1; - vu16 EMPTY3; - vu16 CSR2; - vu16 EMPTY4; - vu16 CLK; -} BSPI_TypeDef; - -typedef volatile struct -{ - vu16 CRR; - vu16 EMPTY1; - vu16 CMR; - vu16 EMPTY2; - vu16 M1R; - vu16 EMPTY3; - vu16 M2R; - vu16 EMPTY4; - vu16 A1R; - vu16 EMPTY5; - vu16 A2R; - vu16 EMPTY6; - vu16 MCR; - vu16 EMPTY7; - vu16 DA1R; - vu16 EMPTY8; - vu16 DA2R; - vu16 EMPTY9; - vu16 DB1R; - vu16 EMPTY10; - vu16 DB2R; - vu16 EMPTY11[27]; -} CAN_MsgObj_TypeDef; - -typedef volatile struct -{ - vu16 CR; - vu16 EMPTY1; - vu16 SR; - vu16 EMPTY2; - vu16 ERR; - vu16 EMPTY3; - vu16 BTR; - vu16 EMPTY4; - vu16 IDR; - vu16 EMPTY5; - vu16 TESTR; - vu16 EMPTY6; - vu16 BRPR; - vu16 EMPTY7[3]; - CAN_MsgObj_TypeDef sMsgObj[2]; - vu16 EMPTY8[16]; - vu16 TR1R; - vu16 EMPTY9; - vu16 TR2R; - vu16 EMPTY10[13]; - vu16 ND1R; - vu16 EMPTY11; - vu16 ND2R; - vu16 EMPTY12[13]; - vu16 IP1R; - vu16 EMPTY13; - vu16 IP2R; - vu16 EMPTY14[13]; - vu16 MV1R; - vu16 EMPTY15; - vu16 MV2R; - vu16 EMPTY16; -} CAN_TypeDef; - -typedef volatile struct -{ - vu32 ICR; - vu32 CICR; - vu32 CIPR; - vu32 EMPTY1[3]; - vu32 IVR; - vu32 FIR; - vu32 IER; - vu32 EMPTY2[7]; - vu32 IPR; - vu32 EMPTY3[7]; - vu32 SIR[32]; -} EIC_TypeDef; - -typedef volatile struct -{ - vu16 BCON0; - vu16 EMPTY1; - vu16 BCON1; - vu16 EMPTY2; - vu16 BCON2; - vu16 EMPTY3; - vu16 BCON3; - vu16 EMPTY4; -} EMI_TypeDef; - -typedef volatile struct -{ - vu32 CR0; - vu32 CR1; - vu32 DR0; - vu32 DR1; - vu32 AR; - vu32 ER; -} FLASHR_TypeDef; - -typedef volatile struct -{ - vu32 NVWPAR; - vu32 EMPTY; - vu32 NVAPR0; - vu32 NVAPR1; -} FLASHPR_TypeDef; - -typedef volatile struct -{ - vu16 PC0; - vu16 EMPTY1; - vu16 PC1; - vu16 EMPTY2; - vu16 PC2; - vu16 EMPTY3; - vu16 PD; - vu16 EMPTY4; -} GPIO_TypeDef; - -typedef volatile struct -{ - vu8 CR; - vu8 EMPTY1[3]; - vu8 SR1; - vu8 EMPTY2[3]; - vu8 SR2; - vu8 EMPTY3[3]; - vu8 CCR; - vu8 EMPTY4[3]; - vu8 OAR1; - vu8 EMPTY5[3]; - vu8 OAR2; - vu8 EMPTY6[3]; - vu8 DR; - vu8 EMPTY7[3]; - vu8 ECCR; -} I2C_TypeDef; - -typedef volatile struct -{ - vu32 CCR; - vu32 EMPTY1; - vu32 CFR; - vu32 EMPTY2[3]; - vu32 PLL1CR; - vu32 PER; - vu32 SMR; -} RCCU_TypeDef; - -typedef volatile struct -{ - vu16 MDIVR; - vu16 EMPTY1; - vu16 PDIVR; - vu16 EMPTY2; - vu16 RSTR; - vu16 EMPTY3; - vu16 PLL2CR; - vu16 EMPTY4; - vu16 BOOTCR; - vu16 EMPTY5; - vu16 PWRCR; -} PCU_TypeDef; - -typedef volatile struct -{ - vu16 CRH; - vu16 EMPTY1; - vu16 CRL; - vu16 EMPTY2; - vu16 PRLH; - vu16 EMPTY3; - vu16 PRLL; - vu16 EMPTY4; - vu16 DIVH; - vu16 EMPTY5; - vu16 DIVL; - vu16 EMPTY6; - vu16 CNTH; - vu16 EMPTY7; - vu16 CNTL; - vu16 EMPTY8; - vu16 ALRH; - vu16 EMPTY9; - vu16 ALRL; -} RTC_TypeDef; - -typedef volatile struct -{ - vu16 ICAR; - vu16 EMPTY1; - vu16 ICBR; - vu16 EMPTY2; - vu16 OCAR; - vu16 EMPTY3; - vu16 OCBR; - vu16 EMPTY4; - vu16 CNTR; - vu16 EMPTY5; - vu16 CR1; - vu16 EMPTY6; - vu16 CR2; - vu16 EMPTY7; - vu16 SR; -} TIM_TypeDef; - -typedef volatile struct -{ - vu16 BR; - vu16 EMPTY1; - vu16 TxBUFR; - vu16 EMPTY2; - vu16 RxBUFR; - vu16 EMPTY3; - vu16 CR; - vu16 EMPTY4; - vu16 IER; - vu16 EMPTY5; - vu16 SR; - vu16 EMPTY6; - vu16 GTR; - vu16 EMPTY7; - vu16 TOR; - vu16 EMPTY8; - vu16 TxRSTR; - vu16 EMPTY9; - vu16 RxRSTR; -} UART_TypeDef; - -typedef volatile struct -{ - vu32 EP0R; - vu32 EP1R; - vu32 EP2R; - vu32 EP3R; - vu32 EP4R; - vu32 EP5R; - vu32 EP6R; - vu32 EP7R; - vu32 EP8R; - vu32 EP9R; - vu32 EP10R; - vu32 EP11R; - vu32 EP12R; - vu32 EP13R; - vu32 EP14R; - vu32 EP15R; - vu32 CNTR; - vu32 ISTR; - vu32 FNR; - vu32 DADDR; - vu32 BTABLE; -} USB_TypeDef; - -typedef volatile struct -{ - vu16 CR; - vu16 EMPTY1; - vu16 PR; - vu16 EMPTY2; - vu16 VR; - vu16 EMPTY3; - vu16 CNT; - vu16 EMPTY4; - vu16 SR; - vu16 EMPTY5; - vu16 MR; - vu16 EMPTY6; - vu16 KR; -} WDG_TypeDef; - -typedef volatile struct -{ - vu8 SR; - vu8 EMPTY1[7]; - vu8 CTRL; - vu8 EMPTY2[3]; - vu8 MRH; - vu8 EMPTY3[3]; - vu8 MRL; - vu8 EMPTY4[3]; - vu8 TRH; - vu8 EMPTY5[3]; - vu8 TRL; - vu8 EMPTY6[3]; - vu8 PRH; - vu8 EMPTY7[3]; - vu8 PRL; -} XTI_TypeDef; - - -/* IRQ vectors */ -typedef volatile struct -{ - vu32 T0TIMI_IRQHandler; - vu32 FLASH_IRQHandler; - vu32 RCCU_IRQHandler; - vu32 RTC_IRQHandler; - vu32 WDG_IRQHandler; - vu32 XTI_IRQHandler; - vu32 USBHP_IRQHandler; - vu32 I2C0ITERR_IRQHandler; - vu32 I2C1ITERR_IRQHandler; - vu32 UART0_IRQHandler; - vu32 UART1_IRQHandler; - vu32 UART2_IRQHandler; - vu32 UART3_IRQHandler; - vu32 BSPI0_IRQHandler; - vu32 BSPI1_IRQHandler; - vu32 I2C0_IRQHandler; - vu32 I2C1_IRQHandler; - vu32 CAN_IRQHandler; - vu32 ADC12_IRQHandler; - vu32 T1TIMI_IRQHandler; - vu32 T2TIMI_IRQHandler; - vu32 T3TIMI_IRQHandler; - vu32 EMPTY1[3]; - vu32 HDLC_IRQHandler; - vu32 USBLP_IRQHandler; - vu32 EMPTY2[2]; - vu32 T0TOI_IRQHandler; - vu32 T0OC1_IRQHandler; - vu32 T0OC2_IRQHandler; -} IRQVectors_TypeDef; - -/*===================================================================*/ - -/* Memory mapping */ - -#define RAM_BASE 0x20000000 - -#define FLASHR_BASE 0x40100000 -#define FLASHPR_BASE 0x4010DFB0 - -#define EXTMEM_BASE 0x60000000 -#define RCCU_BASE 0xA0000000 -#define PCU_BASE 0xA0000040 -#define APB1_BASE 0xC0000000 -#define APB2_BASE 0xE0000000 -#define EIC_BASE 0xFFFFF800 - -#define I2C0_BASE (APB1_BASE + 0x1000) -#define I2C1_BASE (APB1_BASE + 0x2000) -#define UART0_BASE (APB1_BASE + 0x4000) -#define UART1_BASE (APB1_BASE + 0x5000) -#define UART2_BASE (APB1_BASE + 0x6000) -#define UART3_BASE (APB1_BASE + 0x7000) -#define CAN_BASE (APB1_BASE + 0x9000) -#define BSPI0_BASE (APB1_BASE + 0xA000) -#define BSPI1_BASE (APB1_BASE + 0xB000) -#define USB_BASE (APB1_BASE + 0x8800) - -#define XTI_BASE (APB2_BASE + 0x101C) -#define GPIO0_BASE (APB2_BASE + 0x3000) -#define GPIO1_BASE (APB2_BASE + 0x4000) -#define GPIO2_BASE (APB2_BASE + 0x5000) -#define ADC12_BASE (APB2_BASE + 0x7000) -#define TIM0_BASE (APB2_BASE + 0x9000) -#define TIM1_BASE (APB2_BASE + 0xA000) -#define TIM2_BASE (APB2_BASE + 0xB000) -#define TIM3_BASE (APB2_BASE + 0xC000) -#define RTC_BASE (APB2_BASE + 0xD000) -#define WDG_BASE (APB2_BASE + 0xE000) - -#define EMI_BASE (EXTMEM_BASE + 0x0C000000) - -/*===================================================================*/ - -/* IP data access */ - -#ifndef DEBUG - #define ADC12 ((ADC12_TypeDef *)ADC12_BASE) - - #define APB1 ((APB_TypeDef *)APB1_BASE) - #define APB2 ((APB_TypeDef *)APB2_BASE+0x10) - - #define BSPI0 ((BSPI_TypeDef *)BSPI0_BASE) - #define BSPI1 ((BSPI_TypeDef *)BSPI1_BASE) - - #define CAN ((CAN_TypeDef *)CAN_BASE) - - #define EIC ((EIC_TypeDef *)EIC_BASE) - - #define EMI ((EMI_TypeDef *)EMI_BASE) - - #define FLASHR ((FLASHR_TypeDef *)FLASHR_BASE) - #define FLASHPR ((FLASHPR_TypeDef *)FLASHPR_BASE) - - #define GPIO0 ((GPIO_TypeDef *)GPIO0_BASE) - #define GPIO1 ((GPIO_TypeDef *)GPIO1_BASE) - #define GPIO2 ((GPIO_TypeDef *)GPIO2_BASE) - - #define I2C0 ((I2C_TypeDef *)I2C0_BASE) - #define I2C1 ((I2C_TypeDef *)I2C1_BASE) - - #define PCU ((PCU_TypeDef *)PCU_BASE) - - #define RCCU ((RCCU_TypeDef *)RCCU_BASE) - - #define RTC ((RTC_TypeDef *)RTC_BASE) - - #define TIM0 ((TIM_TypeDef *)TIM0_BASE) - #define TIM1 ((TIM_TypeDef *)TIM1_BASE) - #define TIM2 ((TIM_TypeDef *)TIM2_BASE) - #define TIM3 ((TIM_TypeDef *)TIM3_BASE) - - #define UART0 ((UART_TypeDef *)UART0_BASE) - #define UART1 ((UART_TypeDef *)UART1_BASE) - #define UART2 ((UART_TypeDef *)UART2_BASE) - #define UART3 ((UART_TypeDef *)UART3_BASE) - - #define USB ((USB_TypeDef *)USB_BASE) - - #define WDG ((WDG_TypeDef *)WDG_BASE) - - #define XTI ((XTI_TypeDef *)XTI_BASE) - - #define IRQVectors ((IRQVectors_TypeDef *)&T0TIMI_Addr) - -#else /* DEBUG */ - - #ifdef _ADC12 - EXT ADC12_TypeDef *ADC12; - #endif - - #ifdef _APB - #ifdef _APB1 - EXT APB_TypeDef *APB1; - #endif - #ifdef _APB2 - EXT APB_TypeDef *APB2; - #endif - #endif - - #ifdef _BSPI - #ifdef _BSPI0 - EXT BSPI_TypeDef *BSPI0; - #endif - #ifdef _BSPI1 - EXT BSPI_TypeDef *BSPI1; - #endif - #endif - - #ifdef _CAN - EXT CAN_TypeDef *CAN; - #endif - - #ifdef _EIC - EXT EIC_TypeDef *EIC; - #endif - - #ifdef _EMI - EXT EMI_TypeDef *EMI; - #endif - - #ifdef _FLASH - EXT FLASHR_TypeDef *FLASHR; - EXT FLASHPR_TypeDef *FLASHPR; - #endif - - #ifdef _GPIO - #ifdef _GPIO0 - EXT GPIO_TypeDef *GPIO0; - #endif - #ifdef _GPIO1 - EXT GPIO_TypeDef *GPIO1; - #endif - #ifdef _GPIO2 - EXT GPIO_TypeDef *GPIO2; - #endif - #endif - - #ifdef _I2C - #ifdef _I2C0 - EXT I2C_TypeDef *I2C0; - #endif - #ifdef _I2C1 - EXT I2C_TypeDef *I2C1; - #endif - #endif - - #ifdef _PCU - EXT PCU_TypeDef *PCU; - #endif - - #ifdef _RCCU - EXT RCCU_TypeDef *RCCU; - #endif - - #ifdef _RTC - EXT RTC_TypeDef *RTC; - #endif - - #ifdef _TIM - #ifdef _TIM0 - EXT TIM_TypeDef *TIM0; - #endif - #ifdef _TIM1 - EXT TIM_TypeDef *TIM1; - #endif - #ifdef _TIM2 - EXT TIM_TypeDef *TIM2; - #endif - #ifdef _TIM3 - EXT TIM_TypeDef *TIM3; - #endif - #endif - - #ifdef _UART - #ifdef _UART0 - EXT UART_TypeDef *UART0; - #endif - #ifdef _UART1 - EXT UART_TypeDef *UART1; - #endif - #ifdef _UART2 - EXT UART_TypeDef *UART2; - #endif - #ifdef _UART3 - EXT UART_TypeDef *UART3; - #endif - #endif - - #ifdef _USB - EXT USB_TypeDef *USB; - #endif - - #ifdef _WDG - EXT WDG_TypeDef *WDG; - #endif - - #ifdef _XTI - EXT XTI_TypeDef *XTI; - #endif - - #ifdef _IRQVectors - EXT IRQVectors_TypeDef *IRQVectors; - #endif - -#endif /* DEBUG */ - -#endif /* __71x_map_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR71x_IAR/Library/include/71x_type.h b/Demo/ARM7_STR71x_IAR/Library/include/71x_type.h deleted file mode 100644 index 39e2175f2..000000000 --- a/Demo/ARM7_STR71x_IAR/Library/include/71x_type.h +++ /dev/null @@ -1,50 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : 71x_type.h -* Author : MCD Application Team -* Date First Issued : 05/16/2003 -* Description : Common data types -******************************************************************************** -* History: -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef _71x_type_H -#define _71x_type_H - -typedef unsigned long u32; -typedef unsigned short u16; -typedef unsigned char u8; - -typedef signed long s32; -typedef signed short s16; -typedef signed char s8; - -typedef volatile unsigned long vu32; -typedef volatile unsigned short vu16; -typedef volatile unsigned char vu8; - -typedef volatile signed long vs32; -typedef volatile signed short vs16; -typedef volatile signed char vs8; - -/*===================================================================*/ -typedef enum { FALSE = 0, TRUE = !FALSE } bool; -/*===================================================================*/ -typedef enum { RESET = 0, SET = !RESET } FlagStatus; -/*===================================================================*/ -typedef enum { DISABLE = 0, ENABLE = !DISABLE} FunctionalState; -/*===================================================================*/ -typedef enum { INDIRECT = 0, DIRECT = !INDIRECT} RegisterAccess; -/*===================================================================*/ - -#endif /* _71x_type_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR71x_IAR/Library/include/eic.h b/Demo/ARM7_STR71x_IAR/Library/include/eic.h deleted file mode 100644 index cbe149b56..000000000 --- a/Demo/ARM7_STR71x_IAR/Library/include/eic.h +++ /dev/null @@ -1,199 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : eic.h -* Author : MCD Application Team -* Date First Issued : 25/06/2003 -* Description : This file contains all the functions prototypes for the -* EIC software library. -******************************************************************************** -* History: -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef __eic_H -#define __eic_H - -#include "71x_map.h" - -typedef enum -{ - T0TIMI_IRQChannel = 0, - FLASH_IRQChannel = 1, - RCCU_IRQChannel = 2, - RTC_IRQChannel = 3, - WDG_IRQChannel = 4, - XTI_IRQChannel = 5, - USBHP_IRQChannel = 6, - I2C0ITERR_IRQChannel = 7, - I2C1ITERR_IRQChannel = 8, - UART0_IRQChannel = 9, - UART1_IRQChannel = 10, - UART2_IRQChannel = 11, - UART3_IRQChannel = 12, - SPI0_IRQChannel = 13, - SPI1_IRQChannel = 14, - I2C0_IRQChannel = 15, - I2C1_IRQChannel = 16, - CAN_IRQChannel = 17, - ADC_IRQChannel = 18, - T1TIMI_IRQChannel = 19, - T2TIMI_IRQChannel = 20, - T3TIMI_IRQChannel = 21, - HDLC_IRQChannel = 25, - USBLP_IRQChannel = 26, - T0TOI_IRQChannel = 29, - T0OC1_IRQChannel = 30, - T0OC2_IRQChannel = 31 -} IRQChannel_TypeDef; - -typedef enum -{ - T0TIMI_FIQChannel = 0x00000001, - WDG_FIQChannel = 0x00000002, - WDGT0TIMI_FIQChannels = 0x00000003 -} FIQChannel_TypeDef; - -/******************************************************************************* -* Function Name : EIC_Init -* Description : Initialise the EIC using the load PC instruction -* (PC = PC +offset) -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void EIC_Init(void); - -/******************************************************************************* -* Function Name : EIC_IRQConfig -* Description : Enable or Disable IRQ interrupts -* Input 1 : New status : can be ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -inline void EIC_IRQConfig(FunctionalState NewState) -{ - if (NewState==ENABLE) EIC->ICR |= 0x0001; else EIC->ICR &= ~0x0001; -} - -/******************************************************************************* -* Function Name : EIC_FIQConfig -* Description : Enable or Disable FIQ interrupts -* Input 1 : New status : can be ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -inline void EIC_FIQConfig(FunctionalState NewState) -{ - if (NewState==ENABLE) EIC->ICR |= 0x0002; else EIC->ICR &= ~0x0002; -} - -/******************************************************************************* -* Function Name : EIC_IRQChannelConfig -* Description : Configure the IRQ Channel -* Input 1 : IRQ channel name -* Input 2 : Channel New status : can be ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -inline void EIC_IRQChannelConfig(IRQChannel_TypeDef IRQChannel, FunctionalState NewState) -{ - if (NewState==ENABLE) EIC->IER |= 0x0001 << IRQChannel; - else EIC->IER &= ~(0x0001 << IRQChannel); -} - -/******************************************************************************* -* Function Name : EIC_FIQChannelConfig -* Description : Configure the FIQ Channel -* Input 1 : FIQ channel name -* Input 2 : Channel New status : can be ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -inline void EIC_FIQChannelConfig(FIQChannel_TypeDef FIQChannel, - FunctionalState NewState) -{ - if (NewState==ENABLE) EIC->FIR |= FIQChannel; - else EIC->FIR &= ~FIQChannel; -} - -/******************************************************************************* -* Function Name : EIC_IRQChannelPriorityConfig -* Description : Configure the selected IRQ channel priority -* Input 1 : IRQ channel name -* Input 2 : IRQ channel priority -* Output : None -* Return : None -*******************************************************************************/ -inline void EIC_IRQChannelPriorityConfig(IRQChannel_TypeDef IRQChannel, u8 Priority) -{ - EIC->SIR[IRQChannel] = (EIC->SIR[IRQChannel]&0xFFFF0000) | (u16)Priority & 0x000F; -} - -/******************************************************************************* -* Function Name : EIC_CurrentPriorityLevelConfig -* Description : Change the current priority level of the srved IRQ routine -* Input 1 : New priority -* Output : None -* Return : None -*******************************************************************************/ -void EIC_CurrentPriorityLevelConfig(u8 NewPriorityLevel); - -/******************************************************************************* -* Function Name : EIC_CurrentPriorityLevelValue -* Description : Return the current priority level of the current served IRQ -* routine -* Input : None -* Output : None -* Return : The current priority level -*******************************************************************************/ -inline u8 EIC_CurrentPriorityLevelValue(void) -{ - return EIC->CIPR & 0xF; -} - -/******************************************************************************* -* Function Name : EIC_CurrentIRQChannelValue -* Description : Return the current served IRQ channel number -* Input 0 : None -* Output : None -* Return : The current served IRQ channel number -*******************************************************************************/ -inline IRQChannel_TypeDef EIC_CurrentIRQChannelValue(void) -{ - return (IRQChannel_TypeDef)(EIC->CICR & 0x1F); -} - -/******************************************************************************* -* Function Name : EIC_CurrentFIQChannelValue -* Description : Return the current served FIQ channel number -* Input : None -* Output : None -* Return : The current served FIQ channel number -*******************************************************************************/ -inline FIQChannel_TypeDef EIC_CurrentFIQChannelValue(void) -{ - return (FIQChannel_TypeDef)((EIC->FIR >> 2) & 0x0003); -} - -/******************************************************************************* -* Function Name : EIC_FIPendingBitClear -* Description : Clear the FIQ pending bit -* Input 1 : FIQ channel -* Output : None -* Return : None -*******************************************************************************/ -inline void EIC_FIQPendingBitClear(FIQChannel_TypeDef FIQChannel) -{ - EIC->FIR = (EIC->FIR & 0x0003) | (FIQChannel << 2); -} - -#endif /* __eic_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR71x_IAR/Library/include/gpio.h b/Demo/ARM7_STR71x_IAR/Library/include/gpio.h deleted file mode 100644 index 2ea6decf6..000000000 --- a/Demo/ARM7_STR71x_IAR/Library/include/gpio.h +++ /dev/null @@ -1,126 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : gpio.h -* Author : MCD Application Team -* Date First Issued : 08/06/2003 -* Description : This file contains all the functions prototypes for the -* GPIO software library. -******************************************************************************** -* History: -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef __gpio_H -#define __gpio_H - -#include "71x_map.h" - -typedef enum -{ - GPIO_HI_AIN_TRI, - GPIO_IN_TRI_TTL, - GPIO_IN_TRI_CMOS, - GPIO_IPUPD_WP, - GPIO_OUT_OD, - GPIO_OUT_PP, - GPIO_AF_OD, - GPIO_AF_PP -} GpioPinMode_TypeDef; - -#define GPIO_LSB 0x00 -#define GPIO_MSB 0x08 - -/******************************************************************************* -* Function Name : GPIO_Config -* Description : Configure the GPIO port pins -* Input 1 : GPIOx (x can be 0,1 or 2) the desired port -* Input 2 : Port_Pins : pins placements -* Input 3 : Pins Mode -* Output : None -* Return : None -*******************************************************************************/ -void GPIO_Config (GPIO_TypeDef *GPIOx, u16 Port_Pins, GpioPinMode_TypeDef GPIO_Mode); - -/******************************************************************************* -* Function Name : GPIO_BitRead -* Description : Read the desired port pin value -* Input 1 : Selected GPIO port -* Input 2 : Pin number -* Output : None -* Return : The selected pin value -*******************************************************************************/ -inline u8 GPIO_BitRead(GPIO_TypeDef *GPIOx, u8 Port_Pin) -{ - return (GPIOx->PD >> Port_Pin) & 0x0001; -} - -/******************************************************************************* -* Function Name : GPIO_ByteRead -* Description : Read the desired port Byte value -* Input 1 : Selected GPIO port -* Input 2 : GPIO_MSB or GPIO_LSB -* Output : None -* Return : The GPIO_MSB or GPIO_LSB of the selected PD register -*******************************************************************************/ -inline u8 GPIO_ByteRead(GPIO_TypeDef *GPIOx, u8 Port_Byte) -{ - return (u8)(GPIOx->PD >> Port_Byte); -} - -/******************************************************************************* -* Function Name : GPIO_WordRead -* Description : Read the desired port word value -* Input 1 : Selected GPIO port -* Output : None -* Return : The selected PD register value -*******************************************************************************/ -inline u16 GPIO_WordRead(GPIO_TypeDef *GPIOx) -{ - return GPIOx->PD; -} - -/******************************************************************************* -* Function Name : GPIO_BitWrite -* Description : Set or reset the selected port pin -* Input 1 : Selected GPIO port -* Input 2 : Pin number -* Input 3 : bit value -* Output : None -* Return : None -*******************************************************************************/ -void GPIO_BitWrite(GPIO_TypeDef *GPIOx, u8 Port_Pin, u8 Port_Val); - -/******************************************************************************* -* Function Name : GPIO_ByteWrite -* Description : Write byte value to the selected PD register -* Input 1 : Selected GPIO port -* Input 2 : GPIO_MSB or GPIO_LSB -* Input 3 : Byte value -* Output : None -* Return : None -*******************************************************************************/ -void GPIO_ByteWrite(GPIO_TypeDef *GPIOx, u8 Port_Byte, u8 Port_Val); - -/******************************************************************************* -* Function Name : GPIO_WordWrite -* Description : Write word value to the selected PD register -* Input 1 : Selected GPIO port -* Input 2 : Value -* Output : None -* Return : None -*******************************************************************************/ -inline void GPIO_WordWrite(GPIO_TypeDef *GPIOx, u16 Port_Val) -{ - GPIOx->PD = Port_Val; -} - -#endif /* __gpio_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR71x_IAR/Library/include/pcu.h b/Demo/ARM7_STR71x_IAR/Library/include/pcu.h deleted file mode 100644 index b36296330..000000000 --- a/Demo/ARM7_STR71x_IAR/Library/include/pcu.h +++ /dev/null @@ -1,193 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : pcu.h -* Author : MCD Application Team -* Date First Issued : 30/05/2003 -* Description : This file contains all the functions prototypes for the -* PCU software library. -******************************************************************************** -* History: -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef __PCU_H -#define __PCU_H - -#include "71x_map.h" - -typedef enum -{ - PCU_WREN = 0x8000, - PCU_VROK = 0x1000 -} PCU_Flags; - -typedef enum -{ - PCU_STABLE, - PCU_UNSTABLE -} PCU_VR_Status; - -typedef enum -{ - PCU_MVR = 0x0008, - PCU_LPR = 0x0020 -} PCU_VR; - -typedef enum -{ - WFI_CLOCK2_16, - WFI_EXTERNAL -} WFI_CLOCKS; - -typedef enum -{ - PCU_SLOW, - PCU_STOP, - PCU_STANDBY -} LPM_MODES; - - -// VR_OK : Voltage Regulator OK -#define PCU_VROK_Mask 0x1000 - -// Main Voltage Regulator -#define PCU_MVR_Mask 0x0008 - -// Low Power Voltage Regulator -#define PCU_LPR_Mask 0x0020 - -// PCU register Write Enable Bit -#define PCU_WREN_Mask 0x8000 - -// Low Voltage Detector -#define PCU_LVD_Mask 0x0100 - -// Power Down Flag -#define PCU_PWRDWN_Mask 0x0040 - -// WFI Mode Clock Selection Bit -#define PCU_WFI_CKSEL_Mask 0x00000002 - -// Halt Mode Enable Bit -#define PCU_EN_HALT_Mask 0x00000800 - -// Halt Mode Flag -#define PCU_HALT_Mask 0x0002 - -// Stop Mode Enable Bit -#define PCU_STOP_EN_Mask 0x00000400 - -// Low Power Regulator in Wait For interrupt Mode -#define PCU_LPRWFI_Mask 0x0020 - -// Low Power Mode in Wait For interrupt Mode -#define PCU_LPOWFI_Mask 0x00000001 - -// Software Reset Enable -#define PCU_SRESEN_Mask 0x00000001 - - -/******************************************************************************* -* Function Name : PCU_MVRStatus -* Description : This routine is used to check the Main Voltage Regulator -* : NewState. -* Input : None -* Return : STABLE, UNSTABLE -*******************************************************************************/ -inline PCU_VR_Status PCU_MVRStatus ( void ) -{ - return (PCU->PWRCR & PCU_VROK_Mask) == 0x00 ? PCU_UNSTABLE : PCU_STABLE; -} - -/******************************************************************************* -* Function Name : PCU_FlagStatus -* Description : This routine is used to return the PCU register flag -* Input 1 : The flag to get -* Return : RESET, SET -*******************************************************************************/ -inline FlagStatus PCU_FlagStatus ( PCU_Flags Xflag ) -{ - return ( PCU->PWRCR & Xflag ) == 0x00 ? RESET : SET; -} - -/******************************************************************************* -* Function Name : PCU_VRConfig -* Description : This routine is used to configure PCU voltage regultors -* Input 1 : MVR : Main voltage Regulator - LPR : Low Power Regulator -* Input 2 : ENABLE : Enable the Voltage Regulator - DISABLE: Disable ( ByPass ) the VR -* Return : None -*******************************************************************************/ -void PCU_VRConfig ( PCU_VR xVR, FunctionalState NewState ); - -/******************************************************************************* -* Function Name : PCU_VRStatus -* Description : This routine is used to get the PCU voltage regultors status -* Input : MVR : Main voltage Regulator - LPR : Low Power Regulator -* Return : ENABLE : Enable the Voltage Regulator - DISABLE: Disable ( ByPass ) the VR -*******************************************************************************/ -inline FunctionalState PCU_VRStatus ( PCU_VR xVR ) -{ - return ( PCU->PWRCR & xVR ) == 0 ? ENABLE : DISABLE; -} - -/******************************************************************************* -* Function Name : PCU_LVDDisable -* Description : This routine is used to disable the Low Voltage Detector. -* Input : None -* Return : None -*******************************************************************************/ -inline void PCU_LVDDisable ( void ) -{ - PCU->PWRCR |= PCU_WREN_Mask; // Unlock Power Control Register - PCU->PWRCR |= PCU_LVD_Mask; // Set the LVD DIS Flag -} - -/******************************************************************************* -* Function Name : PCU_LVDStatus -* Description : This routine is used to get the LVD NewState. -* Input : None -* Return : ENABLE, DISABLE -*******************************************************************************/ -inline FunctionalState PCU_LVDStatus ( void ) -{ - return ( PCU->PWRCR & PCU_LVD_Mask ) == 0 ? ENABLE : DISABLE; -} - -/******************************************************************************* -* Function Name : PCU_WFIEnter -* Description : This routine is used to force the Device to enter in WFI mode -* Input 1 : CLOCK2_16 : Clock2_16 as system clock for WFI mode -* EXTERNAL : external clock as system clock for WFI mode -* Input 2 : ENABLE : Enable Low Power Regulator during Wait For Interrupt Mode -* DISABLE: Disable Low Power Regulator during Wait For Interrupt Mode -* Input 3 : ENABLE : Enable Low Power Mode during Wait For Interrupt Mode -* DISABLE: Disable Low Power Mode during Wait For Interrupt Mode -* Return : None -*******************************************************************************/ -void PCU_WFIEnter ( WFI_CLOCKS Xclock, FunctionalState Xlpr, FunctionalState Xlpm ); - -/******************************************************************************* -* Function Name : PCU_LPMEnter -* Description : This routine is used to force the Device to enter low -* power mode -* Input : SLOW : Slow Mode - STOP : Stop Mode - HALT : Halt Mode -* Return : None -*******************************************************************************/ -void PCU_LPMEnter ( LPM_MODES Xmode); - -#endif // __PCU_H - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR71x_IAR/Library/include/rccu.h b/Demo/ARM7_STR71x_IAR/Library/include/rccu.h deleted file mode 100644 index 86c76130a..000000000 --- a/Demo/ARM7_STR71x_IAR/Library/include/rccu.h +++ /dev/null @@ -1,319 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : rccu.h -* Author : MCD Application Team -* Date First Issued : 28/07/2003 -* Description : This file contains all the functions prototypes for the -* RCCU software library. -******************************************************************************** -* History: -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#ifndef __RCCU_H -#define __RCCU_H - -#include "71x_map.h" - -typedef enum { - RCCU_DEFAULT=0x00, - RCCU_RCLK_2 =0x01, - RCCU_RCLK_4 =0x02, - RCCU_RCLK_8 =0x03 - } RCCU_Clock_Div; - -typedef enum { - RCCU_PLL1_Output, - RCCU_CLOCK2_16, - RCCU_CLOCK2, - RCCU_RTC_CLOCK - } RCCU_RCLK_Clocks; - - - typedef enum { - RCCU_PLL1_Mul_12=0x01, - RCCU_PLL1_Mul_16=0x03, - RCCU_PLL1_Mul_20=0x00, - RCCU_PLL1_Mul_24=0x02 - } RCCU_PLL1_Mul; - -typedef enum { - RCCU_PLL2_Mul_12=0x01, - RCCU_PLL2_Mul_16=0x03, - RCCU_PLL2_Mul_20=0x00, - RCCU_PLL2_Mul_28=0x02 - } RCCU_PLL2_Mul; - -typedef enum { - RCCU_Div_1=0x00, - RCCU_Div_2=0x01, - RCCU_Div_3=0x02, - RCCU_Div_4=0x03, - RCCU_Div_5=0x04, - RCCU_Div_6=0x05, - RCCU_Div_7=0x06 - } RCCU_PLL_Div; - -typedef enum { - RCCU_PLL2_Output = 0x01, - RCCU_USBCK = 0x00 - } RCCU_USB_Clocks; - -typedef enum { - RCCU_CLK2, - RCCU_RCLK, - RCCU_MCLK, - RCCU_PCLK, - RCCU_FCLK - } RCCU_Clocks; - -typedef enum { - RCCU_PLL1_LOCK_IT = 0x0080, - RCCU_CKAF_IT = 0x0100, - RCCU_CK2_16_IT = 0x0200, - RCCU_STOP_IT = 0x0400 - } RCCU_Interrupts; - -typedef enum { - RCCU_PLL1_LOCK = 0x0002, - RCCU_CKAF_ST = 0x0004, - RCCU_PLL1_LOCK_I = 0x0800, - RCCU_CKAF_I = 0x1000, - RCCU_CK2_16_I = 0x2000, - RCCU_STOP_I = 0x4000 - } RCCU_Flags; - -typedef enum { - RCCU_ExternalReset = 0x00000000, - RCCU_SoftwareReset = 0x00000020, - RCCU_WDGReset = 0x00000040, - RCCU_RTCAlarmReset = 0x00000080, - RCCU_LVDReset = 0x00000200, - RCCU_WKPReset = 0x00000400 - }RCCU_ResetSources; - - -#define RCCU_Div2_Mask 0x00008000 -#define RCCU_Div2_Index 0x0F -#define RCCU_FACT_Mask 0x0003 - -#define RCCU_FACT1_Mask 0x0003 - -#define RCCU_FACT2_Mask 0x0300 -#define RCCU_FACT2_Index 0x08 - -#define RCCU_MX_Mask 0x00000030 -#define RCCU_MX_Index 0x04 - -#define RCCU_DX_Mask 0x00000007 - -#define RCCU_FREEN_Mask 0x00000080 - -#define RCCU_CSU_CKSEL_Mask 0x00000001 - -#define RCCU_CK2_16_Mask 0x00000008 - -#define RCCU_CKAF_SEL_Mask 0x00000004 - -#define RCCU_LOCK_Mask 0x00000002 - -#define RCCU_USBEN_Mask 0x0100 -#define RCCU_USBEN_Index 0x08 -#define RCCU_ResetSources_Mask 0x000006E0 - -// RTC Oscillator Frequency value = 32 768 Hz -#define RCCU_RTC_Osc 32768 - - -/******************************************************************************* -* Function Name : RCCU_Div2Config -* Description : Enables/Disables the clock division by two -* Input : NewState : ENABLE or DISABLE -* Return : None -*******************************************************************************/ -inline void RCCU_Div2Config ( FunctionalState NewState ) -{ - if (NewState == ENABLE) RCCU->CFR |= RCCU_Div2_Mask; - else RCCU->CFR &= ~RCCU_Div2_Mask; -} - -/******************************************************************************* -* Function Name : RCCU_Div2Status -* Description : Gets the Div2 Flag status -* Input : None -* Input : FlagStatus -* Return : None -*******************************************************************************/ -inline FlagStatus RCCU_Div2Status ( void ) -{ - return (RCCU->CFR & RCCU_Div2_Mask) == 0 ? RESET : SET; -} - -/******************************************************************************* -* Function Name : RCCU_MCLKConfig -* Description : Selects the division factor for RCLK to obtain the -* MCLK clock for the CPU -* Input : New_Clock : RCCU_DEFAULT, RCCU_RCLK_2, RCCU_RCLK_4, RCCU_RCLK_8 -* Return : None -*******************************************************************************/ -inline void RCCU_MCLKConfig ( RCCU_Clock_Div New_Clock ) -{ - PCU->MDIVR = ( PCU->MDIVR & ~RCCU_FACT_Mask ) | New_Clock; -} - -/******************************************************************************* -* Function Name : RCCU_FCLKConfig -* Description : Selects the division factor for RCLK to obtain the -* FCLK clock for the APB1 fast peripherals (PCLK1). -* Input : New_Clock : RCCU_DEFAULT, RCCU_RCLK_2, -* RCCU_RCLK_4, RCCU_RCLK_8 -* Return : None -*******************************************************************************/ -inline void RCCU_FCLKConfig ( RCCU_Clock_Div New_Clock ) -{ - PCU->PDIVR = ( PCU->PDIVR & ~RCCU_FACT1_Mask ) | New_Clock; -} - -/******************************************************************************* -* Function Name : RCCU_PCLKConfig -* Description : Selects the division factor for RCLK to obtain the -* PCLK clock for the APB2 peripherals (PCLK2). -* Input : New_Clock : RCCU_DEFAULT, RCCU_RCLK_2, -* RCCU_RCLK_4, RCCU_RCLK_8 -* Return : None -*******************************************************************************/ -inline void RCCU_PCLKConfig ( RCCU_Clock_Div New_Clock ) -{ - PCU->PDIVR =(PCU->PDIVR & ~RCCU_FACT2_Mask)|(New_Clock << RCCU_FACT2_Index); -} - -/******************************************************************************* -* Function Name : RCCU_PLL1Config -* Description : Configures the PLL1 div & mul factors. -* Input : New_Mul : RCCU_Mul_12, RCCU_Mul_16, RCCU_Mul_20, RCCU_Mul_28 -* : New_Div : RCCU_Div_1, RCCU_Div_2, RCCU_Div_3, -* RCCU_Div_4, RCCU_Div_5, RCCU_Div_6, RCCU_Div_7 -* Return : None -*******************************************************************************/ -void RCCU_PLL1Config ( RCCU_PLL1_Mul New_Mul, RCCU_PLL_Div New_Div ); - -/******************************************************************************* -* Function Name : RCCU_PLL2Config -* Description : Configures the PLL2 div & mul factors. -* Input : New_Mul : RCCU_Mul_12, RCCU_Mul_16, RCCU_Mul_20, RCCU_Mul_28 -* : New_Div : RCCU_Div_1, RCCU_Div_2, RCCU_Div_3, RCCU_Div_4, -* RCCU_Div_5, RCCU_Div_6, RCCU_Div_7 -* Return : None -*******************************************************************************/ -void RCCU_PLL2Config ( RCCU_PLL2_Mul New_Mul, RCCU_PLL_Div New_Div ); - -/******************************************************************************* -* Function Name : RCCU_RCLKSourceConfig -* Description : Selects the RCLK source clock -* Input : New_Clock : RCCU_PLL1_OutPut, RCCU_CLOCK2_16, RCCU_CLOCK2 -* Return : None -*******************************************************************************/ -void RCCU_RCLKSourceConfig ( RCCU_RCLK_Clocks New_Clock ); - -/******************************************************************************* -* Function Name : RCCU_RCLKClockSource -* Description : Returns the current RCLK source clock -* Input : None -* Return : RCCU_PLL1_Output, RCCU_CLOCK2_16, RCCU_CLOCK2 -*******************************************************************************/ -RCCU_RCLK_Clocks RCCU_RCLKClockSource ( void ); - -/******************************************************************************* -* Function Name : RCCU_USBCLKConfig -* Description : Selects the USB source clock -* Input : New_Clock : RCCU_PLL2_Output, RCCU_USBCK -* Return : None -*******************************************************************************/ -inline void RCCU_USBCLKConfig ( RCCU_USB_Clocks New_Clock ) -{ - PCU->PLL2CR = (PCU->PLL2CR & ~RCCU_USBEN_Mask)|(New_Clock << RCCU_USBEN_Index); -} - -/******************************************************************************* -* Function Name : RCCU_USBClockSource -* Description : Gets the USB source clock -* Input : None -* Return : RCCU_USB_Clocks -*******************************************************************************/ -RCCU_USB_Clocks RCCU_USBClockSource ( void ); - -/******************************************************************************* -* Function Name : RCCU_FrequencyValue -* Description : Calculates & Returns any internal RCCU clock freuqency -* passed in parametres -* Input : RCCU_Clocks : RCCU_CLK2, RCCU_RCLK, RCCU_MCLK, -* RCCU_PCLK, RCCU_FCLK -* Return : u32 -*******************************************************************************/ -u32 RCCU_FrequencyValue ( RCCU_Clocks Internal_Clk ); - -/******************************************************************************* -* Function Name : RCCU_ITConfig -* Description : Configures the RCCU interrupts -* Input : RCCU interrupts : RCCU_CK2_16_IT, RCCU_CKAF_IT, -* RCCU_PLL1_LOCK_IT -* Return : None -*******************************************************************************/ -inline void RCCU_ITConfig ( RCCU_Interrupts RCCU_IT, FunctionalState NewState) -{ - if (NewState == ENABLE) RCCU->CCR |= RCCU_IT; else RCCU->CCR &= ~RCCU_IT; -} - -/******************************************************************************* -* Function Name : RCCU_FlagStatus -* Description : Checks the RCCU clock flag register status -* Input : RCCU Flags : RCCU_CK2_16, RCCU_CKAF, RCCU_PLL1_LOCK -* Return : FlagStatus : SET or RESET -*******************************************************************************/ -inline FlagStatus RCCU_FlagStatus ( RCCU_Flags RCCU_flag ) -{ - return (RCCU->CFR & RCCU_flag) == 0 ? RESET : SET; -} - -/******************************************************************************* -* Function Name : RCCU_FlagClear -* Description : Clears a specified flag in the RCCU registers -* Input : RCCU Flags : RCCU_CK2_16, RCCU_CKAF, RCCU_PLL1_LOCK -* Return : None -*******************************************************************************/ -inline void RCCU_FlagClear ( RCCU_Interrupts RCCU_IT ) -{ - RCCU->CFR |= RCCU_IT; -} - -/******************************************************************************* -* Function Name : RCCU_ResetSources -* Description : Return the source of the system reset -* Input : None -* Return : The reset source -*******************************************************************************/ -inline RCCU_ResetSources RCCU_ResetSource () -{ - - switch(RCCU->CFR & RCCU_ResetSources_Mask) - { - case 0x00000020: return RCCU_SoftwareReset; - case 0x00000040: return RCCU_WDGReset; - case 0x00000080: return RCCU_RTCAlarmReset; - case 0x00000200: return RCCU_LVDReset; - case 0x00000400: return RCCU_WKPReset; - default : return RCCU_ExternalReset; - } -} - -#endif // __RCCU_H - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR71x_IAR/Library/include/tim.h b/Demo/ARM7_STR71x_IAR/Library/include/tim.h deleted file mode 100644 index fbb3ff080..000000000 --- a/Demo/ARM7_STR71x_IAR/Library/include/tim.h +++ /dev/null @@ -1,345 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : tim.h -* Author : MCD Application Team -* Date First Issued : 08/09/2003 -* Description : This file contains all the functions prototypes for the -* TIM software library. -******************************************************************************** -* History: -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#ifndef __TIM_H -#define __TIM_H - -#include "71x_map.h" - -typedef enum { TIM_EXTERNAL, - TIM_INTERNAL - } TIM_Clocks; - -typedef enum { TIM_RISING, - TIM_FALLING - } TIM_Clock_Edges; - -typedef enum { TIM_CHANNEL_A, - TIM_CHANNEL_B - } TIM_Channels; - -typedef enum { TIM_WITH_IT, - TIM_WITHOUT_IT - } TIM_IT_Mode; - -typedef enum { TIM_TIMING, - TIM_WAVE - } TIM_OC_Modes; - -typedef enum { TIM_HIGH, - TIM_LOW - } TIM_Logic_Levels; - -typedef enum { TIM_START, - TIM_STOP, - TIM_CLEAR - } TIM_CounterOperations; - -typedef enum { TIM_ICFA = 0x8000, - TIM_OCFA = 0x4000, - TIM_TOF = 0x2000, - TIM_ICFB = 0x1000, - TIM_OCFB = 0x0800 - } TIM_Flags; - -typedef struct { u16 Pulse; - u16 Period; - } PWMI_parameters; - -#define TIM_ECKEN_Mask 0x0001 -#define TIM_EXEDG_Mask 0x0002 - -#define TIM_IEDGA_Mask 0x0004 -#define TIM_IEDGB_Mask 0x0008 - -#define TIM_PWM_Mask 0x0010 - -#define TIM_OMP_Mask 0x0020 - -#define TIM_OCAE_Mask 0x0040 -#define TIM_OCBE_Mask 0x0080 - -#define TIM_OLVLA_Mask 0x0100 -#define TIM_OLVLB_Mask 0x0200 - -#define TIM_FOLVA_Mask 0x0400 -#define TIM_FOLVB_Mask 0x0800 - -#define TIM_PWMI_Mask 0x4000 - -#define TIM_EN_Mask 0x8000 - -#define TIM_OCBIE_mask 0x0800 -#define TIM_ICBIE_Mask 0x1000 -#define TIM_TOE_Mask 0x2000 -#define TIM_ICAIE_Mask 0x8000 -#define TIM_OCAIE_mask 0x4000 - -#define TIM_ICA_IT 0x8000 // Input Capture Channel A -#define TIM_OCA_IT 0x4000 // Output Compare Channel A -#define TIM_TO_IT 0x2000 // Timer OverFlow -#define TIM_ICB_IT 0x1000 // Input Capture Channel B -#define TIM_OCB_IT 0x0800 // Input Capture Channel A - - -/******************************************************************************* -* Function Name : TIM_Init -* Description : This routine is used to Initialize the TIM peripheral -* Input : TIM Timer to Initialize -* Return : None -*******************************************************************************/ -void TIM_Init( TIM_TypeDef *TIMx ); - -/******************************************************************************* -* Function Name : TIM_ClockSourceConfig -* Description : This routine is used to configure the TIM clock source -* Input : (1) TIM Timer -* : (2) TIM_Clocks : Specifies the TIM source clock -* - TIM_INTERNAL : The TIM is clocked by the APB2 frequency -* divided by the prescaler value. -* - TIM_EXTERNAL : The TIM is clocked by an external Clock -* Return : None -*******************************************************************************/ -inline void TIM_ClockSourceConfig ( TIM_TypeDef *TIMx, TIM_Clocks Xclock ) -{ - if (Xclock==TIM_EXTERNAL) TIMx->CR1|=TIM_ECKEN_Mask; else TIMx->CR1&=~TIM_ECKEN_Mask; -} - -/******************************************************************************* -* Function Name : TIM_ClockSourceValue -* Description : This routine is used to get the TIM clock source -* Input : TIM Timer -* Return : TIM_Clocks : Specifies the TIM source clock -* - TIM_INTERNAL : The TIM is clocked by the APB2 frequency -* divided by the prescaler value. -* - TIM_EXTERNAL : The TIM is clocked by an external Clock -*******************************************************************************/ -inline TIM_Clocks TIM_ClockSourceValue ( TIM_TypeDef *TIMx ) -{ - return ( TIMx->CR1 & TIM_ECKEN_Mask) == 0 ? TIM_INTERNAL : TIM_EXTERNAL; -} - -/******************************************************************************* -* Function Name : TIM_PrescalerConfig -* Description : This routine is used to configure the TIM prescaler value -* ( using an internal clock ) -* Input : (1) TIM Timer -* : (2) Prescaler ( u8 ) -* Return : None -*******************************************************************************/ -inline void TIM_PrescalerConfig ( TIM_TypeDef *TIMx, u8 Xprescaler ) -{ - TIMx->CR2 = ( TIMx->CR2 & 0xFF00 ) | Xprescaler; -} - -/******************************************************************************* -* Function Name : TIM_PrescalerValue -* Description : This routine is used to get the TIM prescaler value -* ( when using using an internal clock ) -* Input : TIM Timer -* Return : Prescaler ( u8 ) -*******************************************************************************/ -inline u8 TIM_PrescalerValue ( TIM_TypeDef *TIMx ) -{ - return TIMx->CR2 & 0x00FF; -} - -/******************************************************************************* -* Function Name : TIM_ClockLevelConfig -* Description : This routine is used to configure the TIM clock level -* ( using an external clock ) -* Input : TIM Timer -* : TIM_Clock_Edges : Specifies the active adge of the external clock -* - TIM_RISING : The rising edge -* - TIM_FALLING : The falling edge -* Return : None -*******************************************************************************/ -inline void TIM_ClockLevelConfig ( TIM_TypeDef *TIMx, TIM_Clock_Edges Xedge ) -{ - if (Xedge == TIM_RISING) TIMx->CR1 |= TIM_EXEDG_Mask; else TIMx->CR1 &= ~TIM_EXEDG_Mask; -} - -/******************************************************************************* -* Function Name : TIM_ClockLevelValue -* Description : This routine is used to get the TIM clock level -* Input : TIM Timer -* Output : TIM_Clock_Edges : Specifies the active adge of the external clock -* - TIM_RISING : The rising edge -* - TIM_FALLING : The falling edge -*******************************************************************************/ -inline TIM_Clock_Edges TIM_ClockLevelValue ( TIM_TypeDef *TIMx ) -{ - return ( TIMx->CR1 & TIM_EXEDG_Mask ) == 0 ? TIM_FALLING : TIM_RISING; -} - -/******************************************************************************* -* Function Name : TIM_ICAPModeConfig -* Description : This routine is used to configure the input capture feature -* Input : (1) TIM Timer -* : (2) Input Capture Channel ( Channel_A or Channel_B ) -* : (3) Active Edge : Rising edge or Falling edge. -* Output : None -*******************************************************************************/ -void TIM_ICAPModeConfig ( TIM_TypeDef *TIMx, - TIM_Channels Xchannel, - TIM_Clock_Edges Xedge ); - -/******************************************************************************* -* Function Name : TIM_ICAPValue -* Description : This routine is used to get the Input Capture value -* Input : (1) TIM Timer -* : (2) Input Capture Channel ( Channel_A or Channel_B ) -* Output : None -*******************************************************************************/ -inline u16 TIM_ICAPValue ( TIM_TypeDef *TIMx, TIM_Channels Xchannel ) -{ - return Xchannel == TIM_CHANNEL_A ? TIMx->ICAR : TIMx->ICBR; -} - -/******************************************************************************* -* Function Name : TIM_OCMPModeConfig -* Description : This routine is used to configure the output compare feature -* Input : (1) TIM Timer -* : (2) OCMP Channel ( Channel_A or Channel_B ) -* : (3) Pulse Length -* : (4) OC_Mode : output wave, or only timing. -* : (5) Level : Rising edge or Falling edge after the == -* Output : None -*******************************************************************************/ -void TIM_OCMPModeConfig ( TIM_TypeDef *TIMx, - TIM_Channels Xchannel, - u16 XpulseLength, - TIM_OC_Modes Xmode, - TIM_Logic_Levels Xlevel ); - -/******************************************************************************* -* Function Name : TIM_OPModeConfig -* Description : This routine is used to configure the one pulse mode -* Input : (1) TIM Timer -* : (3) XpulseLength : Length of the pulse -* : (4) Level1 : Level during the pulse -* : (5) Level2 : Level after the pulse -* : (6) Activation Edge : High or Low on ICAP A -* Output : None -*******************************************************************************/ -void TIM_OPModeConfig ( TIM_TypeDef *TIMx, - u16 XpulseLength, - TIM_Logic_Levels XLevel1, - TIM_Logic_Levels XLevel2, - TIM_Clock_Edges Xedge ); - -/******************************************************************************* -* Function Name : TIM_PWMOModeConfig -* Description : This routine is used to configure the PWM in output mode -* Input : (1) TIM Timer -* : (2) DutyCycle : u16 -* : (3) Level 1 : During the Duty Cycle -* : (4) Level 2 : During the after the pulse -* : (5) Full period : u16 -* Output : None -*******************************************************************************/ -void TIM_PWMOModeConfig ( TIM_TypeDef *TIMx, - u16 XDutyCycle, - TIM_Logic_Levels XLevel1, - u16 XFullperiod, - TIM_Logic_Levels XLevel2 - ); - -/******************************************************************************* -* Function Name : TIM_PWMInputConfig -* Description : This routine is used to configure the PWM in input mode -* Input : (1) TIM Timer -* : (2) First Activation Edge -* Output : None -*******************************************************************************/ -void TIM_PWMIModeConfig ( TIM_TypeDef *TIMx, TIM_Clock_Edges Xedge ); - -/******************************************************************************* -* Function Name : TIM_PWMIValue -* Description : This routine is used to get the PWMI values -* Input : (1) TIM Timer -* Output : PWMI_parameters : - u16 Dyty cycle - - u16 Full period -*******************************************************************************/ -PWMI_parameters TIM_PWMIValue (TIM_TypeDef *TIMx ); - -/******************************************************************************* -* Function Name : TIM_CounterConfig -* Description : This routine is used to start/stop and clear the selected -* timer counter -* Input : (1) TIM Timer -* : (2) TIM_CounterOperations - TIM_START Enables or resumes the counter -* TIM_STOP Stops the TIM counter -* TIM_CLEAR Set the TIM counter value to FFFCh -* Output : None -*******************************************************************************/ -void TIM_CounterConfig ( TIM_TypeDef *TIMx, TIM_CounterOperations Xoperation ); - -/******************************************************************************* -* Function Name : TIM_ITConfig -* Description : This routine is used to configure the TIM IT -* Input : (1) TIM Timer -* : (2) TIM interrupt -* : (2) ENABLE / DISABLE -* Output : None -*******************************************************************************/ -inline void TIM_ITConfig ( TIM_TypeDef *TIMx, u16 New_IT, FunctionalState NewState ) -{ - if (NewState == ENABLE) TIMx->CR2 |= New_IT; else TIMx->CR2 &= ~New_IT; -} - -/******************************************************************************* -* Function Name : TIM_FlagStatus -* Description : This routine is used to check whether a Flag is Set. -* Input : (1) TIM Timer -* : (2) The TIM FLag -* Output : Flag NewState -*******************************************************************************/ -inline FlagStatus TIM_FlagStatus ( TIM_TypeDef *TIMx, TIM_Flags Xflag ) -{ - return (TIMx->SR & Xflag) == 0 ? RESET : SET; -} - -/******************************************************************************* -* Function Name : TIM_FlagClear -* Description : This routine is used to clear Flags. -* Input : (1) TIM Timer -* : (2) The TIM FLag -* Output : None -*******************************************************************************/ -inline void TIM_FlagClear ( TIM_TypeDef *TIMx, TIM_Flags Xflag ) -{ - TIMx->SR &= ~Xflag; -} - -/******************************************************************************* -* Function Name : TIM_CounterValue -* Description : This routine returns the timer counter value. -* Input : TIM Timer -* Output : The counter value -*******************************************************************************/ -inline u16 TIM_CounterValue(TIM_TypeDef *TIMx) -{ - return TIMx->CNTR; -} -#endif // __TIM_H - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR71x_IAR/Library/include/uart.h b/Demo/ARM7_STR71x_IAR/Library/include/uart.h deleted file mode 100644 index 7ca40bc4e..000000000 --- a/Demo/ARM7_STR71x_IAR/Library/include/uart.h +++ /dev/null @@ -1,390 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : uart.h -* Author : MCD Application Team -* Date First Issued : 16/05/2003 -* Description : This file contains all the functions prototypes for the -* UART software library. -******************************************************************************** -* History: -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef _UART_H -#define _UART_H - -#include "71x_map.h" -#include "rccu.h" - -typedef enum -{ - UART_RxFIFO, - UART_TxFIFO -} UARTFIFO_TypeDef; - -typedef enum -{ - UART_EVEN_PARITY = 0x0000, - UART_ODD_PARITY = 0x0020, - UART_NO_PARITY -} UARTParity_TypeDef; - -typedef enum -{ - UART_0_5_StopBits = 0x00, - UART_1_StopBits = 0x08, - UART_1_5_StopBits = 0x10, - UART_2_StopBits = 0x18 -} UARTStopBits_TypeDef; - -typedef enum -{ - UARTM_8D = 0x01, - UARTM_7D_P = 0x03, - UARTM_9D = 0x04, - UARTM_8D_W = 0x05, - UARTM_8D_P = 0x07 -} UARTMode_TypeDef; - - -#define DUMMY 0 - -// UART flags definition -#define UART_TxFull 0x0200 -#define UART_RxHalfFull 0x0100 -#define UART_TimeOutIdle 0x0080 -#define UART_TimeOutNotEmpty 0x0040 -#define UART_OverrunError 0x0020 -#define UART_FrameError 0x0010 -#define UART_ParityError 0x0008 -#define UART_TxHalfEmpty 0x0004 -#define UART_TxEmpty 0x0002 -#define UART_RxBufFull 0x0001 - -// CR regiter bit definition -#define UART_FIFOEnableBit 10 -#define UART_RxEnableBit 8 -#define UART_RunBit 7 -#define UART_LoopBackBit 6 -#define UART_ParityOddBit 5 -#define UART_StopBits 3 - -// Stop bits definition -#define UART_05StopBits 0x00 -#define UART_1StopBit (0x01<<3) -#define UART_15StopBits (0x02<<3) -#define UART_2StopBits (0x03<<3) - -// Modes definition -#define UART_8BitsData 0x01 -#define UART_7BitsData 0x03 -#define UART_9BitsData 0x04 -#define UART_8BitsDataWakeUp 0x05 -#define UART_8BitsDataParity 0x07 - -/******************************************************************************* -* Function Name : UART_Init -* Description : This function initializes the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Output : None -* Return : None -*******************************************************************************/ -void UART_Init(UART_TypeDef *UARTx); - -/******************************************************************************* -* Function Name : UART_ModeConfig -* Description : This function configures the mode of the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : The UART mode -* Output : None -* Return : None -*******************************************************************************/ -inline void UART_ModeConfig(UART_TypeDef *UARTx, UARTMode_TypeDef UART_Mode) -{ - UARTx->CR = (UARTx->CR&0xFFF8)|(u16)UART_Mode; -} - -/******************************************************************************* -* Function Name : UART_BaudRateConfig -* Description : This function configures the baud rate of the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : The baudrate value -* Output : None -* Return : None -*******************************************************************************/ -void UART_BaudRateConfig(UART_TypeDef *UARTx, u32 BaudRate); - -/******************************************************************************* -* Function Name : UART_ParityConfig -* Description : This function configures the data parity of the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : The parity type -* Output : None -* Return : None -*******************************************************************************/ -inline void UART_ParityConfig(UART_TypeDef *UARTx, UARTParity_TypeDef Parity) -{ - UARTx->CR = (UARTx->CR&0xFFDF)|(u16)Parity; -} - -/******************************************************************************* -* Function Name : UART_StopBitsConfig -* Description : This function configures the number of stop bits of the -* selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : The number of stop bits -* Output : None -* Return : None -*******************************************************************************/ -inline void UART_StopBitsConfig(UART_TypeDef *UARTx, UARTStopBits_TypeDef StopBits) -{ - UARTx->CR = (UARTx->CR&0xFFE7)|(u16)StopBits; -} - -/******************************************************************************* -* Function Name : UART_Config -* Description : This function configures the baudrate, the mode, the data -* parity and the number of stop bits of the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : The baudrate value -* Input 3 : The parity type -* Input 4 : The number of stop bits -* Input 5 : The UART mode -* Output : None -* Return : None -*******************************************************************************/ -void UART_Config(UART_TypeDef *UARTx, u32 BaudRate, UARTParity_TypeDef Parity, - UARTStopBits_TypeDef StopBits, UARTMode_TypeDef Mode); - -/******************************************************************************* -* Function Name : UART_ItConfig -* Description : This function enables or disables the interrupts of the -* selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : The new interrupt flag -* Input 3 : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void UART_ItConfig(UART_TypeDef *UARTx, u16 UART_Flag, FunctionalState NewState); - -/******************************************************************************* -* Function Name : UART_FifoConfig -* Description : This function enables or disables the Rx and Tx FIFOs of -* the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void UART_FifoConfig(UART_TypeDef *UARTx, FunctionalState NewState); - -/******************************************************************************* -* Function Name : UART_FifoReset -* Description : This function resets the Rx and the Tx FIFOs of the -* selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : RxFIFO or TxFIFO -* Output : None -* Return : None -*******************************************************************************/ -void UART_FifoReset(UART_TypeDef *UARTx, UARTFIFO_TypeDef FIFO); - -/******************************************************************************* -* Function Name : UART_LoopBackConfig -* Description : This function enables or disables the loop back mode of -* the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void UART_LoopBackConfig(UART_TypeDef *UARTx, FunctionalState NewState); - -/******************************************************************************* -* Function Name : UART_TimeOutPeriodConfig -* Description : This function configure the Time Out Period. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : The time-out period value -* Output : None -* Return : None -*******************************************************************************/ -inline void UART_TimeOutPeriodConfig(UART_TypeDef *UARTx, u16 TimeOutPeriod) -{ - UARTx->TOR = TimeOutPeriod; -} - -/******************************************************************************* -* Function Name : UART_GuardTimeConfig -* Description : This function configure the Guard Time. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : The guard time value -* Output : None -* Return : None -*******************************************************************************/ -inline void UART_GuardTimeConfig(UART_TypeDef *UARTx, u16 GuardTime) -{ - UARTx->GTR = GuardTime; -} - -/******************************************************************************* -* Function Name : UART_RxConfig -* Description : This function enable and disable the UART data reception. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void UART_RxConfig(UART_TypeDef *UARTx, FunctionalState NewState); - -/******************************************************************************* -* Function Name : UART_OnOffConfig -* Description : This function sets On/Off the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void UART_OnOffConfig(UART_TypeDef *UARTx, FunctionalState NewState); - -/******************************************************************************* -* Function Name : UART_ByteSend -* Description : This function sends a data byte to the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the data byte to send -* Output : None -* Return : None -*******************************************************************************/ -void UART_ByteSend(UART_TypeDef *UARTx, u8 *Data); - -/******************************************************************************* -* Function Name : UART_9BitByteSend -* Description : This function sends a 9 bits data byte to the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the data to send -* Output : None -* Return : None -*******************************************************************************/ -void UART_9BitByteSend(UART_TypeDef *UARTx, u16 *Data); - -/******************************************************************************* -* Function Name : UART_DataSend -* Description : This function sends several data bytes to the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the data to send -* Input 3 : The data length in bytes -* Output : None -* Return : None -*******************************************************************************/ -void UART_DataSend(UART_TypeDef *UARTx, u8 *Data, u8 DataLength); - -/******************************************************************************* -* Function Name : UART_9BitDataSend -* Description : This function sends several 9 bits data bytes to the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the data to send -* Input 3 : The data length -* Output : None -* Return : None -*******************************************************************************/ -void UART_9BitDataSend(UART_TypeDef *UARTx, u16 *Data, u8 DataLength); - -/******************************************************************************* -* Function Name : UART_StringSend -* Description : This function sends a string to the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the string to send -* Output : None -* Return : None -*******************************************************************************/ -void UART_StringSend(UART_TypeDef *UARTx, u8 *String); - -/******************************************************************************* -* Function Name : UART_ByteReceive -* Description : This function gets a data byte from the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the buffer where the data will be stored -* Input 3 : The time-out period -* Output : The received data -* Return : The UARTx.SR register contents -*******************************************************************************/ -u16 UART_ByteReceive(UART_TypeDef *UARTx, u8 *Data, u8 TimeOut); - -/******************************************************************************* -* Function Name : UART_9BitByteReceive -* Description : This function gets a 9 bits data byte from the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the buffer where the data will be stored -* Input 3 : The time-out period value -* Output : The received data -* Return : The UARTx.SR register contents -*******************************************************************************/ -u16 UART_9BitByteReceive(UART_TypeDef *UARTx, u16 *Data, u8 TimeOut); - -/******************************************************************************* -* Function Name : UART_DataReceive -* Description : This function gets 8 bits data bytes from the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the buffer where the data will be stored -* Input 3 : The data length -* Input 4 : The time-out period value -* Output : The received data -* Return : The UARTx.SR register contents -*******************************************************************************/ -u16 UART_DataReceive(UART_TypeDef *UARTx, u8 *Data, u8 DataLength, u8 TimeOut); - -/******************************************************************************* -* Function Name : UART_9BitDataReceive -* Description : This function gets 9 bits data bytes from the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the buffer where the data will be stored -* Input 3 : The data length -* Input 4 : The time-out value -* Output : The received data -* Return : The UARTx.SR register contents -*******************************************************************************/ -u16 UART_9BitDataReceive(UART_TypeDef *UARTx, u16 *Data, u8 DataLength, u8 TimeOut); - -/******************************************************************************* -* Function Name : UART_StringReceive -* Description : This function gets 8 bits data bytes from the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the buffer where the string will be stored -* Output : None -* Return : None -*******************************************************************************/ -u16 UART_StringReceive(UART_TypeDef *UARTx, u8 *Data); - -/******************************************************************************* -* Function Name : UART_FlagStatus -* Description : This function gets the flags status of the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Output : None -* Return : None -*******************************************************************************/ -inline u16 UART_FlagStatus(UART_TypeDef *UARTx) -{ - return UARTx->SR; -} - -#ifdef USE_SERIAL_PORT -/******************************************************************************* -* Function Name : sendchar -* Description : This function sends a character to the selected UART. -* Input 1 : A pointer to the character to send. -* Output : None -* Return : None -*******************************************************************************/ -void sendchar( char *ch ); -#endif /* USE_SERIAL_PORT */ - -#endif /* _UART_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR71x_IAR/Library/include/wdg.h b/Demo/ARM7_STR71x_IAR/Library/include/wdg.h deleted file mode 100644 index 2a592ef79..000000000 --- a/Demo/ARM7_STR71x_IAR/Library/include/wdg.h +++ /dev/null @@ -1,129 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : wdg.h -* Author : MCD Application Team -* Date First Issued : 25/08/2003 -* Description : This file contains all the functions prototypes for the -* WDG software library. -******************************************************************************** -* History: -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef __WDG_H -#define __WDG_H - -#include "71x_map.h" -#include "rccu.h" - -/******************************************************************************* -* Function Name : WDG_Enable -* Description : Enable the Watchdog Mode -* Input : None -* Return : None -*******************************************************************************/ -inline void WDG_Enable ( void ) -{ - WDG->CR |= 0x01; -} - -/******************************************************************************* -* Function Name : WDG_CntRefresh -* Description : Refresh and update the WDG counter to avoid a system reset. -* Input : None -* Return : None -*******************************************************************************/ -inline void WDG_CntRefresh ( void ) -{ - //write the first value in the key register - WDG->KR = 0xA55A; - //write the consecutive value - WDG->KR = 0x5AA5; -} - -/******************************************************************************* -* Function Name : WDG_PrescalerConfig -* Description : Set the counter prescaler value. -* Divide the counter clock by (Prescaler + 1) -* Input : Prescaler data value (8 bit) -* Return : None -*******************************************************************************/ -inline void WDG_PrescalerConfig ( u8 Prescaler ) -{ - WDG->PR = Prescaler; -} - -/******************************************************************************* -* Function Name : WDG_CntReloadUpdate -* Description : Update the counter pre-load value. -* Input : Pre-load data value (16 bit) -* Return : None -*******************************************************************************/ -inline void WDG_CntReloadUpdate ( u16 PreLoadValue ) -{ - WDG->VR = PreLoadValue; -} - -/******************************************************************************* -* Function Name : WDG_PeriodValueConfig -* Description : Set the prescaler and counter reload value based on the -* time needed -* Input : Amount of time (us) needed, peripheral clock2 value -* Return : None -*******************************************************************************/ -void WDG_PeriodValueConfig ( u32 Time ); - -/******************************************************************************* -* Function Name : WDG_CntOnOffConfig -* Description : Start or stop the free auto-reload timer to countdown. -* Input : ENABLE or DISABLE -* Return : None -*******************************************************************************/ -inline void WDG_CntOnOffConfig ( FunctionalState NewState ) -{ - if (NewState == ENABLE) WDG->CR |= 0x0002; else WDG->CR &= ~0x0002; -} - -/******************************************************************************* -* Function Name : WDG_ECITConfig -* Description : Enable or Disable the end of count interrupt -* Input : ENABLE or DISABLE -* Return : None -*******************************************************************************/ -inline void WDG_ECITConfig (FunctionalState NewState) -{ - if (NewState == ENABLE) WDG->MR |= 0x0001; else WDG->MR &= ~0x0001; -} - -/******************************************************************************* -* Function Name : WDG_ECFlagClear -* Description : Clear the end of count flag -* Input : None -* Return : None -*******************************************************************************/ -inline void WDG_ECFlagClear ( void ) -{ - WDG->SR = 0x0000; -} - -/******************************************************************************* -* Function Name : WDG_ECStatus -* Description : Return the end of count status -* Input : None -* Return : NewState value -*******************************************************************************/ -inline u16 WDG_ECStatus ( void ) -{ - return WDG->SR; -} - -#endif // __WDG_H - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR71x_IAR/Library/rccu.c b/Demo/ARM7_STR71x_IAR/Library/rccu.c deleted file mode 100644 index 70e0aac1c..000000000 --- a/Demo/ARM7_STR71x_IAR/Library/rccu.c +++ /dev/null @@ -1,183 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : rccu.c -* Author : MCD Application Team -* Date First Issued : 07/28/2003 -* Description : This file provides all the RCCU software functions -******************************************************************************** -* History: -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#include "rccu.h" - -/******************************************************************************* -* Function Name : RCCU_PLL1Config -* Description : Configures the PLL1 div & mul factors. -* Input : New_Mul ( RCCU_PLL1_Mul_12, RCCU_PLL1_Mul_16, RCCU_PLL1_Mul_20, -* RCCU_PLL1_Mul_24 ) -* : New_Div ( RCCU_Div_1, RCCU_Div_2, RCCU_Div_3, RCCU_Div_4, -* RCCU_Div_5, RCCU_Div_6, RCCU_Div_7) -* Return : None -*******************************************************************************/ -void RCCU_PLL1Config ( RCCU_PLL1_Mul New_Mul, RCCU_PLL_Div New_Div ) -{ - u32 Tmp = ( RCCU->PLL1CR & ~RCCU_MX_Mask ) | ( New_Mul << RCCU_MX_Index ); - RCCU->PLL1CR = ( Tmp & ~RCCU_DX_Mask ) | New_Div | 0x40; -} - -/******************************************************************************* -* Function Name : RCCU_PLL2Config -* Description : Configures the PLL2 div & mul factors. -* Input : New_Mul ( RCCU_PLL2_Mul_12, RCCU_PLL2_Mul_16, RCCU_PLL2_Mul_20, -* RCCU_Mul_PLL2_28 ) -* : New_Div ( RCCU_Div_1, RCCU_Div_2, RCCU_Div_3, RCCU_Div_4, -* RCCU_Div_5, RCCU_Div_6, RCCU_Div_7) -* Return : None -*******************************************************************************/ -void RCCU_PLL2Config ( RCCU_PLL2_Mul New_Mul, RCCU_PLL_Div New_Div ) -{ - u32 Tmp = ( PCU->PLL2CR & ~RCCU_MX_Mask ) | ( New_Mul << RCCU_MX_Index ); - PCU->PLL2CR = ( Tmp & ~RCCU_DX_Mask ) | ( New_Div | RCCU_FREEN_Mask ); -} - -/******************************************************************************* -* Function Name : RCCU_RCLKSourceConfig -* Description : Selects the RCLK source clock -* Input : New_Clock ( RCCU_PLL1_Output, RCCU_CLOCK2_16, RCCU_CLOCK2 ) -* Return : None -*******************************************************************************/ -void RCCU_RCLKSourceConfig ( RCCU_RCLK_Clocks New_Clock ) -{ - switch ( New_Clock ) - { - case RCCU_CLOCK2 :{// Resets the CSU_Cksel bit in clk_flag - RCCU->CFR &= ~RCCU_CSU_CKSEL_Mask; - // Set the CK2_16 Bit in the CFR - RCCU->CFR |= RCCU_CK2_16_Mask; - // Deselect The CKAF - RCCU->CCR &= ~RCCU_CKAF_SEL_Mask; - // switch off the PLL1 - RCCU->PLL1CR=((RCCU->PLL1CR & ~RCCU_DX_Mask)\ - |0x00000003) & ~RCCU_FREEN_Mask; - break;} - case RCCU_CLOCK2_16 :{// ReSet the CK2_16 Bit in the CFR - RCCU->CFR &= ~RCCU_CK2_16_Mask; - // Deselect The CKAF - RCCU->CCR &= ~RCCU_CKAF_SEL_Mask; - // switch off the PLL1 - RCCU->PLL1CR=((RCCU->PLL1CR & ~RCCU_DX_Mask)\ - |0x00000003) & ~RCCU_FREEN_Mask; - break;} - case RCCU_PLL1_Output:{// Set the CK2_16 Bit in the CFR - RCCU->CFR = RCCU->CFR | RCCU_CK2_16_Mask; - // Waits the PLL1 to lock if DX bits are different from '111' - // If all DX bit are set the PLL lock flag in meaningless - if (( RCCU->PLL1CR & 0x0007 ) != 7) - while(!(RCCU->CFR & RCCU_LOCK_Mask)); - // Deselect The CKAF - RCCU->CCR &= ~RCCU_CKAF_SEL_Mask; - // Select The CSU_CKSEL - RCCU->CFR |= RCCU_CSU_CKSEL_Mask; - break;} - case RCCU_RTC_CLOCK : {RCCU->CCR |= 0x04; - break;} - } -} - -/******************************************************************************* -* Function Name : RCCU_RCLKClockSource -* Description : Returns the current RCLK source clock -* Input : None -* Return : RCCU_PLL1_Output, RCCU_CLOCK2_16, RCCU_CLOCK2, RCCU_RTC_CLOCK -*******************************************************************************/ -RCCU_RCLK_Clocks RCCU_RCLKClockSource ( void ) -{ - if ((RCCU->CCR & 0x04)==0x04) - return RCCU_RTC_CLOCK; - - else if ((RCCU->CFR & RCCU_CK2_16_Mask)==0) - return RCCU_CLOCK2_16; - - else if (RCCU->CFR & RCCU_CSU_CKSEL_Mask) - return RCCU_PLL1_Output; - - else - return RCCU_CLOCK2; -} - -/******************************************************************************* -* Function Name : RCCU_USBClockSource -* Description : Gets the RCLK source clock -* Input : None -* Return : RCCU_USB_Clocks ( RCCU_PLL2_Output, RCCU_USBCK ) -*******************************************************************************/ -RCCU_USB_Clocks RCCU_USBClockSource ( void ) -{ - if ((PCU->PLL2CR & RCCU_USBEN_Mask ) >> RCCU_USBEN_Index == 1 ) - return RCCU_PLL2_Output; - else return RCCU_USBCK; -} - -/******************************************************************************* -* Function Name : RCCU_FrequencyValue -* Description : Calculates & Returns any internal RCCU clock frequency -* passed in parametres -* Input : RCCU_Clocks ( RCCU_CLK2, RCCU_RCLK, RCCU_MCLK, RCCU_PCLK, RCCU_FCLK ) -* Return : u32 -*******************************************************************************/ -u32 RCCU_FrequencyValue ( RCCU_Clocks Internal_Clk ) -{ - u32 Tmp; - u8 Div, Mul; - RCCU_RCLK_Clocks CurrentRCLK; - - Tmp = ( RCCU_Div2Status() == SET )? RCCU_Main_Osc / 2 : RCCU_Main_Osc; - - if ( Internal_Clk == RCCU_CLK2 ) - { - Div = 1; - Mul = 1; - } - else - { CurrentRCLK = RCCU_RCLKClockSource (); - switch ( CurrentRCLK ){ - case RCCU_CLOCK2_16 : Div = 16; - Mul = 1; - break; - case RCCU_CLOCK2 : Div = 1; - Mul = 1; - break; - case RCCU_PLL1_Output :{Mul=(RCCU->PLL1CR & RCCU_MX_Mask ) >> RCCU_MX_Index; - switch ( Mul ) - {case 0: Mul = 20; break; - case 1: Mul = 12; break; - case 2: Mul = 28; break; - case 3: Mul = 16; break; - } - Div = ( RCCU->PLL1CR & RCCU_DX_Mask ) + 1; - break;} - case RCCU_RTC_CLOCK : Mul = 1; - Div = 1; - Tmp = RCCU_RTC_Osc; - break;}} - - switch ( Internal_Clk ){ - case RCCU_MCLK :{Div <<= PCU->MDIVR & RCCU_FACT_Mask; - break;} - case RCCU_PCLK :{Div <<=(PCU->PDIVR & RCCU_FACT2_Mask ) >> RCCU_FACT2_Index; - break;} - case RCCU_FCLK :{Div <<= PCU->PDIVR & 0x3; - break;}} - - return (Tmp * Mul) / Div; -} - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR71x_IAR/Library/uart.c b/Demo/ARM7_STR71x_IAR/Library/uart.c deleted file mode 100644 index c299345ca..000000000 --- a/Demo/ARM7_STR71x_IAR/Library/uart.c +++ /dev/null @@ -1,365 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : uart.c -* Author : MCD Application Team -* Date First Issued : 06/08/2003 -* Description : This file provides all the UART software functions -******************************************************************************** -* History: -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#include "uart.h" - -/******************************************************************************* -* Function Name : UART_Init -* Description : This function initializes the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Output : None -* Return : None -*******************************************************************************/ -void UART_Init(UART_TypeDef *UARTx) -{ - UARTx->IER = 0x00; - UARTx->CR = 0x00; - (void)UARTx->RxBUFR; - UARTx->RxRSTR = 0xFFFF; - UARTx->TxRSTR = 0xFFFF; -} - -/******************************************************************************* -* Function Name : UART_BaudRateConfig -* Description : This function configures the baud rate of the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : The baudrate value -* Output : None -* Return : None -*******************************************************************************/ -void UART_BaudRateConfig(UART_TypeDef *UARTx, u32 BaudRate) -{ - UARTx->BR = (u16)(RCCU_FrequencyValue(RCCU_FCLK)/(16*BaudRate)); -} - -/******************************************************************************* -* Function Name : UART_Config -* Description : This function configures the baudrate, the mode, the data -* parity and the number of stop bits of the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : The baudrate value -* Input 3 : The parity type -* Input 4 : The number of stop bits -* Input 5 : The UART mode -* Output : None -* Return : None -*******************************************************************************/ -void UART_Config(UART_TypeDef *UARTx, u32 BaudRate, UARTParity_TypeDef Parity, - UARTStopBits_TypeDef StopBits, UARTMode_TypeDef Mode) -{ - UART_ModeConfig(UARTx, Mode); - UART_BaudRateConfig(UARTx, BaudRate); - UART_ParityConfig(UARTx, Parity); - UART_StopBitsConfig(UARTx, StopBits); -} - -/******************************************************************************* -* Function Name : UART_ItConfig -* Description : This function enables or disables the interrupts of the -* selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : The new interrupt flag -* Input 3 : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void UART_ItConfig(UART_TypeDef *UARTx, u16 UART_Flag, FunctionalState NewState) -{ - if (NewState==ENABLE) UARTx->IER|=UART_Flag; else UARTx->IER&=~UART_Flag; -} - -/******************************************************************************* -* Function Name : UART_FifoConfig -* Description : This function enables or disables the Rx and Tx FIFOs of -* the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void UART_FifoConfig(UART_TypeDef *UARTx, FunctionalState NewState) -{ - if (NewState==ENABLE) UARTx->CR|=0x0400; else UARTx->CR&=~0x0400; -} - -/******************************************************************************* -* Function Name : UART_FifoReset -* Description : This function resets the Rx and the Tx FIFOs of the -* selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : UART_RxFIFO or UART_TxFIFO -* Output : None -* Return : None -*******************************************************************************/ -void UART_FifoReset(UART_TypeDef *UARTx, UARTFIFO_TypeDef FIFO) -{ - if (FIFO==UART_RxFIFO) UARTx->RxRSTR=0xFFFF; else UARTx->TxRSTR=0xFFFF; -} - -/******************************************************************************* -* Function Name : UART_LoopBackConfig -* Description : This function enables or disables the loop back mode of -* the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void UART_LoopBackConfig(UART_TypeDef *UARTx, FunctionalState NewState) -{ - if (NewState==ENABLE) UARTx->CR|=0x0040; else UARTx->CR&=~0x0040; -} - -/******************************************************************************* -* Function Name : UART_RxConfig -* Description : This function enables or disables the UART data reception. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void UART_RxConfig(UART_TypeDef *UARTx, FunctionalState NewState) -{ - if (NewState==ENABLE) UARTx->CR|=0x0100; else UARTx->CR&=~0x0100; -} - -/******************************************************************************* -* Function Name : UART_OnOffConfig -* Description : This function sets On/Off the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void UART_OnOffConfig(UART_TypeDef *UARTx, FunctionalState NewState) -{ - if (NewState==ENABLE) UARTx->CR|=0x0080; else UARTx->CR&=~0x0080; -} - -/******************************************************************************* -* Function Name : UART_ByteSend -* Description : This function sends a data byte to the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the data byte to send -* Output : None -* Return : None -*******************************************************************************/ -void UART_ByteSend(UART_TypeDef *UARTx, u8 *Data) -{ - if (UARTx->CR & (0x0001<SR & UART_TxFull)); // while the UART_TxFIFO contain 16 characters. - else // if FIFO DISABLED - while (!(UARTx->SR & UART_TxEmpty)); // while the transmit shift register not empty - UARTx->TxBUFR = *Data; -} - -/******************************************************************************* -* Function Name : UART_9BitByteSend -* Description : This function sends a 9 bits data byte to the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the data to send -* Output : None -* Return : None -*******************************************************************************/ -void UART_9BitByteSend(UART_TypeDef *UARTx, u16 *Data) -{ - if(UARTx->CR & (0x0001<SR & UART_TxFull)); // while the UART_TxFIFO contain 16 characters. - else // if FIFO DISABLED - while (!(UARTx->SR & UART_TxEmpty)); // while the transmit shift register not empty - UARTx->TxBUFR = *Data; -} - -/******************************************************************************* -* Function Name : UART_DataSend -* Description : This function sends several data bytes to the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the data to send -* Input 3 : The data length in bytes -* Output : None -* Return : None -*******************************************************************************/ -void UART_DataSend(UART_TypeDef *UARTx, u8 *Data, u8 DataLength) -{ - while(DataLength--) - { - UART_ByteSend(UARTx,Data); - Data++; - } -} - -/******************************************************************************* -* Function Name : UART_9BitDataSend -* Description : This function sends several 9 bits data bytes to the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the data to send -* Input 3 : The data length -* Output : None -* Return : None -*******************************************************************************/ -void UART_9BitDataSend(UART_TypeDef *UARTx, u16 *Data, u8 DataLength) -{ - while(DataLength--) - { - UART_9BitByteSend(UARTx,Data); - Data++; - } -} - -/******************************************************************************* -* Function Name : UART_StringSend -* Description : This function sends a string to the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the string to send -* Output : None -* Return : None -*******************************************************************************/ -void UART_StringSend(UART_TypeDef *UARTx, u8 *String) -{ - u8 *Data=String; - while(*Data != '\0') - UART_ByteSend(UARTx, Data++); - *Data='\0'; - UART_ByteSend(UARTx, Data); -} - -/******************************************************************************* -* Function Name : UART_ByteReceive -* Description : This function gets a data byte from the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the buffer where the data will be stored -* Input 3 : The time-out period -* Output : The received data -* Return : The UARTx.SR register contents -*******************************************************************************/ -u16 UART_ByteReceive(UART_TypeDef *UARTx, u8 *Data, u8 TimeOut) -{ - u16 wStatus; - UARTx->TOR=TimeOut;// reload the Timeout counter - while (!((wStatus=UARTx->SR) & (UART_TimeOutIdle|UART_RxHalfFull|UART_RxBufFull)));// while the UART_RxFIFO is empty and no Timeoutidle - *Data = (u8)UARTx->RxBUFR; // then read the Receive Buffer Register - return wStatus; -} - -/******************************************************************************* -* Function Name : UART_9BitByteReceive -* Description : This function gets a 9 bits data byte from the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the buffer where the data will be stored -* Input 3 : The time-out period value -* Output : The received data -* Return : The UARTx.SR register contents -*******************************************************************************/ -u16 UART_9BitByteReceive(UART_TypeDef *UARTx, u16 *Data, u8 TimeOut) -{ - u16 wStatus; - UARTx->TOR=TimeOut;// reload the Timeout counter - while (!((wStatus=UARTx->SR) & (UART_TimeOutIdle|UART_RxHalfFull|UART_RxBufFull)));// while the UART_RxFIFO is empty and no Timeoutidle - *Data = (u16)UARTx->RxBUFR; // then read the RxBUFR - return wStatus; -} - -/******************************************************************************* -* Function Name : UART_DataReceive -* Description : This function gets 8 bits data bytes from the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the buffer where the data will be stored -* Input 3 : The data length -* Input 4 : The time-out period value -* Output : The received data -* Return : The UARTx.SR register contents -*******************************************************************************/ -u16 UART_DataReceive(UART_TypeDef *UARTx, u8 *Data, u8 DataLength, u8 TimeOut) -{ - u16 wStatus; - while(DataLength--) - wStatus=UART_ByteReceive(UARTx,Data++,TimeOut); - return wStatus; -} - -/******************************************************************************* -* Function Name : UART_9BitDataReceive -* Description : This function gets 9 bits data bytes from the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the buffer where the data will be stored -* Input 3 : The data length -* Input 4 : The time-out value -* Output : The received data -* Return : The UARTx.SR register contents -*******************************************************************************/ -u16 UART_9BitDataReceive(UART_TypeDef *UARTx, u16 *Data, u8 DataLength, u8 TimeOut) -{ - u16 wStatus; - while(DataLength--) - wStatus=UART_9BitByteReceive(UARTx,Data++,TimeOut); - return wStatus; -} - -/******************************************************************************* -* Function Name : UART_StringReceive -* Description : This function gets 8 bits data bytes from the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the buffer where the string will be stored -* Output : The received string -* Return : The UARTx.SR register contents -*******************************************************************************/ -u16 UART_StringReceive(UART_TypeDef *UARTx, u8 *Data) -{ - u8 *pSTRING=Data; - u16 wStatus; - do - { - while (!((wStatus=UARTx->SR) & (UART_RxHalfFull|UART_RxBufFull)));// while the UART_RxFIFO is empty and no Timeoutidle - *(pSTRING++) = (u8)UARTx->RxBUFR; // then read the RxBUFR - } while((*(pSTRING - 1)!=0x0D)&(*(pSTRING - 1)!='\0')); - *(pSTRING - 1)='\0'; - return wStatus; -} - -#ifdef USE_SERIAL_PORT -/******************************************************************************* -* Function Name : sendchar -* Description : This function sends a character to the selected UART. -* Input 1 : A pointer to the character to send. -* Output : None -* Return : None -*******************************************************************************/ -void sendchar( char *ch ) -{ - #ifdef USE_UART0 - #define UARTx UART0 - #endif /* Use_UART0 */ - - #ifdef USE_UART1 - #define UARTx UART1 - #endif /* Use_UART1 */ - - #ifdef USE_UART2 - #define UARTx UART2 - #endif /* Use_UART2 */ - - #ifdef USE_UART3 - #define UARTx UART3 - #endif /* Use_UART3 */ - - UART_ByteSend(UARTx,(u8 *)ch); -} -#endif /* USE_SERIAL_PORT */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR71x_IAR/Library/wdg.c b/Demo/ARM7_STR71x_IAR/Library/wdg.c deleted file mode 100644 index efd656c49..000000000 --- a/Demo/ARM7_STR71x_IAR/Library/wdg.c +++ /dev/null @@ -1,83 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : WDG.c -* Author : MCD Application Team -* Date First Issued : 10/24/2003 -* Description : This file provides all the WDG software functions -******************************************************************************** -* History: -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#include "wdg.h" - -#ifndef abs - #define abs(x) ((x)>0 ? (x) : -(x)) -#endif - -/******************************************************************************* -* Function Name : FindFactors -* Description : Search for the best (a,b) values that fit n = a*b -* with the following constraints: 1<=a<=256, 1<=b<=65536 -* Input 1 : n: the number to decompose -* Input/Output 2 : a: a pointer to the first factor -* Input/Output 3 : b: a pointer to the second factor -* Return : None -*******************************************************************************/ -static void FindFactors(unsigned long n, unsigned int *a, unsigned long *b) -{ - unsigned long b0; - unsigned int a0; - long err, err_min=n; - - *a = a0 = ((n-1)/65536ul) + 1; - *b = b0 = n / *a; - - for (; *a <= 256; (*a)++) - { - *b = n / *a; - err = (long)*a * (long)*b - (long)n; - if (abs(err) > (*a / 2)) - { - (*b)++; - err = (long)*a * (long)*b - (long)n; - } - if (abs(err) < abs(err_min)) - { - err_min = err; - a0 = *a; - b0 = *b; - if (err == 0) break; - } - } - - *a = a0; - *b = b0; -} - -/******************************************************************************* -* Function Name : WDG_PeriodValueConfig -* Description : Set the prescaler and counter reload value -* Input : Amount of time (us) needed -* Return : None -*******************************************************************************/ -void WDG_PeriodValueConfig ( u32 Time ) -{ - unsigned int a; - unsigned long n, b; - - n = Time * (RCCU_FrequencyValue(RCCU_PCLK) / 1000000); - FindFactors(n, &a, &b); - WDG->PR = a - 1; - WDG->VR = b - 1; -} - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR71x_IAR/ParTest/ParTest.c b/Demo/ARM7_STR71x_IAR/ParTest/ParTest.c deleted file mode 100644 index 578b50745..000000000 --- a/Demo/ARM7_STR71x_IAR/ParTest/ParTest.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* Library includes. */ -#include "GPIO.h" - -/* Scheduler includes. */ -#include "FreeRTOS.h" - -/* Demo application includes. */ -#include "partest.h" - -/*----------------------------------------------------------- - * Simple parallel port IO routines for the LED's - which are - * connected to the second nibble of GPIO port 1. - *-----------------------------------------------------------*/ - -#define partstLED_3 0x0080 -#define partstLED_2 0x0040 -#define partstLED_1 0x0020 -#define partstLED_0 0x0010 -#define partstON_BOARD 0x0100 /* The LED built onto the KickStart board. */ - -#define partstALL_LEDs ( partstLED_0 | partstLED_1 | partstLED_2 | partstLED_3 | partstON_BOARD ) - -#define partstFIRST_LED_BIT 4 - -/* This demo application uses files that are common to all port demo -applications. These files assume 6 LED's are available, whereas I have -only 5 (including the LED built onto the development board). To prevent -two tasks trying to use the same LED a bit of remapping is performed. -The ComTest tasks will try and use LED's 6 and 7. LED 6 is ignored and -has no effect, LED 7 is mapped to LED3. The LED usage is described in -the port documentation available from the FreeRTOS.org WEB site. */ -#define partstCOM_TEST_LED 7 -#define partstRX_CHAR_LED 3 - -/*-----------------------------------------------------------*/ - -void vParTestInitialise( void ) -{ - /* Configure the bits used to flash LED's on port 1 as output. */ - GPIO_Config(GPIO1, partstALL_LEDs, GPIO_OUT_OD); -} -/*-----------------------------------------------------------*/ - -void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) -{ - if( uxLED == partstCOM_TEST_LED ) - { - /* Remap as described above. */ - uxLED = partstRX_CHAR_LED; - } - - /* Adjust the LED value to map to the port pins actually being used, - then write the required value to the port. */ - uxLED += partstFIRST_LED_BIT; - GPIO_BitWrite( GPIO1, uxLED, !xValue ); -} -/*-----------------------------------------------------------*/ - -void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) -{ - if( uxLED == partstCOM_TEST_LED ) - { - /* Remap as described above. */ - uxLED = partstRX_CHAR_LED; - } - - /* Adjust the LED value to map to the port pins actually being used, - then write the opposite value to the current state to the port pin. */ - uxLED += partstFIRST_LED_BIT; - GPIO_BitWrite(GPIO1, uxLED, ~GPIO_BitRead( GPIO1, uxLED ) ); -} - - - - diff --git a/Demo/ARM7_STR71x_IAR/RTOSDemo.dep b/Demo/ARM7_STR71x_IAR/RTOSDemo.dep deleted file mode 100644 index 800760c68..000000000 --- a/Demo/ARM7_STR71x_IAR/RTOSDemo.dep +++ /dev/null @@ -1,866 +0,0 @@ - - - - 2 - - Debug - - $PROJ_DIR$\..\Common\Minimal\comtest.c - $PROJ_DIR$\Debug\Obj\tasks.pbi - $PROJ_DIR$\Debug\Obj\serial.pbi - $PROJ_DIR$\Debug\Obj\71x_lib.pbi - $PROJ_DIR$\Debug\Obj\wdg.pbi - $PROJ_DIR$\Debug\Obj\semtest.r79 - $TOOLKIT_DIR$\inc\string.h - $TOOLKIT_DIR$\inc\ysizet.h - $PROJ_DIR$\..\Common\include\comtest.h - $PROJ_DIR$\Debug\Obj\BlockQ.pbi - $PROJ_DIR$\..\Common\include\dynamic.h - $PROJ_DIR$\Library\include\71x_map.h - $PROJ_DIR$\Debug\Obj\list.r79 - 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$PROJ_DIR$\..\..\Source\portable\IAR\STR71x\portasm.s79 - $PROJ_DIR$\..\..\Source\queue.c - $PROJ_DIR$\..\..\Source\tasks.c - $PROJ_DIR$\..\Common\Minimal\flash.c - $PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c - $PROJ_DIR$\..\Common\Minimal\dynamic.c - $PROJ_DIR$\..\Common\Minimal\integer.c - $PROJ_DIR$\main.c - $PROJ_DIR$\ParTest\ParTest.c - $PROJ_DIR$\..\Common\Minimal\PollQ.c - $PROJ_DIR$\..\Common\Minimal\semtest.c - $PROJ_DIR$\serial\serial.c - $PROJ_DIR$\Library\gpio.c - $PROJ_DIR$\Library\71x_lib.c - - - $PROJ_DIR$\..\Common\Minimal\comtest.c - - - ICCARM - 23 - - - - - [ROOT_NODE] - - - XLINK - 20 - - - - - $PROJ_DIR$\cstartup.s79 - - - AARM - 6 - - - - - $PROJ_DIR$\vect.s79 - - - AARM - 8 - - - - - $PROJ_DIR$\..\Common\Minimal\BlockQ.c - - - ICCARM - 12 - - - - - $PROJ_DIR$\serial\serialISR.s79 - - - AARM - 21 - - - - - $PROJ_DIR$\Library\rccu.c - - - ICCARM - 14 - - - - - $PROJ_DIR$\Library\uart.c - - - ICCARM - 7 - - - - - $PROJ_DIR$\Library\wdg.c - - - ICCARM - 2 - - - - - $PROJ_DIR$\..\..\Source\list.c - - - ICCARM - 1 - - - - - $PROJ_DIR$\..\..\Source\portable\IAR\STR71x\port.c - - - ICCARM - 22 - - - - - $PROJ_DIR$\..\..\Source\portable\IAR\STR71x\portasm.s79 - - - AARM - 9 - - - - - $PROJ_DIR$\..\..\Source\queue.c - - - ICCARM - 25 - - - - - $PROJ_DIR$\..\..\Source\tasks.c - - - ICCARM - 11 - - - - - $PROJ_DIR$\..\Common\Minimal\flash.c - - - ICCARM - 16 - - - - - $PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c - - - ICCARM - 10 - - - - - $PROJ_DIR$\..\Common\Minimal\dynamic.c - - - ICCARM - 0 - - - - - $PROJ_DIR$\..\Common\Minimal\integer.c - - - ICCARM - 13 - - - - - $PROJ_DIR$\main.c - - - ICCARM - 17 - - - - - $PROJ_DIR$\ParTest\ParTest.c - - - ICCARM - 3 - - - - - $PROJ_DIR$\..\Common\Minimal\PollQ.c - - - ICCARM - 15 - - - - - $PROJ_DIR$\..\Common\Minimal\semtest.c - - - ICCARM - 19 - - - - - $PROJ_DIR$\serial\serial.c - - - ICCARM - 24 - - - - - $PROJ_DIR$\Library\gpio.c - - - ICCARM - 18 - - - - - $PROJ_DIR$\Library\71x_lib.c - - - ICCARM - 4 - - - - - [MULTI_TOOL] - XLINK - - - - - diff --git a/Demo/ARM7_STR71x_IAR/RTOSDemo.ewd b/Demo/ARM7_STR71x_IAR/RTOSDemo.ewd deleted file mode 100644 index bf7182a47..000000000 --- a/Demo/ARM7_STR71x_IAR/RTOSDemo.ewd +++ /dev/null @@ -1,913 +0,0 @@ - - - - 1 - - Debug - - ARM - - 1 - - C-SPY - 2 - - 12 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ARMSIM_ID - 2 - - 0 - 1 - 1 - - - - - ANGEL_ID - 2 - - 0 - 1 - 1 - - - - - - - - - - - - IARROM_ID - 2 - - 0 - 1 - 1 - - - - - - - - - - JLINK_ID - 2 - - 1 - 1 - 1 - - - - - - - - - - - - - - - MACRAIGOR_ID - 2 - - 1 - 1 - 1 - - - - - - - - - - - - - - - - - - RDI_ID - 2 - - 1 - 1 - 1 - - - - - - - - - - - - - - - - - THIRDPARTY_ID - 2 - - 0 - 1 - 1 - - - - - - - - - $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin - 1 - - - $EW_DIR$\common\plugins\Profiling\Profiling.ewplugin - 1 - - - $EW_DIR$\common\plugins\Trace\Trace.ewplugin - 1 - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin - 0 - - - - - Release - - ARM - - 0 - - C-SPY - 2 - - 12 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ARMSIM_ID - 2 - - 0 - 1 - 0 - - - - - ANGEL_ID - 2 - - 0 - 1 - 0 - - - - - - - - - - - - IARROM_ID - 2 - - 0 - 1 - 0 - - - - - - - - - - JLINK_ID - 2 - - 1 - 1 - 0 - - - - - - - - - - - - - - - MACRAIGOR_ID - 2 - - 1 - 1 - 0 - - - - - - - - - - - - - - - - - - RDI_ID - 2 - - 1 - 1 - 0 - - - - - - - - - - - - - - - - - THIRDPARTY_ID - 2 - - 0 - 1 - 0 - - - - - - - - - $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin - 1 - - - $EW_DIR$\common\plugins\Profiling\Profiling.ewplugin - 1 - - - $EW_DIR$\common\plugins\Trace\Trace.ewplugin - 1 - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin - 0 - - - - - - diff --git a/Demo/ARM7_STR71x_IAR/RTOSDemo.ewp b/Demo/ARM7_STR71x_IAR/RTOSDemo.ewp deleted file mode 100644 index b87cca4f9..000000000 --- a/Demo/ARM7_STR71x_IAR/RTOSDemo.ewp +++ /dev/null @@ -1,1733 +0,0 @@ - - - - 1 - - Debug - - ARM - - 1 - - General - 2 - - 8 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 11 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 5 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - XLINK - 2 - - 17 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - XAR - 2 - - 0 - 1 - 1 - - - - - - - BILINK - 0 - - - - - Release - - ARM - - 0 - - General - 2 - - 8 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 11 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 5 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - XLINK - 2 - - 17 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - XAR - 2 - - 0 - 1 - 0 - - - - - - - BILINK - 0 - - - - - Demo Source - - $PROJ_DIR$\..\Common\Minimal\BlockQ.c - - - $PROJ_DIR$\..\Common\Minimal\comtest.c - - - $PROJ_DIR$\..\Common\Minimal\dynamic.c - - - $PROJ_DIR$\..\Common\Minimal\flash.c - - - $PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c - - - $PROJ_DIR$\..\Common\Minimal\integer.c - - - $PROJ_DIR$\main.c - - - $PROJ_DIR$\ParTest\ParTest.c - - - $PROJ_DIR$\..\Common\Minimal\PollQ.c - - - $PROJ_DIR$\..\Common\Minimal\semtest.c - - - $PROJ_DIR$\serial\serial.c - - - $PROJ_DIR$\serial\serialISR.s79 - - - - Library Source - - $PROJ_DIR$\Library\71x_lib.c - - - $PROJ_DIR$\Library\gpio.c - - - $PROJ_DIR$\Library\rccu.c - - - $PROJ_DIR$\Library\uart.c - - - $PROJ_DIR$\Library\wdg.c - - - - RTOS Source - - $PROJ_DIR$\..\..\Source\list.c - - - $PROJ_DIR$\..\..\Source\portable\IAR\STR71x\port.c - - - $PROJ_DIR$\..\..\Source\portable\IAR\STR71x\portasm.s79 - - - $PROJ_DIR$\..\..\Source\queue.c - - - $PROJ_DIR$\..\..\Source\tasks.c - - - - System Files - - $PROJ_DIR$\cstartup.s79 - - - $PROJ_DIR$\lnkarm.xcl - - - $PROJ_DIR$\vect.s79 - - - - - diff --git a/Demo/ARM7_STR71x_IAR/RTOSDemo.eww b/Demo/ARM7_STR71x_IAR/RTOSDemo.eww deleted file mode 100644 index 239a9381e..000000000 --- a/Demo/ARM7_STR71x_IAR/RTOSDemo.eww +++ /dev/null @@ -1,10 +0,0 @@ - - - - - $WS_DIR$\RTOSDemo.ewp - - - - - diff --git a/Demo/ARM7_STR71x_IAR/cstartup.s79 b/Demo/ARM7_STR71x_IAR/cstartup.s79 deleted file mode 100644 index 74e9763f8..000000000 --- a/Demo/ARM7_STR71x_IAR/cstartup.s79 +++ /dev/null @@ -1,212 +0,0 @@ -;----------------------------------------------------------------------------- -; This file contains the startup code used by the ICCARM C compiler. -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; All code in the modules (except ?RESET) will be placed in the ICODE segment. -; -; $Revision: 1.1 $ -; -;----------------------------------------------------------------------------- - -; -; Naming covention of labels in this file: -; -; ?xxx - External labels only accessed from assembler. -; __xxx - External labels accessed from or defined in C. -; xxx - Labels local to one module (note: this file contains -; several modules). -; main - The starting point of the user program. -; - -;--------------------------------------------------------------- -; Macros and definitions for the whole file -;--------------------------------------------------------------- - - -; --- Standard definitions of mode bits and interrupt (I & F) flags in PSRs - - - -Mode_USR DEFINE 0x10 -Mode_FIQ DEFINE 0x11 -Mode_IRQ DEFINE 0x12 -Mode_SVC DEFINE 0x13 -Mode_ABT DEFINE 0x17 -Mode_UNDEF DEFINE 0x1B -Mode_SYS DEFINE 0x1F ; available on ARM Arch 4 and later - -I_Bit DEFINE 0x80 ; when I bit is set, IRQ is disabled -F_Bit DEFINE 0x40 ; when F bit is set, FIQ is disabled - - -; --- System memory locations - -RAM_Base DEFINE 0x20000000 -RAM_Limit DEFINE 0x20010000 -SRAM_Base DEFINE 0x60000000 - -SVC_Stack DEFINE RAM_Limit ; 512 byte SVC stack at - ; top of memory - used by kernel. -IRQ_Stack DEFINE SVC_Stack-512 ; followed by IRQ stack -USR_Stack DEFINE IRQ_Stack-512 ; followed by USR stack. Tasks run in - ; system mode but task stacks are allocated - ; when the task is created. -FIQ_Stack DEFINE USR_Stack-8 ; followed by FIQ stack -ABT_Stack DEFINE FIQ_Stack-8 ; followed by ABT stack -UNDEF_Stack DEFINE ABT_Stack-8 ; followed by UNDEF stack - -EIC_Base_addr DEFINE 0xFFFFF800 ; EIC base address -ICR_off_addr DEFINE 0x00 ; Interrupt Control register offset -CIPR_off_addr DEFINE 0x08 ; Current Interrupt Priority Register offset -IVR_off_addr DEFINE 0x18 ; Interrupt Vector Register offset -FIR_off_addr DEFINE 0x1C ; Fast Interrupt Register offset -IER_off_addr DEFINE 0x20 ; Interrupt Enable Register offset -IPR_off_addr DEFINE 0x40 ; Interrupt Pending Bit Register offset -SIR0_off_addr DEFINE 0x60 ; Source Interrupt Register 0 - -EMI_Base_addr DEFINE 0x6C000000 ; EMI base address -BCON0_off_addr DEFINE 0x00 ; Bank 0 configuration register offset -BCON1_off_addr DEFINE 0x04 ; Bank 1 configuration register offset -BCON2_off_addr DEFINE 0x08 ; Bank 2 configuration register offset -BCON3_off_addr DEFINE 0x0C ; Bank 3 configuration register offset - -GPIO2_Base_addr DEFINE 0xE0005000 ; GPIO2 base address -PC0_off_addr DEFINE 0x00 ; Port Configuration Register 0 offset -PC1_off_addr DEFINE 0x04 ; Port Configuration Register 1 offset -PC2_off_addr DEFINE 0x08 ; Port Configuration Register 2 offset -PD_off_addr DEFINE 0x0C ; Port Data Register offset - -CPM_Base_addr DEFINE 0xA0000040 ; CPM Base Address -BOOTCONF_off_addr DEFINE 0x10 ; CPM - Boot Configuration Register -FLASH_mask DEFINE 0x0000 ; to remap FLASH at 0x0 -RAM_mask DEFINE 0x0002 ; to remap RAM at 0x0 -EXTMEM_mask DEFINE 0x0003 ; to remap EXTMEM at 0x0 - -;--------------------------------------------------------------- -; ?RESET -; Reset Vector. -; Normally, segment INTVEC is linked at address 0. -; For debugging purposes, INTVEC may be placed at other -; addresses. -; A debugger that honors the entry point will start the -; program in a normal way even if INTVEC is not at address 0. -;--------------------------------------------------------------- - - MODULE ?RESET - COMMON INTVEC:CODE:NOROOT(2) - PUBLIC __program_start - EXTERN ?cstartup - CODE32 ; Always ARM mode after reset - -__program_start - ldr pc,=?cstartup ; Absolute jump can reach 4 GByte - b ?cstartup ; Relative branch allows remap, limited to 32 MByte - - LTORG - ENDMOD - - -;--------------------------------------------------------------- -; ?CSTARTUP -;--------------------------------------------------------------- - MODULE ?CSTARTUP - -; RSEG IRQ_STACK:DATA(2) -; RSEG SVC_STACK:DATA:NOROOT(2) -; RSEG CSTACK:DATA(2) - RSEG ICODE:CODE:NOROOT(2) - PUBLIC ?cstartup - EXTERN ?main - - - - - CODE32 -?cstartup - - - NOP ; Wait for OSC stabilization - NOP - NOP - NOP - NOP - NOP - NOP - NOP - NOP - - - /* Setup a stack for each mode - note that this only sets up a usable stack - for system/user, SWI and IRQ modes. Also each mode is setup with - interrupts initially disabled. */ - msr CPSR_c, #Mode_UNDEF|I_Bit|F_Bit /* Undefined Instruction Mode */ - LDR SP, =UNDEF_Stack - - msr CPSR_c, #Mode_ABT|I_Bit|F_Bit /* Abort Mode */ - LDR SP, =ABT_Stack - - msr CPSR_c, #Mode_FIQ|I_Bit|F_Bit /* FIQ Mode */ - LDR SP, =FIQ_Stack - - msr CPSR_c, #Mode_IRQ|I_Bit|F_Bit /* IRQ Mode */ - LDR SP, =IRQ_Stack - - msr CPSR_c, #Mode_SVC|I_Bit|F_Bit /* Supervisor Mode */ - LDR SP, =SVC_Stack - - msr CPSR_c, #Mode_SYS|I_Bit|F_Bit /* System Mode */ - LDR SP, =USR_Stack - - /* We want to start in supervisor mode. Operation will switch to system - mode when the first task starts. */ - msr CPSR_c, #Mode_SVC|I_Bit|F_Bit - - - IMPORT T0TIMI_Addr - -EIC_INIT - LDR r3, =EIC_Base_addr - LDR r4, =0x00000000 - STR r4, [r3, #ICR_off_addr] ; Disable FIQ and IRQ - STR r4, [r3, #IER_off_addr] ; Disable all channels interrupts - LDR r4, =0xFFFFFFFF - STR r4, [r3, #IPR_off_addr] ; Clear all IRQ pending bits - LDR r4, =0x0C - STR r4, [r3, #FIR_off_addr] ; Disable FIQ channels and clear FIQ pending bits - LDR r4, =0x00000000 - STR r4, [r3, #CIPR_off_addr] ; Reset the current priority register - LDR r4, =0xE59F0000 - STR r4, [r3, #IVR_off_addr] ; Write the LDR pc,pc,#offset instruction code in IVR[31:16] - LDR r2, =32 ; 32 Channel to initialize - LDR r0, =T0TIMI_Addr ; Read the address of the IRQs address table - LDR r1, =0x00000FFF - AND r0,r0,r1 - LDR r5, =SIR0_off_addr ; Read SIR0 address - SUB r4,r0,#8 ; subtract 8 for prefetch - LDR r1, =0xF7E8 ; add the offset to the 0x00000000 address(IVR address + 7E8 = 0x00000000) - ; 0xF7E8 used to complete the LDR pc,pc,#offset opcode - ADD r1,r4,r1 ; compute the jump offset -EIC_INI MOV r4, r1, LSL #16 ; Left shift the result - STR r4, [r3, r5] ; Store the result in SIRx register - ADD r1, r1, #4 ; Next IRQ address - ADD r5, r5, #4 ; Next SIR - SUBS r2, r2, #1 ; Decrement the number of SIR registers to initialize - BNE EIC_INI ; If more then continue - - - ldr r0,=?main - bx r0 - - LTORG - - ENDMOD - - - END - - diff --git a/Demo/ARM7_STR71x_IAR/lnkarm.xcl b/Demo/ARM7_STR71x_IAR/lnkarm.xcl deleted file mode 100644 index eb3403a7c..000000000 --- a/Demo/ARM7_STR71x_IAR/lnkarm.xcl +++ /dev/null @@ -1,201 +0,0 @@ -//************************************************************************* -// XLINK command file template for EWARM/ICCARM -// -// Usage: xlink -f lnkarm -// -s -// -// $Revision: 1.1 $ -//************************************************************************* - -// Code memory in flash --DROMSTART=0x00000000 --DROMEND=0x0003FFFF --DVECSTART=ROMSTART - -// Data memory --DRAMSTART=0x20000000 --DRAMEND=0x2000FFFF - - -//************************************************************************* -// In this file it is assumed that the system has the following -// memory layout: -// -// Exception vectors [0x000000--0x00001F] RAM or ROM -// ROMSTART--ROMEND [0x008000--0x0FFFFF] ROM (or other non-volatile memory) -// RAMSTART--RAMEND [0x100000--0x7FFFFF] RAM (or other read/write memory) -// -// ------------- -// Code segments - may be placed anywhere in memory. -// ------------- -// -// INTVEC -- Exception vector table. -// SWITAB -- Software interrupt vector table. -// ICODE -- Startup (cstartup) and exception code. -// DIFUNCT -- Dynamic initialization vectors used by C++. -// CODE -- Compiler generated code. -// CODE_I -- Compiler generated code declared __ramfunc (executes in RAM) -// CODE_ID -- Initializer for CODE_I (ROM). -// -// ------------- -// Data segments - may be placed anywhere in memory. -// ------------- -// -// CSTACK -- The stack used by C/C++ programs (system and user mode). -// IRQ_STACK -- The stack used by IRQ service routines. -// SVC_STACK -- The stack used in supervisor mode -// (Define other exception stacks as needed for -// FIQ, ABT, UND). -// HEAP -- The heap used by malloc and free in C and new and -// delete in C++. -// INITTAB -- Table containing addresses and sizes of segments that -// need to be initialized at startup (by cstartup). -// CHECKSUM -- The linker places checksum byte(s) in this segment, -// when the -J linker command line option is used. -// DATA_y -- Data objects. -// -// Where _y can be one of: -// -// _AN -- Holds uninitialized located objects, i.e. objects with -// an absolute location given by the @ operator or the -// #pragma location directive. Since these segments -// contain objects which already have a fixed address, -// they should not be mentioned in this linker command -// file. -// _C -- Constants (ROM). -// _I -- Initialized data (RAM). -// _ID -- The original content of _I (copied to _I by cstartup) (ROM). -// _N -- Uninitialized data (RAM). -// _Z -- Zero initialized data (RAM). -// -// Note: Be sure to use end values for the defined address ranges. -// Otherwise, the linker may allocate space outside the -// intended memory range. -//************************************************************************* - - -//************************************************ -// Inform the linker about the CPU family used. -//************************************************ - --carm - -//************************************************************************* -// Segment placement - General information -// -// All numbers in the segment placement command lines below are interpreted -// as hexadecimal unless they are immediately preceded by a '.', which -// denotes decimal notation. -// -// When specifying the segment placement using the -P instead of the -Z -// option, the linker is free to split each segment into its segment parts -// and randomly place these parts within the given ranges in order to -// achieve a more efficient memory usage. One disadvantage, however, is -// that it is not possible to find the start or end address (using -// the assembler operators .sfb./.sfe.) of a segment which has been split -// and reformed. -// -// When generating an output file which is to be used for programming -// external ROM/Flash devices, the -M linker option is very useful -// (see xlink.pdf for details). -//************************************************************************* - - -//************************************************************************* -// Read-only segments mapped to ROM. -//************************************************************************* - -//************************************************ -// Address range for reset and exception -// vectors (INTVEC). -// The vector area is 32 bytes, -// an additional 32 bytes is allocated for the -// constant table used by ldr PC in cstartup.s79. -//************************************************ - --Z(CODE)INTVEC=VECSTART:+0x940 - -//************************************************ -// Startup code and exception routines (ICODE). -//************************************************ - --Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND --Z(CODE)SWITAB=ROMSTART-ROMEND - -//************************************************ -// Code segments may be placed anywhere. -//************************************************ - --Z(CODE)CODE=ROMSTART-ROMEND - -//************************************************ -// Original ROM location for __ramfunc code copied -// to and executed from RAM. -//************************************************ - --Z(CONST)CODE_ID=ROMSTART-ROMEND - -//************************************************ -// Various constants and initializers. -//************************************************ - --Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND --Z(CONST)CHECKSUM=ROMSTART-ROMEND - - -//************************************************************************* -// Read/write segments mapped to RAM. -//************************************************************************* - -//************************************************ -// Data segments. -//************************************************ - --Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND - -//************************************************ -// __ramfunc code copied to and executed from RAM. -//************************************************ - --Z(DATA)CODE_I=RAMSTART-RAMEND - -//************************************************ -// ICCARM produces code for __ramfunc functions in -// CODE_I segments. The -Q XLINK command line -// option redirects XLINK to emit the code in the -// CODE_ID segment instead, but to keep symbol and -// debug information associated with the CODE_I -// segment, where the code will execute. -//************************************************ - --QCODE_I=CODE_ID - -//************************************************************************* -// Stack and heap segments. -//************************************************************************* - -//-D_CSTACK_SIZE=400 -// -D_SVC_STACK_SIZE=10 -//-D_IRQ_STACK_SIZE=500 -//-D_HEAP_SIZE=4 - -//-Z(DATA)CSTACK+_CSTACK_SIZE=RAMSTART-RAMEND -//-Z(DATA)SVC_STACK+_SVC_STACK_SIZE=RAMSTART-RAMEND -//-Z(DATA)IRQ_STACK+_IRQ_STACK_SIZE,HEAP+_HEAP_SIZE=RAMSTART-RAMEND - -//************************************************************************* -// ELF/DWARF support. -// -// Uncomment the line "-Felf" below to generate ELF/DWARF output. -// Available format specifiers are: -// -// "-yn": Suppress DWARF debug output -// "-yp": Multiple ELF program sections -// "-yas": Format suitable for debuggers from ARM Ltd (also sets -p flag) -// -// "-Felf" and the format specifiers can also be supplied directly as -// command line options, or selected from the Xlink Output tab in the -// IAR Embedded Workbench. -//************************************************************************* - -// -Felf diff --git a/Demo/ARM7_STR71x_IAR/main.c b/Demo/ARM7_STR71x_IAR/main.c deleted file mode 100644 index c77647dbf..000000000 --- a/Demo/ARM7_STR71x_IAR/main.c +++ /dev/null @@ -1,246 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. - The processor MUST be in supervisor mode when vTaskStartScheduler is - called. The demo applications included in the FreeRTOS.org download switch - to supervisor mode prior to main being called. If you are not using one of - these demo application projects then ensure Supervisor mode is used. -*/ - -/* - * Creates all the demo application tasks, then starts the scheduler. The WEB - * documentation provides more details of the demo application tasks. - * - * Main.c also creates a task called "Check". This only executes every three - * seconds but has the highest priority so is guaranteed to get processor time. - * Its main function is to check that all the other tasks are still operational. - * Each task (other than the "flash" tasks) maintains a unique count that is - * incremented each time the task successfully completes its function. Should - * any error occur within such a task the count is permanently halted. The - * check task inspects the count of each task to ensure it has changed since - * the last time the check task executed. If all the count variables have - * changed all the tasks are still executing error free, and the check task - * toggles the onboard LED. Should any task contain an error at any time - * the LED toggle rate will change from 3 seconds to 500ms. - * - */ - -/* Library includes. */ -#include "RCCU.h" -#include "wdg.h" - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Demo application includes. */ -#include "flash.h" -#include "integer.h" -#include "PollQ.h" -#include "BlockQ.h" -#include "semtest.h" -#include "dynamic.h" -#include "partest.h" -#include "comtest2.h" - -/* Priorities for the demo application tasks. */ -#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) - -/* Constants required by the 'Check' task. */ -#define mainNO_ERROR_FLASH_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS ) -#define mainERROR_FLASH_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS ) -#define mainCHECK_TASK_LED ( 4 ) - -/* Constants for the ComTest tasks. */ -#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 115200 ) -#define mainCOM_TEST_LED ( 6 ) /* The LED built onto the kickstart board. */ - -/* - * The task that executes at the highest priority and calls - * prvCheckOtherTasksAreStillRunning(). See the description at the top - * of the file. - */ -static void vErrorChecks( void *pvParameters ); - -/* - * Configure the processor for use with the IAR STR71x demo board. This - * just sets the PLL for the required frequency. - */ -static void prvSetupHardware( void ); - -/* - * Checks that all the demo application tasks are still executing without error - * - as described at the top of the file. Called by vErrorChecks(). - */ -static portLONG prvCheckOtherTasksAreStillRunning( void ); - - -/*-----------------------------------------------------------*/ - -/* - * Starts all the other tasks, then starts the scheduler. - */ -void main( void ) -{ - /* Setup any hardware that has not already been configured by the low - level init routines. */ - prvSetupHardware(); - - /* Initialise the LED outputs for use by the demo application tasks. */ - vParTestInitialise(); - - /* Start all the standard demo application tasks. */ - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - vStartDynamicPriorityTasks(); - vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); - - /* Start the check task - which is defined in this file. */ - xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - - /* Start the scheduler. - - NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. - The processor MUST be in supervisor mode when vTaskStartScheduler is - called. The demo applications included in the FreeRTOS.org download switch - to supervisor mode prior to main being called. If you are not using one of - these demo application projects then ensure Supervisor mode is used here. */ - - vTaskStartScheduler(); - - /* We should never get here as control is now taken by the scheduler. */ - return; -} -/*-----------------------------------------------------------*/ - -static void prvSetupHardware( void ) -{ - /* Setup the PLL to generate a 48MHz clock from the 4MHz CLK. */ - - /* Turn of the div by two. */ - RCCU_Div2Config( DISABLE ); - - /* 48MHz = ( 4MHz * 12 ) / 1 */ - RCCU_PLL1Config( RCCU_PLL1_Mul_12, RCCU_Div_1 ); - RCCU_RCLKSourceConfig( RCCU_PLL1_Output ); -} -/*-----------------------------------------------------------*/ - -static void vErrorChecks( void *pvParameters ) -{ -portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD; -portTickType xLastWakeTime; - - /* The parameters are not used in this task. */ - ( void ) pvParameters; - - /* Initialise xLastWakeTime to ensure the first call to vTaskDelayUntil() - functions correctly. */ - xLastWakeTime = xTaskGetTickCount(); - - /* Cycle for ever, delaying then checking all the other tasks are still - operating without error. If an error is detected then the delay period - is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so - the on board LED flash rate will increase. */ - - for( ;; ) - { - /* Delay until it is time to execute again. The delay period is - shorter following an error so the LED flashes faster. */ - vTaskDelayUntil( &xLastWakeTime, xDelayPeriod ); - - /* Check all the standard demo application tasks are executing without - error. */ - if( prvCheckOtherTasksAreStillRunning() != pdPASS ) - { - /* An error has been detected in one of the tasks - flash faster. */ - xDelayPeriod = mainERROR_FLASH_PERIOD; - } - - vParTestToggleLED( mainCHECK_TASK_LED ); - } -} -/*-----------------------------------------------------------*/ - -static portLONG prvCheckOtherTasksAreStillRunning( void ) -{ -portLONG lReturn = ( portLONG ) pdPASS; - - /* Check all the demo tasks (other than the flash tasks) to ensure - that they are all still running, and that none of them have detected - an error. */ - - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - lReturn = ( portLONG ) pdFAIL; - } - - if( xArePollingQueuesStillRunning() != pdTRUE ) - { - lReturn = ( portLONG ) pdFAIL; - } - - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - lReturn = ( portLONG ) pdFAIL; - } - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - lReturn = ( portLONG ) pdFAIL; - } - - if( xAreComTestTasksStillRunning() != pdTRUE ) - { - lReturn = ( portLONG ) pdFAIL; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - lReturn = ( portLONG ) pdFAIL; - } - - return lReturn; -} -/*-----------------------------------------------------------*/ - - diff --git a/Demo/ARM7_STR71x_IAR/serial/serial.c b/Demo/ARM7_STR71x_IAR/serial/serial.c deleted file mode 100644 index 60ab53fa7..000000000 --- a/Demo/ARM7_STR71x_IAR/serial/serial.c +++ /dev/null @@ -1,242 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0. -*/ - -/* Library includes. */ -#include "uart.h" -#include "gpio.h" -#include "eic.h" - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "queue.h" - -/* Demo application includes. */ -#include "serial.h" - -#define UART0_Rx_Pin ( 0x0001<< 8 ) -#define UART0_Tx_Pin ( 0x0001<< 9 ) - -#define serINVALID_QUEUE ( ( xQueueHandle ) 0 ) -#define serNO_BLOCK ( ( portTickType ) 0 ) - -/* Macros to turn on and off the Tx empty interrupt. */ -#define serINTERRUPT_ON() UART0->IER |= UART_TxHalfEmpty -#define serINTERRUPT_OFF() UART0->IER &= ~UART_TxHalfEmpty - -/*-----------------------------------------------------------*/ - -/* Queues used to hold received characters, and characters waiting to be -transmitted. */ -static xQueueHandle xRxedChars; -static xQueueHandle xCharsForTx; - -/*-----------------------------------------------------------*/ - -/* Interrupt entry point written in the assembler file serialISR.s79. */ -extern void vSerialISREntry( void ); - -/* The interrupt service routine - called from the assembly entry point. */ -__arm void vSerialISR( void ); - -/*-----------------------------------------------------------*/ - -/* - * See the serial2.h header file. - */ -xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) -{ -xComPortHandle xReturn; - - /* Create the queues used to hold Rx and Tx characters. */ - xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); - xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); - - /* If the queues were created correctly then setup the serial port - hardware. */ - if( ( xRxedChars != serINVALID_QUEUE ) && ( xCharsForTx != serINVALID_QUEUE ) ) - { - portENTER_CRITICAL(); - { - /* Setup the UART port pins. */ - GPIO_Config( GPIO0, UART0_Tx_Pin, GPIO_AF_PP ); - GPIO_Config( GPIO0, UART0_Rx_Pin, GPIO_IN_TRI_CMOS ); - - /* Configure the UART. */ - UART_OnOffConfig( UART0, ENABLE ); - UART_FifoConfig( UART0, DISABLE ); - UART_FifoReset( UART0, UART_RxFIFO ); - UART_FifoReset( UART0, UART_TxFIFO ); - UART_LoopBackConfig(UART0, DISABLE ); - UART_Config( UART0, ulWantedBaud, UART_NO_PARITY, UART_1_StopBits, UARTM_8D ); - UART_RxConfig( UART0, ENABLE ); - - /* Configure the IEC for the UART interrupts. */ - EIC_IRQChannelPriorityConfig( UART0_IRQChannel, 1 ); - EIC_IRQChannelConfig( UART0_IRQChannel, ENABLE ); - EIC_IRQConfig( ENABLE ); - UART_ItConfig( UART0, UART_RxBufFull, ENABLE ); - } - portEXIT_CRITICAL(); - } - else - { - xReturn = ( xComPortHandle ) 0; - } - - /* This demo file only supports a single port but we have to return - something to comply with the standard demo header file. */ - return xReturn; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) -{ - /* The port handle is not required as this driver only supports one port. */ - ( void ) pxPort; - - /* Get the next character from the buffer. Return false if no characters - are available, or arrive before xBlockTime expires. */ - if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) - { - return pdTRUE; - } - else - { - return pdFALSE; - } -} -/*-----------------------------------------------------------*/ - -void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength ) -{ -signed portCHAR *pxNext; - - /* A couple of parameters that this port does not use. */ - ( void ) usStringLength; - ( void ) pxPort; - - /* NOTE: This implementation does not handle the queue being full as no - block time is used! */ - - /* The port handle is not required as this driver only supports UART0. */ - ( void ) pxPort; - - /* Send each character in the string, one at a time. */ - pxNext = ( signed portCHAR * ) pcString; - while( *pxNext ) - { - xSerialPutChar( pxPort, *pxNext, serNO_BLOCK ); - pxNext++; - } -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) -{ - /* Place the character in the queue of characters to be transmitted. */ - if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) - { - return pdFAIL; - } - - /* Turn on the Tx interrupt so the ISR will remove the character from the - queue and send it. This does not need to be in a critical section as - if the interrupt has already removed the character the next interrupt - will simply turn off the Tx interrupt again. */ - serINTERRUPT_ON(); - - return pdPASS; -} -/*-----------------------------------------------------------*/ - -void vSerialClose( xComPortHandle xPort ) -{ - /* Not supported as not required by the demo application. */ -} -/*-----------------------------------------------------------*/ - -/* Serial port ISR. This can cause a context switch so is not defined as a -standard ISR using the __irq keyword. Instead a wrapper function is defined -within serialISR.s79 which in turn calls this function. See the port -documentation on the FreeRTOS.org website for more information. */ -__arm void vSerialISR( void ) -{ -unsigned portSHORT usStatus; -signed portCHAR cChar; -portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByPost = pdFALSE; - - /* What caused the interrupt? */ - usStatus = UART_FlagStatus( UART0 ); - - if( usStatus & UART_TxHalfEmpty ) - { - /* The interrupt was caused by the THR becoming empty. Are there any - more characters to transmit? */ - if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE ) - { - /* A character was retrieved from the queue so can be sent to the - THR now. */ - UART0->TxBUFR = cChar; - } - else - { - /* Queue empty, nothing to send so turn off the Tx interrupt. */ - serINTERRUPT_OFF(); - } - } - - if( usStatus & UART_RxBufFull ) - { - /* The interrupt was caused by a character being received. Grab the - character from the RHR and place it in the queue of received - characters. */ - cChar = UART0->RxBUFR; - xTaskWokenByPost = xQueueSendFromISR( xRxedChars, &cChar, xTaskWokenByPost ); - } - - /* If a task was woken by either a character being received or a character - being transmitted then we may need to switch to another task. */ - portEND_SWITCHING_ISR( ( xTaskWokenByPost || xTaskWokenByTx ) ); - - /* End the interrupt in the EIC. */ - portCLEAR_EIC(); -} - - - - - - diff --git a/Demo/ARM7_STR71x_IAR/serial/serialISR.s79 b/Demo/ARM7_STR71x_IAR/serial/serialISR.s79 deleted file mode 100644 index da0a0bd17..000000000 --- a/Demo/ARM7_STR71x_IAR/serial/serialISR.s79 +++ /dev/null @@ -1,24 +0,0 @@ - RSEG ICODE:CODE - CODE32 - - EXTERN vSerialISR - PUBLIC vSerialISREntry - -; Wrapper for the serial port interrupt service routine. This can cause a -; context switch so requires an assembly wrapper. - -; Defines the portSAVE_CONTEXT and portRESTORE_CONTEXT macros. -#include "ISR_Support.h" - -vSerialISREntry: - - portSAVE_CONTEXT ; Save the context of the current task. - - bl vSerialISR ; Call the ISR routine. - - portRESTORE_CONTEXT ; Restore the context of the current task - - ; which may be different to the task that - ; was interrupted. - - END - diff --git a/Demo/ARM7_STR71x_IAR/settings/RTOSDemo.dbgdt b/Demo/ARM7_STR71x_IAR/settings/RTOSDemo.dbgdt deleted file mode 100644 index cd1e2ee2f..000000000 --- a/Demo/ARM7_STR71x_IAR/settings/RTOSDemo.dbgdt +++ /dev/null @@ -1,81 +0,0 @@ - - - - - - - - - - - - 129272727 - - - - - - - - 200 - - - - 100 - - - - - - - 20115330776 - 200 - - - - - - - TabID-24393-22702 - Workspace - Workspace - - - RTOSDemoRTOSDemo/Demo SourceRTOSDemo/RTOS SourceRTOSDemo/System FilesRTOSDemo/System Files/vect.s79 - - - - 0 - - - TabID-13122-22708 - Debug Log - Debug-Log - - - - TabID-23870-22711 - Build - Build - - - TabID-19116-28152BreakpointsBreakpoints - - 0TabID-10243-6871RegisterRegister0001CPSR0 - - - - - - 0100000010000001 - - - - - - - iaridepm1debuggergui1-2-2853203-2-212512578125111706128124764075-2-2853447-2-2200200125000178731280625764075-2-22191602-2-21604221100250019749778125111706 - - - - diff --git a/Demo/ARM7_STR71x_IAR/settings/RTOSDemo.dni b/Demo/ARM7_STR71x_IAR/settings/RTOSDemo.dni deleted file mode 100644 index e6db9e63b..000000000 --- a/Demo/ARM7_STR71x_IAR/settings/RTOSDemo.dni +++ /dev/null @@ -1,23 +0,0 @@ -[DisAssemblyWindow] -NumStates=_ 1 -State 1=_ 1 -[JLinkDriver] -WatchVectorCatch=_ 0 -WatchCond=_ 0 -Watch0=_ 0 "0x00000000" 0 "0x00000000" 0 "0x00000000" 0 "0x00000000" 0 0 0 0 -Watch1=_ 0 "0x00000000" 0 "0x00000000" 0 "0x00000000" 0 "0x00000000" 0 0 0 0 -[Low Level] -Pipeline mode=0 -Initialized=0 -[Disassemble mode] -mode=0 -[Breakpoints] -Bp0=_ "Code" "{E:\Dev\FreeRTOS\Source\portable\IAR\STR71x\port.c}.240.4@1" 1 0 0 0 "" 0 "" -Count=1 -[Log file] -LoggingEnabled=_ 0 -LogFile=_ "" -Category=_ 0 -[TermIOLog] -LoggingEnabled=_ 0 -LogFile=_ "" diff --git a/Demo/ARM7_STR71x_IAR/settings/RTOSDemo.wsdt b/Demo/ARM7_STR71x_IAR/settings/RTOSDemo.wsdt deleted file mode 100644 index 5acc21f72..000000000 --- a/Demo/ARM7_STR71x_IAR/settings/RTOSDemo.wsdt +++ /dev/null @@ -1,75 +0,0 @@ - - - - - - RTOSDemo/Debug - - - - - - - - - 227272727 - - - - - - - 20115330776 - - - - - - - - - - - TabID-14962-21036 - Workspace - Workspace - - - RTOSDemoRTOSDemo/source - - - - 0 - - - TabID-24623-22493 - Build - Build - - - - TabID-13645-22698 - Debug Log - Debug-Log - - - TabID-25855-25419BreakpointsBreakpoints - - 0 - - - - - - TextEditorE:\Dev\FreeRTOS\Demo\ARM7_STR71x_IAR\main.c0984693469300100000010000001 - - - - - - - iaridepm1debuggergui1-2-2675301-2-221211312518766189375605004-2-23971602-2-2160439910025003565681312518766 - - - - diff --git a/Demo/ARM7_STR71x_IAR/vect.s79 b/Demo/ARM7_STR71x_IAR/vect.s79 deleted file mode 100644 index f363a0d35..000000000 --- a/Demo/ARM7_STR71x_IAR/vect.s79 +++ /dev/null @@ -1,127 +0,0 @@ -#include "FreeRTOSConfig.h" - -IVR_ADDR DEFINE 0xFFFFF818 - -;******************************************************************************* -; Import the Reset_Handler address from 71x_init.s -;******************************************************************************* - - IMPORT __program_start - -;******************************************************************************* -; Import exception handlers -;******************************************************************************* - - IMPORT vPortYieldProcessor ; FreeRTOS SWI handler - -;******************************************************************************* -; Import IRQ handlers from 71x_it.c -;******************************************************************************* - - IMPORT vPortNonPreemptiveTick ; Cooperative FreeRTOS tick handler - IMPORT vPortPreemptiveTickISR ; Preemptive FreeRTOS tick handler - IMPORT vSerialISREntry ; Demo serial port handler - -;******************************************************************************* -; Export Peripherals IRQ handlers table address -;******************************************************************************* - - CODE32 - - - LDR PC, Reset_Addr - LDR PC, Undefined_Addr - LDR PC, SWI_Addr - LDR PC, Prefetch_Addr - LDR PC, Abort_Addr - NOP ; Reserved vector - LDR PC, =IVR_ADDR - LDR PC, FIQ_Addr - - - -;******************************************************************************* -; Exception handlers address table -;******************************************************************************* - -Reset_Addr DCD __program_start -Undefined_Addr DCD UndefinedHandler -SWI_Addr DCD vPortYieldProcessor -Prefetch_Addr DCD PrefetchAbortHandler -Abort_Addr DCD DataAbortHandler - DCD 0 ; Reserved vector -IRQ_Addr DCD IRQHandler -FIQ_Addr DCD FIQHandler - -;******************************************************************************* -; Peripherals IRQ handlers address table -;******************************************************************************* - - EXPORT T0TIMI_Addr - -T0TIMI_Addr DCD DefaultISR -FLASH_Addr DCD DefaultISR -RCCU_Addr DCD DefaultISR -RTC_Addr DCD DefaultISR -#if configUSE_PREEMPTION == 0 -WDG_Addr DCD vPortNonPreemptiveTick ; Tick ISR if the cooperative scheduler is used. -#else -WDG_Addr DCD vPortPreemptiveTickISR ; Tick ISR if the preemptive scheduler is used. -#endif -XTI_Addr DCD DefaultISR -USBHP_Addr DCD DefaultISR -I2C0ITERR_Addr DCD DefaultISR -I2C1ITERR_ADDR DCD DefaultISR -UART0_Addr DCD vSerialISREntry -UART1_Addr DCD DefaultISR -UART2_ADDR DCD DefaultISR -UART3_ADDR DCD DefaultISR -BSPI0_ADDR DCD DefaultISR -BSPI1_Addr DCD DefaultISR -I2C0_Addr DCD DefaultISR -I2C1_Addr DCD DefaultISR -CAN_Addr DCD DefaultISR -ADC12_Addr DCD DefaultISR -T1TIMI_Addr DCD DefaultISR -T2TIMI_Addr DCD DefaultISR -T3TIMI_Addr DCD DefaultISR - DCD 0 ; reserved - DCD 0 ; reserved - DCD 0 ; reserved -HDLC_Addr DCD DefaultISR -USBLP_Addr DCD DefaultISR - DCD 0 ; reserved - DCD 0 ; reserved -T0TOI_Addr DCD DefaultISR -T0OC1_Addr DCD DefaultISR -T0OC2_Addr DCD DefaultISR - - -;******************************************************************************* -; Exception Handlers -;******************************************************************************* - - -UndefinedHandler - b UndefinedHandler - -PrefetchAbortHandler - b PrefetchAbortHandler - -DataAbortHandler - b DataAbortHandler - -IRQHandler - b DefaultISR - -FIQHandler - b FIQHandler - -DefaultISR - b DefaultISR - - - - LTORG - - END diff --git a/Demo/ARM7_STR75x_GCC/FreeRTOSConfig.h b/Demo/ARM7_STR75x_GCC/FreeRTOSConfig.h deleted file mode 100644 index c70e63d7e..000000000 --- a/Demo/ARM7_STR75x_GCC/FreeRTOSConfig.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -#include <75x_lib.h> - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 60000000 ) /* Timer clock. */ -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 100 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) 12800 ) -#define configMAX_TASK_NAME_LEN ( 16 ) -#define configUSE_TRACE_FACILITY 0 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 0 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 0 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/ARM7_STR75x_GCC/ParTest/ParTest.c b/Demo/ARM7_STR75x_GCC/ParTest/ParTest.c deleted file mode 100644 index a2feddb69..000000000 --- a/Demo/ARM7_STR75x_GCC/ParTest/ParTest.c +++ /dev/null @@ -1,137 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* Library includes. */ -#include "75x_GPIO.h" -#include "75x_map.h" - -/* Scheduler includes. */ -#include "FreeRTOS.h" - -/* Demo application includes. */ -#include "partest.h" - -/*----------------------------------------------------------- - * Simple parallel port IO routines for the LED's - *-----------------------------------------------------------*/ - -#define partstNUM_LEDS 4 - -typedef struct GPIOMAP -{ - GPIO_TypeDef *pxPort; - unsigned portLONG ulPin; - unsigned portLONG ulValue; -} GPIO_MAP; - -static GPIO_MAP xLEDMap[ partstNUM_LEDS ] = -{ - { ( GPIO_TypeDef * )GPIO1_BASE, GPIO_Pin_1, 0UL }, - { ( GPIO_TypeDef * )GPIO0_BASE, GPIO_Pin_16, 0UL }, - { ( GPIO_TypeDef * )GPIO2_BASE, GPIO_Pin_18, 0UL }, - { ( GPIO_TypeDef * )GPIO2_BASE, GPIO_Pin_19, 0UL } -}; - -/*-----------------------------------------------------------*/ - -void vParTestInitialise( void ) -{ -GPIO_InitTypeDef GPIO_InitStructure ; - - /* Configure the bits used to flash LED's on port 1 as output. */ - - /* Configure LED3 */ - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_16; - GPIO_Init(GPIO0,&GPIO_InitStructure); - - /* Configure LED2 */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1; - GPIO_Init(GPIO1, &GPIO_InitStructure); - - /* Configure LED4 and LED5 */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_18 | GPIO_Pin_19; - GPIO_Init(GPIO2, &GPIO_InitStructure); - - vParTestSetLED( 0, 0 ); - vParTestSetLED( 1, 0 ); - vParTestSetLED( 2, 0 ); - vParTestSetLED( 3, 0 ); -} -/*-----------------------------------------------------------*/ - -void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) -{ - if( uxLED < partstNUM_LEDS ) - { - portENTER_CRITICAL(); - { - if( xValue ) - { - GPIO_WriteBit( xLEDMap[ uxLED ].pxPort, xLEDMap[ uxLED ].ulPin, Bit_RESET ); - xLEDMap[ uxLED ].ulValue = 0; - } - else - { - GPIO_WriteBit( xLEDMap[ uxLED ].pxPort, xLEDMap[ uxLED ].ulPin, Bit_SET ); - xLEDMap[ uxLED ].ulValue = 1; - } - } - portEXIT_CRITICAL(); - } -} -/*-----------------------------------------------------------*/ - -void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) -{ - if( uxLED < partstNUM_LEDS ) - { - portENTER_CRITICAL(); - { - if( xLEDMap[ uxLED ].ulValue == 1 ) - { - GPIO_WriteBit( xLEDMap[ uxLED ].pxPort, xLEDMap[ uxLED ].ulPin, Bit_RESET ); - xLEDMap[ uxLED ].ulValue = 0; - } - else - { - GPIO_WriteBit( xLEDMap[ uxLED ].pxPort, xLEDMap[ uxLED ].ulPin, Bit_SET ); - xLEDMap[ uxLED ].ulValue = 1; - } - } - portEXIT_CRITICAL(); - } -} - - - - diff --git a/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_adc.h b/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_adc.h deleted file mode 100644 index bce23f731..000000000 --- a/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_adc.h +++ /dev/null @@ -1,177 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_adc.h -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file contains all the functions prototypes for the -* ADC software library. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __75x_ADC_H -#define __75x_ADC_H - -/* Includes ------------------------------------------------------------------*/ -#include "75x_map.h" - -/* Exported types ------------------------------------------------------------*/ -/* ADC Init structure definition */ -typedef struct -{ - u16 ADC_ConversionMode; - u16 ADC_ExtTrigger; - u16 ADC_AutoClockOff; - u8 ADC_SamplingPrescaler; - u8 ADC_ConversionPrescaler; - u8 ADC_FirstChannel; - u8 ADC_ChannelNumber; - }ADC_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ -/* ADC control status flags */ -#define ADC_FLAG_ECH 0x0001 -#define ADC_FLAG_EOC 0x0002 -#define ADC_FLAG_JECH 0x0004 -#define ADC_FLAG_JEOC 0x0008 -#define ADC_FLAG_AnalogWatchdog0_LowThreshold 0x0010 -#define ADC_FLAG_AnalogWatchdog0_HighThreshold 0x0020 -#define ADC_FLAG_AnalogWatchdog1_LowThreshold 0x0040 -#define ADC_FLAG_AnalogWatchdog1_HighThreshold 0x0080 -#define ADC_FLAG_AnalogWatchdog2_LowThreshold 0x0100 -#define ADC_FLAG_AnalogWatchdog2_HighThreshold 0x0200 -#define ADC_FLAG_AnalogWatchdog3_LowThreshold 0x0400 -#define ADC_FLAG_AnalogWatchdog3_HighThreshold 0x0800 - -/* ADC Interrupt sources */ -#define ADC_IT_ECH 0x0001 -#define ADC_IT_EOC 0x0002 -#define ADC_IT_JECH 0x0004 -#define ADC_IT_JEOC 0x0008 -#define ADC_IT_AnalogWatchdog0_LowThreshold 0x0010 -#define ADC_IT_AnalogWatchdog0_HighThreshold 0x0020 -#define ADC_IT_AnalogWatchdog1_LowThreshold 0x0040 -#define ADC_IT_AnalogWatchdog1_HighThreshold 0x0080 -#define ADC_IT_AnalogWatchdog2_LowThreshold 0x0100 -#define ADC_IT_AnalogWatchdog2_HighThreshold 0x0200 -#define ADC_IT_AnalogWatchdog3_LowThreshold 0x0400 -#define ADC_IT_AnalogWatchdog3_HighThreshold 0x0800 -#define ADC_IT_ALL 0x0FFF - -/* ADC Watchdogs Thresholds */ -#define ADC_AnalogWatchdog0 0x0030 -#define ADC_AnalogWatchdog1 0x00C0 -#define ADC_AnalogWatchdog2 0x0300 -#define ADC_AnalogWatchdog3 0x0C00 - -/* ADC Channels */ -#define ADC_CHANNEL0 0x0 -#define ADC_CHANNEL1 0x1 -#define ADC_CHANNEL2 0x2 -#define ADC_CHANNEL3 0x3 -#define ADC_CHANNEL4 0x4 -#define ADC_CHANNEL5 0x5 -#define ADC_CHANNEL6 0x6 -#define ADC_CHANNEL7 0x7 -#define ADC_CHANNEL8 0x8 -#define ADC_CHANNEL9 0x9 -#define ADC_CHANNEL10 0xA -#define ADC_CHANNEL11 0xB -#define ADC_CHANNEL12 0xC -#define ADC_CHANNEL13 0xD -#define ADC_CHANNEL14 0xE -#define ADC_CHANNEL15 0xF - -/* ADC DMA Channels */ -#define ADC_DMA_CHANNEL0 0x0001 -#define ADC_DMA_CHANNEL1 0x0002 -#define ADC_DMA_CHANNEL2 0x0004 -#define ADC_DMA_CHANNEL3 0x0008 -#define ADC_DMA_CHANNEL4 0x0010 -#define ADC_DMA_CHANNEL5 0x0020 -#define ADC_DMA_CHANNEL6 0x0040 -#define ADC_DMA_CHANNEL7 0x0080 -#define ADC_DMA_CHANNEL8 0x0100 -#define ADC_DMA_CHANNEL9 0x0200 -#define ADC_DMA_CHANNEL10 0x0400 -#define ADC_DMA_CHANNEL11 0x0800 -#define ADC_DMA_CHANNEL12 0x1000 -#define ADC_DMA_CHANNEL13 0x2000 -#define ADC_DMA_CHANNEL14 0x4000 -#define ADC_DMA_CHANNEL15 0x8000 - -/* Trigger conversion detection */ -#define ADC_ExtTrigger_LowLevel 0x4FFF -#define ADC_ExtTrigger_HighLevel 0x5000 -#define ADC_ExtTrigger_FallingEdge 0x6000 -#define ADC_ExtTrigger_RisingEdge 0x7000 -#define ADC_ExtTrigger_Disable 0x8FFF - -/* DMA enable config */ -#define ADC_DMA_ExtTrigger_HighLevel 0x6000 -#define ADC_DMA_ExtTrigger_LowLevel 0x4FFF -#define ADC_DMA_Enable 0x8000 -#define ADC_DMA_Disable 0x3FFF - -/* Injected Trigger conversion detection */ -#define ADC_Injec_ExtTrigger_RisingEdge 0x6000 -#define ADC_Injec_ExtTrigger_FallingEdge 0xDFFF -#define ADC_Injec_ExtTrigger_Disable 0x3FFF - -/* Start Conversion */ -#define ADC_Conversion_Start 0x0001 -#define ADC_Conversion_Stop 0xFFFE - -/* ADC Conversion Modes */ -#define ADC_ConversionMode_Scan 0x8000 -#define ADC_ConversionMode_OneShot 0x7FFF - -/* Auto Clock Off */ -#define ADC_AutoClockOff_Enable 0x4000 -#define ADC_AutoClockOff_Disable 0xBFFF - -/* Calibration */ -#define ADC_Calibration_ON 0x0002 -#define ADC_CalibAverage_Disable 0x0020 -#define ADC_CalibAverage_Enable 0xFFDF - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -void ADC_DeInit(void); -void ADC_Init(ADC_InitTypeDef *ADC_InitStruct); -void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct); -void ADC_Cmd(FunctionalState NewState); -void ADC_StartCalibration(u16 ADC_CalibAverage); -FlagStatus ADC_GetCalibrationStatus(void); -void ADC_ConversionCmd(u16 ADC_Conversion); -FlagStatus ADC_GetSTARTBitStatus(void); -void ADC_AutoClockOffConfig(FunctionalState NewState); -u16 ADC_GetConversionValue(u8 ADC_CHANNEL); -void ADC_ITConfig(u16 ADC_IT, FunctionalState NewState); -void ADC_AnalogWatchdogConfig(u16 ADC_AnalogWatchdog, u8 ADC_CHANNEL, - u16 LowThreshold, u16 HighThreshold); -void ADC_AnalogWatchdogCmd(u16 ADC_AnalogWatchdog, FunctionalState NewState); -u16 ADC_GetAnalogWatchdogResult(u16 ADC_AnalogWatchdog); -void ADC_StartInjectedConversion(void); -void ADC_InjectedConversionConfig(u16 ADC_Injec_ExtTrigger, u8 FirstChannel, u8 ChannelNumber); -void ADC_DMAConfig(u16 ADC_DMA_CHANNEL, FunctionalState NewState); -void ADC_DMACmd(u16 ADC_DMA); -u16 ADC_GetDMAFirstEnabledChannel(void); -FlagStatus ADC_GetFlagStatus(u16 ADC_FLAG); -void ADC_ClearFlag(u16 ADC_FLAG); -ITStatus ADC_GetITStatus(u16 ADC_IT); -void ADC_ClearITPendingBit(u16 ADC_IT); - -#endif /*__75x_ADC_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_can.h b/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_can.h deleted file mode 100644 index 9b630ee0c..000000000 --- a/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_can.h +++ /dev/null @@ -1,165 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_can.h -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file contains all the functions prototypes for the -* CAN bus software library. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __75x_CAN_H -#define __75x_CAN_H - -/* Includes ------------------------------------------------------------------*/ -#include "75x_map.h" - -/* Exported types ------------------------------------------------------------*/ - -/* CAN Init structure define */ -typedef struct -{ - u8 CAN_ConfigParameters; - u32 CAN_Bitrate; -}CAN_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ -/* Standard bitrates available*/ -enum -{ - CAN_BITRATE_100K, - CAN_BITRATE_125K, - CAN_BITRATE_250K, - CAN_BITRATE_500K, - CAN_BITRATE_1M -}; - -/* Control register*/ -#define CAN_CR_TEST 0x0080 -#define CAN_CR_CCE 0x0040 -#define CAN_CR_DAR 0x0020 -#define CAN_CR_EIE 0x0008 -#define CAN_CR_SIE 0x0004 -#define CAN_CR_IE 0x0002 -#define CAN_CR_INIT 0x0001 - -/* Status register */ -#define CAN_SR_BOFF 0x0080 -#define CAN_SR_EWARN 0x0040 -#define CAN_SR_EPASS 0x0020 -#define CAN_SR_RXOK 0x0010 -#define CAN_SR_TXOK 0x0008 -#define CAN_SR_LEC 0x0007 - -/* Test register*/ -#define CAN_TESTR_RX 0x0080 -#define CAN_TESTR_TX1 0x0040 -#define CAN_TESTR_TX0 0x0020 -#define CAN_TESTR_LBACK 0x0010 -#define CAN_TESTR_SILENT 0x0008 -#define CAN_TESTR_BASIC 0x0004 - -/* IFn / Command Request register*/ -#define CAN_CRR_BUSY 0x8000 - -/* IFn / Command Mask register*/ -#define CAN_CMR_WRRD 0x0080 -#define CAN_CMR_MASK 0x0040 -#define CAN_CMR_ARB 0x0020 -#define CAN_CMR_CONTROL 0x0010 -#define CAN_CMR_CLRINTPND 0x0008 -#define CAN_CMR_TXRQSTNEWDAT 0x0004 -#define CAN_CMR_DATAA 0x0002 -#define CAN_CMR_DATAB 0x0001 - -/* IFn / Mask 2 register*/ -#define CAN_M2R_MXTD 0x8000 -#define CAN_M2R_MDIR 0x4000 - -/* IFn / Arbitration 2 register*/ -#define CAN_A2R_MSGVAL 0x8000 -#define CAN_A2R_XTD 0x4000 -#define CAN_A2R_DIR 0x2000 - -/* IFn / Message Control register*/ -#define CAN_MCR_NEWDAT 0x8000 -#define CAN_MCR_MSGLST 0x4000 -#define CAN_MCR_INTPND 0x2000 -#define CAN_MCR_UMASK 0x1000 -#define CAN_MCR_TXIE 0x0800 -#define CAN_MCR_RXIE 0x0400 -#define CAN_MCR_RMTEN 0x0200 -#define CAN_MCR_TXRQST 0x0100 -#define CAN_MCR_EOB 0x0080 - - -/* Wake-up modes*/ -enum -{ - CAN_WAKEUP_ON_EXT, - CAN_WAKEUP_ON_CAN -}; - - -/* CAN message structure*/ -typedef struct -{ - u32 IdType; - u32 Id; - u8 Dlc; - u8 Data[8]; -} canmsg; - -/* Message ID types*/ -enum -{ - CAN_STD_ID, - CAN_EXT_ID -}; - -/* Message ID limits*/ - -#define CAN_LAST_STD_ID ((1<<11) - 1) -#define CAN_LAST_EXT_ID ((1L<<29) - 1) - -/* Exported functions ------------------------------------------------------- */ - -void CAN_Init (CAN_InitTypeDef *CAN_InitStruct); -void CAN_DeInit (void); -void CAN_StructInit(CAN_InitTypeDef *CAN_InitStruct); -void CAN_SetBitrate(u32 bitrate); -void CAN_SetTiming(u32 tseg1, u32 tseg2, u32 sjw, u32 brp); -ErrorStatus CAN_SetUnusedMsgObj(u32 msgobj); -ErrorStatus CAN_SetTxMsgObj(u32 msgobj, u32 idType); -ErrorStatus CAN_SetRxMsgObj(u32 msgobj, u32 idType, u32 idLow, u32 idHigh, bool singleOrFifoLast); -void CAN_InvalidateAllMsgObj(void); -ErrorStatus CAN_ReleaseMessage(u32 msgobj); -ErrorStatus CAN_SendMessage(u32 msgobj, canmsg* pCanMsg); -ErrorStatus CAN_ReceiveMessage(u32 msgobj, bool release, canmsg* pCanMsg); -ErrorStatus CAN_WaitEndOfTx(void); -ErrorStatus CAN_BasicSendMessage(canmsg* pCanMsg); -ErrorStatus CAN_BasicReceiveMessage(canmsg* pCanMsg); -void CAN_EnterTestMode(u8 TestMask); -void CAN_EnterInitMode(u8 InitMask); -void CAN_LeaveInitMode(void); -void CAN_LeaveTestMode(void); -void CAN_ReleaseTxMessage(u32 msgobj); -void CAN_ReleaseRxMessage(u32 msgobj); -u32 CAN_IsMessageWaiting(u32 msgobj); -u32 CAN_IsTransmitRequested(u32 msgobj); -u32 CAN_IsInterruptPending(u32 msgobj); -u32 CAN_IsObjectValid(u32 msgobj); - -#endif /* __75x_CAN_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_cfg.h b/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_cfg.h deleted file mode 100644 index e1042a246..000000000 --- a/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_cfg.h +++ /dev/null @@ -1,48 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_cfg.h -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file contains all the functions prototypes for the -* CFG software library. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __75x_CFG_H -#define __75x_CFG_H - -/* Includes ------------------------------------------------------------------*/ -#include "75x_map.h" - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -#define CFG_BootSpace_FLASH 0x00000000 -#define CFG_BootSpace_SRAM 0x00000002 -#define CFG_BootSpace_ExtSMI 0x00000003 - -#define CFG_FLASHBurst_Disable 0xFFFFFEFF -#define CFG_FLASHBurst_Enable 0x00000100 - -#define CFG_USBFilter_Disable 0xFFFFFDFF -#define CFG_USBFilter_Enable 0x00000200 - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -void CFG_BootSpaceConfig(u32 CFG_BootSpace); -void CFG_FLASHBurstConfig(u32 CFG_FLASHBurst); -void CFG_USBFilterConfig(u32 CFG_USBFilter); -FlagStatus CFG_GetFlagStatus(void); - -#endif /* __75x_CFG_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_conf.h b/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_conf.h deleted file mode 100644 index ab3c5394f..000000000 --- a/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_conf.h +++ /dev/null @@ -1,106 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_conf.h -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : Library configuration file. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __75x_CONF_H -#define __75x_CONF_H - -/* Includes ------------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Comment the line below to compile the library in release mode */ -//#define DEBUG - -/************************************* SMI ************************************/ -//#define _SMI - -/************************************* CFG ************************************/ -#define _CFG - -/************************************* MRCC ************************************/ -#define _MRCC - -/************************************* ADC ************************************/ -//#define _ADC - -/************************************* TB *************************************/ -#define _TB - -/************************************* TIM ************************************/ -#define _TIM -#define _TIM0 -#define _TIM1 -#define _TIM2 - -/************************************* PWM ************************************/ -#define _PWM - -/************************************* WDG ************************************/ -#define _WDG - -/************************************* SSP ************************************/ -//#define _SSP -//#define _SSP0 -//#define _SSP1 - -/************************************* CAN ************************************/ -//#define _CAN - -/************************************* I2C ************************************/ -//#define _I2C - -/************************************* UART ***********************************/ -#define _UART -#define _UART0 -#define _UART1 -#define _UART2 - -/************************************* GPIO ***********************************/ -#define _GPIO -#define _GPIO0 -#define _GPIO1 -#define _GPIO2 -#define _GPIOREMAP - -/************************************* DMA ************************************/ -//#define _DMA -//#define _DMA_Stream0 -//#define _DMA_Stream1 -//#define _DMA_Stream2 -//#define _DMA_Stream3 - -/************************************* RTC ************************************/ -//#define _RTC - -/************************************* EXTIT **********************************/ -#define _EXTIT - -/************************************* EIC ************************************/ -#define _EIC - -/* Comment the following line, depending on the external Quartz oscillator used - in your application */ -#define Main_Oscillator 4000000 /* 4 MHz Quartz oscillator used */ -//#define Main_Oscillator 8000000 /* 8 MHz Quartz oscillator used */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -#endif /* __75x_CONF_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_dma.h b/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_dma.h deleted file mode 100644 index f71b1cad4..000000000 --- a/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_dma.h +++ /dev/null @@ -1,140 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_dma.h -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file contains all the functions prototypes for the -* DMA software library. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion ------------------------------------ */ -#ifndef __75x_DMA_H -#define __75x_DMA_H - -/* Includes ------------------------------------------------------------------*/ -#include "75x_map.h" - -/* Exported types ------------------------------------------------------------*/ -/* DMA Init structure definition */ -typedef struct -{ - u32 DMA_SRCBaseAddr; - u32 DMA_DSTBaseAddr; - u16 DMA_BufferSize; - u16 DMA_SRC; - u16 DMA_DST; - u16 DMA_SRCSize; - u16 DMA_SRCBurst; - u16 DMA_DSTSize; - u16 DMA_Mode; - u16 DMA_M2M; - u16 DMA_DIR; -}DMA_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ -/* DMA interrupt Mask */ -#define DMA_IT_SI0 0x0001 -#define DMA_IT_SI1 0x0002 -#define DMA_IT_SI2 0x0004 -#define DMA_IT_SI3 0x0008 -#define DMA_IT_SE0 0x0010 -#define DMA_IT_SE1 0x0020 -#define DMA_IT_SE2 0x0040 -#define DMA_IT_SE3 0x0080 -#define DMA_IT_ALL 0x00FF - -/* DMA Flags */ -#define DMA_FLAG_SI0 0x0001 -#define DMA_FLAG_SI1 0x0002 -#define DMA_FLAG_SI2 0x0004 -#define DMA_FLAG_SI3 0x0008 -#define DMA_FLAG_SE0 0x0010 -#define DMA_FLAG_SE1 0x0020 -#define DMA_FLAG_SE2 0x0040 -#define DMA_FLAG_SE3 0x0080 -#define DMA_FLAG_ACT0 0x0100 -#define DMA_FLAG_ACT1 0x0200 -#define DMA_FLAG_ACT2 0x0400 -#define DMA_FLAG_ACT3 0x0800 - -/* DMA Increment Current Source Register */ -#define DMA_SRC_INCR 0x0002 -#define DMA_SRC_NOT_INCR 0xFFFD - -/* DMA Increment Current Destination Register */ -#define DMA_DST_INCR 0x0004 -#define DMA_DST_NOT_INCR 0xFFFB - -/* Source to DMA data width */ -#define DMA_SRCSize_Byte 0x0000 -#define DMA_SRCSize_HalfWord 0x0008 -#define DMA_SRCSize_Word 0x0010 - -/* DMA source burst size */ -#define DMA_SRCBurst_1Data 0x0000 -#define DMA_SRCBurst_4Data 0x0020 -#define DMA_SRCBurst_8Data 0x0040 -#define DMA_SRCBurst_16Data 0x0060 - -/* DMA destination data width */ -#define DMA_DSTSize_Byte 0x0000 -#define DMA_DSTSize_HalfWord 0x0080 -#define DMA_DSTSize_Word 0x0100 - -/* DMA mode */ -#define DMA_Mode_Circular 0x0200 -#define DMA_Mode_Normal 0xFDFF - -/* Memory to Memory Transfer */ -#define DMA_M2M_Enable 0x0800 -#define DMA_M2M_Disable 0xF7FF - -/* Direction Transfer */ -#define DMA_DIR_PeriphDST 0x2000 -#define DMA_DIR_PeriphSRC 0xDFFF - -/* DMA streamx Registers */ -#define DMA_SOURCEL 0x00000000 /* source base address low register */ -#define DMA_SOURCEH 0x00000004 /* source base address high register */ -#define DMA_DESTL 0x00000008 /* destination base address low register */ -#define DMA_DESTH 0x0000000C /* destination base address high register */ -#define DMA_MAX 0x00000010 /* Maximum count register */ -#define DMA_CTRL 0x00000014 /* Control register */ -#define DMA_SOCURRH 0x00000018 /* Current Source address high register */ -#define DMA_SOCURRL 0x0000001C /* Current Source address low register */ -#define DMA_DECURRH 0x00000020 /* Current Destination address high register */ -#define DMA_DECURRL 0x00000024 /* Current Destination address low register */ -#define DMA_TCNT 0x00000028 /* Terminal Counter Register */ -#define DMA_LUBUFF 0x0000002C /* Last Used Buffer location */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -void DMA_DeInit(DMA_Stream_TypeDef* DMA_Streamx); -void DMA_Init(DMA_Stream_TypeDef* DMA_Streamx, DMA_InitTypeDef* DMA_InitStruct); -void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); -void DMA_Cmd(DMA_Stream_TypeDef* DMA_Streamx, FunctionalState NewState); -void DMA_ITConfig(u16 DMA_IT, FunctionalState NewState); -u32 DMA_GetCurrDSTAddr(DMA_Stream_TypeDef* DMA_Streamx); -u32 DMA_GetCurrSRCAddr(DMA_Stream_TypeDef* DMA_Streamx); -u16 DMA_GetTerminalCounter(DMA_Stream_TypeDef* DMA_Streamx); -void DMA_LastBufferSweepConfig(DMA_Stream_TypeDef* DMA_Streamx, FunctionalState NewState); -void DMA_LastBufferAddrConfig(DMA_Stream_TypeDef* DMA_Streamx, u16 DMA_LastBufferAddr); -FlagStatus DMA_GetFlagStatus(u16 DMA_FLAG); -void DMA_ClearFlag(u16 DMA_FLAG); -ITStatus DMA_GetITStatus(u16 DMA_IT); -void DMA_ClearITPendingBit(u16 DMA_IT); - -#endif /* __75x_DMA_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_eic.h b/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_eic.h deleted file mode 100644 index c7e6a07cf..000000000 --- a/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_eic.h +++ /dev/null @@ -1,97 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_eic.h -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file contains all the functions prototypes for the -* EIC software library. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __75x_EIC_H -#define __75x_EIC_H - -/* Includes ------------------------------------------------------------------*/ -#include "75x_map.h" - -/* Exported types ------------------------------------------------------------*/ -typedef struct -{ - u8 EIC_IRQChannel; - u8 EIC_IRQChannelPriority; - FunctionalState EIC_IRQChannelCmd; -}EIC_IRQInitTypeDef; - -typedef struct -{ - u8 EIC_FIQChannel; - FunctionalState EIC_FIQChannelCmd; -}EIC_FIQInitTypeDef; - -/* Exported constants --------------------------------------------------------*/ -/* IRQ channels */ -#define WAKUP_IRQChannel 0 -#define TIM2_OC2_IRQChannel 1 -#define TIM2_OC1_IRQChannel 2 -#define TIM2_IC12_IRQChannel 3 -#define TIM2_UP_IRQChannel 4 -#define TIM1_OC2_IRQChannel 5 -#define TIM1_OC1_IRQChannel 6 -#define TIM1_IC12_IRQChannel 7 -#define TIM1_UP_IRQChannel 8 -#define TIM0_OC2_IRQChannel 9 -#define TIM0_OC1_IRQChannel 10 -#define TIM0_IC12_IRQChannel 11 -#define TIM0_UP_IRQChannel 12 -#define PWM_OC123_IRQChannel 13 -#define PWM_EM_IRQChannel 14 -#define PWM_UP_IRQChannel 15 -#define I2C_IRQChannel 16 -#define SSP1_IRQChannel 17 -#define SSP0_IRQChannel 18 -#define UART2_IRQChannel 19 -#define UART1_IRQChannel 20 -#define UART0_IRQChannel 21 -#define CAN_IRQChannel 22 -#define USB_LP_IRQChannel 23 -#define USB_HP_IRQChannel 24 -#define ADC_IRQChannel 25 -#define DMA_IRQChannel 26 -#define EXTIT_IRQChannel 27 -#define MRCC_IRQChannel 28 -#define FLASHSMI_IRQChannel 29 -#define RTC_IRQChannel 30 -#define TB_IRQChannel 31 - -/* FIQ channels */ -#define EXTIT_Line0_FIQChannel 0x00000001 -#define WATCHDOG_FIQChannel 0x00000002 - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -void EIC_DeInit(void); -void EIC_IRQInit(EIC_IRQInitTypeDef* EIC_IRQInitStruct); -void EIC_FIQInit(EIC_FIQInitTypeDef* EIC_FIQInitStruct); -void EIC_IRQStructInit(EIC_IRQInitTypeDef* EIC_IRQInitStruct); -void EIC_FIQStructInit(EIC_FIQInitTypeDef* EIC_FIQInitStruct); -void EIC_IRQCmd(FunctionalState NewState); -void EIC_FIQCmd(FunctionalState NewState); -u8 EIC_GetCurrentIRQChannel(void); -u8 EIC_GetCurrentIRQChannelPriority(void); -void EIC_CurrentIRQPriorityConfig(u8 NewPriority); -u8 EIC_GetCurrentFIQChannel(void); -void EIC_ClearFIQPendingBit(u8 EIC_FIQChannel); - -#endif /* __75x_EIC_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_extit.h b/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_extit.h deleted file mode 100644 index 5dbbc3a09..000000000 --- a/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_extit.h +++ /dev/null @@ -1,77 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_extit.h -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file contains all the functions prototypes for the -* EXTIT software library. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __75x_EXTIT_H -#define __75x_EXTIT_H - -/* Includes ------------------------------------------------------------------*/ -#include "75x_map.h" - -/* Exported types ------------------------------------------------------------*/ -/* EXTIT Trigger enumeration */ -typedef enum -{ - EXTIT_ITTrigger_Falling = 1, - EXTIT_ITTrigger_Rising -}EXTITTrigger_TypeDef; - -/* EXTIT Init Structure definition */ -typedef struct -{ - u32 EXTIT_ITLine; - EXTITTrigger_TypeDef EXTIT_ITTrigger; - FunctionalState EXTIT_ITLineCmd; -}EXTIT_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ -/* EXTIT Lines */ -#define EXTIT_ITLineNone 0x0000 /* No interrupt selected */ -#define EXTIT_ITLine0 0x0001 /* External interrupt line 0 */ -#define EXTIT_ITLine1 0x0002 /* External interrupt line 1 */ -#define EXTIT_ITLine2 0x0004 /* External interrupt line 2 */ -#define EXTIT_ITLine3 0x0008 /* External interrupt line 3 */ -#define EXTIT_ITLine4 0x0010 /* External interrupt line 4 */ -#define EXTIT_ITLine5 0x0020 /* External interrupt line 5 */ -#define EXTIT_ITLine6 0x0040 /* External interrupt line 6 */ -#define EXTIT_ITLine7 0x0080 /* External interrupt line 7 */ -#define EXTIT_ITLine8 0x0100 /* External interrupt line 8 */ -#define EXTIT_ITLine9 0x0200 /* External interrupt line 9 */ -#define EXTIT_ITLine10 0x0400 /* External interrupt line 10 */ -#define EXTIT_ITLine11 0x0800 /* External interrupt line 11 */ -#define EXTIT_ITLine12 0x1000 /* External interrupt line 12 */ -#define EXTIT_ITLine13 0x2000 /* External interrupt line 13 */ -#define EXTIT_ITLine14 0x4000 /* External interrupt line 14 */ -#define EXTIT_ITLine15 0x8000 /* External interrupt line 15 */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -void EXTIT_DeInit(void); -void EXTIT_Init(EXTIT_InitTypeDef* EXTIT_InitStruct); -void EXTIT_StructInit(EXTIT_InitTypeDef* EXTIT_InitStruct); -void EXTIT_GenerateSWInterrupt(u16 EXTIT_ITLine); -FlagStatus EXTIT_GetFlagStatus(u16 EXTIT_ITLine); -void EXTIT_ClearFlag(u16 EXTIT_ITLine); -ITStatus EXTIT_GetITStatus(u16 EXTIT_ITLine); -void EXTIT_ClearITPendingBit(u16 EXTIT_ITLine); - -#endif /* __75x_EXTIT_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_gpio.h b/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_gpio.h deleted file mode 100644 index 53aad69ca..000000000 --- a/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_gpio.h +++ /dev/null @@ -1,120 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_gpio.h -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file contains all the functions prototypes for the -* GPIO software library. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __75x_GPIO_H -#define __75x_GPIO_H - -/* Includes ------------------------------------------------------------------*/ -#include "75x_map.h" - -/* Exported types ------------------------------------------------------------*/ -/* Configuration Mode enumeration */ -typedef enum -{ GPIO_Mode_AIN = 1, - GPIO_Mode_IN_FLOATING, - GPIO_Mode_IPD, - GPIO_Mode_IPU, - GPIO_Mode_Out_OD, - GPIO_Mode_Out_PP, - GPIO_Mode_AF_OD, - GPIO_Mode_AF_PP -}GPIOMode_TypeDef; - -/* GPIO Init structure definition */ -typedef struct -{ - u32 GPIO_Pin; - GPIOMode_TypeDef GPIO_Mode; -}GPIO_InitTypeDef; - -/* Bit_SET and Bit_RESET enumeration */ -typedef enum -{ Bit_RESET = 0, - Bit_SET -}BitAction; - - -/* Exported constants --------------------------------------------------------*/ -/* GPIO pins define */ -#define GPIO_Pin_None 0x00000000 /* No pin selected */ -#define GPIO_Pin_0 0x00000001 /* Pin 0 selected */ -#define GPIO_Pin_1 0x00000002 /* Pin 1 selected */ -#define GPIO_Pin_2 0x00000004 /* Pin 2 selected */ -#define GPIO_Pin_3 0x00000008 /* Pin 3 selected */ -#define GPIO_Pin_4 0x00000010 /* Pin 4 selected */ -#define GPIO_Pin_5 0x00000020 /* Pin 5 selected */ -#define GPIO_Pin_6 0x00000040 /* Pin 6 selected */ -#define GPIO_Pin_7 0x00000080 /* Pin 7 selected */ -#define GPIO_Pin_8 0x00000100 /* Pin 8 selected */ -#define GPIO_Pin_9 0x00000200 /* Pin 9 selected */ -#define GPIO_Pin_10 0x00000400 /* Pin 10 selected */ -#define GPIO_Pin_11 0x00000800 /* Pin 11 selected */ -#define GPIO_Pin_12 0x00001000 /* Pin 12 selected */ -#define GPIO_Pin_13 0x00002000 /* Pin 13 selected */ -#define GPIO_Pin_14 0x00004000 /* Pin 14 selected */ -#define GPIO_Pin_15 0x00008000 /* Pin 15 selected */ -#define GPIO_Pin_16 0x00010000 /* Pin 16 selected */ -#define GPIO_Pin_17 0x00020000 /* Pin 17 selected */ -#define GPIO_Pin_18 0x00040000 /* Pin 18 selected */ -#define GPIO_Pin_19 0x00080000 /* Pin 19 selected */ -#define GPIO_Pin_20 0x00100000 /* Pin 20 selected */ -#define GPIO_Pin_21 0x00200000 /* Pin 21 selected */ -#define GPIO_Pin_22 0x00400000 /* Pin 22 selected */ -#define GPIO_Pin_23 0x00800000 /* Pin 23 selected */ -#define GPIO_Pin_24 0x01000000 /* Pin 24 selected */ -#define GPIO_Pin_25 0x02000000 /* Pin 25 selected */ -#define GPIO_Pin_26 0x04000000 /* Pin 26 selected */ -#define GPIO_Pin_27 0x08000000 /* Pin 27 selected */ -#define GPIO_Pin_28 0x10000000 /* Pin 28 selected */ -#define GPIO_Pin_29 0x20000000 /* Pin 29 selected */ -#define GPIO_Pin_30 0x40000000 /* Pin 30 selected */ -#define GPIO_Pin_31 0x80000000 /* Pin 31 selected */ -#define GPIO_Pin_All 0xFFFFFFFF /* All pins selected */ - -/* GPIO Remap define */ -#define GPIO_Remap_SMI_CS3_EN 0x23 /* SMI CS3 Enable */ -#define GPIO_Remap_SMI_CS2_EN 0x22 /* SMI CS2 Enable */ -#define GPIO_Remap_SMI_CS1_EN 0x21 /* SMI CS1 Enable */ -#define GPIO_Remap_SMI_EN 0x20 /* SMI Enable */ -#define GPIO_Remap_DBGOFF 0x45 /* JTAG Disable */ -#define GPIO_Remap_UART1 0x44 /* UART1 Alternate Function mapping */ -#define GPIO_Remap_UART2 0x43 /* UART2 Alternate Function mapping */ -#define GPIO_Remap_SSP1 0x42 /* SSP1 Alternate Function mapping */ -#define GPIO_Remap_TIM2 0x41 /* TIM2 Alternate Function mapping */ -#define GPIO_Remap_TIM0 0x40 /* TIM0 Alternate Function mapping */ - - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -void GPIO_DeInit(GPIO_TypeDef* GPIOx); -void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); -void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); -u32 GPIO_Read(GPIO_TypeDef* GPIOx); -u8 GPIO_ReadBit(GPIO_TypeDef* GPIOx, u32 GPIO_Pin); -void GPIO_Write(GPIO_TypeDef* GPIOx, u32 PortVal); -void GPIO_WriteBit(GPIO_TypeDef* GPIOx,u32 GPIO_Pin, BitAction BitVal); -void GPIO_PinMaskConfig(GPIO_TypeDef* GPIOx, u32 GPIO_Pin, FunctionalState NewState); -u32 GPIO_GetPortMask(GPIO_TypeDef* GPIOx); -void GPIO_PinRemapConfig(u16 GPIO_Remap, FunctionalState NewState); - -#endif /* __75x_GPIO_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_i2c.h b/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_i2c.h deleted file mode 100644 index 0e3a8c511..000000000 --- a/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_i2c.h +++ /dev/null @@ -1,115 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_i2c.h -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file contains all the functions prototypes for the -* I2C software library. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion ------------------------------------ */ -#ifndef __75x_I2C_H -#define __75x_I2C_H - -/* Includes ----------------------------------------------------------------- */ -#include "75x_map.h" - -/* Exported types ----------------------------------------------------------- */ -/* I2C Init structure definition */ -typedef struct -{ - u32 I2C_CLKSpeed; - u16 I2C_OwnAddress; - u8 I2C_GeneralCall; - u8 I2C_Ack; -}I2C_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ -/* General Call */ -#define I2C_GeneralCall_Enable 0x10 -#define I2C_GeneralCall_Disable 0xEF - -/* Acknowledgement */ -#define I2C_Ack_Enable 0x04 -#define I2C_Ack_Disable 0xFB - -/* I2C Flags */ -#define I2C_FLAG_SB 0x0001 -#define I2C_FLAG_M_SL 0x0002 -#define I2C_FLAG_ADSL 0x0004 -#define I2C_FLAG_BTF 0x0008 -#define I2C_FLAG_BUSY 0x0010 -#define I2C_FLAG_TRA 0x0020 -#define I2C_FLAG_ADD10 0x0040 -#define I2C_FLAG_EVF 0x0080 -#define I2C_FLAG_GCAL 0x0100 -#define I2C_FLAG_BERR 0x0200 -#define I2C_FLAG_ARLO 0x0400 -#define I2C_FLAG_STOPF 0x0800 -#define I2C_FLAG_AF 0x1000 -#define I2C_FLAG_ENDAD 0x2000 -#define I2C_FLAG_ACK 0x4000 - -/* I2C Events */ -#define I2C_EVENT_SLAVE_ADDRESS_MATCHED ( I2C_FLAG_EVF | I2C_FLAG_BUSY |I2C_FLAG_ADSL) -#define I2C_EVENT_SLAVE_BYTE_RECEIVED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_BTF ) -#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_BTF | I2C_FLAG_TRA ) -#define I2C_EVENT_MASTER_MODE_SELECT ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL | I2C_FLAG_SB ) -#define I2C_EVENT_MASTER_MODE_SELECTED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL | I2C_FLAG_ENDAD ) -#define I2C_EVENT_MASTER_BYTE_RECEIVED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL | I2C_FLAG_BTF ) -#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL | I2C_FLAG_BTF | I2C_FLAG_TRA ) -#define I2C_EVENT_MASTER_MODE_ADDRESS10 ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL |I2C_FLAG_ADD10 ) -#define I2C_EVENT_SLAVE_STOP_DETECTED I2C_FLAG_STOPF -#define I2C_EVENT_SLAVE_ACK_FAILURE ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_BTF | I2C_FLAG_TRA | I2C_FLAG_AF) - -#define I2C_BUS_ERROR_DETECTED I2C_FLAG_BERR -#define I2C_ARBITRATION_LOST I2C_FLAG_ARLO -#define I2C_SLAVE_GENERAL_CALL (I2C_FLAG_BUSY | I2C_FLAG_GCAL) - -/* Master/Receiver Mode */ -#define I2C_MODE_TRANSMITTER 0x00 -#define I2C_MODE_RECEIVER 0x01 - -/* I2C Registers offset */ -#define I2C_CR 0x00 -#define I2C_SR1 0x04 -#define I2C_SR2 0x08 -#define I2C_CCR 0x0C -#define I2C_OAR1 0x10 -#define I2C_OAR2 0x14 -#define I2C_DR 0x18 -#define I2C_ECCR 0x1C - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -void I2C_DeInit(void); -void I2C_Init(I2C_InitTypeDef* I2C_InitStruct); -void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); -void I2C_Cmd(FunctionalState NewState); -void I2C_GenerateSTART(FunctionalState NewState); -void I2C_GenerateSTOP(FunctionalState NewState); -void I2C_AcknowledgeConfig(FunctionalState NewState); -void I2C_ITConfig(FunctionalState NewState); -u16 I2C_GetLastEvent(void); -ErrorStatus I2C_CheckEvent(u16 I2C_EVENT); -void I2C_SendData(u8 Data); -u8 I2C_ReceiveData(void); -void I2C_Send7bitAddress(u8 Address, u8 Direction); -u8 I2C_ReadRegister(u8 I2C_Register); -FlagStatus I2C_GetFlagStatus(u16 I2C_FLAG); -void I2C_ClearFlag(u16 I2C_FLAG, ...); - -#endif /* __75x_I2C_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_lib.h b/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_lib.h deleted file mode 100644 index 8048ffcc3..000000000 --- a/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_lib.h +++ /dev/null @@ -1,103 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_lib.h -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file includes the peripherals header files in the -* user application. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __75x_LIB_H -#define __75x_LIB_H - -/* Includes ------------------------------------------------------------------*/ -#include "75x_map.h" - -#ifdef _SMI - #include "75x_smi.h" -#endif /*_SMI */ - -#ifdef _CFG - #include "75x_cfg.h" -#endif /*_CFG*/ - -#ifdef _MRCC - #include "75x_mrcc.h" -#endif /*_MRCC */ - -#ifdef _ADC - #include "75x_adc.h" -#endif /*_ADC */ - -#ifdef _TB - #include "75x_tb.h" -#endif /*_TB */ - -#ifdef _TIM - #include "75x_tim.h" -#endif /*_TIM */ - -#ifdef _PWM - #include "75x_pwm.h" -#endif /*_PWM */ - -#ifdef _WDG - #include "75x_wdg.h" -#endif /*_WDG */ - -#ifdef _SSP - #include "75x_ssp.h" -#endif /*_SSP */ - -#ifdef _CAN - #include "75x_can.h" -#endif /*_CAN */ - -#ifdef _I2C - #include "75x_i2c.h" -#endif /*_I2C */ - -#ifdef _UART - #include "75x_uart.h" -#endif /*_UART */ - -#ifdef _GPIO - #include "75x_gpio.h" -#endif /*_GPIO */ - -#ifdef _DMA - #include "75x_dma.h" -#endif /*_DMA */ - -#ifdef _RTC - #include "75x_rtc.h" -#endif /*_RTC */ - -#ifdef _EXTIT - #include "75x_extit.h" -#endif /*_EXTIT */ - -#ifdef _EIC - #include "75x_eic.h" -#endif /*_EIC */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -void debug(void); - -#endif /* __75x_LIB_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_map.h b/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_map.h deleted file mode 100644 index d000f1b45..000000000 --- a/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_map.h +++ /dev/null @@ -1,697 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_map.h -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file contains all the peripheral register's definitions -* and memory mapping. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __75x_MAP_H -#define __75x_MAP_H - -#ifndef EXT - #define EXT extern -#endif /* EXT */ - -/* Includes ------------------------------------------------------------------*/ -#include "75x_conf.h" -#include "75x_type.h" - -/* Exported types ------------------------------------------------------------*/ -/******************************************************************************/ -/* IP registers structures */ -/******************************************************************************/ - -/*------------------------ Analog to Digital Converter -----------------------*/ -typedef struct -{ - vu16 CLR0; - u16 EMPTY1; - vu16 CLR1; - u16 EMPTY2; - vu16 CLR2; - u16 EMPTY3; - vu16 CLR3; - u16 EMPTY4; - vu16 CLR4; - u16 EMPTY5; - vu16 TRA0; - u16 EMPTY6; - vu16 TRA1; - u16 EMPTY7; - vu16 TRA2; - u16 EMPTY8; - vu16 TRA3; - u16 EMPTY9; - vu16 TRB0; - u16 EMPTY10; - vu16 TRB1; - u16 EMPTY11; - vu16 TRB2; - u16 EMPTY12; - vu16 TRB3; - u16 EMPTY13; - vu16 DMAR; - u16 EMPTY14[7]; - vu16 DMAE; - u16 EMPTY15 ; - vu16 PBR; - u16 EMPTY16; - vu16 IMR; - u16 EMPTY17; - vu16 D0; - u16 EMPTY18; - vu16 D1; - u16 EMPTY19; - vu16 D2; - u16 EMPTY20; - vu16 D3; - u16 EMPTY21; - vu16 D4; - u16 EMPTY22; - vu16 D5; - u16 EMPTY23; - vu16 D6; - u16 EMPTY24; - vu16 D7; - u16 EMPTY25; - vu16 D8; - u16 EMPTY26; - vu16 D9; - u16 EMPTY27; - vu16 D10; - u16 EMPTY28; - vu16 D11; - u16 EMPTY29; - vu16 D12; - u16 EMPTY30; - vu16 D13; - u16 EMPTY31; - vu16 D14; - u16 EMPTY32; - vu16 D15; - u16 EMPTY33; -} ADC_TypeDef; - -/*------------------------ Controller Area Network ---------------------------*/ -typedef struct -{ - vu16 CRR; - u16 EMPTY1; - vu16 CMR; - u16 EMPTY2; - vu16 M1R; - u16 EMPTY3; - vu16 M2R; - u16 EMPTY4; - vu16 A1R; - u16 EMPTY5; - vu16 A2R; - u16 EMPTY6; - vu16 MCR; - u16 EMPTY7; - vu16 DA1R; - u16 EMPTY8; - vu16 DA2R; - u16 EMPTY9; - vu16 DB1R; - u16 EMPTY10; - vu16 DB2R; - u16 EMPTY11[27]; -} CAN_MsgObj_TypeDef; - -typedef struct -{ - vu16 CR; - u16 EMPTY1; - vu16 SR; - u16 EMPTY2; - vu16 ERR; - u16 EMPTY3; - vu16 BTR; - u16 EMPTY4; - vu16 IDR; - u16 EMPTY5; - vu16 TESTR; - u16 EMPTY6; - vu16 BRPR; - u16 EMPTY7[3]; - CAN_MsgObj_TypeDef sMsgObj[2]; - u16 EMPTY8[16]; - vu16 TXR1R; - u16 EMPTY9; - vu16 TXR2R; - u16 EMPTY10[13]; - vu16 ND1R; - u16 EMPTY11; - vu16 ND2R; - u16 EMPTY12[13]; - vu16 IP1R; - u16 EMPTY13; - vu16 IP2R; - u16 EMPTY14[13]; - vu16 MV1R; - u16 EMPTY15; - vu16 MV2R; - u16 EMPTY16; -} CAN_TypeDef; - -/*--------------------------- Configuration Register -------------------------*/ -typedef struct -{ - vu32 GLCONF; -} CFG_TypeDef; - -/*-------------------------------- DMA Controller ----------------------------*/ -typedef struct -{ - vu16 SOURCEL; - u16 EMPTY1; - vu16 SOURCEH; - u16 EMPTY2; - vu16 DESTL; - u16 EMPTY3; - vu16 DESTH; - u16 EMPTY4; - vu16 MAX; - u16 EMPTY5; - vu16 CTRL; - u16 EMPTY6; - vuc16 SOCURRH; - u16 EMPTY7; - vuc16 SOCURRL; - u16 EMPTY8; - vuc16 DECURRH; - u16 EMPTY9; - vuc16 DECURRL; - u16 EMPTY10; - vuc16 TCNT; - u16 EMPTY11; - vu16 LUBUFF; - u16 EMPTY12; -} DMA_Stream_TypeDef; - -typedef struct -{ - vu16 MASK; - u16 EMPTY4; - vu16 CLR; - u16 EMPTY5; - vuc16 STATUS; - u16 EMPTY6; - vu16 LAST; - u16 EMPTY7; -} DMA_TypeDef; - -/*----------------------- Enhanced Interrupt Controller ----------------------*/ -typedef struct -{ - vu32 ICR; - vuc32 CICR; - vu32 CIPR; - u32 EMPTY1; - vu32 FIER; - vu32 FIPR; - vu32 IVR; - vu32 FIR; - vu32 IER; - u32 EMPTY2[7]; - vu32 IPR; - u32 EMPTY3[7]; - vu32 SIRn[32]; -} EIC_TypeDef; - -/*------------------------- External Interrupt Controller --------------------*/ -typedef struct -{ - vu32 MR; - vu32 TSR; - vu32 SWIR; - vu32 PR; -} EXTIT_TypeDef; - -/*-------------------------- General Purpose IO ports ------------------------*/ -typedef struct -{ - vu32 PC0; - vu32 PC1; - vu32 PC2; - vu32 PD; - vu32 PM; -} GPIO_TypeDef; - -typedef struct -{ - vu32 REMAP0R; - vu32 REMAP1R; -} GPIOREMAP_TypeDef; - -/*--------------------------------- I2C interface ----------------------------*/ -typedef struct -{ - vu8 CR; - u8 EMPTY1[3]; - vu8 SR1; - u8 EMPTY2[3]; - vu8 SR2; - u8 EMPTY3[3]; - vu8 CCR; - u8 EMPTY4[3]; - vu8 OAR1; - u8 EMPTY5[3]; - vu8 OAR2; - u8 EMPTY6[3]; - vu8 DR; - u8 EMPTY7[3]; - vu8 ECCR; - u8 EMPTY8[3]; -} I2C_TypeDef; - -/*---------------------------- Power, Reset and Clocks -----------------------*/ -typedef struct -{ - vu32 CLKCTL; - vu32 RFSR; - vu32 PWRCTRL; - u32 EMPTY1; - vu32 PCLKEN; - vu32 PSWRES; - u32 EMPTY2[2]; - vu32 BKP0; - vu32 BKP1; -} MRCC_TypeDef; - -/*-------------------------------- Real Time Clock ---------------------------*/ -typedef struct -{ - vu16 CRH; - u16 EMPTY; - vu16 CRL; - u16 EMPTY1; - vu16 PRLH; - u16 EMPTY2; - vu16 PRLL; - u16 EMPTY3; - vu16 DIVH; - u16 EMPTY4; - vu16 DIVL; - u16 EMPTY5; - vu16 CNTH; - u16 EMPTY6; - vu16 CNTL; - u16 EMPTY7; - vu16 ALRH; - u16 EMPTY8; - vu16 ALRL; - u16 EMPTY9; -} RTC_TypeDef; - -/*---------------------------- Serial Memory Interface -----------------------*/ -typedef struct -{ - vu32 CR1; - vu32 CR2; - vu32 SR; - vu32 TR; - vuc32 RR; -} SMI_TypeDef; - -/*--------------------------------- Timer Base -------------------------------*/ -typedef struct -{ - vu16 CR; - u16 EMPTY1; - vu16 SCR; - u16 EMPTY2; - vu16 IMCR; - u16 EMPTY3[7]; - vu16 RSR; - u16 EMPTY4; - vu16 RER; - u16 EMPTY5; - vu16 ISR; - u16 EMPTY6; - vu16 CNT; - u16 EMPTY7; - vu16 PSC; - u16 EMPTY8[3]; - vu16 ARR; - u16 EMPTY9[13]; - vu16 ICR1; - u16 EMPTY10; -} TB_TypeDef; - -/*------------------------------------ TIM -----------------------------------*/ -typedef struct -{ - vu16 CR; - u16 EMPTY1; - vu16 SCR; - u16 EMPTY2; - vu16 IMCR; - u16 EMPTY3; - vu16 OMR1; - u16 EMPTY4[5]; - vu16 RSR; - u16 EMPTY5; - vu16 RER; - u16 EMPTY6; - vu16 ISR; - u16 EMPTY7; - vu16 CNT; - u16 EMPTY8; - vu16 PSC; - u16 EMPTY9[3]; - vu16 ARR; - u16 EMPTY10; - vu16 OCR1; - u16 EMPTY11; - vu16 OCR2; - u16 EMPTY12[9]; - vu16 ICR1; - u16 EMPTY13; - vu16 ICR2; - u16 EMPTY14[9]; - vu16 DMAB; - u16 EMPTY15; -} TIM_TypeDef; - -/*------------------------------------ PWM -----------------------------------*/ -typedef struct -{ - vu16 CR; - u16 EMPTY1; - vu16 SCR; - u16 EMPTY2[3]; - vu16 OMR1; - u16 EMPTY3; - vu16 OMR2; - u16 EMPTY4[3]; - vu16 RSR; - u16 EMPTY5; - vu16 RER; - u16 EMPTY6; - vu16 ISR; - u16 EMPTY7; - vu16 CNT; - u16 EMPTY8; - vu16 PSC; - u16 EMPTY9; - vu16 RCR; - u16 EMPTY10; - vu16 ARR; - u16 EMPTY11; - vu16 OCR1; - u16 EMPTY12; - vu16 OCR2; - u16 EMPTY13; - vu16 OCR3; - u16 EMPTY14[15]; - vu16 DTR; - u16 EMPTY15; - vu16 DMAB; - u16 EMPTY16; -} PWM_TypeDef; - -/*----------------------- Synchronous Serial Peripheral ----------------------*/ -typedef struct -{ - vu32 CR0; - vu32 CR1; - vu32 DR; - vu32 SR; - vu32 PR; - vu32 IMSCR; - vu32 RISR; - vu32 MISR; - vu32 ICR; - vu32 DMACR; -} SSP_TypeDef; - -/*---------------- Universal Asynchronous Receiver Transmitter ---------------*/ -typedef struct -{ - vu16 DR; - u16 EMPTY; - vu16 RSR; - u16 EMPTY1[9]; - vu16 FR; - u16 EMPTY2; - vu16 BKR; - u16 EMPTY3[3]; - vu16 IBRD; - u16 EMPTY4; - vu16 FBRD; - u16 EMPTY5; - vu16 LCR; - u16 EMPTY6; - vu16 CR; - u16 EMPTY7; - vu16 IFLS; - u16 EMPTY8; - vu16 IMSC; - u16 EMPTY9; - vu16 RIS; - u16 EMPTY10; - vu16 MIS; - u16 EMPTY11; - vu16 ICR; - u16 EMPTY12; - vu16 DMACR; - u16 EMPTY13; -} UART_TypeDef; - -/*---------------------------------- WATCHDOG --------------------------------*/ -typedef struct -{ - vu16 CR; - u16 EMPTY1; - vu16 PR; - u16 EMPTY2; - vu16 VR; - u16 EMPTY3; - vu16 CNT; - u16 EMPTY4; - vu16 SR; - u16 EMPTY5; - vu16 MR; - u16 EMPTY6; - vu16 KR; - u16 EMPTY7; -} WDG_TypeDef; - -/******************************************************************************* -* Peripherals' Base addresses -*******************************************************************************/ - -#define SRAM_BASE 0x40000000 - -#define CONFIG_BASE 0x60000000 - -#define SMIR_BASE 0x90000000 - -#define PERIPH_BASE 0xFFFF0000 - -#define CFG_BASE (CONFIG_BASE + 0x0010) -#define MRCC_BASE (CONFIG_BASE + 0x0020) -#define ADC_BASE (PERIPH_BASE + 0x8400) -#define TB_BASE (PERIPH_BASE + 0x8800) -#define TIM0_BASE (PERIPH_BASE + 0x8C00) -#define TIM1_BASE (PERIPH_BASE + 0x9000) -#define TIM2_BASE (PERIPH_BASE + 0x9400) -#define PWM_BASE (PERIPH_BASE + 0x9800) -#define WDG_BASE (PERIPH_BASE + 0xB000) -#define SSP0_BASE (PERIPH_BASE + 0xB800) -#define SSP1_BASE (PERIPH_BASE + 0xBC00) -#define CAN_BASE (PERIPH_BASE + 0xC400) -#define I2C_BASE (PERIPH_BASE + 0xCC00) -#define UART0_BASE (PERIPH_BASE + 0xD400) -#define UART1_BASE (PERIPH_BASE + 0xD800) -#define UART2_BASE (PERIPH_BASE + 0xDC00) -#define GPIO0_BASE (PERIPH_BASE + 0xE400) -#define GPIOREMAP_BASE (PERIPH_BASE + 0xE420) -#define GPIO1_BASE (PERIPH_BASE + 0xE440) -#define GPIO2_BASE (PERIPH_BASE + 0xE480) -#define DMA_BASE (PERIPH_BASE + 0xECF0) -#define DMA_Stream0_BASE (PERIPH_BASE + 0xEC00) -#define DMA_Stream1_BASE (PERIPH_BASE + 0xEC40) -#define DMA_Stream2_BASE (PERIPH_BASE + 0xEC80) -#define DMA_Stream3_BASE (PERIPH_BASE + 0xECC0) -#define RTC_BASE (PERIPH_BASE + 0xF000) -#define EXTIT_BASE (PERIPH_BASE + 0xF400) -#define EIC_BASE (PERIPH_BASE + 0xF800) - -/******************************************************************************* - IPs' declaration -*******************************************************************************/ - -/*------------------- Non Debug Mode -----------------------------------------*/ - -#ifndef DEBUG - #define SMI ((SMI_TypeDef *) SMIR_BASE) - #define CFG ((CFG_TypeDef *) CFG_BASE) - #define MRCC ((MRCC_TypeDef *) MRCC_BASE) - #define ADC ((ADC_TypeDef *) ADC_BASE) - #define TB ((TB_TypeDef *) TB_BASE) - #define TIM0 ((TIM_TypeDef *) TIM0_BASE) - #define TIM1 ((TIM_TypeDef *) TIM1_BASE) - #define TIM2 ((TIM_TypeDef *) TIM2_BASE) - #define PWM ((PWM_TypeDef *) PWM_BASE) - #define WDG ((WDG_TypeDef *) WDG_BASE) - #define SSP0 ((SSP_TypeDef *) SSP0_BASE) - #define SSP1 ((SSP_TypeDef *) SSP1_BASE) - #define CAN ((CAN_TypeDef *) CAN_BASE) - #define I2C ((I2C_TypeDef *) I2C_BASE) - #define UART0 ((UART_TypeDef *) UART0_BASE) - #define UART1 ((UART_TypeDef *) UART1_BASE) - #define UART2 ((UART_TypeDef *) UART2_BASE) - #define GPIO0 ((GPIO_TypeDef *) GPIO0_BASE) - #define GPIOREMAP ((GPIOREMAP_TypeDef *) GPIOREMAP_BASE) - #define GPIO1 ((GPIO_TypeDef *) GPIO1_BASE) - #define GPIO2 ((GPIO_TypeDef *) GPIO2_BASE) - #define DMA ((DMA_TypeDef *) DMA_BASE) - #define DMA_Stream0 ((DMA_Stream_TypeDef *) DMA_Stream0_BASE) - #define DMA_Stream1 ((DMA_Stream_TypeDef *) DMA_Stream1_BASE) - #define DMA_Stream2 ((DMA_Stream_TypeDef *) DMA_Stream2_BASE) - #define DMA_Stream3 ((DMA_Stream_TypeDef *) DMA_Stream3_BASE) - #define RTC ((RTC_TypeDef *) RTC_BASE) - #define EXTIT ((EXTIT_TypeDef *) EXTIT_BASE) - #define EIC ((EIC_TypeDef *) EIC_BASE) -#else /* DEBUG */ - #ifdef _SMI - EXT SMI_TypeDef *SMI; - #endif /*_SMI */ - - #ifdef _CFG - EXT CFG_TypeDef *CFG; - #endif /*_CFG */ - - #ifdef _MRCC - EXT MRCC_TypeDef *MRCC; - #endif /*_MRCC */ - - #ifdef _ADC - EXT ADC_TypeDef *ADC; - #endif /*_ADC */ - - #ifdef _TB - EXT TB_TypeDef *TB; - #endif /*_TB */ - - #ifdef _TIM0 - EXT TIM_TypeDef *TIM0; - #endif /*_TIM0 */ - - #ifdef _TIM1 - EXT TIM_TypeDef *TIM1; - #endif /*_TIM1 */ - - #ifdef _TIM2 - EXT TIM_TypeDef *TIM2; - #endif /*_TIM2 */ - - #ifdef _PWM - EXT PWM_TypeDef *PWM; - #endif /*_PWM */ - - #ifdef _WDG - EXT WDG_TypeDef *WDG; - #endif /*_WDG */ - - #ifdef _SSP0 - EXT SSP_TypeDef *SSP0; - #endif /*_SSP0 */ - - #ifdef _SSP1 - EXT SSP_TypeDef *SSP1; - #endif /*_SSP1 */ - - #ifdef _CAN - EXT CAN_TypeDef *CAN; - #endif /*_CAN */ - - #ifdef _I2C - EXT I2C_TypeDef *I2C; - #endif /*_I2C */ - - #ifdef _UART0 - EXT UART_TypeDef *UART0; - #endif /*_UART0 */ - - #ifdef _UART1 - EXT UART_TypeDef *UART1; - #endif /*_UART1 */ - - #ifdef _UART2 - EXT UART_TypeDef *UART2; - #endif /*_UART2 */ - - #ifdef _GPIO0 - EXT GPIO_TypeDef *GPIO0; - #endif /*_GPIO0 */ - - #ifdef _GPIOREMAP - EXT GPIOREMAP_TypeDef *GPIOREMAP; - #endif /*_GPIOREMAP */ - - #ifdef _GPIO1 - EXT GPIO_TypeDef *GPIO1; - #endif /*_GPIO1 */ - - #ifdef _GPIO2 - EXT GPIO_TypeDef *GPIO2; - #endif /*_GPIO2 */ - - #ifdef _DMA - EXT DMA_TypeDef *DMA; - #endif /*_DMA */ - - #ifdef _DMA_Stream0 - EXT DMA_Stream_TypeDef *DMA_Stream0; - #endif /*_DMA_Stream0 */ - - #ifdef _DMA_Stream1 - EXT DMA_Stream_TypeDef *DMA_Stream1; - #endif /*_DMA_Stream1 */ - - #ifdef _DMA_Stream2 - EXT DMA_Stream_TypeDef *DMA_Stream2; - #endif /*_DMA_Stream2 */ - - #ifdef _DMA_Stream3 - EXT DMA_Stream_TypeDef *DMA_Stream3; - #endif /*_DMA_Stream3 */ - - #ifdef _RTC - EXT RTC_TypeDef *RTC; - #endif /*_RTC */ - - #ifdef _EXTIT - EXT EXTIT_TypeDef *EXTIT; - #endif /*_EXTIT */ - - #ifdef _EIC - EXT EIC_TypeDef *EIC; - #endif /*_EIC */ - -#endif /* DEBUG */ - -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -#endif /* __75x_MAP_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_mrcc.h b/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_mrcc.h deleted file mode 100644 index 91c178429..000000000 --- a/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_mrcc.h +++ /dev/null @@ -1,241 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_mrcc.h -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file contains all the functions prototypes for the -* MRCC software library. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __75x_MRCC_H -#define __75x_MRCC_H - -/* Includes ------------------------------------------------------------------*/ -#include "75x_map.h" - -/* Exported types ------------------------------------------------------------*/ -/* MRCC Buck-up registers */ -typedef enum -{ - MRCC_BKP0, - MRCC_BKP1 -}MRCC_BKPReg; - -typedef enum -{ - FREEOSC, - OSC4MPLL, - OSC4M, - CKRTC, - Disabled, - OSC4M_Div128, - LPOSC, - OSC32K, - Internal, - External, - ON, - OFF -}CLKSourceTypeDef; - - -typedef struct -{ - CLKSourceTypeDef CKSYS_Source; /* FREEOSC, OSC4MPLL, OSC4M, CKRTC */ - CLKSourceTypeDef CKRTC_Source; /* Disabled, OSC4M_Div128, OSC32K, LPOSC */ - CLKSourceTypeDef CKUSB_Source; /* Disabled, Internal, External */ - CLKSourceTypeDef PLL_Status; /* ON, OFF */ - CLKSourceTypeDef OSC4M_Status; /* ON, OFF */ - CLKSourceTypeDef LPOSC_Status; /* ON, OFF */ - CLKSourceTypeDef OSC32K_Status; /* ON, OFF */ - u32 CKSYS_Frequency; - u32 HCLK_Frequency; - u32 CKTIM_Frequency; - u32 PCLK_Frequency; -}MRCC_ClocksTypeDef; - -/* Exported constants --------------------------------------------------------*/ -/* Oscillator divider by 2 */ -#define MRCC_XTDIV2_Disable 0xFFFF7FFF -#define MRCC_XTDIV2_Enable 0x00008000 - -/* System clock source */ -#define MRCC_CKSYS_FREEOSC 0x01 -#define MRCC_CKSYS_OSC4M 0x02 -#define MRCC_CKSYS_OSC4MPLL 0x03 -#define MRCC_CKSYS_RTC 0x04 - -/* PLL multiplication factors */ -#define MRCC_PLL_Disabled 0xFEFFFFFF -#define MRCC_PLL_NoChange 0x00000001 -#define MRCC_PLL_Mul_12 0x18000000 -#define MRCC_PLL_Mul_14 0x10000000 -#define MRCC_PLL_Mul_15 0x08000000 -#define MRCC_PLL_Mul_16 0x00000000 - -/* AHB clock source */ -#define MRCC_CKSYS_Div1 0x00000000 -#define MRCC_CKSYS_Div2 0x00000008 -#define MRCC_CKSYS_Div4 0x00000010 -#define MRCC_CKSYS_Div8 0x00000018 - -/* TIM clock source */ -#define MRCC_HCLK_Div1 0x00000000 -#define MRCC_HCLK_Div2 0x00000001 -#define MRCC_HCLK_Div4 0x00000002 -#define MRCC_HCLK_Div8 0x00000003 - -/* APB clock source */ -#define MRCC_CKTIM_Div1 0xFFFFFFFB -#define MRCC_CKTIM_Div2 0x00000004 - -/* RTC clock sources */ -#define MRCC_CKRTC_OSC4M_Div128 0x01000000 -#define MRCC_CKRTC_OSC32K 0x02000000 -#define MRCC_CKRTC_LPOSC 0x03000000 - -/* USB clock sources */ -#define MRCC_CKUSB_Internal 0xFFBFFFFF -#define MRCC_CKUSB_External 0x00400000 - -/* MRCC Interrupts */ -#define MRCC_IT_LOCK 0x40000000 -#define MRCC_IT_NCKD 0x00080000 - -/* Peripheral Clock */ -#define MRCC_Peripheral_ALL 0x1975623F -#define MRCC_Peripheral_EXTIT 0x10000000 -#define MRCC_Peripheral_RTC 0x08000000 -#define MRCC_Peripheral_GPIO 0x01000000 -#define MRCC_Peripheral_UART2 0x00400000 -#define MRCC_Peripheral_UART1 0x00200000 -#define MRCC_Peripheral_UART0 0x00100000 -#define MRCC_Peripheral_I2C 0x00040000 -#define MRCC_Peripheral_CAN 0x00010000 -#define MRCC_Peripheral_SSP1 0x00004000 -#define MRCC_Peripheral_SSP0 0x00002000 -#define MRCC_Peripheral_USB 0x00000200 -#define MRCC_Peripheral_PWM 0x00000020 -#define MRCC_Peripheral_TIM2 0x00000010 -#define MRCC_Peripheral_TIM1 0x00000008 -#define MRCC_Peripheral_TIM0 0x00000004 -#define MRCC_Peripheral_TB 0x00000002 -#define MRCC_Peripheral_ADC 0x00000001 - -/* Clock sources to measure theire frequency */ -#define MRCC_ClockSource_CKSYS 0x01 -#define MRCC_ClockSource_HCLK 0x02 -#define MRCC_ClockSource_PCLK 0x03 -#define MRCC_ClockSource_CKTIM 0x04 - -/* Low Power Debug Mode */ -#define MRCC_LPDM_Disable 0xFFFFFFF7 -#define MRCC_LPDM_Enable 0x00000008 - -/* WFI Mode parameters */ -#define MRCC_WFIParam_FLASHPowerDown 0x00000000 -#define MRCC_WFIParam_FLASHOn 0x00000010 -#define MRCC_WFIParam_FLASHOff 0x00004000 - -/* STOP Mode parameters */ -#define MRCC_STOPParam_Default 0x00000000 -#define MRCC_STOPParam_OSC4MOff 0x00008000 -#define MRCC_STOPParam_FLASHOff 0x00004000 -#define MRCC_STOPParam_MVREGOff 0x00002000 - -/* I/O Pins voltage range */ -#define MRCC_IOVoltageRange_5V 0xFFFEFFFF -#define MRCC_IOVoltageRange_3V3 0x00010000 - -/* Clock sources to output on MCO pin */ -#define MRCC_MCO_HCLK 0x00000000 -#define MRCC_MCO_PCLK 0x00000040 -#define MRCC_MCO_OSC4M 0x00000080 -#define MRCC_MCO_CKPLL2 0x000000C0 -#define MRCC_MCOPrescaler_1 0xFFFFFFDF -#define MRCC_MCOPrescaler_2 0x00000020 - -/* 4MHz main oscillator configuration */ -#define MRCC_OSC4M_Default 0xFFFCFFFF -#define MRCC_OSC4M_Disable 0x00020000 -#define MRCC_OSC4M_Bypass 0x00010000 - -/* OSC32K oscillator configuration */ -#define MRCC_OSC32K_Disable 0xDFFFFFFF -#define MRCC_OSC32K_Enable 0x20000000 -#define MRCC_OSC32KBypass_Disable 0xBFFFFFFF -#define MRCC_OSC32KBypass_Enable 0x40000000 - -/* LPOSC oscillator configuration */ -#define MRCC_LPOSC_Disable 0xEFFFFFFF -#define MRCC_LPOSC_Enable 0x10000000 - -/* RTC measurement configuration */ -#define MRCC_RTCM_Disable 0xFBFFFFFF -#define MRCC_RTCM_Enable 0x04000000 - -/* MRCC Flags */ -#define MRCC_FLAG_LOCK 0x3F -#define MRCC_FLAG_LOCKIF 0x3D -#define MRCC_FLAG_CKSEL 0x37 -#define MRCC_FLAG_CKOSCSEL 0x35 -#define MRCC_FLAG_NCKD 0x32 -#define MRCC_FLAG_SWR 0x5D -#define MRCC_FLAG_WDGR 0x5C -#define MRCC_FLAG_EXTR 0x5B -#define MRCC_FLAG_WKP 0x5A -#define MRCC_FLAG_STDB 0x59 -#define MRCC_FLAG_BCOUNT 0x58 -#define MRCC_FLAG_OSC32KRDY 0x7F -#define MRCC_FLAG_CKRTCOK 0x7B -#define MRCC_FLAG_LPDONE 0x67 -#define MRCC_FLAG_LP 0x60 - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -void MRCC_DeInit(void); -void MRCC_XTDIV2Config(u32 MRCC_XTDIV2); -ErrorStatus MRCC_CKSYSConfig(u32 MRCC_CKSYS, u32 MRCC_PLL); -void MRCC_HCLKConfig(u32 MRCC_HCLK); -void MRCC_CKTIMConfig(u32 MRCC_CKTIM); -void MRCC_PCLKConfig(u32 MRCC_PCLK); -ErrorStatus MRCC_CKRTCConfig(u32 MRCC_CKRTC); -ErrorStatus MRCC_CKUSBConfig(u32 MRCC_CKUSB); -void MRCC_ITConfig(u32 MRCC_IT, FunctionalState NewState); -void MRCC_PeripheralClockConfig(u32 MRCC_Peripheral, FunctionalState NewState); -void MRCC_PeripheralSWResetConfig(u32 MRCC_Peripheral, FunctionalState NewState); -void MRCC_GetClocksStatus(MRCC_ClocksTypeDef* MRCC_ClocksStatus); -void MRCC_LPMC_DBGConfig(u32 MRCC_LPDM); -void MRCC_EnterWFIMode(u32 MRCC_WFIParam); -void MRCC_EnterSTOPMode(u32 MRCC_STOPParam); -void MRCC_EnterSTANDBYMode(void); -void MRCC_GenerateSWReset(void); -void MRCC_WriteBackupRegister(MRCC_BKPReg MRCC_BKP, u32 Data); -u32 MRCC_ReadBackupRegister(MRCC_BKPReg MRCC_BKP); -void MRCC_IOVoltageRangeConfig(u32 MRCC_IOVoltageRange); -void MRCC_MCOConfig(u32 MRCC_MCO, u32 MCO_MCOPrescaler); -ErrorStatus MRCC_OSC4MConfig(u32 MRCC_OSC4M); -ErrorStatus MRCC_OSC32KConfig(u32 MRCC_OSC32K, u32 MRCC_OSC32KBypass); -ErrorStatus MRCC_LPOSCConfig(u32 MRCC_LPOSC); -void MRCC_RTCMConfig(u32 MRCC_RTCM); -void MRCC_SetBuilderCounter(u8 BuilderCounter); -u16 MRCC_GetCKSYSCounter(void); -FlagStatus MRCC_GetFlagStatus(u8 MRCC_FLAG); -void MRCC_ClearFlag(u8 MRCC_FLAG); -ITStatus MRCC_GetITStatus(u32 MRCC_IT); -void MRCC_ClearITPendingBit(u32 MRCC_IT); -ErrorStatus MRCC_WaitForOSC4MStartUp(void); - -#endif /* __75x_MRCC_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_pwm.h b/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_pwm.h deleted file mode 100644 index 28edba9e8..000000000 --- a/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_pwm.h +++ /dev/null @@ -1,215 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_pwm.h -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file contains all the functions prototypes for the -* PWM software library. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __75x_PWM_H -#define __75x_PWM_H - -/* Includes ------------------------------------------------------------------*/ -#include "75x_map.h" - -/* Exported types ------------------------------------------------------------*/ - -typedef struct -{ - u16 PWM_Mode; /* PWM Mode */ - u16 PWM_Prescaler; /* Prescaler value */ - u16 PWM_CounterMode; /* Counter mode: Up/Down, Edge aligned or center aligned */ - u16 PWM_Period; /* Period value */ - u16 PWM_Complementary; /* Complementary PWM selection */ - u16 PWM_OCState; /* Output compare off-state in Run mode */ - u16 PWM_OCNState; /* Complementary Output compare off-state in Run mode */ - u16 PWM_Channel; /* PWM Channel: 1, 2 or 3 */ - u16 PWM_Pulse1; /* PWM or OCM Channel 1 pulse length */ - u16 PWM_Pulse2; /* PWM or OCM Channel 2 pulse length */ - u16 PWM_Pulse3; /* PWM or OCM Channel 3 pulse length */ - u16 PWM_Polarity1; /* PWM, OCM or OPM Channel 1 polarity */ - u16 PWM_Polarity2; /* PWM or OCM Channel 2 polarity */ - u16 PWM_Polarity3; /* PWM or OCM Channel 3 polarity */ - u16 PWM_Polarity1N; /* PWM or OCM Channel 1N polarity */ - u16 PWM_Polarity2N; /* PWM or OCM Channel 2N polarity */ - u16 PWM_Polarity3N; /* PWM or OCM Channel 3N polarity */ - u16 PWM_DTRAccess; /* Enable or disable the configuration of DTR register parameters: - DeadTime, Emergency, LOCKLevel, OSSIState, OCState and OCNState */ - u16 PWM_DeadTime; /* Dead Time value */ - u16 PWM_Emergency; /* Emergency selection: Enable / Disable */ - u16 PWM_LOCKLevel; /* LOCK level */ - u16 PWM_OSSIState; /* Off-State Selection for Idle state */ - u8 PWM_RepetitionCounter; /* Repetition counter value */ -} PWM_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ -/* PWM modes */ -#define PWM_Mode_OCTiming 0x0001 -#define PWM_Mode_OCActive 0x0002 -#define PWM_Mode_OCInactive 0x0003 -#define PWM_Mode_OCToggle 0x0004 -#define PWM_Mode_PWM 0x0005 - -/* PWM Counter Mode */ -#define PWM_CounterMode_Up 0x0000 -#define PWM_CounterMode_Down 0x0010 -#define PWM_CounterMode_CenterAligned1 0x0020 -#define PWM_CounterMode_CenterAligned2 0x0040 -#define PWM_CounterMode_CenterAligned3 0x0060 - -/* PWM Channel */ -#define PWM_Channel_1 0x0001 -#define PWM_Channel_2 0x0002 -#define PWM_Channel_3 0x0004 -#define PWM_Channel_ALL 0x0007 - -/* PWM Polarity channel 1 */ -#define PWM_Polarity1_High 0x0001 -#define PWM_Polarity1_Low 0x0002 - -/* PWM Polarity channel 2 */ -#define PWM_Polarity2_High 0x0001 -#define PWM_Polarity2_Low 0x0002 - -/* PWM Polarity channel 3 */ -#define PWM_Polarity3_High 0x0001 -#define PWM_Polarity3_Low 0x0002 - -/* PWM Polarity channel 1N */ -#define PWM_Polarity1N_High 0x0001 -#define PWM_Polarity1N_Low 0x0002 - -/* PWM Polarity channel 2N */ -#define PWM_Polarity2N_High 0x0001 -#define PWM_Polarity2N_Low 0x0002 - -/* PWM Polarity channel 3N */ -#define PWM_Polarity3N_High 0x0001 -#define PWM_Polarity3N_Low 0x0002 - -/* PWM interrupt sources */ -#define PWM_IT_OC1 0x0100 -#define PWM_IT_OC2 0x0200 -#define PWM_IT_OC3 0x0400 -#define PWM_IT_Update 0x0001 -#define PWM_IT_GlobalUpdate 0x1001 -#define PWM_IT_Emergency 0x8000 - -/* PWM DMA sources */ -#define PWM_DMASource_OC1 0x0100 -#define PWM_DMASource_OC2 0x0200 -#define PWM_DMASource_OC3 0x0400 -#define PWM_DMASource_Update 0x0001 - -/* PWM DMA Base address */ -#define PWM_DMABase_CR 0x0000 -#define PWM_DMABase_SCR 0x0800 -#define PWM_DMABase_OMR1 0x1800 -#define PWM_DMABase_OMR2 0x2000 -#define PWM_DMABase_RSR 0x3000 -#define PWM_DMABase_RER 0x3800 -#define PWM_DMABase_ISR 0x4000 -#define PWM_DMABase_CNT 0x4800 -#define PWM_DMABase_PSC 0x5000 -#define PWM_DMABase_RCR 0x5800 -#define PWM_DMABase_ARR 0x6000 -#define PWM_DMABase_OCR1 0x6800 -#define PWM_DMABase_OCR2 0x7000 -#define PWM_DMABase_OCR3 0x7800 -#define PWM_DMABase_DTR 0xB800 - -/* PWM OCM state */ -#define PWM_OCRMState_Enable 0x0005 -#define PWM_OCRMState_Disable 0x0006 - -/* PWM Flags */ -#define PWM_FLAG_OC1 0x0100 -#define PWM_FLAG_OC2 0x0200 -#define PWM_FLAG_OC3 0x0400 -#define PWM_FLAG_Update 0x0001 -#define PWM_FLAG_Emergency 0x8000 - -/* PWM_ForcedAction */ -#define PWM_ForcedAction_Active 0x000A -#define PWM_ForcedAction_InActive 0x0008 - -/* PWM TRGO Mode */ -#define PWM_TRGOMode_Enable 0x0100 -#define PWM_TRGOMode_Update 0x0200 -#define PWM_TRGOMode_Reset 0x0000 -#define PWM_TRGOMode_OC 0x0300 - -/* PWM Complementary outputs Enable/Disable */ -#define PWM_Complementary_Disable 0x0001 -#define PWM_Complementary_Enable 0x0002 - -/* PWM DTR Access Enable/Disable */ -#define PWM_DTRAccess_Enable 0x0001 -#define PWM_DTRAccess_Disable 0x0002 - -/* PWM Emergency input Enable/Disable */ -#define PWM_Emergency_Disable 0x0000 -#define PWM_Emergency_Enable 0x1000 - -/* OC states */ -#define PWM_OCNState_Disable 0x0001 -#define PWM_OCNState_Enable 0x0002 -#define PWM_OCNState_OffState 0x0003 - -/* OCN states */ -#define PWM_OCState_Disable 0x0004 -#define PWM_OCState_Enable 0x0005 -#define PWM_OCState_OffState 0x0006 - -/* PWM LOCK level */ -#define PWM_LOCKLevel_1 0x0400 -#define PWM_LOCKLevel_2 0x0800 -#define PWM_LOCKLevel_3 0x0C00 -#define PWM_LOCKLevel_OFF 0x0000 - -/* Off State selection for Idle state */ -#define PWM_OSSIState_Disable 0x0000 -#define PWM_OSSIState_Enable 0x2000 - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -void PWM_DeInit(void); -void PWM_Init(PWM_InitTypeDef* PWM_InitStruct); -void PWM_StructInit(PWM_InitTypeDef *PWM_InitStruct); -void PWM_Cmd(FunctionalState Newstate); -void PWM_CtrlPWMOutputs(FunctionalState Newstate); -void PWM_ITConfig(u16 PWM_IT, FunctionalState Newstate); -void PWM_DMAConfig(u16 PWM_DMASources, u16 PWM_OCRMState, u16 PWM_DMABase); -void PWM_DMACmd(u16 PWM_DMASources, FunctionalState Newstate); -void PWM_SetPrescaler(u16 Prescaler); -void PWM_SetPeriod(u16 Period); -void PWM_SetPulse(u16 PWM_Channel, u16 Pulse); -void PWM_SetPulse1(u16 Pulse); -void PWM_SetPulse2(u16 Pulse); -void PWM_SetPulse3(u16 Pulse); -void PWM_DebugCmd(FunctionalState Newstate); -void PWM_CounterModeConfig(u16 PWM_CounterMode); -void PWM_ForcedOCConfig(u16 PWM_Channel, u16 PWM_ForcedAction); -void PWM_SetDeadTime(u16 DeadTime); -void PWM_ResetCounter(void); -void PWM_TRGOSelection(u16 PWM_TRGOMode); -FlagStatus PWM_GetFlagStatus(u16 PWM_FLAG); -void PWM_ClearFlag(u16 PWM_FLAG); -ITStatus PWM_GetITStatus(u16 PWM_IT); -void PWM_ClearITPendingBit(u16 PWM_IT); - -#endif /* __75x_PWM_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_rtc.h b/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_rtc.h deleted file mode 100644 index a54dee958..000000000 --- a/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_rtc.h +++ /dev/null @@ -1,63 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_rtc.h -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file contains all the functions prototypes for the -* RTC software library. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __75x_RTC_H -#define __75x_RTC_H - -/* Includes ------------------------------------------------------------------*/ -#include "75x_map.h" - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* RTC interrupts define */ -#define RTC_IT_Overflow 0x0004 /* Overflow interrupt */ -#define RTC_IT_Alarm 0x0002 /* Alarm interrupt */ -#define RTC_IT_Second 0x0001 /* Second interrupt */ - -/* RTC interrupts flags */ -#define RTC_FLAG_RTOFF 0x0020 /* RTC Operation OFF flag */ -#define RTC_FLAG_RSF 0x0008 /* Registers Synchronized flag */ -#define RTC_FLAG_Overflow 0x0004 /* Overflow interrupt flag */ -#define RTC_FLAG_Alarm 0x0002 /* Alarm interrupt flag */ -#define RTC_FLAG_Second 0x0001 /* Second interrupt flag */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -void RTC_DeInit(void); -void RTC_ITConfig(u16 RTC_IT, FunctionalState NewState); -void RTC_EnterConfigMode(void); -void RTC_ExitConfigMode(void); -u32 RTC_GetCounter(void); -void RTC_SetCounter(u32 CounterValue); -void RTC_SetPrescaler(u32 PrescalerValue); -u32 RTC_GetPrescaler(void); -void RTC_SetAlarm(u32 AlarmValue); -u32 RTC_GetDivider(void); -void RTC_WaitForLastTask(void); -void RTC_WaitForSynchro(void); -FlagStatus RTC_GetFlagStatus(u16 RTC_FLAG); -void RTC_ClearFlag(u16 RTC_FLAG); -ITStatus RTC_GetITStatus(u16 RTC_IT); -void RTC_ClearITPendingBit(u16 RTC_IT); - -#endif /* __75x_RTC_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_smi.h b/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_smi.h deleted file mode 100644 index 1e4a71bd2..000000000 --- a/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_smi.h +++ /dev/null @@ -1,111 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_smi.h -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file contains all the functions prototypes for the -* SMI software library. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __75x_SMI_H -#define __75x_SMI_H - -/* Includes ------------------------------------------------------------------*/ -#include "75x_map.h" - -/* Exported types ------------------------------------------------------------*/ -typedef struct -{ - u8 SMI_ClockHold; - u8 SMI_Prescaler; - u8 SMI_DeselectTime; -} SMI_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ -/* SMI mode */ -#define SMI_Mode_HW 0xEFFFFFFF -#define SMI_Mode_SW 0x10000000 - -/* Reception Length */ -#define SMI_RxLength_0Bytes 0x00000000 -#define SMI_RxLength_1Byte 0x00000010 -#define SMI_RxLength_2Bytes 0x00000020 -#define SMI_RxLength_3Bytes 0x00000030 -#define SMI_RxLength_4Bytes 0x00000040 - -/* Transmission Length */ -#define SMI_TxLength_0Bytes 0x00000000 -#define SMI_TxLength_1Byte 0x00000001 -#define SMI_TxLength_2Bytes 0x00000002 -#define SMI_TxLength_3Bytes 0x00000003 -#define SMI_TxLength_4Bytes 0x00000004 - -/* SMI memory Banks */ -#define SMI_Bank_0 0x00000001 -#define SMI_Bank_1 0x00000002 -#define SMI_Bank_2 0x00000004 -#define SMI_Bank_3 0x00000008 - -/* SMI Interrupts */ -#define SMI_IT_WC 0x00000200 -#define SMI_IT_TF 0x00000100 - -/* Fast Read Mode */ -#define SMI_FastRead_Disable 0xFFFF7FFF -#define SMI_FastRead_Enable 0x00008000 - -/* Write Burst Mode */ -#define SMI_WriteBurst_Disable 0xDFFFFFFF -#define SMI_WriteBurst_Enable 0x20000000 - -/* SMI Flags */ -#define SMI_FLAG_Bank3_WM 0x00008000 -#define SMI_FLAG_Bank2_WM 0x00004000 -#define SMI_FLAG_Bank1_WM 0x00002000 -#define SMI_FLAG_Bank0_WM 0x00001000 -#define SMI_FLAG_ERF2 0x00000800 -#define SMI_FLAG_ERF1 0x00000400 -#define SMI_FLAG_WC 0x00000200 -#define SMI_FLAG_TF 0x00000100 - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -void SMI_DeInit(void); -void SMI_Init(SMI_InitTypeDef* SMI_InitStruct); -void SMI_StructInit(SMI_InitTypeDef* SMI_InitStruct); -void SMI_ModeConfig(u32 SMI_Mode); -void SMI_TxRxLengthConfig(u32 SMI_TxLength, u32 SMI_RxLength); -void SMI_BankCmd(u32 SMI_Bank, FunctionalState NewState); -void SMI_ITConfig(u32 SMI_IT, FunctionalState NewState); -void SMI_SelectBank(u32 SMI_Bank); -void SMI_SendWENCmd(void); -void SMI_SendRSRCmd(void); -void SMI_SendCmd(u32 Command); -void SMI_FastReadConfig(u32 SMI_FastRead); -void SMI_WriteBurstConfig(u32 SMI_WriteBurst); -void SMI_WriteByte(u32 WriteAddr, u8 Data); -void SMI_WriteHalfWord(u32 WriteAddr, u16 Data); -void SMI_WriteWord(u32 WriteAddr, u32 Data); -u8 SMI_ReadByte(u32 ReadAddr); -u16 SMI_ReadHalfWord(u32 ReadAddr); -u32 SMI_ReadWord(u32 ReadAddr); -u8 SMI_ReadMemoryStatusRegister(void); -FlagStatus SMI_GetFlagStatus(u32 SMI_FLAG); -void SMI_ClearFlag(u32 SMI_FLAG); -ITStatus SMI_GetITStatus(u32 SMI_IT); -void SMI_ClearITPendingBit(u32 SMI_IT); - -#endif /* __75x_SMI_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_ssp.h b/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_ssp.h deleted file mode 100644 index 96dec886a..000000000 --- a/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_ssp.h +++ /dev/null @@ -1,135 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_SSP.h -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file contains all the functions prototypes for the -* SSP software library. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __75x_SSP_H -#define __75x_SSP_H - -/* Includes ------------------------------------------------------------------*/ -#include "75x_map.h" - -/* Exported types ------------------------------------------------------------*/ -/* SSP Init structure definition */ -typedef struct -{ - u16 SSP_FrameFormat; - u16 SSP_Mode; - u16 SSP_CPOL; - u16 SSP_CPHA; - u16 SSP_DataSize; - u16 SSP_NSS; - u16 SSP_SlaveOutput; - u8 SSP_ClockRate; - u8 SSP_ClockPrescaler; -}SSP_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ -/* SSP Frame Format Select */ -#define SSP_FrameFormat_TI 0x0010 -#define SSP_FrameFormat_Motorola 0xFFCF - -/* SSP Master/Slave Select */ -#define SSP_Mode_Master 0xFFFB -#define SSP_Mode_Slave 0x0004 - -/* SSP Clock Polarity */ -#define SSP_CPOL_Low 0xFFBF -#define SSP_CPOL_High 0x0040 - -/* SSP Clock Phase */ -#define SSP_CPHA_1Edge 0xFF7F -#define SSP_CPHA_2Edge 0x0080 - -/* SSP Data Size */ -#define SSP_DataSize_16b 0x000F -#define SSP_DataSize_15b 0x000E -#define SSP_DataSize_14b 0x000D -#define SSP_DataSize_13b 0x000C -#define SSP_DataSize_12b 0x000B -#define SSP_DataSize_11b 0x000A -#define SSP_DataSize_10b 0x0009 -#define SSP_DataSize_9b 0x0008 -#define SSP_DataSize_8b 0x0007 -#define SSP_DataSize_7b 0x0006 -#define SSP_DataSize_6b 0x0005 -#define SSP_DataSize_5b 0x0004 -#define SSP_DataSize_4b 0x0003 - -/* SSP Slave Select management config */ -#define SSP_NSS_Hard 0xFFEF -#define SSP_NSS_Soft 0x0010 - -/* SSP NSS internal config */ -#define SSP_NSSInternal_Set 0x0020 -#define SSP_NSSInternal_Reset 0xFFDF - -/* SSP Slave output config */ -#define SSP_SlaveOutput_Enable 0xFFF7 -#define SSP_SlaveOutput_Disable 0x0008 - -/* SSP Interrupts */ -#define SSP_IT_TxFifo 0x0008 -#define SSP_IT_RxFifo 0x0004 -#define SSP_IT_RxTimeOut 0x0002 -#define SSP_IT_RxOverrun 0x0001 - -/* SSP Flags */ -#define SSP_FLAG_Busy 0x0024 -#define SSP_FLAG_RxFifoFull 0x0023 -#define SSP_FLAG_RxFifoNotEmpty 0x0022 -#define SSP_FLAG_TxFifoNotFull 0x0021 -#define SSP_FLAG_TxFifoEmpty 0x0020 -#define SSP_FLAG_TxFifo 0x0043 -#define SSP_FLAG_RxFifo 0x0042 -#define SSP_FLAG_RxTimeOut 0x0041 -#define SSP_FLAG_RxOverrun 0x0040 - -/* SSP DMA Requests */ -#define SSP0_DMA_Transmit 0x0002 -#define SSP0_DMA_Receive 0x0001 - -#define SSP0_DMATxReq_Single 0xFFF7 -#define SSP0_DMATxReq_Burst 0x0008 - -#define SSP0_DMARxReq_Single 0xFFFB -#define SSP0_DMARxReq_Burst 0x0004 - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -void SSP_DeInit(SSP_TypeDef* SSPx); -void SSP_Init(SSP_TypeDef* SSPx, SSP_InitTypeDef* SSP_InitStruct); -void SSP_StructInit(SSP_InitTypeDef* SSP_InitStruct); -void SSP_Cmd(SSP_TypeDef* SSPx, FunctionalState NewState); -void SSP_ITConfig(SSP_TypeDef* SSPx, u16 SSP_IT, FunctionalState NewState); -void SSP_DMACmd(u16 SSP0_DMAtransfer, FunctionalState NewState); -void SSP_DMATxConfig(u16 SSP0_DMATxReq); -void SSP_DMARxConfig(u16 SSP0_DMARxReq); -void SSP_SendData(SSP_TypeDef* SSPx, u16 Data); -u16 SSP_ReceiveData(SSP_TypeDef* SSPx); -void SSP_LoopBackConfig(SSP_TypeDef* SSPx, FunctionalState NewState); -void SSP_NSSInternalConfig(SSP_TypeDef* SSPx, u16 SSP_NSSState); -FlagStatus SSP_GetFlagStatus(SSP_TypeDef* SSPx, u16 SSP_FLAG); -void SSP_ClearFlag(SSP_TypeDef* SSPx, u16 SSP_FLAG); -ITStatus SSP_GetITStatus(SSP_TypeDef* SSPx, u16 SSP_IT); -void SSP_ClearITPendingBit(SSP_TypeDef* SSPx, u16 SSP_IT); - -#endif /* __75x_SSP_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_tb.h b/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_tb.h deleted file mode 100644 index e5054935d..000000000 --- a/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_tb.h +++ /dev/null @@ -1,93 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_tb.h -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file contains all the functions prototypes for the -* TB software library. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __75x_TB_H -#define __75x_TB_H - -/* Includes ------------------------------------------------------------------*/ -#include "75x_map.h" - -/* Exported types ------------------------------------------------------------*/ -typedef struct -{ - u16 TB_Mode; /* TB mode */ - u16 TB_ClockSource; /* TB clock source: CK_TIM or CK_RTC */ - u16 TB_CounterMode; /* TB counter mode */ - u16 TB_ICAPolarity; /* TB Input Capture signal Polarity */ - u16 TB_Prescaler; /* TB Prescaler factor */ - u16 TB_AutoReload; /* TB AutoReload factor */ -} TB_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ -/* TB modes */ -#define TB_Mode_IC 0x0002 -#define TB_Mode_Timing 0x0001 - -/* TB clock source */ -#define TB_ClockSource_CKTIM 0x0001 -#define TB_ClockSource_CKRTC 0x0002 - -/* TB Input capture polarity */ -#define TB_ICAPolarity_Rising 0x7000 -#define TB_ICAPolarity_Falling 0x8000 - -/* TB counter modes */ -#define TB_CounterMode_Up 0x0000 -#define TB_CounterMode_Down 0x0010 -#define TB_CounterMode_CenterAligned 0x0060 - -/* TB interrupt sources */ -#define TB_IT_Update 0x0001 -#define TB_IT_IC 0x0004 -#define TB_IT_GlobalUpdate 0x8001 - -/* TB Flags */ -#define TB_FLAG_IC 0x0004 -#define TB_FLAG_Update 0x0001 - -/* TB Slave Mode Selection */ -#define TB_SMSMode_Trigger 0x0018 -#define TB_SMSMode_Gated 0x0010 -#define TB_SMSMode_External 0x0008 -#define TB_SMSMode_Reset 0x0000 - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -void TB_DeInit(void); -void TB_Init(TB_InitTypeDef* TB_InitStruct); -void TB_StructInit(TB_InitTypeDef *TB_InitStruct); -void TB_Cmd(FunctionalState Newstate ); -void TB_ITConfig(u16 TB_IT, FunctionalState Newstate); -void TB_SetPrescaler(u16 Prescaler); -void TB_ResetCounter(void); -void TB_DebugCmd(FunctionalState Newstate); -void TB_CounterModeConfig(u16 TB_CounterMode); -void TB_SLaveModeConfig(u16 TB_SMSMode); -u16 TB_GetCounter(void); -u16 TB_GetICAP1(void); -void TB_SetCounter(u16 Counter); -FlagStatus TB_GetFlagStatus(u16 TB_FLAG); -void TB_ClearFlag(u16 TB_FLAG); -ITStatus TB_GetITStatus(u16 TB_IT); -void TB_ClearITPendingBit(u16 TB_IT); - -#endif /* __75x_TB_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_tim.h b/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_tim.h deleted file mode 100644 index 02b51321b..000000000 --- a/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_tim.h +++ /dev/null @@ -1,232 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_tim.h -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file contains all the functions prototypes for the -* TIM software library. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __75x_TIM_H -#define __75x_TIM_H - -/* Includes ------------------------------------------------------------------*/ -#include "75x_map.h" - -/* Exported types ------------------------------------------------------------*/ -typedef struct -{ - u16 TIM_Mode; /* Timer Mode */ - u16 TIM_Prescaler; /* Prescaler value */ - u16 TIM_ClockSource; /* Timer clock source */ - u16 TIM_ExtCLKEdge; /* External clock edge */ - u16 TIM_CounterMode; /* Counter mode: Up/Down, Edge aligned or center aligned */ - u16 TIM_Period; /* Period value */ - u16 TIM_Channel; /* Timer Channel: 1, 2 or All */ - u16 TIM_Pulse1; /* PWM or OCM Channel 1 pulse length */ - u16 TIM_Pulse2; /* PWM or OCM Channel 2 pulse length */ - u16 TIM_RepetitivePulse; /* OPM Repetitive pulse state: enable or disable */ - u16 TIM_Polarity1; /* PWM, OCM or OPM Channel 1 polarity */ - u16 TIM_Polarity2; /* PWM or OCM Channel 2 polarity */ - u16 TIM_IC1Selection; /* Input Capture 1 selection: TI1 or TI2 */ - u16 TIM_IC2Selection; /* Input Capture 2 selection: TI1 or TI2 */ - u16 TIM_IC1Polarity; /* Input Capture 1 polarity */ - u16 TIM_IC2Polarity; /* Input Capture 2 polarity */ - u16 TIM_PWMI_ICSelection; /* PWM Input Capture selection: TI1 or TI2 */ - u16 TIM_PWMI_ICPolarity; /* PWM Input Capture Polarity */ -} TIM_InitTypeDef; - -/* Master and slave synchronized Timer peripherals */ -typedef enum -{ - PWM_Master = 0x01, - TIM0_Master, - TIM1_Master, - TIM2_Master -}Master_TypeDef; - -typedef enum -{ - PWM_Slave = 0x05, - TIM0_Slave, - TIM1_Slave, - TIM2_Slave -}Slave_TypeDef; - -/* Exported constants --------------------------------------------------------*/ -/* TIM modes */ -#define TIM_Mode_OCTiming 0x0001 -#define TIM_Mode_OCActive 0x0002 -#define TIM_Mode_OCInactive 0x0003 -#define TIM_Mode_OCToggle 0x0004 -#define TIM_Mode_PWM 0x0005 -#define TIM_Mode_PWMI 0x0006 -#define TIM_Mode_IC 0x0007 -#define TIM_Mode_Encoder1 0x0008 -#define TIM_Mode_Encoder2 0x0009 -#define TIM_Mode_Encoder3 0x000A -#define TIM_Mode_OPM_PWM 0x000B -#define TIM_Mode_OPM_Toggle 0x000C -#define TIM_Mode_OPM_Active 0x000D - -/* TIM Clock Source */ -#define TIM_ClockSource_Internal 0x0001 -#define TIM_ClockSource_TI11 0x0002 -#define TIM_ClockSource_TI12 0x0003 -#define TIM_ClockSource_TI22 0x0004 -#define TIM_ClockSource_TI21 0x0005 - -/* TIM External Clock Edge */ -#define TIM_ExtCLKEdge_Falling 0x0001 -#define TIM_ExtCLKEdge_Rising 0x0002 - -/* TIM Counter Mode */ -#define TIM_CounterMode_Up 0x0000 -#define TIM_CounterMode_Down 0x0010 -#define TIM_CounterMode_CenterAligned1 0x0020 -#define TIM_CounterMode_CenterAligned2 0x0040 -#define TIM_CounterMode_CenterAligned3 0x0060 - -/* TIM Channel */ -#define TIM_Channel_1 0x0001 -#define TIM_Channel_2 0x0002 -#define TIM_Channel_ALL 0x0003 - -/* TIM Polarity channel 1 */ -#define TIM_Polarity1_High 0x0001 -#define TIM_Polarity1_Low 0x0002 - -/* TIM Polarity channel 2 */ -#define TIM_Polarity2_High 0x0001 -#define TIM_Polarity2_Low 0x0002 - -#define TIM_RepetitivePulse_Disable 0x0005 -#define TIM_RepetitivePulse_Enable 0x0006 - -/* TIM Input Capture channel 1 Selection */ -#define TIM_IC1Selection_TI1 0x0001 -#define TIM_IC1Selection_TI2 0x0002 - -/* TIM Input Capture channel 2 Selection */ -#define TIM_IC2Selection_TI1 0x0001 -#define TIM_IC2Selection_TI2 0x0002 - -/* TIM Input Capture channel 1 Polarity */ -#define TIM_IC1Polarity_Falling 0x0001 -#define TIM_IC1Polarity_Rising 0x0002 - -/* TIM Input Capture channel 2 Polarity */ -#define TIM_IC2Polarity_Falling 0x0001 -#define TIM_IC2Polarity_Rising 0x0002 - -/* TIM PWM Input IC Selection */ -#define TIM_PWMI_ICSelection_TI1 0x0001 -#define TIM_PWMI_ICSelection_TI2 0x0002 - -/* TIM PWM Input IC Polarity */ -#define TIM_PWMI_ICPolarity_Falling 0x0003 -#define TIM_PWMI_ICPolarity_Rising 0x0004 - -/* TIM interrupt sources */ -#define TIM_IT_IC1 0x0004 -#define TIM_IT_IC2 0x0008 -#define TIM_IT_OC1 0x0100 -#define TIM_IT_OC2 0x0200 -#define TIM_IT_Update 0x0001 -#define TIM_IT_GlobalUpdate 0x1001 - -/* TIM DMA sources */ -#define TIM_DMASource_IC1 0x0004 -#define TIM_DMASource_IC2 0x0008 -#define TIM_DMASource_OC1 0x0100 -#define TIM_DMASource_OC2 0x0200 -#define TIM_DMASource_Update 0x0001 - -/* TIM DMA Base address */ -#define TIM_DMABase_CR 0x0000 -#define TIM_DMABase_SCR 0x0800 -#define TIM_DMABase_IMCR 0x1000 -#define TIM_DMABase_OMR1 0x1800 -#define TIM_DMABase_RSR 0x3000 -#define TIM_DMABase_RER 0x3800 -#define TIM_DMABase_ISR 0x4000 -#define TIM_DMABase_CNT 0x4800 -#define TIM_DMABase_PSC 0x5000 -#define TIM_DMABase_ARR 0x6000 -#define TIM_DMABase_OCR1 0x6800 -#define TIM_DMABase_OCR2 0x7000 -#define TIM_DMABase_ICR1 0x9800 -#define TIM_DMABase_ICR2 0xA000 - -/* TIM Flags */ -#define TIM_FLAG_IC1 0x0004 -#define TIM_FLAG_IC2 0x0008 -#define TIM_FLAG_OC1 0x0100 -#define TIM_FLAG_OC2 0x0200 -#define TIM_FLAG_Update 0x0001 - -/* TIM_ForcedAction */ -#define TIM_ForcedAction_Active 0x000A -#define TIM_ForcedAction_InActive 0x0008 - -/* TIM synchronization action */ -#define TIM_SynchroAction_Enable 0x0100 -#define TIM_SynchroAction_Update 0x0200 -#define TIM_SynchroAction_Reset 0x0000 -#define TIM_SynchroAction_OC 0x0300 - -/* TIM synchronization mode */ -#define TIM_SynchroMode_Gated 0x0010 -#define TIM_SynchroMode_Trigger 0x0018 -#define TIM_SynchroMode_External 0x0008 -#define TIM_SynchroMode_Reset 0x0000 - -/* OCRM bit states */ -#define TIM_OCRMState_Enable 0x0005 -#define TIM_OCRMState_Disable 0x0006 - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -void TIM_DeInit(TIM_TypeDef *TIMx); -void TIM_Init(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct); -void TIM_StructInit(TIM_InitTypeDef *TIM_InitStruct); -void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState Newstate); -void TIM_ITConfig(TIM_TypeDef *TIMx, u16 TIM_IT, FunctionalState Newstate); -void TIM_PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_Channel, FunctionalState Newstate); -void TIM_DMAConfig(u16 TIM_DMASources, u16 TIM_OCRMState, u16 TIM_DMABase); -void TIM_DMACmd(u16 TIM_DMASources, FunctionalState Newstate); -void TIM_ClockSourceConfig(TIM_TypeDef *TIMx, u16 TIM_ClockSource, - u16 TIM_ExtCLKEdge); -void TIM_SetPrescaler(TIM_TypeDef* TIMx, u16 Prescaler); -void TIM_SetPeriod(TIM_TypeDef* TIMx, u16 Period); -void TIM_SetPulse(TIM_TypeDef* TIMx, u16 TIM_Channel, u16 Pulse); -u16 TIM_GetICAP1(TIM_TypeDef *TIMx); -u16 TIM_GetICAP2(TIM_TypeDef *TIMx); -u16 TIM_GetPWMIPulse(TIM_TypeDef *TIMx); -u16 TIM_GetPWMIPeriod(TIM_TypeDef *TIMx); -void TIM_DebugCmd(TIM_TypeDef *TIMx, FunctionalState Newstate); -void TIM_CounterModeConfig(TIM_TypeDef* TIMx, u16 TIM_CounterMode); -void TIM_ForcedOCConfig(TIM_TypeDef* TIMx, u16 TIM_Channel, - u16 TIM_ForcedAction); -void TIM_ResetCounter(TIM_TypeDef* TIMx); -void TIM_SynchroConfig(Master_TypeDef Master, Slave_TypeDef Slave, - u16 TIM_SynchroAction, u16 TIM_SynchroMode); -FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, u16 TIM_FLAG); -void TIM_ClearFlag(TIM_TypeDef* TIMx, u16 TIM_FLAG); -ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, u16 TIM_IT); -void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, u16 TIM_IT); - -#endif /* __75x_TIM_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_type.h b/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_type.h deleted file mode 100644 index 6f8842700..000000000 --- a/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_type.h +++ /dev/null @@ -1,71 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_type.h -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file contains all the common data types used for the -* STR75x software library. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __75x_TYPE_H -#define __75x_TYPE_H - -/* Includes ------------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -typedef signed long s32; -typedef signed short s16; -typedef signed char s8; - -typedef volatile signed long vs32; -typedef volatile signed short vs16; -typedef volatile signed char vs8; - -typedef unsigned long u32; -typedef unsigned short u16; -typedef unsigned char u8; - -typedef volatile unsigned long vu32; -typedef volatile unsigned short vu16; -typedef volatile unsigned char vu8; - -typedef volatile unsigned long const vuc32; /* Read Only */ -typedef volatile unsigned short const vuc16; /* Read Only */ -typedef volatile unsigned char const vuc8; /* Read Only */ - - -typedef enum { FALSE = 0, TRUE = !FALSE } bool; - -typedef enum { RESET = 0, SET = !RESET } FlagStatus, ITStatus; - -typedef enum { DISABLE = 0, ENABLE = !DISABLE} FunctionalState; - -typedef enum { ERROR = 0, SUCCESS = !ERROR} ErrorStatus; - -#define U8_MAX ((u8)255) -#define S8_MAX ((s8)127) -#define S8_MIN ((s8)-128) -#define U16_MAX ((u16)65535u) -#define S16_MAX ((s16)32767) -#define S16_MIN ((s16)-32768) -#define U32_MAX ((u32)4294967295uL) -#define S32_MAX ((s32)2147483647) -#define S32_MIN ((s32)-2147483648) - -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -#endif /* __75x_TYPE_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_uart.h b/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_uart.h deleted file mode 100644 index 6fc5033ab..000000000 --- a/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_uart.h +++ /dev/null @@ -1,178 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_uart.h -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file contains all the functions prototypes for the -* UART software library. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __75x_UART_H -#define __75x_UART_H - -/* Includes ------------------------------------------------------------------*/ -#include "75x_map.h" - -/* Exported types ------------------------------------------------------------*/ -/* UART FIFO Level enumeration */ -typedef enum -{ - UART_FIFOLevel_1_8 = 0x0000, /* FIFO size 16 bytes, FIFO level 2 bytes */ - UART_FIFOLevel_1_4 = 0x0001, /* FIFO size 16 bytes, FIFO level 4 bytes */ - UART_FIFOLevel_1_2 = 0x0002, /* FIFO size 16 bytes, FIFO level 8 bytes */ - UART_FIFOLevel_3_4 = 0x0003, /* FIFO size 16 bytes, FIFO level 12 bytes */ - UART_FIFOLevel_7_8 = 0x0004 /* FIFO size 16 bytes, FIFO level 14 bytes */ -}UART_FIFOLevel; - -/* UART Init Structure definition */ -typedef struct -{ - u16 UART_WordLength; - u16 UART_StopBits; - u16 UART_Parity; - u32 UART_BaudRate; - u16 UART_HardwareFlowControl; - u16 UART_Mode; - u16 UART_FIFO; - UART_FIFOLevel UART_TxFIFOLevel; - UART_FIFOLevel UART_RxFIFOLevel; -}UART_InitTypeDef; - - -/* UART RTS enumeration */ -typedef enum -{ - RTSRESET = 1, - RTSSET -}UART_RTSTypeDef; - - -/* Exported constants --------------------------------------------------------*/ -/* UART Data Length */ -#define UART_WordLength_5D 0x0000 /* 5 bits Data */ -#define UART_WordLength_6D 0x0020 /* 6 bits Data */ -#define UART_WordLength_7D 0x0040 /* 7 bits Data */ -#define UART_WordLength_8D 0x0060 /* 8 bits Data */ - -/* UART Stop Bits */ -#define UART_StopBits_1 0xFFF7 /* One stop bit is transmitted at - the end of frame */ -#define UART_StopBits_2 0x0008 /* Tow stop bits are transmitted - at the end of frame */ - -/* UART Parity */ -#define UART_Parity_No 0x0000 /* Parity Disable */ -#define UART_Parity_Even 0x0006 /* Even Parity */ -#define UART_Parity_Odd 0x0002 /* Odd Parity */ -#define UART_Parity_OddStick 0x0082 /* 1 is transmitted as bit parity */ -#define UART_Parity_EvenStick 0x0086 /* 0 is transmitted as bit parity */ - -/* UART Hardware Flow Control */ -#define UART_HardwareFlowControl_None 0x0000/* HFC Disable */ -#define UART_HardwareFlowControl_RTS 0x4000/* RTS Enable */ -#define UART_HardwareFlowControl_CTS 0x8000/* CTS Enable */ -#define UART_HardwareFlowControl_RTS_CTS 0xC000/* CTS and RTS Enable */ - -/* UART Mode */ -#define UART_Mode_Rx 0x0200 /* UART Rx Enabled */ -#define UART_Mode_Tx 0x0100 /* UART Tx Enbled */ -#define UART_Mode_Tx_Rx 0x0300 /* UART Tx and Rx Enabled */ - -/* UART FIFO */ -#define UART_FIFO_Disable 0xFFEF /* FIFOs Disable */ -#define UART_FIFO_Enable 0x0010 /* FIFOs Enable */ - -/* UART Interrupt definition */ -#define UART_IT_OverrunError 0x0400 /* Overrun Error interrupt */ -#define UART_IT_BreakError 0x0200 /* Break Error interrupt */ -#define UART_IT_ParityError 0x0100 /* Parity Error interrupt */ -#define UART_IT_FrameError 0x0080 /* Frame Error interrupt */ -#define UART_IT_ReceiveTimeOut 0x0040 /* Receive Time Out interrupt */ -#define UART_IT_Transmit 0x0020 /* Transmit interrupt */ -#define UART_IT_Receive 0x0010 /* Receive interrupt */ -#define UART_IT_CTS 0x0002 /* CTS interrupt */ - -/* UART0 DMA transfer */ -#define UART0_DMATransfer_Single 0xFFF7 /* Single DMA transfer */ -#define UART0_DMATransfer_Burst 0x0008 /* Burst DMA transfer */ - -/* UART0 DMA On Error */ -#define UART0_DMAOnError_Enable 0xFFFB /* DMA receive request enabled - when the UART0 error interrupt - is asserted. */ -#define UART0_DMAOnError_Disable 0x0004 /* DMA receive request disabled - when the UART0 error interrupt - is asserted. */ - -/* UART0 DMA Request */ -#define UART0_DMAReq_Tx 0x0002 /* Transmit DMA Enable */ -#define UART0_DMAReq_Rx 0x0001 /* Receive DMA Enable */ - -/* UART FLAG */ -#define UART_FLAG_OverrunError 0x23 /* Overrun error flag */ -#define UART_FLAG_Break 0x22 /* break error flag */ -#define UART_FLAG_ParityError 0x21 /* parity error flag */ -#define UART_FLAG_FrameError 0x20 /* frame error flag */ -#define UART_FLAG_TxFIFOEmpty 0x47 /* Transmit FIFO Empty flag */ -#define UART_FLAG_RxFIFOFull 0x46 /* Receive FIFO Full flag */ -#define UART_FLAG_TxFIFOFull 0x45 /* Transmit FIFO Full flag */ -#define UART_FLAG_RxFIFOEmpty 0x44 /* Receive FIFO Empty flag */ -#define UART_FLAG_Busy 0x43 /* UART Busy flag */ -#define UART_FLAG_CTS 0x40 /* CTS flag */ -#define UART_RawIT_OverrunError 0x6A /* Overrun Error Masked IT flag */ -#define UART_RawIT_BreakError 0x69 /* Break Error Masked IT flag */ -#define UART_RawIT_ParityError 0x68 /* Parity Error Masked IT flag */ -#define UART_RawIT_FrameError 0x67 /* Frame Error Masked IT flag */ -#define UART_RawIT_ReceiveTimeOut 0x66 /* ReceiveTimeOut Masked IT flag */ -#define UART_RawIT_Transmit 0x65 /* Transmit Masked IT flag */ -#define UART_RawIT_Receive 0x64 /* Receive Masked IT flag */ -#define UART_RawIT_CTS 0x61 /* CTS Masked IT flag */ - -/* UART LIN break length */ -#define UART_LINBreakLength_10 0x0000 /* 10 low bits */ -#define UART_LINBreakLength_11 0x0200 /* 11 low bits */ -#define UART_LINBreakLength_12 0x0400 /* 12 low bits */ -#define UART_LINBreakLength_13 0x0600 /* 13 low bits */ -#define UART_LINBreakLength_14 0x0800 /* 14 low bits */ -#define UART_LINBreakLength_15 0x0A00 /* 15 low bits */ -#define UART_LINBreakLength_16 0x0C00 /* 16 low bits */ -#define UART_LINBreakLength_17 0x0E00 /* 17 low bits */ -#define UART_LINBreakLength_18 0x1000 /* 18 low bits */ -#define UART_LINBreakLength_19 0x1200 /* 19 low bits */ -#define UART_LINBreakLength_20 0x1400 /* 20 low bits */ -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -void UART_DeInit(UART_TypeDef* UARTx); -void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct); -void UART_StructInit(UART_InitTypeDef* UART_InitStruct); -void UART_Cmd(UART_TypeDef* UARTx, FunctionalState NewState); -void UART_ITConfig(UART_TypeDef* UARTx, u16 UART_IT, FunctionalState NewState); -void UART_DMAConfig(u16 UART0_DMATransfer, u16 UART0_DMAOnError); -void UART_DMACmd(u16 UART0_DMAReq, FunctionalState NewState); -void UART_LoopBackConfig(UART_TypeDef* UARTx, FunctionalState NewState); -void UART_LINConfig(UART_TypeDef* UARTx, u16 UART_LINBreakLength); -void UART_LINCmd(UART_TypeDef* UARTx, FunctionalState NewState); -void UART_SendData(UART_TypeDef* UARTx, u8 Data); -u8 UART_ReceiveData(UART_TypeDef* UARTx); -void UART_SendBreak(UART_TypeDef* UARTx); -void UART_RTSConfig(UART_TypeDef* UARTx,UART_RTSTypeDef RTSState); -FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, u16 UART_FLAG); -void UART_ClearFlag(UART_TypeDef* UARTx, u16 UART_FLAG); -ITStatus UART_GetITStatus(UART_TypeDef* UARTx, u16 UART_IT); -void UART_ClearITPendingBit(UART_TypeDef* UARTx, u16 UART_IT); - -#endif /* __75x_UART_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_wdg.h b/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_wdg.h deleted file mode 100644 index 3390b63f3..000000000 --- a/Demo/ARM7_STR75x_GCC/STLibrary/inc/75x_wdg.h +++ /dev/null @@ -1,62 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_wdg.h -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file contains all the functions prototypes for the -* WDG software library. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __75x_WDG_H -#define __75x_WDG_H - -/* Includes ------------------------------------------------------------------*/ -#include "75x_map.h" - -/* Exported types ------------------------------------------------------------*/ - typedef struct -{ - u16 WDG_Mode; /* Watchdog or Timer mode */ - u16 WDG_Preload; /* Preload register */ - u8 WDG_Prescaler; /* Prescaler register */ -}WDG_InitTypeDef; -/* Exported constants --------------------------------------------------------*/ - -/* WDG/Timer Select */ -#define WDG_Mode_WDG 0x0001 -#define WDG_Mode_Timer 0xFFFE - -/* WDG End of Count interrupt request */ -#define WDG_IT_EC 0x0001 - -/* WDG end of count Flag */ -#define WDG_FLAG_EC 0x0001 - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -void WDG_DeInit(void); -void WDG_Init(WDG_InitTypeDef* WDG_InitStruct); -void WDG_StructInit(WDG_InitTypeDef* WDG_InitStruct); -void WDG_Cmd(FunctionalState NewState); -void WDG_ITConfig(FunctionalState NewState); -u16 WDG_GetCounter(void); -FlagStatus WDG_GetFlagStatus(void); -void WDG_ClearFlag(void); -ITStatus WDG_GetITStatus(void); -void WDG_ClearITPendingBit(void); - -#endif /* __WDG_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_GCC/STLibrary/inc/lcd.h b/Demo/ARM7_STR75x_GCC/STLibrary/inc/lcd.h deleted file mode 100644 index 11df54c1b..000000000 --- a/Demo/ARM7_STR75x_GCC/STLibrary/inc/lcd.h +++ /dev/null @@ -1,120 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : lcd.h -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file contains all the functions prototypes for the -* lcd software driver. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion ---------------------------------------*/ -#ifndef __LCD_H -#define __LCD_H - -/* Includes --------------------------------------------------------------------*/ -#include "75x_lib.h" - -/* Exported types --------------------------------------------------------------*/ - - /* Data lines configuration mode */ - typedef enum - { - Input, - Output - } DataConfigMode_TypeDef; - - /* Text color mode */ - typedef enum - { - BlackText=0, - WhiteText=1 - } TextColorMode_TypeDef; - - /* Dot On/Off mode */ - typedef enum - { - Dot_On, - Dot_Off - } DotMode_TypeDef; - -/* Exported constants ----------------------------------------------------------*/ - -/* LCD Control pins */ -#define CtrlPin_E2 0x00000001 -#define CtrlPin_E1 0x00000002 -#define CtrlPin_RW 0x00000004 -#define CtrlPin_DI 0x00000008 - -/* LCD Commands */ -#define DISPLAY_ON 0xAF -#define DISPLAY_OFF 0xAE -#define START_LINE 0xC0 -#define START_COLUMN 0x00 -#define CLOCKWISE_OUTPUT 0xA0 -#define DYNAMIC_DRIVE 0xA4 -#define DUTY_CYCLE 0xA9 -#define READ_MODIFY_WRITE_OFF 0xEE -#define SOFTWARE_RESET 0xE2 - -/* LCD Lines when LCD is managed as 2*17 characters */ -#define Line1 0x0 -#define Line2 0x2 - -/* Exported macro --------------------------------------------------------------*/ -/* Exported functions ----------------------------------------------------------*/ -/*----- Low layer function -----*/ -void LCD_CtrlLinesConfig(void); -void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, u32 CtrlPins, BitAction BitVal); -void LCD_DataLinesConfig(DataConfigMode_TypeDef Mode); -void LCD_DataLinesWrite(GPIO_TypeDef* GPIOx, u32 PortVal); - -/*----- Medium layer function -----*/ -void LCD_CheckMasterStatus(void); -void LCD_CheckSlaveStatus(void); -void LCD_SendMasterCmd(u8 Cmd); -void LCD_SendSlaveCmd(u8 Cmd); -void LCD_SendMasterData(u8 Data); -u32 LCD_ReadMasterData(void); -void LCD_SendSlaveData(u8 Data); -u32 LCD_ReadSlaveData(void); -void LCD_SetMasterPage(u8 Page); -void LCD_SetSlavePage(u8 Page); -void LCD_SetMasterColumn(u8 Address); -void LCD_SetSlaveColumn(u8 Address); -void LCD_DrawChar(u8 Line, u8 Column, u8 Width, u8 *Bmp); -u8 LCD_HexToAsciiLow(u8 byte); -u8 LCD_HexToAsciiHigh(u8 byte); -void LCD_SetTextColor(TextColorMode_TypeDef TextColor); - -/*----- High layer function -----*/ -void LCD_Init(void); -/* LCD managed as 2 Lines, 17 characters each one (2Lines*17Char) */ -void LCD_ClearLine(u8 Line); -void LCD_DisplayChar(u8 Line, u8 Column, u8 Ascii, TextColorMode_TypeDef CharMode); -void LCD_DisplayString(u8 Line, u8 *ptr, TextColorMode_TypeDef CharMode); -void LCD_Printf(u8* ptr, ...); -/* LCD managed as 122*32 dots */ -void LCD_ClearMaster(void); -void LCD_ClearSlave(void); -void LCD_Clear(void); -void LCD_DrawMasterGraphic(u8 *Bmp); -void LCD_DrawSlaveGraphic(u8 *Bmp); -void LCD_DrawGraphic(u8 *Bmp); -void LCD_ScrollGraphic(u8 *Bmp, u32 nCount); -void LCD_DrawPixel(u8 XPos, u8 YPos, DotMode_TypeDef Mode); -void LCD_DrawLine(u8 XPos1, u8 YPos1, u8 XPos2, u8 YPos2); -void LCD_DrawBox(u8 XPos, u8 YPos, u8 Dx, u8 Dy); - -#endif /*__LCD_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE******/ diff --git a/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_adc.c b/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_adc.c deleted file mode 100644 index 93905cb6c..000000000 --- a/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_adc.c +++ /dev/null @@ -1,869 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_adc.c -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file provides all the ADC software functions. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -#include "75x_adc.h" -#include "75x_mrcc.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Mask for Power Down Mode */ -#define ADC_PowerDown_Enable 0x8000 -#define ADC_PowerDown_Disable 0x7FFF - -/* Mask for Watchdog Thresholds Enable */ -#define ADC_AnalogWatchdog_Enable 0x8000 -#define ADC_AnalogWatchdog_Disable 0x7FFF - -/* Mask for Injected conversion start */ -#define ADC_Injec_ConversionStart 0x8000 - -/* DMA enable */ -#define ADC_DMA_ExtEnable_Mask 0x4000 - -/* Injected start trigger enable */ -#define ADC_Injec_ExtTrigger_Enable 0x4000 - -/* ADC Masks */ -#define ADC_DMAFirstEnabledChannel_Mask 0x000F -#define ADC_DataRegisterOffset 0x0050 -#define ADC_FirstChannel_Mask 0xFFF0 -#define ADC_ChannelNumber_Mask 0xFC3F -#define ADC_Threshold_Mask 0xFC00 -#define ADC_AnalogWatchdogChannel_Mask 0xC3FF -#define ADC_Prescalers_Mask 0x7F18 -#define ADC_SPEN_Mask 0x8000 -#define ADC_FallingEdge_Mask 0xEFFF -#define ADC_LowLevel_Mask 0x4000 -#define ADC_HighLevel_Mask 0xDFFF -#define ADC_Calibration_Mask 0x0002 - -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/******************************************************************************* -* Function Name : ADC_DeInit -* Description : Deinitializes the ADC peripheral registers to their default -* reset values. -* Input : None. -* Output : None -* Return : None. -*******************************************************************************/ -void ADC_DeInit(void) -{ - /* Reset the ADC registers values*/ - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_ADC,ENABLE); - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_ADC,DISABLE); -} - -/******************************************************************************* -* Function Name : ADC_Init -* Description : Initializes the ADC peripheral according to the specified -* parameters in the ADC_InitStruct. -* Input : - ADC_InitStruct: pointer to an ADC_InitTypeDef structure that - contains the configuration information for the ADC peripheral. -* Output : None -* Return : None -*******************************************************************************/ -void ADC_Init(ADC_InitTypeDef* ADC_InitStruct) -{ - /* Configure the conversion mode */ - if(ADC_InitStruct->ADC_ConversionMode == ADC_ConversionMode_Scan) - { - /* Set the scan conversion mode */ - ADC->CLR2 |= ADC_ConversionMode_Scan; - } - else - { - /* Set the one-shot conversion mode */ - ADC->CLR2 &= ADC_ConversionMode_OneShot; - } - - /* Configure the external start conversion trigger */ - switch(ADC_InitStruct->ADC_ExtTrigger) - { - case ADC_ExtTrigger_HighLevel: - /* Start conversion on High level of the external trigger (TIM0) */ - ADC->CLR0 &= ADC_HighLevel_Mask; - ADC->CLR0 |= ADC_ExtTrigger_HighLevel; - break; - - case ADC_ExtTrigger_LowLevel: - /* Start conversion on low level of the external trigger (TIM0) */ - ADC->CLR0 &= ADC_ExtTrigger_LowLevel; - ADC->CLR0 |= ADC_LowLevel_Mask; - break; - - case ADC_ExtTrigger_RisingEdge: - /* Start conversion on rising edge of the external trigger (TIM0) */ - ADC->CLR0 |= ADC_ExtTrigger_RisingEdge; - break; - - case ADC_ExtTrigger_FallingEdge: - /* Start conversion on falling edge of the external trigger (TIM0) */ - ADC->CLR0 &= ADC_FallingEdge_Mask; - ADC->CLR0 |= ADC_ExtTrigger_FallingEdge; - break; - - case ADC_ExtTrigger_Disable: - /* Disable the external trigger and start the conversion by software */ - ADC->CLR0 &= ADC_ExtTrigger_Disable; - break; - - default: - break; - } - - /* Configure the auto clock off feature */ - if (ADC_InitStruct->ADC_AutoClockOff == ADC_AutoClockOff_Enable) - { - /* Enable the auto clock off feature */ - ADC->CLR4 |= ADC_AutoClockOff_Enable; - } - else - { - /* Disable the auto clock off feature */ - ADC->CLR4 &= ADC_AutoClockOff_Disable; - } - - /* Clear conversion prescaler CNVP[2:0], sampling prescaler SMPP[2:0] bits - and Sample prescaler enable SPEN bit */ - ADC->CLR1 &= ADC_Prescalers_Mask; - /* Set conversion prescaler value (sampling and conversion prescalers are equal - while SPEN bit is reset */ - ADC->CLR1 |= (ADC_InitStruct->ADC_ConversionPrescaler<<5); - - /* In case ADC_SamplingPrescaler member is different from the conversion one */ - if(ADC_InitStruct->ADC_SamplingPrescaler != ADC_InitStruct->ADC_ConversionPrescaler) - { - /* Set the sampling prescaler value */ - ADC->CLR1 |= ADC_InitStruct->ADC_SamplingPrescaler; - /* Set SPEN bit (sampling and conversion prescalers are different */ - ADC->CLR1 = (ADC->CLR1 | ADC_SPEN_Mask); - } - - /* Clear first channel to be converted FCH[3:0] bits */ - ADC->CLR2 &= ADC_FirstChannel_Mask; - /* Set the first channel to be converted */ - ADC->CLR2 |= ADC_InitStruct->ADC_FirstChannel; - /* Clear number of channels to be converted NCH[3:0] bits */ - ADC->CLR2 &= ADC_ChannelNumber_Mask; - /* Set the number of channels to be converted */ - ADC->CLR2 |= ((ADC_InitStruct->ADC_ChannelNumber)-1<<6); -} - -/******************************************************************************* -* Function Name : ADC_StructInit -* Description : Fills each ADC_InitStruct member with its default value. -* Input : - ADC_InitStruct: pointer to an ADC_InitTypeDef structure - which will be initialized. -* Output : None -* Return : None. -*******************************************************************************/ -void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) -{ - /* Initialize the ADC_ConversionMode member */ - ADC_InitStruct->ADC_ConversionMode = ADC_ConversionMode_OneShot; - - /* Initialize the ADC_ExtTrigger member */ - ADC_InitStruct->ADC_ExtTrigger = ADC_ExtTrigger_Disable; - - /* Initialize the ADC_AutoClockOff member */ - ADC_InitStruct->ADC_AutoClockOff = ADC_AutoClockOff_Disable; - - /* Initialize the ADC_SamplingPrescaler member */ - ADC_InitStruct->ADC_SamplingPrescaler = 0; - - /* Initialize the ADC_ConversionPrescaler member */ - ADC_InitStruct->ADC_ConversionPrescaler = 0; - - /* Initialize the ADC_FirstChannel member */ - ADC_InitStruct->ADC_FirstChannel = ADC_CHANNEL0; - - /* Initialize the ADC_ChannelNumber member */ - ADC_InitStruct->ADC_ChannelNumber = 1; - } - -/******************************************************************************* -* Function Name : ADC_StartCalibration -* Description : Starts the ADC Calibration. Calibration average enabled/disabled. -* Input : - ADC_CalibAverage: Enables or disables ADC calibration average. -* This parameter can be one of the following values: -* - ADC_CalibAverage_Enable: enable calibration average -* - ADC_CalibAverage_Disable: disable calibration average -* Output : None -* Return : None -*******************************************************************************/ -void ADC_StartCalibration(u16 ADC_CalibAverage) -{ - if (ADC_CalibAverage == ADC_CalibAverage_Enable) - { - /* Enable ADC Calibration Average */ - ADC->CLR4 &= ADC_CalibAverage_Enable; - } - else - { - /* Disable ADC Calibration Average */ - ADC->CLR4 |= ADC_CalibAverage_Disable; - } - - /* Start Calibration */ - ADC->CLR0 |= ADC_Calibration_ON; -} - -/******************************************************************************* -* Function Name : ADC_GetCalibrationStatus -* Description : Get the ADC Calibration Status. -* Input : None -* Output : None -* Return : The NewState of the ADC calibration (SET or RESET). -*******************************************************************************/ -FlagStatus ADC_GetCalibrationStatus(void) -{ - /* Check the status of the ADC calibration */ - if((ADC->CLR0 & ADC_Calibration_Mask) != RESET) - { - /* Return SET if ADC Calibration is on going */ - return SET; - } - else - { - /* Return RESET if ADC Calibration is finished */ - return RESET; - } -} - -/******************************************************************************* -* Function Name : ADC_ConversionCmd -* Description : Starts or stops the ADC conversion. -* Input : - ADC_Conversion: specifies the ADC command to apply. -* This parameter can be one of the following values: -* - ADC_Conversion_Start: start conversion -* - ADC_Conversion_Stop: stop conversion -* Output : None -* Return : None -*******************************************************************************/ -void ADC_ConversionCmd (u16 ADC_Conversion) -{ - if (ADC_Conversion == ADC_Conversion_Start) - { - /* Start the ADC Conversion */ - ADC->CLR0 |= ADC_Conversion_Start; - } - else - { - /* Stop the ADC Conversion */ - ADC->CLR0 &= ADC_Conversion_Stop; - } -} - -/******************************************************************************* -* Function Name : ADC_GetSTARTBitStatus -* Description : Gets the ADC START/STOP bit Status. -* Input : None -* Output : None -* Return : The NewState of the ADC START/STOP bit (SET or RESET). -*******************************************************************************/ -FlagStatus ADC_GetSTARTBitStatus(void) -{ - /* Check the status of the ADC START/STOP bit */ - if((ADC->CLR0 & ADC_Conversion_Start) != RESET) - { - /* Return SET if ADC Conversion is started */ - return SET; - } - else - { - /* Return RESET if ADC Conversion is stopped */ - return RESET; - } -} - -/******************************************************************************* -* Function Name : ADC_Cmd -* Description : Enables the ADC peripheral or puts it in power down mode. -* - NewState: new state of the ADC peripheral. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None. -*******************************************************************************/ -void ADC_Cmd(FunctionalState NewState) -{ - if (NewState == DISABLE) - { - /* Enable ADC Power Down Mode */ - ADC->CLR4 |= ADC_PowerDown_Enable; - } - else - { - /* Disable ADC Power Down Mode */ - ADC->CLR4 &= ADC_PowerDown_Disable; - } -} - -/******************************************************************************* -* Function Name : ADC_AutoClockOffConfig -* Description : Enables or disables the Auto clock off feature. -* - NewState: new state of the Auto clock off feature. This -* parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None. -*******************************************************************************/ -void ADC_AutoClockOffConfig(FunctionalState NewState) -{ - if (NewState == ENABLE) - { - /* Enable ADC Auto Clock Off */ - ADC->CLR4 |= ADC_AutoClockOff_Enable; - } - else - { - /* Disable ADC Auto Clock Off */ - ADC->CLR4 &= ADC_AutoClockOff_Disable; - } -} - -/******************************************************************************* -* Function Name : ADC_AnalogWatchdogConfig -* Description : Configures the analog input channel to be used for the selected -* Analog Watchdog and defines its corresponding High and Low -* threshold values. -* Input : - ADC_AnalogWatchdog: specifies the analog watchdog which will -* be affected to the desired converted channel. This parameter -* can be one of the following values: -* - ADC_AnalogWatchdog0: select analog watchdog 0 -* - ADC_AnalogWatchdog1: select analog watchdog 1 -* - ADC_AnalogWatchdog2: select analog watchdog 2 -* - ADC_AnalogWatchdog3: select analog watchdog 3 -* - ADC_CHANNEL: specifies the channel linked to the selected -* analog watchdog. This parameter can be ADC_CHANNELx where x -* can be (0..15) -* - LowThreshold: Low Threshold for the selected Analog watchdog -* - HighThreshold: High Threshold for the selected Analog watchdog -* Output : None -* Return : None -*******************************************************************************/ -void ADC_AnalogWatchdogConfig(u16 ADC_AnalogWatchdog, u8 ADC_CHANNEL, - u16 LowThreshold, u16 HighThreshold) -{ - switch (ADC_AnalogWatchdog) - { - /* Set the selected channel and their corresponding High and Low thresholds */ - case ADC_AnalogWatchdog0 : - ADC->TRA0 = (ADC->TRA0 & ADC_AnalogWatchdogChannel_Mask) | ((u16) ADC_CHANNEL<<10); - ADC->TRA0 = (ADC->TRA0 & ADC_Threshold_Mask) | HighThreshold; - ADC->TRB0 = (ADC->TRB0 & ADC_Threshold_Mask) | LowThreshold; - break; - - case ADC_AnalogWatchdog1 : - ADC->TRA1 = (ADC->TRA1 & ADC_AnalogWatchdogChannel_Mask) | ((u16) ADC_CHANNEL<<10); - ADC->TRA1 = (ADC->TRA1 & ADC_Threshold_Mask) | HighThreshold; - ADC->TRB1 = (ADC->TRB1 & ADC_Threshold_Mask) | LowThreshold; - break; - - case ADC_AnalogWatchdog2 : - ADC->TRA2 = (ADC->TRA2 & ADC_AnalogWatchdogChannel_Mask) | ((u16) ADC_CHANNEL<<10); - ADC->TRA2 = (ADC->TRA2 & ADC_Threshold_Mask) | HighThreshold; - ADC->TRB2 = (ADC->TRB2 & ADC_Threshold_Mask) | LowThreshold; - break; - - case ADC_AnalogWatchdog3 : - ADC->TRA3 = (ADC->TRA3 & ADC_AnalogWatchdogChannel_Mask) | ((u16) ADC_CHANNEL<<10); - ADC->TRA3 = (ADC->TRA3 & ADC_Threshold_Mask) | HighThreshold; - ADC->TRB3 = (ADC->TRB3 & ADC_Threshold_Mask) | LowThreshold; - break; - - default: - break; - } -} - -/******************************************************************************* -* Function Name : ADC_AnalogWatchdogCmd -* Description : Enables or disables the selected analog Watchdog. -* Input : - ADC_AnalogWatchdog: specifies the analog watchdog to be -* enabled or disabled. This parameter can be one of the -* following values: -* - ADC_AnalogWatchdog0: select analog watchdog 0 -* - ADC_AnalogWatchdog1: select analog watchdog 1 -* - ADC_AnalogWatchdog2: select analog watchdog 2 -* - ADC_AnalogWatchdog3: select analog watchdog 3 -* - NewState: new state of the specified analog watchdog. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None. -*******************************************************************************/ -void ADC_AnalogWatchdogCmd(u16 ADC_AnalogWatchdog, FunctionalState NewState) -{ - if (NewState == ENABLE) - { - /* Enable the selected ADC AnalogWatchdogx */ - switch (ADC_AnalogWatchdog) - { - case ADC_AnalogWatchdog0 : - ADC->TRB0 |= ADC_AnalogWatchdog_Enable; - break; - - case ADC_AnalogWatchdog1 : - ADC->TRB1 |= ADC_AnalogWatchdog_Enable; - break; - - case ADC_AnalogWatchdog2 : - ADC->TRB2 |= ADC_AnalogWatchdog_Enable; - break; - - case ADC_AnalogWatchdog3 : - ADC->TRB3 |= ADC_AnalogWatchdog_Enable; - break; - - default: - break; - } - } - else - { - /* Disable the selected ADC AnalogWatchdogx */ - switch (ADC_AnalogWatchdog) - { - case ADC_AnalogWatchdog0 : - ADC->TRB0 &= ADC_AnalogWatchdog_Disable; - break; - - case ADC_AnalogWatchdog1 : - ADC->TRB1 &= ADC_AnalogWatchdog_Disable; - break; - - case ADC_AnalogWatchdog2 : - ADC->TRB2 &= ADC_AnalogWatchdog_Disable; - break; - - case ADC_AnalogWatchdog3 : - ADC->TRB3 &= ADC_AnalogWatchdog_Disable; - break; - - default: - break; - } - } -} - -/******************************************************************************* -* Function Name : ADC_GetAnalogWatchdogResult -* Description : Returns the comparison result of the selected analog watchdog. -* Input : - ADC_AnalogWatchdog: specifies the analog watchdog channel -* which its comparison result will be returned. This parameter -* can be one of the following values: -* - ADC_AnalogWatchdog0: select analog watchdog 0 -* - ADC_AnalogWatchdog1: select analog watchdog 1 -* - ADC_AnalogWatchdog2: select analog watchdog 2 -* - ADC_AnalogWatchdog3: select analog watchdog 3 -* Output : None -* Return : The analog watchdog comparaison result value -*******************************************************************************/ -u16 ADC_GetAnalogWatchdogResult(u16 ADC_AnalogWatchdog) -{ - /* Return the selected ADC AnalogWatchdogx comparaison result */ - switch(ADC_AnalogWatchdog) - { - case ADC_AnalogWatchdog0 : - return ((ADC->PBR & ADC_AnalogWatchdog)>>4); - - case ADC_AnalogWatchdog1 : - return ((ADC->PBR & ADC_AnalogWatchdog)>>6); - - case ADC_AnalogWatchdog2 : - return ((ADC->PBR & ADC_AnalogWatchdog)>>8); - - case ADC_AnalogWatchdog3 : - return ((ADC->PBR & ADC_AnalogWatchdog)>>10); - - default : return (0xFF); /* if a wrong value of ADC_AnalogWatchdog is selected */ - } -} - -/******************************************************************************* -* Function Name : ADC_InjectedConversionConfig -* Description : Configures the start trigger level for the injected channels -* and the injected analog input channels to be converted. -* Input : - ADC_Injec_ExtTrigger: specifies the start trigger level. -* This parameter can be one of the following values: -* - ADC_Injec_ExtTrigger_Disable : external trigger disabled -* - ADC_Injec_ExtTrigger_RisingEdge: external trigger -* configured as rising edge of PWM Timer TRGO signal -* - ADC_Injec_ExtTrigger_FallingEdge: external trigger -* configured as falling edge of PWM Timer TRGO signal -* - FirstChannel: specifies the first injected channel to be -* converted. -* This parameter can be ADC_CHANNELx where x can be (0..15). -* - ChannelNumber: specifies the Number of the injected channels -* to be converted. This parameter can be a value from 1 to 16. -* Output : None -* Return : None -*******************************************************************************/ -void ADC_InjectedConversionConfig(u16 ADC_Injec_ExtTrigger, u8 FirstChannel, u8 ChannelNumber) -{ - /* Configure the external start injected conversion trigger */ - switch (ADC_Injec_ExtTrigger) - { - case ADC_Injec_ExtTrigger_Disable : - /* Disable the external trigger and start the injected conversion by software */ - ADC->CLR3 &= ADC_Injec_ExtTrigger_Disable ; - break; - case ADC_Injec_ExtTrigger_RisingEdge : - /* Start injected conversion on rising edge of the external trigger (PWM) */ - ADC->CLR3 |= ADC_Injec_ExtTrigger_RisingEdge; - break; - case ADC_Injec_ExtTrigger_FallingEdge : - /* Start injected conversion on falling edge of the external trigger (PWM) */ - ADC->CLR3 |= ADC_Injec_ExtTrigger_Enable; - ADC->CLR3 &= ADC_Injec_ExtTrigger_FallingEdge; - break; - - default: - break; - } - - /* Clear first injected channel to be converted JFCH[3:0] bits */ - ADC->CLR3 &= ADC_FirstChannel_Mask; - /* Set the first injected channel to be converted */ - ADC->CLR3 |= FirstChannel; - /* Clear number of injected channels to be converted JNCH[3:0] bits */ - ADC->CLR3 &= ADC_ChannelNumber_Mask; - /* Set the number of injected channels to be converted */ - ADC->CLR3 |= ((ChannelNumber-1)<<6); -} - -/******************************************************************************* -* Function Name : ADC_StartInjectedConversion -* Description : Starts by software the conversion of the injected input channels. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void ADC_StartInjectedConversion(void) -{ - /* Start the injected ADC Conversion */ - ADC->CLR3 |= ADC_Injec_ConversionStart; -} - -/******************************************************************************* -* Function Name : ADC_GetConversionValue -* Description : Reads the conversion result from the appropriate data register. -* Input : - ADC_CHANNEL :specifies the ADC channel which its conversion -* value have to be returned. This parameter can be ADC_CHANNELx -* where x can be (0..15) to select channelx -* Output : None -* Return : The returned value holds the conversion result of the selected -* channel. -*******************************************************************************/ -u16 ADC_GetConversionValue(u8 ADC_CHANNEL) -{ - /* Return the conversion result of the selected channel */ - return *((u16 *)(ADC_BASE + ((ADC_CHANNEL<<2) + ADC_DataRegisterOffset))); -} - -/******************************************************************************* -* Function Name : ADC_ITConfig -* Description : Enables or disables the specified ADC interrupts. -* Input : - ADC_IT: specifies the ADC interrupts to be enabled or disabled. -* This parameter can be any combination of the following values: -* - ADC_IT_ECH: End of chain conversion interrupt -* - ADC_IT_EOC: End of channel conversion interrupt -* - ADC_IT_JECH: Injected end of chain conversion interrupt -* - ADC_IT_JEOC: Injected end of channel conversion interrupt -* - ADC_IT_AnalogWatchdog0_LowThreshold: -* Analog Watchdog 0 LowThreshold interrupt -* - ADC_IT_AnalogWatchdog0_HighThreshold: -* Analog Watchdog 0 HighThreshold interrupt -* - ADC_IT_AnalogWatchdog1_LowThreshold: -* Analog Watchdog 1 LowThreshold interrupt -* - ADC_IT_AnalogWatchdog1_HighThreshold: -* Analog Watchdog 1 HighThreshold interrupt -* - ADC_IT_AnalogWatchdog2_LowThreshold: -* Analog Watchdog 2 LowThreshold interrupt -* - ADC_IT_AnalogWatchdog2_HighThreshold: -* Analog Watchdog 2 HighThreshold interrupt -* - ADC_IT_AnalogWatchdog3_LowThreshold: -* Analog Watchdog 3 LowThreshold interrupt -* - ADC_IT_AnalogWatchdog3_HighThreshold: -* Analog Watchdog 5 HighThreshold interrupt -* - ADC_IT_ALL: All interrupts -* - NewState: new state of the specified ADC interrupts. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void ADC_ITConfig(u16 ADC_IT, FunctionalState NewState) -{ - if (NewState == ENABLE) - { - /* Enable the selected ADC interrupts */ - ADC->IMR |= ADC_IT; - } - else - { - /* Disable the selected ADC interrupts */ - ADC->IMR &= ~ADC_IT; - } -} - -/******************************************************************************* -* Function Name : ADC_DMAConfig -* Description : Configures the ADC’s DMA interface. -* Input : - ADC_DMA_CHANNEL: specifies the channels to be enabled or -* disabled for DMA transfer. This parameter can be any -* combination of ADC_DMA_CHANNELx where x can be (0..15). -* - NewState: new state of the specified ADC DMA channels. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void ADC_DMAConfig(u16 ADC_DMA_CHANNEL, FunctionalState NewState) -{ - if(NewState == ENABLE) - { - /* Enable DMA for the selected channels */ - ADC->DMAR |= ADC_DMA_CHANNEL ; - } - else - { - /* Disable DMA for the selected channels */ - ADC->DMAR &= ~ADC_DMA_CHANNEL; - } -} - -/******************************************************************************* -* Function Name : ADC_DMACmd -* Description : Enable or disable the DMA transfer for the ADC. -* Input : - ADC_DMA: specifies the DMA command. This parameter can be -* one of the following values: -* - ADC_DMA_Disable: disable the DMA capability -* - ADC_DMA_Enable: enabled by setting the global -* enable bit -* - ADC_DMA_ExtTrigger_HighLevel: enabled by detection of -* high level of TIM2 OC2 signal -* - ADC_DMA_ExtTrigger_LowLevel: enabled by detection of -* low level of TIM2 OC2 signal -* Output : None -* Return : None -*******************************************************************************/ -void ADC_DMACmd(u16 ADC_DMA) -{ - /* Configure the DMA external trigger enable */ - switch (ADC_DMA) - { - case ADC_DMA_Disable : - /* Disable DMA transfer */ - ADC->DMAE &= ADC_DMA_Disable; - break; - - case ADC_DMA_Enable : - /* Enable DMA transfer */ - ADC->DMAE |= ADC_DMA_Enable; - break; - - case ADC_DMA_ExtTrigger_HighLevel : - /* Enable DMA transfer on high level of the external trigger (TIM2) */ - ADC->DMAE &= ADC_DMA_Disable; - ADC->DMAE |= ADC_DMA_ExtTrigger_HighLevel; - break; - - case ADC_DMA_ExtTrigger_LowLevel : - /* Enable DMA transfer on low level of the external trigger (TIM2) */ - ADC->DMAE |= ADC_DMA_ExtEnable_Mask; - ADC->DMAE &= ADC_DMA_ExtTrigger_LowLevel; - break; - - default: - break; - } -} - -/******************************************************************************* -* Function Name : ADC_GetDMAFirstEnabledChannel -* Description : Gets the first DMA-enabled channel configured at the time that -* DMA was last globally enabled. -* Input : None -* Output : None -* Return : The first DMA enabled channel -*******************************************************************************/ -u16 ADC_GetDMAFirstEnabledChannel(void) -{ - /* Return the DMA first enabled channel */ - return (ADC->DMAE & ADC_DMAFirstEnabledChannel_Mask); -} - -/******************************************************************************* -* Function Name : ADC_GetFlagStatus -* Description : Checks whether the specified ADC flag is set or not. -* Input : - ADC_FLAG: specifies the ADC flag to check. This parameter -* can be one of the following values: -* - ADC_FLAG_ECH: End of chain conversion Flag -* - ADC_FLAG_EOC: End of channel conversion Flag -* - ADC_FLAG_JECH: End of injected chain conversion Flag -* - ADC_FLAG_JEOC: End of injected channel conversion Flag -* - ADC_FLAG_AnalogWatchdog0_LowThreshold: -* Analog Watchdog 0 LowThreshold Flag -* - ADC_FLAG_AnalogWatchdog0_HighThreshold: -* Analog Watchdog 0 HighThreshold Flag -* - ADC_FLAG_AnalogWatchdog1_LowThreshold: -* Analog Watchdog 1 LowThreshold Flag -* - ADC_FLAG_AnalogWatchdog1_HighThreshold: -* Analog Watchdog 1 HighThreshold Flag -* - ADC_FLAG_AnalogWatchdog2_LowThreshold: -* Analog Watchdog 2 LowThreshold Flag -* - ADC_FLAG_AnalogWatchdog2_HighThreshold: -* Analog Watchdog 2 HighThreshold Flag -* - ADC_FLAG_AnalogWatchdog3_LowThreshold: -* Analog Watchdog 3 LowThreshold Flag -* - ADC_FLAG_AnalogWatchdog3_HighThreshold: -* Analog Watchdog 3 HighThreshold Flag -* Output : None -* Return : The new state of the ADC_FLAG (SET or RESET). -*******************************************************************************/ -FlagStatus ADC_GetFlagStatus(u16 ADC_FLAG) -{ - /* Check the status of the specified ADC flag */ - if((ADC->PBR & ADC_FLAG) != RESET) - { - /* Return SET if ADC_FLAG is set */ - return SET; - } - else - { - /* Return RESET if ADC_FLAG is reset */ - return RESET; - } -} - -/******************************************************************************* -* Function Name : ADC_ClearFlag -* Description : Clears the ADC’s pending flags. -* Input : - ADC_FLAG: specifies the flag to clear. This parameter can -* be any combination of the following values: -* - ADC_FLAG_ECH: End of chain conversion flag -* - ADC_FLAG_EOC: End of channel conversion flag -* - ADC_FLAG_JECH: Injected end of chain conversion flag -* - ADC_FLAG_JEOC: Injected end of channel conversion flag -* - ADC_FLAG_AnalogWatchdog0_LowThreshold: -* Analog Watchdog 0 LowThreshold flag -* - ADC_FLAG_AnalogWatchdog0_HighThreshold: -* Analog Watchdog 0 HighThreshold flag -* - ADC_FLAG_AnalogWatchdog1_LowThreshold: -* Analog Watchdog 1 LowThreshold flag -* - ADC_FLAG_AnalogWatchdog1_HighThreshold: -* Analog Watchdog 1 HighThreshold flag -* - ADC_FLAG_AnalogWatchdog2_LowThreshold: -* Analog Watchdog 2 LowThreshold flag -* - ADC_FLAG_AnalogWatchdog2_HighThreshold: -* Analog Watchdog 2 HighThreshold flag -* - ADC_FLAG_AnalogWatchdog3_LowThreshold: -* Analog Watchdog 3 LowThreshold flag -* - ADC_FLAG_AnalogWatchdog3_HighThreshold: -* Analog Watchdog 3 HighThreshold flag -* Output : None -* Return : None -*******************************************************************************/ -void ADC_ClearFlag(u16 ADC_FLAG) -{ - /* Clear the selected ADC flag */ - ADC->PBR = ADC_FLAG; -} - -/******************************************************************************* -* Function Name : ADC_GetITStatus -* Description : Checks whether the specified ADC interrupt has occured or not. -* Input : - ADC_IT: specifies the ADC interrupt source to check. This -* parameter can be one of the following values: -* - ADC_IT_ECH :End of chain conversion interrupt -* - ADC_IT_EOC :End of channel conversion interrupt -* - ADC_IT_JECH :End of injected chain conversion interrupt -* - ADC_IT_JEOC :End of injected channel conversion interrupt -* - ADC_IT_AnalogWatchdog0_LowThreshold: -* Analog Watchdog 0 LowThreshold interrupt -* - ADC_IT_AnalogWatchdog0_HighThreshold: -* Analog Watchdog 0 HighThreshold interrupt -* - ADC_IT_AnalogWatchdog1_LowThreshold: -* Analog Watchdog 1 LowThreshold interrupt -* - ADC_IT_AnalogWatchdog1_HighThreshold: -* Analog Watchdog 1 HighThreshold interrupt -* - ADC_IT_AnalogWatchdog2_LowThreshold: -* Analog Watchdog 2 LowThreshold interrupt -* - ADC_IT_AnalogWatchdog2_HighThreshold: -* Analog Watchdog 2 HighThreshold interrupt -* - ADC_IT_AnalogWatchdog3_LowThreshold: -* Analog Watchdog 3 LowThreshold interrupt -* - ADC_IT_AnalogWatchdog3_HighThreshold: -* Analog Watchdog 3 HighThreshold interrupt -* Output : None -* Return : The new state of the ADC_IT (SET or RESET). -*******************************************************************************/ -ITStatus ADC_GetITStatus(u16 ADC_IT) -{ - /* Check the status of the specified ADC interrupt */ - if((ADC->PBR & ADC_IT) != RESET) - { - /* Return SET if the ADC interrupt flag is set */ - return SET; - } - else - { - /* Return RESET if the ADC interrupt flag is reset */ - return RESET; - } -} - -/******************************************************************************* -* Function Name : ADC_ClearITPendingBit -* Description : Clears the ADC’s interrupt pending bits. -* Input : - ADC_IT: specifies the interrupt pending bit to clear. This -* parameter can be can be any combination of the following -* values: -* - ADC_IT_ECH: End of chain conversion interrupt -* - ADC_IT_EOC: End of channel conversion interrupt -* - ADC_IT_JECH: Injected end of chain conversion interrupt -* - ADC_IT_JEOC: Injected end of channel conversion interrupt -* - ADC_IT_AnalogWatchdog0_LowThreshold: -* Analog Watchdog 0 LowThreshold interrupt -* - ADC_IT_AnalogWatchdog0_HighThreshold: -* Analog Watchdog 0 HighThreshold interrupt -* - ADC_IT_AnalogWatchdog1_LowThreshold: -* Analog Watchdog 1 LowThreshold interrupt -* - ADC_IT_AnalogWatchdog1_HighThreshold: -* Analog Watchdog 1 HighThreshold interrupt -* - ADC_IT_AnalogWatchdog2_LowThreshold: -* Analog Watchdog 2 LowThreshold interrupt -* - ADC_IT_AnalogWatchdog2_HighThreshold: -* Analog Watchdog 2 HighThreshold interrupt -* - ADC_IT_AnalogWatchdog3_LowThreshold: -* Analog Watchdog 3 LowThreshold interrupt -* - ADC_IT_AnalogWatchdog3_HighThreshold: -* Analog Watchdog 5 HighThreshold interrupt -* Output : None -* Return : None -*******************************************************************************/ -void ADC_ClearITPendingBit(u16 ADC_IT) -{ - /* Clear the selected ADC interrupts pending bits */ - ADC->PBR = ADC_IT; -} - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_can.c b/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_can.c deleted file mode 100644 index 0472200ba..000000000 --- a/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_can.c +++ /dev/null @@ -1,765 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_can.c -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file provides all the CAN software functions. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -#include "75x_can.h" -#include "75x_mrcc.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/*----------------------------------------------------------------------------*/ -/* Macro Name : xxx_ID_MSK, xxx_ID_ARB */ -/* Description : Form the Mask and Arbitration registers value to filter */ -/* a range of identifiers or a fixed identifier, for standard*/ -/* and extended IDs */ -/*----------------------------------------------------------------------------*/ -#define RANGE_ID_MSK(range_start, range_end) (~((range_end) - (range_start))) -#define RANGE_ID_ARB(range_start, range_end) ((range_start) & (range_end)) - -#define FIXED_ID_MSK(id) RANGE_ID_MSK((id), (id)) -#define FIXED_ID_ARB(id) RANGE_ID_ARB((id), (id)) - -#define STD_RANGE_ID_MSK(range_start, range_end) ((u16)((RANGE_ID_MSK((range_start), (range_end)) & 0x7FF) << 2)) -#define STD_RANGE_ID_ARB(range_start, range_end) ((u16)(RANGE_ID_ARB((range_start), (range_end)) << 2)) - -#define STD_FIXED_ID_MSK(id) ((u16)((FIXED_ID_MSK(id) & 0x7FF) << 2)) -#define STD_FIXED_ID_ARB(id) ((u16)(FIXED_ID_ARB(id) << 2)) - -#define EXT_RANGE_ID_MSK_L(range_start, range_end) ((u16)(RANGE_ID_MSK((range_start), (range_end)) >> 11)) -#define EXT_RANGE_ID_MSK_H(range_start, range_end) ((u16)(STD_RANGE_ID_MSK((range_start), (range_end)) | ((RANGE_ID_MSK((range_start), (range_end)) >> 27) & 0x03))) -#define EXT_RANGE_ID_ARB_L(range_start, range_end) ((u16)(RANGE_ID_ARB((range_start), (range_end)) >> 11)) -#define EXT_RANGE_ID_ARB_H(range_start, range_end) ((u16)(STD_RANGE_ID_ARB((range_start), (range_end)) | ((RANGE_ID_ARB((range_start), (range_end)) >> 27) & 0x03))) - -#define EXT_FIXED_ID_MSK_L(id) ((u16)(FIXED_ID_MSK(id) >> 11)) -#define EXT_FIXED_ID_MSK_H(id) ((u16)(STD_FIXED_ID_MSK(id) | ((FIXED_ID_MSK(id) >> 27) & 0x03))) -#define EXT_FIXED_ID_ARB_L(id) ((u16)(FIXED_ID_ARB(id) >> 11)) -#define EXT_FIXED_ID_ARB_H(id) ((u16)(STD_FIXED_ID_ARB(id) | ((FIXED_ID_ARB(id) >> 27) & 0x03))) - -/* macro to format the timing register value from the timing parameters*/ -#define CAN_TIMING(tseg1, tseg2, sjw, brp) ((((tseg2-1) & 0x07) << 12) | (((tseg1-1) & 0x0F) << 8) | (((sjw-1) & 0x03) << 6) | ((brp-1) & 0x3F)) - -/* Private variables ---------------------------------------------------------*/ -/* array of pre-defined timing parameters for standard bitrates*/ -u16 CanTimings[] = { /* value bitrate NTQ TSEG1 TSEG2 SJW BRP */ - CAN_TIMING(11, 4, 4, 5), /* 0x3AC4 100 kbit/s 16 11 4 4 5 */ - CAN_TIMING(11, 4, 4, 4), /* 0x3AC3 125 kbit/s 16 11 4 4 4 */ - CAN_TIMING( 4, 3, 3, 4), /* 0x2383 250 kbit/s 8 4 3 3 4 */ - CAN_TIMING(13, 2, 1, 1), /* 0x1C00 500 kbit/s 16 13 2 1 1 */ - CAN_TIMING( 4, 3, 1, 1), /* 0x2300 1 Mbit/s 8 4 3 1 1 */ -}; - -/* Private function prototypes -----------------------------------------------*/ -static u32 GetFreeIF(void); -/* Private functions ---------------------------------------------------------*/ - -/******************************************************************************* -* Function Name : CAN_DeInit -* Description : Deinitializes the CAN peripheral registers to their default -* reset values. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void CAN_DeInit (void) -{ - /* Reset the CAN registers values*/ - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_CAN,ENABLE); - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_CAN,DISABLE); -} - -/******************************************************************************* -* Function Name : CAN_Init -* Description : Initializes the CAN peripheral according to the specified -* parameters in the CAN_InitStruct. -* Input : CAN_InitStruct: pointer to a CAN_InitTypeDef structure that -* contains the configuration information for the CAN peripheral. -* Output : None -* Return : None -*******************************************************************************/ -void CAN_Init(CAN_InitTypeDef* CAN_InitStruct) -{ - CAN_EnterInitMode(CAN_CR_CCE | CAN_InitStruct->CAN_ConfigParameters); - CAN_SetBitrate(CAN_InitStruct->CAN_Bitrate); - CAN_LeaveInitMode(); - CAN_LeaveTestMode(); -} - -/******************************************************************************* -* Function Name : CAN_StructInit -* Description : Fills each CAN_InitStruct member with its reset value. -* Input : CAN_InitStruct : pointer to a CAN_InitTypeDef structure which -* will be initialized. -* Output : None -* Return : None. -*******************************************************************************/ -void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) -{ -/* Reset CAN init structure parameters values */ - CAN_InitStruct->CAN_ConfigParameters = 0x0; - CAN_InitStruct->CAN_Bitrate = 0x2301; -} - -/******************************************************************************* -* Function Name : CAN_SetBitrate -* Description : Setups a standard CAN bitrate. -* Input : bitrate: specifies the bit rate. -* Output : None -* Return : None -*******************************************************************************/ -void CAN_SetBitrate(u32 bitrate) -{ - CAN->BTR = CanTimings[bitrate]; /* write the predefined timing value */ - CAN->BRPR = 0; /* clear the Extended Baud Rate Prescaler */ -} - -/******************************************************************************* -* Function Name : CAN_SetTiming -* Description : Setups the CAN timing with specific parameters -* Input : - tseg1: specifies Time Segment before the sample point. -* This parameter must be a number between 1 and 16. -* - tseg2: Time Segment after the sample point. This parameter -* must be a number between 1 and 8. -* - sjw: Synchronisation Jump Width. This parameter must be -* a number between 1 and 4. -* - brp: Baud Rate Prescaler. This parameter must be a number -* between 1 and 1024. -* Output : None -* Return : None -*******************************************************************************/ -void CAN_SetTiming(u32 tseg1, u32 tseg2, u32 sjw, u32 brp) -{ - CAN->BTR = CAN_TIMING(tseg1, tseg2, sjw, brp); - CAN->BRPR = ((brp-1) >> 6) & 0x0F; -} - -/******************************************************************************* -* Function Name : GetFreeIF -* Description : Searchs the first free message interface, starting from 0. -* Input : None -* Output : None -* Return : A free message interface number (0 or 1) if found, else 2 -*******************************************************************************/ -static u32 GetFreeIF(void) -{ - if ((CAN->sMsgObj[0].CRR & CAN_CRR_BUSY) == 0) - return 0; - else if ((CAN->sMsgObj[1].CRR & CAN_CRR_BUSY) == 0) - return 1; - else - return 2; -} - -/******************************************************************************* -* Function Name : CAN_SetUnusedMsgObj -* Description : Configures the message object as unused -* Input : msgobj: specifies the Message object number, from 0 to 31. -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Interface to treat the message -* - ERROR: No interface found to treat the message -*******************************************************************************/ -ErrorStatus CAN_SetUnusedMsgObj(u32 msgobj) -{ - u32 msg_if=0; - - if ((msg_if = GetFreeIF()) == 2) - { - return ERROR; - } - - CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD - | CAN_CMR_MASK - | CAN_CMR_ARB - | CAN_CMR_CONTROL - | CAN_CMR_DATAA - | CAN_CMR_DATAB; - - CAN->sMsgObj[msg_if].M1R = 0; - CAN->sMsgObj[msg_if].M2R = 0; - - CAN->sMsgObj[msg_if].A1R = 0; - CAN->sMsgObj[msg_if].A2R = 0; - - CAN->sMsgObj[msg_if].MCR = 0; - - CAN->sMsgObj[msg_if].DA1R = 0; - CAN->sMsgObj[msg_if].DA2R = 0; - CAN->sMsgObj[msg_if].DB1R = 0; - CAN->sMsgObj[msg_if].DB2R = 0; - - CAN->sMsgObj[msg_if].CRR = 1 + msgobj; - - return SUCCESS; -} - -/******************************************************************************* -* Function Name : CAN_SetTxMsgObj -* Description : Configures the message object as TX. -* Input : - msgobj: specifies the Message object number, from 0 to 31. -* - idType: specifies the identifier type of the frames that -* will be transmitted using this message object. -* This parameter can be one of the following values: -* - CAN_STD_ID (standard ID, 11-bit) -* - CAN_EXT_ID (extended ID, 29-bit) -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Interface to treat the message -* - ERROR: No interface found to treat the message -*******************************************************************************/ -ErrorStatus CAN_SetTxMsgObj(u32 msgobj, u32 idType) -{ - u32 msg_if=0; - - if ((msg_if = GetFreeIF()) == 2) - { - return ERROR; - } - - CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD - | CAN_CMR_MASK - | CAN_CMR_ARB - | CAN_CMR_CONTROL - | CAN_CMR_DATAA - | CAN_CMR_DATAB; - - CAN->sMsgObj[msg_if].M1R = 0; - CAN->sMsgObj[msg_if].A1R = 0; - - if (idType == CAN_STD_ID) - { - CAN->sMsgObj[msg_if].M2R = CAN_M2R_MDIR; - CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_DIR; - } - else - { - CAN->sMsgObj[msg_if].M2R = CAN_M2R_MDIR | CAN_M2R_MXTD; - CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_DIR | CAN_A2R_XTD; - } - - CAN->sMsgObj[msg_if].MCR = CAN_MCR_TXIE | CAN_MCR_EOB; - - CAN->sMsgObj[msg_if].DA1R = 0; - CAN->sMsgObj[msg_if].DA2R = 0; - CAN->sMsgObj[msg_if].DB1R = 0; - CAN->sMsgObj[msg_if].DB2R = 0; - - CAN->sMsgObj[msg_if].CRR = 1 + msgobj; - - return SUCCESS; -} - -/******************************************************************************* -* Function Name : CAN_SetRxMsgObj -* Description : Configures the message object as RX. -* Input : - msgobj: specifies the Message object number, from 0 to 31. -* - idType: specifies the identifier type of the frames that -* will be transmitted using this message object. -* This parameter can be one of the following values: -* - CAN_STD_ID (standard ID, 11-bit) -* - CAN_EXT_ID (extended ID, 29-bit) -* - idLow: specifies the low part of the identifier range used -* for acceptance filtering. -* - idHigh: specifies the high part of the identifier range -* used for acceptance filtering. -* - singleOrFifoLast: specifies the end-of-buffer indicator. -* This parameter can be one of the following values: -* - TRUE: for a single receive object or a FIFO receive -* object that is the last one of the FIFO. -* - FALSE: for a FIFO receive object that is not the -* last one. -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Interface to treat the message -* - ERROR: No interface found to treat the message -*******************************************************************************/ -ErrorStatus CAN_SetRxMsgObj(u32 msgobj, u32 idType, u32 idLow, u32 idHigh, bool singleOrFifoLast) -{ - u32 msg_if=0; - - if ((msg_if = GetFreeIF()) == 2) - { - return ERROR; - } - - CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD - | CAN_CMR_MASK - | CAN_CMR_ARB - | CAN_CMR_CONTROL - | CAN_CMR_DATAA - | CAN_CMR_DATAB; - - if (idType == CAN_STD_ID) - { - CAN->sMsgObj[msg_if].M1R = 0; - CAN->sMsgObj[msg_if].M2R = STD_RANGE_ID_MSK(idLow, idHigh); - - CAN->sMsgObj[msg_if].A1R = 0; - CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | STD_RANGE_ID_ARB(idLow, idHigh); - } - else - { - CAN->sMsgObj[msg_if].M1R = EXT_RANGE_ID_MSK_L(idLow, idHigh); - CAN->sMsgObj[msg_if].M2R = CAN_M2R_MXTD | EXT_RANGE_ID_MSK_H(idLow, idHigh); - - CAN->sMsgObj[msg_if].A1R = EXT_RANGE_ID_ARB_L(idLow, idHigh); - CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_XTD | EXT_RANGE_ID_ARB_H(idLow, idHigh); - } - - CAN->sMsgObj[msg_if].MCR = CAN_MCR_RXIE | CAN_MCR_UMASK | (singleOrFifoLast ? CAN_MCR_EOB : 0); - - CAN->sMsgObj[msg_if].DA1R = 0; - CAN->sMsgObj[msg_if].DA2R = 0; - CAN->sMsgObj[msg_if].DB1R = 0; - CAN->sMsgObj[msg_if].DB2R = 0; - - CAN->sMsgObj[msg_if].CRR = 1 + msgobj; - - return SUCCESS; -} - -/******************************************************************************* -* Function Name : CAN_InvalidateAllMsgObj -* Description : Configures all the message objects as unused. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void CAN_InvalidateAllMsgObj(void) -{ - u32 i=0; - for (i = 0; i < 32; i++) - CAN_SetUnusedMsgObj(i); -} - - -/******************************************************************************* -* Function Name : CAN_ReleaseMessage -* Description : Releases the message object -* Input : - msgobj: specifies the Message object number, from 0 to 31. -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Interface to treat the message -* - ERROR: No interface found to treat the message -*******************************************************************************/ -ErrorStatus CAN_ReleaseMessage(u32 msgobj) -{ - u32 msg_if=0; - - if ((msg_if = GetFreeIF()) == 2) - { - return ERROR; - } - - CAN->sMsgObj[msg_if].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQSTNEWDAT; - CAN->sMsgObj[msg_if].CRR = 1 + msgobj; - - return SUCCESS; -} - -/******************************************************************************* -* Function Name : CAN_SendMessage -* Description : Start transmission of a message -* Input : - msgobj: specifies the Message object number, from 0 to 31. -* : - pCanMsg: pointer to the message structure containing data -* to transmit. -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Transmission OK -* - ERROR: No transmission -*******************************************************************************/ -ErrorStatus CAN_SendMessage(u32 msgobj, canmsg* pCanMsg) -{ - if (CAN->sMsgObj[0].CRR & CAN_CRR_BUSY) - { - return ERROR; - } - - CAN->SR &= ~CAN_SR_TXOK; - - /* read the Arbitration and Message Control*/ - CAN->sMsgObj[0].CMR = CAN_CMR_ARB | CAN_CMR_CONTROL; - - CAN->sMsgObj[0].CRR = 1 + msgobj; - - if (CAN->sMsgObj[0].CRR & CAN_CRR_BUSY) - { - return ERROR; - } - - /* update the contents needed for transmission*/ - CAN->sMsgObj[0].CMR = CAN_CMR_WRRD - | CAN_CMR_ARB - | CAN_CMR_CONTROL - | CAN_CMR_DATAA - | CAN_CMR_DATAB; - - if ((CAN->sMsgObj[0].A2R & CAN_A2R_XTD) == 0) - { - /* standard ID*/ - CAN->sMsgObj[0].A1R = 0; - CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | STD_FIXED_ID_ARB(pCanMsg->Id); - } - else - { - /* extended ID*/ - CAN->sMsgObj[0].A1R = EXT_FIXED_ID_ARB_L(pCanMsg->Id); - CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | EXT_FIXED_ID_ARB_H(pCanMsg->Id); - } - - CAN->sMsgObj[0].MCR = (CAN->sMsgObj[0].MCR & 0xFEF0) | CAN_MCR_NEWDAT | CAN_MCR_TXRQST | pCanMsg->Dlc; - - CAN->sMsgObj[0].DA1R = ((u16)pCanMsg->Data[1]<<8) | pCanMsg->Data[0]; - CAN->sMsgObj[0].DA2R = ((u16)pCanMsg->Data[3]<<8) | pCanMsg->Data[2]; - CAN->sMsgObj[0].DB1R = ((u16)pCanMsg->Data[5]<<8) | pCanMsg->Data[4]; - CAN->sMsgObj[0].DB2R = ((u16)pCanMsg->Data[7]<<8) | pCanMsg->Data[6]; - - CAN->sMsgObj[0].CRR = 1 + msgobj; - - return SUCCESS; -} - -/******************************************************************************* -* Function Name : CAN_ReceiveMessage -* Description : Gets the message, if received. -* Input : - msgobj: specifies the Message object number, from 0 to 31. -* - release: specifies the message release indicator. -* This parameter can be one of the following values: -* - TRUE: the message object is released when getting -* the data. -* - FALSE: the message object is not released. -* - pCanMsg: pointer to the message structure where received -* data is copied. -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Reception OK -* - ERROR: No message pending -*******************************************************************************/ -ErrorStatus CAN_ReceiveMessage(u32 msgobj, bool release, canmsg* pCanMsg) -{ - if (!CAN_IsMessageWaiting(msgobj)) - { - return ERROR; - } - - CAN->SR &= ~CAN_SR_RXOK; - - /* read the message contents*/ - CAN->sMsgObj[1].CMR = CAN_CMR_MASK - | CAN_CMR_ARB - | CAN_CMR_CONTROL - | CAN_CMR_CLRINTPND - | (release ? CAN_CMR_TXRQSTNEWDAT : 0) - | CAN_CMR_DATAA - | CAN_CMR_DATAB; - - CAN->sMsgObj[1].CRR = 1 + msgobj; - - if (CAN->sMsgObj[1].CRR & CAN_CRR_BUSY) - { - return ERROR; - } - - if ((CAN->sMsgObj[1].A2R & CAN_A2R_XTD) == 0) - { - /* standard ID*/ - pCanMsg->IdType = CAN_STD_ID; - pCanMsg->Id = (CAN->sMsgObj[1].A2R >> 2) & 0x07FF; - } - else - { - /* extended ID*/ - pCanMsg->IdType = CAN_EXT_ID; - pCanMsg->Id = ((CAN->sMsgObj[1].A2R >> 2) & 0x07FF); - pCanMsg->Id |= ((u32)CAN->sMsgObj[1].A1R << 11); - pCanMsg->Id |= (((u32)CAN->sMsgObj[1].A2R & 0x0003) << 27); - } - - pCanMsg->Dlc = CAN->sMsgObj[1].MCR & 0x0F; - - pCanMsg->Data[0] = (u8) CAN->sMsgObj[1].DA1R; - pCanMsg->Data[1] = (u8)(CAN->sMsgObj[1].DA1R >> 8); - pCanMsg->Data[2] = (u8) CAN->sMsgObj[1].DA2R; - pCanMsg->Data[3] = (u8)(CAN->sMsgObj[1].DA2R >> 8); - pCanMsg->Data[4] = (u8) CAN->sMsgObj[1].DB1R; - pCanMsg->Data[5] = (u8)(CAN->sMsgObj[1].DB1R >> 8); - pCanMsg->Data[6] = (u8) CAN->sMsgObj[1].DB2R; - pCanMsg->Data[7] = (u8)(CAN->sMsgObj[1].DB2R >> 8); - - return SUCCESS; -} - -/******************************************************************************* -* Function Name : CAN_WaitEndOfTx -* Description : Waits until current transmission is finished. -* Input : None -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Transmission ended -* - ERROR: Transmission did not occur yet -*******************************************************************************/ -ErrorStatus CAN_WaitEndOfTx(void) -{ - if ((CAN->SR & CAN_SR_TXOK) == 0) - { - return ERROR; - } - CAN->SR &= ~CAN_SR_TXOK; - - return SUCCESS; -} - -/******************************************************************************* -* Function Name : CAN_BasicSendMessage -* Description : Starts transmission of a message in BASIC mode. This mode -* does not use the message RAM. -* Input : pCanMsg: Pointer to the message structure containing data to -* transmit. -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Transmission OK -* - ERROR: No transmission -*******************************************************************************/ -ErrorStatus CAN_BasicSendMessage(canmsg* pCanMsg) -{ - /* clear NewDat bit in IF2 to detect next reception*/ - CAN->sMsgObj[1].MCR &= ~CAN_MCR_NEWDAT; - - CAN->SR &= ~CAN_SR_TXOK; - CAN->sMsgObj[0].CMR = CAN_CMR_WRRD - | CAN_CMR_ARB - | CAN_CMR_CONTROL - | CAN_CMR_DATAA - | CAN_CMR_DATAB; - - if (pCanMsg->IdType == CAN_STD_ID) - { - /* standard ID*/ - CAN->sMsgObj[0].A1R = 0; - CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | STD_FIXED_ID_ARB(pCanMsg->Id); - } - else - { - /* extended ID*/ - CAN->sMsgObj[0].A1R = EXT_FIXED_ID_ARB_L(pCanMsg->Id); - CAN->sMsgObj[0].A2R = ((CAN->sMsgObj[0].A2R) & 0xE000) | EXT_FIXED_ID_ARB_H(pCanMsg->Id); - } - - CAN->sMsgObj[0].MCR = (CAN->sMsgObj[0].MCR & 0xFCF0) | pCanMsg->Dlc; - - CAN->sMsgObj[0].DA1R = ((u16)pCanMsg->Data[1]<<8) | pCanMsg->Data[0]; - CAN->sMsgObj[0].DA2R = ((u16)pCanMsg->Data[3]<<8) | pCanMsg->Data[2]; - CAN->sMsgObj[0].DB1R = ((u16)pCanMsg->Data[5]<<8) | pCanMsg->Data[4]; - CAN->sMsgObj[0].DB2R = ((u16)pCanMsg->Data[7]<<8) | pCanMsg->Data[6]; - - /* request transmission*/ - if (CAN->sMsgObj[0].CRR == CAN_CRR_BUSY ) - { - return ERROR; - } - - return SUCCESS; -} - -/******************************************************************************* -* Function Name : CAN_BasicReceiveMessage -* Description : Gets the message in BASIC mode, if received. This mode does -* not use the message RAM. -* Input : pCanMsg: pointer to the message structure where message is copied. -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Reception OK -* - ERROR: No message pending -*******************************************************************************/ -ErrorStatus CAN_BasicReceiveMessage(canmsg* pCanMsg) -{ - if ((CAN->sMsgObj[1].MCR & CAN_MCR_NEWDAT) == 0) - { - return ERROR; - } - - CAN->SR &= ~CAN_SR_RXOK; - - CAN->sMsgObj[1].CMR = CAN_CMR_ARB - | CAN_CMR_CONTROL - | CAN_CMR_DATAA - | CAN_CMR_DATAB; - - if ((CAN->sMsgObj[1].A2R & CAN_A2R_XTD) == 0) - { - /* standard ID*/ - pCanMsg->IdType = CAN_STD_ID; - pCanMsg->Id = (CAN->sMsgObj[1].A2R >> 2) & 0x07FF; - } - else - { - /* extended ID*/ - pCanMsg->IdType = CAN_EXT_ID; - pCanMsg->Id = ((CAN->sMsgObj[1].A2R >> 2) & 0x07FF); - pCanMsg->Id |= ((u32)CAN->sMsgObj[1].A1R << 11); - pCanMsg->Id |= (((u32)CAN->sMsgObj[1].A2R & 0x0003) << 27); - } - - pCanMsg->Dlc = CAN->sMsgObj[1].MCR & 0x0F; - - pCanMsg->Data[0] = (u8) CAN->sMsgObj[1].DA1R; - pCanMsg->Data[1] = (u8)(CAN->sMsgObj[1].DA1R >> 8); - pCanMsg->Data[2] = (u8) CAN->sMsgObj[1].DA2R; - pCanMsg->Data[3] = (u8)(CAN->sMsgObj[1].DA2R >> 8); - pCanMsg->Data[4] = (u8) CAN->sMsgObj[1].DB1R; - pCanMsg->Data[5] = (u8)(CAN->sMsgObj[1].DB1R >> 8); - pCanMsg->Data[6] = (u8) CAN->sMsgObj[1].DB2R; - pCanMsg->Data[7] = (u8)(CAN->sMsgObj[1].DB2R >> 8); - - return SUCCESS; -} - -/******************************************************************************* -* Function Name : CAN_EnterInitMode -* Description : Switchs the CAN into initialization mode. This function must -* be used in conjunction with CAN_LeaveInitMode(). -* Input : InitMask: specifies the CAN configuration in normal mode. -* Output : None -* Return : None -*******************************************************************************/ -void CAN_EnterInitMode(u8 InitMask) -{ - CAN->CR = InitMask | CAN_CR_INIT; - CAN->SR = 0; /* reset the status*/ -} - -/******************************************************************************* -* Function Name : CAN_LeaveInitMode -* Description : Leaves the initialization mode (switch into normal mode). -* This function must be used in conjunction with CAN_EnterInitMode(). -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void CAN_LeaveInitMode(void) -{ - CAN->CR &= ~(CAN_CR_INIT | CAN_CR_CCE); -} - -/******************************************************************************* -* Function Name : CAN_EnterTestMode -* Description : Switchs the CAN into test mode. This function must be used in -* conjunction with CAN_LeaveTestMode(). -* Input : TestMask: specifies the configuration in test modes. -* Output : None -* Return : None -*******************************************************************************/ -void CAN_EnterTestMode(u8 TestMask) -{ - CAN->CR |= CAN_CR_TEST; - CAN->TESTR |= TestMask; -} - -/******************************************************************************* -* Function Name : CAN_LeaveTestMode -* Description : Leaves the current test mode (switch into normal mode). -* This function must be used in conjunction with CAN_EnterTestMode(). -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void CAN_LeaveTestMode(void) -{ - CAN->CR |= CAN_CR_TEST; - CAN->TESTR &= ~(CAN_TESTR_LBACK | CAN_TESTR_SILENT | CAN_TESTR_BASIC); - CAN->CR &= ~CAN_CR_TEST; -} - -/******************************************************************************* -* Function Name : CAN_ReleaseTxMessage -* Description : Releases the transmit message object. -* Input : - msgobj: specifies the Message object number, from 0 to 31. -* Output : None -* Return : None -*******************************************************************************/ -void CAN_ReleaseTxMessage(u32 msgobj) -{ - CAN->sMsgObj[0].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQSTNEWDAT; - CAN->sMsgObj[0].CRR = 1 + msgobj; -} - -/******************************************************************************* -* Function Name : CAN_ReleaseRxMessage -* Description : Releases the receive message object. -* Input : - msgobj: specifies the Message object number, from 0 to 31. -* Output : None -* Return : None -*******************************************************************************/ -void CAN_ReleaseRxMessage(u32 msgobj) -{ - CAN->sMsgObj[1].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQSTNEWDAT; - CAN->sMsgObj[1].CRR = 1 + msgobj; -} - -/******************************************************************************* -* Function Name : CAN_IsMessageWaiting -* Description : Tests the waiting status of a received message. -* Input : - msgobj: specifies the Message object number, from 0 to 31. -* Output : None -* Return : A non-zero value if the corresponding message object has -* received a message waiting to be copied, else 0. -*******************************************************************************/ -u32 CAN_IsMessageWaiting(u32 msgobj) -{ - return (msgobj < 16 ? CAN->ND1R & (1 << msgobj) : CAN->ND2R & (1 << (msgobj-16))); -} - -/******************************************************************************* -* Function Name : CAN_IsTransmitRequested -* Description : Tests the request status of a transmitted message. -* Input : - msgobj: specifies the Message object number, from 0 to 31. -* Output : None -* Return : A non-zero value if the corresponding message is requested -* to transmit, else 0. -*******************************************************************************/ -u32 CAN_IsTransmitRequested(u32 msgobj) -{ - return (msgobj < 16 ? CAN->TXR1R & (1 << msgobj) : CAN->TXR2R & (1 << (msgobj-16))); -} - -/******************************************************************************* -* Function Name : CAN_IsInterruptPending -* Description : Tests the interrupt status of a message object. -* Input : - msgobj: specifies the Message object number, from 0 to 31. -* Output : None -* Return : A non-zero value if the corresponding message has an -* interrupt pending, else 0. -*******************************************************************************/ -u32 CAN_IsInterruptPending(u32 msgobj) -{ - return (msgobj < 16 ? CAN->IP1R & (1 << msgobj) : CAN->IP2R & (1 << (msgobj-16))); -} - -/******************************************************************************* -* Function Name : CAN_IsObjectValid -* Description : Tests the validity of a message object (ready to use). -* Input : - msgobj: specifies the Message object number, from 0 to 31. -* Output : None -* Return : A non-zero value if the corresponding message object is -* valid, else 0. -*******************************************************************************/ -u32 CAN_IsObjectValid(u32 msgobj) -{ - return (msgobj < 16 ? CAN->MV1R & (1 << msgobj) : CAN->MV2R & (1 << (msgobj-16))); -} -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_cfg.c b/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_cfg.c deleted file mode 100644 index 593e8b84d..000000000 --- a/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_cfg.c +++ /dev/null @@ -1,122 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_cfg.c -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file provides all the CFG software functions. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -#include "75x_cfg.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define CFG_SWBOOT_Mask 0xFFFFFFFC -#define CFG_FLASHBusy_Mask 0x00000080 - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/******************************************************************************* -* Function Name : CFG_BootSpaceConfig -* Description : Selects which memory space will be remapped at address 0x00. -* Input : - CFG_BootSpace: specifies the memory space to be remapped -* at address 0x00. -* This parameter can be one of the following values: -* - CFG_BootSpace_FLASH -* - CFG_BootSpace_SRAM -* - CFG_BootSpace_ExtSMI -* Output : None -* Return : None -*******************************************************************************/ -void CFG_BootSpaceConfig(u32 CFG_BootSpace) -{ - u32 Temp = 0; - - /* Clear SW_BOOT[1:0] bits */ - Temp = CFG->GLCONF & CFG_SWBOOT_Mask; - - /* Set SW_BOOT[1:0] bits according to CFG_BootSpace parameter value */ - Temp |= CFG_BootSpace; - - /* Store the new value */ - CFG->GLCONF = Temp; -} - -/******************************************************************************* -* Function Name : CFG_FLASHBurstConfig -* Description : Enables or disables the FLASH Burst mode. -* Input : - CCFG_FLASHBurst: specifies the new state of the FLASH Burst -* mode. -* This parameter can be one of the following values: -* - CFG_FLASHBurst_Disable -* - CFG_FLASHBurst_Enable -* Output : None -* Return : None -*******************************************************************************/ -void CFG_FLASHBurstConfig(u32 CFG_FLASHBurst) -{ - if(CFG_FLASHBurst == CFG_FLASHBurst_Enable) - { - CFG->GLCONF |= CFG_FLASHBurst_Enable; - } - else - { - CFG->GLCONF &= CFG_FLASHBurst_Disable; - } -} - -/******************************************************************************* -* Function Name : CFG_USBFilterConfig -* Description : Enables or disables the USB Filter. -* Input : - CFG_USBFilter: specifies the new state of the USB Filter. -* This parameter can be one of the following values: -* - CFG_USBFilter_Disable -* - CFG_USBFilter_Enable -* Output : None -* Return : None -*******************************************************************************/ -void CFG_USBFilterConfig(u32 CFG_USBFilter) -{ - if(CFG_USBFilter == CFG_USBFilter_Enable) - { - CFG->GLCONF |= CFG_USBFilter_Enable; - } - else - { - CFG->GLCONF &= CFG_USBFilter_Disable; - } -} - -/******************************************************************************* -* Function Name : CFG_GetFlagStatus -* Description : Checks whether the FLASH Busy flag is set or not. -* Input : None -* Output : None -* Return : The new state of FLASH Busy flag (SET or RESET). -*******************************************************************************/ -FlagStatus CFG_GetFlagStatus(void) -{ - if((CFG->GLCONF & CFG_FLASHBusy_Mask) != RESET) - { - return SET; - } - else - { - return RESET; - } -} - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_dma.c b/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_dma.c deleted file mode 100644 index 7bc09466d..000000000 --- a/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_dma.c +++ /dev/null @@ -1,596 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_dma.c -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file provides all the DMA software functions. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -#include "75x_dma.h" -#include "75x_mrcc.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* DMA enable */ -#define DMA_Enable 0x0001 -#define DMA_Disable 0xFFFE - -/* DMA Last Buffer Sweep */ -#define DMA_Last0_Enable_Mask 0x0001 -#define DMA_Last0_Disable_Mask 0xFFFE -#define DMA_Last1_Enable_Mask 0x0002 -#define DMA_Last1_Disable_Mask 0xFFFD -#define DMA_Last2_Enable_Mask 0x0004 -#define DMA_Last2_Disable_Mask 0xFFFB -#define DMA_Last3_Enable_Mask 0x0008 -#define DMA_Last3_Disable_Mask 0xFFF7 - -/* DMA Masks */ -#define DMA_Stream0_MASK_Mask 0xFFEE -#define DMA_Stream0_CLR_Mask 0x0011 -#define DMA_Stream0_LAST_Mask 0xFFFE - -#define DMA_Stream1_MASK_Mask 0xFFDD -#define DMA_Stream1_CLR_Mask 0x0022 -#define DMA_Stream1_LAST_Mask 0xFFFD - -#define DMA_Stream2_MASK_Mask 0xFFBB -#define DMA_Stream2_CLR_Mask 0x0044 -#define DMA_Stream2_LAST_Mask 0xFFFB - -#define DMA_Stream3_MASK_Mask 0xFF77 -#define DMA_Stream3_CLR_Mask 0x0088 -#define DMA_Stream3_LAST_Mask 0xFFF7 - -#define DMA_SRCSize_Mask 0xFFE7 -#define DMA_SRCBurst_Mask 0xFF9F -#define DMA_DSTSize_Mask 0xFE7F - -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/******************************************************************************* -* Function Name : DMA_DeInit -* Description : Deinitializes the DMA streamx registers to their default reset -* values. -* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA -* Stream. -* Output : None -* Return : None -*******************************************************************************/ -void DMA_DeInit(DMA_Stream_TypeDef* DMA_Streamx) -{ - /* Reset streamx source base address register */ - DMA_Streamx->SOURCEL = 0; - DMA_Streamx->SOURCEH = 0; - - /* Reset streamx destination base address register */ - DMA_Streamx->DESTL = 0; - DMA_Streamx->DESTH = 0; - - /* Reset streamx maximum count register */ - DMA_Streamx->MAX = 0; - /* Reset streamx control register */ - DMA_Streamx->CTRL = 0; - /* Reset streamx last used buffer location register */ - DMA_Streamx->LUBUFF = 0; - - switch(*(u32*)&DMA_Streamx) - { - case DMA_Stream0_BASE: - /* Reset interrupt mask, clear and flag bits for stream0 */ - DMA->MASK &= DMA_Stream0_MASK_Mask; - DMA->CLR |= DMA_Stream0_CLR_Mask; - DMA->LAST &= DMA_Stream0_LAST_Mask; - break; - - case DMA_Stream1_BASE: - /* Reset interrupt mask, clear and flag bits for stream1 */ - DMA->MASK &= DMA_Stream1_MASK_Mask; - DMA->CLR |= DMA_Stream1_CLR_Mask; - DMA->LAST &= DMA_Stream1_LAST_Mask; - break; - - case DMA_Stream2_BASE: - /* Reset interrupt mask, clear and flag bits for stream2 */ - DMA->MASK &= DMA_Stream2_MASK_Mask; - DMA->CLR |= DMA_Stream2_CLR_Mask; - DMA->LAST &= DMA_Stream2_LAST_Mask; - break; - - case DMA_Stream3_BASE: - /* Reset interrupt mask, clear and flag bits for stream3 */ - DMA->MASK &= DMA_Stream3_MASK_Mask; - DMA->CLR |= DMA_Stream3_CLR_Mask; - DMA->LAST &= DMA_Stream3_LAST_Mask; - break; - - default: - break; - } -} - -/******************************************************************************* -* Function Name : DMA_Init -* Description : Initializes the DMAx stream according to the specified -* parameters in the DMA_InitStruct. -* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA -* Stream. -* - DMA_InitStruct: pointer to a DMA_InitTypeDef structure that -* contains the configuration information for the specified -* DMA stream. -* Output : None -* Return : None -******************************************************************************/ -void DMA_Init(DMA_Stream_TypeDef* DMA_Streamx, DMA_InitTypeDef* DMA_InitStruct) -{ - /* set the buffer Size */ - DMA_Streamx->MAX = DMA_InitStruct->DMA_BufferSize ; - - /* Configure the incrementation of the current source Register */ - if(DMA_InitStruct->DMA_SRC == DMA_SRC_INCR) - { - /* Increment current source register */ - DMA_Streamx->CTRL |= DMA_SRC_INCR; - } - else - { - /* Current source register unchanged */ - DMA_Streamx->CTRL &= DMA_SRC_NOT_INCR; - } - - /* Configure the incrementation of the current destination Register */ - if(DMA_InitStruct->DMA_DST == DMA_DST_INCR) - { - /* Increment current source register */ - DMA_Streamx->CTRL |= DMA_DST_INCR; - } - else - { - /* Current source register unchanged */ - DMA_Streamx->CTRL &= DMA_DST_NOT_INCR; - } - - /* Clear source to DMA data width SOSIZE[1:0] bits */ - DMA_Streamx->CTRL &= DMA_SRCSize_Mask; - /* Set the source to DMA data width */ - DMA_Streamx->CTRL |= DMA_InitStruct->DMA_SRCSize; - - /* Clear the DMA peripheral burst size SOBURST[1:0] bits */ - DMA_Streamx->CTRL &= DMA_SRCBurst_Mask; - /* Set the DMA peripheral burst size */ - DMA_Streamx->CTRL |= DMA_InitStruct->DMA_SRCBurst; - - /* Clear destination to DMA dat width DESIZE[1:0] bits */ - DMA_Streamx->CTRL &= DMA_DSTSize_Mask; - /* Set the destination to DMA data width */ - DMA_Streamx->CTRL |= DMA_InitStruct->DMA_DSTSize; - - /* Configure the circular mode */ - if(DMA_InitStruct->DMA_Mode == DMA_Mode_Circular) - { - /* Set circular mode */ - DMA_Streamx->CTRL |= DMA_Mode_Circular; - } - else - { - /* Set normal mode */ - DMA_Streamx->CTRL &= DMA_Mode_Normal; - } - - /* Configure the direction transfer */ - if(DMA_InitStruct->DMA_DIR == DMA_DIR_PeriphDST) - { - /* Set peripheral as destination */ - DMA_Streamx->CTRL |= DMA_DIR_PeriphDST; - } - else - { - /* Set peripheral as source */ - DMA_Streamx->CTRL &= DMA_DIR_PeriphSRC; - } - - /* Configure the memory to memory transfer only for stream3 */ - if(DMA_Streamx == DMA_Stream3) - { - if(DMA_InitStruct->DMA_M2M == DMA_M2M_Enable) - { - /* Enable memory to memory transfer for stream3 */ - DMA_Streamx->CTRL |= DMA_M2M_Enable; - } - else - { - /* Disable memory to memory transfer for stream3 */ - DMA_Streamx->CTRL &= DMA_M2M_Disable; - } - } - - /* Configure the source base address */ - DMA_Streamx->SOURCEL = DMA_InitStruct->DMA_SRCBaseAddr; - DMA_Streamx->SOURCEH = DMA_InitStruct->DMA_SRCBaseAddr >> 16; - - /* Configure the destination base address */ - DMA_Streamx->DESTL = DMA_InitStruct->DMA_DSTBaseAddr; - DMA_Streamx->DESTH = DMA_InitStruct->DMA_DSTBaseAddr >> 16; -} - -/******************************************************************************* -* Function Name : DMA_StructInit -* Description : Fills each DMA_InitStruct member with its default value. -* Input : DMA_InitStruct : pointer to a DMA_InitTypeDef structure -* which will be initialized. -* Output : None -* Return : None -*******************************************************************************/ -void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) -{ - /* Initialize the DMA_BufferSize member */ - DMA_InitStruct->DMA_BufferSize = 0; - - /* initialize the DMA_SRCBaseAddr member */ - DMA_InitStruct->DMA_SRCBaseAddr = 0; - - /* Initialize the DMA_DSTBaseAddr member */ - DMA_InitStruct ->DMA_DSTBaseAddr = 0; - - /* Initialize the DMA_SRC member */ - DMA_InitStruct->DMA_SRC = DMA_SRC_NOT_INCR; - - /* Initialize the DMA_DST member */ - DMA_InitStruct->DMA_DST = DMA_DST_NOT_INCR; - - /* Initialize the DMA_SRCSize member */ - DMA_InitStruct->DMA_SRCSize = DMA_SRCSize_Byte; - - /* Initialize the DMA_SRCBurst member */ - DMA_InitStruct->DMA_SRCBurst = DMA_SRCBurst_1Data; - - /* Initialize the DMA_DSTSize member */ - DMA_InitStruct->DMA_DSTSize = DMA_DSTSize_Byte; - - /* Initialize the DMA_Mode member */ - DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; - - /* Initialize the DMA_M2M member */ - DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; - - /* Initialize the DMA_DIR member */ - DMA_InitStruct->DMA_DIR = DMA_DIR_PeriphSRC; -} - -/******************************************************************************* -* Function Name : DMA_Cmd -* Description : Enables or disables the specified DMA stream. -* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA -* Stream. -* - NewState: new state of the DMAx stream. This parameter can -* be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void DMA_Cmd(DMA_Stream_TypeDef* DMA_Streamx, FunctionalState NewState) -{ - if(NewState == ENABLE) - { - /* Enable the selected DMA streamx */ - DMA_Streamx->CTRL |= DMA_Enable; - } - else - { - /* Disable the selected DMA streamx */ - DMA_Streamx->CTRL &= DMA_Disable; - } -} - -/******************************************************************************* -* Function Name : DMA_ITConfig -* Description : Enables or disables the specified DMA interrupts. -* Input : - DMA_IT: specifies the DMA interrupts sources to be enabled -* or disabled. This parameter can be any combination of the -* following values: -* - DMA_IT_SI0: Stream0 transfer end interrupt mask -* - DMA_IT_SI1: Stream1 transfer end interrupt mask -* - DMA_IT_SI2: Stream2 transfer end interrupt mask -* - DMA_IT_SI3: Stream3 transfer end interrupt mask -* - DMA_IT_SE0: Stream0 transfer error interrupt mask -* - DMA_IT_SE1: Stream1 transfer error interrupt mask -* - DMA_IT_SE2: Stream2 transfer error interrupt mask -* - DMA_IT_SE3: Stream3 transfer error interrupt mask -* - DMA_IT_ALL: ALL DMA interrupts mask -* - NewState: new state of the specified DMA interrupts. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void DMA_ITConfig(u16 DMA_IT, FunctionalState NewState) -{ - if(NewState == ENABLE) - { - /* Enable the selected DMA interrupts */ - DMA->MASK |= DMA_IT; - } - else - { - /* Disable the selected DMA interrupts */ - DMA->MASK &= ~DMA_IT; - } -} - -/******************************************************************************* -* Function Name : DMA_GetCurrDSTAddr -* Description : Returns the current value of the destination address pointer -* related to the specified DMA stream. -* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA -* Stream. -* Output : None -* Return : The current value of the destination address pointer related -* to the specified DMA stream. -*******************************************************************************/ -u32 DMA_GetCurrDSTAddr(DMA_Stream_TypeDef* DMA_Streamx) -{ - u32 Tmp = 0; - - /* Get high current destination address */ - Tmp = (DMA_Streamx->DECURRH)<<16; - /* Get low current destination address */ - Tmp |= DMA_Streamx->DECURRL; - - /* Return the current destination address value for streamx */ - return Tmp; -} - -/******************************************************************************* -* Function Name : DMA_GetCurrSRCAddr -* Description : Returns the current value of the source address pointer -* related to the specified DMA stream. -* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA -* Stream. -* Output : None -* Return : The current value of the source address pointer related to -* the specified DMA stream. -*******************************************************************************/ -u32 DMA_GetCurrSRCAddr(DMA_Stream_TypeDef* DMA_Streamx) -{ - u32 Tmp = 0; - - /* Get high current source address */ - Tmp = (DMA_Streamx->SOCURRH)<<16; - /* Get slow current source address */ - Tmp |= DMA_Streamx->SOCURRL; - - /* Return the current source address value for streamx */ - return Tmp; -} - -/******************************************************************************* -* Function Name : DMA_GetTerminalCounter -* Description : Returns the number of data units remaining in the current -* DMA stream transfer. -* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA -* Stream. -* Output : None -* Return : The number of data units remaining in the current DMA stream -* transfer. -*******************************************************************************/ -u16 DMA_GetTerminalCounter(DMA_Stream_TypeDef* DMA_Streamx) -{ - /* Return the terminal counter value for streamx */ - return(DMA_Streamx->TCNT); -} - -/******************************************************************************* -* Function Name : DMA_LastBufferSweepConfig -* Description : Activates or disactivates the last buffer sweep mode for the -* DMA streamx configured in circular buffer mode. -* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA -* Stream. -* - NewState: new state of the Last buffer sweep DMA_Streamx. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void DMA_LastBufferSweepConfig(DMA_Stream_TypeDef* DMA_Streamx, FunctionalState NewState) -{ - switch(*(u32*)&DMA_Streamx) - { - case DMA_Stream0_BASE: - if(NewState == ENABLE) - { - /* Activates the last circular buffer sweep mode for stream0 */ - DMA->LAST |= DMA_Last0_Enable_Mask; - } - else - { - /* Disactivates the last circular buffer sweep mode for stream0 */ - DMA->LAST &= DMA_Last0_Disable_Mask; - } - break; - - case DMA_Stream1_BASE: - if(NewState == ENABLE) - { - /* Activates the last circular buffer sweep mode for stream1 */ - DMA->LAST |= DMA_Last1_Enable_Mask; - } - else - { - /* Disactivates the last circular buffer sweep mode for stream1 */ - DMA->LAST &= DMA_Last1_Disable_Mask; - } - break; - - case DMA_Stream2_BASE: - if(NewState == ENABLE) - { - /* Activates the last circular buffer sweep mode for stream2 */ - DMA->LAST |= DMA_Last2_Enable_Mask; - } - else - { - /* Disactivates the last circular buffer sweep mode for stream2 */ - DMA->LAST &= DMA_Last2_Disable_Mask; - } - break; - - case DMA_Stream3_BASE: - if(NewState == ENABLE) - { - /* Activates the last circular buffer sweep mode for stream3 */ - DMA->LAST |= DMA_Last3_Enable_Mask; - } - else - { - /* Disactivates the last circular buffer sweep mode for stream3 */ - DMA->LAST &= DMA_Last3_Disable_Mask; - } - break; - - default: - break; - } -} - -/******************************************************************************* -* Function Name : DMA_LastBufferAddrConfig -* Description : Configures the circular buffer position where the last data -* to be used by the specified DMA stream is located. -* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA -* Stream. -* - DMA_LastBufferAddr: specifies the circular buffer position -* where the last data to be used by the specified DMA stream -* is located. -* This member must be a number between 0 and the stream BufferSize-1. -* Output : None -* Return : None -*******************************************************************************/ -void DMA_LastBufferAddrConfig(DMA_Stream_TypeDef* DMA_Streamx, u16 DMA_LastBufferAddr) -{ - /* Set the streamx last data circular buffer location */ - DMA_Streamx->LUBUFF = DMA_LastBufferAddr; -} - -/******************************************************************************* -* Function Name : DMA_GetFlagStatus -* Description : Checks whether the specified DMA flag is set or not. -* Input : - DMA_FLAG: specifies the flag to check. This parameter can -* be one of the following values: -* - DMA_FLAG_SI0: Stream0 transfer end flag. -* - DMA_FLAG_SI1: Stream1 transfer end flag. -* - DMA_FLAG_SI2: Stream2 transfer end flag. -* - DMA_FLAG_SI3: Stream3 transfer end flag. -* - DMA_FLAG_SE0: Stream0 transfer error flag. -* - DMA_FLAG_SE1: Stream1 transfer error flag. -* - DMA_FLAG_SE2: Stream2 transfer error flag. -* - DMA_FLAG_SE3: Stream3 transfer error flag. -* - DMA_FLAG_ACT0: Stream0 status. -* - DMA_FLAG_ACT1: Stream1 status. -* - DMA_FLAG_ACT2: Stream2 status. -* - DMA_FLAG_ACT3: Stream3 status. -* Output : None -* Return : The new state of DMA_FLAG (SET or RESET). -*******************************************************************************/ -FlagStatus DMA_GetFlagStatus(u16 DMA_FLAG) -{ - /* Check the status of the specified DMA flag */ - if((DMA->STATUS & DMA_FLAG) != RESET) - { - /* Return SET if DMA_FLAG is set */ - return SET; - } - else - { - /* Return RESET if DMA_FLAG is reset */ - return RESET; - } -} - -/******************************************************************************* -* Function Name : DMA_ClearFlag -* Description : Clears the DMA’s pending flags. -* Input : - DMA_FLAG: specifies the flag to clear. This parameter can -* be any combination of the following values: -* - DMA_FLAG_SI0: Stream0 transfer end flag. -* - DMA_FLAG_SI1: Stream1 transfer end flag. -* - DMA_FLAG_SI2: Stream2 transfer end flag. -* - DMA_FLAG_SI3: Stream3 transfer end flag. -* - DMA_FLAG_SE0: Stream0 transfer error flag. -* - DMA_FLAG_SE1: Stream1 transfer error flag. -* - DMA_FLAG_SE2: Stream2 transfer error flag. -* - DMA_FLAG_SE3: Stream3 transfer error flag. -* Output : None -* Return : None -*******************************************************************************/ -void DMA_ClearFlag(u16 DMA_FLAG) -{ - /* Clear the selected DMA flags */ - DMA->CLR = DMA_FLAG ; -} - -/******************************************************************************* -* Function Name : DMA_GetITStatus -* Description : Checks whether the specified DMA interrupt has occured or not. -* Input : - DMA_IT: specifies the DMA interrupt source to check. -* This parameter can be one of the following values: -* - DMA_IT_SI0: Stream0 transfer end interrupt -* - DMA_IT_SI1: Stream1 transfer end interrupt -* - DMA_IT_SI2: Stream2 transfer end interrupt -* - DMA_IT_SI3: Stream3 transfer end interrupt -* - DMA_IT_SE0: Stream0 transfer error interrupt -* - DMA_IT_SE1: Stream1 transfer error interrupt -* - DMA_IT_SE2: Stream2 transfer error interrupt -* - DMA_IT_SE3: Stream3 transfer error interrupt -* Output : None -* Return : The new state of DMA_IT (SET or RESET). -*******************************************************************************/ -ITStatus DMA_GetITStatus(u16 DMA_IT) -{ - /* Check the status of the specified DMA interrupt */ - if((DMA->STATUS & DMA_IT) != RESET) - { - /* Return SET if the DMA interrupt flag is set */ - return SET; - } - else - { - /* Return RESET if the DMA interrupt flag is reset */ - return RESET; - } -} - -/******************************************************************************* -* Function Name : DMA_ClearITPendingBit -* Description : Clears the DMA’s interrupt pending bits. -* Input : - DMA_IT: specifies the interrupt pending bit to clear. -* This parameter can be any combination of the following values: -* - DMA_IT_SI0: Stream0 transfer end interrupt. -* - DMA_IT_SI1: Stream1 transfer end interrupt. -* - DMA_IT_SI2: Stream2 transfer end interrupt. -* - DMA_IT_SI3: Stream3 transfer end interrupt. -* - DMA_IT_SE0: Stream0 transfer error interrupt. -* - DMA_IT_SE1: Stream1 transfer error interrupt. -* - DMA_IT_SE2: Stream2 transfer error interrupt. -* - DMA_IT_SE3: Stream3 transfer error interrupt. -* - DMA_IT_ALL: All DMA interrupts. -* Output : None -* Return : None -*******************************************************************************/ -void DMA_ClearITPendingBit(u16 DMA_IT) -{ - /* Clear the selected DMA interrupts pending bits */ - DMA->CLR = DMA_IT ; -} - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_eic.c b/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_eic.c deleted file mode 100644 index ca9ead80f..000000000 --- a/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_eic.c +++ /dev/null @@ -1,258 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_eic.c -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file provides all the EIC software functions. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -#include "75x_eic.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define EIC_IRQEnable_Mask 0x00000001 -#define EIC_IRQDisable_Mask 0xFFFFFFFE - -#define EIC_FIQEnable_Mask 0x00000002 -#define EIC_FIQDisable_Mask 0xFFFFFFFD - -#define EIC_SIPL_Mask 0x0000000F -#define EIC_SIPL_Reset_Mask 0xFFFFFFF0 - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/******************************************************************************* -* Function Name : EIC_DeInit -* Description : Deinitializes the EIC peripheral registers to their default -* reset values. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void EIC_DeInit(void) -{ - EIC->ICR = 0x00; - EIC->CIPR = 0x00; - EIC->FIR = 0x0C; - EIC->IER = 0x00; - EIC->IPR = 0xFFFFFFFF; -} - -/******************************************************************************* -* Function Name : EIC_IRQInit -* Description : Configures the IRQ channels according to the specified -* parameters in the EIC_IRQInitStruct. -* Input : EIC_IRQInitStruct: pointer to a EIC_IRQInitTypeDef structure. -* Output : None -* Return : None -*******************************************************************************/ -void EIC_IRQInit(EIC_IRQInitTypeDef* EIC_IRQInitStruct) -{ - u32 Tmp = 0; - - if(EIC_IRQInitStruct->EIC_IRQChannelCmd == ENABLE) - { - /* Enable the selected IRQ channel */ - EIC->IER |= 1 << EIC_IRQInitStruct->EIC_IRQChannel; - - /* Configure the selected IRQ channel priority ***************************/ - /* Clear SIPL[3:0] bits */ - EIC->SIRn[EIC_IRQInitStruct->EIC_IRQChannel] &= EIC_SIPL_Reset_Mask; - - /* Configure SIPL[3:0] bits according to EIC_IRQChannelPriority parameter */ - Tmp = EIC_IRQInitStruct->EIC_IRQChannelPriority & EIC_SIPL_Mask; - EIC->SIRn[EIC_IRQInitStruct->EIC_IRQChannel] |= Tmp; - } - else - { - /* Disable the select IRQ channel */ - EIC->IER &=~ (1 << EIC_IRQInitStruct->EIC_IRQChannel); - } -} - -/******************************************************************************* -* Function Name : EIC_FIQInit -* Description : Configures the FIQ channels according to the specified -* parameters in the EIC_FIQInitStruct. -* Input : EIC_FIQInitStruct: pointer to a EIC_FIQInitTypeDef structure. -* Output : None -* Return : None -*******************************************************************************/ -void EIC_FIQInit(EIC_FIQInitTypeDef* EIC_FIQInitStruct) -{ - if(EIC_FIQInitStruct->EIC_FIQChannelCmd == ENABLE) - { - /* Enable the selected FIQ channel */ - EIC->FIER |= EIC_FIQInitStruct->EIC_FIQChannel ; - } - else - { - /* Disable the selected FIQ channel */ - EIC->FIER &= ~EIC_FIQInitStruct->EIC_FIQChannel; - } -} - -/******************************************************************************* -* Function Name : EIC_IRQStructInit -* Description : Fills each EIC_IRQInitStruct member with its default value. -* Input : EIC_IRQInitStruct: pointer to a EIC_IRQInitTypeDef structure -* which will be initialized. -* Output : None -* Return : None -*******************************************************************************/ -void EIC_IRQStructInit(EIC_IRQInitTypeDef* EIC_IRQInitStruct) -{ - EIC_IRQInitStruct->EIC_IRQChannel = 0x1F; - EIC_IRQInitStruct->EIC_IRQChannelPriority = 0; - EIC_IRQInitStruct->EIC_IRQChannelCmd = DISABLE; -} - -/******************************************************************************* -* Function Name : EIC_FIQStructInit -* Description : Fills each EIC_FIQInitStruct member with its default value. -* Input : EIC_FIQInitStruct: pointer to a EIC_FIQInitTypeDef structure -* which will be initialized. -* Output : None -* Return : None -*******************************************************************************/ -void EIC_FIQStructInit(EIC_FIQInitTypeDef* EIC_FIQInitStruct) -{ - EIC_FIQInitStruct->EIC_FIQChannel = 0x03; - EIC_FIQInitStruct->EIC_FIQChannelCmd = DISABLE; -} - -/******************************************************************************* -* Function Name : EIC_IRQCmd -* Description : Enables or disables EIC IRQ output request to CPU. -* Input : NewState: new state of the EIC IRQ output request to CPU. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void EIC_IRQCmd(FunctionalState NewState) -{ - if(NewState == ENABLE) - { - /* Enable EIC IRQ output request to CPU */ - EIC->ICR |= EIC_IRQEnable_Mask; - } - else - { - /* Disable EIC IRQ output request to CPU */ - EIC->ICR &= EIC_IRQDisable_Mask; - } -} - -/******************************************************************************* -* Function Name : EIC_FIQCmd -* Description : Enables or disables EIC FIQ output request to CPU. -* Input : NewState: new state of the EIC FIQ output request to CPU. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void EIC_FIQCmd(FunctionalState NewState) -{ - if(NewState == ENABLE) - { - /* Enable EIC FIQ output request to CPU */ - EIC->ICR |= EIC_FIQEnable_Mask; - } - else - { - /* Disable EIC FIQ output request to CPU */ - EIC->ICR &= EIC_FIQDisable_Mask; - } -} - -/******************************************************************************* -* Function Name : EIC_GetCurrentIRQChannel -* Description : Returns the current served IRQ channel identifier. -* Input : None -* Output : None -* Return : The current served IRQ channel. -*******************************************************************************/ -u8 EIC_GetCurrentIRQChannel(void) -{ - /* Read and return the CIC[4:0] bits of CICR register */ - return ((u8) (EIC->CICR)); -} - -/******************************************************************************* -* Function Name : EIC_GetCurrentIRQChannelPriority -* Description : Returns the priority level of the current served IRQ channel. -* Input : None -* Output : None -* Return : The priority level of the current served IRQ channel. -*******************************************************************************/ -u8 EIC_GetCurrentIRQChannelPriority(void) -{ - /* Read and return the CIP[3:0] bits of CIPR register */ - return ((u8) (EIC->CIPR)); -} - -/******************************************************************************* -* Function Name : EIC_CurrentIRQPriorityConfig -* Description : Changes the priority of the current served IRQ channel. -* The new priority value must be higher, or equal, than the -* priority value associated to the interrupt channel currently -* serviced. -* Input : NewPriority: new priority value of the IRQ interrupt routine -* currently serviced. -* Output : None -* Return : None -*******************************************************************************/ -void EIC_CurrentIRQPriorityConfig(u8 NewPriority) -{ - /* Disable EIC IRQ output request to CPU */ - EIC->ICR &= EIC_IRQDisable_Mask; - - /* Change the current priority */ - EIC->CIPR = NewPriority; - - /* Enable EIC IRQ output request to CPU */ - EIC->ICR |= EIC_IRQEnable_Mask; -} - -/******************************************************************************* -* Function Name : EIC_GetCurrentFIQChannel -* Description : Returns the current served FIQ channel identifier. -* Input : None -* Output : None -* Return : The current served FIQ channel. -*******************************************************************************/ -u8 EIC_GetCurrentFIQChannel(void) -{ - /* Read and return the FIP[1:0] bits of FIPR register */ - return ((u8) (EIC->FIPR)); -} - -/******************************************************************************* -* Function Name : EIC_ClearFIQPendingBit -* Description : Clears the pending bit of the selected FIQ Channel. -* Input : EIC_FIQChannel: specifies the FIQ channel to clear its -* pending bit. -* Output : None -* Return : None -*******************************************************************************/ -void EIC_ClearFIQPendingBit(u8 EIC_FIQChannel) -{ - /* Clear the correspondent FIQ pending bit */ - EIC->FIPR = EIC_FIQChannel ; -} - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_extit.c b/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_extit.c deleted file mode 100644 index 997cb24f2..000000000 --- a/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_extit.c +++ /dev/null @@ -1,179 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_extit.c -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file provides all the EXTIT software functions. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -#include "75x_extit.h" -#include "75x_mrcc.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/******************************************************************************* -* Function Name : EXTIT_DeInit -* Description : Deinitializes the EXTIT peripheral registers to their default -* reset values. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void EXTIT_DeInit(void) -{ - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_EXTIT,ENABLE); - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_EXTIT,DISABLE); -} - -/******************************************************************************* -* Function Name : EXTIT_Init -* Description : Initializes the EXTIT peripheral according to the specified -* parameters in the EXTIT_InitStruct . -* Input : - EXTIT_InitStruct: pointer to a EXTIT_InitTypeDef structure -* that contains the configuration information for the EXTIT -* peripheral. -* Output : None -* Return : None -*******************************************************************************/ -void EXTIT_Init(EXTIT_InitTypeDef* EXTIT_InitStruct) -{ - if(EXTIT_InitStruct->EXTIT_ITLineCmd == ENABLE) - { - /* Enable the selected external interrupts */ - EXTIT->MR |= EXTIT_InitStruct->EXTIT_ITLine; - - /* Select the trigger for the selected external interrupts */ - if(EXTIT_InitStruct->EXTIT_ITTrigger == EXTIT_ITTrigger_Falling) - { - /* Falling edge */ - EXTIT->TSR &= ~EXTIT_InitStruct->EXTIT_ITLine; - } - else if (EXTIT_InitStruct->EXTIT_ITTrigger == EXTIT_ITTrigger_Rising) - { - /* Rising edge */ - EXTIT->TSR |= EXTIT_InitStruct->EXTIT_ITLine; - } - } - else if(EXTIT_InitStruct->EXTIT_ITLineCmd == DISABLE) - { - /* Disable the selected external interrupts */ - EXTIT->MR &= ~EXTIT_InitStruct->EXTIT_ITLine; - } -} - -/******************************************************************************* -* Function Name : EXTIT_StructInit -* Description : Fills each EXTIT_InitStruct member with its reset value. -* Input : - EXTIT_InitStruct: pointer to a EXTIT_InitTypeDef structure -* which will be initialized. -* Output : None -* Return : None -*******************************************************************************/ -void EXTIT_StructInit(EXTIT_InitTypeDef* EXTIT_InitStruct) -{ - EXTIT_InitStruct->EXTIT_ITLine = EXTIT_ITLineNone; - EXTIT_InitStruct->EXTIT_ITTrigger = EXTIT_ITTrigger_Falling; - EXTIT_InitStruct->EXTIT_ITLineCmd = DISABLE; -} - -/******************************************************************************* -* Function Name : EXTIT_GenerateSWInterrupt -* Description : Generates a Software interrupt. -* Input : - EXTIT_ITLine: specifies the EXTIT lines to be enabled or -* disabled. This parameter can be: -* - EXTIT_ITLinex: External interrupt line x where x(0..15) -* Output : None -* Return : None -*******************************************************************************/ -void EXTIT_GenerateSWInterrupt(u16 EXTIT_ITLine) -{ - EXTIT->SWIR |= EXTIT_ITLine; -} - -/******************************************************************************* -* Function Name : EXTIT_GetFlagStatus -* Description : Checks whether the specified EXTIT line flag is set or not. -* Input : - EXTIT_ITLine: specifies the EXTIT lines flag to check. -* This parameter can be: -* - EXTIT_ITLinex: External interrupt line x where x(0..15) -* Output : None -* Return : The new state of EXTIT_ITLine (SET or RESET). -*******************************************************************************/ -FlagStatus EXTIT_GetFlagStatus(u16 EXTIT_ITLine) -{ - if((EXTIT->PR & EXTIT_ITLine) != RESET) - { - return SET; - } - else - { - return RESET; - } -} - -/******************************************************************************* -* Function Name : EXTIT_ClearFlag -* Description : Clears the EXTIT’s line pending flags. -* Input : - EXTIT_ITLine: specifies the EXTIT lines flags to clear. -* This parameter can be: -* - EXTIT_ITLinex: External interrupt line x where x(0..15) -* Output : None -* Return : None -*******************************************************************************/ -void EXTIT_ClearFlag(u16 EXTIT_ITLine) -{ - EXTIT->PR = EXTIT_ITLine; -} - -/******************************************************************************* -* Function Name : EXTIT_GetITStatus -* Description : Checks whether the specified EXTIT line is asserted or not. -* Input : - EXTIT_ITLine: specifies the EXTIT lines to check. -* This parameter can be: -* - EXTIT_ITLinex: External interrupt line x where x(0..15) -* Output : None -* Return : The new state of EXTIT_ITLine (SET or RESET). -*******************************************************************************/ -ITStatus EXTIT_GetITStatus(u16 EXTIT_ITLine) -{ - if(((EXTIT->PR & EXTIT_ITLine) != RESET)&& ((EXTIT->MR & EXTIT_ITLine) != RESET)) - { - return SET; - } - else - { - return RESET; - } -} - -/******************************************************************************* -* Function Name : EXTIT_ClearITPendingBit -* Description : Clears the EXTIT’s line pending bits. -* Input : - EXTIT_ITLine: specifies the EXTIT lines to clear. -* This parameter can be: -* - EXTIT_ITLinex: External interrupt line x where x(0..15) -* Output : None -* Return : None -*******************************************************************************/ -void EXTIT_ClearITPendingBit(u16 EXTIT_ITLine) -{ - EXTIT->PR = EXTIT_ITLine; -} - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_gpio.c b/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_gpio.c deleted file mode 100644 index dcc7d7920..000000000 --- a/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_gpio.c +++ /dev/null @@ -1,320 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_gpio.c -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file provides all the GPIO software functions. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -#include "75x_gpio.h" -#include "75x_mrcc.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define GPIO_Remap_Mask 0x1F /* GPIO remapping mask */ -#define GPIO_Pin_Mask 0x000FFFFF /* GPIO1 and GPIO2 all pins mask */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/******************************************************************************* -* Function Name : GPIO_DeInit -* Description : Deinitializes the GPIOx peripheral registers to their default -* reset values. -* The I/O remapping register 0 and 1 are not reset by this function. -* Input : GPIOx: where x can be 0,1 or 2 to select the GPIO peripheral. -* Output : None -* Return : None -*******************************************************************************/ -void GPIO_DeInit(GPIO_TypeDef* GPIOx) -{ - /* Reset the GPIOx registers values */ - GPIOx->PC0 = 0xFFFFFFFF; - GPIOx->PC1 = 0x0; - GPIOx->PC2 = 0x0; - GPIOx->PM = 0x0; -} - -/******************************************************************************* -* Function Name : GPIO_Init -* Description : Initializes the GPIOx peripheral according to the specified -* parameters in the GPIO_InitStruct. This function will not -* change the configuration for a pin if the corresponding mask -* bit is set, except pins configured as input pull-up or pull-down. -* These pins are automatically masked after each configuration. -* Input :- GPIOx: where x can be (0..2) to select the GPIO peripheral. -* - GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that -* contains the configuration information for the specified GPIO -* peripheral. -* Output : None -* Return : None -*******************************************************************************/ -void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) -{ - /* GPIOx Mode and Pins Set */ - if((GPIOx != GPIO0) && (GPIO_InitStruct->GPIO_Pin == GPIO_Pin_All)) - { - GPIO_InitStruct->GPIO_Pin = GPIO_Pin_Mask; - } - - switch(GPIO_InitStruct->GPIO_Mode) - { - case GPIO_Mode_AIN: - GPIOx->PC0 &= ~GPIO_InitStruct->GPIO_Pin; - GPIOx->PC1 &= ~GPIO_InitStruct->GPIO_Pin; - GPIOx->PC2 &= ~GPIO_InitStruct->GPIO_Pin; - break; - - case GPIO_Mode_IN_FLOATING: - GPIOx->PC0 |= GPIO_InitStruct->GPIO_Pin; - GPIOx->PC1 &= ~GPIO_InitStruct->GPIO_Pin; - GPIOx->PC2 &= ~GPIO_InitStruct->GPIO_Pin; - break; - - case GPIO_Mode_IPD: - GPIOx->PM &= ~GPIO_InitStruct->GPIO_Pin; - GPIOx->PC0 |= GPIO_InitStruct->GPIO_Pin; - GPIOx->PC1 |= GPIO_InitStruct->GPIO_Pin; - GPIOx->PC2 &= ~GPIO_InitStruct->GPIO_Pin; - GPIOx->PD &= ~GPIO_InitStruct->GPIO_Pin; - GPIOx->PM |= GPIO_InitStruct->GPIO_Pin; - break; - - case GPIO_Mode_IPU: - GPIOx->PM &= ~GPIO_InitStruct->GPIO_Pin; - GPIOx->PC0 |= GPIO_InitStruct->GPIO_Pin; - GPIOx->PC1 |= GPIO_InitStruct->GPIO_Pin; - GPIOx->PC2 &= ~GPIO_InitStruct->GPIO_Pin; - GPIOx->PD |= GPIO_InitStruct->GPIO_Pin; - GPIOx->PM |= GPIO_InitStruct->GPIO_Pin; - break; - - case GPIO_Mode_Out_OD: - GPIOx->PC0 &= ~GPIO_InitStruct->GPIO_Pin; - GPIOx->PC1 &= ~GPIO_InitStruct->GPIO_Pin; - GPIOx->PC2 |= GPIO_InitStruct->GPIO_Pin; - break; - - case GPIO_Mode_Out_PP: - GPIOx->PC0 |= GPIO_InitStruct->GPIO_Pin; - GPIOx->PC1 &= ~GPIO_InitStruct->GPIO_Pin; - GPIOx->PC2 |= GPIO_InitStruct->GPIO_Pin; - break; - - case GPIO_Mode_AF_OD: - GPIOx->PD |= GPIO_InitStruct->GPIO_Pin; - GPIOx->PC1 |= GPIO_InitStruct->GPIO_Pin; - GPIOx->PC0 &= ~GPIO_InitStruct->GPIO_Pin; - GPIOx->PC2 |= GPIO_InitStruct->GPIO_Pin; - break; - - case GPIO_Mode_AF_PP: - GPIOx->PC0 |= GPIO_InitStruct->GPIO_Pin; - GPIOx->PC1 |= GPIO_InitStruct->GPIO_Pin; - GPIOx->PC2 |= GPIO_InitStruct->GPIO_Pin; - break; - - default : - GPIOx->PC0 |= GPIO_InitStruct->GPIO_Pin; - GPIOx->PC1 &= ~GPIO_InitStruct->GPIO_Pin; - GPIOx->PC2 &= ~GPIO_InitStruct->GPIO_Pin; - break; - } -} - -/******************************************************************************* -* Function Name : GPIO_StructInit -* Description : Fills each GPIO_InitStruct member with its default value. -* Input : GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure -* which will be initialized. -* Output : None -* Return : None -*******************************************************************************/ -void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) -{ - /* Reset GPIO init structure parameters values */ - GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; -} - -/******************************************************************************* -* Function Name : GPIO_Read -* Description : Reads the specified GPIO data port. -* Input : GPIOx: where x can be 0,1 or 2 to select the GPIO peripheral. -* Output : None -* Return : GPIO data port word value. -*******************************************************************************/ -u32 GPIO_Read(GPIO_TypeDef* GPIOx) -{ - return GPIOx->PD; -} - -/******************************************************************************* -* Function Name : GPIO_ReadBit -* Description : Reads the specified data port bit. -* Input : - GPIOx: where x can be (0..2) to select the GPIO peripheral. -* : - GPIO_Pin: specifies the port bit to read. -* This parameter can be GPIO_Pin_x where x can be (0..31) for -* GPIO0 and x(0..19) for GPIO1 and GPIO2. -* Output : None -* Return : The port pin value -*******************************************************************************/ -u8 GPIO_ReadBit(GPIO_TypeDef* GPIOx, u32 GPIO_Pin) -{ - if ((GPIOx->PD & GPIO_Pin) != Bit_RESET) - { - return Bit_SET; - } - else - { - return Bit_RESET; - } -} - -/******************************************************************************* -* Function Name : GPIO_Write -* Description : Writes data to the specified GPIO data port. -* Input :- GPIOx: where x can be 0,1 or 2 to select the GPIO peripheral. -* - PortVal: specifies the value to be written to the data port -* register. -* Output : None -* Return : None -*******************************************************************************/ -void GPIO_Write(GPIO_TypeDef* GPIOx, u32 PortVal) -{ - GPIOx->PD = PortVal; -} - -/******************************************************************************* -* Function Name : GPIO_WriteBit -* Description : Sets or clears the selected data port bit. -* Input : - GPIOx: where x can be (0..2) to select the GPIO peripheral. -* - GPIO_Pin: specifies the port bit to be written. -* This parameter can be GPIO_Pin_x where x can be (0..31) for -* GPIO0 and x(0..19) for GPIO1 and GPIO2. -* - BitVal: specifies the value to be written to the selected bit. -* This parameter must be one of the BitAction enum values: -* - Bit_RESET: to clear the port pin -* - Bit_SET: to set the port pin -* Output : None -* Return : None -*******************************************************************************/ -void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u32 GPIO_Pin, BitAction BitVal) -{ - if(BitVal != Bit_RESET) - { - GPIOx->PD |= GPIO_Pin; - } - else - { - GPIOx->PD &= ~GPIO_Pin; - } -} - -/******************************************************************************* -* Function Name : GPIO_PinMaskConfig -* Description : Enables or disables write protection to the selected bits in -* the I/O port registers (PxC2, PxC1, PxC0 and PxD). -* Input :- GPIOx: where x can be 0,1 or 2 to select the GPIO peripheral. -* - GPIO_Pin: specifies the port bit to be protected. -* This parameter can be GPIO_Pin_x where x can be (0..31) for -* GPIO0 and x(0..19) for GPIO1 and GPIO2. -* - NewState: new state of the port pin. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void GPIO_PinMaskConfig(GPIO_TypeDef* GPIOx, u32 GPIO_Pin, FunctionalState NewState) -{ - if(NewState == ENABLE) - { - GPIOx->PM |= GPIO_Pin; - } - else - { - GPIOx->PM &= ~GPIO_Pin; - } -} - -/******************************************************************************* -* Function Name : GPIO_GetPortMask -* Description : Gets the GPIOx port mask value. -* Input : GPIOx: where x can be 0,1 or 2 to select the GPIO peripheral. -* Output : None -* Return : GPIO port mask value. -*******************************************************************************/ -u32 GPIO_GetPortMask(GPIO_TypeDef* GPIOx) -{ - return GPIOx->PM; -} - -/******************************************************************************* -* Function Name : GPIO_PinRemapConfig -* Description : Changes the mapping of the specified pin. -* Input :- GPIO_Remap: selects the pin to remap. -* This parameter can be one of the following values: -* - GPIO_Remap_SMI_CS3_EN: Enable SMI CS3 -* - GPIO_Remap_SMI_CS2_EN: Enable SMI CS2 -* - GPIO_Remap_SMI_CS1_EN: Enable SMI CS1 -* - GPIO_Remap_SMI_EN: Enable SMI Alternate Functions: -* SMI_CS0, SMI_CK, SMI_DIN and SMI_DOUT -* - GPIO_Remap_DBGOFF: JTAG Disable -* - GPIO_Remap_UART1: UART1 Alternate Function mapping -* - GPIO_Remap_UART2: UART2 Alternate Function mapping -* - GPIO_Remap_SSP1: SSP1 Alternate Function mapping -* - GPIO_Remap_TIM2: TIM2 Alternate Function mapping -* - GPIO_Remap_TIM0: TIM0 Alternate Function mapping -* - NewState: new state of the port pin. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void GPIO_PinRemapConfig(u16 GPIO_Remap, FunctionalState NewState) -{ - u32 GPIOReg = 0; - u32 PinPos = 0; - - /* Get the GPIO register index */ - GPIOReg = GPIO_Remap >> 5; - - /* Get the pin position */ - PinPos = GPIO_Remap & GPIO_Remap_Mask; - - if(GPIOReg == 1) /* The pin to remap is in REMAP0R register */ - { - if(NewState == ENABLE) - { - GPIOREMAP->REMAP0R |= (1 << PinPos); - } - else - { - GPIOREMAP->REMAP0R &= ~(1 << PinPos); - } - } - else if(GPIOReg == 2) /* The pin to remap is in REMAP1R register */ - { - if(NewState == ENABLE) - { - GPIOREMAP->REMAP1R |= (1 << PinPos); - } - else - { - GPIOREMAP->REMAP1R &= ~(1 << PinPos); - } - } -} - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_i2c.c b/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_i2c.c deleted file mode 100644 index e5e5d001c..000000000 --- a/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_i2c.c +++ /dev/null @@ -1,568 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_i2c.c -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file provides all the I2C software functions. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -#include "75x_i2c.h" -#include "75x_mrcc.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* I2C IT enable */ -#define I2C_IT_Enable 0x01 -#define I2C_IT_Disable 0xFE - -/* I2C Peripheral Enable/Disable */ -#define I2C_PE_Set 0x20 -#define I2C_PE_Reset 0xDF - -/* I2C START Enable/Disable */ -#define I2C_Start_Enable 0x08 -#define I2C_Start_Disable 0xF7 - -/* I2C STOP Enable/Disable */ -#define I2C_Stop_Enable 0x02 -#define I2C_Stop_Disable 0xFD - -/* Address direction bit */ -#define I2C_ADD0_Set 0x01 -#define I2C_ADD0_Reset 0xFE - -/* I2C Masks */ -#define I2C_Frequency_Mask 0x1F -#define I2C_AddressHigh_Mask 0xF9 -#define I2C_OwnAddress_Mask 0x0300 -#define I2C_StandardMode_Mask 0x7f -#define I2C_FastMode_Mask 0x80 -#define I2C_Event_Mask 0x3FFF - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/******************************************************************************* -* Function Name : I2C_DeInit -* Description : Deinitializes the I2C peripheral registers to their default -* reset values. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void I2C_DeInit(void) -{ - /* Reset the I2C registers values*/ - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_I2C,ENABLE); - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_I2C,DISABLE); -} - -/******************************************************************************* -* Function Name : I2C_Init -* Description : Initializes the I2C peripheral according to the specified -* parameters in the I2C_Initstruct. -* Input : - I2C_InitStruct: pointer to a I2C_InitTypeDef structure that -* contains the configuration information for the specified I2C -* peripheral. -* Output : None -* Return : None -*******************************************************************************/ -void I2C_Init(I2C_InitTypeDef* I2C_InitStruct) -{ - u8 ITEState = 0; - u16 Result = 0x0F; - u32 APBClock = 8000000; - MRCC_ClocksTypeDef MRCC_ClocksStatus; - - /* Get APBClock frequency value */ - MRCC_GetClocksStatus(&MRCC_ClocksStatus); - APBClock = MRCC_ClocksStatus.PCLK_Frequency; - /* Save ITE bit state */ - ITEState = I2C->CR & 0xFE; - /* Disable I2C peripheral to set FR[2:0] bits */ - I2C_Cmd(DISABLE); - /* Clear frequency FR[2:0] bits */ - I2C->OAR2 &= I2C_Frequency_Mask; - - /* Set frequency bits depending on APBClock value */ - if (APBClock < 10000000) - I2C->OAR2 &= 0x1F; - else if (APBClock < 16670000) - I2C->OAR2 |= 0x20; - else if (APBClock < 26670000) - I2C->OAR2 |= 0x40; - else if (APBClock < 40000000) - I2C->OAR2 |= 0x60; - else if (APBClock < 53330000) - I2C->OAR2 |= 0x80; - else if (APBClock < 66000000) - I2C->OAR2 |= 0xA0; - else if (APBClock < 80000000) - I2C->OAR2 |= 0xC0; - else if (APBClock < 100000000) - I2C->OAR2 |= 0xE0; - I2C_Cmd(ENABLE); - - /* Restore the ITE bit state */ - I2C->CR |= ITEState; - - /* Configure general call */ - if (I2C_InitStruct->I2C_GeneralCall == I2C_GeneralCall_Enable) - { - /* Enable general call */ - I2C->CR |= I2C_GeneralCall_Enable; - } - else - { - /* Disable general call */ - I2C->CR &= I2C_GeneralCall_Disable; - } - - /* Configure acknowledgement */ - if (I2C_InitStruct->I2C_Ack == I2C_Ack_Enable) - { - /* Enable acknowledgement */ - I2C->CR |= I2C_Ack_Enable; - } - else - { - /* Disable acknowledgement */ - I2C->CR &= I2C_Ack_Disable; - } - - /* Configure LSB own address */ - I2C->OAR1 = I2C_InitStruct->I2C_OwnAddress; - /* Clear MSB own address ADD[9:8] bits */ - I2C->OAR2 &= I2C_AddressHigh_Mask; - /* Set MSB own address value */ - I2C->OAR2 |= (I2C_InitStruct->I2C_OwnAddress & I2C_OwnAddress_Mask)>>7; - - /* Configure speed in standard mode */ - if (I2C_InitStruct->I2C_CLKSpeed <= 100000) - { - /* Standard mode speed calculate */ - Result = ((APBClock/I2C_InitStruct->I2C_CLKSpeed)-7)/2; - /* Set speed value and clear FM/SM bit for standard mode in LSB clock divider */ - I2C->CCR = Result & I2C_StandardMode_Mask; - } - /* Configure speed in fast mode */ - else if (I2C_InitStruct->I2C_CLKSpeed <= 400000) - { - /* Fast mode speed calculate */ - Result = ((APBClock/I2C_InitStruct->I2C_CLKSpeed)-9)/3; - /* Set speed value and set FM/SM bit for fast mode in LSB clock divider */ - I2C->CCR = Result | I2C_FastMode_Mask; - } - /* Set speed in MSB clock divider */ - I2C->ECCR = Result >>7; -} - -/******************************************************************************* -* Function Name : I2C_StructInit -* Description : Fills each I2C_InitStruct member with its default value. -* Input : - I2C_InitStruct: pointer to an I2C_InitTypeDef structure - which will be initialized. -* Output : None -* Return : None. -*******************************************************************************/ -void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) -{ - /* Initialize the I2C_CLKSpeed member */ - I2C_InitStruct->I2C_CLKSpeed = 5000; - - /* Initialize the I2C_OwnAddress member */ - I2C_InitStruct->I2C_OwnAddress = 0x0; - - /* Initialize the I2C_GeneralCall member */ - I2C_InitStruct->I2C_GeneralCall = I2C_GeneralCall_Disable; - - /* Initialize the I2C_Ack member */ - I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; -} - -/******************************************************************************* -* Function Name : I2C_Cmd -* Description : Enables or disables the I2C peripheral. -* Input : - NewState: new state of the I2C peripheral. This parameter -* can be: ENABLE or DISABLE. -* Output : None -* Return : None. -*******************************************************************************/ -void I2C_Cmd(FunctionalState NewState) -{ - if (NewState == ENABLE) - { - /* Enable the I2C peripheral by setting twice the PE bit on the CR register */ - I2C->CR |= I2C_PE_Set; - I2C->CR |= I2C_PE_Set; - } - else - { - /* Disable the I2C peripheral */ - I2C->CR &= I2C_PE_Reset; - } -} - -/******************************************************************************* -* Function Name : I2C_GenerateSTART -* Description : Generates I2C communication START condition. -* Input : - NewState: new state of the I2C START condition generation. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None. -*******************************************************************************/ -void I2C_GenerateSTART(FunctionalState NewState) -{ - if (NewState == ENABLE) - { - /* Generate a START condition */ - I2C->CR |= I2C_Start_Enable; - } - else - { - /* Disable the START condition generation */ - I2C->CR &= I2C_Start_Disable; - } -} - -/******************************************************************************* -* Function Name : I2C_GenerateSTOP -* Description : Generates I2C communication STOP condition. -* Input : - NewState: new state of the I2C STOP condition generation. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None. -*******************************************************************************/ -void I2C_GenerateSTOP(FunctionalState NewState) -{ - if (NewState == ENABLE) - { - /* Generate a SIOP condition */ - I2C->CR |= I2C_Stop_Enable; - } - else - { - /* Disable the STOP condition generation */ - I2C->CR &= I2C_Stop_Disable; - } -} - -/******************************************************************************* -* Function Name : I2C_AcknowledgeConfig -* Description : Enables or disables I2C acknowledge feature. -* Input : - NewState: new state of the I2C Acknowledgement. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None. -*******************************************************************************/ -void I2C_AcknowledgeConfig(FunctionalState NewState) -{ - if (NewState == ENABLE) - { - /* Enable the acknowledgement */ - I2C->CR |= I2C_Ack_Enable; - } - else - { - /* Disable the acknowledgement */ - I2C->CR &= I2C_Ack_Disable; - } -} - -/******************************************************************************* -* Function Name : I2C_ITConfig -* Description : Enables or disables the I2C interrupt. -* Input : - NewState: new state of the I2C interrupt. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None. -*******************************************************************************/ -void I2C_ITConfig(FunctionalState NewState) -{ - if (NewState == ENABLE) - { - /* Enable the I2C interrupt */ - I2C->CR |= I2C_IT_Enable; - } - else - { - /* Disable the I2C interrupt */ - I2C->CR &= I2C_IT_Disable; - } -} - -/******************************************************************************* -* Function Name : I2C_GetLastEvent -* Description : Gets the last I2C event that has occurred. -* Input : None -* Output : None -* Return : The Last happened Event. -*******************************************************************************/ -u16 I2C_GetLastEvent(void) -{ - u16 Flag1 = 0, Flag2 = 0, LastEvent = 0; - - Flag1 = I2C->SR1; - Flag2 = I2C->SR2; - Flag2 = Flag2<<8; - /* Get the last event value from I2C status register */ - LastEvent = (((Flag1 | (Flag2)) & I2C_Event_Mask)); - /* Return the last event */ - return LastEvent; -} - -/******************************************************************************* -* Function Name : I2C_CheckEvent -* Description : Checks whether the Last I2C Event is equal to the one passed -* as parameter. -* Input : - I2C_EVENT: specifies the event to be checked. This parameter -* can be one of the following values: -* - I2C_EVENT_SLAVE_ADDRESS_MATCHED -* - I2C_EVENT_SLAVE_BYTE_RECEIVED -* - I2C_EVENT_SLAVE_BYTE_TRANSMITTED -* - I2C_EVENT_SLAVE_ACK_FAILURE -* - I2C_EVENT_MASTER_MODE_SELECT -* - I2C_EVENT_MASTER_MODE_SELECTED -* - I2C_EVENT_MASTER_BYTE_RECEIVED -* - I2C_EVENT_MASTER_BYTE_TRANSMITTED -* - I2C_EVENT_MASTER_MODE_ADDRESS10 -* - I2C_EVENT_SLAVE_STOP_DETECTED -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Last event is equal to the I2C_Event -* - ERROR: Last event is different from the I2C_Event -*******************************************************************************/ -ErrorStatus I2C_CheckEvent(u16 I2C_EVENT) -{ - u16 LastEvent = I2C_GetLastEvent(); - - /* Check whether the last event is equal to I2C_EVENT */ - if (LastEvent == I2C_EVENT) - { - /* Return SUCCESS when last event is equal to I2C_EVENT */ - return SUCCESS; - } - else - { - /* Return ERROR when last event is different from I2C_EVENT */ - return ERROR; - } -} - -/******************************************************************************* -* Function Name : I2C_SendData -* Description : Sends a data byte. -* Input : - Data: indicates the byte to be transmitted. -* Output : None -* Return : None. -*******************************************************************************/ -void I2C_SendData(u8 Data) -{ - /* Write in the DR register the byte to be sent */ - I2C->DR = Data; -} - -/******************************************************************************* -* Function Name : I2C_ReceiveData -* Description : Reads the received byte. -* Input : None -* Output : None -* Return : The received byte -*******************************************************************************/ -u8 I2C_ReceiveData(void) -{ - /* Return from the DR register the received byte */ - return I2C->DR; -} - -/******************************************************************************* -* Function Name : I2C_Send7bitAddress -* Description : Transmits the address byte to select the slave device. -* Input : - Address: specifies the slave address which will be transmitted -* - Direction: specifies whether the I2C device will be a -* Transmitter or a Receiver. This parameter can be one of the -* following values -* - I2C_MODE_TRANSMITTER: Transmitter mode -* - I2C_MODE_RECEIVER: Receiver mode -* Output : None -* Return : None. -*******************************************************************************/ -void I2C_Send7bitAddress(u8 Address, u8 Direction) -{ - /* Test on the direction to define the read/write bit */ - if (Direction == I2C_MODE_RECEIVER) - { - /* Set the address bit0 for read */ - Address |= I2C_ADD0_Set; - } - else - { - /* Reset the address bit0 for write */ - Address &= I2C_ADD0_Reset; - } - /* Send the address */ - I2C->DR = Address; -} - -/******************************************************************************* -* Function Name : I2C_ReadRegister -* Description : Reads the specified I2C register and returns its value. -* Input1 : - I2C_Register: specifies the register to read. -* This parameter can be one of the following values: -* - I2C_CR: CR register. -* - I2C_SR1: SR1 register. -* - I2C_SR2: SR2 register. -* - I2C_CCR: CCR register. -* - I2C_OAR1: OAR1 register. -* - I2C_OAR2: OAR2 register. -* - I2C_DR: DR register. -* - I2C_ECCR: ECCR register. -* Output : None -* Return : The value of the read register. -*******************************************************************************/ -u8 I2C_ReadRegister(u8 I2C_Register) -{ - /* Return the selected register value */ - return (*(u8 *)(I2C_BASE + I2C_Register)); -} - -/******************************************************************************* -* Function Name : I2C_GetFlagStatus -* Description : Checks whether the specified I2C flag is set or not. -* Input : - I2C_FLAG: specifies the flag to check. -* This parameter can be one of the following values: -* - I2C_FLAG_SB: Start bit flag (Master mode) -* - I2C_FLAG_M_SL: Master/Slave flag -* - I2C_FLAG_ADSL: Address matched flag (Slave mode) -* - I2C_FLAG_BTF: Byte transfer finished flag -* - I2C_FLAG_BUSY: Bus busy flag -* - I2C_FLAG_TRA: Transmitter/Receiver flag -* - I2C_FLAG_ADD10: 10-bit addressing in Master mode flag -* - I2C_FLAG_EVF: Event flag -* - I2C_FLAG_GCAL: General call flag (slave mode) -* - I2C_FLAG_BERR: Bus error flag -* - I2C_FLAG_ARLO: Arbitration lost flag -* - I2C_FLAG_STOPF: Stop detection flag (slave mode) -* - I2C_FLAG_AF: Acknowledge failure flag -* - I2C_FLAG_ENDAD: End of address transmission flag -* - I2C_FLAG_ACK: Acknowledge enable flag -* Output : None -* Return : The NewState of the I2C_FLAG (SET or RESET). -*******************************************************************************/ -FlagStatus I2C_GetFlagStatus(u16 I2C_FLAG) -{ - u16 Flag1 = 0, Flag2 = 0, Flag3 = 0, Tmp = 0; - - Flag1 = I2C->SR1; - Flag2 = I2C->SR2; - Flag2 = Flag2<<8; - Flag3 = I2C->CR & 0x04; - - /* Get all the I2C flags in a unique register*/ - Tmp = (((Flag1 | (Flag2)) & I2C_Event_Mask) | (Flag3<<12)); - - /* Check the status of the specified I2C flag */ - if((Tmp & I2C_FLAG) != RESET) - { - /* Return SET if I2C_FLAG is set */ - return SET; - } - else - { - /* Return RESET if I2C_FLAG is reset */ - return RESET; - } -} - -/******************************************************************************* -* Function Name : I2C_ClearFlag -* Description : Clears the I2C’s pending flags -* Input : - I2C_FLAG: specifies the flag to clear. -* This parameter can be one of the following values: -* - I2C_FLAG_SB: Start bit flag -* - I2C_FLAG_M_SL: Master/Slave flag -* - I2C_FLAG_ADSL: Adress matched flag -* - I2C_FLAG_BTF: Byte transfer finished flag -* - I2C_FLAG_BUSY: Bus busy flag -* - I2C_FLAG_TRA: Transmitter/Receiver flag -* - I2C_FLAG_ADD10: 10-bit addressing in Master mode flag -* - I2C_FLAG_EVF: Event flag -* - I2C_FLAG_GCAL: General call flag -* - I2C_FLAG_BERR: Bus error flag -* - I2C_FLAG_ARLO: Arbitration lost flag -* - I2C_FLAG_STOPF: Stop detection flag -* - I2C_FLAG_AF: Acknowledge failure flag -* - I2C_FLAG_ENDAD: End of address transmission flag -* - I2C_FLAG_ACK: Acknowledge enable flag -* - parameter needed in the case that the flag to be cleared -* need a write in one register -* Output : None -* Return : None -*******************************************************************************/ -void I2C_ClearFlag(u16 I2C_FLAG, ...) -{ - u8 Tmp = (u8)*((u32 *) & I2C_FLAG + sizeof(I2C_FLAG)); - - /* flags that need a read of the SR2 register to be cleared */ - if ((I2C_FLAG == I2C_FLAG_ADD10) || (I2C_FLAG == I2C_FLAG_EVF) || - (I2C_FLAG == I2C_FLAG_STOPF) || (I2C_FLAG == I2C_FLAG_AF) || - (I2C_FLAG == I2C_FLAG_BERR) || (I2C_FLAG == I2C_FLAG_ARLO) || - (I2C_FLAG == I2C_FLAG_ENDAD)) - { - /* Read the SR2 register */ - (void)I2C->SR2; - - /* Two flags need a second step to be cleared */ - switch (I2C_FLAG) - { - case I2C_FLAG_ADD10: - /* Send the MSB 10bit address passed as second parameter */ - I2C->DR = Tmp; - break; - case I2C_FLAG_ENDAD: - /* Write to the I2C_CR register by setting PE bit */ - I2C->CR |= I2C_PE_Set; - break; - } - } - /* flags that need a read of the SR1 register to be cleared */ - else if (I2C_FLAG==I2C_FLAG_SB || I2C_FLAG==I2C_FLAG_ADSL || I2C_FLAG==I2C_FLAG_BTF || I2C_FLAG==I2C_FLAG_TRA) - { - /* Read the SR1 register */ - (void)I2C->SR1; - - /* three flags need a second step to be cleared */ - if (I2C_FLAG == I2C_FLAG_SB) - { - /* Send the address byte passed as second parameter */ - I2C->DR=Tmp; - } - else if (I2C_FLAG==I2C_FLAG_BTF || I2C_FLAG==I2C_FLAG_TRA) - { - /* return the received byte in the variable passed as second parameter */ - Tmp=I2C->DR; - } - } - /* flags that need to disable the I2C interface */ - else if ( I2C_FLAG==I2C_FLAG_M_SL || I2C_FLAG==I2C_FLAG_GCAL) - { - I2C_Cmd(DISABLE); - I2C_Cmd(ENABLE); - } -} - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_it.c b/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_it.c deleted file mode 100644 index b73503624..000000000 --- a/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_it.c +++ /dev/null @@ -1,448 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_it.c -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : Main Interrupt Service Routines. -* This file can be used to describe all the exceptions -* subroutines that may occur within user application. -* When an interrupt happens, the software will branch -* automatically to the corresponding routine according -* to the interrupt vector loaded in the PC register. -* The following routines are all empty, user can write code -* for exceptions handlers and peripherals IRQ interrupts. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/******************************************************************************* -* Function Name : Undefined_Handler -* Description : This function handles Undefined instruction exception. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void Undefined_Handler(void) -{ -} - -/******************************************************************************* -* Function Name : FIQ_Handler -* Description : This function handles FIQ exception. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void FIQ_Handler(void) -{ -} - -/******************************************************************************* -* Function Name : SWI_Handler -* Description : This function handles SW exception. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void SWI_Handler(void) -{ -} - -/******************************************************************************* -* Function Name : Prefetch_Handler -* Description : This function handles preftetch abort exception. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void Prefetch_Handler(void) -{ -} - -/******************************************************************************* -* Function Name : Abort_Handler -* Description : This function handles data abort exception. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void Abort_Handler(void) -{ -} - -/******************************************************************************* -* Function Name : WAKUP_IRQHandler -* Description : This function handles External line 15(WAKUP) interrupt -* request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void WAKUP_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : TIM2_OC2_IRQHandler -* Description : This function handles TIM2 Output Compare 2 interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void TIM2_OC2_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : TIM2_OC1_IRQHandler -* Description : This function handles TIM2 Output Compare 1 interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void TIM2_OC1_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : TIM2_IC12_IRQHandler -* Description : This function handles TIM2 Input Capture 1 & 2 interrupt -* request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void TIM2_IC12_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : TIM2_UP_IRQHandler -* Description : This function handles TIM2 Update interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void TIM2_UP_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : TIM1_OC2_IRQHandler -* Description : This function handles TIM1 Output Compare 2 interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void TIM1_OC2_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : TIM1_OC1_IRQHandler -* Description : This function handles TIM1 Output Compare 1 interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void TIM1_OC1_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : TIM1_IC12_IRQHandler -* Description : This function handles TIM1 Input Capture 1 & 2 interrupt -* request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void TIM1_IC12_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : TIM1_UP_IRQHandler -* Description : This function handles TIM1 Update interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void TIM1_UP_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : TIM0_OC2_IRQHandler -* Description : This function handles TIM0 Output Compare 2 interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void TIM0_OC2_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : TIM0_OC1_IRQHandler -* Description : This function handles TIM0 Output Compare 1 interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void TIM0_OC1_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : TIM0_IC12_IRQHandler -* Description : This function handles TIM0 Input Capture 1 & 2 interrupt -* request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void TIM0_IC12_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : TIM0_UP_IRQHandler -* Description : This function handles TIM0 Update interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void TIM0_UP_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : PWM_OC123_IRQHandler -* Description : This function handles PWM Output Compare 1,2&3 interrupt -* request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void PWM_OC123_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : PWM_EM_IRQHandler -* Description : This function handles PWM Emergency interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void PWM_EM_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : PWM_UP_IRQHandler -* Description : This function handles PWM Update interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void PWM_UP_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : I2C_IRQHandler -* Description : This function handles I2C global interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void I2C_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : SSP1_IRQHandler -* Description : This function handles SSP1 interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void SSP1_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : SSP0_IRQHandler -* Description : This function handles SSP0 interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void SSP0_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : UART2_IRQHandler -* Description : This function handles UART2 global interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void UART2_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : UART1_IRQHandler -* Description : This function handles UART1 global interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void UART1_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : UART0_IRQHandler -* Description : This function handles UART0 global interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void UART0_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : CAN_IRQHandler -* Description : This function handles CAN global interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void CAN_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : USBLP_IRQHandler -* Description : This function handles USB Low Priority event interrupt -* request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void USB_LP_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : USBHP_IRQHandler -* Description : This function handles USB High Priority event interrupt -* request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void USB_HP_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : ADC_IRQHandler -* Description : This function handles ADC global interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void ADC_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : DMA_IRQHandler -* Description : This function handles DMA global interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void DMA_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : EXTIT_IRQHandler -* Description : This function handles External lines 14 to 1 interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void EXTIT_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : MRCC_IRQHandler -* Description : This function handles MRCC interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void MRCC_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : FLASHSMI_IRQHandler -* Description : This function handles Flash and SMI global interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void FLASHSMI_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : RTC_IRQHandler -* Description : This function handles RTC global interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void RTC_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : TB_IRQHandler -* Description : This function handles TB global interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void TB_IRQHandler(void) -{ -} - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_lib.c b/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_lib.c deleted file mode 100644 index 16c87f064..000000000 --- a/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_lib.c +++ /dev/null @@ -1,178 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_lib.c -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file provides all peripherals pointers initialization. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#define EXT - -/* Includes ------------------------------------------------------------------*/ -#include "75x_lib.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -#ifdef DEBUG - -/******************************************************************************* -* Function Name : debug -* Description : This function initialize peripherals pointers. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void debug(void) -{ -/************************************* SMI ************************************/ -#ifdef _SMI - SMI = (SMI_TypeDef *) SMIR_BASE; -#endif /*_SMI */ - -/************************************* CFG ************************************/ -#ifdef _CFG - CFG = (CFG_TypeDef *) CFG_BASE; -#endif /*_CFG */ - -/************************************* MRCC ***********************************/ -#ifdef _MRCC - MRCC = (MRCC_TypeDef *) MRCC_BASE; -#endif /*_MRCC */ - -/************************************* ADC ************************************/ -#ifdef _ADC - ADC = (ADC_TypeDef *) ADC_BASE; -#endif /*_ADC */ - -/************************************* TB *************************************/ -#ifdef _TB - TB = (TB_TypeDef *) TB_BASE; -#endif /*_TB */ - -/************************************* TIM ************************************/ -#ifdef _TIM0 - TIM0 = (TIM_TypeDef *) TIM0_BASE; -#endif /*_TIM0 */ - -#ifdef _TIM1 - TIM1 = (TIM_TypeDef *) TIM1_BASE; -#endif /*_TIM1 */ - -#ifdef _TIM2 - TIM2 = (TIM_TypeDef *) TIM2_BASE; -#endif /*_TIM2 */ - -/************************************* PWM ************************************/ -#ifdef _PWM - PWM = (PWM_TypeDef *) PWM_BASE; -#endif /*_PWM */ - -/************************************* WDG ************************************/ -#ifdef _WDG - WDG = (WDG_TypeDef *) WDG_BASE; -#endif /*_WDG */ - -/************************************* SSP ************************************/ -#ifdef _SSP0 - SSP0 = (SSP_TypeDef *) SSP0_BASE; -#endif /*_SSP0 */ - -#ifdef _SSP1 - SSP1 = (SSP_TypeDef *) SSP1_BASE; -#endif /*_SSP1 */ - -/************************************* CAN ************************************/ -#ifdef _CAN - CAN = (CAN_TypeDef *) CAN_BASE; -#endif /*_CAN */ - -/************************************* I2C ************************************/ -#ifdef _I2C - I2C = (I2C_TypeDef *) I2C_BASE; -#endif /*_I2C */ - -/************************************* UART ***********************************/ -#ifdef _UART0 - UART0 = (UART_TypeDef *) UART0_BASE; -#endif /*_UART0 */ - -#ifdef _UART1 - UART1 = (UART_TypeDef *) UART1_BASE; -#endif /*_UART1 */ - -#ifdef _UART2 - UART2 = (UART_TypeDef *) UART2_BASE; -#endif /*_UART2 */ - -/************************************* GPIO ***********************************/ -#ifdef _GPIO0 - GPIO0 = (GPIO_TypeDef *) GPIO0_BASE; -#endif /*_GPIO0 */ - -#ifdef _GPIO1 - GPIO1 = (GPIO_TypeDef *) GPIO1_BASE; -#endif /*_GPIO1 */ - -#ifdef _GPIO2 - GPIO2 = (GPIO_TypeDef *) GPIO2_BASE; -#endif /*_GPIO2 */ - -#ifdef _GPIOREMAP - GPIOREMAP = (GPIOREMAP_TypeDef *) GPIOREMAP_BASE; -#endif /*_GPIOREMAP */ - -/************************************* DMA ************************************/ -#ifdef _DMA - DMA = (DMA_TypeDef *) DMA_BASE; -#endif /*_DMA */ - -#ifdef _DMA_Stream0 - DMA_Stream0 = (DMA_Stream_TypeDef *) DMA_Stream0_BASE; -#endif /*_DMA_Stream0 */ - -#ifdef _DMA_Stream1 - DMA_Stream1 = (DMA_Stream_TypeDef *) DMA_Stream1_BASE; -#endif /*_DMA_Stream1 */ - -#ifdef _DMA_Stream2 - DMA_Stream2 = (DMA_Stream_TypeDef *) DMA_Stream2_BASE; -#endif /*_DMA_Stream2 */ - -#ifdef _DMA_Stream3 - DMA_Stream3 = (DMA_Stream_TypeDef *) DMA_Stream3_BASE; -#endif /*_DMA_Stream3 */ - -/************************************* RTC ************************************/ -#ifdef _RTC - RTC = (RTC_TypeDef *) RTC_BASE; -#endif /*_RTC */ - -/************************************* EXTIT **********************************/ -#ifdef _EXTIT - EXTIT = (EXTIT_TypeDef *) EXTIT_BASE; -#endif /*_EXTIT */ - -/************************************* EIC ************************************/ -#ifdef _EIC - EIC = (EIC_TypeDef *) EIC_BASE; -#endif /*_EIC */ - -} - -#endif - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_mrcc.c b/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_mrcc.c deleted file mode 100644 index fadfb73c7..000000000 --- a/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_mrcc.c +++ /dev/null @@ -1,1673 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_mrcc.c -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file provides all the MRCC software functions. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -#include "75x_mrcc.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define MRCC_FLAG_Mask 0x1F /* MRCC Flag Mask */ - -/* MRCC_PWRCTRL mask bits */ -#define MRCC_LP_Set_Mask 0x00000001 -#define MRCC_LP_Reset_Mask 0xFFFFFFFE -#define MRCC_SWRESET_Mask 0x00000002 -#define MRCC_WFI_Mask 0x00000004 -#define MRCC_STANDBY_Mask 0x00000006 -#define MRCC_LPMC_Reset_Mask 0xFFFFFFF9 -#define MRCC_LPDONE_Reset_Mask 0xFFFFFF7F -#define MRCC_LPPARAM_Reset_Mask 0xFFFF1FFF -#define MRCC_WFIParam_Reset_Mask 0xFFFF1FEF -#define MRCC_CKRTCSEL_Set_Mask 0x03000000 -#define MRCC_CKRTCSEL_Reset_Mask 0xFCFFFFFF -#define MRCC_CKRTCOK_Mask 0x08000000 -#define MRCC_LPOSCEN_Mask 0x10000000 -#define MRCC_OSC32KEN_Mask 0x20000000 - -/* MRCC_CLKCTL mask bits */ -#define MRCC_PPRESC_Set_Mask 0x00000003 -#define MRCC_PPRESC_Reset_Mask 0xFFFFFFFC -#define MRCC_PPRESC2_Mask 0x00000004 -#define MRCC_HPRESC_Set_Mask 0x00000018 -#define MRCC_HPRESC_Reset_Mask 0xFFFFFFE7 -#define MRCC_MCOS_Reset_Mask 0xFFFFFF3F -#define MRCC_XTDIV2_Set_Mask 0x00008000 -#define MRCC_XTDIV2_Reset_Mask 0xFFFF7FFF -#define MRCC_OSC4MBYP_Set_Mask 0x00010000 -#define MRCC_OSC4MBYP_Reset_Mask 0xFFFEFFFF -#define MRCC_OSC4MOFF_Set_Mask 0x00020000 -#define MRCC_OSC4MOFF_Reset_Mask 0xFFFDFFFF -#define MRCC_NCKDF_Set_Mask 0x00040000 -#define MRCC_NCKDF_Reset_Mask 0xFFFBFFFF -#define MRCC_CKOSCSEL_Set_Mask 0x00200000 -#define MRCC_CKOSCSEL_Reset_Mask 0xFFDFFFFF -#define MRCC_CKUSBSEL_Mask 0x00400000 -#define MRCC_CKSEL_Set_Mask 0x00800000 -#define MRCC_CKSEL_Reset_Mask 0xFF7FFFFF -#define MRCC_CKSEL_CKOSCSEL_Mask 0x00A00000 -#define MRCC_PLLEN_Set_Mask 0x01000000 -#define MRCC_PLLEN_Reset_Mask 0xFEFFFFFF -#define MRCC_PLL2EN_Set_Mask 0x02000000 -#define MRCC_PLL2EN_Reset_Mask 0xFDFFFFFF -#define MRCC_MX_Set_Mask 0x18000000 -#define MRCC_MX_Reset_Mask 0xE7FFFFFF -#define MRCC_LOCK_Mask 0x80000000 -#define MRCC_PLLEN_LOCK_Mask 0x81000000 - -/* Typical Value of the OSC4M in Hz */ -#define OSC4M_Value 4000000 - -/* Typical Value of the OSC4M divided by 128 (used to clock the RTC) in Hz */ -#define OSC4M_Div128_Value 31250 - -/* Typical Value of the OS32K Oscillator Frequency in Hz */ -#define OSC32K_Value 32768 - -/* Typical Reset Value of the Internal LPOSC Oscillator Frequency in Hz */ -#define LPOSC_Value 245000 - -/* Typical Reset Value of the Internal FREEOSC Oscillator Frequency in Hz */ -#define FREEOSC_Value 5000000 - -/* Time out for OSC4M start up */ -#define OSC4MStartUp_TimeOut 0xFE - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -static ErrorStatus SetCKSYS_FREEOSC(void); -static ErrorStatus SetCKSYS_OSC4M(u32 PLL_State); -static ErrorStatus SetCKSYS_OSC4MPLL(u32 PLL_Mul); -static ErrorStatus SetCKSYS_RTC(u32 PLL_State); -static void WriteLPBit(void); -static void WriteCKOSCSELBit(void); - -/* Private functions ---------------------------------------------------------*/ - -/******************************************************************************* -* Function Name : MRCC_DeInit -* Description : Deinitializes the MRCC peripheral registers to their default -* reset values. -* - Depending on the system clock state, some bits in MRCC_CLKCTL -* register can’t be reset. -* - The OSC32K, LPOSC and RTC clock selection configuration -* bits in MRCC_PWRCTRL register are not cleared by this -* function. To reset those bits, use the dedicated functions -* available within this driver. -* - The MRCC_RFSR, MRCC_BKP0 and MRCC_BKP1 registers are not -* reset by this function. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void MRCC_DeInit(void) -{ - /* Try to clear NCKDF bit */ - MRCC->CLKCTL &= MRCC_NCKDF_Reset_Mask; - - if((MRCC->CLKCTL & MRCC_NCKDF_Set_Mask) != RESET) - {/* No clock detected on OSC4M */ - - /* Reset LOCKIE, LOCKIF, CKUSBSEL, NCKDIE, OSC4MOFF, OSC4MBYP, MCOS[1:0], - MCOP, HPRESC[1:0], PPRES[2:0] bits */ - MRCC->CLKCTL &= 0x9FB40000; - - if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) - { - /* Clear CKOSCSEL bit --------------------------------------------------*/ - /* Execute CKOSCSEL bit writing sequence */ - WriteCKOSCSELBit(); - } - } - else - {/* Clock present on OSC4M */ - - if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) - { - /* Reset CKSEL bit */ - MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask; - - /* Clear CKOSCSEL bit --------------------------------------------------*/ - /* Execute CKOSCSEL bit writing sequence */ - WriteCKOSCSELBit(); - } - - if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) == RESET) - { - /* Set CKSEL bit */ - MRCC->CLKCTL |= MRCC_CKSEL_Set_Mask; - } - - /* Disable PLL */ - MRCC->CLKCTL &= MRCC_PLLEN_Reset_Mask; - - /* Reset LOCKIE, LOCKIF, MX[1:0], CKUSBSEL, NCKDIE, MCOS[1:0], MCOP, - HPRESC[1:0], PPRES[2:0] bits */ - MRCC->CLKCTL &= 0x87B70000; - - /* Reset CKSEL bit */ - MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask; - - /* Reset OSC4MOFF and OSC4MBYP bits */ - MRCC->CLKCTL &= 0xFFFCFFFF; - } - - /* Reset RTCM, EN33V, LP_PARAM[15:13], WFI_FLASH_EN, LPMC_DBG and LPMC[1:0] bits */ - MRCC->PWRCTRL &= 0xFBFE1FE1; - - /* Reset PCLKEN register bits */ - MRCC->PCLKEN = 0x00; - - /* Reset PSWRES register bits */ - MRCC->PSWRES = 0x00; - - /* Clear NCKDF bit */ - MRCC->CLKCTL &= MRCC_NCKDF_Reset_Mask; -} - -/******************************************************************************* -* Function Name : MRCC_XTDIV2Config -* Description : Enables or disables the oscillator divider by 2. This function -* must not be used when the PLL is enabled. -* Input : - MRCC_XTDIV2: specifies the new state of the oscillator -* divider by 2. -* This parameter can be one of the following values: -* - MRCC_XTDIV2_Disable: oscillator divider by 2 disbaled -* - MRCC_XTDIV2_Enable: oscillator divider by 2 enbaled -* Output : None -* Return : None -*******************************************************************************/ -void MRCC_XTDIV2Config(u32 MRCC_XTDIV2) -{ - if(MRCC_XTDIV2 == MRCC_XTDIV2_Enable) - { - MRCC->CLKCTL |= MRCC_XTDIV2_Enable; - } - else - { - MRCC->CLKCTL &= MRCC_XTDIV2_Disable; - } -} - -/******************************************************************************* -* Function Name : MRCC_CKSYSConfig -* Description : Configures the system clock (CK_SYS). -* Input : - MRCC_CKSYS: specifies the clock source used as system clock. -* This parameter can be one of the following values: -* - MRCC_CKSYS_FREEOSC -* - MRCC_CKSYS_OSC4M -* - MRCC_CKSYS_OSC4MPLL -* - MRCC_CKSYS_RTC (RTC clock source must be previously -* configured using MRCC_CKRTCConfig() function) -* : - MRCC_PLL: specifies the PLL configuration. -* This parameter can be one of the following values: -* - MRCC_PLL_Disabled: PLL disabled -* - MRCC_PLL_NoChange: No change on PLL configuration -* - MRCC_PLL_Mul_12: Multiplication by 12 -* - MRCC_PLL_Mul_14: Multiplication by 14 -* - MRCC_PLL_Mul_15: Multiplication by 15 -* - MRCC_PLL_Mul_16: Multiplication by 16 -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Clock configuration succeeded -* - ERROR: Clock configuration failed -*******************************************************************************/ -ErrorStatus MRCC_CKSYSConfig(u32 MRCC_CKSYS, u32 MRCC_PLL) -{ - ErrorStatus Status = ERROR; - - switch(MRCC_CKSYS) - { - case MRCC_CKSYS_FREEOSC: - if((MRCC_PLL == MRCC_PLL_Disabled) || (MRCC_PLL == MRCC_PLL_NoChange)) - { - Status = SetCKSYS_FREEOSC(); - } - break; - - case MRCC_CKSYS_OSC4M: - if((MRCC_PLL == MRCC_PLL_Disabled) || (MRCC_PLL == MRCC_PLL_NoChange)) - { - Status = SetCKSYS_OSC4M(MRCC_PLL); - } - break; - - case MRCC_CKSYS_OSC4MPLL: - if((MRCC_PLL == MRCC_PLL_Mul_12) || (MRCC_PLL == MRCC_PLL_Mul_14) || - (MRCC_PLL == MRCC_PLL_Mul_15) || (MRCC_PLL == MRCC_PLL_Mul_16)) - { - Status = SetCKSYS_OSC4MPLL(MRCC_PLL); - } - break; - - case MRCC_CKSYS_RTC: - if((MRCC_PLL == MRCC_PLL_Disabled) || (MRCC_PLL == MRCC_PLL_NoChange)) - { - Status = SetCKSYS_RTC(MRCC_PLL); - } - break; - - default: - Status = ERROR; - break; - } - return Status; -} - -/******************************************************************************* -* Function Name : MRCC_HCLKConfig -* Description : Configures the AHB clock (HCLK). -* Input : - MRCC_HCLK: defines the AHB clock. This clock is derived -* from the system clock(CK_SYS). -* This parameter can be one of the following values: -* - MRCC_CKSYS_Div1: AHB clock = CK_SYS -* - MRCC_CKSYS_Div2: AHB clock = CK_SYS/2 -* - MRCC_CKSYS_Div4: AHB clock = CK_SYS/4 -* - MRCC_CKSYS_Div8: AHB clock = CK_SYS/8 -* Output : None -* Return : None -*******************************************************************************/ -void MRCC_HCLKConfig(u32 MRCC_HCLK) -{ - u32 Temp = 0; - - /* Clear HPRESC[1:0] bits */ - Temp = MRCC->CLKCTL & MRCC_HPRESC_Reset_Mask; - - /* Set HPRESC[1:0] bits according to MRCC_HCLK value */ - Temp |= MRCC_HCLK; - - /* Store the new value */ - MRCC->CLKCTL = Temp; -} - -/******************************************************************************* -* Function Name : MRCC_CKTIMConfig -* Description : Configures the TIM clock (CK_TIM). -* Input : - MRCC_CKTIM: defines the TIM clock. This clock is derived -* from the AHB clock(HCLK). -* This parameter can be one of the following values: -* - MRCC_HCLK_Div1: TIM clock = HCLK -* - MRCC_HCLK_Div2: TIM clock = HCLK/2 -* - MRCC_HCLK_Div4: TIM clock = HCLK/4 -* - MRCC_HCLK_Div8: TIM clock = HCLK/8 -* Output : None -* Return : None -*******************************************************************************/ -void MRCC_CKTIMConfig(u32 MRCC_CKTIM) -{ - u32 Temp = 0; - - /* Clear PPRESC[1:0] bits */ - Temp = MRCC->CLKCTL & MRCC_PPRESC_Reset_Mask; - - /* Set PPRESC[1:0] bits according to MRCC_CKTIM value */ - Temp |= MRCC_CKTIM; - - /* Store the new value */ - MRCC->CLKCTL = Temp; -} - -/******************************************************************************* -* Function Name : MRCC_PCLKConfig -* Description : Configures the APB clock (PCLK). -* Input : - MRCC_PCLK: defines the APB clock. This clock is derived -* from the TIM clock(CK_TIM). -* This parameter can be one of the following values: -* - MRCC_CKTIM_Div1: APB clock = CKTIM -* - MRCC_CKTIM_Div2: APB clock = CKTIM/2 -* Output : None -* Return : None -*******************************************************************************/ -void MRCC_PCLKConfig(u32 MRCC_PCLK) -{ - if(MRCC_PCLK == MRCC_CKTIM_Div2) - { - MRCC->CLKCTL |= MRCC_CKTIM_Div2; - } - else - { - MRCC->CLKCTL &= MRCC_CKTIM_Div1; - } -} - -/******************************************************************************* -* Function Name : MRCC_CKRTCConfig -* Description : Configures the RTC clock (CK_RTC). -* Input : - MRCC_CKRTC: specifies the clock source to be used as RTC -* clock. -* This parameter can be one of the following values: -* - MRCC_CKRTC_OSC4M_Div128 -* - MRCC_CKRTC_OSC32K (OSC32K must be previously enabled -* using MRCC_OSC32KConfig() function) -* - MRCC_CKRTC_LPOSC (LPOSC must be previously enabled -* using MRCC_LPOSCConfig() function) -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Clock configuration succeeded -* - ERROR: Clock configuration failed -*******************************************************************************/ -ErrorStatus MRCC_CKRTCConfig(u32 MRCC_CKRTC) -{ - u32 Tmp = 0; - - if(((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) && - ((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET)) - { - /* CK_RTC used as CK_SYS clock source */ - return ERROR; - } - else - { - /* Clear CKRTCSEL[1:0] bits */ - Tmp = MRCC->PWRCTRL & MRCC_CKRTCSEL_Reset_Mask; - - /* Set CKRTCSEL[1:0] bits according to MRCC_CKRTC value */ - Tmp |= MRCC_CKRTC; - - /* Store the new value */ - MRCC->PWRCTRL = Tmp; - } - - return SUCCESS; -} - -/******************************************************************************* -* Function Name : MRCC_CKUSBConfig -* Description : Configures the USB clock(CK_USB). -* Input : - MRCC_CKUSB: specifies the clock source to be used as USB -* clock. -* This parameter can be one of the following values: -* - MRCC_CKUSB_Internal(CK_PLL2 enabled) -* - MRCC_CKUSB_External(CK_PLL2 disabled) -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Clock configuration succeeded -* - ERROR: Clock configuration failed -*******************************************************************************/ -ErrorStatus MRCC_CKUSBConfig(u32 MRCC_CKUSB) -{ - if(MRCC_CKUSB == MRCC_CKUSB_External) - { - /* Disable CK_PLL2 */ - MRCC->CLKCTL &= MRCC_PLL2EN_Reset_Mask; - - /* External USB clock selected */ - MRCC->CLKCTL |= MRCC_CKUSB_External; - } - else - { - if((MRCC->CLKCTL & MRCC_PLLEN_LOCK_Mask) != RESET) - { /* PLL enabled and locked */ - - /* Enable CK_PLL2 */ - MRCC->CLKCTL |= MRCC_PLL2EN_Set_Mask; - - /* Internal USB clock selected */ - MRCC->CLKCTL &= MRCC_CKUSB_Internal; - } - else - { - /* PLL not enabled */ - return ERROR; - } - } - - return SUCCESS; -} - -/******************************************************************************* -* Function Name : MRCC_ITConfig -* Description : Enables or disables the specified MRCC interrupts. -* Input : - MRCC_IT: specifies the MRCC interrupts sources to be -* enabled or disabled. This parameter can be any combination -* of the following values: -* - MRCC_IT_LOCK: PLL lock interrupt -* - MRCC_IT_NCKD: No Clock detected interrupt -* - NewState: new state of the MRCC interrupts. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void MRCC_ITConfig(u32 MRCC_IT, FunctionalState NewState) -{ - if(NewState == ENABLE) - { - MRCC->CLKCTL |= MRCC_IT; - } - else - { - MRCC->CLKCTL &= ~MRCC_IT; - } -} - -/******************************************************************************* -* Function Name : MRCC_PeripheralClockConfig -* Description : Enables or disables the specified peripheral clock. -* Input : - MRCC_Peripheral: specifies the peripheral to gates its -* clock. More than one peripheral can be selected using -* the “|” operator. -* - NewState: new state of the specified peripheral clock. -* This parameter can be one of the following values: -* - ENABLE: the selected peripheral clock is enabled -* - DISABLE: the selected peripheral clock is disabled -* Output : None -* Return : None -*******************************************************************************/ -void MRCC_PeripheralClockConfig(u32 MRCC_Peripheral, FunctionalState NewState) -{ - if(NewState == ENABLE) - { - MRCC->PCLKEN |= MRCC_Peripheral; - } - else - { - MRCC->PCLKEN &= ~MRCC_Peripheral; - } -} - -/******************************************************************************* -* Function Name : MRCC_PeripheralSWResetConfig -* Description : Forces or releases peripheral software reset. -* Input : - MRCC_Peripheral: specifies the peripheral to reset. More -* than one peripheral can be selected using the “|” operator. -* - NewState: new state of the specified peripheral software -* reset. This parameter can be one of the following values: -* - ENABLE: the selected peripheral is kept under reset -* - DISABLE: the selected peripheral exits from reset -* Output : None -* Return : None -*******************************************************************************/ -void MRCC_PeripheralSWResetConfig(u32 MRCC_Peripheral, FunctionalState NewState) -{ - if(NewState == ENABLE) - { - MRCC->PSWRES |= MRCC_Peripheral; - } - else - { - MRCC->PSWRES &= ~MRCC_Peripheral; - } -} - -/******************************************************************************* -* Function Name : MRCC_GetClocksStatus -* Description : Returns the status and frequencies of different on chip clocks. -* Don’t use this function when CK_SYS is clocked by an external -* clock source (OSC4M bypassed). -* Input : - MRCC_ClocksStatus: pointer to a MRCC_ClocksTypeDef structure -* which will hold the clocks information. -* Output : None -* Return : None -*******************************************************************************/ -void MRCC_GetClocksStatus(MRCC_ClocksTypeDef* MRCC_ClocksStatus) -{ - u32 PLLMul = 0; - u32 Temp = 0; - u32 Presc = 0; - - /* Get the Status of PLL */ - if((MRCC->CLKCTL & MRCC_PLLEN_Set_Mask) == RESET) - { - MRCC_ClocksStatus->PLL_Status = OFF; - } - else - { - MRCC_ClocksStatus->PLL_Status = ON; - } - - /* Get the Status of OSC4M */ - if((MRCC->CLKCTL & MRCC_OSC4MOFF_Set_Mask) == RESET) - { - MRCC_ClocksStatus->OSC4M_Status = ON; - } - else - { - MRCC_ClocksStatus->OSC4M_Status = OFF; - } - - /* Get the Status of LPOSC */ - if((MRCC->PWRCTRL & MRCC_LPOSCEN_Mask) == RESET) - { - MRCC_ClocksStatus->LPOSC_Status = OFF; - } - else - { - MRCC_ClocksStatus->LPOSC_Status = ON; - } - - /* Get the Status of OSC32K */ - if((MRCC->PWRCTRL & MRCC_OSC32KEN_Mask) == RESET) - { - MRCC_ClocksStatus->OSC32K_Status = OFF; - } - else - { - MRCC_ClocksStatus->OSC32K_Status = ON; - } - -/* Get CKU_SB source ---------------------------------------------------------*/ - if((MRCC->CLKCTL & MRCC_CKUSBSEL_Mask) != RESET) - { - MRCC_ClocksStatus->CKUSB_Source = External; - } - else - { - if((MRCC->CLKCTL & MRCC_PLL2EN_Set_Mask) != RESET) - { - MRCC_ClocksStatus->CKUSB_Source = Internal; - - } - else - { - MRCC_ClocksStatus->CKUSB_Source = Disabled; - } - } - -/* Get CK_RTC source ---------------------------------------------------------*/ - Temp = MRCC->PWRCTRL & MRCC_CKRTCSEL_Set_Mask; - Temp = Temp >> 24; - - switch(Temp) - { - case 0x00: - MRCC_ClocksStatus->CKRTC_Source = Disabled; - break; - - case 0x01: - MRCC_ClocksStatus->CKRTC_Source = OSC4M_Div128; - break; - - case 0x02: - MRCC_ClocksStatus->CKRTC_Source = OSC32K; - break; - - case 0x03: - MRCC_ClocksStatus->CKRTC_Source = LPOSC; - break; - - default: - MRCC_ClocksStatus->CKRTC_Source = Disabled; - break; - } - -/* Get CK_SYS source ---------------------------------------------------------*/ - if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET) - {/* CK_OSC used as CK_SYS clock source */ - - if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) - { /* CK_RTC used as CK_OSC clock source */ - MRCC_ClocksStatus->CKSYS_Source = CKRTC; - - if(MRCC_ClocksStatus->CKRTC_Source == OSC32K) - { - /* CK_SYS clock frequency */ - MRCC_ClocksStatus->CKSYS_Frequency = OSC32K_Value; - } - else if(MRCC_ClocksStatus->CKRTC_Source == LPOSC) - - { - /* CK_SYS clock frequency */ - MRCC_ClocksStatus->CKSYS_Frequency = LPOSC_Value; - } - else if(MRCC_ClocksStatus->CKRTC_Source == OSC4M_Div128) - - { - /* CK_SYS clock frequency */ - MRCC_ClocksStatus->CKSYS_Frequency = OSC4M_Div128_Value; - } - } - else - { /* OSC4M used as CK_OSC clock source */ - MRCC_ClocksStatus->CKSYS_Source = OSC4M; - - if((MRCC->CLKCTL & MRCC_XTDIV2_Set_Mask) != RESET) - { - /* CK_SYS clock frequency */ - MRCC_ClocksStatus->CKSYS_Frequency = Main_Oscillator >> 1; - } - else - { - /* CK_SYS clock frequency */ - MRCC_ClocksStatus->CKSYS_Frequency = Main_Oscillator; - } - } - } - else - {/* CK_PLL1 used as CK_SYS clock */ - - if(MRCC_ClocksStatus->PLL_Status == OFF) - { /* FREEOSC used as CK_PLL1 clock source */ - MRCC_ClocksStatus->CKSYS_Source = FREEOSC; - - /* CK_SYS clock frequency */ - MRCC_ClocksStatus->CKSYS_Frequency = FREEOSC_Value; - } - else - { /* OSC4M followed by PLL used as CK_PLL1 clock source */ - MRCC_ClocksStatus->CKSYS_Source = OSC4MPLL; - - /* Get PLL factor ------------------------------------------------------*/ - Temp = MRCC->CLKCTL & MRCC_MX_Set_Mask; - Temp = Temp >> 27; - - switch(Temp) - { - case 0x00: - PLLMul = 16; - break; - - case 0x01: - PLLMul = 15; - break; - - case 0x02: - PLLMul = 14; - break; - - case 0x03: - PLLMul = 12; - break; - - default: - PLLMul = 16; - break; - } - - /* CK_SYS clock frequency */ - MRCC_ClocksStatus->CKSYS_Frequency = OSC4M_Value * PLLMul; - } - } - -/* Compute HCLK, CKTIM and PCLK clocks frequencies ---------------------------*/ - /* Get HCLK prescaler */ - Presc = MRCC->CLKCTL & MRCC_HPRESC_Set_Mask; - Presc = Presc >> 3; - /* HCLK clock frequency */ - MRCC_ClocksStatus->HCLK_Frequency = MRCC_ClocksStatus->CKSYS_Frequency >> Presc; - - /* Get CK_TIM prescaler */ - Presc = MRCC->CLKCTL & MRCC_PPRESC_Set_Mask; - /* CK_TIM clock frequency */ - MRCC_ClocksStatus->CKTIM_Frequency = MRCC_ClocksStatus->HCLK_Frequency >> Presc; - - /* Get PCLK prescaler */ - Presc = MRCC->CLKCTL & MRCC_PPRESC2_Mask; - Presc = Presc >> 2; - /* PCLK clock frequency */ - MRCC_ClocksStatus->PCLK_Frequency = MRCC_ClocksStatus->CKTIM_Frequency >> Presc; -} - -/******************************************************************************* -* Function Name : MRCC_LPMC_DBGonfig -* Description : Enables or disables the Low Power Debug Mode. -* Input : - MRCC_LPDM: specifies the LPDM new state value. -* This parameter can be one of the following values: -* - MRCC_LPDM_Disable -* - MRCC_LPDM_Enable -* Output : None -* Return : None -*******************************************************************************/ -void MRCC_LPMC_DBGConfig(u32 MRCC_LPDM) -{ - if(MRCC_LPDM == MRCC_LPDM_Enable) - { - MRCC->PWRCTRL |= MRCC_LPDM_Enable; - } - else - { - MRCC->PWRCTRL &= MRCC_LPDM_Disable; - } -} - -/******************************************************************************* -* Function Name : MRCC_EnterWFIMode -* Description : Enters WFI mode. -* If the Flash is used in Burst mode, it must be kept enabled -* in WFI mode(use MRCC_WFIParam_FLASHOn as parameter) -* Input : - MRCC_WFIParam: specifies the WFI mode control parameters. -* This parameter can be one of the following values: -* - MRCC_WFIParam_FLASHPowerDown(DMA not allowed during WFI) -* - MRCC_WFIParam_FLASHOn(DMA allowed during WFI) -* - MRCC_WFIParam_FLASHOff(DMA not allowed during WFI) -* Output : None -* Return : None -*******************************************************************************/ -void MRCC_EnterWFIMode(u32 MRCC_WFIParam) -{ -/* Low Power mode configuration ----------------------------------------------*/ - /* Clear LPMC[1:0] bits */ - MRCC->PWRCTRL &= MRCC_LPMC_Reset_Mask; - - /* Select WFI mode */ - MRCC->PWRCTRL |= MRCC_WFI_Mask; - -/* Low Power mode control parameters configuration ---------------------------*/ - /* Clear LP_PARAM[15:13] and WFI_FLASH_EN bits */ - MRCC->PWRCTRL &= MRCC_WFIParam_Reset_Mask; - - if(MRCC_WFIParam != MRCC_WFIParam_FLASHPowerDown) - { - /* Set LP_PARAM[15:13] and WFI_FLASH_EN bits according to MRCC_WFIParam value */ - MRCC->PWRCTRL |= MRCC_WFIParam; - } - -/* Execute the Low Power bit writing sequence --------------------------------*/ - WriteLPBit(); -} - -/******************************************************************************* -* Function Name : MRCC_EnterSTOPMode -* Description : Enters STOP mode. -* Input : - MRCC_STOPParam: specifies the STOP mode control parameters. -* This parameter can be one of the following values: -* - MRCC_STOPParam_Default (OSC4M On, FLASH On, MVREG On) -* - MRCC_STOPParam_OSC4MOff -* - MRCC_STOPParam_FLASHOff -* - MRCC_STOPParam_MVREGOff -* Output : None -* Return : None -*******************************************************************************/ -void MRCC_EnterSTOPMode(u32 MRCC_STOPParam) -{ -/* Low Power mode configuration ----------------------------------------------*/ - /* Clear LPMC[1:0] bits (STOP mode is selected) */ - MRCC->PWRCTRL &= MRCC_LPMC_Reset_Mask; - -/* Low Power mode control parameters configuration ---------------------------*/ - /* Clear LP_PARAM[15:13] bits */ - MRCC->PWRCTRL &= MRCC_LPPARAM_Reset_Mask; - - if(MRCC_STOPParam != MRCC_STOPParam_Default) - { - /* Set LP_PARAM[15:13] bits according to MRCC_STOPParam value */ - MRCC->PWRCTRL |= MRCC_STOPParam; - } - -/* Execute the Low Power bit writing sequence --------------------------------*/ - WriteLPBit(); -} - -/******************************************************************************* -* Function Name : MRCC_EnterSTANDBYMode -* Description : Enters STANDBY mode. -* Make sure that WKPF flag is cleared before using this function. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void MRCC_EnterSTANDBYMode(void) -{ -/* Low Power mode configuration ----------------------------------------------*/ - /* Clear LPMC[1:0] bits */ - MRCC->PWRCTRL &= MRCC_LPMC_Reset_Mask; - - /* Select STANDBY mode */ - MRCC->PWRCTRL |= MRCC_STANDBY_Mask; - -/* Execute the Low Power bit writing sequence --------------------------------*/ - WriteLPBit(); -} - -/******************************************************************************* -* Function Name : MRCC_GenerateSWReset -* Description : Generates a system software reset. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void MRCC_GenerateSWReset(void) -{ -/* Low Power mode configuration ----------------------------------------------*/ - /* Clear LPMC[1:0] bits */ - MRCC->PWRCTRL &= MRCC_LPMC_Reset_Mask; - - /* Select software reset */ - MRCC->PWRCTRL |= MRCC_SWRESET_Mask; - -/* Execute the Low Power bit writing sequence --------------------------------*/ - WriteLPBit(); -} - -/******************************************************************************* -* Function Name : MRCC_WriteBackupRegister -* Description : Writes user data to the specified backup register. -* Input : - MRCC_BKP: specifies the backup register. -* This parameter can be one of the following values: -* - MRCC_BKP0 -* - MRCC_BKP1 -* - Data: data to write. -* Output : None -* Return : None -*******************************************************************************/ -void MRCC_WriteBackupRegister(MRCC_BKPReg MRCC_BKP, u32 Data) -{ - if(MRCC_BKP == MRCC_BKP0) - { - MRCC->BKP0 = Data; - } - else - { - MRCC->BKP1 = Data; - } -} - -/******************************************************************************* -* Function Name : MRCC_ReadBackupRegister -* Description : Reads data from the specified backup register. -* Input : - MRCC_BKP: specifies the backup register. -* This parameter can be one of the following values: -* - MRCC_BKP0 -* - MRCC_BKP1 -* Output : None -* Return : The content of the specified backup register. -*******************************************************************************/ -u32 MRCC_ReadBackupRegister(MRCC_BKPReg MRCC_BKP) -{ - if(MRCC_BKP == MRCC_BKP0) - { - return(MRCC->BKP0); - } - else - { - return(MRCC->BKP1); - } -} - -/******************************************************************************* -* Function Name : MRCC_IOVoltageRangeConfig -* Description : Configures the I/O pins voltage range. -* Input : - MRCC_IOVoltageRange: specifies the I/O pins voltage range. -* This parameter can be one of the following values: -* - MRCC_IOVoltageRange_5V -* - MRCC_IOVoltageRange_3V3 -* Output : None -* Return : None -*******************************************************************************/ -void MRCC_IOVoltageRangeConfig(u32 MRCC_IOVoltageRange) -{ - if(MRCC_IOVoltageRange == MRCC_IOVoltageRange_3V3) - { - MRCC->PWRCTRL |= MRCC_IOVoltageRange_3V3; - } - else - { - MRCC->PWRCTRL &= MRCC_IOVoltageRange_5V; - } -} - -/******************************************************************************* -* Function Name : MRCC_MCOConfig -* Description : Selects the clock source to output on MCO pin (P0.1). -* To output the clock, the associated alternate function must -* be enabled in the I/O port controller. -* Input : - MRCC_MCO: specifies the clock source to output. -* This parameter can be one of the following values: -* - MRCC_MCO_HCLK -* - MRCC_MCO_PCLK -* - MRCC_MCO_OSC4M -* - MRCC_MCO_CKPLL2 -* - MRCC_MCOPrescaler: specifies if prescaler, divide by 1 or 2, -* is applied to this clock before outputting it to MCO pin. -* This parameter can be one of the following values: -* - MRCC_MCOPrescaler_1 -* - MRCC_MCOPrescaler_2 -* Output : None -* Return : None -*******************************************************************************/ -void MRCC_MCOConfig(u32 MRCC_MCO, u32 MCO_MCOPrescaler) -{ - u32 Temp = 0; -/* MCO prescaler configuration -----------------------------------------------*/ - if(MCO_MCOPrescaler == MRCC_MCOPrescaler_2) - { - MRCC->CLKCTL |= MRCC_MCOPrescaler_2; - } - else - { - MRCC->CLKCTL &= MRCC_MCOPrescaler_1; - } - -/* MCO selection configuration -----------------------------------------------*/ - - /* Clear MCOS[1:0] bits */ - Temp = MRCC->CLKCTL & MRCC_MCOS_Reset_Mask; - - /* Set MCOS[1:0] bits according to MRCC_MCO value */ - Temp |= MRCC_MCO; - - /* Store the new value */ - MRCC->CLKCTL = Temp; -} - -/******************************************************************************* -* Function Name : MRCC_OSC4MConfig -* Description : Configures the 4MHz main oscillator (OSC4M). -* This function must be used when the CK_SYS is not clocked -* by the OSC4M and the PLL is not enabled. -* Input : - MRCC_OSC4M: specifies the new state of the OSC4M oscillator. -* This parameter can be one of the following values: -* - MRCC_OSC4M_Default: OSC4M enabled, bypass disabled -* - MRCC_OSC4M_Disable: OSC4M disabled -* - MRCC_OSC4M_Bypass: OSC4M bypassed -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Clock configuration succeeded -* - ERROR: Clock configuration failed -*******************************************************************************/ -ErrorStatus MRCC_OSC4MConfig(u32 MRCC_OSC4M) -{ - ErrorStatus Status = SUCCESS; - -/* If CK_SYS is driven by OSC4M or the PLL is enabled, exit ------------------*/ - if(((MRCC->CLKCTL & MRCC_CKSEL_CKOSCSEL_Mask) == MRCC_CKSEL_Set_Mask) || - (((MRCC->CLKCTL & MRCC_CKSEL_CKOSCSEL_Mask) == MRCC_CKSEL_CKOSCSEL_Mask) && - ((MRCC->PWRCTRL & MRCC_CKRTCSEL_Reset_Mask) != RESET))|| - ((MRCC->CLKCTL & MRCC_PLLEN_Set_Mask) != RESET)) - { - Status = ERROR; - } -/* Else configure the OSC4MOFF and OSC4MBYP bits -----------------------------*/ - else - { - switch(MRCC_OSC4M) - { - case MRCC_OSC4M_Default: - MRCC->CLKCTL &= MRCC_OSC4MOFF_Reset_Mask & MRCC_OSC4MBYP_Reset_Mask; - break; - - case MRCC_OSC4M_Disable: - MRCC->CLKCTL &= MRCC_OSC4MBYP_Reset_Mask; - MRCC->CLKCTL |= MRCC_OSC4MOFF_Set_Mask; - break; - - case MRCC_OSC4M_Bypass: - MRCC->CLKCTL &= MRCC_OSC4MOFF_Reset_Mask; - MRCC->CLKCTL |= MRCC_OSC4MBYP_Set_Mask; - break; - - default: - Status = ERROR; - break; - } - } - - return Status; -} - -/******************************************************************************* -* Function Name : MRCC_OSC32KConfig -* Description : Configures the OSC32K oscillator. -* This function must be used when the CK_SYS is not clocked by -* the CK_RTC. -* Input : - MRCC_OSC32K: specifies the new state of the OSC32K oscillator. -* This parameter can be one of the following values: -* - MRCC_OSC32K_Disable: OSC32K disabled -* - MRCC_OSC32K_Enable: OSC32K enabled -* - MRCC_OSC32KBypass: specifies if the OSC32K oscillator is -* bypassed or not. -* This parameter can be one of the following values: -* - MRCC_OSC32KBypass_Disable: OSC32K selected -* - MRCC_OSC32KBypass_Enable: OSC32K bypassed -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Clock configuration succeeded -* - ERROR: Clock configuration failed -*******************************************************************************/ -ErrorStatus MRCC_OSC32KConfig(u32 MRCC_OSC32K, u32 MRCC_OSC32KBypass) -{ -/* If CK_SYS is driven by CK_RTC, exit ---------------------------------------*/ - if(((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET) && - ((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET)) - { - return ERROR; - } -/* Else configure the OSC32KEN and OSC32KBYP bits ----------------------------*/ - else - { - /* Configure OSC32KEN bit */ - if(MRCC_OSC32K == MRCC_OSC32K_Enable) - { - MRCC->PWRCTRL |= MRCC_OSC32K_Enable; - } - else - { - MRCC->PWRCTRL &= MRCC_OSC32K_Disable; - } - - /* Configure OSC32KBYP bit */ - if(MRCC_OSC32KBypass == MRCC_OSC32KBypass_Enable) - { - MRCC->PWRCTRL |= MRCC_OSC32KBypass_Enable; - } - else - { - MRCC->PWRCTRL &= MRCC_OSC32KBypass_Disable; - } - - return SUCCESS; - } -} - -/******************************************************************************* -* Function Name : MRCC_LPOSCConfig -* Description : Enables or disables the LPOSC oscillator. -* This function must be used when the CK_SYS is not clocked by -* the CK_RTC. -* Input : - MRCC_LPOSC: specifies the new state of the LPOSC oscillator. -* This parameter can be one of the following values: -* - MRCC_LPOSC_Disable: LPOSC disabled -* - MRCC_LPOSC_Enable: LPOSC enabled -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Clock configuration succeeded -* - ERROR: Clock configuration failed -*******************************************************************************/ -ErrorStatus MRCC_LPOSCConfig(u32 MRCC_LPOSC) -{ -/* If CK_SYS is driven by CK_RTC or LPOSC is used as CK_RTC clock source, exit*/ - if((((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET) && - ((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET)) || - ((MRCC->PWRCTRL & MRCC_CKRTCSEL_Set_Mask) == MRCC_CKRTC_LPOSC)) - { - return ERROR; - } -/* Else configure the LPOSCEN bit --------------------------------------------*/ - else - { - if(MRCC_LPOSC == MRCC_LPOSC_Enable) - { - MRCC->PWRCTRL |= MRCC_LPOSC_Enable; - } - else - { - MRCC->PWRCTRL &= MRCC_LPOSC_Disable; - } - - return SUCCESS; - } -} - -/******************************************************************************* -* Function Name : MRCC_RTCMConfig -* Description : Enables or disables RTC clock measurement. -* Input : - MRCC_RTCM: specifies whether CK_RTC is connected to TB -* timer IC1 or not. -* This parameter can be one of the following values: -* - MRCC_RTCM_Disable: CK_RTC not connected to TB timer IC1 -* - MRCC_RTCM_Enable: CK_RTC connected to TB timer IC1 -* Output : None -* Return : None -*******************************************************************************/ -void MRCC_RTCMConfig(u32 MRCC_RTCM) -{ - if(MRCC_RTCM == MRCC_RTCM_Enable) - { - MRCC->PWRCTRL |= MRCC_RTCM_Enable; - } - else - { - MRCC->PWRCTRL &= MRCC_RTCM_Disable; - } -} - -/******************************************************************************* -* Function Name : MRCC_SetBuilderCounter -* Description : Sets the builder counter value which defines the delay for -* the 4MHz main oscillator (OSC4M) clock to be stabilized. -* Input : - BuilderCounter: defines the delay for the OSC4M oscillator -* clock to be stabilized. -* Output : None -* Return : None -*******************************************************************************/ -void MRCC_SetBuilderCounter(u8 BuilderCounter) -{ - *(u8 *) 0x60000026 = BuilderCounter; -} - -/******************************************************************************* -* Function Name : MRCC_GetCKSYSCounter -* Description : Gets the result of the delay applied to CK_SYS before -* starting the CPU. -* Input : None -* Output : None -* Return : SCOUNT value. -*******************************************************************************/ -u16 MRCC_GetCKSYSCounter(void) -{ - return((u16)(MRCC->RFSR & 0x0FFF)); -} - -/******************************************************************************* -* Function Name : MRCC_GetFlagStatus -* Description : Checks whether the specified MRCC flag is set or not. -* Input : - MRCC_FLAG: specifies the flag to check. -* This parameter can be one of the following values: -* - MRCC_FLAG_LOCK: PLL Locked flag -* - MRCC_FLAG_LOCKIF: PLL Lock Interrupt status flag -* - MRCC_FLAG_CKSEL: CK_SYS source staus flag -* - MRCC_FLAG_CKOSCSEL: CK_OSC clock source staus flag -* - MRCC_FLAG_NCKD: No Clock Detected flag -* - MRCC_FLAG_SWR: Software Reset flag -* - MRCC_FLAG_WDGR: Watchdog Reset flag -* - MRCC_FLAG_EXTR: External Reset flag -* - MRCC_FLAG_WKP: Wake-Up flag -* - MRCC_FLAG_STDB: STANDBY flag -* - MRCC_FLAG_BCOUNT: Builder Counter Flag -* - MRCC_FLAG_OSC32KRDY: Oscillator 32K Ready -* - MRCC_FLAG_CKRTCOK: CK_RTC OK -* - MRCC_FLAG_LPDONE: Low Power Bit Sequence has been performed -* - MRCC_FLAG_LP: Low Power Mode Entry -* Output : None -* Return : The new state of MRCC_FLAG (SET or RESET). -*******************************************************************************/ -FlagStatus MRCC_GetFlagStatus(u8 MRCC_FLAG) -{ - u32 MRCCReg = 0, FlagPos = 0; - u32 StatusReg = 0; - - /* Get the MRCC register index */ - MRCCReg = MRCC_FLAG >> 5; - - /* Get the flag position */ - FlagPos = MRCC_FLAG & MRCC_FLAG_Mask; - - if(MRCCReg == 1) /* The flag to check is in CLKCTL register */ - { - StatusReg = MRCC->CLKCTL; - } - else if (MRCCReg == 2) /* The flag to check is in RFSR register */ - { - StatusReg = MRCC->RFSR; - } - else if(MRCCReg == 3) /* The flag to check is in PWRCTRL register */ - { - StatusReg = MRCC->PWRCTRL; - } - - if((StatusReg & (1 << FlagPos))!= RESET) - { - return SET; - } - else - { - return RESET; - } -} - -/******************************************************************************* -* Function Name : MRCC_ClearFlag -* Description : Clears the MRCC’s pending flags. -* Input : - MRCC_FLAG: specifies the flag to clear. -* This parameter can be one of the following values: -* - MRCC_FLAG_NCKD: No Clock Detected flag -* - MRCC_FLAG_SWR: Software Reset flag -* - MRCC_FLAG_WDGR: Watchdog Reset flag -* - MRCC_FLAG_EXTR: External Reset flag -* - MRCC_FLAG_WKP: Wake-Up flag -* - MRCC_FLAG_STDB: STANDBY flag -* - MRCC_FLAG_LPDONE: Low Power Bit Sequence has been performed -* Output : None -* Return : None -*******************************************************************************/ -void MRCC_ClearFlag(u8 MRCC_FLAG) -{ - u32 MRCCReg = 0, FlagPos = 0; - - /* Get the MRCC register index */ - MRCCReg = MRCC_FLAG >> 5; - - /* Get the flag position */ - FlagPos = MRCC_FLAG & MRCC_FLAG_Mask; - - if(MRCCReg == 1) /* The flag to clear is in CLKCTL register */ - { - MRCC->CLKCTL &= ~(1 << FlagPos); - } - else if (MRCCReg == 2) /* The flag to clear is in RFSR register */ - { - MRCC->RFSR &= ~(1 << FlagPos); - } - else if(MRCCReg == 3) /* The flag to clear is in PWRCTRL register */ - { - MRCC->PWRCTRL &= ~(1 << FlagPos); - } -} - -/******************************************************************************* -* Function Name : MRCC_GetITStatus -* Description : Checks whether the specified MRCC interrupt has occurred or not. -* Input : - MRCC_IT: specifies the MRCC interrupt source to check. -* This parameter can be one of the following values: -* - MRCC_IT_LOCK: PLL lock interrupt -* - MRCC_IT_NCKD: No Clock detected interrupt -* Output : None -* Return : The new state of MRCC_IT (SET or RESET). -*******************************************************************************/ -ITStatus MRCC_GetITStatus(u32 MRCC_IT) -{ - /* Check the specified interrupt pending bit */ - if((MRCC->CLKCTL & (MRCC_IT >> 1)) != RESET) - { - return SET; - } - else - { - return RESET; - } -} - -/******************************************************************************* -* Function Name : MRCC_ClearITPendingBit -* Description : Clears the MRCC’s interrupt pending bits. -* Input : - MRCC_IT: specifies the interrupt pending bit to clear. -* This parameter can be any combination of the following -* values: -* - MRCC_IT_LOCK: PLL lock interrupt -* - MRCC_IT_NCKD: No Clock detected interrupt -* Output : None -* Return : None -*******************************************************************************/ -void MRCC_ClearITPendingBit(u32 MRCC_IT) -{ - /* Clear the specified interrupt pending bit */ - MRCC->CLKCTL &= ~(MRCC_IT >> 1); -} - -/******************************************************************************* -* Function Name : MRCC_WaitForOSC4MStartUp -* Description : Waits for OSC4M start-up. -* Input : None -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: OSC4M oscillator is stable and ready to use -* - ERROR: no clock is detected on OSC4M -*******************************************************************************/ -ErrorStatus MRCC_WaitForOSC4MStartUp(void) -{ - u32 StartUpCounter = 0; - - do - { - /* Clear No Clock Detected flag */ - if(MRCC_GetFlagStatus(MRCC_FLAG_NCKD) != RESET) - { - MRCC_ClearFlag(MRCC_FLAG_NCKD); - } - - StartUpCounter++; - - }while((MRCC_GetFlagStatus(MRCC_FLAG_BCOUNT) == RESET)&& - (StartUpCounter != OSC4MStartUp_TimeOut)); - - if(MRCC_GetFlagStatus(MRCC_FLAG_BCOUNT) != RESET) - { - return SUCCESS; - } - else - { - return ERROR; - } -} - -/******************************************************************************* -* Function Name : SetCKSYS_FREEOSC -* Description : Selects FREEOSC as CK_SYS clock source. -* Input : None -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Clock configuration succeeded -* - ERROR: Clock configuration failed -*******************************************************************************/ -static ErrorStatus SetCKSYS_FREEOSC(void) -{ - /* Check if the PLL is enabled */ - if((MRCC->CLKCTL & MRCC_PLLEN_Set_Mask) != RESET) - { - if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) == RESET) - { /* CK_PLL1 used as Ck_SYS clock source*/ - - if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) - {/* Check if CK_RTC source clock is present*/ - if((MRCC->PWRCTRL & MRCC_CKRTCSEL_Set_Mask) == RESET) - { - /* CK_RTC disabled*/ - return ERROR; - } - } - - /* Select CK_OSC as CK_SYS clock source */ - MRCC->CLKCTL |= MRCC_CKSEL_Set_Mask; - } - - /* Disable PLL */ - MRCC->CLKCTL &= MRCC_PLLEN_Reset_Mask; - } - - /* Select CK_PLL1 as CK_SYS clock source */ - MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask; - - if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) == RESET) - { - return SUCCESS; - } - else - { - return ERROR; - } -} - -/******************************************************************************* -* Function Name : SetCKSYS_OSC4M -* Description : Selects 4MHz main oscillator (OSC4M) as CK_SYS clock source. -* Input : PLL_State: specifies the PLL state. -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Clock configuration succeeded -* - ERROR: Clock configuration failed -*******************************************************************************/ -static ErrorStatus SetCKSYS_OSC4M(u32 PLL_State) -{ -/* If OSC4M is not present, exit ---------------------------------------------*/ - if(((MRCC->CLKCTL & MRCC_NCKDF_Set_Mask) != RESET) || - ((MRCC->CLKCTL & MRCC_OSC4MOFF_Set_Mask) != RESET) ) - { - /* OSC4M disabled or OSC4M clock is not present*/ - return ERROR; - } - -/* Else configure CKSEL and CKOSCSEL bits ------------------------------------*/ - if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) - { /* CK_RTC used as CK_OSC clock */ - - if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET) - { - /* Select CK_PLL1 as CK_SYS clock source */ - MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask; - } - - /* Clear CKOSCSEL bit ----------------------------------------------------*/ - /* Execute CKOSCSEL bit writing sequence */ - WriteCKOSCSELBit(); - - /* Check if CKOSCSEL is set to 0 */ - if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) - { - return ERROR; - } - } - - /* Select CK_OSC as CK_SYS clock source */ - MRCC->CLKCTL |= MRCC_CKSEL_Set_Mask; - - if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET) - { - if(PLL_State == MRCC_PLL_Disabled) - { - /* Disable PLL */ - MRCC->CLKCTL &= MRCC_PLLEN_Reset_Mask; - } - - return SUCCESS; - } - else - { - return ERROR; - } -} - -/******************************************************************************* -* Function Name : SetCKSYS_OSC4MPLL -* Description : Selects 4MHz main oscillator (OSC4M) followed by PLL as -* CK_SYS clock source. -* Input : PLL_Mul: specifies the PLL factor. -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Clock configuration succeeded -* - ERROR: Clock configuration failed -*******************************************************************************/ -static ErrorStatus SetCKSYS_OSC4MPLL(u32 PLL_Mul) -{ - /* Check if 4MHz main oscillator clock is present */ - if(((MRCC->CLKCTL & MRCC_NCKDF_Set_Mask) == RESET) && - ((MRCC->CLKCTL & MRCC_OSC4MOFF_Set_Mask) == RESET)) - { - if(((MRCC->CLKCTL & MRCC_PLLEN_Set_Mask) != RESET) && - ((MRCC->CLKCTL & MRCC_MX_Set_Mask) == PLL_Mul)) - { - /* Select CK_PLL1 as CK_SYS clock source */ - MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask; - - if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) == RESET) - { - return SUCCESS; - } - else - { - return ERROR; - } - } - else - { - /* If CK_RTC is selected as CK_OSC clock source */ - if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) - { - if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET) - { - /* Clear CKSEL bit */ - MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask; - } - - /* Clear CKOSCSEL bit ------------------------------------------------*/ - /* Execute CKOSCSEL bit writing sequence */ - WriteCKOSCSELBit(); - - /* Check if CKOSCSEL is set to 0 */ - if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) - { - return ERROR; - } - } - - /* Select CK_OSC as CK_SYS clock source */ - MRCC->CLKCTL |= MRCC_CKSEL_Set_Mask; - - /* Disable PLL */ - MRCC->CLKCTL &= MRCC_PLLEN_Reset_Mask; - - /* Configure PLL factor */ - if(PLL_Mul == MRCC_PLL_Mul_16) - { - MRCC->CLKCTL &= MRCC_MX_Reset_Mask; - } - else if((PLL_Mul == MRCC_PLL_Mul_15) || (PLL_Mul == MRCC_PLL_Mul_14) || - (PLL_Mul == MRCC_PLL_Mul_12)) - { - /* Clear MX[1:0] bits */ - MRCC->CLKCTL &= MRCC_MX_Reset_Mask; - /* Set MX[1:0] bits according to PLL_Mul value */ - MRCC->CLKCTL |= PLL_Mul; - } - - if(Main_Oscillator == 4000000) - {/* 4 MHz external Quartz oscillator used as main oscillator */ - /* Disable Oscillator Divider by 2 */ - MRCC->CLKCTL &= MRCC_XTDIV2_Reset_Mask; - } - else if(Main_Oscillator == 8000000) - {/* 8 MHz external Quartz oscillator used as main oscillator */ - /* Enable Oscillator Divider by 2 */ - MRCC->CLKCTL |= MRCC_XTDIV2_Set_Mask; - } - - /* Enable PLL */ - MRCC->CLKCTL |= MRCC_PLLEN_Set_Mask; - - /* Wait until the PLL is locked */ - while((MRCC->CLKCTL & MRCC_LOCK_Mask) == RESET) - { - /* If OSC4M clock disapear or the PLL is disabled, exit */ - if(((MRCC->CLKCTL & MRCC_NCKDF_Set_Mask) != RESET) || - ((MRCC->CLKCTL & MRCC_PLLEN_Set_Mask) == RESET)) - { - return ERROR; - } - } - - /* Select CK_PLL1 as CK_SYS clock source */ - MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask; - - if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) == RESET) - { - return SUCCESS; - } - else - { - return ERROR; - } - } - } - else - { - /* OSC4M disabled or OSC4M clock is not present*/ - return ERROR; - } -} - -/******************************************************************************* -* Function Name : SetCKSYS_RTC -* Description : Selects RTC clock (CK_RTC) as CK_SYS clock source. -* Input : PLL_State: specifies the PLL state. -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Clock configuration succeeded -* - ERROR: Clock configuration failed -*******************************************************************************/ -static ErrorStatus SetCKSYS_RTC(u32 PLL_State) -{ - /* Check if CK_RTC clock is enabled and ready to use */ - if(((MRCC->PWRCTRL & MRCC_CKRTCSEL_Set_Mask) != RESET)|| - ((MRCC->CLKCTL & MRCC_CKRTCOK_Mask) == RESET)) - { -/* Configure CK_RTC as Ck_SYS clock source -----------------------------------*/ - if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) == RESET) - { - /* Select CK_PLL1 as CK_SYS clock source */ - MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask; - - /* Set CKOSCSEL bit ----------------------------------------------------*/ - /* Execute CKOSCSEL bit writing sequence */ - WriteCKOSCSELBit(); - - /* Check if CKOSCSEL is set to 1 */ - if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) == RESET) - { - return ERROR; - } - } - - /* Select CK_OSC as CK_SYS clock source */ - MRCC->CLKCTL |= MRCC_CKSEL_Set_Mask; - - if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET) - { - if(PLL_State == MRCC_PLL_Disabled) - { - /* Disable PLL */ - MRCC->CLKCTL &= MRCC_PLLEN_Reset_Mask; - } - - return SUCCESS; - } - else - { - return ERROR; - } - } - else - { - /* CK_RTC disabled */ - return ERROR; - } -} - -/******************************************************************************* -* Function Name : WriteLPBit -* Description : Executes the Low Power bit writing sequence. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -static void WriteLPBit(void) -{ - u32 Tmp = 0, Tmp1 = 0, Tmp2 = 0; - - /* Clear LP_DONE flag */ - MRCC->PWRCTRL &= MRCC_LPDONE_Reset_Mask; - - Tmp = MRCC->PWRCTRL; - Tmp1 = Tmp | MRCC_LP_Set_Mask; - Tmp2 = Tmp & MRCC_LP_Reset_Mask; - - /* Set LP bit */ - MRCC->PWRCTRL = Tmp1; - - /* Set LP bit */ - MRCC->PWRCTRL = Tmp1; - - /* Reset LP bit */ - MRCC->PWRCTRL = Tmp2; - - /* Set LP bit */ - MRCC->PWRCTRL = Tmp1; - - /* Read LP bit*/ - Tmp = MRCC->PWRCTRL; -} - -/******************************************************************************* -* Function Name : WriteCKOSCSELBit -* Description : Executes the CKOSCSEL bit writing sequence. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -static void WriteCKOSCSELBit(void) -{ - u32 Tmp = 0, Tmp1 = 0, Tmp2 = 0; - - Tmp = MRCC->CLKCTL; - Tmp1 = Tmp | MRCC_CKOSCSEL_Set_Mask; - Tmp2 = Tmp & MRCC_CKOSCSEL_Reset_Mask; - - /* Set CKOSCSEL bit */ - MRCC->CLKCTL = Tmp1; - - /* Set CKOSCSEL bit */ - MRCC->CLKCTL = Tmp1; - - /* Reset CKOSCSEL bit */ - MRCC->CLKCTL = Tmp2; - - /* Set CKOSCSEL bit */ - MRCC->CLKCTL = Tmp1; - - /* Read CKOSCSEL bit */ - Tmp = MRCC->CLKCTL; -} -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_pwm.c b/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_pwm.c deleted file mode 100644 index 79c15aa5b..000000000 --- a/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_pwm.c +++ /dev/null @@ -1,1153 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_pwm.c -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file provides all the PWM software functions. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -#include "75x_pwm.h" -#include "75x_mrcc.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* PWM interrupt masks */ -#define PWM_IT_Clear_Mask 0x7FFF -#define PWM_IT_Enable_Mask 0xEFFF - -/* PWM_CR Masks bit */ -#define PWM_CounterMode_Mask 0xFF8F -#define PWM_DBASE_Mask 0x077F -#define PWM_MasterModeSelection_Mask 0xFC7F - -/* PWM Update flag selection Set/Reset value */ -#define PWM_UFS_Reset 0xFFFE -#define PWM_UFS_Set 0x0001 - -/* PWM Counter value */ -#define PWM_COUNTER_Reset 0x0002 -#define PWM_COUNTER_Start 0x0004 -#define PWM_COUNTER_Stop 0xFFFB - -/* PWM Debug Mode Set/Reset value */ -#define PWM_DBGC_Set 0x0400 -#define PWM_DBGC_Reset 0xFBFF - -/* PWM Output Compare Polarity Set/Reset value */ -#define PWM_OC1P_Set 0x0020 -#define PWM_OC1P_Reset 0xFFDF - -#define PWM_OC1NP_Set 0x0080 -#define PWM_OC1NP_Reset 0xFF7F - -#define PWM_OC2P_Set 0x2000 -#define PWM_OC2P_Reset 0xDFFF - -#define PWM_OC2NP_Set 0x8000 -#define PWM_OC2NP_Reset 0x7FFF - -#define PWM_OC3P_Set 0x0020 -#define PWM_OC3P_Reset 0xFFDF - -#define PWM_OC3NP_Set 0x0080 -#define PWM_OC3NP_Reset 0xFF7F - -/* PWM Output Compare control mode constant */ -#define PWM_OCControl_PWM 0x000C -#define PWM_OCControl_OCToggle 0x0006 -#define PWM_OCControl_OCInactive 0x0004 -#define PWM_OCControl_OCActive 0x0002 -#define PWM_OCControl_OCTiming 0x0000 - -/* PWM Output Compare mode Enable value */ -#define PWM_OC1_Enable 0x0010 -#define PWM_OC2_Enable 0x1000 -#define PWM_OC3_Enable 0x0010 - -#define PWM_OC1_Disable 0xFFEF -#define PWM_OC2_Disable 0xEFFF -#define PWM_OC3_Disable 0xFFEF - -#define PWM_OC1N_Enable 0x0040 -#define PWM_OC2N_Enable 0x4000 -#define PWM_OC3N_Enable 0x0040 - -#define PWM_OC1N_Disable 0xFFBF -#define PWM_OC2N_Disable 0xBFFF -#define PWM_OC3N_Disable 0xFFBF - -/* PWM Output Compare mode Mask value */ -#define PWM_OC1C_Mask 0xFFF1 -#define PWM_OC2C_Mask 0xF1FF -#define PWM_OC3C_Mask 0xFFF1 - -/* PWM Preload bit Set/Reset value */ -#define PWM_PLD1_Set 0x0001 -#define PWM_PLD2_Set 0x0100 -#define PWM_PLD3_Set 0x0001 - -/* PWM OCRM Set/Reset value */ -#define PWM_OCMR_Set 0x0080 -#define PWM_OCMR_Reset 0xFF7F - -/* PWM_DTR bit Masks value */ -#define PWM_DTR_Mask 0xFC00 -#define PWM_LOCK_Mask 0xF3FF - -/* PWM MOE Set value */ -#define PWM_MOE_Set 0x8000 -#define PWM_MOE_Reset 0x7FFF - -/* PWM OSSR bit Set/Reset value */ -#define PWM_OSSR_Set 0x4000 -#define PWM_OSSR_Reset 0xBFFF - -/* Reset Register Masks */ -#define PWM_Prescaler_Reset_Mask 0x0000 -#define PWM_Pulse1_Reset_Mask 0x0000 -#define PWM_Pulse2_Reset_Mask 0x0000 -#define PWM_Pulse3_Reset_Mask 0x0000 -#define PWM_Period_Reset_Mask 0xFFFF -#define PWM_RepetitionCounter_Reset_Mask 0x0000 -#define PWM_DeadTime_Reset_Mask 0x0000 - -/* Private function prototypes -----------------------------------------------*/ -static void OCM_ModuleConfig(PWM_InitTypeDef* PWM_InitStruct); - -/* Private functions ---------------------------------------------------------*/ - -/****************************************************************************** -* Function Name : PWM_DeInit -* Description : Deinitializes PWM peripheral registers to their default reset -* values. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void PWM_DeInit(void) -{ - /* Enters and exits the PWM peripheral to and from reset */ - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_PWM,ENABLE); - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_PWM,DISABLE); -} - -/******************************************************************************* -* Function Name : PWM_Init -* Description : Initializes the PWM peripheral according to the specified -* parameters in the PWM_InitStruct . -* Input : PWM_InitStruct: pointer to a PWM_InitTypeDef structure that -* contains the configuration information for the PWM peripheral. -* Output : None -* Return : None -*******************************************************************************/ -void PWM_Init(PWM_InitTypeDef* PWM_InitStruct) -{ - /* Sets the prescaler value */ - PWM->PSC = PWM_InitStruct->PWM_Prescaler; - - /* Selects the counter mode */ - PWM->CR &= PWM_CounterMode_Mask; - PWM->CR |= PWM_InitStruct->PWM_CounterMode; - - /* Sets the period value */ - PWM->ARR = PWM_InitStruct->PWM_Period; - - /* Sets the repetition counter */ - PWM->RCR &= PWM_RepetitionCounter_Reset_Mask; - PWM->RCR |= PWM_InitStruct->PWM_RepetitionCounter; - - /* Configures the PWM according to the PWM_InitTypeDef structure parameters */ - OCM_ModuleConfig(PWM_InitStruct); -} - -/******************************************************************************* -* Function Name : PWM_StructInit -* Description : Fills each PWM_InitStruct member with its default value. -* Input : PWM_InitStruct : pointer to a PWM_InitTypeDef structure which -* will be initialized. -* Output : None -* Return : None. -*******************************************************************************/ -void PWM_StructInit(PWM_InitTypeDef *PWM_InitStruct) -{ - /* Sets the default configuration */ - PWM_InitStruct->PWM_Mode = PWM_Mode_OCTiming; - PWM_InitStruct->PWM_Prescaler = PWM_Prescaler_Reset_Mask; - PWM_InitStruct->PWM_CounterMode = PWM_CounterMode_Up; - PWM_InitStruct->PWM_Period = PWM_Period_Reset_Mask; - PWM_InitStruct->PWM_Complementary = PWM_Complementary_Disable; - PWM_InitStruct->PWM_OCState = PWM_OCState_Disable; - PWM_InitStruct->PWM_OCNState = PWM_OCNState_Disable; - PWM_InitStruct->PWM_Channel = PWM_Channel_1; - PWM_InitStruct->PWM_Pulse1 = PWM_Pulse1_Reset_Mask; - PWM_InitStruct->PWM_Pulse2 = PWM_Pulse2_Reset_Mask; - PWM_InitStruct->PWM_Pulse3 = PWM_Pulse3_Reset_Mask; - PWM_InitStruct->PWM_Polarity1 = PWM_Polarity1_High; - PWM_InitStruct->PWM_Polarity2 = PWM_Polarity2_High; - PWM_InitStruct->PWM_Polarity3 = PWM_Polarity3_High; - PWM_InitStruct->PWM_Polarity1N = PWM_Polarity1N_High; - PWM_InitStruct->PWM_Polarity2N = PWM_Polarity2N_High; - PWM_InitStruct->PWM_Polarity3N = PWM_Polarity3N_High; - PWM_InitStruct->PWM_DTRAccess = PWM_DTRAccess_Disable; - PWM_InitStruct->PWM_DeadTime = PWM_DeadTime_Reset_Mask; - PWM_InitStruct->PWM_Emergency = PWM_Emergency_Disable; - PWM_InitStruct->PWM_LOCKLevel = PWM_LOCKLevel_OFF; - PWM_InitStruct->PWM_OSSIState = PWM_OSSIState_Disable; - PWM_InitStruct->PWM_RepetitionCounter = PWM_RepetitionCounter_Reset_Mask; -} - -/******************************************************************************* -* Function Name : PWM_Cmd -* Description : Enables or disables the PWM peripheral. -* Input : Newstate: new state of the PWM peripheral. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void PWM_Cmd(FunctionalState Newstate) -{ - if(Newstate == ENABLE) - { - PWM->CR |= PWM_COUNTER_Start; - } - else - { - PWM->CR &= PWM_COUNTER_Stop; - } -} - -/******************************************************************************* -* Function Name : PWM_CtrlPWMOutputs -* Description : Enables or disables PWM peripheral Main Outputs. -* Input : Newstate: new state of the PWM peripheral Main Outputs. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void PWM_CtrlPWMOutputs(FunctionalState Newstate) -{ - if(Newstate == ENABLE) - { - PWM->DTR |= PWM_MOE_Set; - } - else - { - PWM->DTR &= PWM_MOE_Reset; - } -} - -/******************************************************************************* -* Function Name : PWM_ITConfig -* Description : Enables or disables the PWM interrupts. -* Input : - PWM_IT: specifies the PWM interrupts sources to be enabled -* or disabled. -* This parameter can be any combination of the following values: -* - PWM_IT_OC1: PWM Output Compare 1 Interrupt source -* - PWM_IT_OC2: PWM Output Compare 2 Interrupt source -* - PWM_IT_OC3: PWM Output Compare 3 Interrupt source -* - PWM_IT_Update: PWM update Interrupt source -* - PWM_IT_Emergency: PWM Emergency interrupt source -* - PWM_IT_GlobalUpdate: PWM global update Interrupt -* source -* - Newstate: new state of PWM interrupts. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void PWM_ITConfig(u16 PWM_IT, FunctionalState Newstate) -{ - u16 PWM_IT_Enable = 0; - - PWM_IT_Enable = PWM_IT & PWM_IT_Enable_Mask; - - if(Newstate == ENABLE) - { - /* Update interrupt global source: overflow/undeflow, counter reset operation - or slave mode controller in reset mode */ - if ((PWM_IT & PWM_IT_GlobalUpdate) == PWM_IT_GlobalUpdate) - { - PWM->CR &= PWM_UFS_Reset; - } - /* Update interrupt source: counter overflow/underflow */ - else if ((PWM_IT & PWM_IT_Update) == PWM_IT_Update) - { - PWM->CR |= PWM_UFS_Set; - } - /* Select and enable the interrupts requests */ - PWM->RSR |= PWM_IT_Enable; - PWM->RER |= PWM_IT_Enable; - } - /* Disable the interrupts requests */ - else - { - PWM->RSR &= ~PWM_IT_Enable; - PWM->RER &= ~PWM_IT_Enable; - } -} - -/******************************************************************************* -* Function Name : PWM_DMAConfig -* Description : Configures the PWM’s DMA interface. -* Input : - PWM_DMASources: specifies the DMA Request sources. -* This parameter can be any combination of the following values: -* - PWM_DMASource_OC1: PWM Output Compare 1 DMA source -* - PWM_DMASource_OC2: PWM Output Compare 2 DMA source -* - PWM_DMASource_OC3: PWM Output Compare 3 DMA source -* - PWM_DMASource_Update: PWM Update DMA source -* - PWM_OCRMState: the state of output compare request mode. -* This parameter can be one of the following values: -* - PWM_OCRMState_Enable -* - PWM_OCRMState_Disable -* - PWM_DMABase:DMA Base address. -* This parameter can be one of the following values: -* PWM_DMABase_CR, PWM_DMABase_SCR, PWM_DMABase_OMR1, -* PWM_DMABase_OMR2, PWM_DMABase_RSR, PWM_DMABase_RER, -* PWM_DMABase_ISR, PWM_DMABase_CNT, PWM_DMABase_PSC, -* PWM_DMABase_RCR, PWM_DMABase_ARR, PWM_DMABase_OCR1, -* PWM_DMABase_OCR2, PWM_DMABase_OCR3 ,PWM_DMABase_DTR. -* Output : None -* Return : None -*******************************************************************************/ -void PWM_DMAConfig(u16 PWM_DMASources, u16 PWM_OCRMState, u16 PWM_DMABase) -{ - /* Select the DMA requests */ - PWM->RSR &= ~PWM_DMASources; - - /* Sets the OCRM state */ - if(PWM_OCRMState == PWM_OCRMState_Enable) - { - PWM->RSR |= PWM_OCMR_Set; - } - else - { - PWM->RSR &= PWM_OCMR_Reset; - } - - /* Sets the DMA Base address */ - PWM->CR &= PWM_DBASE_Mask; - PWM->CR |= PWM_DMABase; -} - -/******************************************************************************* -* Function Name : PWM_DMACmd -* Description : Enables or disables the PWM’s DMA interface. -* Input : - PWM_DMASources: specifies the DMA Request sources. -* This parameter can be any combination of the following values: -* - PWM_DMASource_OC1: PWM Output Compare 1 DMA source -* - PWM_DMASource_OC2: PWM Output Compare 2 DMA source -* - PWM_DMASource_OC3: PWM Output Compare 3 DMA source -* - PWM_DMASource_Update: PWM Update DMA source -* - Newstate: new state of the DMA Request sources. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void PWM_DMACmd(u16 PWM_DMASources, FunctionalState Newstate) -{ - if(Newstate == ENABLE) - { - PWM->RER |= PWM_DMASources; - } - else - { - PWM->RER &= ~PWM_DMASources; - } -} - -/******************************************************************************* -* Function Name : PWM_SetPrescaler -* Description : Sets the PWM prescaler value. -* Input : Prescaler: PWM prescaler new value. -* Output : None -* Return : None -*******************************************************************************/ -void PWM_SetPrescaler(u16 Prescaler) -{ - PWM->PSC = Prescaler; -} - -/******************************************************************************* -* Function Name : PWM_SetPeriod -* Description : Sets the PWM period value. -* Input : Period: PWM period new value. -* Output : None -* Return : None -*******************************************************************************/ -void PWM_SetPeriod(u16 Period) -{ - PWM->ARR = Period; -} - -/******************************************************************************* -* Function Name : PWM_SetPulse -* Description : Sets the PWM pulse value. -* Input : - PWM_Channel: specifies the PWM channel to be used. -* This parameter can be one of the following values: -* - PWM_Channel_1: PWM Channel 1 is used -* - PWM_Channel_2: PWM Channel 2 is used -* - PWM_Channel_3: PWM Channel 3 is used -* - PWM_Channel_ALL: PWM Channel 1, Channel 2 and 3 are used -* - Pulse: PWM pulse new value. -* Output : None -* Return : None -*******************************************************************************/ -void PWM_SetPulse(u16 PWM_Channel, u16 Pulse) -{ - /* Sets Channel 1 pulse value */ - if(PWM_Channel == PWM_Channel_1) - { - PWM->OCR1 = Pulse; - } - /* Sets Channel 2 pulse value */ - else if(PWM_Channel == PWM_Channel_2) - { - PWM->OCR2 = Pulse; - } - /* Sets Channel 3 pulse value */ - else if(PWM_Channel == PWM_Channel_3) - { - PWM->OCR3 = Pulse; - } - /* Sets Channel 1, Channel 2 and Channel 3 pulse values */ - else if(PWM_Channel == PWM_Channel_ALL) - { - PWM->OCR1 = Pulse; - PWM->OCR2 = Pulse; - PWM->OCR3 = Pulse; - } -} - -/******************************************************************************* -* Function Name : PWM_SetPulse1 -* Description : Sets the PWM Channel 1 pulse value. -* Input : - Pulse: PWM Channel 1 pulse new value. -* Output : None -* Return : None -*******************************************************************************/ -void PWM_SetPulse1(u16 Pulse) -{ - PWM->OCR1 = Pulse; -} - -/******************************************************************************* -* Function Name : PWM_SetPulse2 -* Description : Sets the PWM Channel 2 pulse value. -* Input : - Pulse: PWM Channel 2 pulse new value. -* Output : None -* Return : None -*******************************************************************************/ -void PWM_SetPulse2(u16 Pulse) -{ - PWM->OCR2 = Pulse; -} - -/******************************************************************************* -* Function Name : PWM_SetPulse3 -* Description : Sets the PWM Channel 3 pulse value. -* Input : - Pulse: PWM Channel 3 pulse new value. -* Output : None -* Return : None -*******************************************************************************/ -void PWM_SetPulse3(u16 Pulse) -{ - PWM->OCR3 = Pulse; -} - -/******************************************************************************* -* Function Name : PWM_DebugCmd -* Description : Enables or disables PWM peripheral Debug control. -* Input : Newstate: new state of the PWM Debug control. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void PWM_DebugCmd(FunctionalState Newstate) -{ - if(Newstate == ENABLE) - { - PWM->CR |= PWM_DBGC_Set; - } - else - { - PWM->CR &= PWM_DBGC_Reset; - } -} - -/******************************************************************************* -* Function Name : PWM_CounterModeConfig -* Description : Specifies the Counter Mode to be used. -* Input : PWM_CounterMode: specifies the Counter Mode to be used -* This parameter can be one of the following values: -* - PWM_CounterMode_Up: PWM Up Counting Mode -* - PWM_CounterMode_Down: PWM Down Counting Mode -* - PWM_CounterMode_CenterAligned1: PWM Center Aligned1 Mode -* - PWM_CounterMode_CenterAligned2: PWM Center Aligned2 Mode -* - PWM_CounterMode_CenterAligned3: PWM Center Aligned3 Mode -* Output : None -* Return : None -*******************************************************************************/ -void PWM_CounterModeConfig(u16 PWM_CounterMode) -{ - /* Counter mode configuration */ - PWM->CR &= PWM_CounterMode_Mask; - PWM->CR |= PWM_CounterMode; -} - -/******************************************************************************* -* Function Name : PWM_ForcedOCConfig -* Description : Forces the PWM output waveform to active or inactive level. -* Input : - PWM_Channel: specifies the PWM channel to be used. -* This parameter can be one of the following values: -* - PWM_Channel_1: PWM Channel 1 is used -* - PWM_Channel_2: PWM Channel 2 is used -* - PWM_Channel_3: PWM Channel 3 is used -* - PWM_Channel_ALL: PWM Channel 1, Channel 2 and 3 are used -* - PWM_ForcedAction: specifies the forced Action to be set to the -* output waveform. -* This parameter can be one of the following values: -* - PWM_ForcedAction_Active: Force active level on OCxREF -* - PWM_ForcedAction_InActive: Force inactive level on -* OCxREF -* Output : None -* Return : None -*******************************************************************************/ -void PWM_ForcedOCConfig(u16 PWM_Channel, u16 PWM_ForcedAction) -{ - /* Channel 1 Forced Output Compare mode configuration */ - if(PWM_Channel == PWM_Channel_1) - { - PWM->OMR1 &= PWM_OC1C_Mask; - PWM->OMR1 |= PWM_ForcedAction; - } - /* Channel 2 Forced Output Compare mode configuration */ - else - { - if(PWM_Channel == PWM_Channel_2) - { - PWM->OMR1 &= PWM_OC2C_Mask; - PWM->OMR1 |= (PWM_ForcedAction<<8); - } - else - { - /* Channel 3 Forced Output Compare mode configuration */ - if(PWM_Channel == PWM_Channel_3) - { - PWM->OMR2 &= PWM_OC3C_Mask; - PWM->OMR2 |= PWM_ForcedAction; - } - /* Channel 1, Channel 2 and Channel 3 Forced Output Compare mode - configuration */ - else - { - PWM->OMR1 &= PWM_OC1C_Mask; - PWM->OMR1 |= PWM_ForcedAction; - - PWM->OMR1 &= PWM_OC2C_Mask; - PWM->OMR1 |= (PWM_ForcedAction<<8); - - PWM->OMR2 &= PWM_OC3C_Mask; - PWM->OMR2 |= PWM_ForcedAction; - } - } - } -} - -/******************************************************************************* -* Function Name : PWM_SetDeadTime -* Description : Inserts dead time between the OCx and OCNx. -* Input : DeadTime: PWM Dead Time value. -* Output : None -* Return : None -*******************************************************************************/ -void PWM_SetDeadTime(u16 DeadTime) -{ - /* Sets the dead time value */ - PWM->DTR &= PWM_DTR_Mask; - PWM->DTR |= DeadTime; -} - -/******************************************************************************* -* Function Name : PWM_ResetCounter -* Description : Re-intializes the PWM counter and generates an update of the -* registers. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void PWM_ResetCounter(void) -{ - /* Resets the PWM counter */ - PWM->CR |= PWM_COUNTER_Reset; -} - -/******************************************************************************* -* Function Name : PWM_TRGOSelection -* Description : Sets the PWM Master Mode selection bits. -* Input : PWM_TRGOMode: specifies the TRGO source. -* This parameter can be one of the following values: -* - PWM_TRGOMode_Enable: The CNT_EN bit is used as TRGO -* - PWM_TRGOMode_Update: The Update event is used as TRGO -* - PWM_TRGOMode_Reset: The CNT_RST bit is used as TRGO -* - PWM_TRGOMode_OC: The OC1 signal is used as TRGO -* Output : None -* Return : None -*******************************************************************************/ -void PWM_TRGOSelection(u16 PWM_TRGOMode) -{ - /* Sets the synchronization action */ - PWM->CR &= PWM_MasterModeSelection_Mask; - PWM->CR |= PWM_TRGOMode; -} - -/******************************************************************************* -* Function Name : PWM_GetFlagStatus -* Description : Checks whether the specified PWM flag is set or not. -* Input : PWM_FLAG: specifies the flag to check. -* This parameter can be one of the following values: -* - PWM_FLAG_OC1: Output Compare 1 Flag -* - PWM_FLAG_OC2: Output Compare 2 Flag -* - PWM_FLAG_OC3: Output Compare 3 Flag -* - PWM_FLAG_Update: PWM update Flag -* - PWM_FLAG_Emergency: PWM Emergency Flag -* Output : None -* Return : The new state of the PWM_FLAG(SET or RESET). -*******************************************************************************/ -FlagStatus PWM_GetFlagStatus(u16 PWM_FLAG) -{ - if((PWM->ISR & PWM_FLAG) != RESET ) - { - return SET; - } - else - { - return RESET; - } -} - -/******************************************************************************* -* Function Name : PWM_ClearFlag -* Description : Clears the PWM’s pending flags. -* Input : PWM_FLAG: specifies the flag to clear. -* This parameter can be any combination of the following values: -* - PWM_FLAG_OC1: Output Compare 1 flag -* - PWM_FLAG_OC2: Output Compare 2 flag -* - PWM_FLAG_OC3: Output Compare 3 flag -* - PWM_FLAG_Update: PWM update flag -* - PWM_FLAG_Emergency: PWM Emergency flag -* Output : None -* Return : None -*******************************************************************************/ -void PWM_ClearFlag(u16 PWM_FLAG) -{ - /* Clears the flags */ - PWM->ISR &= ~PWM_FLAG; -} - -/******************************************************************************* -* Function Name : PWM_GetITStatus -* Description : Checks whether the PWM interrupt has occurred or not. -* Input : PWM_IT: specifies the PWM interrupt source to check. -* This parameter can be one of the following values: -* - PWM_IT_OC1: PWM Output Compare 1 Interrupt source -* - PWM_IT_OC2: PWM Output Compare 2 Interrupt source -* - PWM_IT_OC3: PWM Output Compare 3 Interrupt source -* - PWM_IT_Update: PWM update Interrupt source -* - PWM_IT_Emergency: PWM Emergency interrupt source -* - PWM_IT_GlobalUpdate: PWM global update Interrupt -* source -* Output : None -* Return : The new state of the PWM_IT(SET or RESET). -*******************************************************************************/ -ITStatus PWM_GetITStatus(u16 PWM_IT) -{ - u16 PWM_IT_Check = 0; - - /* Calculates the pending bits to be checked */ - PWM_IT_Check = PWM_IT & PWM_IT_Clear_Mask; - - if((PWM->ISR & PWM_IT_Check) != RESET ) - { - return SET; - } - else - { - return RESET; - } -} - -/******************************************************************************* -* Function Name : PWM_ClearITPendingBit -* Description : Clears the PWM's interrupt pending bits. -* Input : PWM_IT: specifies the pending bit to clear. -* This parameter can be any combination of the following values: -* - PWM_IT_OC1: PWM Output Compare 1 Interrupt source -* - PWM_IT_OC2: PWM Output Compare 2 Interrupt source -* - PWM_IT_OC3: PWM Output Compare 3 Interrupt source -* - PWM_IT_Update: PWM update Interrupt source -* - PWM_IT_Emergency: PWM Emergency interrupt source -* - PWM_IT_GlobalUpdate: PWM global update Interrupt -* source -* Output : None -* Return : None -*******************************************************************************/ -void PWM_ClearITPendingBit(u16 PWM_IT) -{ - u16 PWM_IT_Clear = 0; - - /* Calculates the pending bits to be cleared */ - PWM_IT_Clear = PWM_IT & PWM_IT_Clear_Mask; - - /* Clears the pending bits */ - PWM->ISR &= ~PWM_IT_Clear; - -} - -/******************************************************************************* -* Function Name : OCM_ModuleConfig -* Description : Output Compare Module configuration. -* Input : PWM_InitStruct: pointer to a PWM_InitTypeDef structure that -* contains the configuration information for the PWM peripheral. -* Output : None -* Return : None -*******************************************************************************/ -static void OCM_ModuleConfig(PWM_InitTypeDef* PWM_InitStruct) -{ - u16 PWM_OCControl = 0x0000; - u16 DTR_REG = 0x0000; - - if(PWM_InitStruct->PWM_Mode == PWM_Mode_OCTiming) - { - PWM_OCControl = PWM_OCControl_OCTiming; - } - else - { - if(PWM_InitStruct->PWM_Mode == PWM_Mode_OCActive) - { - PWM_OCControl = PWM_OCControl_OCActive; - } - else - { - if(PWM_InitStruct->PWM_Mode == PWM_Mode_OCInactive) - { - PWM_OCControl = PWM_OCControl_OCInactive; - } - else - { - if(PWM_InitStruct->PWM_Mode == PWM_Mode_OCToggle) - { - PWM_OCControl = PWM_OCControl_OCToggle; - } - else - { - PWM_OCControl = PWM_OCControl_PWM; - - } - } - } - } - - /* Read DTR register */ - DTR_REG = PWM->DTR & 0x8000; - -/*Channel 1 Configuration-----------------------------------------------------*/ - if(PWM_InitStruct->PWM_Channel == PWM_Channel_1) - { - /* PWM Output Complementary Configuration */ - if(PWM_InitStruct->PWM_Complementary == PWM_Complementary_Enable) - { - /* Configures Channel 1 on Output Compare mode */ - PWM->OMR1 &= PWM_OC1C_Mask; - PWM->OMR1 |= PWM_OCControl|PWM_OC1_Enable|PWM_OC1N_Enable|PWM_PLD1_Set; - PWM->OCR1 = PWM_InitStruct->PWM_Pulse1; - - /* Sets the OC1 wave polarity */ - if(PWM_InitStruct->PWM_Polarity1 == PWM_Polarity1_Low) - { - PWM->OMR1 |= PWM_OC1P_Set; - } - else - { - PWM->OMR1 &= PWM_OC1P_Reset; - } - - /* Sets the OC1N wave polarity */ - if(PWM_InitStruct->PWM_Polarity1N == PWM_Polarity1N_Low) - { - PWM->OMR1 |= PWM_OC1NP_Set; - } - else - { - PWM->OMR1 &= PWM_OC1NP_Reset; - } - }/* End complementary case */ - /* Single PWM Output configuratuion */ - else - { - switch(PWM_InitStruct->PWM_OCState) - { - case PWM_OCState_Enable: - { - /* Configures Channel 1 on Output Compare mode */ - PWM->OMR1 &= PWM_OC1C_Mask; - PWM->OMR1 |= PWM_OCControl|PWM_OC1_Enable; - PWM->OMR1 |= PWM_PLD1_Set; - PWM->OCR1 = PWM_InitStruct->PWM_Pulse1; - - /* Sets the OC1 wave polarity */ - if(PWM_InitStruct->PWM_Polarity1 == PWM_Polarity1_Low) - { - PWM->OMR1 |= PWM_OC1P_Set; - } - else - { - PWM->OMR1 &= PWM_OC1P_Reset; - } - } - break; - case PWM_OCState_Disable: - { - /* OC1E = 0 and OSSR = 0 sets the polarity */ - PWM->OMR1 &= PWM_OC1_Disable; - DTR_REG &= PWM_OSSR_Reset; - } - break; - case PWM_OCState_OffState: - { - /* OC1E = 0 and OSSR = 1 and sets the polarity */ - PWM->OMR1 &= PWM_OC1_Disable; - DTR_REG |= PWM_OSSR_Set; - - /* Sets the OC1 wave polarity */ - if(PWM_InitStruct->PWM_Polarity1 == PWM_Polarity1_Low) - { - PWM->OMR1 |= PWM_OC1P_Set; - } - else - { - PWM->OMR1 &= PWM_OC1P_Reset; - } - } - break; - } - - switch(PWM_InitStruct->PWM_OCNState) - { - case PWM_OCNState_Enable: - { - /* Configures Channel 1N on Output Compare mode */ - PWM->OMR1 &= PWM_OC1C_Mask; - PWM->OMR1 |= PWM_OCControl |PWM_OC1N_Enable |PWM_PLD1_Set; - PWM->OCR1 = PWM_InitStruct->PWM_Pulse1; - - /* Sets the OC1N wave polarity */ - if(PWM_InitStruct->PWM_Polarity1N == PWM_Polarity1N_Low) - { - PWM->OMR1 |= PWM_OC1NP_Set; - } - else - { - PWM->OMR1 &= PWM_OC1NP_Reset; - } - } - break; - case PWM_OCNState_Disable: - { - /* OC1N = 0 OSSR = 0 */ - PWM->OMR1 &= PWM_OC1N_Disable; - DTR_REG &= PWM_OSSR_Reset; - } - break; - case PWM_OCNState_OffState: - { - /* OC1N = 0 OSSR = 1 and sets the polarity */ - PWM->OMR1 &= PWM_OC1N_Disable; - DTR_REG |= PWM_OSSR_Set; - - if(PWM_InitStruct->PWM_Polarity1N == PWM_Polarity1N_Low) - { - PWM->OMR1 |= PWM_OC1NP_Set; - } - else - { - PWM->OMR1 &= PWM_OC1NP_Reset; - } - } - break; - } - } /* End not complementary case */ - }/* end channel 1 */ - -/*Channel 2 Configuration-----------------------------------------------------*/ - if(PWM_InitStruct->PWM_Channel == PWM_Channel_2) - { - /* PWM Output Complementary Configuration */ - if(PWM_InitStruct->PWM_Complementary == PWM_Complementary_Enable) - { - /* Configures Channel 2 on Output Compare mode */ - PWM->OMR1 &= PWM_OC2C_Mask; - PWM->OMR1 |= (PWM_OCControl<<8)|PWM_OC2_Enable|PWM_OC2N_Enable|PWM_PLD2_Set; - PWM->OCR2 = PWM_InitStruct->PWM_Pulse2; - - /* Set the OC2 wave polarity */ - if(PWM_InitStruct->PWM_Polarity2 == PWM_Polarity2_Low) - { - PWM->OMR1 |= PWM_OC2P_Set; - } - else - { - PWM->OMR1 &= PWM_OC2P_Reset; - } - - /* Sets the OC2N wave polarity */ - if(PWM_InitStruct->PWM_Polarity2N == PWM_Polarity2N_Low) - { - PWM->OMR1 |= PWM_OC2NP_Set; - } - else - { - PWM->OMR1 &= PWM_OC2NP_Reset; - } - - }/* End complentary case */ - else - /* Single PWM Output configuratuion */ - { - switch(PWM_InitStruct->PWM_OCState) - { - case PWM_OCState_Enable: - { - /* Configures Channel 2 on Output Compare mode */ - PWM->OMR1 &= PWM_OC2C_Mask; - PWM->OMR1 |= (PWM_OCControl<<8)|PWM_OC2_Enable|PWM_PLD2_Set; - PWM->OCR2 = PWM_InitStruct->PWM_Pulse2; - - /* Sets the OC2 wave polarity */ - if(PWM_InitStruct->PWM_Polarity2 == PWM_Polarity2_Low) - { - PWM->OMR1 |= PWM_OC2P_Set; - } - else - { - PWM->OMR1 &= PWM_OC2P_Reset; - } - } - break; - case PWM_OCState_Disable: - { - /* OC2E = 0 and OSSR = 0 */ - PWM->OMR1 &= PWM_OC2_Disable; - DTR_REG &= PWM_OSSR_Reset; - } - break; - case PWM_OCState_OffState: - { - /* OC2E = 0 and OSSR = 1 sets the polarity */ - PWM->OMR1 &= PWM_OC2_Disable; - DTR_REG |= PWM_OSSR_Set; - - /* Sets the OC2 wave polarity */ - if(PWM_InitStruct->PWM_Polarity2 == PWM_Polarity2_Low) - { - PWM->OMR1 |= PWM_OC2P_Set; - } - else - { - PWM->OMR1 &= PWM_OC2P_Reset; - } - } - break; - } - switch(PWM_InitStruct->PWM_OCNState) - { - case PWM_OCNState_Enable: - { - /* Configures Channel 2N on Output Compare mode */ - PWM->OMR1 &= PWM_OC2C_Mask; - PWM->OMR1 |= (PWM_OCControl<<8)|PWM_OC2N_Enable|PWM_PLD2_Set; - PWM->OCR2 = PWM_InitStruct->PWM_Pulse2; - - /* Sets the OC2 wave polarity */ - if(PWM_InitStruct->PWM_Polarity2N == PWM_Polarity2N_Low) - { - PWM->OMR1 |= PWM_OC2NP_Set; - } - else - { - PWM->OMR1 &= PWM_OC2NP_Reset; - } - } - break; - case PWM_OCNState_Disable: - { - /* OC2N = 0 OSSR = 0 */ - PWM->OMR1 &= PWM_OC2N_Disable; - DTR_REG &= PWM_OSSR_Reset; - } - break; - case PWM_OCNState_OffState: - { - /* OC2N = 0 OSSR = 1 and sets the polarity */ - PWM->OMR1 &= PWM_OC2N_Disable; - DTR_REG |= PWM_OSSR_Set; - - if(PWM_InitStruct->PWM_Polarity2N == PWM_Polarity2N_Low) - { - PWM->OMR1 |= PWM_OC2NP_Set; - } - else - { - PWM->OMR1 &= PWM_OC2NP_Reset; - } - } - break; - } - } /* End not complementary case */ - }/* end channel 2 */ - -/*Channel 3 Configuration-----------------------------------------------------*/ - if(PWM_InitStruct->PWM_Channel == PWM_Channel_3) - { - /* PWM Output Complementary Configuration */ - if(PWM_InitStruct->PWM_Complementary == PWM_Complementary_Enable) - { - /* Configures Channel 3 on Output Compare mode */ - PWM->OMR2 &= PWM_OC3C_Mask; - PWM->OMR2 |= PWM_OCControl|PWM_OC3_Enable|PWM_OC3N_Enable|PWM_PLD3_Set; - PWM->OCR3 = PWM_InitStruct->PWM_Pulse3; - - /* Sets the OC3 wave polarity */ - if(PWM_InitStruct->PWM_Polarity3 == PWM_Polarity3_Low) - { - PWM->OMR2 |= PWM_OC3P_Set; - } - else - { - PWM->OMR2 &= PWM_OC3P_Reset; - } - - /* Sets the OC3N wave polarity */ - if(PWM_InitStruct->PWM_Polarity3N == PWM_Polarity3N_Low) - { - PWM->OMR2 |= PWM_OC3NP_Set; - } - else - { - PWM->OMR2 &= PWM_OC3NP_Reset; - } - }/* End complementary case */ - else - /* Single PWM Output configuratuion */ - { - switch(PWM_InitStruct->PWM_OCState) - { - case PWM_OCState_Enable: - { - /* Configures Channel 3 on Output Compare mode */ - PWM->OMR2 &= PWM_OC3C_Mask; - PWM->OMR2 |= PWM_OCControl|PWM_OC3_Enable|PWM_PLD3_Set; - PWM->OCR3 = PWM_InitStruct->PWM_Pulse3; - - /* Sets the OCC wave polarity */ - if(PWM_InitStruct->PWM_Polarity3 == PWM_Polarity3_Low) - { - PWM->OMR2 |= PWM_OC3P_Set; - } - else - { - PWM->OMR2 &= PWM_OC3P_Reset; - } - } - break; - case PWM_OCState_Disable: - { - /* OC3E = 0 and OSSR = 0 */ - PWM->OMR2 &= PWM_OC3_Disable; - DTR_REG &= PWM_OSSR_Reset; - } - break; - case PWM_OCState_OffState: - { - /* OC3E = 0 and OSSR = 1 sets the polarity */ - PWM->OMR2 &= PWM_OC3_Disable; - DTR_REG |= PWM_OSSR_Set; - - if(PWM_InitStruct->PWM_Polarity3 == PWM_Polarity3_Low) - { - PWM->OMR2 |= PWM_OC3P_Set; - } - else - { - PWM->OMR2 &= PWM_OC3P_Reset; - } - } - break; - } - - switch(PWM_InitStruct->PWM_OCNState) - { - case PWM_OCNState_Enable: - { - /* Configures Channel 3N on Output Compare mode */ - PWM->OMR2 &= PWM_OC3C_Mask; - PWM->OMR2 |= PWM_OCControl |PWM_OC3N_Enable|PWM_PLD3_Set; - PWM->OCR3 = PWM_InitStruct->PWM_Pulse3; - - /* Sets the OC3 wave polarity */ - if(PWM_InitStruct->PWM_Polarity3N == PWM_Polarity3N_Low) - { - PWM->OMR2 |= PWM_OC3NP_Set; - } - else - { - PWM->OMR2 &= PWM_OC3NP_Reset; - } - } - break; - case PWM_OCNState_Disable: - { - /* OC3N = 0 OSSR = 0 */ - PWM->OMR2 &= PWM_OC3N_Disable; - DTR_REG &= PWM_OSSR_Reset; - } - break; - case PWM_OCNState_OffState: - { - /* OC3N = 0 OSSR = 1 and sets the polarity */ - PWM->OMR2 &= PWM_OC3N_Disable; - DTR_REG |= PWM_OSSR_Set; - - if(PWM_InitStruct->PWM_Polarity3N == PWM_Polarity3N_Low) - { - PWM->OMR2 |= PWM_OC3NP_Set; - } - else - { - PWM->OMR2 &= PWM_OC3NP_Reset; - } - } - break; - } - } /* End not complementary case */ - }/* end channel 3 */ - - if(PWM_InitStruct->PWM_DTRAccess == PWM_DTRAccess_Enable) - { - DTR_REG |= PWM_InitStruct->PWM_LOCKLevel | PWM_InitStruct->PWM_Emergency | - PWM_InitStruct->PWM_DeadTime | PWM_InitStruct->PWM_OSSIState; - PWM->DTR = DTR_REG; - } -} -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_rtc.c b/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_rtc.c deleted file mode 100644 index ab6da500b..000000000 --- a/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_rtc.c +++ /dev/null @@ -1,326 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_rtc.c -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file provides all the RTC software functions. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -#include "75x_rtc.h" -#include "75x_mrcc.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define RTC_CNF_Enable_Mask 0x0010 /* Configuration Flag Enable Mask */ -#define RTC_CNF_Disable_Mask 0xFFEF /* Configuration Flag Disable Mask */ -#define RTC_LSB_Mask 0x0000FFFF /* RTC LSB Mask */ -#define RTC_MSB_Mask 0xFFFF0000 /* RTC MSB Mask */ -#define RTC_Prescaler_MSB_Mask 0x000F0000 /* RTC Prescaler MSB Mask */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/******************************************************************************* -* Function Name : RTC_DeInit -* Description : Deinitializes the RTC peripheral registers to their -* default reset values. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void RTC_DeInit(void) -{ - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_RTC,ENABLE); - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_RTC,DISABLE); -} - -/******************************************************************************* -* Function Name : RTC_ITConfig -* Description : Enables or disables the specified RTC interrupts. -* Input : - RTC_IT: specifies the RTC interrupts sources to be enabled -* or disabled. -* This parameter can be a combination of one or more of the -* following values: -* - RTC_IT_Overflow: Overflow interrupt -* - RTC_IT_Alarm: Alarm interrupt -* - RTC_IT_Second: Second interrupt -* - NewState: new state of the specified RTC interrupts. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void RTC_ITConfig(u16 RTC_IT, FunctionalState NewState) -{ - if(NewState == ENABLE) - { - RTC->CRH |= RTC_IT; - } - else - { - RTC->CRH &= ~RTC_IT; - } -} - -/******************************************************************************* -* Function Name : RTC_EnterConfigMode -* Description : Enters the RTC configuration mode. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void RTC_EnterConfigMode(void) -{ - /* Set the CNF flag to enter in the Configuration Mode */ - RTC->CRL |= RTC_CNF_Enable_Mask; -} - -/******************************************************************************* -* Function Name : RTC_ExitConfigMode -* Description : Exits from the RTC configuration mode. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void RTC_ExitConfigMode(void) -{ - /* Reset the CNF flag to exit from the Configuration Mode */ - RTC->CRL &= RTC_CNF_Disable_Mask; -} - -/******************************************************************************* -* Function Name : RTC_GetCounter -* Description : Gets the RTC counter value. -* Input : None -* Output : None -* Return : RTC counter value. -*******************************************************************************/ -u32 RTC_GetCounter(void) -{ - u16 Tmp = 0; - Tmp = RTC->CNTL; - - return (((u32)RTC->CNTH << 16 ) |Tmp) ; -} - -/******************************************************************************* -* Function Name : RTC_SetCounter -* Description : Sets the RTC counter value. -* Input : RTC counter new value. -* Output : None -* Return : None -*******************************************************************************/ -void RTC_SetCounter(u32 CounterValue) -{ - RTC_EnterConfigMode(); - -/* COUNTER Config ------------------------------------------------------------*/ - /* Set RTC COUNTER MSB word */ - RTC->CNTH =(CounterValue & RTC_MSB_Mask) >> 16; - /* Set RTC COUNTER LSB word */ - RTC->CNTL =(CounterValue & RTC_LSB_Mask); - - RTC_ExitConfigMode(); -} - -/******************************************************************************* -* Function Name : RTC_SetPrescaler -* Description : Sets the RTC prescaler value. -* Input : RTC prescaler new value. -* Output : None -* Return : None -*******************************************************************************/ -void RTC_SetPrescaler(u32 PrescalerValue) -{ - RTC_EnterConfigMode(); - -/* PRESCALER Config ----------------------------------------------------------*/ - /* Set RTC PRESCALER MSB word */ - RTC->PRLH = (PrescalerValue & RTC_Prescaler_MSB_Mask) >> 16; - /* Set RTC PRESCALER LSB word */ - RTC->PRLL = (PrescalerValue & RTC_LSB_Mask); - - RTC_ExitConfigMode(); -} - -/******************************************************************************* -* Function Name : RTC_GetPrescaler -* Description : Gets the RTC prescaler value. -* Input : None -* Output : None -* Return : RTC prescaler value. -*******************************************************************************/ -u32 RTC_GetPrescaler(void) -{ - u16 Tmp = 0; - Tmp = RTC->PRLL; - - return (((u32)(RTC->PRLH & 0x000F) << 16 ) | Tmp); -} - -/******************************************************************************* -* Function Name : RTC_SetAlarm -* Description : Sets the RTC alarm value. -* Input : RTC alarm new value. -* Output : None -* Return : None -*******************************************************************************/ -void RTC_SetAlarm(u32 AlarmValue) -{ - RTC_EnterConfigMode(); - -/* ALARM Config --------------------------------------------------------------*/ - /* Set the ALARM MSB word */ - RTC->ALRH = (AlarmValue & RTC_MSB_Mask) >> 16; - /* Set the ALARM LSB word */ - RTC->ALRL = (AlarmValue & RTC_LSB_Mask); - - RTC_ExitConfigMode(); -} - -/******************************************************************************* -* Function Name : RTC_GetDivider -* Description : Gets the RTC divider value. -* Input : None -* Output : None -* Return : RTC Divider value. -*******************************************************************************/ -u32 RTC_GetDivider(void) -{ - u16 Tmp = 0; - Tmp = RTC->DIVL ; - return (((u32)(RTC->DIVH & 0x000F) << 16 ) | Tmp); -} - -/******************************************************************************* -* Function Name : RTC_WaitForLastTask -* Description : Waits until last write operation on RTC registers has finished. -* This function must be called before any write to RTC registers. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void RTC_WaitForLastTask(void) -{ - /* Loop until RTOFF flag is set */ - while ((RTC->CRL & RTC_FLAG_RTOFF) == RESET); -} - -/******************************************************************************* -* Function Name : RTC_WaitForSynchro -* Description : Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL) -* are synchronized with RTC APB clock. -* This function must be called before any read operation after -* an APB reset or an APB clock stop. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void RTC_WaitForSynchro(void) -{ - /* Clear RSF flag */ - RTC->CRL &= ~RTC_FLAG_RSF; - - /* Loop until RSF flag is set */ - while((RTC->CRL & RTC_FLAG_RSF)== RESET); -} - -/******************************************************************************* -* Function Name : RTC_GetFlagStatus -* Description : Checks whether the specified RTC flag is set or not. -* Input : RTC_FLAG: specifies the flag to check. -* This parameter can be one the following values: -* - RTC_FLAG_RTOFF: RTC Operation OFF flag -* - RTC_FLAG_RSF: Registers Synchronized flag -* - RTC_FLAG_Overflow: Overflow interrupt flag -* - RTC_FLAG_Alarm: Alarm interrupt flag -* - RTC_FLAG_Second: Second interrupt flag -* Output : None -* Return : The new state of RTC_FLAG (SET or RESET). -*******************************************************************************/ -FlagStatus RTC_GetFlagStatus(u16 RTC_FLAG) -{ - if((RTC->CRL & RTC_FLAG) != RESET) - { - return SET; - } - else - { - return RESET; - } -} - -/******************************************************************************* -* Function Name : RTC_ClearFlag -* Description : Clears the RTC’s pending flags. -* Input : RTC_FLAG: specifies the flag to clear. -* This parameter can be a combination of one or more of -* the following values: -* - RTC_FLAG_RSF: Registers Synchronized flag. This flag -* is cleared only after an APB reset or an APB Clock stop. -* - RTC_FLAG_Overflow: Overflow interrupt flag -* - RTC_FLAG_Alarm: Alarm interrupt flag -* - RTC_FLAG_Second: Second interrupt flag -* Output : None -* Return : None -*******************************************************************************/ -void RTC_ClearFlag(u16 RTC_FLAG) -{ - /* Clear the coressponding RTC flag */ - RTC->CRL &= ~RTC_FLAG; -} - -/******************************************************************************* -* Function Name : RTC_GetITStatus -* Description : Checks whether the specified RTC interrupt has occured or not. -* Input : RTC_IT: specifies the RTC interrupts sources to check. -* This parameter can be a combination of one or more of -* the following values: -* - RTC_IT_Overflow: Overflow interrupt -* - RTC_IT_Alarm: Alarm interrupt -* - RTC_IT_Second: Second interrupt -* Output : None -* Return : The new state of the RTC_IT (SET or RESET). -*******************************************************************************/ -ITStatus RTC_GetITStatus(u16 RTC_IT) -{ - if(((RTC->CRH & RTC_IT) != RESET)&& ((RTC->CRL & RTC_IT) != RESET)) - { - return SET; - } - else - { - return RESET; - } -} - -/******************************************************************************* -* Function Name : RTC_ClearITPendingBit -* Description : Clears the RTC’s interrupt pending bits. -* Input : RTC_IT: specifies the interrupt pending bit to clear. -* This parameter can be any combination of one or more of -* the following values: -* - RTC_IT_Overflow: Overflow interrupt -* - RTC_IT_Alarm: Alarm interrupt -* - RTC_IT_Second: Second interrupt -* Output : None -* Return : None -*******************************************************************************/ -void RTC_ClearITPendingBit(u16 RTC_IT) -{ - /* Clear the coressponding RTC pending bit */ - RTC->CRL &= ~RTC_IT; -} - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_smi.c b/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_smi.c deleted file mode 100644 index 9af53a9e8..000000000 --- a/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_smi.c +++ /dev/null @@ -1,551 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_smi.c -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file provides all the SMI software functions. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -#include "75x_smi.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* SMI_CR1 mask bits */ -#define SMI_HOLDPRESCTCS_RESET_Mask 0xFF00800F -#define SMI_Prescaler_MaxValue 0x7F -#define SMI_DeselectTime_MaxValue 0x0F -#define SMI_ClockHold_Mask 0x00 -#define SMI_Prescaler_Mask 0x02 -#define SMI_DeselectTime_Mask 0x5 - -/* SMI_CR2 mask bits */ -#define SMI_BS_RESET_Mask 0xFFFFCFFF -#define SMI_BS_Bank1_Mask 0x00001000 -#define SMI_BS_Bank2_Mask 0x00002000 -#define SMI_BS_Bank3_Mask 0x00003000 -#define SMI_WEN_Mask 0x00000800 -#define SMI_RSR_Mask 0x00000400 -#define SMI_SEND_Mask 0x00000080 -#define SMI_TRARECLENGTH_RESET_Mask 0xFFFFFF88 - -/* SMI_SR mask bits */ -#define SMI_STATUSREGISTER_Mask 0xFF - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/******************************************************************************* -* Function Name : SMI_DeInit -* Description : Deinitializes the SMI peripheral registers to their default -* reset values. This function must not be used when booting -* from the SMI external memory. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void SMI_DeInit(void) -{ - SMI->CR1 = 0x00000250; - SMI->CR2 = 0x00; - SMI->SR &= 0xFFFFF0FF; - SMI->TR = 0x00; -} - -/******************************************************************************* -* Function Name : SMI_Init -* Description : Initializes the SMI peripheral according to the specified -* parameters in the SMI_InitStruct. -* Input : - SMI_InitStruct: pointer to a SMI_InitTypeDef structure that -* contains the configuration information for the specified -* SMI peripheral. -* Output : None -* Return : None -*******************************************************************************/ -void SMI_Init(SMI_InitTypeDef* SMI_InitStruct) -{ - u32 Temp = 0; - - /* Clear HOLD[7:0], PRESC[6:0] and TCS[3:0] bits */ - Temp = SMI->CR1 & SMI_HOLDPRESCTCS_RESET_Mask; - - /* Set HOLD[7:0] bits according to SMI_ClockHold value */ - Temp |= SMI_InitStruct->SMI_ClockHold << 16; - - if(SMI_InitStruct->SMI_Prescaler <= SMI_Prescaler_MaxValue) - { - /* Set PRESC[6:0] bits according to SMI_Prescaler value */ - Temp |= SMI_InitStruct->SMI_Prescaler << 8; - } - - if(SMI_InitStruct->SMI_DeselectTime <= SMI_DeselectTime_MaxValue) - { - /* Set TCS[3:0] bits according to SMI_DeselectTime value */ - Temp |= SMI_InitStruct->SMI_DeselectTime << 4; - } - - /* Store the new value */ - SMI->CR1 = Temp; -} - -/******************************************************************************* -* Function Name : SMI_StructInit -* Description : Fills each SMI_InitStruct member with its reset value. -* Input : - SMI_InitStruct: pointer to a SMI_InitTypeDef structure which -* will be initialized. -* Output : None -* Return : None -*******************************************************************************/ -void SMI_StructInit(SMI_InitTypeDef* SMI_InitStruct) -{ - /* SMI_CK is sent continuously */ - SMI_InitStruct->SMI_ClockHold = SMI_ClockHold_Mask; - - /* SMI_CK = HCLK/2 */ - SMI_InitStruct->SMI_Prescaler = SMI_Prescaler_Mask; - - /* Deselect Time set to 6*SMI_CK periods */ - SMI_InitStruct->SMI_DeselectTime = SMI_DeselectTime_Mask; -} - -/******************************************************************************* -* Function Name : SMI_ModeConfig -* Description : Selects the SMI mode: hardware or software. -* Input : - SMI_Mode: specifies the SMI mode. -* This parameter can be one of the following values: -* - SMI_Mode_HW: SMI in hardware mode -* - SMI_Mode_SW: SMI in software mode -* Output : None -* Return : None -*******************************************************************************/ -void SMI_ModeConfig(u32 SMI_Mode) -{ - if(SMI_Mode == SMI_Mode_SW) - { - SMI->CR1 |= SMI_Mode_SW; - } - else - { - SMI->CR1 &= SMI_Mode_HW; - } -} - -/******************************************************************************* -* Function Name : SMI_TxRxLengthConfig -* Description : Configures the number of bytes to be transmitted and received -* to/from external memory. This function is used in Software -* mode only. -* Input : - SMI_TxLength: specifies the number of bytes to be transmitted -* to external memory. -* This parameter can be one of the following values: -* - SMI_TxLength_0Bytes: No bytes transmitted -* - SMI_TxLength_1Byte: 1 byte transmitted -* - SMI_TxLength_2Bytes: 2 bytes transmitted -* - SMI_TxLength_3Bytes: 3 bytes transmitted -* - SMI_TxLength_4Bytes: 4 bytes transmitted -* - SMI_RxLength: specifies the number of bytes to be received -* from external memory. -* This parameter can be one of the following values: -* - SMI_RxLength_0Bytes: No bytes received -* - SMI_RxLength_1Byte: 1 byte received -* - SMI_RxLength_2Bytes: 2 bytes received -* - SMI_RxLength_3Bytes: 3 bytes received -* - SMI_RxLength_4Bytes: 4 bytes received -* Output : None -* Return : None -*******************************************************************************/ -void SMI_TxRxLengthConfig(u32 SMI_TxLength, u32 SMI_RxLength) -{ - u32 Temp = 0; - - /* Clear TRA_LENGTH[2:0] and REC_LENGTH[2:0] bits */ - Temp = SMI->CR2 & SMI_TRARECLENGTH_RESET_Mask; - - /* Set TRA_LENGTH[2:0] and REC_LENGTH[2:0] bits according to function parameters */ - Temp |= SMI_TxLength | SMI_RxLength; - - /* Store the new value */ - SMI->CR2 = Temp; -} - -/******************************************************************************* -* Function Name : SMI_BankCmd -* Description : Enables or disables the specified memory Bank. -* Input : - SMI_Bank: specifies the memory Bank to be enabled or disabled. -* This parameter can be any combination of the following values: -* - SMI_Bank_0 -* - SMI_Bank_1 -* - SMI_Bank_2 -* - SMI_Bank_3 -* - NewState: new state of the specified memory Bank. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void SMI_BankCmd(u32 SMI_Bank, FunctionalState NewState) -{ - if(NewState == ENABLE) - { - SMI->CR1 |= SMI_Bank; - } - else - { - SMI->CR1 &= ~SMI_Bank; - } -} - -/******************************************************************************* -* Function Name : SMI_ITConfig -* Description : Enables or disables the specified SMI interrupts. -* Input : - SMI_IT: specifies the SMI interrupts sources to be -* enabled or disabled. This parameter can be any combination -* of the following values: -* - SMI_IT_WC : Write Complete Interrupt -* - SMI_IT_TF : Transfer Finished Interrupt -* - NewState: new state of the specified SMI interrupts. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void SMI_ITConfig(u32 SMI_IT, FunctionalState NewState) -{ - if(NewState == ENABLE) - { - SMI->CR2 |= SMI_IT; - } - else - { - SMI->CR2 &= ~SMI_IT; - } -} - -/******************************************************************************* -* Function Name : SMI_SelectBank -* Description : Selects the memory Bank to be accessed. Only one Bank can be -* selected at a time. -* Input : - SMI_Bank: specifies the memory Bank to be selected. -* This parameter can be one of the following values: -* - SMI_Bank_0 -* - SMI_Bank_1 -* - SMI_Bank_2 -* - SMI_Bank_3 -* Output : None -* Return : None -*******************************************************************************/ -void SMI_SelectBank(u32 SMI_Bank) -{ - /* Clear BS[1:0] bits (Bank0 is selected)*/ - SMI->CR2 &= SMI_BS_RESET_Mask; - - switch(SMI_Bank) - { - case SMI_Bank_1: - /* Select Bank1 */ - SMI->CR2 |= SMI_BS_Bank1_Mask; - break; - - case SMI_Bank_2: - /* Select Bank2 */ - SMI->CR2 |= SMI_BS_Bank2_Mask; - break; - - case SMI_Bank_3: - /* Select Bank3 */ - SMI->CR2 |= SMI_BS_Bank3_Mask; - break; - - default: - break; - } -} - -/******************************************************************************* -* Function Name : SMI_SendWENCmd -* Description : Sends a Write Enable command to the selected memory Bank. -* This function is used in Hardware mode only. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void SMI_SendWENCmd(void) -{ - SMI->CR2 |= SMI_WEN_Mask; -} - -/******************************************************************************* -* Function Name : SMI_SendRSRCmd -* Description : Sends a Read Status Register Command to the selected memory -* Bank. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void SMI_SendRSRCmd(void) -{ - SMI->CR2 |= SMI_RSR_Mask; -} - -/******************************************************************************* -* Function Name : SMI_SendCmd -* Description : Sends command to the selected memory Bank. This function is -* used in Software mode only. -* Input : - Command: specifies the command to send to the external memory. -* Output : None -* Return : None -*******************************************************************************/ -void SMI_SendCmd(u32 Command) -{ - /* Load the command in the Transmit Register */ - SMI->TR = Command; - - /* Start transfer */ - SMI->CR2 |= SMI_SEND_Mask; -} - -/******************************************************************************* -* Function Name : SMI_FastReadConfig -* Description : Enables or disables the Fast Read Mode. -* Input : - SMI_FastRead: specifies whether the Fast Read Mode is -* enabled or disabled. -* This parameter can be one of the following values: -* - SMI_FastRead_Disable : Fast Read Mode disabled -* - SMI_FastRead_Enable : Fast Read Mode enabled -* Output : None -* Return : None -*******************************************************************************/ -void SMI_FastReadConfig(u32 SMI_FastRead) -{ - if(SMI_FastRead == SMI_FastRead_Enable) - { - SMI->CR1 |= SMI_FastRead_Enable; - } - else - { - SMI->CR1 &= SMI_FastRead_Disable; - } -} - -/******************************************************************************* -* Function Name : SMI_WriteBurstConfig -* Description : Enables or disables the Write Burst Mode. -* Input : - SMI_WriteBurst: specifies whether the Write Burst Mode is -* enabled or disabled. -* This parameter can be one of the following values: -* - SMI_WriteBurst_Disable : Write Burst Mode disabled -* - SMI_WriteBurst_Enable : Write Burst Mode enabled -* Output : None -* Return : None -*******************************************************************************/ -void SMI_WriteBurstConfig(u32 SMI_WriteBurst) -{ - if(SMI_WriteBurst == SMI_WriteBurst_Enable) - { - SMI->CR1 |= SMI_WriteBurst_Enable; - } - else - { - SMI->CR1 &= SMI_WriteBurst_Disable; - } -} - -/******************************************************************************* -* Function Name : SMI_WriteByte -* Description : Writes a Byte to the selected memory Bank. This function is -* used in Hardware mode only. -* Before calling this function, send a Write Enable command to -* the selected memory Bank using SMI_SendWENCmd() function. -* Input : - WriteAddr: external memory address from which the data will -* be written. -* - Data: data to be written to the external memory. -* Output : None -* Return : None -*******************************************************************************/ -void SMI_WriteByte(u32 WriteAddr, u8 Data) -{ - /* Transfer data to the memory */ - *(u8 *) WriteAddr = Data; -} - -/******************************************************************************* -* Function Name : SMI_WriteHalfWord -* Description : Writes a Half Word to the selected memory Bank. This function -* is used in Hardware mode only. -* Before calling this function, send a Write Enable command to -* the selected memory Bank using SMI_SendWENCmd() function. -* Input : - WriteAddr: external memory address from which the data will -* be written. -* - Data: data to be written to the external memory. -* Output : None -* Return : None -*******************************************************************************/ -void SMI_WriteHalfWord(u32 WriteAddr, u16 Data) -{ - /* Transfer data to the memory */ - *(u16 *) WriteAddr = Data; -} - -/******************************************************************************* -* Function Name : SMI_WriteWord -* Description : Writes a Word to the selected memory Bank. This function is -* used in Hardware mode only. -* Before calling this function, send a Write Enable command to -* the selected memory Bank using SMI_SendWENCmd() function. -* Input : - WriteAddr: external memory address from which the data will -* be written. -* - Data: data to be written to the external memory. -* Output : None -* Return : None -*******************************************************************************/ -void SMI_WriteWord(u32 WriteAddr, u32 Data) -{ - /* Transfer data to the memory */ - *(u32 *) WriteAddr = Data; -} - -/******************************************************************************* -* Function Name : SMI_ReadByte -* Description : Reads a Byte from the selected memory Bank. This function is -* used in Hardware mode only. -* Input : - ReadAddr: external memory address to read from. -* Output : None -* Return : Data read from the external memory. -*******************************************************************************/ -u8 SMI_ReadByte(u32 ReadAddr) -{ - return(*(u8 *) ReadAddr); -} - -/******************************************************************************* -* Function Name : SMI_ReadHalfWord -* Description : Reads a Half Word from the selected memory Bank. This function -* is used in Hardware mode only. -* Input : - ReadAddr: external memory address to read from. -* Output : None -* Return : Data read from the external memory. -*******************************************************************************/ -u16 SMI_ReadHalfWord(u32 ReadAddr) -{ - return(*(u16 *) ReadAddr); -} - -/******************************************************************************* -* Function Name : SMI_ReadWord -* Description : Reads a Word from the selected memory Bank. This function is -* used in Hardware mode only. -* Input : - ReadAddr: external memory address to read from. -* Output : None -* Return : Data read from the external memory. -*******************************************************************************/ -u32 SMI_ReadWord(u32 ReadAddr) -{ - return(*(u32 *) ReadAddr); -} - -/******************************************************************************* -* Function Name : SMI_ReadMemoryStatusRegister -* Description : Reads the status register of the memory connected to the -* selected Bank. -* Input : None -* Output : None -* Return : External memory status register value. -*******************************************************************************/ -u8 SMI_ReadMemoryStatusRegister(void) -{ - return((u8) (SMI->SR & SMI_STATUSREGISTER_Mask)); -} - -/******************************************************************************* -* Function Name : SMI_GetFlagStatus -* Description : Checks whether the specified SMI flag is set or not. -* Input : - SMI_FLAG: specifies the flag to check. -* This parameter can be one of the following values: -* - SMI_FLAG_Bank3_WM : Memory Bank3 Write Mode flag -* - SMI_FLAG_Bank2_WM : Memory Bank2 Write Mode flag -* - SMI_FLAG_Bank1_WM : Memory Bank1 Write Mode flag -* - SMI_FLAG_Bank0_WM : Memory Bank0 Write Mode flag -* - SMI_FLAG_ERF2 : Error Flag 2: Forbidden Write Request -* - SMI_FLAG_ERF1 : Error Flag 1: Forbidden Access -* - SMI_FLAG_WC : Write Complete flag -* - SMI_FLAG_TF : Transfer Finished flag -* Output : None -* Return : The new state of SMI_FLAG (SET or RESET). -*******************************************************************************/ -FlagStatus SMI_GetFlagStatus(u32 SMI_FLAG) -{ - if((SMI->SR & SMI_FLAG) != RESET) - { - return SET; - } - else - { - return RESET; - } -} - -/******************************************************************************* -* Function Name : SMI_ClearFlag -* Description : Clears the SMI’s pending flags. -* Input : - SMI_FLAG: specifies the flag to clear. -* This parameter can be any combination of the following values: -* - SMI_FLAG_ERF2 : Error Flag 2: Forbidden Write Request -* - SMI_FLAG_ERF1 : Error Flag 1: Forbidden Access -* - SMI_FLAG_WC : Write Complete flag -* - SMI_FLAG_TF : Transfer Finished flag -* Output : None -* Return : None -*******************************************************************************/ -void SMI_ClearFlag(u32 SMI_FLAG) -{ - SMI->SR &= ~SMI_FLAG; -} - -/******************************************************************************* -* Function Name : SMI_GetITStatus -* Description : Checks whether the specified SMI interrupt has occurred or not. -* Input : - SMI_FLAG: specifies the interrupt source to check. -* This parameter can be one of the following values: -* - SMI_IT_WC : Write Complete Interrupt -* - SMI_IT_TF : Transfer Finished Interrupt -* Output : None -* Return : The new state of SMI_IT (SET or RESET). -*******************************************************************************/ -ITStatus SMI_GetITStatus(u32 SMI_IT) -{ - if(((SMI->CR2 & SMI_IT) != RESET) && ((SMI->SR & SMI_IT) != RESET)) - { - return SET; - } - else - { - return RESET; - } -} - -/******************************************************************************* -* Function Name : SMI_ClearITPendingBit -* Description : Clears the SMI’s interrupt pending bits. -* Input : - SMI_FLAG: specifies the interrupts sources to clear. -* This parameter can be any combination of the following values: -* - SMI_IT_WC : Write Complete Interrupt -* - SMI_IT_TF : Transfer Finished Interrupt -* Output : None -* Return : None -*******************************************************************************/ -void SMI_ClearITPendingBit(u32 SMI_IT) -{ - SMI->SR &= ~SMI_IT; -} - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_ssp.c b/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_ssp.c deleted file mode 100644 index b4ccd215e..000000000 --- a/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_ssp.c +++ /dev/null @@ -1,588 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_ssp.c -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file provides all the SSP software functions. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -#include "75x_ssp.h" -#include "75x_mrcc.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* SSP peripheral Enable */ -#define SSP_Enable 0x0002 -#define SSP_Disable 0xFFFD - -/* SSP Loop Back Mode Enable */ -#define SSP_LoopBackMode_Enable 0x0001 -#define SSP_LoopBackMode_Disable 0xFFFE - -/* SSP Flag Mask */ -#define SSP_Flag_Mask 0x001F - -/* SSP DMA transmit/ receive enable/disable Masks */ -#define SSP0_DMA_TransmitEnable 0x0002 -#define SSP0_DMA_TransmitDisable 0xFFFD -#define SSP0_DMA_ReceiveEnable 0x0001 -#define SSP0_DMA_ReceiveDisable 0xFFFE - -/* SSP Masks */ -#define SSP_FrameFormat_Mask 0xFFCF -#define SSP_DataSize_Mask 0xFFF0 -#define SSP_ClockRate_Mask 0x00FF -#define SSP_ClockPrescaler_Mask 0xFF00 -#define SSP_SSI_Set_Mask 0x0020 -#define SSP_SSI_Reset_Mask 0xFFDF - - -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/******************************************************************************* -* Function Name : SSP_DeInit -* Description : Deinitializes the SSPx peripheral registers to their default -* reset values. -* Input : SSPx: where x can be 0 or 1 to select the SSP peripheral. -* Output : None -* Return : None -*******************************************************************************/ -void SSP_DeInit(SSP_TypeDef* SSPx) -{ - if(SSPx == SSP0) - { - /* Reset the SSP0 registers values*/ - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_SSP0,ENABLE); - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_SSP0,DISABLE); - } - else if (SSPx == SSP1) - { - /* Reset the SSP1 registers values*/ - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_SSP1,ENABLE); - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_SSP1,DISABLE); - } -} - -/******************************************************************************* -* Function Name : SSP_Init -* Description : Initializes the SSPx peripheral according to the specified -* parameters in the SSP_InitTypeDef structure. -* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. -* - SSP_InitStruct: pointer to a SSP_InitTypeDef structure that -* contains the configuration information for the specified SSP -* peripheral. -* Output : None -* Return : None -*******************************************************************************/ -void SSP_Init(SSP_TypeDef* SSPx, SSP_InitTypeDef* SSP_InitStruct) -{ - /* Configure the Frame format */ - if(SSP_InitStruct->SSP_FrameFormat == SSP_FrameFormat_TI) - { - /* Clear the FRF[1:0] bits */ - SSPx->CR0 &= SSP_FrameFormat_Mask; - /* Set the TI frame format */ - SSPx->CR0 |= SSP_FrameFormat_TI; - } - else - { - /* Set the Motorola frame format */ - SSPx->CR0 &= SSP_FrameFormat_Motorola; - /* Configure the Clock polarity */ - if(SSP_InitStruct->SSP_CPOL == SSP_CPOL_High) - { - /* SCK is held high when no data is being transfered */ - SSPx->CR0 |= SSP_CPOL_High; - } - else - { - /* SCK is held low when no data is being transfered */ - SSPx->CR0 &= SSP_CPOL_Low; - } - /* Configure the Clock Phase */ - if(SSP_InitStruct->SSP_CPHA == SSP_CPHA_2Edge) - { - /* Data captured on second clock edge */ - SSPx->CR0 |= SSP_CPHA_2Edge; - } - else - { - /* Data captured on first clock edge */ - SSPx->CR0 &= SSP_CPHA_1Edge; - } - } - - /* Configure the Mode */ - if(SSP_InitStruct->SSP_Mode == SSP_Mode_Slave) - { - /* Set the slave mode */ - SSPx->CR1 |= SSP_Mode_Slave; - /* Configure the Slave output */ - if(SSP_InitStruct->SSP_SlaveOutput == SSP_SlaveOutput_Disable) - { - /* Slave output disabled */ - SSPx->CR1 |= SSP_SlaveOutput_Disable; - } - else - { - /* Slave output enabled */ - SSPx->CR1 &= SSP_SlaveOutput_Enable; - } - /* Configure the NSS pin */ - if(SSP_InitStruct->SSP_NSS == SSP_NSS_Soft) - { - /* Slave selected by software through SSI bit */ - SSPx->CR1 |= SSP_NSS_Soft; - SSPx->CR1 &= SSP_SSI_Reset_Mask; - } - else - { - /* Slave selected by hardware through external SSpin */ - SSPx->CR1 &= SSP_NSS_Hard; - } - /* Configure the Clock rate and prescaler in TI slave mode */ - if(SSP_InitStruct->SSP_FrameFormat == SSP_FrameFormat_TI) - { - /* Clear clock rate SCR[7:0] bits */ - SSPx->CR0 &= SSP_ClockRate_Mask; - /* Set the serial clock rate */ - SSPx->CR0 |= (SSP_InitStruct->SSP_ClockRate<<8); - /* Clear clock prescaler CPSDVSR[7:0] bits */ - SSPx->PR &= SSP_ClockPrescaler_Mask; - /* Set the serial clock prescaler */ - SSPx->PR |= SSP_InitStruct->SSP_ClockPrescaler; - } - } - else - { - /* Set the master mode */ - SSPx->CR1 &= SSP_Mode_Master; - /* Configure the NSS pin */ - if(SSP_InitStruct->SSP_NSS == SSP_NSS_Soft) - { - /* Master selected by software through SSI bit */ - SSPx->CR1 |= SSP_NSS_Soft; - SSPx->CR1 |= SSP_SSI_Set_Mask; - } - else - { - /* Master selected by hardware through external SSpin */ - SSPx->CR1 &= SSP_NSS_Hard; - } - /* Clear clock rate SCR[7:0] bits */ - SSPx->CR0 &= SSP_ClockRate_Mask; - /* Set the serial clock rate */ - SSPx->CR0 |= (SSP_InitStruct->SSP_ClockRate<<8); - /* Clear clock prescaler CPSDVSR[7:0] bits */ - SSPx->PR &= SSP_ClockPrescaler_Mask; - /* Set the serial clock prescaler */ - SSPx->PR |= SSP_InitStruct->SSP_ClockPrescaler; - } - - /* Clear data size DSS[3:0] bits */ - SSPx->CR0 &= SSP_DataSize_Mask; - /* Set the data size */ - SSPx->CR0 |= SSP_InitStruct->SSP_DataSize; -} - -/******************************************************************************* -* Function Name : SSP_StructInit -* Description : Fills each SSP_InitStruct member with its default value. -* Input : SSP_InitStruct : pointer to a SSP_InitTypeDef structure - which will be initialized. -* Output : None -* Return : None -*******************************************************************************/ -void SSP_StructInit(SSP_InitTypeDef* SSP_InitStruct) -{ - /* Initialize the SSP_FrameFormat member */ - SSP_InitStruct->SSP_FrameFormat = SSP_FrameFormat_Motorola; - - /* Initialize the SSP_Mode member */ - SSP_InitStruct->SSP_Mode = SSP_Mode_Master; - - /* Initialize the SSP_CPOL member */ - SSP_InitStruct->SSP_CPOL = SSP_CPOL_Low; - - /* Initialize the SSP_CPHA member */ - SSP_InitStruct->SSP_CPHA = SSP_CPHA_1Edge; - - /* Initialize the SSP_DataSize member */ - SSP_InitStruct->SSP_DataSize = SSP_DataSize_8b; - - /* Initialize the SSP_NSS member */ - SSP_InitStruct->SSP_NSS = SSP_NSS_Hard; - - /* Initialize the SSP_SlaveOutput member */ - SSP_InitStruct->SSP_SlaveOutput = SSP_SlaveOutput_Enable; - - /* Initialize the SSP_ClockRate member */ - SSP_InitStruct->SSP_ClockRate = 0; - - /* Initialize the SSP_ClockPrescaler member */ - SSP_InitStruct->SSP_ClockPrescaler = 0; -} - -/******************************************************************************* -* Function Name : SSP_Cmd -* Description : Enables or disables the specified SSP peripheral. -* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. -* - NewState: new state of the SSPx peripheral. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void SSP_Cmd(SSP_TypeDef* SSPx, FunctionalState NewState) -{ - if(NewState == ENABLE) - { - /* Enable the SSP peripheral */ - SSPx->CR1 |= SSP_Enable; - } - else - { - /* Disable the SSP peripheral */ - SSPx->CR1 &= SSP_Disable; - } -} - -/******************************************************************************* -* Function Name : SSP_ITConfig -* Description : Enables or disables the specified SSP interrupts. -* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. -* - SSP_IT: specifies the SSP interrupts sources to be enabled -* or disabled. This parameter can be any combination of the -* following values: -* - SSP_IT_TxFifo: Transmit FIFO half empty or less interrupt -* - SSP_IT_RxFifo: Receive FIFO half full or less interrupt -* - SSP_IT_RxTimeOut: Receive timeout interrupt -* - SSP_IT_RxOverrun: Receive overrun interrupt -* - NewState: new state of the specified SSP interrupts. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void SSP_ITConfig(SSP_TypeDef* SSPx, u16 SSP_IT, FunctionalState NewState) -{ - if(NewState == ENABLE) - { - /* Enable the selected SSP interrupts */ - SSPx->IMSCR |= SSP_IT; - } - else - { - /* Disable the selected SSP interrupts */ - SSPx->IMSCR &= ~SSP_IT; - } -} - -/******************************************************************************* -* Function Name : SSP_DMACmd -* Description : Configures the SSP0 DMA interface. -* Input : - SSP0_DMAtransfer : specifies the DMA transfer to be -* enabled or disabled. This parameter can be one of the -* following values: -* - SSP0_DMA_Transmit: transmit Fifo DMA transfer -* - SSP0_DMA_Receive: receive Fifo DMA transfer -* - NewState: new state of SSP0 DMA transfer. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void SSP_DMACmd(u16 SSP0_DMAtransfer, FunctionalState NewState) -{ - if(NewState == ENABLE) - { - if(SSP0_DMAtransfer == SSP0_DMA_Transmit) - { - /* Enable DMA for the transmit FIFO */ - SSP0->DMACR |= SSP0_DMA_TransmitEnable; - } - else - { - /* Enable DMA for the receive FIFO */ - SSP0->DMACR |= SSP0_DMA_ReceiveEnable; - } - } - else - { - if(SSP0_DMAtransfer == SSP0_DMA_Transmit) - { - /* Disable DMA for the transmit FIFO */ - SSP0->DMACR &= SSP0_DMA_TransmitDisable; - } - else - { - /* Disable DMA for the receive FIFO */ - SSP0->DMACR &= SSP0_DMA_ReceiveDisable; - } - } -} - -/******************************************************************************* -* Function Name : SSP_DMATxConfig -* Description : Configures the SSP0 DMA transmit transfer. -* Input : - SSP0_DMATxReq : specifies the SSP0 DMA transmit request to -* be enabled. This parameter can be one of the following -* values: -* - SSP0_DMATxReq_Single: Transmit FIFO DMA single -* request enabled -* - SSP0_DMATxReq_Burst: Transmit FIFO DMA burst request -* enabled -* Output : None -* Return : None -*******************************************************************************/ -void SSP_DMATxConfig(u16 SSP0_DMATxReq) -{ - if(SSP0_DMATxReq == SSP0_DMATxReq_Burst) - { - /* Enable DMA transmit burst request */ - SSP0->DMACR |= SSP0_DMATxReq_Burst; - } - else - { - /* Enable DMA transmit single request */ - SSP0->DMACR &= SSP0_DMATxReq_Single; - } -} - -/******************************************************************************* -* Function Name : SSP_DMARxConfig -* Description : Configures the SSP0 DMA receive transfer. -* Input : - SSP0_DMARxReq : specifies the SSP0 DMA receive request to -* be enabled. This parameter can be one of the following -* values: -* - SSP0_DMARxReq_Single: Receive FIFO DMA burst request -* enabled -* - SSP0_DMARxReq_Burst: Receive FIFO DMA single request -* enabled -* Output : None -* Return : None -*******************************************************************************/ -void SSP_DMARxConfig(u16 SSP0_DMARxReq) -{ - if(SSP0_DMARxReq == SSP0_DMARxReq_Burst) - { - /* Enable DMA receive burst request */ - SSP0->DMACR |= SSP0_DMARxReq_Burst; - } - else - { - /* Enable DMA receive single request */ - SSP0->DMACR &= SSP0_DMARxReq_Single; - } -} - -/******************************************************************************* -* Function Name : SSP_SendData -* Description : Transmits a Data through the SSP peripheral. -* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. -* - Data : Data to be transmitted. -* Output : None -* Return : None -*******************************************************************************/ -void SSP_SendData(SSP_TypeDef* SSPx, u16 Data) -{ - /* Write in the DR register the data to be sent */ - SSPx->DR = Data; -} - -/******************************************************************************* -* Function Name : SSP_ReceiveData -* Description : Returns the most recent received data by the SSP peripheral. -* Input : SSPx: where x can be 0 or 1 to select the SSP peripheral. -* Output : None -* Return : The value of the received data. -*******************************************************************************/ -u16 SSP_ReceiveData(SSP_TypeDef* SSPx) -{ - /* Return the data in the DR register */ - return SSPx->DR; -} - -/******************************************************************************* -* Function Name : SSP_LoopBackConfig -* Description : Enables or disables the Loop back mode for the selected SSP -* peripheral. -* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. -* - NewState: new state of the Loop Back mode. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void SSP_LoopBackConfig(SSP_TypeDef* SSPx, FunctionalState NewState) -{ - if(NewState == ENABLE) - { - /* Enable loop back mode */ - SSPx->CR1 |= SSP_LoopBackMode_Enable; - } - else - { - /* Disable loop back mode */ - SSPx->CR1 &= SSP_LoopBackMode_Disable; - } -} - -/******************************************************************************* -* Function Name : SSP_NSSInternalConfig -* Description : Configures by software the NSS pin. -* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. -* - SSP_NSSState: NSS internal state.This parameter can be one -* of the following values: -* - SSP_NSSInternal_Set: Set NSS pin internally -* - SSP_NSSInternal_Reset: Reset NSS pin internally -* Output : None -* Return : None -*******************************************************************************/ -void SSP_NSSInternalConfig(SSP_TypeDef* SSPx, u16 SSP_NSSState) -{ - if(SSP_NSSState == SSP_NSSInternal_Set) - { - /* Set NSS pin internally */ - SSPx->CR1 |= SSP_NSSInternal_Set; - } - else - { - /* Reset NSS pin internally */ - SSPx->CR1 &= SSP_NSSInternal_Reset; - } -} - -/******************************************************************************* -* Function Name : SSP_GetFlagStatus -* Description : Checks whether the specified SSP flag is set or not. -* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. -* - SSP_FLAG: specifies the flag to check. This parameter can -* be one of the following values: -* - SSP_FLAG_Busy: busy flag -* - SSP_FLAG_RxFifoFull: Receive FIFO full flag -* - SSP_FLAG_RxFifoNotEmpty: Receive FIFO not empty flag -* - SSP_FLAG_TxFifoNotFull: Transmit FIFO not full flag -* - SSP_FLAG_TxFifoEmpty: Transmit FIFO empty flag -* - SSP_FLAG_TxFifo: Transmit FIFO half empty or less flag -* - SSP_FLAG_RxFifo: Receive FIFO half full or less flag -* - SSP_FLAG_RxTimeOut: Receive timeout flag -* - SSP_FLAG_RxOverrun: Receive overrun flag -* Output : None -* Return : The new state of SSP_FLAG(SET or RESET). -*******************************************************************************/ -FlagStatus SSP_GetFlagStatus(SSP_TypeDef* SSPx, u16 SSP_FLAG) -{ - u32 SSPReg = 0, FlagPos = 0; - u32 StatusReg = 0; - - /* Get the SSP register index */ - SSPReg = SSP_FLAG >> 5; - - /* Get the flag position */ - FlagPos = SSP_FLAG & SSP_Flag_Mask; - - /* Find the register of the flag to check */ - if(SSPReg == 1) - { - /* The flag to check is in SR register */ - StatusReg = SSPx->SR; - } - else if (SSPReg == 2) - { - /* The flag to check is in RISR register */ - StatusReg = SSPx->RISR; - } - - /* Check the status of the specified SSP flag */ - if((StatusReg & (1 << FlagPos)) != RESET) - { - /* Return SET if the SSP flag is set */ - return SET; - } - else - { - /* Return RESET if the SSP flag is reset */ - return RESET; - } -} - -/******************************************************************************* -* Function Name : SSP_ClearFlag -* Description : Clears the SSPx’s pending flags. -* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. -* - SSP_FLAG: specifies the flag to clear. This parameter can -* be one of the following values: -* - SSP_FLAG_RxTimeOut: Receive timeout flag -* - SSP_FLAG_RxOverrun: Receive overrun flag -* Output : None -* Return : None -*******************************************************************************/ -void SSP_ClearFlag(SSP_TypeDef* SSPx, u16 SSP_FLAG) -{ - u8 FlagPos = 0; - - /* Get the flag position */ - FlagPos = SSP_FLAG & SSP_Flag_Mask; - - /* Clear the selected SSP flag */ - SSPx->ICR = (1 << FlagPos); -} - -/******************************************************************************* -* Function Name : SSP_GetITStatus -* Description : Checks whether the specified SSP interrupt has occurred or not. -* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. -* - SSP_IT: specifies the interrupt source to check. -* This parameter can be one of the following values: -* - SSP_IT_TxFifo: Transmit FIFO half empty or less interrupt -* - SSP_IT_RxFifo: Receive FIFO half full or less interrupt -* - SSP_IT_RxTimeOut: Receive timeout interrupt -* - SSP_IT_RxOverrun: Receive overrun interrupt -* Output : None -* Return : The new state of SSP_IT(SET or RESET). -*******************************************************************************/ -ITStatus SSP_GetITStatus(SSP_TypeDef* SSPx, u16 SSP_IT) -{ - /* Check the status of the specified interrupt flag */ - if((SSPx->MISR & SSP_IT) != RESET) - { - /* Return SET if the SSP interrupt flag is set */ - return SET; - } - else - { - /* Return RESET if SSP interrupt flag is reset */ - return RESET; - } -} - -/******************************************************************************* -* Function Name : SSP_ClearITPendingBit -* Description : Clears the SSPx’s interrupt pending bits. -* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. -* - SSP_IT: specifies the interrupt pending bit to clear. -* This parameter can be any combination of the following values: -* - SSP_IT_RxTimeOut: Receive timeout interrupt -* - SSP_IT_RxOverrun: Receive overrun interrupt -* Output : None -* Return : None -*******************************************************************************/ -void SSP_ClearITPendingBit(SSP_TypeDef* SSPx, u16 SSP_IT) -{ - /* Clear the selected SSP interrupts pending bits */ - SSPx->ICR = SSP_IT; -} - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_tb.c b/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_tb.c deleted file mode 100644 index 4f461f997..000000000 --- a/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_tb.c +++ /dev/null @@ -1,425 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_tb.c -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file provides all the TB software functions. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -#include "75x_tb.h" -#include "75x_mrcc.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -#define TB_IT_Enable_Mask 0x7FFF -#define TB_IT_Clear_Mask 0x7FFF -#define TB_IC_Enable 0x0004 -#define TB_ICPolarity_Set 0x0008 -#define TB_ICPolarity_Reset 0xFFF7 -#define TB_UFS_Reset 0xFFFE -#define TB_UFS_Set 0x0001 - -/* TB debug state */ -#define TB_DBGC_Set 0x0400 -#define TB_DBGC_Reset 0xFB7F - -/* TB counter state */ -#define TB_COUNTER_Reset 0x0002 -#define TB_COUNTER_Start 0x0004 -#define TB_COUNTER_Stop 0xFFFB - -#define TB_SMS_EXTCLK_Set 0x0008 -#define TB_SMS_RESETCLK_Set 0x0000 - -/* TB Slave Mode Enable Set/Reset value */ -#define TB_SME_Reset 0x731B -#define TB_SME_Set 0x0004 - -/* TB Trigger Selection value */ -#define TB_TS_IC1_Set 0x0200 - -/* TB SCR Masks bit */ -#define TB_SlaveModeSelection_Mask 0x7307 -#define TB_TriggerSelection_Mask 0x701F - -/* Reset Register Masks */ -#define TB_Prescaler_Reset_Mask 0x0000 -#define TB_CounterMode_Mask 0xFF8F -#define TB_AutoReload_Reset_Mask 0xFFFF - -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - - /****************************************************************************** -* Function Name : TB_DeInit -* Description : Deinitializes the TB peripheral registers to their default -* reset values. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void TB_DeInit(void) -{ - /* Enters and exits the TB peripheral to and from reset */ - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TB,ENABLE); - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TB,DISABLE); -} - -/******************************************************************************* -* Function Name : TB_Init -* Description : Initializes TB peripheral according to the specified -* parameters in the TB_InitStruct. -* Input : TB_InitStruct: pointer to a TB_InitTypeDef structure that -* contains the configuration information for the TB peripheral. -* Output : None -* Return : None -*******************************************************************************/ -void TB_Init(TB_InitTypeDef* TB_InitStruct) -{ - /* Set the TB prescaler value */ - TB->PSC = TB_InitStruct->TB_Prescaler; - - /* Set the TB period value */ - TB->ARR = TB_InitStruct->TB_AutoReload; - - /* Set the corresponding counter mode */ - TB->CR = (TB->CR & TB_CounterMode_Mask) | TB_InitStruct->TB_CounterMode; - - /* Set the corresponding clock source */ - if(TB_InitStruct->TB_ClockSource == TB_ClockSource_CKRTC) - { - TB->SCR &= TB_SME_Reset & TB_SlaveModeSelection_Mask & TB_TriggerSelection_Mask; - TB->SCR |= TB_SMS_EXTCLK_Set | TB_SME_Set | TB_TS_IC1_Set; - } - else - { - TB->SCR &= TB_SME_Reset & TB_SlaveModeSelection_Mask & TB_TriggerSelection_Mask; - } - - if(TB_InitStruct->TB_Mode == TB_Mode_IC) - { - /* Set the corresponding value in TB SCR register */ - TB->SCR &= TB_SME_Reset & TB_SlaveModeSelection_Mask & TB_TriggerSelection_Mask; - TB->SCR |= TB_SMS_RESETCLK_Set | TB_SME_Set | TB_TS_IC1_Set; - - /* Set the IC1 enable bit */ - TB->IMCR |= TB_IC_Enable; - - /* Set the input signal polarity */ - if (TB_InitStruct->TB_ICAPolarity == TB_ICAPolarity_Falling) - { - TB->IMCR |= TB_ICPolarity_Set; - } - else - { - TB->IMCR &= TB_ICPolarity_Reset; - } - } -} - -/******************************************************************************* -* Function Name : TB_StructInit -* Description : Fills each TB_InitStruct member with its default value -* Input : TB_InitStruct : pointer to a TB_InitTypeDef structure which -* will be initialized. -* Output : None -* Return : None -*******************************************************************************/ -void TB_StructInit(TB_InitTypeDef *TB_InitStruct) -{ - TB_InitStruct->TB_Mode = TB_Mode_Timing; - TB_InitStruct->TB_ClockSource = TB_ClockSource_CKTIM; - TB_InitStruct->TB_CounterMode = TB_CounterMode_Up; - TB_InitStruct->TB_ICAPolarity = TB_ICAPolarity_Rising; - TB_InitStruct->TB_Prescaler = TB_Prescaler_Reset_Mask; - TB_InitStruct->TB_AutoReload = TB_AutoReload_Reset_Mask; -} - -/******************************************************************************* -* Function Name : TB_Cmd -* Description : Enables or disables the TB peripheral. -* Input : Newstate: new state of the TB peripheral. This parameter can -* be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void TB_Cmd(FunctionalState Newstate) -{ - if(Newstate == ENABLE) - { - TB->CR |= TB_COUNTER_Start; - } - else - { - TB->CR &= TB_COUNTER_Stop; - } -} - -/******************************************************************************* -* Function Name : TB_ITConfig -* Description : Enables or disables the specified TB interrupt. -* Input : - TB_IT: specifies the TB interrupt sources to be enabled or -* disabled. -* This parameter can be any combination of the following values: -* - TB_IT_Update: TB Update interrupt -* - TB_IT_GlobalUpdate: TB Global Update interrupt -* - TB_IT_IC: TB Input Capture interrupt -* - Newstate: new state of the specified TB interrupts. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void TB_ITConfig(u16 TB_IT, FunctionalState Newstate) -{ - u16 TB_IT_Enable = 0; - - TB_IT_Enable = TB_IT & TB_IT_Enable_Mask; - - if(Newstate == ENABLE) - { - /* Update interrupt global source: overflow/undeflow, counter reset operation - or slave mode controller in reset mode */ - if ((TB_IT & TB_IT_GlobalUpdate) == TB_IT_GlobalUpdate) - { - TB->CR &= TB_UFS_Reset; - } - /* Update interrupt source: counter overflow/underflow */ - else if ((TB_IT & TB_IT_Update) == TB_IT_Update) - { - TB->CR |= TB_UFS_Set; - } - /* Select and enable the interrupts requests */ - TB->RSR |= TB_IT_Enable; - TB->RER |= TB_IT_Enable; - } - /* Disable the interrupts requests */ - else - { - TB->RSR &= ~TB_IT_Enable; - TB->RER &= ~TB_IT_Enable; - } -} - -/******************************************************************************* -* Function Name : TB_SetPrescaler -* Description : Sets the TB Prescaler value. -* Input : Prescaler: specifies the TB Prescaler value. -* Output : None -* Return : None -*******************************************************************************/ -void TB_SetPrescaler(u16 Prescaler) -{ - /* Sets the prescaler value */ - TB->PSC = Prescaler; -} - -/******************************************************************************* -* Function Name : TB_ResetCounter -* Description : Re-intializes the counter and generates an update of the -* registers. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void TB_ResetCounter(void) -{ - /* Re-intializes TB counter */ - TB->CR |= TB_COUNTER_Reset; -} - -/******************************************************************************* -* Function Name : TB_DebugCmd -* Description : Enables or disables TB peripheral Debug control. -* Input : Newstate: new state of the TB Debug control. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void TB_DebugCmd(FunctionalState Newstate) -{ - if(Newstate == ENABLE) - { - TB->CR |= TB_DBGC_Set; - } - else - { - TB->CR &= TB_DBGC_Reset; - } -} - -/******************************************************************************* -* Function Name : TB_CounterModeConfig -* Description : Configures the TB Counter Mode. -* Input : TB_CounterMode: specifies the TB counter mode to be used. -* This parameter can be one of the following values: -* - TB_CounterMode_Up: TB Up Counting Mode -* - TB_CounterMode_Down: TB Down Counting Mode -* - TB_CounterMode_CenterAligned: TB Center Aligned Mode -* Output : None -* Return : None -*******************************************************************************/ -void TB_CounterModeConfig(u16 TB_CounterMode) -{ - /* Counter mode configuration */ - TB->CR &= TB_CounterMode_Mask; - TB->CR |= TB_CounterMode; -} - -/******************************************************************************* -* Function Name : TB_SLaveModeConfig -* Description : Configures the TB slave Mode. -* Input : TB_SMSMode: specifies the TB slave mode to be used. -* This parameter can be one of the following values: -* - TB_SMSMode_Trigger: The counter starts at a rising -* edge of the trigger -* - TB_SMSMode_Gated: The counter clock is enabled when -* trigger signal is high -* - TB_SMSMode_External: The rising edge of selected trigger -* clocks the counter -* - TB_SMSMode_Reset: The rising edge of the selected -* trigger signal resets the counter -* Output : None -* Return : None -*******************************************************************************/ -void TB_SLaveModeConfig(u16 TB_SMSMode) -{ - TB->SCR &= TB_SME_Reset & TB_SlaveModeSelection_Mask & TB_TriggerSelection_Mask; - TB->SCR |= TB_SME_Set | TB_SMSMode | TB_TS_IC1_Set; -} -/******************************************************************************* -* Function Name : TB_GetCounter -* Description : Gets the TB Counter value. -* Input : None -* Output : None -* Return : The TB counter register value. -*******************************************************************************/ -u16 TB_GetCounter(void) -{ - return TB->CNT; -} - -/******************************************************************************* -* Function Name : TB_GetICAP1 -* Description : Gets the TB Input capture value. -* Input : None -* Output : None -* Return : The TB ICR1 register value. -*******************************************************************************/ -u16 TB_GetICAP1(void) -{ - return TB->ICR1; -} - -/******************************************************************************* -* Function Name : TB_SetCounter -* Description : Sets the TB Counter value. -* Input : Counter: specifies the TB Counter value. -* Output : None -* Return : None -*******************************************************************************/ -void TB_SetCounter(u16 Counter) -{ - TB->CNT = Counter; -} - -/******************************************************************************* -* Function Name : TB_GetFlagStatus -* Description : Checks whether the specified TB flag is set or not. -* Input : TB_FLAG: specifies the flag to check. -* This parameter can be one of the following values: -* - TB_FLAG_IC: TB Input Capture flag -* - TB_FLAG_Update: TB update flag -* Output : None -* Return : The new state of the TB_FLAG (SET or RESET). -*******************************************************************************/ -FlagStatus TB_GetFlagStatus(u16 TB_FLAG) -{ - if((TB->ISR & TB_FLAG) != RESET ) - { - return SET; - } - else - { - return RESET; - } -} - -/******************************************************************************* -* Function Name : TB_ClearFlag -* Description : Clears the TB’s pending flags. -* Input : TB_FLAG: specifies the flag to clear. -* This parameter can be any combination of the following values: -* - TB_FLAG_IC: TB Input Capture flag -* - TB_FLAG_Update: TB update flag -* Output : None -* Return : None -*******************************************************************************/ -void TB_ClearFlag(u16 TB_FLAG) -{ - /* Clears the flags */ - TB->ISR &= ~TB_FLAG; -} - -/******************************************************************************* -* Function Name : TB_GetITStatus -* Description : Checks whether the specified TB interrupt has occurred or not. -* Input : TB_IT: specifies the interrupt to check. -* This parameter can be one of the following values: -* - TB_IT_Update: TB Update interrupt -* - TB_IT_GlobalUpdate: TB Global Update interrupt -* - TB_IT_IC: TB Input Capture interrupt -* Output : None -* Return : The new state of the TB_IT (SET or RESET). -*******************************************************************************/ -ITStatus TB_GetITStatus(u16 TB_IT) -{ - u16 TB_IT_Check = 0; - - /* Calculates the pending bits to be checked */ - TB_IT_Check = TB_IT & TB_IT_Clear_Mask; - - if((TB->ISR & TB_IT_Check) != RESET ) - { - return SET; - } - else - { - return RESET; - } -} - -/******************************************************************************* -* Function Name : TB_ClearITPendingBit -* Description : Clears the TB's interrupt pending bits. -* Input : TB_IT: specifies the interrupt pending bit to clear. -* This parameter can be any combination of the following values: -* - TB_IT_Update: TB Update interrupt -* - TB_IT_GlobalUpdate: TB Global Update interrupt -* - TB_IT_IC: TB Input Capture interrupt -* Output : None -* Return : None -*******************************************************************************/ -void TB_ClearITPendingBit(u16 TB_IT) -{ - u16 TB_IT_Clear = 0; - - /* Calculates the pending bits to be cleared */ - TB_IT_Clear = TB_IT & TB_IT_Clear_Mask; - - /* Clears the pending bits */ - TB->ISR &= ~TB_IT_Clear; -} -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_tim.c b/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_tim.c deleted file mode 100644 index d23d97965..000000000 --- a/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_tim.c +++ /dev/null @@ -1,1360 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_tim.c -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file provides all the TIM software functions. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -#include "75x_tim.h" -#include "75x_mrcc.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* TIM interrupt masks */ -#define TIM_IT_Clear_Mask 0x7FFF -#define TIM_IT_Enable_Mask 0x7FFF - -/* TIM Input Capture Selection Set/Reset */ -#define TIM_IC1S_Set 0x0001 -#define TIM_IC1S_Reset 0x003E - -/* TIM Input Capture Selection Set/Reset */ -#define TIM_IC2S_Set 0x0002 -#define TIM_IC2S_Reset 0x003D - -/* TIM_SCR Masks bit */ -#define TIM_Encoder_Mask 0x731C -#define TIM_SlaveModeSelection_Mask 0x7307 -#define TIM_TriggerSelection_Mask 0x701F -#define TIM_InternalTriggerSelection_Mask 0x031F - -/* TIM Encoder mode Set value */ -#define TIM_Encoder1_Set 0x0001 -#define TIM_Encoder2_Set 0x0002 -#define TIM_Encoder3_Set 0x0003 - -/* TIM Slave Mode Enable Set/Reset value */ -#define TIM_SME_Reset 0x731B -#define TIM_SME_Set 0x0004 - -/* TIM Internal Trigger Selection value */ -#define TIM_ITS_TIM0 0x1000 -#define TIM_ITS_TIM1 0x2000 -#define TIM_ITS_TIM2 0x3000 -#define TIM_ITS_PWM 0x4000 - -/* TIM Trigger Selection value */ -#define TIM_TS_IC1_Set 0x0200 -#define TIM_TS_IC2_Set 0x0300 - -/* TIM Slave Mode selction external clock Set value */ -#define TIM_SMS_EXTCLK_Set 0x0008 -#define TIM_SMS_RESETCLK_Set 0x0000 - -/* TIM_CR Masks bit */ -#define TIM_DBASE_Mask 0x077F -#define TIM_MasterModeSelection_Mask 0xFC7F -#define TIM_CounterMode_Mask 0xFF8F - -/* TIM Update flag selection Set/Reset value */ -#define TIM_UFS_Reset 0xFFFE -#define TIM_UFS_Set 0x0001 - -/* TIM Counter value */ -#define TIM_COUNTER_Reset 0x0002 -#define TIM_COUNTER_Start 0x0004 -#define TIM_COUNTER_Stop 0xFFFB - -/* TIM One pulse Mode set value */ -#define TIM_OPM_Set 0x0008 -#define TIM_OPM_Reset 0xFFF7 - -/* TIM Debug Mode Set/Reset value */ -#define TIM_DBGC_Set 0x0400 -#define TIM_DBGC_Reset 0xFB7F - -/* TIM Input Capture Enable/Disable value */ -#define TIM_IC1_Enable 0x0004 -#define TIM_IC2_Enable 0x0010 - -/* TIM Input Capture Polarity Set/Reset value */ -#define TIM_IC1P_Set 0x0008 -#define TIM_IC2P_Set 0x0020 -#define TIM_IC1P_Reset 0x0037 -#define TIM_IC2P_Reset 0x001F - -/* TIM Output Compare Polarity Set/Reset value */ -#define TIM_OC1P_Set 0x0020 -#define TIM_OC2P_Set 0x2000 -#define TIM_OC1P_Reset 0x3F1F -#define TIM_OC2P_Reset 0x1F3F - -/* TIM Output Compare control mode constant */ -#define TIM_OCControl_PWM 0x000C -#define TIM_OCControl_OCToggle 0x0006 -#define TIM_OCControl_OCInactive 0x0004 -#define TIM_OCControl_OCActive 0x0002 -#define TIM_OCControl_OCTiming 0x0000 - -/* TIM Output Compare mode Enable value */ -#define TIM_OC1_Enable 0x0010 -#define TIM_OC2_Enable 0x1000 - -/* TIM Output Compare mode Mask value */ -#define TIM_OC1C_Mask 0x3F31 -#define TIM_OC2C_Mask 0x313F - -/* TIM Preload bit Set/Reset value */ -#define TIM_PLD1_Set 0x0001 -#define TIM_PLD1_Reset 0xFFFE - -#define TIM_PLD2_Set 0x0100 -#define TIM_PLD2_Reset 0xFEFF - -/* TIM OCRM Set/Reset value */ -#define TIM_OCRM_Set 0x0080 -#define TIM_OCRM_Reset 0x030D - -/* Reset Register Masks */ -#define TIM_Pulse2_Reset_Mask 0x0000 -#define TIM_Prescaler_Reset_Mask 0x0000 -#define TIM_Pulse1_Reset_Mask 0x0000 -#define TIM_Period_Reset_Mask 0xFFFF -#define TIM_Counter_Reset 0x0002 - -/* Private function prototypes -----------------------------------------------*/ -static void ICAP_ModuleConfig(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct); -static void Encoder_ModeConfig(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct); -static void OCM_ModuleConfig(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct); - -/* Private functions ---------------------------------------------------------*/ - -/****************************************************************************** -* Function Name : TIM_DeInit -* Description : Deinitializes TIM peripheral registers to their default reset -* values. -* Input : TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. -* Output : None -* Return : None -*******************************************************************************/ -void TIM_DeInit(TIM_TypeDef *TIMx) -{ - if(TIMx == TIM0) - { - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TIM0,ENABLE); - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TIM0,DISABLE); - } - else if(TIMx == TIM1) - { - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TIM1,ENABLE); - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TIM1,DISABLE); - } - else if(TIMx == TIM2) - { - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TIM2,ENABLE); - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TIM2,DISABLE); - } -} - -/******************************************************************************* -* Function Name : TIM_Init -* Description : Initializes the TIMx peripheral according to the specified -* parameters in the TIM_InitStruct . -* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. -* - TIM_InitStruct: pointer to a TIM_InitTypeDef structure that -* contains the configuration information for the specified TIM -* peripheral. -* Output : None -* Return : None -*******************************************************************************/ -void TIM_Init(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct) -{ - /* Set the prescaler value */ - TIMx->PSC = TIM_InitStruct->TIM_Prescaler; - - /* Select the clock source */ - TIM_ClockSourceConfig(TIMx, TIM_InitStruct->TIM_ClockSource, - TIM_InitStruct->TIM_ExtCLKEdge); - - /* Select the counter mode */ - TIMx->CR &= TIM_CounterMode_Mask; - TIMx->CR |= TIM_InitStruct->TIM_CounterMode; - - /* Set the period value */ - TIMx->ARR = TIM_InitStruct->TIM_Period; - - switch(TIM_InitStruct->TIM_Mode) - { - case TIM_Mode_OCTiming: case TIM_Mode_OCActive: case TIM_Mode_OCInactive: - case TIM_Mode_OCToggle: case TIM_Mode_PWM: - OCM_ModuleConfig(TIMx, TIM_InitStruct); - break; - - case TIM_Mode_PWMI: case TIM_Mode_IC: - ICAP_ModuleConfig(TIMx, TIM_InitStruct); - break; - - case TIM_Mode_Encoder1: case TIM_Mode_Encoder2: case TIM_Mode_Encoder3: - Encoder_ModeConfig(TIMx, TIM_InitStruct); - break; - - case TIM_Mode_OPM_PWM: case TIM_Mode_OPM_Toggle: case TIM_Mode_OPM_Active: - - /* Output module configuration */ - OCM_ModuleConfig(TIMx, TIM_InitStruct); - - /* Input module configuration */ - ICAP_ModuleConfig(TIMx, TIM_InitStruct); - - /* Set the slave mode to trigger Mode */ - TIMx->SCR |= TIM_SynchroMode_Trigger; - - /* Repetitive pulse state selection */ - if(TIM_InitStruct->TIM_RepetitivePulse == TIM_RepetitivePulse_Disable) - { - TIMx->CR |= TIM_OPM_Set; - } - else - { - TIMx->CR &= TIM_OPM_Reset; - } - break; - - default: - break; - } -} - -/******************************************************************************* -* Function Name : TIM_StructInit -* Description : Fills each TIM_InitStruct member with its default value. -* Input : TIM_InitStruct : pointer to a TIM_InitTypeDef structure -* which will be initialized. -* Output : None -* Return : None. -*******************************************************************************/ -void TIM_StructInit(TIM_InitTypeDef *TIM_InitStruct) -{ - /* Set the default configuration */ - TIM_InitStruct->TIM_Mode = TIM_Mode_OCTiming; - TIM_InitStruct->TIM_Prescaler = TIM_Prescaler_Reset_Mask; - TIM_InitStruct->TIM_ClockSource = TIM_ClockSource_Internal; - TIM_InitStruct->TIM_ExtCLKEdge = TIM_ExtCLKEdge_Rising; - TIM_InitStruct->TIM_CounterMode = TIM_CounterMode_Up; - TIM_InitStruct->TIM_Period = TIM_Period_Reset_Mask; - TIM_InitStruct->TIM_Channel = TIM_Channel_ALL; - TIM_InitStruct->TIM_Pulse1 = TIM_Pulse1_Reset_Mask; - TIM_InitStruct->TIM_Pulse2 = TIM_Pulse2_Reset_Mask; - TIM_InitStruct->TIM_RepetitivePulse = TIM_RepetitivePulse_Disable; - TIM_InitStruct->TIM_Polarity1 = TIM_Polarity1_Low; - TIM_InitStruct->TIM_Polarity2 = TIM_Polarity2_Low; - TIM_InitStruct->TIM_IC1Selection = TIM_IC1Selection_TI1; - TIM_InitStruct->TIM_IC2Selection = TIM_IC2Selection_TI1; - TIM_InitStruct->TIM_IC1Polarity = TIM_IC1Polarity_Rising; - TIM_InitStruct->TIM_IC2Polarity = TIM_IC2Polarity_Rising; - TIM_InitStruct->TIM_PWMI_ICSelection = TIM_PWMI_ICSelection_TI1; - TIM_InitStruct->TIM_PWMI_ICPolarity = TIM_PWMI_ICPolarity_Rising; -} - -/******************************************************************************* -* Function Name : TIM_Cmd -* Description : Enables or disables the specified TIM peripheral. -* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. -* - Newstate: new state of the TIMx peripheral. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState Newstate) -{ - if(Newstate == ENABLE) - { - TIMx->CR |= TIM_COUNTER_Start; - } - else - { - TIMx->CR &= TIM_COUNTER_Stop; - } -} - -/******************************************************************************* -* Function Name : TIM_ITConfig -* Description : Enables or disables the TIM interrupts. -* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. -* - TIM_IT: specifies the TIM interrupts sources to be enabled -* or disabled. -* This parameter can be any combination of the following values: -* - TIM_IT_IC1: Input Capture 1 Interrupt -* - TIM_IT_OC1: Output Compare 1 Interrupt -* - TIM_IT_Update: Timer update Interrupt -* - TIM_IT_GlobalUpdate: Timer global update Interrupt -* - TIM_IT_IC2: Input Capture 2 Interrupt -* - TIM_IT_OC2: Output Compare 2 Interrupt -* - Newstate: new state of the specified TIMx interrupts. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void TIM_ITConfig(TIM_TypeDef *TIMx, u16 TIM_IT, FunctionalState Newstate) -{ - u16 TIM_IT_Enable = 0; - - TIM_IT_Enable = TIM_IT & TIM_IT_Enable_Mask; - - if(Newstate == ENABLE) - { - /* Update interrupt global source: overflow/undeflow, counter reset operation - or slave mode controller in reset mode */ - if((TIM_IT & TIM_IT_GlobalUpdate) == TIM_IT_GlobalUpdate) - { - TIMx->CR &= TIM_UFS_Reset; - } - /* Update interrupt source: counter overflow/underflow */ - else if((TIM_IT & TIM_IT_Update) == TIM_IT_Update) - { - TIMx->CR |= TIM_UFS_Set; - } - /* Select and enable the interrupts requests */ - TIMx->RSR |= TIM_IT_Enable; - TIMx->RER |= TIM_IT_Enable; - } - /* Disable the interrupts requests */ - else - { - TIMx->RSR &= ~TIM_IT_Enable; - TIMx->RER &= ~TIM_IT_Enable; - } -} - -/******************************************************************************* -* Function Name : TIM_PreloadConfig -* Description : Enables or disables TIM peripheral Preload register on OCRx. -* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. -* - TIM_Channel: specifies the TIM channel to be used. -* This parameter can be one of the following values: -* - TIM_Channel_1: TIM Channel 1 is used -* - TIM_Channel_2: TIM Channel 2 is used -* - TIM_Channel_ALL: TIM Channel 1and 2 are used -* - Newstate: new state of the TIMx peripheral Preload register -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void TIM_PreloadConfig(TIM_TypeDef *TIMx, u16 TIM_Channel, FunctionalState Newstate) -{ - if(Newstate == ENABLE) - { - switch (TIM_Channel) - { - case TIM_Channel_1: - TIMx->OMR1 |= TIM_PLD1_Set; - break; - - case TIM_Channel_2: - TIMx->OMR1 |= TIM_PLD2_Set; - break; - - case TIM_Channel_ALL: - TIMx->OMR1 |= TIM_PLD1_Set | TIM_PLD2_Set; - break; - - default: - break; - } - } - else - { - switch (TIM_Channel) - { - case TIM_Channel_1: - TIMx->OMR1 &= TIM_PLD1_Reset; - break; - - case TIM_Channel_2: - TIMx->OMR1 &= TIM_PLD2_Reset; - break; - - case TIM_Channel_ALL: - TIMx->OMR1 &= TIM_PLD1_Reset & TIM_PLD2_Reset; - break; - - default: - break; - } - } -} - -/******************************************************************************* -* Function Name : TIM_DMAConfig -* Description : Configures the TIM0’s DMA interface. -* Input : - TIM_DMASources: specifies the DMA Request sources. -* This parameter can be any combination of the following values: -* - TIM_DMASource_OC1: Output Compare 1 DMA source -* - TIM_DMASource_OC2: Output Compare 2 DMA source -* - TIM_DMASource_IC1: Input Capture 1 DMA source -* - TIM_DMASource_IC2: Input Capture 2 DMA source -* - TIM_DMASource_Update: Timer Update DMA source -* - TIM_OCRMState: the state of output compare request mode. -* This parameter can be one of the following values: -* - TIM_OCRMState_Enable -* - TIM_OCRMState_Disable -* - TIM_DMABase:DMA Base address. -* This parameter can be one of the following values: -* TIM_DMABase_CR, TIM_DMABase_SCR, TIM_DMABase_IMCR, -* TIM_DMABase_OMR1, TIM_DMABase_RSR, -* TIM_DMABase_RER, TIM_DMABase_ISR, TIM_DMABase_CNT, -* TIM_DMABase_PSC, TIM_DMABase_ARR, TIM_DMABase_OCR1, -* TIM_DMABase_OCR2, TIM_DMABase_ICR1, TIM_DMABase_ICR2 -* Output : None -* Return : None -*******************************************************************************/ -void TIM_DMAConfig(u16 TIM_DMASources, u16 TIM_OCRMState, u16 TIM_DMABase) -{ - /* Select the DMA requests */ - TIM0->RSR &= TIM_DMASources; - - /* Set the OCRM state */ - if(TIM_OCRMState == TIM_OCRMState_Enable) - { - TIM0->RSR |= TIM_OCRM_Set; - } - else - { - TIM0->RSR &= TIM_OCRM_Reset; - } - - /* Set the DMA Base address */ - TIM0->CR &= TIM_DBASE_Mask; - TIM0->CR |= TIM_DMABase; -} - -/******************************************************************************* -* Function Name : TIM_DMACmd -* Description : Enables or disables the TIM0’s DMA interface. -* Input : - TIM_DMASources: specifies the DMA Request sources. -* This parameter can be any combination of the following values: -* - TIM_DMASource_OC1: Output Compare 1 DMA source -* - TIM_DMASource_OC2: Output Compare 2 DMA source -* - TIM_DMASource_IC1: Input Capture 1 DMA source -* - TIM_DMASource_IC2: Input Capture 2 DMA source -* - TIM_DMASource_Update: Timer Update DMA source -* - Newstate: new state of the DMA Request sources. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void TIM_DMACmd(u16 TIM_DMASources, FunctionalState Newstate) -{ - if(Newstate == ENABLE) - { - TIM0->RER |= TIM_DMASources; - } - else - { - TIM0->RER &= ~TIM_DMASources; - } -} - -/******************************************************************************* -* Function Name : TIM_ClockSourceConfig -* Description : Configures the TIM clock source. -* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. -* - TIM_ClockSource: specifies the TIM clock source to be -* selected. -* This parameter can be one of the following values: -* - TIM_ClockSource_Internal: CK_TIM internal clock -* - TIM_ClockSource_TI11: External input pin TI1 -* connected to IC1 channel. -* - TIM_ClockSource_TI12: External input pin TI1 -* connected to IC2 channel. -* - TIM_ClockSource_TI22: External input pin TI2 -* connected to IC2 channel. -* - TIM_ClockSource_TI21: External input pin TI2 -* connected to IC1 channel. -* - TIM_ExtCLKEdge: specifies the External input signal edge. -* This parameter can be one of the following values: -* - TIM_ExtCLKEdge_Falling : Falling edge selected. -* - TIM_ExtCLKEdge_Rising : Rising edge selected. -* Output : None -* Return : None -*******************************************************************************/ -void TIM_ClockSourceConfig(TIM_TypeDef *TIMx, u16 TIM_ClockSource, - u16 TIM_ExtCLKEdge) -{ - if(TIM_ClockSource == TIM_ClockSource_Internal) - { - /* CK_TIM is used as clock source */ - TIMx->SCR &= TIM_SME_Reset & TIM_SlaveModeSelection_Mask & TIM_TriggerSelection_Mask; - } - else - /* Input Captures are used as TIM external clock */ - { - TIMx->SCR &= TIM_SME_Reset & TIM_SlaveModeSelection_Mask & TIM_TriggerSelection_Mask; - TIMx->SCR |= TIM_SMS_EXTCLK_Set | TIM_SME_Set; - - if((TIM_ClockSource == TIM_ClockSource_TI11) || - (TIM_ClockSource == TIM_ClockSource_TI21)) - /* Input Capture 1 is selected */ - { - /* Input capture Enable */ - TIMx->IMCR |= TIM_IC1_Enable; - TIMx->SCR |= TIM_TS_IC1_Set; - - if(TIM_ExtCLKEdge == TIM_ExtCLKEdge_Falling) - /* Set the corresponding polarity */ - { - TIMx->IMCR |= TIM_IC1P_Set; - } - else - { - TIMx->IMCR &= TIM_IC1P_Reset; - } - if(TIM_ClockSource == TIM_ClockSource_TI11) - { - /* External signal TI1 connected to IC1 channel */ - TIMx->IMCR &= TIM_IC1S_Reset; - } - else - { - /* External signal TI2 connected to IC1 channel */ - TIMx->IMCR |= TIM_IC1S_Set; - } - } - else - /* Input Capture 2 is selected */ - { - /* Input capture Enable */ - TIMx->IMCR |= TIM_IC2_Enable; - TIMx->SCR |= TIM_TS_IC2_Set; - - if(TIM_ExtCLKEdge == TIM_ExtCLKEdge_Falling) - /* Set the corresponding polarity */ - { - TIMx->IMCR |= TIM_IC2P_Set; - } - else - { - TIMx->IMCR &= TIM_IC2P_Reset; - } - if(TIM_ClockSource == TIM_ClockSource_TI22) - { - /* External signal TI2 connected to IC2 channel */ - TIMx->IMCR &= TIM_IC2S_Reset; - } - else - { - /* External signal TI1 connected to IC2 channel */ - TIMx->IMCR |= TIM_IC2S_Set; - } - } - } -} - -/******************************************************************************* -* Function Name : TIM_SetPrescaler -* Description : Sets the TIM prescaler value. -* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral -* - Prescaler: TIM prescaler new value. -* Output : None -* Return : None -*******************************************************************************/ -void TIM_SetPrescaler(TIM_TypeDef* TIMx, u16 Prescaler) -{ - TIMx->PSC = Prescaler; -} - -/******************************************************************************* -* Function Name : TIM_SetPeriod -* Description : Sets the TIM period value. -* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral -* - Period: TIM period new value. -* Output : None -* Return : None -*******************************************************************************/ -void TIM_SetPeriod(TIM_TypeDef* TIMx, u16 Period) -{ - TIMx->ARR = Period; -} - -/******************************************************************************* -* Function Name : TIM_SetPulse -* Description : Sets the TIM pulse value. -* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral -* - TIM_Channel: specifies the TIM channel to be used. -* This parameter can be one of the following values: -* - TIM_Channel_1: TIM Channel 1 is used -* - TIM_Channel_2: TIM Channel 2 is used -* - TIM_Channel_ALL: TIM Channel 1and 2 are used -* - Pulse: TIM pulse new value. -* Output : None -* Return : None -*******************************************************************************/ -void TIM_SetPulse(TIM_TypeDef* TIMx, u16 TIM_Channel, u16 Pulse) -{ - /* Set Channel 1 pulse value */ - if(TIM_Channel == TIM_Channel_1) - { - TIMx->OCR1 = Pulse; - } - /* Set Channel 2 pulse value */ - else if(TIM_Channel == TIM_Channel_2) - { - TIMx->OCR2 = Pulse; - } - /* Set Channel 1 and Channel 2 pulse values */ - else if(TIM_Channel == TIM_Channel_ALL) - { - TIMx->OCR1 = Pulse; - TIMx->OCR2 = Pulse; - } -} - -/******************************************************************************* -* Function Name : TIM_GetICAP1 -* Description : Gets the Input Capture 1 value. -* Input : TIMx: where x can be 0, 1 or 2 to select the TIM peripheral -* Output : None -* Return : Input Capture 1 Register value. -*******************************************************************************/ -u16 TIM_GetICAP1(TIM_TypeDef *TIMx) -{ - return TIMx->ICR1; -} - -/******************************************************************************* -* Function Name : TIM_GetICAP2 -* Description : Gets the Input Capture 2 value. -* Input : TIMx: where x can be 0, 1 or 2 to select the TIM peripheral -* Output : None -* Return : Input Capture 2 Register value -*******************************************************************************/ -u16 TIM_GetICAP2(TIM_TypeDef *TIMx) -{ - return TIMx->ICR2; -} - -/******************************************************************************* -* Function Name : TIM_GetPWMIPulse -* Description : Gets the PWM Input pulse value. -* Input : TIMx: where x can be 0, 1 or 2 to select the TIM peripheral -* Output : None -* Return : Input Capture 2 Register value -*******************************************************************************/ -u16 TIM_GetPWMIPulse(TIM_TypeDef *TIMx) -{ - return TIMx->ICR2; -} - -/******************************************************************************* -* Function Name : TIM_GetPWMIPeriod -* Description : Gets the PWM Input period value. -* Input : TIMx: where x can be 0, 1 or 2 to select the TIM peripheral -* Output : None -* Return : Input Capture 1 Register value -*******************************************************************************/ -u16 TIM_GetPWMIPeriod(TIM_TypeDef *TIMx) -{ - return TIMx->ICR1; -} - -/******************************************************************************* -* Function Name : TIM_DebugCmd -* Description : Enables or disables the specified TIM peripheral Debug control. -* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral -* - Newstate: new state of the TIMx Debug control. - This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void TIM_DebugCmd(TIM_TypeDef *TIMx, FunctionalState Newstate) -{ - if(Newstate == ENABLE) - { - TIMx->CR |= TIM_DBGC_Set; - } - else - { - TIMx->CR &= TIM_DBGC_Reset; - } -} - -/******************************************************************************* -* Function Name : TIM_CounterModeConfig -* Description : Specifies the Counter Mode to be used. -* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. -* - TIM_CounterMode: specifies the Counter Mode to be used -* This parameter can be one of the following values: -* - TIM_CounterMode_Up: TIM Up Counting Mode -* - TIM_CounterMode_Down: TIM Down Counting Mode -* - TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 -* - TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 -* - TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 -* Output : None -* Return : None -*******************************************************************************/ -void TIM_CounterModeConfig(TIM_TypeDef* TIMx, u16 TIM_CounterMode) -{ - /* Counter mode configuration */ - TIMx->CR &= TIM_CounterMode_Mask; - TIMx->CR |= TIM_CounterMode; -} - -/******************************************************************************* -* Function Name : TIM_ForcedOCConfig -* Description : Forces the TIM output waveform to active or inactive level. -* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. -* - TIM_Channel: specifies the TIM channel to be used. -* This parameter can be one of the following values: -* - TIM_Channel_1: Timer Channel 1 is used -* - TIM_Channel_2: Timer Channel 2 is used -* - TIM_Channel_ALL: Timer Channel 1 and 2 are used -* - TIM_ForcedAction: specifies the forced Action to be set to -* the output waveform. -* This parameter can be one of the following values: -* - TIM_ForcedAction_Active: Force active level on OCxREF -* - TIM_ForcedAction_InActive: Force inactive level on -* OCxREF. -* Output : None -* Return : None -*******************************************************************************/ -void TIM_ForcedOCConfig(TIM_TypeDef* TIMx, u16 TIM_Channel,u16 TIM_ForcedAction) -{ - /* Channel 1 Forced Output Compare mode configuration */ - if(TIM_Channel == TIM_Channel_1) - { - TIMx->OMR1 &= TIM_OC1C_Mask; - TIMx->OMR1 |= TIM_ForcedAction; - } - /* Channel 2 Forced Output Compare mode configuration */ - else - { - if(TIM_Channel == TIM_Channel_2) - { - TIMx->OMR1 &= TIM_OC2C_Mask; - TIMx->OMR1 |= (TIM_ForcedAction<<8); - } - /* Channel 1 and Channel 2 Forced Output Compare mode configuration */ - else - { - TIMx->OMR1 &= TIM_OC1C_Mask & TIM_OC2C_Mask; - TIMx->OMR1 |= TIM_ForcedAction |(TIM_ForcedAction<<8); - } - } -} - -/******************************************************************************* -* Function Name : TIM_ResetCounter -* Description : Re-intializes the TIM counter and generates an update of the -* registers. -* Input : TIMx: where x can be 0, 1 or 2 to select the TIM peripheral -* Output : None -* Return : None -*******************************************************************************/ -void TIM_ResetCounter(TIM_TypeDef* TIMx) -{ - /* Re-intialize the TIM counter */ - TIMx->CR |= TIM_COUNTER_Reset; -} - -/******************************************************************************* -* Function Name : TIM_SynchroConfig -* Description : Synchronizes two Timers in a specified mode. -* Input : - Master: specifies the peripheral master. -* This parameter can be one of the following values: -* PWM_Master, TIM0_Master, TIM1_Master or TIM2_Master. -* - Slave: specifies the peripheral slave. -* This parameter can be one of the following values: -* PWM_Slave, TIM0_Slave, TIM1_Slave or TIM2_Slave. -* - TIM_SynchroAction: specifies the synchronization Action to -* be used. -* This parameter can be one of the following values: -* - TIM_SynchroAction_Enable: The CNT_EN bit is used as TRGO -* - TIM_SynchroAction_Update: The Update event is used as TRGO -* - TIM_SynchroAction_Reset: The CNT_RST bit is used as TRGO -* - TIM_SynchroAction_OC: The OC1 signal is used as TRGO -* - TIM_SynchroMode: specifies the synchronization Mode to be used. -* This parameter can be one of the following values: -* - TIM_SynchroMode_Gated: Both start and stop of the -* counter is controlled. -* - TIM_SynchroMode_Trigger: Only the start of the -* counter is controlled. -* - TIM_SynchroMode_External: The rising edge of selected trigger -* clocks the counter. -* - TIM_SynchroMode_Reset: The rising edge of the selected trigger -* signal resets the counter and generates an update of the registers. -* Output : None -* Return : None -*******************************************************************************/ -void TIM_SynchroConfig(Master_TypeDef Master, Slave_TypeDef Slave, - u16 TIM_SynchroAction, u16 TIM_SynchroMode) -{ - switch (Slave) - { - case PWM_Slave: - { - PWM->SCR &= TIM_SME_Reset & TIM_TriggerSelection_Mask & TIM_SlaveModeSelection_Mask & - TIM_InternalTriggerSelection_Mask; - PWM->SCR |= TIM_SynchroMode | TIM_SME_Set; - - if(Master == TIM1_Master) - { - /* Set the internal trigger */ - PWM->SCR |= TIM_ITS_TIM1; - - /* Set the synchronization action */ - TIM1->CR &= TIM_MasterModeSelection_Mask; - TIM1->CR |= TIM_SynchroAction; - } - - else if(Master == TIM0_Master) - { - /* Set the internal trigger */ - PWM->SCR |= TIM_ITS_TIM0; - - /* Set the synchronization action */ - TIM0->CR &= TIM_MasterModeSelection_Mask; - TIM0->CR |= TIM_SynchroAction; - } - - else if(Master == TIM2_Master) - { - /* Set the internal trigger */ - PWM->SCR |= TIM_ITS_TIM2; - - /* Set the synchronization action */ - TIM2->CR &= TIM_MasterModeSelection_Mask; - TIM2->CR |= TIM_SynchroAction; - } - } - break; - - case TIM0_Slave: - { - TIM0->SCR &= TIM_SME_Reset & TIM_TriggerSelection_Mask & TIM_SlaveModeSelection_Mask & - TIM_InternalTriggerSelection_Mask; - TIM0->SCR |= TIM_SynchroMode | TIM_SME_Set; - - if(Master == PWM_Master) - { - /* Set the internal trigger */ - TIM0->SCR |= TIM_ITS_PWM; - - /* Set the synchronization action */ - PWM->CR &= TIM_MasterModeSelection_Mask; - PWM->CR |= TIM_SynchroAction; - } - - else if(Master == TIM1_Master) - { - /* Set the internal trigger */ - TIM0->SCR |= TIM_ITS_TIM1; - - /* Set the synchronization action */ - TIM1->CR &= TIM_MasterModeSelection_Mask; - TIM1->CR |= TIM_SynchroAction; - } - - else if(Master == TIM2_Master) - { - /* Set the internal trigger */ - TIM0->SCR |= TIM_ITS_TIM2; - - /* Set the synchronization action */ - TIM2->CR &= TIM_MasterModeSelection_Mask; - TIM2->CR |= TIM_SynchroAction; - } - } - break; - - case TIM1_Slave: - { - - TIM1->SCR &= TIM_SME_Reset & TIM_TriggerSelection_Mask & TIM_SlaveModeSelection_Mask & - TIM_InternalTriggerSelection_Mask; - TIM1->SCR |= TIM_SynchroMode | TIM_SME_Set; - - if(Master == PWM_Master) - { - /* Set the internal trigger */ - TIM1->SCR |= TIM_ITS_PWM; - - /* Set the synchronization action */ - PWM->CR &= TIM_MasterModeSelection_Mask; - PWM->CR |= TIM_SynchroAction; - } - else if(Master == TIM0_Master) - { - /* Set the internal trigger */ - TIM1->SCR |= TIM_ITS_TIM0; - - /* Set the synchronization action */ - TIM0->CR &= TIM_MasterModeSelection_Mask; - TIM0->CR |= TIM_SynchroAction; - } - - else if(Master == TIM2_Master) - { - /* Set the internal trigger */ - TIM1->SCR |= TIM_ITS_TIM2; - - /* Set the synchronization action */ - TIM2->CR &= TIM_MasterModeSelection_Mask; - TIM2->CR |= TIM_SynchroAction; - } - } - break; - - case TIM2_Slave: - { - - TIM2->SCR &= TIM_SME_Reset & TIM_TriggerSelection_Mask & TIM_SlaveModeSelection_Mask & - TIM_InternalTriggerSelection_Mask; - TIM2->SCR |= TIM_SynchroMode | TIM_SME_Set; - - if(Master == PWM_Master) - { - /* Internal trigger selection */ - TIM2->SCR |= TIM_ITS_PWM; - - /* Set the synchronization action */ - PWM->CR &= TIM_MasterModeSelection_Mask; - PWM->CR |= TIM_SynchroAction; - } - - else if(Master == TIM1_Master) - { - /* Internal trigger selection */ - TIM2->SCR |= TIM_ITS_TIM1; - - /* Set the synchronization action */ - TIM1->CR &= TIM_MasterModeSelection_Mask; - TIM1->CR |= TIM_SynchroAction; - } - - else if(Master == TIM0_Master) - { - /* Internal trigger selection */ - TIM2->SCR |= TIM_ITS_TIM0; - - /* Set the synchronization action */ - TIM0->CR &= TIM_MasterModeSelection_Mask; - TIM0->CR |= TIM_SynchroAction; - } - } - break; - - default: - break; - } -} - -/******************************************************************************* -* Function Name : TIM_GetFlagStatus -* Description : Checks whether the specified TIM flag is set or not. -* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. -* - TIM_FLAG: specifies the flag to check. -* This parameter can be one of the following values: -* - TIM_FLAG_IC1: Input Capture 1 Flag -* - TIM_FLAG_OC1: Output Compare 1 Flag -* - TIM_FLAG_Update: Timer update Flag -* - TIM_FLAG_IC2: Input Capture 2 Flag -* - TIM_FLAG_OC2: Output Compare 2 Flag -* Output : None -* Return : The new state of TIM_FLAG (SET or RESET). -*******************************************************************************/ -FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, u16 TIM_FLAG) -{ - if((TIMx->ISR & TIM_FLAG) != RESET ) - { - return SET; - } - else - { - return RESET; - } -} - -/******************************************************************************* -* Function Name : TIM_ClearFlag -* Description : Clears the TIMx's pending flags. -* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. -* - TIM_FLAG: specifies the flag bit to clear. -* This parameter can be any combination of the following values: -* - TIM_FLAG_IC1: Timer Input Capture 1 flag -* - TIM_FLAG_OC1: Timer Output Compare 1 flag -* - TIM_FLAG_Update: Timer update flag -* - TIM_FLAG_IC2: Timer Input Capture 2 flag -* - TIM_FLAG_OC2: Timer Output Compare 2 flag -* Output : None -* Return : None -*******************************************************************************/ -void TIM_ClearFlag(TIM_TypeDef* TIMx, u16 TIM_FLAG) -{ - /* Clear the flags */ - TIMx->ISR &= ~TIM_FLAG; -} - -/******************************************************************************* -* Function Name : TIM_GetITStatus -* Description : Checks whether the specified TIM interrupt has occurred or not. -* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. -* - TIM_IT: specifies the TIM interrupt source to check. -* This parameter can be one of the following values: -* - TIM_IT_IC1: Input Capture 1 interrupt -* - TIM_IT_OC1: Output Compare 1 interrupt -* - TIM_IT_Update: Timer update interrupt -* - TIM_IT_GlobalUpdate: Timer global update interrupt -* - TIM_IT_IC2: Input Capture 2 interrupt -* - TIM_IT_OC2: Output Compare 2 interrupt -* Output : None -* Return : The new state of TIM_IT(SET or RESET). -*******************************************************************************/ -ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, u16 TIM_IT) -{ - u16 TIM_IT_Check = 0; - - /* Calculates the pending bits to be checked */ - TIM_IT_Check = TIM_IT & TIM_IT_Clear_Mask; - - if((TIMx->ISR & TIM_IT_Check) != RESET ) - { - return SET; - } - else - { - return RESET; - } -} - -/******************************************************************************* -* Function Name : TIM_ClearITPendingBit -* Description : Clears the TIM's interrupt pending bits. -* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. -* - TIM_IT: specifies the interrupt pending bit to clear. -* This parameter can be one of the following values: -* - TIM_IT_IC1: Input Capture 1 Interrupt -* - TIM_IT_OC1: Output Compare 1 Interrupt -* - TIM_IT_Update: Timer update Interrupt -* - TIM_IT_GlobalUpdate: Timer global update Interrupt -* - TIM_IT_IC2: Input Capture 2 Interrupt -* - TIM_IT_OC2: Output Compare 2 Interrupt -* Output : None -* Return : None -*******************************************************************************/ -void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, u16 TIM_IT) -{ - u16 TIM_IT_Clear = 0; - - /* Calculate the pending bits to be cleared */ - TIM_IT_Clear = TIM_IT & TIM_IT_Clear_Mask; - - /* Clear the pending bits */ - TIMx->ISR &= ~TIM_IT_Clear; -} - -/******************************************************************************* -* Function Name : OCM_ModuleConfig -* Description : Output Compare Module configuration -* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral -* - TIM_InitStruct: pointer to a TIM_InitTypeDef structure that -* contains the configuration information for the specified TIM -* peripheral. -* Output : None -* Return : None -*******************************************************************************/ -static void OCM_ModuleConfig(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct) -{ - u16 TIM_OCControl = 0x0000; - - if(TIM_InitStruct->TIM_Mode == TIM_Mode_OCTiming) - { - TIM_OCControl = TIM_OCControl_OCTiming; - } - else - { - if((TIM_InitStruct->TIM_Mode == TIM_Mode_OCActive) || - (TIM_InitStruct->TIM_Mode == TIM_Mode_OPM_Active)) - { - TIM_OCControl = TIM_OCControl_OCActive; - } - else - { - if(TIM_InitStruct->TIM_Mode == TIM_Mode_OCInactive) - { - TIM_OCControl = TIM_OCControl_OCInactive; - } - else - { - if((TIM_InitStruct->TIM_Mode == TIM_Mode_OCToggle) || - (TIM_InitStruct->TIM_Mode == TIM_Mode_OPM_Toggle)) - { - TIM_OCControl = TIM_OCControl_OCToggle; - } - else - { - TIM_OCControl = TIM_OCControl_PWM; - - } - } - } - } - - if(TIM_InitStruct->TIM_Channel == TIM_Channel_1) - { - /* Configure Channel 1 on Output Compare mode */ - TIMx->OMR1 &= TIM_OC1C_Mask; - TIMx->OMR1 |= TIM_OCControl|TIM_OC1_Enable; - TIMx->OMR1 |= TIM_PLD1_Set; - TIMx->OCR1 = TIM_InitStruct->TIM_Pulse1; - - /* Set the OC1 wave polarity */ - if(TIM_InitStruct->TIM_Polarity1 == TIM_Polarity1_Low) - { - TIMx->OMR1 |= TIM_OC1P_Set; - } - else - { - TIMx->OMR1 &= TIM_OC1P_Reset; - } - } - else - { - if(TIM_InitStruct->TIM_Channel == TIM_Channel_2) - { - /* Configure Channel 2 on Output Compare mode */ - TIMx->OMR1 &= TIM_OC2C_Mask; - TIMx->OMR1 |= TIM_OCControl<<8|TIM_OC2_Enable; - TIMx->OMR1 |= TIM_PLD2_Set; - TIMx->OCR2 = TIM_InitStruct->TIM_Pulse2; - - /* Set the OCB wave polarity */ - if(TIM_InitStruct->TIM_Polarity2 == TIM_Polarity2_Low) - { - TIMx->OMR1 |= TIM_OC2P_Set; - } - else - { - TIMx->OMR1 &= TIM_OC2P_Reset; - } - } - /* Configure Channel 1 and Channel 2 on Output Compare mode */ - else - { - TIMx->OMR1 &= TIM_OC1C_Mask & TIM_OC2C_Mask; - TIMx->OMR1 |= TIM_OCControl|(TIM_OCControl<<8)|TIM_OC1_Enable|TIM_OC2_Enable| - TIM_PLD1_Set|TIM_PLD2_Set; - - TIMx->OCR1 = TIM_InitStruct->TIM_Pulse1; - TIMx->OCR2 = TIM_InitStruct->TIM_Pulse2; - - /* Set the OC1 wave polarity */ - if(TIM_InitStruct->TIM_Polarity1 == TIM_Polarity1_Low) - { - TIMx->OMR1 |= TIM_OC1P_Set; - } - else - { - TIMx->OMR1 &= TIM_OC1P_Reset; - } - - /* Set the OC2 wave polarity */ - if(TIM_InitStruct->TIM_Polarity2 == TIM_Polarity2_Low) - { - TIMx->OMR1 |= TIM_OC2P_Set; - } - else - { - TIMx->OMR1 &= TIM_OC2P_Reset; - } - } - } -} - -/******************************************************************************* -* Function Name : ICAP_ModuleConfig -* Description : Input Capture Module configuration -* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral -* - TIM_InitStruct: pointer to a TIM_InitTypeDef structure that -* contains the configuration information for the specified TIM -* peripheral. -* Output : None -* Return : None -*******************************************************************************/ -static void ICAP_ModuleConfig(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct) -{ - if(TIM_InitStruct->TIM_Mode == TIM_Mode_PWMI) - { /* PWM input mode configuration */ - TIMx->SCR |= TIM_TS_IC1_Set|TIM_SMS_RESETCLK_Set|TIM_SME_Set; - - /* Channel 1 and channel 2 input selection */ - if(TIM_InitStruct->TIM_PWMI_ICSelection == TIM_PWMI_ICSelection_TI1) - { - TIMx->IMCR &= TIM_IC1S_Reset; - TIMx->IMCR |= TIM_IC2S_Set; - } - else - { - TIMx->IMCR |= TIM_IC1S_Set; - TIMx->IMCR &= TIM_IC2S_Reset; - } - - /* Channel polarity */ - if(TIM_InitStruct->TIM_PWMI_ICPolarity == TIM_PWMI_ICPolarity_Rising) - { - TIMx->IMCR &= TIM_IC1P_Reset; - TIMx->IMCR |= TIM_IC2P_Set; - } - else - { - TIMx->IMCR |= TIM_IC1P_Set; - TIMx->IMCR &= TIM_IC2P_Reset; - } - - /* Input capture Enable */ - TIMx->IMCR |= TIM_IC1_Enable |TIM_IC2_Enable; - } - else - { - if(TIM_InitStruct->TIM_Channel == TIM_Channel_1) - { - /* Input Capture 1 mode configuration */ - TIMx->SCR &= TIM_TriggerSelection_Mask & TIM_SlaveModeSelection_Mask; - TIMx->SCR |= TIM_TS_IC1_Set|TIM_SMS_RESETCLK_Set|TIM_SME_Set; - - /* Channel 1 input selection */ - if(TIM_InitStruct->TIM_IC1Selection == TIM_IC1Selection_TI1) - { - TIMx->IMCR &= TIM_IC1S_Reset; - } - else - { - TIMx->IMCR |= TIM_IC1S_Set; - } - /* Channel 1 polarity */ - if(TIM_InitStruct->TIM_IC1Polarity == TIM_IC1Polarity_Rising) - { - TIMx->IMCR &= TIM_IC1P_Reset; - } - else - { - TIMx->IMCR |= TIM_IC1P_Set; - } - - /* Input capture Enable */ - TIMx->IMCR |= TIM_IC1_Enable; - } - else - { - /* Input Capture 2 mode configuration */ - TIMx->SCR &= (TIM_TriggerSelection_Mask & TIM_SlaveModeSelection_Mask); - TIMx->SCR |= TIM_TS_IC2_Set|TIM_SMS_RESETCLK_Set|TIM_SME_Set; - - /* Channel 2 input selection */ - if(TIM_InitStruct->TIM_IC2Selection == TIM_IC2Selection_TI2) - { - TIMx->IMCR &= TIM_IC2S_Reset; - } - else - { - TIMx->IMCR |= TIM_IC2S_Set; - } - - /* Channel 2 polarity */ - if(TIM_InitStruct->TIM_IC2Polarity == TIM_IC2Polarity_Rising) - { - TIMx->IMCR &= TIM_IC2P_Reset; - } - else - { - TIMx->IMCR |= TIM_IC2P_Set; - } - - /* Input capture Enable */ - TIMx->IMCR |= TIM_IC2_Enable; - } - } -} - -/******************************************************************************* -* Function Name : Encoder_ModeConfig -* Description : Encoder Mode configuration -* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral -* - TIM_InitStruct: pointer to a TIM_InitTypeDef structure that -* contains the configuration information for the specified TIM -* peripheral. -* Output : None -* Return : None -*******************************************************************************/ -static void Encoder_ModeConfig(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct) -{ - /* Set Encoder mode */ - TIMx->SCR &= TIM_Encoder_Mask; - - if(TIM_InitStruct->TIM_Mode == TIM_Mode_Encoder1) - { - TIMx->SCR |= TIM_Encoder1_Set; - } - else if (TIM_InitStruct->TIM_Mode == TIM_Mode_Encoder2) - { - TIMx->SCR |= TIM_Encoder2_Set; - } - else - { - TIMx->SCR |= TIM_Encoder3_Set; - } - - /* Channel 1 input selection */ - if(TIM_InitStruct->TIM_IC1Selection == TIM_IC1Selection_TI2) - { - TIMx->IMCR |= TIM_IC1S_Set; - } - else - { - TIMx->IMCR &= TIM_IC1S_Reset; - } - - /* Channel 2 input selection */ - if(TIM_InitStruct->TIM_IC2Selection == TIM_IC2Selection_TI1) - { - TIMx->IMCR |= TIM_IC2S_Set; - } - else - { - TIMx->IMCR &= TIM_IC2S_Reset; - } - - /* Channel 1 polarity */ - if(TIM_InitStruct->TIM_IC1Polarity == TIM_IC1Polarity_Falling) - { - TIMx->IMCR |= TIM_IC1P_Set; - } - else - { - TIMx->IMCR &= TIM_IC1P_Reset; - } - - /* Channel 2 polarity */ - if(TIM_InitStruct->TIM_IC2Polarity == TIM_IC2Polarity_Falling) - { - TIMx->IMCR |= TIM_IC2P_Set; - } - else - { - TIMx->IMCR &= TIM_IC2P_Reset; - } -} -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_uart.c b/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_uart.c deleted file mode 100644 index 5494ff335..000000000 --- a/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_uart.c +++ /dev/null @@ -1,599 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_uart.c -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file provides all the UART software functions. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -#include "75x_uart.h" -#include "75x_mrcc.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* UART LIN Mask */ -#define UART_LIN_Disable_Mask 0xFEFF /* LIN Disable Mask */ -#define UART_LIN_Enable_Mask 0x0100 /* LIN Enable Mask */ - -/* UART Mask */ -#define UART_Enable_Mask 0x0001 /* UART Enable Mask */ -#define UART_Disable_Mask 0xFFFE /* UART Disable Mask */ - -/* UART LoopBack */ -#define UART_LoopBack_Disable_Mask 0xFF7F/* LoopBack Disable Mask */ -#define UART_LoopBack_Enable_Mask 0x0080/* LoopBack Enable Mask */ - -#define UART_WordLength_Mask 0xFF9F /* UART Word Length Mask */ -#define UART_Parity_Mask 0xFF79 /* UART Parity Mask */ -#define UART_HardwareFlowControl_Mask 0x3FFF /* UART Hardware Flow Control Mask */ -#define UART_TxRxFIFOLevel_Mask 0xFFC0 /* UART Tx Rx FIFO Level Mask */ -#define UART_LINBreakLength_Mask 0xE1FF /* UART LIN Break Length Mask */ -#define UART_BreakChar_Mask 0x0001 /* UART Break Character send Mask */ -#define UART_FLAG_Mask 0x1F /* UART Flag Mask */ -#define UART_Mode_Mask 0xFCFF /* UART Mode Mask */ -#define UART_RTSSET_Mask 0xF7FF /* RTS signal is high */ -#define UART_RTSRESET_Mask 0x0800 /* RTS signal is low */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/******************************************************************************* -* Function Name : UART_DeInit -* Description : Deinitializes the UARTx peripheral registers to their default -* reset values. -* Input : UARTx: where x can be 0,1 or 2 to select the UART peripheral. -* Output : None -* Return : None -*******************************************************************************/ -void UART_DeInit(UART_TypeDef* UARTx) -{ - /* Reset the UARTx registers values */ - if(UARTx == UART0) - { - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_UART0,ENABLE); - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_UART0,DISABLE); - } - else if(UARTx == UART1) - { - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_UART1,ENABLE); - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_UART1,DISABLE); - } - else if(UARTx == UART2) - { - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_UART2,ENABLE); - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_UART2,DISABLE); - } -} - -/******************************************************************************* -* Function Name : UART_Init -* Description : Initializes the UARTx peripheral according to the specified -* parameters in the UART_InitStruct . -* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral. -* - UART_InitStruct: pointer to a UART_InitTypeDef structure -* that contains the configuration information for the -* specified UART peripheral. -* Output : None -* Return : None -*******************************************************************************/ -void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct) -{ - - u32 APBClock = 0; - u32 IntegerDivider = 0; - u32 FractionalDivider = 0; - MRCC_ClocksTypeDef MRCC_ClocksStatus; - - /* Clear the WLEN bits */ - UARTx->LCR &= UART_WordLength_Mask; - /* Set the WLEN bits according to UART_WordLength value */ - UARTx->LCR |= UART_InitStruct->UART_WordLength; - - /* Choose Stop Bits */ - if(UART_InitStruct->UART_StopBits == UART_StopBits_1) - { - /* One Stop Bit */ - UARTx->LCR &= UART_StopBits_1; - } - else - { - /* Two Stop Bits */ - UARTx->LCR |= UART_StopBits_2; - } - - /* Clear SPS, EPS and PEN bits */ - UARTx->LCR &= UART_Parity_Mask; - /* Set PS, EPS and PEN bits according to UART_Parity value */ - UARTx->LCR |= UART_InitStruct->UART_Parity; - - /* Configure the BaudRate --------------------------------------------------*/ - /* Get the APB frequency */ - MRCC_GetClocksStatus(&MRCC_ClocksStatus); - APBClock = MRCC_ClocksStatus.PCLK_Frequency; - - /* Determine the integer part */ - IntegerDivider = ((100) * (APBClock) / (16 * (UART_InitStruct->UART_BaudRate))); - UARTx->IBRD = IntegerDivider / 100; - - /* Determine the fractional part */ - FractionalDivider = IntegerDivider - (100 * (UARTx->IBRD)); - UARTx->FBRD = ((((FractionalDivider * 64) + 50) / 100)); - - /* Choose the Hardware Flow Control */ - /* Clear RTSEn and CTSEn bits */ - UARTx->CR &= UART_HardwareFlowControl_Mask; - /* Set RTSEn and CTSEn bits according to UART_HardwareFlowControl value */ - UARTx->CR |= UART_InitStruct->UART_HardwareFlowControl; - - /* Configure the UART mode */ - /* Clear TXE and RXE bits */ - UARTx->CR &= UART_Mode_Mask; - /* Set TXE and RXE bits according to UART_Mode value */ - UARTx->CR |= UART_InitStruct->UART_Mode; - - /* Enable or disable the FIFOs */ - /* Set the FIFOs Levels */ - if(UART_InitStruct->UART_FIFO == UART_FIFO_Enable) - { - /* Enable the FIFOs */ - UARTx->LCR |= UART_FIFO_Enable; - - /* Clear TXIFLSEL and RXIFLSEL bits */ - UARTx->IFLS &= UART_TxRxFIFOLevel_Mask; - - /* Set RXIFLSEL bits according to UART_RxFIFOLevel value */ - UARTx->IFLS |= (UART_InitStruct->UART_RxFIFOLevel << 3); - - /* Set TXIFLSEL bits according to UART_TxFIFOLevel value */ - UARTx->IFLS |= UART_InitStruct->UART_TxFIFOLevel; - } - else - { - /* Disable the FIFOs */ - UARTx->LCR &= UART_FIFO_Disable; - } -} - -/******************************************************************************* -* Function Name : UART_StructInit -* Description : Fills each UART_InitStruct member with its default value. -* Input : UART_InitStruct: pointer to a UART_InitTypeDef structure which -* will be initialized. -* Output : None -* Return : None -*******************************************************************************/ -void UART_StructInit(UART_InitTypeDef* UART_InitStruct) -{ - /* UART_InitStruct members default value */ - UART_InitStruct->UART_WordLength = UART_WordLength_8D; - UART_InitStruct->UART_StopBits = UART_StopBits_1; - UART_InitStruct->UART_Parity = UART_Parity_Odd ; - UART_InitStruct->UART_BaudRate = 9600; - UART_InitStruct->UART_HardwareFlowControl = UART_HardwareFlowControl_None; - UART_InitStruct->UART_Mode = UART_Mode_Tx_Rx; - UART_InitStruct->UART_FIFO = UART_FIFO_Enable; - UART_InitStruct->UART_TxFIFOLevel = UART_FIFOLevel_1_2; - UART_InitStruct->UART_RxFIFOLevel = UART_FIFOLevel_1_2; -} - -/******************************************************************************* -* Function Name : UART_Cmd -* Description : Enables or disables the specified UART peripheral. -* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral -* - NewState: new state of the UARTx peripheral. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void UART_Cmd(UART_TypeDef* UARTx, FunctionalState NewState) -{ - if (NewState == ENABLE) - { - /* Enable the selected UART by setting the UARTEN bit in the CR register */ - UARTx->CR |= UART_Enable_Mask; - } - else - { - /* Disable the selected UART by clearing the UARTEN bit in the CR register */ - UARTx->CR &= UART_Disable_Mask; - } -} - -/******************************************************************************* -* Function Name : UART_ITConfig -* Description : Enables or disables the specified UART interrupts. -* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral -* - UART_IT: specifies the UART interrupts sources to be -* enabled or disabled. This parameter can be any combination -* of the following values: -* - UART_IT_OverrunError: Overrun Error interrupt -* - UART_IT_BreakError: Break Error interrupt -* - UART_IT_ParityError: Parity Error interrupt -* - UART_IT_FrameError: Frame Error interrupt -* - UART_IT_ReceiveTimeOut: Receive Time Out interrupt -* - UART_IT_Transmit: Transmit interrupt -* - UART_IT_Receive: Receive interrupt -* - UART_IT_CTS: CTS interrupt -* - NewState: new state of the UARTx peripheral. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void UART_ITConfig(UART_TypeDef* UARTx, u16 UART_IT, FunctionalState NewState) -{ - if(NewState == ENABLE) - { - /* Enables the selected interrupts */ - UARTx->IMSC |= UART_IT; - } - else - { - /* Disables the selected interrupts */ - UARTx->IMSC &= ~UART_IT; - } -} - -/******************************************************************************* -* Function Name : UART_DMAConfig -* Description : Configures the UART0 DMA interface. -* Input : - UART0_DMAtransfer : specifies the configuration of DMA request. -* This parameter can be: -* - UART0_DMATransfer_Single: Single DMA transfer -* - UART0_DMATransfer_Burst: Burst DMA transfer -* - UART0_DMAOnError: specifies the DMA on error request. -* This parameter can be: -* - UART0_DMAOnError_Enable: DMA receive request enabled -* when the UART error interrupt is asserted. -* - UART0_DMAOnError_Disable: DMA receive request disabled -* when the UART error interrupt is asserted. -* Output : None -* Return : None -*******************************************************************************/ -void UART_DMAConfig(u16 UART0_DMATransfer, u16 UART0_DMAOnError) -{ - if(UART0_DMATransfer == UART0_DMATransfer_Single) - { - /* Configure the DMA request from the UART0 as single transfer */ - UART0->DMACR &= UART0_DMATransfer_Single; - } - else - { - UART0->DMACR |= UART0_DMATransfer_Burst; - } - - if(UART0_DMAOnError == UART0_DMAOnError_Enable) - { - UART0->DMACR &= UART0_DMAOnError_Enable; - } - else - { - UART0->DMACR |= UART0_DMAOnError_Disable; - } -} - -/******************************************************************************* -* Function Name : UART_DMACmd -* Description : Enables or disables the UART0’s DMA interface. -* Input : - UART0_DMAReq: specifies the DMA request. -* This parameter can be: -* - UART0_DMAReq_Tx: Transmit DMA request -* - UART0_DMAReq_Rx: Receive DMA request -* - NewState: new state of the UART0’s DMA request. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void UART_DMACmd(u16 UART0_DMAReq, FunctionalState NewState) -{ - if(UART0_DMAReq == UART0_DMAReq_Tx) - { - if(NewState == ENABLE) - { - UART0->DMACR |= UART0_DMAReq_Tx; - } - else - { - UART0->DMACR &= ~UART0_DMAReq_Tx; - } - } - else - { - if(NewState == ENABLE) - { - UART0->DMACR |= UART0_DMAReq_Rx; - } - else - { - UART0->DMACR &= ~UART0_DMAReq_Rx; - } - } -} - -/******************************************************************************* -* Function Name : UART_LoopBackConfig -* Description : Enables or disables LoopBack mode in UARTx. -* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral -* - NewState: new state of the UARTx’s LoopBack mode. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void UART_LoopBackConfig(UART_TypeDef* UARTx, FunctionalState NewState) -{ - if (NewState == ENABLE) - { - /* Enable the LoopBack mode of the specified UART */ - UARTx->CR |= UART_LoopBack_Enable_Mask; - } - else - { - /* Disable the LoopBack mode of the specified UART */ - UARTx->CR &= UART_LoopBack_Disable_Mask; - } -} - -/******************************************************************************* -* Function Name : UART_LINConfig -* Description : Sets the LIN break length. -* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral. -* - UART_LINBreakLength: Break length value. -* This parameter can be: -* - UART_LINBreakLength_10: 10 low bits -* - UART_LINBreakLength_11: 11 low bits -* - UART_LINBreakLength_12: 12 low bits -* - UART_LINBreakLength_13: 13 low bits -* - UART_LINBreakLength_14: 14 low bits -* - UART_LINBreakLength_15: 15 low bits -* - UART_LINBreakLength_16: 16 low bits -* - UART_LINBreakLength_17: 17 low bits -* - UART_LINBreakLength_18: 18 low bits -* - UART_LINBreakLength_19: 19 low bits -* - UART_LINBreakLength_20: 20 low bits -* Output : None -* Return : None -*******************************************************************************/ -void UART_LINConfig(UART_TypeDef* UARTx, u16 UART_LINBreakLength) -{ - /* Clear LBKLEN bits */ - UARTx->LCR &= UART_LINBreakLength_Mask; - - /* Set LBKLEN bits according to UART_LINBreakLength value */ - UARTx->LCR |= UART_LINBreakLength; -} - -/******************************************************************************* -* Function Name : UART_LINCmd -* Description : Enables or disables LIN master mode in UARTx. -* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral -* - NewState: new state of the UARTx’s LIN interface. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void UART_LINCmd(UART_TypeDef* UARTx, FunctionalState NewState) -{ - if(NewState == ENABLE) - { - /* Enable the LIN mode of the specified UART */ - UARTx->LCR |= UART_LIN_Enable_Mask; - } - else - { - /* Disable the LIN mode of the specified UART */ - UARTx->LCR &= UART_LIN_Disable_Mask; - } -} - -/******************************************************************************* -* Function Name : UART_SendData -* Description : Transmits a signle Byte of data through the UARTx peripheral. -* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral. -* - Data: the byte to transmit -* Output : None -* Return : None -*******************************************************************************/ -void UART_SendData(UART_TypeDef* UARTx, u8 Data) -{ - /* Transmit one byte */ - UARTx->DR = Data; -} - -/******************************************************************************* -* Function Name : UART_ReceiveData -* Description : Returns the most recent received Byte by the UARTx peripheral. -* Input : UARTx: where x can be 0,1 or 2 to select the UART peripheral. -* Output : None -* Return : The received data -*******************************************************************************/ -u8 UART_ReceiveData(UART_TypeDef* UARTx) -{ - /* Receive one byte */ - return ((u8)UARTx->DR); -} - -/******************************************************************************* -* Function Name : UART_SendBreak -* Description : Transmits break characters. -* Input : UARTx: where x can be 0,1 or 2 to select the UART peripheral. -* Output : None -* Return : None -*******************************************************************************/ -void UART_SendBreak(UART_TypeDef* UARTx) -{ - /* Send break characters */ - UARTx->BKR |= UART_BreakChar_Mask; -} - -/******************************************************************************* -* Function Name : UART_RTSConfig -* Description : Sets or Resets the RTS signal -* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral. -* - RTSState: new state of the RTS signal. -* This parameter can be: RTSSET or RTSRESET -* Output : None -* Return : None -*******************************************************************************/ -void UART_RTSConfig(UART_TypeDef* UARTx, UART_RTSTypeDef RTSState) -{ - if(RTSState == RTSRESET) - { - UARTx->CR |= UART_RTSRESET_Mask; - } - else if(RTSState == RTSSET) - { - UARTx->CR &= UART_RTSSET_Mask; - } -} - -/******************************************************************************* -* Function Name : UART_GetFlagStatus -* Description : Checks whether the specified UART flag is set or not. -* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral -* - UART_FLAG: specifies the flag to check. -* This parameter can be one of the following values: -* - UART_FLAG_OverrunError: Overrun error flag -* - UART_FLAG_Break: break error flag -* - UART_FLAG_ParityError: parity error flag -* - UART_FLAG_FrameError: frame error flag -* - UART_FLAG_TxFIFOEmpty: Transmit FIFO Empty flag -* - UART_FLAG_RxFIFOFull: Receive FIFO Full flag -* - UART_FLAG_TxFIFOFull: Transmit FIFO Full flag -* - UART_FLAG_RxFIFOEmpty: Receive FIFO Empty flag -* - UART_FLAG_Busy: Busy flag -* - UART_FLAG_CTS: CTS flag -* - UART_RawIT_OverrunError: Overrun Error interrupt flag -* - UART_RawIT_BreakError: Break Error interrupt flag -* - UART_RawIT_ParityError: Parity Error interrupt flag -* - UART_RawIT_FrameError: Frame Error interrupt flag -* - UART_RawIT_ReceiveTimeOut: ReceiveTimeOut interrupt flag -* - UART_RawIT_Transmit: Transmit interrupt flag -* - UART_RawIT_Receive: Receive interrupt flag -* - UART_RawIT_CTS: CTS interrupt flag -* Output : None -* Return : The new state of UART_FLAG (SET or RESET). -*******************************************************************************/ -FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, u16 UART_FLAG) -{ - u32 UARTReg = 0, FlagPos = 0; - u32 StatusReg = 0; - - /* Get the UART register index */ - UARTReg = UART_FLAG >> 5; - - /* Get the flag position */ - FlagPos = UART_FLAG & UART_FLAG_Mask; - - if(UARTReg == 1) /* The flag to check is in RSR register */ - { - StatusReg = UARTx->RSR; - } - else if (UARTReg == 2) /* The flag to check is in FR register */ - { - StatusReg = UARTx->FR; - } - else if(UARTReg == 3) /* The flag to check is in RIS register */ - { - StatusReg = UARTx->RIS; - } - - if((StatusReg & (1 << FlagPos))!= RESET) - { - return SET; - } - else - { - return RESET; - } -} - -/******************************************************************************* -* Function Name : UART_ClearFlag -* Description : Clears the UARTx’s pending flags. -* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral. -* - UART_FLAG: specifies the flag to clear. -* This parameter can be one of the following values: -* - UART_FLAG_OverrunError: Overrun error flag -* - UART_FLAG_Break: break error flag -* - UART_FLAG_ParityError: parity error flag -* - UART_FLAG_FrameError: frame error flag -* Output : None -* Return : None -*******************************************************************************/ -void UART_ClearFlag(UART_TypeDef* UARTx, u16 UART_FLAG) -{ - u8 FlagPos = 0; - - /* Get the flag position */ - FlagPos = UART_FLAG & UART_FLAG_Mask; - - /* Clear the sepecified flag */ - UARTx->RSR &= ~(1 << FlagPos); -} - -/******************************************************************************* -* Function Name : UART_GetITStatus -* Description : Checks whether the specified UART interrupt has occurred or not. -* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral. -* - UART_IT: specifies the interrupt source to check. -* This parameter can be one of the following values: -* - UART_IT_OverrunError: Overrun Error interrupt -* - UART_IT_BreakError: Break Error interrupt -* - UART_IT_ParityError: Parity Error interrupt -* - UART_IT_FrameError: Frame Error interrupt -* - UART_IT_ReceiveTimeOut: Receive Time Out interrupt -* - UART_IT_Transmit: Transmit interrupt -* - UART_IT_Receive: Receive interrupt -* - UART_IT_CTS: CTS interrupt -* Output : None -* Return : The new state of UART_IT (SET or RESET). -*******************************************************************************/ -ITStatus UART_GetITStatus(UART_TypeDef* UARTx, u16 UART_IT) -{ - if((UARTx->MIS & UART_IT) != RESET) - { - return SET; - } - else - { - return RESET; - } -} - -/******************************************************************************* -* Function Name : UART_ClearITPendingBit -* Description : Clears the UARTx’s interrupt pending bits. -* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral. -* - UART_IT: specifies the interrupt pending bit to clear. -* More than one interrupt can be cleared using the “|” operator. -* This parameter can be: -* - UART_IT_OverrunError: Overrun Error interrupt -* - UART_IT_BreakError: Break Error interrupt -* - UART_IT_ParityError: Parity Error interrupt -* - UART_IT_FrameError: Frame Error interrupt -* - UART_IT_ReceiveTimeOut: Receive Time Out interrupt -* - UART_IT_Transmit: Transmit interrupt -* - UART_IT_Receive: Receive interrupt -* - UART_IT_CTS: CTS interrupt -* Output : None -* Return : None -*******************************************************************************/ -void UART_ClearITPendingBit(UART_TypeDef* UARTx, u16 UART_IT) -{ - /* Clear the specified interrupt */ - UARTx->ICR = UART_IT; -} - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_wdg.c b/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_wdg.c deleted file mode 100644 index 812d627a9..000000000 --- a/Demo/ARM7_STR75x_GCC/STLibrary/src/75x_wdg.c +++ /dev/null @@ -1,244 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_wdg.c -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file provides all the WDG software functions. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -#include "75x_wdg.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Registers reset value */ -#define WDG_Preload_Mask 0xFFFF -#define WDG_Prescaler_Mask 0xFF - -/* WDG Start/Stop counter */ -#define WDG_Counter_Start_Mask 0x0002 -#define WDG_Counter_Stop_Mask 0xFFFD - -/* WDG Sequence */ -#define WDG_KeyValue1_Mask 0xA55A -#define WDG_KeyValue2_Mask 0x5AA5 - -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/****************************************************************************** -* Function Name : WDG_DeInit -* Description : Deinitializes the WDG peripheral registers to their default -* reset values. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void WDG_DeInit(void) -{ - /* Reset all the WDG registers */ - WDG->CR = 0x0000; - WDG->PR = 0x00FF; - WDG->VR = 0xFFFF; - WDG->CNT = 0xFFFF; - WDG->SR = 0x0000; - WDG->MR = 0x0000; - WDG->KR = 0x0000; -} - -/******************************************************************************* -* Function Name : WDG_Init -* Description : Initializes WDG peripheral according to the specified -* parameters in the WDG_InitStruct. -* Input : WDG_InitStruct: pointer to a WDG_InitTypeDef structure that -* contains the configuration information for the WDG peripheral. -* Output : None -* Return : None -*******************************************************************************/ -void WDG_Init(WDG_InitTypeDef* WDG_InitStruct) -{ - /* Configure WDG Prescaler register value */ - WDG->PR = WDG_InitStruct->WDG_Prescaler; - - /* Configure WDG Pre-load register value */ - WDG->VR = WDG_InitStruct->WDG_Preload ; - - if(WDG_InitStruct->WDG_Mode == WDG_Mode_WDG) - { - /* Select WDG mode */ - WDG->CR |= WDG_Mode_WDG ; - } - else - { - /* Select Timer mode */ - WDG->CR &= WDG_Mode_Timer; - } -} - -/******************************************************************************* -* Function Name : WDG_StructInit -* Description : Fills each WDG_InitStruct member with its default value. -* Input : WDG_InitStruct : pointer to a WDG_InitTypeDef structure -* which will be initialized. -* Output : None -* Return : None -*******************************************************************************/ -void WDG_StructInit(WDG_InitTypeDef *WDG_InitStruct) -{ - /* Initialize mode */ - WDG_InitStruct->WDG_Mode = WDG_Mode_Timer; - - /* Initialize Preload */ - WDG_InitStruct->WDG_Preload = WDG_Preload_Mask ; - - /* Initialize Prescaler */ - WDG_InitStruct->WDG_Prescaler = WDG_Prescaler_Mask; -} - -/******************************************************************************* -* Function Name : WDG_Cmd -* Description : Enables or disables the WDG peripheral. -* Input : NewState: new state of the WDG peripheral. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void WDG_Cmd(FunctionalState NewState) -{ - if((WDG->CR & WDG_Mode_WDG) == 0) - { - /* Timer mode */ - if(NewState == ENABLE) - { - /* Start timer by setting SC bit in Control register */ - WDG->CR |= WDG_Counter_Start_Mask; - } - else - { - /* Stop timer by clearing SC bit in Control register */ - WDG->CR &= WDG_Counter_Stop_Mask; - } - } - else - { - /* Watchdog mode */ - if(NewState == ENABLE) - { - WDG->KR = WDG_KeyValue1_Mask; - WDG->KR = WDG_KeyValue2_Mask; - } - } -} - -/******************************************************************************* -* Function Name : WDG_ITConfig -* Description : Enables or disables the WDG End of Count(EC) interrupt. -* Input : Newstate: new state of the WDG End of Count(EC) interrupt. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void WDG_ITConfig(FunctionalState NewState) -{ - if(NewState == ENABLE) - { - /* Enable the End of Count interrupt */ - WDG->MR |= WDG_IT_EC; - } - else - { - /* Disable the End of Count interrupt */ - WDG->MR &= ~WDG_IT_EC; - } -} - -/******************************************************************************* -* Function Name : WDG_GetCounter -* Description : Gets the WDG’s current counter value. -* Input : None -* Output : None -* Return : The WDG current counter value -*******************************************************************************/ -u16 WDG_GetCounter(void) -{ - return WDG->CNT; -} - -/******************************************************************************* -* Function Name : WDG_GetFlagStatus -* Description : Checks whether the WDG End of Count(EC) flag is set or not. -* Input : None -* Output : None -* Return : The new state of WDG End of Count(EC) flag (SET or RESET). -*******************************************************************************/ -FlagStatus WDG_GetFlagStatus(void) -{ - if((WDG->SR & WDG_FLAG_EC) != RESET ) - { - return SET; - } - else - { - return RESET; - } -} - -/******************************************************************************* -* Function Name : WDG_ClearFlag -* Description : Clears the WDG’s End of Count(EC) pending flag. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void WDG_ClearFlag(void) -{ - /* Clear the EC pending bit */ - WDG->SR &= ~WDG_FLAG_EC; -} - -/******************************************************************************* -* Function Name : WDG_GetITStatus -* Description : Checks whether the WDG End of Count(EC) interrupt has -* occurred or not. -* Input : None -* Output : None -* Return : The new state of WDG End of Count(EC) interrupt (SET or RESET). -*******************************************************************************/ -ITStatus WDG_GetITStatus(void) -{ - if(((WDG->SR & WDG_IT_EC) != RESET )&&((WDG->MR & WDG_IT_EC) != RESET )) - { - return SET; - } - else - { - return RESET; - } -} - -/******************************************************************************* -* Function Name : WDG_ClearITPendingBit -* Description : Clears the WDG's End of Count(EC) interrupt pending bit. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void WDG_ClearITPendingBit(void) -{ - /* Clear the EC pending bit */ - WDG->SR &= ~WDG_IT_EC; -} - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_GCC/STLibrary/src/lcd.c b/Demo/ARM7_STR75x_GCC/STLibrary/src/lcd.c deleted file mode 100644 index 3436bd22d..000000000 --- a/Demo/ARM7_STR75x_GCC/STLibrary/src/lcd.c +++ /dev/null @@ -1,1403 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : lcd.c -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file includes the LCD driver for GXM12232-2SL liquid -* Crystal Display Module of STR75x-EVAL. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -#include "lcd.h" - -/* Private typedef -----------------------------------------------------------*/ - - /* Peripherals InitStructure define */ -GPIO_InitTypeDef GPIO_InitStructure; - -/* Private define ------------------------------------------------------------*/ -#define LCD_GPIO_Pins 0x3FC00 -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - /* Global variable to set the written text color: used for LCD_Printf */ - TextColorMode_TypeDef TextMode = BlackText; - - /* ASCII Table: each character is 7 column (7dots large) on two pages (16dots high) */ - /* 7 column character: Two 8bit data to display one column*/ - const u8 AsciiDotsTable[1778] = { - /* ASCII 0 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 1 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 2 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 3 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 4 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 5 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 6 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 7 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 8 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 9 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - /* ASCII 10 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - /* ASCII 11 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 12 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 13 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - /* ASCII 14 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 15 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 16 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 17 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 18 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 19 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 20 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 21 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 22 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 23 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 24 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 25 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 26 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 27 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 28 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - /* ASCII 29 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - /* ASCII 30 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - /* ASCII 31 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - /* ASCII 32 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - /* ASCII 33 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x13,0xe0,0x00,0x00,0x00,0x00,0x00,0x00, - /* ASCII 34 */ 0x00,0x00,0x00,0xe0,0x00,0x20,0x00,0x00,0x00,0xe0,0x00,0x20,0x00,0x00, - /* ASCII 35 */ 0x00,0x00,0x35,0x00,0x0f,0x80,0x35,0x60,0x0f,0x80,0x05,0x60,0x00,0x00, - /* ASCII 36 */ 0x00,0x00,0x0d,0x80,0x0a,0x40,0x3a,0x60,0x06,0x40,0x00,0x00,0x00,0x00, - /* ASCII 37 */ 0x00,0x00,0x02,0x40,0x02,0xa0,0x0a,0x40,0x15,0x00,0x09,0x00,0x00,0x00, - /* ASCII 38 */ 0x00,0x00,0x0c,0x00,0x13,0x00,0x14,0x80,0x08,0x80,0x14,0x00,0x00,0x00, - /* ASCII 39 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xe0,0x00,0x00,0x00,0x00,0x00,0x00, - /* ASCII 40 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x1f,0x80,0x60,0x60,0x00,0x00,0x00,0x00, - /* ASCII 41 */ 0x00,0x00,0x00,0x00,0x60,0x60,0x1f,0x80,0x00,0x00,0x00,0x00,0x00,0x00, - /* ASCII 42 */ 0x00,0x00,0x00,0x40,0x03,0x40,0x00,0xe0,0x03,0x40,0x00,0x40,0x00,0x00, - /* ASCII 43 */ 0x02,0x00,0x02,0x00,0x02,0x00,0x1f,0xc0,0x02,0x00,0x02,0x00,0x02,0x00, - /* ASCII 44 */ 0x00,0x00,0x00,0x00,0x60,0x00,0x38,0x00,0x08,0x00,0x00,0x00,0x00,0x00, - /* ASCII 45 */ 0x00,0x00,0x02,0x00,0x02,0x00,0x02,0x00,0x02,0x00,0x02,0x00,0x00,0x00, - /* ASCII 46 */ 0x00,0x00,0x00,0x00,0x18,0x00,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - /* ASCII 47 */ 0x00,0x00,0x20,0x00,0x18,0x00,0x06,0x00,0x01,0x80,0x00,0x60,0x00,0x00, - /* ASCII 48 */ 0x00,0x00,0x0f,0xc0,0x10,0x20,0x10,0x20,0x10,0x20,0x0f,0xc0,0x00,0x00, - /* ASCII 49 */ 0x00,0x00,0x10,0x00,0x10,0x20,0x1f,0xe0,0x10,0x00,0x10,0x00,0x00,0x00, - /* ASCII 50 */ 0x00,0x00,0x18,0x40,0x14,0x20,0x12,0x20,0x11,0x20,0x18,0xc0,0x00,0x00, - /* ASCII 51 */ 0x00,0x00,0x08,0x40,0x10,0x20,0x11,0x20,0x11,0x20,0x0e,0xc0,0x00,0x00, - /* ASCII 52 */ 0x00,0x00,0x06,0x00,0x05,0x00,0x04,0xc0,0x14,0x20,0x1f,0xe0,0x14,0x00, - /* ASCII 53 */ 0x00,0x00,0x08,0x00,0x11,0xe0,0x11,0x20,0x11,0x20,0x0e,0x20,0x00,0x00, - /* ASCII 54 */ 0x00,0x00,0x0f,0x80,0x11,0x40,0x11,0x20,0x11,0x20,0x0e,0x20,0x00,0x00, - /* ASCII 55 */ 0x00,0x00,0x00,0x60,0x00,0x20,0x18,0x20,0x07,0x20,0x00,0xe0,0x00,0x00, - /* ASCII 56 */ 0x00,0x00,0x0e,0xc0,0x11,0x20,0x11,0x20,0x11,0x20,0x0e,0xc0,0x00,0x00, - /* ASCII 57 */ 0x00,0x00,0x11,0xc0,0x12,0x20,0x12,0x20,0x0a,0x20,0x07,0xc0,0x00,0x00, - /* ASCII 58 */ 0x00,0x00,0x00,0x00,0x19,0x80,0x19,0x80,0x00,0x00,0x00,0x00,0x00,0x00, - /* ASCII 59 */ 0x00,0x00,0x00,0x00,0x30,0x00,0x19,0x80,0x09,0x80,0x00,0x00,0x00,0x00, - /* ASCII 60 */ 0x02,0x00,0x05,0x00,0x05,0x00,0x08,0x80,0x10,0x40,0x10,0x40,0x00,0x00, - /* ASCII 61 */ 0x00,0x00,0x05,0x00,0x05,0x00,0x05,0x00,0x05,0x00,0x05,0x00,0x00,0x00, - /* ASCII 62 */ 0x10,0x40,0x10,0x40,0x08,0x80,0x05,0x00,0x05,0x00,0x02,0x00,0x00,0x00, - /* ASCII 63 */ 0x00,0x00,0x00,0x00,0x10,0x80,0x14,0x40,0x02,0x40,0x01,0x80,0x00,0x00, - /* ASCII 64 */ 0x00,0x00,0x1f,0xe0,0x20,0x10,0x23,0x10,0x24,0x90,0x17,0xe0,0x00,0x00, - /* ASCII 65 */ 0x10,0x00,0x1c,0x00,0x17,0xa0,0x04,0x60,0x17,0x80,0x1c,0x00,0x10,0x00, - /* ASCII 66 */ 0x10,0x20,0x1f,0xe0,0x11,0x20,0x11,0x20,0x11,0x20,0x0e,0xc0,0x00,0x00, - /* ASCII 67 */ 0x00,0x00,0x0f,0xc0,0x10,0x20,0x10,0x20,0x10,0x20,0x08,0x60,0x00,0x00, - /* ASCII 68 */ 0x10,0x20,0x1f,0xe0,0x10,0x20,0x10,0x20,0x08,0x40,0x07,0x80,0x00,0x00, - /* ASCII 69 */ 0x10,0x20,0x1f,0xe0,0x11,0x20,0x13,0xa0,0x10,0x20,0x18,0x60,0x00,0x00, - /* ASCII 70 */ 0x00,0x00,0x10,0x20,0x1f,0xe0,0x11,0x20,0x03,0xa0,0x00,0x20,0x00,0x60, - /* ASCII 71 */ 0x00,0x00,0x0f,0xc0,0x10,0x20,0x10,0x20,0x12,0x20,0x0e,0x60,0x02,0x00, - /* ASCII 72 */ 0x10,0x20,0x1f,0xe0,0x11,0x20,0x01,0x00,0x11,0x20,0x1f,0xe0,0x10,0x20, - /* ASCII 73 */ 0x00,0x00,0x10,0x20,0x10,0x20,0x1f,0xe0,0x10,0x20,0x10,0x20,0x00,0x00, - /* ASCII 74 */ 0x00,0x00,0x0e,0x00,0x10,0x20,0x10,0x20,0x0f,0xe0,0x00,0x20,0x00,0x00, - /* ASCII 75 */ 0x10,0x20,0x1f,0xe0,0x12,0x20,0x03,0x00,0x04,0xa0,0x18,0x60,0x10,0x20, - /* ASCII 76 */ 0x00,0x00,0x10,0x20,0x1f,0xe0,0x10,0x20,0x10,0x00,0x1c,0x00,0x00,0x00, - /* ASCII 77 */ 0x10,0x20,0x1f,0xe0,0x10,0xe0,0x03,0x00,0x10,0xe0,0x1f,0xe0,0x10,0x20, - /* ASCII 78 */ 0x10,0x20,0x1f,0xe0,0x10,0xe0,0x07,0x00,0x18,0x20,0x1f,0xe0,0x00,0x20, - /* ASCII 79 */ 0x00,0x00,0x0f,0xc0,0x10,0x20,0x10,0x20,0x10,0x20,0x0f,0xc0,0x00,0x00, - /* ASCII 80 */ 0x00,0x00,0x10,0x20,0x1f,0xe0,0x12,0x20,0x02,0x20,0x01,0xc0,0x00,0x00, - /* ASCII 81 */ 0x00,0x00,0x0f,0xc0,0x10,0x20,0x30,0x20,0x30,0x20,0x2f,0xc0,0x00,0x00, - /* ASCII 82 */ 0x10,0x20,0x1f,0xe0,0x12,0x20,0x02,0x20,0x06,0x20,0x09,0xc0,0x10,0x00, - /* ASCII 83 */ 0x00,0x00,0x18,0xc0,0x09,0x20,0x11,0x20,0x11,0x40,0x0e,0x60,0x00,0x00, - /* ASCII 84 */ 0x00,0x60,0x00,0x20,0x10,0x20,0x1f,0xe0,0x10,0x20,0x00,0x20,0x00,0x60, - /* ASCII 85 */ 0x00,0x20,0x0f,0xe0,0x10,0x20,0x10,0x00,0x10,0x20,0x0f,0xe0,0x00,0x20, - /* ASCII 86 */ 0x00,0x20,0x00,0xe0,0x07,0x20,0x18,0x00,0x07,0x20,0x00,0xe0,0x00,0x20, - /* ASCII 87 */ 0x00,0x20,0x0f,0xe0,0x10,0x20,0x0f,0x00,0x10,0x20,0x0f,0xe0,0x00,0x20, - /* ASCII 88 */ 0x10,0x20,0x18,0x60,0x04,0x80,0x03,0x00,0x04,0x80,0x18,0x60,0x10,0x20, - /* ASCII 89 */ 0x00,0x20,0x00,0x60,0x11,0xa0,0x1e,0x00,0x11,0xa0,0x00,0x60,0x00,0x20, - /* ASCII 90 */ 0x00,0x00,0x18,0x60,0x14,0x20,0x13,0x20,0x10,0xa0,0x18,0x60,0x00,0x00, - /* ASCII 91 */ 0x00,0x00,0x00,0x00,0x7f,0xe0,0x40,0x20,0x40,0x20,0x00,0x00,0x00,0x00, - /* ASCII 92 */ 0x00,0x00,0x00,0x20,0x01,0xc0,0x06,0x00,0x38,0x00,0x00,0x00,0x00,0x00, - /* ASCII 93 */ 0x00,0x00,0x00,0x00,0x40,0x20,0x40,0x20,0x7f,0xe0,0x00,0x00,0x00,0x00, - /* ASCII 94 */ 0x00,0x00,0x01,0x00,0x00,0x80,0x00,0x60,0x00,0x80,0x01,0x00,0x00,0x00, - /* ASCII 95 */ 0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00, - /* ASCII 96 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x40,0x00,0x00,0x00,0x00, - /* ASCII 97 */ 0x00,0x00,0x0d,0x00,0x12,0x80,0x12,0x80,0x12,0x80,0x1f,0x00,0x10,0x00, - /* ASCII 98 */ 0x10,0x20,0x1f,0xe0,0x11,0x00,0x10,0x80,0x10,0x80,0x0f,0x00,0x00,0x00, - /* ASCII 99 */ 0x00,0x00,0x0f,0x00,0x10,0x80,0x10,0x80,0x10,0x80,0x09,0x80,0x00,0x00, - /* ASCII 100 */ 0x00,0x00,0x0f,0x00,0x10,0x80,0x10,0x80,0x11,0x20,0x1f,0xe0,0x10,0x00, - /* ASCII 101 */ 0x00,0x00,0x0f,0x00,0x12,0x80,0x12,0x80,0x12,0x80,0x13,0x00,0x00,0x00, - /* ASCII 102 */ 0x00,0x00,0x10,0x80,0x1f,0xc0,0x10,0xa0,0x10,0xa0,0x10,0xa0,0x00,0x00, - /* ASCII 103 */ 0x00,0x00,0x0f,0x00,0x50,0x80,0x50,0x80,0x51,0x00,0x3f,0x80,0x00,0x80, - /* ASCII 104 */ 0x10,0x20,0x1f,0xe0,0x11,0x00,0x00,0x80,0x10,0x80,0x1f,0x00,0x10,0x00, - /* ASCII 105 */ 0x00,0x00,0x10,0x80,0x10,0x80,0x1f,0xa0,0x10,0x00,0x10,0x00,0x00,0x00, - /* ASCII 106 */ 0x00,0x00,0x40,0x80,0x40,0x80,0x40,0xa0,0x3f,0x80,0x00,0x00,0x00,0x00, - /* ASCII 107 */ 0x10,0x20,0x1f,0xe0,0x02,0x00,0x16,0x80,0x19,0x80,0x10,0x80,0x00,0x00, - /* ASCII 108 */ 0x00,0x00,0x10,0x00,0x10,0x20,0x1f,0xe0,0x10,0x00,0x10,0x00,0x00,0x00, - /* ASCII 109 */ 0x10,0x80,0x1f,0x80,0x10,0x80,0x1f,0x00,0x10,0x80,0x1f,0x00,0x10,0x00, - /* ASCII 110 */ 0x10,0x80,0x1f,0x80,0x11,0x00,0x00,0x80,0x10,0x80,0x1f,0x00,0x10,0x00, - /* ASCII 111 */ 0x00,0x00,0x0f,0x00,0x10,0x80,0x10,0x80,0x10,0x80,0x0f,0x00,0x00,0x00, - /* ASCII 112 */ 0x40,0x80,0x7f,0x80,0x51,0x00,0x10,0x80,0x10,0x80,0x0f,0x00,0x00,0x00, - /* ASCII 113 */ 0x00,0x00,0x0f,0x00,0x10,0x80,0x10,0x80,0x51,0x00,0x7f,0x80,0x40,0x80, - /* ASCII 114 */ 0x00,0x00,0x10,0x80,0x1f,0x80,0x11,0x00,0x10,0x80,0x10,0x80,0x00,0x00, - /* ASCII 115 */ 0x00,0x00,0x19,0x00,0x12,0x80,0x12,0x80,0x12,0x80,0x0d,0x80,0x00,0x00, - /* ASCII 116 */ 0x00,0x00,0x00,0x80,0x0f,0xc0,0x10,0x80,0x10,0x80,0x10,0x80,0x08,0x00, - /* ASCII 117 */ 0x00,0x80,0x0f,0x80,0x10,0x00,0x10,0x00,0x08,0x80,0x1f,0x80,0x10,0x00, - /* ASCII 118 */ 0x00,0x80,0x03,0x80,0x0c,0x80,0x10,0x00,0x0c,0x80,0x03,0x80,0x00,0x80, - /* ASCII 119 */ 0x00,0x80,0x0f,0x80,0x10,0x80,0x0e,0x00,0x10,0x80,0x0f,0x80,0x00,0x80, - /* ASCII 120 */ 0x10,0x80,0x19,0x80,0x06,0x00,0x06,0x00,0x19,0x80,0x10,0x80,0x00,0x00, - /* ASCII 121 */ 0x00,0x80,0x41,0x80,0x46,0x80,0x78,0x00,0x4c,0x80,0x03,0x80,0x00,0x80, - /* ASCII 122 */ 0x00,0x00,0x19,0x80,0x14,0x80,0x12,0x80,0x11,0x80,0x18,0x80,0x00,0x00, - /* ASCII 123 */ 0x00,0x00,0x00,0x00,0x04,0x00,0x3b,0xc0,0x40,0x20,0x00,0x00,0x00,0x00, - /* ASCII 124 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x3f,0xe0,0x00,0x00,0x00,0x00,0x00,0x00, - /* ASCII 125 */ 0x00,0x00,0x00,0x00,0x40,0x20,0x3b,0xc0,0x04,0x00,0x00,0x00,0x00,0x00, - /* ASCII 126 */ 0x00,0x00,0x04,0x00,0x02,0x00,0x04,0x00,0x04,0x00,0x02,0x00,0x00,0x00}; - -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/******************************************************************************* -* Function Name : LCD_DataLinesConfig -* Description : Configure data lines D0~D7 (P2.10~P2.17) in Input Floating mode -* for read from LCD or in Output Push-Pull mode for write on LCD -* Input : - Mode: specifies the configuration mode for data lines D0~D7 -* - Input: configure in Input Floating mode -* - Output: configure in Output Push-Pul mode -* Output : None -* Return : None -*******************************************************************************/ -void LCD_DataLinesConfig(DataConfigMode_TypeDef Mode) -{ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | - GPIO_Pin_14 | GPIO_Pin_15 | GPIO_Pin_16 | GPIO_Pin_17; - if (Mode == Input) - { - /* Configure D0~D7 lines (P2.10~2.17) in Input Floating mode */ - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - } - else - { - /* Configure D0~D7 lines (P2.10~2.17) in Output Push-Pull mode */ - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; - } - GPIO_Init(GPIO2, &GPIO_InitStructure); -} - -/******************************************************************************* -* Function Name : LCD_DataLinesWrite -* Description : Write a value on D0~D7 (P2.10~P2.17) -* Input : - GPIOx: GPIO port to write on. It could be -* - PortVal: value to write -* Output : None -* Return : None. -*******************************************************************************/ -void LCD_DataLinesWrite(GPIO_TypeDef* GPIOx, u32 PortVal) -{ - u32 Tmp = 0; - - /* Store the PM register value */ - Tmp = GPIO_GetPortMask(GPIOx); - /* Mask the corresponding GPIO pins */ - GPIO_PinMaskConfig(GPIOx, LCD_GPIO_Pins, DISABLE); - GPIO_PinMaskConfig(GPIOx, ~LCD_GPIO_Pins, ENABLE); - /* Write in the hole register */ - GPIO_Write(GPIOx, (PortVal<<10)); - - GPIO_PinMaskConfig(GPIOx, ~LCD_GPIO_Pins, DISABLE); - /* Return the initial PM register value */ - GPIO_PinMaskConfig(GPIOx, Tmp, ENABLE); - -} - -/******************************************************************************* -* Function Name : LCD_CtrlLinesConfig -* Description : Configure control lines E2, E1, RW, DI (P2.0~P2.3) in -* Output Push-Pull mode. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void LCD_CtrlLinesConfig(void) -{ - /* Configure E2, E1, RW, DI lines (P2.0~2.3) in Output Push-Pull mode */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; - GPIO_Init(GPIO2, &GPIO_InitStructure); -} - -/******************************************************************************* -* Function Name : LCD_CtrlLinesWrite -* Description : Set or reset control lines E2, E1, RW, DI (P2.0~P2.3). -* Input : - GPIOx: where x can be 0,1 or 2 to select the GPIO peripheral. -* - CtrlPins: the Control line. This parameter can be: -* - CtrlPin_E2: Enabe clock signal for Slave -* - CtrlPin_E1: Enabe clock signal for Master -* - CtrlPin_RW: Read/Write control line -* - CtrlPin_DI: -* Output : None -* Return : None -*******************************************************************************/ -void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, u32 CtrlPins, BitAction BitVal) -{ - /* Set or Reset the control line */ - if(BitVal != Bit_RESET) - { - GPIOx->PD |= CtrlPins; - } - else - { - GPIOx->PD &= ~CtrlPins; - } -} - -/******************************************************************************* -* Function Name : LCD_CheckMasterStatus -* Description : Check whether master LCD is busy or not -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void LCD_CheckMasterStatus(void) -{ - u8 MasterStatus = 0; - - /* Configure Data lines as Input */ - LCD_DataLinesConfig(Input); - /* Start the master read sequence */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_RW, Bit_SET); /* RW = 1 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_DI, Bit_RESET); /* DI = 0 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_SET); /* E1 = 1 */ - MasterStatus = GPIO_Read(GPIO2); - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ - - /* Wait until BF is cleared: D7 line */ - while ((MasterStatus & 0x20000)) - { - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_SET); /* E1 = 1 */ - MasterStatus = GPIO_Read(GPIO2); - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ - } -} - -/******************************************************************************* -* Function Name : LCD_CheckSlaveStatus -* Description : Check whether slave LCD is busy or not -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void LCD_CheckSlaveStatus(void) -{ - u8 SlaveStatus = 0; - - /* Configure Data lines as Input */ - LCD_DataLinesConfig(Input); - /* Start the slave read sequence */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_RW, Bit_SET); /* RW = 1 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_DI, Bit_RESET); /* DI = 0 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_SET); /* E2 = 1 */ - SlaveStatus = GPIO_Read(GPIO2); - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ - - /* Wait until BF is cleared: D7 line */ - while ((SlaveStatus & 0x20000)) - { - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_SET); /* E2 = 1 */ - SlaveStatus = GPIO_Read(GPIO2); - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ - } -} - -/******************************************************************************* -* Function Name : LCD_SendMasterCmd -* Description : Send one byte command to master LCD. -* Input : - Cmd: the user expected command to send to master LCD -* Output : None -* Return : None -*******************************************************************************/ -void LCD_SendMasterCmd(u8 Cmd) -{ - /* Check the master status */ - LCD_CheckMasterStatus(); - /* Configure Data lines as Output */ - LCD_DataLinesConfig(Output); - /* Start the master send command sequence */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_RW, Bit_RESET); /* RW = 0 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_DI, Bit_RESET); /* DI = 0 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_SET); /* E1 = 1 */ - /* Write master command */ - LCD_DataLinesWrite(GPIO2, (u32)Cmd); - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ -} - -/******************************************************************************* -* Function Name : LCD_SendSlaveCmd -* Description : Send one byte command to slave LCD -* Input : - Cmd: the user expected command to send to slave LCD. -* Output : None -* Return : None -*******************************************************************************/ -void LCD_SendSlaveCmd(u8 Cmd) -{ - /* Check the slave status */ - LCD_CheckSlaveStatus(); - /* Configure Data lines as Output */ - LCD_DataLinesConfig(Output); - /* Start the slave send command sequence */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_RW, Bit_RESET); /* RW = 0 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_DI, Bit_RESET); /* DI = 0 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_SET); /* E2 = 1 */ - /* Write slave command */ - LCD_DataLinesWrite(GPIO2, (u32)Cmd); - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ -} - -/******************************************************************************* -* Function Name : LCD_SendMasterData -* Description : Display one byte data to master LCD. -* Input : - Data: the user expected data to display on master LCD. -* Output : None -* Return : None -*******************************************************************************/ -void LCD_SendMasterData(u8 Data) -{ - /* Check the master status */ - LCD_CheckMasterStatus(); - /* Configure Data lines as Output */ - LCD_DataLinesConfig(Output); - /* Start the master send data sequence */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_RW, Bit_RESET); /* RW = 0 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_DI, Bit_SET); /* DI = 1 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_SET); /* E1 = 1 */ - /* Write data to the master */ - LCD_DataLinesWrite(GPIO2, (u32)Data); - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ -} - -/******************************************************************************* -* Function Name : LCD_ReadMasterData -* Description : Read master byte data displayed on master LCD. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -u32 LCD_ReadMasterData(void) -{ - u32 MasterData = 0; - - /* Check the master status */ - LCD_CheckMasterStatus(); - /* Configure Data lines as Input */ - LCD_DataLinesConfig(Input); - /* Start the master read data sequence */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_RW, Bit_SET); /* RW = 1 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_DI, Bit_SET); /* DI = 1 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_SET); /* E1 = 1 */ - /* Read data from the master */ - MasterData = ((GPIO_Read(GPIO2)&0x3FC00)>>10); - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ - /* Read the master returned data */ - return MasterData; -} - -/******************************************************************************* -* Function Name : LCD_SendSlaveData -* Description : Display one byte data to slave LCD. -* Input : - Data: the user expected data to display on slave LCD. -* Output : None -* Return : None -*******************************************************************************/ -void LCD_SendSlaveData(u8 Data) -{ - /* Check the slave status */ - LCD_CheckSlaveStatus(); - /* Configure Data lines as Output */ - LCD_DataLinesConfig(Output); - /* Start the slave send data sequence */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_RW, Bit_RESET); /* RW = 0 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_DI, Bit_SET); /* DI = 1 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_SET); /* E2 = 1 */ - /* Write data to the slave */ - LCD_DataLinesWrite(GPIO2, (u32)Data); - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ -} - -/******************************************************************************* -* Function Name : LCD_ReadSlaveData -* Description : Read slave byte data displayed on slave LCD. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -u32 LCD_ReadSlaveData(void) -{ - u32 SlaveData = 0; - - /* Check the slave status */ - LCD_CheckSlaveStatus(); - /* Configure Data lines as Input */ - LCD_DataLinesConfig(Input); - /* Start the slave read data sequence */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_RW, Bit_SET); /* RW = 1 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_DI, Bit_SET); /* DI = 1 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_SET); /* E2 = 1 */ - /* Read data from the slave */ - SlaveData = ((GPIO_Read(GPIO2)&0x3FC00)>>10); - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ - /* Read the slave returned data */ - return SlaveData; -} - -/******************************************************************************* -* Function Name : LCD_Init -* Description : Initialize master and slave LCD. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void LCD_Init(void) -{ - /* Enable GPIO Clock */ - MRCC_PeripheralClockConfig(MRCC_Peripheral_GPIO, ENABLE); - - /* Configure control lines signals as output mode */ - LCD_CtrlLinesConfig(); - - /* Master LCD Init */ - LCD_SendMasterCmd(SOFTWARE_RESET); - LCD_SendMasterCmd(DISPLAY_OFF); - LCD_SendMasterCmd(DYNAMIC_DRIVE); - LCD_SendMasterCmd(DUTY_CYCLE); - LCD_SendMasterCmd(CLOCKWISE_OUTPUT); - LCD_SendMasterCmd(READ_MODIFY_WRITE_OFF); - LCD_SendMasterCmd(START_COLUMN); /* Set master column address to 0 */ - LCD_SendMasterCmd(START_LINE); /* Set master display start line to 0 */ - LCD_SendMasterCmd(DISPLAY_ON ); - - /* Slave LCD Init */ - LCD_SendSlaveCmd(SOFTWARE_RESET); - LCD_SendSlaveCmd(DISPLAY_OFF); - LCD_SendSlaveCmd(DYNAMIC_DRIVE); - LCD_SendSlaveCmd(DUTY_CYCLE); - LCD_SendSlaveCmd(CLOCKWISE_OUTPUT); - LCD_SendSlaveCmd(READ_MODIFY_WRITE_OFF); - LCD_SendSlaveCmd(START_COLUMN ); /* Set slave column address to 0 */ - LCD_SendSlaveCmd(START_LINE); /* Set slave display start line to 0 */ - LCD_SendSlaveCmd(DISPLAY_ON); - - /* Clear LCD */ - LCD_Clear(); - /* Set current Page to 0 for Master and Slave LCDs */ - LCD_SetSlavePage(0); - LCD_SetMasterPage(0); -} - -/******************************************************************************* -* Function Name : LCD_SetSlavePage -* Description : Set the display page of slave LCD, the page range is 0 to 3, -* make sure the input will not exceed this range ,otherwise it -* will reach a undecided result. -* Input : - Page: specifies the expected display page of slave LCD -* Output : None -* Return : None -*******************************************************************************/ -void LCD_SetSlavePage(u8 Page) -{ - /* Set Slave page */ - LCD_SendSlaveCmd(0xB8|Page); -} - -/******************************************************************************* -* Function Name : LCD_SetMasterPage -* Description : Set the display page of master LCD, the page range is 0 to 3, -* make sure the input will not exceed this range ,otherwise it -* will reach a undecided result. -* Input : - Page: specifies the expected display page of master LCD -* Output : None -* Return : None -*******************************************************************************/ -void LCD_SetMasterPage(u8 Page) -{ - /* Set Master page */ - LCD_SendMasterCmd(0xB8|Page); -} - -/******************************************************************************* -* Function Name : SetAddress -* Description : Set the display column of slave LCD. Column range is 0 to 61. -* Input : - Address: specifies the expected display column of slave LCD -* Output : None -* Return : None -*******************************************************************************/ -void LCD_SetSlaveColumn(u8 Address) -{ - /* Set Slave column address */ - LCD_SendSlaveCmd(Address&0x7F); -} - -/******************************************************************************* -* Function Name : LCD_SetMasterColumn -* Description : Set the display column of master LCD. Column range is 0 to 61. -* Input : - Address: specifies the expected display column of slave LCD -* Output : None -* Return : None -*******************************************************************************/ -void LCD_SetMasterColumn(u8 Address) -{ - /* Set Master column address */ - LCD_SendMasterCmd(Address&0x7F); -} - -/******************************************************************************* -* Function Name : LCD_SetTextColor -* Description : Set the text color for LCD. -* Input : - TextColor: BlackText: character on black, bottom on white. -* WhiteText: character on white, bottom on black. -* Output : None -* Return : None -*******************************************************************************/ -void LCD_SetTextColor(TextColorMode_TypeDef TextColor) -{ - if(TextColor) - { - /* Set White Text color */ - TextMode=WhiteText; - } - else - { - /* Set Black Text color */ - TextMode=BlackText; - } -} - -/******************************************************************************* -* Function Name : LCD_Clear -* Description : Clear the Master and Slave LCDs display. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void LCD_Clear(void) -{ - u8 Page = 0, Column = 0; - - /* Clear master and slave LCDs page by page */ - for (Page=0; Page<4; Page++) - { - /* Set master and slave page by page */ - LCD_SetMasterPage(Page); - LCD_SetSlavePage(Page); - /* Set master and slave column address */ - LCD_SetMasterColumn(0); - LCD_SetSlaveColumn(0); - /* Send empty data to master and slave column address on the selected page */ - for (Column=0; Column<61; Column++) - { - LCD_SendSlaveData(0); - LCD_SendMasterData(0); - } - } -} - -/******************************************************************************* -* Function Name : LCD_ClearLine -* Description : Clear the selected line of the LCD. -* Input : - Line: the Line to clear. -* - Line1 (Page0&1): clear the first line -* - Line2 (Page2&3): clear the second line -* Output : None -* Return : None -*******************************************************************************/ -void LCD_ClearLine(u8 Line) -{ - u8 Page = 0, Column = 0; - - /* Clear the slected master and slave line */ - for (Page=Line; Page 121) - { - /* Return if column exceeded 121 */ - return; - } - if (X > 60) - { - /* To be displayed on slave LCD (Window = 1) */ - Window = 1; - /* Get the Slave relative start column */ - ActualColumn = X%61; - } - else - { - /* To be displayed on master LCD (Window = 0) */ - ActualColumn = X; - } - - /* Switch window, display the character upper part */ - if (Window) - { - /* Display it on slave LCD */ - LCD_SetSlavePage(Line); - LCD_SetSlaveColumn(ActualColumn); - LCD_SendSlaveData(Bmp[i]); - } - else - { - /* Display it on master LCD */ - LCD_SetMasterPage(Line); - LCD_SetMasterColumn(ActualColumn); - LCD_SendMasterData(Bmp[i]); - } - /* Switch window, diplay the character lower part */ - if (Window) - { - /* Display it on slave LCD */ - LCD_SetSlavePage(Line+1); - LCD_SetSlaveColumn(ActualColumn); - LCD_SendSlaveData(Bmp[i+1]); - } - else - { - /* Display it on master LCD */ - LCD_SetMasterPage(Line+1); - LCD_SetMasterColumn(ActualColumn); - LCD_SendMasterData(Bmp[i+1]); - } - /* Increment by 2 the character table index */ - i+=2; - } -} - -/******************************************************************************* -* Function Name : LCD_DisplayChar -* Description : Display one character (7dots large, 16dots high). -* Note: -* the LCD can only display two line character,so page 0 and 1 -* is to display the first line, page2 and page 3 is to display -* the second line. -* Input : - Line: the Line where to display the character. -* - Line1 (Page0&1): display character on the first line -* - Line2 (Page2&3): display character on the second line -* - Column: start column address. -* - Ascii: character ascii code. -* - CharMode: BlackText: character on black, bottom on white. -* WhiteText: character on white, bottom on black. -* Output : None -* Return : None -*******************************************************************************/ -void LCD_DisplayChar(u8 Line, u8 Column, u8 Ascii, TextColorMode_TypeDef CharMode) -{ - u8 DotBuffer[14], i = 0; - - /* Display the character lower and upper 8bit parts (2*7columns) */ - for (i=0;i<14;i++) - { - /* Character displayed as white Text on black buttom */ - if(CharMode) - { - if(i%2==0) - { - DotBuffer[i] = ~AsciiDotsTable[Ascii*14+i+1]; - } - else - { - DotBuffer[i] = ~AsciiDotsTable[Ascii*14+i-1]; - } - } - /* Character displayed as black Text on white buttom */ - else - { - if(i%2==0) - { - DotBuffer[i] = AsciiDotsTable[Ascii*14+i+1]; - } - else - { - DotBuffer[i] = AsciiDotsTable[Ascii*14+i-1]; - } - } - } - /* Display the asc code after conversion */ - LCD_DrawChar(Line, Column, 7, DotBuffer); -} - -/******************************************************************************* -* Function Name : LCD_HexToAsciiLow -* Description : This function is used to convert the low nibble of an -* unsigned byte (0-F hex) to ASCII. -* Input : - byte: byte to convert to ASCII. -* Output : None -* Return : ASCII value result of the conversion. -*******************************************************************************/ -u8 LCD_HexToAsciiLow(u8 byte) -{ - /* Keep lower nibble only */ - byte = byte & 0x0F; - /* If the ascii is a number */ - if (byte <= 0x09) - { - /* Add 0x30 to its ascii */ - return(byte + 0x30); - } - else - { - /* Add 0x37 to its ascii */ - return (byte + 0x37); - } -} - -/******************************************************************************* -* Function Name : LCD_HexToAsciiHigh -* Description : This function is used to convert the high nibble of an -* unsigned byte (0-F hex) to ASCII. -* Input : - byte: byte to convert to ASCII. -* Output : None -* Return : ASCII value result of the conversion. -*******************************************************************************/ -u8 LCD_HexToAsciiHigh(u8 byte) -{ - /* Keep upper nibble only */ - byte = byte & 0xF0; - byte = byte >> 4; - /* If the ascii is a number */ - if (byte <= 0x09) - { - /* Add 0x30 to display its ascii */ - return(byte + 0x30); - } - else - { - /* Add 0x37 to display its ascii */ - return (byte + 0x37); - } -} - -/******************************************************************************* -* Function Name : LCD_DisplayString -* Description : This function is used to display a 17char max string of -* characters on the LCD display on the selected line. -* Note: -* this function is the user interface to use the LCD driver. -* Input : - *ptr: pointer to string to display on LCD. -* - Line: the Line where to display the character. -* - Line1 (Page0&1): display character on the first line -* - Line2 (Page2&3): display character on the second line -* Output : None -* Return : None -*******************************************************************************/ -void LCD_DisplayString(u8 Line, u8 *ptr, TextColorMode_TypeDef CharMode) -{ - u8 RefColumn = 0, i = 0; - - /* Send the string character by character on lCD */ - while ((*ptr!=0)&(i<17)) - { - /* Display one character on LCD */ - LCD_DisplayChar(Line, RefColumn, *ptr, CharMode); - /* Increment the column position by 7 */ - RefColumn+=7; - /* Point on the next character */ - ptr++; - /* Increment the character counter */ - i++; - /* If we reach the maximum Line character */ - if(i==17) - { - LCD_DisplayChar(Line, RefColumn-1, 0x1f, CharMode); /* Add missed columns */ - } - } -} - -/******************************************************************************* -* Function Name : LCD_Printf -* Description : This function is used to display a string of characters -* on the LCD display. -* Note: -* this function is the user interface to use the LCD driver. -* Input : - *ptr: pointer to string to display on LCD. -* Output : None -* Return : None -*******************************************************************************/ -void LCD_Printf(u8 *ptr, ...) -{ - u8 RefColumn = 0, RefPage = 0, i = 0, c1 = 0; - u16 var = 0, c2 = 0, c3 = 0, c4 = 0, c5 = 0; - u32 WordVar = 0; - - /* Store pointer on LCD_Printf second parameter (String) */ - u8 *var_ptr=(u8 *)(&ptr+1); - - /* Send String */ - while (*ptr != 0) - { - c1 = *ptr; - /* Limited to AsciiDotsTable code table */ - if(c1 <= 128) - { - /* Carriage return */ - if ( *ptr == '\r') - { - ptr++; - RefColumn = 0; - } - /* Jump to Line2 */ - else if( *ptr == '\n') - { - /* Point on the string to display */ - ptr++; - /* Clear Line2 */ - LCD_ClearLine(Line2); - /* Point on first Line2 column */ - RefColumn = 0; - /* Increment RefPage by 2 */ - RefPage+=2; - } - /* Display value on the passed format */ - else if( *ptr == '%') - { - ptr++; - /* Display decimal value */ - if (*ptr == 'd') - { - ptr++; - /* Get the word value to display */ - WordVar = ((*var_ptr)|(*(var_ptr+1)<<8)|(*(var_ptr+2)<<16)); - c1=WordVar/10000; - c2=(WordVar%10000)/1000; - c3=(WordVar%1000)/100; - c4=(WordVar%100)/10; - c5=(WordVar%10); - /* Display the ten miles digit */ - if (c1!=0) - { - LCD_DisplayChar(RefPage, RefColumn, c1+0x30, TextMode); - RefColumn+=7; - } - /* Display the miles digit */ - if (!((c1==0)&(c2==0))) - { - LCD_DisplayChar(RefPage, RefColumn, c2+0x30, TextMode); - RefColumn+=7; - } - /* Display the hundred digit */ - if (!((c1==0)&(c2==0)&(c3==0))) - { - LCD_DisplayChar(RefPage, RefColumn, c3+0x30, TextMode); - RefColumn+=7; - } - /* Display the tens digit */ - if (!((c1==0)&(c2==0)&(c3==0)&(c4==0))) - { - LCD_DisplayChar(RefPage, RefColumn, c4+0x30, TextMode); - RefColumn+=7; - } - /* Display the rest */ - LCD_DisplayChar(RefPage, RefColumn, c5+0x30, TextMode); - RefColumn+=7; - } - /* Display 16bits Hex value */ - else if (*ptr == 'x') - { - ptr++; - /* Display 8bits MSB */ - var_ptr = var_ptr +1; - var = *var_ptr; - c1 = LCD_HexToAsciiHigh(var); - LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); - RefColumn+=7; - c1 = LCD_HexToAsciiLow(var); - LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); - RefColumn+=7; - /* Display 8bits LSB */ - var_ptr = var_ptr -1; - var = *var_ptr; - var_ptr = var_ptr +4; - c1 = LCD_HexToAsciiHigh(var); - LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); - RefColumn+=7; - c1 = LCD_HexToAsciiLow(var); - LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); - RefColumn+=7; - } - /* Display 32bits Hex value */ - else if (*ptr == 'w') - { - ptr++; - /* Display 16bits MSB */ - var_ptr = var_ptr +3; - var = *var_ptr; - c1 = LCD_HexToAsciiHigh(var); - LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); - RefColumn+=7; - c1 = LCD_HexToAsciiLow(var); - LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); - RefColumn+=7; - var_ptr = var_ptr -1; - var = *var_ptr; - c1 = LCD_HexToAsciiHigh(var); - LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); - RefColumn+=7; - c1 = LCD_HexToAsciiLow(var); - LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); - RefColumn+=7; - /* Display 16bits LSB */ - var_ptr = var_ptr -1; - var = *var_ptr; - var_ptr = var_ptr +4; - c1 = LCD_HexToAsciiHigh(var); - LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); - RefColumn+=7; - c1 = LCD_HexToAsciiLow(var); - LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); - RefColumn+=7; - var_ptr = var_ptr -5; - var = *var_ptr; - var_ptr = var_ptr +4; - c1 = LCD_HexToAsciiHigh(var); - LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); - RefColumn+=7; - c1 = LCD_HexToAsciiLow(var); - LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); - RefColumn+=7; - } - else - { - /* Display '%' character which is followed by (d, x or w) */ - ptr--; - c1 = *ptr; - LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); - RefColumn+=7; - ptr++; - i++; - if(i==17) - { - /* Add missed columns */ - LCD_DisplayChar(RefPage, RefColumn-1, 0x1f, TextMode); - RefColumn = 0; - RefPage+=2; - } - } - } - else - { - /* Display characters different from (\r, \n, %) */ - LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); - RefColumn+=7; - ptr++; - i++; - if(i==17) - { - /* Add missed columns */ - LCD_DisplayChar(RefPage, RefColumn-1, 0x1f, TextMode); - LCD_ClearLine(Line2); - RefColumn = 0; - RefPage+=2; - } - } - } - } - /* Display spaces if string doesn't reach the max LCD characters size */ - while(RefColumn<119) - { - /* Display Spaces */ - LCD_DisplayChar(RefPage, RefColumn, 0x20, TextMode); - RefColumn+=7; - /* Add missed columns */ - LCD_DisplayChar(RefPage, RefColumn, 0x1f, TextMode); - } -} - -/******************************************************************************* -* Function Name : LCD_DrawMasterGraphic -* Description : Draw a Graphic image on master LCD. -* Input : - Bmp: the pointer of the dot matrix data. -* Output : None -* Return : None. -*******************************************************************************/ -void LCD_DrawMasterGraphic(u8 *Bmp) -{ - u8 j = 0, k = 0, ActPage = 0; - - /* Draw graphic on master: 61 Column *4 Pages */ - while(j<244) - { - /* Draw on master page by page */ - LCD_SetMasterPage(ActPage); - for(k=0; k<61; k++) - { - LCD_SetMasterColumn(k); - LCD_SendMasterData(*Bmp++); - j++; - } - ActPage++; - } -} - -/******************************************************************************* -* Function Name : LCD_DrawSlaveGraphic -* Description : Draw a Graphic image on slave LCD. -* Input : - Bmp: the pointer of the dot matrix data. -* Output : None -* Return : None. -*******************************************************************************/ -void LCD_DrawSlaveGraphic(u8 *Bmp) -{ - u8 j = 0, k = 0, ActPage = 0; - - /* Draw graphic on slave: 61 Column *4 Pages */ - while(j<244) - { - /* Draw on slave page by page */ - LCD_SetSlavePage(ActPage); - for(k=0; k<61; k++) - { - LCD_SetSlaveColumn(k); - LCD_SendSlaveData(*Bmp++); - j++; - } - ActPage++; - } -} - -/******************************************************************************* -* Function Name : LCD_DrawGraphic -* Description : Draw a Graphic image on LCD. -* Input : - Bmp: the pointer of the dot matrix data. -* Output : None -* Return : None. -*******************************************************************************/ -void LCD_DrawGraphic(u8 *Bmp) -{ - u8 Pos = 0, ActPage = 0; - u16 j = 0, k = 0; - - /* Draw graphic on LCD: 122 Column *4 Pages */ - while(j<488) - { - if(!Pos) - { - /* Draw on master page by page */ - LCD_SetMasterPage(ActPage); - for(k=0; k<61; k++) - { - LCD_SetMasterColumn(k); - LCD_SendMasterData(*Bmp++); - j++; - } - Pos=1; - } - else - { - /* Draw on slave page by page */ - LCD_SetSlavePage(ActPage); - for(k=0; k<61; k++) - { - LCD_SetSlaveColumn(k); - LCD_SendSlaveData(*Bmp++); - j++; - } - ActPage++; - Pos=0; - } - } -} - -/******************************************************************************* -* Function Name : LCD_ScrollGraphic -* Description : Scroll a Graphic image on LCD. -* Input : - Bmp: the pointer of the dot matrix data. -* - nCount: specifies the delay time length. -* Output : None -* Return : None. -*******************************************************************************/ -void LCD_ScrollGraphic(u8 *Bmp, u32 nCount) -{ - u8 Pos = 0, ActPage = 0; - u16 j = 0, k = 0; - u32 Counter = 0; - - /* Draw graphic on LCD: 122 Column *4 Pages */ - while(j<488) - { - if(!Pos) - { - /* Draw on master page by page */ - LCD_SetMasterPage(ActPage); - for(k=0; k<61; k++) - { - LCD_SetMasterColumn(k); - LCD_SendMasterData(*Bmp++); - Counter = nCount; - /* Set a delay */ - for(; Counter != 0; Counter--); - j++; - } - Pos=1; - } - else - { - /* Draw on slave page by page */ - LCD_SetSlavePage(ActPage); - for(k=0; k<61; k++) - { - LCD_SetSlaveColumn(k); - Counter = nCount; - /* Set a delay */ - for(; Counter != 0; Counter--); - LCD_SendSlaveData(*Bmp++); - j++; - } - ActPage++; - Pos=0; - } - } -} - -/******************************************************************************* -* Function Name : LCD_DrawPixel -* Description : Draw a Graphic image on slave LCD. -* Input : - XPos: the dot line number of the pixel. -* - 1->61 : displayed on master LCD -* - 62->122: displayed on slave LCD -* - YPos: column address of the pixel from 1->32. -* - Mode: Dot_On: Pixel turned on (black). -* Dot_Off: Pixel turned off (black). -* Output : None -* Return : None. -*******************************************************************************/ -void LCD_DrawPixel(u8 XPos, u8 YPos, DotMode_TypeDef Mode) -{ - u8 Page = 0, Position = 0; - u16 Mask = 0; - u32 MasterDataIn = 0, MasterDataOut = 0, SlaveDataIn = 0, SlaveDataOut = 0; - - /* Pixel page */ - Page = (XPos-1)/8; - /* Pixel column */ - Position = (YPos-1)/61; /* 0:Master, 1:Slave */ - /* Mask for the pixel */ - Mask= 1<<((XPos-1)%8); - /* If Position=0 draw pixel on master LCD */ - if(!Position) - { - LCD_SetMasterPage(Page); - LCD_SetMasterColumn(YPos-1); - MasterDataIn = LCD_ReadMasterData(); - MasterDataIn = LCD_ReadMasterData(); - LCD_SetMasterColumn(YPos-1); - if(Mode==Dot_On) - { - MasterDataOut = MasterDataIn | Mask; - } - else - { - MasterDataOut = MasterDataIn & (~Mask); - } - LCD_SendMasterData(MasterDataOut); - } - /* If Position=1 draw pixel on slave LCD */ - else - { - LCD_SetSlavePage(Page); - LCD_SetSlaveColumn(YPos-62); - SlaveDataIn = LCD_ReadSlaveData(); - SlaveDataIn = LCD_ReadSlaveData(); - LCD_SetSlaveColumn(YPos-62); - if(Mode==Dot_On) - { - SlaveDataOut = SlaveDataIn | Mask; - } - else - { - SlaveDataOut = SlaveDataIn & (~Mask); - } - LCD_SendSlaveData(SlaveDataOut); - } -} - -/******************************************************************************* -* Function Name : LCD_DrawLine -* Description : Draw a line on master and slave LCDs. -* Input : - XPos1: the dot line number of the source point . -* - XPos2: the dot line number of the destination point . -* - YPos1: the dot column number of the source point. -* - YPos2: the dot column number of the destination point. -* Output : None -* Return : None. -*******************************************************************************/ -void LCD_DrawLine(u8 XPos1, u8 YPos1, u8 XPos2, u8 YPos2) -{ - u8 XPos = 0, YPos = 0; - - /* Use XPos1, YPos1, XPos2 and YPos2 */ - if((XPos2>=XPos1)&(YPos2>=YPos1)) - { - for(XPos=XPos1; XPos<=XPos2; XPos++) - { - for(YPos=YPos1; YPos<=YPos2; YPos++) - { - LCD_DrawPixel(XPos, YPos, Dot_On); - } - } - } - else if((XPos2=YPos1)) - { - for(XPos=XPos2; XPos<=XPos1; XPos++) - { - for(YPos=YPos1; YPos<=YPos2; YPos++) - { - LCD_DrawPixel(XPos, YPos, Dot_On); - } - } - } - else if((XPos2>=XPos1)&(YPos2FLASH - - - /* the program code is stored in the .text section, which goes to Flash */ - .text : - { - . = ALIGN(4); - - *(.text) /* remaining code */ - *(.rodata) /* read-only data (constants) */ - *(.rodata*) - *(.glue_7) - *(.glue_7t) - - . = ALIGN(4); - _etext = .; - /* This is used by the startup in order to initialize the .data secion */ - _sidata = _etext; - } >FLASH - - - - /* This is the initialized data section - The program executes knowing that the data is in the RAM - but the loader puts the initial values in the FLASH (inidata). - It is one task of the startup to copy the initial values from FLASH to RAM. */ - .data : AT ( _sidata ) - { - . = ALIGN(4); - /* This is used by the startup in order to initialize the .data secion */ - _sdata = . ; - - *(.data) - - . = ALIGN(4); - /* This is used by the startup in order to initialize the .data secion */ - _edata = . ; - } >RAM - - - - /* This is the uninitialized data section */ - .bss : - { - . = ALIGN(4); - /* This is used by the startup in order to initialize the .bss secion */ - _sbss = .; - - *(.bss) - *(COMMON) - - . = ALIGN(4); - /* This is used by the startup in order to initialize the .bss secion */ - _ebss = . ; - } >RAM - - PROVIDE ( end = _ebss ); - PROVIDE ( _end = _ebss ); - - /* This is the user stack section - This is just to check that there is enough RAM left for the User mode stack - It should generate an error if it's full. - */ - ._usrstack : - { - . = ALIGN(4); - _susrstack = . ; - - . = . + _Minimum_Stack_Size ; - - . = ALIGN(4); - _eusrstack = . ; - } >RAM - - - - /* this is the FLASH Bank1 */ - /* the C or assembly source must explicitly place the code or data there - using the "section" attribute */ - .b1text : - { - *(.b1text) /* remaining code */ - *(.b1rodata) /* read-only data (constants) */ - *(.b1rodata*) - } >FLASHB1 - - /* this is the EXTMEM */ - /* the C or assembly source must explicitly place the code or data there - using the "section" attribute */ - - /* EXTMEM Bank0 */ - .eb0text : - { - *(.eb0text) /* remaining code */ - *(.eb0rodata) /* read-only data (constants) */ - *(.eb0rodata*) - } >EXTMEMB0 - - /* EXTMEM Bank1 */ - .eb1text : - { - *(.eb1text) /* remaining code */ - *(.eb1rodata) /* read-only data (constants) */ - *(.eb1rodata*) - } >EXTMEMB1 - - /* EXTMEM Bank2 */ - .eb2text : - { - *(.eb2text) /* remaining code */ - *(.eb2rodata) /* read-only data (constants) */ - *(.eb2rodata*) - } >EXTMEMB2 - - /* EXTMEM Bank0 */ - .eb3text : - { - *(.eb3text) /* remaining code */ - *(.eb3rodata) /* read-only data (constants) */ - *(.eb3rodata*) - } >EXTMEMB3 - - - - /* after that it's only debugging information. */ - - /* remove the debugging information from the standard libraries */ - DISCARD : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - Symbols in the DWARF debugging sections are relative to the beginning - of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } -} - - - diff --git a/Demo/ARM7_STR75x_GCC/main.c b/Demo/ARM7_STR75x_GCC/main.c deleted file mode 100644 index 995430393..000000000 --- a/Demo/ARM7_STR75x_GCC/main.c +++ /dev/null @@ -1,318 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * Creates all the demo application tasks, then starts the scheduler. The WEB - * documentation provides more details of the demo application tasks. - * - * In addition to the standard demo tasks there are two tasks defined within - * this file: - * - * 1 - The check task - * The 'check' task is responsible for ensuring that all the standard demo - * tasks are executing as expected. It only executes every three seconds, but - * has the highest priority within the system so is guaranteed to get execution - * time. Any errors discovered by the check task are latched until the - * processor is reset. At the end of each cycle the check task sends either - * a pass or fail message to the 'print' task for display on the LCD. - * - * 2 - The print task - * The print task is the LCD 'gatekeeper'. That is, it is the only task that - * should access the LCD directly so is always guaranteed exclusive (and - * therefore consistent) access. The print task simply blocks on a queue - * to wait for messages from other tasks wishing to display text on the LCD. - * When a message arrives it displays its contents on the LCD then blocks to - * wait again. - */ - -/* ST includes. */ -#include "lcd.h" - -/* Kernel includes. */ -#include "FreeRTOS.h" -#include "Task.h" -#include "Queue.h" - -/* Demo application includes. */ -#include "ParTest.h" -#include "flash.h" -#include "integer.h" -#include "blocktim.h" -#include "BlockQ.h" -#include "comtest2.h" -#include "dynamic.h" - -/* Demo application task priorities. */ -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) - -/* How often should we check the other tasks? */ -#define mainCHECK_TASK_CYCLE_TIME ( 3000 ) - -/* The maximum offset into the pass and fail strings sent to the LCD. An -offset is used a simple method of using a different column each time a message -is written to the LCD. */ -#define mainMAX_WRITE_COLUMN ( 14 ) - -/* Baud rate used by the comtest tasks. */ -#define mainCOM_TEST_BAUD_RATE ( 19200 ) - -/* The LED used by the comtest tasks. See the comtest.c file for more -information. */ -#define mainCOM_TEST_LED ( 3 ) - -/* The number of messages that can be queued for display on the LCD at any one -time. */ -#define mainLCD_QUEUE_LENGTH ( 2 ) - -/* The time to wait when sending to mainLCD_QUEUE_LENGTH. */ -#define mainNO_DELAY ( 0 ) - -/*-----------------------------------------------------------*/ - -/* The type that is posted to the LCD queue. */ -typedef struct LCD_MESSAGE -{ - unsigned portCHAR *pucString; /* Points to the string to be displayed. */ - unsigned portCHAR ucLine; /* The line of the LCD that should be used. */ -} LCDMessage; - -/*-----------------------------------------------------------*/ - -/* - * The task that executes at the highest priority and checks the operation of - * all the other tasks in the system. See the description at the top of the - * file. - */ -static void vCheckTask( void *pvParameters ); - -/* - * ST provided routine to configure the processor. - */ -static void prvSetupHardware(void); - -/* - * The only task that should access the LCD. Other tasks wanting to write - * to the LCD should send a message of type LCDMessage containing the - * information to display to the print task. The print task simply blocks - * waiting for the arrival of such messages, displays the message, then blocks - * again. - */ -static void vPrintTask( void *pvParameters ); - -/*-----------------------------------------------------------*/ - -/* The queue used to communicate with the LCD print task. */ -static xQueueHandle xLCDQueue; - -/*-----------------------------------------------------------*/ - -/* Create all the demo application tasks, then start the scheduler. */ -int main( void ) -{ - /* Perform any hardware setup necessary. */ - prvSetupHardware(); - vParTestInitialise(); - - /* Create the queue used to communicate with the LCD print task. */ - xLCDQueue = xQueueCreate( mainLCD_QUEUE_LENGTH, sizeof( LCDMessage ) ); - - /* Create the standard demo application tasks. See the WEB documentation - for more information on these tasks. */ - vCreateBlockTimeTasks(); - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); - vStartDynamicPriorityTasks(); - vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - - /* Create the tasks defined within this file. */ - xTaskCreate( vPrintTask, ( signed portCHAR * ) "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL ); - xTaskCreate( vCheckTask, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - - vTaskStartScheduler(); - - /* Execution will only reach here if there was insufficient heap to - start the scheduler. */ - return 0; -} -/*-----------------------------------------------------------*/ - -static void vCheckTask( void *pvParameters ) -{ -static unsigned portLONG ulErrorDetected = pdFALSE; -portTickType xLastExecutionTime; -unsigned portCHAR *ucErrorMessage = ( unsigned portCHAR * )" FAIL"; -unsigned portCHAR *ucSuccessMessage = ( unsigned portCHAR * )" PASS"; -unsigned portBASE_TYPE uxColumn = mainMAX_WRITE_COLUMN; -LCDMessage xMessage; - - /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() - works correctly. */ - xLastExecutionTime = xTaskGetTickCount(); - - for( ;; ) - { - /* Wait until it is time for the next cycle. */ - vTaskDelayUntil( &xLastExecutionTime, mainCHECK_TASK_CYCLE_TIME ); - - /* Has an error been found in any of the standard demo tasks? */ - - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - ulErrorDetected = pdTRUE; - } - - if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) - { - ulErrorDetected = pdTRUE; - } - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - ulErrorDetected = pdTRUE; - } - - if( xAreComTestTasksStillRunning() != pdTRUE ) - { - ulErrorDetected = pdTRUE; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - ulErrorDetected = pdTRUE; - } - - /* Calculate the LCD line on which we would like the message to - be displayed. The column variable is used for convenience as - it is incremented each cycle anyway. */ - xMessage.ucLine = ( unsigned portCHAR ) ( uxColumn & 0x01 ); - - /* The message displayed depends on whether an error was found or - not. Any discovered error is latched. Here the column variable - is used as an index into the text string as a simple way of moving - the text from column to column. */ - if( ulErrorDetected == pdFALSE ) - { - xMessage.pucString = ucSuccessMessage + uxColumn; - } - else - { - xMessage.pucString = ucErrorMessage + uxColumn; - } - - /* Send the message to the print task for display. */ - xQueueSend( xLCDQueue, ( void * ) &xMessage, mainNO_DELAY ); - - /* Make sure the message is printed in a different column the next - time around. */ - uxColumn--; - if( uxColumn == 0 ) - { - uxColumn = mainMAX_WRITE_COLUMN; - } - } -} - -/*-----------------------------------------------------------*/ - -static void vPrintTask( void *pvParameters ) -{ -LCDMessage xMessage; - - for( ;; ) - { - /* Wait until a message arrives. */ - while( xQueueReceive( xLCDQueue, ( void * ) &xMessage, portMAX_DELAY ) != pdPASS ); - - /* The message contains the text to display, and the line on which the - text should be displayed. */ - LCD_Clear(); - LCD_DisplayString( xMessage.ucLine, xMessage.pucString, BlackText ); - } -} -/*-----------------------------------------------------------*/ - -static void prvSetupHardware(void) -{ -ErrorStatus OSC4MStartUpStatus01; - - /* ST provided routine. */ - - /* MRCC system reset */ - MRCC_DeInit(); - - /* Wait for OSC4M start-up */ - OSC4MStartUpStatus01 = MRCC_WaitForOSC4MStartUp(); - - if(OSC4MStartUpStatus01 == SUCCESS) - { - /* Set HCLK to 60MHz */ - MRCC_HCLKConfig(MRCC_CKSYS_Div1); - - /* Set CKTIM to 60MHz */ - MRCC_CKTIMConfig(MRCC_HCLK_Div1); - - /* Set PCLK to 30MHz */ - MRCC_PCLKConfig(MRCC_CKTIM_Div2); - - /* Enable Flash Burst mode */ - CFG_FLASHBurstConfig(CFG_FLASHBurst_Enable); - - /* Set CK_SYS to 60 MHz */ - MRCC_CKSYSConfig(MRCC_CKSYS_OSC4MPLL, MRCC_PLL_Mul_15); - } - - /* GPIO pins optimized for 3V3 operation */ - MRCC_IOVoltageRangeConfig(MRCC_IOVoltageRange_3V3); - - /* GPIO clock source enable */ - MRCC_PeripheralClockConfig(MRCC_Peripheral_GPIO, ENABLE); - - /* EXTIT clock source enable */ - MRCC_PeripheralClockConfig(MRCC_Peripheral_EXTIT, ENABLE); - /* TB clock source enable */ - MRCC_PeripheralClockConfig(MRCC_Peripheral_TB, ENABLE); - - /* Initialize the demonstration menu */ - LCD_Init(); - - LCD_DisplayString(Line1, ( unsigned portCHAR * ) "www.FreeRTOS.org", BlackText); - LCD_DisplayString(Line2, ( unsigned portCHAR * ) " STR750 Demo ", BlackText); - - EIC_IRQCmd(ENABLE); -} -/*-----------------------------------------------------------*/ - diff --git a/Demo/ARM7_STR75x_GCC/rtosdemo.prj b/Demo/ARM7_STR75x_GCC/rtosdemo.prj deleted file mode 100644 index 88882784f..000000000 --- a/Demo/ARM7_STR75x_GCC/rtosdemo.prj +++ /dev/null @@ -1,1594 +0,0 @@ -RIDE Project File -File Version=3 -[BN] -Build=BN746-ST7-ARM-80C51-P1-STR750 -[Ref] -Ref=11 -[Type] -Type=0 -[Environment] -Begin Group CompEdit -EditCodeCoverage=0 -TestMakeDate=1 -Promptrebuild=0 -DebugMessage=1000 -Promptdirtyoptions=0 -Prompttoreloadfiles=0 -Promptsucsorfail=0 -Promptenddebug=1 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-[Dim Views] -Nb Dim Views=13 -0 (0,0-0,0) -1 (0,0-0,0) -2 (0,0-0,0) -3 (0,0-0,0) -4 (76,125-823,634) -5 (553,156-783,399) -6 (220,230-941,725) -7 (0,0-0,0) -8 (0,0-0,0) -9 (0,0-0,0) -10 (0,0-0,0) -11 (0,0-0,0) -12 (0,0-0,0) - -[DebugTool] -Debug= - -[Project Rect] -(0,0-0,0) - -[LastSel] -LastAOF=c:\e\dev\freertos\demo\arm7_str75x_gcc\rtosdemo.elf - diff --git a/Demo/ARM7_STR75x_GCC/serial/serial.c b/Demo/ARM7_STR75x_GCC/serial/serial.c deleted file mode 100644 index 9c74e1050..000000000 --- a/Demo/ARM7_STR75x_GCC/serial/serial.c +++ /dev/null @@ -1,235 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0. -*/ - - -/*----------------------------------------------------------- - * Components that can be compiled to either ARM or THUMB mode are - * contained in this file.c The ISR routines, which can only be compiled - * to ARM mode, are contained in serialISR.c. - *----------------------------------------------------------*/ - - - -/* Library includes. */ -#include "75x_uart.h" -#include "75x_gpio.h" -#include "75x_eic.h" -#include "75x_mrcc.h" - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "queue.h" - -/* Demo application includes. */ -#include "serial.h" - -#define serINVALID_QUEUE ( ( xQueueHandle ) 0 ) -#define serNO_BLOCK ( ( portTickType ) 0 ) - -/*-----------------------------------------------------------*/ - -/* Queues used to hold received characters, and characters waiting to be -transmitted. */ -static xQueueHandle xRxedChars; -static xQueueHandle xCharsForTx; - -static volatile portBASE_TYPE xQueueEmpty = pdTRUE; - -/*-----------------------------------------------------------*/ - -/* The interrupt service routine - called from the assembly entry point. */ -void vSerialISR( void ); -void vConfigureQueues( xQueueHandle xQForRx, xQueueHandle xQForTx, volatile portBASE_TYPE *pxEmptyFlag ); - -/*-----------------------------------------------------------*/ - -/* - * See the serial2.h header file. - */ -xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) -{ -xComPortHandle xReturn; -UART_InitTypeDef UART_InitStructure; -GPIO_InitTypeDef GPIO_InitStructure; -EIC_IRQInitTypeDef EIC_IRQInitStructure; - - /* Create the queues used to hold Rx and Tx characters. */ - xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); - xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); - - /* If the queues were created correctly then setup the serial port - hardware. */ - if( ( xRxedChars != serINVALID_QUEUE ) && ( xCharsForTx != serINVALID_QUEUE ) ) - { - - vConfigureQueues( xRxedChars, xCharsForTx, &xQueueEmpty ); - - portENTER_CRITICAL(); - { - /* Enable the UART0 Clock. */ - MRCC_PeripheralClockConfig( MRCC_Peripheral_UART0, ENABLE ); - - /* Configure the UART0_Tx as alternate function */ - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11; - GPIO_Init(GPIO0, &GPIO_InitStructure); - - /* Configure the UART0_Rx as input floating */ - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; - GPIO_Init(GPIO0, &GPIO_InitStructure); - - /* Configure UART0. */ - UART_InitStructure.UART_WordLength = UART_WordLength_8D; - UART_InitStructure.UART_StopBits = UART_StopBits_1; - UART_InitStructure.UART_Parity = UART_Parity_No; - UART_InitStructure.UART_BaudRate = ulWantedBaud; - UART_InitStructure.UART_HardwareFlowControl = UART_HardwareFlowControl_None; - UART_InitStructure.UART_Mode = UART_Mode_Tx_Rx; - UART_InitStructure.UART_TxFIFOLevel = UART_FIFOLevel_1_2; /* FIFO size 16 bytes, FIFO level 8 bytes */ - UART_InitStructure.UART_RxFIFOLevel = UART_FIFOLevel_1_2; /* FIFO size 16 bytes, FIFO level 8 bytes */ - UART_Init(UART0, &UART_InitStructure); - - /* Enable the UART0 */ - UART_Cmd(UART0, ENABLE); - - /* Configure the IEC for the UART interrupts. */ - EIC_IRQInitStructure.EIC_IRQChannelCmd = ENABLE; - EIC_IRQInitStructure.EIC_IRQChannel = UART0_IRQChannel; - EIC_IRQInitStructure.EIC_IRQChannelPriority = 1; - EIC_IRQInit(&EIC_IRQInitStructure); - - xQueueEmpty = pdTRUE; - UART_ITConfig( UART0, UART_IT_Transmit | UART_IT_Receive, ENABLE ); - } - portEXIT_CRITICAL(); - } - else - { - xReturn = ( xComPortHandle ) 0; - } - - /* This demo file only supports a single port but we have to return - something to comply with the standard demo header file. */ - return xReturn; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) -{ - /* The port handle is not required as this driver only supports one port. */ - ( void ) pxPort; - - /* Get the next character from the buffer. Return false if no characters - are available, or arrive before xBlockTime expires. */ - if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) - { - return pdTRUE; - } - else - { - return pdFALSE; - } -} -/*-----------------------------------------------------------*/ - -void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength ) -{ -signed portCHAR *pxNext; - - /* A couple of parameters that this port does not use. */ - ( void ) usStringLength; - ( void ) pxPort; - - /* NOTE: This implementation does not handle the queue being full as no - block time is used! */ - - /* The port handle is not required as this driver only supports UART0. */ - ( void ) pxPort; - - /* Send each character in the string, one at a time. */ - pxNext = ( signed portCHAR * ) pcString; - while( *pxNext ) - { - xSerialPutChar( pxPort, *pxNext, serNO_BLOCK ); - pxNext++; - } -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) -{ -portBASE_TYPE xReturn; - - /* Place the character in the queue of characters to be transmitted. */ - portENTER_CRITICAL(); - { - if( xQueueEmpty == pdTRUE ) - { - UART0->DR = cOutChar; - xReturn = pdPASS; - } - else - { - if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) - { - xReturn = pdFAIL; - } - else - { - xReturn = pdPASS; - } - } - - xQueueEmpty = pdFALSE; - } - portEXIT_CRITICAL(); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -void vSerialClose( xComPortHandle xPort ) -{ - /* Not supported as not required by the demo application. */ -} -/*-----------------------------------------------------------*/ - - - - - - diff --git a/Demo/ARM7_STR75x_GCC/serial/serialISR.c b/Demo/ARM7_STR75x_GCC/serial/serialISR.c deleted file mode 100644 index 53aba6c28..000000000 --- a/Demo/ARM7_STR75x_GCC/serial/serialISR.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/*----------------------------------------------------------- - * Components that can be compiled to either ARM or THUMB mode are - * contained in serial.c The ISR routines, which can only be compiled - * to ARM mode, are contained in this file. - *----------------------------------------------------------*/ - - - -/* Library includes. */ -#include "75x_uart.h" - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "queue.h" - -static xQueueHandle xRxedChars; -static xQueueHandle xCharsForTx; -static portBASE_TYPE volatile *pxQueueEmpty; - -void vConfigureQueues( xQueueHandle xQForRx, xQueueHandle xQForTx, portBASE_TYPE volatile *pxEmptyFlag ) -{ - xRxedChars = xQForRx; - xCharsForTx = xQForTx; - pxQueueEmpty = pxEmptyFlag; -} -/*-----------------------------------------------------------*/ - -void vSerialISR( void ) -{ -signed portCHAR cChar; -portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByPost = pdFALSE; - - do - { - if( UART0->MIS & UART_IT_Transmit ) - { - /* The interrupt was caused by the THR becoming empty. Are there any - more characters to transmit? */ - if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE ) - { - /* A character was retrieved from the queue so can be sent to the - THR now. */ - UART0->DR = cChar; - } - else - { - *pxQueueEmpty = pdTRUE; - } - - UART_ClearITPendingBit( UART0, UART_IT_Transmit ); - } - - if( UART0->MIS & UART_IT_Receive ) - { - /* The interrupt was caused by a character being received. Grab the - character from the RHR and place it in the queue of received - characters. */ - cChar = UART0->DR; - xTaskWokenByPost = xQueueSendFromISR( xRxedChars, &cChar, xTaskWokenByPost ); - UART_ClearITPendingBit( UART0, UART_IT_Receive ); - } - } while( UART0->MIS ); - - /* If a task was woken by either a character being received or a character - being transmitted then we may need to switch to another task. */ - portEND_SWITCHING_ISR( ( xTaskWokenByPost || xTaskWokenByTx ) ); -} - - diff --git a/Demo/ARM7_STR75x_IAR/75x_init.s b/Demo/ARM7_STR75x_IAR/75x_init.s deleted file mode 100644 index a4b018b67..000000000 --- a/Demo/ARM7_STR75x_IAR/75x_init.s +++ /dev/null @@ -1,249 +0,0 @@ -;******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -;* File Name : 75x_init.s -;* Author : MCD Application Team -;* Date First Issued : 03/10/2006 -;* Description : This module performs: -;* - Memory remapping (if required), -;* - Stack pointer initialisation for each mode , -;* - Interrupt Controller Initialisation -;* - Branches to ?main in the C library (which eventually -;* calls main()). -;* On reset, the ARM core starts up in Supervisor (SVC) mode, -;* in ARM state,with IRQ and FIQ disabled. -;******************************************************************************* -; History: -; 07/17/2006 : V1.0 -; 03/10/2006 : V0.1 -;******************************************************************************* -; THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -; CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -;******************************************************************************* - - IMPORT WAKUP_Addr ; imported from 75x_vect.s - - - - - ; Depending on Your Application, Disable or Enable the following Defines - ; ---------------------------------------------------------------------------- - ; SMI Bank0 configuration - ; ---------------------------------------------------------------------------- - ; If you need to accees the SMI Bank0 - ; uncomment next line - ;#define SMI_Bank0_EN - - ; ---------------------------------------------------------------------------- - ; Memory remapping - ; ---------------------------------------------------------------------------- - ;#define Remap_SRAM ; remap SRAM at address 0x00 - - ; ---------------------------------------------------------------------------- - ; EIC initialization - ; ---------------------------------------------------------------------------- - #define EIC_INIT ; Configure and Initialize EIC - -; Standard definitions of mode bits and interrupt (I & F) flags in PSRs -Mode_USR EQU 0x10 -Mode_FIQ EQU 0x11 -Mode_IRQ EQU 0x12 -Mode_SVC EQU 0x13 -Mode_ABT EQU 0x17 -Mode_UND EQU 0x1B -Mode_SYS EQU 0x1F - -I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled -F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled - - -; MRCC Register -MRCC_PCLKEN_Addr EQU 0x60000030 ; Peripheral Clock Enable register base address - -; CFG Register -CFG_GLCONF_Addr EQU 0x60000010 ; Global Configuration register base address -SRAM_mask EQU 0x0002 ; to remap RAM at 0x0 - -; GPIO Register -GPIOREMAP0R_Addr EQU 0xFFFFE420 -SMI_EN_Mask EQU 0x00000001 - -; SMI Register -SMI_CR1_Addr EQU 0x90000000 - -; EIC Registers offsets -EIC_Base_addr EQU 0xFFFFF800 ; EIC base address -ICR_off_addr EQU 0x00 ; Interrupt Control register offset -CIPR_off_addr EQU 0x08 ; Current Interrupt Priority Register offset -IVR_off_addr EQU 0x18 ; Interrupt Vector Register offset -FIR_off_addr EQU 0x1C ; Fast Interrupt Register offset -IER_off_addr EQU 0x20 ; Interrupt Enable Register offset -IPR_off_addr EQU 0x40 ; Interrupt Pending Bit Register offset -SIR0_off_addr EQU 0x60 ; Source Interrupt Register 0 - - -;--------------------------------------------------------------- -; ?program_start -;--------------------------------------------------------------- - MODULE ?program_start - RSEG IRQ_STACK:DATA(2) - RSEG FIQ_STACK:DATA(2) - RSEG UND_STACK:DATA(2) - RSEG ABT_STACK:DATA(2) - RSEG SVC_STACK:DATA(2) - RSEG CSTACK:DATA(2) - RSEG ICODE:CODE(2) - PUBLIC __program_start - EXTERN ?main - CODE32 - - -__program_start: - LDR pc, =NextInst - -NextInst -; Reset all Peripheral Clocks -; This is usefull only when using debugger to Reset\Run the application - - #ifdef SMI_Bank0_EN - LDR r0, =0x01000000 ; Disable peripherals clock (except GPIO) - #else - LDR r0, =0x00000000 ; Disable peripherals clock - #endif - LDR r1, =MRCC_PCLKEN_Addr - STR r0, [r1] - - #ifdef SMI_Bank0_EN - LDR r0, =0x1875623F ; Peripherals kept under reset (except GPIO) - #else - LDR r0, =0x1975623F ; Peripherals kept under reset - #endif - - STR r0, [r1,#4] - MOV r0, #0 - NOP ; Wait - NOP - NOP - NOP - STR r0, [r1,#4] ; Disable peripherals reset - -; Initialize stack pointer registers -; Enter each mode in turn and set up the stack pointer - - - MSR CPSR_c, #Mode_FIQ|I_Bit|F_Bit ; No interrupts - ldr sp,=SFE(FIQ_STACK) & 0xFFFFFFF8 ; End of FIQ_STACK - - MSR CPSR_c, #Mode_IRQ|I_Bit|F_Bit ; No interrupts - ldr sp,=SFE(IRQ_STACK) & 0xFFFFFFF8 ; End of IRQ_STACK - - MSR CPSR_c, #Mode_ABT|I_Bit|F_Bit ; No interrupts - ldr sp,=SFE(ABT_STACK) & 0xFFFFFFF8 ; End of ABT_STACK - - MSR CPSR_c, #Mode_UND|I_Bit|F_Bit ; No interrupts - ldr sp,=SFE(UND_STACK) & 0xFFFFFFF8 ; End of UND_STACK - - MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit ; No interrupts - ldr sp,=SFE(SVC_STACK) & 0xFFFFFFF8 ; End of SVC_STACK - -; ------------------------------------------------------------------------------ -; Description : Enable SMI Bank0: enable GPIOs clock in MRCC_PCLKEN register, -; enable SMI alternate function in GPIO_REMAP register and enable -; Bank0 in SMI_CR1 register. -; ------------------------------------------------------------------------------ - #ifdef SMI_Bank0_EN - MOV r0, #0x01000000 - LDR r1, =MRCC_PCLKEN_Addr - STR r0, [r1] ; Enable GPIOs clock - - LDR r1, =GPIOREMAP0R_Addr - MOV r0, #SMI_EN_Mask - LDR r2, [r1] - ORR r2, r2, r0 - STR r2, [r1] ; Enable SMI alternate function - - LDR r0, =0x251 ; SMI Bank0 enabled, Prescaler = 2, Deselect Time = 5 - LDR r1, =SMI_CR1_Addr - STR r0, [r1] ; Configure CR1 register - LDR r0, =0x00 - STR r0, [r1,#4] ; Reset CR2 register - #endif - -; ------------------------------------------------------------------------------ -; Description : Remapping SRAM at address 0x00 after the application has -; started executing. -; ------------------------------------------------------------------------------ - #ifdef Remap_SRAM - MOV r0, #SRAM_mask - LDR r1, =CFG_GLCONF_Addr - LDR r2, [r1] ; Read GLCONF Register - BIC r2, r2, #0x03 ; Reset the SW_BOOT bits - ORR r2, r2, r0 ; Change the SW_BOOT bits - STR r2, [r1] ; Write GLCONF Register - #endif - -;------------------------------------------------------------------------------- -;Description : Initialize the EIC as following : -; - IRQ disabled -; - FIQ disabled -; - IVR contains the load PC opcode -; - All channels are disabled -; - All channels priority equal to 0 -; - All SIR registers contains offset to the related IRQ table entry -;------------------------------------------------------------------------------- - #ifdef EIC_INIT - LDR r3, =EIC_Base_addr - LDR r4, =0x00000000 - STR r4, [r3, #ICR_off_addr] ; Disable FIQ and IRQ - STR r4, [r3, #IER_off_addr] ; Disable all interrupts channels - - LDR r4, =0xFFFFFFFF - STR r4, [r3, #IPR_off_addr] ; Clear all IRQ pending bits - - LDR r4, =0x18 - STR r4, [r3, #FIR_off_addr] ; Disable FIQ channels and clear FIQ pending bits - - LDR r4, =0x00000000 - STR r4, [r3, #CIPR_off_addr] ; Reset the current priority register - - LDR r4, =0xE59F0000 ; Write the LDR pc,pc,#offset.. - STR r4, [r3, #IVR_off_addr] ; ..instruction code in IVR[31:16] - - - LDR r2,= 32 ; 32 Channel to initialize - LDR r0, =WAKUP_Addr ; Read the address of the IRQs address table - LDR r1, =0x00000FFF - AND r0,r0,r1 - LDR r5,=SIR0_off_addr ; Read SIR0 address - SUB r4,r0,#8 ; subtract 8 for prefetch - LDR r1, =0xF7E8 ; add the offset to the 0x00 address.. - ; ..(IVR address + 7E8 = 0x00) - ; 0xF7E8 used to complete the LDR pc,offset opcode - ADD r1,r4,r1 ; compute the jump offset -EIC_INI - MOV r4, r1, LSL #16 ; Left shift the result - STR r4, [r3, r5] ; Store the result in SIRx register - ADD r1, r1, #4 ; Next IRQ address - ADD r5, r5, #4 ; Next SIR - SUBS r2, r2, #1 ; Decrement the number of SIR registers to initialize - BNE EIC_INI ; If more then continue - - #endif - - -; --- Branch to C Library entry point - - IMPORT ?main - - B ?main ; use B not BL, because an application will never return this way - - - - - LTORG - - - END -;******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE***** diff --git a/Demo/ARM7_STR75x_IAR/75x_vect.s b/Demo/ARM7_STR75x_IAR/75x_vect.s deleted file mode 100644 index 991bda794..000000000 --- a/Demo/ARM7_STR75x_IAR/75x_vect.s +++ /dev/null @@ -1,882 +0,0 @@ -;******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -;* File Name : 75x_vect.c -;* Author : MCD Application Team -;* Date First Issued : 03/10/2006 -;* Description : This file used to initialize the exception and IRQ -;* vectors, and to enter/return to/from exceptions handlers. -;******************************************************************************* -; History: -; 07/17/2006 : V1.0 -; 03/10/2006 : V0.1 -;******************************************************************************* -;* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -;* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -;******************************************************************************* - -#include "FreeRTOSConfig.h" -#include "ISR_Support.h" - - - PROGRAM ?RESET - COMMON INTVEC:CODE(2) - CODE32 - -EIC_base_addr EQU 0xFFFFF800 ; EIC base address -CICR_off_addr EQU 0x04 ; Current Interrupt Channel Register -IVR_off_addr EQU 0x18 ; Interrupt Vector Register -IPR_off_addr EQU 0x40 ; Interrupt Pending Register - - -;******************************************************************************* -; Import the __program_start address from 75x_init.s -;******************************************************************************* - - IMPORT __program_start - - - -;******************************************************************************* -; Import exception handlers -;******************************************************************************* - - IMPORT Undefined_Handler - IMPORT SWI_Handler - IMPORT Prefetch_Handler - IMPORT Abort_Handler - IMPORT FIQ_Handler - -;******************************************************************************* -; Import IRQ handlers from 75x_it.c -;******************************************************************************* - - IMPORT WAKUP_IRQHandler - IMPORT TIM2_OC2_IRQHandler - IMPORT TIM2_OC1_IRQHandler - IMPORT TIM2_IC12_IRQHandler - IMPORT TIM2_UP_IRQHandler - IMPORT TIM1_OC2_IRQHandler - IMPORT TIM1_OC1_IRQHandler - IMPORT TIM1_IC12_IRQHandler - IMPORT TIM1_UP_IRQHandler - IMPORT TIM0_OC2_IRQHandler - IMPORT TIM0_OC1_IRQHandler - IMPORT TIM0_IC12_IRQHandler - IMPORT TIM0_UP_IRQHandler - IMPORT PWM_OC123_IRQHandler - IMPORT PWM_EM_IRQHandler - IMPORT PWM_UP_IRQHandler - IMPORT I2C_IRQHandler - IMPORT SSP1_IRQHandler - IMPORT SSP0_IRQHandler - IMPORT UART2_IRQHandler - IMPORT UART1_IRQHandler - IMPORT vSerialISR - IMPORT CAN_IRQHandler - IMPORT USB_LP_IRQHandler - IMPORT USB_HP_IRQHandler - IMPORT ADC_IRQHandler - IMPORT DMA_IRQHandler - IMPORT EXTIT_IRQHandler - IMPORT MRCC_IRQHandler - IMPORT FLASHSMI_IRQHandler - IMPORT RTC_IRQHandler - IMPORT TB_IRQHandler - IMPORT vPortPreemptiveTick - IMPORT vPortYieldProcessor - IMPORT UART0_IRQHandler - -;******************************************************************************* -; Export Peripherals IRQ handlers table address -;******************************************************************************* - - EXPORT WAKUP_Addr - -;******************************************************************************* -; Exception vectors -;******************************************************************************* - - - LDR PC, Reset_Addr - LDR PC, Undefined_Addr - LDR PC, SWI_Addr - LDR PC, Prefetch_Addr - LDR PC, Abort_Addr - NOP ; Reserved vector - LDR PC, IRQ_Addr - LDR PC, FIQ_Addr - -;******************************************************************************* -; Exception handlers address table -;******************************************************************************* - -Reset_Addr DCD __program_start -Undefined_Addr DCD UndefinedHandler -SWI_Addr DCD vPortYieldProcessor -Prefetch_Addr DCD PrefetchAbortHandler -Abort_Addr DCD DataAbortHandler - DCD 0 ; Reserved vector -IRQ_Addr DCD IRQHandler -FIQ_Addr DCD FIQHandler - -;******************************************************************************* -; Peripherals IRQ handlers address table -;******************************************************************************* - -WAKUP_Addr DCD WAKUPIRQHandler -TIM2_OC2_Addr DCD TIM2_OC2IRQHandler -TIM2_OC1_Addr DCD TIM2_OC1IRQHandler -TIM2_IC12_Addr DCD TIM2_IC12IRQHandler -TIM2_UP_Addr DCD TIM2_UPIRQHandler -TIM1_OC2_Addr DCD TIM1_OC2IRQHandler -TIM1_OC1_Addr DCD TIM1_OC1IRQHandler -TIM1_IC12_Addr DCD TIM1_IC12IRQHandler -TIM1_UP_Addr DCD TIM1_UPIRQHandler -TIM0_OC2_Addr DCD TIM0_OC2IRQHandler -TIM0_OC1_Addr DCD TIM0_OC1IRQHandler -TIM0_IC12_Addr DCD TIM0_IC12IRQHandler -TIM0_UP_Addr DCD TIM0_UPIRQHandler -PWM_OC123_Addr DCD PWM_OC123IRQHandler -PWM_EM_Addr DCD PWM_EMIRQHandler -PWM_UP_Addr DCD PWM_UPIRQHandler -I2C_Addr DCD I2CIRQHandler -SSP1_Addr DCD SSP1IRQHandler -SSP0_Addr DCD SSP0IRQHandler -UART2_Addr DCD UART2IRQHandler -UART1_Addr DCD UART1IRQHandler -UART0_Addr DCD vSerialISR -CAN_Addr DCD CANIRQHandler -USB_LP_Addr DCD USB_LPIRQHandler -USB_HP_Addr DCD USB_HPIRQHandler -ADC_Addr DCD ADCIRQHandler -DMA_Addr DCD DMAIRQHandler -EXTIT_Addr DCD EXTITIRQHandler -MRCC_Addr DCD MRCCIRQHandler -FLASHSMI_Addr DCD FLASHSMIIRQHandler -RTC_Addr DCD RTCIRQHandler -TB_Addr DCD vPortPreemptiveTick - -;******************************************************************************* -; Exception Handlers -;******************************************************************************* - -;******************************************************************************* -;* Macro Name : SaveContext -;* Description : This macro used to save the context before entering -;* an exception handler. -;* Input : The range of registers to store. -;* Output : none -;******************************************************************************* -SaveContext MACRO reg1,reg2 - STMFD sp!,{reg1-reg2,lr} ; Save The workspace plus the current return - ; address lr_ mode into the stack. - MRS r1,spsr ; Save the spsr_mode into r1. - STMFD sp!,{r1} ; Save spsr. - ENDM - -;******************************************************************************* -;* Macro Name : RestoreContext -;* Description : This macro used to restore the context to return from -;* an exception handler and continue the program execution. -;* Input : The range of registers to restore. -;* Output : none -;******************************************************************************* -RestoreContext MACRO reg1,reg2 - LDMFD sp!,{r1} ; Restore the saved spsr_mode into r1. - MSR spsr_cxsf,r1 ; Restore spsr_mode. - LDMFD sp!,{reg1-reg2,pc}^; Return to the instruction following... - ; ...the exception interrupt. - ENDM - -;******************************************************************************* -;* Function Name : UndefinedHandler -;* Description : This function called when undefined instruction exception -;* is entered. -;* Input : none -;* Output : none -;******************************************************************************* -UndefinedHandler - SaveContext r0,r12 ; Save the workspace plus the current - ; return address lr_ und and spsr_und. - ldr r0,=Undefined_Handler - ldr lr,=Undefined_Handler_end - bx r0 ;Branch to Undefined_Handler -Undefined_Handler_end: - RestoreContext r0,r12 ; Return to the instruction following... - ; ...the undefined instruction. - -;******************************************************************************* -;* Function Name : SWIHandler -;* Description : This function called when SWI instruction executed. -;* Input : none -;* Output : none -;******************************************************************************* -SWIHandler - SaveContext r0,r12 ; Save the workspace plus the current - ; return address lr_ svc and spsr_svc. - ldr r0,= SWI_Handler - ldr lr,= SWI_Handler_end - bx r0 ;Branch to SWI_Handler -SWI_Handler_end: - RestoreContext r0,r12 ; Return to the instruction following... - ; ...the SWI instruction. - -;******************************************************************************* -;* Function Name : IRQHandler -;* Description : This function called when IRQ exception is entered. -;* Input : none -;* Output : none -;******************************************************************************* -IRQHandler - portSAVE_CONTEXT ; Save the context of the current task. - - LDR r0, =EIC_base_addr - LDR r1, =IVR_off_addr - LDR lr, =ReturnAddress ; Load the return address. - ADD pc,r0,r1 ; Branch to the IRQ handler. -ReturnAddress - LDR r0, =EIC_base_addr - LDR r2, [r0, #CICR_off_addr] ; Get the IRQ channel number - MOV r3,#1 - MOV r3,r3,LSL r2 - STR r3,[r0, #IPR_off_addr] ; Clear the corresponding IPR bit. - - portRESTORE_CONTEXT ; Restore the context of the selected task. - - -;******************************************************************************* -;* Function Name : PrefetchAbortHandler -;* Description : This function called when Prefetch Abort exception is entered. -;* Input : none -;* Output : none -;******************************************************************************* -PrefetchAbortHandler - SUB lr,lr,#4 ; Update the link register. - SaveContext r0,r7 ; Save the workspace plus the current - ; return address lr_abt and spsr_abt. - ldr r0,= Prefetch_Handler - ldr lr,= Prefetch_Handler_end - bx r0 ;Branch to Prefetch_Handler -Prefetch_Handler_end: - RestoreContext r0,r7 ; Return to the instruction following that... - ; ...has generated the prefetch abort exception. - -;******************************************************************************* -;* Function Name : DataAbortHandler -;* Description : This function is called when Data Abort exception is entered. -;* Input : none -;* Output : none -;******************************************************************************* -DataAbortHandler - SUB lr,lr,#8 ; Update the link register. - SaveContext r0,r12 ; Save the workspace plus the current - ; return address lr_ abt and spsr_abt. - ldr r0,= Abort_Handler - ldr lr,= Abort_Handler_end - bx r0 ;Branch to Abort_Handler -Abort_Handler_end: - RestoreContext r0,r12 ; Return to the instruction following that... - ; ...has generated the data abort exception. - -;******************************************************************************* -;* Function Name : FIQHandler -;* Description : This function is called when FIQ exception is entered. -;* Input : none -;* Output : none -;******************************************************************************* -FIQHandler - SUB lr,lr,#4 ; Update the link register. - SaveContext r0,r7 ; Save the workspace plus the current - ; return address lr_ fiq and spsr_fiq. - ldr r0,= FIQ_Handler - ldr lr,= FIQ_Handler_end - bx r0 ;Branch to FIQ_Handler -FIQ_Handler_end: - RestoreContext r0,r7 ; Restore the context and return to the... - ; ...program execution. - -;******************************************************************************* -;* Macro Name : IRQ_to_SYS -;* Description : This macro used to switch form IRQ mode to SYS mode. -;* Input : none. -;* Output : none -;******************************************************************************* -IRQ_to_SYS MACRO - MSR cpsr_c,#0x1F - STMFD sp!,{lr} - ENDM - -;******************************************************************************* -;* Macro Name : SYS_to_IRQ -;* Description : This macro used to switch from SYS mode to IRQ mode. -;* Input : none. -;* Output : none -;******************************************************************************* -SYS_to_IRQ MACRO - LDMFD sp!,{lr} - MSR cpsr_c,#0xD2 - MOV pc,lr - ENDM - -;******************************************************************************* -;* Function Name : WAKUPIRQHandler -;* Description : This function used to switch to SYS mode before entering -;* the WAKUP_IRQHandler function located in 75x_it.c. -;* Then to return to IRQ mode after the WAKUP_IRQHandler -;* function termination. -;* Input : none -;* Output : none -;******************************************************************************* -WAKUPIRQHandler - IRQ_to_SYS - ldr r0,=WAKUP_IRQHandler - ldr lr,=WAKUP_IRQHandler_end - bx r0 -WAKUP_IRQHandler_end: - SYS_to_IRQ - -;******************************************************************************* -;* Function Name : TIM2_OC2IRQHandler -;* Description : This function used to switch to SYS mode before entering -;* the TIM2_OC2_IRQHandler function located in 75x_it.c. -;* Then to return to IRQ mode after the TIM2_OC2_IRQHandler -;* function termination. -;* Input : none -;* Output : none -;******************************************************************************* -TIM2_OC2IRQHandler - IRQ_to_SYS - ldr r0,=TIM2_OC2_IRQHandler - ldr lr,=TIM2_OC2_IRQHandler_end - bx r0 -TIM2_OC2_IRQHandler_end: - SYS_to_IRQ - -;******************************************************************************* -;* Function Name : TIM2_OC1IRQHandler -;* Description : This function used to switch to SYS mode before entering -;* the TIM2_OC1_IRQHandler function located in 75x_it.c. -;* Then to return to IRQ mode after the TIM2_OC1_IRQHandler -;* function termination. -;* Input : none -;* Output : none -;******************************************************************************* -TIM2_OC1IRQHandler - IRQ_to_SYS - ldr r0,=TIM2_OC1_IRQHandler - ldr lr,=TIM2_OC1_IRQHandler_end - bx r0 -TIM2_OC1_IRQHandler_end: - SYS_to_IRQ - -;******************************************************************************* -;* Function Name : TIM2_IC12IRQHandler -;* Description : This function used to switch to SYS mode before entering -;* the TIM2_IC12_IRQHandler function located in 75x_it.c. -;* Then to return to IRQ mode after the TIM2_IC12_IRQHandler -;* function termination. -;* Input : none -;* Output : none -;******************************************************************************* -TIM2_IC12IRQHandler - IRQ_to_SYS - ldr r0,=TIM2_IC12_IRQHandler - ldr lr,=TIM2_IC12_IRQHandler_end - bx r0 -TIM2_IC12_IRQHandler_end: - SYS_to_IRQ - -;******************************************************************************* -;* Function Name : TIM2_UPIRQHandler -;* Description : This function used to switch to SYS mode before entering -;* the TIM2_UP_IRQHandler function located in 75x_it.c. -;* Then to return to IRQ mode after the TIM2_UP_IRQHandler -;* function termination. -;* Input : none -;* Output : none -;******************************************************************************* -TIM2_UPIRQHandler - IRQ_to_SYS - ldr r0,=TIM2_UP_IRQHandler - ldr lr,=TIM2_UP_IRQHandler_end - bx r0 -TIM2_UP_IRQHandler_end: - SYS_to_IRQ - -;******************************************************************************* -;* Function Name : TIM1_OC2IRQHandler -;* Description : This function used to switch to SYS mode before entering -;* the TIM1_OC2_IRQHandler function located in 75x_it.c. -;* Then to return to IRQ mode after the TIM1_OC2_IRQHandler -;* function termination. -;* Input : none -;* Output : none -;******************************************************************************* -TIM1_OC2IRQHandler - IRQ_to_SYS - ldr r0,=TIM1_OC2_IRQHandler - ldr lr,=TIM1_OC2_IRQHandler_end - bx r0 -TIM1_OC2_IRQHandler_end: - SYS_to_IRQ - -;******************************************************************************* -;* Function Name : TIM1_OC1IRQHandler -;* Description : This function used to switch to SYS mode before entering -;* the TIM1_OC1_IRQHandler function located in 75x_it.c. -;* Then to return to IRQ mode after the TIM1_OC1_IRQHandler -;* function termination. -;* Input : none -;* Output : none -;******************************************************************************* -TIM1_OC1IRQHandler - IRQ_to_SYS - ldr r0,=TIM1_OC1_IRQHandler - ldr lr,=TIM1_OC1_IRQHandler_end - bx r0 -TIM1_OC1_IRQHandler_end: - SYS_to_IRQ - -;******************************************************************************* -;* Function Name : TIM1_IC12IRQHandler -;* Description : This function used to switch to SYS mode before entering -;* the TIM1_IC12_IRQHandler function located in 75x_it.c. -;* Then to return to IRQ mode after the TIM1_IC12_IRQHandler -;* function termination. -;* Input : none -;* Output : none -;******************************************************************************* -TIM1_IC12IRQHandler - IRQ_to_SYS - ldr r0,=TIM1_IC12_IRQHandler - ldr lr,=TIM1_IC12_IRQHandler_end - bx r0 -TIM1_IC12_IRQHandler_end: - SYS_to_IRQ - -;******************************************************************************* -;* Function Name : TIM1_UPIRQHandler -;* Description : This function used to switch to SYS mode before entering -;* the TIM1_UP_IRQHandler function located in 75x_it.c. -;* Then to return to IRQ mode after the TIM1_UP_IRQHandler -;* function termination. -;* Input : none -;* Output : none -;******************************************************************************* -TIM1_UPIRQHandler - IRQ_to_SYS - ldr r0,=TIM1_UP_IRQHandler - ldr lr,=TIM1_UP_IRQHandler_end - bx r0 -TIM1_UP_IRQHandler_end: - SYS_to_IRQ - -;******************************************************************************* -;* Function Name : TIM0_OC2IRQHandler -;* Description : This function used to switch to SYS mode before entering -;* the TIM0_OC2_IRQHandler function located in 75x_it.c. -;* Then to return to IRQ mode after the TIM0_OC2_IRQHandler -;* function termination. -;* Input : none -;* Output : none -;******************************************************************************* -TIM0_OC2IRQHandler - IRQ_to_SYS - ldr r0,=TIM0_OC2_IRQHandler - ldr lr,=TIM0_OC2_IRQHandler_end - bx r0 -TIM0_OC2_IRQHandler_end: - SYS_to_IRQ - -;******************************************************************************* -;* Function Name : TIM0_OC1IRQHandler -;* Description : This function used to switch to SYS mode before entering -;* the TIM0_OC1_IRQHandler function located in 75x_it.c. -;* Then to return to IRQ mode after the TIM0_OC1_IRQHandler -;* function termination. -;* Input : none -;* Output : none -;******************************************************************************* -TIM0_OC1IRQHandler - IRQ_to_SYS - ldr r0,=TIM0_OC1_IRQHandler - ldr lr,=TIM0_OC1_IRQHandler_end - bx r0 -TIM0_OC1_IRQHandler_end: - SYS_to_IRQ - -;******************************************************************************* -;* Function Name : TIM0_IC12IRQHandler -;* Description : This function used to switch to SYS mode before entering -;* the TIM0_IC12_IRQHandler function located in 75x_it.c. -;* Then to return to IRQ mode after the TIM0_IC12_IRQHandler -;* function termination. -;* Input : none -;* Output : none -;******************************************************************************* -TIM0_IC12IRQHandler - IRQ_to_SYS - ldr r0,=TIM0_IC12_IRQHandler - ldr lr,=TIM0_IC12_IRQHandler_end - bx r0 -TIM0_IC12_IRQHandler_end: - SYS_to_IRQ - -;******************************************************************************* -;* Function Name : TIM0_UPIRQHandler -;* Description : This function used to switch to SYS mode before entering -;* the TIM0_UP_IRQHandler function located in 75x_it.c. -;* Then to return to IRQ mode after the TIM0_UP_IRQHandler -;* function termination. -;* Input : none -;* Output : none -;******************************************************************************* -TIM0_UPIRQHandler - IRQ_to_SYS - ldr r0,=TIM0_UP_IRQHandler - ldr lr,=TIM0_UP_IRQHandler_end - bx r0 -TIM0_UP_IRQHandler_end: - SYS_to_IRQ - -;******************************************************************************* -;* Function Name : PWM_OC123IRQHandler -;* Description : This function used to switch to SYS mode before entering -;* the PWM_OC123_IRQHandler function located in 75x_it.c. -;* Then to return to IRQ mode after the PWM_OC123_IRQHandler -;* function termination. -;* Input : none -;* Output : none -;******************************************************************************* -PWM_OC123IRQHandler - IRQ_to_SYS - ldr r0,=PWM_OC123_IRQHandler - ldr lr,=PWM_OC123_IRQHandler_end - bx r0 -PWM_OC123_IRQHandler_end: - SYS_to_IRQ - -;******************************************************************************* -;* Function Name : PWM_EMIRQHandler -;* Description : This function used to switch to SYS mode before entering -;* the PWM_EM_IRQHandler function located in 75x_it.c. -;* Then to return to IRQ mode after the PWM_EM_IRQHandler -;* function termination. -;* Input : none -;* Output : none -;******************************************************************************* -PWM_EMIRQHandler - IRQ_to_SYS - ldr r0,=PWM_EM_IRQHandler - ldr lr,=PWM_EM_IRQHandler_end - bx r0 -PWM_EM_IRQHandler_end: - SYS_to_IRQ - -;******************************************************************************* -;* Function Name : PWM_UPIRQHandler -;* Description : This function used to switch to SYS mode before entering -;* the PWM_UP_IRQHandler function located in 75x_it.c. -;* Then to return to IRQ mode after the PWM_UP_IRQHandler -;* function termination. -;* Input : none -;* Output : none -;******************************************************************************* -PWM_UPIRQHandler - IRQ_to_SYS - ldr r0,=PWM_UP_IRQHandler - ldr lr,=PWM_UP_IRQHandler_end - bx r0 -PWM_UP_IRQHandler_end: - SYS_to_IRQ - -;******************************************************************************* -;* Function Name : I2CIRQHandler -;* Description : This function used to switch to SYS mode before entering -;* the I2C_IRQHandler function located in 75x_it.c. -;* Then to return to IRQ mode after the I2C_IRQHandler function -;* termination. -;* Input : none -;* Output : none -;******************************************************************************* -I2CIRQHandler - IRQ_to_SYS - ldr r0,=I2C_IRQHandler - ldr lr,=I2C_IRQHandler_end - bx r0 -I2C_IRQHandler_end: - SYS_to_IRQ - -;******************************************************************************* -;* Function Name : SSP1IRQHandler -;* Description : This function used to switch to SYS mode before entering -;* the SSP1_IRQHandler function located in 75x_it.c. -;* Then to return to IRQ mode after the SSP1_IRQHandler -;* function termination. -;* Input : none -;* Output : none -;******************************************************************************* -SSP1IRQHandler - IRQ_to_SYS - ldr r0,=SSP1_IRQHandler - ldr lr,=SSP1_IRQHandler_end - bx r0 -SSP1_IRQHandler_end: - SYS_to_IRQ - -;******************************************************************************* -;* Function Name : SSP0IRQHandler -;* Description : This function used to switch to SYS mode before entering -;* the SSP0_IRQHandler function located in 75x_it.c. -;* Then to return to IRQ mode after the SSP0_IRQHandler -;* function termination. -;* Input : none -;* Output : none -;******************************************************************************* -SSP0IRQHandler - IRQ_to_SYS - ldr r0,=SSP0_IRQHandler - ldr lr,=SSP0_IRQHandler_end - bx r0 -SSP0_IRQHandler_end: - SYS_to_IRQ - -;******************************************************************************* -;* Function Name : UART2IRQHandler -;* Description : This function used to switch to SYS mode before entering -;* the UART2_IRQHandler function located in 75x_it.c. -;* Then to return to IRQ mode after the UART2_IRQHandler -;* function termination. -;* Input : none -;* Output : none -;******************************************************************************* -UART2IRQHandler - IRQ_to_SYS - ldr r0,=UART2_IRQHandler - ldr lr,=UART2_IRQHandler_end - bx r0 -UART2_IRQHandler_end: - SYS_to_IRQ - -;******************************************************************************* -;* Function Name : UART1IRQHandler -;* Description : This function used to switch to SYS mode before entering -;* the UART1_IRQHandler function located in 75x_it.c. -;* Then to return to IRQ mode after the UART1_IRQHandler -;* function termination. -;* Input : none -;* Output : none -;******************************************************************************* -UART1IRQHandler - IRQ_to_SYS - ldr r0,=UART1_IRQHandler - ldr lr,=UART1_IRQHandler_end - bx r0 -UART1_IRQHandler_end: - SYS_to_IRQ - -;******************************************************************************* -;* Function Name : UART0IRQHandler -;* Description : This function used to switch to SYS mode before entering -;* the UART0_IRQHandler function located in 75x_it.c. -;* Then to return to IRQ mode after the UART0_IRQHandler -;* function termination. -;* Input : none -;* Output : none -;******************************************************************************* -UART0IRQHandler - IRQ_to_SYS - ldr r0,=UART0_IRQHandler - ldr lr,=UART0_IRQHandler_end - bx r0 -UART0_IRQHandler_end: - SYS_to_IRQ - -;******************************************************************************* -;* Function Name : CANIRQHandler -;* Description : This function used to switch to SYS mode before entering -;* the CAN_IRQHandler function located in 75x_it.c. -;* Then to return to IRQ mode after the CAN_IRQHandler function -;* termination. -;* Input : none -;* Output : none -;******************************************************************************* -CANIRQHandler - IRQ_to_SYS - ldr r0,=CAN_IRQHandler - ldr lr,=CAN_IRQHandler_end - bx r0 -CAN_IRQHandler_end: - SYS_to_IRQ - -;******************************************************************************* -;* Function Name : USB_LPIRQHandler -;* Description : This function used to switch to SYS mode before entering -;* the USB_LP_IRQHandler function located in 75x_it.c. -;* Then to return to IRQ mode after the USB_LP_IRQHandler -;* function termination. -;* Input : none -;* Output : none -;******************************************************************************* -USB_LPIRQHandler - IRQ_to_SYS - ldr r0,=USB_LP_IRQHandler - ldr lr,=USB_LP_IRQHandler_end - bx r0 -USB_LP_IRQHandler_end: - SYS_to_IRQ - -;******************************************************************************* -;* Function Name : USB_HPIRQHandler -;* Description : This function used to switch to SYS mode before entering -;* the USB_HP_IRQHandler function located in 75x_it.c. -;* Then to return to IRQ mode after the USB_HP_IRQHandler -;* function termination. -;* Input : none -;* Output : none -;******************************************************************************* -USB_HPIRQHandler - IRQ_to_SYS - ldr r0,=USB_HP_IRQHandler - ldr lr,=USB_HP_IRQHandler_end - bx r0 -USB_HP_IRQHandler_end: - SYS_to_IRQ - -;******************************************************************************* -;* Function Name : ADCIRQHandler -;* Description : This function used to switch to SYS mode before entering -;* the ADC_IRQHandler function located in 75x_it.c. -;* Then to return to IRQ mode after the ADC_IRQHandler -;* function termination. -;* Input : none -;* Output : none -;******************************************************************************* -ADCIRQHandler - IRQ_to_SYS - ldr r0,=ADC_IRQHandler - ldr lr,=ADC_IRQHandler_end - bx r0 -ADC_IRQHandler_end: - SYS_to_IRQ - -;******************************************************************************* -;* Function Name : DMAIRQHandler -;* Description : This function used to switch to SYS mode before entering -;* the DMA_IRQHandler function located in 75x_it.c. -;* Then to return to IRQ mode after the DMA_IRQHandler -;* function termination. -;* Input : none -;* Output : none -;******************************************************************************* -DMAIRQHandler - IRQ_to_SYS - ldr r0,=DMA_IRQHandler - ldr lr,=DMA_IRQHandler_end - bx r0 -DMA_IRQHandler_end: - SYS_to_IRQ - -;******************************************************************************* -;* Function Name : EXTITIRQHandler -;* Description : This function used to switch to SYS mode before entering -;* the EXTIT_IRQHandler function located in 75x_it.c. -;* Then to return to IRQ mode after the EXTIT_IRQHandler -;* function termination. -;* Input : none -;* Output : none -;******************************************************************************* -EXTITIRQHandler - IRQ_to_SYS - ldr r0,=EXTIT_IRQHandler - ldr lr,=EXTIT_IRQHandler_end - bx r0 -EXTIT_IRQHandler_end: - SYS_to_IRQ - -;******************************************************************************* -;* Function Name : MRCCIRQHandler -;* Description : This function used to switch to SYS mode before entering -;* the MRCC_IRQHandler function located in 75x_it.c. -;* Then to return to IRQ mode after the MRCC_IRQHandler -;* function termination. -;* Input : none -;* Output : none -;******************************************************************************* -MRCCIRQHandler - IRQ_to_SYS - ldr r0,=MRCC_IRQHandler - ldr lr,=MRCC_IRQHandler_end - bx r0 -MRCC_IRQHandler_end: - SYS_to_IRQ - -;******************************************************************************* -;* Function Name : FLASHSMIIRQHandler -;* Description : This function used to switch to SYS mode before entering -;* the FLASHSMI_IRQHandler function located in 75x_it.c. -;* Then to return to IRQ mode after the FLASHSMI_IRQHandler -;* function termination. -;* Input : none -;* Output : none -;******************************************************************************* -FLASHSMIIRQHandler - IRQ_to_SYS - ldr r0,=FLASHSMI_IRQHandler - ldr lr,=FLASHSMI_IRQHandler_end - bx r0 -FLASHSMI_IRQHandler_end: - SYS_to_IRQ - -;******************************************************************************* -;* Function Name : RTCIRQHandler -;* Description : This function used to switch to SYS mode before entering -;* the RTC_IRQHandler function located in 75x_it.c. -;* Then to return to IRQ mode after the RTC_IRQHandler function -;* termination. -;* Input : none -;* Output : none -;******************************************************************************* -RTCIRQHandler - IRQ_to_SYS - ldr r0,=RTC_IRQHandler - ldr lr,=RTC_IRQHandler_end - bx r0 -RTC_IRQHandler_end: - SYS_to_IRQ - -;******************************************************************************* -;* Function Name : TBIRQHandler -;* Description : This function used to switch to SYS mode before entering -;* the TB_IRQHandler function located in 75x_it.c. -;* Then to return to IRQ mode after the TB_IRQHandler function -;* termination. -;* Input : none -;* Output : none -;******************************************************************************* -TBIRQHandler - IRQ_to_SYS - ldr r0,=TB_IRQHandler - ldr lr,=TB_IRQHandler_end - bx r0 -TB_IRQHandler_end: - SYS_to_IRQ - - LTORG - - END -;******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE***** - - - - - - - - - - - diff --git a/Demo/ARM7_STR75x_IAR/FreeRTOSConfig.h b/Demo/ARM7_STR75x_IAR/FreeRTOSConfig.h deleted file mode 100644 index 964ec4062..000000000 --- a/Demo/ARM7_STR75x_IAR/FreeRTOSConfig.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 60000000 ) /* Timer clock. */ -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 100 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) 12800 ) -#define configMAX_TASK_NAME_LEN ( 16 ) -#define configUSE_TRACE_FACILITY 0 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 0 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 0 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/ARM7_STR75x_IAR/ParTest/ParTest.c b/Demo/ARM7_STR75x_IAR/ParTest/ParTest.c deleted file mode 100644 index a2feddb69..000000000 --- a/Demo/ARM7_STR75x_IAR/ParTest/ParTest.c +++ /dev/null @@ -1,137 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* Library includes. */ -#include "75x_GPIO.h" -#include "75x_map.h" - -/* Scheduler includes. */ -#include "FreeRTOS.h" - -/* Demo application includes. */ -#include "partest.h" - -/*----------------------------------------------------------- - * Simple parallel port IO routines for the LED's - *-----------------------------------------------------------*/ - -#define partstNUM_LEDS 4 - -typedef struct GPIOMAP -{ - GPIO_TypeDef *pxPort; - unsigned portLONG ulPin; - unsigned portLONG ulValue; -} GPIO_MAP; - -static GPIO_MAP xLEDMap[ partstNUM_LEDS ] = -{ - { ( GPIO_TypeDef * )GPIO1_BASE, GPIO_Pin_1, 0UL }, - { ( GPIO_TypeDef * )GPIO0_BASE, GPIO_Pin_16, 0UL }, - { ( GPIO_TypeDef * )GPIO2_BASE, GPIO_Pin_18, 0UL }, - { ( GPIO_TypeDef * )GPIO2_BASE, GPIO_Pin_19, 0UL } -}; - -/*-----------------------------------------------------------*/ - -void vParTestInitialise( void ) -{ -GPIO_InitTypeDef GPIO_InitStructure ; - - /* Configure the bits used to flash LED's on port 1 as output. */ - - /* Configure LED3 */ - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_16; - GPIO_Init(GPIO0,&GPIO_InitStructure); - - /* Configure LED2 */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1; - GPIO_Init(GPIO1, &GPIO_InitStructure); - - /* Configure LED4 and LED5 */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_18 | GPIO_Pin_19; - GPIO_Init(GPIO2, &GPIO_InitStructure); - - vParTestSetLED( 0, 0 ); - vParTestSetLED( 1, 0 ); - vParTestSetLED( 2, 0 ); - vParTestSetLED( 3, 0 ); -} -/*-----------------------------------------------------------*/ - -void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) -{ - if( uxLED < partstNUM_LEDS ) - { - portENTER_CRITICAL(); - { - if( xValue ) - { - GPIO_WriteBit( xLEDMap[ uxLED ].pxPort, xLEDMap[ uxLED ].ulPin, Bit_RESET ); - xLEDMap[ uxLED ].ulValue = 0; - } - else - { - GPIO_WriteBit( xLEDMap[ uxLED ].pxPort, xLEDMap[ uxLED ].ulPin, Bit_SET ); - xLEDMap[ uxLED ].ulValue = 1; - } - } - portEXIT_CRITICAL(); - } -} -/*-----------------------------------------------------------*/ - -void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) -{ - if( uxLED < partstNUM_LEDS ) - { - portENTER_CRITICAL(); - { - if( xLEDMap[ uxLED ].ulValue == 1 ) - { - GPIO_WriteBit( xLEDMap[ uxLED ].pxPort, xLEDMap[ uxLED ].ulPin, Bit_RESET ); - xLEDMap[ uxLED ].ulValue = 0; - } - else - { - GPIO_WriteBit( xLEDMap[ uxLED ].pxPort, xLEDMap[ uxLED ].ulPin, Bit_SET ); - xLEDMap[ uxLED ].ulValue = 1; - } - } - portEXIT_CRITICAL(); - } -} - - - - diff --git a/Demo/ARM7_STR75x_IAR/RTOSDemo.ewd b/Demo/ARM7_STR75x_IAR/RTOSDemo.ewd deleted file mode 100644 index 77da49bb2..000000000 --- a/Demo/ARM7_STR75x_IAR/RTOSDemo.ewd +++ /dev/null @@ -1,1043 +0,0 @@ - - - - 1 - - Debug - - ARM - - 1 - - C-SPY - 2 - - 13 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - ARMSIM_ID - 2 - - 0 - 1 - 1 - - - - - ANGEL_ID - 2 - - 0 - 1 - 1 - - - - - - - - - - - - IARROM_ID - 2 - - 0 - 1 - 1 - - - - - - - - - - JLINK_ID - 2 - - 6 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - MACRAIGOR_ID - 2 - - 2 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - RDI_ID - 2 - - 1 - 1 - 1 - - - - - - - - - - - - - - - - - THIRDPARTY_ID - 2 - - 0 - 1 - 1 - - - - - - - - - $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin - 1 - - - $EW_DIR$\common\plugins\Orti\Orti.ewplugin - 0 - - - $EW_DIR$\common\plugins\Profiling\Profiling.ewplugin - 1 - - - $EW_DIR$\common\plugins\Stack\stack.ewplugin - 1 - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin - 0 - - - - - Release - - ARM - - 1 - - C-SPY - 2 - - 13 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - ARMSIM_ID - 2 - - 0 - 1 - 1 - - - - - ANGEL_ID - 2 - - 0 - 1 - 1 - - - - - - - - - - - - IARROM_ID - 2 - - 0 - 1 - 1 - - - - - - - - - - JLINK_ID - 2 - - 6 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - MACRAIGOR_ID - 2 - - 2 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - RDI_ID - 2 - - 1 - 1 - 1 - - - - - - - - - - - - - - - - - THIRDPARTY_ID - 2 - - 0 - 1 - 1 - - - - - - - - - $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin - 1 - - - $EW_DIR$\common\plugins\Orti\Orti.ewplugin - 0 - - - $EW_DIR$\common\plugins\Profiling\Profiling.ewplugin - 1 - - - $EW_DIR$\common\plugins\Stack\stack.ewplugin - 1 - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin - 0 - - - - - - diff --git a/Demo/ARM7_STR75x_IAR/RTOSDemo.ewp b/Demo/ARM7_STR75x_IAR/RTOSDemo.ewp deleted file mode 100644 index c078f2f2f..000000000 --- a/Demo/ARM7_STR75x_IAR/RTOSDemo.ewp +++ /dev/null @@ -1,1741 +0,0 @@ - - - - 1 - - Debug - - ARM - - 1 - - General - 2 - - 9 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 13 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 7 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - XLINK - 2 - - 18 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - XAR - 2 - - 0 - 1 - 1 - - - - - - - BILINK - 0 - - - - - Release - - ARM - - 1 - - General - 2 - - 9 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 13 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 7 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - XLINK - 2 - - 18 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - XAR - 2 - - 0 - 1 - 1 - - - - - - - BILINK - 0 - - - - - Demo Source - - $PROJ_DIR$\..\Common\Minimal\BlockQ.c - - - $PROJ_DIR$\..\Common\Minimal\blocktim.c - - - $PROJ_DIR$\..\Common\Minimal\comtest.c - - - $PROJ_DIR$\..\Common\Minimal\dynamic.c - - - $PROJ_DIR$\..\Common\Minimal\flash.c - - - $PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c - - - $PROJ_DIR$\..\Common\Minimal\integer.c - - - $PROJ_DIR$\STLibrary\src\lcd.c - - - $PROJ_DIR$\main.c - - - $PROJ_DIR$\ParTest\ParTest.c - - - $PROJ_DIR$\serial\serial.c - - - - Library Source - - $PROJ_DIR$\STLibrary\src\75x_cfg.c - - - $PROJ_DIR$\STLibrary\src\75x_eic.c - - - $PROJ_DIR$\STLibrary\src\75x_gpio.c - - - $PROJ_DIR$\STLibrary\src\75x_it.c - - - $PROJ_DIR$\STLibrary\src\75x_lib.c - - - $PROJ_DIR$\STLibrary\src\75x_mrcc.c - - - $PROJ_DIR$\STLibrary\src\75x_tb.c - - - $PROJ_DIR$\STLibrary\src\75x_uart.c - - - - RTOS Source - - $PROJ_DIR$\..\..\Source\list.c - - - $PROJ_DIR$\..\..\Source\portable\IAR\STR75x\port.c - - - $PROJ_DIR$\..\..\Source\portable\IAR\STR75x\portasm.s79 - - - $PROJ_DIR$\..\..\Source\queue.c - - - $PROJ_DIR$\..\..\Source\tasks.c - - - - startup - - $PROJ_DIR$\75x_init.s - - - $PROJ_DIR$\75x_vect.s - - - - - diff --git a/Demo/ARM7_STR75x_IAR/RTOSDemo.eww b/Demo/ARM7_STR75x_IAR/RTOSDemo.eww deleted file mode 100644 index 239a9381e..000000000 --- a/Demo/ARM7_STR75x_IAR/RTOSDemo.eww +++ /dev/null @@ -1,10 +0,0 @@ - - - - - $WS_DIR$\RTOSDemo.ewp - - - - - diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_adc.h b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_adc.h deleted file mode 100644 index bce23f731..000000000 --- a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_adc.h +++ /dev/null @@ -1,177 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_adc.h -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file contains all the functions prototypes for the -* ADC software library. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __75x_ADC_H -#define __75x_ADC_H - -/* Includes ------------------------------------------------------------------*/ -#include "75x_map.h" - -/* Exported types ------------------------------------------------------------*/ -/* ADC Init structure definition */ -typedef struct -{ - u16 ADC_ConversionMode; - u16 ADC_ExtTrigger; - u16 ADC_AutoClockOff; - u8 ADC_SamplingPrescaler; - u8 ADC_ConversionPrescaler; - u8 ADC_FirstChannel; - u8 ADC_ChannelNumber; - }ADC_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ -/* ADC control status flags */ -#define ADC_FLAG_ECH 0x0001 -#define ADC_FLAG_EOC 0x0002 -#define ADC_FLAG_JECH 0x0004 -#define ADC_FLAG_JEOC 0x0008 -#define ADC_FLAG_AnalogWatchdog0_LowThreshold 0x0010 -#define ADC_FLAG_AnalogWatchdog0_HighThreshold 0x0020 -#define ADC_FLAG_AnalogWatchdog1_LowThreshold 0x0040 -#define ADC_FLAG_AnalogWatchdog1_HighThreshold 0x0080 -#define ADC_FLAG_AnalogWatchdog2_LowThreshold 0x0100 -#define ADC_FLAG_AnalogWatchdog2_HighThreshold 0x0200 -#define ADC_FLAG_AnalogWatchdog3_LowThreshold 0x0400 -#define ADC_FLAG_AnalogWatchdog3_HighThreshold 0x0800 - -/* ADC Interrupt sources */ -#define ADC_IT_ECH 0x0001 -#define ADC_IT_EOC 0x0002 -#define ADC_IT_JECH 0x0004 -#define ADC_IT_JEOC 0x0008 -#define ADC_IT_AnalogWatchdog0_LowThreshold 0x0010 -#define ADC_IT_AnalogWatchdog0_HighThreshold 0x0020 -#define ADC_IT_AnalogWatchdog1_LowThreshold 0x0040 -#define ADC_IT_AnalogWatchdog1_HighThreshold 0x0080 -#define ADC_IT_AnalogWatchdog2_LowThreshold 0x0100 -#define ADC_IT_AnalogWatchdog2_HighThreshold 0x0200 -#define ADC_IT_AnalogWatchdog3_LowThreshold 0x0400 -#define ADC_IT_AnalogWatchdog3_HighThreshold 0x0800 -#define ADC_IT_ALL 0x0FFF - -/* ADC Watchdogs Thresholds */ -#define ADC_AnalogWatchdog0 0x0030 -#define ADC_AnalogWatchdog1 0x00C0 -#define ADC_AnalogWatchdog2 0x0300 -#define ADC_AnalogWatchdog3 0x0C00 - -/* ADC Channels */ -#define ADC_CHANNEL0 0x0 -#define ADC_CHANNEL1 0x1 -#define ADC_CHANNEL2 0x2 -#define ADC_CHANNEL3 0x3 -#define ADC_CHANNEL4 0x4 -#define ADC_CHANNEL5 0x5 -#define ADC_CHANNEL6 0x6 -#define ADC_CHANNEL7 0x7 -#define ADC_CHANNEL8 0x8 -#define ADC_CHANNEL9 0x9 -#define ADC_CHANNEL10 0xA -#define ADC_CHANNEL11 0xB -#define ADC_CHANNEL12 0xC -#define ADC_CHANNEL13 0xD -#define ADC_CHANNEL14 0xE -#define ADC_CHANNEL15 0xF - -/* ADC DMA Channels */ -#define ADC_DMA_CHANNEL0 0x0001 -#define ADC_DMA_CHANNEL1 0x0002 -#define ADC_DMA_CHANNEL2 0x0004 -#define ADC_DMA_CHANNEL3 0x0008 -#define ADC_DMA_CHANNEL4 0x0010 -#define ADC_DMA_CHANNEL5 0x0020 -#define ADC_DMA_CHANNEL6 0x0040 -#define ADC_DMA_CHANNEL7 0x0080 -#define ADC_DMA_CHANNEL8 0x0100 -#define ADC_DMA_CHANNEL9 0x0200 -#define ADC_DMA_CHANNEL10 0x0400 -#define ADC_DMA_CHANNEL11 0x0800 -#define ADC_DMA_CHANNEL12 0x1000 -#define ADC_DMA_CHANNEL13 0x2000 -#define ADC_DMA_CHANNEL14 0x4000 -#define ADC_DMA_CHANNEL15 0x8000 - -/* Trigger conversion detection */ -#define ADC_ExtTrigger_LowLevel 0x4FFF -#define ADC_ExtTrigger_HighLevel 0x5000 -#define ADC_ExtTrigger_FallingEdge 0x6000 -#define ADC_ExtTrigger_RisingEdge 0x7000 -#define ADC_ExtTrigger_Disable 0x8FFF - -/* DMA enable config */ -#define ADC_DMA_ExtTrigger_HighLevel 0x6000 -#define ADC_DMA_ExtTrigger_LowLevel 0x4FFF -#define ADC_DMA_Enable 0x8000 -#define ADC_DMA_Disable 0x3FFF - -/* Injected Trigger conversion detection */ -#define ADC_Injec_ExtTrigger_RisingEdge 0x6000 -#define ADC_Injec_ExtTrigger_FallingEdge 0xDFFF -#define ADC_Injec_ExtTrigger_Disable 0x3FFF - -/* Start Conversion */ -#define ADC_Conversion_Start 0x0001 -#define ADC_Conversion_Stop 0xFFFE - -/* ADC Conversion Modes */ -#define ADC_ConversionMode_Scan 0x8000 -#define ADC_ConversionMode_OneShot 0x7FFF - -/* Auto Clock Off */ -#define ADC_AutoClockOff_Enable 0x4000 -#define ADC_AutoClockOff_Disable 0xBFFF - -/* Calibration */ -#define ADC_Calibration_ON 0x0002 -#define ADC_CalibAverage_Disable 0x0020 -#define ADC_CalibAverage_Enable 0xFFDF - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -void ADC_DeInit(void); -void ADC_Init(ADC_InitTypeDef *ADC_InitStruct); -void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct); -void ADC_Cmd(FunctionalState NewState); -void ADC_StartCalibration(u16 ADC_CalibAverage); -FlagStatus ADC_GetCalibrationStatus(void); -void ADC_ConversionCmd(u16 ADC_Conversion); -FlagStatus ADC_GetSTARTBitStatus(void); -void ADC_AutoClockOffConfig(FunctionalState NewState); -u16 ADC_GetConversionValue(u8 ADC_CHANNEL); -void ADC_ITConfig(u16 ADC_IT, FunctionalState NewState); -void ADC_AnalogWatchdogConfig(u16 ADC_AnalogWatchdog, u8 ADC_CHANNEL, - u16 LowThreshold, u16 HighThreshold); -void ADC_AnalogWatchdogCmd(u16 ADC_AnalogWatchdog, FunctionalState NewState); -u16 ADC_GetAnalogWatchdogResult(u16 ADC_AnalogWatchdog); -void ADC_StartInjectedConversion(void); -void ADC_InjectedConversionConfig(u16 ADC_Injec_ExtTrigger, u8 FirstChannel, u8 ChannelNumber); -void ADC_DMAConfig(u16 ADC_DMA_CHANNEL, FunctionalState NewState); -void ADC_DMACmd(u16 ADC_DMA); -u16 ADC_GetDMAFirstEnabledChannel(void); -FlagStatus ADC_GetFlagStatus(u16 ADC_FLAG); -void ADC_ClearFlag(u16 ADC_FLAG); -ITStatus ADC_GetITStatus(u16 ADC_IT); -void ADC_ClearITPendingBit(u16 ADC_IT); - -#endif /*__75x_ADC_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_can.h b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_can.h deleted file mode 100644 index 9b630ee0c..000000000 --- a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_can.h +++ /dev/null @@ -1,165 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_can.h -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file contains all the functions prototypes for the -* CAN bus software library. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __75x_CAN_H -#define __75x_CAN_H - -/* Includes ------------------------------------------------------------------*/ -#include "75x_map.h" - -/* Exported types ------------------------------------------------------------*/ - -/* CAN Init structure define */ -typedef struct -{ - u8 CAN_ConfigParameters; - u32 CAN_Bitrate; -}CAN_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ -/* Standard bitrates available*/ -enum -{ - CAN_BITRATE_100K, - CAN_BITRATE_125K, - CAN_BITRATE_250K, - CAN_BITRATE_500K, - CAN_BITRATE_1M -}; - -/* Control register*/ -#define CAN_CR_TEST 0x0080 -#define CAN_CR_CCE 0x0040 -#define CAN_CR_DAR 0x0020 -#define CAN_CR_EIE 0x0008 -#define CAN_CR_SIE 0x0004 -#define CAN_CR_IE 0x0002 -#define CAN_CR_INIT 0x0001 - -/* Status register */ -#define CAN_SR_BOFF 0x0080 -#define CAN_SR_EWARN 0x0040 -#define CAN_SR_EPASS 0x0020 -#define CAN_SR_RXOK 0x0010 -#define CAN_SR_TXOK 0x0008 -#define CAN_SR_LEC 0x0007 - -/* Test register*/ -#define CAN_TESTR_RX 0x0080 -#define CAN_TESTR_TX1 0x0040 -#define CAN_TESTR_TX0 0x0020 -#define CAN_TESTR_LBACK 0x0010 -#define CAN_TESTR_SILENT 0x0008 -#define CAN_TESTR_BASIC 0x0004 - -/* IFn / Command Request register*/ -#define CAN_CRR_BUSY 0x8000 - -/* IFn / Command Mask register*/ -#define CAN_CMR_WRRD 0x0080 -#define CAN_CMR_MASK 0x0040 -#define CAN_CMR_ARB 0x0020 -#define CAN_CMR_CONTROL 0x0010 -#define CAN_CMR_CLRINTPND 0x0008 -#define CAN_CMR_TXRQSTNEWDAT 0x0004 -#define CAN_CMR_DATAA 0x0002 -#define CAN_CMR_DATAB 0x0001 - -/* IFn / Mask 2 register*/ -#define CAN_M2R_MXTD 0x8000 -#define CAN_M2R_MDIR 0x4000 - -/* IFn / Arbitration 2 register*/ -#define CAN_A2R_MSGVAL 0x8000 -#define CAN_A2R_XTD 0x4000 -#define CAN_A2R_DIR 0x2000 - -/* IFn / Message Control register*/ -#define CAN_MCR_NEWDAT 0x8000 -#define CAN_MCR_MSGLST 0x4000 -#define CAN_MCR_INTPND 0x2000 -#define CAN_MCR_UMASK 0x1000 -#define CAN_MCR_TXIE 0x0800 -#define CAN_MCR_RXIE 0x0400 -#define CAN_MCR_RMTEN 0x0200 -#define CAN_MCR_TXRQST 0x0100 -#define CAN_MCR_EOB 0x0080 - - -/* Wake-up modes*/ -enum -{ - CAN_WAKEUP_ON_EXT, - CAN_WAKEUP_ON_CAN -}; - - -/* CAN message structure*/ -typedef struct -{ - u32 IdType; - u32 Id; - u8 Dlc; - u8 Data[8]; -} canmsg; - -/* Message ID types*/ -enum -{ - CAN_STD_ID, - CAN_EXT_ID -}; - -/* Message ID limits*/ - -#define CAN_LAST_STD_ID ((1<<11) - 1) -#define CAN_LAST_EXT_ID ((1L<<29) - 1) - -/* Exported functions ------------------------------------------------------- */ - -void CAN_Init (CAN_InitTypeDef *CAN_InitStruct); -void CAN_DeInit (void); -void CAN_StructInit(CAN_InitTypeDef *CAN_InitStruct); -void CAN_SetBitrate(u32 bitrate); -void CAN_SetTiming(u32 tseg1, u32 tseg2, u32 sjw, u32 brp); -ErrorStatus CAN_SetUnusedMsgObj(u32 msgobj); -ErrorStatus CAN_SetTxMsgObj(u32 msgobj, u32 idType); -ErrorStatus CAN_SetRxMsgObj(u32 msgobj, u32 idType, u32 idLow, u32 idHigh, bool singleOrFifoLast); -void CAN_InvalidateAllMsgObj(void); -ErrorStatus CAN_ReleaseMessage(u32 msgobj); -ErrorStatus CAN_SendMessage(u32 msgobj, canmsg* pCanMsg); -ErrorStatus CAN_ReceiveMessage(u32 msgobj, bool release, canmsg* pCanMsg); -ErrorStatus CAN_WaitEndOfTx(void); -ErrorStatus CAN_BasicSendMessage(canmsg* pCanMsg); -ErrorStatus CAN_BasicReceiveMessage(canmsg* pCanMsg); -void CAN_EnterTestMode(u8 TestMask); -void CAN_EnterInitMode(u8 InitMask); -void CAN_LeaveInitMode(void); -void CAN_LeaveTestMode(void); -void CAN_ReleaseTxMessage(u32 msgobj); -void CAN_ReleaseRxMessage(u32 msgobj); -u32 CAN_IsMessageWaiting(u32 msgobj); -u32 CAN_IsTransmitRequested(u32 msgobj); -u32 CAN_IsInterruptPending(u32 msgobj); -u32 CAN_IsObjectValid(u32 msgobj); - -#endif /* __75x_CAN_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_cfg.h b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_cfg.h deleted file mode 100644 index e1042a246..000000000 --- a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_cfg.h +++ /dev/null @@ -1,48 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_cfg.h -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file contains all the functions prototypes for the -* CFG software library. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __75x_CFG_H -#define __75x_CFG_H - -/* Includes ------------------------------------------------------------------*/ -#include "75x_map.h" - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -#define CFG_BootSpace_FLASH 0x00000000 -#define CFG_BootSpace_SRAM 0x00000002 -#define CFG_BootSpace_ExtSMI 0x00000003 - -#define CFG_FLASHBurst_Disable 0xFFFFFEFF -#define CFG_FLASHBurst_Enable 0x00000100 - -#define CFG_USBFilter_Disable 0xFFFFFDFF -#define CFG_USBFilter_Enable 0x00000200 - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -void CFG_BootSpaceConfig(u32 CFG_BootSpace); -void CFG_FLASHBurstConfig(u32 CFG_FLASHBurst); -void CFG_USBFilterConfig(u32 CFG_USBFilter); -FlagStatus CFG_GetFlagStatus(void); - -#endif /* __75x_CFG_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_conf.h b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_conf.h deleted file mode 100644 index ab3c5394f..000000000 --- a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_conf.h +++ /dev/null @@ -1,106 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_conf.h -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : Library configuration file. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __75x_CONF_H -#define __75x_CONF_H - -/* Includes ------------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Comment the line below to compile the library in release mode */ -//#define DEBUG - -/************************************* SMI ************************************/ -//#define _SMI - -/************************************* CFG ************************************/ -#define _CFG - -/************************************* MRCC ************************************/ -#define _MRCC - -/************************************* ADC ************************************/ -//#define _ADC - -/************************************* TB *************************************/ -#define _TB - -/************************************* TIM ************************************/ -#define _TIM -#define _TIM0 -#define _TIM1 -#define _TIM2 - -/************************************* PWM ************************************/ -#define _PWM - -/************************************* WDG ************************************/ -#define _WDG - -/************************************* SSP ************************************/ -//#define _SSP -//#define _SSP0 -//#define _SSP1 - -/************************************* CAN ************************************/ -//#define _CAN - -/************************************* I2C ************************************/ -//#define _I2C - -/************************************* UART ***********************************/ -#define _UART -#define _UART0 -#define _UART1 -#define _UART2 - -/************************************* GPIO ***********************************/ -#define _GPIO -#define _GPIO0 -#define _GPIO1 -#define _GPIO2 -#define _GPIOREMAP - -/************************************* DMA ************************************/ -//#define _DMA -//#define _DMA_Stream0 -//#define _DMA_Stream1 -//#define _DMA_Stream2 -//#define _DMA_Stream3 - -/************************************* RTC ************************************/ -//#define _RTC - -/************************************* EXTIT **********************************/ -#define _EXTIT - -/************************************* EIC ************************************/ -#define _EIC - -/* Comment the following line, depending on the external Quartz oscillator used - in your application */ -#define Main_Oscillator 4000000 /* 4 MHz Quartz oscillator used */ -//#define Main_Oscillator 8000000 /* 8 MHz Quartz oscillator used */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -#endif /* __75x_CONF_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_dma.h b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_dma.h deleted file mode 100644 index f71b1cad4..000000000 --- a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_dma.h +++ /dev/null @@ -1,140 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_dma.h -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file contains all the functions prototypes for the -* DMA software library. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion ------------------------------------ */ -#ifndef __75x_DMA_H -#define __75x_DMA_H - -/* Includes ------------------------------------------------------------------*/ -#include "75x_map.h" - -/* Exported types ------------------------------------------------------------*/ -/* DMA Init structure definition */ -typedef struct -{ - u32 DMA_SRCBaseAddr; - u32 DMA_DSTBaseAddr; - u16 DMA_BufferSize; - u16 DMA_SRC; - u16 DMA_DST; - u16 DMA_SRCSize; - u16 DMA_SRCBurst; - u16 DMA_DSTSize; - u16 DMA_Mode; - u16 DMA_M2M; - u16 DMA_DIR; -}DMA_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ -/* DMA interrupt Mask */ -#define DMA_IT_SI0 0x0001 -#define DMA_IT_SI1 0x0002 -#define DMA_IT_SI2 0x0004 -#define DMA_IT_SI3 0x0008 -#define DMA_IT_SE0 0x0010 -#define DMA_IT_SE1 0x0020 -#define DMA_IT_SE2 0x0040 -#define DMA_IT_SE3 0x0080 -#define DMA_IT_ALL 0x00FF - -/* DMA Flags */ -#define DMA_FLAG_SI0 0x0001 -#define DMA_FLAG_SI1 0x0002 -#define DMA_FLAG_SI2 0x0004 -#define DMA_FLAG_SI3 0x0008 -#define DMA_FLAG_SE0 0x0010 -#define DMA_FLAG_SE1 0x0020 -#define DMA_FLAG_SE2 0x0040 -#define DMA_FLAG_SE3 0x0080 -#define DMA_FLAG_ACT0 0x0100 -#define DMA_FLAG_ACT1 0x0200 -#define DMA_FLAG_ACT2 0x0400 -#define DMA_FLAG_ACT3 0x0800 - -/* DMA Increment Current Source Register */ -#define DMA_SRC_INCR 0x0002 -#define DMA_SRC_NOT_INCR 0xFFFD - -/* DMA Increment Current Destination Register */ -#define DMA_DST_INCR 0x0004 -#define DMA_DST_NOT_INCR 0xFFFB - -/* Source to DMA data width */ -#define DMA_SRCSize_Byte 0x0000 -#define DMA_SRCSize_HalfWord 0x0008 -#define DMA_SRCSize_Word 0x0010 - -/* DMA source burst size */ -#define DMA_SRCBurst_1Data 0x0000 -#define DMA_SRCBurst_4Data 0x0020 -#define DMA_SRCBurst_8Data 0x0040 -#define DMA_SRCBurst_16Data 0x0060 - -/* DMA destination data width */ -#define DMA_DSTSize_Byte 0x0000 -#define DMA_DSTSize_HalfWord 0x0080 -#define DMA_DSTSize_Word 0x0100 - -/* DMA mode */ -#define DMA_Mode_Circular 0x0200 -#define DMA_Mode_Normal 0xFDFF - -/* Memory to Memory Transfer */ -#define DMA_M2M_Enable 0x0800 -#define DMA_M2M_Disable 0xF7FF - -/* Direction Transfer */ -#define DMA_DIR_PeriphDST 0x2000 -#define DMA_DIR_PeriphSRC 0xDFFF - -/* DMA streamx Registers */ -#define DMA_SOURCEL 0x00000000 /* source base address low register */ -#define DMA_SOURCEH 0x00000004 /* source base address high register */ -#define DMA_DESTL 0x00000008 /* destination base address low register */ -#define DMA_DESTH 0x0000000C /* destination base address high register */ -#define DMA_MAX 0x00000010 /* Maximum count register */ -#define DMA_CTRL 0x00000014 /* Control register */ -#define DMA_SOCURRH 0x00000018 /* Current Source address high register */ -#define DMA_SOCURRL 0x0000001C /* Current Source address low register */ -#define DMA_DECURRH 0x00000020 /* Current Destination address high register */ -#define DMA_DECURRL 0x00000024 /* Current Destination address low register */ -#define DMA_TCNT 0x00000028 /* Terminal Counter Register */ -#define DMA_LUBUFF 0x0000002C /* Last Used Buffer location */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -void DMA_DeInit(DMA_Stream_TypeDef* DMA_Streamx); -void DMA_Init(DMA_Stream_TypeDef* DMA_Streamx, DMA_InitTypeDef* DMA_InitStruct); -void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); -void DMA_Cmd(DMA_Stream_TypeDef* DMA_Streamx, FunctionalState NewState); -void DMA_ITConfig(u16 DMA_IT, FunctionalState NewState); -u32 DMA_GetCurrDSTAddr(DMA_Stream_TypeDef* DMA_Streamx); -u32 DMA_GetCurrSRCAddr(DMA_Stream_TypeDef* DMA_Streamx); -u16 DMA_GetTerminalCounter(DMA_Stream_TypeDef* DMA_Streamx); -void DMA_LastBufferSweepConfig(DMA_Stream_TypeDef* DMA_Streamx, FunctionalState NewState); -void DMA_LastBufferAddrConfig(DMA_Stream_TypeDef* DMA_Streamx, u16 DMA_LastBufferAddr); -FlagStatus DMA_GetFlagStatus(u16 DMA_FLAG); -void DMA_ClearFlag(u16 DMA_FLAG); -ITStatus DMA_GetITStatus(u16 DMA_IT); -void DMA_ClearITPendingBit(u16 DMA_IT); - -#endif /* __75x_DMA_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_eic.h b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_eic.h deleted file mode 100644 index c7e6a07cf..000000000 --- a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_eic.h +++ /dev/null @@ -1,97 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_eic.h -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file contains all the functions prototypes for the -* EIC software library. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __75x_EIC_H -#define __75x_EIC_H - -/* Includes ------------------------------------------------------------------*/ -#include "75x_map.h" - -/* Exported types ------------------------------------------------------------*/ -typedef struct -{ - u8 EIC_IRQChannel; - u8 EIC_IRQChannelPriority; - FunctionalState EIC_IRQChannelCmd; -}EIC_IRQInitTypeDef; - -typedef struct -{ - u8 EIC_FIQChannel; - FunctionalState EIC_FIQChannelCmd; -}EIC_FIQInitTypeDef; - -/* Exported constants --------------------------------------------------------*/ -/* IRQ channels */ -#define WAKUP_IRQChannel 0 -#define TIM2_OC2_IRQChannel 1 -#define TIM2_OC1_IRQChannel 2 -#define TIM2_IC12_IRQChannel 3 -#define TIM2_UP_IRQChannel 4 -#define TIM1_OC2_IRQChannel 5 -#define TIM1_OC1_IRQChannel 6 -#define TIM1_IC12_IRQChannel 7 -#define TIM1_UP_IRQChannel 8 -#define TIM0_OC2_IRQChannel 9 -#define TIM0_OC1_IRQChannel 10 -#define TIM0_IC12_IRQChannel 11 -#define TIM0_UP_IRQChannel 12 -#define PWM_OC123_IRQChannel 13 -#define PWM_EM_IRQChannel 14 -#define PWM_UP_IRQChannel 15 -#define I2C_IRQChannel 16 -#define SSP1_IRQChannel 17 -#define SSP0_IRQChannel 18 -#define UART2_IRQChannel 19 -#define UART1_IRQChannel 20 -#define UART0_IRQChannel 21 -#define CAN_IRQChannel 22 -#define USB_LP_IRQChannel 23 -#define USB_HP_IRQChannel 24 -#define ADC_IRQChannel 25 -#define DMA_IRQChannel 26 -#define EXTIT_IRQChannel 27 -#define MRCC_IRQChannel 28 -#define FLASHSMI_IRQChannel 29 -#define RTC_IRQChannel 30 -#define TB_IRQChannel 31 - -/* FIQ channels */ -#define EXTIT_Line0_FIQChannel 0x00000001 -#define WATCHDOG_FIQChannel 0x00000002 - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -void EIC_DeInit(void); -void EIC_IRQInit(EIC_IRQInitTypeDef* EIC_IRQInitStruct); -void EIC_FIQInit(EIC_FIQInitTypeDef* EIC_FIQInitStruct); -void EIC_IRQStructInit(EIC_IRQInitTypeDef* EIC_IRQInitStruct); -void EIC_FIQStructInit(EIC_FIQInitTypeDef* EIC_FIQInitStruct); -void EIC_IRQCmd(FunctionalState NewState); -void EIC_FIQCmd(FunctionalState NewState); -u8 EIC_GetCurrentIRQChannel(void); -u8 EIC_GetCurrentIRQChannelPriority(void); -void EIC_CurrentIRQPriorityConfig(u8 NewPriority); -u8 EIC_GetCurrentFIQChannel(void); -void EIC_ClearFIQPendingBit(u8 EIC_FIQChannel); - -#endif /* __75x_EIC_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_extit.h b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_extit.h deleted file mode 100644 index 5dbbc3a09..000000000 --- a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_extit.h +++ /dev/null @@ -1,77 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_extit.h -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file contains all the functions prototypes for the -* EXTIT software library. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __75x_EXTIT_H -#define __75x_EXTIT_H - -/* Includes ------------------------------------------------------------------*/ -#include "75x_map.h" - -/* Exported types ------------------------------------------------------------*/ -/* EXTIT Trigger enumeration */ -typedef enum -{ - EXTIT_ITTrigger_Falling = 1, - EXTIT_ITTrigger_Rising -}EXTITTrigger_TypeDef; - -/* EXTIT Init Structure definition */ -typedef struct -{ - u32 EXTIT_ITLine; - EXTITTrigger_TypeDef EXTIT_ITTrigger; - FunctionalState EXTIT_ITLineCmd; -}EXTIT_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ -/* EXTIT Lines */ -#define EXTIT_ITLineNone 0x0000 /* No interrupt selected */ -#define EXTIT_ITLine0 0x0001 /* External interrupt line 0 */ -#define EXTIT_ITLine1 0x0002 /* External interrupt line 1 */ -#define EXTIT_ITLine2 0x0004 /* External interrupt line 2 */ -#define EXTIT_ITLine3 0x0008 /* External interrupt line 3 */ -#define EXTIT_ITLine4 0x0010 /* External interrupt line 4 */ -#define EXTIT_ITLine5 0x0020 /* External interrupt line 5 */ -#define EXTIT_ITLine6 0x0040 /* External interrupt line 6 */ -#define EXTIT_ITLine7 0x0080 /* External interrupt line 7 */ -#define EXTIT_ITLine8 0x0100 /* External interrupt line 8 */ -#define EXTIT_ITLine9 0x0200 /* External interrupt line 9 */ -#define EXTIT_ITLine10 0x0400 /* External interrupt line 10 */ -#define EXTIT_ITLine11 0x0800 /* External interrupt line 11 */ -#define EXTIT_ITLine12 0x1000 /* External interrupt line 12 */ -#define EXTIT_ITLine13 0x2000 /* External interrupt line 13 */ -#define EXTIT_ITLine14 0x4000 /* External interrupt line 14 */ -#define EXTIT_ITLine15 0x8000 /* External interrupt line 15 */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -void EXTIT_DeInit(void); -void EXTIT_Init(EXTIT_InitTypeDef* EXTIT_InitStruct); -void EXTIT_StructInit(EXTIT_InitTypeDef* EXTIT_InitStruct); -void EXTIT_GenerateSWInterrupt(u16 EXTIT_ITLine); -FlagStatus EXTIT_GetFlagStatus(u16 EXTIT_ITLine); -void EXTIT_ClearFlag(u16 EXTIT_ITLine); -ITStatus EXTIT_GetITStatus(u16 EXTIT_ITLine); -void EXTIT_ClearITPendingBit(u16 EXTIT_ITLine); - -#endif /* __75x_EXTIT_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_gpio.h b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_gpio.h deleted file mode 100644 index 53aad69ca..000000000 --- a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_gpio.h +++ /dev/null @@ -1,120 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_gpio.h -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file contains all the functions prototypes for the -* GPIO software library. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __75x_GPIO_H -#define __75x_GPIO_H - -/* Includes ------------------------------------------------------------------*/ -#include "75x_map.h" - -/* Exported types ------------------------------------------------------------*/ -/* Configuration Mode enumeration */ -typedef enum -{ GPIO_Mode_AIN = 1, - GPIO_Mode_IN_FLOATING, - GPIO_Mode_IPD, - GPIO_Mode_IPU, - GPIO_Mode_Out_OD, - GPIO_Mode_Out_PP, - GPIO_Mode_AF_OD, - GPIO_Mode_AF_PP -}GPIOMode_TypeDef; - -/* GPIO Init structure definition */ -typedef struct -{ - u32 GPIO_Pin; - GPIOMode_TypeDef GPIO_Mode; -}GPIO_InitTypeDef; - -/* Bit_SET and Bit_RESET enumeration */ -typedef enum -{ Bit_RESET = 0, - Bit_SET -}BitAction; - - -/* Exported constants --------------------------------------------------------*/ -/* GPIO pins define */ -#define GPIO_Pin_None 0x00000000 /* No pin selected */ -#define GPIO_Pin_0 0x00000001 /* Pin 0 selected */ -#define GPIO_Pin_1 0x00000002 /* Pin 1 selected */ -#define GPIO_Pin_2 0x00000004 /* Pin 2 selected */ -#define GPIO_Pin_3 0x00000008 /* Pin 3 selected */ -#define GPIO_Pin_4 0x00000010 /* Pin 4 selected */ -#define GPIO_Pin_5 0x00000020 /* Pin 5 selected */ -#define GPIO_Pin_6 0x00000040 /* Pin 6 selected */ -#define GPIO_Pin_7 0x00000080 /* Pin 7 selected */ -#define GPIO_Pin_8 0x00000100 /* Pin 8 selected */ -#define GPIO_Pin_9 0x00000200 /* Pin 9 selected */ -#define GPIO_Pin_10 0x00000400 /* Pin 10 selected */ -#define GPIO_Pin_11 0x00000800 /* Pin 11 selected */ -#define GPIO_Pin_12 0x00001000 /* Pin 12 selected */ -#define GPIO_Pin_13 0x00002000 /* Pin 13 selected */ -#define GPIO_Pin_14 0x00004000 /* Pin 14 selected */ -#define GPIO_Pin_15 0x00008000 /* Pin 15 selected */ -#define GPIO_Pin_16 0x00010000 /* Pin 16 selected */ -#define GPIO_Pin_17 0x00020000 /* Pin 17 selected */ -#define GPIO_Pin_18 0x00040000 /* Pin 18 selected */ -#define GPIO_Pin_19 0x00080000 /* Pin 19 selected */ -#define GPIO_Pin_20 0x00100000 /* Pin 20 selected */ -#define GPIO_Pin_21 0x00200000 /* Pin 21 selected */ -#define GPIO_Pin_22 0x00400000 /* Pin 22 selected */ -#define GPIO_Pin_23 0x00800000 /* Pin 23 selected */ -#define GPIO_Pin_24 0x01000000 /* Pin 24 selected */ -#define GPIO_Pin_25 0x02000000 /* Pin 25 selected */ -#define GPIO_Pin_26 0x04000000 /* Pin 26 selected */ -#define GPIO_Pin_27 0x08000000 /* Pin 27 selected */ -#define GPIO_Pin_28 0x10000000 /* Pin 28 selected */ -#define GPIO_Pin_29 0x20000000 /* Pin 29 selected */ -#define GPIO_Pin_30 0x40000000 /* Pin 30 selected */ -#define GPIO_Pin_31 0x80000000 /* Pin 31 selected */ -#define GPIO_Pin_All 0xFFFFFFFF /* All pins selected */ - -/* GPIO Remap define */ -#define GPIO_Remap_SMI_CS3_EN 0x23 /* SMI CS3 Enable */ -#define GPIO_Remap_SMI_CS2_EN 0x22 /* SMI CS2 Enable */ -#define GPIO_Remap_SMI_CS1_EN 0x21 /* SMI CS1 Enable */ -#define GPIO_Remap_SMI_EN 0x20 /* SMI Enable */ -#define GPIO_Remap_DBGOFF 0x45 /* JTAG Disable */ -#define GPIO_Remap_UART1 0x44 /* UART1 Alternate Function mapping */ -#define GPIO_Remap_UART2 0x43 /* UART2 Alternate Function mapping */ -#define GPIO_Remap_SSP1 0x42 /* SSP1 Alternate Function mapping */ -#define GPIO_Remap_TIM2 0x41 /* TIM2 Alternate Function mapping */ -#define GPIO_Remap_TIM0 0x40 /* TIM0 Alternate Function mapping */ - - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -void GPIO_DeInit(GPIO_TypeDef* GPIOx); -void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); -void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); -u32 GPIO_Read(GPIO_TypeDef* GPIOx); -u8 GPIO_ReadBit(GPIO_TypeDef* GPIOx, u32 GPIO_Pin); -void GPIO_Write(GPIO_TypeDef* GPIOx, u32 PortVal); -void GPIO_WriteBit(GPIO_TypeDef* GPIOx,u32 GPIO_Pin, BitAction BitVal); -void GPIO_PinMaskConfig(GPIO_TypeDef* GPIOx, u32 GPIO_Pin, FunctionalState NewState); -u32 GPIO_GetPortMask(GPIO_TypeDef* GPIOx); -void GPIO_PinRemapConfig(u16 GPIO_Remap, FunctionalState NewState); - -#endif /* __75x_GPIO_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_i2c.h b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_i2c.h deleted file mode 100644 index 0e3a8c511..000000000 --- a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_i2c.h +++ /dev/null @@ -1,115 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_i2c.h -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file contains all the functions prototypes for the -* I2C software library. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion ------------------------------------ */ -#ifndef __75x_I2C_H -#define __75x_I2C_H - -/* Includes ----------------------------------------------------------------- */ -#include "75x_map.h" - -/* Exported types ----------------------------------------------------------- */ -/* I2C Init structure definition */ -typedef struct -{ - u32 I2C_CLKSpeed; - u16 I2C_OwnAddress; - u8 I2C_GeneralCall; - u8 I2C_Ack; -}I2C_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ -/* General Call */ -#define I2C_GeneralCall_Enable 0x10 -#define I2C_GeneralCall_Disable 0xEF - -/* Acknowledgement */ -#define I2C_Ack_Enable 0x04 -#define I2C_Ack_Disable 0xFB - -/* I2C Flags */ -#define I2C_FLAG_SB 0x0001 -#define I2C_FLAG_M_SL 0x0002 -#define I2C_FLAG_ADSL 0x0004 -#define I2C_FLAG_BTF 0x0008 -#define I2C_FLAG_BUSY 0x0010 -#define I2C_FLAG_TRA 0x0020 -#define I2C_FLAG_ADD10 0x0040 -#define I2C_FLAG_EVF 0x0080 -#define I2C_FLAG_GCAL 0x0100 -#define I2C_FLAG_BERR 0x0200 -#define I2C_FLAG_ARLO 0x0400 -#define I2C_FLAG_STOPF 0x0800 -#define I2C_FLAG_AF 0x1000 -#define I2C_FLAG_ENDAD 0x2000 -#define I2C_FLAG_ACK 0x4000 - -/* I2C Events */ -#define I2C_EVENT_SLAVE_ADDRESS_MATCHED ( I2C_FLAG_EVF | I2C_FLAG_BUSY |I2C_FLAG_ADSL) -#define I2C_EVENT_SLAVE_BYTE_RECEIVED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_BTF ) -#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_BTF | I2C_FLAG_TRA ) -#define I2C_EVENT_MASTER_MODE_SELECT ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL | I2C_FLAG_SB ) -#define I2C_EVENT_MASTER_MODE_SELECTED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL | I2C_FLAG_ENDAD ) -#define I2C_EVENT_MASTER_BYTE_RECEIVED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL | I2C_FLAG_BTF ) -#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL | I2C_FLAG_BTF | I2C_FLAG_TRA ) -#define I2C_EVENT_MASTER_MODE_ADDRESS10 ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL |I2C_FLAG_ADD10 ) -#define I2C_EVENT_SLAVE_STOP_DETECTED I2C_FLAG_STOPF -#define I2C_EVENT_SLAVE_ACK_FAILURE ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_BTF | I2C_FLAG_TRA | I2C_FLAG_AF) - -#define I2C_BUS_ERROR_DETECTED I2C_FLAG_BERR -#define I2C_ARBITRATION_LOST I2C_FLAG_ARLO -#define I2C_SLAVE_GENERAL_CALL (I2C_FLAG_BUSY | I2C_FLAG_GCAL) - -/* Master/Receiver Mode */ -#define I2C_MODE_TRANSMITTER 0x00 -#define I2C_MODE_RECEIVER 0x01 - -/* I2C Registers offset */ -#define I2C_CR 0x00 -#define I2C_SR1 0x04 -#define I2C_SR2 0x08 -#define I2C_CCR 0x0C -#define I2C_OAR1 0x10 -#define I2C_OAR2 0x14 -#define I2C_DR 0x18 -#define I2C_ECCR 0x1C - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -void I2C_DeInit(void); -void I2C_Init(I2C_InitTypeDef* I2C_InitStruct); -void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); -void I2C_Cmd(FunctionalState NewState); -void I2C_GenerateSTART(FunctionalState NewState); -void I2C_GenerateSTOP(FunctionalState NewState); -void I2C_AcknowledgeConfig(FunctionalState NewState); -void I2C_ITConfig(FunctionalState NewState); -u16 I2C_GetLastEvent(void); -ErrorStatus I2C_CheckEvent(u16 I2C_EVENT); -void I2C_SendData(u8 Data); -u8 I2C_ReceiveData(void); -void I2C_Send7bitAddress(u8 Address, u8 Direction); -u8 I2C_ReadRegister(u8 I2C_Register); -FlagStatus I2C_GetFlagStatus(u16 I2C_FLAG); -void I2C_ClearFlag(u16 I2C_FLAG, ...); - -#endif /* __75x_I2C_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_lib.h b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_lib.h deleted file mode 100644 index 8048ffcc3..000000000 --- a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_lib.h +++ /dev/null @@ -1,103 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_lib.h -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file includes the peripherals header files in the -* user application. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __75x_LIB_H -#define __75x_LIB_H - -/* Includes ------------------------------------------------------------------*/ -#include "75x_map.h" - -#ifdef _SMI - #include "75x_smi.h" -#endif /*_SMI */ - -#ifdef _CFG - #include "75x_cfg.h" -#endif /*_CFG*/ - -#ifdef _MRCC - #include "75x_mrcc.h" -#endif /*_MRCC */ - -#ifdef _ADC - #include "75x_adc.h" -#endif /*_ADC */ - -#ifdef _TB - #include "75x_tb.h" -#endif /*_TB */ - -#ifdef _TIM - #include "75x_tim.h" -#endif /*_TIM */ - -#ifdef _PWM - #include "75x_pwm.h" -#endif /*_PWM */ - -#ifdef _WDG - #include "75x_wdg.h" -#endif /*_WDG */ - -#ifdef _SSP - #include "75x_ssp.h" -#endif /*_SSP */ - -#ifdef _CAN - #include "75x_can.h" -#endif /*_CAN */ - -#ifdef _I2C - #include "75x_i2c.h" -#endif /*_I2C */ - -#ifdef _UART - #include "75x_uart.h" -#endif /*_UART */ - -#ifdef _GPIO - #include "75x_gpio.h" -#endif /*_GPIO */ - -#ifdef _DMA - #include "75x_dma.h" -#endif /*_DMA */ - -#ifdef _RTC - #include "75x_rtc.h" -#endif /*_RTC */ - -#ifdef _EXTIT - #include "75x_extit.h" -#endif /*_EXTIT */ - -#ifdef _EIC - #include "75x_eic.h" -#endif /*_EIC */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -void debug(void); - -#endif /* __75x_LIB_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_map.h b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_map.h deleted file mode 100644 index d000f1b45..000000000 --- a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_map.h +++ /dev/null @@ -1,697 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_map.h -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file contains all the peripheral register's definitions -* and memory mapping. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __75x_MAP_H -#define __75x_MAP_H - -#ifndef EXT - #define EXT extern -#endif /* EXT */ - -/* Includes ------------------------------------------------------------------*/ -#include "75x_conf.h" -#include "75x_type.h" - -/* Exported types ------------------------------------------------------------*/ -/******************************************************************************/ -/* IP registers structures */ -/******************************************************************************/ - -/*------------------------ Analog to Digital Converter -----------------------*/ -typedef struct -{ - vu16 CLR0; - u16 EMPTY1; - vu16 CLR1; - u16 EMPTY2; - vu16 CLR2; - u16 EMPTY3; - vu16 CLR3; - u16 EMPTY4; - vu16 CLR4; - u16 EMPTY5; - vu16 TRA0; - u16 EMPTY6; - vu16 TRA1; - u16 EMPTY7; - vu16 TRA2; - u16 EMPTY8; - vu16 TRA3; - u16 EMPTY9; - vu16 TRB0; - u16 EMPTY10; - vu16 TRB1; - u16 EMPTY11; - vu16 TRB2; - u16 EMPTY12; - vu16 TRB3; - u16 EMPTY13; - vu16 DMAR; - u16 EMPTY14[7]; - vu16 DMAE; - u16 EMPTY15 ; - vu16 PBR; - u16 EMPTY16; - vu16 IMR; - u16 EMPTY17; - vu16 D0; - u16 EMPTY18; - vu16 D1; - u16 EMPTY19; - vu16 D2; - u16 EMPTY20; - vu16 D3; - u16 EMPTY21; - vu16 D4; - u16 EMPTY22; - vu16 D5; - u16 EMPTY23; - vu16 D6; - u16 EMPTY24; - vu16 D7; - u16 EMPTY25; - vu16 D8; - u16 EMPTY26; - vu16 D9; - u16 EMPTY27; - vu16 D10; - u16 EMPTY28; - vu16 D11; - u16 EMPTY29; - vu16 D12; - u16 EMPTY30; - vu16 D13; - u16 EMPTY31; - vu16 D14; - u16 EMPTY32; - vu16 D15; - u16 EMPTY33; -} ADC_TypeDef; - -/*------------------------ Controller Area Network ---------------------------*/ -typedef struct -{ - vu16 CRR; - u16 EMPTY1; - vu16 CMR; - u16 EMPTY2; - vu16 M1R; - u16 EMPTY3; - vu16 M2R; - u16 EMPTY4; - vu16 A1R; - u16 EMPTY5; - vu16 A2R; - u16 EMPTY6; - vu16 MCR; - u16 EMPTY7; - vu16 DA1R; - u16 EMPTY8; - vu16 DA2R; - u16 EMPTY9; - vu16 DB1R; - u16 EMPTY10; - vu16 DB2R; - u16 EMPTY11[27]; -} CAN_MsgObj_TypeDef; - -typedef struct -{ - vu16 CR; - u16 EMPTY1; - vu16 SR; - u16 EMPTY2; - vu16 ERR; - u16 EMPTY3; - vu16 BTR; - u16 EMPTY4; - vu16 IDR; - u16 EMPTY5; - vu16 TESTR; - u16 EMPTY6; - vu16 BRPR; - u16 EMPTY7[3]; - CAN_MsgObj_TypeDef sMsgObj[2]; - u16 EMPTY8[16]; - vu16 TXR1R; - u16 EMPTY9; - vu16 TXR2R; - u16 EMPTY10[13]; - vu16 ND1R; - u16 EMPTY11; - vu16 ND2R; - u16 EMPTY12[13]; - vu16 IP1R; - u16 EMPTY13; - vu16 IP2R; - u16 EMPTY14[13]; - vu16 MV1R; - u16 EMPTY15; - vu16 MV2R; - u16 EMPTY16; -} CAN_TypeDef; - -/*--------------------------- Configuration Register -------------------------*/ -typedef struct -{ - vu32 GLCONF; -} CFG_TypeDef; - -/*-------------------------------- DMA Controller ----------------------------*/ -typedef struct -{ - vu16 SOURCEL; - u16 EMPTY1; - vu16 SOURCEH; - u16 EMPTY2; - vu16 DESTL; - u16 EMPTY3; - vu16 DESTH; - u16 EMPTY4; - vu16 MAX; - u16 EMPTY5; - vu16 CTRL; - u16 EMPTY6; - vuc16 SOCURRH; - u16 EMPTY7; - vuc16 SOCURRL; - u16 EMPTY8; - vuc16 DECURRH; - u16 EMPTY9; - vuc16 DECURRL; - u16 EMPTY10; - vuc16 TCNT; - u16 EMPTY11; - vu16 LUBUFF; - u16 EMPTY12; -} DMA_Stream_TypeDef; - -typedef struct -{ - vu16 MASK; - u16 EMPTY4; - vu16 CLR; - u16 EMPTY5; - vuc16 STATUS; - u16 EMPTY6; - vu16 LAST; - u16 EMPTY7; -} DMA_TypeDef; - -/*----------------------- Enhanced Interrupt Controller ----------------------*/ -typedef struct -{ - vu32 ICR; - vuc32 CICR; - vu32 CIPR; - u32 EMPTY1; - vu32 FIER; - vu32 FIPR; - vu32 IVR; - vu32 FIR; - vu32 IER; - u32 EMPTY2[7]; - vu32 IPR; - u32 EMPTY3[7]; - vu32 SIRn[32]; -} EIC_TypeDef; - -/*------------------------- External Interrupt Controller --------------------*/ -typedef struct -{ - vu32 MR; - vu32 TSR; - vu32 SWIR; - vu32 PR; -} EXTIT_TypeDef; - -/*-------------------------- General Purpose IO ports ------------------------*/ -typedef struct -{ - vu32 PC0; - vu32 PC1; - vu32 PC2; - vu32 PD; - vu32 PM; -} GPIO_TypeDef; - -typedef struct -{ - vu32 REMAP0R; - vu32 REMAP1R; -} GPIOREMAP_TypeDef; - -/*--------------------------------- I2C interface ----------------------------*/ -typedef struct -{ - vu8 CR; - u8 EMPTY1[3]; - vu8 SR1; - u8 EMPTY2[3]; - vu8 SR2; - u8 EMPTY3[3]; - vu8 CCR; - u8 EMPTY4[3]; - vu8 OAR1; - u8 EMPTY5[3]; - vu8 OAR2; - u8 EMPTY6[3]; - vu8 DR; - u8 EMPTY7[3]; - vu8 ECCR; - u8 EMPTY8[3]; -} I2C_TypeDef; - -/*---------------------------- Power, Reset and Clocks -----------------------*/ -typedef struct -{ - vu32 CLKCTL; - vu32 RFSR; - vu32 PWRCTRL; - u32 EMPTY1; - vu32 PCLKEN; - vu32 PSWRES; - u32 EMPTY2[2]; - vu32 BKP0; - vu32 BKP1; -} MRCC_TypeDef; - -/*-------------------------------- Real Time Clock ---------------------------*/ -typedef struct -{ - vu16 CRH; - u16 EMPTY; - vu16 CRL; - u16 EMPTY1; - vu16 PRLH; - u16 EMPTY2; - vu16 PRLL; - u16 EMPTY3; - vu16 DIVH; - u16 EMPTY4; - vu16 DIVL; - u16 EMPTY5; - vu16 CNTH; - u16 EMPTY6; - vu16 CNTL; - u16 EMPTY7; - vu16 ALRH; - u16 EMPTY8; - vu16 ALRL; - u16 EMPTY9; -} RTC_TypeDef; - -/*---------------------------- Serial Memory Interface -----------------------*/ -typedef struct -{ - vu32 CR1; - vu32 CR2; - vu32 SR; - vu32 TR; - vuc32 RR; -} SMI_TypeDef; - -/*--------------------------------- Timer Base -------------------------------*/ -typedef struct -{ - vu16 CR; - u16 EMPTY1; - vu16 SCR; - u16 EMPTY2; - vu16 IMCR; - u16 EMPTY3[7]; - vu16 RSR; - u16 EMPTY4; - vu16 RER; - u16 EMPTY5; - vu16 ISR; - u16 EMPTY6; - vu16 CNT; - u16 EMPTY7; - vu16 PSC; - u16 EMPTY8[3]; - vu16 ARR; - u16 EMPTY9[13]; - vu16 ICR1; - u16 EMPTY10; -} TB_TypeDef; - -/*------------------------------------ TIM -----------------------------------*/ -typedef struct -{ - vu16 CR; - u16 EMPTY1; - vu16 SCR; - u16 EMPTY2; - vu16 IMCR; - u16 EMPTY3; - vu16 OMR1; - u16 EMPTY4[5]; - vu16 RSR; - u16 EMPTY5; - vu16 RER; - u16 EMPTY6; - vu16 ISR; - u16 EMPTY7; - vu16 CNT; - u16 EMPTY8; - vu16 PSC; - u16 EMPTY9[3]; - vu16 ARR; - u16 EMPTY10; - vu16 OCR1; - u16 EMPTY11; - vu16 OCR2; - u16 EMPTY12[9]; - vu16 ICR1; - u16 EMPTY13; - vu16 ICR2; - u16 EMPTY14[9]; - vu16 DMAB; - u16 EMPTY15; -} TIM_TypeDef; - -/*------------------------------------ PWM -----------------------------------*/ -typedef struct -{ - vu16 CR; - u16 EMPTY1; - vu16 SCR; - u16 EMPTY2[3]; - vu16 OMR1; - u16 EMPTY3; - vu16 OMR2; - u16 EMPTY4[3]; - vu16 RSR; - u16 EMPTY5; - vu16 RER; - u16 EMPTY6; - vu16 ISR; - u16 EMPTY7; - vu16 CNT; - u16 EMPTY8; - vu16 PSC; - u16 EMPTY9; - vu16 RCR; - u16 EMPTY10; - vu16 ARR; - u16 EMPTY11; - vu16 OCR1; - u16 EMPTY12; - vu16 OCR2; - u16 EMPTY13; - vu16 OCR3; - u16 EMPTY14[15]; - vu16 DTR; - u16 EMPTY15; - vu16 DMAB; - u16 EMPTY16; -} PWM_TypeDef; - -/*----------------------- Synchronous Serial Peripheral ----------------------*/ -typedef struct -{ - vu32 CR0; - vu32 CR1; - vu32 DR; - vu32 SR; - vu32 PR; - vu32 IMSCR; - vu32 RISR; - vu32 MISR; - vu32 ICR; - vu32 DMACR; -} SSP_TypeDef; - -/*---------------- Universal Asynchronous Receiver Transmitter ---------------*/ -typedef struct -{ - vu16 DR; - u16 EMPTY; - vu16 RSR; - u16 EMPTY1[9]; - vu16 FR; - u16 EMPTY2; - vu16 BKR; - u16 EMPTY3[3]; - vu16 IBRD; - u16 EMPTY4; - vu16 FBRD; - u16 EMPTY5; - vu16 LCR; - u16 EMPTY6; - vu16 CR; - u16 EMPTY7; - vu16 IFLS; - u16 EMPTY8; - vu16 IMSC; - u16 EMPTY9; - vu16 RIS; - u16 EMPTY10; - vu16 MIS; - u16 EMPTY11; - vu16 ICR; - u16 EMPTY12; - vu16 DMACR; - u16 EMPTY13; -} UART_TypeDef; - -/*---------------------------------- WATCHDOG --------------------------------*/ -typedef struct -{ - vu16 CR; - u16 EMPTY1; - vu16 PR; - u16 EMPTY2; - vu16 VR; - u16 EMPTY3; - vu16 CNT; - u16 EMPTY4; - vu16 SR; - u16 EMPTY5; - vu16 MR; - u16 EMPTY6; - vu16 KR; - u16 EMPTY7; -} WDG_TypeDef; - -/******************************************************************************* -* Peripherals' Base addresses -*******************************************************************************/ - -#define SRAM_BASE 0x40000000 - -#define CONFIG_BASE 0x60000000 - -#define SMIR_BASE 0x90000000 - -#define PERIPH_BASE 0xFFFF0000 - -#define CFG_BASE (CONFIG_BASE + 0x0010) -#define MRCC_BASE (CONFIG_BASE + 0x0020) -#define ADC_BASE (PERIPH_BASE + 0x8400) -#define TB_BASE (PERIPH_BASE + 0x8800) -#define TIM0_BASE (PERIPH_BASE + 0x8C00) -#define TIM1_BASE (PERIPH_BASE + 0x9000) -#define TIM2_BASE (PERIPH_BASE + 0x9400) -#define PWM_BASE (PERIPH_BASE + 0x9800) -#define WDG_BASE (PERIPH_BASE + 0xB000) -#define SSP0_BASE (PERIPH_BASE + 0xB800) -#define SSP1_BASE (PERIPH_BASE + 0xBC00) -#define CAN_BASE (PERIPH_BASE + 0xC400) -#define I2C_BASE (PERIPH_BASE + 0xCC00) -#define UART0_BASE (PERIPH_BASE + 0xD400) -#define UART1_BASE (PERIPH_BASE + 0xD800) -#define UART2_BASE (PERIPH_BASE + 0xDC00) -#define GPIO0_BASE (PERIPH_BASE + 0xE400) -#define GPIOREMAP_BASE (PERIPH_BASE + 0xE420) -#define GPIO1_BASE (PERIPH_BASE + 0xE440) -#define GPIO2_BASE (PERIPH_BASE + 0xE480) -#define DMA_BASE (PERIPH_BASE + 0xECF0) -#define DMA_Stream0_BASE (PERIPH_BASE + 0xEC00) -#define DMA_Stream1_BASE (PERIPH_BASE + 0xEC40) -#define DMA_Stream2_BASE (PERIPH_BASE + 0xEC80) -#define DMA_Stream3_BASE (PERIPH_BASE + 0xECC0) -#define RTC_BASE (PERIPH_BASE + 0xF000) -#define EXTIT_BASE (PERIPH_BASE + 0xF400) -#define EIC_BASE (PERIPH_BASE + 0xF800) - -/******************************************************************************* - IPs' declaration -*******************************************************************************/ - -/*------------------- Non Debug Mode -----------------------------------------*/ - -#ifndef DEBUG - #define SMI ((SMI_TypeDef *) SMIR_BASE) - #define CFG ((CFG_TypeDef *) CFG_BASE) - #define MRCC ((MRCC_TypeDef *) MRCC_BASE) - #define ADC ((ADC_TypeDef *) ADC_BASE) - #define TB ((TB_TypeDef *) TB_BASE) - #define TIM0 ((TIM_TypeDef *) TIM0_BASE) - #define TIM1 ((TIM_TypeDef *) TIM1_BASE) - #define TIM2 ((TIM_TypeDef *) TIM2_BASE) - #define PWM ((PWM_TypeDef *) PWM_BASE) - #define WDG ((WDG_TypeDef *) WDG_BASE) - #define SSP0 ((SSP_TypeDef *) SSP0_BASE) - #define SSP1 ((SSP_TypeDef *) SSP1_BASE) - #define CAN ((CAN_TypeDef *) CAN_BASE) - #define I2C ((I2C_TypeDef *) I2C_BASE) - #define UART0 ((UART_TypeDef *) UART0_BASE) - #define UART1 ((UART_TypeDef *) UART1_BASE) - #define UART2 ((UART_TypeDef *) UART2_BASE) - #define GPIO0 ((GPIO_TypeDef *) GPIO0_BASE) - #define GPIOREMAP ((GPIOREMAP_TypeDef *) GPIOREMAP_BASE) - #define GPIO1 ((GPIO_TypeDef *) GPIO1_BASE) - #define GPIO2 ((GPIO_TypeDef *) GPIO2_BASE) - #define DMA ((DMA_TypeDef *) DMA_BASE) - #define DMA_Stream0 ((DMA_Stream_TypeDef *) DMA_Stream0_BASE) - #define DMA_Stream1 ((DMA_Stream_TypeDef *) DMA_Stream1_BASE) - #define DMA_Stream2 ((DMA_Stream_TypeDef *) DMA_Stream2_BASE) - #define DMA_Stream3 ((DMA_Stream_TypeDef *) DMA_Stream3_BASE) - #define RTC ((RTC_TypeDef *) RTC_BASE) - #define EXTIT ((EXTIT_TypeDef *) EXTIT_BASE) - #define EIC ((EIC_TypeDef *) EIC_BASE) -#else /* DEBUG */ - #ifdef _SMI - EXT SMI_TypeDef *SMI; - #endif /*_SMI */ - - #ifdef _CFG - EXT CFG_TypeDef *CFG; - #endif /*_CFG */ - - #ifdef _MRCC - EXT MRCC_TypeDef *MRCC; - #endif /*_MRCC */ - - #ifdef _ADC - EXT ADC_TypeDef *ADC; - #endif /*_ADC */ - - #ifdef _TB - EXT TB_TypeDef *TB; - #endif /*_TB */ - - #ifdef _TIM0 - EXT TIM_TypeDef *TIM0; - #endif /*_TIM0 */ - - #ifdef _TIM1 - EXT TIM_TypeDef *TIM1; - #endif /*_TIM1 */ - - #ifdef _TIM2 - EXT TIM_TypeDef *TIM2; - #endif /*_TIM2 */ - - #ifdef _PWM - EXT PWM_TypeDef *PWM; - #endif /*_PWM */ - - #ifdef _WDG - EXT WDG_TypeDef *WDG; - #endif /*_WDG */ - - #ifdef _SSP0 - EXT SSP_TypeDef *SSP0; - #endif /*_SSP0 */ - - #ifdef _SSP1 - EXT SSP_TypeDef *SSP1; - #endif /*_SSP1 */ - - #ifdef _CAN - EXT CAN_TypeDef *CAN; - #endif /*_CAN */ - - #ifdef _I2C - EXT I2C_TypeDef *I2C; - #endif /*_I2C */ - - #ifdef _UART0 - EXT UART_TypeDef *UART0; - #endif /*_UART0 */ - - #ifdef _UART1 - EXT UART_TypeDef *UART1; - #endif /*_UART1 */ - - #ifdef _UART2 - EXT UART_TypeDef *UART2; - #endif /*_UART2 */ - - #ifdef _GPIO0 - EXT GPIO_TypeDef *GPIO0; - #endif /*_GPIO0 */ - - #ifdef _GPIOREMAP - EXT GPIOREMAP_TypeDef *GPIOREMAP; - #endif /*_GPIOREMAP */ - - #ifdef _GPIO1 - EXT GPIO_TypeDef *GPIO1; - #endif /*_GPIO1 */ - - #ifdef _GPIO2 - EXT GPIO_TypeDef *GPIO2; - #endif /*_GPIO2 */ - - #ifdef _DMA - EXT DMA_TypeDef *DMA; - #endif /*_DMA */ - - #ifdef _DMA_Stream0 - EXT DMA_Stream_TypeDef *DMA_Stream0; - #endif /*_DMA_Stream0 */ - - #ifdef _DMA_Stream1 - EXT DMA_Stream_TypeDef *DMA_Stream1; - #endif /*_DMA_Stream1 */ - - #ifdef _DMA_Stream2 - EXT DMA_Stream_TypeDef *DMA_Stream2; - #endif /*_DMA_Stream2 */ - - #ifdef _DMA_Stream3 - EXT DMA_Stream_TypeDef *DMA_Stream3; - #endif /*_DMA_Stream3 */ - - #ifdef _RTC - EXT RTC_TypeDef *RTC; - #endif /*_RTC */ - - #ifdef _EXTIT - EXT EXTIT_TypeDef *EXTIT; - #endif /*_EXTIT */ - - #ifdef _EIC - EXT EIC_TypeDef *EIC; - #endif /*_EIC */ - -#endif /* DEBUG */ - -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -#endif /* __75x_MAP_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_mrcc.h b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_mrcc.h deleted file mode 100644 index 91c178429..000000000 --- a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_mrcc.h +++ /dev/null @@ -1,241 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_mrcc.h -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file contains all the functions prototypes for the -* MRCC software library. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __75x_MRCC_H -#define __75x_MRCC_H - -/* Includes ------------------------------------------------------------------*/ -#include "75x_map.h" - -/* Exported types ------------------------------------------------------------*/ -/* MRCC Buck-up registers */ -typedef enum -{ - MRCC_BKP0, - MRCC_BKP1 -}MRCC_BKPReg; - -typedef enum -{ - FREEOSC, - OSC4MPLL, - OSC4M, - CKRTC, - Disabled, - OSC4M_Div128, - LPOSC, - OSC32K, - Internal, - External, - ON, - OFF -}CLKSourceTypeDef; - - -typedef struct -{ - CLKSourceTypeDef CKSYS_Source; /* FREEOSC, OSC4MPLL, OSC4M, CKRTC */ - CLKSourceTypeDef CKRTC_Source; /* Disabled, OSC4M_Div128, OSC32K, LPOSC */ - CLKSourceTypeDef CKUSB_Source; /* Disabled, Internal, External */ - CLKSourceTypeDef PLL_Status; /* ON, OFF */ - CLKSourceTypeDef OSC4M_Status; /* ON, OFF */ - CLKSourceTypeDef LPOSC_Status; /* ON, OFF */ - CLKSourceTypeDef OSC32K_Status; /* ON, OFF */ - u32 CKSYS_Frequency; - u32 HCLK_Frequency; - u32 CKTIM_Frequency; - u32 PCLK_Frequency; -}MRCC_ClocksTypeDef; - -/* Exported constants --------------------------------------------------------*/ -/* Oscillator divider by 2 */ -#define MRCC_XTDIV2_Disable 0xFFFF7FFF -#define MRCC_XTDIV2_Enable 0x00008000 - -/* System clock source */ -#define MRCC_CKSYS_FREEOSC 0x01 -#define MRCC_CKSYS_OSC4M 0x02 -#define MRCC_CKSYS_OSC4MPLL 0x03 -#define MRCC_CKSYS_RTC 0x04 - -/* PLL multiplication factors */ -#define MRCC_PLL_Disabled 0xFEFFFFFF -#define MRCC_PLL_NoChange 0x00000001 -#define MRCC_PLL_Mul_12 0x18000000 -#define MRCC_PLL_Mul_14 0x10000000 -#define MRCC_PLL_Mul_15 0x08000000 -#define MRCC_PLL_Mul_16 0x00000000 - -/* AHB clock source */ -#define MRCC_CKSYS_Div1 0x00000000 -#define MRCC_CKSYS_Div2 0x00000008 -#define MRCC_CKSYS_Div4 0x00000010 -#define MRCC_CKSYS_Div8 0x00000018 - -/* TIM clock source */ -#define MRCC_HCLK_Div1 0x00000000 -#define MRCC_HCLK_Div2 0x00000001 -#define MRCC_HCLK_Div4 0x00000002 -#define MRCC_HCLK_Div8 0x00000003 - -/* APB clock source */ -#define MRCC_CKTIM_Div1 0xFFFFFFFB -#define MRCC_CKTIM_Div2 0x00000004 - -/* RTC clock sources */ -#define MRCC_CKRTC_OSC4M_Div128 0x01000000 -#define MRCC_CKRTC_OSC32K 0x02000000 -#define MRCC_CKRTC_LPOSC 0x03000000 - -/* USB clock sources */ -#define MRCC_CKUSB_Internal 0xFFBFFFFF -#define MRCC_CKUSB_External 0x00400000 - -/* MRCC Interrupts */ -#define MRCC_IT_LOCK 0x40000000 -#define MRCC_IT_NCKD 0x00080000 - -/* Peripheral Clock */ -#define MRCC_Peripheral_ALL 0x1975623F -#define MRCC_Peripheral_EXTIT 0x10000000 -#define MRCC_Peripheral_RTC 0x08000000 -#define MRCC_Peripheral_GPIO 0x01000000 -#define MRCC_Peripheral_UART2 0x00400000 -#define MRCC_Peripheral_UART1 0x00200000 -#define MRCC_Peripheral_UART0 0x00100000 -#define MRCC_Peripheral_I2C 0x00040000 -#define MRCC_Peripheral_CAN 0x00010000 -#define MRCC_Peripheral_SSP1 0x00004000 -#define MRCC_Peripheral_SSP0 0x00002000 -#define MRCC_Peripheral_USB 0x00000200 -#define MRCC_Peripheral_PWM 0x00000020 -#define MRCC_Peripheral_TIM2 0x00000010 -#define MRCC_Peripheral_TIM1 0x00000008 -#define MRCC_Peripheral_TIM0 0x00000004 -#define MRCC_Peripheral_TB 0x00000002 -#define MRCC_Peripheral_ADC 0x00000001 - -/* Clock sources to measure theire frequency */ -#define MRCC_ClockSource_CKSYS 0x01 -#define MRCC_ClockSource_HCLK 0x02 -#define MRCC_ClockSource_PCLK 0x03 -#define MRCC_ClockSource_CKTIM 0x04 - -/* Low Power Debug Mode */ -#define MRCC_LPDM_Disable 0xFFFFFFF7 -#define MRCC_LPDM_Enable 0x00000008 - -/* WFI Mode parameters */ -#define MRCC_WFIParam_FLASHPowerDown 0x00000000 -#define MRCC_WFIParam_FLASHOn 0x00000010 -#define MRCC_WFIParam_FLASHOff 0x00004000 - -/* STOP Mode parameters */ -#define MRCC_STOPParam_Default 0x00000000 -#define MRCC_STOPParam_OSC4MOff 0x00008000 -#define MRCC_STOPParam_FLASHOff 0x00004000 -#define MRCC_STOPParam_MVREGOff 0x00002000 - -/* I/O Pins voltage range */ -#define MRCC_IOVoltageRange_5V 0xFFFEFFFF -#define MRCC_IOVoltageRange_3V3 0x00010000 - -/* Clock sources to output on MCO pin */ -#define MRCC_MCO_HCLK 0x00000000 -#define MRCC_MCO_PCLK 0x00000040 -#define MRCC_MCO_OSC4M 0x00000080 -#define MRCC_MCO_CKPLL2 0x000000C0 -#define MRCC_MCOPrescaler_1 0xFFFFFFDF -#define MRCC_MCOPrescaler_2 0x00000020 - -/* 4MHz main oscillator configuration */ -#define MRCC_OSC4M_Default 0xFFFCFFFF -#define MRCC_OSC4M_Disable 0x00020000 -#define MRCC_OSC4M_Bypass 0x00010000 - -/* OSC32K oscillator configuration */ -#define MRCC_OSC32K_Disable 0xDFFFFFFF -#define MRCC_OSC32K_Enable 0x20000000 -#define MRCC_OSC32KBypass_Disable 0xBFFFFFFF -#define MRCC_OSC32KBypass_Enable 0x40000000 - -/* LPOSC oscillator configuration */ -#define MRCC_LPOSC_Disable 0xEFFFFFFF -#define MRCC_LPOSC_Enable 0x10000000 - -/* RTC measurement configuration */ -#define MRCC_RTCM_Disable 0xFBFFFFFF -#define MRCC_RTCM_Enable 0x04000000 - -/* MRCC Flags */ -#define MRCC_FLAG_LOCK 0x3F -#define MRCC_FLAG_LOCKIF 0x3D -#define MRCC_FLAG_CKSEL 0x37 -#define MRCC_FLAG_CKOSCSEL 0x35 -#define MRCC_FLAG_NCKD 0x32 -#define MRCC_FLAG_SWR 0x5D -#define MRCC_FLAG_WDGR 0x5C -#define MRCC_FLAG_EXTR 0x5B -#define MRCC_FLAG_WKP 0x5A -#define MRCC_FLAG_STDB 0x59 -#define MRCC_FLAG_BCOUNT 0x58 -#define MRCC_FLAG_OSC32KRDY 0x7F -#define MRCC_FLAG_CKRTCOK 0x7B -#define MRCC_FLAG_LPDONE 0x67 -#define MRCC_FLAG_LP 0x60 - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -void MRCC_DeInit(void); -void MRCC_XTDIV2Config(u32 MRCC_XTDIV2); -ErrorStatus MRCC_CKSYSConfig(u32 MRCC_CKSYS, u32 MRCC_PLL); -void MRCC_HCLKConfig(u32 MRCC_HCLK); -void MRCC_CKTIMConfig(u32 MRCC_CKTIM); -void MRCC_PCLKConfig(u32 MRCC_PCLK); -ErrorStatus MRCC_CKRTCConfig(u32 MRCC_CKRTC); -ErrorStatus MRCC_CKUSBConfig(u32 MRCC_CKUSB); -void MRCC_ITConfig(u32 MRCC_IT, FunctionalState NewState); -void MRCC_PeripheralClockConfig(u32 MRCC_Peripheral, FunctionalState NewState); -void MRCC_PeripheralSWResetConfig(u32 MRCC_Peripheral, FunctionalState NewState); -void MRCC_GetClocksStatus(MRCC_ClocksTypeDef* MRCC_ClocksStatus); -void MRCC_LPMC_DBGConfig(u32 MRCC_LPDM); -void MRCC_EnterWFIMode(u32 MRCC_WFIParam); -void MRCC_EnterSTOPMode(u32 MRCC_STOPParam); -void MRCC_EnterSTANDBYMode(void); -void MRCC_GenerateSWReset(void); -void MRCC_WriteBackupRegister(MRCC_BKPReg MRCC_BKP, u32 Data); -u32 MRCC_ReadBackupRegister(MRCC_BKPReg MRCC_BKP); -void MRCC_IOVoltageRangeConfig(u32 MRCC_IOVoltageRange); -void MRCC_MCOConfig(u32 MRCC_MCO, u32 MCO_MCOPrescaler); -ErrorStatus MRCC_OSC4MConfig(u32 MRCC_OSC4M); -ErrorStatus MRCC_OSC32KConfig(u32 MRCC_OSC32K, u32 MRCC_OSC32KBypass); -ErrorStatus MRCC_LPOSCConfig(u32 MRCC_LPOSC); -void MRCC_RTCMConfig(u32 MRCC_RTCM); -void MRCC_SetBuilderCounter(u8 BuilderCounter); -u16 MRCC_GetCKSYSCounter(void); -FlagStatus MRCC_GetFlagStatus(u8 MRCC_FLAG); -void MRCC_ClearFlag(u8 MRCC_FLAG); -ITStatus MRCC_GetITStatus(u32 MRCC_IT); -void MRCC_ClearITPendingBit(u32 MRCC_IT); -ErrorStatus MRCC_WaitForOSC4MStartUp(void); - -#endif /* __75x_MRCC_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_pwm.h b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_pwm.h deleted file mode 100644 index 28edba9e8..000000000 --- a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_pwm.h +++ /dev/null @@ -1,215 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_pwm.h -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file contains all the functions prototypes for the -* PWM software library. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __75x_PWM_H -#define __75x_PWM_H - -/* Includes ------------------------------------------------------------------*/ -#include "75x_map.h" - -/* Exported types ------------------------------------------------------------*/ - -typedef struct -{ - u16 PWM_Mode; /* PWM Mode */ - u16 PWM_Prescaler; /* Prescaler value */ - u16 PWM_CounterMode; /* Counter mode: Up/Down, Edge aligned or center aligned */ - u16 PWM_Period; /* Period value */ - u16 PWM_Complementary; /* Complementary PWM selection */ - u16 PWM_OCState; /* Output compare off-state in Run mode */ - u16 PWM_OCNState; /* Complementary Output compare off-state in Run mode */ - u16 PWM_Channel; /* PWM Channel: 1, 2 or 3 */ - u16 PWM_Pulse1; /* PWM or OCM Channel 1 pulse length */ - u16 PWM_Pulse2; /* PWM or OCM Channel 2 pulse length */ - u16 PWM_Pulse3; /* PWM or OCM Channel 3 pulse length */ - u16 PWM_Polarity1; /* PWM, OCM or OPM Channel 1 polarity */ - u16 PWM_Polarity2; /* PWM or OCM Channel 2 polarity */ - u16 PWM_Polarity3; /* PWM or OCM Channel 3 polarity */ - u16 PWM_Polarity1N; /* PWM or OCM Channel 1N polarity */ - u16 PWM_Polarity2N; /* PWM or OCM Channel 2N polarity */ - u16 PWM_Polarity3N; /* PWM or OCM Channel 3N polarity */ - u16 PWM_DTRAccess; /* Enable or disable the configuration of DTR register parameters: - DeadTime, Emergency, LOCKLevel, OSSIState, OCState and OCNState */ - u16 PWM_DeadTime; /* Dead Time value */ - u16 PWM_Emergency; /* Emergency selection: Enable / Disable */ - u16 PWM_LOCKLevel; /* LOCK level */ - u16 PWM_OSSIState; /* Off-State Selection for Idle state */ - u8 PWM_RepetitionCounter; /* Repetition counter value */ -} PWM_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ -/* PWM modes */ -#define PWM_Mode_OCTiming 0x0001 -#define PWM_Mode_OCActive 0x0002 -#define PWM_Mode_OCInactive 0x0003 -#define PWM_Mode_OCToggle 0x0004 -#define PWM_Mode_PWM 0x0005 - -/* PWM Counter Mode */ -#define PWM_CounterMode_Up 0x0000 -#define PWM_CounterMode_Down 0x0010 -#define PWM_CounterMode_CenterAligned1 0x0020 -#define PWM_CounterMode_CenterAligned2 0x0040 -#define PWM_CounterMode_CenterAligned3 0x0060 - -/* PWM Channel */ -#define PWM_Channel_1 0x0001 -#define PWM_Channel_2 0x0002 -#define PWM_Channel_3 0x0004 -#define PWM_Channel_ALL 0x0007 - -/* PWM Polarity channel 1 */ -#define PWM_Polarity1_High 0x0001 -#define PWM_Polarity1_Low 0x0002 - -/* PWM Polarity channel 2 */ -#define PWM_Polarity2_High 0x0001 -#define PWM_Polarity2_Low 0x0002 - -/* PWM Polarity channel 3 */ -#define PWM_Polarity3_High 0x0001 -#define PWM_Polarity3_Low 0x0002 - -/* PWM Polarity channel 1N */ -#define PWM_Polarity1N_High 0x0001 -#define PWM_Polarity1N_Low 0x0002 - -/* PWM Polarity channel 2N */ -#define PWM_Polarity2N_High 0x0001 -#define PWM_Polarity2N_Low 0x0002 - -/* PWM Polarity channel 3N */ -#define PWM_Polarity3N_High 0x0001 -#define PWM_Polarity3N_Low 0x0002 - -/* PWM interrupt sources */ -#define PWM_IT_OC1 0x0100 -#define PWM_IT_OC2 0x0200 -#define PWM_IT_OC3 0x0400 -#define PWM_IT_Update 0x0001 -#define PWM_IT_GlobalUpdate 0x1001 -#define PWM_IT_Emergency 0x8000 - -/* PWM DMA sources */ -#define PWM_DMASource_OC1 0x0100 -#define PWM_DMASource_OC2 0x0200 -#define PWM_DMASource_OC3 0x0400 -#define PWM_DMASource_Update 0x0001 - -/* PWM DMA Base address */ -#define PWM_DMABase_CR 0x0000 -#define PWM_DMABase_SCR 0x0800 -#define PWM_DMABase_OMR1 0x1800 -#define PWM_DMABase_OMR2 0x2000 -#define PWM_DMABase_RSR 0x3000 -#define PWM_DMABase_RER 0x3800 -#define PWM_DMABase_ISR 0x4000 -#define PWM_DMABase_CNT 0x4800 -#define PWM_DMABase_PSC 0x5000 -#define PWM_DMABase_RCR 0x5800 -#define PWM_DMABase_ARR 0x6000 -#define PWM_DMABase_OCR1 0x6800 -#define PWM_DMABase_OCR2 0x7000 -#define PWM_DMABase_OCR3 0x7800 -#define PWM_DMABase_DTR 0xB800 - -/* PWM OCM state */ -#define PWM_OCRMState_Enable 0x0005 -#define PWM_OCRMState_Disable 0x0006 - -/* PWM Flags */ -#define PWM_FLAG_OC1 0x0100 -#define PWM_FLAG_OC2 0x0200 -#define PWM_FLAG_OC3 0x0400 -#define PWM_FLAG_Update 0x0001 -#define PWM_FLAG_Emergency 0x8000 - -/* PWM_ForcedAction */ -#define PWM_ForcedAction_Active 0x000A -#define PWM_ForcedAction_InActive 0x0008 - -/* PWM TRGO Mode */ -#define PWM_TRGOMode_Enable 0x0100 -#define PWM_TRGOMode_Update 0x0200 -#define PWM_TRGOMode_Reset 0x0000 -#define PWM_TRGOMode_OC 0x0300 - -/* PWM Complementary outputs Enable/Disable */ -#define PWM_Complementary_Disable 0x0001 -#define PWM_Complementary_Enable 0x0002 - -/* PWM DTR Access Enable/Disable */ -#define PWM_DTRAccess_Enable 0x0001 -#define PWM_DTRAccess_Disable 0x0002 - -/* PWM Emergency input Enable/Disable */ -#define PWM_Emergency_Disable 0x0000 -#define PWM_Emergency_Enable 0x1000 - -/* OC states */ -#define PWM_OCNState_Disable 0x0001 -#define PWM_OCNState_Enable 0x0002 -#define PWM_OCNState_OffState 0x0003 - -/* OCN states */ -#define PWM_OCState_Disable 0x0004 -#define PWM_OCState_Enable 0x0005 -#define PWM_OCState_OffState 0x0006 - -/* PWM LOCK level */ -#define PWM_LOCKLevel_1 0x0400 -#define PWM_LOCKLevel_2 0x0800 -#define PWM_LOCKLevel_3 0x0C00 -#define PWM_LOCKLevel_OFF 0x0000 - -/* Off State selection for Idle state */ -#define PWM_OSSIState_Disable 0x0000 -#define PWM_OSSIState_Enable 0x2000 - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -void PWM_DeInit(void); -void PWM_Init(PWM_InitTypeDef* PWM_InitStruct); -void PWM_StructInit(PWM_InitTypeDef *PWM_InitStruct); -void PWM_Cmd(FunctionalState Newstate); -void PWM_CtrlPWMOutputs(FunctionalState Newstate); -void PWM_ITConfig(u16 PWM_IT, FunctionalState Newstate); -void PWM_DMAConfig(u16 PWM_DMASources, u16 PWM_OCRMState, u16 PWM_DMABase); -void PWM_DMACmd(u16 PWM_DMASources, FunctionalState Newstate); -void PWM_SetPrescaler(u16 Prescaler); -void PWM_SetPeriod(u16 Period); -void PWM_SetPulse(u16 PWM_Channel, u16 Pulse); -void PWM_SetPulse1(u16 Pulse); -void PWM_SetPulse2(u16 Pulse); -void PWM_SetPulse3(u16 Pulse); -void PWM_DebugCmd(FunctionalState Newstate); -void PWM_CounterModeConfig(u16 PWM_CounterMode); -void PWM_ForcedOCConfig(u16 PWM_Channel, u16 PWM_ForcedAction); -void PWM_SetDeadTime(u16 DeadTime); -void PWM_ResetCounter(void); -void PWM_TRGOSelection(u16 PWM_TRGOMode); -FlagStatus PWM_GetFlagStatus(u16 PWM_FLAG); -void PWM_ClearFlag(u16 PWM_FLAG); -ITStatus PWM_GetITStatus(u16 PWM_IT); -void PWM_ClearITPendingBit(u16 PWM_IT); - -#endif /* __75x_PWM_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_rtc.h b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_rtc.h deleted file mode 100644 index a54dee958..000000000 --- a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_rtc.h +++ /dev/null @@ -1,63 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_rtc.h -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file contains all the functions prototypes for the -* RTC software library. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __75x_RTC_H -#define __75x_RTC_H - -/* Includes ------------------------------------------------------------------*/ -#include "75x_map.h" - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* RTC interrupts define */ -#define RTC_IT_Overflow 0x0004 /* Overflow interrupt */ -#define RTC_IT_Alarm 0x0002 /* Alarm interrupt */ -#define RTC_IT_Second 0x0001 /* Second interrupt */ - -/* RTC interrupts flags */ -#define RTC_FLAG_RTOFF 0x0020 /* RTC Operation OFF flag */ -#define RTC_FLAG_RSF 0x0008 /* Registers Synchronized flag */ -#define RTC_FLAG_Overflow 0x0004 /* Overflow interrupt flag */ -#define RTC_FLAG_Alarm 0x0002 /* Alarm interrupt flag */ -#define RTC_FLAG_Second 0x0001 /* Second interrupt flag */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -void RTC_DeInit(void); -void RTC_ITConfig(u16 RTC_IT, FunctionalState NewState); -void RTC_EnterConfigMode(void); -void RTC_ExitConfigMode(void); -u32 RTC_GetCounter(void); -void RTC_SetCounter(u32 CounterValue); -void RTC_SetPrescaler(u32 PrescalerValue); -u32 RTC_GetPrescaler(void); -void RTC_SetAlarm(u32 AlarmValue); -u32 RTC_GetDivider(void); -void RTC_WaitForLastTask(void); -void RTC_WaitForSynchro(void); -FlagStatus RTC_GetFlagStatus(u16 RTC_FLAG); -void RTC_ClearFlag(u16 RTC_FLAG); -ITStatus RTC_GetITStatus(u16 RTC_IT); -void RTC_ClearITPendingBit(u16 RTC_IT); - -#endif /* __75x_RTC_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_smi.h b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_smi.h deleted file mode 100644 index 1e4a71bd2..000000000 --- a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_smi.h +++ /dev/null @@ -1,111 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_smi.h -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file contains all the functions prototypes for the -* SMI software library. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __75x_SMI_H -#define __75x_SMI_H - -/* Includes ------------------------------------------------------------------*/ -#include "75x_map.h" - -/* Exported types ------------------------------------------------------------*/ -typedef struct -{ - u8 SMI_ClockHold; - u8 SMI_Prescaler; - u8 SMI_DeselectTime; -} SMI_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ -/* SMI mode */ -#define SMI_Mode_HW 0xEFFFFFFF -#define SMI_Mode_SW 0x10000000 - -/* Reception Length */ -#define SMI_RxLength_0Bytes 0x00000000 -#define SMI_RxLength_1Byte 0x00000010 -#define SMI_RxLength_2Bytes 0x00000020 -#define SMI_RxLength_3Bytes 0x00000030 -#define SMI_RxLength_4Bytes 0x00000040 - -/* Transmission Length */ -#define SMI_TxLength_0Bytes 0x00000000 -#define SMI_TxLength_1Byte 0x00000001 -#define SMI_TxLength_2Bytes 0x00000002 -#define SMI_TxLength_3Bytes 0x00000003 -#define SMI_TxLength_4Bytes 0x00000004 - -/* SMI memory Banks */ -#define SMI_Bank_0 0x00000001 -#define SMI_Bank_1 0x00000002 -#define SMI_Bank_2 0x00000004 -#define SMI_Bank_3 0x00000008 - -/* SMI Interrupts */ -#define SMI_IT_WC 0x00000200 -#define SMI_IT_TF 0x00000100 - -/* Fast Read Mode */ -#define SMI_FastRead_Disable 0xFFFF7FFF -#define SMI_FastRead_Enable 0x00008000 - -/* Write Burst Mode */ -#define SMI_WriteBurst_Disable 0xDFFFFFFF -#define SMI_WriteBurst_Enable 0x20000000 - -/* SMI Flags */ -#define SMI_FLAG_Bank3_WM 0x00008000 -#define SMI_FLAG_Bank2_WM 0x00004000 -#define SMI_FLAG_Bank1_WM 0x00002000 -#define SMI_FLAG_Bank0_WM 0x00001000 -#define SMI_FLAG_ERF2 0x00000800 -#define SMI_FLAG_ERF1 0x00000400 -#define SMI_FLAG_WC 0x00000200 -#define SMI_FLAG_TF 0x00000100 - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -void SMI_DeInit(void); -void SMI_Init(SMI_InitTypeDef* SMI_InitStruct); -void SMI_StructInit(SMI_InitTypeDef* SMI_InitStruct); -void SMI_ModeConfig(u32 SMI_Mode); -void SMI_TxRxLengthConfig(u32 SMI_TxLength, u32 SMI_RxLength); -void SMI_BankCmd(u32 SMI_Bank, FunctionalState NewState); -void SMI_ITConfig(u32 SMI_IT, FunctionalState NewState); -void SMI_SelectBank(u32 SMI_Bank); -void SMI_SendWENCmd(void); -void SMI_SendRSRCmd(void); -void SMI_SendCmd(u32 Command); -void SMI_FastReadConfig(u32 SMI_FastRead); -void SMI_WriteBurstConfig(u32 SMI_WriteBurst); -void SMI_WriteByte(u32 WriteAddr, u8 Data); -void SMI_WriteHalfWord(u32 WriteAddr, u16 Data); -void SMI_WriteWord(u32 WriteAddr, u32 Data); -u8 SMI_ReadByte(u32 ReadAddr); -u16 SMI_ReadHalfWord(u32 ReadAddr); -u32 SMI_ReadWord(u32 ReadAddr); -u8 SMI_ReadMemoryStatusRegister(void); -FlagStatus SMI_GetFlagStatus(u32 SMI_FLAG); -void SMI_ClearFlag(u32 SMI_FLAG); -ITStatus SMI_GetITStatus(u32 SMI_IT); -void SMI_ClearITPendingBit(u32 SMI_IT); - -#endif /* __75x_SMI_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_ssp.h b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_ssp.h deleted file mode 100644 index 96dec886a..000000000 --- a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_ssp.h +++ /dev/null @@ -1,135 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_SSP.h -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file contains all the functions prototypes for the -* SSP software library. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __75x_SSP_H -#define __75x_SSP_H - -/* Includes ------------------------------------------------------------------*/ -#include "75x_map.h" - -/* Exported types ------------------------------------------------------------*/ -/* SSP Init structure definition */ -typedef struct -{ - u16 SSP_FrameFormat; - u16 SSP_Mode; - u16 SSP_CPOL; - u16 SSP_CPHA; - u16 SSP_DataSize; - u16 SSP_NSS; - u16 SSP_SlaveOutput; - u8 SSP_ClockRate; - u8 SSP_ClockPrescaler; -}SSP_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ -/* SSP Frame Format Select */ -#define SSP_FrameFormat_TI 0x0010 -#define SSP_FrameFormat_Motorola 0xFFCF - -/* SSP Master/Slave Select */ -#define SSP_Mode_Master 0xFFFB -#define SSP_Mode_Slave 0x0004 - -/* SSP Clock Polarity */ -#define SSP_CPOL_Low 0xFFBF -#define SSP_CPOL_High 0x0040 - -/* SSP Clock Phase */ -#define SSP_CPHA_1Edge 0xFF7F -#define SSP_CPHA_2Edge 0x0080 - -/* SSP Data Size */ -#define SSP_DataSize_16b 0x000F -#define SSP_DataSize_15b 0x000E -#define SSP_DataSize_14b 0x000D -#define SSP_DataSize_13b 0x000C -#define SSP_DataSize_12b 0x000B -#define SSP_DataSize_11b 0x000A -#define SSP_DataSize_10b 0x0009 -#define SSP_DataSize_9b 0x0008 -#define SSP_DataSize_8b 0x0007 -#define SSP_DataSize_7b 0x0006 -#define SSP_DataSize_6b 0x0005 -#define SSP_DataSize_5b 0x0004 -#define SSP_DataSize_4b 0x0003 - -/* SSP Slave Select management config */ -#define SSP_NSS_Hard 0xFFEF -#define SSP_NSS_Soft 0x0010 - -/* SSP NSS internal config */ -#define SSP_NSSInternal_Set 0x0020 -#define SSP_NSSInternal_Reset 0xFFDF - -/* SSP Slave output config */ -#define SSP_SlaveOutput_Enable 0xFFF7 -#define SSP_SlaveOutput_Disable 0x0008 - -/* SSP Interrupts */ -#define SSP_IT_TxFifo 0x0008 -#define SSP_IT_RxFifo 0x0004 -#define SSP_IT_RxTimeOut 0x0002 -#define SSP_IT_RxOverrun 0x0001 - -/* SSP Flags */ -#define SSP_FLAG_Busy 0x0024 -#define SSP_FLAG_RxFifoFull 0x0023 -#define SSP_FLAG_RxFifoNotEmpty 0x0022 -#define SSP_FLAG_TxFifoNotFull 0x0021 -#define SSP_FLAG_TxFifoEmpty 0x0020 -#define SSP_FLAG_TxFifo 0x0043 -#define SSP_FLAG_RxFifo 0x0042 -#define SSP_FLAG_RxTimeOut 0x0041 -#define SSP_FLAG_RxOverrun 0x0040 - -/* SSP DMA Requests */ -#define SSP0_DMA_Transmit 0x0002 -#define SSP0_DMA_Receive 0x0001 - -#define SSP0_DMATxReq_Single 0xFFF7 -#define SSP0_DMATxReq_Burst 0x0008 - -#define SSP0_DMARxReq_Single 0xFFFB -#define SSP0_DMARxReq_Burst 0x0004 - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -void SSP_DeInit(SSP_TypeDef* SSPx); -void SSP_Init(SSP_TypeDef* SSPx, SSP_InitTypeDef* SSP_InitStruct); -void SSP_StructInit(SSP_InitTypeDef* SSP_InitStruct); -void SSP_Cmd(SSP_TypeDef* SSPx, FunctionalState NewState); -void SSP_ITConfig(SSP_TypeDef* SSPx, u16 SSP_IT, FunctionalState NewState); -void SSP_DMACmd(u16 SSP0_DMAtransfer, FunctionalState NewState); -void SSP_DMATxConfig(u16 SSP0_DMATxReq); -void SSP_DMARxConfig(u16 SSP0_DMARxReq); -void SSP_SendData(SSP_TypeDef* SSPx, u16 Data); -u16 SSP_ReceiveData(SSP_TypeDef* SSPx); -void SSP_LoopBackConfig(SSP_TypeDef* SSPx, FunctionalState NewState); -void SSP_NSSInternalConfig(SSP_TypeDef* SSPx, u16 SSP_NSSState); -FlagStatus SSP_GetFlagStatus(SSP_TypeDef* SSPx, u16 SSP_FLAG); -void SSP_ClearFlag(SSP_TypeDef* SSPx, u16 SSP_FLAG); -ITStatus SSP_GetITStatus(SSP_TypeDef* SSPx, u16 SSP_IT); -void SSP_ClearITPendingBit(SSP_TypeDef* SSPx, u16 SSP_IT); - -#endif /* __75x_SSP_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_tb.h b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_tb.h deleted file mode 100644 index e5054935d..000000000 --- a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_tb.h +++ /dev/null @@ -1,93 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_tb.h -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file contains all the functions prototypes for the -* TB software library. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __75x_TB_H -#define __75x_TB_H - -/* Includes ------------------------------------------------------------------*/ -#include "75x_map.h" - -/* Exported types ------------------------------------------------------------*/ -typedef struct -{ - u16 TB_Mode; /* TB mode */ - u16 TB_ClockSource; /* TB clock source: CK_TIM or CK_RTC */ - u16 TB_CounterMode; /* TB counter mode */ - u16 TB_ICAPolarity; /* TB Input Capture signal Polarity */ - u16 TB_Prescaler; /* TB Prescaler factor */ - u16 TB_AutoReload; /* TB AutoReload factor */ -} TB_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ -/* TB modes */ -#define TB_Mode_IC 0x0002 -#define TB_Mode_Timing 0x0001 - -/* TB clock source */ -#define TB_ClockSource_CKTIM 0x0001 -#define TB_ClockSource_CKRTC 0x0002 - -/* TB Input capture polarity */ -#define TB_ICAPolarity_Rising 0x7000 -#define TB_ICAPolarity_Falling 0x8000 - -/* TB counter modes */ -#define TB_CounterMode_Up 0x0000 -#define TB_CounterMode_Down 0x0010 -#define TB_CounterMode_CenterAligned 0x0060 - -/* TB interrupt sources */ -#define TB_IT_Update 0x0001 -#define TB_IT_IC 0x0004 -#define TB_IT_GlobalUpdate 0x8001 - -/* TB Flags */ -#define TB_FLAG_IC 0x0004 -#define TB_FLAG_Update 0x0001 - -/* TB Slave Mode Selection */ -#define TB_SMSMode_Trigger 0x0018 -#define TB_SMSMode_Gated 0x0010 -#define TB_SMSMode_External 0x0008 -#define TB_SMSMode_Reset 0x0000 - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -void TB_DeInit(void); -void TB_Init(TB_InitTypeDef* TB_InitStruct); -void TB_StructInit(TB_InitTypeDef *TB_InitStruct); -void TB_Cmd(FunctionalState Newstate ); -void TB_ITConfig(u16 TB_IT, FunctionalState Newstate); -void TB_SetPrescaler(u16 Prescaler); -void TB_ResetCounter(void); -void TB_DebugCmd(FunctionalState Newstate); -void TB_CounterModeConfig(u16 TB_CounterMode); -void TB_SLaveModeConfig(u16 TB_SMSMode); -u16 TB_GetCounter(void); -u16 TB_GetICAP1(void); -void TB_SetCounter(u16 Counter); -FlagStatus TB_GetFlagStatus(u16 TB_FLAG); -void TB_ClearFlag(u16 TB_FLAG); -ITStatus TB_GetITStatus(u16 TB_IT); -void TB_ClearITPendingBit(u16 TB_IT); - -#endif /* __75x_TB_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_tim.h b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_tim.h deleted file mode 100644 index 02b51321b..000000000 --- a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_tim.h +++ /dev/null @@ -1,232 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_tim.h -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file contains all the functions prototypes for the -* TIM software library. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __75x_TIM_H -#define __75x_TIM_H - -/* Includes ------------------------------------------------------------------*/ -#include "75x_map.h" - -/* Exported types ------------------------------------------------------------*/ -typedef struct -{ - u16 TIM_Mode; /* Timer Mode */ - u16 TIM_Prescaler; /* Prescaler value */ - u16 TIM_ClockSource; /* Timer clock source */ - u16 TIM_ExtCLKEdge; /* External clock edge */ - u16 TIM_CounterMode; /* Counter mode: Up/Down, Edge aligned or center aligned */ - u16 TIM_Period; /* Period value */ - u16 TIM_Channel; /* Timer Channel: 1, 2 or All */ - u16 TIM_Pulse1; /* PWM or OCM Channel 1 pulse length */ - u16 TIM_Pulse2; /* PWM or OCM Channel 2 pulse length */ - u16 TIM_RepetitivePulse; /* OPM Repetitive pulse state: enable or disable */ - u16 TIM_Polarity1; /* PWM, OCM or OPM Channel 1 polarity */ - u16 TIM_Polarity2; /* PWM or OCM Channel 2 polarity */ - u16 TIM_IC1Selection; /* Input Capture 1 selection: TI1 or TI2 */ - u16 TIM_IC2Selection; /* Input Capture 2 selection: TI1 or TI2 */ - u16 TIM_IC1Polarity; /* Input Capture 1 polarity */ - u16 TIM_IC2Polarity; /* Input Capture 2 polarity */ - u16 TIM_PWMI_ICSelection; /* PWM Input Capture selection: TI1 or TI2 */ - u16 TIM_PWMI_ICPolarity; /* PWM Input Capture Polarity */ -} TIM_InitTypeDef; - -/* Master and slave synchronized Timer peripherals */ -typedef enum -{ - PWM_Master = 0x01, - TIM0_Master, - TIM1_Master, - TIM2_Master -}Master_TypeDef; - -typedef enum -{ - PWM_Slave = 0x05, - TIM0_Slave, - TIM1_Slave, - TIM2_Slave -}Slave_TypeDef; - -/* Exported constants --------------------------------------------------------*/ -/* TIM modes */ -#define TIM_Mode_OCTiming 0x0001 -#define TIM_Mode_OCActive 0x0002 -#define TIM_Mode_OCInactive 0x0003 -#define TIM_Mode_OCToggle 0x0004 -#define TIM_Mode_PWM 0x0005 -#define TIM_Mode_PWMI 0x0006 -#define TIM_Mode_IC 0x0007 -#define TIM_Mode_Encoder1 0x0008 -#define TIM_Mode_Encoder2 0x0009 -#define TIM_Mode_Encoder3 0x000A -#define TIM_Mode_OPM_PWM 0x000B -#define TIM_Mode_OPM_Toggle 0x000C -#define TIM_Mode_OPM_Active 0x000D - -/* TIM Clock Source */ -#define TIM_ClockSource_Internal 0x0001 -#define TIM_ClockSource_TI11 0x0002 -#define TIM_ClockSource_TI12 0x0003 -#define TIM_ClockSource_TI22 0x0004 -#define TIM_ClockSource_TI21 0x0005 - -/* TIM External Clock Edge */ -#define TIM_ExtCLKEdge_Falling 0x0001 -#define TIM_ExtCLKEdge_Rising 0x0002 - -/* TIM Counter Mode */ -#define TIM_CounterMode_Up 0x0000 -#define TIM_CounterMode_Down 0x0010 -#define TIM_CounterMode_CenterAligned1 0x0020 -#define TIM_CounterMode_CenterAligned2 0x0040 -#define TIM_CounterMode_CenterAligned3 0x0060 - -/* TIM Channel */ -#define TIM_Channel_1 0x0001 -#define TIM_Channel_2 0x0002 -#define TIM_Channel_ALL 0x0003 - -/* TIM Polarity channel 1 */ -#define TIM_Polarity1_High 0x0001 -#define TIM_Polarity1_Low 0x0002 - -/* TIM Polarity channel 2 */ -#define TIM_Polarity2_High 0x0001 -#define TIM_Polarity2_Low 0x0002 - -#define TIM_RepetitivePulse_Disable 0x0005 -#define TIM_RepetitivePulse_Enable 0x0006 - -/* TIM Input Capture channel 1 Selection */ -#define TIM_IC1Selection_TI1 0x0001 -#define TIM_IC1Selection_TI2 0x0002 - -/* TIM Input Capture channel 2 Selection */ -#define TIM_IC2Selection_TI1 0x0001 -#define TIM_IC2Selection_TI2 0x0002 - -/* TIM Input Capture channel 1 Polarity */ -#define TIM_IC1Polarity_Falling 0x0001 -#define TIM_IC1Polarity_Rising 0x0002 - -/* TIM Input Capture channel 2 Polarity */ -#define TIM_IC2Polarity_Falling 0x0001 -#define TIM_IC2Polarity_Rising 0x0002 - -/* TIM PWM Input IC Selection */ -#define TIM_PWMI_ICSelection_TI1 0x0001 -#define TIM_PWMI_ICSelection_TI2 0x0002 - -/* TIM PWM Input IC Polarity */ -#define TIM_PWMI_ICPolarity_Falling 0x0003 -#define TIM_PWMI_ICPolarity_Rising 0x0004 - -/* TIM interrupt sources */ -#define TIM_IT_IC1 0x0004 -#define TIM_IT_IC2 0x0008 -#define TIM_IT_OC1 0x0100 -#define TIM_IT_OC2 0x0200 -#define TIM_IT_Update 0x0001 -#define TIM_IT_GlobalUpdate 0x1001 - -/* TIM DMA sources */ -#define TIM_DMASource_IC1 0x0004 -#define TIM_DMASource_IC2 0x0008 -#define TIM_DMASource_OC1 0x0100 -#define TIM_DMASource_OC2 0x0200 -#define TIM_DMASource_Update 0x0001 - -/* TIM DMA Base address */ -#define TIM_DMABase_CR 0x0000 -#define TIM_DMABase_SCR 0x0800 -#define TIM_DMABase_IMCR 0x1000 -#define TIM_DMABase_OMR1 0x1800 -#define TIM_DMABase_RSR 0x3000 -#define TIM_DMABase_RER 0x3800 -#define TIM_DMABase_ISR 0x4000 -#define TIM_DMABase_CNT 0x4800 -#define TIM_DMABase_PSC 0x5000 -#define TIM_DMABase_ARR 0x6000 -#define TIM_DMABase_OCR1 0x6800 -#define TIM_DMABase_OCR2 0x7000 -#define TIM_DMABase_ICR1 0x9800 -#define TIM_DMABase_ICR2 0xA000 - -/* TIM Flags */ -#define TIM_FLAG_IC1 0x0004 -#define TIM_FLAG_IC2 0x0008 -#define TIM_FLAG_OC1 0x0100 -#define TIM_FLAG_OC2 0x0200 -#define TIM_FLAG_Update 0x0001 - -/* TIM_ForcedAction */ -#define TIM_ForcedAction_Active 0x000A -#define TIM_ForcedAction_InActive 0x0008 - -/* TIM synchronization action */ -#define TIM_SynchroAction_Enable 0x0100 -#define TIM_SynchroAction_Update 0x0200 -#define TIM_SynchroAction_Reset 0x0000 -#define TIM_SynchroAction_OC 0x0300 - -/* TIM synchronization mode */ -#define TIM_SynchroMode_Gated 0x0010 -#define TIM_SynchroMode_Trigger 0x0018 -#define TIM_SynchroMode_External 0x0008 -#define TIM_SynchroMode_Reset 0x0000 - -/* OCRM bit states */ -#define TIM_OCRMState_Enable 0x0005 -#define TIM_OCRMState_Disable 0x0006 - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -void TIM_DeInit(TIM_TypeDef *TIMx); -void TIM_Init(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct); -void TIM_StructInit(TIM_InitTypeDef *TIM_InitStruct); -void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState Newstate); -void TIM_ITConfig(TIM_TypeDef *TIMx, u16 TIM_IT, FunctionalState Newstate); -void TIM_PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_Channel, FunctionalState Newstate); -void TIM_DMAConfig(u16 TIM_DMASources, u16 TIM_OCRMState, u16 TIM_DMABase); -void TIM_DMACmd(u16 TIM_DMASources, FunctionalState Newstate); -void TIM_ClockSourceConfig(TIM_TypeDef *TIMx, u16 TIM_ClockSource, - u16 TIM_ExtCLKEdge); -void TIM_SetPrescaler(TIM_TypeDef* TIMx, u16 Prescaler); -void TIM_SetPeriod(TIM_TypeDef* TIMx, u16 Period); -void TIM_SetPulse(TIM_TypeDef* TIMx, u16 TIM_Channel, u16 Pulse); -u16 TIM_GetICAP1(TIM_TypeDef *TIMx); -u16 TIM_GetICAP2(TIM_TypeDef *TIMx); -u16 TIM_GetPWMIPulse(TIM_TypeDef *TIMx); -u16 TIM_GetPWMIPeriod(TIM_TypeDef *TIMx); -void TIM_DebugCmd(TIM_TypeDef *TIMx, FunctionalState Newstate); -void TIM_CounterModeConfig(TIM_TypeDef* TIMx, u16 TIM_CounterMode); -void TIM_ForcedOCConfig(TIM_TypeDef* TIMx, u16 TIM_Channel, - u16 TIM_ForcedAction); -void TIM_ResetCounter(TIM_TypeDef* TIMx); -void TIM_SynchroConfig(Master_TypeDef Master, Slave_TypeDef Slave, - u16 TIM_SynchroAction, u16 TIM_SynchroMode); -FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, u16 TIM_FLAG); -void TIM_ClearFlag(TIM_TypeDef* TIMx, u16 TIM_FLAG); -ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, u16 TIM_IT); -void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, u16 TIM_IT); - -#endif /* __75x_TIM_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_type.h b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_type.h deleted file mode 100644 index 6f8842700..000000000 --- a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_type.h +++ /dev/null @@ -1,71 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_type.h -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file contains all the common data types used for the -* STR75x software library. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __75x_TYPE_H -#define __75x_TYPE_H - -/* Includes ------------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -typedef signed long s32; -typedef signed short s16; -typedef signed char s8; - -typedef volatile signed long vs32; -typedef volatile signed short vs16; -typedef volatile signed char vs8; - -typedef unsigned long u32; -typedef unsigned short u16; -typedef unsigned char u8; - -typedef volatile unsigned long vu32; -typedef volatile unsigned short vu16; -typedef volatile unsigned char vu8; - -typedef volatile unsigned long const vuc32; /* Read Only */ -typedef volatile unsigned short const vuc16; /* Read Only */ -typedef volatile unsigned char const vuc8; /* Read Only */ - - -typedef enum { FALSE = 0, TRUE = !FALSE } bool; - -typedef enum { RESET = 0, SET = !RESET } FlagStatus, ITStatus; - -typedef enum { DISABLE = 0, ENABLE = !DISABLE} FunctionalState; - -typedef enum { ERROR = 0, SUCCESS = !ERROR} ErrorStatus; - -#define U8_MAX ((u8)255) -#define S8_MAX ((s8)127) -#define S8_MIN ((s8)-128) -#define U16_MAX ((u16)65535u) -#define S16_MAX ((s16)32767) -#define S16_MIN ((s16)-32768) -#define U32_MAX ((u32)4294967295uL) -#define S32_MAX ((s32)2147483647) -#define S32_MIN ((s32)-2147483648) - -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -#endif /* __75x_TYPE_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_uart.h b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_uart.h deleted file mode 100644 index 6fc5033ab..000000000 --- a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_uart.h +++ /dev/null @@ -1,178 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_uart.h -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file contains all the functions prototypes for the -* UART software library. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __75x_UART_H -#define __75x_UART_H - -/* Includes ------------------------------------------------------------------*/ -#include "75x_map.h" - -/* Exported types ------------------------------------------------------------*/ -/* UART FIFO Level enumeration */ -typedef enum -{ - UART_FIFOLevel_1_8 = 0x0000, /* FIFO size 16 bytes, FIFO level 2 bytes */ - UART_FIFOLevel_1_4 = 0x0001, /* FIFO size 16 bytes, FIFO level 4 bytes */ - UART_FIFOLevel_1_2 = 0x0002, /* FIFO size 16 bytes, FIFO level 8 bytes */ - UART_FIFOLevel_3_4 = 0x0003, /* FIFO size 16 bytes, FIFO level 12 bytes */ - UART_FIFOLevel_7_8 = 0x0004 /* FIFO size 16 bytes, FIFO level 14 bytes */ -}UART_FIFOLevel; - -/* UART Init Structure definition */ -typedef struct -{ - u16 UART_WordLength; - u16 UART_StopBits; - u16 UART_Parity; - u32 UART_BaudRate; - u16 UART_HardwareFlowControl; - u16 UART_Mode; - u16 UART_FIFO; - UART_FIFOLevel UART_TxFIFOLevel; - UART_FIFOLevel UART_RxFIFOLevel; -}UART_InitTypeDef; - - -/* UART RTS enumeration */ -typedef enum -{ - RTSRESET = 1, - RTSSET -}UART_RTSTypeDef; - - -/* Exported constants --------------------------------------------------------*/ -/* UART Data Length */ -#define UART_WordLength_5D 0x0000 /* 5 bits Data */ -#define UART_WordLength_6D 0x0020 /* 6 bits Data */ -#define UART_WordLength_7D 0x0040 /* 7 bits Data */ -#define UART_WordLength_8D 0x0060 /* 8 bits Data */ - -/* UART Stop Bits */ -#define UART_StopBits_1 0xFFF7 /* One stop bit is transmitted at - the end of frame */ -#define UART_StopBits_2 0x0008 /* Tow stop bits are transmitted - at the end of frame */ - -/* UART Parity */ -#define UART_Parity_No 0x0000 /* Parity Disable */ -#define UART_Parity_Even 0x0006 /* Even Parity */ -#define UART_Parity_Odd 0x0002 /* Odd Parity */ -#define UART_Parity_OddStick 0x0082 /* 1 is transmitted as bit parity */ -#define UART_Parity_EvenStick 0x0086 /* 0 is transmitted as bit parity */ - -/* UART Hardware Flow Control */ -#define UART_HardwareFlowControl_None 0x0000/* HFC Disable */ -#define UART_HardwareFlowControl_RTS 0x4000/* RTS Enable */ -#define UART_HardwareFlowControl_CTS 0x8000/* CTS Enable */ -#define UART_HardwareFlowControl_RTS_CTS 0xC000/* CTS and RTS Enable */ - -/* UART Mode */ -#define UART_Mode_Rx 0x0200 /* UART Rx Enabled */ -#define UART_Mode_Tx 0x0100 /* UART Tx Enbled */ -#define UART_Mode_Tx_Rx 0x0300 /* UART Tx and Rx Enabled */ - -/* UART FIFO */ -#define UART_FIFO_Disable 0xFFEF /* FIFOs Disable */ -#define UART_FIFO_Enable 0x0010 /* FIFOs Enable */ - -/* UART Interrupt definition */ -#define UART_IT_OverrunError 0x0400 /* Overrun Error interrupt */ -#define UART_IT_BreakError 0x0200 /* Break Error interrupt */ -#define UART_IT_ParityError 0x0100 /* Parity Error interrupt */ -#define UART_IT_FrameError 0x0080 /* Frame Error interrupt */ -#define UART_IT_ReceiveTimeOut 0x0040 /* Receive Time Out interrupt */ -#define UART_IT_Transmit 0x0020 /* Transmit interrupt */ -#define UART_IT_Receive 0x0010 /* Receive interrupt */ -#define UART_IT_CTS 0x0002 /* CTS interrupt */ - -/* UART0 DMA transfer */ -#define UART0_DMATransfer_Single 0xFFF7 /* Single DMA transfer */ -#define UART0_DMATransfer_Burst 0x0008 /* Burst DMA transfer */ - -/* UART0 DMA On Error */ -#define UART0_DMAOnError_Enable 0xFFFB /* DMA receive request enabled - when the UART0 error interrupt - is asserted. */ -#define UART0_DMAOnError_Disable 0x0004 /* DMA receive request disabled - when the UART0 error interrupt - is asserted. */ - -/* UART0 DMA Request */ -#define UART0_DMAReq_Tx 0x0002 /* Transmit DMA Enable */ -#define UART0_DMAReq_Rx 0x0001 /* Receive DMA Enable */ - -/* UART FLAG */ -#define UART_FLAG_OverrunError 0x23 /* Overrun error flag */ -#define UART_FLAG_Break 0x22 /* break error flag */ -#define UART_FLAG_ParityError 0x21 /* parity error flag */ -#define UART_FLAG_FrameError 0x20 /* frame error flag */ -#define UART_FLAG_TxFIFOEmpty 0x47 /* Transmit FIFO Empty flag */ -#define UART_FLAG_RxFIFOFull 0x46 /* Receive FIFO Full flag */ -#define UART_FLAG_TxFIFOFull 0x45 /* Transmit FIFO Full flag */ -#define UART_FLAG_RxFIFOEmpty 0x44 /* Receive FIFO Empty flag */ -#define UART_FLAG_Busy 0x43 /* UART Busy flag */ -#define UART_FLAG_CTS 0x40 /* CTS flag */ -#define UART_RawIT_OverrunError 0x6A /* Overrun Error Masked IT flag */ -#define UART_RawIT_BreakError 0x69 /* Break Error Masked IT flag */ -#define UART_RawIT_ParityError 0x68 /* Parity Error Masked IT flag */ -#define UART_RawIT_FrameError 0x67 /* Frame Error Masked IT flag */ -#define UART_RawIT_ReceiveTimeOut 0x66 /* ReceiveTimeOut Masked IT flag */ -#define UART_RawIT_Transmit 0x65 /* Transmit Masked IT flag */ -#define UART_RawIT_Receive 0x64 /* Receive Masked IT flag */ -#define UART_RawIT_CTS 0x61 /* CTS Masked IT flag */ - -/* UART LIN break length */ -#define UART_LINBreakLength_10 0x0000 /* 10 low bits */ -#define UART_LINBreakLength_11 0x0200 /* 11 low bits */ -#define UART_LINBreakLength_12 0x0400 /* 12 low bits */ -#define UART_LINBreakLength_13 0x0600 /* 13 low bits */ -#define UART_LINBreakLength_14 0x0800 /* 14 low bits */ -#define UART_LINBreakLength_15 0x0A00 /* 15 low bits */ -#define UART_LINBreakLength_16 0x0C00 /* 16 low bits */ -#define UART_LINBreakLength_17 0x0E00 /* 17 low bits */ -#define UART_LINBreakLength_18 0x1000 /* 18 low bits */ -#define UART_LINBreakLength_19 0x1200 /* 19 low bits */ -#define UART_LINBreakLength_20 0x1400 /* 20 low bits */ -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -void UART_DeInit(UART_TypeDef* UARTx); -void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct); -void UART_StructInit(UART_InitTypeDef* UART_InitStruct); -void UART_Cmd(UART_TypeDef* UARTx, FunctionalState NewState); -void UART_ITConfig(UART_TypeDef* UARTx, u16 UART_IT, FunctionalState NewState); -void UART_DMAConfig(u16 UART0_DMATransfer, u16 UART0_DMAOnError); -void UART_DMACmd(u16 UART0_DMAReq, FunctionalState NewState); -void UART_LoopBackConfig(UART_TypeDef* UARTx, FunctionalState NewState); -void UART_LINConfig(UART_TypeDef* UARTx, u16 UART_LINBreakLength); -void UART_LINCmd(UART_TypeDef* UARTx, FunctionalState NewState); -void UART_SendData(UART_TypeDef* UARTx, u8 Data); -u8 UART_ReceiveData(UART_TypeDef* UARTx); -void UART_SendBreak(UART_TypeDef* UARTx); -void UART_RTSConfig(UART_TypeDef* UARTx,UART_RTSTypeDef RTSState); -FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, u16 UART_FLAG); -void UART_ClearFlag(UART_TypeDef* UARTx, u16 UART_FLAG); -ITStatus UART_GetITStatus(UART_TypeDef* UARTx, u16 UART_IT); -void UART_ClearITPendingBit(UART_TypeDef* UARTx, u16 UART_IT); - -#endif /* __75x_UART_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_wdg.h b/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_wdg.h deleted file mode 100644 index 3390b63f3..000000000 --- a/Demo/ARM7_STR75x_IAR/STLibrary/inc/75x_wdg.h +++ /dev/null @@ -1,62 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_wdg.h -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file contains all the functions prototypes for the -* WDG software library. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __75x_WDG_H -#define __75x_WDG_H - -/* Includes ------------------------------------------------------------------*/ -#include "75x_map.h" - -/* Exported types ------------------------------------------------------------*/ - typedef struct -{ - u16 WDG_Mode; /* Watchdog or Timer mode */ - u16 WDG_Preload; /* Preload register */ - u8 WDG_Prescaler; /* Prescaler register */ -}WDG_InitTypeDef; -/* Exported constants --------------------------------------------------------*/ - -/* WDG/Timer Select */ -#define WDG_Mode_WDG 0x0001 -#define WDG_Mode_Timer 0xFFFE - -/* WDG End of Count interrupt request */ -#define WDG_IT_EC 0x0001 - -/* WDG end of count Flag */ -#define WDG_FLAG_EC 0x0001 - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -void WDG_DeInit(void); -void WDG_Init(WDG_InitTypeDef* WDG_InitStruct); -void WDG_StructInit(WDG_InitTypeDef* WDG_InitStruct); -void WDG_Cmd(FunctionalState NewState); -void WDG_ITConfig(FunctionalState NewState); -u16 WDG_GetCounter(void); -FlagStatus WDG_GetFlagStatus(void); -void WDG_ClearFlag(void); -ITStatus WDG_GetITStatus(void); -void WDG_ClearITPendingBit(void); - -#endif /* __WDG_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/inc/lcd.h b/Demo/ARM7_STR75x_IAR/STLibrary/inc/lcd.h deleted file mode 100644 index 11df54c1b..000000000 --- a/Demo/ARM7_STR75x_IAR/STLibrary/inc/lcd.h +++ /dev/null @@ -1,120 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : lcd.h -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file contains all the functions prototypes for the -* lcd software driver. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion ---------------------------------------*/ -#ifndef __LCD_H -#define __LCD_H - -/* Includes --------------------------------------------------------------------*/ -#include "75x_lib.h" - -/* Exported types --------------------------------------------------------------*/ - - /* Data lines configuration mode */ - typedef enum - { - Input, - Output - } DataConfigMode_TypeDef; - - /* Text color mode */ - typedef enum - { - BlackText=0, - WhiteText=1 - } TextColorMode_TypeDef; - - /* Dot On/Off mode */ - typedef enum - { - Dot_On, - Dot_Off - } DotMode_TypeDef; - -/* Exported constants ----------------------------------------------------------*/ - -/* LCD Control pins */ -#define CtrlPin_E2 0x00000001 -#define CtrlPin_E1 0x00000002 -#define CtrlPin_RW 0x00000004 -#define CtrlPin_DI 0x00000008 - -/* LCD Commands */ -#define DISPLAY_ON 0xAF -#define DISPLAY_OFF 0xAE -#define START_LINE 0xC0 -#define START_COLUMN 0x00 -#define CLOCKWISE_OUTPUT 0xA0 -#define DYNAMIC_DRIVE 0xA4 -#define DUTY_CYCLE 0xA9 -#define READ_MODIFY_WRITE_OFF 0xEE -#define SOFTWARE_RESET 0xE2 - -/* LCD Lines when LCD is managed as 2*17 characters */ -#define Line1 0x0 -#define Line2 0x2 - -/* Exported macro --------------------------------------------------------------*/ -/* Exported functions ----------------------------------------------------------*/ -/*----- Low layer function -----*/ -void LCD_CtrlLinesConfig(void); -void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, u32 CtrlPins, BitAction BitVal); -void LCD_DataLinesConfig(DataConfigMode_TypeDef Mode); -void LCD_DataLinesWrite(GPIO_TypeDef* GPIOx, u32 PortVal); - -/*----- Medium layer function -----*/ -void LCD_CheckMasterStatus(void); -void LCD_CheckSlaveStatus(void); -void LCD_SendMasterCmd(u8 Cmd); -void LCD_SendSlaveCmd(u8 Cmd); -void LCD_SendMasterData(u8 Data); -u32 LCD_ReadMasterData(void); -void LCD_SendSlaveData(u8 Data); -u32 LCD_ReadSlaveData(void); -void LCD_SetMasterPage(u8 Page); -void LCD_SetSlavePage(u8 Page); -void LCD_SetMasterColumn(u8 Address); -void LCD_SetSlaveColumn(u8 Address); -void LCD_DrawChar(u8 Line, u8 Column, u8 Width, u8 *Bmp); -u8 LCD_HexToAsciiLow(u8 byte); -u8 LCD_HexToAsciiHigh(u8 byte); -void LCD_SetTextColor(TextColorMode_TypeDef TextColor); - -/*----- High layer function -----*/ -void LCD_Init(void); -/* LCD managed as 2 Lines, 17 characters each one (2Lines*17Char) */ -void LCD_ClearLine(u8 Line); -void LCD_DisplayChar(u8 Line, u8 Column, u8 Ascii, TextColorMode_TypeDef CharMode); -void LCD_DisplayString(u8 Line, u8 *ptr, TextColorMode_TypeDef CharMode); -void LCD_Printf(u8* ptr, ...); -/* LCD managed as 122*32 dots */ -void LCD_ClearMaster(void); -void LCD_ClearSlave(void); -void LCD_Clear(void); -void LCD_DrawMasterGraphic(u8 *Bmp); -void LCD_DrawSlaveGraphic(u8 *Bmp); -void LCD_DrawGraphic(u8 *Bmp); -void LCD_ScrollGraphic(u8 *Bmp, u32 nCount); -void LCD_DrawPixel(u8 XPos, u8 YPos, DotMode_TypeDef Mode); -void LCD_DrawLine(u8 XPos1, u8 YPos1, u8 XPos2, u8 YPos2); -void LCD_DrawBox(u8 XPos, u8 YPos, u8 Dx, u8 Dy); - -#endif /*__LCD_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE******/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_adc.c b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_adc.c deleted file mode 100644 index 93905cb6c..000000000 --- a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_adc.c +++ /dev/null @@ -1,869 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_adc.c -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file provides all the ADC software functions. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -#include "75x_adc.h" -#include "75x_mrcc.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Mask for Power Down Mode */ -#define ADC_PowerDown_Enable 0x8000 -#define ADC_PowerDown_Disable 0x7FFF - -/* Mask for Watchdog Thresholds Enable */ -#define ADC_AnalogWatchdog_Enable 0x8000 -#define ADC_AnalogWatchdog_Disable 0x7FFF - -/* Mask for Injected conversion start */ -#define ADC_Injec_ConversionStart 0x8000 - -/* DMA enable */ -#define ADC_DMA_ExtEnable_Mask 0x4000 - -/* Injected start trigger enable */ -#define ADC_Injec_ExtTrigger_Enable 0x4000 - -/* ADC Masks */ -#define ADC_DMAFirstEnabledChannel_Mask 0x000F -#define ADC_DataRegisterOffset 0x0050 -#define ADC_FirstChannel_Mask 0xFFF0 -#define ADC_ChannelNumber_Mask 0xFC3F -#define ADC_Threshold_Mask 0xFC00 -#define ADC_AnalogWatchdogChannel_Mask 0xC3FF -#define ADC_Prescalers_Mask 0x7F18 -#define ADC_SPEN_Mask 0x8000 -#define ADC_FallingEdge_Mask 0xEFFF -#define ADC_LowLevel_Mask 0x4000 -#define ADC_HighLevel_Mask 0xDFFF -#define ADC_Calibration_Mask 0x0002 - -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/******************************************************************************* -* Function Name : ADC_DeInit -* Description : Deinitializes the ADC peripheral registers to their default -* reset values. -* Input : None. -* Output : None -* Return : None. -*******************************************************************************/ -void ADC_DeInit(void) -{ - /* Reset the ADC registers values*/ - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_ADC,ENABLE); - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_ADC,DISABLE); -} - -/******************************************************************************* -* Function Name : ADC_Init -* Description : Initializes the ADC peripheral according to the specified -* parameters in the ADC_InitStruct. -* Input : - ADC_InitStruct: pointer to an ADC_InitTypeDef structure that - contains the configuration information for the ADC peripheral. -* Output : None -* Return : None -*******************************************************************************/ -void ADC_Init(ADC_InitTypeDef* ADC_InitStruct) -{ - /* Configure the conversion mode */ - if(ADC_InitStruct->ADC_ConversionMode == ADC_ConversionMode_Scan) - { - /* Set the scan conversion mode */ - ADC->CLR2 |= ADC_ConversionMode_Scan; - } - else - { - /* Set the one-shot conversion mode */ - ADC->CLR2 &= ADC_ConversionMode_OneShot; - } - - /* Configure the external start conversion trigger */ - switch(ADC_InitStruct->ADC_ExtTrigger) - { - case ADC_ExtTrigger_HighLevel: - /* Start conversion on High level of the external trigger (TIM0) */ - ADC->CLR0 &= ADC_HighLevel_Mask; - ADC->CLR0 |= ADC_ExtTrigger_HighLevel; - break; - - case ADC_ExtTrigger_LowLevel: - /* Start conversion on low level of the external trigger (TIM0) */ - ADC->CLR0 &= ADC_ExtTrigger_LowLevel; - ADC->CLR0 |= ADC_LowLevel_Mask; - break; - - case ADC_ExtTrigger_RisingEdge: - /* Start conversion on rising edge of the external trigger (TIM0) */ - ADC->CLR0 |= ADC_ExtTrigger_RisingEdge; - break; - - case ADC_ExtTrigger_FallingEdge: - /* Start conversion on falling edge of the external trigger (TIM0) */ - ADC->CLR0 &= ADC_FallingEdge_Mask; - ADC->CLR0 |= ADC_ExtTrigger_FallingEdge; - break; - - case ADC_ExtTrigger_Disable: - /* Disable the external trigger and start the conversion by software */ - ADC->CLR0 &= ADC_ExtTrigger_Disable; - break; - - default: - break; - } - - /* Configure the auto clock off feature */ - if (ADC_InitStruct->ADC_AutoClockOff == ADC_AutoClockOff_Enable) - { - /* Enable the auto clock off feature */ - ADC->CLR4 |= ADC_AutoClockOff_Enable; - } - else - { - /* Disable the auto clock off feature */ - ADC->CLR4 &= ADC_AutoClockOff_Disable; - } - - /* Clear conversion prescaler CNVP[2:0], sampling prescaler SMPP[2:0] bits - and Sample prescaler enable SPEN bit */ - ADC->CLR1 &= ADC_Prescalers_Mask; - /* Set conversion prescaler value (sampling and conversion prescalers are equal - while SPEN bit is reset */ - ADC->CLR1 |= (ADC_InitStruct->ADC_ConversionPrescaler<<5); - - /* In case ADC_SamplingPrescaler member is different from the conversion one */ - if(ADC_InitStruct->ADC_SamplingPrescaler != ADC_InitStruct->ADC_ConversionPrescaler) - { - /* Set the sampling prescaler value */ - ADC->CLR1 |= ADC_InitStruct->ADC_SamplingPrescaler; - /* Set SPEN bit (sampling and conversion prescalers are different */ - ADC->CLR1 = (ADC->CLR1 | ADC_SPEN_Mask); - } - - /* Clear first channel to be converted FCH[3:0] bits */ - ADC->CLR2 &= ADC_FirstChannel_Mask; - /* Set the first channel to be converted */ - ADC->CLR2 |= ADC_InitStruct->ADC_FirstChannel; - /* Clear number of channels to be converted NCH[3:0] bits */ - ADC->CLR2 &= ADC_ChannelNumber_Mask; - /* Set the number of channels to be converted */ - ADC->CLR2 |= ((ADC_InitStruct->ADC_ChannelNumber)-1<<6); -} - -/******************************************************************************* -* Function Name : ADC_StructInit -* Description : Fills each ADC_InitStruct member with its default value. -* Input : - ADC_InitStruct: pointer to an ADC_InitTypeDef structure - which will be initialized. -* Output : None -* Return : None. -*******************************************************************************/ -void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) -{ - /* Initialize the ADC_ConversionMode member */ - ADC_InitStruct->ADC_ConversionMode = ADC_ConversionMode_OneShot; - - /* Initialize the ADC_ExtTrigger member */ - ADC_InitStruct->ADC_ExtTrigger = ADC_ExtTrigger_Disable; - - /* Initialize the ADC_AutoClockOff member */ - ADC_InitStruct->ADC_AutoClockOff = ADC_AutoClockOff_Disable; - - /* Initialize the ADC_SamplingPrescaler member */ - ADC_InitStruct->ADC_SamplingPrescaler = 0; - - /* Initialize the ADC_ConversionPrescaler member */ - ADC_InitStruct->ADC_ConversionPrescaler = 0; - - /* Initialize the ADC_FirstChannel member */ - ADC_InitStruct->ADC_FirstChannel = ADC_CHANNEL0; - - /* Initialize the ADC_ChannelNumber member */ - ADC_InitStruct->ADC_ChannelNumber = 1; - } - -/******************************************************************************* -* Function Name : ADC_StartCalibration -* Description : Starts the ADC Calibration. Calibration average enabled/disabled. -* Input : - ADC_CalibAverage: Enables or disables ADC calibration average. -* This parameter can be one of the following values: -* - ADC_CalibAverage_Enable: enable calibration average -* - ADC_CalibAverage_Disable: disable calibration average -* Output : None -* Return : None -*******************************************************************************/ -void ADC_StartCalibration(u16 ADC_CalibAverage) -{ - if (ADC_CalibAverage == ADC_CalibAverage_Enable) - { - /* Enable ADC Calibration Average */ - ADC->CLR4 &= ADC_CalibAverage_Enable; - } - else - { - /* Disable ADC Calibration Average */ - ADC->CLR4 |= ADC_CalibAverage_Disable; - } - - /* Start Calibration */ - ADC->CLR0 |= ADC_Calibration_ON; -} - -/******************************************************************************* -* Function Name : ADC_GetCalibrationStatus -* Description : Get the ADC Calibration Status. -* Input : None -* Output : None -* Return : The NewState of the ADC calibration (SET or RESET). -*******************************************************************************/ -FlagStatus ADC_GetCalibrationStatus(void) -{ - /* Check the status of the ADC calibration */ - if((ADC->CLR0 & ADC_Calibration_Mask) != RESET) - { - /* Return SET if ADC Calibration is on going */ - return SET; - } - else - { - /* Return RESET if ADC Calibration is finished */ - return RESET; - } -} - -/******************************************************************************* -* Function Name : ADC_ConversionCmd -* Description : Starts or stops the ADC conversion. -* Input : - ADC_Conversion: specifies the ADC command to apply. -* This parameter can be one of the following values: -* - ADC_Conversion_Start: start conversion -* - ADC_Conversion_Stop: stop conversion -* Output : None -* Return : None -*******************************************************************************/ -void ADC_ConversionCmd (u16 ADC_Conversion) -{ - if (ADC_Conversion == ADC_Conversion_Start) - { - /* Start the ADC Conversion */ - ADC->CLR0 |= ADC_Conversion_Start; - } - else - { - /* Stop the ADC Conversion */ - ADC->CLR0 &= ADC_Conversion_Stop; - } -} - -/******************************************************************************* -* Function Name : ADC_GetSTARTBitStatus -* Description : Gets the ADC START/STOP bit Status. -* Input : None -* Output : None -* Return : The NewState of the ADC START/STOP bit (SET or RESET). -*******************************************************************************/ -FlagStatus ADC_GetSTARTBitStatus(void) -{ - /* Check the status of the ADC START/STOP bit */ - if((ADC->CLR0 & ADC_Conversion_Start) != RESET) - { - /* Return SET if ADC Conversion is started */ - return SET; - } - else - { - /* Return RESET if ADC Conversion is stopped */ - return RESET; - } -} - -/******************************************************************************* -* Function Name : ADC_Cmd -* Description : Enables the ADC peripheral or puts it in power down mode. -* - NewState: new state of the ADC peripheral. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None. -*******************************************************************************/ -void ADC_Cmd(FunctionalState NewState) -{ - if (NewState == DISABLE) - { - /* Enable ADC Power Down Mode */ - ADC->CLR4 |= ADC_PowerDown_Enable; - } - else - { - /* Disable ADC Power Down Mode */ - ADC->CLR4 &= ADC_PowerDown_Disable; - } -} - -/******************************************************************************* -* Function Name : ADC_AutoClockOffConfig -* Description : Enables or disables the Auto clock off feature. -* - NewState: new state of the Auto clock off feature. This -* parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None. -*******************************************************************************/ -void ADC_AutoClockOffConfig(FunctionalState NewState) -{ - if (NewState == ENABLE) - { - /* Enable ADC Auto Clock Off */ - ADC->CLR4 |= ADC_AutoClockOff_Enable; - } - else - { - /* Disable ADC Auto Clock Off */ - ADC->CLR4 &= ADC_AutoClockOff_Disable; - } -} - -/******************************************************************************* -* Function Name : ADC_AnalogWatchdogConfig -* Description : Configures the analog input channel to be used for the selected -* Analog Watchdog and defines its corresponding High and Low -* threshold values. -* Input : - ADC_AnalogWatchdog: specifies the analog watchdog which will -* be affected to the desired converted channel. This parameter -* can be one of the following values: -* - ADC_AnalogWatchdog0: select analog watchdog 0 -* - ADC_AnalogWatchdog1: select analog watchdog 1 -* - ADC_AnalogWatchdog2: select analog watchdog 2 -* - ADC_AnalogWatchdog3: select analog watchdog 3 -* - ADC_CHANNEL: specifies the channel linked to the selected -* analog watchdog. This parameter can be ADC_CHANNELx where x -* can be (0..15) -* - LowThreshold: Low Threshold for the selected Analog watchdog -* - HighThreshold: High Threshold for the selected Analog watchdog -* Output : None -* Return : None -*******************************************************************************/ -void ADC_AnalogWatchdogConfig(u16 ADC_AnalogWatchdog, u8 ADC_CHANNEL, - u16 LowThreshold, u16 HighThreshold) -{ - switch (ADC_AnalogWatchdog) - { - /* Set the selected channel and their corresponding High and Low thresholds */ - case ADC_AnalogWatchdog0 : - ADC->TRA0 = (ADC->TRA0 & ADC_AnalogWatchdogChannel_Mask) | ((u16) ADC_CHANNEL<<10); - ADC->TRA0 = (ADC->TRA0 & ADC_Threshold_Mask) | HighThreshold; - ADC->TRB0 = (ADC->TRB0 & ADC_Threshold_Mask) | LowThreshold; - break; - - case ADC_AnalogWatchdog1 : - ADC->TRA1 = (ADC->TRA1 & ADC_AnalogWatchdogChannel_Mask) | ((u16) ADC_CHANNEL<<10); - ADC->TRA1 = (ADC->TRA1 & ADC_Threshold_Mask) | HighThreshold; - ADC->TRB1 = (ADC->TRB1 & ADC_Threshold_Mask) | LowThreshold; - break; - - case ADC_AnalogWatchdog2 : - ADC->TRA2 = (ADC->TRA2 & ADC_AnalogWatchdogChannel_Mask) | ((u16) ADC_CHANNEL<<10); - ADC->TRA2 = (ADC->TRA2 & ADC_Threshold_Mask) | HighThreshold; - ADC->TRB2 = (ADC->TRB2 & ADC_Threshold_Mask) | LowThreshold; - break; - - case ADC_AnalogWatchdog3 : - ADC->TRA3 = (ADC->TRA3 & ADC_AnalogWatchdogChannel_Mask) | ((u16) ADC_CHANNEL<<10); - ADC->TRA3 = (ADC->TRA3 & ADC_Threshold_Mask) | HighThreshold; - ADC->TRB3 = (ADC->TRB3 & ADC_Threshold_Mask) | LowThreshold; - break; - - default: - break; - } -} - -/******************************************************************************* -* Function Name : ADC_AnalogWatchdogCmd -* Description : Enables or disables the selected analog Watchdog. -* Input : - ADC_AnalogWatchdog: specifies the analog watchdog to be -* enabled or disabled. This parameter can be one of the -* following values: -* - ADC_AnalogWatchdog0: select analog watchdog 0 -* - ADC_AnalogWatchdog1: select analog watchdog 1 -* - ADC_AnalogWatchdog2: select analog watchdog 2 -* - ADC_AnalogWatchdog3: select analog watchdog 3 -* - NewState: new state of the specified analog watchdog. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None. -*******************************************************************************/ -void ADC_AnalogWatchdogCmd(u16 ADC_AnalogWatchdog, FunctionalState NewState) -{ - if (NewState == ENABLE) - { - /* Enable the selected ADC AnalogWatchdogx */ - switch (ADC_AnalogWatchdog) - { - case ADC_AnalogWatchdog0 : - ADC->TRB0 |= ADC_AnalogWatchdog_Enable; - break; - - case ADC_AnalogWatchdog1 : - ADC->TRB1 |= ADC_AnalogWatchdog_Enable; - break; - - case ADC_AnalogWatchdog2 : - ADC->TRB2 |= ADC_AnalogWatchdog_Enable; - break; - - case ADC_AnalogWatchdog3 : - ADC->TRB3 |= ADC_AnalogWatchdog_Enable; - break; - - default: - break; - } - } - else - { - /* Disable the selected ADC AnalogWatchdogx */ - switch (ADC_AnalogWatchdog) - { - case ADC_AnalogWatchdog0 : - ADC->TRB0 &= ADC_AnalogWatchdog_Disable; - break; - - case ADC_AnalogWatchdog1 : - ADC->TRB1 &= ADC_AnalogWatchdog_Disable; - break; - - case ADC_AnalogWatchdog2 : - ADC->TRB2 &= ADC_AnalogWatchdog_Disable; - break; - - case ADC_AnalogWatchdog3 : - ADC->TRB3 &= ADC_AnalogWatchdog_Disable; - break; - - default: - break; - } - } -} - -/******************************************************************************* -* Function Name : ADC_GetAnalogWatchdogResult -* Description : Returns the comparison result of the selected analog watchdog. -* Input : - ADC_AnalogWatchdog: specifies the analog watchdog channel -* which its comparison result will be returned. This parameter -* can be one of the following values: -* - ADC_AnalogWatchdog0: select analog watchdog 0 -* - ADC_AnalogWatchdog1: select analog watchdog 1 -* - ADC_AnalogWatchdog2: select analog watchdog 2 -* - ADC_AnalogWatchdog3: select analog watchdog 3 -* Output : None -* Return : The analog watchdog comparaison result value -*******************************************************************************/ -u16 ADC_GetAnalogWatchdogResult(u16 ADC_AnalogWatchdog) -{ - /* Return the selected ADC AnalogWatchdogx comparaison result */ - switch(ADC_AnalogWatchdog) - { - case ADC_AnalogWatchdog0 : - return ((ADC->PBR & ADC_AnalogWatchdog)>>4); - - case ADC_AnalogWatchdog1 : - return ((ADC->PBR & ADC_AnalogWatchdog)>>6); - - case ADC_AnalogWatchdog2 : - return ((ADC->PBR & ADC_AnalogWatchdog)>>8); - - case ADC_AnalogWatchdog3 : - return ((ADC->PBR & ADC_AnalogWatchdog)>>10); - - default : return (0xFF); /* if a wrong value of ADC_AnalogWatchdog is selected */ - } -} - -/******************************************************************************* -* Function Name : ADC_InjectedConversionConfig -* Description : Configures the start trigger level for the injected channels -* and the injected analog input channels to be converted. -* Input : - ADC_Injec_ExtTrigger: specifies the start trigger level. -* This parameter can be one of the following values: -* - ADC_Injec_ExtTrigger_Disable : external trigger disabled -* - ADC_Injec_ExtTrigger_RisingEdge: external trigger -* configured as rising edge of PWM Timer TRGO signal -* - ADC_Injec_ExtTrigger_FallingEdge: external trigger -* configured as falling edge of PWM Timer TRGO signal -* - FirstChannel: specifies the first injected channel to be -* converted. -* This parameter can be ADC_CHANNELx where x can be (0..15). -* - ChannelNumber: specifies the Number of the injected channels -* to be converted. This parameter can be a value from 1 to 16. -* Output : None -* Return : None -*******************************************************************************/ -void ADC_InjectedConversionConfig(u16 ADC_Injec_ExtTrigger, u8 FirstChannel, u8 ChannelNumber) -{ - /* Configure the external start injected conversion trigger */ - switch (ADC_Injec_ExtTrigger) - { - case ADC_Injec_ExtTrigger_Disable : - /* Disable the external trigger and start the injected conversion by software */ - ADC->CLR3 &= ADC_Injec_ExtTrigger_Disable ; - break; - case ADC_Injec_ExtTrigger_RisingEdge : - /* Start injected conversion on rising edge of the external trigger (PWM) */ - ADC->CLR3 |= ADC_Injec_ExtTrigger_RisingEdge; - break; - case ADC_Injec_ExtTrigger_FallingEdge : - /* Start injected conversion on falling edge of the external trigger (PWM) */ - ADC->CLR3 |= ADC_Injec_ExtTrigger_Enable; - ADC->CLR3 &= ADC_Injec_ExtTrigger_FallingEdge; - break; - - default: - break; - } - - /* Clear first injected channel to be converted JFCH[3:0] bits */ - ADC->CLR3 &= ADC_FirstChannel_Mask; - /* Set the first injected channel to be converted */ - ADC->CLR3 |= FirstChannel; - /* Clear number of injected channels to be converted JNCH[3:0] bits */ - ADC->CLR3 &= ADC_ChannelNumber_Mask; - /* Set the number of injected channels to be converted */ - ADC->CLR3 |= ((ChannelNumber-1)<<6); -} - -/******************************************************************************* -* Function Name : ADC_StartInjectedConversion -* Description : Starts by software the conversion of the injected input channels. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void ADC_StartInjectedConversion(void) -{ - /* Start the injected ADC Conversion */ - ADC->CLR3 |= ADC_Injec_ConversionStart; -} - -/******************************************************************************* -* Function Name : ADC_GetConversionValue -* Description : Reads the conversion result from the appropriate data register. -* Input : - ADC_CHANNEL :specifies the ADC channel which its conversion -* value have to be returned. This parameter can be ADC_CHANNELx -* where x can be (0..15) to select channelx -* Output : None -* Return : The returned value holds the conversion result of the selected -* channel. -*******************************************************************************/ -u16 ADC_GetConversionValue(u8 ADC_CHANNEL) -{ - /* Return the conversion result of the selected channel */ - return *((u16 *)(ADC_BASE + ((ADC_CHANNEL<<2) + ADC_DataRegisterOffset))); -} - -/******************************************************************************* -* Function Name : ADC_ITConfig -* Description : Enables or disables the specified ADC interrupts. -* Input : - ADC_IT: specifies the ADC interrupts to be enabled or disabled. -* This parameter can be any combination of the following values: -* - ADC_IT_ECH: End of chain conversion interrupt -* - ADC_IT_EOC: End of channel conversion interrupt -* - ADC_IT_JECH: Injected end of chain conversion interrupt -* - ADC_IT_JEOC: Injected end of channel conversion interrupt -* - ADC_IT_AnalogWatchdog0_LowThreshold: -* Analog Watchdog 0 LowThreshold interrupt -* - ADC_IT_AnalogWatchdog0_HighThreshold: -* Analog Watchdog 0 HighThreshold interrupt -* - ADC_IT_AnalogWatchdog1_LowThreshold: -* Analog Watchdog 1 LowThreshold interrupt -* - ADC_IT_AnalogWatchdog1_HighThreshold: -* Analog Watchdog 1 HighThreshold interrupt -* - ADC_IT_AnalogWatchdog2_LowThreshold: -* Analog Watchdog 2 LowThreshold interrupt -* - ADC_IT_AnalogWatchdog2_HighThreshold: -* Analog Watchdog 2 HighThreshold interrupt -* - ADC_IT_AnalogWatchdog3_LowThreshold: -* Analog Watchdog 3 LowThreshold interrupt -* - ADC_IT_AnalogWatchdog3_HighThreshold: -* Analog Watchdog 5 HighThreshold interrupt -* - ADC_IT_ALL: All interrupts -* - NewState: new state of the specified ADC interrupts. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void ADC_ITConfig(u16 ADC_IT, FunctionalState NewState) -{ - if (NewState == ENABLE) - { - /* Enable the selected ADC interrupts */ - ADC->IMR |= ADC_IT; - } - else - { - /* Disable the selected ADC interrupts */ - ADC->IMR &= ~ADC_IT; - } -} - -/******************************************************************************* -* Function Name : ADC_DMAConfig -* Description : Configures the ADC’s DMA interface. -* Input : - ADC_DMA_CHANNEL: specifies the channels to be enabled or -* disabled for DMA transfer. This parameter can be any -* combination of ADC_DMA_CHANNELx where x can be (0..15). -* - NewState: new state of the specified ADC DMA channels. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void ADC_DMAConfig(u16 ADC_DMA_CHANNEL, FunctionalState NewState) -{ - if(NewState == ENABLE) - { - /* Enable DMA for the selected channels */ - ADC->DMAR |= ADC_DMA_CHANNEL ; - } - else - { - /* Disable DMA for the selected channels */ - ADC->DMAR &= ~ADC_DMA_CHANNEL; - } -} - -/******************************************************************************* -* Function Name : ADC_DMACmd -* Description : Enable or disable the DMA transfer for the ADC. -* Input : - ADC_DMA: specifies the DMA command. This parameter can be -* one of the following values: -* - ADC_DMA_Disable: disable the DMA capability -* - ADC_DMA_Enable: enabled by setting the global -* enable bit -* - ADC_DMA_ExtTrigger_HighLevel: enabled by detection of -* high level of TIM2 OC2 signal -* - ADC_DMA_ExtTrigger_LowLevel: enabled by detection of -* low level of TIM2 OC2 signal -* Output : None -* Return : None -*******************************************************************************/ -void ADC_DMACmd(u16 ADC_DMA) -{ - /* Configure the DMA external trigger enable */ - switch (ADC_DMA) - { - case ADC_DMA_Disable : - /* Disable DMA transfer */ - ADC->DMAE &= ADC_DMA_Disable; - break; - - case ADC_DMA_Enable : - /* Enable DMA transfer */ - ADC->DMAE |= ADC_DMA_Enable; - break; - - case ADC_DMA_ExtTrigger_HighLevel : - /* Enable DMA transfer on high level of the external trigger (TIM2) */ - ADC->DMAE &= ADC_DMA_Disable; - ADC->DMAE |= ADC_DMA_ExtTrigger_HighLevel; - break; - - case ADC_DMA_ExtTrigger_LowLevel : - /* Enable DMA transfer on low level of the external trigger (TIM2) */ - ADC->DMAE |= ADC_DMA_ExtEnable_Mask; - ADC->DMAE &= ADC_DMA_ExtTrigger_LowLevel; - break; - - default: - break; - } -} - -/******************************************************************************* -* Function Name : ADC_GetDMAFirstEnabledChannel -* Description : Gets the first DMA-enabled channel configured at the time that -* DMA was last globally enabled. -* Input : None -* Output : None -* Return : The first DMA enabled channel -*******************************************************************************/ -u16 ADC_GetDMAFirstEnabledChannel(void) -{ - /* Return the DMA first enabled channel */ - return (ADC->DMAE & ADC_DMAFirstEnabledChannel_Mask); -} - -/******************************************************************************* -* Function Name : ADC_GetFlagStatus -* Description : Checks whether the specified ADC flag is set or not. -* Input : - ADC_FLAG: specifies the ADC flag to check. This parameter -* can be one of the following values: -* - ADC_FLAG_ECH: End of chain conversion Flag -* - ADC_FLAG_EOC: End of channel conversion Flag -* - ADC_FLAG_JECH: End of injected chain conversion Flag -* - ADC_FLAG_JEOC: End of injected channel conversion Flag -* - ADC_FLAG_AnalogWatchdog0_LowThreshold: -* Analog Watchdog 0 LowThreshold Flag -* - ADC_FLAG_AnalogWatchdog0_HighThreshold: -* Analog Watchdog 0 HighThreshold Flag -* - ADC_FLAG_AnalogWatchdog1_LowThreshold: -* Analog Watchdog 1 LowThreshold Flag -* - ADC_FLAG_AnalogWatchdog1_HighThreshold: -* Analog Watchdog 1 HighThreshold Flag -* - ADC_FLAG_AnalogWatchdog2_LowThreshold: -* Analog Watchdog 2 LowThreshold Flag -* - ADC_FLAG_AnalogWatchdog2_HighThreshold: -* Analog Watchdog 2 HighThreshold Flag -* - ADC_FLAG_AnalogWatchdog3_LowThreshold: -* Analog Watchdog 3 LowThreshold Flag -* - ADC_FLAG_AnalogWatchdog3_HighThreshold: -* Analog Watchdog 3 HighThreshold Flag -* Output : None -* Return : The new state of the ADC_FLAG (SET or RESET). -*******************************************************************************/ -FlagStatus ADC_GetFlagStatus(u16 ADC_FLAG) -{ - /* Check the status of the specified ADC flag */ - if((ADC->PBR & ADC_FLAG) != RESET) - { - /* Return SET if ADC_FLAG is set */ - return SET; - } - else - { - /* Return RESET if ADC_FLAG is reset */ - return RESET; - } -} - -/******************************************************************************* -* Function Name : ADC_ClearFlag -* Description : Clears the ADC’s pending flags. -* Input : - ADC_FLAG: specifies the flag to clear. This parameter can -* be any combination of the following values: -* - ADC_FLAG_ECH: End of chain conversion flag -* - ADC_FLAG_EOC: End of channel conversion flag -* - ADC_FLAG_JECH: Injected end of chain conversion flag -* - ADC_FLAG_JEOC: Injected end of channel conversion flag -* - ADC_FLAG_AnalogWatchdog0_LowThreshold: -* Analog Watchdog 0 LowThreshold flag -* - ADC_FLAG_AnalogWatchdog0_HighThreshold: -* Analog Watchdog 0 HighThreshold flag -* - ADC_FLAG_AnalogWatchdog1_LowThreshold: -* Analog Watchdog 1 LowThreshold flag -* - ADC_FLAG_AnalogWatchdog1_HighThreshold: -* Analog Watchdog 1 HighThreshold flag -* - ADC_FLAG_AnalogWatchdog2_LowThreshold: -* Analog Watchdog 2 LowThreshold flag -* - ADC_FLAG_AnalogWatchdog2_HighThreshold: -* Analog Watchdog 2 HighThreshold flag -* - ADC_FLAG_AnalogWatchdog3_LowThreshold: -* Analog Watchdog 3 LowThreshold flag -* - ADC_FLAG_AnalogWatchdog3_HighThreshold: -* Analog Watchdog 3 HighThreshold flag -* Output : None -* Return : None -*******************************************************************************/ -void ADC_ClearFlag(u16 ADC_FLAG) -{ - /* Clear the selected ADC flag */ - ADC->PBR = ADC_FLAG; -} - -/******************************************************************************* -* Function Name : ADC_GetITStatus -* Description : Checks whether the specified ADC interrupt has occured or not. -* Input : - ADC_IT: specifies the ADC interrupt source to check. This -* parameter can be one of the following values: -* - ADC_IT_ECH :End of chain conversion interrupt -* - ADC_IT_EOC :End of channel conversion interrupt -* - ADC_IT_JECH :End of injected chain conversion interrupt -* - ADC_IT_JEOC :End of injected channel conversion interrupt -* - ADC_IT_AnalogWatchdog0_LowThreshold: -* Analog Watchdog 0 LowThreshold interrupt -* - ADC_IT_AnalogWatchdog0_HighThreshold: -* Analog Watchdog 0 HighThreshold interrupt -* - ADC_IT_AnalogWatchdog1_LowThreshold: -* Analog Watchdog 1 LowThreshold interrupt -* - ADC_IT_AnalogWatchdog1_HighThreshold: -* Analog Watchdog 1 HighThreshold interrupt -* - ADC_IT_AnalogWatchdog2_LowThreshold: -* Analog Watchdog 2 LowThreshold interrupt -* - ADC_IT_AnalogWatchdog2_HighThreshold: -* Analog Watchdog 2 HighThreshold interrupt -* - ADC_IT_AnalogWatchdog3_LowThreshold: -* Analog Watchdog 3 LowThreshold interrupt -* - ADC_IT_AnalogWatchdog3_HighThreshold: -* Analog Watchdog 3 HighThreshold interrupt -* Output : None -* Return : The new state of the ADC_IT (SET or RESET). -*******************************************************************************/ -ITStatus ADC_GetITStatus(u16 ADC_IT) -{ - /* Check the status of the specified ADC interrupt */ - if((ADC->PBR & ADC_IT) != RESET) - { - /* Return SET if the ADC interrupt flag is set */ - return SET; - } - else - { - /* Return RESET if the ADC interrupt flag is reset */ - return RESET; - } -} - -/******************************************************************************* -* Function Name : ADC_ClearITPendingBit -* Description : Clears the ADC’s interrupt pending bits. -* Input : - ADC_IT: specifies the interrupt pending bit to clear. This -* parameter can be can be any combination of the following -* values: -* - ADC_IT_ECH: End of chain conversion interrupt -* - ADC_IT_EOC: End of channel conversion interrupt -* - ADC_IT_JECH: Injected end of chain conversion interrupt -* - ADC_IT_JEOC: Injected end of channel conversion interrupt -* - ADC_IT_AnalogWatchdog0_LowThreshold: -* Analog Watchdog 0 LowThreshold interrupt -* - ADC_IT_AnalogWatchdog0_HighThreshold: -* Analog Watchdog 0 HighThreshold interrupt -* - ADC_IT_AnalogWatchdog1_LowThreshold: -* Analog Watchdog 1 LowThreshold interrupt -* - ADC_IT_AnalogWatchdog1_HighThreshold: -* Analog Watchdog 1 HighThreshold interrupt -* - ADC_IT_AnalogWatchdog2_LowThreshold: -* Analog Watchdog 2 LowThreshold interrupt -* - ADC_IT_AnalogWatchdog2_HighThreshold: -* Analog Watchdog 2 HighThreshold interrupt -* - ADC_IT_AnalogWatchdog3_LowThreshold: -* Analog Watchdog 3 LowThreshold interrupt -* - ADC_IT_AnalogWatchdog3_HighThreshold: -* Analog Watchdog 5 HighThreshold interrupt -* Output : None -* Return : None -*******************************************************************************/ -void ADC_ClearITPendingBit(u16 ADC_IT) -{ - /* Clear the selected ADC interrupts pending bits */ - ADC->PBR = ADC_IT; -} - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_can.c b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_can.c deleted file mode 100644 index 0472200ba..000000000 --- a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_can.c +++ /dev/null @@ -1,765 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_can.c -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file provides all the CAN software functions. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -#include "75x_can.h" -#include "75x_mrcc.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/*----------------------------------------------------------------------------*/ -/* Macro Name : xxx_ID_MSK, xxx_ID_ARB */ -/* Description : Form the Mask and Arbitration registers value to filter */ -/* a range of identifiers or a fixed identifier, for standard*/ -/* and extended IDs */ -/*----------------------------------------------------------------------------*/ -#define RANGE_ID_MSK(range_start, range_end) (~((range_end) - (range_start))) -#define RANGE_ID_ARB(range_start, range_end) ((range_start) & (range_end)) - -#define FIXED_ID_MSK(id) RANGE_ID_MSK((id), (id)) -#define FIXED_ID_ARB(id) RANGE_ID_ARB((id), (id)) - -#define STD_RANGE_ID_MSK(range_start, range_end) ((u16)((RANGE_ID_MSK((range_start), (range_end)) & 0x7FF) << 2)) -#define STD_RANGE_ID_ARB(range_start, range_end) ((u16)(RANGE_ID_ARB((range_start), (range_end)) << 2)) - -#define STD_FIXED_ID_MSK(id) ((u16)((FIXED_ID_MSK(id) & 0x7FF) << 2)) -#define STD_FIXED_ID_ARB(id) ((u16)(FIXED_ID_ARB(id) << 2)) - -#define EXT_RANGE_ID_MSK_L(range_start, range_end) ((u16)(RANGE_ID_MSK((range_start), (range_end)) >> 11)) -#define EXT_RANGE_ID_MSK_H(range_start, range_end) ((u16)(STD_RANGE_ID_MSK((range_start), (range_end)) | ((RANGE_ID_MSK((range_start), (range_end)) >> 27) & 0x03))) -#define EXT_RANGE_ID_ARB_L(range_start, range_end) ((u16)(RANGE_ID_ARB((range_start), (range_end)) >> 11)) -#define EXT_RANGE_ID_ARB_H(range_start, range_end) ((u16)(STD_RANGE_ID_ARB((range_start), (range_end)) | ((RANGE_ID_ARB((range_start), (range_end)) >> 27) & 0x03))) - -#define EXT_FIXED_ID_MSK_L(id) ((u16)(FIXED_ID_MSK(id) >> 11)) -#define EXT_FIXED_ID_MSK_H(id) ((u16)(STD_FIXED_ID_MSK(id) | ((FIXED_ID_MSK(id) >> 27) & 0x03))) -#define EXT_FIXED_ID_ARB_L(id) ((u16)(FIXED_ID_ARB(id) >> 11)) -#define EXT_FIXED_ID_ARB_H(id) ((u16)(STD_FIXED_ID_ARB(id) | ((FIXED_ID_ARB(id) >> 27) & 0x03))) - -/* macro to format the timing register value from the timing parameters*/ -#define CAN_TIMING(tseg1, tseg2, sjw, brp) ((((tseg2-1) & 0x07) << 12) | (((tseg1-1) & 0x0F) << 8) | (((sjw-1) & 0x03) << 6) | ((brp-1) & 0x3F)) - -/* Private variables ---------------------------------------------------------*/ -/* array of pre-defined timing parameters for standard bitrates*/ -u16 CanTimings[] = { /* value bitrate NTQ TSEG1 TSEG2 SJW BRP */ - CAN_TIMING(11, 4, 4, 5), /* 0x3AC4 100 kbit/s 16 11 4 4 5 */ - CAN_TIMING(11, 4, 4, 4), /* 0x3AC3 125 kbit/s 16 11 4 4 4 */ - CAN_TIMING( 4, 3, 3, 4), /* 0x2383 250 kbit/s 8 4 3 3 4 */ - CAN_TIMING(13, 2, 1, 1), /* 0x1C00 500 kbit/s 16 13 2 1 1 */ - CAN_TIMING( 4, 3, 1, 1), /* 0x2300 1 Mbit/s 8 4 3 1 1 */ -}; - -/* Private function prototypes -----------------------------------------------*/ -static u32 GetFreeIF(void); -/* Private functions ---------------------------------------------------------*/ - -/******************************************************************************* -* Function Name : CAN_DeInit -* Description : Deinitializes the CAN peripheral registers to their default -* reset values. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void CAN_DeInit (void) -{ - /* Reset the CAN registers values*/ - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_CAN,ENABLE); - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_CAN,DISABLE); -} - -/******************************************************************************* -* Function Name : CAN_Init -* Description : Initializes the CAN peripheral according to the specified -* parameters in the CAN_InitStruct. -* Input : CAN_InitStruct: pointer to a CAN_InitTypeDef structure that -* contains the configuration information for the CAN peripheral. -* Output : None -* Return : None -*******************************************************************************/ -void CAN_Init(CAN_InitTypeDef* CAN_InitStruct) -{ - CAN_EnterInitMode(CAN_CR_CCE | CAN_InitStruct->CAN_ConfigParameters); - CAN_SetBitrate(CAN_InitStruct->CAN_Bitrate); - CAN_LeaveInitMode(); - CAN_LeaveTestMode(); -} - -/******************************************************************************* -* Function Name : CAN_StructInit -* Description : Fills each CAN_InitStruct member with its reset value. -* Input : CAN_InitStruct : pointer to a CAN_InitTypeDef structure which -* will be initialized. -* Output : None -* Return : None. -*******************************************************************************/ -void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) -{ -/* Reset CAN init structure parameters values */ - CAN_InitStruct->CAN_ConfigParameters = 0x0; - CAN_InitStruct->CAN_Bitrate = 0x2301; -} - -/******************************************************************************* -* Function Name : CAN_SetBitrate -* Description : Setups a standard CAN bitrate. -* Input : bitrate: specifies the bit rate. -* Output : None -* Return : None -*******************************************************************************/ -void CAN_SetBitrate(u32 bitrate) -{ - CAN->BTR = CanTimings[bitrate]; /* write the predefined timing value */ - CAN->BRPR = 0; /* clear the Extended Baud Rate Prescaler */ -} - -/******************************************************************************* -* Function Name : CAN_SetTiming -* Description : Setups the CAN timing with specific parameters -* Input : - tseg1: specifies Time Segment before the sample point. -* This parameter must be a number between 1 and 16. -* - tseg2: Time Segment after the sample point. This parameter -* must be a number between 1 and 8. -* - sjw: Synchronisation Jump Width. This parameter must be -* a number between 1 and 4. -* - brp: Baud Rate Prescaler. This parameter must be a number -* between 1 and 1024. -* Output : None -* Return : None -*******************************************************************************/ -void CAN_SetTiming(u32 tseg1, u32 tseg2, u32 sjw, u32 brp) -{ - CAN->BTR = CAN_TIMING(tseg1, tseg2, sjw, brp); - CAN->BRPR = ((brp-1) >> 6) & 0x0F; -} - -/******************************************************************************* -* Function Name : GetFreeIF -* Description : Searchs the first free message interface, starting from 0. -* Input : None -* Output : None -* Return : A free message interface number (0 or 1) if found, else 2 -*******************************************************************************/ -static u32 GetFreeIF(void) -{ - if ((CAN->sMsgObj[0].CRR & CAN_CRR_BUSY) == 0) - return 0; - else if ((CAN->sMsgObj[1].CRR & CAN_CRR_BUSY) == 0) - return 1; - else - return 2; -} - -/******************************************************************************* -* Function Name : CAN_SetUnusedMsgObj -* Description : Configures the message object as unused -* Input : msgobj: specifies the Message object number, from 0 to 31. -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Interface to treat the message -* - ERROR: No interface found to treat the message -*******************************************************************************/ -ErrorStatus CAN_SetUnusedMsgObj(u32 msgobj) -{ - u32 msg_if=0; - - if ((msg_if = GetFreeIF()) == 2) - { - return ERROR; - } - - CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD - | CAN_CMR_MASK - | CAN_CMR_ARB - | CAN_CMR_CONTROL - | CAN_CMR_DATAA - | CAN_CMR_DATAB; - - CAN->sMsgObj[msg_if].M1R = 0; - CAN->sMsgObj[msg_if].M2R = 0; - - CAN->sMsgObj[msg_if].A1R = 0; - CAN->sMsgObj[msg_if].A2R = 0; - - CAN->sMsgObj[msg_if].MCR = 0; - - CAN->sMsgObj[msg_if].DA1R = 0; - CAN->sMsgObj[msg_if].DA2R = 0; - CAN->sMsgObj[msg_if].DB1R = 0; - CAN->sMsgObj[msg_if].DB2R = 0; - - CAN->sMsgObj[msg_if].CRR = 1 + msgobj; - - return SUCCESS; -} - -/******************************************************************************* -* Function Name : CAN_SetTxMsgObj -* Description : Configures the message object as TX. -* Input : - msgobj: specifies the Message object number, from 0 to 31. -* - idType: specifies the identifier type of the frames that -* will be transmitted using this message object. -* This parameter can be one of the following values: -* - CAN_STD_ID (standard ID, 11-bit) -* - CAN_EXT_ID (extended ID, 29-bit) -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Interface to treat the message -* - ERROR: No interface found to treat the message -*******************************************************************************/ -ErrorStatus CAN_SetTxMsgObj(u32 msgobj, u32 idType) -{ - u32 msg_if=0; - - if ((msg_if = GetFreeIF()) == 2) - { - return ERROR; - } - - CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD - | CAN_CMR_MASK - | CAN_CMR_ARB - | CAN_CMR_CONTROL - | CAN_CMR_DATAA - | CAN_CMR_DATAB; - - CAN->sMsgObj[msg_if].M1R = 0; - CAN->sMsgObj[msg_if].A1R = 0; - - if (idType == CAN_STD_ID) - { - CAN->sMsgObj[msg_if].M2R = CAN_M2R_MDIR; - CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_DIR; - } - else - { - CAN->sMsgObj[msg_if].M2R = CAN_M2R_MDIR | CAN_M2R_MXTD; - CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_DIR | CAN_A2R_XTD; - } - - CAN->sMsgObj[msg_if].MCR = CAN_MCR_TXIE | CAN_MCR_EOB; - - CAN->sMsgObj[msg_if].DA1R = 0; - CAN->sMsgObj[msg_if].DA2R = 0; - CAN->sMsgObj[msg_if].DB1R = 0; - CAN->sMsgObj[msg_if].DB2R = 0; - - CAN->sMsgObj[msg_if].CRR = 1 + msgobj; - - return SUCCESS; -} - -/******************************************************************************* -* Function Name : CAN_SetRxMsgObj -* Description : Configures the message object as RX. -* Input : - msgobj: specifies the Message object number, from 0 to 31. -* - idType: specifies the identifier type of the frames that -* will be transmitted using this message object. -* This parameter can be one of the following values: -* - CAN_STD_ID (standard ID, 11-bit) -* - CAN_EXT_ID (extended ID, 29-bit) -* - idLow: specifies the low part of the identifier range used -* for acceptance filtering. -* - idHigh: specifies the high part of the identifier range -* used for acceptance filtering. -* - singleOrFifoLast: specifies the end-of-buffer indicator. -* This parameter can be one of the following values: -* - TRUE: for a single receive object or a FIFO receive -* object that is the last one of the FIFO. -* - FALSE: for a FIFO receive object that is not the -* last one. -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Interface to treat the message -* - ERROR: No interface found to treat the message -*******************************************************************************/ -ErrorStatus CAN_SetRxMsgObj(u32 msgobj, u32 idType, u32 idLow, u32 idHigh, bool singleOrFifoLast) -{ - u32 msg_if=0; - - if ((msg_if = GetFreeIF()) == 2) - { - return ERROR; - } - - CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD - | CAN_CMR_MASK - | CAN_CMR_ARB - | CAN_CMR_CONTROL - | CAN_CMR_DATAA - | CAN_CMR_DATAB; - - if (idType == CAN_STD_ID) - { - CAN->sMsgObj[msg_if].M1R = 0; - CAN->sMsgObj[msg_if].M2R = STD_RANGE_ID_MSK(idLow, idHigh); - - CAN->sMsgObj[msg_if].A1R = 0; - CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | STD_RANGE_ID_ARB(idLow, idHigh); - } - else - { - CAN->sMsgObj[msg_if].M1R = EXT_RANGE_ID_MSK_L(idLow, idHigh); - CAN->sMsgObj[msg_if].M2R = CAN_M2R_MXTD | EXT_RANGE_ID_MSK_H(idLow, idHigh); - - CAN->sMsgObj[msg_if].A1R = EXT_RANGE_ID_ARB_L(idLow, idHigh); - CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_XTD | EXT_RANGE_ID_ARB_H(idLow, idHigh); - } - - CAN->sMsgObj[msg_if].MCR = CAN_MCR_RXIE | CAN_MCR_UMASK | (singleOrFifoLast ? CAN_MCR_EOB : 0); - - CAN->sMsgObj[msg_if].DA1R = 0; - CAN->sMsgObj[msg_if].DA2R = 0; - CAN->sMsgObj[msg_if].DB1R = 0; - CAN->sMsgObj[msg_if].DB2R = 0; - - CAN->sMsgObj[msg_if].CRR = 1 + msgobj; - - return SUCCESS; -} - -/******************************************************************************* -* Function Name : CAN_InvalidateAllMsgObj -* Description : Configures all the message objects as unused. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void CAN_InvalidateAllMsgObj(void) -{ - u32 i=0; - for (i = 0; i < 32; i++) - CAN_SetUnusedMsgObj(i); -} - - -/******************************************************************************* -* Function Name : CAN_ReleaseMessage -* Description : Releases the message object -* Input : - msgobj: specifies the Message object number, from 0 to 31. -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Interface to treat the message -* - ERROR: No interface found to treat the message -*******************************************************************************/ -ErrorStatus CAN_ReleaseMessage(u32 msgobj) -{ - u32 msg_if=0; - - if ((msg_if = GetFreeIF()) == 2) - { - return ERROR; - } - - CAN->sMsgObj[msg_if].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQSTNEWDAT; - CAN->sMsgObj[msg_if].CRR = 1 + msgobj; - - return SUCCESS; -} - -/******************************************************************************* -* Function Name : CAN_SendMessage -* Description : Start transmission of a message -* Input : - msgobj: specifies the Message object number, from 0 to 31. -* : - pCanMsg: pointer to the message structure containing data -* to transmit. -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Transmission OK -* - ERROR: No transmission -*******************************************************************************/ -ErrorStatus CAN_SendMessage(u32 msgobj, canmsg* pCanMsg) -{ - if (CAN->sMsgObj[0].CRR & CAN_CRR_BUSY) - { - return ERROR; - } - - CAN->SR &= ~CAN_SR_TXOK; - - /* read the Arbitration and Message Control*/ - CAN->sMsgObj[0].CMR = CAN_CMR_ARB | CAN_CMR_CONTROL; - - CAN->sMsgObj[0].CRR = 1 + msgobj; - - if (CAN->sMsgObj[0].CRR & CAN_CRR_BUSY) - { - return ERROR; - } - - /* update the contents needed for transmission*/ - CAN->sMsgObj[0].CMR = CAN_CMR_WRRD - | CAN_CMR_ARB - | CAN_CMR_CONTROL - | CAN_CMR_DATAA - | CAN_CMR_DATAB; - - if ((CAN->sMsgObj[0].A2R & CAN_A2R_XTD) == 0) - { - /* standard ID*/ - CAN->sMsgObj[0].A1R = 0; - CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | STD_FIXED_ID_ARB(pCanMsg->Id); - } - else - { - /* extended ID*/ - CAN->sMsgObj[0].A1R = EXT_FIXED_ID_ARB_L(pCanMsg->Id); - CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | EXT_FIXED_ID_ARB_H(pCanMsg->Id); - } - - CAN->sMsgObj[0].MCR = (CAN->sMsgObj[0].MCR & 0xFEF0) | CAN_MCR_NEWDAT | CAN_MCR_TXRQST | pCanMsg->Dlc; - - CAN->sMsgObj[0].DA1R = ((u16)pCanMsg->Data[1]<<8) | pCanMsg->Data[0]; - CAN->sMsgObj[0].DA2R = ((u16)pCanMsg->Data[3]<<8) | pCanMsg->Data[2]; - CAN->sMsgObj[0].DB1R = ((u16)pCanMsg->Data[5]<<8) | pCanMsg->Data[4]; - CAN->sMsgObj[0].DB2R = ((u16)pCanMsg->Data[7]<<8) | pCanMsg->Data[6]; - - CAN->sMsgObj[0].CRR = 1 + msgobj; - - return SUCCESS; -} - -/******************************************************************************* -* Function Name : CAN_ReceiveMessage -* Description : Gets the message, if received. -* Input : - msgobj: specifies the Message object number, from 0 to 31. -* - release: specifies the message release indicator. -* This parameter can be one of the following values: -* - TRUE: the message object is released when getting -* the data. -* - FALSE: the message object is not released. -* - pCanMsg: pointer to the message structure where received -* data is copied. -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Reception OK -* - ERROR: No message pending -*******************************************************************************/ -ErrorStatus CAN_ReceiveMessage(u32 msgobj, bool release, canmsg* pCanMsg) -{ - if (!CAN_IsMessageWaiting(msgobj)) - { - return ERROR; - } - - CAN->SR &= ~CAN_SR_RXOK; - - /* read the message contents*/ - CAN->sMsgObj[1].CMR = CAN_CMR_MASK - | CAN_CMR_ARB - | CAN_CMR_CONTROL - | CAN_CMR_CLRINTPND - | (release ? CAN_CMR_TXRQSTNEWDAT : 0) - | CAN_CMR_DATAA - | CAN_CMR_DATAB; - - CAN->sMsgObj[1].CRR = 1 + msgobj; - - if (CAN->sMsgObj[1].CRR & CAN_CRR_BUSY) - { - return ERROR; - } - - if ((CAN->sMsgObj[1].A2R & CAN_A2R_XTD) == 0) - { - /* standard ID*/ - pCanMsg->IdType = CAN_STD_ID; - pCanMsg->Id = (CAN->sMsgObj[1].A2R >> 2) & 0x07FF; - } - else - { - /* extended ID*/ - pCanMsg->IdType = CAN_EXT_ID; - pCanMsg->Id = ((CAN->sMsgObj[1].A2R >> 2) & 0x07FF); - pCanMsg->Id |= ((u32)CAN->sMsgObj[1].A1R << 11); - pCanMsg->Id |= (((u32)CAN->sMsgObj[1].A2R & 0x0003) << 27); - } - - pCanMsg->Dlc = CAN->sMsgObj[1].MCR & 0x0F; - - pCanMsg->Data[0] = (u8) CAN->sMsgObj[1].DA1R; - pCanMsg->Data[1] = (u8)(CAN->sMsgObj[1].DA1R >> 8); - pCanMsg->Data[2] = (u8) CAN->sMsgObj[1].DA2R; - pCanMsg->Data[3] = (u8)(CAN->sMsgObj[1].DA2R >> 8); - pCanMsg->Data[4] = (u8) CAN->sMsgObj[1].DB1R; - pCanMsg->Data[5] = (u8)(CAN->sMsgObj[1].DB1R >> 8); - pCanMsg->Data[6] = (u8) CAN->sMsgObj[1].DB2R; - pCanMsg->Data[7] = (u8)(CAN->sMsgObj[1].DB2R >> 8); - - return SUCCESS; -} - -/******************************************************************************* -* Function Name : CAN_WaitEndOfTx -* Description : Waits until current transmission is finished. -* Input : None -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Transmission ended -* - ERROR: Transmission did not occur yet -*******************************************************************************/ -ErrorStatus CAN_WaitEndOfTx(void) -{ - if ((CAN->SR & CAN_SR_TXOK) == 0) - { - return ERROR; - } - CAN->SR &= ~CAN_SR_TXOK; - - return SUCCESS; -} - -/******************************************************************************* -* Function Name : CAN_BasicSendMessage -* Description : Starts transmission of a message in BASIC mode. This mode -* does not use the message RAM. -* Input : pCanMsg: Pointer to the message structure containing data to -* transmit. -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Transmission OK -* - ERROR: No transmission -*******************************************************************************/ -ErrorStatus CAN_BasicSendMessage(canmsg* pCanMsg) -{ - /* clear NewDat bit in IF2 to detect next reception*/ - CAN->sMsgObj[1].MCR &= ~CAN_MCR_NEWDAT; - - CAN->SR &= ~CAN_SR_TXOK; - CAN->sMsgObj[0].CMR = CAN_CMR_WRRD - | CAN_CMR_ARB - | CAN_CMR_CONTROL - | CAN_CMR_DATAA - | CAN_CMR_DATAB; - - if (pCanMsg->IdType == CAN_STD_ID) - { - /* standard ID*/ - CAN->sMsgObj[0].A1R = 0; - CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | STD_FIXED_ID_ARB(pCanMsg->Id); - } - else - { - /* extended ID*/ - CAN->sMsgObj[0].A1R = EXT_FIXED_ID_ARB_L(pCanMsg->Id); - CAN->sMsgObj[0].A2R = ((CAN->sMsgObj[0].A2R) & 0xE000) | EXT_FIXED_ID_ARB_H(pCanMsg->Id); - } - - CAN->sMsgObj[0].MCR = (CAN->sMsgObj[0].MCR & 0xFCF0) | pCanMsg->Dlc; - - CAN->sMsgObj[0].DA1R = ((u16)pCanMsg->Data[1]<<8) | pCanMsg->Data[0]; - CAN->sMsgObj[0].DA2R = ((u16)pCanMsg->Data[3]<<8) | pCanMsg->Data[2]; - CAN->sMsgObj[0].DB1R = ((u16)pCanMsg->Data[5]<<8) | pCanMsg->Data[4]; - CAN->sMsgObj[0].DB2R = ((u16)pCanMsg->Data[7]<<8) | pCanMsg->Data[6]; - - /* request transmission*/ - if (CAN->sMsgObj[0].CRR == CAN_CRR_BUSY ) - { - return ERROR; - } - - return SUCCESS; -} - -/******************************************************************************* -* Function Name : CAN_BasicReceiveMessage -* Description : Gets the message in BASIC mode, if received. This mode does -* not use the message RAM. -* Input : pCanMsg: pointer to the message structure where message is copied. -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Reception OK -* - ERROR: No message pending -*******************************************************************************/ -ErrorStatus CAN_BasicReceiveMessage(canmsg* pCanMsg) -{ - if ((CAN->sMsgObj[1].MCR & CAN_MCR_NEWDAT) == 0) - { - return ERROR; - } - - CAN->SR &= ~CAN_SR_RXOK; - - CAN->sMsgObj[1].CMR = CAN_CMR_ARB - | CAN_CMR_CONTROL - | CAN_CMR_DATAA - | CAN_CMR_DATAB; - - if ((CAN->sMsgObj[1].A2R & CAN_A2R_XTD) == 0) - { - /* standard ID*/ - pCanMsg->IdType = CAN_STD_ID; - pCanMsg->Id = (CAN->sMsgObj[1].A2R >> 2) & 0x07FF; - } - else - { - /* extended ID*/ - pCanMsg->IdType = CAN_EXT_ID; - pCanMsg->Id = ((CAN->sMsgObj[1].A2R >> 2) & 0x07FF); - pCanMsg->Id |= ((u32)CAN->sMsgObj[1].A1R << 11); - pCanMsg->Id |= (((u32)CAN->sMsgObj[1].A2R & 0x0003) << 27); - } - - pCanMsg->Dlc = CAN->sMsgObj[1].MCR & 0x0F; - - pCanMsg->Data[0] = (u8) CAN->sMsgObj[1].DA1R; - pCanMsg->Data[1] = (u8)(CAN->sMsgObj[1].DA1R >> 8); - pCanMsg->Data[2] = (u8) CAN->sMsgObj[1].DA2R; - pCanMsg->Data[3] = (u8)(CAN->sMsgObj[1].DA2R >> 8); - pCanMsg->Data[4] = (u8) CAN->sMsgObj[1].DB1R; - pCanMsg->Data[5] = (u8)(CAN->sMsgObj[1].DB1R >> 8); - pCanMsg->Data[6] = (u8) CAN->sMsgObj[1].DB2R; - pCanMsg->Data[7] = (u8)(CAN->sMsgObj[1].DB2R >> 8); - - return SUCCESS; -} - -/******************************************************************************* -* Function Name : CAN_EnterInitMode -* Description : Switchs the CAN into initialization mode. This function must -* be used in conjunction with CAN_LeaveInitMode(). -* Input : InitMask: specifies the CAN configuration in normal mode. -* Output : None -* Return : None -*******************************************************************************/ -void CAN_EnterInitMode(u8 InitMask) -{ - CAN->CR = InitMask | CAN_CR_INIT; - CAN->SR = 0; /* reset the status*/ -} - -/******************************************************************************* -* Function Name : CAN_LeaveInitMode -* Description : Leaves the initialization mode (switch into normal mode). -* This function must be used in conjunction with CAN_EnterInitMode(). -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void CAN_LeaveInitMode(void) -{ - CAN->CR &= ~(CAN_CR_INIT | CAN_CR_CCE); -} - -/******************************************************************************* -* Function Name : CAN_EnterTestMode -* Description : Switchs the CAN into test mode. This function must be used in -* conjunction with CAN_LeaveTestMode(). -* Input : TestMask: specifies the configuration in test modes. -* Output : None -* Return : None -*******************************************************************************/ -void CAN_EnterTestMode(u8 TestMask) -{ - CAN->CR |= CAN_CR_TEST; - CAN->TESTR |= TestMask; -} - -/******************************************************************************* -* Function Name : CAN_LeaveTestMode -* Description : Leaves the current test mode (switch into normal mode). -* This function must be used in conjunction with CAN_EnterTestMode(). -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void CAN_LeaveTestMode(void) -{ - CAN->CR |= CAN_CR_TEST; - CAN->TESTR &= ~(CAN_TESTR_LBACK | CAN_TESTR_SILENT | CAN_TESTR_BASIC); - CAN->CR &= ~CAN_CR_TEST; -} - -/******************************************************************************* -* Function Name : CAN_ReleaseTxMessage -* Description : Releases the transmit message object. -* Input : - msgobj: specifies the Message object number, from 0 to 31. -* Output : None -* Return : None -*******************************************************************************/ -void CAN_ReleaseTxMessage(u32 msgobj) -{ - CAN->sMsgObj[0].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQSTNEWDAT; - CAN->sMsgObj[0].CRR = 1 + msgobj; -} - -/******************************************************************************* -* Function Name : CAN_ReleaseRxMessage -* Description : Releases the receive message object. -* Input : - msgobj: specifies the Message object number, from 0 to 31. -* Output : None -* Return : None -*******************************************************************************/ -void CAN_ReleaseRxMessage(u32 msgobj) -{ - CAN->sMsgObj[1].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQSTNEWDAT; - CAN->sMsgObj[1].CRR = 1 + msgobj; -} - -/******************************************************************************* -* Function Name : CAN_IsMessageWaiting -* Description : Tests the waiting status of a received message. -* Input : - msgobj: specifies the Message object number, from 0 to 31. -* Output : None -* Return : A non-zero value if the corresponding message object has -* received a message waiting to be copied, else 0. -*******************************************************************************/ -u32 CAN_IsMessageWaiting(u32 msgobj) -{ - return (msgobj < 16 ? CAN->ND1R & (1 << msgobj) : CAN->ND2R & (1 << (msgobj-16))); -} - -/******************************************************************************* -* Function Name : CAN_IsTransmitRequested -* Description : Tests the request status of a transmitted message. -* Input : - msgobj: specifies the Message object number, from 0 to 31. -* Output : None -* Return : A non-zero value if the corresponding message is requested -* to transmit, else 0. -*******************************************************************************/ -u32 CAN_IsTransmitRequested(u32 msgobj) -{ - return (msgobj < 16 ? CAN->TXR1R & (1 << msgobj) : CAN->TXR2R & (1 << (msgobj-16))); -} - -/******************************************************************************* -* Function Name : CAN_IsInterruptPending -* Description : Tests the interrupt status of a message object. -* Input : - msgobj: specifies the Message object number, from 0 to 31. -* Output : None -* Return : A non-zero value if the corresponding message has an -* interrupt pending, else 0. -*******************************************************************************/ -u32 CAN_IsInterruptPending(u32 msgobj) -{ - return (msgobj < 16 ? CAN->IP1R & (1 << msgobj) : CAN->IP2R & (1 << (msgobj-16))); -} - -/******************************************************************************* -* Function Name : CAN_IsObjectValid -* Description : Tests the validity of a message object (ready to use). -* Input : - msgobj: specifies the Message object number, from 0 to 31. -* Output : None -* Return : A non-zero value if the corresponding message object is -* valid, else 0. -*******************************************************************************/ -u32 CAN_IsObjectValid(u32 msgobj) -{ - return (msgobj < 16 ? CAN->MV1R & (1 << msgobj) : CAN->MV2R & (1 << (msgobj-16))); -} -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_cfg.c b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_cfg.c deleted file mode 100644 index 593e8b84d..000000000 --- a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_cfg.c +++ /dev/null @@ -1,122 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_cfg.c -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file provides all the CFG software functions. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -#include "75x_cfg.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define CFG_SWBOOT_Mask 0xFFFFFFFC -#define CFG_FLASHBusy_Mask 0x00000080 - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/******************************************************************************* -* Function Name : CFG_BootSpaceConfig -* Description : Selects which memory space will be remapped at address 0x00. -* Input : - CFG_BootSpace: specifies the memory space to be remapped -* at address 0x00. -* This parameter can be one of the following values: -* - CFG_BootSpace_FLASH -* - CFG_BootSpace_SRAM -* - CFG_BootSpace_ExtSMI -* Output : None -* Return : None -*******************************************************************************/ -void CFG_BootSpaceConfig(u32 CFG_BootSpace) -{ - u32 Temp = 0; - - /* Clear SW_BOOT[1:0] bits */ - Temp = CFG->GLCONF & CFG_SWBOOT_Mask; - - /* Set SW_BOOT[1:0] bits according to CFG_BootSpace parameter value */ - Temp |= CFG_BootSpace; - - /* Store the new value */ - CFG->GLCONF = Temp; -} - -/******************************************************************************* -* Function Name : CFG_FLASHBurstConfig -* Description : Enables or disables the FLASH Burst mode. -* Input : - CCFG_FLASHBurst: specifies the new state of the FLASH Burst -* mode. -* This parameter can be one of the following values: -* - CFG_FLASHBurst_Disable -* - CFG_FLASHBurst_Enable -* Output : None -* Return : None -*******************************************************************************/ -void CFG_FLASHBurstConfig(u32 CFG_FLASHBurst) -{ - if(CFG_FLASHBurst == CFG_FLASHBurst_Enable) - { - CFG->GLCONF |= CFG_FLASHBurst_Enable; - } - else - { - CFG->GLCONF &= CFG_FLASHBurst_Disable; - } -} - -/******************************************************************************* -* Function Name : CFG_USBFilterConfig -* Description : Enables or disables the USB Filter. -* Input : - CFG_USBFilter: specifies the new state of the USB Filter. -* This parameter can be one of the following values: -* - CFG_USBFilter_Disable -* - CFG_USBFilter_Enable -* Output : None -* Return : None -*******************************************************************************/ -void CFG_USBFilterConfig(u32 CFG_USBFilter) -{ - if(CFG_USBFilter == CFG_USBFilter_Enable) - { - CFG->GLCONF |= CFG_USBFilter_Enable; - } - else - { - CFG->GLCONF &= CFG_USBFilter_Disable; - } -} - -/******************************************************************************* -* Function Name : CFG_GetFlagStatus -* Description : Checks whether the FLASH Busy flag is set or not. -* Input : None -* Output : None -* Return : The new state of FLASH Busy flag (SET or RESET). -*******************************************************************************/ -FlagStatus CFG_GetFlagStatus(void) -{ - if((CFG->GLCONF & CFG_FLASHBusy_Mask) != RESET) - { - return SET; - } - else - { - return RESET; - } -} - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_dma.c b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_dma.c deleted file mode 100644 index 7bc09466d..000000000 --- a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_dma.c +++ /dev/null @@ -1,596 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_dma.c -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file provides all the DMA software functions. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -#include "75x_dma.h" -#include "75x_mrcc.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* DMA enable */ -#define DMA_Enable 0x0001 -#define DMA_Disable 0xFFFE - -/* DMA Last Buffer Sweep */ -#define DMA_Last0_Enable_Mask 0x0001 -#define DMA_Last0_Disable_Mask 0xFFFE -#define DMA_Last1_Enable_Mask 0x0002 -#define DMA_Last1_Disable_Mask 0xFFFD -#define DMA_Last2_Enable_Mask 0x0004 -#define DMA_Last2_Disable_Mask 0xFFFB -#define DMA_Last3_Enable_Mask 0x0008 -#define DMA_Last3_Disable_Mask 0xFFF7 - -/* DMA Masks */ -#define DMA_Stream0_MASK_Mask 0xFFEE -#define DMA_Stream0_CLR_Mask 0x0011 -#define DMA_Stream0_LAST_Mask 0xFFFE - -#define DMA_Stream1_MASK_Mask 0xFFDD -#define DMA_Stream1_CLR_Mask 0x0022 -#define DMA_Stream1_LAST_Mask 0xFFFD - -#define DMA_Stream2_MASK_Mask 0xFFBB -#define DMA_Stream2_CLR_Mask 0x0044 -#define DMA_Stream2_LAST_Mask 0xFFFB - -#define DMA_Stream3_MASK_Mask 0xFF77 -#define DMA_Stream3_CLR_Mask 0x0088 -#define DMA_Stream3_LAST_Mask 0xFFF7 - -#define DMA_SRCSize_Mask 0xFFE7 -#define DMA_SRCBurst_Mask 0xFF9F -#define DMA_DSTSize_Mask 0xFE7F - -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/******************************************************************************* -* Function Name : DMA_DeInit -* Description : Deinitializes the DMA streamx registers to their default reset -* values. -* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA -* Stream. -* Output : None -* Return : None -*******************************************************************************/ -void DMA_DeInit(DMA_Stream_TypeDef* DMA_Streamx) -{ - /* Reset streamx source base address register */ - DMA_Streamx->SOURCEL = 0; - DMA_Streamx->SOURCEH = 0; - - /* Reset streamx destination base address register */ - DMA_Streamx->DESTL = 0; - DMA_Streamx->DESTH = 0; - - /* Reset streamx maximum count register */ - DMA_Streamx->MAX = 0; - /* Reset streamx control register */ - DMA_Streamx->CTRL = 0; - /* Reset streamx last used buffer location register */ - DMA_Streamx->LUBUFF = 0; - - switch(*(u32*)&DMA_Streamx) - { - case DMA_Stream0_BASE: - /* Reset interrupt mask, clear and flag bits for stream0 */ - DMA->MASK &= DMA_Stream0_MASK_Mask; - DMA->CLR |= DMA_Stream0_CLR_Mask; - DMA->LAST &= DMA_Stream0_LAST_Mask; - break; - - case DMA_Stream1_BASE: - /* Reset interrupt mask, clear and flag bits for stream1 */ - DMA->MASK &= DMA_Stream1_MASK_Mask; - DMA->CLR |= DMA_Stream1_CLR_Mask; - DMA->LAST &= DMA_Stream1_LAST_Mask; - break; - - case DMA_Stream2_BASE: - /* Reset interrupt mask, clear and flag bits for stream2 */ - DMA->MASK &= DMA_Stream2_MASK_Mask; - DMA->CLR |= DMA_Stream2_CLR_Mask; - DMA->LAST &= DMA_Stream2_LAST_Mask; - break; - - case DMA_Stream3_BASE: - /* Reset interrupt mask, clear and flag bits for stream3 */ - DMA->MASK &= DMA_Stream3_MASK_Mask; - DMA->CLR |= DMA_Stream3_CLR_Mask; - DMA->LAST &= DMA_Stream3_LAST_Mask; - break; - - default: - break; - } -} - -/******************************************************************************* -* Function Name : DMA_Init -* Description : Initializes the DMAx stream according to the specified -* parameters in the DMA_InitStruct. -* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA -* Stream. -* - DMA_InitStruct: pointer to a DMA_InitTypeDef structure that -* contains the configuration information for the specified -* DMA stream. -* Output : None -* Return : None -******************************************************************************/ -void DMA_Init(DMA_Stream_TypeDef* DMA_Streamx, DMA_InitTypeDef* DMA_InitStruct) -{ - /* set the buffer Size */ - DMA_Streamx->MAX = DMA_InitStruct->DMA_BufferSize ; - - /* Configure the incrementation of the current source Register */ - if(DMA_InitStruct->DMA_SRC == DMA_SRC_INCR) - { - /* Increment current source register */ - DMA_Streamx->CTRL |= DMA_SRC_INCR; - } - else - { - /* Current source register unchanged */ - DMA_Streamx->CTRL &= DMA_SRC_NOT_INCR; - } - - /* Configure the incrementation of the current destination Register */ - if(DMA_InitStruct->DMA_DST == DMA_DST_INCR) - { - /* Increment current source register */ - DMA_Streamx->CTRL |= DMA_DST_INCR; - } - else - { - /* Current source register unchanged */ - DMA_Streamx->CTRL &= DMA_DST_NOT_INCR; - } - - /* Clear source to DMA data width SOSIZE[1:0] bits */ - DMA_Streamx->CTRL &= DMA_SRCSize_Mask; - /* Set the source to DMA data width */ - DMA_Streamx->CTRL |= DMA_InitStruct->DMA_SRCSize; - - /* Clear the DMA peripheral burst size SOBURST[1:0] bits */ - DMA_Streamx->CTRL &= DMA_SRCBurst_Mask; - /* Set the DMA peripheral burst size */ - DMA_Streamx->CTRL |= DMA_InitStruct->DMA_SRCBurst; - - /* Clear destination to DMA dat width DESIZE[1:0] bits */ - DMA_Streamx->CTRL &= DMA_DSTSize_Mask; - /* Set the destination to DMA data width */ - DMA_Streamx->CTRL |= DMA_InitStruct->DMA_DSTSize; - - /* Configure the circular mode */ - if(DMA_InitStruct->DMA_Mode == DMA_Mode_Circular) - { - /* Set circular mode */ - DMA_Streamx->CTRL |= DMA_Mode_Circular; - } - else - { - /* Set normal mode */ - DMA_Streamx->CTRL &= DMA_Mode_Normal; - } - - /* Configure the direction transfer */ - if(DMA_InitStruct->DMA_DIR == DMA_DIR_PeriphDST) - { - /* Set peripheral as destination */ - DMA_Streamx->CTRL |= DMA_DIR_PeriphDST; - } - else - { - /* Set peripheral as source */ - DMA_Streamx->CTRL &= DMA_DIR_PeriphSRC; - } - - /* Configure the memory to memory transfer only for stream3 */ - if(DMA_Streamx == DMA_Stream3) - { - if(DMA_InitStruct->DMA_M2M == DMA_M2M_Enable) - { - /* Enable memory to memory transfer for stream3 */ - DMA_Streamx->CTRL |= DMA_M2M_Enable; - } - else - { - /* Disable memory to memory transfer for stream3 */ - DMA_Streamx->CTRL &= DMA_M2M_Disable; - } - } - - /* Configure the source base address */ - DMA_Streamx->SOURCEL = DMA_InitStruct->DMA_SRCBaseAddr; - DMA_Streamx->SOURCEH = DMA_InitStruct->DMA_SRCBaseAddr >> 16; - - /* Configure the destination base address */ - DMA_Streamx->DESTL = DMA_InitStruct->DMA_DSTBaseAddr; - DMA_Streamx->DESTH = DMA_InitStruct->DMA_DSTBaseAddr >> 16; -} - -/******************************************************************************* -* Function Name : DMA_StructInit -* Description : Fills each DMA_InitStruct member with its default value. -* Input : DMA_InitStruct : pointer to a DMA_InitTypeDef structure -* which will be initialized. -* Output : None -* Return : None -*******************************************************************************/ -void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) -{ - /* Initialize the DMA_BufferSize member */ - DMA_InitStruct->DMA_BufferSize = 0; - - /* initialize the DMA_SRCBaseAddr member */ - DMA_InitStruct->DMA_SRCBaseAddr = 0; - - /* Initialize the DMA_DSTBaseAddr member */ - DMA_InitStruct ->DMA_DSTBaseAddr = 0; - - /* Initialize the DMA_SRC member */ - DMA_InitStruct->DMA_SRC = DMA_SRC_NOT_INCR; - - /* Initialize the DMA_DST member */ - DMA_InitStruct->DMA_DST = DMA_DST_NOT_INCR; - - /* Initialize the DMA_SRCSize member */ - DMA_InitStruct->DMA_SRCSize = DMA_SRCSize_Byte; - - /* Initialize the DMA_SRCBurst member */ - DMA_InitStruct->DMA_SRCBurst = DMA_SRCBurst_1Data; - - /* Initialize the DMA_DSTSize member */ - DMA_InitStruct->DMA_DSTSize = DMA_DSTSize_Byte; - - /* Initialize the DMA_Mode member */ - DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; - - /* Initialize the DMA_M2M member */ - DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; - - /* Initialize the DMA_DIR member */ - DMA_InitStruct->DMA_DIR = DMA_DIR_PeriphSRC; -} - -/******************************************************************************* -* Function Name : DMA_Cmd -* Description : Enables or disables the specified DMA stream. -* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA -* Stream. -* - NewState: new state of the DMAx stream. This parameter can -* be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void DMA_Cmd(DMA_Stream_TypeDef* DMA_Streamx, FunctionalState NewState) -{ - if(NewState == ENABLE) - { - /* Enable the selected DMA streamx */ - DMA_Streamx->CTRL |= DMA_Enable; - } - else - { - /* Disable the selected DMA streamx */ - DMA_Streamx->CTRL &= DMA_Disable; - } -} - -/******************************************************************************* -* Function Name : DMA_ITConfig -* Description : Enables or disables the specified DMA interrupts. -* Input : - DMA_IT: specifies the DMA interrupts sources to be enabled -* or disabled. This parameter can be any combination of the -* following values: -* - DMA_IT_SI0: Stream0 transfer end interrupt mask -* - DMA_IT_SI1: Stream1 transfer end interrupt mask -* - DMA_IT_SI2: Stream2 transfer end interrupt mask -* - DMA_IT_SI3: Stream3 transfer end interrupt mask -* - DMA_IT_SE0: Stream0 transfer error interrupt mask -* - DMA_IT_SE1: Stream1 transfer error interrupt mask -* - DMA_IT_SE2: Stream2 transfer error interrupt mask -* - DMA_IT_SE3: Stream3 transfer error interrupt mask -* - DMA_IT_ALL: ALL DMA interrupts mask -* - NewState: new state of the specified DMA interrupts. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void DMA_ITConfig(u16 DMA_IT, FunctionalState NewState) -{ - if(NewState == ENABLE) - { - /* Enable the selected DMA interrupts */ - DMA->MASK |= DMA_IT; - } - else - { - /* Disable the selected DMA interrupts */ - DMA->MASK &= ~DMA_IT; - } -} - -/******************************************************************************* -* Function Name : DMA_GetCurrDSTAddr -* Description : Returns the current value of the destination address pointer -* related to the specified DMA stream. -* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA -* Stream. -* Output : None -* Return : The current value of the destination address pointer related -* to the specified DMA stream. -*******************************************************************************/ -u32 DMA_GetCurrDSTAddr(DMA_Stream_TypeDef* DMA_Streamx) -{ - u32 Tmp = 0; - - /* Get high current destination address */ - Tmp = (DMA_Streamx->DECURRH)<<16; - /* Get low current destination address */ - Tmp |= DMA_Streamx->DECURRL; - - /* Return the current destination address value for streamx */ - return Tmp; -} - -/******************************************************************************* -* Function Name : DMA_GetCurrSRCAddr -* Description : Returns the current value of the source address pointer -* related to the specified DMA stream. -* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA -* Stream. -* Output : None -* Return : The current value of the source address pointer related to -* the specified DMA stream. -*******************************************************************************/ -u32 DMA_GetCurrSRCAddr(DMA_Stream_TypeDef* DMA_Streamx) -{ - u32 Tmp = 0; - - /* Get high current source address */ - Tmp = (DMA_Streamx->SOCURRH)<<16; - /* Get slow current source address */ - Tmp |= DMA_Streamx->SOCURRL; - - /* Return the current source address value for streamx */ - return Tmp; -} - -/******************************************************************************* -* Function Name : DMA_GetTerminalCounter -* Description : Returns the number of data units remaining in the current -* DMA stream transfer. -* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA -* Stream. -* Output : None -* Return : The number of data units remaining in the current DMA stream -* transfer. -*******************************************************************************/ -u16 DMA_GetTerminalCounter(DMA_Stream_TypeDef* DMA_Streamx) -{ - /* Return the terminal counter value for streamx */ - return(DMA_Streamx->TCNT); -} - -/******************************************************************************* -* Function Name : DMA_LastBufferSweepConfig -* Description : Activates or disactivates the last buffer sweep mode for the -* DMA streamx configured in circular buffer mode. -* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA -* Stream. -* - NewState: new state of the Last buffer sweep DMA_Streamx. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void DMA_LastBufferSweepConfig(DMA_Stream_TypeDef* DMA_Streamx, FunctionalState NewState) -{ - switch(*(u32*)&DMA_Streamx) - { - case DMA_Stream0_BASE: - if(NewState == ENABLE) - { - /* Activates the last circular buffer sweep mode for stream0 */ - DMA->LAST |= DMA_Last0_Enable_Mask; - } - else - { - /* Disactivates the last circular buffer sweep mode for stream0 */ - DMA->LAST &= DMA_Last0_Disable_Mask; - } - break; - - case DMA_Stream1_BASE: - if(NewState == ENABLE) - { - /* Activates the last circular buffer sweep mode for stream1 */ - DMA->LAST |= DMA_Last1_Enable_Mask; - } - else - { - /* Disactivates the last circular buffer sweep mode for stream1 */ - DMA->LAST &= DMA_Last1_Disable_Mask; - } - break; - - case DMA_Stream2_BASE: - if(NewState == ENABLE) - { - /* Activates the last circular buffer sweep mode for stream2 */ - DMA->LAST |= DMA_Last2_Enable_Mask; - } - else - { - /* Disactivates the last circular buffer sweep mode for stream2 */ - DMA->LAST &= DMA_Last2_Disable_Mask; - } - break; - - case DMA_Stream3_BASE: - if(NewState == ENABLE) - { - /* Activates the last circular buffer sweep mode for stream3 */ - DMA->LAST |= DMA_Last3_Enable_Mask; - } - else - { - /* Disactivates the last circular buffer sweep mode for stream3 */ - DMA->LAST &= DMA_Last3_Disable_Mask; - } - break; - - default: - break; - } -} - -/******************************************************************************* -* Function Name : DMA_LastBufferAddrConfig -* Description : Configures the circular buffer position where the last data -* to be used by the specified DMA stream is located. -* Input : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA -* Stream. -* - DMA_LastBufferAddr: specifies the circular buffer position -* where the last data to be used by the specified DMA stream -* is located. -* This member must be a number between 0 and the stream BufferSize-1. -* Output : None -* Return : None -*******************************************************************************/ -void DMA_LastBufferAddrConfig(DMA_Stream_TypeDef* DMA_Streamx, u16 DMA_LastBufferAddr) -{ - /* Set the streamx last data circular buffer location */ - DMA_Streamx->LUBUFF = DMA_LastBufferAddr; -} - -/******************************************************************************* -* Function Name : DMA_GetFlagStatus -* Description : Checks whether the specified DMA flag is set or not. -* Input : - DMA_FLAG: specifies the flag to check. This parameter can -* be one of the following values: -* - DMA_FLAG_SI0: Stream0 transfer end flag. -* - DMA_FLAG_SI1: Stream1 transfer end flag. -* - DMA_FLAG_SI2: Stream2 transfer end flag. -* - DMA_FLAG_SI3: Stream3 transfer end flag. -* - DMA_FLAG_SE0: Stream0 transfer error flag. -* - DMA_FLAG_SE1: Stream1 transfer error flag. -* - DMA_FLAG_SE2: Stream2 transfer error flag. -* - DMA_FLAG_SE3: Stream3 transfer error flag. -* - DMA_FLAG_ACT0: Stream0 status. -* - DMA_FLAG_ACT1: Stream1 status. -* - DMA_FLAG_ACT2: Stream2 status. -* - DMA_FLAG_ACT3: Stream3 status. -* Output : None -* Return : The new state of DMA_FLAG (SET or RESET). -*******************************************************************************/ -FlagStatus DMA_GetFlagStatus(u16 DMA_FLAG) -{ - /* Check the status of the specified DMA flag */ - if((DMA->STATUS & DMA_FLAG) != RESET) - { - /* Return SET if DMA_FLAG is set */ - return SET; - } - else - { - /* Return RESET if DMA_FLAG is reset */ - return RESET; - } -} - -/******************************************************************************* -* Function Name : DMA_ClearFlag -* Description : Clears the DMA’s pending flags. -* Input : - DMA_FLAG: specifies the flag to clear. This parameter can -* be any combination of the following values: -* - DMA_FLAG_SI0: Stream0 transfer end flag. -* - DMA_FLAG_SI1: Stream1 transfer end flag. -* - DMA_FLAG_SI2: Stream2 transfer end flag. -* - DMA_FLAG_SI3: Stream3 transfer end flag. -* - DMA_FLAG_SE0: Stream0 transfer error flag. -* - DMA_FLAG_SE1: Stream1 transfer error flag. -* - DMA_FLAG_SE2: Stream2 transfer error flag. -* - DMA_FLAG_SE3: Stream3 transfer error flag. -* Output : None -* Return : None -*******************************************************************************/ -void DMA_ClearFlag(u16 DMA_FLAG) -{ - /* Clear the selected DMA flags */ - DMA->CLR = DMA_FLAG ; -} - -/******************************************************************************* -* Function Name : DMA_GetITStatus -* Description : Checks whether the specified DMA interrupt has occured or not. -* Input : - DMA_IT: specifies the DMA interrupt source to check. -* This parameter can be one of the following values: -* - DMA_IT_SI0: Stream0 transfer end interrupt -* - DMA_IT_SI1: Stream1 transfer end interrupt -* - DMA_IT_SI2: Stream2 transfer end interrupt -* - DMA_IT_SI3: Stream3 transfer end interrupt -* - DMA_IT_SE0: Stream0 transfer error interrupt -* - DMA_IT_SE1: Stream1 transfer error interrupt -* - DMA_IT_SE2: Stream2 transfer error interrupt -* - DMA_IT_SE3: Stream3 transfer error interrupt -* Output : None -* Return : The new state of DMA_IT (SET or RESET). -*******************************************************************************/ -ITStatus DMA_GetITStatus(u16 DMA_IT) -{ - /* Check the status of the specified DMA interrupt */ - if((DMA->STATUS & DMA_IT) != RESET) - { - /* Return SET if the DMA interrupt flag is set */ - return SET; - } - else - { - /* Return RESET if the DMA interrupt flag is reset */ - return RESET; - } -} - -/******************************************************************************* -* Function Name : DMA_ClearITPendingBit -* Description : Clears the DMA’s interrupt pending bits. -* Input : - DMA_IT: specifies the interrupt pending bit to clear. -* This parameter can be any combination of the following values: -* - DMA_IT_SI0: Stream0 transfer end interrupt. -* - DMA_IT_SI1: Stream1 transfer end interrupt. -* - DMA_IT_SI2: Stream2 transfer end interrupt. -* - DMA_IT_SI3: Stream3 transfer end interrupt. -* - DMA_IT_SE0: Stream0 transfer error interrupt. -* - DMA_IT_SE1: Stream1 transfer error interrupt. -* - DMA_IT_SE2: Stream2 transfer error interrupt. -* - DMA_IT_SE3: Stream3 transfer error interrupt. -* - DMA_IT_ALL: All DMA interrupts. -* Output : None -* Return : None -*******************************************************************************/ -void DMA_ClearITPendingBit(u16 DMA_IT) -{ - /* Clear the selected DMA interrupts pending bits */ - DMA->CLR = DMA_IT ; -} - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_eic.c b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_eic.c deleted file mode 100644 index ca9ead80f..000000000 --- a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_eic.c +++ /dev/null @@ -1,258 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_eic.c -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file provides all the EIC software functions. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -#include "75x_eic.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define EIC_IRQEnable_Mask 0x00000001 -#define EIC_IRQDisable_Mask 0xFFFFFFFE - -#define EIC_FIQEnable_Mask 0x00000002 -#define EIC_FIQDisable_Mask 0xFFFFFFFD - -#define EIC_SIPL_Mask 0x0000000F -#define EIC_SIPL_Reset_Mask 0xFFFFFFF0 - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/******************************************************************************* -* Function Name : EIC_DeInit -* Description : Deinitializes the EIC peripheral registers to their default -* reset values. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void EIC_DeInit(void) -{ - EIC->ICR = 0x00; - EIC->CIPR = 0x00; - EIC->FIR = 0x0C; - EIC->IER = 0x00; - EIC->IPR = 0xFFFFFFFF; -} - -/******************************************************************************* -* Function Name : EIC_IRQInit -* Description : Configures the IRQ channels according to the specified -* parameters in the EIC_IRQInitStruct. -* Input : EIC_IRQInitStruct: pointer to a EIC_IRQInitTypeDef structure. -* Output : None -* Return : None -*******************************************************************************/ -void EIC_IRQInit(EIC_IRQInitTypeDef* EIC_IRQInitStruct) -{ - u32 Tmp = 0; - - if(EIC_IRQInitStruct->EIC_IRQChannelCmd == ENABLE) - { - /* Enable the selected IRQ channel */ - EIC->IER |= 1 << EIC_IRQInitStruct->EIC_IRQChannel; - - /* Configure the selected IRQ channel priority ***************************/ - /* Clear SIPL[3:0] bits */ - EIC->SIRn[EIC_IRQInitStruct->EIC_IRQChannel] &= EIC_SIPL_Reset_Mask; - - /* Configure SIPL[3:0] bits according to EIC_IRQChannelPriority parameter */ - Tmp = EIC_IRQInitStruct->EIC_IRQChannelPriority & EIC_SIPL_Mask; - EIC->SIRn[EIC_IRQInitStruct->EIC_IRQChannel] |= Tmp; - } - else - { - /* Disable the select IRQ channel */ - EIC->IER &=~ (1 << EIC_IRQInitStruct->EIC_IRQChannel); - } -} - -/******************************************************************************* -* Function Name : EIC_FIQInit -* Description : Configures the FIQ channels according to the specified -* parameters in the EIC_FIQInitStruct. -* Input : EIC_FIQInitStruct: pointer to a EIC_FIQInitTypeDef structure. -* Output : None -* Return : None -*******************************************************************************/ -void EIC_FIQInit(EIC_FIQInitTypeDef* EIC_FIQInitStruct) -{ - if(EIC_FIQInitStruct->EIC_FIQChannelCmd == ENABLE) - { - /* Enable the selected FIQ channel */ - EIC->FIER |= EIC_FIQInitStruct->EIC_FIQChannel ; - } - else - { - /* Disable the selected FIQ channel */ - EIC->FIER &= ~EIC_FIQInitStruct->EIC_FIQChannel; - } -} - -/******************************************************************************* -* Function Name : EIC_IRQStructInit -* Description : Fills each EIC_IRQInitStruct member with its default value. -* Input : EIC_IRQInitStruct: pointer to a EIC_IRQInitTypeDef structure -* which will be initialized. -* Output : None -* Return : None -*******************************************************************************/ -void EIC_IRQStructInit(EIC_IRQInitTypeDef* EIC_IRQInitStruct) -{ - EIC_IRQInitStruct->EIC_IRQChannel = 0x1F; - EIC_IRQInitStruct->EIC_IRQChannelPriority = 0; - EIC_IRQInitStruct->EIC_IRQChannelCmd = DISABLE; -} - -/******************************************************************************* -* Function Name : EIC_FIQStructInit -* Description : Fills each EIC_FIQInitStruct member with its default value. -* Input : EIC_FIQInitStruct: pointer to a EIC_FIQInitTypeDef structure -* which will be initialized. -* Output : None -* Return : None -*******************************************************************************/ -void EIC_FIQStructInit(EIC_FIQInitTypeDef* EIC_FIQInitStruct) -{ - EIC_FIQInitStruct->EIC_FIQChannel = 0x03; - EIC_FIQInitStruct->EIC_FIQChannelCmd = DISABLE; -} - -/******************************************************************************* -* Function Name : EIC_IRQCmd -* Description : Enables or disables EIC IRQ output request to CPU. -* Input : NewState: new state of the EIC IRQ output request to CPU. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void EIC_IRQCmd(FunctionalState NewState) -{ - if(NewState == ENABLE) - { - /* Enable EIC IRQ output request to CPU */ - EIC->ICR |= EIC_IRQEnable_Mask; - } - else - { - /* Disable EIC IRQ output request to CPU */ - EIC->ICR &= EIC_IRQDisable_Mask; - } -} - -/******************************************************************************* -* Function Name : EIC_FIQCmd -* Description : Enables or disables EIC FIQ output request to CPU. -* Input : NewState: new state of the EIC FIQ output request to CPU. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void EIC_FIQCmd(FunctionalState NewState) -{ - if(NewState == ENABLE) - { - /* Enable EIC FIQ output request to CPU */ - EIC->ICR |= EIC_FIQEnable_Mask; - } - else - { - /* Disable EIC FIQ output request to CPU */ - EIC->ICR &= EIC_FIQDisable_Mask; - } -} - -/******************************************************************************* -* Function Name : EIC_GetCurrentIRQChannel -* Description : Returns the current served IRQ channel identifier. -* Input : None -* Output : None -* Return : The current served IRQ channel. -*******************************************************************************/ -u8 EIC_GetCurrentIRQChannel(void) -{ - /* Read and return the CIC[4:0] bits of CICR register */ - return ((u8) (EIC->CICR)); -} - -/******************************************************************************* -* Function Name : EIC_GetCurrentIRQChannelPriority -* Description : Returns the priority level of the current served IRQ channel. -* Input : None -* Output : None -* Return : The priority level of the current served IRQ channel. -*******************************************************************************/ -u8 EIC_GetCurrentIRQChannelPriority(void) -{ - /* Read and return the CIP[3:0] bits of CIPR register */ - return ((u8) (EIC->CIPR)); -} - -/******************************************************************************* -* Function Name : EIC_CurrentIRQPriorityConfig -* Description : Changes the priority of the current served IRQ channel. -* The new priority value must be higher, or equal, than the -* priority value associated to the interrupt channel currently -* serviced. -* Input : NewPriority: new priority value of the IRQ interrupt routine -* currently serviced. -* Output : None -* Return : None -*******************************************************************************/ -void EIC_CurrentIRQPriorityConfig(u8 NewPriority) -{ - /* Disable EIC IRQ output request to CPU */ - EIC->ICR &= EIC_IRQDisable_Mask; - - /* Change the current priority */ - EIC->CIPR = NewPriority; - - /* Enable EIC IRQ output request to CPU */ - EIC->ICR |= EIC_IRQEnable_Mask; -} - -/******************************************************************************* -* Function Name : EIC_GetCurrentFIQChannel -* Description : Returns the current served FIQ channel identifier. -* Input : None -* Output : None -* Return : The current served FIQ channel. -*******************************************************************************/ -u8 EIC_GetCurrentFIQChannel(void) -{ - /* Read and return the FIP[1:0] bits of FIPR register */ - return ((u8) (EIC->FIPR)); -} - -/******************************************************************************* -* Function Name : EIC_ClearFIQPendingBit -* Description : Clears the pending bit of the selected FIQ Channel. -* Input : EIC_FIQChannel: specifies the FIQ channel to clear its -* pending bit. -* Output : None -* Return : None -*******************************************************************************/ -void EIC_ClearFIQPendingBit(u8 EIC_FIQChannel) -{ - /* Clear the correspondent FIQ pending bit */ - EIC->FIPR = EIC_FIQChannel ; -} - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_extit.c b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_extit.c deleted file mode 100644 index 997cb24f2..000000000 --- a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_extit.c +++ /dev/null @@ -1,179 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_extit.c -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file provides all the EXTIT software functions. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -#include "75x_extit.h" -#include "75x_mrcc.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/******************************************************************************* -* Function Name : EXTIT_DeInit -* Description : Deinitializes the EXTIT peripheral registers to their default -* reset values. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void EXTIT_DeInit(void) -{ - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_EXTIT,ENABLE); - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_EXTIT,DISABLE); -} - -/******************************************************************************* -* Function Name : EXTIT_Init -* Description : Initializes the EXTIT peripheral according to the specified -* parameters in the EXTIT_InitStruct . -* Input : - EXTIT_InitStruct: pointer to a EXTIT_InitTypeDef structure -* that contains the configuration information for the EXTIT -* peripheral. -* Output : None -* Return : None -*******************************************************************************/ -void EXTIT_Init(EXTIT_InitTypeDef* EXTIT_InitStruct) -{ - if(EXTIT_InitStruct->EXTIT_ITLineCmd == ENABLE) - { - /* Enable the selected external interrupts */ - EXTIT->MR |= EXTIT_InitStruct->EXTIT_ITLine; - - /* Select the trigger for the selected external interrupts */ - if(EXTIT_InitStruct->EXTIT_ITTrigger == EXTIT_ITTrigger_Falling) - { - /* Falling edge */ - EXTIT->TSR &= ~EXTIT_InitStruct->EXTIT_ITLine; - } - else if (EXTIT_InitStruct->EXTIT_ITTrigger == EXTIT_ITTrigger_Rising) - { - /* Rising edge */ - EXTIT->TSR |= EXTIT_InitStruct->EXTIT_ITLine; - } - } - else if(EXTIT_InitStruct->EXTIT_ITLineCmd == DISABLE) - { - /* Disable the selected external interrupts */ - EXTIT->MR &= ~EXTIT_InitStruct->EXTIT_ITLine; - } -} - -/******************************************************************************* -* Function Name : EXTIT_StructInit -* Description : Fills each EXTIT_InitStruct member with its reset value. -* Input : - EXTIT_InitStruct: pointer to a EXTIT_InitTypeDef structure -* which will be initialized. -* Output : None -* Return : None -*******************************************************************************/ -void EXTIT_StructInit(EXTIT_InitTypeDef* EXTIT_InitStruct) -{ - EXTIT_InitStruct->EXTIT_ITLine = EXTIT_ITLineNone; - EXTIT_InitStruct->EXTIT_ITTrigger = EXTIT_ITTrigger_Falling; - EXTIT_InitStruct->EXTIT_ITLineCmd = DISABLE; -} - -/******************************************************************************* -* Function Name : EXTIT_GenerateSWInterrupt -* Description : Generates a Software interrupt. -* Input : - EXTIT_ITLine: specifies the EXTIT lines to be enabled or -* disabled. This parameter can be: -* - EXTIT_ITLinex: External interrupt line x where x(0..15) -* Output : None -* Return : None -*******************************************************************************/ -void EXTIT_GenerateSWInterrupt(u16 EXTIT_ITLine) -{ - EXTIT->SWIR |= EXTIT_ITLine; -} - -/******************************************************************************* -* Function Name : EXTIT_GetFlagStatus -* Description : Checks whether the specified EXTIT line flag is set or not. -* Input : - EXTIT_ITLine: specifies the EXTIT lines flag to check. -* This parameter can be: -* - EXTIT_ITLinex: External interrupt line x where x(0..15) -* Output : None -* Return : The new state of EXTIT_ITLine (SET or RESET). -*******************************************************************************/ -FlagStatus EXTIT_GetFlagStatus(u16 EXTIT_ITLine) -{ - if((EXTIT->PR & EXTIT_ITLine) != RESET) - { - return SET; - } - else - { - return RESET; - } -} - -/******************************************************************************* -* Function Name : EXTIT_ClearFlag -* Description : Clears the EXTIT’s line pending flags. -* Input : - EXTIT_ITLine: specifies the EXTIT lines flags to clear. -* This parameter can be: -* - EXTIT_ITLinex: External interrupt line x where x(0..15) -* Output : None -* Return : None -*******************************************************************************/ -void EXTIT_ClearFlag(u16 EXTIT_ITLine) -{ - EXTIT->PR = EXTIT_ITLine; -} - -/******************************************************************************* -* Function Name : EXTIT_GetITStatus -* Description : Checks whether the specified EXTIT line is asserted or not. -* Input : - EXTIT_ITLine: specifies the EXTIT lines to check. -* This parameter can be: -* - EXTIT_ITLinex: External interrupt line x where x(0..15) -* Output : None -* Return : The new state of EXTIT_ITLine (SET or RESET). -*******************************************************************************/ -ITStatus EXTIT_GetITStatus(u16 EXTIT_ITLine) -{ - if(((EXTIT->PR & EXTIT_ITLine) != RESET)&& ((EXTIT->MR & EXTIT_ITLine) != RESET)) - { - return SET; - } - else - { - return RESET; - } -} - -/******************************************************************************* -* Function Name : EXTIT_ClearITPendingBit -* Description : Clears the EXTIT’s line pending bits. -* Input : - EXTIT_ITLine: specifies the EXTIT lines to clear. -* This parameter can be: -* - EXTIT_ITLinex: External interrupt line x where x(0..15) -* Output : None -* Return : None -*******************************************************************************/ -void EXTIT_ClearITPendingBit(u16 EXTIT_ITLine) -{ - EXTIT->PR = EXTIT_ITLine; -} - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_gpio.c b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_gpio.c deleted file mode 100644 index dcc7d7920..000000000 --- a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_gpio.c +++ /dev/null @@ -1,320 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_gpio.c -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file provides all the GPIO software functions. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -#include "75x_gpio.h" -#include "75x_mrcc.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define GPIO_Remap_Mask 0x1F /* GPIO remapping mask */ -#define GPIO_Pin_Mask 0x000FFFFF /* GPIO1 and GPIO2 all pins mask */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/******************************************************************************* -* Function Name : GPIO_DeInit -* Description : Deinitializes the GPIOx peripheral registers to their default -* reset values. -* The I/O remapping register 0 and 1 are not reset by this function. -* Input : GPIOx: where x can be 0,1 or 2 to select the GPIO peripheral. -* Output : None -* Return : None -*******************************************************************************/ -void GPIO_DeInit(GPIO_TypeDef* GPIOx) -{ - /* Reset the GPIOx registers values */ - GPIOx->PC0 = 0xFFFFFFFF; - GPIOx->PC1 = 0x0; - GPIOx->PC2 = 0x0; - GPIOx->PM = 0x0; -} - -/******************************************************************************* -* Function Name : GPIO_Init -* Description : Initializes the GPIOx peripheral according to the specified -* parameters in the GPIO_InitStruct. This function will not -* change the configuration for a pin if the corresponding mask -* bit is set, except pins configured as input pull-up or pull-down. -* These pins are automatically masked after each configuration. -* Input :- GPIOx: where x can be (0..2) to select the GPIO peripheral. -* - GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that -* contains the configuration information for the specified GPIO -* peripheral. -* Output : None -* Return : None -*******************************************************************************/ -void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) -{ - /* GPIOx Mode and Pins Set */ - if((GPIOx != GPIO0) && (GPIO_InitStruct->GPIO_Pin == GPIO_Pin_All)) - { - GPIO_InitStruct->GPIO_Pin = GPIO_Pin_Mask; - } - - switch(GPIO_InitStruct->GPIO_Mode) - { - case GPIO_Mode_AIN: - GPIOx->PC0 &= ~GPIO_InitStruct->GPIO_Pin; - GPIOx->PC1 &= ~GPIO_InitStruct->GPIO_Pin; - GPIOx->PC2 &= ~GPIO_InitStruct->GPIO_Pin; - break; - - case GPIO_Mode_IN_FLOATING: - GPIOx->PC0 |= GPIO_InitStruct->GPIO_Pin; - GPIOx->PC1 &= ~GPIO_InitStruct->GPIO_Pin; - GPIOx->PC2 &= ~GPIO_InitStruct->GPIO_Pin; - break; - - case GPIO_Mode_IPD: - GPIOx->PM &= ~GPIO_InitStruct->GPIO_Pin; - GPIOx->PC0 |= GPIO_InitStruct->GPIO_Pin; - GPIOx->PC1 |= GPIO_InitStruct->GPIO_Pin; - GPIOx->PC2 &= ~GPIO_InitStruct->GPIO_Pin; - GPIOx->PD &= ~GPIO_InitStruct->GPIO_Pin; - GPIOx->PM |= GPIO_InitStruct->GPIO_Pin; - break; - - case GPIO_Mode_IPU: - GPIOx->PM &= ~GPIO_InitStruct->GPIO_Pin; - GPIOx->PC0 |= GPIO_InitStruct->GPIO_Pin; - GPIOx->PC1 |= GPIO_InitStruct->GPIO_Pin; - GPIOx->PC2 &= ~GPIO_InitStruct->GPIO_Pin; - GPIOx->PD |= GPIO_InitStruct->GPIO_Pin; - GPIOx->PM |= GPIO_InitStruct->GPIO_Pin; - break; - - case GPIO_Mode_Out_OD: - GPIOx->PC0 &= ~GPIO_InitStruct->GPIO_Pin; - GPIOx->PC1 &= ~GPIO_InitStruct->GPIO_Pin; - GPIOx->PC2 |= GPIO_InitStruct->GPIO_Pin; - break; - - case GPIO_Mode_Out_PP: - GPIOx->PC0 |= GPIO_InitStruct->GPIO_Pin; - GPIOx->PC1 &= ~GPIO_InitStruct->GPIO_Pin; - GPIOx->PC2 |= GPIO_InitStruct->GPIO_Pin; - break; - - case GPIO_Mode_AF_OD: - GPIOx->PD |= GPIO_InitStruct->GPIO_Pin; - GPIOx->PC1 |= GPIO_InitStruct->GPIO_Pin; - GPIOx->PC0 &= ~GPIO_InitStruct->GPIO_Pin; - GPIOx->PC2 |= GPIO_InitStruct->GPIO_Pin; - break; - - case GPIO_Mode_AF_PP: - GPIOx->PC0 |= GPIO_InitStruct->GPIO_Pin; - GPIOx->PC1 |= GPIO_InitStruct->GPIO_Pin; - GPIOx->PC2 |= GPIO_InitStruct->GPIO_Pin; - break; - - default : - GPIOx->PC0 |= GPIO_InitStruct->GPIO_Pin; - GPIOx->PC1 &= ~GPIO_InitStruct->GPIO_Pin; - GPIOx->PC2 &= ~GPIO_InitStruct->GPIO_Pin; - break; - } -} - -/******************************************************************************* -* Function Name : GPIO_StructInit -* Description : Fills each GPIO_InitStruct member with its default value. -* Input : GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure -* which will be initialized. -* Output : None -* Return : None -*******************************************************************************/ -void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) -{ - /* Reset GPIO init structure parameters values */ - GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; -} - -/******************************************************************************* -* Function Name : GPIO_Read -* Description : Reads the specified GPIO data port. -* Input : GPIOx: where x can be 0,1 or 2 to select the GPIO peripheral. -* Output : None -* Return : GPIO data port word value. -*******************************************************************************/ -u32 GPIO_Read(GPIO_TypeDef* GPIOx) -{ - return GPIOx->PD; -} - -/******************************************************************************* -* Function Name : GPIO_ReadBit -* Description : Reads the specified data port bit. -* Input : - GPIOx: where x can be (0..2) to select the GPIO peripheral. -* : - GPIO_Pin: specifies the port bit to read. -* This parameter can be GPIO_Pin_x where x can be (0..31) for -* GPIO0 and x(0..19) for GPIO1 and GPIO2. -* Output : None -* Return : The port pin value -*******************************************************************************/ -u8 GPIO_ReadBit(GPIO_TypeDef* GPIOx, u32 GPIO_Pin) -{ - if ((GPIOx->PD & GPIO_Pin) != Bit_RESET) - { - return Bit_SET; - } - else - { - return Bit_RESET; - } -} - -/******************************************************************************* -* Function Name : GPIO_Write -* Description : Writes data to the specified GPIO data port. -* Input :- GPIOx: where x can be 0,1 or 2 to select the GPIO peripheral. -* - PortVal: specifies the value to be written to the data port -* register. -* Output : None -* Return : None -*******************************************************************************/ -void GPIO_Write(GPIO_TypeDef* GPIOx, u32 PortVal) -{ - GPIOx->PD = PortVal; -} - -/******************************************************************************* -* Function Name : GPIO_WriteBit -* Description : Sets or clears the selected data port bit. -* Input : - GPIOx: where x can be (0..2) to select the GPIO peripheral. -* - GPIO_Pin: specifies the port bit to be written. -* This parameter can be GPIO_Pin_x where x can be (0..31) for -* GPIO0 and x(0..19) for GPIO1 and GPIO2. -* - BitVal: specifies the value to be written to the selected bit. -* This parameter must be one of the BitAction enum values: -* - Bit_RESET: to clear the port pin -* - Bit_SET: to set the port pin -* Output : None -* Return : None -*******************************************************************************/ -void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u32 GPIO_Pin, BitAction BitVal) -{ - if(BitVal != Bit_RESET) - { - GPIOx->PD |= GPIO_Pin; - } - else - { - GPIOx->PD &= ~GPIO_Pin; - } -} - -/******************************************************************************* -* Function Name : GPIO_PinMaskConfig -* Description : Enables or disables write protection to the selected bits in -* the I/O port registers (PxC2, PxC1, PxC0 and PxD). -* Input :- GPIOx: where x can be 0,1 or 2 to select the GPIO peripheral. -* - GPIO_Pin: specifies the port bit to be protected. -* This parameter can be GPIO_Pin_x where x can be (0..31) for -* GPIO0 and x(0..19) for GPIO1 and GPIO2. -* - NewState: new state of the port pin. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void GPIO_PinMaskConfig(GPIO_TypeDef* GPIOx, u32 GPIO_Pin, FunctionalState NewState) -{ - if(NewState == ENABLE) - { - GPIOx->PM |= GPIO_Pin; - } - else - { - GPIOx->PM &= ~GPIO_Pin; - } -} - -/******************************************************************************* -* Function Name : GPIO_GetPortMask -* Description : Gets the GPIOx port mask value. -* Input : GPIOx: where x can be 0,1 or 2 to select the GPIO peripheral. -* Output : None -* Return : GPIO port mask value. -*******************************************************************************/ -u32 GPIO_GetPortMask(GPIO_TypeDef* GPIOx) -{ - return GPIOx->PM; -} - -/******************************************************************************* -* Function Name : GPIO_PinRemapConfig -* Description : Changes the mapping of the specified pin. -* Input :- GPIO_Remap: selects the pin to remap. -* This parameter can be one of the following values: -* - GPIO_Remap_SMI_CS3_EN: Enable SMI CS3 -* - GPIO_Remap_SMI_CS2_EN: Enable SMI CS2 -* - GPIO_Remap_SMI_CS1_EN: Enable SMI CS1 -* - GPIO_Remap_SMI_EN: Enable SMI Alternate Functions: -* SMI_CS0, SMI_CK, SMI_DIN and SMI_DOUT -* - GPIO_Remap_DBGOFF: JTAG Disable -* - GPIO_Remap_UART1: UART1 Alternate Function mapping -* - GPIO_Remap_UART2: UART2 Alternate Function mapping -* - GPIO_Remap_SSP1: SSP1 Alternate Function mapping -* - GPIO_Remap_TIM2: TIM2 Alternate Function mapping -* - GPIO_Remap_TIM0: TIM0 Alternate Function mapping -* - NewState: new state of the port pin. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void GPIO_PinRemapConfig(u16 GPIO_Remap, FunctionalState NewState) -{ - u32 GPIOReg = 0; - u32 PinPos = 0; - - /* Get the GPIO register index */ - GPIOReg = GPIO_Remap >> 5; - - /* Get the pin position */ - PinPos = GPIO_Remap & GPIO_Remap_Mask; - - if(GPIOReg == 1) /* The pin to remap is in REMAP0R register */ - { - if(NewState == ENABLE) - { - GPIOREMAP->REMAP0R |= (1 << PinPos); - } - else - { - GPIOREMAP->REMAP0R &= ~(1 << PinPos); - } - } - else if(GPIOReg == 2) /* The pin to remap is in REMAP1R register */ - { - if(NewState == ENABLE) - { - GPIOREMAP->REMAP1R |= (1 << PinPos); - } - else - { - GPIOREMAP->REMAP1R &= ~(1 << PinPos); - } - } -} - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_i2c.c b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_i2c.c deleted file mode 100644 index e5e5d001c..000000000 --- a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_i2c.c +++ /dev/null @@ -1,568 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_i2c.c -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file provides all the I2C software functions. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -#include "75x_i2c.h" -#include "75x_mrcc.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* I2C IT enable */ -#define I2C_IT_Enable 0x01 -#define I2C_IT_Disable 0xFE - -/* I2C Peripheral Enable/Disable */ -#define I2C_PE_Set 0x20 -#define I2C_PE_Reset 0xDF - -/* I2C START Enable/Disable */ -#define I2C_Start_Enable 0x08 -#define I2C_Start_Disable 0xF7 - -/* I2C STOP Enable/Disable */ -#define I2C_Stop_Enable 0x02 -#define I2C_Stop_Disable 0xFD - -/* Address direction bit */ -#define I2C_ADD0_Set 0x01 -#define I2C_ADD0_Reset 0xFE - -/* I2C Masks */ -#define I2C_Frequency_Mask 0x1F -#define I2C_AddressHigh_Mask 0xF9 -#define I2C_OwnAddress_Mask 0x0300 -#define I2C_StandardMode_Mask 0x7f -#define I2C_FastMode_Mask 0x80 -#define I2C_Event_Mask 0x3FFF - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/******************************************************************************* -* Function Name : I2C_DeInit -* Description : Deinitializes the I2C peripheral registers to their default -* reset values. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void I2C_DeInit(void) -{ - /* Reset the I2C registers values*/ - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_I2C,ENABLE); - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_I2C,DISABLE); -} - -/******************************************************************************* -* Function Name : I2C_Init -* Description : Initializes the I2C peripheral according to the specified -* parameters in the I2C_Initstruct. -* Input : - I2C_InitStruct: pointer to a I2C_InitTypeDef structure that -* contains the configuration information for the specified I2C -* peripheral. -* Output : None -* Return : None -*******************************************************************************/ -void I2C_Init(I2C_InitTypeDef* I2C_InitStruct) -{ - u8 ITEState = 0; - u16 Result = 0x0F; - u32 APBClock = 8000000; - MRCC_ClocksTypeDef MRCC_ClocksStatus; - - /* Get APBClock frequency value */ - MRCC_GetClocksStatus(&MRCC_ClocksStatus); - APBClock = MRCC_ClocksStatus.PCLK_Frequency; - /* Save ITE bit state */ - ITEState = I2C->CR & 0xFE; - /* Disable I2C peripheral to set FR[2:0] bits */ - I2C_Cmd(DISABLE); - /* Clear frequency FR[2:0] bits */ - I2C->OAR2 &= I2C_Frequency_Mask; - - /* Set frequency bits depending on APBClock value */ - if (APBClock < 10000000) - I2C->OAR2 &= 0x1F; - else if (APBClock < 16670000) - I2C->OAR2 |= 0x20; - else if (APBClock < 26670000) - I2C->OAR2 |= 0x40; - else if (APBClock < 40000000) - I2C->OAR2 |= 0x60; - else if (APBClock < 53330000) - I2C->OAR2 |= 0x80; - else if (APBClock < 66000000) - I2C->OAR2 |= 0xA0; - else if (APBClock < 80000000) - I2C->OAR2 |= 0xC0; - else if (APBClock < 100000000) - I2C->OAR2 |= 0xE0; - I2C_Cmd(ENABLE); - - /* Restore the ITE bit state */ - I2C->CR |= ITEState; - - /* Configure general call */ - if (I2C_InitStruct->I2C_GeneralCall == I2C_GeneralCall_Enable) - { - /* Enable general call */ - I2C->CR |= I2C_GeneralCall_Enable; - } - else - { - /* Disable general call */ - I2C->CR &= I2C_GeneralCall_Disable; - } - - /* Configure acknowledgement */ - if (I2C_InitStruct->I2C_Ack == I2C_Ack_Enable) - { - /* Enable acknowledgement */ - I2C->CR |= I2C_Ack_Enable; - } - else - { - /* Disable acknowledgement */ - I2C->CR &= I2C_Ack_Disable; - } - - /* Configure LSB own address */ - I2C->OAR1 = I2C_InitStruct->I2C_OwnAddress; - /* Clear MSB own address ADD[9:8] bits */ - I2C->OAR2 &= I2C_AddressHigh_Mask; - /* Set MSB own address value */ - I2C->OAR2 |= (I2C_InitStruct->I2C_OwnAddress & I2C_OwnAddress_Mask)>>7; - - /* Configure speed in standard mode */ - if (I2C_InitStruct->I2C_CLKSpeed <= 100000) - { - /* Standard mode speed calculate */ - Result = ((APBClock/I2C_InitStruct->I2C_CLKSpeed)-7)/2; - /* Set speed value and clear FM/SM bit for standard mode in LSB clock divider */ - I2C->CCR = Result & I2C_StandardMode_Mask; - } - /* Configure speed in fast mode */ - else if (I2C_InitStruct->I2C_CLKSpeed <= 400000) - { - /* Fast mode speed calculate */ - Result = ((APBClock/I2C_InitStruct->I2C_CLKSpeed)-9)/3; - /* Set speed value and set FM/SM bit for fast mode in LSB clock divider */ - I2C->CCR = Result | I2C_FastMode_Mask; - } - /* Set speed in MSB clock divider */ - I2C->ECCR = Result >>7; -} - -/******************************************************************************* -* Function Name : I2C_StructInit -* Description : Fills each I2C_InitStruct member with its default value. -* Input : - I2C_InitStruct: pointer to an I2C_InitTypeDef structure - which will be initialized. -* Output : None -* Return : None. -*******************************************************************************/ -void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) -{ - /* Initialize the I2C_CLKSpeed member */ - I2C_InitStruct->I2C_CLKSpeed = 5000; - - /* Initialize the I2C_OwnAddress member */ - I2C_InitStruct->I2C_OwnAddress = 0x0; - - /* Initialize the I2C_GeneralCall member */ - I2C_InitStruct->I2C_GeneralCall = I2C_GeneralCall_Disable; - - /* Initialize the I2C_Ack member */ - I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; -} - -/******************************************************************************* -* Function Name : I2C_Cmd -* Description : Enables or disables the I2C peripheral. -* Input : - NewState: new state of the I2C peripheral. This parameter -* can be: ENABLE or DISABLE. -* Output : None -* Return : None. -*******************************************************************************/ -void I2C_Cmd(FunctionalState NewState) -{ - if (NewState == ENABLE) - { - /* Enable the I2C peripheral by setting twice the PE bit on the CR register */ - I2C->CR |= I2C_PE_Set; - I2C->CR |= I2C_PE_Set; - } - else - { - /* Disable the I2C peripheral */ - I2C->CR &= I2C_PE_Reset; - } -} - -/******************************************************************************* -* Function Name : I2C_GenerateSTART -* Description : Generates I2C communication START condition. -* Input : - NewState: new state of the I2C START condition generation. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None. -*******************************************************************************/ -void I2C_GenerateSTART(FunctionalState NewState) -{ - if (NewState == ENABLE) - { - /* Generate a START condition */ - I2C->CR |= I2C_Start_Enable; - } - else - { - /* Disable the START condition generation */ - I2C->CR &= I2C_Start_Disable; - } -} - -/******************************************************************************* -* Function Name : I2C_GenerateSTOP -* Description : Generates I2C communication STOP condition. -* Input : - NewState: new state of the I2C STOP condition generation. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None. -*******************************************************************************/ -void I2C_GenerateSTOP(FunctionalState NewState) -{ - if (NewState == ENABLE) - { - /* Generate a SIOP condition */ - I2C->CR |= I2C_Stop_Enable; - } - else - { - /* Disable the STOP condition generation */ - I2C->CR &= I2C_Stop_Disable; - } -} - -/******************************************************************************* -* Function Name : I2C_AcknowledgeConfig -* Description : Enables or disables I2C acknowledge feature. -* Input : - NewState: new state of the I2C Acknowledgement. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None. -*******************************************************************************/ -void I2C_AcknowledgeConfig(FunctionalState NewState) -{ - if (NewState == ENABLE) - { - /* Enable the acknowledgement */ - I2C->CR |= I2C_Ack_Enable; - } - else - { - /* Disable the acknowledgement */ - I2C->CR &= I2C_Ack_Disable; - } -} - -/******************************************************************************* -* Function Name : I2C_ITConfig -* Description : Enables or disables the I2C interrupt. -* Input : - NewState: new state of the I2C interrupt. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None. -*******************************************************************************/ -void I2C_ITConfig(FunctionalState NewState) -{ - if (NewState == ENABLE) - { - /* Enable the I2C interrupt */ - I2C->CR |= I2C_IT_Enable; - } - else - { - /* Disable the I2C interrupt */ - I2C->CR &= I2C_IT_Disable; - } -} - -/******************************************************************************* -* Function Name : I2C_GetLastEvent -* Description : Gets the last I2C event that has occurred. -* Input : None -* Output : None -* Return : The Last happened Event. -*******************************************************************************/ -u16 I2C_GetLastEvent(void) -{ - u16 Flag1 = 0, Flag2 = 0, LastEvent = 0; - - Flag1 = I2C->SR1; - Flag2 = I2C->SR2; - Flag2 = Flag2<<8; - /* Get the last event value from I2C status register */ - LastEvent = (((Flag1 | (Flag2)) & I2C_Event_Mask)); - /* Return the last event */ - return LastEvent; -} - -/******************************************************************************* -* Function Name : I2C_CheckEvent -* Description : Checks whether the Last I2C Event is equal to the one passed -* as parameter. -* Input : - I2C_EVENT: specifies the event to be checked. This parameter -* can be one of the following values: -* - I2C_EVENT_SLAVE_ADDRESS_MATCHED -* - I2C_EVENT_SLAVE_BYTE_RECEIVED -* - I2C_EVENT_SLAVE_BYTE_TRANSMITTED -* - I2C_EVENT_SLAVE_ACK_FAILURE -* - I2C_EVENT_MASTER_MODE_SELECT -* - I2C_EVENT_MASTER_MODE_SELECTED -* - I2C_EVENT_MASTER_BYTE_RECEIVED -* - I2C_EVENT_MASTER_BYTE_TRANSMITTED -* - I2C_EVENT_MASTER_MODE_ADDRESS10 -* - I2C_EVENT_SLAVE_STOP_DETECTED -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Last event is equal to the I2C_Event -* - ERROR: Last event is different from the I2C_Event -*******************************************************************************/ -ErrorStatus I2C_CheckEvent(u16 I2C_EVENT) -{ - u16 LastEvent = I2C_GetLastEvent(); - - /* Check whether the last event is equal to I2C_EVENT */ - if (LastEvent == I2C_EVENT) - { - /* Return SUCCESS when last event is equal to I2C_EVENT */ - return SUCCESS; - } - else - { - /* Return ERROR when last event is different from I2C_EVENT */ - return ERROR; - } -} - -/******************************************************************************* -* Function Name : I2C_SendData -* Description : Sends a data byte. -* Input : - Data: indicates the byte to be transmitted. -* Output : None -* Return : None. -*******************************************************************************/ -void I2C_SendData(u8 Data) -{ - /* Write in the DR register the byte to be sent */ - I2C->DR = Data; -} - -/******************************************************************************* -* Function Name : I2C_ReceiveData -* Description : Reads the received byte. -* Input : None -* Output : None -* Return : The received byte -*******************************************************************************/ -u8 I2C_ReceiveData(void) -{ - /* Return from the DR register the received byte */ - return I2C->DR; -} - -/******************************************************************************* -* Function Name : I2C_Send7bitAddress -* Description : Transmits the address byte to select the slave device. -* Input : - Address: specifies the slave address which will be transmitted -* - Direction: specifies whether the I2C device will be a -* Transmitter or a Receiver. This parameter can be one of the -* following values -* - I2C_MODE_TRANSMITTER: Transmitter mode -* - I2C_MODE_RECEIVER: Receiver mode -* Output : None -* Return : None. -*******************************************************************************/ -void I2C_Send7bitAddress(u8 Address, u8 Direction) -{ - /* Test on the direction to define the read/write bit */ - if (Direction == I2C_MODE_RECEIVER) - { - /* Set the address bit0 for read */ - Address |= I2C_ADD0_Set; - } - else - { - /* Reset the address bit0 for write */ - Address &= I2C_ADD0_Reset; - } - /* Send the address */ - I2C->DR = Address; -} - -/******************************************************************************* -* Function Name : I2C_ReadRegister -* Description : Reads the specified I2C register and returns its value. -* Input1 : - I2C_Register: specifies the register to read. -* This parameter can be one of the following values: -* - I2C_CR: CR register. -* - I2C_SR1: SR1 register. -* - I2C_SR2: SR2 register. -* - I2C_CCR: CCR register. -* - I2C_OAR1: OAR1 register. -* - I2C_OAR2: OAR2 register. -* - I2C_DR: DR register. -* - I2C_ECCR: ECCR register. -* Output : None -* Return : The value of the read register. -*******************************************************************************/ -u8 I2C_ReadRegister(u8 I2C_Register) -{ - /* Return the selected register value */ - return (*(u8 *)(I2C_BASE + I2C_Register)); -} - -/******************************************************************************* -* Function Name : I2C_GetFlagStatus -* Description : Checks whether the specified I2C flag is set or not. -* Input : - I2C_FLAG: specifies the flag to check. -* This parameter can be one of the following values: -* - I2C_FLAG_SB: Start bit flag (Master mode) -* - I2C_FLAG_M_SL: Master/Slave flag -* - I2C_FLAG_ADSL: Address matched flag (Slave mode) -* - I2C_FLAG_BTF: Byte transfer finished flag -* - I2C_FLAG_BUSY: Bus busy flag -* - I2C_FLAG_TRA: Transmitter/Receiver flag -* - I2C_FLAG_ADD10: 10-bit addressing in Master mode flag -* - I2C_FLAG_EVF: Event flag -* - I2C_FLAG_GCAL: General call flag (slave mode) -* - I2C_FLAG_BERR: Bus error flag -* - I2C_FLAG_ARLO: Arbitration lost flag -* - I2C_FLAG_STOPF: Stop detection flag (slave mode) -* - I2C_FLAG_AF: Acknowledge failure flag -* - I2C_FLAG_ENDAD: End of address transmission flag -* - I2C_FLAG_ACK: Acknowledge enable flag -* Output : None -* Return : The NewState of the I2C_FLAG (SET or RESET). -*******************************************************************************/ -FlagStatus I2C_GetFlagStatus(u16 I2C_FLAG) -{ - u16 Flag1 = 0, Flag2 = 0, Flag3 = 0, Tmp = 0; - - Flag1 = I2C->SR1; - Flag2 = I2C->SR2; - Flag2 = Flag2<<8; - Flag3 = I2C->CR & 0x04; - - /* Get all the I2C flags in a unique register*/ - Tmp = (((Flag1 | (Flag2)) & I2C_Event_Mask) | (Flag3<<12)); - - /* Check the status of the specified I2C flag */ - if((Tmp & I2C_FLAG) != RESET) - { - /* Return SET if I2C_FLAG is set */ - return SET; - } - else - { - /* Return RESET if I2C_FLAG is reset */ - return RESET; - } -} - -/******************************************************************************* -* Function Name : I2C_ClearFlag -* Description : Clears the I2C’s pending flags -* Input : - I2C_FLAG: specifies the flag to clear. -* This parameter can be one of the following values: -* - I2C_FLAG_SB: Start bit flag -* - I2C_FLAG_M_SL: Master/Slave flag -* - I2C_FLAG_ADSL: Adress matched flag -* - I2C_FLAG_BTF: Byte transfer finished flag -* - I2C_FLAG_BUSY: Bus busy flag -* - I2C_FLAG_TRA: Transmitter/Receiver flag -* - I2C_FLAG_ADD10: 10-bit addressing in Master mode flag -* - I2C_FLAG_EVF: Event flag -* - I2C_FLAG_GCAL: General call flag -* - I2C_FLAG_BERR: Bus error flag -* - I2C_FLAG_ARLO: Arbitration lost flag -* - I2C_FLAG_STOPF: Stop detection flag -* - I2C_FLAG_AF: Acknowledge failure flag -* - I2C_FLAG_ENDAD: End of address transmission flag -* - I2C_FLAG_ACK: Acknowledge enable flag -* - parameter needed in the case that the flag to be cleared -* need a write in one register -* Output : None -* Return : None -*******************************************************************************/ -void I2C_ClearFlag(u16 I2C_FLAG, ...) -{ - u8 Tmp = (u8)*((u32 *) & I2C_FLAG + sizeof(I2C_FLAG)); - - /* flags that need a read of the SR2 register to be cleared */ - if ((I2C_FLAG == I2C_FLAG_ADD10) || (I2C_FLAG == I2C_FLAG_EVF) || - (I2C_FLAG == I2C_FLAG_STOPF) || (I2C_FLAG == I2C_FLAG_AF) || - (I2C_FLAG == I2C_FLAG_BERR) || (I2C_FLAG == I2C_FLAG_ARLO) || - (I2C_FLAG == I2C_FLAG_ENDAD)) - { - /* Read the SR2 register */ - (void)I2C->SR2; - - /* Two flags need a second step to be cleared */ - switch (I2C_FLAG) - { - case I2C_FLAG_ADD10: - /* Send the MSB 10bit address passed as second parameter */ - I2C->DR = Tmp; - break; - case I2C_FLAG_ENDAD: - /* Write to the I2C_CR register by setting PE bit */ - I2C->CR |= I2C_PE_Set; - break; - } - } - /* flags that need a read of the SR1 register to be cleared */ - else if (I2C_FLAG==I2C_FLAG_SB || I2C_FLAG==I2C_FLAG_ADSL || I2C_FLAG==I2C_FLAG_BTF || I2C_FLAG==I2C_FLAG_TRA) - { - /* Read the SR1 register */ - (void)I2C->SR1; - - /* three flags need a second step to be cleared */ - if (I2C_FLAG == I2C_FLAG_SB) - { - /* Send the address byte passed as second parameter */ - I2C->DR=Tmp; - } - else if (I2C_FLAG==I2C_FLAG_BTF || I2C_FLAG==I2C_FLAG_TRA) - { - /* return the received byte in the variable passed as second parameter */ - Tmp=I2C->DR; - } - } - /* flags that need to disable the I2C interface */ - else if ( I2C_FLAG==I2C_FLAG_M_SL || I2C_FLAG==I2C_FLAG_GCAL) - { - I2C_Cmd(DISABLE); - I2C_Cmd(ENABLE); - } -} - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_it.c b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_it.c deleted file mode 100644 index b73503624..000000000 --- a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_it.c +++ /dev/null @@ -1,448 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_it.c -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : Main Interrupt Service Routines. -* This file can be used to describe all the exceptions -* subroutines that may occur within user application. -* When an interrupt happens, the software will branch -* automatically to the corresponding routine according -* to the interrupt vector loaded in the PC register. -* The following routines are all empty, user can write code -* for exceptions handlers and peripherals IRQ interrupts. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/******************************************************************************* -* Function Name : Undefined_Handler -* Description : This function handles Undefined instruction exception. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void Undefined_Handler(void) -{ -} - -/******************************************************************************* -* Function Name : FIQ_Handler -* Description : This function handles FIQ exception. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void FIQ_Handler(void) -{ -} - -/******************************************************************************* -* Function Name : SWI_Handler -* Description : This function handles SW exception. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void SWI_Handler(void) -{ -} - -/******************************************************************************* -* Function Name : Prefetch_Handler -* Description : This function handles preftetch abort exception. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void Prefetch_Handler(void) -{ -} - -/******************************************************************************* -* Function Name : Abort_Handler -* Description : This function handles data abort exception. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void Abort_Handler(void) -{ -} - -/******************************************************************************* -* Function Name : WAKUP_IRQHandler -* Description : This function handles External line 15(WAKUP) interrupt -* request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void WAKUP_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : TIM2_OC2_IRQHandler -* Description : This function handles TIM2 Output Compare 2 interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void TIM2_OC2_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : TIM2_OC1_IRQHandler -* Description : This function handles TIM2 Output Compare 1 interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void TIM2_OC1_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : TIM2_IC12_IRQHandler -* Description : This function handles TIM2 Input Capture 1 & 2 interrupt -* request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void TIM2_IC12_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : TIM2_UP_IRQHandler -* Description : This function handles TIM2 Update interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void TIM2_UP_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : TIM1_OC2_IRQHandler -* Description : This function handles TIM1 Output Compare 2 interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void TIM1_OC2_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : TIM1_OC1_IRQHandler -* Description : This function handles TIM1 Output Compare 1 interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void TIM1_OC1_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : TIM1_IC12_IRQHandler -* Description : This function handles TIM1 Input Capture 1 & 2 interrupt -* request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void TIM1_IC12_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : TIM1_UP_IRQHandler -* Description : This function handles TIM1 Update interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void TIM1_UP_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : TIM0_OC2_IRQHandler -* Description : This function handles TIM0 Output Compare 2 interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void TIM0_OC2_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : TIM0_OC1_IRQHandler -* Description : This function handles TIM0 Output Compare 1 interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void TIM0_OC1_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : TIM0_IC12_IRQHandler -* Description : This function handles TIM0 Input Capture 1 & 2 interrupt -* request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void TIM0_IC12_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : TIM0_UP_IRQHandler -* Description : This function handles TIM0 Update interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void TIM0_UP_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : PWM_OC123_IRQHandler -* Description : This function handles PWM Output Compare 1,2&3 interrupt -* request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void PWM_OC123_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : PWM_EM_IRQHandler -* Description : This function handles PWM Emergency interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void PWM_EM_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : PWM_UP_IRQHandler -* Description : This function handles PWM Update interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void PWM_UP_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : I2C_IRQHandler -* Description : This function handles I2C global interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void I2C_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : SSP1_IRQHandler -* Description : This function handles SSP1 interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void SSP1_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : SSP0_IRQHandler -* Description : This function handles SSP0 interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void SSP0_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : UART2_IRQHandler -* Description : This function handles UART2 global interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void UART2_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : UART1_IRQHandler -* Description : This function handles UART1 global interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void UART1_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : UART0_IRQHandler -* Description : This function handles UART0 global interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void UART0_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : CAN_IRQHandler -* Description : This function handles CAN global interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void CAN_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : USBLP_IRQHandler -* Description : This function handles USB Low Priority event interrupt -* request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void USB_LP_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : USBHP_IRQHandler -* Description : This function handles USB High Priority event interrupt -* request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void USB_HP_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : ADC_IRQHandler -* Description : This function handles ADC global interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void ADC_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : DMA_IRQHandler -* Description : This function handles DMA global interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void DMA_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : EXTIT_IRQHandler -* Description : This function handles External lines 14 to 1 interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void EXTIT_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : MRCC_IRQHandler -* Description : This function handles MRCC interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void MRCC_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : FLASHSMI_IRQHandler -* Description : This function handles Flash and SMI global interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void FLASHSMI_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : RTC_IRQHandler -* Description : This function handles RTC global interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void RTC_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : TB_IRQHandler -* Description : This function handles TB global interrupt request. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void TB_IRQHandler(void) -{ -} - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_lib.c b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_lib.c deleted file mode 100644 index 16c87f064..000000000 --- a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_lib.c +++ /dev/null @@ -1,178 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_lib.c -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file provides all peripherals pointers initialization. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#define EXT - -/* Includes ------------------------------------------------------------------*/ -#include "75x_lib.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -#ifdef DEBUG - -/******************************************************************************* -* Function Name : debug -* Description : This function initialize peripherals pointers. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void debug(void) -{ -/************************************* SMI ************************************/ -#ifdef _SMI - SMI = (SMI_TypeDef *) SMIR_BASE; -#endif /*_SMI */ - -/************************************* CFG ************************************/ -#ifdef _CFG - CFG = (CFG_TypeDef *) CFG_BASE; -#endif /*_CFG */ - -/************************************* MRCC ***********************************/ -#ifdef _MRCC - MRCC = (MRCC_TypeDef *) MRCC_BASE; -#endif /*_MRCC */ - -/************************************* ADC ************************************/ -#ifdef _ADC - ADC = (ADC_TypeDef *) ADC_BASE; -#endif /*_ADC */ - -/************************************* TB *************************************/ -#ifdef _TB - TB = (TB_TypeDef *) TB_BASE; -#endif /*_TB */ - -/************************************* TIM ************************************/ -#ifdef _TIM0 - TIM0 = (TIM_TypeDef *) TIM0_BASE; -#endif /*_TIM0 */ - -#ifdef _TIM1 - TIM1 = (TIM_TypeDef *) TIM1_BASE; -#endif /*_TIM1 */ - -#ifdef _TIM2 - TIM2 = (TIM_TypeDef *) TIM2_BASE; -#endif /*_TIM2 */ - -/************************************* PWM ************************************/ -#ifdef _PWM - PWM = (PWM_TypeDef *) PWM_BASE; -#endif /*_PWM */ - -/************************************* WDG ************************************/ -#ifdef _WDG - WDG = (WDG_TypeDef *) WDG_BASE; -#endif /*_WDG */ - -/************************************* SSP ************************************/ -#ifdef _SSP0 - SSP0 = (SSP_TypeDef *) SSP0_BASE; -#endif /*_SSP0 */ - -#ifdef _SSP1 - SSP1 = (SSP_TypeDef *) SSP1_BASE; -#endif /*_SSP1 */ - -/************************************* CAN ************************************/ -#ifdef _CAN - CAN = (CAN_TypeDef *) CAN_BASE; -#endif /*_CAN */ - -/************************************* I2C ************************************/ -#ifdef _I2C - I2C = (I2C_TypeDef *) I2C_BASE; -#endif /*_I2C */ - -/************************************* UART ***********************************/ -#ifdef _UART0 - UART0 = (UART_TypeDef *) UART0_BASE; -#endif /*_UART0 */ - -#ifdef _UART1 - UART1 = (UART_TypeDef *) UART1_BASE; -#endif /*_UART1 */ - -#ifdef _UART2 - UART2 = (UART_TypeDef *) UART2_BASE; -#endif /*_UART2 */ - -/************************************* GPIO ***********************************/ -#ifdef _GPIO0 - GPIO0 = (GPIO_TypeDef *) GPIO0_BASE; -#endif /*_GPIO0 */ - -#ifdef _GPIO1 - GPIO1 = (GPIO_TypeDef *) GPIO1_BASE; -#endif /*_GPIO1 */ - -#ifdef _GPIO2 - GPIO2 = (GPIO_TypeDef *) GPIO2_BASE; -#endif /*_GPIO2 */ - -#ifdef _GPIOREMAP - GPIOREMAP = (GPIOREMAP_TypeDef *) GPIOREMAP_BASE; -#endif /*_GPIOREMAP */ - -/************************************* DMA ************************************/ -#ifdef _DMA - DMA = (DMA_TypeDef *) DMA_BASE; -#endif /*_DMA */ - -#ifdef _DMA_Stream0 - DMA_Stream0 = (DMA_Stream_TypeDef *) DMA_Stream0_BASE; -#endif /*_DMA_Stream0 */ - -#ifdef _DMA_Stream1 - DMA_Stream1 = (DMA_Stream_TypeDef *) DMA_Stream1_BASE; -#endif /*_DMA_Stream1 */ - -#ifdef _DMA_Stream2 - DMA_Stream2 = (DMA_Stream_TypeDef *) DMA_Stream2_BASE; -#endif /*_DMA_Stream2 */ - -#ifdef _DMA_Stream3 - DMA_Stream3 = (DMA_Stream_TypeDef *) DMA_Stream3_BASE; -#endif /*_DMA_Stream3 */ - -/************************************* RTC ************************************/ -#ifdef _RTC - RTC = (RTC_TypeDef *) RTC_BASE; -#endif /*_RTC */ - -/************************************* EXTIT **********************************/ -#ifdef _EXTIT - EXTIT = (EXTIT_TypeDef *) EXTIT_BASE; -#endif /*_EXTIT */ - -/************************************* EIC ************************************/ -#ifdef _EIC - EIC = (EIC_TypeDef *) EIC_BASE; -#endif /*_EIC */ - -} - -#endif - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_mrcc.c b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_mrcc.c deleted file mode 100644 index fadfb73c7..000000000 --- a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_mrcc.c +++ /dev/null @@ -1,1673 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_mrcc.c -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file provides all the MRCC software functions. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -#include "75x_mrcc.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define MRCC_FLAG_Mask 0x1F /* MRCC Flag Mask */ - -/* MRCC_PWRCTRL mask bits */ -#define MRCC_LP_Set_Mask 0x00000001 -#define MRCC_LP_Reset_Mask 0xFFFFFFFE -#define MRCC_SWRESET_Mask 0x00000002 -#define MRCC_WFI_Mask 0x00000004 -#define MRCC_STANDBY_Mask 0x00000006 -#define MRCC_LPMC_Reset_Mask 0xFFFFFFF9 -#define MRCC_LPDONE_Reset_Mask 0xFFFFFF7F -#define MRCC_LPPARAM_Reset_Mask 0xFFFF1FFF -#define MRCC_WFIParam_Reset_Mask 0xFFFF1FEF -#define MRCC_CKRTCSEL_Set_Mask 0x03000000 -#define MRCC_CKRTCSEL_Reset_Mask 0xFCFFFFFF -#define MRCC_CKRTCOK_Mask 0x08000000 -#define MRCC_LPOSCEN_Mask 0x10000000 -#define MRCC_OSC32KEN_Mask 0x20000000 - -/* MRCC_CLKCTL mask bits */ -#define MRCC_PPRESC_Set_Mask 0x00000003 -#define MRCC_PPRESC_Reset_Mask 0xFFFFFFFC -#define MRCC_PPRESC2_Mask 0x00000004 -#define MRCC_HPRESC_Set_Mask 0x00000018 -#define MRCC_HPRESC_Reset_Mask 0xFFFFFFE7 -#define MRCC_MCOS_Reset_Mask 0xFFFFFF3F -#define MRCC_XTDIV2_Set_Mask 0x00008000 -#define MRCC_XTDIV2_Reset_Mask 0xFFFF7FFF -#define MRCC_OSC4MBYP_Set_Mask 0x00010000 -#define MRCC_OSC4MBYP_Reset_Mask 0xFFFEFFFF -#define MRCC_OSC4MOFF_Set_Mask 0x00020000 -#define MRCC_OSC4MOFF_Reset_Mask 0xFFFDFFFF -#define MRCC_NCKDF_Set_Mask 0x00040000 -#define MRCC_NCKDF_Reset_Mask 0xFFFBFFFF -#define MRCC_CKOSCSEL_Set_Mask 0x00200000 -#define MRCC_CKOSCSEL_Reset_Mask 0xFFDFFFFF -#define MRCC_CKUSBSEL_Mask 0x00400000 -#define MRCC_CKSEL_Set_Mask 0x00800000 -#define MRCC_CKSEL_Reset_Mask 0xFF7FFFFF -#define MRCC_CKSEL_CKOSCSEL_Mask 0x00A00000 -#define MRCC_PLLEN_Set_Mask 0x01000000 -#define MRCC_PLLEN_Reset_Mask 0xFEFFFFFF -#define MRCC_PLL2EN_Set_Mask 0x02000000 -#define MRCC_PLL2EN_Reset_Mask 0xFDFFFFFF -#define MRCC_MX_Set_Mask 0x18000000 -#define MRCC_MX_Reset_Mask 0xE7FFFFFF -#define MRCC_LOCK_Mask 0x80000000 -#define MRCC_PLLEN_LOCK_Mask 0x81000000 - -/* Typical Value of the OSC4M in Hz */ -#define OSC4M_Value 4000000 - -/* Typical Value of the OSC4M divided by 128 (used to clock the RTC) in Hz */ -#define OSC4M_Div128_Value 31250 - -/* Typical Value of the OS32K Oscillator Frequency in Hz */ -#define OSC32K_Value 32768 - -/* Typical Reset Value of the Internal LPOSC Oscillator Frequency in Hz */ -#define LPOSC_Value 245000 - -/* Typical Reset Value of the Internal FREEOSC Oscillator Frequency in Hz */ -#define FREEOSC_Value 5000000 - -/* Time out for OSC4M start up */ -#define OSC4MStartUp_TimeOut 0xFE - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -static ErrorStatus SetCKSYS_FREEOSC(void); -static ErrorStatus SetCKSYS_OSC4M(u32 PLL_State); -static ErrorStatus SetCKSYS_OSC4MPLL(u32 PLL_Mul); -static ErrorStatus SetCKSYS_RTC(u32 PLL_State); -static void WriteLPBit(void); -static void WriteCKOSCSELBit(void); - -/* Private functions ---------------------------------------------------------*/ - -/******************************************************************************* -* Function Name : MRCC_DeInit -* Description : Deinitializes the MRCC peripheral registers to their default -* reset values. -* - Depending on the system clock state, some bits in MRCC_CLKCTL -* register can’t be reset. -* - The OSC32K, LPOSC and RTC clock selection configuration -* bits in MRCC_PWRCTRL register are not cleared by this -* function. To reset those bits, use the dedicated functions -* available within this driver. -* - The MRCC_RFSR, MRCC_BKP0 and MRCC_BKP1 registers are not -* reset by this function. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void MRCC_DeInit(void) -{ - /* Try to clear NCKDF bit */ - MRCC->CLKCTL &= MRCC_NCKDF_Reset_Mask; - - if((MRCC->CLKCTL & MRCC_NCKDF_Set_Mask) != RESET) - {/* No clock detected on OSC4M */ - - /* Reset LOCKIE, LOCKIF, CKUSBSEL, NCKDIE, OSC4MOFF, OSC4MBYP, MCOS[1:0], - MCOP, HPRESC[1:0], PPRES[2:0] bits */ - MRCC->CLKCTL &= 0x9FB40000; - - if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) - { - /* Clear CKOSCSEL bit --------------------------------------------------*/ - /* Execute CKOSCSEL bit writing sequence */ - WriteCKOSCSELBit(); - } - } - else - {/* Clock present on OSC4M */ - - if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) - { - /* Reset CKSEL bit */ - MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask; - - /* Clear CKOSCSEL bit --------------------------------------------------*/ - /* Execute CKOSCSEL bit writing sequence */ - WriteCKOSCSELBit(); - } - - if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) == RESET) - { - /* Set CKSEL bit */ - MRCC->CLKCTL |= MRCC_CKSEL_Set_Mask; - } - - /* Disable PLL */ - MRCC->CLKCTL &= MRCC_PLLEN_Reset_Mask; - - /* Reset LOCKIE, LOCKIF, MX[1:0], CKUSBSEL, NCKDIE, MCOS[1:0], MCOP, - HPRESC[1:0], PPRES[2:0] bits */ - MRCC->CLKCTL &= 0x87B70000; - - /* Reset CKSEL bit */ - MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask; - - /* Reset OSC4MOFF and OSC4MBYP bits */ - MRCC->CLKCTL &= 0xFFFCFFFF; - } - - /* Reset RTCM, EN33V, LP_PARAM[15:13], WFI_FLASH_EN, LPMC_DBG and LPMC[1:0] bits */ - MRCC->PWRCTRL &= 0xFBFE1FE1; - - /* Reset PCLKEN register bits */ - MRCC->PCLKEN = 0x00; - - /* Reset PSWRES register bits */ - MRCC->PSWRES = 0x00; - - /* Clear NCKDF bit */ - MRCC->CLKCTL &= MRCC_NCKDF_Reset_Mask; -} - -/******************************************************************************* -* Function Name : MRCC_XTDIV2Config -* Description : Enables or disables the oscillator divider by 2. This function -* must not be used when the PLL is enabled. -* Input : - MRCC_XTDIV2: specifies the new state of the oscillator -* divider by 2. -* This parameter can be one of the following values: -* - MRCC_XTDIV2_Disable: oscillator divider by 2 disbaled -* - MRCC_XTDIV2_Enable: oscillator divider by 2 enbaled -* Output : None -* Return : None -*******************************************************************************/ -void MRCC_XTDIV2Config(u32 MRCC_XTDIV2) -{ - if(MRCC_XTDIV2 == MRCC_XTDIV2_Enable) - { - MRCC->CLKCTL |= MRCC_XTDIV2_Enable; - } - else - { - MRCC->CLKCTL &= MRCC_XTDIV2_Disable; - } -} - -/******************************************************************************* -* Function Name : MRCC_CKSYSConfig -* Description : Configures the system clock (CK_SYS). -* Input : - MRCC_CKSYS: specifies the clock source used as system clock. -* This parameter can be one of the following values: -* - MRCC_CKSYS_FREEOSC -* - MRCC_CKSYS_OSC4M -* - MRCC_CKSYS_OSC4MPLL -* - MRCC_CKSYS_RTC (RTC clock source must be previously -* configured using MRCC_CKRTCConfig() function) -* : - MRCC_PLL: specifies the PLL configuration. -* This parameter can be one of the following values: -* - MRCC_PLL_Disabled: PLL disabled -* - MRCC_PLL_NoChange: No change on PLL configuration -* - MRCC_PLL_Mul_12: Multiplication by 12 -* - MRCC_PLL_Mul_14: Multiplication by 14 -* - MRCC_PLL_Mul_15: Multiplication by 15 -* - MRCC_PLL_Mul_16: Multiplication by 16 -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Clock configuration succeeded -* - ERROR: Clock configuration failed -*******************************************************************************/ -ErrorStatus MRCC_CKSYSConfig(u32 MRCC_CKSYS, u32 MRCC_PLL) -{ - ErrorStatus Status = ERROR; - - switch(MRCC_CKSYS) - { - case MRCC_CKSYS_FREEOSC: - if((MRCC_PLL == MRCC_PLL_Disabled) || (MRCC_PLL == MRCC_PLL_NoChange)) - { - Status = SetCKSYS_FREEOSC(); - } - break; - - case MRCC_CKSYS_OSC4M: - if((MRCC_PLL == MRCC_PLL_Disabled) || (MRCC_PLL == MRCC_PLL_NoChange)) - { - Status = SetCKSYS_OSC4M(MRCC_PLL); - } - break; - - case MRCC_CKSYS_OSC4MPLL: - if((MRCC_PLL == MRCC_PLL_Mul_12) || (MRCC_PLL == MRCC_PLL_Mul_14) || - (MRCC_PLL == MRCC_PLL_Mul_15) || (MRCC_PLL == MRCC_PLL_Mul_16)) - { - Status = SetCKSYS_OSC4MPLL(MRCC_PLL); - } - break; - - case MRCC_CKSYS_RTC: - if((MRCC_PLL == MRCC_PLL_Disabled) || (MRCC_PLL == MRCC_PLL_NoChange)) - { - Status = SetCKSYS_RTC(MRCC_PLL); - } - break; - - default: - Status = ERROR; - break; - } - return Status; -} - -/******************************************************************************* -* Function Name : MRCC_HCLKConfig -* Description : Configures the AHB clock (HCLK). -* Input : - MRCC_HCLK: defines the AHB clock. This clock is derived -* from the system clock(CK_SYS). -* This parameter can be one of the following values: -* - MRCC_CKSYS_Div1: AHB clock = CK_SYS -* - MRCC_CKSYS_Div2: AHB clock = CK_SYS/2 -* - MRCC_CKSYS_Div4: AHB clock = CK_SYS/4 -* - MRCC_CKSYS_Div8: AHB clock = CK_SYS/8 -* Output : None -* Return : None -*******************************************************************************/ -void MRCC_HCLKConfig(u32 MRCC_HCLK) -{ - u32 Temp = 0; - - /* Clear HPRESC[1:0] bits */ - Temp = MRCC->CLKCTL & MRCC_HPRESC_Reset_Mask; - - /* Set HPRESC[1:0] bits according to MRCC_HCLK value */ - Temp |= MRCC_HCLK; - - /* Store the new value */ - MRCC->CLKCTL = Temp; -} - -/******************************************************************************* -* Function Name : MRCC_CKTIMConfig -* Description : Configures the TIM clock (CK_TIM). -* Input : - MRCC_CKTIM: defines the TIM clock. This clock is derived -* from the AHB clock(HCLK). -* This parameter can be one of the following values: -* - MRCC_HCLK_Div1: TIM clock = HCLK -* - MRCC_HCLK_Div2: TIM clock = HCLK/2 -* - MRCC_HCLK_Div4: TIM clock = HCLK/4 -* - MRCC_HCLK_Div8: TIM clock = HCLK/8 -* Output : None -* Return : None -*******************************************************************************/ -void MRCC_CKTIMConfig(u32 MRCC_CKTIM) -{ - u32 Temp = 0; - - /* Clear PPRESC[1:0] bits */ - Temp = MRCC->CLKCTL & MRCC_PPRESC_Reset_Mask; - - /* Set PPRESC[1:0] bits according to MRCC_CKTIM value */ - Temp |= MRCC_CKTIM; - - /* Store the new value */ - MRCC->CLKCTL = Temp; -} - -/******************************************************************************* -* Function Name : MRCC_PCLKConfig -* Description : Configures the APB clock (PCLK). -* Input : - MRCC_PCLK: defines the APB clock. This clock is derived -* from the TIM clock(CK_TIM). -* This parameter can be one of the following values: -* - MRCC_CKTIM_Div1: APB clock = CKTIM -* - MRCC_CKTIM_Div2: APB clock = CKTIM/2 -* Output : None -* Return : None -*******************************************************************************/ -void MRCC_PCLKConfig(u32 MRCC_PCLK) -{ - if(MRCC_PCLK == MRCC_CKTIM_Div2) - { - MRCC->CLKCTL |= MRCC_CKTIM_Div2; - } - else - { - MRCC->CLKCTL &= MRCC_CKTIM_Div1; - } -} - -/******************************************************************************* -* Function Name : MRCC_CKRTCConfig -* Description : Configures the RTC clock (CK_RTC). -* Input : - MRCC_CKRTC: specifies the clock source to be used as RTC -* clock. -* This parameter can be one of the following values: -* - MRCC_CKRTC_OSC4M_Div128 -* - MRCC_CKRTC_OSC32K (OSC32K must be previously enabled -* using MRCC_OSC32KConfig() function) -* - MRCC_CKRTC_LPOSC (LPOSC must be previously enabled -* using MRCC_LPOSCConfig() function) -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Clock configuration succeeded -* - ERROR: Clock configuration failed -*******************************************************************************/ -ErrorStatus MRCC_CKRTCConfig(u32 MRCC_CKRTC) -{ - u32 Tmp = 0; - - if(((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) && - ((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET)) - { - /* CK_RTC used as CK_SYS clock source */ - return ERROR; - } - else - { - /* Clear CKRTCSEL[1:0] bits */ - Tmp = MRCC->PWRCTRL & MRCC_CKRTCSEL_Reset_Mask; - - /* Set CKRTCSEL[1:0] bits according to MRCC_CKRTC value */ - Tmp |= MRCC_CKRTC; - - /* Store the new value */ - MRCC->PWRCTRL = Tmp; - } - - return SUCCESS; -} - -/******************************************************************************* -* Function Name : MRCC_CKUSBConfig -* Description : Configures the USB clock(CK_USB). -* Input : - MRCC_CKUSB: specifies the clock source to be used as USB -* clock. -* This parameter can be one of the following values: -* - MRCC_CKUSB_Internal(CK_PLL2 enabled) -* - MRCC_CKUSB_External(CK_PLL2 disabled) -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Clock configuration succeeded -* - ERROR: Clock configuration failed -*******************************************************************************/ -ErrorStatus MRCC_CKUSBConfig(u32 MRCC_CKUSB) -{ - if(MRCC_CKUSB == MRCC_CKUSB_External) - { - /* Disable CK_PLL2 */ - MRCC->CLKCTL &= MRCC_PLL2EN_Reset_Mask; - - /* External USB clock selected */ - MRCC->CLKCTL |= MRCC_CKUSB_External; - } - else - { - if((MRCC->CLKCTL & MRCC_PLLEN_LOCK_Mask) != RESET) - { /* PLL enabled and locked */ - - /* Enable CK_PLL2 */ - MRCC->CLKCTL |= MRCC_PLL2EN_Set_Mask; - - /* Internal USB clock selected */ - MRCC->CLKCTL &= MRCC_CKUSB_Internal; - } - else - { - /* PLL not enabled */ - return ERROR; - } - } - - return SUCCESS; -} - -/******************************************************************************* -* Function Name : MRCC_ITConfig -* Description : Enables or disables the specified MRCC interrupts. -* Input : - MRCC_IT: specifies the MRCC interrupts sources to be -* enabled or disabled. This parameter can be any combination -* of the following values: -* - MRCC_IT_LOCK: PLL lock interrupt -* - MRCC_IT_NCKD: No Clock detected interrupt -* - NewState: new state of the MRCC interrupts. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void MRCC_ITConfig(u32 MRCC_IT, FunctionalState NewState) -{ - if(NewState == ENABLE) - { - MRCC->CLKCTL |= MRCC_IT; - } - else - { - MRCC->CLKCTL &= ~MRCC_IT; - } -} - -/******************************************************************************* -* Function Name : MRCC_PeripheralClockConfig -* Description : Enables or disables the specified peripheral clock. -* Input : - MRCC_Peripheral: specifies the peripheral to gates its -* clock. More than one peripheral can be selected using -* the “|” operator. -* - NewState: new state of the specified peripheral clock. -* This parameter can be one of the following values: -* - ENABLE: the selected peripheral clock is enabled -* - DISABLE: the selected peripheral clock is disabled -* Output : None -* Return : None -*******************************************************************************/ -void MRCC_PeripheralClockConfig(u32 MRCC_Peripheral, FunctionalState NewState) -{ - if(NewState == ENABLE) - { - MRCC->PCLKEN |= MRCC_Peripheral; - } - else - { - MRCC->PCLKEN &= ~MRCC_Peripheral; - } -} - -/******************************************************************************* -* Function Name : MRCC_PeripheralSWResetConfig -* Description : Forces or releases peripheral software reset. -* Input : - MRCC_Peripheral: specifies the peripheral to reset. More -* than one peripheral can be selected using the “|” operator. -* - NewState: new state of the specified peripheral software -* reset. This parameter can be one of the following values: -* - ENABLE: the selected peripheral is kept under reset -* - DISABLE: the selected peripheral exits from reset -* Output : None -* Return : None -*******************************************************************************/ -void MRCC_PeripheralSWResetConfig(u32 MRCC_Peripheral, FunctionalState NewState) -{ - if(NewState == ENABLE) - { - MRCC->PSWRES |= MRCC_Peripheral; - } - else - { - MRCC->PSWRES &= ~MRCC_Peripheral; - } -} - -/******************************************************************************* -* Function Name : MRCC_GetClocksStatus -* Description : Returns the status and frequencies of different on chip clocks. -* Don’t use this function when CK_SYS is clocked by an external -* clock source (OSC4M bypassed). -* Input : - MRCC_ClocksStatus: pointer to a MRCC_ClocksTypeDef structure -* which will hold the clocks information. -* Output : None -* Return : None -*******************************************************************************/ -void MRCC_GetClocksStatus(MRCC_ClocksTypeDef* MRCC_ClocksStatus) -{ - u32 PLLMul = 0; - u32 Temp = 0; - u32 Presc = 0; - - /* Get the Status of PLL */ - if((MRCC->CLKCTL & MRCC_PLLEN_Set_Mask) == RESET) - { - MRCC_ClocksStatus->PLL_Status = OFF; - } - else - { - MRCC_ClocksStatus->PLL_Status = ON; - } - - /* Get the Status of OSC4M */ - if((MRCC->CLKCTL & MRCC_OSC4MOFF_Set_Mask) == RESET) - { - MRCC_ClocksStatus->OSC4M_Status = ON; - } - else - { - MRCC_ClocksStatus->OSC4M_Status = OFF; - } - - /* Get the Status of LPOSC */ - if((MRCC->PWRCTRL & MRCC_LPOSCEN_Mask) == RESET) - { - MRCC_ClocksStatus->LPOSC_Status = OFF; - } - else - { - MRCC_ClocksStatus->LPOSC_Status = ON; - } - - /* Get the Status of OSC32K */ - if((MRCC->PWRCTRL & MRCC_OSC32KEN_Mask) == RESET) - { - MRCC_ClocksStatus->OSC32K_Status = OFF; - } - else - { - MRCC_ClocksStatus->OSC32K_Status = ON; - } - -/* Get CKU_SB source ---------------------------------------------------------*/ - if((MRCC->CLKCTL & MRCC_CKUSBSEL_Mask) != RESET) - { - MRCC_ClocksStatus->CKUSB_Source = External; - } - else - { - if((MRCC->CLKCTL & MRCC_PLL2EN_Set_Mask) != RESET) - { - MRCC_ClocksStatus->CKUSB_Source = Internal; - - } - else - { - MRCC_ClocksStatus->CKUSB_Source = Disabled; - } - } - -/* Get CK_RTC source ---------------------------------------------------------*/ - Temp = MRCC->PWRCTRL & MRCC_CKRTCSEL_Set_Mask; - Temp = Temp >> 24; - - switch(Temp) - { - case 0x00: - MRCC_ClocksStatus->CKRTC_Source = Disabled; - break; - - case 0x01: - MRCC_ClocksStatus->CKRTC_Source = OSC4M_Div128; - break; - - case 0x02: - MRCC_ClocksStatus->CKRTC_Source = OSC32K; - break; - - case 0x03: - MRCC_ClocksStatus->CKRTC_Source = LPOSC; - break; - - default: - MRCC_ClocksStatus->CKRTC_Source = Disabled; - break; - } - -/* Get CK_SYS source ---------------------------------------------------------*/ - if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET) - {/* CK_OSC used as CK_SYS clock source */ - - if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) - { /* CK_RTC used as CK_OSC clock source */ - MRCC_ClocksStatus->CKSYS_Source = CKRTC; - - if(MRCC_ClocksStatus->CKRTC_Source == OSC32K) - { - /* CK_SYS clock frequency */ - MRCC_ClocksStatus->CKSYS_Frequency = OSC32K_Value; - } - else if(MRCC_ClocksStatus->CKRTC_Source == LPOSC) - - { - /* CK_SYS clock frequency */ - MRCC_ClocksStatus->CKSYS_Frequency = LPOSC_Value; - } - else if(MRCC_ClocksStatus->CKRTC_Source == OSC4M_Div128) - - { - /* CK_SYS clock frequency */ - MRCC_ClocksStatus->CKSYS_Frequency = OSC4M_Div128_Value; - } - } - else - { /* OSC4M used as CK_OSC clock source */ - MRCC_ClocksStatus->CKSYS_Source = OSC4M; - - if((MRCC->CLKCTL & MRCC_XTDIV2_Set_Mask) != RESET) - { - /* CK_SYS clock frequency */ - MRCC_ClocksStatus->CKSYS_Frequency = Main_Oscillator >> 1; - } - else - { - /* CK_SYS clock frequency */ - MRCC_ClocksStatus->CKSYS_Frequency = Main_Oscillator; - } - } - } - else - {/* CK_PLL1 used as CK_SYS clock */ - - if(MRCC_ClocksStatus->PLL_Status == OFF) - { /* FREEOSC used as CK_PLL1 clock source */ - MRCC_ClocksStatus->CKSYS_Source = FREEOSC; - - /* CK_SYS clock frequency */ - MRCC_ClocksStatus->CKSYS_Frequency = FREEOSC_Value; - } - else - { /* OSC4M followed by PLL used as CK_PLL1 clock source */ - MRCC_ClocksStatus->CKSYS_Source = OSC4MPLL; - - /* Get PLL factor ------------------------------------------------------*/ - Temp = MRCC->CLKCTL & MRCC_MX_Set_Mask; - Temp = Temp >> 27; - - switch(Temp) - { - case 0x00: - PLLMul = 16; - break; - - case 0x01: - PLLMul = 15; - break; - - case 0x02: - PLLMul = 14; - break; - - case 0x03: - PLLMul = 12; - break; - - default: - PLLMul = 16; - break; - } - - /* CK_SYS clock frequency */ - MRCC_ClocksStatus->CKSYS_Frequency = OSC4M_Value * PLLMul; - } - } - -/* Compute HCLK, CKTIM and PCLK clocks frequencies ---------------------------*/ - /* Get HCLK prescaler */ - Presc = MRCC->CLKCTL & MRCC_HPRESC_Set_Mask; - Presc = Presc >> 3; - /* HCLK clock frequency */ - MRCC_ClocksStatus->HCLK_Frequency = MRCC_ClocksStatus->CKSYS_Frequency >> Presc; - - /* Get CK_TIM prescaler */ - Presc = MRCC->CLKCTL & MRCC_PPRESC_Set_Mask; - /* CK_TIM clock frequency */ - MRCC_ClocksStatus->CKTIM_Frequency = MRCC_ClocksStatus->HCLK_Frequency >> Presc; - - /* Get PCLK prescaler */ - Presc = MRCC->CLKCTL & MRCC_PPRESC2_Mask; - Presc = Presc >> 2; - /* PCLK clock frequency */ - MRCC_ClocksStatus->PCLK_Frequency = MRCC_ClocksStatus->CKTIM_Frequency >> Presc; -} - -/******************************************************************************* -* Function Name : MRCC_LPMC_DBGonfig -* Description : Enables or disables the Low Power Debug Mode. -* Input : - MRCC_LPDM: specifies the LPDM new state value. -* This parameter can be one of the following values: -* - MRCC_LPDM_Disable -* - MRCC_LPDM_Enable -* Output : None -* Return : None -*******************************************************************************/ -void MRCC_LPMC_DBGConfig(u32 MRCC_LPDM) -{ - if(MRCC_LPDM == MRCC_LPDM_Enable) - { - MRCC->PWRCTRL |= MRCC_LPDM_Enable; - } - else - { - MRCC->PWRCTRL &= MRCC_LPDM_Disable; - } -} - -/******************************************************************************* -* Function Name : MRCC_EnterWFIMode -* Description : Enters WFI mode. -* If the Flash is used in Burst mode, it must be kept enabled -* in WFI mode(use MRCC_WFIParam_FLASHOn as parameter) -* Input : - MRCC_WFIParam: specifies the WFI mode control parameters. -* This parameter can be one of the following values: -* - MRCC_WFIParam_FLASHPowerDown(DMA not allowed during WFI) -* - MRCC_WFIParam_FLASHOn(DMA allowed during WFI) -* - MRCC_WFIParam_FLASHOff(DMA not allowed during WFI) -* Output : None -* Return : None -*******************************************************************************/ -void MRCC_EnterWFIMode(u32 MRCC_WFIParam) -{ -/* Low Power mode configuration ----------------------------------------------*/ - /* Clear LPMC[1:0] bits */ - MRCC->PWRCTRL &= MRCC_LPMC_Reset_Mask; - - /* Select WFI mode */ - MRCC->PWRCTRL |= MRCC_WFI_Mask; - -/* Low Power mode control parameters configuration ---------------------------*/ - /* Clear LP_PARAM[15:13] and WFI_FLASH_EN bits */ - MRCC->PWRCTRL &= MRCC_WFIParam_Reset_Mask; - - if(MRCC_WFIParam != MRCC_WFIParam_FLASHPowerDown) - { - /* Set LP_PARAM[15:13] and WFI_FLASH_EN bits according to MRCC_WFIParam value */ - MRCC->PWRCTRL |= MRCC_WFIParam; - } - -/* Execute the Low Power bit writing sequence --------------------------------*/ - WriteLPBit(); -} - -/******************************************************************************* -* Function Name : MRCC_EnterSTOPMode -* Description : Enters STOP mode. -* Input : - MRCC_STOPParam: specifies the STOP mode control parameters. -* This parameter can be one of the following values: -* - MRCC_STOPParam_Default (OSC4M On, FLASH On, MVREG On) -* - MRCC_STOPParam_OSC4MOff -* - MRCC_STOPParam_FLASHOff -* - MRCC_STOPParam_MVREGOff -* Output : None -* Return : None -*******************************************************************************/ -void MRCC_EnterSTOPMode(u32 MRCC_STOPParam) -{ -/* Low Power mode configuration ----------------------------------------------*/ - /* Clear LPMC[1:0] bits (STOP mode is selected) */ - MRCC->PWRCTRL &= MRCC_LPMC_Reset_Mask; - -/* Low Power mode control parameters configuration ---------------------------*/ - /* Clear LP_PARAM[15:13] bits */ - MRCC->PWRCTRL &= MRCC_LPPARAM_Reset_Mask; - - if(MRCC_STOPParam != MRCC_STOPParam_Default) - { - /* Set LP_PARAM[15:13] bits according to MRCC_STOPParam value */ - MRCC->PWRCTRL |= MRCC_STOPParam; - } - -/* Execute the Low Power bit writing sequence --------------------------------*/ - WriteLPBit(); -} - -/******************************************************************************* -* Function Name : MRCC_EnterSTANDBYMode -* Description : Enters STANDBY mode. -* Make sure that WKPF flag is cleared before using this function. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void MRCC_EnterSTANDBYMode(void) -{ -/* Low Power mode configuration ----------------------------------------------*/ - /* Clear LPMC[1:0] bits */ - MRCC->PWRCTRL &= MRCC_LPMC_Reset_Mask; - - /* Select STANDBY mode */ - MRCC->PWRCTRL |= MRCC_STANDBY_Mask; - -/* Execute the Low Power bit writing sequence --------------------------------*/ - WriteLPBit(); -} - -/******************************************************************************* -* Function Name : MRCC_GenerateSWReset -* Description : Generates a system software reset. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void MRCC_GenerateSWReset(void) -{ -/* Low Power mode configuration ----------------------------------------------*/ - /* Clear LPMC[1:0] bits */ - MRCC->PWRCTRL &= MRCC_LPMC_Reset_Mask; - - /* Select software reset */ - MRCC->PWRCTRL |= MRCC_SWRESET_Mask; - -/* Execute the Low Power bit writing sequence --------------------------------*/ - WriteLPBit(); -} - -/******************************************************************************* -* Function Name : MRCC_WriteBackupRegister -* Description : Writes user data to the specified backup register. -* Input : - MRCC_BKP: specifies the backup register. -* This parameter can be one of the following values: -* - MRCC_BKP0 -* - MRCC_BKP1 -* - Data: data to write. -* Output : None -* Return : None -*******************************************************************************/ -void MRCC_WriteBackupRegister(MRCC_BKPReg MRCC_BKP, u32 Data) -{ - if(MRCC_BKP == MRCC_BKP0) - { - MRCC->BKP0 = Data; - } - else - { - MRCC->BKP1 = Data; - } -} - -/******************************************************************************* -* Function Name : MRCC_ReadBackupRegister -* Description : Reads data from the specified backup register. -* Input : - MRCC_BKP: specifies the backup register. -* This parameter can be one of the following values: -* - MRCC_BKP0 -* - MRCC_BKP1 -* Output : None -* Return : The content of the specified backup register. -*******************************************************************************/ -u32 MRCC_ReadBackupRegister(MRCC_BKPReg MRCC_BKP) -{ - if(MRCC_BKP == MRCC_BKP0) - { - return(MRCC->BKP0); - } - else - { - return(MRCC->BKP1); - } -} - -/******************************************************************************* -* Function Name : MRCC_IOVoltageRangeConfig -* Description : Configures the I/O pins voltage range. -* Input : - MRCC_IOVoltageRange: specifies the I/O pins voltage range. -* This parameter can be one of the following values: -* - MRCC_IOVoltageRange_5V -* - MRCC_IOVoltageRange_3V3 -* Output : None -* Return : None -*******************************************************************************/ -void MRCC_IOVoltageRangeConfig(u32 MRCC_IOVoltageRange) -{ - if(MRCC_IOVoltageRange == MRCC_IOVoltageRange_3V3) - { - MRCC->PWRCTRL |= MRCC_IOVoltageRange_3V3; - } - else - { - MRCC->PWRCTRL &= MRCC_IOVoltageRange_5V; - } -} - -/******************************************************************************* -* Function Name : MRCC_MCOConfig -* Description : Selects the clock source to output on MCO pin (P0.1). -* To output the clock, the associated alternate function must -* be enabled in the I/O port controller. -* Input : - MRCC_MCO: specifies the clock source to output. -* This parameter can be one of the following values: -* - MRCC_MCO_HCLK -* - MRCC_MCO_PCLK -* - MRCC_MCO_OSC4M -* - MRCC_MCO_CKPLL2 -* - MRCC_MCOPrescaler: specifies if prescaler, divide by 1 or 2, -* is applied to this clock before outputting it to MCO pin. -* This parameter can be one of the following values: -* - MRCC_MCOPrescaler_1 -* - MRCC_MCOPrescaler_2 -* Output : None -* Return : None -*******************************************************************************/ -void MRCC_MCOConfig(u32 MRCC_MCO, u32 MCO_MCOPrescaler) -{ - u32 Temp = 0; -/* MCO prescaler configuration -----------------------------------------------*/ - if(MCO_MCOPrescaler == MRCC_MCOPrescaler_2) - { - MRCC->CLKCTL |= MRCC_MCOPrescaler_2; - } - else - { - MRCC->CLKCTL &= MRCC_MCOPrescaler_1; - } - -/* MCO selection configuration -----------------------------------------------*/ - - /* Clear MCOS[1:0] bits */ - Temp = MRCC->CLKCTL & MRCC_MCOS_Reset_Mask; - - /* Set MCOS[1:0] bits according to MRCC_MCO value */ - Temp |= MRCC_MCO; - - /* Store the new value */ - MRCC->CLKCTL = Temp; -} - -/******************************************************************************* -* Function Name : MRCC_OSC4MConfig -* Description : Configures the 4MHz main oscillator (OSC4M). -* This function must be used when the CK_SYS is not clocked -* by the OSC4M and the PLL is not enabled. -* Input : - MRCC_OSC4M: specifies the new state of the OSC4M oscillator. -* This parameter can be one of the following values: -* - MRCC_OSC4M_Default: OSC4M enabled, bypass disabled -* - MRCC_OSC4M_Disable: OSC4M disabled -* - MRCC_OSC4M_Bypass: OSC4M bypassed -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Clock configuration succeeded -* - ERROR: Clock configuration failed -*******************************************************************************/ -ErrorStatus MRCC_OSC4MConfig(u32 MRCC_OSC4M) -{ - ErrorStatus Status = SUCCESS; - -/* If CK_SYS is driven by OSC4M or the PLL is enabled, exit ------------------*/ - if(((MRCC->CLKCTL & MRCC_CKSEL_CKOSCSEL_Mask) == MRCC_CKSEL_Set_Mask) || - (((MRCC->CLKCTL & MRCC_CKSEL_CKOSCSEL_Mask) == MRCC_CKSEL_CKOSCSEL_Mask) && - ((MRCC->PWRCTRL & MRCC_CKRTCSEL_Reset_Mask) != RESET))|| - ((MRCC->CLKCTL & MRCC_PLLEN_Set_Mask) != RESET)) - { - Status = ERROR; - } -/* Else configure the OSC4MOFF and OSC4MBYP bits -----------------------------*/ - else - { - switch(MRCC_OSC4M) - { - case MRCC_OSC4M_Default: - MRCC->CLKCTL &= MRCC_OSC4MOFF_Reset_Mask & MRCC_OSC4MBYP_Reset_Mask; - break; - - case MRCC_OSC4M_Disable: - MRCC->CLKCTL &= MRCC_OSC4MBYP_Reset_Mask; - MRCC->CLKCTL |= MRCC_OSC4MOFF_Set_Mask; - break; - - case MRCC_OSC4M_Bypass: - MRCC->CLKCTL &= MRCC_OSC4MOFF_Reset_Mask; - MRCC->CLKCTL |= MRCC_OSC4MBYP_Set_Mask; - break; - - default: - Status = ERROR; - break; - } - } - - return Status; -} - -/******************************************************************************* -* Function Name : MRCC_OSC32KConfig -* Description : Configures the OSC32K oscillator. -* This function must be used when the CK_SYS is not clocked by -* the CK_RTC. -* Input : - MRCC_OSC32K: specifies the new state of the OSC32K oscillator. -* This parameter can be one of the following values: -* - MRCC_OSC32K_Disable: OSC32K disabled -* - MRCC_OSC32K_Enable: OSC32K enabled -* - MRCC_OSC32KBypass: specifies if the OSC32K oscillator is -* bypassed or not. -* This parameter can be one of the following values: -* - MRCC_OSC32KBypass_Disable: OSC32K selected -* - MRCC_OSC32KBypass_Enable: OSC32K bypassed -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Clock configuration succeeded -* - ERROR: Clock configuration failed -*******************************************************************************/ -ErrorStatus MRCC_OSC32KConfig(u32 MRCC_OSC32K, u32 MRCC_OSC32KBypass) -{ -/* If CK_SYS is driven by CK_RTC, exit ---------------------------------------*/ - if(((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET) && - ((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET)) - { - return ERROR; - } -/* Else configure the OSC32KEN and OSC32KBYP bits ----------------------------*/ - else - { - /* Configure OSC32KEN bit */ - if(MRCC_OSC32K == MRCC_OSC32K_Enable) - { - MRCC->PWRCTRL |= MRCC_OSC32K_Enable; - } - else - { - MRCC->PWRCTRL &= MRCC_OSC32K_Disable; - } - - /* Configure OSC32KBYP bit */ - if(MRCC_OSC32KBypass == MRCC_OSC32KBypass_Enable) - { - MRCC->PWRCTRL |= MRCC_OSC32KBypass_Enable; - } - else - { - MRCC->PWRCTRL &= MRCC_OSC32KBypass_Disable; - } - - return SUCCESS; - } -} - -/******************************************************************************* -* Function Name : MRCC_LPOSCConfig -* Description : Enables or disables the LPOSC oscillator. -* This function must be used when the CK_SYS is not clocked by -* the CK_RTC. -* Input : - MRCC_LPOSC: specifies the new state of the LPOSC oscillator. -* This parameter can be one of the following values: -* - MRCC_LPOSC_Disable: LPOSC disabled -* - MRCC_LPOSC_Enable: LPOSC enabled -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Clock configuration succeeded -* - ERROR: Clock configuration failed -*******************************************************************************/ -ErrorStatus MRCC_LPOSCConfig(u32 MRCC_LPOSC) -{ -/* If CK_SYS is driven by CK_RTC or LPOSC is used as CK_RTC clock source, exit*/ - if((((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET) && - ((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET)) || - ((MRCC->PWRCTRL & MRCC_CKRTCSEL_Set_Mask) == MRCC_CKRTC_LPOSC)) - { - return ERROR; - } -/* Else configure the LPOSCEN bit --------------------------------------------*/ - else - { - if(MRCC_LPOSC == MRCC_LPOSC_Enable) - { - MRCC->PWRCTRL |= MRCC_LPOSC_Enable; - } - else - { - MRCC->PWRCTRL &= MRCC_LPOSC_Disable; - } - - return SUCCESS; - } -} - -/******************************************************************************* -* Function Name : MRCC_RTCMConfig -* Description : Enables or disables RTC clock measurement. -* Input : - MRCC_RTCM: specifies whether CK_RTC is connected to TB -* timer IC1 or not. -* This parameter can be one of the following values: -* - MRCC_RTCM_Disable: CK_RTC not connected to TB timer IC1 -* - MRCC_RTCM_Enable: CK_RTC connected to TB timer IC1 -* Output : None -* Return : None -*******************************************************************************/ -void MRCC_RTCMConfig(u32 MRCC_RTCM) -{ - if(MRCC_RTCM == MRCC_RTCM_Enable) - { - MRCC->PWRCTRL |= MRCC_RTCM_Enable; - } - else - { - MRCC->PWRCTRL &= MRCC_RTCM_Disable; - } -} - -/******************************************************************************* -* Function Name : MRCC_SetBuilderCounter -* Description : Sets the builder counter value which defines the delay for -* the 4MHz main oscillator (OSC4M) clock to be stabilized. -* Input : - BuilderCounter: defines the delay for the OSC4M oscillator -* clock to be stabilized. -* Output : None -* Return : None -*******************************************************************************/ -void MRCC_SetBuilderCounter(u8 BuilderCounter) -{ - *(u8 *) 0x60000026 = BuilderCounter; -} - -/******************************************************************************* -* Function Name : MRCC_GetCKSYSCounter -* Description : Gets the result of the delay applied to CK_SYS before -* starting the CPU. -* Input : None -* Output : None -* Return : SCOUNT value. -*******************************************************************************/ -u16 MRCC_GetCKSYSCounter(void) -{ - return((u16)(MRCC->RFSR & 0x0FFF)); -} - -/******************************************************************************* -* Function Name : MRCC_GetFlagStatus -* Description : Checks whether the specified MRCC flag is set or not. -* Input : - MRCC_FLAG: specifies the flag to check. -* This parameter can be one of the following values: -* - MRCC_FLAG_LOCK: PLL Locked flag -* - MRCC_FLAG_LOCKIF: PLL Lock Interrupt status flag -* - MRCC_FLAG_CKSEL: CK_SYS source staus flag -* - MRCC_FLAG_CKOSCSEL: CK_OSC clock source staus flag -* - MRCC_FLAG_NCKD: No Clock Detected flag -* - MRCC_FLAG_SWR: Software Reset flag -* - MRCC_FLAG_WDGR: Watchdog Reset flag -* - MRCC_FLAG_EXTR: External Reset flag -* - MRCC_FLAG_WKP: Wake-Up flag -* - MRCC_FLAG_STDB: STANDBY flag -* - MRCC_FLAG_BCOUNT: Builder Counter Flag -* - MRCC_FLAG_OSC32KRDY: Oscillator 32K Ready -* - MRCC_FLAG_CKRTCOK: CK_RTC OK -* - MRCC_FLAG_LPDONE: Low Power Bit Sequence has been performed -* - MRCC_FLAG_LP: Low Power Mode Entry -* Output : None -* Return : The new state of MRCC_FLAG (SET or RESET). -*******************************************************************************/ -FlagStatus MRCC_GetFlagStatus(u8 MRCC_FLAG) -{ - u32 MRCCReg = 0, FlagPos = 0; - u32 StatusReg = 0; - - /* Get the MRCC register index */ - MRCCReg = MRCC_FLAG >> 5; - - /* Get the flag position */ - FlagPos = MRCC_FLAG & MRCC_FLAG_Mask; - - if(MRCCReg == 1) /* The flag to check is in CLKCTL register */ - { - StatusReg = MRCC->CLKCTL; - } - else if (MRCCReg == 2) /* The flag to check is in RFSR register */ - { - StatusReg = MRCC->RFSR; - } - else if(MRCCReg == 3) /* The flag to check is in PWRCTRL register */ - { - StatusReg = MRCC->PWRCTRL; - } - - if((StatusReg & (1 << FlagPos))!= RESET) - { - return SET; - } - else - { - return RESET; - } -} - -/******************************************************************************* -* Function Name : MRCC_ClearFlag -* Description : Clears the MRCC’s pending flags. -* Input : - MRCC_FLAG: specifies the flag to clear. -* This parameter can be one of the following values: -* - MRCC_FLAG_NCKD: No Clock Detected flag -* - MRCC_FLAG_SWR: Software Reset flag -* - MRCC_FLAG_WDGR: Watchdog Reset flag -* - MRCC_FLAG_EXTR: External Reset flag -* - MRCC_FLAG_WKP: Wake-Up flag -* - MRCC_FLAG_STDB: STANDBY flag -* - MRCC_FLAG_LPDONE: Low Power Bit Sequence has been performed -* Output : None -* Return : None -*******************************************************************************/ -void MRCC_ClearFlag(u8 MRCC_FLAG) -{ - u32 MRCCReg = 0, FlagPos = 0; - - /* Get the MRCC register index */ - MRCCReg = MRCC_FLAG >> 5; - - /* Get the flag position */ - FlagPos = MRCC_FLAG & MRCC_FLAG_Mask; - - if(MRCCReg == 1) /* The flag to clear is in CLKCTL register */ - { - MRCC->CLKCTL &= ~(1 << FlagPos); - } - else if (MRCCReg == 2) /* The flag to clear is in RFSR register */ - { - MRCC->RFSR &= ~(1 << FlagPos); - } - else if(MRCCReg == 3) /* The flag to clear is in PWRCTRL register */ - { - MRCC->PWRCTRL &= ~(1 << FlagPos); - } -} - -/******************************************************************************* -* Function Name : MRCC_GetITStatus -* Description : Checks whether the specified MRCC interrupt has occurred or not. -* Input : - MRCC_IT: specifies the MRCC interrupt source to check. -* This parameter can be one of the following values: -* - MRCC_IT_LOCK: PLL lock interrupt -* - MRCC_IT_NCKD: No Clock detected interrupt -* Output : None -* Return : The new state of MRCC_IT (SET or RESET). -*******************************************************************************/ -ITStatus MRCC_GetITStatus(u32 MRCC_IT) -{ - /* Check the specified interrupt pending bit */ - if((MRCC->CLKCTL & (MRCC_IT >> 1)) != RESET) - { - return SET; - } - else - { - return RESET; - } -} - -/******************************************************************************* -* Function Name : MRCC_ClearITPendingBit -* Description : Clears the MRCC’s interrupt pending bits. -* Input : - MRCC_IT: specifies the interrupt pending bit to clear. -* This parameter can be any combination of the following -* values: -* - MRCC_IT_LOCK: PLL lock interrupt -* - MRCC_IT_NCKD: No Clock detected interrupt -* Output : None -* Return : None -*******************************************************************************/ -void MRCC_ClearITPendingBit(u32 MRCC_IT) -{ - /* Clear the specified interrupt pending bit */ - MRCC->CLKCTL &= ~(MRCC_IT >> 1); -} - -/******************************************************************************* -* Function Name : MRCC_WaitForOSC4MStartUp -* Description : Waits for OSC4M start-up. -* Input : None -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: OSC4M oscillator is stable and ready to use -* - ERROR: no clock is detected on OSC4M -*******************************************************************************/ -ErrorStatus MRCC_WaitForOSC4MStartUp(void) -{ - u32 StartUpCounter = 0; - - do - { - /* Clear No Clock Detected flag */ - if(MRCC_GetFlagStatus(MRCC_FLAG_NCKD) != RESET) - { - MRCC_ClearFlag(MRCC_FLAG_NCKD); - } - - StartUpCounter++; - - }while((MRCC_GetFlagStatus(MRCC_FLAG_BCOUNT) == RESET)&& - (StartUpCounter != OSC4MStartUp_TimeOut)); - - if(MRCC_GetFlagStatus(MRCC_FLAG_BCOUNT) != RESET) - { - return SUCCESS; - } - else - { - return ERROR; - } -} - -/******************************************************************************* -* Function Name : SetCKSYS_FREEOSC -* Description : Selects FREEOSC as CK_SYS clock source. -* Input : None -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Clock configuration succeeded -* - ERROR: Clock configuration failed -*******************************************************************************/ -static ErrorStatus SetCKSYS_FREEOSC(void) -{ - /* Check if the PLL is enabled */ - if((MRCC->CLKCTL & MRCC_PLLEN_Set_Mask) != RESET) - { - if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) == RESET) - { /* CK_PLL1 used as Ck_SYS clock source*/ - - if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) - {/* Check if CK_RTC source clock is present*/ - if((MRCC->PWRCTRL & MRCC_CKRTCSEL_Set_Mask) == RESET) - { - /* CK_RTC disabled*/ - return ERROR; - } - } - - /* Select CK_OSC as CK_SYS clock source */ - MRCC->CLKCTL |= MRCC_CKSEL_Set_Mask; - } - - /* Disable PLL */ - MRCC->CLKCTL &= MRCC_PLLEN_Reset_Mask; - } - - /* Select CK_PLL1 as CK_SYS clock source */ - MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask; - - if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) == RESET) - { - return SUCCESS; - } - else - { - return ERROR; - } -} - -/******************************************************************************* -* Function Name : SetCKSYS_OSC4M -* Description : Selects 4MHz main oscillator (OSC4M) as CK_SYS clock source. -* Input : PLL_State: specifies the PLL state. -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Clock configuration succeeded -* - ERROR: Clock configuration failed -*******************************************************************************/ -static ErrorStatus SetCKSYS_OSC4M(u32 PLL_State) -{ -/* If OSC4M is not present, exit ---------------------------------------------*/ - if(((MRCC->CLKCTL & MRCC_NCKDF_Set_Mask) != RESET) || - ((MRCC->CLKCTL & MRCC_OSC4MOFF_Set_Mask) != RESET) ) - { - /* OSC4M disabled or OSC4M clock is not present*/ - return ERROR; - } - -/* Else configure CKSEL and CKOSCSEL bits ------------------------------------*/ - if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) - { /* CK_RTC used as CK_OSC clock */ - - if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET) - { - /* Select CK_PLL1 as CK_SYS clock source */ - MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask; - } - - /* Clear CKOSCSEL bit ----------------------------------------------------*/ - /* Execute CKOSCSEL bit writing sequence */ - WriteCKOSCSELBit(); - - /* Check if CKOSCSEL is set to 0 */ - if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) - { - return ERROR; - } - } - - /* Select CK_OSC as CK_SYS clock source */ - MRCC->CLKCTL |= MRCC_CKSEL_Set_Mask; - - if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET) - { - if(PLL_State == MRCC_PLL_Disabled) - { - /* Disable PLL */ - MRCC->CLKCTL &= MRCC_PLLEN_Reset_Mask; - } - - return SUCCESS; - } - else - { - return ERROR; - } -} - -/******************************************************************************* -* Function Name : SetCKSYS_OSC4MPLL -* Description : Selects 4MHz main oscillator (OSC4M) followed by PLL as -* CK_SYS clock source. -* Input : PLL_Mul: specifies the PLL factor. -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Clock configuration succeeded -* - ERROR: Clock configuration failed -*******************************************************************************/ -static ErrorStatus SetCKSYS_OSC4MPLL(u32 PLL_Mul) -{ - /* Check if 4MHz main oscillator clock is present */ - if(((MRCC->CLKCTL & MRCC_NCKDF_Set_Mask) == RESET) && - ((MRCC->CLKCTL & MRCC_OSC4MOFF_Set_Mask) == RESET)) - { - if(((MRCC->CLKCTL & MRCC_PLLEN_Set_Mask) != RESET) && - ((MRCC->CLKCTL & MRCC_MX_Set_Mask) == PLL_Mul)) - { - /* Select CK_PLL1 as CK_SYS clock source */ - MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask; - - if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) == RESET) - { - return SUCCESS; - } - else - { - return ERROR; - } - } - else - { - /* If CK_RTC is selected as CK_OSC clock source */ - if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) - { - if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET) - { - /* Clear CKSEL bit */ - MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask; - } - - /* Clear CKOSCSEL bit ------------------------------------------------*/ - /* Execute CKOSCSEL bit writing sequence */ - WriteCKOSCSELBit(); - - /* Check if CKOSCSEL is set to 0 */ - if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) != RESET) - { - return ERROR; - } - } - - /* Select CK_OSC as CK_SYS clock source */ - MRCC->CLKCTL |= MRCC_CKSEL_Set_Mask; - - /* Disable PLL */ - MRCC->CLKCTL &= MRCC_PLLEN_Reset_Mask; - - /* Configure PLL factor */ - if(PLL_Mul == MRCC_PLL_Mul_16) - { - MRCC->CLKCTL &= MRCC_MX_Reset_Mask; - } - else if((PLL_Mul == MRCC_PLL_Mul_15) || (PLL_Mul == MRCC_PLL_Mul_14) || - (PLL_Mul == MRCC_PLL_Mul_12)) - { - /* Clear MX[1:0] bits */ - MRCC->CLKCTL &= MRCC_MX_Reset_Mask; - /* Set MX[1:0] bits according to PLL_Mul value */ - MRCC->CLKCTL |= PLL_Mul; - } - - if(Main_Oscillator == 4000000) - {/* 4 MHz external Quartz oscillator used as main oscillator */ - /* Disable Oscillator Divider by 2 */ - MRCC->CLKCTL &= MRCC_XTDIV2_Reset_Mask; - } - else if(Main_Oscillator == 8000000) - {/* 8 MHz external Quartz oscillator used as main oscillator */ - /* Enable Oscillator Divider by 2 */ - MRCC->CLKCTL |= MRCC_XTDIV2_Set_Mask; - } - - /* Enable PLL */ - MRCC->CLKCTL |= MRCC_PLLEN_Set_Mask; - - /* Wait until the PLL is locked */ - while((MRCC->CLKCTL & MRCC_LOCK_Mask) == RESET) - { - /* If OSC4M clock disapear or the PLL is disabled, exit */ - if(((MRCC->CLKCTL & MRCC_NCKDF_Set_Mask) != RESET) || - ((MRCC->CLKCTL & MRCC_PLLEN_Set_Mask) == RESET)) - { - return ERROR; - } - } - - /* Select CK_PLL1 as CK_SYS clock source */ - MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask; - - if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) == RESET) - { - return SUCCESS; - } - else - { - return ERROR; - } - } - } - else - { - /* OSC4M disabled or OSC4M clock is not present*/ - return ERROR; - } -} - -/******************************************************************************* -* Function Name : SetCKSYS_RTC -* Description : Selects RTC clock (CK_RTC) as CK_SYS clock source. -* Input : PLL_State: specifies the PLL state. -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Clock configuration succeeded -* - ERROR: Clock configuration failed -*******************************************************************************/ -static ErrorStatus SetCKSYS_RTC(u32 PLL_State) -{ - /* Check if CK_RTC clock is enabled and ready to use */ - if(((MRCC->PWRCTRL & MRCC_CKRTCSEL_Set_Mask) != RESET)|| - ((MRCC->CLKCTL & MRCC_CKRTCOK_Mask) == RESET)) - { -/* Configure CK_RTC as Ck_SYS clock source -----------------------------------*/ - if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) == RESET) - { - /* Select CK_PLL1 as CK_SYS clock source */ - MRCC->CLKCTL &= MRCC_CKSEL_Reset_Mask; - - /* Set CKOSCSEL bit ----------------------------------------------------*/ - /* Execute CKOSCSEL bit writing sequence */ - WriteCKOSCSELBit(); - - /* Check if CKOSCSEL is set to 1 */ - if((MRCC->CLKCTL & MRCC_CKOSCSEL_Set_Mask) == RESET) - { - return ERROR; - } - } - - /* Select CK_OSC as CK_SYS clock source */ - MRCC->CLKCTL |= MRCC_CKSEL_Set_Mask; - - if((MRCC->CLKCTL & MRCC_CKSEL_Set_Mask) != RESET) - { - if(PLL_State == MRCC_PLL_Disabled) - { - /* Disable PLL */ - MRCC->CLKCTL &= MRCC_PLLEN_Reset_Mask; - } - - return SUCCESS; - } - else - { - return ERROR; - } - } - else - { - /* CK_RTC disabled */ - return ERROR; - } -} - -/******************************************************************************* -* Function Name : WriteLPBit -* Description : Executes the Low Power bit writing sequence. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -static void WriteLPBit(void) -{ - u32 Tmp = 0, Tmp1 = 0, Tmp2 = 0; - - /* Clear LP_DONE flag */ - MRCC->PWRCTRL &= MRCC_LPDONE_Reset_Mask; - - Tmp = MRCC->PWRCTRL; - Tmp1 = Tmp | MRCC_LP_Set_Mask; - Tmp2 = Tmp & MRCC_LP_Reset_Mask; - - /* Set LP bit */ - MRCC->PWRCTRL = Tmp1; - - /* Set LP bit */ - MRCC->PWRCTRL = Tmp1; - - /* Reset LP bit */ - MRCC->PWRCTRL = Tmp2; - - /* Set LP bit */ - MRCC->PWRCTRL = Tmp1; - - /* Read LP bit*/ - Tmp = MRCC->PWRCTRL; -} - -/******************************************************************************* -* Function Name : WriteCKOSCSELBit -* Description : Executes the CKOSCSEL bit writing sequence. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -static void WriteCKOSCSELBit(void) -{ - u32 Tmp = 0, Tmp1 = 0, Tmp2 = 0; - - Tmp = MRCC->CLKCTL; - Tmp1 = Tmp | MRCC_CKOSCSEL_Set_Mask; - Tmp2 = Tmp & MRCC_CKOSCSEL_Reset_Mask; - - /* Set CKOSCSEL bit */ - MRCC->CLKCTL = Tmp1; - - /* Set CKOSCSEL bit */ - MRCC->CLKCTL = Tmp1; - - /* Reset CKOSCSEL bit */ - MRCC->CLKCTL = Tmp2; - - /* Set CKOSCSEL bit */ - MRCC->CLKCTL = Tmp1; - - /* Read CKOSCSEL bit */ - Tmp = MRCC->CLKCTL; -} -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_pwm.c b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_pwm.c deleted file mode 100644 index 79c15aa5b..000000000 --- a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_pwm.c +++ /dev/null @@ -1,1153 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_pwm.c -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file provides all the PWM software functions. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -#include "75x_pwm.h" -#include "75x_mrcc.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* PWM interrupt masks */ -#define PWM_IT_Clear_Mask 0x7FFF -#define PWM_IT_Enable_Mask 0xEFFF - -/* PWM_CR Masks bit */ -#define PWM_CounterMode_Mask 0xFF8F -#define PWM_DBASE_Mask 0x077F -#define PWM_MasterModeSelection_Mask 0xFC7F - -/* PWM Update flag selection Set/Reset value */ -#define PWM_UFS_Reset 0xFFFE -#define PWM_UFS_Set 0x0001 - -/* PWM Counter value */ -#define PWM_COUNTER_Reset 0x0002 -#define PWM_COUNTER_Start 0x0004 -#define PWM_COUNTER_Stop 0xFFFB - -/* PWM Debug Mode Set/Reset value */ -#define PWM_DBGC_Set 0x0400 -#define PWM_DBGC_Reset 0xFBFF - -/* PWM Output Compare Polarity Set/Reset value */ -#define PWM_OC1P_Set 0x0020 -#define PWM_OC1P_Reset 0xFFDF - -#define PWM_OC1NP_Set 0x0080 -#define PWM_OC1NP_Reset 0xFF7F - -#define PWM_OC2P_Set 0x2000 -#define PWM_OC2P_Reset 0xDFFF - -#define PWM_OC2NP_Set 0x8000 -#define PWM_OC2NP_Reset 0x7FFF - -#define PWM_OC3P_Set 0x0020 -#define PWM_OC3P_Reset 0xFFDF - -#define PWM_OC3NP_Set 0x0080 -#define PWM_OC3NP_Reset 0xFF7F - -/* PWM Output Compare control mode constant */ -#define PWM_OCControl_PWM 0x000C -#define PWM_OCControl_OCToggle 0x0006 -#define PWM_OCControl_OCInactive 0x0004 -#define PWM_OCControl_OCActive 0x0002 -#define PWM_OCControl_OCTiming 0x0000 - -/* PWM Output Compare mode Enable value */ -#define PWM_OC1_Enable 0x0010 -#define PWM_OC2_Enable 0x1000 -#define PWM_OC3_Enable 0x0010 - -#define PWM_OC1_Disable 0xFFEF -#define PWM_OC2_Disable 0xEFFF -#define PWM_OC3_Disable 0xFFEF - -#define PWM_OC1N_Enable 0x0040 -#define PWM_OC2N_Enable 0x4000 -#define PWM_OC3N_Enable 0x0040 - -#define PWM_OC1N_Disable 0xFFBF -#define PWM_OC2N_Disable 0xBFFF -#define PWM_OC3N_Disable 0xFFBF - -/* PWM Output Compare mode Mask value */ -#define PWM_OC1C_Mask 0xFFF1 -#define PWM_OC2C_Mask 0xF1FF -#define PWM_OC3C_Mask 0xFFF1 - -/* PWM Preload bit Set/Reset value */ -#define PWM_PLD1_Set 0x0001 -#define PWM_PLD2_Set 0x0100 -#define PWM_PLD3_Set 0x0001 - -/* PWM OCRM Set/Reset value */ -#define PWM_OCMR_Set 0x0080 -#define PWM_OCMR_Reset 0xFF7F - -/* PWM_DTR bit Masks value */ -#define PWM_DTR_Mask 0xFC00 -#define PWM_LOCK_Mask 0xF3FF - -/* PWM MOE Set value */ -#define PWM_MOE_Set 0x8000 -#define PWM_MOE_Reset 0x7FFF - -/* PWM OSSR bit Set/Reset value */ -#define PWM_OSSR_Set 0x4000 -#define PWM_OSSR_Reset 0xBFFF - -/* Reset Register Masks */ -#define PWM_Prescaler_Reset_Mask 0x0000 -#define PWM_Pulse1_Reset_Mask 0x0000 -#define PWM_Pulse2_Reset_Mask 0x0000 -#define PWM_Pulse3_Reset_Mask 0x0000 -#define PWM_Period_Reset_Mask 0xFFFF -#define PWM_RepetitionCounter_Reset_Mask 0x0000 -#define PWM_DeadTime_Reset_Mask 0x0000 - -/* Private function prototypes -----------------------------------------------*/ -static void OCM_ModuleConfig(PWM_InitTypeDef* PWM_InitStruct); - -/* Private functions ---------------------------------------------------------*/ - -/****************************************************************************** -* Function Name : PWM_DeInit -* Description : Deinitializes PWM peripheral registers to their default reset -* values. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void PWM_DeInit(void) -{ - /* Enters and exits the PWM peripheral to and from reset */ - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_PWM,ENABLE); - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_PWM,DISABLE); -} - -/******************************************************************************* -* Function Name : PWM_Init -* Description : Initializes the PWM peripheral according to the specified -* parameters in the PWM_InitStruct . -* Input : PWM_InitStruct: pointer to a PWM_InitTypeDef structure that -* contains the configuration information for the PWM peripheral. -* Output : None -* Return : None -*******************************************************************************/ -void PWM_Init(PWM_InitTypeDef* PWM_InitStruct) -{ - /* Sets the prescaler value */ - PWM->PSC = PWM_InitStruct->PWM_Prescaler; - - /* Selects the counter mode */ - PWM->CR &= PWM_CounterMode_Mask; - PWM->CR |= PWM_InitStruct->PWM_CounterMode; - - /* Sets the period value */ - PWM->ARR = PWM_InitStruct->PWM_Period; - - /* Sets the repetition counter */ - PWM->RCR &= PWM_RepetitionCounter_Reset_Mask; - PWM->RCR |= PWM_InitStruct->PWM_RepetitionCounter; - - /* Configures the PWM according to the PWM_InitTypeDef structure parameters */ - OCM_ModuleConfig(PWM_InitStruct); -} - -/******************************************************************************* -* Function Name : PWM_StructInit -* Description : Fills each PWM_InitStruct member with its default value. -* Input : PWM_InitStruct : pointer to a PWM_InitTypeDef structure which -* will be initialized. -* Output : None -* Return : None. -*******************************************************************************/ -void PWM_StructInit(PWM_InitTypeDef *PWM_InitStruct) -{ - /* Sets the default configuration */ - PWM_InitStruct->PWM_Mode = PWM_Mode_OCTiming; - PWM_InitStruct->PWM_Prescaler = PWM_Prescaler_Reset_Mask; - PWM_InitStruct->PWM_CounterMode = PWM_CounterMode_Up; - PWM_InitStruct->PWM_Period = PWM_Period_Reset_Mask; - PWM_InitStruct->PWM_Complementary = PWM_Complementary_Disable; - PWM_InitStruct->PWM_OCState = PWM_OCState_Disable; - PWM_InitStruct->PWM_OCNState = PWM_OCNState_Disable; - PWM_InitStruct->PWM_Channel = PWM_Channel_1; - PWM_InitStruct->PWM_Pulse1 = PWM_Pulse1_Reset_Mask; - PWM_InitStruct->PWM_Pulse2 = PWM_Pulse2_Reset_Mask; - PWM_InitStruct->PWM_Pulse3 = PWM_Pulse3_Reset_Mask; - PWM_InitStruct->PWM_Polarity1 = PWM_Polarity1_High; - PWM_InitStruct->PWM_Polarity2 = PWM_Polarity2_High; - PWM_InitStruct->PWM_Polarity3 = PWM_Polarity3_High; - PWM_InitStruct->PWM_Polarity1N = PWM_Polarity1N_High; - PWM_InitStruct->PWM_Polarity2N = PWM_Polarity2N_High; - PWM_InitStruct->PWM_Polarity3N = PWM_Polarity3N_High; - PWM_InitStruct->PWM_DTRAccess = PWM_DTRAccess_Disable; - PWM_InitStruct->PWM_DeadTime = PWM_DeadTime_Reset_Mask; - PWM_InitStruct->PWM_Emergency = PWM_Emergency_Disable; - PWM_InitStruct->PWM_LOCKLevel = PWM_LOCKLevel_OFF; - PWM_InitStruct->PWM_OSSIState = PWM_OSSIState_Disable; - PWM_InitStruct->PWM_RepetitionCounter = PWM_RepetitionCounter_Reset_Mask; -} - -/******************************************************************************* -* Function Name : PWM_Cmd -* Description : Enables or disables the PWM peripheral. -* Input : Newstate: new state of the PWM peripheral. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void PWM_Cmd(FunctionalState Newstate) -{ - if(Newstate == ENABLE) - { - PWM->CR |= PWM_COUNTER_Start; - } - else - { - PWM->CR &= PWM_COUNTER_Stop; - } -} - -/******************************************************************************* -* Function Name : PWM_CtrlPWMOutputs -* Description : Enables or disables PWM peripheral Main Outputs. -* Input : Newstate: new state of the PWM peripheral Main Outputs. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void PWM_CtrlPWMOutputs(FunctionalState Newstate) -{ - if(Newstate == ENABLE) - { - PWM->DTR |= PWM_MOE_Set; - } - else - { - PWM->DTR &= PWM_MOE_Reset; - } -} - -/******************************************************************************* -* Function Name : PWM_ITConfig -* Description : Enables or disables the PWM interrupts. -* Input : - PWM_IT: specifies the PWM interrupts sources to be enabled -* or disabled. -* This parameter can be any combination of the following values: -* - PWM_IT_OC1: PWM Output Compare 1 Interrupt source -* - PWM_IT_OC2: PWM Output Compare 2 Interrupt source -* - PWM_IT_OC3: PWM Output Compare 3 Interrupt source -* - PWM_IT_Update: PWM update Interrupt source -* - PWM_IT_Emergency: PWM Emergency interrupt source -* - PWM_IT_GlobalUpdate: PWM global update Interrupt -* source -* - Newstate: new state of PWM interrupts. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void PWM_ITConfig(u16 PWM_IT, FunctionalState Newstate) -{ - u16 PWM_IT_Enable = 0; - - PWM_IT_Enable = PWM_IT & PWM_IT_Enable_Mask; - - if(Newstate == ENABLE) - { - /* Update interrupt global source: overflow/undeflow, counter reset operation - or slave mode controller in reset mode */ - if ((PWM_IT & PWM_IT_GlobalUpdate) == PWM_IT_GlobalUpdate) - { - PWM->CR &= PWM_UFS_Reset; - } - /* Update interrupt source: counter overflow/underflow */ - else if ((PWM_IT & PWM_IT_Update) == PWM_IT_Update) - { - PWM->CR |= PWM_UFS_Set; - } - /* Select and enable the interrupts requests */ - PWM->RSR |= PWM_IT_Enable; - PWM->RER |= PWM_IT_Enable; - } - /* Disable the interrupts requests */ - else - { - PWM->RSR &= ~PWM_IT_Enable; - PWM->RER &= ~PWM_IT_Enable; - } -} - -/******************************************************************************* -* Function Name : PWM_DMAConfig -* Description : Configures the PWM’s DMA interface. -* Input : - PWM_DMASources: specifies the DMA Request sources. -* This parameter can be any combination of the following values: -* - PWM_DMASource_OC1: PWM Output Compare 1 DMA source -* - PWM_DMASource_OC2: PWM Output Compare 2 DMA source -* - PWM_DMASource_OC3: PWM Output Compare 3 DMA source -* - PWM_DMASource_Update: PWM Update DMA source -* - PWM_OCRMState: the state of output compare request mode. -* This parameter can be one of the following values: -* - PWM_OCRMState_Enable -* - PWM_OCRMState_Disable -* - PWM_DMABase:DMA Base address. -* This parameter can be one of the following values: -* PWM_DMABase_CR, PWM_DMABase_SCR, PWM_DMABase_OMR1, -* PWM_DMABase_OMR2, PWM_DMABase_RSR, PWM_DMABase_RER, -* PWM_DMABase_ISR, PWM_DMABase_CNT, PWM_DMABase_PSC, -* PWM_DMABase_RCR, PWM_DMABase_ARR, PWM_DMABase_OCR1, -* PWM_DMABase_OCR2, PWM_DMABase_OCR3 ,PWM_DMABase_DTR. -* Output : None -* Return : None -*******************************************************************************/ -void PWM_DMAConfig(u16 PWM_DMASources, u16 PWM_OCRMState, u16 PWM_DMABase) -{ - /* Select the DMA requests */ - PWM->RSR &= ~PWM_DMASources; - - /* Sets the OCRM state */ - if(PWM_OCRMState == PWM_OCRMState_Enable) - { - PWM->RSR |= PWM_OCMR_Set; - } - else - { - PWM->RSR &= PWM_OCMR_Reset; - } - - /* Sets the DMA Base address */ - PWM->CR &= PWM_DBASE_Mask; - PWM->CR |= PWM_DMABase; -} - -/******************************************************************************* -* Function Name : PWM_DMACmd -* Description : Enables or disables the PWM’s DMA interface. -* Input : - PWM_DMASources: specifies the DMA Request sources. -* This parameter can be any combination of the following values: -* - PWM_DMASource_OC1: PWM Output Compare 1 DMA source -* - PWM_DMASource_OC2: PWM Output Compare 2 DMA source -* - PWM_DMASource_OC3: PWM Output Compare 3 DMA source -* - PWM_DMASource_Update: PWM Update DMA source -* - Newstate: new state of the DMA Request sources. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void PWM_DMACmd(u16 PWM_DMASources, FunctionalState Newstate) -{ - if(Newstate == ENABLE) - { - PWM->RER |= PWM_DMASources; - } - else - { - PWM->RER &= ~PWM_DMASources; - } -} - -/******************************************************************************* -* Function Name : PWM_SetPrescaler -* Description : Sets the PWM prescaler value. -* Input : Prescaler: PWM prescaler new value. -* Output : None -* Return : None -*******************************************************************************/ -void PWM_SetPrescaler(u16 Prescaler) -{ - PWM->PSC = Prescaler; -} - -/******************************************************************************* -* Function Name : PWM_SetPeriod -* Description : Sets the PWM period value. -* Input : Period: PWM period new value. -* Output : None -* Return : None -*******************************************************************************/ -void PWM_SetPeriod(u16 Period) -{ - PWM->ARR = Period; -} - -/******************************************************************************* -* Function Name : PWM_SetPulse -* Description : Sets the PWM pulse value. -* Input : - PWM_Channel: specifies the PWM channel to be used. -* This parameter can be one of the following values: -* - PWM_Channel_1: PWM Channel 1 is used -* - PWM_Channel_2: PWM Channel 2 is used -* - PWM_Channel_3: PWM Channel 3 is used -* - PWM_Channel_ALL: PWM Channel 1, Channel 2 and 3 are used -* - Pulse: PWM pulse new value. -* Output : None -* Return : None -*******************************************************************************/ -void PWM_SetPulse(u16 PWM_Channel, u16 Pulse) -{ - /* Sets Channel 1 pulse value */ - if(PWM_Channel == PWM_Channel_1) - { - PWM->OCR1 = Pulse; - } - /* Sets Channel 2 pulse value */ - else if(PWM_Channel == PWM_Channel_2) - { - PWM->OCR2 = Pulse; - } - /* Sets Channel 3 pulse value */ - else if(PWM_Channel == PWM_Channel_3) - { - PWM->OCR3 = Pulse; - } - /* Sets Channel 1, Channel 2 and Channel 3 pulse values */ - else if(PWM_Channel == PWM_Channel_ALL) - { - PWM->OCR1 = Pulse; - PWM->OCR2 = Pulse; - PWM->OCR3 = Pulse; - } -} - -/******************************************************************************* -* Function Name : PWM_SetPulse1 -* Description : Sets the PWM Channel 1 pulse value. -* Input : - Pulse: PWM Channel 1 pulse new value. -* Output : None -* Return : None -*******************************************************************************/ -void PWM_SetPulse1(u16 Pulse) -{ - PWM->OCR1 = Pulse; -} - -/******************************************************************************* -* Function Name : PWM_SetPulse2 -* Description : Sets the PWM Channel 2 pulse value. -* Input : - Pulse: PWM Channel 2 pulse new value. -* Output : None -* Return : None -*******************************************************************************/ -void PWM_SetPulse2(u16 Pulse) -{ - PWM->OCR2 = Pulse; -} - -/******************************************************************************* -* Function Name : PWM_SetPulse3 -* Description : Sets the PWM Channel 3 pulse value. -* Input : - Pulse: PWM Channel 3 pulse new value. -* Output : None -* Return : None -*******************************************************************************/ -void PWM_SetPulse3(u16 Pulse) -{ - PWM->OCR3 = Pulse; -} - -/******************************************************************************* -* Function Name : PWM_DebugCmd -* Description : Enables or disables PWM peripheral Debug control. -* Input : Newstate: new state of the PWM Debug control. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void PWM_DebugCmd(FunctionalState Newstate) -{ - if(Newstate == ENABLE) - { - PWM->CR |= PWM_DBGC_Set; - } - else - { - PWM->CR &= PWM_DBGC_Reset; - } -} - -/******************************************************************************* -* Function Name : PWM_CounterModeConfig -* Description : Specifies the Counter Mode to be used. -* Input : PWM_CounterMode: specifies the Counter Mode to be used -* This parameter can be one of the following values: -* - PWM_CounterMode_Up: PWM Up Counting Mode -* - PWM_CounterMode_Down: PWM Down Counting Mode -* - PWM_CounterMode_CenterAligned1: PWM Center Aligned1 Mode -* - PWM_CounterMode_CenterAligned2: PWM Center Aligned2 Mode -* - PWM_CounterMode_CenterAligned3: PWM Center Aligned3 Mode -* Output : None -* Return : None -*******************************************************************************/ -void PWM_CounterModeConfig(u16 PWM_CounterMode) -{ - /* Counter mode configuration */ - PWM->CR &= PWM_CounterMode_Mask; - PWM->CR |= PWM_CounterMode; -} - -/******************************************************************************* -* Function Name : PWM_ForcedOCConfig -* Description : Forces the PWM output waveform to active or inactive level. -* Input : - PWM_Channel: specifies the PWM channel to be used. -* This parameter can be one of the following values: -* - PWM_Channel_1: PWM Channel 1 is used -* - PWM_Channel_2: PWM Channel 2 is used -* - PWM_Channel_3: PWM Channel 3 is used -* - PWM_Channel_ALL: PWM Channel 1, Channel 2 and 3 are used -* - PWM_ForcedAction: specifies the forced Action to be set to the -* output waveform. -* This parameter can be one of the following values: -* - PWM_ForcedAction_Active: Force active level on OCxREF -* - PWM_ForcedAction_InActive: Force inactive level on -* OCxREF -* Output : None -* Return : None -*******************************************************************************/ -void PWM_ForcedOCConfig(u16 PWM_Channel, u16 PWM_ForcedAction) -{ - /* Channel 1 Forced Output Compare mode configuration */ - if(PWM_Channel == PWM_Channel_1) - { - PWM->OMR1 &= PWM_OC1C_Mask; - PWM->OMR1 |= PWM_ForcedAction; - } - /* Channel 2 Forced Output Compare mode configuration */ - else - { - if(PWM_Channel == PWM_Channel_2) - { - PWM->OMR1 &= PWM_OC2C_Mask; - PWM->OMR1 |= (PWM_ForcedAction<<8); - } - else - { - /* Channel 3 Forced Output Compare mode configuration */ - if(PWM_Channel == PWM_Channel_3) - { - PWM->OMR2 &= PWM_OC3C_Mask; - PWM->OMR2 |= PWM_ForcedAction; - } - /* Channel 1, Channel 2 and Channel 3 Forced Output Compare mode - configuration */ - else - { - PWM->OMR1 &= PWM_OC1C_Mask; - PWM->OMR1 |= PWM_ForcedAction; - - PWM->OMR1 &= PWM_OC2C_Mask; - PWM->OMR1 |= (PWM_ForcedAction<<8); - - PWM->OMR2 &= PWM_OC3C_Mask; - PWM->OMR2 |= PWM_ForcedAction; - } - } - } -} - -/******************************************************************************* -* Function Name : PWM_SetDeadTime -* Description : Inserts dead time between the OCx and OCNx. -* Input : DeadTime: PWM Dead Time value. -* Output : None -* Return : None -*******************************************************************************/ -void PWM_SetDeadTime(u16 DeadTime) -{ - /* Sets the dead time value */ - PWM->DTR &= PWM_DTR_Mask; - PWM->DTR |= DeadTime; -} - -/******************************************************************************* -* Function Name : PWM_ResetCounter -* Description : Re-intializes the PWM counter and generates an update of the -* registers. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void PWM_ResetCounter(void) -{ - /* Resets the PWM counter */ - PWM->CR |= PWM_COUNTER_Reset; -} - -/******************************************************************************* -* Function Name : PWM_TRGOSelection -* Description : Sets the PWM Master Mode selection bits. -* Input : PWM_TRGOMode: specifies the TRGO source. -* This parameter can be one of the following values: -* - PWM_TRGOMode_Enable: The CNT_EN bit is used as TRGO -* - PWM_TRGOMode_Update: The Update event is used as TRGO -* - PWM_TRGOMode_Reset: The CNT_RST bit is used as TRGO -* - PWM_TRGOMode_OC: The OC1 signal is used as TRGO -* Output : None -* Return : None -*******************************************************************************/ -void PWM_TRGOSelection(u16 PWM_TRGOMode) -{ - /* Sets the synchronization action */ - PWM->CR &= PWM_MasterModeSelection_Mask; - PWM->CR |= PWM_TRGOMode; -} - -/******************************************************************************* -* Function Name : PWM_GetFlagStatus -* Description : Checks whether the specified PWM flag is set or not. -* Input : PWM_FLAG: specifies the flag to check. -* This parameter can be one of the following values: -* - PWM_FLAG_OC1: Output Compare 1 Flag -* - PWM_FLAG_OC2: Output Compare 2 Flag -* - PWM_FLAG_OC3: Output Compare 3 Flag -* - PWM_FLAG_Update: PWM update Flag -* - PWM_FLAG_Emergency: PWM Emergency Flag -* Output : None -* Return : The new state of the PWM_FLAG(SET or RESET). -*******************************************************************************/ -FlagStatus PWM_GetFlagStatus(u16 PWM_FLAG) -{ - if((PWM->ISR & PWM_FLAG) != RESET ) - { - return SET; - } - else - { - return RESET; - } -} - -/******************************************************************************* -* Function Name : PWM_ClearFlag -* Description : Clears the PWM’s pending flags. -* Input : PWM_FLAG: specifies the flag to clear. -* This parameter can be any combination of the following values: -* - PWM_FLAG_OC1: Output Compare 1 flag -* - PWM_FLAG_OC2: Output Compare 2 flag -* - PWM_FLAG_OC3: Output Compare 3 flag -* - PWM_FLAG_Update: PWM update flag -* - PWM_FLAG_Emergency: PWM Emergency flag -* Output : None -* Return : None -*******************************************************************************/ -void PWM_ClearFlag(u16 PWM_FLAG) -{ - /* Clears the flags */ - PWM->ISR &= ~PWM_FLAG; -} - -/******************************************************************************* -* Function Name : PWM_GetITStatus -* Description : Checks whether the PWM interrupt has occurred or not. -* Input : PWM_IT: specifies the PWM interrupt source to check. -* This parameter can be one of the following values: -* - PWM_IT_OC1: PWM Output Compare 1 Interrupt source -* - PWM_IT_OC2: PWM Output Compare 2 Interrupt source -* - PWM_IT_OC3: PWM Output Compare 3 Interrupt source -* - PWM_IT_Update: PWM update Interrupt source -* - PWM_IT_Emergency: PWM Emergency interrupt source -* - PWM_IT_GlobalUpdate: PWM global update Interrupt -* source -* Output : None -* Return : The new state of the PWM_IT(SET or RESET). -*******************************************************************************/ -ITStatus PWM_GetITStatus(u16 PWM_IT) -{ - u16 PWM_IT_Check = 0; - - /* Calculates the pending bits to be checked */ - PWM_IT_Check = PWM_IT & PWM_IT_Clear_Mask; - - if((PWM->ISR & PWM_IT_Check) != RESET ) - { - return SET; - } - else - { - return RESET; - } -} - -/******************************************************************************* -* Function Name : PWM_ClearITPendingBit -* Description : Clears the PWM's interrupt pending bits. -* Input : PWM_IT: specifies the pending bit to clear. -* This parameter can be any combination of the following values: -* - PWM_IT_OC1: PWM Output Compare 1 Interrupt source -* - PWM_IT_OC2: PWM Output Compare 2 Interrupt source -* - PWM_IT_OC3: PWM Output Compare 3 Interrupt source -* - PWM_IT_Update: PWM update Interrupt source -* - PWM_IT_Emergency: PWM Emergency interrupt source -* - PWM_IT_GlobalUpdate: PWM global update Interrupt -* source -* Output : None -* Return : None -*******************************************************************************/ -void PWM_ClearITPendingBit(u16 PWM_IT) -{ - u16 PWM_IT_Clear = 0; - - /* Calculates the pending bits to be cleared */ - PWM_IT_Clear = PWM_IT & PWM_IT_Clear_Mask; - - /* Clears the pending bits */ - PWM->ISR &= ~PWM_IT_Clear; - -} - -/******************************************************************************* -* Function Name : OCM_ModuleConfig -* Description : Output Compare Module configuration. -* Input : PWM_InitStruct: pointer to a PWM_InitTypeDef structure that -* contains the configuration information for the PWM peripheral. -* Output : None -* Return : None -*******************************************************************************/ -static void OCM_ModuleConfig(PWM_InitTypeDef* PWM_InitStruct) -{ - u16 PWM_OCControl = 0x0000; - u16 DTR_REG = 0x0000; - - if(PWM_InitStruct->PWM_Mode == PWM_Mode_OCTiming) - { - PWM_OCControl = PWM_OCControl_OCTiming; - } - else - { - if(PWM_InitStruct->PWM_Mode == PWM_Mode_OCActive) - { - PWM_OCControl = PWM_OCControl_OCActive; - } - else - { - if(PWM_InitStruct->PWM_Mode == PWM_Mode_OCInactive) - { - PWM_OCControl = PWM_OCControl_OCInactive; - } - else - { - if(PWM_InitStruct->PWM_Mode == PWM_Mode_OCToggle) - { - PWM_OCControl = PWM_OCControl_OCToggle; - } - else - { - PWM_OCControl = PWM_OCControl_PWM; - - } - } - } - } - - /* Read DTR register */ - DTR_REG = PWM->DTR & 0x8000; - -/*Channel 1 Configuration-----------------------------------------------------*/ - if(PWM_InitStruct->PWM_Channel == PWM_Channel_1) - { - /* PWM Output Complementary Configuration */ - if(PWM_InitStruct->PWM_Complementary == PWM_Complementary_Enable) - { - /* Configures Channel 1 on Output Compare mode */ - PWM->OMR1 &= PWM_OC1C_Mask; - PWM->OMR1 |= PWM_OCControl|PWM_OC1_Enable|PWM_OC1N_Enable|PWM_PLD1_Set; - PWM->OCR1 = PWM_InitStruct->PWM_Pulse1; - - /* Sets the OC1 wave polarity */ - if(PWM_InitStruct->PWM_Polarity1 == PWM_Polarity1_Low) - { - PWM->OMR1 |= PWM_OC1P_Set; - } - else - { - PWM->OMR1 &= PWM_OC1P_Reset; - } - - /* Sets the OC1N wave polarity */ - if(PWM_InitStruct->PWM_Polarity1N == PWM_Polarity1N_Low) - { - PWM->OMR1 |= PWM_OC1NP_Set; - } - else - { - PWM->OMR1 &= PWM_OC1NP_Reset; - } - }/* End complementary case */ - /* Single PWM Output configuratuion */ - else - { - switch(PWM_InitStruct->PWM_OCState) - { - case PWM_OCState_Enable: - { - /* Configures Channel 1 on Output Compare mode */ - PWM->OMR1 &= PWM_OC1C_Mask; - PWM->OMR1 |= PWM_OCControl|PWM_OC1_Enable; - PWM->OMR1 |= PWM_PLD1_Set; - PWM->OCR1 = PWM_InitStruct->PWM_Pulse1; - - /* Sets the OC1 wave polarity */ - if(PWM_InitStruct->PWM_Polarity1 == PWM_Polarity1_Low) - { - PWM->OMR1 |= PWM_OC1P_Set; - } - else - { - PWM->OMR1 &= PWM_OC1P_Reset; - } - } - break; - case PWM_OCState_Disable: - { - /* OC1E = 0 and OSSR = 0 sets the polarity */ - PWM->OMR1 &= PWM_OC1_Disable; - DTR_REG &= PWM_OSSR_Reset; - } - break; - case PWM_OCState_OffState: - { - /* OC1E = 0 and OSSR = 1 and sets the polarity */ - PWM->OMR1 &= PWM_OC1_Disable; - DTR_REG |= PWM_OSSR_Set; - - /* Sets the OC1 wave polarity */ - if(PWM_InitStruct->PWM_Polarity1 == PWM_Polarity1_Low) - { - PWM->OMR1 |= PWM_OC1P_Set; - } - else - { - PWM->OMR1 &= PWM_OC1P_Reset; - } - } - break; - } - - switch(PWM_InitStruct->PWM_OCNState) - { - case PWM_OCNState_Enable: - { - /* Configures Channel 1N on Output Compare mode */ - PWM->OMR1 &= PWM_OC1C_Mask; - PWM->OMR1 |= PWM_OCControl |PWM_OC1N_Enable |PWM_PLD1_Set; - PWM->OCR1 = PWM_InitStruct->PWM_Pulse1; - - /* Sets the OC1N wave polarity */ - if(PWM_InitStruct->PWM_Polarity1N == PWM_Polarity1N_Low) - { - PWM->OMR1 |= PWM_OC1NP_Set; - } - else - { - PWM->OMR1 &= PWM_OC1NP_Reset; - } - } - break; - case PWM_OCNState_Disable: - { - /* OC1N = 0 OSSR = 0 */ - PWM->OMR1 &= PWM_OC1N_Disable; - DTR_REG &= PWM_OSSR_Reset; - } - break; - case PWM_OCNState_OffState: - { - /* OC1N = 0 OSSR = 1 and sets the polarity */ - PWM->OMR1 &= PWM_OC1N_Disable; - DTR_REG |= PWM_OSSR_Set; - - if(PWM_InitStruct->PWM_Polarity1N == PWM_Polarity1N_Low) - { - PWM->OMR1 |= PWM_OC1NP_Set; - } - else - { - PWM->OMR1 &= PWM_OC1NP_Reset; - } - } - break; - } - } /* End not complementary case */ - }/* end channel 1 */ - -/*Channel 2 Configuration-----------------------------------------------------*/ - if(PWM_InitStruct->PWM_Channel == PWM_Channel_2) - { - /* PWM Output Complementary Configuration */ - if(PWM_InitStruct->PWM_Complementary == PWM_Complementary_Enable) - { - /* Configures Channel 2 on Output Compare mode */ - PWM->OMR1 &= PWM_OC2C_Mask; - PWM->OMR1 |= (PWM_OCControl<<8)|PWM_OC2_Enable|PWM_OC2N_Enable|PWM_PLD2_Set; - PWM->OCR2 = PWM_InitStruct->PWM_Pulse2; - - /* Set the OC2 wave polarity */ - if(PWM_InitStruct->PWM_Polarity2 == PWM_Polarity2_Low) - { - PWM->OMR1 |= PWM_OC2P_Set; - } - else - { - PWM->OMR1 &= PWM_OC2P_Reset; - } - - /* Sets the OC2N wave polarity */ - if(PWM_InitStruct->PWM_Polarity2N == PWM_Polarity2N_Low) - { - PWM->OMR1 |= PWM_OC2NP_Set; - } - else - { - PWM->OMR1 &= PWM_OC2NP_Reset; - } - - }/* End complentary case */ - else - /* Single PWM Output configuratuion */ - { - switch(PWM_InitStruct->PWM_OCState) - { - case PWM_OCState_Enable: - { - /* Configures Channel 2 on Output Compare mode */ - PWM->OMR1 &= PWM_OC2C_Mask; - PWM->OMR1 |= (PWM_OCControl<<8)|PWM_OC2_Enable|PWM_PLD2_Set; - PWM->OCR2 = PWM_InitStruct->PWM_Pulse2; - - /* Sets the OC2 wave polarity */ - if(PWM_InitStruct->PWM_Polarity2 == PWM_Polarity2_Low) - { - PWM->OMR1 |= PWM_OC2P_Set; - } - else - { - PWM->OMR1 &= PWM_OC2P_Reset; - } - } - break; - case PWM_OCState_Disable: - { - /* OC2E = 0 and OSSR = 0 */ - PWM->OMR1 &= PWM_OC2_Disable; - DTR_REG &= PWM_OSSR_Reset; - } - break; - case PWM_OCState_OffState: - { - /* OC2E = 0 and OSSR = 1 sets the polarity */ - PWM->OMR1 &= PWM_OC2_Disable; - DTR_REG |= PWM_OSSR_Set; - - /* Sets the OC2 wave polarity */ - if(PWM_InitStruct->PWM_Polarity2 == PWM_Polarity2_Low) - { - PWM->OMR1 |= PWM_OC2P_Set; - } - else - { - PWM->OMR1 &= PWM_OC2P_Reset; - } - } - break; - } - switch(PWM_InitStruct->PWM_OCNState) - { - case PWM_OCNState_Enable: - { - /* Configures Channel 2N on Output Compare mode */ - PWM->OMR1 &= PWM_OC2C_Mask; - PWM->OMR1 |= (PWM_OCControl<<8)|PWM_OC2N_Enable|PWM_PLD2_Set; - PWM->OCR2 = PWM_InitStruct->PWM_Pulse2; - - /* Sets the OC2 wave polarity */ - if(PWM_InitStruct->PWM_Polarity2N == PWM_Polarity2N_Low) - { - PWM->OMR1 |= PWM_OC2NP_Set; - } - else - { - PWM->OMR1 &= PWM_OC2NP_Reset; - } - } - break; - case PWM_OCNState_Disable: - { - /* OC2N = 0 OSSR = 0 */ - PWM->OMR1 &= PWM_OC2N_Disable; - DTR_REG &= PWM_OSSR_Reset; - } - break; - case PWM_OCNState_OffState: - { - /* OC2N = 0 OSSR = 1 and sets the polarity */ - PWM->OMR1 &= PWM_OC2N_Disable; - DTR_REG |= PWM_OSSR_Set; - - if(PWM_InitStruct->PWM_Polarity2N == PWM_Polarity2N_Low) - { - PWM->OMR1 |= PWM_OC2NP_Set; - } - else - { - PWM->OMR1 &= PWM_OC2NP_Reset; - } - } - break; - } - } /* End not complementary case */ - }/* end channel 2 */ - -/*Channel 3 Configuration-----------------------------------------------------*/ - if(PWM_InitStruct->PWM_Channel == PWM_Channel_3) - { - /* PWM Output Complementary Configuration */ - if(PWM_InitStruct->PWM_Complementary == PWM_Complementary_Enable) - { - /* Configures Channel 3 on Output Compare mode */ - PWM->OMR2 &= PWM_OC3C_Mask; - PWM->OMR2 |= PWM_OCControl|PWM_OC3_Enable|PWM_OC3N_Enable|PWM_PLD3_Set; - PWM->OCR3 = PWM_InitStruct->PWM_Pulse3; - - /* Sets the OC3 wave polarity */ - if(PWM_InitStruct->PWM_Polarity3 == PWM_Polarity3_Low) - { - PWM->OMR2 |= PWM_OC3P_Set; - } - else - { - PWM->OMR2 &= PWM_OC3P_Reset; - } - - /* Sets the OC3N wave polarity */ - if(PWM_InitStruct->PWM_Polarity3N == PWM_Polarity3N_Low) - { - PWM->OMR2 |= PWM_OC3NP_Set; - } - else - { - PWM->OMR2 &= PWM_OC3NP_Reset; - } - }/* End complementary case */ - else - /* Single PWM Output configuratuion */ - { - switch(PWM_InitStruct->PWM_OCState) - { - case PWM_OCState_Enable: - { - /* Configures Channel 3 on Output Compare mode */ - PWM->OMR2 &= PWM_OC3C_Mask; - PWM->OMR2 |= PWM_OCControl|PWM_OC3_Enable|PWM_PLD3_Set; - PWM->OCR3 = PWM_InitStruct->PWM_Pulse3; - - /* Sets the OCC wave polarity */ - if(PWM_InitStruct->PWM_Polarity3 == PWM_Polarity3_Low) - { - PWM->OMR2 |= PWM_OC3P_Set; - } - else - { - PWM->OMR2 &= PWM_OC3P_Reset; - } - } - break; - case PWM_OCState_Disable: - { - /* OC3E = 0 and OSSR = 0 */ - PWM->OMR2 &= PWM_OC3_Disable; - DTR_REG &= PWM_OSSR_Reset; - } - break; - case PWM_OCState_OffState: - { - /* OC3E = 0 and OSSR = 1 sets the polarity */ - PWM->OMR2 &= PWM_OC3_Disable; - DTR_REG |= PWM_OSSR_Set; - - if(PWM_InitStruct->PWM_Polarity3 == PWM_Polarity3_Low) - { - PWM->OMR2 |= PWM_OC3P_Set; - } - else - { - PWM->OMR2 &= PWM_OC3P_Reset; - } - } - break; - } - - switch(PWM_InitStruct->PWM_OCNState) - { - case PWM_OCNState_Enable: - { - /* Configures Channel 3N on Output Compare mode */ - PWM->OMR2 &= PWM_OC3C_Mask; - PWM->OMR2 |= PWM_OCControl |PWM_OC3N_Enable|PWM_PLD3_Set; - PWM->OCR3 = PWM_InitStruct->PWM_Pulse3; - - /* Sets the OC3 wave polarity */ - if(PWM_InitStruct->PWM_Polarity3N == PWM_Polarity3N_Low) - { - PWM->OMR2 |= PWM_OC3NP_Set; - } - else - { - PWM->OMR2 &= PWM_OC3NP_Reset; - } - } - break; - case PWM_OCNState_Disable: - { - /* OC3N = 0 OSSR = 0 */ - PWM->OMR2 &= PWM_OC3N_Disable; - DTR_REG &= PWM_OSSR_Reset; - } - break; - case PWM_OCNState_OffState: - { - /* OC3N = 0 OSSR = 1 and sets the polarity */ - PWM->OMR2 &= PWM_OC3N_Disable; - DTR_REG |= PWM_OSSR_Set; - - if(PWM_InitStruct->PWM_Polarity3N == PWM_Polarity3N_Low) - { - PWM->OMR2 |= PWM_OC3NP_Set; - } - else - { - PWM->OMR2 &= PWM_OC3NP_Reset; - } - } - break; - } - } /* End not complementary case */ - }/* end channel 3 */ - - if(PWM_InitStruct->PWM_DTRAccess == PWM_DTRAccess_Enable) - { - DTR_REG |= PWM_InitStruct->PWM_LOCKLevel | PWM_InitStruct->PWM_Emergency | - PWM_InitStruct->PWM_DeadTime | PWM_InitStruct->PWM_OSSIState; - PWM->DTR = DTR_REG; - } -} -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_rtc.c b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_rtc.c deleted file mode 100644 index ab6da500b..000000000 --- a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_rtc.c +++ /dev/null @@ -1,326 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_rtc.c -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file provides all the RTC software functions. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -#include "75x_rtc.h" -#include "75x_mrcc.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define RTC_CNF_Enable_Mask 0x0010 /* Configuration Flag Enable Mask */ -#define RTC_CNF_Disable_Mask 0xFFEF /* Configuration Flag Disable Mask */ -#define RTC_LSB_Mask 0x0000FFFF /* RTC LSB Mask */ -#define RTC_MSB_Mask 0xFFFF0000 /* RTC MSB Mask */ -#define RTC_Prescaler_MSB_Mask 0x000F0000 /* RTC Prescaler MSB Mask */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/******************************************************************************* -* Function Name : RTC_DeInit -* Description : Deinitializes the RTC peripheral registers to their -* default reset values. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void RTC_DeInit(void) -{ - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_RTC,ENABLE); - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_RTC,DISABLE); -} - -/******************************************************************************* -* Function Name : RTC_ITConfig -* Description : Enables or disables the specified RTC interrupts. -* Input : - RTC_IT: specifies the RTC interrupts sources to be enabled -* or disabled. -* This parameter can be a combination of one or more of the -* following values: -* - RTC_IT_Overflow: Overflow interrupt -* - RTC_IT_Alarm: Alarm interrupt -* - RTC_IT_Second: Second interrupt -* - NewState: new state of the specified RTC interrupts. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void RTC_ITConfig(u16 RTC_IT, FunctionalState NewState) -{ - if(NewState == ENABLE) - { - RTC->CRH |= RTC_IT; - } - else - { - RTC->CRH &= ~RTC_IT; - } -} - -/******************************************************************************* -* Function Name : RTC_EnterConfigMode -* Description : Enters the RTC configuration mode. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void RTC_EnterConfigMode(void) -{ - /* Set the CNF flag to enter in the Configuration Mode */ - RTC->CRL |= RTC_CNF_Enable_Mask; -} - -/******************************************************************************* -* Function Name : RTC_ExitConfigMode -* Description : Exits from the RTC configuration mode. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void RTC_ExitConfigMode(void) -{ - /* Reset the CNF flag to exit from the Configuration Mode */ - RTC->CRL &= RTC_CNF_Disable_Mask; -} - -/******************************************************************************* -* Function Name : RTC_GetCounter -* Description : Gets the RTC counter value. -* Input : None -* Output : None -* Return : RTC counter value. -*******************************************************************************/ -u32 RTC_GetCounter(void) -{ - u16 Tmp = 0; - Tmp = RTC->CNTL; - - return (((u32)RTC->CNTH << 16 ) |Tmp) ; -} - -/******************************************************************************* -* Function Name : RTC_SetCounter -* Description : Sets the RTC counter value. -* Input : RTC counter new value. -* Output : None -* Return : None -*******************************************************************************/ -void RTC_SetCounter(u32 CounterValue) -{ - RTC_EnterConfigMode(); - -/* COUNTER Config ------------------------------------------------------------*/ - /* Set RTC COUNTER MSB word */ - RTC->CNTH =(CounterValue & RTC_MSB_Mask) >> 16; - /* Set RTC COUNTER LSB word */ - RTC->CNTL =(CounterValue & RTC_LSB_Mask); - - RTC_ExitConfigMode(); -} - -/******************************************************************************* -* Function Name : RTC_SetPrescaler -* Description : Sets the RTC prescaler value. -* Input : RTC prescaler new value. -* Output : None -* Return : None -*******************************************************************************/ -void RTC_SetPrescaler(u32 PrescalerValue) -{ - RTC_EnterConfigMode(); - -/* PRESCALER Config ----------------------------------------------------------*/ - /* Set RTC PRESCALER MSB word */ - RTC->PRLH = (PrescalerValue & RTC_Prescaler_MSB_Mask) >> 16; - /* Set RTC PRESCALER LSB word */ - RTC->PRLL = (PrescalerValue & RTC_LSB_Mask); - - RTC_ExitConfigMode(); -} - -/******************************************************************************* -* Function Name : RTC_GetPrescaler -* Description : Gets the RTC prescaler value. -* Input : None -* Output : None -* Return : RTC prescaler value. -*******************************************************************************/ -u32 RTC_GetPrescaler(void) -{ - u16 Tmp = 0; - Tmp = RTC->PRLL; - - return (((u32)(RTC->PRLH & 0x000F) << 16 ) | Tmp); -} - -/******************************************************************************* -* Function Name : RTC_SetAlarm -* Description : Sets the RTC alarm value. -* Input : RTC alarm new value. -* Output : None -* Return : None -*******************************************************************************/ -void RTC_SetAlarm(u32 AlarmValue) -{ - RTC_EnterConfigMode(); - -/* ALARM Config --------------------------------------------------------------*/ - /* Set the ALARM MSB word */ - RTC->ALRH = (AlarmValue & RTC_MSB_Mask) >> 16; - /* Set the ALARM LSB word */ - RTC->ALRL = (AlarmValue & RTC_LSB_Mask); - - RTC_ExitConfigMode(); -} - -/******************************************************************************* -* Function Name : RTC_GetDivider -* Description : Gets the RTC divider value. -* Input : None -* Output : None -* Return : RTC Divider value. -*******************************************************************************/ -u32 RTC_GetDivider(void) -{ - u16 Tmp = 0; - Tmp = RTC->DIVL ; - return (((u32)(RTC->DIVH & 0x000F) << 16 ) | Tmp); -} - -/******************************************************************************* -* Function Name : RTC_WaitForLastTask -* Description : Waits until last write operation on RTC registers has finished. -* This function must be called before any write to RTC registers. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void RTC_WaitForLastTask(void) -{ - /* Loop until RTOFF flag is set */ - while ((RTC->CRL & RTC_FLAG_RTOFF) == RESET); -} - -/******************************************************************************* -* Function Name : RTC_WaitForSynchro -* Description : Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL) -* are synchronized with RTC APB clock. -* This function must be called before any read operation after -* an APB reset or an APB clock stop. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void RTC_WaitForSynchro(void) -{ - /* Clear RSF flag */ - RTC->CRL &= ~RTC_FLAG_RSF; - - /* Loop until RSF flag is set */ - while((RTC->CRL & RTC_FLAG_RSF)== RESET); -} - -/******************************************************************************* -* Function Name : RTC_GetFlagStatus -* Description : Checks whether the specified RTC flag is set or not. -* Input : RTC_FLAG: specifies the flag to check. -* This parameter can be one the following values: -* - RTC_FLAG_RTOFF: RTC Operation OFF flag -* - RTC_FLAG_RSF: Registers Synchronized flag -* - RTC_FLAG_Overflow: Overflow interrupt flag -* - RTC_FLAG_Alarm: Alarm interrupt flag -* - RTC_FLAG_Second: Second interrupt flag -* Output : None -* Return : The new state of RTC_FLAG (SET or RESET). -*******************************************************************************/ -FlagStatus RTC_GetFlagStatus(u16 RTC_FLAG) -{ - if((RTC->CRL & RTC_FLAG) != RESET) - { - return SET; - } - else - { - return RESET; - } -} - -/******************************************************************************* -* Function Name : RTC_ClearFlag -* Description : Clears the RTC’s pending flags. -* Input : RTC_FLAG: specifies the flag to clear. -* This parameter can be a combination of one or more of -* the following values: -* - RTC_FLAG_RSF: Registers Synchronized flag. This flag -* is cleared only after an APB reset or an APB Clock stop. -* - RTC_FLAG_Overflow: Overflow interrupt flag -* - RTC_FLAG_Alarm: Alarm interrupt flag -* - RTC_FLAG_Second: Second interrupt flag -* Output : None -* Return : None -*******************************************************************************/ -void RTC_ClearFlag(u16 RTC_FLAG) -{ - /* Clear the coressponding RTC flag */ - RTC->CRL &= ~RTC_FLAG; -} - -/******************************************************************************* -* Function Name : RTC_GetITStatus -* Description : Checks whether the specified RTC interrupt has occured or not. -* Input : RTC_IT: specifies the RTC interrupts sources to check. -* This parameter can be a combination of one or more of -* the following values: -* - RTC_IT_Overflow: Overflow interrupt -* - RTC_IT_Alarm: Alarm interrupt -* - RTC_IT_Second: Second interrupt -* Output : None -* Return : The new state of the RTC_IT (SET or RESET). -*******************************************************************************/ -ITStatus RTC_GetITStatus(u16 RTC_IT) -{ - if(((RTC->CRH & RTC_IT) != RESET)&& ((RTC->CRL & RTC_IT) != RESET)) - { - return SET; - } - else - { - return RESET; - } -} - -/******************************************************************************* -* Function Name : RTC_ClearITPendingBit -* Description : Clears the RTC’s interrupt pending bits. -* Input : RTC_IT: specifies the interrupt pending bit to clear. -* This parameter can be any combination of one or more of -* the following values: -* - RTC_IT_Overflow: Overflow interrupt -* - RTC_IT_Alarm: Alarm interrupt -* - RTC_IT_Second: Second interrupt -* Output : None -* Return : None -*******************************************************************************/ -void RTC_ClearITPendingBit(u16 RTC_IT) -{ - /* Clear the coressponding RTC pending bit */ - RTC->CRL &= ~RTC_IT; -} - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_smi.c b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_smi.c deleted file mode 100644 index 9af53a9e8..000000000 --- a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_smi.c +++ /dev/null @@ -1,551 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_smi.c -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file provides all the SMI software functions. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -#include "75x_smi.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* SMI_CR1 mask bits */ -#define SMI_HOLDPRESCTCS_RESET_Mask 0xFF00800F -#define SMI_Prescaler_MaxValue 0x7F -#define SMI_DeselectTime_MaxValue 0x0F -#define SMI_ClockHold_Mask 0x00 -#define SMI_Prescaler_Mask 0x02 -#define SMI_DeselectTime_Mask 0x5 - -/* SMI_CR2 mask bits */ -#define SMI_BS_RESET_Mask 0xFFFFCFFF -#define SMI_BS_Bank1_Mask 0x00001000 -#define SMI_BS_Bank2_Mask 0x00002000 -#define SMI_BS_Bank3_Mask 0x00003000 -#define SMI_WEN_Mask 0x00000800 -#define SMI_RSR_Mask 0x00000400 -#define SMI_SEND_Mask 0x00000080 -#define SMI_TRARECLENGTH_RESET_Mask 0xFFFFFF88 - -/* SMI_SR mask bits */ -#define SMI_STATUSREGISTER_Mask 0xFF - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/******************************************************************************* -* Function Name : SMI_DeInit -* Description : Deinitializes the SMI peripheral registers to their default -* reset values. This function must not be used when booting -* from the SMI external memory. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void SMI_DeInit(void) -{ - SMI->CR1 = 0x00000250; - SMI->CR2 = 0x00; - SMI->SR &= 0xFFFFF0FF; - SMI->TR = 0x00; -} - -/******************************************************************************* -* Function Name : SMI_Init -* Description : Initializes the SMI peripheral according to the specified -* parameters in the SMI_InitStruct. -* Input : - SMI_InitStruct: pointer to a SMI_InitTypeDef structure that -* contains the configuration information for the specified -* SMI peripheral. -* Output : None -* Return : None -*******************************************************************************/ -void SMI_Init(SMI_InitTypeDef* SMI_InitStruct) -{ - u32 Temp = 0; - - /* Clear HOLD[7:0], PRESC[6:0] and TCS[3:0] bits */ - Temp = SMI->CR1 & SMI_HOLDPRESCTCS_RESET_Mask; - - /* Set HOLD[7:0] bits according to SMI_ClockHold value */ - Temp |= SMI_InitStruct->SMI_ClockHold << 16; - - if(SMI_InitStruct->SMI_Prescaler <= SMI_Prescaler_MaxValue) - { - /* Set PRESC[6:0] bits according to SMI_Prescaler value */ - Temp |= SMI_InitStruct->SMI_Prescaler << 8; - } - - if(SMI_InitStruct->SMI_DeselectTime <= SMI_DeselectTime_MaxValue) - { - /* Set TCS[3:0] bits according to SMI_DeselectTime value */ - Temp |= SMI_InitStruct->SMI_DeselectTime << 4; - } - - /* Store the new value */ - SMI->CR1 = Temp; -} - -/******************************************************************************* -* Function Name : SMI_StructInit -* Description : Fills each SMI_InitStruct member with its reset value. -* Input : - SMI_InitStruct: pointer to a SMI_InitTypeDef structure which -* will be initialized. -* Output : None -* Return : None -*******************************************************************************/ -void SMI_StructInit(SMI_InitTypeDef* SMI_InitStruct) -{ - /* SMI_CK is sent continuously */ - SMI_InitStruct->SMI_ClockHold = SMI_ClockHold_Mask; - - /* SMI_CK = HCLK/2 */ - SMI_InitStruct->SMI_Prescaler = SMI_Prescaler_Mask; - - /* Deselect Time set to 6*SMI_CK periods */ - SMI_InitStruct->SMI_DeselectTime = SMI_DeselectTime_Mask; -} - -/******************************************************************************* -* Function Name : SMI_ModeConfig -* Description : Selects the SMI mode: hardware or software. -* Input : - SMI_Mode: specifies the SMI mode. -* This parameter can be one of the following values: -* - SMI_Mode_HW: SMI in hardware mode -* - SMI_Mode_SW: SMI in software mode -* Output : None -* Return : None -*******************************************************************************/ -void SMI_ModeConfig(u32 SMI_Mode) -{ - if(SMI_Mode == SMI_Mode_SW) - { - SMI->CR1 |= SMI_Mode_SW; - } - else - { - SMI->CR1 &= SMI_Mode_HW; - } -} - -/******************************************************************************* -* Function Name : SMI_TxRxLengthConfig -* Description : Configures the number of bytes to be transmitted and received -* to/from external memory. This function is used in Software -* mode only. -* Input : - SMI_TxLength: specifies the number of bytes to be transmitted -* to external memory. -* This parameter can be one of the following values: -* - SMI_TxLength_0Bytes: No bytes transmitted -* - SMI_TxLength_1Byte: 1 byte transmitted -* - SMI_TxLength_2Bytes: 2 bytes transmitted -* - SMI_TxLength_3Bytes: 3 bytes transmitted -* - SMI_TxLength_4Bytes: 4 bytes transmitted -* - SMI_RxLength: specifies the number of bytes to be received -* from external memory. -* This parameter can be one of the following values: -* - SMI_RxLength_0Bytes: No bytes received -* - SMI_RxLength_1Byte: 1 byte received -* - SMI_RxLength_2Bytes: 2 bytes received -* - SMI_RxLength_3Bytes: 3 bytes received -* - SMI_RxLength_4Bytes: 4 bytes received -* Output : None -* Return : None -*******************************************************************************/ -void SMI_TxRxLengthConfig(u32 SMI_TxLength, u32 SMI_RxLength) -{ - u32 Temp = 0; - - /* Clear TRA_LENGTH[2:0] and REC_LENGTH[2:0] bits */ - Temp = SMI->CR2 & SMI_TRARECLENGTH_RESET_Mask; - - /* Set TRA_LENGTH[2:0] and REC_LENGTH[2:0] bits according to function parameters */ - Temp |= SMI_TxLength | SMI_RxLength; - - /* Store the new value */ - SMI->CR2 = Temp; -} - -/******************************************************************************* -* Function Name : SMI_BankCmd -* Description : Enables or disables the specified memory Bank. -* Input : - SMI_Bank: specifies the memory Bank to be enabled or disabled. -* This parameter can be any combination of the following values: -* - SMI_Bank_0 -* - SMI_Bank_1 -* - SMI_Bank_2 -* - SMI_Bank_3 -* - NewState: new state of the specified memory Bank. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void SMI_BankCmd(u32 SMI_Bank, FunctionalState NewState) -{ - if(NewState == ENABLE) - { - SMI->CR1 |= SMI_Bank; - } - else - { - SMI->CR1 &= ~SMI_Bank; - } -} - -/******************************************************************************* -* Function Name : SMI_ITConfig -* Description : Enables or disables the specified SMI interrupts. -* Input : - SMI_IT: specifies the SMI interrupts sources to be -* enabled or disabled. This parameter can be any combination -* of the following values: -* - SMI_IT_WC : Write Complete Interrupt -* - SMI_IT_TF : Transfer Finished Interrupt -* - NewState: new state of the specified SMI interrupts. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void SMI_ITConfig(u32 SMI_IT, FunctionalState NewState) -{ - if(NewState == ENABLE) - { - SMI->CR2 |= SMI_IT; - } - else - { - SMI->CR2 &= ~SMI_IT; - } -} - -/******************************************************************************* -* Function Name : SMI_SelectBank -* Description : Selects the memory Bank to be accessed. Only one Bank can be -* selected at a time. -* Input : - SMI_Bank: specifies the memory Bank to be selected. -* This parameter can be one of the following values: -* - SMI_Bank_0 -* - SMI_Bank_1 -* - SMI_Bank_2 -* - SMI_Bank_3 -* Output : None -* Return : None -*******************************************************************************/ -void SMI_SelectBank(u32 SMI_Bank) -{ - /* Clear BS[1:0] bits (Bank0 is selected)*/ - SMI->CR2 &= SMI_BS_RESET_Mask; - - switch(SMI_Bank) - { - case SMI_Bank_1: - /* Select Bank1 */ - SMI->CR2 |= SMI_BS_Bank1_Mask; - break; - - case SMI_Bank_2: - /* Select Bank2 */ - SMI->CR2 |= SMI_BS_Bank2_Mask; - break; - - case SMI_Bank_3: - /* Select Bank3 */ - SMI->CR2 |= SMI_BS_Bank3_Mask; - break; - - default: - break; - } -} - -/******************************************************************************* -* Function Name : SMI_SendWENCmd -* Description : Sends a Write Enable command to the selected memory Bank. -* This function is used in Hardware mode only. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void SMI_SendWENCmd(void) -{ - SMI->CR2 |= SMI_WEN_Mask; -} - -/******************************************************************************* -* Function Name : SMI_SendRSRCmd -* Description : Sends a Read Status Register Command to the selected memory -* Bank. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void SMI_SendRSRCmd(void) -{ - SMI->CR2 |= SMI_RSR_Mask; -} - -/******************************************************************************* -* Function Name : SMI_SendCmd -* Description : Sends command to the selected memory Bank. This function is -* used in Software mode only. -* Input : - Command: specifies the command to send to the external memory. -* Output : None -* Return : None -*******************************************************************************/ -void SMI_SendCmd(u32 Command) -{ - /* Load the command in the Transmit Register */ - SMI->TR = Command; - - /* Start transfer */ - SMI->CR2 |= SMI_SEND_Mask; -} - -/******************************************************************************* -* Function Name : SMI_FastReadConfig -* Description : Enables or disables the Fast Read Mode. -* Input : - SMI_FastRead: specifies whether the Fast Read Mode is -* enabled or disabled. -* This parameter can be one of the following values: -* - SMI_FastRead_Disable : Fast Read Mode disabled -* - SMI_FastRead_Enable : Fast Read Mode enabled -* Output : None -* Return : None -*******************************************************************************/ -void SMI_FastReadConfig(u32 SMI_FastRead) -{ - if(SMI_FastRead == SMI_FastRead_Enable) - { - SMI->CR1 |= SMI_FastRead_Enable; - } - else - { - SMI->CR1 &= SMI_FastRead_Disable; - } -} - -/******************************************************************************* -* Function Name : SMI_WriteBurstConfig -* Description : Enables or disables the Write Burst Mode. -* Input : - SMI_WriteBurst: specifies whether the Write Burst Mode is -* enabled or disabled. -* This parameter can be one of the following values: -* - SMI_WriteBurst_Disable : Write Burst Mode disabled -* - SMI_WriteBurst_Enable : Write Burst Mode enabled -* Output : None -* Return : None -*******************************************************************************/ -void SMI_WriteBurstConfig(u32 SMI_WriteBurst) -{ - if(SMI_WriteBurst == SMI_WriteBurst_Enable) - { - SMI->CR1 |= SMI_WriteBurst_Enable; - } - else - { - SMI->CR1 &= SMI_WriteBurst_Disable; - } -} - -/******************************************************************************* -* Function Name : SMI_WriteByte -* Description : Writes a Byte to the selected memory Bank. This function is -* used in Hardware mode only. -* Before calling this function, send a Write Enable command to -* the selected memory Bank using SMI_SendWENCmd() function. -* Input : - WriteAddr: external memory address from which the data will -* be written. -* - Data: data to be written to the external memory. -* Output : None -* Return : None -*******************************************************************************/ -void SMI_WriteByte(u32 WriteAddr, u8 Data) -{ - /* Transfer data to the memory */ - *(u8 *) WriteAddr = Data; -} - -/******************************************************************************* -* Function Name : SMI_WriteHalfWord -* Description : Writes a Half Word to the selected memory Bank. This function -* is used in Hardware mode only. -* Before calling this function, send a Write Enable command to -* the selected memory Bank using SMI_SendWENCmd() function. -* Input : - WriteAddr: external memory address from which the data will -* be written. -* - Data: data to be written to the external memory. -* Output : None -* Return : None -*******************************************************************************/ -void SMI_WriteHalfWord(u32 WriteAddr, u16 Data) -{ - /* Transfer data to the memory */ - *(u16 *) WriteAddr = Data; -} - -/******************************************************************************* -* Function Name : SMI_WriteWord -* Description : Writes a Word to the selected memory Bank. This function is -* used in Hardware mode only. -* Before calling this function, send a Write Enable command to -* the selected memory Bank using SMI_SendWENCmd() function. -* Input : - WriteAddr: external memory address from which the data will -* be written. -* - Data: data to be written to the external memory. -* Output : None -* Return : None -*******************************************************************************/ -void SMI_WriteWord(u32 WriteAddr, u32 Data) -{ - /* Transfer data to the memory */ - *(u32 *) WriteAddr = Data; -} - -/******************************************************************************* -* Function Name : SMI_ReadByte -* Description : Reads a Byte from the selected memory Bank. This function is -* used in Hardware mode only. -* Input : - ReadAddr: external memory address to read from. -* Output : None -* Return : Data read from the external memory. -*******************************************************************************/ -u8 SMI_ReadByte(u32 ReadAddr) -{ - return(*(u8 *) ReadAddr); -} - -/******************************************************************************* -* Function Name : SMI_ReadHalfWord -* Description : Reads a Half Word from the selected memory Bank. This function -* is used in Hardware mode only. -* Input : - ReadAddr: external memory address to read from. -* Output : None -* Return : Data read from the external memory. -*******************************************************************************/ -u16 SMI_ReadHalfWord(u32 ReadAddr) -{ - return(*(u16 *) ReadAddr); -} - -/******************************************************************************* -* Function Name : SMI_ReadWord -* Description : Reads a Word from the selected memory Bank. This function is -* used in Hardware mode only. -* Input : - ReadAddr: external memory address to read from. -* Output : None -* Return : Data read from the external memory. -*******************************************************************************/ -u32 SMI_ReadWord(u32 ReadAddr) -{ - return(*(u32 *) ReadAddr); -} - -/******************************************************************************* -* Function Name : SMI_ReadMemoryStatusRegister -* Description : Reads the status register of the memory connected to the -* selected Bank. -* Input : None -* Output : None -* Return : External memory status register value. -*******************************************************************************/ -u8 SMI_ReadMemoryStatusRegister(void) -{ - return((u8) (SMI->SR & SMI_STATUSREGISTER_Mask)); -} - -/******************************************************************************* -* Function Name : SMI_GetFlagStatus -* Description : Checks whether the specified SMI flag is set or not. -* Input : - SMI_FLAG: specifies the flag to check. -* This parameter can be one of the following values: -* - SMI_FLAG_Bank3_WM : Memory Bank3 Write Mode flag -* - SMI_FLAG_Bank2_WM : Memory Bank2 Write Mode flag -* - SMI_FLAG_Bank1_WM : Memory Bank1 Write Mode flag -* - SMI_FLAG_Bank0_WM : Memory Bank0 Write Mode flag -* - SMI_FLAG_ERF2 : Error Flag 2: Forbidden Write Request -* - SMI_FLAG_ERF1 : Error Flag 1: Forbidden Access -* - SMI_FLAG_WC : Write Complete flag -* - SMI_FLAG_TF : Transfer Finished flag -* Output : None -* Return : The new state of SMI_FLAG (SET or RESET). -*******************************************************************************/ -FlagStatus SMI_GetFlagStatus(u32 SMI_FLAG) -{ - if((SMI->SR & SMI_FLAG) != RESET) - { - return SET; - } - else - { - return RESET; - } -} - -/******************************************************************************* -* Function Name : SMI_ClearFlag -* Description : Clears the SMI’s pending flags. -* Input : - SMI_FLAG: specifies the flag to clear. -* This parameter can be any combination of the following values: -* - SMI_FLAG_ERF2 : Error Flag 2: Forbidden Write Request -* - SMI_FLAG_ERF1 : Error Flag 1: Forbidden Access -* - SMI_FLAG_WC : Write Complete flag -* - SMI_FLAG_TF : Transfer Finished flag -* Output : None -* Return : None -*******************************************************************************/ -void SMI_ClearFlag(u32 SMI_FLAG) -{ - SMI->SR &= ~SMI_FLAG; -} - -/******************************************************************************* -* Function Name : SMI_GetITStatus -* Description : Checks whether the specified SMI interrupt has occurred or not. -* Input : - SMI_FLAG: specifies the interrupt source to check. -* This parameter can be one of the following values: -* - SMI_IT_WC : Write Complete Interrupt -* - SMI_IT_TF : Transfer Finished Interrupt -* Output : None -* Return : The new state of SMI_IT (SET or RESET). -*******************************************************************************/ -ITStatus SMI_GetITStatus(u32 SMI_IT) -{ - if(((SMI->CR2 & SMI_IT) != RESET) && ((SMI->SR & SMI_IT) != RESET)) - { - return SET; - } - else - { - return RESET; - } -} - -/******************************************************************************* -* Function Name : SMI_ClearITPendingBit -* Description : Clears the SMI’s interrupt pending bits. -* Input : - SMI_FLAG: specifies the interrupts sources to clear. -* This parameter can be any combination of the following values: -* - SMI_IT_WC : Write Complete Interrupt -* - SMI_IT_TF : Transfer Finished Interrupt -* Output : None -* Return : None -*******************************************************************************/ -void SMI_ClearITPendingBit(u32 SMI_IT) -{ - SMI->SR &= ~SMI_IT; -} - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_ssp.c b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_ssp.c deleted file mode 100644 index b4ccd215e..000000000 --- a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_ssp.c +++ /dev/null @@ -1,588 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_ssp.c -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file provides all the SSP software functions. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -#include "75x_ssp.h" -#include "75x_mrcc.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* SSP peripheral Enable */ -#define SSP_Enable 0x0002 -#define SSP_Disable 0xFFFD - -/* SSP Loop Back Mode Enable */ -#define SSP_LoopBackMode_Enable 0x0001 -#define SSP_LoopBackMode_Disable 0xFFFE - -/* SSP Flag Mask */ -#define SSP_Flag_Mask 0x001F - -/* SSP DMA transmit/ receive enable/disable Masks */ -#define SSP0_DMA_TransmitEnable 0x0002 -#define SSP0_DMA_TransmitDisable 0xFFFD -#define SSP0_DMA_ReceiveEnable 0x0001 -#define SSP0_DMA_ReceiveDisable 0xFFFE - -/* SSP Masks */ -#define SSP_FrameFormat_Mask 0xFFCF -#define SSP_DataSize_Mask 0xFFF0 -#define SSP_ClockRate_Mask 0x00FF -#define SSP_ClockPrescaler_Mask 0xFF00 -#define SSP_SSI_Set_Mask 0x0020 -#define SSP_SSI_Reset_Mask 0xFFDF - - -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/******************************************************************************* -* Function Name : SSP_DeInit -* Description : Deinitializes the SSPx peripheral registers to their default -* reset values. -* Input : SSPx: where x can be 0 or 1 to select the SSP peripheral. -* Output : None -* Return : None -*******************************************************************************/ -void SSP_DeInit(SSP_TypeDef* SSPx) -{ - if(SSPx == SSP0) - { - /* Reset the SSP0 registers values*/ - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_SSP0,ENABLE); - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_SSP0,DISABLE); - } - else if (SSPx == SSP1) - { - /* Reset the SSP1 registers values*/ - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_SSP1,ENABLE); - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_SSP1,DISABLE); - } -} - -/******************************************************************************* -* Function Name : SSP_Init -* Description : Initializes the SSPx peripheral according to the specified -* parameters in the SSP_InitTypeDef structure. -* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. -* - SSP_InitStruct: pointer to a SSP_InitTypeDef structure that -* contains the configuration information for the specified SSP -* peripheral. -* Output : None -* Return : None -*******************************************************************************/ -void SSP_Init(SSP_TypeDef* SSPx, SSP_InitTypeDef* SSP_InitStruct) -{ - /* Configure the Frame format */ - if(SSP_InitStruct->SSP_FrameFormat == SSP_FrameFormat_TI) - { - /* Clear the FRF[1:0] bits */ - SSPx->CR0 &= SSP_FrameFormat_Mask; - /* Set the TI frame format */ - SSPx->CR0 |= SSP_FrameFormat_TI; - } - else - { - /* Set the Motorola frame format */ - SSPx->CR0 &= SSP_FrameFormat_Motorola; - /* Configure the Clock polarity */ - if(SSP_InitStruct->SSP_CPOL == SSP_CPOL_High) - { - /* SCK is held high when no data is being transfered */ - SSPx->CR0 |= SSP_CPOL_High; - } - else - { - /* SCK is held low when no data is being transfered */ - SSPx->CR0 &= SSP_CPOL_Low; - } - /* Configure the Clock Phase */ - if(SSP_InitStruct->SSP_CPHA == SSP_CPHA_2Edge) - { - /* Data captured on second clock edge */ - SSPx->CR0 |= SSP_CPHA_2Edge; - } - else - { - /* Data captured on first clock edge */ - SSPx->CR0 &= SSP_CPHA_1Edge; - } - } - - /* Configure the Mode */ - if(SSP_InitStruct->SSP_Mode == SSP_Mode_Slave) - { - /* Set the slave mode */ - SSPx->CR1 |= SSP_Mode_Slave; - /* Configure the Slave output */ - if(SSP_InitStruct->SSP_SlaveOutput == SSP_SlaveOutput_Disable) - { - /* Slave output disabled */ - SSPx->CR1 |= SSP_SlaveOutput_Disable; - } - else - { - /* Slave output enabled */ - SSPx->CR1 &= SSP_SlaveOutput_Enable; - } - /* Configure the NSS pin */ - if(SSP_InitStruct->SSP_NSS == SSP_NSS_Soft) - { - /* Slave selected by software through SSI bit */ - SSPx->CR1 |= SSP_NSS_Soft; - SSPx->CR1 &= SSP_SSI_Reset_Mask; - } - else - { - /* Slave selected by hardware through external SSpin */ - SSPx->CR1 &= SSP_NSS_Hard; - } - /* Configure the Clock rate and prescaler in TI slave mode */ - if(SSP_InitStruct->SSP_FrameFormat == SSP_FrameFormat_TI) - { - /* Clear clock rate SCR[7:0] bits */ - SSPx->CR0 &= SSP_ClockRate_Mask; - /* Set the serial clock rate */ - SSPx->CR0 |= (SSP_InitStruct->SSP_ClockRate<<8); - /* Clear clock prescaler CPSDVSR[7:0] bits */ - SSPx->PR &= SSP_ClockPrescaler_Mask; - /* Set the serial clock prescaler */ - SSPx->PR |= SSP_InitStruct->SSP_ClockPrescaler; - } - } - else - { - /* Set the master mode */ - SSPx->CR1 &= SSP_Mode_Master; - /* Configure the NSS pin */ - if(SSP_InitStruct->SSP_NSS == SSP_NSS_Soft) - { - /* Master selected by software through SSI bit */ - SSPx->CR1 |= SSP_NSS_Soft; - SSPx->CR1 |= SSP_SSI_Set_Mask; - } - else - { - /* Master selected by hardware through external SSpin */ - SSPx->CR1 &= SSP_NSS_Hard; - } - /* Clear clock rate SCR[7:0] bits */ - SSPx->CR0 &= SSP_ClockRate_Mask; - /* Set the serial clock rate */ - SSPx->CR0 |= (SSP_InitStruct->SSP_ClockRate<<8); - /* Clear clock prescaler CPSDVSR[7:0] bits */ - SSPx->PR &= SSP_ClockPrescaler_Mask; - /* Set the serial clock prescaler */ - SSPx->PR |= SSP_InitStruct->SSP_ClockPrescaler; - } - - /* Clear data size DSS[3:0] bits */ - SSPx->CR0 &= SSP_DataSize_Mask; - /* Set the data size */ - SSPx->CR0 |= SSP_InitStruct->SSP_DataSize; -} - -/******************************************************************************* -* Function Name : SSP_StructInit -* Description : Fills each SSP_InitStruct member with its default value. -* Input : SSP_InitStruct : pointer to a SSP_InitTypeDef structure - which will be initialized. -* Output : None -* Return : None -*******************************************************************************/ -void SSP_StructInit(SSP_InitTypeDef* SSP_InitStruct) -{ - /* Initialize the SSP_FrameFormat member */ - SSP_InitStruct->SSP_FrameFormat = SSP_FrameFormat_Motorola; - - /* Initialize the SSP_Mode member */ - SSP_InitStruct->SSP_Mode = SSP_Mode_Master; - - /* Initialize the SSP_CPOL member */ - SSP_InitStruct->SSP_CPOL = SSP_CPOL_Low; - - /* Initialize the SSP_CPHA member */ - SSP_InitStruct->SSP_CPHA = SSP_CPHA_1Edge; - - /* Initialize the SSP_DataSize member */ - SSP_InitStruct->SSP_DataSize = SSP_DataSize_8b; - - /* Initialize the SSP_NSS member */ - SSP_InitStruct->SSP_NSS = SSP_NSS_Hard; - - /* Initialize the SSP_SlaveOutput member */ - SSP_InitStruct->SSP_SlaveOutput = SSP_SlaveOutput_Enable; - - /* Initialize the SSP_ClockRate member */ - SSP_InitStruct->SSP_ClockRate = 0; - - /* Initialize the SSP_ClockPrescaler member */ - SSP_InitStruct->SSP_ClockPrescaler = 0; -} - -/******************************************************************************* -* Function Name : SSP_Cmd -* Description : Enables or disables the specified SSP peripheral. -* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. -* - NewState: new state of the SSPx peripheral. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void SSP_Cmd(SSP_TypeDef* SSPx, FunctionalState NewState) -{ - if(NewState == ENABLE) - { - /* Enable the SSP peripheral */ - SSPx->CR1 |= SSP_Enable; - } - else - { - /* Disable the SSP peripheral */ - SSPx->CR1 &= SSP_Disable; - } -} - -/******************************************************************************* -* Function Name : SSP_ITConfig -* Description : Enables or disables the specified SSP interrupts. -* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. -* - SSP_IT: specifies the SSP interrupts sources to be enabled -* or disabled. This parameter can be any combination of the -* following values: -* - SSP_IT_TxFifo: Transmit FIFO half empty or less interrupt -* - SSP_IT_RxFifo: Receive FIFO half full or less interrupt -* - SSP_IT_RxTimeOut: Receive timeout interrupt -* - SSP_IT_RxOverrun: Receive overrun interrupt -* - NewState: new state of the specified SSP interrupts. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void SSP_ITConfig(SSP_TypeDef* SSPx, u16 SSP_IT, FunctionalState NewState) -{ - if(NewState == ENABLE) - { - /* Enable the selected SSP interrupts */ - SSPx->IMSCR |= SSP_IT; - } - else - { - /* Disable the selected SSP interrupts */ - SSPx->IMSCR &= ~SSP_IT; - } -} - -/******************************************************************************* -* Function Name : SSP_DMACmd -* Description : Configures the SSP0 DMA interface. -* Input : - SSP0_DMAtransfer : specifies the DMA transfer to be -* enabled or disabled. This parameter can be one of the -* following values: -* - SSP0_DMA_Transmit: transmit Fifo DMA transfer -* - SSP0_DMA_Receive: receive Fifo DMA transfer -* - NewState: new state of SSP0 DMA transfer. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void SSP_DMACmd(u16 SSP0_DMAtransfer, FunctionalState NewState) -{ - if(NewState == ENABLE) - { - if(SSP0_DMAtransfer == SSP0_DMA_Transmit) - { - /* Enable DMA for the transmit FIFO */ - SSP0->DMACR |= SSP0_DMA_TransmitEnable; - } - else - { - /* Enable DMA for the receive FIFO */ - SSP0->DMACR |= SSP0_DMA_ReceiveEnable; - } - } - else - { - if(SSP0_DMAtransfer == SSP0_DMA_Transmit) - { - /* Disable DMA for the transmit FIFO */ - SSP0->DMACR &= SSP0_DMA_TransmitDisable; - } - else - { - /* Disable DMA for the receive FIFO */ - SSP0->DMACR &= SSP0_DMA_ReceiveDisable; - } - } -} - -/******************************************************************************* -* Function Name : SSP_DMATxConfig -* Description : Configures the SSP0 DMA transmit transfer. -* Input : - SSP0_DMATxReq : specifies the SSP0 DMA transmit request to -* be enabled. This parameter can be one of the following -* values: -* - SSP0_DMATxReq_Single: Transmit FIFO DMA single -* request enabled -* - SSP0_DMATxReq_Burst: Transmit FIFO DMA burst request -* enabled -* Output : None -* Return : None -*******************************************************************************/ -void SSP_DMATxConfig(u16 SSP0_DMATxReq) -{ - if(SSP0_DMATxReq == SSP0_DMATxReq_Burst) - { - /* Enable DMA transmit burst request */ - SSP0->DMACR |= SSP0_DMATxReq_Burst; - } - else - { - /* Enable DMA transmit single request */ - SSP0->DMACR &= SSP0_DMATxReq_Single; - } -} - -/******************************************************************************* -* Function Name : SSP_DMARxConfig -* Description : Configures the SSP0 DMA receive transfer. -* Input : - SSP0_DMARxReq : specifies the SSP0 DMA receive request to -* be enabled. This parameter can be one of the following -* values: -* - SSP0_DMARxReq_Single: Receive FIFO DMA burst request -* enabled -* - SSP0_DMARxReq_Burst: Receive FIFO DMA single request -* enabled -* Output : None -* Return : None -*******************************************************************************/ -void SSP_DMARxConfig(u16 SSP0_DMARxReq) -{ - if(SSP0_DMARxReq == SSP0_DMARxReq_Burst) - { - /* Enable DMA receive burst request */ - SSP0->DMACR |= SSP0_DMARxReq_Burst; - } - else - { - /* Enable DMA receive single request */ - SSP0->DMACR &= SSP0_DMARxReq_Single; - } -} - -/******************************************************************************* -* Function Name : SSP_SendData -* Description : Transmits a Data through the SSP peripheral. -* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. -* - Data : Data to be transmitted. -* Output : None -* Return : None -*******************************************************************************/ -void SSP_SendData(SSP_TypeDef* SSPx, u16 Data) -{ - /* Write in the DR register the data to be sent */ - SSPx->DR = Data; -} - -/******************************************************************************* -* Function Name : SSP_ReceiveData -* Description : Returns the most recent received data by the SSP peripheral. -* Input : SSPx: where x can be 0 or 1 to select the SSP peripheral. -* Output : None -* Return : The value of the received data. -*******************************************************************************/ -u16 SSP_ReceiveData(SSP_TypeDef* SSPx) -{ - /* Return the data in the DR register */ - return SSPx->DR; -} - -/******************************************************************************* -* Function Name : SSP_LoopBackConfig -* Description : Enables or disables the Loop back mode for the selected SSP -* peripheral. -* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. -* - NewState: new state of the Loop Back mode. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void SSP_LoopBackConfig(SSP_TypeDef* SSPx, FunctionalState NewState) -{ - if(NewState == ENABLE) - { - /* Enable loop back mode */ - SSPx->CR1 |= SSP_LoopBackMode_Enable; - } - else - { - /* Disable loop back mode */ - SSPx->CR1 &= SSP_LoopBackMode_Disable; - } -} - -/******************************************************************************* -* Function Name : SSP_NSSInternalConfig -* Description : Configures by software the NSS pin. -* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. -* - SSP_NSSState: NSS internal state.This parameter can be one -* of the following values: -* - SSP_NSSInternal_Set: Set NSS pin internally -* - SSP_NSSInternal_Reset: Reset NSS pin internally -* Output : None -* Return : None -*******************************************************************************/ -void SSP_NSSInternalConfig(SSP_TypeDef* SSPx, u16 SSP_NSSState) -{ - if(SSP_NSSState == SSP_NSSInternal_Set) - { - /* Set NSS pin internally */ - SSPx->CR1 |= SSP_NSSInternal_Set; - } - else - { - /* Reset NSS pin internally */ - SSPx->CR1 &= SSP_NSSInternal_Reset; - } -} - -/******************************************************************************* -* Function Name : SSP_GetFlagStatus -* Description : Checks whether the specified SSP flag is set or not. -* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. -* - SSP_FLAG: specifies the flag to check. This parameter can -* be one of the following values: -* - SSP_FLAG_Busy: busy flag -* - SSP_FLAG_RxFifoFull: Receive FIFO full flag -* - SSP_FLAG_RxFifoNotEmpty: Receive FIFO not empty flag -* - SSP_FLAG_TxFifoNotFull: Transmit FIFO not full flag -* - SSP_FLAG_TxFifoEmpty: Transmit FIFO empty flag -* - SSP_FLAG_TxFifo: Transmit FIFO half empty or less flag -* - SSP_FLAG_RxFifo: Receive FIFO half full or less flag -* - SSP_FLAG_RxTimeOut: Receive timeout flag -* - SSP_FLAG_RxOverrun: Receive overrun flag -* Output : None -* Return : The new state of SSP_FLAG(SET or RESET). -*******************************************************************************/ -FlagStatus SSP_GetFlagStatus(SSP_TypeDef* SSPx, u16 SSP_FLAG) -{ - u32 SSPReg = 0, FlagPos = 0; - u32 StatusReg = 0; - - /* Get the SSP register index */ - SSPReg = SSP_FLAG >> 5; - - /* Get the flag position */ - FlagPos = SSP_FLAG & SSP_Flag_Mask; - - /* Find the register of the flag to check */ - if(SSPReg == 1) - { - /* The flag to check is in SR register */ - StatusReg = SSPx->SR; - } - else if (SSPReg == 2) - { - /* The flag to check is in RISR register */ - StatusReg = SSPx->RISR; - } - - /* Check the status of the specified SSP flag */ - if((StatusReg & (1 << FlagPos)) != RESET) - { - /* Return SET if the SSP flag is set */ - return SET; - } - else - { - /* Return RESET if the SSP flag is reset */ - return RESET; - } -} - -/******************************************************************************* -* Function Name : SSP_ClearFlag -* Description : Clears the SSPx’s pending flags. -* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. -* - SSP_FLAG: specifies the flag to clear. This parameter can -* be one of the following values: -* - SSP_FLAG_RxTimeOut: Receive timeout flag -* - SSP_FLAG_RxOverrun: Receive overrun flag -* Output : None -* Return : None -*******************************************************************************/ -void SSP_ClearFlag(SSP_TypeDef* SSPx, u16 SSP_FLAG) -{ - u8 FlagPos = 0; - - /* Get the flag position */ - FlagPos = SSP_FLAG & SSP_Flag_Mask; - - /* Clear the selected SSP flag */ - SSPx->ICR = (1 << FlagPos); -} - -/******************************************************************************* -* Function Name : SSP_GetITStatus -* Description : Checks whether the specified SSP interrupt has occurred or not. -* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. -* - SSP_IT: specifies the interrupt source to check. -* This parameter can be one of the following values: -* - SSP_IT_TxFifo: Transmit FIFO half empty or less interrupt -* - SSP_IT_RxFifo: Receive FIFO half full or less interrupt -* - SSP_IT_RxTimeOut: Receive timeout interrupt -* - SSP_IT_RxOverrun: Receive overrun interrupt -* Output : None -* Return : The new state of SSP_IT(SET or RESET). -*******************************************************************************/ -ITStatus SSP_GetITStatus(SSP_TypeDef* SSPx, u16 SSP_IT) -{ - /* Check the status of the specified interrupt flag */ - if((SSPx->MISR & SSP_IT) != RESET) - { - /* Return SET if the SSP interrupt flag is set */ - return SET; - } - else - { - /* Return RESET if SSP interrupt flag is reset */ - return RESET; - } -} - -/******************************************************************************* -* Function Name : SSP_ClearITPendingBit -* Description : Clears the SSPx’s interrupt pending bits. -* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. -* - SSP_IT: specifies the interrupt pending bit to clear. -* This parameter can be any combination of the following values: -* - SSP_IT_RxTimeOut: Receive timeout interrupt -* - SSP_IT_RxOverrun: Receive overrun interrupt -* Output : None -* Return : None -*******************************************************************************/ -void SSP_ClearITPendingBit(SSP_TypeDef* SSPx, u16 SSP_IT) -{ - /* Clear the selected SSP interrupts pending bits */ - SSPx->ICR = SSP_IT; -} - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_tb.c b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_tb.c deleted file mode 100644 index 4f461f997..000000000 --- a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_tb.c +++ /dev/null @@ -1,425 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_tb.c -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file provides all the TB software functions. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -#include "75x_tb.h" -#include "75x_mrcc.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -#define TB_IT_Enable_Mask 0x7FFF -#define TB_IT_Clear_Mask 0x7FFF -#define TB_IC_Enable 0x0004 -#define TB_ICPolarity_Set 0x0008 -#define TB_ICPolarity_Reset 0xFFF7 -#define TB_UFS_Reset 0xFFFE -#define TB_UFS_Set 0x0001 - -/* TB debug state */ -#define TB_DBGC_Set 0x0400 -#define TB_DBGC_Reset 0xFB7F - -/* TB counter state */ -#define TB_COUNTER_Reset 0x0002 -#define TB_COUNTER_Start 0x0004 -#define TB_COUNTER_Stop 0xFFFB - -#define TB_SMS_EXTCLK_Set 0x0008 -#define TB_SMS_RESETCLK_Set 0x0000 - -/* TB Slave Mode Enable Set/Reset value */ -#define TB_SME_Reset 0x731B -#define TB_SME_Set 0x0004 - -/* TB Trigger Selection value */ -#define TB_TS_IC1_Set 0x0200 - -/* TB SCR Masks bit */ -#define TB_SlaveModeSelection_Mask 0x7307 -#define TB_TriggerSelection_Mask 0x701F - -/* Reset Register Masks */ -#define TB_Prescaler_Reset_Mask 0x0000 -#define TB_CounterMode_Mask 0xFF8F -#define TB_AutoReload_Reset_Mask 0xFFFF - -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - - /****************************************************************************** -* Function Name : TB_DeInit -* Description : Deinitializes the TB peripheral registers to their default -* reset values. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void TB_DeInit(void) -{ - /* Enters and exits the TB peripheral to and from reset */ - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TB,ENABLE); - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TB,DISABLE); -} - -/******************************************************************************* -* Function Name : TB_Init -* Description : Initializes TB peripheral according to the specified -* parameters in the TB_InitStruct. -* Input : TB_InitStruct: pointer to a TB_InitTypeDef structure that -* contains the configuration information for the TB peripheral. -* Output : None -* Return : None -*******************************************************************************/ -void TB_Init(TB_InitTypeDef* TB_InitStruct) -{ - /* Set the TB prescaler value */ - TB->PSC = TB_InitStruct->TB_Prescaler; - - /* Set the TB period value */ - TB->ARR = TB_InitStruct->TB_AutoReload; - - /* Set the corresponding counter mode */ - TB->CR = (TB->CR & TB_CounterMode_Mask) | TB_InitStruct->TB_CounterMode; - - /* Set the corresponding clock source */ - if(TB_InitStruct->TB_ClockSource == TB_ClockSource_CKRTC) - { - TB->SCR &= TB_SME_Reset & TB_SlaveModeSelection_Mask & TB_TriggerSelection_Mask; - TB->SCR |= TB_SMS_EXTCLK_Set | TB_SME_Set | TB_TS_IC1_Set; - } - else - { - TB->SCR &= TB_SME_Reset & TB_SlaveModeSelection_Mask & TB_TriggerSelection_Mask; - } - - if(TB_InitStruct->TB_Mode == TB_Mode_IC) - { - /* Set the corresponding value in TB SCR register */ - TB->SCR &= TB_SME_Reset & TB_SlaveModeSelection_Mask & TB_TriggerSelection_Mask; - TB->SCR |= TB_SMS_RESETCLK_Set | TB_SME_Set | TB_TS_IC1_Set; - - /* Set the IC1 enable bit */ - TB->IMCR |= TB_IC_Enable; - - /* Set the input signal polarity */ - if (TB_InitStruct->TB_ICAPolarity == TB_ICAPolarity_Falling) - { - TB->IMCR |= TB_ICPolarity_Set; - } - else - { - TB->IMCR &= TB_ICPolarity_Reset; - } - } -} - -/******************************************************************************* -* Function Name : TB_StructInit -* Description : Fills each TB_InitStruct member with its default value -* Input : TB_InitStruct : pointer to a TB_InitTypeDef structure which -* will be initialized. -* Output : None -* Return : None -*******************************************************************************/ -void TB_StructInit(TB_InitTypeDef *TB_InitStruct) -{ - TB_InitStruct->TB_Mode = TB_Mode_Timing; - TB_InitStruct->TB_ClockSource = TB_ClockSource_CKTIM; - TB_InitStruct->TB_CounterMode = TB_CounterMode_Up; - TB_InitStruct->TB_ICAPolarity = TB_ICAPolarity_Rising; - TB_InitStruct->TB_Prescaler = TB_Prescaler_Reset_Mask; - TB_InitStruct->TB_AutoReload = TB_AutoReload_Reset_Mask; -} - -/******************************************************************************* -* Function Name : TB_Cmd -* Description : Enables or disables the TB peripheral. -* Input : Newstate: new state of the TB peripheral. This parameter can -* be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void TB_Cmd(FunctionalState Newstate) -{ - if(Newstate == ENABLE) - { - TB->CR |= TB_COUNTER_Start; - } - else - { - TB->CR &= TB_COUNTER_Stop; - } -} - -/******************************************************************************* -* Function Name : TB_ITConfig -* Description : Enables or disables the specified TB interrupt. -* Input : - TB_IT: specifies the TB interrupt sources to be enabled or -* disabled. -* This parameter can be any combination of the following values: -* - TB_IT_Update: TB Update interrupt -* - TB_IT_GlobalUpdate: TB Global Update interrupt -* - TB_IT_IC: TB Input Capture interrupt -* - Newstate: new state of the specified TB interrupts. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void TB_ITConfig(u16 TB_IT, FunctionalState Newstate) -{ - u16 TB_IT_Enable = 0; - - TB_IT_Enable = TB_IT & TB_IT_Enable_Mask; - - if(Newstate == ENABLE) - { - /* Update interrupt global source: overflow/undeflow, counter reset operation - or slave mode controller in reset mode */ - if ((TB_IT & TB_IT_GlobalUpdate) == TB_IT_GlobalUpdate) - { - TB->CR &= TB_UFS_Reset; - } - /* Update interrupt source: counter overflow/underflow */ - else if ((TB_IT & TB_IT_Update) == TB_IT_Update) - { - TB->CR |= TB_UFS_Set; - } - /* Select and enable the interrupts requests */ - TB->RSR |= TB_IT_Enable; - TB->RER |= TB_IT_Enable; - } - /* Disable the interrupts requests */ - else - { - TB->RSR &= ~TB_IT_Enable; - TB->RER &= ~TB_IT_Enable; - } -} - -/******************************************************************************* -* Function Name : TB_SetPrescaler -* Description : Sets the TB Prescaler value. -* Input : Prescaler: specifies the TB Prescaler value. -* Output : None -* Return : None -*******************************************************************************/ -void TB_SetPrescaler(u16 Prescaler) -{ - /* Sets the prescaler value */ - TB->PSC = Prescaler; -} - -/******************************************************************************* -* Function Name : TB_ResetCounter -* Description : Re-intializes the counter and generates an update of the -* registers. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void TB_ResetCounter(void) -{ - /* Re-intializes TB counter */ - TB->CR |= TB_COUNTER_Reset; -} - -/******************************************************************************* -* Function Name : TB_DebugCmd -* Description : Enables or disables TB peripheral Debug control. -* Input : Newstate: new state of the TB Debug control. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void TB_DebugCmd(FunctionalState Newstate) -{ - if(Newstate == ENABLE) - { - TB->CR |= TB_DBGC_Set; - } - else - { - TB->CR &= TB_DBGC_Reset; - } -} - -/******************************************************************************* -* Function Name : TB_CounterModeConfig -* Description : Configures the TB Counter Mode. -* Input : TB_CounterMode: specifies the TB counter mode to be used. -* This parameter can be one of the following values: -* - TB_CounterMode_Up: TB Up Counting Mode -* - TB_CounterMode_Down: TB Down Counting Mode -* - TB_CounterMode_CenterAligned: TB Center Aligned Mode -* Output : None -* Return : None -*******************************************************************************/ -void TB_CounterModeConfig(u16 TB_CounterMode) -{ - /* Counter mode configuration */ - TB->CR &= TB_CounterMode_Mask; - TB->CR |= TB_CounterMode; -} - -/******************************************************************************* -* Function Name : TB_SLaveModeConfig -* Description : Configures the TB slave Mode. -* Input : TB_SMSMode: specifies the TB slave mode to be used. -* This parameter can be one of the following values: -* - TB_SMSMode_Trigger: The counter starts at a rising -* edge of the trigger -* - TB_SMSMode_Gated: The counter clock is enabled when -* trigger signal is high -* - TB_SMSMode_External: The rising edge of selected trigger -* clocks the counter -* - TB_SMSMode_Reset: The rising edge of the selected -* trigger signal resets the counter -* Output : None -* Return : None -*******************************************************************************/ -void TB_SLaveModeConfig(u16 TB_SMSMode) -{ - TB->SCR &= TB_SME_Reset & TB_SlaveModeSelection_Mask & TB_TriggerSelection_Mask; - TB->SCR |= TB_SME_Set | TB_SMSMode | TB_TS_IC1_Set; -} -/******************************************************************************* -* Function Name : TB_GetCounter -* Description : Gets the TB Counter value. -* Input : None -* Output : None -* Return : The TB counter register value. -*******************************************************************************/ -u16 TB_GetCounter(void) -{ - return TB->CNT; -} - -/******************************************************************************* -* Function Name : TB_GetICAP1 -* Description : Gets the TB Input capture value. -* Input : None -* Output : None -* Return : The TB ICR1 register value. -*******************************************************************************/ -u16 TB_GetICAP1(void) -{ - return TB->ICR1; -} - -/******************************************************************************* -* Function Name : TB_SetCounter -* Description : Sets the TB Counter value. -* Input : Counter: specifies the TB Counter value. -* Output : None -* Return : None -*******************************************************************************/ -void TB_SetCounter(u16 Counter) -{ - TB->CNT = Counter; -} - -/******************************************************************************* -* Function Name : TB_GetFlagStatus -* Description : Checks whether the specified TB flag is set or not. -* Input : TB_FLAG: specifies the flag to check. -* This parameter can be one of the following values: -* - TB_FLAG_IC: TB Input Capture flag -* - TB_FLAG_Update: TB update flag -* Output : None -* Return : The new state of the TB_FLAG (SET or RESET). -*******************************************************************************/ -FlagStatus TB_GetFlagStatus(u16 TB_FLAG) -{ - if((TB->ISR & TB_FLAG) != RESET ) - { - return SET; - } - else - { - return RESET; - } -} - -/******************************************************************************* -* Function Name : TB_ClearFlag -* Description : Clears the TB’s pending flags. -* Input : TB_FLAG: specifies the flag to clear. -* This parameter can be any combination of the following values: -* - TB_FLAG_IC: TB Input Capture flag -* - TB_FLAG_Update: TB update flag -* Output : None -* Return : None -*******************************************************************************/ -void TB_ClearFlag(u16 TB_FLAG) -{ - /* Clears the flags */ - TB->ISR &= ~TB_FLAG; -} - -/******************************************************************************* -* Function Name : TB_GetITStatus -* Description : Checks whether the specified TB interrupt has occurred or not. -* Input : TB_IT: specifies the interrupt to check. -* This parameter can be one of the following values: -* - TB_IT_Update: TB Update interrupt -* - TB_IT_GlobalUpdate: TB Global Update interrupt -* - TB_IT_IC: TB Input Capture interrupt -* Output : None -* Return : The new state of the TB_IT (SET or RESET). -*******************************************************************************/ -ITStatus TB_GetITStatus(u16 TB_IT) -{ - u16 TB_IT_Check = 0; - - /* Calculates the pending bits to be checked */ - TB_IT_Check = TB_IT & TB_IT_Clear_Mask; - - if((TB->ISR & TB_IT_Check) != RESET ) - { - return SET; - } - else - { - return RESET; - } -} - -/******************************************************************************* -* Function Name : TB_ClearITPendingBit -* Description : Clears the TB's interrupt pending bits. -* Input : TB_IT: specifies the interrupt pending bit to clear. -* This parameter can be any combination of the following values: -* - TB_IT_Update: TB Update interrupt -* - TB_IT_GlobalUpdate: TB Global Update interrupt -* - TB_IT_IC: TB Input Capture interrupt -* Output : None -* Return : None -*******************************************************************************/ -void TB_ClearITPendingBit(u16 TB_IT) -{ - u16 TB_IT_Clear = 0; - - /* Calculates the pending bits to be cleared */ - TB_IT_Clear = TB_IT & TB_IT_Clear_Mask; - - /* Clears the pending bits */ - TB->ISR &= ~TB_IT_Clear; -} -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_tim.c b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_tim.c deleted file mode 100644 index d23d97965..000000000 --- a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_tim.c +++ /dev/null @@ -1,1360 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_tim.c -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file provides all the TIM software functions. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -#include "75x_tim.h" -#include "75x_mrcc.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* TIM interrupt masks */ -#define TIM_IT_Clear_Mask 0x7FFF -#define TIM_IT_Enable_Mask 0x7FFF - -/* TIM Input Capture Selection Set/Reset */ -#define TIM_IC1S_Set 0x0001 -#define TIM_IC1S_Reset 0x003E - -/* TIM Input Capture Selection Set/Reset */ -#define TIM_IC2S_Set 0x0002 -#define TIM_IC2S_Reset 0x003D - -/* TIM_SCR Masks bit */ -#define TIM_Encoder_Mask 0x731C -#define TIM_SlaveModeSelection_Mask 0x7307 -#define TIM_TriggerSelection_Mask 0x701F -#define TIM_InternalTriggerSelection_Mask 0x031F - -/* TIM Encoder mode Set value */ -#define TIM_Encoder1_Set 0x0001 -#define TIM_Encoder2_Set 0x0002 -#define TIM_Encoder3_Set 0x0003 - -/* TIM Slave Mode Enable Set/Reset value */ -#define TIM_SME_Reset 0x731B -#define TIM_SME_Set 0x0004 - -/* TIM Internal Trigger Selection value */ -#define TIM_ITS_TIM0 0x1000 -#define TIM_ITS_TIM1 0x2000 -#define TIM_ITS_TIM2 0x3000 -#define TIM_ITS_PWM 0x4000 - -/* TIM Trigger Selection value */ -#define TIM_TS_IC1_Set 0x0200 -#define TIM_TS_IC2_Set 0x0300 - -/* TIM Slave Mode selction external clock Set value */ -#define TIM_SMS_EXTCLK_Set 0x0008 -#define TIM_SMS_RESETCLK_Set 0x0000 - -/* TIM_CR Masks bit */ -#define TIM_DBASE_Mask 0x077F -#define TIM_MasterModeSelection_Mask 0xFC7F -#define TIM_CounterMode_Mask 0xFF8F - -/* TIM Update flag selection Set/Reset value */ -#define TIM_UFS_Reset 0xFFFE -#define TIM_UFS_Set 0x0001 - -/* TIM Counter value */ -#define TIM_COUNTER_Reset 0x0002 -#define TIM_COUNTER_Start 0x0004 -#define TIM_COUNTER_Stop 0xFFFB - -/* TIM One pulse Mode set value */ -#define TIM_OPM_Set 0x0008 -#define TIM_OPM_Reset 0xFFF7 - -/* TIM Debug Mode Set/Reset value */ -#define TIM_DBGC_Set 0x0400 -#define TIM_DBGC_Reset 0xFB7F - -/* TIM Input Capture Enable/Disable value */ -#define TIM_IC1_Enable 0x0004 -#define TIM_IC2_Enable 0x0010 - -/* TIM Input Capture Polarity Set/Reset value */ -#define TIM_IC1P_Set 0x0008 -#define TIM_IC2P_Set 0x0020 -#define TIM_IC1P_Reset 0x0037 -#define TIM_IC2P_Reset 0x001F - -/* TIM Output Compare Polarity Set/Reset value */ -#define TIM_OC1P_Set 0x0020 -#define TIM_OC2P_Set 0x2000 -#define TIM_OC1P_Reset 0x3F1F -#define TIM_OC2P_Reset 0x1F3F - -/* TIM Output Compare control mode constant */ -#define TIM_OCControl_PWM 0x000C -#define TIM_OCControl_OCToggle 0x0006 -#define TIM_OCControl_OCInactive 0x0004 -#define TIM_OCControl_OCActive 0x0002 -#define TIM_OCControl_OCTiming 0x0000 - -/* TIM Output Compare mode Enable value */ -#define TIM_OC1_Enable 0x0010 -#define TIM_OC2_Enable 0x1000 - -/* TIM Output Compare mode Mask value */ -#define TIM_OC1C_Mask 0x3F31 -#define TIM_OC2C_Mask 0x313F - -/* TIM Preload bit Set/Reset value */ -#define TIM_PLD1_Set 0x0001 -#define TIM_PLD1_Reset 0xFFFE - -#define TIM_PLD2_Set 0x0100 -#define TIM_PLD2_Reset 0xFEFF - -/* TIM OCRM Set/Reset value */ -#define TIM_OCRM_Set 0x0080 -#define TIM_OCRM_Reset 0x030D - -/* Reset Register Masks */ -#define TIM_Pulse2_Reset_Mask 0x0000 -#define TIM_Prescaler_Reset_Mask 0x0000 -#define TIM_Pulse1_Reset_Mask 0x0000 -#define TIM_Period_Reset_Mask 0xFFFF -#define TIM_Counter_Reset 0x0002 - -/* Private function prototypes -----------------------------------------------*/ -static void ICAP_ModuleConfig(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct); -static void Encoder_ModeConfig(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct); -static void OCM_ModuleConfig(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct); - -/* Private functions ---------------------------------------------------------*/ - -/****************************************************************************** -* Function Name : TIM_DeInit -* Description : Deinitializes TIM peripheral registers to their default reset -* values. -* Input : TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. -* Output : None -* Return : None -*******************************************************************************/ -void TIM_DeInit(TIM_TypeDef *TIMx) -{ - if(TIMx == TIM0) - { - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TIM0,ENABLE); - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TIM0,DISABLE); - } - else if(TIMx == TIM1) - { - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TIM1,ENABLE); - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TIM1,DISABLE); - } - else if(TIMx == TIM2) - { - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TIM2,ENABLE); - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TIM2,DISABLE); - } -} - -/******************************************************************************* -* Function Name : TIM_Init -* Description : Initializes the TIMx peripheral according to the specified -* parameters in the TIM_InitStruct . -* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. -* - TIM_InitStruct: pointer to a TIM_InitTypeDef structure that -* contains the configuration information for the specified TIM -* peripheral. -* Output : None -* Return : None -*******************************************************************************/ -void TIM_Init(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct) -{ - /* Set the prescaler value */ - TIMx->PSC = TIM_InitStruct->TIM_Prescaler; - - /* Select the clock source */ - TIM_ClockSourceConfig(TIMx, TIM_InitStruct->TIM_ClockSource, - TIM_InitStruct->TIM_ExtCLKEdge); - - /* Select the counter mode */ - TIMx->CR &= TIM_CounterMode_Mask; - TIMx->CR |= TIM_InitStruct->TIM_CounterMode; - - /* Set the period value */ - TIMx->ARR = TIM_InitStruct->TIM_Period; - - switch(TIM_InitStruct->TIM_Mode) - { - case TIM_Mode_OCTiming: case TIM_Mode_OCActive: case TIM_Mode_OCInactive: - case TIM_Mode_OCToggle: case TIM_Mode_PWM: - OCM_ModuleConfig(TIMx, TIM_InitStruct); - break; - - case TIM_Mode_PWMI: case TIM_Mode_IC: - ICAP_ModuleConfig(TIMx, TIM_InitStruct); - break; - - case TIM_Mode_Encoder1: case TIM_Mode_Encoder2: case TIM_Mode_Encoder3: - Encoder_ModeConfig(TIMx, TIM_InitStruct); - break; - - case TIM_Mode_OPM_PWM: case TIM_Mode_OPM_Toggle: case TIM_Mode_OPM_Active: - - /* Output module configuration */ - OCM_ModuleConfig(TIMx, TIM_InitStruct); - - /* Input module configuration */ - ICAP_ModuleConfig(TIMx, TIM_InitStruct); - - /* Set the slave mode to trigger Mode */ - TIMx->SCR |= TIM_SynchroMode_Trigger; - - /* Repetitive pulse state selection */ - if(TIM_InitStruct->TIM_RepetitivePulse == TIM_RepetitivePulse_Disable) - { - TIMx->CR |= TIM_OPM_Set; - } - else - { - TIMx->CR &= TIM_OPM_Reset; - } - break; - - default: - break; - } -} - -/******************************************************************************* -* Function Name : TIM_StructInit -* Description : Fills each TIM_InitStruct member with its default value. -* Input : TIM_InitStruct : pointer to a TIM_InitTypeDef structure -* which will be initialized. -* Output : None -* Return : None. -*******************************************************************************/ -void TIM_StructInit(TIM_InitTypeDef *TIM_InitStruct) -{ - /* Set the default configuration */ - TIM_InitStruct->TIM_Mode = TIM_Mode_OCTiming; - TIM_InitStruct->TIM_Prescaler = TIM_Prescaler_Reset_Mask; - TIM_InitStruct->TIM_ClockSource = TIM_ClockSource_Internal; - TIM_InitStruct->TIM_ExtCLKEdge = TIM_ExtCLKEdge_Rising; - TIM_InitStruct->TIM_CounterMode = TIM_CounterMode_Up; - TIM_InitStruct->TIM_Period = TIM_Period_Reset_Mask; - TIM_InitStruct->TIM_Channel = TIM_Channel_ALL; - TIM_InitStruct->TIM_Pulse1 = TIM_Pulse1_Reset_Mask; - TIM_InitStruct->TIM_Pulse2 = TIM_Pulse2_Reset_Mask; - TIM_InitStruct->TIM_RepetitivePulse = TIM_RepetitivePulse_Disable; - TIM_InitStruct->TIM_Polarity1 = TIM_Polarity1_Low; - TIM_InitStruct->TIM_Polarity2 = TIM_Polarity2_Low; - TIM_InitStruct->TIM_IC1Selection = TIM_IC1Selection_TI1; - TIM_InitStruct->TIM_IC2Selection = TIM_IC2Selection_TI1; - TIM_InitStruct->TIM_IC1Polarity = TIM_IC1Polarity_Rising; - TIM_InitStruct->TIM_IC2Polarity = TIM_IC2Polarity_Rising; - TIM_InitStruct->TIM_PWMI_ICSelection = TIM_PWMI_ICSelection_TI1; - TIM_InitStruct->TIM_PWMI_ICPolarity = TIM_PWMI_ICPolarity_Rising; -} - -/******************************************************************************* -* Function Name : TIM_Cmd -* Description : Enables or disables the specified TIM peripheral. -* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. -* - Newstate: new state of the TIMx peripheral. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState Newstate) -{ - if(Newstate == ENABLE) - { - TIMx->CR |= TIM_COUNTER_Start; - } - else - { - TIMx->CR &= TIM_COUNTER_Stop; - } -} - -/******************************************************************************* -* Function Name : TIM_ITConfig -* Description : Enables or disables the TIM interrupts. -* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. -* - TIM_IT: specifies the TIM interrupts sources to be enabled -* or disabled. -* This parameter can be any combination of the following values: -* - TIM_IT_IC1: Input Capture 1 Interrupt -* - TIM_IT_OC1: Output Compare 1 Interrupt -* - TIM_IT_Update: Timer update Interrupt -* - TIM_IT_GlobalUpdate: Timer global update Interrupt -* - TIM_IT_IC2: Input Capture 2 Interrupt -* - TIM_IT_OC2: Output Compare 2 Interrupt -* - Newstate: new state of the specified TIMx interrupts. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void TIM_ITConfig(TIM_TypeDef *TIMx, u16 TIM_IT, FunctionalState Newstate) -{ - u16 TIM_IT_Enable = 0; - - TIM_IT_Enable = TIM_IT & TIM_IT_Enable_Mask; - - if(Newstate == ENABLE) - { - /* Update interrupt global source: overflow/undeflow, counter reset operation - or slave mode controller in reset mode */ - if((TIM_IT & TIM_IT_GlobalUpdate) == TIM_IT_GlobalUpdate) - { - TIMx->CR &= TIM_UFS_Reset; - } - /* Update interrupt source: counter overflow/underflow */ - else if((TIM_IT & TIM_IT_Update) == TIM_IT_Update) - { - TIMx->CR |= TIM_UFS_Set; - } - /* Select and enable the interrupts requests */ - TIMx->RSR |= TIM_IT_Enable; - TIMx->RER |= TIM_IT_Enable; - } - /* Disable the interrupts requests */ - else - { - TIMx->RSR &= ~TIM_IT_Enable; - TIMx->RER &= ~TIM_IT_Enable; - } -} - -/******************************************************************************* -* Function Name : TIM_PreloadConfig -* Description : Enables or disables TIM peripheral Preload register on OCRx. -* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. -* - TIM_Channel: specifies the TIM channel to be used. -* This parameter can be one of the following values: -* - TIM_Channel_1: TIM Channel 1 is used -* - TIM_Channel_2: TIM Channel 2 is used -* - TIM_Channel_ALL: TIM Channel 1and 2 are used -* - Newstate: new state of the TIMx peripheral Preload register -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void TIM_PreloadConfig(TIM_TypeDef *TIMx, u16 TIM_Channel, FunctionalState Newstate) -{ - if(Newstate == ENABLE) - { - switch (TIM_Channel) - { - case TIM_Channel_1: - TIMx->OMR1 |= TIM_PLD1_Set; - break; - - case TIM_Channel_2: - TIMx->OMR1 |= TIM_PLD2_Set; - break; - - case TIM_Channel_ALL: - TIMx->OMR1 |= TIM_PLD1_Set | TIM_PLD2_Set; - break; - - default: - break; - } - } - else - { - switch (TIM_Channel) - { - case TIM_Channel_1: - TIMx->OMR1 &= TIM_PLD1_Reset; - break; - - case TIM_Channel_2: - TIMx->OMR1 &= TIM_PLD2_Reset; - break; - - case TIM_Channel_ALL: - TIMx->OMR1 &= TIM_PLD1_Reset & TIM_PLD2_Reset; - break; - - default: - break; - } - } -} - -/******************************************************************************* -* Function Name : TIM_DMAConfig -* Description : Configures the TIM0’s DMA interface. -* Input : - TIM_DMASources: specifies the DMA Request sources. -* This parameter can be any combination of the following values: -* - TIM_DMASource_OC1: Output Compare 1 DMA source -* - TIM_DMASource_OC2: Output Compare 2 DMA source -* - TIM_DMASource_IC1: Input Capture 1 DMA source -* - TIM_DMASource_IC2: Input Capture 2 DMA source -* - TIM_DMASource_Update: Timer Update DMA source -* - TIM_OCRMState: the state of output compare request mode. -* This parameter can be one of the following values: -* - TIM_OCRMState_Enable -* - TIM_OCRMState_Disable -* - TIM_DMABase:DMA Base address. -* This parameter can be one of the following values: -* TIM_DMABase_CR, TIM_DMABase_SCR, TIM_DMABase_IMCR, -* TIM_DMABase_OMR1, TIM_DMABase_RSR, -* TIM_DMABase_RER, TIM_DMABase_ISR, TIM_DMABase_CNT, -* TIM_DMABase_PSC, TIM_DMABase_ARR, TIM_DMABase_OCR1, -* TIM_DMABase_OCR2, TIM_DMABase_ICR1, TIM_DMABase_ICR2 -* Output : None -* Return : None -*******************************************************************************/ -void TIM_DMAConfig(u16 TIM_DMASources, u16 TIM_OCRMState, u16 TIM_DMABase) -{ - /* Select the DMA requests */ - TIM0->RSR &= TIM_DMASources; - - /* Set the OCRM state */ - if(TIM_OCRMState == TIM_OCRMState_Enable) - { - TIM0->RSR |= TIM_OCRM_Set; - } - else - { - TIM0->RSR &= TIM_OCRM_Reset; - } - - /* Set the DMA Base address */ - TIM0->CR &= TIM_DBASE_Mask; - TIM0->CR |= TIM_DMABase; -} - -/******************************************************************************* -* Function Name : TIM_DMACmd -* Description : Enables or disables the TIM0’s DMA interface. -* Input : - TIM_DMASources: specifies the DMA Request sources. -* This parameter can be any combination of the following values: -* - TIM_DMASource_OC1: Output Compare 1 DMA source -* - TIM_DMASource_OC2: Output Compare 2 DMA source -* - TIM_DMASource_IC1: Input Capture 1 DMA source -* - TIM_DMASource_IC2: Input Capture 2 DMA source -* - TIM_DMASource_Update: Timer Update DMA source -* - Newstate: new state of the DMA Request sources. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void TIM_DMACmd(u16 TIM_DMASources, FunctionalState Newstate) -{ - if(Newstate == ENABLE) - { - TIM0->RER |= TIM_DMASources; - } - else - { - TIM0->RER &= ~TIM_DMASources; - } -} - -/******************************************************************************* -* Function Name : TIM_ClockSourceConfig -* Description : Configures the TIM clock source. -* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. -* - TIM_ClockSource: specifies the TIM clock source to be -* selected. -* This parameter can be one of the following values: -* - TIM_ClockSource_Internal: CK_TIM internal clock -* - TIM_ClockSource_TI11: External input pin TI1 -* connected to IC1 channel. -* - TIM_ClockSource_TI12: External input pin TI1 -* connected to IC2 channel. -* - TIM_ClockSource_TI22: External input pin TI2 -* connected to IC2 channel. -* - TIM_ClockSource_TI21: External input pin TI2 -* connected to IC1 channel. -* - TIM_ExtCLKEdge: specifies the External input signal edge. -* This parameter can be one of the following values: -* - TIM_ExtCLKEdge_Falling : Falling edge selected. -* - TIM_ExtCLKEdge_Rising : Rising edge selected. -* Output : None -* Return : None -*******************************************************************************/ -void TIM_ClockSourceConfig(TIM_TypeDef *TIMx, u16 TIM_ClockSource, - u16 TIM_ExtCLKEdge) -{ - if(TIM_ClockSource == TIM_ClockSource_Internal) - { - /* CK_TIM is used as clock source */ - TIMx->SCR &= TIM_SME_Reset & TIM_SlaveModeSelection_Mask & TIM_TriggerSelection_Mask; - } - else - /* Input Captures are used as TIM external clock */ - { - TIMx->SCR &= TIM_SME_Reset & TIM_SlaveModeSelection_Mask & TIM_TriggerSelection_Mask; - TIMx->SCR |= TIM_SMS_EXTCLK_Set | TIM_SME_Set; - - if((TIM_ClockSource == TIM_ClockSource_TI11) || - (TIM_ClockSource == TIM_ClockSource_TI21)) - /* Input Capture 1 is selected */ - { - /* Input capture Enable */ - TIMx->IMCR |= TIM_IC1_Enable; - TIMx->SCR |= TIM_TS_IC1_Set; - - if(TIM_ExtCLKEdge == TIM_ExtCLKEdge_Falling) - /* Set the corresponding polarity */ - { - TIMx->IMCR |= TIM_IC1P_Set; - } - else - { - TIMx->IMCR &= TIM_IC1P_Reset; - } - if(TIM_ClockSource == TIM_ClockSource_TI11) - { - /* External signal TI1 connected to IC1 channel */ - TIMx->IMCR &= TIM_IC1S_Reset; - } - else - { - /* External signal TI2 connected to IC1 channel */ - TIMx->IMCR |= TIM_IC1S_Set; - } - } - else - /* Input Capture 2 is selected */ - { - /* Input capture Enable */ - TIMx->IMCR |= TIM_IC2_Enable; - TIMx->SCR |= TIM_TS_IC2_Set; - - if(TIM_ExtCLKEdge == TIM_ExtCLKEdge_Falling) - /* Set the corresponding polarity */ - { - TIMx->IMCR |= TIM_IC2P_Set; - } - else - { - TIMx->IMCR &= TIM_IC2P_Reset; - } - if(TIM_ClockSource == TIM_ClockSource_TI22) - { - /* External signal TI2 connected to IC2 channel */ - TIMx->IMCR &= TIM_IC2S_Reset; - } - else - { - /* External signal TI1 connected to IC2 channel */ - TIMx->IMCR |= TIM_IC2S_Set; - } - } - } -} - -/******************************************************************************* -* Function Name : TIM_SetPrescaler -* Description : Sets the TIM prescaler value. -* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral -* - Prescaler: TIM prescaler new value. -* Output : None -* Return : None -*******************************************************************************/ -void TIM_SetPrescaler(TIM_TypeDef* TIMx, u16 Prescaler) -{ - TIMx->PSC = Prescaler; -} - -/******************************************************************************* -* Function Name : TIM_SetPeriod -* Description : Sets the TIM period value. -* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral -* - Period: TIM period new value. -* Output : None -* Return : None -*******************************************************************************/ -void TIM_SetPeriod(TIM_TypeDef* TIMx, u16 Period) -{ - TIMx->ARR = Period; -} - -/******************************************************************************* -* Function Name : TIM_SetPulse -* Description : Sets the TIM pulse value. -* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral -* - TIM_Channel: specifies the TIM channel to be used. -* This parameter can be one of the following values: -* - TIM_Channel_1: TIM Channel 1 is used -* - TIM_Channel_2: TIM Channel 2 is used -* - TIM_Channel_ALL: TIM Channel 1and 2 are used -* - Pulse: TIM pulse new value. -* Output : None -* Return : None -*******************************************************************************/ -void TIM_SetPulse(TIM_TypeDef* TIMx, u16 TIM_Channel, u16 Pulse) -{ - /* Set Channel 1 pulse value */ - if(TIM_Channel == TIM_Channel_1) - { - TIMx->OCR1 = Pulse; - } - /* Set Channel 2 pulse value */ - else if(TIM_Channel == TIM_Channel_2) - { - TIMx->OCR2 = Pulse; - } - /* Set Channel 1 and Channel 2 pulse values */ - else if(TIM_Channel == TIM_Channel_ALL) - { - TIMx->OCR1 = Pulse; - TIMx->OCR2 = Pulse; - } -} - -/******************************************************************************* -* Function Name : TIM_GetICAP1 -* Description : Gets the Input Capture 1 value. -* Input : TIMx: where x can be 0, 1 or 2 to select the TIM peripheral -* Output : None -* Return : Input Capture 1 Register value. -*******************************************************************************/ -u16 TIM_GetICAP1(TIM_TypeDef *TIMx) -{ - return TIMx->ICR1; -} - -/******************************************************************************* -* Function Name : TIM_GetICAP2 -* Description : Gets the Input Capture 2 value. -* Input : TIMx: where x can be 0, 1 or 2 to select the TIM peripheral -* Output : None -* Return : Input Capture 2 Register value -*******************************************************************************/ -u16 TIM_GetICAP2(TIM_TypeDef *TIMx) -{ - return TIMx->ICR2; -} - -/******************************************************************************* -* Function Name : TIM_GetPWMIPulse -* Description : Gets the PWM Input pulse value. -* Input : TIMx: where x can be 0, 1 or 2 to select the TIM peripheral -* Output : None -* Return : Input Capture 2 Register value -*******************************************************************************/ -u16 TIM_GetPWMIPulse(TIM_TypeDef *TIMx) -{ - return TIMx->ICR2; -} - -/******************************************************************************* -* Function Name : TIM_GetPWMIPeriod -* Description : Gets the PWM Input period value. -* Input : TIMx: where x can be 0, 1 or 2 to select the TIM peripheral -* Output : None -* Return : Input Capture 1 Register value -*******************************************************************************/ -u16 TIM_GetPWMIPeriod(TIM_TypeDef *TIMx) -{ - return TIMx->ICR1; -} - -/******************************************************************************* -* Function Name : TIM_DebugCmd -* Description : Enables or disables the specified TIM peripheral Debug control. -* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral -* - Newstate: new state of the TIMx Debug control. - This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void TIM_DebugCmd(TIM_TypeDef *TIMx, FunctionalState Newstate) -{ - if(Newstate == ENABLE) - { - TIMx->CR |= TIM_DBGC_Set; - } - else - { - TIMx->CR &= TIM_DBGC_Reset; - } -} - -/******************************************************************************* -* Function Name : TIM_CounterModeConfig -* Description : Specifies the Counter Mode to be used. -* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. -* - TIM_CounterMode: specifies the Counter Mode to be used -* This parameter can be one of the following values: -* - TIM_CounterMode_Up: TIM Up Counting Mode -* - TIM_CounterMode_Down: TIM Down Counting Mode -* - TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 -* - TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 -* - TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 -* Output : None -* Return : None -*******************************************************************************/ -void TIM_CounterModeConfig(TIM_TypeDef* TIMx, u16 TIM_CounterMode) -{ - /* Counter mode configuration */ - TIMx->CR &= TIM_CounterMode_Mask; - TIMx->CR |= TIM_CounterMode; -} - -/******************************************************************************* -* Function Name : TIM_ForcedOCConfig -* Description : Forces the TIM output waveform to active or inactive level. -* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. -* - TIM_Channel: specifies the TIM channel to be used. -* This parameter can be one of the following values: -* - TIM_Channel_1: Timer Channel 1 is used -* - TIM_Channel_2: Timer Channel 2 is used -* - TIM_Channel_ALL: Timer Channel 1 and 2 are used -* - TIM_ForcedAction: specifies the forced Action to be set to -* the output waveform. -* This parameter can be one of the following values: -* - TIM_ForcedAction_Active: Force active level on OCxREF -* - TIM_ForcedAction_InActive: Force inactive level on -* OCxREF. -* Output : None -* Return : None -*******************************************************************************/ -void TIM_ForcedOCConfig(TIM_TypeDef* TIMx, u16 TIM_Channel,u16 TIM_ForcedAction) -{ - /* Channel 1 Forced Output Compare mode configuration */ - if(TIM_Channel == TIM_Channel_1) - { - TIMx->OMR1 &= TIM_OC1C_Mask; - TIMx->OMR1 |= TIM_ForcedAction; - } - /* Channel 2 Forced Output Compare mode configuration */ - else - { - if(TIM_Channel == TIM_Channel_2) - { - TIMx->OMR1 &= TIM_OC2C_Mask; - TIMx->OMR1 |= (TIM_ForcedAction<<8); - } - /* Channel 1 and Channel 2 Forced Output Compare mode configuration */ - else - { - TIMx->OMR1 &= TIM_OC1C_Mask & TIM_OC2C_Mask; - TIMx->OMR1 |= TIM_ForcedAction |(TIM_ForcedAction<<8); - } - } -} - -/******************************************************************************* -* Function Name : TIM_ResetCounter -* Description : Re-intializes the TIM counter and generates an update of the -* registers. -* Input : TIMx: where x can be 0, 1 or 2 to select the TIM peripheral -* Output : None -* Return : None -*******************************************************************************/ -void TIM_ResetCounter(TIM_TypeDef* TIMx) -{ - /* Re-intialize the TIM counter */ - TIMx->CR |= TIM_COUNTER_Reset; -} - -/******************************************************************************* -* Function Name : TIM_SynchroConfig -* Description : Synchronizes two Timers in a specified mode. -* Input : - Master: specifies the peripheral master. -* This parameter can be one of the following values: -* PWM_Master, TIM0_Master, TIM1_Master or TIM2_Master. -* - Slave: specifies the peripheral slave. -* This parameter can be one of the following values: -* PWM_Slave, TIM0_Slave, TIM1_Slave or TIM2_Slave. -* - TIM_SynchroAction: specifies the synchronization Action to -* be used. -* This parameter can be one of the following values: -* - TIM_SynchroAction_Enable: The CNT_EN bit is used as TRGO -* - TIM_SynchroAction_Update: The Update event is used as TRGO -* - TIM_SynchroAction_Reset: The CNT_RST bit is used as TRGO -* - TIM_SynchroAction_OC: The OC1 signal is used as TRGO -* - TIM_SynchroMode: specifies the synchronization Mode to be used. -* This parameter can be one of the following values: -* - TIM_SynchroMode_Gated: Both start and stop of the -* counter is controlled. -* - TIM_SynchroMode_Trigger: Only the start of the -* counter is controlled. -* - TIM_SynchroMode_External: The rising edge of selected trigger -* clocks the counter. -* - TIM_SynchroMode_Reset: The rising edge of the selected trigger -* signal resets the counter and generates an update of the registers. -* Output : None -* Return : None -*******************************************************************************/ -void TIM_SynchroConfig(Master_TypeDef Master, Slave_TypeDef Slave, - u16 TIM_SynchroAction, u16 TIM_SynchroMode) -{ - switch (Slave) - { - case PWM_Slave: - { - PWM->SCR &= TIM_SME_Reset & TIM_TriggerSelection_Mask & TIM_SlaveModeSelection_Mask & - TIM_InternalTriggerSelection_Mask; - PWM->SCR |= TIM_SynchroMode | TIM_SME_Set; - - if(Master == TIM1_Master) - { - /* Set the internal trigger */ - PWM->SCR |= TIM_ITS_TIM1; - - /* Set the synchronization action */ - TIM1->CR &= TIM_MasterModeSelection_Mask; - TIM1->CR |= TIM_SynchroAction; - } - - else if(Master == TIM0_Master) - { - /* Set the internal trigger */ - PWM->SCR |= TIM_ITS_TIM0; - - /* Set the synchronization action */ - TIM0->CR &= TIM_MasterModeSelection_Mask; - TIM0->CR |= TIM_SynchroAction; - } - - else if(Master == TIM2_Master) - { - /* Set the internal trigger */ - PWM->SCR |= TIM_ITS_TIM2; - - /* Set the synchronization action */ - TIM2->CR &= TIM_MasterModeSelection_Mask; - TIM2->CR |= TIM_SynchroAction; - } - } - break; - - case TIM0_Slave: - { - TIM0->SCR &= TIM_SME_Reset & TIM_TriggerSelection_Mask & TIM_SlaveModeSelection_Mask & - TIM_InternalTriggerSelection_Mask; - TIM0->SCR |= TIM_SynchroMode | TIM_SME_Set; - - if(Master == PWM_Master) - { - /* Set the internal trigger */ - TIM0->SCR |= TIM_ITS_PWM; - - /* Set the synchronization action */ - PWM->CR &= TIM_MasterModeSelection_Mask; - PWM->CR |= TIM_SynchroAction; - } - - else if(Master == TIM1_Master) - { - /* Set the internal trigger */ - TIM0->SCR |= TIM_ITS_TIM1; - - /* Set the synchronization action */ - TIM1->CR &= TIM_MasterModeSelection_Mask; - TIM1->CR |= TIM_SynchroAction; - } - - else if(Master == TIM2_Master) - { - /* Set the internal trigger */ - TIM0->SCR |= TIM_ITS_TIM2; - - /* Set the synchronization action */ - TIM2->CR &= TIM_MasterModeSelection_Mask; - TIM2->CR |= TIM_SynchroAction; - } - } - break; - - case TIM1_Slave: - { - - TIM1->SCR &= TIM_SME_Reset & TIM_TriggerSelection_Mask & TIM_SlaveModeSelection_Mask & - TIM_InternalTriggerSelection_Mask; - TIM1->SCR |= TIM_SynchroMode | TIM_SME_Set; - - if(Master == PWM_Master) - { - /* Set the internal trigger */ - TIM1->SCR |= TIM_ITS_PWM; - - /* Set the synchronization action */ - PWM->CR &= TIM_MasterModeSelection_Mask; - PWM->CR |= TIM_SynchroAction; - } - else if(Master == TIM0_Master) - { - /* Set the internal trigger */ - TIM1->SCR |= TIM_ITS_TIM0; - - /* Set the synchronization action */ - TIM0->CR &= TIM_MasterModeSelection_Mask; - TIM0->CR |= TIM_SynchroAction; - } - - else if(Master == TIM2_Master) - { - /* Set the internal trigger */ - TIM1->SCR |= TIM_ITS_TIM2; - - /* Set the synchronization action */ - TIM2->CR &= TIM_MasterModeSelection_Mask; - TIM2->CR |= TIM_SynchroAction; - } - } - break; - - case TIM2_Slave: - { - - TIM2->SCR &= TIM_SME_Reset & TIM_TriggerSelection_Mask & TIM_SlaveModeSelection_Mask & - TIM_InternalTriggerSelection_Mask; - TIM2->SCR |= TIM_SynchroMode | TIM_SME_Set; - - if(Master == PWM_Master) - { - /* Internal trigger selection */ - TIM2->SCR |= TIM_ITS_PWM; - - /* Set the synchronization action */ - PWM->CR &= TIM_MasterModeSelection_Mask; - PWM->CR |= TIM_SynchroAction; - } - - else if(Master == TIM1_Master) - { - /* Internal trigger selection */ - TIM2->SCR |= TIM_ITS_TIM1; - - /* Set the synchronization action */ - TIM1->CR &= TIM_MasterModeSelection_Mask; - TIM1->CR |= TIM_SynchroAction; - } - - else if(Master == TIM0_Master) - { - /* Internal trigger selection */ - TIM2->SCR |= TIM_ITS_TIM0; - - /* Set the synchronization action */ - TIM0->CR &= TIM_MasterModeSelection_Mask; - TIM0->CR |= TIM_SynchroAction; - } - } - break; - - default: - break; - } -} - -/******************************************************************************* -* Function Name : TIM_GetFlagStatus -* Description : Checks whether the specified TIM flag is set or not. -* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. -* - TIM_FLAG: specifies the flag to check. -* This parameter can be one of the following values: -* - TIM_FLAG_IC1: Input Capture 1 Flag -* - TIM_FLAG_OC1: Output Compare 1 Flag -* - TIM_FLAG_Update: Timer update Flag -* - TIM_FLAG_IC2: Input Capture 2 Flag -* - TIM_FLAG_OC2: Output Compare 2 Flag -* Output : None -* Return : The new state of TIM_FLAG (SET or RESET). -*******************************************************************************/ -FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, u16 TIM_FLAG) -{ - if((TIMx->ISR & TIM_FLAG) != RESET ) - { - return SET; - } - else - { - return RESET; - } -} - -/******************************************************************************* -* Function Name : TIM_ClearFlag -* Description : Clears the TIMx's pending flags. -* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. -* - TIM_FLAG: specifies the flag bit to clear. -* This parameter can be any combination of the following values: -* - TIM_FLAG_IC1: Timer Input Capture 1 flag -* - TIM_FLAG_OC1: Timer Output Compare 1 flag -* - TIM_FLAG_Update: Timer update flag -* - TIM_FLAG_IC2: Timer Input Capture 2 flag -* - TIM_FLAG_OC2: Timer Output Compare 2 flag -* Output : None -* Return : None -*******************************************************************************/ -void TIM_ClearFlag(TIM_TypeDef* TIMx, u16 TIM_FLAG) -{ - /* Clear the flags */ - TIMx->ISR &= ~TIM_FLAG; -} - -/******************************************************************************* -* Function Name : TIM_GetITStatus -* Description : Checks whether the specified TIM interrupt has occurred or not. -* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. -* - TIM_IT: specifies the TIM interrupt source to check. -* This parameter can be one of the following values: -* - TIM_IT_IC1: Input Capture 1 interrupt -* - TIM_IT_OC1: Output Compare 1 interrupt -* - TIM_IT_Update: Timer update interrupt -* - TIM_IT_GlobalUpdate: Timer global update interrupt -* - TIM_IT_IC2: Input Capture 2 interrupt -* - TIM_IT_OC2: Output Compare 2 interrupt -* Output : None -* Return : The new state of TIM_IT(SET or RESET). -*******************************************************************************/ -ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, u16 TIM_IT) -{ - u16 TIM_IT_Check = 0; - - /* Calculates the pending bits to be checked */ - TIM_IT_Check = TIM_IT & TIM_IT_Clear_Mask; - - if((TIMx->ISR & TIM_IT_Check) != RESET ) - { - return SET; - } - else - { - return RESET; - } -} - -/******************************************************************************* -* Function Name : TIM_ClearITPendingBit -* Description : Clears the TIM's interrupt pending bits. -* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral. -* - TIM_IT: specifies the interrupt pending bit to clear. -* This parameter can be one of the following values: -* - TIM_IT_IC1: Input Capture 1 Interrupt -* - TIM_IT_OC1: Output Compare 1 Interrupt -* - TIM_IT_Update: Timer update Interrupt -* - TIM_IT_GlobalUpdate: Timer global update Interrupt -* - TIM_IT_IC2: Input Capture 2 Interrupt -* - TIM_IT_OC2: Output Compare 2 Interrupt -* Output : None -* Return : None -*******************************************************************************/ -void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, u16 TIM_IT) -{ - u16 TIM_IT_Clear = 0; - - /* Calculate the pending bits to be cleared */ - TIM_IT_Clear = TIM_IT & TIM_IT_Clear_Mask; - - /* Clear the pending bits */ - TIMx->ISR &= ~TIM_IT_Clear; -} - -/******************************************************************************* -* Function Name : OCM_ModuleConfig -* Description : Output Compare Module configuration -* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral -* - TIM_InitStruct: pointer to a TIM_InitTypeDef structure that -* contains the configuration information for the specified TIM -* peripheral. -* Output : None -* Return : None -*******************************************************************************/ -static void OCM_ModuleConfig(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct) -{ - u16 TIM_OCControl = 0x0000; - - if(TIM_InitStruct->TIM_Mode == TIM_Mode_OCTiming) - { - TIM_OCControl = TIM_OCControl_OCTiming; - } - else - { - if((TIM_InitStruct->TIM_Mode == TIM_Mode_OCActive) || - (TIM_InitStruct->TIM_Mode == TIM_Mode_OPM_Active)) - { - TIM_OCControl = TIM_OCControl_OCActive; - } - else - { - if(TIM_InitStruct->TIM_Mode == TIM_Mode_OCInactive) - { - TIM_OCControl = TIM_OCControl_OCInactive; - } - else - { - if((TIM_InitStruct->TIM_Mode == TIM_Mode_OCToggle) || - (TIM_InitStruct->TIM_Mode == TIM_Mode_OPM_Toggle)) - { - TIM_OCControl = TIM_OCControl_OCToggle; - } - else - { - TIM_OCControl = TIM_OCControl_PWM; - - } - } - } - } - - if(TIM_InitStruct->TIM_Channel == TIM_Channel_1) - { - /* Configure Channel 1 on Output Compare mode */ - TIMx->OMR1 &= TIM_OC1C_Mask; - TIMx->OMR1 |= TIM_OCControl|TIM_OC1_Enable; - TIMx->OMR1 |= TIM_PLD1_Set; - TIMx->OCR1 = TIM_InitStruct->TIM_Pulse1; - - /* Set the OC1 wave polarity */ - if(TIM_InitStruct->TIM_Polarity1 == TIM_Polarity1_Low) - { - TIMx->OMR1 |= TIM_OC1P_Set; - } - else - { - TIMx->OMR1 &= TIM_OC1P_Reset; - } - } - else - { - if(TIM_InitStruct->TIM_Channel == TIM_Channel_2) - { - /* Configure Channel 2 on Output Compare mode */ - TIMx->OMR1 &= TIM_OC2C_Mask; - TIMx->OMR1 |= TIM_OCControl<<8|TIM_OC2_Enable; - TIMx->OMR1 |= TIM_PLD2_Set; - TIMx->OCR2 = TIM_InitStruct->TIM_Pulse2; - - /* Set the OCB wave polarity */ - if(TIM_InitStruct->TIM_Polarity2 == TIM_Polarity2_Low) - { - TIMx->OMR1 |= TIM_OC2P_Set; - } - else - { - TIMx->OMR1 &= TIM_OC2P_Reset; - } - } - /* Configure Channel 1 and Channel 2 on Output Compare mode */ - else - { - TIMx->OMR1 &= TIM_OC1C_Mask & TIM_OC2C_Mask; - TIMx->OMR1 |= TIM_OCControl|(TIM_OCControl<<8)|TIM_OC1_Enable|TIM_OC2_Enable| - TIM_PLD1_Set|TIM_PLD2_Set; - - TIMx->OCR1 = TIM_InitStruct->TIM_Pulse1; - TIMx->OCR2 = TIM_InitStruct->TIM_Pulse2; - - /* Set the OC1 wave polarity */ - if(TIM_InitStruct->TIM_Polarity1 == TIM_Polarity1_Low) - { - TIMx->OMR1 |= TIM_OC1P_Set; - } - else - { - TIMx->OMR1 &= TIM_OC1P_Reset; - } - - /* Set the OC2 wave polarity */ - if(TIM_InitStruct->TIM_Polarity2 == TIM_Polarity2_Low) - { - TIMx->OMR1 |= TIM_OC2P_Set; - } - else - { - TIMx->OMR1 &= TIM_OC2P_Reset; - } - } - } -} - -/******************************************************************************* -* Function Name : ICAP_ModuleConfig -* Description : Input Capture Module configuration -* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral -* - TIM_InitStruct: pointer to a TIM_InitTypeDef structure that -* contains the configuration information for the specified TIM -* peripheral. -* Output : None -* Return : None -*******************************************************************************/ -static void ICAP_ModuleConfig(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct) -{ - if(TIM_InitStruct->TIM_Mode == TIM_Mode_PWMI) - { /* PWM input mode configuration */ - TIMx->SCR |= TIM_TS_IC1_Set|TIM_SMS_RESETCLK_Set|TIM_SME_Set; - - /* Channel 1 and channel 2 input selection */ - if(TIM_InitStruct->TIM_PWMI_ICSelection == TIM_PWMI_ICSelection_TI1) - { - TIMx->IMCR &= TIM_IC1S_Reset; - TIMx->IMCR |= TIM_IC2S_Set; - } - else - { - TIMx->IMCR |= TIM_IC1S_Set; - TIMx->IMCR &= TIM_IC2S_Reset; - } - - /* Channel polarity */ - if(TIM_InitStruct->TIM_PWMI_ICPolarity == TIM_PWMI_ICPolarity_Rising) - { - TIMx->IMCR &= TIM_IC1P_Reset; - TIMx->IMCR |= TIM_IC2P_Set; - } - else - { - TIMx->IMCR |= TIM_IC1P_Set; - TIMx->IMCR &= TIM_IC2P_Reset; - } - - /* Input capture Enable */ - TIMx->IMCR |= TIM_IC1_Enable |TIM_IC2_Enable; - } - else - { - if(TIM_InitStruct->TIM_Channel == TIM_Channel_1) - { - /* Input Capture 1 mode configuration */ - TIMx->SCR &= TIM_TriggerSelection_Mask & TIM_SlaveModeSelection_Mask; - TIMx->SCR |= TIM_TS_IC1_Set|TIM_SMS_RESETCLK_Set|TIM_SME_Set; - - /* Channel 1 input selection */ - if(TIM_InitStruct->TIM_IC1Selection == TIM_IC1Selection_TI1) - { - TIMx->IMCR &= TIM_IC1S_Reset; - } - else - { - TIMx->IMCR |= TIM_IC1S_Set; - } - /* Channel 1 polarity */ - if(TIM_InitStruct->TIM_IC1Polarity == TIM_IC1Polarity_Rising) - { - TIMx->IMCR &= TIM_IC1P_Reset; - } - else - { - TIMx->IMCR |= TIM_IC1P_Set; - } - - /* Input capture Enable */ - TIMx->IMCR |= TIM_IC1_Enable; - } - else - { - /* Input Capture 2 mode configuration */ - TIMx->SCR &= (TIM_TriggerSelection_Mask & TIM_SlaveModeSelection_Mask); - TIMx->SCR |= TIM_TS_IC2_Set|TIM_SMS_RESETCLK_Set|TIM_SME_Set; - - /* Channel 2 input selection */ - if(TIM_InitStruct->TIM_IC2Selection == TIM_IC2Selection_TI2) - { - TIMx->IMCR &= TIM_IC2S_Reset; - } - else - { - TIMx->IMCR |= TIM_IC2S_Set; - } - - /* Channel 2 polarity */ - if(TIM_InitStruct->TIM_IC2Polarity == TIM_IC2Polarity_Rising) - { - TIMx->IMCR &= TIM_IC2P_Reset; - } - else - { - TIMx->IMCR |= TIM_IC2P_Set; - } - - /* Input capture Enable */ - TIMx->IMCR |= TIM_IC2_Enable; - } - } -} - -/******************************************************************************* -* Function Name : Encoder_ModeConfig -* Description : Encoder Mode configuration -* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral -* - TIM_InitStruct: pointer to a TIM_InitTypeDef structure that -* contains the configuration information for the specified TIM -* peripheral. -* Output : None -* Return : None -*******************************************************************************/ -static void Encoder_ModeConfig(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct) -{ - /* Set Encoder mode */ - TIMx->SCR &= TIM_Encoder_Mask; - - if(TIM_InitStruct->TIM_Mode == TIM_Mode_Encoder1) - { - TIMx->SCR |= TIM_Encoder1_Set; - } - else if (TIM_InitStruct->TIM_Mode == TIM_Mode_Encoder2) - { - TIMx->SCR |= TIM_Encoder2_Set; - } - else - { - TIMx->SCR |= TIM_Encoder3_Set; - } - - /* Channel 1 input selection */ - if(TIM_InitStruct->TIM_IC1Selection == TIM_IC1Selection_TI2) - { - TIMx->IMCR |= TIM_IC1S_Set; - } - else - { - TIMx->IMCR &= TIM_IC1S_Reset; - } - - /* Channel 2 input selection */ - if(TIM_InitStruct->TIM_IC2Selection == TIM_IC2Selection_TI1) - { - TIMx->IMCR |= TIM_IC2S_Set; - } - else - { - TIMx->IMCR &= TIM_IC2S_Reset; - } - - /* Channel 1 polarity */ - if(TIM_InitStruct->TIM_IC1Polarity == TIM_IC1Polarity_Falling) - { - TIMx->IMCR |= TIM_IC1P_Set; - } - else - { - TIMx->IMCR &= TIM_IC1P_Reset; - } - - /* Channel 2 polarity */ - if(TIM_InitStruct->TIM_IC2Polarity == TIM_IC2Polarity_Falling) - { - TIMx->IMCR |= TIM_IC2P_Set; - } - else - { - TIMx->IMCR &= TIM_IC2P_Reset; - } -} -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_uart.c b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_uart.c deleted file mode 100644 index 5494ff335..000000000 --- a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_uart.c +++ /dev/null @@ -1,599 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_uart.c -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file provides all the UART software functions. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -#include "75x_uart.h" -#include "75x_mrcc.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* UART LIN Mask */ -#define UART_LIN_Disable_Mask 0xFEFF /* LIN Disable Mask */ -#define UART_LIN_Enable_Mask 0x0100 /* LIN Enable Mask */ - -/* UART Mask */ -#define UART_Enable_Mask 0x0001 /* UART Enable Mask */ -#define UART_Disable_Mask 0xFFFE /* UART Disable Mask */ - -/* UART LoopBack */ -#define UART_LoopBack_Disable_Mask 0xFF7F/* LoopBack Disable Mask */ -#define UART_LoopBack_Enable_Mask 0x0080/* LoopBack Enable Mask */ - -#define UART_WordLength_Mask 0xFF9F /* UART Word Length Mask */ -#define UART_Parity_Mask 0xFF79 /* UART Parity Mask */ -#define UART_HardwareFlowControl_Mask 0x3FFF /* UART Hardware Flow Control Mask */ -#define UART_TxRxFIFOLevel_Mask 0xFFC0 /* UART Tx Rx FIFO Level Mask */ -#define UART_LINBreakLength_Mask 0xE1FF /* UART LIN Break Length Mask */ -#define UART_BreakChar_Mask 0x0001 /* UART Break Character send Mask */ -#define UART_FLAG_Mask 0x1F /* UART Flag Mask */ -#define UART_Mode_Mask 0xFCFF /* UART Mode Mask */ -#define UART_RTSSET_Mask 0xF7FF /* RTS signal is high */ -#define UART_RTSRESET_Mask 0x0800 /* RTS signal is low */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/******************************************************************************* -* Function Name : UART_DeInit -* Description : Deinitializes the UARTx peripheral registers to their default -* reset values. -* Input : UARTx: where x can be 0,1 or 2 to select the UART peripheral. -* Output : None -* Return : None -*******************************************************************************/ -void UART_DeInit(UART_TypeDef* UARTx) -{ - /* Reset the UARTx registers values */ - if(UARTx == UART0) - { - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_UART0,ENABLE); - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_UART0,DISABLE); - } - else if(UARTx == UART1) - { - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_UART1,ENABLE); - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_UART1,DISABLE); - } - else if(UARTx == UART2) - { - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_UART2,ENABLE); - MRCC_PeripheralSWResetConfig(MRCC_Peripheral_UART2,DISABLE); - } -} - -/******************************************************************************* -* Function Name : UART_Init -* Description : Initializes the UARTx peripheral according to the specified -* parameters in the UART_InitStruct . -* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral. -* - UART_InitStruct: pointer to a UART_InitTypeDef structure -* that contains the configuration information for the -* specified UART peripheral. -* Output : None -* Return : None -*******************************************************************************/ -void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct) -{ - - u32 APBClock = 0; - u32 IntegerDivider = 0; - u32 FractionalDivider = 0; - MRCC_ClocksTypeDef MRCC_ClocksStatus; - - /* Clear the WLEN bits */ - UARTx->LCR &= UART_WordLength_Mask; - /* Set the WLEN bits according to UART_WordLength value */ - UARTx->LCR |= UART_InitStruct->UART_WordLength; - - /* Choose Stop Bits */ - if(UART_InitStruct->UART_StopBits == UART_StopBits_1) - { - /* One Stop Bit */ - UARTx->LCR &= UART_StopBits_1; - } - else - { - /* Two Stop Bits */ - UARTx->LCR |= UART_StopBits_2; - } - - /* Clear SPS, EPS and PEN bits */ - UARTx->LCR &= UART_Parity_Mask; - /* Set PS, EPS and PEN bits according to UART_Parity value */ - UARTx->LCR |= UART_InitStruct->UART_Parity; - - /* Configure the BaudRate --------------------------------------------------*/ - /* Get the APB frequency */ - MRCC_GetClocksStatus(&MRCC_ClocksStatus); - APBClock = MRCC_ClocksStatus.PCLK_Frequency; - - /* Determine the integer part */ - IntegerDivider = ((100) * (APBClock) / (16 * (UART_InitStruct->UART_BaudRate))); - UARTx->IBRD = IntegerDivider / 100; - - /* Determine the fractional part */ - FractionalDivider = IntegerDivider - (100 * (UARTx->IBRD)); - UARTx->FBRD = ((((FractionalDivider * 64) + 50) / 100)); - - /* Choose the Hardware Flow Control */ - /* Clear RTSEn and CTSEn bits */ - UARTx->CR &= UART_HardwareFlowControl_Mask; - /* Set RTSEn and CTSEn bits according to UART_HardwareFlowControl value */ - UARTx->CR |= UART_InitStruct->UART_HardwareFlowControl; - - /* Configure the UART mode */ - /* Clear TXE and RXE bits */ - UARTx->CR &= UART_Mode_Mask; - /* Set TXE and RXE bits according to UART_Mode value */ - UARTx->CR |= UART_InitStruct->UART_Mode; - - /* Enable or disable the FIFOs */ - /* Set the FIFOs Levels */ - if(UART_InitStruct->UART_FIFO == UART_FIFO_Enable) - { - /* Enable the FIFOs */ - UARTx->LCR |= UART_FIFO_Enable; - - /* Clear TXIFLSEL and RXIFLSEL bits */ - UARTx->IFLS &= UART_TxRxFIFOLevel_Mask; - - /* Set RXIFLSEL bits according to UART_RxFIFOLevel value */ - UARTx->IFLS |= (UART_InitStruct->UART_RxFIFOLevel << 3); - - /* Set TXIFLSEL bits according to UART_TxFIFOLevel value */ - UARTx->IFLS |= UART_InitStruct->UART_TxFIFOLevel; - } - else - { - /* Disable the FIFOs */ - UARTx->LCR &= UART_FIFO_Disable; - } -} - -/******************************************************************************* -* Function Name : UART_StructInit -* Description : Fills each UART_InitStruct member with its default value. -* Input : UART_InitStruct: pointer to a UART_InitTypeDef structure which -* will be initialized. -* Output : None -* Return : None -*******************************************************************************/ -void UART_StructInit(UART_InitTypeDef* UART_InitStruct) -{ - /* UART_InitStruct members default value */ - UART_InitStruct->UART_WordLength = UART_WordLength_8D; - UART_InitStruct->UART_StopBits = UART_StopBits_1; - UART_InitStruct->UART_Parity = UART_Parity_Odd ; - UART_InitStruct->UART_BaudRate = 9600; - UART_InitStruct->UART_HardwareFlowControl = UART_HardwareFlowControl_None; - UART_InitStruct->UART_Mode = UART_Mode_Tx_Rx; - UART_InitStruct->UART_FIFO = UART_FIFO_Enable; - UART_InitStruct->UART_TxFIFOLevel = UART_FIFOLevel_1_2; - UART_InitStruct->UART_RxFIFOLevel = UART_FIFOLevel_1_2; -} - -/******************************************************************************* -* Function Name : UART_Cmd -* Description : Enables or disables the specified UART peripheral. -* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral -* - NewState: new state of the UARTx peripheral. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void UART_Cmd(UART_TypeDef* UARTx, FunctionalState NewState) -{ - if (NewState == ENABLE) - { - /* Enable the selected UART by setting the UARTEN bit in the CR register */ - UARTx->CR |= UART_Enable_Mask; - } - else - { - /* Disable the selected UART by clearing the UARTEN bit in the CR register */ - UARTx->CR &= UART_Disable_Mask; - } -} - -/******************************************************************************* -* Function Name : UART_ITConfig -* Description : Enables or disables the specified UART interrupts. -* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral -* - UART_IT: specifies the UART interrupts sources to be -* enabled or disabled. This parameter can be any combination -* of the following values: -* - UART_IT_OverrunError: Overrun Error interrupt -* - UART_IT_BreakError: Break Error interrupt -* - UART_IT_ParityError: Parity Error interrupt -* - UART_IT_FrameError: Frame Error interrupt -* - UART_IT_ReceiveTimeOut: Receive Time Out interrupt -* - UART_IT_Transmit: Transmit interrupt -* - UART_IT_Receive: Receive interrupt -* - UART_IT_CTS: CTS interrupt -* - NewState: new state of the UARTx peripheral. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void UART_ITConfig(UART_TypeDef* UARTx, u16 UART_IT, FunctionalState NewState) -{ - if(NewState == ENABLE) - { - /* Enables the selected interrupts */ - UARTx->IMSC |= UART_IT; - } - else - { - /* Disables the selected interrupts */ - UARTx->IMSC &= ~UART_IT; - } -} - -/******************************************************************************* -* Function Name : UART_DMAConfig -* Description : Configures the UART0 DMA interface. -* Input : - UART0_DMAtransfer : specifies the configuration of DMA request. -* This parameter can be: -* - UART0_DMATransfer_Single: Single DMA transfer -* - UART0_DMATransfer_Burst: Burst DMA transfer -* - UART0_DMAOnError: specifies the DMA on error request. -* This parameter can be: -* - UART0_DMAOnError_Enable: DMA receive request enabled -* when the UART error interrupt is asserted. -* - UART0_DMAOnError_Disable: DMA receive request disabled -* when the UART error interrupt is asserted. -* Output : None -* Return : None -*******************************************************************************/ -void UART_DMAConfig(u16 UART0_DMATransfer, u16 UART0_DMAOnError) -{ - if(UART0_DMATransfer == UART0_DMATransfer_Single) - { - /* Configure the DMA request from the UART0 as single transfer */ - UART0->DMACR &= UART0_DMATransfer_Single; - } - else - { - UART0->DMACR |= UART0_DMATransfer_Burst; - } - - if(UART0_DMAOnError == UART0_DMAOnError_Enable) - { - UART0->DMACR &= UART0_DMAOnError_Enable; - } - else - { - UART0->DMACR |= UART0_DMAOnError_Disable; - } -} - -/******************************************************************************* -* Function Name : UART_DMACmd -* Description : Enables or disables the UART0’s DMA interface. -* Input : - UART0_DMAReq: specifies the DMA request. -* This parameter can be: -* - UART0_DMAReq_Tx: Transmit DMA request -* - UART0_DMAReq_Rx: Receive DMA request -* - NewState: new state of the UART0’s DMA request. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void UART_DMACmd(u16 UART0_DMAReq, FunctionalState NewState) -{ - if(UART0_DMAReq == UART0_DMAReq_Tx) - { - if(NewState == ENABLE) - { - UART0->DMACR |= UART0_DMAReq_Tx; - } - else - { - UART0->DMACR &= ~UART0_DMAReq_Tx; - } - } - else - { - if(NewState == ENABLE) - { - UART0->DMACR |= UART0_DMAReq_Rx; - } - else - { - UART0->DMACR &= ~UART0_DMAReq_Rx; - } - } -} - -/******************************************************************************* -* Function Name : UART_LoopBackConfig -* Description : Enables or disables LoopBack mode in UARTx. -* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral -* - NewState: new state of the UARTx’s LoopBack mode. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void UART_LoopBackConfig(UART_TypeDef* UARTx, FunctionalState NewState) -{ - if (NewState == ENABLE) - { - /* Enable the LoopBack mode of the specified UART */ - UARTx->CR |= UART_LoopBack_Enable_Mask; - } - else - { - /* Disable the LoopBack mode of the specified UART */ - UARTx->CR &= UART_LoopBack_Disable_Mask; - } -} - -/******************************************************************************* -* Function Name : UART_LINConfig -* Description : Sets the LIN break length. -* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral. -* - UART_LINBreakLength: Break length value. -* This parameter can be: -* - UART_LINBreakLength_10: 10 low bits -* - UART_LINBreakLength_11: 11 low bits -* - UART_LINBreakLength_12: 12 low bits -* - UART_LINBreakLength_13: 13 low bits -* - UART_LINBreakLength_14: 14 low bits -* - UART_LINBreakLength_15: 15 low bits -* - UART_LINBreakLength_16: 16 low bits -* - UART_LINBreakLength_17: 17 low bits -* - UART_LINBreakLength_18: 18 low bits -* - UART_LINBreakLength_19: 19 low bits -* - UART_LINBreakLength_20: 20 low bits -* Output : None -* Return : None -*******************************************************************************/ -void UART_LINConfig(UART_TypeDef* UARTx, u16 UART_LINBreakLength) -{ - /* Clear LBKLEN bits */ - UARTx->LCR &= UART_LINBreakLength_Mask; - - /* Set LBKLEN bits according to UART_LINBreakLength value */ - UARTx->LCR |= UART_LINBreakLength; -} - -/******************************************************************************* -* Function Name : UART_LINCmd -* Description : Enables or disables LIN master mode in UARTx. -* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral -* - NewState: new state of the UARTx’s LIN interface. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void UART_LINCmd(UART_TypeDef* UARTx, FunctionalState NewState) -{ - if(NewState == ENABLE) - { - /* Enable the LIN mode of the specified UART */ - UARTx->LCR |= UART_LIN_Enable_Mask; - } - else - { - /* Disable the LIN mode of the specified UART */ - UARTx->LCR &= UART_LIN_Disable_Mask; - } -} - -/******************************************************************************* -* Function Name : UART_SendData -* Description : Transmits a signle Byte of data through the UARTx peripheral. -* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral. -* - Data: the byte to transmit -* Output : None -* Return : None -*******************************************************************************/ -void UART_SendData(UART_TypeDef* UARTx, u8 Data) -{ - /* Transmit one byte */ - UARTx->DR = Data; -} - -/******************************************************************************* -* Function Name : UART_ReceiveData -* Description : Returns the most recent received Byte by the UARTx peripheral. -* Input : UARTx: where x can be 0,1 or 2 to select the UART peripheral. -* Output : None -* Return : The received data -*******************************************************************************/ -u8 UART_ReceiveData(UART_TypeDef* UARTx) -{ - /* Receive one byte */ - return ((u8)UARTx->DR); -} - -/******************************************************************************* -* Function Name : UART_SendBreak -* Description : Transmits break characters. -* Input : UARTx: where x can be 0,1 or 2 to select the UART peripheral. -* Output : None -* Return : None -*******************************************************************************/ -void UART_SendBreak(UART_TypeDef* UARTx) -{ - /* Send break characters */ - UARTx->BKR |= UART_BreakChar_Mask; -} - -/******************************************************************************* -* Function Name : UART_RTSConfig -* Description : Sets or Resets the RTS signal -* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral. -* - RTSState: new state of the RTS signal. -* This parameter can be: RTSSET or RTSRESET -* Output : None -* Return : None -*******************************************************************************/ -void UART_RTSConfig(UART_TypeDef* UARTx, UART_RTSTypeDef RTSState) -{ - if(RTSState == RTSRESET) - { - UARTx->CR |= UART_RTSRESET_Mask; - } - else if(RTSState == RTSSET) - { - UARTx->CR &= UART_RTSSET_Mask; - } -} - -/******************************************************************************* -* Function Name : UART_GetFlagStatus -* Description : Checks whether the specified UART flag is set or not. -* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral -* - UART_FLAG: specifies the flag to check. -* This parameter can be one of the following values: -* - UART_FLAG_OverrunError: Overrun error flag -* - UART_FLAG_Break: break error flag -* - UART_FLAG_ParityError: parity error flag -* - UART_FLAG_FrameError: frame error flag -* - UART_FLAG_TxFIFOEmpty: Transmit FIFO Empty flag -* - UART_FLAG_RxFIFOFull: Receive FIFO Full flag -* - UART_FLAG_TxFIFOFull: Transmit FIFO Full flag -* - UART_FLAG_RxFIFOEmpty: Receive FIFO Empty flag -* - UART_FLAG_Busy: Busy flag -* - UART_FLAG_CTS: CTS flag -* - UART_RawIT_OverrunError: Overrun Error interrupt flag -* - UART_RawIT_BreakError: Break Error interrupt flag -* - UART_RawIT_ParityError: Parity Error interrupt flag -* - UART_RawIT_FrameError: Frame Error interrupt flag -* - UART_RawIT_ReceiveTimeOut: ReceiveTimeOut interrupt flag -* - UART_RawIT_Transmit: Transmit interrupt flag -* - UART_RawIT_Receive: Receive interrupt flag -* - UART_RawIT_CTS: CTS interrupt flag -* Output : None -* Return : The new state of UART_FLAG (SET or RESET). -*******************************************************************************/ -FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, u16 UART_FLAG) -{ - u32 UARTReg = 0, FlagPos = 0; - u32 StatusReg = 0; - - /* Get the UART register index */ - UARTReg = UART_FLAG >> 5; - - /* Get the flag position */ - FlagPos = UART_FLAG & UART_FLAG_Mask; - - if(UARTReg == 1) /* The flag to check is in RSR register */ - { - StatusReg = UARTx->RSR; - } - else if (UARTReg == 2) /* The flag to check is in FR register */ - { - StatusReg = UARTx->FR; - } - else if(UARTReg == 3) /* The flag to check is in RIS register */ - { - StatusReg = UARTx->RIS; - } - - if((StatusReg & (1 << FlagPos))!= RESET) - { - return SET; - } - else - { - return RESET; - } -} - -/******************************************************************************* -* Function Name : UART_ClearFlag -* Description : Clears the UARTx’s pending flags. -* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral. -* - UART_FLAG: specifies the flag to clear. -* This parameter can be one of the following values: -* - UART_FLAG_OverrunError: Overrun error flag -* - UART_FLAG_Break: break error flag -* - UART_FLAG_ParityError: parity error flag -* - UART_FLAG_FrameError: frame error flag -* Output : None -* Return : None -*******************************************************************************/ -void UART_ClearFlag(UART_TypeDef* UARTx, u16 UART_FLAG) -{ - u8 FlagPos = 0; - - /* Get the flag position */ - FlagPos = UART_FLAG & UART_FLAG_Mask; - - /* Clear the sepecified flag */ - UARTx->RSR &= ~(1 << FlagPos); -} - -/******************************************************************************* -* Function Name : UART_GetITStatus -* Description : Checks whether the specified UART interrupt has occurred or not. -* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral. -* - UART_IT: specifies the interrupt source to check. -* This parameter can be one of the following values: -* - UART_IT_OverrunError: Overrun Error interrupt -* - UART_IT_BreakError: Break Error interrupt -* - UART_IT_ParityError: Parity Error interrupt -* - UART_IT_FrameError: Frame Error interrupt -* - UART_IT_ReceiveTimeOut: Receive Time Out interrupt -* - UART_IT_Transmit: Transmit interrupt -* - UART_IT_Receive: Receive interrupt -* - UART_IT_CTS: CTS interrupt -* Output : None -* Return : The new state of UART_IT (SET or RESET). -*******************************************************************************/ -ITStatus UART_GetITStatus(UART_TypeDef* UARTx, u16 UART_IT) -{ - if((UARTx->MIS & UART_IT) != RESET) - { - return SET; - } - else - { - return RESET; - } -} - -/******************************************************************************* -* Function Name : UART_ClearITPendingBit -* Description : Clears the UARTx’s interrupt pending bits. -* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral. -* - UART_IT: specifies the interrupt pending bit to clear. -* More than one interrupt can be cleared using the “|” operator. -* This parameter can be: -* - UART_IT_OverrunError: Overrun Error interrupt -* - UART_IT_BreakError: Break Error interrupt -* - UART_IT_ParityError: Parity Error interrupt -* - UART_IT_FrameError: Frame Error interrupt -* - UART_IT_ReceiveTimeOut: Receive Time Out interrupt -* - UART_IT_Transmit: Transmit interrupt -* - UART_IT_Receive: Receive interrupt -* - UART_IT_CTS: CTS interrupt -* Output : None -* Return : None -*******************************************************************************/ -void UART_ClearITPendingBit(UART_TypeDef* UARTx, u16 UART_IT) -{ - /* Clear the specified interrupt */ - UARTx->ICR = UART_IT; -} - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_wdg.c b/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_wdg.c deleted file mode 100644 index 812d627a9..000000000 --- a/Demo/ARM7_STR75x_IAR/STLibrary/src/75x_wdg.c +++ /dev/null @@ -1,244 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 75x_wdg.c -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file provides all the WDG software functions. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -#include "75x_wdg.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Registers reset value */ -#define WDG_Preload_Mask 0xFFFF -#define WDG_Prescaler_Mask 0xFF - -/* WDG Start/Stop counter */ -#define WDG_Counter_Start_Mask 0x0002 -#define WDG_Counter_Stop_Mask 0xFFFD - -/* WDG Sequence */ -#define WDG_KeyValue1_Mask 0xA55A -#define WDG_KeyValue2_Mask 0x5AA5 - -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/****************************************************************************** -* Function Name : WDG_DeInit -* Description : Deinitializes the WDG peripheral registers to their default -* reset values. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void WDG_DeInit(void) -{ - /* Reset all the WDG registers */ - WDG->CR = 0x0000; - WDG->PR = 0x00FF; - WDG->VR = 0xFFFF; - WDG->CNT = 0xFFFF; - WDG->SR = 0x0000; - WDG->MR = 0x0000; - WDG->KR = 0x0000; -} - -/******************************************************************************* -* Function Name : WDG_Init -* Description : Initializes WDG peripheral according to the specified -* parameters in the WDG_InitStruct. -* Input : WDG_InitStruct: pointer to a WDG_InitTypeDef structure that -* contains the configuration information for the WDG peripheral. -* Output : None -* Return : None -*******************************************************************************/ -void WDG_Init(WDG_InitTypeDef* WDG_InitStruct) -{ - /* Configure WDG Prescaler register value */ - WDG->PR = WDG_InitStruct->WDG_Prescaler; - - /* Configure WDG Pre-load register value */ - WDG->VR = WDG_InitStruct->WDG_Preload ; - - if(WDG_InitStruct->WDG_Mode == WDG_Mode_WDG) - { - /* Select WDG mode */ - WDG->CR |= WDG_Mode_WDG ; - } - else - { - /* Select Timer mode */ - WDG->CR &= WDG_Mode_Timer; - } -} - -/******************************************************************************* -* Function Name : WDG_StructInit -* Description : Fills each WDG_InitStruct member with its default value. -* Input : WDG_InitStruct : pointer to a WDG_InitTypeDef structure -* which will be initialized. -* Output : None -* Return : None -*******************************************************************************/ -void WDG_StructInit(WDG_InitTypeDef *WDG_InitStruct) -{ - /* Initialize mode */ - WDG_InitStruct->WDG_Mode = WDG_Mode_Timer; - - /* Initialize Preload */ - WDG_InitStruct->WDG_Preload = WDG_Preload_Mask ; - - /* Initialize Prescaler */ - WDG_InitStruct->WDG_Prescaler = WDG_Prescaler_Mask; -} - -/******************************************************************************* -* Function Name : WDG_Cmd -* Description : Enables or disables the WDG peripheral. -* Input : NewState: new state of the WDG peripheral. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void WDG_Cmd(FunctionalState NewState) -{ - if((WDG->CR & WDG_Mode_WDG) == 0) - { - /* Timer mode */ - if(NewState == ENABLE) - { - /* Start timer by setting SC bit in Control register */ - WDG->CR |= WDG_Counter_Start_Mask; - } - else - { - /* Stop timer by clearing SC bit in Control register */ - WDG->CR &= WDG_Counter_Stop_Mask; - } - } - else - { - /* Watchdog mode */ - if(NewState == ENABLE) - { - WDG->KR = WDG_KeyValue1_Mask; - WDG->KR = WDG_KeyValue2_Mask; - } - } -} - -/******************************************************************************* -* Function Name : WDG_ITConfig -* Description : Enables or disables the WDG End of Count(EC) interrupt. -* Input : Newstate: new state of the WDG End of Count(EC) interrupt. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void WDG_ITConfig(FunctionalState NewState) -{ - if(NewState == ENABLE) - { - /* Enable the End of Count interrupt */ - WDG->MR |= WDG_IT_EC; - } - else - { - /* Disable the End of Count interrupt */ - WDG->MR &= ~WDG_IT_EC; - } -} - -/******************************************************************************* -* Function Name : WDG_GetCounter -* Description : Gets the WDG’s current counter value. -* Input : None -* Output : None -* Return : The WDG current counter value -*******************************************************************************/ -u16 WDG_GetCounter(void) -{ - return WDG->CNT; -} - -/******************************************************************************* -* Function Name : WDG_GetFlagStatus -* Description : Checks whether the WDG End of Count(EC) flag is set or not. -* Input : None -* Output : None -* Return : The new state of WDG End of Count(EC) flag (SET or RESET). -*******************************************************************************/ -FlagStatus WDG_GetFlagStatus(void) -{ - if((WDG->SR & WDG_FLAG_EC) != RESET ) - { - return SET; - } - else - { - return RESET; - } -} - -/******************************************************************************* -* Function Name : WDG_ClearFlag -* Description : Clears the WDG’s End of Count(EC) pending flag. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void WDG_ClearFlag(void) -{ - /* Clear the EC pending bit */ - WDG->SR &= ~WDG_FLAG_EC; -} - -/******************************************************************************* -* Function Name : WDG_GetITStatus -* Description : Checks whether the WDG End of Count(EC) interrupt has -* occurred or not. -* Input : None -* Output : None -* Return : The new state of WDG End of Count(EC) interrupt (SET or RESET). -*******************************************************************************/ -ITStatus WDG_GetITStatus(void) -{ - if(((WDG->SR & WDG_IT_EC) != RESET )&&((WDG->MR & WDG_IT_EC) != RESET )) - { - return SET; - } - else - { - return RESET; - } -} - -/******************************************************************************* -* Function Name : WDG_ClearITPendingBit -* Description : Clears the WDG's End of Count(EC) interrupt pending bit. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void WDG_ClearITPendingBit(void) -{ - /* Clear the EC pending bit */ - WDG->SR &= ~WDG_IT_EC; -} - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR75x_IAR/STLibrary/src/lcd.c b/Demo/ARM7_STR75x_IAR/STLibrary/src/lcd.c deleted file mode 100644 index 3436bd22d..000000000 --- a/Demo/ARM7_STR75x_IAR/STLibrary/src/lcd.c +++ /dev/null @@ -1,1403 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : lcd.c -* Author : MCD Application Team -* Date First Issued : 03/10/2006 -* Description : This file includes the LCD driver for GXM12232-2SL liquid -* Crystal Display Module of STR75x-EVAL. -******************************************************************************** -* History: -* 07/17/2006 : V1.0 -* 03/10/2006 : V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -#include "lcd.h" - -/* Private typedef -----------------------------------------------------------*/ - - /* Peripherals InitStructure define */ -GPIO_InitTypeDef GPIO_InitStructure; - -/* Private define ------------------------------------------------------------*/ -#define LCD_GPIO_Pins 0x3FC00 -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - /* Global variable to set the written text color: used for LCD_Printf */ - TextColorMode_TypeDef TextMode = BlackText; - - /* ASCII Table: each character is 7 column (7dots large) on two pages (16dots high) */ - /* 7 column character: Two 8bit data to display one column*/ - const u8 AsciiDotsTable[1778] = { - /* ASCII 0 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 1 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 2 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 3 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 4 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 5 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 6 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 7 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 8 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 9 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - /* ASCII 10 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - /* ASCII 11 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 12 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 13 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - /* ASCII 14 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 15 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 16 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 17 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 18 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 19 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 20 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 21 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 22 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 23 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 24 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 25 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 26 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 27 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 28 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - /* ASCII 29 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - /* ASCII 30 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - /* ASCII 31 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - /* ASCII 32 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - /* ASCII 33 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x13,0xe0,0x00,0x00,0x00,0x00,0x00,0x00, - /* ASCII 34 */ 0x00,0x00,0x00,0xe0,0x00,0x20,0x00,0x00,0x00,0xe0,0x00,0x20,0x00,0x00, - /* ASCII 35 */ 0x00,0x00,0x35,0x00,0x0f,0x80,0x35,0x60,0x0f,0x80,0x05,0x60,0x00,0x00, - /* ASCII 36 */ 0x00,0x00,0x0d,0x80,0x0a,0x40,0x3a,0x60,0x06,0x40,0x00,0x00,0x00,0x00, - /* ASCII 37 */ 0x00,0x00,0x02,0x40,0x02,0xa0,0x0a,0x40,0x15,0x00,0x09,0x00,0x00,0x00, - /* ASCII 38 */ 0x00,0x00,0x0c,0x00,0x13,0x00,0x14,0x80,0x08,0x80,0x14,0x00,0x00,0x00, - /* ASCII 39 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xe0,0x00,0x00,0x00,0x00,0x00,0x00, - /* ASCII 40 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x1f,0x80,0x60,0x60,0x00,0x00,0x00,0x00, - /* ASCII 41 */ 0x00,0x00,0x00,0x00,0x60,0x60,0x1f,0x80,0x00,0x00,0x00,0x00,0x00,0x00, - /* ASCII 42 */ 0x00,0x00,0x00,0x40,0x03,0x40,0x00,0xe0,0x03,0x40,0x00,0x40,0x00,0x00, - /* ASCII 43 */ 0x02,0x00,0x02,0x00,0x02,0x00,0x1f,0xc0,0x02,0x00,0x02,0x00,0x02,0x00, - /* ASCII 44 */ 0x00,0x00,0x00,0x00,0x60,0x00,0x38,0x00,0x08,0x00,0x00,0x00,0x00,0x00, - /* ASCII 45 */ 0x00,0x00,0x02,0x00,0x02,0x00,0x02,0x00,0x02,0x00,0x02,0x00,0x00,0x00, - /* ASCII 46 */ 0x00,0x00,0x00,0x00,0x18,0x00,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - /* ASCII 47 */ 0x00,0x00,0x20,0x00,0x18,0x00,0x06,0x00,0x01,0x80,0x00,0x60,0x00,0x00, - /* ASCII 48 */ 0x00,0x00,0x0f,0xc0,0x10,0x20,0x10,0x20,0x10,0x20,0x0f,0xc0,0x00,0x00, - /* ASCII 49 */ 0x00,0x00,0x10,0x00,0x10,0x20,0x1f,0xe0,0x10,0x00,0x10,0x00,0x00,0x00, - /* ASCII 50 */ 0x00,0x00,0x18,0x40,0x14,0x20,0x12,0x20,0x11,0x20,0x18,0xc0,0x00,0x00, - /* ASCII 51 */ 0x00,0x00,0x08,0x40,0x10,0x20,0x11,0x20,0x11,0x20,0x0e,0xc0,0x00,0x00, - /* ASCII 52 */ 0x00,0x00,0x06,0x00,0x05,0x00,0x04,0xc0,0x14,0x20,0x1f,0xe0,0x14,0x00, - /* ASCII 53 */ 0x00,0x00,0x08,0x00,0x11,0xe0,0x11,0x20,0x11,0x20,0x0e,0x20,0x00,0x00, - /* ASCII 54 */ 0x00,0x00,0x0f,0x80,0x11,0x40,0x11,0x20,0x11,0x20,0x0e,0x20,0x00,0x00, - /* ASCII 55 */ 0x00,0x00,0x00,0x60,0x00,0x20,0x18,0x20,0x07,0x20,0x00,0xe0,0x00,0x00, - /* ASCII 56 */ 0x00,0x00,0x0e,0xc0,0x11,0x20,0x11,0x20,0x11,0x20,0x0e,0xc0,0x00,0x00, - /* ASCII 57 */ 0x00,0x00,0x11,0xc0,0x12,0x20,0x12,0x20,0x0a,0x20,0x07,0xc0,0x00,0x00, - /* ASCII 58 */ 0x00,0x00,0x00,0x00,0x19,0x80,0x19,0x80,0x00,0x00,0x00,0x00,0x00,0x00, - /* ASCII 59 */ 0x00,0x00,0x00,0x00,0x30,0x00,0x19,0x80,0x09,0x80,0x00,0x00,0x00,0x00, - /* ASCII 60 */ 0x02,0x00,0x05,0x00,0x05,0x00,0x08,0x80,0x10,0x40,0x10,0x40,0x00,0x00, - /* ASCII 61 */ 0x00,0x00,0x05,0x00,0x05,0x00,0x05,0x00,0x05,0x00,0x05,0x00,0x00,0x00, - /* ASCII 62 */ 0x10,0x40,0x10,0x40,0x08,0x80,0x05,0x00,0x05,0x00,0x02,0x00,0x00,0x00, - /* ASCII 63 */ 0x00,0x00,0x00,0x00,0x10,0x80,0x14,0x40,0x02,0x40,0x01,0x80,0x00,0x00, - /* ASCII 64 */ 0x00,0x00,0x1f,0xe0,0x20,0x10,0x23,0x10,0x24,0x90,0x17,0xe0,0x00,0x00, - /* ASCII 65 */ 0x10,0x00,0x1c,0x00,0x17,0xa0,0x04,0x60,0x17,0x80,0x1c,0x00,0x10,0x00, - /* ASCII 66 */ 0x10,0x20,0x1f,0xe0,0x11,0x20,0x11,0x20,0x11,0x20,0x0e,0xc0,0x00,0x00, - /* ASCII 67 */ 0x00,0x00,0x0f,0xc0,0x10,0x20,0x10,0x20,0x10,0x20,0x08,0x60,0x00,0x00, - /* ASCII 68 */ 0x10,0x20,0x1f,0xe0,0x10,0x20,0x10,0x20,0x08,0x40,0x07,0x80,0x00,0x00, - /* ASCII 69 */ 0x10,0x20,0x1f,0xe0,0x11,0x20,0x13,0xa0,0x10,0x20,0x18,0x60,0x00,0x00, - /* ASCII 70 */ 0x00,0x00,0x10,0x20,0x1f,0xe0,0x11,0x20,0x03,0xa0,0x00,0x20,0x00,0x60, - /* ASCII 71 */ 0x00,0x00,0x0f,0xc0,0x10,0x20,0x10,0x20,0x12,0x20,0x0e,0x60,0x02,0x00, - /* ASCII 72 */ 0x10,0x20,0x1f,0xe0,0x11,0x20,0x01,0x00,0x11,0x20,0x1f,0xe0,0x10,0x20, - /* ASCII 73 */ 0x00,0x00,0x10,0x20,0x10,0x20,0x1f,0xe0,0x10,0x20,0x10,0x20,0x00,0x00, - /* ASCII 74 */ 0x00,0x00,0x0e,0x00,0x10,0x20,0x10,0x20,0x0f,0xe0,0x00,0x20,0x00,0x00, - /* ASCII 75 */ 0x10,0x20,0x1f,0xe0,0x12,0x20,0x03,0x00,0x04,0xa0,0x18,0x60,0x10,0x20, - /* ASCII 76 */ 0x00,0x00,0x10,0x20,0x1f,0xe0,0x10,0x20,0x10,0x00,0x1c,0x00,0x00,0x00, - /* ASCII 77 */ 0x10,0x20,0x1f,0xe0,0x10,0xe0,0x03,0x00,0x10,0xe0,0x1f,0xe0,0x10,0x20, - /* ASCII 78 */ 0x10,0x20,0x1f,0xe0,0x10,0xe0,0x07,0x00,0x18,0x20,0x1f,0xe0,0x00,0x20, - /* ASCII 79 */ 0x00,0x00,0x0f,0xc0,0x10,0x20,0x10,0x20,0x10,0x20,0x0f,0xc0,0x00,0x00, - /* ASCII 80 */ 0x00,0x00,0x10,0x20,0x1f,0xe0,0x12,0x20,0x02,0x20,0x01,0xc0,0x00,0x00, - /* ASCII 81 */ 0x00,0x00,0x0f,0xc0,0x10,0x20,0x30,0x20,0x30,0x20,0x2f,0xc0,0x00,0x00, - /* ASCII 82 */ 0x10,0x20,0x1f,0xe0,0x12,0x20,0x02,0x20,0x06,0x20,0x09,0xc0,0x10,0x00, - /* ASCII 83 */ 0x00,0x00,0x18,0xc0,0x09,0x20,0x11,0x20,0x11,0x40,0x0e,0x60,0x00,0x00, - /* ASCII 84 */ 0x00,0x60,0x00,0x20,0x10,0x20,0x1f,0xe0,0x10,0x20,0x00,0x20,0x00,0x60, - /* ASCII 85 */ 0x00,0x20,0x0f,0xe0,0x10,0x20,0x10,0x00,0x10,0x20,0x0f,0xe0,0x00,0x20, - /* ASCII 86 */ 0x00,0x20,0x00,0xe0,0x07,0x20,0x18,0x00,0x07,0x20,0x00,0xe0,0x00,0x20, - /* ASCII 87 */ 0x00,0x20,0x0f,0xe0,0x10,0x20,0x0f,0x00,0x10,0x20,0x0f,0xe0,0x00,0x20, - /* ASCII 88 */ 0x10,0x20,0x18,0x60,0x04,0x80,0x03,0x00,0x04,0x80,0x18,0x60,0x10,0x20, - /* ASCII 89 */ 0x00,0x20,0x00,0x60,0x11,0xa0,0x1e,0x00,0x11,0xa0,0x00,0x60,0x00,0x20, - /* ASCII 90 */ 0x00,0x00,0x18,0x60,0x14,0x20,0x13,0x20,0x10,0xa0,0x18,0x60,0x00,0x00, - /* ASCII 91 */ 0x00,0x00,0x00,0x00,0x7f,0xe0,0x40,0x20,0x40,0x20,0x00,0x00,0x00,0x00, - /* ASCII 92 */ 0x00,0x00,0x00,0x20,0x01,0xc0,0x06,0x00,0x38,0x00,0x00,0x00,0x00,0x00, - /* ASCII 93 */ 0x00,0x00,0x00,0x00,0x40,0x20,0x40,0x20,0x7f,0xe0,0x00,0x00,0x00,0x00, - /* ASCII 94 */ 0x00,0x00,0x01,0x00,0x00,0x80,0x00,0x60,0x00,0x80,0x01,0x00,0x00,0x00, - /* ASCII 95 */ 0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00, - /* ASCII 96 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x40,0x00,0x00,0x00,0x00, - /* ASCII 97 */ 0x00,0x00,0x0d,0x00,0x12,0x80,0x12,0x80,0x12,0x80,0x1f,0x00,0x10,0x00, - /* ASCII 98 */ 0x10,0x20,0x1f,0xe0,0x11,0x00,0x10,0x80,0x10,0x80,0x0f,0x00,0x00,0x00, - /* ASCII 99 */ 0x00,0x00,0x0f,0x00,0x10,0x80,0x10,0x80,0x10,0x80,0x09,0x80,0x00,0x00, - /* ASCII 100 */ 0x00,0x00,0x0f,0x00,0x10,0x80,0x10,0x80,0x11,0x20,0x1f,0xe0,0x10,0x00, - /* ASCII 101 */ 0x00,0x00,0x0f,0x00,0x12,0x80,0x12,0x80,0x12,0x80,0x13,0x00,0x00,0x00, - /* ASCII 102 */ 0x00,0x00,0x10,0x80,0x1f,0xc0,0x10,0xa0,0x10,0xa0,0x10,0xa0,0x00,0x00, - /* ASCII 103 */ 0x00,0x00,0x0f,0x00,0x50,0x80,0x50,0x80,0x51,0x00,0x3f,0x80,0x00,0x80, - /* ASCII 104 */ 0x10,0x20,0x1f,0xe0,0x11,0x00,0x00,0x80,0x10,0x80,0x1f,0x00,0x10,0x00, - /* ASCII 105 */ 0x00,0x00,0x10,0x80,0x10,0x80,0x1f,0xa0,0x10,0x00,0x10,0x00,0x00,0x00, - /* ASCII 106 */ 0x00,0x00,0x40,0x80,0x40,0x80,0x40,0xa0,0x3f,0x80,0x00,0x00,0x00,0x00, - /* ASCII 107 */ 0x10,0x20,0x1f,0xe0,0x02,0x00,0x16,0x80,0x19,0x80,0x10,0x80,0x00,0x00, - /* ASCII 108 */ 0x00,0x00,0x10,0x00,0x10,0x20,0x1f,0xe0,0x10,0x00,0x10,0x00,0x00,0x00, - /* ASCII 109 */ 0x10,0x80,0x1f,0x80,0x10,0x80,0x1f,0x00,0x10,0x80,0x1f,0x00,0x10,0x00, - /* ASCII 110 */ 0x10,0x80,0x1f,0x80,0x11,0x00,0x00,0x80,0x10,0x80,0x1f,0x00,0x10,0x00, - /* ASCII 111 */ 0x00,0x00,0x0f,0x00,0x10,0x80,0x10,0x80,0x10,0x80,0x0f,0x00,0x00,0x00, - /* ASCII 112 */ 0x40,0x80,0x7f,0x80,0x51,0x00,0x10,0x80,0x10,0x80,0x0f,0x00,0x00,0x00, - /* ASCII 113 */ 0x00,0x00,0x0f,0x00,0x10,0x80,0x10,0x80,0x51,0x00,0x7f,0x80,0x40,0x80, - /* ASCII 114 */ 0x00,0x00,0x10,0x80,0x1f,0x80,0x11,0x00,0x10,0x80,0x10,0x80,0x00,0x00, - /* ASCII 115 */ 0x00,0x00,0x19,0x00,0x12,0x80,0x12,0x80,0x12,0x80,0x0d,0x80,0x00,0x00, - /* ASCII 116 */ 0x00,0x00,0x00,0x80,0x0f,0xc0,0x10,0x80,0x10,0x80,0x10,0x80,0x08,0x00, - /* ASCII 117 */ 0x00,0x80,0x0f,0x80,0x10,0x00,0x10,0x00,0x08,0x80,0x1f,0x80,0x10,0x00, - /* ASCII 118 */ 0x00,0x80,0x03,0x80,0x0c,0x80,0x10,0x00,0x0c,0x80,0x03,0x80,0x00,0x80, - /* ASCII 119 */ 0x00,0x80,0x0f,0x80,0x10,0x80,0x0e,0x00,0x10,0x80,0x0f,0x80,0x00,0x80, - /* ASCII 120 */ 0x10,0x80,0x19,0x80,0x06,0x00,0x06,0x00,0x19,0x80,0x10,0x80,0x00,0x00, - /* ASCII 121 */ 0x00,0x80,0x41,0x80,0x46,0x80,0x78,0x00,0x4c,0x80,0x03,0x80,0x00,0x80, - /* ASCII 122 */ 0x00,0x00,0x19,0x80,0x14,0x80,0x12,0x80,0x11,0x80,0x18,0x80,0x00,0x00, - /* ASCII 123 */ 0x00,0x00,0x00,0x00,0x04,0x00,0x3b,0xc0,0x40,0x20,0x00,0x00,0x00,0x00, - /* ASCII 124 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x3f,0xe0,0x00,0x00,0x00,0x00,0x00,0x00, - /* ASCII 125 */ 0x00,0x00,0x00,0x00,0x40,0x20,0x3b,0xc0,0x04,0x00,0x00,0x00,0x00,0x00, - /* ASCII 126 */ 0x00,0x00,0x04,0x00,0x02,0x00,0x04,0x00,0x04,0x00,0x02,0x00,0x00,0x00}; - -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/******************************************************************************* -* Function Name : LCD_DataLinesConfig -* Description : Configure data lines D0~D7 (P2.10~P2.17) in Input Floating mode -* for read from LCD or in Output Push-Pull mode for write on LCD -* Input : - Mode: specifies the configuration mode for data lines D0~D7 -* - Input: configure in Input Floating mode -* - Output: configure in Output Push-Pul mode -* Output : None -* Return : None -*******************************************************************************/ -void LCD_DataLinesConfig(DataConfigMode_TypeDef Mode) -{ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | - GPIO_Pin_14 | GPIO_Pin_15 | GPIO_Pin_16 | GPIO_Pin_17; - if (Mode == Input) - { - /* Configure D0~D7 lines (P2.10~2.17) in Input Floating mode */ - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - } - else - { - /* Configure D0~D7 lines (P2.10~2.17) in Output Push-Pull mode */ - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; - } - GPIO_Init(GPIO2, &GPIO_InitStructure); -} - -/******************************************************************************* -* Function Name : LCD_DataLinesWrite -* Description : Write a value on D0~D7 (P2.10~P2.17) -* Input : - GPIOx: GPIO port to write on. It could be -* - PortVal: value to write -* Output : None -* Return : None. -*******************************************************************************/ -void LCD_DataLinesWrite(GPIO_TypeDef* GPIOx, u32 PortVal) -{ - u32 Tmp = 0; - - /* Store the PM register value */ - Tmp = GPIO_GetPortMask(GPIOx); - /* Mask the corresponding GPIO pins */ - GPIO_PinMaskConfig(GPIOx, LCD_GPIO_Pins, DISABLE); - GPIO_PinMaskConfig(GPIOx, ~LCD_GPIO_Pins, ENABLE); - /* Write in the hole register */ - GPIO_Write(GPIOx, (PortVal<<10)); - - GPIO_PinMaskConfig(GPIOx, ~LCD_GPIO_Pins, DISABLE); - /* Return the initial PM register value */ - GPIO_PinMaskConfig(GPIOx, Tmp, ENABLE); - -} - -/******************************************************************************* -* Function Name : LCD_CtrlLinesConfig -* Description : Configure control lines E2, E1, RW, DI (P2.0~P2.3) in -* Output Push-Pull mode. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void LCD_CtrlLinesConfig(void) -{ - /* Configure E2, E1, RW, DI lines (P2.0~2.3) in Output Push-Pull mode */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; - GPIO_Init(GPIO2, &GPIO_InitStructure); -} - -/******************************************************************************* -* Function Name : LCD_CtrlLinesWrite -* Description : Set or reset control lines E2, E1, RW, DI (P2.0~P2.3). -* Input : - GPIOx: where x can be 0,1 or 2 to select the GPIO peripheral. -* - CtrlPins: the Control line. This parameter can be: -* - CtrlPin_E2: Enabe clock signal for Slave -* - CtrlPin_E1: Enabe clock signal for Master -* - CtrlPin_RW: Read/Write control line -* - CtrlPin_DI: -* Output : None -* Return : None -*******************************************************************************/ -void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, u32 CtrlPins, BitAction BitVal) -{ - /* Set or Reset the control line */ - if(BitVal != Bit_RESET) - { - GPIOx->PD |= CtrlPins; - } - else - { - GPIOx->PD &= ~CtrlPins; - } -} - -/******************************************************************************* -* Function Name : LCD_CheckMasterStatus -* Description : Check whether master LCD is busy or not -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void LCD_CheckMasterStatus(void) -{ - u8 MasterStatus = 0; - - /* Configure Data lines as Input */ - LCD_DataLinesConfig(Input); - /* Start the master read sequence */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_RW, Bit_SET); /* RW = 1 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_DI, Bit_RESET); /* DI = 0 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_SET); /* E1 = 1 */ - MasterStatus = GPIO_Read(GPIO2); - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ - - /* Wait until BF is cleared: D7 line */ - while ((MasterStatus & 0x20000)) - { - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_SET); /* E1 = 1 */ - MasterStatus = GPIO_Read(GPIO2); - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ - } -} - -/******************************************************************************* -* Function Name : LCD_CheckSlaveStatus -* Description : Check whether slave LCD is busy or not -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void LCD_CheckSlaveStatus(void) -{ - u8 SlaveStatus = 0; - - /* Configure Data lines as Input */ - LCD_DataLinesConfig(Input); - /* Start the slave read sequence */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_RW, Bit_SET); /* RW = 1 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_DI, Bit_RESET); /* DI = 0 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_SET); /* E2 = 1 */ - SlaveStatus = GPIO_Read(GPIO2); - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ - - /* Wait until BF is cleared: D7 line */ - while ((SlaveStatus & 0x20000)) - { - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_SET); /* E2 = 1 */ - SlaveStatus = GPIO_Read(GPIO2); - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ - } -} - -/******************************************************************************* -* Function Name : LCD_SendMasterCmd -* Description : Send one byte command to master LCD. -* Input : - Cmd: the user expected command to send to master LCD -* Output : None -* Return : None -*******************************************************************************/ -void LCD_SendMasterCmd(u8 Cmd) -{ - /* Check the master status */ - LCD_CheckMasterStatus(); - /* Configure Data lines as Output */ - LCD_DataLinesConfig(Output); - /* Start the master send command sequence */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_RW, Bit_RESET); /* RW = 0 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_DI, Bit_RESET); /* DI = 0 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_SET); /* E1 = 1 */ - /* Write master command */ - LCD_DataLinesWrite(GPIO2, (u32)Cmd); - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ -} - -/******************************************************************************* -* Function Name : LCD_SendSlaveCmd -* Description : Send one byte command to slave LCD -* Input : - Cmd: the user expected command to send to slave LCD. -* Output : None -* Return : None -*******************************************************************************/ -void LCD_SendSlaveCmd(u8 Cmd) -{ - /* Check the slave status */ - LCD_CheckSlaveStatus(); - /* Configure Data lines as Output */ - LCD_DataLinesConfig(Output); - /* Start the slave send command sequence */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_RW, Bit_RESET); /* RW = 0 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_DI, Bit_RESET); /* DI = 0 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_SET); /* E2 = 1 */ - /* Write slave command */ - LCD_DataLinesWrite(GPIO2, (u32)Cmd); - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ -} - -/******************************************************************************* -* Function Name : LCD_SendMasterData -* Description : Display one byte data to master LCD. -* Input : - Data: the user expected data to display on master LCD. -* Output : None -* Return : None -*******************************************************************************/ -void LCD_SendMasterData(u8 Data) -{ - /* Check the master status */ - LCD_CheckMasterStatus(); - /* Configure Data lines as Output */ - LCD_DataLinesConfig(Output); - /* Start the master send data sequence */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_RW, Bit_RESET); /* RW = 0 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_DI, Bit_SET); /* DI = 1 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_SET); /* E1 = 1 */ - /* Write data to the master */ - LCD_DataLinesWrite(GPIO2, (u32)Data); - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ -} - -/******************************************************************************* -* Function Name : LCD_ReadMasterData -* Description : Read master byte data displayed on master LCD. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -u32 LCD_ReadMasterData(void) -{ - u32 MasterData = 0; - - /* Check the master status */ - LCD_CheckMasterStatus(); - /* Configure Data lines as Input */ - LCD_DataLinesConfig(Input); - /* Start the master read data sequence */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_RW, Bit_SET); /* RW = 1 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_DI, Bit_SET); /* DI = 1 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_SET); /* E1 = 1 */ - /* Read data from the master */ - MasterData = ((GPIO_Read(GPIO2)&0x3FC00)>>10); - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ - /* Read the master returned data */ - return MasterData; -} - -/******************************************************************************* -* Function Name : LCD_SendSlaveData -* Description : Display one byte data to slave LCD. -* Input : - Data: the user expected data to display on slave LCD. -* Output : None -* Return : None -*******************************************************************************/ -void LCD_SendSlaveData(u8 Data) -{ - /* Check the slave status */ - LCD_CheckSlaveStatus(); - /* Configure Data lines as Output */ - LCD_DataLinesConfig(Output); - /* Start the slave send data sequence */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_RW, Bit_RESET); /* RW = 0 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_DI, Bit_SET); /* DI = 1 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_SET); /* E2 = 1 */ - /* Write data to the slave */ - LCD_DataLinesWrite(GPIO2, (u32)Data); - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ -} - -/******************************************************************************* -* Function Name : LCD_ReadSlaveData -* Description : Read slave byte data displayed on slave LCD. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -u32 LCD_ReadSlaveData(void) -{ - u32 SlaveData = 0; - - /* Check the slave status */ - LCD_CheckSlaveStatus(); - /* Configure Data lines as Input */ - LCD_DataLinesConfig(Input); - /* Start the slave read data sequence */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_RW, Bit_SET); /* RW = 1 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_DI, Bit_SET); /* DI = 1 */ - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_SET); /* E2 = 1 */ - /* Read data from the slave */ - SlaveData = ((GPIO_Read(GPIO2)&0x3FC00)>>10); - LCD_CtrlLinesWrite(GPIO2, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ - /* Read the slave returned data */ - return SlaveData; -} - -/******************************************************************************* -* Function Name : LCD_Init -* Description : Initialize master and slave LCD. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void LCD_Init(void) -{ - /* Enable GPIO Clock */ - MRCC_PeripheralClockConfig(MRCC_Peripheral_GPIO, ENABLE); - - /* Configure control lines signals as output mode */ - LCD_CtrlLinesConfig(); - - /* Master LCD Init */ - LCD_SendMasterCmd(SOFTWARE_RESET); - LCD_SendMasterCmd(DISPLAY_OFF); - LCD_SendMasterCmd(DYNAMIC_DRIVE); - LCD_SendMasterCmd(DUTY_CYCLE); - LCD_SendMasterCmd(CLOCKWISE_OUTPUT); - LCD_SendMasterCmd(READ_MODIFY_WRITE_OFF); - LCD_SendMasterCmd(START_COLUMN); /* Set master column address to 0 */ - LCD_SendMasterCmd(START_LINE); /* Set master display start line to 0 */ - LCD_SendMasterCmd(DISPLAY_ON ); - - /* Slave LCD Init */ - LCD_SendSlaveCmd(SOFTWARE_RESET); - LCD_SendSlaveCmd(DISPLAY_OFF); - LCD_SendSlaveCmd(DYNAMIC_DRIVE); - LCD_SendSlaveCmd(DUTY_CYCLE); - LCD_SendSlaveCmd(CLOCKWISE_OUTPUT); - LCD_SendSlaveCmd(READ_MODIFY_WRITE_OFF); - LCD_SendSlaveCmd(START_COLUMN ); /* Set slave column address to 0 */ - LCD_SendSlaveCmd(START_LINE); /* Set slave display start line to 0 */ - LCD_SendSlaveCmd(DISPLAY_ON); - - /* Clear LCD */ - LCD_Clear(); - /* Set current Page to 0 for Master and Slave LCDs */ - LCD_SetSlavePage(0); - LCD_SetMasterPage(0); -} - -/******************************************************************************* -* Function Name : LCD_SetSlavePage -* Description : Set the display page of slave LCD, the page range is 0 to 3, -* make sure the input will not exceed this range ,otherwise it -* will reach a undecided result. -* Input : - Page: specifies the expected display page of slave LCD -* Output : None -* Return : None -*******************************************************************************/ -void LCD_SetSlavePage(u8 Page) -{ - /* Set Slave page */ - LCD_SendSlaveCmd(0xB8|Page); -} - -/******************************************************************************* -* Function Name : LCD_SetMasterPage -* Description : Set the display page of master LCD, the page range is 0 to 3, -* make sure the input will not exceed this range ,otherwise it -* will reach a undecided result. -* Input : - Page: specifies the expected display page of master LCD -* Output : None -* Return : None -*******************************************************************************/ -void LCD_SetMasterPage(u8 Page) -{ - /* Set Master page */ - LCD_SendMasterCmd(0xB8|Page); -} - -/******************************************************************************* -* Function Name : SetAddress -* Description : Set the display column of slave LCD. Column range is 0 to 61. -* Input : - Address: specifies the expected display column of slave LCD -* Output : None -* Return : None -*******************************************************************************/ -void LCD_SetSlaveColumn(u8 Address) -{ - /* Set Slave column address */ - LCD_SendSlaveCmd(Address&0x7F); -} - -/******************************************************************************* -* Function Name : LCD_SetMasterColumn -* Description : Set the display column of master LCD. Column range is 0 to 61. -* Input : - Address: specifies the expected display column of slave LCD -* Output : None -* Return : None -*******************************************************************************/ -void LCD_SetMasterColumn(u8 Address) -{ - /* Set Master column address */ - LCD_SendMasterCmd(Address&0x7F); -} - -/******************************************************************************* -* Function Name : LCD_SetTextColor -* Description : Set the text color for LCD. -* Input : - TextColor: BlackText: character on black, bottom on white. -* WhiteText: character on white, bottom on black. -* Output : None -* Return : None -*******************************************************************************/ -void LCD_SetTextColor(TextColorMode_TypeDef TextColor) -{ - if(TextColor) - { - /* Set White Text color */ - TextMode=WhiteText; - } - else - { - /* Set Black Text color */ - TextMode=BlackText; - } -} - -/******************************************************************************* -* Function Name : LCD_Clear -* Description : Clear the Master and Slave LCDs display. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void LCD_Clear(void) -{ - u8 Page = 0, Column = 0; - - /* Clear master and slave LCDs page by page */ - for (Page=0; Page<4; Page++) - { - /* Set master and slave page by page */ - LCD_SetMasterPage(Page); - LCD_SetSlavePage(Page); - /* Set master and slave column address */ - LCD_SetMasterColumn(0); - LCD_SetSlaveColumn(0); - /* Send empty data to master and slave column address on the selected page */ - for (Column=0; Column<61; Column++) - { - LCD_SendSlaveData(0); - LCD_SendMasterData(0); - } - } -} - -/******************************************************************************* -* Function Name : LCD_ClearLine -* Description : Clear the selected line of the LCD. -* Input : - Line: the Line to clear. -* - Line1 (Page0&1): clear the first line -* - Line2 (Page2&3): clear the second line -* Output : None -* Return : None -*******************************************************************************/ -void LCD_ClearLine(u8 Line) -{ - u8 Page = 0, Column = 0; - - /* Clear the slected master and slave line */ - for (Page=Line; Page 121) - { - /* Return if column exceeded 121 */ - return; - } - if (X > 60) - { - /* To be displayed on slave LCD (Window = 1) */ - Window = 1; - /* Get the Slave relative start column */ - ActualColumn = X%61; - } - else - { - /* To be displayed on master LCD (Window = 0) */ - ActualColumn = X; - } - - /* Switch window, display the character upper part */ - if (Window) - { - /* Display it on slave LCD */ - LCD_SetSlavePage(Line); - LCD_SetSlaveColumn(ActualColumn); - LCD_SendSlaveData(Bmp[i]); - } - else - { - /* Display it on master LCD */ - LCD_SetMasterPage(Line); - LCD_SetMasterColumn(ActualColumn); - LCD_SendMasterData(Bmp[i]); - } - /* Switch window, diplay the character lower part */ - if (Window) - { - /* Display it on slave LCD */ - LCD_SetSlavePage(Line+1); - LCD_SetSlaveColumn(ActualColumn); - LCD_SendSlaveData(Bmp[i+1]); - } - else - { - /* Display it on master LCD */ - LCD_SetMasterPage(Line+1); - LCD_SetMasterColumn(ActualColumn); - LCD_SendMasterData(Bmp[i+1]); - } - /* Increment by 2 the character table index */ - i+=2; - } -} - -/******************************************************************************* -* Function Name : LCD_DisplayChar -* Description : Display one character (7dots large, 16dots high). -* Note: -* the LCD can only display two line character,so page 0 and 1 -* is to display the first line, page2 and page 3 is to display -* the second line. -* Input : - Line: the Line where to display the character. -* - Line1 (Page0&1): display character on the first line -* - Line2 (Page2&3): display character on the second line -* - Column: start column address. -* - Ascii: character ascii code. -* - CharMode: BlackText: character on black, bottom on white. -* WhiteText: character on white, bottom on black. -* Output : None -* Return : None -*******************************************************************************/ -void LCD_DisplayChar(u8 Line, u8 Column, u8 Ascii, TextColorMode_TypeDef CharMode) -{ - u8 DotBuffer[14], i = 0; - - /* Display the character lower and upper 8bit parts (2*7columns) */ - for (i=0;i<14;i++) - { - /* Character displayed as white Text on black buttom */ - if(CharMode) - { - if(i%2==0) - { - DotBuffer[i] = ~AsciiDotsTable[Ascii*14+i+1]; - } - else - { - DotBuffer[i] = ~AsciiDotsTable[Ascii*14+i-1]; - } - } - /* Character displayed as black Text on white buttom */ - else - { - if(i%2==0) - { - DotBuffer[i] = AsciiDotsTable[Ascii*14+i+1]; - } - else - { - DotBuffer[i] = AsciiDotsTable[Ascii*14+i-1]; - } - } - } - /* Display the asc code after conversion */ - LCD_DrawChar(Line, Column, 7, DotBuffer); -} - -/******************************************************************************* -* Function Name : LCD_HexToAsciiLow -* Description : This function is used to convert the low nibble of an -* unsigned byte (0-F hex) to ASCII. -* Input : - byte: byte to convert to ASCII. -* Output : None -* Return : ASCII value result of the conversion. -*******************************************************************************/ -u8 LCD_HexToAsciiLow(u8 byte) -{ - /* Keep lower nibble only */ - byte = byte & 0x0F; - /* If the ascii is a number */ - if (byte <= 0x09) - { - /* Add 0x30 to its ascii */ - return(byte + 0x30); - } - else - { - /* Add 0x37 to its ascii */ - return (byte + 0x37); - } -} - -/******************************************************************************* -* Function Name : LCD_HexToAsciiHigh -* Description : This function is used to convert the high nibble of an -* unsigned byte (0-F hex) to ASCII. -* Input : - byte: byte to convert to ASCII. -* Output : None -* Return : ASCII value result of the conversion. -*******************************************************************************/ -u8 LCD_HexToAsciiHigh(u8 byte) -{ - /* Keep upper nibble only */ - byte = byte & 0xF0; - byte = byte >> 4; - /* If the ascii is a number */ - if (byte <= 0x09) - { - /* Add 0x30 to display its ascii */ - return(byte + 0x30); - } - else - { - /* Add 0x37 to display its ascii */ - return (byte + 0x37); - } -} - -/******************************************************************************* -* Function Name : LCD_DisplayString -* Description : This function is used to display a 17char max string of -* characters on the LCD display on the selected line. -* Note: -* this function is the user interface to use the LCD driver. -* Input : - *ptr: pointer to string to display on LCD. -* - Line: the Line where to display the character. -* - Line1 (Page0&1): display character on the first line -* - Line2 (Page2&3): display character on the second line -* Output : None -* Return : None -*******************************************************************************/ -void LCD_DisplayString(u8 Line, u8 *ptr, TextColorMode_TypeDef CharMode) -{ - u8 RefColumn = 0, i = 0; - - /* Send the string character by character on lCD */ - while ((*ptr!=0)&(i<17)) - { - /* Display one character on LCD */ - LCD_DisplayChar(Line, RefColumn, *ptr, CharMode); - /* Increment the column position by 7 */ - RefColumn+=7; - /* Point on the next character */ - ptr++; - /* Increment the character counter */ - i++; - /* If we reach the maximum Line character */ - if(i==17) - { - LCD_DisplayChar(Line, RefColumn-1, 0x1f, CharMode); /* Add missed columns */ - } - } -} - -/******************************************************************************* -* Function Name : LCD_Printf -* Description : This function is used to display a string of characters -* on the LCD display. -* Note: -* this function is the user interface to use the LCD driver. -* Input : - *ptr: pointer to string to display on LCD. -* Output : None -* Return : None -*******************************************************************************/ -void LCD_Printf(u8 *ptr, ...) -{ - u8 RefColumn = 0, RefPage = 0, i = 0, c1 = 0; - u16 var = 0, c2 = 0, c3 = 0, c4 = 0, c5 = 0; - u32 WordVar = 0; - - /* Store pointer on LCD_Printf second parameter (String) */ - u8 *var_ptr=(u8 *)(&ptr+1); - - /* Send String */ - while (*ptr != 0) - { - c1 = *ptr; - /* Limited to AsciiDotsTable code table */ - if(c1 <= 128) - { - /* Carriage return */ - if ( *ptr == '\r') - { - ptr++; - RefColumn = 0; - } - /* Jump to Line2 */ - else if( *ptr == '\n') - { - /* Point on the string to display */ - ptr++; - /* Clear Line2 */ - LCD_ClearLine(Line2); - /* Point on first Line2 column */ - RefColumn = 0; - /* Increment RefPage by 2 */ - RefPage+=2; - } - /* Display value on the passed format */ - else if( *ptr == '%') - { - ptr++; - /* Display decimal value */ - if (*ptr == 'd') - { - ptr++; - /* Get the word value to display */ - WordVar = ((*var_ptr)|(*(var_ptr+1)<<8)|(*(var_ptr+2)<<16)); - c1=WordVar/10000; - c2=(WordVar%10000)/1000; - c3=(WordVar%1000)/100; - c4=(WordVar%100)/10; - c5=(WordVar%10); - /* Display the ten miles digit */ - if (c1!=0) - { - LCD_DisplayChar(RefPage, RefColumn, c1+0x30, TextMode); - RefColumn+=7; - } - /* Display the miles digit */ - if (!((c1==0)&(c2==0))) - { - LCD_DisplayChar(RefPage, RefColumn, c2+0x30, TextMode); - RefColumn+=7; - } - /* Display the hundred digit */ - if (!((c1==0)&(c2==0)&(c3==0))) - { - LCD_DisplayChar(RefPage, RefColumn, c3+0x30, TextMode); - RefColumn+=7; - } - /* Display the tens digit */ - if (!((c1==0)&(c2==0)&(c3==0)&(c4==0))) - { - LCD_DisplayChar(RefPage, RefColumn, c4+0x30, TextMode); - RefColumn+=7; - } - /* Display the rest */ - LCD_DisplayChar(RefPage, RefColumn, c5+0x30, TextMode); - RefColumn+=7; - } - /* Display 16bits Hex value */ - else if (*ptr == 'x') - { - ptr++; - /* Display 8bits MSB */ - var_ptr = var_ptr +1; - var = *var_ptr; - c1 = LCD_HexToAsciiHigh(var); - LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); - RefColumn+=7; - c1 = LCD_HexToAsciiLow(var); - LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); - RefColumn+=7; - /* Display 8bits LSB */ - var_ptr = var_ptr -1; - var = *var_ptr; - var_ptr = var_ptr +4; - c1 = LCD_HexToAsciiHigh(var); - LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); - RefColumn+=7; - c1 = LCD_HexToAsciiLow(var); - LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); - RefColumn+=7; - } - /* Display 32bits Hex value */ - else if (*ptr == 'w') - { - ptr++; - /* Display 16bits MSB */ - var_ptr = var_ptr +3; - var = *var_ptr; - c1 = LCD_HexToAsciiHigh(var); - LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); - RefColumn+=7; - c1 = LCD_HexToAsciiLow(var); - LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); - RefColumn+=7; - var_ptr = var_ptr -1; - var = *var_ptr; - c1 = LCD_HexToAsciiHigh(var); - LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); - RefColumn+=7; - c1 = LCD_HexToAsciiLow(var); - LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); - RefColumn+=7; - /* Display 16bits LSB */ - var_ptr = var_ptr -1; - var = *var_ptr; - var_ptr = var_ptr +4; - c1 = LCD_HexToAsciiHigh(var); - LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); - RefColumn+=7; - c1 = LCD_HexToAsciiLow(var); - LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); - RefColumn+=7; - var_ptr = var_ptr -5; - var = *var_ptr; - var_ptr = var_ptr +4; - c1 = LCD_HexToAsciiHigh(var); - LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); - RefColumn+=7; - c1 = LCD_HexToAsciiLow(var); - LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); - RefColumn+=7; - } - else - { - /* Display '%' character which is followed by (d, x or w) */ - ptr--; - c1 = *ptr; - LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); - RefColumn+=7; - ptr++; - i++; - if(i==17) - { - /* Add missed columns */ - LCD_DisplayChar(RefPage, RefColumn-1, 0x1f, TextMode); - RefColumn = 0; - RefPage+=2; - } - } - } - else - { - /* Display characters different from (\r, \n, %) */ - LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); - RefColumn+=7; - ptr++; - i++; - if(i==17) - { - /* Add missed columns */ - LCD_DisplayChar(RefPage, RefColumn-1, 0x1f, TextMode); - LCD_ClearLine(Line2); - RefColumn = 0; - RefPage+=2; - } - } - } - } - /* Display spaces if string doesn't reach the max LCD characters size */ - while(RefColumn<119) - { - /* Display Spaces */ - LCD_DisplayChar(RefPage, RefColumn, 0x20, TextMode); - RefColumn+=7; - /* Add missed columns */ - LCD_DisplayChar(RefPage, RefColumn, 0x1f, TextMode); - } -} - -/******************************************************************************* -* Function Name : LCD_DrawMasterGraphic -* Description : Draw a Graphic image on master LCD. -* Input : - Bmp: the pointer of the dot matrix data. -* Output : None -* Return : None. -*******************************************************************************/ -void LCD_DrawMasterGraphic(u8 *Bmp) -{ - u8 j = 0, k = 0, ActPage = 0; - - /* Draw graphic on master: 61 Column *4 Pages */ - while(j<244) - { - /* Draw on master page by page */ - LCD_SetMasterPage(ActPage); - for(k=0; k<61; k++) - { - LCD_SetMasterColumn(k); - LCD_SendMasterData(*Bmp++); - j++; - } - ActPage++; - } -} - -/******************************************************************************* -* Function Name : LCD_DrawSlaveGraphic -* Description : Draw a Graphic image on slave LCD. -* Input : - Bmp: the pointer of the dot matrix data. -* Output : None -* Return : None. -*******************************************************************************/ -void LCD_DrawSlaveGraphic(u8 *Bmp) -{ - u8 j = 0, k = 0, ActPage = 0; - - /* Draw graphic on slave: 61 Column *4 Pages */ - while(j<244) - { - /* Draw on slave page by page */ - LCD_SetSlavePage(ActPage); - for(k=0; k<61; k++) - { - LCD_SetSlaveColumn(k); - LCD_SendSlaveData(*Bmp++); - j++; - } - ActPage++; - } -} - -/******************************************************************************* -* Function Name : LCD_DrawGraphic -* Description : Draw a Graphic image on LCD. -* Input : - Bmp: the pointer of the dot matrix data. -* Output : None -* Return : None. -*******************************************************************************/ -void LCD_DrawGraphic(u8 *Bmp) -{ - u8 Pos = 0, ActPage = 0; - u16 j = 0, k = 0; - - /* Draw graphic on LCD: 122 Column *4 Pages */ - while(j<488) - { - if(!Pos) - { - /* Draw on master page by page */ - LCD_SetMasterPage(ActPage); - for(k=0; k<61; k++) - { - LCD_SetMasterColumn(k); - LCD_SendMasterData(*Bmp++); - j++; - } - Pos=1; - } - else - { - /* Draw on slave page by page */ - LCD_SetSlavePage(ActPage); - for(k=0; k<61; k++) - { - LCD_SetSlaveColumn(k); - LCD_SendSlaveData(*Bmp++); - j++; - } - ActPage++; - Pos=0; - } - } -} - -/******************************************************************************* -* Function Name : LCD_ScrollGraphic -* Description : Scroll a Graphic image on LCD. -* Input : - Bmp: the pointer of the dot matrix data. -* - nCount: specifies the delay time length. -* Output : None -* Return : None. -*******************************************************************************/ -void LCD_ScrollGraphic(u8 *Bmp, u32 nCount) -{ - u8 Pos = 0, ActPage = 0; - u16 j = 0, k = 0; - u32 Counter = 0; - - /* Draw graphic on LCD: 122 Column *4 Pages */ - while(j<488) - { - if(!Pos) - { - /* Draw on master page by page */ - LCD_SetMasterPage(ActPage); - for(k=0; k<61; k++) - { - LCD_SetMasterColumn(k); - LCD_SendMasterData(*Bmp++); - Counter = nCount; - /* Set a delay */ - for(; Counter != 0; Counter--); - j++; - } - Pos=1; - } - else - { - /* Draw on slave page by page */ - LCD_SetSlavePage(ActPage); - for(k=0; k<61; k++) - { - LCD_SetSlaveColumn(k); - Counter = nCount; - /* Set a delay */ - for(; Counter != 0; Counter--); - LCD_SendSlaveData(*Bmp++); - j++; - } - ActPage++; - Pos=0; - } - } -} - -/******************************************************************************* -* Function Name : LCD_DrawPixel -* Description : Draw a Graphic image on slave LCD. -* Input : - XPos: the dot line number of the pixel. -* - 1->61 : displayed on master LCD -* - 62->122: displayed on slave LCD -* - YPos: column address of the pixel from 1->32. -* - Mode: Dot_On: Pixel turned on (black). -* Dot_Off: Pixel turned off (black). -* Output : None -* Return : None. -*******************************************************************************/ -void LCD_DrawPixel(u8 XPos, u8 YPos, DotMode_TypeDef Mode) -{ - u8 Page = 0, Position = 0; - u16 Mask = 0; - u32 MasterDataIn = 0, MasterDataOut = 0, SlaveDataIn = 0, SlaveDataOut = 0; - - /* Pixel page */ - Page = (XPos-1)/8; - /* Pixel column */ - Position = (YPos-1)/61; /* 0:Master, 1:Slave */ - /* Mask for the pixel */ - Mask= 1<<((XPos-1)%8); - /* If Position=0 draw pixel on master LCD */ - if(!Position) - { - LCD_SetMasterPage(Page); - LCD_SetMasterColumn(YPos-1); - MasterDataIn = LCD_ReadMasterData(); - MasterDataIn = LCD_ReadMasterData(); - LCD_SetMasterColumn(YPos-1); - if(Mode==Dot_On) - { - MasterDataOut = MasterDataIn | Mask; - } - else - { - MasterDataOut = MasterDataIn & (~Mask); - } - LCD_SendMasterData(MasterDataOut); - } - /* If Position=1 draw pixel on slave LCD */ - else - { - LCD_SetSlavePage(Page); - LCD_SetSlaveColumn(YPos-62); - SlaveDataIn = LCD_ReadSlaveData(); - SlaveDataIn = LCD_ReadSlaveData(); - LCD_SetSlaveColumn(YPos-62); - if(Mode==Dot_On) - { - SlaveDataOut = SlaveDataIn | Mask; - } - else - { - SlaveDataOut = SlaveDataIn & (~Mask); - } - LCD_SendSlaveData(SlaveDataOut); - } -} - -/******************************************************************************* -* Function Name : LCD_DrawLine -* Description : Draw a line on master and slave LCDs. -* Input : - XPos1: the dot line number of the source point . -* - XPos2: the dot line number of the destination point . -* - YPos1: the dot column number of the source point. -* - YPos2: the dot column number of the destination point. -* Output : None -* Return : None. -*******************************************************************************/ -void LCD_DrawLine(u8 XPos1, u8 YPos1, u8 XPos2, u8 YPos2) -{ - u8 XPos = 0, YPos = 0; - - /* Use XPos1, YPos1, XPos2 and YPos2 */ - if((XPos2>=XPos1)&(YPos2>=YPos1)) - { - for(XPos=XPos1; XPos<=XPos2; XPos++) - { - for(YPos=YPos1; YPos<=YPos2; YPos++) - { - LCD_DrawPixel(XPos, YPos, Dot_On); - } - } - } - else if((XPos2=YPos1)) - { - for(XPos=XPos2; XPos<=XPos1; XPos++) - { - for(YPos=YPos1; YPos<=YPos2; YPos++) - { - LCD_DrawPixel(XPos, YPos, Dot_On); - } - } - } - else if((XPos2>=XPos1)&(YPos2 -;* : -s -;******************************************************************************* -; History: -; 07/17/2006 : V1.0 -; 03/10/2006 : V0.1 -;******************************************************************************* -; THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -; CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -;******************************************************************************/ - -// Embedded Flash (256/128/64Kbytes) -// The user has to change the flash memory length depending STR75xFxx devices - -// Code memory in flash --DROMSTART=0x20000000 --DROMEND=0x2003FFFF //0x2001FFFF;0x200FFFF - -// Data memory --DRAMSTART=0x40000000 --DRAMEND=0x40003FFF - - -//************************************************************************* -// ------------- -// Code segments - may be placed anywhere in memory. -// ------------- -// -// INTVEC -- Exception vector table. -// SWITAB -- Software interrupt vector table. -// ICODE -- Startup (cstartup) and exception code. -// DIFUNCT -- Dynamic initialization vectors used by C++. -// CODE -- Compiler generated code. -// CODE_I -- Compiler generated code declared __ramfunc (executes in RAM) -// CODE_ID -- Initializer for CODE_I (ROM). -// -// ------------- -// Data segments - may be placed anywhere in memory. -// ------------- -// -// CSTACK -- The stack used by C/C++ programs (system and user mode). -// IRQ_STACK -- The stack used by IRQ service routines. -// SVC_STACK -- The stack used in supervisor mode -// UND_STACK -- The stack used in Und mode -// ABT_STACK -- The stack used in Abort mode -// FIQ_STACK -- The stack used by FIQ service routines -// HEAP -- The heap used by malloc and free in C and new and -// delete in C++. -// INITTAB -- Table containing addresses and sizes of segments that -// need to be initialized at startup (by cstartup). -// CHECKSUM -- The linker places checksum byte(s) in this segment, -// when the -J linker command line option is used. -// DATA_y -- Data objects. -// -// Where _y can be one of: -// -// _AN -- Holds uninitialized located objects, i.e. objects with -// an absolute location given by the @ operator or the -// #pragma location directive. Since these segments -// contain objects which already have a fixed address, -// they should not be mentioned in this linker command -// file. -// _C -- Constants (ROM). -// _I -- Initialized data (RAM). -// _ID -- The original content of _I (copied to _I by cstartup) (ROM). -// _N -- Uninitialized data (RAM). -// _Z -- Zero initialized data (RAM). -// -// Note: Be sure to use end values for the defined address ranges. -// Otherwise, the linker may allocate space outside the -// intended memory range. -//************************************************************************* - - -//************************************************ -// Inform the linker about the CPU family used. -//************************************************ - --carm - -//************************************************************************* -// Segment placement - General information -// -// All numbers in the segment placement command lines below are interpreted -// as hexadecimal unless they are immediately preceded by a '.', which -// denotes decimal notation. -// -// When specifying the segment placement using the -P instead of the -Z -// option, the linker is free to split each segment into its segment parts -// and randomly place these parts within the given ranges in order to -// achieve a more efficient memory usage. One disadvantage, however, is -// that it is not possible to find the start or end address (using -// the assembler operators .sfb./.sfe.) of a segment which has been split -// and reformed. -// -// When generating an output file which is to be used for programming -// external ROM/Flash devices, the -M linker option is very useful -// (see xlink.pdf for details). -//************************************************************************* - - -//************************************************************************* -// Read-only segments mapped to ROM. -//************************************************************************* - -//************************************************ -// Address range for reset and exception -// vectors (INTVEC). -//************************************************ - --Z(CODE)INTVEC=ROMSTART-ROMEND - -//************************************************ -// Startup code and exception routines (ICODE). -//************************************************ - --Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND --Z(CODE)SWITAB=ROMSTART-ROMEND - -//************************************************ -// Code segments may be placed anywhere. -//************************************************ - --Z(CODE)CODE=ROMSTART-ROMEND - -//************************************************ -// Original ROM location for __ramfunc code copied -// to and executed from RAM. -//************************************************ - --Z(CONST)CODE_ID=ROMSTART-ROMEND - -//************************************************ -// Various constants and initializers. -//************************************************ - --Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND --Z(CONST)CHECKSUM=ROMSTART-ROMEND - - -//************************************************************************* -// Read/write segments mapped to RAM. -//************************************************************************* - -//************************************************ -// Data segments. -//************************************************ - --Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND - -//************************************************ -// __ramfunc code copied to and executed from RAM. -//************************************************ - --Z(DATA)CODE_I=RAMSTART-RAMEND - -//************************************************ -// ICCARM produces code for __ramfunc functions in -// CODE_I segments. The -Q XLINK command line -// option redirects XLINK to emit the code in the -// CODE_ID segment instead, but to keep symbol and -// debug information associated with the CODE_I -// segment, where the code will execute. -//************************************************ - --QCODE_I=CODE_ID - -//************************************************************************* -// Stack and heap segments. -//************************************************************************* - -// Add size >0 for ABT_Stack, UND_Stack if you need them. -// size must be 8 byte aligned. - --D_CSTACK_SIZE=0x100 --D_SVC_STACK_SIZE=0x400 --D_IRQ_STACK_SIZE=0x400 --D_FIQ_STACK_SIZE=0x40 --D_ABT_STACK_SIZE=0x0 --D_UND_STACK_SIZE=0x0 --D_HEAP_SIZE=0x10 - --Z(DATA)CSTACK+_CSTACK_SIZE=RAMSTART-RAMEND --Z(DATA)SVC_STACK+_SVC_STACK_SIZE=RAMSTART-RAMEND --Z(DATA)ABT_STACK+_ABT_STACK_SIZE=RAMSTART-RAMEND --Z(DATA)UND_STACK+_UND_STACK_SIZE=RAMSTART-RAMEND --Z(DATA)FIQ_STACK+_FIQ_STACK_SIZE=RAMSTART-RAMEND --Z(DATA)IRQ_STACK+_IRQ_STACK_SIZE=RAMSTART-RAMEND --Z(DATA)HEAP+_HEAP_SIZE=RAMSTART-RAMEND - -//************************************************************************* -// ELF/DWARF support. -// -// Uncomment the line "-Felf" below to generate ELF/DWARF output. -// Available format specifiers are: -// -// "-yn": Suppress DWARF debug output -// "-yp": Multiple ELF program sections -// "-yas": Format suitable for debuggers from ARM Ltd (also sets -p flag) -// -// "-Felf" and the format specifiers can also be supplied directly as -// command line options, or selected from the Xlink Output tab in the -// IAR Embedded Workbench. -//************************************************************************* - -// -Felf diff --git a/Demo/ARM7_STR75x_IAR/main.c b/Demo/ARM7_STR75x_IAR/main.c deleted file mode 100644 index 27928e827..000000000 --- a/Demo/ARM7_STR75x_IAR/main.c +++ /dev/null @@ -1,315 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * Creates all the demo application tasks, then starts the scheduler. The WEB - * documentation provides more details of the demo application tasks. - * - * In addition to the standard demo tasks there are two tasks defined within - * this file: - * - * 1 - The check task - * The 'check' task is responsible for ensuring that all the standard demo - * tasks are executing as expected. It only executes every three seconds, but - * has the highest priority within the system so is guaranteed to get execution - * time. Any errors discovered by the check task are latched until the - * processor is reset. At the end of each cycle the check task sends either - * a pass or fail message to the 'print' task for display on the LCD. - * - * 2 - The print task - * The print task is the LCD 'gatekeeper'. That is, it is the only task that - * should access the LCD directly so is always guaranteed exclusive (and - * therefore consistent) access. The print task simply blocks on a queue - * to wait for messages from other tasks wishing to display text on the LCD. - * When a message arrives it displays its contents on the LCD then blocks to - * wait again. - */ - -/* ST includes. */ -#include "lcd.h" - -/* Kernel includes. */ -#include "FreeRTOS.h" -#include "Task.h" -#include "Queue.h" - -/* Demo application includes. */ -#include "ParTest.h" -#include "flash.h" -#include "integer.h" -#include "blocktim.h" -#include "BlockQ.h" -#include "comtest2.h" -#include "dynamic.h" - -/* Demo application task priorities. */ -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) - -/* How often should we check the other tasks? */ -#define mainCHECK_TASK_CYCLE_TIME ( 3000 ) - -/* The maximum offset into the pass and fail strings sent to the LCD. An -offset is used a simple method of using a different column each time a message -is written to the LCD. */ -#define mainMAX_WRITE_COLUMN ( 14 ) - -/* Baud rate used by the comtest tasks. */ -#define mainCOM_TEST_BAUD_RATE ( 19200 ) - -/* The LED used by the comtest tasks. See the comtest.c file for more -information. */ -#define mainCOM_TEST_LED ( 3 ) - -/* The number of messages that can be queued for display on the LCD at any one -time. */ -#define mainLCD_QUEUE_LENGTH ( 2 ) - -/* The time to wait when sending to mainLCD_QUEUE_LENGTH. */ -#define mainNO_DELAY ( 0 ) - -/*-----------------------------------------------------------*/ - -/* The type that is posted to the LCD queue. */ -typedef struct LCD_MESSAGE -{ - unsigned portCHAR *pucString; /* Points to the string to be displayed. */ - unsigned portCHAR ucLine; /* The line of the LCD that should be used. */ -} LCDMessage; - -/*-----------------------------------------------------------*/ - -/* - * The task that executes at the highest priority and checks the operation of - * all the other tasks in the system. See the description at the top of the - * file. - */ -static void vCheckTask( void *pvParameters ); - -/* - * ST provided routine to configure the processor. - */ -static void prvSetupHardware(void); - -/* - * The only task that should access the LCD. Other tasks wanting to write - * to the LCD should send a message of type LCDMessage containing the - * information to display to the print task. The print task simply blocks - * waiting for the arrival of such messages, displays the message, then blocks - * again. - */ -static void vPrintTask( void *pvParameters ); - -/*-----------------------------------------------------------*/ - -/* The queue used to communicate with the LCD print task. */ -static xQueueHandle xLCDQueue; - -/*-----------------------------------------------------------*/ - -/* Create all the demo application tasks, then start the scheduler. */ -void main( void ) -{ - /* Perform any hardware setup necessary. */ - prvSetupHardware(); - vParTestInitialise(); - - /* Create the queue used to communicate with the LCD print task. */ - xLCDQueue = xQueueCreate( mainLCD_QUEUE_LENGTH, sizeof( LCDMessage ) ); - - /* Create the standard demo application tasks. See the WEB documentation - for more information on these tasks. */ - vCreateBlockTimeTasks(); - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); - vStartDynamicPriorityTasks(); - vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - - /* Create the tasks defined within this file. */ - xTaskCreate( vPrintTask, ( signed portCHAR * ) "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL ); - xTaskCreate( vCheckTask, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - - vTaskStartScheduler(); - - /* Execution will only reach here if there was insufficient heap to - start the scheduler. */ -} -/*-----------------------------------------------------------*/ - -static void vCheckTask( void *pvParameters ) -{ -static unsigned portLONG ulErrorDetected = pdFALSE; -portTickType xLastExecutionTime; -unsigned portCHAR *cErrorMessage = " FAIL"; -unsigned portCHAR *cSuccessMessage = " PASS"; -unsigned portBASE_TYPE uxColumn = mainMAX_WRITE_COLUMN; -LCDMessage xMessage; - - /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() - works correctly. */ - xLastExecutionTime = xTaskGetTickCount(); - - for( ;; ) - { - /* Wait until it is time for the next cycle. */ - vTaskDelayUntil( &xLastExecutionTime, mainCHECK_TASK_CYCLE_TIME ); - - /* Has an error been found in any of the standard demo tasks? */ - - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - ulErrorDetected = pdTRUE; - } - - if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) - { - ulErrorDetected = pdTRUE; - } - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - ulErrorDetected = pdTRUE; - } - - if( xAreComTestTasksStillRunning() != pdTRUE ) - { - ulErrorDetected = pdTRUE; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - ulErrorDetected = pdTRUE; - } - - /* Calculate the LCD line on which we would like the message to - be displayed. The column variable is used for convenience as - it is incremented each cycle anyway. */ - xMessage.ucLine = ( unsigned portCHAR ) ( uxColumn & 0x01 ); - - /* The message displayed depends on whether an error was found or - not. Any discovered error is latched. Here the column variable - is used as an index into the text string as a simple way of moving - the text from column to column. */ - if( ulErrorDetected == pdFALSE ) - { - xMessage.pucString = cSuccessMessage + uxColumn; - } - else - { - xMessage.pucString = cErrorMessage + uxColumn; - } - - /* Send the message to the print task for display. */ - xQueueSend( xLCDQueue, ( void * ) &xMessage, mainNO_DELAY ); - - /* Make sure the message is printed in a different column the next - time around. */ - uxColumn--; - if( uxColumn == 0 ) - { - uxColumn = mainMAX_WRITE_COLUMN; - } - } -} -/*-----------------------------------------------------------*/ - -static void vPrintTask( void *pvParameters ) -{ -LCDMessage xMessage; - - for( ;; ) - { - /* Wait until a message arrives. */ - while( xQueueReceive( xLCDQueue, ( void * ) &xMessage, portMAX_DELAY ) != pdPASS ); - - /* The message contains the text to display, and the line on which the - text should be displayed. */ - LCD_Clear(); - LCD_DisplayString( xMessage.ucLine, xMessage.pucString, BlackText ); - } -} -/*-----------------------------------------------------------*/ - -static void prvSetupHardware(void) -{ -ErrorStatus OSC4MStartUpStatus01; - - /* ST provided routine. */ - - /* MRCC system reset */ - MRCC_DeInit(); - - /* Wait for OSC4M start-up */ - OSC4MStartUpStatus01 = MRCC_WaitForOSC4MStartUp(); - - if(OSC4MStartUpStatus01 == SUCCESS) - { - /* Set HCLK to 60MHz */ - MRCC_HCLKConfig(MRCC_CKSYS_Div1); - - /* Set CKTIM to 60MHz */ - MRCC_CKTIMConfig(MRCC_HCLK_Div1); - - /* Set PCLK to 30MHz */ - MRCC_PCLKConfig(MRCC_CKTIM_Div2); - - /* Enable Flash Burst mode */ - CFG_FLASHBurstConfig(CFG_FLASHBurst_Enable); - - /* Set CK_SYS to 60 MHz */ - MRCC_CKSYSConfig(MRCC_CKSYS_OSC4MPLL, MRCC_PLL_Mul_15); - } - - /* GPIO pins optimized for 3V3 operation */ - MRCC_IOVoltageRangeConfig(MRCC_IOVoltageRange_3V3); - - /* GPIO clock source enable */ - MRCC_PeripheralClockConfig(MRCC_Peripheral_GPIO, ENABLE); - - /* EXTIT clock source enable */ - MRCC_PeripheralClockConfig(MRCC_Peripheral_EXTIT, ENABLE); - /* TB clock source enable */ - MRCC_PeripheralClockConfig(MRCC_Peripheral_TB, ENABLE); - - /* Initialize the demonstration menu */ - LCD_Init(); - - LCD_DisplayString(Line1, "www.FreeRTOS.org", BlackText); - LCD_DisplayString(Line2, " STR750 Demo ", BlackText); - - EIC_IRQCmd(ENABLE); -} -/*-----------------------------------------------------------*/ diff --git a/Demo/ARM7_STR75x_IAR/serial/serial.c b/Demo/ARM7_STR75x_IAR/serial/serial.c deleted file mode 100644 index 59aef9320..000000000 --- a/Demo/ARM7_STR75x_IAR/serial/serial.c +++ /dev/null @@ -1,263 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0. -*/ - -/* Library includes. */ -#include "75x_uart.h" -#include "75x_gpio.h" -#include "75x_eic.h" -#include "75x_mrcc.h" - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "queue.h" - -/* Demo application includes. */ -#include "serial.h" - -#define serINVALID_QUEUE ( ( xQueueHandle ) 0 ) -#define serNO_BLOCK ( ( portTickType ) 0 ) - -/*-----------------------------------------------------------*/ - -/* Queues used to hold received characters, and characters waiting to be -transmitted. */ -static xQueueHandle xRxedChars; -static xQueueHandle xCharsForTx; - -static volatile portBASE_TYPE xQueueEmpty = pdTRUE; - -/*-----------------------------------------------------------*/ - -/* The interrupt service routine - called from the assembly entry point. */ -__arm void vSerialISR( void ); - -/*-----------------------------------------------------------*/ - -/* - * See the serial2.h header file. - */ -xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) -{ -xComPortHandle xReturn; -UART_InitTypeDef UART_InitStructure; -GPIO_InitTypeDef GPIO_InitStructure; -EIC_IRQInitTypeDef EIC_IRQInitStructure; - - /* Create the queues used to hold Rx and Tx characters. */ - xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); - xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); - - /* If the queues were created correctly then setup the serial port - hardware. */ - if( ( xRxedChars != serINVALID_QUEUE ) && ( xCharsForTx != serINVALID_QUEUE ) ) - { - portENTER_CRITICAL(); - { - /* Enable the UART0 Clock. */ - MRCC_PeripheralClockConfig( MRCC_Peripheral_UART0, ENABLE ); - - /* Configure the UART0_Tx as alternate function */ - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11; - GPIO_Init(GPIO0, &GPIO_InitStructure); - - /* Configure the UART0_Rx as input floating */ - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; - GPIO_Init(GPIO0, &GPIO_InitStructure); - - /* Configure UART0. */ - UART_InitStructure.UART_WordLength = UART_WordLength_8D; - UART_InitStructure.UART_StopBits = UART_StopBits_1; - UART_InitStructure.UART_Parity = UART_Parity_No; - UART_InitStructure.UART_BaudRate = ulWantedBaud; - UART_InitStructure.UART_HardwareFlowControl = UART_HardwareFlowControl_None; - UART_InitStructure.UART_Mode = UART_Mode_Tx_Rx; - UART_InitStructure.UART_TxFIFOLevel = UART_FIFOLevel_1_2; /* FIFO size 16 bytes, FIFO level 8 bytes */ - UART_InitStructure.UART_RxFIFOLevel = UART_FIFOLevel_1_2; /* FIFO size 16 bytes, FIFO level 8 bytes */ - UART_Init(UART0, &UART_InitStructure); - - /* Enable the UART0 */ - UART_Cmd(UART0, ENABLE); - - /* Configure the IEC for the UART interrupts. */ - EIC_IRQInitStructure.EIC_IRQChannelCmd = ENABLE; - EIC_IRQInitStructure.EIC_IRQChannel = UART0_IRQChannel; - EIC_IRQInitStructure.EIC_IRQChannelPriority = 1; - EIC_IRQInit(&EIC_IRQInitStructure); - - xQueueEmpty = pdTRUE; - UART_ITConfig( UART0, UART_IT_Transmit | UART_IT_Receive, ENABLE ); - } - portEXIT_CRITICAL(); - } - else - { - xReturn = ( xComPortHandle ) 0; - } - - /* This demo file only supports a single port but we have to return - something to comply with the standard demo header file. */ - return xReturn; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) -{ - /* The port handle is not required as this driver only supports one port. */ - ( void ) pxPort; - - /* Get the next character from the buffer. Return false if no characters - are available, or arrive before xBlockTime expires. */ - if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) - { - return pdTRUE; - } - else - { - return pdFALSE; - } -} -/*-----------------------------------------------------------*/ - -void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength ) -{ -signed portCHAR *pxNext; - - /* A couple of parameters that this port does not use. */ - ( void ) usStringLength; - ( void ) pxPort; - - /* NOTE: This implementation does not handle the queue being full as no - block time is used! */ - - /* The port handle is not required as this driver only supports UART0. */ - ( void ) pxPort; - - /* Send each character in the string, one at a time. */ - pxNext = ( signed portCHAR * ) pcString; - while( *pxNext ) - { - xSerialPutChar( pxPort, *pxNext, serNO_BLOCK ); - pxNext++; - } -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) -{ -portBASE_TYPE xReturn; - - /* Place the character in the queue of characters to be transmitted. */ - portENTER_CRITICAL(); - { - if( xQueueEmpty == pdTRUE ) - { - UART0->DR = cOutChar; - xReturn = pdPASS; - } - else - { - if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) - { - xReturn = pdFAIL; - } - else - { - xReturn = pdPASS; - } - } - - xQueueEmpty = pdFALSE; - } - portEXIT_CRITICAL(); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -void vSerialClose( xComPortHandle xPort ) -{ - /* Not supported as not required by the demo application. */ -} -/*-----------------------------------------------------------*/ - -__arm void vSerialISR( void ) -{ -signed portCHAR cChar; -portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByPost = pdFALSE; - - do - { - if( UART0->MIS & UART_IT_Transmit ) - { - /* The interrupt was caused by the THR becoming empty. Are there any - more characters to transmit? */ - if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE ) - { - /* A character was retrieved from the queue so can be sent to the - THR now. */ - UART0->DR = cChar; - } - else - { - xQueueEmpty = pdTRUE; - } - - UART_ClearITPendingBit( UART0, UART_IT_Transmit ); - } - - if( UART0->MIS & UART_IT_Receive ) - { - /* The interrupt was caused by a character being received. Grab the - character from the RHR and place it in the queue of received - characters. */ - cChar = UART0->DR; - xTaskWokenByPost = xQueueSendFromISR( xRxedChars, &cChar, xTaskWokenByPost ); - UART_ClearITPendingBit( UART0, UART_IT_Receive ); - } - } while( UART0->MIS ); - - /* If a task was woken by either a character being received or a character - being transmitted then we may need to switch to another task. */ - portEND_SWITCHING_ISR( ( xTaskWokenByPost || xTaskWokenByTx ) ); -} - - - - - - diff --git a/Demo/ARM7_STR75x_IAR/settings/RTOSDemo.dbgdt b/Demo/ARM7_STR75x_IAR/settings/RTOSDemo.dbgdt deleted file mode 100644 index 1c29a21aa..000000000 --- a/Demo/ARM7_STR75x_IAR/settings/RTOSDemo.dbgdt +++ /dev/null @@ -1,88 +0,0 @@ - - - - - - - - - - - - - 158272727 - - - - - - - - 200 - - - - 100 - - 20 - 1004 - 267 - 66 - - - {W}Watch-0:TB->CR4200143100100100200 - - - - - - - TabID-22366-21915 - Debug Log - Debug-Log - - - - TabID-21843-21924 - Build - Build - - - - TabID-21385-32577 - Breakpoints - Breakpoints - - - - - 0 - - - TabID-346-21918 - Workspace - Workspace - - - RTOSDemo - - - - 0 - - - - - - TextEditorC:\E\Dev\FreeRTOS\Demo\ARM7_STR75x_IAR\main.c01195333533300100000010000001 - - - - - - - iaridepm1debuggergui1-2-2796232-2-20000167143820988-2-21301402-2-21404132100285713580200 - - - - diff --git a/Demo/ARM7_STR75x_IAR/settings/RTOSDemo.dni b/Demo/ARM7_STR75x_IAR/settings/RTOSDemo.dni deleted file mode 100644 index 6b1ac8cf7..000000000 --- a/Demo/ARM7_STR75x_IAR/settings/RTOSDemo.dni +++ /dev/null @@ -1,40 +0,0 @@ -[JLinkDriver] -WatchCond=_ 0 -Watch0=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 -Watch1=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 -[DisAssemblyWindow] -NumStates=_ 1 -State 1=_ 1 -[StackPlugin] -Enabled=1 -OverflowWarningsEnabled=1 -WarningThreshold=90 -SpWarningsEnabled=1 -WarnHow=0 -UseTrigger=1 -TriggerName=main -LimitSize=0 -ByteLimit=50 -[Interrupts] -Enabled=1 -[MemoryMap] -Enabled=0 -Base=0 -UseAuto=0 -TypeViolation=1 -UnspecRange=1 -ActionState=1 -[Log file] -LoggingEnabled=_ 0 -LogFile=_ "" -Category=_ 0 -[TermIOLog] -LoggingEnabled=_ 0 -LogFile=_ "" -[Disassemble mode] -mode=0 -[Breakpoints] -Count=0 -[TraceHelper] -Enabled=0 -ShowSource=1 diff --git a/Demo/ARM7_STR75x_IAR/settings/RTOSDemo.wsdt b/Demo/ARM7_STR75x_IAR/settings/RTOSDemo.wsdt deleted file mode 100644 index 9ecfb8432..000000000 --- a/Demo/ARM7_STR75x_IAR/settings/RTOSDemo.wsdt +++ /dev/null @@ -1,64 +0,0 @@ - - - - - - RTOSDemo/Debug - - - - - - - - - 224272727 - - - - - - - 300Find-in-FilesDebug-LogBreakpoints20100426766 - - - - - 48268826300BuildDebug-LogBreakpoints - 300BuildFind-in-FilesBreakpoints - - - 100300BuildFind-in-FilesDebug-Log - - - - - - - TabID-5322-15070 - Workspace - Workspace - - - RTOSDemoRTOSDemo/source - - - - 0TabID-10308-14988BuildBuildTabID-11884-28246BreakpointsBreakpointsTabID-30248-21129Debug LogDebug-Log0 - - - - - - TextEditorC:\E\Dev\FreeRTOS\Demo\ARM7_STR75x_IAR\main.c011953335333TextEditorC:\E\temp\rc\2\V4.1.2rc1\Demo\ARM7_STR75x_IAR\STLibrary\inc\75x_map.h0013451345TextEditorC:\E\temp\rc\2\V4.1.2rc1\Demo\ARM7_STR75x_IAR\STLibrary\src\75x_it.c02119391939TextEditorC:\E\temp\rc\2\V4.1.2rc1\Demo\ARM7_STR75x_IAR\STLibrary\src\lcd.c0212162211623930100000010000001 - - - - - - - iaridepm1-2-2705298-2-20000214286727366-2-22211402-2-214042231002857229424142857205761 - - - - diff --git a/Demo/ARM7_STR75x_IAR/settings/RTOSDemo_lnk.par b/Demo/ARM7_STR75x_IAR/settings/RTOSDemo_lnk.par deleted file mode 100644 index 88b582c54..000000000 --- a/Demo/ARM7_STR75x_IAR/settings/RTOSDemo_lnk.par +++ /dev/null @@ -1,17 +0,0 @@ -// IAR XLINK Setup -// Autogenerated file - do not edit -% -setrangelist($evec_ADR,[0-3F]); -setrangelist($internal_ROM,[8000-FFFFF]); -setrangelist($external_ROM,[]); -setrangelist($internal_RAM,[100000-7FFFFF]); -setrangelist($external_RAM,[]); -$CSTACK_SIZE=2000; -$IRQSTACK_SIZE=400; -$HEAP_SIZE=8000; -$COMMANDS=""; -$STACK_LOCATION="Internal RAM"; -$IRQSTACK_LOCATION="Internal RAM"; -$HEAP_LOCATION="Internal RAM"; -$iar_saved_xclfilename="C:\E\Dev\FreeRTOS\Demo\ARM7_STR75x_IAR\RTOSDemo_lnk.xcl"; -% \ No newline at end of file diff --git a/Demo/ARM9_STR91X_IAR/91x_init_IAR.s b/Demo/ARM9_STR91X_IAR/91x_init_IAR.s deleted file mode 100644 index 1204e0871..000000000 --- a/Demo/ARM9_STR91X_IAR/91x_init_IAR.s +++ /dev/null @@ -1,175 +0,0 @@ -;******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -;* File Name : 91x_init.s -;* Author : MCD Application Team -;* Date First Issued : 05/18/2006 : Version 1.0 -;* Description : This module performs: -;* - FLASH/RAM initialization, -;* - Stack pointer initialization for each mode , -;* - Branches to ?main in the C library (which eventually -;* calls main()). -;* -;* On reset, the ARM core starts up in Supervisor (SVC) mode, -;* in ARM state,with IRQ and FIQ disabled. -;******************************************************************************* -; History: -; 05/24/2006 : Version 1.1 -; 05/18/2006 : Version 1.0 -;******************************************************************************* -;* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH -;* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS -;* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT -;* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT -;* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION -;* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -;******************************************************************************/ - -; Depending in Your Application, Disable or Enable the following Define - -; #define BUFFERED_Mode ; Work on Buffered mode, when enabling this define - ; just enable the Buffered define on 91x_conf.h - -; --- Standard definitions of mode bits and interrupt (I & F) flags in PSRs - -Mode_USR EQU 0x10 -Mode_FIQ EQU 0x11 -Mode_IRQ EQU 0x12 -Mode_SVC EQU 0x13 -Mode_ABT EQU 0x17 -Mode_UND EQU 0x1B -Mode_SYS EQU 0x1F ; available on ARM Arch 4 and later - -I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled -F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled - -;--- BASE ADDRESSES -; System memory locations - -SRAM_Base EQU 0x04000000 -SRAM_Limit EQU 0x04018000 ; at the top of 96 KB SRAM - -SVC_Stack DEFINE SRAM_Limit ; 512 byte SVC stack at - ; top of memory - used by kernel. -IRQ_Stack DEFINE SVC_Stack-512 ; followed by IRQ stack -USR_Stack DEFINE IRQ_Stack-512 ; followed by USR stack. Tasks run in - ; system mode but task stacks are allocated - ; when the task is created. -FIQ_Stack DEFINE USR_Stack-8 ; followed by FIQ stack -ABT_Stack DEFINE FIQ_Stack-8 ; followed by ABT stack -UND_Stack DEFINE ABT_Stack-8 ; followed by UNDEF stack - - EXTERN main - -; STR9X register specific definition - -FMI_BBSR_AHB_UB EQU 0x54000000 -FMI_BBADR_AHB_UB EQU 0x5400000C -FMI_NBBSR_AHB_UB EQU 0x54000004 -FMI_NBBADR_AHB_UB EQU 0x54000010 - -SCU_SCRO_APB1_UB EQU 0x4C002034 -SCRO_AHB_UNB EQU 0x5C002034 - - - -;--------------------------------------------------------------- -; ?program_start -;--------------------------------------------------------------- - MODULE ?program_start - RSEG ICODE:CODE(2) - IMPORT LINK - PUBLIC __program_start - EXTERN ?main - CODE32 - - -__program_start: - LDR pc, =NextInst - - -NextInst - - - NOP ; execute some instructions to access CPU registers after wake - NOP ; up from Reset, while waiting for OSC stabilization - NOP - NOP - NOP - NOP - NOP - NOP - NOP - ldr r0,=LINK ; to include the vector table inside the final executable. - - - -; --- Remap Flash Bank 0 at address 0x0 and Bank 1 at address 0x80000, -; when the bank 0 is the boot bank, then enable the Bank 1. - - LDR R6, =0x54000000 - LDR R7, =0x4 - STR R7, [R6] - - LDR R6, =0x54000004 - LDR R7, =0x3 - STR R7, [R6] - - LDR R6, =0x5400000C - LDR R7, =0x0 - STR R7, [R6] - - LDR R6, =0x54000010 - LDR R7, =0x20000 - STR R7, [R6] - - LDR R6, =0x54000018 - LDR R7, =0x18 - STR R7, [R6] - -; --- Enable 96K RAM - LDR R0, = SCRO_AHB_UNB - LDR R1, = 0x0196 - STR R1, [R0] - - - /* Setup a stack for each mode - note that this only sets up a usable stack - for system/user, SWI and IRQ modes. Also each mode is setup with - interrupts initially disabled. */ - - MSR CPSR_c, #Mode_FIQ|I_Bit|F_Bit ; No interrupts - LDR SP, =FIQ_Stack - - MSR CPSR_c, #Mode_IRQ|I_Bit|F_Bit ; No interrupts - LDR SP, =IRQ_Stack - - MSR CPSR_c, #Mode_ABT|I_Bit|F_Bit ; No interrupts - LDR SP, =ABT_Stack - - MSR CPSR_c, #Mode_UND|I_Bit|F_Bit ; No interrupts - LDR SP, =UND_Stack - - MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit ; No interrupts - LDR SP, =SVC_Stack - - MSR CPSR_c, #Mode_SYS|I_Bit|F_Bit ; No interrupts - LDR SP, =USR_Stack - - /* We want to start in supervisor mode. Operation will switch to system - mode when the first task starts. */ - MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit - - -; --- Set bits 17-18 of the Core Configuration Control Register - - MOV r0, #0x60000 - MCR p15,0x1,r0,c15,c1,0 - - -; --- Now enter the C code - B ?main ; Note : use B not BL, because an application will - ; never return this way - - LTORG - - END -;******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE**** - diff --git a/Demo/ARM9_STR91X_IAR/91x_vect_IAR.s b/Demo/ARM9_STR91X_IAR/91x_vect_IAR.s deleted file mode 100644 index c87b0004b..000000000 --- a/Demo/ARM9_STR91X_IAR/91x_vect_IAR.s +++ /dev/null @@ -1,134 +0,0 @@ -;******************** (C) COPYRIGHT 2005 STMicroelectronics ******************** -;* File Name : 91x_vect.s -;* Author : MCD Application Team -;* Date First Issued : 10/25/2005 : Beta Version V0.1 -;* Description : This File used to initialize the exception and IRQ -;* vectors, and to enter/return to/from exceptions -;* handlers. -;******************************************************************************* -; History: -; 10/25/2005 : Beta Version V0.1 -;******************************************************************************* -; THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH -; CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS -; A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT -; OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT -; OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION -; CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -;******************************************************************************/ - -#include "FreeRTOSConfig.h" -#include "ISR_Support.h" - - MODULE ?RESET - COMMON INTVEC:CODE(2) - CODE32 - EXPORT LINK - -VectorAddress EQU 0xFFFFF030 ; VIC Vector address register address. -VectorAddressDaisy EQU 0xFC000030 ; Daisy VIC Vector address register - ; address. -LINK EQU 0x0 - -I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled -F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled - -;******************************************************************************* -; MACRO -;******************************************************************************* - -;******************************************************************************* -; Import the __program_start address from 91x_init.s -;******************************************************************************* - - IMPORT __program_start - -;******************************************************************************* -; Import exception handlers -;******************************************************************************* - - IMPORT vPortYieldProcessor ; FreeRTOS SWI handler - -;******************************************************************************* -; Export Peripherals IRQ handlers table address -;******************************************************************************* - -;******************************************************************************* -; Exception vectors -;******************************************************************************* - - LDR PC, Reset_Addr - LDR PC, Undefined_Addr - LDR PC, SWI_Addr - LDR PC, Prefetch_Addr - LDR PC, Abort_Addr - NOP ; Reserved vector - LDR PC, IRQ_Addr - LDR PC, FIQ_Addr - -;******************************************************************************* -; Exception handlers address table -;******************************************************************************* - -Reset_Addr DCD __program_start -Undefined_Addr DCD UndefinedHandler -SWI_Addr DCD vPortYieldProcessor -Prefetch_Addr DCD PrefetchAbortHandler -Abort_Addr DCD DataAbortHandler - DCD 0 ; Reserved vector -IRQ_Addr DCD IRQHandler -FIQ_Addr DCD FIQHandler - - -;******************************************************************************* -; Exception Handlers -;******************************************************************************* - -; - NOTE - -; The IRQ and SWI handlers are the only managed exception. - -UndefinedHandler - b UndefinedHandler - -PrefetchAbortHandler - b PrefetchAbortHandler - -DataAbortHandler - b DataAbortHandler - -FIQHandler - b FIQHandler - -DefaultISR - b DefaultISR - - -;******************************************************************************* -;* Function Name : IRQHandler -;* Description : This function called when IRQ exception is entered. -;* Input : none -;* Output : none -;******************************************************************************* - -IRQHandler - portSAVE_CONTEXT ; Save the context of the current task. - - LDR r0, = VectorAddress - LDR r0, [r0] ; Read the routine address - LDR r1, = VectorAddressDaisy - LDR r1, [r1] - MOV lr, pc - bx r0 - LDR r0, = VectorAddress ; Write to the VectorAddress to clear the - STR r0, [r0] ; respective interrupt in the internal interrupt - LDR r1, = VectorAddressDaisy ; Write to the VectorAddressDaisy to clear the - STR r1,[r1] ; respective interrupt in the internal interrupt - - portRESTORE_CONTEXT ; Restore the context of the selected task. - - - LTORG - - END - -;******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE**** diff --git a/Demo/ARM9_STR91X_IAR/FreeRTOSConfig.h b/Demo/ARM9_STR91X_IAR/FreeRTOSConfig.h deleted file mode 100644 index 544d456bc..000000000 --- a/Demo/ARM9_STR91X_IAR/FreeRTOSConfig.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 96000000 ) -#define configCPU_PERIPH_HZ ( ( unsigned portLONG ) 48000000 ) -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 180 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) 50000 ) -#define configMAX_TASK_NAME_LEN ( 16 ) -#define configUSE_TRACE_FACILITY 1 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 1 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/ARM9_STR91X_IAR/Library/include/91x_ahbapb.h b/Demo/ARM9_STR91X_IAR/Library/include/91x_ahbapb.h deleted file mode 100644 index 1828d488e..000000000 --- a/Demo/ARM9_STR91X_IAR/Library/include/91x_ahbapb.h +++ /dev/null @@ -1,60 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 91x_ahbapb.h -* Author : MCD Application Team -* Date First Issued : 05/18/2006 : Version 1.0 -* Description : This file contains all the functions prototypes for the -* AHBAPB software library. -******************************************************************************** -* History: -* 05/24/2006 : Version 1.1 -* 05/18/2006 : Version 1.0 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH -* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS -* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT -* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT -* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION -* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef _91x_AHBAPB_H -#define _91x_AHBAPB_H - -#include "91x_map.h" - -#define AHBAPB_Split_Enable 0x01000000 -#define AHBAPB_Split_Disable 0xFEFFFFFF -#define AHBAPB_Error_Enable 0x0000100 -#define AHBAPB_Error_Disable 0xFFFFEFF - -/*FLAG*/ -#define AHBAPB_FLAG_ERROR 0x01 /* error flag*/ -#define AHBAPB_FLAG_OUTM 0x10 /* Out of Memory flag */ -#define AHBAPB_FLAG_APBT 0x20 /* APB Time-out flag */ -#define AHBAPB_FLAG_RW 0x40 /*Access type flag*/ - -/* Includes ------------------------------------------------------------------*/ - - -/* AHBAPB Init structure definition */ -typedef struct -{ - u32 AHBAPB_SetTimeOut; - u32 AHBAPB_Error; - u32 AHBAPB_Split; - u8 AHBAPB_SplitCounter; -}AHBAPB_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ -void AHBAPB_DeInit(AHBAPB_TypeDef* AHBAPBx); -void AHBAPB_Init(AHBAPB_TypeDef* AHBAPBx, AHBAPB_InitTypeDef* AHBAPB_InitStruct); -void AHBAPB_StructInit(AHBAPB_InitTypeDef* AHBAPB_InitStruct); -FlagStatus AHBAPB_GetFlagStatus(AHBAPB_TypeDef* AHBAPBx, u8 AHBAPB_FLAG); -void AHBAPB_ClearFlag(AHBAPB_TypeDef* AHBAPBx, u8 AHBAPB_FLAG); -u32 AHBAPB_GetPeriphAddrError(AHBAPB_TypeDef* AHBAPBx); - - -#endif /* _91x_AHBAPB_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM9_STR91X_IAR/Library/include/91x_conf.h b/Demo/ARM9_STR91X_IAR/Library/include/91x_conf.h deleted file mode 100644 index 565ec916e..000000000 --- a/Demo/ARM9_STR91X_IAR/Library/include/91x_conf.h +++ /dev/null @@ -1,119 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 91x_conf.h -* Author : MCD Application Team -* Date First Issued : 03/31/2006 : Beta Version V0.1 -* Description : Library configuration. -******************************************************************************** -* History: -* 03/31/2006 : Beta Version V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH -* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS -* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT -* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT -* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION -* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - - -#ifndef __91x_CONF_H -#define __91x_CONF_H - -/* To work in buffered mode just decomment the following line */ - -//#define Buffered - -/* Comment the line below to put the library in release mode */ - -//#ifndef inline -// #define inline inline -//#endif - -/************************* AHBAPB *************************/ -#define _AHBAPB -#define _AHBAPB0 -#define _AHBAPB1 -/************************* VIC *************************/ -#define _VIC -#define _VIC0 -#define _VIC1 -/************************* DMA *************************/ -//#define _DMA -//#define _DMA_Channel0 -//#define _DMA_Channel1 -//#define _DMA_Channel2 -//#define _DMA_Channel3 -//#define _DMA_Channel4 -//#define _DMA_Channel5 -//#define _DMA_Channel6 -//#define _DMA_Channel7 - -/************************* EMI *************************/ -//#define _EMI -//#define _EMI_Bank0 -//#define _EMI_Bank1 -//#define _EMI_Bank2 -//#define _EMI_Bank3 -/************************* FMI *************************/ -#define _FMI -/************************* WIU *************************/ -//#define _WIU -/************************* TIM *************************/ -//#define _TIM -//#define _TIM0 -//#define _TIM1 -//#define _TIM2 -//#define _TIM3 -/************************* GPIO ************************/ -#define _GPIO -#define _GPIO0 -#define _GPIO1 -#define _GPIO2 -#define _GPIO3 -#define _GPIO4 -#define _GPIO5 -#define _GPIO6 -#define _GPIO7 -#define _GPIO8 -#define _GPIO9 -/************************* RTC *************************/ -//#define _RTC -/************************* SCU *************************/ -#define _SCU -/************************* MC **************************/ -//#define _MC -/************************* UART ************************/ -#define _UART -//#define _UART0 -#define _UART1 -//#define _UART2 -/************************* SSP *************************/ -//#define _SSP -//#define _SSP0 -//#define _SSP1 -/************************* CAN *************************/ -//#define _CAN -/************************* ADC *************************/ -//#define _ADC -/************************* WDG *************************/ -#define _WDG -/************************* I2C *************************/ -//#define _I2C -//#define _I2C0 -//#define _I2C1 -/************************ ENET *************************/ -#define _ENET -/************************ DENET ************************/ -//#define _DENET - -/*---------------------------- _Main_Crystal frequency value (KHz)------------*/ - -#ifndef _Main_Crystal -#define _Main_Crystal 25000 -#endif -/*------------------------------------------------------------------------------*/ - - -#endif /* __91x_CONF_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM9_STR91X_IAR/Library/include/91x_dma.h b/Demo/ARM9_STR91X_IAR/Library/include/91x_dma.h deleted file mode 100644 index 6a383aafe..000000000 --- a/Demo/ARM9_STR91X_IAR/Library/include/91x_dma.h +++ /dev/null @@ -1,247 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : template.h -* Author : MCD Application Team -* Date First Issued : 05/18/2006 : Version 1.0 -* Description : provide a short description of the source file indicating -* its purpose. -******************************************************************************** -* History: -* 05/24/2006 : Version 1.1 -* 05/18/2006 : Version 1.0 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __91x_DMA_H -#define __91x_DMA_H - -/* Includes ------------------------------------------------------------------*/ -#include"91x_map.h" - - -/* Exported types ------------------------------------------------------------*/ - -typedef struct -{ - u32 DMA_Channel_SrcAdd; /* The current source address (byte-aligned) of the data to be transferred.*/ - - u32 DMA_Channel_DesAdd; /* The current destination address (byte-aligned) of the data to be transferred.*/ - - u32 DMA_Channel_LLstItm; /* The word- aligned address for the next Linked List Item. */ - - u32 DMA_Channel_DesWidth; /* Destination transfer width. */ - - u32 DMA_Channel_SrcWidth; /* Source transfer width. */ - - u32 DMA_Channel_DesBstSize; /* The destination burst size which indicates the number of transfers that make up a destination burst transfer request.*/ - - u32 DMA_Channel_SrcBstSize; /* The source burst size.Indicates the number of transfers that make up a source burst */ - - u32 DMA_Channel_TrsfSize; /* Transfer size which indicates the size of the transfer when the DMA controller is the flow controller*/ - - u32 DMA_Channel_FlowCntrl; /* Flow control and transfer type. */ - - u32 DMA_Channel_Src; /* Source peripheral: selects the DMA source request peripheral. */ - - u32 DMA_Channel_Des; /* Destination peripheral:selects the DMA destination request peripheral. */ - -} DMA_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - - /* Interrupts masks */ - -#define DMA_ITMask_IE 0x4000 /* Interrupt error mask. */ -#define DMA_ITMask_ITC 0x8000 /* Terminal count interrupt mask.*/ -#define DMA_ITMask_ALL 0xC000 /* All DMA_Channelx interrupts enable/disable mask*/ - - /* Sources Request (used as masks) */ - -#define DMA_USB_RX_Mask 0x0001 -#define DMA_USB_TX_Mask 0x0002 -#define DMA_TIM0_Mask 0x0004 -#define DMA_TIM1_Mask 0x0008 -#define DMA_UART0_RX_Mask 0x0010 -#define DMA_UART0_TX_Mask 0x0020 -#define DMA_UART1_RX_Mask 0x0040 -#define DMA_UART1_TX_Mask 0x0080 -#define DMA_External_Req0_Mask 0x0100 -#define DMA_External_Req1_Mask 0x0200 -#define DMA_I2C0_Mask 0x0400 -#define DMA_I2C1_Mask 0x0800 -#define DMA_SSP0_RX_Mask 0x1000 -#define DMA_SSP0_TX_Mask 0x2000 -#define DMA_SSP1_RX_Mask 0x4000 -#define DMA_SSP1_TX_Mask 0x8000 - - -/* Previleged Mode and user mode */ - -#define DMA_PrevilegedMode 0x10000000 -#define DMA_UserMode 0xEFFFFFFF - - -/* Error and Terminal Count interrupts Status, after and before"raw" masking */ -#define DMA_IS 0x01 -#define DMA_TCS 0x02 -#define DMA_ES 0x03 -#define DMA_TCRS 0x04 -#define DMA_ERS 0x05 - - -/* interrupt clear: Terminal Count flag Clear and Error flag clear*/ - -#define DMA_TCC 0x01 -#define DMA_EC 0x02 - -/* channel index "0...7"*/ - -#define Channel0 0 -#define Channel1 1 -#define Channel2 2 -#define Channel3 3 -#define Channel4 4 -#define Channel5 5 -#define Channel6 6 -#define Channel7 7 - - - -/* Destination request selection: selects the DMA Destination request peripheral */ - -#define DMA_DES_USB_RX 0x00 -#define DMA_DES_USB_TX 0x40 -#define DMA_DES_TIM1 0x80 -#define DMA_DES_TIM2 0xC0 -#define DMA_DES_UART0_RX 0x100 -#define DMA_DES_UART0_TX 0x140 -#define DMA_DES_UART1_RX 0x180 -#define DMA_DES_UART1_TX 0x1C0 -#define DMA_DES_External_Req0 0x200 -#define DMA_DES_External_Req1 0x240 -#define DMA_DES_I2C0 0x280 -#define DMA_DES_I2C1 0x2C0 -#define DMA_DES_SSP0_RX 0x300 -#define DMA_DES_SSP0_TX 0x340 -#define DMA_DES_SSP1_RX 0x380 -#define DMA_DES_SSP1_TX 0x3C0 - - - - -/* Source request selection: selects the DMA Source request peripheral */ - -#define DMA_SRC_USB_RX 0x00 -#define DMA_SRC_USB_TX 0x02 -#define DMA_SRC_TIM1 0x04 -#define DMA_SRC_TIM2 0x06 -#define DMA_SRC_UART0_RX 0x08 -#define DMA_SRC_UART0_TX 0x0A -#define DMA_SRC_UART1_RX 0x0C -#define DMA_SRC_UART1_TX 0x0E -#define DMA_SRC_External_Req0 0x10 -#define DMA_SRC_External_Req1 0x12 -#define DMA_SRC_I2C0 0x14 -#define DMA_SRC_I2C1 0x16 -#define DMA_SRC_SSP0_RX 0x18 -#define DMA_SRC_SSP0_TX 0x1A -#define DMA_SRC_SSP1_RX 0x1C -#define DMA_SRC_SSP1_TX 0x1E - - - - - -#define DMA_FlowCntrlt0_DMA 0x00000000 /* transfer type :Memory-to-memory, flow controller:DMA */ -#define DMA_FlowCntrl1_DMA 0x00000800 /* transfer type :Memory-to-peripheral, flow controller:DMA */ -#define DMA_FlowCntrl2_DMA 0x00001000 /* transfer type :Peripheral-to-memory, flow controller:DMA */ -#define DMA_FlowCntrl3_DMA 0x00001800 /* transfer type :Source peripheral-to-destination peripheral, flow controller:DMA */ -#define DMA_FlowCntrl_DestPerip 0x00002000 /* transfer type :Source peripheral-to-destination peripheral, flow controller:Destination peripheral */ -#define DMA_FlowCntrl_Perip1 0x00002800 /* transfer type :Memory-to-peripheral, flow controller:peripheral */ -#define DMA_FlowCntrl_Perip2 0x00003000 /* transfer type : Peripheral-to-memory, flow controller:peripheral */ -#define DMA_FlowCntrl_SrcPerip 0x00003800 /* transfer type :Source peripheral-to-destination peripheral, flow controller:Source peripheral */ - - - - -#define DMA_SrcBst_1Data 0x00000000 /* Source Burst transfer request IS 1 Data ( DATA = Source transfer width ) */ -#define DMA_SrcBst_4Data 0x00001000 /* Source Burst transfer request IS 4 Data */ -#define DMA_SrcBst_8Data 0x00002000 /* Source Burst transfer request IS 8 Data */ -#define DMA_SrcBst_16Data 0x00003000 /* Source Burst transfer request IS 16 Data */ -#define DMA_SrcBst_32Data 0x00004000 /* Source Burst transfer request IS 32 Data */ -#define DMA_SrcBst_64Data 0x00005000 /* Source Burst transfer request IS 64Data */ -#define DMA_SrcBst_128Data 0x00006000 /* Source Burst transfer request IS 128 Data */ -#define DMA_SrcBst_256Data 0x00007000 /* Source Burst transfer request IS 256 Data */ - - - - -#define DMA_DesBst_1Data 0x00000000 /*Destination Burst transfer request IS 1Data ( DATA = destination transfer width ) */ -#define DMA_DesBst_4Data 0x00008000 /*Destination Burst transfer request IS 1 Data */ -#define DMA_DesBst_8Data 0x00010000 /*Destination Burst transfer request IS 4 Data */ -#define DMA_DesBst_16Data 0x00018000 /*Destination Burst transfer request IS 8 Data */ -#define DMA_DesBst_32Data 0x00020000 /*Destination Burst transfer request IS 16 Data */ -#define DMA_DesBst_64Data 0x00028000 /*Destination Burst transfer request IS 32 Data */ -#define DMA_DesBst_128Data 0x00030000 /*Destination Burst transfer request IS 128 Data */ -#define DMA_DesBst_256Data 0x00038000 /*Destination Burst transfer request IS 256 Data */ - - - - - -#define DMA_SrcWidth_Byte 0x00000000 /* source Width is one Byte */ -#define DMA_SrcWidth_HalfWord 0x00040000 /* source Width is one HalfWord */ -#define DMA_SrcWidth_Word 0x00080000 /* source Width is one Word */ - - - - -#define DMA_DesWidth_Byte 0x00000000 /* Destination Width is one Byte */ -#define DMA_DesWidth_HalfWord 0x00200000 /* Destination Width is one HalfWord */ -#define DMA_DesWidth_Word 0x00400000 /* Destination Width is one Word */ - - - - - - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -void DMA_DeInit(void); -void DMA_Init(DMA_Channel_TypeDef * DMA_Channelx, DMA_InitTypeDef * DMA_InitStruct); -void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct); -void DMA_Cmd(FunctionalState NewState); -void DMA_ITMaskConfig(DMA_Channel_TypeDef * DMA_Channelx, u16 DMA_ITMask, FunctionalState NewState); -void DMA_ITConfig(DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState); -FlagStatus DMA_GetChannelStatus(u8 ChannelIndx ); -ITStatus DMA_GetITStatus(u8 ChannelIndx,u8 DMA_ITReq); -void DMA_ClearIT(u8 ChannelIndx,u8 DMA_ITClr); -void DMA_SyncConfig(u16 DMA_SrcReq, FunctionalState NewState); -FlagStatus DMA_GetSReq(u16 DMA_SrcReq); -FlagStatus DMA_GetLSReq(u16 DMA_SrcReq); -FlagStatus DMA_GetBReq(u16 DMA_SrcReq); -FlagStatus DMA_GetLBReq(u16 DMA_SrcReq); -FlagStatus DMA_GetChannelActiveStatus( DMA_Channel_TypeDef * DMA_Channelx); -void DMA_SetSReq(u16 DMA_SrcReq); -void DMA_SetLSReq(u16 DMA_SrcReq); -void DMA_SetBReq(u16 DMA_SrcReq); -void DMA_SetLBReq(u16 DMA_SrcReq); -void DMA_ChannelCmd (DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState); -void DMA_ChannelHalt (DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState); -void DMA_ChannelBuffering (DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState); -void DMA_ChannelLockTrsf(DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState); -void DMA_ChannelCache(DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState); -void DMA_ChannelProt0Mode(DMA_Channel_TypeDef * DMA_Channelx,u32 Prot0Mode); -void DMA_ChannelSRCIncConfig (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState); -void DMA_ChannelDESIncConfig (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState); - -#endif /* __91x_DMA_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM9_STR91X_IAR/Library/include/91x_enet.h b/Demo/ARM9_STR91X_IAR/Library/include/91x_enet.h deleted file mode 100644 index c22d8dd22..000000000 --- a/Demo/ARM9_STR91X_IAR/Library/include/91x_enet.h +++ /dev/null @@ -1,357 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 91x_enet.h -* Author : MCD Application Team -* Date First Issued : May 2006 -* Description : ENET driver defines & function prototypes -******************************************************************************** -* History: -* May 2006: v1.0 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#ifndef _ENET_H_ -#define _ENET_H_ - -#include <91x_lib.h> - -#define ENET_BUFFER_SIZE 1520 -/*Structures typedef----------------------------------------------------------*/ - -/*Struct containing the DMA Descriptor data */ -typedef struct { - volatile u32 dmaStatCntl; /* DMA Status and Control Register */ - volatile u32 dmaAddr; /* DMA Start Address Register */ - volatile u32 dmaNext; /* DMA Next Descriptor Register */ - volatile u32 dmaPackStatus; /* DMA Packet Status and Control Register */ -} ENET_DMADSCRBase; - - -/* ENET_MACConfig Struct*/ -typedef struct { - FunctionalState ReceiveALL; /* Receive All frames: no address rule filtering */ - u32 MIIPrescaler; /* MII Clock Prescaler value */ - FunctionalState LoopbackMode; /* MAC Loopback mode */ - u32 AddressFilteringMode; /* Address Filtering Mode */ - u32 VLANFilteringMode; /* VLAN Filtering Mode */ - FunctionalState PassWrongFrame; /* Pass wrong frame (CRC, overlength, runt..)*/ - FunctionalState LateCollision; /* Retransmit frame when late collision*/ - FunctionalState BroadcastFrameReception; /* Accept broardcast frame */ - FunctionalState PacketRetry; /* Retransmit frame in case of collision */ - FunctionalState RxFrameFiltering; /* Filter early runt frame and address filter fail frames*/ - FunctionalState AutomaticPadRemoval; /* Automatic Padding removal */ - FunctionalState DeferralCheck; /* Excessive Defferal check */ -} ENET_MACConfig; - -/* ENET_TxStatus Struct*/ -typedef struct { - FlagStatus PacketRetry; - u8 ByteCount; - u8 collisionCount; - FlagStatus LateCollisionObserved; - FlagStatus Deffered; - FlagStatus UnderRun; - FlagStatus ExcessiveCollision; - FlagStatus LateCollision; - FlagStatus ExcessiveDefferal; - FlagStatus LossOfCarrier; - FlagStatus NoCarrier; - FlagStatus FrameAborted; -} ENET_TxStatus; - -/* ENET_RxStatus Struct*/ -typedef struct { - FlagStatus FrameAborted; - FlagStatus PacketFilter; - FlagStatus FilteringFail; - FlagStatus BroadCastFrame; - FlagStatus MulticastFrame; - FlagStatus UnsupportedControFrame; - FlagStatus ControlFrame; - FlagStatus LengthError; - FlagStatus Vlan2Tag; - FlagStatus Vlan1Tag; - FlagStatus CRCError; - FlagStatus ExtraBit; - FlagStatus MIIError; - FlagStatus FrameType; - FlagStatus LateCollision; - FlagStatus OverLength; - FlagStatus RuntFrame; - FlagStatus WatchDogTimout; - FlagStatus FalseCarrierIndication; - u16 FrameLength; -} ENET_RxStatus; - -/*Constants-------------------------------------------------------------------*/ - - -/* AddressFilteringMode */ -#define MAC_Perfect_Multicast_Perfect 0x0 -#define MAC_Perfect_Muticast_Hash 0x1<<17 -#define MAC_Hash_Multicast_Hash 0x3<<17 -#define Inverse 0x4<<17 -#define Promiscuous 0x5<<17 -#define MAC_Hash_Muticast_All 0x6<<17 - -/* VLANFilteringMode */ -#define VLANFilter_VLTAG_VLID 1 -#define VLANfilter_VLTAG 0 - -/* MIIPrescaler */ -#define MIIPrescaler_1 0 /* Prescaler for MDC clock when HCLK < 50 MHz */ -#define MIIPrescaler_2 1 /* Precaler for MDC when HCLK > = 50 MHz */ - - -/* MAC Address*/ -#define MAC_ADDR0 0x0D -#define MAC_ADDR1 0x0A -#define MAC_ADDR2 0x08 -#define MAC_ADDR3 0x04 -#define MAC_ADDR4 0x02 -#define MAC_ADDR5 0x01 - -/* Multicast Address */ -#define MCAST_ADDR0 0xFF -#define MCAST_ADDR1 0x00 -#define MCAST_ADDR2 0xFF -#define MCAST_ADDR3 0x00 -#define MCAST_ADDR4 0xFF -#define MCAST_ADDR5 0x00 - - - -#define ENET_MAX_PACKET_SIZE 1520 -#define ENET_NEXT_ENABLE 0x4000 - -/*ENET_OperatingMode*/ -/* Set the full/half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_100M 0x2100 -#define PHY_HALFDUPLEX_100M 0x2000 -/* Set the full/half-duplex mode at 10 Mb/s */ -#define PHY_FULLDUPLEX_10M 0x0100 -#define PHY_HALFDUPLEX_10M 0x0000 - - -/*----------------------------functions----------------------------------------*/ - -void ENET_MACControlConfig(ENET_MACConfig *MAC_Config); -void ENET_GetRxStatus(ENET_RxStatus * RxStatus); -void ENET_GetTxStatus(ENET_TxStatus * TxStatus); -long ENET_SetOperatingMode(void); -void ENET_InitClocksGPIO(void); -void ENET_MIIWriteReg (u8 phyDev, u8 phyReg, u32 phyVal); -u32 ENET_MIIReadReg (u8 phyDev, u32 phyReg ); -void ENET_RxDscrInit(void); -void ENET_TxDscrInit(void); -void ENET_Init(void); -void ENET_Start(void); -u32 ENET_RxPacketGetSize(void); -void ENET_TxPkt(void *ppkt, u16 size); -u32 ENET_HandleRxPkt(void *ppkt); - - -/*Driver internal constants---------------------------------------------------*/ - -/* MII Address */ -/* Description of bit field values of the MII Address Register */ -#define MAC_MIIA_PADDR 0x0000F800 -#define MAC_MII_ADDR_PHY_ADDR MAC_MIIA_PADDR /* Phy Address (default: 0): select one of 32 dev */ -#define MAC_MII_ADDR_MII_REG 0x000007C0 /* MII Register (default: 0) */ -#define MAC_MII_ADDR_MII_WRITE 0x00000002 /* MII Write */ -#define MAC_MIIA_PHY_DEV_ADDR (0x00005000 & MAC_MIIA_PADDR) /*To be changed if PHY device address changes */ -#define MAC_MII_ADDR_MII_BUSY 0x00000001 /* MII Busy */ - - -/* MII DATA register */ -#define MAC_MII_DATA_REG 0x0000FFFF /* MII Data */ - -/* MII Read / write timeouts*/ -#define MII_READ_TO 0x0004FFFF -#define MII_WRITE_TO 0x0004FFFF - -/* Description of common PHY registers */ -#define MAC_MII_REG_XCR 0x00000000 /* Tranceiver control register */ -#define MAC_MII_REG_XSR 0x00000001 /* Tranceiver status register */ -#define MAC_MII_REG_PID1 0x00000002 /* Tranceiver PHY identifier 1 */ -#define MAC_MII_REG_PID2 0x00000003 /* Tranceiver PHY identifier 2 */ -#define MAC_MII_REG_ANA 0x00000004 /* Auto-Negociation Advertissement register */ -#define MAC_MII_REG_ANLPA 0x00000005 /* Auto-Negociation Link Partner Ability register */ -#define MAC_MII_REG_ANE 0x00000006 /* Auto-Negociation Expansion register */ - - - - -/* MAC_MCR register fields */ -#define MAC_MCR_RA 0x80000000 -#define MAC_MCR_EN 0x40000000 -#define MAC_MCR_PS 0x03000000 -#define MAC_MCR_DRO 0x00800000 -#define MAC_MCR_LM 0x00600000 -#define MAC_MCR_FDM 0x00100000 -#define MAC_MCR_AFM 0x000E0000 -#define MAC_MCR_PWF 0x00010000 -#define MAC_MCR_VFM 0x00008000 -#define MAC_MCR_ELC 0x00001000 -#define MAC_MCR_DBF 0x00000800 -#define MAC_MCR_DPR 0x00000400 -#define MAC_MCR_RVFF 0x00000200 -#define MAC_MCR_APR 0x00000100 -#define MAC_MCR_BL 0x000000C0 -#define MAC_MCR_DCE 0x00000020 -#define MAC_MCR_RVBE 0x00000010 -#define MAC_MCR_TE 0x00000008 -#define MAC_MCR_RE 0x00000004 -#define MAC_MCR_RCFA 0x00000001 - -/* MTS */ -#define MAC_MTS_FA 0x00000001 -#define MAC_MTS_NC 0x00000004 -#define MAC_MTS_LOC 0x00000008 -#define MAC_MTS_ED 0x00000010 -#define MAC_MTS_LC 0x00000020 -#define MAC_MTS_EC 0x00000040 -#define MAC_MTS_UR 0x00000080 -#define MAC_MTS_DEF 0x00000100 -#define MAC_MTS_LCO 0x00000200 -#define MAC_MTS_CC 0x00003C00 -#define MAC_MTS_BC 0x7FFC0000 -#define MAC_MTS_PR 0x80000000 - -/* MRS */ -#define MAC_MRS_FL 0x000007FF -#define MAC_MRS_FCI 0x00002000 -#define MAC_MRS_WT 0x00004000 -#define MAC_MRS_RF 0x00008000 -#define MAC_MRS_OL 0x00010000 -#define MAC_MRS_LC 0x00020000 -#define MAC_MRS_FT 0x00040000 -#define MAC_MRS_ME 0x00080000 -#define MAC_MRS_EB 0x00100000 -#define MAC_MRS_CE 0x00200000 -#define MAC_MRS_VL1 0x00400000 -#define MAC_MRS_VL2 0x00800000 -#define MAC_MRS_LE 0x01000000 -#define MAC_MRS_CF 0x02000000 -#define MAC_MRS_UCF 0x04000000 -#define MAC_MRS_MCF 0x08000000 -#define MAC_MRS_BF 0x10000000 -#define MAC_MRS_FF 0x20000000 -#define MAC_MRS_PF 0x40000000 -#define MAC_MRS_FA 0x80000000 - -/* SCR */ -#define DMA_SCR_SRESET 0x00000001 /* Soft Reset (DMA_SCR_RESET) */ -#define DMA_SCR_LOOPB 0x00000002 /* Loopback mode (DMA_SCR_LOOPB) */ -#define DMA_SCR_RX_MBSIZE 0x00000010 /* Max defined burst length in RX mode (DMA_SCR_RX_MAX_BURST_...) */ -#define DMA_SCR_TX_MBSIZE 0x000000C0 /* Max defined burst length in TX mode (DMA_SCR_TX_MAX_BURST_...) */ -#define DMA_SCR_RX_MAX_BURST_SZ DMA_SCR_RX_MBSIZE /* Maximum value of defined burst length in RX mode */ -#define DMA_SCR_RX_MAX_BURST_SZ_VAL 0x00000000 /* Default value of burst length in RX mode */ -#define DMA_SCR_TX_MAX_BURST_SZ DMA_SCR_TX_MBSIZE /* Maximum value of defined burst length in TX mode */ -#define DMA_SCR_TX_MAX_BURST_SZ_VAL 0x000000C0 /* Default value of burst length in TX mode */ - - -/* DMA_RX_START */ -#define DMA_RX_START_DMAEN 0x00000001 -#define DMA_RX_START_STFETCH 0x00000004 -#define DMA_RX_START_FFAIL 0x00000020 -#define DMA_RX_START_RUNT 0x00000040 -#define DMA_RX_START_COLLS 0x00000080 -#define DMA_RX_START_DMA_EN 0x00000001 /* set = 0 by sw force a DMA abort */ -#define DMA_RX_START_FETCH 0x00000004 /* start fetching the 1st descriptor */ -#define DMA_RX_START_FILTER_FAIL 0x00000020 /* if = 1 the address filtering failed cond */ -#define DMA_RX_START_RUNT 0x00000040 /* discard damaged RX frames from cpu charge */ -#define DMA_RX_START_COLLS_SEEN 0x00000080 /* Late Collision Seen Cond discard frame automat. */ -#define DMA_RX_START_DFETCH_DLY 0x00FFFF00 /* Descriptor Fetch Delay */ -#define DMA_RX_START_DFETCH_DLY_POS 8 -#define DMA_RX_START_DFETCH_DEFAULT 0x00010000 /* Descriptor Fetch Delay default value */ - -/* DMA_DSCR_PACK_STAT */ -#define DMA_DSCR_PACK_STAT 0x00010000 - - -/* DMA_TX_START */ -#define DMA_TX_START_DMAEN 0x00000001 -#define DMA_TX_START_STFETCH 0x00000004 -#define DMA_TX_START_URUN 0x00000020 -#define DMA_TX_START_DISPAD 0x00000040 -#define DMA_TX_START_ADDCTC 0x00000080 -#define DMA_TX_START_DMA_EN 0x00000001 /* set = 0 by sw force a DMA abort */ -#define DMA_TX_START_FETCH 0x00000004 /* start fetching the 1st descriptor */ -#define DMA_RX_START_FILTER_FAIL 0x00000020 /* if = 1 the address filtering failed cond */ -#define DMA_TX_START_DFETCH_DLY 0x00FFFF00 /* Descriptor Fetch Delay */ -#define DMA_TX_START_DFETCH_DEFAULT 0x00010000 /* Descriptor Fetch Delay */ -#define DMA_TX_START_DFETCH_DLY_POS 0x8 -#define DMA_TX_START_URUN 0x00000020 -#define DMA_TX_START_DIS_PADDING 0x00000040 /* Avoid automatic addition of padding bits by MAC*/ -#define DMA_TX_START_ADD_CRC_DIS 0x00000080 /* Tell MAC not to ADD CRC field at end of frame */ - -/* DMA_DSCR_CNTL */ -#define DMA_DSCR_CNTL_XFERCOUNT 0x00000FFF -#define DMA_DSCR_CNTL_NXTEN 0x00004000 - -/* DMA_DSCR_ADDR */ -#define DMA_DSCR_ADDR 0xFFFFFFFC /* for DMA Start Address (32 bit Word Align) */ -#define DMA_DSCR_ADDR_FIX_ADDR 0x00000002 /* Disable incrementing of DMA_ADDR */ -#define DMA_DSCR_ADDR_WRAPEN_SET 0x00000001 -#define DMA_DSCR_ADDR_WRAPEN_RST 0x00000000 - -/* DMA_DSCR_NEXT_ADDR TX/RX */ -#define DMA_DSCR_NXT_DSCR_ADDR 0xFFFFFFFC /* Points to Next descriptor starting address */ -#define DMA_DSCR_NXT_NPOL_EN 0x00000001 /* Next Descriptor Polling Enable */ -#define DMA_DSCR_NXT_NEXT_EN 0x00000002 /* Next Descriptor Fetch mode Enable */ - -/* DMA Descriptor Packet Status: TX */ -#define DMA_DSCR_TX_STATUS_FA_MSK 0x00000001 /* Frame Aborted */ -#define DMA_DSCR_TX_STATUS_JTO_MSK 0x00000002 /* Jabber Timeout. */ -#define DMA_DSCR_TX_STATUS_NOC_MSK 0x00000004 /* No Carrier */ -#define DMA_DSCR_TX_STATUS_LOC_MSK 0x00000008 /* Loss of Carrier */ -#define DMA_DSCR_TX_STATUS_EXCD_MSK 0x00000010 /* Excessive Deferral */ -#define DMA_DSCR_TX_STATUS_LCOLL_MSK 0x00000020 /* Late Collision */ -#define DMA_DSCR_TX_STATUS_ECOLL_MSK 0x00000040 /* Excessive Collisions */ -#define DMA_DSCR_TX_STATUS_URUN_MSK 0x00000080 /* Under Run */ -#define DMA_DSCR_TX_STATUS_DEFER_MSK 0x00000100 /* Deferred */ -#define DMA_DSCR_TX_STATUS_LCOLLO_MSK 0x00000200 /* Late Collision Observed */ -#define DMA_DSCR_TX_STATUS_CCNT_MSK 0x00003C00 /* Collision Count */ -#define DMA_DSCR_TX_STATUS_HBFAIL_MSK 0x00004000 /* Heart Beat Fail */ -#define DMA_DSCR_TX_STATUS_VALID_MSK 0x00010000 /* Valid bit indicator - This bit marks the dscriptors this word belong */ -#define DMA_DSCR_TX_STATUS_PKT_RTRY_MSK 0x80000000 /* Packet Retry */ -#define DMA_DSCR_TX_STATUS_ORED_ERR_MSK 0x000003D7 /* for total number of errors */ - -/* DMA Descriptor Packet Status: RX */ -#define DMA_DSCR_RX_STATUS_FLEN_MSK 0x000007ff /* 0x00003FFF * Frame Length (max 2047) */ -#define DMA_DSCR_RX_STATUS_FTLONG_MSK 0x00001000 /* Over Lenght */ -#define DMA_DSCR_RX_STATUS_FCI_MSK 0x00002000 /* Frame too Long */ -#define DMA_DSCR_RX_STATUS_WDTO_MSK 0x00004000 /* Watchdog Timeout */ -#define DMA_DSCR_RX_STATUS_RUNTFR_MSK 0x00008000 /* Runt Frame */ -#define DMA_DSCR_RX_STATUS_VALID_MSK 0x00010000 /* Valid bit indicator - This bit marks the dscriptors this word */ -#define DMA_DSCR_RX_STATUS_COLLSEEN_MSK 0x00020000 /* Collision Seen */ -#define DMA_DSCR_RX_STATUS_FTYPE_MSK 0x00040000 /* Frame Type */ -#define DMA_DSCR_RX_STATUS_MII_ERR_MSK 0x00080000 /* MII Error */ -#define DMA_DSCR_RX_STATUS_DRBBIT_MSK 0x00100000 /* Dribbling Bit */ -#define DMA_DSCR_RX_STATUS_CRC_ERR_MSK 0x00200000 /* CRC Error */ -#define DMA_DSCR_RX_STATUS_VLAN1_FR_MSK 0x00400000 /* One-Level VLAN Frame */ -#define DMA_DSCR_RX_STATUS_VLAN2_FR_MSK 0x00800000 /* Two-Level VLAN Frame */ -#define DMA_DSCR_RX_STATUS_LEN_ERR_MSK 0x01000000 /* Length Error */ -#define DMA_DSCR_RX_STATUS_CTL_FR_MSK 0x02000000 /* Control Frame */ -#define DMA_DSCR_RX_STATUS_UCTRL_FR_MSK 0x04000000 /* Unsupported Control Frame */ -#define DMA_DSCR_RX_STATUS_MCAST_FR_MSK 0x08000000 /* Multicast Frame */ -#define DMA_DSCR_RX_STATUS_BCAST_FR_MSK 0x10000000 /* BroadCast Frame */ -#define DMA_DSCR_RX_STATUS_FLT_FAIL_MSK 0x20000000 /* Filtering Fail */ -#define DMA_DSCR_RX_STATUS_PKT_FILT_MSK 0x40000000 /* Packet Filter */ -#define DMA_DSCR_RX_STATUS_MIS_FR_MSK 0x80000000 /* Missed Frame */ -#define DMA_DSCR_RX_STATUS_ERROR_MSK (DMA_DSCR_RX_STATUS_LEN_ERR | DMA_DSCR_RX_STATUS_CRC_ERR | \ - DMA_DSCR_RX_STATUS_MII_ERR | DMA_DSCR_RX_STATUS_RUNTFR | \ - DMA_DSCR_RX_STATUS_FTLONG | DMA_DSCR_RX_STATUS_COLLSEEN) -#define DMA_DSCR_RX_STATUS_ORED_ERR_MSK 0x00000000 /*Mask for total number of errors */ - - -#endif /* _ENET_H_ */ - -/******************** (C) COPYRIGHT 2006 STMicroelectronics *******************/ - diff --git a/Demo/ARM9_STR91X_IAR/Library/include/91x_fmi.h b/Demo/ARM9_STR91X_IAR/Library/include/91x_fmi.h deleted file mode 100644 index 06e811567..000000000 --- a/Demo/ARM9_STR91X_IAR/Library/include/91x_fmi.h +++ /dev/null @@ -1,184 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 91x_fmi.h -* Author : MCD Application Team -* Date First Issued : 05/18/2006 : Version 1.0 -* Description : This file contains all the functions prototypes for the -* FMI software library. -******************************************************************************** -* History: -* 05/24/2006 : Version 1.1 -* 05/18/2006 : Version 1.0 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH -* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS -* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT -* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT -* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION -* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - - -/* Define to prevent recursive inclusion ------------------------------------ */ - -#ifndef __91x_FMI_H -#define __91x_FMI_H - -/* ========================================================================== */ -/* When bank 1 is remapped at address 0x0, decomment the following line */ -/* ========================================================================== */ - -//#define Remap_Bank_1 - - -/* Includes ------------------------------------------------------------------*/ - -#include "91x_map.h" - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* FMI banks */ - -#ifdef Remap_Bank_1 - -#define FMI_BANK_0 ((*(vu32*)0x54000010) << 2) /* FMI Bank 0 */ -#define FMI_BANK_1 ((*(vu32*)0x5400000C) << 2) /* FMI Bank 1 */ - -#else /* Remap Bank 0 */ - -#define FMI_BANK_0 ((*(vu32*)0x5400000C) << 2) /* FMI Bank 0 */ -#define FMI_BANK_1 ((*(vu32*)0x54000010) << 2) /* FMI Bank 1 */ - -#endif - -/* FMI sectors */ - -#define FMI_B0S0 0x00000000 + FMI_BANK_0 /* Bank 0 sector 0 */ -#define FMI_B0S1 0x00010000 + FMI_BANK_0 /* Bank 0 sector 1 */ -#define FMI_B0S2 0x00020000 + FMI_BANK_0 /* Bank 0 sector 2 */ -#define FMI_B0S3 0x00030000 + FMI_BANK_0 /* Bank 0 sector 3 */ -#define FMI_B0S4 0x00040000 + FMI_BANK_0 /* Bank 0 sector 4 */ -#define FMI_B0S5 0x00050000 + FMI_BANK_0 /* Bank 0 sector 5 */ -#define FMI_B0S6 0x00060000 + FMI_BANK_0 /* Bank 0 sector 6 */ -#define FMI_B0S7 0x00070000 + FMI_BANK_0 /* Bank 0 sector 7 */ - -#define FMI_B1S0 0x00000000 + FMI_BANK_1 /* Bank 1 sector 0 */ -#define FMI_B1S1 0x00002000 + FMI_BANK_1 /* Bank 1 sector 1 */ -#define FMI_B1S2 0x00004000 + FMI_BANK_1 /* Bank 1 sector 2 */ -#define FMI_B1S3 0x00006000 + FMI_BANK_1 /* Bank 1 sector 3 */ - -/* FMI Flags */ - -#define FMI_FLAG_SPS 0x02 /* Sector Protection Status Flag */ -#define FMI_FLAG_PSS 0x04 /* Program Suspend Status Flag */ -#define FMI_FLAG_PS 0x10 /* Program Status Flag */ -#define FMI_FLAG_ES 0x20 /* Erase Status Flag */ -#define FMI_FLAG_ESS 0x40 /* Erase Suspend Status Flag */ -#define FMI_FLAG_PECS 0x80 /* FPEC Status Flag */ - -/* FMI read wait states */ - -#define FMI_READ_WAIT_STATE_1 0x0000 /* One read wait state */ -#define FMI_READ_WAIT_STATE_2 0x2000 /* Two read wait states */ -#define FMI_READ_WAIT_STATE_3 0x4000 /* Three read wait states */ - -/* FMI write wait states */ - -#define FMI_WRITE_WAIT_STATE_0 0xFFFFFEFF /* Zero wait state */ -#define FMI_WRITE_WAIT_STATE_1 0x00000100 /* One wait state */ - -/* FMI power down configuration */ - -#define FMI_PWD_ENABLE 0x1000 /* FMI Power Down Enable */ -#define FMI_PWD_DISABLE 0x0000 /* FMI Power Down Disable */ - -/* FMI low voltage detector */ - -#define FMI_LVD_ENABLE 0x0000 /* FMI Low Voltage Detector Enable */ -#define FMI_LVD_DISABLE 0x0800 /* FMI Low Voltage Detector Disable */ - -/* FMI frequency range */ - -#define FMI_FREQ_LOW 0x0000 /* FMI Low bus working frequency */ -#define FMI_FREQ_HIGH 0x0040 /* FMI High bus working gfrequency */ - /* Above 66 MHz*/ -/* FMI OTP word addresses */ - -#define FMI_OTP_WORD_0 0x00 /* OTP word 0 */ -#define FMI_OTP_WORD_1 0x04 /* OTP word 1 */ -#define FMI_OTP_WORD_2 0x08 /* OTP word 2 */ -#define FMI_OTP_WORD_3 0x0C /* OTP word 3 */ -#define FMI_OTP_WORD_4 0x10 /* OTP word 4 */ -#define FMI_OTP_WORD_5 0x14 /* OTP word 5 */ -#define FMI_OTP_WORD_6 0x18 /* OTP word 6 */ -#define FMI_OTP_WORD_7 0x1C /* OTP word 7 */ - -/* FMI OTP halfword addresses */ - -#define FMI_OTP_LOW_HALFWORD_0 0x00 /* OTP Low halfword 0 */ -#define FMI_OTP_HIGH_HALFWORD_0 0x02 /* OTP High halfword 0 */ -#define FMI_OTP_LOW_HALFWORD_1 0x04 /* OTP Low halfword 1 */ -#define FMI_OTP_HIGH_HALFWORD_1 0x06 /* OTP High halfword 1 */ -#define FMI_OTP_LOW_HALFWORD_2 0x08 /* OTP Low halfword 2 */ -#define FMI_OTP_HIGH_HALFWORD_2 0x0A /* OTP High halfword 2 */ -#define FMI_OTP_LOW_HALFWORD_3 0x0C /* OTP Low halfword 3 */ -#define FMI_OTP_HIGH_HALFWORD_3 0x0E /* OTP High halfword 3 */ -#define FMI_OTP_LOW_HALFWORD_4 0x10 /* OTP Low halfword 4 */ -#define FMI_OTP_HIGH_HALFWORD_4 0x12 /* OTP High halfword 4 */ -#define FMI_OTP_LOW_HALFWORD_5 0x14 /* OTP Low halfword 5 */ -#define FMI_OTP_HIGH_HALFWORD_5 0x16 /* OTP High halfword 5 */ -#define FMI_OTP_LOW_HALFWORD_6 0x18 /* OTP Low halfword 6 */ -#define FMI_OTP_HIGH_HALFWORD_6 0x1A /* OTP High halfword 6 */ -#define FMI_OTP_LOW_HALFWORD_7 0x1C /* OTP Low halfword 7 */ -#define FMI_OTP_HIGH_HALFWORD_7 0x1E /* OTP High halfword 7 */ - -/* FMI sectors Masks */ - -#define FMI_B0S0_MASK 0x0001 /* FMI B0S0 mask */ -#define FMI_B0S1_MASK 0x0002 /* FMI B0S1 mask */ -#define FMI_B0S2_MASK 0x0004 /* FMI B0S2 mask */ -#define FMI_B0S3_MASK 0x0008 /* FMI B0S3 mask */ -#define FMI_B0S4_MASK 0x0010 /* FMI B0S4 mask */ -#define FMI_B0S5_MASK 0x0020 /* FMI B0S5 mask */ -#define FMI_B0S6_MASK 0x0040 /* FMI B0S6 mask */ -#define FMI_B0S7_MASK 0x0080 /* FMI B0S7 mask */ - -#define FMI_B1S0_MASK 0x0100 /* FMI B1S0 mask */ -#define FMI_B1S1_MASK 0x0200 /* FMI B1S1 mask */ -#define FMI_B1S2_MASK 0x0400 /* FMI B1S2 mask */ -#define FMI_B1S3_MASK 0x0800 /* FMI B1S3 mask */ - -/* Timeout error */ - -#define FMI_TIME_OUT_ERROR 0x00 /* Timeout error */ -#define FMI_NO_TIME_OUT_ERROR 0x01 /* No Timeout error */ - -/* Module private variables --------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -void FMI_BankRemapConfig(u8 FMI_BootBankSize, u8 FMI_NonBootBankSize, \ - u32 FMI_BootBankAddress, u32 FMI_NonBootBankAddress); -void FMI_Config(u16 FMI_ReadWaitState, u32 FMI_WriteWaitState, u16 FMI_PWD,\ - u16 FMI_LVDEN, u16 FMI_FreqRange); -void FMI_EraseSector(vu32 FMI_Sector); -void FMI_EraseBank(vu32 FMI_Bank); -void FMI_WriteHalfWord(u32 FMI_Address, u16 FMI_Data); -void FMI_WriteOTPHalfWord(u8 FMI_OTPHWAddress, u16 FMI_OTPData); -u32 FMI_ReadWord(u32 FMI_Address); -u32 FMI_ReadOTPData(u8 FMI_OTPAddress); -FlagStatus FMI_GetFlagStatus(u8 FMI_Flag, vu32 FMI_Bank); -u16 FMI_GetReadWaitStateValue(void); -u16 FMI_GetWriteWaitStateValue(void); -void FMI_SuspendEnable(vu32 FMI_Bank); -void FMI_ResumeEnable(vu32 FMI_Bank); -void FMI_ClearFlag(vu32 FMI_Bank); -void FMI_WriteProtectionCmd(vu32 FMI_Sector, FunctionalState FMI_NewState); -FlagStatus FMI_GetWriteProtectionStatus(u32 FMI_Sector_Protection); -u8 FMI_WaitForLastOperation(vu32 FMI_Bank); - -#endif /* __91x_FMI_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ - diff --git a/Demo/ARM9_STR91X_IAR/Library/include/91x_gpio.h b/Demo/ARM9_STR91X_IAR/Library/include/91x_gpio.h deleted file mode 100644 index f4e565804..000000000 --- a/Demo/ARM9_STR91X_IAR/Library/include/91x_gpio.h +++ /dev/null @@ -1,93 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 91x_gpio.h -* Author : MCD Application Team -* Date First Issued : 05/18/2006 : Version 1.0 -* Description : This file contains all the functions prototypes for the -* GPIO software library. -******************************************************************************** -* History: -* 05/24/2006 : Version 1.1 -* 05/18/2006 : Version 1.0 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH -* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS -* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT -* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT -* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION -* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion ------------------------------------ */ - -#ifndef _91x_GPIO_H -#define _91x_GPIO_H - -/* Includes ------------------------------------------------------------------*/ -#include "91x_map.h" - -/* GPIO Init structure definition */ -typedef struct -{ - u8 GPIO_Pin; - u8 GPIO_Direction; - u8 GPIO_Type; - u8 GPIO_IPConnected; - u16 GPIO_Alternate; -}GPIO_InitTypeDef; - -/* Bit_SET and Bit_RESET enumeration */ -typedef enum -{ Bit_RESET = 0, - Bit_SET -}BitAction; - - -/* Exported constants --------------------------------------------------------*/ -#define GPIO_Pin_None 0x00 -#define GPIO_Pin_0 0x01 -#define GPIO_Pin_1 0x02 -#define GPIO_Pin_2 0x04 -#define GPIO_Pin_3 0x08 -#define GPIO_Pin_4 0x10 -#define GPIO_Pin_5 0x20 -#define GPIO_Pin_6 0x40 -#define GPIO_Pin_7 0x80 -#define GPIO_Pin_All 0xFF - -#define GPIO_PinInput 0x00 -#define GPIO_PinOutput 0x01 - -#define GPIO_Type_PushPull 0x00 -#define GPIO_Type_OpenCollector 0x01 - -#define GPIO_IPConnected_Disable 0x00 -#define GPIO_IPConnected_Enable 0x01 - -#define GPIO_InputAlt1 0x00 -#define GPIO_OutputAlt1 0x01 -#define GPIO_OutputAlt2 0x02 -#define GPIO_OutputAlt3 0x03 - -#define GPIO_ANAChannel0 0x01 -#define GPIO_ANAChannel1 0x02 -#define GPIO_ANAChannel2 0x04 -#define GPIO_ANAChannel3 0x08 -#define GPIO_ANAChannel4 0x10 -#define GPIO_ANAChannel5 0x20 -#define GPIO_ANAChannel6 0x40 -#define GPIO_ANAChannel7 0x80 -#define GPIO_ANAChannelALL 0xFF - -void GPIO_DeInit(GPIO_TypeDef* GPIOx); -void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); -void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); -u8 GPIO_ReadBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin); -u8 GPIO_Read(GPIO_TypeDef* GPIOx); -void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin, BitAction BitVal); -void GPIO_Write(GPIO_TypeDef* GPIOx, u8 PortVal); -void GPIO_EMIConfig(FunctionalState NewState); -void GPIO_ANAPinConfig(u8 GPIO_ANAChannel, FunctionalState NewState); - -#endif /* _91x_GPIO_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM9_STR91X_IAR/Library/include/91x_it.h b/Demo/ARM9_STR91X_IAR/Library/include/91x_it.h deleted file mode 100644 index a8e35fcb1..000000000 --- a/Demo/ARM9_STR91X_IAR/Library/include/91x_it.h +++ /dev/null @@ -1,73 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 91x_it.h -* Author : MCD Application Team -* Date First Issued : 05/18/2006 : Version 1.0 -* Description : This file contains the headers of the interrupt -* handlers'routines -******************************************************************************** -* History: -* 05/24/2006 : Version 1.1 -* 05/18/2006 : Version 1.0 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH -* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS -* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT -* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT -* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION -* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion ------------------------------------ */ -#ifndef _91x_IT_H -#define _91x_IT_H - -/* Includes ------------------------------------------------------------------*/ -#include "91x_lib.h" - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Module private variables --------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -void Undefined_Handler (void); -void SWI_Handler (void); -void Prefetch_Handler (void); -void Abort_Handler (void); -void FIQ_Handler (void); -void WDG_IRQHandler (void); -void SW_IRQHandler (void); -void ARMRX_IRQHandler (void); -void ARMTX_IRQHandler (void); -void TIM0_IRQHandler (void); -void TIM1_IRQHandler (void); -void TIM2_IRQHandler (void); -void TIM3_IRQHandler (void); -void USBHP_IRQHandler (void); -void USBLP_IRQHandler (void); -void SCU_IRQHandler (void); -void ENET_IRQHandler (void); -void DMA_IRQHandler (void); -void CAN_IRQHandler (void); -void MC_IRQHandler (void); -void ADC_IRQHandler (void); -void UART0_IRQHandler (void); -void UART1_IRQHandler (void); -void UART2_IRQHandler (void); -void I2C0_IRQHandler (void); -void I2C1_IRQHandler (void); -void SSP0_IRQHandler (void); -void SSP1_IRQHandler (void); -void LVD_IRQHandler (void); -void RTC_IRQHandler (void); -void WIU_IRQHandler (void); -void EXTIT0_IRQHandler (void); -void EXTIT1_IRQHandler (void); -void EXTIT2_IRQHandler (void); -void EXTIT3_IRQHandler (void); -void USBWU_IRQHandler (void); -void PFQBC_IRQHandler (void); - -#endif /* _91x_IT_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM9_STR91X_IAR/Library/include/91x_lib.h b/Demo/ARM9_STR91X_IAR/Library/include/91x_lib.h deleted file mode 100644 index 823b25012..000000000 --- a/Demo/ARM9_STR91X_IAR/Library/include/91x_lib.h +++ /dev/null @@ -1,114 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 91x_lib.h -* Author : MCD Application Team -* Date First Issued : 05/18/2006 : Version 1.0 -* Description : Used to include the peripherals header file in the -* user application. -******************************************************************************** -* History: -* 05/24/2006 : Version 1.1 -* 05/18/2006 : Version 1.0 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH -* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS -* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT -* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT -* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION -* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#ifndef __91x_LIB_H -#define __91x_LIB_H - -#include "91x_map.h" -#include "91x_conf.h" - -#ifdef _AHBAPB - #include "91x_ahbapb.h" -#endif /* _AHBAPB */ - -#ifdef _EMI - #include "91x_emi.h" -#endif /* _EMI */ - -#ifdef _DMA - #include "91x_dma.h" -#endif /* _DMA */ - -#ifdef _FMI - #include "91x_fmi.h" -#endif /* _FMI */ - -#ifdef _VIC - #include "91x_vic.h" -#endif /* _VIC */ - -#ifdef _WIU - #include "91x_wiu.h" -#endif /* _WIU */ - -#ifdef _TIM - #include "91x_tim.h" -#endif /* _TIM */ - -#ifdef _GPIO - #include "91x_gpio.h" -#endif /* _GPIO */ - -#ifdef _RTC - #include "91x_rtc.h" -#endif /* _RTC */ - -#ifdef _SCU - #include "91x_scu.h" -#endif /* _SCU */ - -#ifdef _UART - #include "91x_uart.h" -#endif /* _UART */ - -#ifdef _SSP - #include "91x_ssp.h" -#endif /* _SSP */ - -#ifdef _CAN - #include "91x_can.h" -#endif /* _CAN */ - -#ifdef _ADC - #include "91x_adc.h" -#endif /* _ADC */ - -#ifdef _WDG - #include "91x_wdg.h" -#endif /* _WDG */ - -#ifdef _I2C - #include "91x_i2c.h" -#endif /* _I2C */ - -#ifdef _WIU - #include "91x_wiu.h" -#endif - -#ifdef _MC - #include "91x_mc.h" -#endif - -#ifdef _ENET - #include "91x_enet.h" -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Module private variables --------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - - void debug( void ); - - -#endif /* __91x_LIB_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM9_STR91X_IAR/Library/include/91x_map.h b/Demo/ARM9_STR91X_IAR/Library/include/91x_map.h deleted file mode 100644 index e405a2630..000000000 --- a/Demo/ARM9_STR91X_IAR/Library/include/91x_map.h +++ /dev/null @@ -1,878 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 91x_map.h -* Author : MCD Application Team -* Date First Issued : 05/18/2006 : Version 1.0 -* Description : Peripherals registers definition and memory mapping. -******************************************************************************** -* History: -* 05/24/2006 : Version 1.1 -* 05/18/2006 : Version 1.0 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH -* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS -* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT -* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT -* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION -* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion ------------------------------------ */ -#ifndef __91x_MAP_H -#define __91x_MAP_H - -#ifndef EXT - #define EXT extern -#endif /* EXT */ - -/* Includes ------------------------------------------------------------------*/ -#include "91x_conf.h" -#include "91x_type.h" - -/******************************************************************************/ -/* IP registers structures */ -/******************************************************************************/ - -/*------------------------------------ FMI -----------------------------------*/ - -typedef struct -{ - vu32 BBSR; /* Boot Bank Size Register */ - vu32 NBBSR; /* Non-Boot Bank Size Register */ - vu32 EMPTY1; - vu32 BBADR; /* Boot Bank Base Address Register */ - vu32 NBBADR; /* Non-Boot Bank Base Address Register */ - vu32 EMPTY2; - vu32 CR; /* Control Register */ - vu32 SR; /* Status Register */ - vu32 BCE5ADDR; /* BC Fifth Entry Target Address Register */ -} FMI_TypeDef; - -/*---------------------- Analog to Digital Convertor ------------------------*/ - -typedef struct -{ - vu16 CR; /* Control Register */ - vu16 EMPTY1; - vu16 CCR; /* Channel Configuration Register */ - vu16 EMPTY2; - vu16 HTR; /* Higher Threshold Register */ - vu16 EMPTY3; - vu16 LTR; /* Lower Threshold Register */ - vu16 EMPTY4; - vu16 CRR; /* Compare Result Register */ - vu16 EMPTY5; - vu16 DR0; /* Data Register for Channel 0 */ - vu16 EMPTY6; - vu16 DR1; /* Data Register for Channel 1 */ - vu16 EMPTY7; - vu16 DR2; /* Data Register for Channel 2 */ - vu16 EMPTY8; - vu16 DR3; /* Data Register for Channel 3 */ - vu16 EMPTY9; - vu16 DR4; /* Data Register for Channel 4 */ - vu16 EMPTY10; - vu16 DR5; /* Data Register for Channel 5 */ - vu16 EMPTY11; - vu16 DR6; /* Data Register for Channel 6 */ - vu16 EMPTY12; - vu16 DR7; /* Data Register for Channel 7 */ - vu16 EMPTY13; - vu16 PRS; /* Prescaler Value Register */ - vu16 EMPTY14; -} ADC_TypeDef; - -/*--------------------- AHB APB BRIDGE registers strcture --------------------*/ - -typedef struct -{ - vu32 BSR; /* Bridge Status Register */ - vu32 BCR; /* Bridge Configuration Register */ - vu32 PAER; /* Peripheral Address Error register */ -} AHBAPB_TypeDef; - -/*--------------- Controller Area Network Interface Register -----------------*/ - -typedef struct -{ - vu16 CRR; /* IFn Command request Register */ - vu16 EMPTY1; - vu16 CMR; /* IFn Command Mask Register */ - vu16 EMPTY2; - vu16 M1R; /* IFn Message Mask 1 Register */ - vu16 EMPTY3; - vu16 M2R; /* IFn Message Mask 2 Register */ - vu16 EMPTY4; - vu16 A1R; /* IFn Message Arbitration 1 Register */ - vu16 EMPTY5; - vu16 A2R; /* IFn Message Arbitration 2 Register */ - vu16 EMPTY6; - vu16 MCR; /* IFn Message Control Register */ - vu16 EMPTY7; - vu16 DA1R; /* IFn DATA A 1 Register */ - vu16 EMPTY8; - vu16 DA2R; /* IFn DATA A 2 Register */ - vu16 EMPTY9; - vu16 DB1R; /* IFn DATA B 1 Register */ - vu16 EMPTY10; - vu16 DB2R; /* IFn DATA B 2 Register */ - vu16 EMPTY11[27]; -} CAN_MsgObj_TypeDef; - -typedef struct -{ - vu16 CR; /* Control Register */ - vu16 EMPTY1; - vu16 SR; /* Status Register */ - vu16 EMPTY2; - vu16 ERR; /* Error counter Register */ - vu16 EMPTY3; - vu16 BTR; /* Bit Timing Register */ - vu16 EMPTY4; - vu16 IDR; /* Interrupt Identifier Register */ - vu16 EMPTY5; - vu16 TESTR; /* Test Register */ - vu16 EMPTY6; - vu16 BRPR; /* BRP Extension Register */ - vu16 EMPTY7[3]; - CAN_MsgObj_TypeDef sMsgObj[2]; - vu16 EMPTY8[16]; - vu16 TXR1R; /* Transmission request 1 Register */ - vu16 EMPTY9; - vu16 TXR2R; /* Transmission Request 2 Register */ - vu16 EMPTY10[13]; - vu16 ND1R; /* New Data 1 Register */ - vu16 EMPTY11; - vu16 ND2R; /* New Data 2 Register */ - vu16 EMPTY12[13]; - vu16 IP1R; /* Interrupt Pending 1 Register */ - vu16 EMPTY13; - vu16 IP2R; /* Interrupt Pending 2 Register */ - vu16 EMPTY14[13]; - vu16 MV1R; /* Message Valid 1 Register */ - vu16 EMPTY15; - vu16 MV2R; /* Message VAlid 2 Register */ - vu16 EMPTY16; -} CAN_TypeDef; - -/*----------------------- System Control Unit---------------------------------*/ - -typedef struct -{ - vu32 CLKCNTR; /* Clock Control Register */ - vu32 PLLCONF; /* PLL Configuration Register */ - vu32 SYSSTATUS; /* System Status Register */ - vu32 PWRMNG; /* Power Management Register */ - vu32 ITCMSK; /* Interrupt Mask Register */ - vu32 PCGRO; /* Peripheral Clock Gating Register 0 */ - vu32 PCGR1; /* Peripheral Clock Gating Register 1 */ - vu32 PRR0; /* Peripheral Reset Register 0 */ - vu32 PRR1; /* Peripheral Reset Register 1 */ - vu32 MGR0; /* Idle Mode Mask Gating Register 0 */ - vu32 MGR1; /* Idle Mode Mask Gating Register 1 */ - vu32 PECGR0; /* Peripheral Emulation Clock Gating Register 0 */ - vu32 PECGR1; /* Peripheral Emulation Clock Gating Register 1 */ - vu32 SCR0; /* System Configuration Register 0 */ - vu32 SCR1; /* System Configuration Register 1 */ - vu32 SCR2; /* System Configuration Register 2 */ - u32 EMPTY1; - vu32 GPIOOUT[8]; /* GPIO Output Registers */ - vu32 GPIOIN[8]; /* GPIO Input Registers */ - vu32 GPIOTYPE[10]; /* GPIO Type Registers */ - vu32 GPIOEMI; /* GPIO EMI Selector Register */ - vu32 WKUPSEL; /* Wake-Up Selection Register */ - u32 EMPTY2[2]; - vu32 GPIOANA; /* GPIO Analag mode Register */ -} SCU_TypeDef; - -/*------------------------- DMA Channelx Registers ---------------------------*/ - -typedef struct -{ - vu32 SRC; /* Channelx Source Address Register */ - vu32 DES; /* Channelx Destination Address Register */ - vu32 LLI; /* Channelx Lincked List Item Register */ - vu32 CC; /* Channelx Contol Register */ - vu32 CCNF; /* Channelx Configuration Register */ -} DMA_Channel_TypeDef; - -/* x can be ,0,1,2,3,4,5,6 or 7. There are eight Channels AHB BUS Master */ - -/*----------------------------- DMA Controller -------------------------------*/ - -typedef struct -{ - vu32 ISR; /* Interrupt Status Register */ - vu32 TCISR; /* Terminal Count Interrupt Status Register */ - vu32 TCICR; /* Terminal CountInterrupt Clear Register */ - vu32 EISR; /* Error Interrupt Status Register */ - vu32 EICR; /* Error Interrupt Clear Register */ - vu32 TCRISR; /* Terminal Count Raw Interrupt Status Register */ - vu32 ERISR; /* Raw Error Interrupt Status Register */ - vu32 ENCSR; /* Enabled Channel Status Register */ - vu32 SBRR; /* Software Burst Request Register */ - vu32 SSRR; /* Software Single Request Register */ - vu32 SLBRR; /* Software Last Burst Request Register */ - vu32 SLSRR; /* Software Last Single Request Register */ - vu32 CNFR; /* Configuration Register */ - vu32 SYNR; /* Syncronization Register */ -} DMA_TypeDef; - -/*--------------------------------- TIM Timer --------------------------------*/ - -typedef struct -{ - vu16 IC1R; /* Input Capture 1 Register */ - vu16 EMPTY1; - vu16 IC2R; /* Input Capture 2 Register */ - vu16 EMPTY2; - vu16 OC1R; /* Output Compare 1 Register */ - vu16 EMPTY3; - vu16 OC2R; /* Output Compare 2 Register */ - vu16 EMPTY4; - vu16 CNTR; /* Counter Register */ - vu16 EMPTY5; - vu16 CR1; /* Control Register 1 */ - vu16 EMPTY6; - vu16 CR2; /* Control Register 2 */ - vu16 EMPTY7; - vu16 SR; /* Status Register */ - vu16 EMPTY8; -} TIM_TypeDef; - -/*---------------------------- EMI Bankx Registers ---------------------------*/ - -typedef struct -{ - vu32 ICR; /* Bankx Idle Cycle Control Register */ - vu32 RCR; /* Bankx Read Wait State Control Register */ - vu32 WCR; /* Bankx Write Wait State Control Register */ - vu32 OECR; /* Bankx Output Enable Assertion Delay Control Register */ - vu32 WECR; /* Bankx Write Enable Assertion Delay Control Register */ - vu32 BCR; /* Bankx Control Register */ - } EMI_Bank_TypeDef; - -/*---------------------------- Ethernet Controller ---------------------------*/ - -/* MAC Registers */ -typedef struct -{ - vu32 MCR; /* ENET Control Register */ - vu32 MAH; /* ENET Address High Register */ - vu32 MAL; /* ENET Address Low Register */ - vu32 MCHA; /* Multicast Address High Register */ - vu32 MCLA; /* Multicast Address Low Register */ - vu32 MIIA; /* MII Address Register */ - vu32 MIID; /* MII Data Register */ - vu32 MCF; /* ENET Control Frame Register */ - vu32 VL1; /* VLAN1 Register */ - vu32 VL2; /* VLAN2 register */ - vu32 MTS; /* ENET Transmission Status Register */ - vu32 MRS; /* ENET Reception Status Register */ -} ENET_MAC_TypeDef; - -/* DMA Registers */ -typedef struct -{ - vu32 SCR; /* DMA Status and Control Register */ - vu32 IER; /* DMA Interrupt Sources Enable Register */ - vu32 ISR; /* DMA Interrupt Status Register */ - vu32 CCR; /* Clock Control Relation : HCLK, PCLK and - ENET_CLK phase relations */ - vu32 RXSTR; /* Rx DMA start Register */ - vu32 RXCR; /* Rx DMA Control Register */ - vu32 RXSAR; /* Rx DMA Base Address Register */ - vu32 RXNDAR; /* Rx DMA Next Descriptor Address Register */ - vu32 RXCAR; /* Rx DMA Current Address Register */ - vu32 RXCTCR; /* Rx DMA Current Transfer Count Register */ - vu32 RXTOR; /* Rx DMA FIFO Time Out Register */ - vu32 RXSR; /* Rx DMA FIFO Status Register */ - vu32 TXSTR; /* Tx DMA start Register */ - vu32 TXCR; /* Tx DMA Control Register */ - vu32 TXSAR; /* Tx DMA Base Address Register */ - vu32 TXNDAR; /* Tx DMA Next Descriptor Address Register */ - vu32 TXCAR; /* Tx DMA Current Address Register */ - vu32 TXTCR; /* Tx DMA Current Transfer Count Register */ - vu32 TXTOR; /* Tx DMA FIFO Time Out Register */ - vu32 TXSR; /* Tx DMA FIFO Status Register */ -} ENET_DMA_TypeDef; - -/*------------------------------------- GPIO ---------------------------------*/ - -typedef struct -{ - vu8 DR[1021]; /* Data Register */ - vu32 DDR; /* Data Direction Register */ -} GPIO_TypeDef; - -/*-------------------------------- I2C interface -----------------------------*/ - -typedef struct -{ - vu8 CR; /* Control Register */ - vu8 EMPTY1[3]; - vu8 SR1; /* Status Register 1 */ - vu8 EMPTY2[3]; - vu8 SR2; /* Status Register 2 */ - vu8 EMPTY3[3]; - vu8 CCR; /* Clock Control Register */ - vu8 EMPTY4[3]; - vu8 OAR1; /* Own Address Register 1 */ - vu8 EMPTY5[3]; - vu8 OAR2; /* Own Address Register 2 */ - vu8 EMPTY6[3]; - vu8 DR; /* Data Register */ - vu8 EMPTY7[3]; - vu8 ECCR; /* Extended Clock Control Register */ - vu8 EMPTY8[3]; -} I2C_TypeDef; - -/*------------------------------------- VIC ----------------------------------*/ - -typedef struct -{ - vu32 ISR; /* IRQ Status Register */ - vu32 FSR; /* FIQ Status Register */ - vu32 RINTSR; /* Raw Interrupt Status Register */ - vu32 INTSR; /* Interrupt Select Register */ - vu32 INTER; /* Interrupt Enable Register */ - vu32 INTECR; /* Interrupt Enable Clear Register */ - vu32 SWINTR; /* Software Interrupt Register */ - vu32 SWINTCR; /* Software Interrupt clear Register */ - vu32 PER; /* Protection Enable Register */ - vu32 EMPTY1[3]; - vu32 VAR; /* Vector Address Register */ - vu32 DVAR; /* Default Vector Address Register */ - vu32 EMPTY2[50]; - vu32 VAiR[16]; /* Vector Address 0-15 Register */ - vu32 EMPTY3[48]; - vu32 VCiR[16]; /* Vector Control 0-15 Register */ -} VIC_TypeDef; - -/*-------------------------------- Motor Control -----------------------------*/ - -typedef struct -{ - vu16 TCPT; /* Tacho Capture Register */ - vu16 EMPTY1; - vu16 TCMP; /* Tacho Compare Register */ - vu16 EMPTY2; - vu16 IPR; /* Input Pending Register */ - vu16 EMPTY3; - vu16 TPRS; /* Tacho Prescaler Register */ - vu16 EMPTY4; - vu16 CPRS; /* PWM Counter Prescaler Register */ - vu16 EMPTY5; - vu16 REP; /* Repetition Counter Register */ - vu16 EMPTY6; - vu16 CMPW; /* Compare Phase W Preload Register */ - vu16 EMPTY7; - vu16 CMPV; /* Compare Phase V Preload Register */ - vu16 EMPTY8; - vu16 CMPU; /* Compare Phase U Preload Register */ - vu16 EMPTY9; - vu16 CMP0; /* Compare 0 Preload Register */ - vu16 EMPTY10; - vu16 PCR0; /* Peripheral Control Register 0 */ - vu16 EMPTY11; - vu16 PCR1; /* Peripheral Control Register 1 */ - vu16 EMPTY12; - vu16 PCR2; /* Peripheral Control Register 2 */ - vu16 EMPTY13; - vu16 PSR; /* Polarity Selection Register */ - vu16 EMPTY14; - vu16 OPR; /* Output Peripheral Register */ - vu16 EMPTY15; - vu16 IMR; /* Interrupt Mask Register */ - vu16 EMPTY16; - vu16 DTG; /* Dead Time Generator Register */ - vu16 EMPTY17; - vu16 ESC; /* Emergency Stop Clear Register */ - vu16 EMPTY18; -}MC_TypeDef; - -/*------------------------------------- RTC ----------------------------------*/ - -typedef struct -{ - vu32 TR; /* Time Register */ - vu32 DTR; /* Date Register */ - vu32 ATR; /* Alarm time Register */ - vu32 CR; /* Control Register */ - vu32 SR; /* Status Register */ - vu32 MILR; /* Millisec Register */ -}RTC_TypeDef; - -/*------------------------------------- SSP ----------------------------------*/ - -typedef struct -{ - vu16 CR0; /* Control Register 1 */ - vu16 EMPTY1; - vu16 CR1; /* Control Register 2 */ - vu16 EMPTY2; - vu16 DR; /* Data Register */ - vu16 EMPTY3; - vu16 SR; /* Status Register */ - vu16 EMPTY4; - vu16 PR; /* Clock Prescale Register */ - vu16 EMPTY5; - vu16 IMSCR; /* Interrupt Mask Set or Clear Register */ - vu16 EMPTY6; - vu16 RISR; /* Raw Interrupt Status Register */ - vu16 EMPTY7; - vu16 MISR; /* Masked Interrupt Status Register */ - vu16 EMPTY8; - vu16 ICR; /* Interrupt Clear Register */ - vu16 EMPTY9; - vu16 DMACR; /* DMA Control Register */ - vu16 EMPTY10; -}SSP_TypeDef; - -/*------------------------------------ UART ----------------------------------*/ - -typedef struct -{ - vu16 DR; /* Data Register */ - vu16 EMPTY1; - vu16 RSECR; /* Receive Status Register (read)/Error Clear Register (write) */ - vu16 EMPTY2[9]; - vu16 FR; /* Flag Register */ - vu16 EMPTY3[3]; - vu16 ILPR; /* IrDA Low-Power counter Register */ - vu16 EMPTY4; - vu16 IBRD; /* Integer Baud Rate Divisor Register */ - vu16 EMPTY5; - vu16 FBRD; /* Fractional Baud Rate Divisor Register */ - vu16 EMPTY6; - vu16 LCR; /* Line Control Register, High byte */ - vu16 EMPTY7; - vu16 CR; /* Control Register */ - vu16 EMPTY8; - vu16 IFLS; /* Interrupt FIFO Level Select Register */ - vu16 EMPTY9; - vu16 IMSC; /* Interrupt Mask Set/Clear Register */ - vu16 EMPTY10; - vu16 RIS; /* Raw Interrupt Status Register */ - vu16 EMPTY11; - vu16 MIS; /* Masked Interrupt Status Register */ - vu16 EMPTY12; - vu16 ICR; /* Interrupt Clear Register */ - vu16 EMPTY13; - vu16 DMACR; /* DMA Control Register */ - vu16 EMPTY14; -}UART_TypeDef; - -/*------------------------------- Wake-up System -----------------------------*/ - -typedef struct -{ - vu32 CTRL; /* Control Register */ - vu32 MR; /* Mask Register */ - vu32 TR; /* Trigger Register */ - vu32 PR; /* Pending Register */ - vu32 INTR; /* Software Interrupt Register */ -} WIU_TypeDef; - -/*------------------------------- WatchDog Timer -----------------------------*/ - -typedef struct -{ - vu16 CR; /* Control Register */ - vu16 EMPTY1; - vu16 PR; /* Presclar Register */ - vu16 EMPTY2; - vu16 VR; /* Pre-load Value Register */ - vu16 EMPTY3; - vu16 CNT; /* Counter Register */ - vu16 EMPTY4; - vu16 SR; /* Status Register */ - vu16 EMPTY5; - vu16 MR; /* Mask Register */ - vu16 EMPTY6; - vu16 KR; /* Key Register */ - vu16 EMPTY7; -} WDG_TypeDef; - -/******************************************************************************* -* Memory Mapping of STR91x * -*******************************************************************************/ - -#define AHB_APB_BRDG0_U (0x58000000) /* AHB/APB Bridge 0 UnBuffered Space */ -#define AHB_APB_BRDG0_B (0x48000000) /* AHB/APB Bridge 0 Buffered Space */ - -#define AHB_APB_BRDG1_U (0x5C000000) /* AHB/APB Bridge 1 UnBuffered Space */ -#define AHB_APB_BRDG1_B (0x4C000000) /* AHB/APB Bridge 1 Buffered Space */ - -#define AHB_EMI_U (0x74000000) /* EMI UnBuffered Space */ -#define AHB_EMI_B (0x64000000) /* EMI Buffered Space */ - -#define AHB_DMA_U (0x78000000) /* DMA UnBuffered Space */ -#define AHB_DMA_B (0x68000000) /* DMA Buffered Space */ - -#define AHB_ENET_MAC_U (0x7C000400) /* ENET_MAC UnBuffered Space */ -#define AHB_ENET_MAC_B (0x6C000000) /* ENET_MAC Buffered Space */ - -#define AHB_ENET_DMA_U (0x7C000000) /* ENET_DMA Unbuffered Space */ -#define AHB_ENET_DMA_B (0x6C000400) /* ENET_DMA Buffered Space */ - -#define AHB_VIC1_U (0xFC000000) /* Secondary VIC1 UnBuffered Space */ -#define AHB_VIC0_U (0xFFFFF000) /* Primary VIC0 UnBuffered Space */ - -#define AHB_FMI_U (0x54000000) /* FMI Unbuffered Space */ -#define AHB_FMI_B (0x44000000) /* FMI buffered Space */ - -/******************************************************************************* -* Addresses related to the VICs' peripherals * -*******************************************************************************/ - -#define VIC0_BASE (AHB_VIC0_U) -#define VIC1_BASE (AHB_VIC1_U) - -/******************************************************************************* -* Addresses related to the EMI banks * -*******************************************************************************/ - -#define AHB_EMIB3_OFST (0x00000040) /* Offset of EMI bank3 */ -#define AHB_EMIB2_OFST (0x00000020) /* Offset of EMI bank2 */ -#define AHB_EMIB1_OFST (0x00000000) /* Offset of EMI bank1 */ -#define AHB_EMIB0_OFST (0x000000E0) /* Offset of EMI bank0 */ - -/******************************************************************************* -* Addresses related to the DMA peripheral * -*******************************************************************************/ - -#define AHB_DMA_Channel0_OFST (0x00000100) /* Offset of Channel 0 */ -#define AHB_DMA_Channel1_OFST (0x00000120) /* Offset of Channel 1 */ -#define AHB_DMA_Channel2_OFST (0x00000140) /* Offset of Channel 2 */ -#define AHB_DMA_Channel3_OFST (0x00000160) /* Offset of Channel 3 */ -#define AHB_DMA_Channel4_OFST (0x00000180) /* Offset of Channel 4 */ -#define AHB_DMA_Channel5_OFST (0x000001A0) /* Offset of Channel 5 */ -#define AHB_DMA_Channel6_OFST (0x000001C0) /* Offset of Channel 6 */ -#define AHB_DMA_Channel7_OFST (0x000001E0) /* Offset of Channel 7 */ - -/******************************************************************************* -* Addresses related to the APB0 sub-system * -*******************************************************************************/ - -#define APB_WIU_OFST (0x00001000) /* Offset of WIU */ -#define APB_TIM0_OFST (0x00002000) /* Offset of TIM0 */ -#define APB_TIM1_OFST (0x00003000) /* Offset of TIM1 */ -#define APB_TIM2_OFST (0x00004000) /* Offset of TIM2 */ -#define APB_TIM3_OFST (0x00005000) /* Offset of TIM3 */ -#define APB_GPIO0_OFST (0x00006000) /* Offset of GPIO0 */ -#define APB_GPIO1_OFST (0x00007000) /* Offset of GPIO1 */ -#define APB_GPIO2_OFST (0x00008000) /* Offset of GPIO2 */ -#define APB_GPIO3_OFST (0x00009000) /* Offset of GPIO3 */ -#define APB_GPIO4_OFST (0x0000A000) /* Offset of GPIO4 */ -#define APB_GPIO5_OFST (0x0000B000) /* Offset of GPIO5 */ -#define APB_GPIO6_OFST (0x0000C000) /* Offset of GPIO6 */ -#define APB_GPIO7_OFST (0x0000D000) /* Offset of GPIO7 */ -#define APB_GPIO8_OFST (0x0000E000) /* Offset of GPIO8 */ -#define APB_GPIO9_OFST (0x0000F000) /* Offset of GPIO9 */ - -/******************************************************************************* -* Addresses related to the APB1 sub-system * -*******************************************************************************/ - -#define APB_RTC_OFST (0x00001000) /* Offset of RTC */ -#define APB_SCU_OFST (0x00002000) /* Offset of System Controller */ -#define APB_MC_OFST (0x00003000) /* Offset of Motor Control */ -#define APB_UART0_OFST (0x00004000) /* Offset of UART0 */ -#define APB_UART1_OFST (0x00005000) /* Offset of UART1 */ -#define APB_UART2_OFST (0x00006000) /* Offset of UART2 */ -#define APB_SSP0_OFST (0x00007000) /* Offset of SSP0 */ -#define APB_SSP1_OFST (0x00008000) /* Offset of SSPI */ -#define APB_CAN_OFST (0x00009000) /* Offset of CAN */ -#define APB_ADC_OFST (0x0000A000) /* Offset of ADC */ -#define APB_WDG_OFST (0x0000B000) /* Offset of WDG */ -#define APB_I2C0_OFST (0x0000C000) /* Offset of I2C0 */ -#define APB_I2C1_OFST (0x0000D000) /* Offset of I2C1 */ - -/*----------------------------------------------------------------------------*/ -/*----------------------------- Unbuffered Mode ------------------------------*/ -/*----------------------------------------------------------------------------*/ - -#ifndef Buffered - -/******************************************************************************* -* AHBAPB peripheral Unbuffered Base Address * -*******************************************************************************/ - -#define AHBAPB0_BASE (AHB_APB_BRDG0_U) -#define AHBAPB1_BASE (AHB_APB_BRDG1_U) - -/******************************************************************************* -* ENET peripheral Unbuffered Base Address * -*******************************************************************************/ - -#define ENET_MAC_BASE (AHB_ENET_MAC_U) -#define ENET_DMA_BASE (AHB_ENET_DMA_U) - -/******************************************************************************* -* DMA peripheral Unbuffered Base Address * -*******************************************************************************/ - -#define DMA_BASE (AHB_DMA_U) - -/******************************************************************************* -* EMI peripheral Unbuffered Base Address * -*******************************************************************************/ - -#define EMI_BASE (AHB_EMI_U) - -/******************************************************************************* -* FMI peripheral Unbuffered Base Address * -*******************************************************************************/ - -#define FMI_BASE (AHB_FMI_U) - - -#else /* Buffered */ - -/*----------------------------------------------------------------------------*/ -/*------------------------------ Buffered Mode -------------------------------*/ -/*----------------------------------------------------------------------------*/ - -/******************************************************************************* -* AHBAPB peripheral Buffered Base Address * -*******************************************************************************/ - -#define AHBAPB0_BASE (AHB_APB_BRDG0_B) -#define AHBAPB1_BASE (AHB_APB_BRDG1_B) - -/******************************************************************************* -* ENET peripheral Unbuffered Base Address * -*******************************************************************************/ - -#define ENET_MAC_BASE (AHB_ENET_MAC_B) -#define ENET_DMA_BASE (AHB_ENET_DMA_B) - -/******************************************************************************* -* DMA peripheral Buffered Base Address * -*******************************************************************************/ - -#define DMA_BASE (AHB_DMA_B) - -/******************************************************************************* -* EMI peripheral Buffered Base Address * -*******************************************************************************/ - -#define EMI_BASE (AHB_EMI_B) - -/******************************************************************************* -* FMI peripheral Buffered Base Address * -*******************************************************************************/ - -#define FMI_BASE (AHB_FMI_B) - -#endif /* Buffered */ - -/******************************************************************************* -* DMA channels Base Address * -*******************************************************************************/ -#define DMA_Channel0_BASE (DMA_BASE + AHB_DMA_Channel0_OFST) -#define DMA_Channel1_BASE (DMA_BASE + AHB_DMA_Channel1_OFST) -#define DMA_Channel2_BASE (DMA_BASE + AHB_DMA_Channel2_OFST) -#define DMA_Channel3_BASE (DMA_BASE + AHB_DMA_Channel3_OFST) -#define DMA_Channel4_BASE (DMA_BASE + AHB_DMA_Channel4_OFST) -#define DMA_Channel5_BASE (DMA_BASE + AHB_DMA_Channel5_OFST) -#define DMA_Channel6_BASE (DMA_BASE + AHB_DMA_Channel6_OFST) -#define DMA_Channel7_BASE (DMA_BASE + AHB_DMA_Channel7_OFST) - -/******************************************************************************* -* EMI Banks peripheral Base Address * -*******************************************************************************/ - -#define EMI_Bank0_BASE (EMI_BASE + AHB_EMIB0_OFST) -#define EMI_Bank1_BASE (EMI_BASE + AHB_EMIB1_OFST) -#define EMI_Bank2_BASE (EMI_BASE + AHB_EMIB2_OFST) -#define EMI_Bank3_BASE (EMI_BASE + AHB_EMIB3_OFST) - -/******************************************************************************* -* APB0 Peripherals' Base addresses * -*******************************************************************************/ - -#define WIU_BASE (AHBAPB0_BASE + APB_WIU_OFST) -#define TIM0_BASE (AHBAPB0_BASE + APB_TIM0_OFST) -#define TIM1_BASE (AHBAPB0_BASE + APB_TIM1_OFST) -#define TIM2_BASE (AHBAPB0_BASE + APB_TIM2_OFST) -#define TIM3_BASE (AHBAPB0_BASE + APB_TIM3_OFST) -#define GPIO0_BASE (AHBAPB0_BASE + APB_GPIO0_OFST) -#define GPIO1_BASE (AHBAPB0_BASE + APB_GPIO1_OFST) -#define GPIO2_BASE (AHBAPB0_BASE + APB_GPIO2_OFST) -#define GPIO3_BASE (AHBAPB0_BASE + APB_GPIO3_OFST) -#define GPIO4_BASE (AHBAPB0_BASE + APB_GPIO4_OFST) -#define GPIO5_BASE (AHBAPB0_BASE + APB_GPIO5_OFST) -#define GPIO6_BASE (AHBAPB0_BASE + APB_GPIO6_OFST) -#define GPIO7_BASE (AHBAPB0_BASE + APB_GPIO7_OFST) -#define GPIO8_BASE (AHBAPB0_BASE + APB_GPIO8_OFST) -#define GPIO9_BASE (AHBAPB0_BASE + APB_GPIO9_OFST) - -/******************************************************************************* -* APB1 Peripherals' Base addresses * -*******************************************************************************/ - -#define RTC_BASE (AHBAPB1_BASE + APB_RTC_OFST) -#define SCU_BASE (AHBAPB1_BASE + APB_SCU_OFST) -#define MC_BASE (AHBAPB1_BASE + APB_MC_OFST) -#define UART0_BASE (AHBAPB1_BASE + APB_UART0_OFST) -#define UART1_BASE (AHBAPB1_BASE + APB_UART1_OFST) -#define UART2_BASE (AHBAPB1_BASE + APB_UART2_OFST) -#define SSP0_BASE (AHBAPB1_BASE + APB_SSP0_OFST) -#define SSP1_BASE (AHBAPB1_BASE + APB_SSP1_OFST) -#define CAN_BASE (AHBAPB1_BASE + APB_CAN_OFST) -#define ADC_BASE (AHBAPB1_BASE + APB_ADC_OFST) -#define WDG_BASE (AHBAPB1_BASE + APB_WDG_OFST) -#define I2C0_BASE (AHBAPB1_BASE + APB_I2C0_OFST) -#define I2C1_BASE (AHBAPB1_BASE + APB_I2C1_OFST) - -/******************************************************************************* -* IPs' declaration * -*******************************************************************************/ - -/*------------------------------ Non Debug Mode ------------------------------*/ - -#ifndef DEBUG - -/*********************************** AHBAPB ***********************************/ - -#define AHBAPB0 ((AHBAPB_TypeDef *)AHBAPB0_BASE) -#define AHBAPB1 ((AHBAPB_TypeDef *)AHBAPB1_BASE) - -/************************************* EMI ************************************/ - -#define EMI ((EMI_TypeDef *)EMI_BASE) - -/************************************* DMA ************************************/ - -#define DMA ((DMA_TypeDef *)DMA_BASE) -#define DMA_Channel0 ((DMA_Channel_TypeDef *)DMA_Channel0_BASE) -#define DMA_Channel1 ((DMA_Channel_TypeDef *)DMA_Channel1_BASE) -#define DMA_Channel2 ((DMA_Channel_TypeDef *)DMA_Channel2_BASE) -#define DMA_Channel3 ((DMA_Channel_TypeDef *)DMA_Channel3_BASE) -#define DMA_Channel4 ((DMA_Channel_TypeDef *)DMA_Channel4_BASE) -#define DMA_Channel5 ((DMA_Channel_TypeDef *)DMA_Channel5_BASE) -#define DMA_Channel6 ((DMA_Channel_TypeDef *)DMA_Channel6_BASE) -#define DMA_Channel7 ((DMA_Channel_TypeDef *)DMA_Channel7_BASE) - -/************************************* EMI ************************************/ - -#define EMI_Bank0 ((EMI_Bank_TypeDef *)EMI_Bank0_BASE) -#define EMI_Bank1 ((EMI_Bank_TypeDef *)EMI_Bank1_BASE) -#define EMI_Bank2 ((EMI_Bank_TypeDef *)EMI_Bank2_BASE) -#define EMI_Bank3 ((EMI_Bank_TypeDef *)EMI_Bank3_BASE) - -/************************************* ENET_MAC ************************************/ - -#define ENET_MAC ((ENET_MAC_TypeDef *)ENET_MAC_BASE) - -/************************************* ENET_DMA ************************************/ - -#define ENET_DMA ((ENET_DMA_TypeDef *)ENET_DMA_BASE) - -/************************************* FMI ************************************/ - -#define FMI ((FMI_TypeDef *)FMI_BASE) - -/************************************* VIC ************************************/ - -#define VIC0 ((VIC_TypeDef *)VIC0_BASE) -#define VIC1 ((VIC_TypeDef *)VIC1_BASE) - -/******************************************************************************* -* APB0 Peripherals' * -*******************************************************************************/ -#define WIU ((WIU_TypeDef *)WIU_BASE) -#define TIM0 ((TIM_TypeDef *)TIM0_BASE) -#define TIM1 ((TIM_TypeDef *)TIM1_BASE) -#define TIM2 ((TIM_TypeDef *)TIM2_BASE) -#define TIM3 ((TIM_TypeDef *)TIM3_BASE) -#define GPIO0 ((GPIO_TypeDef *)GPIO0_BASE) -#define GPIO1 ((GPIO_TypeDef *)GPIO1_BASE) -#define GPIO2 ((GPIO_TypeDef *)GPIO2_BASE) -#define GPIO3 ((GPIO_TypeDef *)GPIO3_BASE) -#define GPIO4 ((GPIO_TypeDef *)GPIO4_BASE) -#define GPIO5 ((GPIO_TypeDef *)GPIO5_BASE) -#define GPIO6 ((GPIO_TypeDef *)GPIO6_BASE) -#define GPIO7 ((GPIO_TypeDef *)GPIO7_BASE) -#define GPIO8 ((GPIO_TypeDef *)GPIO8_BASE) -#define GPIO9 ((GPIO_TypeDef *)GPIO9_BASE) -/******************************************************************************* -* APB1 Peripherals' * -*******************************************************************************/ -#define RTC ((RTC_TypeDef *)RTC_BASE) -#define SCU ((SCU_TypeDef *)SCU_BASE) -#define MC ((MC_TypeDef *)MC_BASE) -#define UART0 ((UART_TypeDef *)UART0_BASE) -#define UART1 ((UART_TypeDef *)UART1_BASE) -#define UART2 ((UART_TypeDef *)UART2_BASE) -#define SSP0 ((SSP_TypeDef *)SSP0_BASE) -#define SSP1 ((SSP_TypeDef *)SSP1_BASE) -#define CAN ((CAN_TypeDef *)CAN_BASE) -#define ADC ((ADC_TypeDef *)ADC_BASE) -#define WDG ((WDG_TypeDef *)WDG_BASE) -#define I2C0 ((I2C_TypeDef *)I2C0_BASE) -#define I2C1 ((I2C_TypeDef *)I2C1_BASE) -#define ENET_MAC ((ENET_MAC_TypeDef *)ENET_MAC_BASE) -#define ENET_DMA ((ENET_DMA_TypeDef *)ENET_DMA_BASE) - -#else /* DEBUG */ - -/*-------------------------------- Debug Mode --------------------------------*/ - -EXT AHBAPB_TypeDef *AHBAPB0; -EXT AHBAPB_TypeDef *AHBAPB1; -EXT DMA_TypeDef *DMA; -EXT DMA_Channel_TypeDef *DMA_Channel0; -EXT DMA_Channel_TypeDef *DMA_Channel1; -EXT DMA_Channel_TypeDef *DMA_Channel2; -EXT DMA_Channel_TypeDef *DMA_Channel3; -EXT DMA_Channel_TypeDef *DMA_Channel4; -EXT DMA_Channel_TypeDef *DMA_Channel5; -EXT DMA_Channel_TypeDef *DMA_Channel6; -EXT DMA_Channel_TypeDef *DMA_Channel7; -EXT EMI_Bank_TypeDef *EMI_Bank0; -EXT EMI_Bank_TypeDef *EMI_Bank1; -EXT EMI_Bank_TypeDef *EMI_Bank2; -EXT EMI_Bank_TypeDef *EMI_Bank3; -EXT FMI_TypeDef *FMI; -EXT VIC_TypeDef *VIC0; -EXT VIC_TypeDef *VIC1; -EXT WIU_TypeDef *WIU; -EXT TIM_TypeDef *TIM0; -EXT TIM_TypeDef *TIM1; -EXT TIM_TypeDef *TIM2; -EXT TIM_TypeDef *TIM3; -EXT GPIO_TypeDef *GPIO0; -EXT GPIO_TypeDef *GPIO1; -EXT GPIO_TypeDef *GPIO2; -EXT GPIO_TypeDef *GPIO3; -EXT GPIO_TypeDef *GPIO4; -EXT GPIO_TypeDef *GPIO5; -EXT GPIO_TypeDef *GPIO6; -EXT GPIO_TypeDef *GPIO7; -EXT GPIO_TypeDef *GPIO8; -EXT GPIO_TypeDef *GPIO9; -EXT RTC_TypeDef *RTC; -EXT SCU_TypeDef *SCU; -EXT MC_TypeDef *MC; -EXT UART_TypeDef *UART0; -EXT UART_TypeDef *UART1; -EXT UART_TypeDef *UART2; -EXT SSP_TypeDef *SSP0; -EXT SSP_TypeDef *SSP1; -EXT CAN_TypeDef *CAN; -EXT ADC_TypeDef *ADC; -EXT WDG_TypeDef *WDG; -EXT I2C_TypeDef *I2C0; -EXT I2C_TypeDef *I2C1; -EXT ENET_MAC_TypeDef *ENET_MAC; -EXT ENET_DMA_TypeDef *ENET_DMA; - - -#endif /* DEBUG */ - -#endif /* __91x_MAP_H*/ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ - diff --git a/Demo/ARM9_STR91X_IAR/Library/include/91x_scu.h b/Demo/ARM9_STR91X_IAR/Library/include/91x_scu.h deleted file mode 100644 index b9d04f558..000000000 --- a/Demo/ARM9_STR91X_IAR/Library/include/91x_scu.h +++ /dev/null @@ -1,196 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 91x_scu.h -* Author : MCD Application Team -* Date First Issued : 05/18/2006 : Version 1.0 -* Description : This file provides the SCU library software functions -* prototypes & definitions -******************************************************************************** -* History: -* 05/24/2006 : Version 1.1 -* 05/18/2006 : Version 1.0 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH -* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS -* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT -* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT -* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION -* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __91x_SCU_H -#define __91x_SCU_H - -/* Includes ------------------------------------------------------------------*/ -#include "91x_map.h" - -/* Exported constants --------------------------------------------------------*/ - -/*MCLK_Source*/ -#define SCU_MCLK_PLL 0x0 -#define SCU_MCLK_RTC 0x1 -#define SCU_MCLK_OSC 0x2 - -/*RCLK_Divisor*/ -#define SCU_RCLK_Div1 0xFFFFFFE3 -#define SCU_RCLK_Div2 0x4 -#define SCU_RCLK_Div4 0x8 -#define SCU_RCLK_Div8 0xC -#define SCU_RCLK_Div16 0x10 -#define SCU_RCLK_Div1024 0x14 - -/*HCLK_Divisor*/ -#define SCU_HCLK_Div1 0xFFFFFF9F -#define SCU_HCLK_Div2 0x20 -#define SCU_HCLK_Div4 0x40 - -/*PCLK_Divisor*/ -#define SCU_PCLK_Div1 0xFFFFFE7F -#define SCU_PCLK_Div2 0x80 -#define SCU_PCLK_Div4 0x100 -#define SCU_PCLK_Div8 0x180 - -/*FMICLK_Divisor*/ -#define SCU_FMICLK_Div1 0xFFFEFFFF -#define SCU_FMICLK_Div2 0x10000 - -/*BRCLK_Divisor*/ -#define SCU_BRCLK_Div1 0xFFFFFDFF -#define SCU_BRCLK_Div2 0x200 - -/*TIMCLK_Source*/ -#define SCU_TIMCLK_EXT 0x1 -#define SCU_TIMCLK_INT 0x0 - -/*TIMx*/ -#define SCU_TIM01 0x0 -#define SCU_TIM23 0x1 - - -/*USBCLK_Source*/ -#define SCU_USBCLK_MCLK 0xFFFFF3FF -#define SCU_USBCLK_MCLK2 0x400 -#define SCU_USBCLK_EXT 0x800 - -/*SCU_EMIBCLK*/ -#define SCU_EMIBCLK_Div1 0xFFF9FFFF -#define SCU_EMIBCLK_Div2 0x20000 - -/*SCU_EMIMODE*/ -#define SCU_EMI_MUX 0xFFFFFFBF -#define SCU_EMI_DEMUX 0x40 - -/*SCU_EMIALE_LEN*/ -#define SCU_EMIALE_LEN1 0xFFFFFEFF -#define SCU_EMIALE_LEN2 0x100 - -/*SCU_EMIALE_POL*/ -#define SCU_EMIALE_POLLow 0xFFFFFF7F -#define SCU_EMIALE_POLHigh 0x80 - -/*UART_IrDA_Mode*/ -#define SCU_UARTMode_IrDA 0x1 -#define SCU_UARTMode_UART 0x0 - -/*APBPeriph*/ -#define __TIM01 0x1 -#define __TIM23 0x2 -#define __MC 0x4 -#define __UART0 0x8 -#define __UART1 0x10 -#define __UART2 0x20 -#define __I2C0 0x40 -#define __I2C1 0x80 -#define __SSP0 0x100 -#define __SSP1 0x200 -#define __CAN 0x400 -#define __ADC 0x800 -#define __WDG 0x1000 -#define __WIU 0x2000 -#define __GPIO0 0x4000 -#define __GPIO1 0x8000 -#define __GPIO2 0x10000 -#define __GPIO3 0x20000 -#define __GPIO4 0x40000 -#define __GPIO5 0x80000 -#define __GPIO6 0x100000 -#define __GPIO7 0x200000 -#define __GPIO8 0x400000 -#define __GPIO9 0x800000 -#define __RTC 0x1000000 - -/*AHBPeriph*/ -#define __FMI 0x1 -#define __FPQBC 0x2 -#define __SRAM 0x8 -#define __SRAM_ARBITER 0x10 -#define __VIC 0x20 -#define __EMI 0x40 -#define __EMI_MEM_CLK 0x80 -#define __DMA 0x100 -#define __USB 0x200 -#define __USB48M 0x400 -#define __ENET 0x800 -#define __PFQBC_AHB 0x1000 - -/*SCU_IT*/ -#define SCU_IT_LVD_RST 0x10 -#define SCU_IT_SRAM_ERROR 0x8 -#define SCU_IT_ACK_PFQBC 0x4 -#define SCU_IT_LOCK_LOST 0x2 -#define SCU_IT_LOCK 0x1 - -/*SCU_FLAG*/ -#define SCU_FLAG_SRAM_ERROR 0x20 -#define SCU_FLAG_ACK_PFQBC 0x10 -#define SCU_FLAG_LVD_RESET 0x8 -#define SCU_FLAG_WDG_RST 0x4 -#define SCU_FLAG_LOCK_LOST 0x2 -#define SCU_FLAG_LOCK 0x1 - - -/* Module private variables --------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -ErrorStatus SCU_MCLKSourceConfig(u32 MCLK_Source); -ErrorStatus SCU_PLLFactorsConfig(u8 PLLN, u8 PLLM, u8 PLLP); -ErrorStatus SCU_PLLCmd(FunctionalState NewState); -void SCU_RCLKDivisorConfig(u32 RCLK_Divisor); -void SCU_HCLKDivisorConfig(u32 HCLK_Divisor); -void SCU_PCLKDivisorConfig(u32 PCLK_Divisor); -void SCU_APBPeriphClockConfig(u32 APBPeriph, FunctionalState NewState); -void SCU_AHBPeriphClockConfig(u32 AHBPeriph, FunctionalState NewState); -void SCU_APBPeriphReset(u32 APBPeriph, FunctionalState NewState); -void SCU_AHBPeriphReset(u32 AHBPeriph, FunctionalState NewState); -void SCU_APBPeriphIdleConfig(u32 APBPeriph, FunctionalState NewState); -void SCU_AHBPeriphIdleConfig(u32 AHBPeriph, FunctionalState NewState); -void SCU_APBPeriphDebugConfig(u32 APBPeriph, FunctionalState NewState); -void SCU_AHBPeriphDebugConfig(u32 AHBPeriph, FunctionalState NewState); -void SCU_BRCLKDivisorConfig(u32 BRCLK_Divisor); -void SCU_TIMCLKSourceConfig(u8 TIMx, u32 TIMCLK_Source); -void SCU_TIMPresConfig(u8 TIMx, u16 Prescaler); -void SCU_USBCLKConfig(u32 USBCLK_Source); -void SCU_PHYCLKConfig(FunctionalState NewState); -void SCU_FMICLKDivisorConfig(u32 FMICLK_Divisor); -void SCU_EMIBCLKDivisorConfig(u32 SCU_EMIBCLK); -void SCU_EMIModeConfig(u32 SCU_EMIMODE); -void SCU_EMIALEConfig(u32 SCU_EMIALE_LEN, u32 SCU_EMIALE_POL); -void SCU_ITConfig(u32 SCU_IT, FunctionalState NewState); -FlagStatus SCU_GetFlagStatus(u32 SCU_Flag); -void SCU_ClearFlag(u32 SCU_Flag); -u32 SCU_GetPLLFreqValue(void); -u32 SCU_GetMCLKFreqValue(void); -u32 SCU_GetRCLKFreqValue(void); -u32 SCU_GetHCLKFreqValue(void); -u32 SCU_GetPCLKFreqValue(void); -void SCU_WakeUpLineConfig(u8 EXTint); -void SCU_SpecIntRunModeConfig(FunctionalState NewState); -void SCU_EnterIdleMode(void); -void SCU_EnterSleepMode(void); -void SCU_UARTIrDASelect(UART_TypeDef * UARTx, u8 UART_IrDA_Mode); -void SCU_PFQBCCmd(FunctionalState NewState); - -#endif /*__91x_SCU_H*/ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM9_STR91X_IAR/Library/include/91x_tim.h b/Demo/ARM9_STR91X_IAR/Library/include/91x_tim.h deleted file mode 100644 index b587c27ac..000000000 --- a/Demo/ARM9_STR91X_IAR/Library/include/91x_tim.h +++ /dev/null @@ -1,155 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 91x_tim.h -* Author : MCD Application Team -* Date First Issued : 05/18/2006 : Version 1.0 -* Description : This file contains all the functions prototypes for the -* TIM software library. -******************************************************************************** -* History: -* 05/24/2006 : Version 1.1 -* 05/18/2006 : Version 1.0 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH -* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS -* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT -* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT -* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION -* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __91x_TIM_H -#define __91x_TIM_H - -/* Includes ------------------------------------------------------------------*/ -#include "91x_map.h" -#include "91x_scu.h" - -/* Exported types ----------------------------------------------------------- */ - -/* TIM Init structure define */ -typedef struct -{ - u16 TIM_Mode; /* Timer mode */ - u16 TIM_OC1_Modes; /* Output Compare 1 Mode: Timing or Wave */ - u16 TIM_OC2_Modes; /* Output Compare 2 Mode: Timing or Wave */ - u16 TIM_Clock_Source; /* Timer Clock source APB/SCU/EXTERNAL */ - u16 TIM_Clock_Edge; /* Timer Clock Edge: Rising or Falling Edge */ - u16 TIM_OPM_INPUT_Edge; /* Timer Input Capture 1 Edge used in OPM Mode */ - u16 TIM_ICAP1_Edge; /* Timer Input Capture 1 Edge used in ICAP1 Mode */ - u16 TIM_ICAP2_Edge; /* Timer Input Capture 2 Edge used in ICAP2 Mode */ - u8 TIM_Prescaler; /* Timer Prescaler factor */ - u16 TIM_Pulse_Level_1; /* Level applied on the Output Compare Pin 1 */ - u16 TIM_Pulse_Level_2; /* Level applied on the Output Compare Pin 2 */ - u16 TIM_Period_Level; /* Level applied during the Period of a PWM Mode */ - u16 TIM_Pulse_Length_1; /* Pulse 1 Length used in Output Compare 1 Mode */ - u16 TIM_Pulse_Length_2; /* Pulse 2 Length used in Output Compare 2 Mode */ - u16 TIM_Full_Period; /* Period Length used in PWM Mode */ -} TIM_InitTypeDef; - -typedef enum -{ - TIM_START, - TIM_STOP, - TIM_CLEAR -} TIM_CounterOperations; - -/* Exported constants --------------------------------------------------------*/ - -/* TIM MODE */ -#define TIM_PWMI 0x4000 /* PWM INPUT Mode */ -#define TIM_OCM_CHANNEL_1 0x0040 /* OUTPUT COMPARE CHANNEL 1 Mode */ -#define TIM_OCM_CHANNEL_2 0x0080 /* OUTPUT COMPARE CHANNEL 2 Mode */ -#define TIM_OCM_CHANNEL_12 0x00C0 /* OUTPUT COMPARE CHANNEL 1 & 2 Mode */ -#define TIM_PWM 0x0010 /* PWM Mode */ -#define TIM_OPM 0x0020 /* ONE PULSE Mode */ -#define TIM_ICAP_CHANNEL_1 0x0400 /* INPUT CAPTURE 1 Mode */ -#define TIM_ICAP_CHANNEL_2 0x0500 /* INPUT CAPTURE 2 Mode */ -#define TIM_ICAP_CHANNEL_12 0x0600 /* INPUT CAPTURE 1 & 2 Mode */ - -/* TIM OUTPUT COMPARE MODE */ -#define TIM_WAVE 0x0001 -#define TIM_TIMING 0x0002 - -/* TIM CLOCK SOURCE */ -#define TIM_CLK_APB 0xFFFE -#define TIM_CLK_EXTERNAL 0x0001 -#define TIM_CLK_SCU 0x0001 - -/* TIM CLOCK EDGE */ -#define TIM_CLK_EDGE_FALLING 0xFFFD -#define TIM_CLK_EDGE_RISING 0x0002 - -/* TIM OPM INPUT EDGE */ -#define TIM_OPM_EDGE_FALLING 0xFFFB -#define TIM_OPM_EDGE_RISING 0x0004 - -/* TIM ICAPA INPUT EDGE */ -#define TIM_ICAP1_EDGE_FALLING 0xFFFB -#define TIM_ICAP1_EDGE_RISING 0x0004 - -/* TIM ICAPB INPUT EDGE */ -#define TIM_ICAP2_EDGE_FALLING 0xFFF7 -#define TIM_ICAP2_EDGE_RISING 0x0008 - -/* TIM OUTPUT LEVEL */ -#define TIM_HIGH 0x0200 -#define TIM_LOW 0x0300 - -/* TIM OUTPUT EDGE */ -#define TIM_OUTPUT_EDGE_RISING 0x8000 -#define TIM_OUTPUT_EDGE_FALLING 0x0800 - -/* TIM channels */ -#define TIM_PWM_OC1_Channel 0x1 /* PWM/Output Compare 1 Channel */ -#define TIM_OC2_Channel 0x2 /* Output Compare 2 Channel */ - -/* TIM DMA SOURCE */ -#define TIM_DMA_IC1 0x0000 /* Input Capture Channel 1 DMA Source */ -#define TIM_DMA_OC1 0x1000 /* OUTPUT Compare Channel 1 DMA Source */ -#define TIM_DMA_IC2 0x2000 /* Input Capture Channel 2 DMA Source */ -#define TIM_DMA_OC2 0x3000 /* OUTPUT Compare Channel 2 DMA Source */ - -/* TIM DMA ENABLE or DISABLE */ -#define TIM_DMA_ENABLE 0x0400 /* DMA Enable */ -#define TIM_DMA_DISABLE 0xFBFF /* DMA Disable */ - -/* TIM Interruption Sources*/ -#define TIM_IT_IC1 0x8000 /* Input Capture Channel 1 Interrupt Source */ -#define TIM_IT_OC1 0x4000 /* Output Compare Channel 1 Interrupt Source */ -#define TIM_IT_TO 0x2000 /* Timer OverFlow Interrupt Source */ -#define TIM_IT_IC2 0x1000 /* Input Capture Channel 2 Interrupt Source */ -#define TIM_IT_OC2 0x0800 /* Output Compare Channel 2 Interrupt Source */ - -/* TIM Flags */ -#define TIM_FLAG_IC1 0x8000 /* Input Capture Channel 1 Flag */ -#define TIM_FLAG_OC1 0x4000 /* Output Compare Channel 1 Flag */ -#define TIM_FLAG_TO 0x2000 /* Timer OverFlow Flag */ -#define TIM_FLAG_IC2 0x1000 /* Input Capture Channel 2 Flag */ -#define TIM_FLAG_OC2 0x0800 /* Output Compare Channel 2 Flag */ - -/* Module private variables --------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -void TIM_Init(TIM_TypeDef *TIMx, TIM_InitTypeDef *TIM_InitStruct); -void TIM_DeInit(TIM_TypeDef *TIMx); -void TIM_StructInit(TIM_InitTypeDef *TIM_InitStruct); -void TIM_CounterCmd(TIM_TypeDef *TIMx, TIM_CounterOperations TIM_operation); -void TIM_PrescalerConfig(TIM_TypeDef *TIMx, u8 TIM_Prescaler); -u8 TIM_GetPrescalerValue(TIM_TypeDef *TIMx); -u16 TIM_GetCounterValue(TIM_TypeDef *TIMx); -u16 TIM_GetICAP1Value(TIM_TypeDef *TIMx); -u16 TIM_GetICAP2Value(TIM_TypeDef *TIMx); -void TIM_SetPulse(TIM_TypeDef *TIMx,u16 TIM_Channel ,u16 TIM_Pulse); -FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, u16 TIM_Flag); -void TIM_ClearFlag(TIM_TypeDef *TIMx, u16 TIM_Flag); -u16 TIM_GetPWMIPulse(TIM_TypeDef *TIMx); -u16 TIM_GetPWMIPeriod(TIM_TypeDef *TIMx); -void TIM_ITConfig(TIM_TypeDef *TIMx, u16 TIM_IT, FunctionalState TIM_Newstate); -void TIM_DMAConfig(TIM_TypeDef *TIMx, u16 TIM_DMA_Sources); -void TIM_DMACmd(TIM_TypeDef *TIMx, FunctionalState TIM_Newstate); - -#endif /* __91x_TIM_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM9_STR91X_IAR/Library/include/91x_type.h b/Demo/ARM9_STR91X_IAR/Library/include/91x_type.h deleted file mode 100644 index 916d81c68..000000000 --- a/Demo/ARM9_STR91X_IAR/Library/include/91x_type.h +++ /dev/null @@ -1,50 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 91x_type.h -* Author : MCD Application Team -* Date First Issued : 05/18/2006 : Version 1.0 -* Description : It contains common types and constants used in all the -* peripherals' drivers. -******************************************************************************** -* History: -* 05/24/2006 : Version 1.1 -* 05/18/2006 : Version 1.0 -********************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT -* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT -* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION -* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*********************************************************************************/ - -#ifndef __91x_type_H -#define __91x_type_H - - typedef long long u64; - typedef unsigned long u32; - typedef unsigned short u16; - typedef unsigned char u8; - - typedef signed long s32; - typedef signed short s16; - typedef signed char s8; - - typedef volatile unsigned long vu32; - typedef volatile unsigned short vu16; - typedef volatile unsigned char vu8; - - typedef volatile signed long vs32; - typedef volatile signed short vs16; - typedef volatile signed char vs8; - -typedef enum { FALSE = 0, TRUE = !FALSE } bool; - -typedef enum { RESET = 0, SET = !RESET } FlagStatus, ITStatus; - -typedef enum { DISABLE = 0, ENABLE = !DISABLE} FunctionalState; - -typedef enum { ERROR = 0, SUCCESS = !ERROR} ErrorStatus; - -#endif /* __91x_type_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM9_STR91X_IAR/Library/include/91x_uart.h b/Demo/ARM9_STR91X_IAR/Library/include/91x_uart.h deleted file mode 100644 index b979438bb..000000000 --- a/Demo/ARM9_STR91X_IAR/Library/include/91x_uart.h +++ /dev/null @@ -1,174 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 91x_uart.h -* Author : MCD Application Team -* Date First Issued : 05/18/2006 : Version 1.0 -* Description : This file contains all the functions prototypes for the -* UART software library. -******************************************************************************** -* History: -* 05/24/2006 : Version 1.1 -* 05/18/2006 : Version 1.0 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __91x_UART_H -#define __91x_UART_H - -/* Includes ------------------------------------------------------------------*/ -#include <91x_map.h> - -/* Exported types ------------------------------------------------------------*/ -/* UART FIFO Level enumeration */ -typedef enum -{ - UART_FIFOLevel_1_8 = 0x0000, /* FIFO size 16 bytes, FIFO level 2 bytes */ - UART_FIFOLevel_1_4 = 0x0001, /* FIFO size 16 bytes, FIFO level 4 bytes */ - UART_FIFOLevel_1_2 = 0x0002, /* FIFO size 16 bytes, FIFO level 8 bytes */ - UART_FIFOLevel_3_4 = 0x0003, /* FIFO size 16 bytes, FIFO level 12 bytes */ - UART_FIFOLevel_7_8 = 0x0004 /* FIFO size 16 bytes, FIFO level 14 bytes */ -}UART_FIFOLevel; - -/* UART Init Structure definition */ -typedef struct -{ - u16 UART_WordLength; - u16 UART_StopBits; - u16 UART_Parity; - u32 UART_BaudRate; - u16 UART_HardwareFlowControl; - u16 UART_Mode; - u16 UART_FIFO; - UART_FIFOLevel UART_TxFIFOLevel; - UART_FIFOLevel UART_RxFIFOLevel; -}UART_InitTypeDef; - - -/* UART RTS enumeration */ -typedef enum -{ - LowLevel = 0, - HighLevel -}UART_LevelTypeDef; - -/* Exported constants --------------------------------------------------------*/ -/* UART Data Length */ -#define UART_WordLength_5D 0x0000 /* 5 bits Data */ -#define UART_WordLength_6D 0x0020 /* 6 bits Data */ -#define UART_WordLength_7D 0x0040 /* 7 bits Data */ -#define UART_WordLength_8D 0x0060 /* 8 bits Data */ - -/* UART Stop Bits */ -#define UART_StopBits_1 0xFFF7 /* Disable two stop bit is transmitted - at the end of frame */ -#define UART_StopBits_2 0x0008 /* Enable Two stop bits are transmitted - at the end of frame */ -/* UART Parity */ -#define UART_Parity_No 0x0000 /* Parity Disable */ -#define UART_Parity_Even 0x0006 /* Even Parity */ -#define UART_Parity_Odd 0x0002 /* Odd Parity */ -#define UART_Parity_OddStick 0x0082 /* 1 is transmitted as bit parity */ -#define UART_Parity_EvenStick 0x0086 /* 0 is transmitted as bit parity */ - -/* UART Hardware Flow Control */ -#define UART_HardwareFlowControl_None 0x0000 /* HFC Disable */ -#define UART_HardwareFlowControl_RTS 0x4000 /* RTS Enable */ -#define UART_HardwareFlowControl_CTS 0x8000 /* CTS Enable */ -#define UART_HardwareFlowControl_RTS_CTS 0xC000 /* CTS and RTS Enable */ - -/* UART Mode */ -#define UART_Mode_Rx 0x0200 /* UART Rx Enabled */ -#define UART_Mode_Tx 0x0100 /* UART Tx Enbled */ -#define UART_Mode_Tx_Rx 0x0300 /* UART Tx and Rx Enabled */ - -/* UART FIFO */ -#define UART_FIFO_Disable 0xFFEF /* FIFOs Disable */ -#define UART_FIFO_Enable 0x0010 /* FIFOs Enable */ - -/* UART Interrupt definition */ -#define UART_IT_OverrunError 0x0400 /* Overrun Error interrupt mask */ -#define UART_IT_BreakError 0x0200 /* Break Error interrupt mask */ -#define UART_IT_ParityError 0x0100 /* Parity Error interrupt mask */ -#define UART_IT_FrameError 0x0080 /* Frame Error interrupt mask */ -#define UART_IT_ReceiveTimeOut 0x0040 /* Receive Time Out interrupt mask */ -#define UART_IT_Transmit 0x0020 /* Transmit interrupt mask */ -#define UART_IT_Receive 0x0010 /* Receive interrupt mask */ -#define UART_IT_DSR 0x0008 /* DSR interrupt mask */ -#define UART_IT_DCD 0x0004 /* DCD interrupt mask */ -#define UART_IT_CTS 0x0002 /* CTS interrupt mask */ -#define UART_IT_RI 0x0001 /* RI interrupt mask */ - -/* UART DMA On Error */ -#define UART_DMAOnError_Enable 0xFFFB /* DMA receive request enabled - when the UART error interrupt - is asserted. */ -#define UART_DMAOnError_Disable 0x0004 /* DMA receive request disabled - when the UART error interrupt - is asserted. */ -/* UART DMA Request */ -#define UART_DMAReq_Tx 0x02 /* Transmit DMA Enable */ -#define UART_DMAReq_Rx 0x01 /* Receive DMA Enable */ - -/* UART FLAG */ -#define UART_FLAG_OverrunError 0x23 /* Overrun error flag */ -#define UART_FLAG_Break 0x22 /* break error flag */ -#define UART_FLAG_ParityError 0x21 /* parity error flag */ -#define UART_FLAG_FrameError 0x20 /* frame error flag */ -#define UART_FLAG_RI 0x48 /* RI flag */ -#define UART_FLAG_TxFIFOEmpty 0x47 /* Transmit FIFO Empty flag */ -#define UART_FLAG_RxFIFOFull 0x46 /* Receive FIFO Full flag */ -#define UART_FLAG_TxFIFOFull 0x45 /* Transmit FIFO Full flag */ -#define UART_FLAG_RxFIFOEmpty 0x44 /* Receive FIFO Empty flag */ -#define UART_FLAG_Busy 0x43 /* UART Busy flag */ -#define UART_FLAG_DCD 0x42 /* DCD flag */ -#define UART_FLAG_DSR 0x41 /* DSR flag */ -#define UART_FLAG_CTS 0x40 /* CTS flag */ -#define UART_RawIT_OverrunError 0x6A /* Overrun Error Raw IT flag */ -#define UART_RawIT_BreakError 0x69 /* Break Error Raw IT flag */ -#define UART_RawIT_ParityError 0x68 /* Parity Error Raw IT flag */ -#define UART_RawIT_FrameError 0x67 /* Frame Error Raw IT flag */ -#define UART_RawIT_ReceiveTimeOut 0x66 /* ReceiveTimeOut Raw IT flag */ -#define UART_RawIT_Transmit 0x65 /* Transmit Raw IT flag */ -#define UART_RawIT_Receive 0x64 /* Receive Raw IT flag */ -#define UART_RawIT_DSR 0x63 /* DSR Raw IT flag */ -#define UART_RawIT_DCD 0x62 /* DCD Raw IT flag */ -#define UART_RawIT_CTS 0x61 /* CTS Raw IT flag */ -#define UART_RawIT_RI 0x60 /* RI Raw IT flag */ - -/*IrDAx select*/ -#define IrDA0 0x01 /*IrDA0 select*/ -#define IrDA1 0x02 /*IrDA0 select*/ -#define IrDA2 0x03 /*IrDA0 select*/ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -void UART_DeInit(UART_TypeDef* UARTx); -void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct); -void UART_StructInit(UART_InitTypeDef* UART_InitStruct); -void UART_Cmd(UART_TypeDef* UARTx, FunctionalState NewState); -void UART_ITConfig(UART_TypeDef* UARTx, u16 UART_IT, FunctionalState NewState); -void UART_DMAConfig(UART_TypeDef* UARTx, u16 UART_DMAOnError); -void UART_DMACmd(UART_TypeDef* UARTx, u8 UART_DMAReq, FunctionalState NewState); -void UART_LoopBackConfig(UART_TypeDef* UARTx, FunctionalState NewState); -FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, u16 UART_FLAG); -void UART_ClearFlag(UART_TypeDef* UARTx); -void UART_ClearITPendingBit(UART_TypeDef* UARTx, u16 UART_IT); -void UART_IrDALowPowerConfig(u8 IrDAx, FunctionalState NewState); -void UART_IrDACmd(u8 IrDAx, FunctionalState NewState); -void UART_IrDASetCounter(u8 IrDAx, u32 IrDA_Counter); -void UART_SendData(UART_TypeDef* UARTx, u8 Data); -u8 UART_ReceiveData(UART_TypeDef* UARTx); -void UART_SendBreak(UART_TypeDef* UARTx); -void UART_DTRConfig(UART_LevelTypeDef LevelState); -void UART_RTSConfig(UART_LevelTypeDef LevelState); -ITStatus UART_GetITStatus(UART_TypeDef* UARTx, u16 UART_IT); - -#endif /* __91x_UART_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM9_STR91X_IAR/Library/include/91x_vic.h b/Demo/ARM9_STR91X_IAR/Library/include/91x_vic.h deleted file mode 100644 index 127716a38..000000000 --- a/Demo/ARM9_STR91X_IAR/Library/include/91x_vic.h +++ /dev/null @@ -1,94 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 91x_vic.h -* Author : MCD Application Team -* Date First Issued : 05/18/2006 : Version 1.0 -* Description : This file contains all the functions prototypes for the -* VIC software library. -******************************************************************************** -* History: -* 05/24/2006 : Version 1.1 -* 05/18/2006 : Version 1.0 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH -* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS -* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT -* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT -* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION -* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - - -/* Define to prevent recursive inclusion ------------------------------------ */ -#ifndef __91x_VIC_H -#define __91x_VIC_H - -/* Includes ------------------------------------------------------------------*/ -#include "91x_map.h" -#include "91x_it.h" - -/* Exported types ------------------------------------------------------------*/ -/* Type of interrupt */ -typedef enum -{ - VIC_IRQ, - VIC_FIQ -} VIC_ITLineMode; - -/* Exported constants --------------------------------------------------------*/ - -/* VIC sources*/ - -#define WDG_ITLine 0 -#define SW_ITLine 1 -#define ARMRX_ITLine 2 -#define ARMTX_ITLine 3 -#define TIM0_ITLine 4 -#define TIM1_ITLine 5 -#define TIM2_ITLine 6 -#define TIM3_ITLine 7 -#define USBHP_ITLine 8 -#define USBLP_ITLine 9 -#define SCU_ITLine 10 -#define ENET_ITLine 11 -#define DMA_ITLine 12 -#define CAN_ITLine 13 -#define MC_ITLine 14 -#define ADC_ITLine 15 -#define UART0_ITLine 16 -#define UART1_ITLine 17 -#define UART2_ITLine 18 -#define I2C0_ITLine 19 -#define I2C1_ITLine 20 -#define SSP0_ITLine 21 -#define SSP1_ITLine 22 -#define LVD_ITLine 23 -#define RTC_ITLine 24 -#define WIU_ITLine 25 -#define EXTIT0_ITLine 26 -#define EXTIT1_ITLine 27 -#define EXTIT2_ITLine 28 -#define EXTIT3_ITLine 29 -#define USBWU_ITLine 30 -#define PFQBC_ITLine 31 - - -/* Module private variables --------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -void VIC_DeInit(void); -FlagStatus VIC_GetIRQStatus(u16 VIC_Source); -FlagStatus VIC_GetFIQStatus(u16 VIC_Source); -FlagStatus VIC_GetSourceITStatus(u16 VIC_Source); -void VIC_ITCmd(u16 VIC_Source, FunctionalState VIC_NewState); -void VIC_SWITCmd(u16 VIC_Source, FunctionalState VIC_NewState); -void VIC_ProtectionCmd(FunctionalState VIC_NewState); -u32 VIC_GetCurrentISRAdd(VIC_TypeDef* VICx); -u32 VIC_GetISRVectAdd(u16 VIC_Source); -void VIC_Config(u16 VIC_Source, VIC_ITLineMode VIC_LineMode, u8 VIC_Priority); - -#endif /* __91x_VIC_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ - diff --git a/Demo/ARM9_STR91X_IAR/Library/include/91x_wdg.h b/Demo/ARM9_STR91X_IAR/Library/include/91x_wdg.h deleted file mode 100644 index fc70547ad..000000000 --- a/Demo/ARM9_STR91X_IAR/Library/include/91x_wdg.h +++ /dev/null @@ -1,82 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 91x_wdg.h -* Author : MCD Application Team -* Date First Issued : 05/18/2006 : Version 1.0 -* Description : This file contains all the functions prototypes for the -* WDG software library. -******************************************************************************** -* History: -* 05/24/2006 : Version 1.1 -* 05/18/2006 : Version 1.0 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __91x_WDG_H -#define __91x_WDG_H - -/* Includes ------------------------------------------------------------------*/ -#include "91x_map.h" - -/* Exported types ------------------------------------------------------------*/ -typedef struct -{ -u16 WDG_Mode; -u16 WDG_ClockSource; -u16 WDG_Prescaler; -u16 WDG_Preload; - -} WDG_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/* WDG_Mode */ -#define WDG_Mode_Wdg 0x0001 /*WDG configured to run in watchdog mode.*/ -#define WDG_Mode_Timer 0xFFFE /*WDG configured to be in Free-running Timer mode.*/ - - -/* WDG_ClockSource */ -#define WDG_ClockSource_Rtc 0x0004 /* External clock ( 32 khz RTC clock ) will be used as counting clock.*/ -#define WDG_ClockSource_Apb 0xFFFB /*The APB clock signal will be used as counting clock.*/ - -/* WDG_Prescaler */ -/*This member must be a number between 0x00 and 0xFF. -Specifies the Prescaler value to divide the clock source. -The clock of the Watchdog Timer Counter is divided by " WDG_Prescaler + 1".*/ - - - -/* WDG_Preload */ -/*This member must be a number between 0x0000 and 0xFFFF. -This value is loaded in the WDG Counter when it starts counting.*/ - - -/* WDG Sequence */ -#define WDG_KeyValue1 0xA55A -#define WDG_KeyValue2 0x5AA5 - -/* Exported macro ------------------------------------------------------------*/ - - -/* Exported functions ------------------------------------------------------- */ - -void WDG_DeInit(void); -void WDG_Init(WDG_InitTypeDef* WDG_InitStruct); -void WDG_StructInit(WDG_InitTypeDef* WDG_InitStruct); -void WDG_Cmd(FunctionalState NewState); -void WDG_ITConfig(FunctionalState NewState); -u16 WDG_GetCounter(void); -FlagStatus WDG_GetFlagStatus(void); -void WDG_ClearFlag(void); -ITStatus WDG_GetITStatus(void); -void WDG_ClearITPendingBit(void); - -#endif /* __WDG_H */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM9_STR91X_IAR/Library/source/91x_can.c b/Demo/ARM9_STR91X_IAR/Library/source/91x_can.c deleted file mode 100644 index e560d03c5..000000000 --- a/Demo/ARM9_STR91X_IAR/Library/source/91x_can.c +++ /dev/null @@ -1,768 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 91x_can.c -* Author : MCD Application Team -* Date First Issued : 05/18/2006 : Version 1.0 -* Description : This file provides all the CAN software functions. -******************************************************************************** -* History: -* 05/24/2006 : Version 1.1 -* 05/18/2006 : Version 1.0 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -#include "91x_can.h" -#include "91x_scu.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/*----------------------------------------------------------------------------*/ -/* Macro Name : xxx_ID_MSK, xxx_ID_ARB */ -/* Description : Form the Mask and Arbitration registers value to filter */ -/* a range of identifiers or a fixed identifier, for standard*/ -/* and extended IDs */ -/*----------------------------------------------------------------------------*/ -#define RANGE_ID_MSK(range_start, range_end) (~((range_end) - (range_start))) -#define RANGE_ID_ARB(range_start, range_end) ((range_start) & (range_end)) - -#define FIXED_ID_MSK(id) RANGE_ID_MSK((id), (id)) -#define FIXED_ID_ARB(id) RANGE_ID_ARB((id), (id)) - -#define STD_RANGE_ID_MSK(range_start, range_end) ((u16)((RANGE_ID_MSK((range_start), (range_end)) & 0x7FF) << 2)) -#define STD_RANGE_ID_ARB(range_start, range_end) ((u16)(RANGE_ID_ARB((range_start), (range_end)) << 2)) - -#define STD_FIXED_ID_MSK(id) ((u16)((FIXED_ID_MSK(id) & 0x7FF) << 2)) -#define STD_FIXED_ID_ARB(id) ((u16)(FIXED_ID_ARB(id) << 2)) - -#define EXT_RANGE_ID_MSK_L(range_start, range_end) ((u16)(RANGE_ID_MSK((range_start), (range_end)) >> 11)) -#define EXT_RANGE_ID_MSK_H(range_start, range_end) ((u16)(STD_RANGE_ID_MSK((range_start), (range_end)) | ((RANGE_ID_MSK((range_start), (range_end)) >> 27) & 0x03))) -#define EXT_RANGE_ID_ARB_L(range_start, range_end) ((u16)(RANGE_ID_ARB((range_start), (range_end)) >> 11)) -#define EXT_RANGE_ID_ARB_H(range_start, range_end) ((u16)(STD_RANGE_ID_ARB((range_start), (range_end)) | ((RANGE_ID_ARB((range_start), (range_end)) >> 27) & 0x03))) - -#define EXT_FIXED_ID_MSK_L(id) ((u16)(FIXED_ID_MSK(id) >> 11)) -#define EXT_FIXED_ID_MSK_H(id) ((u16)(STD_FIXED_ID_MSK(id) | ((FIXED_ID_MSK(id) >> 27) & 0x03))) -#define EXT_FIXED_ID_ARB_L(id) ((u16)(FIXED_ID_ARB(id) >> 11)) -#define EXT_FIXED_ID_ARB_H(id) ((u16)(STD_FIXED_ID_ARB(id) | ((FIXED_ID_ARB(id) >> 27) & 0x03))) - -/* macro to format the timing register value from the timing parameters*/ -#define CAN_TIMING(tseg1, tseg2, sjw, brp) ((((tseg2-1) & 0x07) << 12) | (((tseg1-1) & 0x0F) << 8) | (((sjw-1) & 0x03) << 6) | ((brp-1) & 0x3F)) - -/* Private variables ---------------------------------------------------------*/ -/* array of pre-defined timing parameters for standard bitrates*/ -u16 CanTimings[] = { /* value bitrate NTQ TSEG1 TSEG2 SJW BRP */ - CAN_TIMING(11, 4, 4, 5), /* 0x3AC4 100 kbit/s 16 11 4 4 5 */ - CAN_TIMING(11, 4, 4, 4), /* 0x3AC3 125 kbit/s 16 11 4 4 4 */ - CAN_TIMING( 4, 3, 3, 4), /* 0x2383 250 kbit/s 8 4 3 3 4 */ - CAN_TIMING(13, 2, 1, 1), /* 0x1C00 500 kbit/s 16 13 2 1 1 */ - CAN_TIMING( 4, 3, 1, 1), /* 0x2300 1 Mbit/s 8 4 3 1 1 */ -}; - -/* Private function prototypes -----------------------------------------------*/ -static u32 GetFreeIF(void); -/* Private functions ---------------------------------------------------------*/ - -/******************************************************************************* -* Function Name : CAN_DeInit -* Description : Deinitializes the CAN peripheral registers to their default -* reset values. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void CAN_DeInit (void) -{ - /* Reset the CAN registers values*/ - - SCU_APBPeriphReset(__CAN,ENABLE); /*CAN peripheral is under Reset */ - SCU_APBPeriphReset(__CAN,DISABLE); /*CAN peripheral Reset off*/ - - -} - -/******************************************************************************* -* Function Name : CAN_Init -* Description : Initializes the CAN peripheral according to the specified -* parameters in the CAN_InitStruct. -* Input : CAN_InitStruct: pointer to a CAN_InitTypeDef structure that -* contains the configuration information for the CAN peripheral. -* Output : None -* Return : None -*******************************************************************************/ -void CAN_Init(CAN_InitTypeDef* CAN_InitStruct) -{ - CAN_EnterInitMode(CAN_CR_CCE | CAN_InitStruct->CAN_ConfigParameters); - CAN_SetBitrate(CAN_InitStruct->CAN_Bitrate); - CAN_LeaveInitMode(); - CAN_LeaveTestMode(); -} - -/******************************************************************************* -* Function Name : CAN_StructInit -* Description : Fills each CAN_InitStruct member with its reset value. -* Input : CAN_InitStruct : pointer to a CAN_InitTypeDef structure which -* will be initialized. -* Output : None -* Return : None. -*******************************************************************************/ -void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) -{ -/* Reset CAN init structure parameters values */ - CAN_InitStruct->CAN_ConfigParameters = 0x0; - CAN_InitStruct->CAN_Bitrate = 0x2301; -} - -/******************************************************************************* -* Function Name : CAN_SetBitrate -* Description : Setups a standard CAN bitrate. -* Input : bitrate: specifies the bit rate. -* Output : None -* Return : None -*******************************************************************************/ -void CAN_SetBitrate(u32 bitrate) -{ - CAN->BTR = CanTimings[bitrate]; /* write the predefined timing value */ - CAN->BRPR = 0; /* clear the Extended Baud Rate Prescaler */ -} - -/******************************************************************************* -* Function Name : CAN_SetTiming -* Description : Setups the CAN timing with specific parameters -* Input : - tseg1: specifies Time Segment before the sample point. -* This parameter must be a number between 1 and 16. -* - tseg2: Time Segment after the sample point. This parameter -* must be a number between 1 and 8. -* - sjw: Synchronisation Jump Width. This parameter must be -* a number between 1 and 4. -* - brp: Baud Rate Prescaler. This parameter must be a number -* between 1 and 1024. -* Output : None -* Return : None -*******************************************************************************/ -void CAN_SetTiming(u32 tseg1, u32 tseg2, u32 sjw, u32 brp) -{ - CAN->BTR = CAN_TIMING(tseg1, tseg2, sjw, brp); - CAN->BRPR = ((brp-1) >> 6) & 0x0F; -} - -/******************************************************************************* -* Function Name : GetFreeIF -* Description : Searchs the first free message interface, starting from 0. -* Input : None -* Output : None -* Return : A free message interface number (0 or 1) if found, else 2 -*******************************************************************************/ -static u32 GetFreeIF(void) -{ - if ((CAN->sMsgObj[0].CRR & CAN_CRR_BUSY) == 0) - return 0; - else if ((CAN->sMsgObj[1].CRR & CAN_CRR_BUSY) == 0) - return 1; - else - return 2; -} - -/******************************************************************************* -* Function Name : CAN_SetUnusedMsgObj -* Description : Configures the message object as unused -* Input : msgobj: specifies the Message object number, from 0 to 31. -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Interface to treat the message -* - ERROR: No interface to treat the message -*******************************************************************************/ -ErrorStatus CAN_SetUnusedMsgObj(u32 msgobj) -{ - u32 msg_if=0; - - if ((msg_if = GetFreeIF()) == 2) - { - return ERROR; - } - - CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD - | CAN_CMR_MASK - | CAN_CMR_ARB - | CAN_CMR_CONTROL - | CAN_CMR_DATAA - | CAN_CMR_DATAB; - - CAN->sMsgObj[msg_if].M1R = 0; - CAN->sMsgObj[msg_if].M2R = 0; - - CAN->sMsgObj[msg_if].A1R = 0; - CAN->sMsgObj[msg_if].A2R = 0; - - CAN->sMsgObj[msg_if].MCR = 0; - - CAN->sMsgObj[msg_if].DA1R = 0; - CAN->sMsgObj[msg_if].DA2R = 0; - CAN->sMsgObj[msg_if].DB1R = 0; - CAN->sMsgObj[msg_if].DB2R = 0; - - CAN->sMsgObj[msg_if].CRR = 1 + msgobj; - - return SUCCESS; -} - -/******************************************************************************* -* Function Name : CAN_SetTxMsgObj -* Description : Configures the message object as TX. -* Input : - msgobj: specifies the Message object number, from 0 to 31. -* - idType: specifies the identifier type of the frames that -* will be transmitted using this message object. -* This parameter can be one of the following values: -* - CAN_STD_ID (standard ID, 11-bit) -* - CAN_EXT_ID (extended ID, 29-bit) -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Interface to treat the message -* - ERROR: No interface to treat the message -*******************************************************************************/ -ErrorStatus CAN_SetTxMsgObj(u32 msgobj, u32 idType) -{ - u32 msg_if=0; - - if ((msg_if = GetFreeIF()) == 2) - { - return ERROR; - } - - CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD - | CAN_CMR_MASK - | CAN_CMR_ARB - | CAN_CMR_CONTROL - | CAN_CMR_DATAA - | CAN_CMR_DATAB; - - CAN->sMsgObj[msg_if].M1R = 0; - CAN->sMsgObj[msg_if].A1R = 0; - - if (idType == CAN_STD_ID) - { - CAN->sMsgObj[msg_if].M2R = CAN_M2R_MDIR; - CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_DIR; - } - else - { - CAN->sMsgObj[msg_if].M2R = CAN_M2R_MDIR | CAN_M2R_MXTD; - CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_DIR | CAN_A2R_XTD; - } - - CAN->sMsgObj[msg_if].MCR = CAN_MCR_TXIE | CAN_MCR_EOB; - - CAN->sMsgObj[msg_if].DA1R = 0; - CAN->sMsgObj[msg_if].DA2R = 0; - CAN->sMsgObj[msg_if].DB1R = 0; - CAN->sMsgObj[msg_if].DB2R = 0; - - CAN->sMsgObj[msg_if].CRR = 1 + msgobj; - - return SUCCESS; -} - -/******************************************************************************* -* Function Name : CAN_SetRxMsgObj -* Description : Configures the message object as RX. -* Input : - msgobj: specifies the Message object number, from 0 to 31. -* - idType: specifies the identifier type of the frames that -* will be transmitted using this message object. -* This parameter can be one of the following values: -* - CAN_STD_ID (standard ID, 11-bit) -* - CAN_EXT_ID (extended ID, 29-bit) -* - idLow: specifies the low part of the identifier range used -* for acceptance filtering. -* - idHigh: specifies the high part of the identifier range -* used for acceptance filtering. -* - singleOrFifoLast: specifies the end-of-buffer indicator. -* This parameter can be one of the following values: -* - TRUE: for a single receive object or a FIFO receive -* object that is the last one of the FIFO. -* - FALSE: for a FIFO receive object that is not the -* last one. -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Interface to treat the message -* - ERROR: No interface to treat the message -*******************************************************************************/ -ErrorStatus CAN_SetRxMsgObj(u32 msgobj, u32 idType, u32 idLow, u32 idHigh, bool singleOrFifoLast) -{ - u32 msg_if=0; - - if ((msg_if = GetFreeIF()) == 2) - { - return ERROR; - } - - CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD - | CAN_CMR_MASK - | CAN_CMR_ARB - | CAN_CMR_CONTROL - | CAN_CMR_DATAA - | CAN_CMR_DATAB; - - if (idType == CAN_STD_ID) - { - CAN->sMsgObj[msg_if].M1R = 0; - CAN->sMsgObj[msg_if].M2R = STD_RANGE_ID_MSK(idLow, idHigh); - - CAN->sMsgObj[msg_if].A1R = 0; - CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | STD_RANGE_ID_ARB(idLow, idHigh); - } - else - { - CAN->sMsgObj[msg_if].M1R = EXT_RANGE_ID_MSK_L(idLow, idHigh); - CAN->sMsgObj[msg_if].M2R = CAN_M2R_MXTD | EXT_RANGE_ID_MSK_H(idLow, idHigh); - - CAN->sMsgObj[msg_if].A1R = EXT_RANGE_ID_ARB_L(idLow, idHigh); - CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_XTD | EXT_RANGE_ID_ARB_H(idLow, idHigh); - } - - CAN->sMsgObj[msg_if].MCR = CAN_MCR_RXIE | CAN_MCR_UMASK | (singleOrFifoLast ? CAN_MCR_EOB : 0); - - CAN->sMsgObj[msg_if].DA1R = 0; - CAN->sMsgObj[msg_if].DA2R = 0; - CAN->sMsgObj[msg_if].DB1R = 0; - CAN->sMsgObj[msg_if].DB2R = 0; - - CAN->sMsgObj[msg_if].CRR = 1 + msgobj; - - return SUCCESS; -} - -/******************************************************************************* -* Function Name : CAN_InvalidateAllMsgObj -* Description : Configures all the message objects as unused. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void CAN_InvalidateAllMsgObj(void) -{ - u32 i=0; - for (i = 0; i < 32; i++) - CAN_SetUnusedMsgObj(i); -} - - -/******************************************************************************* -* Function Name : CAN_ReleaseMessage -* Description : Releases the message object -* Input : - msgobj: specifies the Message object number, from 0 to 31. -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Interface to treat the message -* - ERROR: No interface to treat the message -*******************************************************************************/ -ErrorStatus CAN_ReleaseMessage(u32 msgobj) -{ - u32 msg_if=0; - - if ((msg_if = GetFreeIF()) == 2) - { - return ERROR; - } - - CAN->sMsgObj[msg_if].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQSTNEWDAT; - CAN->sMsgObj[msg_if].CRR = 1 + msgobj; - - return SUCCESS; -} - -/******************************************************************************* -* Function Name : CAN_SendMessage -* Description : Start transmission of a message -* Input : - msgobj: specifies the Message object number, from 0 to 31. -* : - pCanMsg: pointer to the message structure containing data -* to transmit. -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Transmission OK -* - ERROR: No transmission -*******************************************************************************/ -ErrorStatus CAN_SendMessage(u32 msgobj, canmsg* pCanMsg) -{ - if (CAN->sMsgObj[0].CRR & CAN_CRR_BUSY) - { - return ERROR; - } - - CAN->SR &= ~CAN_SR_TXOK; - - /* read the Arbitration and Message Control*/ - CAN->sMsgObj[0].CMR = CAN_CMR_ARB | CAN_CMR_CONTROL; - - CAN->sMsgObj[0].CRR = 1 + msgobj; - - if (CAN->sMsgObj[0].CRR & CAN_CRR_BUSY) - { - return ERROR; - } - - /* update the contents needed for transmission*/ - CAN->sMsgObj[0].CMR = CAN_CMR_WRRD - | CAN_CMR_ARB - | CAN_CMR_CONTROL - | CAN_CMR_DATAA - | CAN_CMR_DATAB; - - if ((CAN->sMsgObj[0].A2R & CAN_A2R_XTD) == 0) - { - /* standard ID*/ - CAN->sMsgObj[0].A1R = 0; - CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | STD_FIXED_ID_ARB(pCanMsg->Id); - } - else - { - /* extended ID*/ - CAN->sMsgObj[0].A1R = EXT_FIXED_ID_ARB_L(pCanMsg->Id); - CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | EXT_FIXED_ID_ARB_H(pCanMsg->Id); - } - - CAN->sMsgObj[0].MCR = (CAN->sMsgObj[0].MCR & 0xFEF0) | CAN_MCR_NEWDAT | CAN_MCR_TXRQST | pCanMsg->Dlc; - - CAN->sMsgObj[0].DA1R = ((u16)pCanMsg->Data[1]<<8) | pCanMsg->Data[0]; - CAN->sMsgObj[0].DA2R = ((u16)pCanMsg->Data[3]<<8) | pCanMsg->Data[2]; - CAN->sMsgObj[0].DB1R = ((u16)pCanMsg->Data[5]<<8) | pCanMsg->Data[4]; - CAN->sMsgObj[0].DB2R = ((u16)pCanMsg->Data[7]<<8) | pCanMsg->Data[6]; - - CAN->sMsgObj[0].CRR = 1 + msgobj; - - return SUCCESS; -} - -/******************************************************************************* -* Function Name : CAN_ReceiveMessage -* Description : Gets the message, if received. -* Input : - msgobj: specifies the Message object number, from 0 to 31. -* - release: specifies the message release indicator. -* This parameter can be one of the following values: -* - TRUE: the message object is released when getting -* the data. -* - FALSE: the message object is not released. -* - pCanMsg: pointer to the message structure where received -* data is copied. -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Reception OK -* - ERROR: No message pending -*******************************************************************************/ -ErrorStatus CAN_ReceiveMessage(u32 msgobj, bool release, canmsg* pCanMsg) -{ - if (!CAN_IsMessageWaiting(msgobj)) - { - return ERROR; - } - - CAN->SR &= ~CAN_SR_RXOK; - - /* read the message contents*/ - CAN->sMsgObj[1].CMR = CAN_CMR_MASK - | CAN_CMR_ARB - | CAN_CMR_CONTROL - | CAN_CMR_CLRINTPND - | (release ? CAN_CMR_TXRQSTNEWDAT : 0) - | CAN_CMR_DATAA - | CAN_CMR_DATAB; - - CAN->sMsgObj[1].CRR = 1 + msgobj; - - if (CAN->sMsgObj[1].CRR & CAN_CRR_BUSY) - { - return ERROR; - } - - if ((CAN->sMsgObj[1].A2R & CAN_A2R_XTD) == 0) - { - /* standard ID*/ - pCanMsg->IdType = CAN_STD_ID; - pCanMsg->Id = (CAN->sMsgObj[1].A2R >> 2) & 0x07FF; - } - else - { - /* extended ID*/ - pCanMsg->IdType = CAN_EXT_ID; - pCanMsg->Id = ((CAN->sMsgObj[1].A2R >> 2) & 0x07FF); - pCanMsg->Id |= ((u32)CAN->sMsgObj[1].A1R << 11); - pCanMsg->Id |= (((u32)CAN->sMsgObj[1].A2R & 0x0003) << 27); - } - - pCanMsg->Dlc = CAN->sMsgObj[1].MCR & 0x0F; - - pCanMsg->Data[0] = (u8) CAN->sMsgObj[1].DA1R; - pCanMsg->Data[1] = (u8)(CAN->sMsgObj[1].DA1R >> 8); - pCanMsg->Data[2] = (u8) CAN->sMsgObj[1].DA2R; - pCanMsg->Data[3] = (u8)(CAN->sMsgObj[1].DA2R >> 8); - pCanMsg->Data[4] = (u8) CAN->sMsgObj[1].DB1R; - pCanMsg->Data[5] = (u8)(CAN->sMsgObj[1].DB1R >> 8); - pCanMsg->Data[6] = (u8) CAN->sMsgObj[1].DB2R; - pCanMsg->Data[7] = (u8)(CAN->sMsgObj[1].DB2R >> 8); - - return SUCCESS; -} - -/******************************************************************************* -* Function Name : CAN_WaitEndOfTx -* Description : Waits until current transmission is finished. -* Input : None -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Transmission ended -* - ERROR: Transmission did not occur yet -*******************************************************************************/ -ErrorStatus CAN_WaitEndOfTx(void) -{ - if ((CAN->SR & CAN_SR_TXOK) == 0) - { - return ERROR; - } - CAN->SR &= ~CAN_SR_TXOK; - - return SUCCESS; -} - -/******************************************************************************* -* Function Name : CAN_BasicSendMessage -* Description : Starts transmission of a message in BASIC mode. This mode -* does not use the message RAM. -* Input : pCanMsg: Pointer to the message structure containing data to -* transmit. -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Transmission OK -* - ERROR: No transmission -*******************************************************************************/ -ErrorStatus CAN_BasicSendMessage(canmsg* pCanMsg) -{ - /* clear NewDat bit in IF2 to detect next reception*/ - CAN->sMsgObj[1].MCR &= ~CAN_MCR_NEWDAT; - - CAN->SR &= ~CAN_SR_TXOK; - CAN->sMsgObj[0].CMR = CAN_CMR_WRRD - | CAN_CMR_ARB - | CAN_CMR_CONTROL - | CAN_CMR_DATAA - | CAN_CMR_DATAB; - - if (pCanMsg->IdType == CAN_STD_ID) - { - /* standard ID*/ - CAN->sMsgObj[0].A1R = 0; - CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | STD_FIXED_ID_ARB(pCanMsg->Id); - } - else - { - /* extended ID*/ - CAN->sMsgObj[0].A1R = EXT_FIXED_ID_ARB_L(pCanMsg->Id); - CAN->sMsgObj[0].A2R = ((CAN->sMsgObj[0].A2R) & 0xE000) | EXT_FIXED_ID_ARB_H(pCanMsg->Id); - } - - CAN->sMsgObj[0].MCR = (CAN->sMsgObj[0].MCR & 0xFCF0) | pCanMsg->Dlc; - - CAN->sMsgObj[0].DA1R = ((u16)pCanMsg->Data[1]<<8) | pCanMsg->Data[0]; - CAN->sMsgObj[0].DA2R = ((u16)pCanMsg->Data[3]<<8) | pCanMsg->Data[2]; - CAN->sMsgObj[0].DB1R = ((u16)pCanMsg->Data[5]<<8) | pCanMsg->Data[4]; - CAN->sMsgObj[0].DB2R = ((u16)pCanMsg->Data[7]<<8) | pCanMsg->Data[6]; - - /* request transmission*/ - if (CAN->sMsgObj[0].CRR == CAN_CRR_BUSY ) - { - return ERROR; - } - - return SUCCESS; -} - -/******************************************************************************* -* Function Name : CAN_BasicReceiveMessage -* Description : Gets the message in BASIC mode, if received. This mode does -* not use the message RAM. -* Input : pCanMsg: pointer to the message structure where message is copied. -* Output : None -* Return : An ErrorStatus enumuration value: -* - SUCCESS: Reception OK -* - ERROR: No message pending -*******************************************************************************/ -ErrorStatus CAN_BasicReceiveMessage(canmsg* pCanMsg) -{ - if ((CAN->sMsgObj[1].MCR & CAN_MCR_NEWDAT) == 0) - { - return ERROR; - } - - CAN->SR &= ~CAN_SR_RXOK; - - CAN->sMsgObj[1].CMR = CAN_CMR_ARB - | CAN_CMR_CONTROL - | CAN_CMR_DATAA - | CAN_CMR_DATAB; - - if ((CAN->sMsgObj[1].A2R & CAN_A2R_XTD) == 0) - { - /* standard ID*/ - pCanMsg->IdType = CAN_STD_ID; - pCanMsg->Id = (CAN->sMsgObj[1].A2R >> 2) & 0x07FF; - } - else - { - /* extended ID*/ - pCanMsg->IdType = CAN_EXT_ID; - pCanMsg->Id = ((CAN->sMsgObj[1].A2R >> 2) & 0x07FF); - pCanMsg->Id |= ((u32)CAN->sMsgObj[1].A1R << 11); - pCanMsg->Id |= (((u32)CAN->sMsgObj[1].A2R & 0x0003) << 27); - } - - pCanMsg->Dlc = CAN->sMsgObj[1].MCR & 0x0F; - - pCanMsg->Data[0] = (u8) CAN->sMsgObj[1].DA1R; - pCanMsg->Data[1] = (u8)(CAN->sMsgObj[1].DA1R >> 8); - pCanMsg->Data[2] = (u8) CAN->sMsgObj[1].DA2R; - pCanMsg->Data[3] = (u8)(CAN->sMsgObj[1].DA2R >> 8); - pCanMsg->Data[4] = (u8) CAN->sMsgObj[1].DB1R; - pCanMsg->Data[5] = (u8)(CAN->sMsgObj[1].DB1R >> 8); - pCanMsg->Data[6] = (u8) CAN->sMsgObj[1].DB2R; - pCanMsg->Data[7] = (u8)(CAN->sMsgObj[1].DB2R >> 8); - - return SUCCESS; -} - -/******************************************************************************* -* Function Name : CAN_EnterInitMode -* Description : Switchs the CAN into initialization mode. This function must -* be used in conjunction with CAN_LeaveInitMode(). -* Input : InitMask: specifies the CAN configuration in normal mode. -* Output : None -* Return : None -*******************************************************************************/ -void CAN_EnterInitMode(u8 InitMask) -{ - CAN->CR = InitMask | CAN_CR_INIT; - CAN->SR = 0; /* reset the status*/ -} - -/******************************************************************************* -* Function Name : CAN_LeaveInitMode -* Description : Leaves the initialization mode (switch into normal mode). -* This function must be used in conjunction with CAN_EnterInitMode(). -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void CAN_LeaveInitMode(void) -{ - CAN->CR &= ~(CAN_CR_INIT | CAN_CR_CCE); -} - -/******************************************************************************* -* Function Name : CAN_EnterTestMode -* Description : Switchs the CAN into test mode. This function must be used in -* conjunction with CAN_LeaveTestMode(). -* Input : TestMask: specifies the configuration in test modes. -* Output : None -* Return : None -*******************************************************************************/ -void CAN_EnterTestMode(u8 TestMask) -{ - CAN->CR |= CAN_CR_TEST; - CAN->TESTR |= TestMask; -} - -/******************************************************************************* -* Function Name : CAN_LeaveTestMode -* Description : Leaves the current test mode (switch into normal mode). -* This function must be used in conjunction with CAN_EnterTestMode(). -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void CAN_LeaveTestMode(void) -{ - CAN->CR |= CAN_CR_TEST; - CAN->TESTR &= ~(CAN_TESTR_LBACK | CAN_TESTR_SILENT | CAN_TESTR_BASIC); - CAN->CR &= ~CAN_CR_TEST; -} - -/******************************************************************************* -* Function Name : CAN_ReleaseTxMessage -* Description : Releases the transmit message object. -* Input : - msgobj: specifies the Message object number, from 0 to 31. -* Output : None -* Return : None -*******************************************************************************/ -void CAN_ReleaseTxMessage(u32 msgobj) -{ - CAN->sMsgObj[0].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQSTNEWDAT; - CAN->sMsgObj[0].CRR = 1 + msgobj; -} - -/******************************************************************************* -* Function Name : CAN_ReleaseRxMessage -* Description : Releases the receive message object. -* Input : - msgobj: specifies the Message object number, from 0 to 31. -* Output : None -* Return : None -*******************************************************************************/ -void CAN_ReleaseRxMessage(u32 msgobj) -{ - CAN->sMsgObj[1].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQSTNEWDAT; - CAN->sMsgObj[1].CRR = 1 + msgobj; -} - -/******************************************************************************* -* Function Name : CAN_IsMessageWaiting -* Description : Tests the waiting status of a received message. -* Input : - msgobj: specifies the Message object number, from 0 to 31. -* Output : None -* Return : A non-zero value if the corresponding message object has -* received a message waiting to be copied, else 0. -*******************************************************************************/ -u32 CAN_IsMessageWaiting(u32 msgobj) -{ - return (msgobj < 16 ? CAN->ND1R & (1 << msgobj) : CAN->ND2R & (1 << (msgobj-16))); -} - -/******************************************************************************* -* Function Name : CAN_IsTransmitRequested -* Description : Tests the request status of a transmitted message. -* Input : - msgobj: specifies the Message object number, from 0 to 31. -* Output : None -* Return : A non-zero value if the corresponding message is requested -* to transmit, else 0. -*******************************************************************************/ -u32 CAN_IsTransmitRequested(u32 msgobj) -{ - return (msgobj < 16 ? CAN->TXR1R & (1 << msgobj) : CAN->TXR2R & (1 << (msgobj-16))); -} - -/******************************************************************************* -* Function Name : CAN_IsInterruptPending -* Description : Tests the interrupt status of a message object. -* Input : - msgobj: specifies the Message object number, from 0 to 31. -* Output : None -* Return : A non-zero value if the corresponding message has an -* interrupt pending, else 0. -*******************************************************************************/ -u32 CAN_IsInterruptPending(u32 msgobj) -{ - return (msgobj < 16 ? CAN->IP1R & (1 << msgobj) : CAN->IP2R & (1 << (msgobj-16))); -} - -/******************************************************************************* -* Function Name : CAN_IsObjectValid -* Description : Tests the validity of a message object (ready to use). -* Input : - msgobj: specifies the Message object number, from 0 to 31. -* Output : None -* Return : A non-zero value if the corresponding message object is -* valid, else 0. -*******************************************************************************/ -u32 CAN_IsObjectValid(u32 msgobj) -{ - return (msgobj < 16 ? CAN->MV1R & (1 << msgobj) : CAN->MV2R & (1 << (msgobj-16))); -} -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM9_STR91X_IAR/Library/source/91x_enet.c b/Demo/ARM9_STR91X_IAR/Library/source/91x_enet.c deleted file mode 100644 index 29650d345..000000000 --- a/Demo/ARM9_STR91X_IAR/Library/source/91x_enet.c +++ /dev/null @@ -1,588 +0,0 @@ -/******************** -* Original work (C) COPYRIGHT 2006 STMicroelectronics ************************** -* Modifications (C) CopyRight 2006 Richard barry -* File Name : 91x_enet.c -* Author : MCD Application Team -* Date First Issued : May 2006 -* Description : ENET library functions -******************************************************************************** -* History: -* May 2006: v1.0 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - - -/* Includes ------------------------------------------------------------------*/ -#include "FreeRTOS.h" -#include "task.h" -#include "91x_lib.h" -#include "string.h" //include when using memcpy function - -/* Include of other module interface headers ---------------------------------*/ -/* Local includes ------------------------------------------------------------*/ -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#ifndef NULL -#define NULL (0) -#endif -/* Function return values */ -#define ENET_OK (1) -#define ENET_NOK (0) - -/* PHY interface constants. */ -#define STE100P_STATUS_REG 0x01 -#define STE100P_CONTROL_REG 0x00 -#define STE100P_LINK_ABILITY 0x05 -#define STE100P_STATUS_LINKED 0x0004 -#define STE100P_AUTO_NEGOTIATE_ABILITY 0x1000 -#define STE100P_AUTO_NEGOTIATE_COMPLETE 0x20 -#define STE100P_10HALF 0x0020 -#define STE100P_10FULL 0x0040 -#define STE100P_100HALF 0x0080 -#define STE100P_100FULL 0x0100 -#define STE100P_CTRL_FULL 0x0100 - - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -#define ENET_NUM_RX_BUFFERS 8 - -static ENET_DMADSCRBase dmaTxDscrBase, dmaRxDscrBase[ ENET_NUM_RX_BUFFERS ]; -static volatile u8 RxBuff[ ENET_NUM_RX_BUFFERS ][ENET_BUFFER_SIZE], TxBuff[ENET_BUFFER_SIZE]; - -/* Private function prototypes -----------------------------------------------*/ -extern MEMCOPY_L2S_BY4(); - -/* Interface functions -------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/******************************************************************************* -* Function Name : ENET_SetMACConfig(ENET_MACConfig * MAC_Config) -* Description : MAC Control Register Configuration -* Input : MAC_Config structure -* Output : None -* Return : None -*******************************************************************************/ -void ENET_MACControlConfig(ENET_MACConfig *MAC_Config) -{ - /* ReceiveALL bit */ - if (MAC_Config->ReceiveALL==ENABLE) ENET_MAC->MCR |= MAC_MCR_RA; - else ENET_MAC->MCR &=~MAC_MCR_RA; - - /* MIIPrescaler */ - ENET_MAC->MCR &=~(0x3<<24); - if ((MAC_Config->MIIPrescaler) == MIIPrescaler_2) - ENET_MAC->MCR |=0x1<<24; - - /* Loopback mode */ - if (MAC_Config->LoopbackMode==ENABLE) - { - ENET_MAC->MCR &=~MAC_MCR_LM; - ENET_MAC->MCR |=0x1<<21; - ENET_MAC->MCR &=~MAC_MCR_DRO; /*enable frame reception during transmission*/ - } - - /* Address filtering mode */ - ENET_MAC->MCR &=~MAC_MCR_AFM; - ENET_MAC->MCR |= MAC_Config->AddressFilteringMode; - - /* VLAN Filtering Mode */ - ENET_MAC->MCR = (MAC_Config->VLANFilteringMode)<<15; - - /*Wrong Frame Pass */ - if (MAC_Config->PassWrongFrame == ENABLE) ENET_MAC->MCR |=MAC_MCR_PWF; - else ENET_MAC->MCR &=~MAC_MCR_PWF; - - /* Late Collision Retransmission*/ - if (MAC_Config->LateCollision == ENABLE) ENET_MAC->MCR |=MAC_MCR_ELC; - else ENET_MAC->MCR &=~MAC_MCR_ELC; - - /* Broadcast Frame Reception */ - if (MAC_Config->BroadcastFrameReception == ENABLE) ENET_MAC->MCR |=MAC_MCR_DBF; - else ENET_MAC->MCR &=~MAC_MCR_DBF; - - /* PacketRetry */ - if (MAC_Config->PacketRetry == ENABLE) ENET_MAC->MCR &=~MAC_MCR_DPR; - else ENET_MAC->MCR |=MAC_MCR_DPR; - - /* RxFrameFiltering */ - if (MAC_Config->RxFrameFiltering == ENABLE) ENET_MAC->MCR |=MAC_MCR_RVFF; - else ENET_MAC->MCR &=~MAC_MCR_RVFF; - - /* AutomaticPadRemoval */ - if (MAC_Config->AutomaticPadRemoval == ENABLE) ENET_MAC->MCR |=MAC_MCR_APR; - else ENET_MAC->MCR &=~MAC_MCR_APR; - - /* DefferalCheck */ - if (MAC_Config->DeferralCheck == ENABLE) ENET_MAC->MCR |=MAC_MCR_DCE; - else ENET_MAC->MCR &=~MAC_MCR_DCE; - -} - - - -/******************************************************************************* -* Function Name : ENET_SetOperatingMode -* Description : Sets the Operating mode -* Input : ENET_OperatingMode:(see ENET_OperatingMode in 91x_enet.h) -* Output : None -* Return : None -*******************************************************************************/ -portBASE_TYPE ENET_SetOperatingMode( void ) -{ -unsigned portLONG ulStatusReg, ulControlReg, ulLinkAbilityReg; - - /* Link status is latched, so read twice to get current value */ - ulStatusReg = ENET_MIIReadReg(0, STE100P_STATUS_REG); - ulStatusReg = ENET_MIIReadReg(0, STE100P_STATUS_REG); - - if( !( ulStatusReg & STE100P_STATUS_LINKED ) ) - { - /* No Link. */ - return pdFAIL; - } - - ulControlReg = ENET_MIIReadReg(0, STE100P_CONTROL_REG); - if (ulControlReg & STE100P_AUTO_NEGOTIATE_ABILITY) - { - /* AutoNegotiation is enabled. */ - if (!(ulStatusReg & STE100P_AUTO_NEGOTIATE_COMPLETE)) - { - /* Auto-negotiation in progress. */ - return pdFAIL; - } - - ulLinkAbilityReg = ENET_MIIReadReg(0, STE100P_LINK_ABILITY); - if( ( ulLinkAbilityReg & STE100P_100FULL ) || ( ulLinkAbilityReg & STE100P_10FULL ) ) - { - ENET_MAC->MCR |=MAC_MCR_FDM; /* full duplex mode */ - ENET_MAC->MCR &=~MAC_MCR_DRO; /* enable frame reception during transmission */ - } - else - { - ENET_MAC->MCR &=~MAC_MCR_FDM; /* half duplex mode */ - ENET_MAC->MCR |=MAC_MCR_DRO; /* disable frame reception during transmission */ - } - } - else - { - if( ulStatusReg & STE100P_CTRL_FULL ) - { - ENET_MAC->MCR |=MAC_MCR_FDM; /* full duplex mode */ - ENET_MAC->MCR &=~MAC_MCR_DRO; /* enable frame reception during transmission */ - } - else - { - ENET_MAC->MCR &=~MAC_MCR_FDM; /* half duplex mode */ - ENET_MAC->MCR |=MAC_MCR_DRO; /* disable frame reception during transmission */ - } - } - - return pdPASS; -} - -/******************************************************************************* -* Function Name : ENET_MIIWriteReg -* Description : Writes a value on the PHY registers -* Input : phyDev PHY device address - : phyReg PHY register to be written -* : phyVal PHY register value -* Output : None -* Return : None -*******************************************************************************/ -void ENET_MIIWriteReg (u8 phyDev, u8 phyReg, u32 phyVal) -{ - - volatile u32 addr; - volatile u32 res; /* temporary result for address register status */ - volatile u32 timeout; - - /* Prepare the MII register address */ - addr = 0; - addr |= ((phyDev<<11) & MAC_MII_ADDR_PHY_ADDR); /* set the PHY address */ - addr |= ((phyReg<<6) & MAC_MII_ADDR_MII_REG); /* select the corresponding register */ - addr |= MAC_MII_ADDR_MII_WRITE; /* in write mode */ - addr |= MAC_MII_ADDR_MII_BUSY; - - /* Check for the Busy flag */ - timeout=0; - do - { - timeout++; - res = ENET_MAC->MIIA; - } while ((res & MAC_MII_ADDR_MII_BUSY) && (timeout < (u32 )MII_WRITE_TO)); - - /* Give the value to the MII data register */ - ENET_MAC->MIID = (phyVal & 0xFFFF); - - /* write the result value into the MII Address register */ - ENET_MAC->MIIA =addr; - - /* Check for the Busy flag */ - timeout=0; - do - { - timeout++; - res = ENET_MAC->MIIA; - } while ((res & MAC_MII_ADDR_MII_BUSY) && (timeout < (u32 )MII_WRITE_TO)); - -} - -/******************************************************************************* -* Function Name : ENET_MIIReadReg -* Description : Writes a value on the PHY -* Input : phyDev PHY device address -* : phyReg PHY register to be read -* Output : None -* Return : The read value (16 bits) -*******************************************************************************/ -u32 ENET_MIIReadReg (u8 phyDev, u32 phyReg ) -{ - - u32 rValue; - u32 addr; - u32 res; /* temporary result for address register status */ - u32 timeout; /* timeout value for read process */ - - /* prepare the MII register address */ - addr = 0; - addr |= ((phyDev<<11) & MAC_MII_ADDR_PHY_ADDR); /* set the PHY address */ - addr |= ((phyReg<<6) & MAC_MII_ADDR_MII_REG); /* select the corresponding register */ - addr &= ~(MAC_MII_ADDR_MII_WRITE); /* ... in read mode */ - addr |= MAC_MII_ADDR_MII_BUSY; - - /* Check for the Busy flag */ - timeout = 0; - - do - { - timeout++; - res = ENET_MAC->MIIA; - } while ((res & MAC_MII_ADDR_MII_BUSY) && (timeout < (u32 )MII_READ_TO)); - - /* write the result value into the MII Address register */ - ENET_MAC->MIIA = addr; - - /* Check for the Busy flag */ - timeout = 0; - - do - { - timeout++; - res = ENET_MAC->MIIA; - } while ((res & MAC_MII_ADDR_MII_BUSY) && (timeout < (u32 )MII_READ_TO)); - - /* read the result value from data register*/ - rValue = ENET_MAC->MIID; - - return (rValue & 0x0000FFFF); -} - -/******************************************************************************* -* Function Name : ENET_RxDscrInit -* Description : Initializes the Rx ENET descriptor chain. Single Descriptor -* Input : None -* Output : None -* Return : None -*******************************************************************************/ - -void ENET_RxDscrInit(void) -{ -int i; - - for( i = 0; i < ENET_NUM_RX_BUFFERS; i++ ) - { - /* Assign temp Rx array to the ENET buffer */ - dmaRxDscrBase[ i ].dmaAddr = (u32)&(RxBuff[ i ][ 0 ]); - - /* Initialize RX ENET Status and control */ - dmaRxDscrBase[ i ].dmaStatCntl = 0x4000; - - /* Initialize the next descriptor- In our case its single descriptor */ - dmaRxDscrBase[ i ].dmaNext = (u32)&(dmaRxDscrBase[i+1]) | 0x01; - - /* Set the max packet size */ - dmaRxDscrBase[ i ].dmaStatCntl = ENET_MAX_PACKET_SIZE | ENET_NEXT_ENABLE; - - /* Setting the VALID bit */ - dmaRxDscrBase[ i ].dmaPackStatus = DMA_DSCR_RX_STATUS_VALID_MSK; - } - - dmaRxDscrBase[ ENET_NUM_RX_BUFFERS - 1 ].dmaNext = (u32)&(dmaRxDscrBase[ 0 ]); - - /* Setting the RX NEXT Descriptor Register inside the ENET */ - ENET_DMA->RXNDAR = (u32)&(dmaRxDscrBase) | 0x01; -} - -/******************************************************************************* -* Function Name : ENET_TxDscrInit -* Description : Initializes the Tx ENET descriptor chain with single descriptor -* Input : None -* Output : None -* Return : None -*******************************************************************************/ - -void ENET_TxDscrInit(void) -{ - - /* ENET Start Address */ - dmaTxDscrBase.dmaAddr = (u32)TxBuff; - - /* Next Descriptor Address */ - dmaTxDscrBase.dmaNext = (u32)&(dmaTxDscrBase); - - /* Initialize ENET status and control */ - dmaTxDscrBase.dmaStatCntl = 0; - - /* Tx next set to Tx decriptor base */ - ENET_DMA->TXNDAR = (u32)&(dmaTxDscrBase); - - /* Enable next enable */ - ENET_DMA->TXNDAR |= DMA_DSCR_NXT_NPOL_EN; - -} - -/******************************************************************************* -* Function Name : ENET_Init -* Description : ENET MAC, PHY and DMA initializations -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void ENET_Init () -{ - - vu32 regValue; - ENET_MACConfig *MAC_Config; - ENET_MACConfig config; - u32 macAddrLow, macAddrHigh; - - /* De-assert the SRESET bit of ENET + MAC devices */ - ENET_DMA->SCR &=~DMA_SCR_SRESET; - MAC_Config =&config; - /* Initialize MAC control register with common values */ - MAC_Config->ReceiveALL = DISABLE; - if (SCU_GetHCLKFreqValue() > 50000) - MAC_Config->MIIPrescaler = MIIPrescaler_2; - MAC_Config->LoopbackMode = DISABLE; - MAC_Config->AddressFilteringMode = MAC_Perfect_Multicast_Perfect; - MAC_Config->PassWrongFrame = DISABLE; - MAC_Config->LateCollision = DISABLE; - MAC_Config->BroadcastFrameReception = ENABLE; - MAC_Config->PacketRetry = ENABLE; - MAC_Config->RxFrameFiltering = ENABLE; - MAC_Config->AutomaticPadRemoval = ENABLE; - MAC_Config->DeferralCheck = ENABLE; - - /* Configure MAC control register */ - ENET_MACControlConfig(MAC_Config); - - /* DMA initialization */ - /* Read the ENET DMA Status and Control Register */ - regValue = ENET_DMA->SCR; - - /* Setup Tx Max burst size */ - regValue &= ~(u32)DMA_SCR_TX_MAX_BURST_SZ; - regValue |= (u32)DMA_SCR_TX_MAX_BURST_SZ_VAL; - - /* Setup Rx Max Burst size */ - regValue &= ~(u32)DMA_SCR_RX_MAX_BURST_SZ; - regValue |= (u32)DMA_SCR_RX_MAX_BURST_SZ_VAL; - - /* Write Tx & Rx burst size to the ENET status and control register */ - ENET_DMA->SCR = regValue; - - /* Put the PHY in reset mode */ - ENET_MIIWriteReg(0x0,MAC_MII_REG_XCR, 0x8000); - - /* Delay to assure PHY reset */ - vTaskDelay( 3000 ); - - /* initialize the opearting mode */ - while( ENET_SetOperatingMode() == pdFAIL ) - { - vTaskDelay( 3000 ); - } - - /*set MAC physical*/ - macAddrLow = (MAC_ADDR3<<24) + (MAC_ADDR2<<16) + \ - (MAC_ADDR1<<8) + MAC_ADDR0; - - // Higher MAC address - macAddrHigh = (MAC_ADDR5<<8) + MAC_ADDR4; - - /* Initialize Rx and Tx descriptors in memory */ - ENET_TxDscrInit(); - ENET_RxDscrInit(); -} - -/******************************************************************************** -* Function Name : ENET_HandleRxPkt -* Description : receive a packet and copy it to memory pointed by ppkt. -* Input : ppkt: pointer on application receive buffer. -* Output : None -* Return : ENET_NOK - If there is no packet -* : ENET_OK - If there is a packet -*******************************************************************************/ -u32 ENET_HandleRxPkt ( void *ppkt) -{ -ENET_DMADSCRBase *pDescr; -u16 size; -static int iNextRx = 0; - - if( dmaRxDscrBase[ iNextRx ].dmaPackStatus & DMA_DSCR_RX_STATUS_VALID_MSK ) - { - return 0; - } - - pDescr = &dmaRxDscrBase[ iNextRx ]; - - /*Get the size of the packet*/ - size = ((pDescr->dmaPackStatus & 0x7ff) - 4); - - //MEMCOPY_L2S_BY4((u8*)ppkt, RxBuff, size); /*optimized memcopy function*/ - memcpy(ppkt, RxBuff[iNextRx], size); //string.h library*/ - - /* Give the buffer back to ENET */ - pDescr->dmaPackStatus = DMA_DSCR_RX_STATUS_VALID_MSK; - - iNextRx++; - - if( iNextRx >= ENET_NUM_RX_BUFFERS ) - { - iNextRx = 0; - } - - /* Return no error */ - return size; -} - -/******************************************************************************* -* Function Name : ENET_TxPkt -* Description : Transmit a packet -* Input : ppkt: pointer to application packet Buffer -* : size: Tx Packet size -* Output : None -* Return : None -*******************************************************************************/ - -u8 *pcGetNextBuffer( void ) -{ - if( dmaTxDscrBase.dmaPackStatus & DMA_DSCR_TX_STATUS_VALID_MSK ) - { - return NULL; - } - else - { - return ( unsigned char * ) TxBuff; - } -} - -void ENET_TxPkt(void *ppkt, u16 size) -{ - /* Setting the Frame Length*/ - dmaTxDscrBase.dmaStatCntl = (size&0xFFF); - - /* Start the ENET by setting the VALID bit in dmaPackStatus of current descr*/ - dmaTxDscrBase.dmaPackStatus = DMA_DSCR_TX_STATUS_VALID_MSK; - - /* Start the transmit operation */ - ENET_DMA->TXSTR|= DMA_TX_START_FETCH; -} - -/******************************************************************************* -* Function Name : ENET_Start -* Description : Enables ENET MAC reception / transmission & starts DMA fetch -* Input : None -* Output : None -* Return : None -*******************************************************************************/ - -void ENET_Start ( void) -{ - u32 value; - - /* Force a ENET abort by software for the receive block */ - ENET_DMA->RXSTR &=~ DMA_RX_START_DMA_EN; - - /* Force a ENET abort by software for the transmit block */ - ENET_DMA->TXSTR &=~DMA_TX_START_DMA_EN; - - /* Reset all interrupts */ - ENET_DMA->ISR = 0xFFFFFFFF; - - /* Setup Descriptor Fetch ENET_PhyDelay for Receive Block */ - value = ENET_DMA->RXSTR; - value &= ~( DMA_RX_START_DFETCH_DLY ); - value |= DMA_RX_START_DFETCH_DEFAULT; - ENET_DMA->RXSTR= value; - - /* Setup Descriptor Fetch ENET_PhyDelay for Transmit Block */ - value = ENET_DMA->TXSTR; - value &= ~( DMA_TX_START_DFETCH_DLY ); - value |= DMA_TX_START_DFETCH_DEFAULT; - ENET_DMA->TXSTR= value; - - /* Set Tx underrun bit */ - value &= ~( DMA_TX_START_URUN ); - value |= DMA_TX_START_URUN; - ENET_DMA->TXSTR = value; - - /* Clear the interrupts */ - ENET_DMA->IER = 0x0; - - /* MAC TX enable */ - ENET_MAC->MCR|= MAC_MCR_TE; - - /* MAC RX enable */ - ENET_MAC->MCR|= MAC_MCR_RE; - - /* Start the DMA Fetch */ - ENET_DMA->RXSTR|= DMA_RX_START_FETCH; -} - - -/******************************************************************************* -* Function Name : ENET_InitClocksGPIO -* Description : Reset, clocks & GPIO Ethernet Pin initializations -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void ENET_InitClocksGPIO(void) -{ - - GPIO_InitTypeDef GPIO_Struct; - - SCU_AHBPeriphClockConfig(__ENET, ENABLE); - SCU_AHBPeriphReset(__ENET,DISABLE); - SCU_PHYCLKConfig(ENABLE); - - GPIO_DeInit(GPIO1); - GPIO_Struct.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 |GPIO_Pin_3 |GPIO_Pin_4 |GPIO_Pin_7 ; - GPIO_Struct.GPIO_Type = GPIO_Type_PushPull; - GPIO_Struct.GPIO_Direction = GPIO_PinOutput; - GPIO_Struct.GPIO_IPConnected = GPIO_IPConnected_Disable; - GPIO_Struct.GPIO_Alternate=GPIO_OutputAlt2; - GPIO_Init(GPIO1, &GPIO_Struct); - - - GPIO_DeInit(GPIO5); - GPIO_Struct.GPIO_Pin = GPIO_Pin_2 | GPIO_Pin_3; - GPIO_Struct.GPIO_Type = GPIO_Type_PushPull; - GPIO_Struct.GPIO_Direction = GPIO_PinOutput; - GPIO_Struct.GPIO_IPConnected = GPIO_IPConnected_Disable; - GPIO_Struct.GPIO_Alternate=GPIO_OutputAlt2; - GPIO_Init(GPIO5, &GPIO_Struct); - -} - -/******************** (C) COPYRIGHT 2006 STMicroelectronics *******************/ - - diff --git a/Demo/ARM9_STR91X_IAR/Library/source/91x_fmi.c b/Demo/ARM9_STR91X_IAR/Library/source/91x_fmi.c deleted file mode 100644 index fb558ada6..000000000 --- a/Demo/ARM9_STR91X_IAR/Library/source/91x_fmi.c +++ /dev/null @@ -1,519 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 91x_fmi.c -* Author : MCD Application Team -* Date First Issued : 05/18/2006 : Version 1.0 -* Description : This file provides all the FMI software functions. -******************************************************************************** -* History: -* 05/24/2006 : Version 1.1 -* 05/18/2006 : Version 1.0 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH -* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS -* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT -* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT -* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION -* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - - -/* Standard include ----------------------------------------------------------*/ -#include "91x_fmi.h" - -/* Include of other module interface headers ---------------------------------*/ -/* Local includes ------------------------------------------------------------*/ -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -#define TIMEOUT 0xFFFFFF /* Timeout value */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Interface functions -------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - - -/******************************************************************************* -* Function Name : FMI_BankRemapConfig -* Description : Configure the addresses and sizes of bank 0 and bank 1. -* Input1 : FMI_BootBankSize: specifies the boot bank size. -* This parameter can be one of the following values: -* - 0x0: 32KBytes. -* - 0x1: 64KBytes. -* - 0x2: 128KBytes. -* - 0x3: 256KBytes. -* - 0x4: 512KBytes. -* .... -* - 0xB: 64MBytes. -* Input2 : FMI_NonBootBankSize: specifies the non boot bank size. -* This parameter can be one of the following values: -* - 0x0: 8KBytes. -* - 0x1: 16KBytes. -* - 0x2: 32KBytes. -* - 0x3: 64KBytes. -* .... -* - 0xD: 64MBytes. -* Input3 : FMI_BootBankAddress: specifies the address of the boot bank. -* Input4 : FMI_NonBootBankAddress: specifies the address of the non -* boot bank. -* Output : None -* Return : None -*******************************************************************************/ -void FMI_BankRemapConfig(u8 FMI_BootBankSize, u8 FMI_NonBootBankSize, \ - u32 FMI_BootBankAddress, u32 FMI_NonBootBankAddress) -{ - FMI->BBSR = FMI_BootBankSize; - FMI->NBBSR = FMI_NonBootBankSize; - FMI->BBADR = (FMI_BootBankAddress >> 2); - FMI->NBBADR = (FMI_NonBootBankAddress >> 2); - FMI->CR |= 0x18; /* Enable bank 1 */ -} - -/******************************************************************************* -* Function Name : FMI_Config -* Description : Configure the FMI. -* Input1 : FMI_ReadWaitState: specifies the needed read wait states. -* This parameter can be one of the following values: -* - FMI_READ_WAIT_STATE_1: One read wait state. -* - FMI_READ_WAIT_STATE_2: Two read wait states. -* - FMI_READ_WAIT_STATE_3: Three read wait states. -* Input2 : FMI_WriteWaitState: specifies the needed write wait states. -* This parameter can be one of the following values: -* - FMI_WRITE_WAIT_STATE_1: One write wait state. -* - FMI_WRITE_WAIT_STATE_2: Two write wait states. -* Input3 : FMI_PWD: specifies the power down mode status. -* This parameter can be one of the following values: -* - FMI_PWD_ENABLE: Enable the PWD. -* - FMI_PWD_DISABLE: Disable the PWD. -* Input4 : FMI_LVDEN: specifies the low voltage detector status. -* This parameter can be one of the following values: -* - FMI_LVD_ENABLE: Enable the LVD. -* - FMI_LVD_DISABLE: Disable the LVD. -* Input5 : FMI_FreqRange: specifies the working frequency range. -* This parameter can be one of the following values: -* - FMI_FREQ_LOW: Low working frequency (up to 66MHz). -* - FMI_FREQ_HIGH: High working frequency (above 66MHz) . -* Output : None -* Return : None -*******************************************************************************/ -void FMI_Config(u16 FMI_ReadWaitState, u32 FMI_WriteWaitState, u16 FMI_PWD,\ - u16 FMI_LVDEN, u16 FMI_FreqRange) -{ - /* Configure the write wait state value */ - if (FMI_WriteWaitState == FMI_WRITE_WAIT_STATE_1) - { - FMI->CR |= FMI_WRITE_WAIT_STATE_1; - } - else - { - FMI->CR &= FMI_WRITE_WAIT_STATE_0; - } - - /* Write a write flash configuration register command */ - *(vu16 *)FMI_BANK_1 = 0x60; - - /* Configure the flash configuration register */ - *(vu16 *)(FMI_BANK_1|FMI_ReadWaitState|FMI_PWD|FMI_LVDEN|FMI_FreqRange) = 0x03; -} - -/******************************************************************************* -* Function Name : FMI_EraseSector -* Description : Erase the needed sector. -* Input : FMI_Sector: specifies the sector to be erased. -* This parameter can be one of the following values: -* - FMI_B0S0: FMI bank 0 sector 0. -* - FMI_B0S1: FMI bank 0 sector 1. -* - FMI_B0S2: FMI bank 0 sector 2. -* - FMI_B0S3: FMI bank 0 sector 3. -* - FMI_B0S4: FMI bank 0 sector 4. -* - FMI_B0S5: FMI bank 0 sector 5. -* - FMI_B0S6: FMI bank 0 sector 6. -* - FMI_B0S7: FMI bank 0 sector 7. -* - FMI_B1S0: FMI bank 1 sector 0. -* - FMI_B1S1: FMI bank 1 sector 1. -* - FMI_B1S2: FMI bank 1 sector 2. -* - FMI_B1S3: FMI bank 1 sector 3. -* Output : None -* Return : None -*******************************************************************************/ -void FMI_EraseSector(vu32 FMI_Sector) -{ - /* Write an erase set-up command to the sector */ - *(vu16 *)FMI_Sector = 0x20; - - /* Write an erase confirm command to the sector */ - *(vu16 *)FMI_Sector = 0xD0; -} - -/******************************************************************************* -* Function Name : FMI_EraseBank -* Description : Erase the needed bank. -* Input : FMI_Bank: specifies the bank to be erased. -* This parameter can be one of the following values: -* - FMI_BANK_0: FMI bank 0. -* - FMI_BANK_1: FMI bank 1. -* Output : None -* Return : None -*******************************************************************************/ -void FMI_EraseBank(vu32 FMI_Bank) -{ - /* Write a bank erase set-up command to the bank */ - *(vu16 *)FMI_Bank = 0x80; - - /* Write an erase confirm command to the sector */ - *(vu16 *)FMI_Bank = 0xD0; -} - -/******************************************************************************* -* Function Name : FMI_WriteHalfWord -* Description : Write a halfword to the needed Flash memory address. -* Input 1 : FMI_Address: specifies the address offset where the data will -* be written. -* Input 2 : FMI_Data: the needed data. -* Output : None -* Return : None -*******************************************************************************/ -void FMI_WriteHalfWord(u32 FMI_Address, u16 FMI_Data) -{ - /* Write a program command to the sector to be written */ - *(vu16 *)(FMI_Address & 0xFFFFFFFC) = 0x40; - - /* Write the halfword to the destination address */ - *(vu16 *)FMI_Address = FMI_Data; -} - -/******************************************************************************* -* Function Name : FMI_WriteOTPHalfWord -* Description : Write a halfword to the needed OTP sector address. -* Input 1 : FMI_OTPHWAddress: specifies the halfword address offset -* where the data will be written. -* This parameter can be one of the following values: -* - FMI_OTP_LOW_HALFWORD_0: OTP Low halfword 0. -* - FMI_OTP_HIGH_HALFWORD_0: OTP High halfword 0. -* - FMI_OTP_LOW_HALFWORD_1: OTP Low halfword 1. -* - FMI_OTP_HIGH_HALFWORD_1: OTP High halfword 1. -* - FMI_OTP_LOW_HALFWORD_2: OTP Low halfword 2. -* - FMI_OTP_HIGH_HALFWORD_2: OTP High halfword 2. -* - FMI_OTP_LOW_HALFWORD_3: OTP Low halfword 3. -* - FMI_OTP_HIGH_HALFWORD_3: OTP High halfword 3. -* - FMI_OTP_LOW_HALFWORD_4: OTP Low halfword 4. -* - FMI_OTP_HIGH_HALFWORD_4: OTP High halfword 4. -* - FMI_OTP_LOW_HALFWORD_5: OTP Low halfword 5. -* - FMI_OTP_HIGH_HALFWORD_5: OTP High halfword 5. -* - FMI_OTP_LOW_HALFWORD_6: OTP Low halfword 6. -* - FMI_OTP_HIGH_HALFWORD_6: OTP High halfword 6. -* - FMI_OTP_LOW_HALFWORD_7: OTP Low halfword 7. -* - FMI_OTP_HIGH_HALFWORD_7: OTP High halfword 7. -* Input 2 : FMI_OTPData: The needed OTP data. -* Output : None -* Return : None -*******************************************************************************/ -void FMI_WriteOTPHalfWord(u8 FMI_OTPHWAddress, u16 FMI_OTPData) -{ - /* Write a write OTP command to the needed address */ - *(vu16 *)(FMI_BANK_1) = 0xC0; - - /* Write the halfword to the destination address */ - *(vu16 *)(FMI_BANK_1 + FMI_OTPHWAddress) = FMI_OTPData; -} - -/******************************************************************************* -* Function Name : FMI_ReadWord -* Description : Read the correspondent data. -* Input : FMI_Address: specifies the needed address. -* Output : None -* Return : The data contained in the specified address. -*******************************************************************************/ -u32 FMI_ReadWord(u32 FMI_Address) -{ - return(*(u32*)FMI_Address); -} - -/******************************************************************************* -* Function Name : FMI_ReadOTPData -* Description : Read data from the OTP sector. -* Input : FMI_OTPAddress: specifies the address of the data to be read. -* This parameter can be one of the following values: -* - FMI_OTP_WORD_0: FMI bank 0 sector 0. -* - FMI_OTP_WORD_1: FMI bank 0 sector 1. -* - FMI_OTP_WORD_2: FMI bank 0 sector 2. -* - FMI_OTP_WORD_3: FMI bank 0 sector 3. -* - FMI_OTP_WORD_4: FMI bank 0 sector 4. -* - FMI_OTP_WORD_5: FMI bank 0 sector 5. -* - FMI_OTP_WORD_6: FMI bank 0 sector 6. -* - FMI_OTP_WORD_7: FMI bank 0 sector 7. -* Output : None -* Return : The needed OTP words. -*******************************************************************************/ -u32 FMI_ReadOTPData(u8 FMI_OTPAddress) -{ - u32 OTP_Data = 0x0; - /* write a read OTP sector command */ - *(vu16 *)(FMI_BANK_1) = 0x98; - - /* Read the correspondent data */ - OTP_Data = (*(vu32*)(FMI_BANK_1 + FMI_OTPAddress)); - - /* Write a read array command */ - *(vu16 *)(FMI_BANK_1) = 0xFF; - - return OTP_Data; -} - -/******************************************************************************* -* Function Name : FMI_GetFlagStatus -* Description : Check whether the specified FMI flag is set or not. -* Input1 : FMI_Flag: flag to check. -* This parameter can be one of the following values: -* - FMI_FLAG_SPS: Sector Protection Status Flag. -* - FMI_FLAG_PSS: Program Suspend Status Flag. -* - FMI_FLAG_PS: Program Status Flag. -* - FMI_FLAG_ES: Erase Status Flag. -* - FMI_FLAG_ESS: Erase Suspend Status Flag. -* - FMI_FLAG_PECS: FPEC Status Flag. -* Input2 : FMI_Bank: specifies the needed bank. -* This parameter can be one of the following values: -* - FMI_BANK_0: FMI bank 0. -* - FMI_BANK_1: FMI bank 1. -* Output : None -* Return : None -*******************************************************************************/ -FlagStatus FMI_GetFlagStatus(u8 FMI_Flag, vu32 FMI_Bank) -{ - u16 FMI_Status_Register = 0; - - /* Write a read status register command */ - *(vu16 *)FMI_Bank = 0x70; - - /* Wait until operation completion */ - while(!((*(vu16 *)FMI_Bank) & 0x80)); - - /* Read the status register */ - FMI_Status_Register = *(vu16 *)FMI_Bank; - - /* Write a read array command */ - *(vu16 *)FMI_Bank = 0xFF; - - if((FMI_Status_Register & FMI_Flag) != RESET) - { - return SET; - } - else - { - return RESET; - } -} - -/******************************************************************************* -* Function Name : FMI_GetReadWaitStateValue -* Description : Get the current Read wait state value. -* Input : None -* Output : None -* Return : The current read wait states value. -*******************************************************************************/ -u16 FMI_GetReadWaitStateValue(void) -{ - u16 FMI_Configuration_Register = 0; - /* Write a read flash configuration register command */ - *(vu16 *)FMI_BANK_1 = 0x90; - - /* Read the flash configuration register */ - FMI_Configuration_Register = *(vu16 *)(FMI_BANK_1 + 0x14); - - /* Write a read array command */ - *(vu16 *)FMI_BANK_1 = 0xFF; - - FMI_Configuration_Register = ((FMI_Configuration_Register>>11) + 1) & 0x3; - - /* Return the wait states value */ - return FMI_Configuration_Register; -} - -/******************************************************************************* -* Function Name : FMI_GetWriteWaitStateValue -* Description : Get the current write wait state value. -* Input : None -* Output : None -* Return : The current write wait states value. -*******************************************************************************/ -u16 FMI_GetWriteWaitStateValue(void) -{ - return ((u16)((FMI->CR & 0x100) >> 8)); -} - -/******************************************************************************* -* Function Name : FMI_SuspendEnable -* Description : Suspend command enable. -* Input : FMI_Bank: specifies the bank to be suspended. -* This parameter can be one of the following values: -* - FMI_BANK_0: FMI bank 0. -* - FMI_BANK_1: FMI bank 1. -* Output : None -* Return : None -*******************************************************************************/ -void FMI_SuspendEnable(vu32 FMI_Bank) -{ - /* Write a suspend command to the bank */ - *(vu16 *)FMI_Bank = 0xB0; -} - -/******************************************************************************* -* Function Name : FMI_ResumeEnable -* Description : Resume the suspended command. -* Input : FMI_Bank: specifies the suspended bank. -* This parameter can be one of the following values: -* - FMI_BANK_0: FMI bank 0. -* - FMI_BANK_1: FMI bank 1. -* Output : None -* Return : None -*******************************************************************************/ -void FMI_ResumeEnable(vu32 FMI_Bank) -{ - /* Write a resume command to the bank */ - *(vu16 *)FMI_Bank = 0xD0; -} - -/******************************************************************************* -* Function Name : FMI_ClearFlag -* Description : Clear the FMI Flags on the correspondent bank. -* Input : FMI_Bank: specifies the needed bank. -* This parameter can be one of the following values: -* - FMI_BANK_0: FMI bank 0. -* - FMI_BANK_1: FMI bank 1. -* Output : None -* Return : None -*******************************************************************************/ -void FMI_ClearFlag(vu32 FMI_Bank) -{ - /* Write a clear status register command */ - *(vu16 *)FMI_Bank = 0x50; -} - -/******************************************************************************* -* Function Name : FMI_WriteProtectionCmd -* Description : Enable or disable the write protection for the needed sector. -* Input1 : FMI_Sector: specifies the sector to be protected or -* unprotected. -* This parameter can be one of the following values: -* - FMI_B0S0: FMI bank 0 sector 0. -* - FMI_B0S1: FMI bank 0 sector 1. -* - FMI_B0S2: FMI bank 0 sector 2. -* - FMI_B0S3: FMI bank 0 sector 3. -* - FMI_B0S4: FMI bank 0 sector 4. -* - FMI_B0S5: FMI bank 0 sector 5. -* - FMI_B0S6: FMI bank 0 sector 6. -* - FMI_B0S7: FMI bank 0 sector 7. -* - FMI_B1S0: FMI bank 1 sector 0. -* - FMI_B1S1: FMI bank 1 sector 1. -* - FMI_B1S2: FMI bank 1 sector 2. -* - FMI_B1S3: FMI bank 1 sector 3. -* Input2 : FMI_NewState: specifies the protection status. -* This parameter can be one of the following values: -* - ENABLE: Enable the protection. -* - DISABLE: Disable the protection. -* Output : None -* Return : None -*******************************************************************************/ -void FMI_WriteProtectionCmd(vu32 FMI_Sector, FunctionalState FMI_NewState) -{ - if (FMI_NewState == ENABLE) - { - *(vu16*)FMI_Sector = 0x60; - *(vu16*)FMI_Sector = 0x01; - *(vu16*)FMI_Sector = 0xFF; - } - else /* DISABLE */ - { - *(vu16*)FMI_Sector = 0x60; - *(vu16*)FMI_Sector = 0xD0; - *(vu16*)FMI_Sector = 0xFF; - } -} - -/******************************************************************************* -* Function Name : FMI_GetWriteProtectionStatus -* Description : Get the write protection status for the needed sector. -* Input : FMI_Sector_Mask: specifies the needed sector mask. -* This parameter can be one of the following values: -* - FMI_B0S0_MASK: FMI bank 0 sector 0. -* - FMI_B0S1_MASK: FMI bank 0 sector 1. -* - FMI_B0S2_MASK: FMI bank 0 sector 2. -* - FMI_B0S3_MASK: FMI bank 0 sector 3. -* - FMI_B0S4_MASK: FMI bank 0 sector 4. -* - FMI_B0S5_MASK: FMI bank 0 sector 5. -* - FMI_B0S6_MASK: FMI bank 0 sector 6. -* - FMI_B0S7_MASK: FMI bank 0 sector 7. -* - FMI_B1S0_MASK: FMI bank 1 sector 0. -* - FMI_B1S1_MASK: FMI bank 1 sector 1. -* - FMI_B1S2_MASK: FMI bank 1 sector 2. -* - FMI_B1S3_MASK: FMI bank 1 sector 3. -* Output : None -* Return : The Protection Status of the needed sector. -* - RESET: The needed sector is not write protected. -* - SET : The needed sector is write protected. -*******************************************************************************/ -FlagStatus FMI_GetWriteProtectionStatus(u32 FMI_Sector_Mask) -{ - u16 Protection_Level_1_Register = 0; - /* Write a read flash protection level 1 register command */ - *(vu16 *)FMI_BANK_1 = 0x90; - - /* Read the flash protection level 1 register */ - Protection_Level_1_Register = *(vu16 *)(FMI_BANK_1 + 0x10); - - /* Write a read array command */ - *(vu16 *)FMI_BANK_1 = 0xFF; - - if (Protection_Level_1_Register &= FMI_Sector_Mask) - { - return SET; - } - else - { - return RESET; - } -} - -/******************************************************************************* -* Function Name : FMI_WaitForLastOperation -* Description : Wait until the last operation (Write halfword, Write OTP -* halfword, Erase sector and Erase bank) completion. -* Input : FMI_Bank: specifies the bank where the operation is on going. -* This parameter can be one of the following values: -* - FMI_BANK_0: FMI bank 0. -* - FMI_BANK_1: FMI bank 1. -* Output : None -* Return : The timeout status. -* This parameter can be one of the following values: -* - FMI_TIME_OUT_ERROR: Timeout error occurred. -* - FMI_NO_TIME_OUT_ERROR: No timeout error. -*******************************************************************************/ -u8 FMI_WaitForLastOperation(vu32 FMI_Bank) -{ - u32 Time_Out = 0; - - /* Write a read status register command */ - *(vu16 *)(FMI_Bank) = 0x70; - - /* Wait until operation compeletion */ - while((!((*(vu16 *)FMI_Bank) & 0x80))&&(Time_Out < TIMEOUT )) - { - Time_Out ++; /* Time Out */ - } - - /* Write a read array command */ - *(vu16 *)FMI_Bank = 0xFF; - - if (Time_Out == TIMEOUT) - { - return FMI_TIME_OUT_ERROR; - } - else - { - return FMI_NO_TIME_OUT_ERROR; - } -} - - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM9_STR91X_IAR/Library/source/91x_gpio.c b/Demo/ARM9_STR91X_IAR/Library/source/91x_gpio.c deleted file mode 100644 index f2d094199..000000000 --- a/Demo/ARM9_STR91X_IAR/Library/source/91x_gpio.c +++ /dev/null @@ -1,407 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 91x_gpio.c -* Author : MCD Application Team -* Date First Issued : 05/18/2006 : Version 1.0 -* Description : This file provides all the GPIO software functions. -******************************************************************************** -* History: -* 05/24/2006 : Version 1.1 -* 05/18/2006 : Version 1.0 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -#include "91x_gpio.h" -#include "91x_scu.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ - static u8 GPIO_GetGPIONumber(GPIO_TypeDef* GPIOx); - -/* Private functions ---------------------------------------------------------*/ - -/******************************************************************************* -* Function Name : GPIO_DeInit -* Description : Deinitializes the GPIOx peripheral registers to their default -* reset values. -* Input : GPIOx: where x can be (0..9) to select the GPIO peripheral. -* Output : None -* Return : None -*******************************************************************************/ -void GPIO_DeInit(GPIO_TypeDef* GPIOx) -{ - - /* Reset the GPIO registers values */ - if(GPIOx == GPIO0) - { - SCU_APBPeriphReset(__GPIO0,ENABLE); - SCU_APBPeriphReset(__GPIO0,DISABLE); - SCU->GPIOTYPE[0x00] = 0x0000 ; - SCU->GPIOOUT[0x00] = 0x0000; - SCU->GPIOIN[0x00] = 0x0000; - } - - if(GPIOx == GPIO1) - { - SCU_APBPeriphReset(__GPIO1,ENABLE); - SCU_APBPeriphReset(__GPIO1,DISABLE); - SCU->GPIOTYPE[0x01] = 0x0000 ; - SCU->GPIOOUT[0x01] = 0x0000; - SCU->GPIOIN[0x01] = 0x0000; - } - - if(GPIOx == GPIO2) - { - SCU_APBPeriphReset(__GPIO2,ENABLE); - SCU_APBPeriphReset(__GPIO2,DISABLE); - SCU->GPIOTYPE[0x02] = 0x0000 ; - SCU->GPIOOUT[0x02] = 0x0000; - SCU->GPIOIN[0x02] = 0x0000; - } - - if(GPIOx == GPIO3) - { - SCU_APBPeriphReset(__GPIO3,ENABLE); - SCU_APBPeriphReset(__GPIO3,DISABLE); - SCU->GPIOTYPE[0x03] = 0x0000 ; - SCU->GPIOOUT[0x03] = 0x0000; - SCU->GPIOIN[0x03] = 0x0000; - } - - if(GPIOx == GPIO4) - { - SCU_APBPeriphReset(__GPIO4,ENABLE); - SCU_APBPeriphReset(__GPIO4,DISABLE); - SCU->GPIOTYPE[0x04] = 0x0000 ; - SCU->GPIOOUT[0x04] = 0x0000; - SCU->GPIOIN[0x04] = 0x0000; - SCU->GPIOANA = 0x00; - } - - if(GPIOx == GPIO5) - { - SCU_APBPeriphReset(__GPIO5,ENABLE); - SCU_APBPeriphReset(__GPIO5,DISABLE); - SCU->GPIOTYPE[0x05] = 0x0000 ; - SCU->GPIOOUT[0x05] = 0x0000; - SCU->GPIOIN[0x05] = 0x0000; - } - - if(GPIOx == GPIO6) - { - SCU_APBPeriphReset(__GPIO6,ENABLE); - SCU_APBPeriphReset(__GPIO6,DISABLE); - SCU->GPIOTYPE[0x06] = 0x0000 ; - SCU->GPIOOUT[0x06] = 0x0000; - SCU->GPIOIN[0x06] = 0x0000; - } - - if(GPIOx == GPIO7) - { - SCU_APBPeriphReset(__GPIO7,ENABLE); - SCU_APBPeriphReset(__GPIO7,DISABLE); - SCU->GPIOOUT[0x07] = 0xAAAA; - SCU->GPIOOUT[0x07] = 0x0000; - SCU->GPIOIN[0x07] = 0x0000; - } - - if(GPIOx == GPIO8) - { - SCU_APBPeriphReset(__GPIO8,ENABLE); - SCU_APBPeriphReset(__GPIO8,DISABLE); - SCU->GPIOEMI = 0x00; - } - - if(GPIOx == GPIO9) - { - SCU_APBPeriphReset(__GPIO9,ENABLE); - SCU_APBPeriphReset(__GPIO9,DISABLE); - SCU->GPIOEMI = 0x00; - } -} -/******************************************************************************* -* Function Name : GPIO_Init -* Description : Initializes the GPIOx peripheral according to the specified -* parameters in the GPIO_InitStruct . -* Input :- GPIOx: where x can be (0..9) to select the GPIO peripheral. -* - GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that -* contains the configuration information for the specified GPIO -* peripheral. -* Output : None -* Return : None -*******************************************************************************/ -void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) -{ - /* Select pin direction */ - u8 PinNumber = 0; - u8 Counter = 0; - u8 GPIO_Number = 0; - - GPIO_Number = GPIO_GetGPIONumber(GPIOx); - - - if(GPIO_InitStruct->GPIO_Direction == GPIO_PinOutput) - { - GPIOx->DDR |= GPIO_InitStruct->GPIO_Pin; - } - else - { - GPIOx->DDR &= ~GPIO_InitStruct->GPIO_Pin; - } - - for (Counter = 0; Counter < 8;Counter++) - { - /*Search pin number*/ - PinNumber = (GPIO_InitStruct->GPIO_Pin & (1 <> Counter) == 1) - { - /*Output ALternate 0*/ - SCU->GPIOOUT[GPIO_Number] &= ~(0x3 <<(Counter *2)); - if(GPIO_InitStruct->GPIO_Alternate == GPIO_OutputAlt1) - { - /*Output ALternate 1*/ - SCU->GPIOOUT[GPIO_Number] |= 1 << (Counter *2); - } - if(GPIO_InitStruct->GPIO_Alternate == GPIO_OutputAlt2) - { - /*Output ALternate 2*/ - SCU->GPIOOUT[GPIO_Number] |= 0x2 << (Counter *2); - } - if(GPIO_InitStruct->GPIO_Alternate == GPIO_OutputAlt3) - { - /*Output ALternate 3*/ - SCU->GPIOOUT[GPIO_Number] |= 0x3 << (Counter *2); - } - - /*Type configuration: PushPull or Open Collector*/ - SCU->GPIOTYPE[GPIO_Number] &= ~(0x1 << Counter) ; - if(GPIO_InitStruct->GPIO_Type == GPIO_Type_OpenCollector) - { - /*Open Drain configuration*/ - SCU->GPIOTYPE[GPIO_Number] |= 0x1 << Counter; - } - - /*IP Connected disable*/ - SCU->GPIOIN[GPIO_Number] &= ~(0x1 << Counter) ; - if(GPIO_InitStruct->GPIO_IPConnected == GPIO_IPConnected_Enable) - { - /*IP Connected enable*/ - SCU->GPIOIN[GPIO_Number] |= 0x1 << Counter; - } - } - } -} - -/******************************************************************************* -* Function Name : GPIO_StructInit -* Description : Initialize the GPIO Init Structure parameters -* Input : GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure -* which will be initialized. -* Output : None -* Return : None -*******************************************************************************/ -void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) -{ - /* Reset GPIO init structure parameters values */ - GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; - GPIO_InitStruct->GPIO_Direction = GPIO_PinInput; - GPIO_InitStruct->GPIO_Type = GPIO_Type_PushPull; - GPIO_InitStruct->GPIO_IPConnected = GPIO_IPConnected_Disable; - GPIO_InitStruct->GPIO_Alternate = GPIO_InputAlt1; -} - -/******************************************************************************* -* Function Name : GPIO_ReadBit -* Description : Reads the specified port pin -* Input : - GPIOx: where x can be (0..9) to select the GPIO peripheral. -* : - GPIO_Pin: the Pin number. This parameter can be GPIO_Pin_x -* where x can be (0..7). -* Output : None -* Return : The port pin value -*******************************************************************************/ -u8 GPIO_ReadBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin) -{ - if ((((GPIOx->DR[GPIO_Pin<<2])) & GPIO_Pin) != Bit_RESET ) - { - return Bit_SET; - } - else - { - return Bit_RESET; - } -} - -/******************************************************************************* -* Function Name : GPIO_Read -* Description : Reads the specified GPIO data port -* Input : - GPIOx: where x can be (0..9) to select the GPIO peripheral. -* Output : None -* Return : GPIO data port word value. -*******************************************************************************/ -u8 GPIO_Read(GPIO_TypeDef* GPIOx) -{ - return (GPIOx->DR[0x3FC]); -} - -/******************************************************************************* -* Function Name : GPIO_WriteBit -* Description : Sets or clears the selected data port bit. -* Input : - GPIOx: where x can be (0..9) to select the GPIO peripheral. -* - GPIO_Pin: the Pin number. This parameter can be GPIO_Pin_x -* where x can be (0..7). -* - BitVal: this parameter specifies the value to be written -* to the selected bit. -* BitVal must be one of the BitAction enum values: -* - Bit_RESET: to clear the port pin -* - Bit_SET: to set the port pin -* Output : None -* Return : None -*******************************************************************************/ -void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin, BitAction BitVal) -{ - if(BitVal == Bit_SET) - { - GPIOx->DR[GPIO_Pin <<2] = GPIO_Pin; - } - else - { - GPIOx->DR[GPIO_Pin <<2] = 0x00; - } -} - -/******************************************************************************* -* Function Name : GPIO_Write -* Description : Writes the passed value in the selected data GPIOx port -* register. -* Input :- GPIOx: where x can be (0..9) to select the GPIO peripheral. -* - PortVal: the value to be written to the data port register. -* Output : None -* Return : None -*******************************************************************************/ -void GPIO_Write(GPIO_TypeDef* GPIOx, u8 PortVal) -{ - GPIOx->DR[0x3FC] = PortVal; -} - -/******************************************************************************* -* Function Name : GPIO_EMIConfig -* Description : Enables or disables GPIO 8 and 9 in EMI mode. -* Input : - NewState: new state of the EMI. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void GPIO_EMIConfig(FunctionalState NewState) -{ - if(NewState == ENABLE) - { - SCU->GPIOEMI = 0x01; - } - else - { - SCU->GPIOEMI = 0x00; - } -} - -/******************************************************************************* -* Function Name : GPIO_ANAPinConfig -* Description : Enables or disables pins from GPIO 4 in Analogue mode. -* Input :- GPIO_ANAChannel: selects the ADC channel pin. -* This parameter can be one of the following values: -* GPIO_ANAChannel0 -* GPIO_ANAChannel1 -* GPIO_ANAChannel2 -* GPIO_ANAChannel3 -* GPIO_ANAChannel4 -* GPIO_ANAChannel5 -* GPIO_ANAChannel6 -* GPIO_ANAChannel7 -* GPIO_ANAChannelALL -* - NewState: new state of the port pin. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void GPIO_ANAPinConfig(u8 GPIO_ANAChannel, FunctionalState NewState) -{ - - if(NewState == ENABLE) - { - if(GPIO_ANAChannel == GPIO_ANAChannelALL) - { - SCU->GPIOOUT[4] = 0x0000; - SCU->GPIOIN[4] = 0x00; - } - else - { - SCU->GPIOOUT[4] &= ~(0x3<<(GPIO_ANAChannel-1)); - SCU->GPIOIN[4] &= ~GPIO_ANAChannel; - } - SCU->GPIOANA |= GPIO_ANAChannel; - - } - else - { - SCU->GPIOANA &= ~GPIO_ANAChannel; - } -} - -/******************************************************************************* -* Function Name : GPIO_GetGPIONumber -* Description : searche the GPIO number. -* Input : GPIOx: where x can be (0..9) to select the GPIO peripheral. -* Output : None -* Return : GPIO number -*******************************************************************************/ -u8 GPIO_GetGPIONumber(GPIO_TypeDef* GPIOx) -{ - - if(GPIOx == GPIO1) - { - return 1; - } - if(GPIOx == GPIO2) - { - return 2; - } - if(GPIOx == GPIO3) - { - return 3; - } - if(GPIOx == GPIO4) - { - return 4; - } - if(GPIOx == GPIO5) - { - return 5; - } - if(GPIOx == GPIO6) - { - return 6; - } - if(GPIOx == GPIO7) - { - return 7; - } - if(GPIOx == GPIO8) - { - return 8; - } - if(GPIOx == GPIO9) - { - return 9; - } - return 0; -} -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM9_STR91X_IAR/Library/source/91x_it.c b/Demo/ARM9_STR91X_IAR/Library/source/91x_it.c deleted file mode 100644 index cb09f2b93..000000000 --- a/Demo/ARM9_STR91X_IAR/Library/source/91x_it.c +++ /dev/null @@ -1,374 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 91x_it.c -* Author : MCD Application Team -* Date First Issued : 03/31/2006 : Beta Version V0.1 -* Description : Main Interrupt Service Routines. -******************************************************************************** -* This file can be used to describe all the exceptions subroutines -* that may occur within user application. -* When an interrupt happens, the software will branch automatically -* to the corresponding routine according to the interrupt vector -* loaded in the PC register. -* The following routines are all empty, user can write code for -* exceptions handlers and peripherals IRQ interrupts. -******************************************************************************** -* History: -* 03/31/2006 : Beta Version V0.1 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH -* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS -* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT -* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT -* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION -* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#include "91x_it.h" - -/******************************************************************************* -* Function Name : Undefined_Handler -* Description : This function Undefined instruction exception. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void Undefined_Handler(void) -{ - // NOT USED. -} -/******************************************************************************* -* Function Name : SWI_Handler -* Description : This function handles SW exception. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void SWI_Handler(void) -{ - // NOT USED. -} -/******************************************************************************* -* Function Name : Prefetch_Handler -* Description : This function handles preftetch abort exception. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void Prefetch_Handler(void) -{ - // NOT USED. -} -/******************************************************************************* -* Function Name : Abort_Handler -* Description : This function handles data abort exception. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void Abort_Handler(void) -{ - // NOT USED. -} -/******************************************************************************* -* Function Name : FIQ_Handler -* Description : This function handles FIQ exception. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void FIQ_Handler(void) -{ - // NOT USED. -} -/******************************************************************************* -* Function Name : SW_IRQHandler -* Description : This function handles the SW interrupt request -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void SW_IRQHandler(void) -{ -} -/******************************************************************************* -* Function Name : ARMRX_IRQHandler -* Description : This function handles the ARMRX interrupt request -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void ARMRX_IRQHandler(void) -{ -} -/******************************************************************************* -* Function Name : ARMTX_IRQHandler -* Description : This function handles the ARMTX interrupt request -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void ARMTX_IRQHandler(void) -{ -} -/******************************************************************************* -* Function Name : TIM0_IRQHandler -* Description : This function handles the TIM0 interrupt request -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void TIM0_IRQHandler(void) -{ -} -/******************************************************************************* -* Function Name : TIM1_IRQHandler -* Description : This function handles the TIM1 interrupt request -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void TIM1_IRQHandler(void) -{ -} -/******************************************************************************* -* Function Name : TIM2_IRQHandler -* Description : This function handles the TIM2 interrupt request -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void TIM2_IRQHandler(void) -{ -} -/******************************************************************************* -* Function Name : TIM3_IRQHandler -* Description : This function handles the TIM3 interrupt request -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void TIM3_IRQHandler(void) -{ -} -/******************************************************************************* -* Function Name : USBHP_IRQHandler -* Description : This function handles the USBHP interrupt request -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void USBHP_IRQHandler(void) -{ -} -/******************************************************************************* -* Function Name : USBLP_IRQHandler -* Description : This function handles the USBLP interrupt request -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void USBLP_IRQHandler(void) -{ -} -/******************************************************************************* -* Function Name : SCU_IRQHandler -* Description : This function handles the SCU interrupt request -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void SCU_IRQHandler(void) -{ -} -/******************************************************************************* -* Function Name : DMA_IRQHandler -* Description : This function handles the DMA interrupt request -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void DMA_IRQHandler(void) -{ -} - -/******************************************************************************* -* Function Name : CAN_IRQHandler -* Description : This function handles the CAN interrupt request -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void CAN_IRQHandler(void) -{ -} -/******************************************************************************* -* Function Name : MC_IRQHandler -* Description : This function handles the MC interrupt request -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void MC_IRQHandler(void) -{ -} -/******************************************************************************* -* Function Name : ADC_IRQHandler -* Description : This function handles the ADC interrupt request -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void ADC_IRQHandler(void) -{ -} -/******************************************************************************* -* Function Name : UART0_IRQHandler -* Description : This function handles the UART0 interrupt request -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void UART0_IRQHandler(void) -{ -} -/******************************************************************************* -* Function Name : UART2_IRQHandler -* Description : This function handles the UART2 interrupt request -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void UART2_IRQHandler(void) -{ -} -/******************************************************************************* -* Function Name : I2C0_IRQHandler -* Description : This function handles the I2C0 interrupt request -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void I2C0_IRQHandler(void) -{ -} -/******************************************************************************* -* Function Name : I2C1_IRQHandler -* Description : This function handles the I2C1 interrupt request -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void I2C1_IRQHandler(void) -{ -} -/******************************************************************************* -* Function Name : SSP0_IRQHandler -* Description : This function handles the SSP0 interrupt request -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void SSP0_IRQHandler(void) -{ -} -/******************************************************************************* -* Function Name : SSP1_IRQHandler -* Description : This function handles the SSP1 interrupt request -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void SSP1_IRQHandler(void) -{ -} -/******************************************************************************* -* Function Name : LVD_IRQHandler -* Description : This function handles the LVD interrupt request -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void LVD_IRQHandler(void) -{ -} -/******************************************************************************* -* Function Name : RTC_IRQHandler -* Description : This function handles the RTC interrupt request -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void RTC_IRQHandler(void) -{ -} -/******************************************************************************* -* Function Name : WIU_IRQHandler -* Description : This function handles the WIU interrupt request -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void WIU_IRQHandler(void) -{ -} -/******************************************************************************* -* Function Name : EXTIT0_IRQHandler -* Description : This function handles the EXTIT0 interrupt request -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void EXTIT0_IRQHandler(void) -{ -} -/******************************************************************************* -* Function Name : EXTIT1_IRQHandler -* Description : This function handles the EXTIT1 interrupt request -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void EXTIT1_IRQHandler(void) -{ -} -/******************************************************************************* -* Function Name : EXTIT2_IRQHandler -* Description : This function handles the EXTIT2 interrupt request -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void EXTIT2_IRQHandler(void) -{ -} -/******************************************************************************* -* Function Name : EXTIT3_IRQHandler -* Description : This function handles the EXTIT3 interrupt request -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void EXTIT3_IRQHandler(void) -{ -} -/******************************************************************************* -* Function Name : USBWU_IRQHandler -* Description : This function handles the USBWU interrupt request -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void USBWU_IRQHandler(void) -{ -} -/******************************************************************************* -* Function Name : PFQBC_IRQHandler -* Description : This function handles the PFQBC interrupt request -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void PFQBC_IRQHandler(void) -{ -} - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM9_STR91X_IAR/Library/source/91x_lib.c b/Demo/ARM9_STR91X_IAR/Library/source/91x_lib.c deleted file mode 100644 index c0eadbb94..000000000 --- a/Demo/ARM9_STR91X_IAR/Library/source/91x_lib.c +++ /dev/null @@ -1,281 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 91x_lib.c -* Author : MCD Application Team -* Date First Issued : 05/18/2006 : Version 1.0 -* Description : This file provides all peripherals pointers - : initialization. -******************************************************************************** -* History: -* 05/24/2006 : Version 1.1 -* 05/18/2006 : Version 1.0 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH -* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS -* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT -* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT -* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION -* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#define EXT - -/* Standard include ----------------------------------------------------------*/ -#include "91x_map.h" - -/* Include of other module interface headers ---------------------------------*/ -/* Local includes ------------------------------------------------------------*/ -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Interface functions -------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -#ifdef DEBUG - -/******************************************************************************* -* Function Name : debug -* Description : this function initialize peripherals pointers -* Input : no one -* Output : no one -* Return : no one -*******************************************************************************/ -void debug(void) -{ - - -/************************* DMA *************************/ - -#ifdef _DMA - DMA = (DMA_TypeDef *)DMA_BASE; -#endif /* _DMA */ - -/************************* DMA *************************/ - - -#ifdef _DMA_Channel0 - DMA_Channel0= (DMA_Channel_TypeDef *)DMA_Channel0_BASE; -#endif /* _DMA_Channel0 */ - -#ifdef _DMA_Channel1 - DMA_Channel1= (DMA_Channel_TypeDef *)DMA_Channel1_BASE; -#endif /* _DMA_Channel1 */ - -#ifdef _DMA_Channel2 - DMA_Channel2 = (DMA_Channel_TypeDef *)DMA_Channel2_BASE; -#endif /* _DMA_Channel2 */ - -#ifdef _DMA_Channel3 - DMA_Channel3 = (DMA_Channel_TypeDef *)DMA_Channel3_BASE; -#endif /* _DMA_Channel3 */ - -#ifdef _DMA_Channel4 - DMA_Channel4 = (DMA_Channel_TypeDef *)DMA_Channel4_BASE; -#endif /* _DMA_Channel4 */ - -#ifdef _DMA_Channel5 - DMA_Channel5= (DMA_Channel_TypeDef *)DMA_Channel5_BASE; -#endif /* _DMA_Channel5*/ - - -#ifdef _DMA_Channel6 - DMA_Channel6 = (DMA_Channel_TypeDef *)DMA_Channel6_BASE; -#endif /* _DMA_Channel6 */ - -#ifdef _DMA_Channel7 - DMA_Channel7 = (DMA_Channel_TypeDef *)DMA_Channel7_BASE; -#endif /* _DMA_Channel7 */ - - - - /************************* EMI *************************/ - -#ifdef _EMI_Bank0 - EMI_Bank0= (EMI_Bank_TypeDef *)EMI_Bank0_BASE; -#endif /* _EMI_Bank0 */ - -#ifdef _EMI_Bank1 - EMI_Bank1= (EMI_Bank_TypeDef *)EMI_Bank1_BASE; -#endif /* _EMI_Bank1 */ - -#ifdef _EMI_Bank2 - EMI_Bank2 = (EMI_Bank_TypeDef *)EMI_Bank2_BASE; -#endif /* _EMI_Bank2 */ - -#ifdef _EMI_Bank3 - EMI_Bank3 = (EMI_Bank_TypeDef *)EMI_Bank3_BASE; - #endif /* _EMI_Bank3 */ - - - -/************************* AHBAPB *************************/ - -#ifdef _AHBAPB0 - AHBAPB0 = (AHBAPB_TypeDef *)AHBAPB0_BASE; -#endif /* _AHBAPB0 */ - -#ifdef _AHBAPB1 - AHBAPB1 = (AHBAPB_TypeDef *)AHBAPB1_BASE; -#endif /*_AHBAPB1 */ - - - -/************************* FMI *************************/ - -#ifdef _FMI - FMI = (FMI_TypeDef *)FMI_BASE; -#endif /* _FMI */ - -/************************* VIC *************************/ - -#ifdef _VIC0 - VIC0 = (VIC_TypeDef *)VIC0_BASE; -#endif /* _VIC0 */ - -#ifdef _VIC1 - VIC1 = (VIC_TypeDef *)VIC1_BASE; -#endif /* _VIC1 */ - -/************************* WIU *************************/ - -#ifdef _WIU - WIU = (WIU_TypeDef *)WIU_BASE; -#endif /* _WIU */ - -/************************* TIM *************************/ - -#ifdef _TIM0 - TIM0 = (TIM_TypeDef *)TIM0_BASE; -#endif /* _TIM0 */ - -#ifdef _TIM1 - TIM1 = (TIM_TypeDef *)TIM1_BASE; -#endif /* _TIM1 */ - -#ifdef _TIM2 - TIM2 = (TIM_TypeDef *)TIM2_BASE; -#endif /* _TIM2 */ - -#ifdef _TIM3 - TIM3 = (TIM_TypeDef *)TIM3_BASE; -#endif /* _TIM3 */ - -/************************* GPIO ************************/ - -#ifdef _GPIO0 - GPIO0 = (GPIO_TypeDef *)GPIO0_BASE; -#endif /* _GPIO0 */ - -#ifdef _GPIO1 - GPIO1 = (GPIO_TypeDef *)GPIO1_BASE; -#endif /* _GPIO1 */ - -#ifdef _GPIO2 - GPIO2 = (GPIO_TypeDef *)GPIO2_BASE; -#endif /* _GPIO2 */ - -#ifdef _GPIO3 - GPIO3 = (GPIO_TypeDef *)GPIO3_BASE; -#endif /* _GPIO3 */ - -#ifdef _GPIO4 - GPIO4 = (GPIO_TypeDef *)GPIO4_BASE; -#endif /* _GPIO4 */ - -#ifdef _GPIO5 - GPIO5 = (GPIO_TypeDef *)GPIO5_BASE; -#endif /* _GPIO5 */ - -#ifdef _GPIO6 - GPIO6 = (GPIO_TypeDef *)GPIO6_BASE; -#endif /* _GPIO6 */ - -#ifdef _GPIO7 - GPIO7 = (GPIO_TypeDef *)GPIO7_BASE; -#endif /* _GPIO7 */ - -#ifdef _GPIO8 - GPIO8 = (GPIO_TypeDef *)GPIO8_BASE; -#endif /* _GPIO8 */ - -#ifdef _GPIO9 - GPIO9 = (GPIO_TypeDef *)GPIO9_BASE; -#endif /* _GPIO9 */ - -/************************* RTC *************************/ - -#ifdef _RTC - RTC = (RTC_TypeDef *)RTC_BASE; -#endif /* _RTC */ - -/************************* PRCCU ***********************/ - -#ifdef _SCU - SCU = (SCU_TypeDef *)SCU_BASE; -#endif /* _PRCCU */ - -/************************** MC *************************/ - -#ifdef _MC - MC = (MC_TypeDef *)MC_BASE; -#endif /* _MC */ - -/************************* UART ************************/ - -#ifdef _UART0 - UART0 = (UART_TypeDef *)UART0_BASE; -#endif /* _UART0 */ - -#ifdef _UART1 - UART1 = (UART_TypeDef *)UART1_BASE; -#endif /* _UART1 */ - -#ifdef _UART2 - UART2 = (UART_TypeDef *)UART2_BASE; -#endif /* _UART2 */ - -/************************* SSP *************************/ - -#ifdef _SSP0 - SSP0 = (SSP_TypeDef *)SSP0_BASE; -#endif /* _SSP0 */ - -#ifdef _SSP1 - SSP1 = (SSP_TypeDef *)SSP1_BASE; -#endif /* _SSP1 */ - -/************************* CAN *************************/ - -#ifdef _CAN - CAN = (CAN_TypeDef *)CAN_BASE; -#endif /* _CAN */ - -/************************* ADC *************************/ - -#ifdef _ADC - ADC = (ADC_TypeDef *)ADC_BASE; -#endif /* _ADC */ - -/************************* WDG *************************/ - -#ifdef _WDG - WDG = (WDG_TypeDef *)WDG_BASE; -#endif /* _WDG */ - -/************************* I2C *************************/ - -#ifdef _I2C0 - I2C0 = (I2C_TypeDef *)I2C0_BASE; -#endif /* _I2C0 */ - -#ifdef _I2C1 - I2C1 = (I2C_TypeDef *)I2C1_BASE; -#endif /* _I2C1 */ -/********************** ENET **************************/ -#ifdef _ENET - ENET_MAC = (ENET_MAC_TypeDef *)ENET_MAC_BASE; - ENET_DMA = (ENET_DMA_TypeDef *)ENET_DMA_BASE; -#endif /* _ENET */ -} -#endif /* DEBUG */ - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM9_STR91X_IAR/Library/source/91x_scu.c b/Demo/ARM9_STR91X_IAR/Library/source/91x_scu.c deleted file mode 100644 index 21116b2a3..000000000 --- a/Demo/ARM9_STR91X_IAR/Library/source/91x_scu.c +++ /dev/null @@ -1,661 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 91x_scu.c -* Author : MCD Application Team -* Date First Issued : 05/18/2006 : Version 1.0 -* Description : This file provides the SCU library software functions -******************************************************************************** -* History: -* 05/24/2006 : Version 1.1 -* 05/18/2006 : Version 1.0 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH -* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS -* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT -* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT -* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION -* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -#include "91x_scu.h" - -/* Include of other module interface headers ---------------------------------*/ -/* Local includes ------------------------------------------------------------*/ -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define SCU_PLLEN 0x80000 -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Interface functions -------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/******************************************************************************* -* Function Name : SCU_MCLKSourceConfig -* Description : Configures the MCLK source clock -* Input : MCLK_Source = SCU_MCLK_OSC, SCU_MCLK_PLL or SCU_MCLK_RTC -* Output : None -* Return : ErrorStatus: SUCCESS or ERROR -* Note : this function returns ERROR if trying to select the PLL as -* clock source while the PLL is disabled or not locked. -*******************************************************************************/ -ErrorStatus SCU_MCLKSourceConfig(u32 MCLK_Source) -{ - u32 CLKCNTR_Value; - - CLKCNTR_Value = SCU->CLKCNTR; /*get CLKCNTR register value*/ - CLKCNTR_Value &=~0x3; /*clear field MCLKSEL*/ - if (MCLK_Source == SCU_MCLK_PLL) /*PLL selected as clock source*/ - { - /*check if PLL enabled & locked*/ - if (!((SCU->PLLCONF&SCU_PLLEN)&&(SCU->SYSSTATUS&SCU_FLAG_LOCK))) - return ERROR; - } - else CLKCNTR_Value |=MCLK_Source; /*OSC or RTC selected as clock source*/ - SCU->CLKCNTR = CLKCNTR_Value; /*Update CLKCNTR register value*/ - return SUCCESS; -} - -/******************************************************************************* -* Function Name : SCU_PLLFactorsConfig -* Description : Sets the PLL factors -* Input : PLLN, PLLM and PLLP -* Output : None -* Return : ErrorStatus: ERROR or SUCCESS -* Notes : -The PLL factors must respect the PLL specification requirements -* -The function returns ERROR if trying to change PLL -* factors while PLL is selected as Main Clock source (MCLK) -* -This function disables the PLL, to enable the PLL use -* function" SCU_PLLCmd(ENABLE)" after setting the PLL factors -******************************************************************************/ -ErrorStatus SCU_PLLFactorsConfig(u8 PLLN, u8 PLLM, u8 PLLP) -{ - if (SCU_PLLCmd(DISABLE)==SUCCESS) /*Disable PLL*/ - { - SCU->PLLCONF =0; /*clear PLLCONF register*/ - SCU->PLLCONF |=(PLLN<<8); /*update PLLN field*/ - SCU->PLLCONF |=PLLM; /*update PLLM field*/ - SCU->PLLCONF |=PLLP<<16; /*update PLLP field*/ - return SUCCESS; - } - return ERROR; -} - -/******************************************************************************* -* Function Name : SCU_PLLCmd -* Description : Enable or Disable the PLL -* Input : NewState = ENABLE or DISABLE -* Output : None -* Return : ErrorStatus: SUCCESS or ERROR -* Note : -The function returns ERROR if: -* *trying to disable the PLL while it is selected as the MCLK -* *trying to enable the PLL while it is already enabled and -* locked -*******************************************************************************/ -ErrorStatus SCU_PLLCmd(FunctionalState NewState) -{ - vu32 i; - if (NewState==ENABLE) - { - if (!((SCU->PLLCONF&SCU_PLLEN)&&(SCU->SYSSTATUS&SCU_FLAG_LOCK))) - { - SCU->SYSSTATUS|=SCU_FLAG_LOCK; /*clear LOCK bit*/ - SCU->PLLCONF |=SCU_PLLEN; /*PLL Enable*/ - while(!SCU->SYSSTATUS&SCU_FLAG_LOCK); /*Wait PLL to lock*/ - return SUCCESS; - } - else return ERROR; - } - else /*NewState = DISABLE*/ - { - if(SCU->CLKCNTR&0x3) /*check if PLL not sys CLK*/ - { - for(i=10;i>0;i--); /*delay before PLL disabling*/ - SCU->PLLCONF &=~SCU_PLLEN; /*PLL Disable*/ - return SUCCESS; - } - else return ERROR; - } -} - -/******************************************************************************* -* Function Name : SCU_RCLKDivisorConfig -* Description : Sets the RCLK divisor value -* Input : RCLK_Divisor -* Output : None -* Return : None -*******************************************************************************/ -void SCU_RCLKDivisorConfig(u32 RCLK_Divisor) -{ - SCU->CLKCNTR &=SCU_RCLK_Div1; /*clear RCLKDIV[2:0] field*/ - if (RCLK_Divisor!=SCU_RCLK_Div1) - SCU->CLKCNTR |= RCLK_Divisor; /*update field with RCLK divisor*/ -} - -/******************************************************************************* -* Function Name : SCU_HCLKDivisorConfig -* Description : Sets the HCLK divisor value -* Input : HCLK_Divisor -* Output : None -* Return : None -*******************************************************************************/ -void SCU_HCLKDivisorConfig(u32 HCLK_Divisor) -{ - SCU->CLKCNTR &=SCU_HCLK_Div1; /*clear AHBDIV[1:0] field*/ - if (HCLK_Divisor!=SCU_HCLK_Div1) - SCU->CLKCNTR |= HCLK_Divisor; /*update field with HCLK divisor*/ -} - -/******************************************************************************* -* Function Name : SCU_PCLKDivisorConfig -* Description : Sets the PCLK divisor value -* Input : PCLK_Divisor -* Output : None -* Return : None -*******************************************************************************/ -void SCU_PCLKDivisorConfig(u32 PCLK_Divisor) -{ - SCU->CLKCNTR &=SCU_PCLK_Div1; /*clear APBDIV[1:0] field*/ - if (PCLK_Divisor!=SCU_PCLK_Div1) - SCU->CLKCNTR |= PCLK_Divisor; /*update field with PCLK Divisor*/ -} - -/******************************************************************************* -* Function Name : SCU_APBPeriphClockConfig -* Description : Enable the clock for an APB peripheral -* Input : -APBPerip : APB peripherals(__RTC, __ADC ,...) -* -NewState : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void SCU_APBPeriphClockConfig(u32 APBPeriph, FunctionalState NewState) -{ - if (NewState==ENABLE) /*Enable clock for APB peripheral*/ - SCU->PCGR1 |=APBPeriph; - else - SCU->PCGR1 &=~APBPeriph; /*Disable clock for APB peripheral*/ -} - -/******************************************************************************* -* Function Name : SCU_AHBPeriphClockConfig -* Description : Enable the clock for an AHB peripheral -* Input : -AHBPerip: AHB peripherals(__USB, __DMA,...) -* -NewState : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void SCU_AHBPeriphClockConfig(u32 AHBPeriph, FunctionalState NewState) -{ - if (NewState==ENABLE) /*Enable clock for AHB peripheral*/ - SCU->PCGRO |=AHBPeriph; - else - SCU->PCGRO &=~AHBPeriph; /*Disable clock for AHB peripheral*/ -} - -/******************************************************************************* -* Function Name : SCU_APBPeriphReset -* Description : Assert or deassert Reset on APB peripheral -* Input : -APBPeriph: APB peripherals(__RTC, __ADC,...) - -NewState : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void SCU_APBPeriphReset(u32 APBPeriph, FunctionalState NewState) -{ - if (NewState==DISABLE) /*APB peripheral not held in Reset*/ - SCU->PRR1 |=APBPeriph; - else - SCU->PRR1 &=~APBPeriph; /*APB peripheral held in Reset*/ -} - -/******************************************************************************* -* Function Name : SCU_AHBPeriphReset -* Description : Assert or deassert Reset on AHB peripheral -* Input : -AHBPeriph: AHB peripherals(__USB, __DMA,...) - -NewState : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void SCU_AHBPeriphReset(u32 AHBPeriph, FunctionalState NewState) -{ - if (NewState==DISABLE) - SCU->PRR0 |=AHBPeriph; /*AHB peripheral not held in Reset*/ - else - SCU->PRR0 &=~AHBPeriph; /*AHB peripheral held in Reset*/ -} - -/******************************************************************************* -* Function Name : SCU_APBPeriphIdleConfig -* Description : Enable or Disable Periph Clock during Idle mode -* Input : -APBPeriph: APB peripherals(__RTC, __ADC,...) - -NewState : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void SCU_APBPeriphIdleConfig(u32 APBPeriph, FunctionalState NewState) -{ - if (NewState==ENABLE) - SCU->MGR1 |=APBPeriph; /*APB peripheral clock enabled during Idle mode*/ - else - SCU->MGR1 &=~APBPeriph; /*APB peripheral clock disabled during Idle mode*/ -} - -/******************************************************************************* -* Function Name : SCU_AHBPeriphIdleConfig -* Description : Enable or Disable Periph Clock during Idle mode -* Input : -AHBPeriph: AHB peripherals(__USB, __DMA,...) - -NewState : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void SCU_AHBPeriphIdleConfig(u32 AHBPeriph, FunctionalState NewState) -{ - if (NewState==ENABLE) - SCU->MGR0 |=AHBPeriph; /*AHB peripheral clock enabled during Idle mode*/ - else - SCU->MGR0 &=~AHBPeriph; /*AHB peripheral clock disabled during Idle mode*/ -} - -/******************************************************************************* -* Function Name : SCU_APBPeriphDebugConfig -* Description : Enable or Disable Periph Clock during ARM debug state -* Input : -APBPeriph: APB peripherals(__RTC, __ADC,...) - -NewState : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void SCU_APBPeriphDebugConfig(u32 APBPeriph, FunctionalState NewState) -{ - if (NewState==ENABLE) - SCU->PECGR1 |=APBPeriph; /*APB peripheral clock enabled during ARM debug state*/ - else - SCU->PECGR1 &=~APBPeriph; /*APB peripheral clock disabled during ARM debug state*/ -} - -/******************************************************************************* -* Function Name : SCU_AHBPeriphDebugConfig -* Description : Enable or Disable Periph Clock during ARM debug state -* Input : -AHBPeriph: AHB peripherals(__USB, __DMA,...) - -NewState : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void SCU_AHBPeriphDebugConfig(u32 AHBPeriph, FunctionalState NewState) -{ - if (NewState==ENABLE) - SCU->PECGR0 |=AHBPeriph; /*AHB peripheral clock enabled during ARM debug state*/ - else - SCU->PECGR0 &=~AHBPeriph; /*AHB peripheral clock disabled during ARM debug state*/ -} -/******************************************************************************* -* Function Name : SCU_BRCLKDivisorConfig -* Description : Sets the BRCLK divisor value -* Input : BRCLK_Divisor -* Output : None -* Return : None -*******************************************************************************/ -void SCU_BRCLKDivisorConfig(u32 BRCLK_Divisor) -{ - SCU->CLKCNTR &=SCU_BRCLK_Div1; /*Clear BRSEL bit*/ - if (BRCLK_Divisor!=SCU_BRCLK_Div1) - SCU->CLKCNTR |= SCU_BRCLK_Div2; /*set bit BRSEL*/ -} - -/******************************************************************************* -* Function Name : SCU_TIMCLKSourceConfig -* Description : Sets the TIMx clock source -* Input : - TIMx : SCU_TIM01 or SCU_TIM23 -* - TIMCLK_Source = SCU_TIMCLK_EXT or SCU_TIMCLK_INT -* Output : None -* Return : None -*******************************************************************************/ -void SCU_TIMCLKSourceConfig(u8 TIMx, u32 TIMCLK_Source) -{ - if (TIMx== SCU_TIM01) /*TIM01 clock source configuration*/ - { - SCU->CLKCNTR &=0xFFFFDFFF; - if (TIMCLK_Source == SCU_TIMCLK_EXT) - SCU->CLKCNTR |=0x2000; - } - else - { - SCU->CLKCNTR &=0xFFFFBFFF; /*TIM23 clock source configuration*/ - if (TIMCLK_Source == SCU_TIMCLK_EXT) - SCU->CLKCNTR |=0x4000; - } -} - -/******************************************************************************* -* Function Name : SCU_TIMPresConfig -* Description : Sets the TIMx Prescaler Value -* Input : - TIMx : SCU_TIM01 or SCU_TIM23 -* - Prescaler (16 bit value) -* Output : None -* Return : None -*******************************************************************************/ -void SCU_TIMPresConfig(u8 TIMx, u16 Prescaler) -{ - if (TIMx==SCU_TIM01) /*TIM01 Prescaler configuration*/ - SCU->SCR1 = Prescaler&0xFFFF; - else - SCU->SCR2 = Prescaler&0xFFFF; /*TIM23 Prescaler configuration*/ -} - -/******************************************************************************* -* Function Name : SCU_USBCLKConfig -* Description : Configures the clock source for the 48MHz USBCLK -* Input : USBCLK_Source: SCU_USBCLK_MCLK,SCU_USBCLK_MCLK2 or SCU_USBCLK_EXT -* Output : None -* Return : None -*******************************************************************************/ -void SCU_USBCLKConfig(u32 USBCLK_Source) -{ - SCU->CLKCNTR &=SCU_USBCLK_MCLK; /*clear USBSEL[1:0] field*/ - if (USBCLK_Source!=SCU_USBCLK_MCLK) - SCU->CLKCNTR |= USBCLK_Source; /*update field with USBCLK_Source*/ -} - -/******************************************************************************* -* Function Name : SCU_PHYCLKConfig -* Description : Enable or Disable PHY clock output -* Input : NewState : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void SCU_PHYCLKConfig(FunctionalState NewState) -{ - if (NewState==ENABLE) - SCU->CLKCNTR |= 0x1000; /*enable MIIPHY clock*/ - else - SCU->CLKCNTR &=~0x1000; /*disable MIIPHY clock*/ -} - -/******************************************************************************* -* Function Name : SCU_FMICLKDivisorConfig -* Description : Set the FMI clock divisor -* Input : FMICLK_Divisor: SCU_FMICLK_Div1 or SCU_FMICLK_DIV2 -* Output : None -* Return : None -*******************************************************************************/ -void SCU_FMICLKDivisorConfig(u32 FMICLK_Divisor) -{ - SCU->CLKCNTR &=SCU_FMICLK_Div1; /*FMICLK = RCLK*/ - if (FMICLK_Divisor!=SCU_FMICLK_Div1) - SCU->CLKCNTR |=SCU_FMICLK_Div2; /*FMICLK = RCLK/2 */ -} - -/******************************************************************************* -* Function Name : SCU_EMIBCLKDivisorConfig -* Description : Set the EMI Bus clock divisor: EMIBCLK = HCLK or HCLK/2 -* Input : SCU_EMICLK: SCU_EMIBCLK_Div1 , SCU_EMIBCLK_Div2 -* Output : None -* Return : None -*******************************************************************************/ -void SCU_EMIBCLKDivisorConfig(u32 SCU_EMIBCLK) -{ - SCU->CLKCNTR &=SCU_EMIBCLK_Div1; /*EMIBCLK = HCLK */ - if (SCU_EMIBCLK!=SCU_EMIBCLK_Div1) - SCU->CLKCNTR |= SCU_EMIBCLK_Div2; /*EMIBCLK = HCLK/2 */ -} - -/******************************************************************************* -* Function Name : SCU_EMIModeConfig -* Description : Configure the EMI as Multiplexed or Demultiplexed -* Input : SCU_EMIMODE : SCU_EMI_MUX or SCU_EMI_DEMUX -* Output : None -* Return : None -*******************************************************************************/ -void SCU_EMIModeConfig(u32 SCU_EMIMODE) -{ - SCU->SCR0 &=SCU_EMI_MUX; /*EMI mode = Multiplexed*/ - if (SCU_EMIMODE!=SCU_EMI_MUX) - SCU->SCR0 |= SCU_EMI_DEMUX; /*EMI mode = Demultiplexed*/ -} - -/******************************************************************************* -* Function Name : SCU_EMIALEConfig -* Description : Configure the ALE signal (length & polarity) -* Input : -SCU_EMIALE_LEN : SCU_EMIALE_LEN1 or SCU_EMIALE_LEN2 -* -SCU_EMIALE_POL : SCU_EMIALE_POLLow or SCU_EMI_POLHigh -* Output : None -* Return : None -*******************************************************************************/ -void SCU_EMIALEConfig(u32 SCU_EMIALE_LEN, u32 SCU_EMIALE_POL) -{ - /*Configure EMI ALE Length*/ - SCU->SCR0 &=SCU_EMIALE_LEN1; - if (SCU_EMIALE_LEN!=SCU_EMIALE_LEN1) - SCU->SCR0 |= SCU_EMIALE_LEN2; - - /*Configure EMI ALE POL*/ - SCU->SCR0 &=SCU_EMIALE_POLLow; - if (SCU_EMIALE_POL!=SCU_EMIALE_POLLow) - SCU->SCR0 |= SCU_EMIALE_POLHigh; -} - -/******************************************************************************* -* Function Name : SCU_ITConfig -* Description : ENBALE or DISABLE an SCU interrupt -* Input : -SCU_IT: interrupt mask -* -NewState: ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void SCU_ITConfig(u32 SCU_IT, FunctionalState NewState) -{ - if (NewState==ENABLE) - SCU->ITCMSK&=~SCU_IT; /*IT enable */ - else - SCU->ITCMSK|=SCU_IT; /*IT disable( mask)*/ -} - -/******************************************************************************* -* Function Name : SCU_GetFlagStatus -* Description : Returns flag status -* Input : SCU_Flag -* Output : NONE -* Return : SET or RESET -*******************************************************************************/ -FlagStatus SCU_GetFlagStatus(u32 SCU_Flag) -{ - if (SCU->SYSSTATUS&SCU_Flag) - return SET; - else return RESET; -} - -/******************************************************************************* -* Function Name : SCU_ClearFlag -* Description : Clears a SYSTATUS Flag -* Input : SCU_Flag -* Output : None -* Return : None -*******************************************************************************/ -void SCU_ClearFlag(u32 SCU_Flag) -{ - SCU->SYSSTATUS = SCU_Flag; -} -/******************************************************************************* -* Function Name : SCU_GetPLLfreqValue -* Description : Gets the current PLL frequency -* Input : None -* Output : None -* Return : PLL frequency (KHz) -*******************************************************************************/ -u32 SCU_GetPLLFreqValue(void) -{ - u8 PLL_M; - u8 PLL_N; - u8 PLL_P; - - PLL_M = SCU->PLLCONF&0xFF; - PLL_N = (SCU->PLLCONF&0xFF00)>>8; - PLL_P = (SCU->PLLCONF&0x70000)>>16; - - if ((PLL_M>0)&&(PLL_N>0)) - return (u32)(((_Main_Crystal*2)*PLL_N)/(PLL_M<CLKCNTR&0x3) == 0x2) return (u32)(_Main_Crystal); - if ((SCU->CLKCNTR&0x3) == 0x1) return (u32)(32); - else return (SCU_GetPLLFreqValue()); -} - -/******************************************************************************* -* Function Name : SCU_GetRCLKFreqValue -* Description : Gets the current RCLK frequency -* Input : None -* Output : None -* Return : RCLK frequency (KHz) -*******************************************************************************/ -u32 SCU_GetRCLKFreqValue(void) -{ - u8 RCLK_Div; - RCLK_Div = (SCU->CLKCNTR&0x1C)>>2; - if (RCLK_Div==0x5) RCLK_Div=10; - return (u32)(SCU_GetMCLKFreqValue() >>RCLK_Div); -} - -/******************************************************************************* -* Function Name : SCU_GetHCLKFreqValue -* Description : Gets the current PCLK frequency -* Input : None -* Output : None -* Return : HCLK frequency (KHz) -*******************************************************************************/ -u32 SCU_GetHCLKFreqValue(void) -{ - u8 HCLK_Div; - HCLK_Div = (SCU->CLKCNTR&0x60)>>5; - return (u32)(SCU_GetRCLKFreqValue() >>HCLK_Div); -} - -/******************************************************************************* -* Function Name : SCU_GetPCLKFreqValue -* Description : Gets the current HCLK frequency -* Input : None -* Output : None -* Return : PCLK frequency (KHz) -*******************************************************************************/ -u32 SCU_GetPCLKFreqValue(void) -{ - u8 PCLK_Div; - PCLK_Div = (SCU->CLKCNTR&0x180)>>7; - return (u32)(SCU_GetRCLKFreqValue() >>PCLK_Div); -} - -/******************************************************************************* -* Function Name : SCU_WakeUpLineConfig -* Description : Configures an External interrupt as WakeUp line -* Input : EXTint : 0 -> 31 -* Output : None -* Return : None -*******************************************************************************/ -void SCU_WakeUpLineConfig(u8 EXTint) -{ - if (EXTint < 8) - { - SCU->WKUPSEL&=~0x7; - SCU->WKUPSEL|=EXTint; - } - else if (EXTint<16) - { - SCU->WKUPSEL&=~0x38; - SCU->WKUPSEL|=(EXTint-8)<<3; - } - else if (EXTint<24) - { - SCU->WKUPSEL&=~0x1C0; - SCU->WKUPSEL|=(EXTint-16)<<6; - } - else - { - SCU->WKUPSEL&=~0xE00; - SCU->WKUPSEL|=(EXTint-24)<<9; - } -} - -/******************************************************************************* -* Function Name : SCU_SpecIntRunModeConfig -* Description : Enables or Disables the Special Run mode -* Input : newstate = ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void SCU_SpecIntRunModeConfig(FunctionalState NewState) -{ - if (NewState == ENABLE) - SCU->PWRMNG |=0x8; - else - SCU->PWRMNG &=~0x8; -} -/******************************************************************************* -* Function Name : SCU_EnterIdleMode -* Description : Enters in Idle mode -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void SCU_EnterIdleMode(void) -{ - SCU->PWRMNG |=0x1; -} -/******************************************************************************* -* Function Name : SCU_EnterSleepMode -* Description : Enters in Sleep mode -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void SCU_EnterSleepMode(void) -{ - SCU->PWRMNG |=0x2; -} - -/******************************************************************************* -* Function Name : SCU_UARTIrDAConfig -* Description : Enable or Disable the Irda mode for UARTx -* Input : - UARTx :x=0,1 or 2 -* - UART_IrDA_Mode : SCU_UARTMode_IrDA or SCU_UARTMode_UART -* Output : None -* Return : None -*******************************************************************************/ -void SCU_UARTIrDASelect(UART_TypeDef * UARTx, u8 UART_IrDA_Mode) -{ - if (UART_IrDA_Mode == SCU_UARTMode_IrDA) - { - if (UARTx== UART0) SCU->SCR0 |=0x400; - else if (UARTx==UART1) SCU->SCR0 |=0x800; - else SCU->SCR0 |=0x1000; - } - else - { - if (UARTx== UART0) SCU->SCR0 &=~0x400; - else if (UARTx==UART1) SCU->SCR0 &=~0x800; - else SCU->SCR0 &=~0x1000; - } -} -/******************************************************************************* -* Function Name : SCU_PFQBCCmd -* Description : Enable or Disable PFQBC -* Input : NewState : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void SCU_PFQBCCmd(FunctionalState NewState) -{ - if (NewState==ENABLE) - SCU->SCR0 |=0x1; - else SCU->SCR0 &=~0x1; -} - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM9_STR91X_IAR/Library/source/91x_uart.c b/Demo/ARM9_STR91X_IAR/Library/source/91x_uart.c deleted file mode 100644 index 84ef375a3..000000000 --- a/Demo/ARM9_STR91X_IAR/Library/source/91x_uart.c +++ /dev/null @@ -1,658 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 91x_uart.c -* Author : MCD Application Team -* Date First Issued : 05/18/2006 : Version 1.0 -* Description : This file provides all the UART software functions. -******************************************************************************** -* History: -* 05/24/2006 : Version 1.1 -* 05/18/2006 : Version 1.0 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -#include "91x_uart.h" -#include "91x_scu.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* UART IrDA Mask */ -#define UART_IrDA_Disable_Mask 0xFFFD /* IrDA Disable Mask */ -#define UART_IrDA_Enable_Mask 0x0002 /* IrDA Enable Mask */ -#define IrDA_LowPower_Enable_Mask 0x0004 /*IrDA lower power mode enable*/ -#define IrDA_LowPower_Disable_Mask 0xFFFB /*IrDA lower power mode enable*/ - -/* UART Mask */ -#define UART_Enable_Mask 0x0001 /* UART Enable Mask */ -#define UART_Disable_Mask 0xFFFE /* UART Disable Mask */ - -/* UART LoopBack */ -#define UART_LoopBack_Disable_Mask 0xFF7F /* LoopBack Disable Mask */ -#define UART_LoopBack_Enable_Mask 0x0080 /* LoopBack Enable Mask */ - -#define UART_WordLength_Mask 0xFF9F /* UART Word Length Mask */ -#define UART_Parity_Mask 0xFF79 /* UART Parity Mask */ -#define UART_HardwareFlowControl_Mask 0x3FFF /* UART Hardware Flow Control Mask */ -#define UART_TxRxFIFOLevel_Mask 0xFFC0 /* UART Tx Rx FIFO Level Mask */ -#define UART_BreakChar_Mask 0x0001 /* UART Break Character send Mask*/ -#define UART_FLAG_Mask 0x1F /* UART Flag Mask */ -#define UART_Mode_Mask 0xFCFF /* UART Mode Mask */ -#define UART_RTS_LowLevel_Mask 0x0800 /* RTS signal is low */ -#define UART_RTS_HighLevel_Mask 0xF7FF /* RTS signal is High */ -#define UART_DTR_LowLevel_Mask 0x0400 /* DTR signal is low */ -#define UART_DTR_HighLevel_Mask 0xFBFF /* DTR signal is High */ -#define UART_ClearFlag_Mask 0xAA /* Clear Flag Mask */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - - /******************************************************************************* -* Function Name : UART_DeInit -* Description : Deinitializes the UARTx peripheral registers -* to their default reset values. -* Input : UARTx: where x can be 0,1 or 2 to select the UART peripheral. -* Output : None -* Return : None -*******************************************************************************/ -void UART_DeInit(UART_TypeDef* UARTx) -{ - /* Reset the UARTx registers values */ - if(UARTx == UART0) - { - SCU_APBPeriphReset(__UART0,ENABLE); - SCU_APBPeriphReset(__UART0,DISABLE); - } - else if(UARTx == UART1) - { - SCU_APBPeriphReset(__UART1,ENABLE); - SCU_APBPeriphReset(__UART1,DISABLE); - } - else if(UARTx == UART2) - { - SCU_APBPeriphReset(__UART2,ENABLE); - SCU_APBPeriphReset(__UART2,DISABLE); - } -} - -/******************************************************************************* -* Function Name : UART_Init -* Description : Initializes the UARTx peripheral according to the specified -* parameters in the UART_InitStruct . -* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral. -* - UART_InitStruct: pointer to a UART_InitTypeDef structure -* that contains the configuration information for the -* specified UART peripheral. -* Output : None -* Return : None -*******************************************************************************/ -void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct) -{ - - u64 UART_MainClock = 0; - u32 IntegerDivider = 0; - u32 FractionalDivider = 0; - - /* Clear the LCR[6:5] bits */ - UARTx->LCR &= UART_WordLength_Mask; - /* Set the LCR[6:5] bits according to UART_WordLength value */ - UARTx->LCR |= UART_InitStruct->UART_WordLength; - - /* Choose Stop Bits */ - if(UART_InitStruct->UART_StopBits == UART_StopBits_2) - { - /* 2 Stop Bit */ - UARTx->LCR |= UART_StopBits_2; - } - else - { - /* One Stop Bits */ - UARTx->LCR &= UART_StopBits_1; - } - - /* Configure the Parity */ - /* Clear the LCR[7]and LCR[2:1] bits */ - UARTx->LCR &= UART_Parity_Mask; - /* Set the LCR[7]and LCR[2:1] bits according to UART_Parity value */ - UARTx->LCR |= UART_InitStruct->UART_Parity; - - /* Configure the BaudRate */ - UART_MainClock = (SCU_GetMCLKFreqValue())*1000; - if((SCU->CLKCNTR & 0x200) != 0x200) - { - UART_MainClock = UART_MainClock/2; - } - /* Determine the integer part */ - IntegerDivider = ((100) * (UART_MainClock) / (16 * (UART_InitStruct->UART_BaudRate))); - UARTx->IBRD = IntegerDivider / 100; - - /* Determine the fractional part */ - FractionalDivider = IntegerDivider - (100 * (UARTx->IBRD)); - UARTx->FBRD = ((((FractionalDivider * 64) + 50) / 100)); - - /* Choose the Hardware Flow Control */ - /* Clear the CR[15:14] bits */ - UARTx->CR &= UART_HardwareFlowControl_Mask; - /* Set the CR[15:14] bits according to UART_HardwareFlowControl value */ - UARTx->CR |= UART_InitStruct->UART_HardwareFlowControl; - - /* Configure the UART mode */ - /* Clear the CR[9:8] bits */ - UARTx->CR &= UART_Mode_Mask; - /* Set the CR[9:8] bits according to UART_Mode value */ - UARTx->CR |= UART_InitStruct->UART_Mode; - - /* Enable or disable the FIFOs */ - /* Set the FIFOs Levels */ - if(UART_InitStruct->UART_FIFO == UART_FIFO_Enable) - { - /* Enable the FIFOs */ - UARTx->LCR |= UART_FIFO_Enable; - - /* Clear TXIFLSEL and RXIFLSEL bits */ - UARTx->IFLS &= UART_TxRxFIFOLevel_Mask; - - /* Set RXIFLSEL bits according to UART_RxFIFOLevel value */ - UARTx->IFLS |= (UART_InitStruct->UART_RxFIFOLevel << 3); - - /* Set TXIFLSEL bits according to UART_TxFIFOLevel value */ - UARTx->IFLS |= UART_InitStruct->UART_TxFIFOLevel; - } - else - { - /* Disable the FIFOs */ - UARTx->LCR &= UART_FIFO_Disable; - } -} - -/******************************************************************************* -* Function Name : UART_StructInit -* Description : Fills each UART_InitStruct member with its reset value. -* Input : UART_InitStruct: pointer to a UART_InitTypeDef structure which -* will be initialized. -* Output : None -* Return : None -*******************************************************************************/ -void UART_StructInit(UART_InitTypeDef* UART_InitStruct) -{ - /* Reset the UART_InitStruct members */ - UART_InitStruct->UART_WordLength = UART_WordLength_8D; - UART_InitStruct->UART_StopBits = UART_StopBits_1; - UART_InitStruct->UART_Parity = UART_Parity_Odd ; - UART_InitStruct->UART_BaudRate = 9600; - UART_InitStruct->UART_HardwareFlowControl = UART_HardwareFlowControl_None; - UART_InitStruct->UART_Mode = UART_Mode_Tx_Rx; - UART_InitStruct->UART_FIFO = UART_FIFO_Enable; - UART_InitStruct->UART_TxFIFOLevel = UART_FIFOLevel_1_2; - UART_InitStruct->UART_RxFIFOLevel = UART_FIFOLevel_1_2; -} - -/******************************************************************************* -* Function Name : UART_Cmd -* Description : Enables or disables the specified UART peripheral. -* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral -* - NewState: new state of the UARTx peripheral. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void UART_Cmd(UART_TypeDef* UARTx, FunctionalState NewState) -{ - if (NewState == ENABLE) - { - /* Enable the selected UART by setting the UARTEN bit in the CR register */ - UARTx->CR |= UART_Enable_Mask; - } - else - { - /* Disable the selected UART by clearing the UARTEN bit in the CR register */ - UARTx->CR &= UART_Disable_Mask; - } -} - -/******************************************************************************* -* Function Name : UART_ITConfig -* Description : Enables or disables the specified UART interrupts. -* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral -* - UART_IT: specifies the UART interrupts sources to be -* enabled or disabled. This parameter can be any combination -* of the following values: -* - UART_IT_OverrunError: Overrun Error interrupt -* - UART_IT_BreakError: Break Error interrupt -* - UART_IT_ParityError: Parity Error interrupt -* - UART_IT_FrameError: Frame Error interrupt -* - UART_IT_ReceiveTimeOut: Receive Time Out interrupt -* - UART_IT_Transmit: Transmit interrupt -* - UART_IT_Receive: Receive interrupt -* - UART_IT_DSR: DSR interrupt -* - UART_IT_DCD: DCD interrupt -* - UART_IT_CTS: CTS interrupt -* - UART_IT_RI: RI interrupt -* - NewState: new state of the UARTx peripheral. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void UART_ITConfig(UART_TypeDef* UARTx, u16 UART_IT, FunctionalState NewState) -{ - if(NewState == ENABLE) - { - /* Enables the selected interrupts */ - UARTx->IMSC |= UART_IT; - } - else - { - /* Disables the selected interrupts */ - UARTx->IMSC &= ~UART_IT; - } -} - -/******************************************************************************* -* Function Name : UART_DMAConfig -* Description : Configures the UARTx’s DMA interface. -* Input : - UARTx: where x can be 1 or 2 to select the UART peripheral -* - UART_DMAOnError: specifies the DMA on error request. -* This parameter can be: -* - UART_DMAOnError_Enable: DMA receive request enabled -* when the UART error interrupt is asserted. -* - UART_DMAOnError_Disable: DMA receive request disabled -* when the UART error interrupt is asserted. -* Output : None -* Return : None -*******************************************************************************/ -void UART_DMAConfig(UART_TypeDef* UARTx, u16 UART_DMAOnError) -{ - if(UART_DMAOnError == UART_DMAOnError_Enable) - { - UARTx->DMACR &= UART_DMAOnError_Enable; - } - else - { - UARTx->DMACR |= UART_DMAOnError_Disable; - } -} - -/******************************************************************************* -* Function Name : UART_DMACmd -* Description : Enables or disables the UARTx’s DMA interface. -* Input : - UARTx: where x can be 1 or 2 to select the UART peripheral -* - UART_DMAReq: enables or disables the request of DMA from UART. -* This parameter can be: -* - UART_DMAReq_Tx: Transmit DMA Enable -* - UART_DMAReq_Rx: Receive DMA Enable -* - NewState: new state of the UARTx peripheral. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void UART_DMACmd(UART_TypeDef* UARTx, u8 UART_DMAReq, FunctionalState NewState) -{ - if(UART_DMAReq == UART_DMAReq_Tx) - { - if(NewState == ENABLE) - { - UARTx->DMACR |= UART_DMAReq_Tx; - } - else - { - UARTx->DMACR &= ~UART_DMAReq_Tx; - } - } - - if(UART_DMAReq == UART_DMAReq_Rx) - { - if(NewState == ENABLE) - { - UARTx->DMACR |= UART_DMAReq_Rx; - } - else - { - UARTx->DMACR &= ~UART_DMAReq_Rx; - } - } -} - -/******************************************************************************* -* Function Name : UART_LoopBackConfig -* Description : Enables or disables the LoopBack mode. -* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral -* - NewState: new state of the UARTx peripheral. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void UART_LoopBackConfig(UART_TypeDef* UARTx, FunctionalState NewState) -{ - if (NewState == ENABLE) - { - /* Enable the LoopBack mode of the specified UART */ - UARTx->CR |= UART_LoopBack_Enable_Mask; - } - else - { - /* Disable the LoopBack mode of the specified UART */ - UARTx->CR &= UART_LoopBack_Disable_Mask; - } -} - -/******************************************************************************* -* Function Name : UART_GetFlagStatus -* Description : Checks whether the specified UART flag is set or not. -* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral -* - UART_FLAG: specifies the flag to check. -* This parameter can be one of the following values: -* - UART_FLAG_OverrunError: Overrun error flag -* - UART_FLAG_Break: break error flag -* - UART_FLAG_ParityError: parity error flag -* - UART_FLAG_FrameError: frame error flag -* - UART_FLAG_RI: RI flag -* - UART_FLAG_TxFIFOEmpty: Transmit FIFO Empty flag -* - UART_FLAG_RxFIFOFull: Receive FIFO Full flag -* - UART_FLAG_TxFIFOFull: Transmit FIFO Full flag -* - UART_FLAG_RxFIFOEmpty: Receive FIFO Empty flag -* - UART_FLAG_Busy: UART Busy flag -* - UART_FLAG_CTS: CTS flag -* - UART_FLAG_DCD: DCD flag -* - UART_FLAG_DSR: DSR flag -* - UART_RawIT_OverrunError: Overrun Error interrupt flag -* - UART_RawIT_BreakError: Break Error interrupt flag -* - UART_RawIT_ParityError: Parity Error interrupt flag -* - UART_RawIT_FrameError: Frame Error interrupt flag -* - UART_RawIT_ReceiveTimeOut: ReceiveTimeOut interrupt flag -* - UART_RawIT_Transmit: Transmit interrupt flag -* - UART_RawIT_Receive: Receive interrupt flag -* - UART_RawIT_DSR: DSR interrupt flag -* - UART_RawIT_DCD: DCD interrupt flag -* - UART_RawIT_CTS: CTS interrupt flag -* - UART_RawIT_RI: RI interrupt flag -* Output : None -* Return : The new state of UART_FLAG (SET or RESET). -*******************************************************************************/ -FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, u16 UART_FLAG) -{ - - u32 UARTReg = 0, FlagPos = 0; - u32 StatusReg = 0; - - /* Get the UART register index */ - UARTReg = UART_FLAG >> 5; - - /* Get the flag position */ - FlagPos = UART_FLAG & UART_FLAG_Mask; - - if(UARTReg == 1) /* The flag to check is in RSR register */ - { - StatusReg = UARTx->RSECR; - } - else if (UARTReg == 2) /* The flag to check is in FR register */ - { - StatusReg = UARTx->FR; - } - else if(UARTReg == 3) /* The flag to check is in RIS register */ - { - StatusReg = UARTx->RIS; - } - - if((StatusReg & (1 << FlagPos))!= RESET) - { - return SET; - } - else - { - return RESET; - } -} - -/******************************************************************************* -* Function Name : UART_ClearFlag -* Description : Clears the UARTx’s flags(Frame, Parity, Break, Overrun error). -* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral. -* Output : None -* Return : None -*******************************************************************************/ -void UART_ClearFlag(UART_TypeDef* UARTx) -{ - /* Clear the flag */ - UARTx->RSECR = UART_ClearFlag_Mask; -} - -/******************************************************************************* -* Function Name : UART_GetITStatus -* Description : Checks whether the specified UART interrupt has occured or not. -* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral. -* - UART_IT: specifies the interrupt pending bit to be checked. -* This parameter can be one of the following values: -* - UART_IT_OverrunError: Overrun Error interrupt -* - UART_IT_BreakError: Break Error interrupt -* - UART_IT_ParityError: Parity Error interrupt -* - UART_IT_FrameError: Frame Error interrupt -* - UART_IT_ReceiveTimeOut: Receive Time Out interrupt -* - UART_IT_Transmit: Transmit interrupt -* - UART_IT_Receive: Receive interrupt -* - UART_IT_DSR: DSR interrupt -* - UART_IT_DCD: DCD interrupt -* - UART_IT_CTS: CTS interrupt -* - UART_IT_RI: RI interrupt -* Output : None -* Return : The new state of UART_IT (SET or RESET). -*******************************************************************************/ -ITStatus UART_GetITStatus(UART_TypeDef* UARTx, u16 UART_IT) -{ - if((UARTx->MIS & UART_IT) != RESET) - { - return SET; - } - else - { - return RESET; - } -} - -/******************************************************************************* -* Function Name : UART_ClearITPendingBit -* Description : Clears the UARTx’s interrupt pending bits. -* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral. -* - UART_IT: specifies the interrupt pending bit to clear. -* More than one interrupt can be cleared using the “|” operator. -* This parameter can be: -* - UART_IT_OverrunError: Overrun Error interrupt -* - UART_IT_BreakError: Break Error interrupt -* - UART_IT_ParityError: Parity Error interrupt -* - UART_IT_FrameError: Frame Error interrupt -* - UART_IT_ReceiveTimeOut: Receive Time Out interrupt -* - UART_IT_Transmit: Transmit interrupt -* - UART_IT_Receive: Receive interrupt -* - UART_IT_DSR: DSR interrupt -* - UART_IT_DCD: DCD interrupt -* - UART_IT_CTS: CTS interrupt -* - UART_IT_RI: RI interrupt -* Output : None -* Return : None -*******************************************************************************/ -void UART_ClearITPendingBit(UART_TypeDef* UARTx, u16 UART_IT) -{ - /* Clear the specified interrupt */ - UARTx->ICR &= UART_IT; -} - -/******************************************************************************* -* Function Name : UART_IrDALowPowerConfig -* Description : Sets the IrDA low power mode -* Input : - IrDAx: where x can be 0,1 or 2 to select the UART/IrDA peripheral. -* - NewState: new state of the UARTIrDA peripheral. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void UART_IrDALowPowerConfig(u8 IrDAx, FunctionalState NewState) -{ - UART_TypeDef* UARTx; - - switch(IrDAx) - { - case IrDA0: UARTx = UART0; - break; - case IrDA1: UARTx = UART1; - break; - case IrDA2: UARTx = UART2; - break; - } - - if (NewState == ENABLE) - { - UARTx->CR |= IrDA_LowPower_Enable_Mask; - } - else - { - UARTx->CR &= IrDA_LowPower_Disable_Mask; - } -} - -/******************************************************************************* -* Function Name : UART_IrDASetCounter -* Description : Sets the IrDA counter divisor value. -* Input : - UARTx: where x can be 0,1 or 2 to select the UART/IrDA peripheral. -* - IrDA_Counter: IrDA counter divisor new value n low power mode(Hz). -* Output : None -* Return : None -*******************************************************************************/ -void UART_IrDASetCounter(u8 IrDAx, u32 IrDA_Counter) -{ - UART_TypeDef* UARTx; - u32 APBClock; - switch(IrDAx) - { - case IrDA0: UARTx = UART0; - break; - case IrDA1: UARTx = UART1; - break; - case IrDA2: UARTx = UART2; - break; - } - /* Get the APB frequency */ - APBClock = (SCU_GetPCLKFreqValue())*1000; - /* Determine the Counter Divisor part */ - UARTx->ILPR = (((APBClock*10) / ( IrDA_Counter)) + 5 )/10; - } - -/******************************************************************************* -* Function Name : UART_IrDACmd -* Description : Enables or disables the UARTx’s IrDA interface. -* Input : - IrDAx: where x can be 0,1 or 2 to select the UART/IrDA peripheral -* - NewState: new state of the UARTx peripheral. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void UART_IrDACmd(u8 IrDAx, FunctionalState NewState) -{ - UART_TypeDef* UARTx; - - switch(IrDAx) - { - case IrDA0: UARTx = UART0; - break; - case IrDA1: UARTx = UART1; - break; - case IrDA2: UARTx = UART2; - break; - } - if(NewState == ENABLE) - { - /* Enable the IrDA mode of the specified UART */ - UARTx->CR |= UART_IrDA_Enable_Mask; - } - else - { - /* Disable the IrDA mode of the specified UART */ - UARTx->CR &= UART_IrDA_Disable_Mask; - } -} - -/******************************************************************************* -* Function Name : UART_SendData -* Description : Transmits signle Byte of data through the UARTx peripheral. -* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral. -* - Data: the byte to transmit -* Output : None -* Return : None -*******************************************************************************/ -void UART_SendData(UART_TypeDef* UARTx, u8 Data) -{ - /* Transmit one byte */ - UARTx->DR = Data; -} - -/******************************************************************************* -* Function Name : UART_ReceiveData -* Description : Returns the most recent received Byte by the UARTx peripheral. -* Input : UARTx: where x can be 0,1 or 2 to select the UART peripheral. -* Output : None -* Return : The received data -*******************************************************************************/ -u8 UART_ReceiveData(UART_TypeDef* UARTx) -{ - /* Receive one byte */ - return ((u8)UARTx->DR); -} - -/******************************************************************************* -* Function Name : UART_SendBreak -* Description : Transmits break characters. -* Input : UARTx: where x can be 0,1 or 2 to select the UART peripheral. -* Output : None -* Return : None -*******************************************************************************/ -void UART_SendBreak(UART_TypeDef* UARTx) -{ - /* Send break characters */ - UARTx->LCR |= UART_BreakChar_Mask; -} - -/******************************************************************************* -* Function Name : UART_RTSConfig -* Description : Sets or Resets the RTS signal -* Input : - LevelState: new state of the RTS signal for UART0 only. -* This parameter can be: LowLevel or HighLevel -* Output : None -* Return : None -*******************************************************************************/ -void UART_RTSConfig(UART_LevelTypeDef LevelState) -{ - if(LevelState == LowLevel) - { - UART0->CR |= UART_RTS_LowLevel_Mask; - } - else - { - UART0->CR &= UART_RTS_HighLevel_Mask; - } -} - -/******************************************************************************* -* Function Name : UART_DTRConfig -* Description : Sets or Resets the DTR signal for UART0 only -* Input : - LevelState: new state of the DTR signal. -* This parameter can be: LowLevel or HighLevel -* Output : None -* Return : None -*******************************************************************************/ -void UART_DTRConfig(UART_LevelTypeDef LevelState) -{ - if(LevelState == LowLevel) - { - UART0->CR |= UART_DTR_LowLevel_Mask; - } - else - { - UART0->CR &= UART_DTR_HighLevel_Mask; - } -} -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM9_STR91X_IAR/Library/source/91x_vic.c b/Demo/ARM9_STR91X_IAR/Library/source/91x_vic.c deleted file mode 100644 index fecb89096..000000000 --- a/Demo/ARM9_STR91X_IAR/Library/source/91x_vic.c +++ /dev/null @@ -1,830 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 91x_vic.c -* Author : MCD Application Team -* Date First Issued : 05/18/2006 : Version 1.0 -* Description : This file provides all the VIC software functions. -******************************************************************************** -* History: -* 05/24/2006 : Version 1.1 -* 05/18/2006 : Version 1.0 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH -* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS -* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT -* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT -* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION -* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - - -/* Standard include ----------------------------------------------------------*/ -#include "91x_vic.h" - -/* Include of other module interface headers ---------------------------------*/ -/* Local includes ------------------------------------------------------------*/ -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -#define VIC_REGISTER_NUMBER 16 -#define VIC_PROTECTION_ENABLE_MASK 0x1 -#define VIC_PROTECTION_DISABLE_MASK 0xFFFFFFFE -#define VIC_VECTOR_ENABLE_MASK 0x20 -#define VIC_IT_SOURCE_MASK 0xFFFFFFE0 -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ - -static void VIC_ITModeConfig(u16 VIC_Source, VIC_ITLineMode VIC_LineMode); -static void VIC_ISRVectAddConfig(u16 VIC_Source, u16 VIC_Priority, \ - void (*VIC_VectAddress)(void)); -static void VIC_VectEnableConfig(u16 VIC_Source, u16 VIC_Priority); -static void VIC_ITSourceConfig(u16 VIC_Source, u16 VIC_Priority); - -/* Interface functions -------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/******************************************************************************* -* Function Name : VIC_DeInit -* Description : Deinitialize the VIC module registers to their default reset -* values. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void VIC_DeInit(void) -{ - SCU_AHBPeriphReset(__VIC, ENABLE); /* VIC peripheral is under Reset */ - SCU_AHBPeriphReset(__VIC, DISABLE); /* VIC peripheral Reset off */ -} - -/******************************************************************************* -* Function Name : VIC_GetIRQStatus -* Description : Get the status of interrupts after IRQ masking. -* Input : VIC_Source: specifies the number of the source line. -* This parameter can be one of the following values: -* - WDG_ITLine : VIC source 0 -* - SW_ITLine : VIC source 1 -* - ARMRX_ITLine : VIC source 2 -* - ARMTX_ITLine : VIC source 3 -* - TIM0_ITLine : VIC source 4 -* - TIM1_ITLine : VIC source 5 -* - TIM2_ITLine : VIC source 6 -* - TIM3_ITLine : VIC source 7 -* - USBHP_ITLine : VIC source 8 -* - USBLP_ITLine : VIC source 9 -* - SCU_ITLine : VIC source 10 -* - ENET_ITLine : VIC source 11 -* - DMA_ITLine : VIC source 12 -* - CAN_ITLine : VIC source 13 -* - MC_ITLine : VIC source 14 -* - ADC_ITLine : VIC source 15 -* - UART0_ITLine : VIC source 16 -* - UART1_ITLine : VIC source 17 -* - UART2_ITLine : VIC source 18 -* - I2C0_ITLine : VIC source 19 -* - I2C1_ITLine : VIC source 20 -* - SSP0_ITLine : VIC source 21 -* - SSP1_ITLine : VIC source 22 -* - LVD_ITLine : VIC source 23 -* - RTC_ITLine : VIC source 24 -* - WIU_ITLine : VIC source 25 -* - EXTIT0_ITLine: VIC source 26 -* - EXTIT1_ITLine: VIC source 27 -* - EXTIT2_ITLine: VIC source 28 -* - EXTIT3_ITLine: VIC source 29 -* - USBWU_ITLine : VIC source 30 -* - PFQBC_ITLine : VIC source 31 -* Output : None -* Return : The status of the IRQ interrupt after masking (SET or RESET). -*******************************************************************************/ -FlagStatus VIC_GetIRQStatus(u16 VIC_Source) -{ - u32 VIC_Mask = 1; - if (VIC_Source < VIC_REGISTER_NUMBER) - { - if ((VIC0->ISR | VIC_Mask << VIC_Source) != RESET) - return SET; - else - return RESET; - } - else - { - if ((VIC1->ISR | VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)) != RESET) - return SET; - else - return RESET; - } -} - -/******************************************************************************* -* Function Name : VIC_GetFIQStatus -* Description : Get the status of interrupts after FIQ masking -* Input : VIC_Source: specifies the number of the source line. -* This parameter can be one of the following values: -* - WDG_ITLine : VIC source 0 -* - SW_ITLine : VIC source 1 -* - ARMRX_ITLine : VIC source 2 -* - ARMTX_ITLine : VIC source 3 -* - TIM0_ITLine : VIC source 4 -* - TIM1_ITLine : VIC source 5 -* - TIM2_ITLine : VIC source 6 -* - TIM3_ITLine : VIC source 7 -* - USBHP_ITLine : VIC source 8 -* - USBLP_ITLine : VIC source 9 -* - SCU_ITLine : VIC source 10 -* - ENET_ITLine : VIC source 11 -* - DMA_ITLine : VIC source 12 -* - CAN_ITLine : VIC source 13 -* - MC_ITLine : VIC source 14 -* - ADC_ITLine : VIC source 15 -* - UART0_ITLine : VIC source 16 -* - UART1_ITLine : VIC source 17 -* - UART2_ITLine : VIC source 18 -* - I2C0_ITLine : VIC source 19 -* - I2C1_ITLine : VIC source 20 -* - SSP0_ITLine : VIC source 21 -* - SSP1_ITLine : VIC source 22 -* - LVD_ITLine : VIC source 23 -* - RTC_ITLine : VIC source 24 -* - WIU_ITLine : VIC source 25 -* - EXTIT0_ITLine: VIC source 26 -* - EXTIT1_ITLine: VIC source 27 -* - EXTIT2_ITLine: VIC source 28 -* - EXTIT3_ITLine: VIC source 29 -* - USBWU_ITLine : VIC source 30 -* - PFQBC_ITLine : VIC source 31 -* Output : None -* Return : The status of the FIQ interrupt after masking (SET or RESET) -*******************************************************************************/ -FlagStatus VIC_GetFIQStatus(u16 VIC_Source) -{ - u32 VIC_Mask = 1; - if (VIC_Source < VIC_REGISTER_NUMBER) - { - if ((VIC0->RINTSR | VIC_Mask << VIC_Source) != RESET) - return SET; - else - return RESET; - } - else - { - if ((VIC1->RINTSR | VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)) != RESET) - return SET; - else - return RESET; - } -} - -/******************************************************************************* -* Function Name : VIC_GetSourceITStatus -* Description : Get the status of the source interrupts before masking. -* Input : VIC_Source: specifies the number of the source line. -* This parameter can be one of the following values: -* - WDG_ITLine : VIC source 0 -* - SW_ITLine : VIC source 1 -* - ARMRX_ITLine : VIC source 2 -* - ARMTX_ITLine : VIC source 3 -* - TIM0_ITLine : VIC source 4 -* - TIM1_ITLine : VIC source 5 -* - TIM2_ITLine : VIC source 6 -* - TIM3_ITLine : VIC source 7 -* - USBHP_ITLine : VIC source 8 -* - USBLP_ITLine : VIC source 9 -* - SCU_ITLine : VIC source 10 -* - ENET_ITLine : VIC source 11 -* - DMA_ITLine : VIC source 12 -* - CAN_ITLine : VIC source 13 -* - MC_ITLine : VIC source 14 -* - ADC_ITLine : VIC source 15 -* - UART0_ITLine : VIC source 16 -* - UART1_ITLine : VIC source 17 -* - UART2_ITLine : VIC source 18 -* - I2C0_ITLine : VIC source 19 -* - I2C1_ITLine : VIC source 20 -* - SSP0_ITLine : VIC source 21 -* - SSP1_ITLine : VIC source 22 -* - LVD_ITLine : VIC source 23 -* - RTC_ITLine : VIC source 24 -* - WIU_ITLine : VIC source 25 -* - EXTIT0_ITLine: VIC source 26 -* - EXTIT1_ITLine: VIC source 27 -* - EXTIT2_ITLine: VIC source 28 -* - EXTIT3_ITLine: VIC source 29 -* - USBWU_ITLine : VIC source 30 -* - PFQBC_ITLine : VIC source 31 -* Output : None -* Return : The status of the source interrupt before masking -*******************************************************************************/ -FlagStatus VIC_GetSourceITStatus(u16 VIC_Source) -{ - u32 VIC_Mask = 1; - if (VIC_Source < VIC_REGISTER_NUMBER) - { - if ((VIC0->FSR | VIC_Mask << VIC_Source) != RESET) - return SET; - else - return RESET; - } - else - { - if ((VIC1->FSR | VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)) != RESET) - return SET; - else - return RESET; - } -} - -/******************************************************************************* -* Function Name : VIC_ITModeConfig -* Description : Select the type of interrupt (IRQ or FIQ) -* Input1 : VIC_Source: specifies the number of the source line. -* This parameter can be one of the following values: -* - WDG_ITLine : VIC source 0 -* - SW_ITLine : VIC source 1 -* - ARMRX_ITLine : VIC source 2 -* - ARMTX_ITLine : VIC source 3 -* - TIM0_ITLine : VIC source 4 -* - TIM1_ITLine : VIC source 5 -* - TIM2_ITLine : VIC source 6 -* - TIM3_ITLine : VIC source 7 -* - USBHP_ITLine : VIC source 8 -* - USBLP_ITLine : VIC source 9 -* - SCU_ITLine : VIC source 10 -* - ENET_ITLine : VIC source 11 -* - DMA_ITLine : VIC source 12 -* - CAN_ITLine : VIC source 13 -* - MC_ITLine : VIC source 14 -* - ADC_ITLine : VIC source 15 -* - UART0_ITLine : VIC source 16 -* - UART1_ITLine : VIC source 17 -* - UART2_ITLine : VIC source 18 -* - I2C0_ITLine : VIC source 19 -* - I2C1_ITLine : VIC source 20 -* - SSP0_ITLine : VIC source 21 -* - SSP1_ITLine : VIC source 22 -* - LVD_ITLine : VIC source 23 -* - RTC_ITLine : VIC source 24 -* - WIU_ITLine : VIC source 25 -* - EXTIT0_ITLine: VIC source 26 -* - EXTIT1_ITLine: VIC source 27 -* - EXTIT2_ITLine: VIC source 28 -* - EXTIT3_ITLine: VIC source 29 -* - USBWU_ITLine : VIC source 30 -* - PFQBC_ITLine : VIC source 31 -* Input2 : VIC_LineMode :specifies the type of interrupt of the source -* line. This parameter can be one of the following values: -* - VIC_IRQ: the correspondent line is configured as IRQ. -* - VIC_FIQ: the correspondent line is configured as FIQ. -* Output : None -* Return : None -*******************************************************************************/ -static void VIC_ITModeConfig(u16 VIC_Source, VIC_ITLineMode VIC_LineMode) -{ - u32 VIC_Mask = 1; - - if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */ - { - if (VIC_LineMode == VIC_IRQ) - VIC0->INTSR &= ~(VIC_Mask << VIC_Source); - else /* VIC_LineMode == VIC_FIQ */ - VIC0->INTSR |= (VIC_Mask << VIC_Source); - } - else /* VIC1 */ - { - if (VIC_LineMode == VIC_IRQ) - VIC1->INTSR &= ~(VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)); - else /* VIC_LineMode == VIC_FIQ */ - VIC1->INTSR |= (VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)); - } -} - -/******************************************************************************* -* Function Name : VIC_ITCmd -* Description : Enable or disable the interrupt request lines. -* Input1 : VIC_Source: specifies the number of the source line. -* This parameter can be one of the following values: -* - WDG_ITLine : VIC source 0 -* - SW_ITLine : VIC source 1 -* - ARMRX_ITLine : VIC source 2 -* - ARMTX_ITLine : VIC source 3 -* - TIM0_ITLine : VIC source 4 -* - TIM1_ITLine : VIC source 5 -* - TIM2_ITLine : VIC source 6 -* - TIM3_ITLine : VIC source 7 -* - USBHP_ITLine : VIC source 8 -* - USBLP_ITLine : VIC source 9 -* - SCU_ITLine : VIC source 10 -* - ENET_ITLine : VIC source 11 -* - DMA_ITLine : VIC source 12 -* - CAN_ITLine : VIC source 13 -* - MC_ITLine : VIC source 14 -* - ADC_ITLine : VIC source 15 -* - UART0_ITLine : VIC source 16 -* - UART1_ITLine : VIC source 17 -* - UART2_ITLine : VIC source 18 -* - I2C0_ITLine : VIC source 19 -* - I2C1_ITLine : VIC source 20 -* - SSP0_ITLine : VIC source 21 -* - SSP1_ITLine : VIC source 22 -* - LVD_ITLine : VIC source 23 -* - RTC_ITLine : VIC source 24 -* - WIU_ITLine : VIC source 25 -* - EXTIT0_ITLine: VIC source 26 -* - EXTIT1_ITLine: VIC source 27 -* - EXTIT2_ITLine: VIC source 28 -* - EXTIT3_ITLine: VIC source 29 -* - USBWU_ITLine : VIC source 30 -* - PFQBC_ITLine : VIC source 31 -* Input2 : FMI_NewState: specifies the line status. -* This parameter can be one of the following values: -* - ENABLE: The line is enabled. -* - DISABLE: The line is disabled. -* Output : None -* Return : None -*******************************************************************************/ -void VIC_ITCmd(u16 VIC_Source, FunctionalState VIC_NewState) -{ - u32 VIC_Mask = 1; - - if (VIC_NewState == ENABLE) - { - if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */ - VIC0->INTER |= (VIC_Mask << VIC_Source); - else /* VIC1 */ - VIC1->INTER |= (VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)); - } - else /* VIC_NewState == DISABLE */ - { - if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */ - VIC0->INTECR |= (VIC_Mask << VIC_Source); - else /* VIC1 */ - VIC1->INTECR |= (VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)); - } -} - -/******************************************************************************* -* Function Name : VIC_SWITCmd -* Description : Generate a software interrupt for the specific source -* interrupt. -* Input1 : VIC_Source: specifies the number of the source line. -* This parameter can be one of the following values: -* - WDG_ITLine : VIC source 0 -* - SW_ITLine : VIC source 1 -* - ARMRX_ITLine : VIC source 2 -* - ARMTX_ITLine : VIC source 3 -* - TIM0_ITLine : VIC source 4 -* - TIM1_ITLine : VIC source 5 -* - TIM2_ITLine : VIC source 6 -* - TIM3_ITLine : VIC source 7 -* - USBHP_ITLine : VIC source 8 -* - USBLP_ITLine : VIC source 9 -* - SCU_ITLine : VIC source 10 -* - ENET_ITLine : VIC source 11 -* - DMA_ITLine : VIC source 12 -* - CAN_ITLine : VIC source 13 -* - MC_ITLine : VIC source 14 -* - ADC_ITLine : VIC source 15 -* - UART0_ITLine : VIC source 16 -* - UART1_ITLine : VIC source 17 -* - UART2_ITLine : VIC source 18 -* - I2C0_ITLine : VIC source 19 -* - I2C1_ITLine : VIC source 20 -* - SSP0_ITLine : VIC source 21 -* - SSP1_ITLine : VIC source 22 -* - LVD_ITLine : VIC source 23 -* - RTC_ITLine : VIC source 24 -* - WIU_ITLine : VIC source 25 -* - EXTIT0_ITLine: VIC source 26 -* - EXTIT1_ITLine: VIC source 27 -* - EXTIT2_ITLine: VIC source 28 -* - EXTIT3_ITLine: VIC source 29 -* - USBWU_ITLine : VIC source 30 -* - PFQBC_ITLine : VIC source 31 -* Input2 : FMI_NewState: specifies the software interrupt status. -* This parameter can be one of the following values: -* - ENABLE: The software interrupt is enabled. -* - DISABLE: The software interrupt is disabled. -* Output : None -* Return : None -*******************************************************************************/ -void VIC_SWITCmd(u16 VIC_Source, FunctionalState VIC_NewState) -{ - u32 VIC_Mask = 1; - - if (VIC_NewState == ENABLE) - { - if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */ - VIC0->SWINTR |= (VIC_Mask << VIC_Source); - else /* VIC1 */ - VIC1->SWINTR |= (VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)); - } - else /* VIC_NewState == DISABLE */ - { - if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */ - VIC0->SWINTCR = (VIC_Mask << VIC_Source); - else /* VIC1 */ - VIC1->SWINTCR = (VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)); - } -} - -/******************************************************************************* -* Function Name : VIC_ProtectionCmd -* Description : Enable or Disable the register access protection. -* Input : FMI_NewState: specifies the protection status. -* This parameter can be one of the following values: -* - ENABLE: The protection is enabled. -* - DISABLE: The protection is disabled. -* Output : None -* Return : None -*******************************************************************************/ -void VIC_ProtectionCmd(FunctionalState VIC_NewState) -{ - if (VIC_NewState == ENABLE) - { - VIC0->PER |= VIC_PROTECTION_ENABLE_MASK; - VIC1->PER |= VIC_PROTECTION_ENABLE_MASK; - } - else - { - VIC0->PER &= VIC_PROTECTION_DISABLE_MASK; - VIC1->PER &= VIC_PROTECTION_DISABLE_MASK; - } -} - -/******************************************************************************* -* Function Name : VIC_GetCurrentISRAdd -* Description : Get the address of the current active ISR. -* Input : VICx: specifies the VIC peripheral -* This parameter can be one of the following values: -* - VIC0: To select VIC0. -* - VIC1: To select VIC1. -* Output : None -* Return : The Address of the active ISR. -*******************************************************************************/ -u32 VIC_GetCurrentISRAdd(VIC_TypeDef* VICx) -{ - return VICx->VAR; -} - -/******************************************************************************* -* Function Name : VIC_ISRVectAddConfig -* Description : Configuration of the ISR vector address. -* Input1 : VIC_Source: specifies the number of the source line. -* This parameter can be one of the following values: -* - WDG_ITLine : VIC source 0 -* - SW_ITLine : VIC source 1 -* - ARMRX_ITLine : VIC source 2 -* - ARMTX_ITLine : VIC source 3 -* - TIM0_ITLine : VIC source 4 -* - TIM1_ITLine : VIC source 5 -* - TIM2_ITLine : VIC source 6 -* - TIM3_ITLine : VIC source 7 -* - USBHP_ITLine : VIC source 8 -* - USBLP_ITLine : VIC source 9 -* - SCU_ITLine : VIC source 10 -* - ENET_ITLine : VIC source 11 -* - DMA_ITLine : VIC source 12 -* - CAN_ITLine : VIC source 13 -* - MC_ITLine : VIC source 14 -* - ADC_ITLine : VIC source 15 -* - UART0_ITLine : VIC source 16 -* - UART1_ITLine : VIC source 17 -* - UART2_ITLine : VIC source 18 -* - I2C0_ITLine : VIC source 19 -* - I2C1_ITLine : VIC source 20 -* - SSP0_ITLine : VIC source 21 -* - SSP1_ITLine : VIC source 22 -* - LVD_ITLine : VIC source 23 -* - RTC_ITLine : VIC source 24 -* - WIU_ITLine : VIC source 25 -* - EXTIT0_ITLine: VIC source 26 -* - EXTIT1_ITLine: VIC source 27 -* - EXTIT2_ITLine: VIC source 28 -* - EXTIT3_ITLine: VIC source 29 -* - USBWU_ITLine : VIC source 30 -* - PFQBC_ITLine : VIC source 31 -* Input2 : VIC_Priority: specifies the priority of the interrupt. -* It can be a value from 0 to 15. 0 is the highest priority. -* Input3 : void (*VIC_VectAddress)(void): specifies the ISR vector -* address pointer. -* Output : None -* Return : None -*******************************************************************************/ -static void VIC_ISRVectAddConfig(u16 VIC_Source, u16 VIC_Priority, \ - void (*VIC_VectAddress)(void)) -{ - if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */ - VIC0->VAiR[VIC_Priority] = (u32)VIC_VectAddress; - else /* VIC1 */ - VIC1->VAiR[VIC_Priority] = (u32)VIC_VectAddress; -} - -/******************************************************************************* -* Function Name : VIC_GetISRVectAdd -* Description : Get the ISR vector address of the correspondent line. -* Input : VIC_Source: specifies the number of the source line. -* This parameter can be one of the following values: -* - WDG_ITLine : VIC source 0 -* - SW_ITLine : VIC source 1 -* - ARMRX_ITLine : VIC source 2 -* - ARMTX_ITLine : VIC source 3 -* - TIM0_ITLine : VIC source 4 -* - TIM1_ITLine : VIC source 5 -* - TIM2_ITLine : VIC source 6 -* - TIM3_ITLine : VIC source 7 -* - USBHP_ITLine : VIC source 8 -* - USBLP_ITLine : VIC source 9 -* - SCU_ITLine : VIC source 10 -* - ENET_ITLine : VIC source 11 -* - DMA_ITLine : VIC source 12 -* - CAN_ITLine : VIC source 13 -* - MC_ITLine : VIC source 14 -* - ADC_ITLine : VIC source 15 -* - UART0_ITLine : VIC source 16 -* - UART1_ITLine : VIC source 17 -* - UART2_ITLine : VIC source 18 -* - I2C0_ITLine : VIC source 19 -* - I2C1_ITLine : VIC source 20 -* - SSP0_ITLine : VIC source 21 -* - SSP1_ITLine : VIC source 22 -* - LVD_ITLine : VIC source 23 -* - RTC_ITLine : VIC source 24 -* - WIU_ITLine : VIC source 25 -* - EXTIT0_ITLine: VIC source 26 -* - EXTIT1_ITLine: VIC source 27 -* - EXTIT2_ITLine: VIC source 28 -* - EXTIT3_ITLine: VIC source 29 -* - USBWU_ITLine : VIC source 30 -* - PFQBC_ITLine : VIC source 31 -* Output : None -* Return : The correspondent ISR vector address. -*******************************************************************************/ -u32 VIC_GetISRVectAdd(u16 VIC_Source) -{ - if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */ - return VIC0->VAiR[VIC_Source]; - else /* VIC1 */ - return VIC1->VAiR[VIC_Source - VIC_REGISTER_NUMBER]; -} - -/******************************************************************************* -* Function Name : VIC_VectEnableConfig -* Description : Enable the vector interrupt. -* Input1 : VIC_Source: specifies the number of the source line. -* This parameter can be one of the following values: -* - WDG_ITLine : VIC source 0 -* - SW_ITLine : VIC source 1 -* - ARMRX_ITLine : VIC source 2 -* - ARMTX_ITLine : VIC source 3 -* - TIM0_ITLine : VIC source 4 -* - TIM1_ITLine : VIC source 5 -* - TIM2_ITLine : VIC source 6 -* - TIM3_ITLine : VIC source 7 -* - USBHP_ITLine : VIC source 8 -* - USBLP_ITLine : VIC source 9 -* - SCU_ITLine : VIC source 10 -* - ENET_ITLine : VIC source 11 -* - DMA_ITLine : VIC source 12 -* - CAN_ITLine : VIC source 13 -* - MC_ITLine : VIC source 14 -* - ADC_ITLine : VIC source 15 -* - UART0_ITLine : VIC source 16 -* - UART1_ITLine : VIC source 17 -* - UART2_ITLine : VIC source 18 -* - I2C0_ITLine : VIC source 19 -* - I2C1_ITLine : VIC source 20 -* - SSP0_ITLine : VIC source 21 -* - SSP1_ITLine : VIC source 22 -* - LVD_ITLine : VIC source 23 -* - RTC_ITLine : VIC source 24 -* - WIU_ITLine : VIC source 25 -* - EXTIT0_ITLine: VIC source 26 -* - EXTIT1_ITLine: VIC source 27 -* - EXTIT2_ITLine: VIC source 28 -* - EXTIT3_ITLine: VIC source 29 -* - USBWU_ITLine : VIC source 30 -* - PFQBC_ITLine : VIC source 31 -* Input2 : VIC_Priority: specifies the priority of the interrupt. -* It can be a value from 0 to 15. 0 is the highest priority. -* Output : None -* Return : None -*******************************************************************************/ -static void VIC_VectEnableConfig(u16 VIC_Source, u16 VIC_Priority) -{ - if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */ - VIC0->VCiR[VIC_Priority] |= VIC_VECTOR_ENABLE_MASK; - else /* VIC1 */ - VIC1->VCiR[VIC_Priority] |= VIC_VECTOR_ENABLE_MASK; -} - -/******************************************************************************* -* Function Name : VIC_ITSourceConfig -* Description : Select the interrupt source. -* Input1 : VIC_Source: specifies the number of the source line. -* This parameter can be one of the following values: -* - WDG_ITLine : VIC source 0 -* - SW_ITLine : VIC source 1 -* - ARMRX_ITLine : VIC source 2 -* - ARMTX_ITLine : VIC source 3 -* - TIM0_ITLine : VIC source 4 -* - TIM1_ITLine : VIC source 5 -* - TIM2_ITLine : VIC source 6 -* - TIM3_ITLine : VIC source 7 -* - USBHP_ITLine : VIC source 8 -* - USBLP_ITLine : VIC source 9 -* - SCU_ITLine : VIC source 10 -* - ENET_ITLine : VIC source 11 -* - DMA_ITLine : VIC source 12 -* - CAN_ITLine : VIC source 13 -* - MC_ITLine : VIC source 14 -* - ADC_ITLine : VIC source 15 -* - UART0_ITLine : VIC source 16 -* - UART1_ITLine : VIC source 17 -* - UART2_ITLine : VIC source 18 -* - I2C0_ITLine : VIC source 19 -* - I2C1_ITLine : VIC source 20 -* - SSP0_ITLine : VIC source 21 -* - SSP1_ITLine : VIC source 22 -* - LVD_ITLine : VIC source 23 -* - RTC_ITLine : VIC source 24 -* - WIU_ITLine : VIC source 25 -* - EXTIT0_ITLine: VIC source 26 -* - EXTIT1_ITLine: VIC source 27 -* - EXTIT2_ITLine: VIC source 28 -* - EXTIT3_ITLine: VIC source 29 -* - USBWU_ITLine : VIC source 30 -* - PFQBC_ITLine : VIC source 31 -* Input2 : VIC_Priority: specifies the priority of the interrupt. -* It can be a value from 0 to 15. 0 is the highest priority. -* Output : None -* Return : None -*******************************************************************************/ -static void VIC_ITSourceConfig(u16 VIC_Source, u16 VIC_Priority) -{ - if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */ - { - VIC0->VCiR[VIC_Priority] &= VIC_IT_SOURCE_MASK; - VIC0->VCiR[VIC_Priority] |= VIC_Source; - } - else /* VIC1 */ - { - VIC1->VCiR[VIC_Priority] &= VIC_IT_SOURCE_MASK; - VIC1->VCiR[VIC_Priority] |= VIC_Source - VIC_REGISTER_NUMBER; - } -} - -/******************************************************************************* -* Function Name : VIC_Config -* Description : Configure the ISR, the line, the mode and the priority for -* each interrupt source line. -* Input1 : VIC_Source: specifies the number of the source line. -* This parameter can be one of the following values: -* - WDG_ITLine : VIC source 0 -* - SW_ITLine : VIC source 1 -* - ARMRX_ITLine : VIC source 2 -* - ARMTX_ITLine : VIC source 3 -* - TIM0_ITLine : VIC source 4 -* - TIM1_ITLine : VIC source 5 -* - TIM2_ITLine : VIC source 6 -* - TIM3_ITLine : VIC source 7 -* - USBHP_ITLine : VIC source 8 -* - USBLP_ITLine : VIC source 9 -* - SCU_ITLine : VIC source 10 -* - ENET_ITLine : VIC source 11 -* - DMA_ITLine : VIC source 12 -* - CAN_ITLine : VIC source 13 -* - MC_ITLine : VIC source 14 -* - ADC_ITLine : VIC source 15 -* - UART0_ITLine : VIC source 16 -* - UART1_ITLine : VIC source 17 -* - UART2_ITLine : VIC source 18 -* - I2C0_ITLine : VIC source 19 -* - I2C1_ITLine : VIC source 20 -* - SSP0_ITLine : VIC source 21 -* - SSP1_ITLine : VIC source 22 -* - LVD_ITLine : VIC source 23 -* - RTC_ITLine : VIC source 24 -* - WIU_ITLine : VIC source 25 -* - EXTIT0_ITLine: VIC source 26 -* - EXTIT1_ITLine: VIC source 27 -* - EXTIT2_ITLine: VIC source 28 -* - EXTIT3_ITLine: VIC source 29 -* - USBWU_ITLine : VIC source 30 -* - PFQBC_ITLine : VIC source 31 -* Input2 : VIC_LineMode :specifies the type of interrupt of the source -* line. This parameter can be one of the following values: -* - VIC_IRQ: the correspondent line is configured as IRQ. -* - VIC_FIQ: the correspondent line is configured as FIQ. -* Input3 : VIC_Priority: specifies the priority of the interrupt. -* It can be a value from 0 to 15. 0 is the highest priority. -* Output : None -* Return : None -*******************************************************************************/ -void VIC_Config(u16 VIC_Source, VIC_ITLineMode VIC_LineMode, u8 VIC_Priority) -{ - switch (VIC_Source) - { - case 0: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, WDG_IRQHandler); - break; - - case 1: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, SW_IRQHandler); - break; - - case 2: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, ARMRX_IRQHandler); - break; - - case 3: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, ARMTX_IRQHandler); - break; - - case 4: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, TIM0_IRQHandler); - break; - - case 5: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, TIM1_IRQHandler); - break; - - case 6: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, TIM2_IRQHandler); - break; - - case 7: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, TIM3_IRQHandler); - break; - - case 8: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, USBHP_IRQHandler); - break; - - case 9: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, USBLP_IRQHandler); - break; - - case 10: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, SCU_IRQHandler); - break; - - case 11: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, ENET_IRQHandler); - break; - - case 12: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, DMA_IRQHandler); - break; - - case 13: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, CAN_IRQHandler); - break; - - case 14: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, MC_IRQHandler); - break; - - case 15: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, ADC_IRQHandler); - break; - - case 16: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, UART0_IRQHandler); - break; - - case 17: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, UART1_IRQHandler); - break; - - case 18: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, UART2_IRQHandler); - break; - - case 19: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, I2C0_IRQHandler); - break; - - case 20: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, I2C1_IRQHandler); - break; - - case 21: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, SSP0_IRQHandler); - break; - - case 22: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, SSP1_IRQHandler); - break; - - case 23: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, LVD_IRQHandler); - break; - - case 24: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, RTC_IRQHandler); - break; - - case 25: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, WIU_IRQHandler); - break; - - case 26: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, EXTIT0_IRQHandler); - break; - - case 27: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, EXTIT1_IRQHandler); - break; - - case 28: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, EXTIT2_IRQHandler); - break; - - case 29: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, EXTIT3_IRQHandler); - break; - - case 30: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, USBWU_IRQHandler); - break; - - case 31: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, PFQBC_IRQHandler); - break; - - default: break; - } - VIC_ITModeConfig(VIC_Source, VIC_LineMode); - VIC_VectEnableConfig(VIC_Source, VIC_Priority); - VIC_ITSourceConfig(VIC_Source, VIC_Priority); -} - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM9_STR91X_IAR/Library/source/91x_wdg.c b/Demo/ARM9_STR91X_IAR/Library/source/91x_wdg.c deleted file mode 100644 index f933635d0..000000000 --- a/Demo/ARM9_STR91X_IAR/Library/source/91x_wdg.c +++ /dev/null @@ -1,277 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : 91x_wdg.c -* Author : MCD Application Team -* Date First Issued : 05/18/2006 : Version 1.0 -* Description : This file provides all the WDG software functions. -******************************************************************************** -* History: -* 05/24/2006 : Version 1.1 -* 05/18/2006 : Version 1.0 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -#include "91x_wdg.h" -#include "91x_scu.h" -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - - -/* WDG End of Count interrupt Flag */ -#define WDG_FLAG_EC 0x0001 - - -/* WDG End of Count interrupt request */ -#define WDG_IT_EC 0x0001 - - - -/* WDG Start/Stop counter */ -#define WDG_Counter_Start 0x0002 -#define WDG_Counter_Stop 0xFFFD - - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Registers reset value */ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/****************************************************************************** -* Function Name : WDG_DeInit -* Description : Deinitializes the WDG peripheral registers to their default -* reset values. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void WDG_DeInit(void) -{ - - SCU_APBPeriphReset(__WDG, ENABLE); /*WDG peripheral under Reset */ - SCU_APBPeriphReset(__WDG, DISABLE); /*WDG peripheral Reset off*/ - -} - -/******************************************************************************* -* Function Name : WDG_StructInit -* Description : Fills the WDG_InitTypeDef structure member with its reset -* value. -* Input : WDG_InitStruct : pointer to a WDG_InitTypeDef structure -* which will be initialized. -* Output : None -* Return : None -*******************************************************************************/ -void WDG_StructInit(WDG_InitTypeDef *WDG_InitStruct) -{ - /* Select the Watchdog running mode*/ - WDG_InitStruct->WDG_Mode = WDG_Mode_Timer; - - /* Select the source clock */ - WDG_InitStruct-> WDG_ClockSource = WDG_ClockSource_Apb; - - /* Initialize Prescaler */ - WDG_InitStruct->WDG_Prescaler =0xFF; - - /* Initialize Preload */ - WDG_InitStruct->WDG_Preload =0xFFFF; - - -} - -/******************************************************************************* -* Function Name : WDG_Init -* Description : Initializes WDG peripheral according to the specified -* parameters in the WDG_InitStruct. -* Input : WDG_InitStruct: pointer to a WDG_InitTypeDef structure that -* contains the configuration information for the WDG peripheral. -* Output : None -* Return : None -*******************************************************************************/ -void WDG_Init(WDG_InitTypeDef* WDG_InitStruct) -{ - - - if(WDG_InitStruct->WDG_ClockSource == WDG_ClockSource_Apb) - { - /* Select The APB clock as clock source */ - WDG->CR &= WDG_ClockSource_Apb; - } - - else - { - /* Select the RTC clock as source */ - WDG->CR |= WDG_ClockSource_Rtc ; - } - - - /* Configure WDG Prescaler register value */ - WDG->PR = WDG_InitStruct->WDG_Prescaler; - - /* Configure WDG Pre-load register value */ - WDG->VR = WDG_InitStruct->WDG_Preload ; - - - if(WDG_InitStruct->WDG_Mode == WDG_Mode_Timer) - { - /* Select Timer mode */ - WDG->CR &= WDG_Mode_Timer; - } - else - { - /* Select WDG mode */ - WDG->CR |= WDG_Mode_Wdg ; - } - - -} - -/******************************************************************************* -* Function Name : WDG_Cmd -* Description : Enables or disables the WDG peripheral. -* Input : NewState: new state of the WDG peripheral (Newstate can be -* ENABLE or DISABLE) -* Output : None -* Return : None -*******************************************************************************/ -void WDG_Cmd(FunctionalState NewState ) -{ - if((WDG->CR & WDG_Mode_Wdg) == 0) - { - /* Timer mode */ - if(NewState == ENABLE) - { - /* Start timer by setting SC bit in Control register */ - WDG->CR |= WDG_Counter_Start; - } - else - { - /* Stop timer by clearning SC bit in Control register */ - WDG->CR &= WDG_Counter_Stop; - } - } - else - { - /* Watchdog mode */ - if(NewState == ENABLE) - { - WDG->KR = WDG_KeyValue1; - WDG->KR = WDG_KeyValue2; - } - } -} - -/******************************************************************************* -* Function Name : WDG_ITConfig -* Description : Enables or disables the WDG End of Count(EC) interrupt. -* Input : Newstate: new state of the End of Count(EC) WDG interrupt. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void WDG_ITConfig(FunctionalState NewState) -{ - if(NewState == ENABLE) - { - /* Enable the End of Count interrupt */ - WDG->MR |= WDG_IT_EC; - } - else - { - /* Disable the End of Count interrupt */ - WDG->MR &= ~WDG_IT_EC; - } -} - -/******************************************************************************* -* Function Name : WDG_GetCounter -* Description : Gets the WDG’s current counter value. -* Input : None -* Output : None -* Return : The WDG current counter value -*******************************************************************************/ -u16 WDG_GetCounter(void) -{ - return WDG->CNT; -} - - - - -/******************************************************************************* -* Function Name : WDG_GetITStatus -* Description : Checks whether the WDG End of Count(EC) interrupt is occured or not. -* Input : None -* Output : None -* Return : The new state of WDG_IT (SET or RESET). -*******************************************************************************/ -ITStatus WDG_GetITStatus(void) -{ - if(((WDG->SR & WDG_IT_EC) != RESET )&&((WDG->MR & WDG_IT_EC) != RESET )) - { - return SET; - } - else - { - return RESET; - } -} - -/******************************************************************************* -* Function Name : WDG_ClearITPendingBit -* Description : Clears the WDG's End of Count(EC) interrupt pending bit. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void WDG_ClearITPendingBit(void) -{ - /* Clear the EC pending bit */ - WDG->SR &= ~WDG_IT_EC; - -} - -/******************************************************************************* -* Function Name : WDG_ClearFlag -* Description : Clears the WDG's End of Count(EC) Flag. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void WDG_ClearFlag(void) -{ - /* Clear the EC Flag */ - - WDG->SR &= ~WDG_FLAG_EC; - -} - - -/******************************************************************************* -* Function Name : WDG_GetFlagStatus -* Description : Checks whether the WDG End of Count(EC) flag is set or not. -* Input : None -* Output : None -* Return : The new state of the WDG_FLAG (SET or RESET). -*******************************************************************************/ -FlagStatus WDG_GetFlagStatus(void) -{ - if((WDG->SR & WDG_FLAG_EC) != RESET ) - { - return SET; - } - else - { - return RESET; - } -} - - - -/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM9_STR91X_IAR/ParTest/ParTest.c b/Demo/ARM9_STR91X_IAR/ParTest/ParTest.c deleted file mode 100644 index 11b764583..000000000 --- a/Demo/ARM9_STR91X_IAR/ParTest/ParTest.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* Library includes. */ -#include "91x_lib.h" - -/* Scheduler includes. */ -#include "FreeRTOS.h" - -/* Demo application includes. */ -#include "partest.h" - -#define partstMAX_LEDs 4 -#define partstLED_PORT *( ( unsigned portSHORT * ) 0x5800f3fc ) - -/*-----------------------------------------------------------*/ - -static GPIO_InitTypeDef GPIO9_InitStruct; - -void vParTestInitialise( void ) -{ - /* Configure the bits used to flash LED's on port 9 as output. */ - GPIO_StructInit( &GPIO9_InitStruct ); - GPIO9_InitStruct.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3; - GPIO9_InitStruct.GPIO_Direction = GPIO_PinOutput; - GPIO_Init( GPIO9, &GPIO9_InitStruct ); -} -/*-----------------------------------------------------------*/ - -void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) -{ -unsigned portSHORT usLED = 0x0001; - - if( uxLED < partstMAX_LEDs ) - { - usLED <<= uxLED; - - portENTER_CRITICAL(); - { - if( xValue ) - { - partstLED_PORT &= ~usLED; - } - else - { - partstLED_PORT |= usLED; - } - } - portEXIT_CRITICAL(); - } -} -/*-----------------------------------------------------------*/ - -void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) -{ -unsigned portSHORT usLED = 0x0001; - - if( uxLED < partstMAX_LEDs ) - { - usLED <<= uxLED; - - portENTER_CRITICAL(); - { - if( partstLED_PORT & usLED ) - { - partstLED_PORT &= ~usLED; - } - else - { - partstLED_PORT |= usLED; - } - } - portEXIT_CRITICAL(); - } -} - - - - diff --git a/Demo/ARM9_STR91X_IAR/RTOSDemo.dep b/Demo/ARM9_STR91X_IAR/RTOSDemo.dep deleted file mode 100644 index bb7376f2e..000000000 --- a/Demo/ARM9_STR91X_IAR/RTOSDemo.dep +++ /dev/null @@ -1,2105 +0,0 @@ - - - - 2 - - ARM - - $PROJ_DIR$\ARM\Obj\comtest.r79 - $PROJ_DIR$\..\Common\include\BlockQ.h - $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\clock.h - $PROJ_DIR$\ARM\Obj\lcd.r79 - $PROJ_DIR$\Library\include\91x_uart.h - $TOOLKIT_DIR$\inc\stdio.h - $TOOLKIT_DIR$\inc\math.h - $PROJ_DIR$\Library\include\91x_map.h - $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\lc.h - $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\uip.h - $PROJ_DIR$\..\..\Source\include\FreeRTOS.h - $PROJ_DIR$\Library\include\91x_lib.h - $PROJ_DIR$\Library\include\91x_ahbapb.h - $PROJ_DIR$\Library\include\91x_scu.h - $PROJ_DIR$\..\..\Source\include\projdefs.h - $PROJ_DIR$\..\..\Source\include\croutine.h - $PROJ_DIR$\..\Common\include\flop.h - $TOOLKIT_DIR$\inc\ymath.h - $PROJ_DIR$\Library\include\91x_gpio.h - $PROJ_DIR$\..\Common\include\flash.h - $PROJ_DIR$\..\..\Source\include\list.h - $PROJ_DIR$\webserver\httpd-fs.h - $PROJ_DIR$\..\Common\Minimal\dynamic.c - $PROJ_DIR$\..\Common\include\integer.h - $PROJ_DIR$\webserver\uip-conf.h - $PROJ_DIR$\webserver\httpd-fsdata.c - $PROJ_DIR$\Library\include\91x_type.h - $PROJ_DIR$\Library\include\91x_vic.h - $TOOLKIT_DIR$\inc\intrinsics.h - $PROJ_DIR$\Library\include\91x_fmi.h - $TOOLKIT_DIR$\inc\DLib_Product.h - $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\pt.h - $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\uip_arch.h - $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\uip_arp.h - $TOOLKIT_DIR$\inc\xencoding_limits.h - $PROJ_DIR$\..\Common\include\comtest.h - $PROJ_DIR$\..\Common\include\dynamic.h - $TOOLKIT_DIR$\inc\yvals.h - $PROJ_DIR$\webserver\webserver.h - $PROJ_DIR$\Library\include\91x_enet.h - $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\lc-switch.h - $TOOLKIT_DIR$\inc\stdint.h - $PROJ_DIR$\Library\include\91x_wdg.h - $PROJ_DIR$\STCode\lcd.h - $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\timer.h - $PROJ_DIR$\..\Common\include\PollQ.h - $TOOLKIT_DIR$\inc\ysizet.h - $TOOLKIT_DIR$\inc\DLib_Threads.h - $PROJ_DIR$\..\..\Source\include\queue.h - $PROJ_DIR$\..\Common\include\comtest2.h - $TOOLKIT_DIR$\inc\inttypes.h - $PROJ_DIR$\..\..\Source\include\portable.h - $TOOLKIT_DIR$\inc\intrinsic.h - $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\uipopt.h - $PROJ_DIR$\webserver\httpd.h - $PROJ_DIR$\..\Common\include\serial.h - $PROJ_DIR$\..\Common\include\partest.h - $PROJ_DIR$\webserver\httpd-cgi.h - $PROJ_DIR$\..\Common\include\semtest.h - $TOOLKIT_DIR$\inc\DLib_Defaults.h - $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\psock.h - $PROJ_DIR$\webserver\clock-arch.h - $TOOLKIT_DIR$\inc\string.h - $PROJ_DIR$\..\..\Source\include\semphr.h - $PROJ_DIR$\..\..\Source\include\task.h - $TOOLKIT_DIR$\inc\stdlib.h - $PROJ_DIR$\webserver\http-strings.h - $TOOLKIT_DIR$\inc\stddef.h - $PROJ_DIR$\webserver\httpd-fsdata.h - $PROJ_DIR$\..\..\Source\portable\IAR\STR91x\portmacro.h - $PROJ_DIR$\ARM\Obj\dynamic.r79 - $PROJ_DIR$\Library\include\91x_it.h - $PROJ_DIR$\..\Common\Minimal\comtest.c - $PROJ_DIR$\..\Common\Minimal\BlockQ.c - $PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c - $PROJ_DIR$\..\Common\Minimal\integer.c - $PROJ_DIR$\STCode\lcd.c - $PROJ_DIR$\main.c - $PROJ_DIR$\..\Common\Minimal\semtest.c - $PROJ_DIR$\..\Common\Minimal\PollQ.c - $PROJ_DIR$\ParTest\ParTest.c - $PROJ_DIR$\serial\serial.c - $PROJ_DIR$\Library\source\91x_enet.c - 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- - - RTOS Source - - $PROJ_DIR$\FreeRTOSConfig.h - - - $PROJ_DIR$\..\..\Source\list.c - - - $PROJ_DIR$\..\..\Source\portable\IAR\STR91x\port.c - - - $PROJ_DIR$\..\..\Source\portable\IAR\STR91x\portasm.s79 - - - $PROJ_DIR$\..\..\Source\queue.c - - - $PROJ_DIR$\..\..\Source\tasks.c - - - - System Files - - $PROJ_DIR$\91x_init_IAR.s - - - $PROJ_DIR$\91x_vect_IAR.s - - - $PROJ_DIR$\lnkarm_flash.xcl - - - $PROJ_DIR$\lnkarm_ram.xcl - - - - uIP - - $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\apps\webserver\http-strings.c - - - $PROJ_DIR$\webserver\httpd-cgi.c - - - $PROJ_DIR$\webserver\httpd-fs.c - - - $PROJ_DIR$\webserver\httpd.c - - - $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\psock.c - - - $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\timer.c - - - $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\uip.c - - - $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\uip_arp.c - - - - - diff --git a/Demo/ARM9_STR91X_IAR/RTOSDemo.eww b/Demo/ARM9_STR91X_IAR/RTOSDemo.eww deleted file mode 100644 index 239a9381e..000000000 --- a/Demo/ARM9_STR91X_IAR/RTOSDemo.eww +++ /dev/null @@ -1,10 +0,0 @@ - - - - - $WS_DIR$\RTOSDemo.ewp - - - - - diff --git a/Demo/ARM9_STR91X_IAR/STCode/lcd.c b/Demo/ARM9_STR91X_IAR/STCode/lcd.c deleted file mode 100644 index 1d13b790f..000000000 --- a/Demo/ARM9_STR91X_IAR/STCode/lcd.c +++ /dev/null @@ -1,1424 +0,0 @@ -/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** -* File Name : lcd.c -* Author : MCD Application Team -* Date First Issued : 05/18/2006 : Version 1.0 -* Description : This file includes the LCD driver for GXM12232-2SL liquid -* Crystal Display Module of STR75x-EVAL. -******************************************************************************** -* History: -* 05/24/2006 : Version 1.1 -* 05/18/2006 : Version 1.0 -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -#include "91x_lib.h" -#include "lcd.h" -#include "FreeRTOS.h" -#include "task.h" - -/* Private typedef -----------------------------------------------------------*/ -static GPIO_InitTypeDef GPIO_InitStructure; - -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - /* Global variable to set the written text color: used for LCD_Printf */ - TextColorMode_TypeDef TextMode=BlackText; - - /* ASCII Table: each character is 7 column (7dots large) on two pages (16dots high) */ - /* 7 column character: Two 8bit data to display one column*/ - u8 AsciiDotsTable[1778] = { - /* ASCII 0 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 1 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 2 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 3 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 4 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 5 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 6 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 7 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 8 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 9 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - /* ASCII 10 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - /* ASCII 11 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 12 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 13 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - /* ASCII 14 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 15 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 16 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 17 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 18 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 19 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 20 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 21 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 22 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 23 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 24 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 25 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 26 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 27 */ 0x1f,0xe0,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x1f,0xe0,0x00,0x00, - /* ASCII 28 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - /* ASCII 29 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - /* ASCII 30 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - /* ASCII 31 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - /* ASCII 32 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - /* ASCII 33 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x13,0xe0,0x00,0x00,0x00,0x00,0x00,0x00, - /* ASCII 34 */ 0x00,0x00,0x00,0xe0,0x00,0x20,0x00,0x00,0x00,0xe0,0x00,0x20,0x00,0x00, - /* ASCII 35 */ 0x00,0x00,0x35,0x00,0x0f,0x80,0x35,0x60,0x0f,0x80,0x05,0x60,0x00,0x00, - /* ASCII 36 */ 0x00,0x00,0x0d,0x80,0x0a,0x40,0x3a,0x60,0x06,0x40,0x00,0x00,0x00,0x00, - /* ASCII 37 */ 0x00,0x00,0x02,0x40,0x02,0xa0,0x0a,0x40,0x15,0x00,0x09,0x00,0x00,0x00, - /* ASCII 38 */ 0x00,0x00,0x0c,0x00,0x13,0x00,0x14,0x80,0x08,0x80,0x14,0x00,0x00,0x00, - /* ASCII 39 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xe0,0x00,0x00,0x00,0x00,0x00,0x00, - /* ASCII 40 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x1f,0x80,0x60,0x60,0x00,0x00,0x00,0x00, - /* ASCII 41 */ 0x00,0x00,0x00,0x00,0x60,0x60,0x1f,0x80,0x00,0x00,0x00,0x00,0x00,0x00, - /* ASCII 42 */ 0x00,0x00,0x00,0x40,0x03,0x40,0x00,0xe0,0x03,0x40,0x00,0x40,0x00,0x00, - /* ASCII 43 */ 0x02,0x00,0x02,0x00,0x02,0x00,0x1f,0xc0,0x02,0x00,0x02,0x00,0x02,0x00, - /* ASCII 44 */ 0x00,0x00,0x00,0x00,0x60,0x00,0x38,0x00,0x08,0x00,0x00,0x00,0x00,0x00, - /* ASCII 45 */ 0x00,0x00,0x02,0x00,0x02,0x00,0x02,0x00,0x02,0x00,0x02,0x00,0x00,0x00, - /* ASCII 46 */ 0x00,0x00,0x00,0x00,0x18,0x00,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - /* ASCII 47 */ 0x00,0x00,0x20,0x00,0x18,0x00,0x06,0x00,0x01,0x80,0x00,0x60,0x00,0x00, - /* ASCII 48 */ 0x00,0x00,0x0f,0xc0,0x10,0x20,0x10,0x20,0x10,0x20,0x0f,0xc0,0x00,0x00, - /* ASCII 49 */ 0x00,0x00,0x10,0x00,0x10,0x20,0x1f,0xe0,0x10,0x00,0x10,0x00,0x00,0x00, - /* ASCII 50 */ 0x00,0x00,0x18,0x40,0x14,0x20,0x12,0x20,0x11,0x20,0x18,0xc0,0x00,0x00, - /* ASCII 51 */ 0x00,0x00,0x08,0x40,0x10,0x20,0x11,0x20,0x11,0x20,0x0e,0xc0,0x00,0x00, - /* ASCII 52 */ 0x00,0x00,0x06,0x00,0x05,0x00,0x04,0xc0,0x14,0x20,0x1f,0xe0,0x14,0x00, - /* ASCII 53 */ 0x00,0x00,0x08,0x00,0x11,0xe0,0x11,0x20,0x11,0x20,0x0e,0x20,0x00,0x00, - /* ASCII 54 */ 0x00,0x00,0x0f,0x80,0x11,0x40,0x11,0x20,0x11,0x20,0x0e,0x20,0x00,0x00, - /* ASCII 55 */ 0x00,0x00,0x00,0x60,0x00,0x20,0x18,0x20,0x07,0x20,0x00,0xe0,0x00,0x00, - /* ASCII 56 */ 0x00,0x00,0x0e,0xc0,0x11,0x20,0x11,0x20,0x11,0x20,0x0e,0xc0,0x00,0x00, - /* ASCII 57 */ 0x00,0x00,0x11,0xc0,0x12,0x20,0x12,0x20,0x0a,0x20,0x07,0xc0,0x00,0x00, - /* ASCII 58 */ 0x00,0x00,0x00,0x00,0x19,0x80,0x19,0x80,0x00,0x00,0x00,0x00,0x00,0x00, - /* ASCII 59 */ 0x00,0x00,0x00,0x00,0x30,0x00,0x19,0x80,0x09,0x80,0x00,0x00,0x00,0x00, - /* ASCII 60 */ 0x02,0x00,0x05,0x00,0x05,0x00,0x08,0x80,0x10,0x40,0x10,0x40,0x00,0x00, - /* ASCII 61 */ 0x00,0x00,0x05,0x00,0x05,0x00,0x05,0x00,0x05,0x00,0x05,0x00,0x00,0x00, - /* ASCII 62 */ 0x10,0x40,0x10,0x40,0x08,0x80,0x05,0x00,0x05,0x00,0x02,0x00,0x00,0x00, - /* ASCII 63 */ 0x00,0x00,0x00,0x00,0x10,0x80,0x14,0x40,0x02,0x40,0x01,0x80,0x00,0x00, - /* ASCII 64 */ 0x00,0x00,0x1f,0xe0,0x20,0x10,0x23,0x10,0x24,0x90,0x17,0xe0,0x00,0x00, - /* ASCII 65 */ 0x10,0x00,0x1c,0x00,0x17,0xa0,0x04,0x60,0x17,0x80,0x1c,0x00,0x10,0x00, - /* ASCII 66 */ 0x10,0x20,0x1f,0xe0,0x11,0x20,0x11,0x20,0x11,0x20,0x0e,0xc0,0x00,0x00, - /* ASCII 67 */ 0x00,0x00,0x0f,0xc0,0x10,0x20,0x10,0x20,0x10,0x20,0x08,0x60,0x00,0x00, - /* ASCII 68 */ 0x10,0x20,0x1f,0xe0,0x10,0x20,0x10,0x20,0x08,0x40,0x07,0x80,0x00,0x00, - /* ASCII 69 */ 0x10,0x20,0x1f,0xe0,0x11,0x20,0x13,0xa0,0x10,0x20,0x18,0x60,0x00,0x00, - /* ASCII 70 */ 0x00,0x00,0x10,0x20,0x1f,0xe0,0x11,0x20,0x03,0xa0,0x00,0x20,0x00,0x60, - /* ASCII 71 */ 0x00,0x00,0x0f,0xc0,0x10,0x20,0x10,0x20,0x12,0x20,0x0e,0x60,0x02,0x00, - /* ASCII 72 */ 0x10,0x20,0x1f,0xe0,0x11,0x20,0x01,0x00,0x11,0x20,0x1f,0xe0,0x10,0x20, - /* ASCII 73 */ 0x00,0x00,0x10,0x20,0x10,0x20,0x1f,0xe0,0x10,0x20,0x10,0x20,0x00,0x00, - /* ASCII 74 */ 0x00,0x00,0x0e,0x00,0x10,0x20,0x10,0x20,0x0f,0xe0,0x00,0x20,0x00,0x00, - /* ASCII 75 */ 0x10,0x20,0x1f,0xe0,0x12,0x20,0x03,0x00,0x04,0xa0,0x18,0x60,0x10,0x20, - /* ASCII 76 */ 0x00,0x00,0x10,0x20,0x1f,0xe0,0x10,0x20,0x10,0x00,0x1c,0x00,0x00,0x00, - /* ASCII 77 */ 0x10,0x20,0x1f,0xe0,0x10,0xe0,0x03,0x00,0x10,0xe0,0x1f,0xe0,0x10,0x20, - /* ASCII 78 */ 0x10,0x20,0x1f,0xe0,0x10,0xe0,0x07,0x00,0x18,0x20,0x1f,0xe0,0x00,0x20, - /* ASCII 79 */ 0x00,0x00,0x0f,0xc0,0x10,0x20,0x10,0x20,0x10,0x20,0x0f,0xc0,0x00,0x00, - /* ASCII 80 */ 0x00,0x00,0x10,0x20,0x1f,0xe0,0x12,0x20,0x02,0x20,0x01,0xc0,0x00,0x00, - /* ASCII 81 */ 0x00,0x00,0x0f,0xc0,0x10,0x20,0x30,0x20,0x30,0x20,0x2f,0xc0,0x00,0x00, - /* ASCII 82 */ 0x10,0x20,0x1f,0xe0,0x12,0x20,0x02,0x20,0x06,0x20,0x09,0xc0,0x10,0x00, - /* ASCII 83 */ 0x00,0x00,0x18,0xc0,0x09,0x20,0x11,0x20,0x11,0x40,0x0e,0x60,0x00,0x00, - /* ASCII 84 */ 0x00,0x60,0x00,0x20,0x10,0x20,0x1f,0xe0,0x10,0x20,0x00,0x20,0x00,0x60, - /* ASCII 85 */ 0x00,0x20,0x0f,0xe0,0x10,0x20,0x10,0x00,0x10,0x20,0x0f,0xe0,0x00,0x20, - /* ASCII 86 */ 0x00,0x20,0x00,0xe0,0x07,0x20,0x18,0x00,0x07,0x20,0x00,0xe0,0x00,0x20, - /* ASCII 87 */ 0x00,0x20,0x0f,0xe0,0x10,0x20,0x0f,0x00,0x10,0x20,0x0f,0xe0,0x00,0x20, - /* ASCII 88 */ 0x10,0x20,0x18,0x60,0x04,0x80,0x03,0x00,0x04,0x80,0x18,0x60,0x10,0x20, - /* ASCII 89 */ 0x00,0x20,0x00,0x60,0x11,0xa0,0x1e,0x00,0x11,0xa0,0x00,0x60,0x00,0x20, - /* ASCII 90 */ 0x00,0x00,0x18,0x60,0x14,0x20,0x13,0x20,0x10,0xa0,0x18,0x60,0x00,0x00, - /* ASCII 91 */ 0x00,0x00,0x00,0x00,0x7f,0xe0,0x40,0x20,0x40,0x20,0x00,0x00,0x00,0x00, - /* ASCII 92 */ 0x00,0x00,0x00,0x20,0x01,0xc0,0x06,0x00,0x38,0x00,0x00,0x00,0x00,0x00, - /* ASCII 93 */ 0x00,0x00,0x00,0x00,0x40,0x20,0x40,0x20,0x7f,0xe0,0x00,0x00,0x00,0x00, - /* ASCII 94 */ 0x00,0x00,0x01,0x00,0x00,0x80,0x00,0x60,0x00,0x80,0x01,0x00,0x00,0x00, - /* ASCII 95 */ 0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00, - /* ASCII 96 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x40,0x00,0x00,0x00,0x00, - /* ASCII 97 */ 0x00,0x00,0x0d,0x00,0x12,0x80,0x12,0x80,0x12,0x80,0x1f,0x00,0x10,0x00, - /* ASCII 98 */ 0x10,0x20,0x1f,0xe0,0x11,0x00,0x10,0x80,0x10,0x80,0x0f,0x00,0x00,0x00, - /* ASCII 99 */ 0x00,0x00,0x0f,0x00,0x10,0x80,0x10,0x80,0x10,0x80,0x09,0x80,0x00,0x00, - /* ASCII 100 */ 0x00,0x00,0x0f,0x00,0x10,0x80,0x10,0x80,0x11,0x20,0x1f,0xe0,0x10,0x00, - /* ASCII 101 */ 0x00,0x00,0x0f,0x00,0x12,0x80,0x12,0x80,0x12,0x80,0x13,0x00,0x00,0x00, - /* ASCII 102 */ 0x00,0x00,0x10,0x80,0x1f,0xc0,0x10,0xa0,0x10,0xa0,0x10,0xa0,0x00,0x00, - /* ASCII 103 */ 0x00,0x00,0x0f,0x00,0x50,0x80,0x50,0x80,0x51,0x00,0x3f,0x80,0x00,0x80, - /* ASCII 104 */ 0x10,0x20,0x1f,0xe0,0x11,0x00,0x00,0x80,0x10,0x80,0x1f,0x00,0x10,0x00, - /* ASCII 105 */ 0x00,0x00,0x10,0x80,0x10,0x80,0x1f,0xa0,0x10,0x00,0x10,0x00,0x00,0x00, - /* ASCII 106 */ 0x00,0x00,0x40,0x80,0x40,0x80,0x40,0xa0,0x3f,0x80,0x00,0x00,0x00,0x00, - /* ASCII 107 */ 0x10,0x20,0x1f,0xe0,0x02,0x00,0x16,0x80,0x19,0x80,0x10,0x80,0x00,0x00, - /* ASCII 108 */ 0x00,0x00,0x10,0x00,0x10,0x20,0x1f,0xe0,0x10,0x00,0x10,0x00,0x00,0x00, - /* ASCII 109 */ 0x10,0x80,0x1f,0x80,0x10,0x80,0x1f,0x00,0x10,0x80,0x1f,0x00,0x10,0x00, - /* ASCII 110 */ 0x10,0x80,0x1f,0x80,0x11,0x00,0x00,0x80,0x10,0x80,0x1f,0x00,0x10,0x00, - /* ASCII 111 */ 0x00,0x00,0x0f,0x00,0x10,0x80,0x10,0x80,0x10,0x80,0x0f,0x00,0x00,0x00, - /* ASCII 112 */ 0x40,0x80,0x7f,0x80,0x51,0x00,0x10,0x80,0x10,0x80,0x0f,0x00,0x00,0x00, - /* ASCII 113 */ 0x00,0x00,0x0f,0x00,0x10,0x80,0x10,0x80,0x51,0x00,0x7f,0x80,0x40,0x80, - /* ASCII 114 */ 0x00,0x00,0x10,0x80,0x1f,0x80,0x11,0x00,0x10,0x80,0x10,0x80,0x00,0x00, - /* ASCII 115 */ 0x00,0x00,0x19,0x00,0x12,0x80,0x12,0x80,0x12,0x80,0x0d,0x80,0x00,0x00, - /* ASCII 116 */ 0x00,0x00,0x00,0x80,0x0f,0xc0,0x10,0x80,0x10,0x80,0x10,0x80,0x08,0x00, - /* ASCII 117 */ 0x00,0x80,0x0f,0x80,0x10,0x00,0x10,0x00,0x08,0x80,0x1f,0x80,0x10,0x00, - /* ASCII 118 */ 0x00,0x80,0x03,0x80,0x0c,0x80,0x10,0x00,0x0c,0x80,0x03,0x80,0x00,0x80, - /* ASCII 119 */ 0x00,0x80,0x0f,0x80,0x10,0x80,0x0e,0x00,0x10,0x80,0x0f,0x80,0x00,0x80, - /* ASCII 120 */ 0x10,0x80,0x19,0x80,0x06,0x00,0x06,0x00,0x19,0x80,0x10,0x80,0x00,0x00, - /* ASCII 121 */ 0x00,0x80,0x41,0x80,0x46,0x80,0x78,0x00,0x4c,0x80,0x03,0x80,0x00,0x80, - /* ASCII 122 */ 0x00,0x00,0x19,0x80,0x14,0x80,0x12,0x80,0x11,0x80,0x18,0x80,0x00,0x00, - /* ASCII 123 */ 0x00,0x00,0x00,0x00,0x04,0x00,0x3b,0xc0,0x40,0x20,0x00,0x00,0x00,0x00, - /* ASCII 124 */ 0x00,0x00,0x00,0x00,0x00,0x00,0x3f,0xe0,0x00,0x00,0x00,0x00,0x00,0x00, - /* ASCII 125 */ 0x00,0x00,0x00,0x00,0x40,0x20,0x3b,0xc0,0x04,0x00,0x00,0x00,0x00,0x00, - /* ASCII 126 */ 0x00,0x00,0x04,0x00,0x02,0x00,0x04,0x00,0x04,0x00,0x02,0x00,0x00,0x00}; - -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/******************************************************************************* -* Function Name : LCD_DataLinesConfig -* Description : Configure data lines D0~D7 (P8.0~P8.7) in Input Floating mode -* for read from LCD or in Output Push-Pull mode for write on LCD -* Input : - Mode: specifies the configuration mode for data lines D0~D7 -* - Input: configure in Input Floating mode -* - Output: configure in Output Push-Pul mode -* Output : None -* Return : None -*******************************************************************************/ -void LCD_DataLinesConfig(DataConfigMode_TypeDef Mode) -{ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_All; - if (Mode == Input) - { - /* Configure D0~D7 lines (P8.0 ->P8.7) as Input */ - GPIO_InitStructure.GPIO_Direction = GPIO_PinInput; - } - else - { - /* Configure D0~D7 lines in Output Push-Pull mode */ - GPIO_InitStructure.GPIO_Direction = GPIO_PinOutput ; - GPIO_InitStructure.GPIO_Type = GPIO_Type_PushPull ; - } - GPIO_Init(GPIO8, &GPIO_InitStructure); -} - -/******************************************************************************* -* Function Name : LCD_DataLinesWrite -* Description : Write a value on D0~D7 (P8.0~P8.7) -* Input : - GPIOx: GPIO port to write on. It could be -* - PortVal: value to write -* Output : None -* Return : None. -*******************************************************************************/ -void LCD_DataLinesWrite(GPIO_TypeDef* GPIOx, u32 PortVal) -{ - GPIOx->DR[0x3FC] = PortVal; -} - -/******************************************************************************* -* Function Name : LCD_CtrlLinesConfig -* Description : Configure control lines E2, E1, RW, DI (P9.4~P9.7) in -* Output Push-Pull mode. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void LCD_CtrlLinesConfig(void) -{ - /* Configure E2, E1, RW, DI lines (P9.4~P9.7) in Output Push-Pull mode */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7; - GPIO_InitStructure.GPIO_Direction = GPIO_PinOutput ; - GPIO_InitStructure.GPIO_Type = GPIO_Type_PushPull ; - GPIO_Init(GPIO9, &GPIO_InitStructure); -} - -/******************************************************************************* -* Function Name : LCD_CtrlLinesWrite -* Description : Set or reset control lines E2, E1, RW, DI (P9.4~P9.7). -* Input : - GPIOx: where x can be 0,1 or 2 to select the GPIO peripheral. -* - CtrlPins: the Control line. This parameter can be: -* - CtrlPin_E2: Enabe clock signal for Slave -* - CtrlPin_E1: Enabe clock signal for Master -* - CtrlPin_RW: Read/Write control line -* - CtrlPin_DI: -* Output : None -* Return : None -*******************************************************************************/ -void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, u32 CtrlPins, BitAction BitVal) -{ - /* Set or Reset the control line */ - if(BitVal == Bit_SET) - { - GPIOx->DR[CtrlPins <<2] = CtrlPins; - } - else - { - GPIOx->DR[CtrlPins <<2] = 0x00; - } -} - -/******************************************************************************* -* Function Name : LCD_CheckMasterStatus -* Description : Check whether master LCD is busy or not -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void LCD_CheckMasterStatus(void) -{ - u8 MasterStatus = 0; - - /* Configure Data lines as Input */ - LCD_DataLinesConfig(Input); - /* Start the master read sequence */ - LCD_CtrlLinesWrite(GPIO9, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ - LCD_CtrlLinesWrite(GPIO9, CtrlPin_RW, Bit_SET); /* RW = 1 */ - LCD_CtrlLinesWrite(GPIO9, CtrlPin_DI, Bit_RESET); /* DI = 0 */ - LCD_CtrlLinesWrite(GPIO9, CtrlPin_E1, Bit_SET); /* E1 = 1 */ - MasterStatus = GPIO_Read(GPIO8); - LCD_CtrlLinesWrite(GPIO9, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ - - /* Wait until BF is cleared */ - while ((MasterStatus & 0x80)) - { - vTaskDelay( 2 ); - LCD_CtrlLinesWrite(GPIO9, CtrlPin_E1, Bit_SET); /* E1 = 1 */ - MasterStatus = GPIO_Read(GPIO8); - LCD_CtrlLinesWrite(GPIO9, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ - } -} - -/******************************************************************************* -* Function Name : LCD_CheckSlaveStatus -* Description : Check whether slave LCD is busy or not -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void LCD_CheckSlaveStatus(void) -{ - u8 SlaveStatus = 0; - - /* Configure Data lines as Input */ - LCD_DataLinesConfig(Input); - /* Start the slave read sequence */ - LCD_CtrlLinesWrite(GPIO9, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ - LCD_CtrlLinesWrite(GPIO9, CtrlPin_RW, Bit_SET); /* RW = 1 */ - LCD_CtrlLinesWrite(GPIO9, CtrlPin_DI, Bit_RESET); /* DI = 0 */ - LCD_CtrlLinesWrite(GPIO9, CtrlPin_E2, Bit_SET); /* E2 = 1 */ - SlaveStatus = GPIO_Read(GPIO8); - LCD_CtrlLinesWrite(GPIO9, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ - - /* Wait until BF is cleared */ - while ((SlaveStatus & 0x80)) - { - vTaskDelay( 2 ); - LCD_CtrlLinesWrite(GPIO9, CtrlPin_E2, Bit_SET); /* E2 = 1 */ - SlaveStatus = GPIO_Read(GPIO8); - LCD_CtrlLinesWrite(GPIO9, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ - } -} - -/******************************************************************************* -* Function Name : LCD_SendMasterCmd -* Description : Send one byte command to master LCD. -* Input : - Cmd: the user expected command to send to master LCD -* Output : None -* Return : None -*******************************************************************************/ -void LCD_SendMasterCmd(u8 Cmd) -{ - /* Check the master status */ - LCD_CheckMasterStatus(); - /* Configure Data lines as Output */ - LCD_DataLinesConfig(Output); - /* Start the master send command sequence */ - LCD_CtrlLinesWrite(GPIO9, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ - LCD_CtrlLinesWrite(GPIO9, CtrlPin_RW, Bit_RESET); /* RW = 0 */ - LCD_CtrlLinesWrite(GPIO9, CtrlPin_DI, Bit_RESET); /* DI = 0 */ - LCD_CtrlLinesWrite(GPIO9, CtrlPin_E1, Bit_SET); /* E1 = 1 */ - /* Write master command */ - LCD_DataLinesWrite(GPIO8, (u32)Cmd); - LCD_CtrlLinesWrite(GPIO9, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ -} - -/******************************************************************************* -* Function Name : LCD_SendSlaveCmd -* Description : Send one byte command to slave LCD -* Input : - Cmd: the user expected command to send to slave LCD. -* Output : None -* Return : None -*******************************************************************************/ -void LCD_SendSlaveCmd(u8 Cmd) -{ - /* Check the slave status */ - LCD_CheckSlaveStatus(); - /* Configure Data lines as Output */ - LCD_DataLinesConfig(Output); - /* Start the slave send command sequence */ - LCD_CtrlLinesWrite(GPIO9, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ - LCD_CtrlLinesWrite(GPIO9, CtrlPin_RW, Bit_RESET); /* RW = 0 */ - LCD_CtrlLinesWrite(GPIO9, CtrlPin_DI, Bit_RESET); /* DI = 0 */ - LCD_CtrlLinesWrite(GPIO9, CtrlPin_E2, Bit_SET); /* E2 = 1 */ - /* Write slave command */ - LCD_DataLinesWrite(GPIO8, (u32)Cmd); - LCD_CtrlLinesWrite(GPIO9, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ -} - -/******************************************************************************* -* Function Name : LCD_SendMasterData -* Description : Display one byte data to master LCD. -* Input : - Data: the user expected data to display on master LCD. -* Output : None -* Return : None -*******************************************************************************/ -void LCD_SendMasterData(u8 Data) -{ - /* Check the master status */ - LCD_CheckMasterStatus(); - /* Configure Data lines as Output */ - LCD_DataLinesConfig(Output); - /* Start the master send data sequence */ - LCD_CtrlLinesWrite(GPIO9, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ - LCD_CtrlLinesWrite(GPIO9, CtrlPin_RW, Bit_RESET); /* RW = 0 */ - LCD_CtrlLinesWrite(GPIO9, CtrlPin_DI, Bit_SET); /* DI = 1 */ - LCD_CtrlLinesWrite(GPIO9, CtrlPin_E1, Bit_SET); /* E1 = 1 */ - /* Write data to the master */ - LCD_DataLinesWrite(GPIO8, (u32)Data); - LCD_CtrlLinesWrite(GPIO9, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ -} - -/******************************************************************************* -* Function Name : LCD_ReadMasterData -* Description : Read master byte data displayed on master LCD. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -u32 LCD_ReadMasterData(void) -{ - u32 MasterData = 0; - - /* Check the master status */ - LCD_CheckMasterStatus(); - /* Configure Data lines as Input */ - LCD_DataLinesConfig(Input); - /* Start the master read data sequence */ - LCD_CtrlLinesWrite(GPIO9, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ - LCD_CtrlLinesWrite(GPIO9, CtrlPin_RW, Bit_SET); /* RW = 1 */ - LCD_CtrlLinesWrite(GPIO9, CtrlPin_DI, Bit_SET); /* DI = 1 */ - LCD_CtrlLinesWrite(GPIO9, CtrlPin_E1, Bit_SET); /* E1 = 1 */ - /* Read data from the master */ - MasterData = (GPIO_Read(GPIO8)); - LCD_CtrlLinesWrite(GPIO9, CtrlPin_E1, Bit_RESET); /* E1 = 0 */ - /* Read the master returned data */ - return MasterData; -} - -/******************************************************************************* -* Function Name : LCD_SendSlaveData -* Description : Display one byte data to slave LCD. -* Input : - Data: the user expected data to display on slave LCD. -* Output : None -* Return : None -*******************************************************************************/ -void LCD_SendSlaveData(u8 Data) -{ - /* Check the slave status */ - LCD_CheckSlaveStatus(); - /* Configure Data lines as Output */ - LCD_DataLinesConfig(Output); - /* Start the slave send data sequence */ - LCD_CtrlLinesWrite(GPIO9, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ - LCD_CtrlLinesWrite(GPIO9, CtrlPin_RW, Bit_RESET); /* RW = 0 */ - LCD_CtrlLinesWrite(GPIO9, CtrlPin_DI, Bit_SET); /* DI = 1 */ - LCD_CtrlLinesWrite(GPIO9, CtrlPin_E2, Bit_SET); /* E2 = 1 */ - /* Write data to the slave */ - LCD_DataLinesWrite(GPIO8, (u32)Data); - LCD_CtrlLinesWrite(GPIO9, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ -} - -/******************************************************************************* -* Function Name : LCD_ReadSlaveData -* Description : Read slave byte data displayed on slave LCD. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -u32 LCD_ReadSlaveData(void) -{ - u32 SlaveData = 0; - - /* Check the slave status */ - LCD_CheckSlaveStatus(); - /* Configure Data lines as Input */ - LCD_DataLinesConfig(Input); - /* Start the slave read data sequence */ - LCD_CtrlLinesWrite(GPIO9, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ - LCD_CtrlLinesWrite(GPIO9, CtrlPin_RW, Bit_SET); /* RW = 1 */ - LCD_CtrlLinesWrite(GPIO9, CtrlPin_DI, Bit_SET); /* DI = 1 */ - LCD_CtrlLinesWrite(GPIO9, CtrlPin_E2, Bit_SET); /* E2 = 1 */ - /* Read data from the slave */ - SlaveData = GPIO_Read(GPIO8); - LCD_CtrlLinesWrite(GPIO9, CtrlPin_E2, Bit_RESET); /* E2 = 0 */ - /* Read the slave returned data */ - return SlaveData; -} - -/******************************************************************************* -* Function Name : LCD_Init -* Description : Initialize master and slave LCD. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void LCD_Init(void) -{ - /* Enable GPIO Clock */ - - - /* Configure control lines signals as output mode */ - LCD_CtrlLinesConfig(); - - /* Master LCD Init */ - LCD_SendMasterCmd(SOFTWARE_RESET); - LCD_SendMasterCmd(DISPLAY_OFF); - LCD_SendMasterCmd(DYNAMIC_DRIVE); - LCD_SendMasterCmd(DUTY_CYCLE); - LCD_SendMasterCmd(CLOCKWISE_OUTPUT); - LCD_SendMasterCmd(READ_MODIFY_WRITE_OFF); - LCD_SendMasterCmd(START_COLUMN); /* Set master column address to 0 */ - LCD_SendMasterCmd(START_LINE); /* Set master display start line to 0 */ - LCD_SendMasterCmd(DISPLAY_ON ); - - /* Slave LCD Init */ - LCD_SendSlaveCmd(SOFTWARE_RESET); - LCD_SendSlaveCmd(DISPLAY_OFF); - LCD_SendSlaveCmd(DYNAMIC_DRIVE); - LCD_SendSlaveCmd(DUTY_CYCLE); - LCD_SendSlaveCmd(CLOCKWISE_OUTPUT); - LCD_SendSlaveCmd(READ_MODIFY_WRITE_OFF); - LCD_SendSlaveCmd(START_COLUMN ); /* Set slave column address to 0 */ - LCD_SendSlaveCmd(START_LINE); /* Set slave display start line to 0 */ - LCD_SendSlaveCmd(DISPLAY_ON); - - /* Clear LCD */ - LCD_Clear(); - /* Set current Page to 0 for Master and Slave LCDs */ - LCD_SetSlavePage(0); - LCD_SetMasterPage(0); -} - -/******************************************************************************* -* Function Name : LCD_SetSlavePage -* Description : Set the display page of slave LCD, the page range is 0 to 3, -* make sure the input will not exceed this range ,otherwise it -* will reach a undecided result. -* Input : - Page: specifies the expected display page of slave LCD -* Output : None -* Return : None -*******************************************************************************/ -void LCD_SetSlavePage(u8 Page) -{ -static u8 ucLastPage = 255; - - /* Set Slave page */ - if( Page != ucLastPage ) - { - LCD_SendSlaveCmd(0xB8|Page); - ucLastPage = Page; - } -} - -/******************************************************************************* -* Function Name : LCD_SetMasterPage -* Description : Set the display page of master LCD, the page range is 0 to 3, -* make sure the input will not exceed this range ,otherwise it -* will reach a undecided result. -* Input : - Page: specifies the expected display page of master LCD -* Output : None -* Return : None -*******************************************************************************/ -void LCD_SetMasterPage(u8 Page) -{ -static u8 ulLastPage = 255; - - /* Set Master page */ - if( Page != ulLastPage ) - { - LCD_SendMasterCmd(0xB8|Page); - ulLastPage = Page; - } -} - -/******************************************************************************* -* Function Name : SetAddress -* Description : Set the display column of slave LCD. Column range is 0 to 61. -* Input : - Address: specifies the expected display column of slave LCD -* Output : None -* Return : None -*******************************************************************************/ -void LCD_SetSlaveColumn(u8 Address) -{ - /* Set Slave column address */ - LCD_SendSlaveCmd(Address&0x7F); -} - -/******************************************************************************* -* Function Name : LCD_SetMasterColumn -* Description : Set the display column of master LCD. Column range is 0 to 61. -* Input : - Address: specifies the expected display column of slave LCD -* Output : None -* Return : None -*******************************************************************************/ -void LCD_SetMasterColumn(u8 Address) -{ - /* Set Master column address */ - LCD_SendMasterCmd(Address&0x7F); -} - -/******************************************************************************* -* Function Name : LCD_SetTextColor -* Description : Set the text color for LCD. -* Input : - TextColor: BlackText: character on black, bottom on white. -* WhiteText: character on white, bottom on black. -* Output : None -* Return : None -*******************************************************************************/ -void LCD_SetTextColor(TextColorMode_TypeDef TextColor) -{ - if(TextColor) - { - /* Set White Text color */ - TextMode=WhiteText; - } - else - { - /* Set Black Text color */ - TextMode=BlackText; - } -} - -/******************************************************************************* -* Function Name : LCD_Clear -* Description : Clear the Master and Slave LCDs display. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void LCD_Clear(void) -{ - u8 Page = 0, Column = 0; - - /* Clear master and slave LCDs page by page */ - for (Page=0; Page<4; Page++) - { - /* Set master and slave page by page */ - LCD_SetMasterPage(Page); - LCD_SetSlavePage(Page); - /* Set master and slave column address */ - LCD_SetMasterColumn(0); - LCD_SetSlaveColumn(0); - /* Send empty data to master and slave column address on the selected page */ - for (Column=0; Column<61; Column++) - { - LCD_SendSlaveData(0); - LCD_SendMasterData(0); - } - } -} - -/******************************************************************************* -* Function Name : LCD_ClearLine -* Description : Clear the selected line of the LCD. -* Input : - Line: the Line to clear. -* - Line1 (Page0&1): clear the first line -* - Line2 (Page2&3): clear the second line -* Output : None -* Return : None -*******************************************************************************/ -void LCD_ClearLine(u8 Line) -{ - u8 Page = 0, Column = 0; - - /* Clear the slected master and slave line */ - for (Page=Line; Page 121) - { - /* Return if column exceeded 121 */ - return; - } - if (X > 60) - { - /* To be displayed on slave LCD (Window = 1) */ - Window = 1; - /* Get the Slave relative start column */ -// ActualColumn = X%61; - ActualColumn = X - 61; - } - else - { - /* To be displayed on master LCD (Window = 0) */ - ActualColumn = X; - } - - /* Switch window, display the character upper part */ - if (Window) - { - /* Display it on slave LCD */ - LCD_SetSlavePage(Line); - LCD_SetSlaveColumn(ActualColumn); - LCD_SendSlaveData(Bmp[i]); - } - else - { - /* Display it on master LCD */ - LCD_SetMasterPage(Line); - LCD_SetMasterColumn(ActualColumn); - LCD_SendMasterData(Bmp[i]); - } - /* Switch window, diplay the character lower part */ - if (Window) - { - /* Display it on slave LCD */ - LCD_SetSlavePage(Line+1); - LCD_SetSlaveColumn(ActualColumn); - LCD_SendSlaveData(Bmp[i+1]); - } - else - { - /* Display it on master LCD */ - LCD_SetMasterPage(Line+1); - LCD_SetMasterColumn(ActualColumn); - LCD_SendMasterData(Bmp[i+1]); - } - /* Increment by 2 the character table index */ - i+=2; - } -} - -/******************************************************************************* -* Function Name : LCD_DisplayChar -* Description : Display one character (7dots large, 16dots high). -* Note: -* the LCD can only display two line character,so page 0 and 1 -* is to display the first line, page2 and page 3 is to display -* the second line. -* Input : - Line: the Line where to display the character. -* - Line1 (Page0&1): display character on the first line -* - Line2 (Page2&3): display character on the second line -* - Column: start column address. -* - Ascii: character ascii code. -* - CharMode: BlackText: character on black, bottom on white. -* WhiteText: character on white, bottom on black. -* Output : None -* Return : None -*******************************************************************************/ -void LCD_DisplayChar(u8 Line, u8 Column, u8 Ascii, TextColorMode_TypeDef CharMode) -{ - u8 DotBuffer[14], i = 0; - - /* Display the character lower and upper 8bit parts (2*7columns) */ - for (i=0;i<14;i++) - { - /* Character displayed as white Text on black buttom */ - if(CharMode) - { - if( i & 0x01 ) - { - DotBuffer[i] = ~AsciiDotsTable[Ascii*14+i-1]; - } - else - { - DotBuffer[i] = ~AsciiDotsTable[Ascii*14+i+1]; - } - } - /* Character displayed as black Text on white buttom */ - else - { - if( ( u8 ) i & 0x01 ) - { - DotBuffer[i] = AsciiDotsTable[Ascii*14+i-1]; - } - else - { - DotBuffer[i] = AsciiDotsTable[Ascii*14+i+1]; - } - } - } - /* Display the asc code after conversion */ - LCD_DrawChar(Line, Column, 7, DotBuffer); -} - -/******************************************************************************* -* Function Name : LCD_HexToAsciiLow -* Description : This function is used to convert the low nibble of an -* unsigned byte (0-F hex) to ASCII. -* Input : - byte: byte to convert to ASCII. -* Output : None -* Return : ASCII value result of the conversion. -*******************************************************************************/ -char LCD_HexToAsciiLow(u8 byte) -{ - /* Keep lower nibble only */ - byte = byte & 0x0F; - /* If the ascii is a number */ - if (byte <= 0x09) - { - /* Add 0x30 to its ascii */ - return(byte + 0x30); - } - else - { - /* Add 0x37 to its ascii */ - return (byte + 0x37); - } -} - -/******************************************************************************* -* Function Name : LCD_HexToAsciiHigh -* Description : This function is used to convert the high nibble of an -* unsigned byte (0-F hex) to ASCII. -* Input : - byte: byte to convert to ASCII. -* Output : None -* Return : ASCII value result of the conversion. -*******************************************************************************/ -char LCD_HexToAsciiHigh(u8 byte) -{ - /* Keep upper nibble only */ - byte = byte & 0xF0; - byte = byte >> 4; - /* If the ascii is a number */ - if (byte <= 0x09) - { - /* Add 0x30 to display its ascii */ - return(byte + 0x30); - } - else - { - /* Add 0x37 to display its ascii */ - return (byte + 0x37); - } -} - -/******************************************************************************* -* Function Name : LCD_DisplayString -* Description : This function is used to display a 17char max string of -* characters on the LCD display on the selected line. -* Note: -* this function is the user interface to use the LCD driver. -* Input : - *ptr: pointer to string to display on LCD. -* - Line: the Line where to display the character. -* - Line1 (Page0&1): display character on the first line -* - Line2 (Page2&3): display character on the second line -* Output : None -* Return : None -*******************************************************************************/ -void LCD_DisplayString(u8 Line, u8 *ptr, TextColorMode_TypeDef CharMode) -{ - u8 RefColumn = 0, i = 0; - - /* Send the string character by character on lCD */ - while ((*ptr!=0)&(i<17)) - { - if( *ptr == ' ' ) - { - if( ptr[1] == ' ') - { - vTaskDelay( 3 ); - } - else - { - vTaskDelay( 16 ); - } - } - - if( *ptr == '.' ) - { - vTaskDelay( 16 ); - } - - /* Display one character on LCD */ - LCD_DisplayChar(Line, RefColumn, *ptr, CharMode); - - /* Increment the column position by 7 */ - RefColumn+=7; - /* Point on the next character */ - ptr++; - /* Increment the character counter */ - i++; - /* If we reach the maximum Line character */ - if(i==17) - { - LCD_DisplayChar(Line, RefColumn-1, 0x1f, CharMode); /* Add missed columns */ - } - } -} - -/******************************************************************************* -* Function Name : LCD_Printf -* Description : This function is used to display a string of characters -* on the LCD display. -* Note: -* this function is the user interface to use the LCD driver. -* Input : - *ptr: pointer to string to display on LCD. -* Output : None -* Return : None -*******************************************************************************/ -void LCD_Printf(u8 *ptr, ...) -{ - u8 RefColumn = 0, RefPage = 0, i = 0, c1 = 0; - u16 var = 0, c2 = 0, c3 = 0, c4 = 0, c5 = 0; - u32 WordVar = 0; - - /* Store pointer on LCD_Printf second parameter (String) */ - u8 *var_ptr=(u8 *)(&ptr+1); - - /* Send String */ - while (*ptr != 0) - { - c1 = *ptr; - /* Limited to AsciiDotsTable code table */ - if(c1 <= 128) - { - /* Carriage return */ - if ( *ptr == '\r') - { - ptr++; - RefColumn = 0; - } - /* Jump to Line2 */ - else if( *ptr == '\n') - { - /* Point on the string to display */ - ptr++; - /* Clear Line2 */ - LCD_ClearLine(Line2); - /* Point on first Line2 column */ - RefColumn = 0; - /* Increment RefPage by 2 */ - RefPage+=2; - } - /* Display value on the passed format */ - else if( *ptr == '%') - { - ptr++; - /* Display decimal value */ - if (*ptr == 'd') - { - ptr++; - /* Get the word value to display */ - WordVar = ((*var_ptr)|(*(var_ptr+1)<<8)|(*(var_ptr+2)<<16)); - c1=WordVar/10000; - c2=(WordVar%10000)/1000; - c3=(WordVar%1000)/100; - c4=(WordVar%100)/10; - c5=(WordVar%10); - /* Display the ten miles digit */ - if (c1!=0) - { - LCD_DisplayChar(RefPage, RefColumn, c1+0x30, TextMode); - RefColumn+=7; - } - /* Display the miles digit */ - if (!((c1==0)&(c2==0))) - { - LCD_DisplayChar(RefPage, RefColumn, c2+0x30, TextMode); - RefColumn+=7; - } - /* Display the hundred digit */ - if (!((c1==0)&(c2==0)&(c3==0))) - { - LCD_DisplayChar(RefPage, RefColumn, c3+0x30, TextMode); - RefColumn+=7; - } - /* Display the tens digit */ - if (!((c1==0)&(c2==0)&(c3==0)&(c4==0))) - { - LCD_DisplayChar(RefPage, RefColumn, c4+0x30, TextMode); - RefColumn+=7; - } - /* Display the rest */ - LCD_DisplayChar(RefPage, RefColumn, c5+0x30, TextMode); - RefColumn+=7; - } - /* Display 16bits Hex value */ - else if (*ptr == 'x') - { - ptr++; - /* Display 8bits MSB */ - var_ptr = var_ptr +1; - var = *var_ptr; - c1 = LCD_HexToAsciiHigh(var); - LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); - RefColumn+=7; - c1 = LCD_HexToAsciiLow(var); - LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); - RefColumn+=7; - /* Display 8bits LSB */ - var_ptr = var_ptr -1; - var = *var_ptr; - var_ptr = var_ptr +4; - c1 = LCD_HexToAsciiHigh(var); - LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); - RefColumn+=7; - c1 = LCD_HexToAsciiLow(var); - LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); - RefColumn+=7; - } - /* Display 32bits Hex value */ - else if (*ptr == 'w') - { - ptr++; - /* Display 16bits MSB */ - var_ptr = var_ptr +3; - var = *var_ptr; - c1 = LCD_HexToAsciiHigh(var); - LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); - RefColumn+=7; - c1 = LCD_HexToAsciiLow(var); - LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); - RefColumn+=7; - var_ptr = var_ptr -1; - var = *var_ptr; - c1 = LCD_HexToAsciiHigh(var); - LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); - RefColumn+=7; - c1 = LCD_HexToAsciiLow(var); - LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); - RefColumn+=7; - /* Display 16bits LSB */ - var_ptr = var_ptr -1; - var = *var_ptr; - var_ptr = var_ptr +4; - c1 = LCD_HexToAsciiHigh(var); - LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); - RefColumn+=7; - c1 = LCD_HexToAsciiLow(var); - LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); - RefColumn+=7; - var_ptr = var_ptr -5; - var = *var_ptr; - var_ptr = var_ptr +4; - c1 = LCD_HexToAsciiHigh(var); - LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); - RefColumn+=7; - c1 = LCD_HexToAsciiLow(var); - LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); - RefColumn+=7; - } - else - { - /* Display '%' character which is followed by (d, x or w) */ - ptr--; - c1 = *ptr; - LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); - RefColumn+=7; - ptr++; - i++; - if(i==17) - { - /* Add missed columns */ - LCD_DisplayChar(RefPage, RefColumn-1, 0x1f, TextMode); - RefColumn = 0; - RefPage+=2; - } - } - } - else - { - /* Display characters different from (\r, \n, %) */ - LCD_DisplayChar(RefPage, RefColumn, c1, TextMode); - RefColumn+=7; - ptr++; - i++; - if(i==17) - { - /* Add missed columns */ - LCD_DisplayChar(RefPage, RefColumn-1, 0x1f, TextMode); - LCD_ClearLine(Line2); - RefColumn = 0; - RefPage+=2; - } - } - } - } - /* Display spaces if string doesn't reach the max LCD characters size */ - while(RefColumn<119) - { - /* Display Spaces */ - LCD_DisplayChar(RefPage, RefColumn, 0x20, TextMode); - RefColumn+=7; - /* Add missed columns */ - LCD_DisplayChar(RefPage, RefColumn, 0x1f, TextMode); - } -} - -/******************************************************************************* -* Function Name : LCD_DrawMasterGraphic -* Description : Draw a Graphic image on master LCD. -* Input : - Bmp: the pointer of the dot matrix data. -* Output : None -* Return : None. -*******************************************************************************/ -void LCD_DrawMasterGraphic(u8 *Bmp) -{ - u8 j = 0, k = 0, ActPage = 0; - - /* Draw graphic on master: 61 Column *4 Pages */ - while(j<244) - { - /* Draw on master page by page */ - LCD_SetMasterPage(ActPage); - for(k=0; k<61; k++) - { - LCD_SetMasterColumn(k); - LCD_SendMasterData(*Bmp++); - j++; - } - ActPage++; - } -} - -/******************************************************************************* -* Function Name : LCD_DrawSlaveGraphic -* Description : Draw a Graphic image on slave LCD. -* Input : - Bmp: the pointer of the dot matrix data. -* Output : None -* Return : None. -*******************************************************************************/ -void LCD_DrawSlaveGraphic(u8 *Bmp) -{ - u8 j = 0, k = 0, ActPage = 0; - - /* Draw graphic on slave: 61 Column *4 Pages */ - while(j<244) - { - /* Draw on slave page by page */ - LCD_SetSlavePage(ActPage); - for(k=0; k<61; k++) - { - LCD_SetSlaveColumn(k); - LCD_SendSlaveData(*Bmp++); - j++; - } - ActPage++; - } -} - -/******************************************************************************* -* Function Name : LCD_DrawGraphic -* Description : Draw a Graphic image on LCD. -* Input : - Bmp: the pointer of the dot matrix data. -* Output : None -* Return : None. -*******************************************************************************/ -void LCD_DrawGraphic(u8 *Bmp) -{ - u8 Pos = 0, ActPage = 0; - u16 j = 0, k = 0; - - /* Draw graphic on LCD: 122 Column *4 Pages */ - while(j<488) - { - if(!Pos) - { - /* Draw on master page by page */ - LCD_SetMasterPage(ActPage); - for(k=0; k<61; k++) - { - LCD_SetMasterColumn(k); - LCD_SendMasterData(*Bmp++); - j++; - } - Pos=1; - } - else - { - /* Draw on slave page by page */ - LCD_SetSlavePage(ActPage); - for(k=0; k<61; k++) - { - LCD_SetSlaveColumn(k); - LCD_SendSlaveData(*Bmp++); - j++; - } - ActPage++; - Pos=0; - } - } -} - -/******************************************************************************* -* Function Name : LCD_ScrollGraphic -* Description : Scroll a Graphic image on LCD. -* Input : - Bmp: the pointer of the dot matrix data. -* - nCount: specifies the delay time length. -* Output : None -* Return : None. -*******************************************************************************/ -void LCD_ScrollGraphic(u8 *Bmp, u32 nCount) -{ - u8 Pos = 0, ActPage = 0; - u16 j = 0, k = 0; - u32 Counter = 0; - - /* Draw graphic on LCD: 122 Column *4 Pages */ - while(j<488) - { - if(!Pos) - { - /* Draw on master page by page */ - LCD_SetMasterPage(ActPage); - for(k=0; k<61; k++) - { - LCD_SetMasterColumn(k); - LCD_SendMasterData(*Bmp++); - Counter = nCount; - /* Set a delay */ - for(; Counter != 0; Counter--); - j++; - } - Pos=1; - } - else - { - /* Draw on slave page by page */ - LCD_SetSlavePage(ActPage); - for(k=0; k<61; k++) - { - LCD_SetSlaveColumn(k); - Counter = nCount; - /* Set a delay */ - for(; Counter != 0; Counter--); - LCD_SendSlaveData(*Bmp++); - j++; - } - ActPage++; - Pos=0; - } - } -} - -/******************************************************************************* -* Function Name : LCD_DrawPixel -* Description : Draw a Graphic image on slave LCD. -* Input : - XPos: the dot line number of the pixel. -* - 1->61 : displayed on master LCD -* - 62->122: displayed on slave LCD -* - YPos: column address of the pixel from 1->32. -* - Mode: Dot_On: Pixel turned on (black). -* Dot_Off: Pixel turned off (black). -* Output : None -* Return : None. -*******************************************************************************/ -void LCD_DrawPixel(u8 XPos, u8 YPos, DotMode_TypeDef Mode) -{ - u8 Page = 0, Position = 0; - u16 Mask = 0; - u32 MasterDataIn = 0, MasterDataOut = 0, SlaveDataIn = 0, SlaveDataOut = 0; - - /* Pixel page */ - Page = (XPos-1)/8; - /* Pixel column */ - Position = (YPos-1)/61; /* 0:Master, 1:Slave */ - /* Mask for the pixel */ - Mask= 1<<((XPos-1)%8); - /* If Position=0 draw pixel on master LCD */ - if(!Position) - { - LCD_SetMasterPage(Page); - LCD_SetMasterColumn(YPos-1); - MasterDataIn = LCD_ReadMasterData(); - MasterDataIn = LCD_ReadMasterData(); - LCD_SetMasterColumn(YPos-1); - if(Mode==Dot_On) - { - MasterDataOut = MasterDataIn | Mask; - } - else - { - MasterDataOut = MasterDataIn & (~Mask); - } - LCD_SendMasterData(MasterDataOut); - } - /* If Position=1 draw pixel on slave LCD */ - else - { - LCD_SetSlavePage(Page); - LCD_SetSlaveColumn(YPos-62); - SlaveDataIn = LCD_ReadSlaveData(); - SlaveDataIn = LCD_ReadSlaveData(); - LCD_SetSlaveColumn(YPos-62); - if(Mode==Dot_On) - { - SlaveDataOut = SlaveDataIn | Mask; - } - else - { - SlaveDataOut = SlaveDataIn & (~Mask); - } - LCD_SendSlaveData(SlaveDataOut); - } -} - -/******************************************************************************* -* Function Name : LCD_DrawLine -* Description : Draw a line on master and slave LCDs. -* Input : - XPos1: the dot line number of the source point . -* - XPos2: the dot line number of the destination point . -* - YPos1: the dot column number of the source point. -* - YPos2: the dot column number of the destination point. -* Output : None -* Return : None. -*******************************************************************************/ -void LCD_DrawLine(u8 XPos1, u8 YPos1, u8 XPos2, u8 YPos2) -{ - u8 XPos = 0, YPos = 0; - - /* Use XPos1, YPos1, XPos2 and YPos2 */ - if((XPos2>=XPos1)&(YPos2>=YPos1)) - { - for(XPos=XPos1; XPos<=XPos2; XPos++) - { - for(YPos=YPos1; YPos<=YPos2; YPos++) - { - LCD_DrawPixel(XPos, YPos, Dot_On); - } - } - } - else if((XPos2=YPos1)) - { - for(XPos=XPos2; XPos<=XPos1; XPos++) - { - for(YPos=YPos1; YPos<=YPos2; YPos++) - { - LCD_DrawPixel(XPos, YPos, Dot_On); - } - } - } - else if((XPos2>=XPos1)&(YPos2 -;* : -s -;************************************************************************************* -;* History: -;* 09/27/2005 : V1.0 -;************************************************************************************* -; THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT -; OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT -; OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION -; CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -;*************************************************************************************/ - -// Code memory in flash --DROMSTART=0x00000000 --DROMEND=0x00080000 --DVECSTART=ROMSTART - -// Data memory --DRAMSTART=0x4000000 --DRAMEND=0x04018000 - - -//************************************************************************* -// In this file it is assumed that the system has the following -// memory layout: -// -// Exception vectors [0x000000--0x00001F] RAM or ROM -// ROMSTART--ROMEND [0x008000--0x0FFFFF] ROM (or other non-volatile memory) -// RAMSTART--RAMEND [0x100000--0x7FFFFF] RAM (or other read/write memory) -// -// ------------- -// Code segments - may be placed anywhere in memory. -// ------------- -// -// INTVEC -- Exception vector table. -// SWITAB -- Software interrupt vector table. -// ICODE -- Startup (cstartup) and exception code. -// DIFUNCT -- Dynamic initialization vectors used by C++. -// CODE -- Compiler generated code. -// CODE_I -- Compiler generated code declared __ramfunc (executes in RAM) -// CODE_ID -- Initializer for CODE_I (ROM). -// -// ------------- -// Data segments - may be placed anywhere in memory. -// ------------- -// -// CSTACK -- The stack used by C/C++ programs (system and user mode). -// IRQ_STACK -- The stack used by IRQ service routines. -// SVC_STACK -- The stack used in supervisor mode -// (Define other exception stacks as needed for -// FIQ, ABT, UND). -// HEAP -- The heap used by malloc and free in C and new and -// delete in C++. -// INITTAB -- Table containing addresses and sizes of segments that -// need to be initialized at startup (by cstartup). -// CHECKSUM -- The linker places checksum byte(s) in this segment, -// when the -J linker command line option is used. -// DATA_y -- Data objects. -// -// Where _y can be one of: -// -// _AN -- Holds uninitialized located objects, i.e. objects with -// an absolute location given by the @ operator or the -// #pragma location directive. Since these segments -// contain objects which already have a fixed address, -// they should not be mentioned in this linker command -// file. -// _C -- Constants (ROM). -// _I -- Initialized data (RAM). -// _ID -- The original content of _I (copied to _I by cstartup) (ROM). -// _N -- Uninitialized data (RAM). -// _Z -- Zero initialized data (RAM). -// -// Note: Be sure to use end values for the defined address ranges. -// Otherwise, the linker may allocate space outside the -// intended memory range. -//************************************************************************* - - -//************************************************ -// Inform the linker about the CPU family used. -//************************************************ - --carm - -//************************************************************************* -// Segment placement - General information -// -// All numbers in the segment placement command lines below are interpreted -// as hexadecimal unless they are immediately preceded by a '.', which -// denotes decimal notation. -// -// When specifying the segment placement using the -P instead of the -Z -// option, the linker is free to split each segment into its segment parts -// and randomly place these parts within the given ranges in order to -// achieve a more efficient memory usage. One disadvantage, however, is -// that it is not possible to find the start or end address (using -// the assembler operators .sfb./.sfe.) of a segment which has been split -// and reformed. -// -// When generating an output file which is to be used for programming -// external ROM/Flash devices, the -M linker option is very useful -// (see xlink.pdf for details). -//************************************************************************* - - -//************************************************************************* -// Read-only segments mapped to ROM. -//************************************************************************* - -//************************************************ -// Address range for reset and exception -// vectors (INTVEC). -// The vector area is 32 bytes, -// an additional 32 bytes is allocated for the -// constant table used by ldr PC in cstartup.s79. -//************************************************ - --Z(CODE)INTVEC=ROMSTART-ROMEND - -//************************************************ -// Startup code and exception routines (ICODE). -//************************************************ - --Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND --Z(CODE)SWITAB=ROMSTART-ROMEND - -//************************************************ -// Code segments may be placed anywhere. -//************************************************ - --Z(CODE)CODE=ROMSTART-ROMEND - -//************************************************ -// Original ROM location for __ramfunc code copied -// to and executed from RAM. -//************************************************ - --Z(CONST)CODE_ID=ROMSTART-ROMEND - -//************************************************ -// Various constants and initializers. -//************************************************ - --Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND --Z(CONST)CHECKSUM=ROMSTART-ROMEND - - -//************************************************************************* -// Read/write segments mapped to RAM. -//************************************************************************* - -//************************************************ -// Data segments. -//************************************************ - --Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND - -//************************************************ -// __ramfunc code copied to and executed from RAM. -//************************************************ - --Z(DATA)CODE_I=RAMSTART-RAMEND - -//************************************************ -// ICCARM produces code for __ramfunc functions in -// CODE_I segments. The -Q XLINK command line -// option redirects XLINK to emit the code in the -// CODE_ID segment instead, but to keep symbol and -// debug information associated with the CODE_I -// segment, where the code will execute. -//************************************************ - --QCODE_I=CODE_ID - -//************************************************************************* -// Stack and heap segments. -//************************************************************************* - -//-D_CSTACK_SIZE=0x1000 -//-D_SVC_STACK_SIZE=0x100 -//-D_IRQ_STACK_SIZE=0x400 -//-D_FIQ_STACK_SIZE=0x40 -//-D_ABT_STACK_SIZE=0x40 -//-D_UND_STACK_SIZE=0x40 -//-D_HEAP_SIZE=0x400 - -//-Z(DATA)CSTACK+_CSTACK_SIZE=RAMSTART-RAMEND -//-Z(DATA)SVC_STACK+_SVC_STACK_SIZE=RAMSTART-RAMEND -//-Z(DATA)ABT_STACK+_ABT_STACK_SIZE=RAMSTART-RAMEND -//-Z(DATA)UND_STACK+_UND_STACK_SIZE=RAMSTART-RAMEND -//-Z(DATA)FIQ_STACK+_FIQ_STACK_SIZE=RAMSTART-RAMEND -//-Z(DATA)IRQ_STACK+_IRQ_STACK_SIZE=RAMSTART-RAMEND -//-Z(DATA)HEAP+_HEAP_SIZE=RAMSTART-RAMEND - -//************************************************************************* -// ELF/DWARF support. -// -// Uncomment the line "-Felf" below to generate ELF/DWARF output. -// Available format specifiers are: -// -// "-yn": Suppress DWARF debug output -// "-yp": Multiple ELF program sections -// "-yas": Format suitable for debuggers from ARM Ltd (also sets -p flag) -// -// "-Felf" and the format specifiers can also be supplied directly as -// command line options, or selected from the Xlink Output tab in the -// IAR Embedded Workbench. -//************************************************************************* - -// -Felf diff --git a/Demo/ARM9_STR91X_IAR/main.c b/Demo/ARM9_STR91X_IAR/main.c deleted file mode 100644 index f14d2c138..000000000 --- a/Demo/ARM9_STR91X_IAR/main.c +++ /dev/null @@ -1,417 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. - The processor MUST be in supervisor mode when vTaskStartScheduler is - called. The demo applications included in the FreeRTOS.org download switch - to supervisor mode prior to main being called. If you are not using one of - these demo application projects then ensure Supervisor mode is used. -*/ - -/* - * Creates all the demo application tasks, then starts the scheduler. The WEB - * documentation provides more details of the demo application tasks. - * - * A few tasks are created that are not part of the standard demo. These are - * the 'LCD' task, the 'LCD Message' task, a WEB server task and the 'Check' - * task. - * - * The LCD task is the only task that accesses the LCD directly, so mutual - * exclusion is ensured. Any task wishing to display text sends the LCD task - * a message containing a pointer to the string that should be displayed. - * The LCD task itself just blocks on a queue waiting for such a message to - * arrive - processing each in turn. - * - * The LCD Message task does nothing other than periodically send messages to - * the LCD task. The messages originating from the LCD Message task are - * displayed on the top row of the LCD. - * - * The Check task only executes every three seconds but has the highest - * priority so is guaranteed to get processor time. Its main function is to - * check that all the other tasks are still operational. Most tasks maintain - * a unique count that is incremented each time the task successfully completes - * a cycle of its function. Should any error occur within such a task the - * count is permanently halted. The check task sets a bit in an error status - * flag should it find any counter variable at a value that indicates an - * error has occurred. The error flag value is converted to a string and sent - * to the LCD task for display on the bottom row on the LCD. - */ - -/* Standard includes. */ -#include - -/* Library includes. */ -#include "91x_lib.h" - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" - -/* Demo application includes. */ -#include "lcd.h" -#include "flash.h" -#include "integer.h" -#include "PollQ.h" -#include "BlockQ.h" -#include "semtest.h" -#include "dynamic.h" -#include "partest.h" -#include "flop.h" -#include "comtest2.h" -#include "serial.h" - -/* Priorities for the demo application tasks. */ -#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainMSG_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) - -/* Delays used by the various tasks defined in this file. */ -#define mainCHECK_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS ) -#define mainSTRING_WRITE_DELAY ( 500 / portTICK_RATE_MS ) -#define mainLCD_DELAY ( 20 / portTICK_RATE_MS ) - -/* Constants for the ComTest tasks. */ -#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 115200 ) -#define mainCOM_TEST_LED ( 3 ) - -/* The maximum number of messages that can be pending to be written to the LCD. */ -#define mainLCD_QUEUE_LEN ( 6 ) - -/* Dimension the buffer used to write the error flag string. */ -#define mainMAX_FLAG_STRING_LEN ( 32 ) - -/* The structure that is passed on the LCD message queue. */ -typedef struct -{ - portCHAR **ppcMessageToDisplay; /*<< Points to a char* pointing to the message to display. */ - portBASE_TYPE xRow; /*<< The row on which the message should be displayed. */ -} xLCDMessage; -/*-----------------------------------------------------------*/ - -/* - * The task that executes at the highest priority and calls - * prvCheckOtherTasksAreStillRunning(). See the description at the top - * of the file. - */ -static void vErrorChecks( void *pvParameters ); - -/* - * Configure the processor clock and ports. - */ -static void prvSetupHardware( void ); - -/* - * Checks that all the demo application tasks are still executing without error - * - as described at the top of the file. Called by vErrorChecks(). - */ -static void prvCheckOtherTasksAreStillRunning( void ); - -/* - * The WEB server task prototype. The task is created in this file but defined - * elsewhere. - */ -extern void vuIP_Task(void *pvParameters); - -/* - * The task that displays text on the LCD. - */ -static void prvLCDTask( void * pvParameters ); - -/* - * The task that sends messages to be displayed on the top row of the LCD. - */ -static void prvLCDMessageTask( void * pvParameters ); - -/*-----------------------------------------------------------*/ - -/* The queue used to pass messages to the LCD task. */ -static xQueueHandle xLCDQueue; - -/* Error status flag. */ -static unsigned portLONG ulErrorFlags = 0; - -/*-----------------------------------------------------------*/ - -/* - * Starts all the other tasks, then starts the scheduler. - */ -void main( void ) -{ - #ifdef DEBUG - debug(); - #endif - - /* Setup any hardware that has not already been configured by the low - level init routines. */ - prvSetupHardware(); - - /* Create the queue used to send data to the LCD task. */ - xLCDQueue = xQueueCreate( mainLCD_QUEUE_LEN, sizeof( xLCDMessage ) ); - - /* Start all the standard demo application tasks. */ - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - vStartDynamicPriorityTasks(); - vStartMathTasks( tskIDLE_PRIORITY ); - vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); - - /* Start the tasks which are defined in this file. */ - xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - xTaskCreate( prvLCDTask, "LCD", configMINIMAL_STACK_SIZE, ( void * ) &xLCDQueue, mainLCD_TASK_PRIORITY, NULL ); - xTaskCreate( prvLCDMessageTask, "MSG", configMINIMAL_STACK_SIZE, ( void * ) &xLCDQueue, mainMSG_TASK_PRIORITY, NULL ); - - /* Finally, create the WEB server task. */ - xTaskCreate( vuIP_Task, "uIP", configMINIMAL_STACK_SIZE * 3, NULL, mainCHECK_TASK_PRIORITY - 1, NULL ); - - - /* Start the scheduler. - - NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. - The processor MUST be in supervisor mode when vTaskStartScheduler is - called. The demo applications included in the FreeRTOS.org download switch - to supervisor mode prior to main being called. If you are not using one of - these demo application projects then ensure Supervisor mode is used here. */ - - vTaskStartScheduler(); - - /* We should never get here as control is now taken by the scheduler. */ - for( ;; ); -} -/*-----------------------------------------------------------*/ - -static void prvSetupHardware( void ) -{ - /* Configuration taken from the ST code. - - Set Flash banks size & address */ - FMI_BankRemapConfig( 4, 2, 0, 0x80000 ); - - /* FMI Waite States */ - FMI_Config( FMI_READ_WAIT_STATE_2, FMI_WRITE_WAIT_STATE_0, FMI_PWD_ENABLE, FMI_LVD_ENABLE, FMI_FREQ_HIGH ); - - /* Configure the FPLL = 96MHz, and APB to 48MHz. */ - SCU_PCLKDivisorConfig( SCU_PCLK_Div2 ); - SCU_PLLFactorsConfig( 192, 25, 2 ); - SCU_PLLCmd( ENABLE ); - SCU_MCLKSourceConfig( SCU_MCLK_PLL ); - - WDG_Cmd( DISABLE ); - VIC_DeInit(); - - /* GPIO8 clock source enable, used by the LCD. */ - SCU_APBPeriphClockConfig(__GPIO8, ENABLE); - GPIO_DeInit(GPIO8); - - /* GPIO 9 clock source enable, used by the LCD. */ - SCU_APBPeriphClockConfig(__GPIO9, ENABLE); - GPIO_DeInit(GPIO9); - - /* Enable VIC clock */ - SCU_AHBPeriphClockConfig(__VIC, ENABLE); - SCU_AHBPeriphReset(__VIC, DISABLE); - - /* Peripheral initialisation. */ - LCD_Init(); - vParTestInitialise(); -} -/*-----------------------------------------------------------*/ - -static void vErrorChecks( void *pvParameters ) -{ -static portCHAR cCheckVal[ mainMAX_FLAG_STRING_LEN ]; -portCHAR *pcFlagString; -xLCDMessage xMessageToSend; -portTickType xLastWakeTime; -portCHAR *pcStringsToDisplay[] = { - "Check status flag" - }; - - /* The parameters are not used in this task. */ - ( void ) pvParameters; - pcFlagString = &cCheckVal[ 0 ]; - - - /* Initialise xLastWakeTime to ensure the first call to vTaskDelayUntil() - functions correctly. */ - xLastWakeTime = xTaskGetTickCount(); - - /* Cycle for ever, delaying then checking all the other tasks are still - operating without error. */ - - for( ;; ) - { - /* Delay until it is time to execute again. */ - vTaskDelayUntil( &xLastWakeTime, mainCHECK_PERIOD ); - - /* Check all the other tasks to see if the error flag needs updating. */ - prvCheckOtherTasksAreStillRunning(); - - /* Create a string indicating the error flag status. */ - sprintf( cCheckVal, "equals 0x%x ", ulErrorFlags ); - xMessageToSend.xRow = Line2; - - /* Send the first part of the message to the LCD task. */ - xMessageToSend.ppcMessageToDisplay = &pcStringsToDisplay[ 0 ]; - xQueueSend( xLCDQueue, ( void * ) &xMessageToSend, 0 ); - vTaskDelay( mainSTRING_WRITE_DELAY ); - - /* Send the second part of the message to the LCD task. */ - xMessageToSend.ppcMessageToDisplay = &pcFlagString; - xQueueSend( xLCDQueue, ( void * ) &xMessageToSend, 0 ); - } -} -/*-----------------------------------------------------------*/ - -static void prvCheckOtherTasksAreStillRunning( void ) -{ - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - ulErrorFlags |= 0x01; - } - - if( xArePollingQueuesStillRunning() != pdTRUE ) - { - ulErrorFlags |= 0x02; - } - - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - ulErrorFlags |= 0x04; - } - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - ulErrorFlags |= 0x08; - } - - if( xAreComTestTasksStillRunning() != pdTRUE ) - { - ulErrorFlags |= 0x10; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - ulErrorFlags |= 0x20; - } - - if( xAreMathsTaskStillRunning() != pdTRUE ) - { - ulErrorFlags |= 0x40; - } -} -/*-----------------------------------------------------------*/ - -static void prvLCDMessageTask( void * pvParameters ) -{ -xQueueHandle *pxLCDQueue; -xLCDMessage xMessageToSend; -portBASE_TYPE xIndex = 0; - -/* The strings that are written to the LCD. */ -portCHAR *pcStringsToDisplay[] = { - "IAR ", - "STR912 ", - "Demo ", - "www.FreeRTOS.org", - "" - }; - - - /* To test the parameter passing mechanism, the queue on which messages are - posted is passed in as a parameter even though it is available as a file - scope variable anyway. */ - pxLCDQueue = ( xQueueHandle * ) pvParameters; - - for( ;; ) - { - /* Wait until it is time to move onto the next string. */ - vTaskDelay( mainSTRING_WRITE_DELAY ); - - /* Configure the message object to send to the LCD task. */ - xMessageToSend.ppcMessageToDisplay = &pcStringsToDisplay[ xIndex ]; - xMessageToSend.xRow = Line1; - - /* Post the message to be displayed. */ - xQueueSend( *pxLCDQueue, ( void * ) &xMessageToSend, 0 ); - - /* Move onto the next message, wrapping when necessary. */ - xIndex++; - if( *( pcStringsToDisplay[ xIndex ] ) == 0x00 ) - { - xIndex = 0; - - /* Delay longer before going back to the start of the messages. */ - vTaskDelay( mainSTRING_WRITE_DELAY * 2 ); - } - } -} -/*-----------------------------------------------------------*/ - -void prvLCDTask( void * pvParameters ) -{ -xQueueHandle *pxLCDQueue; -xLCDMessage xReceivedMessage; -portCHAR *pcString; - - /* To test the parameter passing mechanism, the queue on which messages are - received is passed in as a parameter even though it is available as a file - scope variable anyway. */ - pxLCDQueue = ( xQueueHandle * ) pvParameters; - - for( ;; ) - { - /* Wait for a message to arrive. */ - if( xQueueReceive( *pxLCDQueue, &xReceivedMessage, portMAX_DELAY ) ) - { - /* Where is the string we are going to display? */ - pcString = *xReceivedMessage.ppcMessageToDisplay; - LCD_DisplayString(xReceivedMessage.xRow, pcString, BlackText); - - /* The delay here is just to ensure the LCD task does not starve - out lower priority tasks as writhing to the LCD can take a long - time. */ - vTaskDelay( mainLCD_DELAY ); - } - } -} -/*-----------------------------------------------------------*/ - diff --git a/Demo/ARM9_STR91X_IAR/serial/serial.c b/Demo/ARM9_STR91X_IAR/serial/serial.c deleted file mode 100644 index 18f173807..000000000 --- a/Demo/ARM9_STR91X_IAR/serial/serial.c +++ /dev/null @@ -1,289 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART1. -*/ - -/* Library includes. */ -#include "91x_lib.h" - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "queue.h" -#include "semphr.h" - -/* Demo application includes. */ -#include "serial.h" -/*-----------------------------------------------------------*/ - -/* Misc defines. */ -#define serINVALID_QUEUE ( ( xQueueHandle ) 0 ) -#define serNO_BLOCK ( ( portTickType ) 0 ) -#define serTX_BLOCK_TIME ( 40 / portTICK_RATE_MS ) - -/* Interrupt and status bit definitions. */ -#define mainTXRIS 0x20 -#define mainRXRIS 0x50 -#define serTX_FIFO_FULL 0x20 -#define serCLEAR_ALL_INTERRUPTS 0x3ff -/*-----------------------------------------------------------*/ - -/* The queue used to hold received characters. */ -static xQueueHandle xRxedChars; - -/* The semaphore used to wake a task waiting for space to become available -in the FIFO. */ -static xSemaphoreHandle xTxFIFOSemaphore; - -/*-----------------------------------------------------------*/ - -/* UART interrupt handler. */ -void UART1_IRQHandler( void ); - -/* The interrupt service routine - called from the assembly entry point. */ -__arm void UART1_IRQHandler( void ); - -/*-----------------------------------------------------------*/ - -/* Flag to indicate whether or not a task is blocked waiting for space on -the FIFO. */ -static portLONG lTaskWaiting = pdFALSE; - -/* - * See the serial2.h header file. - */ -xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) -{ -xComPortHandle xReturn; -UART_InitTypeDef xUART1_Init; -GPIO_InitTypeDef GPIO_InitStructure; - - /* Create the queues used to hold Rx characters. */ - xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); - - /* Create the semaphore used to wake a task waiting for space to become - available in the FIFO. */ - vSemaphoreCreateBinary( xTxFIFOSemaphore ); - - /* If the queue/semaphore was created correctly then setup the serial port - hardware. */ - if( ( xRxedChars != serINVALID_QUEUE ) && ( xTxFIFOSemaphore != serINVALID_QUEUE ) ) - { - /* Pre take the semaphore so a task will block if it tries to access - it. */ - xSemaphoreTake( xTxFIFOSemaphore, 0 ); - - /* Configure the UART. */ - xUART1_Init.UART_WordLength = UART_WordLength_8D; - xUART1_Init.UART_StopBits = UART_StopBits_1; - xUART1_Init.UART_Parity = UART_Parity_No; - xUART1_Init.UART_BaudRate = ulWantedBaud; - xUART1_Init.UART_HardwareFlowControl = UART_HardwareFlowControl_None; - xUART1_Init.UART_Mode = UART_Mode_Tx_Rx; - xUART1_Init.UART_FIFO = UART_FIFO_Enable; - - /* Enable the UART1 Clock */ - SCU_APBPeriphClockConfig( __UART1, ENABLE ); - - /* Enable the GPIO3 Clock */ - SCU_APBPeriphClockConfig( __GPIO3, ENABLE ); - - /* Configure UART1_Rx pin GPIO3.2 */ - GPIO_InitStructure.GPIO_Direction = GPIO_PinInput; - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; - GPIO_InitStructure.GPIO_Type = GPIO_Type_PushPull ; - GPIO_InitStructure.GPIO_IPConnected = GPIO_IPConnected_Enable; - GPIO_InitStructure.GPIO_Alternate = GPIO_InputAlt1 ; - GPIO_Init( GPIO3, &GPIO_InitStructure ); - - /* Configure UART1_Tx pin GPIO3.3 */ - GPIO_InitStructure.GPIO_Direction = GPIO_PinOutput; - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3; - GPIO_InitStructure.GPIO_Type = GPIO_Type_PushPull ; - GPIO_InitStructure.GPIO_IPConnected = GPIO_IPConnected_Enable; - GPIO_InitStructure.GPIO_Alternate = GPIO_OutputAlt2 ; - GPIO_Init( GPIO3, &GPIO_InitStructure ); - - - portENTER_CRITICAL(); - { - /* Configure the UART itself. */ - UART_DeInit( UART1 ); - UART_Init( UART1, &xUART1_Init ); - UART_ITConfig( UART1, UART_IT_Receive | UART_IT_Transmit, ENABLE ); - UART1->ICR = serCLEAR_ALL_INTERRUPTS; - UART_LoopBackConfig( UART1, DISABLE ); - UART_IrDACmd( IrDA1, DISABLE ); - - /* Configure the VIC for the UART interrupts. */ - VIC_Config( UART1_ITLine, VIC_IRQ, 9 ); - VIC_ITCmd( UART1_ITLine, ENABLE ); - - UART_Cmd( UART1, ENABLE ); - lTaskWaiting = pdFALSE; - } - portEXIT_CRITICAL(); - } - else - { - xReturn = ( xComPortHandle ) 0; - } - - /* This demo file only supports a single port but we have to return - something to comply with the standard demo header file. */ - return xReturn; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) -{ - /* The port handle is not required as this driver only supports one port. */ - ( void ) pxPort; - - /* Get the next character from the buffer. Return false if no characters - are available, or arrive before xBlockTime expires. */ - if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) - { - return pdTRUE; - } - else - { - return pdFALSE; - } -} -/*-----------------------------------------------------------*/ - -void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength ) -{ -signed portCHAR *pxNext; - - /* A couple of parameters that this port does not use. */ - ( void ) usStringLength; - ( void ) pxPort; - - /* NOTE: This implementation does not handle the queue being full as no - block time is used! */ - - /* The port handle is not required as this driver only supports UART1. */ - ( void ) pxPort; - - /* Send each character in the string, one at a time. */ - pxNext = ( signed portCHAR * ) pcString; - while( *pxNext ) - { - xSerialPutChar( pxPort, *pxNext, serNO_BLOCK ); - pxNext++; - } -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) -{ -portBASE_TYPE xReturn; - - portENTER_CRITICAL(); - { - /* Can we write to the FIFO? */ - if( UART1->FR & serTX_FIFO_FULL ) - { - /* Wait for the interrupt letting us know there is space on the - FIFO. It is ok to block in a critical section, interrupts will be - enabled for other tasks once we force a switch. */ - lTaskWaiting = pdTRUE; - - /* Just to be a bit different this driver uses a semaphore to - block the sending task when the FIFO is full. The standard COMTest - task assumes a queue of adequate length exists so does not use - a block time. For this demo the block time is therefore hard - coded. */ - xReturn = xSemaphoreTake( xTxFIFOSemaphore, serTX_BLOCK_TIME ); - if( xReturn ) - { - UART1->DR = cOutChar; - } - } - else - { - UART1->DR = cOutChar; - xReturn = pdPASS; - } - } - portEXIT_CRITICAL(); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -void vSerialClose( xComPortHandle xPort ) -{ - /* Not supported as not required by the demo application. */ -} -/*-----------------------------------------------------------*/ - -void UART1_IRQHandler( void ) -{ -signed portCHAR cChar; -portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByPost = pdFALSE; - - while( UART1->RIS & mainRXRIS ) - { - /* The interrupt was caused by a character being received. Grab the - character from the DR and place it in the queue of received - characters. */ - cChar = UART1->DR; - xTaskWokenByPost = xQueueSendFromISR( xRxedChars, &cChar, xTaskWokenByPost ); - } - - if( UART1->RIS & mainTXRIS ) - { - if( lTaskWaiting == pdTRUE ) - { - /* This interrupt was caused by space becoming available on the Tx - FIFO, wake any task that is waiting to post (if any). */ - xTaskWokenByTx = xSemaphoreGiveFromISR( xTxFIFOSemaphore, xTaskWokenByTx ); - lTaskWaiting = pdFALSE; - } - - UART1->ICR = mainTXRIS; - } - - /* If a task was woken by either a character being received or a character - being transmitted then we may need to switch to another task. */ - portEND_SWITCHING_ISR( ( xTaskWokenByPost || xTaskWokenByTx ) ); -} - - - - - - diff --git a/Demo/ARM9_STR91X_IAR/settings/FreeRTOS.wsdt b/Demo/ARM9_STR91X_IAR/settings/FreeRTOS.wsdt deleted file mode 100644 index c72818da9..000000000 --- a/Demo/ARM9_STR91X_IAR/settings/FreeRTOS.wsdt +++ /dev/null @@ -1,63 +0,0 @@ - - - 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- - - - - - iaridepm1debuggergui1-2-2728279-2-2200194142857199588200714751029-2-21981402-2-214042001002857205761142857205761 - - - - diff --git a/Demo/ARM9_STR91X_IAR/settings/RTOSDemo.dni b/Demo/ARM9_STR91X_IAR/settings/RTOSDemo.dni deleted file mode 100644 index 6c72d9eb4..000000000 --- a/Demo/ARM9_STR91X_IAR/settings/RTOSDemo.dni +++ /dev/null @@ -1,21 +0,0 @@ -[DisAssemblyWindow] -NumStates=_ 1 -State 1=_ 1 -[JLinkDriver] -WatchCond=_ 0 -Watch0=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 -Watch1=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 -[Log file] -LoggingEnabled=_ 0 -LogFile=_ "" -Category=_ 0 -[TermIOLog] -LoggingEnabled=_ 0 -LogFile=_ "" -[Disassemble mode] -mode=2 -[Breakpoints] -Count=0 -[TraceHelper] -Enabled=0 -ShowSource=1 diff --git a/Demo/ARM9_STR91X_IAR/settings/RTOSDemo.wsdt b/Demo/ARM9_STR91X_IAR/settings/RTOSDemo.wsdt deleted file mode 100644 index ab941bd4f..000000000 --- a/Demo/ARM9_STR91X_IAR/settings/RTOSDemo.wsdt +++ /dev/null @@ -1,66 +0,0 @@ - - - - - - RTOSDemo/THUMB - - - - - - - - - 236272727 - - - - - - - 20100426766 - - - - - - - - TabID-5518-19908 - Workspace - Workspace - - - RTOSDemoRTOSDemo/Demo Source - - - - 0 - - - TabID-22895-20401 - Build - Build - - - - - 0 - - - - - - TextEditorC:\E\Dev\FreeRTOS\Demo\ARM9_STR91X_IAR\webserver\uIP_Task.c0019131925TextEditorC:\E\Dev\FreeRTOS\Demo\ARM9_STR91X_IAR\main.c0272708338210100000010000001 - - - - - - - iaridepm1-2-2363310-2-2200200142857205761222857751029-2-21981402-2-214042001002857205761142857205761 - - - - diff --git a/Demo/ARM9_STR91X_IAR/webserver/Makefile.webserver b/Demo/ARM9_STR91X_IAR/webserver/Makefile.webserver deleted file mode 100644 index f38c47a72..000000000 --- a/Demo/ARM9_STR91X_IAR/webserver/Makefile.webserver +++ /dev/null @@ -1 +0,0 @@ -APP_SOURCES += httpd.c http-strings.c httpd-fs.c httpd-cgi.c diff --git a/Demo/ARM9_STR91X_IAR/webserver/clock-arch.h b/Demo/ARM9_STR91X_IAR/webserver/clock-arch.h deleted file mode 100644 index cde657b62..000000000 --- a/Demo/ARM9_STR91X_IAR/webserver/clock-arch.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (c) 2006, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack - * - * $Id: clock-arch.h,v 1.2 2006/06/12 08:00:31 adam Exp $ - */ - -#ifndef __CLOCK_ARCH_H__ -#define __CLOCK_ARCH_H__ - -#include "FreeRTOS.h" - -typedef unsigned long clock_time_t; -#define CLOCK_CONF_SECOND configTICK_RATE_HZ - -#endif /* __CLOCK_ARCH_H__ */ diff --git a/Demo/ARM9_STR91X_IAR/webserver/http-strings b/Demo/ARM9_STR91X_IAR/webserver/http-strings deleted file mode 100644 index 0d3c30cdd..000000000 --- a/Demo/ARM9_STR91X_IAR/webserver/http-strings +++ /dev/null @@ -1,35 +0,0 @@ -http_http "http://" -http_200 "200 " -http_301 "301 " -http_302 "302 " -http_get "GET " -http_10 "HTTP/1.0" -http_11 "HTTP/1.1" -http_content_type "content-type: " -http_texthtml "text/html" -http_location "location: " -http_host "host: " -http_crnl "\r\n" -http_index_html "/index.html" -http_404_html "/404.html" -http_referer "Referer:" -http_header_200 "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" -http_header_404 "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" -http_content_type_plain "Content-type: text/plain\r\n\r\n" -http_content_type_html "Content-type: text/html\r\n\r\n" -http_content_type_css "Content-type: text/css\r\n\r\n" -http_content_type_text "Content-type: text/text\r\n\r\n" -http_content_type_png "Content-type: image/png\r\n\r\n" -http_content_type_gif "Content-type: image/gif\r\n\r\n" -http_content_type_jpg "Content-type: image/jpeg\r\n\r\n" -http_content_type_binary "Content-type: application/octet-stream\r\n\r\n" -http_html ".html" -http_shtml ".shtml" -http_htm ".htm" -http_css ".css" -http_png ".png" -http_gif ".gif" -http_jpg ".jpg" -http_text ".txt" -http_txt ".txt" - diff --git a/Demo/ARM9_STR91X_IAR/webserver/http-strings.c b/Demo/ARM9_STR91X_IAR/webserver/http-strings.c deleted file mode 100644 index ef7a41c7d..000000000 --- a/Demo/ARM9_STR91X_IAR/webserver/http-strings.c +++ /dev/null @@ -1,102 +0,0 @@ -const char http_http[8] = -/* "http://" */ -{0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, }; -const char http_200[5] = -/* "200 " */ -{0x32, 0x30, 0x30, 0x20, }; -const char http_301[5] = -/* "301 " */ -{0x33, 0x30, 0x31, 0x20, }; -const char http_302[5] = -/* "302 " */ -{0x33, 0x30, 0x32, 0x20, }; -const char http_get[5] = -/* "GET " */ -{0x47, 0x45, 0x54, 0x20, }; -const char http_10[9] = -/* "HTTP/1.0" */ -{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, }; -const char http_11[9] = -/* "HTTP/1.1" */ -{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x31, }; -const char http_content_type[15] = -/* "content-type: " */ -{0x63, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, }; -const char http_texthtml[10] = -/* "text/html" */ -{0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, }; -const char http_location[11] = -/* "location: " */ -{0x6c, 0x6f, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, }; -const char http_host[7] = -/* "host: " */ -{0x68, 0x6f, 0x73, 0x74, 0x3a, 0x20, }; -const char http_crnl[3] = -/* "\r\n" */ -{0xd, 0xa, }; -const char http_index_html[12] = -/* "/index.html" */ -{0x2f, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x68, 0x74, 0x6d, 0x6c, }; -const char http_404_html[10] = -/* "/404.html" */ -{0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, }; -const char http_referer[9] = -/* "Referer:" */ -{0x52, 0x65, 0x66, 0x65, 0x72, 0x65, 0x72, 0x3a, }; -const char http_header_200[84] = -/* "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */ -{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x32, 0x30, 0x30, 0x20, 0x4f, 0x4b, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, }; -const char http_header_404[91] = -/* "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */ -{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x34, 0x30, 0x34, 0x20, 0x4e, 0x6f, 0x74, 0x20, 0x66, 0x6f, 0x75, 0x6e, 0x64, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, }; -const char http_content_type_plain[29] = -/* "Content-type: text/plain\r\n\r\n" */ -{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x70, 0x6c, 0x61, 0x69, 0x6e, 0xd, 0xa, 0xd, 0xa, }; -const char http_content_type_html[28] = -/* "Content-type: text/html\r\n\r\n" */ -{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0xd, 0xa, 0xd, 0xa, }; -const char http_content_type_css [27] = -/* "Content-type: text/css\r\n\r\n" */ -{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x63, 0x73, 0x73, 0xd, 0xa, 0xd, 0xa, }; -const char http_content_type_text[28] = -/* "Content-type: text/text\r\n\r\n" */ -{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x74, 0x65, 0x78, 0x74, 0xd, 0xa, 0xd, 0xa, }; -const char http_content_type_png [28] = -/* "Content-type: image/png\r\n\r\n" */ -{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x70, 0x6e, 0x67, 0xd, 0xa, 0xd, 0xa, }; -const char http_content_type_gif [28] = -/* "Content-type: image/gif\r\n\r\n" */ -{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x67, 0x69, 0x66, 0xd, 0xa, 0xd, 0xa, }; -const char http_content_type_jpg [29] = -/* "Content-type: image/jpeg\r\n\r\n" */ -{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x6a, 0x70, 0x65, 0x67, 0xd, 0xa, 0xd, 0xa, }; -const char http_content_type_binary[43] = -/* "Content-type: application/octet-stream\r\n\r\n" */ -{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x2f, 0x6f, 0x63, 0x74, 0x65, 0x74, 0x2d, 0x73, 0x74, 0x72, 0x65, 0x61, 0x6d, 0xd, 0xa, 0xd, 0xa, }; -const char http_html[6] = -/* ".html" */ -{0x2e, 0x68, 0x74, 0x6d, 0x6c, }; -const char http_shtml[7] = -/* ".shtml" */ -{0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, }; -const char http_htm[5] = -/* ".htm" */ -{0x2e, 0x68, 0x74, 0x6d, }; -const char http_css[5] = -/* ".css" */ -{0x2e, 0x63, 0x73, 0x73, }; -const char http_png[5] = -/* ".png" */ -{0x2e, 0x70, 0x6e, 0x67, }; -const char http_gif[5] = -/* ".gif" */ -{0x2e, 0x67, 0x69, 0x66, }; -const char http_jpg[5] = -/* ".jpg" */ -{0x2e, 0x6a, 0x70, 0x67, }; -const char http_text[5] = -/* ".txt" */ -{0x2e, 0x74, 0x78, 0x74, }; -const char http_txt[5] = -/* ".txt" */ -{0x2e, 0x74, 0x78, 0x74, }; diff --git a/Demo/ARM9_STR91X_IAR/webserver/http-strings.h b/Demo/ARM9_STR91X_IAR/webserver/http-strings.h deleted file mode 100644 index acbe7e17f..000000000 --- a/Demo/ARM9_STR91X_IAR/webserver/http-strings.h +++ /dev/null @@ -1,34 +0,0 @@ -extern const char http_http[8]; -extern const char http_200[5]; -extern const char http_301[5]; -extern const char http_302[5]; -extern const char http_get[5]; -extern const char http_10[9]; -extern const char http_11[9]; -extern const char http_content_type[15]; -extern const char http_texthtml[10]; -extern const char http_location[11]; -extern const char http_host[7]; -extern const char http_crnl[3]; -extern const char http_index_html[12]; -extern const char http_404_html[10]; -extern const char http_referer[9]; -extern const char http_header_200[84]; -extern const char http_header_404[91]; -extern const char http_content_type_plain[29]; -extern const char http_content_type_html[28]; -extern const char http_content_type_css [27]; -extern const char http_content_type_text[28]; -extern const char http_content_type_png [28]; -extern const char http_content_type_gif [28]; -extern const char http_content_type_jpg [29]; -extern const char http_content_type_binary[43]; -extern const char http_html[6]; -extern const char http_shtml[7]; -extern const char http_htm[5]; -extern const char http_css[5]; -extern const char http_png[5]; -extern const char http_gif[5]; -extern const char http_jpg[5]; -extern const char http_text[5]; -extern const char http_txt[5]; diff --git a/Demo/ARM9_STR91X_IAR/webserver/httpd-cgi.c b/Demo/ARM9_STR91X_IAR/webserver/httpd-cgi.c deleted file mode 100644 index 6ad2b9b2d..000000000 --- a/Demo/ARM9_STR91X_IAR/webserver/httpd-cgi.c +++ /dev/null @@ -1,233 +0,0 @@ -/** - * \addtogroup httpd - * @{ - */ - -/** - * \file - * Web server script interface - * \author - * Adam Dunkels - * - */ - -/* - * Copyright (c) 2001-2006, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: httpd-cgi.c,v 1.2 2006/06/11 21:46:37 adam Exp $ - * - */ - -#include "uip.h" -#include "psock.h" -#include "httpd.h" -#include "httpd-cgi.h" -#include "httpd-fs.h" - -#include -#include - -HTTPD_CGI_CALL(file, "file-stats", file_stats); -HTTPD_CGI_CALL(tcp, "tcp-connections", tcp_stats); -HTTPD_CGI_CALL(net, "net-stats", net_stats); -HTTPD_CGI_CALL(rtos, "rtos-stats", rtos_stats ); - - -static const struct httpd_cgi_call *calls[] = { &file, &tcp, &net, &rtos, NULL }; - -/*---------------------------------------------------------------------------*/ -static -PT_THREAD(nullfunction(struct httpd_state *s, char *ptr)) -{ - PSOCK_BEGIN(&s->sout); - PSOCK_END(&s->sout); -} -/*---------------------------------------------------------------------------*/ -httpd_cgifunction -httpd_cgi(char *name) -{ - const struct httpd_cgi_call **f; - - /* Find the matching name in the table, return the function. */ - for(f = calls; *f != NULL; ++f) { - if(strncmp((*f)->name, name, strlen((*f)->name)) == 0) { - return (*f)->function; - } - } - return nullfunction; -} -/*---------------------------------------------------------------------------*/ -static unsigned short -generate_file_stats(void *arg) -{ - char *f = (char *)arg; - return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, "%5u", httpd_fs_count(f)); -} -/*---------------------------------------------------------------------------*/ -static -PT_THREAD(file_stats(struct httpd_state *s, char *ptr)) -{ - PSOCK_BEGIN(&s->sout); - - PSOCK_GENERATOR_SEND(&s->sout, generate_file_stats, strchr(ptr, ' ') + 1); - - PSOCK_END(&s->sout); -} -/*---------------------------------------------------------------------------*/ -static const char closed[] = /* "CLOSED",*/ -{0x43, 0x4c, 0x4f, 0x53, 0x45, 0x44, 0}; -static const char syn_rcvd[] = /* "SYN-RCVD",*/ -{0x53, 0x59, 0x4e, 0x2d, 0x52, 0x43, 0x56, - 0x44, 0}; -static const char syn_sent[] = /* "SYN-SENT",*/ -{0x53, 0x59, 0x4e, 0x2d, 0x53, 0x45, 0x4e, - 0x54, 0}; -static const char established[] = /* "ESTABLISHED",*/ -{0x45, 0x53, 0x54, 0x41, 0x42, 0x4c, 0x49, 0x53, 0x48, - 0x45, 0x44, 0}; -static const char fin_wait_1[] = /* "FIN-WAIT-1",*/ -{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, - 0x54, 0x2d, 0x31, 0}; -static const char fin_wait_2[] = /* "FIN-WAIT-2",*/ -{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, - 0x54, 0x2d, 0x32, 0}; -static const char closing[] = /* "CLOSING",*/ -{0x43, 0x4c, 0x4f, 0x53, 0x49, - 0x4e, 0x47, 0}; -static const char time_wait[] = /* "TIME-WAIT,"*/ -{0x54, 0x49, 0x4d, 0x45, 0x2d, 0x57, 0x41, - 0x49, 0x54, 0}; -static const char last_ack[] = /* "LAST-ACK"*/ -{0x4c, 0x41, 0x53, 0x54, 0x2d, 0x41, 0x43, - 0x4b, 0}; - -static const char *states[] = { - closed, - syn_rcvd, - syn_sent, - established, - fin_wait_1, - fin_wait_2, - closing, - time_wait, - last_ack}; - - -static unsigned short -generate_tcp_stats(void *arg) -{ - struct uip_conn *conn; - struct httpd_state *s = (struct httpd_state *)arg; - - conn = &uip_conns[s->count]; - return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, - "%d%u.%u.%u.%u:%u%s%u%u%c %c\r\n", - htons(conn->lport), - htons(conn->ripaddr[0]) >> 8, - htons(conn->ripaddr[0]) & 0xff, - htons(conn->ripaddr[1]) >> 8, - htons(conn->ripaddr[1]) & 0xff, - htons(conn->rport), - states[conn->tcpstateflags & UIP_TS_MASK], - conn->nrtx, - conn->timer, - (uip_outstanding(conn))? '*':' ', - (uip_stopped(conn))? '!':' '); -} -/*---------------------------------------------------------------------------*/ -static -PT_THREAD(tcp_stats(struct httpd_state *s, char *ptr)) -{ - - PSOCK_BEGIN(&s->sout); - - for(s->count = 0; s->count < UIP_CONNS; ++s->count) { - if((uip_conns[s->count].tcpstateflags & UIP_TS_MASK) != UIP_CLOSED) { - PSOCK_GENERATOR_SEND(&s->sout, generate_tcp_stats, s); - } - } - - PSOCK_END(&s->sout); -} -/*---------------------------------------------------------------------------*/ -static unsigned short -generate_net_stats(void *arg) -{ - struct httpd_state *s = (struct httpd_state *)arg; - return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, - "%5u\n", ((uip_stats_t *)&uip_stat)[s->count]); -} - -static -PT_THREAD(net_stats(struct httpd_state *s, char *ptr)) -{ - PSOCK_BEGIN(&s->sout); - -#if UIP_STATISTICS - - for(s->count = 0; s->count < sizeof(uip_stat) / sizeof(uip_stats_t); - ++s->count) { - PSOCK_GENERATOR_SEND(&s->sout, generate_net_stats, s); - } - -#endif /* UIP_STATISTICS */ - - PSOCK_END(&s->sout); -} -/*---------------------------------------------------------------------------*/ - -extern void vTaskList( signed char *pcWriteBuffer ); -static char cCountBuf[ 32 ]; -long lRefreshCount = 0; -static unsigned short -generate_rtos_stats(void *arg) -{ - lRefreshCount++; - sprintf( cCountBuf, "


Refresh count = %d", lRefreshCount ); - vTaskList( uip_appdata ); - strcat( uip_appdata, cCountBuf ); - - return strlen( uip_appdata ); -} -/*---------------------------------------------------------------------------*/ - - -static -PT_THREAD(rtos_stats(struct httpd_state *s, char *ptr)) -{ - PSOCK_BEGIN(&s->sout); -// for( s->count = 0; s->count < 4; ++s->count ) -// { - PSOCK_GENERATOR_SEND(&s->sout, generate_rtos_stats, NULL); -// } - PSOCK_END(&s->sout); -} - -/** @} */ diff --git a/Demo/ARM9_STR91X_IAR/webserver/httpd-cgi.h b/Demo/ARM9_STR91X_IAR/webserver/httpd-cgi.h deleted file mode 100644 index 7ae928321..000000000 --- a/Demo/ARM9_STR91X_IAR/webserver/httpd-cgi.h +++ /dev/null @@ -1,84 +0,0 @@ -/** - * \addtogroup httpd - * @{ - */ - -/** - * \file - * Web server script interface header file - * \author - * Adam Dunkels - * - */ - - - -/* - * Copyright (c) 2001, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: httpd-cgi.h,v 1.2 2006/06/11 21:46:38 adam Exp $ - * - */ - -#ifndef __HTTPD_CGI_H__ -#define __HTTPD_CGI_H__ - -#include "psock.h" -#include "httpd.h" - -typedef PT_THREAD((* httpd_cgifunction)(struct httpd_state *, char *)); - -httpd_cgifunction httpd_cgi(char *name); - -struct httpd_cgi_call { - const char *name; - const httpd_cgifunction function; -}; - -/** - * \brief HTTPD CGI function declaration - * \param name The C variable name of the function - * \param str The string name of the function, used in the script file - * \param function A pointer to the function that implements it - * - * This macro is used for declaring a HTTPD CGI - * function. This function is then added to the list of - * HTTPD CGI functions with the httpd_cgi_add() function. - * - * \hideinitializer - */ -#define HTTPD_CGI_CALL(name, str, function) \ -static PT_THREAD(function(struct httpd_state *, char *)); \ -static const struct httpd_cgi_call name = {str, function} - -void httpd_cgi_init(void); -#endif /* __HTTPD_CGI_H__ */ - -/** @} */ diff --git a/Demo/ARM9_STR91X_IAR/webserver/httpd-fs.c b/Demo/ARM9_STR91X_IAR/webserver/httpd-fs.c deleted file mode 100644 index dc4aef011..000000000 --- a/Demo/ARM9_STR91X_IAR/webserver/httpd-fs.c +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright (c) 2001, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - * $Id: httpd-fs.c,v 1.1 2006/06/07 09:13:08 adam Exp $ - */ - -#include "httpd.h" -#include "httpd-fs.h" -#include "httpd-fsdata.h" - -#ifndef NULL -#define NULL 0 -#endif /* NULL */ - -#include "httpd-fsdata.c" - -#if HTTPD_FS_STATISTICS -static u16_t count[HTTPD_FS_NUMFILES]; -#endif /* HTTPD_FS_STATISTICS */ - -/*-----------------------------------------------------------------------------------*/ -static u8_t -httpd_fs_strcmp(const char *str1, const char *str2) -{ - u8_t i; - i = 0; - loop: - - if(str2[i] == 0 || - str1[i] == '\r' || - str1[i] == '\n') { - return 0; - } - - if(str1[i] != str2[i]) { - return 1; - } - - - ++i; - goto loop; -} -/*-----------------------------------------------------------------------------------*/ -int -httpd_fs_open(const char *name, struct httpd_fs_file *file) -{ -#if HTTPD_FS_STATISTICS - u16_t i = 0; -#endif /* HTTPD_FS_STATISTICS */ - struct httpd_fsdata_file_noconst *f; - - for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT; - f != NULL; - f = (struct httpd_fsdata_file_noconst *)f->next) { - - if(httpd_fs_strcmp(name, f->name) == 0) { - file->data = f->data; - file->len = f->len; -#if HTTPD_FS_STATISTICS - ++count[i]; -#endif /* HTTPD_FS_STATISTICS */ - return 1; - } -#if HTTPD_FS_STATISTICS - ++i; -#endif /* HTTPD_FS_STATISTICS */ - - } - return 0; -} -/*-----------------------------------------------------------------------------------*/ -void -httpd_fs_init(void) -{ -#if HTTPD_FS_STATISTICS - u16_t i; - for(i = 0; i < HTTPD_FS_NUMFILES; i++) { - count[i] = 0; - } -#endif /* HTTPD_FS_STATISTICS */ -} -/*-----------------------------------------------------------------------------------*/ -#if HTTPD_FS_STATISTICS -u16_t httpd_fs_count -(char *name) -{ - struct httpd_fsdata_file_noconst *f; - u16_t i; - - i = 0; - for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT; - f != NULL; - f = (struct httpd_fsdata_file_noconst *)f->next) { - - if(httpd_fs_strcmp(name, f->name) == 0) { - return count[i]; - } - ++i; - } - return 0; -} -#endif /* HTTPD_FS_STATISTICS */ -/*-----------------------------------------------------------------------------------*/ diff --git a/Demo/ARM9_STR91X_IAR/webserver/httpd-fs.h b/Demo/ARM9_STR91X_IAR/webserver/httpd-fs.h deleted file mode 100644 index b594eea56..000000000 --- a/Demo/ARM9_STR91X_IAR/webserver/httpd-fs.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (c) 2001, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - * $Id: httpd-fs.h,v 1.1 2006/06/07 09:13:08 adam Exp $ - */ -#ifndef __HTTPD_FS_H__ -#define __HTTPD_FS_H__ - -#define HTTPD_FS_STATISTICS 1 - -struct httpd_fs_file { - char *data; - int len; -}; - -/* file must be allocated by caller and will be filled in - by the function. */ -int httpd_fs_open(const char *name, struct httpd_fs_file *file); - -#ifdef HTTPD_FS_STATISTICS -#if HTTPD_FS_STATISTICS == 1 -u16_t httpd_fs_count(char *name); -#endif /* HTTPD_FS_STATISTICS */ -#endif /* HTTPD_FS_STATISTICS */ - -void httpd_fs_init(void); - -#endif /* __HTTPD_FS_H__ */ diff --git a/Demo/ARM9_STR91X_IAR/webserver/httpd-fs/404.html b/Demo/ARM9_STR91X_IAR/webserver/httpd-fs/404.html deleted file mode 100644 index 43e7f4cad..000000000 --- a/Demo/ARM9_STR91X_IAR/webserver/httpd-fs/404.html +++ /dev/null @@ -1,8 +0,0 @@ - - -

-

404 - file not found

-

Go here instead.

-
- - \ No newline at end of file diff --git a/Demo/ARM9_STR91X_IAR/webserver/httpd-fs/index.html b/Demo/ARM9_STR91X_IAR/webserver/httpd-fs/index.html deleted file mode 100644 index 1d3bbeee1..000000000 --- a/Demo/ARM9_STR91X_IAR/webserver/httpd-fs/index.html +++ /dev/null @@ -1,13 +0,0 @@ - - - - FreeRTOS.org uIP WEB server demo - - - -Loading index.shtml. Click here if not automatically redirected. - - - - - diff --git a/Demo/ARM9_STR91X_IAR/webserver/httpd-fs/index.shtml b/Demo/ARM9_STR91X_IAR/webserver/httpd-fs/index.shtml deleted file mode 100644 index 37afd33a5..000000000 --- a/Demo/ARM9_STR91X_IAR/webserver/httpd-fs/index.shtml +++ /dev/null @@ -1,20 +0,0 @@ - - - - FreeRTOS.org uIP WEB server demo - - - -RTOS Stats | TCP Stats | Connections | FreeRTOS.org Homepage -

-

-

-

Task statistics

-Page will refresh evey 2 seconds.

-

Task          State  Priority  Stack	#
************************************************

-%! rtos-stats
-
- - - - diff --git a/Demo/ARM9_STR91X_IAR/webserver/httpd-fs/stats.shtml b/Demo/ARM9_STR91X_IAR/webserver/httpd-fs/stats.shtml deleted file mode 100644 index 3cc2df397..000000000 --- a/Demo/ARM9_STR91X_IAR/webserver/httpd-fs/stats.shtml +++ /dev/null @@ -1,41 +0,0 @@ - - - - FreeRTOS.org uIP WEB server demo - - - -RTOS Stats | TCP Stats | Connections | FreeRTOS.org Homepage -

-

-

-

Network statistics

- -
-IP           Packets dropped
-             Packets received
-             Packets sent
-IP errors    IP version/header length
-             IP length, high byte
-             IP length, low byte
-             IP fragments
-             Header checksum
-             Wrong protocol
-ICMP	     Packets dropped
-             Packets received
-             Packets sent
-             Type errors
-TCP          Packets dropped
-             Packets received
-             Packets sent
-             Checksum errors
-             Data packets without ACKs
-             Resets
-             Retransmissions
-	     No connection avaliable
-	     Connection attempts to closed ports
-
%! net-stats
-
- - - diff --git a/Demo/ARM9_STR91X_IAR/webserver/httpd-fs/tcp.shtml b/Demo/ARM9_STR91X_IAR/webserver/httpd-fs/tcp.shtml deleted file mode 100644 index 4ed468a88..000000000 --- a/Demo/ARM9_STR91X_IAR/webserver/httpd-fs/tcp.shtml +++ /dev/null @@ -1,21 +0,0 @@ - - - - FreeRTOS.org uIP WEB server demo - - - -RTOS Stats | TCP Stats | Connections | FreeRTOS.org Homepage -

-

-
-

Network connections

-

- - -%! tcp-connections - - - - - diff --git a/Demo/ARM9_STR91X_IAR/webserver/httpd-fsdata.c b/Demo/ARM9_STR91X_IAR/webserver/httpd-fsdata.c deleted file mode 100644 index d4017cd19..000000000 --- a/Demo/ARM9_STR91X_IAR/webserver/httpd-fsdata.c +++ /dev/null @@ -1,363 +0,0 @@ -static const unsigned char data_404_html[] = { - /* /404.html */ - 0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0, - 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xa, 0x20, 0x20, 0x3c, - 0x62, 0x6f, 0x64, 0x79, 0x20, 0x62, 0x67, 0x63, 0x6f, 0x6c, - 0x6f, 0x72, 0x3d, 0x22, 0x77, 0x68, 0x69, 0x74, 0x65, 0x22, - 0x3e, 0xa, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x63, 0x65, 0x6e, - 0x74, 0x65, 0x72, 0x3e, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, - 0x20, 0x3c, 0x68, 0x31, 0x3e, 0x34, 0x30, 0x34, 0x20, 0x2d, - 0x20, 0x66, 0x69, 0x6c, 0x65, 0x20, 0x6e, 0x6f, 0x74, 0x20, - 0x66, 0x6f, 0x75, 0x6e, 0x64, 0x3c, 0x2f, 0x68, 0x31, 0x3e, - 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x68, 0x33, - 0x3e, 0x47, 0x6f, 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, - 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0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x73, 0xa, 0x3c, 0x2f, - 0x70, 0x72, 0x65, 0x3e, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, 0x74, - 0x3e, 0xa, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, 0x74, 0x3e, 0xa, - 0x3c, 0x2f, 0x62, 0x6f, 0x64, 0x79, 0x3e, 0xa, 0x3c, 0x2f, - 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xa, 0xa, 0}; - -const struct httpd_fsdata_file file_404_html[] = {{NULL, data_404_html, data_404_html + 10, sizeof(data_404_html) - 10}}; - -const struct httpd_fsdata_file file_index_html[] = {{file_404_html, data_index_html, data_index_html + 12, sizeof(data_index_html) - 12}}; - -const struct httpd_fsdata_file file_index_shtml[] = {{file_index_html, data_index_shtml, data_index_shtml + 13, sizeof(data_index_shtml) - 13}}; - -const struct httpd_fsdata_file file_stats_shtml[] = {{file_index_shtml, data_stats_shtml, data_stats_shtml + 13, sizeof(data_stats_shtml) - 13}}; - -const struct httpd_fsdata_file file_tcp_shtml[] = {{file_stats_shtml, data_tcp_shtml, data_tcp_shtml + 11, sizeof(data_tcp_shtml) - 11}}; - -#define HTTPD_FS_ROOT file_tcp_shtml - -#define HTTPD_FS_NUMFILES 5 diff --git a/Demo/ARM9_STR91X_IAR/webserver/httpd-fsdata.h b/Demo/ARM9_STR91X_IAR/webserver/httpd-fsdata.h deleted file mode 100644 index 52d35c265..000000000 --- a/Demo/ARM9_STR91X_IAR/webserver/httpd-fsdata.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2001, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - * $Id: httpd-fsdata.h,v 1.1 2006/06/07 09:13:08 adam Exp $ - */ -#ifndef __HTTPD_FSDATA_H__ -#define __HTTPD_FSDATA_H__ - -#include "uip.h" - -struct httpd_fsdata_file { - const struct httpd_fsdata_file *next; - const char *name; - const char *data; - const int len; -#ifdef HTTPD_FS_STATISTICS -#if HTTPD_FS_STATISTICS == 1 - u16_t count; -#endif /* HTTPD_FS_STATISTICS */ -#endif /* HTTPD_FS_STATISTICS */ -}; - -struct httpd_fsdata_file_noconst { - struct httpd_fsdata_file *next; - char *name; - char *data; - int len; -#ifdef HTTPD_FS_STATISTICS -#if HTTPD_FS_STATISTICS == 1 - u16_t count; -#endif /* HTTPD_FS_STATISTICS */ -#endif /* HTTPD_FS_STATISTICS */ -}; - -#endif /* __HTTPD_FSDATA_H__ */ diff --git a/Demo/ARM9_STR91X_IAR/webserver/httpd.c b/Demo/ARM9_STR91X_IAR/webserver/httpd.c deleted file mode 100644 index e808688d2..000000000 --- a/Demo/ARM9_STR91X_IAR/webserver/httpd.c +++ /dev/null @@ -1,338 +0,0 @@ -/** - * \addtogroup apps - * @{ - */ - -/** - * \defgroup httpd Web server - * @{ - * The uIP web server is a very simplistic implementation of an HTTP - * server. It can serve web pages and files from a read-only ROM - * filesystem, and provides a very small scripting language. - - */ - -/** - * \file - * Web server - * \author - * Adam Dunkels - */ - - -/* - * Copyright (c) 2004, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * Author: Adam Dunkels - * - * $Id: httpd.c,v 1.2 2006/06/11 21:46:38 adam Exp $ - */ - -#include "uip.h" -#include "httpd.h" -#include "httpd-fs.h" -#include "httpd-cgi.h" -#include "http-strings.h" - -#include - -#define STATE_WAITING 0 -#define STATE_OUTPUT 1 - -#define ISO_nl 0x0a -#define ISO_space 0x20 -#define ISO_bang 0x21 -#define ISO_percent 0x25 -#define ISO_period 0x2e -#define ISO_slash 0x2f -#define ISO_colon 0x3a - - -/*---------------------------------------------------------------------------*/ -static unsigned short -generate_part_of_file(void *state) -{ - struct httpd_state *s = (struct httpd_state *)state; - - if(s->file.len > uip_mss()) { - s->len = uip_mss(); - } else { - s->len = s->file.len; - } - memcpy(uip_appdata, s->file.data, s->len); - - return s->len; -} -/*---------------------------------------------------------------------------*/ -static -PT_THREAD(send_file(struct httpd_state *s)) -{ - PSOCK_BEGIN(&s->sout); - - do { - PSOCK_GENERATOR_SEND(&s->sout, generate_part_of_file, s); - s->file.len -= s->len; - s->file.data += s->len; - } while(s->file.len > 0); - - PSOCK_END(&s->sout); -} -/*---------------------------------------------------------------------------*/ -static -PT_THREAD(send_part_of_file(struct httpd_state *s)) -{ - PSOCK_BEGIN(&s->sout); - - PSOCK_SEND(&s->sout, s->file.data, s->len); - - PSOCK_END(&s->sout); -} -/*---------------------------------------------------------------------------*/ -static void -next_scriptstate(struct httpd_state *s) -{ - char *p; - p = strchr(s->scriptptr, ISO_nl) + 1; - s->scriptlen -= (unsigned short)(p - s->scriptptr); - s->scriptptr = p; -} -/*---------------------------------------------------------------------------*/ -static -PT_THREAD(handle_script(struct httpd_state *s)) -{ - char *ptr; - - PT_BEGIN(&s->scriptpt); - - - while(s->file.len > 0) { - - /* Check if we should start executing a script. */ - if(*s->file.data == ISO_percent && - *(s->file.data + 1) == ISO_bang) { - s->scriptptr = s->file.data + 3; - s->scriptlen = s->file.len - 3; - if(*(s->scriptptr - 1) == ISO_colon) { - httpd_fs_open(s->scriptptr + 1, &s->file); - PT_WAIT_THREAD(&s->scriptpt, send_file(s)); - } else { - PT_WAIT_THREAD(&s->scriptpt, - httpd_cgi(s->scriptptr)(s, s->scriptptr)); - } - next_scriptstate(s); - - /* The script is over, so we reset the pointers and continue - sending the rest of the file. */ - s->file.data = s->scriptptr; - s->file.len = s->scriptlen; - } else { - /* See if we find the start of script marker in the block of HTML - to be sent. */ - - if(s->file.len > uip_mss()) { - s->len = uip_mss(); - } else { - s->len = s->file.len; - } - - if(*s->file.data == ISO_percent) { - ptr = strchr(s->file.data + 1, ISO_percent); - } else { - ptr = strchr(s->file.data, ISO_percent); - } - if(ptr != NULL && - ptr != s->file.data) { - s->len = (int)(ptr - s->file.data); - if(s->len >= uip_mss()) { - s->len = uip_mss(); - } - } - PT_WAIT_THREAD(&s->scriptpt, send_part_of_file(s)); - s->file.data += s->len; - s->file.len -= s->len; - - } - } - - PT_END(&s->scriptpt); -} -/*---------------------------------------------------------------------------*/ -static -PT_THREAD(send_headers(struct httpd_state *s, const char *statushdr)) -{ - char *ptr; - - PSOCK_BEGIN(&s->sout); - - PSOCK_SEND_STR(&s->sout, statushdr); - - ptr = strrchr(s->filename, ISO_period); - if(ptr == NULL) { - PSOCK_SEND_STR(&s->sout, http_content_type_binary); - } else if(strncmp(http_html, ptr, 5) == 0 || - strncmp(http_shtml, ptr, 6) == 0) { - PSOCK_SEND_STR(&s->sout, http_content_type_html); - } else if(strncmp(http_css, ptr, 4) == 0) { - PSOCK_SEND_STR(&s->sout, http_content_type_css); - } else if(strncmp(http_png, ptr, 4) == 0) { - PSOCK_SEND_STR(&s->sout, http_content_type_png); - } else if(strncmp(http_gif, ptr, 4) == 0) { - PSOCK_SEND_STR(&s->sout, http_content_type_gif); - } else if(strncmp(http_jpg, ptr, 4) == 0) { - PSOCK_SEND_STR(&s->sout, http_content_type_jpg); - } else { - PSOCK_SEND_STR(&s->sout, http_content_type_plain); - } - PSOCK_END(&s->sout); -} -/*---------------------------------------------------------------------------*/ -static -PT_THREAD(handle_output(struct httpd_state *s)) -{ - char *ptr; - - PT_BEGIN(&s->outputpt); - - if(!httpd_fs_open(s->filename, &s->file)) { - httpd_fs_open(http_404_html, &s->file); - strcpy(s->filename, http_404_html); - PT_WAIT_THREAD(&s->outputpt, - send_headers(s, - http_header_404)); - PT_WAIT_THREAD(&s->outputpt, - send_file(s)); - } else { - PT_WAIT_THREAD(&s->outputpt, - send_headers(s, - http_header_200)); - ptr = strchr(s->filename, ISO_period); - if(ptr != NULL && strncmp(ptr, http_shtml, 6) == 0) { - PT_INIT(&s->scriptpt); - PT_WAIT_THREAD(&s->outputpt, handle_script(s)); - } else { - PT_WAIT_THREAD(&s->outputpt, - send_file(s)); - } - } - PSOCK_CLOSE(&s->sout); - PT_END(&s->outputpt); -} -/*---------------------------------------------------------------------------*/ -static -PT_THREAD(handle_input(struct httpd_state *s)) -{ - PSOCK_BEGIN(&s->sin); - - PSOCK_READTO(&s->sin, ISO_space); - - - if(strncmp(s->inputbuf, http_get, 4) != 0) { - PSOCK_CLOSE_EXIT(&s->sin); - } - PSOCK_READTO(&s->sin, ISO_space); - - if(s->inputbuf[0] != ISO_slash) { - PSOCK_CLOSE_EXIT(&s->sin); - } - - if(s->inputbuf[1] == ISO_space) { - strncpy(s->filename, http_index_html, sizeof(s->filename)); - } else { - s->inputbuf[PSOCK_DATALEN(&s->sin) - 1] = 0; - strncpy(s->filename, &s->inputbuf[0], sizeof(s->filename)); - } - - /* httpd_log_file(uip_conn->ripaddr, s->filename);*/ - - s->state = STATE_OUTPUT; - - while(1) { - PSOCK_READTO(&s->sin, ISO_nl); - - if(strncmp(s->inputbuf, http_referer, 8) == 0) { - s->inputbuf[PSOCK_DATALEN(&s->sin) - 2] = 0; - /* httpd_log(&s->inputbuf[9]);*/ - } - } - - PSOCK_END(&s->sin); -} -/*---------------------------------------------------------------------------*/ -static void -handle_connection(struct httpd_state *s) -{ - handle_input(s); - if(s->state == STATE_OUTPUT) { - handle_output(s); - } -} -/*---------------------------------------------------------------------------*/ -void -httpd_appcall(void) -{ - struct httpd_state *s = (struct httpd_state *)&(uip_conn->appstate); - - if(uip_closed() || uip_aborted() || uip_timedout()) { - } else if(uip_connected()) { - PSOCK_INIT(&s->sin, s->inputbuf, sizeof(s->inputbuf) - 1); - PSOCK_INIT(&s->sout, s->inputbuf, sizeof(s->inputbuf) - 1); - PT_INIT(&s->outputpt); - s->state = STATE_WAITING; - /* timer_set(&s->timer, CLOCK_SECOND * 100);*/ - s->timer = 0; - handle_connection(s); - } else if(s != NULL) { - if(uip_poll()) { - ++s->timer; - if(s->timer >= 20) { - uip_abort(); - } - } else { - s->timer = 0; - } - handle_connection(s); - } else { - uip_abort(); - } -} -/*---------------------------------------------------------------------------*/ -/** - * \brief Initialize the web server - * - * This function initializes the web server and should be - * called at system boot-up. - */ -void -httpd_init(void) -{ - uip_listen(HTONS(80)); -} -/*---------------------------------------------------------------------------*/ -/** @} */ diff --git a/Demo/ARM9_STR91X_IAR/webserver/httpd.h b/Demo/ARM9_STR91X_IAR/webserver/httpd.h deleted file mode 100644 index 7f7a6666e..000000000 --- a/Demo/ARM9_STR91X_IAR/webserver/httpd.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (c) 2001-2005, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: httpd.h,v 1.2 2006/06/11 21:46:38 adam Exp $ - * - */ - -#ifndef __HTTPD_H__ -#define __HTTPD_H__ - -#include "psock.h" -#include "httpd-fs.h" - -struct httpd_state { - unsigned char timer; - struct psock sin, sout; - struct pt outputpt, scriptpt; - char inputbuf[50]; - char filename[20]; - char state; - struct httpd_fs_file file; - int len; - char *scriptptr; - int scriptlen; - - unsigned short count; -}; - -void httpd_init(void); -void httpd_appcall(void); - -void httpd_log(char *msg); -void httpd_log_file(u16_t *requester, char *file); - -#endif /* __HTTPD_H__ */ diff --git a/Demo/ARM9_STR91X_IAR/webserver/makefsdata b/Demo/ARM9_STR91X_IAR/webserver/makefsdata deleted file mode 100644 index 8d2715a8a..000000000 --- a/Demo/ARM9_STR91X_IAR/webserver/makefsdata +++ /dev/null @@ -1,78 +0,0 @@ -#!/usr/bin/perl - -open(OUTPUT, "> httpd-fsdata.c"); - -chdir("httpd-fs"); - -opendir(DIR, "."); -@files = grep { !/^\./ && !/(CVS|~)/ } readdir(DIR); -closedir(DIR); - -foreach $file (@files) { - - if(-d $file && $file !~ /^\./) { - print "Processing directory $file\n"; - opendir(DIR, $file); - @newfiles = grep { !/^\./ && !/(CVS|~)/ } readdir(DIR); - closedir(DIR); - printf "Adding files @newfiles\n"; - @files = (@files, map { $_ = "$file/$_" } @newfiles); - next; - } -} - -foreach $file (@files) { - if(-f $file) { - - print "Adding file $file\n"; - - open(FILE, $file) || die "Could not open file $file\n"; - - $file =~ s-^-/-; - $fvar = $file; - $fvar =~ s-/-_-g; - $fvar =~ s-\.-_-g; - # for AVR, add PROGMEM here - print(OUTPUT "static const unsigned char data".$fvar."[] = {\n"); - print(OUTPUT "\t/* $file */\n\t"); - for($j = 0; $j < length($file); $j++) { - printf(OUTPUT "%#02x, ", unpack("C", substr($file, $j, 1))); - } - printf(OUTPUT "0,\n"); - - - $i = 0; - while(read(FILE, $data, 1)) { - if($i == 0) { - print(OUTPUT "\t"); - } - printf(OUTPUT "%#02x, ", unpack("C", $data)); - $i++; - if($i == 10) { - print(OUTPUT "\n"); - $i = 0; - } - } - print(OUTPUT "0};\n\n"); - close(FILE); - push(@fvars, $fvar); - push(@pfiles, $file); - } -} - -for($i = 0; $i < @fvars; $i++) { - $file = $pfiles[$i]; - $fvar = $fvars[$i]; - - if($i == 0) { - $prevfile = "NULL"; - } else { - $prevfile = "file" . $fvars[$i - 1]; - } - print(OUTPUT "const struct httpd_fsdata_file file".$fvar."[] = {{$prevfile, data$fvar, "); - print(OUTPUT "data$fvar + ". (length($file) + 1) .", "); - print(OUTPUT "sizeof(data$fvar) - ". (length($file) + 1) ."}};\n\n"); -} - -print(OUTPUT "#define HTTPD_FS_ROOT file$fvars[$i - 1]\n\n"); -print(OUTPUT "#define HTTPD_FS_NUMFILES $i\n"); diff --git a/Demo/ARM9_STR91X_IAR/webserver/makestrings b/Demo/ARM9_STR91X_IAR/webserver/makestrings deleted file mode 100644 index 8a13c6d29..000000000 --- a/Demo/ARM9_STR91X_IAR/webserver/makestrings +++ /dev/null @@ -1,40 +0,0 @@ -#!/usr/bin/perl - - -sub stringify { - my $name = shift(@_); - open(OUTPUTC, "> $name.c"); - open(OUTPUTH, "> $name.h"); - - open(FILE, "$name"); - - while() { - if(/(.+) "(.+)"/) { - $var = $1; - $data = $2; - - $datan = $data; - $datan =~ s/\\r/\r/g; - $datan =~ s/\\n/\n/g; - $datan =~ s/\\01/\01/g; - $datan =~ s/\\0/\0/g; - - printf(OUTPUTC "const char $var\[%d] = \n", length($datan) + 1); - printf(OUTPUTC "/* \"$data\" */\n"); - printf(OUTPUTC "{"); - for($j = 0; $j < length($datan); $j++) { - printf(OUTPUTC "%#02x, ", unpack("C", substr($datan, $j, 1))); - } - printf(OUTPUTC "};\n"); - - printf(OUTPUTH "extern const char $var\[%d];\n", length($datan) + 1); - - } - } - close(OUTPUTC); - close(OUTPUTH); -} -stringify("http-strings"); - -exit 0; - diff --git a/Demo/ARM9_STR91X_IAR/webserver/uIP_Task.c b/Demo/ARM9_STR91X_IAR/webserver/uIP_Task.c deleted file mode 100644 index 1d136f32a..000000000 --- a/Demo/ARM9_STR91X_IAR/webserver/uIP_Task.c +++ /dev/null @@ -1,299 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ -/* Standard includes. */ -#include - -/* Library includes. */ -#include "91x_lib.h" -#include "91x_enet.h" - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "semphr.h" - -/* uip includes. */ -#include "uip.h" -#include "uip_arp.h" -#include "httpd.h" -#include "timer.h" -#include "clock-arch.h" - -/*-----------------------------------------------------------*/ - -/* MAC address configuration. */ -#define uipMAC_ADDR0 0x00 -#define uipMAC_ADDR1 0x12 -#define uipMAC_ADDR2 0x13 -#define uipMAC_ADDR3 0x14 -#define uipMAC_ADDR4 0x15 -#define uipMAC_ADDR5 0x16 - -/* IP address configuration. */ -#define uipIP_ADDR0 172 -#define uipIP_ADDR1 25 -#define uipIP_ADDR2 218 -#define uipIP_ADDR3 26 - -/* Shortcut to the header within the Rx buffer. */ -#define xHeader ((struct uip_eth_hdr *) &uip_buf[ 0 ]) - -/* uIP update frequencies. */ -#define uipMAX_BLOCK_TIME (configTICK_RATE_HZ / 4) - -/* Interrupt status bit definition. */ -#define uipDMI_RX_CURRENT_DONE 0x8000 - -/* If no buffers are available, then wait this long before looking again. */ -#define uipBUFFER_WAIT_DELAY ( 10 / portTICK_RATE_MS ) -#define uipBUFFER_WAIT_ATTEMPTS ( 10 ) - -/* Standard constant. */ -#define uipTOTAL_FRAME_HEADER_SIZE 54 - -/*-----------------------------------------------------------*/ - -/* - * Send the uIP buffer to the MAC. - */ -static void prvENET_Send(void); - -/* - * Setup the MAC address in the MAC itself, and in the uIP stack. - */ -static void prvSetMACAddress( void ); - -/* - * Used to return a pointer to the next buffer to be used. - */ -extern unsigned portCHAR *pcGetNextBuffer( void ); - -/* - * Port functions required by the uIP stack. - */ -void clock_init( void ); -clock_time_t clock_time( void ); - -/*-----------------------------------------------------------*/ - -/* The semaphore used by the ISR to wake the uIP task. */ -xSemaphoreHandle xSemaphore = NULL; - -/*-----------------------------------------------------------*/ - -void clock_init(void) -{ - /* This is done when the scheduler starts. */ -} -/*-----------------------------------------------------------*/ - -clock_time_t clock_time( void ) -{ - return xTaskGetTickCount(); -} -/*-----------------------------------------------------------*/ - -void vuIP_Task( void *pvParameters ) -{ -portBASE_TYPE i; -uip_ipaddr_t xIPAddr; -struct timer periodic_timer, arp_timer; - - /* Create the semaphore used by the ISR to wake this task. */ - vSemaphoreCreateBinary( xSemaphore ); - - /* Initialise the uIP stack. */ - timer_set( &periodic_timer, configTICK_RATE_HZ / 2 ); - timer_set( &arp_timer, configTICK_RATE_HZ * 10 ); - uip_init(); - uip_ipaddr( xIPAddr, uipIP_ADDR0, uipIP_ADDR1, uipIP_ADDR2, uipIP_ADDR3 ); - uip_sethostaddr( xIPAddr ); - httpd_init(); - - /* Initialise the MAC. */ - ENET_InitClocksGPIO(); - ENET_Init(); - portENTER_CRITICAL(); - { - ENET_Start(); - prvSetMACAddress(); - VIC_Config( ENET_ITLine, VIC_IRQ, 1 ); - VIC_ITCmd( ENET_ITLine, ENABLE ); - ENET_DMA->ISR = uipDMI_RX_CURRENT_DONE; - ENET_DMA->IER = uipDMI_RX_CURRENT_DONE; - } - portEXIT_CRITICAL(); - - - while(1) - { - /* Is there received data ready to be processed? */ - uip_len = ENET_HandleRxPkt( uip_buf ); - - if( uip_len > 0 ) - { - /* Standard uIP loop taken from the uIP manual. */ - if( xHeader->type == htons( UIP_ETHTYPE_IP ) ) - { - uip_arp_ipin(); - uip_input(); - - /* If the above function invocation resulted in data that - should be sent out on the network, the global variable - uip_len is set to a value > 0. */ - if( uip_len > 0 ) - { - uip_arp_out(); - prvENET_Send(); - } - } - else if( xHeader->type == htons( UIP_ETHTYPE_ARP ) ) - { - uip_arp_arpin(); - - /* If the above function invocation resulted in data that - should be sent out on the network, the global variable - uip_len is set to a value > 0. */ - if( uip_len > 0 ) - { - prvENET_Send(); - } - } - } - else - { - if( timer_expired( &periodic_timer ) ) - { - timer_reset( &periodic_timer ); - for( i = 0; i < UIP_CONNS; i++ ) - { - uip_periodic( i ); - - /* If the above function invocation resulted in data that - should be sent out on the network, the global variable - uip_len is set to a value > 0. */ - if( uip_len > 0 ) - { - uip_arp_out(); - prvENET_Send(); - } - } - - /* Call the ARP timer function every 10 seconds. */ - if( timer_expired( &arp_timer ) ) - { - timer_reset( &arp_timer ); - uip_arp_timer(); - } - } - else - { - /* We did not receive a packet, and there was no periodic - processing to perform. Block for a fixed period. If a packet - is received during this period we will be woken by the ISR - giving us the Semaphore. */ - xSemaphoreTake( xSemaphore, configTICK_RATE_HZ / 2 ); - } - } - } -} -/*-----------------------------------------------------------*/ - -static void prvENET_Send(void) -{ -portBASE_TYPE i; -static unsigned portCHAR *pcTxData; - - /* Get a DMA buffer into which we can write the data to send. */ - for( i = 0; i < uipBUFFER_WAIT_ATTEMPTS; i++ ) - { - pcTxData = pcGetNextBuffer(); - - if( pcTxData ) - { - break; - } - else - { - vTaskDelay( uipBUFFER_WAIT_DELAY ); - } - } - - if( pcTxData ) - { - /* Copy the header into the Tx buffer. */ - memcpy( ( void * ) pcTxData, ( void * ) uip_buf, uipTOTAL_FRAME_HEADER_SIZE ); - - /* If there is room, also copy in the application data if any. */ - if( ( uip_len > uipTOTAL_FRAME_HEADER_SIZE ) && ( uip_len <= ( ENET_BUFFER_SIZE - uipTOTAL_FRAME_HEADER_SIZE ) ) ) - { - memcpy( ( void * ) &( pcTxData[ uipTOTAL_FRAME_HEADER_SIZE ] ), ( void * ) uip_appdata, ( uip_len - uipTOTAL_FRAME_HEADER_SIZE ) ); - } - - ENET_TxPkt( &pcTxData, uip_len ); - } -} -/*-----------------------------------------------------------*/ - -void ENET_IRQHandler(void) -{ -portBASE_TYPE xSwitchRequired; - - /* Give the semaphore in case the uIP task needs waking. */ - xSwitchRequired = xSemaphoreGiveFromISR( xSemaphore, pdFALSE ); - - /* Clear the interrupt. */ - ENET_DMA->ISR = uipDMI_RX_CURRENT_DONE; - - /* Switch tasks if necessary. */ - portEND_SWITCHING_ISR( xSwitchRequired ); -} -/*-----------------------------------------------------------*/ - -static void prvSetMACAddress( void ) -{ -struct uip_eth_addr xAddr; - - /* Configure the MAC address in the uIP stack. */ - xAddr.addr[ 0 ] = uipMAC_ADDR0; - xAddr.addr[ 1 ] = uipMAC_ADDR1; - xAddr.addr[ 2 ] = uipMAC_ADDR2; - xAddr.addr[ 3 ] = uipMAC_ADDR3; - xAddr.addr[ 4 ] = uipMAC_ADDR4; - xAddr.addr[ 5 ] = uipMAC_ADDR5; - uip_setethaddr( xAddr ); - - /* Write the MAC address to the MAC. */ - ENET_MAC->MAL = ( uipMAC_ADDR3 << 24 ) | ( uipMAC_ADDR2 << 16 ) | ( uipMAC_ADDR1 << 8 ) | ( uipMAC_ADDR0 ); - ENET_MAC->MAH = ( uipMAC_ADDR5 << 8 ) | ( uipMAC_ADDR4 ); -} - diff --git a/Demo/ARM9_STR91X_IAR/webserver/uip-conf.h b/Demo/ARM9_STR91X_IAR/webserver/uip-conf.h deleted file mode 100644 index 6a1754fa8..000000000 --- a/Demo/ARM9_STR91X_IAR/webserver/uip-conf.h +++ /dev/null @@ -1,157 +0,0 @@ -/** - * \addtogroup uipopt - * @{ - */ - -/** - * \name Project-specific configuration options - * @{ - * - * uIP has a number of configuration options that can be overridden - * for each project. These are kept in a project-specific uip-conf.h - * file and all configuration names have the prefix UIP_CONF. - */ - -/* - * Copyright (c) 2006, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack - * - * $Id: uip-conf.h,v 1.6 2006/06/12 08:00:31 adam Exp $ - */ - -/** - * \file - * An example uIP configuration file - * \author - * Adam Dunkels - */ - -#ifndef __UIP_CONF_H__ -#define __UIP_CONF_H__ - -#include - -/** - * 8 bit datatype - * - * This typedef defines the 8-bit type used throughout uIP. - * - * \hideinitializer - */ -typedef uint8_t u8_t; - -/** - * 16 bit datatype - * - * This typedef defines the 16-bit type used throughout uIP. - * - * \hideinitializer - */ -typedef uint16_t u16_t; - -/** - * Statistics datatype - * - * This typedef defines the dataype used for keeping statistics in - * uIP. - * - * \hideinitializer - */ -typedef unsigned short uip_stats_t; - -/** - * Maximum number of TCP connections. - * - * \hideinitializer - */ -#define UIP_CONF_MAX_CONNECTIONS 40 - -/** - * Maximum number of listening TCP ports. - * - * \hideinitializer - */ -#define UIP_CONF_MAX_LISTENPORTS 40 - -/** - * uIP buffer size. - * - * \hideinitializer - */ -#define UIP_CONF_BUFFER_SIZE 1500 - -/** - * CPU byte order. - * - * \hideinitializer - */ -#define UIP_CONF_BYTE_ORDER LITTLE_ENDIAN - -/** - * Logging on or off - * - * \hideinitializer - */ -#define UIP_CONF_LOGGING 0 - -/** - * UDP support on or off - * - * \hideinitializer - */ -#define UIP_CONF_UDP 0 - -/** - * UDP checksums on or off - * - * \hideinitializer - */ -#define UIP_CONF_UDP_CHECKSUMS 1 - -/** - * uIP statistics on or off - * - * \hideinitializer - */ -#define UIP_CONF_STATISTICS 1 - -/* Here we include the header file for the application(s) we use in - our project. */ -/*#include "smtp.h"*/ -/*#include "hello-world.h"*/ -/*#include "telnetd.h"*/ -#include "webserver.h" -/*#include "dhcpc.h"*/ -/*#include "resolv.h"*/ -/*#include "webclient.h"*/ - -#endif /* __UIP_CONF_H__ */ - -/** @} */ -/** @} */ diff --git a/Demo/ARM9_STR91X_IAR/webserver/webserver.h b/Demo/ARM9_STR91X_IAR/webserver/webserver.h deleted file mode 100644 index 1acb290b8..000000000 --- a/Demo/ARM9_STR91X_IAR/webserver/webserver.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2002, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack - * - * $Id: webserver.h,v 1.2 2006/06/11 21:46:38 adam Exp $ - * - */ -#ifndef __WEBSERVER_H__ -#define __WEBSERVER_H__ - -#include "httpd.h" - -typedef struct httpd_state uip_tcp_appstate_t; -/* UIP_APPCALL: the name of the application function. This function - must return void and take no arguments (i.e., C type "void - appfunc(void)"). */ -#ifndef UIP_APPCALL -#define UIP_APPCALL httpd_appcall -#endif - - -#endif /* __WEBSERVER_H__ */ diff --git a/Demo/AVR_ATMega323_IAR/FreeRTOSConfig.h b/Demo/AVR_ATMega323_IAR/FreeRTOSConfig.h deleted file mode 100644 index 16c0ab114..000000000 --- a/Demo/AVR_ATMega323_IAR/FreeRTOSConfig.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -#include - -#define configCALL_STACK_SIZE 20 - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 1 -#define configUSE_TICK_HOOK 0 -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 8000000 ) -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 85 ) -#define configTOTAL_HEAP_SIZE ( (size_t ) ( 1500 ) ) -#define configMAX_TASK_NAME_LEN ( 8 ) -#define configUSE_TRACE_FACILITY 0 -#define configUSE_16_BIT_TICKS 1 -#define configIDLE_SHOULD_YIELD 1 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 1 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 0 -#define INCLUDE_uxTaskPriorityGet 0 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 0 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/AVR_ATMega323_IAR/ParTest/ParTest.c b/Demo/AVR_ATMega323_IAR/ParTest/ParTest.c deleted file mode 100644 index f7026e8e7..000000000 --- a/Demo/AVR_ATMega323_IAR/ParTest/ParTest.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V2.0.0 - - + Use scheduler suspends in place of critical sections. - -Changes from V2.6.0 - - + Replaced the inb() and outb() functions with direct memory - access. This allows the port to be built with the 20050414 build of - WinAVR. -*/ - -#include "FreeRTOS.h" -#include "task.h" -#include "partest.h" - -/*----------------------------------------------------------- - * Simple parallel port IO routines. - *-----------------------------------------------------------*/ - -#define partstALL_BITS_OUTPUT ( ( unsigned portCHAR ) 0xff ) -#define partstALL_OUTPUTS_OFF ( ( unsigned portCHAR ) 0xff ) -#define partstMAX_OUTPUT_LED ( ( unsigned portCHAR ) 7 ) - -static volatile unsigned portCHAR ucCurrentOutputValue = partstALL_OUTPUTS_OFF; /*lint !e956 File scope parameters okay here. */ - -/*-----------------------------------------------------------*/ - -void vParTestInitialise( void ) -{ - ucCurrentOutputValue = partstALL_OUTPUTS_OFF; - - /* Set port B direction to outputs. Start with all output off. */ - DDRB = partstALL_BITS_OUTPUT; - PORTB = ucCurrentOutputValue; -} -/*-----------------------------------------------------------*/ - -void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) -{ -unsigned portCHAR ucBit = ( unsigned portCHAR ) 1; - - if( uxLED <= partstMAX_OUTPUT_LED ) - { - ucBit <<= uxLED; - } - - vTaskSuspendAll(); - { - if( xValue == pdTRUE ) - { - ucBit ^= ( unsigned portCHAR ) 0xff; - ucCurrentOutputValue &= ucBit; - } - else - { - ucCurrentOutputValue |= ucBit; - } - - PORTB = ucCurrentOutputValue; - } - xTaskResumeAll(); -} -/*-----------------------------------------------------------*/ - -void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) -{ -unsigned portCHAR ucBit; - - if( uxLED <= partstMAX_OUTPUT_LED ) - { - ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED; - - vTaskSuspendAll(); - { - if( ucCurrentOutputValue & ucBit ) - { - ucCurrentOutputValue &= ~ucBit; - } - else - { - ucCurrentOutputValue |= ucBit; - } - - PORTB = ucCurrentOutputValue; - } - xTaskResumeAll(); - } -} - - diff --git a/Demo/AVR_ATMega323_IAR/main.c b/Demo/AVR_ATMega323_IAR/main.c deleted file mode 100644 index afae70b23..000000000 --- a/Demo/AVR_ATMega323_IAR/main.c +++ /dev/null @@ -1,279 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * Creates all the demo application tasks, then starts the scheduler. The WEB - * documentation provides more details of the demo application tasks. - * - * Main. c also creates a task called "Check". This only executes every three - * seconds but has the highest priority so is guaranteed to get processor time. - * Its main function is to check that all the other tasks are still operational. - * Each task that does not flash an LED maintains a unique count that is - * incremented each time the task successfully completes its function. Should - * any error occur within such a task the count is permanently halted. The - * check task inspects the count of each task to ensure it has changed since - * the last time the check task executed. If all the count variables have - * changed all the tasks are still executing error free, and the check task - * toggles an LED. Should any task contain an error at any time the LED toggle - * will stop. - * - * The LED flash and communications test tasks do not maintain a count. - */ - -/* -Changes from V1.2.0 - - + Changed the baud rate for the serial test from 19200 to 57600. - -Changes from V1.2.3 - - + The integer and comtest tasks are now used when the cooperative scheduler - is being used. Previously they were only used with the preemptive - scheduler. - -Changes from V1.2.5 - - + Set the baud rate to 38400. This has a smaller error percentage with an - 8MHz clock (according to the manual). - -Changes from V2.0.0 - - + Delay periods are now specified using variables and constants of - portTickType rather than unsigned portLONG. - -Changes from V2.2.0 - - + File can now be built using either the IAR or WinAVR compiler. - -Changes from V2.6.1 - - + The IAR and WinAVR AVR ports are now maintained separately. - -Changes from V4.0.5 - - + Modified to demonstrate the use of co-routines. -*/ - -#include -#include - -#ifdef GCC_MEGA_AVR - /* EEPROM routines used only with the WinAVR compiler. */ - #include -#endif - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" -#include "croutine.h" - -/* Demo file headers. */ -#include "PollQ.h" -#include "integer.h" -#include "serial.h" -#include "comtest.h" -#include "crflash.h" -#include "print.h" -#include "partest.h" -#include "regtest.h" - -/* Priority definitions for most of the tasks in the demo application. Some -tasks just use the idle priority. */ -#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) - -/* Baud rate used by the serial port tasks. */ -#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 38400 ) - -/* LED used by the serial port tasks. This is toggled on each character Tx, -and mainCOM_TEST_LED + 1 is toggles on each character Rx. */ -#define mainCOM_TEST_LED ( 4 ) - -/* LED that is toggled by the check task. The check task periodically checks -that all the other tasks are operating without error. If no errors are found -the LED is toggled. If an error is found at any time the LED is never toggles -again. */ -#define mainCHECK_TASK_LED ( 7 ) - -/* The period between executions of the check task. */ -#define mainCHECK_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS ) - -/* An address in the EEPROM used to count resets. This is used to check that -the demo application is not unexpectedly resetting. */ -#define mainRESET_COUNT_ADDRESS ( ( void * ) 0x50 ) - -/* The number of coroutines to create. */ -#define mainNUM_FLASH_COROUTINES ( 3 ) - -/* - * The task function for the "Check" task. - */ -static void vErrorChecks( void *pvParameters ); - -/* - * Checks the unique counts of other tasks to ensure they are still operational. - * Flashes an LED if everything is okay. - */ -static void prvCheckOtherTasksAreStillRunning( void ); - -/* - * Called on boot to increment a count stored in the EEPROM. This is used to - * ensure the CPU does not reset unexpectedly. - */ -static void prvIncrementResetCount( void ); - -/* - * Idle hook is used to scheduler co-routines. - */ -void vApplicationIdleHook( void ); - -portSHORT main( void ) -{ - prvIncrementResetCount(); - - /* Setup the LED's for output. */ - vParTestInitialise(); - - /* Create the standard demo tasks. */ - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartRegTestTasks(); - - /* Create the tasks defined within this file. */ - xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - - /* Create the co-routines that flash the LED's. */ - vStartFlashCoRoutines( mainNUM_FLASH_COROUTINES ); - - /* In this port, to use preemptive scheduler define configUSE_PREEMPTION - as 1 in portmacro.h. To use the cooperative scheduler define - configUSE_PREEMPTION as 0. */ - vTaskStartScheduler(); - - return 0; -} -/*-----------------------------------------------------------*/ - -static void vErrorChecks( void *pvParameters ) -{ -static volatile unsigned portLONG ulDummyVariable = 3UL; - - /* The parameters are not used. */ - ( void ) pvParameters; - - /* Cycle for ever, delaying then checking all the other tasks are still - operating without error. */ - for( ;; ) - { - vTaskDelay( mainCHECK_PERIOD ); - - /* Perform a bit of 32bit maths to ensure the registers used by the - integer tasks get some exercise. The result here is not important - - see the demo application documentation for more info. */ - ulDummyVariable *= 3; - - prvCheckOtherTasksAreStillRunning(); - } -} -/*-----------------------------------------------------------*/ - -static void prvCheckOtherTasksAreStillRunning( void ) -{ -static portBASE_TYPE xErrorHasOccurred = pdFALSE; - - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - xErrorHasOccurred = pdTRUE; - } - - if( xAreComTestTasksStillRunning() != pdTRUE ) - { - xErrorHasOccurred = pdTRUE; - } - - if( xArePollingQueuesStillRunning() != pdTRUE ) - { - xErrorHasOccurred = pdTRUE; - } - - if( xAreRegTestTasksStillRunning() != pdTRUE ) - { - xErrorHasOccurred = pdTRUE; - } - - if( xErrorHasOccurred == pdFALSE ) - { - /* Toggle the LED if everything is okay so we know if an error occurs even if not - using console IO. */ - vParTestToggleLED( mainCHECK_TASK_LED ); - } -} -/*-----------------------------------------------------------*/ - -static void prvIncrementResetCount( void ) -{ -unsigned portCHAR ucCount; -const unsigned portCHAR ucReadBit = ( unsigned portCHAR ) 0x01; -const unsigned portCHAR ucWrite1 = ( unsigned portCHAR ) 0x04; -const unsigned portCHAR ucWrite2 = ( unsigned portCHAR ) 0x02; - - /* Increment the EEPROM value at 0x00. - - Setup the EEPROM address. */ - EEARH = 0x00; - EEARL = 0x00; - - /* Set the read enable bit. */ - EECR |= ucReadBit; - - /* Wait for the read. */ - while( EECR & ucReadBit ); - - /* The byte is ready. */ - ucCount = EEDR; - - /* Increment the reset count, then write the byte back. */ - ucCount++; - EEDR = ucCount; - EECR = ucWrite1; - EECR = ( ucWrite1 | ucWrite2 ); -} -/*-----------------------------------------------------------*/ - -void vApplicationIdleHook( void ) -{ - vCoRoutineSchedule(); -} - diff --git a/Demo/AVR_ATMega323_IAR/regtest.c b/Demo/AVR_ATMega323_IAR/regtest.c deleted file mode 100644 index d486cc162..000000000 --- a/Demo/AVR_ATMega323_IAR/regtest.c +++ /dev/null @@ -1,362 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Demo file headers. */ -#include "regtest.h" - -/* - * Test tasks that sets registers to known values, then checks to ensure the - * values remain as expected. Test 1 and test 2 use different values. - */ -static void prvRegisterCheck1( void *pvParameters ); -static void prvRegisterCheck2( void *pvParameters ); - -/* Set to a non zero value should an error be found. */ -portBASE_TYPE xRegTestError = pdFALSE; - -/*-----------------------------------------------------------*/ - -void vStartRegTestTasks( void ) -{ - xTaskCreate( prvRegisterCheck1, "Reg1", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); - xTaskCreate( prvRegisterCheck2, "Reg2", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xAreRegTestTasksStillRunning( void ) -{ -portBASE_TYPE xReturn; - - /* If a register was found to contain an unexpected value then the - xRegTestError variable would have been set to a non zero value. */ - if( xRegTestError == pdFALSE ) - { - xReturn = pdTRUE; - } - else - { - xReturn = pdFALSE; - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -static void prvRegisterCheck1( void *pvParameters ) -{ - ( void ) pvParameters; - - for( ;; ) - { - asm( "LDI r31, 5" ); - asm( "MOV r0, r31" ); - asm( "LDI r31, 6" ); - asm( "MOV r1, r31" ); - asm( "LDI r31, 7" ); - asm( "MOV r2, r31" ); - asm( "LDI r31, 8" ); - asm( "MOV r3, r31" ); - asm( "LDI r31, 9" ); - asm( "MOV r4, r31" ); - asm( "LDI r31, 10" ); - asm( "MOV r5, r31" ); - asm( "LDI r31, 11" ); - asm( "MOV r6, r31" ); - asm( "LDI r31, 12" ); - asm( "MOV r7, r31" ); - asm( "LDI r31, 13" ); - asm( "MOV r8, r31" ); - asm( "LDI r31, 14" ); - asm( "MOV r9, r31" ); - asm( "LDI r31, 15" ); - asm( "MOV r10, r31" ); - asm( "LDI r31, 16" ); - asm( "MOV r11, r31" ); - asm( "LDI r31, 17" ); - asm( "MOV r12, r31" ); - asm( "LDI r31, 18" ); - asm( "MOV r13, r31" ); - asm( "LDI r31, 19" ); - asm( "MOV r14, r31" ); - asm( "LDI r31, 20" ); - asm( "MOV r15, r31" ); - asm( "LDI r16, 21" ); - asm( "LDI r17, 22" ); - asm( "LDI r18, 23" ); - asm( "LDI r19, 24" ); - asm( "LDI r20, 25" ); - asm( "LDI r21, 26" ); - asm( "LDI r22, 27" ); - asm( "LDI r23, 28" ); - asm( "LDI r24, 29" ); - asm( "LDI r25, 30" ); - asm( "LDI r26, 31" ); - asm( "LDI r27, 32" ); - asm( "LDI r30, 33" ); - - asm( "LDI r31, 5" ); - asm( "CPSE r31, r0" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 6" ); - asm( "CPSE r31, r1" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 7" ); - asm( "CPSE r31, r2" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 8" ); - asm( "CPSE r31, r3" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 9" ); - asm( "CPSE r31, r4" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 10" ); - asm( "CPSE r31, r5" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 11" ); - asm( "CPSE r31, r6" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 12" ); - asm( "CPSE r31, r7" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 13" ); - asm( "CPSE r31, r8" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 14" ); - asm( "CPSE r31, r9" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 15" ); - asm( "CPSE r31, r10" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 16" ); - asm( "CPSE r31, r11" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 17" ); - asm( "CPSE r31, r12" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 18" ); - asm( "CPSE r31, r13" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 19" ); - asm( "CPSE r31, r14" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 20" ); - asm( "CPSE r31, r15" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 21" ); - asm( "CPSE r31, r16" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 22" ); - asm( "CPSE r31, r17" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 23" ); - asm( "CPSE r31, r18" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 24" ); - asm( "CPSE r31, r19" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 25" ); - asm( "CPSE r31, r20" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 26" ); - asm( "CPSE r31, r21" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 27" ); - asm( "CPSE r31, r22" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 28" ); - asm( "CPSE r31, r23" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 29" ); - asm( "CPSE r31, r24" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 30" ); - asm( "CPSE r31, r25" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 31" ); - asm( "CPSE r31, r26" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 32" ); - asm( "CPSE r31, r27" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 33" ); - asm( "CPSE r31, r30" ); - asm( "STS xRegTestError, r0" ); - } -} -/*-----------------------------------------------------------*/ - -static void prvRegisterCheck2( void *pvParameters ) -{ - ( void ) pvParameters; - - for( ;; ) - { - asm( "LDI r31, 1" ); - asm( "MOV r0, r31" ); - asm( "LDI r31, 2" ); - asm( "MOV r1, r31" ); - asm( "LDI r31, 3" ); - asm( "MOV r2, r31" ); - asm( "LDI r31, 4" ); - asm( "MOV r3, r31" ); - asm( "LDI r31, 5" ); - asm( "MOV r4, r31" ); - asm( "LDI r31, 6" ); - asm( "MOV r5, r31" ); - asm( "LDI r31, 7" ); - asm( "MOV r6, r31" ); - asm( "LDI r31, 8" ); - asm( "MOV r7, r31" ); - asm( "LDI r31, 9" ); - asm( "MOV r8, r31" ); - asm( "LDI r31, 10" ); - asm( "MOV r9, r31" ); - asm( "LDI r31, 11" ); - asm( "MOV r10, r31" ); - asm( "LDI r31, 12" ); - asm( "MOV r11, r31" ); - asm( "LDI r31, 13" ); - asm( "MOV r12, r31" ); - asm( "LDI r31, 14" ); - asm( "MOV r13, r31" ); - asm( "LDI r31, 15" ); - asm( "MOV r14, r31" ); - asm( "LDI r31, 16" ); - asm( "MOV r15, r31" ); - asm( "LDI r16, 17" ); - asm( "LDI r17, 18" ); - asm( "LDI r18, 19" ); - asm( "LDI r19, 20" ); - asm( "LDI r20, 21" ); - asm( "LDI r21, 22" ); - asm( "LDI r22, 23" ); - asm( "LDI r23, 24" ); - asm( "LDI r24, 25" ); - asm( "LDI r25, 26" ); - asm( "LDI r26, 27" ); - asm( "LDI r27, 28" ); - asm( "LDI r30, 29" ); - - asm( "LDI r31, 1" ); - asm( "CPSE r31, r0" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 2" ); - asm( "CPSE r31, r1" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 3" ); - asm( "CPSE r31, r2" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 4" ); - asm( "CPSE r31, r3" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 5" ); - asm( "CPSE r31, r4" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 6" ); - asm( "CPSE r31, r5" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 7" ); - asm( "CPSE r31, r6" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 8" ); - asm( "CPSE r31, r7" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 9" ); - asm( "CPSE r31, r8" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 10" ); - asm( "CPSE r31, r9" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 11" ); - asm( "CPSE r31, r10" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 12" ); - asm( "CPSE r31, r11" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 13" ); - asm( "CPSE r31, r12" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 14" ); - asm( "CPSE r31, r13" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 15" ); - asm( "CPSE r31, r14" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 16" ); - asm( "CPSE r31, r15" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 17" ); - asm( "CPSE r31, r16" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 18" ); - asm( "CPSE r31, r17" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 19" ); - asm( "CPSE r31, r18" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 20" ); - asm( "CPSE r31, r19" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 21" ); - asm( "CPSE r31, r20" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 22" ); - asm( "CPSE r31, r21" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 23" ); - asm( "CPSE r31, r22" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 24" ); - asm( "CPSE r31, r23" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 25" ); - asm( "CPSE r31, r24" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 26" ); - asm( "CPSE r31, r25" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 27" ); - asm( "CPSE r31, r26" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 28" ); - asm( "CPSE r31, r27" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 29" ); - asm( "CPSE r31, r30" ); - asm( "STS xRegTestError, r0" ); - } -} - diff --git a/Demo/AVR_ATMega323_IAR/regtest.h b/Demo/AVR_ATMega323_IAR/regtest.h deleted file mode 100644 index 93110d1af..000000000 --- a/Demo/AVR_ATMega323_IAR/regtest.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef REG_TEST_H -#define REG_TEST_H - -void vStartRegTestTasks( void ); -portBASE_TYPE xAreRegTestTasksStillRunning( void ); - -#endif - diff --git a/Demo/AVR_ATMega323_IAR/rtosdemo.dep b/Demo/AVR_ATMega323_IAR/rtosdemo.dep deleted file mode 100644 index 7624e767c..000000000 --- a/Demo/AVR_ATMega323_IAR/rtosdemo.dep +++ /dev/null @@ -1,554 +0,0 @@ - - - - 2 - - Debug - - $PROJ_DIR$\..\Common\Minimal\flash.c - $PROJ_DIR$\Output\Obj\flash.pbi - $TOOLKIT_DIR$\inc\clib\sysmac.h - $TOOLKIT_DIR$\inc\clib\stdarg.h - $PROJ_DIR$\Output\Obj\regtest.pbi - $PROJ_DIR$\..\..\Source\include\FreeRTOS.h - $PROJ_DIR$\..\Common\include\PollQ.h - $TOOLKIT_DIR$\inc\clib\stddef.h - $TOOLKIT_DIR$\inc\iomacro.h - $PROJ_DIR$\Output\List\PollQ.lst - $PROJ_DIR$\..\Common\include\partest.h - $PROJ_DIR$\Output\Obj\queue.pbi - $PROJ_DIR$\..\Common\include\flash.h - $TOOLKIT_DIR$\inc\clib\string.h - $TOOLKIT_DIR$\inc\clib\stdlib.h - $PROJ_DIR$\..\..\Source\include\queue.h - $PROJ_DIR$\..\..\Source\include\croutine.h - $PROJ_DIR$\..\Common\include\print.h - $PROJ_DIR$\Output\Obj\ParTest.r90 - $PROJ_DIR$\..\Common\include\serial.h - $PROJ_DIR$\Output\Obj\main.r90 - $PROJ_DIR$\Output\Obj\PollQ.r90 - $PROJ_DIR$\FreeRTOSConfig.h - $PROJ_DIR$\Output\Obj\heap_1.r90 - $PROJ_DIR$\Output\Obj\integer.r90 - $TOOLKIT_DIR$\inc\clib\stdio.h - $PROJ_DIR$\Output\List\tasks.s90 - $PROJ_DIR$\Output\List\queue.lst - $PROJ_DIR$\..\Common\include\integer.h - $TOOLKIT_DIR$\src\template\cfgm323.xcl - $PROJ_DIR$\Output\List\ParTest.lst - $PROJ_DIR$\Output\List\comtest.lst - $PROJ_DIR$\Output\List\tasks.lst - $TOOLKIT_DIR$\inc\iom323.h - $PROJ_DIR$\Output\Obj\comtest.r90 - $PROJ_DIR$\Output\Obj\list.pbi - $PROJ_DIR$\Output\Obj\serial.r90 - $PROJ_DIR$\..\..\Source\portable\IAR\ATMega323\portmacro.h - $PROJ_DIR$\regtest.c - $PROJ_DIR$\Output\Obj\crflash.r90 - $PROJ_DIR$\Output\Obj\rtosdemo.pbd - $PROJ_DIR$\Output\Obj\heap_1.pbi - $PROJ_DIR$\Output\Exe\rtosdemo.d90 - $TOOLKIT_DIR$\lib\clib\cl3s-ec-sf.r90 - $PROJ_DIR$\Output\List\integer.s90 - $PROJ_DIR$\Output\List\serial.lst - $PROJ_DIR$\Output\Obj\integer.pbi - $PROJ_DIR$\Output\Exe\rtosdemo.a90 - $PROJ_DIR$\Output\Obj\main.pbi - $PROJ_DIR$\..\..\Source\include\projdefs.h - $PROJ_DIR$\Output\List\regtest.lst - $PROJ_DIR$\Output\Obj\flash.r90 - $PROJ_DIR$\Output\Obj\list.r90 - $PROJ_DIR$\..\..\Source\include\list.h - $PROJ_DIR$\Output\Obj\tasks.r90 - $PROJ_DIR$\Output\Obj\ParTest.pbi - $PROJ_DIR$\..\Common\include\comtest.h - $PROJ_DIR$\Output\List\main.s90 - $PROJ_DIR$\Output\List\serial.s90 - $PROJ_DIR$\Output\List\port.s90 - $PROJ_DIR$\Output\List\heap_1.lst - $PROJ_DIR$\Output\Exe\rtosdemo.cof - $PROJ_DIR$\Output\List\queue.s90 - $PROJ_DIR$\Output\List\PollQ.s90 - $PROJ_DIR$\Output\Obj\port.pbi - $PROJ_DIR$\Output\List\ParTest.s90 - $PROJ_DIR$\Output\List\integer.lst - $PROJ_DIR$\Output\Obj\port.r90 - $PROJ_DIR$\Output\Obj\comtest.pbi - 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- - - - $WS_DIR$\rtosdemo.ewp - - - - - diff --git a/Demo/AVR_ATMega323_IAR/serial/serial.c b/Demo/AVR_ATMega323_IAR/serial/serial.c deleted file mode 100644 index a42db6db9..000000000 --- a/Demo/AVR_ATMega323_IAR/serial/serial.c +++ /dev/null @@ -1,195 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR IAR AVR PORT. */ - - -#include -#include "FreeRTOS.h" -#include "queue.h" -#include "task.h" -#include "serial.h" - -#define serBAUD_DIV_CONSTANT ( ( unsigned portLONG ) 16 ) - -/* Constants for writing to UCSRB. */ -#define serRX_INT_ENABLE ( ( unsigned portCHAR ) 0x80 ) -#define serRX_ENABLE ( ( unsigned portCHAR ) 0x10 ) -#define serTX_ENABLE ( ( unsigned portCHAR ) 0x08 ) -#define serTX_INT_ENABLE ( ( unsigned portCHAR ) 0x20 ) - -/* Constants for writing to UCSRC. */ -#define serUCSRC_SELECT ( ( unsigned portCHAR ) 0x80 ) -#define serEIGHT_DATA_BITS ( ( unsigned portCHAR ) 0x06 ) - -static xQueueHandle xRxedChars; -static xQueueHandle xCharsForTx; - -#define vInterruptOn() \ -{ \ - unsigned portCHAR ucByte; \ - \ - ucByte = UCSRB; \ - ucByte |= serTX_INT_ENABLE; \ - outb( UCSRB, ucByte ); \ -} -/*-----------------------------------------------------------*/ - -#define vInterruptOff() \ -{ \ - unsigned portCHAR ucByte; \ - \ - ucByte = UCSRB; \ - ucByte &= ~serTX_INT_ENABLE; \ - outb( UCSRB, ucByte ); \ -} -/*-----------------------------------------------------------*/ - -xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) -{ -unsigned portLONG ulBaudRateCounter; -unsigned portCHAR ucByte; - - portENTER_CRITICAL(); - { - /* Create the queues used by the com test task. */ - xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); - xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); - - /* Calculate the baud rate register value from the equation in the - data sheet. */ - ulBaudRateCounter = ( configCPU_CLOCK_HZ / ( serBAUD_DIV_CONSTANT * ulWantedBaud ) ) - ( unsigned portLONG ) 1; - - /* Set the baud rate. */ - ucByte = ( unsigned portCHAR ) ( ulBaudRateCounter & ( unsigned portLONG ) 0xff ); - outb( UBRRL, ucByte ); - - ulBaudRateCounter >>= ( unsigned portLONG ) 8; - ucByte = ( unsigned portCHAR ) ( ulBaudRateCounter & ( unsigned portLONG ) 0xff ); - outb( UBRRH, ucByte ); - - /* Enable the Rx interrupt. The Tx interrupt will get enabled - later. Also enable the Rx and Tx. */ - outb( UCSRB, serRX_INT_ENABLE | serRX_ENABLE | serTX_ENABLE ); - - /* Set the data bits to 8. */ - outb( UCSRC, serUCSRC_SELECT | serEIGHT_DATA_BITS ); - } - portEXIT_CRITICAL(); - - /* Unlike other ports, this serial code does not allow for more than one - com port. We therefore don't return a pointer to a port structure and can - instead just return NULL. */ - return NULL; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) -{ - /* Get the next character from the buffer. Return false if no characters - are available, or arrive before xBlockTime expires. */ - if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) - { - return pdTRUE; - } - else - { - return pdFALSE; - } -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) -{ - /* Return false if after the block time there is no room on the Tx queue. */ - if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) - { - return pdFAIL; - } - - vInterruptOn(); - - return pdPASS; -} -/*-----------------------------------------------------------*/ - -void vSerialClose( xComPortHandle xPort ) -{ -unsigned portCHAR ucByte; - - /* Turn off the interrupts. We may also want to delete the queues and/or - re-install the original ISR. */ - - portENTER_CRITICAL(); - { - vInterruptOff(); - ucByte = UCSRB; - ucByte &= ~serRX_INT_ENABLE; - outb( UCSRB, ucByte ); - } - portEXIT_CRITICAL(); -} -/*-----------------------------------------------------------*/ - -__interrupt void SIG_UART_RECV( void ) -{ -signed portCHAR cChar; - - /* Get the character and post it on the queue of Rxed characters. - If the post causes a task to wake force a context switch as the woken task - may have a higher priority than the task we have interrupted. */ - cChar = UDR; - - if( xQueueSendFromISR( xRxedChars, &cChar, pdFALSE ) ) - { - taskYIELD(); - } -} -/*-----------------------------------------------------------*/ - -__interrupt void SIG_UART_DATA( void ) -{ -signed portCHAR cChar, cTaskWoken; - - if( xQueueReceiveFromISR( xCharsForTx, &cChar, &cTaskWoken ) == pdTRUE ) - { - /* Send the next character queued for Tx. */ - outb( UDR, cChar ); - } - else - { - /* Queue empty, nothing to send. */ - vInterruptOff(); - } -} - diff --git a/Demo/AVR_ATMega323_IAR/settings/rtosdemo.dbgdt b/Demo/AVR_ATMega323_IAR/settings/rtosdemo.dbgdt deleted file mode 100644 index 33f4649c2..000000000 --- a/Demo/AVR_ATMega323_IAR/settings/rtosdemo.dbgdt +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/Demo/AVR_ATMega323_IAR/settings/rtosdemo.dni b/Demo/AVR_ATMega323_IAR/settings/rtosdemo.dni deleted file mode 100644 index 9fdf1aa6d..000000000 --- a/Demo/AVR_ATMega323_IAR/settings/rtosdemo.dni +++ /dev/null @@ -1,41 +0,0 @@ -[DisAssemblyWindow] -NumStates=_ 1 -State 1=_ 1 -[Watch] -Watch 1=_ 1 "usCurrentNumberOfTasks" -Watch 2= -Watch 3= -[CodeCoverage] -State=_ 0 -[Profiling] -State=_ 0 -[TermIOSettings] -Filename=_ "" -InputMode=_ 1 -[QWatch] -WindowContent=_ 100 100 100 100 -[Desktop-Debug] -Wnd0=_ "Watch" "open" 44 0 1 -1 -1 -1 -1 1139 276 1595 524 100 100 100 100 -Wnd1=_ "Memory" "open" 44 0 1 -1 -1 -1 -1 1139 217 1591 939 1 1872 0 1872 0 1 0 1 0 -Wnd2=_ "CallStack" "open" 44 0 1 -1 -1 -1 -1 30 699 277 1037 1 -Wnd3=_ "Register" "open" 44 0 1 -1 -1 -1 -1 1237 0 1569 1019 0 0 0 0 -Wnd4=_ "Register" "open" 44 0 1 -1 -1 -1 -1 40 264 1312 986 0 0 0 0 -Wnd5=_ "Editor-DebugSource" "open" 44 0 1 -1 -1 -1 -1 169 991 1062 2036 "E:\Dev\FreeRTOS\Source\portable\IAR\ATMega323\portmacro.s90" 1 1 0 206 6825 6825 -Wnd6=_ "Disassembly" "open" 44 0 1 -1 -1 -4 -28 586 28 1196 854 -Wnd7=_ "Log" "closed" 44 0 1 -1 -1 -4 -28 872 845 1595 1069 -Wnd8=_ "Locals" "closed" 44 0 1 -1 -1 -1 -1 1139 0 1595 276 100 100 100 100 -Wnd9=_ "Terminal I/O" "closed" 44 0 1 -1 -1 -1 -1 1138 522 1595 826 -Maximized=_ 0 -Count=_ 10 -[TermIOLog] -LoggingEnabled=_ 0 -LogFile=_ "" -[Log file] -LoggingEnabled=_ 0 -LogFile=_ "" -Category=_ 0 -[Breakpoints] -Count=0 -[TraceHelper] -Enabled=0 -ShowSource=1 diff --git a/Demo/AVR_ATMega323_IAR/settings/rtosdemo.fmt b/Demo/AVR_ATMega323_IAR/settings/rtosdemo.fmt deleted file mode 100644 index 63403ba0c..000000000 --- a/Demo/AVR_ATMega323_IAR/settings/rtosdemo.fmt +++ /dev/null @@ -1,4 +0,0 @@ -[struct types] -Count=_ 0 -[watch formats] -Count=_ 0 diff --git a/Demo/AVR_ATMega323_IAR/settings/rtosdemo.ini b/Demo/AVR_ATMega323_IAR/settings/rtosdemo.ini deleted file mode 100644 index e433ec84f..000000000 --- a/Demo/AVR_ATMega323_IAR/settings/rtosdemo.ini +++ /dev/null @@ -1,10 +0,0 @@ -[WorkspaceWindow] -ExpandedNodes=_ 1 "rtosdemo" 1 "rtosdemo/Debug" -SelectedTab=_ 0 -[Desktop-Workspace] -Wnd0=_ "TextEditor" "open" 44 0 1 -1 -1 -1 -1 378 14 1227 671 "E:\Dev\FreeRTOS\Source\tasks.c" 1 1 0 1170 37742 37742 -Wnd1=_ "TextEditor" "open" 44 0 1 -1 -1 -1 -1 81 81 930 738 "E:\Dev\FreeRTOS\Source\portable\IAR\ATMega323\portmacro.h" 1 1 0 66 3233 3233 -Wnd2=_ "Workspace2" "open" 44 0 1 -1 -1 -4 -28 0 0 352 713 276 27 27 -Wnd3=_ "Messages2" "open" 44 0 1 -1 -1 -4 -28 -6 714 1590 1104 5 "Build\Messages" 1580 "Find in Files\Line" 79 "Find in Files\Path" 474 "Find in Files\String" 948 "Tool Output\Output" 1560 -Maximized=_ 0 -Count=_ 4 diff --git a/Demo/AVR_ATMega323_IAR/settings/rtosdemo.wsdt b/Demo/AVR_ATMega323_IAR/settings/rtosdemo.wsdt deleted file mode 100644 index 9f6c956df..000000000 --- a/Demo/AVR_ATMega323_IAR/settings/rtosdemo.wsdt +++ /dev/null @@ -1,49 +0,0 @@ - - - - - - rtosdemo/Debug - - - - - - - - - 246272727 - - 20115330776 - - - - - - TabID-12388-19520 - Workspace - Workspace - - - rtosdemortosdemo/Demo Sourcertosdemo/Kernel Sourcertosdemo/portheap.c - - - - 0TabID-19172-8303BuildBuildTabID-954-28216Debug LogDebug-Log0 - - - - - - TextEditorC:\E\Dev\FreeRTOS\Demo\AVR_ATMega323_IAR\regtest.c0190661966190TextEditorC:\E\Dev\FreeRTOS\Demo\AVR_ATMega323_IAR\main.c012355005500TextEditorC:\E\Dev\FreeRTOS\Demo\Common\Minimal\crflash.c0170680768070100000010000001 - - - - - - - iaridepm1-2-2619320-2-2162161115714165638230000638889-2-23071402-2-214043091002857317901116429166667 - - - - diff --git a/Demo/AVR_ATMega323_WinAVR/FreeRTOSConfig.h b/Demo/AVR_ATMega323_WinAVR/FreeRTOSConfig.h deleted file mode 100644 index 6223507d4..000000000 --- a/Demo/AVR_ATMega323_WinAVR/FreeRTOSConfig.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -#include - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 1 -#define configUSE_TICK_HOOK 0 -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 8000000 ) -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 85 ) -#define configTOTAL_HEAP_SIZE ( (size_t ) ( 1500 ) ) -#define configMAX_TASK_NAME_LEN ( 8 ) -#define configUSE_TRACE_FACILITY 0 -#define configUSE_16_BIT_TICKS 1 -#define configIDLE_SHOULD_YIELD 1 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 1 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 0 -#define INCLUDE_uxTaskPriorityGet 0 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 0 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/AVR_ATMega323_WinAVR/ParTest/ParTest.c b/Demo/AVR_ATMega323_WinAVR/ParTest/ParTest.c deleted file mode 100644 index f7026e8e7..000000000 --- a/Demo/AVR_ATMega323_WinAVR/ParTest/ParTest.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V2.0.0 - - + Use scheduler suspends in place of critical sections. - -Changes from V2.6.0 - - + Replaced the inb() and outb() functions with direct memory - access. This allows the port to be built with the 20050414 build of - WinAVR. -*/ - -#include "FreeRTOS.h" -#include "task.h" -#include "partest.h" - -/*----------------------------------------------------------- - * Simple parallel port IO routines. - *-----------------------------------------------------------*/ - -#define partstALL_BITS_OUTPUT ( ( unsigned portCHAR ) 0xff ) -#define partstALL_OUTPUTS_OFF ( ( unsigned portCHAR ) 0xff ) -#define partstMAX_OUTPUT_LED ( ( unsigned portCHAR ) 7 ) - -static volatile unsigned portCHAR ucCurrentOutputValue = partstALL_OUTPUTS_OFF; /*lint !e956 File scope parameters okay here. */ - -/*-----------------------------------------------------------*/ - -void vParTestInitialise( void ) -{ - ucCurrentOutputValue = partstALL_OUTPUTS_OFF; - - /* Set port B direction to outputs. Start with all output off. */ - DDRB = partstALL_BITS_OUTPUT; - PORTB = ucCurrentOutputValue; -} -/*-----------------------------------------------------------*/ - -void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) -{ -unsigned portCHAR ucBit = ( unsigned portCHAR ) 1; - - if( uxLED <= partstMAX_OUTPUT_LED ) - { - ucBit <<= uxLED; - } - - vTaskSuspendAll(); - { - if( xValue == pdTRUE ) - { - ucBit ^= ( unsigned portCHAR ) 0xff; - ucCurrentOutputValue &= ucBit; - } - else - { - ucCurrentOutputValue |= ucBit; - } - - PORTB = ucCurrentOutputValue; - } - xTaskResumeAll(); -} -/*-----------------------------------------------------------*/ - -void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) -{ -unsigned portCHAR ucBit; - - if( uxLED <= partstMAX_OUTPUT_LED ) - { - ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED; - - vTaskSuspendAll(); - { - if( ucCurrentOutputValue & ucBit ) - { - ucCurrentOutputValue &= ~ucBit; - } - else - { - ucCurrentOutputValue |= ucBit; - } - - PORTB = ucCurrentOutputValue; - } - xTaskResumeAll(); - } -} - - diff --git a/Demo/AVR_ATMega323_WinAVR/main.c b/Demo/AVR_ATMega323_WinAVR/main.c deleted file mode 100644 index af45c456c..000000000 --- a/Demo/AVR_ATMega323_WinAVR/main.c +++ /dev/null @@ -1,258 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * Creates all the demo application tasks, then starts the scheduler. The WEB - * documentation provides more details of the demo application tasks. - * - * Main. c also creates a task called "Check". This only executes every three - * seconds but has the highest priority so is guaranteed to get processor time. - * Its main function is to check that all the other tasks are still operational. - * Each task that does not flash an LED maintains a unique count that is - * incremented each time the task successfully completes its function. Should - * any error occur within such a task the count is permanently halted. The - * check task inspects the count of each task to ensure it has changed since - * the last time the check task executed. If all the count variables have - * changed all the tasks are still executing error free, and the check task - * toggles an LED. Should any task contain an error at any time the LED toggle - * will stop. - * - * The LED flash and communications test tasks do not maintain a count. - */ - -/* -Changes from V1.2.0 - - + Changed the baud rate for the serial test from 19200 to 57600. - -Changes from V1.2.3 - - + The integer and comtest tasks are now used when the cooperative scheduler - is being used. Previously they were only used with the preemptive - scheduler. - -Changes from V1.2.5 - - + Set the baud rate to 38400. This has a smaller error percentage with an - 8MHz clock (according to the manual). - -Changes from V2.0.0 - - + Delay periods are now specified using variables and constants of - portTickType rather than unsigned portLONG. - -Changes from V2.6.1 - - + The IAR and WinAVR AVR ports are now maintained separately. - -Changes from V4.0.5 - - + Modified to demonstrate the use of co-routines. - -*/ - -#include -#include - -#ifdef GCC_MEGA_AVR - /* EEPROM routines used only with the WinAVR compiler. */ - #include -#endif - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" -#include "croutine.h" - -/* Demo file headers. */ -#include "PollQ.h" -#include "integer.h" -#include "serial.h" -#include "comtest.h" -#include "crflash.h" -#include "print.h" -#include "partest.h" -#include "regtest.h" - -/* Priority definitions for most of the tasks in the demo application. Some -tasks just use the idle priority. */ -#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) - -/* Baud rate used by the serial port tasks. */ -#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 38400 ) - -/* LED used by the serial port tasks. This is toggled on each character Tx, -and mainCOM_TEST_LED + 1 is toggles on each character Rx. */ -#define mainCOM_TEST_LED ( 4 ) - -/* LED that is toggled by the check task. The check task periodically checks -that all the other tasks are operating without error. If no errors are found -the LED is toggled. If an error is found at any time the LED is never toggles -again. */ -#define mainCHECK_TASK_LED ( 7 ) - -/* The period between executions of the check task. */ -#define mainCHECK_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS ) - -/* An address in the EEPROM used to count resets. This is used to check that -the demo application is not unexpectedly resetting. */ -#define mainRESET_COUNT_ADDRESS ( ( void * ) 0x50 ) - -/* The number of coroutines to create. */ -#define mainNUM_FLASH_COROUTINES ( 3 ) - -/* - * The task function for the "Check" task. - */ -static void vErrorChecks( void *pvParameters ); - -/* - * Checks the unique counts of other tasks to ensure they are still operational. - * Flashes an LED if everything is okay. - */ -static void prvCheckOtherTasksAreStillRunning( void ); - -/* - * Called on boot to increment a count stored in the EEPROM. This is used to - * ensure the CPU does not reset unexpectedly. - */ -static void prvIncrementResetCount( void ); - -/* - * The idle hook is used to scheduler co-routines. - */ -void vApplicationIdleHook( void ); - -/*-----------------------------------------------------------*/ - -portSHORT main( void ) -{ - prvIncrementResetCount(); - - /* Setup the LED's for output. */ - vParTestInitialise(); - - /* Create the standard demo tasks. */ - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartRegTestTasks(); - - /* Create the tasks defined within this file. */ - xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - - /* Create the co-routines that flash the LED's. */ - vStartFlashCoRoutines( mainNUM_FLASH_COROUTINES ); - - /* In this port, to use preemptive scheduler define configUSE_PREEMPTION - as 1 in portmacro.h. To use the cooperative scheduler define - configUSE_PREEMPTION as 0. */ - vTaskStartScheduler(); - - return 0; -} -/*-----------------------------------------------------------*/ - -static void vErrorChecks( void *pvParameters ) -{ -static volatile unsigned portLONG ulDummyVariable = 3UL; - - /* The parameters are not used. */ - ( void ) pvParameters; - - /* Cycle for ever, delaying then checking all the other tasks are still - operating without error. */ - for( ;; ) - { - vTaskDelay( mainCHECK_PERIOD ); - - /* Perform a bit of 32bit maths to ensure the registers used by the - integer tasks get some exercise. The result here is not important - - see the demo application documentation for more info. */ - ulDummyVariable *= 3; - - prvCheckOtherTasksAreStillRunning(); - } -} -/*-----------------------------------------------------------*/ - -static void prvCheckOtherTasksAreStillRunning( void ) -{ -static portBASE_TYPE xErrorHasOccurred = pdFALSE; - - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - xErrorHasOccurred = pdTRUE; - } - - if( xAreComTestTasksStillRunning() != pdTRUE ) - { - xErrorHasOccurred = pdTRUE; - } - - if( xArePollingQueuesStillRunning() != pdTRUE ) - { - xErrorHasOccurred = pdTRUE; - } - - if( xAreRegTestTasksStillRunning() != pdTRUE ) - { - xErrorHasOccurred = pdTRUE; - } - - if( xErrorHasOccurred == pdFALSE ) - { - /* Toggle the LED if everything is okay so we know if an error occurs even if not - using console IO. */ - vParTestToggleLED( mainCHECK_TASK_LED ); - } -} -/*-----------------------------------------------------------*/ - -static void prvIncrementResetCount( void ) -{ -unsigned portCHAR ucCount; - - eeprom_read_block( &ucCount, mainRESET_COUNT_ADDRESS, sizeof( ucCount ) ); - ucCount++; - eeprom_write_byte( mainRESET_COUNT_ADDRESS, ucCount ); -} -/*-----------------------------------------------------------*/ - -void vApplicationIdleHook( void ) -{ - vCoRoutineSchedule(); -} - diff --git a/Demo/AVR_ATMega323_WinAVR/makefile b/Demo/AVR_ATMega323_WinAVR/makefile deleted file mode 100644 index 9bd557d1b..000000000 --- a/Demo/AVR_ATMega323_WinAVR/makefile +++ /dev/null @@ -1,428 +0,0 @@ -# WinAVR Sample makefile written by Eric B. Weddington, Jörg Wunsch, et al. -# Released to the Public Domain -# Please read the make user manual! -# -# Additional material for this makefile was submitted by: -# Tim Henigan -# Peter Fleury -# Reiner Patommel -# Sander Pool -# Frederik Rouleau -# Markus Pfaff -# -# On command line: -# -# make all = Make software. -# -# make clean = Clean out built project files. -# -# make coff = Convert ELF to AVR COFF (for use with AVR Studio 3.x or VMLAB). -# -# make extcoff = Convert ELF to AVR Extended COFF (for use with AVR Studio -# 4.07 or greater). -# -# make program = Download the hex file to the device, using avrdude. Please -# customize the avrdude settings below first! -# -# make filename.s = Just compile filename.c into the assembler code only -# -# To rebuild project do "make clean" then "make all". -# - - -# MCU name -MCU = atmega323 - -# Output format. (can be srec, ihex, binary) -FORMAT = ihex - -# Target file name (without extension). -TARGET = rtosdemo - -# Optimization level, can be [0, 1, 2, 3, s]. 0 turns off optimization. -# (Note: 3 is not always the best optimization level. See avr-libc FAQ.) -OPT = s - - -# List C source files here. (C dependencies are automatically generated.) -DEMO_DIR = ../Common/Minimal -SOURCE_DIR = ../../Source -PORT_DIR = ../../Source/portable/GCC/ATMega323 - -SRC = \ -main.c \ -ParTest/ParTest.c \ -serial/serial.c \ -regtest.c \ -$(SOURCE_DIR)/tasks.c \ -$(SOURCE_DIR)/queue.c \ -$(SOURCE_DIR)/list.c \ -$(SOURCE_DIR)/croutine.c \ -$(SOURCE_DIR)/portable/MemMang/heap_1.c \ -$(PORT_DIR)/port.c \ -$(DEMO_DIR)/crflash.c \ -$(DEMO_DIR)/integer.c \ -$(DEMO_DIR)/PollQ.c \ -$(DEMO_DIR)/comtest.c - - -# If there is more than one source file, append them above, or modify and -# uncomment the following: -#SRC += foo.c bar.c - -# You can also wrap lines by appending a backslash to the end of the line: -#SRC += baz.c \ -#xyzzy.c - - - -# List Assembler source files here. -# Make them always end in a capital .S. Files ending in a lowercase .s -# will not be considered source files but generated files (assembler -# output from the compiler), and will be deleted upon "make clean"! -# Even though the DOS/Win* filesystem matches both .s and .S the same, -# it will preserve the spelling of the filenames, and gcc itself does -# care about how the name is spelled on its command-line. -ASRC = - - -# List any extra directories to look for include files here. -# Each directory must be seperated by a space. -EXTRAINCDIRS = - - -# Optional compiler flags. -# -g: generate debugging information (for GDB, or for COFF conversion) -# -O*: optimization level -# -f...: tuning, see gcc manual and avr-libc documentation -# -Wall...: warning level -# -Wa,...: tell GCC to pass this to the assembler. -# -ahlms: create assembler listing - -DEBUG_LEVEL=-g -WARNINGS=-Wall -Wextra -Wshadow -Wpointer-arith -Wbad-function-cast -Wcast-align -Wsign-compare \ - -Waggregate-return -Wstrict-prototypes -Wmissing-prototypes -Wmissing-declarations -Wunused - -CFLAGS = -D GCC_MEGA_AVR -I. -I../../Source/include -I../Common/include \ -$(DEBUG_LEVEL) -O$(OPT) \ --fsigned-char -funsigned-bitfields -fpack-struct -fshort-enums \ -$(WARNINGS) \ --Wa,-adhlns=$(<:.c=.lst) \ -$(patsubst %,-I%,$(EXTRAINCDIRS)) - - -# Set a "language standard" compiler flag. -# Unremark just one line below to set the language standard to use. -# gnu99 = C99 + GNU extensions. See GCC manual for more information. -#CFLAGS += -std=c89 -#CFLAGS += -std=gnu89 -#CFLAGS += -std=c99 -CFLAGS += -std=gnu99 - - - -# Optional assembler flags. -# -Wa,...: tell GCC to pass this to the assembler. -# -ahlms: create listing -# -gstabs: have the assembler create line number information; note that -# for use in COFF files, additional information about filenames -# and function names needs to be present in the assembler source -# files -- see avr-libc docs [FIXME: not yet described there] -ASFLAGS = -Wa,-adhlns=$(<:.S=.lst),-gstabs - - - -# Optional linker flags. -# -Wl,...: tell GCC to pass this to linker. -# -Map: create map file -# --cref: add cross reference to map file -LDFLAGS = -Wl,-Map=$(TARGET).map,--cref - - - -# Additional libraries - -# Minimalistic printf version -#LDFLAGS += -Wl,-u,vfprintf -lprintf_min - -# Floating point printf version (requires -lm below) -#LDFLAGS += -Wl,-u,vfprintf -lprintf_flt - -# -lm = math library -LDFLAGS += -lm - - - - -# Programming support using avrdude. Settings and variables. - -# Programming hardware: alf avr910 avrisp bascom bsd -# dt006 pavr picoweb pony-stk200 sp12 stk200 stk500 -# -# Type: avrdude -c ? -# to get a full listing. -# -AVRDUDE_PROGRAMMER = stk500 - - -AVRDUDE_PORT = com1 # programmer connected to serial device -#AVRDUDE_PORT = lpt1 # programmer connected to parallel port - -AVRDUDE_WRITE_FLASH = -U flash:w:$(TARGET).hex -#AVRDUDE_WRITE_EEPROM = -U eeprom:w:$(TARGET).eep - -AVRDUDE_FLAGS = -p $(MCU) -P $(AVRDUDE_PORT) -c $(AVRDUDE_PROGRAMMER) - -# Uncomment the following if you want avrdude's erase cycle counter. -# Note that this counter needs to be initialized first using -Yn, -# see avrdude manual. -#AVRDUDE_ERASE += -y - -# Uncomment the following if you do /not/ wish a verification to be -# performed after programming the device. -#AVRDUDE_FLAGS += -V - -# Increase verbosity level. Please use this when submitting bug -# reports about avrdude. See -# to submit bug reports. -#AVRDUDE_FLAGS += -v -v - - - - -# --------------------------------------------------------------------------- - -# Define directories, if needed. -DIRAVR = c:/winavr -DIRAVRBIN = $(DIRAVR)/bin -DIRAVRUTILS = $(DIRAVR)/utils/bin -DIRINC = . -DIRLIB = $(DIRAVR)/avr/lib - - -# Define programs and commands. -SHELL = sh - -CC = avr-gcc - -OBJCOPY = avr-objcopy -OBJDUMP = avr-objdump -SIZE = avr-size - - -# Programming support using avrdude. -AVRDUDE = avrdude - - -REMOVE = rm -f -COPY = cp - -HEXSIZE = $(SIZE) --target=$(FORMAT) $(TARGET).hex -ELFSIZE = $(SIZE) -A $(TARGET).elf - - - -# Define Messages -# English -MSG_ERRORS_NONE = Errors: none -MSG_BEGIN = -------- begin -------- -MSG_END = -------- end -------- -MSG_SIZE_BEFORE = Size before: -MSG_SIZE_AFTER = Size after: -MSG_COFF = Converting to AVR COFF: -MSG_EXTENDED_COFF = Converting to AVR Extended COFF: -MSG_FLASH = Creating load file for Flash: -MSG_EEPROM = Creating load file for EEPROM: -MSG_EXTENDED_LISTING = Creating Extended Listing: -MSG_SYMBOL_TABLE = Creating Symbol Table: -MSG_LINKING = Linking: -MSG_COMPILING = Compiling: -MSG_ASSEMBLING = Assembling: -MSG_CLEANING = Cleaning project: - - - - -# Define all object files. -OBJ = $(SRC:.c=.o) $(ASRC:.S=.o) - -# Define all listing files. -LST = $(ASRC:.S=.lst) $(SRC:.c=.lst) - -# Combine all necessary flags and optional flags. -# Add target processor to flags. -ALL_CFLAGS = -mmcu=$(MCU) -I. $(CFLAGS) -ALL_ASFLAGS = -mmcu=$(MCU) -I. -x assembler-with-cpp $(ASFLAGS) - - - -# Default target. -all: begin gccversion sizebefore $(TARGET).elf $(TARGET).hex $(TARGET).eep \ - $(TARGET).lss $(TARGET).sym sizeafter finished end - - -# Eye candy. -# AVR Studio 3.x does not check make's exit code but relies on -# the following magic strings to be generated by the compile job. -begin: - @echo - @echo $(MSG_BEGIN) - -finished: - @echo $(MSG_ERRORS_NONE) - -end: - @echo $(MSG_END) - @echo - - -# Display size of file. -sizebefore: - @if [ -f $(TARGET).elf ]; then echo; echo $(MSG_SIZE_BEFORE); $(ELFSIZE); echo; fi - -sizeafter: - @if [ -f $(TARGET).elf ]; then echo; echo $(MSG_SIZE_AFTER); $(ELFSIZE); echo; fi - - - -# Display compiler version information. -gccversion : - @$(CC) --version - - - - -# Convert ELF to COFF for use in debugging / simulating in -# AVR Studio or VMLAB. -COFFCONVERT=$(OBJCOPY) --debugging \ - --change-section-address .data-0x800000 \ - --change-section-address .bss-0x800000 \ - --change-section-address .noinit-0x800000 \ - --change-section-address .eeprom-0x810000 - - -coff: $(TARGET).elf - @echo - @echo $(MSG_COFF) $(TARGET).cof - $(COFFCONVERT) -O coff-avr $< $(TARGET).cof - - -extcoff: $(TARGET).elf - @echo - @echo $(MSG_EXTENDED_COFF) $(TARGET).cof - $(COFFCONVERT) -O coff-ext-avr $< $(TARGET).cof - - - - -# Program the device. -program: $(TARGET).hex $(TARGET).eep - $(AVRDUDE) $(AVRDUDE_FLAGS) $(AVRDUDE_WRITE_FLASH) $(AVRDUDE_WRITE_EEPROM) - - - - -# Create final output files (.hex, .eep) from ELF output file. -%.hex: %.elf - @echo - @echo $(MSG_FLASH) $@ - $(OBJCOPY) -O $(FORMAT) -R .eeprom $< $@ - -%.eep: %.elf - @echo - @echo $(MSG_EEPROM) $@ - -$(OBJCOPY) -j .eeprom --set-section-flags=.eeprom="alloc,load" \ - --change-section-lma .eeprom=0 -O $(FORMAT) $< $@ - -# Create extended listing file from ELF output file. -%.lss: %.elf - @echo - @echo $(MSG_EXTENDED_LISTING) $@ - $(OBJDUMP) -h -S $< > $@ - -# Create a symbol table from ELF output file. -%.sym: %.elf - @echo - @echo $(MSG_SYMBOL_TABLE) $@ - avr-nm -n $< > $@ - - - -# Link: create ELF output file from object files. -.SECONDARY : $(TARGET).elf -.PRECIOUS : $(OBJ) -%.elf: $(OBJ) - @echo - @echo $(MSG_LINKING) $@ - $(CC) $(ALL_CFLAGS) $(OBJ) --output $@ $(LDFLAGS) - - -# Compile: create object files from C source files. -%.o : %.c - @echo - @echo $(MSG_COMPILING) $< - $(CC) -c $(ALL_CFLAGS) $< -o $@ - - -# Compile: create assembler files from C source files. -%.s : %.c - $(CC) -S $(ALL_CFLAGS) $< -o $@ - - -# Assemble: create object files from assembler source files. -%.o : %.S - @echo - @echo $(MSG_ASSEMBLING) $< - $(CC) -c $(ALL_ASFLAGS) $< -o $@ - - - - - - -# Target: clean project. -clean: begin clean_list finished end - -clean_list : - @echo - @echo $(MSG_CLEANING) - $(REMOVE) $(TARGET).hex - $(REMOVE) $(TARGET).eep - $(REMOVE) $(TARGET).obj - $(REMOVE) $(TARGET).cof - $(REMOVE) $(TARGET).elf - $(REMOVE) $(TARGET).map - $(REMOVE) $(TARGET).obj - $(REMOVE) $(TARGET).a90 - $(REMOVE) $(TARGET).sym - $(REMOVE) $(TARGET).lnk - $(REMOVE) $(TARGET).lss - $(REMOVE) $(OBJ) - $(REMOVE) $(LST) - $(REMOVE) $(SRC:.c=.s) - $(REMOVE) $(SRC:.c=.d) - - -# Automatically generate C source code dependencies. -# (Code originally taken from the GNU make user manual and modified -# (See README.txt Credits).) -# -# Note that this will work with sh (bash) and sed that is shipped with WinAVR -# (see the SHELL variable defined above). -# This may not work with other shells or other seds. -# -%.d: %.c - set -e; $(CC) -MM $(ALL_CFLAGS) $< \ - | sed 's,\(.*\)\.o[ :]*,\1.o \1.d : ,g' > $@; \ - [ -s $@ ] || rm -f $@ - - -# Remove the '-' if you want to see the dependency files generated. --include $(SRC:.c=.d) - - - -# Listing of phony targets. -.PHONY : all begin finish end sizebefore sizeafter gccversion coff extcoff \ - clean clean_list program - diff --git a/Demo/AVR_ATMega323_WinAVR/regtest.c b/Demo/AVR_ATMega323_WinAVR/regtest.c deleted file mode 100644 index d486cc162..000000000 --- a/Demo/AVR_ATMega323_WinAVR/regtest.c +++ /dev/null @@ -1,362 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Demo file headers. */ -#include "regtest.h" - -/* - * Test tasks that sets registers to known values, then checks to ensure the - * values remain as expected. Test 1 and test 2 use different values. - */ -static void prvRegisterCheck1( void *pvParameters ); -static void prvRegisterCheck2( void *pvParameters ); - -/* Set to a non zero value should an error be found. */ -portBASE_TYPE xRegTestError = pdFALSE; - -/*-----------------------------------------------------------*/ - -void vStartRegTestTasks( void ) -{ - xTaskCreate( prvRegisterCheck1, "Reg1", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); - xTaskCreate( prvRegisterCheck2, "Reg2", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xAreRegTestTasksStillRunning( void ) -{ -portBASE_TYPE xReturn; - - /* If a register was found to contain an unexpected value then the - xRegTestError variable would have been set to a non zero value. */ - if( xRegTestError == pdFALSE ) - { - xReturn = pdTRUE; - } - else - { - xReturn = pdFALSE; - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -static void prvRegisterCheck1( void *pvParameters ) -{ - ( void ) pvParameters; - - for( ;; ) - { - asm( "LDI r31, 5" ); - asm( "MOV r0, r31" ); - asm( "LDI r31, 6" ); - asm( "MOV r1, r31" ); - asm( "LDI r31, 7" ); - asm( "MOV r2, r31" ); - asm( "LDI r31, 8" ); - asm( "MOV r3, r31" ); - asm( "LDI r31, 9" ); - asm( "MOV r4, r31" ); - asm( "LDI r31, 10" ); - asm( "MOV r5, r31" ); - asm( "LDI r31, 11" ); - asm( "MOV r6, r31" ); - asm( "LDI r31, 12" ); - asm( "MOV r7, r31" ); - asm( "LDI r31, 13" ); - asm( "MOV r8, r31" ); - asm( "LDI r31, 14" ); - asm( "MOV r9, r31" ); - asm( "LDI r31, 15" ); - asm( "MOV r10, r31" ); - asm( "LDI r31, 16" ); - asm( "MOV r11, r31" ); - asm( "LDI r31, 17" ); - asm( "MOV r12, r31" ); - asm( "LDI r31, 18" ); - asm( "MOV r13, r31" ); - asm( "LDI r31, 19" ); - asm( "MOV r14, r31" ); - asm( "LDI r31, 20" ); - asm( "MOV r15, r31" ); - asm( "LDI r16, 21" ); - asm( "LDI r17, 22" ); - asm( "LDI r18, 23" ); - asm( "LDI r19, 24" ); - asm( "LDI r20, 25" ); - asm( "LDI r21, 26" ); - asm( "LDI r22, 27" ); - asm( "LDI r23, 28" ); - asm( "LDI r24, 29" ); - asm( "LDI r25, 30" ); - asm( "LDI r26, 31" ); - asm( "LDI r27, 32" ); - asm( "LDI r30, 33" ); - - asm( "LDI r31, 5" ); - asm( "CPSE r31, r0" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 6" ); - asm( "CPSE r31, r1" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 7" ); - asm( "CPSE r31, r2" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 8" ); - asm( "CPSE r31, r3" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 9" ); - asm( "CPSE r31, r4" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 10" ); - asm( "CPSE r31, r5" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 11" ); - asm( "CPSE r31, r6" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 12" ); - asm( "CPSE r31, r7" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 13" ); - asm( "CPSE r31, r8" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 14" ); - asm( "CPSE r31, r9" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 15" ); - asm( "CPSE r31, r10" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 16" ); - asm( "CPSE r31, r11" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 17" ); - asm( "CPSE r31, r12" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 18" ); - asm( "CPSE r31, r13" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 19" ); - asm( "CPSE r31, r14" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 20" ); - asm( "CPSE r31, r15" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 21" ); - asm( "CPSE r31, r16" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 22" ); - asm( "CPSE r31, r17" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 23" ); - asm( "CPSE r31, r18" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 24" ); - asm( "CPSE r31, r19" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 25" ); - asm( "CPSE r31, r20" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 26" ); - asm( "CPSE r31, r21" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 27" ); - asm( "CPSE r31, r22" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 28" ); - asm( "CPSE r31, r23" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 29" ); - asm( "CPSE r31, r24" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 30" ); - asm( "CPSE r31, r25" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 31" ); - asm( "CPSE r31, r26" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 32" ); - asm( "CPSE r31, r27" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 33" ); - asm( "CPSE r31, r30" ); - asm( "STS xRegTestError, r0" ); - } -} -/*-----------------------------------------------------------*/ - -static void prvRegisterCheck2( void *pvParameters ) -{ - ( void ) pvParameters; - - for( ;; ) - { - asm( "LDI r31, 1" ); - asm( "MOV r0, r31" ); - asm( "LDI r31, 2" ); - asm( "MOV r1, r31" ); - asm( "LDI r31, 3" ); - asm( "MOV r2, r31" ); - asm( "LDI r31, 4" ); - asm( "MOV r3, r31" ); - asm( "LDI r31, 5" ); - asm( "MOV r4, r31" ); - asm( "LDI r31, 6" ); - asm( "MOV r5, r31" ); - asm( "LDI r31, 7" ); - asm( "MOV r6, r31" ); - asm( "LDI r31, 8" ); - asm( "MOV r7, r31" ); - asm( "LDI r31, 9" ); - asm( "MOV r8, r31" ); - asm( "LDI r31, 10" ); - asm( "MOV r9, r31" ); - asm( "LDI r31, 11" ); - asm( "MOV r10, r31" ); - asm( "LDI r31, 12" ); - asm( "MOV r11, r31" ); - asm( "LDI r31, 13" ); - asm( "MOV r12, r31" ); - asm( "LDI r31, 14" ); - asm( "MOV r13, r31" ); - asm( "LDI r31, 15" ); - asm( "MOV r14, r31" ); - asm( "LDI r31, 16" ); - asm( "MOV r15, r31" ); - asm( "LDI r16, 17" ); - asm( "LDI r17, 18" ); - asm( "LDI r18, 19" ); - asm( "LDI r19, 20" ); - asm( "LDI r20, 21" ); - asm( "LDI r21, 22" ); - asm( "LDI r22, 23" ); - asm( "LDI r23, 24" ); - asm( "LDI r24, 25" ); - asm( "LDI r25, 26" ); - asm( "LDI r26, 27" ); - asm( "LDI r27, 28" ); - asm( "LDI r30, 29" ); - - asm( "LDI r31, 1" ); - asm( "CPSE r31, r0" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 2" ); - asm( "CPSE r31, r1" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 3" ); - asm( "CPSE r31, r2" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 4" ); - asm( "CPSE r31, r3" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 5" ); - asm( "CPSE r31, r4" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 6" ); - asm( "CPSE r31, r5" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 7" ); - asm( "CPSE r31, r6" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 8" ); - asm( "CPSE r31, r7" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 9" ); - asm( "CPSE r31, r8" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 10" ); - asm( "CPSE r31, r9" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 11" ); - asm( "CPSE r31, r10" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 12" ); - asm( "CPSE r31, r11" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 13" ); - asm( "CPSE r31, r12" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 14" ); - asm( "CPSE r31, r13" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 15" ); - asm( "CPSE r31, r14" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 16" ); - asm( "CPSE r31, r15" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 17" ); - asm( "CPSE r31, r16" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 18" ); - asm( "CPSE r31, r17" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 19" ); - asm( "CPSE r31, r18" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 20" ); - asm( "CPSE r31, r19" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 21" ); - asm( "CPSE r31, r20" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 22" ); - asm( "CPSE r31, r21" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 23" ); - asm( "CPSE r31, r22" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 24" ); - asm( "CPSE r31, r23" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 25" ); - asm( "CPSE r31, r24" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 26" ); - asm( "CPSE r31, r25" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 27" ); - asm( "CPSE r31, r26" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 28" ); - asm( "CPSE r31, r27" ); - asm( "STS xRegTestError, r0" ); - asm( "LDI r31, 29" ); - asm( "CPSE r31, r30" ); - asm( "STS xRegTestError, r0" ); - } -} - diff --git a/Demo/AVR_ATMega323_WinAVR/regtest.h b/Demo/AVR_ATMega323_WinAVR/regtest.h deleted file mode 100644 index 93110d1af..000000000 --- a/Demo/AVR_ATMega323_WinAVR/regtest.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef REG_TEST_H -#define REG_TEST_H - -void vStartRegTestTasks( void ); -portBASE_TYPE xAreRegTestTasksStillRunning( void ); - -#endif - diff --git a/Demo/AVR_ATMega323_WinAVR/serial/serial.c b/Demo/AVR_ATMega323_WinAVR/serial/serial.c deleted file mode 100644 index fc3124b48..000000000 --- a/Demo/AVR_ATMega323_WinAVR/serial/serial.c +++ /dev/null @@ -1,224 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V1.2.3 - - + The function xPortInitMinimal() has been renamed to - xSerialPortInitMinimal() and the function xPortInit() has been renamed - to xSerialPortInit(). - -Changes from V2.0.0 - - + Delay periods are now specified using variables and constants of - portTickType rather than unsigned portLONG. - + xQueueReceiveFromISR() used in place of xQueueReceive() within the ISR. - -Changes from V2.6.0 - - + Replaced the inb() and outb() functions with direct memory - access. This allows the port to be built with the 20050414 build of - WinAVR. -*/ - -/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER. */ - - -#include -#include -#include "FreeRTOS.h" -#include "queue.h" -#include "task.h" -#include "serial.h" - -#define serBAUD_DIV_CONSTANT ( ( unsigned portLONG ) 16 ) - -/* Constants for writing to UCSRB. */ -#define serRX_INT_ENABLE ( ( unsigned portCHAR ) 0x80 ) -#define serRX_ENABLE ( ( unsigned portCHAR ) 0x10 ) -#define serTX_ENABLE ( ( unsigned portCHAR ) 0x08 ) -#define serTX_INT_ENABLE ( ( unsigned portCHAR ) 0x20 ) - -/* Constants for writing to UCSRC. */ -#define serUCSRC_SELECT ( ( unsigned portCHAR ) 0x80 ) -#define serEIGHT_DATA_BITS ( ( unsigned portCHAR ) 0x06 ) - -static xQueueHandle xRxedChars; -static xQueueHandle xCharsForTx; - -#define vInterruptOn() \ -{ \ - unsigned portCHAR ucByte; \ - \ - ucByte = UCSRB; \ - ucByte |= serTX_INT_ENABLE; \ - UCSRB = ucByte; \ -} -/*-----------------------------------------------------------*/ - -#define vInterruptOff() \ -{ \ - unsigned portCHAR ucInByte; \ - \ - ucInByte = UCSRB; \ - ucInByte &= ~serTX_INT_ENABLE; \ - UCSRB = ucInByte; \ -} -/*-----------------------------------------------------------*/ - -xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) -{ -unsigned portLONG ulBaudRateCounter; -unsigned portCHAR ucByte; - - portENTER_CRITICAL(); - { - /* Create the queues used by the com test task. */ - xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); - xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); - - /* Calculate the baud rate register value from the equation in the - data sheet. */ - ulBaudRateCounter = ( configCPU_CLOCK_HZ / ( serBAUD_DIV_CONSTANT * ulWantedBaud ) ) - ( unsigned portLONG ) 1; - - /* Set the baud rate. */ - ucByte = ( unsigned portCHAR ) ( ulBaudRateCounter & ( unsigned portLONG ) 0xff ); - UBRRL = ucByte; - - ulBaudRateCounter >>= ( unsigned portLONG ) 8; - ucByte = ( unsigned portCHAR ) ( ulBaudRateCounter & ( unsigned portLONG ) 0xff ); - UBRRH = ucByte; - - /* Enable the Rx interrupt. The Tx interrupt will get enabled - later. Also enable the Rx and Tx. */ - UCSRB = ( serRX_INT_ENABLE | serRX_ENABLE | serTX_ENABLE ); - - /* Set the data bits to 8. */ - UCSRC = ( serUCSRC_SELECT | serEIGHT_DATA_BITS ); - } - portEXIT_CRITICAL(); - - /* Unlike other ports, this serial code does not allow for more than one - com port. We therefore don't return a pointer to a port structure and can - instead just return NULL. */ - return NULL; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) -{ - /* Only one port is supported. */ - ( void ) pxPort; - - /* Get the next character from the buffer. Return false if no characters - are available, or arrive before xBlockTime expires. */ - if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) - { - return pdTRUE; - } - else - { - return pdFALSE; - } -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) -{ - /* Only one port is supported. */ - ( void ) pxPort; - - /* Return false if after the block time there is no room on the Tx queue. */ - if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) - { - return pdFAIL; - } - - vInterruptOn(); - - return pdPASS; -} -/*-----------------------------------------------------------*/ - -void vSerialClose( xComPortHandle xPort ) -{ -unsigned portCHAR ucByte; - - /* The parameter is not used. */ - ( void ) xPort; - - /* Turn off the interrupts. We may also want to delete the queues and/or - re-install the original ISR. */ - - portENTER_CRITICAL(); - { - vInterruptOff(); - ucByte = UCSRB; - ucByte &= ~serRX_INT_ENABLE; - UCSRB = ucByte; - } - portEXIT_CRITICAL(); -} -/*-----------------------------------------------------------*/ - -SIGNAL( SIG_UART_RECV ) -{ -signed portCHAR cChar; - - /* Get the character and post it on the queue of Rxed characters. - If the post causes a task to wake force a context switch as the woken task - may have a higher priority than the task we have interrupted. */ - cChar = UDR; - - if( xQueueSendFromISR( xRxedChars, &cChar, pdFALSE ) ) - { - taskYIELD(); - } -} -/*-----------------------------------------------------------*/ - -SIGNAL( SIG_UART_DATA ) -{ -signed portCHAR cChar, cTaskWoken; - - if( xQueueReceiveFromISR( xCharsForTx, &cChar, &cTaskWoken ) == pdTRUE ) - { - /* Send the next character queued for Tx. */ - UDR = cChar; - } - else - { - /* Queue empty, nothing to send. */ - vInterruptOff(); - } -} - diff --git a/Demo/CORTEX_LM3S102_GCC/Demo1/FreeRTOSConfig.h b/Demo/CORTEX_LM3S102_GCC/Demo1/FreeRTOSConfig.h deleted file mode 100644 index 51d644b1a..000000000 --- a/Demo/CORTEX_LM3S102_GCC/Demo1/FreeRTOSConfig.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 1 -#define configUSE_TICK_HOOK 0 -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 ) -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 59 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1468 ) ) -#define configMAX_TASK_NAME_LEN ( 3 ) -#define configUSE_TRACE_FACILITY 0 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 0 -#define configUSE_CO_ROUTINES 1 - -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 ) -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 0 -#define INCLUDE_uxTaskPriorityGet 0 -#define INCLUDE_vTaskDelete 0 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 0 -#define INCLUDE_vTaskDelayUntil 0 -#define INCLUDE_vTaskDelay 1 - - - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/CORTEX_LM3S102_GCC/Demo1/main.c b/Demo/CORTEX_LM3S102_GCC/Demo1/main.c deleted file mode 100644 index 16541674a..000000000 --- a/Demo/CORTEX_LM3S102_GCC/Demo1/main.c +++ /dev/null @@ -1,604 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * This demo application creates six co-routines and two tasks (three including - * the idle task). The co-routines execute as part of the idle task hook. - * - * Five of the created co-routines are the standard 'co-routine flash' - * co-routines contained within the Demo/Common/Minimal/crflash.c file and - * documented on the FreeRTOS.org WEB site. - * - * The 'LCD Task' rotates a string on the LCD, delaying between each character - * as necessitated by the slow interface, and delaying between each string just - * long enough to enable the text to be read. - * - * The sixth co-routine and final task control the transmission and reception - * of a string to UART 0. The co-routine periodically sends the first - * character of the string to the UART, with the UART's TxEnd interrupt being - * used to transmit the remaining characters. The UART's RxEnd interrupt - * receives the characters and places them on a queue to be processed by the - * 'COMs Rx' task. An error is latched should an unexpected character be - * received, or any character be received out of sequence. - * - * A loopback connector is required to ensure that each character transmitted - * on the UART is also received on the same UART. For test purposes the UART - * FIFO's are not utalised in order to maximise the interrupt overhead. Also - * a pseudo random interval is used between the start of each transmission in - * order that the resultant interrupts are more randomly distributed and - * therefore more likely to highlight any problems. - * - * The flash co-routines control LED's zero to four. LED five is toggled each - * time the string is transmitted on the UART. LED six is toggled each time - * the string is CORRECTLY received on the UART. LED seven is latched on should - * an error be detected in any task or co-routine. - * - * In addition the idle task makes repetative calls to - * prvSetAndCheckRegisters(). This simply loads the general purpose registers - * with a known value, then checks each register to ensure the held value is - * still correct. As a low priority task this checking routine is likely to - * get repeatedly swapped in and out. A register being found to contain an - * incorrect value is therefore indicative of an error in the task switching - * mechansim. - * - */ - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" -#include "croutine.h" - -/* Demo application include files. */ -#include "partest.h" -#include "crflash.h" - -/* Library include files. */ -#include "DriverLib.h" - -/* The time to delay between writing each character to the LCD. */ -#define mainCHAR_WRITE_DELAY ( 2 / portTICK_RATE_MS ) - -/* The time to delay between writing each string to the LCD. */ -#define mainSTRING_WRITE_DELAY ( 400 / portTICK_RATE_MS ) - -/* The number of flash co-routines to create. */ -#define mainNUM_FLASH_CO_ROUTINES ( 5 ) - -/* The length of the queue used to pass received characters to the Comms Rx -task. */ -#define mainRX_QUEUE_LEN ( 5 ) - -/* The priority of the co-routine used to initiate the transmission of the -string on UART 0. */ -#define mainTX_CO_ROUTINE_PRIORITY ( 1 ) - -/* Only one co-routine is created so its index is not important. */ -#define mainTX_CO_ROUTINE_INDEX ( 0 ) - -/* The time between transmissions of the string on UART 0. This is pseudo -random in order to generate a bit or randomness to when the interrupts occur.*/ -#define mainMIN_TX_DELAY ( 40 / portTICK_RATE_MS ) -#define mainMAX_TX_DELAY ( ( portTickType ) 0x7f ) -#define mainOFFSET_TIME ( ( portTickType ) 3 ) - -/* The time the Comms Rx task should wait to receive a character. This should -be slightly longer than the time between transmissions. If we do not receive -a character after this time then there must be an error in the transmission or -the timing of the transmission. */ -#define mainCOMMS_RX_DELAY ( mainMAX_TX_DELAY + 20 ) - -/* The task priorites. */ -#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY ) -#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) - -/* The LED's toggled by the various tasks. */ -#define mainCOMMS_FAIL_LED ( 7 ) -#define mainCOMMS_RX_LED ( 6 ) -#define mainCOMMS_TX_LED ( 5 ) - -/* The baud rate used by the UART comms tasks/co-routine. */ -#define mainBAUD_RATE ( 57600 ) - -/* FIFO setting for the UART. The FIFO is not used to create a better test. */ -#define mainFIFO_SET ( 0x10 ) - -/* The string that is transmitted on the UART contains sequentially the -characters from mainFIRST_TX_CHAR to mainLAST_TX_CHAR. */ -#define mainFIRST_TX_CHAR '0' -#define mainLAST_TX_CHAR 'z' - -/* Just used to walk through the program memory in order that some random data -can be generated. */ -#define mainTOTAL_PROGRAM_MEMORY ( ( unsigned portLONG * ) ( 8 * 1024 ) ) -#define mainFIRST_PROGRAM_BYTES ( ( unsigned portLONG * ) 4 ) - -/* The error routine that is called if the driver library encounters an error. */ -#ifdef DEBUG -void -__error__(char *pcFilename, unsigned long ulLine) -{ -} -#endif - -/*-----------------------------------------------------------*/ - -/* - * The task that rotates text on the LCD. - */ -static void vLCDTask( void * pvParameters ); - -/* - * The task that receives the characters from UART 0. - */ -static void vCommsRxTask( void * pvParameters ); - -/* - * The co-routine that periodically initiates the transmission of the string on - * the UART. - */ -static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); - -/* - * Writes a string the the LCD. - */ -static void prvWriteString( const portCHAR *pcString ); - -/* - * Initialisation routine for the UART. - */ -static void vSerialInit( void ); - -/* - * Thread safe write to the PDC. - */ -static void prvPDCWrite( portCHAR cAddress, portCHAR cData ); - -/* - * Function to simply set a known value into the general purpose registers - * then read them back to ensure they remain set correctly. An incorrect value - * being indicative of an error in the task switching mechanism. - */ -void prvSetAndCheckRegisters( void ); - -/* - * Latch the LED that indicates that an error has occurred. - */ -void vSetErrorLED( void ); - -/* - * Sets up the PLL and ports used by the demo. - */ -static void prvSetupHardware( void ); - -/*-----------------------------------------------------------*/ - -/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines -defined within this file. */ -unsigned portBASE_TYPE uxErrorStatus = pdPASS; - -/* The next character to transmit. */ -static portCHAR cNextChar; - -/* The queue used to transmit characters from the interrupt to the Comms Rx -task. */ -static xQueueHandle xCommsQueue; - -/*-----------------------------------------------------------*/ - -void Main( void ) -{ - /* Create the queue used to communicate between the UART ISR and the Comms - Rx task. */ - xCommsQueue = xQueueCreate( mainRX_QUEUE_LEN, sizeof( portCHAR ) ); - - /* Setup the ports used by the demo and the clock. */ - prvSetupHardware(); - - /* Create the co-routines that flash the LED's. */ - vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES ); - - /* Create the co-routine that initiates the transmission of characters - on the UART. */ - xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX ); - - /* Create the LCD and Comms Rx tasks. */ - xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL ); - xTaskCreate( vCommsRxTask, "CMS", configMINIMAL_STACK_SIZE, NULL, mainCOMMS_RX_TASK_PRIORITY, NULL ); - - /* Start the scheduler running the tasks and co-routines just created. */ - vTaskStartScheduler(); - - /* Should not get here unless we did not have enough memory to start the - scheduler. */ - for( ;; ); -} -/*-----------------------------------------------------------*/ - -static void prvSetupHardware( void ) -{ - /* Setup the PLL. */ - SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); - - /* Initialise the hardware used to talk to the LCD, LED's and UART. */ - PDCInit(); - vParTestInitialise(); - vSerialInit(); -} -/*-----------------------------------------------------------*/ - -void vApplicationIdleHook( void ) -{ - /* The co-routines are executed in the idle task using the idle task - hook. */ - for( ;; ) - { - /* Schedule the co-routines. */ - vCoRoutineSchedule(); - - /* Run the register check function between each co-routine. */ - prvSetAndCheckRegisters(); - } -} -/*-----------------------------------------------------------*/ - -static void prvWriteString( const portCHAR *pcString ) -{ - /* Write pcString to the LED, pausing between each character. */ - prvPDCWrite(PDC_LCD_CSR, LCD_CLEAR); - while( *pcString ) - { - vTaskDelay( mainCHAR_WRITE_DELAY ); - prvPDCWrite( PDC_LCD_RAM, *pcString ); - pcString++; - } -} -/*-----------------------------------------------------------*/ - -void vLCDTask( void * pvParameters ) -{ -unsigned portBASE_TYPE uxIndex; -const unsigned portCHAR ucCFGData[] = { - 0x30, /* Set data bus to 8-bits. */ - 0x30, - 0x30, - 0x3C, /* Number of lines/font. */ - 0x08, /* Display off. */ - 0x01, /* Display clear. */ - 0x06, /* Entry mode [cursor dir][shift]. */ - 0x0C /* Display on [display on][curson on][blinking on]. */ - }; - -/* The strings that are written to the LCD. */ -const portCHAR *pcStringsToDisplay[] = { - "Stellaris", - "Demo", - "One", - "www.FreeRTOS.org", - "" - }; - - /* Configure the LCD. */ - uxIndex = 0; - while( uxIndex < sizeof( ucCFGData ) ) - { - prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] ); - uxIndex++; - vTaskDelay( mainCHAR_WRITE_DELAY ); - } - - /* Turn the LCD Backlight on. */ - prvPDCWrite( PDC_CSR, 0x01 ); - - /* Clear display. */ - vTaskDelay( mainCHAR_WRITE_DELAY ); - prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); - - uxIndex = 0; - for( ;; ) - { - /* Display the string on the LCD. */ - prvWriteString( pcStringsToDisplay[ uxIndex ] ); - - /* Move on to the next string - wrapping if necessary. */ - uxIndex++; - if( *( pcStringsToDisplay[ uxIndex ] ) == 0x00 ) - { - uxIndex = 0; - /* Longer pause on the last string to be sent. */ - vTaskDelay( mainSTRING_WRITE_DELAY * 2 ); - } - - /* Wait until it is time to move onto the next string. */ - vTaskDelay( mainSTRING_WRITE_DELAY ); - } -} -/*-----------------------------------------------------------*/ - -static void vCommsRxTask( void * pvParameters ) -{ -static portCHAR cRxedChar, cExpectedChar; - - /* Set the char we expect to receive to the start of the string. */ - cExpectedChar = mainFIRST_TX_CHAR; - - for( ;; ) - { - /* Wait for a character to be received. */ - xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY ); - - /* Was the character recived (if any) the expected character. */ - if( cRxedChar != cExpectedChar ) - { - /* Got an unexpected character. This can sometimes occur when - reseting the system using the debugger leaving characters already - in the UART regsters. */ - uxErrorStatus = pdFAIL; - - /* Resync by waiting for the end of the current string. */ - while( cRxedChar != mainLAST_TX_CHAR ) - { - while( !xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, portMAX_DELAY ) ); - } - - /* The next expected character is the start of the string again. */ - cExpectedChar = mainFIRST_TX_CHAR; - } - else - { - if( cExpectedChar == mainLAST_TX_CHAR ) - { - /* We have reached the end of the string - we now expect to - receive the first character in the string again. The LED is - toggled to indicate that the entire string was received without - error. */ - vParTestToggleLED( mainCOMMS_RX_LED ); - cExpectedChar = mainFIRST_TX_CHAR; - } - else - { - /* We got the expected character, we now expect to receive the - next character in the string. */ - cExpectedChar++; - } - } - } -} -/*-----------------------------------------------------------*/ - -static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) -{ -portTickType xDelayPeriod; -static unsigned portLONG *pulRandomBytes = mainFIRST_PROGRAM_BYTES; - - /* Co-routine MUST start with a call to crSTART. */ - crSTART( xHandle ); - - for(;;) - { - /* Was the previously transmitted string received correctly? */ - if( uxErrorStatus != pdPASS ) - { - /* An error was encountered so set the error LED. */ - vSetErrorLED(); - } - - /* The next character to Tx is the first in the string. */ - cNextChar = mainFIRST_TX_CHAR; - - UARTIntDisable( UART0_BASE, UART_INT_TX ); - { - /* Send the first character. */ - if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) - { - HWREG( UART0_BASE + UART_O_DR ) = cNextChar; - } - - /* Move the variable to the char to Tx on so the ISR transmits - the next character in the string once this one has completed. */ - cNextChar++; - } - UARTIntEnable(UART0_BASE, UART_INT_TX); - - /* Toggle the LED to show a new string is being transmitted. */ - vParTestToggleLED( mainCOMMS_TX_LED ); - - /* Delay before we start the string off again. A pseudo-random delay - is used as this will provide a better test. */ - xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes ); - - pulRandomBytes++; - if( pulRandomBytes > mainTOTAL_PROGRAM_MEMORY ) - { - pulRandomBytes = mainFIRST_PROGRAM_BYTES; - } - - /* Make sure we don't wait too long... */ - xDelayPeriod &= mainMAX_TX_DELAY; - - /* ...but we do want to wait. */ - if( xDelayPeriod < mainMIN_TX_DELAY ) - { - xDelayPeriod = mainMIN_TX_DELAY; - } - - /* Block for the random(ish) time. */ - crDELAY( xHandle, xDelayPeriod ); - } - - /* Co-routine MUST end with a call to crEND. */ - crEND(); -} -/*-----------------------------------------------------------*/ - -static void vSerialInit( void ) -{ - /* Enable the UART. GPIOA has already been initialised. */ - SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); - - /* Set GPIO A0 and A1 as peripheral function. They are used to output the - UART signals. */ - GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); - - /* Configure the UART for 8-N-1 operation. */ - UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); - - /* We dont want to use the fifo. This is for test purposes to generate - as many interrupts as possible. */ - HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; - - /* Enable both Rx and Tx interrupts. */ - HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX ); - IntEnable( INT_UART0 ); -} -/*-----------------------------------------------------------*/ - -void vUART_ISR(void) -{ -unsigned portLONG ulStatus; -portCHAR cRxedChar; -portBASE_TYPE xTaskWokenByPost = pdFALSE; - - /* What caused the interrupt. */ - ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); - - /* Clear the interrupt. */ - UARTIntClear( UART0_BASE, ulStatus ); - - /* Was an Rx interrpt pending? */ - if( ulStatus & UART_INT_RX ) - { - if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) ) - { - /* Get the char from the buffer and post it onto the queue of - Rxed chars. Posting the character should wake the task that is - blocked on the queue waiting for characters. */ - cRxedChar = ( portCHAR ) HWREG( UART0_BASE + UART_O_DR ); - xTaskWokenByPost = xQueueSendFromISR( xCommsQueue, &cRxedChar, xTaskWokenByPost ); - } - } - - /* Was a Tx interrupt pending? */ - if( ulStatus & UART_INT_TX ) - { - /* Send the next character in the string. We are not using the FIFO. */ - if( cNextChar <= mainLAST_TX_CHAR ) - { - if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) - { - HWREG( UART0_BASE + UART_O_DR ) = cNextChar; - } - cNextChar++; - } - } - - if( xTaskWokenByPost ) - { - /* If a task was woken by the character being received then we force - a context switch to occur in case the task is of higher priority than - the currently executing task (i.e. the task that this interrupt - interrupted.) */ - portEND_SWITCHING_ISR( xTaskWokenByPost ); - } -} -/*-----------------------------------------------------------*/ - -static void prvPDCWrite( portCHAR cAddress, portCHAR cData ) -{ - vTaskSuspendAll(); - { - PDCWrite( cAddress, cData ); - } - xTaskResumeAll(); -} -/*-----------------------------------------------------------*/ - -void vSetErrorLED( void ) -{ - vParTestSetLED( mainCOMMS_FAIL_LED, pdTRUE ); -} -/*-----------------------------------------------------------*/ - -void prvSetAndCheckRegisters( void ) -{ - /* Fill the general purpose registers with known values. */ - __asm volatile( " mov r11, #10\n" - " add r0, r11, #1\n" - " add r1, r11, #2\n" - " add r2, r11, #3\n" - " add r3, r11, #4\n" - " add r4, r11, #5\n" - " add r5, r11, #6\n" - " add r6, r11, #7\n" - " add r7, r11, #8\n" - " add r8, r11, #9\n" - " add r9, r11, #10\n" - " add r10, r11, #11\n" - " add r12, r11, #12" ); - - /* Check the values are as expected. */ - __asm volatile( " cmp r11, #10\n" - " bne set_error_led\n" - " cmp r0, #11\n" - " bne set_error_led\n" - " cmp r1, #12\n" - " bne set_error_led\n" - " cmp r2, #13\n" - " bne set_error_led\n" - " cmp r3, #14\n" - " bne set_error_led\n" - " cmp r4, #15\n" - " bne set_error_led\n" - " cmp r5, #16\n" - " bne set_error_led\n" - " cmp r6, #17\n" - " bne set_error_led\n" - " cmp r7, #18\n" - " bne set_error_led\n" - " cmp r8, #19\n" - " bne set_error_led\n" - " cmp r9, #20\n" - " bne set_error_led\n" - " cmp r10, #21\n" - " bne set_error_led\n" - " cmp r12, #22\n" - " bne set_error_led\n" - " bx lr" ); - - __asm volatile( "set_error_led:\n" - " push {r14}\n" - " ldr r1, =vSetErrorLED\n" - " blx r1\n" - " pop {r14}\n" - " bx lr" ); -} -/*-----------------------------------------------------------*/ diff --git a/Demo/CORTEX_LM3S102_GCC/Demo1/readme.txt b/Demo/CORTEX_LM3S102_GCC/Demo1/readme.txt deleted file mode 100644 index 208a58805..000000000 --- a/Demo/CORTEX_LM3S102_GCC/Demo1/readme.txt +++ /dev/null @@ -1,3 +0,0 @@ -Move these two fines into the Demo/CORTEX_LM3S102_GCC directory to run Demo 1. - -See the port documentation on the www.FreeRTOS.org site for more information. diff --git a/Demo/CORTEX_LM3S102_GCC/Demo2/FreeRTOSConfig.h b/Demo/CORTEX_LM3S102_GCC/Demo2/FreeRTOSConfig.h deleted file mode 100644 index b39c502a1..000000000 --- a/Demo/CORTEX_LM3S102_GCC/Demo2/FreeRTOSConfig.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 1 -#define configUSE_TICK_HOOK 0 -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 ) -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 59 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1240 ) ) -#define configMAX_TASK_NAME_LEN ( 3 ) -#define configUSE_TRACE_FACILITY 0 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 0 -#define configUSE_CO_ROUTINES 1 - -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 ) -#define configMAX_CO_ROUTINE_PRIORITIES ( 3 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 0 -#define INCLUDE_uxTaskPriorityGet 0 -#define INCLUDE_vTaskDelete 0 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 0 -#define INCLUDE_vTaskDelayUntil 0 -#define INCLUDE_vTaskDelay 1 - - - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/CORTEX_LM3S102_GCC/Demo2/main.c b/Demo/CORTEX_LM3S102_GCC/Demo2/main.c deleted file mode 100644 index 4228e83a8..000000000 --- a/Demo/CORTEX_LM3S102_GCC/Demo2/main.c +++ /dev/null @@ -1,600 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * This demo application creates seven co-routines and one task (two including - * the idle task). The co-routines execute as part of the idle task hook. - * - * Five of the created co-routines are the standard 'co-routine flash' - * co-routines contained within the Demo/Common/Minimal/crflash.c file and - * documented on the FreeRTOS.org WEB site. - * - * The 'LCD Task' rotates a string on the LCD, delaying between each character - * as necessitated by the slow interface, and delaying between each string just - * long enough to enable the text to be read. - * - * The sixth co-routine controls the transmission of a string to UART 0. The - * co-routine periodically sends the first character of the string to the UART, - * with the UART's TxEnd interrupt being used to transmit the remaining - * characters. The UART's RxEnd interrupt receives the characters and places - * them on a queue to be processed by the seventh and final co-routine. An - * error is latched should an unexpected character be received, or any - * character be received out of sequence. - * - * A loopback connector is required to ensure that each character transmitted - * on the UART is also received on the same UART. For test purposes the UART - * FIFO's are not utalised in order to maximise the interrupt overhead. Also - * a pseudo random interval is used between the start of each transmission in - * order that the resultant interrupts are more randomly distributed and - * therefore more likely to highlight any problems. - * - * The flash co-routines control LED's zero to four. LED five is toggled each - * time the string is transmitted on the UART. LED six is toggled each time - * the string is CORRECTLY received on the UART. LED seven is latched on should - * an error be detected in any task or co-routine. - * - * In addition the idle task makes repetative calls to - * prvSetAndCheckRegisters(). This simply loads the general purpose registers - * with a known value, then checks each register to ensure the held value is - * still correct. As a low priority task this checking routine is likely to - * get repeatedly swapped in and out. A register being found to contain an - * incorrect value is therefore indicative of an error in the task switching - * mechansim. - * - */ - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" -#include "croutine.h" - -/* Demo application include files. */ -#include "partest.h" -#include "crflash.h" - -/* Library include files. */ -#include "DriverLib.h" - -/* The time to delay between writing each character to the LCD. */ -#define mainCHAR_WRITE_DELAY ( 2 / portTICK_RATE_MS ) - -/* The time to delay between writing each string to the LCD. */ -#define mainSTRING_WRITE_DELAY ( 400 / portTICK_RATE_MS ) - -/* The number of flash co-routines to create. */ -#define mainNUM_FLASH_CO_ROUTINES ( 5 ) - -/* The length of the queue used to pass received characters to the Comms Rx -task. */ -#define mainRX_QUEUE_LEN ( 5 ) - -/* The priority of the co-routine used to initiate the transmission of the -string on UART 0. */ -#define mainTX_CO_ROUTINE_PRIORITY ( 1 ) - -/* The priority of the co-routine used to receive characters from the UART. */ -#define mainRX_CO_ROUTINE_PRIORITY ( 2 ) - -/* Only one co-routine is created so its index is not important. */ -#define mainTX_CO_ROUTINE_INDEX ( 0 ) -#define mainRX_CO_ROUTINE_INDEX ( 0 ) - -/* The time between transmissions of the string on UART 0. This is pseudo -random in order to generate a bit or randomness to when the interrupts occur.*/ -#define mainMIN_TX_DELAY ( 40 / portTICK_RATE_MS ) -#define mainMAX_TX_DELAY ( ( portTickType ) 0x7f ) -#define mainOFFSET_TIME ( ( portTickType ) 3 ) - -/* The time the Comms Rx task should wait to receive a character. This should -be slightly longer than the time between transmissions. If we do not receive -a character after this time then there must be an error in the transmission or -the timing of the transmission. */ -#define mainCOMMS_RX_DELAY ( mainMAX_TX_DELAY + 20 ) - -/* The task priorites. */ -#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY ) -#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) - -/* The LED's toggled by the various tasks. */ -#define mainCOMMS_FAIL_LED ( 7 ) -#define mainCOMMS_RX_LED ( 6 ) -#define mainCOMMS_TX_LED ( 5 ) - -/* The baud rate used by the UART comms tasks/co-routine. */ -#define mainBAUD_RATE ( 57600 ) - -/* FIFO setting for the UART. The FIFO is not used to create a better test. */ -#define mainFIFO_SET ( 0x10 ) - -/* The string that is transmitted on the UART contains sequentially the -characters from mainFIRST_TX_CHAR to mainLAST_TX_CHAR. */ -#define mainFIRST_TX_CHAR '0' -#define mainLAST_TX_CHAR 'z' - -/* Just used to walk through the program memory in order that some random data -can be generated. */ -#define mainTOTAL_PROGRAM_MEMORY ( ( unsigned portLONG * ) ( 8 * 1024 ) ) -#define mainFIRST_PROGRAM_BYTES ( ( unsigned portLONG * ) 4 ) - -/* The error routine that is called if the driver library encounters an error. */ -#ifdef DEBUG -void -__error__(char *pcFilename, unsigned long ulLine) -{ -} -#endif - -/*-----------------------------------------------------------*/ - -/* - * The task that rotates text on the LCD. - */ -static void vLCDTask( void * pvParameters ); - -/* - * The task that receives the characters from UART 0. - */ -static void vCommsRxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); - -/* - * The co-routine that periodically initiates the transmission of the string on - * the UART. - */ -static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); - -/* - * Writes a string the the LCD. - */ -static void prvWriteString( const portCHAR *pcString ); - -/* - * Initialisation routine for the UART. - */ -static void vSerialInit( void ); - -/* - * Thread safe write to the PDC. - */ -static void prvPDCWrite( portCHAR cAddress, portCHAR cData ); - -/* - * Function to simply set a known value into the general purpose registers - * then read them back to ensure they remain set correctly. An incorrect value - * being indicative of an error in the task switching mechanism. - */ -void prvSetAndCheckRegisters( void ); - -/* - * Latch the LED that indicates that an error has occurred. - */ -void vSetErrorLED( void ); - -/* - * Sets up the PLL and ports used by the demo. - */ -static void prvSetupHardware( void ); - -/*-----------------------------------------------------------*/ - -/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines -defined within this file. */ -unsigned portBASE_TYPE uxErrorStatus = pdPASS; - -/* The next character to transmit. */ -static portCHAR cNextChar; - -/* The queue used to transmit characters from the interrupt to the Comms Rx -task. */ -static xQueueHandle xCommsQueue; - -/*-----------------------------------------------------------*/ - -void Main( void ) -{ - /* Create the queue used to communicate between the UART ISR and the Comms - Rx task. */ - xCommsQueue = xQueueCreate( mainRX_QUEUE_LEN, sizeof( portCHAR ) ); - - /* Setup the ports used by the demo and the clock. */ - prvSetupHardware(); - - /* Create the co-routines that flash the LED's. */ - vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES ); - - /* Create the co-routine that initiates the transmission of characters - on the UART. */ - xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX ); - - /* Create the co-routine that receives characters from the UART. */ - xCoRoutineCreate( vCommsRxCoRoutine, mainRX_CO_ROUTINE_PRIORITY, mainRX_CO_ROUTINE_INDEX ); - - /* Create the LCD task. */ - xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL ); - - /* Start the scheduler running the tasks and co-routines just created. */ - vTaskStartScheduler(); - - /* Should not get here unless we did not have enough memory to start the - scheduler. */ - for( ;; ); -} -/*-----------------------------------------------------------*/ - -static void prvSetupHardware( void ) -{ - /* Setup the PLL. */ - SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); - - /* Initialise the hardware used to talk to the LCD, LED's and UART. */ - PDCInit(); - vParTestInitialise(); - vSerialInit(); -} -/*-----------------------------------------------------------*/ - -void vApplicationIdleHook( void ) -{ - /* The co-routines are executed in the idle task using the idle task - hook. */ - for( ;; ) - { - /* Schedule the co-routines. */ - vCoRoutineSchedule(); - - /* Run the register check function between each co-routine. */ - prvSetAndCheckRegisters(); - } -} -/*-----------------------------------------------------------*/ - -static void prvWriteString( const portCHAR *pcString ) -{ - /* Write pcString to the LED, pausing between each character. */ - prvPDCWrite(PDC_LCD_CSR, LCD_CLEAR); - while( *pcString ) - { - vTaskDelay( mainCHAR_WRITE_DELAY ); - prvPDCWrite( PDC_LCD_RAM, *pcString ); - pcString++; - } -} -/*-----------------------------------------------------------*/ - -void vLCDTask( void * pvParameters ) -{ -unsigned portBASE_TYPE uxIndex; -const unsigned portCHAR ucCFGData[] = { - 0x30, /* Set data bus to 8-bits. */ - 0x30, - 0x30, - 0x3C, /* Number of lines/font. */ - 0x08, /* Display off. */ - 0x01, /* Display clear. */ - 0x06, /* Entry mode [cursor dir][shift]. */ - 0x0C /* Display on [display on][curson on][blinking on]. */ - }; - -/* The strings that are written to the LCD. */ -const portCHAR *pcStringsToDisplay[] = { - "Stellaris", - "Demo", - "Two", - "www.FreeRTOS.org", - "" - }; - - /* Configure the LCD. */ - uxIndex = 0; - while( uxIndex < sizeof( ucCFGData ) ) - { - prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] ); - uxIndex++; - vTaskDelay( mainCHAR_WRITE_DELAY ); - } - - /* Turn the LCD Backlight on. */ - prvPDCWrite( PDC_CSR, 0x01 ); - - /* Clear display. */ - vTaskDelay( mainCHAR_WRITE_DELAY ); - prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); - - uxIndex = 0; - for( ;; ) - { - /* Display the string on the LCD. */ - prvWriteString( pcStringsToDisplay[ uxIndex ] ); - - /* Move on to the next string - wrapping if necessary. */ - uxIndex++; - if( *( pcStringsToDisplay[ uxIndex ] ) == 0x00 ) - { - uxIndex = 0; - /* Longer pause on the last string to be sent. */ - vTaskDelay( mainSTRING_WRITE_DELAY * 2 ); - } - - /* Wait until it is time to move onto the next string. */ - vTaskDelay( mainSTRING_WRITE_DELAY ); - } -} -/*-----------------------------------------------------------*/ - -static void vCommsRxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) -{ -static portCHAR cRxedChar, cExpectedChar = mainFIRST_TX_CHAR; -portBASE_TYPE xResult; - - crSTART( xHandle ); - - for( ;; ) - { - /* Wait for a character to be received. */ - crQUEUE_RECEIVE( xHandle, xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY, &xResult ); - - /* Was the character recived (if any) the expected character. */ - if( ( cRxedChar != cExpectedChar ) || ( xResult != pdPASS ) ) - { - /* Got an unexpected character. This can sometimes occur when - reseting the system using the debugger leaving characters already - in the UART regsters. */ - uxErrorStatus = pdFAIL; - - /* Resync by waiting for the end of the current string. */ - while( cRxedChar != mainLAST_TX_CHAR ) - { - crQUEUE_RECEIVE( xHandle, xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY, &xResult ); - } - - /* The next expected character is the start of the string again. */ - cExpectedChar = mainFIRST_TX_CHAR; - } - else - { - if( cExpectedChar == mainLAST_TX_CHAR ) - { - /* We have reached the end of the string - we now expect to - receive the first character in the string again. The LED is - toggled to indicate that the entire string was received without - error. */ - vParTestToggleLED( mainCOMMS_RX_LED ); - cExpectedChar = mainFIRST_TX_CHAR; - } - else - { - /* We got the expected character, we now expect to receive the - next character in the string. */ - cExpectedChar++; - } - } - } - - crEND(); -} -/*-----------------------------------------------------------*/ - -static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) -{ -portTickType xDelayPeriod; -static unsigned portLONG *pulRandomBytes = mainFIRST_PROGRAM_BYTES; - - /* Co-routine MUST start with a call to crSTART. */ - crSTART( xHandle ); - - for(;;) - { - /* Was the previously transmitted string received correctly? */ - if( uxErrorStatus != pdPASS ) - { - /* An error was encountered so set the error LED. */ - vSetErrorLED(); - } - - /* The next character to Tx is the first in the string. */ - cNextChar = mainFIRST_TX_CHAR; - - UARTIntDisable( UART0_BASE, UART_INT_TX ); - { - /* Send the first character. */ - if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) - { - HWREG( UART0_BASE + UART_O_DR ) = cNextChar; - } - - /* Move the variable to the char to Tx on so the ISR transmits - the next character in the string once this one has completed. */ - cNextChar++; - } - UARTIntEnable(UART0_BASE, UART_INT_TX); - - /* Toggle the LED to show a new string is being transmitted. */ - vParTestToggleLED( mainCOMMS_TX_LED ); - - /* Delay before we start the string off again. A pseudo-random delay - is used as this will provide a better test. */ - xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes ); - - pulRandomBytes++; - if( pulRandomBytes > mainTOTAL_PROGRAM_MEMORY ) - { - pulRandomBytes = mainFIRST_PROGRAM_BYTES; - } - - /* Make sure we don't wait too long... */ - xDelayPeriod &= mainMAX_TX_DELAY; - - /* ...but we do want to wait. */ - if( xDelayPeriod < mainMIN_TX_DELAY ) - { - xDelayPeriod = mainMIN_TX_DELAY; - } - - /* Block for the random(ish) time. */ - crDELAY( xHandle, xDelayPeriod ); - } - - /* Co-routine MUST end with a call to crEND. */ - crEND(); -} -/*-----------------------------------------------------------*/ - -static void vSerialInit( void ) -{ - /* Enable the UART. GPIOA has already been initialised. */ - SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); - - /* Set GPIO A0 and A1 as peripheral function. They are used to output the - UART signals. */ - GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); - - /* Configure the UART for 8-N-1 operation. */ - UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); - - /* We dont want to use the fifo. This is for test purposes to generate - as many interrupts as possible. */ - HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; - - /* Enable both Rx and Tx interrupts. */ - HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX ); - IntEnable( INT_UART0 ); -} -/*-----------------------------------------------------------*/ - -void vUART_ISR(void) -{ -unsigned portLONG ulStatus; -portCHAR cRxedChar; -portBASE_TYPE xTaskWokenByPost = pdFALSE; - - /* What caused the interrupt. */ - ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); - - /* Clear the interrupt. */ - UARTIntClear( UART0_BASE, ulStatus ); - - /* Was an Rx interrpt pending? */ - if( ulStatus & UART_INT_RX ) - { - if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) ) - { - /* Get the char from the buffer and post it onto the queue of - Rxed chars. Posting the character should wake the task that is - blocked on the queue waiting for characters. */ - cRxedChar = ( portCHAR ) HWREG( UART0_BASE + UART_O_DR ); - xTaskWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsQueue, &cRxedChar, xTaskWokenByPost ); - } - } - - /* Was a Tx interrupt pending? */ - if( ulStatus & UART_INT_TX ) - { - /* Send the next character in the string. We are not using the FIFO. */ - if( cNextChar <= mainLAST_TX_CHAR ) - { - if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) - { - HWREG( UART0_BASE + UART_O_DR ) = cNextChar; - } - cNextChar++; - } - } - - if( xTaskWokenByPost ) - { - /* We are posting to a co-routine rather than a task so don't bother - causing a task switch. */ - } -} -/*-----------------------------------------------------------*/ - -static void prvPDCWrite( portCHAR cAddress, portCHAR cData ) -{ - vTaskSuspendAll(); - { - PDCWrite( cAddress, cData ); - } - xTaskResumeAll(); -} -/*-----------------------------------------------------------*/ - -void vSetErrorLED( void ) -{ - vParTestSetLED( mainCOMMS_FAIL_LED, pdTRUE ); -} -/*-----------------------------------------------------------*/ - -void prvSetAndCheckRegisters( void ) -{ - /* Fill the general purpose registers with known values. */ - __asm volatile( " mov r11, #10\n" - " add r0, r11, #1\n" - " add r1, r11, #2\n" - " add r2, r11, #3\n" - " add r3, r11, #4\n" - " add r4, r11, #5\n" - " add r5, r11, #6\n" - " add r6, r11, #7\n" - " add r7, r11, #8\n" - " add r12, r11, #12" ); - - /* Check the values are as expected. */ - __asm volatile( " cmp r11, #10\n" - " bne set_error_led\n" - " cmp r0, #11\n" - " bne set_error_led\n" - " cmp r1, #12\n" - " bne set_error_led\n" - " cmp r2, #13\n" - " bne set_error_led\n" - " cmp r3, #14\n" - " bne set_error_led\n" - " cmp r4, #15\n" - " bne set_error_led\n" - " cmp r5, #16\n" - " bne set_error_led\n" - " cmp r6, #17\n" - " bne set_error_led\n" - " cmp r7, #18\n" - " bne set_error_led\n" - " cmp r12, #22\n" - " bne set_error_led\n" - " bx lr" ); - - __asm volatile( "set_error_led:\n" - " push {r14}\n" - " ldr r1, =vSetErrorLED\n" - " blx r1\n" - " pop {r14}\n" - " bx lr" ); -} -/*-----------------------------------------------------------*/ diff --git a/Demo/CORTEX_LM3S102_GCC/Demo2/readme.txt b/Demo/CORTEX_LM3S102_GCC/Demo2/readme.txt deleted file mode 100644 index e22c810ac..000000000 --- a/Demo/CORTEX_LM3S102_GCC/Demo2/readme.txt +++ /dev/null @@ -1,3 +0,0 @@ -Move these two fines into the Demo/CORTEX_LM3S102_GCC directory to run Demo 2. - -See the port documentation on the www.FreeRTOS.org site for more information. diff --git a/Demo/CORTEX_LM3S102_GCC/FreeRTOSConfig.h b/Demo/CORTEX_LM3S102_GCC/FreeRTOSConfig.h deleted file mode 100644 index 51d644b1a..000000000 --- a/Demo/CORTEX_LM3S102_GCC/FreeRTOSConfig.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 1 -#define configUSE_TICK_HOOK 0 -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 ) -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 59 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1468 ) ) -#define configMAX_TASK_NAME_LEN ( 3 ) -#define configUSE_TRACE_FACILITY 0 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 0 -#define configUSE_CO_ROUTINES 1 - -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 ) -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 0 -#define INCLUDE_uxTaskPriorityGet 0 -#define INCLUDE_vTaskDelete 0 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 0 -#define INCLUDE_vTaskDelayUntil 0 -#define INCLUDE_vTaskDelay 1 - - - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/CORTEX_LM3S102_GCC/Makefile b/Demo/CORTEX_LM3S102_GCC/Makefile deleted file mode 100644 index d587fd2e7..000000000 --- a/Demo/CORTEX_LM3S102_GCC/Makefile +++ /dev/null @@ -1,86 +0,0 @@ -#****************************************************************************** -# -# Makefile - Rules for building the driver library and examples. -# -# Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -# -# Software License Agreement -# -# Luminary Micro, Inc. (LMI) is supplying this software for use solely and -# exclusively on LMI's Stellaris Family of microcontroller products. -# -# The software is owned by LMI and/or its suppliers, and is protected under -# applicable copyright laws. All rights are reserved. Any use in violation -# of the foregoing restrictions may subject the user to criminal sanctions -# under applicable laws, as well as to civil liability for the breach of the -# terms and conditions of this license. -# -# THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -# OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -# LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -# CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -# -#****************************************************************************** - -include makedefs - -RTOS_SOURCE_DIR=../../Source -DEMO_SOURCE_DIR=../Common/Minimal - -CFLAGS+=-I hw_include -I . -I ${RTOS_SOURCE_DIR}/include -I ${RTOS_SOURCE_DIR}/portable/GCC/ARM_CM3 -I ../Common/include -D GCC_ARMCM3_LM3S102 -D inline= - -VPATH=${RTOS_SOURCE_DIR}:${RTOS_SOURCE_DIR}/portable/MemMang:${RTOS_SOURCE_DIR}/portable/GCC/ARM_CM3:${DEMO_SOURCE_DIR}:init:ParTest:hw_include - - -OBJS= ${COMPILER}/main.o \ - ${COMPILER}/pdc.o \ - ${COMPILER}/list.o \ - ${COMPILER}/queue.o \ - ${COMPILER}/tasks.o \ - ${COMPILER}/port.o \ - ${COMPILER}/heap_1.o \ - ${COMPILER}/ParTest.o \ - ${COMPILER}/crflash.o \ - ${COMPILER}/croutine.o -# ${COMPILER}/pendsv_handler.o - -INIT_OBJS= ${COMPILER}/startup.o - -LIBS= hw_include/libdriver.a - - -# -# The default rule, which causes init to be built. -# -all: ${COMPILER} \ - ${COMPILER}/RTOSDemo.axf \ - -# -# The rule to clean out all the build products -# - -clean: - @rm -rf ${COMPILER} ${wildcard *.bin} RTOSDemo.axf - -# -# The rule to create the target directory -# -${COMPILER}: - @mkdir ${COMPILER} - -${COMPILER}/RTOSDemo.axf: ${INIT_OBJS} ${OBJS} ${LIBS} -SCATTER_RTOSDemo=standalone.ld -ENTRY_RTOSDemo=ResetISR - -# -# -# Include the automatically generated dependency files. -# --include ${wildcard ${COMPILER}/*.d} __dummy__ - - - - - - diff --git a/Demo/CORTEX_LM3S102_GCC/ParTest/ParTest.c b/Demo/CORTEX_LM3S102_GCC/ParTest/ParTest.c deleted file mode 100644 index e344c1b7b..000000000 --- a/Demo/CORTEX_LM3S102_GCC/ParTest/ParTest.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/*----------------------------------------------------------- - * Simple parallel port IO routines. - *-----------------------------------------------------------*/ - -/* -*/ - - -#include "FreeRTOS.h" -#include "Task.h" -#include "partest.h" - -#include "pdc.h" - -#define partstPINS (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 Z | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7) - -#define partstALL_OUTPUTS_OFF ( ( unsigned portCHAR ) 0x00 ) -#define partstMAX_OUTPUT_LED ( ( unsigned portCHAR ) 8 ) - -static volatile unsigned portCHAR ucOutputValue = partstALL_OUTPUTS_OFF; - -void vParTestInitialise( void ) -{ - PDCInit(); - PDCWrite( PDC_LED, ucOutputValue ); -} -/*-----------------------------------------------------------*/ - -void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) -{ -unsigned portCHAR ucBit = ( unsigned portCHAR ) 1; - - vTaskSuspendAll(); - { - if( uxLED < partstMAX_OUTPUT_LED ) - { - ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED; - - if( xValue == pdFALSE ) - { - ucBit ^= ( unsigned portCHAR ) 0xff; - ucOutputValue &= ucBit; - } - else - { - ucOutputValue |= ucBit; - } - - PDCWrite( PDC_LED, ucOutputValue ); - } - } - xTaskResumeAll(); -} -/*-----------------------------------------------------------*/ - -void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) -{ -unsigned portCHAR ucBit; - - vTaskSuspendAll(); - { - if( uxLED < partstMAX_OUTPUT_LED ) - { - ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED; - - if( ucOutputValue & ucBit ) - { - ucOutputValue &= ~ucBit; - } - else - { - ucOutputValue |= ucBit; - } - - PDCWrite( PDC_LED, ucOutputValue ); - } - } - xTaskResumeAll(); -} - diff --git a/Demo/CORTEX_LM3S102_GCC/hw_include/DriverLib.h b/Demo/CORTEX_LM3S102_GCC/hw_include/DriverLib.h deleted file mode 100644 index f8383de66..000000000 --- a/Demo/CORTEX_LM3S102_GCC/hw_include/DriverLib.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef INCLUDE_DRIVER_LIB_H -#define INCLUDE_DRIVER_LIB_H - -#include "hw_ints.h" -#include "hw_uart.h" -#include "hw_memmap.h" -#include "hw_types.h" -#include "hw_nvic.h" -#include "hw_ssi.h" - -#include "gpio.h" -#include "interrupt.h" -#include "sysctl.h" -#include "uart.h" -#include "ssi.h" -#include "pdc.h" - -#endif diff --git a/Demo/CORTEX_LM3S102_GCC/hw_include/debug.h b/Demo/CORTEX_LM3S102_GCC/hw_include/debug.h deleted file mode 100644 index 2f259bd23..000000000 --- a/Demo/CORTEX_LM3S102_GCC/hw_include/debug.h +++ /dev/null @@ -1,56 +0,0 @@ -//***************************************************************************** -// -// debug.h - Macros for assisting debug of the driver library. -// -// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 523 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __DEBUG_H__ -#define __DEBUG_H__ - -//***************************************************************************** -// -// Prototype for the function that is called when an invalid argument is passed -// to an API. This is only used when doing a DEBUG build. -// -//***************************************************************************** -extern void __error__(char *pcFilename, unsigned long ulLine); - -//***************************************************************************** -// -// The ASSERT macro, which does the actual assertion checking. Typically, this -// will be for procedure arguments. -// -//***************************************************************************** -#ifdef DEBUG -#define ASSERT(expr) { \ - if(!(expr)) \ - { \ - __error__(__FILE__, __LINE__); \ - } \ - } -#else -#define ASSERT(expr) -#endif - -#endif // __DEBUG_H__ diff --git a/Demo/CORTEX_LM3S102_GCC/hw_include/gpio.h b/Demo/CORTEX_LM3S102_GCC/hw_include/gpio.h deleted file mode 100644 index cdc9a5b19..000000000 --- a/Demo/CORTEX_LM3S102_GCC/hw_include/gpio.h +++ /dev/null @@ -1,135 +0,0 @@ -//***************************************************************************** -// -// gpio.h - Defines and Macros for GPIO API. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 523 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __GPIO_H__ -#define __GPIO_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following values define the bit field for the ucPins argument to several -// of the APIs. -// -//***************************************************************************** -#define GPIO_PIN_0 0x00000001 // GPIO pin 0 -#define GPIO_PIN_1 0x00000002 // GPIO pin 1 -#define GPIO_PIN_2 0x00000004 // GPIO pin 2 -#define GPIO_PIN_3 0x00000008 // GPIO pin 3 -#define GPIO_PIN_4 0x00000010 // GPIO pin 4 -#define GPIO_PIN_5 0x00000020 // GPIO pin 5 -#define GPIO_PIN_6 0x00000040 // GPIO pin 6 -#define GPIO_PIN_7 0x00000080 // GPIO pin 7 - -//***************************************************************************** -// -// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and -// returned from GPIODirModeGet. -// -//***************************************************************************** -#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input -#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output -#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function - -//***************************************************************************** -// -// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and -// returned from GPIOIntTypeGet. -// -//***************************************************************************** -#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge -#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge -#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges -#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level -#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level - -//***************************************************************************** -// -// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter, -// and returned by GPIOPadConfigGet in the *pulStrength parameter. -// -//***************************************************************************** -#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength -#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength -#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength -#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control - -//***************************************************************************** -// -// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter, -// and returned by GPIOPadConfigGet in the *pulPadType parameter. -// -//***************************************************************************** -#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull -#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up -#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down -#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain -#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up -#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down -#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulPinIO); -extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin); -extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulIntType); -extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin); -extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulStrength, - unsigned long ulPadType); -extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin, - unsigned long *pulStrength, - unsigned long *pulPadType); -extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins); -extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked); -extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPortIntRegister(unsigned long ulPort, - void (*pfIntHandler)(void)); -extern void GPIOPortIntUnregister(unsigned long ulPort); -extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, - unsigned char ucVal); -extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins); - -#ifdef __cplusplus -} -#endif - -#endif // __GPIO_H__ diff --git a/Demo/CORTEX_LM3S102_GCC/hw_include/hw_ints.h b/Demo/CORTEX_LM3S102_GCC/hw_include/hw_ints.h deleted file mode 100644 index d32cec40b..000000000 --- a/Demo/CORTEX_LM3S102_GCC/hw_include/hw_ints.h +++ /dev/null @@ -1,82 +0,0 @@ -//***************************************************************************** -// -// hw_ints.h - Macros that define the interrupt assignment on Stellaris. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 523 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_INTS_H__ -#define __HW_INTS_H__ - -//***************************************************************************** -// -// The following define the fault assignments. -// -//***************************************************************************** -#define FAULT_NMI 2 // NMI fault -#define FAULT_HARD 3 // Hard fault -#define FAULT_MPU 4 // MPU fault -#define FAULT_BUS 5 // Bus fault -#define FAULT_USAGE 6 // Usage fault -#define FAULT_SVCALL 11 // SVCall -#define FAULT_DEBUG 12 // Debug monitor -#define FAULT_PENDSV 14 // PendSV -#define FAULT_SYSTICK 15 // System Tick - -//***************************************************************************** -// -// The following define the interrupt assignments. -// -//***************************************************************************** -#define INT_GPIOA 16 // GPIO Port A -#define INT_GPIOB 17 // GPIO Port B -#define INT_GPIOC 18 // GPIO Port C -#define INT_UART0 21 // UART0 Rx and Tx -#define INT_SSI 23 // SSI Rx and Tx -#define INT_I2C 24 // I2C Master and Slave -#define INT_WATCHDOG 34 // Watchdog timer -#define INT_TIMER0A 35 // Timer 0 subtimer A -#define INT_TIMER0B 36 // Timer 0 subtimer B -#define INT_TIMER1A 37 // Timer 1 subtimer A -#define INT_TIMER1B 38 // Timer 1 subtimer B -#define INT_COMP0 41 // Analog Comparator 0 -#define INT_COMP1 42 // Analog Comparator 1 -#define INT_SYSCTL 44 // System Control (PLL, OSC, BO) -#define INT_FLASH 45 // FLASH Control - -//***************************************************************************** -// -// The total number of interrupts. -// -//***************************************************************************** -#define NUM_INTERRUPTS 46 - -//***************************************************************************** -// -// The total number of priority levels. -// -//***************************************************************************** -#define NUM_PRIORITY 8 -#define NUM_PRIORITY_BITS 3 - -#endif // __HW_INTS_H__ diff --git a/Demo/CORTEX_LM3S102_GCC/hw_include/hw_memmap.h b/Demo/CORTEX_LM3S102_GCC/hw_include/hw_memmap.h deleted file mode 100644 index bef5dc618..000000000 --- a/Demo/CORTEX_LM3S102_GCC/hw_include/hw_memmap.h +++ /dev/null @@ -1,57 +0,0 @@ -//***************************************************************************** -// -// hw_memmap.h - Macros defining the memory map of Stellaris. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 523 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_MEMMAP_H__ -#define __HW_MEMMAP_H__ - -//***************************************************************************** -// -// The following define the base address of the memories and peripherals. -// -//***************************************************************************** -#define FLASH_BASE 0x00000000 // FLASH memory -#define SRAM_BASE 0x20000000 // SRAM memory -#define WATCHDOG_BASE 0x40000000 // Watchdog -#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A -#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B -#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C -#define SSI_BASE 0x40008000 // SSI -#define UART0_BASE 0x4000C000 // UART0 -#define I2C_MASTER_BASE 0x40020000 // I2C Master -#define I2C_SLAVE_BASE 0x40020800 // I2C Slave -#define TIMER0_BASE 0x40030000 // Timer0 -#define TIMER1_BASE 0x40031000 // Timer1 -#define COMP_BASE 0x4003C000 // Analog comparators -#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller -#define SYSCTL_BASE 0x400FE000 // System Control -#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell -#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace -#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint -#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl -#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit - -#endif // __HW_MEMMAP_H__ diff --git a/Demo/CORTEX_LM3S102_GCC/hw_include/hw_nvic.h b/Demo/CORTEX_LM3S102_GCC/hw_include/hw_nvic.h deleted file mode 100644 index 77dfe716a..000000000 --- a/Demo/CORTEX_LM3S102_GCC/hw_include/hw_nvic.h +++ /dev/null @@ -1,830 +0,0 @@ -//***************************************************************************** -// -// hw_nvic.h - Macros used when accessing the NVIC hardware. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 523 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_NVIC_H__ -#define __HW_NVIC_H__ - -//***************************************************************************** -// -// The following define the addresses of the NVIC registers. -// -//***************************************************************************** -#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg. -#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg. -#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register -#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register -#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg. -#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register -#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg. -#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register -#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg. -#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register -#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register -#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register -#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register -#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register -#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register -#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register -#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register -#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register -#define NVIC_CPUID 0xE000ED00 // CPUID Base Register -#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register -#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register -#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg. -#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register -#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register -#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority -#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority -#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority -#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State -#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg. -#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register -#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register -#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register -#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register -#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register -#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register -#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register -#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register -#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg. -#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg. -#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select -#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data -#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control -#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg. - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_INT_TYPE register. -// -//***************************************************************************** -#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) -#define NVIC_INT_TYPE_LINES_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_CTRL register. -// -//***************************************************************************** -#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag -#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source -#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable -#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_RELOAD register. -// -//***************************************************************************** -#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value -#define NVIC_ST_RELOAD_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_CURRENT register. -// -//***************************************************************************** -#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value -#define NVIC_ST_CURRENT_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_CAL register. -// -//***************************************************************************** -#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock -#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew -#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value -#define NVIC_ST_CAL_ONEMS_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_EN0 register. -// -//***************************************************************************** -#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable -#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable -#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable -#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable -#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable -#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable -#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable -#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable -#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable -#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable -#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable -#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable -#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable -#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable -#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable -#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable -#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable -#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable -#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable -#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable -#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable -#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable -#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable -#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable -#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable -#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable -#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable -#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable -#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable -#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable -#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable -#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DIS0 register. -// -//***************************************************************************** -#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable -#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable -#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable -#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable -#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable -#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable -#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable -#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable -#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable -#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable -#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable -#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable -#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable -#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable -#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable -#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable -#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable -#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable -#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable -#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable -#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable -#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable -#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable -#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable -#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable -#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable -#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable -#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable -#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable -#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable -#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable -#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PEND0 register. -// -//***************************************************************************** -#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend -#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend -#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend -#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend -#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend -#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend -#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend -#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend -#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend -#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend -#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend -#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend -#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend -#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend -#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend -#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend -#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend -#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend -#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend -#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend -#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend -#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend -#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend -#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend -#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend -#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend -#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend -#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend -#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend -#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend -#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend -#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_UNPEND0 register. -// -//***************************************************************************** -#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend -#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend -#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend -#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend -#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend -#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend -#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend -#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend -#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend -#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend -#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend -#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend -#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend -#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend -#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend -#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend -#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend -#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend -#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend -#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend -#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend -#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend -#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend -#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend -#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend -#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend -#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend -#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend -#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend -#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend -#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend -#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ACTIVE0 register. -// -//***************************************************************************** -#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active -#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active -#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active -#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active -#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active -#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active -#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active -#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active -#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active -#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active -#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active -#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active -#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active -#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active -#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active -#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active -#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active -#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active -#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active -#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active -#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active -#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active -#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active -#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active -#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active -#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active -#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active -#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active -#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active -#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active -#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active -#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI0 register. -// -//***************************************************************************** -#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask -#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask -#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask -#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask -#define NVIC_PRI0_INT3_S 24 -#define NVIC_PRI0_INT2_S 16 -#define NVIC_PRI0_INT1_S 8 -#define NVIC_PRI0_INT0_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI1 register. -// -//***************************************************************************** -#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask -#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask -#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask -#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask -#define NVIC_PRI1_INT7_S 24 -#define NVIC_PRI1_INT6_S 16 -#define NVIC_PRI1_INT5_S 8 -#define NVIC_PRI1_INT4_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI2 register. -// -//***************************************************************************** -#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask -#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask -#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask -#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask -#define NVIC_PRI2_INT11_S 24 -#define NVIC_PRI2_INT10_S 16 -#define NVIC_PRI2_INT9_S 8 -#define NVIC_PRI2_INT8_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI3 register. -// -//***************************************************************************** -#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask -#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask -#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask -#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask -#define NVIC_PRI3_INT15_S 24 -#define NVIC_PRI3_INT14_S 16 -#define NVIC_PRI3_INT13_S 8 -#define NVIC_PRI3_INT12_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI4 register. -// -//***************************************************************************** -#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask -#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask -#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask -#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask -#define NVIC_PRI4_INT19_S 24 -#define NVIC_PRI4_INT18_S 16 -#define NVIC_PRI4_INT17_S 8 -#define NVIC_PRI4_INT16_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI5 register. -// -//***************************************************************************** -#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask -#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask -#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask -#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask -#define NVIC_PRI5_INT23_S 24 -#define NVIC_PRI5_INT22_S 16 -#define NVIC_PRI5_INT21_S 8 -#define NVIC_PRI5_INT20_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI6 register. -// -//***************************************************************************** -#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask -#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask -#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask -#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask -#define NVIC_PRI6_INT27_S 24 -#define NVIC_PRI6_INT26_S 16 -#define NVIC_PRI6_INT25_S 8 -#define NVIC_PRI6_INT24_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI7 register. -// -//***************************************************************************** -#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask -#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask -#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask -#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask -#define NVIC_PRI7_INT31_S 24 -#define NVIC_PRI7_INT30_S 16 -#define NVIC_PRI7_INT29_S 8 -#define NVIC_PRI7_INT28_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_CPUID register. -// -//***************************************************************************** -#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer -#define NVIC_CPUID_VAR_M 0x00F00000 // Variant -#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number -#define NVIC_CPUID_REV_M 0x0000000F // Revision - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_INT_CTRL register. -// -//***************************************************************************** -#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI -#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV -#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV -#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling -#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending -#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception -#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base -#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception -#define NVIC_INT_CTRL_VEC_PEN_S 12 -#define NVIC_INT_CTRL_VEC_ACT_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_VTABLE register. -// -//***************************************************************************** -#define NVIC_VTABLE_BASE 0x20000000 // Vector table base -#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset -#define NVIC_VTABLE_OFFSET_S 8 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_APINT register. -// -//***************************************************************************** -#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask -#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key -#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess -#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group -#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split -#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split -#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split -#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split -#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split -#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split -#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split -#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split -#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request -#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info -#define NVIC_APINT_VECT_RESET 0x00000001 // System reset - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_CTRL register. -// -//***************************************************************************** -#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend -#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable -#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_CFG_CTRL register. -// -//***************************************************************************** -#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault -#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0 -#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access -#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger -#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger -#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_PRI1 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler -#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler -#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler -#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler -#define NVIC_SYS_PRI1_USAGE_S 16 -#define NVIC_SYS_PRI1_BUS_S 8 -#define NVIC_SYS_PRI1_MEM_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_PRI2 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler -#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers -#define NVIC_SYS_PRI2_SVC_S 24 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_PRI3 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler -#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler -#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler -#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler -#define NVIC_SYS_PRI3_TICK_S 24 -#define NVIC_SYS_PRI3_PENDSV_S 16 -#define NVIC_SYS_PRI3_DEBUG_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_HND_CTRL register. -// -//***************************************************************************** -#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable -#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable -#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable -#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended -#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended -#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active -#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active -#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active -#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active -#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active -#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active -#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_FAULT_STAT register. -// -//***************************************************************************** -#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault -#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault -#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault -#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault -#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault -#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault -#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid -#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault -#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault -#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error -#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error -#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault -#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid -#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation -#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation -#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation -#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_HFAULT_STAT register. -// -//***************************************************************************** -#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event -#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler -#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DEBUG_STAT register. -// -//***************************************************************************** -#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted -#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch -#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match -#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction -#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MM_ADDR register. -// -//***************************************************************************** -#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address -#define NVIC_MM_ADDR_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_FAULT_ADDR register. -// -//***************************************************************************** -#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address -#define NVIC_FAULT_ADDR_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_EXC_STACK register. -// -//***************************************************************************** -#define NVIC_EXC_STACK_DEEP 0x00000001 // Exception stack - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_EXC_NUM register. -// -//***************************************************************************** -#define NVIC_EXC_NUM_M 0x000003FF // Exception number -#define NVIC_EXC_NUM_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_COPRO register. -// -//***************************************************************************** -#define NVIC_COPRO_15_M 0xC0000000 // Coprocessor 15 access mask -#define NVIC_COPRO_15_DENIED 0x00000000 // Coprocessor 15 access denied -#define NVIC_COPRO_15_PRIV 0x40000000 // Coprocessor 15 privileged addess -#define NVIC_COPRO_15_FULL 0xC0000000 // Coprocessor 15 full access -#define NVIC_COPRO_14_M 0x30000000 // Coprocessor 14 access mask -#define NVIC_COPRO_14_DENIED 0x00000000 // Coprocessor 14 access denied -#define NVIC_COPRO_14_PRIV 0x10000000 // Coprocessor 14 privileged addess -#define NVIC_COPRO_14_FULL 0x30000000 // Coprocessor 14 full access -#define NVIC_COPRO_13_M 0x0C000000 // Coprocessor 13 access mask -#define NVIC_COPRO_13_DENIED 0x00000000 // Coprocessor 13 access denied -#define NVIC_COPRO_13_PRIV 0x04000000 // Coprocessor 13 privileged addess -#define NVIC_COPRO_13_FULL 0x0C000000 // Coprocessor 13 full access -#define NVIC_COPRO_12_M 0x03000000 // Coprocessor 12 access mask -#define NVIC_COPRO_12_DENIED 0x00000000 // Coprocessor 12 access denied -#define NVIC_COPRO_12_PRIV 0x01000000 // Coprocessor 12 privileged addess -#define NVIC_COPRO_12_FULL 0x03000000 // Coprocessor 12 full access -#define NVIC_COPRO_11_M 0x00C00000 // Coprocessor 11 access mask -#define NVIC_COPRO_11_DENIED 0x00000000 // Coprocessor 11 access denied -#define NVIC_COPRO_11_PRIV 0x00400000 // Coprocessor 11 privileged addess -#define NVIC_COPRO_11_FULL 0x00C00000 // Coprocessor 11 full access -#define NVIC_COPRO_10_M 0x00300000 // Coprocessor 10 access mask -#define NVIC_COPRO_10_DENIED 0x00000000 // Coprocessor 10 access denied -#define NVIC_COPRO_10_PRIV 0x00100000 // Coprocessor 10 privileged addess -#define NVIC_COPRO_10_FULL 0x00300000 // Coprocessor 10 full access -#define NVIC_COPRO_9_M 0x000C0000 // Coprocessor 9 access mask -#define NVIC_COPRO_9_DENIED 0x00000000 // Coprocessor 9 access denied -#define NVIC_COPRO_9_PRIV 0x00040000 // Coprocessor 9 privileged addess -#define NVIC_COPRO_9_FULL 0x000C0000 // Coprocessor 9 full access -#define NVIC_COPRO_8_M 0x00030000 // Coprocessor 8 access mask -#define NVIC_COPRO_8_DENIED 0x00000000 // Coprocessor 8 access denied -#define NVIC_COPRO_8_PRIV 0x00010000 // Coprocessor 8 privileged addess -#define NVIC_COPRO_8_FULL 0x00030000 // Coprocessor 8 full access -#define NVIC_COPRO_7_M 0x0000C000 // Coprocessor 7 access mask -#define NVIC_COPRO_7_DENIED 0x00000000 // Coprocessor 7 access denied -#define NVIC_COPRO_7_PRIV 0x00004000 // Coprocessor 7 privileged addess -#define NVIC_COPRO_7_FULL 0x0000C000 // Coprocessor 7 full access -#define NVIC_COPRO_6_M 0x00003000 // Coprocessor 6 access mask -#define NVIC_COPRO_6_DENIED 0x00000000 // Coprocessor 6 access denied -#define NVIC_COPRO_6_PRIV 0x00001000 // Coprocessor 6 privileged addess -#define NVIC_COPRO_6_FULL 0x00003000 // Coprocessor 6 full access -#define NVIC_COPRO_5_M 0x00000C00 // Coprocessor 5 access mask -#define NVIC_COPRO_5_DENIED 0x00000000 // Coprocessor 5 access denied -#define NVIC_COPRO_5_PRIV 0x00000400 // Coprocessor 5 privileged addess -#define NVIC_COPRO_5_FULL 0x00000C00 // Coprocessor 5 full access -#define NVIC_COPRO_4_M 0x00000300 // Coprocessor 4 access mask -#define NVIC_COPRO_4_DENIED 0x00000000 // Coprocessor 4 access denied -#define NVIC_COPRO_4_PRIV 0x00000100 // Coprocessor 4 privileged addess -#define NVIC_COPRO_4_FULL 0x00000300 // Coprocessor 4 full access -#define NVIC_COPRO_3_M 0x000000C0 // Coprocessor 3 access mask -#define NVIC_COPRO_3_DENIED 0x00000000 // Coprocessor 3 access denied -#define NVIC_COPRO_3_PRIV 0x00000040 // Coprocessor 3 privileged addess -#define NVIC_COPRO_3_FULL 0x000000C0 // Coprocessor 3 full access -#define NVIC_COPRO_2_M 0x00000030 // Coprocessor 2 access mask -#define NVIC_COPRO_2_DENIED 0x00000000 // Coprocessor 2 access denied -#define NVIC_COPRO_2_PRIV 0x00000010 // Coprocessor 2 privileged addess -#define NVIC_COPRO_2_FULL 0x00000030 // Coprocessor 2 full access -#define NVIC_COPRO_1_M 0x0000000C // Coprocessor 1 access mask -#define NVIC_COPRO_1_DENIED 0x00000000 // Coprocessor 1 access denied -#define NVIC_COPRO_1_PRIV 0x00000004 // Coprocessor 1 privileged addess -#define NVIC_COPRO_1_FULL 0x0000000C // Coprocessor 1 full access -#define NVIC_COPRO_0_M 0x00000003 // Coprocessor 0 access mask -#define NVIC_COPRO_0_DENIED 0x00000000 // Coprocessor 0 access denied -#define NVIC_COPRO_0_PRIV 0x00000001 // Coprocessor 0 privileged addess -#define NVIC_COPRO_0_FULL 0x00000003 // Coprocessor 0 full access - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_TYPE register. -// -//***************************************************************************** -#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions -#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions -#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU -#define NVIC_MPU_TYPE_IREGION_S 16 -#define NVIC_MPU_TYPE_DREGION_S 8 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_CTRL register. -// -//***************************************************************************** -#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults -#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_NUMBER register. -// -//***************************************************************************** -#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access -#define NVIC_MPU_NUMBER_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_BASE register. -// -//***************************************************************************** -#define NVIC_MPU_BASE_ADDR_M 0xFFFFFF00 // Base address -#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid -#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number -#define NVIC_MPU_BASE_ADDR_S 8 -#define NVIC_MPU_BASE_REGION_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_ATTR register. -// -//***************************************************************************** -#define NVIC_MPU_ATTR_ATTRS 0xFFFF0000 // Attributes -#define NVIC_MPU_ATTR_SRD 0x0000FF00 // Sub-region disable -#define NVIC_MPU_ATTR_SZENABLE 0x000000FF // Region size - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_CTRL register. -// -//***************************************************************************** -#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask -#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key -#define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor -#define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request -#define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable -#define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core -#define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping -#define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt -#define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available -#define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up -#define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core -#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping -#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core -#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core -#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_XFER register. -// -//***************************************************************************** -#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read -#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register -#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 -#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 -#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 -#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 -#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 -#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 -#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 -#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 -#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 -#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 -#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 -#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 -#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 -#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 -#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 -#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 -#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register -#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP -#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP -#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP -#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_DATA register. -// -//***************************************************************************** -#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache -#define NVIC_DBG_DATA_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_INT register. -// -//***************************************************************************** -#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault -#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors -#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error -#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state -#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check -#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error -#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault -#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status -#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset -#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending -#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SW_TRIG register. -// -//***************************************************************************** -#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger -#define NVIC_SW_TRIG_INTID_S 0 - -#endif // __HW_NVIC_H__ diff --git a/Demo/CORTEX_LM3S102_GCC/hw_include/hw_ssi.h b/Demo/CORTEX_LM3S102_GCC/hw_include/hw_ssi.h deleted file mode 100644 index 37472329f..000000000 --- a/Demo/CORTEX_LM3S102_GCC/hw_include/hw_ssi.h +++ /dev/null @@ -1,113 +0,0 @@ -//***************************************************************************** -// -// hw_ssi.h - Macros used when accessing the SSI hardware. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 523 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_SSI_H__ -#define __HW_SSI_H__ - -//***************************************************************************** -// -// The following define the offsets of the SSI registers. -// -//***************************************************************************** -#define SSI_O_CR0 0x00000000 // Control register 0 -#define SSI_O_CR1 0x00000004 // Control register 1 -#define SSI_O_DR 0x00000008 // Data register -#define SSI_O_SR 0x0000000C // Status register -#define SSI_O_CPSR 0x00000010 // Clock prescale register -#define SSI_O_IM 0x00000014 // Int mask set and clear register -#define SSI_O_RIS 0x00000018 // Raw interrupt register -#define SSI_O_MIS 0x0000001C // Masked interrupt register -#define SSI_O_ICR 0x00000020 // Interrupt clear register - -//***************************************************************************** -// -// The following define the bit fields in the SSI Control register 0. -// -//***************************************************************************** -#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate -#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase -#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity -#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask -#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format -#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format -#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format -#define SSI_CR0_DSS 0x0000000F // Data size select -#define SSI_CR0_DSS_4 0x00000003 // 4 bit data -#define SSI_CR0_DSS_5 0x00000004 // 5 bit data -#define SSI_CR0_DSS_6 0x00000005 // 6 bit data -#define SSI_CR0_DSS_7 0x00000006 // 7 bit data -#define SSI_CR0_DSS_8 0x00000007 // 8 bit data -#define SSI_CR0_DSS_9 0x00000008 // 9 bit data -#define SSI_CR0_DSS_10 0x00000009 // 10 bit data -#define SSI_CR0_DSS_11 0x0000000A // 11 bit data -#define SSI_CR0_DSS_12 0x0000000B // 12 bit data -#define SSI_CR0_DSS_13 0x0000000C // 13 bit data -#define SSI_CR0_DSS_14 0x0000000D // 14 bit data -#define SSI_CR0_DSS_15 0x0000000E // 15 bit data -#define SSI_CR0_DSS_16 0x0000000F // 16 bit data - -//***************************************************************************** -// -// The following define the bit fields in the SSI Control register 1. -// -//***************************************************************************** -#define SSI_CR1_SOD 0x00000008 // Slave mode output disable -#define SSI_CR1_MS 0x00000004 // Master or slave mode select -#define SSI_CR1_SSE 0x00000002 // Sync serial port enable -#define SSI_CR1_LBM 0x00000001 // Loopback mode - -//***************************************************************************** -// -// The following define the bit fields in the SSI Status register -// -//***************************************************************************** -#define SSI_SR_BSY 0x00000010 // SSI busy -#define SSI_SR_RFF 0x00000008 // RX FIFO full -#define SSI_SR_RNE 0x00000004 // RX FIFO not empty -#define SSI_SR_TNF 0x00000002 // TX FIFO not full -#define SSI_SR_TFE 0x00000001 // TX FIFO empty - -//***************************************************************************** -// -// The following define information concerning the SSI Data register. -// -//***************************************************************************** -#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO -#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO - -//***************************************************************************** -// -// The following define the bit fields in the interrupt mask set and clear, -// raw interrupt, masked interrupt, and interrupt clear registers. -// -//***************************************************************************** -#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt -#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt -#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt -#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt - -#endif // __HW_SSI_H__ diff --git a/Demo/CORTEX_LM3S102_GCC/hw_include/hw_sysctl.h b/Demo/CORTEX_LM3S102_GCC/hw_include/hw_sysctl.h deleted file mode 100644 index 044fec21d..000000000 --- a/Demo/CORTEX_LM3S102_GCC/hw_include/hw_sysctl.h +++ /dev/null @@ -1,325 +0,0 @@ -//***************************************************************************** -// -// hw_sysctl.h - Macros used when accessing the system control hardware. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 523 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_SYSCTL_H__ -#define __HW_SYSCTL_H__ - -//***************************************************************************** -// -// The following define the offsets of the system control registers. -// -//***************************************************************************** -#define SYSCTL_DID0 0x400fe000 // Device identification register 0 -#define SYSCTL_DID1 0x400fe004 // Device identification register 1 -#define SYSCTL_DC0 0x400fe008 // Device capabilities register 0 -#define SYSCTL_DC1 0x400fe010 // Device capabilities register 1 -#define SYSCTL_DC2 0x400fe014 // Device capabilities register 2 -#define SYSCTL_DC3 0x400fe018 // Device capabilities register 3 -#define SYSCTL_DC4 0x400fe01C // Device capabilities register 4 -#define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register -#define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register -#define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0 -#define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1 -#define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2 -#define SYSCTL_RIS 0x400fe050 // Raw interrupt status register -#define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register -#define SYSCTL_MISC 0x400fe058 // Interrupt status register -#define SYSCTL_RESC 0x400fe05c // Reset cause register -#define SYSCTL_RCC 0x400fe060 // Run-mode clock config register -#define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register -#define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0 -#define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1 -#define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2 -#define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0 -#define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1 -#define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2 -#define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0 -#define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1 -#define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2 -#define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register -#define SYSCTL_LDOARST 0x400fe160 // LDO reset control register - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DID0 register. -// -//***************************************************************************** -#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask -#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A -#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B -#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask -#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0 -#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DID1 register. -// -//***************************************************************************** -#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask -#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask -#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family -#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask -#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101 -#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102 -#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask -#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C) -#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C) -#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask -#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC -#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant -#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask -#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified) -#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified) -#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified -#define SYSCTL_DID1_PRTNO_SHIFT 16 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC0 register. -// -//***************************************************************************** -#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask -#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2kB of SRAM -#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask -#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8kB of flash - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC1 register. -// -//***************************************************************************** -#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask -#define SYSCTL_DC1_MPU 0x00000080 // Cortex M3 MPU present -#define SYSCTL_DC1_PLL 0x00000010 // PLL present -#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present -#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present -#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present -#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC2 register. -// -//***************************************************************************** -#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present -#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present -#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present -#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present -#define SYSCTL_DC2_I2C 0x00001000 // I2C present -#define SYSCTL_DC2_SSI 0x00000010 // SSI present -#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC3 register. -// -//***************************************************************************** -#define SYSCTL_DC3_32KHZ 0x80000000 // 32kHz pin present -#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present -#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present -#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present -#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present -#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present -#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC4 register. -// -//***************************************************************************** -#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present -#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present -#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_PBORCTL register. -// -//***************************************************************************** -#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer -#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset -#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise -#define SYSCTL_PBORCTL_BOR_SH 2 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_LDOPCTL register. -// -//***************************************************************************** -#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask -#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V -#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V -#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V -#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V -#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V -#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V -#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V -#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V -#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V -#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V -#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0, -// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers. -// -//***************************************************************************** -#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1, -// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers. -// -//***************************************************************************** -#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1 -#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0 -#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1 -#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0 -#define SYSCTL_SET1_I2C 0x00001000 // I2C module -#define SYSCTL_SET1_SSI 0x00000010 // SSI module -#define SYSCTL_SET1_UART0 0x00000001 // UART module 0 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2, -// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers. -// -//***************************************************************************** -#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module -#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module -#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and -// SYSCTL_IMS registers. -// -//***************************************************************************** -#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt -#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt -#define SYSCTL_INT_BOSC_FAIL 0x00000010 // Boot oscillator failure int -#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int -#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt -#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt -#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_RESC register. -// -//***************************************************************************** -#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset -#define SYSCTL_RESC_SW 0x00000010 // Software reset -#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset -#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset -#define SYSCTL_RESC_POR 0x00000002 // Power on reset -#define SYSCTL_RESC_EXT 0x00000001 // External reset - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_RCC register. -// -//***************************************************************************** -#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating -#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider -#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2 -#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3 -#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4 -#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5 -#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6 -#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7 -#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8 -#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9 -#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10 -#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11 -#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12 -#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13 -#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14 -#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15 -#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16 -#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider -#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down -#define SYSCTL_RCC_OE 0x00001000 // PLL output enable -#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass -#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable -#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc -#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal -#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864MHz crystal -#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4MHz crystal -#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal -#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal -#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal -#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal -#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal -#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal -#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal -#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal -#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal -#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select -#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator -#define SYSCTL_RCC_OSCSRC_BOOT 0x00000010 // Use the boot oscillator -#define SYSCTL_RCC_OSCSRC_BOOT4 0x00000020 // Use the boot oscillator / 4 -#define SYSCTL_RCC_BOSCVER 0x00000008 // Boot osc. verification timer en -#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en -#define SYSCTL_RCC_BOSCDIS 0x00000002 // Boot oscillator disable -#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable -#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field -#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field -#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_PLLCFG register. -// -//***************************************************************************** -#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider -#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1 -#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2 -#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4 -#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier -#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider -#define SYSCTL_PLLCFG_F_SHIFT 5 -#define SYSCTL_PLLCFG_R_SHIFT 0 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_CLKVCLR register. -// -//***************************************************************************** -#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_LDOARST register. -// -//***************************************************************************** -#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device - -#endif // __HW_SYSCTL_H__ diff --git a/Demo/CORTEX_LM3S102_GCC/hw_include/hw_types.h b/Demo/CORTEX_LM3S102_GCC/hw_include/hw_types.h deleted file mode 100644 index a944f6662..000000000 --- a/Demo/CORTEX_LM3S102_GCC/hw_include/hw_types.h +++ /dev/null @@ -1,63 +0,0 @@ -//***************************************************************************** -// -// hw_types.h - Common types and macros. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 523 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_TYPES_H__ -#define __HW_TYPES_H__ - -//***************************************************************************** -// -// Define a boolean type, and values for true and false. -// -//***************************************************************************** -typedef unsigned char tBoolean; - -#ifndef true -#define true 1 -#endif - -#ifndef false -#define false 0 -#endif - -//***************************************************************************** -// -// Macros for hardware access, both direct and via the bit-band region. -// -//***************************************************************************** -#define HWREG(x) \ - (*((volatile unsigned long *)(x))) -#define HWREGBITW(x, b) \ - HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) -#define HWREGBITH(x, b) \ - HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) -#define HWREGBITB(x, b) \ - HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) - -#endif // __HW_TYPES_H__ diff --git a/Demo/CORTEX_LM3S102_GCC/hw_include/hw_uart.h b/Demo/CORTEX_LM3S102_GCC/hw_include/hw_uart.h deleted file mode 100644 index 40b6ab2a6..000000000 --- a/Demo/CORTEX_LM3S102_GCC/hw_include/hw_uart.h +++ /dev/null @@ -1,234 +0,0 @@ -//***************************************************************************** -// -// hw_uart.h - Macros and defines used when accessing the UART hardware -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 523 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_UART_H__ -#define __HW_UART_H__ - -//***************************************************************************** -// -// UART Register Offsets. -// -//***************************************************************************** -#define UART_O_DR 0x00000000 // Data Register -#define UART_O_RSR 0x00000004 // Receive Status Register (read) -#define UART_O_ECR 0x00000004 // Error Clear Register (write) -#define UART_O_FR 0x00000018 // Flag Register (read only) -#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg -#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg -#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte -#define UART_O_CTL 0x00000030 // Control Register -#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg -#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg -#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register -#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register -#define UART_O_ICR 0x00000044 // Interrupt Clear Register - -//***************************************************************************** -// -// Data Register bits -// -//***************************************************************************** -#define UART_DR_OE 0x00000800 // Overrun Error -#define UART_DR_BE 0x00000400 // Break Error -#define UART_DR_PE 0x00000200 // Parity Error -#define UART_DR_FE 0x00000100 // Framing Error - -//***************************************************************************** -// -// Receive Status Register bits -// -//***************************************************************************** -#define UART_RSR_OE 0x00000008 // Overrun Error -#define UART_RSR_BE 0x00000004 // Break Error -#define UART_RSR_PE 0x00000002 // Parity Error -#define UART_RSR_FE 0x00000001 // Framing Error - -//***************************************************************************** -// -// Flag Register bits -// -//***************************************************************************** -#define UART_FR_RI 0x100 // Ring Indicator -#define UART_FR_TXFE 0x080 // TX FIFO Empty -#define UART_FR_RXFF 0x040 // RX FIFO Full -#define UART_FR_TXFF 0x020 // TX FIFO Full -#define UART_FR_RXFE 0x010 // RX FIFO Empty -#define UART_FR_BUSY 0x008 // UART Busy - -//***************************************************************************** -// -// Line Control Register High bits -// -//***************************************************************************** -#define UART_LCR_H_SPS 0x80 // Stick Parity Select -#define UART_LCR_H_WLEN 0x60 // Word length -#define UART_LCR_H_WLEN_8 0x60 // 8 bit data -#define UART_LCR_H_WLEN_7 0x40 // 7 bit data -#define UART_LCR_H_WLEN_6 0x20 // 6 bit data -#define UART_LCR_H_WLEN_5 0x00 // 5 bit data -#define UART_LCR_H_FEN 0x10 // Enable FIFO -#define UART_LCR_H_STP2 0x08 // Two Stop Bits Select -#define UART_LCR_H_EPS 0x04 // Even Parity Select -#define UART_LCR_H_PEN 0x02 // Parity Enable -#define UART_LCR_H_BRK 0x01 // Send Break - -//***************************************************************************** -// -// Control Register bits -// -//***************************************************************************** -#define UART_CTL_CTSEN 0x8000 // CTS Hardware Flow Control -#define UART_CTL_RTSEN 0x4000 // RTS Hardware Flow Control -#define UART_CTL_OUT2 0x2000 // OUT2 -#define UART_CTL_OUT1 0x1000 // OUT1 -#define UART_CTL_RTS 0x0800 // Request To Send -#define UART_CTL_DTR 0x0400 // Data Terminal Ready -#define UART_CTL_RXE 0x0200 // Receive Enable -#define UART_CTL_TXE 0x0100 // Transmit Enable -#define UART_CTL_LBE 0x0080 // Loopback Enable -#define UART_CTL_IIRLP 0x0004 // IrDA SIR low power mode -#define UART_CTL_SIREN 0x0002 // SIR Enable -#define UART_CTL_UARTEN 0x0001 // UART Enable - -//***************************************************************************** -// -// Interrupt FIFO Level Select Register bits -// -//***************************************************************************** -#define UART_IFLS_RX1_8 0x00 // 1/8 Full -#define UART_IFLS_RX2_8 0x10 // 1/4 Full -#define UART_IFLS_RX4_8 0x20 // 1/2 Full -#define UART_IFLS_RX6_8 0x30 // 3/4 Full -#define UART_IFLS_RX7_8 0x40 // 7/8 Full -#define UART_IFLS_TX1_8 0x00 // 1/8 Full -#define UART_IFLS_TX2_8 0x01 // 1/4 Full -#define UART_IFLS_TX4_8 0x02 // 1/2 Full -#define UART_IFLS_TX6_8 0x03 // 3/4 Full -#define UART_IFLS_TX7_8 0x04 // 7/8 Full - -//***************************************************************************** -// -// Interrupt Mask Set/Clear Register bits -// -//***************************************************************************** -#define UART_IM_OEIM 0x400 // Overrun Error Interrupt Mask -#define UART_IM_BEIM 0x200 // Break Error Interrupt Mask -#define UART_IM_PEIM 0x100 // Parity Error Interrupt Mask -#define UART_IM_FEIM 0x080 // Framing Error Interrupt Mask -#define UART_IM_RTIM 0x040 // Receive Timeout Interrupt Mask -#define UART_IM_TXIM 0x020 // Transmit Interrupt Mask -#define UART_IM_RXIM 0x010 // Receive Interrupt Mask -#define UART_IM_DSRMIM 0x008 // DSR Interrupt Mask -#define UART_IM_DCDMIM 0x004 // DCD Interrupt Mask -#define UART_IM_CTSMIM 0x002 // CTS Interrupt Mask -#define UART_IM_RIMIM 0x001 // RI Interrupt Mask - -//***************************************************************************** -// -// Raw Interrupt Status Register -// -//***************************************************************************** -#define UART_RIS_OERIS 0x400 // Overrun Error Interrupt Status -#define UART_RIS_BERIS 0x200 // Break Error Interrupt Status -#define UART_RIS_PERIS 0x100 // Parity Error Interrupt Status -#define UART_RIS_FERIS 0x080 // Framing Error Interrupt Status -#define UART_RIS_RTRIS 0x040 // Receive Timeout Interrupt Status -#define UART_RIS_TXRIS 0x020 // Transmit Interrupt Status -#define UART_RIS_RXRIS 0x010 // Receive Interrupt Status -#define UART_RIS_DSRRMIS 0x008 // DSR Interrupt Status -#define UART_RIS_DCDRMIS 0x004 // DCD Interrupt Status -#define UART_RIS_CTSRMIS 0x002 // CTS Interrupt Status -#define UART_RIS_RIRMIS 0x001 // RI Interrupt Status - -//***************************************************************************** -// -// Masked Interrupt Status Register -// -//***************************************************************************** -#define UART_MIS_OEMIS 0x400 // Overrun Error Interrupt Status -#define UART_MIS_BEMIS 0x200 // Break Error Interrupt Status -#define UART_MIS_PEMIS 0x100 // Parity Error Interrupt Status -#define UART_MIS_FEMIS 0x080 // Framing Error Interrupt Status -#define UART_MIS_RTMIS 0x040 // Receive Timeout Interrupt Status -#define UART_MIS_TXMIS 0x020 // Transmit Interrupt Status -#define UART_MIS_RXMIS 0x010 // Receive Interrupt Status -#define UART_MIS_DSRMMIS 0x008 // DSR Interrupt Status -#define UART_MIS_DCDMMIS 0x004 // DCD Interrupt Status -#define UART_MIS_CTSMMIS 0x002 // CTS Interrupt Status -#define UART_MIS_RIMMIS 0x001 // RI Interrupt Status - -//***************************************************************************** -// -// Interrupt Clear Register bits -// -//***************************************************************************** -#define UART_ICR_OEIC 0x200 // Overrun Error Interrupt Clear -#define UART_ICR_BEIC 0x200 // Break Error Interrupt Clear -#define UART_ICR_PEIC 0x200 // Parity Error Interrupt Clear -#define UART_ICR_FEIC 0x200 // Framing Error Interrupt Clear -#define UART_ICR_RTIC 0x200 // Receive Timeout Interrupt Clear -#define UART_ICR_TXIC 0x200 // Transmit Interrupt Clear -#define UART_ICR_RXIC 0x200 // Receive Interrupt Clear -#define UART_ICR_DSRMIC 0x200 // DSR Interrupt Clear -#define UART_ICR_DCDMIC 0x200 // DCD Interrupt Clear -#define UART_ICR_CTSMIC 0x200 // CTS Interrupt Clear -#define UART_ICR_RIMIC 0x200 // RI Interrupt Clear - -//***************************************************************************** -// -// DMA Control Register bits -// -//***************************************************************************** -#define UART_DMACRDMAONERR 0x04 // Disable DMA On Error -#define UART_DMACRTXDMAE 0x02 // Enable Transmit DMA -#define UART_DMACRRXDMAE 0x01 // Enable Receive DMA - -#define UART_RSR_ANY (UART_RSR_OE | \ - UART_RSR_BE | \ - UART_RSR_PE | \ - UART_RSR_FE) - -//***************************************************************************** -// -// Reset Values for UART Registers. -// -//***************************************************************************** -#define UART_RV_DR 0 -#define UART_RV_RSR 0x0 -#define UART_RV_ECR 0 -#define UART_RV_FR 0x90 -#define UART_RV_IBRD 0x0000 -#define UART_RV_FBRD 0x00 -#define UART_RV_LCR_H 0x00 -#define UART_RV_CTL 0x0300 -#define UART_RV_IFLS 0x12 -#define UART_RV_IM 0x000 -#define UART_RV_RIS 0x000 -#define UART_RV_MIS 0x000 -#define UART_RV_ICR 0x000 - -#endif // __HW_UART_H__ diff --git a/Demo/CORTEX_LM3S102_GCC/hw_include/interrupt.h b/Demo/CORTEX_LM3S102_GCC/hw_include/interrupt.h deleted file mode 100644 index 23424af4e..000000000 --- a/Demo/CORTEX_LM3S102_GCC/hw_include/interrupt.h +++ /dev/null @@ -1,57 +0,0 @@ -//***************************************************************************** -// -// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 523 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __INTERRUPT_H__ -#define __INTERRUPT_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void IntMasterEnable(void); -extern void IntMasterDisable(void); -extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)); -extern void IntUnregister(unsigned long ulInterrupt); -extern void IntPriorityGroupingSet(unsigned long ulBits); -extern unsigned long IntPriorityGroupingGet(void); -extern void IntPrioritySet(unsigned long ulInterrupt, - unsigned char ucPriority); -extern long IntPriorityGet(unsigned long ulInterrupt); -extern void IntEnable(unsigned long ulInterrupt); -extern void IntDisable(unsigned long ulInterrupt); - -#ifdef __cplusplus -} -#endif - -#endif // __INTERRUPT_H__ diff --git a/Demo/CORTEX_LM3S102_GCC/hw_include/libdriver.a b/Demo/CORTEX_LM3S102_GCC/hw_include/libdriver.a deleted file mode 100644 index e1c1ec8e7..000000000 Binary files a/Demo/CORTEX_LM3S102_GCC/hw_include/libdriver.a and /dev/null differ diff --git a/Demo/CORTEX_LM3S102_GCC/hw_include/pdc.c b/Demo/CORTEX_LM3S102_GCC/hw_include/pdc.c deleted file mode 100644 index 1e82ed8a8..000000000 --- a/Demo/CORTEX_LM3S102_GCC/hw_include/pdc.c +++ /dev/null @@ -1,132 +0,0 @@ -//***************************************************************************** -// -// pdc.c - Driver for the Peripheral Device Controller (PDC) on the Stellaris -// development board. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 523 of the Stellaris Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup utilities_api -//! @{ -// -//***************************************************************************** - -#include "hw_memmap.h" -#include "hw_types.h" -#include "gpio.h" -#include "ssi.h" -#include "sysctl.h" -#include "pdc.h" - -//***************************************************************************** -// -//! Initializes the connection to the PDC. -//! -//! This function will enable clocking to the SSI and GPIO A modules, configure -//! the GPIO pins to be used for an SSI interface, and it will configure the -//! SSI as a 1Mb master device, operating in MOTO mode. It will also enable -//! the SSI module, and will enable the chip select for the PDC on the -//! Stellaris development board. -//! -//! This function is contained in utils/pdc.c, with -//! utils/pdc.h containing the API definition for use by applications. -//! -//! \return None. -// -//***************************************************************************** -void -PDCInit(void) -{ - // - // Enable the peripherals used to drive the PDC. - // - SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI); - SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); - - // - // Configure the appropriate pins to be SSI instead of GPIO. - // - GPIODirModeSet(GPIO_PORTA_BASE, SSI_CLK | SSI_TX | SSI_RX, - GPIO_DIR_MODE_HW); - GPIODirModeSet(GPIO_PORTA_BASE, SSI_CS, GPIO_DIR_MODE_OUT); - GPIOPadConfigSet(GPIO_PORTA_BASE, SSI_CLK, GPIO_STRENGTH_4MA, - GPIO_PIN_TYPE_STD_WPU); - - // - // Configure the SSI port. - // - SSIConfig(SSI_BASE, SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 1000000, 8); - SSIEnable(SSI_BASE); - - // - // Reset the PDC SSI state machine. The chip select needs to be held low - // for 100ns; the procedure call overhead more than accounts for this time. - // - GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, 0); - GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, PDC_CS); -} - -//***************************************************************************** -// -//! Write a PDC register. -//! -//! \param ucAddr specifies the PDC register to write. -//! \param ucData specifies the data to write. -//! -//! This function will perform the SSI transfers required to write a register -//! in the PDC on the Stellaris development board. -//! -//! This function is contained in utils/pdc.c, with -//! utils/pdc.h containing the API definition for use by applications. -//! -//! \return None. -// -//***************************************************************************** -void -PDCWrite(unsigned char ucAddr, unsigned char ucData) -{ - unsigned long ulTemp; - - // - // Send address and write command. - // - SSIDataPut(SSI_BASE, (ucAddr & 0x0F) | PDC_WR); - - // - // Write the data. - // - SSIDataPut(SSI_BASE, ucData); - - // - // Flush data read during address write. - // - SSIDataGet(SSI_BASE, &ulTemp); - - // - // Flush data read during data write. - // - SSIDataGet(SSI_BASE, &ulTemp); -} - diff --git a/Demo/CORTEX_LM3S102_GCC/hw_include/pdc.h b/Demo/CORTEX_LM3S102_GCC/hw_include/pdc.h deleted file mode 100644 index aba74cd71..000000000 --- a/Demo/CORTEX_LM3S102_GCC/hw_include/pdc.h +++ /dev/null @@ -1,124 +0,0 @@ -//***************************************************************************** -// -// pdc.h - Stellaris development board Peripheral Device Controller definitions -// and prototypes. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 523 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __PDC_H__ -#define __PDC_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The registers within the peripheral device controller. -// -//***************************************************************************** -#define PDC_VER 0x0 // Version register -#define PDC_CSR 0x1 // Command/Status register -#define PDC_DSW 0x4 // DIP Switch register -#define PDC_LED 0x5 // LED register -#define PDC_LCD_CSR 0x6 // LCD Command/Status register -#define PDC_LCD_RAM 0x7 // LCD RAM register -#define PDC_GPXDAT 0x8 // GPIO X Data register -#define PDC_GPXDIR 0x9 // GPIO X Direction register -#define PDC_GPYDAT 0xA // GPIO Y Data register -#define PDC_GPYDIR 0xB // GPIO Y Direction register -#define PDC_GPZDAT 0xC // GPIO Z Data register -#define PDC_GPZDIR 0xD // GPIO Z Direction register - -//***************************************************************************** -// -// Flags indicating a read or write to the peripheral device controller. -// -//***************************************************************************** -#define PDC_RD 0x80 // PDC read command -#define PDC_WR 0x00 // PDC write command - -//***************************************************************************** -// -// LCD panel (Crystalfontz CFAH1602B) commands, RS = 0 -// -//***************************************************************************** -#define LCD_CLEAR 0x01 // Clear display (0 fill DDRAM). -#define LCD_HOME 0x02 // Cursor home. -#define LCD_MODE 0x04 // Set entry mode (cursor dir) -#define LCD_ON 0x08 // Set display, cursor, blinking - // on/off -#define LCD_CUR 0x10 // Cursor, display shift -#define LCD_IF 0x20 // Set interface data length, - // lines, font -#define LCD_CGADDR 0x40 // Set CGRAM AC address -#define LCD_DDADDR 0x80 // Set DDRAM AC address - -//***************************************************************************** -// -// LCD Status bit -// -//***************************************************************************** -#define LCD_B_BUSY 0x80 // Busy flag. - -//***************************************************************************** -// -// The GPIO port A pin numbers for the various SSI signals. -// -//***************************************************************************** -#define SSI_CS GPIO_PIN_3 -#define PDC_CS GPIO_PIN_3 -#define SSI_CLK GPIO_PIN_2 -#define SSI_TX GPIO_PIN_5 -#define SSI_RX GPIO_PIN_4 - -//***************************************************************************** -// -// Function Prototypes -// -//***************************************************************************** -extern void PDCInit(void); -extern unsigned char PDCRead(unsigned char ucAddr); -extern void PDCWrite(unsigned char ucAddr, unsigned char ucData); -extern unsigned char PDCDIPRead(void); -extern void PDCLEDWrite(unsigned char ucLED); -extern unsigned char PDCLEDRead(void); -extern void PDCLCDInit(void); -extern void PDCLCDBacklightOn(void); -extern void PDCLCDBacklightOff(void); -extern void PDCLCDClear(void); -extern void PDCLCDCreateChar(unsigned char ucChar, unsigned char *pucData); -extern void PDCLCDSetPos(unsigned char ucX, unsigned char ucY); -extern void PDCLCDWrite(const char *pcStr, unsigned long ulCount); -extern unsigned char PDCGPIODirRead(unsigned char ucIdx); -extern void PDCGPIODirWrite(unsigned char ucIdx, unsigned char ucValue); -extern unsigned char PDCGPIORead(unsigned char ucIdx); -extern void PDCGPIOWrite(unsigned char ucIdx, unsigned char ucValue); - -#ifdef __cplusplus -} -#endif - -#endif // __PDC_H__ diff --git a/Demo/CORTEX_LM3S102_GCC/hw_include/ssi.h b/Demo/CORTEX_LM3S102_GCC/hw_include/ssi.h deleted file mode 100644 index ef53b348b..000000000 --- a/Demo/CORTEX_LM3S102_GCC/hw_include/ssi.h +++ /dev/null @@ -1,88 +0,0 @@ -//***************************************************************************** -// -// ssi.h - Prototypes for the Synchronous Serial Interface Driver. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 523 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __SSI_H__ -#define __SSI_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear -// as the ulIntFlags parameter, and returned by SSIIntStatus. -// -//***************************************************************************** -#define SSI_TXFF 0x00000008 // TX FIFO half empty or less -#define SSI_RXFF 0x00000004 // RX FIFO half full or less -#define SSI_RXTO 0x00000002 // RX timeout -#define SSI_RXOR 0x00000001 // RX overrun - -//***************************************************************************** -// -// Values that can be passed to SSIConfig. -// -//***************************************************************************** -#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 -#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 -#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 -#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 -#define SSI_FRF_TI 0x00000010 // TI frame format -#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format - -#define SSI_MODE_MASTER 0x00000000 // SSI master -#define SSI_MODE_SLAVE 0x00000001 // SSI slave -#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void SSIConfig(unsigned long ulBase, unsigned long ulProtocol, - unsigned long ulMode, unsigned long ulBitRate, - unsigned long ulDataWidth); -extern void SSIDataGet(unsigned long ulBase, unsigned long *ulData); -extern long SSIDataNonBlockingGet(unsigned long ulBase, unsigned long *ulData); -extern void SSIDataPut(unsigned long ulBase, unsigned long ulData); -extern long SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData); -extern void SSIDisable(unsigned long ulBase); -extern void SSIEnable(unsigned long ulBase); -extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags); -extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); -extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void SSIIntUnregister(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __SSI_H__ diff --git a/Demo/CORTEX_LM3S102_GCC/hw_include/sysctl.h b/Demo/CORTEX_LM3S102_GCC/hw_include/sysctl.h deleted file mode 100644 index 2e1d1e48c..000000000 --- a/Demo/CORTEX_LM3S102_GCC/hw_include/sysctl.h +++ /dev/null @@ -1,221 +0,0 @@ -//***************************************************************************** -// -// sysctl.h - Prototypes for the system control driver. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 523 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __SYSCTL_H__ -#define __SYSCTL_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following are values that can be passed to the -// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(), -// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the -// ulPeripheral parameter. The peripherals in the fourth group (upper nibble -// is 3) can only be used with the SysCtlPeripheralPresent() API. -// -//***************************************************************************** -#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog -#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0 -#define SYSCTL_PERIPH_SSI 0x10000010 // SSI -#define SYSCTL_PERIPH_I2C 0x10001000 // I2C -#define SYSCTL_PERIPH_TIMER0 0x10010000 // Timer 0 -#define SYSCTL_PERIPH_TIMER1 0x10020000 // Timer 1 -#define SYSCTL_PERIPH_COMP0 0x11000000 // Analog comparator 0 -#define SYSCTL_PERIPH_COMP1 0x12000000 // Analog comparator 1 -#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A -#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B -#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C -#define SYSCTL_PERIPH_PLL 0x30000010 // PLL - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlPinPresent() API -// as the ulPin parameter. -// -//***************************************************************************** -#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin -#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin -#define SYSCTL_PIN_C0O 0x00000100 // C0o pin -#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin -#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin -#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin -#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlLDOSet() API as -// the ulVoltage value, or returned by the SysCtlLDOGet() API. -// -//***************************************************************************** -#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V -#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V -#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V -#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V -#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V -#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V -#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V -#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V -#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V -#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V -#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlLDOConfigSet() API. -// -//***************************************************************************** -#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset -#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlIntEnable(), -// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask -// by the SysCtlIntStatus() API. -// -//***************************************************************************** -#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt -#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt -#define SYSCTL_INT_BOSC_FAIL 0x00000010 // Boot oscillator failure int -#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int -#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt -#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt -#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlResetCauseClear() -// API or returned by the SysCtlResetCauseGet() API. -// -//***************************************************************************** -#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset -#define SYSCTL_CAUSE_SW 0x00000010 // Software reset -#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset -#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset -#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset -#define SYSCTL_CAUSE_EXT 0x00000001 // External reset - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlBrownOutConfigSet() -// API as the ulConfig parameter. -// -//***************************************************************************** -#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting -#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlClockSet() API as -// the ulConfig parameter. -// -//***************************************************************************** -#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1 -#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2 -#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3 -#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4 -#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5 -#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6 -#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7 -#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8 -#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9 -#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10 -#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11 -#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12 -#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13 -#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14 -#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15 -#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16 -#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock -#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock -#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz -#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz -#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz -#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz -#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz -#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz -#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz -#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz -#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz -#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz -#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz -#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz -#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc -#define SYSCTL_OSC_BOOT 0x00000010 // Oscillator source is boot osc -#define SYSCTL_OSC_BOOT4 0x00000020 // Oscillator source is boot osc /4 -#define SYSCTL_BOOT_OSC_DIS 0x00000002 // Disable boot oscillator -#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern unsigned long SysCtlSRAMSizeGet(void); -extern unsigned long SysCtlFlashSizeGet(void); -extern tBoolean SysCtlPinPresent(unsigned long ulPin); -extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral); -extern void SysCtlPeripheralReset(unsigned long ulPeripheral); -extern void SysCtlPeripheralEnable(unsigned long ulPeripheral); -extern void SysCtlPeripheralDisable(unsigned long ulPeripheral); -extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral); -extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral); -extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral); -extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral); -extern void SysCtlPeripheralClockGating(tBoolean bEnable); -extern void SysCtlIntRegister(void (*pfnHandler)(void)); -extern void SysCtlIntUnregister(void); -extern void SysCtlIntEnable(unsigned long ulInts); -extern void SysCtlIntDisable(unsigned long ulInts); -extern void SysCtlIntClear(unsigned long ulInts); -extern unsigned long SysCtlIntStatus(tBoolean bMasked); -extern void SysCtlLDOSet(unsigned long ulVoltage); -extern unsigned long SysCtlLDOGet(void); -extern void SysCtlLDOConfigSet(unsigned long ulConfig); -extern void SysCtlReset(void); -extern void SysCtlSleep(void); -extern void SysCtlDeepSleep(void); -extern unsigned long SysCtlResetCauseGet(void); -extern void SysCtlResetCauseClear(unsigned long ulCauses); -extern void SysCtlBrownOutConfigSet(unsigned long ulConfig, - unsigned long ulDelay); -extern void SysCtlClockSet(unsigned long ulConfig); -extern unsigned long SysCtlClockGet(void); -extern void SysCtlBOSCVerificationSet(tBoolean bEnable); -extern void SysCtlMOSCVerificationSet(tBoolean bEnable); -extern void SysCtlPLLVerificationSet(tBoolean bEnable); -extern void SysCtlClkVerificationClear(void); - -#ifdef __cplusplus -} -#endif - -#endif // __SYSCTL_H__ diff --git a/Demo/CORTEX_LM3S102_GCC/hw_include/uart.h b/Demo/CORTEX_LM3S102_GCC/hw_include/uart.h deleted file mode 100644 index ea39859d2..000000000 --- a/Demo/CORTEX_LM3S102_GCC/hw_include/uart.h +++ /dev/null @@ -1,102 +0,0 @@ -//***************************************************************************** -// -// uart.h - Defines and Macros for the UART. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 523 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __UART_H__ -#define __UART_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear -// as the ulIntFlags parameter, and returned from UARTIntStatus. -// -//***************************************************************************** -#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask -#define UART_INT_BE 0x200 // Break Error Interrupt Mask -#define UART_INT_PE 0x100 // Parity Error Interrupt Mask -#define UART_INT_FE 0x080 // Framing Error Interrupt Mask -#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask -#define UART_INT_TX 0x020 // Transmit Interrupt Mask -#define UART_INT_RX 0x010 // Receive Interrupt Mask - -//***************************************************************************** -// -// Values that can be passed to UARTConfigSet as the ulConfig parameter and -// returned by UARTConfigGet in the pulConfig parameter. Additionally, the -// UART_CONFIG_PAR_* subset can be passed to UARTParityModeSet as the ulParity -// parameter, and are returned by UARTParityModeGet. -// -//***************************************************************************** -#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data -#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data -#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data -#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data -#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit -#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits -#define UART_CONFIG_PAR_NONE 0x00000000 // No parity -#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity -#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity -#define UART_CONFIG_PAR_ONE 0x00000086 // Parity bit is one -#define UART_CONFIG_PAR_ZERO 0x00000082 // Parity bit is zero - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity); -extern unsigned long UARTParityModeGet(unsigned long ulBase); -extern void UARTConfigSet(unsigned long ulBase, unsigned long ulBaud, - unsigned long ulConfig); -extern void UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud, - unsigned long *pulConfig); -extern void UARTEnable(unsigned long ulBase); -extern void UARTDisable(unsigned long ulBase); -extern tBoolean UARTCharsAvail(unsigned long ulBase); -extern tBoolean UARTSpaceAvail(unsigned long ulBase); -extern long UARTCharNonBlockingGet(unsigned long ulBase); -extern long UARTCharGet(unsigned long ulBase); -extern tBoolean UARTCharNonBlockingPut(unsigned long ulBase, - unsigned char ucData); -extern void UARTCharPut(unsigned long ulBase, unsigned char ucData); -extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState); -extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); -extern void UARTIntUnregister(unsigned long ulBase); -extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags); - -#ifdef __cplusplus -} -#endif - -#endif // __UART_H__ diff --git a/Demo/CORTEX_LM3S102_GCC/init/startup.c b/Demo/CORTEX_LM3S102_GCC/init/startup.c deleted file mode 100644 index c68821e32..000000000 --- a/Demo/CORTEX_LM3S102_GCC/init/startup.c +++ /dev/null @@ -1,174 +0,0 @@ -//***************************************************************************** -// -// startup.c - Boot code for Stellaris. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -//***************************************************************************** - -//***************************************************************************** -// -// Forward declaration of the default fault handlers. -// -//***************************************************************************** -void ResetISR(void); -static void NmiSR(void); -void FaultISR(void); -extern void xPortPendSVHandler(void); -extern void xPortSysTickHandler(void); -extern void vUART_ISR( void ); - -//***************************************************************************** -// -// The entry point for the application. -// -//***************************************************************************** -extern void entry(void); - -//***************************************************************************** -// -// Reserve space for the system stack. -// -//***************************************************************************** -#ifndef STACK_SIZE -#define STACK_SIZE 51 -#endif -static unsigned long pulMainStack[STACK_SIZE]; - -//***************************************************************************** -// -// The minimal vector table for a Cortex M3. Note that the proper constructs -// must be placed on this to ensure that it ends up at physical address -// 0x0000.0000. -// -//***************************************************************************** -__attribute__ ((section("vectors"))) -void (* const g_pfnVectors[])(void) = -{ - (void (*)(void))((unsigned long)pulMainStack + sizeof(pulMainStack)), - ResetISR, - NmiSR, - FaultISR, //FAULT - 0, // The MPU fault handler - 0, // The bus fault handler - 0, // The usage fault handler - 0, // Reserved - 0, // Reserved - 0, // Reserved - 0, // Reserved - 0, // SVCall handler - 0, // Debug monitor handler - 0, // Reserved - xPortPendSVHandler, // The PendSV handler - xPortSysTickHandler, // The SysTick handler - 0, // GPIO Port A - 0, // GPIO Port B - 0, // GPIO Port C - 0, // GPIO Port D - 0, // GPIO Port E - vUART_ISR // UART0 Rx and Tx -}; - -//***************************************************************************** -// -// The following are constructs created by the linker, indicating where the -// the "data" and "bss" segments reside in memory. The initializers for the -// for the "data" segment resides immediately following the "text" segment. -// -//***************************************************************************** -extern unsigned long _etext; -extern unsigned long _data; -extern unsigned long _edata; -extern unsigned long _bss; -extern unsigned long _ebss; - -//***************************************************************************** -// -// This is the code that gets called when the processor first starts execution -// following a reset event. Only the absolutely necessary set is performed, -// after which the application supplied entry() routine is called. Any fancy -// actions (such as making decisions based on the reset cause register, and -// resetting the bits in that register) are left solely in the hands of the -// application. -// -//***************************************************************************** -void -ResetISR(void) -{ - unsigned long *pulSrc, *pulDest; - - // - // Copy the data segment initializers from flash to SRAM. - // - pulSrc = &_etext; - for(pulDest = &_data; pulDest < &_edata; ) - { - *pulDest++ = *pulSrc++; - } - - // - // Zero fill the bss segment. - // - for(pulDest = &_bss; pulDest < &_ebss; ) - { - *pulDest++ = 0; - } - - // - // Call the application's entry point. - // - Main(); -} - -//***************************************************************************** -// -// This is the code that gets called when the processor receives a NMI. This -// simply enters an infinite loop, preserving the system state for examination -// by a debugger. -// -//***************************************************************************** -static void -NmiSR(void) -{ - // - // Enter an infinite loop. - // - while(1) - { - } -} - -//***************************************************************************** -// -// This is the code that gets called when the processor receives a fault -// interrupt. This simply enters an infinite loop, preserving the system state -// for examination by a debugger. -// -//***************************************************************************** -void -FaultISR(void) -{ - // - // Enter an infinite loop. - // - while(1) - { - } -} diff --git a/Demo/CORTEX_LM3S102_GCC/main.c b/Demo/CORTEX_LM3S102_GCC/main.c deleted file mode 100644 index 16541674a..000000000 --- a/Demo/CORTEX_LM3S102_GCC/main.c +++ /dev/null @@ -1,604 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * This demo application creates six co-routines and two tasks (three including - * the idle task). The co-routines execute as part of the idle task hook. - * - * Five of the created co-routines are the standard 'co-routine flash' - * co-routines contained within the Demo/Common/Minimal/crflash.c file and - * documented on the FreeRTOS.org WEB site. - * - * The 'LCD Task' rotates a string on the LCD, delaying between each character - * as necessitated by the slow interface, and delaying between each string just - * long enough to enable the text to be read. - * - * The sixth co-routine and final task control the transmission and reception - * of a string to UART 0. The co-routine periodically sends the first - * character of the string to the UART, with the UART's TxEnd interrupt being - * used to transmit the remaining characters. The UART's RxEnd interrupt - * receives the characters and places them on a queue to be processed by the - * 'COMs Rx' task. An error is latched should an unexpected character be - * received, or any character be received out of sequence. - * - * A loopback connector is required to ensure that each character transmitted - * on the UART is also received on the same UART. For test purposes the UART - * FIFO's are not utalised in order to maximise the interrupt overhead. Also - * a pseudo random interval is used between the start of each transmission in - * order that the resultant interrupts are more randomly distributed and - * therefore more likely to highlight any problems. - * - * The flash co-routines control LED's zero to four. LED five is toggled each - * time the string is transmitted on the UART. LED six is toggled each time - * the string is CORRECTLY received on the UART. LED seven is latched on should - * an error be detected in any task or co-routine. - * - * In addition the idle task makes repetative calls to - * prvSetAndCheckRegisters(). This simply loads the general purpose registers - * with a known value, then checks each register to ensure the held value is - * still correct. As a low priority task this checking routine is likely to - * get repeatedly swapped in and out. A register being found to contain an - * incorrect value is therefore indicative of an error in the task switching - * mechansim. - * - */ - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" -#include "croutine.h" - -/* Demo application include files. */ -#include "partest.h" -#include "crflash.h" - -/* Library include files. */ -#include "DriverLib.h" - -/* The time to delay between writing each character to the LCD. */ -#define mainCHAR_WRITE_DELAY ( 2 / portTICK_RATE_MS ) - -/* The time to delay between writing each string to the LCD. */ -#define mainSTRING_WRITE_DELAY ( 400 / portTICK_RATE_MS ) - -/* The number of flash co-routines to create. */ -#define mainNUM_FLASH_CO_ROUTINES ( 5 ) - -/* The length of the queue used to pass received characters to the Comms Rx -task. */ -#define mainRX_QUEUE_LEN ( 5 ) - -/* The priority of the co-routine used to initiate the transmission of the -string on UART 0. */ -#define mainTX_CO_ROUTINE_PRIORITY ( 1 ) - -/* Only one co-routine is created so its index is not important. */ -#define mainTX_CO_ROUTINE_INDEX ( 0 ) - -/* The time between transmissions of the string on UART 0. This is pseudo -random in order to generate a bit or randomness to when the interrupts occur.*/ -#define mainMIN_TX_DELAY ( 40 / portTICK_RATE_MS ) -#define mainMAX_TX_DELAY ( ( portTickType ) 0x7f ) -#define mainOFFSET_TIME ( ( portTickType ) 3 ) - -/* The time the Comms Rx task should wait to receive a character. This should -be slightly longer than the time between transmissions. If we do not receive -a character after this time then there must be an error in the transmission or -the timing of the transmission. */ -#define mainCOMMS_RX_DELAY ( mainMAX_TX_DELAY + 20 ) - -/* The task priorites. */ -#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY ) -#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) - -/* The LED's toggled by the various tasks. */ -#define mainCOMMS_FAIL_LED ( 7 ) -#define mainCOMMS_RX_LED ( 6 ) -#define mainCOMMS_TX_LED ( 5 ) - -/* The baud rate used by the UART comms tasks/co-routine. */ -#define mainBAUD_RATE ( 57600 ) - -/* FIFO setting for the UART. The FIFO is not used to create a better test. */ -#define mainFIFO_SET ( 0x10 ) - -/* The string that is transmitted on the UART contains sequentially the -characters from mainFIRST_TX_CHAR to mainLAST_TX_CHAR. */ -#define mainFIRST_TX_CHAR '0' -#define mainLAST_TX_CHAR 'z' - -/* Just used to walk through the program memory in order that some random data -can be generated. */ -#define mainTOTAL_PROGRAM_MEMORY ( ( unsigned portLONG * ) ( 8 * 1024 ) ) -#define mainFIRST_PROGRAM_BYTES ( ( unsigned portLONG * ) 4 ) - -/* The error routine that is called if the driver library encounters an error. */ -#ifdef DEBUG -void -__error__(char *pcFilename, unsigned long ulLine) -{ -} -#endif - -/*-----------------------------------------------------------*/ - -/* - * The task that rotates text on the LCD. - */ -static void vLCDTask( void * pvParameters ); - -/* - * The task that receives the characters from UART 0. - */ -static void vCommsRxTask( void * pvParameters ); - -/* - * The co-routine that periodically initiates the transmission of the string on - * the UART. - */ -static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); - -/* - * Writes a string the the LCD. - */ -static void prvWriteString( const portCHAR *pcString ); - -/* - * Initialisation routine for the UART. - */ -static void vSerialInit( void ); - -/* - * Thread safe write to the PDC. - */ -static void prvPDCWrite( portCHAR cAddress, portCHAR cData ); - -/* - * Function to simply set a known value into the general purpose registers - * then read them back to ensure they remain set correctly. An incorrect value - * being indicative of an error in the task switching mechanism. - */ -void prvSetAndCheckRegisters( void ); - -/* - * Latch the LED that indicates that an error has occurred. - */ -void vSetErrorLED( void ); - -/* - * Sets up the PLL and ports used by the demo. - */ -static void prvSetupHardware( void ); - -/*-----------------------------------------------------------*/ - -/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines -defined within this file. */ -unsigned portBASE_TYPE uxErrorStatus = pdPASS; - -/* The next character to transmit. */ -static portCHAR cNextChar; - -/* The queue used to transmit characters from the interrupt to the Comms Rx -task. */ -static xQueueHandle xCommsQueue; - -/*-----------------------------------------------------------*/ - -void Main( void ) -{ - /* Create the queue used to communicate between the UART ISR and the Comms - Rx task. */ - xCommsQueue = xQueueCreate( mainRX_QUEUE_LEN, sizeof( portCHAR ) ); - - /* Setup the ports used by the demo and the clock. */ - prvSetupHardware(); - - /* Create the co-routines that flash the LED's. */ - vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES ); - - /* Create the co-routine that initiates the transmission of characters - on the UART. */ - xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX ); - - /* Create the LCD and Comms Rx tasks. */ - xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL ); - xTaskCreate( vCommsRxTask, "CMS", configMINIMAL_STACK_SIZE, NULL, mainCOMMS_RX_TASK_PRIORITY, NULL ); - - /* Start the scheduler running the tasks and co-routines just created. */ - vTaskStartScheduler(); - - /* Should not get here unless we did not have enough memory to start the - scheduler. */ - for( ;; ); -} -/*-----------------------------------------------------------*/ - -static void prvSetupHardware( void ) -{ - /* Setup the PLL. */ - SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); - - /* Initialise the hardware used to talk to the LCD, LED's and UART. */ - PDCInit(); - vParTestInitialise(); - vSerialInit(); -} -/*-----------------------------------------------------------*/ - -void vApplicationIdleHook( void ) -{ - /* The co-routines are executed in the idle task using the idle task - hook. */ - for( ;; ) - { - /* Schedule the co-routines. */ - vCoRoutineSchedule(); - - /* Run the register check function between each co-routine. */ - prvSetAndCheckRegisters(); - } -} -/*-----------------------------------------------------------*/ - -static void prvWriteString( const portCHAR *pcString ) -{ - /* Write pcString to the LED, pausing between each character. */ - prvPDCWrite(PDC_LCD_CSR, LCD_CLEAR); - while( *pcString ) - { - vTaskDelay( mainCHAR_WRITE_DELAY ); - prvPDCWrite( PDC_LCD_RAM, *pcString ); - pcString++; - } -} -/*-----------------------------------------------------------*/ - -void vLCDTask( void * pvParameters ) -{ -unsigned portBASE_TYPE uxIndex; -const unsigned portCHAR ucCFGData[] = { - 0x30, /* Set data bus to 8-bits. */ - 0x30, - 0x30, - 0x3C, /* Number of lines/font. */ - 0x08, /* Display off. */ - 0x01, /* Display clear. */ - 0x06, /* Entry mode [cursor dir][shift]. */ - 0x0C /* Display on [display on][curson on][blinking on]. */ - }; - -/* The strings that are written to the LCD. */ -const portCHAR *pcStringsToDisplay[] = { - "Stellaris", - "Demo", - "One", - "www.FreeRTOS.org", - "" - }; - - /* Configure the LCD. */ - uxIndex = 0; - while( uxIndex < sizeof( ucCFGData ) ) - { - prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] ); - uxIndex++; - vTaskDelay( mainCHAR_WRITE_DELAY ); - } - - /* Turn the LCD Backlight on. */ - prvPDCWrite( PDC_CSR, 0x01 ); - - /* Clear display. */ - vTaskDelay( mainCHAR_WRITE_DELAY ); - prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); - - uxIndex = 0; - for( ;; ) - { - /* Display the string on the LCD. */ - prvWriteString( pcStringsToDisplay[ uxIndex ] ); - - /* Move on to the next string - wrapping if necessary. */ - uxIndex++; - if( *( pcStringsToDisplay[ uxIndex ] ) == 0x00 ) - { - uxIndex = 0; - /* Longer pause on the last string to be sent. */ - vTaskDelay( mainSTRING_WRITE_DELAY * 2 ); - } - - /* Wait until it is time to move onto the next string. */ - vTaskDelay( mainSTRING_WRITE_DELAY ); - } -} -/*-----------------------------------------------------------*/ - -static void vCommsRxTask( void * pvParameters ) -{ -static portCHAR cRxedChar, cExpectedChar; - - /* Set the char we expect to receive to the start of the string. */ - cExpectedChar = mainFIRST_TX_CHAR; - - for( ;; ) - { - /* Wait for a character to be received. */ - xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY ); - - /* Was the character recived (if any) the expected character. */ - if( cRxedChar != cExpectedChar ) - { - /* Got an unexpected character. This can sometimes occur when - reseting the system using the debugger leaving characters already - in the UART regsters. */ - uxErrorStatus = pdFAIL; - - /* Resync by waiting for the end of the current string. */ - while( cRxedChar != mainLAST_TX_CHAR ) - { - while( !xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, portMAX_DELAY ) ); - } - - /* The next expected character is the start of the string again. */ - cExpectedChar = mainFIRST_TX_CHAR; - } - else - { - if( cExpectedChar == mainLAST_TX_CHAR ) - { - /* We have reached the end of the string - we now expect to - receive the first character in the string again. The LED is - toggled to indicate that the entire string was received without - error. */ - vParTestToggleLED( mainCOMMS_RX_LED ); - cExpectedChar = mainFIRST_TX_CHAR; - } - else - { - /* We got the expected character, we now expect to receive the - next character in the string. */ - cExpectedChar++; - } - } - } -} -/*-----------------------------------------------------------*/ - -static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) -{ -portTickType xDelayPeriod; -static unsigned portLONG *pulRandomBytes = mainFIRST_PROGRAM_BYTES; - - /* Co-routine MUST start with a call to crSTART. */ - crSTART( xHandle ); - - for(;;) - { - /* Was the previously transmitted string received correctly? */ - if( uxErrorStatus != pdPASS ) - { - /* An error was encountered so set the error LED. */ - vSetErrorLED(); - } - - /* The next character to Tx is the first in the string. */ - cNextChar = mainFIRST_TX_CHAR; - - UARTIntDisable( UART0_BASE, UART_INT_TX ); - { - /* Send the first character. */ - if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) - { - HWREG( UART0_BASE + UART_O_DR ) = cNextChar; - } - - /* Move the variable to the char to Tx on so the ISR transmits - the next character in the string once this one has completed. */ - cNextChar++; - } - UARTIntEnable(UART0_BASE, UART_INT_TX); - - /* Toggle the LED to show a new string is being transmitted. */ - vParTestToggleLED( mainCOMMS_TX_LED ); - - /* Delay before we start the string off again. A pseudo-random delay - is used as this will provide a better test. */ - xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes ); - - pulRandomBytes++; - if( pulRandomBytes > mainTOTAL_PROGRAM_MEMORY ) - { - pulRandomBytes = mainFIRST_PROGRAM_BYTES; - } - - /* Make sure we don't wait too long... */ - xDelayPeriod &= mainMAX_TX_DELAY; - - /* ...but we do want to wait. */ - if( xDelayPeriod < mainMIN_TX_DELAY ) - { - xDelayPeriod = mainMIN_TX_DELAY; - } - - /* Block for the random(ish) time. */ - crDELAY( xHandle, xDelayPeriod ); - } - - /* Co-routine MUST end with a call to crEND. */ - crEND(); -} -/*-----------------------------------------------------------*/ - -static void vSerialInit( void ) -{ - /* Enable the UART. GPIOA has already been initialised. */ - SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); - - /* Set GPIO A0 and A1 as peripheral function. They are used to output the - UART signals. */ - GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); - - /* Configure the UART for 8-N-1 operation. */ - UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); - - /* We dont want to use the fifo. This is for test purposes to generate - as many interrupts as possible. */ - HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; - - /* Enable both Rx and Tx interrupts. */ - HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX ); - IntEnable( INT_UART0 ); -} -/*-----------------------------------------------------------*/ - -void vUART_ISR(void) -{ -unsigned portLONG ulStatus; -portCHAR cRxedChar; -portBASE_TYPE xTaskWokenByPost = pdFALSE; - - /* What caused the interrupt. */ - ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); - - /* Clear the interrupt. */ - UARTIntClear( UART0_BASE, ulStatus ); - - /* Was an Rx interrpt pending? */ - if( ulStatus & UART_INT_RX ) - { - if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) ) - { - /* Get the char from the buffer and post it onto the queue of - Rxed chars. Posting the character should wake the task that is - blocked on the queue waiting for characters. */ - cRxedChar = ( portCHAR ) HWREG( UART0_BASE + UART_O_DR ); - xTaskWokenByPost = xQueueSendFromISR( xCommsQueue, &cRxedChar, xTaskWokenByPost ); - } - } - - /* Was a Tx interrupt pending? */ - if( ulStatus & UART_INT_TX ) - { - /* Send the next character in the string. We are not using the FIFO. */ - if( cNextChar <= mainLAST_TX_CHAR ) - { - if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) - { - HWREG( UART0_BASE + UART_O_DR ) = cNextChar; - } - cNextChar++; - } - } - - if( xTaskWokenByPost ) - { - /* If a task was woken by the character being received then we force - a context switch to occur in case the task is of higher priority than - the currently executing task (i.e. the task that this interrupt - interrupted.) */ - portEND_SWITCHING_ISR( xTaskWokenByPost ); - } -} -/*-----------------------------------------------------------*/ - -static void prvPDCWrite( portCHAR cAddress, portCHAR cData ) -{ - vTaskSuspendAll(); - { - PDCWrite( cAddress, cData ); - } - xTaskResumeAll(); -} -/*-----------------------------------------------------------*/ - -void vSetErrorLED( void ) -{ - vParTestSetLED( mainCOMMS_FAIL_LED, pdTRUE ); -} -/*-----------------------------------------------------------*/ - -void prvSetAndCheckRegisters( void ) -{ - /* Fill the general purpose registers with known values. */ - __asm volatile( " mov r11, #10\n" - " add r0, r11, #1\n" - " add r1, r11, #2\n" - " add r2, r11, #3\n" - " add r3, r11, #4\n" - " add r4, r11, #5\n" - " add r5, r11, #6\n" - " add r6, r11, #7\n" - " add r7, r11, #8\n" - " add r8, r11, #9\n" - " add r9, r11, #10\n" - " add r10, r11, #11\n" - " add r12, r11, #12" ); - - /* Check the values are as expected. */ - __asm volatile( " cmp r11, #10\n" - " bne set_error_led\n" - " cmp r0, #11\n" - " bne set_error_led\n" - " cmp r1, #12\n" - " bne set_error_led\n" - " cmp r2, #13\n" - " bne set_error_led\n" - " cmp r3, #14\n" - " bne set_error_led\n" - " cmp r4, #15\n" - " bne set_error_led\n" - " cmp r5, #16\n" - " bne set_error_led\n" - " cmp r6, #17\n" - " bne set_error_led\n" - " cmp r7, #18\n" - " bne set_error_led\n" - " cmp r8, #19\n" - " bne set_error_led\n" - " cmp r9, #20\n" - " bne set_error_led\n" - " cmp r10, #21\n" - " bne set_error_led\n" - " cmp r12, #22\n" - " bne set_error_led\n" - " bx lr" ); - - __asm volatile( "set_error_led:\n" - " push {r14}\n" - " ldr r1, =vSetErrorLED\n" - " blx r1\n" - " pop {r14}\n" - " bx lr" ); -} -/*-----------------------------------------------------------*/ diff --git a/Demo/CORTEX_LM3S102_GCC/makedefs b/Demo/CORTEX_LM3S102_GCC/makedefs deleted file mode 100644 index 8f7a62be5..000000000 --- a/Demo/CORTEX_LM3S102_GCC/makedefs +++ /dev/null @@ -1,193 +0,0 @@ -#****************************************************************************** -# -# makedefs - Definitions common to all makefiles. -# -# Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -# -# Software License Agreement -# -# Luminary Micro, Inc. (LMI) is supplying this software for use solely and -# exclusively on LMI's Stellaris Family of microcontroller products. -# -# The software is owned by LMI and/or its suppliers, and is protected under -# applicable copyright laws. All rights are reserved. Any use in violation -# of the foregoing restrictions may subject the user to criminal sanctions -# under applicable laws, as well as to civil liability for the breach of the -# terms and conditions of this license. -# -# THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -# OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -# LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -# CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -# -#****************************************************************************** - -#****************************************************************************** -# -# The compiler to be used. -# -#****************************************************************************** -ifndef COMPILER -COMPILER=gcc -endif - -#****************************************************************************** -# -# The debugger to be used. -# -#****************************************************************************** -ifndef DEBUGGER -DEBUGGER=gdb -endif - -#****************************************************************************** -# -# Definitions for using GCC. -# -#****************************************************************************** -ifeq (${COMPILER}, gcc) - -# -# The command for calling the compiler. -# -CC=arm-stellaris-eabi-gcc - -# -# The flags passed to the assembler. -# -AFLAGS=-mthumb \ - -mcpu=cortex-m3 \ - -MD - -# -# The flags passed to the compiler. -# -CFLAGS=-mthumb \ - -mcpu=cortex-m3 \ - -O2 \ - -MD - -# -# The command for calling the library archiver. -# -AR=arm-stellaris-eabi-ar - -# -# The command for calling the linker. -# -LD=arm-stellaris-eabi-ld - -# -# The flags passed to the linker. -# -LDFLAGS= -Map gcc/out.map - -# -# Get the location of libgcc.a from the GCC front-end. -# -LIBGCC=${shell ${CC} -mthumb -march=armv6t2 -print-libgcc-file-name} - -# -# Get the location of libc.a from the GCC front-end. -# -LIBC=${shell ${CC} -mthumb -march=armv6t2 -print-file-name=libc.a} - -# -# The command for extracting images from the linked executables. -# -OBJCOPY=arm-stellaris-eabi-objcopy - -endif - -#****************************************************************************** -# -# Tell the compiler to include debugging information if the DEBUG environment -# variable is set. -# -#****************************************************************************** -ifdef DEBUG -CFLAGS += -g -endif - -#****************************************************************************** -# -# The rule for building the object file from each C source file. -# -#****************************************************************************** -${COMPILER}/%.o: %.c - @if [ 'x${VERBOSE}' = x ]; \ - then \ - echo " CC ${<}"; \ - else \ - echo ${CC} ${CFLAGS} -D${COMPILER} -o ${@} -c ${<}; \ - fi - @${CC} ${CFLAGS} -D${COMPILER} -o ${@} -c ${<} -ifeq (${COMPILER}, rvds) - @mv -f ${notdir ${@:.o=.d}} ${COMPILER} -endif - -#****************************************************************************** -# -# The rule for building the object file from each assembly source file. -# -#****************************************************************************** -${COMPILER}/%.o: %.S - @if [ 'x${VERBOSE}' = x ]; \ - then \ - echo " CC ${<}"; \ - else \ - echo ${CC} ${AFLAGS} -D${COMPILER} -o ${@} -c ${<}; \ - fi -ifeq (${COMPILER}, rvds) - @${CC} ${AFLAGS} -D${COMPILER} -E ${<} > ${@:.o=_.S} - @${CC} ${AFLAGS} -o ${@} -c ${@:.o=_.S} - @rm ${@:.o=_.S} - @${CC} ${AFLAGS} -D${COMPILER} --md -E ${<} - @sed 's,,${@},g' ${notdir ${<:.S=.d}} > ${@:.o=.d} - @rm ${notdir ${<:.S=.d}} -endif -ifeq (${COMPILER}, gcc) - @${CC} ${AFLAGS} -D${COMPILER} -o ${@} -c ${<} -endif - -#****************************************************************************** -# -# The rule for creating an object library. -# -#****************************************************************************** -${COMPILER}/%.a: - @if [ 'x${VERBOSE}' = x ]; \ - then \ - echo " AR ${@}"; \ - else \ - echo ${AR} -cr ${@} ${^}; \ - fi - @${AR} -cr ${@} ${^} - -#****************************************************************************** -# -# The rule for linking the application. -# -#****************************************************************************** -${COMPILER}/%.axf: - @if [ 'x${VERBOSE}' = x ]; \ - then \ - echo " LD ${@}"; \ - fi -ifeq (${COMPILER}, gcc) - @if [ 'x${VERBOSE}' != x ]; \ - then \ - echo ${LD} -T ${SCATTER_${notdir ${@:.axf=}}} \ - --entry ${ENTRY_${notdir ${@:.axf=}}} \ - ${LDFLAGSgcc_${notdir ${@:.axf=}}} \ - ${LDFLAGS} -o ${@} ${^} \ - '${LIBC}' '${LIBGCC}'; \ - fi - @${LD} -T ${SCATTER_${notdir ${@:.axf=}}} \ - --entry ${ENTRY_${notdir ${@:.axf=}}} \ - ${LDFLAGSgcc_${notdir ${@:.axf=}}} \ - ${LDFLAGS} -o ${@} ${^} \ - '${LIBC}' '${LIBGCC}' - @${OBJCOPY} -O binary ${@} ${@:.axf=.bin} -endif diff --git a/Demo/CORTEX_LM3S102_GCC/standalone.ld b/Demo/CORTEX_LM3S102_GCC/standalone.ld deleted file mode 100644 index 1f1d7baab..000000000 --- a/Demo/CORTEX_LM3S102_GCC/standalone.ld +++ /dev/null @@ -1,58 +0,0 @@ -/****************************************************************************** - * - * standalone.ld - Linker script for applications using startup.c and - * DriverLib. - * - * Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. - * - * Software License Agreement - * - * Luminary Micro, Inc. (LMI) is supplying this software for use solely and - * exclusively on LMI's Stellaris Family of microcontroller products. - * - * The software is owned by LMI and/or its suppliers, and is protected under - * applicable copyright laws. All rights are reserved. Any use in violation - * of the foregoing restrictions may subject the user to criminal sanctions - * under applicable laws, as well as to civil liability for the breach of the - * terms and conditions of this license. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - *****************************************************************************/ - -MEMORY -{ - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 8K - SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 2K -} - -SECTIONS -{ - .text : - { - *(vectors) - *(.text) - *(.rodata*) - *(.constdata*) - _etext = .; - } > FLASH - - .data : AT (ADDR(.text) + SIZEOF(.text)) - { - _data = .; - *(vtable) - *(.data) - _edata = .; - } > SRAM - - .bss : - { - _bss = .; - *(.bss) - _ebss = .; - } > SRAM -} diff --git a/Demo/CORTEX_LM3S102_KEIL/Demo1/FreeRTOSConfig.h b/Demo/CORTEX_LM3S102_KEIL/Demo1/FreeRTOSConfig.h deleted file mode 100644 index 51d644b1a..000000000 --- a/Demo/CORTEX_LM3S102_KEIL/Demo1/FreeRTOSConfig.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 1 -#define configUSE_TICK_HOOK 0 -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 ) -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 59 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1468 ) ) -#define configMAX_TASK_NAME_LEN ( 3 ) -#define configUSE_TRACE_FACILITY 0 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 0 -#define configUSE_CO_ROUTINES 1 - -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 ) -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 0 -#define INCLUDE_uxTaskPriorityGet 0 -#define INCLUDE_vTaskDelete 0 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 0 -#define INCLUDE_vTaskDelayUntil 0 -#define INCLUDE_vTaskDelay 1 - - - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/CORTEX_LM3S102_KEIL/Demo1/main.c b/Demo/CORTEX_LM3S102_KEIL/Demo1/main.c deleted file mode 100644 index a43768c20..000000000 --- a/Demo/CORTEX_LM3S102_KEIL/Demo1/main.c +++ /dev/null @@ -1,599 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * This demo application creates six co-routines and two tasks (three including - * the idle task). The co-routines execute as part of the idle task hook. - * - * Five of the created co-routines are the standard 'co-routine flash' - * co-routines contained within the Demo/Common/Minimal/crflash.c file and - * documented on the FreeRTOS.org WEB site. - * - * The 'LCD Task' rotates a string on the LCD, delaying between each character - * as necessitated by the slow interface, and delaying between each string just - * long enough to enable the text to be read. - * - * The sixth co-routine and final task control the transmission and reception - * of a string to UART 0. The co-routine periodically sends the first - * character of the string to the UART, with the UART's TxEnd interrupt being - * used to transmit the remaining characters. The UART's RxEnd interrupt - * receives the characters and places them on a queue to be processed by the - * 'COMs Rx' task. An error is latched should an unexpected character be - * received, or any character be received out of sequence. - * - * A loopback connector is required to ensure that each character transmitted - * on the UART is also received on the same UART. For test purposes the UART - * FIFO's are not utalised in order to maximise the interrupt overhead. Also - * a pseudo random interval is used between the start of each transmission in - * order that the resultant interrupts are more randomly distributed and - * therefore more likely to highlight any problems. - * - * The flash co-routines control LED's zero to four. LED five is toggled each - * time the string is transmitted on the UART. LED six is toggled each time - * the string is CORRECTLY received on the UART. LED seven is latched on should - * an error be detected in any task or co-routine. - * - * In addition the idle task makes repetative calls to - * prvSetAndCheckRegisters(). This simply loads the general purpose registers - * with a known value, then checks each register to ensure the held value is - * still correct. As a low priority task this checking routine is likely to - * get repeatedly swapped in and out. A register being found to contain an - * incorrect value is therefore indicative of an error in the task switching - * mechansim. - * - */ - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" -#include "croutine.h" - -/* Demo application include files. */ -#include "partest.h" -#include "crflash.h" - -/* Library include files. */ -#include "LM3Sxxx.h" -#include "pdc.h" - -/* The time to delay between writing each character to the LCD. */ -#define mainCHAR_WRITE_DELAY ( 2 / portTICK_RATE_MS ) - -/* The time to delay between writing each string to the LCD. */ -#define mainSTRING_WRITE_DELAY ( 400 / portTICK_RATE_MS ) - -/* The number of flash co-routines to create. */ -#define mainNUM_FLASH_CO_ROUTINES ( 5 ) - -/* The length of the queue used to pass received characters to the Comms Rx -task. */ -#define mainRX_QUEUE_LEN ( 5 ) - -/* The priority of the co-routine used to initiate the transmission of the -string on UART 0. */ -#define mainTX_CO_ROUTINE_PRIORITY ( 1 ) - -/* Only one co-routine is created so its index is not important. */ -#define mainTX_CO_ROUTINE_INDEX ( 0 ) - -/* The time between transmissions of the string on UART 0. This is pseudo -random in order to generate a bit or randomness to when the interrupts occur.*/ -#define mainMIN_TX_DELAY ( 40 / portTICK_RATE_MS ) -#define mainMAX_TX_DELAY ( ( portTickType ) 0x7f ) -#define mainOFFSET_TIME ( ( portTickType ) 3 ) - -/* The time the Comms Rx task should wait to receive a character. This should -be slightly longer than the time between transmissions. If we do not receive -a character after this time then there must be an error in the transmission or -the timing of the transmission. */ -#define mainCOMMS_RX_DELAY ( mainMAX_TX_DELAY + 20 ) - -/* The task priorites. */ -#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY ) -#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) - -/* The LED's toggled by the various tasks. */ -#define mainCOMMS_FAIL_LED ( 7 ) -#define mainCOMMS_RX_LED ( 6 ) -#define mainCOMMS_TX_LED ( 5 ) - -/* The baud rate used by the UART comms tasks/co-routine. */ -#define mainBAUD_RATE ( 57600 ) - -/* FIFO setting for the UART. The FIFO is not used to create a better test. */ -#define mainFIFO_SET ( 0x10 ) - -/* The string that is transmitted on the UART contains sequentially the -characters from mainFIRST_TX_CHAR to mainLAST_TX_CHAR. */ -#define mainFIRST_TX_CHAR '0' -#define mainLAST_TX_CHAR 'z' - -/* Just used to walk through the program memory in order that some random data -can be generated. */ -#define mainTOTAL_PROGRAM_MEMORY ( ( unsigned portLONG * ) ( 8 * 1024 ) ) -#define mainFIRST_PROGRAM_BYTES ( ( unsigned portLONG * ) 4 ) - -/*-----------------------------------------------------------*/ - -/* - * The task that rotates text on the LCD. - */ -static void vLCDTask( void * pvParameters ); - -/* - * The task that receives the characters from UART 0. - */ -static void vCommsRxTask( void * pvParameters ); - -/* - * The co-routine that periodically initiates the transmission of the string on - * the UART. - */ -static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); - -/* - * Writes a string the the LCD. - */ -static void prvWriteString( const portCHAR *pcString ); - -/* - * Initialisation routine for the UART. - */ -static void vSerialInit( void ); - -/* - * Thread safe write to the PDC. - */ -static void prvPDCWrite( portCHAR cAddress, portCHAR cData ); - -/* - * Function to simply set a known value into the general purpose registers - * then read them back to ensure they remain set correctly. An incorrect value - * being indicative of an error in the task switching mechanism. - */ -void prvSetAndCheckRegisters( void ); - -/* - * Latch the LED that indicates that an error has occurred. - */ -void vSetErrorLED( void ); - -/* - * Sets up the PLL and ports used by the demo. - */ -static void prvSetupHardware( void ); - -/*-----------------------------------------------------------*/ - -/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines -defined within this file. */ -unsigned portBASE_TYPE uxErrorStatus = pdPASS; - -/* The next character to transmit. */ -static portCHAR cNextChar; - -/* The queue used to transmit characters from the interrupt to the Comms Rx -task. */ -static xQueueHandle xCommsQueue; - -/*-----------------------------------------------------------*/ - -int main( void ) -{ - /* Create the queue used to communicate between the UART ISR and the Comms - Rx task. */ - xCommsQueue = xQueueCreate( mainRX_QUEUE_LEN, sizeof( portCHAR ) ); - - /* Setup the ports used by the demo and the clock. */ - prvSetupHardware(); - - /* Create the co-routines that flash the LED's. */ - vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES ); - - /* Create the co-routine that initiates the transmission of characters - on the UART. */ - xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX ); - - /* Create the LCD and Comms Rx tasks. */ - xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL ); - xTaskCreate( vCommsRxTask, "CMS", configMINIMAL_STACK_SIZE, NULL, mainCOMMS_RX_TASK_PRIORITY, NULL ); - - /* Start the scheduler running the tasks and co-routines just created. */ - vTaskStartScheduler(); - - /* Should not get here unless we did not have enough memory to start the - scheduler. */ - for( ;; ); -} -/*-----------------------------------------------------------*/ - -static void prvSetupHardware( void ) -{ - /* Setup the PLL. */ - SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); - - /* Initialise the hardware used to talk to the LCD, LED's and UART. */ - PDCInit(); - vParTestInitialise(); - vSerialInit(); -} -/*-----------------------------------------------------------*/ - -void vApplicationIdleHook( void ) -{ - /* The co-routines are executed in the idle task using the idle task - hook. */ - for( ;; ) - { - /* Schedule the co-routines. */ - vCoRoutineSchedule(); - - /* Run the register check function between each co-routine. */ - prvSetAndCheckRegisters(); - } -} -/*-----------------------------------------------------------*/ - -static void prvWriteString( const portCHAR *pcString ) -{ - /* Write pcString to the LED, pausing between each character. */ - prvPDCWrite(PDC_LCD_CSR, LCD_CLEAR); - while( *pcString ) - { - vTaskDelay( mainCHAR_WRITE_DELAY ); - prvPDCWrite( PDC_LCD_RAM, *pcString ); - pcString++; - } -} -/*-----------------------------------------------------------*/ - -void vLCDTask( void * pvParameters ) -{ -unsigned portBASE_TYPE uxIndex; -const unsigned portCHAR ucCFGData[] = { - 0x30, /* Set data bus to 8-bits. */ - 0x30, - 0x30, - 0x3C, /* Number of lines/font. */ - 0x08, /* Display off. */ - 0x01, /* Display clear. */ - 0x06, /* Entry mode [cursor dir][shift]. */ - 0x0C /* Display on [display on][curson on][blinking on]. */ - }; - -/* The strings that are written to the LCD. */ -const portCHAR *pcStringsToDisplay[] = { - "Stellaris", - "Demo", - "One", - "www.FreeRTOS.org", - "" - }; - - /* Configure the LCD. */ - uxIndex = 0; - while( uxIndex < sizeof( ucCFGData ) ) - { - prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] ); - uxIndex++; - vTaskDelay( mainCHAR_WRITE_DELAY ); - } - - /* Turn the LCD Backlight on. */ - prvPDCWrite( PDC_CSR, 0x01 ); - - /* Clear display. */ - vTaskDelay( mainCHAR_WRITE_DELAY ); - prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); - - uxIndex = 0; - for( ;; ) - { - /* Display the string on the LCD. */ - prvWriteString( pcStringsToDisplay[ uxIndex ] ); - - /* Move on to the next string - wrapping if necessary. */ - uxIndex++; - if( *( pcStringsToDisplay[ uxIndex ] ) == 0x00 ) - { - uxIndex = 0; - /* Longer pause on the last string to be sent. */ - vTaskDelay( mainSTRING_WRITE_DELAY * 2 ); - } - - /* Wait until it is time to move onto the next string. */ - vTaskDelay( mainSTRING_WRITE_DELAY ); - } -} -/*-----------------------------------------------------------*/ - -static void vCommsRxTask( void * pvParameters ) -{ -static portCHAR cRxedChar, cExpectedChar; - - /* Set the char we expect to receive to the start of the string. */ - cExpectedChar = mainFIRST_TX_CHAR; - - for( ;; ) - { - /* Wait for a character to be received. */ - xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY ); - - /* Was the character recived (if any) the expected character. */ - if( cRxedChar != cExpectedChar ) - { - /* Got an unexpected character. This can sometimes occur when - reseting the system using the debugger leaving characters already - in the UART regsters. */ - uxErrorStatus = pdFAIL; - - /* Resync by waiting for the end of the current string. */ - while( cRxedChar != mainLAST_TX_CHAR ) - { - while( !xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, portMAX_DELAY ) ); - } - - /* The next expected character is the start of the string again. */ - cExpectedChar = mainFIRST_TX_CHAR; - } - else - { - if( cExpectedChar == mainLAST_TX_CHAR ) - { - /* We have reached the end of the string - we now expect to - receive the first character in the string again. The LED is - toggled to indicate that the entire string was received without - error. */ - vParTestToggleLED( mainCOMMS_RX_LED ); - cExpectedChar = mainFIRST_TX_CHAR; - } - else - { - /* We got the expected character, we now expect to receive the - next character in the string. */ - cExpectedChar++; - } - } - } -} -/*-----------------------------------------------------------*/ - -static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) -{ -portTickType xDelayPeriod; -static unsigned portLONG *pulRandomBytes = mainFIRST_PROGRAM_BYTES; - - /* Co-routine MUST start with a call to crSTART. */ - crSTART( xHandle ); - - for(;;) - { - /* Was the previously transmitted string received correctly? */ - if( uxErrorStatus != pdPASS ) - { - /* An error was encountered so set the error LED. */ - vSetErrorLED(); - } - - /* The next character to Tx is the first in the string. */ - cNextChar = mainFIRST_TX_CHAR; - - UARTIntDisable( UART0_BASE, UART_INT_TX ); - { - /* Send the first character. */ - if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) - { - HWREG( UART0_BASE + UART_O_DR ) = cNextChar; - } - - /* Move the variable to the char to Tx on so the ISR transmits - the next character in the string once this one has completed. */ - cNextChar++; - } - UARTIntEnable(UART0_BASE, UART_INT_TX); - - /* Toggle the LED to show a new string is being transmitted. */ - vParTestToggleLED( mainCOMMS_TX_LED ); - - /* Delay before we start the string off again. A pseudo-random delay - is used as this will provide a better test. */ - xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes ); - - pulRandomBytes++; - if( pulRandomBytes > mainTOTAL_PROGRAM_MEMORY ) - { - pulRandomBytes = mainFIRST_PROGRAM_BYTES; - } - - /* Make sure we don't wait too long... */ - xDelayPeriod &= mainMAX_TX_DELAY; - - /* ...but we do want to wait. */ - if( xDelayPeriod < mainMIN_TX_DELAY ) - { - xDelayPeriod = mainMIN_TX_DELAY; - } - - /* Block for the random(ish) time. */ - crDELAY( xHandle, xDelayPeriod ); - } - - /* Co-routine MUST end with a call to crEND. */ - crEND(); -} -/*-----------------------------------------------------------*/ - -static void vSerialInit( void ) -{ - /* Enable the UART. GPIOA has already been initialised. */ - SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); - - /* Set GPIO A0 and A1 as peripheral function. They are used to output the - UART signals. */ - GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); - - /* Configure the UART for 8-N-1 operation. */ - UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); - - /* We dont want to use the fifo. This is for test purposes to generate - as many interrupts as possible. */ - HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; - - /* Enable both Rx and Tx interrupts. */ - HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX ); - IntEnable( INT_UART0 ); -} -/*-----------------------------------------------------------*/ - -void vUART_ISR(void) -{ -unsigned portLONG ulStatus; -portCHAR cRxedChar; -portBASE_TYPE xTaskWokenByPost = pdFALSE; - - /* What caused the interrupt. */ - ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); - - /* Clear the interrupt. */ - UARTIntClear( UART0_BASE, ulStatus ); - - /* Was an Rx interrpt pending? */ - if( ulStatus & UART_INT_RX ) - { - if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) ) - { - /* Get the char from the buffer and post it onto the queue of - Rxed chars. Posting the character should wake the task that is - blocked on the queue waiting for characters. */ - cRxedChar = ( portCHAR ) HWREG( UART0_BASE + UART_O_DR ); - xTaskWokenByPost = xQueueSendFromISR( xCommsQueue, &cRxedChar, xTaskWokenByPost ); - } - } - - /* Was a Tx interrupt pending? */ - if( ulStatus & UART_INT_TX ) - { - /* Send the next character in the string. We are not using the FIFO. */ - if( cNextChar <= mainLAST_TX_CHAR ) - { - if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) - { - HWREG( UART0_BASE + UART_O_DR ) = cNextChar; - } - cNextChar++; - } - } - - if( xTaskWokenByPost ) - { - /* If a task was woken by the character being received then we force - a context switch to occur in case the task is of higher priority than - the currently executing task (i.e. the task that this interrupt - interrupted.) */ - portEND_SWITCHING_ISR( xTaskWokenByPost ); - } -} -/*-----------------------------------------------------------*/ - -static void prvPDCWrite( portCHAR cAddress, portCHAR cData ) -{ - vTaskSuspendAll(); - { - PDCWrite( cAddress, cData ); - } - xTaskResumeAll(); -} -/*-----------------------------------------------------------*/ - -void vSetErrorLED( void ) -{ - vParTestSetLED( mainCOMMS_FAIL_LED, pdTRUE ); -} -/*-----------------------------------------------------------*/ - -__asm void prvSetAndCheckRegisters( void ) -{ - extern vSetErrorLED - - /* Fill the general purpose registers with known values. */ - mov r11, #10 - add r0, r11, #1 - add r1, r11, #2 - add r2, r11, #3 - add r3, r11, #4 - add r4, r11, #5 - add r5, r11, #6 - add r6, r11, #7 - add r7, r11, #8 - add r8, r11, #9 - add r9, r11, #10 - add r10, r11, #11 - add r12, r11, #12 - - /* Check the values are as expected. */ - cmp r11, #10 - bne set_error_led - cmp r0, #11 - bne set_error_led - cmp r1, #12 - bne set_error_led - cmp r2, #13 - bne set_error_led - cmp r3, #14 - bne set_error_led - cmp r4, #15 - bne set_error_led - cmp r5, #16 - bne set_error_led - cmp r6, #17 - bne set_error_led - cmp r7, #18 - bne set_error_led - cmp r8, #19 - bne set_error_led - cmp r9, #20 - bne set_error_led - cmp r10, #21 - bne set_error_led - cmp r12, #22 - bne set_error_led - bx lr - -set_error_led; - push {r14} - ldr r1, =vSetErrorLED - blx r1 - pop {r14} - bx lr; -} -/*-----------------------------------------------------------*/ diff --git a/Demo/CORTEX_LM3S102_KEIL/Demo1/readme.txt b/Demo/CORTEX_LM3S102_KEIL/Demo1/readme.txt deleted file mode 100644 index 10334b9be..000000000 --- a/Demo/CORTEX_LM3S102_KEIL/Demo1/readme.txt +++ /dev/null @@ -1,3 +0,0 @@ -Move these two fines into the Demo/CORTEX_LM3S102_KEIL directory to run Demo 1. - -See the port documentation on the www.FreeRTOS.org site for more information. diff --git a/Demo/CORTEX_LM3S102_KEIL/Demo2/FreeRTOSConfig.h b/Demo/CORTEX_LM3S102_KEIL/Demo2/FreeRTOSConfig.h deleted file mode 100644 index b39c502a1..000000000 --- a/Demo/CORTEX_LM3S102_KEIL/Demo2/FreeRTOSConfig.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 1 -#define configUSE_TICK_HOOK 0 -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 ) -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 59 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1240 ) ) -#define configMAX_TASK_NAME_LEN ( 3 ) -#define configUSE_TRACE_FACILITY 0 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 0 -#define configUSE_CO_ROUTINES 1 - -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 ) -#define configMAX_CO_ROUTINE_PRIORITIES ( 3 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 0 -#define INCLUDE_uxTaskPriorityGet 0 -#define INCLUDE_vTaskDelete 0 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 0 -#define INCLUDE_vTaskDelayUntil 0 -#define INCLUDE_vTaskDelay 1 - - - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/CORTEX_LM3S102_KEIL/Demo2/main.c b/Demo/CORTEX_LM3S102_KEIL/Demo2/main.c deleted file mode 100644 index 9a16a6951..000000000 --- a/Demo/CORTEX_LM3S102_KEIL/Demo2/main.c +++ /dev/null @@ -1,604 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * This demo application creates seven co-routines and one task (two including - * the idle task). The co-routines execute as part of the idle task hook. - * - * Five of the created co-routines are the standard 'co-routine flash' - * co-routines contained within the Demo/Common/Minimal/crflash.c file and - * documented on the FreeRTOS.org WEB site. - * - * The 'LCD Task' rotates a string on the LCD, delaying between each character - * as necessitated by the slow interface, and delaying between each string just - * long enough to enable the text to be read. - * - * The sixth co-routine controls the transmission of a string to UART 0. The - * co-routine periodically sends the first character of the string to the UART, - * with the UART's TxEnd interrupt being used to transmit the remaining - * characters. The UART's RxEnd interrupt receives the characters and places - * them on a queue to be processed by the seventh and final co-routine. An - * error is latched should an unexpected character be received, or any - * character be received out of sequence. - * - * A loopback connector is required to ensure that each character transmitted - * on the UART is also received on the same UART. For test purposes the UART - * FIFO's are not utalised in order to maximise the interrupt overhead. Also - * a pseudo random interval is used between the start of each transmission in - * order that the resultant interrupts are more randomly distributed and - * therefore more likely to highlight any problems. - * - * The flash co-routines control LED's zero to four. LED five is toggled each - * time the string is transmitted on the UART. LED six is toggled each time - * the string is CORRECTLY received on the UART. LED seven is latched on should - * an error be detected in any task or co-routine. - * - * In addition the idle task makes repetative calls to - * prvSetAndCheckRegisters(). This simply loads the general purpose registers - * with a known value, then checks each register to ensure the held value is - * still correct. As a low priority task this checking routine is likely to - * get repeatedly swapped in and out. A register being found to contain an - * incorrect value is therefore indicative of an error in the task switching - * mechansim. - * - */ - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" -#include "croutine.h" - -/* Demo application include files. */ -#include "partest.h" -#include "crflash.h" - -/* Library include files. */ -#include "LM3Sxxx.h" -#include "pdc.h" - -/* The time to delay between writing each character to the LCD. */ -#define mainCHAR_WRITE_DELAY ( 2 / portTICK_RATE_MS ) - -/* The time to delay between writing each string to the LCD. */ -#define mainSTRING_WRITE_DELAY ( 400 / portTICK_RATE_MS ) - -/* The number of flash co-routines to create. */ -#define mainNUM_FLASH_CO_ROUTINES ( 5 ) - -/* The length of the queue used to pass received characters to the Comms Rx -task. */ -#define mainRX_QUEUE_LEN ( 5 ) - -/* The priority of the co-routine used to initiate the transmission of the -string on UART 0. */ -#define mainTX_CO_ROUTINE_PRIORITY ( 1 ) - -/* The priority of the co-routine used to receive characters from the UART. */ -#define mainRX_CO_ROUTINE_PRIORITY ( 2 ) - -/* Only one co-routine is created so its index is not important. */ -#define mainTX_CO_ROUTINE_INDEX ( 0 ) -#define mainRX_CO_ROUTINE_INDEX ( 0 ) - -/* The time between transmissions of the string on UART 0. This is pseudo -random in order to generate a bit or randomness to when the interrupts occur.*/ -#define mainMIN_TX_DELAY ( 40 / portTICK_RATE_MS ) -#define mainMAX_TX_DELAY ( ( portTickType ) 0x7f ) -#define mainOFFSET_TIME ( ( portTickType ) 3 ) - -/* The time the Comms Rx task should wait to receive a character. This should -be slightly longer than the time between transmissions. If we do not receive -a character after this time then there must be an error in the transmission or -the timing of the transmission. */ -#define mainCOMMS_RX_DELAY ( mainMAX_TX_DELAY + 20 ) - -/* The task priorites. */ -#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY ) -#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) - -/* The LED's toggled by the various tasks. */ -#define mainCOMMS_FAIL_LED ( 7 ) -#define mainCOMMS_RX_LED ( 6 ) -#define mainCOMMS_TX_LED ( 5 ) - -/* The baud rate used by the UART comms tasks/co-routine. */ -#define mainBAUD_RATE ( 57600 ) - -/* FIFO setting for the UART. The FIFO is not used to create a better test. */ -#define mainFIFO_SET ( 0x10 ) - -/* The string that is transmitted on the UART contains sequentially the -characters from mainFIRST_TX_CHAR to mainLAST_TX_CHAR. */ -#define mainFIRST_TX_CHAR '0' -#define mainLAST_TX_CHAR 'z' - -/* Just used to walk through the program memory in order that some random data -can be generated. */ -#define mainTOTAL_PROGRAM_MEMORY ( ( unsigned portLONG * ) ( 8 * 1024 ) ) -#define mainFIRST_PROGRAM_BYTES ( ( unsigned portLONG * ) 4 ) - -/*-----------------------------------------------------------*/ - -/* - * The task that rotates text on the LCD. - */ -static void vLCDTask( void * pvParameters ); - -/* - * The task that receives the characters from UART 0. - */ -static void vCommsRxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); - -/* - * The co-routine that periodically initiates the transmission of the string on - * the UART. - */ -static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); - -/* - * Writes a string the the LCD. - */ -static void prvWriteString( const portCHAR *pcString ); - -/* - * Initialisation routine for the UART. - */ -static void vSerialInit( void ); - -/* - * Thread safe write to the PDC. - */ -static void prvPDCWrite( portCHAR cAddress, portCHAR cData ); - -/* - * Function to simply set a known value into the general purpose registers - * then read them back to ensure they remain set correctly. An incorrect value - * being indicative of an error in the task switching mechanism. - */ -void prvSetAndCheckRegisters( void ); - -/* - * Latch the LED that indicates that an error has occurred. - */ -void vSetErrorLED( void ); - -/* - * Sets up the PLL and ports used by the demo. - */ -static void prvSetupHardware( void ); - -/*-----------------------------------------------------------*/ - -/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines -defined within this file. */ -unsigned portBASE_TYPE uxErrorStatus = pdPASS; - -/* The next character to transmit. */ -static portCHAR cNextChar; - -/* The queue used to transmit characters from the interrupt to the Comms Rx -task. */ -static xQueueHandle xCommsQueue; - -/*-----------------------------------------------------------*/ - -int main( void ) -{ - /* Create the queue used to communicate between the UART ISR and the Comms - Rx task. */ - xCommsQueue = xQueueCreate( mainRX_QUEUE_LEN, sizeof( portCHAR ) ); - - /* Setup the ports used by the demo and the clock. */ - prvSetupHardware(); - - /* Create the co-routines that flash the LED's. */ - vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES ); - - /* Create the co-routine that initiates the transmission of characters - on the UART. */ - xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX ); - - /* Create the co-routine that receives characters from the UART. */ - xCoRoutineCreate( vCommsRxCoRoutine, mainRX_CO_ROUTINE_PRIORITY, mainRX_CO_ROUTINE_INDEX ); - - /* Create the LCD task. */ - xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL ); - - /* Start the scheduler running the tasks and co-routines just created. */ - vTaskStartScheduler(); - - /* Should not get here unless we did not have enough memory to start the - scheduler. */ - for( ;; ); -} -/*-----------------------------------------------------------*/ - -static void prvSetupHardware( void ) -{ - /* Setup the PLL. */ - SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); - - /* Initialise the hardware used to talk to the LCD, LED's and UART. */ - PDCInit(); - vParTestInitialise(); - vSerialInit(); -} -/*-----------------------------------------------------------*/ - -void vApplicationIdleHook( void ) -{ - /* The co-routines are executed in the idle task using the idle task - hook. */ - for( ;; ) - { - /* Schedule the co-routines. */ - vCoRoutineSchedule(); - - /* Run the register check function between each co-routine. */ - prvSetAndCheckRegisters(); - } -} -/*-----------------------------------------------------------*/ - -static void prvWriteString( const portCHAR *pcString ) -{ - /* Write pcString to the LED, pausing between each character. */ - prvPDCWrite(PDC_LCD_CSR, LCD_CLEAR); - while( *pcString ) - { - vTaskDelay( mainCHAR_WRITE_DELAY ); - prvPDCWrite( PDC_LCD_RAM, *pcString ); - pcString++; - } -} -/*-----------------------------------------------------------*/ - -void vLCDTask( void * pvParameters ) -{ -unsigned portBASE_TYPE uxIndex; -const unsigned portCHAR ucCFGData[] = { - 0x30, /* Set data bus to 8-bits. */ - 0x30, - 0x30, - 0x3C, /* Number of lines/font. */ - 0x08, /* Display off. */ - 0x01, /* Display clear. */ - 0x06, /* Entry mode [cursor dir][shift]. */ - 0x0C /* Display on [display on][curson on][blinking on]. */ - }; - -/* The strings that are written to the LCD. */ -const portCHAR *pcStringsToDisplay[] = { - "Stellaris", - "Demo", - "Two", - "www.FreeRTOS.org", - "" - }; - - /* Configure the LCD. */ - uxIndex = 0; - while( uxIndex < sizeof( ucCFGData ) ) - { - prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] ); - uxIndex++; - vTaskDelay( mainCHAR_WRITE_DELAY ); - } - - /* Turn the LCD Backlight on. */ - prvPDCWrite( PDC_CSR, 0x01 ); - - /* Clear display. */ - vTaskDelay( mainCHAR_WRITE_DELAY ); - prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); - - uxIndex = 0; - for( ;; ) - { - /* Display the string on the LCD. */ - prvWriteString( pcStringsToDisplay[ uxIndex ] ); - - /* Move on to the next string - wrapping if necessary. */ - uxIndex++; - if( *( pcStringsToDisplay[ uxIndex ] ) == 0x00 ) - { - uxIndex = 0; - /* Longer pause on the last string to be sent. */ - vTaskDelay( mainSTRING_WRITE_DELAY * 2 ); - } - - /* Wait until it is time to move onto the next string. */ - vTaskDelay( mainSTRING_WRITE_DELAY ); - } -} -/*-----------------------------------------------------------*/ - -static void vCommsRxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) -{ -static portCHAR cRxedChar, cExpectedChar = mainFIRST_TX_CHAR; -portBASE_TYPE xResult; - - crSTART( xHandle ); - - for( ;; ) - { - /* Wait for a character to be received. */ - crQUEUE_RECEIVE( xHandle, xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY, &xResult ); - - /* Was the character recived (if any) the expected character. */ - if( ( cRxedChar != cExpectedChar ) || ( xResult != pdPASS ) ) - { - /* Got an unexpected character. This can sometimes occur when - reseting the system using the debugger leaving characters already - in the UART regsters. */ - uxErrorStatus = pdFAIL; - - /* Resync by waiting for the end of the current string. */ - while( cRxedChar != mainLAST_TX_CHAR ) - { - crQUEUE_RECEIVE( xHandle, xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY, &xResult ); - } - - /* The next expected character is the start of the string again. */ - cExpectedChar = mainFIRST_TX_CHAR; - } - else - { - if( cExpectedChar == mainLAST_TX_CHAR ) - { - /* We have reached the end of the string - we now expect to - receive the first character in the string again. The LED is - toggled to indicate that the entire string was received without - error. */ - vParTestToggleLED( mainCOMMS_RX_LED ); - cExpectedChar = mainFIRST_TX_CHAR; - } - else - { - /* We got the expected character, we now expect to receive the - next character in the string. */ - cExpectedChar++; - } - } - } - - crEND(); -} -/*-----------------------------------------------------------*/ - -static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) -{ -portTickType xDelayPeriod; -static unsigned portLONG *pulRandomBytes = mainFIRST_PROGRAM_BYTES; - - /* Co-routine MUST start with a call to crSTART. */ - crSTART( xHandle ); - - for(;;) - { - /* Was the previously transmitted string received correctly? */ - if( uxErrorStatus != pdPASS ) - { - /* An error was encountered so set the error LED. */ - vSetErrorLED(); - } - - /* The next character to Tx is the first in the string. */ - cNextChar = mainFIRST_TX_CHAR; - - UARTIntDisable( UART0_BASE, UART_INT_TX ); - { - /* Send the first character. */ - if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) - { - HWREG( UART0_BASE + UART_O_DR ) = cNextChar; - } - - /* Move the variable to the char to Tx on so the ISR transmits - the next character in the string once this one has completed. */ - cNextChar++; - } - UARTIntEnable(UART0_BASE, UART_INT_TX); - - /* Toggle the LED to show a new string is being transmitted. */ - vParTestToggleLED( mainCOMMS_TX_LED ); - - /* Delay before we start the string off again. A pseudo-random delay - is used as this will provide a better test. */ - xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes ); - - pulRandomBytes++; - if( pulRandomBytes > mainTOTAL_PROGRAM_MEMORY ) - { - pulRandomBytes = mainFIRST_PROGRAM_BYTES; - } - - /* Make sure we don't wait too long... */ - xDelayPeriod &= mainMAX_TX_DELAY; - - /* ...but we do want to wait. */ - if( xDelayPeriod < mainMIN_TX_DELAY ) - { - xDelayPeriod = mainMIN_TX_DELAY; - } - - /* Block for the random(ish) time. */ - crDELAY( xHandle, xDelayPeriod ); - } - - /* Co-routine MUST end with a call to crEND. */ - crEND(); -} -/*-----------------------------------------------------------*/ - -static void vSerialInit( void ) -{ - /* Enable the UART. GPIOA has already been initialised. */ - SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); - - /* Set GPIO A0 and A1 as peripheral function. They are used to output the - UART signals. */ - GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); - - /* Configure the UART for 8-N-1 operation. */ - UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); - - /* We dont want to use the fifo. This is for test purposes to generate - as many interrupts as possible. */ - HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; - - /* Enable both Rx and Tx interrupts. */ - HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX ); - IntEnable( INT_UART0 ); -} -/*-----------------------------------------------------------*/ - -void vUART_ISR(void) -{ -unsigned portLONG ulStatus; -portCHAR cRxedChar; -portBASE_TYPE xTaskWokenByPost = pdFALSE; - - /* What caused the interrupt. */ - ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); - - /* Clear the interrupt. */ - UARTIntClear( UART0_BASE, ulStatus ); - - /* Was an Rx interrpt pending? */ - if( ulStatus & UART_INT_RX ) - { - if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) ) - { - /* Get the char from the buffer and post it onto the queue of - Rxed chars. Posting the character should wake the task that is - blocked on the queue waiting for characters. */ - cRxedChar = ( portCHAR ) HWREG( UART0_BASE + UART_O_DR ); - xTaskWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsQueue, &cRxedChar, xTaskWokenByPost ); - } - } - - /* Was a Tx interrupt pending? */ - if( ulStatus & UART_INT_TX ) - { - /* Send the next character in the string. We are not using the FIFO. */ - if( cNextChar <= mainLAST_TX_CHAR ) - { - if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) - { - HWREG( UART0_BASE + UART_O_DR ) = cNextChar; - } - cNextChar++; - } - } - - if( xTaskWokenByPost ) - { - /* We are posting to a co-routine rather than a task so don't bother - causing a task switch. */ - } -} -/*-----------------------------------------------------------*/ - -static void prvPDCWrite( portCHAR cAddress, portCHAR cData ) -{ - vTaskSuspendAll(); - { - PDCWrite( cAddress, cData ); - } - xTaskResumeAll(); -} -/*-----------------------------------------------------------*/ - -void vSetErrorLED( void ) -{ - vParTestSetLED( mainCOMMS_FAIL_LED, pdTRUE ); -} -/*-----------------------------------------------------------*/ - -__asm void prvSetAndCheckRegisters( void ) -{ - extern vSetErrorLED - - /* Fill the general purpose registers with known values. */ - mov r11, #10 - add r0, r11, #1 - add r1, r11, #2 - add r2, r11, #3 - add r3, r11, #4 - add r4, r11, #5 - add r5, r11, #6 - add r6, r11, #7 - add r7, r11, #8 - add r8, r11, #9 - add r9, r11, #10 - add r10, r11, #11 - add r12, r11, #12 - - /* Check the values are as expected. */ - cmp r11, #10 - bne set_error_led - cmp r0, #11 - bne set_error_led - cmp r1, #12 - bne set_error_led - cmp r2, #13 - bne set_error_led - cmp r3, #14 - bne set_error_led - cmp r4, #15 - bne set_error_led - cmp r5, #16 - bne set_error_led - cmp r6, #17 - bne set_error_led - cmp r7, #18 - bne set_error_led - cmp r8, #19 - bne set_error_led - cmp r9, #20 - bne set_error_led - cmp r10, #21 - bne set_error_led - cmp r12, #22 - bne set_error_led - bx lr - -set_error_led; - push {r14} - ldr r1, =vSetErrorLED - blx r1 - pop {r14} - bx lr; -} -/*-----------------------------------------------------------*/ diff --git a/Demo/CORTEX_LM3S102_KEIL/Demo2/readme.txt b/Demo/CORTEX_LM3S102_KEIL/Demo2/readme.txt deleted file mode 100644 index 2ddb358de..000000000 --- a/Demo/CORTEX_LM3S102_KEIL/Demo2/readme.txt +++ /dev/null @@ -1,3 +0,0 @@ -Move these two fines into the Demo/CORTEX_LM3S102_KEIL directory to run Demo 2. - -See the port documentation on the www.FreeRTOS.org site for more information. diff --git a/Demo/CORTEX_LM3S102_KEIL/FreeRTOS.Opt b/Demo/CORTEX_LM3S102_KEIL/FreeRTOS.Opt deleted file mode 100644 index 548f3b365..000000000 --- a/Demo/CORTEX_LM3S102_KEIL/FreeRTOS.Opt +++ /dev/null @@ -1,47 +0,0 @@ -### uVision2 Project, (C) Keil Software -### Do not modify ! - - cExt (*.c) - aExt (*.s*; *.src; *.a*) - oExt (*.obj) - lExt (*.lib) - tExt (*.txt; *.h; *.inc) - pExt (*.plm) - CppX (*.cpp) - DaveTm { 0,0,0,0,0,0,0,0 } - -Target (LM3S1xx), 0x0004 // Tools: 'ARM-ADS' -GRPOPT 1,(Source),1,0,0 -GRPOPT 2,(Demo),1,0,0 - -OPTFFF 1,1,1,0,0,0,0,0,<..\..\Source\croutine.c> -OPTFFF 1,2,1,0,0,0,0,0,<..\..\Source\list.c> -OPTFFF 1,3,1,0,0,0,0,0,<..\..\Source\queue.c> -OPTFFF 1,4,1,0,0,0,0,0,<..\..\Source\tasks.c> -OPTFFF 1,5,1,0,0,0,0,0,<..\..\Source\portable\MemMang\heap_1.c> -OPTFFF 1,6,1,0,0,0,0,0,<..\..\Source\portable\RVDS\ARM_CM3\port.c> -OPTFFF 2,7,1,0,0,0,0,0,<.\main.c> -OPTFFF 2,8,2,0,0,0,0,0,<.\init\Startup.s> -OPTFFF 2,9,1,0,0,0,0,0,<..\Common\Minimal\crflash.c> -OPTFFF 2,10,1,0,0,0,0,0,<.\ParTest\ParTest.c> -OPTFFF 2,11,1,0,0,0,0,0,<.\include\pdc.c> -OPTFFF 2,12,4,0,0,0,0,0, - - -TARGOPT 1, (LM3S1xx) - ADSCLK=20000000 - OPTTT 1,1,1,0 - OPTHX 1,65535,0,0,0 - OPTLX 79,66,8,<.\uvision\> - OPTOX 16 - OPTLT 1,1,1,0,1,1,0,1,0,0,0,0 - OPTXL 1,1,1,1,1,1,1,0,0 - OPTFL 1,0,1 - OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S101)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S101) - OPTDBG 49150,1,()()()()()()()()()() (BIN\UL2CM3.DLL)()()() - OPTKEY 0,(UL2CM3)(-U -O14 -S0 -C-1 -FO7 -FD20000000 -FC800 -FN1 -FF0LM3S_8 -FS00 -FL02000) - OPTDF 0x0 - OPTLE <> - OPTLC <> -EndOpt - diff --git a/Demo/CORTEX_LM3S102_KEIL/FreeRTOS.Uv2 b/Demo/CORTEX_LM3S102_KEIL/FreeRTOS.Uv2 deleted file mode 100644 index 3afecbd5b..000000000 --- a/Demo/CORTEX_LM3S102_KEIL/FreeRTOS.Uv2 +++ /dev/null @@ -1,109 +0,0 @@ -### uVision2 Project, (C) Keil Software -### Do not modify ! - -Target (LM3S1xx), 0x0004 // Tools: 'ARM-ADS' - -Group (Source) -Group (Demo) - -File 1,1,<..\..\Source\croutine.c> 0x440790D8 -File 1,1,<..\..\Source\list.c> 0x440790D8 -File 1,1,<..\..\Source\queue.c> 0x440790D8 -File 1,1,<..\..\Source\tasks.c> 0x440790D8 -File 1,1,<..\..\Source\portable\MemMang\heap_1.c> 0x440790D8 -File 1,1,<..\..\Source\portable\RVDS\ARM_CM3\port.c> 0x440790D8 -File 2,1,<.\main.c> 0x441EE317 -File 2,2,<.\init\Startup.s> 0x44172A20 -File 2,1,<..\Common\Minimal\crflash.c> 0x440790D8 -File 2,1,<.\ParTest\ParTest.c> 0x440790D8 -File 2,1,<.\include\pdc.c> 0x44187439 -File 2,4, 0x44206F94 - - -Options 1,0,0 // Target 'LM3S1xx' - Device (LM3S101) - Vendor (Luminary Micro) - Cpu (IRAM(0x20000000-0x200007FF) IROM(0-0x1FFF) CLOCK(20000000) CPUTYPE("Cortex-M3")) - FlashUt () - StupF ("STARTUP\Luminary\Startup.s" ("Luminary Startup Code")) - FlashDR (UL2CM3(-U40296420 -O7 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0LM3S_8 -FS00 -FL02000)) - DevID (4079) - Rgf (LM3Sxxx.H) - Mem () - C () - A () - RL () - OH () - DBC_IFX () - DBC_CMS () - DBC_AMS () - DBC_LMS () - UseEnv=0 - EnvBin () - EnvInc () - EnvLib () - EnvReg (˙Luminary\) - OrgReg (˙Luminary\) - TgStat=0 - OutDir (.\uvision\) - OutName (RTOSDemo) - GenApp=1 - GenLib=0 - GenHex=0 - Debug=1 - Browse=1 - LstDir (.\uvision\) - HexSel=1 - MG32K=0 - TGMORE=0 - RunUsr 0 0 <> - RunUsr 1 0 <> - BrunUsr 0 0 <> - BrunUsr 1 0 <> - SVCSID <> - GLFLAGS=1790 - ADSFLGA { 243,31,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - ACPUTYP (Cortex-M3) - ADSTFLGA { 0,12,0,0,99,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - OCMADSIRAM { 0,0,0,0,32,0,8,0,0 } - OCMADSIROM { 1,0,0,0,0,0,32,0,0 } - OCMADSXRAM { 0,0,0,0,0,0,0,0,0 } - OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,32,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,8,0,0,0,0,0,0,0,0,0,0,0 } - RV_STAVEC () - ADSCCFLG { 8,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - ADSCMISC () - ADSCDEFN (RVDS_ARMCM3_LM3S102) - ADSCUDEF () - ADSCINCD (C:\Keil\ARM\RV30\LIB\Luminary;..\CORTEX_LM3S102_KEIL;..\..\Source\portable\RVDS\ARM_CM3;..\..\Source\include;..\Common\include;.\include) - ADSASFLG { 65,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - ADSAMISC (--diag_suppress 1581) - ADSADEFN () - ADSAUDEF () - ADSAINCD () - PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - IncBld=1 - AlwaysBuild=0 - GenAsm=0 - AsmAsm=0 - PublicsOnly=0 - StopCode=3 - CustArgs () - LibMods () - ADSLDFG { 16,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - ADSLDTA (0x00000000) - ADSLDDA (0x20000000) - ADSLDSC () - ADSLDIB () - ADSLDIC () - ADSLDMC (--entry Reset_Handler) - ADSLDIF () - ADSLDDW (6306) - OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S101)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S101) - OPTDBG 49150,1,()()()()()()()()()() (BIN\UL2CM3.DLL)()()() - FLASH1 { 1,0,0,0,1,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0 } - FLASH2 (BIN\UL2CM3.DLL) - FLASH3 ("" ()) - FLASH4 () -EndOpt - diff --git a/Demo/CORTEX_LM3S102_KEIL/FreeRTOSConfig.h b/Demo/CORTEX_LM3S102_KEIL/FreeRTOSConfig.h deleted file mode 100644 index 51d644b1a..000000000 --- a/Demo/CORTEX_LM3S102_KEIL/FreeRTOSConfig.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 1 -#define configUSE_TICK_HOOK 0 -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 ) -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 59 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1468 ) ) -#define configMAX_TASK_NAME_LEN ( 3 ) -#define configUSE_TRACE_FACILITY 0 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 0 -#define configUSE_CO_ROUTINES 1 - -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 ) -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 0 -#define INCLUDE_uxTaskPriorityGet 0 -#define INCLUDE_vTaskDelete 0 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 0 -#define INCLUDE_vTaskDelayUntil 0 -#define INCLUDE_vTaskDelay 1 - - - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/CORTEX_LM3S102_KEIL/ParTest/ParTest.c b/Demo/CORTEX_LM3S102_KEIL/ParTest/ParTest.c deleted file mode 100644 index e344c1b7b..000000000 --- a/Demo/CORTEX_LM3S102_KEIL/ParTest/ParTest.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/*----------------------------------------------------------- - * Simple parallel port IO routines. - *-----------------------------------------------------------*/ - -/* -*/ - - -#include "FreeRTOS.h" -#include "Task.h" -#include "partest.h" - -#include "pdc.h" - -#define partstPINS (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 Z | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7) - -#define partstALL_OUTPUTS_OFF ( ( unsigned portCHAR ) 0x00 ) -#define partstMAX_OUTPUT_LED ( ( unsigned portCHAR ) 8 ) - -static volatile unsigned portCHAR ucOutputValue = partstALL_OUTPUTS_OFF; - -void vParTestInitialise( void ) -{ - PDCInit(); - PDCWrite( PDC_LED, ucOutputValue ); -} -/*-----------------------------------------------------------*/ - -void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) -{ -unsigned portCHAR ucBit = ( unsigned portCHAR ) 1; - - vTaskSuspendAll(); - { - if( uxLED < partstMAX_OUTPUT_LED ) - { - ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED; - - if( xValue == pdFALSE ) - { - ucBit ^= ( unsigned portCHAR ) 0xff; - ucOutputValue &= ucBit; - } - else - { - ucOutputValue |= ucBit; - } - - PDCWrite( PDC_LED, ucOutputValue ); - } - } - xTaskResumeAll(); -} -/*-----------------------------------------------------------*/ - -void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) -{ -unsigned portCHAR ucBit; - - vTaskSuspendAll(); - { - if( uxLED < partstMAX_OUTPUT_LED ) - { - ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED; - - if( ucOutputValue & ucBit ) - { - ucOutputValue &= ~ucBit; - } - else - { - ucOutputValue |= ucBit; - } - - PDCWrite( PDC_LED, ucOutputValue ); - } - } - xTaskResumeAll(); -} - diff --git a/Demo/CORTEX_LM3S102_KEIL/include/pdc.c b/Demo/CORTEX_LM3S102_KEIL/include/pdc.c deleted file mode 100644 index 9e40fc925..000000000 --- a/Demo/CORTEX_LM3S102_KEIL/include/pdc.c +++ /dev/null @@ -1,118 +0,0 @@ -//***************************************************************************** -// -// pdc.c - Driver for the Peripheral Device Controller (PDC) on the Stellaris -// development board. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -//***************************************************************************** - -#include "LM3Sxxx.h" -#include "pdc.h" - -//***************************************************************************** -// -//! Initializes the connection to the PDC. -//! -//! This function will enable clocking to the SSI and GPIO A modules, configure -//! the GPIO pins to be used for an SSI interface, and it will configure the -//! SSI as a 1Mb master device, operating in MOTO mode. It will also enable -//! the SSI module, and will enable the chip select for the PDC on the -//! Stellaris development board. -//! -//! This function is contained in utils/pdc.c, with -//! utils/pdc.h containing the API definition for use by applications. -//! -//! \return None. -// -//***************************************************************************** -void -PDCInit(void) -{ - // - // Enable the peripherals used to drive the PDC. - // - SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI); - SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); - - // - // Configure the appropriate pins to be SSI instead of GPIO. - // - GPIODirModeSet(GPIO_PORTA_BASE, SSI_CLK | SSI_TX | SSI_RX, - GPIO_DIR_MODE_HW); - GPIODirModeSet(GPIO_PORTA_BASE, SSI_CS, GPIO_DIR_MODE_OUT); - GPIOPadConfigSet(GPIO_PORTA_BASE, SSI_CLK, GPIO_STRENGTH_4MA, - GPIO_PIN_TYPE_STD_WPU); - - // - // Configure the SSI port. - // - SSIConfig(SSI_BASE, SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 1000000, 8); - SSIEnable(SSI_BASE); - - // - // Reset the PDC SSI state machine. The chip select needs to be held low - // for 100ns; the procedure call overhead more than accounts for this time. - // - GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, 0); - GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, PDC_CS); -} - -//***************************************************************************** -// -//! Write a PDC register. -//! -//! \param ucAddr specifies the PDC register to write. -//! \param ucData specifies the data to write. -//! -//! This function will perform the SSI transfers required to write a register -//! in the PDC on the Stellaris development board. -//! -//! This function is contained in utils/pdc.c, with -//! utils/pdc.h containing the API definition for use by applications. -//! -//! \return None. -// -//***************************************************************************** -void -PDCWrite(unsigned char ucAddr, unsigned char ucData) -{ - unsigned long ulTemp; - - // - // Send address and write command. - // - SSIDataPut(SSI_BASE, (ucAddr & 0x0F) | PDC_WR); - - // - // Write the data. - // - SSIDataPut(SSI_BASE, ucData); - - // - // Flush data read during address write. - // - SSIDataGet(SSI_BASE, &ulTemp); - - // - // Flush data read during data write. - // - SSIDataGet(SSI_BASE, &ulTemp); -} diff --git a/Demo/CORTEX_LM3S102_KEIL/include/pdc.h b/Demo/CORTEX_LM3S102_KEIL/include/pdc.h deleted file mode 100644 index e787cf937..000000000 --- a/Demo/CORTEX_LM3S102_KEIL/include/pdc.h +++ /dev/null @@ -1,122 +0,0 @@ -//***************************************************************************** -// -// pdc.h - Stellaris development board Peripheral Device Controller definitions -// and prototypes. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -//***************************************************************************** - -#ifndef __PDC_H__ -#define __PDC_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The registers within the peripheral device controller. -// -//***************************************************************************** -#define PDC_VER 0x0 // Version register -#define PDC_CSR 0x1 // Command/Status register -#define PDC_DSW 0x4 // DIP Switch register -#define PDC_LED 0x5 // LED register -#define PDC_LCD_CSR 0x6 // LCD Command/Status register -#define PDC_LCD_RAM 0x7 // LCD RAM register -#define PDC_GPXDAT 0x8 // GPIO X Data register -#define PDC_GPXDIR 0x9 // GPIO X Direction register -#define PDC_GPYDAT 0xA // GPIO Y Data register -#define PDC_GPYDIR 0xB // GPIO Y Direction register -#define PDC_GPZDAT 0xC // GPIO Z Data register -#define PDC_GPZDIR 0xD // GPIO Z Direction register - -//***************************************************************************** -// -// Flags indicating a read or write to the peripheral device controller. -// -//***************************************************************************** -#define PDC_RD 0x80 // PDC read command -#define PDC_WR 0x00 // PDC write command - -//***************************************************************************** -// -// LCD panel (Crystalfontz CFAH1602B) commands, RS = 0 -// -//***************************************************************************** -#define LCD_CLEAR 0x01 // Clear display (0 fill DDRAM). -#define LCD_HOME 0x02 // Cursor home. -#define LCD_MODE 0x04 // Set entry mode (cursor dir) -#define LCD_ON 0x08 // Set display, cursor, blinking - // on/off -#define LCD_CUR 0x10 // Cursor, display shift -#define LCD_IF 0x20 // Set interface data length, - // lines, font -#define LCD_CGADDR 0x40 // Set CGRAM AC address -#define LCD_DDADDR 0x80 // Set DDRAM AC address - -//***************************************************************************** -// -// LCD Status bit -// -//***************************************************************************** -#define LCD_B_BUSY 0x80 // Busy flag. - -//***************************************************************************** -// -// The GPIO port A pin numbers for the various SSI signals. -// -//***************************************************************************** -#define SSI_CS GPIO_PIN_3 -#define PDC_CS GPIO_PIN_3 -#define SSI_CLK GPIO_PIN_2 -#define SSI_TX GPIO_PIN_5 -#define SSI_RX GPIO_PIN_4 - -//***************************************************************************** -// -// Function Prototypes -// -//***************************************************************************** -extern void PDCInit(void); -extern unsigned char PDCRead(unsigned char ucAddr); -extern void PDCWrite(unsigned char ucAddr, unsigned char ucData); -extern unsigned char PDCDIPRead(void); -extern void PDCLEDWrite(unsigned char ucLED); -extern unsigned char PDCLEDRead(void); -extern void PDCLCDInit(void); -extern void PDCLCDBacklightOn(void); -extern void PDCLCDBacklightOff(void); -extern void PDCLCDClear(void); -extern void PDCLCDCreateChar(unsigned char ucChar, unsigned char *pucData); -extern void PDCLCDSetPos(unsigned char ucX, unsigned char ucY); -extern void PDCLCDWrite(const char *pcStr, unsigned long ulCount); -extern unsigned char PDCGPIODirRead(unsigned char ucIdx); -extern void PDCGPIODirWrite(unsigned char ucIdx, unsigned char ucValue); -extern unsigned char PDCGPIORead(unsigned char ucIdx); -extern void PDCGPIOWrite(unsigned char ucIdx, unsigned char ucValue); - -#ifdef __cplusplus -} -#endif - -#endif // __PDC_H__ diff --git a/Demo/CORTEX_LM3S102_KEIL/init/Startup.s b/Demo/CORTEX_LM3S102_KEIL/init/Startup.s deleted file mode 100644 index c58ab3d14..000000000 --- a/Demo/CORTEX_LM3S102_KEIL/init/Startup.s +++ /dev/null @@ -1,162 +0,0 @@ -;/*****************************************************************************/ -;/* STARTUP.S: Startup file for Luminary Micro LM3Sxxx */ -;/*****************************************************************************/ -;/* <<< Use Configuration Wizard in Context Menu >>> */ -;/*****************************************************************************/ -;/* This file is part of the uVision/ARM development tools. */ -;/* Copyright (c) 2005-2006 Keil Software. All rights reserved. */ -;/* This software may only be used under the terms of a valid, current, */ -;/* end user licence from KEIL for a compatible version of KEIL software */ -;/* development tools. Nothing else gives you the right to use this software. */ -;/*****************************************************************************/ - - -;/* -; * The STARTUP.S code is executed after CPU Reset. -; */ - - -;// Stack Configuration -;// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -;// - -Stack_Size EQU 51 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size - - -;// Heap Configuration -;// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -;// - -Heap_Size EQU 0x00000000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -Heap_Mem SPACE Heap_Size - - -; System Control Register Addresses -SYSCTL_BASE EQU 0x400FE000 ; System Control Base Address -PBORCTL_OFS EQU 0x0030 ; Power-On & Brown-Out Reset Control -LDOPC_OFS EQU 0x0034 ; LDO Power -SRCR0_OFS EQU 0x0040 ; Software Reset Control 0 -SRCR1_OFS EQU 0x0044 ; Software Reset Control 1 -SRCR2_OFS EQU 0x0048 ; Software Reset Control 2 -RCC_OFS EQU 0x0060 ; Run-Mode Clock Control -RCGC0_OFS EQU 0x0100 ; Run-Mode Clock Gating Control 0 -RCGC1_OFS EQU 0x0104 ; Run-Mode Clock Gating Control 1 -RCGC2_OFS EQU 0x0108 ; Run-Mode Clock Gating Control 2 -SCGC0_OFS EQU 0x0110 ; Sleep-Mode Clock Gating Control 0 -SCGC1_OFS EQU 0x0114 ; Sleep-Mode Clock Gating Control 1 -SCGC2_OFS EQU 0x0118 ; Sleep-Mode Clock Gating Control 2 -DCGC0_OFS EQU 0x0120 ; Deep-Sleep-Mode Clock Gating Control 0 -DCGC1_OFS EQU 0x0124 ; Deep-Sleep-Mode Clock Gating Control 1 -DCGC2_OFS EQU 0x0128 ; Deep-Sleep-Mode Clock Gating Control 2 - - - PRESERVE8 - - -; Area Definition and Entry Point -; Startup Code must be linked first at Address 0. - - AREA RESET, CODE, READONLY - THUMB - - IMPORT xPortPendSVHandler - IMPORT xPortSysTickHandler - IMPORT vUART_ISR - -; Vector Table -Vectors DCD Stack_Mem + Stack_Size ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NmiSR ; NMI Handler - DCD DefaultISR ; Hard Fault Handler - DCD DefaultISR ; MPU Fault Handler - DCD DefaultISR ; Bus Fault Handler - DCD DefaultISR ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; SVCall Handler - DCD DefaultISR ; Debug Monitor Handler - DCD 0 ; Reserved - DCD xPortPendSVHandler ; PendSV Handler - DCD xPortSysTickHandler ; SysTick Handler - DCD DefaultISR ; GPIO Port A Handler - DCD DefaultISR ; GPIO Port B Handler - DCD DefaultISR ; GPIO Port C Handler - DCD DefaultISR ; GPIO Port D Handler - DCD DefaultISR ; GPIO Port E Handler - DCD vUART_ISR ; UART0 Rx/Tx Handler - DCD DefaultISR ; UART1 Rx/Tx Handler - DCD DefaultISR ; SSI Rx/Tx Handler - DCD DefaultISR ; I2C Master/Slave Handler - DCD DefaultISR ; PWM Fault Handler - DCD DefaultISR ; PWM Generator 0 Handler - DCD DefaultISR ; PWM Generator 1 Handler - DCD DefaultISR ; PWM Generator 2 Handler - DCD DefaultISR ; Quadrature Encoder Handler - DCD DefaultISR ; ADC Sequence 0 Handler - DCD DefaultISR ; ADC Sequence 1 Handler - DCD DefaultISR ; ADC Sequence 2 Handler - DCD DefaultISR ; ADC Sequence 3 Handler - DCD DefaultISR ; Watchdog Timer Handler - DCD DefaultISR ; Timer 0 Subtimer A Handler - DCD DefaultISR ; Timer 0 Subtimer B Handler - DCD DefaultISR ; Timer 1 Subtimer A Handler - DCD DefaultISR ; Timer 1 Subtimer B Handler - DCD DefaultISR ; Timer 2 Subtimer A Handler - DCD DefaultISR ; Timer 2 Subtimer B Handler - DCD DefaultISR ; Analog Comparator 0 Handler - DCD DefaultISR ; Analog Comparator 1 Handler - DCD DefaultISR ; Analog Comparator 2 Handler - DCD DefaultISR ; System Control Handler - DCD DefaultISR ; Flash Control Handler - -; Dummy Handlers are implemented as infinite loops which can be modified. - -NmiSR B NmiSR -FaultISR B FaultISR - EXPORT FaultISR -DefaultISR B DefaultISR - - -; Reset Handler - - EXPORT Reset_Handler -Reset_Handler - -; Enable Clock Gating for Peripherals -; LDR R0, =SYSCTL_BASE ; System Control Base Address -; MVN R1, #0 ; Value 0xFFFFFFFF -; STR R1, [R0,#RCGC0_OFS] ; Run-Mode Clock Gating Ctrl 0 -; STR R1, [R0,#RCGC1_OFS] ; Run-Mode Clock Gating Ctrl 1 -; STR R1, [R0,#RCGC2_OFS] ; Run-Mode Clock Gating Ctrl 2 - -; Enter the C code - - IMPORT __main - LDR R0, =__main - BX R0 - - -; User Initial Stack & Heap - AREA |.text|, CODE, READONLY - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - - END diff --git a/Demo/CORTEX_LM3S102_KEIL/main.c b/Demo/CORTEX_LM3S102_KEIL/main.c deleted file mode 100644 index a43768c20..000000000 --- a/Demo/CORTEX_LM3S102_KEIL/main.c +++ /dev/null @@ -1,599 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * This demo application creates six co-routines and two tasks (three including - * the idle task). The co-routines execute as part of the idle task hook. - * - * Five of the created co-routines are the standard 'co-routine flash' - * co-routines contained within the Demo/Common/Minimal/crflash.c file and - * documented on the FreeRTOS.org WEB site. - * - * The 'LCD Task' rotates a string on the LCD, delaying between each character - * as necessitated by the slow interface, and delaying between each string just - * long enough to enable the text to be read. - * - * The sixth co-routine and final task control the transmission and reception - * of a string to UART 0. The co-routine periodically sends the first - * character of the string to the UART, with the UART's TxEnd interrupt being - * used to transmit the remaining characters. The UART's RxEnd interrupt - * receives the characters and places them on a queue to be processed by the - * 'COMs Rx' task. An error is latched should an unexpected character be - * received, or any character be received out of sequence. - * - * A loopback connector is required to ensure that each character transmitted - * on the UART is also received on the same UART. For test purposes the UART - * FIFO's are not utalised in order to maximise the interrupt overhead. Also - * a pseudo random interval is used between the start of each transmission in - * order that the resultant interrupts are more randomly distributed and - * therefore more likely to highlight any problems. - * - * The flash co-routines control LED's zero to four. LED five is toggled each - * time the string is transmitted on the UART. LED six is toggled each time - * the string is CORRECTLY received on the UART. LED seven is latched on should - * an error be detected in any task or co-routine. - * - * In addition the idle task makes repetative calls to - * prvSetAndCheckRegisters(). This simply loads the general purpose registers - * with a known value, then checks each register to ensure the held value is - * still correct. As a low priority task this checking routine is likely to - * get repeatedly swapped in and out. A register being found to contain an - * incorrect value is therefore indicative of an error in the task switching - * mechansim. - * - */ - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" -#include "croutine.h" - -/* Demo application include files. */ -#include "partest.h" -#include "crflash.h" - -/* Library include files. */ -#include "LM3Sxxx.h" -#include "pdc.h" - -/* The time to delay between writing each character to the LCD. */ -#define mainCHAR_WRITE_DELAY ( 2 / portTICK_RATE_MS ) - -/* The time to delay between writing each string to the LCD. */ -#define mainSTRING_WRITE_DELAY ( 400 / portTICK_RATE_MS ) - -/* The number of flash co-routines to create. */ -#define mainNUM_FLASH_CO_ROUTINES ( 5 ) - -/* The length of the queue used to pass received characters to the Comms Rx -task. */ -#define mainRX_QUEUE_LEN ( 5 ) - -/* The priority of the co-routine used to initiate the transmission of the -string on UART 0. */ -#define mainTX_CO_ROUTINE_PRIORITY ( 1 ) - -/* Only one co-routine is created so its index is not important. */ -#define mainTX_CO_ROUTINE_INDEX ( 0 ) - -/* The time between transmissions of the string on UART 0. This is pseudo -random in order to generate a bit or randomness to when the interrupts occur.*/ -#define mainMIN_TX_DELAY ( 40 / portTICK_RATE_MS ) -#define mainMAX_TX_DELAY ( ( portTickType ) 0x7f ) -#define mainOFFSET_TIME ( ( portTickType ) 3 ) - -/* The time the Comms Rx task should wait to receive a character. This should -be slightly longer than the time between transmissions. If we do not receive -a character after this time then there must be an error in the transmission or -the timing of the transmission. */ -#define mainCOMMS_RX_DELAY ( mainMAX_TX_DELAY + 20 ) - -/* The task priorites. */ -#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY ) -#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) - -/* The LED's toggled by the various tasks. */ -#define mainCOMMS_FAIL_LED ( 7 ) -#define mainCOMMS_RX_LED ( 6 ) -#define mainCOMMS_TX_LED ( 5 ) - -/* The baud rate used by the UART comms tasks/co-routine. */ -#define mainBAUD_RATE ( 57600 ) - -/* FIFO setting for the UART. The FIFO is not used to create a better test. */ -#define mainFIFO_SET ( 0x10 ) - -/* The string that is transmitted on the UART contains sequentially the -characters from mainFIRST_TX_CHAR to mainLAST_TX_CHAR. */ -#define mainFIRST_TX_CHAR '0' -#define mainLAST_TX_CHAR 'z' - -/* Just used to walk through the program memory in order that some random data -can be generated. */ -#define mainTOTAL_PROGRAM_MEMORY ( ( unsigned portLONG * ) ( 8 * 1024 ) ) -#define mainFIRST_PROGRAM_BYTES ( ( unsigned portLONG * ) 4 ) - -/*-----------------------------------------------------------*/ - -/* - * The task that rotates text on the LCD. - */ -static void vLCDTask( void * pvParameters ); - -/* - * The task that receives the characters from UART 0. - */ -static void vCommsRxTask( void * pvParameters ); - -/* - * The co-routine that periodically initiates the transmission of the string on - * the UART. - */ -static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); - -/* - * Writes a string the the LCD. - */ -static void prvWriteString( const portCHAR *pcString ); - -/* - * Initialisation routine for the UART. - */ -static void vSerialInit( void ); - -/* - * Thread safe write to the PDC. - */ -static void prvPDCWrite( portCHAR cAddress, portCHAR cData ); - -/* - * Function to simply set a known value into the general purpose registers - * then read them back to ensure they remain set correctly. An incorrect value - * being indicative of an error in the task switching mechanism. - */ -void prvSetAndCheckRegisters( void ); - -/* - * Latch the LED that indicates that an error has occurred. - */ -void vSetErrorLED( void ); - -/* - * Sets up the PLL and ports used by the demo. - */ -static void prvSetupHardware( void ); - -/*-----------------------------------------------------------*/ - -/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines -defined within this file. */ -unsigned portBASE_TYPE uxErrorStatus = pdPASS; - -/* The next character to transmit. */ -static portCHAR cNextChar; - -/* The queue used to transmit characters from the interrupt to the Comms Rx -task. */ -static xQueueHandle xCommsQueue; - -/*-----------------------------------------------------------*/ - -int main( void ) -{ - /* Create the queue used to communicate between the UART ISR and the Comms - Rx task. */ - xCommsQueue = xQueueCreate( mainRX_QUEUE_LEN, sizeof( portCHAR ) ); - - /* Setup the ports used by the demo and the clock. */ - prvSetupHardware(); - - /* Create the co-routines that flash the LED's. */ - vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES ); - - /* Create the co-routine that initiates the transmission of characters - on the UART. */ - xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX ); - - /* Create the LCD and Comms Rx tasks. */ - xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL ); - xTaskCreate( vCommsRxTask, "CMS", configMINIMAL_STACK_SIZE, NULL, mainCOMMS_RX_TASK_PRIORITY, NULL ); - - /* Start the scheduler running the tasks and co-routines just created. */ - vTaskStartScheduler(); - - /* Should not get here unless we did not have enough memory to start the - scheduler. */ - for( ;; ); -} -/*-----------------------------------------------------------*/ - -static void prvSetupHardware( void ) -{ - /* Setup the PLL. */ - SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); - - /* Initialise the hardware used to talk to the LCD, LED's and UART. */ - PDCInit(); - vParTestInitialise(); - vSerialInit(); -} -/*-----------------------------------------------------------*/ - -void vApplicationIdleHook( void ) -{ - /* The co-routines are executed in the idle task using the idle task - hook. */ - for( ;; ) - { - /* Schedule the co-routines. */ - vCoRoutineSchedule(); - - /* Run the register check function between each co-routine. */ - prvSetAndCheckRegisters(); - } -} -/*-----------------------------------------------------------*/ - -static void prvWriteString( const portCHAR *pcString ) -{ - /* Write pcString to the LED, pausing between each character. */ - prvPDCWrite(PDC_LCD_CSR, LCD_CLEAR); - while( *pcString ) - { - vTaskDelay( mainCHAR_WRITE_DELAY ); - prvPDCWrite( PDC_LCD_RAM, *pcString ); - pcString++; - } -} -/*-----------------------------------------------------------*/ - -void vLCDTask( void * pvParameters ) -{ -unsigned portBASE_TYPE uxIndex; -const unsigned portCHAR ucCFGData[] = { - 0x30, /* Set data bus to 8-bits. */ - 0x30, - 0x30, - 0x3C, /* Number of lines/font. */ - 0x08, /* Display off. */ - 0x01, /* Display clear. */ - 0x06, /* Entry mode [cursor dir][shift]. */ - 0x0C /* Display on [display on][curson on][blinking on]. */ - }; - -/* The strings that are written to the LCD. */ -const portCHAR *pcStringsToDisplay[] = { - "Stellaris", - "Demo", - "One", - "www.FreeRTOS.org", - "" - }; - - /* Configure the LCD. */ - uxIndex = 0; - while( uxIndex < sizeof( ucCFGData ) ) - { - prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] ); - uxIndex++; - vTaskDelay( mainCHAR_WRITE_DELAY ); - } - - /* Turn the LCD Backlight on. */ - prvPDCWrite( PDC_CSR, 0x01 ); - - /* Clear display. */ - vTaskDelay( mainCHAR_WRITE_DELAY ); - prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); - - uxIndex = 0; - for( ;; ) - { - /* Display the string on the LCD. */ - prvWriteString( pcStringsToDisplay[ uxIndex ] ); - - /* Move on to the next string - wrapping if necessary. */ - uxIndex++; - if( *( pcStringsToDisplay[ uxIndex ] ) == 0x00 ) - { - uxIndex = 0; - /* Longer pause on the last string to be sent. */ - vTaskDelay( mainSTRING_WRITE_DELAY * 2 ); - } - - /* Wait until it is time to move onto the next string. */ - vTaskDelay( mainSTRING_WRITE_DELAY ); - } -} -/*-----------------------------------------------------------*/ - -static void vCommsRxTask( void * pvParameters ) -{ -static portCHAR cRxedChar, cExpectedChar; - - /* Set the char we expect to receive to the start of the string. */ - cExpectedChar = mainFIRST_TX_CHAR; - - for( ;; ) - { - /* Wait for a character to be received. */ - xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY ); - - /* Was the character recived (if any) the expected character. */ - if( cRxedChar != cExpectedChar ) - { - /* Got an unexpected character. This can sometimes occur when - reseting the system using the debugger leaving characters already - in the UART regsters. */ - uxErrorStatus = pdFAIL; - - /* Resync by waiting for the end of the current string. */ - while( cRxedChar != mainLAST_TX_CHAR ) - { - while( !xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, portMAX_DELAY ) ); - } - - /* The next expected character is the start of the string again. */ - cExpectedChar = mainFIRST_TX_CHAR; - } - else - { - if( cExpectedChar == mainLAST_TX_CHAR ) - { - /* We have reached the end of the string - we now expect to - receive the first character in the string again. The LED is - toggled to indicate that the entire string was received without - error. */ - vParTestToggleLED( mainCOMMS_RX_LED ); - cExpectedChar = mainFIRST_TX_CHAR; - } - else - { - /* We got the expected character, we now expect to receive the - next character in the string. */ - cExpectedChar++; - } - } - } -} -/*-----------------------------------------------------------*/ - -static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) -{ -portTickType xDelayPeriod; -static unsigned portLONG *pulRandomBytes = mainFIRST_PROGRAM_BYTES; - - /* Co-routine MUST start with a call to crSTART. */ - crSTART( xHandle ); - - for(;;) - { - /* Was the previously transmitted string received correctly? */ - if( uxErrorStatus != pdPASS ) - { - /* An error was encountered so set the error LED. */ - vSetErrorLED(); - } - - /* The next character to Tx is the first in the string. */ - cNextChar = mainFIRST_TX_CHAR; - - UARTIntDisable( UART0_BASE, UART_INT_TX ); - { - /* Send the first character. */ - if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) - { - HWREG( UART0_BASE + UART_O_DR ) = cNextChar; - } - - /* Move the variable to the char to Tx on so the ISR transmits - the next character in the string once this one has completed. */ - cNextChar++; - } - UARTIntEnable(UART0_BASE, UART_INT_TX); - - /* Toggle the LED to show a new string is being transmitted. */ - vParTestToggleLED( mainCOMMS_TX_LED ); - - /* Delay before we start the string off again. A pseudo-random delay - is used as this will provide a better test. */ - xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes ); - - pulRandomBytes++; - if( pulRandomBytes > mainTOTAL_PROGRAM_MEMORY ) - { - pulRandomBytes = mainFIRST_PROGRAM_BYTES; - } - - /* Make sure we don't wait too long... */ - xDelayPeriod &= mainMAX_TX_DELAY; - - /* ...but we do want to wait. */ - if( xDelayPeriod < mainMIN_TX_DELAY ) - { - xDelayPeriod = mainMIN_TX_DELAY; - } - - /* Block for the random(ish) time. */ - crDELAY( xHandle, xDelayPeriod ); - } - - /* Co-routine MUST end with a call to crEND. */ - crEND(); -} -/*-----------------------------------------------------------*/ - -static void vSerialInit( void ) -{ - /* Enable the UART. GPIOA has already been initialised. */ - SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); - - /* Set GPIO A0 and A1 as peripheral function. They are used to output the - UART signals. */ - GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); - - /* Configure the UART for 8-N-1 operation. */ - UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); - - /* We dont want to use the fifo. This is for test purposes to generate - as many interrupts as possible. */ - HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; - - /* Enable both Rx and Tx interrupts. */ - HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX ); - IntEnable( INT_UART0 ); -} -/*-----------------------------------------------------------*/ - -void vUART_ISR(void) -{ -unsigned portLONG ulStatus; -portCHAR cRxedChar; -portBASE_TYPE xTaskWokenByPost = pdFALSE; - - /* What caused the interrupt. */ - ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); - - /* Clear the interrupt. */ - UARTIntClear( UART0_BASE, ulStatus ); - - /* Was an Rx interrpt pending? */ - if( ulStatus & UART_INT_RX ) - { - if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) ) - { - /* Get the char from the buffer and post it onto the queue of - Rxed chars. Posting the character should wake the task that is - blocked on the queue waiting for characters. */ - cRxedChar = ( portCHAR ) HWREG( UART0_BASE + UART_O_DR ); - xTaskWokenByPost = xQueueSendFromISR( xCommsQueue, &cRxedChar, xTaskWokenByPost ); - } - } - - /* Was a Tx interrupt pending? */ - if( ulStatus & UART_INT_TX ) - { - /* Send the next character in the string. We are not using the FIFO. */ - if( cNextChar <= mainLAST_TX_CHAR ) - { - if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) - { - HWREG( UART0_BASE + UART_O_DR ) = cNextChar; - } - cNextChar++; - } - } - - if( xTaskWokenByPost ) - { - /* If a task was woken by the character being received then we force - a context switch to occur in case the task is of higher priority than - the currently executing task (i.e. the task that this interrupt - interrupted.) */ - portEND_SWITCHING_ISR( xTaskWokenByPost ); - } -} -/*-----------------------------------------------------------*/ - -static void prvPDCWrite( portCHAR cAddress, portCHAR cData ) -{ - vTaskSuspendAll(); - { - PDCWrite( cAddress, cData ); - } - xTaskResumeAll(); -} -/*-----------------------------------------------------------*/ - -void vSetErrorLED( void ) -{ - vParTestSetLED( mainCOMMS_FAIL_LED, pdTRUE ); -} -/*-----------------------------------------------------------*/ - -__asm void prvSetAndCheckRegisters( void ) -{ - extern vSetErrorLED - - /* Fill the general purpose registers with known values. */ - mov r11, #10 - add r0, r11, #1 - add r1, r11, #2 - add r2, r11, #3 - add r3, r11, #4 - add r4, r11, #5 - add r5, r11, #6 - add r6, r11, #7 - add r7, r11, #8 - add r8, r11, #9 - add r9, r11, #10 - add r10, r11, #11 - add r12, r11, #12 - - /* Check the values are as expected. */ - cmp r11, #10 - bne set_error_led - cmp r0, #11 - bne set_error_led - cmp r1, #12 - bne set_error_led - cmp r2, #13 - bne set_error_led - cmp r3, #14 - bne set_error_led - cmp r4, #15 - bne set_error_led - cmp r5, #16 - bne set_error_led - cmp r6, #17 - bne set_error_led - cmp r7, #18 - bne set_error_led - cmp r8, #19 - bne set_error_led - cmp r9, #20 - bne set_error_led - cmp r10, #21 - bne set_error_led - cmp r12, #22 - bne set_error_led - bx lr - -set_error_led; - push {r14} - ldr r1, =vSetErrorLED - blx r1 - pop {r14} - bx lr; -} -/*-----------------------------------------------------------*/ diff --git a/Demo/CORTEX_LM3S102_Rowley/Demo1/FreeRTOSConfig.h b/Demo/CORTEX_LM3S102_Rowley/Demo1/FreeRTOSConfig.h deleted file mode 100644 index 51d644b1a..000000000 --- a/Demo/CORTEX_LM3S102_Rowley/Demo1/FreeRTOSConfig.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 1 -#define configUSE_TICK_HOOK 0 -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 ) -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 59 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1468 ) ) -#define configMAX_TASK_NAME_LEN ( 3 ) -#define configUSE_TRACE_FACILITY 0 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 0 -#define configUSE_CO_ROUTINES 1 - -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 ) -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 0 -#define INCLUDE_uxTaskPriorityGet 0 -#define INCLUDE_vTaskDelete 0 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 0 -#define INCLUDE_vTaskDelayUntil 0 -#define INCLUDE_vTaskDelay 1 - - - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/CORTEX_LM3S102_Rowley/Demo1/ParTest.c b/Demo/CORTEX_LM3S102_Rowley/Demo1/ParTest.c deleted file mode 100644 index e344c1b7b..000000000 --- a/Demo/CORTEX_LM3S102_Rowley/Demo1/ParTest.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/*----------------------------------------------------------- - * Simple parallel port IO routines. - *-----------------------------------------------------------*/ - -/* -*/ - - -#include "FreeRTOS.h" -#include "Task.h" -#include "partest.h" - -#include "pdc.h" - -#define partstPINS (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 Z | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7) - -#define partstALL_OUTPUTS_OFF ( ( unsigned portCHAR ) 0x00 ) -#define partstMAX_OUTPUT_LED ( ( unsigned portCHAR ) 8 ) - -static volatile unsigned portCHAR ucOutputValue = partstALL_OUTPUTS_OFF; - -void vParTestInitialise( void ) -{ - PDCInit(); - PDCWrite( PDC_LED, ucOutputValue ); -} -/*-----------------------------------------------------------*/ - -void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) -{ -unsigned portCHAR ucBit = ( unsigned portCHAR ) 1; - - vTaskSuspendAll(); - { - if( uxLED < partstMAX_OUTPUT_LED ) - { - ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED; - - if( xValue == pdFALSE ) - { - ucBit ^= ( unsigned portCHAR ) 0xff; - ucOutputValue &= ucBit; - } - else - { - ucOutputValue |= ucBit; - } - - PDCWrite( PDC_LED, ucOutputValue ); - } - } - xTaskResumeAll(); -} -/*-----------------------------------------------------------*/ - -void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) -{ -unsigned portCHAR ucBit; - - vTaskSuspendAll(); - { - if( uxLED < partstMAX_OUTPUT_LED ) - { - ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED; - - if( ucOutputValue & ucBit ) - { - ucOutputValue &= ~ucBit; - } - else - { - ucOutputValue |= ucBit; - } - - PDCWrite( PDC_LED, ucOutputValue ); - } - } - xTaskResumeAll(); -} - diff --git a/Demo/CORTEX_LM3S102_Rowley/Demo1/main.c b/Demo/CORTEX_LM3S102_Rowley/Demo1/main.c deleted file mode 100644 index 228a0492e..000000000 --- a/Demo/CORTEX_LM3S102_Rowley/Demo1/main.c +++ /dev/null @@ -1,617 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * This demo application creates six co-routines and two tasks (three including - * the idle task). The co-routines execute as part of the idle task hook. - * - * Five of the created co-routines are the standard 'co-routine flash' - * co-routines contained within the Demo/Common/Minimal/crflash.c file and - * documented on the FreeRTOS.org WEB site. - * - * The 'LCD Task' rotates a string on the LCD, delaying between each character - * as necessitated by the slow interface, and delaying between each string just - * long enough to enable the text to be read. - * - * The sixth co-routine and final task control the transmission and reception - * of a string to UART 0. The co-routine periodically sends the first - * character of the string to the UART, with the UART's TxEnd interrupt being - * used to transmit the remaining characters. The UART's RxEnd interrupt - * receives the characters and places them on a queue to be processed by the - * 'COMs Rx' task. An error is latched should an unexpected character be - * received, or any character be received out of sequence. - * - * A loopback connector is required to ensure that each character transmitted - * on the UART is also received on the same UART. For test purposes the UART - * FIFO's are not utalised in order to maximise the interrupt overhead. Also - * a pseudo random interval is used between the start of each transmission in - * order that the resultant interrupts are more randomly distributed and - * therefore more likely to highlight any problems. - * - * The flash co-routines control LED's zero to four. LED five is toggled each - * time the string is transmitted on the UART. LED six is toggled each time - * the string is CORRECTLY received on the UART. LED seven is latched on should - * an error be detected in any task or co-routine. - * - * In addition the idle task makes repetative calls to - * prvSetAndCheckRegisters(). This simply loads the general purpose registers - * with a known value, then checks each register to ensure the held value is - * still correct. As a low priority task this checking routine is likely to - * get repeatedly swapped in and out. A register being found to contain an - * incorrect value is therefore indicative of an error in the task switching - * mechansim. - * - */ - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" -#include "croutine.h" - -/* Demo application include files. */ -#include "partest.h" -#include "crflash.h" - -/* Library include files. */ -#include "DriverLib.h" - -/* The time to delay between writing each character to the LCD. */ -#define mainCHAR_WRITE_DELAY ( 2 / portTICK_RATE_MS ) - -/* The time to delay between writing each string to the LCD. */ -#define mainSTRING_WRITE_DELAY ( 400 / portTICK_RATE_MS ) - -/* The number of flash co-routines to create. */ -#define mainNUM_FLASH_CO_ROUTINES ( 5 ) - -/* The length of the queue used to pass received characters to the Comms Rx -task. */ -#define mainRX_QUEUE_LEN ( 5 ) - -/* The priority of the co-routine used to initiate the transmission of the -string on UART 0. */ -#define mainTX_CO_ROUTINE_PRIORITY ( 1 ) - -/* Only one co-routine is created so its index is not important. */ -#define mainTX_CO_ROUTINE_INDEX ( 0 ) - -/* The time between transmissions of the string on UART 0. This is pseudo -random in order to generate a bit or randomness to when the interrupts occur.*/ -#define mainMIN_TX_DELAY ( 40 / portTICK_RATE_MS ) -#define mainMAX_TX_DELAY ( ( portTickType ) 0x7f ) -#define mainOFFSET_TIME ( ( portTickType ) 3 ) - -/* The time the Comms Rx task should wait to receive a character. This should -be slightly longer than the time between transmissions. If we do not receive -a character after this time then there must be an error in the transmission or -the timing of the transmission. */ -#define mainCOMMS_RX_DELAY ( mainMAX_TX_DELAY + 20 ) - -/* The task priorites. */ -#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY ) -#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) - -/* The LED's toggled by the various tasks. */ -#define mainCOMMS_FAIL_LED ( 7 ) -#define mainCOMMS_RX_LED ( 6 ) -#define mainCOMMS_TX_LED ( 5 ) - -/* The baud rate used by the UART comms tasks/co-routine. */ -#define mainBAUD_RATE ( 57600 ) - -/* FIFO setting for the UART. The FIFO is not used to create a better test. */ -#define mainFIFO_SET ( 0x10 ) - -/* The string that is transmitted on the UART contains sequentially the -characters from mainFIRST_TX_CHAR to mainLAST_TX_CHAR. */ -#define mainFIRST_TX_CHAR '0' -#define mainLAST_TX_CHAR 'z' - -/* Just used to walk through the program memory in order that some random data -can be generated. */ -#define mainTOTAL_PROGRAM_MEMORY ( ( unsigned portLONG * ) ( 8 * 1024 ) ) -#define mainFIRST_PROGRAM_BYTES ( ( unsigned portLONG * ) 4 ) - -/* The error routine that is called if the driver library encounters an error. */ -#ifdef DEBUG -void -__error__(char *pcFilename, unsigned long ulLine) -{ -} -#endif - -/*-----------------------------------------------------------*/ - -/* - * The task that rotates text on the LCD. - */ -static void vLCDTask( void * pvParameters ); - -/* - * The task that receives the characters from UART 0. - */ -static void vCommsRxTask( void * pvParameters ); - -/* - * The co-routine that periodically initiates the transmission of the string on - * the UART. - */ -static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); - -/* - * Writes a string the the LCD. - */ -static void prvWriteString( const portCHAR *pcString ); - -/* - * Initialisation routine for the UART. - */ -static void vSerialInit( void ); - -/* - * Thread safe write to the PDC. - */ -static void prvPDCWrite( portCHAR cAddress, portCHAR cData ); - -/* - * Function to simply set a known value into the general purpose registers - * then read them back to ensure they remain set correctly. An incorrect value - * being indicative of an error in the task switching mechanism. - */ -void prvSetAndCheckRegisters( void ); - -/* - * Latch the LED that indicates that an error has occurred. - */ -void vSetErrorLED( void ); - -/* - * Sets up the PLL and ports used by the demo. - */ -static void prvSetupHardware( void ); - -/*-----------------------------------------------------------*/ - -/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines -defined within this file. */ -unsigned portBASE_TYPE uxErrorStatus = pdPASS; - -/* The next character to transmit. */ -static portCHAR cNextChar; - -/* The queue used to transmit characters from the interrupt to the Comms Rx -task. */ -static xQueueHandle xCommsQueue; - -/*-----------------------------------------------------------*/ - -int main( void ) -{ - /* Create the queue used to communicate between the UART ISR and the Comms - Rx task. */ - xCommsQueue = xQueueCreate( mainRX_QUEUE_LEN, sizeof( portCHAR ) ); - - /* Setup the ports used by the demo and the clock. */ - prvSetupHardware(); - - /* Create the co-routines that flash the LED's. */ - vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES ); - - /* Create the co-routine that initiates the transmission of characters - on the UART. */ - xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX ); - - /* Create the LCD and Comms Rx tasks. */ - xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL ); - xTaskCreate( vCommsRxTask, "CMS", configMINIMAL_STACK_SIZE, NULL, mainCOMMS_RX_TASK_PRIORITY, NULL ); - - /* Start the scheduler running the tasks and co-routines just created. */ - vTaskStartScheduler(); - - /* Should not get here unless we did not have enough memory to start the - scheduler. */ - for( ;; ); - return 0; -} -/*-----------------------------------------------------------*/ - -static void prvSetupHardware( void ) -{ - /* Setup the PLL. */ - SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); - - /* Initialise the hardware used to talk to the LCD, LED's and UART. */ - PDCInit(); - vParTestInitialise(); - vSerialInit(); -} -/*-----------------------------------------------------------*/ - -void vApplicationIdleHook( void ) -{ - /* The co-routines are executed in the idle task using the idle task - hook. */ - for( ;; ) - { - /* Schedule the co-routines. */ - vCoRoutineSchedule(); - - /* Run the register check function between each co-routine. */ - prvSetAndCheckRegisters(); - } -} -/*-----------------------------------------------------------*/ - -static void prvWriteString( const portCHAR *pcString ) -{ - /* Write pcString to the LED, pausing between each character. */ - prvPDCWrite(PDC_LCD_CSR, LCD_CLEAR); - while( *pcString ) - { - vTaskDelay( mainCHAR_WRITE_DELAY ); - prvPDCWrite( PDC_LCD_RAM, *pcString ); - pcString++; - } -} -/*-----------------------------------------------------------*/ - -void vLCDTask( void * pvParameters ) -{ -unsigned portBASE_TYPE uxIndex; -const unsigned portCHAR ucCFGData[] = { - 0x30, /* Set data bus to 8-bits. */ - 0x30, - 0x30, - 0x3C, /* Number of lines/font. */ - 0x08, /* Display off. */ - 0x01, /* Display clear. */ - 0x06, /* Entry mode [cursor dir][shift]. */ - 0x0C /* Display on [display on][curson on][blinking on]. */ - }; - -/* The strings that are written to the LCD. */ -const portCHAR *pcStringsToDisplay[] = { - "Stellaris", - "Demo", - "One", - "www.FreeRTOS.org", - "" - }; - - /* Configure the LCD. */ - uxIndex = 0; - while( uxIndex < sizeof( ucCFGData ) ) - { - prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] ); - uxIndex++; - vTaskDelay( mainCHAR_WRITE_DELAY ); - } - - /* Turn the LCD Backlight on. */ - prvPDCWrite( PDC_CSR, 0x01 ); - - /* Clear display. */ - vTaskDelay( mainCHAR_WRITE_DELAY ); - prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); - - uxIndex = 0; - for( ;; ) - { - /* Display the string on the LCD. */ - prvWriteString( pcStringsToDisplay[ uxIndex ] ); - - /* Move on to the next string - wrapping if necessary. */ - uxIndex++; - if( *( pcStringsToDisplay[ uxIndex ] ) == 0x00 ) - { - uxIndex = 0; - /* Longer pause on the last string to be sent. */ - vTaskDelay( mainSTRING_WRITE_DELAY * 2 ); - } - - /* Wait until it is time to move onto the next string. */ - vTaskDelay( mainSTRING_WRITE_DELAY ); - } -} -/*-----------------------------------------------------------*/ - -static void vCommsRxTask( void * pvParameters ) -{ -static portCHAR cRxedChar, cExpectedChar; - - /* Set the char we expect to receive to the start of the string. */ - cExpectedChar = mainFIRST_TX_CHAR; - - for( ;; ) - { - /* Wait for a character to be received. */ - xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY ); - - /* Was the character recived (if any) the expected character. */ - if( cRxedChar != cExpectedChar ) - { - /* Got an unexpected character. This can sometimes occur when - reseting the system using the debugger leaving characters already - in the UART regsters. */ - uxErrorStatus = pdFAIL; - - /* Resync by waiting for the end of the current string. */ - while( cRxedChar != mainLAST_TX_CHAR ) - { - while( !xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, portMAX_DELAY ) ); - } - - /* The next expected character is the start of the string again. */ - cExpectedChar = mainFIRST_TX_CHAR; - } - else - { - if( cExpectedChar == mainLAST_TX_CHAR ) - { - /* We have reached the end of the string - we now expect to - receive the first character in the string again. The LED is - toggled to indicate that the entire string was received without - error. */ - vParTestToggleLED( mainCOMMS_RX_LED ); - cExpectedChar = mainFIRST_TX_CHAR; - } - else - { - /* We got the expected character, we now expect to receive the - next character in the string. */ - cExpectedChar++; - } - } - } -} -/*-----------------------------------------------------------*/ - -static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) -{ -portTickType xDelayPeriod; -static unsigned portLONG *pulRandomBytes = mainFIRST_PROGRAM_BYTES; - - /* Co-routine MUST start with a call to crSTART. */ - crSTART( xHandle ); - - for(;;) - { - /* Was the previously transmitted string received correctly? */ - if( uxErrorStatus != pdPASS ) - { - /* An error was encountered so set the error LED. */ - vSetErrorLED(); - } - - /* The next character to Tx is the first in the string. */ - cNextChar = mainFIRST_TX_CHAR; - - UARTIntDisable( UART0_BASE, UART_INT_TX ); - { - /* Send the first character. */ - if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) - { - HWREG( UART0_BASE + UART_O_DR ) = cNextChar; - } - - /* Move the variable to the char to Tx on so the ISR transmits - the next character in the string once this one has completed. */ - cNextChar++; - } - UARTIntEnable(UART0_BASE, UART_INT_TX); - - /* Toggle the LED to show a new string is being transmitted. */ - vParTestToggleLED( mainCOMMS_TX_LED ); - - /* Delay before we start the string off again. A pseudo-random delay - is used as this will provide a better test. */ - xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes ); - - pulRandomBytes++; - if( pulRandomBytes > mainTOTAL_PROGRAM_MEMORY ) - { - pulRandomBytes = mainFIRST_PROGRAM_BYTES; - } - - /* Make sure we don't wait too long... */ - xDelayPeriod &= mainMAX_TX_DELAY; - - /* ...but we do want to wait. */ - if( xDelayPeriod < mainMIN_TX_DELAY ) - { - xDelayPeriod = mainMIN_TX_DELAY; - } - - /* Block for the random(ish) time. */ - crDELAY( xHandle, xDelayPeriod ); - } - - /* Co-routine MUST end with a call to crEND. */ - crEND(); -} -/*-----------------------------------------------------------*/ - -static void vSerialInit( void ) -{ - /* Enable the UART. GPIOA has already been initialised. */ - SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); - - /* Set GPIO A0 and A1 as peripheral function. They are used to output the - UART signals. */ - GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); - - /* Configure the UART for 8-N-1 operation. */ - UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); - - /* We dont want to use the fifo. This is for test purposes to generate - as many interrupts as possible. */ - HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; - - /* Enable both Rx and Tx interrupts. */ - HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX ); - IntEnable( INT_UART0 ); -} -/*-----------------------------------------------------------*/ - -void vUART_ISR(void) -{ -unsigned portLONG ulStatus; -portCHAR cRxedChar; -portBASE_TYPE xTaskWokenByPost = pdFALSE; - - /* What caused the interrupt. */ - ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); - - /* Clear the interrupt. */ - UARTIntClear( UART0_BASE, ulStatus ); - - /* Was an Rx interrpt pending? */ - if( ulStatus & UART_INT_RX ) - { - if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) ) - { - /* Get the char from the buffer and post it onto the queue of - Rxed chars. Posting the character should wake the task that is - blocked on the queue waiting for characters. */ - cRxedChar = ( portCHAR ) HWREG( UART0_BASE + UART_O_DR ); - xTaskWokenByPost = xQueueSendFromISR( xCommsQueue, &cRxedChar, xTaskWokenByPost ); - } - } - - /* Was a Tx interrupt pending? */ - if( ulStatus & UART_INT_TX ) - { - /* Send the next character in the string. We are not using the FIFO. */ - if( cNextChar <= mainLAST_TX_CHAR ) - { - if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) - { - HWREG( UART0_BASE + UART_O_DR ) = cNextChar; - } - cNextChar++; - } - } - - if( xTaskWokenByPost ) - { - /* If a task was woken by the character being received then we force - a context switch to occur in case the task is of higher priority than - the currently executing task (i.e. the task that this interrupt - interrupted.) */ - portEND_SWITCHING_ISR( xTaskWokenByPost ); - } -} -/*-----------------------------------------------------------*/ - -static void prvPDCWrite( portCHAR cAddress, portCHAR cData ) -{ - vTaskSuspendAll(); - { - PDCWrite( cAddress, cData ); - } - xTaskResumeAll(); -} -/*-----------------------------------------------------------*/ - -void vSetErrorLED( void ) -{ - vParTestSetLED( mainCOMMS_FAIL_LED, pdTRUE ); -} -/*-----------------------------------------------------------*/ - -void prvSetAndCheckRegisters( void ) -{ - /* Fill the general purpose registers with known values. */ - __asm volatile - ( - " mov r11, #10 \n" - " add r0, r11, #1 \n" - " add r1, r11, #2 \n" - " add r2, r11, #3 \n" - " add r3, r11, #4 \n" - " add r4, r11, #5 \n" - " add r5, r11, #6 \n" - " add r6, r11, #7 \n" - " add r7, r11, #8 \n" - " add r8, r11, #9 \n" - " add r9, r11, #10 \n" - " add r10, r11, #11 \n" - " add r12, r11, #12" - ); - - /* Check the values are as expected. */ - __asm volatile - ( - " cmp r11, #10 \n" - " bne set_error_led \n" - " cmp r0, #11 \n" - " bne set_error_led \n" - " cmp r1, #12 \n" - " bne set_error_led \n" - " cmp r2, #13 \n" - " bne set_error_led \n" - " cmp r3, #14 \n" - " bne set_error_led \n" - " cmp r4, #15 \n" - " bne set_error_led \n" - " cmp r5, #16 \n" - " bne set_error_led \n" - " cmp r6, #17 \n" - " bne set_error_led \n" - " cmp r7, #18 \n" - " bne set_error_led \n" - " cmp r8, #19 \n" - " bne set_error_led \n" - " cmp r9, #20 \n" - " bne set_error_led \n" - " cmp r10, #21 \n" - " bne set_error_led \n" - " cmp r12, #22 \n" - " bne set_error_led \n" - " bx lr" - ); - - __asm volatile - ( - "set_error_led: \n" - " push {r14} \n" - " ldr r1, vSetErrorLEDConst\n" - " blx r1 \n" - " pop {r14} \n" - " bx lr \n" - " \n" - " .align 2 \n" - "vSetErrorLEDConst: .word vSetErrorLED" - ); -} -/*-----------------------------------------------------------*/ diff --git a/Demo/CORTEX_LM3S102_Rowley/Demo1/vectors.s b/Demo/CORTEX_LM3S102_Rowley/Demo1/vectors.s deleted file mode 100644 index 2ff9827a2..000000000 --- a/Demo/CORTEX_LM3S102_Rowley/Demo1/vectors.s +++ /dev/null @@ -1,119 +0,0 @@ -/***************************************************************************** - * Copyright (c) 2006 Rowley Associates Limited. * - * * - * This file may be distributed under the terms of the License Agreement * - * provided with this software. * - * * - * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE * - * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * - *****************************************************************************/ - .section .vectors, "ax" - .code 16 - .align 0 - .global _vectors - - .extern xPortPendSVHandler - .extern xPortSysTickHandler - .extern vUART_ISR - -.macro DEFAULT_ISR_HANDLER name= - .thumb_func - .weak \name -\name: -1: b 1b /* endless loop */ -.endm - -_vectors: - .word __stack_end__ -#ifdef STARTUP_FROM_RESET - .word _start -#else - .word reset_wait -#endif /* STARTUP_FROM_RESET */ - .word NmiISR - .word FaultISR - .word 0 // Populate if using MemManage (MPU) - .word 0 // Populate if using Bus fault - .word 0 // Populate if using Usage fault - .word 0 // Reserved - .word 0 // Reserved - .word 0 // Reserved - .word 0 // Reserved - .word 0 - .word 0 // Populate if using a debug monitor - .word 0 // Reserved - .word xPortPendSVHandler // Populate if using pendable service request - .word xPortSysTickHandler - // External interrupts start her - .word GPIO_Port_A_ISR - .word GPIO_Port_B_ISR - .word GPIO_Port_C_ISR - .word GPIO_Port_D_ISR - .word GPIO_Port_E_ISR - .word vUART_ISR - .word UART1_ISR - .word SSI_ISR - .word I2C_ISR - .word PWM_Fault_ISR - .word PWM_Generator_0_ISR - .word PWM_Generator_1_ISR - .word PWM_Generator_2_ISR - .word QEI_ISR - .word ADC_Sequence_0_ISR - .word ADC_Sequence_1_ISR - .word ADC_Sequence_2_ISR - .word ADC_Sequence_3_ISR - .word Watchdog_timer_ISR - .word Timer0a_ISR - .word Timer0b_ISR - .word Timer1a_ISR - .word Timer1b_ISR - .word Timer2a_ISR - .word Timer2b_ISR - .word Analog_Comparator_0_ISR - .word Analog_Comparator_1_ISR - .word Analog_Comparator_2_ISR - .word System_Control_ISR - .word FLASH_Control_ISR - - .section .init, "ax" - .thumb_func - -DEFAULT_ISR_HANDLER NmiISR -DEFAULT_ISR_HANDLER FaultISR -DEFAULT_ISR_HANDLER SVCallISR -DEFAULT_ISR_HANDLER SysTickISR -DEFAULT_ISR_HANDLER GPIO_Port_A_ISR -DEFAULT_ISR_HANDLER GPIO_Port_B_ISR -DEFAULT_ISR_HANDLER GPIO_Port_C_ISR -DEFAULT_ISR_HANDLER GPIO_Port_D_ISR -DEFAULT_ISR_HANDLER GPIO_Port_E_ISR -DEFAULT_ISR_HANDLER UART0_ISR -DEFAULT_ISR_HANDLER UART1_ISR -DEFAULT_ISR_HANDLER SSI_ISR -DEFAULT_ISR_HANDLER I2C_ISR -DEFAULT_ISR_HANDLER PWM_Fault_ISR -DEFAULT_ISR_HANDLER PWM_Generator_0_ISR -DEFAULT_ISR_HANDLER PWM_Generator_1_ISR -DEFAULT_ISR_HANDLER PWM_Generator_2_ISR -DEFAULT_ISR_HANDLER QEI_ISR -DEFAULT_ISR_HANDLER ADC_Sequence_0_ISR -DEFAULT_ISR_HANDLER ADC_Sequence_1_ISR -DEFAULT_ISR_HANDLER ADC_Sequence_2_ISR -DEFAULT_ISR_HANDLER ADC_Sequence_3_ISR -DEFAULT_ISR_HANDLER Watchdog_timer_ISR -DEFAULT_ISR_HANDLER Timer0a_ISR -DEFAULT_ISR_HANDLER Timer0b_ISR -DEFAULT_ISR_HANDLER Timer1a_ISR -DEFAULT_ISR_HANDLER Timer1b_ISR -DEFAULT_ISR_HANDLER Timer2a_ISR -DEFAULT_ISR_HANDLER Timer2b_ISR -DEFAULT_ISR_HANDLER Analog_Comparator_0_ISR -DEFAULT_ISR_HANDLER Analog_Comparator_1_ISR -DEFAULT_ISR_HANDLER Analog_Comparator_2_ISR -DEFAULT_ISR_HANDLER System_Control_ISR -DEFAULT_ISR_HANDLER FLASH_Control_ISR - -#ifndef STARTUP_FROM_RESET -DEFAULT_ISR_HANDLER reset_wait -#endif /* STARTUP_FROM_RESET */ diff --git a/Demo/CORTEX_LM3S102_Rowley/Demo2/FreeRTOSConfig.h b/Demo/CORTEX_LM3S102_Rowley/Demo2/FreeRTOSConfig.h deleted file mode 100644 index b39c502a1..000000000 --- a/Demo/CORTEX_LM3S102_Rowley/Demo2/FreeRTOSConfig.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 1 -#define configUSE_TICK_HOOK 0 -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 ) -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 59 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1240 ) ) -#define configMAX_TASK_NAME_LEN ( 3 ) -#define configUSE_TRACE_FACILITY 0 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 0 -#define configUSE_CO_ROUTINES 1 - -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 ) -#define configMAX_CO_ROUTINE_PRIORITIES ( 3 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 0 -#define INCLUDE_uxTaskPriorityGet 0 -#define INCLUDE_vTaskDelete 0 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 0 -#define INCLUDE_vTaskDelayUntil 0 -#define INCLUDE_vTaskDelay 1 - - - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/CORTEX_LM3S102_Rowley/Demo2/ParTest.c b/Demo/CORTEX_LM3S102_Rowley/Demo2/ParTest.c deleted file mode 100644 index e344c1b7b..000000000 --- a/Demo/CORTEX_LM3S102_Rowley/Demo2/ParTest.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/*----------------------------------------------------------- - * Simple parallel port IO routines. - *-----------------------------------------------------------*/ - -/* -*/ - - -#include "FreeRTOS.h" -#include "Task.h" -#include "partest.h" - -#include "pdc.h" - -#define partstPINS (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 Z | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7) - -#define partstALL_OUTPUTS_OFF ( ( unsigned portCHAR ) 0x00 ) -#define partstMAX_OUTPUT_LED ( ( unsigned portCHAR ) 8 ) - -static volatile unsigned portCHAR ucOutputValue = partstALL_OUTPUTS_OFF; - -void vParTestInitialise( void ) -{ - PDCInit(); - PDCWrite( PDC_LED, ucOutputValue ); -} -/*-----------------------------------------------------------*/ - -void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) -{ -unsigned portCHAR ucBit = ( unsigned portCHAR ) 1; - - vTaskSuspendAll(); - { - if( uxLED < partstMAX_OUTPUT_LED ) - { - ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED; - - if( xValue == pdFALSE ) - { - ucBit ^= ( unsigned portCHAR ) 0xff; - ucOutputValue &= ucBit; - } - else - { - ucOutputValue |= ucBit; - } - - PDCWrite( PDC_LED, ucOutputValue ); - } - } - xTaskResumeAll(); -} -/*-----------------------------------------------------------*/ - -void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) -{ -unsigned portCHAR ucBit; - - vTaskSuspendAll(); - { - if( uxLED < partstMAX_OUTPUT_LED ) - { - ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED; - - if( ucOutputValue & ucBit ) - { - ucOutputValue &= ~ucBit; - } - else - { - ucOutputValue |= ucBit; - } - - PDCWrite( PDC_LED, ucOutputValue ); - } - } - xTaskResumeAll(); -} - diff --git a/Demo/CORTEX_LM3S102_Rowley/Demo2/main.c b/Demo/CORTEX_LM3S102_Rowley/Demo2/main.c deleted file mode 100644 index ed7afd0c1..000000000 --- a/Demo/CORTEX_LM3S102_Rowley/Demo2/main.c +++ /dev/null @@ -1,622 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * This demo application creates seven co-routines and one task (two including - * the idle task). The co-routines execute as part of the idle task hook. - * - * Five of the created co-routines are the standard 'co-routine flash' - * co-routines contained within the Demo/Common/Minimal/crflash.c file and - * documented on the FreeRTOS.org WEB site. - * - * The 'LCD Task' rotates a string on the LCD, delaying between each character - * as necessitated by the slow interface, and delaying between each string just - * long enough to enable the text to be read. - * - * The sixth co-routine controls the transmission of a string to UART 0. The - * co-routine periodically sends the first character of the string to the UART, - * with the UART's TxEnd interrupt being used to transmit the remaining - * characters. The UART's RxEnd interrupt receives the characters and places - * them on a queue to be processed by the seventh and final co-routine. An - * error is latched should an unexpected character be received, or any - * character be received out of sequence. - * - * A loopback connector is required to ensure that each character transmitted - * on the UART is also received on the same UART. For test purposes the UART - * FIFO's are not utalised in order to maximise the interrupt overhead. Also - * a pseudo random interval is used between the start of each transmission in - * order that the resultant interrupts are more randomly distributed and - * therefore more likely to highlight any problems. - * - * The flash co-routines control LED's zero to four. LED five is toggled each - * time the string is transmitted on the UART. LED six is toggled each time - * the string is CORRECTLY received on the UART. LED seven is latched on should - * an error be detected in any task or co-routine. - * - * In addition the idle task makes repetative calls to - * prvSetAndCheckRegisters(). This simply loads the general purpose registers - * with a known value, then checks each register to ensure the held value is - * still correct. As a low priority task this checking routine is likely to - * get repeatedly swapped in and out. A register being found to contain an - * incorrect value is therefore indicative of an error in the task switching - * mechansim. - * - */ - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" -#include "croutine.h" - -/* Demo application include files. */ -#include "partest.h" -#include "crflash.h" - -/* Library include files. */ -#include "DriverLib.h" - -/* The time to delay between writing each character to the LCD. */ -#define mainCHAR_WRITE_DELAY ( 2 / portTICK_RATE_MS ) - -/* The time to delay between writing each string to the LCD. */ -#define mainSTRING_WRITE_DELAY ( 400 / portTICK_RATE_MS ) - -/* The number of flash co-routines to create. */ -#define mainNUM_FLASH_CO_ROUTINES ( 5 ) - -/* The length of the queue used to pass received characters to the Comms Rx -task. */ -#define mainRX_QUEUE_LEN ( 5 ) - -/* The priority of the co-routine used to initiate the transmission of the -string on UART 0. */ -#define mainTX_CO_ROUTINE_PRIORITY ( 1 ) - -/* The priority of the co-routine used to receive characters from the UART. */ -#define mainRX_CO_ROUTINE_PRIORITY ( 2 ) - -/* Only one co-routine is created so its index is not important. */ -#define mainTX_CO_ROUTINE_INDEX ( 0 ) -#define mainRX_CO_ROUTINE_INDEX ( 0 ) - -/* The time between transmissions of the string on UART 0. This is pseudo -random in order to generate a bit or randomness to when the interrupts occur.*/ -#define mainMIN_TX_DELAY ( 40 / portTICK_RATE_MS ) -#define mainMAX_TX_DELAY ( ( portTickType ) 0x7f ) -#define mainOFFSET_TIME ( ( portTickType ) 3 ) - -/* The time the Comms Rx task should wait to receive a character. This should -be slightly longer than the time between transmissions. If we do not receive -a character after this time then there must be an error in the transmission or -the timing of the transmission. */ -#define mainCOMMS_RX_DELAY ( mainMAX_TX_DELAY + 20 ) - -/* The task priorites. */ -#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY ) -#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) - -/* The LED's toggled by the various tasks. */ -#define mainCOMMS_FAIL_LED ( 7 ) -#define mainCOMMS_RX_LED ( 6 ) -#define mainCOMMS_TX_LED ( 5 ) - -/* The baud rate used by the UART comms tasks/co-routine. */ -#define mainBAUD_RATE ( 57600 ) - -/* FIFO setting for the UART. The FIFO is not used to create a better test. */ -#define mainFIFO_SET ( 0x10 ) - -/* The string that is transmitted on the UART contains sequentially the -characters from mainFIRST_TX_CHAR to mainLAST_TX_CHAR. */ -#define mainFIRST_TX_CHAR '0' -#define mainLAST_TX_CHAR 'z' - -/* Just used to walk through the program memory in order that some random data -can be generated. */ -#define mainTOTAL_PROGRAM_MEMORY ( ( unsigned portLONG * ) ( 8 * 1024 ) ) -#define mainFIRST_PROGRAM_BYTES ( ( unsigned portLONG * ) 4 ) - -/* The error routine that is called if the driver library encounters an error. */ -#ifdef DEBUG -void -__error__(char *pcFilename, unsigned long ulLine) -{ -} -#endif - -/*-----------------------------------------------------------*/ - -/* - * The task that rotates text on the LCD. - */ -static void vLCDTask( void * pvParameters ); - -/* - * The task that receives the characters from UART 0. - */ -static void vCommsRxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); - -/* - * The co-routine that periodically initiates the transmission of the string on - * the UART. - */ -static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); - -/* - * Writes a string the the LCD. - */ -static void prvWriteString( const portCHAR *pcString ); - -/* - * Initialisation routine for the UART. - */ -static void vSerialInit( void ); - -/* - * Thread safe write to the PDC. - */ -static void prvPDCWrite( portCHAR cAddress, portCHAR cData ); - -/* - * Function to simply set a known value into the general purpose registers - * then read them back to ensure they remain set correctly. An incorrect value - * being indicative of an error in the task switching mechanism. - */ -void prvSetAndCheckRegisters( void ); - -/* - * Latch the LED that indicates that an error has occurred. - */ -void vSetErrorLED( void ); - -/* - * Sets up the PLL and ports used by the demo. - */ -static void prvSetupHardware( void ); - -/*-----------------------------------------------------------*/ - -/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines -defined within this file. */ -unsigned portBASE_TYPE uxErrorStatus = pdPASS; - -/* The next character to transmit. */ -static portCHAR cNextChar; - -/* The queue used to transmit characters from the interrupt to the Comms Rx -task. */ -static xQueueHandle xCommsQueue; - -/*-----------------------------------------------------------*/ - -int main( void ) -{ - /* Create the queue used to communicate between the UART ISR and the Comms - Rx task. */ - xCommsQueue = xQueueCreate( mainRX_QUEUE_LEN, sizeof( portCHAR ) ); - - /* Setup the ports used by the demo and the clock. */ - prvSetupHardware(); - - /* Create the co-routines that flash the LED's. */ - vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES ); - - /* Create the co-routine that initiates the transmission of characters - on the UART. */ - xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX ); - - /* Create the co-routine that receives characters from the UART. */ - xCoRoutineCreate( vCommsRxCoRoutine, mainRX_CO_ROUTINE_PRIORITY, mainRX_CO_ROUTINE_INDEX ); - - /* Create the LCD task. */ - xTaskCreate( vLCDTask, "LCD", configMINIMAL_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL ); - - /* Start the scheduler running the tasks and co-routines just created. */ - vTaskStartScheduler(); - - /* Should not get here unless we did not have enough memory to start the - scheduler. */ - for( ;; ); - return 0; -} -/*-----------------------------------------------------------*/ - -static void prvSetupHardware( void ) -{ - /* Setup the PLL. */ - SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); - - /* Initialise the hardware used to talk to the LCD, LED's and UART. */ - PDCInit(); - vParTestInitialise(); - vSerialInit(); -} -/*-----------------------------------------------------------*/ - -void vApplicationIdleHook( void ) -{ - /* The co-routines are executed in the idle task using the idle task - hook. */ - for( ;; ) - { - /* Schedule the co-routines. */ - vCoRoutineSchedule(); - - /* Run the register check function between each co-routine. */ - prvSetAndCheckRegisters(); - } -} -/*-----------------------------------------------------------*/ - -static void prvWriteString( const portCHAR *pcString ) -{ - /* Write pcString to the LED, pausing between each character. */ - prvPDCWrite(PDC_LCD_CSR, LCD_CLEAR); - while( *pcString ) - { - vTaskDelay( mainCHAR_WRITE_DELAY ); - prvPDCWrite( PDC_LCD_RAM, *pcString ); - pcString++; - } -} -/*-----------------------------------------------------------*/ - -void vLCDTask( void * pvParameters ) -{ -unsigned portBASE_TYPE uxIndex; -const unsigned portCHAR ucCFGData[] = { - 0x30, /* Set data bus to 8-bits. */ - 0x30, - 0x30, - 0x3C, /* Number of lines/font. */ - 0x08, /* Display off. */ - 0x01, /* Display clear. */ - 0x06, /* Entry mode [cursor dir][shift]. */ - 0x0C /* Display on [display on][curson on][blinking on]. */ - }; - -/* The strings that are written to the LCD. */ -const portCHAR *pcStringsToDisplay[] = { - "Stellaris", - "Demo", - "Two", - "www.FreeRTOS.org", - "" - }; - - /* Configure the LCD. */ - uxIndex = 0; - while( uxIndex < sizeof( ucCFGData ) ) - { - prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] ); - uxIndex++; - vTaskDelay( mainCHAR_WRITE_DELAY ); - } - - /* Turn the LCD Backlight on. */ - prvPDCWrite( PDC_CSR, 0x01 ); - - /* Clear display. */ - vTaskDelay( mainCHAR_WRITE_DELAY ); - prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); - - uxIndex = 0; - for( ;; ) - { - /* Display the string on the LCD. */ - prvWriteString( pcStringsToDisplay[ uxIndex ] ); - - /* Move on to the next string - wrapping if necessary. */ - uxIndex++; - if( *( pcStringsToDisplay[ uxIndex ] ) == 0x00 ) - { - uxIndex = 0; - /* Longer pause on the last string to be sent. */ - vTaskDelay( mainSTRING_WRITE_DELAY * 2 ); - } - - /* Wait until it is time to move onto the next string. */ - vTaskDelay( mainSTRING_WRITE_DELAY ); - } -} -/*-----------------------------------------------------------*/ - -static void vCommsRxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) -{ -static portCHAR cRxedChar, cExpectedChar = mainFIRST_TX_CHAR; -portBASE_TYPE xResult; - - crSTART( xHandle ); - - for( ;; ) - { - /* Wait for a character to be received. */ - crQUEUE_RECEIVE( xHandle, xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY, &xResult ); - - /* Was the character recived (if any) the expected character. */ - if( ( cRxedChar != cExpectedChar ) || ( xResult != pdPASS ) ) - { - /* Got an unexpected character. This can sometimes occur when - reseting the system using the debugger leaving characters already - in the UART regsters. */ - uxErrorStatus = pdFAIL; - - /* Resync by waiting for the end of the current string. */ - while( cRxedChar != mainLAST_TX_CHAR ) - { - crQUEUE_RECEIVE( xHandle, xCommsQueue, ( void * ) &cRxedChar, mainCOMMS_RX_DELAY, &xResult ); - } - - /* The next expected character is the start of the string again. */ - cExpectedChar = mainFIRST_TX_CHAR; - } - else - { - if( cExpectedChar == mainLAST_TX_CHAR ) - { - /* We have reached the end of the string - we now expect to - receive the first character in the string again. The LED is - toggled to indicate that the entire string was received without - error. */ - vParTestToggleLED( mainCOMMS_RX_LED ); - cExpectedChar = mainFIRST_TX_CHAR; - } - else - { - /* We got the expected character, we now expect to receive the - next character in the string. */ - cExpectedChar++; - } - } - } - - crEND(); -} -/*-----------------------------------------------------------*/ - -static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) -{ -portTickType xDelayPeriod; -static unsigned portLONG *pulRandomBytes = mainFIRST_PROGRAM_BYTES; - - /* Co-routine MUST start with a call to crSTART. */ - crSTART( xHandle ); - - for(;;) - { - /* Was the previously transmitted string received correctly? */ - if( uxErrorStatus != pdPASS ) - { - /* An error was encountered so set the error LED. */ - vSetErrorLED(); - } - - /* The next character to Tx is the first in the string. */ - cNextChar = mainFIRST_TX_CHAR; - - UARTIntDisable( UART0_BASE, UART_INT_TX ); - { - /* Send the first character. */ - if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) - { - HWREG( UART0_BASE + UART_O_DR ) = cNextChar; - } - - /* Move the variable to the char to Tx on so the ISR transmits - the next character in the string once this one has completed. */ - cNextChar++; - } - UARTIntEnable(UART0_BASE, UART_INT_TX); - - /* Toggle the LED to show a new string is being transmitted. */ - vParTestToggleLED( mainCOMMS_TX_LED ); - - /* Delay before we start the string off again. A pseudo-random delay - is used as this will provide a better test. */ - xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes ); - - pulRandomBytes++; - if( pulRandomBytes > mainTOTAL_PROGRAM_MEMORY ) - { - pulRandomBytes = mainFIRST_PROGRAM_BYTES; - } - - /* Make sure we don't wait too long... */ - xDelayPeriod &= mainMAX_TX_DELAY; - - /* ...but we do want to wait. */ - if( xDelayPeriod < mainMIN_TX_DELAY ) - { - xDelayPeriod = mainMIN_TX_DELAY; - } - - /* Block for the random(ish) time. */ - crDELAY( xHandle, xDelayPeriod ); - } - - /* Co-routine MUST end with a call to crEND. */ - crEND(); -} -/*-----------------------------------------------------------*/ - -static void vSerialInit( void ) -{ - /* Enable the UART. GPIOA has already been initialised. */ - SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); - - /* Set GPIO A0 and A1 as peripheral function. They are used to output the - UART signals. */ - GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); - - /* Configure the UART for 8-N-1 operation. */ - UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); - - /* We dont want to use the fifo. This is for test purposes to generate - as many interrupts as possible. */ - HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; - - /* Enable both Rx and Tx interrupts. */ - HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX ); - IntEnable( INT_UART0 ); -} -/*-----------------------------------------------------------*/ - -void vUART_ISR(void) -{ -unsigned portLONG ulStatus; -portCHAR cRxedChar; -portBASE_TYPE xTaskWokenByPost = pdFALSE; - - /* What caused the interrupt. */ - ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); - - /* Clear the interrupt. */ - UARTIntClear( UART0_BASE, ulStatus ); - - /* Was an Rx interrpt pending? */ - if( ulStatus & UART_INT_RX ) - { - if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) ) - { - /* Get the char from the buffer and post it onto the queue of - Rxed chars. Posting the character should wake the task that is - blocked on the queue waiting for characters. */ - cRxedChar = ( portCHAR ) HWREG( UART0_BASE + UART_O_DR ); - xTaskWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsQueue, &cRxedChar, xTaskWokenByPost ); - } - } - - /* Was a Tx interrupt pending? */ - if( ulStatus & UART_INT_TX ) - { - /* Send the next character in the string. We are not using the FIFO. */ - if( cNextChar <= mainLAST_TX_CHAR ) - { - if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) - { - HWREG( UART0_BASE + UART_O_DR ) = cNextChar; - } - cNextChar++; - } - } - - if( xTaskWokenByPost ) - { - /* We are posting to a co-routine rather than a task so don't bother - causing a task switch. */ - } -} -/*-----------------------------------------------------------*/ - -static void prvPDCWrite( portCHAR cAddress, portCHAR cData ) -{ - vTaskSuspendAll(); - { - PDCWrite( cAddress, cData ); - } - xTaskResumeAll(); -} -/*-----------------------------------------------------------*/ - -void vSetErrorLED( void ) -{ - vParTestSetLED( mainCOMMS_FAIL_LED, pdTRUE ); -} -/*-----------------------------------------------------------*/ - -void prvSetAndCheckRegisters( void ) -{ - /* Fill the general purpose registers with known values. */ - __asm volatile - ( - " mov r11, #10 \n" - " add r0, r11, #1 \n" - " add r1, r11, #2 \n" - " add r2, r11, #3 \n" - " add r3, r11, #4 \n" - " add r4, r11, #5 \n" - " add r5, r11, #6 \n" - " add r6, r11, #7 \n" - " add r7, r11, #8 \n" - " add r8, r11, #9 \n" - " add r9, r11, #10 \n" - " add r10, r11, #11 \n" - " add r12, r11, #12" - ); - - /* Check the values are as expected. */ - __asm volatile - ( - " cmp r11, #10 \n" - " bne set_error_led \n" - " cmp r0, #11 \n" - " bne set_error_led \n" - " cmp r1, #12 \n" - " bne set_error_led \n" - " cmp r2, #13 \n" - " bne set_error_led \n" - " cmp r3, #14 \n" - " bne set_error_led \n" - " cmp r4, #15 \n" - " bne set_error_led \n" - " cmp r5, #16 \n" - " bne set_error_led \n" - " cmp r6, #17 \n" - " bne set_error_led \n" - " cmp r7, #18 \n" - " bne set_error_led \n" - " cmp r8, #19 \n" - " bne set_error_led \n" - " cmp r9, #20 \n" - " bne set_error_led \n" - " cmp r10, #21 \n" - " bne set_error_led \n" - " cmp r12, #22 \n" - " bne set_error_led \n" - " bx lr" - ); - - __asm volatile - ( - "set_error_led: \n" - " push {r14} \n" - " ldr r1, vSetErrorLEDConst\n" - " blx r1 \n" - " pop {r14} \n" - " bx lr \n" - " \n" - " .align 2 \n" - "vSetErrorLEDConst: .word vSetErrorLED" - ); -} -/*-----------------------------------------------------------*/ diff --git a/Demo/CORTEX_LM3S102_Rowley/Demo2/vectors.s b/Demo/CORTEX_LM3S102_Rowley/Demo2/vectors.s deleted file mode 100644 index 2ff9827a2..000000000 --- a/Demo/CORTEX_LM3S102_Rowley/Demo2/vectors.s +++ /dev/null @@ -1,119 +0,0 @@ -/***************************************************************************** - * Copyright (c) 2006 Rowley Associates Limited. * - * * - * This file may be distributed under the terms of the License Agreement * - * provided with this software. * - * * - * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE * - * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * - *****************************************************************************/ - .section .vectors, "ax" - .code 16 - .align 0 - .global _vectors - - .extern xPortPendSVHandler - .extern xPortSysTickHandler - .extern vUART_ISR - -.macro DEFAULT_ISR_HANDLER name= - .thumb_func - .weak \name -\name: -1: b 1b /* endless loop */ -.endm - -_vectors: - .word __stack_end__ -#ifdef STARTUP_FROM_RESET - .word _start -#else - .word reset_wait -#endif /* STARTUP_FROM_RESET */ - .word NmiISR - .word FaultISR - .word 0 // Populate if using MemManage (MPU) - .word 0 // Populate if using Bus fault - .word 0 // Populate if using Usage fault - .word 0 // Reserved - .word 0 // Reserved - .word 0 // Reserved - .word 0 // Reserved - .word 0 - .word 0 // Populate if using a debug monitor - .word 0 // Reserved - .word xPortPendSVHandler // Populate if using pendable service request - .word xPortSysTickHandler - // External interrupts start her - .word GPIO_Port_A_ISR - .word GPIO_Port_B_ISR - .word GPIO_Port_C_ISR - .word GPIO_Port_D_ISR - .word GPIO_Port_E_ISR - .word vUART_ISR - .word UART1_ISR - .word SSI_ISR - .word I2C_ISR - .word PWM_Fault_ISR - .word PWM_Generator_0_ISR - .word PWM_Generator_1_ISR - .word PWM_Generator_2_ISR - .word QEI_ISR - .word ADC_Sequence_0_ISR - .word ADC_Sequence_1_ISR - .word ADC_Sequence_2_ISR - .word ADC_Sequence_3_ISR - .word Watchdog_timer_ISR - .word Timer0a_ISR - .word Timer0b_ISR - .word Timer1a_ISR - .word Timer1b_ISR - .word Timer2a_ISR - .word Timer2b_ISR - .word Analog_Comparator_0_ISR - .word Analog_Comparator_1_ISR - .word Analog_Comparator_2_ISR - .word System_Control_ISR - .word FLASH_Control_ISR - - .section .init, "ax" - .thumb_func - -DEFAULT_ISR_HANDLER NmiISR -DEFAULT_ISR_HANDLER FaultISR -DEFAULT_ISR_HANDLER SVCallISR -DEFAULT_ISR_HANDLER SysTickISR -DEFAULT_ISR_HANDLER GPIO_Port_A_ISR -DEFAULT_ISR_HANDLER GPIO_Port_B_ISR -DEFAULT_ISR_HANDLER GPIO_Port_C_ISR -DEFAULT_ISR_HANDLER GPIO_Port_D_ISR -DEFAULT_ISR_HANDLER GPIO_Port_E_ISR -DEFAULT_ISR_HANDLER UART0_ISR -DEFAULT_ISR_HANDLER UART1_ISR -DEFAULT_ISR_HANDLER SSI_ISR -DEFAULT_ISR_HANDLER I2C_ISR -DEFAULT_ISR_HANDLER PWM_Fault_ISR -DEFAULT_ISR_HANDLER PWM_Generator_0_ISR -DEFAULT_ISR_HANDLER PWM_Generator_1_ISR -DEFAULT_ISR_HANDLER PWM_Generator_2_ISR -DEFAULT_ISR_HANDLER QEI_ISR -DEFAULT_ISR_HANDLER ADC_Sequence_0_ISR -DEFAULT_ISR_HANDLER ADC_Sequence_1_ISR -DEFAULT_ISR_HANDLER ADC_Sequence_2_ISR -DEFAULT_ISR_HANDLER ADC_Sequence_3_ISR -DEFAULT_ISR_HANDLER Watchdog_timer_ISR -DEFAULT_ISR_HANDLER Timer0a_ISR -DEFAULT_ISR_HANDLER Timer0b_ISR -DEFAULT_ISR_HANDLER Timer1a_ISR -DEFAULT_ISR_HANDLER Timer1b_ISR -DEFAULT_ISR_HANDLER Timer2a_ISR -DEFAULT_ISR_HANDLER Timer2b_ISR -DEFAULT_ISR_HANDLER Analog_Comparator_0_ISR -DEFAULT_ISR_HANDLER Analog_Comparator_1_ISR -DEFAULT_ISR_HANDLER Analog_Comparator_2_ISR -DEFAULT_ISR_HANDLER System_Control_ISR -DEFAULT_ISR_HANDLER FLASH_Control_ISR - -#ifndef STARTUP_FROM_RESET -DEFAULT_ISR_HANDLER reset_wait -#endif /* STARTUP_FROM_RESET */ diff --git a/Demo/CORTEX_LM3S102_Rowley/Demo3/FreeRTOSConfig.h b/Demo/CORTEX_LM3S102_Rowley/Demo3/FreeRTOSConfig.h deleted file mode 100644 index 54d034cfa..000000000 --- a/Demo/CORTEX_LM3S102_Rowley/Demo3/FreeRTOSConfig.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 0 -#define configUSE_IDLE_HOOK 1 -#define configUSE_TICK_HOOK 0 -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 ) -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 59 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1240 ) ) -#define configMAX_TASK_NAME_LEN ( 3 ) -#define configUSE_TRACE_FACILITY 0 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 0 -#define configUSE_CO_ROUTINES 1 - -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 ) -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 0 -#define INCLUDE_uxTaskPriorityGet 0 -#define INCLUDE_vTaskDelete 0 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 0 -#define INCLUDE_vTaskDelayUntil 0 -#define INCLUDE_vTaskDelay 0 - - - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/CORTEX_LM3S102_Rowley/Demo3/ParTest.c b/Demo/CORTEX_LM3S102_Rowley/Demo3/ParTest.c deleted file mode 100644 index 8c146e890..000000000 --- a/Demo/CORTEX_LM3S102_Rowley/Demo3/ParTest.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/*----------------------------------------------------------- - * Simple parallel port IO routines. - *-----------------------------------------------------------*/ - -/* -*/ - -/* Kernel include files. */ -#include "FreeRTOS.h" -#include "Task.h" -#include "partest.h" - -/* Hardware specific include files. */ -#include "DriverLib.h" - -static const unsigned portLONG ulLEDs[] = -{ - GPIO_PIN_6, GPIO_PIN_1, GPIO_PIN_0 -}; - -#define partstLED_PINS ( GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_6 ) - -#define partstMAX_OUTPUT_LED ( ( unsigned portCHAR ) 3 ) - -/*-----------------------------------------------------------*/ -void vParTestInitialise( void ) -{ -portBASE_TYPE xLED; - - /* The LED's are on port B. */ - GPIODirModeSet( GPIO_PORTB_BASE, partstLED_PINS, GPIO_DIR_MODE_OUT ); - - for( xLED = 0; xLED < partstMAX_OUTPUT_LED; xLED++ ) - { - vParTestSetLED( xLED, pdFALSE ); - } -} -/*-----------------------------------------------------------*/ - -void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) -{ - vTaskSuspendAll(); - { - if( uxLED < partstMAX_OUTPUT_LED ) - { - if( xValue == pdFALSE ) - { - GPIOPinWrite( GPIO_PORTB_BASE, ulLEDs[ uxLED ], ulLEDs[ uxLED ] ); - } - else - { - GPIOPinWrite( GPIO_PORTB_BASE, ulLEDs[ uxLED ], ~ulLEDs[ uxLED ] ); - } - } - } - xTaskResumeAll(); -} -/*-----------------------------------------------------------*/ - -void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) -{ -portBASE_TYPE xCurrentValue; - - vTaskSuspendAll(); - { - if( uxLED < partstMAX_OUTPUT_LED ) - { - xCurrentValue = GPIOPinRead( GPIO_PORTB_BASE, ulLEDs[ uxLED ] ); - if( xCurrentValue ) - { - GPIOPinWrite( GPIO_PORTB_BASE, ulLEDs[ uxLED ], ~ulLEDs[ uxLED ] ); - } - else - { - GPIOPinWrite( GPIO_PORTB_BASE, ulLEDs[ uxLED ], ulLEDs[ uxLED ] ); - } - } - } - xTaskResumeAll(); -} diff --git a/Demo/CORTEX_LM3S102_Rowley/Demo3/main.c b/Demo/CORTEX_LM3S102_Rowley/Demo3/main.c deleted file mode 100644 index 5dc4c012b..000000000 --- a/Demo/CORTEX_LM3S102_Rowley/Demo3/main.c +++ /dev/null @@ -1,290 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/* - * This is a mini co-routine demo for the Rowley CrossFire LM3S102 development - * board. It makes use of the boards tri-colour LED and analogue input. - * - * Four co-routines are created - an 'I2C' co-routine and three 'flash' - * co-routines. - * - * The I2C co-routine triggers an ADC conversion then blocks on a queue to - * wait for the conversion result - which it receives on the queue directly - * from the I2C interrupt service routine. The conversion result is then - * scalled to a delay period. The I2C interrupt then wakes each of the - * flash co-routines before itself delaying for the calculated period and - * then repeating the whole process. - * - * When woken by the I2C co-routine the flash co-routines each block for - * a given period, illuminate an LED for a fixed period, then go back to - * sleep to wait for the next cycle. The uxIndex parameter of the flash - * co-routines is used to ensure that each flashes a different LED, and that - * the delay periods are such that the LED's get flashed in sequence. - */ - - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" -#include "croutine.h" - -/* Demo application include files. */ -#include "partest.h" - -/* Library include files. */ -#include "DriverLib.h" - -/* States of the I2C master interface. */ -#define mainI2C_IDLE 0 -#define mainI2C_READ_1 1 -#define mainI2C_READ_2 2 -#define mainI2C_READ_DONE 3 - -#define mainZERO_LENGTH 0 - -/* Address of the A2D IC on the CrossFire board. */ -#define mainI2CAddress 0x4D - -/* The queue used to send data from the I2C ISR to the co-routine should never -contain more than one item as the same co-routine is used to trigger the I2C -activity. */ -#define mainQUEUE_LENGTH 1 - -/* The CrossFire board contains a tri-colour LED. */ -#define mainNUM_LEDs 3 - -/* The I2C co-routine has a higher priority than the flash co-routines. This -is not really necessary as when the I2C co-routine is active the other -co-routines are delaying. */ -#define mainI2c_CO_ROUTINE_PRIORITY 1 - - -/* The current state of the I2C master. */ -static volatile unsigned portBASE_TYPE uxState = mainI2C_IDLE; - -/* The delay period derived from the A2D value. */ -static volatile portBASE_TYPE uxDelay = 250; - -/* The queue used to communicate between the I2C interrupt and the I2C -co-routine. */ -static xQueueHandle xADCQueue; - -/* The queue used to synchronise the flash co-routines. */ -static xQueueHandle xDelayQueue; - -/* - * Sets up the PLL, I2C and GPIO used by the demo. - */ -static void prvSetupHardware( void ); - -/* The co-routines as described at the top of the file. */ -static void vI2CCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); -static void vFlashCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); - -/*-----------------------------------------------------------*/ - -int main( void ) -{ -unsigned portBASE_TYPE uxCoRoutine; - - /* Setup all the hardware used by this demo. */ - prvSetupHardware(); - - /* Create the queue used to communicate between the ISR and I2C co-routine. - This can only ever contain one value. */ - xADCQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( portTickType ) ); - - /* Create the queue used to synchronise the flash co-routines. The queue - is used to trigger three tasks, but is for synchronisation only and does - not pass any data. It therefore has three position each of zero length. */ - xDelayQueue = xQueueCreate( mainNUM_LEDs, mainZERO_LENGTH ); - - /* Create the co-routine that initiates the i2c. */ - xCoRoutineCreate( vI2CCoRoutine, mainI2c_CO_ROUTINE_PRIORITY, 0 ); - - /* Create the flash co-routines. */ - for( uxCoRoutine = 0; uxCoRoutine < mainNUM_LEDs; uxCoRoutine++ ) - { - xCoRoutineCreate( vFlashCoRoutine, tskIDLE_PRIORITY, uxCoRoutine ); - } - - /* Start the scheduler. From this point on the co-routines should - execute. */ - vTaskStartScheduler(); - - /* Should not get here unless we did not have enough memory to start the - scheduler. */ - for( ;; ); - return 0; -} -/*-----------------------------------------------------------*/ - -static void prvSetupHardware( void ) -{ - /* Setup the PLL. */ - SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); - - /* Enable the I2C used to read the pot. */ - SysCtlPeripheralEnable( SYSCTL_PERIPH_I2C ); - SysCtlPeripheralEnable( SYSCTL_PERIPH_GPIOB ); - GPIOPinTypeI2C( GPIO_PORTB_BASE, GPIO_PIN_2 | GPIO_PIN_3 ); - - /* Initialize the I2C master. */ - I2CMasterInit( I2C_MASTER_BASE, pdFALSE ); - - /* Enable the I2C master interrupt. */ - I2CMasterIntEnable( I2C_MASTER_BASE ); - IntEnable( INT_I2C ); - - /* Initialise the hardware used to talk to the LED's. */ - vParTestInitialise(); -} -/*-----------------------------------------------------------*/ - -static void vI2CCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) -{ -portTickType xADCResult; -static portBASE_TYPE xResult = 0, xMilliSecs, xLED; - - crSTART( xHandle ); - - for( ;; ) - { - /* Start the I2C off to read the ADC. */ - uxState = mainI2C_READ_1; - I2CMasterSlaveAddrSet( I2C_MASTER_BASE, mainI2CAddress, pdTRUE ); - I2CMasterControl( I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_RECEIVE_START ); - - /* Wait to receive the conversion result. */ - crQUEUE_RECEIVE( xHandle, xADCQueue, &xADCResult, portMAX_DELAY, &xResult ); - - /* Scale the result to give a useful range of values for a visual - demo. */ - xADCResult >>= 2; - xMilliSecs = xADCResult / portTICK_RATE_MS; - - /* The delay is split between the four co-routines so they remain in - synch. */ - uxDelay = xMilliSecs / ( mainNUM_LEDs + 1 ); - - /* Trigger each of the flash co-routines. */ - for( xLED = 0; xLED < mainNUM_LEDs; xLED++ ) - { - crQUEUE_SEND( xHandle, xDelayQueue, &xLED, 0, &xResult ); - } - - /* Wait for the full delay time then start again. This delay is long - enough to ensure the flash co-routines have done their thing and gone - back to sleep. */ - crDELAY( xHandle, xMilliSecs ); - } - - crEND(); -} -/*-----------------------------------------------------------*/ - -static void vFlashCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) -{ -portBASE_TYPE xResult, xNothing; - - crSTART( xHandle ); - - for( ;; ) - { - /* Wait for start of next round. */ - crQUEUE_RECEIVE( xHandle, xDelayQueue, &xNothing, portMAX_DELAY, &xResult ); - - /* Wait until it is this co-routines turn to flash. */ - crDELAY( xHandle, uxDelay * uxIndex ); - - /* Turn on the LED for a fixed period. */ - vParTestSetLED( uxIndex, pdTRUE ); - crDELAY( xHandle, uxDelay ); - vParTestSetLED( uxIndex, pdFALSE ); - - /* Go back and wait for the next round. */ - } - - crEND(); -} -/*-----------------------------------------------------------*/ - -void vI2C_ISR(void) -{ -static portTickType xReading; - - /* Clear the interrupt. */ - I2CMasterIntClear( I2C_MASTER_BASE ); - - /* Determine what to do based on the current uxState. */ - switch (uxState) - { - case mainI2C_IDLE: break; - - case mainI2C_READ_1: /* Read ADC result high byte. */ - xReading = I2CMasterDataGet( I2C_MASTER_BASE ); - xReading <<= 8; - - /* Continue the burst read. */ - I2CMasterControl( I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_RECEIVE_CONT ); - uxState = mainI2C_READ_2; - break; - - case mainI2C_READ_2: /* Read ADC result low byte. */ - xReading |= I2CMasterDataGet( I2C_MASTER_BASE ); - - /* Finish the burst read. */ - I2CMasterControl( I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_RECEIVE_FINISH ); - uxState = mainI2C_READ_DONE; - break; - - case mainI2C_READ_DONE: /* Complete. */ - I2CMasterDataGet( I2C_MASTER_BASE ); - uxState = mainI2C_IDLE; - - /* Send the result to the co-routine. */ - crQUEUE_SEND_FROM_ISR( xADCQueue, &xReading, pdFALSE ); - break; - } -} -/*-----------------------------------------------------------*/ - -void vApplicationIdleHook( void ) -{ - for( ;; ) - { - vCoRoutineSchedule(); - } -} - diff --git a/Demo/CORTEX_LM3S102_Rowley/Demo3/vectors.s b/Demo/CORTEX_LM3S102_Rowley/Demo3/vectors.s deleted file mode 100644 index c06b1fefd..000000000 --- a/Demo/CORTEX_LM3S102_Rowley/Demo3/vectors.s +++ /dev/null @@ -1,120 +0,0 @@ -/***************************************************************************** - * Copyright (c) 2006 Rowley Associates Limited. * - * * - * This file may be distributed under the terms of the License Agreement * - * provided with this software. * - * * - * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE * - * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * - *****************************************************************************/ - .section .vectors, "ax" - .code 16 - .align 0 - .global _vectors - - .extern xPortPendSVHandler - .extern xPortSysTickHandler - .extern vI2C_ISR - .extern faultisr - -.macro DEFAULT_ISR_HANDLER name= - .thumb_func - .weak \name -\name: -1: b 1b /* endless loop */ -.endm - -_vectors: - .word __stack_end__ -#ifdef STARTUP_FROM_RESET - .word _start -#else - .word reset_wait -#endif /* STARTUP_FROM_RESET */ - .word NmiISR - .word FaultISR - .word 0 // Populate if using MemManage (MPU) - .word 0 // Populate if using Bus fault - .word 0 // Populate if using Usage fault - .word 0 // Reserved - .word 0 // Reserved - .word 0 // Reserved - .word 0 // Reserved - .word 0 - .word 0 // Populate if using a debug monitor - .word 0 // Reserved - .word xPortPendSVHandler // Populate if using pendable service request - .word xPortSysTickHandler - // External interrupts start her - .word GPIO_Port_A_ISR - .word GPIO_Port_B_ISR - .word GPIO_Port_C_ISR - .word GPIO_Port_D_ISR - .word GPIO_Port_E_ISR - .word UART0_ISR - .word UART1_ISR - .word SSI_ISR - .word vI2C_ISR - .word PWM_Fault_ISR - .word PWM_Generator_0_ISR - .word PWM_Generator_1_ISR - .word PWM_Generator_2_ISR - .word QEI_ISR - .word ADC_Sequence_0_ISR - .word ADC_Sequence_1_ISR - .word ADC_Sequence_2_ISR - .word ADC_Sequence_3_ISR - .word Watchdog_timer_ISR - .word Timer0a_ISR - .word Timer0b_ISR - .word Timer1a_ISR - .word Timer1b_ISR - .word Timer2a_ISR - .word Timer2b_ISR - .word Analog_Comparator_0_ISR - .word Analog_Comparator_1_ISR - .word Analog_Comparator_2_ISR - .word System_Control_ISR - .word FLASH_Control_ISR - - .section .init, "ax" - .thumb_func - -DEFAULT_ISR_HANDLER NmiISR -DEFAULT_ISR_HANDLER FaultISR -DEFAULT_ISR_HANDLER SVCallISR -DEFAULT_ISR_HANDLER SysTickISR -DEFAULT_ISR_HANDLER GPIO_Port_A_ISR -DEFAULT_ISR_HANDLER GPIO_Port_B_ISR -DEFAULT_ISR_HANDLER GPIO_Port_C_ISR -DEFAULT_ISR_HANDLER GPIO_Port_D_ISR -DEFAULT_ISR_HANDLER GPIO_Port_E_ISR -DEFAULT_ISR_HANDLER UART0_ISR -DEFAULT_ISR_HANDLER UART1_ISR -DEFAULT_ISR_HANDLER SSI_ISR -DEFAULT_ISR_HANDLER I2C_ISR -DEFAULT_ISR_HANDLER PWM_Fault_ISR -DEFAULT_ISR_HANDLER PWM_Generator_0_ISR -DEFAULT_ISR_HANDLER PWM_Generator_1_ISR -DEFAULT_ISR_HANDLER PWM_Generator_2_ISR -DEFAULT_ISR_HANDLER QEI_ISR -DEFAULT_ISR_HANDLER ADC_Sequence_0_ISR -DEFAULT_ISR_HANDLER ADC_Sequence_1_ISR -DEFAULT_ISR_HANDLER ADC_Sequence_2_ISR -DEFAULT_ISR_HANDLER ADC_Sequence_3_ISR -DEFAULT_ISR_HANDLER Watchdog_timer_ISR -DEFAULT_ISR_HANDLER Timer0a_ISR -DEFAULT_ISR_HANDLER Timer0b_ISR -DEFAULT_ISR_HANDLER Timer1a_ISR -DEFAULT_ISR_HANDLER Timer1b_ISR -DEFAULT_ISR_HANDLER Timer2a_ISR -DEFAULT_ISR_HANDLER Timer2b_ISR -DEFAULT_ISR_HANDLER Analog_Comparator_0_ISR -DEFAULT_ISR_HANDLER Analog_Comparator_1_ISR -DEFAULT_ISR_HANDLER Analog_Comparator_2_ISR -DEFAULT_ISR_HANDLER System_Control_ISR -DEFAULT_ISR_HANDLER FLASH_Control_ISR - -#ifndef STARTUP_FROM_RESET -DEFAULT_ISR_HANDLER reset_wait -#endif /* STARTUP_FROM_RESET */ diff --git a/Demo/CORTEX_LM3S102_Rowley/RTOSDemo.hzp b/Demo/CORTEX_LM3S102_Rowley/RTOSDemo.hzp deleted file mode 100644 index dc51429e9..000000000 --- a/Demo/CORTEX_LM3S102_Rowley/RTOSDemo.hzp +++ /dev/null @@ -1,110 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Demo/CORTEX_LM3S102_Rowley/RTOSDemo.hzs b/Demo/CORTEX_LM3S102_Rowley/RTOSDemo.hzs deleted file mode 100644 index db7d6d992..000000000 --- a/Demo/CORTEX_LM3S102_Rowley/RTOSDemo.hzs +++ /dev/null @@ -1,90 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/DriverLib.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/DriverLib.h deleted file mode 100644 index 3eb2ebcb6..000000000 --- a/Demo/CORTEX_LM3S102_Rowley/hw_include/DriverLib.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef INCLUDE_DRIVER_LIB_H -#define INCLUDE_DRIVER_LIB_H - -#include "hw_ints.h" -#include "hw_uart.h" -#include "hw_memmap.h" -#include "hw_types.h" -#include "hw_nvic.h" -#include "hw_ssi.h" -#include "hw_i2c.h" - -#include "gpio.h" -#include "interrupt.h" -#include "sysctl.h" -#include "uart.h" -#include "ssi.h" -#include "pdc.h" -#include "i2c.h" - -#endif diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/EULA.txt b/Demo/CORTEX_LM3S102_Rowley/hw_include/EULA.txt deleted file mode 100644 index cba31f7dc..000000000 --- a/Demo/CORTEX_LM3S102_Rowley/hw_include/EULA.txt +++ /dev/null @@ -1,126 +0,0 @@ -IMPORTANT. Read the following LMI Software License Agreement ("Agreement") -completely. - -LUMINARY MICRO SOFTWARE LICENSE AGREEMENT - - This is a legal agreement between you (either as an individual or as an -authorized representative of your employer) and Luminary Micro, Inc. ("LMI"). -It concerns your rights to use this file and any accompanying written materials -(the "Software"). In consideration for LMI allowing you to access the -Software, you are agreeing to be bound by the terms of this Agreement. If you -do not agree to all of the terms of this Agreement, do not download or use the -Software. If you change your mind later, stop using the Software and delete -all copies of the Software in your possession or control. Any copies of the -Software that you have already distributed, where permitted, and do not destroy -will continue to be governed by this Agreement. Your prior use will also -continue to be governed by this Agreement. - -1. LICENSE GRANT. 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The waiver by LMI of any breach of any provision of this -Agreement will not operate or be construed as a waiver of any other or a -subsequent breach of the same or a different provision. diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/comp.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/comp.h deleted file mode 100644 index a4c307b8c..000000000 --- a/Demo/CORTEX_LM3S102_Rowley/hw_include/comp.h +++ /dev/null @@ -1,112 +0,0 @@ -//***************************************************************************** -// -// comp.h - Prototypes for the analog comparator driver. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 523 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __COMP_H__ -#define __COMP_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to ComparatorConfigure() as the ulConfig -// parameter. For each group (i.e. COMP_INT_xxx, COMP_ASRCP_xxx, etc.), one of -// the values may be selected and ORed together will values from the other -// groups. -// -//***************************************************************************** -#define COMP_INT_HIGH 0x00000010 // Interrupt when high -#define COMP_INT_LOW 0x00000000 // Interrupt when low -#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge -#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge -#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges -#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin -#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin -#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference -#define COMP_OUTPUT_NONE 0x00000000 // No comparator output -#define COMP_OUTPUT_NORMAL 0x00000100 // Comparator output normal -#define COMP_OUTPUT_INVERT 0x00000102 // Comparator output inverted - -//***************************************************************************** -// -// Values that can be passed to ComparatorSetRef() as the ulRef parameter. -// -//***************************************************************************** -#define COMP_REF_OFF 0x00000000 // Turn off the internal reference -#define COMP_REF_0V 0x00000300 // Internal reference of 0V -#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V -#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V -#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V -#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V -#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V -#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V -#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V -#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V -#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V -#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V -#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V -#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V -#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V -#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V -#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V -#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V -#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V -#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V -#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V -#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V -#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V -#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V -#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V -#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V -#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V -#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V -#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp, - unsigned long ulConfig); -extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef); -extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp); -extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp, - void (*pfnHandler)(void)); -extern void ComparatorIntUnregister(unsigned long ulBase, - unsigned long ulComp); -extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp, - tBoolean bMasked); -extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp); - -#ifdef __cplusplus -} -#endif - -#endif // __COMP_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/cpu.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/cpu.h deleted file mode 100644 index a93771bdb..000000000 --- a/Demo/CORTEX_LM3S102_Rowley/hw_include/cpu.h +++ /dev/null @@ -1,40 +0,0 @@ -//***************************************************************************** -// -// cpu.h - Prototypes for the CPU instruction wrapper functions. -// -// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 523 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __CPU_H__ -#define __CPU_H__ - -//***************************************************************************** -// -// Prototypes. -// -//***************************************************************************** -extern void CPUcpsid(void); -extern void CPUcpsie(void); -extern void CPUwfi(void); - -#endif // __CPU_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/debug.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/debug.h deleted file mode 100644 index 2f259bd23..000000000 --- a/Demo/CORTEX_LM3S102_Rowley/hw_include/debug.h +++ /dev/null @@ -1,56 +0,0 @@ -//***************************************************************************** -// -// debug.h - Macros for assisting debug of the driver library. -// -// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 523 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __DEBUG_H__ -#define __DEBUG_H__ - -//***************************************************************************** -// -// Prototype for the function that is called when an invalid argument is passed -// to an API. This is only used when doing a DEBUG build. -// -//***************************************************************************** -extern void __error__(char *pcFilename, unsigned long ulLine); - -//***************************************************************************** -// -// The ASSERT macro, which does the actual assertion checking. Typically, this -// will be for procedure arguments. -// -//***************************************************************************** -#ifdef DEBUG -#define ASSERT(expr) { \ - if(!(expr)) \ - { \ - __error__(__FILE__, __LINE__); \ - } \ - } -#else -#define ASSERT(expr) -#endif - -#endif // __DEBUG_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/flash.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/flash.h deleted file mode 100644 index 633254874..000000000 --- a/Demo/CORTEX_LM3S102_Rowley/hw_include/flash.h +++ /dev/null @@ -1,75 +0,0 @@ -//***************************************************************************** -// -// flash.h - Prototypes for the flash driver. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 523 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __FLASH_H__ -#define __FLASH_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to FlashProtectSet(), and returned by -// FlashProtectGet(). -// -//***************************************************************************** -typedef enum -{ - FlashReadWrite, // Flash can be read and written - FlashReadOnly, // Flash can only be read - FlashExecuteOnly // Flash can only be executed -} -tFlashProtection; - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern unsigned long FlashUsecGet(void); -extern void FlashUsecSet(unsigned long ulClocks); -extern long FlashErase(unsigned long ulAddress); -extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress, - unsigned long ulCount); -extern tFlashProtection FlashProtectGet(unsigned long ulAddress); -extern long FlashProtectSet(unsigned long ulAddress, - tFlashProtection eProtect); -extern long FlashProtectSave(void); -extern void FlashIntRegister(void (*pfnHandler)(void)); -extern void FlashIntUnregister(void); -extern void FlashIntEnable(unsigned long ulIntFlags); -extern void FlashIntDisable(unsigned long ulIntFlags); -extern unsigned long FlashIntGetStatus(tBoolean bMasked); -extern void FlashIntClear(unsigned long ulIntFlags); - -#ifdef __cplusplus -} -#endif - -#endif // __FLASH_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/gpio.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/gpio.h deleted file mode 100644 index cdc9a5b19..000000000 --- a/Demo/CORTEX_LM3S102_Rowley/hw_include/gpio.h +++ /dev/null @@ -1,135 +0,0 @@ -//***************************************************************************** -// -// gpio.h - Defines and Macros for GPIO API. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 523 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __GPIO_H__ -#define __GPIO_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following values define the bit field for the ucPins argument to several -// of the APIs. -// -//***************************************************************************** -#define GPIO_PIN_0 0x00000001 // GPIO pin 0 -#define GPIO_PIN_1 0x00000002 // GPIO pin 1 -#define GPIO_PIN_2 0x00000004 // GPIO pin 2 -#define GPIO_PIN_3 0x00000008 // GPIO pin 3 -#define GPIO_PIN_4 0x00000010 // GPIO pin 4 -#define GPIO_PIN_5 0x00000020 // GPIO pin 5 -#define GPIO_PIN_6 0x00000040 // GPIO pin 6 -#define GPIO_PIN_7 0x00000080 // GPIO pin 7 - -//***************************************************************************** -// -// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and -// returned from GPIODirModeGet. -// -//***************************************************************************** -#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input -#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output -#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function - -//***************************************************************************** -// -// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and -// returned from GPIOIntTypeGet. -// -//***************************************************************************** -#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge -#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge -#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges -#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level -#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level - -//***************************************************************************** -// -// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter, -// and returned by GPIOPadConfigGet in the *pulStrength parameter. -// -//***************************************************************************** -#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength -#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength -#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength -#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control - -//***************************************************************************** -// -// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter, -// and returned by GPIOPadConfigGet in the *pulPadType parameter. -// -//***************************************************************************** -#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull -#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up -#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down -#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain -#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up -#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down -#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulPinIO); -extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin); -extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulIntType); -extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin); -extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulStrength, - unsigned long ulPadType); -extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin, - unsigned long *pulStrength, - unsigned long *pulPadType); -extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins); -extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked); -extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPortIntRegister(unsigned long ulPort, - void (*pfIntHandler)(void)); -extern void GPIOPortIntUnregister(unsigned long ulPort); -extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, - unsigned char ucVal); -extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins); - -#ifdef __cplusplus -} -#endif - -#endif // __GPIO_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_comp.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_comp.h deleted file mode 100644 index 81fb0b064..000000000 --- a/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_comp.h +++ /dev/null @@ -1,113 +0,0 @@ -//***************************************************************************** -// -// hw_comp.h - Macros used when accessing the comparator hardware. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 523 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_COMP_H__ -#define __HW_COMP_H__ - -//***************************************************************************** -// -// The following define the offsets of the comparator registers. -// -//***************************************************************************** -#define COMP_O_MIS 0x00000000 // Interrupt status register -#define COMP_O_RIS 0x00000004 // Raw interrupt status register -#define COMP_O_INTEN 0x00000008 // Interrupt enable register -#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg. -#define COMP_O_ACSTAT0 0x00000020 // Comp0 status register -#define COMP_O_ACCTL0 0x00000024 // Comp0 control register -#define COMP_O_ACSTAT1 0x00000040 // Comp1 status register -#define COMP_O_ACCTL1 0x00000044 // Comp1 control register - -//***************************************************************************** -// -// The following define the bit fields in the COMP_MIS, COMP_RIS, and -// COMP_INTEN registers. -// -//***************************************************************************** -#define COMP_INT_1 0x00000002 // Comp1 interrupt -#define COMP_INT_0 0x00000001 // Comp0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the COMP_REFCTL register. -// -//***************************************************************************** -#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable -#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range -#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask -#define COMP_REFCTL_VREF_SHIFT 0 - -//***************************************************************************** -// -// The following define the bit fields in the COMP_ACSTAT0 and COMP_ACSTAT1 -// registers. -// -//***************************************************************************** -#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value - -//***************************************************************************** -// -// The following define the bit fields in the COMP_ACCTL0 and COMP_ACCTL1 -// registers. -// -//***************************************************************************** -#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable -#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask -#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin -#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin -#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference -#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved -#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable -#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select -#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask -#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense -#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge -#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge -#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges -#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select -#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask -#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense -#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge -#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge -#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges -#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert - -//***************************************************************************** -// -// The following define the reset values for the comparator registers. -// -//***************************************************************************** -#define COMP_RV_MIS 0x00000000 // Interrupt status register -#define COMP_RV_RIS 0x00000000 // Raw interrupt status register -#define COMP_RV_INTEN 0x00000000 // Interrupt enable register -#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg. -#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register -#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register -#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register -#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register - -#endif // __HW_COMP_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_flash.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_flash.h deleted file mode 100644 index 8dd755c2b..000000000 --- a/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_flash.h +++ /dev/null @@ -1,141 +0,0 @@ -//***************************************************************************** -// -// hw_flash.h - Macros used when accessing the flash controller. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 523 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_FLASH_H__ -#define __HW_FLASH_H__ - -//***************************************************************************** -// -// The following define the offsets of the FLASH registers. -// -//***************************************************************************** -#define FLASH_FMA 0x400FD000 // Memory address register -#define FLASH_FMD 0x400FD004 // Memory data register -#define FLASH_FMC 0x400FD008 // Memory control register -#define FLASH_FCRIS 0x400FD00c // Raw interrupt status register -#define FLASH_FCIM 0x400FD010 // Interrupt mask register -#define FLASH_FCMISC 0x400FD014 // Interrupt status register -#define FLASH_FMPRE 0x400FE130 // FLASH read protect register -#define FLASH_FMPPE 0x400FE134 // FLASH program protect register -#define FLASH_USECRL 0x400FE140 // uSec reload register - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FMC register. -// -//***************************************************************************** -#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask -#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key -#define FLASH_FMC_REG_MASK 0x00000F00 // Register select mask -#define FLASH_FMC_REG_UDFP 0x00000000 // Select FLASH protection register -#define FLASH_FMC_COMT 0x00000008 // Commit user register -#define FLASH_FMC_MERASE 0x00000004 // Mass erase FLASH -#define FLASH_FMC_ERASE 0x00000002 // Erase FLASH page -#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FCRIS register. -// -//***************************************************************************** -#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status -#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FCIM register. -// -//***************************************************************************** -#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask -#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FMIS register. -// -//***************************************************************************** -#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status -#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FMPRE and FLASH_FMPPE -// registers. -// -//***************************************************************************** -#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31 -#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30 -#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29 -#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28 -#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27 -#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26 -#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25 -#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24 -#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23 -#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22 -#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21 -#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20 -#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19 -#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18 -#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17 -#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16 -#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15 -#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14 -#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13 -#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12 -#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11 -#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10 -#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9 -#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8 -#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7 -#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6 -#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5 -#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4 -#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3 -#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2 -#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1 -#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0 - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_USECRL register. -// -//***************************************************************************** -#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec -#define FLASH_USECRL_SHIFT 0 - -//***************************************************************************** -// -// The erase size is the size of the FLASH block that is erased by an erase -// operation, and the protect size is the size of the FLASH block that is -// protected by each protection register. -// -//***************************************************************************** -#define FLASH_ERASE_SIZE 0x00000400 -#define FLASH_PROTECT_SIZE 0x00000800 - -#endif // __HW_FLASH_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_gpio.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_gpio.h deleted file mode 100644 index ddba2fd9d..000000000 --- a/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_gpio.h +++ /dev/null @@ -1,95 +0,0 @@ -//***************************************************************************** -// -// hw_gpio.h - Defines and Macros for GPIO hardware. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 523 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_GPIO_H__ -#define __HW_GPIO_H__ - -//***************************************************************************** -// -// GPIO Register Offsets. -// -//***************************************************************************** -#define GPIO_O_DATA 0x00000000 // Data register. -#define GPIO_O_DIR 0x00000400 // Data direction register. -#define GPIO_O_IS 0x00000404 // Interrupt sense register. -#define GPIO_O_IBE 0x00000408 // Interrupt both edges register. -#define GPIO_O_IEV 0x0000040C // Intterupt event register. -#define GPIO_O_IM 0x00000410 // Interrupt mask register. -#define GPIO_O_RIS 0x00000414 // Raw interrupt status register. -#define GPIO_O_MIS 0x00000418 // Masked interrupt status reg. -#define GPIO_O_ICR 0x0000041C // Interrupt clear register. -#define GPIO_O_AFSEL 0x00000420 // Mode control select register. -#define GPIO_O_DR2R 0x00000500 // 2ma drive select register. -#define GPIO_O_DR4R 0x00000504 // 4ma drive select register. -#define GPIO_O_DR8R 0x00000508 // 8ma drive select register. -#define GPIO_O_ODR 0x0000050C // Open drain select register. -#define GPIO_O_PUR 0x00000510 // Pull up select register. -#define GPIO_O_PDR 0x00000514 // Pull down select register. -#define GPIO_O_SLR 0x00000518 // Slew rate control enable reg. -#define GPIO_O_DEN 0x0000051C // Digital input enable register. -#define GPIO_O_PeriphID0 0x00000FE0 // -#define GPIO_O_PeriphID1 0x00000FE4 // -#define GPIO_O_PeriphID2 0x00000FE8 // -#define GPIO_O_PeriphID3 0x00000FEC // -#define GPIO_O_PCellID0 0x00000FF0 // -#define GPIO_O_PCellID1 0x00000FF4 // -#define GPIO_O_PCellID2 0x00000FF8 // -#define GPIO_O_PCellID3 0x00000FFC // - -//***************************************************************************** -// -// GPIO Register reset values. -// -//***************************************************************************** -#define GPIO_RV_DATA 0x00000000 // Data register reset value. -#define GPIO_RV_DIR 0x00000000 // Data direction reg RV. -#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV. -#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV. -#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV. -#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV. -#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV. -#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV. -#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV. -#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV. -#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV. -#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV. -#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV. -#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV. -#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV. -#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV. -#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV. -#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV. -#define GPIO_RV_PeriphID0 0x00000061 // -#define GPIO_RV_PeriphID1 0x00000010 // -#define GPIO_RV_PeriphID2 0x00000004 // -#define GPIO_RV_PeriphID3 0x00000000 // -#define GPIO_RV_PCellID0 0x0000000D // -#define GPIO_RV_PCellID1 0x000000F0 // -#define GPIO_RV_PCellID2 0x00000005 // -#define GPIO_RV_PCellID3 0x000000B1 // - -#endif // __HW_GPIO_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_i2c.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_i2c.h deleted file mode 100644 index 3e2e9ee93..000000000 --- a/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_i2c.h +++ /dev/null @@ -1,157 +0,0 @@ -//***************************************************************************** -// -// hw_i2c.h - Macros used when accessing the I2C master and slave hardware. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 523 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_I2C_H__ -#define __HW_I2C_H__ - -//***************************************************************************** -// -// The following define the offsets of the I2C master registers. -// -//***************************************************************************** -#define I2C_MASTER_O_SA 0x00000000 // Slave address register -#define I2C_MASTER_O_CS 0x00000004 // Control and Status register -#define I2C_MASTER_O_DR 0x00000008 // Data register -#define I2C_MASTER_O_TPR 0x0000000C // Timer period register -#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register -#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register -#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg -#define I2C_MASTER_O_ICR 0x0000001c // Interrupt clear register -#define I2C_MASTER_O_CR 0x00000020 // Configuration register - -//***************************************************************************** -// -// The following define the offsets of the I2C slave registers. -// -//***************************************************************************** -#define I2C_SLAVE_O_OAR 0x00000000 // Own address register -#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register -#define I2C_SLAVE_O_DR 0x00000008 // Data register -#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register -#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register -#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg -#define I2C_SLAVE_O_ICR 0x00000018 // Interrupt clear register - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Control and Status -// register. -// -//***************************************************************************** -#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde -#define I2C_MASTER_CS_STOP 0x00000004 // Stop -#define I2C_MASTER_CS_START 0x00000002 // Start -#define I2C_MASTER_CS_RUN 0x00000001 // Run -#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy -#define I2C_MASTER_CS_IDLE 0x00000020 // Idle -#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration -#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged -#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged -#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred -#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data -#define I2C_MASTER_CS_ERR_MASK 0x0000001C - -//***************************************************************************** -// -// The following define values used in determining the contents of the I2C -// Master Timer Period register. -// -//***************************************************************************** -#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period -#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period -#define I2C_SCL_STANDARD 100000 // SCL standard frequency -#define I2C_SCL_FAST 400000 // SCL fast frequency - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Interrupt Mask -// register. -// -//***************************************************************************** -#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Raw Interrupt Status -// register. -// -//***************************************************************************** -#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Masked Interrupt -// Status register. -// -//***************************************************************************** -#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Configuration -// register. -// -//***************************************************************************** -#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable -#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable -#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Control/Status -// register. -// -//***************************************************************************** -#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device -#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received -#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Interrupt Mask -// register. -// -//***************************************************************************** -#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Raw Interrupt Status -// register. -// -//***************************************************************************** -#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Masked Interrupt -// Status register. -// -//***************************************************************************** -#define I2C_SLAVE_MIS_MIS 0x00000001 // Master masked interrupt status - -#endif // __HW_I2C_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_ints.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_ints.h deleted file mode 100644 index d32cec40b..000000000 --- a/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_ints.h +++ /dev/null @@ -1,82 +0,0 @@ -//***************************************************************************** -// -// hw_ints.h - Macros that define the interrupt assignment on Stellaris. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 523 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_INTS_H__ -#define __HW_INTS_H__ - -//***************************************************************************** -// -// The following define the fault assignments. -// -//***************************************************************************** -#define FAULT_NMI 2 // NMI fault -#define FAULT_HARD 3 // Hard fault -#define FAULT_MPU 4 // MPU fault -#define FAULT_BUS 5 // Bus fault -#define FAULT_USAGE 6 // Usage fault -#define FAULT_SVCALL 11 // SVCall -#define FAULT_DEBUG 12 // Debug monitor -#define FAULT_PENDSV 14 // PendSV -#define FAULT_SYSTICK 15 // System Tick - -//***************************************************************************** -// -// The following define the interrupt assignments. -// -//***************************************************************************** -#define INT_GPIOA 16 // GPIO Port A -#define INT_GPIOB 17 // GPIO Port B -#define INT_GPIOC 18 // GPIO Port C -#define INT_UART0 21 // UART0 Rx and Tx -#define INT_SSI 23 // SSI Rx and Tx -#define INT_I2C 24 // I2C Master and Slave -#define INT_WATCHDOG 34 // Watchdog timer -#define INT_TIMER0A 35 // Timer 0 subtimer A -#define INT_TIMER0B 36 // Timer 0 subtimer B -#define INT_TIMER1A 37 // Timer 1 subtimer A -#define INT_TIMER1B 38 // Timer 1 subtimer B -#define INT_COMP0 41 // Analog Comparator 0 -#define INT_COMP1 42 // Analog Comparator 1 -#define INT_SYSCTL 44 // System Control (PLL, OSC, BO) -#define INT_FLASH 45 // FLASH Control - -//***************************************************************************** -// -// The total number of interrupts. -// -//***************************************************************************** -#define NUM_INTERRUPTS 46 - -//***************************************************************************** -// -// The total number of priority levels. -// -//***************************************************************************** -#define NUM_PRIORITY 8 -#define NUM_PRIORITY_BITS 3 - -#endif // __HW_INTS_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_memmap.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_memmap.h deleted file mode 100644 index bef5dc618..000000000 --- a/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_memmap.h +++ /dev/null @@ -1,57 +0,0 @@ -//***************************************************************************** -// -// hw_memmap.h - Macros defining the memory map of Stellaris. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 523 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_MEMMAP_H__ -#define __HW_MEMMAP_H__ - -//***************************************************************************** -// -// The following define the base address of the memories and peripherals. -// -//***************************************************************************** -#define FLASH_BASE 0x00000000 // FLASH memory -#define SRAM_BASE 0x20000000 // SRAM memory -#define WATCHDOG_BASE 0x40000000 // Watchdog -#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A -#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B -#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C -#define SSI_BASE 0x40008000 // SSI -#define UART0_BASE 0x4000C000 // UART0 -#define I2C_MASTER_BASE 0x40020000 // I2C Master -#define I2C_SLAVE_BASE 0x40020800 // I2C Slave -#define TIMER0_BASE 0x40030000 // Timer0 -#define TIMER1_BASE 0x40031000 // Timer1 -#define COMP_BASE 0x4003C000 // Analog comparators -#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller -#define SYSCTL_BASE 0x400FE000 // System Control -#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell -#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace -#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint -#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl -#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit - -#endif // __HW_MEMMAP_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_nvic.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_nvic.h deleted file mode 100644 index 77dfe716a..000000000 --- a/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_nvic.h +++ /dev/null @@ -1,830 +0,0 @@ -//***************************************************************************** -// -// hw_nvic.h - Macros used when accessing the NVIC hardware. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 523 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_NVIC_H__ -#define __HW_NVIC_H__ - -//***************************************************************************** -// -// The following define the addresses of the NVIC registers. -// -//***************************************************************************** -#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg. -#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg. -#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register -#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register -#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg. -#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register -#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg. -#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register -#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg. -#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register -#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register -#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register -#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register -#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register -#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register -#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register -#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register -#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register -#define NVIC_CPUID 0xE000ED00 // CPUID Base Register -#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register -#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register -#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg. -#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register -#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register -#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority -#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority -#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority -#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State -#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg. -#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register -#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register -#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register -#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register -#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register -#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register -#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register -#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register -#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg. -#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg. -#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select -#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data -#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control -#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg. - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_INT_TYPE register. -// -//***************************************************************************** -#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) -#define NVIC_INT_TYPE_LINES_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_CTRL register. -// -//***************************************************************************** -#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag -#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source -#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable -#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_RELOAD register. -// -//***************************************************************************** -#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value -#define NVIC_ST_RELOAD_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_CURRENT register. -// -//***************************************************************************** -#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value -#define NVIC_ST_CURRENT_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_CAL register. -// -//***************************************************************************** -#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock -#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew -#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value -#define NVIC_ST_CAL_ONEMS_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_EN0 register. -// -//***************************************************************************** -#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable -#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable -#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable -#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable -#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable -#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable -#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable -#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable -#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable -#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable -#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable -#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable -#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable -#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable -#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable -#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable -#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable -#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable -#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable -#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable -#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable -#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable -#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable -#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable -#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable -#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable -#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable -#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable -#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable -#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable -#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable -#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DIS0 register. -// -//***************************************************************************** -#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable -#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable -#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable -#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable -#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable -#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable -#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable -#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable -#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable -#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable -#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable -#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable -#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable -#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable -#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable -#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable -#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable -#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable -#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable -#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable -#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable -#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable -#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable -#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable -#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable -#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable -#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable -#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable -#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable -#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable -#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable -#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PEND0 register. -// -//***************************************************************************** -#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend -#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend -#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend -#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend -#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend -#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend -#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend -#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend -#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend -#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend -#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend -#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend -#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend -#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend -#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend -#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend -#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend -#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend -#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend -#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend -#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend -#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend -#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend -#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend -#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend -#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend -#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend -#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend -#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend -#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend -#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend -#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_UNPEND0 register. -// -//***************************************************************************** -#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend -#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend -#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend -#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend -#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend -#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend -#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend -#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend -#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend -#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend -#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend -#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend -#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend -#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend -#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend -#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend -#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend -#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend -#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend -#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend -#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend -#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend -#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend -#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend -#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend -#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend -#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend -#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend -#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend -#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend -#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend -#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ACTIVE0 register. -// -//***************************************************************************** -#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active -#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active -#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active -#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active -#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active -#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active -#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active -#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active -#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active -#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active -#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active -#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active -#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active -#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active -#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active -#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active -#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active -#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active -#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active -#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active -#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active -#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active -#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active -#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active -#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active -#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active -#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active -#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active -#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active -#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active -#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active -#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI0 register. -// -//***************************************************************************** -#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask -#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask -#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask -#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask -#define NVIC_PRI0_INT3_S 24 -#define NVIC_PRI0_INT2_S 16 -#define NVIC_PRI0_INT1_S 8 -#define NVIC_PRI0_INT0_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI1 register. -// -//***************************************************************************** -#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask -#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask -#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask -#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask -#define NVIC_PRI1_INT7_S 24 -#define NVIC_PRI1_INT6_S 16 -#define NVIC_PRI1_INT5_S 8 -#define NVIC_PRI1_INT4_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI2 register. -// -//***************************************************************************** -#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask -#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask -#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask -#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask -#define NVIC_PRI2_INT11_S 24 -#define NVIC_PRI2_INT10_S 16 -#define NVIC_PRI2_INT9_S 8 -#define NVIC_PRI2_INT8_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI3 register. -// -//***************************************************************************** -#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask -#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask -#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask -#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask -#define NVIC_PRI3_INT15_S 24 -#define NVIC_PRI3_INT14_S 16 -#define NVIC_PRI3_INT13_S 8 -#define NVIC_PRI3_INT12_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI4 register. -// -//***************************************************************************** -#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask -#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask -#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask -#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask -#define NVIC_PRI4_INT19_S 24 -#define NVIC_PRI4_INT18_S 16 -#define NVIC_PRI4_INT17_S 8 -#define NVIC_PRI4_INT16_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI5 register. -// -//***************************************************************************** -#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask -#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask -#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask -#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask -#define NVIC_PRI5_INT23_S 24 -#define NVIC_PRI5_INT22_S 16 -#define NVIC_PRI5_INT21_S 8 -#define NVIC_PRI5_INT20_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI6 register. -// -//***************************************************************************** -#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask -#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask -#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask -#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask -#define NVIC_PRI6_INT27_S 24 -#define NVIC_PRI6_INT26_S 16 -#define NVIC_PRI6_INT25_S 8 -#define NVIC_PRI6_INT24_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI7 register. -// -//***************************************************************************** -#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask -#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask -#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask -#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask -#define NVIC_PRI7_INT31_S 24 -#define NVIC_PRI7_INT30_S 16 -#define NVIC_PRI7_INT29_S 8 -#define NVIC_PRI7_INT28_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_CPUID register. -// -//***************************************************************************** -#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer -#define NVIC_CPUID_VAR_M 0x00F00000 // Variant -#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number -#define NVIC_CPUID_REV_M 0x0000000F // Revision - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_INT_CTRL register. -// -//***************************************************************************** -#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI -#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV -#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV -#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling -#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending -#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception -#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base -#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception -#define NVIC_INT_CTRL_VEC_PEN_S 12 -#define NVIC_INT_CTRL_VEC_ACT_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_VTABLE register. -// -//***************************************************************************** -#define NVIC_VTABLE_BASE 0x20000000 // Vector table base -#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset -#define NVIC_VTABLE_OFFSET_S 8 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_APINT register. -// -//***************************************************************************** -#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask -#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key -#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess -#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group -#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split -#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split -#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split -#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split -#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split -#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split -#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split -#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split -#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request -#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info -#define NVIC_APINT_VECT_RESET 0x00000001 // System reset - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_CTRL register. -// -//***************************************************************************** -#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend -#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable -#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_CFG_CTRL register. -// -//***************************************************************************** -#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault -#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0 -#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access -#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger -#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger -#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_PRI1 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler -#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler -#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler -#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler -#define NVIC_SYS_PRI1_USAGE_S 16 -#define NVIC_SYS_PRI1_BUS_S 8 -#define NVIC_SYS_PRI1_MEM_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_PRI2 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler -#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers -#define NVIC_SYS_PRI2_SVC_S 24 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_PRI3 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler -#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler -#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler -#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler -#define NVIC_SYS_PRI3_TICK_S 24 -#define NVIC_SYS_PRI3_PENDSV_S 16 -#define NVIC_SYS_PRI3_DEBUG_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_HND_CTRL register. -// -//***************************************************************************** -#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable -#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable -#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable -#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended -#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended -#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active -#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active -#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active -#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active -#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active -#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active -#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_FAULT_STAT register. -// -//***************************************************************************** -#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault -#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault -#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault -#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault -#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault -#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault -#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid -#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault -#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault -#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error -#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error -#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault -#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid -#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation -#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation -#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation -#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_HFAULT_STAT register. -// -//***************************************************************************** -#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event -#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler -#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DEBUG_STAT register. -// -//***************************************************************************** -#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted -#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch -#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match -#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction -#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MM_ADDR register. -// -//***************************************************************************** -#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address -#define NVIC_MM_ADDR_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_FAULT_ADDR register. -// -//***************************************************************************** -#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address -#define NVIC_FAULT_ADDR_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_EXC_STACK register. -// -//***************************************************************************** -#define NVIC_EXC_STACK_DEEP 0x00000001 // Exception stack - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_EXC_NUM register. -// -//***************************************************************************** -#define NVIC_EXC_NUM_M 0x000003FF // Exception number -#define NVIC_EXC_NUM_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_COPRO register. -// -//***************************************************************************** -#define NVIC_COPRO_15_M 0xC0000000 // Coprocessor 15 access mask -#define NVIC_COPRO_15_DENIED 0x00000000 // Coprocessor 15 access denied -#define NVIC_COPRO_15_PRIV 0x40000000 // Coprocessor 15 privileged addess -#define NVIC_COPRO_15_FULL 0xC0000000 // Coprocessor 15 full access -#define NVIC_COPRO_14_M 0x30000000 // Coprocessor 14 access mask -#define NVIC_COPRO_14_DENIED 0x00000000 // Coprocessor 14 access denied -#define NVIC_COPRO_14_PRIV 0x10000000 // Coprocessor 14 privileged addess -#define NVIC_COPRO_14_FULL 0x30000000 // Coprocessor 14 full access -#define NVIC_COPRO_13_M 0x0C000000 // Coprocessor 13 access mask -#define NVIC_COPRO_13_DENIED 0x00000000 // Coprocessor 13 access denied -#define NVIC_COPRO_13_PRIV 0x04000000 // Coprocessor 13 privileged addess -#define NVIC_COPRO_13_FULL 0x0C000000 // Coprocessor 13 full access -#define NVIC_COPRO_12_M 0x03000000 // Coprocessor 12 access mask -#define NVIC_COPRO_12_DENIED 0x00000000 // Coprocessor 12 access denied -#define NVIC_COPRO_12_PRIV 0x01000000 // Coprocessor 12 privileged addess -#define NVIC_COPRO_12_FULL 0x03000000 // Coprocessor 12 full access -#define NVIC_COPRO_11_M 0x00C00000 // Coprocessor 11 access mask -#define NVIC_COPRO_11_DENIED 0x00000000 // Coprocessor 11 access denied -#define NVIC_COPRO_11_PRIV 0x00400000 // Coprocessor 11 privileged addess -#define NVIC_COPRO_11_FULL 0x00C00000 // Coprocessor 11 full access -#define NVIC_COPRO_10_M 0x00300000 // Coprocessor 10 access mask -#define NVIC_COPRO_10_DENIED 0x00000000 // Coprocessor 10 access denied -#define NVIC_COPRO_10_PRIV 0x00100000 // Coprocessor 10 privileged addess -#define NVIC_COPRO_10_FULL 0x00300000 // Coprocessor 10 full access -#define NVIC_COPRO_9_M 0x000C0000 // Coprocessor 9 access mask -#define NVIC_COPRO_9_DENIED 0x00000000 // Coprocessor 9 access denied -#define NVIC_COPRO_9_PRIV 0x00040000 // Coprocessor 9 privileged addess -#define NVIC_COPRO_9_FULL 0x000C0000 // Coprocessor 9 full access -#define NVIC_COPRO_8_M 0x00030000 // Coprocessor 8 access mask -#define NVIC_COPRO_8_DENIED 0x00000000 // Coprocessor 8 access denied -#define NVIC_COPRO_8_PRIV 0x00010000 // Coprocessor 8 privileged addess -#define NVIC_COPRO_8_FULL 0x00030000 // Coprocessor 8 full access -#define NVIC_COPRO_7_M 0x0000C000 // Coprocessor 7 access mask -#define NVIC_COPRO_7_DENIED 0x00000000 // Coprocessor 7 access denied -#define NVIC_COPRO_7_PRIV 0x00004000 // Coprocessor 7 privileged addess -#define NVIC_COPRO_7_FULL 0x0000C000 // Coprocessor 7 full access -#define NVIC_COPRO_6_M 0x00003000 // Coprocessor 6 access mask -#define NVIC_COPRO_6_DENIED 0x00000000 // Coprocessor 6 access denied -#define NVIC_COPRO_6_PRIV 0x00001000 // Coprocessor 6 privileged addess -#define NVIC_COPRO_6_FULL 0x00003000 // Coprocessor 6 full access -#define NVIC_COPRO_5_M 0x00000C00 // Coprocessor 5 access mask -#define NVIC_COPRO_5_DENIED 0x00000000 // Coprocessor 5 access denied -#define NVIC_COPRO_5_PRIV 0x00000400 // Coprocessor 5 privileged addess -#define NVIC_COPRO_5_FULL 0x00000C00 // Coprocessor 5 full access -#define NVIC_COPRO_4_M 0x00000300 // Coprocessor 4 access mask -#define NVIC_COPRO_4_DENIED 0x00000000 // Coprocessor 4 access denied -#define NVIC_COPRO_4_PRIV 0x00000100 // Coprocessor 4 privileged addess -#define NVIC_COPRO_4_FULL 0x00000300 // Coprocessor 4 full access -#define NVIC_COPRO_3_M 0x000000C0 // Coprocessor 3 access mask -#define NVIC_COPRO_3_DENIED 0x00000000 // Coprocessor 3 access denied -#define NVIC_COPRO_3_PRIV 0x00000040 // Coprocessor 3 privileged addess -#define NVIC_COPRO_3_FULL 0x000000C0 // Coprocessor 3 full access -#define NVIC_COPRO_2_M 0x00000030 // Coprocessor 2 access mask -#define NVIC_COPRO_2_DENIED 0x00000000 // Coprocessor 2 access denied -#define NVIC_COPRO_2_PRIV 0x00000010 // Coprocessor 2 privileged addess -#define NVIC_COPRO_2_FULL 0x00000030 // Coprocessor 2 full access -#define NVIC_COPRO_1_M 0x0000000C // Coprocessor 1 access mask -#define NVIC_COPRO_1_DENIED 0x00000000 // Coprocessor 1 access denied -#define NVIC_COPRO_1_PRIV 0x00000004 // Coprocessor 1 privileged addess -#define NVIC_COPRO_1_FULL 0x0000000C // Coprocessor 1 full access -#define NVIC_COPRO_0_M 0x00000003 // Coprocessor 0 access mask -#define NVIC_COPRO_0_DENIED 0x00000000 // Coprocessor 0 access denied -#define NVIC_COPRO_0_PRIV 0x00000001 // Coprocessor 0 privileged addess -#define NVIC_COPRO_0_FULL 0x00000003 // Coprocessor 0 full access - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_TYPE register. -// -//***************************************************************************** -#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions -#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions -#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU -#define NVIC_MPU_TYPE_IREGION_S 16 -#define NVIC_MPU_TYPE_DREGION_S 8 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_CTRL register. -// -//***************************************************************************** -#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults -#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_NUMBER register. -// -//***************************************************************************** -#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access -#define NVIC_MPU_NUMBER_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_BASE register. -// -//***************************************************************************** -#define NVIC_MPU_BASE_ADDR_M 0xFFFFFF00 // Base address -#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid -#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number -#define NVIC_MPU_BASE_ADDR_S 8 -#define NVIC_MPU_BASE_REGION_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_ATTR register. -// -//***************************************************************************** -#define NVIC_MPU_ATTR_ATTRS 0xFFFF0000 // Attributes -#define NVIC_MPU_ATTR_SRD 0x0000FF00 // Sub-region disable -#define NVIC_MPU_ATTR_SZENABLE 0x000000FF // Region size - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_CTRL register. -// -//***************************************************************************** -#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask -#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key -#define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor -#define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request -#define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable -#define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core -#define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping -#define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt -#define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available -#define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up -#define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core -#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping -#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core -#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core -#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_XFER register. -// -//***************************************************************************** -#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read -#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register -#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 -#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 -#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 -#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 -#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 -#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 -#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 -#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 -#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 -#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 -#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 -#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 -#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 -#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 -#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 -#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 -#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register -#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP -#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP -#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP -#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_DATA register. -// -//***************************************************************************** -#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache -#define NVIC_DBG_DATA_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_INT register. -// -//***************************************************************************** -#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault -#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors -#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error -#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state -#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check -#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error -#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault -#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status -#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset -#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending -#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SW_TRIG register. -// -//***************************************************************************** -#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger -#define NVIC_SW_TRIG_INTID_S 0 - -#endif // __HW_NVIC_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_ssi.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_ssi.h deleted file mode 100644 index 37472329f..000000000 --- a/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_ssi.h +++ /dev/null @@ -1,113 +0,0 @@ -//***************************************************************************** -// -// hw_ssi.h - Macros used when accessing the SSI hardware. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 523 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_SSI_H__ -#define __HW_SSI_H__ - -//***************************************************************************** -// -// The following define the offsets of the SSI registers. -// -//***************************************************************************** -#define SSI_O_CR0 0x00000000 // Control register 0 -#define SSI_O_CR1 0x00000004 // Control register 1 -#define SSI_O_DR 0x00000008 // Data register -#define SSI_O_SR 0x0000000C // Status register -#define SSI_O_CPSR 0x00000010 // Clock prescale register -#define SSI_O_IM 0x00000014 // Int mask set and clear register -#define SSI_O_RIS 0x00000018 // Raw interrupt register -#define SSI_O_MIS 0x0000001C // Masked interrupt register -#define SSI_O_ICR 0x00000020 // Interrupt clear register - -//***************************************************************************** -// -// The following define the bit fields in the SSI Control register 0. -// -//***************************************************************************** -#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate -#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase -#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity -#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask -#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format -#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format -#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format -#define SSI_CR0_DSS 0x0000000F // Data size select -#define SSI_CR0_DSS_4 0x00000003 // 4 bit data -#define SSI_CR0_DSS_5 0x00000004 // 5 bit data -#define SSI_CR0_DSS_6 0x00000005 // 6 bit data -#define SSI_CR0_DSS_7 0x00000006 // 7 bit data -#define SSI_CR0_DSS_8 0x00000007 // 8 bit data -#define SSI_CR0_DSS_9 0x00000008 // 9 bit data -#define SSI_CR0_DSS_10 0x00000009 // 10 bit data -#define SSI_CR0_DSS_11 0x0000000A // 11 bit data -#define SSI_CR0_DSS_12 0x0000000B // 12 bit data -#define SSI_CR0_DSS_13 0x0000000C // 13 bit data -#define SSI_CR0_DSS_14 0x0000000D // 14 bit data -#define SSI_CR0_DSS_15 0x0000000E // 15 bit data -#define SSI_CR0_DSS_16 0x0000000F // 16 bit data - -//***************************************************************************** -// -// The following define the bit fields in the SSI Control register 1. -// -//***************************************************************************** -#define SSI_CR1_SOD 0x00000008 // Slave mode output disable -#define SSI_CR1_MS 0x00000004 // Master or slave mode select -#define SSI_CR1_SSE 0x00000002 // Sync serial port enable -#define SSI_CR1_LBM 0x00000001 // Loopback mode - -//***************************************************************************** -// -// The following define the bit fields in the SSI Status register -// -//***************************************************************************** -#define SSI_SR_BSY 0x00000010 // SSI busy -#define SSI_SR_RFF 0x00000008 // RX FIFO full -#define SSI_SR_RNE 0x00000004 // RX FIFO not empty -#define SSI_SR_TNF 0x00000002 // TX FIFO not full -#define SSI_SR_TFE 0x00000001 // TX FIFO empty - -//***************************************************************************** -// -// The following define information concerning the SSI Data register. -// -//***************************************************************************** -#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO -#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO - -//***************************************************************************** -// -// The following define the bit fields in the interrupt mask set and clear, -// raw interrupt, masked interrupt, and interrupt clear registers. -// -//***************************************************************************** -#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt -#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt -#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt -#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt - -#endif // __HW_SSI_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_sysctl.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_sysctl.h deleted file mode 100644 index 044fec21d..000000000 --- a/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_sysctl.h +++ /dev/null @@ -1,325 +0,0 @@ -//***************************************************************************** -// -// hw_sysctl.h - Macros used when accessing the system control hardware. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 523 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_SYSCTL_H__ -#define __HW_SYSCTL_H__ - -//***************************************************************************** -// -// The following define the offsets of the system control registers. -// -//***************************************************************************** -#define SYSCTL_DID0 0x400fe000 // Device identification register 0 -#define SYSCTL_DID1 0x400fe004 // Device identification register 1 -#define SYSCTL_DC0 0x400fe008 // Device capabilities register 0 -#define SYSCTL_DC1 0x400fe010 // Device capabilities register 1 -#define SYSCTL_DC2 0x400fe014 // Device capabilities register 2 -#define SYSCTL_DC3 0x400fe018 // Device capabilities register 3 -#define SYSCTL_DC4 0x400fe01C // Device capabilities register 4 -#define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register -#define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register -#define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0 -#define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1 -#define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2 -#define SYSCTL_RIS 0x400fe050 // Raw interrupt status register -#define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register -#define SYSCTL_MISC 0x400fe058 // Interrupt status register -#define SYSCTL_RESC 0x400fe05c // Reset cause register -#define SYSCTL_RCC 0x400fe060 // Run-mode clock config register -#define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register -#define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0 -#define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1 -#define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2 -#define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0 -#define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1 -#define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2 -#define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0 -#define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1 -#define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2 -#define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register -#define SYSCTL_LDOARST 0x400fe160 // LDO reset control register - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DID0 register. -// -//***************************************************************************** -#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask -#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A -#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B -#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask -#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0 -#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DID1 register. -// -//***************************************************************************** -#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask -#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask -#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family -#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask -#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101 -#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102 -#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask -#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C) -#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C) -#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask -#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC -#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant -#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask -#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified) -#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified) -#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified -#define SYSCTL_DID1_PRTNO_SHIFT 16 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC0 register. -// -//***************************************************************************** -#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask -#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2kB of SRAM -#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask -#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8kB of flash - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC1 register. -// -//***************************************************************************** -#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask -#define SYSCTL_DC1_MPU 0x00000080 // Cortex M3 MPU present -#define SYSCTL_DC1_PLL 0x00000010 // PLL present -#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present -#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present -#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present -#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC2 register. -// -//***************************************************************************** -#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present -#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present -#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present -#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present -#define SYSCTL_DC2_I2C 0x00001000 // I2C present -#define SYSCTL_DC2_SSI 0x00000010 // SSI present -#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC3 register. -// -//***************************************************************************** -#define SYSCTL_DC3_32KHZ 0x80000000 // 32kHz pin present -#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present -#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present -#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present -#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present -#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present -#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC4 register. -// -//***************************************************************************** -#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present -#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present -#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_PBORCTL register. -// -//***************************************************************************** -#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer -#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset -#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise -#define SYSCTL_PBORCTL_BOR_SH 2 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_LDOPCTL register. -// -//***************************************************************************** -#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask -#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V -#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V -#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V -#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V -#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V -#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V -#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V -#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V -#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V -#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V -#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0, -// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers. -// -//***************************************************************************** -#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1, -// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers. -// -//***************************************************************************** -#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1 -#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0 -#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1 -#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0 -#define SYSCTL_SET1_I2C 0x00001000 // I2C module -#define SYSCTL_SET1_SSI 0x00000010 // SSI module -#define SYSCTL_SET1_UART0 0x00000001 // UART module 0 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2, -// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers. -// -//***************************************************************************** -#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module -#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module -#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and -// SYSCTL_IMS registers. -// -//***************************************************************************** -#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt -#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt -#define SYSCTL_INT_BOSC_FAIL 0x00000010 // Boot oscillator failure int -#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int -#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt -#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt -#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_RESC register. -// -//***************************************************************************** -#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset -#define SYSCTL_RESC_SW 0x00000010 // Software reset -#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset -#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset -#define SYSCTL_RESC_POR 0x00000002 // Power on reset -#define SYSCTL_RESC_EXT 0x00000001 // External reset - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_RCC register. -// -//***************************************************************************** -#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating -#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider -#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2 -#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3 -#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4 -#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5 -#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6 -#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7 -#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8 -#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9 -#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10 -#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11 -#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12 -#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13 -#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14 -#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15 -#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16 -#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider -#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down -#define SYSCTL_RCC_OE 0x00001000 // PLL output enable -#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass -#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable -#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc -#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal -#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864MHz crystal -#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4MHz crystal -#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal -#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal -#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal -#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal -#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal -#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal -#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal -#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal -#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal -#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select -#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator -#define SYSCTL_RCC_OSCSRC_BOOT 0x00000010 // Use the boot oscillator -#define SYSCTL_RCC_OSCSRC_BOOT4 0x00000020 // Use the boot oscillator / 4 -#define SYSCTL_RCC_BOSCVER 0x00000008 // Boot osc. verification timer en -#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en -#define SYSCTL_RCC_BOSCDIS 0x00000002 // Boot oscillator disable -#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable -#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field -#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field -#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_PLLCFG register. -// -//***************************************************************************** -#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider -#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1 -#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2 -#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4 -#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier -#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider -#define SYSCTL_PLLCFG_F_SHIFT 5 -#define SYSCTL_PLLCFG_R_SHIFT 0 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_CLKVCLR register. -// -//***************************************************************************** -#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_LDOARST register. -// -//***************************************************************************** -#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device - -#endif // __HW_SYSCTL_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_timer.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_timer.h deleted file mode 100644 index 9bad906b2..000000000 --- a/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_timer.h +++ /dev/null @@ -1,233 +0,0 @@ -//***************************************************************************** -// -// hw_timer.h - Defines and macros used when accessing the timer. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 523 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_TIMER_H__ -#define __HW_TIMER_H__ - -//***************************************************************************** -// -// The following define the offsets of the timer registers. -// -//***************************************************************************** -#define TIMER_O_CFG 0x00000000 // Configuration register -#define TIMER_O_TAMR 0x00000004 // TimerA mode register -#define TIMER_O_TBMR 0x00000008 // TimerB mode register -#define TIMER_O_CTL 0x0000000C // Control register -#define TIMER_O_IMR 0x00000018 // Interrupt mask register -#define TIMER_O_RIS 0x0000001C // Interrupt status register -#define TIMER_O_MIS 0x00000020 // Masked interrupt status reg. -#define TIMER_O_ICR 0x00000024 // Interrupt clear register -#define TIMER_O_TAILR 0x00000028 // TimerA interval load register -#define TIMER_O_TBILR 0x0000002C // TimerB interval load register -#define TIMER_O_TAMATCHR 0x00000030 // TimerA match register -#define TIMER_O_TBMATCHR 0x00000034 // TimerB match register -#define TIMER_O_TAPR 0x00000038 // TimerA prescale register -#define TIMER_O_TBPR 0x0000003C // TimerB prescale register -#define TIMER_O_TAPMR 0x00000040 // TimerA prescale match register -#define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register -#define TIMER_O_TAR 0x00000048 // TimerA register -#define TIMER_O_TBR 0x0000004C // TimerB register - -//***************************************************************************** -// -// The following define the reset values of the timer registers. -// -//***************************************************************************** -#define TIMER_RV_CFG 0x00000000 // Configuration register RV -#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV -#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV -#define TIMER_RV_CTL 0x00000000 // Control register RV -#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV -#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV -#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV -#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV -#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV -#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV -#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV -#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV -#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV -#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV -#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV -#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV -#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV -#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_CFG register. -// -//***************************************************************************** -#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask -#define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers -#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC -#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_TnMR register. -// -//***************************************************************************** -#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select -#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time -#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask -#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture -#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic -#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_CTL register. -// -//***************************************************************************** -#define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert -#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask -#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges -#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge -#define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge -#define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable -#define TIMER_CTL_TBEN 0x00000100 // TimerB enable -#define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert -#define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable -#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask -#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges -#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge -#define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge -#define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable -#define TIMER_CTL_TAEN 0x00000001 // TimerA enable - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_IMR register. -// -//***************************************************************************** -#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask -#define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask -#define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask -#define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask -#define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask -#define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask -#define TIMER_IMR_TATOIM 0x00000001 // TimerA time out interrupt mask - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_RIS register. -// -//***************************************************************************** -#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status -#define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status -#define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status -#define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status -#define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status -#define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status -#define TIMER_RIS_TATORIS 0x00000001 // TimerA time out raw int status - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_MIS register. -// -//***************************************************************************** -#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status -#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status -#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat -#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status -#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status -#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status -#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_ICR register. -// -//***************************************************************************** -#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear -#define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear -#define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear -#define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear -#define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear -#define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear -#define TIMER_ICR_TATOCINT 0x00000001 // TimerA time out interrupt clear - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_TAILR register. -// -//***************************************************************************** -#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode -#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TBILR register. -// -//***************************************************************************** -#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_TAMATCHR register. -// -//***************************************************************************** -#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode -#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TBMATCHR register. -// -//***************************************************************************** -#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TnPR register. -// -//***************************************************************************** -#define TIMER_TNPR_TNPSR 0x0000000F // TimerN prescale value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TnPMR register. -// -//***************************************************************************** -#define TIMER_TNPMR_TNPSMR 0x0000000F // TimerN prescale match value - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_TAR register. -// -//***************************************************************************** -#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode -#define TIMER_TAR_TARL 0x0000FFFF // TimerA value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TBR register. -// -//***************************************************************************** -#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value - -#endif // __HW_TIMER_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_types.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_types.h deleted file mode 100644 index a944f6662..000000000 --- a/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_types.h +++ /dev/null @@ -1,63 +0,0 @@ -//***************************************************************************** -// -// hw_types.h - Common types and macros. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 523 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_TYPES_H__ -#define __HW_TYPES_H__ - -//***************************************************************************** -// -// Define a boolean type, and values for true and false. -// -//***************************************************************************** -typedef unsigned char tBoolean; - -#ifndef true -#define true 1 -#endif - -#ifndef false -#define false 0 -#endif - -//***************************************************************************** -// -// Macros for hardware access, both direct and via the bit-band region. -// -//***************************************************************************** -#define HWREG(x) \ - (*((volatile unsigned long *)(x))) -#define HWREGBITW(x, b) \ - HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) -#define HWREGBITH(x, b) \ - HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) -#define HWREGBITB(x, b) \ - HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) - -#endif // __HW_TYPES_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_uart.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_uart.h deleted file mode 100644 index 40b6ab2a6..000000000 --- a/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_uart.h +++ /dev/null @@ -1,234 +0,0 @@ -//***************************************************************************** -// -// hw_uart.h - Macros and defines used when accessing the UART hardware -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 523 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_UART_H__ -#define __HW_UART_H__ - -//***************************************************************************** -// -// UART Register Offsets. -// -//***************************************************************************** -#define UART_O_DR 0x00000000 // Data Register -#define UART_O_RSR 0x00000004 // Receive Status Register (read) -#define UART_O_ECR 0x00000004 // Error Clear Register (write) -#define UART_O_FR 0x00000018 // Flag Register (read only) -#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg -#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg -#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte -#define UART_O_CTL 0x00000030 // Control Register -#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg -#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg -#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register -#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register -#define UART_O_ICR 0x00000044 // Interrupt Clear Register - -//***************************************************************************** -// -// Data Register bits -// -//***************************************************************************** -#define UART_DR_OE 0x00000800 // Overrun Error -#define UART_DR_BE 0x00000400 // Break Error -#define UART_DR_PE 0x00000200 // Parity Error -#define UART_DR_FE 0x00000100 // Framing Error - -//***************************************************************************** -// -// Receive Status Register bits -// -//***************************************************************************** -#define UART_RSR_OE 0x00000008 // Overrun Error -#define UART_RSR_BE 0x00000004 // Break Error -#define UART_RSR_PE 0x00000002 // Parity Error -#define UART_RSR_FE 0x00000001 // Framing Error - -//***************************************************************************** -// -// Flag Register bits -// -//***************************************************************************** -#define UART_FR_RI 0x100 // Ring Indicator -#define UART_FR_TXFE 0x080 // TX FIFO Empty -#define UART_FR_RXFF 0x040 // RX FIFO Full -#define UART_FR_TXFF 0x020 // TX FIFO Full -#define UART_FR_RXFE 0x010 // RX FIFO Empty -#define UART_FR_BUSY 0x008 // UART Busy - -//***************************************************************************** -// -// Line Control Register High bits -// -//***************************************************************************** -#define UART_LCR_H_SPS 0x80 // Stick Parity Select -#define UART_LCR_H_WLEN 0x60 // Word length -#define UART_LCR_H_WLEN_8 0x60 // 8 bit data -#define UART_LCR_H_WLEN_7 0x40 // 7 bit data -#define UART_LCR_H_WLEN_6 0x20 // 6 bit data -#define UART_LCR_H_WLEN_5 0x00 // 5 bit data -#define UART_LCR_H_FEN 0x10 // Enable FIFO -#define UART_LCR_H_STP2 0x08 // Two Stop Bits Select -#define UART_LCR_H_EPS 0x04 // Even Parity Select -#define UART_LCR_H_PEN 0x02 // Parity Enable -#define UART_LCR_H_BRK 0x01 // Send Break - -//***************************************************************************** -// -// Control Register bits -// -//***************************************************************************** -#define UART_CTL_CTSEN 0x8000 // CTS Hardware Flow Control -#define UART_CTL_RTSEN 0x4000 // RTS Hardware Flow Control -#define UART_CTL_OUT2 0x2000 // OUT2 -#define UART_CTL_OUT1 0x1000 // OUT1 -#define UART_CTL_RTS 0x0800 // Request To Send -#define UART_CTL_DTR 0x0400 // Data Terminal Ready -#define UART_CTL_RXE 0x0200 // Receive Enable -#define UART_CTL_TXE 0x0100 // Transmit Enable -#define UART_CTL_LBE 0x0080 // Loopback Enable -#define UART_CTL_IIRLP 0x0004 // IrDA SIR low power mode -#define UART_CTL_SIREN 0x0002 // SIR Enable -#define UART_CTL_UARTEN 0x0001 // UART Enable - -//***************************************************************************** -// -// Interrupt FIFO Level Select Register bits -// -//***************************************************************************** -#define UART_IFLS_RX1_8 0x00 // 1/8 Full -#define UART_IFLS_RX2_8 0x10 // 1/4 Full -#define UART_IFLS_RX4_8 0x20 // 1/2 Full -#define UART_IFLS_RX6_8 0x30 // 3/4 Full -#define UART_IFLS_RX7_8 0x40 // 7/8 Full -#define UART_IFLS_TX1_8 0x00 // 1/8 Full -#define UART_IFLS_TX2_8 0x01 // 1/4 Full -#define UART_IFLS_TX4_8 0x02 // 1/2 Full -#define UART_IFLS_TX6_8 0x03 // 3/4 Full -#define UART_IFLS_TX7_8 0x04 // 7/8 Full - -//***************************************************************************** -// -// Interrupt Mask Set/Clear Register bits -// -//***************************************************************************** -#define UART_IM_OEIM 0x400 // Overrun Error Interrupt Mask -#define UART_IM_BEIM 0x200 // Break Error Interrupt Mask -#define UART_IM_PEIM 0x100 // Parity Error Interrupt Mask -#define UART_IM_FEIM 0x080 // Framing Error Interrupt Mask -#define UART_IM_RTIM 0x040 // Receive Timeout Interrupt Mask -#define UART_IM_TXIM 0x020 // Transmit Interrupt Mask -#define UART_IM_RXIM 0x010 // Receive Interrupt Mask -#define UART_IM_DSRMIM 0x008 // DSR Interrupt Mask -#define UART_IM_DCDMIM 0x004 // DCD Interrupt Mask -#define UART_IM_CTSMIM 0x002 // CTS Interrupt Mask -#define UART_IM_RIMIM 0x001 // RI Interrupt Mask - -//***************************************************************************** -// -// Raw Interrupt Status Register -// -//***************************************************************************** -#define UART_RIS_OERIS 0x400 // Overrun Error Interrupt Status -#define UART_RIS_BERIS 0x200 // Break Error Interrupt Status -#define UART_RIS_PERIS 0x100 // Parity Error Interrupt Status -#define UART_RIS_FERIS 0x080 // Framing Error Interrupt Status -#define UART_RIS_RTRIS 0x040 // Receive Timeout Interrupt Status -#define UART_RIS_TXRIS 0x020 // Transmit Interrupt Status -#define UART_RIS_RXRIS 0x010 // Receive Interrupt Status -#define UART_RIS_DSRRMIS 0x008 // DSR Interrupt Status -#define UART_RIS_DCDRMIS 0x004 // DCD Interrupt Status -#define UART_RIS_CTSRMIS 0x002 // CTS Interrupt Status -#define UART_RIS_RIRMIS 0x001 // RI Interrupt Status - -//***************************************************************************** -// -// Masked Interrupt Status Register -// -//***************************************************************************** -#define UART_MIS_OEMIS 0x400 // Overrun Error Interrupt Status -#define UART_MIS_BEMIS 0x200 // Break Error Interrupt Status -#define UART_MIS_PEMIS 0x100 // Parity Error Interrupt Status -#define UART_MIS_FEMIS 0x080 // Framing Error Interrupt Status -#define UART_MIS_RTMIS 0x040 // Receive Timeout Interrupt Status -#define UART_MIS_TXMIS 0x020 // Transmit Interrupt Status -#define UART_MIS_RXMIS 0x010 // Receive Interrupt Status -#define UART_MIS_DSRMMIS 0x008 // DSR Interrupt Status -#define UART_MIS_DCDMMIS 0x004 // DCD Interrupt Status -#define UART_MIS_CTSMMIS 0x002 // CTS Interrupt Status -#define UART_MIS_RIMMIS 0x001 // RI Interrupt Status - -//***************************************************************************** -// -// Interrupt Clear Register bits -// -//***************************************************************************** -#define UART_ICR_OEIC 0x200 // Overrun Error Interrupt Clear -#define UART_ICR_BEIC 0x200 // Break Error Interrupt Clear -#define UART_ICR_PEIC 0x200 // Parity Error Interrupt Clear -#define UART_ICR_FEIC 0x200 // Framing Error Interrupt Clear -#define UART_ICR_RTIC 0x200 // Receive Timeout Interrupt Clear -#define UART_ICR_TXIC 0x200 // Transmit Interrupt Clear -#define UART_ICR_RXIC 0x200 // Receive Interrupt Clear -#define UART_ICR_DSRMIC 0x200 // DSR Interrupt Clear -#define UART_ICR_DCDMIC 0x200 // DCD Interrupt Clear -#define UART_ICR_CTSMIC 0x200 // CTS Interrupt Clear -#define UART_ICR_RIMIC 0x200 // RI Interrupt Clear - -//***************************************************************************** -// -// DMA Control Register bits -// -//***************************************************************************** -#define UART_DMACRDMAONERR 0x04 // Disable DMA On Error -#define UART_DMACRTXDMAE 0x02 // Enable Transmit DMA -#define UART_DMACRRXDMAE 0x01 // Enable Receive DMA - -#define UART_RSR_ANY (UART_RSR_OE | \ - UART_RSR_BE | \ - UART_RSR_PE | \ - UART_RSR_FE) - -//***************************************************************************** -// -// Reset Values for UART Registers. -// -//***************************************************************************** -#define UART_RV_DR 0 -#define UART_RV_RSR 0x0 -#define UART_RV_ECR 0 -#define UART_RV_FR 0x90 -#define UART_RV_IBRD 0x0000 -#define UART_RV_FBRD 0x00 -#define UART_RV_LCR_H 0x00 -#define UART_RV_CTL 0x0300 -#define UART_RV_IFLS 0x12 -#define UART_RV_IM 0x000 -#define UART_RV_RIS 0x000 -#define UART_RV_MIS 0x000 -#define UART_RV_ICR 0x000 - -#endif // __HW_UART_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_watchdog.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_watchdog.h deleted file mode 100644 index 6ae5dff54..000000000 --- a/Demo/CORTEX_LM3S102_Rowley/hw_include/hw_watchdog.h +++ /dev/null @@ -1,99 +0,0 @@ -//***************************************************************************** -// -// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 523 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_WATCHDOG_H__ -#define __HW_WATCHDOG_H__ - -//***************************************************************************** -// -// The following define the offsets of the Watchdog Timer registers. -// -//***************************************************************************** -#define WDT_O_LOAD 0x00000000 // Load register -#define WDT_O_VALUE 0x00000004 // Current value register -#define WDT_O_CTL 0x00000008 // Control register -#define WDT_O_ICR 0x0000000C // Interrupt clear register -#define WDT_O_RIS 0x00000010 // Raw interrupt status register -#define WDT_O_MIS 0x00000014 // Masked interrupt status register -#define WDT_O_TEST 0x00000418 // Test register -#define WDT_O_CAUSE 0x0000041C // Cause register -#define WDT_O_LOCK 0x00000C00 // Lock register - -//***************************************************************************** -// -// The following define the bit fields in the WDT_CTL register. -// -//***************************************************************************** -#define WDT_CTL_RESEN 0x00000002 // Enable reset output -#define WDT_CTL_INTEN 0x00000001 // Enable the WDT counter and int - -//***************************************************************************** -// -// The following define the bit fields in the WDT_ISR, WDT_RIS, and WDT_MIS -// registers. -// -//***************************************************************************** -#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired - -//***************************************************************************** -// -// The following define the bit fields in the WDT_TEST register. -// -//***************************************************************************** -#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable -#define WDT_TEST_TEST_EN 0x00000001 // Watchdog timer reset int test - -//***************************************************************************** -// -// The following define the bit fields in the WDT_CAUSE register. -// -//***************************************************************************** -#define WDT_CAUSE_WDR 0x00000002 // Watchdog timer reset occurred -#define WDT_CAUSE_WDI 0x00000001 // Watchdog timer int occurred - -//***************************************************************************** -// -// The following define the bit fields in the WDT_LOCK register. -// -//***************************************************************************** -#define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked -#define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked -#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer - -//***************************************************************************** -// -// The following define the reset values for the WDT registers. -// -//***************************************************************************** -#define WDT_RV_LOAD 0xFFFFFFFF // Load register -#define WDT_RV_VALUE 0xFFFFFFFF // Current value register -#define WDT_RV_CTL 0x00000000 // Control register -#define WDT_RV_RIS 0x00000000 // Raw interrupt status register -#define WDT_RV_MIS 0x00000000 // Masked interrupt status register -#define WDT_RV_LOCK 0x00000000 // Lock register - -#endif // __HW_WATCHDOG_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/i2c.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/i2c.h deleted file mode 100644 index e48c98d87..000000000 --- a/Demo/CORTEX_LM3S102_Rowley/hw_include/i2c.h +++ /dev/null @@ -1,137 +0,0 @@ -//***************************************************************************** -// -// i2c.h - Prototypes for the I2C Driver. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 523 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __I2C_H__ -#define __I2C_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Defines for the API. -// -//***************************************************************************** -//***************************************************************************** -// -// Interrupt defines. -// -//***************************************************************************** -#define I2C_INT_MASTER 0x00000001 -#define I2C_INT_SLAVE 0x00000002 - -//***************************************************************************** -// -// I2C Master commands. -// -//***************************************************************************** -#define I2C_MASTER_CMD_SINGLE_SEND \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_SINGLE_RECEIVE \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_SEND_START \ - (I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_SEND_CONT \ - (I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_SEND_FINISH \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ - (I2C_MASTER_CS_STOP) -#define I2C_MASTER_CMD_BURST_RECEIVE_START \ - (I2C_MASTER_CS_ACK | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ - (I2C_MASTER_CS_ACK | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) - -//***************************************************************************** -// -// I2C Master error status. -// -//***************************************************************************** -#define I2C_MASTER_ERR_NONE 0 -#define I2C_MASTER_ERR_ADDR_ACK 0x00000004 -#define I2C_MASTER_ERR_DATA_ACK 0x00000008 -#define I2C_MASTER_ERR_ARB_LOST 0x00000010 - -//***************************************************************************** -// -// I2C Slave action requests -// -//***************************************************************************** -#define I2C_SLAVE_ACT_NONE 0 -#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data -#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data - -//***************************************************************************** -// Miscellaneous I2C driver definitions. -//***************************************************************************** -#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void)); -extern void I2CIntUnregister(unsigned long ulBase); -extern tBoolean I2CMasterBusBusy(unsigned long ulBase); -extern tBoolean I2CMasterBusy(unsigned long ulBase); -extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd); -extern unsigned long I2CMasterDataGet(unsigned long ulBase); -extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData); -extern void I2CMasterDisable(unsigned long ulBase); -extern void I2CMasterEnable(unsigned long ulBase); -extern unsigned long I2CMasterErr(unsigned long ulBase); -extern void I2CMasterInit(unsigned long ulBase, tBoolean bFast); -extern void I2CMasterIntClear(unsigned long ulBase); -extern void I2CMasterIntDisable(unsigned long ulBase); -extern void I2CMasterIntEnable(unsigned long ulBase); -extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void I2CMasterSlaveAddrSet(unsigned long ulBase, - unsigned char ucSlaveAddr, - tBoolean bReceive); -extern unsigned long I2CSlaveDataGet(unsigned long ulBase); -extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData); -extern void I2CSlaveDisable(unsigned long ulBase); -extern void I2CSlaveEnable(unsigned long ulBase); -extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr); -extern void I2CSlaveIntClear(unsigned long ulBase); -extern void I2CSlaveIntDisable(unsigned long ulBase); -extern void I2CSlaveIntEnable(unsigned long ulBase); -extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked); -extern unsigned long I2CSlaveStatus(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __I2C_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/interrupt.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/interrupt.h deleted file mode 100644 index 23424af4e..000000000 --- a/Demo/CORTEX_LM3S102_Rowley/hw_include/interrupt.h +++ /dev/null @@ -1,57 +0,0 @@ -//***************************************************************************** -// -// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 523 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __INTERRUPT_H__ -#define __INTERRUPT_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void IntMasterEnable(void); -extern void IntMasterDisable(void); -extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)); -extern void IntUnregister(unsigned long ulInterrupt); -extern void IntPriorityGroupingSet(unsigned long ulBits); -extern unsigned long IntPriorityGroupingGet(void); -extern void IntPrioritySet(unsigned long ulInterrupt, - unsigned char ucPriority); -extern long IntPriorityGet(unsigned long ulInterrupt); -extern void IntEnable(unsigned long ulInterrupt); -extern void IntDisable(unsigned long ulInterrupt); - -#ifdef __cplusplus -} -#endif - -#endif // __INTERRUPT_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/libdriver.a b/Demo/CORTEX_LM3S102_Rowley/hw_include/libdriver.a deleted file mode 100644 index c465e8f71..000000000 Binary files a/Demo/CORTEX_LM3S102_Rowley/hw_include/libdriver.a and /dev/null differ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/pdc.c b/Demo/CORTEX_LM3S102_Rowley/hw_include/pdc.c deleted file mode 100644 index 1e82ed8a8..000000000 --- a/Demo/CORTEX_LM3S102_Rowley/hw_include/pdc.c +++ /dev/null @@ -1,132 +0,0 @@ -//***************************************************************************** -// -// pdc.c - Driver for the Peripheral Device Controller (PDC) on the Stellaris -// development board. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 523 of the Stellaris Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup utilities_api -//! @{ -// -//***************************************************************************** - -#include "hw_memmap.h" -#include "hw_types.h" -#include "gpio.h" -#include "ssi.h" -#include "sysctl.h" -#include "pdc.h" - -//***************************************************************************** -// -//! Initializes the connection to the PDC. -//! -//! This function will enable clocking to the SSI and GPIO A modules, configure -//! the GPIO pins to be used for an SSI interface, and it will configure the -//! SSI as a 1Mb master device, operating in MOTO mode. It will also enable -//! the SSI module, and will enable the chip select for the PDC on the -//! Stellaris development board. -//! -//! This function is contained in utils/pdc.c, with -//! utils/pdc.h containing the API definition for use by applications. -//! -//! \return None. -// -//***************************************************************************** -void -PDCInit(void) -{ - // - // Enable the peripherals used to drive the PDC. - // - SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI); - SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); - - // - // Configure the appropriate pins to be SSI instead of GPIO. - // - GPIODirModeSet(GPIO_PORTA_BASE, SSI_CLK | SSI_TX | SSI_RX, - GPIO_DIR_MODE_HW); - GPIODirModeSet(GPIO_PORTA_BASE, SSI_CS, GPIO_DIR_MODE_OUT); - GPIOPadConfigSet(GPIO_PORTA_BASE, SSI_CLK, GPIO_STRENGTH_4MA, - GPIO_PIN_TYPE_STD_WPU); - - // - // Configure the SSI port. - // - SSIConfig(SSI_BASE, SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 1000000, 8); - SSIEnable(SSI_BASE); - - // - // Reset the PDC SSI state machine. The chip select needs to be held low - // for 100ns; the procedure call overhead more than accounts for this time. - // - GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, 0); - GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, PDC_CS); -} - -//***************************************************************************** -// -//! Write a PDC register. -//! -//! \param ucAddr specifies the PDC register to write. -//! \param ucData specifies the data to write. -//! -//! This function will perform the SSI transfers required to write a register -//! in the PDC on the Stellaris development board. -//! -//! This function is contained in utils/pdc.c, with -//! utils/pdc.h containing the API definition for use by applications. -//! -//! \return None. -// -//***************************************************************************** -void -PDCWrite(unsigned char ucAddr, unsigned char ucData) -{ - unsigned long ulTemp; - - // - // Send address and write command. - // - SSIDataPut(SSI_BASE, (ucAddr & 0x0F) | PDC_WR); - - // - // Write the data. - // - SSIDataPut(SSI_BASE, ucData); - - // - // Flush data read during address write. - // - SSIDataGet(SSI_BASE, &ulTemp); - - // - // Flush data read during data write. - // - SSIDataGet(SSI_BASE, &ulTemp); -} - diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/pdc.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/pdc.h deleted file mode 100644 index aba74cd71..000000000 --- a/Demo/CORTEX_LM3S102_Rowley/hw_include/pdc.h +++ /dev/null @@ -1,124 +0,0 @@ -//***************************************************************************** -// -// pdc.h - Stellaris development board Peripheral Device Controller definitions -// and prototypes. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 523 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __PDC_H__ -#define __PDC_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The registers within the peripheral device controller. -// -//***************************************************************************** -#define PDC_VER 0x0 // Version register -#define PDC_CSR 0x1 // Command/Status register -#define PDC_DSW 0x4 // DIP Switch register -#define PDC_LED 0x5 // LED register -#define PDC_LCD_CSR 0x6 // LCD Command/Status register -#define PDC_LCD_RAM 0x7 // LCD RAM register -#define PDC_GPXDAT 0x8 // GPIO X Data register -#define PDC_GPXDIR 0x9 // GPIO X Direction register -#define PDC_GPYDAT 0xA // GPIO Y Data register -#define PDC_GPYDIR 0xB // GPIO Y Direction register -#define PDC_GPZDAT 0xC // GPIO Z Data register -#define PDC_GPZDIR 0xD // GPIO Z Direction register - -//***************************************************************************** -// -// Flags indicating a read or write to the peripheral device controller. -// -//***************************************************************************** -#define PDC_RD 0x80 // PDC read command -#define PDC_WR 0x00 // PDC write command - -//***************************************************************************** -// -// LCD panel (Crystalfontz CFAH1602B) commands, RS = 0 -// -//***************************************************************************** -#define LCD_CLEAR 0x01 // Clear display (0 fill DDRAM). -#define LCD_HOME 0x02 // Cursor home. -#define LCD_MODE 0x04 // Set entry mode (cursor dir) -#define LCD_ON 0x08 // Set display, cursor, blinking - // on/off -#define LCD_CUR 0x10 // Cursor, display shift -#define LCD_IF 0x20 // Set interface data length, - // lines, font -#define LCD_CGADDR 0x40 // Set CGRAM AC address -#define LCD_DDADDR 0x80 // Set DDRAM AC address - -//***************************************************************************** -// -// LCD Status bit -// -//***************************************************************************** -#define LCD_B_BUSY 0x80 // Busy flag. - -//***************************************************************************** -// -// The GPIO port A pin numbers for the various SSI signals. -// -//***************************************************************************** -#define SSI_CS GPIO_PIN_3 -#define PDC_CS GPIO_PIN_3 -#define SSI_CLK GPIO_PIN_2 -#define SSI_TX GPIO_PIN_5 -#define SSI_RX GPIO_PIN_4 - -//***************************************************************************** -// -// Function Prototypes -// -//***************************************************************************** -extern void PDCInit(void); -extern unsigned char PDCRead(unsigned char ucAddr); -extern void PDCWrite(unsigned char ucAddr, unsigned char ucData); -extern unsigned char PDCDIPRead(void); -extern void PDCLEDWrite(unsigned char ucLED); -extern unsigned char PDCLEDRead(void); -extern void PDCLCDInit(void); -extern void PDCLCDBacklightOn(void); -extern void PDCLCDBacklightOff(void); -extern void PDCLCDClear(void); -extern void PDCLCDCreateChar(unsigned char ucChar, unsigned char *pucData); -extern void PDCLCDSetPos(unsigned char ucX, unsigned char ucY); -extern void PDCLCDWrite(const char *pcStr, unsigned long ulCount); -extern unsigned char PDCGPIODirRead(unsigned char ucIdx); -extern void PDCGPIODirWrite(unsigned char ucIdx, unsigned char ucValue); -extern unsigned char PDCGPIORead(unsigned char ucIdx); -extern void PDCGPIOWrite(unsigned char ucIdx, unsigned char ucValue); - -#ifdef __cplusplus -} -#endif - -#endif // __PDC_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/ssi.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/ssi.h deleted file mode 100644 index ef53b348b..000000000 --- a/Demo/CORTEX_LM3S102_Rowley/hw_include/ssi.h +++ /dev/null @@ -1,88 +0,0 @@ -//***************************************************************************** -// -// ssi.h - Prototypes for the Synchronous Serial Interface Driver. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 523 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __SSI_H__ -#define __SSI_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear -// as the ulIntFlags parameter, and returned by SSIIntStatus. -// -//***************************************************************************** -#define SSI_TXFF 0x00000008 // TX FIFO half empty or less -#define SSI_RXFF 0x00000004 // RX FIFO half full or less -#define SSI_RXTO 0x00000002 // RX timeout -#define SSI_RXOR 0x00000001 // RX overrun - -//***************************************************************************** -// -// Values that can be passed to SSIConfig. -// -//***************************************************************************** -#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 -#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 -#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 -#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 -#define SSI_FRF_TI 0x00000010 // TI frame format -#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format - -#define SSI_MODE_MASTER 0x00000000 // SSI master -#define SSI_MODE_SLAVE 0x00000001 // SSI slave -#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void SSIConfig(unsigned long ulBase, unsigned long ulProtocol, - unsigned long ulMode, unsigned long ulBitRate, - unsigned long ulDataWidth); -extern void SSIDataGet(unsigned long ulBase, unsigned long *ulData); -extern long SSIDataNonBlockingGet(unsigned long ulBase, unsigned long *ulData); -extern void SSIDataPut(unsigned long ulBase, unsigned long ulData); -extern long SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData); -extern void SSIDisable(unsigned long ulBase); -extern void SSIEnable(unsigned long ulBase); -extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags); -extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); -extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void SSIIntUnregister(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __SSI_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/sysctl.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/sysctl.h deleted file mode 100644 index 2e1d1e48c..000000000 --- a/Demo/CORTEX_LM3S102_Rowley/hw_include/sysctl.h +++ /dev/null @@ -1,221 +0,0 @@ -//***************************************************************************** -// -// sysctl.h - Prototypes for the system control driver. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 523 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __SYSCTL_H__ -#define __SYSCTL_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following are values that can be passed to the -// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(), -// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the -// ulPeripheral parameter. The peripherals in the fourth group (upper nibble -// is 3) can only be used with the SysCtlPeripheralPresent() API. -// -//***************************************************************************** -#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog -#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0 -#define SYSCTL_PERIPH_SSI 0x10000010 // SSI -#define SYSCTL_PERIPH_I2C 0x10001000 // I2C -#define SYSCTL_PERIPH_TIMER0 0x10010000 // Timer 0 -#define SYSCTL_PERIPH_TIMER1 0x10020000 // Timer 1 -#define SYSCTL_PERIPH_COMP0 0x11000000 // Analog comparator 0 -#define SYSCTL_PERIPH_COMP1 0x12000000 // Analog comparator 1 -#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A -#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B -#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C -#define SYSCTL_PERIPH_PLL 0x30000010 // PLL - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlPinPresent() API -// as the ulPin parameter. -// -//***************************************************************************** -#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin -#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin -#define SYSCTL_PIN_C0O 0x00000100 // C0o pin -#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin -#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin -#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin -#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlLDOSet() API as -// the ulVoltage value, or returned by the SysCtlLDOGet() API. -// -//***************************************************************************** -#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V -#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V -#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V -#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V -#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V -#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V -#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V -#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V -#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V -#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V -#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlLDOConfigSet() API. -// -//***************************************************************************** -#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset -#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlIntEnable(), -// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask -// by the SysCtlIntStatus() API. -// -//***************************************************************************** -#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt -#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt -#define SYSCTL_INT_BOSC_FAIL 0x00000010 // Boot oscillator failure int -#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int -#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt -#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt -#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlResetCauseClear() -// API or returned by the SysCtlResetCauseGet() API. -// -//***************************************************************************** -#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset -#define SYSCTL_CAUSE_SW 0x00000010 // Software reset -#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset -#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset -#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset -#define SYSCTL_CAUSE_EXT 0x00000001 // External reset - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlBrownOutConfigSet() -// API as the ulConfig parameter. -// -//***************************************************************************** -#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting -#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlClockSet() API as -// the ulConfig parameter. -// -//***************************************************************************** -#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1 -#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2 -#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3 -#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4 -#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5 -#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6 -#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7 -#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8 -#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9 -#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10 -#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11 -#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12 -#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13 -#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14 -#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15 -#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16 -#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock -#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock -#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz -#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz -#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz -#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz -#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz -#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz -#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz -#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz -#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz -#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz -#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz -#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz -#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc -#define SYSCTL_OSC_BOOT 0x00000010 // Oscillator source is boot osc -#define SYSCTL_OSC_BOOT4 0x00000020 // Oscillator source is boot osc /4 -#define SYSCTL_BOOT_OSC_DIS 0x00000002 // Disable boot oscillator -#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern unsigned long SysCtlSRAMSizeGet(void); -extern unsigned long SysCtlFlashSizeGet(void); -extern tBoolean SysCtlPinPresent(unsigned long ulPin); -extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral); -extern void SysCtlPeripheralReset(unsigned long ulPeripheral); -extern void SysCtlPeripheralEnable(unsigned long ulPeripheral); -extern void SysCtlPeripheralDisable(unsigned long ulPeripheral); -extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral); -extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral); -extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral); -extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral); -extern void SysCtlPeripheralClockGating(tBoolean bEnable); -extern void SysCtlIntRegister(void (*pfnHandler)(void)); -extern void SysCtlIntUnregister(void); -extern void SysCtlIntEnable(unsigned long ulInts); -extern void SysCtlIntDisable(unsigned long ulInts); -extern void SysCtlIntClear(unsigned long ulInts); -extern unsigned long SysCtlIntStatus(tBoolean bMasked); -extern void SysCtlLDOSet(unsigned long ulVoltage); -extern unsigned long SysCtlLDOGet(void); -extern void SysCtlLDOConfigSet(unsigned long ulConfig); -extern void SysCtlReset(void); -extern void SysCtlSleep(void); -extern void SysCtlDeepSleep(void); -extern unsigned long SysCtlResetCauseGet(void); -extern void SysCtlResetCauseClear(unsigned long ulCauses); -extern void SysCtlBrownOutConfigSet(unsigned long ulConfig, - unsigned long ulDelay); -extern void SysCtlClockSet(unsigned long ulConfig); -extern unsigned long SysCtlClockGet(void); -extern void SysCtlBOSCVerificationSet(tBoolean bEnable); -extern void SysCtlMOSCVerificationSet(tBoolean bEnable); -extern void SysCtlPLLVerificationSet(tBoolean bEnable); -extern void SysCtlClkVerificationClear(void); - -#ifdef __cplusplus -} -#endif - -#endif // __SYSCTL_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/systick.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/systick.h deleted file mode 100644 index 4f70259ba..000000000 --- a/Demo/CORTEX_LM3S102_Rowley/hw_include/systick.h +++ /dev/null @@ -1,53 +0,0 @@ -//***************************************************************************** -// -// systick.h - Prototypes for the SysTick driver. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 523 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __SYSTICK_H__ -#define __SYSTICK_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void SysTickEnable(void); -extern void SysTickDisable(void); -extern void SysTickIntRegister(void (*pfnHandler)(void)); -extern void SysTickIntUnregister(void); -extern void SysTickPeriodSet(unsigned long ulPeriod); -extern unsigned long SysTickPeriodGet(void); -extern unsigned long SysTickValueGet(void); - -#ifdef __cplusplus -} -#endif - -#endif // __SYSTICK_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/timer.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/timer.h deleted file mode 100644 index 306b141db..000000000 --- a/Demo/CORTEX_LM3S102_Rowley/hw_include/timer.h +++ /dev/null @@ -1,137 +0,0 @@ -//***************************************************************************** -// -// timer.h - Prototypes for the timer module -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 523 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __TIMER_H__ -#define __TIMER_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to TimerConfigure as the ulConfig parameter. -// -//***************************************************************************** -#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer -#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer -#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer -#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers -#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer -#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer -#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter -#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer -#define TIMER_CFG_A_PWM 0x0000000F // Timer A PWM output -#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer -#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer -#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter -#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer -#define TIMER_CFG_B_PWM 0x00000F00 // Timer B PWM output - -//***************************************************************************** -// -// Values that can be passed to TimerIntEnable, TimerIntDisable, and -// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus. -// -//***************************************************************************** -#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt -#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt -#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt -#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask -#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt -#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt -#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerB time out interrupt - -//***************************************************************************** -// -// Values that can be passed to TimerControlEvent as the ulEvent parameter. -// -//***************************************************************************** -#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges -#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges -#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges - -//***************************************************************************** -// -// Values that can be passed to most of the timer APIs as the ulTimer -// parameter. -// -//***************************************************************************** -#define TIMER_A 0x000000ff // Timer A -#define TIMER_B 0x0000ff00 // Timer B -#define TIMER_BOTH 0x0000ffff // Timer Both - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer); -extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer); -extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig); -extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, - tBoolean bInvert); -extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, - tBoolean bEnable); -extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulEvent); -extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer, - tBoolean bStall); -extern void TimerRTCEnable(unsigned long ulBase); -extern void TimerRTCDisable(unsigned long ulBase); -extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerPrescaleGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer); -extern unsigned long TimerValueGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerMatchGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, - void (*pfnHandler)(void)); -extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer); -extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags); -extern void TimerQuiesce(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __TIMER_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/uart.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/uart.h deleted file mode 100644 index ea39859d2..000000000 --- a/Demo/CORTEX_LM3S102_Rowley/hw_include/uart.h +++ /dev/null @@ -1,102 +0,0 @@ -//***************************************************************************** -// -// uart.h - Defines and Macros for the UART. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 523 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __UART_H__ -#define __UART_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear -// as the ulIntFlags parameter, and returned from UARTIntStatus. -// -//***************************************************************************** -#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask -#define UART_INT_BE 0x200 // Break Error Interrupt Mask -#define UART_INT_PE 0x100 // Parity Error Interrupt Mask -#define UART_INT_FE 0x080 // Framing Error Interrupt Mask -#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask -#define UART_INT_TX 0x020 // Transmit Interrupt Mask -#define UART_INT_RX 0x010 // Receive Interrupt Mask - -//***************************************************************************** -// -// Values that can be passed to UARTConfigSet as the ulConfig parameter and -// returned by UARTConfigGet in the pulConfig parameter. Additionally, the -// UART_CONFIG_PAR_* subset can be passed to UARTParityModeSet as the ulParity -// parameter, and are returned by UARTParityModeGet. -// -//***************************************************************************** -#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data -#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data -#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data -#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data -#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit -#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits -#define UART_CONFIG_PAR_NONE 0x00000000 // No parity -#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity -#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity -#define UART_CONFIG_PAR_ONE 0x00000086 // Parity bit is one -#define UART_CONFIG_PAR_ZERO 0x00000082 // Parity bit is zero - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity); -extern unsigned long UARTParityModeGet(unsigned long ulBase); -extern void UARTConfigSet(unsigned long ulBase, unsigned long ulBaud, - unsigned long ulConfig); -extern void UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud, - unsigned long *pulConfig); -extern void UARTEnable(unsigned long ulBase); -extern void UARTDisable(unsigned long ulBase); -extern tBoolean UARTCharsAvail(unsigned long ulBase); -extern tBoolean UARTSpaceAvail(unsigned long ulBase); -extern long UARTCharNonBlockingGet(unsigned long ulBase); -extern long UARTCharGet(unsigned long ulBase); -extern tBoolean UARTCharNonBlockingPut(unsigned long ulBase, - unsigned char ucData); -extern void UARTCharPut(unsigned long ulBase, unsigned char ucData); -extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState); -extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); -extern void UARTIntUnregister(unsigned long ulBase); -extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags); - -#ifdef __cplusplus -} -#endif - -#endif // __UART_H__ diff --git a/Demo/CORTEX_LM3S102_Rowley/hw_include/watchdog.h b/Demo/CORTEX_LM3S102_Rowley/hw_include/watchdog.h deleted file mode 100644 index 2a82b7200..000000000 --- a/Demo/CORTEX_LM3S102_Rowley/hw_include/watchdog.h +++ /dev/null @@ -1,63 +0,0 @@ -//***************************************************************************** -// -// watchdog.h - Prototypes for the Watchdog Timer API -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 523 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __WATCHDOG_H__ -#define __WATCHDOG_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern tBoolean WatchdogRunning(unsigned long ulBase); -extern void WatchdogEnable(unsigned long ulBase); -extern void WatchdogResetEnable(unsigned long ulBase); -extern void WatchdogResetDisable(unsigned long ulBase); -extern void WatchdogLock(unsigned long ulBase); -extern void WatchdogUnlock(unsigned long ulBase); -extern tBoolean WatchdogLockState(unsigned long ulBase); -extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal); -extern unsigned long WatchdogReloadGet(unsigned long ulBase); -extern unsigned long WatchdogValueGet(unsigned long ulBase); -extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); -extern void WatchdogIntUnregister(unsigned long ulBase); -extern void WatchdogIntEnable(unsigned long ulBase); -extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void WatchdogIntClear(unsigned long ulBase); -extern void WatchdogStallDisable(unsigned long ulBase); -extern void WatchdogStallDisable(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __WATCHDOG_H__ diff --git a/Demo/CORTEX_LM3S316_IAR/FreeRTOSConfig.h b/Demo/CORTEX_LM3S316_IAR/FreeRTOSConfig.h deleted file mode 100644 index bf4788e81..000000000 --- a/Demo/CORTEX_LM3S316_IAR/FreeRTOSConfig.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 1 -#define configUSE_TICK_HOOK 0 -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 ) -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 70 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 3000 ) ) -#define configMAX_TASK_NAME_LEN ( 3 ) -#define configUSE_TRACE_FACILITY 0 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 0 -#define configUSE_CO_ROUTINES 1 - -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 ) -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 0 -#define INCLUDE_uxTaskPriorityGet 0 -#define INCLUDE_vTaskDelete 0 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 0 -#define INCLUDE_vTaskDelayUntil 0 -#define INCLUDE_vTaskDelay 1 - - - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/CORTEX_LM3S316_IAR/ParTest/ParTest.c b/Demo/CORTEX_LM3S316_IAR/ParTest/ParTest.c deleted file mode 100644 index e344c1b7b..000000000 --- a/Demo/CORTEX_LM3S316_IAR/ParTest/ParTest.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/*----------------------------------------------------------- - * Simple parallel port IO routines. - *-----------------------------------------------------------*/ - -/* -*/ - - -#include "FreeRTOS.h" -#include "Task.h" -#include "partest.h" - -#include "pdc.h" - -#define partstPINS (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 Z | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7) - -#define partstALL_OUTPUTS_OFF ( ( unsigned portCHAR ) 0x00 ) -#define partstMAX_OUTPUT_LED ( ( unsigned portCHAR ) 8 ) - -static volatile unsigned portCHAR ucOutputValue = partstALL_OUTPUTS_OFF; - -void vParTestInitialise( void ) -{ - PDCInit(); - PDCWrite( PDC_LED, ucOutputValue ); -} -/*-----------------------------------------------------------*/ - -void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) -{ -unsigned portCHAR ucBit = ( unsigned portCHAR ) 1; - - vTaskSuspendAll(); - { - if( uxLED < partstMAX_OUTPUT_LED ) - { - ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED; - - if( xValue == pdFALSE ) - { - ucBit ^= ( unsigned portCHAR ) 0xff; - ucOutputValue &= ucBit; - } - else - { - ucOutputValue |= ucBit; - } - - PDCWrite( PDC_LED, ucOutputValue ); - } - } - xTaskResumeAll(); -} -/*-----------------------------------------------------------*/ - -void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) -{ -unsigned portCHAR ucBit; - - vTaskSuspendAll(); - { - if( uxLED < partstMAX_OUTPUT_LED ) - { - ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED; - - if( ucOutputValue & ucBit ) - { - ucOutputValue &= ~ucBit; - } - else - { - ucOutputValue |= ucBit; - } - - PDCWrite( PDC_LED, ucOutputValue ); - } - } - xTaskResumeAll(); -} - diff --git a/Demo/CORTEX_LM3S316_IAR/RTOSDemo.dep b/Demo/CORTEX_LM3S316_IAR/RTOSDemo.dep deleted file mode 100644 index 0e25ef46c..000000000 --- a/Demo/CORTEX_LM3S316_IAR/RTOSDemo.dep +++ /dev/null @@ -1,535 +0,0 @@ - - - - 2 - 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$TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin - 0 - - - - - - diff --git a/Demo/CORTEX_LM3S316_IAR/RTOSDemo.ewp b/Demo/CORTEX_LM3S316_IAR/RTOSDemo.ewp deleted file mode 100644 index b63c9c75b..000000000 --- a/Demo/CORTEX_LM3S316_IAR/RTOSDemo.ewp +++ /dev/null @@ -1,891 +0,0 @@ - - - - 1 - - Debug - - ARM - - 1 - - General - 2 - - 9 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 13 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 7 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - XLINK - 2 - - 18 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - XAR - 2 - - 0 - 1 - 1 - - - - - - - BILINK - 0 - - - - - Demo Source - - $PROJ_DIR$\commstest.c - - - $PROJ_DIR$\..\Common\Minimal\crflash.c - - - $PROJ_DIR$\main.c - - - $PROJ_DIR$\ParTest\ParTest.c - - - $PROJ_DIR$\registertest.s - - - - FreeRTOS Source - - $PROJ_DIR$\..\..\Source\croutine.c - - - $PROJ_DIR$\..\..\Source\portable\MemMang\heap_1.c - - - $PROJ_DIR$\..\..\Source\list.c - - - $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c - - - $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s - - - $PROJ_DIR$\..\..\Source\queue.c - - - $PROJ_DIR$\..\..\Source\tasks.c - - - - Libraries - - $PROJ_DIR$\hw_include\driverlib.r79 - - - - Luminary Code - - $PROJ_DIR$\hw_include\cspy.c - - - $PROJ_DIR$\hw_include\pdc.c - - - $PROJ_DIR$\hw_include\startup.c - - - - - diff --git a/Demo/CORTEX_LM3S316_IAR/RTOSDemo.eww b/Demo/CORTEX_LM3S316_IAR/RTOSDemo.eww deleted file mode 100644 index 239a9381e..000000000 --- a/Demo/CORTEX_LM3S316_IAR/RTOSDemo.eww +++ /dev/null @@ -1,10 +0,0 @@ - - - - - $WS_DIR$\RTOSDemo.ewp - - - - - diff --git a/Demo/CORTEX_LM3S316_IAR/commstest.c b/Demo/CORTEX_LM3S316_IAR/commstest.c deleted file mode 100644 index 4aed9baa7..000000000 --- a/Demo/CORTEX_LM3S316_IAR/commstest.c +++ /dev/null @@ -1,294 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * The comms test Rx and Tx task and co-routine. See the comments at the top - * of main.c for full information. - */ - - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" -#include "croutine.h" - -/* Demo application include files. */ -#include "partest.h" - -/* Library include files. */ -#include "DriverLib.h" - -/* The LED's toggled by the various tasks. */ -#define commsFAIL_LED ( 7 ) -#define commsRX_LED ( 6 ) -#define commsTX_LED ( 5 ) - -/* The length of the queue used to pass received characters to the Comms Rx -task. */ -#define commsRX_QUEUE_LEN ( 5 ) - -/* The baud rate used by the UART comms tasks/co-routine. */ -#define commsBAUD_RATE ( 57600 ) - -/* FIFO setting for the UART. The FIFO is not used to create a better test. */ -#define commsFIFO_SET ( 0x10 ) - -/* The string that is transmitted on the UART contains sequentially the -characters from commsFIRST_TX_CHAR to commsLAST_TX_CHAR. */ -#define commsFIRST_TX_CHAR '0' -#define commsLAST_TX_CHAR 'z' - -/* Just used to walk through the program memory in order that some random data -can be generated. */ -#define commsTOTAL_PROGRAM_MEMORY ( ( unsigned portLONG * ) ( 8 * 1024 ) ) -#define commsFIRST_PROGRAM_BYTES ( ( unsigned portLONG * ) 4 ) - -/* The time between transmissions of the string on UART 0. This is pseudo -random in order to generate a bit or randomness to when the interrupts occur.*/ -#define commsMIN_TX_DELAY ( 40 / portTICK_RATE_MS ) -#define commsMAX_TX_DELAY ( ( portTickType ) 0x7f ) -#define commsOFFSET_TIME ( ( portTickType ) 3 ) - -/* The time the Comms Rx task should wait to receive a character. This should -be slightly longer than the time between transmissions. If we do not receive -a character after this time then there must be an error in the transmission or -the timing of the transmission. */ -#define commsRX_DELAY ( commsMAX_TX_DELAY + 20 ) - - -static unsigned portBASE_TYPE uxCommsErrorStatus = pdPASS; - -/* The queue used to pass characters out of the ISR. */ -static xQueueHandle xCommsQueue; - -/* The next character to transmit. */ -static portCHAR cNextChar; - -/*-----------------------------------------------------------*/ - -void vSerialInit( void ) -{ - /* Create the queue used to communicate between the UART ISR and the Comms - Rx task. */ - xCommsQueue = xQueueCreate( commsRX_QUEUE_LEN, sizeof( portCHAR ) ); - - /* Enable the UART. GPIOA has already been initialised. */ - SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); - - /* Set GPIO A0 and A1 as peripheral function. They are used to output the - UART signals. */ - GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); - - /* Configure the UART for 8-N-1 operation. */ - UARTConfigSet( UART0_BASE, commsBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); - - /* We dont want to use the fifo. This is for test purposes to generate - as many interrupts as possible. */ - HWREG( UART0_BASE + UART_O_LCR_H ) &= ~commsFIFO_SET; - - /* Enable both Rx and Tx interrupts. */ - HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX ); - IntEnable( INT_UART0 ); -} -/*-----------------------------------------------------------*/ - -void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) -{ -portTickType xDelayPeriod; -static unsigned portLONG *pulRandomBytes = commsFIRST_PROGRAM_BYTES; - - /* Co-routine MUST start with a call to crSTART. */ - crSTART( xHandle ); - - for(;;) - { - /* Was the previously transmitted string received correctly? */ - if( uxCommsErrorStatus != pdPASS ) - { - /* An error was encountered so set the error LED. */ - vParTestSetLED( commsFAIL_LED, pdTRUE ); - } - - /* The next character to Tx is the first in the string. */ - cNextChar = commsFIRST_TX_CHAR; - - UARTIntDisable( UART0_BASE, UART_INT_TX ); - { - /* Send the first character. */ - if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) - { - HWREG( UART0_BASE + UART_O_DR ) = cNextChar; - } - - /* Move the variable to the char to Tx on so the ISR transmits - the next character in the string once this one has completed. */ - cNextChar++; - } - UARTIntEnable(UART0_BASE, UART_INT_TX); - - /* Toggle the LED to show a new string is being transmitted. */ - vParTestToggleLED( commsTX_LED ); - - /* Delay before we start the string off again. A pseudo-random delay - is used as this will provide a better test. */ - xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes ); - - pulRandomBytes++; - if( pulRandomBytes > commsTOTAL_PROGRAM_MEMORY ) - { - pulRandomBytes = commsFIRST_PROGRAM_BYTES; - } - - /* Make sure we don't wait too long... */ - xDelayPeriod &= commsMAX_TX_DELAY; - - /* ...but we do want to wait. */ - if( xDelayPeriod < commsMIN_TX_DELAY ) - { - xDelayPeriod = commsMIN_TX_DELAY; - } - - /* Block for the random(ish) time. */ - crDELAY( xHandle, xDelayPeriod ); - } - - /* Co-routine MUST end with a call to crEND. */ - crEND(); -} -/*-----------------------------------------------------------*/ - -void vUART_ISR( void ) -{ -unsigned portLONG ulStatus; -portCHAR cRxedChar; -portBASE_TYPE xTaskWokenByPost = pdFALSE; - - /* What caused the interrupt. */ - ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); - - /* Clear the interrupt. */ - UARTIntClear( UART0_BASE, ulStatus ); - - /* Was an Rx interrpt pending? */ - if( ulStatus & UART_INT_RX ) - { - if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) ) - { - /* Get the char from the buffer and post it onto the queue of - Rxed chars. Posting the character should wake the task that is - blocked on the queue waiting for characters. */ - cRxedChar = ( portCHAR ) HWREG( UART0_BASE + UART_O_DR ); - xTaskWokenByPost = xQueueSendFromISR( xCommsQueue, &cRxedChar, xTaskWokenByPost ); - } - } - - /* Was a Tx interrupt pending? */ - if( ulStatus & UART_INT_TX ) - { - /* Send the next character in the string. We are not using the FIFO. */ - if( cNextChar <= commsLAST_TX_CHAR ) - { - if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) - { - HWREG( UART0_BASE + UART_O_DR ) = cNextChar; - } - cNextChar++; - } - } - - if( xTaskWokenByPost ) - { - /* If a task was woken by the character being received then we force - a context switch to occur in case the task is of higher priority than - the currently executing task (i.e. the task that this interrupt - interrupted.) */ - portEND_SWITCHING_ISR( xTaskWokenByPost ); - } -} -/*-----------------------------------------------------------*/ - -void vCommsRxTask( void * pvParameters ) -{ -static portCHAR cRxedChar, cExpectedChar; - - /* Set the char we expect to receive to the start of the string. */ - cExpectedChar = commsFIRST_TX_CHAR; - - for( ;; ) - { - /* Wait for a character to be received. */ - xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, commsRX_DELAY ); - - /* Was the character recived (if any) the expected character. */ - if( cRxedChar != cExpectedChar ) - { - /* Got an unexpected character. This can sometimes occur when - reseting the system using the debugger leaving characters already - in the UART regsters. */ - uxCommsErrorStatus = pdFAIL; - - /* Resync by waiting for the end of the current string. */ - while( cRxedChar != commsLAST_TX_CHAR ) - { - while( !xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, portMAX_DELAY ) ); - } - - /* The next expected character is the start of the string again. */ - cExpectedChar = commsFIRST_TX_CHAR; - } - else - { - if( cExpectedChar == commsLAST_TX_CHAR ) - { - /* We have reached the end of the string - we now expect to - receive the first character in the string again. The LED is - toggled to indicate that the entire string was received without - error. */ - vParTestToggleLED( commsRX_LED ); - cExpectedChar = commsFIRST_TX_CHAR; - } - else - { - /* We got the expected character, we now expect to receive the - next character in the string. */ - cExpectedChar++; - } - } - } -} -/*-----------------------------------------------------------*/ - -unsigned portBASE_TYPE uxGetCommsStatus( void ) -{ - return uxCommsErrorStatus; -} diff --git a/Demo/CORTEX_LM3S316_IAR/commstest.h b/Demo/CORTEX_LM3S316_IAR/commstest.h deleted file mode 100644 index 9d1cd28e2..000000000 --- a/Demo/CORTEX_LM3S316_IAR/commstest.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef COMMS_TEST_H -#define COMMS_TEST_H - -/* - * Initialisation routine for the UART. - */ -void vSerialInit( void ); - -/* - * The task that receives the characters from UART 0. - */ -void vCommsRxTask( void * pvParameters ); - -/* - * The co-routine that periodically initiates the transmission of the string on - * the UART. - */ -void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); - -unsigned portBASE_TYPE uxGetCommsStatus( void ); - -#endif diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/DriverLib.h b/Demo/CORTEX_LM3S316_IAR/hw_include/DriverLib.h deleted file mode 100644 index 6374ddca6..000000000 --- a/Demo/CORTEX_LM3S316_IAR/hw_include/DriverLib.h +++ /dev/null @@ -1,22 +0,0 @@ -#ifndef INCLUDE_DRIVER_LIB_H -#define INCLUDE_DRIVER_LIB_H - -#include "hw_ints.h" -#include "hw_uart.h" -#include "hw_memmap.h" -#include "hw_types.h" -#include "hw_nvic.h" -#include "hw_ssi.h" -#include "hw_i2c.h" -#include "hw_adc.h" - -#include "gpio.h" -#include "interrupt.h" -#include "sysctl.h" -#include "uart.h" -#include "ssi.h" -#include "pdc.h" -#include "i2c.h" -#include "adc.h" - -#endif diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/EULA.txt b/Demo/CORTEX_LM3S316_IAR/hw_include/EULA.txt deleted file mode 100644 index cba31f7dc..000000000 --- a/Demo/CORTEX_LM3S316_IAR/hw_include/EULA.txt +++ /dev/null @@ -1,126 +0,0 @@ -IMPORTANT. Read the following LMI Software License Agreement ("Agreement") -completely. - -LUMINARY MICRO SOFTWARE LICENSE AGREEMENT - - This is a legal agreement between you (either as an individual or as an -authorized representative of your employer) and Luminary Micro, Inc. ("LMI"). -It concerns your rights to use this file and any accompanying written materials -(the "Software"). In consideration for LMI allowing you to access the -Software, you are agreeing to be bound by the terms of this Agreement. If you -do not agree to all of the terms of this Agreement, do not download or use the -Software. If you change your mind later, stop using the Software and delete -all copies of the Software in your possession or control. Any copies of the -Software that you have already distributed, where permitted, and do not destroy -will continue to be governed by this Agreement. Your prior use will also -continue to be governed by this Agreement. - -1. LICENSE GRANT. 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You agree that the statutes and -laws of the United States and the State of Texas, USA, without regard to -conflicts of laws principles, will apply to all matters relating to this -Agreement or the Software, and you agree that any litigation will be subject to -the exclusive jurisdiction of the state or federal courts in Austin, Travis -County, Texas, USA. You agree that regardless of any statute or law to the -contrary, any claim or cause of action arising out of or related to this -Agreement or the Software must be filed within one (1) year after such claim or -cause of action arose or be forever barred. - -12. ENTIRE AGREEMENT. This Agreement constitutes the entire agreement -between you and LMI regarding the subject matter of this Agreement, and -supersedes all prior communications, negotiations, understandings, agreements -or representations, either written or oral, if any. This Agreement may only be -amended in written form, executed by you and LMI. - -13. SEVERABILITY. If any provision of this Agreement is held for any -reason to be invalid or unenforceable, then the remaining provisions of this -Agreement will be unimpaired and, unless a modification or replacement of the -invalid or unenforceable provision is further held to deprive you or LMI of a -material benefit, in which case the Agreement will immediately terminate, the -invalid or unenforceable provision will be replaced with a provision that is -valid and enforceable and that comes closest to the intention underlying the -invalid or unenforceable provision. - -14. NO WAIVER. The waiver by LMI of any breach of any provision of this -Agreement will not operate or be construed as a waiver of any other or a -subsequent breach of the same or a different provision. diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/RTOSDemo_lnk.xcl b/Demo/CORTEX_LM3S316_IAR/hw_include/RTOSDemo_lnk.xcl deleted file mode 100644 index d937b98d8..000000000 --- a/Demo/CORTEX_LM3S316_IAR/hw_include/RTOSDemo_lnk.xcl +++ /dev/null @@ -1,192 +0,0 @@ -// Generated : 06/01/06 20:29:52 -//********************************************************************** -// XLINK template command file to be used with the ICCARM C/C++ Compiler -// -// Usage: xlink -f lnkarm -// -s -// -// $Revision: 1.3 $ -// -//********************************************************************** - -//************************************************************************* -// In this file it is assumed that the system has the following -// memory layout: -// -// Exception vectors [0x000000--0x00001F] RAM or ROM -// ROMSTART--ROMEND [0x008000--0x0FFFFF] ROM (or other non-volatile memory) -// RAMSTART--RAMEND [0x100000--0x7FFFFF] RAM (or other read/write memory) -// -// ------------- -// Code segments - may be placed anywhere in memory. -// ------------- -// -// INTVEC -- Exception vector table. -// SWITAB -- Software interrupt vector table. -// ICODE -- Startup (cstartup) and exception code. -// DIFUNCT -- Dynamic initialization vectors used by C++. -// CODE -- Compiler generated code. -// CODE_I -- Compiler generated code declared __ramfunc (executes in RAM) -// CODE_ID -- Initializer for CODE_I (ROM). -// -// ------------- -// Data segments - may be placed anywhere in memory. -// ------------- -// -// CSTACK -- The stack used by C/C++ programs (system and user mode). -// IRQ_STACK -- The stack used by IRQ service routines. -// SVC_STACK -- The stack used in supervisor mode -// (Define other exception stacks as needed for -// FIQ, ABT, UND). -// HEAP -- The heap used by malloc and free in C and new and -// delete in C++. -// INITTAB -- Table containing addresses and sizes of segments that -// need to be initialized at startup (by cstartup). -// CHECKSUM -- The linker places checksum byte(s) in this segment, -// when the -J linker command line option is used. -// DATA_y -- Data objects. -// -// Where _y can be one of: -// -// _AN -- Holds uninitialized located objects, i.e. objects with -// an absolute location given by the @ operator or the -// #pragma location directive. Since these segments -// contain objects which already have a fixed address, -// they should not be mentioned in this linker command -// file. -// _C -- Constants (ROM). -// _I -- Initialized data (RAM). -// _ID -- The original content of _I (copied to _I by cstartup) (ROM). -// _N -- Uninitialized data (RAM). -// _Z -- Zero initialized data (RAM). -// -// Note: Be sure to use end values for the defined address ranges. -// Otherwise, the linker may allocate space outside the -// intended memory range. -//************************************************************************* - -//************************************************ -// Inform the linker about the CPU family used. -//************************************************ - --carm - -//************************************************************************* -// Segment placement - General information -// -// All numbers in the segment placement command lines below are interpreted -// as hexadecimal unless they are immediately preceded by a '.', which -// denotes decimal notation. -// -// When specifying the segment placement using the -P instead of the -Z -// option, the linker is free to split each segment into its segment parts -// and randomly place these parts within the given ranges in order to -// achieve a more efficient memory usage. One disadvantage, however, is -// that it is not possible to find the start or end address (using -// the assembler operators .sfb./.sfe.) of a segment which has been split -// and reformed. -// -// When generating an output file which is to be used for programming -// external ROM/Flash devices, the -M linker option is very useful -// (see xlink.pdf for details). -//************************************************************************* - - -//************************************************************************* -// Read-only segments mapped to ROM. -//************************************************************************* - -//************************************************ -// Address range for reset and exception -// vectors (INTVEC). -// The vector area is 32 bytes, -// an additional 32 bytes is allocated for the -// constant table used by ldr PC in cstartup.s79. -//************************************************ - --Z(CODE)INTVEC=0-3F - -//************************************************ -// Startup code and exception routines (ICODE). -//************************************************ - --Z(CODE)ICODE,DIFUNCT=8000-FFFFF --Z(CODE)SWITAB=8000-FFFFF - -//************************************************ -// Code segments may be placed anywhere. -//************************************************ - --Z(CODE)CODE=8000-FFFFF - -//************************************************ -// Original ROM location for __ramfunc code copied -// to and executed from RAM. -//************************************************ - --Z(CONST)CODE_ID=8000-FFFFF - -//************************************************ -// Various constants and initializers. -//************************************************ - --Z(CONST)INITTAB,DATA_ID,DATA_C=8000-FFFFF --Z(CONST)CHECKSUM=8000-FFFFF - -//************************************************************************* -// Read/write segments mapped to RAM. -//************************************************************************* - -//************************************************ -// Data segments. -//************************************************ - --Z(DATA)DATA_I,DATA_Z,DATA_N=100000-7FFFFF - -//************************************************ -// __ramfunc code copied to and executed from RAM. -//************************************************ - --Z(DATA)CODE_I=100000-7FFFFF - -//************************************************ -// ICCARM produces code for __ramfunc functions in -// CODE_I segments. The -Q XLINK command line -// option redirects XLINK to emit the code in the -// CODE_ID segment instead, but to keep symbol and -// debug information associated with the CODE_I -// segment, where the code will execute. -//************************************************ - --QCODE_I=CODE_ID - -//************************************************************************* -// Stack and heap segments. -//************************************************************************* - --Z(DATA)CSTACK+200=100000-7FFFFF --Z(DATA)IRQ_STACK+100=100000-7FFFFF --Z(DATA)HEAP+8000=100000-7FFFFF - -//********************************************************************** -// Output user defined segments -//********************************************************************** - - - -//************************************************************************* -// ELF/DWARF support. -// -// Uncomment the line "-Felf" below to generate ELF/DWARF output. -// Available format specifiers are: -// -// "-yn": Suppress DWARF debug output -// "-yp": Multiple ELF program sections -// "-yas": Format suitable for debuggers from ARM Ltd (also sets -p flag) -// -// "-Felf" and the format specifiers can also be supplied directly as -// command line options, or selected from the Xlink Output tab in the -// IAR Embedded Workbench. -//************************************************************************* - -// -Felf diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/adc.h b/Demo/CORTEX_LM3S316_IAR/hw_include/adc.h deleted file mode 100644 index 1825664a3..000000000 --- a/Demo/CORTEX_LM3S316_IAR/hw_include/adc.h +++ /dev/null @@ -1,120 +0,0 @@ -//***************************************************************************** -// -// adc.h - ADC headers for using the ADC driver functions. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 635 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __ADC_H__ -#define __ADC_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to ADCSequenceConfigure as the ulTrigger -// parameter. -// -//***************************************************************************** -#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event -#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event -#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event -#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event -#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event -#define ADC_TRIGGER_TIMER 0x00000005 // Timer event -#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event -#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event -#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event -#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event - -//***************************************************************************** -// -// Values that can be passed to ADCSequenceStepConfigure as the ulConfig -// parameter. -// -//***************************************************************************** -#define ADC_CTL_TS 0x00000080 // Temperature sensor select -#define ADC_CTL_IE 0x00000040 // Interrupt enable -#define ADC_CTL_END 0x00000020 // Sequence end select -#define ADC_CTL_D 0x00000010 // Differential select -#define ADC_CTL_CH0 0x00000000 // Input channel 0 -#define ADC_CTL_CH1 0x00000001 // Input channel 1 -#define ADC_CTL_CH2 0x00000002 // Input channel 2 -#define ADC_CTL_CH3 0x00000003 // Input channel 3 - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum, - void (*pfnHandler)(void)); -extern void ADCIntUnregister(unsigned long ulBase, - unsigned long ulSequenceNum); -extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum); -extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum); -extern unsigned long ADCIntStatus(unsigned long ulBase, - unsigned long ulSequenceNum, - tBoolean bMasked); -extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum); -extern void ADCSequenceEnable(unsigned long ulBase, - unsigned long ulSequenceNum); -extern void ADCSequenceDisable(unsigned long ulBase, - unsigned long ulSequenceNum); -extern void ADCSequenceConfigure(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long ulTrigger, - unsigned long ulPriority); -extern void ADCSequenceStepConfigure(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long ulStep, - unsigned long ulConfig); -extern long ADCSequenceOverflow(unsigned long ulBase, - unsigned long ulSequenceNum); -extern long ADCSequenceUnderflow(unsigned long ulBase, - unsigned long ulSequenceNum); -extern long ADCSequenceDataGet(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long *pulBuffer); -extern void ADCProcessorTrigger(unsigned long ulBase, - unsigned long ulSequenceNum); -extern void ADCSoftwareOversampleConfigure(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long ulFactor); -extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long ulStep, - unsigned long ulConfig); -extern void ADCSoftwareOversampleDataGet(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long *pulBuffer, - unsigned long ulCount); - -#ifdef __cplusplus -} -#endif - -#endif // __ADC_H__ diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/asmdefs.h b/Demo/CORTEX_LM3S316_IAR/hw_include/asmdefs.h deleted file mode 100644 index 4a1018a64..000000000 --- a/Demo/CORTEX_LM3S316_IAR/hw_include/asmdefs.h +++ /dev/null @@ -1,130 +0,0 @@ -//***************************************************************************** -// -// asmdefs.h - Macros to allow assembly code be portable among toolchains. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 635 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __ASMDEFS_H__ -#define __ASMDEFS_H__ - -//***************************************************************************** -// -// The defines required for EW-ARM. -// -//***************************************************************************** -#ifdef ewarm - -// -// Section headers. -// -#define __TEXT__ rseg CODE:CODE(2) -#define __DATA__ rseg DATA:DATA(2) -#define __BSS__ rseg DATA:DATA(2) - -// -// Assembler nmenonics. -// -#define __ALIGN__ alignrom 4 -#define __END__ end -#define __EXPORT__ export -#define __IMPORT__ import -#define __LABEL__ -#define __STR__ dcb -#define __THUMB_LABEL__ -#define __WORD__ dcd - -#endif // ewarm - -//***************************************************************************** -// -// The defines required for GCC. -// -//***************************************************************************** -#ifdef gcc - -// -// The assembly code preamble required to put the assembler into the correct -// configuration. -// - .syntax unified - .thumb - -// -// Section headers. -// -#define __TEXT__ .text -#define __DATA__ .data -#define __BSS__ .bss - -// -// Assembler nmenonics. -// -#define __ALIGN__ .balign 4 -#define __END__ .end -#define __EXPORT__ .globl -#define __IMPORT__ .extern -#define __LABEL__ : -#define __STR__ .ascii -#define __THUMB_LABEL__ .thumb_func -#define __WORD__ .word - -#endif // gcc - -//***************************************************************************** -// -// The defines required for RV-MDK. -// -//***************************************************************************** -#ifdef rvmdk - -// -// The assembly code preamble required to put the assembler into the correct -// configuration. -// - thumb - require8 - preserve8 - -// -// Section headers. -// -#define __TEXT__ area ||.text||, code, readonly, align=2 -#define __DATA__ area ||.data||, data, align=2 -#define __BSS__ area ||.bss||, noinit, align=2 - -// -// Assembler nmenonics. -// -#define __ALIGN__ align 4 -#define __END__ end -#define __EXPORT__ export -#define __IMPORT__ import -#define __LABEL__ -#define __STR__ dcb -#define __THUMB_LABEL__ -#define __WORD__ dcd - -#endif // rvmdk - -#endif // __ASMDEF_H__ diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/comp.h b/Demo/CORTEX_LM3S316_IAR/hw_include/comp.h deleted file mode 100644 index 19eda38cc..000000000 --- a/Demo/CORTEX_LM3S316_IAR/hw_include/comp.h +++ /dev/null @@ -1,120 +0,0 @@ -//***************************************************************************** -// -// comp.h - Prototypes for the analog comparator driver. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 635 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __COMP_H__ -#define __COMP_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to ComparatorConfigure() as the ulConfig -// parameter. For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of -// the values may be selected and ORed together will values from the other -// groups. -// -//***************************************************************************** -#define COMP_TRIG_NONE 0x00000000 // No ADC trigger -#define COMP_TRIG_HIGH 0x00000880 // Trigger when high -#define COMP_TRIG_LOW 0x00000800 // Trigger when low -#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge -#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge -#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges -#define COMP_INT_HIGH 0x00000010 // Interrupt when high -#define COMP_INT_LOW 0x00000000 // Interrupt when low -#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge -#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge -#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges -#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin -#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin -#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference -#define COMP_OUTPUT_NONE 0x00000000 // No comparator output -#define COMP_OUTPUT_NORMAL 0x00000100 // Comparator output normal -#define COMP_OUTPUT_INVERT 0x00000102 // Comparator output inverted - -//***************************************************************************** -// -// Values that can be passed to ComparatorSetRef() as the ulRef parameter. -// -//***************************************************************************** -#define COMP_REF_OFF 0x00000000 // Turn off the internal reference -#define COMP_REF_0V 0x00000300 // Internal reference of 0V -#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V -#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V -#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V -#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V -#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V -#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V -#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V -#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V -#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V -#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V -#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V -#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V -#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V -#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V -#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V -#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V -#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V -#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V -#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V -#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V -#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V -#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V -#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V -#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V -#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V -#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V -#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp, - unsigned long ulConfig); -extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef); -extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp); -extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp, - void (*pfnHandler)(void)); -extern void ComparatorIntUnregister(unsigned long ulBase, - unsigned long ulComp); -extern void ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp); -extern void ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp); -extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp, - tBoolean bMasked); -extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp); - -#ifdef __cplusplus -} -#endif - -#endif // __COMP_H__ diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/cpu.h b/Demo/CORTEX_LM3S316_IAR/hw_include/cpu.h deleted file mode 100644 index 0a2e282c3..000000000 --- a/Demo/CORTEX_LM3S316_IAR/hw_include/cpu.h +++ /dev/null @@ -1,40 +0,0 @@ -//***************************************************************************** -// -// cpu.h - Prototypes for the CPU instruction wrapper functions. -// -// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 635 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __CPU_H__ -#define __CPU_H__ - -//***************************************************************************** -// -// Prototypes. -// -//***************************************************************************** -extern void CPUcpsid(void); -extern void CPUcpsie(void); -extern void CPUwfi(void); - -#endif // __CPU_H__ diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/cspy.c b/Demo/CORTEX_LM3S316_IAR/hw_include/cspy.c deleted file mode 100644 index 398ae5949..000000000 --- a/Demo/CORTEX_LM3S316_IAR/hw_include/cspy.c +++ /dev/null @@ -1,119 +0,0 @@ -//***************************************************************************** -// -// cspy.c - Routines for simply ignoring the debugger communciation APIs in -// C-Spy for now. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 635 of the Stellaris Driver Library. -// -//***************************************************************************** - -#include "diag.h" - -//***************************************************************************** -// -// Open a handle for stdio functions (both stdin and stdout). -// -//***************************************************************************** -int -DiagOpenStdio(void) -{ - return(-1); -} - -//***************************************************************************** -// -// Open a host file system file. -// -//***************************************************************************** -int -DiagOpen(const char *pcName, int iMode) -{ - return(-1); -} - -//***************************************************************************** -// -// Close a host file system file. -// -//***************************************************************************** -int -DiagClose(int iHandle) -{ - return(-1); -} - -//***************************************************************************** -// -// Write data to a host file system file. -// -//***************************************************************************** -int -DiagWrite(int iHandle, const char *pcBuf, unsigned long ulLen, int iMode) -{ - return(-1); -} - -//***************************************************************************** -// -// Read data from a host file system file. -// -//***************************************************************************** -int -DiagRead(int iHandle, char *pcBuf, unsigned long ulLen, int iMode) -{ - return(-1); -} - -//***************************************************************************** -// -// Get the length of a host file system file. -// -//***************************************************************************** -long -DiagFlen(int iHandle) -{ - return(-1); -} - -//***************************************************************************** -// -// Terminate the application. -// -//***************************************************************************** -void -DiagExit(int iRet) -{ - while(1) - { - } -} - -//***************************************************************************** -// -// Get the command line arguments from the debugger. -// -//***************************************************************************** -char * -DiagCommandString(char *pcBuf, unsigned long ulLen) -{ - return(0); -} diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/debug.h b/Demo/CORTEX_LM3S316_IAR/hw_include/debug.h deleted file mode 100644 index 83dbbf3c4..000000000 --- a/Demo/CORTEX_LM3S316_IAR/hw_include/debug.h +++ /dev/null @@ -1,56 +0,0 @@ -//***************************************************************************** -// -// debug.h - Macros for assisting debug of the driver library. -// -// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 635 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __DEBUG_H__ -#define __DEBUG_H__ - -//***************************************************************************** -// -// Prototype for the function that is called when an invalid argument is passed -// to an API. This is only used when doing a DEBUG build. -// -//***************************************************************************** -extern void __error__(char *pcFilename, unsigned long ulLine); - -//***************************************************************************** -// -// The ASSERT macro, which does the actual assertion checking. Typically, this -// will be for procedure arguments. -// -//***************************************************************************** -#ifdef DEBUG -#define ASSERT(expr) { \ - if(!(expr)) \ - { \ - __error__(__FILE__, __LINE__); \ - } \ - } -#else -#define ASSERT(expr) -#endif - -#endif // __DEBUG_H__ diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/diag.h b/Demo/CORTEX_LM3S316_IAR/hw_include/diag.h deleted file mode 100644 index 5eda186eb..000000000 --- a/Demo/CORTEX_LM3S316_IAR/hw_include/diag.h +++ /dev/null @@ -1,67 +0,0 @@ -//***************************************************************************** -// -// diag.h - Prototypes for the diagnostic functions. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 635 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __DIAG_H__ -#define __DIAG_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed as the iMode parater to DiagOpen, DiagRead, and -// DiagWrite. -// -//***************************************************************************** -#define OPEN_R 0 // read access -#define OPEN_W 4 // write access -#define OPEN_A 8 // append to file -#define OPEN_B 1 // binary access -#define OPEN_PLUS 2 // read and write access - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern int DiagOpenStdio(void); -extern int DiagOpen(const char *pcName, int iMode); -extern int DiagClose(int iHandle); -extern int DiagWrite(int iHandle, const char *pcBuf, unsigned long ulLen, - int iMode); -extern int DiagRead(int iHandle, char *pcBuf, unsigned long ulLen, int iMode); -extern long DiagFlen(int iHandle); -extern void DiagExit(int iRet); -extern char *DiagCommandString(char *pcBuf, unsigned long ulLen); - -#ifdef __cplusplus -} -#endif - -#endif // __DIAG_H__ diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/driverlib.r79 b/Demo/CORTEX_LM3S316_IAR/hw_include/driverlib.r79 deleted file mode 100644 index 188c42ebb..000000000 Binary files a/Demo/CORTEX_LM3S316_IAR/hw_include/driverlib.r79 and /dev/null differ diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/flash.h b/Demo/CORTEX_LM3S316_IAR/hw_include/flash.h deleted file mode 100644 index 72202763d..000000000 --- a/Demo/CORTEX_LM3S316_IAR/hw_include/flash.h +++ /dev/null @@ -1,75 +0,0 @@ -//***************************************************************************** -// -// flash.h - Prototypes for the flash driver. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 635 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __FLASH_H__ -#define __FLASH_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to FlashProtectSet(), and returned by -// FlashProtectGet(). -// -//***************************************************************************** -typedef enum -{ - FlashReadWrite, // Flash can be read and written - FlashReadOnly, // Flash can only be read - FlashExecuteOnly // Flash can only be executed -} -tFlashProtection; - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern unsigned long FlashUsecGet(void); -extern void FlashUsecSet(unsigned long ulClocks); -extern long FlashErase(unsigned long ulAddress); -extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress, - unsigned long ulCount); -extern tFlashProtection FlashProtectGet(unsigned long ulAddress); -extern long FlashProtectSet(unsigned long ulAddress, - tFlashProtection eProtect); -extern long FlashProtectSave(void); -extern void FlashIntRegister(void (*pfnHandler)(void)); -extern void FlashIntUnregister(void); -extern void FlashIntEnable(unsigned long ulIntFlags); -extern void FlashIntDisable(unsigned long ulIntFlags); -extern unsigned long FlashIntGetStatus(tBoolean bMasked); -extern void FlashIntClear(unsigned long ulIntFlags); - -#ifdef __cplusplus -} -#endif - -#endif // __FLASH_H__ diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/gpio.h b/Demo/CORTEX_LM3S316_IAR/hw_include/gpio.h deleted file mode 100644 index 598fec8a8..000000000 --- a/Demo/CORTEX_LM3S316_IAR/hw_include/gpio.h +++ /dev/null @@ -1,136 +0,0 @@ -//***************************************************************************** -// -// gpio.h - Defines and Macros for GPIO API. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 635 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __GPIO_H__ -#define __GPIO_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following values define the bit field for the ucPins argument to several -// of the APIs. -// -//***************************************************************************** -#define GPIO_PIN_0 0x00000001 // GPIO pin 0 -#define GPIO_PIN_1 0x00000002 // GPIO pin 1 -#define GPIO_PIN_2 0x00000004 // GPIO pin 2 -#define GPIO_PIN_3 0x00000008 // GPIO pin 3 -#define GPIO_PIN_4 0x00000010 // GPIO pin 4 -#define GPIO_PIN_5 0x00000020 // GPIO pin 5 -#define GPIO_PIN_6 0x00000040 // GPIO pin 6 -#define GPIO_PIN_7 0x00000080 // GPIO pin 7 - -//***************************************************************************** -// -// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and -// returned from GPIODirModeGet. -// -//***************************************************************************** -#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input -#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output -#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function - -//***************************************************************************** -// -// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and -// returned from GPIOIntTypeGet. -// -//***************************************************************************** -#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge -#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge -#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges -#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level -#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level - -//***************************************************************************** -// -// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter, -// and returned by GPIOPadConfigGet in the *pulStrength parameter. -// -//***************************************************************************** -#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength -#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength -#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength -#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control - -//***************************************************************************** -// -// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter, -// and returned by GPIOPadConfigGet in the *pulPadType parameter. -// -//***************************************************************************** -#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull -#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up -#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down -#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain -#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up -#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down -#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulPinIO); -extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin); -extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulIntType); -extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin); -extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulStrength, - unsigned long ulPadType); -extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin, - unsigned long *pulStrength, - unsigned long *pulPadType); -extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins); -extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked); -extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPortIntRegister(unsigned long ulPort, - void (*pfIntHandler)(void)); -extern void GPIOPortIntUnregister(unsigned long ulPort); -extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, - unsigned char ucVal); -extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins); - -#ifdef __cplusplus -} -#endif - -#endif // __GPIO_H__ diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/hw_adc.h b/Demo/CORTEX_LM3S316_IAR/hw_include/hw_adc.h deleted file mode 100644 index 36b820467..000000000 --- a/Demo/CORTEX_LM3S316_IAR/hw_include/hw_adc.h +++ /dev/null @@ -1,329 +0,0 @@ -//***************************************************************************** -// -// hw_adc.h - Macros used when accessing the ADC hardware. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 635 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_ADC_H__ -#define __HW_ADC_H__ - -//***************************************************************************** -// -// The following define the offsets of the ADC registers. -// -//***************************************************************************** -#define ADC_O_ACTSS 0x00000000 // Active sample register -#define ADC_O_RIS 0x00000004 // Raw interrupt status register -#define ADC_O_IM 0x00000008 // Interrupt mask register -#define ADC_O_ISC 0x0000000C // Interrupt status/clear register -#define ADC_O_OSTAT 0x00000010 // Overflow status register -#define ADC_O_EMUX 0x00000014 // Event multiplexer select reg. -#define ADC_O_USTAT 0x00000018 // Underflow status register -#define ADC_O_SSPRI 0x00000020 // Channel priority register -#define ADC_O_PSSI 0x00000028 // Processor sample initiate reg. -#define ADC_O_SSMUX0 0x00000040 // Multiplexer select 0 register -#define ADC_O_SSCTL0 0x00000044 // Sample sequence control 0 reg. -#define ADC_O_SSFIFO0 0x00000048 // Result FIFO 0 register -#define ADC_O_SSFSTAT0 0x0000004C // FIFO 0 status register -#define ADC_O_SSMUX1 0x00000060 // Multiplexer select 1 register -#define ADC_O_SSCTL1 0x00000064 // Sample sequence control 1 reg. -#define ADC_O_SSFIFO1 0x00000068 // Result FIFO 1 register -#define ADC_O_SSFSTAT1 0x0000006C // FIFO 1 status register -#define ADC_O_SSMUX2 0x00000080 // Multiplexer select 2 register -#define ADC_O_SSCTL2 0x00000084 // Sample sequence control 2 reg. -#define ADC_O_SSFIFO2 0x00000088 // Result FIFO 2 register -#define ADC_O_SSFSTAT2 0x0000008C // FIFO 2 status register -#define ADC_O_SSMUX3 0x000000A0 // Multiplexer select 3 register -#define ADC_O_SSCTL3 0x000000A4 // Sample sequence control 3 reg. -#define ADC_O_SSFIFO3 0x000000A8 // Result FIFO 3 register -#define ADC_O_SSFSTAT3 0x000000AC // FIFO 3 status register -#define ADC_O_TMLB 0x00000100 // Test mode loopback register - -//***************************************************************************** -// -// The following define the offsets of the ADC sequence registers. -// -//***************************************************************************** -#define ADC_O_SEQ 0x00000040 // Offset to the first sequence -#define ADC_O_SEQ_STEP 0x00000020 // Increment to the next sequence -#define ADC_O_X_SSMUX 0x00000000 // Multiplexer select register -#define ADC_O_X_SSCTL 0x00000004 // Sample sequence control register -#define ADC_O_X_SSFIFO 0x00000008 // Result FIFO register -#define ADC_O_X_SSFSTAT 0x0000000C // FIFO status register - -//***************************************************************************** -// -// The following define the bit fields in the ADC_ACTSS register. -// -//***************************************************************************** -#define ADC_ACTSS_ASEN3 0x00000008 // Sample sequence 3 enable -#define ADC_ACTSS_ASEN2 0x00000004 // Sample sequence 2 enable -#define ADC_ACTSS_ASEN1 0x00000002 // Sample sequence 1 enable -#define ADC_ACTSS_ASEN0 0x00000001 // Sample sequence 0 enable - -//***************************************************************************** -// -// The following define the bit fields in the ADC_RIS register. -// -//***************************************************************************** -#define ADC_RIS_INR3 0x00000008 // Sample sequence 3 interrupt -#define ADC_RIS_INR2 0x00000004 // Sample sequence 2 interrupt -#define ADC_RIS_INR1 0x00000002 // Sample sequence 1 interrupt -#define ADC_RIS_INR0 0x00000001 // Sample sequence 0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the ADC_IM register. -// -//***************************************************************************** -#define ADC_IM_MASK3 0x00000008 // Sample sequence 3 mask -#define ADC_IM_MASK2 0x00000004 // Sample sequence 2 mask -#define ADC_IM_MASK1 0x00000002 // Sample sequence 1 mask -#define ADC_IM_MASK0 0x00000001 // Sample sequence 0 mask - -//***************************************************************************** -// -// The following define the bit fields in the ADC_ISC register. -// -//***************************************************************************** -#define ADC_ISC_IN3 0x00000008 // Sample sequence 3 interrupt -#define ADC_ISC_IN2 0x00000004 // Sample sequence 2 interrupt -#define ADC_ISC_IN1 0x00000002 // Sample sequence 1 interrupt -#define ADC_ISC_IN0 0x00000001 // Sample sequence 0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the ADC_OSTAT register. -// -//***************************************************************************** -#define ADC_OSTAT_OV3 0x00000008 // Sample sequence 3 overflow -#define ADC_OSTAT_OV2 0x00000004 // Sample sequence 2 overflow -#define ADC_OSTAT_OV1 0x00000002 // Sample sequence 1 overflow -#define ADC_OSTAT_OV0 0x00000001 // Sample sequence 0 overflow - -//***************************************************************************** -// -// The following define the bit fields in the ADC_EMUX register. -// -//***************************************************************************** -#define ADC_EMUX_EM3_MASK 0x0000F000 // Event mux 3 mask -#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor event -#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog comparator 0 event -#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog comparator 1 event -#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog comparator 2 event -#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External event -#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer event -#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0 event -#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1 event -#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2 event -#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always event -#define ADC_EMUX_EM2_MASK 0x00000F00 // Event mux 2 mask -#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor event -#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog comparator 0 event -#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog comparator 1 event -#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog comparator 2 event -#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External event -#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer event -#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0 event -#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1 event -#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2 event -#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always event -#define ADC_EMUX_EM1_MASK 0x000000F0 // Event mux 1 mask -#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor event -#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog comparator 0 event -#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog comparator 1 event -#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog comparator 2 event -#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External event -#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer event -#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0 event -#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1 event -#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2 event -#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always event -#define ADC_EMUX_EM0_MASK 0x0000000F // Event mux 0 mask -#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor event -#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog comparator 0 event -#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog comparator 1 event -#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog comparator 2 event -#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External event -#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer event -#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0 event -#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1 event -#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2 event -#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always event -#define ADC_EMUX_EM0_SHIFT 0 // The shift for the first event -#define ADC_EMUX_EM1_SHIFT 4 // The shift for the second event -#define ADC_EMUX_EM2_SHIFT 8 // The shift for the third event -#define ADC_EMUX_EM3_SHIFT 12 // The shift for the fourth event - -//***************************************************************************** -// -// The following define the bit fields in the ADC_USTAT register. -// -//***************************************************************************** -#define ADC_USTAT_UV3 0x00000008 // Sample sequence 3 underflow -#define ADC_USTAT_UV2 0x00000004 // Sample sequence 2 underflow -#define ADC_USTAT_UV1 0x00000002 // Sample sequence 1 underflow -#define ADC_USTAT_UV0 0x00000001 // Sample sequence 0 underflow - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSPRI register. -// -//***************************************************************************** -#define ADC_SSPRI_SS3_MASK 0x00003000 // Sequencer 3 priority mask -#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority -#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority -#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority -#define ADC_SSPRI_SS2_MASK 0x00000300 // Sequencer 2 priority mask -#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority -#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority -#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority -#define ADC_SSPRI_SS1_MASK 0x00000030 // Sequencer 1 priority mask -#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority -#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority -#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority -#define ADC_SSPRI_SS0_MASK 0x00000003 // Sequencer 0 priority mask -#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority -#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority -#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority - -//***************************************************************************** -// -// The following define the bit fields in the ADC_PSSI register. -// -//***************************************************************************** -#define ADC_PSSI_SS3 0x00000008 // Trigger sample sequencer 3 -#define ADC_PSSI_SS2 0x00000004 // Trigger sample sequencer 2 -#define ADC_PSSI_SS1 0x00000002 // Trigger sample sequencer 1 -#define ADC_PSSI_SS0 0x00000001 // Trigger sample sequencer 0 - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSMUX0, ADC_SSMUX1, -// ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present in all -// registers. -// -//***************************************************************************** -#define ADC_SSMUX_MUX7_MASK 0x30000000 // 8th mux select mask -#define ADC_SSMUX_MUX6_MASK 0x03000000 // 7th mux select mask -#define ADC_SSMUX_MUX5_MASK 0x00300000 // 6th mux select mask -#define ADC_SSMUX_MUX4_MASK 0x00030000 // 5th mux select mask -#define ADC_SSMUX_MUX3_MASK 0x00003000 // 4th mux select mask -#define ADC_SSMUX_MUX2_MASK 0x00000300 // 3rd mux select mask -#define ADC_SSMUX_MUX1_MASK 0x00000030 // 2nd mux select mask -#define ADC_SSMUX_MUX0_MASK 0x00000003 // 1st mux select mask -#define ADC_SSMUX_MUX7_SHIFT 28 -#define ADC_SSMUX_MUX6_SHIFT 24 -#define ADC_SSMUX_MUX5_SHIFT 20 -#define ADC_SSMUX_MUX4_SHIFT 16 -#define ADC_SSMUX_MUX3_SHIFT 12 -#define ADC_SSMUX_MUX2_SHIFT 8 -#define ADC_SSMUX_MUX1_SHIFT 4 -#define ADC_SSMUX_MUX0_SHIFT 0 - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSCTL0, ADC_SSCTL1, -// ADC_SSCTL2, and ADC_SSCTL3 registers. Not all fields are present in all -// registers. -// -//***************************************************************************** -#define ADC_SSCTL_TS7 0x80000000 // 8th temperature sensor select -#define ADC_SSCTL_IE7 0x40000000 // 8th interrupt enable -#define ADC_SSCTL_END7 0x20000000 // 8th sequence end select -#define ADC_SSCTL_D7 0x10000000 // 8th differential select -#define ADC_SSCTL_TS6 0x08000000 // 7th temperature sensor select -#define ADC_SSCTL_IE6 0x04000000 // 7th interrupt enable -#define ADC_SSCTL_END6 0x02000000 // 7th sequence end select -#define ADC_SSCTL_D6 0x01000000 // 7th differential select -#define ADC_SSCTL_TS5 0x00800000 // 6th temperature sensor select -#define ADC_SSCTL_IE5 0x00400000 // 6th interrupt enable -#define ADC_SSCTL_END5 0x00200000 // 6th sequence end select -#define ADC_SSCTL_D5 0x00100000 // 6th differential select -#define ADC_SSCTL_TS4 0x00080000 // 5th temperature sensor select -#define ADC_SSCTL_IE4 0x00040000 // 5th interrupt enable -#define ADC_SSCTL_END4 0x00020000 // 5th sequence end select -#define ADC_SSCTL_D4 0x00010000 // 5th differential select -#define ADC_SSCTL_TS3 0x00008000 // 4th temperature sensor select -#define ADC_SSCTL_IE3 0x00004000 // 4th interrupt enable -#define ADC_SSCTL_END3 0x00002000 // 4th sequence end select -#define ADC_SSCTL_D3 0x00001000 // 4th differential select -#define ADC_SSCTL_TS2 0x00000800 // 3rd temperature sensor select -#define ADC_SSCTL_IE2 0x00000400 // 3rd interrupt enable -#define ADC_SSCTL_END2 0x00000200 // 3rd sequence end select -#define ADC_SSCTL_D2 0x00000100 // 3rd differential select -#define ADC_SSCTL_TS1 0x00000080 // 2nd temperature sensor select -#define ADC_SSCTL_IE1 0x00000040 // 2nd interrupt enable -#define ADC_SSCTL_END1 0x00000020 // 2nd sequence end select -#define ADC_SSCTL_D1 0x00000010 // 2nd differential select -#define ADC_SSCTL_TS0 0x00000008 // 1st temperature sensor select -#define ADC_SSCTL_IE0 0x00000004 // 1st interrupt enable -#define ADC_SSCTL_END0 0x00000002 // 1st sequence end select -#define ADC_SSCTL_D0 0x00000001 // 1st differential select - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSFIFO0, ADC_SSFIFO1, -// ADC_SSFIFO2, and ADC_SSFIFO3 registers. -// -//***************************************************************************** -#define ADC_SSFIFO_DATA_MASK 0x000003FF // Sample data -#define ADC_SSFIFO_DATA_SHIFT 0 - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSFSTAT0, ADC_SSFSTAT1, -// ADC_SSFSTAT2, and ADC_SSFSTAT3 registers. -// -//***************************************************************************** -#define ADC_SSFSTAT_FULL 0x00001000 // FIFO is full -#define ADC_SSFSTAT_EMPTY 0x00000100 // FIFO is empty -#define ADC_SSFSTAT_HPTR 0x000000F0 // FIFO head pointer -#define ADC_SSFSTAT_TPTR 0x0000000F // FIFO tail pointer - -//***************************************************************************** -// -// The following define the bit fields in the ADC_TMLB register. -// -//***************************************************************************** -#define ADC_TMLB_LB 0x00000001 // Loopback control signals - -//***************************************************************************** -// -// The following define the bit fields in the loopback ADC data. -// -//***************************************************************************** -#define ADC_LB_CNT_MASK 0x000003C0 // Sample counter mask -#define ADC_LB_CONT 0x00000020 // Continuation sample -#define ADC_LB_DIFF 0x00000010 // Differential sample -#define ADC_LB_TS 0x00000008 // Temperature sensor sample -#define ADC_LB_MUX_MASK 0x00000007 // Input channel number mask -#define ADC_LB_CNT_SHIFT 6 // Sample counter shift -#define ADC_LB_MUX_SHIFT 0 // Input channel number shift - -#endif // __HW_ADC_H__ diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/hw_comp.h b/Demo/CORTEX_LM3S316_IAR/hw_include/hw_comp.h deleted file mode 100644 index 02487e6e8..000000000 --- a/Demo/CORTEX_LM3S316_IAR/hw_include/hw_comp.h +++ /dev/null @@ -1,118 +0,0 @@ -//***************************************************************************** -// -// hw_comp.h - Macros used when accessing the comparator hardware. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 635 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_COMP_H__ -#define __HW_COMP_H__ - -//***************************************************************************** -// -// The following define the offsets of the comparator registers. -// -//***************************************************************************** -#define COMP_O_MIS 0x00000000 // Interrupt status register -#define COMP_O_RIS 0x00000004 // Raw interrupt status register -#define COMP_O_INTEN 0x00000008 // Interrupt enable register -#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg. -#define COMP_O_ACSTAT0 0x00000020 // Comp0 status register -#define COMP_O_ACCTL0 0x00000024 // Comp0 control register -#define COMP_O_ACSTAT1 0x00000040 // Comp1 status register -#define COMP_O_ACCTL1 0x00000044 // Comp1 control register -#define COMP_O_ACSTAT2 0x00000060 // Comp2 status register -#define COMP_O_ACCTL2 0x00000064 // Comp2 control register - -//***************************************************************************** -// -// The following define the bit fields in the COMP_MIS, COMP_RIS, and -// COMP_INTEN registers. -// -//***************************************************************************** -#define COMP_INT_2 0x00000004 // Comp2 interrupt -#define COMP_INT_1 0x00000002 // Comp1 interrupt -#define COMP_INT_0 0x00000001 // Comp0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the COMP_REFCTL register. -// -//***************************************************************************** -#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable -#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range -#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask -#define COMP_REFCTL_VREF_SHIFT 0 - -//***************************************************************************** -// -// The following define the bit fields in the COMP_ACSTAT0, COMP_ACSTAT1, and -// COMP_ACSTAT2 registers. -// -//***************************************************************************** -#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value - -//***************************************************************************** -// -// The following define the bit fields in the COMP_ACCTL0, COMP_ACCTL1, and -// COMP_ACCTL2 registers. -// -//***************************************************************************** -#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable -#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask -#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin -#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin -#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference -#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved -#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable -#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select -#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask -#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense -#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge -#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge -#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges -#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select -#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask -#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense -#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge -#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge -#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges -#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert - -//***************************************************************************** -// -// The following define the reset values for the comparator registers. -// -//***************************************************************************** -#define COMP_RV_MIS 0x00000000 // Interrupt status register -#define COMP_RV_RIS 0x00000000 // Raw interrupt status register -#define COMP_RV_INTEN 0x00000000 // Interrupt enable register -#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg. -#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register -#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register -#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register -#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register -#define COMP_RV_ACSTAT2 0x00000000 // Comp2 status register -#define COMP_RV_ACCTL2 0x00000000 // Comp2 control register - -#endif // __HW_COMP_H__ diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/hw_flash.h b/Demo/CORTEX_LM3S316_IAR/hw_include/hw_flash.h deleted file mode 100644 index 214355194..000000000 --- a/Demo/CORTEX_LM3S316_IAR/hw_include/hw_flash.h +++ /dev/null @@ -1,139 +0,0 @@ -//***************************************************************************** -// -// hw_flash.h - Macros used when accessing the flash controller. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 635 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_FLASH_H__ -#define __HW_FLASH_H__ - -//***************************************************************************** -// -// The following define the offsets of the FLASH registers. -// -//***************************************************************************** -#define FLASH_FMA 0x400FD000 // Memory address register -#define FLASH_FMD 0x400FD004 // Memory data register -#define FLASH_FMC 0x400FD008 // Memory control register -#define FLASH_FCRIS 0x400FD00c // Raw interrupt status register -#define FLASH_FCIM 0x400FD010 // Interrupt mask register -#define FLASH_FCMISC 0x400FD014 // Interrupt status register -#define FLASH_FMPRE 0x400FE130 // FLASH read protect register -#define FLASH_FMPPE 0x400FE134 // FLASH program protect register -#define FLASH_USECRL 0x400FE140 // uSec reload register - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FMC register. -// -//***************************************************************************** -#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask -#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key -#define FLASH_FMC_COMT 0x00000008 // Commit user register -#define FLASH_FMC_MERASE 0x00000004 // Mass erase FLASH -#define FLASH_FMC_ERASE 0x00000002 // Erase FLASH page -#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FCRIS register. -// -//***************************************************************************** -#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status -#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FCIM register. -// -//***************************************************************************** -#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask -#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FMIS register. -// -//***************************************************************************** -#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status -#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FMPRE and FLASH_FMPPE -// registers. -// -//***************************************************************************** -#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31 -#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30 -#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29 -#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28 -#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27 -#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26 -#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25 -#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24 -#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23 -#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22 -#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21 -#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20 -#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19 -#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18 -#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17 -#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16 -#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15 -#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14 -#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13 -#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12 -#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11 -#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10 -#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9 -#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8 -#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7 -#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6 -#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5 -#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4 -#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3 -#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2 -#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1 -#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0 - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_USECRL register. -// -//***************************************************************************** -#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec -#define FLASH_USECRL_SHIFT 0 - -//***************************************************************************** -// -// The erase size is the size of the FLASH block that is erased by an erase -// operation, and the protect size is the size of the FLASH block that is -// protected by each protection register. -// -//***************************************************************************** -#define FLASH_ERASE_SIZE 0x00000400 -#define FLASH_PROTECT_SIZE 0x00000800 - -#endif // __HW_FLASH_H__ diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/hw_gpio.h b/Demo/CORTEX_LM3S316_IAR/hw_include/hw_gpio.h deleted file mode 100644 index 2f85bbc27..000000000 --- a/Demo/CORTEX_LM3S316_IAR/hw_include/hw_gpio.h +++ /dev/null @@ -1,103 +0,0 @@ -//***************************************************************************** -// -// hw_gpio.h - Defines and Macros for GPIO hardware. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 635 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_GPIO_H__ -#define __HW_GPIO_H__ - -//***************************************************************************** -// -// GPIO Register Offsets. -// -//***************************************************************************** -#define GPIO_O_DATA 0x00000000 // Data register. -#define GPIO_O_DIR 0x00000400 // Data direction register. -#define GPIO_O_IS 0x00000404 // Interrupt sense register. -#define GPIO_O_IBE 0x00000408 // Interrupt both edges register. -#define GPIO_O_IEV 0x0000040C // Intterupt event register. -#define GPIO_O_IM 0x00000410 // Interrupt mask register. -#define GPIO_O_RIS 0x00000414 // Raw interrupt status register. -#define GPIO_O_MIS 0x00000418 // Masked interrupt status reg. -#define GPIO_O_ICR 0x0000041C // Interrupt clear register. -#define GPIO_O_AFSEL 0x00000420 // Mode control select register. -#define GPIO_O_DR2R 0x00000500 // 2ma drive select register. -#define GPIO_O_DR4R 0x00000504 // 4ma drive select register. -#define GPIO_O_DR8R 0x00000508 // 8ma drive select register. -#define GPIO_O_ODR 0x0000050C // Open drain select register. -#define GPIO_O_PUR 0x00000510 // Pull up select register. -#define GPIO_O_PDR 0x00000514 // Pull down select register. -#define GPIO_O_SLR 0x00000518 // Slew rate control enable reg. -#define GPIO_O_DEN 0x0000051C // Digital input enable register. -#define GPIO_O_PeriphID4 0x00000FD0 // -#define GPIO_O_PeriphID5 0x00000FD4 // -#define GPIO_O_PeriphID6 0x00000FD8 // -#define GPIO_O_PeriphID7 0x00000FDC // -#define GPIO_O_PeriphID0 0x00000FE0 // -#define GPIO_O_PeriphID1 0x00000FE4 // -#define GPIO_O_PeriphID2 0x00000FE8 // -#define GPIO_O_PeriphID3 0x00000FEC // -#define GPIO_O_PCellID0 0x00000FF0 // -#define GPIO_O_PCellID1 0x00000FF4 // -#define GPIO_O_PCellID2 0x00000FF8 // -#define GPIO_O_PCellID3 0x00000FFC // - -//***************************************************************************** -// -// GPIO Register reset values. -// -//***************************************************************************** -#define GPIO_RV_DATA 0x00000000 // Data register reset value. -#define GPIO_RV_DIR 0x00000000 // Data direction reg RV. -#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV. -#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV. -#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV. -#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV. -#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV. -#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV. -#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV. -#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV. -#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV. -#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV. -#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV. -#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV. -#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV. -#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV. -#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV. -#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV. -#define GPIO_RV_PeriphID4 0x00000000 // -#define GPIO_RV_PeriphID5 0x00000000 // -#define GPIO_RV_PeriphID6 0x00000000 // -#define GPIO_RV_PeriphID7 0x00000000 // -#define GPIO_RV_PeriphID0 0x00000061 // -#define GPIO_RV_PeriphID1 0x00000010 // -#define GPIO_RV_PeriphID2 0x00000004 // -#define GPIO_RV_PeriphID3 0x00000000 // -#define GPIO_RV_PCellID0 0x0000000D // -#define GPIO_RV_PCellID1 0x000000F0 // -#define GPIO_RV_PCellID2 0x00000005 // -#define GPIO_RV_PCellID3 0x000000B1 // - -#endif // __HW_GPIO_H__ diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/hw_i2c.h b/Demo/CORTEX_LM3S316_IAR/hw_include/hw_i2c.h deleted file mode 100644 index 2a5f4fd42..000000000 --- a/Demo/CORTEX_LM3S316_IAR/hw_include/hw_i2c.h +++ /dev/null @@ -1,189 +0,0 @@ -//***************************************************************************** -// -// hw_i2c.h - Macros used when accessing the I2C master and slave hardware. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 635 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_I2C_H__ -#define __HW_I2C_H__ - -//***************************************************************************** -// -// The following define the offsets of the I2C master registers. -// -//***************************************************************************** -#define I2C_MASTER_O_SA 0x00000000 // Slave address register -#define I2C_MASTER_O_CS 0x00000004 // Control and Status register -#define I2C_MASTER_O_DR 0x00000008 // Data register -#define I2C_MASTER_O_TPR 0x0000000C // Timer period register -#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register -#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register -#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg -#define I2C_MASTER_O_MICR 0x0000001c // Interrupt clear register -#define I2C_MASTER_O_CR 0x00000020 // Configuration register - -//***************************************************************************** -// -// The following define the offsets of the I2C slave registers. -// -//***************************************************************************** -#define I2C_SLAVE_O_OAR 0x00000000 // Own address register -#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register -#define I2C_SLAVE_O_DR 0x00000008 // Data register -#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register -#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register -#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg -#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register - -//***************************************************************************** -// -// The followng define the bit fields in the I2C master slave address register. -// -//***************************************************************************** -#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address -#define I2C_MASTER_SA_RS 0x00000001 // Receive/send -#define I2C_MASTER_SA_SA_SHIFT 1 - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Control and Status -// register. -// -//***************************************************************************** -#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde -#define I2C_MASTER_CS_STOP 0x00000004 // Stop -#define I2C_MASTER_CS_START 0x00000002 // Start -#define I2C_MASTER_CS_RUN 0x00000001 // Run -#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy -#define I2C_MASTER_CS_IDLE 0x00000020 // Idle -#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration -#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged -#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged -#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred -#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data -#define I2C_MASTER_CS_ERR_MASK 0x0000001C - -//***************************************************************************** -// -// The following define values used in determining the contents of the I2C -// Master Timer Period register. -// -//***************************************************************************** -#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period -#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period -#define I2C_SCL_STANDARD 100000 // SCL standard frequency -#define I2C_SCL_FAST 400000 // SCL fast frequency - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Interrupt Mask -// register. -// -//***************************************************************************** -#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Raw Interrupt Status -// register. -// -//***************************************************************************** -#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Masked Interrupt -// Status register. -// -//***************************************************************************** -#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Interrupt Clear -// register. -// -//***************************************************************************** -#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Configuration -// register. -// -//***************************************************************************** -#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable -#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable -#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Own Address register. -// -//***************************************************************************** -#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Control/Status -// register. -// -//***************************************************************************** -#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device -#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received -#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Interrupt Mask -// register. -// -//***************************************************************************** -#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Raw Interrupt Status -// register. -// -//***************************************************************************** -#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Masked Interrupt -// Status register. -// -//***************************************************************************** -#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Interrupt Clear -// register. -// -//***************************************************************************** -#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear - -#endif // __HW_I2C_H__ diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/hw_ints.h b/Demo/CORTEX_LM3S316_IAR/hw_include/hw_ints.h deleted file mode 100644 index 65ce1416d..000000000 --- a/Demo/CORTEX_LM3S316_IAR/hw_include/hw_ints.h +++ /dev/null @@ -1,96 +0,0 @@ -//***************************************************************************** -// -// hw_ints.h - Macros that define the interrupt assignment on Stellaris. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 635 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_INTS_H__ -#define __HW_INTS_H__ - -//***************************************************************************** -// -// The following define the fault assignments. -// -//***************************************************************************** -#define FAULT_NMI 2 // NMI fault -#define FAULT_HARD 3 // Hard fault -#define FAULT_MPU 4 // MPU fault -#define FAULT_BUS 5 // Bus fault -#define FAULT_USAGE 6 // Usage fault -#define FAULT_SVCALL 11 // SVCall -#define FAULT_DEBUG 12 // Debug monitor -#define FAULT_PENDSV 14 // PendSV -#define FAULT_SYSTICK 15 // System Tick - -//***************************************************************************** -// -// The following define the interrupt assignments. -// -//***************************************************************************** -#define INT_GPIOA 16 // GPIO Port A -#define INT_GPIOB 17 // GPIO Port B -#define INT_GPIOC 18 // GPIO Port C -#define INT_GPIOD 19 // GPIO Port D -#define INT_GPIOE 20 // GPIO Port E -#define INT_UART0 21 // UART0 Rx and Tx -#define INT_UART1 22 // UART1 Rx and Tx -#define INT_SSI 23 // SSI Rx and Tx -#define INT_I2C 24 // I2C Master and Slave -#define INT_PWM_FAULT 25 // PWM Fault -#define INT_PWM0 26 // PWM Generator 0 -#define INT_PWM1 27 // PWM Generator 1 -#define INT_PWM2 28 // PWM Generator 2 -#define INT_ADC0 30 // ADC Sequence 0 -#define INT_ADC1 31 // ADC Sequence 1 -#define INT_ADC2 32 // ADC Sequence 2 -#define INT_ADC3 33 // ADC Sequence 3 -#define INT_WATCHDOG 34 // Watchdog timer -#define INT_TIMER0A 35 // Timer 0 subtimer A -#define INT_TIMER0B 36 // Timer 0 subtimer B -#define INT_TIMER1A 37 // Timer 1 subtimer A -#define INT_TIMER1B 38 // Timer 1 subtimer B -#define INT_TIMER2A 39 // Timer 2 subtimer A -#define INT_TIMER2B 40 // Timer 2 subtimer B -#define INT_COMP0 41 // Analog Comparator 0 -#define INT_COMP1 42 // Analog Comparator 1 -#define INT_COMP2 43 // Analog Comparator 2 -#define INT_SYSCTL 44 // System Control (PLL, OSC, BO) -#define INT_FLASH 45 // FLASH Control - -//***************************************************************************** -// -// The total number of interrupts. -// -//***************************************************************************** -#define NUM_INTERRUPTS 46 - -//***************************************************************************** -// -// The total number of priority levels. -// -//***************************************************************************** -#define NUM_PRIORITY 8 -#define NUM_PRIORITY_BITS 3 - -#endif // __HW_INTS_H__ diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/hw_memmap.h b/Demo/CORTEX_LM3S316_IAR/hw_include/hw_memmap.h deleted file mode 100644 index 9f701fc97..000000000 --- a/Demo/CORTEX_LM3S316_IAR/hw_include/hw_memmap.h +++ /dev/null @@ -1,63 +0,0 @@ -//***************************************************************************** -// -// hw_memmap.h - Macros defining the memory map of Stellaris. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 635 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_MEMMAP_H__ -#define __HW_MEMMAP_H__ - -//***************************************************************************** -// -// The following define the base address of the memories and peripherals. -// -//***************************************************************************** -#define FLASH_BASE 0x00000000 // FLASH memory -#define SRAM_BASE 0x20000000 // SRAM memory -#define WATCHDOG_BASE 0x40000000 // Watchdog -#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A -#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B -#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C -#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D -#define SSI_BASE 0x40008000 // SSI -#define UART0_BASE 0x4000C000 // UART0 -#define UART1_BASE 0x4000D000 // UART1 -#define I2C_MASTER_BASE 0x40020000 // I2C Master -#define I2C_SLAVE_BASE 0x40020800 // I2C Slave -#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E -#define PWM_BASE 0x40028000 // PWM -#define TIMER0_BASE 0x40030000 // Timer0 -#define TIMER1_BASE 0x40031000 // Timer1 -#define TIMER2_BASE 0x40032000 // Timer2 -#define ADC_BASE 0x40038000 // ADC -#define COMP_BASE 0x4003C000 // Analog comparators -#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller -#define SYSCTL_BASE 0x400FE000 // System Control -#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell -#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace -#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint -#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl -#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit - -#endif // __HW_MEMMAP_H__ diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/hw_nvic.h b/Demo/CORTEX_LM3S316_IAR/hw_include/hw_nvic.h deleted file mode 100644 index 9e3154c88..000000000 --- a/Demo/CORTEX_LM3S316_IAR/hw_include/hw_nvic.h +++ /dev/null @@ -1,830 +0,0 @@ -//***************************************************************************** -// -// hw_nvic.h - Macros used when accessing the NVIC hardware. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 635 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_NVIC_H__ -#define __HW_NVIC_H__ - -//***************************************************************************** -// -// The following define the addresses of the NVIC registers. -// -//***************************************************************************** -#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg. -#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg. -#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register -#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register -#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg. -#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register -#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg. -#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register -#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg. -#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register -#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register -#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register -#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register -#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register -#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register -#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register -#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register -#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register -#define NVIC_CPUID 0xE000ED00 // CPUID Base Register -#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register -#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register -#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg. -#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register -#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register -#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority -#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority -#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority -#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State -#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg. -#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register -#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register -#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register -#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register -#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register -#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register -#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register -#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register -#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg. -#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg. -#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select -#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data -#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control -#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg. - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_INT_TYPE register. -// -//***************************************************************************** -#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) -#define NVIC_INT_TYPE_LINES_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_CTRL register. -// -//***************************************************************************** -#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag -#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source -#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable -#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_RELOAD register. -// -//***************************************************************************** -#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value -#define NVIC_ST_RELOAD_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_CURRENT register. -// -//***************************************************************************** -#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value -#define NVIC_ST_CURRENT_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_CAL register. -// -//***************************************************************************** -#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock -#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew -#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value -#define NVIC_ST_CAL_ONEMS_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_EN0 register. -// -//***************************************************************************** -#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable -#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable -#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable -#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable -#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable -#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable -#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable -#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable -#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable -#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable -#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable -#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable -#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable -#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable -#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable -#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable -#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable -#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable -#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable -#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable -#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable -#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable -#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable -#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable -#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable -#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable -#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable -#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable -#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable -#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable -#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable -#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DIS0 register. -// -//***************************************************************************** -#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable -#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable -#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable -#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable -#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable -#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable -#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable -#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable -#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable -#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable -#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable -#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable -#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable -#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable -#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable -#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable -#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable -#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable -#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable -#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable -#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable -#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable -#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable -#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable -#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable -#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable -#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable -#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable -#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable -#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable -#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable -#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PEND0 register. -// -//***************************************************************************** -#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend -#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend -#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend -#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend -#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend -#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend -#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend -#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend -#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend -#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend -#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend -#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend -#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend -#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend -#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend -#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend -#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend -#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend -#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend -#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend -#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend -#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend -#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend -#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend -#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend -#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend -#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend -#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend -#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend -#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend -#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend -#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_UNPEND0 register. -// -//***************************************************************************** -#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend -#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend -#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend -#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend -#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend -#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend -#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend -#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend -#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend -#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend -#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend -#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend -#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend -#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend -#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend -#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend -#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend -#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend -#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend -#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend -#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend -#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend -#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend -#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend -#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend -#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend -#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend -#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend -#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend -#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend -#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend -#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ACTIVE0 register. -// -//***************************************************************************** -#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active -#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active -#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active -#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active -#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active -#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active -#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active -#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active -#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active -#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active -#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active -#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active -#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active -#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active -#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active -#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active -#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active -#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active -#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active -#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active -#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active -#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active -#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active -#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active -#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active -#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active -#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active -#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active -#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active -#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active -#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active -#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI0 register. -// -//***************************************************************************** -#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask -#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask -#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask -#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask -#define NVIC_PRI0_INT3_S 24 -#define NVIC_PRI0_INT2_S 16 -#define NVIC_PRI0_INT1_S 8 -#define NVIC_PRI0_INT0_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI1 register. -// -//***************************************************************************** -#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask -#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask -#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask -#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask -#define NVIC_PRI1_INT7_S 24 -#define NVIC_PRI1_INT6_S 16 -#define NVIC_PRI1_INT5_S 8 -#define NVIC_PRI1_INT4_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI2 register. -// -//***************************************************************************** -#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask -#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask -#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask -#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask -#define NVIC_PRI2_INT11_S 24 -#define NVIC_PRI2_INT10_S 16 -#define NVIC_PRI2_INT9_S 8 -#define NVIC_PRI2_INT8_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI3 register. -// -//***************************************************************************** -#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask -#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask -#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask -#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask -#define NVIC_PRI3_INT15_S 24 -#define NVIC_PRI3_INT14_S 16 -#define NVIC_PRI3_INT13_S 8 -#define NVIC_PRI3_INT12_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI4 register. -// -//***************************************************************************** -#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask -#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask -#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask -#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask -#define NVIC_PRI4_INT19_S 24 -#define NVIC_PRI4_INT18_S 16 -#define NVIC_PRI4_INT17_S 8 -#define NVIC_PRI4_INT16_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI5 register. -// -//***************************************************************************** -#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask -#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask -#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask -#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask -#define NVIC_PRI5_INT23_S 24 -#define NVIC_PRI5_INT22_S 16 -#define NVIC_PRI5_INT21_S 8 -#define NVIC_PRI5_INT20_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI6 register. -// -//***************************************************************************** -#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask -#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask -#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask -#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask -#define NVIC_PRI6_INT27_S 24 -#define NVIC_PRI6_INT26_S 16 -#define NVIC_PRI6_INT25_S 8 -#define NVIC_PRI6_INT24_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI7 register. -// -//***************************************************************************** -#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask -#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask -#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask -#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask -#define NVIC_PRI7_INT31_S 24 -#define NVIC_PRI7_INT30_S 16 -#define NVIC_PRI7_INT29_S 8 -#define NVIC_PRI7_INT28_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_CPUID register. -// -//***************************************************************************** -#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer -#define NVIC_CPUID_VAR_M 0x00F00000 // Variant -#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number -#define NVIC_CPUID_REV_M 0x0000000F // Revision - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_INT_CTRL register. -// -//***************************************************************************** -#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI -#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV -#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV -#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling -#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending -#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception -#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base -#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception -#define NVIC_INT_CTRL_VEC_PEN_S 12 -#define NVIC_INT_CTRL_VEC_ACT_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_VTABLE register. -// -//***************************************************************************** -#define NVIC_VTABLE_BASE 0x20000000 // Vector table base -#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset -#define NVIC_VTABLE_OFFSET_S 8 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_APINT register. -// -//***************************************************************************** -#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask -#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key -#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess -#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group -#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split -#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split -#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split -#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split -#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split -#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split -#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split -#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split -#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request -#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info -#define NVIC_APINT_VECT_RESET 0x00000001 // System reset - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_CTRL register. -// -//***************************************************************************** -#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend -#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable -#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_CFG_CTRL register. -// -//***************************************************************************** -#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault -#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0 -#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access -#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger -#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger -#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_PRI1 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler -#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler -#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler -#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler -#define NVIC_SYS_PRI1_USAGE_S 16 -#define NVIC_SYS_PRI1_BUS_S 8 -#define NVIC_SYS_PRI1_MEM_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_PRI2 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler -#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers -#define NVIC_SYS_PRI2_SVC_S 24 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_PRI3 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler -#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler -#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler -#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler -#define NVIC_SYS_PRI3_TICK_S 24 -#define NVIC_SYS_PRI3_PENDSV_S 16 -#define NVIC_SYS_PRI3_DEBUG_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_HND_CTRL register. -// -//***************************************************************************** -#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable -#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable -#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable -#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended -#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended -#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active -#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active -#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active -#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active -#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active -#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active -#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_FAULT_STAT register. -// -//***************************************************************************** -#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault -#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault -#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault -#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault -#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault -#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault -#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid -#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault -#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault -#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error -#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error -#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault -#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid -#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation -#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation -#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation -#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_HFAULT_STAT register. -// -//***************************************************************************** -#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event -#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler -#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DEBUG_STAT register. -// -//***************************************************************************** -#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted -#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch -#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match -#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction -#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MM_ADDR register. -// -//***************************************************************************** -#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address -#define NVIC_MM_ADDR_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_FAULT_ADDR register. -// -//***************************************************************************** -#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address -#define NVIC_FAULT_ADDR_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_EXC_STACK register. -// -//***************************************************************************** -#define NVIC_EXC_STACK_DEEP 0x00000001 // Exception stack - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_EXC_NUM register. -// -//***************************************************************************** -#define NVIC_EXC_NUM_M 0x000003FF // Exception number -#define NVIC_EXC_NUM_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_COPRO register. -// -//***************************************************************************** -#define NVIC_COPRO_15_M 0xC0000000 // Coprocessor 15 access mask -#define NVIC_COPRO_15_DENIED 0x00000000 // Coprocessor 15 access denied -#define NVIC_COPRO_15_PRIV 0x40000000 // Coprocessor 15 privileged addess -#define NVIC_COPRO_15_FULL 0xC0000000 // Coprocessor 15 full access -#define NVIC_COPRO_14_M 0x30000000 // Coprocessor 14 access mask -#define NVIC_COPRO_14_DENIED 0x00000000 // Coprocessor 14 access denied -#define NVIC_COPRO_14_PRIV 0x10000000 // Coprocessor 14 privileged addess -#define NVIC_COPRO_14_FULL 0x30000000 // Coprocessor 14 full access -#define NVIC_COPRO_13_M 0x0C000000 // Coprocessor 13 access mask -#define NVIC_COPRO_13_DENIED 0x00000000 // Coprocessor 13 access denied -#define NVIC_COPRO_13_PRIV 0x04000000 // Coprocessor 13 privileged addess -#define NVIC_COPRO_13_FULL 0x0C000000 // Coprocessor 13 full access -#define NVIC_COPRO_12_M 0x03000000 // Coprocessor 12 access mask -#define NVIC_COPRO_12_DENIED 0x00000000 // Coprocessor 12 access denied -#define NVIC_COPRO_12_PRIV 0x01000000 // Coprocessor 12 privileged addess -#define NVIC_COPRO_12_FULL 0x03000000 // Coprocessor 12 full access -#define NVIC_COPRO_11_M 0x00C00000 // Coprocessor 11 access mask -#define NVIC_COPRO_11_DENIED 0x00000000 // Coprocessor 11 access denied -#define NVIC_COPRO_11_PRIV 0x00400000 // Coprocessor 11 privileged addess -#define NVIC_COPRO_11_FULL 0x00C00000 // Coprocessor 11 full access -#define NVIC_COPRO_10_M 0x00300000 // Coprocessor 10 access mask -#define NVIC_COPRO_10_DENIED 0x00000000 // Coprocessor 10 access denied -#define NVIC_COPRO_10_PRIV 0x00100000 // Coprocessor 10 privileged addess -#define NVIC_COPRO_10_FULL 0x00300000 // Coprocessor 10 full access -#define NVIC_COPRO_9_M 0x000C0000 // Coprocessor 9 access mask -#define NVIC_COPRO_9_DENIED 0x00000000 // Coprocessor 9 access denied -#define NVIC_COPRO_9_PRIV 0x00040000 // Coprocessor 9 privileged addess -#define NVIC_COPRO_9_FULL 0x000C0000 // Coprocessor 9 full access -#define NVIC_COPRO_8_M 0x00030000 // Coprocessor 8 access mask -#define NVIC_COPRO_8_DENIED 0x00000000 // Coprocessor 8 access denied -#define NVIC_COPRO_8_PRIV 0x00010000 // Coprocessor 8 privileged addess -#define NVIC_COPRO_8_FULL 0x00030000 // Coprocessor 8 full access -#define NVIC_COPRO_7_M 0x0000C000 // Coprocessor 7 access mask -#define NVIC_COPRO_7_DENIED 0x00000000 // Coprocessor 7 access denied -#define NVIC_COPRO_7_PRIV 0x00004000 // Coprocessor 7 privileged addess -#define NVIC_COPRO_7_FULL 0x0000C000 // Coprocessor 7 full access -#define NVIC_COPRO_6_M 0x00003000 // Coprocessor 6 access mask -#define NVIC_COPRO_6_DENIED 0x00000000 // Coprocessor 6 access denied -#define NVIC_COPRO_6_PRIV 0x00001000 // Coprocessor 6 privileged addess -#define NVIC_COPRO_6_FULL 0x00003000 // Coprocessor 6 full access -#define NVIC_COPRO_5_M 0x00000C00 // Coprocessor 5 access mask -#define NVIC_COPRO_5_DENIED 0x00000000 // Coprocessor 5 access denied -#define NVIC_COPRO_5_PRIV 0x00000400 // Coprocessor 5 privileged addess -#define NVIC_COPRO_5_FULL 0x00000C00 // Coprocessor 5 full access -#define NVIC_COPRO_4_M 0x00000300 // Coprocessor 4 access mask -#define NVIC_COPRO_4_DENIED 0x00000000 // Coprocessor 4 access denied -#define NVIC_COPRO_4_PRIV 0x00000100 // Coprocessor 4 privileged addess -#define NVIC_COPRO_4_FULL 0x00000300 // Coprocessor 4 full access -#define NVIC_COPRO_3_M 0x000000C0 // Coprocessor 3 access mask -#define NVIC_COPRO_3_DENIED 0x00000000 // Coprocessor 3 access denied -#define NVIC_COPRO_3_PRIV 0x00000040 // Coprocessor 3 privileged addess -#define NVIC_COPRO_3_FULL 0x000000C0 // Coprocessor 3 full access -#define NVIC_COPRO_2_M 0x00000030 // Coprocessor 2 access mask -#define NVIC_COPRO_2_DENIED 0x00000000 // Coprocessor 2 access denied -#define NVIC_COPRO_2_PRIV 0x00000010 // Coprocessor 2 privileged addess -#define NVIC_COPRO_2_FULL 0x00000030 // Coprocessor 2 full access -#define NVIC_COPRO_1_M 0x0000000C // Coprocessor 1 access mask -#define NVIC_COPRO_1_DENIED 0x00000000 // Coprocessor 1 access denied -#define NVIC_COPRO_1_PRIV 0x00000004 // Coprocessor 1 privileged addess -#define NVIC_COPRO_1_FULL 0x0000000C // Coprocessor 1 full access -#define NVIC_COPRO_0_M 0x00000003 // Coprocessor 0 access mask -#define NVIC_COPRO_0_DENIED 0x00000000 // Coprocessor 0 access denied -#define NVIC_COPRO_0_PRIV 0x00000001 // Coprocessor 0 privileged addess -#define NVIC_COPRO_0_FULL 0x00000003 // Coprocessor 0 full access - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_TYPE register. -// -//***************************************************************************** -#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions -#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions -#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU -#define NVIC_MPU_TYPE_IREGION_S 16 -#define NVIC_MPU_TYPE_DREGION_S 8 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_CTRL register. -// -//***************************************************************************** -#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults -#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_NUMBER register. -// -//***************************************************************************** -#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access -#define NVIC_MPU_NUMBER_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_BASE register. -// -//***************************************************************************** -#define NVIC_MPU_BASE_ADDR_M 0xFFFFFF00 // Base address -#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid -#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number -#define NVIC_MPU_BASE_ADDR_S 8 -#define NVIC_MPU_BASE_REGION_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_ATTR register. -// -//***************************************************************************** -#define NVIC_MPU_ATTR_ATTRS 0xFFFF0000 // Attributes -#define NVIC_MPU_ATTR_SRD 0x0000FF00 // Sub-region disable -#define NVIC_MPU_ATTR_SZENABLE 0x000000FF // Region size - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_CTRL register. -// -//***************************************************************************** -#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask -#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key -#define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor -#define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request -#define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable -#define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core -#define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping -#define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt -#define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available -#define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up -#define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core -#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping -#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core -#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core -#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_XFER register. -// -//***************************************************************************** -#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read -#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register -#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 -#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 -#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 -#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 -#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 -#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 -#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 -#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 -#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 -#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 -#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 -#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 -#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 -#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 -#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 -#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 -#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register -#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP -#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP -#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP -#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_DATA register. -// -//***************************************************************************** -#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache -#define NVIC_DBG_DATA_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_INT register. -// -//***************************************************************************** -#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault -#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors -#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error -#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state -#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check -#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error -#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault -#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status -#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset -#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending -#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SW_TRIG register. -// -//***************************************************************************** -#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger -#define NVIC_SW_TRIG_INTID_S 0 - -#endif // __HW_NVIC_H__ diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/hw_pwm.h b/Demo/CORTEX_LM3S316_IAR/hw_include/hw_pwm.h deleted file mode 100644 index b14172acf..000000000 --- a/Demo/CORTEX_LM3S316_IAR/hw_include/hw_pwm.h +++ /dev/null @@ -1,260 +0,0 @@ -//***************************************************************************** -// -// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 635 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_PWM_H__ -#define __HW_PWM_H__ - -//***************************************************************************** -// -// PWM Module Register Offsets. -// -//***************************************************************************** -#define PWM_O_CTL 0x00000000 // PWM Master Control register -#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync register -#define PWM_O_ENABLE 0x00000008 // PWM Output Enable register -#define PWM_O_INVERT 0x0000000C // PWM Output Inversion register -#define PWM_O_FAULT 0x00000010 // PWM Output Fault register -#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable register -#define PWM_O_RIS 0x00000018 // PWM Interrupt Raw Status reg. -#define PWM_O_ISC 0x0000001C // PWM Interrupt Status register -#define PWM_O_STATUS 0x00000020 // PWM Status register - -//***************************************************************************** -// -// The following define the bit fields in the PWM Master Control register. -// -//***************************************************************************** -#define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2 -#define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1 -#define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0 - -//***************************************************************************** -// -// The following define the bit fields in the PWM Time Base Sync register. -// -//***************************************************************************** -#define PWM_SYNC_SYNC2 0x00000004 // Reset generator 2 counter -#define PWM_SYNC_SYNC1 0x00000002 // Reset generator 1 counter -#define PWM_SYNC_SYNC0 0x00000001 // Reset generator 0 counter - -//***************************************************************************** -// -// The following define the bit fields in the PWM Output Enable register. -// -//***************************************************************************** -#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 pin enable -#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 pin enable -#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 pin enable -#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 pin enable -#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 pin enable -#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 pin enable - -//***************************************************************************** -// -// The following define the bit fields in the PWM Inversion register. -// -//***************************************************************************** -#define PWM_INVERT_PWM5INV 0x00000020 // PWM5 pin invert -#define PWM_INVERT_PWM4INV 0x00000010 // PWM4 pin invert -#define PWM_INVERT_PWM3INV 0x00000008 // PWM3 pin invert -#define PWM_INVERT_PWM2INV 0x00000004 // PWM2 pin invert -#define PWM_INVERT_PWM1INV 0x00000002 // PWM1 pin invert -#define PWM_INVERT_PWM0INV 0x00000001 // PWM0 pin invert - -//***************************************************************************** -// -// The following define the bit fields in the PWM Fault register. -// -//***************************************************************************** -#define PWM_FAULT_FAULT5 0x00000020 // PWM5 pin fault -#define PWM_FAULT_FAULT4 0x00000010 // PWM5 pin fault -#define PWM_FAULT_FAULT3 0x00000008 // PWM5 pin fault -#define PWM_FAULT_FAULT2 0x00000004 // PWM5 pin fault -#define PWM_FAULT_FAULT1 0x00000002 // PWM5 pin fault -#define PWM_FAULT_FAULT0 0x00000001 // PWM5 pin fault - -//***************************************************************************** -// -// PWM Interrupt Register bit definitions. -// -//***************************************************************************** -#define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending - -//***************************************************************************** -// -// The following define the bit fields in the PWM Status register. -// -//***************************************************************************** -#define PWM_STATUS_FAULT 0x00000001 // Fault status - -//***************************************************************************** -// -// PWM Generator standard offsets. -// -//***************************************************************************** -#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base -#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base -#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base - -#define PWM_O_X_CTL 0x00000000 // Gen Control Reg -#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg -#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg -#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg -#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg -#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg -#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg -#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg -#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg -#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg -#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg -#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg -#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg - -//***************************************************************************** -// -// PWM_X Control Register bit definitions. -// -//***************************************************************************** -#define PWM_X_CTL_ENABLE 0x00000001 // Master enable for gen block -#define PWM_X_CTL_MODE 0x00000002 // Counter mode, down or up/down -#define PWM_X_CTL_DEBUG 0x00000004 // Debug mode -#define PWM_X_CTL_LOADUPD 0x00000008 // Update mode for the load reg -#define PWM_X_CTL_CMPAUPD 0x00000010 // Update mode for comp A reg -#define PWM_X_CTL_CMPBUPD 0x00000020 // Update mode for comp B reg - -//***************************************************************************** -// -// PWM_X Interrupt/Trigger Enable Register bit definitions. -// -//***************************************************************************** -#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Int if COUNT = 0 -#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Int if COUNT = LOAD -#define PWM_X_INTEN_INTCMPAU 0x00000004 // Int if COUNT = CMPA U -#define PWM_X_INTEN_INTCMPAD 0x00000008 // Int if COUNT = CMPA D -#define PWM_X_INTEN_INTCMPBU 0x00000010 // Int if COUNT = CMPA U -#define PWM_X_INTEN_INTCMPBD 0x00000020 // Int if COUNT = CMPA D -#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trig if COUNT = 0 -#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trig if COUNT = LOAD -#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trig if COUNT = CMPA U -#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trig if COUNT = CMPA D -#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trig if COUNT = CMPA U -#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trig if COUNT = CMPA D - -//***************************************************************************** -// -// PWM_X Raw Interrupt Status Register bit definitions. -// -//***************************************************************************** -#define PWM_X_RIS_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 int -#define PWM_X_RIS_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD int -#define PWM_X_RIS_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U int -#define PWM_X_RIS_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D int -#define PWM_X_RIS_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U int -#define PWM_X_RIS_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D int - -//***************************************************************************** -// -// PWM_X Interrupt Status Register bit definitions. -// -//***************************************************************************** -#define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received -#define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd -#define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd -#define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd -#define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd -#define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd - -//***************************************************************************** -// -// PWM_X Generator A/B Control Register bit definitions. -// -//***************************************************************************** -#define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0 -#define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD -#define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U -#define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D -#define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U -#define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D - -//***************************************************************************** -// -// PWM_X Generator A/B Control Register action definitions. -// -//***************************************************************************** -#define PWM_GEN_ACT_NONE 0x0 // Do nothing -#define PWM_GEN_ACT_INV 0x1 // Invert the output signal -#define PWM_GEN_ACT_ZERO 0x2 // Set the output signal to zero -#define PWM_GEN_ACT_ONE 0x3 // Set the output signal to one -#define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action -#define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action -#define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action -#define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action -#define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action -#define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action - -//***************************************************************************** -// -// PWM_X Dead Band Control Register bit definitions. -// -//***************************************************************************** -#define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion - -//***************************************************************************** -// -// PWM Register reset values. -// -//***************************************************************************** -#define PWM_RV_CTL 0x00000000 // Master control of the PWM module -#define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators -#define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM - // output pins -#define PWM_RV_INVERT 0x00000000 // Inversion control for - // PWM output pins -#define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM - // output pins -#define PWM_RV_INTEN 0x00000000 // Interrupt enable -#define PWM_RV_RIS 0x00000000 // Raw interrupt status -#define PWM_RV_ISC 0x00000000 // Interrupt status and clearing -#define PWM_RV_STATUS 0x00000000 // Status -#define PWM_RV_X_CTL 0x00000000 // Master control of the PWM - // generator block -#define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable -#define PWM_RV_X_RIS 0x00000000 // Raw interrupt status -#define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing -#define PWM_RV_X_LOAD 0x00000000 // The load value for the counter -#define PWM_RV_X_COUNT 0x00000000 // The current counter value -#define PWM_RV_X_CMPA 0x00000000 // The comparator A value -#define PWM_RV_X_CMPB 0x00000000 // The comparator B value -#define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A -#define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B -#define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator -#define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay - // count -#define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay - // count - -#endif // __HW_PWM_H__ diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/hw_ssi.h b/Demo/CORTEX_LM3S316_IAR/hw_include/hw_ssi.h deleted file mode 100644 index c8a18fc29..000000000 --- a/Demo/CORTEX_LM3S316_IAR/hw_include/hw_ssi.h +++ /dev/null @@ -1,120 +0,0 @@ -//***************************************************************************** -// -// hw_ssi.h - Macros used when accessing the SSI hardware. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 635 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_SSI_H__ -#define __HW_SSI_H__ - -//***************************************************************************** -// -// The following define the offsets of the SSI registers. -// -//***************************************************************************** -#define SSI_O_CR0 0x00000000 // Control register 0 -#define SSI_O_CR1 0x00000004 // Control register 1 -#define SSI_O_DR 0x00000008 // Data register -#define SSI_O_SR 0x0000000C // Status register -#define SSI_O_CPSR 0x00000010 // Clock prescale register -#define SSI_O_IM 0x00000014 // Int mask set and clear register -#define SSI_O_RIS 0x00000018 // Raw interrupt register -#define SSI_O_MIS 0x0000001C // Masked interrupt register -#define SSI_O_ICR 0x00000020 // Interrupt clear register - -//***************************************************************************** -// -// The following define the bit fields in the SSI Control register 0. -// -//***************************************************************************** -#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate -#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase -#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity -#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask -#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format -#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format -#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format -#define SSI_CR0_DSS 0x0000000F // Data size select -#define SSI_CR0_DSS_4 0x00000003 // 4 bit data -#define SSI_CR0_DSS_5 0x00000004 // 5 bit data -#define SSI_CR0_DSS_6 0x00000005 // 6 bit data -#define SSI_CR0_DSS_7 0x00000006 // 7 bit data -#define SSI_CR0_DSS_8 0x00000007 // 8 bit data -#define SSI_CR0_DSS_9 0x00000008 // 9 bit data -#define SSI_CR0_DSS_10 0x00000009 // 10 bit data -#define SSI_CR0_DSS_11 0x0000000A // 11 bit data -#define SSI_CR0_DSS_12 0x0000000B // 12 bit data -#define SSI_CR0_DSS_13 0x0000000C // 13 bit data -#define SSI_CR0_DSS_14 0x0000000D // 14 bit data -#define SSI_CR0_DSS_15 0x0000000E // 15 bit data -#define SSI_CR0_DSS_16 0x0000000F // 16 bit data - -//***************************************************************************** -// -// The following define the bit fields in the SSI Control register 1. -// -//***************************************************************************** -#define SSI_CR1_SOD 0x00000008 // Slave mode output disable -#define SSI_CR1_MS 0x00000004 // Master or slave mode select -#define SSI_CR1_SSE 0x00000002 // Sync serial port enable -#define SSI_CR1_LBM 0x00000001 // Loopback mode - -//***************************************************************************** -// -// The following define the bit fields in the SSI Status register. -// -//***************************************************************************** -#define SSI_SR_BSY 0x00000010 // SSI busy -#define SSI_SR_RFF 0x00000008 // RX FIFO full -#define SSI_SR_RNE 0x00000004 // RX FIFO not empty -#define SSI_SR_TNF 0x00000002 // TX FIFO not full -#define SSI_SR_TFE 0x00000001 // TX FIFO empty - -//***************************************************************************** -// -// The following define the bit fields in the SSI clock prescale register. -// -//***************************************************************************** -#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale - -//***************************************************************************** -// -// The following define information concerning the SSI Data register. -// -//***************************************************************************** -#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO -#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO - -//***************************************************************************** -// -// The following define the bit fields in the interrupt mask set and clear, -// raw interrupt, masked interrupt, and interrupt clear registers. -// -//***************************************************************************** -#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt -#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt -#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt -#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt - -#endif // __HW_SSI_H__ diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/hw_sysctl.h b/Demo/CORTEX_LM3S316_IAR/hw_include/hw_sysctl.h deleted file mode 100644 index 9a8fff4ee..000000000 --- a/Demo/CORTEX_LM3S316_IAR/hw_include/hw_sysctl.h +++ /dev/null @@ -1,380 +0,0 @@ -//***************************************************************************** -// -// hw_sysctl.h - Macros used when accessing the system control hardware. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 635 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_SYSCTL_H__ -#define __HW_SYSCTL_H__ - -//***************************************************************************** -// -// The following define the offsets of the system control registers. -// -//***************************************************************************** -#define SYSCTL_DID0 0x400fe000 // Device identification register 0 -#define SYSCTL_DID1 0x400fe004 // Device identification register 1 -#define SYSCTL_DC0 0x400fe008 // Device capabilities register 0 -#define SYSCTL_DC1 0x400fe010 // Device capabilities register 1 -#define SYSCTL_DC2 0x400fe014 // Device capabilities register 2 -#define SYSCTL_DC3 0x400fe018 // Device capabilities register 3 -#define SYSCTL_DC4 0x400fe01C // Device capabilities register 4 -#define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register -#define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register -#define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0 -#define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1 -#define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2 -#define SYSCTL_RIS 0x400fe050 // Raw interrupt status register -#define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register -#define SYSCTL_MISC 0x400fe058 // Interrupt status register -#define SYSCTL_RESC 0x400fe05c // Reset cause register -#define SYSCTL_RCC 0x400fe060 // Run-mode clock config register -#define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register -#define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0 -#define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1 -#define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2 -#define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0 -#define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1 -#define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2 -#define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0 -#define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1 -#define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2 -#define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register -#define SYSCTL_LDOARST 0x400fe160 // LDO reset control register - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DID0 register. -// -//***************************************************************************** -#define SYSCTL_DID0_VER_MASK 0x70000000 // DID0 version mask -#define SYSCTL_DID0_VER_0 0x00000000 // DID0 version 0 -#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask -#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A -#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B -#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask -#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0 -#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DID1 register. -// -//***************************************************************************** -#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask -#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask -#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family -#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask -#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101 -#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102 -#define SYSCTL_DID1_PRTNO_301 0x00110000 // LM3S301 -#define SYSCTL_DID1_PRTNO_310 0x00120000 // LM3S310 -#define SYSCTL_DID1_PRTNO_315 0x00130000 // LM3S315 -#define SYSCTL_DID1_PRTNO_316 0x00140000 // LM3S316 -#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask -#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C) -#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C) -#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask -#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC -#define SYSCTL_DID1_PKG_48QFP 0x00000008 // 48-pin QFP -#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant -#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask -#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified) -#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified) -#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified -#define SYSCTL_DID1_PRTNO_SHIFT 16 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC0 register. -// -//***************************************************************************** -#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask -#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2kB of SRAM -#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4kB of SRAM -#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask -#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8kB of flash -#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16kB of flash - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC1 register. -// -//***************************************************************************** -#define SYSCTL_DC1_PWM 0x00100000 // PWM module present -#define SYSCTL_DC1_ADC 0x00010000 // ADC module present -#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask -#define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask -#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250Ksps ADC -#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC -#define SYSCTL_DC1_MPU 0x00000080 // Cortex M3 MPU present -#define SYSCTL_DC1_TEMP 0x00000020 // Temperature sensor present -#define SYSCTL_DC1_PLL 0x00000010 // PLL present -#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present -#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present -#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present -#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC2 register. -// -//***************************************************************************** -#define SYSCTL_DC2_COMP2 0x04000000 // Analog comparator 2 present -#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present -#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present -#define SYSCTL_DC2_TIMER2 0x00040000 // Timer 2 present -#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present -#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present -#define SYSCTL_DC2_I2C 0x00001000 // I2C present -#define SYSCTL_DC2_SSI 0x00000010 // SSI present -#define SYSCTL_DC2_UART1 0x00000002 // UART 1 present -#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC3 register. -// -//***************************************************************************** -#define SYSCTL_DC3_32KHZ 0x80000000 // 32kHz pin present -#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 pin present -#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 pin present -#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 pin present -#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 pin present -#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present -#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present -#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 pin present -#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 pin present -#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 pin present -#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 pin present -#define SYSCTL_DC3_C2O 0x00004000 // C2o pin present -#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ pin present -#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- pin present -#define SYSCTL_DC3_C1O 0x00000800 // C1o pin present -#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ pin present -#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present -#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present -#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present -#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present -#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 pin present -#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 pin present -#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 pin present -#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 pin present -#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 pin present -#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 pin present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC4 register. -// -//***************************************************************************** -#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO port E present -#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO port D present -#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present -#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present -#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_PBORCTL register. -// -//***************************************************************************** -#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer -#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset -#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise -#define SYSCTL_PBORCTL_BOR_SH 2 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_LDOPCTL register. -// -//***************************************************************************** -#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask -#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V -#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V -#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V -#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V -#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V -#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V -#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V -#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V -#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V -#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V -#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0, -// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers. -// -//***************************************************************************** -#define SYSCTL_SET0_PWM 0x00100000 // PWM module -#define SYSCTL_SET0_ADC 0x00010000 // ADC module -#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1, -// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers. -// -//***************************************************************************** -#define SYSCTL_SET1_COMP2 0x04000000 // Analog comparator module 2 -#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1 -#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0 -#define SYSCTL_SET1_TIMER2 0x00040000 // Timer module 2 -#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1 -#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0 -#define SYSCTL_SET1_I2C 0x00001000 // I2C module -#define SYSCTL_SET1_SSI 0x00000010 // SSI module -#define SYSCTL_SET1_UART1 0x00000002 // UART module 1 -#define SYSCTL_SET1_UART0 0x00000001 // UART module 0 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2, -// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers. -// -//***************************************************************************** -#define SYSCTL_SET2_GPIOE 0x00000010 // GPIO E module -#define SYSCTL_SET2_GPIOD 0x00000008 // GPIO D module -#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module -#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module -#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and -// SYSCTL_IMS registers. -// -//***************************************************************************** -#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt -#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt -#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int -#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int -#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt -#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt -#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_RESC register. -// -//***************************************************************************** -#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset -#define SYSCTL_RESC_SW 0x00000010 // Software reset -#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset -#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset -#define SYSCTL_RESC_POR 0x00000002 // Power on reset -#define SYSCTL_RESC_EXT 0x00000001 // External reset - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_RCC register. -// -//***************************************************************************** -#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating -#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider -#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2 -#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3 -#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4 -#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5 -#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6 -#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7 -#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8 -#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9 -#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10 -#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11 -#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12 -#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13 -#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14 -#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15 -#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16 -#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider -#define SYSCTL_RCC_USE_PWMDIV 0x00100000 // Use PWM clock divider -#define SYSCTL_RCC_PWMDIV_MASK 0x000E0000 // PWM clock divider -#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2 -#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4 -#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8 -#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16 -#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32 -#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64 -#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down -#define SYSCTL_RCC_OE 0x00001000 // PLL output enable -#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass -#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable -#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc -#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal -#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864MHz crystal -#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4MHz crystal -#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal -#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal -#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal -#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal -#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal -#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal -#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal -#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal -#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal -#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select -#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator -#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // Use the internal oscillator -#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // Use the internal oscillator / 4 -#define SYSCTL_RCC_IOSCVER 0x00000008 // Int. osc. verification timer en -#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en -#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal oscillator disable -#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable -#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field -#define SYSCTL_RCC_PWMDIV_SHIFT 17 // Shift to the PWMDIV field -#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field -#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_PLLCFG register. -// -//***************************************************************************** -#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider -#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1 -#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2 -#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4 -#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier -#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider -#define SYSCTL_PLLCFG_F_SHIFT 5 -#define SYSCTL_PLLCFG_R_SHIFT 0 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_CLKVCLR register. -// -//***************************************************************************** -#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_LDOARST register. -// -//***************************************************************************** -#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device - -#endif // __HW_SYSCTL_H__ diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/hw_timer.h b/Demo/CORTEX_LM3S316_IAR/hw_include/hw_timer.h deleted file mode 100644 index 9954a9ff1..000000000 --- a/Demo/CORTEX_LM3S316_IAR/hw_include/hw_timer.h +++ /dev/null @@ -1,235 +0,0 @@ -//***************************************************************************** -// -// hw_timer.h - Defines and macros used when accessing the timer. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 635 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_TIMER_H__ -#define __HW_TIMER_H__ - -//***************************************************************************** -// -// The following define the offsets of the timer registers. -// -//***************************************************************************** -#define TIMER_O_CFG 0x00000000 // Configuration register -#define TIMER_O_TAMR 0x00000004 // TimerA mode register -#define TIMER_O_TBMR 0x00000008 // TimerB mode register -#define TIMER_O_CTL 0x0000000C // Control register -#define TIMER_O_IMR 0x00000018 // Interrupt mask register -#define TIMER_O_RIS 0x0000001C // Interrupt status register -#define TIMER_O_MIS 0x00000020 // Masked interrupt status reg. -#define TIMER_O_ICR 0x00000024 // Interrupt clear register -#define TIMER_O_TAILR 0x00000028 // TimerA interval load register -#define TIMER_O_TBILR 0x0000002C // TimerB interval load register -#define TIMER_O_TAMATCHR 0x00000030 // TimerA match register -#define TIMER_O_TBMATCHR 0x00000034 // TimerB match register -#define TIMER_O_TAPR 0x00000038 // TimerA prescale register -#define TIMER_O_TBPR 0x0000003C // TimerB prescale register -#define TIMER_O_TAPMR 0x00000040 // TimerA prescale match register -#define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register -#define TIMER_O_TAR 0x00000048 // TimerA register -#define TIMER_O_TBR 0x0000004C // TimerB register - -//***************************************************************************** -// -// The following define the reset values of the timer registers. -// -//***************************************************************************** -#define TIMER_RV_CFG 0x00000000 // Configuration register RV -#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV -#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV -#define TIMER_RV_CTL 0x00000000 // Control register RV -#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV -#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV -#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV -#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV -#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV -#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV -#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV -#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV -#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV -#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV -#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV -#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV -#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV -#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_CFG register. -// -//***************************************************************************** -#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask -#define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers -#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC -#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_TnMR register. -// -//***************************************************************************** -#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select -#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time -#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask -#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture -#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic -#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_CTL register. -// -//***************************************************************************** -#define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert -#define TIMER_CTL_TBOTE 0x00002000 // TimerB output trigger enable -#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask -#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges -#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge -#define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge -#define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable -#define TIMER_CTL_TBEN 0x00000100 // TimerB enable -#define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert -#define TIMER_CTL_TAOTE 0x00000020 // TimerA output trigger enable -#define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable -#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask -#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges -#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge -#define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge -#define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable -#define TIMER_CTL_TAEN 0x00000001 // TimerA enable - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_IMR register. -// -//***************************************************************************** -#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask -#define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask -#define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask -#define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask -#define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask -#define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask -#define TIMER_IMR_TATOIM 0x00000001 // TimerA time out interrupt mask - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_RIS register. -// -//***************************************************************************** -#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status -#define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status -#define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status -#define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status -#define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status -#define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status -#define TIMER_RIS_TATORIS 0x00000001 // TimerA time out raw int status - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_MIS register. -// -//***************************************************************************** -#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status -#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status -#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat -#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status -#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status -#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status -#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_ICR register. -// -//***************************************************************************** -#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear -#define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear -#define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear -#define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear -#define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear -#define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear -#define TIMER_ICR_TATOCINT 0x00000001 // TimerA time out interrupt clear - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_TAILR register. -// -//***************************************************************************** -#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode -#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TBILR register. -// -//***************************************************************************** -#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_TAMATCHR register. -// -//***************************************************************************** -#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode -#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TBMATCHR register. -// -//***************************************************************************** -#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TnPR register. -// -//***************************************************************************** -#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TnPMR register. -// -//***************************************************************************** -#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_TAR register. -// -//***************************************************************************** -#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode -#define TIMER_TAR_TARL 0x0000FFFF // TimerA value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TBR register. -// -//***************************************************************************** -#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value - -#endif // __HW_TIMER_H__ diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/hw_types.h b/Demo/CORTEX_LM3S316_IAR/hw_include/hw_types.h deleted file mode 100644 index a3b9dcbee..000000000 --- a/Demo/CORTEX_LM3S316_IAR/hw_include/hw_types.h +++ /dev/null @@ -1,67 +0,0 @@ -//***************************************************************************** -// -// hw_types.h - Common types and macros. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 635 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_TYPES_H__ -#define __HW_TYPES_H__ - -//***************************************************************************** -// -// Define a boolean type, and values for true and false. -// -//***************************************************************************** -typedef unsigned char tBoolean; - -#ifndef true -#define true 1 -#endif - -#ifndef false -#define false 0 -#endif - -//***************************************************************************** -// -// Macros for hardware access, both direct and via the bit-band region. -// -//***************************************************************************** -#define HWREG(x) \ - (*((volatile unsigned long *)(x))) -#define HWREGH(x) \ - (*((volatile unsigned short *)(x))) -#define HWREGB(x) \ - (*((volatile unsigned char *)(x))) -#define HWREGBITW(x, b) \ - HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) -#define HWREGBITH(x, b) \ - HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) -#define HWREGBITB(x, b) \ - HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) - -#endif // __HW_TYPES_H__ diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/hw_uart.h b/Demo/CORTEX_LM3S316_IAR/hw_include/hw_uart.h deleted file mode 100644 index 99bdc3c41..000000000 --- a/Demo/CORTEX_LM3S316_IAR/hw_include/hw_uart.h +++ /dev/null @@ -1,239 +0,0 @@ -//***************************************************************************** -// -// hw_uart.h - Macros and defines used when accessing the UART hardware -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 635 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_UART_H__ -#define __HW_UART_H__ - -//***************************************************************************** -// -// UART Register Offsets. -// -//***************************************************************************** -#define UART_O_DR 0x00000000 // Data Register -#define UART_O_RSR 0x00000004 // Receive Status Register (read) -#define UART_O_ECR 0x00000004 // Error Clear Register (write) -#define UART_O_FR 0x00000018 // Flag Register (read only) -#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg -#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg -#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte -#define UART_O_CTL 0x00000030 // Control Register -#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg -#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg -#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register -#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register -#define UART_O_ICR 0x00000044 // Interrupt Clear Register -#define UART_O_PeriphID4 0x00000FD0 // -#define UART_O_PeriphID5 0x00000FD4 // -#define UART_O_PeriphID6 0x00000FD8 // -#define UART_O_PeriphID7 0x00000FDC // -#define UART_O_PeriphID0 0x00000FE0 // -#define UART_O_PeriphID1 0x00000FE4 // -#define UART_O_PeriphID2 0x00000FE8 // -#define UART_O_PeriphID3 0x00000FEC // -#define UART_O_PCellID0 0x00000FF0 // -#define UART_O_PCellID1 0x00000FF4 // -#define UART_O_PCellID2 0x00000FF8 // -#define UART_O_PCellID3 0x00000FFC // - -//***************************************************************************** -// -// Data Register bits -// -//***************************************************************************** -#define UART_DR_OE 0x00000800 // Overrun Error -#define UART_DR_BE 0x00000400 // Break Error -#define UART_DR_PE 0x00000200 // Parity Error -#define UART_DR_FE 0x00000100 // Framing Error -#define UART_DR_DATA_MASK 0x000000FF // UART data - -//***************************************************************************** -// -// Receive Status Register bits -// -//***************************************************************************** -#define UART_RSR_OE 0x00000008 // Overrun Error -#define UART_RSR_BE 0x00000004 // Break Error -#define UART_RSR_PE 0x00000002 // Parity Error -#define UART_RSR_FE 0x00000001 // Framing Error - -//***************************************************************************** -// -// Flag Register bits -// -//***************************************************************************** -#define UART_FR_TXFE 0x00000080 // TX FIFO Empty -#define UART_FR_RXFF 0x00000040 // RX FIFO Full -#define UART_FR_TXFF 0x00000020 // TX FIFO Full -#define UART_FR_RXFE 0x00000010 // RX FIFO Empty -#define UART_FR_BUSY 0x00000008 // UART Busy - -//***************************************************************************** -// -// Integer baud-rate divisor -// -//***************************************************************************** -#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor - -//***************************************************************************** -// -// Fractional baud-rate divisor -// -//***************************************************************************** -#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor - -//***************************************************************************** -// -// Line Control Register High bits -// -//***************************************************************************** -#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select -#define UART_LCR_H_WLEN 0x00000060 // Word length -#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data -#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data -#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data -#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data -#define UART_LCR_H_FEN 0x00000010 // Enable FIFO -#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select -#define UART_LCR_H_EPS 0x00000004 // Even Parity Select -#define UART_LCR_H_PEN 0x00000002 // Parity Enable -#define UART_LCR_H_BRK 0x00000001 // Send Break - -//***************************************************************************** -// -// Control Register bits -// -//***************************************************************************** -#define UART_CTL_RXE 0x00000200 // Receive Enable -#define UART_CTL_TXE 0x00000100 // Transmit Enable -#define UART_CTL_LBE 0x00000080 // Loopback Enable -#define UART_CTL_UARTEN 0x00000001 // UART Enable - -//***************************************************************************** -// -// Interrupt FIFO Level Select Register bits -// -//***************************************************************************** -#define UART_IFLS_RX1_8 0x00000000 // 1/8 Full -#define UART_IFLS_RX2_8 0x00000010 // 1/4 Full -#define UART_IFLS_RX4_8 0x00000020 // 1/2 Full -#define UART_IFLS_RX6_8 0x00000030 // 3/4 Full -#define UART_IFLS_RX7_8 0x00000040 // 7/8 Full -#define UART_IFLS_TX1_8 0x00000000 // 1/8 Full -#define UART_IFLS_TX2_8 0x00000001 // 1/4 Full -#define UART_IFLS_TX4_8 0x00000002 // 1/2 Full -#define UART_IFLS_TX6_8 0x00000003 // 3/4 Full -#define UART_IFLS_TX7_8 0x00000004 // 7/8 Full - -//***************************************************************************** -// -// Interrupt Mask Set/Clear Register bits -// -//***************************************************************************** -#define UART_IM_OEIM 0x00000400 // Overrun Error Interrupt Mask -#define UART_IM_BEIM 0x00000200 // Break Error Interrupt Mask -#define UART_IM_PEIM 0x00000100 // Parity Error Interrupt Mask -#define UART_IM_FEIM 0x00000080 // Framing Error Interrupt Mask -#define UART_IM_RTIM 0x00000040 // Receive Timeout Interrupt Mask -#define UART_IM_TXIM 0x00000020 // Transmit Interrupt Mask -#define UART_IM_RXIM 0x00000010 // Receive Interrupt Mask - -//***************************************************************************** -// -// Raw Interrupt Status Register -// -//***************************************************************************** -#define UART_RIS_OERIS 0x00000400 // Overrun Error Interrupt Status -#define UART_RIS_BERIS 0x00000200 // Break Error Interrupt Status -#define UART_RIS_PERIS 0x00000100 // Parity Error Interrupt Status -#define UART_RIS_FERIS 0x00000080 // Framing Error Interrupt Status -#define UART_RIS_RTRIS 0x00000040 // Receive Timeout Interrupt Status -#define UART_RIS_TXRIS 0x00000020 // Transmit Interrupt Status -#define UART_RIS_RXRIS 0x00000010 // Receive Interrupt Status - -//***************************************************************************** -// -// Masked Interrupt Status Register -// -//***************************************************************************** -#define UART_MIS_OEMIS 0x00000400 // Overrun Error Interrupt Status -#define UART_MIS_BEMIS 0x00000200 // Break Error Interrupt Status -#define UART_MIS_PEMIS 0x00000100 // Parity Error Interrupt Status -#define UART_MIS_FEMIS 0x00000080 // Framing Error Interrupt Status -#define UART_MIS_RTMIS 0x00000040 // Receive Timeout Interrupt Status -#define UART_MIS_TXMIS 0x00000020 // Transmit Interrupt Status -#define UART_MIS_RXMIS 0x00000010 // Receive Interrupt Status - -//***************************************************************************** -// -// Interrupt Clear Register bits -// -//***************************************************************************** -#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear -#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear -#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear -#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear -#define UART_ICR_RTIC 0x00000040 // Receive Timeout Interrupt Clear -#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear -#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear - -#define UART_RSR_ANY (UART_RSR_OE | \ - UART_RSR_BE | \ - UART_RSR_PE | \ - UART_RSR_FE) - -//***************************************************************************** -// -// Reset Values for UART Registers. -// -//***************************************************************************** -#define UART_RV_DR 0x00000000 -#define UART_RV_RSR 0x00000000 -#define UART_RV_ECR 0x00000000 -#define UART_RV_FR 0x00000090 -#define UART_RV_IBRD 0x00000000 -#define UART_RV_FBRD 0x00000000 -#define UART_RV_LCR_H 0x00000000 -#define UART_RV_CTL 0x00000300 -#define UART_RV_IFLS 0x00000012 -#define UART_RV_IM 0x00000000 -#define UART_RV_RIS 0x00000000 -#define UART_RV_MIS 0x00000000 -#define UART_RV_ICR 0x00000000 -#define UART_RV_PeriphID4 0x00000000 -#define UART_RV_PeriphID5 0x00000000 -#define UART_RV_PeriphID6 0x00000000 -#define UART_RV_PeriphID7 0x00000000 -#define UART_RV_PeriphID0 0x00000011 -#define UART_RV_PeriphID1 0x00000000 -#define UART_RV_PeriphID2 0x00000018 -#define UART_RV_PeriphID3 0x00000001 -#define UART_RV_PCellID0 0x0000000D -#define UART_RV_PCellID1 0x000000F0 -#define UART_RV_PCellID2 0x00000005 -#define UART_RV_PCellID3 0x000000B1 - -#endif // __HW_UART_H__ diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/hw_watchdog.h b/Demo/CORTEX_LM3S316_IAR/hw_include/hw_watchdog.h deleted file mode 100644 index e9d3f0b5b..000000000 --- a/Demo/CORTEX_LM3S316_IAR/hw_include/hw_watchdog.h +++ /dev/null @@ -1,116 +0,0 @@ -//***************************************************************************** -// -// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 635 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_WATCHDOG_H__ -#define __HW_WATCHDOG_H__ - -//***************************************************************************** -// -// The following define the offsets of the Watchdog Timer registers. -// -//***************************************************************************** -#define WDT_O_LOAD 0x00000000 // Load register -#define WDT_O_VALUE 0x00000004 // Current value register -#define WDT_O_CTL 0x00000008 // Control register -#define WDT_O_ICR 0x0000000C // Interrupt clear register -#define WDT_O_RIS 0x00000010 // Raw interrupt status register -#define WDT_O_MIS 0x00000014 // Masked interrupt status register -#define WDT_O_TEST 0x00000418 // Test register -#define WDT_O_LOCK 0x00000C00 // Lock register -#define WDT_O_PeriphID4 0x00000FD0 // -#define WDT_O_PeriphID5 0x00000FD4 // -#define WDT_O_PeriphID6 0x00000FD8 // -#define WDT_O_PeriphID7 0x00000FDC // -#define WDT_O_PeriphID0 0x00000FE0 // -#define WDT_O_PeriphID1 0x00000FE4 // -#define WDT_O_PeriphID2 0x00000FE8 // -#define WDT_O_PeriphID3 0x00000FEC // -#define WDT_O_PCellID0 0x00000FF0 // -#define WDT_O_PCellID1 0x00000FF4 // -#define WDT_O_PCellID2 0x00000FF8 // -#define WDT_O_PCellID3 0x00000FFC // - -//***************************************************************************** -// -// The following define the bit fields in the WDT_CTL register. -// -//***************************************************************************** -#define WDT_CTL_RESEN 0x00000002 // Enable reset output -#define WDT_CTL_INTEN 0x00000001 // Enable the WDT counter and int - -//***************************************************************************** -// -// The following define the bit fields in the WDT_ISR, WDT_RIS, and WDT_MIS -// registers. -// -//***************************************************************************** -#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired - -//***************************************************************************** -// -// The following define the bit fields in the WDT_TEST register. -// -//***************************************************************************** -#define WDT_TEST_STALL 0x00000100 // Watchdog stall enable -#ifndef DEPRECATED -#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable -#endif - -//***************************************************************************** -// -// The following define the bit fields in the WDT_LOCK register. -// -//***************************************************************************** -#define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked -#define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked -#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer - -//***************************************************************************** -// -// The following define the reset values for the WDT registers. -// -//***************************************************************************** -#define WDT_RV_LOAD 0xFFFFFFFF // Load register -#define WDT_RV_VALUE 0xFFFFFFFF // Current value register -#define WDT_RV_CTL 0x00000000 // Control register -#define WDT_RV_RIS 0x00000000 // Raw interrupt status register -#define WDT_RV_MIS 0x00000000 // Masked interrupt status register -#define WDT_RV_LOCK 0x00000000 // Lock register -#define WDT_RV_PeriphID4 0x00000000 // -#define WDT_RV_PeriphID5 0x00000000 // -#define WDT_RV_PeriphID6 0x00000000 // -#define WDT_RV_PeriphID7 0x00000000 // -#define WDT_RV_PeriphID0 0x00000005 // -#define WDT_RV_PeriphID1 0x00000018 // -#define WDT_RV_PeriphID2 0x00000018 // -#define WDT_RV_PeriphID3 0x00000001 // -#define WDT_RV_PCellID0 0x0000000D // -#define WDT_RV_PCellID1 0x000000F0 // -#define WDT_RV_PCellID2 0x00000005 // -#define WDT_RV_PCellID3 0x000000B1 // - -#endif // __HW_WATCHDOG_H__ diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/i2c.h b/Demo/CORTEX_LM3S316_IAR/hw_include/i2c.h deleted file mode 100644 index 26bb1dd63..000000000 --- a/Demo/CORTEX_LM3S316_IAR/hw_include/i2c.h +++ /dev/null @@ -1,137 +0,0 @@ -//***************************************************************************** -// -// i2c.h - Prototypes for the I2C Driver. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 635 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __I2C_H__ -#define __I2C_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Defines for the API. -// -//***************************************************************************** -//***************************************************************************** -// -// Interrupt defines. -// -//***************************************************************************** -#define I2C_INT_MASTER 0x00000001 -#define I2C_INT_SLAVE 0x00000002 - -//***************************************************************************** -// -// I2C Master commands. -// -//***************************************************************************** -#define I2C_MASTER_CMD_SINGLE_SEND \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_SINGLE_RECEIVE \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_SEND_START \ - (I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_SEND_CONT \ - (I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_SEND_FINISH \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ - (I2C_MASTER_CS_STOP) -#define I2C_MASTER_CMD_BURST_RECEIVE_START \ - (I2C_MASTER_CS_ACK | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ - (I2C_MASTER_CS_ACK | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) - -//***************************************************************************** -// -// I2C Master error status. -// -//***************************************************************************** -#define I2C_MASTER_ERR_NONE 0 -#define I2C_MASTER_ERR_ADDR_ACK 0x00000004 -#define I2C_MASTER_ERR_DATA_ACK 0x00000008 -#define I2C_MASTER_ERR_ARB_LOST 0x00000010 - -//***************************************************************************** -// -// I2C Slave action requests -// -//***************************************************************************** -#define I2C_SLAVE_ACT_NONE 0 -#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data -#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data - -//***************************************************************************** -// Miscellaneous I2C driver definitions. -//***************************************************************************** -#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void)); -extern void I2CIntUnregister(unsigned long ulBase); -extern tBoolean I2CMasterBusBusy(unsigned long ulBase); -extern tBoolean I2CMasterBusy(unsigned long ulBase); -extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd); -extern unsigned long I2CMasterDataGet(unsigned long ulBase); -extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData); -extern void I2CMasterDisable(unsigned long ulBase); -extern void I2CMasterEnable(unsigned long ulBase); -extern unsigned long I2CMasterErr(unsigned long ulBase); -extern void I2CMasterInit(unsigned long ulBase, tBoolean bFast); -extern void I2CMasterIntClear(unsigned long ulBase); -extern void I2CMasterIntDisable(unsigned long ulBase); -extern void I2CMasterIntEnable(unsigned long ulBase); -extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void I2CMasterSlaveAddrSet(unsigned long ulBase, - unsigned char ucSlaveAddr, - tBoolean bReceive); -extern unsigned long I2CSlaveDataGet(unsigned long ulBase); -extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData); -extern void I2CSlaveDisable(unsigned long ulBase); -extern void I2CSlaveEnable(unsigned long ulBase); -extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr); -extern void I2CSlaveIntClear(unsigned long ulBase); -extern void I2CSlaveIntDisable(unsigned long ulBase); -extern void I2CSlaveIntEnable(unsigned long ulBase); -extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked); -extern unsigned long I2CSlaveStatus(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __I2C_H__ diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/interrupt.h b/Demo/CORTEX_LM3S316_IAR/hw_include/interrupt.h deleted file mode 100644 index 98f0f862c..000000000 --- a/Demo/CORTEX_LM3S316_IAR/hw_include/interrupt.h +++ /dev/null @@ -1,57 +0,0 @@ -//***************************************************************************** -// -// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 635 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __INTERRUPT_H__ -#define __INTERRUPT_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void IntMasterEnable(void); -extern void IntMasterDisable(void); -extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)); -extern void IntUnregister(unsigned long ulInterrupt); -extern void IntPriorityGroupingSet(unsigned long ulBits); -extern unsigned long IntPriorityGroupingGet(void); -extern void IntPrioritySet(unsigned long ulInterrupt, - unsigned char ucPriority); -extern long IntPriorityGet(unsigned long ulInterrupt); -extern void IntEnable(unsigned long ulInterrupt); -extern void IntDisable(unsigned long ulInterrupt); - -#ifdef __cplusplus -} -#endif - -#endif // __INTERRUPT_H__ diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/libdriver.a b/Demo/CORTEX_LM3S316_IAR/hw_include/libdriver.a deleted file mode 100644 index c465e8f71..000000000 Binary files a/Demo/CORTEX_LM3S316_IAR/hw_include/libdriver.a and /dev/null differ diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/lnkarm.xcl b/Demo/CORTEX_LM3S316_IAR/hw_include/lnkarm.xcl deleted file mode 100644 index 0dfdc1d2c..000000000 --- a/Demo/CORTEX_LM3S316_IAR/hw_include/lnkarm.xcl +++ /dev/null @@ -1,196 +0,0 @@ -//************************************************************************* -// XLINK command file template for EWARM/ICCARM -// -// Usage: xlink -f lnkarm -// -s -// -// $Revision: 1.32 $ -//************************************************************************* - -//************************************************************************* -// In this file it is assumed that the system has the following -// memory layout: -// -// Exception vectors [0x000000--0x00001F] RAM or ROM -// ROMSTART--ROMEND [0x008000--0x0FFFFF] ROM (or other non-volatile memory) -// RAMSTART--RAMEND [0x100000--0x7FFFFF] RAM (or other read/write memory) -// -// ------------- -// Code segments - may be placed anywhere in memory. -// ------------- -// -// INTVEC -- Exception vector table. -// SWITAB -- Software interrupt vector table. -// ICODE -- Startup (cstartup) and exception code. -// DIFUNCT -- Dynamic initialization vectors used by C++. -// CODE -- Compiler generated code. -// CODE_I -- Compiler generated code declared __ramfunc (executes in RAM) -// CODE_ID -- Initializer for CODE_I (ROM). -// -// ------------- -// Data segments - may be placed anywhere in memory. -// ------------- -// -// CSTACK -- The stack used by C/C++ programs (system and user mode). -// IRQ_STACK -- The stack used by IRQ service routines. -// SVC_STACK -- The stack used in supervisor mode -// (Define other exception stacks as needed for -// FIQ, ABT, UND). -// HEAP -- The heap used by malloc and free in C and new and -// delete in C++. -// INITTAB -- Table containing addresses and sizes of segments that -// need to be initialized at startup (by cstartup). -// CHECKSUM -- The linker places checksum byte(s) in this segment, -// when the -J linker command line option is used. -// DATA_y -- Data objects. -// -// Where _y can be one of: -// -// _AN -- Holds uninitialized located objects, i.e. objects with -// an absolute location given by the @ operator or the -// #pragma location directive. Since these segments -// contain objects which already have a fixed address, -// they should not be mentioned in this linker command -// file. -// _C -- Constants (ROM). -// _I -- Initialized data (RAM). -// _ID -- The original content of _I (copied to _I by cstartup) (ROM). -// _N -- Uninitialized data (RAM). -// _Z -- Zero initialized data (RAM). -// -// Note: Be sure to use end values for the defined address ranges. -// Otherwise, the linker may allocate space outside the -// intended memory range. -//************************************************************************* - - -//************************************************ -// Inform the linker about the CPU family used. -//************************************************ - --carm - -//************************************************************************* -// Segment placement - General information -// -// All numbers in the segment placement command lines below are interpreted -// as hexadecimal unless they are immediately preceded by a '.', which -// denotes decimal notation. -// -// When specifying the segment placement using the -P instead of the -Z -// option, the linker is free to split each segment into its segment parts -// and randomly place these parts within the given ranges in order to -// achieve a more efficient memory usage. One disadvantage, however, is -// that it is not possible to find the start or end address (using -// the assembler operators .sfb./.sfe.) of a segment which has been split -// and reformed. -// -// When generating an output file which is to be used for programming -// external ROM/Flash devices, the -M linker option is very useful -// (see xlink.pdf for details). -//************************************************************************* - - -//************************************************************************* -// Read-only segments mapped to ROM. -//************************************************************************* - --DROMSTART=08000 --DROMEND=FFFFF - -//************************************************ -// Address range for reset and exception -// vectors (INTVEC). -// The vector area is 32 bytes, -// an additional 32 bytes is allocated for the -// constant table used by ldr PC in cstartup.s79. -//************************************************ - --Z(CODE)INTVEC=00-3F - -//************************************************ -// Startup code and exception routines (ICODE). -//************************************************ - --Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND --Z(CODE)SWITAB=ROMSTART-ROMEND - -//************************************************ -// Code segments may be placed anywhere. -//************************************************ - --Z(CODE)CODE=ROMSTART-ROMEND - -//************************************************ -// Original ROM location for __ramfunc code copied -// to and executed from RAM. -//************************************************ - --Z(CONST)CODE_ID=ROMSTART-ROMEND - -//************************************************ -// Various constants and initializers. -//************************************************ - --Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND --Z(CONST)CHECKSUM=ROMSTART-ROMEND - -//************************************************************************* -// Read/write segments mapped to RAM. -//************************************************************************* - --DRAMSTART=100000 --DRAMEND=7FFFFF - -//************************************************ -// Data segments. -//************************************************ - --Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND - -//************************************************ -// __ramfunc code copied to and executed from RAM. -//************************************************ - --Z(DATA)CODE_I=RAMSTART-RAMEND - -//************************************************ -// ICCARM produces code for __ramfunc functions in -// CODE_I segments. The -Q XLINK command line -// option redirects XLINK to emit the code in the -// CODE_ID segment instead, but to keep symbol and -// debug information associated with the CODE_I -// segment, where the code will execute. -//************************************************ - --QCODE_I=CODE_ID - -//************************************************************************* -// Stack and heap segments. -//************************************************************************* - --D_CSTACK_SIZE=2000 -// -D_SVC_STACK_SIZE=10 --D_IRQ_STACK_SIZE=100 --D_HEAP_SIZE=8000 - --Z(DATA)CSTACK+_CSTACK_SIZE=RAMSTART-RAMEND -// -Z(DATA)SVC_STACK+_SVC_STACK_SIZE=RAMSTART-RAMEND --Z(DATA)IRQ_STACK+_IRQ_STACK_SIZE,HEAP+_HEAP_SIZE=RAMSTART-RAMEND - -//************************************************************************* -// ELF/DWARF support. -// -// Uncomment the line "-Felf" below to generate ELF/DWARF output. -// Available format specifiers are: -// -// "-yn": Suppress DWARF debug output -// "-yp": Multiple ELF program sections -// "-yas": Format suitable for debuggers from ARM Ltd (also sets -p flag) -// -// "-Felf" and the format specifiers can also be supplied directly as -// command line options, or selected from the Xlink Output tab in the -// IAR Embedded Workbench. -//************************************************************************* - -// -Felf diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/lnkarm_standalone.xcl b/Demo/CORTEX_LM3S316_IAR/hw_include/lnkarm_standalone.xcl deleted file mode 100644 index f2cc3632c..000000000 --- a/Demo/CORTEX_LM3S316_IAR/hw_include/lnkarm_standalone.xcl +++ /dev/null @@ -1,192 +0,0 @@ -//************************************************************************* -// XLINK command file template for EWARM/ICCARM -// -// Usage: xlink -f lnkarm -// -s -// -// $Revision: 1.1 $ -//************************************************************************* - -//************************************************************************* -// In this file it is assumed that the system has the following -// memory layout: -// -// ROMSTART--ROMEND [00000000--00001FFF] Flash -// RAMSTART--RAMEND [20000000--200007FF] RAM -// -// ------------- -// Code segments - may be placed anywhere in memory (except INTVEC). -// ------------- -// -// INTVEC -- Exception vector table. -// SWITAB -- Software interrupt vector table. -// ICODE -- Startup (cstartup) and exception code. -// DIFUNCT -- Dynamic initialization vectors used by C++. -// CODE -- Compiler generated code. -// CODE_I -- Compiler generated code declared __ramfunc (executes in RAM) -// CODE_ID -- Initializer for CODE_I (ROM). -// -// ------------- -// Data segments - may be placed anywhere in memory. -// ------------- -// -// CSTACK -- The stack used by C/C++ programs (system and user mode). -// HEAP -- The heap used by malloc and free in C and new and -// delete in C++. -// INITTAB -- Table containing addresses and sizes of segments that -// need to be initialized at startup (by cstartup). -// CHECKSUM -- The linker places checksum byte(s) in this segment, -// when the -J linker command line option is used. -// DATA_y -- Data objects. -// -// Where _y can be one of: -// -// _AN -- Holds uninitialized located objects, i.e. objects with -// an absolute location given by the @ operator or the -// #pragma location directive. Since these segments -// contain objects which already have a fixed address, -// they should not be mentioned in this linker command -// file. -// _C -- Constants (ROM). -// _I -- Initialized data (RAM). -// _ID -- The original content of _I (copied to _I by cstartup) (ROM). -// _N -- Uninitialized data (RAM). -// _Z -- Zero initialized data (RAM). -// -// Note: Be sure to use end values for the defined address ranges. -// Otherwise, the linker may allocate space outside the -// intended memory range. -//************************************************************************* - - -//************************************************ -// Inform the linker about the CPU family used. -//************************************************ - --carm - -//************************************************************************* -// Segment placement - General information -// -// All numbers in the segment placement command lines below are interpreted -// as hexadecimal unless they are immediately preceded by a '.', which -// denotes decimal notation. -// -// When specifying the segment placement using the -P instead of the -Z -// option, the linker is free to split each segment into its segment parts -// and randomly place these parts within the given ranges in order to -// achieve a more efficient memory usage. One disadvantage, however, is -// that it is not possible to find the start or end address (using -// the assembler operators .sfb./.sfe.) of a segment which has been split -// and reformed. -// -// When generating an output file which is to be used for programming -// external ROM/Flash devices, the -M linker option is very useful -// (see xlink.pdf for details). -//************************************************************************* - - -//************************************************************************* -// Read-only segments mapped to ROM. -//************************************************************************* - --DROMSTART=00000000 --DROMEND=00001FFF - -//************************************************ -// Address range for reset and exception -// vectors (INTVEC). -// The vector area is at least 8 bytes, -// and is normally located at address 0. -// It may be changed to a RAM address when -// debugging in RAM (aligned to 2^7). -//************************************************ - --Z(CODE)INTVEC=ROMSTART-ROMEND - -//************************************************ -// Startup code and exception routines (ICODE). -//************************************************ - --Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND --Z(CODE)SWITAB=ROMSTART-ROMEND - -//************************************************ -// Code segments may be placed anywhere. -//************************************************ - --Z(CODE)CODE=ROMSTART-ROMEND - -//************************************************ -// Original ROM location for __ramfunc code copied -// to and executed from RAM. -//************************************************ - --Z(CONST)CODE_ID=ROMSTART-ROMEND - -//************************************************ -// Various constants and initializers. -//************************************************ - --Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND --Z(CONST)CHECKSUM=ROMSTART-ROMEND - -//************************************************************************* -// Read/write segments mapped to RAM. -//************************************************************************* - --DRAMSTART=20000000 --DRAMEND=200007FF - -//************************************************ -// Data segments. -//************************************************ - --Z(DATA)VTABLE=RAMSTART-RAMEND - --Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND - -//************************************************ -// __ramfunc code copied to and executed from RAM. -//************************************************ - --Z(DATA)CODE_I=RAMSTART-RAMEND - -//************************************************ -// ICCARM produces code for __ramfunc functions in -// CODE_I segments. The -Q XLINK command line -// option redirects XLINK to emit the code in the -// CODE_ID segment instead, but to keep symbol and -// debug information associated with the CODE_I -// segment, where the code will execute. -//************************************************ - --QCODE_I=CODE_ID - -//************************************************************************* -// Stack and heap segments. -//************************************************************************* - --D_CSTACK_SIZE=180 --D_IRQ_STACK_SIZE=100 --D_HEAP_SIZE=100 - --Z(DATA)CSTACK+_CSTACK_SIZE=RAMSTART-RAMEND --Z(DATA)HEAP+_HEAP_SIZE=RAMSTART-RAMEND - -//************************************************************************* -// ELF/DWARF support. -// -// Uncomment the line "-Felf" below to generate ELF/DWARF output. -// Available format specifiers are: -// -// "-yn": Suppress DWARF debug output -// "-yp": Multiple ELF program sections -// "-yas": Format suitable for debuggers from ARM Ltd (also sets -p flag) -// -// "-Felf" and the format specifiers can also be supplied directly as -// command line options, or selected from the Xlink Output tab in the -// IAR Embedded Workbench. -//************************************************************************* - -// -Felf diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/pdc.c b/Demo/CORTEX_LM3S316_IAR/hw_include/pdc.c deleted file mode 100644 index 65271d587..000000000 --- a/Demo/CORTEX_LM3S316_IAR/hw_include/pdc.c +++ /dev/null @@ -1,723 +0,0 @@ -//***************************************************************************** -// -// pdc.c - Driver for the Peripheral Device Controller (PDC) on the Stellaris -// development board. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 635 of the Stellaris Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup utilities_api -//! @{ -// -//***************************************************************************** - -#include "hw_memmap.h" -#include "hw_types.h" -#include "debug.h" -#include "gpio.h" -#include "ssi.h" -#include "sysctl.h" -#include "pdc.h" - -//***************************************************************************** -// -//! Initializes the connection to the PDC. -//! -//! This function will enable clocking to the SSI and GPIO A modules, configure -//! the GPIO pins to be used for an SSI interface, and it will configure the -//! SSI as a 1 Mbps master device, operating in MOTO mode. It will also enable -//! the SSI module, and will enable the chip select for the PDC on the -//! Stellaris development board. -//! -//! This function is contained in utils/pdc.c, with -//! utils/pdc.h containing the API definition for use by applications. -//! -//! \return None. -// -//***************************************************************************** -void -PDCInit(void) -{ - // - // Enable the peripherals used to drive the PDC. - // - SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI); - SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); - - // - // Configure the appropriate pins to be SSI instead of GPIO. - // - GPIODirModeSet(GPIO_PORTA_BASE, SSI_CLK | SSI_TX | SSI_RX, - GPIO_DIR_MODE_HW); - GPIODirModeSet(GPIO_PORTA_BASE, SSI_CS, GPIO_DIR_MODE_OUT); - GPIOPadConfigSet(GPIO_PORTA_BASE, SSI_CLK, GPIO_STRENGTH_4MA, - GPIO_PIN_TYPE_STD_WPU); - - // - // Configure the SSI port. - // - SSIConfig(SSI_BASE, SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 1000000, 8); - SSIEnable(SSI_BASE); - - // - // Reset the PDC SSI state machine. The chip select needs to be held low - // for 100ns; the procedure call overhead more than accounts for this time. - // - GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, 0); - GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, PDC_CS); -} - -//***************************************************************************** -// -//! Read a PDC register. -//! -//! \param ucAddr specifies the PDC register to read. -//! -//! This function will perform the SSI transfers required to read a register in -//! the PDC on the Stellaris development board. -//! -//! This function is contained in utils/pdc.c, with -//! utils/pdc.h containing the API definition for use by applications. -//! -//! \return Returns the value read from the PDC. -// -//***************************************************************************** -unsigned char -PDCRead(unsigned char ucAddr) -{ - unsigned long ulTemp; - - // - // Send address and read command. - // - SSIDataPut(SSI_BASE, (ucAddr & 0x0F) | PDC_RD); - - // - // Dummy write to force read. - // - SSIDataPut(SSI_BASE, 0x00); - - // - // Flush data read during address write. - // - SSIDataGet(SSI_BASE, &ulTemp); - - // - // If the LCD control register or RAM is being read, then an additional - // byte needs to be transferred. - // - if((ucAddr == PDC_LCD_CSR) || (ucAddr == PDC_LCD_RAM)) - { - // - // Dummy write to force read. - // - SSIDataPut(SSI_BASE, 0x00); - - // - // Flush read data. - // - SSIDataGet(SSI_BASE, &ulTemp); - } - - // - // Read valid data. - // - SSIDataGet(SSI_BASE, &ulTemp); - - // - // Return the data read. - // - return(ulTemp & 0xFF); -} - -//***************************************************************************** -// -//! Write a PDC register. -//! -//! \param ucAddr specifies the PDC register to write. -//! \param ucData specifies the data to write. -//! -//! This function will perform the SSI transfers required to write a register -//! in the PDC on the Stellaris development board. -//! -//! This function is contained in utils/pdc.c, with -//! utils/pdc.h containing the API definition for use by applications. -//! -//! \return None. -// -//***************************************************************************** -void -PDCWrite(unsigned char ucAddr, unsigned char ucData) -{ - unsigned long ulTemp; - - // - // Send address and write command. - // - SSIDataPut(SSI_BASE, (ucAddr & 0x0F) | PDC_WR); - - // - // Write the data. - // - SSIDataPut(SSI_BASE, ucData); - - // - // Flush data read during address write. - // - SSIDataGet(SSI_BASE, &ulTemp); - - // - // Flush data read during data write. - // - SSIDataGet(SSI_BASE, &ulTemp); -} - -//***************************************************************************** -// -//! Read the current value of the PDC DIP switches. -//! -//! This function will read the current value of the DIP switches attached to -//! the PDC on the Stellaris development board. -//! -//! This function is contained in utils/pdc.c, with -//! utils/pdc.h containing the API definition for use by applications. -//! -//! \return The current state of the DIP switches. -// -//***************************************************************************** -unsigned char -PDCDIPRead(void) -{ - return(PDCRead(PDC_DSW)); -} - -//***************************************************************************** -// -//! Write to the PDC LEDs. -//! -//! \param ucLED value to write to the LEDs. -//! -//! This function set the state of the LEDs connected to the PDC on the -//! Stellaris development board. -//! -//! This function is contained in utils/pdc.c, with -//! utils/pdc.h containing the API definition for use by applications. -//! -//! \return None. -// -//***************************************************************************** -void -PDCLEDWrite(unsigned char ucLED) -{ - PDCWrite(PDC_LED, ucLED); -} - -//***************************************************************************** -// -//! Read the current status of the PDC LEDs. -//! -//! This function will read the state of the LEDs connected to the PDC on the -//! Stellaris development board. -//! -//! This function is contained in utils/pdc.c, with -//! utils/pdc.h containing the API definition for use by applications. -//! -//! \return The value currently displayed by the LEDs. -// -//***************************************************************************** -unsigned char -PDCLEDRead(void) -{ - return(PDCRead(PDC_LED)); -} - -//***************************************************************************** -// -//! Initializes the LCD display. -//! -//! This function will set up the LCD display for writing. It will set the -//! data bus to 8 bits, set the number of lines to 2, and the font size to -//! 5x10. It will also turn the display off, clear the display, turn the -//! display back on, and enable the backlight. -//! -//! This function is contained in utils/pdc.c, with -//! utils/pdc.h containing the API definition for use by applications. -//! -//! \note The PDC must be initialized via the PDCInit() function before this -//! function can be called. Also, it may be necessary to adjust the contrast -//! potentiometer in order to discern any output on the LCD display. -//! -//! \return None. -// -//***************************************************************************** -void -PDCLCDInit(void) -{ - unsigned char pucCfg[] = - { - 0x3C, // Number of lines = 2 / font = 5x10 - 0x08, // Display off - 0x01, // Display clear - 0x06, // Entry mode [cursor dir][shift] - 0x0C, // Display on [display on][curson on][blinking on] - }; - unsigned long ulIdx; - - // - // Set the data bus width to eight bits. - // - PDCWrite(PDC_LCD_CSR, 0x30); - - // - // Wait for 4.1ms by reading the PDC version register enough times to - // guarantee that amount of time has passed. - // - for(ulIdx = 0; ulIdx < 257; ulIdx++) - { - PDCRead(PDC_VER); - } - - // - // Set the data bus width to eight bits. - // - PDCWrite(PDC_LCD_CSR, 0x30); - - // - // Wait for 100us by reading the PDC version register enough times to - // guarantee that amount of time has passed. This works out to 112us plus - // overhead. - // - for(ulIdx = 0; ulIdx < 7; ulIdx++) - { - PDCRead(PDC_VER); - } - - // - // Set the data bus width to eight bits. - // - PDCWrite(PDC_LCD_CSR, 0x30); - - // - // Configure the LCD. - // - for(ulIdx = 0; ulIdx < (sizeof(pucCfg) / sizeof(pucCfg[0])); ulIdx++) - { - // - // Wait until the LCD has finished executing any previous command. - // - while((PDCRead(PDC_LCD_CSR) & LCD_B_BUSY)) - { - } - - // - // Write the next configuration byte. - // - PDCWrite(PDC_LCD_CSR, pucCfg[ulIdx]); - } -} - -//***************************************************************************** -// -//! Turns on the backlight. -//! -//! This function turns on the backlight on the LCD. -//! -//! This function is contained in utils/pdc.c, with -//! utils/pdc.h containing the API definition for use by applications. -//! -//! \return None. -// -//***************************************************************************** -void -PDCLCDBacklightOn(void) -{ - PDCWrite(PDC_CSR, 0x01); -} - -//***************************************************************************** -// -//! Turn off the backlight. -//! -//! This function turns off the backlight on the LCD. -//! -//! This function is contained in utils/pdc.c, with -//! utils/pdc.h containing the API definition for use by applications. -//! -//! \return None. -// -//***************************************************************************** -void -PDCLCDBacklightOff(void) -{ - PDCWrite(PDC_CSR, 0x00); -} - -//***************************************************************************** -// -//! Clear the screen. -//! -//! This function clears the contents of the LCD screen. The cursor will be -//! returned to the upper left corner. -//! -//! This function is contained in utils/pdc.c, with -//! utils/pdc.h containing the API definition for use by applications. -//! -//! \return None. -// -//***************************************************************************** -void -PDCLCDClear(void) -{ - // - // Wait until the LCD has finished executing any previous command. - // - while((PDCRead(PDC_LCD_CSR) & LCD_B_BUSY)) - { - } - - // - // Write the clear display command. - // - PDCWrite(PDC_LCD_CSR, LCD_CLEAR); -} - -//***************************************************************************** -// -//! Write a character pattern to the LCD. -//! -//! \param ucChar is the character index to create. Valid values are zero -//! through seven. -//! \param pucData is the data for the character pattern. It contains eight -//! bytes, with the first byte being the top row of the pattern. In each byte, -//! the LSB is the right pixel of the pattern. -//! -//! This function will write a character pattern into the LCD for use as a -//! character to be displayed. After writing the pattern, it can be used on -//! the LCD by writing the corresponding character index to the display. -//! -//! This function is contained in utils/pdc.c, with -//! utils/pdc.h containing the API definition for use by applications. -//! -//! \return None. -// -//***************************************************************************** -void -PDCLCDCreateChar(unsigned char ucChar, unsigned char *pucData) -{ - // - // Check the arguments. - // - ASSERT(ucChar < 8); - - // - // Wait until the LCD has finished executing any previous command. - // - while((PDCRead(PDC_LCD_CSR) & LCD_B_BUSY)) - { - } - - // - // Write the character pattern memory address. - // - PDCWrite(PDC_LCD_CSR, LCD_CGADDR + (ucChar * 8)); - - // - // Write the pattern to chacter pattern memory. - // - for(ucChar = 0; ucChar < 8; ucChar++) - { - // - // Wait until the LCD has finished executing any previous command. - // - while((PDCRead(PDC_LCD_CSR) & LCD_B_BUSY)) - { - } - - // - // Write this row of the pattern. - // - PDCWrite(PDC_LCD_RAM, *pucData++); - } -} - -//***************************************************************************** -// -//! Set the position of the cursor. -//! -//! \param ucX is the horizontal position. Valid values are zero through -//! fifteen. -//! \param ucY is the vertical position.. Valid values are zero and one. -//! -//! This function will move the cursor to the specified position. All -//! characters written to the LCD are placed at the current cursor position, -//! which is automatically advanced. -//! -//! This function is contained in utils/pdc.c, with -//! utils/pdc.h containing the API definition for use by applications. -//! -//! \return None. -// -//***************************************************************************** -void -PDCLCDSetPos(unsigned char ucX, unsigned char ucY) -{ - // - // Check the arguments. - // - ASSERT(ucX < 16); - ASSERT(ucY < 2); - - // - // Wait until the LCD has finished executing any previous command. - // - while((PDCRead(PDC_LCD_CSR) & LCD_B_BUSY)) - { - } - - // - // Set the cursor position. - // - PDCWrite(PDC_LCD_CSR, LCD_DDADDR | (0x40 * ucY) + ucX); -} - -//***************************************************************************** -// -//! Writes a string to the LCD display. -//! -//! \param pcStr pointer to the string to be displayed. -//! \param ulCount is the number of characters to be displayed. -//! -//! This function will display a string on the LCD at the current cursor -//! position. It is the caller's responsibility to position the cursor to the -//! place where the string should be displayed (either explicitly via -//! PDCLCDSetPos() or implicitly from where the cursor was left after a -//! previous call to PDCLCDWrite()), and to properly account for the LCD -//! boundary (line wrapping is not automatically performed). Null characters -//! are not treated special and are written to the LCD, which interprets it as -//! a special programmable character glyph (see PDCLCDCreateChar()). -//! -//! This function is contained in utils/pdc.c, with -//! utils/pdc.h containing the API definition for use by applications. -//! -//! \return None. -// -//***************************************************************************** -void -PDCLCDWrite(const char *pcStr, unsigned long ulCount) -{ - // - // Write the string to the LCD. - // - while(ulCount--) - { - // - // Wait until the LCD has finished executing any previous command. - // - while((PDCRead(PDC_LCD_CSR) & LCD_B_BUSY)) - { - } - - // - // Write this character to the LCD. - // - PDCWrite(PDC_LCD_RAM, *pcStr++); - } -} - -//***************************************************************************** -// -//! Reads a GPIO direction register. -//! -//! \param ucIdx is the index of the GPIO direction register to read; valid -//! values are 0, 1, and 2. -//! -//! This function reads one of the GPIO direction registers in the PDC. The -//! direction bit is set for pins that are outputs and clear for pins that are -//! inputs. -//! -//! This function is contained in utils/pdc.c, with -//! utils/pdc.h containing the API definition for use by applications. -//! -//! \return The contents of the direction register. -// -//***************************************************************************** -unsigned char -PDCGPIODirRead(unsigned char ucIdx) -{ - // - // Check the argument. - // - ASSERT((ucIdx == 0) || (ucIdx == 1) || (ucIdx == 2)); - - // - // Read the requested direction register. - // - if(ucIdx == 0) - { - return(PDCRead(PDC_GPXDIR)); - } - else if(ucIdx == 1) - { - return(PDCRead(PDC_GPYDIR)); - } - else - { - return(PDCRead(PDC_GPZDIR)); - } -} - -//***************************************************************************** -// -//! Write a GPIO direction register. -//! -//! \param ucIdx is the index of the GPIO direction register to write; valid -//! values are 0, 1, and 2. -//! \param ucValue is the value to write to the GPIO direction register. -//! -//! This function writes ones of the GPIO direction registers in the PDC. The -//! direction bit should be set for pins that are to be outputs and clear for -//! pins that are to be inputs. -//! -//! This function is contained in utils/pdc.c, with -//! utils/pdc.h containing the API definition for use by applications. -//! -//! \return None. -// -//***************************************************************************** -void -PDCGPIODirWrite(unsigned char ucIdx, unsigned char ucValue) -{ - // - // Check the arguments. - // - ASSERT((ucIdx == 0) || (ucIdx == 1) || (ucIdx == 2)); - - // - // Write the requested direction register. - // - if(ucIdx == 0) - { - PDCWrite(PDC_GPXDIR, ucValue); - } - else if(ucIdx == 1) - { - PDCWrite(PDC_GPYDIR, ucValue); - } - else - { - PDCWrite(PDC_GPZDIR, ucValue); - } -} - -//***************************************************************************** -// -//! Reads a GPIO data register. -//! -//! \param ucIdx is the index of the GPIO direction register to read; valid -//! values are 0, 1, and 2. -//! -//! This function reads one of the GPIO data registers in the PDC. The value -//! returned for a pin is the value being driven out for outputs or the value -//! being read for inputs. -//! -//! This function is contained in utils/pdc.c, with -//! utils/pdc.h containing the API definition for use by applications. -//! -//! \return The contents of the data register. -// -//***************************************************************************** -unsigned char -PDCGPIORead(unsigned char ucIdx) -{ - // - // Check the argument. - // - ASSERT((ucIdx == 0) || (ucIdx == 1) || (ucIdx == 2)); - - // - // Read the requested data register. - // - if(ucIdx == 0) - { - return(PDCRead(PDC_GPXDAT)); - } - else if(ucIdx == 1) - { - return(PDCRead(PDC_GPYDAT)); - } - else - { - return(PDCRead(PDC_GPZDAT)); - } -} - -//***************************************************************************** -// -//! Write a GPIO data register. -//! -//! \param ucIdx is the index of the GPIO data register to write; valid values -//! are 0, 1, and 2. -//! \param ucValue is the value to write to the GPIO data register. -//! -//! This function writes one of the GPIO direction registers in the PDC. The -//! written to a pin is driven out for output pins and ignored for input pins. -//! -//! This function is contained in utils/pdc.c, with -//! utils/pdc.h containing the API definition for use by applications. -//! -//! \return None. -// -//***************************************************************************** -void -PDCGPIOWrite(unsigned char ucIdx, unsigned char ucValue) -{ - // - // Check the arguments. - // - ASSERT((ucIdx == 0) || (ucIdx == 1) || (ucIdx == 2)); - - // - // Write the requested data register. - // - if(ucIdx == 0) - { - PDCWrite(PDC_GPXDAT, ucValue); - } - else if(ucIdx == 1) - { - PDCWrite(PDC_GPYDAT, ucValue); - } - else - { - PDCWrite(PDC_GPZDAT, ucValue); - } -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/pdc.h b/Demo/CORTEX_LM3S316_IAR/hw_include/pdc.h deleted file mode 100644 index 952942446..000000000 --- a/Demo/CORTEX_LM3S316_IAR/hw_include/pdc.h +++ /dev/null @@ -1,124 +0,0 @@ -//***************************************************************************** -// -// pdc.h - Stellaris development board Peripheral Device Controller definitions -// and prototypes. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 635 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __PDC_H__ -#define __PDC_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The registers within the peripheral device controller. -// -//***************************************************************************** -#define PDC_VER 0x0 // Version register -#define PDC_CSR 0x1 // Command/Status register -#define PDC_DSW 0x4 // DIP Switch register -#define PDC_LED 0x5 // LED register -#define PDC_LCD_CSR 0x6 // LCD Command/Status register -#define PDC_LCD_RAM 0x7 // LCD RAM register -#define PDC_GPXDAT 0x8 // GPIO X Data register -#define PDC_GPXDIR 0x9 // GPIO X Direction register -#define PDC_GPYDAT 0xA // GPIO Y Data register -#define PDC_GPYDIR 0xB // GPIO Y Direction register -#define PDC_GPZDAT 0xC // GPIO Z Data register -#define PDC_GPZDIR 0xD // GPIO Z Direction register - -//***************************************************************************** -// -// Flags indicating a read or write to the peripheral device controller. -// -//***************************************************************************** -#define PDC_RD 0x80 // PDC read command -#define PDC_WR 0x00 // PDC write command - -//***************************************************************************** -// -// LCD panel (Crystalfontz CFAH1602B) commands, RS = 0 -// -//***************************************************************************** -#define LCD_CLEAR 0x01 // Clear display (0 fill DDRAM). -#define LCD_HOME 0x02 // Cursor home. -#define LCD_MODE 0x04 // Set entry mode (cursor dir) -#define LCD_ON 0x08 // Set display, cursor, blinking - // on/off -#define LCD_CUR 0x10 // Cursor, display shift -#define LCD_IF 0x20 // Set interface data length, - // lines, font -#define LCD_CGADDR 0x40 // Set CGRAM AC address -#define LCD_DDADDR 0x80 // Set DDRAM AC address - -//***************************************************************************** -// -// LCD Status bit -// -//***************************************************************************** -#define LCD_B_BUSY 0x80 // Busy flag. - -//***************************************************************************** -// -// The GPIO port A pin numbers for the various SSI signals. -// -//***************************************************************************** -#define SSI_CS GPIO_PIN_3 -#define PDC_CS GPIO_PIN_3 -#define SSI_CLK GPIO_PIN_2 -#define SSI_TX GPIO_PIN_5 -#define SSI_RX GPIO_PIN_4 - -//***************************************************************************** -// -// Function Prototypes -// -//***************************************************************************** -extern void PDCInit(void); -extern unsigned char PDCRead(unsigned char ucAddr); -extern void PDCWrite(unsigned char ucAddr, unsigned char ucData); -extern unsigned char PDCDIPRead(void); -extern void PDCLEDWrite(unsigned char ucLED); -extern unsigned char PDCLEDRead(void); -extern void PDCLCDInit(void); -extern void PDCLCDBacklightOn(void); -extern void PDCLCDBacklightOff(void); -extern void PDCLCDClear(void); -extern void PDCLCDCreateChar(unsigned char ucChar, unsigned char *pucData); -extern void PDCLCDSetPos(unsigned char ucX, unsigned char ucY); -extern void PDCLCDWrite(const char *pcStr, unsigned long ulCount); -extern unsigned char PDCGPIODirRead(unsigned char ucIdx); -extern void PDCGPIODirWrite(unsigned char ucIdx, unsigned char ucValue); -extern unsigned char PDCGPIORead(unsigned char ucIdx); -extern void PDCGPIOWrite(unsigned char ucIdx, unsigned char ucValue); - -#ifdef __cplusplus -} -#endif - -#endif // __PDC_H__ diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/pwm.h b/Demo/CORTEX_LM3S316_IAR/hw_include/pwm.h deleted file mode 100644 index 13cd4e1a1..000000000 --- a/Demo/CORTEX_LM3S316_IAR/hw_include/pwm.h +++ /dev/null @@ -1,161 +0,0 @@ -//***************************************************************************** -// -// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 635 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __PWM_H__ -#define __PWM_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following defines are passed to PWMGenConfigure() as the ulConfig -// parameter and specify the configuration of the PWM generator. -// -//***************************************************************************** -#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode -#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode -#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates -#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates -#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode -#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode - -//***************************************************************************** -// -// Defines for enabling, disabling, and clearing PWM generator interrupts and -// triggers. -// -//***************************************************************************** -#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0 -#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD -#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U -#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D -#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U -#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D -#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0 -#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD -#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U -#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D -#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U -#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D - -//***************************************************************************** -// -// Defines for enabling, disabling, and clearing PWM interrupts. -// -//***************************************************************************** -#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt -#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt -#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt -#define PWM_INT_FAULT 0x00010000 // Fault interrupt - -//***************************************************************************** -// -// Defines to identify the generators within a module. -// -//***************************************************************************** -#define PWM_GEN_0 0x00000040 // Offset address of Gen0 -#define PWM_GEN_1 0x00000080 // Offset address of Gen1 -#define PWM_GEN_2 0x000000C0 // Offset address of Gen2 - -#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0 -#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1 -#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2 - -//***************************************************************************** -// -// Defines to identify the outputs within a module. -// -//***************************************************************************** -#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0 -#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1 -#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2 -#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3 -#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4 -#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5 - -#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0 -#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1 -#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2 -#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3 -#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4 -#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5 - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen, - unsigned long ulConfig); -extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen, - unsigned long ulPeriod); -extern unsigned long PWMGenPeriodGet(unsigned long ulBase, - unsigned long ulGen); -extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen); -extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen); -extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut, - unsigned long ulWidth); -extern unsigned long PWMPulseWidthGet(unsigned long ulBase, - unsigned long ulPWMOut); -extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen, - unsigned short usRise, unsigned short usFall); -extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen); -extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits); -extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits); -extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits, - tBoolean bEnable); -extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits, - tBoolean bInvert); -extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits, - tBoolean bFaultKill); -extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen, - void (*pfIntHandler)(void)); -extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen); -extern void PWMFaultIntRegister(unsigned long ulBase, - void (*pfIntHandler)(void)); -extern void PWMFaultIntUnregister(unsigned long ulBase); -extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen, - unsigned long ulIntTrig); -extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen, - unsigned long ulIntTrig); -extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen, - tBoolean bMasked); -extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen, - unsigned long ulInts); -extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault); -extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault); -extern void PWMFaultIntClear(unsigned long ulBase); -extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked); - -#ifdef __cplusplus -} -#endif - -#endif // __PWM_H__ diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/ssi.h b/Demo/CORTEX_LM3S316_IAR/hw_include/ssi.h deleted file mode 100644 index 26094b9e1..000000000 --- a/Demo/CORTEX_LM3S316_IAR/hw_include/ssi.h +++ /dev/null @@ -1,88 +0,0 @@ -//***************************************************************************** -// -// ssi.h - Prototypes for the Synchronous Serial Interface Driver. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 635 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __SSI_H__ -#define __SSI_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear -// as the ulIntFlags parameter, and returned by SSIIntStatus. -// -//***************************************************************************** -#define SSI_TXFF 0x00000008 // TX FIFO half empty or less -#define SSI_RXFF 0x00000004 // RX FIFO half full or less -#define SSI_RXTO 0x00000002 // RX timeout -#define SSI_RXOR 0x00000001 // RX overrun - -//***************************************************************************** -// -// Values that can be passed to SSIConfig. -// -//***************************************************************************** -#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 -#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 -#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 -#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 -#define SSI_FRF_TI 0x00000010 // TI frame format -#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format - -#define SSI_MODE_MASTER 0x00000000 // SSI master -#define SSI_MODE_SLAVE 0x00000001 // SSI slave -#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void SSIConfig(unsigned long ulBase, unsigned long ulProtocol, - unsigned long ulMode, unsigned long ulBitRate, - unsigned long ulDataWidth); -extern void SSIDataGet(unsigned long ulBase, unsigned long *ulData); -extern long SSIDataNonBlockingGet(unsigned long ulBase, unsigned long *ulData); -extern void SSIDataPut(unsigned long ulBase, unsigned long ulData); -extern long SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData); -extern void SSIDisable(unsigned long ulBase); -extern void SSIEnable(unsigned long ulBase); -extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags); -extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); -extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void SSIIntUnregister(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __SSI_H__ diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/startup.c b/Demo/CORTEX_LM3S316_IAR/hw_include/startup.c deleted file mode 100644 index b07961b80..000000000 --- a/Demo/CORTEX_LM3S316_IAR/hw_include/startup.c +++ /dev/null @@ -1,297 +0,0 @@ -//***************************************************************************** -// -// startup.c - Boot code for Stellaris. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 635 of the Stellaris Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -// Enable the IAR extensions for this source file. -// -//***************************************************************************** -#pragma language=extended - -//***************************************************************************** -// -// Forward declaration of the default fault handlers. -// -//***************************************************************************** -void ResetISR(void); -static void NmiSR(void); -static void FaultISR(void); -static void IntDefaultHandler(void); - -//***************************************************************************** -// -// External declaration for the interrupt handler used by the application. -// -//***************************************************************************** -extern void xPortPendSVHandler(void); -extern void xPortSysTickHandler(void); -extern void vUART_ISR( void ); - -//***************************************************************************** -// -// The entry point for the application. -// -//***************************************************************************** -extern void main(void); - -//***************************************************************************** -// -// Reserve space for the system stack. -// -//***************************************************************************** -#ifndef STACK_SIZE -#define STACK_SIZE 50 -#endif -static unsigned long pulStack[STACK_SIZE] = { -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb }; -//***************************************************************************** -// -// A union that describes the entries of the vector table. The union is needed -// since the first entry is the stack pointer and the remainder are function -// pointers. -// -//***************************************************************************** -typedef union -{ - void (*pfnHandler)(void); - unsigned long ulPtr; -} -uVectorEntry; - -//***************************************************************************** -// -// The minimal vector table for a Cortex M3. Note that the proper constructs -// must be placed on this to ensure that it ends up at physical address -// 0x0000.0000. -// -//***************************************************************************** -__root const uVectorEntry g_pfnVectors[] @ "INTVEC" = -{ - { .ulPtr = (unsigned long)pulStack + sizeof(pulStack) }, - // The initial stack pointer - ResetISR, // The reset handler - NmiSR, // The NMI handler - FaultISR, // The hard fault handler - IntDefaultHandler, // The MPU fault handler - IntDefaultHandler, // The bus fault handler - IntDefaultHandler, // The usage fault handler - 0, // Reserved - 0, // Reserved - 0, // Reserved - 0, // Reserved - IntDefaultHandler, // SVCall handler - IntDefaultHandler, // Debug monitor handler - 0, // Reserved - xPortPendSVHandler, // The PendSV handler - xPortSysTickHandler, // The SysTick handler - IntDefaultHandler, // GPIO Port A - IntDefaultHandler, // GPIO Port B - IntDefaultHandler, // GPIO Port C - IntDefaultHandler, // GPIO Port D - IntDefaultHandler, // GPIO Port E - vUART_ISR, // UART0 Rx and Tx - IntDefaultHandler, // UART1 Rx and Tx - IntDefaultHandler, // SSI Rx and Tx - IntDefaultHandler, // I2C Master and Slave - IntDefaultHandler, // PWM Fault - IntDefaultHandler, // PWM Generator 0 - IntDefaultHandler, // PWM Generator 1 - IntDefaultHandler, // PWM Generator 2 - 0, // Reserved - IntDefaultHandler, // ADC Sequence 0 - IntDefaultHandler, // ADC Sequence 1 - IntDefaultHandler, // ADC Sequence 2 - IntDefaultHandler, // ADC Sequence 3 - IntDefaultHandler, // Watchdog timer - IntDefaultHandler, // Timer 0 subtimer A - IntDefaultHandler, // Timer 0 subtimer B - IntDefaultHandler, // Timer 1 subtimer A - IntDefaultHandler, // Timer 1 subtimer B - IntDefaultHandler, // Timer 2 subtimer A - IntDefaultHandler, // Timer 2 subtimer B - IntDefaultHandler, // Analog Comparator 0 - IntDefaultHandler, // Analog Comparator 1 - IntDefaultHandler, // Analog Comparator 2 - IntDefaultHandler, // System Control (PLL, OSC, BO) - IntDefaultHandler // FLASH Control -}; - -//***************************************************************************** -// -// The following are constructs created by the linker, indicating where the -// the "data" and "bss" segments reside in memory. The initializers for the -// for the "data" segment resides immediately following the "text" segment. -// -//***************************************************************************** -#pragma segment="DATA_ID" -#pragma segment="DATA_I" -#pragma segment="DATA_Z" - -//***************************************************************************** -// -// This is the code that gets called when the processor first starts execution -// following a reset event. Only the absolutely necessary set is performed, -// after which the application supplied entry() routine is called. Any fancy -// actions (such as making decisions based on the reset cause register, and -// resetting the bits in that register) are left solely in the hands of the -// application. -// -//***************************************************************************** -void -ResetISR(void) -{ - unsigned long *pulSrc, *pulDest, *pulEnd; - - // - // Copy the data segment initializers from flash to SRAM. - // - pulSrc = __segment_begin("DATA_ID"); - pulDest = __segment_begin("DATA_I"); - pulEnd = __segment_end("DATA_I"); - while(pulDest < pulEnd) - { - *pulDest++ = *pulSrc++; - } - - // - // Zero fill the bss segment. - // - pulDest = __segment_begin("DATA_Z"); - pulEnd = __segment_end("DATA_Z"); - while(pulDest < pulEnd) - { - *pulDest++ = 0; - } - - // - // Call the application's entry point. - // - main(); -} - -//***************************************************************************** -// -// This is the code that gets called when the processor receives a NMI. This -// simply enters an infinite loop, preserving the system state for examination -// by a debugger. -// -//***************************************************************************** -static void -NmiSR(void) -{ - // - // Enter an infinite loop. - // - while(1) - { - } -} - -//***************************************************************************** -// -// This is the code that gets called when the processor receives a fault -// interrupt. This simply enters an infinite loop, preserving the system state -// for examination by a debugger. -// -//***************************************************************************** -static void -FaultISR(void) -{ - // - // Enter an infinite loop. - // - while(1) - { - } -} - -//***************************************************************************** -// -// This is the code that gets called when the processor receives an unexpected -// interrupt. This simply enters an infinite loop, preserving the system state -// for examination by a debugger. -// -//***************************************************************************** -static void -IntDefaultHandler(void) -{ - // - // Go into an infinite loop. - // - while(1) - { - } -} diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/sysctl.h b/Demo/CORTEX_LM3S316_IAR/hw_include/sysctl.h deleted file mode 100644 index c5e065012..000000000 --- a/Demo/CORTEX_LM3S316_IAR/hw_include/sysctl.h +++ /dev/null @@ -1,266 +0,0 @@ -//***************************************************************************** -// -// sysctl.h - Prototypes for the system control driver. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 635 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __SYSCTL_H__ -#define __SYSCTL_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following are values that can be passed to the -// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(), -// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the -// ulPeripheral parameter. The peripherals in the fourth group (upper nibble -// is 3) can only be used with the SysCtlPeripheralPresent() API. -// -//***************************************************************************** -#define SYSCTL_PERIPH_PWM 0x00100000 // PWM -#define SYSCTL_PERIPH_ADC 0x00010000 // ADC -#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog -#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0 -#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1 -#define SYSCTL_PERIPH_SSI 0x10000010 // SSI -#define SYSCTL_PERIPH_I2C 0x10001000 // I2C -#define SYSCTL_PERIPH_TIMER0 0x10010000 // Timer 0 -#define SYSCTL_PERIPH_TIMER1 0x10020000 // Timer 1 -#define SYSCTL_PERIPH_TIMER2 0x10040000 // Timer 2 -#define SYSCTL_PERIPH_COMP0 0x11000000 // Analog comparator 0 -#define SYSCTL_PERIPH_COMP1 0x12000000 // Analog comparator 1 -#define SYSCTL_PERIPH_COMP2 0x14000000 // Analog comparator 2 -#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A -#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B -#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C -#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D -#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E -#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU -#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor -#define SYSCTL_PERIPH_PLL 0x30000010 // PLL - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlPinPresent() API -// as the ulPin parameter. -// -//***************************************************************************** -#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin -#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin -#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin -#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin -#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin -#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin -#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin -#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin -#define SYSCTL_PIN_C0O 0x00000100 // C0o pin -#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin -#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin -#define SYSCTL_PIN_C1O 0x00000800 // C1o pin -#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin -#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin -#define SYSCTL_PIN_C2O 0x00004000 // C2o pin -#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin -#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin -#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin -#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin -#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin -#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin -#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin -#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin -#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin -#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin -#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlLDOSet() API as -// the ulVoltage value, or returned by the SysCtlLDOGet() API. -// -//***************************************************************************** -#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V -#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V -#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V -#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V -#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V -#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V -#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V -#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V -#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V -#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V -#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlLDOConfigSet() API. -// -//***************************************************************************** -#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset -#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlIntEnable(), -// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask -// by the SysCtlIntStatus() API. -// -//***************************************************************************** -#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt -#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt -#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int -#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int -#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt -#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt -#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlResetCauseClear() -// API or returned by the SysCtlResetCauseGet() API. -// -//***************************************************************************** -#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset -#define SYSCTL_CAUSE_SW 0x00000010 // Software reset -#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset -#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset -#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset -#define SYSCTL_CAUSE_EXT 0x00000001 // External reset - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlBrownOutConfigSet() -// API as the ulConfig parameter. -// -//***************************************************************************** -#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting -#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlPWMClockSet() API -// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet() -// API. -// -//***************************************************************************** -#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1 -#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2 -#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4 -#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8 -#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16 -#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32 -#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64 - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlClockSet() API as -// the ulConfig parameter. -// -//***************************************************************************** -#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1 -#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2 -#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3 -#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4 -#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5 -#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6 -#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7 -#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8 -#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9 -#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10 -#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11 -#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12 -#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13 -#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14 -#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15 -#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16 -#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock -#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock -#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz -#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz -#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz -#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz -#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz -#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz -#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz -#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz -#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz -#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz -#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz -#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz -#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc -#define SYSCTL_OSC_INT 0x00000010 // Oscillator source is int. osc -#define SYSCTL_OSC_INT4 0x00000020 // Oscillator source is int. osc /4 -#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator -#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern unsigned long SysCtlSRAMSizeGet(void); -extern unsigned long SysCtlFlashSizeGet(void); -extern tBoolean SysCtlPinPresent(unsigned long ulPin); -extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral); -extern void SysCtlPeripheralReset(unsigned long ulPeripheral); -extern void SysCtlPeripheralEnable(unsigned long ulPeripheral); -extern void SysCtlPeripheralDisable(unsigned long ulPeripheral); -extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral); -extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral); -extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral); -extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral); -extern void SysCtlPeripheralClockGating(tBoolean bEnable); -extern void SysCtlIntRegister(void (*pfnHandler)(void)); -extern void SysCtlIntUnregister(void); -extern void SysCtlIntEnable(unsigned long ulInts); -extern void SysCtlIntDisable(unsigned long ulInts); -extern void SysCtlIntClear(unsigned long ulInts); -extern unsigned long SysCtlIntStatus(tBoolean bMasked); -extern void SysCtlLDOSet(unsigned long ulVoltage); -extern unsigned long SysCtlLDOGet(void); -extern void SysCtlLDOConfigSet(unsigned long ulConfig); -extern void SysCtlReset(void); -extern void SysCtlSleep(void); -extern void SysCtlDeepSleep(void); -extern unsigned long SysCtlResetCauseGet(void); -extern void SysCtlResetCauseClear(unsigned long ulCauses); -extern void SysCtlBrownOutConfigSet(unsigned long ulConfig, - unsigned long ulDelay); -extern void SysCtlClockSet(unsigned long ulConfig); -extern unsigned long SysCtlClockGet(void); -extern void SysCtlPWMClockSet(unsigned long ulConfig); -extern unsigned long SysCtlPWMClockGet(void); -extern void SysCtlIOSCVerificationSet(tBoolean bEnable); -extern void SysCtlMOSCVerificationSet(tBoolean bEnable); -extern void SysCtlPLLVerificationSet(tBoolean bEnable); -extern void SysCtlClkVerificationClear(void); - -#ifdef __cplusplus -} -#endif - -#endif // __SYSCTL_H__ diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/systick.h b/Demo/CORTEX_LM3S316_IAR/hw_include/systick.h deleted file mode 100644 index 90560761e..000000000 --- a/Demo/CORTEX_LM3S316_IAR/hw_include/systick.h +++ /dev/null @@ -1,55 +0,0 @@ -//***************************************************************************** -// -// systick.h - Prototypes for the SysTick driver. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 635 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __SYSTICK_H__ -#define __SYSTICK_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void SysTickEnable(void); -extern void SysTickDisable(void); -extern void SysTickIntRegister(void (*pfnHandler)(void)); -extern void SysTickIntUnregister(void); -extern void SysTickIntEnable(void); -extern void SysTickIntDisable(void); -extern void SysTickPeriodSet(unsigned long ulPeriod); -extern unsigned long SysTickPeriodGet(void); -extern unsigned long SysTickValueGet(void); - -#ifdef __cplusplus -} -#endif - -#endif // __SYSTICK_H__ diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/timer.h b/Demo/CORTEX_LM3S316_IAR/hw_include/timer.h deleted file mode 100644 index e60418694..000000000 --- a/Demo/CORTEX_LM3S316_IAR/hw_include/timer.h +++ /dev/null @@ -1,137 +0,0 @@ -//***************************************************************************** -// -// timer.h - Prototypes for the timer module -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 635 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __TIMER_H__ -#define __TIMER_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to TimerConfigure as the ulConfig parameter. -// -//***************************************************************************** -#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer -#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer -#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer -#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers -#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer -#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer -#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter -#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer -#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output -#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer -#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer -#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter -#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer -#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output - -//***************************************************************************** -// -// Values that can be passed to TimerIntEnable, TimerIntDisable, and -// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus. -// -//***************************************************************************** -#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt -#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt -#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt -#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask -#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt -#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt -#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt - -//***************************************************************************** -// -// Values that can be passed to TimerControlEvent as the ulEvent parameter. -// -//***************************************************************************** -#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges -#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges -#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges - -//***************************************************************************** -// -// Values that can be passed to most of the timer APIs as the ulTimer -// parameter. -// -//***************************************************************************** -#define TIMER_A 0x000000ff // Timer A -#define TIMER_B 0x0000ff00 // Timer B -#define TIMER_BOTH 0x0000ffff // Timer Both - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer); -extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer); -extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig); -extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, - tBoolean bInvert); -extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, - tBoolean bEnable); -extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulEvent); -extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer, - tBoolean bStall); -extern void TimerRTCEnable(unsigned long ulBase); -extern void TimerRTCDisable(unsigned long ulBase); -extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerPrescaleGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer); -extern unsigned long TimerValueGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerMatchGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, - void (*pfnHandler)(void)); -extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer); -extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags); -extern void TimerQuiesce(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __TIMER_H__ diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/uart.h b/Demo/CORTEX_LM3S316_IAR/hw_include/uart.h deleted file mode 100644 index d90fba8ff..000000000 --- a/Demo/CORTEX_LM3S316_IAR/hw_include/uart.h +++ /dev/null @@ -1,102 +0,0 @@ -//***************************************************************************** -// -// uart.h - Defines and Macros for the UART. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 635 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __UART_H__ -#define __UART_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear -// as the ulIntFlags parameter, and returned from UARTIntStatus. -// -//***************************************************************************** -#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask -#define UART_INT_BE 0x200 // Break Error Interrupt Mask -#define UART_INT_PE 0x100 // Parity Error Interrupt Mask -#define UART_INT_FE 0x080 // Framing Error Interrupt Mask -#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask -#define UART_INT_TX 0x020 // Transmit Interrupt Mask -#define UART_INT_RX 0x010 // Receive Interrupt Mask - -//***************************************************************************** -// -// Values that can be passed to UARTConfigSet as the ulConfig parameter and -// returned by UARTConfigGet in the pulConfig parameter. Additionally, the -// UART_CONFIG_PAR_* subset can be passed to UARTParityModeSet as the ulParity -// parameter, and are returned by UARTParityModeGet. -// -//***************************************************************************** -#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data -#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data -#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data -#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data -#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit -#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits -#define UART_CONFIG_PAR_NONE 0x00000000 // No parity -#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity -#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity -#define UART_CONFIG_PAR_ONE 0x00000086 // Parity bit is one -#define UART_CONFIG_PAR_ZERO 0x00000082 // Parity bit is zero - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity); -extern unsigned long UARTParityModeGet(unsigned long ulBase); -extern void UARTConfigSet(unsigned long ulBase, unsigned long ulBaud, - unsigned long ulConfig); -extern void UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud, - unsigned long *pulConfig); -extern void UARTEnable(unsigned long ulBase); -extern void UARTDisable(unsigned long ulBase); -extern tBoolean UARTCharsAvail(unsigned long ulBase); -extern tBoolean UARTSpaceAvail(unsigned long ulBase); -extern long UARTCharNonBlockingGet(unsigned long ulBase); -extern long UARTCharGet(unsigned long ulBase); -extern tBoolean UARTCharNonBlockingPut(unsigned long ulBase, - unsigned char ucData); -extern void UARTCharPut(unsigned long ulBase, unsigned char ucData); -extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState); -extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); -extern void UARTIntUnregister(unsigned long ulBase); -extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags); - -#ifdef __cplusplus -} -#endif - -#endif // __UART_H__ diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/watchdog.h b/Demo/CORTEX_LM3S316_IAR/hw_include/watchdog.h deleted file mode 100644 index 4d6dcd21b..000000000 --- a/Demo/CORTEX_LM3S316_IAR/hw_include/watchdog.h +++ /dev/null @@ -1,63 +0,0 @@ -//***************************************************************************** -// -// watchdog.h - Prototypes for the Watchdog Timer API -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 635 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __WATCHDOG_H__ -#define __WATCHDOG_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern tBoolean WatchdogRunning(unsigned long ulBase); -extern void WatchdogEnable(unsigned long ulBase); -extern void WatchdogResetEnable(unsigned long ulBase); -extern void WatchdogResetDisable(unsigned long ulBase); -extern void WatchdogLock(unsigned long ulBase); -extern void WatchdogUnlock(unsigned long ulBase); -extern tBoolean WatchdogLockState(unsigned long ulBase); -extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal); -extern unsigned long WatchdogReloadGet(unsigned long ulBase); -extern unsigned long WatchdogValueGet(unsigned long ulBase); -extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); -extern void WatchdogIntUnregister(unsigned long ulBase); -extern void WatchdogIntEnable(unsigned long ulBase); -extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void WatchdogIntClear(unsigned long ulBase); -extern void WatchdogStallDisable(unsigned long ulBase); -extern void WatchdogStallDisable(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __WATCHDOG_H__ diff --git a/Demo/CORTEX_LM3S316_IAR/main.c b/Demo/CORTEX_LM3S316_IAR/main.c deleted file mode 100644 index 33f723b63..000000000 --- a/Demo/CORTEX_LM3S316_IAR/main.c +++ /dev/null @@ -1,444 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * This demo application creates eight co-routines and four tasks (five - * including the idle task). The co-routines execute as part of the idle task - * hook. The application is limited in size to allow its compilation using - * the KickStart version of the IAR compiler. - * - * Six of the created co-routines are the standard 'co-routine flash' - * co-routines contained within the Demo/Common/Minimal/crflash.c file and - * documented on the FreeRTOS.org WEB site. - * - * The 'LCD Task' waits on a message queue for messages informing it what and - * where to display text. This is the only task that accesses the LCD - * so mutual exclusion is guaranteed. - * - * The 'LCD Message Task' periodically sends strings to the LCD Task using - * the message queue. The strings are rotated to form a short message and - * are written to the top row of the LCD. - * - * The 'ADC Co-routine' periodically reads the ADC input that is connected to - * the light sensor, forms a short message from the value, and then sends this - * message to the LCD Task using the same message queue. The ADC readings are - * displayed on the bottom row of the LCD. - * - * The eighth co-routine and final task control the transmission and reception - * of a string to UART 0. The co-routine periodically sends the first - * character of the string to the UART, with the UART's TxEnd interrupt being - * used to transmit the remaining characters. The UART's RxEnd interrupt - * receives the characters and places them on a queue to be processed by the - * 'COMs Rx' task. An error is latched should an unexpected character be - * received, or any character be received out of sequence. - * - * A loopback connector is required to ensure that each character transmitted - * on the UART is also received on the same UART. For test purposes the UART - * FIFO's are not utalised in order to maximise the interrupt overhead. Also - * a pseudo random interval is used between the start of each transmission in - * order that the resultant interrupts are more randomly distributed and - * therefore more likely to highlight any problems. - * - * The flash co-routines control LED's zero to four. LED five is toggled each - * time the string is transmitted on the UART. LED six is toggled each time - * the string is CORRECTLY received on the UART. LED seven is latched on - * should an error be detected in any task or co-routine. - * - * In addition the idle task makes repetitive calls to - * vSetAndCheckRegisters(). This simply loads the general purpose registers - * with a known value, then checks each register to ensure the held value is - * still correct. As a low priority task this checking routine is likely to - * get repeatedly swapped in and out. A register being found to contain an - * incorrect value is therefore indicative of an error in the task switching - * mechanism. - * - */ - -/* standard include files. */ -#include - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" -#include "croutine.h" - -/* Demo application include files. */ -#include "partest.h" -#include "crflash.h" -#include "commstest.h" - -/* Library include files. */ -#include "DriverLib.h" - -/* The time to delay between writing each character to the LCD. */ -#define mainCHAR_WRITE_DELAY ( 2 / portTICK_RATE_MS ) - -/* The time to delay between writing each string to the LCD. */ -#define mainSTRING_WRITE_DELAY ( 400 / portTICK_RATE_MS ) - -#define mainADC_DELAY ( 200 / portTICK_RATE_MS ) - -/* The number of flash co-routines to create. */ -#define mainNUM_FLASH_CO_ROUTINES ( 5 ) - -/* The length of the queue used to send messages to the LCD task. */ -#define mainLCD_QUEUE_LEN ( 3 ) - -/* The priority of the co-routine used to initiate the transmission of the -string on UART 0. */ -#define mainTX_CO_ROUTINE_PRIORITY ( 1 ) -#define mainADC_CO_ROUTINE_PRIORITY ( 2 ) - -/* Only one of each co-routine is created so its index is not important. */ -#define mainTX_CO_ROUTINE_INDEX ( 0 ) -#define mainADC_CO_ROUTINE_INDEX ( 0 ) - -/* The task priorities. */ -#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainMSG_TASK_PRIORITY ( mainLCD_TASK_PRIORITY - 1 ) -#define mainCOMMS_RX_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) - -/* The LCD had two rows. */ -#define mainTOP_ROW 0 -#define mainBOTTOM_ROW 1 - -/* Dimension for the buffer into which the ADC value string is written. */ -#define mainMAX_ADC_STRING_LEN 20 - -/* The LED that is lit should an error be detected in any of the tasks or -co-routines. */ -#define mainFAIL_LED ( 7 ) - -/*-----------------------------------------------------------*/ - -/* - * The task that displays text on the LCD. - */ -static void prvLCDTask( void * pvParameters ); - -/* - * The task that sends messages to be displayed on the top row of the LCD. - */ -static void prvLCDMessageTask( void * pvParameters ); - -/* - * The co-routine that reads the ADC and sends messages for display on the - * bottom row of the LCD. - */ -static void prvADCCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); - -/* - * Function to simply set a known value into the general purpose registers - * then read them back to ensure they remain set correctly. An incorrect value - * being indicative of an error in the task switching mechanism. - */ -extern void vSetAndCheckRegisters( void ); - -/* - * Latch the LED that indicates that an error has occurred. - */ -void vSetErrorLED( void ); - -/* - * Thread safe write to the PDC. - */ -static void prvPDCWrite( portCHAR cAddress, portCHAR cData ); - -/* - * Sets up the hardware used by the demo. - */ -static void prvSetupHardware( void ); - - -/*-----------------------------------------------------------*/ - -/* The structure that is passed on the LCD message queue. */ -typedef struct -{ - portCHAR **ppcMessageToDisplay; /*<< Points to a char* pointing to the message to display. */ - portBASE_TYPE xRow; /*<< The row on which the message should be displayed. */ -} xLCDMessage; - -/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines -defined within this file. */ -unsigned portBASE_TYPE uxErrorStatus = pdPASS; - -/* The queue used to transmit messages to the LCD task. */ -static xQueueHandle xLCDQueue; - -/*-----------------------------------------------------------*/ - -/* - * Setup the hardware, create the tasks/co-routines, then start the scheduler. - */ -void main( void ) -{ - /* Create the queue used by tasks wanting to write to the LCD. */ - xLCDQueue = xQueueCreate( mainLCD_QUEUE_LEN, sizeof( xLCDMessage ) ); - - /* Setup the ports used by the demo and the clock. */ - prvSetupHardware(); - - /* Create the co-routines that flash the LED's. */ - vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES ); - - /* Create the co-routine that initiates the transmission of characters - on the UART and the task that receives them, as described at the top of - this file. */ - xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX ); - xTaskCreate( vCommsRxTask, "CMS", configMINIMAL_STACK_SIZE, NULL, mainCOMMS_RX_TASK_PRIORITY, NULL ); - - /* Create the task that waits for messages to display on the LCD, plus the - task and co-routine that send messages for display (as described at the top - of this file. */ - xTaskCreate( prvLCDTask, "LCD", configMINIMAL_STACK_SIZE, ( void * ) &xLCDQueue, mainLCD_TASK_PRIORITY, NULL ); - xTaskCreate( prvLCDMessageTask, "MSG", configMINIMAL_STACK_SIZE, ( void * ) &xLCDQueue, mainMSG_TASK_PRIORITY, NULL ); - xCoRoutineCreate( prvADCCoRoutine, mainADC_CO_ROUTINE_PRIORITY, mainADC_CO_ROUTINE_INDEX ); - - /* Start the scheduler running the tasks and co-routines just created. */ - vTaskStartScheduler(); - - /* Should not get here unless we did not have enough memory to start the - scheduler. */ - for( ;; ); -} -/*-----------------------------------------------------------*/ - -static void prvLCDMessageTask( void * pvParameters ) -{ -/* The strings that are written to the LCD. */ -portCHAR *pcStringsToDisplay[] = { - "IAR ", - "Stellaris ", - "Demo ", - "www.FreeRTOS.org", - "" - }; - -xQueueHandle *pxLCDQueue; -xLCDMessage xMessageToSend; -portBASE_TYPE xIndex = 0; - - /* To test the parameter passing mechanism, the queue on which messages are - posted is passed in as a parameter even though it is available as a file - scope variable anyway. */ - pxLCDQueue = ( xQueueHandle * ) pvParameters; - - for( ;; ) - { - /* Wait until it is time to move onto the next string. */ - vTaskDelay( mainSTRING_WRITE_DELAY ); - - /* Create the message object to send to the LCD task. */ - xMessageToSend.ppcMessageToDisplay = &pcStringsToDisplay[ xIndex ]; - xMessageToSend.xRow = mainTOP_ROW; - - /* Post the message to be displayed. */ - if( !xQueueSend( *pxLCDQueue, ( void * ) &xMessageToSend, 0 ) ) - { - uxErrorStatus = pdFAIL; - } - - /* Move onto the next message, wrapping when necessary. */ - xIndex++; - if( *( pcStringsToDisplay[ xIndex ] ) == 0x00 ) - { - xIndex = 0; - - /* Delay longer before going back to the start of the messages. */ - vTaskDelay( mainSTRING_WRITE_DELAY * 2 ); - } - } -} -/*-----------------------------------------------------------*/ - -void prvLCDTask( void * pvParameters ) -{ -unsigned portBASE_TYPE uxIndex; -xQueueHandle *pxLCDQueue; -xLCDMessage xReceivedMessage; -portCHAR *pcString; -const unsigned portCHAR ucCFGData[] = { - 0x30, /* Set data bus to 8-bits. */ - 0x30, - 0x30, - 0x3C, /* Number of lines/font. */ - 0x08, /* Display off. */ - 0x01, /* Display clear. */ - 0x06, /* Entry mode [cursor dir][shift]. */ - 0x0C /* Display on [display on][curson on][blinking on]. */ - }; - - /* To test the parameter passing mechanism, the queue on which messages are - received is passed in as a parameter even though it is available as a file - scope variable anyway. */ - pxLCDQueue = ( xQueueHandle * ) pvParameters; - - /* Configure the LCD. */ - uxIndex = 0; - while( uxIndex < sizeof( ucCFGData ) ) - { - prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] ); - uxIndex++; - vTaskDelay( mainCHAR_WRITE_DELAY ); - } - - /* Turn the LCD Backlight on. */ - prvPDCWrite( PDC_CSR, 0x01 ); - - /* Clear display. */ - vTaskDelay( mainCHAR_WRITE_DELAY ); - prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); - - uxIndex = 0; - for( ;; ) - { - /* Wait for a message to arrive. */ - if( xQueueReceive( *pxLCDQueue, &xReceivedMessage, portMAX_DELAY ) ) - { - /* Which row does the received message say to write to? */ - PDCLCDSetPos( 0, xReceivedMessage.xRow ); - - /* Where is the string we are going to display? */ - pcString = *xReceivedMessage.ppcMessageToDisplay; - - while( *pcString ) - { - /* Don't write out the string too quickly as LCD's are usually - pretty slow devices. */ - vTaskDelay( mainCHAR_WRITE_DELAY ); - prvPDCWrite( PDC_LCD_RAM, *pcString ); - pcString++; - } - } - } -} -/*-----------------------------------------------------------*/ - -static void prvADCCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) -{ -static unsigned portLONG ulADCValue; -static portCHAR cMessageBuffer[ mainMAX_ADC_STRING_LEN ]; -static portCHAR *pcMessage; -static xLCDMessage xMessageToSend; - - /* Co-routines MUST start with a call to crSTART(). */ - crSTART( xHandle ); - - for( ;; ) - { - /* Start an ADC conversion. */ - ADCProcessorTrigger( ADC_BASE, 0 ); - - /* Simply delay - when we unblock the result should be available */ - crDELAY( xHandle, mainADC_DELAY ); - - /* Get the ADC result. */ - ADCSequenceDataGet( ADC_BASE, 0, &ulADCValue ); - - /* Create a string with the result. */ - sprintf( cMessageBuffer, "ADC = %d ", ulADCValue ); - pcMessage = cMessageBuffer; - - /* Configure the message we are going to send for display. */ - xMessageToSend.ppcMessageToDisplay = ( portCHAR** ) &pcMessage; - xMessageToSend.xRow = mainBOTTOM_ROW; - - /* Send the string to the LCD task for display. We are sending - on a task queue so do not have the option to block. */ - if( !xQueueSend( xLCDQueue, ( void * ) &xMessageToSend, 0 ) ) - { - uxErrorStatus = pdFAIL; - } - } - - /* Co-routines MUST end with a call to crEND(). */ - crEND(); -} -/*-----------------------------------------------------------*/ - -static void prvSetupHardware( void ) -{ - /* Setup the PLL. */ - SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); - - /* Initialise the hardware used to talk to the LCD, LED's and UART. */ - PDCInit(); - vParTestInitialise(); - vSerialInit(); - - /* The ADC is used to read the light sensor. */ - SysCtlPeripheralEnable( SYSCTL_PERIPH_ADC ); - ADCSequenceConfigure( ADC_BASE, 3, ADC_TRIGGER_PROCESSOR, 0); - ADCSequenceStepConfigure( ADC_BASE, 0, 0, ADC_CTL_CH0 | ADC_CTL_END ); - ADCSequenceEnable( ADC_BASE, 0 ); - -} -/*-----------------------------------------------------------*/ - -static void prvPDCWrite( portCHAR cAddress, portCHAR cData ) -{ - vTaskSuspendAll(); - { - PDCWrite( cAddress, cData ); - } - xTaskResumeAll(); -} -/*-----------------------------------------------------------*/ - -void vSetErrorLED( void ) -{ - vParTestSetLED( mainFAIL_LED, pdTRUE ); -} -/*-----------------------------------------------------------*/ - -void vApplicationIdleHook( void ) -{ - /* The co-routines are executed in the idle task using the idle task - hook. */ - for( ;; ) - { - /* Schedule the co-routines. */ - vCoRoutineSchedule(); - - /* Run the register check function between each co-routine. */ - vSetAndCheckRegisters(); - - /* See if the comms task and co-routine has found any errors. */ - if( uxGetCommsStatus() != pdPASS ) - { - vParTestSetLED( mainFAIL_LED, pdTRUE ); - } - } -} -/*-----------------------------------------------------------*/ diff --git a/Demo/CORTEX_LM3S316_IAR/registertest.s b/Demo/CORTEX_LM3S316_IAR/registertest.s deleted file mode 100644 index 7f27b5f48..000000000 --- a/Demo/CORTEX_LM3S316_IAR/registertest.s +++ /dev/null @@ -1,60 +0,0 @@ - RSEG ICODE:CODE - - EXTERN vSetErrorLED - - PUBLIC vSetAndCheckRegisters - -vSetAndCheckRegisters: - /* Fill the general purpose registers with known values. */ - mov r11, #10 - add r0, r11, #1 - add r1, r11, #2 - add r2, r11, #3 - add r3, r11, #4 - add r4, r11, #5 - add r5, r11, #6 - add r6, r11, #7 - add r7, r11, #8 - add r8, r11, #9 - add r9, r11, #10 - add r10, r11, #11 - add r12, r11, #12 - - /* Check the values are as expected. */ - cmp r11, #10 - bne set_error_led - cmp r0, #11 - bne set_error_led - cmp r1, #12 - bne set_error_led - cmp r2, #13 - bne set_error_led - cmp r3, #14 - bne set_error_led - cmp r4, #15 - bne set_error_led - cmp r5, #16 - bne set_error_led - cmp r6, #17 - bne set_error_led - cmp r7, #18 - bne set_error_led - cmp r8, #19 - bne set_error_led - cmp r9, #20 - bne set_error_led - cmp r10, #21 - bne set_error_led - cmp r12, #22 - bne set_error_led - bx lr - -set_error_led: - push {r14} - ldr r1, =vSetErrorLED - blx r1 - pop {r14} - bx lr - - END - diff --git a/Demo/CORTEX_LM3S316_IAR/settings/RTOSDemo.dbgdt b/Demo/CORTEX_LM3S316_IAR/settings/RTOSDemo.dbgdt deleted file mode 100644 index f583dfcf3..000000000 --- a/Demo/CORTEX_LM3S316_IAR/settings/RTOSDemo.dbgdt +++ /dev/null @@ -1,65 +0,0 @@ - - - - - - 300 - - - - - - - 274272727 - - - - - - - - 200 - - - - 100 - - 20 - 1004 - 267 - 66 - 300Debug-LogBreakpoints - 20011210310010020020014010010010030010300Debug-LogBuild1001001 - - - - - - - TabID-30594-29847 - Workspace - Workspace - - - RTOSDemoRTOSDemo/FreeRTOS SourceRTOSDemo/FreeRTOS Source/croutine.c - - - - 0TabID-30273-20034Debug LogDebug-Log0 - - - - - - TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\main.c0182781778170TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\FreeRTOSConfig.h02119911991TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\hw_include\startup.c025496449644TextEditorC:\E\Dev\FreeRTOS\Source\tasks.c073326424264240100000010000001 - - - - - - - iaridepm1debuggergui1-2-2728348-2-2200200142857205761250000751029-2-21981402-2-214042001002857205761142857205761 - - - - diff --git a/Demo/CORTEX_LM3S316_IAR/settings/RTOSDemo.dni b/Demo/CORTEX_LM3S316_IAR/settings/RTOSDemo.dni deleted file mode 100644 index 15689c4d4..000000000 --- a/Demo/CORTEX_LM3S316_IAR/settings/RTOSDemo.dni +++ /dev/null @@ -1,32 +0,0 @@ -[JLinkDriver] -WatchCond=_ 0 -Watch0=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 -Watch1=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 -[DisAssemblyWindow] -NumStates=_ 1 -State 1=_ 1 -[StackPlugin] -Enabled=1 -OverflowWarningsEnabled=1 -WarningThreshold=90 -SpWarningsEnabled=1 -WarnHow=0 -UseTrigger=1 -TriggerName=main -LimitSize=0 -ByteLimit=50 -[Log file] -LoggingEnabled=_ 0 -LogFile=_ "" -Category=_ 0 -[TermIOLog] -LoggingEnabled=_ 0 -LogFile=_ "" -[Disassemble mode] -mode=1 -[Breakpoints] -Bp0=_ "Log" "Memory8:0x20000850" 0 0 0 0 "" 0 "" 0 -Count=1 -[TraceHelper] -Enabled=0 -ShowSource=1 diff --git a/Demo/CORTEX_LM3S316_IAR/settings/RTOSDemo.wsdt b/Demo/CORTEX_LM3S316_IAR/settings/RTOSDemo.wsdt deleted file mode 100644 index 0642cf610..000000000 --- a/Demo/CORTEX_LM3S316_IAR/settings/RTOSDemo.wsdt +++ /dev/null @@ -1,58 +0,0 @@ - - - - - - RTOSDemo/Debug - - - - - - - - - 186272727 - - - - - - - 30020100426766 - - - - - - - - - - TabID-2928-28933 - Workspace - Workspace - - - RTOSDemoRTOSDemo/Demo Source - - - - 0TabID-24894-24921BuildBuildTabID-10790-31422Debug LogDebug-Log0 - - - - - - TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\main.c0182781778170TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\FreeRTOSConfig.h02119911991TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\hw_include\startup.c025496449644TextEditorC:\E\Dev\FreeRTOS\Source\tasks.c073326424264240100000010000001 - - - - - - - iaridepm1-2-2728260-2-2200200142857205761187143751029-2-21981402-2-214042001002857205761142857205761 - - - - diff --git a/Demo/CORTEX_LM3S316_IAR/settings/driverlib.wsdt b/Demo/CORTEX_LM3S316_IAR/settings/driverlib.wsdt deleted file mode 100644 index 6deb801e8..000000000 --- a/Demo/CORTEX_LM3S316_IAR/settings/driverlib.wsdt +++ /dev/null @@ -1,51 +0,0 @@ - - - - - - - - qs_dk-lm3s316/Debug - - - - - - - - - 253272727 - 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- - - - - - iaridepm1-2-2728327-2-2200200142857205761235000751029-2-21981402-2-214042001002857205761142857205761 - - - - diff --git a/Demo/CORTEX_LM3S316_IAR/standalone.xcl b/Demo/CORTEX_LM3S316_IAR/standalone.xcl deleted file mode 100644 index fdd107a75..000000000 --- a/Demo/CORTEX_LM3S316_IAR/standalone.xcl +++ /dev/null @@ -1,37 +0,0 @@ -//***************************************************************************** -// -// standalone.xcl - Linker script for EW-ARM. -// -// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. -// -//***************************************************************************** - -// -// Set the CPU type to ARM. -// --carm - -// -// Define the size of flash and SRAM. -// --DROMSTART=00000000 --DROMEND=0000FFFF --DRAMSTART=20000000 --DRAMEND=20001FFF - -// -// Define the sections to place into flash, and the order to place them. -// --Z(CODE)INTVEC=ROMSTART-ROMEND --Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND --Z(CODE)CODE=ROMSTART-ROMEND --Z(CONST)CODE_ID=ROMSTART-ROMEND --Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND --Z(CONST)CHECKSUM=ROMSTART-ROMEND - -// -// Define the sections to place into SRAM, and the order to place them. -// --Z(DATA)VTABLE=RAMSTART-RAMEND --Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND --Z(DATA)CODE_I=RAMSTART-RAMEND diff --git a/Demo/CORTEX_LM3S811_GCC/FreeRTOSConfig.h b/Demo/CORTEX_LM3S811_GCC/FreeRTOSConfig.h deleted file mode 100644 index f68f96346..000000000 --- a/Demo/CORTEX_LM3S811_GCC/FreeRTOSConfig.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 ) -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 70 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 7000 ) ) -#define configMAX_TASK_NAME_LEN ( 10 ) -#define configUSE_TRACE_FACILITY 0 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 0 -#define configUSE_CO_ROUTINES 0 - -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 0 -#define INCLUDE_uxTaskPriorityGet 0 -#define INCLUDE_vTaskDelete 0 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 0 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 - - - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/CORTEX_LM3S811_GCC/Makefile b/Demo/CORTEX_LM3S811_GCC/Makefile deleted file mode 100644 index 814cc6f7e..000000000 --- a/Demo/CORTEX_LM3S811_GCC/Makefile +++ /dev/null @@ -1,85 +0,0 @@ -#****************************************************************************** -# -# Makefile - Rules for building the driver library and examples. -# -# Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -# -# Software License Agreement -# -# Luminary Micro, Inc. (LMI) is supplying this software for use solely and -# exclusively on LMI's Stellaris Family of microcontroller products. -# -# The software is owned by LMI and/or its suppliers, and is protected under -# applicable copyright laws. All rights are reserved. Any use in violation -# of the foregoing restrictions may subject the user to criminal sanctions -# under applicable laws, as well as to civil liability for the breach of the -# terms and conditions of this license. -# -# THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -# OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -# LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -# CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -# -#****************************************************************************** - -include makedefs - -RTOS_SOURCE_DIR=../../Source -DEMO_SOURCE_DIR=../Common/Minimal - -CFLAGS+=-I hw_include -I . -I ${RTOS_SOURCE_DIR}/include -I ${RTOS_SOURCE_DIR}/portable/GCC/ARM_CM3 -I ../Common/include -D GCC_ARMCM3_LM3S102 -D inline= - -VPATH=${RTOS_SOURCE_DIR}:${RTOS_SOURCE_DIR}/portable/MemMang:${RTOS_SOURCE_DIR}/portable/GCC/ARM_CM3:${DEMO_SOURCE_DIR}:init:hw_include - -OBJS=${COMPILER}/main.o \ - ${COMPILER}/list.o \ - ${COMPILER}/queue.o \ - ${COMPILER}/tasks.o \ - ${COMPILER}/port.o \ - ${COMPILER}/heap_1.o \ - ${COMPILER}/BlockQ.o \ - ${COMPILER}/PollQ.o \ - ${COMPILER}/integer.o \ - ${COMPILER}/semtest.o \ - ${COMPILER}/osram96x16.o - -INIT_OBJS= ${COMPILER}/startup.o - -LIBS= hw_include/libdriver.a - - -# -# The default rule, which causes init to be built. -# -all: ${COMPILER} \ - ${COMPILER}/RTOSDemo.axf \ - -# -# The rule to clean out all the build products -# - -clean: - @rm -rf ${COMPILER} ${wildcard *.bin} RTOSDemo.axf - -# -# The rule to create the target directory -# -${COMPILER}: - @mkdir ${COMPILER} - -${COMPILER}/RTOSDemo.axf: ${INIT_OBJS} ${OBJS} ${LIBS} -SCATTER_RTOSDemo=standalone.ld -ENTRY_RTOSDemo=ResetISR - -# -# -# Include the automatically generated dependency files. -# --include ${wildcard ${COMPILER}/*.d} __dummy__ - - - - - - diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/DriverLib.h b/Demo/CORTEX_LM3S811_GCC/hw_include/DriverLib.h deleted file mode 100644 index 47531fbe9..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/DriverLib.h +++ /dev/null @@ -1,39 +0,0 @@ -#ifndef DRIVER_LIB_H -#define DRIVER_LIB_H - -#include "DriverLib.h" -#include "hw_adc.h" -#include "hw_comp.h" -#include "hw_flash.h" -#include "hw_gpio.h" -#include "hw_i2c.h" -#include "hw_ints.h" -#include "hw_memmap.h" -#include "hw_nvic.h" -#include "hw_pwm.h" -#include "hw_qei.h" -#include "hw_ssi.h" -#include "hw_sysctl.h" -#include "hw_timer.h" -#include "hw_types.h" -#include "hw_uart.h" -#include "hw_watchdog.h" -#include "osram96x16.h" -#include "adc.h" -#include "comp.h" -#include "cpu.h" -#include "debug.h" -#include "flash.h" -#include "gpio.h" -#include "i2c.h" -#include "interrupt.h" -#include "pwm.h" -#include "qei.h" -#include "ssi.h" -#include "sysctl.h" -#include "systick.h" -#include "timer.h" -#include "uart.h" -#include "watchdog.h" - -#endif diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/EULA.txt b/Demo/CORTEX_LM3S811_GCC/hw_include/EULA.txt deleted file mode 100644 index 02c57b2f9..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/EULA.txt +++ /dev/null @@ -1,126 +0,0 @@ -IMPORTANT. Read the following LMI Software License Agreement ("Agreement") -completely. - -LUMINARY MICRO SOFTWARE LICENSE AGREEMENT - - This is a legal agreement between you (either as an individual or as an -authorized representative of your employer) and Luminary Micro, Inc. ("LMI"). -It concerns your rights to use this file and any accompanying written materials -(the "Software"). In consideration for LMI allowing you to access the -Software, you are agreeing to be bound by the terms of this Agreement. If you -do not agree to all of the terms of this Agreement, do not download or use the -Software. If you change your mind later, stop using the Software and delete -all copies of the Software in your possession or control. Any copies of the -Software that you have already distributed, where permitted, and do not destroy -will continue to be governed by this Agreement. Your prior use will also -continue to be governed by this Agreement. - -1. LICENSE GRANT. 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The waiver by LMI of any breach of any provision of this -Agreement will not operate or be construed as a waiver of any other or a -subsequent breach of the same or a different provision. diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/adc.c b/Demo/CORTEX_LM3S811_GCC/hw_include/adc.c deleted file mode 100644 index 53f3adf5b..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/adc.c +++ /dev/null @@ -1,946 +0,0 @@ -//***************************************************************************** -// -// adc.c - Driver for the ADC. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup adc_api -//! @{ -// -//***************************************************************************** - -#include "../hw_adc.h" -#include "../hw_ints.h" -#include "../hw_memmap.h" -#include "../hw_types.h" -#include "adc.h" -#include "debug.h" -#include "interrupt.h" - -//***************************************************************************** -// -// The currently configured software oversampling factor for each of the ADC -// sequencers. -// -//***************************************************************************** -#if defined(GROUP_pucoverssamplefactor) || defined(BUILD_ALL) -unsigned char g_pucOversampleFactor[3]; -#else -extern unsigned char g_pucOversampleFactor[3]; -#endif - -//***************************************************************************** -// -//! Registers an interrupt handler for an ADC interrupt. -//! -//! \param ulBase is the base address of the ADC module. -//! \param ulSequenceNum is the sample sequence number. -//! \param pfnHandler is a pointer to the function to be called when the -//! ADC sample sequence interrupt occurs. -//! -//! This function sets the handler to be called when a sample sequence -//! interrupt occurs. This will enable the global interrupt in the interrupt -//! controller; the sequence interrupt must be enabled with ADCIntEnable(). It -//! is the interrupt handler's responsibility to clear the interrupt source via -//! ADCIntClear(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum, - void (*pfnHandler)(void)) -{ - unsigned long ulInt; - - // - // Check the arguments. - // - ASSERT(ulBase == ADC_BASE); - ASSERT(ulSequenceNum < 4); - - // - // Determine the interrupt to register based on the sequence number. - // - ulInt = INT_ADC0 + ulSequenceNum; - - // - // Register the interrupt handler. - // - IntRegister(ulInt, pfnHandler); - - // - // Enable the timer interrupt. - // - IntEnable(ulInt); -} -#endif - -//***************************************************************************** -// -//! Unregisters the interrupt handler for an ADC interrupt. -//! -//! \param ulBase is the base address of the ADC module. -//! \param ulSequenceNum is the sample sequence number. -//! -//! This function unregisters the interrupt handler. This will disable the -//! global interrupt in the interrupt controller; the sequence interrupt must -//! be disabled via ADCIntDisable(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -ADCIntUnregister(unsigned long ulBase, unsigned long ulSequenceNum) -{ - unsigned long ulInt; - - // - // Check the arguments. - // - ASSERT(ulBase == ADC_BASE); - ASSERT(ulSequenceNum < 4); - - // - // Determine the interrupt to unregister based on the sequence number. - // - ulInt = INT_ADC0 + ulSequenceNum; - - // - // Disable the interrupt. - // - IntDisable(ulInt); - - // - // Unregister the interrupt handler. - // - IntUnregister(ulInt); -} -#endif - -//***************************************************************************** -// -//! Disables a sample sequence interrupt. -//! -//! \param ulBase is the base address of the ADC module. -//! \param ulSequenceNum is the sample sequence number. -//! -//! This function disables the requested sample sequence interrupt. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum) -{ - // - // Check the arguments. - // - ASSERT(ulBase == ADC_BASE); - ASSERT(ulSequenceNum < 4); - - // - // Disable this sample sequence interrupt. - // - HWREG(ulBase + ADC_O_IM) &= ~(1 << ulSequenceNum); -} -#endif - -//***************************************************************************** -// -//! Enables a sample sequence interrupt. -//! -//! \param ulBase is the base address of the ADC module. -//! \param ulSequenceNum is the sample sequence number. -//! -//! This function enables the requested sample sequence interrupt. Any -//! outstanding interrupts are cleared before enabling the sample sequence -//! interrupt. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum) -{ - // - // Check the arguments. - // - ASSERT(ulBase == ADC_BASE); - ASSERT(ulSequenceNum < 4); - - // - // Clear any outstanding interrupts on this sample sequence. - // - HWREG(ulBase + ADC_O_ISC) = 1 << ulSequenceNum; - - // - // Enable this sample sequence interrupt. - // - HWREG(ulBase + ADC_O_IM) |= 1 << ulSequenceNum; -} -#endif - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \param ulBase is the base address of the ADC module. -//! \param ulSequenceNum is the sample sequence number. -//! \param bMasked is false if the raw interrupt status is required and true if -//! the masked interrupt status is required. -//! -//! This returns the interrupt status for the specified sample sequence. -//! Either the raw interrupt status or the status of interrupts that are -//! allowed to reflect to the processor can be returned. -//! -//! \return The current raw or masked interrupt status. -// -//***************************************************************************** -#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -ADCIntStatus(unsigned long ulBase, unsigned long ulSequenceNum, - tBoolean bMasked) -{ - // - // Check the arguments. - // - ASSERT(ulBase == ADC_BASE); - ASSERT(ulSequenceNum < 4); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(ulBase + ADC_O_ISC) & (1 << ulSequenceNum)); - } - else - { - return(HWREG(ulBase + ADC_O_RIS) & (1 << ulSequenceNum)); - } -} -#endif - -//***************************************************************************** -// -//! Clears sample sequence interrupt source. -//! -//! \param ulBase is the base address of the ADC module. -//! \param ulSequenceNum is the sample sequence number. -//! -//! The specified sample sequence interrupt is cleared, so that it no longer -//! asserts. This must be done in the interrupt handler to keep it from being -//! called again immediately upon exit. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) -void -ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum) -{ - // - // Check the arugments. - // - ASSERT(ulBase == ADC_BASE); - ASSERT(ulSequenceNum < 4); - - // - // Clear the interrupt. - // - HWREG(ulBase + ADC_O_ISC) = 1 << ulSequenceNum; -} -#endif - -//***************************************************************************** -// -//! Enables a sample sequence. -//! -//! \param ulBase is the base address of the ADC module. -//! \param ulSequenceNum is the sample sequence number. -//! -//! Allows the specified sample sequence to be captured when its trigger is -//! detected. A sample sequence must be configured before it is enabled. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_sequenceenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -ADCSequenceEnable(unsigned long ulBase, unsigned long ulSequenceNum) -{ - // - // Check the arugments. - // - ASSERT(ulBase == ADC_BASE); - ASSERT(ulSequenceNum < 4); - - // - // Enable the specified sequence. - // - HWREG(ulBase + ADC_O_ACTSS) |= 1 << ulSequenceNum; -} -#endif - -//***************************************************************************** -// -//! Disables a sample sequence. -//! -//! \param ulBase is the base address of the ADC module. -//! \param ulSequenceNum is the sample sequence number. -//! -//! Prevents the specified sample sequence from being captured when its trigger -//! is detected. A sample sequence should be disabled before it is configured. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_sequencedisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -ADCSequenceDisable(unsigned long ulBase, unsigned long ulSequenceNum) -{ - // - // Check the arugments. - // - ASSERT(ulBase == ADC_BASE); - ASSERT(ulSequenceNum < 4); - - // - // Disable the specified sequences. - // - HWREG(ulBase + ADC_O_ACTSS) &= ~(1 << ulSequenceNum); -} -#endif - -//***************************************************************************** -// -//! Configures the trigger source and priority of a sample sequence. -//! -//! \param ulBase is the base address of the ADC module. -//! \param ulSequenceNum is the sample sequence number. -//! \param ulTrigger is the trigger source that initiates the sample sequence; -//! must be one of the \b ADC_TRIGGER_* values. -//! \param ulPriority is the relative priority of the sample sequence with -//! respect to the other sample sequences. -//! -//! This function configures the initiation criteria for a sample sequence. -//! Valid sample sequences range from zero to three; sequence zero will capture -//! up to eight samples, sequences one and two will capture up to four samples, -//! and sequence three will capture a single sample. The trigger condition and -//! priority (with respect to other sample sequence execution) is set. -//! -//! The parameter \b ulTrigger can take on the following values: -//! -//! - \b ADC_TRIGGER_PROCESSOR - A trigger generated by the processor, via the -//! ADCProcessorTrigger() function. -//! - \b ADC_TRIGGER_COMP0 - A trigger generated by the first analog -//! comparator; configured with ComparatorConfigure(). -//! - \b ADC_TRIGGER_COMP1 - A trigger generated by the second analog -//! comparator; configured with ComparatorConfigure(). -//! - \b ADC_TRIGGER_COMP2 - A trigger generated by the third analog -//! comparator; configured with ComparatorConfigure(). -//! - \b ADC_TRIGGER_EXTERNAL - A trigger generated by an input from the Port -//! B4 pin. -//! - \b ADC_TRIGGER_TIMER - A trigger generated by a timer; configured with -//! TimerControlTrigger(). -//! - \b ADC_TRIGGER_PWM0 - A trigger generated by the first PWM generator; -//! configured with PWMGenIntTrigEnable(). -//! - \b ADC_TRIGGER_PWM1 - A trigger generated by the second PWM generator; -//! configured with PWMGenIntTrigEnable(). -//! - \b ADC_TRIGGER_PWM2 - A trigger generated by the third PWM generator; -//! configured with PWMGenIntTrigEnable(). -//! - \b ADC_TRIGGER_ALWAYS - A trigger that is always asserted, causing the -//! sample sequence to capture repeatedly (so long as -//! there is not a higher priority source active). -//! -//! Note that not all trigger sources are available on all Stellaris family -//! members; consult the data sheet for the device in question to determine the -//! availability of triggers. -//! -//! The parameter \b ulPriority is a value between 0 and 3, where 0 represents -//! the highest priority and 3 the lowest. Note that when programming the -//! priority among a set of sample sequences, each must have unique priority; -//! it is up to the caller to guarantee the uniqueness of the priorities. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_sequenceconfigure) || defined(BUILD_ALL) || defined(DOXYGEN) -void -ADCSequenceConfigure(unsigned long ulBase, unsigned long ulSequenceNum, - unsigned long ulTrigger, unsigned long ulPriority) -{ - // - // Check the arugments. - // - ASSERT(ulBase == ADC_BASE); - ASSERT(ulSequenceNum < 4); - ASSERT((ulTrigger == ADC_TRIGGER_PROCESSOR) || - (ulTrigger == ADC_TRIGGER_COMP0) || - (ulTrigger == ADC_TRIGGER_COMP1) || - (ulTrigger == ADC_TRIGGER_COMP2) || - (ulTrigger == ADC_TRIGGER_EXTERNAL) || - (ulTrigger == ADC_TRIGGER_TIMER) || - (ulTrigger == ADC_TRIGGER_PWM0) || - (ulTrigger == ADC_TRIGGER_PWM1) || - (ulTrigger == ADC_TRIGGER_PWM2) || - (ulTrigger == ADC_TRIGGER_ALWAYS)); - ASSERT(ulPriority < 4); - - // - // Compute the shift for the bits that control this sample sequence. - // - ulSequenceNum *= 4; - - // - // Set the trigger event for this sample sequence. - // - HWREG(ulBase + ADC_O_EMUX) = ((HWREG(ulBase + ADC_O_EMUX) & - ~(0xf << ulSequenceNum)) | - ((ulTrigger & 0xf) << ulSequenceNum)); - - // - // Set the priority for this sample sequence. - // - HWREG(ulBase + ADC_O_SSPRI) = ((HWREG(ulBase + ADC_O_SSPRI) & - ~(0xf << ulSequenceNum)) | - ((ulPriority & 0x3) << ulSequenceNum)); -} -#endif - -//***************************************************************************** -// -//! Configure a step of the sample sequencer. -//! -//! \param ulBase is the base address of the ADC module. -//! \param ulSequenceNum is the sample sequence number. -//! \param ulStep is the step to be configured. -//! \param ulConfig is the configuration of this step; must be a logical OR of -//! \b ADC_CTL_TS, \b ADC_CTL_IE, \b ADC_CTL_END, \b ADC_CTL_D, and one of the -//! input channel selects (\b ADC_CTL_CH0 through \b ADC_CTL_CH7). -//! -//! This function will set the configuration of the ADC for one step of a -//! sample sequence. The ADC can be configured for single-ended or -//! differential operation (the \b ADC_CTL_D bit selects differential -//! operation when set), the channel to be sampled can be chosen (the -//! \b ADC_CTL_CH0 through \b ADC_CTL_CH7 values), and the internal temperature -//! sensor can be selected (the \b ADC_CTL_TS bit). Additionally, this step -//! can be defined as the last in the sequence (the \b ADC_CTL_END bit) and it -//! can be configured to cause an interrupt when the step is complete (the -//! \b ADC_CTL_IE bit). The configuration is used by the ADC at the -//! appropriate time when the trigger for this sequence occurs. -//! -//! The \b ulStep parameter determines the order in which the samples are -//! captured by the ADC when the trigger occurs. It can range from zero to -//! seven for the first sample sequence, from zero to three for the second and -//! third sample sequence, and can only be zero for the fourth sample sequence. -//! -//! Differential mode only works with adjacent channel pairs (e.g. 0 and 1). -//! The channel select must be the number of the channel pair to sample (e.g. -//! \b ADC_CTL_CH0 for 0 and 1, or \b ADC_CTL_CH1 for 2 and 3) or undefined -//! results will be returned by the ADC. Additionally, if differential mode is -//! selected when the temperature sensor is being sampled, undefined results -//! will be returned by the ADC. -//! -//! It is the responsibility of the caller to ensure that a valid configuration -//! is specified; this function does not check the validity of the specified -//! configuration. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_sequencestepconfigure) || defined(BUILD_ALL) || \ - defined(DOXYGEN) -void -ADCSequenceStepConfigure(unsigned long ulBase, unsigned long ulSequenceNum, - unsigned long ulStep, unsigned long ulConfig) -{ - // - // Check the arugments. - // - ASSERT(ulBase == ADC_BASE); - ASSERT(ulSequenceNum < 4); - ASSERT(((ulSequenceNum == 0) && (ulStep < 8)) || - ((ulSequenceNum == 1) && (ulStep < 4)) || - ((ulSequenceNum == 2) && (ulStep < 4)) || - ((ulSequenceNum == 3) && (ulStep < 1))); - - // - // Get the offset of the sequence to be configured. - // - ulBase += ADC_O_SEQ + (ADC_O_SEQ_STEP * ulSequenceNum); - - // - // Compute the shift for the bits that control this step. - // - ulStep *= 4; - - // - // Set the analog mux value for this step. - // - HWREG(ulBase + ADC_O_X_SSMUX) = ((HWREG(ulBase + ADC_O_X_SSMUX) & - ~(0x0000000f << ulStep)) | - ((ulConfig & 0x0f) << ulStep)); - - // - // Set the control value for this step. - // - HWREG(ulBase + ADC_O_X_SSCTL) = ((HWREG(ulBase + ADC_O_X_SSCTL) & - ~(0x0000000f << ulStep)) | - (((ulConfig & 0xf0) >> 4) << ulStep)); -} -#endif - -//***************************************************************************** -// -//! Determines if a sample sequence overflow occurred. -//! -//! \param ulBase is the base address of the ADC module. -//! \param ulSequenceNum is the sample sequence number. -//! -//! This determines if a sample sequence overflow has occurred. This will -//! happen if the captured samples are not read from the FIFO before the next -//! trigger occurs. -//! -//! \return Returns zero if there was not an overflow, and non-zero if there -//! was. -// -//***************************************************************************** -#if defined(GROUP_sequenceoverflow) || defined(BUILD_ALL) || defined(DOXYGEN) -long -ADCSequenceOverflow(unsigned long ulBase, unsigned long ulSequenceNum) -{ - // - // Check the arguments. - // - ASSERT(ulBase == ADC_BASE); - ASSERT(ulSequenceNum < 4); - - // - // Determine if there was an overflow on this sequence. - // - return(HWREG(ulBase + ADC_O_OSTAT) & (1 << ulSequenceNum)); -} -#endif - -//***************************************************************************** -// -//! Determines if a sample sequence underflow occurred. -//! -//! \param ulBase is the base address of the ADC module. -//! \param ulSequenceNum is the sample sequence number. -//! -//! This determines if a sample sequence underflow has occurred. This will -//! happen if too many samples are read from the FIFO. -//! -//! \return Returns zero if there was not an underflow, and non-zero if there -//! was. -// -//***************************************************************************** -#if defined(GROUP_sequenceunderflow) || defined(BUILD_ALL) || defined(DOXYGEN) -long -ADCSequenceUnderflow(unsigned long ulBase, unsigned long ulSequenceNum) -{ - // - // Check the arguments. - // - ASSERT(ulBase == ADC_BASE); - ASSERT(ulSequenceNum < 4); - - // - // Determine if there was an underflow on this sequence. - // - return(HWREG(ulBase + ADC_O_USTAT) & (1 << ulSequenceNum)); -} -#endif - -//***************************************************************************** -// -//! Gets the captured data for a sample sequence. -//! -//! \param ulBase is the base address of the ADC module. -//! \param ulSequenceNum is the sample sequence number. -//! \param pulBuffer is the address where the data is stored. -//! -//! This function copies data from the specified sample sequence output FIFO to -//! a memory resident buffer. The number of samples available in the hardware -//! FIFO are copied into the buffer, which is assumed to be large enough to -//! hold that many samples. This will only return the samples that are -//! presently available, which may not be the entire sample sequence if it is -//! in the process of being executed. -//! -//! \return Returns the number of samples copied to the buffer. -// -//***************************************************************************** -#if defined(GROUP_sequencedataget) || defined(BUILD_ALL) || defined(DOXYGEN) -long -ADCSequenceDataGet(unsigned long ulBase, unsigned long ulSequenceNum, - unsigned long *pulBuffer) -{ - unsigned long ulCount; - - // - // Check the arguments. - // - ASSERT(ulBase == ADC_BASE); - ASSERT(ulSequenceNum < 4); - - // - // Get the offset of the sequence to be read. - // - ulBase += ADC_O_SEQ + (ADC_O_SEQ_STEP * ulSequenceNum); - - // - // Read samples from the FIFO until it is empty. - // - ulCount = 0; - while(!(HWREG(ulBase + ADC_O_X_SSFSTAT) & ADC_SSFSTAT_EMPTY) && - (ulCount < 8)) - { - // - // Read the FIFO and copy it to the destination. - // - *pulBuffer++ = HWREG(ulBase + ADC_O_X_SSFIFO); - - // - // Increment the count of samples read. - // - ulCount++; - } - - // - // Return the number of samples read. - // - return(ulCount); -} -#endif - -//***************************************************************************** -// -//! Causes a processor trigger for a sample sequence. -//! -//! \param ulBase is the base address of the ADC module. -//! \param ulSequenceNum is the sample sequence number. -//! -//! This function triggers a processor-initiated sample sequence if the sample -//! sequence trigger is configured to ADC_TRIGGER_PROCESSOR. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_processortrigger) || defined(BUILD_ALL) || defined(DOXYGEN) -void -ADCProcessorTrigger(unsigned long ulBase, unsigned long ulSequenceNum) -{ - // - // Check the arguments. - // - ASSERT(ulBase == ADC_BASE); - ASSERT(ulSequenceNum < 4); - - // - // Generate a processor trigger for this sample sequence. - // - HWREG(ulBase + ADC_O_PSSI) = 1 << ulSequenceNum; -} -#endif - -//***************************************************************************** -// -//! Configures the software oversampling factor of the ADC. -//! -//! \param ulBase is the base address of the ADC module. -//! \param ulSequenceNum is the sample sequence number. -//! \param ulFactor is the number of samples to be averaged. -//! -//! This function configures the software oversampling for the ADC, which can -//! be used to provide better resolution on the sampled data. Oversampling is -//! accomplished by averaging multiple samples from the same analog input. -//! Three different oversampling rates are supported; 2x, 4x, and 8x. -//! -//! Oversampling is only supported on the sample sequencers that are more than -//! one sample in depth (i.e. the fourth sample sequencer is not supported). -//! Oversampling by 2x (for example) divides the depth of the sample sequencer -//! by two; so 2x oversampling on the first sample sequencer can only provide -//! four samples per trigger. This also means that 8x oversampling is only -//! available on the first sample sequencer. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_softwareoversampleconfigure) || defined(BUILD_ALL) || \ - defined(DOXYGEN) -void -ADCSoftwareOversampleConfigure(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long ulFactor) -{ - unsigned long ulValue; - - // - // Check the arguments. - // - ASSERT(ulBase == ADC_BASE); - ASSERT(ulSequenceNum < 3); - ASSERT(((ulFactor == 2) || (ulFactor == 4) || (ulFactor == 8)) && - ((ulSequenceNum == 0) || (ulFactor != 8))); - - // - // Convert the oversampling factor to a shift factor. - // - for(ulValue = 0, ulFactor >>= 1; ulFactor; ulValue++, ulFactor >>= 1) - { - } - - // - // Save the sfiht factor. - // - g_pucOversampleFactor[ulSequenceNum] = ulValue; -} -#endif - -//***************************************************************************** -// -//! Configures a step of the software oversampled sequencer. -//! -//! \param ulBase is the base address of the ADC module. -//! \param ulSequenceNum is the sample sequence number. -//! \param ulStep is the step to be configured. -//! \param ulConfig is the configuration of this step. -//! -//! This function configures a step of the sample sequencer when using the -//! software oversampling feature. The number of steps available depends on -//! the oversampling factor set by ADCSoftwareOversampleConfigure(). The value -//! of \e ulConfig is the same as defined for ADCSequenceStepConfigure(). -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_softwareoversamplestepconfigure) || defined(BUILD_ALL) || \ - defined(DOXYGEN) -void -ADCSoftwareOversampleStepConfigure(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long ulStep, - unsigned long ulConfig) -{ - // - // Check the arguments. - // - ASSERT(ulBase == ADC_BASE); - ASSERT(ulSequenceNum < 3); - ASSERT(((ulSequenceNum == 0) && - (ulStep < (8 >> g_pucOversampleFactor[ulSequenceNum]))) || - (ulStep < (4 >> g_pucOversampleFactor[ulSequenceNum]))); - - // - // Get the offset of the sequence to be configured. - // - ulBase += ADC_O_SEQ + (ADC_O_SEQ_STEP * ulSequenceNum); - - // - // Compute the shift for the bits that control this step. - // - ulStep *= 4 << g_pucOversampleFactor[ulSequenceNum]; - - // - // Loop through the hardware steps that make up this step of the software - // oversampled sequence. - // - for(ulSequenceNum = 1 << g_pucOversampleFactor[ulSequenceNum]; - ulSequenceNum; ulSequenceNum--) - { - // - // Set the analog mux value for this step. - // - HWREG(ulBase + ADC_O_X_SSMUX) = ((HWREG(ulBase + ADC_O_X_SSMUX) & - ~(0x0000000f << ulStep)) | - ((ulConfig & 0x0f) << ulStep)); - - // - // Set the control value for this step. - // - HWREG(ulBase + ADC_O_X_SSCTL) = ((HWREG(ulBase + ADC_O_X_SSCTL) & - ~(0x0000000f << ulStep)) | - (((ulConfig & 0xf0) >> 4) << ulStep)); - if(ulSequenceNum != 1) - { - HWREG(ulBase + ADC_O_X_SSCTL) &= ~((ADC_SSCTL_IE0 | - ADC_SSCTL_END0) << ulStep); - } - - // - // Go to the next hardware step. - // - ulStep += 4; - } -} -#endif - -//***************************************************************************** -// -//! Gets the captured data for a sample sequence using software oversampling. -//! -//! \param ulBase is the base address of the ADC module. -//! \param ulSequenceNum is the sample sequence number. -//! \param pulBuffer is the address where the data is stored. -//! \param ulCount is the number of samples to be read. -//! -//! This function copies data from the specified sample sequence output FIFO to -//! a memory resident buffer with software oversampling applied. The requested -//! number of samples are copied into the data buffer; if there are not enough -//! samples in the hardware FIFO to satisfy this many oversampled data items -//! then incorrect results will be returned. It is the caller's responsibility -//! to read only the samples that are available and wait until enough data is -//! available, for example as a result of receiving an interrupt. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_softwareoversampledataget) || defined(BUILD_ALL) || \ - defined(DOXYGEN) -void -ADCSoftwareOversampleDataGet(unsigned long ulBase, unsigned long ulSequenceNum, - unsigned long *pulBuffer, unsigned long ulCount) -{ - unsigned long ulIdx, ulAccum; - - // - // Check the arguments. - // - ASSERT(ulBase == ADC_BASE); - ASSERT(ulSequenceNum < 3); - ASSERT(((ulSequenceNum == 0) && - (ulCount < (8 >> g_pucOversampleFactor[ulSequenceNum]))) || - (ulCount < (4 >> g_pucOversampleFactor[ulSequenceNum]))); - - // - // Get the offset of the sequence to be read. - // - ulBase += ADC_O_SEQ + (ADC_O_SEQ_STEP * ulSequenceNum); - - // - // Read the samples from the FIFO until it is empty. - // - while(ulCount--) - { - // - // Compute the sum of the samples. - // - ulAccum = 0; - for(ulIdx = 1 << g_pucOversampleFactor[ulSequenceNum]; ulIdx; ulIdx--) - { - // - // Read the FIFO and add it to the accumulator. - // - ulAccum += HWREG(ulBase + ADC_O_X_SSFIFO); - } - - // - // Write the averaged sample to the output buffer. - // - *pulBuffer++ = ulAccum >> g_pucOversampleFactor[ulSequenceNum]; - } -} -#endif - -//***************************************************************************** -// -//! Configures the hardware oversampling factor of the ADC. -//! -//! \param ulBase is the base address of the ADC module. -//! \param ulFactor is the number of samples to be averaged. -//! -//! This function configures the hardware oversampling for the ADC, which can -//! be used to provide better resolution on the sampled data. Oversampling is -//! accomplished by averaging multiple samples from the same analog input. Six -//! different oversampling rates are supported; 2x, 4x, 8x, 16x, 32x, and 64x. -//! Specifying an oversampling factor of zero will disable the hardware -//! oversampler. -//! -//! Hardware oversampling applies uniformly to all sample sequencers. It does -//! not reduce the depth of the sample sequencers like the software -//! oversampling APIs; each sample written into the sample sequence FIFO is a -//! fully oversampled analog input reading. -//! -//! Enabling hardware averaging increases the precision of the ADC at the cost -//! of throughput. For example, enabling 4x oversampling reduces the -//! throughput of a 250 KSps ADC to 62.5 KSps. -//! -//! \note Hardware oversampling is available beginning with Rev C0 of the -//! Stellaris microcontroller. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_hardwareoversampleconfigure) || defined(BUILD_ALL) || \ - defined(DOXYGEN) -void -ADCHardwareOversampleConfigure(unsigned long ulBase, - unsigned long ulFactor) -{ - unsigned long ulValue; - - // - // Check the arguments. - // - ASSERT(ulBase == ADC_BASE); - ASSERT(((ulFactor == 0) || (ulFactor == 2) || (ulFactor == 4) || - (ulFactor == 8) || (ulFactor == 16) || (ulFactor == 32) || - (ulFactor == 64))); - - // - // Convert the oversampling factor to a shift factor. - // - for(ulValue = 0, ulFactor >>= 1; ulFactor; ulValue++, ulFactor >>= 1) - { - } - - // - // Write the shift factor to the ADC to configure the hardware oversampler. - // - HWREG(ulBase + ADC_O_SAC) = ulValue; -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/adc.h b/Demo/CORTEX_LM3S811_GCC/hw_include/adc.h deleted file mode 100644 index c1fa37da4..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/adc.h +++ /dev/null @@ -1,126 +0,0 @@ -//***************************************************************************** -// -// adc.h - ADC headers for using the ADC driver functions. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __ADC_H__ -#define __ADC_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to ADCSequenceConfigure as the ulTrigger -// parameter. -// -//***************************************************************************** -#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event -#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event -#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event -#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event -#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event -#define ADC_TRIGGER_TIMER 0x00000005 // Timer event -#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event -#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event -#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event -#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event - -//***************************************************************************** -// -// Values that can be passed to ADCSequenceStepConfigure as the ulConfig -// parameter. -// -//***************************************************************************** -#define ADC_CTL_TS 0x00000080 // Temperature sensor select -#define ADC_CTL_IE 0x00000040 // Interrupt enable -#define ADC_CTL_END 0x00000020 // Sequence end select -#define ADC_CTL_D 0x00000010 // Differential select -#define ADC_CTL_CH0 0x00000000 // Input channel 0 -#define ADC_CTL_CH1 0x00000001 // Input channel 1 -#define ADC_CTL_CH2 0x00000002 // Input channel 2 -#define ADC_CTL_CH3 0x00000003 // Input channel 3 -#define ADC_CTL_CH4 0x00000004 // Input channel 4 -#define ADC_CTL_CH5 0x00000005 // Input channel 5 -#define ADC_CTL_CH6 0x00000006 // Input channel 6 -#define ADC_CTL_CH7 0x00000007 // Input channel 7 - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum, - void (*pfnHandler)(void)); -extern void ADCIntUnregister(unsigned long ulBase, - unsigned long ulSequenceNum); -extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum); -extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum); -extern unsigned long ADCIntStatus(unsigned long ulBase, - unsigned long ulSequenceNum, - tBoolean bMasked); -extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum); -extern void ADCSequenceEnable(unsigned long ulBase, - unsigned long ulSequenceNum); -extern void ADCSequenceDisable(unsigned long ulBase, - unsigned long ulSequenceNum); -extern void ADCSequenceConfigure(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long ulTrigger, - unsigned long ulPriority); -extern void ADCSequenceStepConfigure(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long ulStep, - unsigned long ulConfig); -extern long ADCSequenceOverflow(unsigned long ulBase, - unsigned long ulSequenceNum); -extern long ADCSequenceUnderflow(unsigned long ulBase, - unsigned long ulSequenceNum); -extern long ADCSequenceDataGet(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long *pulBuffer); -extern void ADCProcessorTrigger(unsigned long ulBase, - unsigned long ulSequenceNum); -extern void ADCSoftwareOversampleConfigure(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long ulFactor); -extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long ulStep, - unsigned long ulConfig); -extern void ADCSoftwareOversampleDataGet(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long *pulBuffer, - unsigned long ulCount); -extern void ADCHardwareOversampleConfigure(unsigned long ulBase, - unsigned long ulFactor); - -#ifdef __cplusplus -} -#endif - -#endif // __ADC_H__ diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/comp.c b/Demo/CORTEX_LM3S811_GCC/hw_include/comp.c deleted file mode 100644 index aed156ea5..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/comp.c +++ /dev/null @@ -1,448 +0,0 @@ -//***************************************************************************** -// -// comp.c - Driver for the analog comparator. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup comp_api -//! @{ -// -//***************************************************************************** - -#include "../hw_comp.h" -#include "../hw_ints.h" -#include "../hw_memmap.h" -#include "../hw_types.h" -#include "comp.h" -#include "debug.h" -#include "interrupt.h" - -//***************************************************************************** -// -//! Configures a comparator. -//! -//! \param ulBase is the base address of the comparator module. -//! \param ulComp is the index of the comparator to configure. -//! \param ulConfig is the configuration of the comparator. -//! -//! This function will configure a comparator. The \e ulConfig parameter is -//! the result of a logical OR operation between the \b COMP_TRIG_xxx, -//! \b COMP_INT_xxx, \b COMP_ASRCP_xxx, and \b COMP_OUTPUT_xxx values. -//! -//! The \b COMP_TRIG_xxx term can take on the following values: -//! -//! - \b COMP_TRIG_NONE to have no trigger to the ADC. -//! - \b COMP_TRIG_HIGH to trigger the ADC when the comparator output is high. -//! - \b COMP_TRIG_LOW to trigger the ADC when the comparator output is low. -//! - \b COMP_TRIG_FALL to trigger the ADC when the comparator output goes low. -//! - \b COMP_TRIG_RISE to trigger the ADC when the comparator output goes -//! high. -//! - \b COMP_TRIG_BOTH to trigger the ADC when the comparator output goes low -//! or high. -//! -//! The \b COMP_INT_xxx term can take on the following values: -//! -//! - \b COMP_INT_HIGH to generate an interrupt when the comparator output is -//! high. -//! - \b COMP_INT_LOW to generate an interrupt when the comparator output is -//! low. -//! - \b COMP_INT_FALL to generate an interrupt when the comparator output goes -//! low. -//! - \b COMP_INT_RISE to generate an interrupt when the comparator output goes -//! high. -//! - \b COMP_INT_BOTH to generate an interrupt when the comparator output goes -//! low or high. -//! -//! The \b COMP_ASRCP_xxx term can take on the following values: -//! -//! - \b COMP_ASRCP_PIN to use the dedicated Comp+ pin as the reference -//! voltage. -//! - \b COMP_ASRCP_PIN0 to use the Comp0+ pin as the reference voltage (this -//! the same as \b COMP_ASRCP_PIN for the comparator 0). -//! - \b COMP_ASRCP_REF to use the internally generated voltage as the -//! reference voltage. -//! -//! The \b COMP_OUTPUT_xxx term can take on the following values: -//! -//! - \b COMP_OUTPUT_NONE to disable the output from the comparator to a device -//! pin. -//! - \b COMP_OUTPUT_NORMAL to enable a non-inverted output from the comparator -//! to a device pin. -//! - \b COMP_OUTPUT_INVERT to enable an inverted output from the comparator to -//! a device pin. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_configure) || defined(BUILD_ALL) || defined(DOXYGEN) -void -ComparatorConfigure(unsigned long ulBase, unsigned long ulComp, - unsigned long ulConfig) -{ - // - // Check the arguments. - // - ASSERT(ulBase == COMP_BASE); - ASSERT(ulComp < 3); - - // - // Configure this comparator. - // - HWREG(ulBase + (ulComp * 0x20) + COMP_O_ACCTL0) = ulConfig; -} -#endif - -//***************************************************************************** -// -//! Sets the internal reference voltage. -//! -//! \param ulBase is the base address of the comparator module. -//! \param ulRef is the desired reference voltage. -//! -//! This function will set the internal reference voltage value. The voltage -//! is specified as one of the following values: -//! -//! - \b COMP_REF_OFF to turn off the reference voltage -//! - \b COMP_REF_0V to set the reference voltage to 0 V -//! - \b COMP_REF_0_1375V to set the reference voltage to 0.1375 V -//! - \b COMP_REF_0_275V to set the reference voltage to 0.275 V -//! - \b COMP_REF_0_4125V to set the reference voltage to 0.4125 V -//! - \b COMP_REF_0_55V to set the reference voltage to 0.55 V -//! - \b COMP_REF_0_6875V to set the reference voltage to 0.6875 V -//! - \b COMP_REF_0_825V to set the reference voltage to 0.825 V -//! - \b COMP_REF_0_928125V to set the reference voltage to 0.928125 V -//! - \b COMP_REF_0_9625V to set the reference voltage to 0.9625 V -//! - \b COMP_REF_1_03125V to set the reference voltage to 1.03125 V -//! - \b COMP_REF_1_134375V to set the reference voltage to 1.134375 V -//! - \b COMP_REF_1_1V to set the reference voltage to 1.1 V -//! - \b COMP_REF_1_2375V to set the reference voltage to 1.2375 V -//! - \b COMP_REF_1_340625V to set the reference voltage to 1.340625 V -//! - \b COMP_REF_1_375V to set the reference voltage to 1.375 V -//! - \b COMP_REF_1_44375V to set the reference voltage to 1.44375 V -//! - \b COMP_REF_1_5125V to set the reference voltage to 1.5125 V -//! - \b COMP_REF_1_546875V to set the reference voltage to 1.546875 V -//! - \b COMP_REF_1_65V to set the reference voltage to 1.65 V -//! - \b COMP_REF_1_753125V to set the reference voltage to 1.753125 V -//! - \b COMP_REF_1_7875V to set the reference voltage to 1.7875 V -//! - \b COMP_REF_1_85625V to set the reference voltage to 1.85625 V -//! - \b COMP_REF_1_925V to set the reference voltage to 1.925 V -//! - \b COMP_REF_1_959375V to set the reference voltage to 1.959375 V -//! - \b COMP_REF_2_0625V to set the reference voltage to 2.0625 V -//! - \b COMP_REF_2_165625V to set the reference voltage to 2.165625 V -//! - \b COMP_REF_2_26875V to set the reference voltage to 2.26875 V -//! - \b COMP_REF_2_371875V to set the reference voltage to 2.371875 V -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_refset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -ComparatorRefSet(unsigned long ulBase, unsigned long ulRef) -{ - // - // Check the arguments. - // - ASSERT(ulBase == COMP_BASE); - - // - // Set the voltage reference voltage as requested. - // - HWREG(ulBase + COMP_O_REFCTL) = ulRef; -} -#endif - -//***************************************************************************** -// -//! Gets the current comparator output value. -//! -//! \param ulBase is the base address of the comparator module. -//! \param ulComp is the index of the comparator. -//! -//! This function retrieves the current value of the comparator output. -//! -//! \return Returns \b true if the comparator output is high and \b false if -//! the comparator output is low. -// -//***************************************************************************** -#if defined(GROUP_valueget) || defined(BUILD_ALL) || defined(DOXYGEN) -tBoolean -ComparatorValueGet(unsigned long ulBase, unsigned long ulComp) -{ - // - // Check the arguments. - // - ASSERT(ulBase == COMP_BASE); - ASSERT(ulComp < 3); - - // - // Return the appropriate value based on the comparator's present output - // value. - // - if(HWREG(ulBase + (ulComp * 0x20) + COMP_O_ACSTAT0) & COMP_ACSTAT_OVAL) - { - return(true); - } - else - { - return(false); - } -} -#endif - -//***************************************************************************** -// -//! Registers an interrupt handler for the comparator interrupt. -//! -//! \param ulBase is the base address of the comparator module. -//! \param ulComp is the index of the comparator. -//! \param pfnHandler is a pointer to the function to be called when the -//! comparator interrupt occurs. -//! -//! This sets the handler to be called when the comparator interrupt occurs. -//! This will enable the interrupt in the interrupt controller; it is the -//! interrupt-handler's responsibility to clear the interrupt source via -//! ComparatorIntClear(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp, - void (*pfnHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT(ulBase == COMP_BASE); - ASSERT(ulComp < 3); - - // - // Register the interrupt handler, returning an error if an error occurs. - // - IntRegister(INT_COMP0 + ulComp, pfnHandler); - - // - // Enable the interrupt in the interrupt controller. - // - IntEnable(INT_COMP0 + ulComp); - - // - // Enable the comparator interrupt. - // - HWREG(ulBase + COMP_O_INTEN) |= 1 << ulComp; -} -#endif - -//***************************************************************************** -// -//! Unregisters an interrupt handler for a comparator interrupt. -//! -//! \param ulBase is the base address of the comparator module. -//! \param ulComp is the index of the comparator. -//! -//! This function will clear the handler to be called when a comparator -//! interrupt occurs. This will also mask off the interrupt in the interrupt -//! controller so that the interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -ComparatorIntUnregister(unsigned long ulBase, unsigned long ulComp) -{ - // - // Check the arguments. - // - ASSERT(ulBase == COMP_BASE); - ASSERT(ulComp < 3); - - // - // Disable the comparator interrupt. - // - HWREG(ulBase + COMP_O_INTEN) &= ~(1 << ulComp); - - // - // Disable the interrupt in the interrupt controller. - // - IntDisable(INT_COMP0 + ulComp); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_COMP0 + ulComp); -} -#endif - -//***************************************************************************** -// -//! Enables the comparator interrupt. -//! -//! \param ulBase is the base address of the comparator module. -//! \param ulComp is the index of the comparator. -//! -//! This function enables generation of an interrupt from the specified -//! comparator. Only comparators whose interrupts are enabled can be reflected -//! to the processor. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp) -{ - // - // Check the arguments. - // - ASSERT(ulBase == COMP_BASE); - ASSERT(ulComp < 3); - - // - // Enable the comparator interrupt. - // - HWREG(ulBase + COMP_O_INTEN) |= 1 << ulComp; -} -#endif - -//***************************************************************************** -// -//! Disables the comparator interrupt. -//! -//! \param ulBase is the base address of the comparator module. -//! \param ulComp is the index of the comparator. -//! -//! This function disables generation of an interrupt from the specified -//! comparator. Only comparators whose interrupts are enabled can be reflected -//! to the processor. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp) -{ - // - // Check the arguments. - // - ASSERT(ulBase == COMP_BASE); - ASSERT(ulComp < 3); - - // - // Disable the comparator interrupt. - // - HWREG(ulBase + COMP_O_INTEN) &= ~(1 << ulComp); -} -#endif - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \param ulBase is the base address of the comparator module. -//! \param ulComp is the index of the comparator. -//! \param bMasked is \b false if the raw interrupt status is required and -//! \b true if the masked interrupt status is required. -//! -//! This returns the interrupt status for the comparator. Either the raw or -//! the masked interrupt status can be returned. -//! -//! \return \b true if the interrupt is asserted and \b false if it is not -//! asserted. -// -//***************************************************************************** -#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) -tBoolean -ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp, - tBoolean bMasked) -{ - // - // Check the arguments. - // - ASSERT(ulBase == COMP_BASE); - ASSERT(ulComp < 3); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(((HWREG(ulBase + COMP_O_MIS) >> ulComp) & 1) ? true : false); - } - else - { - return(((HWREG(ulBase + COMP_O_RIS) >> ulComp) & 1) ? true : false); - } -} -#endif - -//***************************************************************************** -// -//! Clears a comparator interrupt. -//! -//! \param ulBase is the base address of the comparator module. -//! \param ulComp is the index of the comparator. -//! -//! The comparator interrupt is cleared, so that it no longer asserts. This -//! must be done in the interrupt handler to keep it from being called again -//! immediately upon exit. Note that for a level triggered interrupt, the -//! interrupt cannot be cleared until it stops asserting. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) -void -ComparatorIntClear(unsigned long ulBase, unsigned long ulComp) -{ - // - // Check the arguments. - // - ASSERT(ulBase == COMP_BASE); - ASSERT(ulComp < 3); - - // - // Clear the interrupt. - // - HWREG(ulBase + COMP_O_MIS) = 1 << ulComp; -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/comp.h b/Demo/CORTEX_LM3S811_GCC/hw_include/comp.h deleted file mode 100644 index 9349982c4..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/comp.h +++ /dev/null @@ -1,120 +0,0 @@ -//***************************************************************************** -// -// comp.h - Prototypes for the analog comparator driver. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __COMP_H__ -#define __COMP_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to ComparatorConfigure() as the ulConfig -// parameter. For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of -// the values may be selected and ORed together will values from the other -// groups. -// -//***************************************************************************** -#define COMP_TRIG_NONE 0x00000000 // No ADC trigger -#define COMP_TRIG_HIGH 0x00000880 // Trigger when high -#define COMP_TRIG_LOW 0x00000800 // Trigger when low -#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge -#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge -#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges -#define COMP_INT_HIGH 0x00000010 // Interrupt when high -#define COMP_INT_LOW 0x00000000 // Interrupt when low -#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge -#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge -#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges -#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin -#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin -#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference -#define COMP_OUTPUT_NONE 0x00000000 // No comparator output -#define COMP_OUTPUT_NORMAL 0x00000100 // Comparator output normal -#define COMP_OUTPUT_INVERT 0x00000102 // Comparator output inverted - -//***************************************************************************** -// -// Values that can be passed to ComparatorSetRef() as the ulRef parameter. -// -//***************************************************************************** -#define COMP_REF_OFF 0x00000000 // Turn off the internal reference -#define COMP_REF_0V 0x00000300 // Internal reference of 0V -#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V -#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V -#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V -#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V -#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V -#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V -#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V -#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V -#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V -#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V -#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V -#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V -#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V -#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V -#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V -#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V -#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V -#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V -#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V -#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V -#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V -#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V -#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V -#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V -#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V -#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V -#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp, - unsigned long ulConfig); -extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef); -extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp); -extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp, - void (*pfnHandler)(void)); -extern void ComparatorIntUnregister(unsigned long ulBase, - unsigned long ulComp); -extern void ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp); -extern void ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp); -extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp, - tBoolean bMasked); -extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp); - -#ifdef __cplusplus -} -#endif - -#endif // __COMP_H__ diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/cpu.h b/Demo/CORTEX_LM3S811_GCC/hw_include/cpu.h deleted file mode 100644 index 688c52223..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/cpu.h +++ /dev/null @@ -1,40 +0,0 @@ -//***************************************************************************** -// -// cpu.h - Prototypes for the CPU instruction wrapper functions. -// -// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __CPU_H__ -#define __CPU_H__ - -//***************************************************************************** -// -// Prototypes. -// -//***************************************************************************** -extern void CPUcpsid(void); -extern void CPUcpsie(void); -extern void CPUwfi(void); - -#endif // __CPU_H__ diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/debug.h b/Demo/CORTEX_LM3S811_GCC/hw_include/debug.h deleted file mode 100644 index e46e2a772..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/debug.h +++ /dev/null @@ -1,56 +0,0 @@ -//***************************************************************************** -// -// debug.h - Macros for assisting debug of the driver library. -// -// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __DEBUG_H__ -#define __DEBUG_H__ - -//***************************************************************************** -// -// Prototype for the function that is called when an invalid argument is passed -// to an API. This is only used when doing a DEBUG build. -// -//***************************************************************************** -extern void __error__(char *pcFilename, unsigned long ulLine); - -//***************************************************************************** -// -// The ASSERT macro, which does the actual assertion checking. Typically, this -// will be for procedure arguments. -// -//***************************************************************************** -#ifdef DEBUG -#define ASSERT(expr) { \ - if(!(expr)) \ - { \ - __error__(__FILE__, __LINE__); \ - } \ - } -#else -#define ASSERT(expr) -#endif - -#endif // __DEBUG_H__ diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/driverlib.r79 b/Demo/CORTEX_LM3S811_GCC/hw_include/driverlib.r79 deleted file mode 100644 index 074f82f12..000000000 Binary files a/Demo/CORTEX_LM3S811_GCC/hw_include/driverlib.r79 and /dev/null differ diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/flash.c b/Demo/CORTEX_LM3S811_GCC/hw_include/flash.c deleted file mode 100644 index ab7335f42..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/flash.c +++ /dev/null @@ -1,668 +0,0 @@ -//***************************************************************************** -// -// flash.c - Driver for programming the on-chip flash. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup flash_api -//! @{ -// -//***************************************************************************** - -#include "../hw_flash.h" -#include "../hw_ints.h" -#include "../hw_memmap.h" -#include "../hw_sysctl.h" -#include "../hw_types.h" -#include "debug.h" -#include "flash.h" -#include "interrupt.h" - -//***************************************************************************** -// -//! Gets the number of processor clocks per micro-second. -//! -//! This function returns the number of clocks per micro-second, as presently -//! known by the flash controller. -//! -//! \return Returns the number of processor clocks per micro-second. -// -//***************************************************************************** -#if defined(GROUP_usecget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -FlashUsecGet(void) -{ - // - // Return the number of clocks per micro-second. - // - return(HWREG(FLASH_USECRL) + 1); -} -#endif - -//***************************************************************************** -// -//! Sets the number of processor clocks per micro-second. -//! -//! \param ulClocks is the number of processor clocks per micro-second. -//! -//! This function is used to tell the flash controller the number of processor -//! clocks per micro-second. This value must be programmed correctly or the -//! flash most likely will not program correctly; it has no affect on reading -//! flash. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_usecset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -FlashUsecSet(unsigned long ulClocks) -{ - // - // Set the number of clocks per micro-second. - // - HWREG(FLASH_USECRL) = ulClocks - 1; -} -#endif - -//***************************************************************************** -// -//! Erases a block of flash. -//! -//! \param ulAddress is the start address of the flash block to be erased. -//! -//! This function will erase a 1 kB block of the on-chip flash. After erasing, -//! the block will be filled with 0xFF bytes. Read-only and execute-only -//! blocks cannot be erased. -//! -//! This function will not return until the block has been erased. -//! -//! \return Returns 0 on success, or -1 if an invalid block address was -//! specified or the block is write-protected. -// -//***************************************************************************** -#if defined(GROUP_erase) || defined(BUILD_ALL) || defined(DOXYGEN) -long -FlashErase(unsigned long ulAddress) -{ - // - // Check the arguments. - // - ASSERT(!(ulAddress & (FLASH_ERASE_SIZE - 1))); - - // - // Clear the flash access interrupt. - // - HWREG(FLASH_FCMISC) = FLASH_FCMISC_ACCESS; - - // - // Erase the block. - // - HWREG(FLASH_FMA) = ulAddress; - HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_ERASE; - - // - // Wait until the word has been programmed. - // - while(HWREG(FLASH_FMC) & FLASH_FMC_ERASE) - { - } - - // - // Return an error if an access violation occurred. - // - if(HWREG(FLASH_FCRIS) & FLASH_FCRIS_ACCESS) - { - return(-1); - } - - // - // Success. - // - return(0); -} -#endif - -//***************************************************************************** -// -//! Programs flash. -//! -//! \param pulData is a pointer to the data to be programmed. -//! \param ulAddress is the starting address in flash to be programmed. Must -//! be a multiple of four. -//! \param ulCount is the number of bytes to be programmed. Must be a multiple -//! of four. -//! -//! This function will program a sequence of words into the on-chip flash. -//! Programming each location consists of the result of an AND operation -//! of the new data and the existing data; in other words bits that contain -//! 1 can remain 1 or be changed to 0, but bits that are 0 cannot be changed -//! to 1. Therefore, a word can be programmed multiple times as long as these -//! rules are followed; if a program operation attempts to change a 0 bit to -//! a 1 bit, that bit will not have its value changed. -//! -//! Since the flash is programmed one word at a time, the starting address and -//! byte count must both be multiples of four. It is up to the caller to -//! verify the programmed contents, if such verification is required. -//! -//! This function will not return until the data has been programmed. -//! -//! \return Returns 0 on success, or -1 if a programming error is encountered. -// -//***************************************************************************** -#if defined(GROUP_program) || defined(BUILD_ALL) || defined(DOXYGEN) -long -FlashProgram(unsigned long *pulData, unsigned long ulAddress, - unsigned long ulCount) -{ - // - // Check the arguments. - // - ASSERT(!(ulAddress & 3)); - ASSERT(!(ulCount & 3)); - - // - // Clear the flash access interrupt. - // - HWREG(FLASH_FCMISC) = FLASH_FCMISC_ACCESS; - - // - // Loop over the words to be programmed. - // - while(ulCount) - { - // - // Program the next word. - // - HWREG(FLASH_FMA) = ulAddress; - HWREG(FLASH_FMD) = *pulData; - HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_WRITE; - - // - // Wait until the word has been programmed. - // - while(HWREG(FLASH_FMC) & FLASH_FMC_WRITE) - { - } - - // - // Increment to the next word. - // - pulData++; - ulAddress += 4; - ulCount -= 4; - } - - // - // Return an error if an access violation occurred. - // - if(HWREG(FLASH_FCRIS) & FLASH_FCRIS_ACCESS) - { - return(-1); - } - - // - // Success. - // - return(0); -} -#endif - -//***************************************************************************** -// -//! Gets the protection setting for a block of flash. -//! -//! \param ulAddress is the start address of the flash block to be queried. -//! -//! This function will get the current protection for the specified 2 kB block -//! of flash. Each block can be read/write, read-only, or execute-only. -//! Read/write blocks can be read, executed, erased, and programmed. Read-only -//! blocks can be read and executed. Execute-only blocks can only be executed; -//! processor and debugger data reads are not allowed. -//! -//! \return Returns the protection setting for this block. See -//! FlashProtectSet() for possible values. -// -//***************************************************************************** -#if defined(GROUP_protectget) || defined(BUILD_ALL) || defined(DOXYGEN) -tFlashProtection -FlashProtectGet(unsigned long ulAddress) -{ - unsigned long ulFMPRE, ulFMPPE; - - // - // Check the argument. - // - ASSERT(!(ulAddress & (FLASH_PROTECT_SIZE - 1))); - - // - // Read the flash protection register and get the bits that apply to the - // specified block. - // - ulFMPRE = HWREG(FLASH_FMPRE); - ulFMPPE = HWREG(FLASH_FMPPE); - switch((((ulFMPRE >> (ulAddress / FLASH_PROTECT_SIZE)) & - FLASH_FMP_BLOCK_0) << 1) | - ((ulFMPPE >> (ulAddress / FLASH_PROTECT_SIZE)) & FLASH_FMP_BLOCK_0)) - { - // - // This block is marked as execute only (i.e. it can not be erased or - // programmed, and the only reads allowed are via the instruction fecth - // interface). - // - case 0: - case 1: - { - return(FlashExecuteOnly); - } - - // - // This block is marked as read only (i.e. it can not be erased or - // programmed). - // - case 2: - { - return(FlashReadOnly); - } - - // - // This block is read/write; it can be read, erased, and programmed. - // - case 3: - default: - { - return(FlashReadWrite); - } - } -} -#endif - -//***************************************************************************** -// -//! Sets the protection setting for a block of flash. -//! -//! \param ulAddress is the start address of the flash block to be protected. -//! \param eProtect is the protection to be applied to the block. Can be one -//! of \b FlashReadWrite, \b FlashReadOnly, or \b FlashExecuteOnly. -//! -//! This function will set the protection for the specified 2 kB block of -//! flash. Blocks which are read/write can be made read-only or execute-only. -//! Blocks which are read-only can be made execute-only. Blocks which are -//! execute-only cannot have their protection modified. Attempts to make the -//! block protection less stringent (i.e. read-only to read/write) will result -//! in a failure (and be prevented by the hardware). -//! -//! Changes to the flash protection are maintained only until the next reset. -//! This allows the application to be executed in the desired flash protection -//! environment to check for inappropriate flash access (via the flash -//! interrupt). To make the flash protection permanent, use the -//! FlashProtectSave() function. -//! -//! \return Returns 0 on success, or -1 if an invalid address or an invalid -//! protection was specified. -// -//***************************************************************************** -#if defined(GROUP_protectset) || defined(BUILD_ALL) || defined(DOXYGEN) -long -FlashProtectSet(unsigned long ulAddress, tFlashProtection eProtect) -{ - unsigned long ulProtectRE, ulProtectPE; - - // - // Check the argument. - // - ASSERT(!(ulAddress & (FLASH_PROTECT_SIZE - 1))); - ASSERT((eProtect == FlashReadWrite) || (eProtect == FlashReadOnly) || - (eProtect == FlashExecuteOnly)); - - // - // Convert the address into a block number. - // - ulAddress /= FLASH_PROTECT_SIZE; - - // - // Get the current protection. - // - ulProtectRE = HWREG(FLASH_FMPRE); - ulProtectPE = HWREG(FLASH_FMPPE); - - // - // Set the protection based on the requested proection. - // - switch(eProtect) - { - // - // Make this block execute only. - // - case FlashExecuteOnly: - { - // - // Turn off the read and program bits for this block. - // - ulProtectRE &= ~(FLASH_FMP_BLOCK_0 << ulAddress); - ulProtectPE &= ~(FLASH_FMP_BLOCK_0 << ulAddress); - - // - // We're done handling this protection. - // - break; - } - - // - // Make this block read only. - // - case FlashReadOnly: - { - // - // The block can not be made read only if it is execute only. - // - if(((ulProtectRE >> ulAddress) & FLASH_FMP_BLOCK_0) != - FLASH_FMP_BLOCK_0) - { - return(-1); - } - - // - // Make this block read only. - // - ulProtectPE &= ~(FLASH_FMP_BLOCK_0 << ulAddress); - - // - // We're done handling this protection. - // - break; - } - - // - // Make this block read/write. - // - case FlashReadWrite: - default: - { - // - // The block can not be made read/write if it is not already - // read/write. - // - if((((ulProtectRE >> ulAddress) & FLASH_FMP_BLOCK_0) != - FLASH_FMP_BLOCK_0) || - (((ulProtectPE >> ulAddress) & FLASH_FMP_BLOCK_0) != - FLASH_FMP_BLOCK_0)) - { - return(-1); - } - - // - // The block is already read/write, so there is nothing to do. - // - return(0); - } - } - - // - // Set the new protection. - // - HWREG(FLASH_FMPRE) = ulProtectRE; - HWREG(FLASH_FMPPE) = ulProtectPE; - - // - // Success. - // - return(0); -} -#endif - -//***************************************************************************** -// -//! Saves the flash protection settings. -//! -//! This function will make the currently programmed flash protection settings -//! permanent. This is a non-reversible operation; a chip reset or power cycle -//! will not change the flash protection. -//! -//! This function will not return until the protection has been saved. -//! -//! \return Returns 0 on success, or -1 if a hardware error is encountered. -// -//***************************************************************************** -#if defined(GROUP_protectsave) || defined(BUILD_ALL) || defined(DOXYGEN) -long -FlashProtectSave(void) -{ - // - // Tell the flash controller to write the flash read protection register. - // - HWREG(FLASH_FMA) = 0; - HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT; - - // - // Wait until the write has completed. - // - while(HWREG(FLASH_FMC) & FLASH_FMC_COMT) - { - } - - // - // Tell the flash controller to write the flash program protection - // register. - // - HWREG(FLASH_FMA) = 1; - HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT; - - // - // Wait until the write has completed. - // - while(HWREG(FLASH_FMC) & FLASH_FMC_COMT) - { - } - - // - // Success. - // - return(0); -} -#endif - -//***************************************************************************** -// -//! Registers an interrupt handler for the flash interrupt. -//! -//! \param pfnHandler is a pointer to the function to be called when the flash -//! interrupt occurs. -//! -//! This sets the handler to be called when the flash interrupt occurs. The -//! flash controller can generate an interrupt when an invalid flash access -//! occurs, such as trying to program or erase a read-only block, or trying to -//! read from an execute-only block. It can also generate an interrupt when a -//! program or erase operation has completed. The interrupt will be -//! automatically enabled when the handler is registered. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -FlashIntRegister(void (*pfnHandler)(void)) -{ - // - // Register the interrupt handler, returning an error if an error occurs. - // - IntRegister(INT_FLASH, pfnHandler); - - // - // Enable the flash interrupt. - // - IntEnable(INT_FLASH); -} -#endif - -//***************************************************************************** -// -//! Unregisters the interrupt handler for the flash interrupt. -//! -//! This function will clear the handler to be called when the flash interrupt -//! occurs. This will also mask off the interrupt in the interrupt controller -//! so that the interrupt handler is no longer called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -FlashIntUnregister(void) -{ - // - // Disable the interrupt. - // - IntDisable(INT_FLASH); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_FLASH); -} -#endif - -//***************************************************************************** -// -//! Enables individual flash controller interrupt sources. -//! -//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. -//! Can be any of the \b FLASH_FCIM_PROGRAM or \b FLASH_FCIM_ACCESS values. -//! -//! Enables the indicated flash controller interrupt sources. Only the sources -//! that are enabled can be reflected to the processor interrupt; disabled -//! sources have no effect on the processor. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -FlashIntEnable(unsigned long ulIntFlags) -{ - // - // Enable the specified interrupts. - // - HWREG(FLASH_FCIM) |= ulIntFlags; -} -#endif - -//***************************************************************************** -// -//! Disables individual flash controller interrupt sources. -//! -//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. -//! Can be any of the \b FLASH_FCIM_PROGRAM or \b FLASH_FCIM_ACCESS values. -//! -//! Disables the indicated flash controller interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -FlashIntDisable(unsigned long ulIntFlags) -{ - // - // Disable the specified interrupts. - // - HWREG(FLASH_FCIM) &= ~(ulIntFlags); -} -#endif - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \param bMasked is false if the raw interrupt status is required and true if -//! the masked interrupt status is required. -//! -//! This returns the interrupt status for the flash controller. Either the raw -//! interrupt status or the status of interrupts that are allowed to reflect to -//! the processor can be returned. -//! -//! \return The current interrupt status, enumerated as a bit field of -//! \b FLASH_FCMISC_PROGRAM and \b FLASH_FCMISC_ACCESS. -// -//***************************************************************************** -#if defined(GROUP_intgetstatus) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -FlashIntGetStatus(tBoolean bMasked) -{ - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(FLASH_FCMISC)); - } - else - { - return(HWREG(FLASH_FCRIS)); - } -} -#endif - -//***************************************************************************** -// -//! Clears flash controller interrupt sources. -//! -//! \param ulIntFlags is the bit mask of the interrupt sources to be cleared. -//! Can be any of the \b FLASH_FCMISC_PROGRAM or \b FLASH_FCMISC_ACCESS -//! values. -//! -//! The specified flash controller interrupt sources are cleared, so that they -//! no longer assert. This must be done in the interrupt handler to keep it -//! from being called again immediately upon exit. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) -void -FlashIntClear(unsigned long ulIntFlags) -{ - // - // Clear the flash interrupt. - // - HWREG(FLASH_FCMISC) = ulIntFlags; -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/flash.h b/Demo/CORTEX_LM3S811_GCC/hw_include/flash.h deleted file mode 100644 index 9c41dda4f..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/flash.h +++ /dev/null @@ -1,75 +0,0 @@ -//***************************************************************************** -// -// flash.h - Prototypes for the flash driver. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __FLASH_H__ -#define __FLASH_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to FlashProtectSet(), and returned by -// FlashProtectGet(). -// -//***************************************************************************** -typedef enum -{ - FlashReadWrite, // Flash can be read and written - FlashReadOnly, // Flash can only be read - FlashExecuteOnly // Flash can only be executed -} -tFlashProtection; - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern unsigned long FlashUsecGet(void); -extern void FlashUsecSet(unsigned long ulClocks); -extern long FlashErase(unsigned long ulAddress); -extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress, - unsigned long ulCount); -extern tFlashProtection FlashProtectGet(unsigned long ulAddress); -extern long FlashProtectSet(unsigned long ulAddress, - tFlashProtection eProtect); -extern long FlashProtectSave(void); -extern void FlashIntRegister(void (*pfnHandler)(void)); -extern void FlashIntUnregister(void); -extern void FlashIntEnable(unsigned long ulIntFlags); -extern void FlashIntDisable(unsigned long ulIntFlags); -extern unsigned long FlashIntGetStatus(tBoolean bMasked); -extern void FlashIntClear(unsigned long ulIntFlags); - -#ifdef __cplusplus -} -#endif - -#endif // __FLASH_H__ diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/gpio.c b/Demo/CORTEX_LM3S811_GCC/hw_include/gpio.c deleted file mode 100644 index a49602e9b..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/gpio.c +++ /dev/null @@ -1,1103 +0,0 @@ -//***************************************************************************** -// -// gpio.c - API for GPIO ports -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup gpio_api -//! @{ -// -//***************************************************************************** - -#include "../hw_gpio.h" -#include "../hw_ints.h" -#include "../hw_memmap.h" -#include "../hw_types.h" -#include "debug.h" -#include "gpio.h" -#include "interrupt.h" - -//***************************************************************************** -// -//! \internal -//! Get GPIO interrupt number. -//! -//! \param ulPort base address of the selected GPIO port -//! -//! Given a GPIO base address, returns the corresponding interrupt number. -//! -//! \return Returns a GPIO interrupt number, or -1 if \e ulPort is invalid. -// -//***************************************************************************** -#if defined(GROUP_getintnumber) || defined(BUILD_ALL) -long -GPIOGetIntNumber(unsigned long ulPort) -{ - unsigned int ulInt; - - // - // Determine the GPIO interrupt number for the given module. - // - switch(ulPort) - { - case GPIO_PORTA_BASE: - { - ulInt = INT_GPIOA; - break; - } - - case GPIO_PORTB_BASE: - { - ulInt = INT_GPIOB; - break; - } - - case GPIO_PORTC_BASE: - { - ulInt = INT_GPIOC; - break; - } - - case GPIO_PORTD_BASE: - { - ulInt = INT_GPIOD; - break; - } - - case GPIO_PORTE_BASE: - { - ulInt = INT_GPIOE; - break; - } - - default: - { - return(-1); - } - } - - // - // Return GPIO interrupt number. - // - return(ulInt); -} -#else -extern long GPIOGetIntNumber(unsigned long ulPort); -#endif - -//***************************************************************************** -// -//! Sets the direction and mode of the specified pins of the selected -//! GPIO port. -//! -//! \param ulPort base address of the selected GPIO port -//! \param ucPins bit-packed representation of the specified pins -//! \param ulPinIO pin direction and/or mode -//! -//! This function will set the specified pins on the selected GPIO port -//! as either an input or output under software control, or it will set the -//! pin to be under hardware control. -//! -//! The parameter \e ulPinIO is an enumerated data type that can be one of -//! the following values: -//! -//! - \b GPIO_DIR_MODE_IN -//! - \b GPIO_DIR_MODE_OUT -//! - \b GPIO_DIR_MODE_HW -//! -//! where \b GPIO_DIR_MODE_IN specifies that the pin will be programmed as -//! a software controlled input, \b GPIO_DIR_MODE_OUT specifies that the pin -//! will be programmed as a software controlled output, and -//! \b GPIO_DIR_MODE_HW specifies that the pin will be placed under -//! hardware control. -//! -//! The pins are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_dirmodeset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulPinIO) -{ - // - // Check the arguments. - // - ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || - (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || - (ulPort == GPIO_PORTE_BASE)); - ASSERT((ulPinIO == GPIO_DIR_MODE_IN) || (ulPinIO == GPIO_DIR_MODE_OUT) || - (ulPinIO == GPIO_DIR_MODE_HW)); - - // - // Set the pin direction and mode. - // - HWREG(ulPort + GPIO_O_DIR) = ((ulPinIO & 1) ? - (HWREG(ulPort + GPIO_O_DIR) | ucPins) : - (HWREG(ulPort + GPIO_O_DIR) & ~(ucPins))); - HWREG(ulPort + GPIO_O_AFSEL) = ((ulPinIO & 2) ? - (HWREG(ulPort + GPIO_O_AFSEL) | ucPins) : - (HWREG(ulPort + GPIO_O_AFSEL) & - ~(ucPins))); -} -#endif - -//***************************************************************************** -// -//! Gets the direction and mode of a specified pin of the selected -//! GPIO port. -//! -//! \param ulPort base address of the selected GPIO port -//! \param ucPin pin number of the specified pin, relative to the selected -//! GPIO port. -//! -//! This function gets the direction and control mode for a specified pin on -//! the selected GPIO port. The pin can be configured as either an input or -//! output under software control, or it can be under hardware control. The -//! type of control and direction are returned as an enumerated data type. -//! -//! \return Returns one of the enumerated data types described for -//! GPIODirModeSet(). -// -//***************************************************************************** -#if defined(GROUP_dirmodeget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -GPIODirModeGet(unsigned long ulPort, unsigned char ucPin) -{ - unsigned long ulDir, ulAFSEL; - - // - // Check the arguments. - // - ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || - (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || - (ulPort == GPIO_PORTE_BASE)); - ASSERT(ucPin < 8); - - // - // Convert from a pin number to a bit position. - // - ucPin = 1 << ucPin; - - // - // Return the pin direction and mode. - // - ulDir = HWREG(ulPort + GPIO_O_DIR); - ulAFSEL = HWREG(ulPort + GPIO_O_AFSEL); - return(((ulDir & ucPin) ? 1 : 0) | ((ulAFSEL & ucPin) ? 2 : 0)); -} -#endif - -//***************************************************************************** -// -//! Sets the interrupt type for the specified pins of the selected GPIO -//! port. -//! -//! \param ulPort base address of the selected GPIO port -//! \param ucPins bit-packed representation of the specified pins -//! \param ulIntType specifies the type of interrupt trigger mechanism -//! -//! This function sets up the various interrupt trigger mechanisms for the -//! specified pins on the selected GPIO port. -//! -//! The parameter \e ulIntType is an enumerated data type that can be one of -//! the following values: -//! -//! - \b GPIO_FALLING_EDGE -//! - \b GPIO_RISING_EDGE -//! - \b GPIO_BOTH_EDGES -//! - \b GPIO_LOW_LEVEL -//! - \b GPIO_HIGH_LEVEL -//! -//! where the different values describe the interrupt detection mechanism -//! (edge or level) and the particular triggering event (falling, rising, -//! or both edges for edge detect, low or high for level detect). -//! -//! The pins are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. -//! -//! \note In order to avoid any spurious interrupts, the user must -//! ensure that the GPIO inputs remain stable for the duration of -//! this function. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_inttypeset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulIntType) -{ - // - // Check the arguments. - // - ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || - (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || - (ulPort == GPIO_PORTE_BASE)); - ASSERT((ulIntType == GPIO_FALLING_EDGE) || - (ulIntType == GPIO_RISING_EDGE) || - (ulIntType == GPIO_BOTH_EDGES) || - (ulIntType == GPIO_LOW_LEVEL) || - (ulIntType == GPIO_HIGH_LEVEL)); - - // - // Set the pin interrupt type. - // - HWREG(ulPort + GPIO_O_IBE) = ((ulIntType & 1) ? - (HWREG(ulPort + GPIO_O_IBE) | ucPins) : - (HWREG(ulPort + GPIO_O_IBE) & ~(ucPins))); - HWREG(ulPort + GPIO_O_IS) = ((ulIntType & 2) ? - (HWREG(ulPort + GPIO_O_IS) | ucPins) : - (HWREG(ulPort + GPIO_O_IS) & ~(ucPins))); - HWREG(ulPort + GPIO_O_IEV) = ((ulIntType & 4) ? - (HWREG(ulPort + GPIO_O_IEV) | ucPins) : - (HWREG(ulPort + GPIO_O_IEV) & ~(ucPins))); -} -#endif - -//***************************************************************************** -// -//! Gets the interrupt type for the specified pin of the selected GPIO -//! port. -//! -//! \param ulPort base address of the selected GPIO port -//! \param ucPin pin number of the specified pin, relative to the selected -//! GPIO port. -//! -//! This function gets the interrupt type for a specified pin on the selected -//! GPIO port. The pin can be configured as a falling edge, rising edge, or -//! both edge detected interrupt, or it can be configured as a low level or -//! high level detected interrupt. The type of interrupt detection mechanism -//! is returned as an enumerated data type. -//! -//! \return Returns one of the enumerated data types described for -//! GPIOIntTypeSet(). -// -//***************************************************************************** -#if defined(GROUP_inttypeget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin) -{ - unsigned long ulIBE, ulIS, ulIEV; - - // - // Check the arguments. - // - ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || - (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || - (ulPort == GPIO_PORTE_BASE)); - ASSERT(ucPin < 8); - - // - // Convert from a pin number to a bit position. - // - ucPin = 1 << ucPin; - - // - // Return the pin interrupt type. - // - ulIBE = HWREG(ulPort + GPIO_O_IBE); - ulIS = HWREG(ulPort + GPIO_O_IS); - ulIEV = HWREG(ulPort + GPIO_O_IEV); - return(((ulIBE & ucPin) ? 1 : 0) | ((ulIS & ucPin) ? 2 : 0) | - ((ulIEV & ucPin) ? 4 : 0)); -} -#endif - -//***************************************************************************** -// -//! Sets the pad configuration for the specified pins of the selected GPIO -//! port. -//! -//! \param ulPort is the base address of the GPIO port. -//! \param ucPins bit-packed representation of the specified pins. -//! \param ulStrength specifies the output drive strength. -//! \param ulPinType specifies the pin type. -//! -//! This function sets the drive strength and type for the specified pins -//! on the selected GPIO port. For pins configured as input ports, the -//! pad is configured as requested, but the only real effect on the input -//! is the configuration of the pull-up or pull-down termination. -//! -//! The parameter \e ulStrength can be one of the following values: -//! -//! - \b GPIO_STRENGTH_2MA -//! - \b GPIO_STRENGTH_4MA -//! - \b GPIO_STRENGTH_8MA -//! - \b GPIO_STRENGTH_8MA_SC -//! -//! where \b GPIO_STRENGTH_xMA specifies either 2, 4, or 8 mA output drive -//! strength, and \b GPIO_OUT_STRENGTH_8MA_SC specifies 8 mA output drive with -//! slew control. -//! -//! The parameter \e ulPinType can be one of the following values: -//! -//! - \b GPIO_PIN_TYPE_STD -//! - \b GPIO_PIN_TYPE_STD_WPU -//! - \b GPIO_PIN_TYPE_STD_WPD -//! - \b GPIO_PIN_TYPE_OD -//! - \b GPIO_PIN_TYPE_OD_WPU -//! - \b GPIO_PIN_TYPE_OD_WPD -//! - \b GPIO_PIN_TYPE_ANALOG -//! -//! where \b GPIO_PIN_TYPE_STD* specifies a push-pull pin, \b GPIO_PIN_TYPE_OD* -//! specifies an open-drain pin, \b *_WPU specifies a weak pull-up, \b *_WPD -//! specifies a weak pull-down, and \b GPIO_PIN_TYPE_ANALOG specifies an -//! analog input (for the comparators). -//! -//! The pins are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_padconfigset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulStrength, unsigned long ulPinType) -{ - // - // Check the arguments. - // - ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || - (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || - (ulPort == GPIO_PORTE_BASE)); - ASSERT((ulStrength == GPIO_STRENGTH_2MA) || - (ulStrength == GPIO_STRENGTH_4MA) || - (ulStrength == GPIO_STRENGTH_8MA) || - (ulStrength == GPIO_STRENGTH_8MA_SC)); - ASSERT((ulPinType == GPIO_PIN_TYPE_STD) || - (ulPinType == GPIO_PIN_TYPE_STD_WPU) || - (ulPinType == GPIO_PIN_TYPE_STD_WPD) || - (ulPinType == GPIO_PIN_TYPE_OD) || - (ulPinType == GPIO_PIN_TYPE_OD_WPU) || - (ulPinType == GPIO_PIN_TYPE_OD_WPD) || - (ulPinType == GPIO_PIN_TYPE_ANALOG)) - - // - // Set the output drive strength. - // - HWREG(ulPort + GPIO_O_DR2R) = ((ulStrength & 1) ? - (HWREG(ulPort + GPIO_O_DR2R) | ucPins) : - (HWREG(ulPort + GPIO_O_DR2R) & ~(ucPins))); - HWREG(ulPort + GPIO_O_DR4R) = ((ulStrength & 2) ? - (HWREG(ulPort + GPIO_O_DR4R) | ucPins) : - (HWREG(ulPort + GPIO_O_DR4R) & ~(ucPins))); - HWREG(ulPort + GPIO_O_DR8R) = ((ulStrength & 4) ? - (HWREG(ulPort + GPIO_O_DR8R) | ucPins) : - (HWREG(ulPort + GPIO_O_DR8R) & ~(ucPins))); - HWREG(ulPort + GPIO_O_SLR) = ((ulStrength & 8) ? - (HWREG(ulPort + GPIO_O_SLR) | ucPins) : - (HWREG(ulPort + GPIO_O_SLR) & ~(ucPins))); - - // - // Set the pin type. - // - HWREG(ulPort + GPIO_O_ODR) = ((ulPinType & 1) ? - (HWREG(ulPort + GPIO_O_ODR) | ucPins) : - (HWREG(ulPort + GPIO_O_ODR) & ~(ucPins))); - HWREG(ulPort + GPIO_O_PUR) = ((ulPinType & 2) ? - (HWREG(ulPort + GPIO_O_PUR) | ucPins) : - (HWREG(ulPort + GPIO_O_PUR) & ~(ucPins))); - HWREG(ulPort + GPIO_O_PDR) = ((ulPinType & 4) ? - (HWREG(ulPort + GPIO_O_PDR) | ucPins) : - (HWREG(ulPort + GPIO_O_PDR) & ~(ucPins))); - HWREG(ulPort + GPIO_O_DEN) = ((ulPinType & 8) ? - (HWREG(ulPort + GPIO_O_DEN) | ucPins) : - (HWREG(ulPort + GPIO_O_DEN) & ~(ucPins))); -} -#endif - -//***************************************************************************** -// -//! Gets the pad configuration for the specified pin of the selected GPIO -//! port. -//! -//! \param ulPort base address of the selected GPIO port -//! \param ucPin pin number of the specified pin, relative to the selected -//! GPIO port. -//! \param pulStrength pointer to storage for the output drive strength -//! \param pulPinType pointer to storage for the output drive type -//! -//! This function gets the pad configuration for a specified pin on the -//! selected GPIO port. The values returned in \e eStrength and \e eOutType -//! correspond to the values used in GPIOPadConfigSet(). This function also -//! works for pins configured as input pins; however, the only meaningful -//! data returned is whether the pin is terminated with a pull-up or -//! down resistor. -//! -//! \return None -// -//***************************************************************************** -#if defined(GROUP_padconfigget) || defined(BUILD_ALL) || defined(DOXYGEN) -void -GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin, - unsigned long *pulStrength, unsigned long *pulPinType) -{ - unsigned long ulTemp1, ulTemp2, ulTemp3, ulTemp4; - - // - // Check the arguments. - // - ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || - (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || - (ulPort == GPIO_PORTE_BASE)); - ASSERT(ucPin < 8); - - // - // Convert from a pin number to a bit position. - // - ucPin = (1 << ucPin); - - // - // Get the drive strength for this pin. - // - ulTemp1 = HWREG(ulPort + GPIO_O_DR2R); - ulTemp2 = HWREG(ulPort + GPIO_O_DR4R); - ulTemp3 = HWREG(ulPort + GPIO_O_DR8R); - ulTemp4 = HWREG(ulPort + GPIO_O_SLR); - *pulStrength = (((ulTemp1 & ucPin) ? 1 : 0) | ((ulTemp2 & ucPin) ? 2 : 0) | - ((ulTemp3 & ucPin) ? 4 : 0) | ((ulTemp4 & ucPin) ? 8 : 0)); - - // - // Get the pin type. - // - ulTemp1 = HWREG(ulPort + GPIO_O_ODR); - ulTemp2 = HWREG(ulPort + GPIO_O_PUR); - ulTemp3 = HWREG(ulPort + GPIO_O_PDR); - ulTemp4 = HWREG(ulPort + GPIO_O_DEN); - *pulPinType = (((ulTemp1 & ucPin) ? 1 : 0) | ((ulTemp2 & ucPin) ? 2 : 0) | - ((ulTemp3 & ucPin) ? 4 : 0) | ((ulTemp4 & ucPin) ? 8 : 0)); -} -#endif - -//***************************************************************************** -// -//! Enables interrupts for the specified pins of the selected GPIO port. -//! -//! \param ulPort base address of the selected GPIO port -//! \param ucPins bit-packed representation of the specified pins -//! -//! Unmasks the interrupt for the specified pins. -//! -//! The pins are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_pinintenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins) -{ - // - // Check the arguments. - // - ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || - (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || - (ulPort == GPIO_PORTE_BASE)); - - // - // Enable the interrupts. - // - HWREG(ulPort + GPIO_O_IM) |= ucPins; -} -#endif - -//***************************************************************************** -// -//! Disables interrupts for the specified pins of the selected GPIO port. -//! -//! \param ulPort base address of the selected GPIO port -//! \param ucPins bit-packed representation of the specified pins -//! -//! Masks the interrupt for the specified pins. -//! -//! The pins are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_pinintdisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins) -{ - // - // Check the arguments. - // - ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || - (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || - (ulPort == GPIO_PORTE_BASE)); - - // - // Disable the interrupts. - // - HWREG(ulPort + GPIO_O_IM) &= ~(ucPins); -} -#endif - -//***************************************************************************** -// -//! Gets interrupt status for all the pins of the selected GPIO port. -//! -//! \param ulPort base address of the selected GPIO port -//! \param bMasked specifies whether masked or raw interrupt -//! status is returned -//! -//! If \e bMasked is set as \b true, then the masked interrupt status is -//! returned; otherwise, the raw interrupt status will be returned. -//! -//! \return Returns a bit-packed byte, where each bit that is set identifies -//! an active masked or raw interrupt, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. Bits -//! 31:8 should be ignored. -// -//***************************************************************************** -#if defined(GROUP_pinintstatus) || defined(BUILD_ALL) || defined(DOXYGEN) -long -GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked) -{ - // - // Check the arguments. - // - ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || - (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || - (ulPort == GPIO_PORTE_BASE)); - - // - // Return the interrupt status. - // - if(bMasked) - { - return(HWREG(ulPort + GPIO_O_MIS)); - } - else - { - return(HWREG(ulPort + GPIO_O_RIS)); - } -} -#endif - -//***************************************************************************** -// -//! Clears the interrupt for the specified pins of the selected GPIO port. -//! -//! \param ulPort base address of the selected GPIO port -//! \param ucPins bit-packed representation of the specified pins -//! -//! Clears the interrupt for the specified pins. -//! -//! The pins are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_pinintclear) || defined(BUILD_ALL) || defined(DOXYGEN) -void -GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins) -{ - // - // Check the arguments. - // - ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || - (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || - (ulPort == GPIO_PORTE_BASE)); - - // - // Clear the interrupts. - // - HWREG(ulPort + GPIO_O_ICR) = ucPins; -} -#endif - -//***************************************************************************** -// -//! Registers an interrupt handler for the selected GPIO port. -//! -//! \param ulPort base address of the selected GPIO port -//! \param pfIntHandler pointer to the GPIO port interrupt handling function -//! -//! This function will ensure that the interrupt handler specified by \e -//! pfIntHandler is called when an interrupt is detected from the selected -//! GPIO port. This function will also enable the corresponding GPIO -//! interrupt in the interrupt controller; individual pin interrupts and -//! interrupt sources must be enabled with GPIOPinIntEnable(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_portintregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -GPIOPortIntRegister(unsigned long ulPort, void (*pfIntHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || - (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || - (ulPort == GPIO_PORTE_BASE)); - - // - // Get the interrupt number associated with the specified GPIO. - // - ulPort = GPIOGetIntNumber(ulPort); - - // - // Register the interrupt handler. - // - IntRegister(ulPort, pfIntHandler); - - // - // Enable the GPIO interrupt. - // - IntEnable(ulPort); -} -#endif - -//***************************************************************************** -// -//! Removes an interrupt handler for the selected GPIO port. -//! -//! \param ulPort base address of the selected GPIO port -//! -//! This function will unregister the interrupt handler for the specified -//! GPIO port. This function will also disable the corresponding -//! GPIO port interrupt in the interrupt controller; individual GPIO interrupts -//! and interrupt sources must be disabled with GPIOPinIntDisable(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_portintunregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -GPIOPortIntUnregister(unsigned long ulPort) -{ - // - // Check the arguments. - // - ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || - (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || - (ulPort == GPIO_PORTE_BASE)); - - // - // Get the interrupt number associated with the specified GPIO. - // - ulPort = GPIOGetIntNumber(ulPort); - - // - // Disable the GPIO interrupt. - // - IntDisable(ulPort); - - // - // Unregister the interrupt handler. - // - IntUnregister(ulPort); -} -#endif - -//***************************************************************************** -// -//! Reads the values present at the specified pins of the selected GPIO port. -//! -//! \param ulPort base address of the selected GPIO port -//! \param ucPins bit-packed representation of the specified pins -//! -//! The values at the specified pins are read, as specified by \e ucPins. -//! Values are returned for both input and output pins, and the value -//! for pins that are not specified by \e ucPins are set to 0. -//! -//! The pins are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. -//! -//! \return Returns a bit-packed byte providing the state of the specified -//! pin, where bit 0 of the byte represents GPIO port pin 0, bit 1 represents -//! GPIO port pin 1, etc. Any bit that is not specified by \e ucPins -//! is returned as a 0. Bits 31:8 should be ignored. -// -//***************************************************************************** -#if defined(GROUP_pinread) || defined(BUILD_ALL) || defined(DOXYGEN) -long -GPIOPinRead(unsigned long ulPort, unsigned char ucPins) -{ - // - // Check the arguments. - // - ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || - (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || - (ulPort == GPIO_PORTE_BASE)); - - // - // Return the pin value(s). - // - return(HWREG(ulPort + (GPIO_O_DATA + (ucPins << 2)))); -} -#endif - -//***************************************************************************** -// -//! Writes a value at the specified pins of the selected GPIO port. -//! -//! \param ulPort base address of the selected GPIO port -//! \param ucPins bit-packed representation of the specified pins -//! \param ucVal value to write to the specified pins -//! -//! Writes the corresponding bit values to the output pins specified -//! by \e ucPins. Writing to a pin configured as an input pin has no -//! effect. -//! -//! The pins are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_pinwrite) || defined(BUILD_ALL) || defined(DOXYGEN) -void -GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, unsigned char ucVal) -{ - // - // Check the arguments. - // - ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || - (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || - (ulPort == GPIO_PORTE_BASE)); - - // - // Write the pins. - // - HWREG(ulPort + (GPIO_O_DATA + (ucPins << 2))) = ucVal; -} -#endif - -//***************************************************************************** -// -//! Configures pin(s) for use as an analog comparator input. -//! -//! \param ulPort base address of the selected GPIO port -//! \param ucPins bit-packed representation of the specified pins -//! -//! The analog comparator input pins must be properly configured for the analog -//! comparator to function correctly. This function provides the proper -//! configuration for those pins. -//! -//! \note This cannot be used to turn any pin into an analog comparator input; -//! it only configures an analog comparator pin for proper operation. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_pintypecomparator) || defined(BUILD_ALL) || defined(DOXYGEN) -void -GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins) -{ - // - // Check the arguments. - // - ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || - (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || - (ulPort == GPIO_PORTE_BASE)); - - // - // Make the pin(s) be inputs. - // - GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_IN); - - // - // Set the pad(s) for analog operation. - // - GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_ANALOG); -} -#endif - -//***************************************************************************** -// -//! Configures pin(s) for use by the I2C peripheral. -//! -//! \param ulPort base address of the selected GPIO port -//! \param ucPins bit-packed representation of the specified pins -//! -//! The I2C pins must be properly configured for the I2C peripheral to function -//! correctly. This function provides the proper configuration for those pins. -//! -//! \note This cannot be used to turn any pin into an I2C pin; it only -//! configures an I2C pin for proper operation. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_pintypei2c) || defined(BUILD_ALL) || defined(DOXYGEN) -void -GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins) -{ - // - // Check the arguments. - // - ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || - (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || - (ulPort == GPIO_PORTE_BASE)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for open-drain operation with a weak pull-up. - // - GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD_WPU); -} -#endif - -//***************************************************************************** -// -//! Configures pin(s) for use by the PWM peripheral. -//! -//! \param ulPort base address of the selected GPIO port -//! \param ucPins bit-packed representation of the specified pins -//! -//! The PWM pins must be properly configured for the PWM peripheral to function -//! correctly. This function provides a typical configuration for those pins; -//! other configurations may work as well depending upon the board setup (for -//! example, using the on-chip pull-ups). -//! -//! \note This cannot be used to turn any pin into a PWM pin; it only -//! configures a PWM pin for proper operation. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_pintypepwm) || defined(BUILD_ALL) || defined(DOXYGEN) -void -GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins) -{ - // - // Check the arguments. - // - ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || - (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || - (ulPort == GPIO_PORTE_BASE)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); -} -#endif - -//***************************************************************************** -// -//! Configures pin(s) for use by the QEI peripheral. -//! -//! \param ulPort base address of the selected GPIO port -//! \param ucPins bit-packed representation of the specified pins -//! -//! The QEI pins must be properly configured for the QEI peripheral to function -//! correctly. This function provides a typical configuration for those pins; -//! other configurations may work as well depending upon the board setup (for -//! example, not using the on-chip pull-ups). -//! -//! \note This cannot be used to turn any pin into a QEI pin; it only -//! configures a QEI pin for proper operation. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_pintypeqei) || defined(BUILD_ALL) || defined(DOXYGEN) -void -GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins) -{ - // - // Check the arguments. - // - ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || - (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || - (ulPort == GPIO_PORTE_BASE)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation with a weak pull-up. - // - GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU); -} -#endif - -//***************************************************************************** -// -//! Configures pin(s) for use by the SSI peripheral. -//! -//! \param ulPort base address of the selected GPIO port -//! \param ucPins bit-packed representation of the specified pins -//! -//! The SSI pins must be properly configured for the SSI peripheral to function -//! correctly. This function provides a typical configuration for those pins; -//! other configurations may work as well depending upon the board setup (for -//! example, using the on-chip pull-ups). -//! -//! \note This cannot be used to turn any pin into a SSI pin; it only -//! configures a SSI pin for proper operation. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_pintypessi) || defined(BUILD_ALL) || defined(DOXYGEN) -void -GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins) -{ - // - // Check the arguments. - // - ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || - (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || - (ulPort == GPIO_PORTE_BASE)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); -} -#endif - -//***************************************************************************** -// -//! Configures pin(s) for use by the Timer peripheral. -//! -//! \param ulPort base address of the selected GPIO port -//! \param ucPins bit-packed representation of the specified pins -//! -//! The CCP pins must be properly configured for the timer peripheral to -//! function correctly. This function provides a typical configuration for -//! those pins; other configurations may work as well depending upon the board -//! setup (for example, using the on-chip pull-ups). -//! -//! \note This cannot be used to turn any pin into a timer pin; it only -//! configures a timer pin for proper operation. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_pintypetimer) || defined(BUILD_ALL) || defined(DOXYGEN) -void -GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins) -{ - // - // Check the arguments. - // - ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || - (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || - (ulPort == GPIO_PORTE_BASE)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); -} -#endif - -//***************************************************************************** -// -//! Configures pin(s) for use by the UART peripheral. -//! -//! \param ulPort base address of the selected GPIO port -//! \param ucPins bit-packed representation of the specified pins -//! -//! The UART pins must be properly configured for the UART peripheral to -//! function correctly. This function provides a typical configuration for -//! those pins; other configurations may work as well depending upon the board -//! setup (for example, using the on-chip pull-ups). -//! -//! \note This cannot be used to turn any pin into a UART pin; it only -//! configures a UART pin for proper operation. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_pintypeuart) || defined(BUILD_ALL) || defined(DOXYGEN) -void -GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins) -{ - // - // Check the arguments. - // - ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || - (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || - (ulPort == GPIO_PORTE_BASE)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/gpio.h b/Demo/CORTEX_LM3S811_GCC/hw_include/gpio.h deleted file mode 100644 index 88d657223..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/gpio.h +++ /dev/null @@ -1,137 +0,0 @@ -//***************************************************************************** -// -// gpio.h - Defines and Macros for GPIO API. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __GPIO_H__ -#define __GPIO_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following values define the bit field for the ucPins argument to several -// of the APIs. -// -//***************************************************************************** -#define GPIO_PIN_0 0x00000001 // GPIO pin 0 -#define GPIO_PIN_1 0x00000002 // GPIO pin 1 -#define GPIO_PIN_2 0x00000004 // GPIO pin 2 -#define GPIO_PIN_3 0x00000008 // GPIO pin 3 -#define GPIO_PIN_4 0x00000010 // GPIO pin 4 -#define GPIO_PIN_5 0x00000020 // GPIO pin 5 -#define GPIO_PIN_6 0x00000040 // GPIO pin 6 -#define GPIO_PIN_7 0x00000080 // GPIO pin 7 - -//***************************************************************************** -// -// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and -// returned from GPIODirModeGet. -// -//***************************************************************************** -#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input -#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output -#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function - -//***************************************************************************** -// -// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and -// returned from GPIOIntTypeGet. -// -//***************************************************************************** -#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge -#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge -#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges -#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level -#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level - -//***************************************************************************** -// -// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter, -// and returned by GPIOPadConfigGet in the *pulStrength parameter. -// -//***************************************************************************** -#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength -#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength -#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength -#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control - -//***************************************************************************** -// -// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter, -// and returned by GPIOPadConfigGet in the *pulPadType parameter. -// -//***************************************************************************** -#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull -#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up -#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down -#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain -#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up -#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down -#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulPinIO); -extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin); -extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulIntType); -extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin); -extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulStrength, - unsigned long ulPadType); -extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin, - unsigned long *pulStrength, - unsigned long *pulPadType); -extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins); -extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked); -extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPortIntRegister(unsigned long ulPort, - void (*pfIntHandler)(void)); -extern void GPIOPortIntUnregister(unsigned long ulPort); -extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, - unsigned char ucVal); -extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins); - -#ifdef __cplusplus -} -#endif - -#endif // __GPIO_H__ diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/hw_adc.h b/Demo/CORTEX_LM3S811_GCC/hw_include/hw_adc.h deleted file mode 100644 index 022b9e963..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/hw_adc.h +++ /dev/null @@ -1,343 +0,0 @@ -//***************************************************************************** -// -// hw_adc.h - Macros used when accessing the ADC hardware. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_ADC_H__ -#define __HW_ADC_H__ - -//***************************************************************************** -// -// The following define the offsets of the ADC registers. -// -//***************************************************************************** -#define ADC_O_ACTSS 0x00000000 // Active sample register -#define ADC_O_RIS 0x00000004 // Raw interrupt status register -#define ADC_O_IM 0x00000008 // Interrupt mask register -#define ADC_O_ISC 0x0000000C // Interrupt status/clear register -#define ADC_O_OSTAT 0x00000010 // Overflow status register -#define ADC_O_EMUX 0x00000014 // Event multiplexer select reg. -#define ADC_O_USTAT 0x00000018 // Underflow status register -#define ADC_O_SSPRI 0x00000020 // Channel priority register -#define ADC_O_PSSI 0x00000028 // Processor sample initiate reg. -#define ADC_O_SAC 0x00000030 // Sample Averaging Control reg. -#define ADC_O_SSMUX0 0x00000040 // Multiplexer select 0 register -#define ADC_O_SSCTL0 0x00000044 // Sample sequence control 0 reg. -#define ADC_O_SSFIFO0 0x00000048 // Result FIFO 0 register -#define ADC_O_SSFSTAT0 0x0000004C // FIFO 0 status register -#define ADC_O_SSMUX1 0x00000060 // Multiplexer select 1 register -#define ADC_O_SSCTL1 0x00000064 // Sample sequence control 1 reg. -#define ADC_O_SSFIFO1 0x00000068 // Result FIFO 1 register -#define ADC_O_SSFSTAT1 0x0000006C // FIFO 1 status register -#define ADC_O_SSMUX2 0x00000080 // Multiplexer select 2 register -#define ADC_O_SSCTL2 0x00000084 // Sample sequence control 2 reg. -#define ADC_O_SSFIFO2 0x00000088 // Result FIFO 2 register -#define ADC_O_SSFSTAT2 0x0000008C // FIFO 2 status register -#define ADC_O_SSMUX3 0x000000A0 // Multiplexer select 3 register -#define ADC_O_SSCTL3 0x000000A4 // Sample sequence control 3 reg. -#define ADC_O_SSFIFO3 0x000000A8 // Result FIFO 3 register -#define ADC_O_SSFSTAT3 0x000000AC // FIFO 3 status register -#define ADC_O_TMLB 0x00000100 // Test mode loopback register - -//***************************************************************************** -// -// The following define the offsets of the ADC sequence registers. -// -//***************************************************************************** -#define ADC_O_SEQ 0x00000040 // Offset to the first sequence -#define ADC_O_SEQ_STEP 0x00000020 // Increment to the next sequence -#define ADC_O_X_SSMUX 0x00000000 // Multiplexer select register -#define ADC_O_X_SSCTL 0x00000004 // Sample sequence control register -#define ADC_O_X_SSFIFO 0x00000008 // Result FIFO register -#define ADC_O_X_SSFSTAT 0x0000000C // FIFO status register - -//***************************************************************************** -// -// The following define the bit fields in the ADC_ACTSS register. -// -//***************************************************************************** -#define ADC_ACTSS_ASEN3 0x00000008 // Sample sequence 3 enable -#define ADC_ACTSS_ASEN2 0x00000004 // Sample sequence 2 enable -#define ADC_ACTSS_ASEN1 0x00000002 // Sample sequence 1 enable -#define ADC_ACTSS_ASEN0 0x00000001 // Sample sequence 0 enable - -//***************************************************************************** -// -// The following define the bit fields in the ADC_RIS register. -// -//***************************************************************************** -#define ADC_RIS_INR3 0x00000008 // Sample sequence 3 interrupt -#define ADC_RIS_INR2 0x00000004 // Sample sequence 2 interrupt -#define ADC_RIS_INR1 0x00000002 // Sample sequence 1 interrupt -#define ADC_RIS_INR0 0x00000001 // Sample sequence 0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the ADC_IM register. -// -//***************************************************************************** -#define ADC_IM_MASK3 0x00000008 // Sample sequence 3 mask -#define ADC_IM_MASK2 0x00000004 // Sample sequence 2 mask -#define ADC_IM_MASK1 0x00000002 // Sample sequence 1 mask -#define ADC_IM_MASK0 0x00000001 // Sample sequence 0 mask - -//***************************************************************************** -// -// The following define the bit fields in the ADC_ISC register. -// -//***************************************************************************** -#define ADC_ISC_IN3 0x00000008 // Sample sequence 3 interrupt -#define ADC_ISC_IN2 0x00000004 // Sample sequence 2 interrupt -#define ADC_ISC_IN1 0x00000002 // Sample sequence 1 interrupt -#define ADC_ISC_IN0 0x00000001 // Sample sequence 0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the ADC_OSTAT register. -// -//***************************************************************************** -#define ADC_OSTAT_OV3 0x00000008 // Sample sequence 3 overflow -#define ADC_OSTAT_OV2 0x00000004 // Sample sequence 2 overflow -#define ADC_OSTAT_OV1 0x00000002 // Sample sequence 1 overflow -#define ADC_OSTAT_OV0 0x00000001 // Sample sequence 0 overflow - -//***************************************************************************** -// -// The following define the bit fields in the ADC_EMUX register. -// -//***************************************************************************** -#define ADC_EMUX_EM3_MASK 0x0000F000 // Event mux 3 mask -#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor event -#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog comparator 0 event -#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog comparator 1 event -#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog comparator 2 event -#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External event -#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer event -#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0 event -#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1 event -#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2 event -#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always event -#define ADC_EMUX_EM2_MASK 0x00000F00 // Event mux 2 mask -#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor event -#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog comparator 0 event -#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog comparator 1 event -#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog comparator 2 event -#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External event -#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer event -#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0 event -#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1 event -#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2 event -#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always event -#define ADC_EMUX_EM1_MASK 0x000000F0 // Event mux 1 mask -#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor event -#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog comparator 0 event -#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog comparator 1 event -#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog comparator 2 event -#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External event -#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer event -#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0 event -#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1 event -#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2 event -#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always event -#define ADC_EMUX_EM0_MASK 0x0000000F // Event mux 0 mask -#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor event -#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog comparator 0 event -#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog comparator 1 event -#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog comparator 2 event -#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External event -#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer event -#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0 event -#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1 event -#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2 event -#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always event -#define ADC_EMUX_EM0_SHIFT 0 // The shift for the first event -#define ADC_EMUX_EM1_SHIFT 4 // The shift for the second event -#define ADC_EMUX_EM2_SHIFT 8 // The shift for the third event -#define ADC_EMUX_EM3_SHIFT 12 // The shift for the fourth event - -//***************************************************************************** -// -// The following define the bit fields in the ADC_USTAT register. -// -//***************************************************************************** -#define ADC_USTAT_UV3 0x00000008 // Sample sequence 3 underflow -#define ADC_USTAT_UV2 0x00000004 // Sample sequence 2 underflow -#define ADC_USTAT_UV1 0x00000002 // Sample sequence 1 underflow -#define ADC_USTAT_UV0 0x00000001 // Sample sequence 0 underflow - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSPRI register. -// -//***************************************************************************** -#define ADC_SSPRI_SS3_MASK 0x00003000 // Sequencer 3 priority mask -#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority -#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority -#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority -#define ADC_SSPRI_SS2_MASK 0x00000300 // Sequencer 2 priority mask -#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority -#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority -#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority -#define ADC_SSPRI_SS1_MASK 0x00000030 // Sequencer 1 priority mask -#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority -#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority -#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority -#define ADC_SSPRI_SS0_MASK 0x00000003 // Sequencer 0 priority mask -#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority -#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority -#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority - -//***************************************************************************** -// -// The following define the bit fields in the ADC_PSSI register. -// -//***************************************************************************** -#define ADC_PSSI_SS3 0x00000008 // Trigger sample sequencer 3 -#define ADC_PSSI_SS2 0x00000004 // Trigger sample sequencer 2 -#define ADC_PSSI_SS1 0x00000002 // Trigger sample sequencer 1 -#define ADC_PSSI_SS0 0x00000001 // Trigger sample sequencer 0 - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SAC register. -// -//***************************************************************************** -#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling -#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling -#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling -#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling -#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling -#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling -#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSMUX0, ADC_SSMUX1, -// ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present in all -// registers. -// -//***************************************************************************** -#define ADC_SSMUX_MUX7_MASK 0x70000000 // 8th mux select mask -#define ADC_SSMUX_MUX6_MASK 0x07000000 // 7th mux select mask -#define ADC_SSMUX_MUX5_MASK 0x00700000 // 6th mux select mask -#define ADC_SSMUX_MUX4_MASK 0x00070000 // 5th mux select mask -#define ADC_SSMUX_MUX3_MASK 0x00007000 // 4th mux select mask -#define ADC_SSMUX_MUX2_MASK 0x00000700 // 3rd mux select mask -#define ADC_SSMUX_MUX1_MASK 0x00000070 // 2nd mux select mask -#define ADC_SSMUX_MUX0_MASK 0x00000007 // 1st mux select mask -#define ADC_SSMUX_MUX7_SHIFT 28 -#define ADC_SSMUX_MUX6_SHIFT 24 -#define ADC_SSMUX_MUX5_SHIFT 20 -#define ADC_SSMUX_MUX4_SHIFT 16 -#define ADC_SSMUX_MUX3_SHIFT 12 -#define ADC_SSMUX_MUX2_SHIFT 8 -#define ADC_SSMUX_MUX1_SHIFT 4 -#define ADC_SSMUX_MUX0_SHIFT 0 - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSCTL0, ADC_SSCTL1, -// ADC_SSCTL2, and ADC_SSCTL3 registers. Not all fields are present in all -// registers. -// -//***************************************************************************** -#define ADC_SSCTL_TS7 0x80000000 // 8th temperature sensor select -#define ADC_SSCTL_IE7 0x40000000 // 8th interrupt enable -#define ADC_SSCTL_END7 0x20000000 // 8th sequence end select -#define ADC_SSCTL_D7 0x10000000 // 8th differential select -#define ADC_SSCTL_TS6 0x08000000 // 7th temperature sensor select -#define ADC_SSCTL_IE6 0x04000000 // 7th interrupt enable -#define ADC_SSCTL_END6 0x02000000 // 7th sequence end select -#define ADC_SSCTL_D6 0x01000000 // 7th differential select -#define ADC_SSCTL_TS5 0x00800000 // 6th temperature sensor select -#define ADC_SSCTL_IE5 0x00400000 // 6th interrupt enable -#define ADC_SSCTL_END5 0x00200000 // 6th sequence end select -#define ADC_SSCTL_D5 0x00100000 // 6th differential select -#define ADC_SSCTL_TS4 0x00080000 // 5th temperature sensor select -#define ADC_SSCTL_IE4 0x00040000 // 5th interrupt enable -#define ADC_SSCTL_END4 0x00020000 // 5th sequence end select -#define ADC_SSCTL_D4 0x00010000 // 5th differential select -#define ADC_SSCTL_TS3 0x00008000 // 4th temperature sensor select -#define ADC_SSCTL_IE3 0x00004000 // 4th interrupt enable -#define ADC_SSCTL_END3 0x00002000 // 4th sequence end select -#define ADC_SSCTL_D3 0x00001000 // 4th differential select -#define ADC_SSCTL_TS2 0x00000800 // 3rd temperature sensor select -#define ADC_SSCTL_IE2 0x00000400 // 3rd interrupt enable -#define ADC_SSCTL_END2 0x00000200 // 3rd sequence end select -#define ADC_SSCTL_D2 0x00000100 // 3rd differential select -#define ADC_SSCTL_TS1 0x00000080 // 2nd temperature sensor select -#define ADC_SSCTL_IE1 0x00000040 // 2nd interrupt enable -#define ADC_SSCTL_END1 0x00000020 // 2nd sequence end select -#define ADC_SSCTL_D1 0x00000010 // 2nd differential select -#define ADC_SSCTL_TS0 0x00000008 // 1st temperature sensor select -#define ADC_SSCTL_IE0 0x00000004 // 1st interrupt enable -#define ADC_SSCTL_END0 0x00000002 // 1st sequence end select -#define ADC_SSCTL_D0 0x00000001 // 1st differential select - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSFIFO0, ADC_SSFIFO1, -// ADC_SSFIFO2, and ADC_SSFIFO3 registers. -// -//***************************************************************************** -#define ADC_SSFIFO_DATA_MASK 0x000003FF // Sample data -#define ADC_SSFIFO_DATA_SHIFT 0 - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSFSTAT0, ADC_SSFSTAT1, -// ADC_SSFSTAT2, and ADC_SSFSTAT3 registers. -// -//***************************************************************************** -#define ADC_SSFSTAT_FULL 0x00001000 // FIFO is full -#define ADC_SSFSTAT_EMPTY 0x00000100 // FIFO is empty -#define ADC_SSFSTAT_HPTR 0x000000F0 // FIFO head pointer -#define ADC_SSFSTAT_TPTR 0x0000000F // FIFO tail pointer - -//***************************************************************************** -// -// The following define the bit fields in the ADC_TMLB register. -// -//***************************************************************************** -#define ADC_TMLB_LB 0x00000001 // Loopback control signals - -//***************************************************************************** -// -// The following define the bit fields in the loopback ADC data. -// -//***************************************************************************** -#define ADC_LB_CNT_MASK 0x000003C0 // Sample counter mask -#define ADC_LB_CONT 0x00000020 // Continuation sample -#define ADC_LB_DIFF 0x00000010 // Differential sample -#define ADC_LB_TS 0x00000008 // Temperature sensor sample -#define ADC_LB_MUX_MASK 0x00000007 // Input channel number mask -#define ADC_LB_CNT_SHIFT 6 // Sample counter shift -#define ADC_LB_MUX_SHIFT 0 // Input channel number shift - -#endif // __HW_ADC_H__ diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/hw_comp.h b/Demo/CORTEX_LM3S811_GCC/hw_include/hw_comp.h deleted file mode 100644 index 991b7a083..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/hw_comp.h +++ /dev/null @@ -1,118 +0,0 @@ -//***************************************************************************** -// -// hw_comp.h - Macros used when accessing the comparator hardware. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_COMP_H__ -#define __HW_COMP_H__ - -//***************************************************************************** -// -// The following define the offsets of the comparator registers. -// -//***************************************************************************** -#define COMP_O_MIS 0x00000000 // Interrupt status register -#define COMP_O_RIS 0x00000004 // Raw interrupt status register -#define COMP_O_INTEN 0x00000008 // Interrupt enable register -#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg. -#define COMP_O_ACSTAT0 0x00000020 // Comp0 status register -#define COMP_O_ACCTL0 0x00000024 // Comp0 control register -#define COMP_O_ACSTAT1 0x00000040 // Comp1 status register -#define COMP_O_ACCTL1 0x00000044 // Comp1 control register -#define COMP_O_ACSTAT2 0x00000060 // Comp2 status register -#define COMP_O_ACCTL2 0x00000064 // Comp2 control register - -//***************************************************************************** -// -// The following define the bit fields in the COMP_MIS, COMP_RIS, and -// COMP_INTEN registers. -// -//***************************************************************************** -#define COMP_INT_2 0x00000004 // Comp2 interrupt -#define COMP_INT_1 0x00000002 // Comp1 interrupt -#define COMP_INT_0 0x00000001 // Comp0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the COMP_REFCTL register. -// -//***************************************************************************** -#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable -#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range -#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask -#define COMP_REFCTL_VREF_SHIFT 0 - -//***************************************************************************** -// -// The following define the bit fields in the COMP_ACSTAT0, COMP_ACSTAT1, and -// COMP_ACSTAT2 registers. -// -//***************************************************************************** -#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value - -//***************************************************************************** -// -// The following define the bit fields in the COMP_ACCTL0, COMP_ACCTL1, and -// COMP_ACCTL2 registers. -// -//***************************************************************************** -#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable -#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask -#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin -#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin -#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference -#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved -#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable -#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select -#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask -#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense -#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge -#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge -#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges -#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select -#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask -#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense -#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge -#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge -#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges -#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert - -//***************************************************************************** -// -// The following define the reset values for the comparator registers. -// -//***************************************************************************** -#define COMP_RV_MIS 0x00000000 // Interrupt status register -#define COMP_RV_RIS 0x00000000 // Raw interrupt status register -#define COMP_RV_INTEN 0x00000000 // Interrupt enable register -#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg. -#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register -#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register -#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register -#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register -#define COMP_RV_ACSTAT2 0x00000000 // Comp2 status register -#define COMP_RV_ACCTL2 0x00000000 // Comp2 control register - -#endif // __HW_COMP_H__ diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/hw_flash.h b/Demo/CORTEX_LM3S811_GCC/hw_include/hw_flash.h deleted file mode 100644 index 53128b436..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/hw_flash.h +++ /dev/null @@ -1,139 +0,0 @@ -//***************************************************************************** -// -// hw_flash.h - Macros used when accessing the flash controller. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_FLASH_H__ -#define __HW_FLASH_H__ - -//***************************************************************************** -// -// The following define the offsets of the FLASH registers. -// -//***************************************************************************** -#define FLASH_FMA 0x400FD000 // Memory address register -#define FLASH_FMD 0x400FD004 // Memory data register -#define FLASH_FMC 0x400FD008 // Memory control register -#define FLASH_FCRIS 0x400FD00c // Raw interrupt status register -#define FLASH_FCIM 0x400FD010 // Interrupt mask register -#define FLASH_FCMISC 0x400FD014 // Interrupt status register -#define FLASH_FMPRE 0x400FE130 // FLASH read protect register -#define FLASH_FMPPE 0x400FE134 // FLASH program protect register -#define FLASH_USECRL 0x400FE140 // uSec reload register - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FMC register. -// -//***************************************************************************** -#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask -#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key -#define FLASH_FMC_COMT 0x00000008 // Commit user register -#define FLASH_FMC_MERASE 0x00000004 // Mass erase FLASH -#define FLASH_FMC_ERASE 0x00000002 // Erase FLASH page -#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FCRIS register. -// -//***************************************************************************** -#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status -#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FCIM register. -// -//***************************************************************************** -#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask -#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FMIS register. -// -//***************************************************************************** -#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status -#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FMPRE and FLASH_FMPPE -// registers. -// -//***************************************************************************** -#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31 -#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30 -#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29 -#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28 -#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27 -#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26 -#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25 -#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24 -#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23 -#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22 -#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21 -#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20 -#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19 -#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18 -#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17 -#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16 -#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15 -#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14 -#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13 -#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12 -#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11 -#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10 -#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9 -#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8 -#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7 -#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6 -#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5 -#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4 -#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3 -#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2 -#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1 -#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0 - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_USECRL register. -// -//***************************************************************************** -#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec -#define FLASH_USECRL_SHIFT 0 - -//***************************************************************************** -// -// The erase size is the size of the FLASH block that is erased by an erase -// operation, and the protect size is the size of the FLASH block that is -// protected by each protection register. -// -//***************************************************************************** -#define FLASH_ERASE_SIZE 0x00000400 -#define FLASH_PROTECT_SIZE 0x00000800 - -#endif // __HW_FLASH_H__ diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/hw_gpio.h b/Demo/CORTEX_LM3S811_GCC/hw_include/hw_gpio.h deleted file mode 100644 index bf25d3f5a..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/hw_gpio.h +++ /dev/null @@ -1,103 +0,0 @@ -//***************************************************************************** -// -// hw_gpio.h - Defines and Macros for GPIO hardware. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_GPIO_H__ -#define __HW_GPIO_H__ - -//***************************************************************************** -// -// GPIO Register Offsets. -// -//***************************************************************************** -#define GPIO_O_DATA 0x00000000 // Data register. -#define GPIO_O_DIR 0x00000400 // Data direction register. -#define GPIO_O_IS 0x00000404 // Interrupt sense register. -#define GPIO_O_IBE 0x00000408 // Interrupt both edges register. -#define GPIO_O_IEV 0x0000040C // Intterupt event register. -#define GPIO_O_IM 0x00000410 // Interrupt mask register. -#define GPIO_O_RIS 0x00000414 // Raw interrupt status register. -#define GPIO_O_MIS 0x00000418 // Masked interrupt status reg. -#define GPIO_O_ICR 0x0000041C // Interrupt clear register. -#define GPIO_O_AFSEL 0x00000420 // Mode control select register. -#define GPIO_O_DR2R 0x00000500 // 2ma drive select register. -#define GPIO_O_DR4R 0x00000504 // 4ma drive select register. -#define GPIO_O_DR8R 0x00000508 // 8ma drive select register. -#define GPIO_O_ODR 0x0000050C // Open drain select register. -#define GPIO_O_PUR 0x00000510 // Pull up select register. -#define GPIO_O_PDR 0x00000514 // Pull down select register. -#define GPIO_O_SLR 0x00000518 // Slew rate control enable reg. -#define GPIO_O_DEN 0x0000051C // Digital input enable register. -#define GPIO_O_PeriphID4 0x00000FD0 // -#define GPIO_O_PeriphID5 0x00000FD4 // -#define GPIO_O_PeriphID6 0x00000FD8 // -#define GPIO_O_PeriphID7 0x00000FDC // -#define GPIO_O_PeriphID0 0x00000FE0 // -#define GPIO_O_PeriphID1 0x00000FE4 // -#define GPIO_O_PeriphID2 0x00000FE8 // -#define GPIO_O_PeriphID3 0x00000FEC // -#define GPIO_O_PCellID0 0x00000FF0 // -#define GPIO_O_PCellID1 0x00000FF4 // -#define GPIO_O_PCellID2 0x00000FF8 // -#define GPIO_O_PCellID3 0x00000FFC // - -//***************************************************************************** -// -// GPIO Register reset values. -// -//***************************************************************************** -#define GPIO_RV_DATA 0x00000000 // Data register reset value. -#define GPIO_RV_DIR 0x00000000 // Data direction reg RV. -#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV. -#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV. -#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV. -#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV. -#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV. -#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV. -#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV. -#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV. -#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV. -#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV. -#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV. -#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV. -#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV. -#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV. -#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV. -#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV. -#define GPIO_RV_PeriphID4 0x00000000 // -#define GPIO_RV_PeriphID5 0x00000000 // -#define GPIO_RV_PeriphID6 0x00000000 // -#define GPIO_RV_PeriphID7 0x00000000 // -#define GPIO_RV_PeriphID0 0x00000061 // -#define GPIO_RV_PeriphID1 0x00000010 // -#define GPIO_RV_PeriphID2 0x00000004 // -#define GPIO_RV_PeriphID3 0x00000000 // -#define GPIO_RV_PCellID0 0x0000000D // -#define GPIO_RV_PCellID1 0x000000F0 // -#define GPIO_RV_PCellID2 0x00000005 // -#define GPIO_RV_PCellID3 0x000000B1 // - -#endif // __HW_GPIO_H__ diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/hw_i2c.h b/Demo/CORTEX_LM3S811_GCC/hw_include/hw_i2c.h deleted file mode 100644 index 2c9f46dab..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/hw_i2c.h +++ /dev/null @@ -1,197 +0,0 @@ -//***************************************************************************** -// -// hw_i2c.h - Macros used when accessing the I2C master and slave hardware. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_I2C_H__ -#define __HW_I2C_H__ - -//***************************************************************************** -// -// The following defines the offset between the I2C master and slave registers. -// -//***************************************************************************** -#define I2C_O_SLAVE 0x00000800 // Offset from master to slave - -//***************************************************************************** -// -// The following define the offsets of the I2C master registers. -// -//***************************************************************************** -#define I2C_MASTER_O_SA 0x00000000 // Slave address register -#define I2C_MASTER_O_CS 0x00000004 // Control and Status register -#define I2C_MASTER_O_DR 0x00000008 // Data register -#define I2C_MASTER_O_TPR 0x0000000C // Timer period register -#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register -#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register -#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg -#define I2C_MASTER_O_MICR 0x0000001c // Interrupt clear register -#define I2C_MASTER_O_CR 0x00000020 // Configuration register - -//***************************************************************************** -// -// The following define the offsets of the I2C slave registers. -// -//***************************************************************************** -#define I2C_SLAVE_O_OAR 0x00000000 // Own address register -#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register -#define I2C_SLAVE_O_DR 0x00000008 // Data register -#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register -#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register -#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg -#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register - -//***************************************************************************** -// -// The followng define the bit fields in the I2C master slave address register. -// -//***************************************************************************** -#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address -#define I2C_MASTER_SA_RS 0x00000001 // Receive/send -#define I2C_MASTER_SA_SA_SHIFT 1 - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Control and Status -// register. -// -//***************************************************************************** -#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde -#define I2C_MASTER_CS_STOP 0x00000004 // Stop -#define I2C_MASTER_CS_START 0x00000002 // Start -#define I2C_MASTER_CS_RUN 0x00000001 // Run -#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy -#define I2C_MASTER_CS_IDLE 0x00000020 // Idle -#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration -#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged -#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged -#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred -#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data -#define I2C_MASTER_CS_ERR_MASK 0x0000001C - -//***************************************************************************** -// -// The following define values used in determining the contents of the I2C -// Master Timer Period register. -// -//***************************************************************************** -#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period -#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period -#define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP) -#define I2C_SCL_STANDARD 100000 // SCL standard frequency -#define I2C_SCL_FAST 400000 // SCL fast frequency - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Interrupt Mask -// register. -// -//***************************************************************************** -#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Raw Interrupt Status -// register. -// -//***************************************************************************** -#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Masked Interrupt -// Status register. -// -//***************************************************************************** -#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Interrupt Clear -// register. -// -//***************************************************************************** -#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Configuration -// register. -// -//***************************************************************************** -#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable -#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable -#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Own Address register. -// -//***************************************************************************** -#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Control/Status -// register. -// -//***************************************************************************** -#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device -#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received -#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Interrupt Mask -// register. -// -//***************************************************************************** -#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Raw Interrupt Status -// register. -// -//***************************************************************************** -#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Masked Interrupt -// Status register. -// -//***************************************************************************** -#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Interrupt Clear -// register. -// -//***************************************************************************** -#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear - -#endif // __HW_I2C_H__ diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/hw_ints.h b/Demo/CORTEX_LM3S811_GCC/hw_include/hw_ints.h deleted file mode 100644 index 2204a2c07..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/hw_ints.h +++ /dev/null @@ -1,97 +0,0 @@ -//***************************************************************************** -// -// hw_ints.h - Macros that define the interrupt assignment on Stellaris. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_INTS_H__ -#define __HW_INTS_H__ - -//***************************************************************************** -// -// The following define the fault assignments. -// -//***************************************************************************** -#define FAULT_NMI 2 // NMI fault -#define FAULT_HARD 3 // Hard fault -#define FAULT_MPU 4 // MPU fault -#define FAULT_BUS 5 // Bus fault -#define FAULT_USAGE 6 // Usage fault -#define FAULT_SVCALL 11 // SVCall -#define FAULT_DEBUG 12 // Debug monitor -#define FAULT_PENDSV 14 // PendSV -#define FAULT_SYSTICK 15 // System Tick - -//***************************************************************************** -// -// The following define the interrupt assignments. -// -//***************************************************************************** -#define INT_GPIOA 16 // GPIO Port A -#define INT_GPIOB 17 // GPIO Port B -#define INT_GPIOC 18 // GPIO Port C -#define INT_GPIOD 19 // GPIO Port D -#define INT_GPIOE 20 // GPIO Port E -#define INT_UART0 21 // UART0 Rx and Tx -#define INT_UART1 22 // UART1 Rx and Tx -#define INT_SSI 23 // SSI Rx and Tx -#define INT_I2C 24 // I2C Master and Slave -#define INT_PWM_FAULT 25 // PWM Fault -#define INT_PWM0 26 // PWM Generator 0 -#define INT_PWM1 27 // PWM Generator 1 -#define INT_PWM2 28 // PWM Generator 2 -#define INT_QEI 29 // Quadrature Encoder -#define INT_ADC0 30 // ADC Sequence 0 -#define INT_ADC1 31 // ADC Sequence 1 -#define INT_ADC2 32 // ADC Sequence 2 -#define INT_ADC3 33 // ADC Sequence 3 -#define INT_WATCHDOG 34 // Watchdog timer -#define INT_TIMER0A 35 // Timer 0 subtimer A -#define INT_TIMER0B 36 // Timer 0 subtimer B -#define INT_TIMER1A 37 // Timer 1 subtimer A -#define INT_TIMER1B 38 // Timer 1 subtimer B -#define INT_TIMER2A 39 // Timer 2 subtimer A -#define INT_TIMER2B 40 // Timer 2 subtimer B -#define INT_COMP0 41 // Analog Comparator 0 -#define INT_COMP1 42 // Analog Comparator 1 -#define INT_COMP2 43 // Analog Comparator 2 -#define INT_SYSCTL 44 // System Control (PLL, OSC, BO) -#define INT_FLASH 45 // FLASH Control - -//***************************************************************************** -// -// The total number of interrupts. -// -//***************************************************************************** -#define NUM_INTERRUPTS 46 - -//***************************************************************************** -// -// The total number of priority levels. -// -//***************************************************************************** -#define NUM_PRIORITY 8 -#define NUM_PRIORITY_BITS 3 - -#endif // __HW_INTS_H__ diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/hw_memmap.h b/Demo/CORTEX_LM3S811_GCC/hw_include/hw_memmap.h deleted file mode 100644 index 2b11f3513..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/hw_memmap.h +++ /dev/null @@ -1,64 +0,0 @@ -//***************************************************************************** -// -// hw_memmap.h - Macros defining the memory map of Stellaris. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_MEMMAP_H__ -#define __HW_MEMMAP_H__ - -//***************************************************************************** -// -// The following define the base address of the memories and peripherals. -// -//***************************************************************************** -#define FLASH_BASE 0x00000000 // FLASH memory -#define SRAM_BASE 0x20000000 // SRAM memory -#define WATCHDOG_BASE 0x40000000 // Watchdog -#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A -#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B -#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C -#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D -#define SSI_BASE 0x40008000 // SSI -#define UART0_BASE 0x4000C000 // UART0 -#define UART1_BASE 0x4000D000 // UART1 -#define I2C_MASTER_BASE 0x40020000 // I2C Master -#define I2C_SLAVE_BASE 0x40020800 // I2C Slave -#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E -#define PWM_BASE 0x40028000 // PWM -#define QEI_BASE 0x4002C000 // QEI -#define TIMER0_BASE 0x40030000 // Timer0 -#define TIMER1_BASE 0x40031000 // Timer1 -#define TIMER2_BASE 0x40032000 // Timer2 -#define ADC_BASE 0x40038000 // ADC -#define COMP_BASE 0x4003C000 // Analog comparators -#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller -#define SYSCTL_BASE 0x400FE000 // System Control -#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell -#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace -#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint -#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl -#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit - -#endif // __HW_MEMMAP_H__ diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/hw_nvic.h b/Demo/CORTEX_LM3S811_GCC/hw_include/hw_nvic.h deleted file mode 100644 index 6598ef88b..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/hw_nvic.h +++ /dev/null @@ -1,830 +0,0 @@ -//***************************************************************************** -// -// hw_nvic.h - Macros used when accessing the NVIC hardware. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_NVIC_H__ -#define __HW_NVIC_H__ - -//***************************************************************************** -// -// The following define the addresses of the NVIC registers. -// -//***************************************************************************** -#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg. -#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg. -#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register -#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register -#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg. -#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register -#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg. -#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register -#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg. -#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register -#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register -#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register -#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register -#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register -#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register -#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register -#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register -#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register -#define NVIC_CPUID 0xE000ED00 // CPUID Base Register -#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register -#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register -#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg. -#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register -#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register -#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority -#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority -#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority -#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State -#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg. -#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register -#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register -#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register -#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register -#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register -#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register -#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register -#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register -#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg. -#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg. -#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select -#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data -#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control -#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg. - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_INT_TYPE register. -// -//***************************************************************************** -#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) -#define NVIC_INT_TYPE_LINES_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_CTRL register. -// -//***************************************************************************** -#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag -#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source -#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable -#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_RELOAD register. -// -//***************************************************************************** -#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value -#define NVIC_ST_RELOAD_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_CURRENT register. -// -//***************************************************************************** -#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value -#define NVIC_ST_CURRENT_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_CAL register. -// -//***************************************************************************** -#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock -#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew -#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value -#define NVIC_ST_CAL_ONEMS_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_EN0 register. -// -//***************************************************************************** -#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable -#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable -#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable -#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable -#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable -#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable -#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable -#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable -#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable -#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable -#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable -#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable -#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable -#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable -#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable -#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable -#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable -#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable -#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable -#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable -#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable -#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable -#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable -#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable -#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable -#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable -#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable -#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable -#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable -#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable -#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable -#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DIS0 register. -// -//***************************************************************************** -#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable -#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable -#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable -#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable -#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable -#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable -#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable -#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable -#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable -#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable -#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable -#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable -#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable -#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable -#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable -#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable -#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable -#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable -#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable -#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable -#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable -#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable -#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable -#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable -#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable -#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable -#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable -#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable -#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable -#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable -#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable -#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PEND0 register. -// -//***************************************************************************** -#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend -#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend -#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend -#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend -#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend -#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend -#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend -#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend -#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend -#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend -#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend -#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend -#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend -#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend -#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend -#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend -#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend -#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend -#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend -#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend -#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend -#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend -#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend -#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend -#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend -#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend -#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend -#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend -#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend -#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend -#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend -#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_UNPEND0 register. -// -//***************************************************************************** -#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend -#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend -#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend -#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend -#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend -#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend -#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend -#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend -#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend -#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend -#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend -#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend -#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend -#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend -#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend -#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend -#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend -#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend -#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend -#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend -#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend -#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend -#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend -#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend -#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend -#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend -#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend -#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend -#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend -#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend -#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend -#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ACTIVE0 register. -// -//***************************************************************************** -#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active -#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active -#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active -#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active -#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active -#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active -#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active -#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active -#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active -#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active -#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active -#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active -#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active -#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active -#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active -#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active -#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active -#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active -#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active -#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active -#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active -#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active -#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active -#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active -#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active -#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active -#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active -#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active -#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active -#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active -#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active -#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI0 register. -// -//***************************************************************************** -#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask -#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask -#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask -#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask -#define NVIC_PRI0_INT3_S 24 -#define NVIC_PRI0_INT2_S 16 -#define NVIC_PRI0_INT1_S 8 -#define NVIC_PRI0_INT0_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI1 register. -// -//***************************************************************************** -#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask -#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask -#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask -#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask -#define NVIC_PRI1_INT7_S 24 -#define NVIC_PRI1_INT6_S 16 -#define NVIC_PRI1_INT5_S 8 -#define NVIC_PRI1_INT4_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI2 register. -// -//***************************************************************************** -#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask -#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask -#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask -#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask -#define NVIC_PRI2_INT11_S 24 -#define NVIC_PRI2_INT10_S 16 -#define NVIC_PRI2_INT9_S 8 -#define NVIC_PRI2_INT8_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI3 register. -// -//***************************************************************************** -#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask -#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask -#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask -#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask -#define NVIC_PRI3_INT15_S 24 -#define NVIC_PRI3_INT14_S 16 -#define NVIC_PRI3_INT13_S 8 -#define NVIC_PRI3_INT12_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI4 register. -// -//***************************************************************************** -#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask -#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask -#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask -#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask -#define NVIC_PRI4_INT19_S 24 -#define NVIC_PRI4_INT18_S 16 -#define NVIC_PRI4_INT17_S 8 -#define NVIC_PRI4_INT16_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI5 register. -// -//***************************************************************************** -#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask -#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask -#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask -#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask -#define NVIC_PRI5_INT23_S 24 -#define NVIC_PRI5_INT22_S 16 -#define NVIC_PRI5_INT21_S 8 -#define NVIC_PRI5_INT20_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI6 register. -// -//***************************************************************************** -#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask -#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask -#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask -#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask -#define NVIC_PRI6_INT27_S 24 -#define NVIC_PRI6_INT26_S 16 -#define NVIC_PRI6_INT25_S 8 -#define NVIC_PRI6_INT24_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI7 register. -// -//***************************************************************************** -#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask -#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask -#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask -#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask -#define NVIC_PRI7_INT31_S 24 -#define NVIC_PRI7_INT30_S 16 -#define NVIC_PRI7_INT29_S 8 -#define NVIC_PRI7_INT28_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_CPUID register. -// -//***************************************************************************** -#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer -#define NVIC_CPUID_VAR_M 0x00F00000 // Variant -#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number -#define NVIC_CPUID_REV_M 0x0000000F // Revision - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_INT_CTRL register. -// -//***************************************************************************** -#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI -#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV -#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV -#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling -#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending -#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception -#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base -#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception -#define NVIC_INT_CTRL_VEC_PEN_S 12 -#define NVIC_INT_CTRL_VEC_ACT_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_VTABLE register. -// -//***************************************************************************** -#define NVIC_VTABLE_BASE 0x20000000 // Vector table base -#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset -#define NVIC_VTABLE_OFFSET_S 8 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_APINT register. -// -//***************************************************************************** -#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask -#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key -#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess -#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group -#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split -#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split -#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split -#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split -#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split -#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split -#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split -#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split -#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request -#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info -#define NVIC_APINT_VECT_RESET 0x00000001 // System reset - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_CTRL register. -// -//***************************************************************************** -#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend -#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable -#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_CFG_CTRL register. -// -//***************************************************************************** -#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault -#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0 -#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access -#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger -#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger -#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_PRI1 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler -#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler -#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler -#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler -#define NVIC_SYS_PRI1_USAGE_S 16 -#define NVIC_SYS_PRI1_BUS_S 8 -#define NVIC_SYS_PRI1_MEM_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_PRI2 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler -#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers -#define NVIC_SYS_PRI2_SVC_S 24 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_PRI3 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler -#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler -#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler -#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler -#define NVIC_SYS_PRI3_TICK_S 24 -#define NVIC_SYS_PRI3_PENDSV_S 16 -#define NVIC_SYS_PRI3_DEBUG_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_HND_CTRL register. -// -//***************************************************************************** -#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable -#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable -#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable -#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended -#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended -#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active -#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active -#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active -#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active -#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active -#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active -#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_FAULT_STAT register. -// -//***************************************************************************** -#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault -#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault -#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault -#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault -#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault -#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault -#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid -#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault -#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault -#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error -#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error -#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault -#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid -#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation -#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation -#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation -#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_HFAULT_STAT register. -// -//***************************************************************************** -#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event -#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler -#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DEBUG_STAT register. -// -//***************************************************************************** -#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted -#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch -#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match -#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction -#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MM_ADDR register. -// -//***************************************************************************** -#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address -#define NVIC_MM_ADDR_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_FAULT_ADDR register. -// -//***************************************************************************** -#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address -#define NVIC_FAULT_ADDR_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_EXC_STACK register. -// -//***************************************************************************** -#define NVIC_EXC_STACK_DEEP 0x00000001 // Exception stack - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_EXC_NUM register. -// -//***************************************************************************** -#define NVIC_EXC_NUM_M 0x000003FF // Exception number -#define NVIC_EXC_NUM_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_COPRO register. -// -//***************************************************************************** -#define NVIC_COPRO_15_M 0xC0000000 // Coprocessor 15 access mask -#define NVIC_COPRO_15_DENIED 0x00000000 // Coprocessor 15 access denied -#define NVIC_COPRO_15_PRIV 0x40000000 // Coprocessor 15 privileged addess -#define NVIC_COPRO_15_FULL 0xC0000000 // Coprocessor 15 full access -#define NVIC_COPRO_14_M 0x30000000 // Coprocessor 14 access mask -#define NVIC_COPRO_14_DENIED 0x00000000 // Coprocessor 14 access denied -#define NVIC_COPRO_14_PRIV 0x10000000 // Coprocessor 14 privileged addess -#define NVIC_COPRO_14_FULL 0x30000000 // Coprocessor 14 full access -#define NVIC_COPRO_13_M 0x0C000000 // Coprocessor 13 access mask -#define NVIC_COPRO_13_DENIED 0x00000000 // Coprocessor 13 access denied -#define NVIC_COPRO_13_PRIV 0x04000000 // Coprocessor 13 privileged addess -#define NVIC_COPRO_13_FULL 0x0C000000 // Coprocessor 13 full access -#define NVIC_COPRO_12_M 0x03000000 // Coprocessor 12 access mask -#define NVIC_COPRO_12_DENIED 0x00000000 // Coprocessor 12 access denied -#define NVIC_COPRO_12_PRIV 0x01000000 // Coprocessor 12 privileged addess -#define NVIC_COPRO_12_FULL 0x03000000 // Coprocessor 12 full access -#define NVIC_COPRO_11_M 0x00C00000 // Coprocessor 11 access mask -#define NVIC_COPRO_11_DENIED 0x00000000 // Coprocessor 11 access denied -#define NVIC_COPRO_11_PRIV 0x00400000 // Coprocessor 11 privileged addess -#define NVIC_COPRO_11_FULL 0x00C00000 // Coprocessor 11 full access -#define NVIC_COPRO_10_M 0x00300000 // Coprocessor 10 access mask -#define NVIC_COPRO_10_DENIED 0x00000000 // Coprocessor 10 access denied -#define NVIC_COPRO_10_PRIV 0x00100000 // Coprocessor 10 privileged addess -#define NVIC_COPRO_10_FULL 0x00300000 // Coprocessor 10 full access -#define NVIC_COPRO_9_M 0x000C0000 // Coprocessor 9 access mask -#define NVIC_COPRO_9_DENIED 0x00000000 // Coprocessor 9 access denied -#define NVIC_COPRO_9_PRIV 0x00040000 // Coprocessor 9 privileged addess -#define NVIC_COPRO_9_FULL 0x000C0000 // Coprocessor 9 full access -#define NVIC_COPRO_8_M 0x00030000 // Coprocessor 8 access mask -#define NVIC_COPRO_8_DENIED 0x00000000 // Coprocessor 8 access denied -#define NVIC_COPRO_8_PRIV 0x00010000 // Coprocessor 8 privileged addess -#define NVIC_COPRO_8_FULL 0x00030000 // Coprocessor 8 full access -#define NVIC_COPRO_7_M 0x0000C000 // Coprocessor 7 access mask -#define NVIC_COPRO_7_DENIED 0x00000000 // Coprocessor 7 access denied -#define NVIC_COPRO_7_PRIV 0x00004000 // Coprocessor 7 privileged addess -#define NVIC_COPRO_7_FULL 0x0000C000 // Coprocessor 7 full access -#define NVIC_COPRO_6_M 0x00003000 // Coprocessor 6 access mask -#define NVIC_COPRO_6_DENIED 0x00000000 // Coprocessor 6 access denied -#define NVIC_COPRO_6_PRIV 0x00001000 // Coprocessor 6 privileged addess -#define NVIC_COPRO_6_FULL 0x00003000 // Coprocessor 6 full access -#define NVIC_COPRO_5_M 0x00000C00 // Coprocessor 5 access mask -#define NVIC_COPRO_5_DENIED 0x00000000 // Coprocessor 5 access denied -#define NVIC_COPRO_5_PRIV 0x00000400 // Coprocessor 5 privileged addess -#define NVIC_COPRO_5_FULL 0x00000C00 // Coprocessor 5 full access -#define NVIC_COPRO_4_M 0x00000300 // Coprocessor 4 access mask -#define NVIC_COPRO_4_DENIED 0x00000000 // Coprocessor 4 access denied -#define NVIC_COPRO_4_PRIV 0x00000100 // Coprocessor 4 privileged addess -#define NVIC_COPRO_4_FULL 0x00000300 // Coprocessor 4 full access -#define NVIC_COPRO_3_M 0x000000C0 // Coprocessor 3 access mask -#define NVIC_COPRO_3_DENIED 0x00000000 // Coprocessor 3 access denied -#define NVIC_COPRO_3_PRIV 0x00000040 // Coprocessor 3 privileged addess -#define NVIC_COPRO_3_FULL 0x000000C0 // Coprocessor 3 full access -#define NVIC_COPRO_2_M 0x00000030 // Coprocessor 2 access mask -#define NVIC_COPRO_2_DENIED 0x00000000 // Coprocessor 2 access denied -#define NVIC_COPRO_2_PRIV 0x00000010 // Coprocessor 2 privileged addess -#define NVIC_COPRO_2_FULL 0x00000030 // Coprocessor 2 full access -#define NVIC_COPRO_1_M 0x0000000C // Coprocessor 1 access mask -#define NVIC_COPRO_1_DENIED 0x00000000 // Coprocessor 1 access denied -#define NVIC_COPRO_1_PRIV 0x00000004 // Coprocessor 1 privileged addess -#define NVIC_COPRO_1_FULL 0x0000000C // Coprocessor 1 full access -#define NVIC_COPRO_0_M 0x00000003 // Coprocessor 0 access mask -#define NVIC_COPRO_0_DENIED 0x00000000 // Coprocessor 0 access denied -#define NVIC_COPRO_0_PRIV 0x00000001 // Coprocessor 0 privileged addess -#define NVIC_COPRO_0_FULL 0x00000003 // Coprocessor 0 full access - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_TYPE register. -// -//***************************************************************************** -#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions -#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions -#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU -#define NVIC_MPU_TYPE_IREGION_S 16 -#define NVIC_MPU_TYPE_DREGION_S 8 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_CTRL register. -// -//***************************************************************************** -#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults -#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_NUMBER register. -// -//***************************************************************************** -#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access -#define NVIC_MPU_NUMBER_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_BASE register. -// -//***************************************************************************** -#define NVIC_MPU_BASE_ADDR_M 0xFFFFFF00 // Base address -#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid -#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number -#define NVIC_MPU_BASE_ADDR_S 8 -#define NVIC_MPU_BASE_REGION_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_ATTR register. -// -//***************************************************************************** -#define NVIC_MPU_ATTR_ATTRS 0xFFFF0000 // Attributes -#define NVIC_MPU_ATTR_SRD 0x0000FF00 // Sub-region disable -#define NVIC_MPU_ATTR_SZENABLE 0x000000FF // Region size - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_CTRL register. -// -//***************************************************************************** -#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask -#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key -#define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor -#define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request -#define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable -#define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core -#define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping -#define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt -#define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available -#define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up -#define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core -#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping -#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core -#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core -#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_XFER register. -// -//***************************************************************************** -#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read -#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register -#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 -#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 -#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 -#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 -#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 -#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 -#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 -#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 -#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 -#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 -#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 -#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 -#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 -#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 -#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 -#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 -#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register -#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP -#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP -#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP -#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_DATA register. -// -//***************************************************************************** -#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache -#define NVIC_DBG_DATA_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_INT register. -// -//***************************************************************************** -#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault -#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors -#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error -#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state -#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check -#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error -#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault -#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status -#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset -#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending -#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SW_TRIG register. -// -//***************************************************************************** -#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger -#define NVIC_SW_TRIG_INTID_S 0 - -#endif // __HW_NVIC_H__ diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/hw_pwm.h b/Demo/CORTEX_LM3S811_GCC/hw_include/hw_pwm.h deleted file mode 100644 index cc42015ab..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/hw_pwm.h +++ /dev/null @@ -1,260 +0,0 @@ -//***************************************************************************** -// -// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_PWM_H__ -#define __HW_PWM_H__ - -//***************************************************************************** -// -// PWM Module Register Offsets. -// -//***************************************************************************** -#define PWM_O_CTL 0x00000000 // PWM Master Control register -#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync register -#define PWM_O_ENABLE 0x00000008 // PWM Output Enable register -#define PWM_O_INVERT 0x0000000C // PWM Output Inversion register -#define PWM_O_FAULT 0x00000010 // PWM Output Fault register -#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable register -#define PWM_O_RIS 0x00000018 // PWM Interrupt Raw Status reg. -#define PWM_O_ISC 0x0000001C // PWM Interrupt Status register -#define PWM_O_STATUS 0x00000020 // PWM Status register - -//***************************************************************************** -// -// The following define the bit fields in the PWM Master Control register. -// -//***************************************************************************** -#define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2 -#define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1 -#define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0 - -//***************************************************************************** -// -// The following define the bit fields in the PWM Time Base Sync register. -// -//***************************************************************************** -#define PWM_SYNC_SYNC2 0x00000004 // Reset generator 2 counter -#define PWM_SYNC_SYNC1 0x00000002 // Reset generator 1 counter -#define PWM_SYNC_SYNC0 0x00000001 // Reset generator 0 counter - -//***************************************************************************** -// -// The following define the bit fields in the PWM Output Enable register. -// -//***************************************************************************** -#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 pin enable -#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 pin enable -#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 pin enable -#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 pin enable -#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 pin enable -#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 pin enable - -//***************************************************************************** -// -// The following define the bit fields in the PWM Inversion register. -// -//***************************************************************************** -#define PWM_INVERT_PWM5INV 0x00000020 // PWM5 pin invert -#define PWM_INVERT_PWM4INV 0x00000010 // PWM4 pin invert -#define PWM_INVERT_PWM3INV 0x00000008 // PWM3 pin invert -#define PWM_INVERT_PWM2INV 0x00000004 // PWM2 pin invert -#define PWM_INVERT_PWM1INV 0x00000002 // PWM1 pin invert -#define PWM_INVERT_PWM0INV 0x00000001 // PWM0 pin invert - -//***************************************************************************** -// -// The following define the bit fields in the PWM Fault register. -// -//***************************************************************************** -#define PWM_FAULT_FAULT5 0x00000020 // PWM5 pin fault -#define PWM_FAULT_FAULT4 0x00000010 // PWM5 pin fault -#define PWM_FAULT_FAULT3 0x00000008 // PWM5 pin fault -#define PWM_FAULT_FAULT2 0x00000004 // PWM5 pin fault -#define PWM_FAULT_FAULT1 0x00000002 // PWM5 pin fault -#define PWM_FAULT_FAULT0 0x00000001 // PWM5 pin fault - -//***************************************************************************** -// -// PWM Interrupt Register bit definitions. -// -//***************************************************************************** -#define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending - -//***************************************************************************** -// -// The following define the bit fields in the PWM Status register. -// -//***************************************************************************** -#define PWM_STATUS_FAULT 0x00000001 // Fault status - -//***************************************************************************** -// -// PWM Generator standard offsets. -// -//***************************************************************************** -#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base -#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base -#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base - -#define PWM_O_X_CTL 0x00000000 // Gen Control Reg -#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg -#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg -#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg -#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg -#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg -#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg -#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg -#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg -#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg -#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg -#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg -#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg - -//***************************************************************************** -// -// PWM_X Control Register bit definitions. -// -//***************************************************************************** -#define PWM_X_CTL_ENABLE 0x00000001 // Master enable for gen block -#define PWM_X_CTL_MODE 0x00000002 // Counter mode, down or up/down -#define PWM_X_CTL_DEBUG 0x00000004 // Debug mode -#define PWM_X_CTL_LOADUPD 0x00000008 // Update mode for the load reg -#define PWM_X_CTL_CMPAUPD 0x00000010 // Update mode for comp A reg -#define PWM_X_CTL_CMPBUPD 0x00000020 // Update mode for comp B reg - -//***************************************************************************** -// -// PWM_X Interrupt/Trigger Enable Register bit definitions. -// -//***************************************************************************** -#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Int if COUNT = 0 -#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Int if COUNT = LOAD -#define PWM_X_INTEN_INTCMPAU 0x00000004 // Int if COUNT = CMPA U -#define PWM_X_INTEN_INTCMPAD 0x00000008 // Int if COUNT = CMPA D -#define PWM_X_INTEN_INTCMPBU 0x00000010 // Int if COUNT = CMPA U -#define PWM_X_INTEN_INTCMPBD 0x00000020 // Int if COUNT = CMPA D -#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trig if COUNT = 0 -#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trig if COUNT = LOAD -#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trig if COUNT = CMPA U -#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trig if COUNT = CMPA D -#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trig if COUNT = CMPA U -#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trig if COUNT = CMPA D - -//***************************************************************************** -// -// PWM_X Raw Interrupt Status Register bit definitions. -// -//***************************************************************************** -#define PWM_X_RIS_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 int -#define PWM_X_RIS_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD int -#define PWM_X_RIS_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U int -#define PWM_X_RIS_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D int -#define PWM_X_RIS_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U int -#define PWM_X_RIS_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D int - -//***************************************************************************** -// -// PWM_X Interrupt Status Register bit definitions. -// -//***************************************************************************** -#define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received -#define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd -#define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd -#define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd -#define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd -#define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd - -//***************************************************************************** -// -// PWM_X Generator A/B Control Register bit definitions. -// -//***************************************************************************** -#define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0 -#define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD -#define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U -#define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D -#define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U -#define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D - -//***************************************************************************** -// -// PWM_X Generator A/B Control Register action definitions. -// -//***************************************************************************** -#define PWM_GEN_ACT_NONE 0x0 // Do nothing -#define PWM_GEN_ACT_INV 0x1 // Invert the output signal -#define PWM_GEN_ACT_ZERO 0x2 // Set the output signal to zero -#define PWM_GEN_ACT_ONE 0x3 // Set the output signal to one -#define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action -#define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action -#define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action -#define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action -#define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action -#define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action - -//***************************************************************************** -// -// PWM_X Dead Band Control Register bit definitions. -// -//***************************************************************************** -#define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion - -//***************************************************************************** -// -// PWM Register reset values. -// -//***************************************************************************** -#define PWM_RV_CTL 0x00000000 // Master control of the PWM module -#define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators -#define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM - // output pins -#define PWM_RV_INVERT 0x00000000 // Inversion control for - // PWM output pins -#define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM - // output pins -#define PWM_RV_INTEN 0x00000000 // Interrupt enable -#define PWM_RV_RIS 0x00000000 // Raw interrupt status -#define PWM_RV_ISC 0x00000000 // Interrupt status and clearing -#define PWM_RV_STATUS 0x00000000 // Status -#define PWM_RV_X_CTL 0x00000000 // Master control of the PWM - // generator block -#define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable -#define PWM_RV_X_RIS 0x00000000 // Raw interrupt status -#define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing -#define PWM_RV_X_LOAD 0x00000000 // The load value for the counter -#define PWM_RV_X_COUNT 0x00000000 // The current counter value -#define PWM_RV_X_CMPA 0x00000000 // The comparator A value -#define PWM_RV_X_CMPB 0x00000000 // The comparator B value -#define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A -#define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B -#define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator -#define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay - // count -#define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay - // count - -#endif // __HW_PWM_H__ diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/hw_qei.h b/Demo/CORTEX_LM3S811_GCC/hw_include/hw_qei.h deleted file mode 100644 index 864459f48..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/hw_qei.h +++ /dev/null @@ -1,176 +0,0 @@ -//***************************************************************************** -// -// hw_qei.h - Macros used when accessing the QEI hardware. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_QEI_H__ -#define __HW_QEI_H__ - -//***************************************************************************** -// -// The following define the offsets of the QEI registers. -// -//***************************************************************************** -#define QEI_O_CTL 0x00000000 // Configuration and control reg. -#define QEI_O_STAT 0x00000004 // Status register -#define QEI_O_POS 0x00000008 // Current position register -#define QEI_O_MAXPOS 0x0000000C // Maximum position register -#define QEI_O_LOAD 0x00000010 // Velocity timer load register -#define QEI_O_TIME 0x00000014 // Velocity timer register -#define QEI_O_COUNT 0x00000018 // Velocity pulse count register -#define QEI_O_SPEED 0x0000001C // Velocity speed register -#define QEI_O_INTEN 0x00000020 // Interrupt enable register -#define QEI_O_RIS 0x00000024 // Raw interrupt status register -#define QEI_O_ISC 0x00000028 // Interrupt status register - -//***************************************************************************** -// -// The following define the bit fields in the QEI_CTL register. -// -//***************************************************************************** -#define QEI_CTL_STALLEN 0x00001000 // Stall enable -#define QEI_CTL_INVI 0x00000800 // Invert Index input -#define QEI_CTL_INVB 0x00000400 // Invert PhB input -#define QEI_CTL_INVA 0x00000200 // Invert PhA input -#define QEI_CTL_VELDIV_M 0x000001C0 // Velocity predivider mask -#define QEI_CTL_VELDIV_1 0x00000000 // Predivide by 1 -#define QEI_CTL_VELDIV_2 0x00000040 // Predivide by 2 -#define QEI_CTL_VELDIV_4 0x00000080 // Predivide by 4 -#define QEI_CTL_VELDIV_8 0x000000C0 // Predivide by 8 -#define QEI_CTL_VELDIV_16 0x00000100 // Predivide by 16 -#define QEI_CTL_VELDIV_32 0x00000140 // Predivide by 32 -#define QEI_CTL_VELDIV_64 0x00000180 // Predivide by 64 -#define QEI_CTL_VELDIV_128 0x000001C0 // Predivide by 128 -#define QEI_CTL_VELEN 0x00000020 // Velocity enable -#define QEI_CTL_RESMODE 0x00000010 // Position counter reset mode -#define QEI_CTL_CAPMODE 0x00000008 // Edge capture mode -#define QEI_CTL_SIGMODE 0x00000004 // Encoder signaling mode -#define QEI_CTL_SWAP 0x00000002 // Swap input signals -#define QEI_CTL_ENABLE 0x00000001 // QEI enable - -//***************************************************************************** -// -// The following define the bit fields in the QEI_STAT register. -// -//***************************************************************************** -#define QEI_STAT_DIRECTION 0x00000002 // Direction of rotation -#define QEI_STAT_ERROR 0x00000001 // Signalling error detected - -//***************************************************************************** -// -// The following define the bit fields in the QEI_POS register. -// -//***************************************************************************** -#define QEI_POS_M 0xFFFFFFFF // Current encoder position -#define QEI_POS_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_MAXPOS register. -// -//***************************************************************************** -#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum encoder position -#define QEI_MAXPOS_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_LOAD register. -// -//***************************************************************************** -#define QEI_LOAD_M 0xFFFFFFFF // Velocity timer load value -#define QEI_LOAD_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_TIME register. -// -//***************************************************************************** -#define QEI_TIME_M 0xFFFFFFFF // Velocity timer current value -#define QEI_TIME_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_COUNT register. -// -//***************************************************************************** -#define QEI_COUNT_M 0xFFFFFFFF // Encoder running pulse count -#define QEI_COUNT_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_SPEED register. -// -//***************************************************************************** -#define QEI_SPEED_M 0xFFFFFFFF // Encoder pulse count -#define QEI_SPEED_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_INTEN register. -// -//***************************************************************************** -#define QEI_INTEN_ERROR 0x00000008 // Phase error detected -#define QEI_INTEN_DIR 0x00000004 // Direction change -#define QEI_INTEN_TIMER 0x00000002 // Velocity timer expired -#define QEI_INTEN_INDEX 0x00000001 // Index pulse detected - -//***************************************************************************** -// -// The following define the bit fields in the QEI_RIS register. -// -//***************************************************************************** -#define QEI_RIS_ERROR 0x00000008 // Phase error detected -#define QEI_RIS_DIR 0x00000004 // Direction change -#define QEI_RIS_TIMER 0x00000002 // Velocity timer expired -#define QEI_RIS_INDEX 0x00000001 // Index pulse detected - -//***************************************************************************** -// -// The following define the bit fields in the QEI_ISC register. -// -//***************************************************************************** -#define QEI_INT_ERROR 0x00000008 // Phase error detected -#define QEI_INT_DIR 0x00000004 // Direction change -#define QEI_INT_TIMER 0x00000002 // Velocity timer expired -#define QEI_INT_INDEX 0x00000001 // Index pulse detected - -//***************************************************************************** -// -// The following define the reset values for the QEI registers. -// -//***************************************************************************** -#define QEI_RV_CTL 0x00000000 // Configuration and control reg. -#define QEI_RV_STAT 0x00000000 // Status register -#define QEI_RV_POS 0x00000000 // Current position register -#define QEI_RV_MAXPOS 0x00000000 // Maximum position register -#define QEI_RV_LOAD 0x00000000 // Velocity timer load register -#define QEI_RV_TIME 0x00000000 // Velocity timer register -#define QEI_RV_COUNT 0x00000000 // Velocity pulse count register -#define QEI_RV_SPEED 0x00000000 // Velocity speed register -#define QEI_RV_INTEN 0x00000000 // Interrupt enable register -#define QEI_RV_RIS 0x00000000 // Raw interrupt status register -#define QEI_RV_ISC 0x00000000 // Interrupt status register - -#endif // __HW_QEI_H__ diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/hw_ssi.h b/Demo/CORTEX_LM3S811_GCC/hw_include/hw_ssi.h deleted file mode 100644 index e4650af40..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/hw_ssi.h +++ /dev/null @@ -1,120 +0,0 @@ -//***************************************************************************** -// -// hw_ssi.h - Macros used when accessing the SSI hardware. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_SSI_H__ -#define __HW_SSI_H__ - -//***************************************************************************** -// -// The following define the offsets of the SSI registers. -// -//***************************************************************************** -#define SSI_O_CR0 0x00000000 // Control register 0 -#define SSI_O_CR1 0x00000004 // Control register 1 -#define SSI_O_DR 0x00000008 // Data register -#define SSI_O_SR 0x0000000C // Status register -#define SSI_O_CPSR 0x00000010 // Clock prescale register -#define SSI_O_IM 0x00000014 // Int mask set and clear register -#define SSI_O_RIS 0x00000018 // Raw interrupt register -#define SSI_O_MIS 0x0000001C // Masked interrupt register -#define SSI_O_ICR 0x00000020 // Interrupt clear register - -//***************************************************************************** -// -// The following define the bit fields in the SSI Control register 0. -// -//***************************************************************************** -#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate -#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase -#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity -#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask -#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format -#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format -#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format -#define SSI_CR0_DSS 0x0000000F // Data size select -#define SSI_CR0_DSS_4 0x00000003 // 4 bit data -#define SSI_CR0_DSS_5 0x00000004 // 5 bit data -#define SSI_CR0_DSS_6 0x00000005 // 6 bit data -#define SSI_CR0_DSS_7 0x00000006 // 7 bit data -#define SSI_CR0_DSS_8 0x00000007 // 8 bit data -#define SSI_CR0_DSS_9 0x00000008 // 9 bit data -#define SSI_CR0_DSS_10 0x00000009 // 10 bit data -#define SSI_CR0_DSS_11 0x0000000A // 11 bit data -#define SSI_CR0_DSS_12 0x0000000B // 12 bit data -#define SSI_CR0_DSS_13 0x0000000C // 13 bit data -#define SSI_CR0_DSS_14 0x0000000D // 14 bit data -#define SSI_CR0_DSS_15 0x0000000E // 15 bit data -#define SSI_CR0_DSS_16 0x0000000F // 16 bit data - -//***************************************************************************** -// -// The following define the bit fields in the SSI Control register 1. -// -//***************************************************************************** -#define SSI_CR1_SOD 0x00000008 // Slave mode output disable -#define SSI_CR1_MS 0x00000004 // Master or slave mode select -#define SSI_CR1_SSE 0x00000002 // Sync serial port enable -#define SSI_CR1_LBM 0x00000001 // Loopback mode - -//***************************************************************************** -// -// The following define the bit fields in the SSI Status register. -// -//***************************************************************************** -#define SSI_SR_BSY 0x00000010 // SSI busy -#define SSI_SR_RFF 0x00000008 // RX FIFO full -#define SSI_SR_RNE 0x00000004 // RX FIFO not empty -#define SSI_SR_TNF 0x00000002 // TX FIFO not full -#define SSI_SR_TFE 0x00000001 // TX FIFO empty - -//***************************************************************************** -// -// The following define the bit fields in the SSI clock prescale register. -// -//***************************************************************************** -#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale - -//***************************************************************************** -// -// The following define information concerning the SSI Data register. -// -//***************************************************************************** -#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO -#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO - -//***************************************************************************** -// -// The following define the bit fields in the interrupt mask set and clear, -// raw interrupt, masked interrupt, and interrupt clear registers. -// -//***************************************************************************** -#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt -#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt -#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt -#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt - -#endif // __HW_SSI_H__ diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/hw_sysctl.h b/Demo/CORTEX_LM3S811_GCC/hw_include/hw_sysctl.h deleted file mode 100644 index cce5ad214..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/hw_sysctl.h +++ /dev/null @@ -1,409 +0,0 @@ -//***************************************************************************** -// -// hw_sysctl.h - Macros used when accessing the system control hardware. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_SYSCTL_H__ -#define __HW_SYSCTL_H__ - -//***************************************************************************** -// -// The following define the offsets of the system control registers. -// -//***************************************************************************** -#define SYSCTL_DID0 0x400fe000 // Device identification register 0 -#define SYSCTL_DID1 0x400fe004 // Device identification register 1 -#define SYSCTL_DC0 0x400fe008 // Device capabilities register 0 -#define SYSCTL_DC1 0x400fe010 // Device capabilities register 1 -#define SYSCTL_DC2 0x400fe014 // Device capabilities register 2 -#define SYSCTL_DC3 0x400fe018 // Device capabilities register 3 -#define SYSCTL_DC4 0x400fe01C // Device capabilities register 4 -#define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register -#define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register -#define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0 -#define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1 -#define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2 -#define SYSCTL_RIS 0x400fe050 // Raw interrupt status register -#define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register -#define SYSCTL_MISC 0x400fe058 // Interrupt status register -#define SYSCTL_RESC 0x400fe05c // Reset cause register -#define SYSCTL_RCC 0x400fe060 // Run-mode clock config register -#define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register -#define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0 -#define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1 -#define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2 -#define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0 -#define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1 -#define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2 -#define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0 -#define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1 -#define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2 -#define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register -#define SYSCTL_LDOARST 0x400fe160 // LDO reset control register - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DID0 register. -// -//***************************************************************************** -#define SYSCTL_DID0_VER_MASK 0x70000000 // DID0 version mask -#define SYSCTL_DID0_VER_0 0x00000000 // DID0 version 0 -#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask -#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A -#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B -#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask -#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0 -#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DID1 register. -// -//***************************************************************************** -#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask -#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask -#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family -#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask -#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101 -#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102 -#define SYSCTL_DID1_PRTNO_301 0x00110000 // LM3S301 -#define SYSCTL_DID1_PRTNO_310 0x00120000 // LM3S310 -#define SYSCTL_DID1_PRTNO_315 0x00130000 // LM3S315 -#define SYSCTL_DID1_PRTNO_316 0x00140000 // LM3S316 -#define SYSCTL_DID1_PRTNO_328 0x00150000 // LM3S328 -#define SYSCTL_DID1_PRTNO_601 0x00210000 // LM3S601 -#define SYSCTL_DID1_PRTNO_610 0x00220000 // LM3S610 -#define SYSCTL_DID1_PRTNO_611 0x00230000 // LM3S611 -#define SYSCTL_DID1_PRTNO_612 0x00240000 // LM3S612 -#define SYSCTL_DID1_PRTNO_613 0x00250000 // LM3S613 -#define SYSCTL_DID1_PRTNO_615 0x00260000 // LM3S615 -#define SYSCTL_DID1_PRTNO_628 0x00270000 // LM3S628 -#define SYSCTL_DID1_PRTNO_801 0x00310000 // LM3S801 -#define SYSCTL_DID1_PRTNO_811 0x00320000 // LM3S811 -#define SYSCTL_DID1_PRTNO_812 0x00330000 // LM3S812 -#define SYSCTL_DID1_PRTNO_815 0x00340000 // LM3S815 -#define SYSCTL_DID1_PRTNO_828 0x00350000 // LM3S828 -#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask -#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C) -#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C) -#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask -#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC -#define SYSCTL_DID1_PKG_48QFP 0x00000008 // 48-pin QFP -#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant -#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask -#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified) -#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified) -#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified -#define SYSCTL_DID1_PRTNO_SHIFT 16 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC0 register. -// -//***************************************************************************** -#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask -#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2kB of SRAM -#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4kB of SRAM -#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8kB of SRAM -#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask -#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8kB of flash -#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16kB of flash -#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32kB of flash -#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64kB of flash - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC1 register. -// -//***************************************************************************** -#define SYSCTL_DC1_PWM 0x00100000 // PWM module present -#define SYSCTL_DC1_ADC 0x00010000 // ADC module present -#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask -#define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask -#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1Msps ADC -#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500Ksps ADC -#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250Ksps ADC -#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC -#define SYSCTL_DC1_MPU 0x00000080 // Cortex M3 MPU present -#define SYSCTL_DC1_TEMP 0x00000020 // Temperature sensor present -#define SYSCTL_DC1_PLL 0x00000010 // PLL present -#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present -#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present -#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present -#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC2 register. -// -//***************************************************************************** -#define SYSCTL_DC2_COMP2 0x04000000 // Analog comparator 2 present -#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present -#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present -#define SYSCTL_DC2_TIMER2 0x00040000 // Timer 2 present -#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present -#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present -#define SYSCTL_DC2_I2C 0x00001000 // I2C present -#define SYSCTL_DC2_QEI 0x00000100 // QEI present -#define SYSCTL_DC2_SSI 0x00000010 // SSI present -#define SYSCTL_DC2_UART1 0x00000002 // UART 1 present -#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC3 register. -// -//***************************************************************************** -#define SYSCTL_DC3_32KHZ 0x80000000 // 32kHz pin present -#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 pin present -#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 pin present -#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 pin present -#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 pin present -#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present -#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present -#define SYSCTL_DC3_ADC7 0x00800000 // ADC7 pin present -#define SYSCTL_DC3_ADC6 0x00400000 // ADC6 pin present -#define SYSCTL_DC3_ADC5 0x00200000 // ADC5 pin present -#define SYSCTL_DC3_ADC4 0x00100000 // ADC4 pin present -#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 pin present -#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 pin present -#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 pin present -#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 pin present -#define SYSCTL_DC3_C2O 0x00004000 // C2o pin present -#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ pin present -#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- pin present -#define SYSCTL_DC3_C1O 0x00000800 // C1o pin present -#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ pin present -#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present -#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present -#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present -#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present -#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 pin present -#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 pin present -#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 pin present -#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 pin present -#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 pin present -#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 pin present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC4 register. -// -//***************************************************************************** -#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO port E present -#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO port D present -#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present -#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present -#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_PBORCTL register. -// -//***************************************************************************** -#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer -#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset -#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise -#define SYSCTL_PBORCTL_BOR_SH 2 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_LDOPCTL register. -// -//***************************************************************************** -#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask -#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V -#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V -#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V -#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V -#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V -#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V -#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V -#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V -#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V -#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V -#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0, -// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers. -// -//***************************************************************************** -#define SYSCTL_SET0_PWM 0x00100000 // PWM module -#define SYSCTL_SET0_ADC 0x00010000 // ADC module -#define SYSCTL_SET0_ADCSPD_MASK 0x00000F00 // ADC speed mask -#define SYSCTL_SET0_ADCSPD_1M 0x00000300 // 1Msps ADC -#define SYSCTL_SET0_ADCSPD_500K 0x00000200 // 500Ksps ADC -#define SYSCTL_SET0_ADCSPD_250K 0x00000100 // 250Ksps ADC -#define SYSCTL_SET0_ADCSPD_125K 0x00000000 // 125Ksps ADC -#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1, -// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers. -// -//***************************************************************************** -#define SYSCTL_SET1_COMP2 0x04000000 // Analog comparator module 2 -#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1 -#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0 -#define SYSCTL_SET1_TIMER2 0x00040000 // Timer module 2 -#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1 -#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0 -#define SYSCTL_SET1_I2C 0x00001000 // I2C module -#define SYSCTL_SET1_QEI 0x00000100 // QEI module -#define SYSCTL_SET1_SSI 0x00000010 // SSI module -#define SYSCTL_SET1_UART1 0x00000002 // UART module 1 -#define SYSCTL_SET1_UART0 0x00000001 // UART module 0 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2, -// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers. -// -//***************************************************************************** -#define SYSCTL_SET2_GPIOE 0x00000010 // GPIO E module -#define SYSCTL_SET2_GPIOD 0x00000008 // GPIO D module -#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module -#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module -#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and -// SYSCTL_IMS registers. -// -//***************************************************************************** -#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt -#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt -#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int -#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int -#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt -#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt -#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_RESC register. -// -//***************************************************************************** -#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset -#define SYSCTL_RESC_SW 0x00000010 // Software reset -#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset -#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset -#define SYSCTL_RESC_POR 0x00000002 // Power on reset -#define SYSCTL_RESC_EXT 0x00000001 // External reset - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_RCC register. -// -//***************************************************************************** -#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating -#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider -#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2 -#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3 -#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4 -#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5 -#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6 -#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7 -#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8 -#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9 -#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10 -#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11 -#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12 -#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13 -#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14 -#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15 -#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16 -#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider -#define SYSCTL_RCC_USE_PWMDIV 0x00100000 // Use PWM clock divider -#define SYSCTL_RCC_PWMDIV_MASK 0x000E0000 // PWM clock divider -#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2 -#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4 -#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8 -#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16 -#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32 -#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64 -#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down -#define SYSCTL_RCC_OE 0x00001000 // PLL output enable -#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass -#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable -#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc -#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal -#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864MHz crystal -#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4MHz crystal -#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal -#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal -#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal -#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal -#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal -#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal -#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal -#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal -#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal -#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select -#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator -#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // Use the internal oscillator -#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // Use the internal oscillator / 4 -#define SYSCTL_RCC_IOSCVER 0x00000008 // Int. osc. verification timer en -#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en -#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal oscillator disable -#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable -#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field -#define SYSCTL_RCC_PWMDIV_SHIFT 17 // Shift to the PWMDIV field -#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field -#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_PLLCFG register. -// -//***************************************************************************** -#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider -#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1 -#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2 -#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4 -#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier -#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider -#define SYSCTL_PLLCFG_F_SHIFT 5 -#define SYSCTL_PLLCFG_R_SHIFT 0 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_CLKVCLR register. -// -//***************************************************************************** -#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_LDOARST register. -// -//***************************************************************************** -#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device - -#endif // __HW_SYSCTL_H__ diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/hw_timer.h b/Demo/CORTEX_LM3S811_GCC/hw_include/hw_timer.h deleted file mode 100644 index 210c3408e..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/hw_timer.h +++ /dev/null @@ -1,235 +0,0 @@ -//***************************************************************************** -// -// hw_timer.h - Defines and macros used when accessing the timer. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_TIMER_H__ -#define __HW_TIMER_H__ - -//***************************************************************************** -// -// The following define the offsets of the timer registers. -// -//***************************************************************************** -#define TIMER_O_CFG 0x00000000 // Configuration register -#define TIMER_O_TAMR 0x00000004 // TimerA mode register -#define TIMER_O_TBMR 0x00000008 // TimerB mode register -#define TIMER_O_CTL 0x0000000C // Control register -#define TIMER_O_IMR 0x00000018 // Interrupt mask register -#define TIMER_O_RIS 0x0000001C // Interrupt status register -#define TIMER_O_MIS 0x00000020 // Masked interrupt status reg. -#define TIMER_O_ICR 0x00000024 // Interrupt clear register -#define TIMER_O_TAILR 0x00000028 // TimerA interval load register -#define TIMER_O_TBILR 0x0000002C // TimerB interval load register -#define TIMER_O_TAMATCHR 0x00000030 // TimerA match register -#define TIMER_O_TBMATCHR 0x00000034 // TimerB match register -#define TIMER_O_TAPR 0x00000038 // TimerA prescale register -#define TIMER_O_TBPR 0x0000003C // TimerB prescale register -#define TIMER_O_TAPMR 0x00000040 // TimerA prescale match register -#define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register -#define TIMER_O_TAR 0x00000048 // TimerA register -#define TIMER_O_TBR 0x0000004C // TimerB register - -//***************************************************************************** -// -// The following define the reset values of the timer registers. -// -//***************************************************************************** -#define TIMER_RV_CFG 0x00000000 // Configuration register RV -#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV -#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV -#define TIMER_RV_CTL 0x00000000 // Control register RV -#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV -#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV -#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV -#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV -#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV -#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV -#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV -#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV -#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV -#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV -#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV -#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV -#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV -#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_CFG register. -// -//***************************************************************************** -#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask -#define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers -#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC -#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_TnMR register. -// -//***************************************************************************** -#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select -#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time -#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask -#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture -#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic -#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_CTL register. -// -//***************************************************************************** -#define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert -#define TIMER_CTL_TBOTE 0x00002000 // TimerB output trigger enable -#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask -#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges -#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge -#define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge -#define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable -#define TIMER_CTL_TBEN 0x00000100 // TimerB enable -#define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert -#define TIMER_CTL_TAOTE 0x00000020 // TimerA output trigger enable -#define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable -#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask -#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges -#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge -#define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge -#define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable -#define TIMER_CTL_TAEN 0x00000001 // TimerA enable - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_IMR register. -// -//***************************************************************************** -#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask -#define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask -#define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask -#define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask -#define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask -#define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask -#define TIMER_IMR_TATOIM 0x00000001 // TimerA time out interrupt mask - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_RIS register. -// -//***************************************************************************** -#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status -#define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status -#define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status -#define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status -#define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status -#define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status -#define TIMER_RIS_TATORIS 0x00000001 // TimerA time out raw int status - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_MIS register. -// -//***************************************************************************** -#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status -#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status -#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat -#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status -#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status -#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status -#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_ICR register. -// -//***************************************************************************** -#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear -#define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear -#define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear -#define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear -#define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear -#define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear -#define TIMER_ICR_TATOCINT 0x00000001 // TimerA time out interrupt clear - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_TAILR register. -// -//***************************************************************************** -#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode -#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TBILR register. -// -//***************************************************************************** -#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_TAMATCHR register. -// -//***************************************************************************** -#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode -#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TBMATCHR register. -// -//***************************************************************************** -#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TnPR register. -// -//***************************************************************************** -#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TnPMR register. -// -//***************************************************************************** -#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_TAR register. -// -//***************************************************************************** -#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode -#define TIMER_TAR_TARL 0x0000FFFF // TimerA value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TBR register. -// -//***************************************************************************** -#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value - -#endif // __HW_TIMER_H__ diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/hw_types.h b/Demo/CORTEX_LM3S811_GCC/hw_include/hw_types.h deleted file mode 100644 index ec05e5415..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/hw_types.h +++ /dev/null @@ -1,67 +0,0 @@ -//***************************************************************************** -// -// hw_types.h - Common types and macros. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_TYPES_H__ -#define __HW_TYPES_H__ - -//***************************************************************************** -// -// Define a boolean type, and values for true and false. -// -//***************************************************************************** -typedef unsigned char tBoolean; - -#ifndef true -#define true 1 -#endif - -#ifndef false -#define false 0 -#endif - -//***************************************************************************** -// -// Macros for hardware access, both direct and via the bit-band region. -// -//***************************************************************************** -#define HWREG(x) \ - (*((volatile unsigned long *)(x))) -#define HWREGH(x) \ - (*((volatile unsigned short *)(x))) -#define HWREGB(x) \ - (*((volatile unsigned char *)(x))) -#define HWREGBITW(x, b) \ - HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) -#define HWREGBITH(x, b) \ - HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) -#define HWREGBITB(x, b) \ - HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) - -#endif // __HW_TYPES_H__ diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/hw_uart.h b/Demo/CORTEX_LM3S811_GCC/hw_include/hw_uart.h deleted file mode 100644 index 6f421b64e..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/hw_uart.h +++ /dev/null @@ -1,239 +0,0 @@ -//***************************************************************************** -// -// hw_uart.h - Macros and defines used when accessing the UART hardware -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_UART_H__ -#define __HW_UART_H__ - -//***************************************************************************** -// -// UART Register Offsets. -// -//***************************************************************************** -#define UART_O_DR 0x00000000 // Data Register -#define UART_O_RSR 0x00000004 // Receive Status Register (read) -#define UART_O_ECR 0x00000004 // Error Clear Register (write) -#define UART_O_FR 0x00000018 // Flag Register (read only) -#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg -#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg -#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte -#define UART_O_CTL 0x00000030 // Control Register -#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg -#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg -#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register -#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register -#define UART_O_ICR 0x00000044 // Interrupt Clear Register -#define UART_O_PeriphID4 0x00000FD0 // -#define UART_O_PeriphID5 0x00000FD4 // -#define UART_O_PeriphID6 0x00000FD8 // -#define UART_O_PeriphID7 0x00000FDC // -#define UART_O_PeriphID0 0x00000FE0 // -#define UART_O_PeriphID1 0x00000FE4 // -#define UART_O_PeriphID2 0x00000FE8 // -#define UART_O_PeriphID3 0x00000FEC // -#define UART_O_PCellID0 0x00000FF0 // -#define UART_O_PCellID1 0x00000FF4 // -#define UART_O_PCellID2 0x00000FF8 // -#define UART_O_PCellID3 0x00000FFC // - -//***************************************************************************** -// -// Data Register bits -// -//***************************************************************************** -#define UART_DR_OE 0x00000800 // Overrun Error -#define UART_DR_BE 0x00000400 // Break Error -#define UART_DR_PE 0x00000200 // Parity Error -#define UART_DR_FE 0x00000100 // Framing Error -#define UART_DR_DATA_MASK 0x000000FF // UART data - -//***************************************************************************** -// -// Receive Status Register bits -// -//***************************************************************************** -#define UART_RSR_OE 0x00000008 // Overrun Error -#define UART_RSR_BE 0x00000004 // Break Error -#define UART_RSR_PE 0x00000002 // Parity Error -#define UART_RSR_FE 0x00000001 // Framing Error - -//***************************************************************************** -// -// Flag Register bits -// -//***************************************************************************** -#define UART_FR_TXFE 0x00000080 // TX FIFO Empty -#define UART_FR_RXFF 0x00000040 // RX FIFO Full -#define UART_FR_TXFF 0x00000020 // TX FIFO Full -#define UART_FR_RXFE 0x00000010 // RX FIFO Empty -#define UART_FR_BUSY 0x00000008 // UART Busy - -//***************************************************************************** -// -// Integer baud-rate divisor -// -//***************************************************************************** -#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor - -//***************************************************************************** -// -// Fractional baud-rate divisor -// -//***************************************************************************** -#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor - -//***************************************************************************** -// -// Line Control Register High bits -// -//***************************************************************************** -#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select -#define UART_LCR_H_WLEN 0x00000060 // Word length -#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data -#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data -#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data -#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data -#define UART_LCR_H_FEN 0x00000010 // Enable FIFO -#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select -#define UART_LCR_H_EPS 0x00000004 // Even Parity Select -#define UART_LCR_H_PEN 0x00000002 // Parity Enable -#define UART_LCR_H_BRK 0x00000001 // Send Break - -//***************************************************************************** -// -// Control Register bits -// -//***************************************************************************** -#define UART_CTL_RXE 0x00000200 // Receive Enable -#define UART_CTL_TXE 0x00000100 // Transmit Enable -#define UART_CTL_LBE 0x00000080 // Loopback Enable -#define UART_CTL_UARTEN 0x00000001 // UART Enable - -//***************************************************************************** -// -// Interrupt FIFO Level Select Register bits -// -//***************************************************************************** -#define UART_IFLS_RX1_8 0x00000000 // 1/8 Full -#define UART_IFLS_RX2_8 0x00000010 // 1/4 Full -#define UART_IFLS_RX4_8 0x00000020 // 1/2 Full -#define UART_IFLS_RX6_8 0x00000030 // 3/4 Full -#define UART_IFLS_RX7_8 0x00000040 // 7/8 Full -#define UART_IFLS_TX1_8 0x00000000 // 1/8 Full -#define UART_IFLS_TX2_8 0x00000001 // 1/4 Full -#define UART_IFLS_TX4_8 0x00000002 // 1/2 Full -#define UART_IFLS_TX6_8 0x00000003 // 3/4 Full -#define UART_IFLS_TX7_8 0x00000004 // 7/8 Full - -//***************************************************************************** -// -// Interrupt Mask Set/Clear Register bits -// -//***************************************************************************** -#define UART_IM_OEIM 0x00000400 // Overrun Error Interrupt Mask -#define UART_IM_BEIM 0x00000200 // Break Error Interrupt Mask -#define UART_IM_PEIM 0x00000100 // Parity Error Interrupt Mask -#define UART_IM_FEIM 0x00000080 // Framing Error Interrupt Mask -#define UART_IM_RTIM 0x00000040 // Receive Timeout Interrupt Mask -#define UART_IM_TXIM 0x00000020 // Transmit Interrupt Mask -#define UART_IM_RXIM 0x00000010 // Receive Interrupt Mask - -//***************************************************************************** -// -// Raw Interrupt Status Register -// -//***************************************************************************** -#define UART_RIS_OERIS 0x00000400 // Overrun Error Interrupt Status -#define UART_RIS_BERIS 0x00000200 // Break Error Interrupt Status -#define UART_RIS_PERIS 0x00000100 // Parity Error Interrupt Status -#define UART_RIS_FERIS 0x00000080 // Framing Error Interrupt Status -#define UART_RIS_RTRIS 0x00000040 // Receive Timeout Interrupt Status -#define UART_RIS_TXRIS 0x00000020 // Transmit Interrupt Status -#define UART_RIS_RXRIS 0x00000010 // Receive Interrupt Status - -//***************************************************************************** -// -// Masked Interrupt Status Register -// -//***************************************************************************** -#define UART_MIS_OEMIS 0x00000400 // Overrun Error Interrupt Status -#define UART_MIS_BEMIS 0x00000200 // Break Error Interrupt Status -#define UART_MIS_PEMIS 0x00000100 // Parity Error Interrupt Status -#define UART_MIS_FEMIS 0x00000080 // Framing Error Interrupt Status -#define UART_MIS_RTMIS 0x00000040 // Receive Timeout Interrupt Status -#define UART_MIS_TXMIS 0x00000020 // Transmit Interrupt Status -#define UART_MIS_RXMIS 0x00000010 // Receive Interrupt Status - -//***************************************************************************** -// -// Interrupt Clear Register bits -// -//***************************************************************************** -#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear -#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear -#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear -#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear -#define UART_ICR_RTIC 0x00000040 // Receive Timeout Interrupt Clear -#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear -#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear - -#define UART_RSR_ANY (UART_RSR_OE | \ - UART_RSR_BE | \ - UART_RSR_PE | \ - UART_RSR_FE) - -//***************************************************************************** -// -// Reset Values for UART Registers. -// -//***************************************************************************** -#define UART_RV_DR 0x00000000 -#define UART_RV_RSR 0x00000000 -#define UART_RV_ECR 0x00000000 -#define UART_RV_FR 0x00000090 -#define UART_RV_IBRD 0x00000000 -#define UART_RV_FBRD 0x00000000 -#define UART_RV_LCR_H 0x00000000 -#define UART_RV_CTL 0x00000300 -#define UART_RV_IFLS 0x00000012 -#define UART_RV_IM 0x00000000 -#define UART_RV_RIS 0x00000000 -#define UART_RV_MIS 0x00000000 -#define UART_RV_ICR 0x00000000 -#define UART_RV_PeriphID4 0x00000000 -#define UART_RV_PeriphID5 0x00000000 -#define UART_RV_PeriphID6 0x00000000 -#define UART_RV_PeriphID7 0x00000000 -#define UART_RV_PeriphID0 0x00000011 -#define UART_RV_PeriphID1 0x00000000 -#define UART_RV_PeriphID2 0x00000018 -#define UART_RV_PeriphID3 0x00000001 -#define UART_RV_PCellID0 0x0000000D -#define UART_RV_PCellID1 0x000000F0 -#define UART_RV_PCellID2 0x00000005 -#define UART_RV_PCellID3 0x000000B1 - -#endif // __HW_UART_H__ diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/hw_watchdog.h b/Demo/CORTEX_LM3S811_GCC/hw_include/hw_watchdog.h deleted file mode 100644 index 2b013ad84..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/hw_watchdog.h +++ /dev/null @@ -1,116 +0,0 @@ -//***************************************************************************** -// -// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_WATCHDOG_H__ -#define __HW_WATCHDOG_H__ - -//***************************************************************************** -// -// The following define the offsets of the Watchdog Timer registers. -// -//***************************************************************************** -#define WDT_O_LOAD 0x00000000 // Load register -#define WDT_O_VALUE 0x00000004 // Current value register -#define WDT_O_CTL 0x00000008 // Control register -#define WDT_O_ICR 0x0000000C // Interrupt clear register -#define WDT_O_RIS 0x00000010 // Raw interrupt status register -#define WDT_O_MIS 0x00000014 // Masked interrupt status register -#define WDT_O_TEST 0x00000418 // Test register -#define WDT_O_LOCK 0x00000C00 // Lock register -#define WDT_O_PeriphID4 0x00000FD0 // -#define WDT_O_PeriphID5 0x00000FD4 // -#define WDT_O_PeriphID6 0x00000FD8 // -#define WDT_O_PeriphID7 0x00000FDC // -#define WDT_O_PeriphID0 0x00000FE0 // -#define WDT_O_PeriphID1 0x00000FE4 // -#define WDT_O_PeriphID2 0x00000FE8 // -#define WDT_O_PeriphID3 0x00000FEC // -#define WDT_O_PCellID0 0x00000FF0 // -#define WDT_O_PCellID1 0x00000FF4 // -#define WDT_O_PCellID2 0x00000FF8 // -#define WDT_O_PCellID3 0x00000FFC // - -//***************************************************************************** -// -// The following define the bit fields in the WDT_CTL register. -// -//***************************************************************************** -#define WDT_CTL_RESEN 0x00000002 // Enable reset output -#define WDT_CTL_INTEN 0x00000001 // Enable the WDT counter and int - -//***************************************************************************** -// -// The following define the bit fields in the WDT_ISR, WDT_RIS, and WDT_MIS -// registers. -// -//***************************************************************************** -#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired - -//***************************************************************************** -// -// The following define the bit fields in the WDT_TEST register. -// -//***************************************************************************** -#define WDT_TEST_STALL 0x00000100 // Watchdog stall enable -#ifndef DEPRECATED -#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable -#endif - -//***************************************************************************** -// -// The following define the bit fields in the WDT_LOCK register. -// -//***************************************************************************** -#define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked -#define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked -#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer - -//***************************************************************************** -// -// The following define the reset values for the WDT registers. -// -//***************************************************************************** -#define WDT_RV_LOAD 0xFFFFFFFF // Load register -#define WDT_RV_VALUE 0xFFFFFFFF // Current value register -#define WDT_RV_CTL 0x00000000 // Control register -#define WDT_RV_RIS 0x00000000 // Raw interrupt status register -#define WDT_RV_MIS 0x00000000 // Masked interrupt status register -#define WDT_RV_LOCK 0x00000000 // Lock register -#define WDT_RV_PeriphID4 0x00000000 // -#define WDT_RV_PeriphID5 0x00000000 // -#define WDT_RV_PeriphID6 0x00000000 // -#define WDT_RV_PeriphID7 0x00000000 // -#define WDT_RV_PeriphID0 0x00000005 // -#define WDT_RV_PeriphID1 0x00000018 // -#define WDT_RV_PeriphID2 0x00000018 // -#define WDT_RV_PeriphID3 0x00000001 // -#define WDT_RV_PCellID0 0x0000000D // -#define WDT_RV_PCellID1 0x000000F0 // -#define WDT_RV_PCellID2 0x00000005 // -#define WDT_RV_PCellID3 0x000000B1 // - -#endif // __HW_WATCHDOG_H__ diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/i2c.c b/Demo/CORTEX_LM3S811_GCC/hw_include/i2c.c deleted file mode 100644 index b460ad603..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/i2c.c +++ /dev/null @@ -1,972 +0,0 @@ -//***************************************************************************** -// -// i2c.c - Driver for Inter-IC (I2C) bus block. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup i2c_api -//! @{ -// -//***************************************************************************** - -#include "../hw_i2c.h" -#include "../hw_ints.h" -#include "../hw_memmap.h" -#include "../hw_types.h" -#include "debug.h" -#include "i2c.h" -#include "interrupt.h" -#include "sysctl.h" - -//***************************************************************************** -// -//! Initializes the I2C Master block. -//! -//! \param ulBase base address of the I2C Master module -//! \param bFast set up for fast data transfers -//! -//! This function initializes operation of the I2C Master block. Upon -//! successful initialization of the I2C block, this function will have -//! set the bus speed for the master, and will have enabled the I2C Master -//! block. -//! -//! If the parameter \e bFast is \b true, then the master block will be -//! set up to transfer data at 400 kbps; otherwise, it will be set up to -//! transfer data at 100 kbps. -//! -//! The I2C clocking is dependent upon the system clock rate returned by -//! SysCtlClockGet(); if it does not return the correct system clock rate then -//! the I2C clock rate will be incorrect. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_masterinit) || defined(BUILD_ALL) || defined(DOXYGEN) -void -I2CMasterInit(unsigned long ulBase, tBoolean bFast) -{ - unsigned long ulSysClk; - unsigned long ulSCLFreq; - unsigned long ulTPR; - - // - // Check the arguments. - // - ASSERT(ulBase == I2C_MASTER_BASE); - - // - // Must enable the device before doing anything else. - // - I2CMasterEnable(ulBase); - - // - // Get the system clock speed. - // - ulSysClk = SysCtlClockGet(); - - // - // Get the desired SCL speed. - // - if(bFast == true) - { - ulSCLFreq = I2C_SCL_FAST; - } - else - { - ulSCLFreq = I2C_SCL_STANDARD; - } - - // - // Compute the clock divider that achieves the fastest speed less than or - // equal to the desired speed. The numerator is biases to favor a larger - // clock divider so that the resulting clock is always less than or equal - // to the desired clock, never greater. - // - ulTPR = (((ulSysClk + (2 * I2C_MASTER_TPR_SCL * ulSCLFreq) - 1) / - (2 * I2C_MASTER_TPR_SCL * ulSCLFreq)) - 1); - HWREG(ulBase + I2C_MASTER_O_TPR) = ulTPR; -} -#endif - -//***************************************************************************** -// -//! Initializes the I2C Slave block. -//! -//! \param ulBase base address of the I2C Slave module -//! \param ucSlaveAddr 7-bit slave address -//! -//! This function initializes operation of the I2C Slave block. Upon -//! successful initialization of the I2C blocks, this function will have -//! set the slave address and have enabled the I2C Slave block. -//! -//! The parameter \e ucSlaveAddr is the value that will be compared -//! against the slave address sent by an I2C master. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_slaveinit) || defined(BUILD_ALL) || defined(DOXYGEN) -void -I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_SLAVE_BASE); - ASSERT(!(ucSlaveAddr & 0x80)); - - // - // Must enable the device before doing anything else. - // - I2CSlaveEnable(ulBase); - - // - // Set up the slave address. - // - HWREG(ulBase + I2C_SLAVE_O_OAR) = ucSlaveAddr; -} -#endif - -//***************************************************************************** -// -//! Enables the I2C Master block. -//! -//! \param ulBase base address of the I2C Master module -//! -//! This will enable operation of the I2C Master block. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_masterenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -I2CMasterEnable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_MASTER_BASE); - - // - // Enable the master block. - // - HWREG(ulBase + I2C_MASTER_O_CR) |= I2C_MASTER_CR_MFE; -} -#endif - -//***************************************************************************** -// -//! Enables the I2C Slave block. -//! -//! \param ulBase base address of the I2C Slave module -//! -//! This will enable operation of the I2C Slave block. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_slaveenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -I2CSlaveEnable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_SLAVE_BASE); - - // - // Enable the clock to the slave block. - // - HWREG(ulBase - I2C_O_SLAVE + I2C_MASTER_O_CR) |= I2C_MASTER_CR_SFE; - - // - // Enable the slave. - // - HWREG(ulBase + I2C_SLAVE_O_CSR) = I2C_SLAVE_CSR_DA; -} -#endif - -//***************************************************************************** -// -//! Disables the I2C master block. -//! -//! \param ulBase base address of the I2C Master module -//! -//! This will disable operation of the I2C master block. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_masterdisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -I2CMasterDisable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_MASTER_BASE); - - // - // Disable the master block. - // - HWREG(ulBase + I2C_MASTER_O_CR) &= ~(I2C_MASTER_CR_MFE); -} -#endif - -//***************************************************************************** -// -//! Disables the I2C slave block. -//! -//! \param ulBase base address of the I2C Slave module -//! -//! This will disable operation of the I2C slave block. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_slavedisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -I2CSlaveDisable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_SLAVE_BASE); - - // - // Disable the slave. - // - HWREG(ulBase + I2C_SLAVE_O_CSR) = 0; - - // - // Disable the clock to the slave block. - // - HWREG(ulBase - I2C_O_SLAVE + I2C_MASTER_O_CR) &= ~(I2C_MASTER_CR_SFE); -} -#endif - -//***************************************************************************** -// -//! Registers an interrupt handler for the I2C module -//! -//! \param ulBase base address of the I2C module -//! \param pfnHandler is a pointer to the function to be called when the -//! synchronous serial interface interrupt occurs. -//! -//! This sets the handler to be called when an I2C interrupt occurs. This -//! will enable the global interrupt in the interrupt controller; specific I2C -//! interrupts must be enabled via I2CMasterIntEnable() and -//! I2CSlaveIntEnable(). If necessary, it is the interrupt handler's -//! responsibility to clear the interrupt source via I2CMasterIntClear() and -//! I2CSlaveIntClear(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -I2CIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_MASTER_BASE); - - // - // Register the interrupt handler, returning an error if an error occurs. - // - IntRegister(INT_I2C, pfnHandler); - - // - // Enable the I2C interrupt. - // - IntEnable(INT_I2C); -} -#endif - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the I2C module. -//! -//! \param ulBase base address of the I2C module -//! -//! This function will clear the handler to be called when an I2C -//! interrupt occurs. This will also mask off the interrupt in the interrupt -//! controller so that the interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -I2CIntUnregister(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_MASTER_BASE); - - // - // Disable the interrupt. - // - IntDisable(INT_I2C); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_I2C); -} -#endif - -//***************************************************************************** -// -//! Enables the I2C Master interrupt. -//! -//! \param ulBase base address of the I2C Master module -//! -//! Enables the I2C Master interrupt source. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_masterintenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -I2CMasterIntEnable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_MASTER_BASE); - - // - // Enable the master interrupt. - // - HWREG(ulBase + I2C_MASTER_O_IMR) = 1; -} -#endif - -//***************************************************************************** -// -//! Enables the I2C Slave interrupt. -//! -//! \param ulBase base address of the I2C Slave module -//! -//! Enables the I2C Slave interrupt source. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_slaveintenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -I2CSlaveIntEnable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_SLAVE_BASE); - - // - // Enable the slave interrupt. - // - HWREG(ulBase + I2C_SLAVE_O_IM) = 1; -} -#endif - -//***************************************************************************** -// -//! Disables the I2C Master interrupt. -//! -//! \param ulBase base address of the I2C Master module -//! -//! Disables the I2C Master interrupt source. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_masterintdisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -I2CMasterIntDisable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_MASTER_BASE); - - // - // Disable the master interrupt. - // - HWREG(ulBase + I2C_MASTER_O_IMR) = 0; -} -#endif - -//***************************************************************************** -// -//! Disables the I2C Slave interrupt. -//! -//! \param ulBase base address of the I2C Slave module -//! -//! Disables the I2C Slave interrupt source. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_slaveintdisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -I2CSlaveIntDisable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_SLAVE_BASE); - - // - // Disable the slave interrupt. - // - HWREG(ulBase + I2C_SLAVE_O_IM) = 0; -} -#endif - -//***************************************************************************** -// -//! Gets the current I2C Master interrupt status. -//! -//! \param ulBase base address of the I2C Master module -//! \param bMasked is false if the raw interrupt status is requested and -//! true if the masked interrupt status is requested. -//! -//! This returns the interrupt status for the I2C Master module. -//! Either the raw interrupt status or the status of interrupts that are -//! allowed to reflect to the processor can be returned. -//! -//! \return The current interrupt status, returned as \b true if active -//! or \b false if not active. -// -//***************************************************************************** -#if defined(GROUP_masterintstatus) || defined(BUILD_ALL) || defined(DOXYGEN) -tBoolean -I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_MASTER_BASE); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return((HWREG(ulBase + I2C_MASTER_O_MIS)) ? true : false); - } - else - { - return((HWREG(ulBase + I2C_MASTER_O_RIS)) ? true : false); - } -} -#endif - -//***************************************************************************** -// -//! Gets the current I2C Slave interrupt status. -//! -//! \param ulBase base address of the I2C Slave module -//! \param bMasked is false if the raw interrupt status is requested and -//! true if the masked interrupt status is requested. -//! -//! This returns the interrupt status for the I2C Slave module. -//! Either the raw interrupt status or the status of interrupts that are -//! allowed to reflect to the processor can be returned. -//! -//! \return The current interrupt status, returned as \b true if active -//! or \b false if not active. -// -//***************************************************************************** -#if defined(GROUP_slaveintstatus) || defined(BUILD_ALL) || defined(DOXYGEN) -tBoolean -I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_SLAVE_BASE); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return((HWREG(ulBase + I2C_SLAVE_O_MIS)) ? true : false); - } - else - { - return((HWREG(ulBase + I2C_SLAVE_O_RIS)) ? true : false); - } -} -#endif - -//***************************************************************************** -// -//! Clears I2C Master interrupt sources. -//! -//! \param ulBase base address of the I2C Master module -//! -//! The I2C Master interrupt source is cleared, so that it no longer asserts. -//! This must be done in the interrupt handler to keep it from being called -//! again immediately upon exit. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_masterintclear) || defined(BUILD_ALL) || defined(DOXYGEN) -void -I2CMasterIntClear(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_MASTER_BASE); - - // - // Clear the I2C master interrupt source. - // - HWREG(ulBase + I2C_MASTER_O_MICR) = I2C_MASTER_MICR_IC; - - // - // Workaround for I2C master interrupt clear errata for rev B Stellaris - // devices. For later devices, this write is ignored and therefore - // harmless (other than the slight performance hit). - // - HWREG(ulBase + I2C_MASTER_O_MIS) = I2C_MASTER_MICR_IC; -} -#endif - -//***************************************************************************** -// -//! Clears I2C Slave interrupt sources. -//! -//! \param ulBase base address of the I2C Slave module -//! -//! The I2C Slave interrupt source is cleared, so that it no longer asserts. -//! This must be done in the interrupt handler to keep it from being called -//! again immediately upon exit. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_slaveintclear) || defined(BUILD_ALL) || defined(DOXYGEN) -void -I2CSlaveIntClear(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_SLAVE_BASE); - - // - // Clear the I2C slave interrupt source. - // - HWREG(ulBase + I2C_SLAVE_O_SICR) = I2C_SLAVE_SICR_IC; -} -#endif - -//***************************************************************************** -// -//! Sets the address that the I2C Master will place on the bus. -//! -//! \param ulBase base address of the I2C Master module -//! \param ucSlaveAddr 7-bit slave address -//! \param bReceive flag indicating the type of communication with the slave -//! -//! This function will set the address that the I2C Master will place on the -//! bus when initiating a transaction. When the parameter \e bReceive is set -//! to \b true, the address will indicate that the I2C Master is initiating -//! a read from the slave; otherwise the address will indicate that the I2C -//! Master is initiating a write to the slave. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_masterslaveaddrset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -I2CMasterSlaveAddrSet(unsigned long ulBase, unsigned char ucSlaveAddr, - tBoolean bReceive) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_MASTER_BASE); - ASSERT(!(ucSlaveAddr & 0x80)); - - // - // Set the address of the slave with which the master will communicate. - // - HWREG(ulBase + I2C_MASTER_O_SA) = (ucSlaveAddr << 1) | bReceive; -} -#endif - -//***************************************************************************** -// -//! Indicates whether or not the I2C Master is busy. -//! -//! \param ulBase base address of the I2C Master module -//! -//! This function returns an indication of whether or not the I2C Master is -//! busy transmitting or receiving data. -//! -//! \return Returns \b true if the I2C Master is busy; otherwise, returns -//! \b false. -// -//***************************************************************************** -#if defined(GROUP_masterbusy) || defined(BUILD_ALL) || defined(DOXYGEN) -tBoolean -I2CMasterBusy(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_MASTER_BASE); - - // - // Return the busy status. - // - if(HWREG(ulBase + I2C_MASTER_O_CS) & I2C_MASTER_CS_BUSY) - { - return(true); - } - else - { - return(false); - } -} -#endif - -//***************************************************************************** -// -//! Indicates whether or not the I2C bus is busy. -//! -//! \param ulBase base address of the I2C Master module -//! -//! This function returns an indication of whether or not the I2C bus is -//! busy. This function can be used in a multi-master environment to -//! determine if another master is currently using the bus. -//! -//! \return Returns \b true if the I2C bus is busy; otherwise, returns -//! \b false. -// -//***************************************************************************** -#if defined(GROUP_masterbusbusy) || defined(BUILD_ALL) || defined(DOXYGEN) -tBoolean -I2CMasterBusBusy(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_MASTER_BASE); - - // - // Return the bus busy status. - // - if(HWREG(ulBase + I2C_MASTER_O_CS) & I2C_MASTER_CS_BUS_BUSY) - { - return(true); - } - else - { - return(false); - } -} -#endif - -//***************************************************************************** -// -//! Controls the state of the I2C Master module. -//! -//! \param ulBase base address of the I2C Master module -//! \param ulCmd command to be issued to the I2C Master module -//! -//! This function is used to control the state of the Master module send and -//! receive operations. The parameter \e ucCmd can be one of the following -//! values: -//! -//! - I2C_MASTER_CMD_SINGLE_SEND -//! - I2C_MASTER_CMD_SINGLE_RECEIVE -//! - I2C_MASTER_CMD_BURST_SEND_START -//! - I2C_MASTER_CMD_BURST_SEND_CONT -//! - I2C_MASTER_CMD_BURST_SEND_FINISH -//! - I2C_MASTER_CMD_BURST_SEND_ERROR_STOP -//! - I2C_MASTER_CMD_BURST_RECEIVE_START -//! - I2C_MASTER_CMD_BURST_RECEIVE_CONT -//! - I2C_MASTER_CMD_BURST_RECEIVE_FINISH -//! - I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_mastercontrol) || defined(BUILD_ALL) || defined(DOXYGEN) -void -I2CMasterControl(unsigned long ulBase, unsigned long ulCmd) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_MASTER_BASE); - ASSERT((ulCmd == I2C_MASTER_CMD_SINGLE_SEND) || - (ulCmd == I2C_MASTER_CMD_SINGLE_RECEIVE) || - (ulCmd == I2C_MASTER_CMD_BURST_SEND_START) || - (ulCmd == I2C_MASTER_CMD_BURST_SEND_CONT) || - (ulCmd == I2C_MASTER_CMD_BURST_SEND_FINISH) || - (ulCmd == I2C_MASTER_CMD_BURST_SEND_ERROR_STOP) || - (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_START) || - (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_CONT) || - (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_FINISH) || - (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP)); - - // - // Send the command. - // - HWREG(ulBase + I2C_MASTER_O_CS) = ulCmd; -} -#endif - -//***************************************************************************** -// -//! Gets the error status of the I2C Master module. -//! -//! \param ulBase base address of the I2C Master module -//! -//! This function is used to obtain the error status of the Master module -//! send and receive operations. It returns one of the following values: -//! -//! - I2C_MASTER_ERR_NONE -//! - I2C_MASTER_ERR_ADDR_ACK -//! - I2C_MASTER_ERR_DATA_ACK -//! - I2C_MASTER_ERR_ARB_LOST -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_mastererr) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -I2CMasterErr(unsigned long ulBase) -{ - unsigned long ulErr; - - // - // Check the arguments. - // - ASSERT(ulBase == I2C_MASTER_BASE); - - // - // Get the raw error state - // - ulErr = HWREG(ulBase + I2C_MASTER_O_CS); - - // - // If the I2C master is busy, then all the other bit are invalid, and - // don't have an error to report. - // - if(ulErr & I2C_MASTER_CS_BUSY) - { - return(I2C_MASTER_ERR_NONE); - } - - // - // Check for errors. - // - if(ulErr & I2C_MASTER_CS_ERROR) - { - return(ulErr & (I2C_MASTER_CS_ERR_MASK)); - } - else - { - return(I2C_MASTER_ERR_NONE); - } -} -#endif - -//***************************************************************************** -// -//! Transmits a byte from the I2C Master. -//! -//! \param ulBase base address of the I2C Master module -//! \param ucData data to be transmitted from the I2C Master -//! -//! This function will place the supplied data into I2C Master Data Register. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_masterdataput) || defined(BUILD_ALL) || defined(DOXYGEN) -void -I2CMasterDataPut(unsigned long ulBase, unsigned char ucData) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_MASTER_BASE); - - // - // Write the byte. - // - HWREG(ulBase + I2C_MASTER_O_DR) = ucData; -} -#endif - -//***************************************************************************** -// -//! Receives a byte that has been sent to the I2C Master. -//! -//! \param ulBase base address of the I2C Master module -//! -//! This function reads a byte of data from the I2C Master Data Register. -//! -//! \return Returns the byte received from by the I2C Master, cast as an -//! unsigned long. -// -//***************************************************************************** -#if defined(GROUP_masterdataget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -I2CMasterDataGet(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_MASTER_BASE); - - // - // Read a byte. - // - return(HWREG(ulBase + I2C_MASTER_O_DR)); -} -#endif - -//***************************************************************************** -// -//! Gets the I2C Slave module status -//! -//! \param ulBase base address of the I2C Slave module -//! -//! This function will return the action requested from a master, if any. The -//! possible values returned are: -//! -//! - I2C_SLAVE_ACT_NONE -//! - I2C_SLAVE_ACT_RREQ -//! - I2C_SLAVE_ACT_TREQ -//! -//! where I2C_SLAVE_ACT_NONE means that no action has been requested of the -//! I2C Slave module, I2C_SLAVE_ACT_RREQ means that an I2C master has sent -//! data to the I2C Slave module, and I2C_SLAVE_ACT_TREQ means that an I2C -//! master has requested that the I2C Slave module send data. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_slavestatus) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -I2CSlaveStatus(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_SLAVE_BASE); - - // - // Return the slave status. - // - return(HWREG(ulBase + I2C_SLAVE_O_CSR)); -} -#endif - -//***************************************************************************** -// -//! Transmits a byte from the I2C Slave. -//! -//! \param ulBase base address of the I2C Slave module -//! \param ucData data to be transmitted from the I2C Slave -//! -//! This function will place the supplied data into I2C Slave Data Register. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_slavedataput) || defined(BUILD_ALL) || defined(DOXYGEN) -void -I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_SLAVE_BASE); - - // - // Write the byte. - // - HWREG(ulBase + I2C_SLAVE_O_DR) = ucData; -} -#endif - -//***************************************************************************** -// -//! Receives a byte that has been sent to the I2C Slave. -//! -//! \param ulBase base address of the I2C Slave module -//! -//! This function reads a byte of data from the I2C Slave Data Register. -//! -//! \return Returns the byte received from by the I2C Slave, cast as an -//! unsigned long. -// -//***************************************************************************** -#if defined(GROUP_slavedataget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -I2CSlaveDataGet(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_SLAVE_BASE); - - // - // Read a byte. - // - return(HWREG(ulBase + I2C_SLAVE_O_DR)); -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/i2c.h b/Demo/CORTEX_LM3S811_GCC/hw_include/i2c.h deleted file mode 100644 index bfe8c8563..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/i2c.h +++ /dev/null @@ -1,137 +0,0 @@ -//***************************************************************************** -// -// i2c.h - Prototypes for the I2C Driver. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __I2C_H__ -#define __I2C_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Defines for the API. -// -//***************************************************************************** -//***************************************************************************** -// -// Interrupt defines. -// -//***************************************************************************** -#define I2C_INT_MASTER 0x00000001 -#define I2C_INT_SLAVE 0x00000002 - -//***************************************************************************** -// -// I2C Master commands. -// -//***************************************************************************** -#define I2C_MASTER_CMD_SINGLE_SEND \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_SINGLE_RECEIVE \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_SEND_START \ - (I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_SEND_CONT \ - (I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_SEND_FINISH \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ - (I2C_MASTER_CS_STOP) -#define I2C_MASTER_CMD_BURST_RECEIVE_START \ - (I2C_MASTER_CS_ACK | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ - (I2C_MASTER_CS_ACK | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) - -//***************************************************************************** -// -// I2C Master error status. -// -//***************************************************************************** -#define I2C_MASTER_ERR_NONE 0 -#define I2C_MASTER_ERR_ADDR_ACK 0x00000004 -#define I2C_MASTER_ERR_DATA_ACK 0x00000008 -#define I2C_MASTER_ERR_ARB_LOST 0x00000010 - -//***************************************************************************** -// -// I2C Slave action requests -// -//***************************************************************************** -#define I2C_SLAVE_ACT_NONE 0 -#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data -#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data - -//***************************************************************************** -// Miscellaneous I2C driver definitions. -//***************************************************************************** -#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void)); -extern void I2CIntUnregister(unsigned long ulBase); -extern tBoolean I2CMasterBusBusy(unsigned long ulBase); -extern tBoolean I2CMasterBusy(unsigned long ulBase); -extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd); -extern unsigned long I2CMasterDataGet(unsigned long ulBase); -extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData); -extern void I2CMasterDisable(unsigned long ulBase); -extern void I2CMasterEnable(unsigned long ulBase); -extern unsigned long I2CMasterErr(unsigned long ulBase); -extern void I2CMasterInit(unsigned long ulBase, tBoolean bFast); -extern void I2CMasterIntClear(unsigned long ulBase); -extern void I2CMasterIntDisable(unsigned long ulBase); -extern void I2CMasterIntEnable(unsigned long ulBase); -extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void I2CMasterSlaveAddrSet(unsigned long ulBase, - unsigned char ucSlaveAddr, - tBoolean bReceive); -extern unsigned long I2CSlaveDataGet(unsigned long ulBase); -extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData); -extern void I2CSlaveDisable(unsigned long ulBase); -extern void I2CSlaveEnable(unsigned long ulBase); -extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr); -extern void I2CSlaveIntClear(unsigned long ulBase); -extern void I2CSlaveIntDisable(unsigned long ulBase); -extern void I2CSlaveIntEnable(unsigned long ulBase); -extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked); -extern unsigned long I2CSlaveStatus(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __I2C_H__ diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/interrupt.c b/Demo/CORTEX_LM3S811_GCC/hw_include/interrupt.c deleted file mode 100644 index 7224a05d8..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/interrupt.c +++ /dev/null @@ -1,552 +0,0 @@ -//***************************************************************************** -// -// interrupt.c - Driver for the NVIC Interrupt Controller. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup interrupt_api -//! @{ -// -//***************************************************************************** - -#include "../hw_ints.h" -#include "../hw_nvic.h" -#include "../hw_types.h" -#include "cpu.h" -#include "debug.h" -#include "interrupt.h" - -//***************************************************************************** -// -// This is a mapping between priority grouping encodings and the number of -// preemption priority bits. -// -//***************************************************************************** -#if defined(GROUP_pulpriority) || defined(BUILD_ALL) -const unsigned long g_pulPriority[] = -{ - NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6, - NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4, NVIC_APINT_PRIGROUP_5_3, - NVIC_APINT_PRIGROUP_6_2, NVIC_APINT_PRIGROUP_7_1 -}; -#else -extern const unsigned long g_pulPriority[]; -#endif - -//***************************************************************************** -// -// This is a mapping between interrupt number and the register that contains -// the priority encoding for that interrupt. -// -//***************************************************************************** -#if defined(GROUP_pulregs) || defined(BUILD_ALL) -const unsigned long g_pulRegs[12] = -{ - 0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1, - NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7 -}; -#else -extern const unsigned long g_pulRegs[12]; -#endif - -//***************************************************************************** -// -//! \internal -//! The default interrupt handler. -//! -//! This is the default interrupt handler for all interrupts. It simply loops -//! forever so that the system state is preserved for observation by a -//! debugger. Since interrupts should be disabled before unregistering the -//! corresponding handler, this should never be called. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_defaulthandler) || defined(BUILD_ALL) -void -IntDefaultHandler(void) -{ - // - // Go into an infinite loop. - // - while(1) - { - } -} -#else -extern void IntDefaultHandler(void); -#endif - -//***************************************************************************** -// -// The processor vector table. -// -// This contains a list of the handlers for the various interrupt sources in -// the system. The layout of this list is defined by the hardware; assertion -// of an interrupt causes the processor to start executing directly at the -// address given in the corresponding location in this list. -// -//***************************************************************************** -#if defined(GROUP_vtable) || defined(BUILD_ALL) -#ifdef ewarm -__no_init void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) @ "VTABLE"; -#else -__attribute__((section("vtable"))) -void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void); -#endif -#else -extern void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void); -#endif - -//***************************************************************************** -// -//! Enables the processor interrupt. -//! -//! Allows the processor to respond to interrupts. This does not affect the -//! set of interrupts enabled in the interrupt controller; it just gates the -//! single interrupt from the controller to the processor. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_masterenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -IntMasterEnable(void) -{ - // - // Enable processor interrupts. - // - CPUcpsie(); -} -#endif - -//***************************************************************************** -// -//! Disables the processor interrupt. -//! -//! Prevents the processor from receiving interrupts. This does not affect the -//! set of interrupts enabled in the interrupt controller; it just gates the -//! single interrupt from the controller to the processor. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_masterdisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -IntMasterDisable(void) -{ - // - // Disable processor interrupts. - // - CPUcpsid(); -} -#endif - -//***************************************************************************** -// -//! Registers a function to be called when an interrupt occurs. -//! -//! \param ulInterrupt specifies the interrupt in question. -//! \param pfnHandler is a pointer to the function to be called. -//! -//! This function is used to specify the handler function to be called when the -//! given interrupt is asserted to the processor. When the interrupt occurs, -//! if it is enabled (via IntEnable()), the handler function will be called in -//! interrupt context. Since the handler function can preempt other code, care -//! must be taken to protect memory or peripherals that are accessed by the -//! handler and other non-handler code. -//! -//! \note The use of this function (directly or indirectly via a peripheral -//! driver interrupt register function) moves the interrupt vector table from -//! flash to SRAM. Therefore, care must be taken when linking the application -//! to ensure that the SRAM vector table is located at the beginning of SRAM; -//! otherwise NVIC will not look in the correct portion of memory for the -//! vector table (it requires the vector table be on a 1 kB memory alignment). -//! Normally, the SRAM vector table is so placed via the use of linker scripts; -//! some tool chains, such as the evaluation version of RV-MDK, do not support -//! linker scripts and therefore will not produce a valid executable. See the -//! discussion of compile-time versus run-time interrupt handler registration -//! in the introduction to this chapter. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_register) || defined(BUILD_ALL) || defined(DOXYGEN) -void -IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)) -{ - unsigned long ulIdx; - - // - // Check the arguments. - // - ASSERT(ulInterrupt < NUM_INTERRUPTS); - - // - // Make sure that the RAM vector table is correctly aligned. - // - ASSERT(((unsigned long)g_pfnRAMVectors & 0x000003ff) == 0); - - // - // See if the RAM vector table has been initialized. - // - if(HWREG(NVIC_VTABLE) != (unsigned long)g_pfnRAMVectors) - { - // - // Copy the vector table from the beginning of FLASH to the RAM vector - // table. - // - for(ulIdx = 0; ulIdx < NUM_INTERRUPTS; ulIdx++) - { - g_pfnRAMVectors[ulIdx] = (void (*)(void))HWREG(ulIdx * 4); - } - - // - // Point NVIC at the RAM vector table. - // - HWREG(NVIC_VTABLE) = (unsigned long)g_pfnRAMVectors; - } - - // - // Save the interrupt handler. - // - g_pfnRAMVectors[ulInterrupt] = pfnHandler; -} -#endif - -//***************************************************************************** -// -//! Unregisters the function to be called when an interrupt occurs. -//! -//! \param ulInterrupt specifies the interrupt in question. -//! -//! This function is used to indicate that no handler should be called when the -//! given interrupt is asserted to the processor. The interrupt source will be -//! automatically disabled (via IntDisable()) if necessary. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_unregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -IntUnregister(unsigned long ulInterrupt) -{ - // - // Check the arguments. - // - ASSERT(ulInterrupt < NUM_INTERRUPTS); - - // - // Reset the interrupt handler. - // - g_pfnRAMVectors[ulInterrupt] = IntDefaultHandler; -} -#endif - -//***************************************************************************** -// -//! Sets the priority grouping of the interrupt controller. -//! -//! \param ulBits specifies the number of bits of preemptable priority. -//! -//! This function specifies the split between preemptable priority levels and -//! subpriority levels in the interrupt priority specification. The range of -//! the grouping values are dependent upon the hardware implementation; on -//! the Stellaris family it can range from 0 to 3. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_prioritygroupingset) || defined(BUILD_ALL) || \ - defined(DOXYGEN) -void -IntPriorityGroupingSet(unsigned long ulBits) -{ - // - // Check the arguments. - // - ASSERT(ulBits < NUM_PRIORITY_BITS); - - // - // Set the priority grouping. - // - HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pulPriority[ulBits]; -} -#endif - -//***************************************************************************** -// -//! Gets the priority grouping of the interrupt controller. -//! -//! This function returns the split between preemptable priority levels and -//! subpriority levels in the interrupt priority specification. -//! -//! \return The number of bits of preemptable priority. -// -//***************************************************************************** -#if defined(GROUP_prioritygroupingget) || defined(BUILD_ALL) || \ - defined(DOXYGEN) -unsigned long -IntPriorityGroupingGet(void) -{ - unsigned long ulLoop, ulValue; - - // - // Read the priority grouping. - // - ulValue = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M; - - // - // Loop through the priority grouping values. - // - for(ulLoop = 0; ulLoop < 8; ulLoop++) - { - // - // Stop looping if this value matches. - // - if(ulValue == g_pulPriority[ulLoop]) - { - break; - } - } - - // - // Return the number of priority bits. - // - return(ulLoop); -} -#endif - -//***************************************************************************** -// -//! Sets the priority of an interrupt. -//! -//! \param ulInterrupt specifies the interrupt in question. -//! \param ucPriority specifies the priority of the interrupt. -//! -//! This function is used to set the priority of an interrupt. When multiple -//! interrupts are asserted simultaneously, the ones with the highest priority -//! are processed before the lower priority interrupts. Smaller numbers -//! correspond to higher interrupt priorities; priority 0 is the highest -//! interrupt priority. -//! -//! The hardware priority mechanism will only look at the upper N bits of the -//! priority level (where N is 3 for the Stellaris family), so any -//! prioritization must be performed in those bits. The remaining bits can be -//! used to sub-prioritize the interrupt sources, and may be used by the -//! hardware priority mechanism on a future part. This arrangement allows -//! priorities to migrate to different NVIC implementations without changing -//! the gross prioritization of the interrupts. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_priorityset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -IntPrioritySet(unsigned long ulInterrupt, unsigned char ucPriority) -{ - unsigned long ulTemp; - - // - // Check the arguments. - // - ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS)); - - // - // Set the interrupt priority. - // - ulTemp = HWREG(g_pulRegs[ulInterrupt >> 2]); - ulTemp &= ~(0xFF << (8 * (ulInterrupt & 3))); - ulTemp |= ucPriority << (8 * (ulInterrupt & 3)); - HWREG(g_pulRegs[ulInterrupt >> 2]) = ulTemp; -} -#endif - -//***************************************************************************** -// -//! Gets the priority of an interrupt. -//! -//! \param ulInterrupt specifies the interrupt in question. -//! -//! This function gets the priority of an interrupt. See IntPrioritySet() for -//! a definition of the priority value. -//! -//! \return Returns the interrupt priority, or -1 if an invalid interrupt was -//! specified. -// -//***************************************************************************** -#if defined(GROUP_priorityget) || defined(BUILD_ALL) || defined(DOXYGEN) -long -IntPriorityGet(unsigned long ulInterrupt) -{ - // - // Check the arguments. - // - ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS)); - - // - // Return the interrupt priority. - // - return((HWREG(g_pulRegs[ulInterrupt >> 2]) >> (8 * (ulInterrupt & 3))) & - 0xFF); -} -#endif - -//***************************************************************************** -// -//! Enables an interrupt. -//! -//! \param ulInterrupt specifies the interrupt to be enabled. -//! -//! The specified interrupt is enabled in the interrupt controller. Other -//! enables for the interrupt (such as at the peripheral level) are unaffected -//! by this function. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -IntEnable(unsigned long ulInterrupt) -{ - // - // Check the arguments. - // - ASSERT(ulInterrupt < NUM_INTERRUPTS); - - // - // Determine the interrupt to enable. - // - if(ulInterrupt == FAULT_MPU) - { - // - // Enable the MemManage interrupt. - // - HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM; - } - else if(ulInterrupt == FAULT_BUS) - { - // - // Enable the bus fault interrupt. - // - HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS; - } - else if(ulInterrupt == FAULT_USAGE) - { - // - // Enable the usage fault interrupt. - // - HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE; - } - else if(ulInterrupt == FAULT_SYSTICK) - { - // - // Enable the System Tick interrupt. - // - HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; - } - else if(ulInterrupt >= INT_GPIOA) - { - // - // Enable the general interrupt. - // - HWREG(NVIC_EN0) = 1 << (ulInterrupt - INT_GPIOA); - } -} -#endif - -//***************************************************************************** -// -//! Disables an interrupt. -//! -//! \param ulInterrupt specifies the interrupt to be disabled. -//! -//! The specified interrupt is disabled in the interrupt controller. Other -//! enables for the interrupt (such as at the peripheral level) are unaffected -//! by this function. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -IntDisable(unsigned long ulInterrupt) -{ - // - // Check the arguments. - // - ASSERT(ulInterrupt < NUM_INTERRUPTS); - - // - // Determine the interrupt to disable. - // - if(ulInterrupt == FAULT_MPU) - { - // - // Disable the MemManage interrupt. - // - HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_MEM); - } - else if(ulInterrupt == FAULT_BUS) - { - // - // Disable the bus fault interrupt. - // - HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_BUS); - } - else if(ulInterrupt == FAULT_USAGE) - { - // - // Disable the usage fault interrupt. - // - HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_USAGE); - } - else if(ulInterrupt == FAULT_SYSTICK) - { - // - // Disable the System Tick interrupt. - // - HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); - } - else if(ulInterrupt >= INT_GPIOA) - { - // - // Disable the general interrupt. - // - HWREG(NVIC_DIS0) = 1 << (ulInterrupt - INT_GPIOA); - } -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/interrupt.h b/Demo/CORTEX_LM3S811_GCC/hw_include/interrupt.h deleted file mode 100644 index 37d414dab..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/interrupt.h +++ /dev/null @@ -1,57 +0,0 @@ -//***************************************************************************** -// -// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __INTERRUPT_H__ -#define __INTERRUPT_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void IntMasterEnable(void); -extern void IntMasterDisable(void); -extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)); -extern void IntUnregister(unsigned long ulInterrupt); -extern void IntPriorityGroupingSet(unsigned long ulBits); -extern unsigned long IntPriorityGroupingGet(void); -extern void IntPrioritySet(unsigned long ulInterrupt, - unsigned char ucPriority); -extern long IntPriorityGet(unsigned long ulInterrupt); -extern void IntEnable(unsigned long ulInterrupt); -extern void IntDisable(unsigned long ulInterrupt); - -#ifdef __cplusplus -} -#endif - -#endif // __INTERRUPT_H__ diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/libdriver.a b/Demo/CORTEX_LM3S811_GCC/hw_include/libdriver.a deleted file mode 100644 index 85385dcf1..000000000 Binary files a/Demo/CORTEX_LM3S811_GCC/hw_include/libdriver.a and /dev/null differ diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/osram96x16.c b/Demo/CORTEX_LM3S811_GCC/hw_include/osram96x16.c deleted file mode 100644 index 647904972..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/osram96x16.c +++ /dev/null @@ -1,975 +0,0 @@ -//***************************************************************************** -// -// osram96x16.c - Driver for the OSRAM 96x16 graphical OLED display. -// -// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1049 of the Stellaris Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup ev_lm3s811_api -//! @{ -// -//***************************************************************************** - -#include "hw_i2c.h" -#include "hw_memmap.h" -#include "hw_sysctl.h" -#include "hw_types.h" -#include "debug.h" -#include "gpio.h" -#include "i2c.h" -#include "sysctl.h" -#include "osram96x16.h" - -//***************************************************************************** -// -// The I2C slave address of the SSD0303 controller on the OLED display. -// -//***************************************************************************** -#define SSD0303_ADDR 0x3d - -//***************************************************************************** -// -// A 5x7 font (in a 6x8 cell, where the sixth column is omitted from this -// table) for displaying text on the OLED display. The data is organized as -// bytes from the left column to the right column, with each byte containing -// the top row in the LSB and the bottom row in the MSB. -// -//***************************************************************************** -static const unsigned char g_pucFont[95][5] = -{ - { 0x00, 0x00, 0x00, 0x00, 0x00 }, // " " - { 0x00, 0x00, 0x4f, 0x00, 0x00 }, // ! - { 0x00, 0x07, 0x00, 0x07, 0x00 }, // " - { 0x14, 0x7f, 0x14, 0x7f, 0x14 }, // # - { 0x24, 0x2a, 0x7f, 0x2a, 0x12 }, // $ - { 0x23, 0x13, 0x08, 0x64, 0x62 }, // % - { 0x36, 0x49, 0x55, 0x22, 0x50 }, // & - { 0x00, 0x05, 0x03, 0x00, 0x00 }, // ' - { 0x00, 0x1c, 0x22, 0x41, 0x00 }, // ( - { 0x00, 0x41, 0x22, 0x1c, 0x00 }, // ) - { 0x14, 0x08, 0x3e, 0x08, 0x14 }, // * - { 0x08, 0x08, 0x3e, 0x08, 0x08 }, // + - { 0x00, 0x50, 0x30, 0x00, 0x00 }, // , - { 0x08, 0x08, 0x08, 0x08, 0x08 }, // - - { 0x00, 0x60, 0x60, 0x00, 0x00 }, // . - { 0x20, 0x10, 0x08, 0x04, 0x02 }, // / - { 0x3e, 0x51, 0x49, 0x45, 0x3e }, // 0 - { 0x00, 0x42, 0x7f, 0x40, 0x00 }, // 1 - { 0x42, 0x61, 0x51, 0x49, 0x46 }, // 2 - { 0x21, 0x41, 0x45, 0x4b, 0x31 }, // 3 - { 0x18, 0x14, 0x12, 0x7f, 0x10 }, // 4 - { 0x27, 0x45, 0x45, 0x45, 0x39 }, // 5 - { 0x3c, 0x4a, 0x49, 0x49, 0x30 }, // 6 - { 0x01, 0x71, 0x09, 0x05, 0x03 }, // 7 - { 0x36, 0x49, 0x49, 0x49, 0x36 }, // 8 - { 0x06, 0x49, 0x49, 0x29, 0x1e }, // 9 - { 0x00, 0x36, 0x36, 0x00, 0x00 }, // : - { 0x00, 0x56, 0x36, 0x00, 0x00 }, // ; - { 0x08, 0x14, 0x22, 0x41, 0x00 }, // < - { 0x14, 0x14, 0x14, 0x14, 0x14 }, // = - { 0x00, 0x41, 0x22, 0x14, 0x08 }, // > - { 0x02, 0x01, 0x51, 0x09, 0x06 }, // ? - { 0x32, 0x49, 0x79, 0x41, 0x3e }, // @ - { 0x7e, 0x11, 0x11, 0x11, 0x7e }, // A - { 0x7f, 0x49, 0x49, 0x49, 0x36 }, // B - { 0x3e, 0x41, 0x41, 0x41, 0x22 }, // C - { 0x7f, 0x41, 0x41, 0x22, 0x1c }, // D - { 0x7f, 0x49, 0x49, 0x49, 0x41 }, // E - { 0x7f, 0x09, 0x09, 0x09, 0x01 }, // F - { 0x3e, 0x41, 0x49, 0x49, 0x7a }, // G - { 0x7f, 0x08, 0x08, 0x08, 0x7f }, // H - { 0x00, 0x41, 0x7f, 0x41, 0x00 }, // I - { 0x20, 0x40, 0x41, 0x3f, 0x01 }, // J - { 0x7f, 0x08, 0x14, 0x22, 0x41 }, // K - { 0x7f, 0x40, 0x40, 0x40, 0x40 }, // L - { 0x7f, 0x02, 0x0c, 0x02, 0x7f }, // M - { 0x7f, 0x04, 0x08, 0x10, 0x7f }, // N - { 0x3e, 0x41, 0x41, 0x41, 0x3e }, // O - { 0x7f, 0x09, 0x09, 0x09, 0x06 }, // P - { 0x3e, 0x41, 0x51, 0x21, 0x5e }, // Q - { 0x7f, 0x09, 0x19, 0x29, 0x46 }, // R - { 0x46, 0x49, 0x49, 0x49, 0x31 }, // S - { 0x01, 0x01, 0x7f, 0x01, 0x01 }, // T - { 0x3f, 0x40, 0x40, 0x40, 0x3f }, // U - { 0x1f, 0x20, 0x40, 0x20, 0x1f }, // V - { 0x3f, 0x40, 0x38, 0x40, 0x3f }, // W - { 0x63, 0x14, 0x08, 0x14, 0x63 }, // X - { 0x07, 0x08, 0x70, 0x08, 0x07 }, // Y - { 0x61, 0x51, 0x49, 0x45, 0x43 }, // Z - { 0x00, 0x7f, 0x41, 0x41, 0x00 }, // [ - { 0x02, 0x04, 0x08, 0x10, 0x20 }, // "\" - { 0x00, 0x41, 0x41, 0x7f, 0x00 }, // ] - { 0x04, 0x02, 0x01, 0x02, 0x04 }, // ^ - { 0x40, 0x40, 0x40, 0x40, 0x40 }, // _ - { 0x00, 0x01, 0x02, 0x04, 0x00 }, // ` - { 0x20, 0x54, 0x54, 0x54, 0x78 }, // a - { 0x7f, 0x48, 0x44, 0x44, 0x38 }, // b - { 0x38, 0x44, 0x44, 0x44, 0x20 }, // c - { 0x38, 0x44, 0x44, 0x48, 0x7f }, // d - { 0x38, 0x54, 0x54, 0x54, 0x18 }, // e - { 0x08, 0x7e, 0x09, 0x01, 0x02 }, // f - { 0x0c, 0x52, 0x52, 0x52, 0x3e }, // g - { 0x7f, 0x08, 0x04, 0x04, 0x78 }, // h - { 0x00, 0x44, 0x7d, 0x40, 0x00 }, // i - { 0x20, 0x40, 0x44, 0x3d, 0x00 }, // j - { 0x7f, 0x10, 0x28, 0x44, 0x00 }, // k - { 0x00, 0x41, 0x7f, 0x40, 0x00 }, // l - { 0x7c, 0x04, 0x18, 0x04, 0x78 }, // m - { 0x7c, 0x08, 0x04, 0x04, 0x78 }, // n - { 0x38, 0x44, 0x44, 0x44, 0x38 }, // o - { 0x7c, 0x14, 0x14, 0x14, 0x08 }, // p - { 0x08, 0x14, 0x14, 0x18, 0x7c }, // q - { 0x7c, 0x08, 0x04, 0x04, 0x08 }, // r - { 0x48, 0x54, 0x54, 0x54, 0x20 }, // s - { 0x04, 0x3f, 0x44, 0x40, 0x20 }, // t - { 0x3c, 0x40, 0x40, 0x20, 0x7c }, // u - { 0x1c, 0x20, 0x40, 0x20, 0x1c }, // v - { 0x3c, 0x40, 0x30, 0x40, 0x3c }, // w - { 0x44, 0x28, 0x10, 0x28, 0x44 }, // x - { 0x0c, 0x50, 0x50, 0x50, 0x3c }, // y - { 0x44, 0x64, 0x54, 0x4c, 0x44 }, // z - { 0x00, 0x08, 0x36, 0x41, 0x00 }, // { - { 0x00, 0x00, 0x7f, 0x00, 0x00 }, // | - { 0x00, 0x41, 0x36, 0x08, 0x00 }, // } - { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~ -}; - -//***************************************************************************** -// -// The sequence of commands used to initialize the SSD0303 controller. Each -// command is described as follows: there is a byte specifying the number of -// bytes in the I2C transfer, followed by that many bytes of command data. -// -//***************************************************************************** -static const unsigned char g_pucOSRAMInit[] = -{ - // - // Turn off the panel - // - 0x04, 0x80, 0xae, 0x80, 0xe3, - - // - // Set lower column address - // - 0x04, 0x80, 0x04, 0x80, 0xe3, - - // - // Set higher column address - // - 0x04, 0x80, 0x12, 0x80, 0xe3, - - // - // Set contrast control register - // - 0x06, 0x80, 0x81, 0x80, 0x2b, 0x80, 0xe3, - - // - // Set segment re-map - // - 0x04, 0x80, 0xa1, 0x80, 0xe3, - - // - // Set display start line - // - 0x04, 0x80, 0x40, 0x80, 0xe3, - - // - // Set display offset - // - 0x06, 0x80, 0xd3, 0x80, 0x00, 0x80, 0xe3, - - // - // Set multiplex ratio - // - 0x06, 0x80, 0xa8, 0x80, 0x0f, 0x80, 0xe3, - - // - // Set the display to normal mode - // - 0x04, 0x80, 0xa4, 0x80, 0xe3, - - // - // Non-inverted display - // - 0x04, 0x80, 0xa6, 0x80, 0xe3, - - // - // Set the page address - // - 0x04, 0x80, 0xb0, 0x80, 0xe3, - - // - // Set COM output scan direction - // - 0x04, 0x80, 0xc8, 0x80, 0xe3, - - // - // Set display clock divide ratio/oscillator frequency - // - 0x06, 0x80, 0xd5, 0x80, 0x72, 0x80, 0xe3, - - // - // Enable mono mode - // - 0x06, 0x80, 0xd8, 0x80, 0x00, 0x80, 0xe3, - - // - // Set pre-charge period - // - 0x06, 0x80, 0xd9, 0x80, 0x22, 0x80, 0xe3, - - // - // Set COM pins hardware configuration - // - 0x06, 0x80, 0xda, 0x80, 0x12, 0x80, 0xe3, - - // - // Set VCOM deslect level - // - 0x06, 0x80, 0xdb, 0x80, 0x0f, 0x80, 0xe3, - - // - // Set DC-DC on - // - 0x06, 0x80, 0xad, 0x80, 0x8b, 0x80, 0xe3, - - // - // Turn on the panel - // - 0x04, 0x80, 0xaf, 0x80, 0xe3, -}; - -//***************************************************************************** -// -// The inter-byte delay required by the SSD0303 OLED controller. -// -//***************************************************************************** -static unsigned long g_ulDelay; - -//***************************************************************************** -// -//! \internal -//! -//! Provide a small delay. -//! -//! \param ulCount is the number of delay loop iterations to perform. -//! -//! Since the SSD0303 controller needs a delay between bytes written to it over -//! the I2C bus, this function provides a means of generating that delay. It -//! is written in assembly to keep the delay consistent across tool chains, -//! avoiding the need to tune the delay based on the tool chain in use. -//! -//! \return None. -// -//***************************************************************************** -#if defined(ewarm) -static void -OSRAMDelay(unsigned long ulCount) -{ - __asm(" subs r0, #1\n" - " bne OSRAMDelay\n" - " bx lr"); -} -#endif -#if defined(gcc) -static void __attribute__((naked)) -OSRAMDelay(unsigned long ulCount) -{ - __asm(" subs r0, #1\n" - " bne OSRAMDelay\n" - " bx lr"); -} -#endif -#if defined(rvmdk) || defined(__ARMCC_VERSION) -__asm void -OSRAMDelay(unsigned long ulCount) -{ - subs r0, #1; - bne OSRAMDelay; - bx lr; -} -#endif - -//***************************************************************************** -// -//! \internal -//! -//! Start a transfer to the SSD0303 controller. -//! -//! \param ucChar is the first byte to be written to the controller. -//! -//! This function will start a transfer to the SSD0303 controller via the I2C -//! bus. -//! -//! The data is written in a polled fashion; this function will not return -//! until the byte has been written to the controller. -//! -//! \return None. -// -//***************************************************************************** -static void -OSRAMWriteFirst(unsigned char ucChar) -{ - // - // Set the slave address. - // - I2CMasterSlaveAddrSet(I2C_MASTER_BASE, SSD0303_ADDR, false); - - // - // Write the first byte to the controller. - // - I2CMasterDataPut(I2C_MASTER_BASE, ucChar); - - // - // Start the transfer. - // - I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_START); -} - -//***************************************************************************** -// -//! \internal -//! -//! Write a byte to the SSD0303 controller. -//! -//! \param ucChar is the byte to be transmitted to the controller. -//! -//! This function continues a transfer to the SSD0303 controller by writing -//! another byte over the I2C bus. This must only be called after calling -//! OSRAMWriteFirst(), but before calling OSRAMWriteFinal(). -//! -//! The data is written in a polled faashion; this function will not return -//! until the byte has been written to the controller. -//! -//! \return None. -// -//***************************************************************************** -static void -OSRAMWriteByte(unsigned char ucChar) -{ - // - // Wait until the current byte has been transferred. - // - while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0) - { - } - - // - // Provide the required inter-byte delay. - // - OSRAMDelay(g_ulDelay); - - // - // Write the next byte to the controller. - // - I2CMasterDataPut(I2C_MASTER_BASE, ucChar); - - // - // Continue the transfer. - // - I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_CONT); -} - -//***************************************************************************** -// -//! \internal -//! -//! Write a sequence of bytes to the SSD0303 controller. -//! -//! This function continues a transfer to the SSD0303 controller by writing a -//! sequence of bytes over the I2C bus. This must only be called after calling -//! OSRAMWriteFirst(), but before calling OSRAMWriteFinal(). -//! -//! The data is written in a polled fashion; this function will not return -//! until the entire byte sequence has been written to the controller. -//! -//! \return None. -// -//***************************************************************************** -static void -OSRAMWriteArray(const unsigned char *pucBuffer, unsigned long ulCount) -{ - // - // Loop while there are more bytes left to be transferred. - // - while(ulCount != 0) - { - // - // Wait until the current byte has been transferred. - // - while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0) - { - } - - // - // Provide the required inter-byte delay. - // - OSRAMDelay(g_ulDelay); - - // - // Write the next byte to the controller. - // - I2CMasterDataPut(I2C_MASTER_BASE, *pucBuffer++); - ulCount--; - - // - // Continue the transfer. - // - I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_CONT); - } -} - -//***************************************************************************** -// -//! \internal -//! -//! Finish a transfer to the SSD0303 controller. -//! -//! \param ucChar is the final byte to be written to the controller. -//! -//! This function will finish a transfer to the SSD0303 controller via the I2C -//! bus. This must only be called after calling OSRAMWriteFirst(). -//! -//! The data is written in a polled fashion; this function will not return -//! until the byte has been written to the controller. -//! -//! \return None. -// -//***************************************************************************** -static void -OSRAMWriteFinal(unsigned char ucChar) -{ - // - // Wait until the current byte has been transferred. - // - while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0) - { - } - - // - // Provide the required inter-byte delay. - // - OSRAMDelay(g_ulDelay); - - // - // Write the final byte to the controller. - // - I2CMasterDataPut(I2C_MASTER_BASE, ucChar); - - // - // Finish the transfer. - // - I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_FINISH); - - // - // Wait until the final byte has been transferred. - // - while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0) - { - } - - // - // Provide the required inter-byte delay. - // - OSRAMDelay(g_ulDelay); -} - -//***************************************************************************** -// -//! Clears the OLED display. -//! -//! This function will clear the display. All pixels in the display will be -//! turned off. -//! -//! This function is contained in osram96x16.c, with -//! osram96x16.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAMClear(void) -{ - static const unsigned char pucRow1[] = - { - 0xb0, 0x80, 0x04, 0x80, 0x12, 0x40 - }; - static const unsigned char pucRow2[] = - { - 0xb1, 0x80, 0x04, 0x80, 0x12, 0x40 - }; - unsigned long ulIdx; - - // - // Move the display cursor to the first column of the first row. - // - OSRAMWriteFirst(0x80); - OSRAMWriteArray(pucRow1, sizeof(pucRow1)); - - // - // Fill this row with zeros. - // - for(ulIdx = 0; ulIdx < 95; ulIdx++) - { - OSRAMWriteByte(0x00); - } - OSRAMWriteFinal(0x00); - - // - // Move the display cursor to the first column of the second row. - // - OSRAMWriteFirst(0x80); - OSRAMWriteArray(pucRow2, sizeof(pucRow2)); - - // - // Fill this row with zeros. - // - for(ulIdx = 0; ulIdx < 95; ulIdx++) - { - OSRAMWriteByte(0x00); - } - OSRAMWriteFinal(0x00); -} - -//***************************************************************************** -// -//! Displays a string on the OLED display. -//! -//! \param pcStr is a pointer to the string to display. -//! \param ulX is the horizontal position to display the string, specified in -//! columns from the left edge of the display. -//! \param ulY is the vertical position to display the string, specified in -//! eight scan line blocks from the top of the display (i.e. only 0 and 1 are -//! valid). -//! -//! This function will draw a string on the display. Only the ASCII characters -//! between 32 (space) and 126 (tilde) are supported; other characters will -//! result in random data being draw on the display (based on whatever appears -//! before/after the font in memory). The font is mono-spaced, so characters -//! such as "i" and "l" have more white space around them than characters such -//! as "m" or "w". -//! -//! If the drawing of the string reaches the right edge of the display, no more -//! characters will be drawn. Therefore, special care is not required to avoid -//! supplying a string that is "too long" to display. -//! -//! This function is contained in osram96x16.c, with -//! osram96x16.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAMStringDraw(const char *pcStr, unsigned long ulX, unsigned long ulY) -{ - // - // Check the arguments. - // - ASSERT(ulX < 96); - ASSERT(ulY < 2); - - // - // Move the display cursor to the requested position on the display. - // - OSRAMWriteFirst(0x80); - OSRAMWriteByte((ulY == 0) ? 0xb0 : 0xb1); - OSRAMWriteByte(0x80); - OSRAMWriteByte((ulX + 36) & 0x0f); - OSRAMWriteByte(0x80); - OSRAMWriteByte(0x10 | (((ulX + 36) >> 4) & 0x0f)); - OSRAMWriteByte(0x40); - - // - // Loop while there are more characters in the string. - // - while(*pcStr != 0) - { - // - // See if there is enough space on the display for this entire - // character. - // - if(ulX <= 90) - { - // - // Write the contents of this character to the display. - // - OSRAMWriteArray(g_pucFont[*pcStr - ' '], 5); - - // - // See if this is the last character to display (either because the - // right edge has been reached or because there are no more - // characters). - // - if((ulX == 90) || (pcStr[1] == 0)) - { - // - // Write the final column of the display. - // - OSRAMWriteFinal(0x00); - - // - // The string has been displayed. - // - return; - } - - // - // Write the inter-character padding column. - // - OSRAMWriteByte(0x00); - } - else - { - // - // Write the portion of the character that will fit onto the - // display. - // - OSRAMWriteArray(g_pucFont[*pcStr - ' '], 95 - ulX); - OSRAMWriteFinal(g_pucFont[*pcStr - ' '][95 - ulX]); - - // - // The string has been displayed. - // - return; - } - - // - // Advance to the next character. - // - pcStr++; - - // - // Increment the X coordinate by the six columns that were just - // written. - // - ulX += 6; - } -} - -//***************************************************************************** -// -//! Displays an image on the OLED display. -//! -//! \param pucImage is a pointer to the image data. -//! \param ulX is the horizontal position to display this image, specified in -//! columns from the left edge of the display. -//! \param ulY is the vertical position to display this image, specified in -//! eight scan line blocks from the top of the display (i.e. only 0 and 1 are -//! valid). -//! \param ulWidth is the width of the image, specified in columns. -//! \param ulHeight is the height of the image, specified in eight row blocks -//! (i.e. only 1 and 2 are valid). -//! -//! This function will display a bitmap graphic on the display. The image to -//! be displayed must be a multiple of eight scan lines high (i.e. one row) and -//! will be drawn at a vertical position that is a multiple of eight scan lines -//! (i.e. scan line zero or scan line eight, corresponding to row zero or row -//! one). -//! -//! The image data is organized with the first row of image data appearing left -//! to right, followed immediately by the second row of image data. Each byte -//! contains the data for the eight scan lines of the column, with the top scan -//! line being in the least significant bit of the byte and the bottom scan -//! line being in the most significant bit of the byte. -//! -//! For example, an image four columns wide and sixteen scan lines tall would -//! be arranged as follows (showing how the eight bytes of the image would -//! appear on the display): -//! -//! \verbatim -//! +-------+ +-------+ +-------+ +-------+ -//! | | 0 | | | 0 | | | 0 | | | 0 | -//! | B | 1 | | B | 1 | | B | 1 | | B | 1 | -//! | y | 2 | | y | 2 | | y | 2 | | y | 2 | -//! | t | 3 | | t | 3 | | t | 3 | | t | 3 | -//! | e | 4 | | e | 4 | | e | 4 | | e | 4 | -//! | | 5 | | | 5 | | | 5 | | | 5 | -//! | 0 | 6 | | 1 | 6 | | 2 | 6 | | 3 | 6 | -//! | | 7 | | | 7 | | | 7 | | | 7 | -//! +-------+ +-------+ +-------+ +-------+ -//! -//! +-------+ +-------+ +-------+ +-------+ -//! | | 0 | | | 0 | | | 0 | | | 0 | -//! | B | 1 | | B | 1 | | B | 1 | | B | 1 | -//! | y | 2 | | y | 2 | | y | 2 | | y | 2 | -//! | t | 3 | | t | 3 | | t | 3 | | t | 3 | -//! | e | 4 | | e | 4 | | e | 4 | | e | 4 | -//! | | 5 | | | 5 | | | 5 | | | 5 | -//! | 4 | 6 | | 5 | 6 | | 6 | 6 | | 7 | 6 | -//! | | 7 | | | 7 | | | 7 | | | 7 | -//! +-------+ +-------+ +-------+ +-------+ -//! \endverbatim -//! -//! This function is contained in osram96x16.c, with -//! osram96x16.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAMImageDraw(const unsigned char *pucImage, unsigned long ulX, - unsigned long ulY, unsigned long ulWidth, - unsigned long ulHeight) -{ - // - // Check the arguments. - // - ASSERT(ulX < 96); - ASSERT(ulY < 2); - ASSERT((ulX + ulWidth) <= 96); - ASSERT((ulY + ulHeight) <= 2); - - // - // The first 36 columns of the LCD buffer are not displayed, so increment - // the X coorddinate by 36 to account for the non-displayed frame buffer - // memory. - // - ulX += 36; - - // - // Loop while there are more rows to display. - // - while(ulHeight--) - { - // - // Write the starting address within this row. - // - OSRAMWriteFirst(0x80); - OSRAMWriteByte((ulY == 0) ? 0xb0 : 0xb1); - OSRAMWriteByte(0x80); - OSRAMWriteByte(ulX & 0x0f); - OSRAMWriteByte(0x80); - OSRAMWriteByte(0x10 | ((ulX >> 4) & 0x0f)); - OSRAMWriteByte(0x40); - - // - // Write this row of image data. - // - OSRAMWriteArray(pucImage, ulWidth - 1); - OSRAMWriteFinal(pucImage[ulWidth - 1]); - - // - // Advance to the next row of the image. - // - pucImage += ulWidth; - ulY++; - } -} - -//***************************************************************************** -// -//! Initialize the OLED display. -//! -//! \param bFast is a boolean that is \e true if the I2C interface should be -//! run at 400 kbps and \e false if it should be run at 100 kbps. -//! -//! This function initializes the I2C interface to the OLED display and -//! configures the SSD0303 controller on the panel. -//! -//! This function is contained in osram96x16.c, with -//! osram96x16.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAMInit(tBoolean bFast) -{ - unsigned long ulIdx; - - // - // Enable the I2C and GPIO port B blocks as they are needed by this driver. - // - SysCtlPeripheralEnable(SYSCTL_PERIPH_I2C); - SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB); - - // - // Configure the I2C SCL and SDA pins for I2C operation. - // - GPIOPinTypeI2C(GPIO_PORTB_BASE, GPIO_PIN_2 | GPIO_PIN_3); - - // - // Initialize the I2C master. - // - I2CMasterInit(I2C_MASTER_BASE, bFast); - - // - // Compute the inter-byte delay for the SSD0303 controller. This delay is - // dependent upon the I2C bus clock rate; the slower the clock the longer - // the delay required. - // - // The derivation of this formula is based on a measured delay of - // OSRAMDelay(1700) for a 100 kHz I2C bus with the CPU running at 50 MHz - // (referred to as C). To scale this to the delay for a different CPU - // speed (since this is just a CPU-based delay loop) is: - // - // f(CPU) - // C * ---------- - // 50,000,000 - // - // To then scale this to the actual I2C rate (since it won't always be - // precisely 100 kHz): - // - // f(CPU) 100,000 - // C * ---------- * ------- - // 50,000,000 f(I2C) - // - // This equation will give the inter-byte delay required for any - // configuration of the I2C master. But, as arranged it is impossible to - // directly compute in 32-bit arithmetic (without loosing a lot of - // accuracy). So, the equation is simplified. - // - // Since f(I2C) is generated by dividing down from f(CPU), replace it with - // the equivalent (where TPR is the value programmed into the Master Timer - // Period Register of the I2C master, with the 1 added back): - // - // 100,000 - // f(CPU) ------- - // C * ---------- * f(CPU) - // 50,000,000 ------------ - // 2 * 10 * TPR - // - // Inverting the dividend in the last term: - // - // f(CPU) 100,000 * 2 * 10 * TPR - // C * ---------- * ---------------------- - // 50,000,000 f(CPU) - // - // The f(CPU) now cancels out. - // - // 100,000 * 2 * 10 * TPR - // C * ---------------------- - // 50,000,000 - // - // Since there are no clock frequencies left in the equation, this equation - // also works for 400 kHz bus operation as well, since the 100,000 in the - // numerator becomes 400,000 but C is 1/4, which cancel out each other. - // Reducing the constants gives: - // - // TPR TPR TPR - // C * --- = 1700 * --- = 340 * --- = 68 * TPR - // 25 25 5 - // - // Note that the constant C is actually a bit larger than it needs to be in - // order to provide some safety margin. - // - g_ulDelay = 68 * (HWREG(I2C_MASTER_BASE + I2C_MASTER_O_TPR) + 1); - - // - // Initialize the SSD0303 controller. Loop through the initialization - // sequence doing a single I2C transfer for each command. - // - for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAMInit); - ulIdx += g_pucOSRAMInit[ulIdx] + 1) - { - // - // Send this command. - // - OSRAMWriteFirst(g_pucOSRAMInit[ulIdx + 1]); - OSRAMWriteArray(g_pucOSRAMInit + ulIdx + 2, g_pucOSRAMInit[ulIdx] - 2); - OSRAMWriteFinal(g_pucOSRAMInit[ulIdx + g_pucOSRAMInit[ulIdx]]); - } - - // - // Clear the frame buffer. - // - OSRAMClear(); -} - -//***************************************************************************** -// -//! Turns on the OLED display. -//! -//! This function will turn on the OLED display, causing it to display the -//! contents of its internal frame buffer. -//! -//! This function is contained in osram96x16.c, with -//! osram96x16.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAMDisplayOn(void) -{ - unsigned long ulIdx; - - // - // Re-initialize the SSD0303 controller. Loop through the initialization - // sequence doing a single I2C transfer for each command. - // - for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAMInit); - ulIdx += g_pucOSRAMInit[ulIdx] + 1) - { - // - // Send this command. - // - OSRAMWriteFirst(g_pucOSRAMInit[ulIdx + 1]); - OSRAMWriteArray(g_pucOSRAMInit + ulIdx + 2, g_pucOSRAMInit[ulIdx] - 2); - OSRAMWriteFinal(g_pucOSRAMInit[ulIdx + g_pucOSRAMInit[ulIdx]]); - } -} - -//***************************************************************************** -// -//! Turns off the OLED display. -//! -//! This function will turn off the OLED display. This will stop the scanning -//! of the panel and turn off the on-chip DC-DC converter, preventing damage to -//! the panel due to burn-in (it has similar characters to a CRT in this -//! respect). -//! -//! This function is contained in osram96x16.c, with -//! osram96x16.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAMDisplayOff(void) -{ - // - // Turn off the DC-DC converter and the display. - // - OSRAMWriteFirst(0x80); - OSRAMWriteByte(0xae); - OSRAMWriteByte(0x80); - OSRAMWriteByte(0xad); - OSRAMWriteByte(0x80); - OSRAMWriteFinal(0x8a); -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/osram96x16.h b/Demo/CORTEX_LM3S811_GCC/hw_include/osram96x16.h deleted file mode 100644 index 0c9cd3692..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/osram96x16.h +++ /dev/null @@ -1,47 +0,0 @@ -//***************************************************************************** -// -// osram96x16.h - Prototypes for the driver for the OSRAM 96x16 graphical OLED -// display. -// -// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __OSRAM96X16_H__ -#define __OSRAM96X16_H__ - -//***************************************************************************** -// -// Prototypes for the driver APIs. -// -//***************************************************************************** -extern void OSRAMClear(void); -extern void OSRAMStringDraw(const char *pcStr, unsigned long ulX, - unsigned long ulY); -extern void OSRAMImageDraw(const unsigned char *pucImage, unsigned long ulX, - unsigned long ulY, unsigned long ulWidth, - unsigned long ulHeight); -extern void OSRAMInit(tBoolean bFast); -extern void OSRAMDisplayOn(void); -extern void OSRAMDisplayOff(void); - -#endif // __OSRAM96X16_H__ diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/pwm.c b/Demo/CORTEX_LM3S811_GCC/hw_include/pwm.c deleted file mode 100644 index 6697566ea..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/pwm.c +++ /dev/null @@ -1,1291 +0,0 @@ -//***************************************************************************** -// -// pwm.c - API for the PWM modules -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup pwm_api -//! @{ -// -//***************************************************************************** - -#include "../hw_ints.h" -#include "../hw_memmap.h" -#include "../hw_pwm.h" -#include "../hw_types.h" -#include "debug.h" -#include "interrupt.h" -#include "pwm.h" - -//***************************************************************************** -// -// Misc macros for manipulating the encoded generator and output defines used -// by the API. -// -//***************************************************************************** -#define PWM_GEN_BADDR(_mod_, _gen_) \ - ((_mod_) + (_gen_)) -#define PWM_OUT_BADDR(_mod_, _out_) \ - ((_mod_) + ((_out_) & 0xFFFFFFC0)) -#define PWM_IS_OUTPUT_ODD(_out_) \ - ((_out_) & 0x00000001) - -//***************************************************************************** -// -//! Configures a PWM generator. -//! -//! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator to configure. Must be one of -//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. -//! \param ulConfig is the configuration for the PWM generator. -//! -//! This function is used to set the mode of operation for a PWM generator. -//! The counting mode, synchronization mode, and debug behavior are all -//! configured. After configuration, the generator is left in the disabled -//! state. -//! -//! A PWM generator can count in two different modes: count down mode or count -//! up/down mode. In count down mode, it will count from a value down to zero, -//! and then reset to the preset value. This will produce left-aligned PWM -//! signals (i.e. the rising edge of the two PWM signals produced by the -//! generator will occur at the same time). In count up/down mode, it will -//! count up from zero to the preset value, count back down to zero, and then -//! repeat the process. This will produce center-aligned PWM signals (i.e. the -//! middle of the high/low period of the PWM signals produced by the generator -//! will occur at the same time). -//! -//! When the PWM generator parameters (period and pulse width) are modified, -//! their affect on the output PWM signals can be delayed. In synchronous -//! mode, the parameter updates are not applied until a synchronization event -//! occurs. This allows multiple parameters to be modified and take affect -//! simultaneously, instead of one at a time. Additionally, parameters to -//! multiple PWM generators in synchronous mode can be updated simultaneously, -//! allowing them to be treated as if they were a unified generator. In -//! non-synchronous mode, the parameter updates are not delayed until a -//! synchronization event. In either mode, the parameter updates only occur -//! when the counter is at zero to help prevent oddly formed PWM signals during -//! the update (i.e. a PWM pulse that is too short or too long). -//! -//! The PWM generator can either pause or continue running when the processor -//! is stopped via the debugger. If configured to pause, it will continue to -//! count until it reaches zero, at which point it will pause until the -//! processor is restarted. If configured to continue running, it will keep -//! counting as if nothing had happened. -//! -//! The \b ulConfig parameter contains the desired configuration. It is the -//! logical OR of the following: \b PWM_GEN_MODE_DOWN or -//! \b PWM_GEN_MODE_UP_DOWN to specify the counting mode, \b PWM_GEN_MODE_SYNC -//! or \b PWM_GEN_MODE_NO_SYNC to specify the synchronization mode, and -//! \b PWM_GEN_MODE_DBG_RUN or \b PWM_GEN_MODE_DBG_STOP to specify the debug -//! behavior. -//! -//! \note Changes to the counter mode will affect the period of the PWM signals -//! produced. PWMGenPeriodSet() and PWMPulseWidthSet() should be called after -//! any changes to the counter mode of a generator. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_genconfigure) || defined(BUILD_ALL) || defined(DOXYGEN) -void -PWMGenConfigure(unsigned long ulBase, unsigned long ulGen, - unsigned long ulConfig) -{ - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || - (ulGen == PWM_GEN_2)); - - // - // Compute the generator's base address. - // - ulGen = PWM_GEN_BADDR(ulBase, ulGen); - - // - // Change the global configuration of the generator. - // - HWREG(ulGen + PWM_O_X_CTL) = ((HWREG(ulGen + PWM_O_X_CTL) & - ~(PWM_X_CTL_MODE | PWM_X_CTL_DEBUG | - PWM_X_CTL_LOADUPD | PWM_X_CTL_CMPAUPD | - PWM_X_CTL_CMPBUPD)) | ulConfig); - - // - // Set the individual PWM generator controls. - // - if(ulConfig & PWM_X_CTL_MODE) - { - // - // In up/down count mode, set the signal high on up count comparison - // and low on down count comparison (i.e. center align the signals). - // - HWREG(ulGen + PWM_O_X_GENA) = ((PWM_GEN_ACT_ONE << - PWM_GEN_ACT_A_UP_SHIFT) | - (PWM_GEN_ACT_ZERO << - PWM_GEN_ACT_A_DN_SHIFT)); - HWREG(ulGen + PWM_O_X_GENB) = ((PWM_GEN_ACT_ONE << - PWM_GEN_ACT_B_UP_SHIFT) | - (PWM_GEN_ACT_ZERO << - PWM_GEN_ACT_B_DN_SHIFT)); - } - else - { - // - // In down count mode, set the signal high on load and low on count - // comparison (i.e. left align the signals). - // - HWREG(ulGen + PWM_O_X_GENA) = ((PWM_GEN_ACT_ONE << - PWM_GEN_ACT_LOAD_SHIFT) | - (PWM_GEN_ACT_ZERO << - PWM_GEN_ACT_A_DN_SHIFT)); - HWREG(ulGen + PWM_O_X_GENB) = ((PWM_GEN_ACT_ONE << - PWM_GEN_ACT_LOAD_SHIFT) | - (PWM_GEN_ACT_ZERO << - PWM_GEN_ACT_B_DN_SHIFT)); - } -} -#endif - -//***************************************************************************** -// -//! Set the period of a PWM generator. -//! -//! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator to be modified. Must be one of -//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. -//! \param ulPeriod specifies the period of PWM generator output, measured -//! in clock ticks. -//! -//! This function sets the period of the specified PWM generator block, where -//! the period of the generator block is defined as the number of \b PWM -//! clock ticks between pulses on the generator block \b zero signal. -//! -//! \note Any subsequent calls made to this function before an update occurs -//! will cause the previous values to be overwritten. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_genperiodset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen, - unsigned long ulPeriod) -{ - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || - (ulGen == PWM_GEN_2)); - - // - // Compute the generator's base address. - // - ulGen = PWM_GEN_BADDR(ulBase, ulGen); - - // - // Set the reload register based on the mode. - // - if(HWREG(ulGen + PWM_O_X_CTL) & PWM_X_CTL_MODE) - { - // - // In up/down count mode, set the reload register to half the requested - // period. - // - ASSERT((ulPeriod / 2) < 65536); - HWREG(ulGen + PWM_O_X_LOAD) = ulPeriod / 2; - } - else - { - // - // In down count mode, set the reload register to the requested period - // minus one. - // - ASSERT((ulPeriod <= 65536) && (ulPeriod != 0)); - HWREG(ulGen + PWM_O_X_LOAD) = ulPeriod - 1; - } -} -#endif - -//***************************************************************************** -// -//! Gets the period of a PWM generator block. -//! -//! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator to query. Must be one of -//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. -//! -//! This function gets the period of the specified PWM generator block. The -//! period of the generator block is defined as the number of \b PWM clock -//! ticks between pulses on the generator block \b zero signal. -//! -//! If the update of the counter for the specified PWM generator has yet -//! to be completed, the value returned may not be the active period. The -//! value returned is the programmed period, measured in \b PWM clock ticks. -//! -//! \return Returns the programmed period of the specified generator block -//! in \b PWM clock ticks. -// -//***************************************************************************** -#if defined(GROUP_genperiodget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -PWMGenPeriodGet(unsigned long ulBase, unsigned long ulGen) -{ - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || - (ulGen == PWM_GEN_2)); - - // - // Compute the generator's base address. - // - ulGen = PWM_GEN_BADDR(ulBase, ulGen); - - // - // Figure out the counter mode. - // - if(HWREG(ulGen + PWM_O_X_CTL) & PWM_X_CTL_MODE) - { - // - // The period is twice the reload register value. - // - return(HWREG(ulGen + PWM_O_X_LOAD) * 2); - } - else - { - // - // The period is the reload register value plus one. - // - return(HWREG(ulGen + PWM_O_X_LOAD) + 1); - } -} -#endif - -//***************************************************************************** -// -//! Enables the timer/counter for a PWM generator block. -//! -//! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator to be enabled. Must be one of -//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. -//! -//! This function allows the \b PWM clock to drive the timer/counter for the -//! specified generator block. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_genenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -PWMGenEnable(unsigned long ulBase, unsigned long ulGen) -{ - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || - (ulGen == PWM_GEN_2)); - - // - // Enable the PWM generator. - // - HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_CTL) |= PWM_X_CTL_ENABLE; -} -#endif - -//***************************************************************************** -// -//! Disables the timer/counter for a PWM generator block. -//! -//! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator to be disabled. Must be one of -//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. -//! -//! This function blocks the \b PWM clock from driving the timer/counter for -//! the specified generator block. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_gendisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -PWMGenDisable(unsigned long ulBase, unsigned long ulGen) -{ - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || - (ulGen == PWM_GEN_2)); - - // - // Disable the PWM generator. - // - HWREG(PWM_GEN_BADDR(ulBase, + ulGen) + PWM_O_X_CTL) &= ~(PWM_X_CTL_ENABLE); -} -#endif - -//***************************************************************************** -// -//! Sets the pulse width for the specified PWM output. -//! -//! \param ulBase is the base address of the PWM module. -//! \param ulPWMOut is the PWM output to modify. Must be one of \b PWM_OUT_0, -//! \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4, or \b PWM_OUT_5. -//! \param ulWidth specifies the width of the positive portion of the pulse. -//! -//! This function sets the pulse width for the specified PWM output, where the -//! pulse width is defined as the number of \b PWM clock ticks. -//! -//! \note Any subsequent calls made to this function before an update occurs -//! will cause the previous values to be overwritten. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_pulsewidthset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut, - unsigned long ulWidth) -{ - unsigned long ulGenBase, ulReg; - - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - ASSERT((ulPWMOut == PWM_OUT_0) || (ulPWMOut == PWM_OUT_1) || - (ulPWMOut == PWM_OUT_2) || (ulPWMOut == PWM_OUT_3) || - (ulPWMOut == PWM_OUT_4) || (ulPWMOut == PWM_OUT_5)); - - // - // Compute the generator's base address. - // - ulGenBase = PWM_OUT_BADDR(ulBase, ulPWMOut); - - // - // If the counter is in up/down count mode, divide the width by two. - // - if(HWREG(ulGenBase + PWM_O_X_CTL) & PWM_X_CTL_MODE) - { - ulWidth /= 2; - } - - // - // Get the period. - // - ulReg = HWREG(ulGenBase + PWM_O_X_LOAD); - - // - // Make sure the width is not too large. - // - ASSERT(ulWidth < ulReg); - - // - // Compute the compare value. - // - ulReg = ulReg - ulWidth; - - // - // Write to the appropriate registers. - // - if(PWM_IS_OUTPUT_ODD(ulPWMOut)) - { - HWREG(ulGenBase + PWM_O_X_CMPB) = ulReg; - } - else - { - HWREG(ulGenBase + PWM_O_X_CMPA) = ulReg; - } -} -#endif - -//***************************************************************************** -// -//! Gets the pulse width of a PWM output. -//! -//! \param ulBase is the base address of the PWM module. -//! \param ulPWMOut is the PWM output to query. Must be one of \b PWM_OUT_0, -//! \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4, or \b PWM_OUT_5. -//! -//! This function gets the currently programmed pulse width for the -//! specified PWM output. If the update of the comparator for the specified -//! output has yet to be completed, the value returned may not be the active -//! pulse width. The value returned is the programmed pulse width, measured -//! in \b PWM clock ticks. -//! -//! \return Returns the width of the pulse in \b PWM clock ticks. -// -//***************************************************************************** -#if defined(GROUP_pulsewidthget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -PWMPulseWidthGet(unsigned long ulBase, unsigned long ulPWMOut) -{ - unsigned long ulGenBase, ulReg, ulLoad; - - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - ASSERT((ulPWMOut == PWM_OUT_0) || (ulPWMOut == PWM_OUT_1) || - (ulPWMOut == PWM_OUT_2) || (ulPWMOut == PWM_OUT_3) || - (ulPWMOut == PWM_OUT_4) || (ulPWMOut == PWM_OUT_5)); - - // - // Compute the generator's base address. - // - ulGenBase = PWM_OUT_BADDR(ulBase, ulPWMOut); - - // - // Then compute the pulse width. If mode is UpDown, set - // width = (load-compare)*2. Otherwise, set width = load - compare - // - ulLoad = HWREG(ulGenBase + PWM_O_X_LOAD); - if(PWM_IS_OUTPUT_ODD(ulPWMOut)) - { - ulReg = HWREG(ulGenBase + PWM_O_X_CMPB); - } - else - { - ulReg = HWREG(ulGenBase + PWM_O_X_CMPA); - } - ulReg = ulLoad - ulReg; - - // - // If in up/down count mode, double the pulse width. - // - if(HWREG(ulGenBase + PWM_O_X_CTL) & PWM_X_CTL_MODE) - { - ulReg = ulReg * 2; - } - - // - // Return the pulse width. - // - return(ulReg); -} -#endif - -//***************************************************************************** -// -//! Enables the PWM dead band output, and sets the dead band delays. -//! -//! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator to modify. Must be one of -//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. -//! \param usRise specifies the width of delay from the rising edge. -//! \param usFall specifies the width of delay from the falling edge. -//! -//! This function sets the dead bands for the specified PWM generator, -//! where the dead bands are defined as the number of \b PWM clock ticks -//! from the rising or falling edge of the generator's \b OutA signal. -//! Note that this function causes the coupling of \b OutB to \b OutA. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_deadbandenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen, - unsigned short usRise, unsigned short usFall) -{ - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || - (ulGen == PWM_GEN_2)); - ASSERT(usRise < 4096); - ASSERT(usFall < 4096); - - // - // Compute the generator's base address. - // - ulGen = PWM_GEN_BADDR(ulBase, ulGen); - - // - // Write the dead band delay values. - // - HWREG(ulGen + PWM_O_X_DBRISE) = usRise; - HWREG(ulGen + PWM_O_X_DBFALL) = usFall; - - // - // Enable the deadband functionality. - // - HWREG(ulGen + PWM_O_X_DBCTL) |= PWM_DBCTL_ENABLE; -} -#endif - -//***************************************************************************** -// -//! Disables the PWM dead band output. -//! -//! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator to modify. Must be one of -//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. -//! -//! This function disables the dead band mode for the specified PWM generator. -//! Doing so decouples the \b OutA and \b OutB signals. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_deadbanddisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen) -{ - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || - (ulGen == PWM_GEN_2)); - - // - // Disable the deadband functionality. - // - HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_DBCTL) &= ~(PWM_DBCTL_ENABLE); -} -#endif - -//***************************************************************************** -// -//! Synchronizes all pending updates. -//! -//! \param ulBase is the base address of the PWM module. -//! \param ulGenBits are the PWM generator blocks to be updated. Must be the -//! logical OR of any of \b PWM_GEN_0_BIT, \b PWM_GEN_1_BIT, or -//! \b PWM_GEN_2_BIT. -//! -//! For the selected PWM generators, this function causes all queued updates to -//! the period or pulse width to be applied the next time the corresponding -//! counter becomes zero. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_syncupdate) || defined(BUILD_ALL) || defined(DOXYGEN) -void -PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits) -{ - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - ASSERT(!(ulGenBits & ~(PWM_GEN_0_BIT | PWM_GEN_1_BIT | PWM_GEN_2_BIT))); - - // - // Update the PWM timing registers. - // - HWREG(ulBase + PWM_O_CTL) = ulGenBits; -} -#endif - -//***************************************************************************** -// -//! Synchronizes the counters in one or multiple PWM generator blocks. -//! -//! \param ulBase is the base address of the PWM module. -//! \param ulGenBits are the PWM generator blocks to be synchronized. Must be -//! the logical OR of any of \b PWM_GEN_0_BIT, \b PWM_GEN_1_BIT, or -//! \b PWM_GEN_2_BIT. -//! -//! For the selected PWM module, this function synchronizes the time base -//! of the generator blocks by causing the specified generator counters to be -//! reset to zero. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_synctimebase) || defined(BUILD_ALL) || defined(DOXYGEN) -void -PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits) -{ - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - ASSERT(!(ulGenBits & ~(PWM_GEN_0_BIT | PWM_GEN_1_BIT | PWM_GEN_2_BIT))); - - // - // Synchronize the counters in the specified generators by writing to - // the module's synchronization register. - // - HWREG(ulBase + PWM_O_SYNC) = ulGenBits; -} -#endif - -//***************************************************************************** -// -//! Enables or disables PWM outputs. -//! -//! \param ulBase is the base address of the PWM module. -//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the -//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT, -//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, or \b PWM_OUT_5_BIT. -//! \param bEnable determines if the signal is enabled or disabled. -//! -//! This function is used to enable or disable the selected PWM outputs. The -//! outputs are selected using the parameter \e ulPWMOutBits. The parameter -//! \e bEnable determines the state of the selected outputs. If \e bEnable is -//! \b true, then the selected PWM outputs are enabled, or placed in the active -//! state. If \e bEnable is \b false, then the selected outputs are disabled, -//! or placed in the inactive state. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_outputstate) || defined(BUILD_ALL) || defined(DOXYGEN) -void -PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits, - tBoolean bEnable) -{ - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT | - PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT))); - - // - // Read the module's ENABLE output control register, and set or clear - // the requested bits. - // - if(bEnable == true) - { - HWREG(ulBase + PWM_O_ENABLE) |= ulPWMOutBits; - } - else - { - HWREG(ulBase + PWM_O_ENABLE) &= ~(ulPWMOutBits); - } -} -#endif - -//***************************************************************************** -// -//! Selects the inversion mode for PWM outputs. -//! -//! \param ulBase is the base address of the PWM module. -//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the -//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT, -//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, or \b PWM_OUT_5_BIT. -//! \param bInvert determines if the signal is inverted or passed through. -//! -//! This function is used to select the inversion mode for the selected PWM -//! outputs. The outputs are selected using the parameter \e ulPWMOutBits. -//! The parameter \e bInvert determines the inversion mode for the selected -//! outputs. If \e bInvert is \b true, this function will cause the specified -//! PWM output signals to be inverted, or made active low. If \e bInvert is -//! \b false, the specified output will be passed through as is, or be made -//! active high. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_outputinvert) || defined(BUILD_ALL) || defined(DOXYGEN) -void -PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits, - tBoolean bInvert) -{ - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT | - PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT))); - - // - // Read the module's INVERT output control register, and set or clear - // the requested bits. - // - if(bInvert == true) - { - HWREG(ulBase + PWM_O_INVERT) |= ulPWMOutBits; - } - else - { - HWREG(ulBase + PWM_O_INVERT) &= ~(ulPWMOutBits); - } -} -#endif - -//***************************************************************************** -// -//! Specifies the state of PWM outputs in response to a fault condition. -//! -//! \param ulBase is the base address of the PWM module. -//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the -//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT, -//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, or \b PWM_OUT_5_BIT. -//! \param bFaultKill determines if the signal is killed or passed through -//! during an active fault condition. -//! -//! This function sets the fault handling characteristics of the selected PWM -//! outputs. The outputs are selected using the parameter \e ulPWMOutBits. -//! The parameter \e bFaultKill determines the fault handling characteristics -//! for the selected outputs. If \e bFaultKill is \b true, then the selected -//! outputs will be made inactive. If \e bFaultKill is \b false, then the -//! selected outputs are unaffected by the detected fault. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_outputfault) || defined(BUILD_ALL) || defined(DOXYGEN) -void -PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits, - tBoolean bFaultKill) -{ - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT | - PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT))); - - // - // Read the module's FAULT output control register, and set or clear - // the requested bits. - // - if(bFaultKill == true) - { - HWREG(ulBase + PWM_O_FAULT) |= ulPWMOutBits; - } - else - { - HWREG(ulBase + PWM_O_FAULT) &= ~(ulPWMOutBits); - } -} -#endif - -//***************************************************************************** -// -//! Registers an interrupt handler for the specified PWM generator block. -//! -//! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator in question. -//! \param pfnIntHandler is a pointer to the function to be called when the PWM -//! generator interrupt occurs. -//! -//! This function will ensure that the interrupt handler specified by -//! \e pfnIntHandler is called when an interrupt is detected for the specified -//! PWM generator block. This function will also enable the corresponding -//! PWM generator interrupt in the interrupt controller; individual generator -//! interrupts and interrupt sources must be enabled with PWMIntEnable() and -//! PWMGenIntTrigEnable(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_genintregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen, - void (*pfnIntHandler)(void)) -{ - unsigned long ulInt; - - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || - (ulGen == PWM_GEN_2)); - - // - // Get the interrupt number associated with the specified generator. - // - ulInt = INT_PWM0 + (ulGen >> 6) - 1; - - // - // Register the interrupt handler. - // - IntRegister(ulInt, pfnIntHandler); - - // - // Enable the PWMx interrupt. - // - IntEnable(ulInt); -} -#endif - -//***************************************************************************** -// -//! Removes an interrupt handler for the specified PWM generator block. -//! -//! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator in question. -//! -//! This function will unregister the interrupt handler for the specified -//! PWM generator block. This function will also disable the corresponding -//! PWM generator interrupt in the interrupt controller; individual generator -//! interrupts and interrupt sources must be disabled with PWMIntDisable() and -//! PWMGenIntTrigDisable(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_genintunregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen) -{ - unsigned long ulInt; - - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || - (ulGen == PWM_GEN_2)); - - // - // Get the interrupt number associated with the specified generator. - // - ulInt = INT_PWM0 + (ulGen >> 6) - 1; - - // - // Disable the PWMx interrupt. - // - IntDisable(ulInt); - - // - // Unregister the interrupt handler. - // - IntUnregister(ulInt); -} -#endif - -//***************************************************************************** -// -//! Registers an interrupt handler for a fault condition detected in a PWM -//! module. -//! -//! \param ulBase is the base address of the PWM module. -//! \param pfnIntHandler is a pointer to the function to be called when the PWM -//! fault interrupt occurs. -//! -//! This function will ensure that the interrupt handler specified by -//! \e pfnIntHandler is called when a fault interrupt is detected for the -//! selected PWM module. This function will also enable the PWM fault -//! interrupt in the NVIC; the PWM fault interrupt must also be enabled at the -//! module level using PWMIntEnable(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_faultintregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -PWMFaultIntRegister(unsigned long ulBase, void (*pfnIntHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - - // - // Register the interrupt handler, returning an error if one occurs. - // - IntRegister(INT_PWM_FAULT, pfnIntHandler); - - // - // Enable the PWM fault interrupt. - // - IntEnable(INT_PWM_FAULT); -} -#endif - -//***************************************************************************** -// -//! Removes the PWM fault condition interrupt handler. -//! -//! \param ulBase is the base address of the PWM module. -//! -//! This function will remove the interrupt handler for a PWM fault interrupt -//! from the selected PWM module. This function will also disable the PWM -//! fault interrupt in the NVIC; the PWM fault interrupt must also be disabled -//! at the module level using PWMIntDisable(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_faultintunregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -PWMFaultIntUnregister(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - - // - // Disable the PWM fault interrupt. - // - IntDisable(INT_PWM_FAULT); - - // - // Unregister the interrupt handler, returning an error if one occurs. - // - IntUnregister(INT_PWM_FAULT); -} -#endif - -//***************************************************************************** -// -//! Enables interrupts and triggers for the specified PWM generator block. -//! -//! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator to have interrupts and triggers enabled. -//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. -//! \param ulIntTrig specifies the interrupts and triggers to be enabled. -//! -//! Unmasks the specified interrupt(s) and trigger(s) by setting the -//! specified bits of the interrupt/trigger enable register for the specified -//! PWM generator. The defined values for the bits are as follows: -//! -//! - PWM_INT_CNT_ZERO -//! - PWM_INT_CNT_LOAD -//! - PWM_INT_CMP_AU -//! - PWM_INT_CMP_AD -//! - PWM_INT_CMP_BU -//! - PWM_INT_CMP_BD -//! - PWM_TR_CNT_ZERO -//! - PWM_TR_CNT_LOAD -//! - PWM_TR_CMP_AU -//! - PWM_TR_CMP_AD -//! - PWM_TR_CMP_BU -//! - PWM_TR_CMP_BD -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_geninttrigenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen, - unsigned long ulIntTrig) -{ - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || - (ulGen == PWM_GEN_2)); - - // - // Enable the specified interrupts/triggers. - // - HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_INTEN) |= ulIntTrig; -} -#endif - -//***************************************************************************** -// -//! Disables interrupts for the specified PWM generator block. -//! -//! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator to have interrupts and triggers disabled. -//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. -//! \param ulIntTrig specifies the interrupts and triggers to be disabled. -//! -//! Masks the specified interrupt(s) and trigger(s) by clearing the -//! specified bits of the interrupt/trigger enable register for the specified -//! PWM generator. The defined values for the bits are as follows: -//! -//! - PWM_INT_CNT_ZERO -//! - PWM_INT_CNT_LOAD -//! - PWM_INT_CMP_AU -//! - PWM_INT_CMP_AD -//! - PWM_INT_CMP_BU -//! - PWM_INT_CMP_BD -//! - PWM_TR_CNT_ZERO -//! - PWM_TR_CNT_LOAD -//! - PWM_TR_CMP_AU -//! - PWM_TR_CMP_AD -//! - PWM_TR_CMP_BU -//! - PWM_TR_CMP_BD -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_geninttrigdisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen, - unsigned long ulIntTrig) -{ - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || - (ulGen == PWM_GEN_2)); - - // - // Disable the specified interrupts/triggers. - // - HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_INTEN) &= ~(ulIntTrig); -} -#endif - -//***************************************************************************** -// -//! Gets interrupt status for the specified PWM generator block. -//! -//! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator to query. Must be one of \b PWM_GEN_0, -//! \b PWM_GEN_1, or \b PWM_GEN_2. -//! \param bMasked specifies whether masked or raw interrupt status is -//! returned. -//! -//! If \e bMasked is set as \b true, then the masked interrupt status is -//! returned; otherwise, the raw interrupt status will be returned. -//! -//! \return Returns the contents of the interrupt status register, or the -//! contents of the raw interrupt status register, for the specified -//! PWM generator. -// -//***************************************************************************** -#if defined(GROUP_genintstatus) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen, tBoolean bMasked) -{ - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || - (ulGen == PWM_GEN_2)); - - // - // Compute the generator's base address. - // - ulGen = PWM_GEN_BADDR(ulBase, ulGen); - - // - // Read and return the specified generator's raw or enabled interrupt - // status. - // - if(bMasked == true) - { - return(HWREG(ulGen + PWM_O_X_ISC)); - } - else - { - return(HWREG(ulGen + PWM_O_X_RIS)); - } -} -#endif - -//***************************************************************************** -// -//! Clears the specified interrupt(s) for the specified PWM generator block. -//! -//! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator to query. Must be one of \b PWM_GEN_0, -//! \b PWM_GEN_1, or \b PWM_GEN_2. -//! \param ulInts specifies the interrupts to be cleared. -//! -//! Clears the specified interrupt(s) by writing a 1 to the specified bits -//! of the interrupt status register for the specified PWM generator. The -//! defined values for the bits are as follows: -//! -//! - PWM_INT_CNT_ZERO -//! - PWM_INT_CNT_LOAD -//! - PWM_INT_CMP_AU -//! - PWM_INT_CMP_AD -//! - PWM_INT_CMP_BU -//! - PWM_INT_CMP_BD -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_genintclear) || defined(BUILD_ALL) || defined(DOXYGEN) -void -PWMGenIntClear(unsigned long ulBase, unsigned long ulGen, unsigned long ulInts) -{ - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || - (ulGen == PWM_GEN_2)); - - // - // Clear the requested interrupts by writing ones to the specified bit - // of the module's interrupt enable register. - // - HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_ISC) = ulInts; -} -#endif - -//***************************************************************************** -// -//! Enables generator and fault interrupts for a PWM module. -//! -//! \param ulBase is the base address of the PWM module. -//! \param ulGenFault contains the interrupts to be enabled. Must be a logical -//! OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2, or -//! \b PWM_INT_FAULT. -//! -//! Unmasks the specified interrupt(s) by setting the specified bits of -//! the interrupt enable register for the selected PWM module. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault) -{ - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - - // - // Read the module's interrupt enable register, and enable interrupts - // for the specified PWM generators. - // - HWREG(ulBase + PWM_O_INTEN) |= ulGenFault; -} -#endif - -//***************************************************************************** -// -//! Disables generator and fault interrupts for a PWM module. -//! -//! \param ulBase is the base address of the PWM module. -//! \param ulGenFault contains the interrupts to be disabled. Must be a -//! logical OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2, -//! or \b PWM_INT_FAULT. -//! -//! Masks the specified interrupt(s) by clearing the specified bits of -//! the interrupt enable register for the selected PWM module. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault) -{ - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - - // - // Read the module's interrupt enable register, and disable interrupts - // for the specified PWM generators. - // - HWREG(ulBase + PWM_O_INTEN) &= ~(ulGenFault); -} -#endif - -//***************************************************************************** -// -//! Clears the fault interrupt for a PWM module. -//! -//! \param ulBase is the base address of the PWM module. -//! -//! Clears the fault interrupt by writing to the appropriate bit of the -//! interrupt status register for the selected PWM module. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_faultintclear) || defined(BUILD_ALL) || defined(DOXYGEN) -void -PWMFaultIntClear(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - - // - // Write the only writeable bit in the module's interrupt register. - // - HWREG(ulBase + PWM_O_ISC) = PWM_INT_INTFAULT; -} -#endif - -//***************************************************************************** -// -//! Gets the interrupt status for a PWM module. -//! -//! \param ulBase is the base address of the PWM module. -//! \param bMasked specifies whether masked or raw interrupt status is -//! returned. -//! -//! If \e bMasked is set as \b true, then the masked interrupt status is -//! returned; otherwise, the raw interrupt status will be returned. -//! -//! \return The current interrupt status, enumerated as a bit field of -//! \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2, and \b PWM_INT_FAULT. -//! -//***************************************************************************** -#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -PWMIntStatus(unsigned long ulBase, tBoolean bMasked) -{ - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - - // - // Read and return either the module's raw or enabled interrupt status. - // - if(bMasked == true) - { - return(HWREG(ulBase + PWM_O_ISC)); - } - else - { - return(HWREG(ulBase + PWM_O_RIS)); - } -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/pwm.h b/Demo/CORTEX_LM3S811_GCC/hw_include/pwm.h deleted file mode 100644 index db835bacd..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/pwm.h +++ /dev/null @@ -1,161 +0,0 @@ -//***************************************************************************** -// -// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __PWM_H__ -#define __PWM_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following defines are passed to PWMGenConfigure() as the ulConfig -// parameter and specify the configuration of the PWM generator. -// -//***************************************************************************** -#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode -#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode -#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates -#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates -#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode -#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode - -//***************************************************************************** -// -// Defines for enabling, disabling, and clearing PWM generator interrupts and -// triggers. -// -//***************************************************************************** -#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0 -#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD -#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U -#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D -#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U -#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D -#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0 -#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD -#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U -#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D -#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U -#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D - -//***************************************************************************** -// -// Defines for enabling, disabling, and clearing PWM interrupts. -// -//***************************************************************************** -#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt -#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt -#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt -#define PWM_INT_FAULT 0x00010000 // Fault interrupt - -//***************************************************************************** -// -// Defines to identify the generators within a module. -// -//***************************************************************************** -#define PWM_GEN_0 0x00000040 // Offset address of Gen0 -#define PWM_GEN_1 0x00000080 // Offset address of Gen1 -#define PWM_GEN_2 0x000000C0 // Offset address of Gen2 - -#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0 -#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1 -#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2 - -//***************************************************************************** -// -// Defines to identify the outputs within a module. -// -//***************************************************************************** -#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0 -#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1 -#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2 -#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3 -#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4 -#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5 - -#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0 -#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1 -#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2 -#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3 -#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4 -#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5 - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen, - unsigned long ulConfig); -extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen, - unsigned long ulPeriod); -extern unsigned long PWMGenPeriodGet(unsigned long ulBase, - unsigned long ulGen); -extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen); -extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen); -extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut, - unsigned long ulWidth); -extern unsigned long PWMPulseWidthGet(unsigned long ulBase, - unsigned long ulPWMOut); -extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen, - unsigned short usRise, unsigned short usFall); -extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen); -extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits); -extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits); -extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits, - tBoolean bEnable); -extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits, - tBoolean bInvert); -extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits, - tBoolean bFaultKill); -extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen, - void (*pfnIntHandler)(void)); -extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen); -extern void PWMFaultIntRegister(unsigned long ulBase, - void (*pfnIntHandler)(void)); -extern void PWMFaultIntUnregister(unsigned long ulBase); -extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen, - unsigned long ulIntTrig); -extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen, - unsigned long ulIntTrig); -extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen, - tBoolean bMasked); -extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen, - unsigned long ulInts); -extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault); -extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault); -extern void PWMFaultIntClear(unsigned long ulBase); -extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked); - -#ifdef __cplusplus -} -#endif - -#endif // __PWM_H__ diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/qei.c b/Demo/CORTEX_LM3S811_GCC/hw_include/qei.c deleted file mode 100644 index eb982de39..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/qei.c +++ /dev/null @@ -1,630 +0,0 @@ -//***************************************************************************** -// -// qei.c - Driver for the Quadrature Encoder with Index. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup qei_api -//! @{ -// -//***************************************************************************** - -#include "../hw_ints.h" -#include "../hw_memmap.h" -#include "../hw_qei.h" -#include "../hw_types.h" -#include "debug.h" -#include "interrupt.h" -#include "qei.h" - -//***************************************************************************** -// -//! Enables the quadrature encoder. -//! -//! \param ulBase is the base address of the quadrature encoder module. -//! -//! This will enable operation of the quadrature encoder module. It must be -//! configured before it is enabled. -//! -//! \sa QEIConfigure() -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -QEIEnable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == QEI_BASE); - - // - // Enable the QEI module. - // - HWREG(ulBase + QEI_O_CTL) |= QEI_CTL_ENABLE; -} -#endif - -//***************************************************************************** -// -//! Disables the quadrature encoder. -//! -//! \param ulBase is the base address of the quadrature encoder module. -//! -//! This will disable operation of the quadrature encoder module. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -QEIDisable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == QEI_BASE); - - // - // Disable the QEI module. - // - HWREG(ulBase + QEI_O_CTL) &= ~(QEI_CTL_ENABLE); -} -#endif - -//***************************************************************************** -// -//! Configures the quadrature encoder. -//! -//! \param ulBase is the base address of the quadrature encoder module. -//! \param ulConfig is the configuration for the quadrature encoder. See below -//! for a description of this parameter. -//! \param ulMaxPosition specifies the maximum position value. -//! -//! This will configure the operation of the quadrature encoder. The -//! \e ulConfig parameter provides the configuration of the encoder and is the -//! logical OR of several values: -//! -//! - \b QEI_CONFIG_CAPTURE_A or \b QEI_CONFIG_CAPTURE_A_B to specify if edges -//! on channel A or on both channels A and B should be counted by the -//! position integrator and velocity accumulator. -//! - \b QEI_CONFIG_NO_RESET or \b QEI_CONFIG_RESET_IDX to specify if the -//! position integrator should be reset when the index pulse is detected. -//! - \b QEI_CONFIG_QUADRATURE or \b QEI_CONFIG_CLOCK_DIR to specify if -//! quadrature signals are being provided on ChA and ChB, or if a direction -//! signal and a clock are being provided instead. -//! - \b QEI_CONFIG_NO_SWAP or \b QEI_CONFIG_SWAP to specify if the signals -//! provided on ChA and ChB should be swapped before being processed. -//! -//! \e ulMaxPosition is the maximum value of the position integrator, and is -//! the value used to reset the position capture when in index reset mode and -//! moving in the reverse (negative) direction. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_configure) || defined(BUILD_ALL) || defined(DOXYGEN) -void -QEIConfigure(unsigned long ulBase, unsigned long ulConfig, - unsigned long ulMaxPosition) -{ - // - // Check the arguments. - // - ASSERT(ulBase == QEI_BASE); - - // - // Write the new configuration to the hardware. - // - HWREG(ulBase + QEI_O_CTL) = ((HWREG(ulBase + QEI_O_CTL) & - ~(QEI_CTL_CAPMODE | QEI_CTL_RESMODE | - QEI_CTL_SIGMODE | QEI_CTL_SWAP)) | - ulConfig); - - // - // Set the maximum position. - // - HWREG(ulBase + QEI_O_MAXPOS) = ulMaxPosition; -} -#endif - -//***************************************************************************** -// -//! Gets the current encoder position. -//! -//! \param ulBase is the base address of the quadrature encoder module. -//! -//! This returns the current position of the encoder. Depending upon the -//! configuration of the encoder, and the incident of an index pulse, this -//! value may or may not contain the expected data (i.e. if in reset on index -//! mode, if an index pulse has not been encountered, the position counter will -//! not be aligned with the index pulse yet). -//! -//! \return The current position of the encoder. -// -//***************************************************************************** -#if defined(GROUP_positionget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -QEIPositionGet(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == QEI_BASE); - - // - // Return the current position counter. - // - return(HWREG(ulBase + QEI_O_POS)); -} -#endif - -//***************************************************************************** -// -//! Sets the current encoder position. -//! -//! \param ulBase is the base address of the quadrature encoder module. -//! \param ulPosition is the new position for the encoder. -//! -//! This sets the current position of the encoder; the encoder position will -//! then be measured relative to this value. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_positionset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -QEIPositionSet(unsigned long ulBase, unsigned long ulPosition) -{ - // - // Check the arguments. - // - ASSERT(ulBase == QEI_BASE); - - // - // Set the position counter. - // - HWREG(ulBase + QEI_O_POS) = ulPosition; -} -#endif - -//***************************************************************************** -// -//! Gets the current direction of rotation. -//! -//! \param ulBase is the base address of the quadrature encoder module. -//! -//! This returns the current direction of rotation. In this case, current -//! means the most recently detected direction of the encoder; it may not be -//! presently moving but this is the direction it last moved before it stopped. -//! -//! \return 1 if moving in the forward direction or -1 if moving in the reverse -//! direction. -// -//***************************************************************************** -#if defined(GROUP_directionget) || defined(BUILD_ALL) || defined(DOXYGEN) -long -QEIDirectionGet(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == QEI_BASE); - - // - // Return the direction of rotation. - // - return((HWREG(ulBase + QEI_O_STAT) & QEI_STAT_DIRECTION) ? -1 : 1); -} -#endif - -//***************************************************************************** -// -//! Gets the encoder error indicator. -//! -//! \param ulBase is the base address of the quadrature encoder module. -//! -//! This returns the error indicator for the quadrature encoder. It is an -//! error for both of the signals of the quadrature input to change at the same -//! time. -//! -//! \return true if an error has occurred and false otherwise. -// -//***************************************************************************** -#if defined(GROUP_errorget) || defined(BUILD_ALL) || defined(DOXYGEN) -tBoolean -QEIErrorGet(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == QEI_BASE); - - // - // Return the error indicator. - // - return((HWREG(ulBase + QEI_O_STAT) & QEI_STAT_ERROR) ? true : false); -} -#endif - -//***************************************************************************** -// -//! Enables the velocity capture. -//! -//! \param ulBase is the base address of the quadrature encoder module. -//! -//! This will enable operation of the velocity capture in the quadrature -//! encoder module. It must be configured before it is enabled. Velocity -//! capture will not occur if the quadrature encoder is not enabled. -//! -//! \sa QEIVelocityConfigure() and QEIEnable() -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_velocityenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -QEIVelocityEnable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == QEI_BASE); - - // - // Enable the velocity capture. - // - HWREG(ulBase + QEI_O_CTL) |= QEI_CTL_VELEN; -} -#endif - -//***************************************************************************** -// -//! Disables the velocity capture. -//! -//! \param ulBase is the base address of the quadrature encoder module. -//! -//! This will disable operation of the velocity capture in the quadrature -//! encoder module. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_velocitydisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -QEIVelocityDisable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == QEI_BASE); - - // - // Disable the velocity capture. - // - HWREG(ulBase + QEI_O_CTL) &= ~(QEI_CTL_VELEN); -} -#endif - -//***************************************************************************** -// -//! Configures the velocity capture. -//! -//! \param ulBase is the base address of the quadrature encoder module. -//! \param ulPreDiv specifies the predivider applied to the input quadrature -//! signal before it is counted; can be one of QEI_VELDIV_1, QEI_VELDIV_2, -//! QEI_VELDIV_4, QEI_VELDIV_8, QEI_VELDIV_16, QEI_VELDIV_32, QEI_VELDIV_64, or -//! QEI_VELDIV_128. -//! \param ulPeriod specifies the number of clock ticks over which to measure -//! the velocity; must be non-zero. -//! -//! This will configure the operation of the velocity capture portion of the -//! quadrature encoder. The position increment signal is predivided as -//! specified by \e ulPreDiv before being accumulated by the velocity capture. -//! The divided signal is accumulated over \e ulPeriod system clock before -//! being saved and resetting the accumulator. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_velocityconfigure) || defined(BUILD_ALL) || defined(DOXYGEN) -void -QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv, - unsigned long ulPeriod) -{ - // - // Check the arguments. - // - ASSERT(ulBase == QEI_BASE); - ASSERT(!(ulPreDiv & ~(QEI_CTL_VELDIV_M))); - ASSERT(ulPeriod != 0); - - // - // Set the velocity predivider. - // - HWREG(ulBase + QEI_O_CTL) = ((HWREG(ulBase + QEI_O_CTL) & - ~(QEI_CTL_VELDIV_M)) | ulPreDiv); - - // - // Set the timer period. - // - HWREG(ulBase + QEI_O_LOAD) = ulPeriod - 1; -} -#endif - -//***************************************************************************** -// -//! Gets the current encoder speed. -//! -//! \param ulBase is the base address of the quadrature encoder module. -//! -//! This returns the current speed of the encoder. The value returned is the -//! number of pulses detected in the specified time period; this number can be -//! multiplied by the number of time periods per second and divided by the -//! number of pulses per revolution to obtain the number of revolutions per -//! second. -//! -//! \return The number of pulses captured in the given time period. -// -//***************************************************************************** -#if defined(GROUP_velocityget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -QEIVelocityGet(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == QEI_BASE); - - // - // Return the speed capture value. - // - return(HWREG(ulBase + QEI_O_SPEED)); -} -#endif - -//***************************************************************************** -// -//! Registers an interrupt handler for the quadrature encoder interrupt. -//! -//! \param ulBase is the base address of the quadrature encoder module. -//! \param pfnHandler is a pointer to the function to be called when the -//! quadrature encoder interrupt occurs. -//! -//! This sets the handler to be called when a quadrature encoder interrupt -//! occurs. This will enable the global interrupt in the interrupt controller; -//! specific quadrature encoder interrupts must be enabled via QEIIntEnable(). -//! It is the interrupt handler's responsibility to clear the interrupt source -//! via QEIIntClear(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT(ulBase == QEI_BASE); - - // - // Register the interrupt handler, returning an error if an error occurs. - // - IntRegister(INT_QEI, pfnHandler); - - // - // Enable the quadrature encoder interrupt. - // - IntEnable(INT_QEI); -} -#endif - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the quadrature encoder interrupt. -//! -//! \param ulBase is the base address of the quadrature encoder module. -//! -//! This function will clear the handler to be called when a quadrature encoder -//! interrupt occurs. This will also mask off the interrupt in the interrupt -//! controller so that the interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -QEIIntUnregister(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == QEI_BASE); - - // - // Disable the interrupt. - // - IntDisable(INT_QEI); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_QEI); -} -#endif - -//***************************************************************************** -// -//! Enables individual quadrature encoder interrupt sources. -//! -//! \param ulBase is the base address of the quadrature encoder module. -//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. -//! Can be any of the QEI_INTERROR, QEI_INTDIR, QEI_INTTIMER, or QEI_INTINDEX -//! values. -//! -//! Enables the indicated quadrature encoder interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags) -{ - // - // Check the arguments. - // - ASSERT(ulBase == QEI_BASE); - - // - // Enable the specified interrupts. - // - HWREG(ulBase + QEI_O_INTEN) |= ulIntFlags; -} -#endif - -//***************************************************************************** -// -//! Disables individual quadrature encoder interrupt sources. -//! -//! \param ulBase is the base address of the quadrature encoder module. -//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. -//! Can be any of the QEI_INTERROR, QEI_INTDIR, QEI_INTTIMER, or QEI_INTINDEX -//! values. -//! -//! Disables the indicated quadrature encoder interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags) -{ - // - // Check the arguments. - // - ASSERT(ulBase == QEI_BASE); - - // - // Disable the specified interrupts. - // - HWREG(ulBase + QEI_O_INTEN) &= ~(ulIntFlags); -} -#endif - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \param ulBase is the base address of the quadrature encoder module. -//! \param bMasked is false if the raw interrupt status is required and true if -//! the masked interrupt status is required. -//! -//! This returns the interrupt status for the quadrature encoder module. -//! Either the raw interrupt status or the status of interrupts that are -//! allowed to reflect to the processor can be returned. -//! -//! \return The current interrupt status, enumerated as a bit field of -//! QEI_INTERROR, QEI_INTDIR, QEI_INTTIMER, and QEI_INTINDEX. -// -//***************************************************************************** -#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -QEIIntStatus(unsigned long ulBase, tBoolean bMasked) -{ - // - // Check the arguments. - // - ASSERT(ulBase == QEI_BASE); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(ulBase + QEI_O_ISC)); - } - else - { - return(HWREG(ulBase + QEI_O_RIS)); - } -} -#endif - -//***************************************************************************** -// -//! Clears quadrature encoder interrupt sources. -//! -//! \param ulBase is the base address of the quadrature encoder module. -//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. -//! Can be any of the QEI_INTERROR, QEI_INTDIR, QEI_INTTIMER, or QEI_INTINDEX -//! values. -//! -//! The specified quadrature encoder interrupt sources are cleared, so that -//! they no longer assert. This must be done in the interrupt handler to keep -//! it from being called again immediately upon exit. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) -void -QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags) -{ - // - // Check the arguments. - // - ASSERT(ulBase == QEI_BASE); - - // - // Clear the requested interrupt sources. - // - HWREG(ulBase + QEI_O_ISC) = ulIntFlags; -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/qei.h b/Demo/CORTEX_LM3S811_GCC/hw_include/qei.h deleted file mode 100644 index 3eaafaeef..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/qei.h +++ /dev/null @@ -1,104 +0,0 @@ -//***************************************************************************** -// -// qei.h - Prototypes for the Quadrature Encoder Driver. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __QEI_H__ -#define __QEI_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to QEIConfigure as the ulConfig paramater. -// -//***************************************************************************** -#define QEI_CONFIG_CAPTURE_A 0x00000000 // Count on ChA edges only -#define QEI_CONFIG_CAPTURE_A_B 0x00000008 // Count on ChA and ChB edges -#define QEI_CONFIG_NO_RESET 0x00000000 // Do not reset on index pulse -#define QEI_CONFIG_RESET_IDX 0x00000010 // Reset position on index pulse -#define QEI_CONFIG_QUADRATURE 0x00000000 // ChA and ChB are quadrature -#define QEI_CONFIG_CLOCK_DIR 0x00000004 // ChA and ChB are clock and dir -#define QEI_CONFIG_NO_SWAP 0x00000000 // Do not swap ChA and ChB -#define QEI_CONFIG_SWAP 0x00000002 // Swap ChA and ChB - -//***************************************************************************** -// -// Values that can be passed to QEIVelocityConfigure as the ulPreDiv parameter. -// -//***************************************************************************** -#define QEI_VELDIV_1 0x00000000 // Predivide by 1 -#define QEI_VELDIV_2 0x00000040 // Predivide by 2 -#define QEI_VELDIV_4 0x00000080 // Predivide by 4 -#define QEI_VELDIV_8 0x000000C0 // Predivide by 8 -#define QEI_VELDIV_16 0x00000100 // Predivide by 16 -#define QEI_VELDIV_32 0x00000140 // Predivide by 32 -#define QEI_VELDIV_64 0x00000180 // Predivide by 64 -#define QEI_VELDIV_128 0x000001C0 // Predivide by 128 - -//***************************************************************************** -// -// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts -// as the ulIntFlags parameter, and returned by QEIGetIntStatus. -// -//***************************************************************************** -#define QEI_INTERROR 0x00000008 // Phase error detected -#define QEI_INTDIR 0x00000004 // Direction change -#define QEI_INTTIMER 0x00000002 // Velocity timer expired -#define QEI_INTINDEX 0x00000001 // Index pulse detected - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void QEIEnable(unsigned long ulBase); -extern void QEIDisable(unsigned long ulBase); -extern void QEIConfigure(unsigned long ulBase, unsigned long ulConfig, - unsigned long ulMaxPosition); -extern unsigned long QEIPositionGet(unsigned long ulBase); -extern void QEIPositionSet(unsigned long ulBase, unsigned long ulPosition); -extern long QEIDirectionGet(unsigned long ulBase); -extern tBoolean QEIErrorGet(unsigned long ulBase); -extern void QEIVelocityEnable(unsigned long ulBase); -extern void QEIVelocityDisable(unsigned long ulBase); -extern void QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv, - unsigned long ulPeriod); -extern unsigned long QEIVelocityGet(unsigned long ulBase); -extern void QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); -extern void QEIIntUnregister(unsigned long ulBase); -extern void QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long QEIIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags); - -#ifdef __cplusplus -} -#endif - -#endif // __QEI_H__ diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/ssi.c b/Demo/CORTEX_LM3S811_GCC/hw_include/ssi.c deleted file mode 100644 index 095aaab33..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/ssi.c +++ /dev/null @@ -1,609 +0,0 @@ -//***************************************************************************** -// -// ssi.c - Driver for Synchronous Serial Interface. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup ssi_api -//! @{ -// -//***************************************************************************** - -#include "../hw_ints.h" -#include "../hw_memmap.h" -#include "../hw_ssi.h" -#include "../hw_types.h" -#include "debug.h" -#include "interrupt.h" -#include "ssi.h" -#include "sysctl.h" - -//***************************************************************************** -// -//! Configures the synchronous serial interface. -//! -//! \param ulBase specifies the SSI module base address. -//! \param ulProtocol specifies the data transfer protocol. -//! \param ulMode specifies the mode of operation. -//! \param ulBitRate specifies the clock rate. -//! \param ulDataWidth specifies number of bits transfered per frame. -//! -//! This function configures the synchronous serial interface. It sets -//! the SSI protocol, mode of operation, bit rate, and data width. -//! -//! The parameter \e ulProtocol defines the data frame format. The parameter -//! \e ulProtocol can be one of the following values: SSI_FRF_MOTO_MODE_0, -//! SSI_FRF_MOTO_MODE_1, SSI_FRF_MOTO_MODE_2, SSI_FRF_MOTO_MODE_3, -//! SSI_FRF_TI, or SSI_FRF_NMW. The Motorola frame formats imply the -//! following polarity and phase configurations: -//! 
-//! Polarity Phase       Mode
-//!   0       0   SSI_FRF_MOTO_MODE_0
-//!   0       1   SSI_FRF_MOTO_MODE_1
-//!   1       0   SSI_FRF_MOTO_MODE_2
-//!   1       1   SSI_FRF_MOTO_MODE_3
-//!
-//! -//! The parameter \e ulMode defines the operating mode of the SSI module. The -//! SSI module can operate as a master or slave; if a slave, the SSI can be -//! configured to disable output on its serial output line. The parameter -//! \e ulMode can be one of the following values: SSI_MODE_MASTER, -//! SSI_MODE_SLAVE, or SSI_MODE_SLAVE_OD. -//! -//! The parameter \e ulBitRate defines the bit rate for the SSI. This bit rate -//! must satisfy the following clock ratio criteria: -//! - FSSI >= 2 * bit rate (master mode) -//! - FSSI >= 12 * bit rate (slave modes) -//! -//! where FSSI is the frequency of the clock supplied to the SSI module. -//! -//! The parameter \e ulDataWidth defines the width of the data transfers. -//! The parameter \e ulDataWidth can be a value between 4 and 16, inclusive. -//! -//! The SSI clocking is dependent upon the system clock rate returned by -//! SysCtlClockGet(); if it does not return the correct system clock rate then -//! the SSI clock rate will be incorrect. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_config) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SSIConfig(unsigned long ulBase, unsigned long ulProtocol, unsigned long ulMode, - unsigned long ulBitRate, unsigned long ulDataWidth) -{ - unsigned long ulMaxBitRate; - unsigned long ulRegVal; - unsigned long ulPreDiv; - unsigned long ulSCR; - unsigned long ulSPH_SPO; - unsigned long ulClock; - - // - // Check the arguments. - // - ASSERT(ulBase == SSI_BASE); - ASSERT((ulProtocol == SSI_FRF_MOTO_MODE_0) || - (ulProtocol == SSI_FRF_MOTO_MODE_1) || - (ulProtocol == SSI_FRF_MOTO_MODE_2) || - (ulProtocol == SSI_FRF_MOTO_MODE_3) || - (ulProtocol == SSI_FRF_TI) || - (ulProtocol == SSI_FRF_NMW)); - ASSERT((ulMode == SSI_MODE_MASTER) || - (ulMode == SSI_MODE_SLAVE) || - (ulMode == SSI_MODE_SLAVE_OD)); - ASSERT((ulDataWidth >= 4) && (ulDataWidth <= 16)); - - // - // Get the processor clock rate. - // - ulClock = SysCtlClockGet(); - - // - // Validate the clock speed. - // - ASSERT(((ulMode == SSI_MODE_MASTER) && (ulBitRate <= (ulClock / 2))) || - ((ulMode != SSI_MODE_MASTER) && (ulBitRate <= (ulClock / 12)))); - ASSERT((ulClock / ulBitRate) <= (254 * 256)); - - // - // Set the mode. - // - ulRegVal = (ulMode == SSI_MODE_SLAVE_OD) ? SSI_CR1_SOD : 0; - ulRegVal |= (ulMode == SSI_MODE_MASTER) ? 0 : SSI_CR1_MS; - HWREG(ulBase + SSI_O_CR1) = ulRegVal; - - // - // Set the clock predivider. - // - ulMaxBitRate = ulClock / ulBitRate; - ulPreDiv = 0; - do - { - ulPreDiv += 2; - ulSCR = (ulMaxBitRate / ulPreDiv) - 1; - } - while(ulSCR > 255); - HWREG(ulBase + SSI_O_CPSR) = ulPreDiv; - - // - // Set protocol and clock rate. - // - ulSPH_SPO = ulProtocol << 6; - ulProtocol &= SSI_CR0_FRF_MASK; - ulRegVal = (ulSCR << 8) | ulSPH_SPO | ulProtocol | (ulDataWidth - 1); - HWREG(ulBase + SSI_O_CR0) = ulRegVal; -} -#endif - -//***************************************************************************** -// -//! Enables the synchronous serial interface. -//! -//! \param ulBase specifies the SSI module base address. -//! -//! This will enable operation of the synchronous serial interface. It must be -//! configured before it is enabled. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SSIEnable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == SSI_BASE); - - // - // Read-modify-write the enable bit. - // - HWREG(ulBase + SSI_O_CR1) |= SSI_CR1_SSE; -} -#endif - -//***************************************************************************** -// -//! Disables the synchronous serial interface. -//! -//! \param ulBase specifies the SSI module base address. -//! -//! This will disable operation of the synchronous serial interface. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SSIDisable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == SSI_BASE); - - // - // Read-modify-write the enable bit. - // - HWREG(ulBase + SSI_O_CR1) &= ~(SSI_CR1_SSE); -} -#endif - -//***************************************************************************** -// -//! Registers an interrupt handler for the synchronous serial interface. -//! -//! \param ulBase specifies the SSI module base address. -//! \param pfnHandler is a pointer to the function to be called when the -//! synchronous serial interface interrupt occurs. -//! -//! This sets the handler to be called when an SSI interrupt -//! occurs. This will enable the global interrupt in the interrupt controller; -//! specific SSI interrupts must be enabled via SSIIntEnable(). If necessary, -//! it is the interrupt handler's responsibility to clear the interrupt source -//! via SSIIntClear(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SSIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT(ulBase == SSI_BASE); - - // - // Register the interrupt handler, returning an error if an error occurs. - // - IntRegister(INT_SSI, pfnHandler); - - // - // Enable the synchronous serial interface interrupt. - // - IntEnable(INT_SSI); -} -#endif - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the synchronous serial interface. -//! -//! \param ulBase specifies the SSI module base address. -//! -//! This function will clear the handler to be called when a SSI -//! interrupt occurs. This will also mask off the interrupt in the interrupt -//! controller so that the interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SSIIntUnregister(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == SSI_BASE); - - // - // Disable the interrupt. - // - IntDisable(INT_SSI); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_SSI); -} -#endif - -//***************************************************************************** -// -//! Enables individual SSI interrupt sources. -//! -//! \param ulBase specifies the SSI module base address. -//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. -//! -//! Enables the indicated SSI interrupt sources. Only the sources that are -//! enabled can be reflected to the processor interrupt; disabled sources -//! have no effect on the processor. The parameter \e ulIntFlags Can be -//! any of the SSI_TXFF, SSI_RXFF, SSI_RXTO, or SSI_RXOR values. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags) -{ - // - // Check the arguments. - // - ASSERT(ulBase == SSI_BASE); - - // - // Enable the specified interrupts. - // - HWREG(ulBase + SSI_O_IM) |= ulIntFlags; -} -#endif - -//***************************************************************************** -// -//! Disables individual SSI interrupt sources. -//! -//! \param ulBase specifies the SSI module base address. -//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. -//! -//! Disables the indicated SSI interrupt sources. The parameter -//! \e ulIntFlags Can be any of the SSI_TXFF, SSI_RXFF, SSI_RXTO, -//! or SSI_RXOR values. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags) -{ - // - // Check the arguments. - // - ASSERT(ulBase == SSI_BASE); - - // - // Disable the specified interrupts. - // - HWREG(ulBase + SSI_O_IM) &= ~(ulIntFlags); -} -#endif - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \param ulBase specifies the SSI module base address. -//! \param bMasked is false if the raw interrupt status is required and -//! true if the masked interrupt status is required. -//! -//! This returns the interrupt status for the SSI module. -//! Either the raw interrupt status or the status of interrupts that are -//! allowed to reflect to the processor can be returned. -//! -//! \return The current interrupt status, enumerated as a bit field of -//! SSI_TXFF, SSI_RXFF, SSI_RXTO, and SSI_RXOR. -// -//***************************************************************************** -#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -SSIIntStatus(unsigned long ulBase, tBoolean bMasked) -{ - // - // Check the arguments. - // - ASSERT(ulBase == SSI_BASE); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(ulBase + SSI_O_MIS)); - } - else - { - return(HWREG(ulBase + SSI_O_RIS)); - } -} -#endif - -//***************************************************************************** -// -//! Clears SSI interrupt sources. -//! -//! \param ulBase specifies the SSI module base address. -//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. -//! -//! The specified SSI interrupt sources are cleared, so that -//! they no longer assert. This must be done in the interrupt handler to -//! keep it from being called again immediately upon exit. -//! The parameter \e ulIntFlags can consist of either or both the SSI_RXTO -//! and SSI_RXOR values. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags) -{ - // - // Check the arguments. - // - ASSERT(ulBase == SSI_BASE); - - // - // Clear the requested interrupt sources. - // - HWREG(ulBase + SSI_O_ICR) = ulIntFlags; -} -#endif - -//***************************************************************************** -// -//! Puts a data element into the SSI transmit FIFO. -//! -//! \param ulBase specifies the SSI module base address. -//! \param ulData data to be transmitted over the SSI interface. -//! -//! This function will place the supplied data into the transmit FIFO of -//! the specified SSI module. -//! -//! \note The upper 32 - N bits of the \e ulData will be discarded by the -//! hardware, where N is the data width as configured by SSIConfig(). For -//! example, if the interface is configured for 8 bit data width, the upper 24 -//! bits of \e ulData will be discarded. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_dataput) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SSIDataPut(unsigned long ulBase, unsigned long ulData) -{ - // - // Check the arguments. - // - ASSERT(ulBase == SSI_BASE); - ASSERT((ulData & (0xfffffffe << (HWREG(ulBase + SSI_O_CR0) & - SSI_CR0_DSS))) == 0); - - // - // Wait until there is space. - // - while(!(HWREG(ulBase + SSI_O_SR) & SSI_SR_TNF)) - { - } - - // - // Write the data to the SSI. - // - HWREG(ulBase + SSI_O_DR) = ulData; -} -#endif - -//***************************************************************************** -// -//! Puts a data element into the SSI transmit FIFO. -//! -//! \param ulBase specifies the SSI module base address. -//! \param ulData data to be transmitted over the SSI interface. -//! -//! This function will place the supplied data into the transmit FIFO of -//! the specified SSI module. If there is no space in the FIFO, then this -//! function will return a zero. -//! -//! \note The upper 32 - N bits of the \e ulData will be discarded by the -//! hardware, where N is the data width as configured by SSIConfig(). For -//! example, if the interface is configured for 8 bit data width, the upper 24 -//! bits of \e ulData will be discarded. -//! -//! \return Returns the number of elements written to the SSI transmit FIFO. -// -//***************************************************************************** -#if defined(GROUP_datanonblockingput) || defined(BUILD_ALL) || defined(DOXYGEN) -long -SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData) -{ - // - // Check the arguments. - // - ASSERT(ulBase == SSI_BASE); - ASSERT((ulData & (0xfffffffe << (HWREG(ulBase + SSI_O_CR0) & - SSI_CR0_DSS))) == 0); - - // - // Check for space to write. - // - if(HWREG(ulBase + SSI_O_SR) & SSI_SR_TNF) - { - HWREG(ulBase + SSI_O_DR) = ulData; - return(1); - } - else - { - return(0); - } -} -#endif - -//***************************************************************************** -// -//! Gets a data element from the SSI receive FIFO. -//! -//! \param ulBase specifies the SSI module base address. -//! \param pulData pointer to a storage location for data that was received -//! over the SSI interface. -//! -//! This function will get received data from the receive FIFO of the specified -//! SSI module, and place that data into the location specified by the -//! \e pulData parameter. -//! -//! \note Only the lower N bits of the value written to \e pulData will contain -//! valid data, where N is the data width as configured by SSIConfig(). For -//! example, if the interface is configured for 8 bit data width, only the -//! lower 8 bits of the value written to \e pulData will contain valid data. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_dataget) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SSIDataGet(unsigned long ulBase, unsigned long *pulData) -{ - // - // Check the arguments. - // - ASSERT(ulBase == SSI_BASE); - - // - // Wait until there is data to be read. - // - while(!(HWREG(ulBase + SSI_O_SR) & SSI_SR_RNE)) - { - } - - // - // Read data from SSI. - // - *pulData = HWREG(ulBase + SSI_O_DR); -} -#endif - -//***************************************************************************** -// -//! Gets a data element from the SSI receive FIFO. -//! -//! \param ulBase specifies the SSI module base address. -//! \param pulData pointer to a storage location for data that was received -//! over the SSI interface. -//! -//! This function will get received data from the receive FIFO of -//! the specified SSI module, and place that data into the location specified -//! by the \e ulData parameter. If there is no data in the FIFO, then this -//! function will return a zero. -//! -//! \note Only the lower N bits of the value written to \e pulData will contain -//! valid data, where N is the data width as configured by SSIConfig(). For -//! example, if the interface is configured for 8 bit data width, only the -//! lower 8 bits of the value written to \e pulData will contain valid data. -//! -//! \return Returns the number of elements read from the SSI receive FIFO. -// -//***************************************************************************** -#if defined(GROUP_datanonblockingget) || defined(BUILD_ALL) || defined(DOXYGEN) -long -SSIDataNonBlockingGet(unsigned long ulBase, unsigned long *pulData) -{ - // - // Check the arguments. - // - ASSERT(ulBase == SSI_BASE); - - // - // Check for data to read. - // - if(HWREG(ulBase + SSI_O_SR) & SSI_SR_RNE) - { - *pulData = HWREG(ulBase + SSI_O_DR); - return(1); - } - else - { - return(0); - } -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/ssi.h b/Demo/CORTEX_LM3S811_GCC/hw_include/ssi.h deleted file mode 100644 index 045d8cb02..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/ssi.h +++ /dev/null @@ -1,89 +0,0 @@ -//***************************************************************************** -// -// ssi.h - Prototypes for the Synchronous Serial Interface Driver. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __SSI_H__ -#define __SSI_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear -// as the ulIntFlags parameter, and returned by SSIIntStatus. -// -//***************************************************************************** -#define SSI_TXFF 0x00000008 // TX FIFO half empty or less -#define SSI_RXFF 0x00000004 // RX FIFO half full or less -#define SSI_RXTO 0x00000002 // RX timeout -#define SSI_RXOR 0x00000001 // RX overrun - -//***************************************************************************** -// -// Values that can be passed to SSIConfig. -// -//***************************************************************************** -#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 -#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 -#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 -#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 -#define SSI_FRF_TI 0x00000010 // TI frame format -#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format - -#define SSI_MODE_MASTER 0x00000000 // SSI master -#define SSI_MODE_SLAVE 0x00000001 // SSI slave -#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void SSIConfig(unsigned long ulBase, unsigned long ulProtocol, - unsigned long ulMode, unsigned long ulBitRate, - unsigned long ulDataWidth); -extern void SSIDataGet(unsigned long ulBase, unsigned long *pulData); -extern long SSIDataNonBlockingGet(unsigned long ulBase, - unsigned long *pulData); -extern void SSIDataPut(unsigned long ulBase, unsigned long ulData); -extern long SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData); -extern void SSIDisable(unsigned long ulBase); -extern void SSIEnable(unsigned long ulBase); -extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags); -extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); -extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void SSIIntUnregister(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __SSI_H__ diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/sysctl.c b/Demo/CORTEX_LM3S811_GCC/hw_include/sysctl.c deleted file mode 100644 index 539d0f76d..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/sysctl.c +++ /dev/null @@ -1,1889 +0,0 @@ -//***************************************************************************** -// -// sysctl.c - Driver for the system controller. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. ALl rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup sysctl_api -//! @{ -// -//***************************************************************************** - -#include "../hw_ints.h" -#include "../hw_memmap.h" -#include "../hw_nvic.h" -#include "../hw_sysctl.h" -#include "../hw_types.h" -#include "cpu.h" -#include "debug.h" -#include "interrupt.h" -#include "sysctl.h" - -//***************************************************************************** -// -// An array that maps the "peripheral set" number (which is stored in the upper -// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL DC? register that -// contains the peripheral present bit for that peripheral. -// -//***************************************************************************** -#if defined(GROUP_puldcregs) || defined(BUILD_ALL) -const unsigned long g_pulDCRegs[] = -{ - SYSCTL_DC1, - SYSCTL_DC2, - SYSCTL_DC4, - SYSCTL_DC1 -}; -#else -extern const unsigned long g_pulDCRegs[]; -#endif - -//***************************************************************************** -// -// An array that maps the "peripheral set" number (which is stored in the upper -// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_SRCR? register that -// controls the software reset for that peripheral. -// -//***************************************************************************** -#if defined(GROUP_pulsrcrregs) || defined(BUILD_ALL) -const unsigned long g_pulSRCRRegs[] = -{ - SYSCTL_SRCR0, - SYSCTL_SRCR1, - SYSCTL_SRCR2 -}; -#else -extern const unsigned long g_pulSRCRRegs[]; -#endif - -//***************************************************************************** -// -// An array that maps the "peripheral set" number (which is stored in the upper -// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_RCGC? register that -// controls the run-mode enable for that peripheral. -// -//***************************************************************************** -#if defined(GROUP_pulrcgcregs) || defined(BUILD_ALL) -const unsigned long g_pulRCGCRegs[] = -{ - SYSCTL_RCGC0, - SYSCTL_RCGC1, - SYSCTL_RCGC2 -}; -#else -extern const unsigned long g_pulRCGCRegs[]; -#endif - -//***************************************************************************** -// -// An array that maps the "peripheral set" number (which is stored in the upper -// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_SCGC? register that -// controls the sleep-mode enable for that peripheral. -// -//***************************************************************************** -#if defined(GROUP_pulscgcregs) || defined(BUILD_ALL) -const unsigned long g_pulSCGCRegs[] = -{ - SYSCTL_SCGC0, - SYSCTL_SCGC1, - SYSCTL_SCGC2 -}; -#else -extern const unsigned long g_pulSCGCRegs[]; -#endif - -//***************************************************************************** -// -// An array that maps the "peripheral set" number (which is stored in the upper -// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_DCGC? register that -// controls the deep-sleep-mode enable for that peripheral. -// -//***************************************************************************** -#if defined(GROUP_pulDCGCregs) || defined(BUILD_ALL) -const unsigned long g_pulDCGCRegs[] = -{ - SYSCTL_DCGC0, - SYSCTL_DCGC1, - SYSCTL_DCGC2 -}; -#else -extern const unsigned long g_pulDCGCRegs[]; -#endif - -//***************************************************************************** -// -// An array that maps the crystal number in RCC to a frequency. -// -//***************************************************************************** -#if defined(GROUP_pulxtals) || defined(BUILD_ALL) -const unsigned long g_pulXtals[] = -{ - 3579545, - 3686400, - 4000000, - 4096000, - 4915200, - 5000000, - 5120000, - 6000000, - 6144000, - 7372800, - 8000000, - 8192000 -}; -#else -extern const unsigned long g_pulXtals[]; -#endif - -//***************************************************************************** -// -//! Gets the size of the SRAM. -//! -//! This function determines the size of the SRAM on the Stellaris device. -//! -//! \return The total number of bytes of SRAM. -// -//***************************************************************************** -#if defined(GROUP_sramsizeget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -SysCtlSRAMSizeGet(void) -{ - // - // Compute the size of the SRAM. - // - return(((HWREG(SYSCTL_DC0) & SYSCTL_DC0_SRAMSZ_MASK) >> 8) + 0x100); -} -#endif - -//***************************************************************************** -// -//! Gets the size of the flash. -//! -//! This function determines the size of the flash on the Stellaris device. -//! -//! \return The total number of bytes of flash. -// -//***************************************************************************** -#if defined(GROUP_flashsizeget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -SysCtlFlashSizeGet(void) -{ - // - // Compute the size of the flash. - // - return(((HWREG(SYSCTL_DC0) & SYSCTL_DC0_FLASHSZ_MASK) << 11) + 0x800); -} -#endif - -//***************************************************************************** -// -//! Determines if a pin is present. -//! -//! \param ulPin is the pin in question. -//! -//! Determines if a particular pin is present in the device. The PWM, analog -//! comparators, ADC, and timers have a varying number of pins across members -//! of the Stellaris family; this will determine which are present on this -//! device. -//! -//! The \b ulPin argument must be only one of the following values: -//! \b SYSCTL_PIN_PWM0, \b SYSCTL_PIN_PWM1, \b SYSCTL_PIN_PWM2, -//! \b SYSCTL_PIN_PWM3, \b SYSCTL_PIN_PWM4, \b SYSCTL_PIN_PWM5, -//! \b SYSCTL_PIN_C0MINUS, \b SYSCTL_PIN_C0PLUS, \b SYSCTL_PIN_C0O, -//! \b SYSCTL_PIN_C1MINUS, \b SYSCTL_PIN_C1PLUS, \b SYSCTL_PIN_C1O, -//! \b SYSCTL_PIN_C2MINUS, \b SYSCTL_PIN_C2PLUS, \b SYSCTL_PIN_C2O, -//! \b SYSCTL_PIN_ADC0, \b SYSCTL_PIN_ADC1, \b SYSCTL_PIN_ADC2, -//! \b SYSCTL_PIN_ADC3, \b SYSCTL_PIN_ADC4, \b SYSCTL_PIN_ADC5, -//! \b SYSCTL_PIN_ADC6, \b SYSCTL_PIN_ADC7, \b SYSCTL_PIN_CCP0, -//! \b SYSCTL_PIN_CCP1, \b SYSCTL_PIN_CCP2, \b SYSCTL_PIN_CCP3, -//! \b SYSCTL_PIN_CCP4, \b SYSCTL_PIN_CCP5, or \b SYSCTL_PIN_32KHZ. -//! -//! \return Returns \b true if the specified pin is present and \b false if it -//! is not. -// -//***************************************************************************** -#if defined(GROUP_pinpresent) || defined(BUILD_ALL) || defined(DOXYGEN) -tBoolean -SysCtlPinPresent(unsigned long ulPin) -{ - // - // Check the arguments. - // - ASSERT((ulPin == SYSCTL_PIN_PWM0) || - (ulPin == SYSCTL_PIN_PWM1) || - (ulPin == SYSCTL_PIN_PWM2) || - (ulPin == SYSCTL_PIN_PWM3) || - (ulPin == SYSCTL_PIN_PWM4) || - (ulPin == SYSCTL_PIN_PWM5) || - (ulPin == SYSCTL_PIN_C0MINUS) || - (ulPin == SYSCTL_PIN_C0PLUS) || - (ulPin == SYSCTL_PIN_C0O) || - (ulPin == SYSCTL_PIN_C1MINUS) || - (ulPin == SYSCTL_PIN_C1PLUS) || - (ulPin == SYSCTL_PIN_C1O) || - (ulPin == SYSCTL_PIN_C2MINUS) || - (ulPin == SYSCTL_PIN_C2PLUS) || - (ulPin == SYSCTL_PIN_C2O) || - (ulPin == SYSCTL_PIN_ADC0) || - (ulPin == SYSCTL_PIN_ADC1) || - (ulPin == SYSCTL_PIN_ADC2) || - (ulPin == SYSCTL_PIN_ADC3) || - (ulPin == SYSCTL_PIN_ADC4) || - (ulPin == SYSCTL_PIN_ADC5) || - (ulPin == SYSCTL_PIN_ADC6) || - (ulPin == SYSCTL_PIN_ADC7) || - (ulPin == SYSCTL_PIN_CCP0) || - (ulPin == SYSCTL_PIN_CCP1) || - (ulPin == SYSCTL_PIN_CCP2) || - (ulPin == SYSCTL_PIN_CCP3) || - (ulPin == SYSCTL_PIN_CCP4) || - (ulPin == SYSCTL_PIN_CCP5) || - (ulPin == SYSCTL_PIN_32KHZ)) - - // - // Determine if this pin is present. - // - if(HWREG(SYSCTL_DC3) & ulPin) - { - return(true); - } - else - { - return(false); - } -} -#endif - -//***************************************************************************** -// -//! Determines if a peripheral is present. -//! -//! \param ulPeripheral is the peripheral in question. -//! -//! Determines if a particular peripheral is present in the device. Each -//! member of the Stellaris family has a different peripheral set; this will -//! determine which are present on this device. -//! -//! The \b ulPeripheral argument must be only one of the following values: -//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, -//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, -//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, -//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, -//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, -//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, -//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_MPU, \b SYSCTL_PERIPH_TEMP, or -//! \b SYSCTL_PERIPH_PLL. -//! -//! \return Returns \b true if the specified peripheral is present and \b false -//! if it is not. -// -//***************************************************************************** -#if defined(GROUP_peripheralpresent) || defined(BUILD_ALL) || defined(DOXYGEN) -tBoolean -SysCtlPeripheralPresent(unsigned long ulPeripheral) -{ - // - // Check the arguments. - // - ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || - (ulPeripheral == SYSCTL_PERIPH_ADC) || - (ulPeripheral == SYSCTL_PERIPH_WDOG) || - (ulPeripheral == SYSCTL_PERIPH_UART0) || - (ulPeripheral == SYSCTL_PERIPH_UART1) || - (ulPeripheral == SYSCTL_PERIPH_SSI) || - (ulPeripheral == SYSCTL_PERIPH_QEI) || - (ulPeripheral == SYSCTL_PERIPH_I2C) || - (ulPeripheral == SYSCTL_PERIPH_TIMER0) || - (ulPeripheral == SYSCTL_PERIPH_TIMER1) || - (ulPeripheral == SYSCTL_PERIPH_TIMER2) || - (ulPeripheral == SYSCTL_PERIPH_COMP0) || - (ulPeripheral == SYSCTL_PERIPH_COMP1) || - (ulPeripheral == SYSCTL_PERIPH_COMP2) || - (ulPeripheral == SYSCTL_PERIPH_GPIOA) || - (ulPeripheral == SYSCTL_PERIPH_GPIOB) || - (ulPeripheral == SYSCTL_PERIPH_GPIOC) || - (ulPeripheral == SYSCTL_PERIPH_GPIOD) || - (ulPeripheral == SYSCTL_PERIPH_GPIOE) || - (ulPeripheral == SYSCTL_PERIPH_MPU) || - (ulPeripheral == SYSCTL_PERIPH_TEMP) || - (ulPeripheral == SYSCTL_PERIPH_PLL)); - - // - // Read the correct DC register and determine if this peripheral exists. - // - if(HWREG(g_pulDCRegs[ulPeripheral >> 28]) & ulPeripheral & 0x0fffffff) - { - return(true); - } - else - { - return(false); - } -} -#endif - -//***************************************************************************** -// -//! Performs a software reset of a peripheral. -//! -//! \param ulPeripheral is the peripheral to reset. -//! -//! This function performs a software reset of the specified peripheral. An -//! individual peripheral reset signal is asserted for a brief period and then -//! deasserted, leaving the peripheral in a operating state but in its reset -//! condition. -//! -//! The \b ulPeripheral argument must be only one of the following values: -//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, -//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, -//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, -//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, -//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, -//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or -//! \b SYSCTL_PERIPH_GPIOE. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_peripheralreset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysCtlPeripheralReset(unsigned long ulPeripheral) -{ - volatile unsigned long ulDelay; - - // - // Check the arguments. - // - ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || - (ulPeripheral == SYSCTL_PERIPH_ADC) || - (ulPeripheral == SYSCTL_PERIPH_WDOG) || - (ulPeripheral == SYSCTL_PERIPH_UART0) || - (ulPeripheral == SYSCTL_PERIPH_UART1) || - (ulPeripheral == SYSCTL_PERIPH_SSI) || - (ulPeripheral == SYSCTL_PERIPH_QEI) || - (ulPeripheral == SYSCTL_PERIPH_I2C) || - (ulPeripheral == SYSCTL_PERIPH_TIMER0) || - (ulPeripheral == SYSCTL_PERIPH_TIMER1) || - (ulPeripheral == SYSCTL_PERIPH_TIMER2) || - (ulPeripheral == SYSCTL_PERIPH_COMP0) || - (ulPeripheral == SYSCTL_PERIPH_COMP1) || - (ulPeripheral == SYSCTL_PERIPH_COMP2) || - (ulPeripheral == SYSCTL_PERIPH_GPIOA) || - (ulPeripheral == SYSCTL_PERIPH_GPIOB) || - (ulPeripheral == SYSCTL_PERIPH_GPIOC) || - (ulPeripheral == SYSCTL_PERIPH_GPIOD) || - (ulPeripheral == SYSCTL_PERIPH_GPIOE)); - - // - // Put the peripheral into the reset state. - // - HWREG(g_pulSRCRRegs[ulPeripheral >> 28]) |= ulPeripheral & 0x0fffffff; - - // - // Delay for a little bit. - // - for(ulDelay = 0; ulDelay < 16; ulDelay++) - { - } - - // - // Take the peripheral out of the reset state. - // - HWREG(g_pulSRCRRegs[ulPeripheral >> 28]) &= ~(ulPeripheral); -} -#endif - -//***************************************************************************** -// -//! Enables a peripheral. -//! -//! \param ulPeripheral is the peripheral to enable. -//! -//! Peripherals are enabled with this function. At power-up, all peripherals -//! are disabled; they must be enabled in order to operate or respond to -//! register reads/writes. -//! -//! The \b ulPeripheral argument must be only one of the following values: -//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, -//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, -//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, -//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, -//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, -//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or -//! \b SYSCTL_PERIPH_GPIOE. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_peripheralenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysCtlPeripheralEnable(unsigned long ulPeripheral) -{ - // - // Check the arguments. - // - ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || - (ulPeripheral == SYSCTL_PERIPH_ADC) || - (ulPeripheral == SYSCTL_PERIPH_WDOG) || - (ulPeripheral == SYSCTL_PERIPH_UART0) || - (ulPeripheral == SYSCTL_PERIPH_UART1) || - (ulPeripheral == SYSCTL_PERIPH_SSI) || - (ulPeripheral == SYSCTL_PERIPH_QEI) || - (ulPeripheral == SYSCTL_PERIPH_I2C) || - (ulPeripheral == SYSCTL_PERIPH_TIMER0) || - (ulPeripheral == SYSCTL_PERIPH_TIMER1) || - (ulPeripheral == SYSCTL_PERIPH_TIMER2) || - (ulPeripheral == SYSCTL_PERIPH_COMP0) || - (ulPeripheral == SYSCTL_PERIPH_COMP1) || - (ulPeripheral == SYSCTL_PERIPH_COMP2) || - (ulPeripheral == SYSCTL_PERIPH_GPIOA) || - (ulPeripheral == SYSCTL_PERIPH_GPIOB) || - (ulPeripheral == SYSCTL_PERIPH_GPIOC) || - (ulPeripheral == SYSCTL_PERIPH_GPIOD) || - (ulPeripheral == SYSCTL_PERIPH_GPIOE)); - - // - // Enable this peripheral. - // - HWREG(g_pulRCGCRegs[ulPeripheral >> 28]) |= ulPeripheral & 0x0fffffff; -} -#endif - -//***************************************************************************** -// -//! Disables a peripheral. -//! -//! \param ulPeripheral is the peripheral to disable. -//! -//! Peripherals are disabled with this function. Once disabled, they will not -//! operate or respond to register reads/writes. -//! -//! The \b ulPeripheral argument must be only one of the following values: -//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, -//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, -//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, -//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, -//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, -//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or -//! \b SYSCTL_PERIPH_GPIOE. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_peripheraldisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysCtlPeripheralDisable(unsigned long ulPeripheral) -{ - // - // Check the arguments. - // - ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || - (ulPeripheral == SYSCTL_PERIPH_ADC) || - (ulPeripheral == SYSCTL_PERIPH_WDOG) || - (ulPeripheral == SYSCTL_PERIPH_UART0) || - (ulPeripheral == SYSCTL_PERIPH_UART1) || - (ulPeripheral == SYSCTL_PERIPH_SSI) || - (ulPeripheral == SYSCTL_PERIPH_QEI) || - (ulPeripheral == SYSCTL_PERIPH_I2C) || - (ulPeripheral == SYSCTL_PERIPH_TIMER0) || - (ulPeripheral == SYSCTL_PERIPH_TIMER1) || - (ulPeripheral == SYSCTL_PERIPH_TIMER2) || - (ulPeripheral == SYSCTL_PERIPH_COMP0) || - (ulPeripheral == SYSCTL_PERIPH_COMP1) || - (ulPeripheral == SYSCTL_PERIPH_COMP2) || - (ulPeripheral == SYSCTL_PERIPH_GPIOA) || - (ulPeripheral == SYSCTL_PERIPH_GPIOB) || - (ulPeripheral == SYSCTL_PERIPH_GPIOC) || - (ulPeripheral == SYSCTL_PERIPH_GPIOD) || - (ulPeripheral == SYSCTL_PERIPH_GPIOE)); - - // - // Disable this peripheral. - // - HWREG(g_pulRCGCRegs[ulPeripheral >> 28]) &= ~(ulPeripheral & 0x0fffffff); -} -#endif - -//***************************************************************************** -// -//! Enables a peripheral in sleep mode. -//! -//! \param ulPeripheral is the peripheral to enable in sleep mode. -//! -//! This function allows a peripheral to continue operating when the processor -//! goes into sleep mode. Since the clocking configuration of the device does -//! not change, any peripheral can safely continue operating while the -//! processor is in sleep mode, and can therefore wake the processor from sleep -//! mode. -//! -//! Sleep mode clocking of peripherals must be enabled via -//! SysCtlPeripheralClockGating(); if disabled, the peripheral sleep mode -//! configuration is maintained but has no effect when sleep mode is entered. -//! -//! The \b ulPeripheral argument must be only one of the following values: -//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, -//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, -//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, -//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, -//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, -//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or -//! \b SYSCTL_PERIPH_GPIOE. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_peripheralsleepenable) || defined(BUILD_ALL) || \ - defined(DOXYGEN) -void -SysCtlPeripheralSleepEnable(unsigned long ulPeripheral) -{ - // - // Check the arguments. - // - ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || - (ulPeripheral == SYSCTL_PERIPH_ADC) || - (ulPeripheral == SYSCTL_PERIPH_WDOG) || - (ulPeripheral == SYSCTL_PERIPH_UART0) || - (ulPeripheral == SYSCTL_PERIPH_UART1) || - (ulPeripheral == SYSCTL_PERIPH_SSI) || - (ulPeripheral == SYSCTL_PERIPH_QEI) || - (ulPeripheral == SYSCTL_PERIPH_I2C) || - (ulPeripheral == SYSCTL_PERIPH_TIMER0) || - (ulPeripheral == SYSCTL_PERIPH_TIMER1) || - (ulPeripheral == SYSCTL_PERIPH_TIMER2) || - (ulPeripheral == SYSCTL_PERIPH_COMP0) || - (ulPeripheral == SYSCTL_PERIPH_COMP1) || - (ulPeripheral == SYSCTL_PERIPH_COMP2) || - (ulPeripheral == SYSCTL_PERIPH_GPIOA) || - (ulPeripheral == SYSCTL_PERIPH_GPIOB) || - (ulPeripheral == SYSCTL_PERIPH_GPIOC) || - (ulPeripheral == SYSCTL_PERIPH_GPIOD) || - (ulPeripheral == SYSCTL_PERIPH_GPIOE)); - - // - // Enable this peripheral in sleep mode. - // - HWREG(g_pulSCGCRegs[ulPeripheral >> 28]) |= ulPeripheral & 0x0fffffff; -} -#endif - -//***************************************************************************** -// -//! Disables a peripheral in sleep mode. -//! -//! \param ulPeripheral is the peripheral to disable in sleep mode. -//! -//! This function causes a peripheral to stop operating when the processor goes -//! into sleep mode. Disabling peripherals while in sleep mode helps to lower -//! the current draw of the device. If enabled (via SysCtlPeripheralEnable()), -//! the peripheral will automatically resume operation when the processor -//! leaves sleep mode, maintaining its entire state from before sleep mode was -//! entered. -//! -//! Sleep mode clocking of peripherals must be enabled via -//! SysCtlPeripheralClockGating(); if disabled, the peripheral sleep mode -//! configuration is maintained but has no effect when sleep mode is entered. -//! -//! The \b ulPeripheral argument must be only one of the following values: -//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, -//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, -//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, -//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, -//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, -//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or -//! \b SYSCTL_PERIPH_GPIOE. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_peripheralsleepdisable) || defined(BUILD_ALL) || \ - defined(DOXYGEN) -void -SysCtlPeripheralSleepDisable(unsigned long ulPeripheral) -{ - // - // Check the arguments. - // - ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || - (ulPeripheral == SYSCTL_PERIPH_ADC) || - (ulPeripheral == SYSCTL_PERIPH_WDOG) || - (ulPeripheral == SYSCTL_PERIPH_UART0) || - (ulPeripheral == SYSCTL_PERIPH_UART1) || - (ulPeripheral == SYSCTL_PERIPH_SSI) || - (ulPeripheral == SYSCTL_PERIPH_QEI) || - (ulPeripheral == SYSCTL_PERIPH_I2C) || - (ulPeripheral == SYSCTL_PERIPH_TIMER0) || - (ulPeripheral == SYSCTL_PERIPH_TIMER1) || - (ulPeripheral == SYSCTL_PERIPH_TIMER2) || - (ulPeripheral == SYSCTL_PERIPH_COMP0) || - (ulPeripheral == SYSCTL_PERIPH_COMP1) || - (ulPeripheral == SYSCTL_PERIPH_COMP2) || - (ulPeripheral == SYSCTL_PERIPH_GPIOA) || - (ulPeripheral == SYSCTL_PERIPH_GPIOB) || - (ulPeripheral == SYSCTL_PERIPH_GPIOC) || - (ulPeripheral == SYSCTL_PERIPH_GPIOD) || - (ulPeripheral == SYSCTL_PERIPH_GPIOE)); - - // - // Disable this peripheral in sleep mode. - // - HWREG(g_pulSCGCRegs[ulPeripheral >> 28]) &= ~(ulPeripheral & 0x0fffffff); -} -#endif - -//***************************************************************************** -// -//! Enables a peripheral in deep-sleep mode. -//! -//! \param ulPeripheral is the peripheral to enable in deep-sleep mode. -//! -//! This function allows a peripheral to continue operating when the processor -//! goes into deep-sleep mode. Since the clocking configuration of the device -//! may change, not all peripherals can safely continue operating while the -//! processor is in sleep mode. Those that must run at a particular frequency -//! (such as a UART) will not work as expected if the clock changes. It is the -//! responsibility of the caller to make sensible choices. -//! -//! Deep-sleep mode clocking of peripherals must be enabled via -//! SysCtlPeripheralClockGating(); if disabled, the peripheral deep-sleep mode -//! configuration is maintained but has no effect when deep-sleep mode is -//! entered. -//! -//! The \b ulPeripheral argument must be one of the following values: -//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, -//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, -//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, -//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, -//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, -//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or -//! \b SYSCTL_PERIPH_GPIOE. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_peripheraldeepsleepenable) || defined(BUILD_ALL) || \ - defined(DOXYGEN) -void -SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral) -{ - // - // Check the arguments. - // - ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || - (ulPeripheral == SYSCTL_PERIPH_ADC) || - (ulPeripheral == SYSCTL_PERIPH_WDOG) || - (ulPeripheral == SYSCTL_PERIPH_UART0) || - (ulPeripheral == SYSCTL_PERIPH_UART1) || - (ulPeripheral == SYSCTL_PERIPH_SSI) || - (ulPeripheral == SYSCTL_PERIPH_QEI) || - (ulPeripheral == SYSCTL_PERIPH_I2C) || - (ulPeripheral == SYSCTL_PERIPH_TIMER0) || - (ulPeripheral == SYSCTL_PERIPH_TIMER1) || - (ulPeripheral == SYSCTL_PERIPH_TIMER2) || - (ulPeripheral == SYSCTL_PERIPH_COMP0) || - (ulPeripheral == SYSCTL_PERIPH_COMP1) || - (ulPeripheral == SYSCTL_PERIPH_COMP2) || - (ulPeripheral == SYSCTL_PERIPH_GPIOA) || - (ulPeripheral == SYSCTL_PERIPH_GPIOB) || - (ulPeripheral == SYSCTL_PERIPH_GPIOC) || - (ulPeripheral == SYSCTL_PERIPH_GPIOD) || - (ulPeripheral == SYSCTL_PERIPH_GPIOE)); - - // - // Enable this peripheral in deep-sleep mode. - // - HWREG(g_pulDCGCRegs[ulPeripheral >> 28]) |= ulPeripheral & 0x0fffffff; -} -#endif - -//***************************************************************************** -// -//! Disables a peripheral in deep-sleep mode. -//! -//! \param ulPeripheral is the peripheral to disable in deep-sleep mode. -//! -//! This function causes a peripheral to stop operating when the processor goes -//! into deep-sleep mode. Disabling peripherals while in deep-sleep mode helps -//! to lower the current draw of the device, and can keep peripherals that -//! require a particular clock frequency from operating when the clock changes -//! as a result of entering deep-sleep mode. If enabled (via -//! SysCtlPeripheralEnable()), the peripheral will automatically resume -//! operation when the processor leaves deep-sleep mode, maintaining its entire -//! state from before deep-sleep mode was entered. -//! -//! Deep-sleep mode clocking of peripherals must be enabled via -//! SysCtlPeripheralClockGating(); if disabled, the peripheral deep-sleep mode -//! configuration is maintained but has no effect when deep-sleep mode is -//! entered. -//! -//! The \b ulPeripheral argument must be one of the following values: -//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, -//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, -//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, -//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, -//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, -//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or -//! \b SYSCTL_PERIPH_GPIOE. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_peripheraldeepsleepdisable) || defined(BUILD_ALL) || \ - defined(DOXYGEN) -void -SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral) -{ - // - // Check the arguments. - // - ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || - (ulPeripheral == SYSCTL_PERIPH_ADC) || - (ulPeripheral == SYSCTL_PERIPH_WDOG) || - (ulPeripheral == SYSCTL_PERIPH_UART0) || - (ulPeripheral == SYSCTL_PERIPH_UART1) || - (ulPeripheral == SYSCTL_PERIPH_SSI) || - (ulPeripheral == SYSCTL_PERIPH_QEI) || - (ulPeripheral == SYSCTL_PERIPH_I2C) || - (ulPeripheral == SYSCTL_PERIPH_TIMER0) || - (ulPeripheral == SYSCTL_PERIPH_TIMER1) || - (ulPeripheral == SYSCTL_PERIPH_TIMER2) || - (ulPeripheral == SYSCTL_PERIPH_COMP0) || - (ulPeripheral == SYSCTL_PERIPH_COMP1) || - (ulPeripheral == SYSCTL_PERIPH_COMP2) || - (ulPeripheral == SYSCTL_PERIPH_GPIOA) || - (ulPeripheral == SYSCTL_PERIPH_GPIOB) || - (ulPeripheral == SYSCTL_PERIPH_GPIOC) || - (ulPeripheral == SYSCTL_PERIPH_GPIOD) || - (ulPeripheral == SYSCTL_PERIPH_GPIOE)); - - // - // Disable this peripheral in deep-sleep mode. - // - HWREG(g_pulDCGCRegs[ulPeripheral >> 28]) &= ~(ulPeripheral & 0x0fffffff); -} -#endif - -//***************************************************************************** -// -//! Controls peripheral clock gating in sleep and deep-sleep mode. -//! -//! \param bEnable is a boolean that is \b true if the sleep and deep-sleep -//! peripheral configuration should be used and \b false if not. -//! -//! This function controls how peripherals are clocked when the processor goes -//! into sleep or deep-sleep mode. By default, the peripherals are clocked the -//! same as in run mode; if peripheral clock gating is enabled they are clocked -//! according to the configuration set by SysCtlPeripheralSleepEnable(), -//! SysCtlPeripheralSleepDisable(), SysCtlPeripheralDeepSleepEnable(), and -//! SysCtlPeripheralDeepSleepDisable(). -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_peripheralclockgating) || defined(BUILD_ALL) || \ - defined(DOXYGEN) -void -SysCtlPeripheralClockGating(tBoolean bEnable) -{ - // - // Enable peripheral clock gating as requested. - // - if(bEnable) - { - HWREG(SYSCTL_RCC) |= SYSCTL_RCC_ACG; - } - else - { - HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_ACG); - } -} -#endif - -//***************************************************************************** -// -//! Registers an interrupt handler for the system control interrupt. -//! -//! \param pfnHandler is a pointer to the function to be called when the system -//! control interrupt occurs. -//! -//! This sets the handler to be called when a system control interrupt occurs. -//! This will enable the global interrupt in the interrupt controller; specific -//! system control interrupts must be enabled via SysCtlIntEnable(). It is the -//! interrupt handler's responsibility to clear the interrupt source via -//! SysCtlIntClear(). -//! -//! System control can generate interrupts when the PLL achieves lock, if the -//! internal LDO current limit is exceeded, if the internal oscillator fails, -//! if the main oscillator fails, if the internal LDO output voltage droops too -//! much, if the external voltage droops too much, or if the PLL fails. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysCtlIntRegister(void (*pfnHandler)(void)) -{ - // - // Register the interrupt handler, returning an error if an error occurs. - // - IntRegister(INT_SYSCTL, pfnHandler); - - // - // Enable the system control interrupt. - // - IntEnable(INT_SYSCTL); -} -#endif - -//***************************************************************************** -// -//! Unregisters the interrupt handler for the system control interrupt. -//! -//! This function will clear the handler to be called when a system control -//! interrupt occurs. This will also mask off the interrupt in the interrupt -//! controller so that the interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysCtlIntUnregister(void) -{ - // - // Disable the interrupt. - // - IntDisable(INT_SYSCTL); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_SYSCTL); -} -#endif - -//***************************************************************************** -// -//! Enables individual system control interrupt sources. -//! -//! \param ulInts is a bit mask of the interrupt sources to be enabled. Must -//! be a logical OR of \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT, -//! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR, -//! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL. -//! -//! Enables the indicated system control interrupt sources. Only the sources -//! that are enabled can be reflected to the processor interrupt; disabled -//! sources have no effect on the processor. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysCtlIntEnable(unsigned long ulInts) -{ - // - // Enable the specified interrupts. - // - HWREG(SYSCTL_IMC) |= ulInts; -} -#endif - -//***************************************************************************** -// -//! Disables individual system control interrupt sources. -//! -//! \param ulInts is a bit mask of the interrupt sources to be disabled. Must -//! be a logical OR of \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT, -//! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR, -//! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL. -//! -//! Disables the indicated system control interrupt sources. Only the sources -//! that are enabled can be reflected to the processor interrupt; disabled -//! sources have no effect on the processor. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysCtlIntDisable(unsigned long ulInts) -{ - // - // Disable the specified interrupts. - // - HWREG(SYSCTL_IMC) &= ~(ulInts); -} -#endif - -//***************************************************************************** -// -//! Clears system control interrupt sources. -//! -//! \param ulInts is a bit mask of the interrupt sources to be cleared. Must -//! be a logical OR of \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT, -//! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR, -//! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL. -//! -//! The specified system control interrupt sources are cleared, so that they no -//! longer assert. This must be done in the interrupt handler to keep it from -//! being called again immediately upon exit. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysCtlIntClear(unsigned long ulInts) -{ - // - // Clear the requested interrupt sources. - // - HWREG(SYSCTL_MISC) = ulInts; -} -#endif - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \param bMasked is false if the raw interrupt status is required and true if -//! the masked interrupt status is required. -//! -//! This returns the interrupt status for the system controller. Either the -//! raw interrupt status or the status of interrupts that are allowed to -//! reflect to the processor can be returned. -//! -//! \return The current interrupt status, enumerated as a bit field of -//! \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT, \b SYSCTL_INT_IOSC_FAIL, -//! \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR, \b SYSCTL_INT_BOR, and -//! \b SYSCTL_INT_PLL_FAIL. -// -//***************************************************************************** -#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -SysCtlIntStatus(tBoolean bMasked) -{ - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(SYSCTL_MISC)); - } - else - { - return(HWREG(SYSCTL_RIS)); - } -} -#endif - -//***************************************************************************** -// -//! Sets the output voltage of the LDO. -//! -//! \param ulVoltage is the required output voltage from the LDO. Must be one -//! of \b SYSCTL_LDO_2_25V, \b SYSCTL_LDO_2_30V, \b SYSCTL_LDO_2_35V, -//! \b SYSCTL_LDO_2_40V, \b SYSCTL_LDO_2_45V, \b SYSCTL_LDO_2_50V, -//! \b SYSCTL_LDO_2_55V, \b SYSCTL_LDO_2_60V, \b SYSCTL_LDO_2_65V, -//! \b SYSCTL_LDO_2_70V, or \b SYSCTL_LDO_2_75V. -//! -//! This function sets the output voltage of the LDO. The default voltage is -//! 2.5 V; it can be adjusted +/- 10%. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_ldoset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysCtlLDOSet(unsigned long ulVoltage) -{ - // - // Check the arguments. - // - ASSERT((ulVoltage == SYSCTL_LDO_2_25V) || - (ulVoltage == SYSCTL_LDO_2_30V) || - (ulVoltage == SYSCTL_LDO_2_35V) || - (ulVoltage == SYSCTL_LDO_2_40V) || - (ulVoltage == SYSCTL_LDO_2_45V) || - (ulVoltage == SYSCTL_LDO_2_50V) || - (ulVoltage == SYSCTL_LDO_2_55V) || - (ulVoltage == SYSCTL_LDO_2_60V) || - (ulVoltage == SYSCTL_LDO_2_65V) || - (ulVoltage == SYSCTL_LDO_2_70V) || - (ulVoltage == SYSCTL_LDO_2_75V)); - - // - // Set the LDO voltage to the requested value. - // - HWREG(SYSCTL_LDOPCTL) = ulVoltage; -} -#endif - -//***************************************************************************** -// -//! Gets the output voltage of the LDO. -//! -//! This function determines the output voltage of the LDO, as specified by the -//! control register. -//! -//! \return Returns the current voltage of the LDO; will be one of -//! \b SYSCTL_LDO_2_25V, \b SYSCTL_LDO_2_30V, \b SYSCTL_LDO_2_35V, -//! \b SYSCTL_LDO_2_40V, \b SYSCTL_LDO_2_45V, \b SYSCTL_LDO_2_50V, -//! \b SYSCTL_LDO_2_55V, \b SYSCTL_LDO_2_60V, \b SYSCTL_LDO_2_65V, -//! \b SYSCTL_LDO_2_70V, or \b SYSCTL_LDO_2_75V. -// -//***************************************************************************** -#if defined(GROUP_ldoget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -SysCtlLDOGet(void) -{ - // - // Return the LDO voltage setting. - // - return(HWREG(SYSCTL_LDOPCTL)); -} -#endif - -//***************************************************************************** -// -//! Configures the LDO failure control. -//! -//! \param ulConfig is the required LDO failure control setting; can be either -//! \b SYSCTL_LDOCFG_ARST or \b SYSCTL_LDOCFG_NORST. -//! -//! This function allows the LDO to be configured to cause a processor reset -//! when the output voltage becomes unregulated. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_ldoconfigset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysCtlLDOConfigSet(unsigned long ulConfig) -{ - // - // Check hte arguments. - // - ASSERT((ulConfig == SYSCTL_LDOCFG_ARST) || - (ulConfig == SYSCTL_LDOCFG_NORST)); - - // - // Set the reset control as requested. - // - HWREG(SYSCTL_LDOARST) = ulConfig; -} -#endif - -//***************************************************************************** -// -//! Resets the device. -//! -//! This function will perform a software reset of the entire device. The -//! processor and all peripherals will be reset and all device registers will -//! return to their default values (with the exception of the reset cause -//! register, which will maintain its current value but have the software reset -//! bit set as well). -//! -//! \return This function does not return. -// -//***************************************************************************** -#if defined(GROUP_reset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysCtlReset(void) -{ - // - // Perform a software reset request. This will cause the device to reset, - // no further code will be executed. - // - HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | NVIC_APINT_SYSRESETREQ; - - // - // The device should have reset, so this should never be reached. Just in - // case, loop forever. - // - while(1) - { - } -} -#endif - -//***************************************************************************** -// -//! Puts the processor into sleep mode. -//! -//! This function places the processor into sleep mode; it will not return -//! until the processor returns to run mode. The peripherals that are enabled -//! via SysCtlPeripheralSleepEnable() continue to operate and can wake up the -//! processor (if automatic clock gating is enabled with -//! SysCtlPeripheralClockGating(), otherwise all peripherals continue to -//! operate). -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_sleep) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysCtlSleep(void) -{ - // - // Wait for an interrupt. - // - CPUwfi(); -} -#endif - -//***************************************************************************** -// -//! Puts the processor into deep-sleep mode. -//! -//! This function places the processor into deep-sleep mode; it will not return -//! until the processor returns to run mode. The peripherals that are enabled -//! via SysCtlPeripheralDeepSleepEnable() continue to operate and can wake up -//! the processor (if automatic clock gating is enabled with -//! SysCtlPeripheralClockGating(), otherwise all peripherals continue to -//! operate). -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_deepsleep) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysCtlDeepSleep(void) -{ - // - // Enable deep-sleep. - // - HWREG(NVIC_SYS_CTRL) |= NVIC_SYS_CTRL_SLEEPDEEP; - - // - // Wait for an interrupt. - // - CPUwfi(); - - // - // Disable deep-sleep so that a future sleep will work correctly. - // - HWREG(NVIC_SYS_CTRL) &= ~(NVIC_SYS_CTRL_SLEEPDEEP); -} -#endif - -//***************************************************************************** -// -//! Gets the reason for a reset. -//! -//! This function will return the reason(s) for a reset. Since the reset -//! reasons are sticky until either cleared by software or an external reset, -//! multiple reset reasons may be returned if multiple resets have occurred. -//! The reset reason will be a logical OR of \b SYSCTL_CAUSE_LDO, -//! \b SYSCTL_CAUSE_SW, \b SYSCTL_CAUSE_WDOG, \b SYSCTL_CAUSE_BOR, -//! \b SYSCTL_CAUSE_POR, and/or \b SYSCTL_CAUSE_EXT. -//! -//! \return The reason(s) for a reset. -// -//***************************************************************************** -#if defined(GROUP_resetcauseget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -SysCtlResetCauseGet(void) -{ - // - // Return the reset reasons. - // - return(HWREG(SYSCTL_RESC)); -} -#endif - -//***************************************************************************** -// -//! Clears reset reasons. -//! -//! \param ulCauses are the reset causes to be cleared; must be a logical OR of -//! \b SYSCTL_CAUSE_LDO, \b SYSCTL_CAUSE_SW, \b SYSCTL_CAUSE_WDOG, -//! \b SYSCTL_CAUSE_BOR, \b SYSCTL_CAUSE_POR, and/or \b SYSCTL_CAUSE_EXT. -//! -//! This function clears the specified sticky reset reasons. Once cleared, -//! another reset for the same reason can be detected, and a reset for a -//! different reason can be distinguished (instead of having two reset causes -//! set). If the reset reason is used by an application, all reset causes -//! should be cleared after they are retrieved with SysCtlResetCauseGet(). -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_resetcauseclear) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysCtlResetCauseClear(unsigned long ulCauses) -{ - // - // Clear the given reset reasons. - // - HWREG(SYSCTL_RESC) &= ~(ulCauses); -} -#endif - -//***************************************************************************** -// -//! Configures the brown-out control. -//! -//! \param ulConfig is the desired configuration of the brown-out control. -//! Must be the logical OR of \b SYSCTL_BOR_RESET and/or -//! \b SYSCTL_BOR_RESAMPLE. -//! \param ulDelay is the number of internal oscillator cycles to wait before -//! resampling an asserted brown-out signal. This value only has meaning when -//! \b SYSCTL_BOR_RESAMPLE is set and must be less than 8192. -//! -//! This function configures how the brown-out control operates. It can detect -//! a brown-out by looking at only the brown-out output, or it can wait for it -//! to be active for two consecutive samples separated by a configurable time. -//! When it detects a brown-out condition, it can either reset the device or -//! generate a processor interrupt. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_brownoutconfigset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysCtlBrownOutConfigSet(unsigned long ulConfig, unsigned long ulDelay) -{ - // - // Check the arguments. - // - ASSERT(!(ulConfig & ~(SYSCTL_BOR_RESET | SYSCTL_BOR_RESAMPLE))); - ASSERT(ulDelay < 8192); - - // - // Configure the brown-out reset control. - // - HWREG(SYSCTL_PBORCTL) = (ulDelay << SYSCTL_PBORCTL_BOR_SH) | ulConfig; -} -#endif - -//***************************************************************************** -// -//! Sets the clocking of the device. -//! -//! \param ulConfig is the required configuration of the device clocking. -//! -//! This function configures the clocking of the device. The input crystal -//! frequency, oscillator to be used, use of the PLL, and the system clock -//! divider are all configured with this function. -//! -//! The \b ulConfig parameter is the logical OR of several different values, -//! many of which are grouped into sets where only one can be chosen. -//! -//! The system clock divider is chosen with one of the following values: -//! \b SYSCTL_SYSDIV_1, \b SYSCTL_SYSDIV_2, \b SYSCTL_SYSDIV_3, -//! \b SYSCTL_SYSDIV_4, \b SYSCTL_SYSDIV_5, \b SYSCTL_SYSDIV_6, -//! \b SYSCTL_SYSDIV_7, \b SYSCTL_SYSDIV_8, \b SYSCTL_SYSDIV_9, -//! \b SYSCTL_SYSDIV_10, \b SYSCTL_SYSDIV_11, \b SYSCTL_SYSDIV_12, -//! \b SYSCTL_SYSDIV_13, \b SYSCTL_SYSDIV_14, \b SYSCTL_SYSDIV_15, or -//! \b SYSCTL_SYSDIV_16. -//! -//! The use of the PLL is chosen with either \b SYSCTL_USE_PLL or -//! \b SYSCTL_USE_OSC. -//! -//! The external crystal frequency is chosen with one of the following values: -//! \b SYSCTL_XTAL_3_57MHZ, \b SYSCTL_XTAL_3_68MHZ, \b SYSCTL_XTAL_4MHZ, -//! \b SYSCTL_XTAL_4_09MHZ, \b SYSCTL_XTAL_4_91MHZ, \b SYSCTL_XTAL_5MHZ, -//! \b SYSCTL_XTAL_5_12MHZ, \b SYSCTL_XTAL_6MHZ, \b SYSCTL_XTAL_6_14MHZ, -//! \b SYSCTL_XTAL_7_37MHZ, \b SYSCTL_XTAL_8MHZ, or \b SYSCTL_XTAL_8_19MHZ. -//! -//! The oscillator source is chosen with one of the following values: -//! \b SYSCTL_OSC_MAIN, \b SYSCTL_OSC_INT, or \b SYSCTL_OSC_INT4. -//! -//! The internal and main oscillators are disabled with the -//! \b SYSCTL_INT_OSC_DIS and \b SYSCTL_MAIN_OSC_DIS flags, respectively. -//! The external oscillator must be enabled in order to use an external clock -//! source. Note that attempts to disable the oscillator used to clock the -//! device will be prevented by the hardware. -//! -//! To clock the system from an external source (such as an external crystal -//! oscillator), use \b SYSCTL_USE_OSC \b | \b SYSCTL_OSC_MAIN. To clock the -//! system from the main oscillator, use \b SYSCTL_USE_OSC \b | -//! \b SYSCTL_OSC_MAIN. To clock the system from the PLL, use -//! \b SYSCTL_USE_PLL \b | \b SYSCTL_OSC_MAIN, and select the appropriate -//! crystal with one of the \b SYSCTL_XTAL_xxx values. -//! -//! \note If selecting the PLL as the system clock source (i.e. via -//! \b SYSCTL_USE_PLL), this function will poll the PLL lock interrupt to -//! determine when the PLL has locked. If an interrupt handler for the -//! system control interrupt is in place, and it responds to and clears the -//! PLL lock interrupt, this function will delay until its timeout has occurred -//! instead of completing as soon as PLL lock is achieved. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_clockset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysCtlClockSet(unsigned long ulConfig) -{ - volatile unsigned long ulDelay; - unsigned long ulRCC; - - // - // Get the current value of the RCC register. - // - ulRCC = HWREG(SYSCTL_RCC); - - // - // Bypass the PLL and system clock dividers for now. - // - ulRCC |= SYSCTL_RCC_BYPASS; - ulRCC &= ~(SYSCTL_RCC_USE_SYSDIV); - - // - // Write the new RCC value. - // - HWREG(SYSCTL_RCC) = ulRCC; - - // - // Make sure that the PLL and system clock dividers are bypassed for now. - // - ulRCC |= SYSCTL_RCC_BYPASS; - ulRCC &= ~(SYSCTL_RCC_USE_SYSDIV); - - // - // Make sure that the required oscillators are enabled. For now, the - // previously enabled oscillators must be enabled along with the newly - // requested oscillators. - // - ulRCC &= (~(SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS) | - (ulConfig & (SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS))); - - // - // Set the new crystal value, oscillator source, and PLL configuration. - // - ulRCC &= ~(SYSCTL_RCC_XTAL_MASK | SYSCTL_RCC_OSCSRC_MASK | - SYSCTL_RCC_PWRDN | SYSCTL_RCC_OE); - ulRCC |= ulConfig & (SYSCTL_RCC_XTAL_MASK | SYSCTL_RCC_OSCSRC_MASK | - SYSCTL_RCC_PWRDN | SYSCTL_RCC_OE); - - // - // Clear the PLL lock interrupt. - // - HWREG(SYSCTL_MISC) = SYSCTL_INT_PLL_LOCK; - - // - // Write the new RCC value. - // - HWREG(SYSCTL_RCC) = ulRCC; - - // - // Wait for a bit so that new crystal value and oscillator source can take - // effect. One of the oscillators may need to be started as well. - // - for(ulDelay = 0; ulDelay < 16; ulDelay++) - { - } - - // - // Disable the appropriate oscillators. - // - ulRCC &= ~(SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS); - ulRCC |= ulConfig & (SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS); - - // - // Write the new RCC value. - // - HWREG(SYSCTL_RCC) = ulRCC; - - // - // Set the requested system divider. This will not get written - // immediately. - // - ulRCC &= ~(SYSCTL_RCC_SYSDIV_MASK | SYSCTL_RCC_USE_SYSDIV); - ulRCC |= ulConfig & (SYSCTL_RCC_SYSDIV_MASK | SYSCTL_RCC_USE_SYSDIV); - - // - // See if the PLL output is being used to clock the system. - // - if(!(ulConfig & SYSCTL_RCC_BYPASS)) - { - // - // Wait until the PLL has locked. - // - for(ulDelay = 32768; ulDelay > 0; ulDelay--) - { - if(HWREG(SYSCTL_RIS) & SYSCTL_INT_PLL_LOCK) - { - break; - } - } - - // - // Enable use of the PLL. - // - ulRCC &= ~(SYSCTL_RCC_BYPASS); - } - - // - // Write the final RCC value. - // - HWREG(SYSCTL_RCC) = ulRCC; - - // - // Delay for a little bit so that the system divider takes effect. - // - for(ulDelay = 0; ulDelay < 16; ulDelay++) - { - } -} -#endif - -//***************************************************************************** -// -//! Gets the processor clock rate. -//! -//! This function determines the clock rate of the processor clock. This is -//! also the clock rate of all the peripheral modules (with the exception of -//! PWM, which has its own clock divider). -//! -//! \note This will not return accurate results if SysCtlClockSet() has not -//! been called to configure the clocking of the device, or if the device is -//! directly clocked from a crystal (or a clock source) that is not one of the -//! supported crystal frequencies. In the later case, this function should be -//! modified to directly return the correct system clock rate. -//! -//! \return The processor clock rate. -// -//***************************************************************************** -#if defined(GROUP_clockget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -SysCtlClockGet(void) -{ - unsigned long ulRCC, ulPLL, ulClk; - - // - // Read RCC. - // - ulRCC = HWREG(SYSCTL_RCC); - - // - // Get the base clock rate. - // - switch(ulRCC & SYSCTL_RCC_OSCSRC_MASK) - { - // - // The main oscillator is the clock source. Determine its rate from - // the crystal setting field. - // - case SYSCTL_RCC_OSCSRC_MAIN: - { - ulClk = g_pulXtals[((ulRCC & SYSCTL_RCC_XTAL_MASK) >> - SYSCTL_RCC_XTAL_SHIFT) - - (SYSCTL_RCC_XTAL_3_57MHZ >> - SYSCTL_RCC_XTAL_SHIFT)]; - break; - } - - // - // The internal oscillator is the source clock. This is not an - // accurate clock (it is +/- 50%); what is used is the nominal. - // - case SYSCTL_RCC_OSCSRC_INT: - { - ulClk = 15000000; - break; - } - - // - // The internal oscillator divided by four is the source clock. This - // is not an accurate clock (it is +/- 50%); what is used is the - // nominal. - // - case SYSCTL_RCC_OSCSRC_INT4: - { - ulClk = 15000000 / 4; - break; - } - - // - // An unknown setting, so return a zero clock (i.e. an unknown clock - // rate). - // - default: - { - return(0); - } - } - - // - // See if the PLL is being used. - // - if(!(ulRCC & SYSCTL_RCC_BYPASS)) - { - // - // Get the PLL configuration. - // - ulPLL = HWREG(SYSCTL_PLLCFG); - - // - // Compute the PLL output frequency based on its input frequency. - // - ulClk = ((ulClk * (((ulPLL & SYSCTL_PLLCFG_F_MASK) >> - SYSCTL_PLLCFG_F_SHIFT) + 2)) / - (((ulPLL & SYSCTL_PLLCFG_R_MASK) >> - SYSCTL_PLLCFG_R_SHIFT) + 2)); - - // - // See if the optional output divide by 2 is being used. - // - if(ulPLL & SYSCTL_PLLCFG_OD_2) - { - ulClk /= 2; - } - - // - // See if the optional output divide by 4 is being used. - // - if(ulPLL & SYSCTL_PLLCFG_OD_4) - { - ulClk /= 4; - } - } - - // - // See if the system divider is being used. - // - if(ulRCC & SYSCTL_RCC_USE_SYSDIV) - { - // - // Adjust the clock rate by the system clock divider. - // - ulClk /= ((ulRCC & SYSCTL_RCC_SYSDIV_MASK) >> - SYSCTL_RCC_SYSDIV_SHIFT) + 1; - } - - // - // Return the computed clock rate. - // - return(ulClk); -} -#endif - -//***************************************************************************** -// -//! Sets the PWM clock configuration. -//! -//! \param ulConfig is the configuration for the PWM clock; it must be one of -//! \b SYSCTL_PWMDIV_1, \b SYSCTL_PWMDIV_2, \b SYSCTL_PWMDIV_4, -//! \b SYSCTL_PWMDIV_8, \b SYSCTL_PWMDIV_16, \b SYSCTL_PWMDIV_32, or -//! \b SYSCTL_PWMDIV_64. -//! -//! This function sets the rate of the clock provided to the PWM module as a -//! ratio of the processor clock. This clock is used by the PWM module to -//! generate PWM signals; its rate forms the basis for all PWM signals. -//! -//! \note The clocking of the PWM is dependent upon the system clock rate as -//! configured by SysCtlClockSet(). -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_pwmclockset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysCtlPWMClockSet(unsigned long ulConfig) -{ - // - // Check the arguments. - // - ASSERT((ulConfig == SYSCTL_PWMDIV_1) || - (ulConfig == SYSCTL_PWMDIV_2) || - (ulConfig == SYSCTL_PWMDIV_4) || - (ulConfig == SYSCTL_PWMDIV_8) || - (ulConfig == SYSCTL_PWMDIV_16) || - (ulConfig == SYSCTL_PWMDIV_32) || - (ulConfig == SYSCTL_PWMDIV_64)); - - // - // Check that there is a PWM block on this part. - // - ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_PWM); - - // - // Set the PWM clock configuration into the run-mode clock configuration - // register. - // - HWREG(SYSCTL_RCC) = ((HWREG(SYSCTL_RCC) & - ~(SYSCTL_RCC_USE_PWMDIV | SYSCTL_RCC_PWMDIV_MASK)) | - ulConfig); -} -#endif - -//***************************************************************************** -// -//! Gets the current PWM clock configuration. -//! -//! This function returns the current PWM clock configuration. -//! -//! \return The current PWM clock configuration; will be one of -//! \b SYSCTL_PWMDIV_1, \b SYSCTL_PWMDIV_2, \b SYSCTL_PWMDIV_4, -//! \b SYSCTL_PWMDIV_8, \b SYSCTL_PWMDIV_16, \b SYSCTL_PWMDIV_32, or -//! \b SYSCTL_PWMDIV_64. -// -//***************************************************************************** -#if defined(GROUP_pwmclockget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -SysCtlPWMClockGet(void) -{ - // - // Check that there is a PWM block on this part. - // - ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_PWM); - - // - // Return the current PWM clock configuration. - // - return(HWREG(SYSCTL_RCC) & - (SYSCTL_RCC_USE_PWMDIV | SYSCTL_RCC_PWMDIV_MASK)); -} -#endif - -//***************************************************************************** -// -//! Sets the sample rate of the ADC. -//! -//! \param ulSpeed is the desired sample rate of the ADC; must be one of -//! \b SYSCTL_ADCSPEED_1MSPS, \b SYSCTL_ADCSPEED_500KSPS, -//! \b SYSCTL_ADCSPEED_250KSPS, or \b SYSCTL_ADCSPEED_125KSPS. -//! -//! This function sets the rate at which the ADC samples are captured by the -//! ADC block. The sampling speed may be limited by the hardware, so the -//! sample rate may end up being slower than requested. SysCtlADCSpeedGet() -//! will return the actual speed in use. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_adcspeedset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysCtlADCSpeedSet(unsigned long ulSpeed) -{ - // - // Check the arguments. - // - ASSERT((ulSpeed == SYSCTL_ADCSPEED_1MSPS) || - (ulSpeed == SYSCTL_ADCSPEED_500KSPS) || - (ulSpeed == SYSCTL_ADCSPEED_250KSPS) || - (ulSpeed == SYSCTL_ADCSPEED_125KSPS)); - - // - // Check that there is an ADC block on this part. - // - ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_ADC); - - // - // Set the ADC speed in run, sleep, and deep-sleep mode. - // - HWREG(SYSCTL_RCGC0) = ((HWREG(SYSCTL_RCGC0) & ~(SYSCTL_SET0_ADCSPD_MASK)) | - ulSpeed); - HWREG(SYSCTL_SCGC0) = ((HWREG(SYSCTL_SCGC0) & ~(SYSCTL_SET0_ADCSPD_MASK)) | - ulSpeed); - HWREG(SYSCTL_DCGC0) = ((HWREG(SYSCTL_DCGC0) & ~(SYSCTL_SET0_ADCSPD_MASK)) | - ulSpeed); -} -#endif - -//***************************************************************************** -// -//! Gets the sample rate of the ADC. -//! -//! This function gets the current sample rate of the ADC. -//! -//! \return Returns the current ADC sample rate; will be one of -//! \b SYSCTL_ADCSPEED_1MSPS, \b SYSCTL_ADCSPEED_500KSPS, -//! \b SYSCTL_ADCSPEED_250KSPS, or \b SYSCTL_ADCSPEED_125KSPS. -// -//***************************************************************************** -#if defined(GROUP_adcspeedget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -SysCtlADCSpeedGet(void) -{ - // - // Check that there is an ADC block on this part. - // - ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_ADC); - - // - // Return the current ADC speed. - // - return(HWREG(SYSCTL_RCGC0) & SYSCTL_SET0_ADCSPD_MASK); -} -#endif - -//***************************************************************************** -// -//! Configures the internal oscillator verification timer. -//! -//! \param bEnable is a boolean that is \b true if the internal oscillator -//! verification timer should be enabled. -//! -//! This function allows the internal oscillator verification timer to be -//! enabled or disabled. When enabled, an interrupt will be generated if the -//! internal oscillator ceases to operate. -//! -//! \note Both oscillators (main and internal) must be enabled for this -//! verification timer to operate as the main oscillator will verify the -//! internal oscillator. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_boscverificationset) || defined(BUILD_ALL) || \ - defined(DOXYGEN) -void -SysCtlIOSCVerificationSet(tBoolean bEnable) -{ - // - // Enable or disable the internal oscillator verification timer as - // requested. - // - if(bEnable) - { - HWREG(SYSCTL_RCC) |= SYSCTL_RCC_IOSCVER; - } - else - { - HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_IOSCVER); - } -} -#endif - -//***************************************************************************** -// -//! Configures the main oscillator verification timer. -//! -//! \param bEnable is a boolean that is \b true if the main oscillator -//! verification timer should be enabled. -//! -//! This function allows the main oscillator verification timer to be enabled -//! or disabled. When enabled, an interrupt will be generated if the main -//! oscillator ceases to operate. -//! -//! \note Both oscillators (main and internal) must be enabled for this -//! verification timer to operate as the internal oscillator will verify the -//! main oscillator. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_moscverificationset) || defined(BUILD_ALL) || \ - defined(DOXYGEN) -void -SysCtlMOSCVerificationSet(tBoolean bEnable) -{ - // - // Enable or disable the main oscillator verification timer as requested. - // - if(bEnable) - { - HWREG(SYSCTL_RCC) |= SYSCTL_RCC_MOSCVER; - } - else - { - HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_MOSCVER); - } -} -#endif - -//***************************************************************************** -// -//! Configures the PLL verification timer. -//! -//! \param bEnable is a boolean that is \b true if the PLL verification timer -//! should be enabled. -//! -//! This function allows the PLL verification timer to be enabled or disabled. -//! When enabled, an interrupt will be generated if the PLL ceases to operate. -//! -//! \note The main oscillator must be enabled for this verification timer to -//! operate as it is used to check the PLL. Also, the verification timer -//! should be disabled while the PLL is being reconfigured via -//! SysCtlClockSet(). -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_pllverificationset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysCtlPLLVerificationSet(tBoolean bEnable) -{ - // - // Enable or disable the PLL verification timer as requested. - // - if(bEnable) - { - HWREG(SYSCTL_RCC) |= SYSCTL_RCC_PLLVER; - } - else - { - HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_PLLVER); - } -} -#endif - -//***************************************************************************** -// -//! Clears the clock verification status. -//! -//! This function clears the status of the clock verification timers, allowing -//! them to assert another failure if detected. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_clkverificationclear) || defined(BUILD_ALL) || \ - defined(DOXYGEN) -void -SysCtlClkVerificationClear(void) -{ - // - // Clear the clock verification. - // - HWREG(SYSCTL_CLKVCLR) = SYSCTL_CLKVCLR_CLR; - - // - // The bit does not self-reset, so clear it. - // - HWREG(SYSCTL_CLKVCLR) = 0; -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/sysctl.h b/Demo/CORTEX_LM3S811_GCC/hw_include/sysctl.h deleted file mode 100644 index 94b147084..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/sysctl.h +++ /dev/null @@ -1,285 +0,0 @@ -//***************************************************************************** -// -// sysctl.h - Prototypes for the system control driver. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __SYSCTL_H__ -#define __SYSCTL_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following are values that can be passed to the -// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(), -// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the -// ulPeripheral parameter. The peripherals in the fourth group (upper nibble -// is 3) can only be used with the SysCtlPeripheralPresent() API. -// -//***************************************************************************** -#define SYSCTL_PERIPH_PWM 0x00100000 // PWM -#define SYSCTL_PERIPH_ADC 0x00010000 // ADC -#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog -#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0 -#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1 -#define SYSCTL_PERIPH_SSI 0x10000010 // SSI -#define SYSCTL_PERIPH_QEI 0x10000100 // QEI -#define SYSCTL_PERIPH_I2C 0x10001000 // I2C -#define SYSCTL_PERIPH_TIMER0 0x10010000 // Timer 0 -#define SYSCTL_PERIPH_TIMER1 0x10020000 // Timer 1 -#define SYSCTL_PERIPH_TIMER2 0x10040000 // Timer 2 -#define SYSCTL_PERIPH_COMP0 0x11000000 // Analog comparator 0 -#define SYSCTL_PERIPH_COMP1 0x12000000 // Analog comparator 1 -#define SYSCTL_PERIPH_COMP2 0x14000000 // Analog comparator 2 -#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A -#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B -#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C -#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D -#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E -#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU -#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor -#define SYSCTL_PERIPH_PLL 0x30000010 // PLL - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlPinPresent() API -// as the ulPin parameter. -// -//***************************************************************************** -#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin -#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin -#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin -#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin -#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin -#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin -#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin -#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin -#define SYSCTL_PIN_C0O 0x00000100 // C0o pin -#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin -#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin -#define SYSCTL_PIN_C1O 0x00000800 // C1o pin -#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin -#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin -#define SYSCTL_PIN_C2O 0x00004000 // C2o pin -#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin -#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin -#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin -#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin -#define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin -#define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin -#define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin -#define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin -#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin -#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin -#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin -#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin -#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin -#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin -#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlLDOSet() API as -// the ulVoltage value, or returned by the SysCtlLDOGet() API. -// -//***************************************************************************** -#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V -#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V -#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V -#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V -#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V -#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V -#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V -#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V -#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V -#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V -#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlLDOConfigSet() API. -// -//***************************************************************************** -#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset -#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlIntEnable(), -// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask -// by the SysCtlIntStatus() API. -// -//***************************************************************************** -#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt -#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt -#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int -#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int -#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt -#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt -#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlResetCauseClear() -// API or returned by the SysCtlResetCauseGet() API. -// -//***************************************************************************** -#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset -#define SYSCTL_CAUSE_SW 0x00000010 // Software reset -#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset -#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset -#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset -#define SYSCTL_CAUSE_EXT 0x00000001 // External reset - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlBrownOutConfigSet() -// API as the ulConfig parameter. -// -//***************************************************************************** -#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting -#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlPWMClockSet() API -// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet() -// API. -// -//***************************************************************************** -#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1 -#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2 -#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4 -#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8 -#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16 -#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32 -#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64 - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlADCSpeedSet() API -// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet() -// API. -// -//***************************************************************************** -#define SYSCTL_ADCSPEED_1MSPS 0x00000300 // 1,000,000 samples per second -#define SYSCTL_ADCSPEED_500KSPS 0x00000200 // 500,000 samples per second -#define SYSCTL_ADCSPEED_250KSPS 0x00000100 // 250,000 samples per second -#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlClockSet() API as -// the ulConfig parameter. -// -//***************************************************************************** -#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1 -#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2 -#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3 -#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4 -#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5 -#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6 -#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7 -#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8 -#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9 -#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10 -#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11 -#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12 -#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13 -#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14 -#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15 -#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16 -#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock -#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock -#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz -#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz -#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz -#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz -#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz -#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz -#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz -#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz -#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz -#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz -#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz -#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz -#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc -#define SYSCTL_OSC_INT 0x00000010 // Oscillator source is int. osc -#define SYSCTL_OSC_INT4 0x00000020 // Oscillator source is int. osc /4 -#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator -#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern unsigned long SysCtlSRAMSizeGet(void); -extern unsigned long SysCtlFlashSizeGet(void); -extern tBoolean SysCtlPinPresent(unsigned long ulPin); -extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral); -extern void SysCtlPeripheralReset(unsigned long ulPeripheral); -extern void SysCtlPeripheralEnable(unsigned long ulPeripheral); -extern void SysCtlPeripheralDisable(unsigned long ulPeripheral); -extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral); -extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral); -extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral); -extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral); -extern void SysCtlPeripheralClockGating(tBoolean bEnable); -extern void SysCtlIntRegister(void (*pfnHandler)(void)); -extern void SysCtlIntUnregister(void); -extern void SysCtlIntEnable(unsigned long ulInts); -extern void SysCtlIntDisable(unsigned long ulInts); -extern void SysCtlIntClear(unsigned long ulInts); -extern unsigned long SysCtlIntStatus(tBoolean bMasked); -extern void SysCtlLDOSet(unsigned long ulVoltage); -extern unsigned long SysCtlLDOGet(void); -extern void SysCtlLDOConfigSet(unsigned long ulConfig); -extern void SysCtlReset(void); -extern void SysCtlSleep(void); -extern void SysCtlDeepSleep(void); -extern unsigned long SysCtlResetCauseGet(void); -extern void SysCtlResetCauseClear(unsigned long ulCauses); -extern void SysCtlBrownOutConfigSet(unsigned long ulConfig, - unsigned long ulDelay); -extern void SysCtlClockSet(unsigned long ulConfig); -extern unsigned long SysCtlClockGet(void); -extern void SysCtlPWMClockSet(unsigned long ulConfig); -extern unsigned long SysCtlPWMClockGet(void); -extern void SysCtlADCSpeedSet(unsigned long ulSpeed); -extern unsigned long SysCtlADCSpeedGet(void); -extern void SysCtlIOSCVerificationSet(tBoolean bEnable); -extern void SysCtlMOSCVerificationSet(tBoolean bEnable); -extern void SysCtlPLLVerificationSet(tBoolean bEnable); -extern void SysCtlClkVerificationClear(void); - -#ifdef __cplusplus -} -#endif - -#endif // __SYSCTL_H__ diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/systick.c b/Demo/CORTEX_LM3S811_GCC/hw_include/systick.c deleted file mode 100644 index 382533513..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/systick.c +++ /dev/null @@ -1,262 +0,0 @@ -//***************************************************************************** -// -// systick.c - Driver for the SysTick timer in NVIC. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup systick_api -//! @{ -// -//***************************************************************************** - -#include "../hw_ints.h" -#include "../hw_nvic.h" -#include "../hw_types.h" -#include "debug.h" -#include "interrupt.h" -#include "systick.h" - -//***************************************************************************** -// -//! Enables the SysTick counter. -//! -//! This will start the SysTick counter. If an interrupt handler has been -//! registered, it will be called when the SysTick counter rolls over. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysTickEnable(void) -{ - // - // Enable SysTick. - // - HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_CLK_SRC | NVIC_ST_CTRL_ENABLE; -} -#endif - -//***************************************************************************** -// -//! Disables the SysTick counter. -//! -//! This will stop the SysTick counter. If an interrupt handler has been -//! registered, it will no longer be called until SysTick is restarted. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysTickDisable(void) -{ - // - // Disable SysTick. - // - HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_ENABLE); -} -#endif - -//***************************************************************************** -// -//! Registers an interrupt handler for the SysTick interrupt. -//! -//! \param pfnHandler is a pointer to the function to be called when the -//! SysTick interrupt occurs. -//! -//! This sets the handler to be called when a SysTick interrupt occurs. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysTickIntRegister(void (*pfnHandler)(void)) -{ - // - // Register the interrupt handler, returning an error if an error occurs. - // - IntRegister(FAULT_SYSTICK, pfnHandler); - - // - // Enable the SysTick interrupt. - // - HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; -} -#endif - -//***************************************************************************** -// -//! Unregisters the interrupt handler for the SysTick interrupt. -//! -//! This function will clear the handler to be called when a SysTick interrupt -//! occurs. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysTickIntUnregister(void) -{ - // - // Disable the SysTick interrupt. - // - HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); - - // - // Unregister the interrupt handler. - // - IntUnregister(FAULT_SYSTICK); -} -#endif - -//***************************************************************************** -// -//! Enables the SysTick interrupt. -//! -//! This function will enable the SysTick interrupt, allowing it to be -//! reflected to the processor. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysTickIntEnable(void) -{ - // - // Enable the SysTick interrupt. - // - HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; -} -#endif - -//***************************************************************************** -// -//! Disables the SysTick interrupt. -//! -//! This function will disable the SysTick interrupt, preventing it from being -//! reflected to the processor. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysTickIntDisable(void) -{ - // - // Disable the SysTick interrupt. - // - HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); -} -#endif - -//***************************************************************************** -// -//! Sets the period of the SysTick counter. -//! -//! \param ulPeriod is the number of clock ticks in each period of the SysTick -//! counter; must be between 1 and 16,777,216, inclusive. -//! -//! This function sets the rate at which the SysTick counter wraps; this -//! equates to the number of processor clocks between interrupts. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_periodset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysTickPeriodSet(unsigned long ulPeriod) -{ - // - // Check the arguments. - // - ASSERT((ulPeriod > 0) && (ulPeriod <= 16777216)); - - // - // Set the period of the SysTick counter. - // - HWREG(NVIC_ST_RELOAD) = ulPeriod - 1; -} -#endif - -//***************************************************************************** -// -//! Gets the period of the SysTick counter. -//! -//! This function returns the rate at which the SysTick counter wraps; this -//! equates to the number of processor clocks between interrupts. -//! -//! \return Returns the period of the SysTick counter. -// -//***************************************************************************** -#if defined(GROUP_periodget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -SysTickPeriodGet(void) -{ - // - // Return the period of the SysTick counter. - // - return(HWREG(NVIC_ST_RELOAD) + 1); -} -#endif - -//***************************************************************************** -// -//! Gets the current value of the SysTick counter. -//! -//! This function returns the current value of the SysTick counter; this will -//! be a value between the period - 1 and zero, inclusive. -//! -//! \return Returns the current value of the SysTick counter. -// -//***************************************************************************** -#if defined(GROUP_valueget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -SysTickValueGet(void) -{ - // - // Return the current value of the SysTick counter. - // - return(HWREG(NVIC_ST_CURRENT)); -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/systick.h b/Demo/CORTEX_LM3S811_GCC/hw_include/systick.h deleted file mode 100644 index bfddfb16f..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/systick.h +++ /dev/null @@ -1,55 +0,0 @@ -//***************************************************************************** -// -// systick.h - Prototypes for the SysTick driver. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __SYSTICK_H__ -#define __SYSTICK_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void SysTickEnable(void); -extern void SysTickDisable(void); -extern void SysTickIntRegister(void (*pfnHandler)(void)); -extern void SysTickIntUnregister(void); -extern void SysTickIntEnable(void); -extern void SysTickIntDisable(void); -extern void SysTickPeriodSet(unsigned long ulPeriod); -extern unsigned long SysTickPeriodGet(void); -extern unsigned long SysTickValueGet(void); - -#ifdef __cplusplus -} -#endif - -#endif // __SYSTICK_H__ diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/timer.c b/Demo/CORTEX_LM3S811_GCC/hw_include/timer.c deleted file mode 100644 index 46ce19a30..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/timer.c +++ /dev/null @@ -1,1125 +0,0 @@ -//***************************************************************************** -// -// timer.c - Driver for the timer module. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup timer_api -//! @{ -// -//***************************************************************************** - -#include "../hw_ints.h" -#include "../hw_memmap.h" -#include "../hw_timer.h" -#include "../hw_types.h" -#include "debug.h" -#include "interrupt.h" -#include "timer.h" - -//***************************************************************************** -// -//! Enables the timer(s). -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer(s) to enable; must be one of \b TIMER_A, -//! \b TIMER_B, or \b TIMER_BOTH. -//! -//! This will enable operation of the timer module. The timer must be -//! configured before it is enabled. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -TimerEnable(unsigned long ulBase, unsigned long ulTimer) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - // - // Enable the timer(s) module. - // - HWREG(ulBase + TIMER_O_CTL) |= ulTimer & (TIMER_CTL_TAEN | TIMER_CTL_TBEN); -} -#endif - -//***************************************************************************** -// -//! Disables the timer(s). -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer(s) to disable; must be one of -//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. -//! -//! This will disable operation of the timer module. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -TimerDisable(unsigned long ulBase, unsigned long ulTimer) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - // - // Disable the timer module. - // - HWREG(ulBase + TIMER_O_CTL) &= ~(ulTimer & - (TIMER_CTL_TAEN | TIMER_CTL_TBEN)); -} -#endif - -//***************************************************************************** -// -//! Configures the timer(s). -//! -//! \param ulBase is the base address of the timer module. -//! \param ulConfig is the configuration for the timer. -//! -//! This function configures the operating mode of the timer(s). The timer -//! module is disabled before being configured, and is left in the disabled -//! state. The configuration is specified in \e ulConfig as one of the -//! following values: -//! -//! - \b TIMER_CFG_32_BIT_OS - 32-bit one shot timer -//! - \b TIMER_CFG_32_BIT_PER - 32-bit periodic timer -//! - \b TIMER_CFG_32_RTC - 32-bit real time clock timer -//! - \b TIMER_CFG_16_BIT_PAIR - Two 16-bit timers -//! -//! When configured for a pair of 16-bit timers, each timer is separately -//! configured. The first timer is configured by setting \e ulConfig to -//! the result of a logical OR operation between one of the following values -//! and \e ulConfig: -//! -//! - \b TIMER_CFG_A_ONE_SHOT - 16-bit one shot timer -//! - \b TIMER_CFG_A_PERIODIC - 16-bit periodic timer -//! - \b TIMER_CFG_A_CAP_COUNT - 16-bit edge count capture -//! - \b TIMER_CFG_A_CAP_TIME - 16-bit edge time capture -//! - \b TIMER_CFG_A_PWM - 16-bit PWM output -//! -//! Similarly, the second timer is configured by setting \e ulConfig to -//! the result of a logical OR operation between one of the corresponding -//! \b TIMER_CFG_B_* values and \e ulConfig. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_configure) || defined(BUILD_ALL) || defined(DOXYGEN) -void -TimerConfigure(unsigned long ulBase, unsigned long ulConfig) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - ASSERT((ulConfig == TIMER_CFG_32_BIT_OS) || - (ulConfig == TIMER_CFG_32_BIT_PER) || - (ulConfig == TIMER_CFG_32_RTC) || - ((ulConfig & 0xff000000) == TIMER_CFG_16_BIT_PAIR)); - ASSERT(((ulConfig & 0xff000000) != TIMER_CFG_16_BIT_PAIR) || - ((((ulConfig & 0x000000ff) == TIMER_CFG_A_ONE_SHOT) || - ((ulConfig & 0x000000ff) == TIMER_CFG_A_PERIODIC) || - ((ulConfig & 0x000000ff) == TIMER_CFG_A_CAP_COUNT) || - ((ulConfig & 0x000000ff) == TIMER_CFG_A_CAP_TIME) || - ((ulConfig & 0x000000ff) == TIMER_CFG_A_PWM)) && - (((ulConfig & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT) || - ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PERIODIC) || - ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_COUNT) || - ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_TIME) || - ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PWM)))); - - // - // Disable the timers. - // - HWREG(ulBase + TIMER_O_CTL) &= ~(TIMER_CTL_TAEN | TIMER_CTL_TBEN); - - // - // Set the global timer configuration. - // - HWREG(ulBase + TIMER_O_CFG) = ulConfig >> 24; - - // - // Set the configuration of the A and B timers. Note that the B timer - // configuration is ignored by the hardware in 32-bit modes. - // - HWREG(ulBase + TIMER_O_TAMR) = ulConfig & 255; - HWREG(ulBase + TIMER_O_TBMR) = (ulConfig >> 8) & 255; -} -#endif - -//***************************************************************************** -// -//! Controls the output level. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, -//! \b TIMER_B, or \b TIMER_BOTH. -//! \param bInvert specifies the output level. -//! -//! This function sets the PWM output level for the specified timer. If the -//! parameter \e bInvert is \b true, then the timer's output will be made -//! active low; otherwise, it will be made active high. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_controllevel) || defined(BUILD_ALL) || defined(DOXYGEN) -void -TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, - tBoolean bInvert) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - // - // Set the output levels as requested. - // - ulTimer &= TIMER_CTL_TAPWML | TIMER_CTL_TBPWML; - HWREG(ulBase + TIMER_O_CTL) = (bInvert ? - (HWREG(ulBase + TIMER_O_CTL) | ulTimer) : - (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer))); -} -#endif - -//***************************************************************************** -// -//! Enables or disables the trigger output. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer to adjust; must be one of \b TIMER_A, -//! \b TIMER_B, or \b TIMER_BOTH. -//! \param bEnable specifies the desired trigger state. -//! -//! This function controls the trigger output for the specified timer. If the -//! parameter \e bEnable is \b true, then the timer's output trigger is -//! enabled; otherwise it is disabled. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_controltrigger) || defined(BUILD_ALL) || defined(DOXYGEN) -void -TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, - tBoolean bEnable) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - // - // Set the trigger output as requested. - // - ulTimer &= TIMER_CTL_TAOTE | TIMER_CTL_TBOTE; - HWREG(ulBase + TIMER_O_CTL) = (bEnable ? - (HWREG(ulBase + TIMER_O_CTL) | ulTimer) : - (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer))); -} -#endif - -//***************************************************************************** -// -//! Controls the event type. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer(s) to be adjusted; must be one of -//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. -//! \param ulEvent specifies the type of event; must be one of -//! \b TIMER_EVENT_POS_EDGE, \b TIMER_EVENT_NEG_EDGE, or -//! \b TIMER_EVENT_BOTH_EDGES. -//! -//! This function sets the signal edge(s) that will trigger the timer when in -//! capture mode. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_controlevent) || defined(BUILD_ALL) || defined(DOXYGEN) -void -TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulEvent) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - // - // Set the event type. - // - ulEvent &= ulTimer & (TIMER_CTL_TAEVENT_MSK | TIMER_CTL_TBEVENT_MSK); - HWREG(ulBase + TIMER_O_CTL) = ((HWREG(ulBase + TIMER_O_CTL) & - ~(TIMER_CTL_TAEVENT_MSK | - TIMER_CTL_TBEVENT_MSK)) | ulEvent); -} -#endif - -//***************************************************************************** -// -//! Controls the stall handling. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer(s) to be adjusted; must be one of -//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. -//! \param bStall specifies the response to a stall signal. -//! -//! This function controls the stall response for the specified timer. If the -//! parameter \e bStall is \b true, then the timer will stop counting if the -//! processor enters debug mode; otherwise the timer will keep running while in -//! debug mode. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_controlstall) || defined(BUILD_ALL) || defined(DOXYGEN) -void -TimerControlStall(unsigned long ulBase, unsigned long ulTimer, - tBoolean bStall) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - // - // Set the stall mode. - // - ulTimer &= TIMER_CTL_TASTALL | TIMER_CTL_TBSTALL; - HWREG(ulBase + TIMER_O_CTL) = (bStall ? - (HWREG(ulBase + TIMER_O_CTL) | ulTimer) : - (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer))); -} -#endif - -//***************************************************************************** -// -//! Enable RTC counting. -//! -//! \param ulBase is the base address of the timer module. -//! -//! This function causes the timer to start counting when in RTC mode. If not -//! configured for RTC mode, this will do nothing. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_rtcenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -TimerRTCEnable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - - // - // Enable RTC counting. - // - HWREG(ulBase + TIMER_O_CTL) |= TIMER_CTL_RTCEN; -} -#endif - -//***************************************************************************** -// -//! Disable RTC counting. -//! -//! \param ulBase is the base address of the timer module. -//! -//! This function causes the timer to stop counting when in RTC mode. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_rtcdisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -TimerRTCDisable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - - // - // Disable RTC counting. - // - HWREG(ulBase + TIMER_O_CTL) &= ~(TIMER_CTL_RTCEN); -} -#endif - -//***************************************************************************** -// -//! Set the timer prescale value. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, -//! \b TIMER_B, or \b TIMER_BOTH. -//! \param ulValue is the timer prescale value; must be between 0 and 255, -//! inclusive. -//! -//! This function sets the value of the input clock prescaler. The prescaler -//! is only operational when in 16-bit mode and is used to extend the range of -//! the 16-bit timer modes. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_prescaleset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - ASSERT(ulValue < 256); - - // - // Set the timer A prescaler if requested. - // - if(ulTimer & TIMER_A) - { - HWREG(ulBase + TIMER_O_TAPR) = ulValue; - } - - // - // Set the timer B prescaler if requested. - // - if(ulTimer & TIMER_B) - { - HWREG(ulBase + TIMER_O_TBPR) = ulValue; - } -} -#endif - -//***************************************************************************** -// -//! Get the timer prescale value. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer; must be one of \b TIMER_A or -//! \b TIMER_B. -//! -//! This function gets the value of the input clock prescaler. The prescaler -//! is only operational when in 16-bit mode and is used to extend the range of -//! the 16-bit timer modes. -//! -//! \return The value of the timer prescaler. -// -//***************************************************************************** -#if defined(GROUP_prescaleget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -TimerPrescaleGet(unsigned long ulBase, unsigned long ulTimer) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - // - // Return the appropriate prescale value. - // - return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAPR) : - HWREG(ulBase + TIMER_O_TBPR)); -} -#endif - -//***************************************************************************** -// -//! Set the timer prescale match value. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, -//! \b TIMER_B, or \b TIMER_BOTH. -//! \param ulValue is the timer prescale match value; must be between 0 and -//! 255, inclusive. -//! -//! This function sets the value of the input clock prescaler match value. -//! When in a 16-bit mode that uses the counter match (edge count or PWM), the -//! prescale match effectively extends the range of the counter to 24-bits. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_prescalematchset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - ASSERT(ulValue < 256); - - // - // Set the timer A prescale match if requested. - // - if(ulTimer & TIMER_A) - { - HWREG(ulBase + TIMER_O_TAPMR) = ulValue; - } - - // - // Set the timer B prescale match if requested. - // - if(ulTimer & TIMER_B) - { - HWREG(ulBase + TIMER_O_TBPMR) = ulValue; - } -} -#endif - -//***************************************************************************** -// -//! Get the timer prescale match value. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer; must be one of \b TIMER_A or -//! \b TIMER_B. -//! -//! This function gets the value of the input clock prescaler match value. -//! When in a 16-bit mode that uses the counter match (edge count or PWM), the -//! prescale match effectively extends the range of the counter to 24-bits. -//! -//! \return The value of the timer prescale match. -// -//***************************************************************************** -#if defined(GROUP_prescalematchget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -TimerPrescaleMatchGet(unsigned long ulBase, unsigned long ulTimer) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - // - // Return the appropriate prescale match value. - // - return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAPMR) : - HWREG(ulBase + TIMER_O_TBPMR)); -} -#endif - -//***************************************************************************** -// -//! Sets the timer load value. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, -//! \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used when the -//! timer is configured for 32-bit operation. -//! \param ulValue is the load value. -//! -//! This function sets the timer load value; if the timer is running then the -//! value will be immediately loaded into the timer. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_loadset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - // - // Set the timer A load value if requested. - // - if(ulTimer & TIMER_A) - { - HWREG(ulBase + TIMER_O_TAILR) = ulValue; - } - - // - // Set the timer B load value if requested. - // - if(ulTimer & TIMER_B) - { - HWREG(ulBase + TIMER_O_TBILR) = ulValue; - } -} -#endif - -//***************************************************************************** -// -//! Gets the timer load value. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer; must be one of \b TIMER_A or -//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured -//! for 32-bit operation. -//! -//! This function gets the currently programmed interval load value for the -//! specified timer. -//! -//! \return Returns the load value for the timer. -// -//***************************************************************************** -#if defined(GROUP_loadget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -TimerLoadGet(unsigned long ulBase, unsigned long ulTimer) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B)); - - // - // Return the appropriate load value. - // - return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAILR) : - HWREG(ulBase + TIMER_O_TBILR)); -} -#endif - -//***************************************************************************** -// -//! Gets the current timer value. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer; must be one of \b TIMER_A or -//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured -//! for 32-bit operation. -//! -//! This function reads the current value of the specified timer. -//! -//! \return Returns the current value of the timer. -// -//***************************************************************************** -#if defined(GROUP_valueget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -TimerValueGet(unsigned long ulBase, unsigned long ulTimer) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B)); - - // - // Return the appropriate timer value. - // - return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAR) : - HWREG(ulBase + TIMER_O_TBR)); -} -#endif - -//***************************************************************************** -// -//! Sets the timer match value. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, -//! \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used when the -//! timer is configured for 32-bit operation. -//! \param ulValue is the match value. -//! -//! This function sets the match value for a timer. This is used in capture -//! count mode to determine when to interrupt the processor and in PWM mode to -//! determine the duty cycle of the output signal. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_matchset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - // - // Set the timer A match value if requested. - // - if(ulTimer & TIMER_A) - { - HWREG(ulBase + TIMER_O_TAMATCHR) = ulValue; - } - - // - // Set the timer B match value if requested. - // - if(ulTimer & TIMER_B) - { - HWREG(ulBase + TIMER_O_TBMATCHR) = ulValue; - } -} -#endif - -//***************************************************************************** -// -//! Gets the timer match value. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer; must be one of \b TIMER_A or -//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured -//! for 32-bit operation. -//! -//! This function gets the match value for the specified timer. -//! -//! \return Returns the match value for the timer. -// -//***************************************************************************** -#if defined(GROUP_matchget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -TimerMatchGet(unsigned long ulBase, unsigned long ulTimer) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B)); - - // - // Return the appropriate match value. - // - return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAMATCHR) : - HWREG(ulBase + TIMER_O_TBMATCHR)); -} -#endif - -//***************************************************************************** -// -//! Registers an interrupt handler for the timer interrupt. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer(s); must be one of \b TIMER_A, -//! \b TIMER_B, or \b TIMER_BOTH. -//! \param pfnHandler is a pointer to the function to be called when the timer -//! interrupt occurs. -//! -//! This sets the handler to be called when a timer interrupt occurs. This -//! will enable the global interrupt in the interrupt controller; specific -//! timer interrupts must be enabled via TimerIntEnable(). It is the interrupt -//! handler's responsibility to clear the interrupt source via TimerIntClear(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, - void (*pfnHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - // - // Get the interrupt number for this timer module. - // - ulBase = ((ulBase == TIMER0_BASE) ? INT_TIMER0A : - ((ulBase == TIMER1_BASE) ? INT_TIMER1A : INT_TIMER2A)); - - // - // Register an interrupt handler for timer A if requested. - // - if(ulTimer & TIMER_A) - { - // - // Register the interrupt handler. - // - IntRegister(ulBase, pfnHandler); - - // - // Enable the interrupt. - // - IntEnable(ulBase); - } - - // - // Register an interrupt handler for timer B if requested. - // - if(ulTimer & TIMER_B) - { - // - // Register the interrupt handler. - // - IntRegister(ulBase + 1, pfnHandler); - - // - // Enable the interrupt. - // - IntEnable(ulBase + 1); - } -} -#endif - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the timer interrupt. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer(s); must be one of \b TIMER_A, -//! \b TIMER_B, or \b TIMER_BOTH. -//! -//! This function will clear the handler to be called when a timer interrupt -//! occurs. This will also mask off the interrupt in the interrupt controller -//! so that the interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - // - // Get the interrupt number for this timer module. - // - ulBase = ((ulBase == TIMER0_BASE) ? INT_TIMER0A : - ((ulBase == TIMER1_BASE) ? INT_TIMER1A : INT_TIMER2A)); - - // - // Unregister the interrupt handler for timer A if requested. - // - if(ulTimer & TIMER_A) - { - // - // Disable the interrupt. - // - IntDisable(ulBase); - - // - // Unregister the interrupt handler. - // - IntUnregister(ulBase); - } - - // - // Unregister the interrupt handler for timer B if requested. - // - if(ulTimer & TIMER_B) - { - // - // Disable the interrupt. - // - IntDisable(ulBase + 1); - - // - // Unregister the interrupt handler. - // - IntUnregister(ulBase + 1); - } -} -#endif - -//***************************************************************************** -// -//! Enables individual timer interrupt sources. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. -//! -//! Enables the indicated timer interrupt sources. Only the sources that are -//! enabled can be reflected to the processor interrupt; disabled sources have -//! no effect on the processor. -//! -//! The parameter \e ulIntFlags must be the logical OR of any combination of -//! the following: -//! -//! - TIMER_CAPB_EVENT - Capture B event interrupt -//! - TIMER_CAPB_MATCH - Capture B match interrupt -//! - TIMER_TIMB_TIMEOUT - Timer B timeout interrupt -//! - TIMER_RTC_MATCH - RTC interrupt mask -//! - TIMER_CAPA_EVENT - Capture A event interrupt -//! - TIMER_CAPA_MATCH - Capture A match interrupt -//! - TIMER_TIMA_TIMEOUT - Timer A timeout interrupt -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - - // - // Enable the specified interrupts. - // - HWREG(ulBase + TIMER_O_IMR) |= ulIntFlags; -} -#endif - -//***************************************************************************** -// -//! Disables individual timer interrupt sources. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. -//! -//! Disables the indicated timer interrupt sources. Only the sources that are -//! enabled can be reflected to the processor interrupt; disabled sources have -//! no effect on the processor. -//! -//! The parameter \e ulIntFlags has the same definition as the \e ulIntFlags -//! parameter to TimerIntEnable(). -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - - // - // Disable the specified interrupts. - // - HWREG(ulBase + TIMER_O_IMR) &= ~(ulIntFlags); -} -#endif - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \param ulBase is the base address of the timer module. -//! \param bMasked is false if the raw interrupt status is required and true if -//! the masked interrupt status is required. -//! -//! This returns the interrupt status for the timer module. Either the raw -//! interrupt status or the status of interrupts that are allowed to reflect to -//! the processor can be returned. -//! -//! \return The current interrupt status, enumerated as a bit field of -//! values described in TimerIntEnable(). -// -//***************************************************************************** -#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -TimerIntStatus(unsigned long ulBase, tBoolean bMasked) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - return(bMasked ? HWREG(ulBase + TIMER_O_MIS) : - HWREG(ulBase + TIMER_O_RIS)); -} -#endif - -//***************************************************************************** -// -//! Clears timer interrupt sources. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. -//! -//! The specified timer interrupt sources are cleared, so that they no longer -//! assert. This must be done in the interrupt handler to keep it from being -//! called again immediately upon exit. -//! -//! The parameter \e ulIntFlags has the same definition as the \e ulIntFlags -//! parameter to TimerIntEnable(). -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) -void -TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - - // - // Clear the requested interrupt sources. - // - HWREG(ulBase + TIMER_O_ICR) = ulIntFlags; -} -#endif - -//***************************************************************************** -// -//! Puts the timer into its reset state. -//! -//! \param ulBase is the base address of the timer module. -//! -//! The specified timer is disabled, and all its interrupts are disabled, -//! cleared, and unregistered. Then the timer registers are set to their reset -//! value. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_quiesce) || defined(BUILD_ALL) || defined(DOXYGEN) -void -TimerQuiesce(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - - // - // Disable the timer. - // - HWREG(ulBase + TIMER_O_CTL) = TIMER_RV_CTL; - - // - // Disable all the timer interrupts. - // - HWREG(ulBase + TIMER_O_IMR) = TIMER_RV_IMR; - - // - // Clear all the timer interrupts. - // - HWREG(ulBase + TIMER_O_ICR) = 0xFFFFFFFF; - - // - // Unregister the interrupt handler. This also disables interrupts to the - // core. - // - TimerIntUnregister(ulBase, TIMER_BOTH); - - // - // Set all the registers to their reset value. - // - HWREG(ulBase + TIMER_O_CFG) = TIMER_RV_CFG; - HWREG(ulBase + TIMER_O_TAMR) = TIMER_RV_TAMR; - HWREG(ulBase + TIMER_O_TBMR) = TIMER_RV_TBMR; - HWREG(ulBase + TIMER_O_RIS) = TIMER_RV_RIS; - HWREG(ulBase + TIMER_O_MIS) = TIMER_RV_MIS; - HWREG(ulBase + TIMER_O_TAILR) = TIMER_RV_TAILR; - HWREG(ulBase + TIMER_O_TBILR) = TIMER_RV_TBILR; - HWREG(ulBase + TIMER_O_TAMATCHR) = TIMER_RV_TAMATCHR; - HWREG(ulBase + TIMER_O_TBMATCHR) = TIMER_RV_TBMATCHR; - HWREG(ulBase + TIMER_O_TAPR) = TIMER_RV_TAPR; - HWREG(ulBase + TIMER_O_TBPR) = TIMER_RV_TBPR; - HWREG(ulBase + TIMER_O_TAPMR) = TIMER_RV_TAPMR; - HWREG(ulBase + TIMER_O_TBPMR) = TIMER_RV_TBPMR; - HWREG(ulBase + TIMER_O_TAR) = TIMER_RV_TAR; - HWREG(ulBase + TIMER_O_TBR) = TIMER_RV_TBR; -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/timer.h b/Demo/CORTEX_LM3S811_GCC/hw_include/timer.h deleted file mode 100644 index 660c325f4..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/timer.h +++ /dev/null @@ -1,137 +0,0 @@ -//***************************************************************************** -// -// timer.h - Prototypes for the timer module -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __TIMER_H__ -#define __TIMER_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to TimerConfigure as the ulConfig parameter. -// -//***************************************************************************** -#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer -#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer -#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer -#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers -#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer -#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer -#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter -#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer -#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output -#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer -#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer -#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter -#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer -#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output - -//***************************************************************************** -// -// Values that can be passed to TimerIntEnable, TimerIntDisable, and -// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus. -// -//***************************************************************************** -#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt -#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt -#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt -#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask -#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt -#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt -#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt - -//***************************************************************************** -// -// Values that can be passed to TimerControlEvent as the ulEvent parameter. -// -//***************************************************************************** -#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges -#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges -#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges - -//***************************************************************************** -// -// Values that can be passed to most of the timer APIs as the ulTimer -// parameter. -// -//***************************************************************************** -#define TIMER_A 0x000000ff // Timer A -#define TIMER_B 0x0000ff00 // Timer B -#define TIMER_BOTH 0x0000ffff // Timer Both - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer); -extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer); -extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig); -extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, - tBoolean bInvert); -extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, - tBoolean bEnable); -extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulEvent); -extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer, - tBoolean bStall); -extern void TimerRTCEnable(unsigned long ulBase); -extern void TimerRTCDisable(unsigned long ulBase); -extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerPrescaleGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer); -extern unsigned long TimerValueGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerMatchGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, - void (*pfnHandler)(void)); -extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer); -extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags); -extern void TimerQuiesce(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __TIMER_H__ diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/uart.c b/Demo/CORTEX_LM3S811_GCC/hw_include/uart.c deleted file mode 100644 index cbae1b0ca..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/uart.c +++ /dev/null @@ -1,821 +0,0 @@ -//***************************************************************************** -// -// uart.c - Driver for the UART. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup uart_api -//! @{ -// -//***************************************************************************** - -#include "../hw_ints.h" -#include "../hw_memmap.h" -#include "../hw_types.h" -#include "../hw_uart.h" -#include "debug.h" -#include "interrupt.h" -#include "sysctl.h" -#include "uart.h" - -//***************************************************************************** -// -//! Sets the type of parity. -//! -//! \param ulBase is the base address of the UART port. -//! \param ulParity specifies the type of parity to use. -//! -//! Sets the type of parity to use for transmitting and expect when receiving. -//! The \e ulParity parameter must be one of \b UART_CONFIG_PAR_NONE, -//! \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE, -//! or \b UART_CONFIG_PAR_ZERO. The last two allow direct control of the -//! parity bit; it will always be either be one or zero based on the mode. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_paritymodeset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -UARTParityModeSet(unsigned long ulBase, unsigned long ulParity) -{ - // - // Check the arguments. - // - ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); - ASSERT((ulParity == UART_CONFIG_PAR_NONE) || - (ulParity == UART_CONFIG_PAR_EVEN) || - (ulParity == UART_CONFIG_PAR_ODD) || - (ulParity == UART_CONFIG_PAR_ONE) || - (ulParity == UART_CONFIG_PAR_ZERO)); - - // - // Set the parity mode. - // - HWREG(ulBase + UART_O_LCR_H) = ((HWREG(ulBase + UART_O_LCR_H) & - ~(UART_LCR_H_SPS | UART_LCR_H_EPS | - UART_LCR_H_PEN)) | ulParity); -} -#endif - -//***************************************************************************** -// -//! Gets the type of parity currently being used. -//! -//! \param ulBase is the base address of the UART port. -//! -//! \return The current parity settings, specified as one of -//! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, -//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO. -// -//***************************************************************************** -#if defined(GROUP_paritymodeget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -UARTParityModeGet(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); - - // - // Return the current parity setting. - // - return(HWREG(ulBase + UART_O_LCR_H) & - (UART_LCR_H_SPS | UART_LCR_H_EPS | UART_LCR_H_PEN)); -} -#endif - -//***************************************************************************** -// -//! Sets the configuration of a UART. -//! -//! \param ulBase is the base address of the UART port. -//! \param ulBaud is the desired baud rate. -//! \param ulConfig is the data format for the port (number of data bits, -//! number of stop bits, and parity). -//! -//! This function will configure the UART for operation in the specified data -//! format. The baud rate is provided in the \e ulBaud parameter and the -//! data format in the \e ulConfig parameter. -//! -//! The \e ulConfig parameter is the logical OR of three values: the number of -//! data bits, the number of stop bits, and the parity. \b UART_CONFIG_WLEN_8, -//! \b UART_CONFIG_WLEN_7, \b UART_CONFIG_WLEN_6, and \b UART_CONFIG_WLEN_5 -//! select from eight to five data bits per byte (respectively). -//! \b UART_CONFIG_STOP_ONE and \b UART_CONFIG_STOP_TWO select one or two stop -//! bits (respectively). \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, -//! \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE, and \b UART_CONFIG_PAR_ZERO -//! select the parity mode (no parity bit, even parity bit, odd parity bit, -//! parity bit always one, and parity bit always zero, respectively). -//! -//! The baud rate is dependent upon the system clock rate returned by -//! SysCtlClockGet(); if it does not return the correct system clock rate then -//! the baud rate will be incorrect. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_configset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -UARTConfigSet(unsigned long ulBase, unsigned long ulBaud, - unsigned long ulConfig) -{ - unsigned long ulUARTClk, ulInt, ulFrac; - - // - // Check the arguments. - // - ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); - - // - // Stop the UART. - // - UARTDisable(ulBase); - - // - // Determine the UART clock rate. - // - ulUARTClk = SysCtlClockGet(); - - // - // Compute the fractional baud rate divider. - // - ulInt = ulUARTClk / (16 * ulBaud); - ulFrac = ulUARTClk % (16 * ulBaud); - ulFrac = ((((2 * ulFrac * 4) / ulBaud) + 1) / 2); - - // - // Set the baud rate. - // - HWREG(ulBase + UART_O_IBRD) = ulInt; - HWREG(ulBase + UART_O_FBRD) = ulFrac; - - // - // Set parity, data length, and number of stop bits. - // - HWREG(ulBase + UART_O_LCR_H) = ulConfig; - - // - // Clear the flags register. - // - HWREG(ulBase + UART_O_FR) = 0; - - // - // Start the UART. - // - UARTEnable(ulBase); -} -#endif - -//***************************************************************************** -// -//! Gets the current configuration of a UART. -//! -//! \param ulBase is the base address of the UART port. -//! \param pulBaud is a pointer to storage for the baud rate. -//! \param pulConfig is a pointer to storage for the data format. -//! -//! The baud rate and data format for the UART is determined. The returned -//! baud rate is the actual baud rate; it may not be the exact baud rate -//! requested or an ``official'' baud rate. The data format returned in -//! \e pulConfig is enumerated the same as the \e ulConfig parameter of -//! UARTConfigSet(). -//! -//! The baud rate is dependent upon the system clock rate returned by -//! SysCtlClockGet(); if it does not return the correct system clock rate then -//! the baud rate will be computed incorrectly. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_configget) || defined(BUILD_ALL) || defined(DOXYGEN) -void -UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud, - unsigned long *pulConfig) - -{ - unsigned long ulInt, ulFrac; - - // - // Check the arguments. - // - ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); - - // - // Compute the baud rate. - // - ulInt = HWREG(ulBase + UART_O_IBRD); - ulFrac = HWREG(ulBase + UART_O_FBRD); - *pulBaud = (SysCtlClockGet() * 4) / ((64 * ulInt) + ulFrac); - - // - // Get the parity, data length, and number of stop bits. - // - *pulConfig = (HWREG(ulBase + UART_O_LCR_H) & - (UART_LCR_H_SPS | UART_LCR_H_WLEN | UART_LCR_H_STP2 | - UART_LCR_H_EPS | UART_LCR_H_PEN)); -} -#endif - -//***************************************************************************** -// -//! Enables transmitting and receiving. -//! -//! \param ulBase is the base address of the UART port. -//! -//! Sets the UARTEN, TXE, and RXE bits, and enables the transmit and receive -//! FIFOs. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -UARTEnable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); - - // - // Enable the FIFO. - // - HWREG(ulBase + UART_O_LCR_H) |= UART_LCR_H_FEN; - - // - // Enable RX, TX, and the UART. - // - HWREG(ulBase + UART_O_CTL) |= (UART_CTL_UARTEN | UART_CTL_TXE | - UART_CTL_RXE); -} -#endif - -//***************************************************************************** -// -//! Disables transmitting and receiving. -//! -//! \param ulBase is the base address of the UART port. -//! -//! Clears the UARTEN, TXE, and RXE bits, then waits for the end of -//! transmission of the current character, and flushes the transmit FIFO. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -UARTDisable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); - - // - // Wait for end of TX. - // - while(HWREG(ulBase + UART_O_FR) & UART_FR_BUSY) - { - } - - // - // Disable the FIFO. - // - HWREG(ulBase + UART_O_LCR_H) &= ~(UART_LCR_H_FEN); - - // - // Disable the UART. - // - HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE | - UART_CTL_RXE); -} -#endif - -//***************************************************************************** -// -//! Determines if there are any characters in the receive FIFO. -//! -//! \param ulBase is the base address of the UART port. -//! -//! This function returns a flag indicating whether or not there is data -//! available in the receive FIFO. -//! -//! \return Returns \b true if there is data in the receive FIFO, and \b false -//! if there is no data in the receive FIFO. -// -//***************************************************************************** -#if defined(GROUP_charsavail) || defined(BUILD_ALL) || defined(DOXYGEN) -tBoolean -UARTCharsAvail(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); - - // - // Return the availability of characters. - // - return((HWREG(ulBase + UART_O_FR) & UART_FR_RXFE) ? false : true); -} -#endif - -//***************************************************************************** -// -//! Determines if there is any space in the transmit FIFO. -//! -//! \param ulBase is the base address of the UART port. -//! -//! This function returns a flag indicating whether or not there is space -//! available in the transmit FIFO. -//! -//! \return Returns \b true if there is space available in the transmit FIFO, -//! and \b false if there is no space available in the transmit FIFO. -// -//***************************************************************************** -#if defined(GROUP_spaceavail) || defined(BUILD_ALL) || defined(DOXYGEN) -tBoolean -UARTSpaceAvail(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); - - // - // Return the availability of space. - // - return((HWREG(ulBase + UART_O_FR) & UART_FR_TXFF) ? false : true); -} -#endif - -//***************************************************************************** -// -//! Receives a character from the specified port. -//! -//! \param ulBase is the base address of the UART port. -//! -//! Gets a character from the receive FIFO for the specified port. -//! -//! \return Returns the character read from the specified port, cast as a -//! \e long. A \b -1 will be returned if there are no characters present in -//! the receive FIFO. The UARTCharsAvail() function should be called before -//! attempting to call this function. -// -//***************************************************************************** -#if defined(GROUP_charnonblockingget) || defined(BUILD_ALL) || defined(DOXYGEN) -long -UARTCharNonBlockingGet(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); - - // - // See if there are any characters in the receive FIFO. - // - if(!(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE)) - { - // - // Read and return the next character. - // - return(HWREG(ulBase + UART_O_DR)); - } - else - { - // - // There are no characters, so return a failure. - // - return(-1); - } -} -#endif - -//***************************************************************************** -// -//! Waits for a character from the specified port. -//! -//! \param ulBase is the base address of the UART port. -//! -//! Gets a character from the receive FIFO for the specified port. If there -//! are no characters available, this function will wait until a character is -//! received before returning. -//! -//! \return Returns the character read from the specified port, cast as an -//! \e int. -// -//***************************************************************************** -#if defined(GROUP_charget) || defined(BUILD_ALL) || defined(DOXYGEN) -long -UARTCharGet(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); - - // - // Wait until a char is available. - // - while(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE) - { - } - - // - // Now get the char. - // - return(HWREG(ulBase + UART_O_DR)); -} -#endif - -//***************************************************************************** -// -//! Sends a character to the specified port. -//! -//! \param ulBase is the base address of the UART port. -//! \param ucData is the character to be transmitted. -//! -//! Writes the character \e ucData to the transmit FIFO for the specified port. -//! This function does not block, so if there is no space available, then a -//! \b false is returned, and the application will have to retry the function -//! later. -//! -//! \return Returns \b true if the character was successfully placed in the -//! transmit FIFO, and \b false if there was no space available in the transmit -//! FIFO. -// -//***************************************************************************** -#if defined(GROUP_charnonblockingput) || defined(BUILD_ALL) || defined(DOXYGEN) -tBoolean -UARTCharNonBlockingPut(unsigned long ulBase, unsigned char ucData) -{ - // - // Check the arguments. - // - ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); - - // - // See if there is space in the transmit FIFO. - // - if(!(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF)) - { - // - // Write this character to the transmit FIFO. - // - HWREG(ulBase + UART_O_DR) = ucData; - - // - // Success. - // - return(true); - } - else - { - // - // There is no space in the transmit FIFO, so return a failure. - // - return(false); - } -} -#endif - -//***************************************************************************** -// -//! Waits to send a character from the specified port. -//! -//! \param ulBase is the base address of the UART port. -//! \param ucData is the character to be transmitted. -//! -//! Sends the character \e ucData to the transmit FIFO for the specified port. -//! If there is no space available in the transmit FIFO, this function will -//! wait until there is space available before returning. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_charput) || defined(BUILD_ALL) || defined(DOXYGEN) -void -UARTCharPut(unsigned long ulBase, unsigned char ucData) -{ - // - // Check the arguments. - // - ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); - - // - // Wait until space is available. - // - while(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF) - { - } - - // - // Send the char. - // - HWREG(ulBase + UART_O_DR) = ucData; -} -#endif - -//***************************************************************************** -// -//! Causes a BREAK to be sent. -//! -//! \param ulBase is the base address of the UART port. -//! \param bBreakState controls the output level. -//! -//! Calling this function with \e bBreakState set to \b true will assert a -//! break condition on the UART. Calling this function with \e bBreakState set -//! to \b false will remove the break condition. For proper transmission of a -//! break command, the break must be asserted for at least two complete frames. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_breakctl) || defined(BUILD_ALL) || defined(DOXYGEN) -void -UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState) -{ - // - // Check the arguments. - // - ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); - - // - // Set the break condition as requested. - // - HWREG(ulBase + UART_O_LCR_H) = - (bBreakState ? - (HWREG(ulBase + UART_O_LCR_H) | UART_LCR_H_BRK) : - (HWREG(ulBase + UART_O_LCR_H) & ~(UART_LCR_H_BRK))); -} -#endif - -//***************************************************************************** -// -//! Registers an interrupt handler for a UART interrupt. -//! -//! \param ulBase is the base address of the UART port. -//! \param pfnHandler is a pointer to the function to be called when the -//! UART interrupt occurs. -//! -//! This function does the actual registering of the interrupt handler. This -//! will enable the global interrupt in the interrupt controller; specific UART -//! interrupts must be enabled via UARTIntEnable(). It is the interrupt -//! handler's responsibility to clear the interrupt source. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -UARTIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) -{ - unsigned long ulInt; - - // - // Check the arguments. - // - ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); - - // - // Determine the interrupt number based on the UART port. - // - ulInt = (ulBase == UART0_BASE) ? INT_UART0 : INT_UART1; - - // - // Register the interrupt handler. - // - IntRegister(ulInt, pfnHandler); - - // - // Enable the UART interrupt. - // - IntEnable(ulInt); -} -#endif - -//***************************************************************************** -// -//! Unregisters an interrupt handler for a UART interrupt. -//! -//! \param ulBase is the base address of the UART port. -//! -//! This function does the actual unregistering of the interrupt handler. It -//! will clear the handler to be called when a UART interrupt occurs. This -//! will also mask off the interrupt in the interrupt controller so that the -//! interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -UARTIntUnregister(unsigned long ulBase) -{ - unsigned long ulInt; - - // - // Check the arguments. - // - ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); - - // - // Determine the interrupt number based on the UART port. - // - ulInt = (ulBase == UART0_BASE) ? INT_UART0 : INT_UART1; - - // - // Disable the interrupt. - // - IntDisable(ulInt); - - // - // Unregister the interrupt handler. - // - IntUnregister(ulInt); -} -#endif - -//***************************************************************************** -// -//! Enables individual UART interrupt sources. -//! -//! \param ulBase is the base address of the UART port. -//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. -//! -//! Enables the indicated UART interrupt sources. Only the sources that are -//! enabled can be reflected to the processor interrupt; disabled sources have -//! no effect on the processor. -//! -//! The parameter \e ulIntFlags is the logical OR of any of the following: -//! -//! - UART_INT_OE - Overrun Error interrupt -//! - UART_INT_BE - Break Error interrupt -//! - UART_INT_PE - Parity Error interrupt -//! - UART_INT_FE - Framing Error interrupt -//! - UART_INT_RT - Receive Timeout interrupt -//! - UART_INT_TX - Transmit interrupt -//! - UART_INT_RX - Receive interrupt -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags) -{ - // - // Check the arguments. - // - ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); - - // - // Enable the specified interrupts. - // - HWREG(ulBase + UART_O_IM) |= ulIntFlags; -} -#endif - -//***************************************************************************** -// -//! Disables individual UART interrupt sources. -//! -//! \param ulBase is the base address of the UART port. -//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. -//! -//! Disables the indicated UART interrupt sources. Only the sources that are -//! enabled can be reflected to the processor interrupt; disabled sources have -//! no effect on the processor. -//! -//! The parameter \e ulIntFlags has the same definition as the same parameter -//! to UARTIntEnable(). -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags) -{ - // - // Check the arguments. - // - ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); - - // - // Disable the specified interrupts. - // - HWREG(ulBase + UART_O_IM) &= ~(ulIntFlags); -} -#endif - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \param ulBase is the base address of the UART port. -//! \param bMasked is false if the raw interrupt status is required and true -//! if the masked interrupt status is required. -//! -//! This returns the interrupt status for the specified UART. Either the raw -//! interrupt status or the status of interrupts that are allowed to reflect to -//! the processor can be returned. -//! -//! \return The current interrupt status, enumerated as a bit field of -//! values described in UARTIntEnable(). -// -//***************************************************************************** -#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -UARTIntStatus(unsigned long ulBase, tBoolean bMasked) -{ - // - // Check the arguments. - // - ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(ulBase + UART_O_MIS)); - } - else - { - return(HWREG(ulBase + UART_O_RIS)); - } -} -#endif - -//***************************************************************************** -// -//! Clears UART interrupt sources. -//! -//! \param ulBase is the base address of the UART port. -//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. -//! -//! The specified UART interrupt sources are cleared, so that they no longer -//! assert. This must be done in the interrupt handler to keep it from being -//! called again immediately upon exit. -//! -//! The parameter \e ulIntFlags has the same definition as the same parameter -//! to UARTIntEnable(). -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) -void -UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags) -{ - // - // Check the arguments. - // - ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); - - // - // Clear the requested interrupt sources. - // - HWREG(ulBase + UART_O_ICR) = ulIntFlags; -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/uart.h b/Demo/CORTEX_LM3S811_GCC/hw_include/uart.h deleted file mode 100644 index b82f2eec5..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/uart.h +++ /dev/null @@ -1,102 +0,0 @@ -//***************************************************************************** -// -// uart.h - Defines and Macros for the UART. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __UART_H__ -#define __UART_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear -// as the ulIntFlags parameter, and returned from UARTIntStatus. -// -//***************************************************************************** -#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask -#define UART_INT_BE 0x200 // Break Error Interrupt Mask -#define UART_INT_PE 0x100 // Parity Error Interrupt Mask -#define UART_INT_FE 0x080 // Framing Error Interrupt Mask -#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask -#define UART_INT_TX 0x020 // Transmit Interrupt Mask -#define UART_INT_RX 0x010 // Receive Interrupt Mask - -//***************************************************************************** -// -// Values that can be passed to UARTConfigSet as the ulConfig parameter and -// returned by UARTConfigGet in the pulConfig parameter. Additionally, the -// UART_CONFIG_PAR_* subset can be passed to UARTParityModeSet as the ulParity -// parameter, and are returned by UARTParityModeGet. -// -//***************************************************************************** -#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data -#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data -#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data -#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data -#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit -#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits -#define UART_CONFIG_PAR_NONE 0x00000000 // No parity -#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity -#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity -#define UART_CONFIG_PAR_ONE 0x00000086 // Parity bit is one -#define UART_CONFIG_PAR_ZERO 0x00000082 // Parity bit is zero - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity); -extern unsigned long UARTParityModeGet(unsigned long ulBase); -extern void UARTConfigSet(unsigned long ulBase, unsigned long ulBaud, - unsigned long ulConfig); -extern void UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud, - unsigned long *pulConfig); -extern void UARTEnable(unsigned long ulBase); -extern void UARTDisable(unsigned long ulBase); -extern tBoolean UARTCharsAvail(unsigned long ulBase); -extern tBoolean UARTSpaceAvail(unsigned long ulBase); -extern long UARTCharNonBlockingGet(unsigned long ulBase); -extern long UARTCharGet(unsigned long ulBase); -extern tBoolean UARTCharNonBlockingPut(unsigned long ulBase, - unsigned char ucData); -extern void UARTCharPut(unsigned long ulBase, unsigned char ucData); -extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState); -extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); -extern void UARTIntUnregister(unsigned long ulBase); -extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags); - -#ifdef __cplusplus -} -#endif - -#endif // __UART_H__ diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/watchdog.c b/Demo/CORTEX_LM3S811_GCC/hw_include/watchdog.c deleted file mode 100644 index 53332d051..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/watchdog.c +++ /dev/null @@ -1,592 +0,0 @@ -//***************************************************************************** -// -// watchdog.c - Driver for the Watchdog Timer Module. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup watchdog_api -//! @{ -// -//***************************************************************************** - -#include "../hw_ints.h" -#include "../hw_memmap.h" -#include "../hw_types.h" -#include "../hw_watchdog.h" -#include "debug.h" -#include "interrupt.h" -#include "watchdog.h" - -//***************************************************************************** -// -//! Determines if the watchdog timer is enabled. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! This will check to see if the watchdog timer is enabled. -//! -//! \return Returns \b true if the watchdog timer is enabled, and \b false -//! if it is not. -// -//***************************************************************************** -#if defined(GROUP_running) || defined(BUILD_ALL) || defined(DOXYGEN) -tBoolean -WatchdogRunning(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == WATCHDOG_BASE); - - // - // See if the watchdog timer module is enabled, and return. - // - return(HWREG(ulBase + WDT_O_CTL) & WDT_CTL_INTEN); -} -#endif - -//***************************************************************************** -// -//! Enables the watchdog timer. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! This will enable the watchdog timer counter and interrupt. -//! -//! \note This function will have no effect if the watchdog timer has -//! been locked. -//! -//! \sa WatchdogLock(), WatchdogUnlock() -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -WatchdogEnable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == WATCHDOG_BASE); - - // - // Enable the watchdog timer module. - // - HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_INTEN; -} -#endif - -//***************************************************************************** -// -//! Enables the watchdog timer reset. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! Enables the capability of the watchdog timer to issue a reset to the -//! processor upon a second timeout condition. -//! -//! \note This function will have no effect if the watchdog timer has -//! been locked. -//! -//! \sa WatchdogLock(), WatchdogUnlock() -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_resetenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -WatchdogResetEnable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == WATCHDOG_BASE); - - // - // Enable the watchdog reset. - // - HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_RESEN; -} -#endif - -//***************************************************************************** -// -//! Disables the watchdog timer reset. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! Disables the capability of the watchdog timer to issue a reset to the -//! processor upon a second timeout condition. -//! -//! \note This function will have no effect if the watchdog timer has -//! been locked. -//! -//! \sa WatchdogLock(), WatchdogUnlock() -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_resetdisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -WatchdogResetDisable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == WATCHDOG_BASE); - - // - // Disable the watchdog reset. - // - HWREG(ulBase + WDT_O_CTL) &= ~(WDT_CTL_RESEN); -} -#endif - -//***************************************************************************** -// -//! Enables the watchdog timer lock mechanism. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! Locks out write access to the watchdog timer configuration registers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_lock) || defined(BUILD_ALL) || defined(DOXYGEN) -void -WatchdogLock(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == WATCHDOG_BASE); - - // - // Lock out watchdog register writes. Writing anything to the WDT_O_LOCK - // register causes the lock to go into effect. - // - HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_LOCKED; -} -#endif - -//***************************************************************************** -// -//! Disables the watchdog timer lock mechanism. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! Enables write access to the watchdog timer configuration registers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_unlock) || defined(BUILD_ALL) || defined(DOXYGEN) -void -WatchdogUnlock(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == WATCHDOG_BASE); - - // - // Unlock watchdog register writes. - // - HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_UNLOCK; -} -#endif - -//***************************************************************************** -// -//! Gets the state of the watchdog timer lock mechanism. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! Returns the lock state of the watchdog timer registers. -//! -//! \return Returns \b true if the watchdog timer registers are locked, and -//! \b false if they are not locked. -// -//***************************************************************************** -#if defined(GROUP_lockstate) || defined(BUILD_ALL) || defined(DOXYGEN) -tBoolean -WatchdogLockState(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == WATCHDOG_BASE); - - // - // Get the lock state. - // - return((HWREG(ulBase + WDT_O_LOCK) == WDT_LOCK_LOCKED) ? true : false); -} -#endif - -//***************************************************************************** -// -//! Sets the watchdog timer reload value. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! \param ulLoadVal is the load value for the watchdog timer. -//! -//! This function sets the value to load into the watchdog timer when the count -//! reaches zero for the first time; if the watchdog timer is running when this -//! function is called, then the value will be immediately loaded into the -//! watchdog timer counter. If the parameter \e ulLoadVal is 0, then an -//! interrupt is immediately generated. -//! -//! \note This function will have no effect if the watchdog timer has -//! been locked. -//! -//! \sa WatchdogLock(), WatchdogUnlock(), WatchdogReloadGet() -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_reloadset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal) -{ - // - // Check the arguments. - // - ASSERT(ulBase == WATCHDOG_BASE); - - // - // Set the load register. - // - HWREG(ulBase + WDT_O_LOAD) = ulLoadVal; -} -#endif - -//***************************************************************************** -// -//! Gets the watchdog timer reload value. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! This function gets the value that is loaded into the watchdog timer when -//! the count reaches zero for the first time. -//! -//! \sa WatchdogReloadSet() -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_reloadget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -WatchdogReloadGet(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == WATCHDOG_BASE); - - // - // Get the load register. - // - return(HWREG(ulBase + WDT_O_LOAD)); -} -#endif - -//***************************************************************************** -// -//! Gets the current watchdog timer value. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! This function reads the current value of the watchdog timer. -//! -//! \return Returns the current value of the watchdog timer. -// -//***************************************************************************** -#if defined(GROUP_valueget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -WatchdogValueGet(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == WATCHDOG_BASE); - - // - // Get the current watchdog timer register value. - // - return(HWREG(ulBase + WDT_O_VALUE)); -} -#endif - -//***************************************************************************** -// -//! Registers an interrupt handler for watchdog timer interrupt. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! \param pfnHandler is a pointer to the function to be called when the -//! watchdog timer interrupt occurs. -//! -//! This function does the actual registering of the interrupt handler. This -//! will enable the global interrupt in the interrupt controller; the watchdog -//! timer interrupt must be enabled via WatchdogEnable(). It is the interrupt -//! handler's responsibility to clear the interrupt source via -//! WatchdogIntClear(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -WatchdogIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT(ulBase == WATCHDOG_BASE); - - // - // Register the interrupt handler. - // - IntRegister(INT_WATCHDOG, pfnHandler); - - // - // Enable the watchdog timer interrupt. - // - IntEnable(INT_WATCHDOG); -} -#endif - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the watchdog timer interrupt. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! This function does the actual unregistering of the interrupt handler. This -//! function will clear the handler to be called when a watchdog timer -//! interrupt occurs. This will also mask off the interrupt in the interrupt -//! controller so that the interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -WatchdogIntUnregister(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == WATCHDOG_BASE); - - // - // Disable the interrupt. - // - IntDisable(INT_WATCHDOG); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_WATCHDOG); -} -#endif - -//***************************************************************************** -// -//! Enables the watchdog timer interrupt. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! Enables the watchdog timer interrupt. -//! -//! \note This function will have no effect if the watchdog timer has -//! been locked. -//! -//! \sa WatchdogLock(), WatchdogUnlock(), WatchdogEnable() -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -WatchdogIntEnable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == WATCHDOG_BASE); - - // - // Enable the watchdog interrupt. - // - HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_INTEN; -} -#endif - -//***************************************************************************** -// -//! Gets the current watchdog timer interrupt status. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! \param bMasked is \b false if the raw interrupt status is required and -//! \b true if the masked interrupt status is required. -//! -//! This returns the interrupt status for the watchdog timer module. Either -//! the raw interrupt status or the status of interrupt that is allowed to -//! reflect to the processor can be returned. -//! -//! \return The current interrupt status, where a 1 indicates that the watchdog -//! interrupt is active, and a 0 indicates that it is not active. -// -//***************************************************************************** -#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked) -{ - // - // Check the arguments. - // - ASSERT(ulBase == WATCHDOG_BASE); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(ulBase + WDT_O_MIS)); - } - else - { - return(HWREG(ulBase + WDT_O_RIS)); - } -} -#endif - -//***************************************************************************** -// -//! Clears the watchdog timer interrupt. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! The watchdog timer interrupt source is cleared, so that it no longer -//! asserts. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) -void -WatchdogIntClear(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == WATCHDOG_BASE); - - // - // Clear the interrupt source. - // - HWREG(ulBase + WDT_O_ICR) = WDT_INT_TIMEOUT; -} -#endif - -//***************************************************************************** -// -//! Enables stalling of the watchdog timer during debug events. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! This function allows the watchdog timer to stop counting when the processor -//! is stopped by the debugger. By doing so, the watchdog is prevented from -//! expiring (typically almost immediately from a human time perspective) and -//! resetting the system (if reset is enabled). The watchdog will instead -//! expired after the appropriate number of processor cycles have been executed -//! while debugging (or at the appropriate time after the processor has been -//! restarted). -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_stallenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -WatchdogStallEnable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == WATCHDOG_BASE); - - // - // Enable timer stalling. - // - HWREG(ulBase + WDT_O_TEST) |= WDT_TEST_STALL; -} -#endif - -//***************************************************************************** -// -//! Disables stalling of the watchdog timer during debug events. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! This function disables the debug mode stall of the watchdog timer. By -//! doing so, the watchdog timer continues to count regardless of the processor -//! debug state. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_stalldisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -WatchdogStallDisable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == WATCHDOG_BASE); - - // - // Disable timer stalling. - // - HWREG(ulBase + WDT_O_TEST) &= ~(WDT_TEST_STALL); -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/Demo/CORTEX_LM3S811_GCC/hw_include/watchdog.h b/Demo/CORTEX_LM3S811_GCC/hw_include/watchdog.h deleted file mode 100644 index 9378504a0..000000000 --- a/Demo/CORTEX_LM3S811_GCC/hw_include/watchdog.h +++ /dev/null @@ -1,63 +0,0 @@ -//***************************************************************************** -// -// watchdog.h - Prototypes for the Watchdog Timer API -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __WATCHDOG_H__ -#define __WATCHDOG_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern tBoolean WatchdogRunning(unsigned long ulBase); -extern void WatchdogEnable(unsigned long ulBase); -extern void WatchdogResetEnable(unsigned long ulBase); -extern void WatchdogResetDisable(unsigned long ulBase); -extern void WatchdogLock(unsigned long ulBase); -extern void WatchdogUnlock(unsigned long ulBase); -extern tBoolean WatchdogLockState(unsigned long ulBase); -extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal); -extern unsigned long WatchdogReloadGet(unsigned long ulBase); -extern unsigned long WatchdogValueGet(unsigned long ulBase); -extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); -extern void WatchdogIntUnregister(unsigned long ulBase); -extern void WatchdogIntEnable(unsigned long ulBase); -extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void WatchdogIntClear(unsigned long ulBase); -extern void WatchdogStallDisable(unsigned long ulBase); -extern void WatchdogStallDisable(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __WATCHDOG_H__ diff --git a/Demo/CORTEX_LM3S811_GCC/init/startup.c b/Demo/CORTEX_LM3S811_GCC/init/startup.c deleted file mode 100644 index 407a49792..000000000 --- a/Demo/CORTEX_LM3S811_GCC/init/startup.c +++ /dev/null @@ -1,221 +0,0 @@ -//***************************************************************************** -// -// startup.c - Boot code for Stellaris. -// -// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 1049 of the Stellaris Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -// Forward declaration of the default fault handlers. -// -//***************************************************************************** -void ResetISR(void); -static void NmiSR(void); -static void FaultISR(void); -static void IntDefaultHandler(void); -extern void xPortPendSVHandler(void); -extern void xPortSysTickHandler(void); -extern void vUART_ISR( void ); -extern void vGPIO_ISR( void ); - -//***************************************************************************** -// -// The entry point for the application. -// -//***************************************************************************** -extern int main(void); - -//***************************************************************************** -// -// Reserve space for the system stack. -// -//***************************************************************************** -#ifndef STACK_SIZE -#define STACK_SIZE 64 -#endif -static unsigned long pulStack[STACK_SIZE]; - -//***************************************************************************** -// -// The minimal vector table for a Cortex M3. Note that the proper constructs -// must be placed on this to ensure that it ends up at physical address -// 0x0000.0000. -// -//***************************************************************************** -__attribute__ ((section(".isr_vector"))) -void (* const g_pfnVectors[])(void) = -{ - (void (*)(void))((unsigned long)pulStack + sizeof(pulStack)), - // The initial stack pointer - ResetISR, // The reset handler - NmiSR, // The NMI handler - FaultISR, // The hard fault handler - IntDefaultHandler, // The MPU fault handler - IntDefaultHandler, // The bus fault handler - IntDefaultHandler, // The usage fault handler - 0, // Reserved - 0, // Reserved - 0, // Reserved - 0, // Reserved - IntDefaultHandler, // SVCall handler - IntDefaultHandler, // Debug monitor handler - 0, // Reserved - xPortPendSVHandler, // The PendSV handler - xPortSysTickHandler, // The SysTick handler - IntDefaultHandler, // GPIO Port A - IntDefaultHandler, // GPIO Port B - vGPIO_ISR, // GPIO Port C - IntDefaultHandler, // GPIO Port D - IntDefaultHandler, // GPIO Port E - vUART_ISR, // UART0 Rx and Tx - IntDefaultHandler, // UART1 Rx and Tx - IntDefaultHandler, // SSI Rx and Tx - IntDefaultHandler, // I2C Master and Slave - IntDefaultHandler, // PWM Fault - IntDefaultHandler, // PWM Generator 0 - IntDefaultHandler, // PWM Generator 1 - IntDefaultHandler, // PWM Generator 2 - IntDefaultHandler, // Quadrature Encoder - IntDefaultHandler, // ADC Sequence 0 - IntDefaultHandler, // ADC Sequence 1 - IntDefaultHandler, // ADC Sequence 2 - IntDefaultHandler, // ADC Sequence 3 - IntDefaultHandler, // Watchdog timer - IntDefaultHandler, // Timer 0 subtimer A - IntDefaultHandler, // Timer 0 subtimer B - IntDefaultHandler, // Timer 1 subtimer A - IntDefaultHandler, // Timer 1 subtimer B - IntDefaultHandler, // Timer 2 subtimer A - IntDefaultHandler, // Timer 2 subtimer B - IntDefaultHandler, // Analog Comparator 0 - IntDefaultHandler, // Analog Comparator 1 - IntDefaultHandler, // Analog Comparator 2 - IntDefaultHandler, // System Control (PLL, OSC, BO) - IntDefaultHandler // FLASH Control -}; - -//***************************************************************************** -// -// The following are constructs created by the linker, indicating where the -// the "data" and "bss" segments reside in memory. The initializers for the -// for the "data" segment resides immediately following the "text" segment. -// -//***************************************************************************** -extern unsigned long _etext; -extern unsigned long _data; -extern unsigned long _edata; -extern unsigned long _bss; -extern unsigned long _ebss; - -//***************************************************************************** -// -// This is the code that gets called when the processor first starts execution -// following a reset event. Only the absolutely necessary set is performed, -// after which the application supplied main() routine is called. Any fancy -// actions (such as making decisions based on the reset cause register, and -// resetting the bits in that register) are left solely in the hands of the -// application. -// -//***************************************************************************** -void -ResetISR(void) -{ - unsigned long *pulSrc, *pulDest; - - // - // Copy the data segment initializers from flash to SRAM. - // - pulSrc = &_etext; - for(pulDest = &_data; pulDest < &_edata; ) - { - *pulDest++ = *pulSrc++; - } - - // - // Zero fill the bss segment. - // - for(pulDest = &_bss; pulDest < &_ebss; ) - { - *pulDest++ = 0; - } - - // - // Call the application's entry point. - // - main(); -} - -//***************************************************************************** -// -// This is the code that gets called when the processor receives a NMI. This -// simply enters an infinite loop, preserving the system state for examination -// by a debugger. -// -//***************************************************************************** -static void -NmiSR(void) -{ - // - // Enter an infinite loop. - // - while(1) - { - } -} - -//***************************************************************************** -// -// This is the code that gets called when the processor receives a fault -// interrupt. This simply enters an infinite loop, preserving the system state -// for examination by a debugger. -// -//***************************************************************************** -static void -FaultISR(void) -{ - // - // Enter an infinite loop. - // - while(1) - { - } -} - -//***************************************************************************** -// -// This is the code that gets called when the processor receives an unexpected -// interrupt. This simply enters an infinite loop, preserving the system state -// for examination by a debugger. -// -//***************************************************************************** -static void -IntDefaultHandler(void) -{ - // - // Go into an infinite loop. - // - while(1) - { - } -} diff --git a/Demo/CORTEX_LM3S811_GCC/main.c b/Demo/CORTEX_LM3S811_GCC/main.c deleted file mode 100644 index 29a167896..000000000 --- a/Demo/CORTEX_LM3S811_GCC/main.c +++ /dev/null @@ -1,362 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/* - * This project contains an application demonstrating the use of the - * FreeRTOS.org mini real time scheduler on the Luminary Micro LM3S811 Eval - * board. See http://www.FreeRTOS.org for more information. - * - * main() simply sets up the hardware, creates all the demo application tasks, - * then starts the scheduler. http://www.freertos.org/a00102.html provides - * more information on the standard demo tasks. - * - * In addition to a subset of the standard demo application tasks, main.c also - * defines the following tasks: - * - * + A 'Print' task. The print task is the only task permitted to access the - * LCD - thus ensuring mutual exclusion and consistent access to the resource. - * Other tasks do not access the LCD directly, but instead send the text they - * wish to display to the print task. The print task spends most of its time - * blocked - only waking when a message is queued for display. - * - * + A 'Button handler' task. The eval board contains a user push button that - * is configured to generate interrupts. The interrupt handler uses a - * semaphore to wake the button handler task - demonstrating how the priority - * mechanism can be used to defer interrupt processing to the task level. The - * button handler task sends a message both to the LCD (via the print task) and - * the UART where it can be viewed using a dumb terminal (via the UART to USB - * converter on the eval board). NOTES: The dumb terminal must be closed in - * order to reflash the microcontroller. A very basic interrupt driven UART - * driver is used that does not use the FIFO. 19200 baud is used. - * - * + A 'check' task. The check task only executes every five seconds but has a - * high priority so is guaranteed to get processor time. Its function is to - * check that all the other tasks are still operational and that no errors have - * been detected at any time. If no errors have every been detected 'PASS' is - * written to the display (via the print task) - if an error has ever been - * detected the message is changed to 'FAIL'. The position of the message is - * changed for each write. - */ - - - -/* Environment includes. */ -#include "DriverLib.h" - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" -#include "semphr.h" - -/* Demo app includes. */ -#include "integer.h" -#include "PollQ.h" -#include "semtest.h" -#include "BlockQ.h" - -/* Delay between cycles of the 'check' task. */ -#define mainCHECK_DELAY ( ( portTickType ) 5000 / portTICK_RATE_MS ) - -/* UART configuration - note this does not use the FIFO so is not very -efficient. */ -#define mainBAUD_RATE ( 19200 ) -#define mainFIFO_SET ( 0x10 ) - -/* Demo task priorities. */ -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) - -/* Demo board specifics. */ -#define mainPUSH_BUTTON GPIO_PIN_4 - -/* Misc. */ -#define mainQUEUE_SIZE ( 3 ) -#define mainDEBOUNCE_DELAY ( ( portTickType ) 150 / portTICK_RATE_MS ) -#define mainNO_DELAY ( ( portTickType ) 0 ) -/* - * Configure the processor and peripherals for this demo. - */ -static void prvSetupHardware( void ); - -/* - * The 'check' task, as described at the top of this file. - */ -static void vCheckTask( void *pvParameters ); - -/* - * The task that is woken by the ISR that processes GPIO interrupts originating - * from the push button. - */ -static void vButtonHandlerTask( void *pvParameters ); - -/* - * The task that controls access to the LCD. - */ -static void vPrintTask( void *pvParameter ); - -/* String that is transmitted on the UART. */ -static portCHAR *cMessage = "Task woken by button interrupt! --- "; -static volatile portCHAR *pcNextChar; - -/* The semaphore used to wake the button handler task from within the GPIO -interrupt handler. */ -xSemaphoreHandle xButtonSemaphore; - -/* The queue used to send strings to the print task for display on the LCD. */ -xQueueHandle xPrintQueue; - -/*-----------------------------------------------------------*/ - -int main( void ) -{ - /* Configure the clocks, UART and GPIO. */ - prvSetupHardware(); - - /* Create the semaphore used to wake the button handler task from the GPIO - ISR. */ - vSemaphoreCreateBinary( xButtonSemaphore ); - xSemaphoreTake( xButtonSemaphore, 0 ); - - /* Create the queue used to pass message to vPrintTask. */ - xPrintQueue = xQueueCreate( mainQUEUE_SIZE, sizeof( portCHAR * ) ); - - /* Start the standard demo tasks. */ - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - - /* Start the tasks defined within the file. */ - xTaskCreate( vCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - xTaskCreate( vButtonHandlerTask, "Status", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY + 1, NULL ); - xTaskCreate( vPrintTask, "Print", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL ); - - /* Start the scheduler. */ - vTaskStartScheduler(); - - /* Will only get here if there was insufficient heap to start the - scheduler. */ - - return 0; -} -/*-----------------------------------------------------------*/ - -static void vCheckTask( void *pvParameters ) -{ -portBASE_TYPE xErrorOccurred = pdFALSE; -portTickType xLastExecutionTime; -const portCHAR *pcPassMessage = "PASS"; -const portCHAR *pcFailMessage = "FAIL"; - - /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() - works correctly. */ - xLastExecutionTime = xTaskGetTickCount(); - - for( ;; ) - { - /* Perform this check every mainCHECK_DELAY milliseconds. */ - vTaskDelayUntil( &xLastExecutionTime, mainCHECK_DELAY ); - - /* Has an error been found in any task? */ - - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - xErrorOccurred = pdTRUE; - } - - if( xArePollingQueuesStillRunning() != pdTRUE ) - { - xErrorOccurred = pdTRUE; - } - - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - xErrorOccurred = pdTRUE; - } - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - xErrorOccurred = pdTRUE; - } - - /* Send either a pass or fail message. If an error is found it is - never cleared again. We do not write directly to the LCD, but instead - queue a message for display by the print task. */ - if( xErrorOccurred == pdTRUE ) - { - xQueueSend( xPrintQueue, &pcFailMessage, portMAX_DELAY ); - } - else - { - xQueueSend( xPrintQueue, &pcPassMessage, portMAX_DELAY ); - } - } -} -/*-----------------------------------------------------------*/ - -static void prvSetupHardware( void ) -{ - /* Setup the PLL. */ - SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); - - /* Setup the push button. */ - SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC); - GPIODirModeSet(GPIO_PORTC_BASE, mainPUSH_BUTTON, GPIO_DIR_MODE_IN); - GPIOIntTypeSet( GPIO_PORTC_BASE, mainPUSH_BUTTON,GPIO_FALLING_EDGE ); - GPIOPinIntEnable( GPIO_PORTC_BASE, mainPUSH_BUTTON ); - IntEnable( INT_GPIOC ); - - - - /* Enable the UART. */ - SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); - SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); - - /* Set GPIO A0 and A1 as peripheral function. They are used to output the - UART signals. */ - GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); - - /* Configure the UART for 8-N-1 operation. */ - UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); - - /* We don't want to use the fifo. This is for test purposes to generate - as many interrupts as possible. */ - HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; - - /* Enable Tx interrupts. */ - HWREG( UART0_BASE + UART_O_IM ) |= UART_INT_TX; - IntEnable( INT_UART0 ); - - - /* Initialise the LCD> */ - OSRAMInit( false ); - OSRAMStringDraw("www.FreeRTOS.org", 0, 0); - OSRAMStringDraw("LM3S811 demo", 16, 1); -} -/*-----------------------------------------------------------*/ - -static void vButtonHandlerTask( void *pvParameters ) -{ -const portCHAR *pcInterruptMessage = "Int"; - - for( ;; ) - { - /* Wait for a GPIO interrupt to wake this task. */ - while( xSemaphoreTake( xButtonSemaphore, portMAX_DELAY ) != pdPASS ); - - /* Start the Tx of the message on the UART. */ - UARTIntDisable( UART0_BASE, UART_INT_TX ); - { - pcNextChar = cMessage; - - /* Send the first character. */ - if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) - { - HWREG( UART0_BASE + UART_O_DR ) = *pcNextChar; - } - - pcNextChar++; - } - UARTIntEnable(UART0_BASE, UART_INT_TX); - - /* Queue a message for the print task to display on the LCD. */ - xQueueSend( xPrintQueue, &pcInterruptMessage, portMAX_DELAY ); - - /* Make sure we don't process bounces. */ - vTaskDelay( mainDEBOUNCE_DELAY ); - xSemaphoreTake( xButtonSemaphore, mainNO_DELAY ); - } -} - -/*-----------------------------------------------------------*/ - -void vUART_ISR(void) -{ -unsigned portLONG ulStatus; - - /* What caused the interrupt. */ - ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); - - /* Clear the interrupt. */ - UARTIntClear( UART0_BASE, ulStatus ); - - /* Was a Tx interrupt pending? */ - if( ulStatus & UART_INT_TX ) - { - /* Send the next character in the string. We are not using the FIFO. */ - if( *pcNextChar != 0 ) - { - if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) - { - HWREG( UART0_BASE + UART_O_DR ) = *pcNextChar; - } - pcNextChar++; - } - } -} -/*-----------------------------------------------------------*/ - -void vGPIO_ISR( void ) -{ - /* Clear the interrupt. */ - GPIOPinIntClear(GPIO_PORTC_BASE, mainPUSH_BUTTON); - - /* Wake the button handler task. */ - if( xSemaphoreGiveFromISR( xButtonSemaphore, pdFALSE ) ) - { - portEND_SWITCHING_ISR( pdTRUE ); - } -} -/*-----------------------------------------------------------*/ - -static void vPrintTask( void *pvParameters ) -{ -portCHAR *pcMessage; -unsigned portBASE_TYPE uxLine = 0, uxRow = 0; - - for( ;; ) - { - /* Wait for a message to arrive. */ - xQueueReceive( xPrintQueue, &pcMessage, portMAX_DELAY ); - - /* Write the message to the LCD. */ - uxRow++; - uxLine++; - OSRAMClear(); - OSRAMStringDraw( pcMessage, uxLine & 0x3f, uxRow & 0x01); - } -} - diff --git a/Demo/CORTEX_LM3S811_GCC/makedefs b/Demo/CORTEX_LM3S811_GCC/makedefs deleted file mode 100644 index efd7530d4..000000000 --- a/Demo/CORTEX_LM3S811_GCC/makedefs +++ /dev/null @@ -1,208 +0,0 @@ -#****************************************************************************** -# -# makedefs - Definitions common to all makefiles. -# -# Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -# -# Software License Agreement -# -# Luminary Micro, Inc. (LMI) is supplying this software for use solely and -# exclusively on LMI's Stellaris Family of microcontroller products. -# -# The software is owned by LMI and/or its suppliers, and is protected under -# applicable copyright laws. All rights are reserved. Any use in violation -# of the foregoing restrictions may subject the user to criminal sanctions -# under applicable laws, as well as to civil liability for the breach of the -# terms and conditions of this license. -# -# THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -# OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -# LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -# CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -# -#****************************************************************************** - -#****************************************************************************** -# -# Get the operating system name. If this is Cygwin, the .d files will be -# munged to convert c: into /cygdrive/c so that "make" will be happy with the -# auto-generated dependencies. -# -#****************************************************************************** -os:=${shell uname -s} - -#****************************************************************************** -# -# The compiler to be used. -# -#****************************************************************************** -ifndef COMPILER -COMPILER=gcc -endif - -#****************************************************************************** -# -# The debugger to be used. -# -#****************************************************************************** -ifndef DEBUGGER -DEBUGGER=gdb -endif - -#****************************************************************************** -# -# Definitions for using GCC. -# -#****************************************************************************** -ifeq (${COMPILER}, gcc) - -# -# The command for calling the compiler. -# -CC=arm-stellaris-eabi-gcc - -# -# The flags passed to the assembler. -# -AFLAGS=-mthumb \ - -mcpu=cortex-m3 \ - -MD - -# -# The flags passed to the compiler. -# -CFLAGS=-mthumb \ - -mcpu=cortex-m3 \ - -O2 \ - -MD - -# -# The command for calling the library archiver. -# -AR=arm-stellaris-eabi-ar - -# -# The command for calling the linker. -# -LD=arm-stellaris-eabi-ld - -# -# The flags passed to the linker. -# -LDFLAGS= -Map gcc/out.map - -# -# Get the location of libgcc.a from the GCC front-end. -# -LIBGCC=${shell ${CC} -mthumb -march=armv6t2 -print-libgcc-file-name} - -# -# Get the location of libc.a from the GCC front-end. -# -LIBC=${shell ${CC} -mthumb -march=armv6t2 -print-file-name=libc.a} - -# -# The command for extracting images from the linked executables. -# -OBJCOPY=arm-stellaris-eabi-objcopy - -endif - -#****************************************************************************** -# -# Tell the compiler to include debugging information if the DEBUG environment -# variable is set. -# -#****************************************************************************** -ifdef DEBUG -CFLAGS += -g -endif - -#****************************************************************************** -# -# The rule for building the object file from each C source file. -# -#****************************************************************************** -${COMPILER}/%.o: %.c - @if [ 'x${VERBOSE}' = x ]; \ - then \ - echo " CC ${<}"; \ - else \ - echo ${CC} ${CFLAGS} -D${COMPILER} -o ${@} -c ${<}; \ - fi - @${CC} ${CFLAGS} -D${COMPILER} -o ${@} -c ${<} -ifeq (${COMPILER}, rvds) - @mv -f ${notdir ${@:.o=.d}} ${COMPILER} -endif -ifneq ($(findstring CYGWIN, ${os}), ) - @perl -i.bak -p -e 's/[Cc]:/\/cygdrive\/c/g' ${@:.o=.d} -endif - -#****************************************************************************** -# -# The rule for building the object file from each assembly source file. -# -#****************************************************************************** -${COMPILER}/%.o: %.S - @if [ 'x${VERBOSE}' = x ]; \ - then \ - echo " CC ${<}"; \ - else \ - echo ${CC} ${AFLAGS} -D${COMPILER} -o ${@} -c ${<}; \ - fi -ifeq (${COMPILER}, rvds) - @${CC} ${AFLAGS} -D${COMPILER} -E ${<} > ${@:.o=_.S} - @${CC} ${AFLAGS} -o ${@} -c ${@:.o=_.S} - @rm ${@:.o=_.S} - @${CC} ${AFLAGS} -D${COMPILER} --md -E ${<} - @sed 's,,${@},g' ${notdir ${<:.S=.d}} > ${@:.o=.d} - @rm ${notdir ${<:.S=.d}} -endif -ifeq (${COMPILER}, gcc) - @${CC} ${AFLAGS} -D${COMPILER} -o ${@} -c ${<} -endif -ifneq ($(findstring CYGWIN, ${os}), ) - @perl -i.bak -p -e 's/[Cc]:/\/cygdrive\/c/g' ${@:.o=.d} -endif - -#****************************************************************************** -# -# The rule for creating an object library. -# -#****************************************************************************** -${COMPILER}/%.a: - @if [ 'x${VERBOSE}' = x ]; \ - then \ - echo " AR ${@}"; \ - else \ - echo ${AR} -cr ${@} ${^}; \ - fi - @${AR} -cr ${@} ${^} - -#****************************************************************************** -# -# The rule for linking the application. -# -#****************************************************************************** -${COMPILER}/%.axf: - @if [ 'x${VERBOSE}' = x ]; \ - then \ - echo " LD ${@}"; \ - fi -ifeq (${COMPILER}, gcc) - @if [ 'x${VERBOSE}' != x ]; \ - then \ - echo ${LD} -T ${SCATTER_${notdir ${@:.axf=}}} \ - --entry ${ENTRY_${notdir ${@:.axf=}}} \ - ${LDFLAGSgcc_${notdir ${@:.axf=}}} \ - ${LDFLAGS} -o ${@} ${^} \ - '${LIBC}' '${LIBGCC}'; \ - fi - @${LD} -T ${SCATTER_${notdir ${@:.axf=}}} \ - --entry ${ENTRY_${notdir ${@:.axf=}}} \ - ${LDFLAGSgcc_${notdir ${@:.axf=}}} \ - ${LDFLAGS} -o ${@} ${^} \ - '${LIBC}' '${LIBGCC}' - @${OBJCOPY} -O binary ${@} ${@:.axf=.bin} -endif diff --git a/Demo/CORTEX_LM3S811_GCC/standalone.ld b/Demo/CORTEX_LM3S811_GCC/standalone.ld deleted file mode 100644 index 8ee3fe2f8..000000000 --- a/Demo/CORTEX_LM3S811_GCC/standalone.ld +++ /dev/null @@ -1,60 +0,0 @@ -/****************************************************************************** - * - * standalone.ld - Linker script for applications using startup.c and - * DriverLib. - * - * Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. - * - * Software License Agreement - * - * Luminary Micro, Inc. (LMI) is supplying this software for use solely and - * exclusively on LMI's microcontroller products. - * - * The software is owned by LMI and/or its suppliers, and is protected under - * applicable copyright laws. All rights are reserved. Any use in violation - * of the foregoing restrictions may subject the user to criminal sanctions - * under applicable laws, as well as to civil liability for the breach of the - * terms and conditions of this license. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - * This is part of revision 1049 of the Stellaris Driver Library. - * - *****************************************************************************/ - -MEMORY -{ - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K - SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 8K -} - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text) - *(.rodata*) - _etext = .; - } > FLASH - - .data : AT (ADDR(.text) + SIZEOF(.text)) - { - _data = .; - *(vtable) - *(.data) - _edata = .; - } > SRAM - - .bss : - { - _bss = .; - *(.bss) - *(COMMON) - _ebss = .; - } > SRAM -} diff --git a/Demo/CORTEX_LM3S811_IAR/FreeRTOSConfig.h b/Demo/CORTEX_LM3S811_IAR/FreeRTOSConfig.h deleted file mode 100644 index e33887ba2..000000000 --- a/Demo/CORTEX_LM3S811_IAR/FreeRTOSConfig.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 ) -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 70 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 7000 ) ) -#define configMAX_TASK_NAME_LEN ( 10 ) -#define configUSE_TRACE_FACILITY 0 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 0 -#define configUSE_CO_ROUTINES 1 - -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 0 -#define INCLUDE_uxTaskPriorityGet 0 -#define INCLUDE_vTaskDelete 0 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 0 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 - - - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/DriverLib.h b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/DriverLib.h deleted file mode 100644 index 47531fbe9..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/DriverLib.h +++ /dev/null @@ -1,39 +0,0 @@ -#ifndef DRIVER_LIB_H -#define DRIVER_LIB_H - -#include "DriverLib.h" -#include "hw_adc.h" -#include "hw_comp.h" -#include "hw_flash.h" -#include "hw_gpio.h" -#include "hw_i2c.h" -#include "hw_ints.h" -#include "hw_memmap.h" -#include "hw_nvic.h" -#include "hw_pwm.h" -#include "hw_qei.h" -#include "hw_ssi.h" -#include "hw_sysctl.h" -#include "hw_timer.h" -#include "hw_types.h" -#include "hw_uart.h" -#include "hw_watchdog.h" -#include "osram96x16.h" -#include "adc.h" -#include "comp.h" -#include "cpu.h" -#include "debug.h" -#include "flash.h" -#include "gpio.h" -#include "i2c.h" -#include "interrupt.h" -#include "pwm.h" -#include "qei.h" -#include "ssi.h" -#include "sysctl.h" -#include "systick.h" -#include "timer.h" -#include "uart.h" -#include "watchdog.h" - -#endif diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/EULA.txt b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/EULA.txt deleted file mode 100644 index 02c57b2f9..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/EULA.txt +++ /dev/null @@ -1,126 +0,0 @@ -IMPORTANT. Read the following LMI Software License Agreement ("Agreement") -completely. - -LUMINARY MICRO SOFTWARE LICENSE AGREEMENT - - This is a legal agreement between you (either as an individual or as an -authorized representative of your employer) and Luminary Micro, Inc. ("LMI"). -It concerns your rights to use this file and any accompanying written materials -(the "Software"). In consideration for LMI allowing you to access the -Software, you are agreeing to be bound by the terms of this Agreement. If you -do not agree to all of the terms of this Agreement, do not download or use the -Software. If you change your mind later, stop using the Software and delete -all copies of the Software in your possession or control. Any copies of the -Software that you have already distributed, where permitted, and do not destroy -will continue to be governed by this Agreement. Your prior use will also -continue to be governed by this Agreement. - -1. LICENSE GRANT. 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You agree that the statutes and -laws of the United States and the State of Texas, USA, without regard to -conflicts of laws principles, will apply to all matters relating to this -Agreement or the Software, and you agree that any litigation will be subject to -the exclusive jurisdiction of the state or federal courts in Austin, Travis -County, Texas, USA. You agree that regardless of any statute or law to the -contrary, any claim or cause of action arising out of or related to this -Agreement or the Software must be filed within one (1) year after such claim or -cause of action arose or be forever barred. - -12. ENTIRE AGREEMENT. This Agreement constitutes the entire agreement -between you and LMI regarding the subject matter of this Agreement, and -supersedes all prior communications, negotiations, understandings, agreements -or representations, either written or oral, if any. This Agreement may only be -amended in written form, executed by you and LMI. - -13. SEVERABILITY. If any provision of this Agreement is held for any -reason to be invalid or unenforceable, then the remaining provisions of this -Agreement will be unimpaired and, unless a modification or replacement of the -invalid or unenforceable provision is further held to deprive you or LMI of a -material benefit, in which case the Agreement will immediately terminate, the -invalid or unenforceable provision will be replaced with a provision that is -valid and enforceable and that comes closest to the intention underlying the -invalid or unenforceable provision. - -14. NO WAIVER. The waiver by LMI of any breach of any provision of this -Agreement will not operate or be construed as a waiver of any other or a -subsequent breach of the same or a different provision. diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/adc.c b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/adc.c deleted file mode 100644 index 53f3adf5b..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/adc.c +++ /dev/null @@ -1,946 +0,0 @@ -//***************************************************************************** -// -// adc.c - Driver for the ADC. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup adc_api -//! @{ -// -//***************************************************************************** - -#include "../hw_adc.h" -#include "../hw_ints.h" -#include "../hw_memmap.h" -#include "../hw_types.h" -#include "adc.h" -#include "debug.h" -#include "interrupt.h" - -//***************************************************************************** -// -// The currently configured software oversampling factor for each of the ADC -// sequencers. -// -//***************************************************************************** -#if defined(GROUP_pucoverssamplefactor) || defined(BUILD_ALL) -unsigned char g_pucOversampleFactor[3]; -#else -extern unsigned char g_pucOversampleFactor[3]; -#endif - -//***************************************************************************** -// -//! Registers an interrupt handler for an ADC interrupt. -//! -//! \param ulBase is the base address of the ADC module. -//! \param ulSequenceNum is the sample sequence number. -//! \param pfnHandler is a pointer to the function to be called when the -//! ADC sample sequence interrupt occurs. -//! -//! This function sets the handler to be called when a sample sequence -//! interrupt occurs. This will enable the global interrupt in the interrupt -//! controller; the sequence interrupt must be enabled with ADCIntEnable(). It -//! is the interrupt handler's responsibility to clear the interrupt source via -//! ADCIntClear(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum, - void (*pfnHandler)(void)) -{ - unsigned long ulInt; - - // - // Check the arguments. - // - ASSERT(ulBase == ADC_BASE); - ASSERT(ulSequenceNum < 4); - - // - // Determine the interrupt to register based on the sequence number. - // - ulInt = INT_ADC0 + ulSequenceNum; - - // - // Register the interrupt handler. - // - IntRegister(ulInt, pfnHandler); - - // - // Enable the timer interrupt. - // - IntEnable(ulInt); -} -#endif - -//***************************************************************************** -// -//! Unregisters the interrupt handler for an ADC interrupt. -//! -//! \param ulBase is the base address of the ADC module. -//! \param ulSequenceNum is the sample sequence number. -//! -//! This function unregisters the interrupt handler. This will disable the -//! global interrupt in the interrupt controller; the sequence interrupt must -//! be disabled via ADCIntDisable(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -ADCIntUnregister(unsigned long ulBase, unsigned long ulSequenceNum) -{ - unsigned long ulInt; - - // - // Check the arguments. - // - ASSERT(ulBase == ADC_BASE); - ASSERT(ulSequenceNum < 4); - - // - // Determine the interrupt to unregister based on the sequence number. - // - ulInt = INT_ADC0 + ulSequenceNum; - - // - // Disable the interrupt. - // - IntDisable(ulInt); - - // - // Unregister the interrupt handler. - // - IntUnregister(ulInt); -} -#endif - -//***************************************************************************** -// -//! Disables a sample sequence interrupt. -//! -//! \param ulBase is the base address of the ADC module. -//! \param ulSequenceNum is the sample sequence number. -//! -//! This function disables the requested sample sequence interrupt. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum) -{ - // - // Check the arguments. - // - ASSERT(ulBase == ADC_BASE); - ASSERT(ulSequenceNum < 4); - - // - // Disable this sample sequence interrupt. - // - HWREG(ulBase + ADC_O_IM) &= ~(1 << ulSequenceNum); -} -#endif - -//***************************************************************************** -// -//! Enables a sample sequence interrupt. -//! -//! \param ulBase is the base address of the ADC module. -//! \param ulSequenceNum is the sample sequence number. -//! -//! This function enables the requested sample sequence interrupt. Any -//! outstanding interrupts are cleared before enabling the sample sequence -//! interrupt. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum) -{ - // - // Check the arguments. - // - ASSERT(ulBase == ADC_BASE); - ASSERT(ulSequenceNum < 4); - - // - // Clear any outstanding interrupts on this sample sequence. - // - HWREG(ulBase + ADC_O_ISC) = 1 << ulSequenceNum; - - // - // Enable this sample sequence interrupt. - // - HWREG(ulBase + ADC_O_IM) |= 1 << ulSequenceNum; -} -#endif - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \param ulBase is the base address of the ADC module. -//! \param ulSequenceNum is the sample sequence number. -//! \param bMasked is false if the raw interrupt status is required and true if -//! the masked interrupt status is required. -//! -//! This returns the interrupt status for the specified sample sequence. -//! Either the raw interrupt status or the status of interrupts that are -//! allowed to reflect to the processor can be returned. -//! -//! \return The current raw or masked interrupt status. -// -//***************************************************************************** -#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -ADCIntStatus(unsigned long ulBase, unsigned long ulSequenceNum, - tBoolean bMasked) -{ - // - // Check the arguments. - // - ASSERT(ulBase == ADC_BASE); - ASSERT(ulSequenceNum < 4); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(ulBase + ADC_O_ISC) & (1 << ulSequenceNum)); - } - else - { - return(HWREG(ulBase + ADC_O_RIS) & (1 << ulSequenceNum)); - } -} -#endif - -//***************************************************************************** -// -//! Clears sample sequence interrupt source. -//! -//! \param ulBase is the base address of the ADC module. -//! \param ulSequenceNum is the sample sequence number. -//! -//! The specified sample sequence interrupt is cleared, so that it no longer -//! asserts. This must be done in the interrupt handler to keep it from being -//! called again immediately upon exit. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) -void -ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum) -{ - // - // Check the arugments. - // - ASSERT(ulBase == ADC_BASE); - ASSERT(ulSequenceNum < 4); - - // - // Clear the interrupt. - // - HWREG(ulBase + ADC_O_ISC) = 1 << ulSequenceNum; -} -#endif - -//***************************************************************************** -// -//! Enables a sample sequence. -//! -//! \param ulBase is the base address of the ADC module. -//! \param ulSequenceNum is the sample sequence number. -//! -//! Allows the specified sample sequence to be captured when its trigger is -//! detected. A sample sequence must be configured before it is enabled. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_sequenceenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -ADCSequenceEnable(unsigned long ulBase, unsigned long ulSequenceNum) -{ - // - // Check the arugments. - // - ASSERT(ulBase == ADC_BASE); - ASSERT(ulSequenceNum < 4); - - // - // Enable the specified sequence. - // - HWREG(ulBase + ADC_O_ACTSS) |= 1 << ulSequenceNum; -} -#endif - -//***************************************************************************** -// -//! Disables a sample sequence. -//! -//! \param ulBase is the base address of the ADC module. -//! \param ulSequenceNum is the sample sequence number. -//! -//! Prevents the specified sample sequence from being captured when its trigger -//! is detected. A sample sequence should be disabled before it is configured. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_sequencedisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -ADCSequenceDisable(unsigned long ulBase, unsigned long ulSequenceNum) -{ - // - // Check the arugments. - // - ASSERT(ulBase == ADC_BASE); - ASSERT(ulSequenceNum < 4); - - // - // Disable the specified sequences. - // - HWREG(ulBase + ADC_O_ACTSS) &= ~(1 << ulSequenceNum); -} -#endif - -//***************************************************************************** -// -//! Configures the trigger source and priority of a sample sequence. -//! -//! \param ulBase is the base address of the ADC module. -//! \param ulSequenceNum is the sample sequence number. -//! \param ulTrigger is the trigger source that initiates the sample sequence; -//! must be one of the \b ADC_TRIGGER_* values. -//! \param ulPriority is the relative priority of the sample sequence with -//! respect to the other sample sequences. -//! -//! This function configures the initiation criteria for a sample sequence. -//! Valid sample sequences range from zero to three; sequence zero will capture -//! up to eight samples, sequences one and two will capture up to four samples, -//! and sequence three will capture a single sample. The trigger condition and -//! priority (with respect to other sample sequence execution) is set. -//! -//! The parameter \b ulTrigger can take on the following values: -//! -//! - \b ADC_TRIGGER_PROCESSOR - A trigger generated by the processor, via the -//! ADCProcessorTrigger() function. -//! - \b ADC_TRIGGER_COMP0 - A trigger generated by the first analog -//! comparator; configured with ComparatorConfigure(). -//! - \b ADC_TRIGGER_COMP1 - A trigger generated by the second analog -//! comparator; configured with ComparatorConfigure(). -//! - \b ADC_TRIGGER_COMP2 - A trigger generated by the third analog -//! comparator; configured with ComparatorConfigure(). -//! - \b ADC_TRIGGER_EXTERNAL - A trigger generated by an input from the Port -//! B4 pin. -//! - \b ADC_TRIGGER_TIMER - A trigger generated by a timer; configured with -//! TimerControlTrigger(). -//! - \b ADC_TRIGGER_PWM0 - A trigger generated by the first PWM generator; -//! configured with PWMGenIntTrigEnable(). -//! - \b ADC_TRIGGER_PWM1 - A trigger generated by the second PWM generator; -//! configured with PWMGenIntTrigEnable(). -//! - \b ADC_TRIGGER_PWM2 - A trigger generated by the third PWM generator; -//! configured with PWMGenIntTrigEnable(). -//! - \b ADC_TRIGGER_ALWAYS - A trigger that is always asserted, causing the -//! sample sequence to capture repeatedly (so long as -//! there is not a higher priority source active). -//! -//! Note that not all trigger sources are available on all Stellaris family -//! members; consult the data sheet for the device in question to determine the -//! availability of triggers. -//! -//! The parameter \b ulPriority is a value between 0 and 3, where 0 represents -//! the highest priority and 3 the lowest. Note that when programming the -//! priority among a set of sample sequences, each must have unique priority; -//! it is up to the caller to guarantee the uniqueness of the priorities. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_sequenceconfigure) || defined(BUILD_ALL) || defined(DOXYGEN) -void -ADCSequenceConfigure(unsigned long ulBase, unsigned long ulSequenceNum, - unsigned long ulTrigger, unsigned long ulPriority) -{ - // - // Check the arugments. - // - ASSERT(ulBase == ADC_BASE); - ASSERT(ulSequenceNum < 4); - ASSERT((ulTrigger == ADC_TRIGGER_PROCESSOR) || - (ulTrigger == ADC_TRIGGER_COMP0) || - (ulTrigger == ADC_TRIGGER_COMP1) || - (ulTrigger == ADC_TRIGGER_COMP2) || - (ulTrigger == ADC_TRIGGER_EXTERNAL) || - (ulTrigger == ADC_TRIGGER_TIMER) || - (ulTrigger == ADC_TRIGGER_PWM0) || - (ulTrigger == ADC_TRIGGER_PWM1) || - (ulTrigger == ADC_TRIGGER_PWM2) || - (ulTrigger == ADC_TRIGGER_ALWAYS)); - ASSERT(ulPriority < 4); - - // - // Compute the shift for the bits that control this sample sequence. - // - ulSequenceNum *= 4; - - // - // Set the trigger event for this sample sequence. - // - HWREG(ulBase + ADC_O_EMUX) = ((HWREG(ulBase + ADC_O_EMUX) & - ~(0xf << ulSequenceNum)) | - ((ulTrigger & 0xf) << ulSequenceNum)); - - // - // Set the priority for this sample sequence. - // - HWREG(ulBase + ADC_O_SSPRI) = ((HWREG(ulBase + ADC_O_SSPRI) & - ~(0xf << ulSequenceNum)) | - ((ulPriority & 0x3) << ulSequenceNum)); -} -#endif - -//***************************************************************************** -// -//! Configure a step of the sample sequencer. -//! -//! \param ulBase is the base address of the ADC module. -//! \param ulSequenceNum is the sample sequence number. -//! \param ulStep is the step to be configured. -//! \param ulConfig is the configuration of this step; must be a logical OR of -//! \b ADC_CTL_TS, \b ADC_CTL_IE, \b ADC_CTL_END, \b ADC_CTL_D, and one of the -//! input channel selects (\b ADC_CTL_CH0 through \b ADC_CTL_CH7). -//! -//! This function will set the configuration of the ADC for one step of a -//! sample sequence. The ADC can be configured for single-ended or -//! differential operation (the \b ADC_CTL_D bit selects differential -//! operation when set), the channel to be sampled can be chosen (the -//! \b ADC_CTL_CH0 through \b ADC_CTL_CH7 values), and the internal temperature -//! sensor can be selected (the \b ADC_CTL_TS bit). Additionally, this step -//! can be defined as the last in the sequence (the \b ADC_CTL_END bit) and it -//! can be configured to cause an interrupt when the step is complete (the -//! \b ADC_CTL_IE bit). The configuration is used by the ADC at the -//! appropriate time when the trigger for this sequence occurs. -//! -//! The \b ulStep parameter determines the order in which the samples are -//! captured by the ADC when the trigger occurs. It can range from zero to -//! seven for the first sample sequence, from zero to three for the second and -//! third sample sequence, and can only be zero for the fourth sample sequence. -//! -//! Differential mode only works with adjacent channel pairs (e.g. 0 and 1). -//! The channel select must be the number of the channel pair to sample (e.g. -//! \b ADC_CTL_CH0 for 0 and 1, or \b ADC_CTL_CH1 for 2 and 3) or undefined -//! results will be returned by the ADC. Additionally, if differential mode is -//! selected when the temperature sensor is being sampled, undefined results -//! will be returned by the ADC. -//! -//! It is the responsibility of the caller to ensure that a valid configuration -//! is specified; this function does not check the validity of the specified -//! configuration. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_sequencestepconfigure) || defined(BUILD_ALL) || \ - defined(DOXYGEN) -void -ADCSequenceStepConfigure(unsigned long ulBase, unsigned long ulSequenceNum, - unsigned long ulStep, unsigned long ulConfig) -{ - // - // Check the arugments. - // - ASSERT(ulBase == ADC_BASE); - ASSERT(ulSequenceNum < 4); - ASSERT(((ulSequenceNum == 0) && (ulStep < 8)) || - ((ulSequenceNum == 1) && (ulStep < 4)) || - ((ulSequenceNum == 2) && (ulStep < 4)) || - ((ulSequenceNum == 3) && (ulStep < 1))); - - // - // Get the offset of the sequence to be configured. - // - ulBase += ADC_O_SEQ + (ADC_O_SEQ_STEP * ulSequenceNum); - - // - // Compute the shift for the bits that control this step. - // - ulStep *= 4; - - // - // Set the analog mux value for this step. - // - HWREG(ulBase + ADC_O_X_SSMUX) = ((HWREG(ulBase + ADC_O_X_SSMUX) & - ~(0x0000000f << ulStep)) | - ((ulConfig & 0x0f) << ulStep)); - - // - // Set the control value for this step. - // - HWREG(ulBase + ADC_O_X_SSCTL) = ((HWREG(ulBase + ADC_O_X_SSCTL) & - ~(0x0000000f << ulStep)) | - (((ulConfig & 0xf0) >> 4) << ulStep)); -} -#endif - -//***************************************************************************** -// -//! Determines if a sample sequence overflow occurred. -//! -//! \param ulBase is the base address of the ADC module. -//! \param ulSequenceNum is the sample sequence number. -//! -//! This determines if a sample sequence overflow has occurred. This will -//! happen if the captured samples are not read from the FIFO before the next -//! trigger occurs. -//! -//! \return Returns zero if there was not an overflow, and non-zero if there -//! was. -// -//***************************************************************************** -#if defined(GROUP_sequenceoverflow) || defined(BUILD_ALL) || defined(DOXYGEN) -long -ADCSequenceOverflow(unsigned long ulBase, unsigned long ulSequenceNum) -{ - // - // Check the arguments. - // - ASSERT(ulBase == ADC_BASE); - ASSERT(ulSequenceNum < 4); - - // - // Determine if there was an overflow on this sequence. - // - return(HWREG(ulBase + ADC_O_OSTAT) & (1 << ulSequenceNum)); -} -#endif - -//***************************************************************************** -// -//! Determines if a sample sequence underflow occurred. -//! -//! \param ulBase is the base address of the ADC module. -//! \param ulSequenceNum is the sample sequence number. -//! -//! This determines if a sample sequence underflow has occurred. This will -//! happen if too many samples are read from the FIFO. -//! -//! \return Returns zero if there was not an underflow, and non-zero if there -//! was. -// -//***************************************************************************** -#if defined(GROUP_sequenceunderflow) || defined(BUILD_ALL) || defined(DOXYGEN) -long -ADCSequenceUnderflow(unsigned long ulBase, unsigned long ulSequenceNum) -{ - // - // Check the arguments. - // - ASSERT(ulBase == ADC_BASE); - ASSERT(ulSequenceNum < 4); - - // - // Determine if there was an underflow on this sequence. - // - return(HWREG(ulBase + ADC_O_USTAT) & (1 << ulSequenceNum)); -} -#endif - -//***************************************************************************** -// -//! Gets the captured data for a sample sequence. -//! -//! \param ulBase is the base address of the ADC module. -//! \param ulSequenceNum is the sample sequence number. -//! \param pulBuffer is the address where the data is stored. -//! -//! This function copies data from the specified sample sequence output FIFO to -//! a memory resident buffer. The number of samples available in the hardware -//! FIFO are copied into the buffer, which is assumed to be large enough to -//! hold that many samples. This will only return the samples that are -//! presently available, which may not be the entire sample sequence if it is -//! in the process of being executed. -//! -//! \return Returns the number of samples copied to the buffer. -// -//***************************************************************************** -#if defined(GROUP_sequencedataget) || defined(BUILD_ALL) || defined(DOXYGEN) -long -ADCSequenceDataGet(unsigned long ulBase, unsigned long ulSequenceNum, - unsigned long *pulBuffer) -{ - unsigned long ulCount; - - // - // Check the arguments. - // - ASSERT(ulBase == ADC_BASE); - ASSERT(ulSequenceNum < 4); - - // - // Get the offset of the sequence to be read. - // - ulBase += ADC_O_SEQ + (ADC_O_SEQ_STEP * ulSequenceNum); - - // - // Read samples from the FIFO until it is empty. - // - ulCount = 0; - while(!(HWREG(ulBase + ADC_O_X_SSFSTAT) & ADC_SSFSTAT_EMPTY) && - (ulCount < 8)) - { - // - // Read the FIFO and copy it to the destination. - // - *pulBuffer++ = HWREG(ulBase + ADC_O_X_SSFIFO); - - // - // Increment the count of samples read. - // - ulCount++; - } - - // - // Return the number of samples read. - // - return(ulCount); -} -#endif - -//***************************************************************************** -// -//! Causes a processor trigger for a sample sequence. -//! -//! \param ulBase is the base address of the ADC module. -//! \param ulSequenceNum is the sample sequence number. -//! -//! This function triggers a processor-initiated sample sequence if the sample -//! sequence trigger is configured to ADC_TRIGGER_PROCESSOR. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_processortrigger) || defined(BUILD_ALL) || defined(DOXYGEN) -void -ADCProcessorTrigger(unsigned long ulBase, unsigned long ulSequenceNum) -{ - // - // Check the arguments. - // - ASSERT(ulBase == ADC_BASE); - ASSERT(ulSequenceNum < 4); - - // - // Generate a processor trigger for this sample sequence. - // - HWREG(ulBase + ADC_O_PSSI) = 1 << ulSequenceNum; -} -#endif - -//***************************************************************************** -// -//! Configures the software oversampling factor of the ADC. -//! -//! \param ulBase is the base address of the ADC module. -//! \param ulSequenceNum is the sample sequence number. -//! \param ulFactor is the number of samples to be averaged. -//! -//! This function configures the software oversampling for the ADC, which can -//! be used to provide better resolution on the sampled data. Oversampling is -//! accomplished by averaging multiple samples from the same analog input. -//! Three different oversampling rates are supported; 2x, 4x, and 8x. -//! -//! Oversampling is only supported on the sample sequencers that are more than -//! one sample in depth (i.e. the fourth sample sequencer is not supported). -//! Oversampling by 2x (for example) divides the depth of the sample sequencer -//! by two; so 2x oversampling on the first sample sequencer can only provide -//! four samples per trigger. This also means that 8x oversampling is only -//! available on the first sample sequencer. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_softwareoversampleconfigure) || defined(BUILD_ALL) || \ - defined(DOXYGEN) -void -ADCSoftwareOversampleConfigure(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long ulFactor) -{ - unsigned long ulValue; - - // - // Check the arguments. - // - ASSERT(ulBase == ADC_BASE); - ASSERT(ulSequenceNum < 3); - ASSERT(((ulFactor == 2) || (ulFactor == 4) || (ulFactor == 8)) && - ((ulSequenceNum == 0) || (ulFactor != 8))); - - // - // Convert the oversampling factor to a shift factor. - // - for(ulValue = 0, ulFactor >>= 1; ulFactor; ulValue++, ulFactor >>= 1) - { - } - - // - // Save the sfiht factor. - // - g_pucOversampleFactor[ulSequenceNum] = ulValue; -} -#endif - -//***************************************************************************** -// -//! Configures a step of the software oversampled sequencer. -//! -//! \param ulBase is the base address of the ADC module. -//! \param ulSequenceNum is the sample sequence number. -//! \param ulStep is the step to be configured. -//! \param ulConfig is the configuration of this step. -//! -//! This function configures a step of the sample sequencer when using the -//! software oversampling feature. The number of steps available depends on -//! the oversampling factor set by ADCSoftwareOversampleConfigure(). The value -//! of \e ulConfig is the same as defined for ADCSequenceStepConfigure(). -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_softwareoversamplestepconfigure) || defined(BUILD_ALL) || \ - defined(DOXYGEN) -void -ADCSoftwareOversampleStepConfigure(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long ulStep, - unsigned long ulConfig) -{ - // - // Check the arguments. - // - ASSERT(ulBase == ADC_BASE); - ASSERT(ulSequenceNum < 3); - ASSERT(((ulSequenceNum == 0) && - (ulStep < (8 >> g_pucOversampleFactor[ulSequenceNum]))) || - (ulStep < (4 >> g_pucOversampleFactor[ulSequenceNum]))); - - // - // Get the offset of the sequence to be configured. - // - ulBase += ADC_O_SEQ + (ADC_O_SEQ_STEP * ulSequenceNum); - - // - // Compute the shift for the bits that control this step. - // - ulStep *= 4 << g_pucOversampleFactor[ulSequenceNum]; - - // - // Loop through the hardware steps that make up this step of the software - // oversampled sequence. - // - for(ulSequenceNum = 1 << g_pucOversampleFactor[ulSequenceNum]; - ulSequenceNum; ulSequenceNum--) - { - // - // Set the analog mux value for this step. - // - HWREG(ulBase + ADC_O_X_SSMUX) = ((HWREG(ulBase + ADC_O_X_SSMUX) & - ~(0x0000000f << ulStep)) | - ((ulConfig & 0x0f) << ulStep)); - - // - // Set the control value for this step. - // - HWREG(ulBase + ADC_O_X_SSCTL) = ((HWREG(ulBase + ADC_O_X_SSCTL) & - ~(0x0000000f << ulStep)) | - (((ulConfig & 0xf0) >> 4) << ulStep)); - if(ulSequenceNum != 1) - { - HWREG(ulBase + ADC_O_X_SSCTL) &= ~((ADC_SSCTL_IE0 | - ADC_SSCTL_END0) << ulStep); - } - - // - // Go to the next hardware step. - // - ulStep += 4; - } -} -#endif - -//***************************************************************************** -// -//! Gets the captured data for a sample sequence using software oversampling. -//! -//! \param ulBase is the base address of the ADC module. -//! \param ulSequenceNum is the sample sequence number. -//! \param pulBuffer is the address where the data is stored. -//! \param ulCount is the number of samples to be read. -//! -//! This function copies data from the specified sample sequence output FIFO to -//! a memory resident buffer with software oversampling applied. The requested -//! number of samples are copied into the data buffer; if there are not enough -//! samples in the hardware FIFO to satisfy this many oversampled data items -//! then incorrect results will be returned. It is the caller's responsibility -//! to read only the samples that are available and wait until enough data is -//! available, for example as a result of receiving an interrupt. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_softwareoversampledataget) || defined(BUILD_ALL) || \ - defined(DOXYGEN) -void -ADCSoftwareOversampleDataGet(unsigned long ulBase, unsigned long ulSequenceNum, - unsigned long *pulBuffer, unsigned long ulCount) -{ - unsigned long ulIdx, ulAccum; - - // - // Check the arguments. - // - ASSERT(ulBase == ADC_BASE); - ASSERT(ulSequenceNum < 3); - ASSERT(((ulSequenceNum == 0) && - (ulCount < (8 >> g_pucOversampleFactor[ulSequenceNum]))) || - (ulCount < (4 >> g_pucOversampleFactor[ulSequenceNum]))); - - // - // Get the offset of the sequence to be read. - // - ulBase += ADC_O_SEQ + (ADC_O_SEQ_STEP * ulSequenceNum); - - // - // Read the samples from the FIFO until it is empty. - // - while(ulCount--) - { - // - // Compute the sum of the samples. - // - ulAccum = 0; - for(ulIdx = 1 << g_pucOversampleFactor[ulSequenceNum]; ulIdx; ulIdx--) - { - // - // Read the FIFO and add it to the accumulator. - // - ulAccum += HWREG(ulBase + ADC_O_X_SSFIFO); - } - - // - // Write the averaged sample to the output buffer. - // - *pulBuffer++ = ulAccum >> g_pucOversampleFactor[ulSequenceNum]; - } -} -#endif - -//***************************************************************************** -// -//! Configures the hardware oversampling factor of the ADC. -//! -//! \param ulBase is the base address of the ADC module. -//! \param ulFactor is the number of samples to be averaged. -//! -//! This function configures the hardware oversampling for the ADC, which can -//! be used to provide better resolution on the sampled data. Oversampling is -//! accomplished by averaging multiple samples from the same analog input. Six -//! different oversampling rates are supported; 2x, 4x, 8x, 16x, 32x, and 64x. -//! Specifying an oversampling factor of zero will disable the hardware -//! oversampler. -//! -//! Hardware oversampling applies uniformly to all sample sequencers. It does -//! not reduce the depth of the sample sequencers like the software -//! oversampling APIs; each sample written into the sample sequence FIFO is a -//! fully oversampled analog input reading. -//! -//! Enabling hardware averaging increases the precision of the ADC at the cost -//! of throughput. For example, enabling 4x oversampling reduces the -//! throughput of a 250 KSps ADC to 62.5 KSps. -//! -//! \note Hardware oversampling is available beginning with Rev C0 of the -//! Stellaris microcontroller. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_hardwareoversampleconfigure) || defined(BUILD_ALL) || \ - defined(DOXYGEN) -void -ADCHardwareOversampleConfigure(unsigned long ulBase, - unsigned long ulFactor) -{ - unsigned long ulValue; - - // - // Check the arguments. - // - ASSERT(ulBase == ADC_BASE); - ASSERT(((ulFactor == 0) || (ulFactor == 2) || (ulFactor == 4) || - (ulFactor == 8) || (ulFactor == 16) || (ulFactor == 32) || - (ulFactor == 64))); - - // - // Convert the oversampling factor to a shift factor. - // - for(ulValue = 0, ulFactor >>= 1; ulFactor; ulValue++, ulFactor >>= 1) - { - } - - // - // Write the shift factor to the ADC to configure the hardware oversampler. - // - HWREG(ulBase + ADC_O_SAC) = ulValue; -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/adc.h b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/adc.h deleted file mode 100644 index c1fa37da4..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/adc.h +++ /dev/null @@ -1,126 +0,0 @@ -//***************************************************************************** -// -// adc.h - ADC headers for using the ADC driver functions. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __ADC_H__ -#define __ADC_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to ADCSequenceConfigure as the ulTrigger -// parameter. -// -//***************************************************************************** -#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event -#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event -#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event -#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event -#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event -#define ADC_TRIGGER_TIMER 0x00000005 // Timer event -#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event -#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event -#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event -#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event - -//***************************************************************************** -// -// Values that can be passed to ADCSequenceStepConfigure as the ulConfig -// parameter. -// -//***************************************************************************** -#define ADC_CTL_TS 0x00000080 // Temperature sensor select -#define ADC_CTL_IE 0x00000040 // Interrupt enable -#define ADC_CTL_END 0x00000020 // Sequence end select -#define ADC_CTL_D 0x00000010 // Differential select -#define ADC_CTL_CH0 0x00000000 // Input channel 0 -#define ADC_CTL_CH1 0x00000001 // Input channel 1 -#define ADC_CTL_CH2 0x00000002 // Input channel 2 -#define ADC_CTL_CH3 0x00000003 // Input channel 3 -#define ADC_CTL_CH4 0x00000004 // Input channel 4 -#define ADC_CTL_CH5 0x00000005 // Input channel 5 -#define ADC_CTL_CH6 0x00000006 // Input channel 6 -#define ADC_CTL_CH7 0x00000007 // Input channel 7 - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum, - void (*pfnHandler)(void)); -extern void ADCIntUnregister(unsigned long ulBase, - unsigned long ulSequenceNum); -extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum); -extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum); -extern unsigned long ADCIntStatus(unsigned long ulBase, - unsigned long ulSequenceNum, - tBoolean bMasked); -extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum); -extern void ADCSequenceEnable(unsigned long ulBase, - unsigned long ulSequenceNum); -extern void ADCSequenceDisable(unsigned long ulBase, - unsigned long ulSequenceNum); -extern void ADCSequenceConfigure(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long ulTrigger, - unsigned long ulPriority); -extern void ADCSequenceStepConfigure(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long ulStep, - unsigned long ulConfig); -extern long ADCSequenceOverflow(unsigned long ulBase, - unsigned long ulSequenceNum); -extern long ADCSequenceUnderflow(unsigned long ulBase, - unsigned long ulSequenceNum); -extern long ADCSequenceDataGet(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long *pulBuffer); -extern void ADCProcessorTrigger(unsigned long ulBase, - unsigned long ulSequenceNum); -extern void ADCSoftwareOversampleConfigure(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long ulFactor); -extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long ulStep, - unsigned long ulConfig); -extern void ADCSoftwareOversampleDataGet(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long *pulBuffer, - unsigned long ulCount); -extern void ADCHardwareOversampleConfigure(unsigned long ulBase, - unsigned long ulFactor); - -#ifdef __cplusplus -} -#endif - -#endif // __ADC_H__ diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/comp.c b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/comp.c deleted file mode 100644 index aed156ea5..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/comp.c +++ /dev/null @@ -1,448 +0,0 @@ -//***************************************************************************** -// -// comp.c - Driver for the analog comparator. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup comp_api -//! @{ -// -//***************************************************************************** - -#include "../hw_comp.h" -#include "../hw_ints.h" -#include "../hw_memmap.h" -#include "../hw_types.h" -#include "comp.h" -#include "debug.h" -#include "interrupt.h" - -//***************************************************************************** -// -//! Configures a comparator. -//! -//! \param ulBase is the base address of the comparator module. -//! \param ulComp is the index of the comparator to configure. -//! \param ulConfig is the configuration of the comparator. -//! -//! This function will configure a comparator. The \e ulConfig parameter is -//! the result of a logical OR operation between the \b COMP_TRIG_xxx, -//! \b COMP_INT_xxx, \b COMP_ASRCP_xxx, and \b COMP_OUTPUT_xxx values. -//! -//! The \b COMP_TRIG_xxx term can take on the following values: -//! -//! - \b COMP_TRIG_NONE to have no trigger to the ADC. -//! - \b COMP_TRIG_HIGH to trigger the ADC when the comparator output is high. -//! - \b COMP_TRIG_LOW to trigger the ADC when the comparator output is low. -//! - \b COMP_TRIG_FALL to trigger the ADC when the comparator output goes low. -//! - \b COMP_TRIG_RISE to trigger the ADC when the comparator output goes -//! high. -//! - \b COMP_TRIG_BOTH to trigger the ADC when the comparator output goes low -//! or high. -//! -//! The \b COMP_INT_xxx term can take on the following values: -//! -//! - \b COMP_INT_HIGH to generate an interrupt when the comparator output is -//! high. -//! - \b COMP_INT_LOW to generate an interrupt when the comparator output is -//! low. -//! - \b COMP_INT_FALL to generate an interrupt when the comparator output goes -//! low. -//! - \b COMP_INT_RISE to generate an interrupt when the comparator output goes -//! high. -//! - \b COMP_INT_BOTH to generate an interrupt when the comparator output goes -//! low or high. -//! -//! The \b COMP_ASRCP_xxx term can take on the following values: -//! -//! - \b COMP_ASRCP_PIN to use the dedicated Comp+ pin as the reference -//! voltage. -//! - \b COMP_ASRCP_PIN0 to use the Comp0+ pin as the reference voltage (this -//! the same as \b COMP_ASRCP_PIN for the comparator 0). -//! - \b COMP_ASRCP_REF to use the internally generated voltage as the -//! reference voltage. -//! -//! The \b COMP_OUTPUT_xxx term can take on the following values: -//! -//! - \b COMP_OUTPUT_NONE to disable the output from the comparator to a device -//! pin. -//! - \b COMP_OUTPUT_NORMAL to enable a non-inverted output from the comparator -//! to a device pin. -//! - \b COMP_OUTPUT_INVERT to enable an inverted output from the comparator to -//! a device pin. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_configure) || defined(BUILD_ALL) || defined(DOXYGEN) -void -ComparatorConfigure(unsigned long ulBase, unsigned long ulComp, - unsigned long ulConfig) -{ - // - // Check the arguments. - // - ASSERT(ulBase == COMP_BASE); - ASSERT(ulComp < 3); - - // - // Configure this comparator. - // - HWREG(ulBase + (ulComp * 0x20) + COMP_O_ACCTL0) = ulConfig; -} -#endif - -//***************************************************************************** -// -//! Sets the internal reference voltage. -//! -//! \param ulBase is the base address of the comparator module. -//! \param ulRef is the desired reference voltage. -//! -//! This function will set the internal reference voltage value. The voltage -//! is specified as one of the following values: -//! -//! - \b COMP_REF_OFF to turn off the reference voltage -//! - \b COMP_REF_0V to set the reference voltage to 0 V -//! - \b COMP_REF_0_1375V to set the reference voltage to 0.1375 V -//! - \b COMP_REF_0_275V to set the reference voltage to 0.275 V -//! - \b COMP_REF_0_4125V to set the reference voltage to 0.4125 V -//! - \b COMP_REF_0_55V to set the reference voltage to 0.55 V -//! - \b COMP_REF_0_6875V to set the reference voltage to 0.6875 V -//! - \b COMP_REF_0_825V to set the reference voltage to 0.825 V -//! - \b COMP_REF_0_928125V to set the reference voltage to 0.928125 V -//! - \b COMP_REF_0_9625V to set the reference voltage to 0.9625 V -//! - \b COMP_REF_1_03125V to set the reference voltage to 1.03125 V -//! - \b COMP_REF_1_134375V to set the reference voltage to 1.134375 V -//! - \b COMP_REF_1_1V to set the reference voltage to 1.1 V -//! - \b COMP_REF_1_2375V to set the reference voltage to 1.2375 V -//! - \b COMP_REF_1_340625V to set the reference voltage to 1.340625 V -//! - \b COMP_REF_1_375V to set the reference voltage to 1.375 V -//! - \b COMP_REF_1_44375V to set the reference voltage to 1.44375 V -//! - \b COMP_REF_1_5125V to set the reference voltage to 1.5125 V -//! - \b COMP_REF_1_546875V to set the reference voltage to 1.546875 V -//! - \b COMP_REF_1_65V to set the reference voltage to 1.65 V -//! - \b COMP_REF_1_753125V to set the reference voltage to 1.753125 V -//! - \b COMP_REF_1_7875V to set the reference voltage to 1.7875 V -//! - \b COMP_REF_1_85625V to set the reference voltage to 1.85625 V -//! - \b COMP_REF_1_925V to set the reference voltage to 1.925 V -//! - \b COMP_REF_1_959375V to set the reference voltage to 1.959375 V -//! - \b COMP_REF_2_0625V to set the reference voltage to 2.0625 V -//! - \b COMP_REF_2_165625V to set the reference voltage to 2.165625 V -//! - \b COMP_REF_2_26875V to set the reference voltage to 2.26875 V -//! - \b COMP_REF_2_371875V to set the reference voltage to 2.371875 V -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_refset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -ComparatorRefSet(unsigned long ulBase, unsigned long ulRef) -{ - // - // Check the arguments. - // - ASSERT(ulBase == COMP_BASE); - - // - // Set the voltage reference voltage as requested. - // - HWREG(ulBase + COMP_O_REFCTL) = ulRef; -} -#endif - -//***************************************************************************** -// -//! Gets the current comparator output value. -//! -//! \param ulBase is the base address of the comparator module. -//! \param ulComp is the index of the comparator. -//! -//! This function retrieves the current value of the comparator output. -//! -//! \return Returns \b true if the comparator output is high and \b false if -//! the comparator output is low. -// -//***************************************************************************** -#if defined(GROUP_valueget) || defined(BUILD_ALL) || defined(DOXYGEN) -tBoolean -ComparatorValueGet(unsigned long ulBase, unsigned long ulComp) -{ - // - // Check the arguments. - // - ASSERT(ulBase == COMP_BASE); - ASSERT(ulComp < 3); - - // - // Return the appropriate value based on the comparator's present output - // value. - // - if(HWREG(ulBase + (ulComp * 0x20) + COMP_O_ACSTAT0) & COMP_ACSTAT_OVAL) - { - return(true); - } - else - { - return(false); - } -} -#endif - -//***************************************************************************** -// -//! Registers an interrupt handler for the comparator interrupt. -//! -//! \param ulBase is the base address of the comparator module. -//! \param ulComp is the index of the comparator. -//! \param pfnHandler is a pointer to the function to be called when the -//! comparator interrupt occurs. -//! -//! This sets the handler to be called when the comparator interrupt occurs. -//! This will enable the interrupt in the interrupt controller; it is the -//! interrupt-handler's responsibility to clear the interrupt source via -//! ComparatorIntClear(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp, - void (*pfnHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT(ulBase == COMP_BASE); - ASSERT(ulComp < 3); - - // - // Register the interrupt handler, returning an error if an error occurs. - // - IntRegister(INT_COMP0 + ulComp, pfnHandler); - - // - // Enable the interrupt in the interrupt controller. - // - IntEnable(INT_COMP0 + ulComp); - - // - // Enable the comparator interrupt. - // - HWREG(ulBase + COMP_O_INTEN) |= 1 << ulComp; -} -#endif - -//***************************************************************************** -// -//! Unregisters an interrupt handler for a comparator interrupt. -//! -//! \param ulBase is the base address of the comparator module. -//! \param ulComp is the index of the comparator. -//! -//! This function will clear the handler to be called when a comparator -//! interrupt occurs. This will also mask off the interrupt in the interrupt -//! controller so that the interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -ComparatorIntUnregister(unsigned long ulBase, unsigned long ulComp) -{ - // - // Check the arguments. - // - ASSERT(ulBase == COMP_BASE); - ASSERT(ulComp < 3); - - // - // Disable the comparator interrupt. - // - HWREG(ulBase + COMP_O_INTEN) &= ~(1 << ulComp); - - // - // Disable the interrupt in the interrupt controller. - // - IntDisable(INT_COMP0 + ulComp); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_COMP0 + ulComp); -} -#endif - -//***************************************************************************** -// -//! Enables the comparator interrupt. -//! -//! \param ulBase is the base address of the comparator module. -//! \param ulComp is the index of the comparator. -//! -//! This function enables generation of an interrupt from the specified -//! comparator. Only comparators whose interrupts are enabled can be reflected -//! to the processor. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp) -{ - // - // Check the arguments. - // - ASSERT(ulBase == COMP_BASE); - ASSERT(ulComp < 3); - - // - // Enable the comparator interrupt. - // - HWREG(ulBase + COMP_O_INTEN) |= 1 << ulComp; -} -#endif - -//***************************************************************************** -// -//! Disables the comparator interrupt. -//! -//! \param ulBase is the base address of the comparator module. -//! \param ulComp is the index of the comparator. -//! -//! This function disables generation of an interrupt from the specified -//! comparator. Only comparators whose interrupts are enabled can be reflected -//! to the processor. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp) -{ - // - // Check the arguments. - // - ASSERT(ulBase == COMP_BASE); - ASSERT(ulComp < 3); - - // - // Disable the comparator interrupt. - // - HWREG(ulBase + COMP_O_INTEN) &= ~(1 << ulComp); -} -#endif - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \param ulBase is the base address of the comparator module. -//! \param ulComp is the index of the comparator. -//! \param bMasked is \b false if the raw interrupt status is required and -//! \b true if the masked interrupt status is required. -//! -//! This returns the interrupt status for the comparator. Either the raw or -//! the masked interrupt status can be returned. -//! -//! \return \b true if the interrupt is asserted and \b false if it is not -//! asserted. -// -//***************************************************************************** -#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) -tBoolean -ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp, - tBoolean bMasked) -{ - // - // Check the arguments. - // - ASSERT(ulBase == COMP_BASE); - ASSERT(ulComp < 3); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(((HWREG(ulBase + COMP_O_MIS) >> ulComp) & 1) ? true : false); - } - else - { - return(((HWREG(ulBase + COMP_O_RIS) >> ulComp) & 1) ? true : false); - } -} -#endif - -//***************************************************************************** -// -//! Clears a comparator interrupt. -//! -//! \param ulBase is the base address of the comparator module. -//! \param ulComp is the index of the comparator. -//! -//! The comparator interrupt is cleared, so that it no longer asserts. This -//! must be done in the interrupt handler to keep it from being called again -//! immediately upon exit. Note that for a level triggered interrupt, the -//! interrupt cannot be cleared until it stops asserting. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) -void -ComparatorIntClear(unsigned long ulBase, unsigned long ulComp) -{ - // - // Check the arguments. - // - ASSERT(ulBase == COMP_BASE); - ASSERT(ulComp < 3); - - // - // Clear the interrupt. - // - HWREG(ulBase + COMP_O_MIS) = 1 << ulComp; -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/comp.h b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/comp.h deleted file mode 100644 index 9349982c4..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/comp.h +++ /dev/null @@ -1,120 +0,0 @@ -//***************************************************************************** -// -// comp.h - Prototypes for the analog comparator driver. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __COMP_H__ -#define __COMP_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to ComparatorConfigure() as the ulConfig -// parameter. For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of -// the values may be selected and ORed together will values from the other -// groups. -// -//***************************************************************************** -#define COMP_TRIG_NONE 0x00000000 // No ADC trigger -#define COMP_TRIG_HIGH 0x00000880 // Trigger when high -#define COMP_TRIG_LOW 0x00000800 // Trigger when low -#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge -#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge -#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges -#define COMP_INT_HIGH 0x00000010 // Interrupt when high -#define COMP_INT_LOW 0x00000000 // Interrupt when low -#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge -#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge -#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges -#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin -#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin -#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference -#define COMP_OUTPUT_NONE 0x00000000 // No comparator output -#define COMP_OUTPUT_NORMAL 0x00000100 // Comparator output normal -#define COMP_OUTPUT_INVERT 0x00000102 // Comparator output inverted - -//***************************************************************************** -// -// Values that can be passed to ComparatorSetRef() as the ulRef parameter. -// -//***************************************************************************** -#define COMP_REF_OFF 0x00000000 // Turn off the internal reference -#define COMP_REF_0V 0x00000300 // Internal reference of 0V -#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V -#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V -#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V -#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V -#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V -#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V -#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V -#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V -#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V -#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V -#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V -#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V -#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V -#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V -#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V -#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V -#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V -#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V -#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V -#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V -#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V -#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V -#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V -#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V -#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V -#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V -#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp, - unsigned long ulConfig); -extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef); -extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp); -extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp, - void (*pfnHandler)(void)); -extern void ComparatorIntUnregister(unsigned long ulBase, - unsigned long ulComp); -extern void ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp); -extern void ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp); -extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp, - tBoolean bMasked); -extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp); - -#ifdef __cplusplus -} -#endif - -#endif // __COMP_H__ diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/cpu.h b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/cpu.h deleted file mode 100644 index 688c52223..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/cpu.h +++ /dev/null @@ -1,40 +0,0 @@ -//***************************************************************************** -// -// cpu.h - Prototypes for the CPU instruction wrapper functions. -// -// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __CPU_H__ -#define __CPU_H__ - -//***************************************************************************** -// -// Prototypes. -// -//***************************************************************************** -extern void CPUcpsid(void); -extern void CPUcpsie(void); -extern void CPUwfi(void); - -#endif // __CPU_H__ diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/debug.h b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/debug.h deleted file mode 100644 index e46e2a772..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/debug.h +++ /dev/null @@ -1,56 +0,0 @@ -//***************************************************************************** -// -// debug.h - Macros for assisting debug of the driver library. -// -// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __DEBUG_H__ -#define __DEBUG_H__ - -//***************************************************************************** -// -// Prototype for the function that is called when an invalid argument is passed -// to an API. This is only used when doing a DEBUG build. -// -//***************************************************************************** -extern void __error__(char *pcFilename, unsigned long ulLine); - -//***************************************************************************** -// -// The ASSERT macro, which does the actual assertion checking. Typically, this -// will be for procedure arguments. -// -//***************************************************************************** -#ifdef DEBUG -#define ASSERT(expr) { \ - if(!(expr)) \ - { \ - __error__(__FILE__, __LINE__); \ - } \ - } -#else -#define ASSERT(expr) -#endif - -#endif // __DEBUG_H__ diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/driverlib.r79 b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/driverlib.r79 deleted file mode 100644 index 074f82f12..000000000 Binary files a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/driverlib.r79 and /dev/null differ diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/flash.c b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/flash.c deleted file mode 100644 index ab7335f42..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/flash.c +++ /dev/null @@ -1,668 +0,0 @@ -//***************************************************************************** -// -// flash.c - Driver for programming the on-chip flash. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup flash_api -//! @{ -// -//***************************************************************************** - -#include "../hw_flash.h" -#include "../hw_ints.h" -#include "../hw_memmap.h" -#include "../hw_sysctl.h" -#include "../hw_types.h" -#include "debug.h" -#include "flash.h" -#include "interrupt.h" - -//***************************************************************************** -// -//! Gets the number of processor clocks per micro-second. -//! -//! This function returns the number of clocks per micro-second, as presently -//! known by the flash controller. -//! -//! \return Returns the number of processor clocks per micro-second. -// -//***************************************************************************** -#if defined(GROUP_usecget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -FlashUsecGet(void) -{ - // - // Return the number of clocks per micro-second. - // - return(HWREG(FLASH_USECRL) + 1); -} -#endif - -//***************************************************************************** -// -//! Sets the number of processor clocks per micro-second. -//! -//! \param ulClocks is the number of processor clocks per micro-second. -//! -//! This function is used to tell the flash controller the number of processor -//! clocks per micro-second. This value must be programmed correctly or the -//! flash most likely will not program correctly; it has no affect on reading -//! flash. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_usecset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -FlashUsecSet(unsigned long ulClocks) -{ - // - // Set the number of clocks per micro-second. - // - HWREG(FLASH_USECRL) = ulClocks - 1; -} -#endif - -//***************************************************************************** -// -//! Erases a block of flash. -//! -//! \param ulAddress is the start address of the flash block to be erased. -//! -//! This function will erase a 1 kB block of the on-chip flash. After erasing, -//! the block will be filled with 0xFF bytes. Read-only and execute-only -//! blocks cannot be erased. -//! -//! This function will not return until the block has been erased. -//! -//! \return Returns 0 on success, or -1 if an invalid block address was -//! specified or the block is write-protected. -// -//***************************************************************************** -#if defined(GROUP_erase) || defined(BUILD_ALL) || defined(DOXYGEN) -long -FlashErase(unsigned long ulAddress) -{ - // - // Check the arguments. - // - ASSERT(!(ulAddress & (FLASH_ERASE_SIZE - 1))); - - // - // Clear the flash access interrupt. - // - HWREG(FLASH_FCMISC) = FLASH_FCMISC_ACCESS; - - // - // Erase the block. - // - HWREG(FLASH_FMA) = ulAddress; - HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_ERASE; - - // - // Wait until the word has been programmed. - // - while(HWREG(FLASH_FMC) & FLASH_FMC_ERASE) - { - } - - // - // Return an error if an access violation occurred. - // - if(HWREG(FLASH_FCRIS) & FLASH_FCRIS_ACCESS) - { - return(-1); - } - - // - // Success. - // - return(0); -} -#endif - -//***************************************************************************** -// -//! Programs flash. -//! -//! \param pulData is a pointer to the data to be programmed. -//! \param ulAddress is the starting address in flash to be programmed. Must -//! be a multiple of four. -//! \param ulCount is the number of bytes to be programmed. Must be a multiple -//! of four. -//! -//! This function will program a sequence of words into the on-chip flash. -//! Programming each location consists of the result of an AND operation -//! of the new data and the existing data; in other words bits that contain -//! 1 can remain 1 or be changed to 0, but bits that are 0 cannot be changed -//! to 1. Therefore, a word can be programmed multiple times as long as these -//! rules are followed; if a program operation attempts to change a 0 bit to -//! a 1 bit, that bit will not have its value changed. -//! -//! Since the flash is programmed one word at a time, the starting address and -//! byte count must both be multiples of four. It is up to the caller to -//! verify the programmed contents, if such verification is required. -//! -//! This function will not return until the data has been programmed. -//! -//! \return Returns 0 on success, or -1 if a programming error is encountered. -// -//***************************************************************************** -#if defined(GROUP_program) || defined(BUILD_ALL) || defined(DOXYGEN) -long -FlashProgram(unsigned long *pulData, unsigned long ulAddress, - unsigned long ulCount) -{ - // - // Check the arguments. - // - ASSERT(!(ulAddress & 3)); - ASSERT(!(ulCount & 3)); - - // - // Clear the flash access interrupt. - // - HWREG(FLASH_FCMISC) = FLASH_FCMISC_ACCESS; - - // - // Loop over the words to be programmed. - // - while(ulCount) - { - // - // Program the next word. - // - HWREG(FLASH_FMA) = ulAddress; - HWREG(FLASH_FMD) = *pulData; - HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_WRITE; - - // - // Wait until the word has been programmed. - // - while(HWREG(FLASH_FMC) & FLASH_FMC_WRITE) - { - } - - // - // Increment to the next word. - // - pulData++; - ulAddress += 4; - ulCount -= 4; - } - - // - // Return an error if an access violation occurred. - // - if(HWREG(FLASH_FCRIS) & FLASH_FCRIS_ACCESS) - { - return(-1); - } - - // - // Success. - // - return(0); -} -#endif - -//***************************************************************************** -// -//! Gets the protection setting for a block of flash. -//! -//! \param ulAddress is the start address of the flash block to be queried. -//! -//! This function will get the current protection for the specified 2 kB block -//! of flash. Each block can be read/write, read-only, or execute-only. -//! Read/write blocks can be read, executed, erased, and programmed. Read-only -//! blocks can be read and executed. Execute-only blocks can only be executed; -//! processor and debugger data reads are not allowed. -//! -//! \return Returns the protection setting for this block. See -//! FlashProtectSet() for possible values. -// -//***************************************************************************** -#if defined(GROUP_protectget) || defined(BUILD_ALL) || defined(DOXYGEN) -tFlashProtection -FlashProtectGet(unsigned long ulAddress) -{ - unsigned long ulFMPRE, ulFMPPE; - - // - // Check the argument. - // - ASSERT(!(ulAddress & (FLASH_PROTECT_SIZE - 1))); - - // - // Read the flash protection register and get the bits that apply to the - // specified block. - // - ulFMPRE = HWREG(FLASH_FMPRE); - ulFMPPE = HWREG(FLASH_FMPPE); - switch((((ulFMPRE >> (ulAddress / FLASH_PROTECT_SIZE)) & - FLASH_FMP_BLOCK_0) << 1) | - ((ulFMPPE >> (ulAddress / FLASH_PROTECT_SIZE)) & FLASH_FMP_BLOCK_0)) - { - // - // This block is marked as execute only (i.e. it can not be erased or - // programmed, and the only reads allowed are via the instruction fecth - // interface). - // - case 0: - case 1: - { - return(FlashExecuteOnly); - } - - // - // This block is marked as read only (i.e. it can not be erased or - // programmed). - // - case 2: - { - return(FlashReadOnly); - } - - // - // This block is read/write; it can be read, erased, and programmed. - // - case 3: - default: - { - return(FlashReadWrite); - } - } -} -#endif - -//***************************************************************************** -// -//! Sets the protection setting for a block of flash. -//! -//! \param ulAddress is the start address of the flash block to be protected. -//! \param eProtect is the protection to be applied to the block. Can be one -//! of \b FlashReadWrite, \b FlashReadOnly, or \b FlashExecuteOnly. -//! -//! This function will set the protection for the specified 2 kB block of -//! flash. Blocks which are read/write can be made read-only or execute-only. -//! Blocks which are read-only can be made execute-only. Blocks which are -//! execute-only cannot have their protection modified. Attempts to make the -//! block protection less stringent (i.e. read-only to read/write) will result -//! in a failure (and be prevented by the hardware). -//! -//! Changes to the flash protection are maintained only until the next reset. -//! This allows the application to be executed in the desired flash protection -//! environment to check for inappropriate flash access (via the flash -//! interrupt). To make the flash protection permanent, use the -//! FlashProtectSave() function. -//! -//! \return Returns 0 on success, or -1 if an invalid address or an invalid -//! protection was specified. -// -//***************************************************************************** -#if defined(GROUP_protectset) || defined(BUILD_ALL) || defined(DOXYGEN) -long -FlashProtectSet(unsigned long ulAddress, tFlashProtection eProtect) -{ - unsigned long ulProtectRE, ulProtectPE; - - // - // Check the argument. - // - ASSERT(!(ulAddress & (FLASH_PROTECT_SIZE - 1))); - ASSERT((eProtect == FlashReadWrite) || (eProtect == FlashReadOnly) || - (eProtect == FlashExecuteOnly)); - - // - // Convert the address into a block number. - // - ulAddress /= FLASH_PROTECT_SIZE; - - // - // Get the current protection. - // - ulProtectRE = HWREG(FLASH_FMPRE); - ulProtectPE = HWREG(FLASH_FMPPE); - - // - // Set the protection based on the requested proection. - // - switch(eProtect) - { - // - // Make this block execute only. - // - case FlashExecuteOnly: - { - // - // Turn off the read and program bits for this block. - // - ulProtectRE &= ~(FLASH_FMP_BLOCK_0 << ulAddress); - ulProtectPE &= ~(FLASH_FMP_BLOCK_0 << ulAddress); - - // - // We're done handling this protection. - // - break; - } - - // - // Make this block read only. - // - case FlashReadOnly: - { - // - // The block can not be made read only if it is execute only. - // - if(((ulProtectRE >> ulAddress) & FLASH_FMP_BLOCK_0) != - FLASH_FMP_BLOCK_0) - { - return(-1); - } - - // - // Make this block read only. - // - ulProtectPE &= ~(FLASH_FMP_BLOCK_0 << ulAddress); - - // - // We're done handling this protection. - // - break; - } - - // - // Make this block read/write. - // - case FlashReadWrite: - default: - { - // - // The block can not be made read/write if it is not already - // read/write. - // - if((((ulProtectRE >> ulAddress) & FLASH_FMP_BLOCK_0) != - FLASH_FMP_BLOCK_0) || - (((ulProtectPE >> ulAddress) & FLASH_FMP_BLOCK_0) != - FLASH_FMP_BLOCK_0)) - { - return(-1); - } - - // - // The block is already read/write, so there is nothing to do. - // - return(0); - } - } - - // - // Set the new protection. - // - HWREG(FLASH_FMPRE) = ulProtectRE; - HWREG(FLASH_FMPPE) = ulProtectPE; - - // - // Success. - // - return(0); -} -#endif - -//***************************************************************************** -// -//! Saves the flash protection settings. -//! -//! This function will make the currently programmed flash protection settings -//! permanent. This is a non-reversible operation; a chip reset or power cycle -//! will not change the flash protection. -//! -//! This function will not return until the protection has been saved. -//! -//! \return Returns 0 on success, or -1 if a hardware error is encountered. -// -//***************************************************************************** -#if defined(GROUP_protectsave) || defined(BUILD_ALL) || defined(DOXYGEN) -long -FlashProtectSave(void) -{ - // - // Tell the flash controller to write the flash read protection register. - // - HWREG(FLASH_FMA) = 0; - HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT; - - // - // Wait until the write has completed. - // - while(HWREG(FLASH_FMC) & FLASH_FMC_COMT) - { - } - - // - // Tell the flash controller to write the flash program protection - // register. - // - HWREG(FLASH_FMA) = 1; - HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT; - - // - // Wait until the write has completed. - // - while(HWREG(FLASH_FMC) & FLASH_FMC_COMT) - { - } - - // - // Success. - // - return(0); -} -#endif - -//***************************************************************************** -// -//! Registers an interrupt handler for the flash interrupt. -//! -//! \param pfnHandler is a pointer to the function to be called when the flash -//! interrupt occurs. -//! -//! This sets the handler to be called when the flash interrupt occurs. The -//! flash controller can generate an interrupt when an invalid flash access -//! occurs, such as trying to program or erase a read-only block, or trying to -//! read from an execute-only block. It can also generate an interrupt when a -//! program or erase operation has completed. The interrupt will be -//! automatically enabled when the handler is registered. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -FlashIntRegister(void (*pfnHandler)(void)) -{ - // - // Register the interrupt handler, returning an error if an error occurs. - // - IntRegister(INT_FLASH, pfnHandler); - - // - // Enable the flash interrupt. - // - IntEnable(INT_FLASH); -} -#endif - -//***************************************************************************** -// -//! Unregisters the interrupt handler for the flash interrupt. -//! -//! This function will clear the handler to be called when the flash interrupt -//! occurs. This will also mask off the interrupt in the interrupt controller -//! so that the interrupt handler is no longer called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -FlashIntUnregister(void) -{ - // - // Disable the interrupt. - // - IntDisable(INT_FLASH); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_FLASH); -} -#endif - -//***************************************************************************** -// -//! Enables individual flash controller interrupt sources. -//! -//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. -//! Can be any of the \b FLASH_FCIM_PROGRAM or \b FLASH_FCIM_ACCESS values. -//! -//! Enables the indicated flash controller interrupt sources. Only the sources -//! that are enabled can be reflected to the processor interrupt; disabled -//! sources have no effect on the processor. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -FlashIntEnable(unsigned long ulIntFlags) -{ - // - // Enable the specified interrupts. - // - HWREG(FLASH_FCIM) |= ulIntFlags; -} -#endif - -//***************************************************************************** -// -//! Disables individual flash controller interrupt sources. -//! -//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. -//! Can be any of the \b FLASH_FCIM_PROGRAM or \b FLASH_FCIM_ACCESS values. -//! -//! Disables the indicated flash controller interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -FlashIntDisable(unsigned long ulIntFlags) -{ - // - // Disable the specified interrupts. - // - HWREG(FLASH_FCIM) &= ~(ulIntFlags); -} -#endif - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \param bMasked is false if the raw interrupt status is required and true if -//! the masked interrupt status is required. -//! -//! This returns the interrupt status for the flash controller. Either the raw -//! interrupt status or the status of interrupts that are allowed to reflect to -//! the processor can be returned. -//! -//! \return The current interrupt status, enumerated as a bit field of -//! \b FLASH_FCMISC_PROGRAM and \b FLASH_FCMISC_ACCESS. -// -//***************************************************************************** -#if defined(GROUP_intgetstatus) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -FlashIntGetStatus(tBoolean bMasked) -{ - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(FLASH_FCMISC)); - } - else - { - return(HWREG(FLASH_FCRIS)); - } -} -#endif - -//***************************************************************************** -// -//! Clears flash controller interrupt sources. -//! -//! \param ulIntFlags is the bit mask of the interrupt sources to be cleared. -//! Can be any of the \b FLASH_FCMISC_PROGRAM or \b FLASH_FCMISC_ACCESS -//! values. -//! -//! The specified flash controller interrupt sources are cleared, so that they -//! no longer assert. This must be done in the interrupt handler to keep it -//! from being called again immediately upon exit. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) -void -FlashIntClear(unsigned long ulIntFlags) -{ - // - // Clear the flash interrupt. - // - HWREG(FLASH_FCMISC) = ulIntFlags; -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/flash.h b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/flash.h deleted file mode 100644 index 9c41dda4f..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/flash.h +++ /dev/null @@ -1,75 +0,0 @@ -//***************************************************************************** -// -// flash.h - Prototypes for the flash driver. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __FLASH_H__ -#define __FLASH_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to FlashProtectSet(), and returned by -// FlashProtectGet(). -// -//***************************************************************************** -typedef enum -{ - FlashReadWrite, // Flash can be read and written - FlashReadOnly, // Flash can only be read - FlashExecuteOnly // Flash can only be executed -} -tFlashProtection; - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern unsigned long FlashUsecGet(void); -extern void FlashUsecSet(unsigned long ulClocks); -extern long FlashErase(unsigned long ulAddress); -extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress, - unsigned long ulCount); -extern tFlashProtection FlashProtectGet(unsigned long ulAddress); -extern long FlashProtectSet(unsigned long ulAddress, - tFlashProtection eProtect); -extern long FlashProtectSave(void); -extern void FlashIntRegister(void (*pfnHandler)(void)); -extern void FlashIntUnregister(void); -extern void FlashIntEnable(unsigned long ulIntFlags); -extern void FlashIntDisable(unsigned long ulIntFlags); -extern unsigned long FlashIntGetStatus(tBoolean bMasked); -extern void FlashIntClear(unsigned long ulIntFlags); - -#ifdef __cplusplus -} -#endif - -#endif // __FLASH_H__ diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/gpio.c b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/gpio.c deleted file mode 100644 index a49602e9b..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/gpio.c +++ /dev/null @@ -1,1103 +0,0 @@ -//***************************************************************************** -// -// gpio.c - API for GPIO ports -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup gpio_api -//! @{ -// -//***************************************************************************** - -#include "../hw_gpio.h" -#include "../hw_ints.h" -#include "../hw_memmap.h" -#include "../hw_types.h" -#include "debug.h" -#include "gpio.h" -#include "interrupt.h" - -//***************************************************************************** -// -//! \internal -//! Get GPIO interrupt number. -//! -//! \param ulPort base address of the selected GPIO port -//! -//! Given a GPIO base address, returns the corresponding interrupt number. -//! -//! \return Returns a GPIO interrupt number, or -1 if \e ulPort is invalid. -// -//***************************************************************************** -#if defined(GROUP_getintnumber) || defined(BUILD_ALL) -long -GPIOGetIntNumber(unsigned long ulPort) -{ - unsigned int ulInt; - - // - // Determine the GPIO interrupt number for the given module. - // - switch(ulPort) - { - case GPIO_PORTA_BASE: - { - ulInt = INT_GPIOA; - break; - } - - case GPIO_PORTB_BASE: - { - ulInt = INT_GPIOB; - break; - } - - case GPIO_PORTC_BASE: - { - ulInt = INT_GPIOC; - break; - } - - case GPIO_PORTD_BASE: - { - ulInt = INT_GPIOD; - break; - } - - case GPIO_PORTE_BASE: - { - ulInt = INT_GPIOE; - break; - } - - default: - { - return(-1); - } - } - - // - // Return GPIO interrupt number. - // - return(ulInt); -} -#else -extern long GPIOGetIntNumber(unsigned long ulPort); -#endif - -//***************************************************************************** -// -//! Sets the direction and mode of the specified pins of the selected -//! GPIO port. -//! -//! \param ulPort base address of the selected GPIO port -//! \param ucPins bit-packed representation of the specified pins -//! \param ulPinIO pin direction and/or mode -//! -//! This function will set the specified pins on the selected GPIO port -//! as either an input or output under software control, or it will set the -//! pin to be under hardware control. -//! -//! The parameter \e ulPinIO is an enumerated data type that can be one of -//! the following values: -//! -//! - \b GPIO_DIR_MODE_IN -//! - \b GPIO_DIR_MODE_OUT -//! - \b GPIO_DIR_MODE_HW -//! -//! where \b GPIO_DIR_MODE_IN specifies that the pin will be programmed as -//! a software controlled input, \b GPIO_DIR_MODE_OUT specifies that the pin -//! will be programmed as a software controlled output, and -//! \b GPIO_DIR_MODE_HW specifies that the pin will be placed under -//! hardware control. -//! -//! The pins are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_dirmodeset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulPinIO) -{ - // - // Check the arguments. - // - ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || - (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || - (ulPort == GPIO_PORTE_BASE)); - ASSERT((ulPinIO == GPIO_DIR_MODE_IN) || (ulPinIO == GPIO_DIR_MODE_OUT) || - (ulPinIO == GPIO_DIR_MODE_HW)); - - // - // Set the pin direction and mode. - // - HWREG(ulPort + GPIO_O_DIR) = ((ulPinIO & 1) ? - (HWREG(ulPort + GPIO_O_DIR) | ucPins) : - (HWREG(ulPort + GPIO_O_DIR) & ~(ucPins))); - HWREG(ulPort + GPIO_O_AFSEL) = ((ulPinIO & 2) ? - (HWREG(ulPort + GPIO_O_AFSEL) | ucPins) : - (HWREG(ulPort + GPIO_O_AFSEL) & - ~(ucPins))); -} -#endif - -//***************************************************************************** -// -//! Gets the direction and mode of a specified pin of the selected -//! GPIO port. -//! -//! \param ulPort base address of the selected GPIO port -//! \param ucPin pin number of the specified pin, relative to the selected -//! GPIO port. -//! -//! This function gets the direction and control mode for a specified pin on -//! the selected GPIO port. The pin can be configured as either an input or -//! output under software control, or it can be under hardware control. The -//! type of control and direction are returned as an enumerated data type. -//! -//! \return Returns one of the enumerated data types described for -//! GPIODirModeSet(). -// -//***************************************************************************** -#if defined(GROUP_dirmodeget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -GPIODirModeGet(unsigned long ulPort, unsigned char ucPin) -{ - unsigned long ulDir, ulAFSEL; - - // - // Check the arguments. - // - ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || - (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || - (ulPort == GPIO_PORTE_BASE)); - ASSERT(ucPin < 8); - - // - // Convert from a pin number to a bit position. - // - ucPin = 1 << ucPin; - - // - // Return the pin direction and mode. - // - ulDir = HWREG(ulPort + GPIO_O_DIR); - ulAFSEL = HWREG(ulPort + GPIO_O_AFSEL); - return(((ulDir & ucPin) ? 1 : 0) | ((ulAFSEL & ucPin) ? 2 : 0)); -} -#endif - -//***************************************************************************** -// -//! Sets the interrupt type for the specified pins of the selected GPIO -//! port. -//! -//! \param ulPort base address of the selected GPIO port -//! \param ucPins bit-packed representation of the specified pins -//! \param ulIntType specifies the type of interrupt trigger mechanism -//! -//! This function sets up the various interrupt trigger mechanisms for the -//! specified pins on the selected GPIO port. -//! -//! The parameter \e ulIntType is an enumerated data type that can be one of -//! the following values: -//! -//! - \b GPIO_FALLING_EDGE -//! - \b GPIO_RISING_EDGE -//! - \b GPIO_BOTH_EDGES -//! - \b GPIO_LOW_LEVEL -//! - \b GPIO_HIGH_LEVEL -//! -//! where the different values describe the interrupt detection mechanism -//! (edge or level) and the particular triggering event (falling, rising, -//! or both edges for edge detect, low or high for level detect). -//! -//! The pins are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. -//! -//! \note In order to avoid any spurious interrupts, the user must -//! ensure that the GPIO inputs remain stable for the duration of -//! this function. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_inttypeset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulIntType) -{ - // - // Check the arguments. - // - ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || - (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || - (ulPort == GPIO_PORTE_BASE)); - ASSERT((ulIntType == GPIO_FALLING_EDGE) || - (ulIntType == GPIO_RISING_EDGE) || - (ulIntType == GPIO_BOTH_EDGES) || - (ulIntType == GPIO_LOW_LEVEL) || - (ulIntType == GPIO_HIGH_LEVEL)); - - // - // Set the pin interrupt type. - // - HWREG(ulPort + GPIO_O_IBE) = ((ulIntType & 1) ? - (HWREG(ulPort + GPIO_O_IBE) | ucPins) : - (HWREG(ulPort + GPIO_O_IBE) & ~(ucPins))); - HWREG(ulPort + GPIO_O_IS) = ((ulIntType & 2) ? - (HWREG(ulPort + GPIO_O_IS) | ucPins) : - (HWREG(ulPort + GPIO_O_IS) & ~(ucPins))); - HWREG(ulPort + GPIO_O_IEV) = ((ulIntType & 4) ? - (HWREG(ulPort + GPIO_O_IEV) | ucPins) : - (HWREG(ulPort + GPIO_O_IEV) & ~(ucPins))); -} -#endif - -//***************************************************************************** -// -//! Gets the interrupt type for the specified pin of the selected GPIO -//! port. -//! -//! \param ulPort base address of the selected GPIO port -//! \param ucPin pin number of the specified pin, relative to the selected -//! GPIO port. -//! -//! This function gets the interrupt type for a specified pin on the selected -//! GPIO port. The pin can be configured as a falling edge, rising edge, or -//! both edge detected interrupt, or it can be configured as a low level or -//! high level detected interrupt. The type of interrupt detection mechanism -//! is returned as an enumerated data type. -//! -//! \return Returns one of the enumerated data types described for -//! GPIOIntTypeSet(). -// -//***************************************************************************** -#if defined(GROUP_inttypeget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin) -{ - unsigned long ulIBE, ulIS, ulIEV; - - // - // Check the arguments. - // - ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || - (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || - (ulPort == GPIO_PORTE_BASE)); - ASSERT(ucPin < 8); - - // - // Convert from a pin number to a bit position. - // - ucPin = 1 << ucPin; - - // - // Return the pin interrupt type. - // - ulIBE = HWREG(ulPort + GPIO_O_IBE); - ulIS = HWREG(ulPort + GPIO_O_IS); - ulIEV = HWREG(ulPort + GPIO_O_IEV); - return(((ulIBE & ucPin) ? 1 : 0) | ((ulIS & ucPin) ? 2 : 0) | - ((ulIEV & ucPin) ? 4 : 0)); -} -#endif - -//***************************************************************************** -// -//! Sets the pad configuration for the specified pins of the selected GPIO -//! port. -//! -//! \param ulPort is the base address of the GPIO port. -//! \param ucPins bit-packed representation of the specified pins. -//! \param ulStrength specifies the output drive strength. -//! \param ulPinType specifies the pin type. -//! -//! This function sets the drive strength and type for the specified pins -//! on the selected GPIO port. For pins configured as input ports, the -//! pad is configured as requested, but the only real effect on the input -//! is the configuration of the pull-up or pull-down termination. -//! -//! The parameter \e ulStrength can be one of the following values: -//! -//! - \b GPIO_STRENGTH_2MA -//! - \b GPIO_STRENGTH_4MA -//! - \b GPIO_STRENGTH_8MA -//! - \b GPIO_STRENGTH_8MA_SC -//! -//! where \b GPIO_STRENGTH_xMA specifies either 2, 4, or 8 mA output drive -//! strength, and \b GPIO_OUT_STRENGTH_8MA_SC specifies 8 mA output drive with -//! slew control. -//! -//! The parameter \e ulPinType can be one of the following values: -//! -//! - \b GPIO_PIN_TYPE_STD -//! - \b GPIO_PIN_TYPE_STD_WPU -//! - \b GPIO_PIN_TYPE_STD_WPD -//! - \b GPIO_PIN_TYPE_OD -//! - \b GPIO_PIN_TYPE_OD_WPU -//! - \b GPIO_PIN_TYPE_OD_WPD -//! - \b GPIO_PIN_TYPE_ANALOG -//! -//! where \b GPIO_PIN_TYPE_STD* specifies a push-pull pin, \b GPIO_PIN_TYPE_OD* -//! specifies an open-drain pin, \b *_WPU specifies a weak pull-up, \b *_WPD -//! specifies a weak pull-down, and \b GPIO_PIN_TYPE_ANALOG specifies an -//! analog input (for the comparators). -//! -//! The pins are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_padconfigset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulStrength, unsigned long ulPinType) -{ - // - // Check the arguments. - // - ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || - (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || - (ulPort == GPIO_PORTE_BASE)); - ASSERT((ulStrength == GPIO_STRENGTH_2MA) || - (ulStrength == GPIO_STRENGTH_4MA) || - (ulStrength == GPIO_STRENGTH_8MA) || - (ulStrength == GPIO_STRENGTH_8MA_SC)); - ASSERT((ulPinType == GPIO_PIN_TYPE_STD) || - (ulPinType == GPIO_PIN_TYPE_STD_WPU) || - (ulPinType == GPIO_PIN_TYPE_STD_WPD) || - (ulPinType == GPIO_PIN_TYPE_OD) || - (ulPinType == GPIO_PIN_TYPE_OD_WPU) || - (ulPinType == GPIO_PIN_TYPE_OD_WPD) || - (ulPinType == GPIO_PIN_TYPE_ANALOG)) - - // - // Set the output drive strength. - // - HWREG(ulPort + GPIO_O_DR2R) = ((ulStrength & 1) ? - (HWREG(ulPort + GPIO_O_DR2R) | ucPins) : - (HWREG(ulPort + GPIO_O_DR2R) & ~(ucPins))); - HWREG(ulPort + GPIO_O_DR4R) = ((ulStrength & 2) ? - (HWREG(ulPort + GPIO_O_DR4R) | ucPins) : - (HWREG(ulPort + GPIO_O_DR4R) & ~(ucPins))); - HWREG(ulPort + GPIO_O_DR8R) = ((ulStrength & 4) ? - (HWREG(ulPort + GPIO_O_DR8R) | ucPins) : - (HWREG(ulPort + GPIO_O_DR8R) & ~(ucPins))); - HWREG(ulPort + GPIO_O_SLR) = ((ulStrength & 8) ? - (HWREG(ulPort + GPIO_O_SLR) | ucPins) : - (HWREG(ulPort + GPIO_O_SLR) & ~(ucPins))); - - // - // Set the pin type. - // - HWREG(ulPort + GPIO_O_ODR) = ((ulPinType & 1) ? - (HWREG(ulPort + GPIO_O_ODR) | ucPins) : - (HWREG(ulPort + GPIO_O_ODR) & ~(ucPins))); - HWREG(ulPort + GPIO_O_PUR) = ((ulPinType & 2) ? - (HWREG(ulPort + GPIO_O_PUR) | ucPins) : - (HWREG(ulPort + GPIO_O_PUR) & ~(ucPins))); - HWREG(ulPort + GPIO_O_PDR) = ((ulPinType & 4) ? - (HWREG(ulPort + GPIO_O_PDR) | ucPins) : - (HWREG(ulPort + GPIO_O_PDR) & ~(ucPins))); - HWREG(ulPort + GPIO_O_DEN) = ((ulPinType & 8) ? - (HWREG(ulPort + GPIO_O_DEN) | ucPins) : - (HWREG(ulPort + GPIO_O_DEN) & ~(ucPins))); -} -#endif - -//***************************************************************************** -// -//! Gets the pad configuration for the specified pin of the selected GPIO -//! port. -//! -//! \param ulPort base address of the selected GPIO port -//! \param ucPin pin number of the specified pin, relative to the selected -//! GPIO port. -//! \param pulStrength pointer to storage for the output drive strength -//! \param pulPinType pointer to storage for the output drive type -//! -//! This function gets the pad configuration for a specified pin on the -//! selected GPIO port. The values returned in \e eStrength and \e eOutType -//! correspond to the values used in GPIOPadConfigSet(). This function also -//! works for pins configured as input pins; however, the only meaningful -//! data returned is whether the pin is terminated with a pull-up or -//! down resistor. -//! -//! \return None -// -//***************************************************************************** -#if defined(GROUP_padconfigget) || defined(BUILD_ALL) || defined(DOXYGEN) -void -GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin, - unsigned long *pulStrength, unsigned long *pulPinType) -{ - unsigned long ulTemp1, ulTemp2, ulTemp3, ulTemp4; - - // - // Check the arguments. - // - ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || - (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || - (ulPort == GPIO_PORTE_BASE)); - ASSERT(ucPin < 8); - - // - // Convert from a pin number to a bit position. - // - ucPin = (1 << ucPin); - - // - // Get the drive strength for this pin. - // - ulTemp1 = HWREG(ulPort + GPIO_O_DR2R); - ulTemp2 = HWREG(ulPort + GPIO_O_DR4R); - ulTemp3 = HWREG(ulPort + GPIO_O_DR8R); - ulTemp4 = HWREG(ulPort + GPIO_O_SLR); - *pulStrength = (((ulTemp1 & ucPin) ? 1 : 0) | ((ulTemp2 & ucPin) ? 2 : 0) | - ((ulTemp3 & ucPin) ? 4 : 0) | ((ulTemp4 & ucPin) ? 8 : 0)); - - // - // Get the pin type. - // - ulTemp1 = HWREG(ulPort + GPIO_O_ODR); - ulTemp2 = HWREG(ulPort + GPIO_O_PUR); - ulTemp3 = HWREG(ulPort + GPIO_O_PDR); - ulTemp4 = HWREG(ulPort + GPIO_O_DEN); - *pulPinType = (((ulTemp1 & ucPin) ? 1 : 0) | ((ulTemp2 & ucPin) ? 2 : 0) | - ((ulTemp3 & ucPin) ? 4 : 0) | ((ulTemp4 & ucPin) ? 8 : 0)); -} -#endif - -//***************************************************************************** -// -//! Enables interrupts for the specified pins of the selected GPIO port. -//! -//! \param ulPort base address of the selected GPIO port -//! \param ucPins bit-packed representation of the specified pins -//! -//! Unmasks the interrupt for the specified pins. -//! -//! The pins are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_pinintenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins) -{ - // - // Check the arguments. - // - ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || - (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || - (ulPort == GPIO_PORTE_BASE)); - - // - // Enable the interrupts. - // - HWREG(ulPort + GPIO_O_IM) |= ucPins; -} -#endif - -//***************************************************************************** -// -//! Disables interrupts for the specified pins of the selected GPIO port. -//! -//! \param ulPort base address of the selected GPIO port -//! \param ucPins bit-packed representation of the specified pins -//! -//! Masks the interrupt for the specified pins. -//! -//! The pins are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_pinintdisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins) -{ - // - // Check the arguments. - // - ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || - (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || - (ulPort == GPIO_PORTE_BASE)); - - // - // Disable the interrupts. - // - HWREG(ulPort + GPIO_O_IM) &= ~(ucPins); -} -#endif - -//***************************************************************************** -// -//! Gets interrupt status for all the pins of the selected GPIO port. -//! -//! \param ulPort base address of the selected GPIO port -//! \param bMasked specifies whether masked or raw interrupt -//! status is returned -//! -//! If \e bMasked is set as \b true, then the masked interrupt status is -//! returned; otherwise, the raw interrupt status will be returned. -//! -//! \return Returns a bit-packed byte, where each bit that is set identifies -//! an active masked or raw interrupt, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. Bits -//! 31:8 should be ignored. -// -//***************************************************************************** -#if defined(GROUP_pinintstatus) || defined(BUILD_ALL) || defined(DOXYGEN) -long -GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked) -{ - // - // Check the arguments. - // - ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || - (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || - (ulPort == GPIO_PORTE_BASE)); - - // - // Return the interrupt status. - // - if(bMasked) - { - return(HWREG(ulPort + GPIO_O_MIS)); - } - else - { - return(HWREG(ulPort + GPIO_O_RIS)); - } -} -#endif - -//***************************************************************************** -// -//! Clears the interrupt for the specified pins of the selected GPIO port. -//! -//! \param ulPort base address of the selected GPIO port -//! \param ucPins bit-packed representation of the specified pins -//! -//! Clears the interrupt for the specified pins. -//! -//! The pins are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_pinintclear) || defined(BUILD_ALL) || defined(DOXYGEN) -void -GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins) -{ - // - // Check the arguments. - // - ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || - (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || - (ulPort == GPIO_PORTE_BASE)); - - // - // Clear the interrupts. - // - HWREG(ulPort + GPIO_O_ICR) = ucPins; -} -#endif - -//***************************************************************************** -// -//! Registers an interrupt handler for the selected GPIO port. -//! -//! \param ulPort base address of the selected GPIO port -//! \param pfIntHandler pointer to the GPIO port interrupt handling function -//! -//! This function will ensure that the interrupt handler specified by \e -//! pfIntHandler is called when an interrupt is detected from the selected -//! GPIO port. This function will also enable the corresponding GPIO -//! interrupt in the interrupt controller; individual pin interrupts and -//! interrupt sources must be enabled with GPIOPinIntEnable(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_portintregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -GPIOPortIntRegister(unsigned long ulPort, void (*pfIntHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || - (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || - (ulPort == GPIO_PORTE_BASE)); - - // - // Get the interrupt number associated with the specified GPIO. - // - ulPort = GPIOGetIntNumber(ulPort); - - // - // Register the interrupt handler. - // - IntRegister(ulPort, pfIntHandler); - - // - // Enable the GPIO interrupt. - // - IntEnable(ulPort); -} -#endif - -//***************************************************************************** -// -//! Removes an interrupt handler for the selected GPIO port. -//! -//! \param ulPort base address of the selected GPIO port -//! -//! This function will unregister the interrupt handler for the specified -//! GPIO port. This function will also disable the corresponding -//! GPIO port interrupt in the interrupt controller; individual GPIO interrupts -//! and interrupt sources must be disabled with GPIOPinIntDisable(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_portintunregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -GPIOPortIntUnregister(unsigned long ulPort) -{ - // - // Check the arguments. - // - ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || - (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || - (ulPort == GPIO_PORTE_BASE)); - - // - // Get the interrupt number associated with the specified GPIO. - // - ulPort = GPIOGetIntNumber(ulPort); - - // - // Disable the GPIO interrupt. - // - IntDisable(ulPort); - - // - // Unregister the interrupt handler. - // - IntUnregister(ulPort); -} -#endif - -//***************************************************************************** -// -//! Reads the values present at the specified pins of the selected GPIO port. -//! -//! \param ulPort base address of the selected GPIO port -//! \param ucPins bit-packed representation of the specified pins -//! -//! The values at the specified pins are read, as specified by \e ucPins. -//! Values are returned for both input and output pins, and the value -//! for pins that are not specified by \e ucPins are set to 0. -//! -//! The pins are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. -//! -//! \return Returns a bit-packed byte providing the state of the specified -//! pin, where bit 0 of the byte represents GPIO port pin 0, bit 1 represents -//! GPIO port pin 1, etc. Any bit that is not specified by \e ucPins -//! is returned as a 0. Bits 31:8 should be ignored. -// -//***************************************************************************** -#if defined(GROUP_pinread) || defined(BUILD_ALL) || defined(DOXYGEN) -long -GPIOPinRead(unsigned long ulPort, unsigned char ucPins) -{ - // - // Check the arguments. - // - ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || - (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || - (ulPort == GPIO_PORTE_BASE)); - - // - // Return the pin value(s). - // - return(HWREG(ulPort + (GPIO_O_DATA + (ucPins << 2)))); -} -#endif - -//***************************************************************************** -// -//! Writes a value at the specified pins of the selected GPIO port. -//! -//! \param ulPort base address of the selected GPIO port -//! \param ucPins bit-packed representation of the specified pins -//! \param ucVal value to write to the specified pins -//! -//! Writes the corresponding bit values to the output pins specified -//! by \e ucPins. Writing to a pin configured as an input pin has no -//! effect. -//! -//! The pins are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, etc. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_pinwrite) || defined(BUILD_ALL) || defined(DOXYGEN) -void -GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, unsigned char ucVal) -{ - // - // Check the arguments. - // - ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || - (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || - (ulPort == GPIO_PORTE_BASE)); - - // - // Write the pins. - // - HWREG(ulPort + (GPIO_O_DATA + (ucPins << 2))) = ucVal; -} -#endif - -//***************************************************************************** -// -//! Configures pin(s) for use as an analog comparator input. -//! -//! \param ulPort base address of the selected GPIO port -//! \param ucPins bit-packed representation of the specified pins -//! -//! The analog comparator input pins must be properly configured for the analog -//! comparator to function correctly. This function provides the proper -//! configuration for those pins. -//! -//! \note This cannot be used to turn any pin into an analog comparator input; -//! it only configures an analog comparator pin for proper operation. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_pintypecomparator) || defined(BUILD_ALL) || defined(DOXYGEN) -void -GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins) -{ - // - // Check the arguments. - // - ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || - (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || - (ulPort == GPIO_PORTE_BASE)); - - // - // Make the pin(s) be inputs. - // - GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_IN); - - // - // Set the pad(s) for analog operation. - // - GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_ANALOG); -} -#endif - -//***************************************************************************** -// -//! Configures pin(s) for use by the I2C peripheral. -//! -//! \param ulPort base address of the selected GPIO port -//! \param ucPins bit-packed representation of the specified pins -//! -//! The I2C pins must be properly configured for the I2C peripheral to function -//! correctly. This function provides the proper configuration for those pins. -//! -//! \note This cannot be used to turn any pin into an I2C pin; it only -//! configures an I2C pin for proper operation. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_pintypei2c) || defined(BUILD_ALL) || defined(DOXYGEN) -void -GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins) -{ - // - // Check the arguments. - // - ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || - (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || - (ulPort == GPIO_PORTE_BASE)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for open-drain operation with a weak pull-up. - // - GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD_WPU); -} -#endif - -//***************************************************************************** -// -//! Configures pin(s) for use by the PWM peripheral. -//! -//! \param ulPort base address of the selected GPIO port -//! \param ucPins bit-packed representation of the specified pins -//! -//! The PWM pins must be properly configured for the PWM peripheral to function -//! correctly. This function provides a typical configuration for those pins; -//! other configurations may work as well depending upon the board setup (for -//! example, using the on-chip pull-ups). -//! -//! \note This cannot be used to turn any pin into a PWM pin; it only -//! configures a PWM pin for proper operation. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_pintypepwm) || defined(BUILD_ALL) || defined(DOXYGEN) -void -GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins) -{ - // - // Check the arguments. - // - ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || - (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || - (ulPort == GPIO_PORTE_BASE)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); -} -#endif - -//***************************************************************************** -// -//! Configures pin(s) for use by the QEI peripheral. -//! -//! \param ulPort base address of the selected GPIO port -//! \param ucPins bit-packed representation of the specified pins -//! -//! The QEI pins must be properly configured for the QEI peripheral to function -//! correctly. This function provides a typical configuration for those pins; -//! other configurations may work as well depending upon the board setup (for -//! example, not using the on-chip pull-ups). -//! -//! \note This cannot be used to turn any pin into a QEI pin; it only -//! configures a QEI pin for proper operation. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_pintypeqei) || defined(BUILD_ALL) || defined(DOXYGEN) -void -GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins) -{ - // - // Check the arguments. - // - ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || - (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || - (ulPort == GPIO_PORTE_BASE)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation with a weak pull-up. - // - GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU); -} -#endif - -//***************************************************************************** -// -//! Configures pin(s) for use by the SSI peripheral. -//! -//! \param ulPort base address of the selected GPIO port -//! \param ucPins bit-packed representation of the specified pins -//! -//! The SSI pins must be properly configured for the SSI peripheral to function -//! correctly. This function provides a typical configuration for those pins; -//! other configurations may work as well depending upon the board setup (for -//! example, using the on-chip pull-ups). -//! -//! \note This cannot be used to turn any pin into a SSI pin; it only -//! configures a SSI pin for proper operation. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_pintypessi) || defined(BUILD_ALL) || defined(DOXYGEN) -void -GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins) -{ - // - // Check the arguments. - // - ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || - (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || - (ulPort == GPIO_PORTE_BASE)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); -} -#endif - -//***************************************************************************** -// -//! Configures pin(s) for use by the Timer peripheral. -//! -//! \param ulPort base address of the selected GPIO port -//! \param ucPins bit-packed representation of the specified pins -//! -//! The CCP pins must be properly configured for the timer peripheral to -//! function correctly. This function provides a typical configuration for -//! those pins; other configurations may work as well depending upon the board -//! setup (for example, using the on-chip pull-ups). -//! -//! \note This cannot be used to turn any pin into a timer pin; it only -//! configures a timer pin for proper operation. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_pintypetimer) || defined(BUILD_ALL) || defined(DOXYGEN) -void -GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins) -{ - // - // Check the arguments. - // - ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || - (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || - (ulPort == GPIO_PORTE_BASE)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); -} -#endif - -//***************************************************************************** -// -//! Configures pin(s) for use by the UART peripheral. -//! -//! \param ulPort base address of the selected GPIO port -//! \param ucPins bit-packed representation of the specified pins -//! -//! The UART pins must be properly configured for the UART peripheral to -//! function correctly. This function provides a typical configuration for -//! those pins; other configurations may work as well depending upon the board -//! setup (for example, using the on-chip pull-ups). -//! -//! \note This cannot be used to turn any pin into a UART pin; it only -//! configures a UART pin for proper operation. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_pintypeuart) || defined(BUILD_ALL) || defined(DOXYGEN) -void -GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins) -{ - // - // Check the arguments. - // - ASSERT((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTB_BASE) || - (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTD_BASE) || - (ulPort == GPIO_PORTE_BASE)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/gpio.h b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/gpio.h deleted file mode 100644 index 88d657223..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/gpio.h +++ /dev/null @@ -1,137 +0,0 @@ -//***************************************************************************** -// -// gpio.h - Defines and Macros for GPIO API. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __GPIO_H__ -#define __GPIO_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following values define the bit field for the ucPins argument to several -// of the APIs. -// -//***************************************************************************** -#define GPIO_PIN_0 0x00000001 // GPIO pin 0 -#define GPIO_PIN_1 0x00000002 // GPIO pin 1 -#define GPIO_PIN_2 0x00000004 // GPIO pin 2 -#define GPIO_PIN_3 0x00000008 // GPIO pin 3 -#define GPIO_PIN_4 0x00000010 // GPIO pin 4 -#define GPIO_PIN_5 0x00000020 // GPIO pin 5 -#define GPIO_PIN_6 0x00000040 // GPIO pin 6 -#define GPIO_PIN_7 0x00000080 // GPIO pin 7 - -//***************************************************************************** -// -// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and -// returned from GPIODirModeGet. -// -//***************************************************************************** -#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input -#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output -#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function - -//***************************************************************************** -// -// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and -// returned from GPIOIntTypeGet. -// -//***************************************************************************** -#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge -#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge -#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges -#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level -#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level - -//***************************************************************************** -// -// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter, -// and returned by GPIOPadConfigGet in the *pulStrength parameter. -// -//***************************************************************************** -#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength -#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength -#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength -#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control - -//***************************************************************************** -// -// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter, -// and returned by GPIOPadConfigGet in the *pulPadType parameter. -// -//***************************************************************************** -#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull -#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up -#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down -#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain -#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up -#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down -#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulPinIO); -extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin); -extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulIntType); -extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin); -extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulStrength, - unsigned long ulPadType); -extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin, - unsigned long *pulStrength, - unsigned long *pulPadType); -extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins); -extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked); -extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPortIntRegister(unsigned long ulPort, - void (*pfIntHandler)(void)); -extern void GPIOPortIntUnregister(unsigned long ulPort); -extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, - unsigned char ucVal); -extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins); - -#ifdef __cplusplus -} -#endif - -#endif // __GPIO_H__ diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_adc.h b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_adc.h deleted file mode 100644 index 022b9e963..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_adc.h +++ /dev/null @@ -1,343 +0,0 @@ -//***************************************************************************** -// -// hw_adc.h - Macros used when accessing the ADC hardware. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_ADC_H__ -#define __HW_ADC_H__ - -//***************************************************************************** -// -// The following define the offsets of the ADC registers. -// -//***************************************************************************** -#define ADC_O_ACTSS 0x00000000 // Active sample register -#define ADC_O_RIS 0x00000004 // Raw interrupt status register -#define ADC_O_IM 0x00000008 // Interrupt mask register -#define ADC_O_ISC 0x0000000C // Interrupt status/clear register -#define ADC_O_OSTAT 0x00000010 // Overflow status register -#define ADC_O_EMUX 0x00000014 // Event multiplexer select reg. -#define ADC_O_USTAT 0x00000018 // Underflow status register -#define ADC_O_SSPRI 0x00000020 // Channel priority register -#define ADC_O_PSSI 0x00000028 // Processor sample initiate reg. -#define ADC_O_SAC 0x00000030 // Sample Averaging Control reg. -#define ADC_O_SSMUX0 0x00000040 // Multiplexer select 0 register -#define ADC_O_SSCTL0 0x00000044 // Sample sequence control 0 reg. -#define ADC_O_SSFIFO0 0x00000048 // Result FIFO 0 register -#define ADC_O_SSFSTAT0 0x0000004C // FIFO 0 status register -#define ADC_O_SSMUX1 0x00000060 // Multiplexer select 1 register -#define ADC_O_SSCTL1 0x00000064 // Sample sequence control 1 reg. -#define ADC_O_SSFIFO1 0x00000068 // Result FIFO 1 register -#define ADC_O_SSFSTAT1 0x0000006C // FIFO 1 status register -#define ADC_O_SSMUX2 0x00000080 // Multiplexer select 2 register -#define ADC_O_SSCTL2 0x00000084 // Sample sequence control 2 reg. -#define ADC_O_SSFIFO2 0x00000088 // Result FIFO 2 register -#define ADC_O_SSFSTAT2 0x0000008C // FIFO 2 status register -#define ADC_O_SSMUX3 0x000000A0 // Multiplexer select 3 register -#define ADC_O_SSCTL3 0x000000A4 // Sample sequence control 3 reg. -#define ADC_O_SSFIFO3 0x000000A8 // Result FIFO 3 register -#define ADC_O_SSFSTAT3 0x000000AC // FIFO 3 status register -#define ADC_O_TMLB 0x00000100 // Test mode loopback register - -//***************************************************************************** -// -// The following define the offsets of the ADC sequence registers. -// -//***************************************************************************** -#define ADC_O_SEQ 0x00000040 // Offset to the first sequence -#define ADC_O_SEQ_STEP 0x00000020 // Increment to the next sequence -#define ADC_O_X_SSMUX 0x00000000 // Multiplexer select register -#define ADC_O_X_SSCTL 0x00000004 // Sample sequence control register -#define ADC_O_X_SSFIFO 0x00000008 // Result FIFO register -#define ADC_O_X_SSFSTAT 0x0000000C // FIFO status register - -//***************************************************************************** -// -// The following define the bit fields in the ADC_ACTSS register. -// -//***************************************************************************** -#define ADC_ACTSS_ASEN3 0x00000008 // Sample sequence 3 enable -#define ADC_ACTSS_ASEN2 0x00000004 // Sample sequence 2 enable -#define ADC_ACTSS_ASEN1 0x00000002 // Sample sequence 1 enable -#define ADC_ACTSS_ASEN0 0x00000001 // Sample sequence 0 enable - -//***************************************************************************** -// -// The following define the bit fields in the ADC_RIS register. -// -//***************************************************************************** -#define ADC_RIS_INR3 0x00000008 // Sample sequence 3 interrupt -#define ADC_RIS_INR2 0x00000004 // Sample sequence 2 interrupt -#define ADC_RIS_INR1 0x00000002 // Sample sequence 1 interrupt -#define ADC_RIS_INR0 0x00000001 // Sample sequence 0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the ADC_IM register. -// -//***************************************************************************** -#define ADC_IM_MASK3 0x00000008 // Sample sequence 3 mask -#define ADC_IM_MASK2 0x00000004 // Sample sequence 2 mask -#define ADC_IM_MASK1 0x00000002 // Sample sequence 1 mask -#define ADC_IM_MASK0 0x00000001 // Sample sequence 0 mask - -//***************************************************************************** -// -// The following define the bit fields in the ADC_ISC register. -// -//***************************************************************************** -#define ADC_ISC_IN3 0x00000008 // Sample sequence 3 interrupt -#define ADC_ISC_IN2 0x00000004 // Sample sequence 2 interrupt -#define ADC_ISC_IN1 0x00000002 // Sample sequence 1 interrupt -#define ADC_ISC_IN0 0x00000001 // Sample sequence 0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the ADC_OSTAT register. -// -//***************************************************************************** -#define ADC_OSTAT_OV3 0x00000008 // Sample sequence 3 overflow -#define ADC_OSTAT_OV2 0x00000004 // Sample sequence 2 overflow -#define ADC_OSTAT_OV1 0x00000002 // Sample sequence 1 overflow -#define ADC_OSTAT_OV0 0x00000001 // Sample sequence 0 overflow - -//***************************************************************************** -// -// The following define the bit fields in the ADC_EMUX register. -// -//***************************************************************************** -#define ADC_EMUX_EM3_MASK 0x0000F000 // Event mux 3 mask -#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor event -#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog comparator 0 event -#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog comparator 1 event -#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog comparator 2 event -#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External event -#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer event -#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0 event -#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1 event -#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2 event -#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always event -#define ADC_EMUX_EM2_MASK 0x00000F00 // Event mux 2 mask -#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor event -#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog comparator 0 event -#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog comparator 1 event -#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog comparator 2 event -#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External event -#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer event -#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0 event -#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1 event -#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2 event -#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always event -#define ADC_EMUX_EM1_MASK 0x000000F0 // Event mux 1 mask -#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor event -#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog comparator 0 event -#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog comparator 1 event -#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog comparator 2 event -#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External event -#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer event -#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0 event -#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1 event -#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2 event -#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always event -#define ADC_EMUX_EM0_MASK 0x0000000F // Event mux 0 mask -#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor event -#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog comparator 0 event -#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog comparator 1 event -#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog comparator 2 event -#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External event -#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer event -#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0 event -#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1 event -#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2 event -#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always event -#define ADC_EMUX_EM0_SHIFT 0 // The shift for the first event -#define ADC_EMUX_EM1_SHIFT 4 // The shift for the second event -#define ADC_EMUX_EM2_SHIFT 8 // The shift for the third event -#define ADC_EMUX_EM3_SHIFT 12 // The shift for the fourth event - -//***************************************************************************** -// -// The following define the bit fields in the ADC_USTAT register. -// -//***************************************************************************** -#define ADC_USTAT_UV3 0x00000008 // Sample sequence 3 underflow -#define ADC_USTAT_UV2 0x00000004 // Sample sequence 2 underflow -#define ADC_USTAT_UV1 0x00000002 // Sample sequence 1 underflow -#define ADC_USTAT_UV0 0x00000001 // Sample sequence 0 underflow - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSPRI register. -// -//***************************************************************************** -#define ADC_SSPRI_SS3_MASK 0x00003000 // Sequencer 3 priority mask -#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority -#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority -#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority -#define ADC_SSPRI_SS2_MASK 0x00000300 // Sequencer 2 priority mask -#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority -#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority -#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority -#define ADC_SSPRI_SS1_MASK 0x00000030 // Sequencer 1 priority mask -#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority -#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority -#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority -#define ADC_SSPRI_SS0_MASK 0x00000003 // Sequencer 0 priority mask -#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority -#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority -#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority - -//***************************************************************************** -// -// The following define the bit fields in the ADC_PSSI register. -// -//***************************************************************************** -#define ADC_PSSI_SS3 0x00000008 // Trigger sample sequencer 3 -#define ADC_PSSI_SS2 0x00000004 // Trigger sample sequencer 2 -#define ADC_PSSI_SS1 0x00000002 // Trigger sample sequencer 1 -#define ADC_PSSI_SS0 0x00000001 // Trigger sample sequencer 0 - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SAC register. -// -//***************************************************************************** -#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling -#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling -#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling -#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling -#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling -#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling -#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSMUX0, ADC_SSMUX1, -// ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present in all -// registers. -// -//***************************************************************************** -#define ADC_SSMUX_MUX7_MASK 0x70000000 // 8th mux select mask -#define ADC_SSMUX_MUX6_MASK 0x07000000 // 7th mux select mask -#define ADC_SSMUX_MUX5_MASK 0x00700000 // 6th mux select mask -#define ADC_SSMUX_MUX4_MASK 0x00070000 // 5th mux select mask -#define ADC_SSMUX_MUX3_MASK 0x00007000 // 4th mux select mask -#define ADC_SSMUX_MUX2_MASK 0x00000700 // 3rd mux select mask -#define ADC_SSMUX_MUX1_MASK 0x00000070 // 2nd mux select mask -#define ADC_SSMUX_MUX0_MASK 0x00000007 // 1st mux select mask -#define ADC_SSMUX_MUX7_SHIFT 28 -#define ADC_SSMUX_MUX6_SHIFT 24 -#define ADC_SSMUX_MUX5_SHIFT 20 -#define ADC_SSMUX_MUX4_SHIFT 16 -#define ADC_SSMUX_MUX3_SHIFT 12 -#define ADC_SSMUX_MUX2_SHIFT 8 -#define ADC_SSMUX_MUX1_SHIFT 4 -#define ADC_SSMUX_MUX0_SHIFT 0 - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSCTL0, ADC_SSCTL1, -// ADC_SSCTL2, and ADC_SSCTL3 registers. Not all fields are present in all -// registers. -// -//***************************************************************************** -#define ADC_SSCTL_TS7 0x80000000 // 8th temperature sensor select -#define ADC_SSCTL_IE7 0x40000000 // 8th interrupt enable -#define ADC_SSCTL_END7 0x20000000 // 8th sequence end select -#define ADC_SSCTL_D7 0x10000000 // 8th differential select -#define ADC_SSCTL_TS6 0x08000000 // 7th temperature sensor select -#define ADC_SSCTL_IE6 0x04000000 // 7th interrupt enable -#define ADC_SSCTL_END6 0x02000000 // 7th sequence end select -#define ADC_SSCTL_D6 0x01000000 // 7th differential select -#define ADC_SSCTL_TS5 0x00800000 // 6th temperature sensor select -#define ADC_SSCTL_IE5 0x00400000 // 6th interrupt enable -#define ADC_SSCTL_END5 0x00200000 // 6th sequence end select -#define ADC_SSCTL_D5 0x00100000 // 6th differential select -#define ADC_SSCTL_TS4 0x00080000 // 5th temperature sensor select -#define ADC_SSCTL_IE4 0x00040000 // 5th interrupt enable -#define ADC_SSCTL_END4 0x00020000 // 5th sequence end select -#define ADC_SSCTL_D4 0x00010000 // 5th differential select -#define ADC_SSCTL_TS3 0x00008000 // 4th temperature sensor select -#define ADC_SSCTL_IE3 0x00004000 // 4th interrupt enable -#define ADC_SSCTL_END3 0x00002000 // 4th sequence end select -#define ADC_SSCTL_D3 0x00001000 // 4th differential select -#define ADC_SSCTL_TS2 0x00000800 // 3rd temperature sensor select -#define ADC_SSCTL_IE2 0x00000400 // 3rd interrupt enable -#define ADC_SSCTL_END2 0x00000200 // 3rd sequence end select -#define ADC_SSCTL_D2 0x00000100 // 3rd differential select -#define ADC_SSCTL_TS1 0x00000080 // 2nd temperature sensor select -#define ADC_SSCTL_IE1 0x00000040 // 2nd interrupt enable -#define ADC_SSCTL_END1 0x00000020 // 2nd sequence end select -#define ADC_SSCTL_D1 0x00000010 // 2nd differential select -#define ADC_SSCTL_TS0 0x00000008 // 1st temperature sensor select -#define ADC_SSCTL_IE0 0x00000004 // 1st interrupt enable -#define ADC_SSCTL_END0 0x00000002 // 1st sequence end select -#define ADC_SSCTL_D0 0x00000001 // 1st differential select - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSFIFO0, ADC_SSFIFO1, -// ADC_SSFIFO2, and ADC_SSFIFO3 registers. -// -//***************************************************************************** -#define ADC_SSFIFO_DATA_MASK 0x000003FF // Sample data -#define ADC_SSFIFO_DATA_SHIFT 0 - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSFSTAT0, ADC_SSFSTAT1, -// ADC_SSFSTAT2, and ADC_SSFSTAT3 registers. -// -//***************************************************************************** -#define ADC_SSFSTAT_FULL 0x00001000 // FIFO is full -#define ADC_SSFSTAT_EMPTY 0x00000100 // FIFO is empty -#define ADC_SSFSTAT_HPTR 0x000000F0 // FIFO head pointer -#define ADC_SSFSTAT_TPTR 0x0000000F // FIFO tail pointer - -//***************************************************************************** -// -// The following define the bit fields in the ADC_TMLB register. -// -//***************************************************************************** -#define ADC_TMLB_LB 0x00000001 // Loopback control signals - -//***************************************************************************** -// -// The following define the bit fields in the loopback ADC data. -// -//***************************************************************************** -#define ADC_LB_CNT_MASK 0x000003C0 // Sample counter mask -#define ADC_LB_CONT 0x00000020 // Continuation sample -#define ADC_LB_DIFF 0x00000010 // Differential sample -#define ADC_LB_TS 0x00000008 // Temperature sensor sample -#define ADC_LB_MUX_MASK 0x00000007 // Input channel number mask -#define ADC_LB_CNT_SHIFT 6 // Sample counter shift -#define ADC_LB_MUX_SHIFT 0 // Input channel number shift - -#endif // __HW_ADC_H__ diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_comp.h b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_comp.h deleted file mode 100644 index 991b7a083..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_comp.h +++ /dev/null @@ -1,118 +0,0 @@ -//***************************************************************************** -// -// hw_comp.h - Macros used when accessing the comparator hardware. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_COMP_H__ -#define __HW_COMP_H__ - -//***************************************************************************** -// -// The following define the offsets of the comparator registers. -// -//***************************************************************************** -#define COMP_O_MIS 0x00000000 // Interrupt status register -#define COMP_O_RIS 0x00000004 // Raw interrupt status register -#define COMP_O_INTEN 0x00000008 // Interrupt enable register -#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg. -#define COMP_O_ACSTAT0 0x00000020 // Comp0 status register -#define COMP_O_ACCTL0 0x00000024 // Comp0 control register -#define COMP_O_ACSTAT1 0x00000040 // Comp1 status register -#define COMP_O_ACCTL1 0x00000044 // Comp1 control register -#define COMP_O_ACSTAT2 0x00000060 // Comp2 status register -#define COMP_O_ACCTL2 0x00000064 // Comp2 control register - -//***************************************************************************** -// -// The following define the bit fields in the COMP_MIS, COMP_RIS, and -// COMP_INTEN registers. -// -//***************************************************************************** -#define COMP_INT_2 0x00000004 // Comp2 interrupt -#define COMP_INT_1 0x00000002 // Comp1 interrupt -#define COMP_INT_0 0x00000001 // Comp0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the COMP_REFCTL register. -// -//***************************************************************************** -#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable -#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range -#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask -#define COMP_REFCTL_VREF_SHIFT 0 - -//***************************************************************************** -// -// The following define the bit fields in the COMP_ACSTAT0, COMP_ACSTAT1, and -// COMP_ACSTAT2 registers. -// -//***************************************************************************** -#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value - -//***************************************************************************** -// -// The following define the bit fields in the COMP_ACCTL0, COMP_ACCTL1, and -// COMP_ACCTL2 registers. -// -//***************************************************************************** -#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable -#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask -#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin -#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin -#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference -#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved -#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable -#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select -#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask -#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense -#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge -#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge -#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges -#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select -#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask -#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense -#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge -#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge -#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges -#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert - -//***************************************************************************** -// -// The following define the reset values for the comparator registers. -// -//***************************************************************************** -#define COMP_RV_MIS 0x00000000 // Interrupt status register -#define COMP_RV_RIS 0x00000000 // Raw interrupt status register -#define COMP_RV_INTEN 0x00000000 // Interrupt enable register -#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg. -#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register -#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register -#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register -#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register -#define COMP_RV_ACSTAT2 0x00000000 // Comp2 status register -#define COMP_RV_ACCTL2 0x00000000 // Comp2 control register - -#endif // __HW_COMP_H__ diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_flash.h b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_flash.h deleted file mode 100644 index 53128b436..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_flash.h +++ /dev/null @@ -1,139 +0,0 @@ -//***************************************************************************** -// -// hw_flash.h - Macros used when accessing the flash controller. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_FLASH_H__ -#define __HW_FLASH_H__ - -//***************************************************************************** -// -// The following define the offsets of the FLASH registers. -// -//***************************************************************************** -#define FLASH_FMA 0x400FD000 // Memory address register -#define FLASH_FMD 0x400FD004 // Memory data register -#define FLASH_FMC 0x400FD008 // Memory control register -#define FLASH_FCRIS 0x400FD00c // Raw interrupt status register -#define FLASH_FCIM 0x400FD010 // Interrupt mask register -#define FLASH_FCMISC 0x400FD014 // Interrupt status register -#define FLASH_FMPRE 0x400FE130 // FLASH read protect register -#define FLASH_FMPPE 0x400FE134 // FLASH program protect register -#define FLASH_USECRL 0x400FE140 // uSec reload register - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FMC register. -// -//***************************************************************************** -#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask -#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key -#define FLASH_FMC_COMT 0x00000008 // Commit user register -#define FLASH_FMC_MERASE 0x00000004 // Mass erase FLASH -#define FLASH_FMC_ERASE 0x00000002 // Erase FLASH page -#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FCRIS register. -// -//***************************************************************************** -#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status -#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FCIM register. -// -//***************************************************************************** -#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask -#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FMIS register. -// -//***************************************************************************** -#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status -#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FMPRE and FLASH_FMPPE -// registers. -// -//***************************************************************************** -#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31 -#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30 -#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29 -#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28 -#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27 -#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26 -#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25 -#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24 -#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23 -#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22 -#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21 -#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20 -#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19 -#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18 -#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17 -#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16 -#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15 -#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14 -#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13 -#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12 -#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11 -#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10 -#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9 -#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8 -#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7 -#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6 -#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5 -#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4 -#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3 -#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2 -#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1 -#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0 - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_USECRL register. -// -//***************************************************************************** -#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec -#define FLASH_USECRL_SHIFT 0 - -//***************************************************************************** -// -// The erase size is the size of the FLASH block that is erased by an erase -// operation, and the protect size is the size of the FLASH block that is -// protected by each protection register. -// -//***************************************************************************** -#define FLASH_ERASE_SIZE 0x00000400 -#define FLASH_PROTECT_SIZE 0x00000800 - -#endif // __HW_FLASH_H__ diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_gpio.h b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_gpio.h deleted file mode 100644 index bf25d3f5a..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_gpio.h +++ /dev/null @@ -1,103 +0,0 @@ -//***************************************************************************** -// -// hw_gpio.h - Defines and Macros for GPIO hardware. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_GPIO_H__ -#define __HW_GPIO_H__ - -//***************************************************************************** -// -// GPIO Register Offsets. -// -//***************************************************************************** -#define GPIO_O_DATA 0x00000000 // Data register. -#define GPIO_O_DIR 0x00000400 // Data direction register. -#define GPIO_O_IS 0x00000404 // Interrupt sense register. -#define GPIO_O_IBE 0x00000408 // Interrupt both edges register. -#define GPIO_O_IEV 0x0000040C // Intterupt event register. -#define GPIO_O_IM 0x00000410 // Interrupt mask register. -#define GPIO_O_RIS 0x00000414 // Raw interrupt status register. -#define GPIO_O_MIS 0x00000418 // Masked interrupt status reg. -#define GPIO_O_ICR 0x0000041C // Interrupt clear register. -#define GPIO_O_AFSEL 0x00000420 // Mode control select register. -#define GPIO_O_DR2R 0x00000500 // 2ma drive select register. -#define GPIO_O_DR4R 0x00000504 // 4ma drive select register. -#define GPIO_O_DR8R 0x00000508 // 8ma drive select register. -#define GPIO_O_ODR 0x0000050C // Open drain select register. -#define GPIO_O_PUR 0x00000510 // Pull up select register. -#define GPIO_O_PDR 0x00000514 // Pull down select register. -#define GPIO_O_SLR 0x00000518 // Slew rate control enable reg. -#define GPIO_O_DEN 0x0000051C // Digital input enable register. -#define GPIO_O_PeriphID4 0x00000FD0 // -#define GPIO_O_PeriphID5 0x00000FD4 // -#define GPIO_O_PeriphID6 0x00000FD8 // -#define GPIO_O_PeriphID7 0x00000FDC // -#define GPIO_O_PeriphID0 0x00000FE0 // -#define GPIO_O_PeriphID1 0x00000FE4 // -#define GPIO_O_PeriphID2 0x00000FE8 // -#define GPIO_O_PeriphID3 0x00000FEC // -#define GPIO_O_PCellID0 0x00000FF0 // -#define GPIO_O_PCellID1 0x00000FF4 // -#define GPIO_O_PCellID2 0x00000FF8 // -#define GPIO_O_PCellID3 0x00000FFC // - -//***************************************************************************** -// -// GPIO Register reset values. -// -//***************************************************************************** -#define GPIO_RV_DATA 0x00000000 // Data register reset value. -#define GPIO_RV_DIR 0x00000000 // Data direction reg RV. -#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV. -#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV. -#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV. -#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV. -#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV. -#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV. -#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV. -#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV. -#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV. -#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV. -#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV. -#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV. -#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV. -#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV. -#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV. -#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV. -#define GPIO_RV_PeriphID4 0x00000000 // -#define GPIO_RV_PeriphID5 0x00000000 // -#define GPIO_RV_PeriphID6 0x00000000 // -#define GPIO_RV_PeriphID7 0x00000000 // -#define GPIO_RV_PeriphID0 0x00000061 // -#define GPIO_RV_PeriphID1 0x00000010 // -#define GPIO_RV_PeriphID2 0x00000004 // -#define GPIO_RV_PeriphID3 0x00000000 // -#define GPIO_RV_PCellID0 0x0000000D // -#define GPIO_RV_PCellID1 0x000000F0 // -#define GPIO_RV_PCellID2 0x00000005 // -#define GPIO_RV_PCellID3 0x000000B1 // - -#endif // __HW_GPIO_H__ diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_i2c.h b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_i2c.h deleted file mode 100644 index 2c9f46dab..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_i2c.h +++ /dev/null @@ -1,197 +0,0 @@ -//***************************************************************************** -// -// hw_i2c.h - Macros used when accessing the I2C master and slave hardware. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_I2C_H__ -#define __HW_I2C_H__ - -//***************************************************************************** -// -// The following defines the offset between the I2C master and slave registers. -// -//***************************************************************************** -#define I2C_O_SLAVE 0x00000800 // Offset from master to slave - -//***************************************************************************** -// -// The following define the offsets of the I2C master registers. -// -//***************************************************************************** -#define I2C_MASTER_O_SA 0x00000000 // Slave address register -#define I2C_MASTER_O_CS 0x00000004 // Control and Status register -#define I2C_MASTER_O_DR 0x00000008 // Data register -#define I2C_MASTER_O_TPR 0x0000000C // Timer period register -#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register -#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register -#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg -#define I2C_MASTER_O_MICR 0x0000001c // Interrupt clear register -#define I2C_MASTER_O_CR 0x00000020 // Configuration register - -//***************************************************************************** -// -// The following define the offsets of the I2C slave registers. -// -//***************************************************************************** -#define I2C_SLAVE_O_OAR 0x00000000 // Own address register -#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register -#define I2C_SLAVE_O_DR 0x00000008 // Data register -#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register -#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register -#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg -#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register - -//***************************************************************************** -// -// The followng define the bit fields in the I2C master slave address register. -// -//***************************************************************************** -#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address -#define I2C_MASTER_SA_RS 0x00000001 // Receive/send -#define I2C_MASTER_SA_SA_SHIFT 1 - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Control and Status -// register. -// -//***************************************************************************** -#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde -#define I2C_MASTER_CS_STOP 0x00000004 // Stop -#define I2C_MASTER_CS_START 0x00000002 // Start -#define I2C_MASTER_CS_RUN 0x00000001 // Run -#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy -#define I2C_MASTER_CS_IDLE 0x00000020 // Idle -#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration -#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged -#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged -#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred -#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data -#define I2C_MASTER_CS_ERR_MASK 0x0000001C - -//***************************************************************************** -// -// The following define values used in determining the contents of the I2C -// Master Timer Period register. -// -//***************************************************************************** -#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period -#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period -#define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP) -#define I2C_SCL_STANDARD 100000 // SCL standard frequency -#define I2C_SCL_FAST 400000 // SCL fast frequency - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Interrupt Mask -// register. -// -//***************************************************************************** -#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Raw Interrupt Status -// register. -// -//***************************************************************************** -#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Masked Interrupt -// Status register. -// -//***************************************************************************** -#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Interrupt Clear -// register. -// -//***************************************************************************** -#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Configuration -// register. -// -//***************************************************************************** -#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable -#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable -#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Own Address register. -// -//***************************************************************************** -#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Control/Status -// register. -// -//***************************************************************************** -#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device -#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received -#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Interrupt Mask -// register. -// -//***************************************************************************** -#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Raw Interrupt Status -// register. -// -//***************************************************************************** -#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Masked Interrupt -// Status register. -// -//***************************************************************************** -#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Interrupt Clear -// register. -// -//***************************************************************************** -#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear - -#endif // __HW_I2C_H__ diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_ints.h b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_ints.h deleted file mode 100644 index 2204a2c07..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_ints.h +++ /dev/null @@ -1,97 +0,0 @@ -//***************************************************************************** -// -// hw_ints.h - Macros that define the interrupt assignment on Stellaris. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_INTS_H__ -#define __HW_INTS_H__ - -//***************************************************************************** -// -// The following define the fault assignments. -// -//***************************************************************************** -#define FAULT_NMI 2 // NMI fault -#define FAULT_HARD 3 // Hard fault -#define FAULT_MPU 4 // MPU fault -#define FAULT_BUS 5 // Bus fault -#define FAULT_USAGE 6 // Usage fault -#define FAULT_SVCALL 11 // SVCall -#define FAULT_DEBUG 12 // Debug monitor -#define FAULT_PENDSV 14 // PendSV -#define FAULT_SYSTICK 15 // System Tick - -//***************************************************************************** -// -// The following define the interrupt assignments. -// -//***************************************************************************** -#define INT_GPIOA 16 // GPIO Port A -#define INT_GPIOB 17 // GPIO Port B -#define INT_GPIOC 18 // GPIO Port C -#define INT_GPIOD 19 // GPIO Port D -#define INT_GPIOE 20 // GPIO Port E -#define INT_UART0 21 // UART0 Rx and Tx -#define INT_UART1 22 // UART1 Rx and Tx -#define INT_SSI 23 // SSI Rx and Tx -#define INT_I2C 24 // I2C Master and Slave -#define INT_PWM_FAULT 25 // PWM Fault -#define INT_PWM0 26 // PWM Generator 0 -#define INT_PWM1 27 // PWM Generator 1 -#define INT_PWM2 28 // PWM Generator 2 -#define INT_QEI 29 // Quadrature Encoder -#define INT_ADC0 30 // ADC Sequence 0 -#define INT_ADC1 31 // ADC Sequence 1 -#define INT_ADC2 32 // ADC Sequence 2 -#define INT_ADC3 33 // ADC Sequence 3 -#define INT_WATCHDOG 34 // Watchdog timer -#define INT_TIMER0A 35 // Timer 0 subtimer A -#define INT_TIMER0B 36 // Timer 0 subtimer B -#define INT_TIMER1A 37 // Timer 1 subtimer A -#define INT_TIMER1B 38 // Timer 1 subtimer B -#define INT_TIMER2A 39 // Timer 2 subtimer A -#define INT_TIMER2B 40 // Timer 2 subtimer B -#define INT_COMP0 41 // Analog Comparator 0 -#define INT_COMP1 42 // Analog Comparator 1 -#define INT_COMP2 43 // Analog Comparator 2 -#define INT_SYSCTL 44 // System Control (PLL, OSC, BO) -#define INT_FLASH 45 // FLASH Control - -//***************************************************************************** -// -// The total number of interrupts. -// -//***************************************************************************** -#define NUM_INTERRUPTS 46 - -//***************************************************************************** -// -// The total number of priority levels. -// -//***************************************************************************** -#define NUM_PRIORITY 8 -#define NUM_PRIORITY_BITS 3 - -#endif // __HW_INTS_H__ diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_memmap.h b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_memmap.h deleted file mode 100644 index 2b11f3513..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_memmap.h +++ /dev/null @@ -1,64 +0,0 @@ -//***************************************************************************** -// -// hw_memmap.h - Macros defining the memory map of Stellaris. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_MEMMAP_H__ -#define __HW_MEMMAP_H__ - -//***************************************************************************** -// -// The following define the base address of the memories and peripherals. -// -//***************************************************************************** -#define FLASH_BASE 0x00000000 // FLASH memory -#define SRAM_BASE 0x20000000 // SRAM memory -#define WATCHDOG_BASE 0x40000000 // Watchdog -#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A -#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B -#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C -#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D -#define SSI_BASE 0x40008000 // SSI -#define UART0_BASE 0x4000C000 // UART0 -#define UART1_BASE 0x4000D000 // UART1 -#define I2C_MASTER_BASE 0x40020000 // I2C Master -#define I2C_SLAVE_BASE 0x40020800 // I2C Slave -#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E -#define PWM_BASE 0x40028000 // PWM -#define QEI_BASE 0x4002C000 // QEI -#define TIMER0_BASE 0x40030000 // Timer0 -#define TIMER1_BASE 0x40031000 // Timer1 -#define TIMER2_BASE 0x40032000 // Timer2 -#define ADC_BASE 0x40038000 // ADC -#define COMP_BASE 0x4003C000 // Analog comparators -#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller -#define SYSCTL_BASE 0x400FE000 // System Control -#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell -#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace -#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint -#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl -#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit - -#endif // __HW_MEMMAP_H__ diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_nvic.h b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_nvic.h deleted file mode 100644 index 6598ef88b..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_nvic.h +++ /dev/null @@ -1,830 +0,0 @@ -//***************************************************************************** -// -// hw_nvic.h - Macros used when accessing the NVIC hardware. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_NVIC_H__ -#define __HW_NVIC_H__ - -//***************************************************************************** -// -// The following define the addresses of the NVIC registers. -// -//***************************************************************************** -#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg. -#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg. -#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register -#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register -#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg. -#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register -#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg. -#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register -#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg. -#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register -#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register -#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register -#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register -#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register -#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register -#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register -#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register -#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register -#define NVIC_CPUID 0xE000ED00 // CPUID Base Register -#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register -#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register -#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg. -#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register -#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register -#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority -#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority -#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority -#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State -#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg. -#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register -#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register -#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register -#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register -#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register -#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register -#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register -#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register -#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg. -#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg. -#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select -#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data -#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control -#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg. - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_INT_TYPE register. -// -//***************************************************************************** -#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) -#define NVIC_INT_TYPE_LINES_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_CTRL register. -// -//***************************************************************************** -#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag -#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source -#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable -#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_RELOAD register. -// -//***************************************************************************** -#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value -#define NVIC_ST_RELOAD_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_CURRENT register. -// -//***************************************************************************** -#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value -#define NVIC_ST_CURRENT_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_CAL register. -// -//***************************************************************************** -#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock -#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew -#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value -#define NVIC_ST_CAL_ONEMS_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_EN0 register. -// -//***************************************************************************** -#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable -#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable -#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable -#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable -#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable -#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable -#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable -#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable -#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable -#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable -#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable -#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable -#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable -#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable -#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable -#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable -#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable -#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable -#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable -#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable -#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable -#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable -#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable -#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable -#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable -#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable -#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable -#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable -#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable -#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable -#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable -#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DIS0 register. -// -//***************************************************************************** -#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable -#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable -#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable -#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable -#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable -#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable -#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable -#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable -#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable -#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable -#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable -#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable -#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable -#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable -#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable -#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable -#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable -#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable -#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable -#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable -#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable -#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable -#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable -#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable -#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable -#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable -#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable -#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable -#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable -#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable -#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable -#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PEND0 register. -// -//***************************************************************************** -#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend -#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend -#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend -#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend -#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend -#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend -#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend -#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend -#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend -#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend -#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend -#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend -#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend -#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend -#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend -#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend -#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend -#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend -#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend -#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend -#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend -#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend -#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend -#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend -#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend -#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend -#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend -#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend -#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend -#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend -#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend -#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_UNPEND0 register. -// -//***************************************************************************** -#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend -#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend -#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend -#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend -#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend -#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend -#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend -#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend -#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend -#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend -#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend -#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend -#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend -#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend -#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend -#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend -#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend -#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend -#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend -#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend -#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend -#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend -#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend -#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend -#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend -#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend -#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend -#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend -#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend -#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend -#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend -#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ACTIVE0 register. -// -//***************************************************************************** -#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active -#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active -#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active -#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active -#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active -#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active -#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active -#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active -#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active -#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active -#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active -#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active -#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active -#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active -#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active -#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active -#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active -#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active -#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active -#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active -#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active -#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active -#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active -#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active -#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active -#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active -#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active -#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active -#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active -#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active -#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active -#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI0 register. -// -//***************************************************************************** -#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask -#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask -#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask -#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask -#define NVIC_PRI0_INT3_S 24 -#define NVIC_PRI0_INT2_S 16 -#define NVIC_PRI0_INT1_S 8 -#define NVIC_PRI0_INT0_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI1 register. -// -//***************************************************************************** -#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask -#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask -#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask -#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask -#define NVIC_PRI1_INT7_S 24 -#define NVIC_PRI1_INT6_S 16 -#define NVIC_PRI1_INT5_S 8 -#define NVIC_PRI1_INT4_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI2 register. -// -//***************************************************************************** -#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask -#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask -#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask -#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask -#define NVIC_PRI2_INT11_S 24 -#define NVIC_PRI2_INT10_S 16 -#define NVIC_PRI2_INT9_S 8 -#define NVIC_PRI2_INT8_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI3 register. -// -//***************************************************************************** -#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask -#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask -#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask -#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask -#define NVIC_PRI3_INT15_S 24 -#define NVIC_PRI3_INT14_S 16 -#define NVIC_PRI3_INT13_S 8 -#define NVIC_PRI3_INT12_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI4 register. -// -//***************************************************************************** -#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask -#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask -#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask -#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask -#define NVIC_PRI4_INT19_S 24 -#define NVIC_PRI4_INT18_S 16 -#define NVIC_PRI4_INT17_S 8 -#define NVIC_PRI4_INT16_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI5 register. -// -//***************************************************************************** -#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask -#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask -#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask -#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask -#define NVIC_PRI5_INT23_S 24 -#define NVIC_PRI5_INT22_S 16 -#define NVIC_PRI5_INT21_S 8 -#define NVIC_PRI5_INT20_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI6 register. -// -//***************************************************************************** -#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask -#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask -#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask -#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask -#define NVIC_PRI6_INT27_S 24 -#define NVIC_PRI6_INT26_S 16 -#define NVIC_PRI6_INT25_S 8 -#define NVIC_PRI6_INT24_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI7 register. -// -//***************************************************************************** -#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask -#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask -#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask -#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask -#define NVIC_PRI7_INT31_S 24 -#define NVIC_PRI7_INT30_S 16 -#define NVIC_PRI7_INT29_S 8 -#define NVIC_PRI7_INT28_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_CPUID register. -// -//***************************************************************************** -#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer -#define NVIC_CPUID_VAR_M 0x00F00000 // Variant -#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number -#define NVIC_CPUID_REV_M 0x0000000F // Revision - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_INT_CTRL register. -// -//***************************************************************************** -#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI -#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV -#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV -#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling -#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending -#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception -#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base -#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception -#define NVIC_INT_CTRL_VEC_PEN_S 12 -#define NVIC_INT_CTRL_VEC_ACT_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_VTABLE register. -// -//***************************************************************************** -#define NVIC_VTABLE_BASE 0x20000000 // Vector table base -#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset -#define NVIC_VTABLE_OFFSET_S 8 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_APINT register. -// -//***************************************************************************** -#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask -#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key -#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess -#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group -#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split -#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split -#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split -#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split -#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split -#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split -#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split -#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split -#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request -#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info -#define NVIC_APINT_VECT_RESET 0x00000001 // System reset - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_CTRL register. -// -//***************************************************************************** -#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend -#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable -#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_CFG_CTRL register. -// -//***************************************************************************** -#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault -#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0 -#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access -#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger -#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger -#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_PRI1 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler -#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler -#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler -#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler -#define NVIC_SYS_PRI1_USAGE_S 16 -#define NVIC_SYS_PRI1_BUS_S 8 -#define NVIC_SYS_PRI1_MEM_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_PRI2 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler -#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers -#define NVIC_SYS_PRI2_SVC_S 24 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_PRI3 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler -#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler -#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler -#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler -#define NVIC_SYS_PRI3_TICK_S 24 -#define NVIC_SYS_PRI3_PENDSV_S 16 -#define NVIC_SYS_PRI3_DEBUG_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_HND_CTRL register. -// -//***************************************************************************** -#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable -#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable -#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable -#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended -#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended -#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active -#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active -#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active -#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active -#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active -#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active -#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_FAULT_STAT register. -// -//***************************************************************************** -#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault -#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault -#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault -#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault -#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault -#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault -#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid -#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault -#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault -#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error -#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error -#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault -#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid -#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation -#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation -#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation -#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_HFAULT_STAT register. -// -//***************************************************************************** -#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event -#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler -#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DEBUG_STAT register. -// -//***************************************************************************** -#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted -#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch -#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match -#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction -#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MM_ADDR register. -// -//***************************************************************************** -#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address -#define NVIC_MM_ADDR_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_FAULT_ADDR register. -// -//***************************************************************************** -#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address -#define NVIC_FAULT_ADDR_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_EXC_STACK register. -// -//***************************************************************************** -#define NVIC_EXC_STACK_DEEP 0x00000001 // Exception stack - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_EXC_NUM register. -// -//***************************************************************************** -#define NVIC_EXC_NUM_M 0x000003FF // Exception number -#define NVIC_EXC_NUM_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_COPRO register. -// -//***************************************************************************** -#define NVIC_COPRO_15_M 0xC0000000 // Coprocessor 15 access mask -#define NVIC_COPRO_15_DENIED 0x00000000 // Coprocessor 15 access denied -#define NVIC_COPRO_15_PRIV 0x40000000 // Coprocessor 15 privileged addess -#define NVIC_COPRO_15_FULL 0xC0000000 // Coprocessor 15 full access -#define NVIC_COPRO_14_M 0x30000000 // Coprocessor 14 access mask -#define NVIC_COPRO_14_DENIED 0x00000000 // Coprocessor 14 access denied -#define NVIC_COPRO_14_PRIV 0x10000000 // Coprocessor 14 privileged addess -#define NVIC_COPRO_14_FULL 0x30000000 // Coprocessor 14 full access -#define NVIC_COPRO_13_M 0x0C000000 // Coprocessor 13 access mask -#define NVIC_COPRO_13_DENIED 0x00000000 // Coprocessor 13 access denied -#define NVIC_COPRO_13_PRIV 0x04000000 // Coprocessor 13 privileged addess -#define NVIC_COPRO_13_FULL 0x0C000000 // Coprocessor 13 full access -#define NVIC_COPRO_12_M 0x03000000 // Coprocessor 12 access mask -#define NVIC_COPRO_12_DENIED 0x00000000 // Coprocessor 12 access denied -#define NVIC_COPRO_12_PRIV 0x01000000 // Coprocessor 12 privileged addess -#define NVIC_COPRO_12_FULL 0x03000000 // Coprocessor 12 full access -#define NVIC_COPRO_11_M 0x00C00000 // Coprocessor 11 access mask -#define NVIC_COPRO_11_DENIED 0x00000000 // Coprocessor 11 access denied -#define NVIC_COPRO_11_PRIV 0x00400000 // Coprocessor 11 privileged addess -#define NVIC_COPRO_11_FULL 0x00C00000 // Coprocessor 11 full access -#define NVIC_COPRO_10_M 0x00300000 // Coprocessor 10 access mask -#define NVIC_COPRO_10_DENIED 0x00000000 // Coprocessor 10 access denied -#define NVIC_COPRO_10_PRIV 0x00100000 // Coprocessor 10 privileged addess -#define NVIC_COPRO_10_FULL 0x00300000 // Coprocessor 10 full access -#define NVIC_COPRO_9_M 0x000C0000 // Coprocessor 9 access mask -#define NVIC_COPRO_9_DENIED 0x00000000 // Coprocessor 9 access denied -#define NVIC_COPRO_9_PRIV 0x00040000 // Coprocessor 9 privileged addess -#define NVIC_COPRO_9_FULL 0x000C0000 // Coprocessor 9 full access -#define NVIC_COPRO_8_M 0x00030000 // Coprocessor 8 access mask -#define NVIC_COPRO_8_DENIED 0x00000000 // Coprocessor 8 access denied -#define NVIC_COPRO_8_PRIV 0x00010000 // Coprocessor 8 privileged addess -#define NVIC_COPRO_8_FULL 0x00030000 // Coprocessor 8 full access -#define NVIC_COPRO_7_M 0x0000C000 // Coprocessor 7 access mask -#define NVIC_COPRO_7_DENIED 0x00000000 // Coprocessor 7 access denied -#define NVIC_COPRO_7_PRIV 0x00004000 // Coprocessor 7 privileged addess -#define NVIC_COPRO_7_FULL 0x0000C000 // Coprocessor 7 full access -#define NVIC_COPRO_6_M 0x00003000 // Coprocessor 6 access mask -#define NVIC_COPRO_6_DENIED 0x00000000 // Coprocessor 6 access denied -#define NVIC_COPRO_6_PRIV 0x00001000 // Coprocessor 6 privileged addess -#define NVIC_COPRO_6_FULL 0x00003000 // Coprocessor 6 full access -#define NVIC_COPRO_5_M 0x00000C00 // Coprocessor 5 access mask -#define NVIC_COPRO_5_DENIED 0x00000000 // Coprocessor 5 access denied -#define NVIC_COPRO_5_PRIV 0x00000400 // Coprocessor 5 privileged addess -#define NVIC_COPRO_5_FULL 0x00000C00 // Coprocessor 5 full access -#define NVIC_COPRO_4_M 0x00000300 // Coprocessor 4 access mask -#define NVIC_COPRO_4_DENIED 0x00000000 // Coprocessor 4 access denied -#define NVIC_COPRO_4_PRIV 0x00000100 // Coprocessor 4 privileged addess -#define NVIC_COPRO_4_FULL 0x00000300 // Coprocessor 4 full access -#define NVIC_COPRO_3_M 0x000000C0 // Coprocessor 3 access mask -#define NVIC_COPRO_3_DENIED 0x00000000 // Coprocessor 3 access denied -#define NVIC_COPRO_3_PRIV 0x00000040 // Coprocessor 3 privileged addess -#define NVIC_COPRO_3_FULL 0x000000C0 // Coprocessor 3 full access -#define NVIC_COPRO_2_M 0x00000030 // Coprocessor 2 access mask -#define NVIC_COPRO_2_DENIED 0x00000000 // Coprocessor 2 access denied -#define NVIC_COPRO_2_PRIV 0x00000010 // Coprocessor 2 privileged addess -#define NVIC_COPRO_2_FULL 0x00000030 // Coprocessor 2 full access -#define NVIC_COPRO_1_M 0x0000000C // Coprocessor 1 access mask -#define NVIC_COPRO_1_DENIED 0x00000000 // Coprocessor 1 access denied -#define NVIC_COPRO_1_PRIV 0x00000004 // Coprocessor 1 privileged addess -#define NVIC_COPRO_1_FULL 0x0000000C // Coprocessor 1 full access -#define NVIC_COPRO_0_M 0x00000003 // Coprocessor 0 access mask -#define NVIC_COPRO_0_DENIED 0x00000000 // Coprocessor 0 access denied -#define NVIC_COPRO_0_PRIV 0x00000001 // Coprocessor 0 privileged addess -#define NVIC_COPRO_0_FULL 0x00000003 // Coprocessor 0 full access - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_TYPE register. -// -//***************************************************************************** -#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions -#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions -#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU -#define NVIC_MPU_TYPE_IREGION_S 16 -#define NVIC_MPU_TYPE_DREGION_S 8 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_CTRL register. -// -//***************************************************************************** -#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults -#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_NUMBER register. -// -//***************************************************************************** -#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access -#define NVIC_MPU_NUMBER_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_BASE register. -// -//***************************************************************************** -#define NVIC_MPU_BASE_ADDR_M 0xFFFFFF00 // Base address -#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid -#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number -#define NVIC_MPU_BASE_ADDR_S 8 -#define NVIC_MPU_BASE_REGION_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_ATTR register. -// -//***************************************************************************** -#define NVIC_MPU_ATTR_ATTRS 0xFFFF0000 // Attributes -#define NVIC_MPU_ATTR_SRD 0x0000FF00 // Sub-region disable -#define NVIC_MPU_ATTR_SZENABLE 0x000000FF // Region size - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_CTRL register. -// -//***************************************************************************** -#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask -#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key -#define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor -#define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request -#define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable -#define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core -#define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping -#define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt -#define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available -#define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up -#define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core -#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping -#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core -#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core -#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_XFER register. -// -//***************************************************************************** -#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read -#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register -#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 -#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 -#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 -#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 -#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 -#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 -#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 -#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 -#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 -#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 -#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 -#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 -#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 -#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 -#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 -#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 -#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register -#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP -#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP -#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP -#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_DATA register. -// -//***************************************************************************** -#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache -#define NVIC_DBG_DATA_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_INT register. -// -//***************************************************************************** -#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault -#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors -#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error -#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state -#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check -#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error -#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault -#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status -#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset -#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending -#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SW_TRIG register. -// -//***************************************************************************** -#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger -#define NVIC_SW_TRIG_INTID_S 0 - -#endif // __HW_NVIC_H__ diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_pwm.h b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_pwm.h deleted file mode 100644 index cc42015ab..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_pwm.h +++ /dev/null @@ -1,260 +0,0 @@ -//***************************************************************************** -// -// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_PWM_H__ -#define __HW_PWM_H__ - -//***************************************************************************** -// -// PWM Module Register Offsets. -// -//***************************************************************************** -#define PWM_O_CTL 0x00000000 // PWM Master Control register -#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync register -#define PWM_O_ENABLE 0x00000008 // PWM Output Enable register -#define PWM_O_INVERT 0x0000000C // PWM Output Inversion register -#define PWM_O_FAULT 0x00000010 // PWM Output Fault register -#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable register -#define PWM_O_RIS 0x00000018 // PWM Interrupt Raw Status reg. -#define PWM_O_ISC 0x0000001C // PWM Interrupt Status register -#define PWM_O_STATUS 0x00000020 // PWM Status register - -//***************************************************************************** -// -// The following define the bit fields in the PWM Master Control register. -// -//***************************************************************************** -#define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2 -#define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1 -#define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0 - -//***************************************************************************** -// -// The following define the bit fields in the PWM Time Base Sync register. -// -//***************************************************************************** -#define PWM_SYNC_SYNC2 0x00000004 // Reset generator 2 counter -#define PWM_SYNC_SYNC1 0x00000002 // Reset generator 1 counter -#define PWM_SYNC_SYNC0 0x00000001 // Reset generator 0 counter - -//***************************************************************************** -// -// The following define the bit fields in the PWM Output Enable register. -// -//***************************************************************************** -#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 pin enable -#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 pin enable -#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 pin enable -#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 pin enable -#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 pin enable -#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 pin enable - -//***************************************************************************** -// -// The following define the bit fields in the PWM Inversion register. -// -//***************************************************************************** -#define PWM_INVERT_PWM5INV 0x00000020 // PWM5 pin invert -#define PWM_INVERT_PWM4INV 0x00000010 // PWM4 pin invert -#define PWM_INVERT_PWM3INV 0x00000008 // PWM3 pin invert -#define PWM_INVERT_PWM2INV 0x00000004 // PWM2 pin invert -#define PWM_INVERT_PWM1INV 0x00000002 // PWM1 pin invert -#define PWM_INVERT_PWM0INV 0x00000001 // PWM0 pin invert - -//***************************************************************************** -// -// The following define the bit fields in the PWM Fault register. -// -//***************************************************************************** -#define PWM_FAULT_FAULT5 0x00000020 // PWM5 pin fault -#define PWM_FAULT_FAULT4 0x00000010 // PWM5 pin fault -#define PWM_FAULT_FAULT3 0x00000008 // PWM5 pin fault -#define PWM_FAULT_FAULT2 0x00000004 // PWM5 pin fault -#define PWM_FAULT_FAULT1 0x00000002 // PWM5 pin fault -#define PWM_FAULT_FAULT0 0x00000001 // PWM5 pin fault - -//***************************************************************************** -// -// PWM Interrupt Register bit definitions. -// -//***************************************************************************** -#define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending - -//***************************************************************************** -// -// The following define the bit fields in the PWM Status register. -// -//***************************************************************************** -#define PWM_STATUS_FAULT 0x00000001 // Fault status - -//***************************************************************************** -// -// PWM Generator standard offsets. -// -//***************************************************************************** -#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base -#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base -#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base - -#define PWM_O_X_CTL 0x00000000 // Gen Control Reg -#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg -#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg -#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg -#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg -#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg -#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg -#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg -#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg -#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg -#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg -#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg -#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg - -//***************************************************************************** -// -// PWM_X Control Register bit definitions. -// -//***************************************************************************** -#define PWM_X_CTL_ENABLE 0x00000001 // Master enable for gen block -#define PWM_X_CTL_MODE 0x00000002 // Counter mode, down or up/down -#define PWM_X_CTL_DEBUG 0x00000004 // Debug mode -#define PWM_X_CTL_LOADUPD 0x00000008 // Update mode for the load reg -#define PWM_X_CTL_CMPAUPD 0x00000010 // Update mode for comp A reg -#define PWM_X_CTL_CMPBUPD 0x00000020 // Update mode for comp B reg - -//***************************************************************************** -// -// PWM_X Interrupt/Trigger Enable Register bit definitions. -// -//***************************************************************************** -#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Int if COUNT = 0 -#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Int if COUNT = LOAD -#define PWM_X_INTEN_INTCMPAU 0x00000004 // Int if COUNT = CMPA U -#define PWM_X_INTEN_INTCMPAD 0x00000008 // Int if COUNT = CMPA D -#define PWM_X_INTEN_INTCMPBU 0x00000010 // Int if COUNT = CMPA U -#define PWM_X_INTEN_INTCMPBD 0x00000020 // Int if COUNT = CMPA D -#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trig if COUNT = 0 -#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trig if COUNT = LOAD -#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trig if COUNT = CMPA U -#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trig if COUNT = CMPA D -#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trig if COUNT = CMPA U -#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trig if COUNT = CMPA D - -//***************************************************************************** -// -// PWM_X Raw Interrupt Status Register bit definitions. -// -//***************************************************************************** -#define PWM_X_RIS_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 int -#define PWM_X_RIS_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD int -#define PWM_X_RIS_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U int -#define PWM_X_RIS_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D int -#define PWM_X_RIS_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U int -#define PWM_X_RIS_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D int - -//***************************************************************************** -// -// PWM_X Interrupt Status Register bit definitions. -// -//***************************************************************************** -#define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received -#define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd -#define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd -#define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd -#define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd -#define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd - -//***************************************************************************** -// -// PWM_X Generator A/B Control Register bit definitions. -// -//***************************************************************************** -#define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0 -#define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD -#define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U -#define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D -#define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U -#define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D - -//***************************************************************************** -// -// PWM_X Generator A/B Control Register action definitions. -// -//***************************************************************************** -#define PWM_GEN_ACT_NONE 0x0 // Do nothing -#define PWM_GEN_ACT_INV 0x1 // Invert the output signal -#define PWM_GEN_ACT_ZERO 0x2 // Set the output signal to zero -#define PWM_GEN_ACT_ONE 0x3 // Set the output signal to one -#define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action -#define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action -#define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action -#define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action -#define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action -#define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action - -//***************************************************************************** -// -// PWM_X Dead Band Control Register bit definitions. -// -//***************************************************************************** -#define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion - -//***************************************************************************** -// -// PWM Register reset values. -// -//***************************************************************************** -#define PWM_RV_CTL 0x00000000 // Master control of the PWM module -#define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators -#define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM - // output pins -#define PWM_RV_INVERT 0x00000000 // Inversion control for - // PWM output pins -#define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM - // output pins -#define PWM_RV_INTEN 0x00000000 // Interrupt enable -#define PWM_RV_RIS 0x00000000 // Raw interrupt status -#define PWM_RV_ISC 0x00000000 // Interrupt status and clearing -#define PWM_RV_STATUS 0x00000000 // Status -#define PWM_RV_X_CTL 0x00000000 // Master control of the PWM - // generator block -#define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable -#define PWM_RV_X_RIS 0x00000000 // Raw interrupt status -#define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing -#define PWM_RV_X_LOAD 0x00000000 // The load value for the counter -#define PWM_RV_X_COUNT 0x00000000 // The current counter value -#define PWM_RV_X_CMPA 0x00000000 // The comparator A value -#define PWM_RV_X_CMPB 0x00000000 // The comparator B value -#define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A -#define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B -#define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator -#define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay - // count -#define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay - // count - -#endif // __HW_PWM_H__ diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_qei.h b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_qei.h deleted file mode 100644 index 864459f48..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_qei.h +++ /dev/null @@ -1,176 +0,0 @@ -//***************************************************************************** -// -// hw_qei.h - Macros used when accessing the QEI hardware. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_QEI_H__ -#define __HW_QEI_H__ - -//***************************************************************************** -// -// The following define the offsets of the QEI registers. -// -//***************************************************************************** -#define QEI_O_CTL 0x00000000 // Configuration and control reg. -#define QEI_O_STAT 0x00000004 // Status register -#define QEI_O_POS 0x00000008 // Current position register -#define QEI_O_MAXPOS 0x0000000C // Maximum position register -#define QEI_O_LOAD 0x00000010 // Velocity timer load register -#define QEI_O_TIME 0x00000014 // Velocity timer register -#define QEI_O_COUNT 0x00000018 // Velocity pulse count register -#define QEI_O_SPEED 0x0000001C // Velocity speed register -#define QEI_O_INTEN 0x00000020 // Interrupt enable register -#define QEI_O_RIS 0x00000024 // Raw interrupt status register -#define QEI_O_ISC 0x00000028 // Interrupt status register - -//***************************************************************************** -// -// The following define the bit fields in the QEI_CTL register. -// -//***************************************************************************** -#define QEI_CTL_STALLEN 0x00001000 // Stall enable -#define QEI_CTL_INVI 0x00000800 // Invert Index input -#define QEI_CTL_INVB 0x00000400 // Invert PhB input -#define QEI_CTL_INVA 0x00000200 // Invert PhA input -#define QEI_CTL_VELDIV_M 0x000001C0 // Velocity predivider mask -#define QEI_CTL_VELDIV_1 0x00000000 // Predivide by 1 -#define QEI_CTL_VELDIV_2 0x00000040 // Predivide by 2 -#define QEI_CTL_VELDIV_4 0x00000080 // Predivide by 4 -#define QEI_CTL_VELDIV_8 0x000000C0 // Predivide by 8 -#define QEI_CTL_VELDIV_16 0x00000100 // Predivide by 16 -#define QEI_CTL_VELDIV_32 0x00000140 // Predivide by 32 -#define QEI_CTL_VELDIV_64 0x00000180 // Predivide by 64 -#define QEI_CTL_VELDIV_128 0x000001C0 // Predivide by 128 -#define QEI_CTL_VELEN 0x00000020 // Velocity enable -#define QEI_CTL_RESMODE 0x00000010 // Position counter reset mode -#define QEI_CTL_CAPMODE 0x00000008 // Edge capture mode -#define QEI_CTL_SIGMODE 0x00000004 // Encoder signaling mode -#define QEI_CTL_SWAP 0x00000002 // Swap input signals -#define QEI_CTL_ENABLE 0x00000001 // QEI enable - -//***************************************************************************** -// -// The following define the bit fields in the QEI_STAT register. -// -//***************************************************************************** -#define QEI_STAT_DIRECTION 0x00000002 // Direction of rotation -#define QEI_STAT_ERROR 0x00000001 // Signalling error detected - -//***************************************************************************** -// -// The following define the bit fields in the QEI_POS register. -// -//***************************************************************************** -#define QEI_POS_M 0xFFFFFFFF // Current encoder position -#define QEI_POS_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_MAXPOS register. -// -//***************************************************************************** -#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum encoder position -#define QEI_MAXPOS_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_LOAD register. -// -//***************************************************************************** -#define QEI_LOAD_M 0xFFFFFFFF // Velocity timer load value -#define QEI_LOAD_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_TIME register. -// -//***************************************************************************** -#define QEI_TIME_M 0xFFFFFFFF // Velocity timer current value -#define QEI_TIME_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_COUNT register. -// -//***************************************************************************** -#define QEI_COUNT_M 0xFFFFFFFF // Encoder running pulse count -#define QEI_COUNT_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_SPEED register. -// -//***************************************************************************** -#define QEI_SPEED_M 0xFFFFFFFF // Encoder pulse count -#define QEI_SPEED_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_INTEN register. -// -//***************************************************************************** -#define QEI_INTEN_ERROR 0x00000008 // Phase error detected -#define QEI_INTEN_DIR 0x00000004 // Direction change -#define QEI_INTEN_TIMER 0x00000002 // Velocity timer expired -#define QEI_INTEN_INDEX 0x00000001 // Index pulse detected - -//***************************************************************************** -// -// The following define the bit fields in the QEI_RIS register. -// -//***************************************************************************** -#define QEI_RIS_ERROR 0x00000008 // Phase error detected -#define QEI_RIS_DIR 0x00000004 // Direction change -#define QEI_RIS_TIMER 0x00000002 // Velocity timer expired -#define QEI_RIS_INDEX 0x00000001 // Index pulse detected - -//***************************************************************************** -// -// The following define the bit fields in the QEI_ISC register. -// -//***************************************************************************** -#define QEI_INT_ERROR 0x00000008 // Phase error detected -#define QEI_INT_DIR 0x00000004 // Direction change -#define QEI_INT_TIMER 0x00000002 // Velocity timer expired -#define QEI_INT_INDEX 0x00000001 // Index pulse detected - -//***************************************************************************** -// -// The following define the reset values for the QEI registers. -// -//***************************************************************************** -#define QEI_RV_CTL 0x00000000 // Configuration and control reg. -#define QEI_RV_STAT 0x00000000 // Status register -#define QEI_RV_POS 0x00000000 // Current position register -#define QEI_RV_MAXPOS 0x00000000 // Maximum position register -#define QEI_RV_LOAD 0x00000000 // Velocity timer load register -#define QEI_RV_TIME 0x00000000 // Velocity timer register -#define QEI_RV_COUNT 0x00000000 // Velocity pulse count register -#define QEI_RV_SPEED 0x00000000 // Velocity speed register -#define QEI_RV_INTEN 0x00000000 // Interrupt enable register -#define QEI_RV_RIS 0x00000000 // Raw interrupt status register -#define QEI_RV_ISC 0x00000000 // Interrupt status register - -#endif // __HW_QEI_H__ diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_ssi.h b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_ssi.h deleted file mode 100644 index e4650af40..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_ssi.h +++ /dev/null @@ -1,120 +0,0 @@ -//***************************************************************************** -// -// hw_ssi.h - Macros used when accessing the SSI hardware. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_SSI_H__ -#define __HW_SSI_H__ - -//***************************************************************************** -// -// The following define the offsets of the SSI registers. -// -//***************************************************************************** -#define SSI_O_CR0 0x00000000 // Control register 0 -#define SSI_O_CR1 0x00000004 // Control register 1 -#define SSI_O_DR 0x00000008 // Data register -#define SSI_O_SR 0x0000000C // Status register -#define SSI_O_CPSR 0x00000010 // Clock prescale register -#define SSI_O_IM 0x00000014 // Int mask set and clear register -#define SSI_O_RIS 0x00000018 // Raw interrupt register -#define SSI_O_MIS 0x0000001C // Masked interrupt register -#define SSI_O_ICR 0x00000020 // Interrupt clear register - -//***************************************************************************** -// -// The following define the bit fields in the SSI Control register 0. -// -//***************************************************************************** -#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate -#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase -#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity -#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask -#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format -#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format -#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format -#define SSI_CR0_DSS 0x0000000F // Data size select -#define SSI_CR0_DSS_4 0x00000003 // 4 bit data -#define SSI_CR0_DSS_5 0x00000004 // 5 bit data -#define SSI_CR0_DSS_6 0x00000005 // 6 bit data -#define SSI_CR0_DSS_7 0x00000006 // 7 bit data -#define SSI_CR0_DSS_8 0x00000007 // 8 bit data -#define SSI_CR0_DSS_9 0x00000008 // 9 bit data -#define SSI_CR0_DSS_10 0x00000009 // 10 bit data -#define SSI_CR0_DSS_11 0x0000000A // 11 bit data -#define SSI_CR0_DSS_12 0x0000000B // 12 bit data -#define SSI_CR0_DSS_13 0x0000000C // 13 bit data -#define SSI_CR0_DSS_14 0x0000000D // 14 bit data -#define SSI_CR0_DSS_15 0x0000000E // 15 bit data -#define SSI_CR0_DSS_16 0x0000000F // 16 bit data - -//***************************************************************************** -// -// The following define the bit fields in the SSI Control register 1. -// -//***************************************************************************** -#define SSI_CR1_SOD 0x00000008 // Slave mode output disable -#define SSI_CR1_MS 0x00000004 // Master or slave mode select -#define SSI_CR1_SSE 0x00000002 // Sync serial port enable -#define SSI_CR1_LBM 0x00000001 // Loopback mode - -//***************************************************************************** -// -// The following define the bit fields in the SSI Status register. -// -//***************************************************************************** -#define SSI_SR_BSY 0x00000010 // SSI busy -#define SSI_SR_RFF 0x00000008 // RX FIFO full -#define SSI_SR_RNE 0x00000004 // RX FIFO not empty -#define SSI_SR_TNF 0x00000002 // TX FIFO not full -#define SSI_SR_TFE 0x00000001 // TX FIFO empty - -//***************************************************************************** -// -// The following define the bit fields in the SSI clock prescale register. -// -//***************************************************************************** -#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale - -//***************************************************************************** -// -// The following define information concerning the SSI Data register. -// -//***************************************************************************** -#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO -#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO - -//***************************************************************************** -// -// The following define the bit fields in the interrupt mask set and clear, -// raw interrupt, masked interrupt, and interrupt clear registers. -// -//***************************************************************************** -#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt -#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt -#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt -#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt - -#endif // __HW_SSI_H__ diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_sysctl.h b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_sysctl.h deleted file mode 100644 index cce5ad214..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_sysctl.h +++ /dev/null @@ -1,409 +0,0 @@ -//***************************************************************************** -// -// hw_sysctl.h - Macros used when accessing the system control hardware. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_SYSCTL_H__ -#define __HW_SYSCTL_H__ - -//***************************************************************************** -// -// The following define the offsets of the system control registers. -// -//***************************************************************************** -#define SYSCTL_DID0 0x400fe000 // Device identification register 0 -#define SYSCTL_DID1 0x400fe004 // Device identification register 1 -#define SYSCTL_DC0 0x400fe008 // Device capabilities register 0 -#define SYSCTL_DC1 0x400fe010 // Device capabilities register 1 -#define SYSCTL_DC2 0x400fe014 // Device capabilities register 2 -#define SYSCTL_DC3 0x400fe018 // Device capabilities register 3 -#define SYSCTL_DC4 0x400fe01C // Device capabilities register 4 -#define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register -#define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register -#define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0 -#define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1 -#define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2 -#define SYSCTL_RIS 0x400fe050 // Raw interrupt status register -#define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register -#define SYSCTL_MISC 0x400fe058 // Interrupt status register -#define SYSCTL_RESC 0x400fe05c // Reset cause register -#define SYSCTL_RCC 0x400fe060 // Run-mode clock config register -#define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register -#define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0 -#define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1 -#define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2 -#define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0 -#define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1 -#define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2 -#define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0 -#define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1 -#define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2 -#define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register -#define SYSCTL_LDOARST 0x400fe160 // LDO reset control register - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DID0 register. -// -//***************************************************************************** -#define SYSCTL_DID0_VER_MASK 0x70000000 // DID0 version mask -#define SYSCTL_DID0_VER_0 0x00000000 // DID0 version 0 -#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask -#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A -#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B -#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask -#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0 -#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DID1 register. -// -//***************************************************************************** -#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask -#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask -#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family -#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask -#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101 -#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102 -#define SYSCTL_DID1_PRTNO_301 0x00110000 // LM3S301 -#define SYSCTL_DID1_PRTNO_310 0x00120000 // LM3S310 -#define SYSCTL_DID1_PRTNO_315 0x00130000 // LM3S315 -#define SYSCTL_DID1_PRTNO_316 0x00140000 // LM3S316 -#define SYSCTL_DID1_PRTNO_328 0x00150000 // LM3S328 -#define SYSCTL_DID1_PRTNO_601 0x00210000 // LM3S601 -#define SYSCTL_DID1_PRTNO_610 0x00220000 // LM3S610 -#define SYSCTL_DID1_PRTNO_611 0x00230000 // LM3S611 -#define SYSCTL_DID1_PRTNO_612 0x00240000 // LM3S612 -#define SYSCTL_DID1_PRTNO_613 0x00250000 // LM3S613 -#define SYSCTL_DID1_PRTNO_615 0x00260000 // LM3S615 -#define SYSCTL_DID1_PRTNO_628 0x00270000 // LM3S628 -#define SYSCTL_DID1_PRTNO_801 0x00310000 // LM3S801 -#define SYSCTL_DID1_PRTNO_811 0x00320000 // LM3S811 -#define SYSCTL_DID1_PRTNO_812 0x00330000 // LM3S812 -#define SYSCTL_DID1_PRTNO_815 0x00340000 // LM3S815 -#define SYSCTL_DID1_PRTNO_828 0x00350000 // LM3S828 -#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask -#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C) -#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C) -#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask -#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC -#define SYSCTL_DID1_PKG_48QFP 0x00000008 // 48-pin QFP -#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant -#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask -#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified) -#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified) -#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified -#define SYSCTL_DID1_PRTNO_SHIFT 16 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC0 register. -// -//***************************************************************************** -#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask -#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2kB of SRAM -#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4kB of SRAM -#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8kB of SRAM -#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask -#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8kB of flash -#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16kB of flash -#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32kB of flash -#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64kB of flash - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC1 register. -// -//***************************************************************************** -#define SYSCTL_DC1_PWM 0x00100000 // PWM module present -#define SYSCTL_DC1_ADC 0x00010000 // ADC module present -#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask -#define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask -#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1Msps ADC -#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500Ksps ADC -#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250Ksps ADC -#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC -#define SYSCTL_DC1_MPU 0x00000080 // Cortex M3 MPU present -#define SYSCTL_DC1_TEMP 0x00000020 // Temperature sensor present -#define SYSCTL_DC1_PLL 0x00000010 // PLL present -#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present -#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present -#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present -#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC2 register. -// -//***************************************************************************** -#define SYSCTL_DC2_COMP2 0x04000000 // Analog comparator 2 present -#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present -#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present -#define SYSCTL_DC2_TIMER2 0x00040000 // Timer 2 present -#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present -#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present -#define SYSCTL_DC2_I2C 0x00001000 // I2C present -#define SYSCTL_DC2_QEI 0x00000100 // QEI present -#define SYSCTL_DC2_SSI 0x00000010 // SSI present -#define SYSCTL_DC2_UART1 0x00000002 // UART 1 present -#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC3 register. -// -//***************************************************************************** -#define SYSCTL_DC3_32KHZ 0x80000000 // 32kHz pin present -#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 pin present -#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 pin present -#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 pin present -#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 pin present -#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present -#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present -#define SYSCTL_DC3_ADC7 0x00800000 // ADC7 pin present -#define SYSCTL_DC3_ADC6 0x00400000 // ADC6 pin present -#define SYSCTL_DC3_ADC5 0x00200000 // ADC5 pin present -#define SYSCTL_DC3_ADC4 0x00100000 // ADC4 pin present -#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 pin present -#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 pin present -#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 pin present -#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 pin present -#define SYSCTL_DC3_C2O 0x00004000 // C2o pin present -#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ pin present -#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- pin present -#define SYSCTL_DC3_C1O 0x00000800 // C1o pin present -#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ pin present -#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present -#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present -#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present -#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present -#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 pin present -#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 pin present -#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 pin present -#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 pin present -#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 pin present -#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 pin present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC4 register. -// -//***************************************************************************** -#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO port E present -#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO port D present -#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present -#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present -#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_PBORCTL register. -// -//***************************************************************************** -#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer -#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset -#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise -#define SYSCTL_PBORCTL_BOR_SH 2 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_LDOPCTL register. -// -//***************************************************************************** -#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask -#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V -#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V -#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V -#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V -#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V -#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V -#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V -#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V -#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V -#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V -#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0, -// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers. -// -//***************************************************************************** -#define SYSCTL_SET0_PWM 0x00100000 // PWM module -#define SYSCTL_SET0_ADC 0x00010000 // ADC module -#define SYSCTL_SET0_ADCSPD_MASK 0x00000F00 // ADC speed mask -#define SYSCTL_SET0_ADCSPD_1M 0x00000300 // 1Msps ADC -#define SYSCTL_SET0_ADCSPD_500K 0x00000200 // 500Ksps ADC -#define SYSCTL_SET0_ADCSPD_250K 0x00000100 // 250Ksps ADC -#define SYSCTL_SET0_ADCSPD_125K 0x00000000 // 125Ksps ADC -#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1, -// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers. -// -//***************************************************************************** -#define SYSCTL_SET1_COMP2 0x04000000 // Analog comparator module 2 -#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1 -#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0 -#define SYSCTL_SET1_TIMER2 0x00040000 // Timer module 2 -#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1 -#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0 -#define SYSCTL_SET1_I2C 0x00001000 // I2C module -#define SYSCTL_SET1_QEI 0x00000100 // QEI module -#define SYSCTL_SET1_SSI 0x00000010 // SSI module -#define SYSCTL_SET1_UART1 0x00000002 // UART module 1 -#define SYSCTL_SET1_UART0 0x00000001 // UART module 0 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2, -// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers. -// -//***************************************************************************** -#define SYSCTL_SET2_GPIOE 0x00000010 // GPIO E module -#define SYSCTL_SET2_GPIOD 0x00000008 // GPIO D module -#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module -#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module -#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and -// SYSCTL_IMS registers. -// -//***************************************************************************** -#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt -#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt -#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int -#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int -#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt -#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt -#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_RESC register. -// -//***************************************************************************** -#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset -#define SYSCTL_RESC_SW 0x00000010 // Software reset -#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset -#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset -#define SYSCTL_RESC_POR 0x00000002 // Power on reset -#define SYSCTL_RESC_EXT 0x00000001 // External reset - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_RCC register. -// -//***************************************************************************** -#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating -#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider -#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2 -#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3 -#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4 -#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5 -#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6 -#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7 -#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8 -#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9 -#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10 -#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11 -#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12 -#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13 -#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14 -#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15 -#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16 -#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider -#define SYSCTL_RCC_USE_PWMDIV 0x00100000 // Use PWM clock divider -#define SYSCTL_RCC_PWMDIV_MASK 0x000E0000 // PWM clock divider -#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2 -#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4 -#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8 -#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16 -#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32 -#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64 -#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down -#define SYSCTL_RCC_OE 0x00001000 // PLL output enable -#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass -#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable -#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc -#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal -#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864MHz crystal -#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4MHz crystal -#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal -#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal -#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal -#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal -#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal -#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal -#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal -#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal -#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal -#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select -#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator -#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // Use the internal oscillator -#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // Use the internal oscillator / 4 -#define SYSCTL_RCC_IOSCVER 0x00000008 // Int. osc. verification timer en -#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en -#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal oscillator disable -#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable -#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field -#define SYSCTL_RCC_PWMDIV_SHIFT 17 // Shift to the PWMDIV field -#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field -#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_PLLCFG register. -// -//***************************************************************************** -#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider -#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1 -#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2 -#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4 -#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier -#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider -#define SYSCTL_PLLCFG_F_SHIFT 5 -#define SYSCTL_PLLCFG_R_SHIFT 0 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_CLKVCLR register. -// -//***************************************************************************** -#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_LDOARST register. -// -//***************************************************************************** -#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device - -#endif // __HW_SYSCTL_H__ diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_timer.h b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_timer.h deleted file mode 100644 index 210c3408e..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_timer.h +++ /dev/null @@ -1,235 +0,0 @@ -//***************************************************************************** -// -// hw_timer.h - Defines and macros used when accessing the timer. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_TIMER_H__ -#define __HW_TIMER_H__ - -//***************************************************************************** -// -// The following define the offsets of the timer registers. -// -//***************************************************************************** -#define TIMER_O_CFG 0x00000000 // Configuration register -#define TIMER_O_TAMR 0x00000004 // TimerA mode register -#define TIMER_O_TBMR 0x00000008 // TimerB mode register -#define TIMER_O_CTL 0x0000000C // Control register -#define TIMER_O_IMR 0x00000018 // Interrupt mask register -#define TIMER_O_RIS 0x0000001C // Interrupt status register -#define TIMER_O_MIS 0x00000020 // Masked interrupt status reg. -#define TIMER_O_ICR 0x00000024 // Interrupt clear register -#define TIMER_O_TAILR 0x00000028 // TimerA interval load register -#define TIMER_O_TBILR 0x0000002C // TimerB interval load register -#define TIMER_O_TAMATCHR 0x00000030 // TimerA match register -#define TIMER_O_TBMATCHR 0x00000034 // TimerB match register -#define TIMER_O_TAPR 0x00000038 // TimerA prescale register -#define TIMER_O_TBPR 0x0000003C // TimerB prescale register -#define TIMER_O_TAPMR 0x00000040 // TimerA prescale match register -#define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register -#define TIMER_O_TAR 0x00000048 // TimerA register -#define TIMER_O_TBR 0x0000004C // TimerB register - -//***************************************************************************** -// -// The following define the reset values of the timer registers. -// -//***************************************************************************** -#define TIMER_RV_CFG 0x00000000 // Configuration register RV -#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV -#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV -#define TIMER_RV_CTL 0x00000000 // Control register RV -#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV -#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV -#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV -#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV -#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV -#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV -#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV -#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV -#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV -#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV -#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV -#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV -#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV -#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_CFG register. -// -//***************************************************************************** -#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask -#define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers -#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC -#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_TnMR register. -// -//***************************************************************************** -#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select -#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time -#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask -#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture -#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic -#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_CTL register. -// -//***************************************************************************** -#define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert -#define TIMER_CTL_TBOTE 0x00002000 // TimerB output trigger enable -#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask -#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges -#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge -#define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge -#define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable -#define TIMER_CTL_TBEN 0x00000100 // TimerB enable -#define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert -#define TIMER_CTL_TAOTE 0x00000020 // TimerA output trigger enable -#define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable -#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask -#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges -#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge -#define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge -#define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable -#define TIMER_CTL_TAEN 0x00000001 // TimerA enable - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_IMR register. -// -//***************************************************************************** -#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask -#define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask -#define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask -#define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask -#define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask -#define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask -#define TIMER_IMR_TATOIM 0x00000001 // TimerA time out interrupt mask - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_RIS register. -// -//***************************************************************************** -#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status -#define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status -#define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status -#define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status -#define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status -#define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status -#define TIMER_RIS_TATORIS 0x00000001 // TimerA time out raw int status - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_MIS register. -// -//***************************************************************************** -#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status -#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status -#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat -#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status -#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status -#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status -#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_ICR register. -// -//***************************************************************************** -#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear -#define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear -#define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear -#define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear -#define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear -#define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear -#define TIMER_ICR_TATOCINT 0x00000001 // TimerA time out interrupt clear - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_TAILR register. -// -//***************************************************************************** -#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode -#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TBILR register. -// -//***************************************************************************** -#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_TAMATCHR register. -// -//***************************************************************************** -#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode -#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TBMATCHR register. -// -//***************************************************************************** -#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TnPR register. -// -//***************************************************************************** -#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TnPMR register. -// -//***************************************************************************** -#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_TAR register. -// -//***************************************************************************** -#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode -#define TIMER_TAR_TARL 0x0000FFFF // TimerA value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TBR register. -// -//***************************************************************************** -#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value - -#endif // __HW_TIMER_H__ diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_types.h b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_types.h deleted file mode 100644 index ec05e5415..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_types.h +++ /dev/null @@ -1,67 +0,0 @@ -//***************************************************************************** -// -// hw_types.h - Common types and macros. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_TYPES_H__ -#define __HW_TYPES_H__ - -//***************************************************************************** -// -// Define a boolean type, and values for true and false. -// -//***************************************************************************** -typedef unsigned char tBoolean; - -#ifndef true -#define true 1 -#endif - -#ifndef false -#define false 0 -#endif - -//***************************************************************************** -// -// Macros for hardware access, both direct and via the bit-band region. -// -//***************************************************************************** -#define HWREG(x) \ - (*((volatile unsigned long *)(x))) -#define HWREGH(x) \ - (*((volatile unsigned short *)(x))) -#define HWREGB(x) \ - (*((volatile unsigned char *)(x))) -#define HWREGBITW(x, b) \ - HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) -#define HWREGBITH(x, b) \ - HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) -#define HWREGBITB(x, b) \ - HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) - -#endif // __HW_TYPES_H__ diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_uart.h b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_uart.h deleted file mode 100644 index 6f421b64e..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_uart.h +++ /dev/null @@ -1,239 +0,0 @@ -//***************************************************************************** -// -// hw_uart.h - Macros and defines used when accessing the UART hardware -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_UART_H__ -#define __HW_UART_H__ - -//***************************************************************************** -// -// UART Register Offsets. -// -//***************************************************************************** -#define UART_O_DR 0x00000000 // Data Register -#define UART_O_RSR 0x00000004 // Receive Status Register (read) -#define UART_O_ECR 0x00000004 // Error Clear Register (write) -#define UART_O_FR 0x00000018 // Flag Register (read only) -#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg -#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg -#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte -#define UART_O_CTL 0x00000030 // Control Register -#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg -#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg -#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register -#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register -#define UART_O_ICR 0x00000044 // Interrupt Clear Register -#define UART_O_PeriphID4 0x00000FD0 // -#define UART_O_PeriphID5 0x00000FD4 // -#define UART_O_PeriphID6 0x00000FD8 // -#define UART_O_PeriphID7 0x00000FDC // -#define UART_O_PeriphID0 0x00000FE0 // -#define UART_O_PeriphID1 0x00000FE4 // -#define UART_O_PeriphID2 0x00000FE8 // -#define UART_O_PeriphID3 0x00000FEC // -#define UART_O_PCellID0 0x00000FF0 // -#define UART_O_PCellID1 0x00000FF4 // -#define UART_O_PCellID2 0x00000FF8 // -#define UART_O_PCellID3 0x00000FFC // - -//***************************************************************************** -// -// Data Register bits -// -//***************************************************************************** -#define UART_DR_OE 0x00000800 // Overrun Error -#define UART_DR_BE 0x00000400 // Break Error -#define UART_DR_PE 0x00000200 // Parity Error -#define UART_DR_FE 0x00000100 // Framing Error -#define UART_DR_DATA_MASK 0x000000FF // UART data - -//***************************************************************************** -// -// Receive Status Register bits -// -//***************************************************************************** -#define UART_RSR_OE 0x00000008 // Overrun Error -#define UART_RSR_BE 0x00000004 // Break Error -#define UART_RSR_PE 0x00000002 // Parity Error -#define UART_RSR_FE 0x00000001 // Framing Error - -//***************************************************************************** -// -// Flag Register bits -// -//***************************************************************************** -#define UART_FR_TXFE 0x00000080 // TX FIFO Empty -#define UART_FR_RXFF 0x00000040 // RX FIFO Full -#define UART_FR_TXFF 0x00000020 // TX FIFO Full -#define UART_FR_RXFE 0x00000010 // RX FIFO Empty -#define UART_FR_BUSY 0x00000008 // UART Busy - -//***************************************************************************** -// -// Integer baud-rate divisor -// -//***************************************************************************** -#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor - -//***************************************************************************** -// -// Fractional baud-rate divisor -// -//***************************************************************************** -#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor - -//***************************************************************************** -// -// Line Control Register High bits -// -//***************************************************************************** -#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select -#define UART_LCR_H_WLEN 0x00000060 // Word length -#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data -#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data -#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data -#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data -#define UART_LCR_H_FEN 0x00000010 // Enable FIFO -#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select -#define UART_LCR_H_EPS 0x00000004 // Even Parity Select -#define UART_LCR_H_PEN 0x00000002 // Parity Enable -#define UART_LCR_H_BRK 0x00000001 // Send Break - -//***************************************************************************** -// -// Control Register bits -// -//***************************************************************************** -#define UART_CTL_RXE 0x00000200 // Receive Enable -#define UART_CTL_TXE 0x00000100 // Transmit Enable -#define UART_CTL_LBE 0x00000080 // Loopback Enable -#define UART_CTL_UARTEN 0x00000001 // UART Enable - -//***************************************************************************** -// -// Interrupt FIFO Level Select Register bits -// -//***************************************************************************** -#define UART_IFLS_RX1_8 0x00000000 // 1/8 Full -#define UART_IFLS_RX2_8 0x00000010 // 1/4 Full -#define UART_IFLS_RX4_8 0x00000020 // 1/2 Full -#define UART_IFLS_RX6_8 0x00000030 // 3/4 Full -#define UART_IFLS_RX7_8 0x00000040 // 7/8 Full -#define UART_IFLS_TX1_8 0x00000000 // 1/8 Full -#define UART_IFLS_TX2_8 0x00000001 // 1/4 Full -#define UART_IFLS_TX4_8 0x00000002 // 1/2 Full -#define UART_IFLS_TX6_8 0x00000003 // 3/4 Full -#define UART_IFLS_TX7_8 0x00000004 // 7/8 Full - -//***************************************************************************** -// -// Interrupt Mask Set/Clear Register bits -// -//***************************************************************************** -#define UART_IM_OEIM 0x00000400 // Overrun Error Interrupt Mask -#define UART_IM_BEIM 0x00000200 // Break Error Interrupt Mask -#define UART_IM_PEIM 0x00000100 // Parity Error Interrupt Mask -#define UART_IM_FEIM 0x00000080 // Framing Error Interrupt Mask -#define UART_IM_RTIM 0x00000040 // Receive Timeout Interrupt Mask -#define UART_IM_TXIM 0x00000020 // Transmit Interrupt Mask -#define UART_IM_RXIM 0x00000010 // Receive Interrupt Mask - -//***************************************************************************** -// -// Raw Interrupt Status Register -// -//***************************************************************************** -#define UART_RIS_OERIS 0x00000400 // Overrun Error Interrupt Status -#define UART_RIS_BERIS 0x00000200 // Break Error Interrupt Status -#define UART_RIS_PERIS 0x00000100 // Parity Error Interrupt Status -#define UART_RIS_FERIS 0x00000080 // Framing Error Interrupt Status -#define UART_RIS_RTRIS 0x00000040 // Receive Timeout Interrupt Status -#define UART_RIS_TXRIS 0x00000020 // Transmit Interrupt Status -#define UART_RIS_RXRIS 0x00000010 // Receive Interrupt Status - -//***************************************************************************** -// -// Masked Interrupt Status Register -// -//***************************************************************************** -#define UART_MIS_OEMIS 0x00000400 // Overrun Error Interrupt Status -#define UART_MIS_BEMIS 0x00000200 // Break Error Interrupt Status -#define UART_MIS_PEMIS 0x00000100 // Parity Error Interrupt Status -#define UART_MIS_FEMIS 0x00000080 // Framing Error Interrupt Status -#define UART_MIS_RTMIS 0x00000040 // Receive Timeout Interrupt Status -#define UART_MIS_TXMIS 0x00000020 // Transmit Interrupt Status -#define UART_MIS_RXMIS 0x00000010 // Receive Interrupt Status - -//***************************************************************************** -// -// Interrupt Clear Register bits -// -//***************************************************************************** -#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear -#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear -#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear -#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear -#define UART_ICR_RTIC 0x00000040 // Receive Timeout Interrupt Clear -#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear -#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear - -#define UART_RSR_ANY (UART_RSR_OE | \ - UART_RSR_BE | \ - UART_RSR_PE | \ - UART_RSR_FE) - -//***************************************************************************** -// -// Reset Values for UART Registers. -// -//***************************************************************************** -#define UART_RV_DR 0x00000000 -#define UART_RV_RSR 0x00000000 -#define UART_RV_ECR 0x00000000 -#define UART_RV_FR 0x00000090 -#define UART_RV_IBRD 0x00000000 -#define UART_RV_FBRD 0x00000000 -#define UART_RV_LCR_H 0x00000000 -#define UART_RV_CTL 0x00000300 -#define UART_RV_IFLS 0x00000012 -#define UART_RV_IM 0x00000000 -#define UART_RV_RIS 0x00000000 -#define UART_RV_MIS 0x00000000 -#define UART_RV_ICR 0x00000000 -#define UART_RV_PeriphID4 0x00000000 -#define UART_RV_PeriphID5 0x00000000 -#define UART_RV_PeriphID6 0x00000000 -#define UART_RV_PeriphID7 0x00000000 -#define UART_RV_PeriphID0 0x00000011 -#define UART_RV_PeriphID1 0x00000000 -#define UART_RV_PeriphID2 0x00000018 -#define UART_RV_PeriphID3 0x00000001 -#define UART_RV_PCellID0 0x0000000D -#define UART_RV_PCellID1 0x000000F0 -#define UART_RV_PCellID2 0x00000005 -#define UART_RV_PCellID3 0x000000B1 - -#endif // __HW_UART_H__ diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_watchdog.h b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_watchdog.h deleted file mode 100644 index 2b013ad84..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/hw_watchdog.h +++ /dev/null @@ -1,116 +0,0 @@ -//***************************************************************************** -// -// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_WATCHDOG_H__ -#define __HW_WATCHDOG_H__ - -//***************************************************************************** -// -// The following define the offsets of the Watchdog Timer registers. -// -//***************************************************************************** -#define WDT_O_LOAD 0x00000000 // Load register -#define WDT_O_VALUE 0x00000004 // Current value register -#define WDT_O_CTL 0x00000008 // Control register -#define WDT_O_ICR 0x0000000C // Interrupt clear register -#define WDT_O_RIS 0x00000010 // Raw interrupt status register -#define WDT_O_MIS 0x00000014 // Masked interrupt status register -#define WDT_O_TEST 0x00000418 // Test register -#define WDT_O_LOCK 0x00000C00 // Lock register -#define WDT_O_PeriphID4 0x00000FD0 // -#define WDT_O_PeriphID5 0x00000FD4 // -#define WDT_O_PeriphID6 0x00000FD8 // -#define WDT_O_PeriphID7 0x00000FDC // -#define WDT_O_PeriphID0 0x00000FE0 // -#define WDT_O_PeriphID1 0x00000FE4 // -#define WDT_O_PeriphID2 0x00000FE8 // -#define WDT_O_PeriphID3 0x00000FEC // -#define WDT_O_PCellID0 0x00000FF0 // -#define WDT_O_PCellID1 0x00000FF4 // -#define WDT_O_PCellID2 0x00000FF8 // -#define WDT_O_PCellID3 0x00000FFC // - -//***************************************************************************** -// -// The following define the bit fields in the WDT_CTL register. -// -//***************************************************************************** -#define WDT_CTL_RESEN 0x00000002 // Enable reset output -#define WDT_CTL_INTEN 0x00000001 // Enable the WDT counter and int - -//***************************************************************************** -// -// The following define the bit fields in the WDT_ISR, WDT_RIS, and WDT_MIS -// registers. -// -//***************************************************************************** -#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired - -//***************************************************************************** -// -// The following define the bit fields in the WDT_TEST register. -// -//***************************************************************************** -#define WDT_TEST_STALL 0x00000100 // Watchdog stall enable -#ifndef DEPRECATED -#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable -#endif - -//***************************************************************************** -// -// The following define the bit fields in the WDT_LOCK register. -// -//***************************************************************************** -#define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked -#define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked -#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer - -//***************************************************************************** -// -// The following define the reset values for the WDT registers. -// -//***************************************************************************** -#define WDT_RV_LOAD 0xFFFFFFFF // Load register -#define WDT_RV_VALUE 0xFFFFFFFF // Current value register -#define WDT_RV_CTL 0x00000000 // Control register -#define WDT_RV_RIS 0x00000000 // Raw interrupt status register -#define WDT_RV_MIS 0x00000000 // Masked interrupt status register -#define WDT_RV_LOCK 0x00000000 // Lock register -#define WDT_RV_PeriphID4 0x00000000 // -#define WDT_RV_PeriphID5 0x00000000 // -#define WDT_RV_PeriphID6 0x00000000 // -#define WDT_RV_PeriphID7 0x00000000 // -#define WDT_RV_PeriphID0 0x00000005 // -#define WDT_RV_PeriphID1 0x00000018 // -#define WDT_RV_PeriphID2 0x00000018 // -#define WDT_RV_PeriphID3 0x00000001 // -#define WDT_RV_PCellID0 0x0000000D // -#define WDT_RV_PCellID1 0x000000F0 // -#define WDT_RV_PCellID2 0x00000005 // -#define WDT_RV_PCellID3 0x000000B1 // - -#endif // __HW_WATCHDOG_H__ diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/i2c.c b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/i2c.c deleted file mode 100644 index b460ad603..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/i2c.c +++ /dev/null @@ -1,972 +0,0 @@ -//***************************************************************************** -// -// i2c.c - Driver for Inter-IC (I2C) bus block. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup i2c_api -//! @{ -// -//***************************************************************************** - -#include "../hw_i2c.h" -#include "../hw_ints.h" -#include "../hw_memmap.h" -#include "../hw_types.h" -#include "debug.h" -#include "i2c.h" -#include "interrupt.h" -#include "sysctl.h" - -//***************************************************************************** -// -//! Initializes the I2C Master block. -//! -//! \param ulBase base address of the I2C Master module -//! \param bFast set up for fast data transfers -//! -//! This function initializes operation of the I2C Master block. Upon -//! successful initialization of the I2C block, this function will have -//! set the bus speed for the master, and will have enabled the I2C Master -//! block. -//! -//! If the parameter \e bFast is \b true, then the master block will be -//! set up to transfer data at 400 kbps; otherwise, it will be set up to -//! transfer data at 100 kbps. -//! -//! The I2C clocking is dependent upon the system clock rate returned by -//! SysCtlClockGet(); if it does not return the correct system clock rate then -//! the I2C clock rate will be incorrect. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_masterinit) || defined(BUILD_ALL) || defined(DOXYGEN) -void -I2CMasterInit(unsigned long ulBase, tBoolean bFast) -{ - unsigned long ulSysClk; - unsigned long ulSCLFreq; - unsigned long ulTPR; - - // - // Check the arguments. - // - ASSERT(ulBase == I2C_MASTER_BASE); - - // - // Must enable the device before doing anything else. - // - I2CMasterEnable(ulBase); - - // - // Get the system clock speed. - // - ulSysClk = SysCtlClockGet(); - - // - // Get the desired SCL speed. - // - if(bFast == true) - { - ulSCLFreq = I2C_SCL_FAST; - } - else - { - ulSCLFreq = I2C_SCL_STANDARD; - } - - // - // Compute the clock divider that achieves the fastest speed less than or - // equal to the desired speed. The numerator is biases to favor a larger - // clock divider so that the resulting clock is always less than or equal - // to the desired clock, never greater. - // - ulTPR = (((ulSysClk + (2 * I2C_MASTER_TPR_SCL * ulSCLFreq) - 1) / - (2 * I2C_MASTER_TPR_SCL * ulSCLFreq)) - 1); - HWREG(ulBase + I2C_MASTER_O_TPR) = ulTPR; -} -#endif - -//***************************************************************************** -// -//! Initializes the I2C Slave block. -//! -//! \param ulBase base address of the I2C Slave module -//! \param ucSlaveAddr 7-bit slave address -//! -//! This function initializes operation of the I2C Slave block. Upon -//! successful initialization of the I2C blocks, this function will have -//! set the slave address and have enabled the I2C Slave block. -//! -//! The parameter \e ucSlaveAddr is the value that will be compared -//! against the slave address sent by an I2C master. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_slaveinit) || defined(BUILD_ALL) || defined(DOXYGEN) -void -I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_SLAVE_BASE); - ASSERT(!(ucSlaveAddr & 0x80)); - - // - // Must enable the device before doing anything else. - // - I2CSlaveEnable(ulBase); - - // - // Set up the slave address. - // - HWREG(ulBase + I2C_SLAVE_O_OAR) = ucSlaveAddr; -} -#endif - -//***************************************************************************** -// -//! Enables the I2C Master block. -//! -//! \param ulBase base address of the I2C Master module -//! -//! This will enable operation of the I2C Master block. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_masterenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -I2CMasterEnable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_MASTER_BASE); - - // - // Enable the master block. - // - HWREG(ulBase + I2C_MASTER_O_CR) |= I2C_MASTER_CR_MFE; -} -#endif - -//***************************************************************************** -// -//! Enables the I2C Slave block. -//! -//! \param ulBase base address of the I2C Slave module -//! -//! This will enable operation of the I2C Slave block. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_slaveenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -I2CSlaveEnable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_SLAVE_BASE); - - // - // Enable the clock to the slave block. - // - HWREG(ulBase - I2C_O_SLAVE + I2C_MASTER_O_CR) |= I2C_MASTER_CR_SFE; - - // - // Enable the slave. - // - HWREG(ulBase + I2C_SLAVE_O_CSR) = I2C_SLAVE_CSR_DA; -} -#endif - -//***************************************************************************** -// -//! Disables the I2C master block. -//! -//! \param ulBase base address of the I2C Master module -//! -//! This will disable operation of the I2C master block. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_masterdisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -I2CMasterDisable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_MASTER_BASE); - - // - // Disable the master block. - // - HWREG(ulBase + I2C_MASTER_O_CR) &= ~(I2C_MASTER_CR_MFE); -} -#endif - -//***************************************************************************** -// -//! Disables the I2C slave block. -//! -//! \param ulBase base address of the I2C Slave module -//! -//! This will disable operation of the I2C slave block. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_slavedisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -I2CSlaveDisable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_SLAVE_BASE); - - // - // Disable the slave. - // - HWREG(ulBase + I2C_SLAVE_O_CSR) = 0; - - // - // Disable the clock to the slave block. - // - HWREG(ulBase - I2C_O_SLAVE + I2C_MASTER_O_CR) &= ~(I2C_MASTER_CR_SFE); -} -#endif - -//***************************************************************************** -// -//! Registers an interrupt handler for the I2C module -//! -//! \param ulBase base address of the I2C module -//! \param pfnHandler is a pointer to the function to be called when the -//! synchronous serial interface interrupt occurs. -//! -//! This sets the handler to be called when an I2C interrupt occurs. This -//! will enable the global interrupt in the interrupt controller; specific I2C -//! interrupts must be enabled via I2CMasterIntEnable() and -//! I2CSlaveIntEnable(). If necessary, it is the interrupt handler's -//! responsibility to clear the interrupt source via I2CMasterIntClear() and -//! I2CSlaveIntClear(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -I2CIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_MASTER_BASE); - - // - // Register the interrupt handler, returning an error if an error occurs. - // - IntRegister(INT_I2C, pfnHandler); - - // - // Enable the I2C interrupt. - // - IntEnable(INT_I2C); -} -#endif - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the I2C module. -//! -//! \param ulBase base address of the I2C module -//! -//! This function will clear the handler to be called when an I2C -//! interrupt occurs. This will also mask off the interrupt in the interrupt -//! controller so that the interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -I2CIntUnregister(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_MASTER_BASE); - - // - // Disable the interrupt. - // - IntDisable(INT_I2C); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_I2C); -} -#endif - -//***************************************************************************** -// -//! Enables the I2C Master interrupt. -//! -//! \param ulBase base address of the I2C Master module -//! -//! Enables the I2C Master interrupt source. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_masterintenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -I2CMasterIntEnable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_MASTER_BASE); - - // - // Enable the master interrupt. - // - HWREG(ulBase + I2C_MASTER_O_IMR) = 1; -} -#endif - -//***************************************************************************** -// -//! Enables the I2C Slave interrupt. -//! -//! \param ulBase base address of the I2C Slave module -//! -//! Enables the I2C Slave interrupt source. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_slaveintenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -I2CSlaveIntEnable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_SLAVE_BASE); - - // - // Enable the slave interrupt. - // - HWREG(ulBase + I2C_SLAVE_O_IM) = 1; -} -#endif - -//***************************************************************************** -// -//! Disables the I2C Master interrupt. -//! -//! \param ulBase base address of the I2C Master module -//! -//! Disables the I2C Master interrupt source. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_masterintdisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -I2CMasterIntDisable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_MASTER_BASE); - - // - // Disable the master interrupt. - // - HWREG(ulBase + I2C_MASTER_O_IMR) = 0; -} -#endif - -//***************************************************************************** -// -//! Disables the I2C Slave interrupt. -//! -//! \param ulBase base address of the I2C Slave module -//! -//! Disables the I2C Slave interrupt source. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_slaveintdisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -I2CSlaveIntDisable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_SLAVE_BASE); - - // - // Disable the slave interrupt. - // - HWREG(ulBase + I2C_SLAVE_O_IM) = 0; -} -#endif - -//***************************************************************************** -// -//! Gets the current I2C Master interrupt status. -//! -//! \param ulBase base address of the I2C Master module -//! \param bMasked is false if the raw interrupt status is requested and -//! true if the masked interrupt status is requested. -//! -//! This returns the interrupt status for the I2C Master module. -//! Either the raw interrupt status or the status of interrupts that are -//! allowed to reflect to the processor can be returned. -//! -//! \return The current interrupt status, returned as \b true if active -//! or \b false if not active. -// -//***************************************************************************** -#if defined(GROUP_masterintstatus) || defined(BUILD_ALL) || defined(DOXYGEN) -tBoolean -I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_MASTER_BASE); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return((HWREG(ulBase + I2C_MASTER_O_MIS)) ? true : false); - } - else - { - return((HWREG(ulBase + I2C_MASTER_O_RIS)) ? true : false); - } -} -#endif - -//***************************************************************************** -// -//! Gets the current I2C Slave interrupt status. -//! -//! \param ulBase base address of the I2C Slave module -//! \param bMasked is false if the raw interrupt status is requested and -//! true if the masked interrupt status is requested. -//! -//! This returns the interrupt status for the I2C Slave module. -//! Either the raw interrupt status or the status of interrupts that are -//! allowed to reflect to the processor can be returned. -//! -//! \return The current interrupt status, returned as \b true if active -//! or \b false if not active. -// -//***************************************************************************** -#if defined(GROUP_slaveintstatus) || defined(BUILD_ALL) || defined(DOXYGEN) -tBoolean -I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_SLAVE_BASE); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return((HWREG(ulBase + I2C_SLAVE_O_MIS)) ? true : false); - } - else - { - return((HWREG(ulBase + I2C_SLAVE_O_RIS)) ? true : false); - } -} -#endif - -//***************************************************************************** -// -//! Clears I2C Master interrupt sources. -//! -//! \param ulBase base address of the I2C Master module -//! -//! The I2C Master interrupt source is cleared, so that it no longer asserts. -//! This must be done in the interrupt handler to keep it from being called -//! again immediately upon exit. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_masterintclear) || defined(BUILD_ALL) || defined(DOXYGEN) -void -I2CMasterIntClear(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_MASTER_BASE); - - // - // Clear the I2C master interrupt source. - // - HWREG(ulBase + I2C_MASTER_O_MICR) = I2C_MASTER_MICR_IC; - - // - // Workaround for I2C master interrupt clear errata for rev B Stellaris - // devices. For later devices, this write is ignored and therefore - // harmless (other than the slight performance hit). - // - HWREG(ulBase + I2C_MASTER_O_MIS) = I2C_MASTER_MICR_IC; -} -#endif - -//***************************************************************************** -// -//! Clears I2C Slave interrupt sources. -//! -//! \param ulBase base address of the I2C Slave module -//! -//! The I2C Slave interrupt source is cleared, so that it no longer asserts. -//! This must be done in the interrupt handler to keep it from being called -//! again immediately upon exit. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_slaveintclear) || defined(BUILD_ALL) || defined(DOXYGEN) -void -I2CSlaveIntClear(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_SLAVE_BASE); - - // - // Clear the I2C slave interrupt source. - // - HWREG(ulBase + I2C_SLAVE_O_SICR) = I2C_SLAVE_SICR_IC; -} -#endif - -//***************************************************************************** -// -//! Sets the address that the I2C Master will place on the bus. -//! -//! \param ulBase base address of the I2C Master module -//! \param ucSlaveAddr 7-bit slave address -//! \param bReceive flag indicating the type of communication with the slave -//! -//! This function will set the address that the I2C Master will place on the -//! bus when initiating a transaction. When the parameter \e bReceive is set -//! to \b true, the address will indicate that the I2C Master is initiating -//! a read from the slave; otherwise the address will indicate that the I2C -//! Master is initiating a write to the slave. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_masterslaveaddrset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -I2CMasterSlaveAddrSet(unsigned long ulBase, unsigned char ucSlaveAddr, - tBoolean bReceive) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_MASTER_BASE); - ASSERT(!(ucSlaveAddr & 0x80)); - - // - // Set the address of the slave with which the master will communicate. - // - HWREG(ulBase + I2C_MASTER_O_SA) = (ucSlaveAddr << 1) | bReceive; -} -#endif - -//***************************************************************************** -// -//! Indicates whether or not the I2C Master is busy. -//! -//! \param ulBase base address of the I2C Master module -//! -//! This function returns an indication of whether or not the I2C Master is -//! busy transmitting or receiving data. -//! -//! \return Returns \b true if the I2C Master is busy; otherwise, returns -//! \b false. -// -//***************************************************************************** -#if defined(GROUP_masterbusy) || defined(BUILD_ALL) || defined(DOXYGEN) -tBoolean -I2CMasterBusy(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_MASTER_BASE); - - // - // Return the busy status. - // - if(HWREG(ulBase + I2C_MASTER_O_CS) & I2C_MASTER_CS_BUSY) - { - return(true); - } - else - { - return(false); - } -} -#endif - -//***************************************************************************** -// -//! Indicates whether or not the I2C bus is busy. -//! -//! \param ulBase base address of the I2C Master module -//! -//! This function returns an indication of whether or not the I2C bus is -//! busy. This function can be used in a multi-master environment to -//! determine if another master is currently using the bus. -//! -//! \return Returns \b true if the I2C bus is busy; otherwise, returns -//! \b false. -// -//***************************************************************************** -#if defined(GROUP_masterbusbusy) || defined(BUILD_ALL) || defined(DOXYGEN) -tBoolean -I2CMasterBusBusy(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_MASTER_BASE); - - // - // Return the bus busy status. - // - if(HWREG(ulBase + I2C_MASTER_O_CS) & I2C_MASTER_CS_BUS_BUSY) - { - return(true); - } - else - { - return(false); - } -} -#endif - -//***************************************************************************** -// -//! Controls the state of the I2C Master module. -//! -//! \param ulBase base address of the I2C Master module -//! \param ulCmd command to be issued to the I2C Master module -//! -//! This function is used to control the state of the Master module send and -//! receive operations. The parameter \e ucCmd can be one of the following -//! values: -//! -//! - I2C_MASTER_CMD_SINGLE_SEND -//! - I2C_MASTER_CMD_SINGLE_RECEIVE -//! - I2C_MASTER_CMD_BURST_SEND_START -//! - I2C_MASTER_CMD_BURST_SEND_CONT -//! - I2C_MASTER_CMD_BURST_SEND_FINISH -//! - I2C_MASTER_CMD_BURST_SEND_ERROR_STOP -//! - I2C_MASTER_CMD_BURST_RECEIVE_START -//! - I2C_MASTER_CMD_BURST_RECEIVE_CONT -//! - I2C_MASTER_CMD_BURST_RECEIVE_FINISH -//! - I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_mastercontrol) || defined(BUILD_ALL) || defined(DOXYGEN) -void -I2CMasterControl(unsigned long ulBase, unsigned long ulCmd) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_MASTER_BASE); - ASSERT((ulCmd == I2C_MASTER_CMD_SINGLE_SEND) || - (ulCmd == I2C_MASTER_CMD_SINGLE_RECEIVE) || - (ulCmd == I2C_MASTER_CMD_BURST_SEND_START) || - (ulCmd == I2C_MASTER_CMD_BURST_SEND_CONT) || - (ulCmd == I2C_MASTER_CMD_BURST_SEND_FINISH) || - (ulCmd == I2C_MASTER_CMD_BURST_SEND_ERROR_STOP) || - (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_START) || - (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_CONT) || - (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_FINISH) || - (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP)); - - // - // Send the command. - // - HWREG(ulBase + I2C_MASTER_O_CS) = ulCmd; -} -#endif - -//***************************************************************************** -// -//! Gets the error status of the I2C Master module. -//! -//! \param ulBase base address of the I2C Master module -//! -//! This function is used to obtain the error status of the Master module -//! send and receive operations. It returns one of the following values: -//! -//! - I2C_MASTER_ERR_NONE -//! - I2C_MASTER_ERR_ADDR_ACK -//! - I2C_MASTER_ERR_DATA_ACK -//! - I2C_MASTER_ERR_ARB_LOST -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_mastererr) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -I2CMasterErr(unsigned long ulBase) -{ - unsigned long ulErr; - - // - // Check the arguments. - // - ASSERT(ulBase == I2C_MASTER_BASE); - - // - // Get the raw error state - // - ulErr = HWREG(ulBase + I2C_MASTER_O_CS); - - // - // If the I2C master is busy, then all the other bit are invalid, and - // don't have an error to report. - // - if(ulErr & I2C_MASTER_CS_BUSY) - { - return(I2C_MASTER_ERR_NONE); - } - - // - // Check for errors. - // - if(ulErr & I2C_MASTER_CS_ERROR) - { - return(ulErr & (I2C_MASTER_CS_ERR_MASK)); - } - else - { - return(I2C_MASTER_ERR_NONE); - } -} -#endif - -//***************************************************************************** -// -//! Transmits a byte from the I2C Master. -//! -//! \param ulBase base address of the I2C Master module -//! \param ucData data to be transmitted from the I2C Master -//! -//! This function will place the supplied data into I2C Master Data Register. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_masterdataput) || defined(BUILD_ALL) || defined(DOXYGEN) -void -I2CMasterDataPut(unsigned long ulBase, unsigned char ucData) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_MASTER_BASE); - - // - // Write the byte. - // - HWREG(ulBase + I2C_MASTER_O_DR) = ucData; -} -#endif - -//***************************************************************************** -// -//! Receives a byte that has been sent to the I2C Master. -//! -//! \param ulBase base address of the I2C Master module -//! -//! This function reads a byte of data from the I2C Master Data Register. -//! -//! \return Returns the byte received from by the I2C Master, cast as an -//! unsigned long. -// -//***************************************************************************** -#if defined(GROUP_masterdataget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -I2CMasterDataGet(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_MASTER_BASE); - - // - // Read a byte. - // - return(HWREG(ulBase + I2C_MASTER_O_DR)); -} -#endif - -//***************************************************************************** -// -//! Gets the I2C Slave module status -//! -//! \param ulBase base address of the I2C Slave module -//! -//! This function will return the action requested from a master, if any. The -//! possible values returned are: -//! -//! - I2C_SLAVE_ACT_NONE -//! - I2C_SLAVE_ACT_RREQ -//! - I2C_SLAVE_ACT_TREQ -//! -//! where I2C_SLAVE_ACT_NONE means that no action has been requested of the -//! I2C Slave module, I2C_SLAVE_ACT_RREQ means that an I2C master has sent -//! data to the I2C Slave module, and I2C_SLAVE_ACT_TREQ means that an I2C -//! master has requested that the I2C Slave module send data. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_slavestatus) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -I2CSlaveStatus(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_SLAVE_BASE); - - // - // Return the slave status. - // - return(HWREG(ulBase + I2C_SLAVE_O_CSR)); -} -#endif - -//***************************************************************************** -// -//! Transmits a byte from the I2C Slave. -//! -//! \param ulBase base address of the I2C Slave module -//! \param ucData data to be transmitted from the I2C Slave -//! -//! This function will place the supplied data into I2C Slave Data Register. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_slavedataput) || defined(BUILD_ALL) || defined(DOXYGEN) -void -I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_SLAVE_BASE); - - // - // Write the byte. - // - HWREG(ulBase + I2C_SLAVE_O_DR) = ucData; -} -#endif - -//***************************************************************************** -// -//! Receives a byte that has been sent to the I2C Slave. -//! -//! \param ulBase base address of the I2C Slave module -//! -//! This function reads a byte of data from the I2C Slave Data Register. -//! -//! \return Returns the byte received from by the I2C Slave, cast as an -//! unsigned long. -// -//***************************************************************************** -#if defined(GROUP_slavedataget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -I2CSlaveDataGet(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == I2C_SLAVE_BASE); - - // - // Read a byte. - // - return(HWREG(ulBase + I2C_SLAVE_O_DR)); -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/i2c.h b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/i2c.h deleted file mode 100644 index bfe8c8563..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/i2c.h +++ /dev/null @@ -1,137 +0,0 @@ -//***************************************************************************** -// -// i2c.h - Prototypes for the I2C Driver. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __I2C_H__ -#define __I2C_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Defines for the API. -// -//***************************************************************************** -//***************************************************************************** -// -// Interrupt defines. -// -//***************************************************************************** -#define I2C_INT_MASTER 0x00000001 -#define I2C_INT_SLAVE 0x00000002 - -//***************************************************************************** -// -// I2C Master commands. -// -//***************************************************************************** -#define I2C_MASTER_CMD_SINGLE_SEND \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_SINGLE_RECEIVE \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_SEND_START \ - (I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_SEND_CONT \ - (I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_SEND_FINISH \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ - (I2C_MASTER_CS_STOP) -#define I2C_MASTER_CMD_BURST_RECEIVE_START \ - (I2C_MASTER_CS_ACK | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ - (I2C_MASTER_CS_ACK | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) - -//***************************************************************************** -// -// I2C Master error status. -// -//***************************************************************************** -#define I2C_MASTER_ERR_NONE 0 -#define I2C_MASTER_ERR_ADDR_ACK 0x00000004 -#define I2C_MASTER_ERR_DATA_ACK 0x00000008 -#define I2C_MASTER_ERR_ARB_LOST 0x00000010 - -//***************************************************************************** -// -// I2C Slave action requests -// -//***************************************************************************** -#define I2C_SLAVE_ACT_NONE 0 -#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data -#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data - -//***************************************************************************** -// Miscellaneous I2C driver definitions. -//***************************************************************************** -#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void)); -extern void I2CIntUnregister(unsigned long ulBase); -extern tBoolean I2CMasterBusBusy(unsigned long ulBase); -extern tBoolean I2CMasterBusy(unsigned long ulBase); -extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd); -extern unsigned long I2CMasterDataGet(unsigned long ulBase); -extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData); -extern void I2CMasterDisable(unsigned long ulBase); -extern void I2CMasterEnable(unsigned long ulBase); -extern unsigned long I2CMasterErr(unsigned long ulBase); -extern void I2CMasterInit(unsigned long ulBase, tBoolean bFast); -extern void I2CMasterIntClear(unsigned long ulBase); -extern void I2CMasterIntDisable(unsigned long ulBase); -extern void I2CMasterIntEnable(unsigned long ulBase); -extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void I2CMasterSlaveAddrSet(unsigned long ulBase, - unsigned char ucSlaveAddr, - tBoolean bReceive); -extern unsigned long I2CSlaveDataGet(unsigned long ulBase); -extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData); -extern void I2CSlaveDisable(unsigned long ulBase); -extern void I2CSlaveEnable(unsigned long ulBase); -extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr); -extern void I2CSlaveIntClear(unsigned long ulBase); -extern void I2CSlaveIntDisable(unsigned long ulBase); -extern void I2CSlaveIntEnable(unsigned long ulBase); -extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked); -extern unsigned long I2CSlaveStatus(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __I2C_H__ diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/interrupt.c b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/interrupt.c deleted file mode 100644 index 7224a05d8..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/interrupt.c +++ /dev/null @@ -1,552 +0,0 @@ -//***************************************************************************** -// -// interrupt.c - Driver for the NVIC Interrupt Controller. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup interrupt_api -//! @{ -// -//***************************************************************************** - -#include "../hw_ints.h" -#include "../hw_nvic.h" -#include "../hw_types.h" -#include "cpu.h" -#include "debug.h" -#include "interrupt.h" - -//***************************************************************************** -// -// This is a mapping between priority grouping encodings and the number of -// preemption priority bits. -// -//***************************************************************************** -#if defined(GROUP_pulpriority) || defined(BUILD_ALL) -const unsigned long g_pulPriority[] = -{ - NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6, - NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4, NVIC_APINT_PRIGROUP_5_3, - NVIC_APINT_PRIGROUP_6_2, NVIC_APINT_PRIGROUP_7_1 -}; -#else -extern const unsigned long g_pulPriority[]; -#endif - -//***************************************************************************** -// -// This is a mapping between interrupt number and the register that contains -// the priority encoding for that interrupt. -// -//***************************************************************************** -#if defined(GROUP_pulregs) || defined(BUILD_ALL) -const unsigned long g_pulRegs[12] = -{ - 0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1, - NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7 -}; -#else -extern const unsigned long g_pulRegs[12]; -#endif - -//***************************************************************************** -// -//! \internal -//! The default interrupt handler. -//! -//! This is the default interrupt handler for all interrupts. It simply loops -//! forever so that the system state is preserved for observation by a -//! debugger. Since interrupts should be disabled before unregistering the -//! corresponding handler, this should never be called. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_defaulthandler) || defined(BUILD_ALL) -void -IntDefaultHandler(void) -{ - // - // Go into an infinite loop. - // - while(1) - { - } -} -#else -extern void IntDefaultHandler(void); -#endif - -//***************************************************************************** -// -// The processor vector table. -// -// This contains a list of the handlers for the various interrupt sources in -// the system. The layout of this list is defined by the hardware; assertion -// of an interrupt causes the processor to start executing directly at the -// address given in the corresponding location in this list. -// -//***************************************************************************** -#if defined(GROUP_vtable) || defined(BUILD_ALL) -#ifdef ewarm -__no_init void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) @ "VTABLE"; -#else -__attribute__((section("vtable"))) -void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void); -#endif -#else -extern void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void); -#endif - -//***************************************************************************** -// -//! Enables the processor interrupt. -//! -//! Allows the processor to respond to interrupts. This does not affect the -//! set of interrupts enabled in the interrupt controller; it just gates the -//! single interrupt from the controller to the processor. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_masterenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -IntMasterEnable(void) -{ - // - // Enable processor interrupts. - // - CPUcpsie(); -} -#endif - -//***************************************************************************** -// -//! Disables the processor interrupt. -//! -//! Prevents the processor from receiving interrupts. This does not affect the -//! set of interrupts enabled in the interrupt controller; it just gates the -//! single interrupt from the controller to the processor. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_masterdisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -IntMasterDisable(void) -{ - // - // Disable processor interrupts. - // - CPUcpsid(); -} -#endif - -//***************************************************************************** -// -//! Registers a function to be called when an interrupt occurs. -//! -//! \param ulInterrupt specifies the interrupt in question. -//! \param pfnHandler is a pointer to the function to be called. -//! -//! This function is used to specify the handler function to be called when the -//! given interrupt is asserted to the processor. When the interrupt occurs, -//! if it is enabled (via IntEnable()), the handler function will be called in -//! interrupt context. Since the handler function can preempt other code, care -//! must be taken to protect memory or peripherals that are accessed by the -//! handler and other non-handler code. -//! -//! \note The use of this function (directly or indirectly via a peripheral -//! driver interrupt register function) moves the interrupt vector table from -//! flash to SRAM. Therefore, care must be taken when linking the application -//! to ensure that the SRAM vector table is located at the beginning of SRAM; -//! otherwise NVIC will not look in the correct portion of memory for the -//! vector table (it requires the vector table be on a 1 kB memory alignment). -//! Normally, the SRAM vector table is so placed via the use of linker scripts; -//! some tool chains, such as the evaluation version of RV-MDK, do not support -//! linker scripts and therefore will not produce a valid executable. See the -//! discussion of compile-time versus run-time interrupt handler registration -//! in the introduction to this chapter. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_register) || defined(BUILD_ALL) || defined(DOXYGEN) -void -IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)) -{ - unsigned long ulIdx; - - // - // Check the arguments. - // - ASSERT(ulInterrupt < NUM_INTERRUPTS); - - // - // Make sure that the RAM vector table is correctly aligned. - // - ASSERT(((unsigned long)g_pfnRAMVectors & 0x000003ff) == 0); - - // - // See if the RAM vector table has been initialized. - // - if(HWREG(NVIC_VTABLE) != (unsigned long)g_pfnRAMVectors) - { - // - // Copy the vector table from the beginning of FLASH to the RAM vector - // table. - // - for(ulIdx = 0; ulIdx < NUM_INTERRUPTS; ulIdx++) - { - g_pfnRAMVectors[ulIdx] = (void (*)(void))HWREG(ulIdx * 4); - } - - // - // Point NVIC at the RAM vector table. - // - HWREG(NVIC_VTABLE) = (unsigned long)g_pfnRAMVectors; - } - - // - // Save the interrupt handler. - // - g_pfnRAMVectors[ulInterrupt] = pfnHandler; -} -#endif - -//***************************************************************************** -// -//! Unregisters the function to be called when an interrupt occurs. -//! -//! \param ulInterrupt specifies the interrupt in question. -//! -//! This function is used to indicate that no handler should be called when the -//! given interrupt is asserted to the processor. The interrupt source will be -//! automatically disabled (via IntDisable()) if necessary. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_unregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -IntUnregister(unsigned long ulInterrupt) -{ - // - // Check the arguments. - // - ASSERT(ulInterrupt < NUM_INTERRUPTS); - - // - // Reset the interrupt handler. - // - g_pfnRAMVectors[ulInterrupt] = IntDefaultHandler; -} -#endif - -//***************************************************************************** -// -//! Sets the priority grouping of the interrupt controller. -//! -//! \param ulBits specifies the number of bits of preemptable priority. -//! -//! This function specifies the split between preemptable priority levels and -//! subpriority levels in the interrupt priority specification. The range of -//! the grouping values are dependent upon the hardware implementation; on -//! the Stellaris family it can range from 0 to 3. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_prioritygroupingset) || defined(BUILD_ALL) || \ - defined(DOXYGEN) -void -IntPriorityGroupingSet(unsigned long ulBits) -{ - // - // Check the arguments. - // - ASSERT(ulBits < NUM_PRIORITY_BITS); - - // - // Set the priority grouping. - // - HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pulPriority[ulBits]; -} -#endif - -//***************************************************************************** -// -//! Gets the priority grouping of the interrupt controller. -//! -//! This function returns the split between preemptable priority levels and -//! subpriority levels in the interrupt priority specification. -//! -//! \return The number of bits of preemptable priority. -// -//***************************************************************************** -#if defined(GROUP_prioritygroupingget) || defined(BUILD_ALL) || \ - defined(DOXYGEN) -unsigned long -IntPriorityGroupingGet(void) -{ - unsigned long ulLoop, ulValue; - - // - // Read the priority grouping. - // - ulValue = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M; - - // - // Loop through the priority grouping values. - // - for(ulLoop = 0; ulLoop < 8; ulLoop++) - { - // - // Stop looping if this value matches. - // - if(ulValue == g_pulPriority[ulLoop]) - { - break; - } - } - - // - // Return the number of priority bits. - // - return(ulLoop); -} -#endif - -//***************************************************************************** -// -//! Sets the priority of an interrupt. -//! -//! \param ulInterrupt specifies the interrupt in question. -//! \param ucPriority specifies the priority of the interrupt. -//! -//! This function is used to set the priority of an interrupt. When multiple -//! interrupts are asserted simultaneously, the ones with the highest priority -//! are processed before the lower priority interrupts. Smaller numbers -//! correspond to higher interrupt priorities; priority 0 is the highest -//! interrupt priority. -//! -//! The hardware priority mechanism will only look at the upper N bits of the -//! priority level (where N is 3 for the Stellaris family), so any -//! prioritization must be performed in those bits. The remaining bits can be -//! used to sub-prioritize the interrupt sources, and may be used by the -//! hardware priority mechanism on a future part. This arrangement allows -//! priorities to migrate to different NVIC implementations without changing -//! the gross prioritization of the interrupts. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_priorityset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -IntPrioritySet(unsigned long ulInterrupt, unsigned char ucPriority) -{ - unsigned long ulTemp; - - // - // Check the arguments. - // - ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS)); - - // - // Set the interrupt priority. - // - ulTemp = HWREG(g_pulRegs[ulInterrupt >> 2]); - ulTemp &= ~(0xFF << (8 * (ulInterrupt & 3))); - ulTemp |= ucPriority << (8 * (ulInterrupt & 3)); - HWREG(g_pulRegs[ulInterrupt >> 2]) = ulTemp; -} -#endif - -//***************************************************************************** -// -//! Gets the priority of an interrupt. -//! -//! \param ulInterrupt specifies the interrupt in question. -//! -//! This function gets the priority of an interrupt. See IntPrioritySet() for -//! a definition of the priority value. -//! -//! \return Returns the interrupt priority, or -1 if an invalid interrupt was -//! specified. -// -//***************************************************************************** -#if defined(GROUP_priorityget) || defined(BUILD_ALL) || defined(DOXYGEN) -long -IntPriorityGet(unsigned long ulInterrupt) -{ - // - // Check the arguments. - // - ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS)); - - // - // Return the interrupt priority. - // - return((HWREG(g_pulRegs[ulInterrupt >> 2]) >> (8 * (ulInterrupt & 3))) & - 0xFF); -} -#endif - -//***************************************************************************** -// -//! Enables an interrupt. -//! -//! \param ulInterrupt specifies the interrupt to be enabled. -//! -//! The specified interrupt is enabled in the interrupt controller. Other -//! enables for the interrupt (such as at the peripheral level) are unaffected -//! by this function. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -IntEnable(unsigned long ulInterrupt) -{ - // - // Check the arguments. - // - ASSERT(ulInterrupt < NUM_INTERRUPTS); - - // - // Determine the interrupt to enable. - // - if(ulInterrupt == FAULT_MPU) - { - // - // Enable the MemManage interrupt. - // - HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM; - } - else if(ulInterrupt == FAULT_BUS) - { - // - // Enable the bus fault interrupt. - // - HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS; - } - else if(ulInterrupt == FAULT_USAGE) - { - // - // Enable the usage fault interrupt. - // - HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE; - } - else if(ulInterrupt == FAULT_SYSTICK) - { - // - // Enable the System Tick interrupt. - // - HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; - } - else if(ulInterrupt >= INT_GPIOA) - { - // - // Enable the general interrupt. - // - HWREG(NVIC_EN0) = 1 << (ulInterrupt - INT_GPIOA); - } -} -#endif - -//***************************************************************************** -// -//! Disables an interrupt. -//! -//! \param ulInterrupt specifies the interrupt to be disabled. -//! -//! The specified interrupt is disabled in the interrupt controller. Other -//! enables for the interrupt (such as at the peripheral level) are unaffected -//! by this function. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -IntDisable(unsigned long ulInterrupt) -{ - // - // Check the arguments. - // - ASSERT(ulInterrupt < NUM_INTERRUPTS); - - // - // Determine the interrupt to disable. - // - if(ulInterrupt == FAULT_MPU) - { - // - // Disable the MemManage interrupt. - // - HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_MEM); - } - else if(ulInterrupt == FAULT_BUS) - { - // - // Disable the bus fault interrupt. - // - HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_BUS); - } - else if(ulInterrupt == FAULT_USAGE) - { - // - // Disable the usage fault interrupt. - // - HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_USAGE); - } - else if(ulInterrupt == FAULT_SYSTICK) - { - // - // Disable the System Tick interrupt. - // - HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); - } - else if(ulInterrupt >= INT_GPIOA) - { - // - // Disable the general interrupt. - // - HWREG(NVIC_DIS0) = 1 << (ulInterrupt - INT_GPIOA); - } -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/interrupt.h b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/interrupt.h deleted file mode 100644 index 37d414dab..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/interrupt.h +++ /dev/null @@ -1,57 +0,0 @@ -//***************************************************************************** -// -// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __INTERRUPT_H__ -#define __INTERRUPT_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void IntMasterEnable(void); -extern void IntMasterDisable(void); -extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)); -extern void IntUnregister(unsigned long ulInterrupt); -extern void IntPriorityGroupingSet(unsigned long ulBits); -extern unsigned long IntPriorityGroupingGet(void); -extern void IntPrioritySet(unsigned long ulInterrupt, - unsigned char ucPriority); -extern long IntPriorityGet(unsigned long ulInterrupt); -extern void IntEnable(unsigned long ulInterrupt); -extern void IntDisable(unsigned long ulInterrupt); - -#ifdef __cplusplus -} -#endif - -#endif // __INTERRUPT_H__ diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/osram96x16.c b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/osram96x16.c deleted file mode 100644 index 54f260d7a..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/osram96x16.c +++ /dev/null @@ -1,968 +0,0 @@ -//***************************************************************************** -// -// osram96x16.c - Driver for the OSRAM 96x16 graphical OLED display. -// -// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup ev_lm3s811_api -//! @{ -// -//***************************************************************************** - -#include "DriverLib.h" -#include "osram96x16.h" -#define ewarm -//***************************************************************************** -// -// The I2C slave address of the SSD0303 controller on the OLED display. -// -//***************************************************************************** -#define SSD0303_ADDR 0x3d - -//***************************************************************************** -// -// A 5x7 font (in a 6x8 cell, where the sixth column is omitted from this -// table) for displaying text on the OLED display. The data is organized as -// bytes from the left column to the right column, with each byte containing -// the top row in the LSB and the bottom row in the MSB. -// -//***************************************************************************** -static const unsigned char g_pucFont[95][5] = -{ - { 0x00, 0x00, 0x00, 0x00, 0x00 }, // " " - { 0x00, 0x00, 0x4f, 0x00, 0x00 }, // ! - { 0x00, 0x07, 0x00, 0x07, 0x00 }, // " - { 0x14, 0x7f, 0x14, 0x7f, 0x14 }, // # - { 0x24, 0x2a, 0x7f, 0x2a, 0x12 }, // $ - { 0x23, 0x13, 0x08, 0x64, 0x62 }, // % - { 0x36, 0x49, 0x55, 0x22, 0x50 }, // & - { 0x00, 0x05, 0x03, 0x00, 0x00 }, // ' - { 0x00, 0x1c, 0x22, 0x41, 0x00 }, // ( - { 0x00, 0x41, 0x22, 0x1c, 0x00 }, // ) - { 0x14, 0x08, 0x3e, 0x08, 0x14 }, // * - { 0x08, 0x08, 0x3e, 0x08, 0x08 }, // + - { 0x00, 0x50, 0x30, 0x00, 0x00 }, // , - { 0x08, 0x08, 0x08, 0x08, 0x08 }, // - - { 0x00, 0x60, 0x60, 0x00, 0x00 }, // . - { 0x20, 0x10, 0x08, 0x04, 0x02 }, // / - { 0x3e, 0x51, 0x49, 0x45, 0x3e }, // 0 - { 0x00, 0x42, 0x7f, 0x40, 0x00 }, // 1 - { 0x42, 0x61, 0x51, 0x49, 0x46 }, // 2 - { 0x21, 0x41, 0x45, 0x4b, 0x31 }, // 3 - { 0x18, 0x14, 0x12, 0x7f, 0x10 }, // 4 - { 0x27, 0x45, 0x45, 0x45, 0x39 }, // 5 - { 0x3c, 0x4a, 0x49, 0x49, 0x30 }, // 6 - { 0x01, 0x71, 0x09, 0x05, 0x03 }, // 7 - { 0x36, 0x49, 0x49, 0x49, 0x36 }, // 8 - { 0x06, 0x49, 0x49, 0x29, 0x1e }, // 9 - { 0x00, 0x36, 0x36, 0x00, 0x00 }, // : - { 0x00, 0x56, 0x36, 0x00, 0x00 }, // ; - { 0x08, 0x14, 0x22, 0x41, 0x00 }, // < - { 0x14, 0x14, 0x14, 0x14, 0x14 }, // = - { 0x00, 0x41, 0x22, 0x14, 0x08 }, // > - { 0x02, 0x01, 0x51, 0x09, 0x06 }, // ? - { 0x32, 0x49, 0x79, 0x41, 0x3e }, // @ - { 0x7e, 0x11, 0x11, 0x11, 0x7e }, // A - { 0x7f, 0x49, 0x49, 0x49, 0x36 }, // B - { 0x3e, 0x41, 0x41, 0x41, 0x22 }, // C - { 0x7f, 0x41, 0x41, 0x22, 0x1c }, // D - { 0x7f, 0x49, 0x49, 0x49, 0x41 }, // E - { 0x7f, 0x09, 0x09, 0x09, 0x01 }, // F - { 0x3e, 0x41, 0x49, 0x49, 0x7a }, // G - { 0x7f, 0x08, 0x08, 0x08, 0x7f }, // H - { 0x00, 0x41, 0x7f, 0x41, 0x00 }, // I - { 0x20, 0x40, 0x41, 0x3f, 0x01 }, // J - { 0x7f, 0x08, 0x14, 0x22, 0x41 }, // K - { 0x7f, 0x40, 0x40, 0x40, 0x40 }, // L - { 0x7f, 0x02, 0x0c, 0x02, 0x7f }, // M - { 0x7f, 0x04, 0x08, 0x10, 0x7f }, // N - { 0x3e, 0x41, 0x41, 0x41, 0x3e }, // O - { 0x7f, 0x09, 0x09, 0x09, 0x06 }, // P - { 0x3e, 0x41, 0x51, 0x21, 0x5e }, // Q - { 0x7f, 0x09, 0x19, 0x29, 0x46 }, // R - { 0x46, 0x49, 0x49, 0x49, 0x31 }, // S - { 0x01, 0x01, 0x7f, 0x01, 0x01 }, // T - { 0x3f, 0x40, 0x40, 0x40, 0x3f }, // U - { 0x1f, 0x20, 0x40, 0x20, 0x1f }, // V - { 0x3f, 0x40, 0x38, 0x40, 0x3f }, // W - { 0x63, 0x14, 0x08, 0x14, 0x63 }, // X - { 0x07, 0x08, 0x70, 0x08, 0x07 }, // Y - { 0x61, 0x51, 0x49, 0x45, 0x43 }, // Z - { 0x00, 0x7f, 0x41, 0x41, 0x00 }, // [ - { 0x02, 0x04, 0x08, 0x10, 0x20 }, // "\" - { 0x00, 0x41, 0x41, 0x7f, 0x00 }, // ] - { 0x04, 0x02, 0x01, 0x02, 0x04 }, // ^ - { 0x40, 0x40, 0x40, 0x40, 0x40 }, // _ - { 0x00, 0x01, 0x02, 0x04, 0x00 }, // ` - { 0x20, 0x54, 0x54, 0x54, 0x78 }, // a - { 0x7f, 0x48, 0x44, 0x44, 0x38 }, // b - { 0x38, 0x44, 0x44, 0x44, 0x20 }, // c - { 0x38, 0x44, 0x44, 0x48, 0x7f }, // d - { 0x38, 0x54, 0x54, 0x54, 0x18 }, // e - { 0x08, 0x7e, 0x09, 0x01, 0x02 }, // f - { 0x0c, 0x52, 0x52, 0x52, 0x3e }, // g - { 0x7f, 0x08, 0x04, 0x04, 0x78 }, // h - { 0x00, 0x44, 0x7d, 0x40, 0x00 }, // i - { 0x20, 0x40, 0x44, 0x3d, 0x00 }, // j - { 0x7f, 0x10, 0x28, 0x44, 0x00 }, // k - { 0x00, 0x41, 0x7f, 0x40, 0x00 }, // l - { 0x7c, 0x04, 0x18, 0x04, 0x78 }, // m - { 0x7c, 0x08, 0x04, 0x04, 0x78 }, // n - { 0x38, 0x44, 0x44, 0x44, 0x38 }, // o - { 0x7c, 0x14, 0x14, 0x14, 0x08 }, // p - { 0x08, 0x14, 0x14, 0x18, 0x7c }, // q - { 0x7c, 0x08, 0x04, 0x04, 0x08 }, // r - { 0x48, 0x54, 0x54, 0x54, 0x20 }, // s - { 0x04, 0x3f, 0x44, 0x40, 0x20 }, // t - { 0x3c, 0x40, 0x40, 0x20, 0x7c }, // u - { 0x1c, 0x20, 0x40, 0x20, 0x1c }, // v - { 0x3c, 0x40, 0x30, 0x40, 0x3c }, // w - { 0x44, 0x28, 0x10, 0x28, 0x44 }, // x - { 0x0c, 0x50, 0x50, 0x50, 0x3c }, // y - { 0x44, 0x64, 0x54, 0x4c, 0x44 }, // z - { 0x00, 0x08, 0x36, 0x41, 0x00 }, // { - { 0x00, 0x00, 0x7f, 0x00, 0x00 }, // | - { 0x00, 0x41, 0x36, 0x08, 0x00 }, // } - { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~ -}; - -//***************************************************************************** -// -// The sequence of commands used to initialize the SSD0303 controller. Each -// command is described as follows: there is a byte specifying the number of -// bytes in the I2C transfer, followed by that many bytes of command data. -// -//***************************************************************************** -static const unsigned char g_pucOSRAMInit[] = -{ - // - // Turn off the panel - // - 0x04, 0x80, 0xae, 0x80, 0xe3, - - // - // Set lower column address - // - 0x04, 0x80, 0x04, 0x80, 0xe3, - - // - // Set higher column address - // - 0x04, 0x80, 0x12, 0x80, 0xe3, - - // - // Set contrast control register - // - 0x06, 0x80, 0x81, 0x80, 0x2b, 0x80, 0xe3, - - // - // Set segment re-map - // - 0x04, 0x80, 0xa1, 0x80, 0xe3, - - // - // Set display start line - // - 0x04, 0x80, 0x40, 0x80, 0xe3, - - // - // Set display offset - // - 0x06, 0x80, 0xd3, 0x80, 0x00, 0x80, 0xe3, - - // - // Set multiplex ratio - // - 0x06, 0x80, 0xa8, 0x80, 0x0f, 0x80, 0xe3, - - // - // Set the display to normal mode - // - 0x04, 0x80, 0xa4, 0x80, 0xe3, - - // - // Non-inverted display - // - 0x04, 0x80, 0xa6, 0x80, 0xe3, - - // - // Set the page address - // - 0x04, 0x80, 0xb0, 0x80, 0xe3, - - // - // Set COM output scan direction - // - 0x04, 0x80, 0xc8, 0x80, 0xe3, - - // - // Set display clock divide ratio/oscillator frequency - // - 0x06, 0x80, 0xd5, 0x80, 0x72, 0x80, 0xe3, - - // - // Enable mono mode - // - 0x06, 0x80, 0xd8, 0x80, 0x00, 0x80, 0xe3, - - // - // Set pre-charge period - // - 0x06, 0x80, 0xd9, 0x80, 0x22, 0x80, 0xe3, - - // - // Set COM pins hardware configuration - // - 0x06, 0x80, 0xda, 0x80, 0x12, 0x80, 0xe3, - - // - // Set VCOM deslect level - // - 0x06, 0x80, 0xdb, 0x80, 0x0f, 0x80, 0xe3, - - // - // Set DC-DC on - // - 0x06, 0x80, 0xad, 0x80, 0x8b, 0x80, 0xe3, - - // - // Turn on the panel - // - 0x04, 0x80, 0xaf, 0x80, 0xe3, -}; - -//***************************************************************************** -// -// The inter-byte delay required by the SSD0303 OLED controller. -// -//***************************************************************************** -static unsigned long g_ulDelay; - -//***************************************************************************** -// -//! \internal -//! -//! Provide a small delay. -//! -//! \param ulCount is the number of delay loop iterations to perform. -//! -//! Since the SSD0303 controller needs a delay between bytes written to it over -//! the I2C bus, this function provides a means of generating that delay. It -//! is written in assembly to keep the delay consistent across tool chains, -//! avoiding the need to tune the delay based on the tool chain in use. -//! -//! \return None. -// -//***************************************************************************** -#if defined(ewarm) -static void -OSRAMDelay(unsigned long ulCount) -{ - __asm(" subs r0, #1\n" - " bne OSRAMDelay\n" - " bx lr"); -} -#endif -#if defined(gcc) -static void __attribute__((naked)) -OSRAMDelay(unsigned long ulCount) -{ - __asm(" subs r0, #1\n" - " bne OSRAMDelay\n" - " bx lr"); -} -#endif -#if defined(rvmdk) || defined(__ARMCC_VERSION) -__asm void -OSRAMDelay(unsigned long ulCount) -{ - subs r0, #1; - bne OSRAMDelay; - bx lr; -} -#endif - -//***************************************************************************** -// -//! \internal -//! -//! Start a transfer to the SSD0303 controller. -//! -//! \param ucChar is the first byte to be written to the controller. -//! -//! This function will start a transfer to the SSD0303 controller via the I2C -//! bus. -//! -//! The data is written in a polled fashion; this function will not return -//! until the byte has been written to the controller. -//! -//! \return None. -// -//***************************************************************************** -static void -OSRAMWriteFirst(unsigned char ucChar) -{ - // - // Set the slave address. - // - I2CMasterSlaveAddrSet(I2C_MASTER_BASE, SSD0303_ADDR, false); - - // - // Write the first byte to the controller. - // - I2CMasterDataPut(I2C_MASTER_BASE, ucChar); - - // - // Start the transfer. - // - I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_START); -} - -//***************************************************************************** -// -//! \internal -//! -//! Write a byte to the SSD0303 controller. -//! -//! \param ucChar is the byte to be transmitted to the controller. -//! -//! This function continues a transfer to the SSD0303 controller by writing -//! another byte over the I2C bus. This must only be called after calling -//! OSRAMWriteFirst(), but before calling OSRAMWriteFinal(). -//! -//! The data is written in a polled faashion; this function will not return -//! until the byte has been written to the controller. -//! -//! \return None. -// -//***************************************************************************** -static void -OSRAMWriteByte(unsigned char ucChar) -{ - // - // Wait until the current byte has been transferred. - // - while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0) - { - } - - // - // Provide the required inter-byte delay. - // - OSRAMDelay(g_ulDelay); - - // - // Write the next byte to the controller. - // - I2CMasterDataPut(I2C_MASTER_BASE, ucChar); - - // - // Continue the transfer. - // - I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_CONT); -} - -//***************************************************************************** -// -//! \internal -//! -//! Write a sequence of bytes to the SSD0303 controller. -//! -//! This function continues a transfer to the SSD0303 controller by writing a -//! sequence of bytes over the I2C bus. This must only be called after calling -//! OSRAMWriteFirst(), but before calling OSRAMWriteFinal(). -//! -//! The data is written in a polled fashion; this function will not return -//! until the entire byte sequence has been written to the controller. -//! -//! \return None. -// -//***************************************************************************** -static void -OSRAMWriteArray(const unsigned char *pucBuffer, unsigned long ulCount) -{ - // - // Loop while there are more bytes left to be transferred. - // - while(ulCount != 0) - { - // - // Wait until the current byte has been transferred. - // - while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0) - { - } - - // - // Provide the required inter-byte delay. - // - OSRAMDelay(g_ulDelay); - - // - // Write the next byte to the controller. - // - I2CMasterDataPut(I2C_MASTER_BASE, *pucBuffer++); - ulCount--; - - // - // Continue the transfer. - // - I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_CONT); - } -} - -//***************************************************************************** -// -//! \internal -//! -//! Finish a transfer to the SSD0303 controller. -//! -//! \param ucChar is the final byte to be written to the controller. -//! -//! This function will finish a transfer to the SSD0303 controller via the I2C -//! bus. This must only be called after calling OSRAMWriteFirst(). -//! -//! The data is written in a polled fashion; this function will not return -//! until the byte has been written to the controller. -//! -//! \return None. -// -//***************************************************************************** -static void -OSRAMWriteFinal(unsigned char ucChar) -{ - // - // Wait until the current byte has been transferred. - // - while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0) - { - } - - // - // Provide the required inter-byte delay. - // - OSRAMDelay(g_ulDelay); - - // - // Write the final byte to the controller. - // - I2CMasterDataPut(I2C_MASTER_BASE, ucChar); - - // - // Finish the transfer. - // - I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_FINISH); - - // - // Wait until the final byte has been transferred. - // - while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0) - { - } - - // - // Provide the required inter-byte delay. - // - OSRAMDelay(g_ulDelay); -} - -//***************************************************************************** -// -//! Clears the OLED display. -//! -//! This function will clear the display. All pixels in the display will be -//! turned off. -//! -//! This function is contained in osram96x16.c, with -//! osram96x16.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAMClear(void) -{ - static const unsigned char pucRow1[] = - { - 0xb0, 0x80, 0x04, 0x80, 0x12, 0x40 - }; - static const unsigned char pucRow2[] = - { - 0xb1, 0x80, 0x04, 0x80, 0x12, 0x40 - }; - unsigned long ulIdx; - - // - // Move the display cursor to the first column of the first row. - // - OSRAMWriteFirst(0x80); - OSRAMWriteArray(pucRow1, sizeof(pucRow1)); - - // - // Fill this row with zeros. - // - for(ulIdx = 0; ulIdx < 95; ulIdx++) - { - OSRAMWriteByte(0x00); - } - OSRAMWriteFinal(0x00); - - // - // Move the display cursor to the first column of the second row. - // - OSRAMWriteFirst(0x80); - OSRAMWriteArray(pucRow2, sizeof(pucRow2)); - - // - // Fill this row with zeros. - // - for(ulIdx = 0; ulIdx < 95; ulIdx++) - { - OSRAMWriteByte(0x00); - } - OSRAMWriteFinal(0x00); -} - -//***************************************************************************** -// -//! Displays a string on the OLED display. -//! -//! \param pcStr is a pointer to the string to display. -//! \param ulX is the horizontal position to display the string, specified in -//! columns from the left edge of the display. -//! \param ulY is the vertical position to display the string, specified in -//! eight scan line blocks from the top of the display (i.e. only 0 and 1 are -//! valid). -//! -//! This function will draw a string on the display. Only the ASCII characters -//! between 32 (space) and 126 (tilde) are supported; other characters will -//! result in random data being draw on the display (based on whatever appears -//! before/after the font in memory). The font is mono-spaced, so characters -//! such as "i" and "l" have more white space around them than characters such -//! as "m" or "w". -//! -//! If the drawing of the string reaches the right edge of the display, no more -//! characters will be drawn. Therefore, special care is not required to avoid -//! supplying a string that is "too long" to display. -//! -//! This function is contained in osram96x16.c, with -//! osram96x16.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAMStringDraw(const char *pcStr, unsigned long ulX, unsigned long ulY) -{ - // - // Check the arguments. - // - ASSERT(ulX < 96); - ASSERT(ulY < 2); - - // - // Move the display cursor to the requested position on the display. - // - OSRAMWriteFirst(0x80); - OSRAMWriteByte((ulY == 0) ? 0xb0 : 0xb1); - OSRAMWriteByte(0x80); - OSRAMWriteByte((ulX + 36) & 0x0f); - OSRAMWriteByte(0x80); - OSRAMWriteByte(0x10 | (((ulX + 36) >> 4) & 0x0f)); - OSRAMWriteByte(0x40); - - // - // Loop while there are more characters in the string. - // - while(*pcStr != 0) - { - // - // See if there is enough space on the display for this entire - // character. - // - if(ulX <= 90) - { - // - // Write the contents of this character to the display. - // - OSRAMWriteArray(g_pucFont[*pcStr - ' '], 5); - - // - // See if this is the last character to display (either because the - // right edge has been reached or because there are no more - // characters). - // - if((ulX == 90) || (pcStr[1] == 0)) - { - // - // Write the final column of the display. - // - OSRAMWriteFinal(0x00); - - // - // The string has been displayed. - // - return; - } - - // - // Write the inter-character padding column. - // - OSRAMWriteByte(0x00); - } - else - { - // - // Write the portion of the character that will fit onto the - // display. - // - OSRAMWriteArray(g_pucFont[*pcStr - ' '], 95 - ulX); - OSRAMWriteFinal(g_pucFont[*pcStr - ' '][95 - ulX]); - - // - // The string has been displayed. - // - return; - } - - // - // Advance to the next character. - // - pcStr++; - - // - // Increment the X coordinate by the six columns that were just - // written. - // - ulX += 6; - } -} - -//***************************************************************************** -// -//! Displays an image on the OLED display. -//! -//! \param pucImage is a pointer to the image data. -//! \param ulX is the horizontal position to display this image, specified in -//! columns from the left edge of the display. -//! \param ulY is the vertical position to display this image, specified in -//! eight scan line blocks from the top of the display (i.e. only 0 and 1 are -//! valid). -//! \param ulWidth is the width of the image, specified in columns. -//! \param ulHeight is the height of the image, specified in eight row blocks -//! (i.e. only 1 and 2 are valid). -//! -//! This function will display a bitmap graphic on the display. The image to -//! be displayed must be a multiple of eight scan lines high (i.e. one row) and -//! will be drawn at a vertical position that is a multiple of eight scan lines -//! (i.e. scan line zero or scan line eight, corresponding to row zero or row -//! one). -//! -//! The image data is organized with the first row of image data appearing left -//! to right, followed immediately by the second row of image data. Each byte -//! contains the data for the eight scan lines of the column, with the top scan -//! line being in the least significant bit of the byte and the bottom scan -//! line being in the most significant bit of the byte. -//! -//! For example, an image four columns wide and sixteen scan lines tall would -//! be arranged as follows (showing how the eight bytes of the image would -//! appear on the display): -//! -//! \verbatim -//! +-------+ +-------+ +-------+ +-------+ -//! | | 0 | | | 0 | | | 0 | | | 0 | -//! | B | 1 | | B | 1 | | B | 1 | | B | 1 | -//! | y | 2 | | y | 2 | | y | 2 | | y | 2 | -//! | t | 3 | | t | 3 | | t | 3 | | t | 3 | -//! | e | 4 | | e | 4 | | e | 4 | | e | 4 | -//! | | 5 | | | 5 | | | 5 | | | 5 | -//! | 0 | 6 | | 1 | 6 | | 2 | 6 | | 3 | 6 | -//! | | 7 | | | 7 | | | 7 | | | 7 | -//! +-------+ +-------+ +-------+ +-------+ -//! -//! +-------+ +-------+ +-------+ +-------+ -//! | | 0 | | | 0 | | | 0 | | | 0 | -//! | B | 1 | | B | 1 | | B | 1 | | B | 1 | -//! | y | 2 | | y | 2 | | y | 2 | | y | 2 | -//! | t | 3 | | t | 3 | | t | 3 | | t | 3 | -//! | e | 4 | | e | 4 | | e | 4 | | e | 4 | -//! | | 5 | | | 5 | | | 5 | | | 5 | -//! | 4 | 6 | | 5 | 6 | | 6 | 6 | | 7 | 6 | -//! | | 7 | | | 7 | | | 7 | | | 7 | -//! +-------+ +-------+ +-------+ +-------+ -//! \endverbatim -//! -//! This function is contained in osram96x16.c, with -//! osram96x16.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAMImageDraw(const unsigned char *pucImage, unsigned long ulX, - unsigned long ulY, unsigned long ulWidth, - unsigned long ulHeight) -{ - // - // Check the arguments. - // - ASSERT(ulX < 96); - ASSERT(ulY < 2); - ASSERT((ulX + ulWidth) <= 96); - ASSERT((ulY + ulHeight) <= 2); - - // - // The first 36 columns of the LCD buffer are not displayed, so increment - // the X coorddinate by 36 to account for the non-displayed frame buffer - // memory. - // - ulX += 36; - - // - // Loop while there are more rows to display. - // - while(ulHeight--) - { - // - // Write the starting address within this row. - // - OSRAMWriteFirst(0x80); - OSRAMWriteByte((ulY == 0) ? 0xb0 : 0xb1); - OSRAMWriteByte(0x80); - OSRAMWriteByte(ulX & 0x0f); - OSRAMWriteByte(0x80); - OSRAMWriteByte(0x10 | ((ulX >> 4) & 0x0f)); - OSRAMWriteByte(0x40); - - // - // Write this row of image data. - // - OSRAMWriteArray(pucImage, ulWidth - 1); - OSRAMWriteFinal(pucImage[ulWidth - 1]); - - // - // Advance to the next row of the image. - // - pucImage += ulWidth; - ulY++; - } -} - -//***************************************************************************** -// -//! Initialize the OLED display. -//! -//! \param bFast is a boolean that is \e true if the I2C interface should be -//! run at 400 kbps and \e false if it should be run at 100 kbps. -//! -//! This function initializes the I2C interface to the OLED display and -//! configures the SSD0303 controller on the panel. -//! -//! This function is contained in osram96x16.c, with -//! osram96x16.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAMInit(tBoolean bFast) -{ - unsigned long ulIdx; - - // - // Enable the I2C and GPIO port B blocks as they are needed by this driver. - // - SysCtlPeripheralEnable(SYSCTL_PERIPH_I2C); - SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB); - - // - // Configure the I2C SCL and SDA pins for I2C operation. - // - GPIOPinTypeI2C(GPIO_PORTB_BASE, GPIO_PIN_2 | GPIO_PIN_3); - - // - // Initialize the I2C master. - // - I2CMasterInit(I2C_MASTER_BASE, bFast); - - // - // Compute the inter-byte delay for the SSD0303 controller. This delay is - // dependent upon the I2C bus clock rate; the slower the clock the longer - // the delay required. - // - // The derivation of this formula is based on a measured delay of - // OSRAMDelay(1700) for a 100 kHz I2C bus with the CPU running at 50 MHz - // (referred to as C). To scale this to the delay for a different CPU - // speed (since this is just a CPU-based delay loop) is: - // - // f(CPU) - // C * ---------- - // 50,000,000 - // - // To then scale this to the actual I2C rate (since it won't always be - // precisely 100 kHz): - // - // f(CPU) 100,000 - // C * ---------- * ------- - // 50,000,000 f(I2C) - // - // This equation will give the inter-byte delay required for any - // configuration of the I2C master. But, as arranged it is impossible to - // directly compute in 32-bit arithmetic (without loosing a lot of - // accuracy). So, the equation is simplified. - // - // Since f(I2C) is generated by dividing down from f(CPU), replace it with - // the equivalent (where TPR is the value programmed into the Master Timer - // Period Register of the I2C master, with the 1 added back): - // - // 100,000 - // f(CPU) ------- - // C * ---------- * f(CPU) - // 50,000,000 ------------ - // 2 * 10 * TPR - // - // Inverting the dividend in the last term: - // - // f(CPU) 100,000 * 2 * 10 * TPR - // C * ---------- * ---------------------- - // 50,000,000 f(CPU) - // - // The f(CPU) now cancels out. - // - // 100,000 * 2 * 10 * TPR - // C * ---------------------- - // 50,000,000 - // - // Since there are no clock frequencies left in the equation, this equation - // also works for 400 kHz bus operation as well, since the 100,000 in the - // numerator becomes 400,000 but C is 1/4, which cancel out each other. - // Reducing the constants gives: - // - // TPR TPR TPR - // C * --- = 1700 * --- = 340 * --- = 68 * TPR - // 25 25 5 - // - // Note that the constant C is actually a bit larger than it needs to be in - // order to provide some safety margin. - // - g_ulDelay = 68 * (HWREG(I2C_MASTER_BASE + I2C_MASTER_O_TPR) + 1); - - // - // Initialize the SSD0303 controller. Loop through the initialization - // sequence doing a single I2C transfer for each command. - // - for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAMInit); - ulIdx += g_pucOSRAMInit[ulIdx] + 1) - { - // - // Send this command. - // - OSRAMWriteFirst(g_pucOSRAMInit[ulIdx + 1]); - OSRAMWriteArray(g_pucOSRAMInit + ulIdx + 2, g_pucOSRAMInit[ulIdx] - 2); - OSRAMWriteFinal(g_pucOSRAMInit[ulIdx + g_pucOSRAMInit[ulIdx]]); - } - - // - // Clear the frame buffer. - // - OSRAMClear(); -} - -//***************************************************************************** -// -//! Turns on the OLED display. -//! -//! This function will turn on the OLED display, causing it to display the -//! contents of its internal frame buffer. -//! -//! This function is contained in osram96x16.c, with -//! osram96x16.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAMDisplayOn(void) -{ - unsigned long ulIdx; - - // - // Re-initialize the SSD0303 controller. Loop through the initialization - // sequence doing a single I2C transfer for each command. - // - for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAMInit); - ulIdx += g_pucOSRAMInit[ulIdx] + 1) - { - // - // Send this command. - // - OSRAMWriteFirst(g_pucOSRAMInit[ulIdx + 1]); - OSRAMWriteArray(g_pucOSRAMInit + ulIdx + 2, g_pucOSRAMInit[ulIdx] - 2); - OSRAMWriteFinal(g_pucOSRAMInit[ulIdx + g_pucOSRAMInit[ulIdx]]); - } -} - -//***************************************************************************** -// -//! Turns off the OLED display. -//! -//! This function will turn off the OLED display. This will stop the scanning -//! of the panel and turn off the on-chip DC-DC converter, preventing damage to -//! the panel due to burn-in (it has similar characters to a CRT in this -//! respect). -//! -//! This function is contained in osram96x16.c, with -//! osram96x16.h containing the API definition for use by -//! applications. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAMDisplayOff(void) -{ - // - // Turn off the DC-DC converter and the display. - // - OSRAMWriteFirst(0x80); - OSRAMWriteByte(0xae); - OSRAMWriteByte(0x80); - OSRAMWriteByte(0xad); - OSRAMWriteByte(0x80); - OSRAMWriteFinal(0x8a); -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/osram96x16.h b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/osram96x16.h deleted file mode 100644 index 0c9cd3692..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/osram96x16.h +++ /dev/null @@ -1,47 +0,0 @@ -//***************************************************************************** -// -// osram96x16.h - Prototypes for the driver for the OSRAM 96x16 graphical OLED -// display. -// -// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __OSRAM96X16_H__ -#define __OSRAM96X16_H__ - -//***************************************************************************** -// -// Prototypes for the driver APIs. -// -//***************************************************************************** -extern void OSRAMClear(void); -extern void OSRAMStringDraw(const char *pcStr, unsigned long ulX, - unsigned long ulY); -extern void OSRAMImageDraw(const unsigned char *pucImage, unsigned long ulX, - unsigned long ulY, unsigned long ulWidth, - unsigned long ulHeight); -extern void OSRAMInit(tBoolean bFast); -extern void OSRAMDisplayOn(void); -extern void OSRAMDisplayOff(void); - -#endif // __OSRAM96X16_H__ diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/pwm.c b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/pwm.c deleted file mode 100644 index 6697566ea..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/pwm.c +++ /dev/null @@ -1,1291 +0,0 @@ -//***************************************************************************** -// -// pwm.c - API for the PWM modules -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup pwm_api -//! @{ -// -//***************************************************************************** - -#include "../hw_ints.h" -#include "../hw_memmap.h" -#include "../hw_pwm.h" -#include "../hw_types.h" -#include "debug.h" -#include "interrupt.h" -#include "pwm.h" - -//***************************************************************************** -// -// Misc macros for manipulating the encoded generator and output defines used -// by the API. -// -//***************************************************************************** -#define PWM_GEN_BADDR(_mod_, _gen_) \ - ((_mod_) + (_gen_)) -#define PWM_OUT_BADDR(_mod_, _out_) \ - ((_mod_) + ((_out_) & 0xFFFFFFC0)) -#define PWM_IS_OUTPUT_ODD(_out_) \ - ((_out_) & 0x00000001) - -//***************************************************************************** -// -//! Configures a PWM generator. -//! -//! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator to configure. Must be one of -//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. -//! \param ulConfig is the configuration for the PWM generator. -//! -//! This function is used to set the mode of operation for a PWM generator. -//! The counting mode, synchronization mode, and debug behavior are all -//! configured. After configuration, the generator is left in the disabled -//! state. -//! -//! A PWM generator can count in two different modes: count down mode or count -//! up/down mode. In count down mode, it will count from a value down to zero, -//! and then reset to the preset value. This will produce left-aligned PWM -//! signals (i.e. the rising edge of the two PWM signals produced by the -//! generator will occur at the same time). In count up/down mode, it will -//! count up from zero to the preset value, count back down to zero, and then -//! repeat the process. This will produce center-aligned PWM signals (i.e. the -//! middle of the high/low period of the PWM signals produced by the generator -//! will occur at the same time). -//! -//! When the PWM generator parameters (period and pulse width) are modified, -//! their affect on the output PWM signals can be delayed. In synchronous -//! mode, the parameter updates are not applied until a synchronization event -//! occurs. This allows multiple parameters to be modified and take affect -//! simultaneously, instead of one at a time. Additionally, parameters to -//! multiple PWM generators in synchronous mode can be updated simultaneously, -//! allowing them to be treated as if they were a unified generator. In -//! non-synchronous mode, the parameter updates are not delayed until a -//! synchronization event. In either mode, the parameter updates only occur -//! when the counter is at zero to help prevent oddly formed PWM signals during -//! the update (i.e. a PWM pulse that is too short or too long). -//! -//! The PWM generator can either pause or continue running when the processor -//! is stopped via the debugger. If configured to pause, it will continue to -//! count until it reaches zero, at which point it will pause until the -//! processor is restarted. If configured to continue running, it will keep -//! counting as if nothing had happened. -//! -//! The \b ulConfig parameter contains the desired configuration. It is the -//! logical OR of the following: \b PWM_GEN_MODE_DOWN or -//! \b PWM_GEN_MODE_UP_DOWN to specify the counting mode, \b PWM_GEN_MODE_SYNC -//! or \b PWM_GEN_MODE_NO_SYNC to specify the synchronization mode, and -//! \b PWM_GEN_MODE_DBG_RUN or \b PWM_GEN_MODE_DBG_STOP to specify the debug -//! behavior. -//! -//! \note Changes to the counter mode will affect the period of the PWM signals -//! produced. PWMGenPeriodSet() and PWMPulseWidthSet() should be called after -//! any changes to the counter mode of a generator. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_genconfigure) || defined(BUILD_ALL) || defined(DOXYGEN) -void -PWMGenConfigure(unsigned long ulBase, unsigned long ulGen, - unsigned long ulConfig) -{ - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || - (ulGen == PWM_GEN_2)); - - // - // Compute the generator's base address. - // - ulGen = PWM_GEN_BADDR(ulBase, ulGen); - - // - // Change the global configuration of the generator. - // - HWREG(ulGen + PWM_O_X_CTL) = ((HWREG(ulGen + PWM_O_X_CTL) & - ~(PWM_X_CTL_MODE | PWM_X_CTL_DEBUG | - PWM_X_CTL_LOADUPD | PWM_X_CTL_CMPAUPD | - PWM_X_CTL_CMPBUPD)) | ulConfig); - - // - // Set the individual PWM generator controls. - // - if(ulConfig & PWM_X_CTL_MODE) - { - // - // In up/down count mode, set the signal high on up count comparison - // and low on down count comparison (i.e. center align the signals). - // - HWREG(ulGen + PWM_O_X_GENA) = ((PWM_GEN_ACT_ONE << - PWM_GEN_ACT_A_UP_SHIFT) | - (PWM_GEN_ACT_ZERO << - PWM_GEN_ACT_A_DN_SHIFT)); - HWREG(ulGen + PWM_O_X_GENB) = ((PWM_GEN_ACT_ONE << - PWM_GEN_ACT_B_UP_SHIFT) | - (PWM_GEN_ACT_ZERO << - PWM_GEN_ACT_B_DN_SHIFT)); - } - else - { - // - // In down count mode, set the signal high on load and low on count - // comparison (i.e. left align the signals). - // - HWREG(ulGen + PWM_O_X_GENA) = ((PWM_GEN_ACT_ONE << - PWM_GEN_ACT_LOAD_SHIFT) | - (PWM_GEN_ACT_ZERO << - PWM_GEN_ACT_A_DN_SHIFT)); - HWREG(ulGen + PWM_O_X_GENB) = ((PWM_GEN_ACT_ONE << - PWM_GEN_ACT_LOAD_SHIFT) | - (PWM_GEN_ACT_ZERO << - PWM_GEN_ACT_B_DN_SHIFT)); - } -} -#endif - -//***************************************************************************** -// -//! Set the period of a PWM generator. -//! -//! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator to be modified. Must be one of -//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. -//! \param ulPeriod specifies the period of PWM generator output, measured -//! in clock ticks. -//! -//! This function sets the period of the specified PWM generator block, where -//! the period of the generator block is defined as the number of \b PWM -//! clock ticks between pulses on the generator block \b zero signal. -//! -//! \note Any subsequent calls made to this function before an update occurs -//! will cause the previous values to be overwritten. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_genperiodset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen, - unsigned long ulPeriod) -{ - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || - (ulGen == PWM_GEN_2)); - - // - // Compute the generator's base address. - // - ulGen = PWM_GEN_BADDR(ulBase, ulGen); - - // - // Set the reload register based on the mode. - // - if(HWREG(ulGen + PWM_O_X_CTL) & PWM_X_CTL_MODE) - { - // - // In up/down count mode, set the reload register to half the requested - // period. - // - ASSERT((ulPeriod / 2) < 65536); - HWREG(ulGen + PWM_O_X_LOAD) = ulPeriod / 2; - } - else - { - // - // In down count mode, set the reload register to the requested period - // minus one. - // - ASSERT((ulPeriod <= 65536) && (ulPeriod != 0)); - HWREG(ulGen + PWM_O_X_LOAD) = ulPeriod - 1; - } -} -#endif - -//***************************************************************************** -// -//! Gets the period of a PWM generator block. -//! -//! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator to query. Must be one of -//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. -//! -//! This function gets the period of the specified PWM generator block. The -//! period of the generator block is defined as the number of \b PWM clock -//! ticks between pulses on the generator block \b zero signal. -//! -//! If the update of the counter for the specified PWM generator has yet -//! to be completed, the value returned may not be the active period. The -//! value returned is the programmed period, measured in \b PWM clock ticks. -//! -//! \return Returns the programmed period of the specified generator block -//! in \b PWM clock ticks. -// -//***************************************************************************** -#if defined(GROUP_genperiodget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -PWMGenPeriodGet(unsigned long ulBase, unsigned long ulGen) -{ - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || - (ulGen == PWM_GEN_2)); - - // - // Compute the generator's base address. - // - ulGen = PWM_GEN_BADDR(ulBase, ulGen); - - // - // Figure out the counter mode. - // - if(HWREG(ulGen + PWM_O_X_CTL) & PWM_X_CTL_MODE) - { - // - // The period is twice the reload register value. - // - return(HWREG(ulGen + PWM_O_X_LOAD) * 2); - } - else - { - // - // The period is the reload register value plus one. - // - return(HWREG(ulGen + PWM_O_X_LOAD) + 1); - } -} -#endif - -//***************************************************************************** -// -//! Enables the timer/counter for a PWM generator block. -//! -//! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator to be enabled. Must be one of -//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. -//! -//! This function allows the \b PWM clock to drive the timer/counter for the -//! specified generator block. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_genenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -PWMGenEnable(unsigned long ulBase, unsigned long ulGen) -{ - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || - (ulGen == PWM_GEN_2)); - - // - // Enable the PWM generator. - // - HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_CTL) |= PWM_X_CTL_ENABLE; -} -#endif - -//***************************************************************************** -// -//! Disables the timer/counter for a PWM generator block. -//! -//! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator to be disabled. Must be one of -//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. -//! -//! This function blocks the \b PWM clock from driving the timer/counter for -//! the specified generator block. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_gendisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -PWMGenDisable(unsigned long ulBase, unsigned long ulGen) -{ - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || - (ulGen == PWM_GEN_2)); - - // - // Disable the PWM generator. - // - HWREG(PWM_GEN_BADDR(ulBase, + ulGen) + PWM_O_X_CTL) &= ~(PWM_X_CTL_ENABLE); -} -#endif - -//***************************************************************************** -// -//! Sets the pulse width for the specified PWM output. -//! -//! \param ulBase is the base address of the PWM module. -//! \param ulPWMOut is the PWM output to modify. Must be one of \b PWM_OUT_0, -//! \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4, or \b PWM_OUT_5. -//! \param ulWidth specifies the width of the positive portion of the pulse. -//! -//! This function sets the pulse width for the specified PWM output, where the -//! pulse width is defined as the number of \b PWM clock ticks. -//! -//! \note Any subsequent calls made to this function before an update occurs -//! will cause the previous values to be overwritten. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_pulsewidthset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut, - unsigned long ulWidth) -{ - unsigned long ulGenBase, ulReg; - - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - ASSERT((ulPWMOut == PWM_OUT_0) || (ulPWMOut == PWM_OUT_1) || - (ulPWMOut == PWM_OUT_2) || (ulPWMOut == PWM_OUT_3) || - (ulPWMOut == PWM_OUT_4) || (ulPWMOut == PWM_OUT_5)); - - // - // Compute the generator's base address. - // - ulGenBase = PWM_OUT_BADDR(ulBase, ulPWMOut); - - // - // If the counter is in up/down count mode, divide the width by two. - // - if(HWREG(ulGenBase + PWM_O_X_CTL) & PWM_X_CTL_MODE) - { - ulWidth /= 2; - } - - // - // Get the period. - // - ulReg = HWREG(ulGenBase + PWM_O_X_LOAD); - - // - // Make sure the width is not too large. - // - ASSERT(ulWidth < ulReg); - - // - // Compute the compare value. - // - ulReg = ulReg - ulWidth; - - // - // Write to the appropriate registers. - // - if(PWM_IS_OUTPUT_ODD(ulPWMOut)) - { - HWREG(ulGenBase + PWM_O_X_CMPB) = ulReg; - } - else - { - HWREG(ulGenBase + PWM_O_X_CMPA) = ulReg; - } -} -#endif - -//***************************************************************************** -// -//! Gets the pulse width of a PWM output. -//! -//! \param ulBase is the base address of the PWM module. -//! \param ulPWMOut is the PWM output to query. Must be one of \b PWM_OUT_0, -//! \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4, or \b PWM_OUT_5. -//! -//! This function gets the currently programmed pulse width for the -//! specified PWM output. If the update of the comparator for the specified -//! output has yet to be completed, the value returned may not be the active -//! pulse width. The value returned is the programmed pulse width, measured -//! in \b PWM clock ticks. -//! -//! \return Returns the width of the pulse in \b PWM clock ticks. -// -//***************************************************************************** -#if defined(GROUP_pulsewidthget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -PWMPulseWidthGet(unsigned long ulBase, unsigned long ulPWMOut) -{ - unsigned long ulGenBase, ulReg, ulLoad; - - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - ASSERT((ulPWMOut == PWM_OUT_0) || (ulPWMOut == PWM_OUT_1) || - (ulPWMOut == PWM_OUT_2) || (ulPWMOut == PWM_OUT_3) || - (ulPWMOut == PWM_OUT_4) || (ulPWMOut == PWM_OUT_5)); - - // - // Compute the generator's base address. - // - ulGenBase = PWM_OUT_BADDR(ulBase, ulPWMOut); - - // - // Then compute the pulse width. If mode is UpDown, set - // width = (load-compare)*2. Otherwise, set width = load - compare - // - ulLoad = HWREG(ulGenBase + PWM_O_X_LOAD); - if(PWM_IS_OUTPUT_ODD(ulPWMOut)) - { - ulReg = HWREG(ulGenBase + PWM_O_X_CMPB); - } - else - { - ulReg = HWREG(ulGenBase + PWM_O_X_CMPA); - } - ulReg = ulLoad - ulReg; - - // - // If in up/down count mode, double the pulse width. - // - if(HWREG(ulGenBase + PWM_O_X_CTL) & PWM_X_CTL_MODE) - { - ulReg = ulReg * 2; - } - - // - // Return the pulse width. - // - return(ulReg); -} -#endif - -//***************************************************************************** -// -//! Enables the PWM dead band output, and sets the dead band delays. -//! -//! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator to modify. Must be one of -//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. -//! \param usRise specifies the width of delay from the rising edge. -//! \param usFall specifies the width of delay from the falling edge. -//! -//! This function sets the dead bands for the specified PWM generator, -//! where the dead bands are defined as the number of \b PWM clock ticks -//! from the rising or falling edge of the generator's \b OutA signal. -//! Note that this function causes the coupling of \b OutB to \b OutA. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_deadbandenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen, - unsigned short usRise, unsigned short usFall) -{ - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || - (ulGen == PWM_GEN_2)); - ASSERT(usRise < 4096); - ASSERT(usFall < 4096); - - // - // Compute the generator's base address. - // - ulGen = PWM_GEN_BADDR(ulBase, ulGen); - - // - // Write the dead band delay values. - // - HWREG(ulGen + PWM_O_X_DBRISE) = usRise; - HWREG(ulGen + PWM_O_X_DBFALL) = usFall; - - // - // Enable the deadband functionality. - // - HWREG(ulGen + PWM_O_X_DBCTL) |= PWM_DBCTL_ENABLE; -} -#endif - -//***************************************************************************** -// -//! Disables the PWM dead band output. -//! -//! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator to modify. Must be one of -//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. -//! -//! This function disables the dead band mode for the specified PWM generator. -//! Doing so decouples the \b OutA and \b OutB signals. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_deadbanddisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen) -{ - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || - (ulGen == PWM_GEN_2)); - - // - // Disable the deadband functionality. - // - HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_DBCTL) &= ~(PWM_DBCTL_ENABLE); -} -#endif - -//***************************************************************************** -// -//! Synchronizes all pending updates. -//! -//! \param ulBase is the base address of the PWM module. -//! \param ulGenBits are the PWM generator blocks to be updated. Must be the -//! logical OR of any of \b PWM_GEN_0_BIT, \b PWM_GEN_1_BIT, or -//! \b PWM_GEN_2_BIT. -//! -//! For the selected PWM generators, this function causes all queued updates to -//! the period or pulse width to be applied the next time the corresponding -//! counter becomes zero. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_syncupdate) || defined(BUILD_ALL) || defined(DOXYGEN) -void -PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits) -{ - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - ASSERT(!(ulGenBits & ~(PWM_GEN_0_BIT | PWM_GEN_1_BIT | PWM_GEN_2_BIT))); - - // - // Update the PWM timing registers. - // - HWREG(ulBase + PWM_O_CTL) = ulGenBits; -} -#endif - -//***************************************************************************** -// -//! Synchronizes the counters in one or multiple PWM generator blocks. -//! -//! \param ulBase is the base address of the PWM module. -//! \param ulGenBits are the PWM generator blocks to be synchronized. Must be -//! the logical OR of any of \b PWM_GEN_0_BIT, \b PWM_GEN_1_BIT, or -//! \b PWM_GEN_2_BIT. -//! -//! For the selected PWM module, this function synchronizes the time base -//! of the generator blocks by causing the specified generator counters to be -//! reset to zero. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_synctimebase) || defined(BUILD_ALL) || defined(DOXYGEN) -void -PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits) -{ - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - ASSERT(!(ulGenBits & ~(PWM_GEN_0_BIT | PWM_GEN_1_BIT | PWM_GEN_2_BIT))); - - // - // Synchronize the counters in the specified generators by writing to - // the module's synchronization register. - // - HWREG(ulBase + PWM_O_SYNC) = ulGenBits; -} -#endif - -//***************************************************************************** -// -//! Enables or disables PWM outputs. -//! -//! \param ulBase is the base address of the PWM module. -//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the -//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT, -//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, or \b PWM_OUT_5_BIT. -//! \param bEnable determines if the signal is enabled or disabled. -//! -//! This function is used to enable or disable the selected PWM outputs. The -//! outputs are selected using the parameter \e ulPWMOutBits. The parameter -//! \e bEnable determines the state of the selected outputs. If \e bEnable is -//! \b true, then the selected PWM outputs are enabled, or placed in the active -//! state. If \e bEnable is \b false, then the selected outputs are disabled, -//! or placed in the inactive state. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_outputstate) || defined(BUILD_ALL) || defined(DOXYGEN) -void -PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits, - tBoolean bEnable) -{ - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT | - PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT))); - - // - // Read the module's ENABLE output control register, and set or clear - // the requested bits. - // - if(bEnable == true) - { - HWREG(ulBase + PWM_O_ENABLE) |= ulPWMOutBits; - } - else - { - HWREG(ulBase + PWM_O_ENABLE) &= ~(ulPWMOutBits); - } -} -#endif - -//***************************************************************************** -// -//! Selects the inversion mode for PWM outputs. -//! -//! \param ulBase is the base address of the PWM module. -//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the -//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT, -//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, or \b PWM_OUT_5_BIT. -//! \param bInvert determines if the signal is inverted or passed through. -//! -//! This function is used to select the inversion mode for the selected PWM -//! outputs. The outputs are selected using the parameter \e ulPWMOutBits. -//! The parameter \e bInvert determines the inversion mode for the selected -//! outputs. If \e bInvert is \b true, this function will cause the specified -//! PWM output signals to be inverted, or made active low. If \e bInvert is -//! \b false, the specified output will be passed through as is, or be made -//! active high. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_outputinvert) || defined(BUILD_ALL) || defined(DOXYGEN) -void -PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits, - tBoolean bInvert) -{ - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT | - PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT))); - - // - // Read the module's INVERT output control register, and set or clear - // the requested bits. - // - if(bInvert == true) - { - HWREG(ulBase + PWM_O_INVERT) |= ulPWMOutBits; - } - else - { - HWREG(ulBase + PWM_O_INVERT) &= ~(ulPWMOutBits); - } -} -#endif - -//***************************************************************************** -// -//! Specifies the state of PWM outputs in response to a fault condition. -//! -//! \param ulBase is the base address of the PWM module. -//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the -//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT, -//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, or \b PWM_OUT_5_BIT. -//! \param bFaultKill determines if the signal is killed or passed through -//! during an active fault condition. -//! -//! This function sets the fault handling characteristics of the selected PWM -//! outputs. The outputs are selected using the parameter \e ulPWMOutBits. -//! The parameter \e bFaultKill determines the fault handling characteristics -//! for the selected outputs. If \e bFaultKill is \b true, then the selected -//! outputs will be made inactive. If \e bFaultKill is \b false, then the -//! selected outputs are unaffected by the detected fault. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_outputfault) || defined(BUILD_ALL) || defined(DOXYGEN) -void -PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits, - tBoolean bFaultKill) -{ - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT | - PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT))); - - // - // Read the module's FAULT output control register, and set or clear - // the requested bits. - // - if(bFaultKill == true) - { - HWREG(ulBase + PWM_O_FAULT) |= ulPWMOutBits; - } - else - { - HWREG(ulBase + PWM_O_FAULT) &= ~(ulPWMOutBits); - } -} -#endif - -//***************************************************************************** -// -//! Registers an interrupt handler for the specified PWM generator block. -//! -//! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator in question. -//! \param pfnIntHandler is a pointer to the function to be called when the PWM -//! generator interrupt occurs. -//! -//! This function will ensure that the interrupt handler specified by -//! \e pfnIntHandler is called when an interrupt is detected for the specified -//! PWM generator block. This function will also enable the corresponding -//! PWM generator interrupt in the interrupt controller; individual generator -//! interrupts and interrupt sources must be enabled with PWMIntEnable() and -//! PWMGenIntTrigEnable(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_genintregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen, - void (*pfnIntHandler)(void)) -{ - unsigned long ulInt; - - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || - (ulGen == PWM_GEN_2)); - - // - // Get the interrupt number associated with the specified generator. - // - ulInt = INT_PWM0 + (ulGen >> 6) - 1; - - // - // Register the interrupt handler. - // - IntRegister(ulInt, pfnIntHandler); - - // - // Enable the PWMx interrupt. - // - IntEnable(ulInt); -} -#endif - -//***************************************************************************** -// -//! Removes an interrupt handler for the specified PWM generator block. -//! -//! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator in question. -//! -//! This function will unregister the interrupt handler for the specified -//! PWM generator block. This function will also disable the corresponding -//! PWM generator interrupt in the interrupt controller; individual generator -//! interrupts and interrupt sources must be disabled with PWMIntDisable() and -//! PWMGenIntTrigDisable(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_genintunregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen) -{ - unsigned long ulInt; - - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || - (ulGen == PWM_GEN_2)); - - // - // Get the interrupt number associated with the specified generator. - // - ulInt = INT_PWM0 + (ulGen >> 6) - 1; - - // - // Disable the PWMx interrupt. - // - IntDisable(ulInt); - - // - // Unregister the interrupt handler. - // - IntUnregister(ulInt); -} -#endif - -//***************************************************************************** -// -//! Registers an interrupt handler for a fault condition detected in a PWM -//! module. -//! -//! \param ulBase is the base address of the PWM module. -//! \param pfnIntHandler is a pointer to the function to be called when the PWM -//! fault interrupt occurs. -//! -//! This function will ensure that the interrupt handler specified by -//! \e pfnIntHandler is called when a fault interrupt is detected for the -//! selected PWM module. This function will also enable the PWM fault -//! interrupt in the NVIC; the PWM fault interrupt must also be enabled at the -//! module level using PWMIntEnable(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_faultintregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -PWMFaultIntRegister(unsigned long ulBase, void (*pfnIntHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - - // - // Register the interrupt handler, returning an error if one occurs. - // - IntRegister(INT_PWM_FAULT, pfnIntHandler); - - // - // Enable the PWM fault interrupt. - // - IntEnable(INT_PWM_FAULT); -} -#endif - -//***************************************************************************** -// -//! Removes the PWM fault condition interrupt handler. -//! -//! \param ulBase is the base address of the PWM module. -//! -//! This function will remove the interrupt handler for a PWM fault interrupt -//! from the selected PWM module. This function will also disable the PWM -//! fault interrupt in the NVIC; the PWM fault interrupt must also be disabled -//! at the module level using PWMIntDisable(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_faultintunregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -PWMFaultIntUnregister(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - - // - // Disable the PWM fault interrupt. - // - IntDisable(INT_PWM_FAULT); - - // - // Unregister the interrupt handler, returning an error if one occurs. - // - IntUnregister(INT_PWM_FAULT); -} -#endif - -//***************************************************************************** -// -//! Enables interrupts and triggers for the specified PWM generator block. -//! -//! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator to have interrupts and triggers enabled. -//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. -//! \param ulIntTrig specifies the interrupts and triggers to be enabled. -//! -//! Unmasks the specified interrupt(s) and trigger(s) by setting the -//! specified bits of the interrupt/trigger enable register for the specified -//! PWM generator. The defined values for the bits are as follows: -//! -//! - PWM_INT_CNT_ZERO -//! - PWM_INT_CNT_LOAD -//! - PWM_INT_CMP_AU -//! - PWM_INT_CMP_AD -//! - PWM_INT_CMP_BU -//! - PWM_INT_CMP_BD -//! - PWM_TR_CNT_ZERO -//! - PWM_TR_CNT_LOAD -//! - PWM_TR_CMP_AU -//! - PWM_TR_CMP_AD -//! - PWM_TR_CMP_BU -//! - PWM_TR_CMP_BD -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_geninttrigenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen, - unsigned long ulIntTrig) -{ - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || - (ulGen == PWM_GEN_2)); - - // - // Enable the specified interrupts/triggers. - // - HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_INTEN) |= ulIntTrig; -} -#endif - -//***************************************************************************** -// -//! Disables interrupts for the specified PWM generator block. -//! -//! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator to have interrupts and triggers disabled. -//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2. -//! \param ulIntTrig specifies the interrupts and triggers to be disabled. -//! -//! Masks the specified interrupt(s) and trigger(s) by clearing the -//! specified bits of the interrupt/trigger enable register for the specified -//! PWM generator. The defined values for the bits are as follows: -//! -//! - PWM_INT_CNT_ZERO -//! - PWM_INT_CNT_LOAD -//! - PWM_INT_CMP_AU -//! - PWM_INT_CMP_AD -//! - PWM_INT_CMP_BU -//! - PWM_INT_CMP_BD -//! - PWM_TR_CNT_ZERO -//! - PWM_TR_CNT_LOAD -//! - PWM_TR_CMP_AU -//! - PWM_TR_CMP_AD -//! - PWM_TR_CMP_BU -//! - PWM_TR_CMP_BD -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_geninttrigdisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen, - unsigned long ulIntTrig) -{ - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || - (ulGen == PWM_GEN_2)); - - // - // Disable the specified interrupts/triggers. - // - HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_INTEN) &= ~(ulIntTrig); -} -#endif - -//***************************************************************************** -// -//! Gets interrupt status for the specified PWM generator block. -//! -//! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator to query. Must be one of \b PWM_GEN_0, -//! \b PWM_GEN_1, or \b PWM_GEN_2. -//! \param bMasked specifies whether masked or raw interrupt status is -//! returned. -//! -//! If \e bMasked is set as \b true, then the masked interrupt status is -//! returned; otherwise, the raw interrupt status will be returned. -//! -//! \return Returns the contents of the interrupt status register, or the -//! contents of the raw interrupt status register, for the specified -//! PWM generator. -// -//***************************************************************************** -#if defined(GROUP_genintstatus) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen, tBoolean bMasked) -{ - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || - (ulGen == PWM_GEN_2)); - - // - // Compute the generator's base address. - // - ulGen = PWM_GEN_BADDR(ulBase, ulGen); - - // - // Read and return the specified generator's raw or enabled interrupt - // status. - // - if(bMasked == true) - { - return(HWREG(ulGen + PWM_O_X_ISC)); - } - else - { - return(HWREG(ulGen + PWM_O_X_RIS)); - } -} -#endif - -//***************************************************************************** -// -//! Clears the specified interrupt(s) for the specified PWM generator block. -//! -//! \param ulBase is the base address of the PWM module. -//! \param ulGen is the PWM generator to query. Must be one of \b PWM_GEN_0, -//! \b PWM_GEN_1, or \b PWM_GEN_2. -//! \param ulInts specifies the interrupts to be cleared. -//! -//! Clears the specified interrupt(s) by writing a 1 to the specified bits -//! of the interrupt status register for the specified PWM generator. The -//! defined values for the bits are as follows: -//! -//! - PWM_INT_CNT_ZERO -//! - PWM_INT_CNT_LOAD -//! - PWM_INT_CMP_AU -//! - PWM_INT_CMP_AD -//! - PWM_INT_CMP_BU -//! - PWM_INT_CMP_BD -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_genintclear) || defined(BUILD_ALL) || defined(DOXYGEN) -void -PWMGenIntClear(unsigned long ulBase, unsigned long ulGen, unsigned long ulInts) -{ - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) || - (ulGen == PWM_GEN_2)); - - // - // Clear the requested interrupts by writing ones to the specified bit - // of the module's interrupt enable register. - // - HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_ISC) = ulInts; -} -#endif - -//***************************************************************************** -// -//! Enables generator and fault interrupts for a PWM module. -//! -//! \param ulBase is the base address of the PWM module. -//! \param ulGenFault contains the interrupts to be enabled. Must be a logical -//! OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2, or -//! \b PWM_INT_FAULT. -//! -//! Unmasks the specified interrupt(s) by setting the specified bits of -//! the interrupt enable register for the selected PWM module. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault) -{ - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - - // - // Read the module's interrupt enable register, and enable interrupts - // for the specified PWM generators. - // - HWREG(ulBase + PWM_O_INTEN) |= ulGenFault; -} -#endif - -//***************************************************************************** -// -//! Disables generator and fault interrupts for a PWM module. -//! -//! \param ulBase is the base address of the PWM module. -//! \param ulGenFault contains the interrupts to be disabled. Must be a -//! logical OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2, -//! or \b PWM_INT_FAULT. -//! -//! Masks the specified interrupt(s) by clearing the specified bits of -//! the interrupt enable register for the selected PWM module. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault) -{ - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - - // - // Read the module's interrupt enable register, and disable interrupts - // for the specified PWM generators. - // - HWREG(ulBase + PWM_O_INTEN) &= ~(ulGenFault); -} -#endif - -//***************************************************************************** -// -//! Clears the fault interrupt for a PWM module. -//! -//! \param ulBase is the base address of the PWM module. -//! -//! Clears the fault interrupt by writing to the appropriate bit of the -//! interrupt status register for the selected PWM module. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_faultintclear) || defined(BUILD_ALL) || defined(DOXYGEN) -void -PWMFaultIntClear(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - - // - // Write the only writeable bit in the module's interrupt register. - // - HWREG(ulBase + PWM_O_ISC) = PWM_INT_INTFAULT; -} -#endif - -//***************************************************************************** -// -//! Gets the interrupt status for a PWM module. -//! -//! \param ulBase is the base address of the PWM module. -//! \param bMasked specifies whether masked or raw interrupt status is -//! returned. -//! -//! If \e bMasked is set as \b true, then the masked interrupt status is -//! returned; otherwise, the raw interrupt status will be returned. -//! -//! \return The current interrupt status, enumerated as a bit field of -//! \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2, and \b PWM_INT_FAULT. -//! -//***************************************************************************** -#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -PWMIntStatus(unsigned long ulBase, tBoolean bMasked) -{ - // - // Check the arguments. - // - ASSERT(ulBase == PWM_BASE); - - // - // Read and return either the module's raw or enabled interrupt status. - // - if(bMasked == true) - { - return(HWREG(ulBase + PWM_O_ISC)); - } - else - { - return(HWREG(ulBase + PWM_O_RIS)); - } -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/pwm.h b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/pwm.h deleted file mode 100644 index db835bacd..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/pwm.h +++ /dev/null @@ -1,161 +0,0 @@ -//***************************************************************************** -// -// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __PWM_H__ -#define __PWM_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following defines are passed to PWMGenConfigure() as the ulConfig -// parameter and specify the configuration of the PWM generator. -// -//***************************************************************************** -#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode -#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode -#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates -#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates -#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode -#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode - -//***************************************************************************** -// -// Defines for enabling, disabling, and clearing PWM generator interrupts and -// triggers. -// -//***************************************************************************** -#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0 -#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD -#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U -#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D -#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U -#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D -#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0 -#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD -#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U -#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D -#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U -#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D - -//***************************************************************************** -// -// Defines for enabling, disabling, and clearing PWM interrupts. -// -//***************************************************************************** -#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt -#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt -#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt -#define PWM_INT_FAULT 0x00010000 // Fault interrupt - -//***************************************************************************** -// -// Defines to identify the generators within a module. -// -//***************************************************************************** -#define PWM_GEN_0 0x00000040 // Offset address of Gen0 -#define PWM_GEN_1 0x00000080 // Offset address of Gen1 -#define PWM_GEN_2 0x000000C0 // Offset address of Gen2 - -#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0 -#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1 -#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2 - -//***************************************************************************** -// -// Defines to identify the outputs within a module. -// -//***************************************************************************** -#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0 -#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1 -#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2 -#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3 -#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4 -#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5 - -#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0 -#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1 -#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2 -#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3 -#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4 -#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5 - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen, - unsigned long ulConfig); -extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen, - unsigned long ulPeriod); -extern unsigned long PWMGenPeriodGet(unsigned long ulBase, - unsigned long ulGen); -extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen); -extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen); -extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut, - unsigned long ulWidth); -extern unsigned long PWMPulseWidthGet(unsigned long ulBase, - unsigned long ulPWMOut); -extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen, - unsigned short usRise, unsigned short usFall); -extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen); -extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits); -extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits); -extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits, - tBoolean bEnable); -extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits, - tBoolean bInvert); -extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits, - tBoolean bFaultKill); -extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen, - void (*pfnIntHandler)(void)); -extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen); -extern void PWMFaultIntRegister(unsigned long ulBase, - void (*pfnIntHandler)(void)); -extern void PWMFaultIntUnregister(unsigned long ulBase); -extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen, - unsigned long ulIntTrig); -extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen, - unsigned long ulIntTrig); -extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen, - tBoolean bMasked); -extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen, - unsigned long ulInts); -extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault); -extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault); -extern void PWMFaultIntClear(unsigned long ulBase); -extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked); - -#ifdef __cplusplus -} -#endif - -#endif // __PWM_H__ diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/qei.c b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/qei.c deleted file mode 100644 index eb982de39..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/qei.c +++ /dev/null @@ -1,630 +0,0 @@ -//***************************************************************************** -// -// qei.c - Driver for the Quadrature Encoder with Index. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup qei_api -//! @{ -// -//***************************************************************************** - -#include "../hw_ints.h" -#include "../hw_memmap.h" -#include "../hw_qei.h" -#include "../hw_types.h" -#include "debug.h" -#include "interrupt.h" -#include "qei.h" - -//***************************************************************************** -// -//! Enables the quadrature encoder. -//! -//! \param ulBase is the base address of the quadrature encoder module. -//! -//! This will enable operation of the quadrature encoder module. It must be -//! configured before it is enabled. -//! -//! \sa QEIConfigure() -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -QEIEnable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == QEI_BASE); - - // - // Enable the QEI module. - // - HWREG(ulBase + QEI_O_CTL) |= QEI_CTL_ENABLE; -} -#endif - -//***************************************************************************** -// -//! Disables the quadrature encoder. -//! -//! \param ulBase is the base address of the quadrature encoder module. -//! -//! This will disable operation of the quadrature encoder module. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -QEIDisable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == QEI_BASE); - - // - // Disable the QEI module. - // - HWREG(ulBase + QEI_O_CTL) &= ~(QEI_CTL_ENABLE); -} -#endif - -//***************************************************************************** -// -//! Configures the quadrature encoder. -//! -//! \param ulBase is the base address of the quadrature encoder module. -//! \param ulConfig is the configuration for the quadrature encoder. See below -//! for a description of this parameter. -//! \param ulMaxPosition specifies the maximum position value. -//! -//! This will configure the operation of the quadrature encoder. The -//! \e ulConfig parameter provides the configuration of the encoder and is the -//! logical OR of several values: -//! -//! - \b QEI_CONFIG_CAPTURE_A or \b QEI_CONFIG_CAPTURE_A_B to specify if edges -//! on channel A or on both channels A and B should be counted by the -//! position integrator and velocity accumulator. -//! - \b QEI_CONFIG_NO_RESET or \b QEI_CONFIG_RESET_IDX to specify if the -//! position integrator should be reset when the index pulse is detected. -//! - \b QEI_CONFIG_QUADRATURE or \b QEI_CONFIG_CLOCK_DIR to specify if -//! quadrature signals are being provided on ChA and ChB, or if a direction -//! signal and a clock are being provided instead. -//! - \b QEI_CONFIG_NO_SWAP or \b QEI_CONFIG_SWAP to specify if the signals -//! provided on ChA and ChB should be swapped before being processed. -//! -//! \e ulMaxPosition is the maximum value of the position integrator, and is -//! the value used to reset the position capture when in index reset mode and -//! moving in the reverse (negative) direction. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_configure) || defined(BUILD_ALL) || defined(DOXYGEN) -void -QEIConfigure(unsigned long ulBase, unsigned long ulConfig, - unsigned long ulMaxPosition) -{ - // - // Check the arguments. - // - ASSERT(ulBase == QEI_BASE); - - // - // Write the new configuration to the hardware. - // - HWREG(ulBase + QEI_O_CTL) = ((HWREG(ulBase + QEI_O_CTL) & - ~(QEI_CTL_CAPMODE | QEI_CTL_RESMODE | - QEI_CTL_SIGMODE | QEI_CTL_SWAP)) | - ulConfig); - - // - // Set the maximum position. - // - HWREG(ulBase + QEI_O_MAXPOS) = ulMaxPosition; -} -#endif - -//***************************************************************************** -// -//! Gets the current encoder position. -//! -//! \param ulBase is the base address of the quadrature encoder module. -//! -//! This returns the current position of the encoder. Depending upon the -//! configuration of the encoder, and the incident of an index pulse, this -//! value may or may not contain the expected data (i.e. if in reset on index -//! mode, if an index pulse has not been encountered, the position counter will -//! not be aligned with the index pulse yet). -//! -//! \return The current position of the encoder. -// -//***************************************************************************** -#if defined(GROUP_positionget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -QEIPositionGet(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == QEI_BASE); - - // - // Return the current position counter. - // - return(HWREG(ulBase + QEI_O_POS)); -} -#endif - -//***************************************************************************** -// -//! Sets the current encoder position. -//! -//! \param ulBase is the base address of the quadrature encoder module. -//! \param ulPosition is the new position for the encoder. -//! -//! This sets the current position of the encoder; the encoder position will -//! then be measured relative to this value. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_positionset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -QEIPositionSet(unsigned long ulBase, unsigned long ulPosition) -{ - // - // Check the arguments. - // - ASSERT(ulBase == QEI_BASE); - - // - // Set the position counter. - // - HWREG(ulBase + QEI_O_POS) = ulPosition; -} -#endif - -//***************************************************************************** -// -//! Gets the current direction of rotation. -//! -//! \param ulBase is the base address of the quadrature encoder module. -//! -//! This returns the current direction of rotation. In this case, current -//! means the most recently detected direction of the encoder; it may not be -//! presently moving but this is the direction it last moved before it stopped. -//! -//! \return 1 if moving in the forward direction or -1 if moving in the reverse -//! direction. -// -//***************************************************************************** -#if defined(GROUP_directionget) || defined(BUILD_ALL) || defined(DOXYGEN) -long -QEIDirectionGet(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == QEI_BASE); - - // - // Return the direction of rotation. - // - return((HWREG(ulBase + QEI_O_STAT) & QEI_STAT_DIRECTION) ? -1 : 1); -} -#endif - -//***************************************************************************** -// -//! Gets the encoder error indicator. -//! -//! \param ulBase is the base address of the quadrature encoder module. -//! -//! This returns the error indicator for the quadrature encoder. It is an -//! error for both of the signals of the quadrature input to change at the same -//! time. -//! -//! \return true if an error has occurred and false otherwise. -// -//***************************************************************************** -#if defined(GROUP_errorget) || defined(BUILD_ALL) || defined(DOXYGEN) -tBoolean -QEIErrorGet(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == QEI_BASE); - - // - // Return the error indicator. - // - return((HWREG(ulBase + QEI_O_STAT) & QEI_STAT_ERROR) ? true : false); -} -#endif - -//***************************************************************************** -// -//! Enables the velocity capture. -//! -//! \param ulBase is the base address of the quadrature encoder module. -//! -//! This will enable operation of the velocity capture in the quadrature -//! encoder module. It must be configured before it is enabled. Velocity -//! capture will not occur if the quadrature encoder is not enabled. -//! -//! \sa QEIVelocityConfigure() and QEIEnable() -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_velocityenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -QEIVelocityEnable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == QEI_BASE); - - // - // Enable the velocity capture. - // - HWREG(ulBase + QEI_O_CTL) |= QEI_CTL_VELEN; -} -#endif - -//***************************************************************************** -// -//! Disables the velocity capture. -//! -//! \param ulBase is the base address of the quadrature encoder module. -//! -//! This will disable operation of the velocity capture in the quadrature -//! encoder module. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_velocitydisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -QEIVelocityDisable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == QEI_BASE); - - // - // Disable the velocity capture. - // - HWREG(ulBase + QEI_O_CTL) &= ~(QEI_CTL_VELEN); -} -#endif - -//***************************************************************************** -// -//! Configures the velocity capture. -//! -//! \param ulBase is the base address of the quadrature encoder module. -//! \param ulPreDiv specifies the predivider applied to the input quadrature -//! signal before it is counted; can be one of QEI_VELDIV_1, QEI_VELDIV_2, -//! QEI_VELDIV_4, QEI_VELDIV_8, QEI_VELDIV_16, QEI_VELDIV_32, QEI_VELDIV_64, or -//! QEI_VELDIV_128. -//! \param ulPeriod specifies the number of clock ticks over which to measure -//! the velocity; must be non-zero. -//! -//! This will configure the operation of the velocity capture portion of the -//! quadrature encoder. The position increment signal is predivided as -//! specified by \e ulPreDiv before being accumulated by the velocity capture. -//! The divided signal is accumulated over \e ulPeriod system clock before -//! being saved and resetting the accumulator. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_velocityconfigure) || defined(BUILD_ALL) || defined(DOXYGEN) -void -QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv, - unsigned long ulPeriod) -{ - // - // Check the arguments. - // - ASSERT(ulBase == QEI_BASE); - ASSERT(!(ulPreDiv & ~(QEI_CTL_VELDIV_M))); - ASSERT(ulPeriod != 0); - - // - // Set the velocity predivider. - // - HWREG(ulBase + QEI_O_CTL) = ((HWREG(ulBase + QEI_O_CTL) & - ~(QEI_CTL_VELDIV_M)) | ulPreDiv); - - // - // Set the timer period. - // - HWREG(ulBase + QEI_O_LOAD) = ulPeriod - 1; -} -#endif - -//***************************************************************************** -// -//! Gets the current encoder speed. -//! -//! \param ulBase is the base address of the quadrature encoder module. -//! -//! This returns the current speed of the encoder. The value returned is the -//! number of pulses detected in the specified time period; this number can be -//! multiplied by the number of time periods per second and divided by the -//! number of pulses per revolution to obtain the number of revolutions per -//! second. -//! -//! \return The number of pulses captured in the given time period. -// -//***************************************************************************** -#if defined(GROUP_velocityget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -QEIVelocityGet(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == QEI_BASE); - - // - // Return the speed capture value. - // - return(HWREG(ulBase + QEI_O_SPEED)); -} -#endif - -//***************************************************************************** -// -//! Registers an interrupt handler for the quadrature encoder interrupt. -//! -//! \param ulBase is the base address of the quadrature encoder module. -//! \param pfnHandler is a pointer to the function to be called when the -//! quadrature encoder interrupt occurs. -//! -//! This sets the handler to be called when a quadrature encoder interrupt -//! occurs. This will enable the global interrupt in the interrupt controller; -//! specific quadrature encoder interrupts must be enabled via QEIIntEnable(). -//! It is the interrupt handler's responsibility to clear the interrupt source -//! via QEIIntClear(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT(ulBase == QEI_BASE); - - // - // Register the interrupt handler, returning an error if an error occurs. - // - IntRegister(INT_QEI, pfnHandler); - - // - // Enable the quadrature encoder interrupt. - // - IntEnable(INT_QEI); -} -#endif - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the quadrature encoder interrupt. -//! -//! \param ulBase is the base address of the quadrature encoder module. -//! -//! This function will clear the handler to be called when a quadrature encoder -//! interrupt occurs. This will also mask off the interrupt in the interrupt -//! controller so that the interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -QEIIntUnregister(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == QEI_BASE); - - // - // Disable the interrupt. - // - IntDisable(INT_QEI); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_QEI); -} -#endif - -//***************************************************************************** -// -//! Enables individual quadrature encoder interrupt sources. -//! -//! \param ulBase is the base address of the quadrature encoder module. -//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. -//! Can be any of the QEI_INTERROR, QEI_INTDIR, QEI_INTTIMER, or QEI_INTINDEX -//! values. -//! -//! Enables the indicated quadrature encoder interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags) -{ - // - // Check the arguments. - // - ASSERT(ulBase == QEI_BASE); - - // - // Enable the specified interrupts. - // - HWREG(ulBase + QEI_O_INTEN) |= ulIntFlags; -} -#endif - -//***************************************************************************** -// -//! Disables individual quadrature encoder interrupt sources. -//! -//! \param ulBase is the base address of the quadrature encoder module. -//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. -//! Can be any of the QEI_INTERROR, QEI_INTDIR, QEI_INTTIMER, or QEI_INTINDEX -//! values. -//! -//! Disables the indicated quadrature encoder interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags) -{ - // - // Check the arguments. - // - ASSERT(ulBase == QEI_BASE); - - // - // Disable the specified interrupts. - // - HWREG(ulBase + QEI_O_INTEN) &= ~(ulIntFlags); -} -#endif - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \param ulBase is the base address of the quadrature encoder module. -//! \param bMasked is false if the raw interrupt status is required and true if -//! the masked interrupt status is required. -//! -//! This returns the interrupt status for the quadrature encoder module. -//! Either the raw interrupt status or the status of interrupts that are -//! allowed to reflect to the processor can be returned. -//! -//! \return The current interrupt status, enumerated as a bit field of -//! QEI_INTERROR, QEI_INTDIR, QEI_INTTIMER, and QEI_INTINDEX. -// -//***************************************************************************** -#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -QEIIntStatus(unsigned long ulBase, tBoolean bMasked) -{ - // - // Check the arguments. - // - ASSERT(ulBase == QEI_BASE); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(ulBase + QEI_O_ISC)); - } - else - { - return(HWREG(ulBase + QEI_O_RIS)); - } -} -#endif - -//***************************************************************************** -// -//! Clears quadrature encoder interrupt sources. -//! -//! \param ulBase is the base address of the quadrature encoder module. -//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. -//! Can be any of the QEI_INTERROR, QEI_INTDIR, QEI_INTTIMER, or QEI_INTINDEX -//! values. -//! -//! The specified quadrature encoder interrupt sources are cleared, so that -//! they no longer assert. This must be done in the interrupt handler to keep -//! it from being called again immediately upon exit. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) -void -QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags) -{ - // - // Check the arguments. - // - ASSERT(ulBase == QEI_BASE); - - // - // Clear the requested interrupt sources. - // - HWREG(ulBase + QEI_O_ISC) = ulIntFlags; -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/qei.h b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/qei.h deleted file mode 100644 index 3eaafaeef..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/qei.h +++ /dev/null @@ -1,104 +0,0 @@ -//***************************************************************************** -// -// qei.h - Prototypes for the Quadrature Encoder Driver. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __QEI_H__ -#define __QEI_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to QEIConfigure as the ulConfig paramater. -// -//***************************************************************************** -#define QEI_CONFIG_CAPTURE_A 0x00000000 // Count on ChA edges only -#define QEI_CONFIG_CAPTURE_A_B 0x00000008 // Count on ChA and ChB edges -#define QEI_CONFIG_NO_RESET 0x00000000 // Do not reset on index pulse -#define QEI_CONFIG_RESET_IDX 0x00000010 // Reset position on index pulse -#define QEI_CONFIG_QUADRATURE 0x00000000 // ChA and ChB are quadrature -#define QEI_CONFIG_CLOCK_DIR 0x00000004 // ChA and ChB are clock and dir -#define QEI_CONFIG_NO_SWAP 0x00000000 // Do not swap ChA and ChB -#define QEI_CONFIG_SWAP 0x00000002 // Swap ChA and ChB - -//***************************************************************************** -// -// Values that can be passed to QEIVelocityConfigure as the ulPreDiv parameter. -// -//***************************************************************************** -#define QEI_VELDIV_1 0x00000000 // Predivide by 1 -#define QEI_VELDIV_2 0x00000040 // Predivide by 2 -#define QEI_VELDIV_4 0x00000080 // Predivide by 4 -#define QEI_VELDIV_8 0x000000C0 // Predivide by 8 -#define QEI_VELDIV_16 0x00000100 // Predivide by 16 -#define QEI_VELDIV_32 0x00000140 // Predivide by 32 -#define QEI_VELDIV_64 0x00000180 // Predivide by 64 -#define QEI_VELDIV_128 0x000001C0 // Predivide by 128 - -//***************************************************************************** -// -// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts -// as the ulIntFlags parameter, and returned by QEIGetIntStatus. -// -//***************************************************************************** -#define QEI_INTERROR 0x00000008 // Phase error detected -#define QEI_INTDIR 0x00000004 // Direction change -#define QEI_INTTIMER 0x00000002 // Velocity timer expired -#define QEI_INTINDEX 0x00000001 // Index pulse detected - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void QEIEnable(unsigned long ulBase); -extern void QEIDisable(unsigned long ulBase); -extern void QEIConfigure(unsigned long ulBase, unsigned long ulConfig, - unsigned long ulMaxPosition); -extern unsigned long QEIPositionGet(unsigned long ulBase); -extern void QEIPositionSet(unsigned long ulBase, unsigned long ulPosition); -extern long QEIDirectionGet(unsigned long ulBase); -extern tBoolean QEIErrorGet(unsigned long ulBase); -extern void QEIVelocityEnable(unsigned long ulBase); -extern void QEIVelocityDisable(unsigned long ulBase); -extern void QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv, - unsigned long ulPeriod); -extern unsigned long QEIVelocityGet(unsigned long ulBase); -extern void QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); -extern void QEIIntUnregister(unsigned long ulBase); -extern void QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long QEIIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags); - -#ifdef __cplusplus -} -#endif - -#endif // __QEI_H__ diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/ssi.c b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/ssi.c deleted file mode 100644 index 095aaab33..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/ssi.c +++ /dev/null @@ -1,609 +0,0 @@ -//***************************************************************************** -// -// ssi.c - Driver for Synchronous Serial Interface. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup ssi_api -//! @{ -// -//***************************************************************************** - -#include "../hw_ints.h" -#include "../hw_memmap.h" -#include "../hw_ssi.h" -#include "../hw_types.h" -#include "debug.h" -#include "interrupt.h" -#include "ssi.h" -#include "sysctl.h" - -//***************************************************************************** -// -//! Configures the synchronous serial interface. -//! -//! \param ulBase specifies the SSI module base address. -//! \param ulProtocol specifies the data transfer protocol. -//! \param ulMode specifies the mode of operation. -//! \param ulBitRate specifies the clock rate. -//! \param ulDataWidth specifies number of bits transfered per frame. -//! -//! This function configures the synchronous serial interface. It sets -//! the SSI protocol, mode of operation, bit rate, and data width. -//! -//! The parameter \e ulProtocol defines the data frame format. The parameter -//! \e ulProtocol can be one of the following values: SSI_FRF_MOTO_MODE_0, -//! SSI_FRF_MOTO_MODE_1, SSI_FRF_MOTO_MODE_2, SSI_FRF_MOTO_MODE_3, -//! SSI_FRF_TI, or SSI_FRF_NMW. The Motorola frame formats imply the -//! following polarity and phase configurations: -//! 
-//! Polarity Phase       Mode
-//!   0       0   SSI_FRF_MOTO_MODE_0
-//!   0       1   SSI_FRF_MOTO_MODE_1
-//!   1       0   SSI_FRF_MOTO_MODE_2
-//!   1       1   SSI_FRF_MOTO_MODE_3
-//!
-//! -//! The parameter \e ulMode defines the operating mode of the SSI module. The -//! SSI module can operate as a master or slave; if a slave, the SSI can be -//! configured to disable output on its serial output line. The parameter -//! \e ulMode can be one of the following values: SSI_MODE_MASTER, -//! SSI_MODE_SLAVE, or SSI_MODE_SLAVE_OD. -//! -//! The parameter \e ulBitRate defines the bit rate for the SSI. This bit rate -//! must satisfy the following clock ratio criteria: -//! - FSSI >= 2 * bit rate (master mode) -//! - FSSI >= 12 * bit rate (slave modes) -//! -//! where FSSI is the frequency of the clock supplied to the SSI module. -//! -//! The parameter \e ulDataWidth defines the width of the data transfers. -//! The parameter \e ulDataWidth can be a value between 4 and 16, inclusive. -//! -//! The SSI clocking is dependent upon the system clock rate returned by -//! SysCtlClockGet(); if it does not return the correct system clock rate then -//! the SSI clock rate will be incorrect. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_config) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SSIConfig(unsigned long ulBase, unsigned long ulProtocol, unsigned long ulMode, - unsigned long ulBitRate, unsigned long ulDataWidth) -{ - unsigned long ulMaxBitRate; - unsigned long ulRegVal; - unsigned long ulPreDiv; - unsigned long ulSCR; - unsigned long ulSPH_SPO; - unsigned long ulClock; - - // - // Check the arguments. - // - ASSERT(ulBase == SSI_BASE); - ASSERT((ulProtocol == SSI_FRF_MOTO_MODE_0) || - (ulProtocol == SSI_FRF_MOTO_MODE_1) || - (ulProtocol == SSI_FRF_MOTO_MODE_2) || - (ulProtocol == SSI_FRF_MOTO_MODE_3) || - (ulProtocol == SSI_FRF_TI) || - (ulProtocol == SSI_FRF_NMW)); - ASSERT((ulMode == SSI_MODE_MASTER) || - (ulMode == SSI_MODE_SLAVE) || - (ulMode == SSI_MODE_SLAVE_OD)); - ASSERT((ulDataWidth >= 4) && (ulDataWidth <= 16)); - - // - // Get the processor clock rate. - // - ulClock = SysCtlClockGet(); - - // - // Validate the clock speed. - // - ASSERT(((ulMode == SSI_MODE_MASTER) && (ulBitRate <= (ulClock / 2))) || - ((ulMode != SSI_MODE_MASTER) && (ulBitRate <= (ulClock / 12)))); - ASSERT((ulClock / ulBitRate) <= (254 * 256)); - - // - // Set the mode. - // - ulRegVal = (ulMode == SSI_MODE_SLAVE_OD) ? SSI_CR1_SOD : 0; - ulRegVal |= (ulMode == SSI_MODE_MASTER) ? 0 : SSI_CR1_MS; - HWREG(ulBase + SSI_O_CR1) = ulRegVal; - - // - // Set the clock predivider. - // - ulMaxBitRate = ulClock / ulBitRate; - ulPreDiv = 0; - do - { - ulPreDiv += 2; - ulSCR = (ulMaxBitRate / ulPreDiv) - 1; - } - while(ulSCR > 255); - HWREG(ulBase + SSI_O_CPSR) = ulPreDiv; - - // - // Set protocol and clock rate. - // - ulSPH_SPO = ulProtocol << 6; - ulProtocol &= SSI_CR0_FRF_MASK; - ulRegVal = (ulSCR << 8) | ulSPH_SPO | ulProtocol | (ulDataWidth - 1); - HWREG(ulBase + SSI_O_CR0) = ulRegVal; -} -#endif - -//***************************************************************************** -// -//! Enables the synchronous serial interface. -//! -//! \param ulBase specifies the SSI module base address. -//! -//! This will enable operation of the synchronous serial interface. It must be -//! configured before it is enabled. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SSIEnable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == SSI_BASE); - - // - // Read-modify-write the enable bit. - // - HWREG(ulBase + SSI_O_CR1) |= SSI_CR1_SSE; -} -#endif - -//***************************************************************************** -// -//! Disables the synchronous serial interface. -//! -//! \param ulBase specifies the SSI module base address. -//! -//! This will disable operation of the synchronous serial interface. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SSIDisable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == SSI_BASE); - - // - // Read-modify-write the enable bit. - // - HWREG(ulBase + SSI_O_CR1) &= ~(SSI_CR1_SSE); -} -#endif - -//***************************************************************************** -// -//! Registers an interrupt handler for the synchronous serial interface. -//! -//! \param ulBase specifies the SSI module base address. -//! \param pfnHandler is a pointer to the function to be called when the -//! synchronous serial interface interrupt occurs. -//! -//! This sets the handler to be called when an SSI interrupt -//! occurs. This will enable the global interrupt in the interrupt controller; -//! specific SSI interrupts must be enabled via SSIIntEnable(). If necessary, -//! it is the interrupt handler's responsibility to clear the interrupt source -//! via SSIIntClear(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SSIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT(ulBase == SSI_BASE); - - // - // Register the interrupt handler, returning an error if an error occurs. - // - IntRegister(INT_SSI, pfnHandler); - - // - // Enable the synchronous serial interface interrupt. - // - IntEnable(INT_SSI); -} -#endif - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the synchronous serial interface. -//! -//! \param ulBase specifies the SSI module base address. -//! -//! This function will clear the handler to be called when a SSI -//! interrupt occurs. This will also mask off the interrupt in the interrupt -//! controller so that the interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SSIIntUnregister(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == SSI_BASE); - - // - // Disable the interrupt. - // - IntDisable(INT_SSI); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_SSI); -} -#endif - -//***************************************************************************** -// -//! Enables individual SSI interrupt sources. -//! -//! \param ulBase specifies the SSI module base address. -//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. -//! -//! Enables the indicated SSI interrupt sources. Only the sources that are -//! enabled can be reflected to the processor interrupt; disabled sources -//! have no effect on the processor. The parameter \e ulIntFlags Can be -//! any of the SSI_TXFF, SSI_RXFF, SSI_RXTO, or SSI_RXOR values. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags) -{ - // - // Check the arguments. - // - ASSERT(ulBase == SSI_BASE); - - // - // Enable the specified interrupts. - // - HWREG(ulBase + SSI_O_IM) |= ulIntFlags; -} -#endif - -//***************************************************************************** -// -//! Disables individual SSI interrupt sources. -//! -//! \param ulBase specifies the SSI module base address. -//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. -//! -//! Disables the indicated SSI interrupt sources. The parameter -//! \e ulIntFlags Can be any of the SSI_TXFF, SSI_RXFF, SSI_RXTO, -//! or SSI_RXOR values. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags) -{ - // - // Check the arguments. - // - ASSERT(ulBase == SSI_BASE); - - // - // Disable the specified interrupts. - // - HWREG(ulBase + SSI_O_IM) &= ~(ulIntFlags); -} -#endif - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \param ulBase specifies the SSI module base address. -//! \param bMasked is false if the raw interrupt status is required and -//! true if the masked interrupt status is required. -//! -//! This returns the interrupt status for the SSI module. -//! Either the raw interrupt status or the status of interrupts that are -//! allowed to reflect to the processor can be returned. -//! -//! \return The current interrupt status, enumerated as a bit field of -//! SSI_TXFF, SSI_RXFF, SSI_RXTO, and SSI_RXOR. -// -//***************************************************************************** -#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -SSIIntStatus(unsigned long ulBase, tBoolean bMasked) -{ - // - // Check the arguments. - // - ASSERT(ulBase == SSI_BASE); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(ulBase + SSI_O_MIS)); - } - else - { - return(HWREG(ulBase + SSI_O_RIS)); - } -} -#endif - -//***************************************************************************** -// -//! Clears SSI interrupt sources. -//! -//! \param ulBase specifies the SSI module base address. -//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. -//! -//! The specified SSI interrupt sources are cleared, so that -//! they no longer assert. This must be done in the interrupt handler to -//! keep it from being called again immediately upon exit. -//! The parameter \e ulIntFlags can consist of either or both the SSI_RXTO -//! and SSI_RXOR values. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags) -{ - // - // Check the arguments. - // - ASSERT(ulBase == SSI_BASE); - - // - // Clear the requested interrupt sources. - // - HWREG(ulBase + SSI_O_ICR) = ulIntFlags; -} -#endif - -//***************************************************************************** -// -//! Puts a data element into the SSI transmit FIFO. -//! -//! \param ulBase specifies the SSI module base address. -//! \param ulData data to be transmitted over the SSI interface. -//! -//! This function will place the supplied data into the transmit FIFO of -//! the specified SSI module. -//! -//! \note The upper 32 - N bits of the \e ulData will be discarded by the -//! hardware, where N is the data width as configured by SSIConfig(). For -//! example, if the interface is configured for 8 bit data width, the upper 24 -//! bits of \e ulData will be discarded. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_dataput) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SSIDataPut(unsigned long ulBase, unsigned long ulData) -{ - // - // Check the arguments. - // - ASSERT(ulBase == SSI_BASE); - ASSERT((ulData & (0xfffffffe << (HWREG(ulBase + SSI_O_CR0) & - SSI_CR0_DSS))) == 0); - - // - // Wait until there is space. - // - while(!(HWREG(ulBase + SSI_O_SR) & SSI_SR_TNF)) - { - } - - // - // Write the data to the SSI. - // - HWREG(ulBase + SSI_O_DR) = ulData; -} -#endif - -//***************************************************************************** -// -//! Puts a data element into the SSI transmit FIFO. -//! -//! \param ulBase specifies the SSI module base address. -//! \param ulData data to be transmitted over the SSI interface. -//! -//! This function will place the supplied data into the transmit FIFO of -//! the specified SSI module. If there is no space in the FIFO, then this -//! function will return a zero. -//! -//! \note The upper 32 - N bits of the \e ulData will be discarded by the -//! hardware, where N is the data width as configured by SSIConfig(). For -//! example, if the interface is configured for 8 bit data width, the upper 24 -//! bits of \e ulData will be discarded. -//! -//! \return Returns the number of elements written to the SSI transmit FIFO. -// -//***************************************************************************** -#if defined(GROUP_datanonblockingput) || defined(BUILD_ALL) || defined(DOXYGEN) -long -SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData) -{ - // - // Check the arguments. - // - ASSERT(ulBase == SSI_BASE); - ASSERT((ulData & (0xfffffffe << (HWREG(ulBase + SSI_O_CR0) & - SSI_CR0_DSS))) == 0); - - // - // Check for space to write. - // - if(HWREG(ulBase + SSI_O_SR) & SSI_SR_TNF) - { - HWREG(ulBase + SSI_O_DR) = ulData; - return(1); - } - else - { - return(0); - } -} -#endif - -//***************************************************************************** -// -//! Gets a data element from the SSI receive FIFO. -//! -//! \param ulBase specifies the SSI module base address. -//! \param pulData pointer to a storage location for data that was received -//! over the SSI interface. -//! -//! This function will get received data from the receive FIFO of the specified -//! SSI module, and place that data into the location specified by the -//! \e pulData parameter. -//! -//! \note Only the lower N bits of the value written to \e pulData will contain -//! valid data, where N is the data width as configured by SSIConfig(). For -//! example, if the interface is configured for 8 bit data width, only the -//! lower 8 bits of the value written to \e pulData will contain valid data. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_dataget) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SSIDataGet(unsigned long ulBase, unsigned long *pulData) -{ - // - // Check the arguments. - // - ASSERT(ulBase == SSI_BASE); - - // - // Wait until there is data to be read. - // - while(!(HWREG(ulBase + SSI_O_SR) & SSI_SR_RNE)) - { - } - - // - // Read data from SSI. - // - *pulData = HWREG(ulBase + SSI_O_DR); -} -#endif - -//***************************************************************************** -// -//! Gets a data element from the SSI receive FIFO. -//! -//! \param ulBase specifies the SSI module base address. -//! \param pulData pointer to a storage location for data that was received -//! over the SSI interface. -//! -//! This function will get received data from the receive FIFO of -//! the specified SSI module, and place that data into the location specified -//! by the \e ulData parameter. If there is no data in the FIFO, then this -//! function will return a zero. -//! -//! \note Only the lower N bits of the value written to \e pulData will contain -//! valid data, where N is the data width as configured by SSIConfig(). For -//! example, if the interface is configured for 8 bit data width, only the -//! lower 8 bits of the value written to \e pulData will contain valid data. -//! -//! \return Returns the number of elements read from the SSI receive FIFO. -// -//***************************************************************************** -#if defined(GROUP_datanonblockingget) || defined(BUILD_ALL) || defined(DOXYGEN) -long -SSIDataNonBlockingGet(unsigned long ulBase, unsigned long *pulData) -{ - // - // Check the arguments. - // - ASSERT(ulBase == SSI_BASE); - - // - // Check for data to read. - // - if(HWREG(ulBase + SSI_O_SR) & SSI_SR_RNE) - { - *pulData = HWREG(ulBase + SSI_O_DR); - return(1); - } - else - { - return(0); - } -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/ssi.h b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/ssi.h deleted file mode 100644 index 045d8cb02..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/ssi.h +++ /dev/null @@ -1,89 +0,0 @@ -//***************************************************************************** -// -// ssi.h - Prototypes for the Synchronous Serial Interface Driver. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __SSI_H__ -#define __SSI_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear -// as the ulIntFlags parameter, and returned by SSIIntStatus. -// -//***************************************************************************** -#define SSI_TXFF 0x00000008 // TX FIFO half empty or less -#define SSI_RXFF 0x00000004 // RX FIFO half full or less -#define SSI_RXTO 0x00000002 // RX timeout -#define SSI_RXOR 0x00000001 // RX overrun - -//***************************************************************************** -// -// Values that can be passed to SSIConfig. -// -//***************************************************************************** -#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 -#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 -#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 -#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 -#define SSI_FRF_TI 0x00000010 // TI frame format -#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format - -#define SSI_MODE_MASTER 0x00000000 // SSI master -#define SSI_MODE_SLAVE 0x00000001 // SSI slave -#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void SSIConfig(unsigned long ulBase, unsigned long ulProtocol, - unsigned long ulMode, unsigned long ulBitRate, - unsigned long ulDataWidth); -extern void SSIDataGet(unsigned long ulBase, unsigned long *pulData); -extern long SSIDataNonBlockingGet(unsigned long ulBase, - unsigned long *pulData); -extern void SSIDataPut(unsigned long ulBase, unsigned long ulData); -extern long SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData); -extern void SSIDisable(unsigned long ulBase); -extern void SSIEnable(unsigned long ulBase); -extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags); -extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); -extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void SSIIntUnregister(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __SSI_H__ diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/sysctl.c b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/sysctl.c deleted file mode 100644 index 539d0f76d..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/sysctl.c +++ /dev/null @@ -1,1889 +0,0 @@ -//***************************************************************************** -// -// sysctl.c - Driver for the system controller. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. ALl rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup sysctl_api -//! @{ -// -//***************************************************************************** - -#include "../hw_ints.h" -#include "../hw_memmap.h" -#include "../hw_nvic.h" -#include "../hw_sysctl.h" -#include "../hw_types.h" -#include "cpu.h" -#include "debug.h" -#include "interrupt.h" -#include "sysctl.h" - -//***************************************************************************** -// -// An array that maps the "peripheral set" number (which is stored in the upper -// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL DC? register that -// contains the peripheral present bit for that peripheral. -// -//***************************************************************************** -#if defined(GROUP_puldcregs) || defined(BUILD_ALL) -const unsigned long g_pulDCRegs[] = -{ - SYSCTL_DC1, - SYSCTL_DC2, - SYSCTL_DC4, - SYSCTL_DC1 -}; -#else -extern const unsigned long g_pulDCRegs[]; -#endif - -//***************************************************************************** -// -// An array that maps the "peripheral set" number (which is stored in the upper -// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_SRCR? register that -// controls the software reset for that peripheral. -// -//***************************************************************************** -#if defined(GROUP_pulsrcrregs) || defined(BUILD_ALL) -const unsigned long g_pulSRCRRegs[] = -{ - SYSCTL_SRCR0, - SYSCTL_SRCR1, - SYSCTL_SRCR2 -}; -#else -extern const unsigned long g_pulSRCRRegs[]; -#endif - -//***************************************************************************** -// -// An array that maps the "peripheral set" number (which is stored in the upper -// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_RCGC? register that -// controls the run-mode enable for that peripheral. -// -//***************************************************************************** -#if defined(GROUP_pulrcgcregs) || defined(BUILD_ALL) -const unsigned long g_pulRCGCRegs[] = -{ - SYSCTL_RCGC0, - SYSCTL_RCGC1, - SYSCTL_RCGC2 -}; -#else -extern const unsigned long g_pulRCGCRegs[]; -#endif - -//***************************************************************************** -// -// An array that maps the "peripheral set" number (which is stored in the upper -// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_SCGC? register that -// controls the sleep-mode enable for that peripheral. -// -//***************************************************************************** -#if defined(GROUP_pulscgcregs) || defined(BUILD_ALL) -const unsigned long g_pulSCGCRegs[] = -{ - SYSCTL_SCGC0, - SYSCTL_SCGC1, - SYSCTL_SCGC2 -}; -#else -extern const unsigned long g_pulSCGCRegs[]; -#endif - -//***************************************************************************** -// -// An array that maps the "peripheral set" number (which is stored in the upper -// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_DCGC? register that -// controls the deep-sleep-mode enable for that peripheral. -// -//***************************************************************************** -#if defined(GROUP_pulDCGCregs) || defined(BUILD_ALL) -const unsigned long g_pulDCGCRegs[] = -{ - SYSCTL_DCGC0, - SYSCTL_DCGC1, - SYSCTL_DCGC2 -}; -#else -extern const unsigned long g_pulDCGCRegs[]; -#endif - -//***************************************************************************** -// -// An array that maps the crystal number in RCC to a frequency. -// -//***************************************************************************** -#if defined(GROUP_pulxtals) || defined(BUILD_ALL) -const unsigned long g_pulXtals[] = -{ - 3579545, - 3686400, - 4000000, - 4096000, - 4915200, - 5000000, - 5120000, - 6000000, - 6144000, - 7372800, - 8000000, - 8192000 -}; -#else -extern const unsigned long g_pulXtals[]; -#endif - -//***************************************************************************** -// -//! Gets the size of the SRAM. -//! -//! This function determines the size of the SRAM on the Stellaris device. -//! -//! \return The total number of bytes of SRAM. -// -//***************************************************************************** -#if defined(GROUP_sramsizeget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -SysCtlSRAMSizeGet(void) -{ - // - // Compute the size of the SRAM. - // - return(((HWREG(SYSCTL_DC0) & SYSCTL_DC0_SRAMSZ_MASK) >> 8) + 0x100); -} -#endif - -//***************************************************************************** -// -//! Gets the size of the flash. -//! -//! This function determines the size of the flash on the Stellaris device. -//! -//! \return The total number of bytes of flash. -// -//***************************************************************************** -#if defined(GROUP_flashsizeget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -SysCtlFlashSizeGet(void) -{ - // - // Compute the size of the flash. - // - return(((HWREG(SYSCTL_DC0) & SYSCTL_DC0_FLASHSZ_MASK) << 11) + 0x800); -} -#endif - -//***************************************************************************** -// -//! Determines if a pin is present. -//! -//! \param ulPin is the pin in question. -//! -//! Determines if a particular pin is present in the device. The PWM, analog -//! comparators, ADC, and timers have a varying number of pins across members -//! of the Stellaris family; this will determine which are present on this -//! device. -//! -//! The \b ulPin argument must be only one of the following values: -//! \b SYSCTL_PIN_PWM0, \b SYSCTL_PIN_PWM1, \b SYSCTL_PIN_PWM2, -//! \b SYSCTL_PIN_PWM3, \b SYSCTL_PIN_PWM4, \b SYSCTL_PIN_PWM5, -//! \b SYSCTL_PIN_C0MINUS, \b SYSCTL_PIN_C0PLUS, \b SYSCTL_PIN_C0O, -//! \b SYSCTL_PIN_C1MINUS, \b SYSCTL_PIN_C1PLUS, \b SYSCTL_PIN_C1O, -//! \b SYSCTL_PIN_C2MINUS, \b SYSCTL_PIN_C2PLUS, \b SYSCTL_PIN_C2O, -//! \b SYSCTL_PIN_ADC0, \b SYSCTL_PIN_ADC1, \b SYSCTL_PIN_ADC2, -//! \b SYSCTL_PIN_ADC3, \b SYSCTL_PIN_ADC4, \b SYSCTL_PIN_ADC5, -//! \b SYSCTL_PIN_ADC6, \b SYSCTL_PIN_ADC7, \b SYSCTL_PIN_CCP0, -//! \b SYSCTL_PIN_CCP1, \b SYSCTL_PIN_CCP2, \b SYSCTL_PIN_CCP3, -//! \b SYSCTL_PIN_CCP4, \b SYSCTL_PIN_CCP5, or \b SYSCTL_PIN_32KHZ. -//! -//! \return Returns \b true if the specified pin is present and \b false if it -//! is not. -// -//***************************************************************************** -#if defined(GROUP_pinpresent) || defined(BUILD_ALL) || defined(DOXYGEN) -tBoolean -SysCtlPinPresent(unsigned long ulPin) -{ - // - // Check the arguments. - // - ASSERT((ulPin == SYSCTL_PIN_PWM0) || - (ulPin == SYSCTL_PIN_PWM1) || - (ulPin == SYSCTL_PIN_PWM2) || - (ulPin == SYSCTL_PIN_PWM3) || - (ulPin == SYSCTL_PIN_PWM4) || - (ulPin == SYSCTL_PIN_PWM5) || - (ulPin == SYSCTL_PIN_C0MINUS) || - (ulPin == SYSCTL_PIN_C0PLUS) || - (ulPin == SYSCTL_PIN_C0O) || - (ulPin == SYSCTL_PIN_C1MINUS) || - (ulPin == SYSCTL_PIN_C1PLUS) || - (ulPin == SYSCTL_PIN_C1O) || - (ulPin == SYSCTL_PIN_C2MINUS) || - (ulPin == SYSCTL_PIN_C2PLUS) || - (ulPin == SYSCTL_PIN_C2O) || - (ulPin == SYSCTL_PIN_ADC0) || - (ulPin == SYSCTL_PIN_ADC1) || - (ulPin == SYSCTL_PIN_ADC2) || - (ulPin == SYSCTL_PIN_ADC3) || - (ulPin == SYSCTL_PIN_ADC4) || - (ulPin == SYSCTL_PIN_ADC5) || - (ulPin == SYSCTL_PIN_ADC6) || - (ulPin == SYSCTL_PIN_ADC7) || - (ulPin == SYSCTL_PIN_CCP0) || - (ulPin == SYSCTL_PIN_CCP1) || - (ulPin == SYSCTL_PIN_CCP2) || - (ulPin == SYSCTL_PIN_CCP3) || - (ulPin == SYSCTL_PIN_CCP4) || - (ulPin == SYSCTL_PIN_CCP5) || - (ulPin == SYSCTL_PIN_32KHZ)) - - // - // Determine if this pin is present. - // - if(HWREG(SYSCTL_DC3) & ulPin) - { - return(true); - } - else - { - return(false); - } -} -#endif - -//***************************************************************************** -// -//! Determines if a peripheral is present. -//! -//! \param ulPeripheral is the peripheral in question. -//! -//! Determines if a particular peripheral is present in the device. Each -//! member of the Stellaris family has a different peripheral set; this will -//! determine which are present on this device. -//! -//! The \b ulPeripheral argument must be only one of the following values: -//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, -//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, -//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, -//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, -//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, -//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, -//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_MPU, \b SYSCTL_PERIPH_TEMP, or -//! \b SYSCTL_PERIPH_PLL. -//! -//! \return Returns \b true if the specified peripheral is present and \b false -//! if it is not. -// -//***************************************************************************** -#if defined(GROUP_peripheralpresent) || defined(BUILD_ALL) || defined(DOXYGEN) -tBoolean -SysCtlPeripheralPresent(unsigned long ulPeripheral) -{ - // - // Check the arguments. - // - ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || - (ulPeripheral == SYSCTL_PERIPH_ADC) || - (ulPeripheral == SYSCTL_PERIPH_WDOG) || - (ulPeripheral == SYSCTL_PERIPH_UART0) || - (ulPeripheral == SYSCTL_PERIPH_UART1) || - (ulPeripheral == SYSCTL_PERIPH_SSI) || - (ulPeripheral == SYSCTL_PERIPH_QEI) || - (ulPeripheral == SYSCTL_PERIPH_I2C) || - (ulPeripheral == SYSCTL_PERIPH_TIMER0) || - (ulPeripheral == SYSCTL_PERIPH_TIMER1) || - (ulPeripheral == SYSCTL_PERIPH_TIMER2) || - (ulPeripheral == SYSCTL_PERIPH_COMP0) || - (ulPeripheral == SYSCTL_PERIPH_COMP1) || - (ulPeripheral == SYSCTL_PERIPH_COMP2) || - (ulPeripheral == SYSCTL_PERIPH_GPIOA) || - (ulPeripheral == SYSCTL_PERIPH_GPIOB) || - (ulPeripheral == SYSCTL_PERIPH_GPIOC) || - (ulPeripheral == SYSCTL_PERIPH_GPIOD) || - (ulPeripheral == SYSCTL_PERIPH_GPIOE) || - (ulPeripheral == SYSCTL_PERIPH_MPU) || - (ulPeripheral == SYSCTL_PERIPH_TEMP) || - (ulPeripheral == SYSCTL_PERIPH_PLL)); - - // - // Read the correct DC register and determine if this peripheral exists. - // - if(HWREG(g_pulDCRegs[ulPeripheral >> 28]) & ulPeripheral & 0x0fffffff) - { - return(true); - } - else - { - return(false); - } -} -#endif - -//***************************************************************************** -// -//! Performs a software reset of a peripheral. -//! -//! \param ulPeripheral is the peripheral to reset. -//! -//! This function performs a software reset of the specified peripheral. An -//! individual peripheral reset signal is asserted for a brief period and then -//! deasserted, leaving the peripheral in a operating state but in its reset -//! condition. -//! -//! The \b ulPeripheral argument must be only one of the following values: -//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, -//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, -//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, -//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, -//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, -//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or -//! \b SYSCTL_PERIPH_GPIOE. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_peripheralreset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysCtlPeripheralReset(unsigned long ulPeripheral) -{ - volatile unsigned long ulDelay; - - // - // Check the arguments. - // - ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || - (ulPeripheral == SYSCTL_PERIPH_ADC) || - (ulPeripheral == SYSCTL_PERIPH_WDOG) || - (ulPeripheral == SYSCTL_PERIPH_UART0) || - (ulPeripheral == SYSCTL_PERIPH_UART1) || - (ulPeripheral == SYSCTL_PERIPH_SSI) || - (ulPeripheral == SYSCTL_PERIPH_QEI) || - (ulPeripheral == SYSCTL_PERIPH_I2C) || - (ulPeripheral == SYSCTL_PERIPH_TIMER0) || - (ulPeripheral == SYSCTL_PERIPH_TIMER1) || - (ulPeripheral == SYSCTL_PERIPH_TIMER2) || - (ulPeripheral == SYSCTL_PERIPH_COMP0) || - (ulPeripheral == SYSCTL_PERIPH_COMP1) || - (ulPeripheral == SYSCTL_PERIPH_COMP2) || - (ulPeripheral == SYSCTL_PERIPH_GPIOA) || - (ulPeripheral == SYSCTL_PERIPH_GPIOB) || - (ulPeripheral == SYSCTL_PERIPH_GPIOC) || - (ulPeripheral == SYSCTL_PERIPH_GPIOD) || - (ulPeripheral == SYSCTL_PERIPH_GPIOE)); - - // - // Put the peripheral into the reset state. - // - HWREG(g_pulSRCRRegs[ulPeripheral >> 28]) |= ulPeripheral & 0x0fffffff; - - // - // Delay for a little bit. - // - for(ulDelay = 0; ulDelay < 16; ulDelay++) - { - } - - // - // Take the peripheral out of the reset state. - // - HWREG(g_pulSRCRRegs[ulPeripheral >> 28]) &= ~(ulPeripheral); -} -#endif - -//***************************************************************************** -// -//! Enables a peripheral. -//! -//! \param ulPeripheral is the peripheral to enable. -//! -//! Peripherals are enabled with this function. At power-up, all peripherals -//! are disabled; they must be enabled in order to operate or respond to -//! register reads/writes. -//! -//! The \b ulPeripheral argument must be only one of the following values: -//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, -//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, -//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, -//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, -//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, -//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or -//! \b SYSCTL_PERIPH_GPIOE. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_peripheralenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysCtlPeripheralEnable(unsigned long ulPeripheral) -{ - // - // Check the arguments. - // - ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || - (ulPeripheral == SYSCTL_PERIPH_ADC) || - (ulPeripheral == SYSCTL_PERIPH_WDOG) || - (ulPeripheral == SYSCTL_PERIPH_UART0) || - (ulPeripheral == SYSCTL_PERIPH_UART1) || - (ulPeripheral == SYSCTL_PERIPH_SSI) || - (ulPeripheral == SYSCTL_PERIPH_QEI) || - (ulPeripheral == SYSCTL_PERIPH_I2C) || - (ulPeripheral == SYSCTL_PERIPH_TIMER0) || - (ulPeripheral == SYSCTL_PERIPH_TIMER1) || - (ulPeripheral == SYSCTL_PERIPH_TIMER2) || - (ulPeripheral == SYSCTL_PERIPH_COMP0) || - (ulPeripheral == SYSCTL_PERIPH_COMP1) || - (ulPeripheral == SYSCTL_PERIPH_COMP2) || - (ulPeripheral == SYSCTL_PERIPH_GPIOA) || - (ulPeripheral == SYSCTL_PERIPH_GPIOB) || - (ulPeripheral == SYSCTL_PERIPH_GPIOC) || - (ulPeripheral == SYSCTL_PERIPH_GPIOD) || - (ulPeripheral == SYSCTL_PERIPH_GPIOE)); - - // - // Enable this peripheral. - // - HWREG(g_pulRCGCRegs[ulPeripheral >> 28]) |= ulPeripheral & 0x0fffffff; -} -#endif - -//***************************************************************************** -// -//! Disables a peripheral. -//! -//! \param ulPeripheral is the peripheral to disable. -//! -//! Peripherals are disabled with this function. Once disabled, they will not -//! operate or respond to register reads/writes. -//! -//! The \b ulPeripheral argument must be only one of the following values: -//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, -//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, -//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, -//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, -//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, -//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or -//! \b SYSCTL_PERIPH_GPIOE. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_peripheraldisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysCtlPeripheralDisable(unsigned long ulPeripheral) -{ - // - // Check the arguments. - // - ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || - (ulPeripheral == SYSCTL_PERIPH_ADC) || - (ulPeripheral == SYSCTL_PERIPH_WDOG) || - (ulPeripheral == SYSCTL_PERIPH_UART0) || - (ulPeripheral == SYSCTL_PERIPH_UART1) || - (ulPeripheral == SYSCTL_PERIPH_SSI) || - (ulPeripheral == SYSCTL_PERIPH_QEI) || - (ulPeripheral == SYSCTL_PERIPH_I2C) || - (ulPeripheral == SYSCTL_PERIPH_TIMER0) || - (ulPeripheral == SYSCTL_PERIPH_TIMER1) || - (ulPeripheral == SYSCTL_PERIPH_TIMER2) || - (ulPeripheral == SYSCTL_PERIPH_COMP0) || - (ulPeripheral == SYSCTL_PERIPH_COMP1) || - (ulPeripheral == SYSCTL_PERIPH_COMP2) || - (ulPeripheral == SYSCTL_PERIPH_GPIOA) || - (ulPeripheral == SYSCTL_PERIPH_GPIOB) || - (ulPeripheral == SYSCTL_PERIPH_GPIOC) || - (ulPeripheral == SYSCTL_PERIPH_GPIOD) || - (ulPeripheral == SYSCTL_PERIPH_GPIOE)); - - // - // Disable this peripheral. - // - HWREG(g_pulRCGCRegs[ulPeripheral >> 28]) &= ~(ulPeripheral & 0x0fffffff); -} -#endif - -//***************************************************************************** -// -//! Enables a peripheral in sleep mode. -//! -//! \param ulPeripheral is the peripheral to enable in sleep mode. -//! -//! This function allows a peripheral to continue operating when the processor -//! goes into sleep mode. Since the clocking configuration of the device does -//! not change, any peripheral can safely continue operating while the -//! processor is in sleep mode, and can therefore wake the processor from sleep -//! mode. -//! -//! Sleep mode clocking of peripherals must be enabled via -//! SysCtlPeripheralClockGating(); if disabled, the peripheral sleep mode -//! configuration is maintained but has no effect when sleep mode is entered. -//! -//! The \b ulPeripheral argument must be only one of the following values: -//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, -//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, -//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, -//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, -//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, -//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or -//! \b SYSCTL_PERIPH_GPIOE. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_peripheralsleepenable) || defined(BUILD_ALL) || \ - defined(DOXYGEN) -void -SysCtlPeripheralSleepEnable(unsigned long ulPeripheral) -{ - // - // Check the arguments. - // - ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || - (ulPeripheral == SYSCTL_PERIPH_ADC) || - (ulPeripheral == SYSCTL_PERIPH_WDOG) || - (ulPeripheral == SYSCTL_PERIPH_UART0) || - (ulPeripheral == SYSCTL_PERIPH_UART1) || - (ulPeripheral == SYSCTL_PERIPH_SSI) || - (ulPeripheral == SYSCTL_PERIPH_QEI) || - (ulPeripheral == SYSCTL_PERIPH_I2C) || - (ulPeripheral == SYSCTL_PERIPH_TIMER0) || - (ulPeripheral == SYSCTL_PERIPH_TIMER1) || - (ulPeripheral == SYSCTL_PERIPH_TIMER2) || - (ulPeripheral == SYSCTL_PERIPH_COMP0) || - (ulPeripheral == SYSCTL_PERIPH_COMP1) || - (ulPeripheral == SYSCTL_PERIPH_COMP2) || - (ulPeripheral == SYSCTL_PERIPH_GPIOA) || - (ulPeripheral == SYSCTL_PERIPH_GPIOB) || - (ulPeripheral == SYSCTL_PERIPH_GPIOC) || - (ulPeripheral == SYSCTL_PERIPH_GPIOD) || - (ulPeripheral == SYSCTL_PERIPH_GPIOE)); - - // - // Enable this peripheral in sleep mode. - // - HWREG(g_pulSCGCRegs[ulPeripheral >> 28]) |= ulPeripheral & 0x0fffffff; -} -#endif - -//***************************************************************************** -// -//! Disables a peripheral in sleep mode. -//! -//! \param ulPeripheral is the peripheral to disable in sleep mode. -//! -//! This function causes a peripheral to stop operating when the processor goes -//! into sleep mode. Disabling peripherals while in sleep mode helps to lower -//! the current draw of the device. If enabled (via SysCtlPeripheralEnable()), -//! the peripheral will automatically resume operation when the processor -//! leaves sleep mode, maintaining its entire state from before sleep mode was -//! entered. -//! -//! Sleep mode clocking of peripherals must be enabled via -//! SysCtlPeripheralClockGating(); if disabled, the peripheral sleep mode -//! configuration is maintained but has no effect when sleep mode is entered. -//! -//! The \b ulPeripheral argument must be only one of the following values: -//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, -//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, -//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, -//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, -//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, -//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or -//! \b SYSCTL_PERIPH_GPIOE. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_peripheralsleepdisable) || defined(BUILD_ALL) || \ - defined(DOXYGEN) -void -SysCtlPeripheralSleepDisable(unsigned long ulPeripheral) -{ - // - // Check the arguments. - // - ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || - (ulPeripheral == SYSCTL_PERIPH_ADC) || - (ulPeripheral == SYSCTL_PERIPH_WDOG) || - (ulPeripheral == SYSCTL_PERIPH_UART0) || - (ulPeripheral == SYSCTL_PERIPH_UART1) || - (ulPeripheral == SYSCTL_PERIPH_SSI) || - (ulPeripheral == SYSCTL_PERIPH_QEI) || - (ulPeripheral == SYSCTL_PERIPH_I2C) || - (ulPeripheral == SYSCTL_PERIPH_TIMER0) || - (ulPeripheral == SYSCTL_PERIPH_TIMER1) || - (ulPeripheral == SYSCTL_PERIPH_TIMER2) || - (ulPeripheral == SYSCTL_PERIPH_COMP0) || - (ulPeripheral == SYSCTL_PERIPH_COMP1) || - (ulPeripheral == SYSCTL_PERIPH_COMP2) || - (ulPeripheral == SYSCTL_PERIPH_GPIOA) || - (ulPeripheral == SYSCTL_PERIPH_GPIOB) || - (ulPeripheral == SYSCTL_PERIPH_GPIOC) || - (ulPeripheral == SYSCTL_PERIPH_GPIOD) || - (ulPeripheral == SYSCTL_PERIPH_GPIOE)); - - // - // Disable this peripheral in sleep mode. - // - HWREG(g_pulSCGCRegs[ulPeripheral >> 28]) &= ~(ulPeripheral & 0x0fffffff); -} -#endif - -//***************************************************************************** -// -//! Enables a peripheral in deep-sleep mode. -//! -//! \param ulPeripheral is the peripheral to enable in deep-sleep mode. -//! -//! This function allows a peripheral to continue operating when the processor -//! goes into deep-sleep mode. Since the clocking configuration of the device -//! may change, not all peripherals can safely continue operating while the -//! processor is in sleep mode. Those that must run at a particular frequency -//! (such as a UART) will not work as expected if the clock changes. It is the -//! responsibility of the caller to make sensible choices. -//! -//! Deep-sleep mode clocking of peripherals must be enabled via -//! SysCtlPeripheralClockGating(); if disabled, the peripheral deep-sleep mode -//! configuration is maintained but has no effect when deep-sleep mode is -//! entered. -//! -//! The \b ulPeripheral argument must be one of the following values: -//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, -//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, -//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, -//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, -//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, -//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or -//! \b SYSCTL_PERIPH_GPIOE. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_peripheraldeepsleepenable) || defined(BUILD_ALL) || \ - defined(DOXYGEN) -void -SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral) -{ - // - // Check the arguments. - // - ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || - (ulPeripheral == SYSCTL_PERIPH_ADC) || - (ulPeripheral == SYSCTL_PERIPH_WDOG) || - (ulPeripheral == SYSCTL_PERIPH_UART0) || - (ulPeripheral == SYSCTL_PERIPH_UART1) || - (ulPeripheral == SYSCTL_PERIPH_SSI) || - (ulPeripheral == SYSCTL_PERIPH_QEI) || - (ulPeripheral == SYSCTL_PERIPH_I2C) || - (ulPeripheral == SYSCTL_PERIPH_TIMER0) || - (ulPeripheral == SYSCTL_PERIPH_TIMER1) || - (ulPeripheral == SYSCTL_PERIPH_TIMER2) || - (ulPeripheral == SYSCTL_PERIPH_COMP0) || - (ulPeripheral == SYSCTL_PERIPH_COMP1) || - (ulPeripheral == SYSCTL_PERIPH_COMP2) || - (ulPeripheral == SYSCTL_PERIPH_GPIOA) || - (ulPeripheral == SYSCTL_PERIPH_GPIOB) || - (ulPeripheral == SYSCTL_PERIPH_GPIOC) || - (ulPeripheral == SYSCTL_PERIPH_GPIOD) || - (ulPeripheral == SYSCTL_PERIPH_GPIOE)); - - // - // Enable this peripheral in deep-sleep mode. - // - HWREG(g_pulDCGCRegs[ulPeripheral >> 28]) |= ulPeripheral & 0x0fffffff; -} -#endif - -//***************************************************************************** -// -//! Disables a peripheral in deep-sleep mode. -//! -//! \param ulPeripheral is the peripheral to disable in deep-sleep mode. -//! -//! This function causes a peripheral to stop operating when the processor goes -//! into deep-sleep mode. Disabling peripherals while in deep-sleep mode helps -//! to lower the current draw of the device, and can keep peripherals that -//! require a particular clock frequency from operating when the clock changes -//! as a result of entering deep-sleep mode. If enabled (via -//! SysCtlPeripheralEnable()), the peripheral will automatically resume -//! operation when the processor leaves deep-sleep mode, maintaining its entire -//! state from before deep-sleep mode was entered. -//! -//! Deep-sleep mode clocking of peripherals must be enabled via -//! SysCtlPeripheralClockGating(); if disabled, the peripheral deep-sleep mode -//! configuration is maintained but has no effect when deep-sleep mode is -//! entered. -//! -//! The \b ulPeripheral argument must be one of the following values: -//! \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_WDOG, -//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_SSI, -//! \b SYSCTL_PERIPH_QEI, \b SYSCTL_PERIPH_I2C, \b SYSCTL_PERIPH_TIMER0, -//! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_COMP0, -//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_GPIOA, -//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, or -//! \b SYSCTL_PERIPH_GPIOE. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_peripheraldeepsleepdisable) || defined(BUILD_ALL) || \ - defined(DOXYGEN) -void -SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral) -{ - // - // Check the arguments. - // - ASSERT((ulPeripheral == SYSCTL_PERIPH_PWM) || - (ulPeripheral == SYSCTL_PERIPH_ADC) || - (ulPeripheral == SYSCTL_PERIPH_WDOG) || - (ulPeripheral == SYSCTL_PERIPH_UART0) || - (ulPeripheral == SYSCTL_PERIPH_UART1) || - (ulPeripheral == SYSCTL_PERIPH_SSI) || - (ulPeripheral == SYSCTL_PERIPH_QEI) || - (ulPeripheral == SYSCTL_PERIPH_I2C) || - (ulPeripheral == SYSCTL_PERIPH_TIMER0) || - (ulPeripheral == SYSCTL_PERIPH_TIMER1) || - (ulPeripheral == SYSCTL_PERIPH_TIMER2) || - (ulPeripheral == SYSCTL_PERIPH_COMP0) || - (ulPeripheral == SYSCTL_PERIPH_COMP1) || - (ulPeripheral == SYSCTL_PERIPH_COMP2) || - (ulPeripheral == SYSCTL_PERIPH_GPIOA) || - (ulPeripheral == SYSCTL_PERIPH_GPIOB) || - (ulPeripheral == SYSCTL_PERIPH_GPIOC) || - (ulPeripheral == SYSCTL_PERIPH_GPIOD) || - (ulPeripheral == SYSCTL_PERIPH_GPIOE)); - - // - // Disable this peripheral in deep-sleep mode. - // - HWREG(g_pulDCGCRegs[ulPeripheral >> 28]) &= ~(ulPeripheral & 0x0fffffff); -} -#endif - -//***************************************************************************** -// -//! Controls peripheral clock gating in sleep and deep-sleep mode. -//! -//! \param bEnable is a boolean that is \b true if the sleep and deep-sleep -//! peripheral configuration should be used and \b false if not. -//! -//! This function controls how peripherals are clocked when the processor goes -//! into sleep or deep-sleep mode. By default, the peripherals are clocked the -//! same as in run mode; if peripheral clock gating is enabled they are clocked -//! according to the configuration set by SysCtlPeripheralSleepEnable(), -//! SysCtlPeripheralSleepDisable(), SysCtlPeripheralDeepSleepEnable(), and -//! SysCtlPeripheralDeepSleepDisable(). -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_peripheralclockgating) || defined(BUILD_ALL) || \ - defined(DOXYGEN) -void -SysCtlPeripheralClockGating(tBoolean bEnable) -{ - // - // Enable peripheral clock gating as requested. - // - if(bEnable) - { - HWREG(SYSCTL_RCC) |= SYSCTL_RCC_ACG; - } - else - { - HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_ACG); - } -} -#endif - -//***************************************************************************** -// -//! Registers an interrupt handler for the system control interrupt. -//! -//! \param pfnHandler is a pointer to the function to be called when the system -//! control interrupt occurs. -//! -//! This sets the handler to be called when a system control interrupt occurs. -//! This will enable the global interrupt in the interrupt controller; specific -//! system control interrupts must be enabled via SysCtlIntEnable(). It is the -//! interrupt handler's responsibility to clear the interrupt source via -//! SysCtlIntClear(). -//! -//! System control can generate interrupts when the PLL achieves lock, if the -//! internal LDO current limit is exceeded, if the internal oscillator fails, -//! if the main oscillator fails, if the internal LDO output voltage droops too -//! much, if the external voltage droops too much, or if the PLL fails. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysCtlIntRegister(void (*pfnHandler)(void)) -{ - // - // Register the interrupt handler, returning an error if an error occurs. - // - IntRegister(INT_SYSCTL, pfnHandler); - - // - // Enable the system control interrupt. - // - IntEnable(INT_SYSCTL); -} -#endif - -//***************************************************************************** -// -//! Unregisters the interrupt handler for the system control interrupt. -//! -//! This function will clear the handler to be called when a system control -//! interrupt occurs. This will also mask off the interrupt in the interrupt -//! controller so that the interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysCtlIntUnregister(void) -{ - // - // Disable the interrupt. - // - IntDisable(INT_SYSCTL); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_SYSCTL); -} -#endif - -//***************************************************************************** -// -//! Enables individual system control interrupt sources. -//! -//! \param ulInts is a bit mask of the interrupt sources to be enabled. Must -//! be a logical OR of \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT, -//! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR, -//! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL. -//! -//! Enables the indicated system control interrupt sources. Only the sources -//! that are enabled can be reflected to the processor interrupt; disabled -//! sources have no effect on the processor. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysCtlIntEnable(unsigned long ulInts) -{ - // - // Enable the specified interrupts. - // - HWREG(SYSCTL_IMC) |= ulInts; -} -#endif - -//***************************************************************************** -// -//! Disables individual system control interrupt sources. -//! -//! \param ulInts is a bit mask of the interrupt sources to be disabled. Must -//! be a logical OR of \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT, -//! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR, -//! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL. -//! -//! Disables the indicated system control interrupt sources. Only the sources -//! that are enabled can be reflected to the processor interrupt; disabled -//! sources have no effect on the processor. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysCtlIntDisable(unsigned long ulInts) -{ - // - // Disable the specified interrupts. - // - HWREG(SYSCTL_IMC) &= ~(ulInts); -} -#endif - -//***************************************************************************** -// -//! Clears system control interrupt sources. -//! -//! \param ulInts is a bit mask of the interrupt sources to be cleared. Must -//! be a logical OR of \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT, -//! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR, -//! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL. -//! -//! The specified system control interrupt sources are cleared, so that they no -//! longer assert. This must be done in the interrupt handler to keep it from -//! being called again immediately upon exit. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysCtlIntClear(unsigned long ulInts) -{ - // - // Clear the requested interrupt sources. - // - HWREG(SYSCTL_MISC) = ulInts; -} -#endif - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \param bMasked is false if the raw interrupt status is required and true if -//! the masked interrupt status is required. -//! -//! This returns the interrupt status for the system controller. Either the -//! raw interrupt status or the status of interrupts that are allowed to -//! reflect to the processor can be returned. -//! -//! \return The current interrupt status, enumerated as a bit field of -//! \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT, \b SYSCTL_INT_IOSC_FAIL, -//! \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR, \b SYSCTL_INT_BOR, and -//! \b SYSCTL_INT_PLL_FAIL. -// -//***************************************************************************** -#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -SysCtlIntStatus(tBoolean bMasked) -{ - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(SYSCTL_MISC)); - } - else - { - return(HWREG(SYSCTL_RIS)); - } -} -#endif - -//***************************************************************************** -// -//! Sets the output voltage of the LDO. -//! -//! \param ulVoltage is the required output voltage from the LDO. Must be one -//! of \b SYSCTL_LDO_2_25V, \b SYSCTL_LDO_2_30V, \b SYSCTL_LDO_2_35V, -//! \b SYSCTL_LDO_2_40V, \b SYSCTL_LDO_2_45V, \b SYSCTL_LDO_2_50V, -//! \b SYSCTL_LDO_2_55V, \b SYSCTL_LDO_2_60V, \b SYSCTL_LDO_2_65V, -//! \b SYSCTL_LDO_2_70V, or \b SYSCTL_LDO_2_75V. -//! -//! This function sets the output voltage of the LDO. The default voltage is -//! 2.5 V; it can be adjusted +/- 10%. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_ldoset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysCtlLDOSet(unsigned long ulVoltage) -{ - // - // Check the arguments. - // - ASSERT((ulVoltage == SYSCTL_LDO_2_25V) || - (ulVoltage == SYSCTL_LDO_2_30V) || - (ulVoltage == SYSCTL_LDO_2_35V) || - (ulVoltage == SYSCTL_LDO_2_40V) || - (ulVoltage == SYSCTL_LDO_2_45V) || - (ulVoltage == SYSCTL_LDO_2_50V) || - (ulVoltage == SYSCTL_LDO_2_55V) || - (ulVoltage == SYSCTL_LDO_2_60V) || - (ulVoltage == SYSCTL_LDO_2_65V) || - (ulVoltage == SYSCTL_LDO_2_70V) || - (ulVoltage == SYSCTL_LDO_2_75V)); - - // - // Set the LDO voltage to the requested value. - // - HWREG(SYSCTL_LDOPCTL) = ulVoltage; -} -#endif - -//***************************************************************************** -// -//! Gets the output voltage of the LDO. -//! -//! This function determines the output voltage of the LDO, as specified by the -//! control register. -//! -//! \return Returns the current voltage of the LDO; will be one of -//! \b SYSCTL_LDO_2_25V, \b SYSCTL_LDO_2_30V, \b SYSCTL_LDO_2_35V, -//! \b SYSCTL_LDO_2_40V, \b SYSCTL_LDO_2_45V, \b SYSCTL_LDO_2_50V, -//! \b SYSCTL_LDO_2_55V, \b SYSCTL_LDO_2_60V, \b SYSCTL_LDO_2_65V, -//! \b SYSCTL_LDO_2_70V, or \b SYSCTL_LDO_2_75V. -// -//***************************************************************************** -#if defined(GROUP_ldoget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -SysCtlLDOGet(void) -{ - // - // Return the LDO voltage setting. - // - return(HWREG(SYSCTL_LDOPCTL)); -} -#endif - -//***************************************************************************** -// -//! Configures the LDO failure control. -//! -//! \param ulConfig is the required LDO failure control setting; can be either -//! \b SYSCTL_LDOCFG_ARST or \b SYSCTL_LDOCFG_NORST. -//! -//! This function allows the LDO to be configured to cause a processor reset -//! when the output voltage becomes unregulated. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_ldoconfigset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysCtlLDOConfigSet(unsigned long ulConfig) -{ - // - // Check hte arguments. - // - ASSERT((ulConfig == SYSCTL_LDOCFG_ARST) || - (ulConfig == SYSCTL_LDOCFG_NORST)); - - // - // Set the reset control as requested. - // - HWREG(SYSCTL_LDOARST) = ulConfig; -} -#endif - -//***************************************************************************** -// -//! Resets the device. -//! -//! This function will perform a software reset of the entire device. The -//! processor and all peripherals will be reset and all device registers will -//! return to their default values (with the exception of the reset cause -//! register, which will maintain its current value but have the software reset -//! bit set as well). -//! -//! \return This function does not return. -// -//***************************************************************************** -#if defined(GROUP_reset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysCtlReset(void) -{ - // - // Perform a software reset request. This will cause the device to reset, - // no further code will be executed. - // - HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | NVIC_APINT_SYSRESETREQ; - - // - // The device should have reset, so this should never be reached. Just in - // case, loop forever. - // - while(1) - { - } -} -#endif - -//***************************************************************************** -// -//! Puts the processor into sleep mode. -//! -//! This function places the processor into sleep mode; it will not return -//! until the processor returns to run mode. The peripherals that are enabled -//! via SysCtlPeripheralSleepEnable() continue to operate and can wake up the -//! processor (if automatic clock gating is enabled with -//! SysCtlPeripheralClockGating(), otherwise all peripherals continue to -//! operate). -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_sleep) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysCtlSleep(void) -{ - // - // Wait for an interrupt. - // - CPUwfi(); -} -#endif - -//***************************************************************************** -// -//! Puts the processor into deep-sleep mode. -//! -//! This function places the processor into deep-sleep mode; it will not return -//! until the processor returns to run mode. The peripherals that are enabled -//! via SysCtlPeripheralDeepSleepEnable() continue to operate and can wake up -//! the processor (if automatic clock gating is enabled with -//! SysCtlPeripheralClockGating(), otherwise all peripherals continue to -//! operate). -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_deepsleep) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysCtlDeepSleep(void) -{ - // - // Enable deep-sleep. - // - HWREG(NVIC_SYS_CTRL) |= NVIC_SYS_CTRL_SLEEPDEEP; - - // - // Wait for an interrupt. - // - CPUwfi(); - - // - // Disable deep-sleep so that a future sleep will work correctly. - // - HWREG(NVIC_SYS_CTRL) &= ~(NVIC_SYS_CTRL_SLEEPDEEP); -} -#endif - -//***************************************************************************** -// -//! Gets the reason for a reset. -//! -//! This function will return the reason(s) for a reset. Since the reset -//! reasons are sticky until either cleared by software or an external reset, -//! multiple reset reasons may be returned if multiple resets have occurred. -//! The reset reason will be a logical OR of \b SYSCTL_CAUSE_LDO, -//! \b SYSCTL_CAUSE_SW, \b SYSCTL_CAUSE_WDOG, \b SYSCTL_CAUSE_BOR, -//! \b SYSCTL_CAUSE_POR, and/or \b SYSCTL_CAUSE_EXT. -//! -//! \return The reason(s) for a reset. -// -//***************************************************************************** -#if defined(GROUP_resetcauseget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -SysCtlResetCauseGet(void) -{ - // - // Return the reset reasons. - // - return(HWREG(SYSCTL_RESC)); -} -#endif - -//***************************************************************************** -// -//! Clears reset reasons. -//! -//! \param ulCauses are the reset causes to be cleared; must be a logical OR of -//! \b SYSCTL_CAUSE_LDO, \b SYSCTL_CAUSE_SW, \b SYSCTL_CAUSE_WDOG, -//! \b SYSCTL_CAUSE_BOR, \b SYSCTL_CAUSE_POR, and/or \b SYSCTL_CAUSE_EXT. -//! -//! This function clears the specified sticky reset reasons. Once cleared, -//! another reset for the same reason can be detected, and a reset for a -//! different reason can be distinguished (instead of having two reset causes -//! set). If the reset reason is used by an application, all reset causes -//! should be cleared after they are retrieved with SysCtlResetCauseGet(). -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_resetcauseclear) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysCtlResetCauseClear(unsigned long ulCauses) -{ - // - // Clear the given reset reasons. - // - HWREG(SYSCTL_RESC) &= ~(ulCauses); -} -#endif - -//***************************************************************************** -// -//! Configures the brown-out control. -//! -//! \param ulConfig is the desired configuration of the brown-out control. -//! Must be the logical OR of \b SYSCTL_BOR_RESET and/or -//! \b SYSCTL_BOR_RESAMPLE. -//! \param ulDelay is the number of internal oscillator cycles to wait before -//! resampling an asserted brown-out signal. This value only has meaning when -//! \b SYSCTL_BOR_RESAMPLE is set and must be less than 8192. -//! -//! This function configures how the brown-out control operates. It can detect -//! a brown-out by looking at only the brown-out output, or it can wait for it -//! to be active for two consecutive samples separated by a configurable time. -//! When it detects a brown-out condition, it can either reset the device or -//! generate a processor interrupt. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_brownoutconfigset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysCtlBrownOutConfigSet(unsigned long ulConfig, unsigned long ulDelay) -{ - // - // Check the arguments. - // - ASSERT(!(ulConfig & ~(SYSCTL_BOR_RESET | SYSCTL_BOR_RESAMPLE))); - ASSERT(ulDelay < 8192); - - // - // Configure the brown-out reset control. - // - HWREG(SYSCTL_PBORCTL) = (ulDelay << SYSCTL_PBORCTL_BOR_SH) | ulConfig; -} -#endif - -//***************************************************************************** -// -//! Sets the clocking of the device. -//! -//! \param ulConfig is the required configuration of the device clocking. -//! -//! This function configures the clocking of the device. The input crystal -//! frequency, oscillator to be used, use of the PLL, and the system clock -//! divider are all configured with this function. -//! -//! The \b ulConfig parameter is the logical OR of several different values, -//! many of which are grouped into sets where only one can be chosen. -//! -//! The system clock divider is chosen with one of the following values: -//! \b SYSCTL_SYSDIV_1, \b SYSCTL_SYSDIV_2, \b SYSCTL_SYSDIV_3, -//! \b SYSCTL_SYSDIV_4, \b SYSCTL_SYSDIV_5, \b SYSCTL_SYSDIV_6, -//! \b SYSCTL_SYSDIV_7, \b SYSCTL_SYSDIV_8, \b SYSCTL_SYSDIV_9, -//! \b SYSCTL_SYSDIV_10, \b SYSCTL_SYSDIV_11, \b SYSCTL_SYSDIV_12, -//! \b SYSCTL_SYSDIV_13, \b SYSCTL_SYSDIV_14, \b SYSCTL_SYSDIV_15, or -//! \b SYSCTL_SYSDIV_16. -//! -//! The use of the PLL is chosen with either \b SYSCTL_USE_PLL or -//! \b SYSCTL_USE_OSC. -//! -//! The external crystal frequency is chosen with one of the following values: -//! \b SYSCTL_XTAL_3_57MHZ, \b SYSCTL_XTAL_3_68MHZ, \b SYSCTL_XTAL_4MHZ, -//! \b SYSCTL_XTAL_4_09MHZ, \b SYSCTL_XTAL_4_91MHZ, \b SYSCTL_XTAL_5MHZ, -//! \b SYSCTL_XTAL_5_12MHZ, \b SYSCTL_XTAL_6MHZ, \b SYSCTL_XTAL_6_14MHZ, -//! \b SYSCTL_XTAL_7_37MHZ, \b SYSCTL_XTAL_8MHZ, or \b SYSCTL_XTAL_8_19MHZ. -//! -//! The oscillator source is chosen with one of the following values: -//! \b SYSCTL_OSC_MAIN, \b SYSCTL_OSC_INT, or \b SYSCTL_OSC_INT4. -//! -//! The internal and main oscillators are disabled with the -//! \b SYSCTL_INT_OSC_DIS and \b SYSCTL_MAIN_OSC_DIS flags, respectively. -//! The external oscillator must be enabled in order to use an external clock -//! source. Note that attempts to disable the oscillator used to clock the -//! device will be prevented by the hardware. -//! -//! To clock the system from an external source (such as an external crystal -//! oscillator), use \b SYSCTL_USE_OSC \b | \b SYSCTL_OSC_MAIN. To clock the -//! system from the main oscillator, use \b SYSCTL_USE_OSC \b | -//! \b SYSCTL_OSC_MAIN. To clock the system from the PLL, use -//! \b SYSCTL_USE_PLL \b | \b SYSCTL_OSC_MAIN, and select the appropriate -//! crystal with one of the \b SYSCTL_XTAL_xxx values. -//! -//! \note If selecting the PLL as the system clock source (i.e. via -//! \b SYSCTL_USE_PLL), this function will poll the PLL lock interrupt to -//! determine when the PLL has locked. If an interrupt handler for the -//! system control interrupt is in place, and it responds to and clears the -//! PLL lock interrupt, this function will delay until its timeout has occurred -//! instead of completing as soon as PLL lock is achieved. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_clockset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysCtlClockSet(unsigned long ulConfig) -{ - volatile unsigned long ulDelay; - unsigned long ulRCC; - - // - // Get the current value of the RCC register. - // - ulRCC = HWREG(SYSCTL_RCC); - - // - // Bypass the PLL and system clock dividers for now. - // - ulRCC |= SYSCTL_RCC_BYPASS; - ulRCC &= ~(SYSCTL_RCC_USE_SYSDIV); - - // - // Write the new RCC value. - // - HWREG(SYSCTL_RCC) = ulRCC; - - // - // Make sure that the PLL and system clock dividers are bypassed for now. - // - ulRCC |= SYSCTL_RCC_BYPASS; - ulRCC &= ~(SYSCTL_RCC_USE_SYSDIV); - - // - // Make sure that the required oscillators are enabled. For now, the - // previously enabled oscillators must be enabled along with the newly - // requested oscillators. - // - ulRCC &= (~(SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS) | - (ulConfig & (SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS))); - - // - // Set the new crystal value, oscillator source, and PLL configuration. - // - ulRCC &= ~(SYSCTL_RCC_XTAL_MASK | SYSCTL_RCC_OSCSRC_MASK | - SYSCTL_RCC_PWRDN | SYSCTL_RCC_OE); - ulRCC |= ulConfig & (SYSCTL_RCC_XTAL_MASK | SYSCTL_RCC_OSCSRC_MASK | - SYSCTL_RCC_PWRDN | SYSCTL_RCC_OE); - - // - // Clear the PLL lock interrupt. - // - HWREG(SYSCTL_MISC) = SYSCTL_INT_PLL_LOCK; - - // - // Write the new RCC value. - // - HWREG(SYSCTL_RCC) = ulRCC; - - // - // Wait for a bit so that new crystal value and oscillator source can take - // effect. One of the oscillators may need to be started as well. - // - for(ulDelay = 0; ulDelay < 16; ulDelay++) - { - } - - // - // Disable the appropriate oscillators. - // - ulRCC &= ~(SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS); - ulRCC |= ulConfig & (SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS); - - // - // Write the new RCC value. - // - HWREG(SYSCTL_RCC) = ulRCC; - - // - // Set the requested system divider. This will not get written - // immediately. - // - ulRCC &= ~(SYSCTL_RCC_SYSDIV_MASK | SYSCTL_RCC_USE_SYSDIV); - ulRCC |= ulConfig & (SYSCTL_RCC_SYSDIV_MASK | SYSCTL_RCC_USE_SYSDIV); - - // - // See if the PLL output is being used to clock the system. - // - if(!(ulConfig & SYSCTL_RCC_BYPASS)) - { - // - // Wait until the PLL has locked. - // - for(ulDelay = 32768; ulDelay > 0; ulDelay--) - { - if(HWREG(SYSCTL_RIS) & SYSCTL_INT_PLL_LOCK) - { - break; - } - } - - // - // Enable use of the PLL. - // - ulRCC &= ~(SYSCTL_RCC_BYPASS); - } - - // - // Write the final RCC value. - // - HWREG(SYSCTL_RCC) = ulRCC; - - // - // Delay for a little bit so that the system divider takes effect. - // - for(ulDelay = 0; ulDelay < 16; ulDelay++) - { - } -} -#endif - -//***************************************************************************** -// -//! Gets the processor clock rate. -//! -//! This function determines the clock rate of the processor clock. This is -//! also the clock rate of all the peripheral modules (with the exception of -//! PWM, which has its own clock divider). -//! -//! \note This will not return accurate results if SysCtlClockSet() has not -//! been called to configure the clocking of the device, or if the device is -//! directly clocked from a crystal (or a clock source) that is not one of the -//! supported crystal frequencies. In the later case, this function should be -//! modified to directly return the correct system clock rate. -//! -//! \return The processor clock rate. -// -//***************************************************************************** -#if defined(GROUP_clockget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -SysCtlClockGet(void) -{ - unsigned long ulRCC, ulPLL, ulClk; - - // - // Read RCC. - // - ulRCC = HWREG(SYSCTL_RCC); - - // - // Get the base clock rate. - // - switch(ulRCC & SYSCTL_RCC_OSCSRC_MASK) - { - // - // The main oscillator is the clock source. Determine its rate from - // the crystal setting field. - // - case SYSCTL_RCC_OSCSRC_MAIN: - { - ulClk = g_pulXtals[((ulRCC & SYSCTL_RCC_XTAL_MASK) >> - SYSCTL_RCC_XTAL_SHIFT) - - (SYSCTL_RCC_XTAL_3_57MHZ >> - SYSCTL_RCC_XTAL_SHIFT)]; - break; - } - - // - // The internal oscillator is the source clock. This is not an - // accurate clock (it is +/- 50%); what is used is the nominal. - // - case SYSCTL_RCC_OSCSRC_INT: - { - ulClk = 15000000; - break; - } - - // - // The internal oscillator divided by four is the source clock. This - // is not an accurate clock (it is +/- 50%); what is used is the - // nominal. - // - case SYSCTL_RCC_OSCSRC_INT4: - { - ulClk = 15000000 / 4; - break; - } - - // - // An unknown setting, so return a zero clock (i.e. an unknown clock - // rate). - // - default: - { - return(0); - } - } - - // - // See if the PLL is being used. - // - if(!(ulRCC & SYSCTL_RCC_BYPASS)) - { - // - // Get the PLL configuration. - // - ulPLL = HWREG(SYSCTL_PLLCFG); - - // - // Compute the PLL output frequency based on its input frequency. - // - ulClk = ((ulClk * (((ulPLL & SYSCTL_PLLCFG_F_MASK) >> - SYSCTL_PLLCFG_F_SHIFT) + 2)) / - (((ulPLL & SYSCTL_PLLCFG_R_MASK) >> - SYSCTL_PLLCFG_R_SHIFT) + 2)); - - // - // See if the optional output divide by 2 is being used. - // - if(ulPLL & SYSCTL_PLLCFG_OD_2) - { - ulClk /= 2; - } - - // - // See if the optional output divide by 4 is being used. - // - if(ulPLL & SYSCTL_PLLCFG_OD_4) - { - ulClk /= 4; - } - } - - // - // See if the system divider is being used. - // - if(ulRCC & SYSCTL_RCC_USE_SYSDIV) - { - // - // Adjust the clock rate by the system clock divider. - // - ulClk /= ((ulRCC & SYSCTL_RCC_SYSDIV_MASK) >> - SYSCTL_RCC_SYSDIV_SHIFT) + 1; - } - - // - // Return the computed clock rate. - // - return(ulClk); -} -#endif - -//***************************************************************************** -// -//! Sets the PWM clock configuration. -//! -//! \param ulConfig is the configuration for the PWM clock; it must be one of -//! \b SYSCTL_PWMDIV_1, \b SYSCTL_PWMDIV_2, \b SYSCTL_PWMDIV_4, -//! \b SYSCTL_PWMDIV_8, \b SYSCTL_PWMDIV_16, \b SYSCTL_PWMDIV_32, or -//! \b SYSCTL_PWMDIV_64. -//! -//! This function sets the rate of the clock provided to the PWM module as a -//! ratio of the processor clock. This clock is used by the PWM module to -//! generate PWM signals; its rate forms the basis for all PWM signals. -//! -//! \note The clocking of the PWM is dependent upon the system clock rate as -//! configured by SysCtlClockSet(). -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_pwmclockset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysCtlPWMClockSet(unsigned long ulConfig) -{ - // - // Check the arguments. - // - ASSERT((ulConfig == SYSCTL_PWMDIV_1) || - (ulConfig == SYSCTL_PWMDIV_2) || - (ulConfig == SYSCTL_PWMDIV_4) || - (ulConfig == SYSCTL_PWMDIV_8) || - (ulConfig == SYSCTL_PWMDIV_16) || - (ulConfig == SYSCTL_PWMDIV_32) || - (ulConfig == SYSCTL_PWMDIV_64)); - - // - // Check that there is a PWM block on this part. - // - ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_PWM); - - // - // Set the PWM clock configuration into the run-mode clock configuration - // register. - // - HWREG(SYSCTL_RCC) = ((HWREG(SYSCTL_RCC) & - ~(SYSCTL_RCC_USE_PWMDIV | SYSCTL_RCC_PWMDIV_MASK)) | - ulConfig); -} -#endif - -//***************************************************************************** -// -//! Gets the current PWM clock configuration. -//! -//! This function returns the current PWM clock configuration. -//! -//! \return The current PWM clock configuration; will be one of -//! \b SYSCTL_PWMDIV_1, \b SYSCTL_PWMDIV_2, \b SYSCTL_PWMDIV_4, -//! \b SYSCTL_PWMDIV_8, \b SYSCTL_PWMDIV_16, \b SYSCTL_PWMDIV_32, or -//! \b SYSCTL_PWMDIV_64. -// -//***************************************************************************** -#if defined(GROUP_pwmclockget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -SysCtlPWMClockGet(void) -{ - // - // Check that there is a PWM block on this part. - // - ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_PWM); - - // - // Return the current PWM clock configuration. - // - return(HWREG(SYSCTL_RCC) & - (SYSCTL_RCC_USE_PWMDIV | SYSCTL_RCC_PWMDIV_MASK)); -} -#endif - -//***************************************************************************** -// -//! Sets the sample rate of the ADC. -//! -//! \param ulSpeed is the desired sample rate of the ADC; must be one of -//! \b SYSCTL_ADCSPEED_1MSPS, \b SYSCTL_ADCSPEED_500KSPS, -//! \b SYSCTL_ADCSPEED_250KSPS, or \b SYSCTL_ADCSPEED_125KSPS. -//! -//! This function sets the rate at which the ADC samples are captured by the -//! ADC block. The sampling speed may be limited by the hardware, so the -//! sample rate may end up being slower than requested. SysCtlADCSpeedGet() -//! will return the actual speed in use. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_adcspeedset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysCtlADCSpeedSet(unsigned long ulSpeed) -{ - // - // Check the arguments. - // - ASSERT((ulSpeed == SYSCTL_ADCSPEED_1MSPS) || - (ulSpeed == SYSCTL_ADCSPEED_500KSPS) || - (ulSpeed == SYSCTL_ADCSPEED_250KSPS) || - (ulSpeed == SYSCTL_ADCSPEED_125KSPS)); - - // - // Check that there is an ADC block on this part. - // - ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_ADC); - - // - // Set the ADC speed in run, sleep, and deep-sleep mode. - // - HWREG(SYSCTL_RCGC0) = ((HWREG(SYSCTL_RCGC0) & ~(SYSCTL_SET0_ADCSPD_MASK)) | - ulSpeed); - HWREG(SYSCTL_SCGC0) = ((HWREG(SYSCTL_SCGC0) & ~(SYSCTL_SET0_ADCSPD_MASK)) | - ulSpeed); - HWREG(SYSCTL_DCGC0) = ((HWREG(SYSCTL_DCGC0) & ~(SYSCTL_SET0_ADCSPD_MASK)) | - ulSpeed); -} -#endif - -//***************************************************************************** -// -//! Gets the sample rate of the ADC. -//! -//! This function gets the current sample rate of the ADC. -//! -//! \return Returns the current ADC sample rate; will be one of -//! \b SYSCTL_ADCSPEED_1MSPS, \b SYSCTL_ADCSPEED_500KSPS, -//! \b SYSCTL_ADCSPEED_250KSPS, or \b SYSCTL_ADCSPEED_125KSPS. -// -//***************************************************************************** -#if defined(GROUP_adcspeedget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -SysCtlADCSpeedGet(void) -{ - // - // Check that there is an ADC block on this part. - // - ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_ADC); - - // - // Return the current ADC speed. - // - return(HWREG(SYSCTL_RCGC0) & SYSCTL_SET0_ADCSPD_MASK); -} -#endif - -//***************************************************************************** -// -//! Configures the internal oscillator verification timer. -//! -//! \param bEnable is a boolean that is \b true if the internal oscillator -//! verification timer should be enabled. -//! -//! This function allows the internal oscillator verification timer to be -//! enabled or disabled. When enabled, an interrupt will be generated if the -//! internal oscillator ceases to operate. -//! -//! \note Both oscillators (main and internal) must be enabled for this -//! verification timer to operate as the main oscillator will verify the -//! internal oscillator. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_boscverificationset) || defined(BUILD_ALL) || \ - defined(DOXYGEN) -void -SysCtlIOSCVerificationSet(tBoolean bEnable) -{ - // - // Enable or disable the internal oscillator verification timer as - // requested. - // - if(bEnable) - { - HWREG(SYSCTL_RCC) |= SYSCTL_RCC_IOSCVER; - } - else - { - HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_IOSCVER); - } -} -#endif - -//***************************************************************************** -// -//! Configures the main oscillator verification timer. -//! -//! \param bEnable is a boolean that is \b true if the main oscillator -//! verification timer should be enabled. -//! -//! This function allows the main oscillator verification timer to be enabled -//! or disabled. When enabled, an interrupt will be generated if the main -//! oscillator ceases to operate. -//! -//! \note Both oscillators (main and internal) must be enabled for this -//! verification timer to operate as the internal oscillator will verify the -//! main oscillator. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_moscverificationset) || defined(BUILD_ALL) || \ - defined(DOXYGEN) -void -SysCtlMOSCVerificationSet(tBoolean bEnable) -{ - // - // Enable or disable the main oscillator verification timer as requested. - // - if(bEnable) - { - HWREG(SYSCTL_RCC) |= SYSCTL_RCC_MOSCVER; - } - else - { - HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_MOSCVER); - } -} -#endif - -//***************************************************************************** -// -//! Configures the PLL verification timer. -//! -//! \param bEnable is a boolean that is \b true if the PLL verification timer -//! should be enabled. -//! -//! This function allows the PLL verification timer to be enabled or disabled. -//! When enabled, an interrupt will be generated if the PLL ceases to operate. -//! -//! \note The main oscillator must be enabled for this verification timer to -//! operate as it is used to check the PLL. Also, the verification timer -//! should be disabled while the PLL is being reconfigured via -//! SysCtlClockSet(). -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_pllverificationset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysCtlPLLVerificationSet(tBoolean bEnable) -{ - // - // Enable or disable the PLL verification timer as requested. - // - if(bEnable) - { - HWREG(SYSCTL_RCC) |= SYSCTL_RCC_PLLVER; - } - else - { - HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_PLLVER); - } -} -#endif - -//***************************************************************************** -// -//! Clears the clock verification status. -//! -//! This function clears the status of the clock verification timers, allowing -//! them to assert another failure if detected. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_clkverificationclear) || defined(BUILD_ALL) || \ - defined(DOXYGEN) -void -SysCtlClkVerificationClear(void) -{ - // - // Clear the clock verification. - // - HWREG(SYSCTL_CLKVCLR) = SYSCTL_CLKVCLR_CLR; - - // - // The bit does not self-reset, so clear it. - // - HWREG(SYSCTL_CLKVCLR) = 0; -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/sysctl.h b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/sysctl.h deleted file mode 100644 index 94b147084..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/sysctl.h +++ /dev/null @@ -1,285 +0,0 @@ -//***************************************************************************** -// -// sysctl.h - Prototypes for the system control driver. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __SYSCTL_H__ -#define __SYSCTL_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following are values that can be passed to the -// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(), -// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the -// ulPeripheral parameter. The peripherals in the fourth group (upper nibble -// is 3) can only be used with the SysCtlPeripheralPresent() API. -// -//***************************************************************************** -#define SYSCTL_PERIPH_PWM 0x00100000 // PWM -#define SYSCTL_PERIPH_ADC 0x00010000 // ADC -#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog -#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0 -#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1 -#define SYSCTL_PERIPH_SSI 0x10000010 // SSI -#define SYSCTL_PERIPH_QEI 0x10000100 // QEI -#define SYSCTL_PERIPH_I2C 0x10001000 // I2C -#define SYSCTL_PERIPH_TIMER0 0x10010000 // Timer 0 -#define SYSCTL_PERIPH_TIMER1 0x10020000 // Timer 1 -#define SYSCTL_PERIPH_TIMER2 0x10040000 // Timer 2 -#define SYSCTL_PERIPH_COMP0 0x11000000 // Analog comparator 0 -#define SYSCTL_PERIPH_COMP1 0x12000000 // Analog comparator 1 -#define SYSCTL_PERIPH_COMP2 0x14000000 // Analog comparator 2 -#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A -#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B -#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C -#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D -#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E -#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU -#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor -#define SYSCTL_PERIPH_PLL 0x30000010 // PLL - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlPinPresent() API -// as the ulPin parameter. -// -//***************************************************************************** -#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin -#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin -#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin -#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin -#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin -#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin -#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin -#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin -#define SYSCTL_PIN_C0O 0x00000100 // C0o pin -#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin -#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin -#define SYSCTL_PIN_C1O 0x00000800 // C1o pin -#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin -#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin -#define SYSCTL_PIN_C2O 0x00004000 // C2o pin -#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin -#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin -#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin -#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin -#define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin -#define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin -#define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin -#define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin -#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin -#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin -#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin -#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin -#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin -#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin -#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlLDOSet() API as -// the ulVoltage value, or returned by the SysCtlLDOGet() API. -// -//***************************************************************************** -#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V -#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V -#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V -#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V -#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V -#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V -#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V -#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V -#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V -#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V -#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlLDOConfigSet() API. -// -//***************************************************************************** -#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset -#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlIntEnable(), -// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask -// by the SysCtlIntStatus() API. -// -//***************************************************************************** -#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt -#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt -#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int -#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int -#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt -#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt -#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlResetCauseClear() -// API or returned by the SysCtlResetCauseGet() API. -// -//***************************************************************************** -#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset -#define SYSCTL_CAUSE_SW 0x00000010 // Software reset -#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset -#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset -#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset -#define SYSCTL_CAUSE_EXT 0x00000001 // External reset - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlBrownOutConfigSet() -// API as the ulConfig parameter. -// -//***************************************************************************** -#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting -#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlPWMClockSet() API -// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet() -// API. -// -//***************************************************************************** -#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1 -#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2 -#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4 -#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8 -#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16 -#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32 -#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64 - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlADCSpeedSet() API -// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet() -// API. -// -//***************************************************************************** -#define SYSCTL_ADCSPEED_1MSPS 0x00000300 // 1,000,000 samples per second -#define SYSCTL_ADCSPEED_500KSPS 0x00000200 // 500,000 samples per second -#define SYSCTL_ADCSPEED_250KSPS 0x00000100 // 250,000 samples per second -#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlClockSet() API as -// the ulConfig parameter. -// -//***************************************************************************** -#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1 -#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2 -#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3 -#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4 -#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5 -#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6 -#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7 -#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8 -#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9 -#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10 -#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11 -#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12 -#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13 -#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14 -#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15 -#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16 -#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock -#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock -#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz -#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz -#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz -#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz -#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz -#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz -#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz -#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz -#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz -#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz -#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz -#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz -#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc -#define SYSCTL_OSC_INT 0x00000010 // Oscillator source is int. osc -#define SYSCTL_OSC_INT4 0x00000020 // Oscillator source is int. osc /4 -#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator -#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern unsigned long SysCtlSRAMSizeGet(void); -extern unsigned long SysCtlFlashSizeGet(void); -extern tBoolean SysCtlPinPresent(unsigned long ulPin); -extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral); -extern void SysCtlPeripheralReset(unsigned long ulPeripheral); -extern void SysCtlPeripheralEnable(unsigned long ulPeripheral); -extern void SysCtlPeripheralDisable(unsigned long ulPeripheral); -extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral); -extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral); -extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral); -extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral); -extern void SysCtlPeripheralClockGating(tBoolean bEnable); -extern void SysCtlIntRegister(void (*pfnHandler)(void)); -extern void SysCtlIntUnregister(void); -extern void SysCtlIntEnable(unsigned long ulInts); -extern void SysCtlIntDisable(unsigned long ulInts); -extern void SysCtlIntClear(unsigned long ulInts); -extern unsigned long SysCtlIntStatus(tBoolean bMasked); -extern void SysCtlLDOSet(unsigned long ulVoltage); -extern unsigned long SysCtlLDOGet(void); -extern void SysCtlLDOConfigSet(unsigned long ulConfig); -extern void SysCtlReset(void); -extern void SysCtlSleep(void); -extern void SysCtlDeepSleep(void); -extern unsigned long SysCtlResetCauseGet(void); -extern void SysCtlResetCauseClear(unsigned long ulCauses); -extern void SysCtlBrownOutConfigSet(unsigned long ulConfig, - unsigned long ulDelay); -extern void SysCtlClockSet(unsigned long ulConfig); -extern unsigned long SysCtlClockGet(void); -extern void SysCtlPWMClockSet(unsigned long ulConfig); -extern unsigned long SysCtlPWMClockGet(void); -extern void SysCtlADCSpeedSet(unsigned long ulSpeed); -extern unsigned long SysCtlADCSpeedGet(void); -extern void SysCtlIOSCVerificationSet(tBoolean bEnable); -extern void SysCtlMOSCVerificationSet(tBoolean bEnable); -extern void SysCtlPLLVerificationSet(tBoolean bEnable); -extern void SysCtlClkVerificationClear(void); - -#ifdef __cplusplus -} -#endif - -#endif // __SYSCTL_H__ diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/systick.c b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/systick.c deleted file mode 100644 index 382533513..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/systick.c +++ /dev/null @@ -1,262 +0,0 @@ -//***************************************************************************** -// -// systick.c - Driver for the SysTick timer in NVIC. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup systick_api -//! @{ -// -//***************************************************************************** - -#include "../hw_ints.h" -#include "../hw_nvic.h" -#include "../hw_types.h" -#include "debug.h" -#include "interrupt.h" -#include "systick.h" - -//***************************************************************************** -// -//! Enables the SysTick counter. -//! -//! This will start the SysTick counter. If an interrupt handler has been -//! registered, it will be called when the SysTick counter rolls over. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysTickEnable(void) -{ - // - // Enable SysTick. - // - HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_CLK_SRC | NVIC_ST_CTRL_ENABLE; -} -#endif - -//***************************************************************************** -// -//! Disables the SysTick counter. -//! -//! This will stop the SysTick counter. If an interrupt handler has been -//! registered, it will no longer be called until SysTick is restarted. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysTickDisable(void) -{ - // - // Disable SysTick. - // - HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_ENABLE); -} -#endif - -//***************************************************************************** -// -//! Registers an interrupt handler for the SysTick interrupt. -//! -//! \param pfnHandler is a pointer to the function to be called when the -//! SysTick interrupt occurs. -//! -//! This sets the handler to be called when a SysTick interrupt occurs. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysTickIntRegister(void (*pfnHandler)(void)) -{ - // - // Register the interrupt handler, returning an error if an error occurs. - // - IntRegister(FAULT_SYSTICK, pfnHandler); - - // - // Enable the SysTick interrupt. - // - HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; -} -#endif - -//***************************************************************************** -// -//! Unregisters the interrupt handler for the SysTick interrupt. -//! -//! This function will clear the handler to be called when a SysTick interrupt -//! occurs. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysTickIntUnregister(void) -{ - // - // Disable the SysTick interrupt. - // - HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); - - // - // Unregister the interrupt handler. - // - IntUnregister(FAULT_SYSTICK); -} -#endif - -//***************************************************************************** -// -//! Enables the SysTick interrupt. -//! -//! This function will enable the SysTick interrupt, allowing it to be -//! reflected to the processor. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysTickIntEnable(void) -{ - // - // Enable the SysTick interrupt. - // - HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; -} -#endif - -//***************************************************************************** -// -//! Disables the SysTick interrupt. -//! -//! This function will disable the SysTick interrupt, preventing it from being -//! reflected to the processor. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysTickIntDisable(void) -{ - // - // Disable the SysTick interrupt. - // - HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); -} -#endif - -//***************************************************************************** -// -//! Sets the period of the SysTick counter. -//! -//! \param ulPeriod is the number of clock ticks in each period of the SysTick -//! counter; must be between 1 and 16,777,216, inclusive. -//! -//! This function sets the rate at which the SysTick counter wraps; this -//! equates to the number of processor clocks between interrupts. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_periodset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -SysTickPeriodSet(unsigned long ulPeriod) -{ - // - // Check the arguments. - // - ASSERT((ulPeriod > 0) && (ulPeriod <= 16777216)); - - // - // Set the period of the SysTick counter. - // - HWREG(NVIC_ST_RELOAD) = ulPeriod - 1; -} -#endif - -//***************************************************************************** -// -//! Gets the period of the SysTick counter. -//! -//! This function returns the rate at which the SysTick counter wraps; this -//! equates to the number of processor clocks between interrupts. -//! -//! \return Returns the period of the SysTick counter. -// -//***************************************************************************** -#if defined(GROUP_periodget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -SysTickPeriodGet(void) -{ - // - // Return the period of the SysTick counter. - // - return(HWREG(NVIC_ST_RELOAD) + 1); -} -#endif - -//***************************************************************************** -// -//! Gets the current value of the SysTick counter. -//! -//! This function returns the current value of the SysTick counter; this will -//! be a value between the period - 1 and zero, inclusive. -//! -//! \return Returns the current value of the SysTick counter. -// -//***************************************************************************** -#if defined(GROUP_valueget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -SysTickValueGet(void) -{ - // - // Return the current value of the SysTick counter. - // - return(HWREG(NVIC_ST_CURRENT)); -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/systick.h b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/systick.h deleted file mode 100644 index bfddfb16f..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/systick.h +++ /dev/null @@ -1,55 +0,0 @@ -//***************************************************************************** -// -// systick.h - Prototypes for the SysTick driver. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __SYSTICK_H__ -#define __SYSTICK_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void SysTickEnable(void); -extern void SysTickDisable(void); -extern void SysTickIntRegister(void (*pfnHandler)(void)); -extern void SysTickIntUnregister(void); -extern void SysTickIntEnable(void); -extern void SysTickIntDisable(void); -extern void SysTickPeriodSet(unsigned long ulPeriod); -extern unsigned long SysTickPeriodGet(void); -extern unsigned long SysTickValueGet(void); - -#ifdef __cplusplus -} -#endif - -#endif // __SYSTICK_H__ diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/timer.c b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/timer.c deleted file mode 100644 index 46ce19a30..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/timer.c +++ /dev/null @@ -1,1125 +0,0 @@ -//***************************************************************************** -// -// timer.c - Driver for the timer module. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup timer_api -//! @{ -// -//***************************************************************************** - -#include "../hw_ints.h" -#include "../hw_memmap.h" -#include "../hw_timer.h" -#include "../hw_types.h" -#include "debug.h" -#include "interrupt.h" -#include "timer.h" - -//***************************************************************************** -// -//! Enables the timer(s). -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer(s) to enable; must be one of \b TIMER_A, -//! \b TIMER_B, or \b TIMER_BOTH. -//! -//! This will enable operation of the timer module. The timer must be -//! configured before it is enabled. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -TimerEnable(unsigned long ulBase, unsigned long ulTimer) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - // - // Enable the timer(s) module. - // - HWREG(ulBase + TIMER_O_CTL) |= ulTimer & (TIMER_CTL_TAEN | TIMER_CTL_TBEN); -} -#endif - -//***************************************************************************** -// -//! Disables the timer(s). -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer(s) to disable; must be one of -//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. -//! -//! This will disable operation of the timer module. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -TimerDisable(unsigned long ulBase, unsigned long ulTimer) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - // - // Disable the timer module. - // - HWREG(ulBase + TIMER_O_CTL) &= ~(ulTimer & - (TIMER_CTL_TAEN | TIMER_CTL_TBEN)); -} -#endif - -//***************************************************************************** -// -//! Configures the timer(s). -//! -//! \param ulBase is the base address of the timer module. -//! \param ulConfig is the configuration for the timer. -//! -//! This function configures the operating mode of the timer(s). The timer -//! module is disabled before being configured, and is left in the disabled -//! state. The configuration is specified in \e ulConfig as one of the -//! following values: -//! -//! - \b TIMER_CFG_32_BIT_OS - 32-bit one shot timer -//! - \b TIMER_CFG_32_BIT_PER - 32-bit periodic timer -//! - \b TIMER_CFG_32_RTC - 32-bit real time clock timer -//! - \b TIMER_CFG_16_BIT_PAIR - Two 16-bit timers -//! -//! When configured for a pair of 16-bit timers, each timer is separately -//! configured. The first timer is configured by setting \e ulConfig to -//! the result of a logical OR operation between one of the following values -//! and \e ulConfig: -//! -//! - \b TIMER_CFG_A_ONE_SHOT - 16-bit one shot timer -//! - \b TIMER_CFG_A_PERIODIC - 16-bit periodic timer -//! - \b TIMER_CFG_A_CAP_COUNT - 16-bit edge count capture -//! - \b TIMER_CFG_A_CAP_TIME - 16-bit edge time capture -//! - \b TIMER_CFG_A_PWM - 16-bit PWM output -//! -//! Similarly, the second timer is configured by setting \e ulConfig to -//! the result of a logical OR operation between one of the corresponding -//! \b TIMER_CFG_B_* values and \e ulConfig. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_configure) || defined(BUILD_ALL) || defined(DOXYGEN) -void -TimerConfigure(unsigned long ulBase, unsigned long ulConfig) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - ASSERT((ulConfig == TIMER_CFG_32_BIT_OS) || - (ulConfig == TIMER_CFG_32_BIT_PER) || - (ulConfig == TIMER_CFG_32_RTC) || - ((ulConfig & 0xff000000) == TIMER_CFG_16_BIT_PAIR)); - ASSERT(((ulConfig & 0xff000000) != TIMER_CFG_16_BIT_PAIR) || - ((((ulConfig & 0x000000ff) == TIMER_CFG_A_ONE_SHOT) || - ((ulConfig & 0x000000ff) == TIMER_CFG_A_PERIODIC) || - ((ulConfig & 0x000000ff) == TIMER_CFG_A_CAP_COUNT) || - ((ulConfig & 0x000000ff) == TIMER_CFG_A_CAP_TIME) || - ((ulConfig & 0x000000ff) == TIMER_CFG_A_PWM)) && - (((ulConfig & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT) || - ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PERIODIC) || - ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_COUNT) || - ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_TIME) || - ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PWM)))); - - // - // Disable the timers. - // - HWREG(ulBase + TIMER_O_CTL) &= ~(TIMER_CTL_TAEN | TIMER_CTL_TBEN); - - // - // Set the global timer configuration. - // - HWREG(ulBase + TIMER_O_CFG) = ulConfig >> 24; - - // - // Set the configuration of the A and B timers. Note that the B timer - // configuration is ignored by the hardware in 32-bit modes. - // - HWREG(ulBase + TIMER_O_TAMR) = ulConfig & 255; - HWREG(ulBase + TIMER_O_TBMR) = (ulConfig >> 8) & 255; -} -#endif - -//***************************************************************************** -// -//! Controls the output level. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, -//! \b TIMER_B, or \b TIMER_BOTH. -//! \param bInvert specifies the output level. -//! -//! This function sets the PWM output level for the specified timer. If the -//! parameter \e bInvert is \b true, then the timer's output will be made -//! active low; otherwise, it will be made active high. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_controllevel) || defined(BUILD_ALL) || defined(DOXYGEN) -void -TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, - tBoolean bInvert) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - // - // Set the output levels as requested. - // - ulTimer &= TIMER_CTL_TAPWML | TIMER_CTL_TBPWML; - HWREG(ulBase + TIMER_O_CTL) = (bInvert ? - (HWREG(ulBase + TIMER_O_CTL) | ulTimer) : - (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer))); -} -#endif - -//***************************************************************************** -// -//! Enables or disables the trigger output. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer to adjust; must be one of \b TIMER_A, -//! \b TIMER_B, or \b TIMER_BOTH. -//! \param bEnable specifies the desired trigger state. -//! -//! This function controls the trigger output for the specified timer. If the -//! parameter \e bEnable is \b true, then the timer's output trigger is -//! enabled; otherwise it is disabled. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_controltrigger) || defined(BUILD_ALL) || defined(DOXYGEN) -void -TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, - tBoolean bEnable) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - // - // Set the trigger output as requested. - // - ulTimer &= TIMER_CTL_TAOTE | TIMER_CTL_TBOTE; - HWREG(ulBase + TIMER_O_CTL) = (bEnable ? - (HWREG(ulBase + TIMER_O_CTL) | ulTimer) : - (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer))); -} -#endif - -//***************************************************************************** -// -//! Controls the event type. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer(s) to be adjusted; must be one of -//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. -//! \param ulEvent specifies the type of event; must be one of -//! \b TIMER_EVENT_POS_EDGE, \b TIMER_EVENT_NEG_EDGE, or -//! \b TIMER_EVENT_BOTH_EDGES. -//! -//! This function sets the signal edge(s) that will trigger the timer when in -//! capture mode. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_controlevent) || defined(BUILD_ALL) || defined(DOXYGEN) -void -TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulEvent) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - // - // Set the event type. - // - ulEvent &= ulTimer & (TIMER_CTL_TAEVENT_MSK | TIMER_CTL_TBEVENT_MSK); - HWREG(ulBase + TIMER_O_CTL) = ((HWREG(ulBase + TIMER_O_CTL) & - ~(TIMER_CTL_TAEVENT_MSK | - TIMER_CTL_TBEVENT_MSK)) | ulEvent); -} -#endif - -//***************************************************************************** -// -//! Controls the stall handling. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer(s) to be adjusted; must be one of -//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. -//! \param bStall specifies the response to a stall signal. -//! -//! This function controls the stall response for the specified timer. If the -//! parameter \e bStall is \b true, then the timer will stop counting if the -//! processor enters debug mode; otherwise the timer will keep running while in -//! debug mode. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_controlstall) || defined(BUILD_ALL) || defined(DOXYGEN) -void -TimerControlStall(unsigned long ulBase, unsigned long ulTimer, - tBoolean bStall) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - // - // Set the stall mode. - // - ulTimer &= TIMER_CTL_TASTALL | TIMER_CTL_TBSTALL; - HWREG(ulBase + TIMER_O_CTL) = (bStall ? - (HWREG(ulBase + TIMER_O_CTL) | ulTimer) : - (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer))); -} -#endif - -//***************************************************************************** -// -//! Enable RTC counting. -//! -//! \param ulBase is the base address of the timer module. -//! -//! This function causes the timer to start counting when in RTC mode. If not -//! configured for RTC mode, this will do nothing. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_rtcenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -TimerRTCEnable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - - // - // Enable RTC counting. - // - HWREG(ulBase + TIMER_O_CTL) |= TIMER_CTL_RTCEN; -} -#endif - -//***************************************************************************** -// -//! Disable RTC counting. -//! -//! \param ulBase is the base address of the timer module. -//! -//! This function causes the timer to stop counting when in RTC mode. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_rtcdisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -TimerRTCDisable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - - // - // Disable RTC counting. - // - HWREG(ulBase + TIMER_O_CTL) &= ~(TIMER_CTL_RTCEN); -} -#endif - -//***************************************************************************** -// -//! Set the timer prescale value. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, -//! \b TIMER_B, or \b TIMER_BOTH. -//! \param ulValue is the timer prescale value; must be between 0 and 255, -//! inclusive. -//! -//! This function sets the value of the input clock prescaler. The prescaler -//! is only operational when in 16-bit mode and is used to extend the range of -//! the 16-bit timer modes. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_prescaleset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - ASSERT(ulValue < 256); - - // - // Set the timer A prescaler if requested. - // - if(ulTimer & TIMER_A) - { - HWREG(ulBase + TIMER_O_TAPR) = ulValue; - } - - // - // Set the timer B prescaler if requested. - // - if(ulTimer & TIMER_B) - { - HWREG(ulBase + TIMER_O_TBPR) = ulValue; - } -} -#endif - -//***************************************************************************** -// -//! Get the timer prescale value. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer; must be one of \b TIMER_A or -//! \b TIMER_B. -//! -//! This function gets the value of the input clock prescaler. The prescaler -//! is only operational when in 16-bit mode and is used to extend the range of -//! the 16-bit timer modes. -//! -//! \return The value of the timer prescaler. -// -//***************************************************************************** -#if defined(GROUP_prescaleget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -TimerPrescaleGet(unsigned long ulBase, unsigned long ulTimer) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - // - // Return the appropriate prescale value. - // - return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAPR) : - HWREG(ulBase + TIMER_O_TBPR)); -} -#endif - -//***************************************************************************** -// -//! Set the timer prescale match value. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, -//! \b TIMER_B, or \b TIMER_BOTH. -//! \param ulValue is the timer prescale match value; must be between 0 and -//! 255, inclusive. -//! -//! This function sets the value of the input clock prescaler match value. -//! When in a 16-bit mode that uses the counter match (edge count or PWM), the -//! prescale match effectively extends the range of the counter to 24-bits. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_prescalematchset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - ASSERT(ulValue < 256); - - // - // Set the timer A prescale match if requested. - // - if(ulTimer & TIMER_A) - { - HWREG(ulBase + TIMER_O_TAPMR) = ulValue; - } - - // - // Set the timer B prescale match if requested. - // - if(ulTimer & TIMER_B) - { - HWREG(ulBase + TIMER_O_TBPMR) = ulValue; - } -} -#endif - -//***************************************************************************** -// -//! Get the timer prescale match value. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer; must be one of \b TIMER_A or -//! \b TIMER_B. -//! -//! This function gets the value of the input clock prescaler match value. -//! When in a 16-bit mode that uses the counter match (edge count or PWM), the -//! prescale match effectively extends the range of the counter to 24-bits. -//! -//! \return The value of the timer prescale match. -// -//***************************************************************************** -#if defined(GROUP_prescalematchget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -TimerPrescaleMatchGet(unsigned long ulBase, unsigned long ulTimer) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - // - // Return the appropriate prescale match value. - // - return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAPMR) : - HWREG(ulBase + TIMER_O_TBPMR)); -} -#endif - -//***************************************************************************** -// -//! Sets the timer load value. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, -//! \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used when the -//! timer is configured for 32-bit operation. -//! \param ulValue is the load value. -//! -//! This function sets the timer load value; if the timer is running then the -//! value will be immediately loaded into the timer. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_loadset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - // - // Set the timer A load value if requested. - // - if(ulTimer & TIMER_A) - { - HWREG(ulBase + TIMER_O_TAILR) = ulValue; - } - - // - // Set the timer B load value if requested. - // - if(ulTimer & TIMER_B) - { - HWREG(ulBase + TIMER_O_TBILR) = ulValue; - } -} -#endif - -//***************************************************************************** -// -//! Gets the timer load value. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer; must be one of \b TIMER_A or -//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured -//! for 32-bit operation. -//! -//! This function gets the currently programmed interval load value for the -//! specified timer. -//! -//! \return Returns the load value for the timer. -// -//***************************************************************************** -#if defined(GROUP_loadget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -TimerLoadGet(unsigned long ulBase, unsigned long ulTimer) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B)); - - // - // Return the appropriate load value. - // - return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAILR) : - HWREG(ulBase + TIMER_O_TBILR)); -} -#endif - -//***************************************************************************** -// -//! Gets the current timer value. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer; must be one of \b TIMER_A or -//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured -//! for 32-bit operation. -//! -//! This function reads the current value of the specified timer. -//! -//! \return Returns the current value of the timer. -// -//***************************************************************************** -#if defined(GROUP_valueget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -TimerValueGet(unsigned long ulBase, unsigned long ulTimer) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B)); - - // - // Return the appropriate timer value. - // - return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAR) : - HWREG(ulBase + TIMER_O_TBR)); -} -#endif - -//***************************************************************************** -// -//! Sets the timer match value. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, -//! \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used when the -//! timer is configured for 32-bit operation. -//! \param ulValue is the match value. -//! -//! This function sets the match value for a timer. This is used in capture -//! count mode to determine when to interrupt the processor and in PWM mode to -//! determine the duty cycle of the output signal. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_matchset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - // - // Set the timer A match value if requested. - // - if(ulTimer & TIMER_A) - { - HWREG(ulBase + TIMER_O_TAMATCHR) = ulValue; - } - - // - // Set the timer B match value if requested. - // - if(ulTimer & TIMER_B) - { - HWREG(ulBase + TIMER_O_TBMATCHR) = ulValue; - } -} -#endif - -//***************************************************************************** -// -//! Gets the timer match value. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer; must be one of \b TIMER_A or -//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured -//! for 32-bit operation. -//! -//! This function gets the match value for the specified timer. -//! -//! \return Returns the match value for the timer. -// -//***************************************************************************** -#if defined(GROUP_matchget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -TimerMatchGet(unsigned long ulBase, unsigned long ulTimer) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B)); - - // - // Return the appropriate match value. - // - return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAMATCHR) : - HWREG(ulBase + TIMER_O_TBMATCHR)); -} -#endif - -//***************************************************************************** -// -//! Registers an interrupt handler for the timer interrupt. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer(s); must be one of \b TIMER_A, -//! \b TIMER_B, or \b TIMER_BOTH. -//! \param pfnHandler is a pointer to the function to be called when the timer -//! interrupt occurs. -//! -//! This sets the handler to be called when a timer interrupt occurs. This -//! will enable the global interrupt in the interrupt controller; specific -//! timer interrupts must be enabled via TimerIntEnable(). It is the interrupt -//! handler's responsibility to clear the interrupt source via TimerIntClear(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, - void (*pfnHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - // - // Get the interrupt number for this timer module. - // - ulBase = ((ulBase == TIMER0_BASE) ? INT_TIMER0A : - ((ulBase == TIMER1_BASE) ? INT_TIMER1A : INT_TIMER2A)); - - // - // Register an interrupt handler for timer A if requested. - // - if(ulTimer & TIMER_A) - { - // - // Register the interrupt handler. - // - IntRegister(ulBase, pfnHandler); - - // - // Enable the interrupt. - // - IntEnable(ulBase); - } - - // - // Register an interrupt handler for timer B if requested. - // - if(ulTimer & TIMER_B) - { - // - // Register the interrupt handler. - // - IntRegister(ulBase + 1, pfnHandler); - - // - // Enable the interrupt. - // - IntEnable(ulBase + 1); - } -} -#endif - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the timer interrupt. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer(s); must be one of \b TIMER_A, -//! \b TIMER_B, or \b TIMER_BOTH. -//! -//! This function will clear the handler to be called when a timer interrupt -//! occurs. This will also mask off the interrupt in the interrupt controller -//! so that the interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - // - // Get the interrupt number for this timer module. - // - ulBase = ((ulBase == TIMER0_BASE) ? INT_TIMER0A : - ((ulBase == TIMER1_BASE) ? INT_TIMER1A : INT_TIMER2A)); - - // - // Unregister the interrupt handler for timer A if requested. - // - if(ulTimer & TIMER_A) - { - // - // Disable the interrupt. - // - IntDisable(ulBase); - - // - // Unregister the interrupt handler. - // - IntUnregister(ulBase); - } - - // - // Unregister the interrupt handler for timer B if requested. - // - if(ulTimer & TIMER_B) - { - // - // Disable the interrupt. - // - IntDisable(ulBase + 1); - - // - // Unregister the interrupt handler. - // - IntUnregister(ulBase + 1); - } -} -#endif - -//***************************************************************************** -// -//! Enables individual timer interrupt sources. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. -//! -//! Enables the indicated timer interrupt sources. Only the sources that are -//! enabled can be reflected to the processor interrupt; disabled sources have -//! no effect on the processor. -//! -//! The parameter \e ulIntFlags must be the logical OR of any combination of -//! the following: -//! -//! - TIMER_CAPB_EVENT - Capture B event interrupt -//! - TIMER_CAPB_MATCH - Capture B match interrupt -//! - TIMER_TIMB_TIMEOUT - Timer B timeout interrupt -//! - TIMER_RTC_MATCH - RTC interrupt mask -//! - TIMER_CAPA_EVENT - Capture A event interrupt -//! - TIMER_CAPA_MATCH - Capture A match interrupt -//! - TIMER_TIMA_TIMEOUT - Timer A timeout interrupt -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - - // - // Enable the specified interrupts. - // - HWREG(ulBase + TIMER_O_IMR) |= ulIntFlags; -} -#endif - -//***************************************************************************** -// -//! Disables individual timer interrupt sources. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. -//! -//! Disables the indicated timer interrupt sources. Only the sources that are -//! enabled can be reflected to the processor interrupt; disabled sources have -//! no effect on the processor. -//! -//! The parameter \e ulIntFlags has the same definition as the \e ulIntFlags -//! parameter to TimerIntEnable(). -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - - // - // Disable the specified interrupts. - // - HWREG(ulBase + TIMER_O_IMR) &= ~(ulIntFlags); -} -#endif - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \param ulBase is the base address of the timer module. -//! \param bMasked is false if the raw interrupt status is required and true if -//! the masked interrupt status is required. -//! -//! This returns the interrupt status for the timer module. Either the raw -//! interrupt status or the status of interrupts that are allowed to reflect to -//! the processor can be returned. -//! -//! \return The current interrupt status, enumerated as a bit field of -//! values described in TimerIntEnable(). -// -//***************************************************************************** -#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -TimerIntStatus(unsigned long ulBase, tBoolean bMasked) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - return(bMasked ? HWREG(ulBase + TIMER_O_MIS) : - HWREG(ulBase + TIMER_O_RIS)); -} -#endif - -//***************************************************************************** -// -//! Clears timer interrupt sources. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. -//! -//! The specified timer interrupt sources are cleared, so that they no longer -//! assert. This must be done in the interrupt handler to keep it from being -//! called again immediately upon exit. -//! -//! The parameter \e ulIntFlags has the same definition as the \e ulIntFlags -//! parameter to TimerIntEnable(). -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) -void -TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - - // - // Clear the requested interrupt sources. - // - HWREG(ulBase + TIMER_O_ICR) = ulIntFlags; -} -#endif - -//***************************************************************************** -// -//! Puts the timer into its reset state. -//! -//! \param ulBase is the base address of the timer module. -//! -//! The specified timer is disabled, and all its interrupts are disabled, -//! cleared, and unregistered. Then the timer registers are set to their reset -//! value. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_quiesce) || defined(BUILD_ALL) || defined(DOXYGEN) -void -TimerQuiesce(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || - (ulBase == TIMER2_BASE)); - - // - // Disable the timer. - // - HWREG(ulBase + TIMER_O_CTL) = TIMER_RV_CTL; - - // - // Disable all the timer interrupts. - // - HWREG(ulBase + TIMER_O_IMR) = TIMER_RV_IMR; - - // - // Clear all the timer interrupts. - // - HWREG(ulBase + TIMER_O_ICR) = 0xFFFFFFFF; - - // - // Unregister the interrupt handler. This also disables interrupts to the - // core. - // - TimerIntUnregister(ulBase, TIMER_BOTH); - - // - // Set all the registers to their reset value. - // - HWREG(ulBase + TIMER_O_CFG) = TIMER_RV_CFG; - HWREG(ulBase + TIMER_O_TAMR) = TIMER_RV_TAMR; - HWREG(ulBase + TIMER_O_TBMR) = TIMER_RV_TBMR; - HWREG(ulBase + TIMER_O_RIS) = TIMER_RV_RIS; - HWREG(ulBase + TIMER_O_MIS) = TIMER_RV_MIS; - HWREG(ulBase + TIMER_O_TAILR) = TIMER_RV_TAILR; - HWREG(ulBase + TIMER_O_TBILR) = TIMER_RV_TBILR; - HWREG(ulBase + TIMER_O_TAMATCHR) = TIMER_RV_TAMATCHR; - HWREG(ulBase + TIMER_O_TBMATCHR) = TIMER_RV_TBMATCHR; - HWREG(ulBase + TIMER_O_TAPR) = TIMER_RV_TAPR; - HWREG(ulBase + TIMER_O_TBPR) = TIMER_RV_TBPR; - HWREG(ulBase + TIMER_O_TAPMR) = TIMER_RV_TAPMR; - HWREG(ulBase + TIMER_O_TBPMR) = TIMER_RV_TBPMR; - HWREG(ulBase + TIMER_O_TAR) = TIMER_RV_TAR; - HWREG(ulBase + TIMER_O_TBR) = TIMER_RV_TBR; -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/timer.h b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/timer.h deleted file mode 100644 index 660c325f4..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/timer.h +++ /dev/null @@ -1,137 +0,0 @@ -//***************************************************************************** -// -// timer.h - Prototypes for the timer module -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __TIMER_H__ -#define __TIMER_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to TimerConfigure as the ulConfig parameter. -// -//***************************************************************************** -#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer -#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer -#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer -#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers -#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer -#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer -#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter -#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer -#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output -#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer -#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer -#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter -#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer -#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output - -//***************************************************************************** -// -// Values that can be passed to TimerIntEnable, TimerIntDisable, and -// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus. -// -//***************************************************************************** -#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt -#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt -#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt -#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask -#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt -#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt -#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt - -//***************************************************************************** -// -// Values that can be passed to TimerControlEvent as the ulEvent parameter. -// -//***************************************************************************** -#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges -#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges -#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges - -//***************************************************************************** -// -// Values that can be passed to most of the timer APIs as the ulTimer -// parameter. -// -//***************************************************************************** -#define TIMER_A 0x000000ff // Timer A -#define TIMER_B 0x0000ff00 // Timer B -#define TIMER_BOTH 0x0000ffff // Timer Both - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer); -extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer); -extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig); -extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, - tBoolean bInvert); -extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, - tBoolean bEnable); -extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulEvent); -extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer, - tBoolean bStall); -extern void TimerRTCEnable(unsigned long ulBase); -extern void TimerRTCDisable(unsigned long ulBase); -extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerPrescaleGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer); -extern unsigned long TimerValueGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerMatchGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, - void (*pfnHandler)(void)); -extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer); -extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags); -extern void TimerQuiesce(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __TIMER_H__ diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/uart.c b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/uart.c deleted file mode 100644 index cbae1b0ca..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/uart.c +++ /dev/null @@ -1,821 +0,0 @@ -//***************************************************************************** -// -// uart.c - Driver for the UART. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup uart_api -//! @{ -// -//***************************************************************************** - -#include "../hw_ints.h" -#include "../hw_memmap.h" -#include "../hw_types.h" -#include "../hw_uart.h" -#include "debug.h" -#include "interrupt.h" -#include "sysctl.h" -#include "uart.h" - -//***************************************************************************** -// -//! Sets the type of parity. -//! -//! \param ulBase is the base address of the UART port. -//! \param ulParity specifies the type of parity to use. -//! -//! Sets the type of parity to use for transmitting and expect when receiving. -//! The \e ulParity parameter must be one of \b UART_CONFIG_PAR_NONE, -//! \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE, -//! or \b UART_CONFIG_PAR_ZERO. The last two allow direct control of the -//! parity bit; it will always be either be one or zero based on the mode. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_paritymodeset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -UARTParityModeSet(unsigned long ulBase, unsigned long ulParity) -{ - // - // Check the arguments. - // - ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); - ASSERT((ulParity == UART_CONFIG_PAR_NONE) || - (ulParity == UART_CONFIG_PAR_EVEN) || - (ulParity == UART_CONFIG_PAR_ODD) || - (ulParity == UART_CONFIG_PAR_ONE) || - (ulParity == UART_CONFIG_PAR_ZERO)); - - // - // Set the parity mode. - // - HWREG(ulBase + UART_O_LCR_H) = ((HWREG(ulBase + UART_O_LCR_H) & - ~(UART_LCR_H_SPS | UART_LCR_H_EPS | - UART_LCR_H_PEN)) | ulParity); -} -#endif - -//***************************************************************************** -// -//! Gets the type of parity currently being used. -//! -//! \param ulBase is the base address of the UART port. -//! -//! \return The current parity settings, specified as one of -//! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, -//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO. -// -//***************************************************************************** -#if defined(GROUP_paritymodeget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -UARTParityModeGet(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); - - // - // Return the current parity setting. - // - return(HWREG(ulBase + UART_O_LCR_H) & - (UART_LCR_H_SPS | UART_LCR_H_EPS | UART_LCR_H_PEN)); -} -#endif - -//***************************************************************************** -// -//! Sets the configuration of a UART. -//! -//! \param ulBase is the base address of the UART port. -//! \param ulBaud is the desired baud rate. -//! \param ulConfig is the data format for the port (number of data bits, -//! number of stop bits, and parity). -//! -//! This function will configure the UART for operation in the specified data -//! format. The baud rate is provided in the \e ulBaud parameter and the -//! data format in the \e ulConfig parameter. -//! -//! The \e ulConfig parameter is the logical OR of three values: the number of -//! data bits, the number of stop bits, and the parity. \b UART_CONFIG_WLEN_8, -//! \b UART_CONFIG_WLEN_7, \b UART_CONFIG_WLEN_6, and \b UART_CONFIG_WLEN_5 -//! select from eight to five data bits per byte (respectively). -//! \b UART_CONFIG_STOP_ONE and \b UART_CONFIG_STOP_TWO select one or two stop -//! bits (respectively). \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, -//! \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE, and \b UART_CONFIG_PAR_ZERO -//! select the parity mode (no parity bit, even parity bit, odd parity bit, -//! parity bit always one, and parity bit always zero, respectively). -//! -//! The baud rate is dependent upon the system clock rate returned by -//! SysCtlClockGet(); if it does not return the correct system clock rate then -//! the baud rate will be incorrect. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_configset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -UARTConfigSet(unsigned long ulBase, unsigned long ulBaud, - unsigned long ulConfig) -{ - unsigned long ulUARTClk, ulInt, ulFrac; - - // - // Check the arguments. - // - ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); - - // - // Stop the UART. - // - UARTDisable(ulBase); - - // - // Determine the UART clock rate. - // - ulUARTClk = SysCtlClockGet(); - - // - // Compute the fractional baud rate divider. - // - ulInt = ulUARTClk / (16 * ulBaud); - ulFrac = ulUARTClk % (16 * ulBaud); - ulFrac = ((((2 * ulFrac * 4) / ulBaud) + 1) / 2); - - // - // Set the baud rate. - // - HWREG(ulBase + UART_O_IBRD) = ulInt; - HWREG(ulBase + UART_O_FBRD) = ulFrac; - - // - // Set parity, data length, and number of stop bits. - // - HWREG(ulBase + UART_O_LCR_H) = ulConfig; - - // - // Clear the flags register. - // - HWREG(ulBase + UART_O_FR) = 0; - - // - // Start the UART. - // - UARTEnable(ulBase); -} -#endif - -//***************************************************************************** -// -//! Gets the current configuration of a UART. -//! -//! \param ulBase is the base address of the UART port. -//! \param pulBaud is a pointer to storage for the baud rate. -//! \param pulConfig is a pointer to storage for the data format. -//! -//! The baud rate and data format for the UART is determined. The returned -//! baud rate is the actual baud rate; it may not be the exact baud rate -//! requested or an ``official'' baud rate. The data format returned in -//! \e pulConfig is enumerated the same as the \e ulConfig parameter of -//! UARTConfigSet(). -//! -//! The baud rate is dependent upon the system clock rate returned by -//! SysCtlClockGet(); if it does not return the correct system clock rate then -//! the baud rate will be computed incorrectly. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_configget) || defined(BUILD_ALL) || defined(DOXYGEN) -void -UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud, - unsigned long *pulConfig) - -{ - unsigned long ulInt, ulFrac; - - // - // Check the arguments. - // - ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); - - // - // Compute the baud rate. - // - ulInt = HWREG(ulBase + UART_O_IBRD); - ulFrac = HWREG(ulBase + UART_O_FBRD); - *pulBaud = (SysCtlClockGet() * 4) / ((64 * ulInt) + ulFrac); - - // - // Get the parity, data length, and number of stop bits. - // - *pulConfig = (HWREG(ulBase + UART_O_LCR_H) & - (UART_LCR_H_SPS | UART_LCR_H_WLEN | UART_LCR_H_STP2 | - UART_LCR_H_EPS | UART_LCR_H_PEN)); -} -#endif - -//***************************************************************************** -// -//! Enables transmitting and receiving. -//! -//! \param ulBase is the base address of the UART port. -//! -//! Sets the UARTEN, TXE, and RXE bits, and enables the transmit and receive -//! FIFOs. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -UARTEnable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); - - // - // Enable the FIFO. - // - HWREG(ulBase + UART_O_LCR_H) |= UART_LCR_H_FEN; - - // - // Enable RX, TX, and the UART. - // - HWREG(ulBase + UART_O_CTL) |= (UART_CTL_UARTEN | UART_CTL_TXE | - UART_CTL_RXE); -} -#endif - -//***************************************************************************** -// -//! Disables transmitting and receiving. -//! -//! \param ulBase is the base address of the UART port. -//! -//! Clears the UARTEN, TXE, and RXE bits, then waits for the end of -//! transmission of the current character, and flushes the transmit FIFO. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -UARTDisable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); - - // - // Wait for end of TX. - // - while(HWREG(ulBase + UART_O_FR) & UART_FR_BUSY) - { - } - - // - // Disable the FIFO. - // - HWREG(ulBase + UART_O_LCR_H) &= ~(UART_LCR_H_FEN); - - // - // Disable the UART. - // - HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE | - UART_CTL_RXE); -} -#endif - -//***************************************************************************** -// -//! Determines if there are any characters in the receive FIFO. -//! -//! \param ulBase is the base address of the UART port. -//! -//! This function returns a flag indicating whether or not there is data -//! available in the receive FIFO. -//! -//! \return Returns \b true if there is data in the receive FIFO, and \b false -//! if there is no data in the receive FIFO. -// -//***************************************************************************** -#if defined(GROUP_charsavail) || defined(BUILD_ALL) || defined(DOXYGEN) -tBoolean -UARTCharsAvail(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); - - // - // Return the availability of characters. - // - return((HWREG(ulBase + UART_O_FR) & UART_FR_RXFE) ? false : true); -} -#endif - -//***************************************************************************** -// -//! Determines if there is any space in the transmit FIFO. -//! -//! \param ulBase is the base address of the UART port. -//! -//! This function returns a flag indicating whether or not there is space -//! available in the transmit FIFO. -//! -//! \return Returns \b true if there is space available in the transmit FIFO, -//! and \b false if there is no space available in the transmit FIFO. -// -//***************************************************************************** -#if defined(GROUP_spaceavail) || defined(BUILD_ALL) || defined(DOXYGEN) -tBoolean -UARTSpaceAvail(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); - - // - // Return the availability of space. - // - return((HWREG(ulBase + UART_O_FR) & UART_FR_TXFF) ? false : true); -} -#endif - -//***************************************************************************** -// -//! Receives a character from the specified port. -//! -//! \param ulBase is the base address of the UART port. -//! -//! Gets a character from the receive FIFO for the specified port. -//! -//! \return Returns the character read from the specified port, cast as a -//! \e long. A \b -1 will be returned if there are no characters present in -//! the receive FIFO. The UARTCharsAvail() function should be called before -//! attempting to call this function. -// -//***************************************************************************** -#if defined(GROUP_charnonblockingget) || defined(BUILD_ALL) || defined(DOXYGEN) -long -UARTCharNonBlockingGet(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); - - // - // See if there are any characters in the receive FIFO. - // - if(!(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE)) - { - // - // Read and return the next character. - // - return(HWREG(ulBase + UART_O_DR)); - } - else - { - // - // There are no characters, so return a failure. - // - return(-1); - } -} -#endif - -//***************************************************************************** -// -//! Waits for a character from the specified port. -//! -//! \param ulBase is the base address of the UART port. -//! -//! Gets a character from the receive FIFO for the specified port. If there -//! are no characters available, this function will wait until a character is -//! received before returning. -//! -//! \return Returns the character read from the specified port, cast as an -//! \e int. -// -//***************************************************************************** -#if defined(GROUP_charget) || defined(BUILD_ALL) || defined(DOXYGEN) -long -UARTCharGet(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); - - // - // Wait until a char is available. - // - while(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE) - { - } - - // - // Now get the char. - // - return(HWREG(ulBase + UART_O_DR)); -} -#endif - -//***************************************************************************** -// -//! Sends a character to the specified port. -//! -//! \param ulBase is the base address of the UART port. -//! \param ucData is the character to be transmitted. -//! -//! Writes the character \e ucData to the transmit FIFO for the specified port. -//! This function does not block, so if there is no space available, then a -//! \b false is returned, and the application will have to retry the function -//! later. -//! -//! \return Returns \b true if the character was successfully placed in the -//! transmit FIFO, and \b false if there was no space available in the transmit -//! FIFO. -// -//***************************************************************************** -#if defined(GROUP_charnonblockingput) || defined(BUILD_ALL) || defined(DOXYGEN) -tBoolean -UARTCharNonBlockingPut(unsigned long ulBase, unsigned char ucData) -{ - // - // Check the arguments. - // - ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); - - // - // See if there is space in the transmit FIFO. - // - if(!(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF)) - { - // - // Write this character to the transmit FIFO. - // - HWREG(ulBase + UART_O_DR) = ucData; - - // - // Success. - // - return(true); - } - else - { - // - // There is no space in the transmit FIFO, so return a failure. - // - return(false); - } -} -#endif - -//***************************************************************************** -// -//! Waits to send a character from the specified port. -//! -//! \param ulBase is the base address of the UART port. -//! \param ucData is the character to be transmitted. -//! -//! Sends the character \e ucData to the transmit FIFO for the specified port. -//! If there is no space available in the transmit FIFO, this function will -//! wait until there is space available before returning. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_charput) || defined(BUILD_ALL) || defined(DOXYGEN) -void -UARTCharPut(unsigned long ulBase, unsigned char ucData) -{ - // - // Check the arguments. - // - ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); - - // - // Wait until space is available. - // - while(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF) - { - } - - // - // Send the char. - // - HWREG(ulBase + UART_O_DR) = ucData; -} -#endif - -//***************************************************************************** -// -//! Causes a BREAK to be sent. -//! -//! \param ulBase is the base address of the UART port. -//! \param bBreakState controls the output level. -//! -//! Calling this function with \e bBreakState set to \b true will assert a -//! break condition on the UART. Calling this function with \e bBreakState set -//! to \b false will remove the break condition. For proper transmission of a -//! break command, the break must be asserted for at least two complete frames. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_breakctl) || defined(BUILD_ALL) || defined(DOXYGEN) -void -UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState) -{ - // - // Check the arguments. - // - ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); - - // - // Set the break condition as requested. - // - HWREG(ulBase + UART_O_LCR_H) = - (bBreakState ? - (HWREG(ulBase + UART_O_LCR_H) | UART_LCR_H_BRK) : - (HWREG(ulBase + UART_O_LCR_H) & ~(UART_LCR_H_BRK))); -} -#endif - -//***************************************************************************** -// -//! Registers an interrupt handler for a UART interrupt. -//! -//! \param ulBase is the base address of the UART port. -//! \param pfnHandler is a pointer to the function to be called when the -//! UART interrupt occurs. -//! -//! This function does the actual registering of the interrupt handler. This -//! will enable the global interrupt in the interrupt controller; specific UART -//! interrupts must be enabled via UARTIntEnable(). It is the interrupt -//! handler's responsibility to clear the interrupt source. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -UARTIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) -{ - unsigned long ulInt; - - // - // Check the arguments. - // - ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); - - // - // Determine the interrupt number based on the UART port. - // - ulInt = (ulBase == UART0_BASE) ? INT_UART0 : INT_UART1; - - // - // Register the interrupt handler. - // - IntRegister(ulInt, pfnHandler); - - // - // Enable the UART interrupt. - // - IntEnable(ulInt); -} -#endif - -//***************************************************************************** -// -//! Unregisters an interrupt handler for a UART interrupt. -//! -//! \param ulBase is the base address of the UART port. -//! -//! This function does the actual unregistering of the interrupt handler. It -//! will clear the handler to be called when a UART interrupt occurs. This -//! will also mask off the interrupt in the interrupt controller so that the -//! interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -UARTIntUnregister(unsigned long ulBase) -{ - unsigned long ulInt; - - // - // Check the arguments. - // - ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); - - // - // Determine the interrupt number based on the UART port. - // - ulInt = (ulBase == UART0_BASE) ? INT_UART0 : INT_UART1; - - // - // Disable the interrupt. - // - IntDisable(ulInt); - - // - // Unregister the interrupt handler. - // - IntUnregister(ulInt); -} -#endif - -//***************************************************************************** -// -//! Enables individual UART interrupt sources. -//! -//! \param ulBase is the base address of the UART port. -//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. -//! -//! Enables the indicated UART interrupt sources. Only the sources that are -//! enabled can be reflected to the processor interrupt; disabled sources have -//! no effect on the processor. -//! -//! The parameter \e ulIntFlags is the logical OR of any of the following: -//! -//! - UART_INT_OE - Overrun Error interrupt -//! - UART_INT_BE - Break Error interrupt -//! - UART_INT_PE - Parity Error interrupt -//! - UART_INT_FE - Framing Error interrupt -//! - UART_INT_RT - Receive Timeout interrupt -//! - UART_INT_TX - Transmit interrupt -//! - UART_INT_RX - Receive interrupt -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags) -{ - // - // Check the arguments. - // - ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); - - // - // Enable the specified interrupts. - // - HWREG(ulBase + UART_O_IM) |= ulIntFlags; -} -#endif - -//***************************************************************************** -// -//! Disables individual UART interrupt sources. -//! -//! \param ulBase is the base address of the UART port. -//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. -//! -//! Disables the indicated UART interrupt sources. Only the sources that are -//! enabled can be reflected to the processor interrupt; disabled sources have -//! no effect on the processor. -//! -//! The parameter \e ulIntFlags has the same definition as the same parameter -//! to UARTIntEnable(). -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags) -{ - // - // Check the arguments. - // - ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); - - // - // Disable the specified interrupts. - // - HWREG(ulBase + UART_O_IM) &= ~(ulIntFlags); -} -#endif - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \param ulBase is the base address of the UART port. -//! \param bMasked is false if the raw interrupt status is required and true -//! if the masked interrupt status is required. -//! -//! This returns the interrupt status for the specified UART. Either the raw -//! interrupt status or the status of interrupts that are allowed to reflect to -//! the processor can be returned. -//! -//! \return The current interrupt status, enumerated as a bit field of -//! values described in UARTIntEnable(). -// -//***************************************************************************** -#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -UARTIntStatus(unsigned long ulBase, tBoolean bMasked) -{ - // - // Check the arguments. - // - ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(ulBase + UART_O_MIS)); - } - else - { - return(HWREG(ulBase + UART_O_RIS)); - } -} -#endif - -//***************************************************************************** -// -//! Clears UART interrupt sources. -//! -//! \param ulBase is the base address of the UART port. -//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. -//! -//! The specified UART interrupt sources are cleared, so that they no longer -//! assert. This must be done in the interrupt handler to keep it from being -//! called again immediately upon exit. -//! -//! The parameter \e ulIntFlags has the same definition as the same parameter -//! to UARTIntEnable(). -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) -void -UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags) -{ - // - // Check the arguments. - // - ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE)); - - // - // Clear the requested interrupt sources. - // - HWREG(ulBase + UART_O_ICR) = ulIntFlags; -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/uart.h b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/uart.h deleted file mode 100644 index b82f2eec5..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/uart.h +++ /dev/null @@ -1,102 +0,0 @@ -//***************************************************************************** -// -// uart.h - Defines and Macros for the UART. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __UART_H__ -#define __UART_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear -// as the ulIntFlags parameter, and returned from UARTIntStatus. -// -//***************************************************************************** -#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask -#define UART_INT_BE 0x200 // Break Error Interrupt Mask -#define UART_INT_PE 0x100 // Parity Error Interrupt Mask -#define UART_INT_FE 0x080 // Framing Error Interrupt Mask -#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask -#define UART_INT_TX 0x020 // Transmit Interrupt Mask -#define UART_INT_RX 0x010 // Receive Interrupt Mask - -//***************************************************************************** -// -// Values that can be passed to UARTConfigSet as the ulConfig parameter and -// returned by UARTConfigGet in the pulConfig parameter. Additionally, the -// UART_CONFIG_PAR_* subset can be passed to UARTParityModeSet as the ulParity -// parameter, and are returned by UARTParityModeGet. -// -//***************************************************************************** -#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data -#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data -#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data -#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data -#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit -#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits -#define UART_CONFIG_PAR_NONE 0x00000000 // No parity -#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity -#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity -#define UART_CONFIG_PAR_ONE 0x00000086 // Parity bit is one -#define UART_CONFIG_PAR_ZERO 0x00000082 // Parity bit is zero - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity); -extern unsigned long UARTParityModeGet(unsigned long ulBase); -extern void UARTConfigSet(unsigned long ulBase, unsigned long ulBaud, - unsigned long ulConfig); -extern void UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud, - unsigned long *pulConfig); -extern void UARTEnable(unsigned long ulBase); -extern void UARTDisable(unsigned long ulBase); -extern tBoolean UARTCharsAvail(unsigned long ulBase); -extern tBoolean UARTSpaceAvail(unsigned long ulBase); -extern long UARTCharNonBlockingGet(unsigned long ulBase); -extern long UARTCharGet(unsigned long ulBase); -extern tBoolean UARTCharNonBlockingPut(unsigned long ulBase, - unsigned char ucData); -extern void UARTCharPut(unsigned long ulBase, unsigned char ucData); -extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState); -extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); -extern void UARTIntUnregister(unsigned long ulBase); -extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags); - -#ifdef __cplusplus -} -#endif - -#endif // __UART_H__ diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/watchdog.c b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/watchdog.c deleted file mode 100644 index 53332d051..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/watchdog.c +++ /dev/null @@ -1,592 +0,0 @@ -//***************************************************************************** -// -// watchdog.c - Driver for the Watchdog Timer Module. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup watchdog_api -//! @{ -// -//***************************************************************************** - -#include "../hw_ints.h" -#include "../hw_memmap.h" -#include "../hw_types.h" -#include "../hw_watchdog.h" -#include "debug.h" -#include "interrupt.h" -#include "watchdog.h" - -//***************************************************************************** -// -//! Determines if the watchdog timer is enabled. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! This will check to see if the watchdog timer is enabled. -//! -//! \return Returns \b true if the watchdog timer is enabled, and \b false -//! if it is not. -// -//***************************************************************************** -#if defined(GROUP_running) || defined(BUILD_ALL) || defined(DOXYGEN) -tBoolean -WatchdogRunning(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == WATCHDOG_BASE); - - // - // See if the watchdog timer module is enabled, and return. - // - return(HWREG(ulBase + WDT_O_CTL) & WDT_CTL_INTEN); -} -#endif - -//***************************************************************************** -// -//! Enables the watchdog timer. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! This will enable the watchdog timer counter and interrupt. -//! -//! \note This function will have no effect if the watchdog timer has -//! been locked. -//! -//! \sa WatchdogLock(), WatchdogUnlock() -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -WatchdogEnable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == WATCHDOG_BASE); - - // - // Enable the watchdog timer module. - // - HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_INTEN; -} -#endif - -//***************************************************************************** -// -//! Enables the watchdog timer reset. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! Enables the capability of the watchdog timer to issue a reset to the -//! processor upon a second timeout condition. -//! -//! \note This function will have no effect if the watchdog timer has -//! been locked. -//! -//! \sa WatchdogLock(), WatchdogUnlock() -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_resetenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -WatchdogResetEnable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == WATCHDOG_BASE); - - // - // Enable the watchdog reset. - // - HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_RESEN; -} -#endif - -//***************************************************************************** -// -//! Disables the watchdog timer reset. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! Disables the capability of the watchdog timer to issue a reset to the -//! processor upon a second timeout condition. -//! -//! \note This function will have no effect if the watchdog timer has -//! been locked. -//! -//! \sa WatchdogLock(), WatchdogUnlock() -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_resetdisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -WatchdogResetDisable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == WATCHDOG_BASE); - - // - // Disable the watchdog reset. - // - HWREG(ulBase + WDT_O_CTL) &= ~(WDT_CTL_RESEN); -} -#endif - -//***************************************************************************** -// -//! Enables the watchdog timer lock mechanism. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! Locks out write access to the watchdog timer configuration registers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_lock) || defined(BUILD_ALL) || defined(DOXYGEN) -void -WatchdogLock(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == WATCHDOG_BASE); - - // - // Lock out watchdog register writes. Writing anything to the WDT_O_LOCK - // register causes the lock to go into effect. - // - HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_LOCKED; -} -#endif - -//***************************************************************************** -// -//! Disables the watchdog timer lock mechanism. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! Enables write access to the watchdog timer configuration registers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_unlock) || defined(BUILD_ALL) || defined(DOXYGEN) -void -WatchdogUnlock(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == WATCHDOG_BASE); - - // - // Unlock watchdog register writes. - // - HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_UNLOCK; -} -#endif - -//***************************************************************************** -// -//! Gets the state of the watchdog timer lock mechanism. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! Returns the lock state of the watchdog timer registers. -//! -//! \return Returns \b true if the watchdog timer registers are locked, and -//! \b false if they are not locked. -// -//***************************************************************************** -#if defined(GROUP_lockstate) || defined(BUILD_ALL) || defined(DOXYGEN) -tBoolean -WatchdogLockState(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == WATCHDOG_BASE); - - // - // Get the lock state. - // - return((HWREG(ulBase + WDT_O_LOCK) == WDT_LOCK_LOCKED) ? true : false); -} -#endif - -//***************************************************************************** -// -//! Sets the watchdog timer reload value. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! \param ulLoadVal is the load value for the watchdog timer. -//! -//! This function sets the value to load into the watchdog timer when the count -//! reaches zero for the first time; if the watchdog timer is running when this -//! function is called, then the value will be immediately loaded into the -//! watchdog timer counter. If the parameter \e ulLoadVal is 0, then an -//! interrupt is immediately generated. -//! -//! \note This function will have no effect if the watchdog timer has -//! been locked. -//! -//! \sa WatchdogLock(), WatchdogUnlock(), WatchdogReloadGet() -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_reloadset) || defined(BUILD_ALL) || defined(DOXYGEN) -void -WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal) -{ - // - // Check the arguments. - // - ASSERT(ulBase == WATCHDOG_BASE); - - // - // Set the load register. - // - HWREG(ulBase + WDT_O_LOAD) = ulLoadVal; -} -#endif - -//***************************************************************************** -// -//! Gets the watchdog timer reload value. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! This function gets the value that is loaded into the watchdog timer when -//! the count reaches zero for the first time. -//! -//! \sa WatchdogReloadSet() -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_reloadget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -WatchdogReloadGet(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == WATCHDOG_BASE); - - // - // Get the load register. - // - return(HWREG(ulBase + WDT_O_LOAD)); -} -#endif - -//***************************************************************************** -// -//! Gets the current watchdog timer value. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! This function reads the current value of the watchdog timer. -//! -//! \return Returns the current value of the watchdog timer. -// -//***************************************************************************** -#if defined(GROUP_valueget) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -WatchdogValueGet(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == WATCHDOG_BASE); - - // - // Get the current watchdog timer register value. - // - return(HWREG(ulBase + WDT_O_VALUE)); -} -#endif - -//***************************************************************************** -// -//! Registers an interrupt handler for watchdog timer interrupt. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! \param pfnHandler is a pointer to the function to be called when the -//! watchdog timer interrupt occurs. -//! -//! This function does the actual registering of the interrupt handler. This -//! will enable the global interrupt in the interrupt controller; the watchdog -//! timer interrupt must be enabled via WatchdogEnable(). It is the interrupt -//! handler's responsibility to clear the interrupt source via -//! WatchdogIntClear(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -WatchdogIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT(ulBase == WATCHDOG_BASE); - - // - // Register the interrupt handler. - // - IntRegister(INT_WATCHDOG, pfnHandler); - - // - // Enable the watchdog timer interrupt. - // - IntEnable(INT_WATCHDOG); -} -#endif - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the watchdog timer interrupt. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! This function does the actual unregistering of the interrupt handler. This -//! function will clear the handler to be called when a watchdog timer -//! interrupt occurs. This will also mask off the interrupt in the interrupt -//! controller so that the interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN) -void -WatchdogIntUnregister(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == WATCHDOG_BASE); - - // - // Disable the interrupt. - // - IntDisable(INT_WATCHDOG); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_WATCHDOG); -} -#endif - -//***************************************************************************** -// -//! Enables the watchdog timer interrupt. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! Enables the watchdog timer interrupt. -//! -//! \note This function will have no effect if the watchdog timer has -//! been locked. -//! -//! \sa WatchdogLock(), WatchdogUnlock(), WatchdogEnable() -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -WatchdogIntEnable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == WATCHDOG_BASE); - - // - // Enable the watchdog interrupt. - // - HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_INTEN; -} -#endif - -//***************************************************************************** -// -//! Gets the current watchdog timer interrupt status. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! \param bMasked is \b false if the raw interrupt status is required and -//! \b true if the masked interrupt status is required. -//! -//! This returns the interrupt status for the watchdog timer module. Either -//! the raw interrupt status or the status of interrupt that is allowed to -//! reflect to the processor can be returned. -//! -//! \return The current interrupt status, where a 1 indicates that the watchdog -//! interrupt is active, and a 0 indicates that it is not active. -// -//***************************************************************************** -#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN) -unsigned long -WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked) -{ - // - // Check the arguments. - // - ASSERT(ulBase == WATCHDOG_BASE); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(ulBase + WDT_O_MIS)); - } - else - { - return(HWREG(ulBase + WDT_O_RIS)); - } -} -#endif - -//***************************************************************************** -// -//! Clears the watchdog timer interrupt. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! The watchdog timer interrupt source is cleared, so that it no longer -//! asserts. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN) -void -WatchdogIntClear(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == WATCHDOG_BASE); - - // - // Clear the interrupt source. - // - HWREG(ulBase + WDT_O_ICR) = WDT_INT_TIMEOUT; -} -#endif - -//***************************************************************************** -// -//! Enables stalling of the watchdog timer during debug events. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! This function allows the watchdog timer to stop counting when the processor -//! is stopped by the debugger. By doing so, the watchdog is prevented from -//! expiring (typically almost immediately from a human time perspective) and -//! resetting the system (if reset is enabled). The watchdog will instead -//! expired after the appropriate number of processor cycles have been executed -//! while debugging (or at the appropriate time after the processor has been -//! restarted). -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_stallenable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -WatchdogStallEnable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == WATCHDOG_BASE); - - // - // Enable timer stalling. - // - HWREG(ulBase + WDT_O_TEST) |= WDT_TEST_STALL; -} -#endif - -//***************************************************************************** -// -//! Disables stalling of the watchdog timer during debug events. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! This function disables the debug mode stall of the watchdog timer. By -//! doing so, the watchdog timer continues to count regardless of the processor -//! debug state. -//! -//! \return None. -// -//***************************************************************************** -#if defined(GROUP_stalldisable) || defined(BUILD_ALL) || defined(DOXYGEN) -void -WatchdogStallDisable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == WATCHDOG_BASE); - - // - // Disable timer stalling. - // - HWREG(ulBase + WDT_O_TEST) &= ~(WDT_TEST_STALL); -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/watchdog.h b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/watchdog.h deleted file mode 100644 index 9378504a0..000000000 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/watchdog.h +++ /dev/null @@ -1,63 +0,0 @@ -//***************************************************************************** -// -// watchdog.h - Prototypes for the Watchdog Timer API -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __WATCHDOG_H__ -#define __WATCHDOG_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern tBoolean WatchdogRunning(unsigned long ulBase); -extern void WatchdogEnable(unsigned long ulBase); -extern void WatchdogResetEnable(unsigned long ulBase); -extern void WatchdogResetDisable(unsigned long ulBase); -extern void WatchdogLock(unsigned long ulBase); -extern void WatchdogUnlock(unsigned long ulBase); -extern tBoolean WatchdogLockState(unsigned long ulBase); -extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal); -extern unsigned long WatchdogReloadGet(unsigned long ulBase); -extern unsigned long WatchdogValueGet(unsigned long ulBase); -extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); -extern void WatchdogIntUnregister(unsigned long ulBase); -extern void WatchdogIntEnable(unsigned long ulBase); -extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void WatchdogIntClear(unsigned long ulBase); -extern void WatchdogStallDisable(unsigned long ulBase); -extern void WatchdogStallDisable(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __WATCHDOG_H__ diff --git a/Demo/CORTEX_LM3S811_IAR/RTOSDemo.dep b/Demo/CORTEX_LM3S811_IAR/RTOSDemo.dep deleted file mode 100644 index 53577a423..000000000 --- a/Demo/CORTEX_LM3S811_IAR/RTOSDemo.dep +++ /dev/null @@ -1,430 +0,0 @@ - - - - 2 - - Debug - - $PROJ_DIR$\ewarm\Exe\RTOSDemo.sim - $PROJ_DIR$\LuminaryCode\osram96x16.h - $PROJ_DIR$\ewarm\Obj\main.pbi - $TOOLKIT_DIR$\lib\dl7mptnnl8f.h - $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portmacro.h - $PROJ_DIR$\LuminaryCode\pwm.h - $PROJ_DIR$\ewarm\Obj\BlockQ.r79 - $PROJ_DIR$\ewarm\Obj\heap_1.pbi - $PROJ_DIR$\LuminaryCode\interrupt.h - $PROJ_DIR$\LuminaryCode\watchdog.h - $TOOLKIT_DIR$\inc\DLib_Threads.h - $PROJ_DIR$\..\..\Source\include\portable.h - $PROJ_DIR$\ewarm\Obj\list.r79 - $PROJ_DIR$\LuminaryCode\driverlib.r79 - $PROJ_DIR$\LuminaryCode\debug.h - $PROJ_DIR$\..\Common\include\semtest.h - $PROJ_DIR$\LuminaryCode\timer.h - $PROJ_DIR$\..\Common\include\PollQ.h - $PROJ_DIR$\ewarm\Obj\tasks.pbi - $PROJ_DIR$\ewarm\Obj\osram96x16.r79 - $PROJ_DIR$\..\..\Source\list.c - $PROJ_DIR$\ewarm\List\RTOSDemo.map - $PROJ_DIR$\LuminaryCode\hw_types.h - $PROJ_DIR$\LuminaryCode\hw_timer.h - $PROJ_DIR$\LuminaryCode\systick.h - $PROJ_DIR$\LuminaryCode\adc.h - $PROJ_DIR$\..\Common\Minimal\BlockQ.c - $PROJ_DIR$\LuminaryCode\ssi.h - $PROJ_DIR$\ewarm\Exe\RTOSDemo.d79 - $PROJ_DIR$\LuminaryCode\hw_watchdog.h - $PROJ_DIR$\LuminaryCode\hw_gpio.h - $PROJ_DIR$\ewarm\Obj\startup.r79 - $PROJ_DIR$\LuminaryCode\hw_ints.h - $PROJ_DIR$\startup.c - $PROJ_DIR$\..\..\Source\portable\MemMang\heap_1.c - $PROJ_DIR$\..\Common\include\integer.h - $PROJ_DIR$\FreeRTOSConfig.h - $PROJ_DIR$\LuminaryCode\flash.h - $PROJ_DIR$\ewarm\Obj\startup.pbi - $PROJ_DIR$\..\..\Source\include\croutine.h - $PROJ_DIR$\ewarm\Obj\heap_1.r79 - $TOOLKIT_DIR$\lib\dl7mptnnl8f.r79 - $PROJ_DIR$\LuminaryCode\qei.h - $PROJ_DIR$\LuminaryCode\DriverLib.h - $PROJ_DIR$\..\..\Source\include\semphr.h - $PROJ_DIR$\LuminaryCode\osram96x16.c - $PROJ_DIR$\ewarm\Obj\PollQ.r79 - $PROJ_DIR$\LuminaryCode\hw_ssi.h - $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s - $PROJ_DIR$\ewarm\Obj\main.r79 - $PROJ_DIR$\..\..\Source\queue.c - $TOOLKIT_DIR$\inc\yvals.h - $TOOLKIT_DIR$\inc\stdlib.h - $PROJ_DIR$\LuminaryCode\hw_pwm.h - $PROJ_DIR$\..\..\Source\include\task.h - $PROJ_DIR$\LuminaryCode\hw_uart.h - $PROJ_DIR$\..\Common\Minimal\PollQ.c - $PROJ_DIR$\LuminaryCode\gpio.h - $PROJ_DIR$\LuminaryCode\hw_comp.h - $PROJ_DIR$\ewarm\Obj\port.r79 - $PROJ_DIR$\ewarm\Obj\tasks.r79 - $PROJ_DIR$\LuminaryCode\hw_i2c.h - $PROJ_DIR$\ewarm\Obj\PollQ.pbi - $PROJ_DIR$\ewarm\Obj\queue.pbi - $PROJ_DIR$\ewarm\Obj\integer.pbi - $TOOLKIT_DIR$\inc\string.h - $TOOLKIT_DIR$\inc\stddef.h - $TOOLKIT_DIR$\inc\DLib_Product.h - $PROJ_DIR$\LuminaryCode\cpu.h - $PROJ_DIR$\ewarm\Obj\semtest.pbi - $PROJ_DIR$\LuminaryCode\hw_memmap.h - $PROJ_DIR$\ewarm\Obj\BlockQ.pbi - $PROJ_DIR$\..\Common\Minimal\integer.c - $PROJ_DIR$\LuminaryCode\hw_qei.h - $PROJ_DIR$\LuminaryCode\hw_adc.h - $TOOLKIT_DIR$\inc\ysizet.h - $PROJ_DIR$\ewarm\Obj\RTOSDemo.pbd - $TOOLKIT_DIR$\inc\DLib_Defaults.h - $TOOLKIT_DIR$\inc\xencoding_limits.h - $PROJ_DIR$\standalone.xcl - $PROJ_DIR$\main.c - $PROJ_DIR$\..\Common\Minimal\semtest.c - $PROJ_DIR$\LuminaryCode\comp.h - $PROJ_DIR$\..\..\Source\tasks.c - $PROJ_DIR$\LuminaryCode\hw_flash.h - $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c - $PROJ_DIR$\..\..\Source\include\list.h - $PROJ_DIR$\ewarm\Obj\queue.r79 - $PROJ_DIR$\..\..\Source\include\FreeRTOS.h - $PROJ_DIR$\LuminaryCode\hw_nvic.h - $PROJ_DIR$\ewarm\Obj\portasm.r79 - $PROJ_DIR$\ewarm\Obj\semtest.r79 - $TOOLKIT_DIR$\inc\stdio.h - $PROJ_DIR$\..\..\Source\include\projdefs.h - $PROJ_DIR$\LuminaryCode\i2c.h - $PROJ_DIR$\ewarm\Obj\list.pbi - $PROJ_DIR$\ewarm\Obj\osram96x16.pbi - $PROJ_DIR$\ewarm\Obj\integer.r79 - $PROJ_DIR$\LuminaryCode\uart.h - $PROJ_DIR$\ewarm\Obj\port.pbi - $PROJ_DIR$\..\..\Source\include\queue.h - $PROJ_DIR$\LuminaryCode\sysctl.h - $PROJ_DIR$\..\Common\include\BlockQ.h - $PROJ_DIR$\LuminaryCode\hw_sysctl.h - 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- - BICOMP - 88 66 51 77 67 78 10 75 93 36 11 4 54 86 - - - - - - - diff --git a/Demo/CORTEX_LM3S811_IAR/RTOSDemo.ewd b/Demo/CORTEX_LM3S811_IAR/RTOSDemo.ewd deleted file mode 100644 index 8e50f7c4c..000000000 --- a/Demo/CORTEX_LM3S811_IAR/RTOSDemo.ewd +++ /dev/null @@ -1,570 +0,0 @@ - - - - 1 - - Debug - - ARM - - 1 - - C-SPY - 2 - - 13 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - ARMSIM_ID - 2 - - 0 - 1 - 1 - - - - - ANGEL_ID - 2 - - 0 - 1 - 1 - - - - - - - - - - - - IARROM_ID - 2 - - 0 - 1 - 1 - - - - - - - - - - JLINK_ID - 2 - - 6 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - LMIFTDI_ID - 2 - - 0 - 1 - 1 - - - - - - - - - - - - MACRAIGOR_ID - 2 - - 2 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - RDI_ID - 2 - - 1 - 1 - 1 - - - - - - - - - - - - - - - - - THIRDPARTY_ID - 2 - - 0 - 1 - 1 - - - - - - - - - $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin - 1 - - - $EW_DIR$\common\plugins\Orti\Orti.ewplugin - 0 - - - $EW_DIR$\common\plugins\Profiling\Profiling.ewplugin - 1 - - - $EW_DIR$\common\plugins\Stack\Stack.ewplugin - 1 - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin - 0 - - - - - - diff --git a/Demo/CORTEX_LM3S811_IAR/RTOSDemo.ewp b/Demo/CORTEX_LM3S811_IAR/RTOSDemo.ewp deleted file mode 100644 index c4f6b76bd..000000000 --- a/Demo/CORTEX_LM3S811_IAR/RTOSDemo.ewp +++ /dev/null @@ -1,886 +0,0 @@ - - - - 1 - - Debug - - ARM - - 1 - - General - 2 - - 9 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 14 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 7 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - XLINK - 2 - - 18 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - XAR - 2 - - 0 - 1 - 1 - - - - - - - BILINK - 0 - - - - - Demo Source - - $PROJ_DIR$\..\Common\Minimal\BlockQ.c - - - $PROJ_DIR$\..\Common\Minimal\integer.c - - - $PROJ_DIR$\main.c - - - $PROJ_DIR$\LuminaryCode\osram96x16.c - - - $PROJ_DIR$\..\Common\Minimal\PollQ.c - - - $PROJ_DIR$\..\Common\Minimal\semtest.c - - - $PROJ_DIR$\startup.c - - - - Libraries - - $PROJ_DIR$\LuminaryCode\driverlib.r79 - - - - Scheduler Source - - $PROJ_DIR$\..\..\Source\portable\MemMang\heap_1.c - - - $PROJ_DIR$\..\..\Source\list.c - - - $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c - - - $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s - - - $PROJ_DIR$\..\..\Source\queue.c - - - $PROJ_DIR$\..\..\Source\tasks.c - - - - - diff --git a/Demo/CORTEX_LM3S811_IAR/RTOSDemo.eww b/Demo/CORTEX_LM3S811_IAR/RTOSDemo.eww deleted file mode 100644 index b7687f61f..000000000 --- a/Demo/CORTEX_LM3S811_IAR/RTOSDemo.eww +++ /dev/null @@ -1,54 +0,0 @@ - - - - - $WS_DIR$\RTOSDemo.ewp - - - - All Examples - - driverlib - Debug - - - bitband - Debug - - - gpio_jtag - Debug - - - hello - Debug - - - interrupts - Debug - - - pwmgen - Debug - - - qs_ev-lm3s811 - Debug - - - timers - Debug - - - uart_echo - Debug - - - watchdog - Debug - - - - - - diff --git a/Demo/CORTEX_LM3S811_IAR/main.c b/Demo/CORTEX_LM3S811_IAR/main.c deleted file mode 100644 index fdb478981..000000000 --- a/Demo/CORTEX_LM3S811_IAR/main.c +++ /dev/null @@ -1,362 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/* - * This project contains an application demonstrating the use of the - * FreeRTOS.org mini real time scheduler on the Luminary Micro LM3S811 Eval - * board. See http://www.FreeRTOS.org for more information. - * - * main() simply sets up the hardware, creates all the demo application tasks, - * then starts the scheduler. http://www.freertos.org/a00102.html provides - * more information on the standard demo tasks. - * - * In addition to a subset of the standard demo application tasks, main.c also - * defines the following tasks: - * - * + A 'Print' task. The print task is the only task permitted to access the - * LCD - thus ensuring mutual exclusion and consistent access to the resource. - * Other tasks do not access the LCD directly, but instead send the text they - * wish to display to the print task. The print task spends most of its time - * blocked - only waking when a message is queued for display. - * - * + A 'Button handler' task. The eval board contains a user push button that - * is configured to generate interrupts. The interrupt handler uses a - * semaphore to wake the button handler task - demonstrating how the priority - * mechanism can be used to defer interrupt processing to the task level. The - * button handler task sends a message both to the LCD (via the print task) and - * the UART where it can be viewed using a dumb terminal (via the UART to USB - * converter on the eval board). NOTES: The dumb terminal must be closed in - * order to reflash the microcontroller. A very basic interrupt driven UART - * driver is used that does not use the FIFO. 19200 baud is used. - * - * + A 'check' task. The check task only executes every five seconds but has a - * high priority so is guaranteed to get processor time. Its function is to - * check that all the other tasks are still operational and that no errors have - * been detected at any time. If no errors have every been detected 'PASS' is - * written to the display (via the print task) - if an error has ever been - * detected the message is changed to 'FAIL'. The position of the message is - * changed for each write. - */ - - - -/* Environment includes. */ -#include "DriverLib.h" - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" -#include "semphr.h" - -/* Demo app includes. */ -#include "integer.h" -#include "PollQ.h" -#include "semtest.h" -#include "BlockQ.h" - -/* Delay between cycles of the 'check' task. */ -#define mainCHECK_DELAY ( ( portTickType ) 5000 / portTICK_RATE_MS ) - -/* UART configuration - note this does not use the FIFO so is not very -efficient. */ -#define mainBAUD_RATE ( 19200 ) -#define mainFIFO_SET ( 0x10 ) - -/* Demo task priorities. */ -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) - -/* Demo board specifics. */ -#define mainPUSH_BUTTON GPIO_PIN_4 - -/* Misc. */ -#define mainQUEUE_SIZE ( 3 ) -#define mainDEBOUNCE_DELAY ( ( portTickType ) 150 / portTICK_RATE_MS ) -#define mainNO_DELAY ( ( portTickType ) 0 ) -/* - * Configure the processor and peripherals for this demo. - */ -static void prvSetupHardware( void ); - -/* - * The 'check' task, as described at the top of this file. - */ -static void vCheckTask( void *pvParameters ); - -/* - * The task that is woken by the ISR that processes GPIO interrupts originating - * from the push button. - */ -static void vButtonHandlerTask( void *pvParameters ); - -/* - * The task that controls access to the LCD. - */ -static void vPrintTask( void *pvParameter ); - -/* String that is transmitted on the UART. */ -static portCHAR *cMessage = "Task woken by button interrupt! --- "; -static volatile portCHAR *pcNextChar; - -/* The semaphore used to wake the button handler task from within the GPIO -interrupt handler. */ -xSemaphoreHandle xButtonSemaphore; - -/* The queue used to send strings to the print task for display on the LCD. */ -xQueueHandle xPrintQueue; - -/*-----------------------------------------------------------*/ - -int main( void ) -{ - /* Configure the clocks, UART and GPIO. */ - prvSetupHardware(); - - /* Create the semaphore used to wake the button handler task from the GPIO - ISR. */ - vSemaphoreCreateBinary( xButtonSemaphore ); - xSemaphoreTake( xButtonSemaphore, 0 ); - - /* Create the queue used to pass message to vPrintTask. */ - xPrintQueue = xQueueCreate( mainQUEUE_SIZE, sizeof( portCHAR * ) ); - - /* Start the standard demo tasks. */ - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - - /* Start the tasks defined within the file. */ - xTaskCreate( vCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - xTaskCreate( vButtonHandlerTask, "Status", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY + 1, NULL ); - xTaskCreate( vPrintTask, "Print", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL ); - - /* Start the scheduler. */ - vTaskStartScheduler(); - - /* Will only get here if there was insufficient heap to start the - scheduler. */ - - return 0; -} -/*-----------------------------------------------------------*/ - -static void vCheckTask( void *pvParameters ) -{ -portBASE_TYPE xErrorOccurred = pdFALSE; -portTickType xLastExecutionTime; -const portCHAR *pcPassMessage = "PASS"; -const portCHAR *pcFailMessage = "FAIL"; - - /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() - works correctly. */ - xLastExecutionTime = xTaskGetTickCount(); - - for( ;; ) - { - /* Perform this check every mainCHECK_DELAY milliseconds. */ - vTaskDelayUntil( &xLastExecutionTime, mainCHECK_DELAY ); - - /* Has an error been found in any task? */ - - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - xErrorOccurred = pdTRUE; - } - - if( xArePollingQueuesStillRunning() != pdTRUE ) - { - xErrorOccurred = pdTRUE; - } - - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - xErrorOccurred = pdTRUE; - } - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - xErrorOccurred = pdTRUE; - } - - /* Send either a pass or fail message. If an error is found it is - never cleared again. We do not write directly to the LCD, but instead - queue a message for display by the print task. */ - if( xErrorOccurred == pdTRUE ) - { - xQueueSend( xPrintQueue, &pcFailMessage, portMAX_DELAY ); - } - else - { - xQueueSend( xPrintQueue, &pcPassMessage, portMAX_DELAY ); - } - } -} -/*-----------------------------------------------------------*/ - -static void prvSetupHardware( void ) -{ - /* Setup the PLL. */ - SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); - - /* Setup the push button. */ - SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC); - GPIODirModeSet(GPIO_PORTC_BASE, mainPUSH_BUTTON, GPIO_DIR_MODE_IN); - GPIOIntTypeSet( GPIO_PORTC_BASE, mainPUSH_BUTTON,GPIO_FALLING_EDGE ); - GPIOPinIntEnable( GPIO_PORTC_BASE, mainPUSH_BUTTON ); - IntEnable( INT_GPIOC ); - - - - /* Enable the UART. */ - SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); - SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); - - /* Set GPIO A0 and A1 as peripheral function. They are used to output the - UART signals. */ - GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); - - /* Configure the UART for 8-N-1 operation. */ - UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); - - /* We don't want to use the fifo. This is for test purposes to generate - as many interrupts as possible. */ - HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; - - /* Enable Tx interrupts. */ - HWREG( UART0_BASE + UART_O_IM ) |= UART_INT_TX; - IntEnable( INT_UART0 ); - - - /* Initialise the LCD> */ - OSRAMInit( false ); - OSRAMStringDraw("www.FreeRTOS.org", 0, 0); - OSRAMStringDraw("LM3S811 demo", 16, 1); -} -/*-----------------------------------------------------------*/ - -static void vButtonHandlerTask( void *pvParameters ) -{ -const portCHAR *pcInterruptMessage = "Int"; - - for( ;; ) - { - /* Wait for a GPIO interrupt to wake this task. */ - while( xSemaphoreTake( xButtonSemaphore, portMAX_DELAY ) != pdPASS ); - - /* Start the Tx of the message on the UART. */ - UARTIntDisable( UART0_BASE, UART_INT_TX ); - { - pcNextChar = cMessage; - - /* Send the first character. */ - if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) - { - HWREG( UART0_BASE + UART_O_DR ) = *pcNextChar; - } - - pcNextChar++; - } - UARTIntEnable(UART0_BASE, UART_INT_TX); - - /* Queue a message for the print task to display on the LCD. */ - xQueueSend( xPrintQueue, &pcInterruptMessage, portMAX_DELAY ); - - /* Make sure we don't process bounces. */ - vTaskDelay( mainDEBOUNCE_DELAY ); - xSemaphoreTake( xButtonSemaphore, mainNO_DELAY ); - } -} - -/*-----------------------------------------------------------*/ - -void vUART_ISR(void) -{ -unsigned portLONG ulStatus; - - /* What caused the interrupt. */ - ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); - - /* Clear the interrupt. */ - UARTIntClear( UART0_BASE, ulStatus ); - - /* Was a Tx interrupt pending? */ - if( ulStatus & UART_INT_TX ) - { - /* Send the next character in the string. We are not using the FIFO. */ - if( *pcNextChar != NULL ) - { - if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) - { - HWREG( UART0_BASE + UART_O_DR ) = *pcNextChar; - } - pcNextChar++; - } - } -} -/*-----------------------------------------------------------*/ - -void vGPIO_ISR( void ) -{ - /* Clear the interrupt. */ - GPIOPinIntClear(GPIO_PORTC_BASE, mainPUSH_BUTTON); - - /* Wake the button handler task. */ - if( xSemaphoreGiveFromISR( xButtonSemaphore, pdFALSE ) ) - { - portEND_SWITCHING_ISR( pdTRUE ); - } -} -/*-----------------------------------------------------------*/ - -static void vPrintTask( void *pvParameters ) -{ -portCHAR *pcMessage; -unsigned portBASE_TYPE uxLine = 0, uxRow = 0; - - for( ;; ) - { - /* Wait for a message to arrive. */ - xQueueReceive( xPrintQueue, &pcMessage, portMAX_DELAY ); - - /* Write the message to the LCD. */ - uxRow++; - uxLine++; - OSRAMClear(); - OSRAMStringDraw( pcMessage, uxLine & 0x3f, uxRow & 0x01); - } -} - diff --git a/Demo/CORTEX_LM3S811_IAR/standalone.xcl b/Demo/CORTEX_LM3S811_IAR/standalone.xcl deleted file mode 100644 index fdd107a75..000000000 --- a/Demo/CORTEX_LM3S811_IAR/standalone.xcl +++ /dev/null @@ -1,37 +0,0 @@ -//***************************************************************************** -// -// standalone.xcl - Linker script for EW-ARM. -// -// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. -// -//***************************************************************************** - -// -// Set the CPU type to ARM. -// --carm - -// -// Define the size of flash and SRAM. -// --DROMSTART=00000000 --DROMEND=0000FFFF --DRAMSTART=20000000 --DRAMEND=20001FFF - -// -// Define the sections to place into flash, and the order to place them. -// --Z(CODE)INTVEC=ROMSTART-ROMEND --Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND --Z(CODE)CODE=ROMSTART-ROMEND --Z(CONST)CODE_ID=ROMSTART-ROMEND --Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND --Z(CONST)CHECKSUM=ROMSTART-ROMEND - -// -// Define the sections to place into SRAM, and the order to place them. -// --Z(DATA)VTABLE=RAMSTART-RAMEND --Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND --Z(DATA)CODE_I=RAMSTART-RAMEND diff --git a/Demo/CORTEX_LM3S811_IAR/startup.c b/Demo/CORTEX_LM3S811_IAR/startup.c deleted file mode 100644 index 44bd7701c..000000000 --- a/Demo/CORTEX_LM3S811_IAR/startup.c +++ /dev/null @@ -1,249 +0,0 @@ -//***************************************************************************** -// -// startup_ewarm.c - Boot code for Stellaris. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 991 of the Stellaris Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -// Enable the IAR extensions for this source file. -// -//***************************************************************************** -#pragma language=extended - -//***************************************************************************** -// -// Forward declaration of the default fault handlers. -// -//***************************************************************************** -void ResetISR(void); -static void NmiSR(void); -static void FaultISR(void); -static void IntDefaultHandler(void); - -//***************************************************************************** -// -// The entry point for the application. -// -//***************************************************************************** -extern int main(void); - -//***************************************************************************** -// -// External declaration for the interrupt handler used by the application. -// -//***************************************************************************** -extern void xPortPendSVHandler(void); -extern void xPortSysTickHandler(void); -extern void vGPIO_ISR(void); -extern void vUART_ISR(void); - -//***************************************************************************** -// -// Reserve space for the system stack. -// -//***************************************************************************** -#ifndef STACK_SIZE -#define STACK_SIZE 64 -#endif -static unsigned long pulStack[STACK_SIZE]; - -//***************************************************************************** -// -// A union that describes the entries of the vector table. The union is needed -// since the first entry is the stack pointer and the remainder are function -// pointers. -// -//***************************************************************************** -typedef union -{ - void (*pfnHandler)(void); - unsigned long ulPtr; -} -uVectorEntry; - -//***************************************************************************** -// -// The minimal vector table for a Cortex M3. Note that the proper constructs -// must be placed on this to ensure that it ends up at physical address -// 0x0000.0000. -// -//***************************************************************************** -__root const uVectorEntry g_pfnVectors[] @ "INTVEC" = -{ - { .ulPtr = (unsigned long)pulStack + sizeof(pulStack) }, - // The initial stack pointer - ResetISR, // The reset handler - NmiSR, // The NMI handler - FaultISR, // The hard fault handler - IntDefaultHandler, // The MPU fault handler - IntDefaultHandler, // The bus fault handler - IntDefaultHandler, // The usage fault handler - 0, // Reserved - 0, // Reserved - 0, // Reserved - 0, // Reserved - IntDefaultHandler, // SVCall handler - IntDefaultHandler, // Debug monitor handler - 0, // Reserved - xPortPendSVHandler, // The PendSV handler - xPortSysTickHandler, // The SysTick handler - IntDefaultHandler, // GPIO Port A - IntDefaultHandler, // GPIO Port B - vGPIO_ISR, // GPIO Port C - IntDefaultHandler, // GPIO Port D - IntDefaultHandler, // GPIO Port E - vUART_ISR, // UART0 Rx and Tx - IntDefaultHandler, // UART1 Rx and Tx - IntDefaultHandler, // SSI Rx and Tx - IntDefaultHandler, // I2C Master and Slave - IntDefaultHandler, // PWM Fault - IntDefaultHandler, // PWM Generator 0 - IntDefaultHandler, // PWM Generator 1 - IntDefaultHandler, // PWM Generator 2 - IntDefaultHandler, // Quadrature Encoder - IntDefaultHandler, // ADC Sequence 0 - IntDefaultHandler, // ADC Sequence 1 - IntDefaultHandler, // ADC Sequence 2 - IntDefaultHandler, // ADC Sequence 3 - IntDefaultHandler, // Watchdog timer - IntDefaultHandler, // Timer 0 subtimer A - IntDefaultHandler, // Timer 0 subtimer B - IntDefaultHandler, // Timer 1 subtimer A - IntDefaultHandler, // Timer 1 subtimer B - IntDefaultHandler, // Timer 2 subtimer A - IntDefaultHandler, // Timer 2 subtimer B - IntDefaultHandler, // Analog Comparator 0 - IntDefaultHandler, // Analog Comparator 1 - IntDefaultHandler, // Analog Comparator 2 - IntDefaultHandler, // System Control (PLL, OSC, BO) - IntDefaultHandler // FLASH Control -}; - -//***************************************************************************** -// -// The following are constructs created by the linker, indicating where the -// the "data" and "bss" segments reside in memory. The initializers for the -// for the "data" segment resides immediately following the "text" segment. -// -//***************************************************************************** -#pragma segment="DATA_ID" -#pragma segment="DATA_I" -#pragma segment="DATA_Z" - -//***************************************************************************** -// -// This is the code that gets called when the processor first starts execution -// following a reset event. Only the absolutely necessary set is performed, -// after which the application supplied entry() routine is called. Any fancy -// actions (such as making decisions based on the reset cause register, and -// resetting the bits in that register) are left solely in the hands of the -// application. -// -//***************************************************************************** -void -ResetISR(void) -{ - unsigned long *pulSrc, *pulDest, *pulEnd; - - // - // Copy the data segment initializers from flash to SRAM. - // - pulSrc = __segment_begin("DATA_ID"); - pulDest = __segment_begin("DATA_I"); - pulEnd = __segment_end("DATA_I"); - while(pulDest < pulEnd) - { - *pulDest++ = *pulSrc++; - } - - // - // Zero fill the bss segment. - // - pulDest = __segment_begin("DATA_Z"); - pulEnd = __segment_end("DATA_Z"); - while(pulDest < pulEnd) - { - *pulDest++ = 0; - } - - // - // Call the application's entry point. - // - main(); -} - -//***************************************************************************** -// -// This is the code that gets called when the processor receives a NMI. This -// simply enters an infinite loop, preserving the system state for examination -// by a debugger. -// -//***************************************************************************** -static void -NmiSR(void) -{ - // - // Enter an infinite loop. - // - while(1) - { - } -} - -//***************************************************************************** -// -// This is the code that gets called when the processor receives a fault -// interrupt. This simply enters an infinite loop, preserving the system state -// for examination by a debugger. -// -//***************************************************************************** -static void -FaultISR(void) -{ - // - // Enter an infinite loop. - // - while(1) - { - } -} - -//***************************************************************************** -// -// This is the code that gets called when the processor receives an unexpected -// interrupt. This simply enters an infinite loop, preserving the system state -// for examination by a debugger. -// -//***************************************************************************** -static void -IntDefaultHandler(void) -{ - // - // Go into an infinite loop. - // - while(1) - { - } -} diff --git a/Demo/CORTEX_LM3S811_KEIL/FreeRTOSConfig.h b/Demo/CORTEX_LM3S811_KEIL/FreeRTOSConfig.h deleted file mode 100644 index 8749cfa03..000000000 --- a/Demo/CORTEX_LM3S811_KEIL/FreeRTOSConfig.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 ) -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 59 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 7000 ) ) -#define configMAX_TASK_NAME_LEN ( 3 ) -#define configUSE_TRACE_FACILITY 0 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 0 -#define configUSE_CO_ROUTINES 0 - -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 ) -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 0 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 - - - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/DriverLib.h b/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/DriverLib.h deleted file mode 100644 index 956bf129a..000000000 --- a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/DriverLib.h +++ /dev/null @@ -1,39 +0,0 @@ -#ifndef DRIVER_LIB_H -#define DRIVER_LIB_H - -#include "DriverLib.h" -#include "hw_adc.h" -#include "hw_comp.h" -#include "hw_flash.h" -#include "hw_gpio.h" -#include "hw_i2c.h" -#include "hw_ints.h" -#include "hw_memmap.h" -#include "hw_nvic.h" -#include "hw_pwm.h" -#include "hw_qei.h" -#include "hw_ssi.h" -#include "hw_sysctl.h" -#include "hw_timer.h" -#include "hw_types.h" -#include "hw_uart.h" -#include "hw_watchdog.h" -#include "osram96x16.h" -#include "src\adc.h" -#include "src\comp.h" -#include "src\cpu.h" -#include "src\debug.h" -#include "src\flash.h" -#include "src\gpio.h" -#include "src\i2c.h" -#include "src\interrupt.h" -#include "src\pwm.h" -#include "src\qei.h" -#include "src\ssi.h" -#include "src\sysctl.h" -#include "src\systick.h" -#include "src\timer.h" -#include "src\uart.h" -#include "src\watchdog.h" - -#endif diff --git a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_adc.h b/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_adc.h deleted file mode 100644 index 4d981c611..000000000 --- a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_adc.h +++ /dev/null @@ -1,329 +0,0 @@ -//***************************************************************************** -// -// hw_adc.h - Macros used when accessing the ADC hardware. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 816 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_ADC_H__ -#define __HW_ADC_H__ - -//***************************************************************************** -// -// The following define the offsets of the ADC registers. -// -//***************************************************************************** -#define ADC_O_ACTSS 0x00000000 // Active sample register -#define ADC_O_RIS 0x00000004 // Raw interrupt status register -#define ADC_O_IM 0x00000008 // Interrupt mask register -#define ADC_O_ISC 0x0000000C // Interrupt status/clear register -#define ADC_O_OSTAT 0x00000010 // Overflow status register -#define ADC_O_EMUX 0x00000014 // Event multiplexer select reg. -#define ADC_O_USTAT 0x00000018 // Underflow status register -#define ADC_O_SSPRI 0x00000020 // Channel priority register -#define ADC_O_PSSI 0x00000028 // Processor sample initiate reg. -#define ADC_O_SSMUX0 0x00000040 // Multiplexer select 0 register -#define ADC_O_SSCTL0 0x00000044 // Sample sequence control 0 reg. -#define ADC_O_SSFIFO0 0x00000048 // Result FIFO 0 register -#define ADC_O_SSFSTAT0 0x0000004C // FIFO 0 status register -#define ADC_O_SSMUX1 0x00000060 // Multiplexer select 1 register -#define ADC_O_SSCTL1 0x00000064 // Sample sequence control 1 reg. -#define ADC_O_SSFIFO1 0x00000068 // Result FIFO 1 register -#define ADC_O_SSFSTAT1 0x0000006C // FIFO 1 status register -#define ADC_O_SSMUX2 0x00000080 // Multiplexer select 2 register -#define ADC_O_SSCTL2 0x00000084 // Sample sequence control 2 reg. -#define ADC_O_SSFIFO2 0x00000088 // Result FIFO 2 register -#define ADC_O_SSFSTAT2 0x0000008C // FIFO 2 status register -#define ADC_O_SSMUX3 0x000000A0 // Multiplexer select 3 register -#define ADC_O_SSCTL3 0x000000A4 // Sample sequence control 3 reg. -#define ADC_O_SSFIFO3 0x000000A8 // Result FIFO 3 register -#define ADC_O_SSFSTAT3 0x000000AC // FIFO 3 status register -#define ADC_O_TMLB 0x00000100 // Test mode loopback register - -//***************************************************************************** -// -// The following define the offsets of the ADC sequence registers. -// -//***************************************************************************** -#define ADC_O_SEQ 0x00000040 // Offset to the first sequence -#define ADC_O_SEQ_STEP 0x00000020 // Increment to the next sequence -#define ADC_O_X_SSMUX 0x00000000 // Multiplexer select register -#define ADC_O_X_SSCTL 0x00000004 // Sample sequence control register -#define ADC_O_X_SSFIFO 0x00000008 // Result FIFO register -#define ADC_O_X_SSFSTAT 0x0000000C // FIFO status register - -//***************************************************************************** -// -// The following define the bit fields in the ADC_ACTSS register. -// -//***************************************************************************** -#define ADC_ACTSS_ASEN3 0x00000008 // Sample sequence 3 enable -#define ADC_ACTSS_ASEN2 0x00000004 // Sample sequence 2 enable -#define ADC_ACTSS_ASEN1 0x00000002 // Sample sequence 1 enable -#define ADC_ACTSS_ASEN0 0x00000001 // Sample sequence 0 enable - -//***************************************************************************** -// -// The following define the bit fields in the ADC_RIS register. -// -//***************************************************************************** -#define ADC_RIS_INR3 0x00000008 // Sample sequence 3 interrupt -#define ADC_RIS_INR2 0x00000004 // Sample sequence 2 interrupt -#define ADC_RIS_INR1 0x00000002 // Sample sequence 1 interrupt -#define ADC_RIS_INR0 0x00000001 // Sample sequence 0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the ADC_IM register. -// -//***************************************************************************** -#define ADC_IM_MASK3 0x00000008 // Sample sequence 3 mask -#define ADC_IM_MASK2 0x00000004 // Sample sequence 2 mask -#define ADC_IM_MASK1 0x00000002 // Sample sequence 1 mask -#define ADC_IM_MASK0 0x00000001 // Sample sequence 0 mask - -//***************************************************************************** -// -// The following define the bit fields in the ADC_ISC register. -// -//***************************************************************************** -#define ADC_ISC_IN3 0x00000008 // Sample sequence 3 interrupt -#define ADC_ISC_IN2 0x00000004 // Sample sequence 2 interrupt -#define ADC_ISC_IN1 0x00000002 // Sample sequence 1 interrupt -#define ADC_ISC_IN0 0x00000001 // Sample sequence 0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the ADC_OSTAT register. -// -//***************************************************************************** -#define ADC_OSTAT_OV3 0x00000008 // Sample sequence 3 overflow -#define ADC_OSTAT_OV2 0x00000004 // Sample sequence 2 overflow -#define ADC_OSTAT_OV1 0x00000002 // Sample sequence 1 overflow -#define ADC_OSTAT_OV0 0x00000001 // Sample sequence 0 overflow - -//***************************************************************************** -// -// The following define the bit fields in the ADC_EMUX register. -// -//***************************************************************************** -#define ADC_EMUX_EM3_MASK 0x0000F000 // Event mux 3 mask -#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor event -#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog comparator 0 event -#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog comparator 1 event -#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog comparator 2 event -#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External event -#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer event -#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0 event -#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1 event -#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2 event -#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always event -#define ADC_EMUX_EM2_MASK 0x00000F00 // Event mux 2 mask -#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor event -#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog comparator 0 event -#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog comparator 1 event -#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog comparator 2 event -#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External event -#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer event -#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0 event -#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1 event -#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2 event -#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always event -#define ADC_EMUX_EM1_MASK 0x000000F0 // Event mux 1 mask -#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor event -#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog comparator 0 event -#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog comparator 1 event -#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog comparator 2 event -#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External event -#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer event -#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0 event -#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1 event -#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2 event -#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always event -#define ADC_EMUX_EM0_MASK 0x0000000F // Event mux 0 mask -#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor event -#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog comparator 0 event -#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog comparator 1 event -#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog comparator 2 event -#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External event -#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer event -#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0 event -#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1 event -#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2 event -#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always event -#define ADC_EMUX_EM0_SHIFT 0 // The shift for the first event -#define ADC_EMUX_EM1_SHIFT 4 // The shift for the second event -#define ADC_EMUX_EM2_SHIFT 8 // The shift for the third event -#define ADC_EMUX_EM3_SHIFT 12 // The shift for the fourth event - -//***************************************************************************** -// -// The following define the bit fields in the ADC_USTAT register. -// -//***************************************************************************** -#define ADC_USTAT_UV3 0x00000008 // Sample sequence 3 underflow -#define ADC_USTAT_UV2 0x00000004 // Sample sequence 2 underflow -#define ADC_USTAT_UV1 0x00000002 // Sample sequence 1 underflow -#define ADC_USTAT_UV0 0x00000001 // Sample sequence 0 underflow - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSPRI register. -// -//***************************************************************************** -#define ADC_SSPRI_SS3_MASK 0x00003000 // Sequencer 3 priority mask -#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority -#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority -#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority -#define ADC_SSPRI_SS2_MASK 0x00000300 // Sequencer 2 priority mask -#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority -#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority -#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority -#define ADC_SSPRI_SS1_MASK 0x00000030 // Sequencer 1 priority mask -#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority -#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority -#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority -#define ADC_SSPRI_SS0_MASK 0x00000003 // Sequencer 0 priority mask -#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority -#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority -#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority -#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority - -//***************************************************************************** -// -// The following define the bit fields in the ADC_PSSI register. -// -//***************************************************************************** -#define ADC_PSSI_SS3 0x00000008 // Trigger sample sequencer 3 -#define ADC_PSSI_SS2 0x00000004 // Trigger sample sequencer 2 -#define ADC_PSSI_SS1 0x00000002 // Trigger sample sequencer 1 -#define ADC_PSSI_SS0 0x00000001 // Trigger sample sequencer 0 - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSMUX0, ADC_SSMUX1, -// ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present in all -// registers. -// -//***************************************************************************** -#define ADC_SSMUX_MUX7_MASK 0x70000000 // 8th mux select mask -#define ADC_SSMUX_MUX6_MASK 0x07000000 // 7th mux select mask -#define ADC_SSMUX_MUX5_MASK 0x00700000 // 6th mux select mask -#define ADC_SSMUX_MUX4_MASK 0x00070000 // 5th mux select mask -#define ADC_SSMUX_MUX3_MASK 0x00007000 // 4th mux select mask -#define ADC_SSMUX_MUX2_MASK 0x00000700 // 3rd mux select mask -#define ADC_SSMUX_MUX1_MASK 0x00000070 // 2nd mux select mask -#define ADC_SSMUX_MUX0_MASK 0x00000007 // 1st mux select mask -#define ADC_SSMUX_MUX7_SHIFT 28 -#define ADC_SSMUX_MUX6_SHIFT 24 -#define ADC_SSMUX_MUX5_SHIFT 20 -#define ADC_SSMUX_MUX4_SHIFT 16 -#define ADC_SSMUX_MUX3_SHIFT 12 -#define ADC_SSMUX_MUX2_SHIFT 8 -#define ADC_SSMUX_MUX1_SHIFT 4 -#define ADC_SSMUX_MUX0_SHIFT 0 - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSCTL0, ADC_SSCTL1, -// ADC_SSCTL2, and ADC_SSCTL3 registers. Not all fields are present in all -// registers. -// -//***************************************************************************** -#define ADC_SSCTL_TS7 0x80000000 // 8th temperature sensor select -#define ADC_SSCTL_IE7 0x40000000 // 8th interrupt enable -#define ADC_SSCTL_END7 0x20000000 // 8th sequence end select -#define ADC_SSCTL_D7 0x10000000 // 8th differential select -#define ADC_SSCTL_TS6 0x08000000 // 7th temperature sensor select -#define ADC_SSCTL_IE6 0x04000000 // 7th interrupt enable -#define ADC_SSCTL_END6 0x02000000 // 7th sequence end select -#define ADC_SSCTL_D6 0x01000000 // 7th differential select -#define ADC_SSCTL_TS5 0x00800000 // 6th temperature sensor select -#define ADC_SSCTL_IE5 0x00400000 // 6th interrupt enable -#define ADC_SSCTL_END5 0x00200000 // 6th sequence end select -#define ADC_SSCTL_D5 0x00100000 // 6th differential select -#define ADC_SSCTL_TS4 0x00080000 // 5th temperature sensor select -#define ADC_SSCTL_IE4 0x00040000 // 5th interrupt enable -#define ADC_SSCTL_END4 0x00020000 // 5th sequence end select -#define ADC_SSCTL_D4 0x00010000 // 5th differential select -#define ADC_SSCTL_TS3 0x00008000 // 4th temperature sensor select -#define ADC_SSCTL_IE3 0x00004000 // 4th interrupt enable -#define ADC_SSCTL_END3 0x00002000 // 4th sequence end select -#define ADC_SSCTL_D3 0x00001000 // 4th differential select -#define ADC_SSCTL_TS2 0x00000800 // 3rd temperature sensor select -#define ADC_SSCTL_IE2 0x00000400 // 3rd interrupt enable -#define ADC_SSCTL_END2 0x00000200 // 3rd sequence end select -#define ADC_SSCTL_D2 0x00000100 // 3rd differential select -#define ADC_SSCTL_TS1 0x00000080 // 2nd temperature sensor select -#define ADC_SSCTL_IE1 0x00000040 // 2nd interrupt enable -#define ADC_SSCTL_END1 0x00000020 // 2nd sequence end select -#define ADC_SSCTL_D1 0x00000010 // 2nd differential select -#define ADC_SSCTL_TS0 0x00000008 // 1st temperature sensor select -#define ADC_SSCTL_IE0 0x00000004 // 1st interrupt enable -#define ADC_SSCTL_END0 0x00000002 // 1st sequence end select -#define ADC_SSCTL_D0 0x00000001 // 1st differential select - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSFIFO0, ADC_SSFIFO1, -// ADC_SSFIFO2, and ADC_SSFIFO3 registers. -// -//***************************************************************************** -#define ADC_SSFIFO_DATA_MASK 0x000003FF // Sample data -#define ADC_SSFIFO_DATA_SHIFT 0 - -//***************************************************************************** -// -// The following define the bit fields in the ADC_SSFSTAT0, ADC_SSFSTAT1, -// ADC_SSFSTAT2, and ADC_SSFSTAT3 registers. -// -//***************************************************************************** -#define ADC_SSFSTAT_FULL 0x00001000 // FIFO is full -#define ADC_SSFSTAT_EMPTY 0x00000100 // FIFO is empty -#define ADC_SSFSTAT_HPTR 0x000000F0 // FIFO head pointer -#define ADC_SSFSTAT_TPTR 0x0000000F // FIFO tail pointer - -//***************************************************************************** -// -// The following define the bit fields in the ADC_TMLB register. -// -//***************************************************************************** -#define ADC_TMLB_LB 0x00000001 // Loopback control signals - -//***************************************************************************** -// -// The following define the bit fields in the loopback ADC data. -// -//***************************************************************************** -#define ADC_LB_CNT_MASK 0x000003C0 // Sample counter mask -#define ADC_LB_CONT 0x00000020 // Continuation sample -#define ADC_LB_DIFF 0x00000010 // Differential sample -#define ADC_LB_TS 0x00000008 // Temperature sensor sample -#define ADC_LB_MUX_MASK 0x00000007 // Input channel number mask -#define ADC_LB_CNT_SHIFT 6 // Sample counter shift -#define ADC_LB_MUX_SHIFT 0 // Input channel number shift - -#endif // __HW_ADC_H__ diff --git a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_comp.h b/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_comp.h deleted file mode 100644 index 9c5212b00..000000000 --- a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_comp.h +++ /dev/null @@ -1,118 +0,0 @@ -//***************************************************************************** -// -// hw_comp.h - Macros used when accessing the comparator hardware. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 816 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_COMP_H__ -#define __HW_COMP_H__ - -//***************************************************************************** -// -// The following define the offsets of the comparator registers. -// -//***************************************************************************** -#define COMP_O_MIS 0x00000000 // Interrupt status register -#define COMP_O_RIS 0x00000004 // Raw interrupt status register -#define COMP_O_INTEN 0x00000008 // Interrupt enable register -#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg. -#define COMP_O_ACSTAT0 0x00000020 // Comp0 status register -#define COMP_O_ACCTL0 0x00000024 // Comp0 control register -#define COMP_O_ACSTAT1 0x00000040 // Comp1 status register -#define COMP_O_ACCTL1 0x00000044 // Comp1 control register -#define COMP_O_ACSTAT2 0x00000060 // Comp2 status register -#define COMP_O_ACCTL2 0x00000064 // Comp2 control register - -//***************************************************************************** -// -// The following define the bit fields in the COMP_MIS, COMP_RIS, and -// COMP_INTEN registers. -// -//***************************************************************************** -#define COMP_INT_2 0x00000004 // Comp2 interrupt -#define COMP_INT_1 0x00000002 // Comp1 interrupt -#define COMP_INT_0 0x00000001 // Comp0 interrupt - -//***************************************************************************** -// -// The following define the bit fields in the COMP_REFCTL register. -// -//***************************************************************************** -#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable -#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range -#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask -#define COMP_REFCTL_VREF_SHIFT 0 - -//***************************************************************************** -// -// The following define the bit fields in the COMP_ACSTAT0, COMP_ACSTAT1, and -// COMP_ACSTAT2 registers. -// -//***************************************************************************** -#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value - -//***************************************************************************** -// -// The following define the bit fields in the COMP_ACCTL0, COMP_ACCTL1, and -// COMP_ACCTL2 registers. -// -//***************************************************************************** -#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable -#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask -#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin -#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin -#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference -#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved -#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable -#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select -#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask -#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense -#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge -#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge -#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges -#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select -#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask -#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense -#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge -#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge -#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges -#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert - -//***************************************************************************** -// -// The following define the reset values for the comparator registers. -// -//***************************************************************************** -#define COMP_RV_MIS 0x00000000 // Interrupt status register -#define COMP_RV_RIS 0x00000000 // Raw interrupt status register -#define COMP_RV_INTEN 0x00000000 // Interrupt enable register -#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg. -#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register -#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register -#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register -#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register -#define COMP_RV_ACSTAT2 0x00000000 // Comp2 status register -#define COMP_RV_ACCTL2 0x00000000 // Comp2 control register - -#endif // __HW_COMP_H__ diff --git a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_flash.h b/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_flash.h deleted file mode 100644 index d27ebcfbf..000000000 --- a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_flash.h +++ /dev/null @@ -1,139 +0,0 @@ -//***************************************************************************** -// -// hw_flash.h - Macros used when accessing the flash controller. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 816 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_FLASH_H__ -#define __HW_FLASH_H__ - -//***************************************************************************** -// -// The following define the offsets of the FLASH registers. -// -//***************************************************************************** -#define FLASH_FMA 0x400FD000 // Memory address register -#define FLASH_FMD 0x400FD004 // Memory data register -#define FLASH_FMC 0x400FD008 // Memory control register -#define FLASH_FCRIS 0x400FD00c // Raw interrupt status register -#define FLASH_FCIM 0x400FD010 // Interrupt mask register -#define FLASH_FCMISC 0x400FD014 // Interrupt status register -#define FLASH_FMPRE 0x400FE130 // FLASH read protect register -#define FLASH_FMPPE 0x400FE134 // FLASH program protect register -#define FLASH_USECRL 0x400FE140 // uSec reload register - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FMC register. -// -//***************************************************************************** -#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask -#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key -#define FLASH_FMC_COMT 0x00000008 // Commit user register -#define FLASH_FMC_MERASE 0x00000004 // Mass erase FLASH -#define FLASH_FMC_ERASE 0x00000002 // Erase FLASH page -#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FCRIS register. -// -//***************************************************************************** -#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status -#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FCIM register. -// -//***************************************************************************** -#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask -#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FMIS register. -// -//***************************************************************************** -#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status -#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_FMPRE and FLASH_FMPPE -// registers. -// -//***************************************************************************** -#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31 -#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30 -#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29 -#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28 -#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27 -#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26 -#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25 -#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24 -#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23 -#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22 -#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21 -#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20 -#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19 -#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18 -#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17 -#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16 -#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15 -#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14 -#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13 -#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12 -#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11 -#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10 -#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9 -#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8 -#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7 -#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6 -#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5 -#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4 -#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3 -#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2 -#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1 -#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0 - -//***************************************************************************** -// -// The following define the bit fields in the FLASH_USECRL register. -// -//***************************************************************************** -#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec -#define FLASH_USECRL_SHIFT 0 - -//***************************************************************************** -// -// The erase size is the size of the FLASH block that is erased by an erase -// operation, and the protect size is the size of the FLASH block that is -// protected by each protection register. -// -//***************************************************************************** -#define FLASH_ERASE_SIZE 0x00000400 -#define FLASH_PROTECT_SIZE 0x00000800 - -#endif // __HW_FLASH_H__ diff --git a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_gpio.h b/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_gpio.h deleted file mode 100644 index 10bf23b24..000000000 --- a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_gpio.h +++ /dev/null @@ -1,103 +0,0 @@ -//***************************************************************************** -// -// hw_gpio.h - Defines and Macros for GPIO hardware. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 816 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_GPIO_H__ -#define __HW_GPIO_H__ - -//***************************************************************************** -// -// GPIO Register Offsets. -// -//***************************************************************************** -#define GPIO_O_DATA 0x00000000 // Data register. -#define GPIO_O_DIR 0x00000400 // Data direction register. -#define GPIO_O_IS 0x00000404 // Interrupt sense register. -#define GPIO_O_IBE 0x00000408 // Interrupt both edges register. -#define GPIO_O_IEV 0x0000040C // Intterupt event register. -#define GPIO_O_IM 0x00000410 // Interrupt mask register. -#define GPIO_O_RIS 0x00000414 // Raw interrupt status register. -#define GPIO_O_MIS 0x00000418 // Masked interrupt status reg. -#define GPIO_O_ICR 0x0000041C // Interrupt clear register. -#define GPIO_O_AFSEL 0x00000420 // Mode control select register. -#define GPIO_O_DR2R 0x00000500 // 2ma drive select register. -#define GPIO_O_DR4R 0x00000504 // 4ma drive select register. -#define GPIO_O_DR8R 0x00000508 // 8ma drive select register. -#define GPIO_O_ODR 0x0000050C // Open drain select register. -#define GPIO_O_PUR 0x00000510 // Pull up select register. -#define GPIO_O_PDR 0x00000514 // Pull down select register. -#define GPIO_O_SLR 0x00000518 // Slew rate control enable reg. -#define GPIO_O_DEN 0x0000051C // Digital input enable register. -#define GPIO_O_PeriphID4 0x00000FD0 // -#define GPIO_O_PeriphID5 0x00000FD4 // -#define GPIO_O_PeriphID6 0x00000FD8 // -#define GPIO_O_PeriphID7 0x00000FDC // -#define GPIO_O_PeriphID0 0x00000FE0 // -#define GPIO_O_PeriphID1 0x00000FE4 // -#define GPIO_O_PeriphID2 0x00000FE8 // -#define GPIO_O_PeriphID3 0x00000FEC // -#define GPIO_O_PCellID0 0x00000FF0 // -#define GPIO_O_PCellID1 0x00000FF4 // -#define GPIO_O_PCellID2 0x00000FF8 // -#define GPIO_O_PCellID3 0x00000FFC // - -//***************************************************************************** -// -// GPIO Register reset values. -// -//***************************************************************************** -#define GPIO_RV_DATA 0x00000000 // Data register reset value. -#define GPIO_RV_DIR 0x00000000 // Data direction reg RV. -#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV. -#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV. -#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV. -#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV. -#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV. -#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV. -#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV. -#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV. -#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV. -#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV. -#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV. -#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV. -#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV. -#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV. -#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV. -#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV. -#define GPIO_RV_PeriphID4 0x00000000 // -#define GPIO_RV_PeriphID5 0x00000000 // -#define GPIO_RV_PeriphID6 0x00000000 // -#define GPIO_RV_PeriphID7 0x00000000 // -#define GPIO_RV_PeriphID0 0x00000061 // -#define GPIO_RV_PeriphID1 0x00000010 // -#define GPIO_RV_PeriphID2 0x00000004 // -#define GPIO_RV_PeriphID3 0x00000000 // -#define GPIO_RV_PCellID0 0x0000000D // -#define GPIO_RV_PCellID1 0x000000F0 // -#define GPIO_RV_PCellID2 0x00000005 // -#define GPIO_RV_PCellID3 0x000000B1 // - -#endif // __HW_GPIO_H__ diff --git a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_i2c.h b/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_i2c.h deleted file mode 100644 index 2a3900c59..000000000 --- a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_i2c.h +++ /dev/null @@ -1,197 +0,0 @@ -//***************************************************************************** -// -// hw_i2c.h - Macros used when accessing the I2C master and slave hardware. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 816 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_I2C_H__ -#define __HW_I2C_H__ - -//***************************************************************************** -// -// The following defines the offset between the I2C master and slave registers. -// -//***************************************************************************** -#define I2C_O_SLAVE 0x00000800 // Offset from master to slave - -//***************************************************************************** -// -// The following define the offsets of the I2C master registers. -// -//***************************************************************************** -#define I2C_MASTER_O_SA 0x00000000 // Slave address register -#define I2C_MASTER_O_CS 0x00000004 // Control and Status register -#define I2C_MASTER_O_DR 0x00000008 // Data register -#define I2C_MASTER_O_TPR 0x0000000C // Timer period register -#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register -#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register -#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg -#define I2C_MASTER_O_MICR 0x0000001c // Interrupt clear register -#define I2C_MASTER_O_CR 0x00000020 // Configuration register - -//***************************************************************************** -// -// The following define the offsets of the I2C slave registers. -// -//***************************************************************************** -#define I2C_SLAVE_O_OAR 0x00000000 // Own address register -#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register -#define I2C_SLAVE_O_DR 0x00000008 // Data register -#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register -#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register -#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg -#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register - -//***************************************************************************** -// -// The followng define the bit fields in the I2C master slave address register. -// -//***************************************************************************** -#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address -#define I2C_MASTER_SA_RS 0x00000001 // Receive/send -#define I2C_MASTER_SA_SA_SHIFT 1 - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Control and Status -// register. -// -//***************************************************************************** -#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde -#define I2C_MASTER_CS_STOP 0x00000004 // Stop -#define I2C_MASTER_CS_START 0x00000002 // Start -#define I2C_MASTER_CS_RUN 0x00000001 // Run -#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy -#define I2C_MASTER_CS_IDLE 0x00000020 // Idle -#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration -#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged -#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged -#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred -#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data -#define I2C_MASTER_CS_ERR_MASK 0x0000001C - -//***************************************************************************** -// -// The following define values used in determining the contents of the I2C -// Master Timer Period register. -// -//***************************************************************************** -#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period -#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period -#define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP) -#define I2C_SCL_STANDARD 100000 // SCL standard frequency -#define I2C_SCL_FAST 400000 // SCL fast frequency - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Interrupt Mask -// register. -// -//***************************************************************************** -#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Raw Interrupt Status -// register. -// -//***************************************************************************** -#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Masked Interrupt -// Status register. -// -//***************************************************************************** -#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Interrupt Clear -// register. -// -//***************************************************************************** -#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear - -//***************************************************************************** -// -// The following define the bit fields in the I2C Master Configuration -// register. -// -//***************************************************************************** -#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable -#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable -#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Own Address register. -// -//***************************************************************************** -#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Control/Status -// register. -// -//***************************************************************************** -#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device -#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received -#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Interrupt Mask -// register. -// -//***************************************************************************** -#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Raw Interrupt Status -// register. -// -//***************************************************************************** -#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Masked Interrupt -// Status register. -// -//***************************************************************************** -#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status - -//***************************************************************************** -// -// The following define the bit fields in the I2C Slave Interrupt Clear -// register. -// -//***************************************************************************** -#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear - -#endif // __HW_I2C_H__ diff --git a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_ints.h b/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_ints.h deleted file mode 100644 index 820d5cdff..000000000 --- a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_ints.h +++ /dev/null @@ -1,97 +0,0 @@ -//***************************************************************************** -// -// hw_ints.h - Macros that define the interrupt assignment on Stellaris. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 816 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_INTS_H__ -#define __HW_INTS_H__ - -//***************************************************************************** -// -// The following define the fault assignments. -// -//***************************************************************************** -#define FAULT_NMI 2 // NMI fault -#define FAULT_HARD 3 // Hard fault -#define FAULT_MPU 4 // MPU fault -#define FAULT_BUS 5 // Bus fault -#define FAULT_USAGE 6 // Usage fault -#define FAULT_SVCALL 11 // SVCall -#define FAULT_DEBUG 12 // Debug monitor -#define FAULT_PENDSV 14 // PendSV -#define FAULT_SYSTICK 15 // System Tick - -//***************************************************************************** -// -// The following define the interrupt assignments. -// -//***************************************************************************** -#define INT_GPIOA 16 // GPIO Port A -#define INT_GPIOB 17 // GPIO Port B -#define INT_GPIOC 18 // GPIO Port C -#define INT_GPIOD 19 // GPIO Port D -#define INT_GPIOE 20 // GPIO Port E -#define INT_UART0 21 // UART0 Rx and Tx -#define INT_UART1 22 // UART1 Rx and Tx -#define INT_SSI 23 // SSI Rx and Tx -#define INT_I2C 24 // I2C Master and Slave -#define INT_PWM_FAULT 25 // PWM Fault -#define INT_PWM0 26 // PWM Generator 0 -#define INT_PWM1 27 // PWM Generator 1 -#define INT_PWM2 28 // PWM Generator 2 -#define INT_QEI 29 // Quadrature Encoder -#define INT_ADC0 30 // ADC Sequence 0 -#define INT_ADC1 31 // ADC Sequence 1 -#define INT_ADC2 32 // ADC Sequence 2 -#define INT_ADC3 33 // ADC Sequence 3 -#define INT_WATCHDOG 34 // Watchdog timer -#define INT_TIMER0A 35 // Timer 0 subtimer A -#define INT_TIMER0B 36 // Timer 0 subtimer B -#define INT_TIMER1A 37 // Timer 1 subtimer A -#define INT_TIMER1B 38 // Timer 1 subtimer B -#define INT_TIMER2A 39 // Timer 2 subtimer A -#define INT_TIMER2B 40 // Timer 2 subtimer B -#define INT_COMP0 41 // Analog Comparator 0 -#define INT_COMP1 42 // Analog Comparator 1 -#define INT_COMP2 43 // Analog Comparator 2 -#define INT_SYSCTL 44 // System Control (PLL, OSC, BO) -#define INT_FLASH 45 // FLASH Control - -//***************************************************************************** -// -// The total number of interrupts. -// -//***************************************************************************** -#define NUM_INTERRUPTS 46 - -//***************************************************************************** -// -// The total number of priority levels. -// -//***************************************************************************** -#define NUM_PRIORITY 8 -#define NUM_PRIORITY_BITS 3 - -#endif // __HW_INTS_H__ diff --git a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_memmap.h b/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_memmap.h deleted file mode 100644 index 4340d63d1..000000000 --- a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_memmap.h +++ /dev/null @@ -1,64 +0,0 @@ -//***************************************************************************** -// -// hw_memmap.h - Macros defining the memory map of Stellaris. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 816 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_MEMMAP_H__ -#define __HW_MEMMAP_H__ - -//***************************************************************************** -// -// The following define the base address of the memories and peripherals. -// -//***************************************************************************** -#define FLASH_BASE 0x00000000 // FLASH memory -#define SRAM_BASE 0x20000000 // SRAM memory -#define WATCHDOG_BASE 0x40000000 // Watchdog -#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A -#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B -#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C -#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D -#define SSI_BASE 0x40008000 // SSI -#define UART0_BASE 0x4000C000 // UART0 -#define UART1_BASE 0x4000D000 // UART1 -#define I2C_MASTER_BASE 0x40020000 // I2C Master -#define I2C_SLAVE_BASE 0x40020800 // I2C Slave -#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E -#define PWM_BASE 0x40028000 // PWM -#define QEI_BASE 0x4002C000 // QEI -#define TIMER0_BASE 0x40030000 // Timer0 -#define TIMER1_BASE 0x40031000 // Timer1 -#define TIMER2_BASE 0x40032000 // Timer2 -#define ADC_BASE 0x40038000 // ADC -#define COMP_BASE 0x4003C000 // Analog comparators -#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller -#define SYSCTL_BASE 0x400FE000 // System Control -#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell -#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace -#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint -#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl -#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit - -#endif // __HW_MEMMAP_H__ diff --git a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_nvic.h b/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_nvic.h deleted file mode 100644 index 692af25df..000000000 --- a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_nvic.h +++ /dev/null @@ -1,830 +0,0 @@ -//***************************************************************************** -// -// hw_nvic.h - Macros used when accessing the NVIC hardware. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 816 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_NVIC_H__ -#define __HW_NVIC_H__ - -//***************************************************************************** -// -// The following define the addresses of the NVIC registers. -// -//***************************************************************************** -#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg. -#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg. -#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register -#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register -#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg. -#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register -#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg. -#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register -#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg. -#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register -#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register -#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register -#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register -#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register -#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register -#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register -#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register -#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register -#define NVIC_CPUID 0xE000ED00 // CPUID Base Register -#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register -#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register -#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg. -#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register -#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register -#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority -#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority -#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority -#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State -#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg. -#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register -#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register -#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register -#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register -#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register -#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register -#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register -#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register -#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg. -#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg. -#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select -#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data -#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control -#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg. - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_INT_TYPE register. -// -//***************************************************************************** -#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) -#define NVIC_INT_TYPE_LINES_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_CTRL register. -// -//***************************************************************************** -#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag -#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source -#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable -#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_RELOAD register. -// -//***************************************************************************** -#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value -#define NVIC_ST_RELOAD_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_CURRENT register. -// -//***************************************************************************** -#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value -#define NVIC_ST_CURRENT_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ST_CAL register. -// -//***************************************************************************** -#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock -#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew -#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value -#define NVIC_ST_CAL_ONEMS_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_EN0 register. -// -//***************************************************************************** -#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable -#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable -#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable -#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable -#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable -#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable -#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable -#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable -#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable -#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable -#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable -#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable -#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable -#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable -#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable -#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable -#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable -#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable -#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable -#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable -#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable -#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable -#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable -#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable -#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable -#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable -#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable -#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable -#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable -#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable -#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable -#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DIS0 register. -// -//***************************************************************************** -#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable -#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable -#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable -#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable -#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable -#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable -#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable -#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable -#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable -#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable -#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable -#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable -#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable -#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable -#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable -#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable -#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable -#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable -#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable -#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable -#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable -#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable -#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable -#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable -#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable -#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable -#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable -#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable -#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable -#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable -#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable -#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PEND0 register. -// -//***************************************************************************** -#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend -#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend -#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend -#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend -#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend -#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend -#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend -#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend -#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend -#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend -#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend -#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend -#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend -#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend -#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend -#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend -#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend -#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend -#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend -#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend -#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend -#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend -#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend -#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend -#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend -#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend -#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend -#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend -#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend -#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend -#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend -#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_UNPEND0 register. -// -//***************************************************************************** -#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend -#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend -#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend -#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend -#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend -#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend -#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend -#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend -#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend -#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend -#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend -#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend -#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend -#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend -#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend -#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend -#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend -#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend -#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend -#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend -#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend -#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend -#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend -#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend -#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend -#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend -#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend -#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend -#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend -#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend -#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend -#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_ACTIVE0 register. -// -//***************************************************************************** -#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active -#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active -#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active -#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active -#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active -#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active -#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active -#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active -#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active -#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active -#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active -#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active -#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active -#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active -#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active -#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active -#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active -#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active -#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active -#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active -#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active -#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active -#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active -#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active -#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active -#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active -#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active -#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active -#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active -#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active -#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active -#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI0 register. -// -//***************************************************************************** -#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask -#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask -#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask -#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask -#define NVIC_PRI0_INT3_S 24 -#define NVIC_PRI0_INT2_S 16 -#define NVIC_PRI0_INT1_S 8 -#define NVIC_PRI0_INT0_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI1 register. -// -//***************************************************************************** -#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask -#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask -#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask -#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask -#define NVIC_PRI1_INT7_S 24 -#define NVIC_PRI1_INT6_S 16 -#define NVIC_PRI1_INT5_S 8 -#define NVIC_PRI1_INT4_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI2 register. -// -//***************************************************************************** -#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask -#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask -#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask -#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask -#define NVIC_PRI2_INT11_S 24 -#define NVIC_PRI2_INT10_S 16 -#define NVIC_PRI2_INT9_S 8 -#define NVIC_PRI2_INT8_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI3 register. -// -//***************************************************************************** -#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask -#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask -#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask -#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask -#define NVIC_PRI3_INT15_S 24 -#define NVIC_PRI3_INT14_S 16 -#define NVIC_PRI3_INT13_S 8 -#define NVIC_PRI3_INT12_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI4 register. -// -//***************************************************************************** -#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask -#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask -#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask -#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask -#define NVIC_PRI4_INT19_S 24 -#define NVIC_PRI4_INT18_S 16 -#define NVIC_PRI4_INT17_S 8 -#define NVIC_PRI4_INT16_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI5 register. -// -//***************************************************************************** -#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask -#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask -#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask -#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask -#define NVIC_PRI5_INT23_S 24 -#define NVIC_PRI5_INT22_S 16 -#define NVIC_PRI5_INT21_S 8 -#define NVIC_PRI5_INT20_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI6 register. -// -//***************************************************************************** -#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask -#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask -#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask -#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask -#define NVIC_PRI6_INT27_S 24 -#define NVIC_PRI6_INT26_S 16 -#define NVIC_PRI6_INT25_S 8 -#define NVIC_PRI6_INT24_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_PRI7 register. -// -//***************************************************************************** -#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask -#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask -#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask -#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask -#define NVIC_PRI7_INT31_S 24 -#define NVIC_PRI7_INT30_S 16 -#define NVIC_PRI7_INT29_S 8 -#define NVIC_PRI7_INT28_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_CPUID register. -// -//***************************************************************************** -#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer -#define NVIC_CPUID_VAR_M 0x00F00000 // Variant -#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number -#define NVIC_CPUID_REV_M 0x0000000F // Revision - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_INT_CTRL register. -// -//***************************************************************************** -#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI -#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV -#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV -#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling -#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending -#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception -#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base -#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception -#define NVIC_INT_CTRL_VEC_PEN_S 12 -#define NVIC_INT_CTRL_VEC_ACT_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_VTABLE register. -// -//***************************************************************************** -#define NVIC_VTABLE_BASE 0x20000000 // Vector table base -#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset -#define NVIC_VTABLE_OFFSET_S 8 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_APINT register. -// -//***************************************************************************** -#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask -#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key -#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess -#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group -#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split -#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split -#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split -#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split -#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split -#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split -#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split -#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split -#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request -#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info -#define NVIC_APINT_VECT_RESET 0x00000001 // System reset - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_CTRL register. -// -//***************************************************************************** -#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend -#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable -#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_CFG_CTRL register. -// -//***************************************************************************** -#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault -#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0 -#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access -#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger -#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger -#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_PRI1 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler -#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler -#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler -#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler -#define NVIC_SYS_PRI1_USAGE_S 16 -#define NVIC_SYS_PRI1_BUS_S 8 -#define NVIC_SYS_PRI1_MEM_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_PRI2 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler -#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers -#define NVIC_SYS_PRI2_SVC_S 24 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_PRI3 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler -#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler -#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler -#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler -#define NVIC_SYS_PRI3_TICK_S 24 -#define NVIC_SYS_PRI3_PENDSV_S 16 -#define NVIC_SYS_PRI3_DEBUG_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SYS_HND_CTRL register. -// -//***************************************************************************** -#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable -#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable -#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable -#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended -#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended -#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active -#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active -#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active -#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active -#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active -#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active -#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_FAULT_STAT register. -// -//***************************************************************************** -#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault -#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault -#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault -#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault -#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault -#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault -#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid -#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault -#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault -#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error -#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error -#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault -#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid -#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation -#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation -#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation -#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_HFAULT_STAT register. -// -//***************************************************************************** -#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event -#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler -#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DEBUG_STAT register. -// -//***************************************************************************** -#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted -#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch -#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match -#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction -#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MM_ADDR register. -// -//***************************************************************************** -#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address -#define NVIC_MM_ADDR_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_FAULT_ADDR register. -// -//***************************************************************************** -#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address -#define NVIC_FAULT_ADDR_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_EXC_STACK register. -// -//***************************************************************************** -#define NVIC_EXC_STACK_DEEP 0x00000001 // Exception stack - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_EXC_NUM register. -// -//***************************************************************************** -#define NVIC_EXC_NUM_M 0x000003FF // Exception number -#define NVIC_EXC_NUM_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_COPRO register. -// -//***************************************************************************** -#define NVIC_COPRO_15_M 0xC0000000 // Coprocessor 15 access mask -#define NVIC_COPRO_15_DENIED 0x00000000 // Coprocessor 15 access denied -#define NVIC_COPRO_15_PRIV 0x40000000 // Coprocessor 15 privileged addess -#define NVIC_COPRO_15_FULL 0xC0000000 // Coprocessor 15 full access -#define NVIC_COPRO_14_M 0x30000000 // Coprocessor 14 access mask -#define NVIC_COPRO_14_DENIED 0x00000000 // Coprocessor 14 access denied -#define NVIC_COPRO_14_PRIV 0x10000000 // Coprocessor 14 privileged addess -#define NVIC_COPRO_14_FULL 0x30000000 // Coprocessor 14 full access -#define NVIC_COPRO_13_M 0x0C000000 // Coprocessor 13 access mask -#define NVIC_COPRO_13_DENIED 0x00000000 // Coprocessor 13 access denied -#define NVIC_COPRO_13_PRIV 0x04000000 // Coprocessor 13 privileged addess -#define NVIC_COPRO_13_FULL 0x0C000000 // Coprocessor 13 full access -#define NVIC_COPRO_12_M 0x03000000 // Coprocessor 12 access mask -#define NVIC_COPRO_12_DENIED 0x00000000 // Coprocessor 12 access denied -#define NVIC_COPRO_12_PRIV 0x01000000 // Coprocessor 12 privileged addess -#define NVIC_COPRO_12_FULL 0x03000000 // Coprocessor 12 full access -#define NVIC_COPRO_11_M 0x00C00000 // Coprocessor 11 access mask -#define NVIC_COPRO_11_DENIED 0x00000000 // Coprocessor 11 access denied -#define NVIC_COPRO_11_PRIV 0x00400000 // Coprocessor 11 privileged addess -#define NVIC_COPRO_11_FULL 0x00C00000 // Coprocessor 11 full access -#define NVIC_COPRO_10_M 0x00300000 // Coprocessor 10 access mask -#define NVIC_COPRO_10_DENIED 0x00000000 // Coprocessor 10 access denied -#define NVIC_COPRO_10_PRIV 0x00100000 // Coprocessor 10 privileged addess -#define NVIC_COPRO_10_FULL 0x00300000 // Coprocessor 10 full access -#define NVIC_COPRO_9_M 0x000C0000 // Coprocessor 9 access mask -#define NVIC_COPRO_9_DENIED 0x00000000 // Coprocessor 9 access denied -#define NVIC_COPRO_9_PRIV 0x00040000 // Coprocessor 9 privileged addess -#define NVIC_COPRO_9_FULL 0x000C0000 // Coprocessor 9 full access -#define NVIC_COPRO_8_M 0x00030000 // Coprocessor 8 access mask -#define NVIC_COPRO_8_DENIED 0x00000000 // Coprocessor 8 access denied -#define NVIC_COPRO_8_PRIV 0x00010000 // Coprocessor 8 privileged addess -#define NVIC_COPRO_8_FULL 0x00030000 // Coprocessor 8 full access -#define NVIC_COPRO_7_M 0x0000C000 // Coprocessor 7 access mask -#define NVIC_COPRO_7_DENIED 0x00000000 // Coprocessor 7 access denied -#define NVIC_COPRO_7_PRIV 0x00004000 // Coprocessor 7 privileged addess -#define NVIC_COPRO_7_FULL 0x0000C000 // Coprocessor 7 full access -#define NVIC_COPRO_6_M 0x00003000 // Coprocessor 6 access mask -#define NVIC_COPRO_6_DENIED 0x00000000 // Coprocessor 6 access denied -#define NVIC_COPRO_6_PRIV 0x00001000 // Coprocessor 6 privileged addess -#define NVIC_COPRO_6_FULL 0x00003000 // Coprocessor 6 full access -#define NVIC_COPRO_5_M 0x00000C00 // Coprocessor 5 access mask -#define NVIC_COPRO_5_DENIED 0x00000000 // Coprocessor 5 access denied -#define NVIC_COPRO_5_PRIV 0x00000400 // Coprocessor 5 privileged addess -#define NVIC_COPRO_5_FULL 0x00000C00 // Coprocessor 5 full access -#define NVIC_COPRO_4_M 0x00000300 // Coprocessor 4 access mask -#define NVIC_COPRO_4_DENIED 0x00000000 // Coprocessor 4 access denied -#define NVIC_COPRO_4_PRIV 0x00000100 // Coprocessor 4 privileged addess -#define NVIC_COPRO_4_FULL 0x00000300 // Coprocessor 4 full access -#define NVIC_COPRO_3_M 0x000000C0 // Coprocessor 3 access mask -#define NVIC_COPRO_3_DENIED 0x00000000 // Coprocessor 3 access denied -#define NVIC_COPRO_3_PRIV 0x00000040 // Coprocessor 3 privileged addess -#define NVIC_COPRO_3_FULL 0x000000C0 // Coprocessor 3 full access -#define NVIC_COPRO_2_M 0x00000030 // Coprocessor 2 access mask -#define NVIC_COPRO_2_DENIED 0x00000000 // Coprocessor 2 access denied -#define NVIC_COPRO_2_PRIV 0x00000010 // Coprocessor 2 privileged addess -#define NVIC_COPRO_2_FULL 0x00000030 // Coprocessor 2 full access -#define NVIC_COPRO_1_M 0x0000000C // Coprocessor 1 access mask -#define NVIC_COPRO_1_DENIED 0x00000000 // Coprocessor 1 access denied -#define NVIC_COPRO_1_PRIV 0x00000004 // Coprocessor 1 privileged addess -#define NVIC_COPRO_1_FULL 0x0000000C // Coprocessor 1 full access -#define NVIC_COPRO_0_M 0x00000003 // Coprocessor 0 access mask -#define NVIC_COPRO_0_DENIED 0x00000000 // Coprocessor 0 access denied -#define NVIC_COPRO_0_PRIV 0x00000001 // Coprocessor 0 privileged addess -#define NVIC_COPRO_0_FULL 0x00000003 // Coprocessor 0 full access - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_TYPE register. -// -//***************************************************************************** -#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions -#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions -#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU -#define NVIC_MPU_TYPE_IREGION_S 16 -#define NVIC_MPU_TYPE_DREGION_S 8 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_CTRL register. -// -//***************************************************************************** -#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults -#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_NUMBER register. -// -//***************************************************************************** -#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access -#define NVIC_MPU_NUMBER_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_BASE register. -// -//***************************************************************************** -#define NVIC_MPU_BASE_ADDR_M 0xFFFFFF00 // Base address -#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid -#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number -#define NVIC_MPU_BASE_ADDR_S 8 -#define NVIC_MPU_BASE_REGION_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_MPU_ATTR register. -// -//***************************************************************************** -#define NVIC_MPU_ATTR_ATTRS 0xFFFF0000 // Attributes -#define NVIC_MPU_ATTR_SRD 0x0000FF00 // Sub-region disable -#define NVIC_MPU_ATTR_SZENABLE 0x000000FF // Region size - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_CTRL register. -// -//***************************************************************************** -#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask -#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key -#define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor -#define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request -#define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable -#define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core -#define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping -#define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt -#define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available -#define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up -#define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core -#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping -#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core -#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core -#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_XFER register. -// -//***************************************************************************** -#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read -#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register -#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 -#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 -#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 -#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 -#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 -#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 -#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 -#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 -#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 -#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 -#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 -#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 -#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 -#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 -#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 -#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 -#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register -#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP -#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP -#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP -#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_DATA register. -// -//***************************************************************************** -#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache -#define NVIC_DBG_DATA_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_DBG_INT register. -// -//***************************************************************************** -#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault -#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors -#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error -#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state -#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check -#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error -#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault -#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status -#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset -#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending -#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch - -//***************************************************************************** -// -// The following define the bit fields in the NVIC_SW_TRIG register. -// -//***************************************************************************** -#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger -#define NVIC_SW_TRIG_INTID_S 0 - -#endif // __HW_NVIC_H__ diff --git a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_pwm.h b/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_pwm.h deleted file mode 100644 index a324eaa90..000000000 --- a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_pwm.h +++ /dev/null @@ -1,260 +0,0 @@ -//***************************************************************************** -// -// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 816 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_PWM_H__ -#define __HW_PWM_H__ - -//***************************************************************************** -// -// PWM Module Register Offsets. -// -//***************************************************************************** -#define PWM_O_CTL 0x00000000 // PWM Master Control register -#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync register -#define PWM_O_ENABLE 0x00000008 // PWM Output Enable register -#define PWM_O_INVERT 0x0000000C // PWM Output Inversion register -#define PWM_O_FAULT 0x00000010 // PWM Output Fault register -#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable register -#define PWM_O_RIS 0x00000018 // PWM Interrupt Raw Status reg. -#define PWM_O_ISC 0x0000001C // PWM Interrupt Status register -#define PWM_O_STATUS 0x00000020 // PWM Status register - -//***************************************************************************** -// -// The following define the bit fields in the PWM Master Control register. -// -//***************************************************************************** -#define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2 -#define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1 -#define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0 - -//***************************************************************************** -// -// The following define the bit fields in the PWM Time Base Sync register. -// -//***************************************************************************** -#define PWM_SYNC_SYNC2 0x00000004 // Reset generator 2 counter -#define PWM_SYNC_SYNC1 0x00000002 // Reset generator 1 counter -#define PWM_SYNC_SYNC0 0x00000001 // Reset generator 0 counter - -//***************************************************************************** -// -// The following define the bit fields in the PWM Output Enable register. -// -//***************************************************************************** -#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 pin enable -#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 pin enable -#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 pin enable -#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 pin enable -#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 pin enable -#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 pin enable - -//***************************************************************************** -// -// The following define the bit fields in the PWM Inversion register. -// -//***************************************************************************** -#define PWM_INVERT_PWM5INV 0x00000020 // PWM5 pin invert -#define PWM_INVERT_PWM4INV 0x00000010 // PWM4 pin invert -#define PWM_INVERT_PWM3INV 0x00000008 // PWM3 pin invert -#define PWM_INVERT_PWM2INV 0x00000004 // PWM2 pin invert -#define PWM_INVERT_PWM1INV 0x00000002 // PWM1 pin invert -#define PWM_INVERT_PWM0INV 0x00000001 // PWM0 pin invert - -//***************************************************************************** -// -// The following define the bit fields in the PWM Fault register. -// -//***************************************************************************** -#define PWM_FAULT_FAULT5 0x00000020 // PWM5 pin fault -#define PWM_FAULT_FAULT4 0x00000010 // PWM5 pin fault -#define PWM_FAULT_FAULT3 0x00000008 // PWM5 pin fault -#define PWM_FAULT_FAULT2 0x00000004 // PWM5 pin fault -#define PWM_FAULT_FAULT1 0x00000002 // PWM5 pin fault -#define PWM_FAULT_FAULT0 0x00000001 // PWM5 pin fault - -//***************************************************************************** -// -// PWM Interrupt Register bit definitions. -// -//***************************************************************************** -#define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending - -//***************************************************************************** -// -// The following define the bit fields in the PWM Status register. -// -//***************************************************************************** -#define PWM_STATUS_FAULT 0x00000001 // Fault status - -//***************************************************************************** -// -// PWM Generator standard offsets. -// -//***************************************************************************** -#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base -#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base -#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base - -#define PWM_O_X_CTL 0x00000000 // Gen Control Reg -#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg -#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg -#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg -#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg -#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg -#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg -#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg -#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg -#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg -#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg -#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg -#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg - -//***************************************************************************** -// -// PWM_X Control Register bit definitions. -// -//***************************************************************************** -#define PWM_X_CTL_ENABLE 0x00000001 // Master enable for gen block -#define PWM_X_CTL_MODE 0x00000002 // Counter mode, down or up/down -#define PWM_X_CTL_DEBUG 0x00000004 // Debug mode -#define PWM_X_CTL_LOADUPD 0x00000008 // Update mode for the load reg -#define PWM_X_CTL_CMPAUPD 0x00000010 // Update mode for comp A reg -#define PWM_X_CTL_CMPBUPD 0x00000020 // Update mode for comp B reg - -//***************************************************************************** -// -// PWM_X Interrupt/Trigger Enable Register bit definitions. -// -//***************************************************************************** -#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Int if COUNT = 0 -#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Int if COUNT = LOAD -#define PWM_X_INTEN_INTCMPAU 0x00000004 // Int if COUNT = CMPA U -#define PWM_X_INTEN_INTCMPAD 0x00000008 // Int if COUNT = CMPA D -#define PWM_X_INTEN_INTCMPBU 0x00000010 // Int if COUNT = CMPA U -#define PWM_X_INTEN_INTCMPBD 0x00000020 // Int if COUNT = CMPA D -#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trig if COUNT = 0 -#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trig if COUNT = LOAD -#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trig if COUNT = CMPA U -#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trig if COUNT = CMPA D -#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trig if COUNT = CMPA U -#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trig if COUNT = CMPA D - -//***************************************************************************** -// -// PWM_X Raw Interrupt Status Register bit definitions. -// -//***************************************************************************** -#define PWM_X_RIS_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 int -#define PWM_X_RIS_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD int -#define PWM_X_RIS_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U int -#define PWM_X_RIS_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D int -#define PWM_X_RIS_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U int -#define PWM_X_RIS_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D int - -//***************************************************************************** -// -// PWM_X Interrupt Status Register bit definitions. -// -//***************************************************************************** -#define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received -#define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd -#define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd -#define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd -#define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd -#define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd - -//***************************************************************************** -// -// PWM_X Generator A/B Control Register bit definitions. -// -//***************************************************************************** -#define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0 -#define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD -#define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U -#define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D -#define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U -#define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D - -//***************************************************************************** -// -// PWM_X Generator A/B Control Register action definitions. -// -//***************************************************************************** -#define PWM_GEN_ACT_NONE 0x0 // Do nothing -#define PWM_GEN_ACT_INV 0x1 // Invert the output signal -#define PWM_GEN_ACT_ZERO 0x2 // Set the output signal to zero -#define PWM_GEN_ACT_ONE 0x3 // Set the output signal to one -#define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action -#define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action -#define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action -#define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action -#define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action -#define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action - -//***************************************************************************** -// -// PWM_X Dead Band Control Register bit definitions. -// -//***************************************************************************** -#define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion - -//***************************************************************************** -// -// PWM Register reset values. -// -//***************************************************************************** -#define PWM_RV_CTL 0x00000000 // Master control of the PWM module -#define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators -#define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM - // output pins -#define PWM_RV_INVERT 0x00000000 // Inversion control for - // PWM output pins -#define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM - // output pins -#define PWM_RV_INTEN 0x00000000 // Interrupt enable -#define PWM_RV_RIS 0x00000000 // Raw interrupt status -#define PWM_RV_ISC 0x00000000 // Interrupt status and clearing -#define PWM_RV_STATUS 0x00000000 // Status -#define PWM_RV_X_CTL 0x00000000 // Master control of the PWM - // generator block -#define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable -#define PWM_RV_X_RIS 0x00000000 // Raw interrupt status -#define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing -#define PWM_RV_X_LOAD 0x00000000 // The load value for the counter -#define PWM_RV_X_COUNT 0x00000000 // The current counter value -#define PWM_RV_X_CMPA 0x00000000 // The comparator A value -#define PWM_RV_X_CMPB 0x00000000 // The comparator B value -#define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A -#define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B -#define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator -#define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay - // count -#define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay - // count - -#endif // __HW_PWM_H__ diff --git a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_qei.h b/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_qei.h deleted file mode 100644 index 64ebcd18e..000000000 --- a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_qei.h +++ /dev/null @@ -1,176 +0,0 @@ -//***************************************************************************** -// -// hw_qei.h - Macros used when accessing the QEI hardware. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 816 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_QEI_H__ -#define __HW_QEI_H__ - -//***************************************************************************** -// -// The following define the offsets of the QEI registers. -// -//***************************************************************************** -#define QEI_O_CTL 0x00000000 // Configuration and control reg. -#define QEI_O_STAT 0x00000004 // Status register -#define QEI_O_POS 0x00000008 // Current position register -#define QEI_O_MAXPOS 0x0000000C // Maximum position register -#define QEI_O_LOAD 0x00000010 // Velocity timer load register -#define QEI_O_TIME 0x00000014 // Velocity timer register -#define QEI_O_COUNT 0x00000018 // Velocity pulse count register -#define QEI_O_SPEED 0x0000001C // Velocity speed register -#define QEI_O_INTEN 0x00000020 // Interrupt enable register -#define QEI_O_RIS 0x00000024 // Raw interrupt status register -#define QEI_O_ISC 0x00000028 // Interrupt status register - -//***************************************************************************** -// -// The following define the bit fields in the QEI_CTL register. -// -//***************************************************************************** -#define QEI_CTL_STALLEN 0x00001000 // Stall enable -#define QEI_CTL_INVI 0x00000800 // Invert Index input -#define QEI_CTL_INVB 0x00000400 // Invert PhB input -#define QEI_CTL_INVA 0x00000200 // Invert PhA input -#define QEI_CTL_VELDIV_M 0x000001C0 // Velocity predivider mask -#define QEI_CTL_VELDIV_1 0x00000000 // Predivide by 1 -#define QEI_CTL_VELDIV_2 0x00000040 // Predivide by 2 -#define QEI_CTL_VELDIV_4 0x00000080 // Predivide by 4 -#define QEI_CTL_VELDIV_8 0x000000C0 // Predivide by 8 -#define QEI_CTL_VELDIV_16 0x00000100 // Predivide by 16 -#define QEI_CTL_VELDIV_32 0x00000140 // Predivide by 32 -#define QEI_CTL_VELDIV_64 0x00000180 // Predivide by 64 -#define QEI_CTL_VELDIV_128 0x000001C0 // Predivide by 128 -#define QEI_CTL_VELEN 0x00000020 // Velocity enable -#define QEI_CTL_RESMODE 0x00000010 // Position counter reset mode -#define QEI_CTL_CAPMODE 0x00000008 // Edge capture mode -#define QEI_CTL_SIGMODE 0x00000004 // Encoder signaling mode -#define QEI_CTL_SWAP 0x00000002 // Swap input signals -#define QEI_CTL_ENABLE 0x00000001 // QEI enable - -//***************************************************************************** -// -// The following define the bit fields in the QEI_STAT register. -// -//***************************************************************************** -#define QEI_STAT_DIRECTION 0x00000002 // Direction of rotation -#define QEI_STAT_ERROR 0x00000001 // Signalling error detected - -//***************************************************************************** -// -// The following define the bit fields in the QEI_POS register. -// -//***************************************************************************** -#define QEI_POS_M 0xFFFFFFFF // Current encoder position -#define QEI_POS_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_MAXPOS register. -// -//***************************************************************************** -#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum encoder position -#define QEI_MAXPOS_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_LOAD register. -// -//***************************************************************************** -#define QEI_LOAD_M 0xFFFFFFFF // Velocity timer load value -#define QEI_LOAD_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_TIME register. -// -//***************************************************************************** -#define QEI_TIME_M 0xFFFFFFFF // Velocity timer current value -#define QEI_TIME_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_COUNT register. -// -//***************************************************************************** -#define QEI_COUNT_M 0xFFFFFFFF // Encoder running pulse count -#define QEI_COUNT_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_SPEED register. -// -//***************************************************************************** -#define QEI_SPEED_M 0xFFFFFFFF // Encoder pulse count -#define QEI_SPEED_S 0 - -//***************************************************************************** -// -// The following define the bit fields in the QEI_INTEN register. -// -//***************************************************************************** -#define QEI_INTEN_ERROR 0x00000008 // Phase error detected -#define QEI_INTEN_DIR 0x00000004 // Direction change -#define QEI_INTEN_TIMER 0x00000002 // Velocity timer expired -#define QEI_INTEN_INDEX 0x00000001 // Index pulse detected - -//***************************************************************************** -// -// The following define the bit fields in the QEI_RIS register. -// -//***************************************************************************** -#define QEI_RIS_ERROR 0x00000008 // Phase error detected -#define QEI_RIS_DIR 0x00000004 // Direction change -#define QEI_RIS_TIMER 0x00000002 // Velocity timer expired -#define QEI_RIS_INDEX 0x00000001 // Index pulse detected - -//***************************************************************************** -// -// The following define the bit fields in the QEI_ISC register. -// -//***************************************************************************** -#define QEI_INT_ERROR 0x00000008 // Phase error detected -#define QEI_INT_DIR 0x00000004 // Direction change -#define QEI_INT_TIMER 0x00000002 // Velocity timer expired -#define QEI_INT_INDEX 0x00000001 // Index pulse detected - -//***************************************************************************** -// -// The following define the reset values for the QEI registers. -// -//***************************************************************************** -#define QEI_RV_CTL 0x00000000 // Configuration and control reg. -#define QEI_RV_STAT 0x00000000 // Status register -#define QEI_RV_POS 0x00000000 // Current position register -#define QEI_RV_MAXPOS 0x00000000 // Maximum position register -#define QEI_RV_LOAD 0x00000000 // Velocity timer load register -#define QEI_RV_TIME 0x00000000 // Velocity timer register -#define QEI_RV_COUNT 0x00000000 // Velocity pulse count register -#define QEI_RV_SPEED 0x00000000 // Velocity speed register -#define QEI_RV_INTEN 0x00000000 // Interrupt enable register -#define QEI_RV_RIS 0x00000000 // Raw interrupt status register -#define QEI_RV_ISC 0x00000000 // Interrupt status register - -#endif // __HW_QEI_H__ diff --git a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_ssi.h b/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_ssi.h deleted file mode 100644 index 9ebf6279a..000000000 --- a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_ssi.h +++ /dev/null @@ -1,120 +0,0 @@ -//***************************************************************************** -// -// hw_ssi.h - Macros used when accessing the SSI hardware. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 816 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_SSI_H__ -#define __HW_SSI_H__ - -//***************************************************************************** -// -// The following define the offsets of the SSI registers. -// -//***************************************************************************** -#define SSI_O_CR0 0x00000000 // Control register 0 -#define SSI_O_CR1 0x00000004 // Control register 1 -#define SSI_O_DR 0x00000008 // Data register -#define SSI_O_SR 0x0000000C // Status register -#define SSI_O_CPSR 0x00000010 // Clock prescale register -#define SSI_O_IM 0x00000014 // Int mask set and clear register -#define SSI_O_RIS 0x00000018 // Raw interrupt register -#define SSI_O_MIS 0x0000001C // Masked interrupt register -#define SSI_O_ICR 0x00000020 // Interrupt clear register - -//***************************************************************************** -// -// The following define the bit fields in the SSI Control register 0. -// -//***************************************************************************** -#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate -#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase -#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity -#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask -#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format -#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format -#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format -#define SSI_CR0_DSS 0x0000000F // Data size select -#define SSI_CR0_DSS_4 0x00000003 // 4 bit data -#define SSI_CR0_DSS_5 0x00000004 // 5 bit data -#define SSI_CR0_DSS_6 0x00000005 // 6 bit data -#define SSI_CR0_DSS_7 0x00000006 // 7 bit data -#define SSI_CR0_DSS_8 0x00000007 // 8 bit data -#define SSI_CR0_DSS_9 0x00000008 // 9 bit data -#define SSI_CR0_DSS_10 0x00000009 // 10 bit data -#define SSI_CR0_DSS_11 0x0000000A // 11 bit data -#define SSI_CR0_DSS_12 0x0000000B // 12 bit data -#define SSI_CR0_DSS_13 0x0000000C // 13 bit data -#define SSI_CR0_DSS_14 0x0000000D // 14 bit data -#define SSI_CR0_DSS_15 0x0000000E // 15 bit data -#define SSI_CR0_DSS_16 0x0000000F // 16 bit data - -//***************************************************************************** -// -// The following define the bit fields in the SSI Control register 1. -// -//***************************************************************************** -#define SSI_CR1_SOD 0x00000008 // Slave mode output disable -#define SSI_CR1_MS 0x00000004 // Master or slave mode select -#define SSI_CR1_SSE 0x00000002 // Sync serial port enable -#define SSI_CR1_LBM 0x00000001 // Loopback mode - -//***************************************************************************** -// -// The following define the bit fields in the SSI Status register. -// -//***************************************************************************** -#define SSI_SR_BSY 0x00000010 // SSI busy -#define SSI_SR_RFF 0x00000008 // RX FIFO full -#define SSI_SR_RNE 0x00000004 // RX FIFO not empty -#define SSI_SR_TNF 0x00000002 // TX FIFO not full -#define SSI_SR_TFE 0x00000001 // TX FIFO empty - -//***************************************************************************** -// -// The following define the bit fields in the SSI clock prescale register. -// -//***************************************************************************** -#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale - -//***************************************************************************** -// -// The following define information concerning the SSI Data register. -// -//***************************************************************************** -#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO -#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO - -//***************************************************************************** -// -// The following define the bit fields in the interrupt mask set and clear, -// raw interrupt, masked interrupt, and interrupt clear registers. -// -//***************************************************************************** -#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt -#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt -#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt -#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt - -#endif // __HW_SSI_H__ diff --git a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_sysctl.h b/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_sysctl.h deleted file mode 100644 index 5ac87f228..000000000 --- a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_sysctl.h +++ /dev/null @@ -1,409 +0,0 @@ -//***************************************************************************** -// -// hw_sysctl.h - Macros used when accessing the system control hardware. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 816 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_SYSCTL_H__ -#define __HW_SYSCTL_H__ - -//***************************************************************************** -// -// The following define the offsets of the system control registers. -// -//***************************************************************************** -#define SYSCTL_DID0 0x400fe000 // Device identification register 0 -#define SYSCTL_DID1 0x400fe004 // Device identification register 1 -#define SYSCTL_DC0 0x400fe008 // Device capabilities register 0 -#define SYSCTL_DC1 0x400fe010 // Device capabilities register 1 -#define SYSCTL_DC2 0x400fe014 // Device capabilities register 2 -#define SYSCTL_DC3 0x400fe018 // Device capabilities register 3 -#define SYSCTL_DC4 0x400fe01C // Device capabilities register 4 -#define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register -#define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register -#define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0 -#define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1 -#define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2 -#define SYSCTL_RIS 0x400fe050 // Raw interrupt status register -#define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register -#define SYSCTL_MISC 0x400fe058 // Interrupt status register -#define SYSCTL_RESC 0x400fe05c // Reset cause register -#define SYSCTL_RCC 0x400fe060 // Run-mode clock config register -#define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register -#define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0 -#define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1 -#define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2 -#define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0 -#define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1 -#define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2 -#define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0 -#define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1 -#define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2 -#define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register -#define SYSCTL_LDOARST 0x400fe160 // LDO reset control register - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DID0 register. -// -//***************************************************************************** -#define SYSCTL_DID0_VER_MASK 0x70000000 // DID0 version mask -#define SYSCTL_DID0_VER_0 0x00000000 // DID0 version 0 -#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask -#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A -#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B -#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask -#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0 -#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DID1 register. -// -//***************************************************************************** -#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask -#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask -#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family -#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask -#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101 -#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102 -#define SYSCTL_DID1_PRTNO_301 0x00110000 // LM3S301 -#define SYSCTL_DID1_PRTNO_310 0x00120000 // LM3S310 -#define SYSCTL_DID1_PRTNO_315 0x00130000 // LM3S315 -#define SYSCTL_DID1_PRTNO_316 0x00140000 // LM3S316 -#define SYSCTL_DID1_PRTNO_328 0x00150000 // LM3S328 -#define SYSCTL_DID1_PRTNO_601 0x00210000 // LM3S601 -#define SYSCTL_DID1_PRTNO_610 0x00220000 // LM3S610 -#define SYSCTL_DID1_PRTNO_611 0x00230000 // LM3S611 -#define SYSCTL_DID1_PRTNO_612 0x00240000 // LM3S612 -#define SYSCTL_DID1_PRTNO_613 0x00250000 // LM3S613 -#define SYSCTL_DID1_PRTNO_615 0x00260000 // LM3S615 -#define SYSCTL_DID1_PRTNO_628 0x00270000 // LM3S628 -#define SYSCTL_DID1_PRTNO_801 0x00310000 // LM3S801 -#define SYSCTL_DID1_PRTNO_811 0x00320000 // LM3S811 -#define SYSCTL_DID1_PRTNO_812 0x00330000 // LM3S812 -#define SYSCTL_DID1_PRTNO_815 0x00340000 // LM3S815 -#define SYSCTL_DID1_PRTNO_828 0x00350000 // LM3S828 -#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask -#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C) -#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C) -#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask -#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC -#define SYSCTL_DID1_PKG_48QFP 0x00000008 // 48-pin QFP -#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant -#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask -#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified) -#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified) -#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified -#define SYSCTL_DID1_PRTNO_SHIFT 16 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC0 register. -// -//***************************************************************************** -#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask -#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2kB of SRAM -#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4kB of SRAM -#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8kB of SRAM -#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask -#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8kB of flash -#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16kB of flash -#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32kB of flash -#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64kB of flash - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC1 register. -// -//***************************************************************************** -#define SYSCTL_DC1_PWM 0x00100000 // PWM module present -#define SYSCTL_DC1_ADC 0x00010000 // ADC module present -#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask -#define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask -#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1Msps ADC -#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500Ksps ADC -#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250Ksps ADC -#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC -#define SYSCTL_DC1_MPU 0x00000080 // Cortex M3 MPU present -#define SYSCTL_DC1_TEMP 0x00000020 // Temperature sensor present -#define SYSCTL_DC1_PLL 0x00000010 // PLL present -#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present -#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present -#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present -#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC2 register. -// -//***************************************************************************** -#define SYSCTL_DC2_COMP2 0x04000000 // Analog comparator 2 present -#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present -#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present -#define SYSCTL_DC2_TIMER2 0x00040000 // Timer 2 present -#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present -#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present -#define SYSCTL_DC2_I2C 0x00001000 // I2C present -#define SYSCTL_DC2_QEI 0x00000100 // QEI present -#define SYSCTL_DC2_SSI 0x00000010 // SSI present -#define SYSCTL_DC2_UART1 0x00000002 // UART 1 present -#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC3 register. -// -//***************************************************************************** -#define SYSCTL_DC3_32KHZ 0x80000000 // 32kHz pin present -#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 pin present -#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 pin present -#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 pin present -#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 pin present -#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present -#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present -#define SYSCTL_DC3_ADC7 0x00800000 // ADC7 pin present -#define SYSCTL_DC3_ADC6 0x00400000 // ADC6 pin present -#define SYSCTL_DC3_ADC5 0x00200000 // ADC5 pin present -#define SYSCTL_DC3_ADC4 0x00100000 // ADC4 pin present -#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 pin present -#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 pin present -#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 pin present -#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 pin present -#define SYSCTL_DC3_C2O 0x00004000 // C2o pin present -#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ pin present -#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- pin present -#define SYSCTL_DC3_C1O 0x00000800 // C1o pin present -#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ pin present -#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present -#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present -#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present -#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present -#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 pin present -#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 pin present -#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 pin present -#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 pin present -#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 pin present -#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 pin present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_DC4 register. -// -//***************************************************************************** -#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO port E present -#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO port D present -#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present -#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present -#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_PBORCTL register. -// -//***************************************************************************** -#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer -#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset -#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise -#define SYSCTL_PBORCTL_BOR_SH 2 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_LDOPCTL register. -// -//***************************************************************************** -#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask -#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V -#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V -#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V -#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V -#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V -#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V -#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V -#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V -#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V -#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V -#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0, -// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers. -// -//***************************************************************************** -#define SYSCTL_SET0_PWM 0x00100000 // PWM module -#define SYSCTL_SET0_ADC 0x00010000 // ADC module -#define SYSCTL_SET0_ADCSPD_MASK 0x00000F00 // ADC speed mask -#define SYSCTL_SET0_ADCSPD_1M 0x00000300 // 1Msps ADC -#define SYSCTL_SET0_ADCSPD_500K 0x00000200 // 500Ksps ADC -#define SYSCTL_SET0_ADCSPD_250K 0x00000100 // 250Ksps ADC -#define SYSCTL_SET0_ADCSPD_125K 0x00000000 // 125Ksps ADC -#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1, -// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers. -// -//***************************************************************************** -#define SYSCTL_SET1_COMP2 0x04000000 // Analog comparator module 2 -#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1 -#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0 -#define SYSCTL_SET1_TIMER2 0x00040000 // Timer module 2 -#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1 -#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0 -#define SYSCTL_SET1_I2C 0x00001000 // I2C module -#define SYSCTL_SET1_QEI 0x00000100 // QEI module -#define SYSCTL_SET1_SSI 0x00000010 // SSI module -#define SYSCTL_SET1_UART1 0x00000002 // UART module 1 -#define SYSCTL_SET1_UART0 0x00000001 // UART module 0 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2, -// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers. -// -//***************************************************************************** -#define SYSCTL_SET2_GPIOE 0x00000010 // GPIO E module -#define SYSCTL_SET2_GPIOD 0x00000008 // GPIO D module -#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module -#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module -#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and -// SYSCTL_IMS registers. -// -//***************************************************************************** -#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt -#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt -#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int -#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int -#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt -#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt -#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_RESC register. -// -//***************************************************************************** -#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset -#define SYSCTL_RESC_SW 0x00000010 // Software reset -#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset -#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset -#define SYSCTL_RESC_POR 0x00000002 // Power on reset -#define SYSCTL_RESC_EXT 0x00000001 // External reset - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_RCC register. -// -//***************************************************************************** -#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating -#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider -#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2 -#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3 -#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4 -#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5 -#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6 -#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7 -#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8 -#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9 -#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10 -#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11 -#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12 -#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13 -#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14 -#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15 -#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16 -#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider -#define SYSCTL_RCC_USE_PWMDIV 0x00100000 // Use PWM clock divider -#define SYSCTL_RCC_PWMDIV_MASK 0x000E0000 // PWM clock divider -#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2 -#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4 -#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8 -#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16 -#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32 -#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64 -#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down -#define SYSCTL_RCC_OE 0x00001000 // PLL output enable -#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass -#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable -#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc -#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal -#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864MHz crystal -#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4MHz crystal -#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal -#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal -#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal -#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal -#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal -#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal -#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal -#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal -#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal -#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select -#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator -#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // Use the internal oscillator -#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // Use the internal oscillator / 4 -#define SYSCTL_RCC_IOSCVER 0x00000008 // Int. osc. verification timer en -#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en -#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal oscillator disable -#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable -#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field -#define SYSCTL_RCC_PWMDIV_SHIFT 17 // Shift to the PWMDIV field -#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field -#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_PLLCFG register. -// -//***************************************************************************** -#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider -#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1 -#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2 -#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4 -#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier -#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider -#define SYSCTL_PLLCFG_F_SHIFT 5 -#define SYSCTL_PLLCFG_R_SHIFT 0 - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_CLKVCLR register. -// -//***************************************************************************** -#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault - -//***************************************************************************** -// -// The following define the bit fields in the SYSCTL_LDOARST register. -// -//***************************************************************************** -#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device - -#endif // __HW_SYSCTL_H__ diff --git a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_timer.h b/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_timer.h deleted file mode 100644 index 6a09cd826..000000000 --- a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_timer.h +++ /dev/null @@ -1,235 +0,0 @@ -//***************************************************************************** -// -// hw_timer.h - Defines and macros used when accessing the timer. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 816 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_TIMER_H__ -#define __HW_TIMER_H__ - -//***************************************************************************** -// -// The following define the offsets of the timer registers. -// -//***************************************************************************** -#define TIMER_O_CFG 0x00000000 // Configuration register -#define TIMER_O_TAMR 0x00000004 // TimerA mode register -#define TIMER_O_TBMR 0x00000008 // TimerB mode register -#define TIMER_O_CTL 0x0000000C // Control register -#define TIMER_O_IMR 0x00000018 // Interrupt mask register -#define TIMER_O_RIS 0x0000001C // Interrupt status register -#define TIMER_O_MIS 0x00000020 // Masked interrupt status reg. -#define TIMER_O_ICR 0x00000024 // Interrupt clear register -#define TIMER_O_TAILR 0x00000028 // TimerA interval load register -#define TIMER_O_TBILR 0x0000002C // TimerB interval load register -#define TIMER_O_TAMATCHR 0x00000030 // TimerA match register -#define TIMER_O_TBMATCHR 0x00000034 // TimerB match register -#define TIMER_O_TAPR 0x00000038 // TimerA prescale register -#define TIMER_O_TBPR 0x0000003C // TimerB prescale register -#define TIMER_O_TAPMR 0x00000040 // TimerA prescale match register -#define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register -#define TIMER_O_TAR 0x00000048 // TimerA register -#define TIMER_O_TBR 0x0000004C // TimerB register - -//***************************************************************************** -// -// The following define the reset values of the timer registers. -// -//***************************************************************************** -#define TIMER_RV_CFG 0x00000000 // Configuration register RV -#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV -#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV -#define TIMER_RV_CTL 0x00000000 // Control register RV -#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV -#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV -#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV -#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV -#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV -#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV -#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV -#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV -#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV -#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV -#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV -#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV -#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV -#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_CFG register. -// -//***************************************************************************** -#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask -#define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers -#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC -#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_TnMR register. -// -//***************************************************************************** -#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select -#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time -#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask -#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture -#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic -#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_CTL register. -// -//***************************************************************************** -#define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert -#define TIMER_CTL_TBOTE 0x00002000 // TimerB output trigger enable -#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask -#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges -#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge -#define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge -#define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable -#define TIMER_CTL_TBEN 0x00000100 // TimerB enable -#define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert -#define TIMER_CTL_TAOTE 0x00000020 // TimerA output trigger enable -#define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable -#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask -#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges -#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge -#define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge -#define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable -#define TIMER_CTL_TAEN 0x00000001 // TimerA enable - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_IMR register. -// -//***************************************************************************** -#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask -#define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask -#define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask -#define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask -#define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask -#define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask -#define TIMER_IMR_TATOIM 0x00000001 // TimerA time out interrupt mask - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_RIS register. -// -//***************************************************************************** -#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status -#define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status -#define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status -#define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status -#define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status -#define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status -#define TIMER_RIS_TATORIS 0x00000001 // TimerA time out raw int status - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_MIS register. -// -//***************************************************************************** -#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status -#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status -#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat -#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status -#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status -#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status -#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_ICR register. -// -//***************************************************************************** -#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear -#define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear -#define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear -#define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear -#define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear -#define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear -#define TIMER_ICR_TATOCINT 0x00000001 // TimerA time out interrupt clear - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_TAILR register. -// -//***************************************************************************** -#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode -#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TBILR register. -// -//***************************************************************************** -#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_TAMATCHR register. -// -//***************************************************************************** -#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode -#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TBMATCHR register. -// -//***************************************************************************** -#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TnPR register. -// -//***************************************************************************** -#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TnPMR register. -// -//***************************************************************************** -#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value - -//***************************************************************************** -// -// The following define the bit fields in the TIMER_TAR register. -// -//***************************************************************************** -#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode -#define TIMER_TAR_TARL 0x0000FFFF // TimerA value - -//***************************************************************************** -// -// The following defines the bit fields in the TIMER_TBR register. -// -//***************************************************************************** -#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value - -#endif // __HW_TIMER_H__ diff --git a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_types.h b/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_types.h deleted file mode 100644 index 0a6084ae3..000000000 --- a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_types.h +++ /dev/null @@ -1,67 +0,0 @@ -//***************************************************************************** -// -// hw_types.h - Common types and macros. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 816 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_TYPES_H__ -#define __HW_TYPES_H__ - -//***************************************************************************** -// -// Define a boolean type, and values for true and false. -// -//***************************************************************************** -typedef unsigned char tBoolean; - -#ifndef true -#define true 1 -#endif - -#ifndef false -#define false 0 -#endif - -//***************************************************************************** -// -// Macros for hardware access, both direct and via the bit-band region. -// -//***************************************************************************** -#define HWREG(x) \ - (*((volatile unsigned long *)(x))) -#define HWREGH(x) \ - (*((volatile unsigned short *)(x))) -#define HWREGB(x) \ - (*((volatile unsigned char *)(x))) -#define HWREGBITW(x, b) \ - HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) -#define HWREGBITH(x, b) \ - HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) -#define HWREGBITB(x, b) \ - HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) - -#endif // __HW_TYPES_H__ diff --git a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_uart.h b/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_uart.h deleted file mode 100644 index a688a6aed..000000000 --- a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_uart.h +++ /dev/null @@ -1,239 +0,0 @@ -//***************************************************************************** -// -// hw_uart.h - Macros and defines used when accessing the UART hardware -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 816 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_UART_H__ -#define __HW_UART_H__ - -//***************************************************************************** -// -// UART Register Offsets. -// -//***************************************************************************** -#define UART_O_DR 0x00000000 // Data Register -#define UART_O_RSR 0x00000004 // Receive Status Register (read) -#define UART_O_ECR 0x00000004 // Error Clear Register (write) -#define UART_O_FR 0x00000018 // Flag Register (read only) -#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg -#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg -#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte -#define UART_O_CTL 0x00000030 // Control Register -#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg -#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg -#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register -#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register -#define UART_O_ICR 0x00000044 // Interrupt Clear Register -#define UART_O_PeriphID4 0x00000FD0 // -#define UART_O_PeriphID5 0x00000FD4 // -#define UART_O_PeriphID6 0x00000FD8 // -#define UART_O_PeriphID7 0x00000FDC // -#define UART_O_PeriphID0 0x00000FE0 // -#define UART_O_PeriphID1 0x00000FE4 // -#define UART_O_PeriphID2 0x00000FE8 // -#define UART_O_PeriphID3 0x00000FEC // -#define UART_O_PCellID0 0x00000FF0 // -#define UART_O_PCellID1 0x00000FF4 // -#define UART_O_PCellID2 0x00000FF8 // -#define UART_O_PCellID3 0x00000FFC // - -//***************************************************************************** -// -// Data Register bits -// -//***************************************************************************** -#define UART_DR_OE 0x00000800 // Overrun Error -#define UART_DR_BE 0x00000400 // Break Error -#define UART_DR_PE 0x00000200 // Parity Error -#define UART_DR_FE 0x00000100 // Framing Error -#define UART_DR_DATA_MASK 0x000000FF // UART data - -//***************************************************************************** -// -// Receive Status Register bits -// -//***************************************************************************** -#define UART_RSR_OE 0x00000008 // Overrun Error -#define UART_RSR_BE 0x00000004 // Break Error -#define UART_RSR_PE 0x00000002 // Parity Error -#define UART_RSR_FE 0x00000001 // Framing Error - -//***************************************************************************** -// -// Flag Register bits -// -//***************************************************************************** -#define UART_FR_TXFE 0x00000080 // TX FIFO Empty -#define UART_FR_RXFF 0x00000040 // RX FIFO Full -#define UART_FR_TXFF 0x00000020 // TX FIFO Full -#define UART_FR_RXFE 0x00000010 // RX FIFO Empty -#define UART_FR_BUSY 0x00000008 // UART Busy - -//***************************************************************************** -// -// Integer baud-rate divisor -// -//***************************************************************************** -#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor - -//***************************************************************************** -// -// Fractional baud-rate divisor -// -//***************************************************************************** -#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor - -//***************************************************************************** -// -// Line Control Register High bits -// -//***************************************************************************** -#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select -#define UART_LCR_H_WLEN 0x00000060 // Word length -#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data -#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data -#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data -#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data -#define UART_LCR_H_FEN 0x00000010 // Enable FIFO -#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select -#define UART_LCR_H_EPS 0x00000004 // Even Parity Select -#define UART_LCR_H_PEN 0x00000002 // Parity Enable -#define UART_LCR_H_BRK 0x00000001 // Send Break - -//***************************************************************************** -// -// Control Register bits -// -//***************************************************************************** -#define UART_CTL_RXE 0x00000200 // Receive Enable -#define UART_CTL_TXE 0x00000100 // Transmit Enable -#define UART_CTL_LBE 0x00000080 // Loopback Enable -#define UART_CTL_UARTEN 0x00000001 // UART Enable - -//***************************************************************************** -// -// Interrupt FIFO Level Select Register bits -// -//***************************************************************************** -#define UART_IFLS_RX1_8 0x00000000 // 1/8 Full -#define UART_IFLS_RX2_8 0x00000010 // 1/4 Full -#define UART_IFLS_RX4_8 0x00000020 // 1/2 Full -#define UART_IFLS_RX6_8 0x00000030 // 3/4 Full -#define UART_IFLS_RX7_8 0x00000040 // 7/8 Full -#define UART_IFLS_TX1_8 0x00000000 // 1/8 Full -#define UART_IFLS_TX2_8 0x00000001 // 1/4 Full -#define UART_IFLS_TX4_8 0x00000002 // 1/2 Full -#define UART_IFLS_TX6_8 0x00000003 // 3/4 Full -#define UART_IFLS_TX7_8 0x00000004 // 7/8 Full - -//***************************************************************************** -// -// Interrupt Mask Set/Clear Register bits -// -//***************************************************************************** -#define UART_IM_OEIM 0x00000400 // Overrun Error Interrupt Mask -#define UART_IM_BEIM 0x00000200 // Break Error Interrupt Mask -#define UART_IM_PEIM 0x00000100 // Parity Error Interrupt Mask -#define UART_IM_FEIM 0x00000080 // Framing Error Interrupt Mask -#define UART_IM_RTIM 0x00000040 // Receive Timeout Interrupt Mask -#define UART_IM_TXIM 0x00000020 // Transmit Interrupt Mask -#define UART_IM_RXIM 0x00000010 // Receive Interrupt Mask - -//***************************************************************************** -// -// Raw Interrupt Status Register -// -//***************************************************************************** -#define UART_RIS_OERIS 0x00000400 // Overrun Error Interrupt Status -#define UART_RIS_BERIS 0x00000200 // Break Error Interrupt Status -#define UART_RIS_PERIS 0x00000100 // Parity Error Interrupt Status -#define UART_RIS_FERIS 0x00000080 // Framing Error Interrupt Status -#define UART_RIS_RTRIS 0x00000040 // Receive Timeout Interrupt Status -#define UART_RIS_TXRIS 0x00000020 // Transmit Interrupt Status -#define UART_RIS_RXRIS 0x00000010 // Receive Interrupt Status - -//***************************************************************************** -// -// Masked Interrupt Status Register -// -//***************************************************************************** -#define UART_MIS_OEMIS 0x00000400 // Overrun Error Interrupt Status -#define UART_MIS_BEMIS 0x00000200 // Break Error Interrupt Status -#define UART_MIS_PEMIS 0x00000100 // Parity Error Interrupt Status -#define UART_MIS_FEMIS 0x00000080 // Framing Error Interrupt Status -#define UART_MIS_RTMIS 0x00000040 // Receive Timeout Interrupt Status -#define UART_MIS_TXMIS 0x00000020 // Transmit Interrupt Status -#define UART_MIS_RXMIS 0x00000010 // Receive Interrupt Status - -//***************************************************************************** -// -// Interrupt Clear Register bits -// -//***************************************************************************** -#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear -#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear -#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear -#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear -#define UART_ICR_RTIC 0x00000040 // Receive Timeout Interrupt Clear -#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear -#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear - -#define UART_RSR_ANY (UART_RSR_OE | \ - UART_RSR_BE | \ - UART_RSR_PE | \ - UART_RSR_FE) - -//***************************************************************************** -// -// Reset Values for UART Registers. -// -//***************************************************************************** -#define UART_RV_DR 0x00000000 -#define UART_RV_RSR 0x00000000 -#define UART_RV_ECR 0x00000000 -#define UART_RV_FR 0x00000090 -#define UART_RV_IBRD 0x00000000 -#define UART_RV_FBRD 0x00000000 -#define UART_RV_LCR_H 0x00000000 -#define UART_RV_CTL 0x00000300 -#define UART_RV_IFLS 0x00000012 -#define UART_RV_IM 0x00000000 -#define UART_RV_RIS 0x00000000 -#define UART_RV_MIS 0x00000000 -#define UART_RV_ICR 0x00000000 -#define UART_RV_PeriphID4 0x00000000 -#define UART_RV_PeriphID5 0x00000000 -#define UART_RV_PeriphID6 0x00000000 -#define UART_RV_PeriphID7 0x00000000 -#define UART_RV_PeriphID0 0x00000011 -#define UART_RV_PeriphID1 0x00000000 -#define UART_RV_PeriphID2 0x00000018 -#define UART_RV_PeriphID3 0x00000001 -#define UART_RV_PCellID0 0x0000000D -#define UART_RV_PCellID1 0x000000F0 -#define UART_RV_PCellID2 0x00000005 -#define UART_RV_PCellID3 0x000000B1 - -#endif // __HW_UART_H__ diff --git a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_watchdog.h b/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_watchdog.h deleted file mode 100644 index e6e3fa50a..000000000 --- a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/hw_watchdog.h +++ /dev/null @@ -1,116 +0,0 @@ -//***************************************************************************** -// -// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 816 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __HW_WATCHDOG_H__ -#define __HW_WATCHDOG_H__ - -//***************************************************************************** -// -// The following define the offsets of the Watchdog Timer registers. -// -//***************************************************************************** -#define WDT_O_LOAD 0x00000000 // Load register -#define WDT_O_VALUE 0x00000004 // Current value register -#define WDT_O_CTL 0x00000008 // Control register -#define WDT_O_ICR 0x0000000C // Interrupt clear register -#define WDT_O_RIS 0x00000010 // Raw interrupt status register -#define WDT_O_MIS 0x00000014 // Masked interrupt status register -#define WDT_O_TEST 0x00000418 // Test register -#define WDT_O_LOCK 0x00000C00 // Lock register -#define WDT_O_PeriphID4 0x00000FD0 // -#define WDT_O_PeriphID5 0x00000FD4 // -#define WDT_O_PeriphID6 0x00000FD8 // -#define WDT_O_PeriphID7 0x00000FDC // -#define WDT_O_PeriphID0 0x00000FE0 // -#define WDT_O_PeriphID1 0x00000FE4 // -#define WDT_O_PeriphID2 0x00000FE8 // -#define WDT_O_PeriphID3 0x00000FEC // -#define WDT_O_PCellID0 0x00000FF0 // -#define WDT_O_PCellID1 0x00000FF4 // -#define WDT_O_PCellID2 0x00000FF8 // -#define WDT_O_PCellID3 0x00000FFC // - -//***************************************************************************** -// -// The following define the bit fields in the WDT_CTL register. -// -//***************************************************************************** -#define WDT_CTL_RESEN 0x00000002 // Enable reset output -#define WDT_CTL_INTEN 0x00000001 // Enable the WDT counter and int - -//***************************************************************************** -// -// The following define the bit fields in the WDT_ISR, WDT_RIS, and WDT_MIS -// registers. -// -//***************************************************************************** -#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired - -//***************************************************************************** -// -// The following define the bit fields in the WDT_TEST register. -// -//***************************************************************************** -#define WDT_TEST_STALL 0x00000100 // Watchdog stall enable -#ifndef DEPRECATED -#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable -#endif - -//***************************************************************************** -// -// The following define the bit fields in the WDT_LOCK register. -// -//***************************************************************************** -#define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked -#define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked -#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer - -//***************************************************************************** -// -// The following define the reset values for the WDT registers. -// -//***************************************************************************** -#define WDT_RV_LOAD 0xFFFFFFFF // Load register -#define WDT_RV_VALUE 0xFFFFFFFF // Current value register -#define WDT_RV_CTL 0x00000000 // Control register -#define WDT_RV_RIS 0x00000000 // Raw interrupt status register -#define WDT_RV_MIS 0x00000000 // Masked interrupt status register -#define WDT_RV_LOCK 0x00000000 // Lock register -#define WDT_RV_PeriphID4 0x00000000 // -#define WDT_RV_PeriphID5 0x00000000 // -#define WDT_RV_PeriphID6 0x00000000 // -#define WDT_RV_PeriphID7 0x00000000 // -#define WDT_RV_PeriphID0 0x00000005 // -#define WDT_RV_PeriphID1 0x00000018 // -#define WDT_RV_PeriphID2 0x00000018 // -#define WDT_RV_PeriphID3 0x00000001 // -#define WDT_RV_PCellID0 0x0000000D // -#define WDT_RV_PCellID1 0x000000F0 // -#define WDT_RV_PCellID2 0x00000005 // -#define WDT_RV_PCellID3 0x000000B1 // - -#endif // __HW_WATCHDOG_H__ diff --git a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/osram96x16.c b/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/osram96x16.c deleted file mode 100644 index 7c6ef0184..000000000 --- a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/osram96x16.c +++ /dev/null @@ -1,952 +0,0 @@ -//***************************************************************************** -// -// osram96x16.c - Driver for the OSRAM 96x16 graphical OLED display. -// -// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 816 of the Stellaris Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup ev_lm3s811_api -//! @{ -// -//***************************************************************************** - -#include "hw_i2c.h" -#include "hw_memmap.h" -#include "hw_sysctl.h" -#include "hw_types.h" -#include "src/debug.h" -#include "src/gpio.h" -#include "src/i2c.h" -#include "src/sysctl.h" -#include "osram96x16.h" - -//***************************************************************************** -// -// The I2C slave address of the SSD0303 controller on the OLED display. -// -//***************************************************************************** -#define SSD0303_ADDR 0x3d - -//***************************************************************************** -// -// A 5x7 font (in a 6x8 cell, where the sixth column is omitted from this -// table) for displaying text on the OLED display. The data is organized as -// bytes from the left column to the right column, with each byte containing -// the top row in the LSB and the bottom row in the MSB. -// -//***************************************************************************** -static const unsigned char g_pucFont[95][5] = -{ - { 0x00, 0x00, 0x00, 0x00, 0x00 }, // " " - { 0x00, 0x00, 0x4f, 0x00, 0x00 }, // ! - { 0x00, 0x07, 0x00, 0x07, 0x00 }, // " - { 0x14, 0x7f, 0x14, 0x7f, 0x14 }, // # - { 0x24, 0x2a, 0x7f, 0x2a, 0x12 }, // $ - { 0x23, 0x13, 0x08, 0x64, 0x62 }, // % - { 0x36, 0x49, 0x55, 0x22, 0x50 }, // & - { 0x00, 0x05, 0x03, 0x00, 0x00 }, // ' - { 0x00, 0x1c, 0x22, 0x41, 0x00 }, // ( - { 0x00, 0x41, 0x22, 0x1c, 0x00 }, // ) - { 0x14, 0x08, 0x3e, 0x08, 0x14 }, // * - { 0x08, 0x08, 0x3e, 0x08, 0x08 }, // + - { 0x00, 0x50, 0x30, 0x00, 0x00 }, // , - { 0x08, 0x08, 0x08, 0x08, 0x08 }, // - - { 0x00, 0x60, 0x60, 0x00, 0x00 }, // . - { 0x20, 0x10, 0x08, 0x04, 0x02 }, // / - { 0x3e, 0x51, 0x49, 0x45, 0x3e }, // 0 - { 0x00, 0x42, 0x7f, 0x40, 0x00 }, // 1 - { 0x42, 0x61, 0x51, 0x49, 0x46 }, // 2 - { 0x21, 0x41, 0x45, 0x4b, 0x31 }, // 3 - { 0x18, 0x14, 0x12, 0x7f, 0x10 }, // 4 - { 0x27, 0x45, 0x45, 0x45, 0x39 }, // 5 - { 0x3c, 0x4a, 0x49, 0x49, 0x30 }, // 6 - { 0x01, 0x71, 0x09, 0x05, 0x03 }, // 7 - { 0x36, 0x49, 0x49, 0x49, 0x36 }, // 8 - { 0x06, 0x49, 0x49, 0x29, 0x1e }, // 9 - { 0x00, 0x36, 0x36, 0x00, 0x00 }, // : - { 0x00, 0x56, 0x36, 0x00, 0x00 }, // ; - { 0x08, 0x14, 0x22, 0x41, 0x00 }, // < - { 0x14, 0x14, 0x14, 0x14, 0x14 }, // = - { 0x00, 0x41, 0x22, 0x14, 0x08 }, // > - { 0x02, 0x01, 0x51, 0x09, 0x06 }, // ? - { 0x32, 0x49, 0x79, 0x41, 0x3e }, // @ - { 0x7e, 0x11, 0x11, 0x11, 0x7e }, // A - { 0x7f, 0x49, 0x49, 0x49, 0x36 }, // B - { 0x3e, 0x41, 0x41, 0x41, 0x22 }, // C - { 0x7f, 0x41, 0x41, 0x22, 0x1c }, // D - { 0x7f, 0x49, 0x49, 0x49, 0x41 }, // E - { 0x7f, 0x09, 0x09, 0x09, 0x01 }, // F - { 0x3e, 0x41, 0x49, 0x49, 0x7a }, // G - { 0x7f, 0x08, 0x08, 0x08, 0x7f }, // H - { 0x00, 0x41, 0x7f, 0x41, 0x00 }, // I - { 0x20, 0x40, 0x41, 0x3f, 0x01 }, // J - { 0x7f, 0x08, 0x14, 0x22, 0x41 }, // K - { 0x7f, 0x40, 0x40, 0x40, 0x40 }, // L - { 0x7f, 0x02, 0x0c, 0x02, 0x7f }, // M - { 0x7f, 0x04, 0x08, 0x10, 0x7f }, // N - { 0x3e, 0x41, 0x41, 0x41, 0x3e }, // O - { 0x7f, 0x09, 0x09, 0x09, 0x06 }, // P - { 0x3e, 0x41, 0x51, 0x21, 0x5e }, // Q - { 0x7f, 0x09, 0x19, 0x29, 0x46 }, // R - { 0x46, 0x49, 0x49, 0x49, 0x31 }, // S - { 0x01, 0x01, 0x7f, 0x01, 0x01 }, // T - { 0x3f, 0x40, 0x40, 0x40, 0x3f }, // U - { 0x1f, 0x20, 0x40, 0x20, 0x1f }, // V - { 0x3f, 0x40, 0x38, 0x40, 0x3f }, // W - { 0x63, 0x14, 0x08, 0x14, 0x63 }, // X - { 0x07, 0x08, 0x70, 0x08, 0x07 }, // Y - { 0x61, 0x51, 0x49, 0x45, 0x43 }, // Z - { 0x00, 0x7f, 0x41, 0x41, 0x00 }, // [ - { 0x02, 0x04, 0x08, 0x10, 0x20 }, // "\" - { 0x00, 0x41, 0x41, 0x7f, 0x00 }, // ] - { 0x04, 0x02, 0x01, 0x02, 0x04 }, // ^ - { 0x40, 0x40, 0x40, 0x40, 0x40 }, // _ - { 0x00, 0x01, 0x02, 0x04, 0x00 }, // ` - { 0x20, 0x54, 0x54, 0x54, 0x78 }, // a - { 0x7f, 0x48, 0x44, 0x44, 0x38 }, // b - { 0x38, 0x44, 0x44, 0x44, 0x20 }, // c - { 0x38, 0x44, 0x44, 0x48, 0x7f }, // d - { 0x38, 0x54, 0x54, 0x54, 0x18 }, // e - { 0x08, 0x7e, 0x09, 0x01, 0x02 }, // f - { 0x0c, 0x52, 0x52, 0x52, 0x3e }, // g - { 0x7f, 0x08, 0x04, 0x04, 0x78 }, // h - { 0x00, 0x44, 0x7d, 0x40, 0x00 }, // i - { 0x20, 0x40, 0x44, 0x3d, 0x00 }, // j - { 0x7f, 0x10, 0x28, 0x44, 0x00 }, // k - { 0x00, 0x41, 0x7f, 0x40, 0x00 }, // l - { 0x7c, 0x04, 0x18, 0x04, 0x78 }, // m - { 0x7c, 0x08, 0x04, 0x04, 0x78 }, // n - { 0x38, 0x44, 0x44, 0x44, 0x38 }, // o - { 0x7c, 0x14, 0x14, 0x14, 0x08 }, // p - { 0x08, 0x14, 0x14, 0x18, 0x7c }, // q - { 0x7c, 0x08, 0x04, 0x04, 0x08 }, // r - { 0x48, 0x54, 0x54, 0x54, 0x20 }, // s - { 0x04, 0x3f, 0x44, 0x40, 0x20 }, // t - { 0x3c, 0x40, 0x40, 0x20, 0x7c }, // u - { 0x1c, 0x20, 0x40, 0x20, 0x1c }, // v - { 0x3c, 0x40, 0x30, 0x40, 0x3c }, // w - { 0x44, 0x28, 0x10, 0x28, 0x44 }, // x - { 0x0c, 0x50, 0x50, 0x50, 0x3c }, // y - { 0x44, 0x64, 0x54, 0x4c, 0x44 }, // z - { 0x00, 0x08, 0x36, 0x41, 0x00 }, // { - { 0x00, 0x00, 0x7f, 0x00, 0x00 }, // | - { 0x00, 0x41, 0x36, 0x08, 0x00 }, // } - { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~ -}; - -//***************************************************************************** -// -// The sequence of commands used to initialize the SSD0303 controller. Each -// command is described as follows: there is a byte specifying the number of -// bytes in the I2C transfer, followed by that many bytes of command data. -// -//***************************************************************************** -static const unsigned char g_pucOSRAMInit[] = -{ - // - // Turn off the panel - // - 0x02, 0x80, 0xae, - - // - // Set lower column address - // - 0x02, 0x80, 0x04, - - // - // Set higher column address - // - 0x02, 0x80, 0x12, - - // - // Set contrast control register - // - 0x04, 0x80, 0x81, 0x80, 0x2b, - - // - // Set segment re-map - // - 0x02, 0x80, 0xa1, - - // - // Set display start line - // - 0x02, 0x80, 0x40, - - // - // Set display offset - // - 0x04, 0x80, 0xd3, 0x80, 0x00, - - // - // Set multiplex ratio - // - 0x04, 0x80, 0xa8, 0x80, 0x0f, - - // - // Set the display to normal mode - // - 0x02, 0x80, 0xa4, - - // - // Non-inverted display - // - 0x02, 0x80, 0xa6, - - // - // Set the page address - // - 0x02, 0x80, 0xb0, - - // - // Set COM output scan direction - // - 0x02, 0x80, 0xc8, - - // - // Set display clock divide ratio/oscillator frequency - // - 0x04, 0x80, 0xd5, 0x80, 0x72, - - // - // Enable mono mode - // - 0x04, 0x80, 0xd8, 0x80, 0x00, - - // - // Set pre-charge period - // - 0x04, 0x80, 0xd9, 0x80, 0x22, - - // - // Set COM pins hardware configuration - // - 0x04, 0x80, 0xda, 0x80, 0x12, - - // - // Set VCOM deslect level - // - 0x04, 0x80, 0xdb, 0x80, 0x0f, - - // - // Set DC-DC on - // - 0x04, 0x80, 0xad, 0x80, 0x8b, - - // - // Turn on the panel - // - 0x02, 0x80, 0xaf, -}; - -//***************************************************************************** -// -// The inter-byte delay required by the SSD0303 OLED controller. -// -//***************************************************************************** -static unsigned long g_ulDelay; - -//***************************************************************************** -// -//! \internal -//! -//! Provide a small delay. -//! -//! \param ulCount is the number of delay loop iterations to perform. -//! -//! Since the SSD0303 controller needs a delay between bytes written to it over -//! the I2C bus, this function provides a means of generating that delay. It -//! is written in assembly to keep the delay consistent across tool chains, -//! avoiding the need to tune the delay based on the tool chain in use. -//! -//! \return None. -// -//***************************************************************************** -#if defined(ewarm) -static void -OSRAMDelay(unsigned long ulCount) -{ - __asm(" subs r0, #1\n" - " bne OSRAMDelay\n" - " bx lr"); -} -#endif -#if defined(gcc) -static void __attribute__((naked)) -OSRAMDelay(unsigned long ulCount) -{ - __asm(" subs r0, #1\n" - " bne OSRAMDelay\n" - " bx lr"); -} -#endif -#if defined(rvmdk) || defined(__ARMCC_VERSION) -__asm void -OSRAMDelay(unsigned long ulCount) -{ - subs r0, #1; - bne OSRAMDelay; - bx lr; -} -#endif - -//***************************************************************************** -// -//! \internal -//! -//! Start a transfer to the SSD0303 controller. -//! -//! \param ucChar is the first byte to be written to the controller. -//! -//! This function will start a transfer to the SSD0303 controller via the I2C -//! bus. -//! -//! The data is written in a polled fashion; this function will not return -//! until the byte has been written to the controller. -//! -//! \return None. -// -//***************************************************************************** -static void -OSRAMWriteFirst(unsigned char ucChar) -{ - // - // Set the slave address. - // - I2CMasterSlaveAddrSet(I2C_MASTER_BASE, SSD0303_ADDR, false); - - // - // Write the first byte to the controller. - // - I2CMasterDataPut(I2C_MASTER_BASE, ucChar); - - // - // Start the transfer. - // - I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_START); -} - -//***************************************************************************** -// -//! \internal -//! -//! Write a byte to the SSD0303 controller. -//! -//! \param ucChar is the byte to be transmitted to the controller. -//! -//! This function continues a transfer to the SSD0303 controller by writing -//! another byte over the I2C bus. This must only be called after calling -//! OSRAMWriteFirst(), but before calling OSRAMWriteFinal(). -//! -//! The data is written in a polled faashion; this function will not return -//! until the byte has been written to the controller. -//! -//! \return None. -// -//***************************************************************************** -static void -OSRAMWriteByte(unsigned char ucChar) -{ - // - // Wait until the current byte has been transferred. - // - while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0) - { - } - - // - // Provide the required inter-byte delay. - // - OSRAMDelay(g_ulDelay); - - // - // Write the next byte to the controller. - // - I2CMasterDataPut(I2C_MASTER_BASE, ucChar); - - // - // Continue the transfer. - // - I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_CONT); -} - -//***************************************************************************** -// -//! \internal -//! -//! Write a sequence of bytes to the SSD0303 controller. -//! -//! This function continues a transfer to the SSD0303 controller by writing a -//! sequence of bytes over the I2C bus. This must only be called after calling -//! OSRAMWriteFirst(), but before calling OSRAMWriteFinal(). -//! -//! The data is written in a polled fashion; this function will not return -//! until the entire byte sequence has been written to the controller. -//! -//! \return None. -// -//***************************************************************************** -static void -OSRAMWriteArray(const unsigned char *pucBuffer, unsigned long ulCount) -{ - // - // Loop while there are more bytes left to be transferred. - // - while(ulCount != 0) - { - // - // Wait until the current byte has been transferred. - // - while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0) - { - } - - // - // Provide the required inter-byte delay. - // - OSRAMDelay(g_ulDelay); - - // - // Write the next byte to the controller. - // - I2CMasterDataPut(I2C_MASTER_BASE, *pucBuffer++); - ulCount--; - - // - // Continue the transfer. - // - I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_CONT); - } -} - -//***************************************************************************** -// -//! \internal -//! -//! Finish a transfer to the SSD0303 controller. -//! -//! \param ucChar is the final byte to be written to the controller. -//! -//! This function will finish a transfer to the SSD0303 controller via the I2C -//! bus. This must only be called after calling OSRAMWriteFirst(). -//! -//! The data is written in a polled fashion; this function will not return -//! until the byte has been written to the controller. -//! -//! \return None. -// -//***************************************************************************** -static void -OSRAMWriteFinal(unsigned char ucChar) -{ - // - // Wait until the current byte has been transferred. - // - while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0) - { - } - - // - // Provide the required inter-byte delay. - // - OSRAMDelay(g_ulDelay); - - // - // Write the final byte to the controller. - // - I2CMasterDataPut(I2C_MASTER_BASE, ucChar); - - // - // Finish the transfer. - // - I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_FINISH); - - // - // Wait until the final byte has been transferred. - // - while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0) - { - } - - // - // Provide the required inter-byte delay. - // - OSRAMDelay(g_ulDelay); -} - -//***************************************************************************** -// -//! Clears the OLED display. -//! -//! This function will clear the display. All pixels in the display will be -//! turned off. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAMClear(void) -{ - static const unsigned char pucRow1[] = - { - 0xb0, 0x80, 0x04, 0x80, 0x12, 0x40 - }; - static const unsigned char pucRow2[] = - { - 0xb1, 0x80, 0x04, 0x80, 0x12, 0x40 - }; - unsigned long ulIdx; - - // - // Move the display cursor to the first column of the first row. - // - OSRAMWriteFirst(0x80); - OSRAMWriteArray(pucRow1, sizeof(pucRow1)); - - // - // Fill this row with zeros. - // - for(ulIdx = 0; ulIdx < 95; ulIdx++) - { - OSRAMWriteByte(0x00); - } - OSRAMWriteFinal(0x00); - - // - // Move the display cursor to the first column of the second row. - // - OSRAMWriteFirst(0x80); - OSRAMWriteArray(pucRow2, sizeof(pucRow2)); - - // - // Fill this row with zeros. - // - for(ulIdx = 0; ulIdx < 95; ulIdx++) - { - OSRAMWriteByte(0x00); - } - OSRAMWriteFinal(0x00); -} - -//***************************************************************************** -// -//! Displays a string on the OLED display. -//! -//! \param pcStr is a pointer to the string to display. -//! \param ulX is the horizontal position to display the string, specified in -//! columns from the left edge of the display. -//! \param ulY is the vertical position to display the string, specified in -//! eight scan line blocks from the top of the display (i.e. only 0 and 1 are -//! valid). -//! -//! This function will draw a string on the display. Only the ASCII characters -//! between 32 (space) and 126 (tilde) are supported; other characters will -//! result in random data being draw on the display (based on whatever appears -//! before/after the font in memory). The font is mono-spaced, so characters -//! such as "i" and "l" have more white space around them than characters such -//! as "m" or "w". -//! -//! If the drawing of the string reaches the right edge of the display, no more -//! characters will be drawn. Therefore, special care is not required to avoid -//! supplying a string that is "too long" to display. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAMStringDraw(const char *pcStr, unsigned long ulX, unsigned long ulY) -{ - // - // Check the arguments. - // - ASSERT(ulX < 96); - ASSERT(ulY < 2); - - // - // Move the display cursor to the requested position on the display. - // - OSRAMWriteFirst(0x80); - OSRAMWriteByte((ulY == 0) ? 0xb0 : 0xb1); - OSRAMWriteByte(0x80); - OSRAMWriteByte((ulX + 36) & 0x0f); - OSRAMWriteByte(0x80); - OSRAMWriteByte(0x10 | (((ulX + 36) >> 4) & 0x0f)); - OSRAMWriteByte(0x40); - - // - // Loop while there are more characters in the string. - // - while(*pcStr != 0) - { - // - // See if there is enough space on the display for this entire - // character. - // - if(ulX <= 90) - { - // - // Write the contents of this character to the display. - // - OSRAMWriteArray(g_pucFont[*pcStr - ' '], 5); - - // - // See if this is the last character to display (either because the - // right edge has been reached or because there are no more - // characters). - // - if((ulX == 90) || (pcStr[1] == 0)) - { - // - // Write the final column of the display. - // - OSRAMWriteFinal(0x00); - - // - // The string has been displayed. - // - return; - } - - // - // Write the inter-character padding column. - // - OSRAMWriteByte(0x00); - } - else - { - // - // Write the portion of the character that will fit onto the - // display. - // - OSRAMWriteArray(g_pucFont[*pcStr - ' '], 95 - ulX); - OSRAMWriteFinal(g_pucFont[*pcStr - ' '][95 - ulX]); - - // - // The string has been displayed. - // - return; - } - - // - // Advance to the next character. - // - pcStr++; - - // - // Increment the X coordinate by the six columns that were just - // written. - // - ulX += 6; - } -} - -//***************************************************************************** -// -//! Displays an image on the OLED display. -//! -//! \param pucImage is a pointer to the image data. -//! \param ulX is the horizontal position to display this image, specified in -//! columns from the left edge of the display. -//! \param ulY is the vertical position to display this image, specified in -//! eight scan line blocks from the top of the display (i.e. only 0 and 1 are -//! valid). -//! \param ulWidth is the width of the image, specified in columns. -//! \param ulHeight is the height of the image, specified in eight row blocks -//! (i.e. only 1 and 2 are valid). -//! -//! This function will display a bitmap graphic on the display. The image to -//! be displayed must be a multiple of eight scan lines high (i.e. one row) and -//! will be drawn at a vertical position that is a multiple of eight scan lines -//! (i.e. scan line zero or scan line eight, corresponding to row zero or row -//! one). -//! -//! The image data is organized with the first row of image data appearing left -//! to right, followed immediately by the second row of image data. Each byte -//! contains the data for the eight scan lines of the column, with the top scan -//! line being in the least significant bit of the byte and the bottom scan -//! line being in the most significant bit of the byte. -//! -//! For example, an image four columns wide and sixteen scan lines tall would -//! be arranged as follows (showing how the eight bytes of the image would -//! appear on the display): -//! -//! \verbatim -//! +-------+ +-------+ +-------+ +-------+ -//! | | 0 | | | 0 | | | 0 | | | 0 | -//! | B | 1 | | B | 1 | | B | 1 | | B | 1 | -//! | y | 2 | | y | 2 | | y | 2 | | y | 2 | -//! | t | 3 | | t | 3 | | t | 3 | | t | 3 | -//! | e | 4 | | e | 4 | | e | 4 | | e | 4 | -//! | | 5 | | | 5 | | | 5 | | | 5 | -//! | 0 | 6 | | 1 | 6 | | 2 | 6 | | 3 | 6 | -//! | | 7 | | | 7 | | | 7 | | | 7 | -//! +-------+ +-------+ +-------+ +-------+ -//! -//! +-------+ +-------+ +-------+ +-------+ -//! | | 0 | | | 0 | | | 0 | | | 0 | -//! | B | 1 | | B | 1 | | B | 1 | | B | 1 | -//! | y | 2 | | y | 2 | | y | 2 | | y | 2 | -//! | t | 3 | | t | 3 | | t | 3 | | t | 3 | -//! | e | 4 | | e | 4 | | e | 4 | | e | 4 | -//! | | 5 | | | 5 | | | 5 | | | 5 | -//! | 4 | 6 | | 5 | 6 | | 6 | 6 | | 7 | 6 | -//! | | 7 | | | 7 | | | 7 | | | 7 | -//! +-------+ +-------+ +-------+ +-------+ -//! \endverbatim -//! -//! \return None. -// -//***************************************************************************** -void -OSRAMImageDraw(const unsigned char *pucImage, unsigned long ulX, - unsigned long ulY, unsigned long ulWidth, - unsigned long ulHeight) -{ - // - // Check the arguments. - // - ASSERT(ulX < 96); - ASSERT(ulY < 2); - ASSERT((ulX + ulWidth) <= 96); - ASSERT((ulY + ulHeight) <= 2); - - // - // The first 36 columns of the LCD buffer are not displayed, so increment - // the X coorddinate by 36 to account for the non-displayed frame buffer - // memory. - // - ulX += 36; - - // - // Loop while there are more rows to display. - // - while(ulHeight--) - { - // - // Write the starting address within this row. - // - OSRAMWriteFirst(0x80); - OSRAMWriteByte((ulY == 0) ? 0xb0 : 0xb1); - OSRAMWriteByte(0x80); - OSRAMWriteByte(ulX & 0x0f); - OSRAMWriteByte(0x80); - OSRAMWriteByte(0x10 | ((ulX >> 4) & 0x0f)); - OSRAMWriteByte(0x40); - - // - // Write this row of image data. - // - OSRAMWriteArray(pucImage, ulWidth - 1); - OSRAMWriteFinal(pucImage[ulWidth - 1]); - - // - // Advance to the next row of the image. - // - pucImage += ulWidth; - ulY++; - } -} - -//***************************************************************************** -// -//! Initialize the OLED display. -//! -//! \param bFast is a boolean that is \e true if the I2C interface should be -//! run at 400 kbps and \e false if it should be run at 100 kbps. -//! -//! This function initializes the I2C interface to the OLED display and -//! configures the SSD0303 controller on the panel. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAMInit(tBoolean bFast) -{ - unsigned long ulIdx; - - // - // Enable the I2C and GPIO port B blocks as they are needed by this driver. - // - SysCtlPeripheralEnable(SYSCTL_PERIPH_I2C); - SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB); - - // - // Configure the I2C SCL and SDA pins for I2C operation. - // - GPIOPinTypeI2C(GPIO_PORTB_BASE, GPIO_PIN_2 | GPIO_PIN_3); - - // - // Initialize the I2C master. - // - I2CMasterInit(I2C_MASTER_BASE, bFast); - - // - // Compute the inter-byte delay for the SSD0303 controller. This delay is - // dependent upon the I2C bus clock rate; the slower the clock the longer - // the delay required. - // - // The derivation of this formula is based on a measured delay of - // OSRAMDelay(1700) for a 100 kHz I2C bus with the CPU running at 50 MHz - // (referred to as C). To scale this to the delay for a different CPU - // speed (since this is just a CPU-based delay loop) is: - // - // f(CPU) - // C * ---------- - // 50,000,000 - // - // To then scale this to the actual I2C rate (since it won't always be - // precisely 100 kHz): - // - // f(CPU) 100,000 - // C * ---------- * ------- - // 50,000,000 f(I2C) - // - // This equation will give the inter-byte delay required for any - // configuration of the I2C master. But, as arranged it is impossible to - // directly compute in 32-bit arithmetic (without loosing a lot of - // accuracy). So, the equation is simplified. - // - // Since f(I2C) is generated by dividing down from f(CPU), replace it with - // the equivalent (where TPR is the value programmed into the Master Timer - // Period Register of the I2C master, with the 1 added back): - // - // 100,000 - // f(CPU) ------- - // C * ---------- * f(CPU) - // 50,000,000 ------------ - // 2 * 10 * TPR - // - // Inverting the dividend in the last term: - // - // f(CPU) 100,000 * 2 * 10 * TPR - // C * ---------- * ---------------------- - // 50,000,000 f(CPU) - // - // The f(CPU) now cancels out. - // - // 100,000 * 2 * 10 * TPR - // C * ---------------------- - // 50,000,000 - // - // Since there are no clock frequencies left in the equation, this equation - // also works for 400 kHz bus operation as well, since the 100,000 in the - // numerator becomes 400,000 but C is 1/4, which cancel out each other. - // Reducing the constants gives: - // - // TPR TPR TPR - // C * --- = 1700 * --- = 340 * --- - // 25 25 5 - // - // Note that the constant C is actually a bit larger than it needs to be in - // order to provide some safety margin. - // - // When the panel is being initialized, the value of C actually needs to be - // a bit longer (3200 instead of 1700). So, set the larger value for now. - // - g_ulDelay = (640 * (HWREG(I2C_MASTER_BASE + I2C_MASTER_O_TPR) + 1)) / 5; - - // - // Initialize the SSD0303 controller. Loop through the initialization - // sequence doing a single I2C transfer for each command. - // - for(ulIdx = 0; ulIdx < sizeof(g_pucOSRAMInit); - ulIdx += g_pucOSRAMInit[ulIdx] + 1) - { - // - // Send this command. - // - OSRAMWriteFirst(g_pucOSRAMInit[ulIdx + 1]); - OSRAMWriteArray(g_pucOSRAMInit + ulIdx + 2, g_pucOSRAMInit[ulIdx] - 2); - OSRAMWriteFinal(g_pucOSRAMInit[ulIdx + g_pucOSRAMInit[ulIdx]]); - } - - // - // Now, switch to the actual value of C. - // - g_ulDelay = (340 * (HWREG(I2C_MASTER_BASE + I2C_MASTER_O_TPR) + 1)) / 5; - - // - // Clear the frame buffer. - // - OSRAMClear(); -} - -//***************************************************************************** -// -//! Turns on the OLED display. -//! -//! This function will turn on the OLED display, causing it to display the -//! contents of its internal frame buffer. -//! -//! \return None. -// -//***************************************************************************** -void -OSRAMDisplayOn(void) -{ - // - // Turn on the DC-DC converter and the display. - // - OSRAMWriteFirst(0x80); - OSRAMWriteByte(0xad); - OSRAMWriteByte(0x80); - OSRAMWriteByte(0x8b); - OSRAMWriteByte(0x80); - OSRAMWriteFinal(0xaf); -} - -//***************************************************************************** -// -//! Turns off the OLED display. -//! -//! This function will turn off the OLED display. This will stop the scanning -//! of the panel and turn off the on-chip DC-DC converter, preventing damage to -//! the panel due to burn-in (it has similar characters to a CRT in this -//! respect). -//! -//! \return None. -// -//***************************************************************************** -void -OSRAMDisplayOff(void) -{ - // - // Turn off the DC-DC converter and the display. - // - OSRAMWriteFirst(0x80); - OSRAMWriteByte(0xad); - OSRAMWriteByte(0x80); - OSRAMWriteByte(0x8a); - OSRAMWriteByte(0x80); - OSRAMWriteFinal(0xae); -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/osram96x16.h b/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/osram96x16.h deleted file mode 100644 index 54cf4215a..000000000 --- a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/osram96x16.h +++ /dev/null @@ -1,47 +0,0 @@ -//***************************************************************************** -// -// osram96x16.h - Prototypes for the driver for the OSRAM 96x16 graphical OLED -// display. -// -// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 852 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __OSRAM96X16_H__ -#define __OSRAM96X16_H__ - -//***************************************************************************** -// -// Prototypes for the driver APIs. -// -//***************************************************************************** -extern void OSRAMClear(void); -extern void OSRAMStringDraw(const char *pcStr, unsigned long ulX, - unsigned long ulY); -extern void OSRAMImageDraw(const unsigned char *pucImage, unsigned long ulX, - unsigned long ulY, unsigned long ulWidth, - unsigned long ulHeight); -extern void OSRAMInit(tBoolean bFast); -extern void OSRAMDisplayOn(void); -extern void OSRAMDisplayOff(void); - -#endif // __OSRAM96X16_H__ diff --git a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/adc.h b/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/adc.h deleted file mode 100644 index ee06b9c29..000000000 --- a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/adc.h +++ /dev/null @@ -1,124 +0,0 @@ -//***************************************************************************** -// -// adc.h - ADC headers for using the ADC driver functions. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 816 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __ADC_H__ -#define __ADC_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to ADCSequenceConfigure as the ulTrigger -// parameter. -// -//***************************************************************************** -#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event -#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event -#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event -#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event -#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event -#define ADC_TRIGGER_TIMER 0x00000005 // Timer event -#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event -#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event -#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event -#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event - -//***************************************************************************** -// -// Values that can be passed to ADCSequenceStepConfigure as the ulConfig -// parameter. -// -//***************************************************************************** -#define ADC_CTL_TS 0x00000080 // Temperature sensor select -#define ADC_CTL_IE 0x00000040 // Interrupt enable -#define ADC_CTL_END 0x00000020 // Sequence end select -#define ADC_CTL_D 0x00000010 // Differential select -#define ADC_CTL_CH0 0x00000000 // Input channel 0 -#define ADC_CTL_CH1 0x00000001 // Input channel 1 -#define ADC_CTL_CH2 0x00000002 // Input channel 2 -#define ADC_CTL_CH3 0x00000003 // Input channel 3 -#define ADC_CTL_CH4 0x00000004 // Input channel 4 -#define ADC_CTL_CH5 0x00000005 // Input channel 5 -#define ADC_CTL_CH6 0x00000006 // Input channel 6 -#define ADC_CTL_CH7 0x00000007 // Input channel 7 - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum, - void (*pfnHandler)(void)); -extern void ADCIntUnregister(unsigned long ulBase, - unsigned long ulSequenceNum); -extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum); -extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum); -extern unsigned long ADCIntStatus(unsigned long ulBase, - unsigned long ulSequenceNum, - tBoolean bMasked); -extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum); -extern void ADCSequenceEnable(unsigned long ulBase, - unsigned long ulSequenceNum); -extern void ADCSequenceDisable(unsigned long ulBase, - unsigned long ulSequenceNum); -extern void ADCSequenceConfigure(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long ulTrigger, - unsigned long ulPriority); -extern void ADCSequenceStepConfigure(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long ulStep, - unsigned long ulConfig); -extern long ADCSequenceOverflow(unsigned long ulBase, - unsigned long ulSequenceNum); -extern long ADCSequenceUnderflow(unsigned long ulBase, - unsigned long ulSequenceNum); -extern long ADCSequenceDataGet(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long *pulBuffer); -extern void ADCProcessorTrigger(unsigned long ulBase, - unsigned long ulSequenceNum); -extern void ADCSoftwareOversampleConfigure(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long ulFactor); -extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long ulStep, - unsigned long ulConfig); -extern void ADCSoftwareOversampleDataGet(unsigned long ulBase, - unsigned long ulSequenceNum, - unsigned long *pulBuffer, - unsigned long ulCount); - -#ifdef __cplusplus -} -#endif - -#endif // __ADC_H__ diff --git a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/comp.h b/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/comp.h deleted file mode 100644 index 14751223a..000000000 --- a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/comp.h +++ /dev/null @@ -1,120 +0,0 @@ -//***************************************************************************** -// -// comp.h - Prototypes for the analog comparator driver. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 816 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __COMP_H__ -#define __COMP_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to ComparatorConfigure() as the ulConfig -// parameter. For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of -// the values may be selected and ORed together will values from the other -// groups. -// -//***************************************************************************** -#define COMP_TRIG_NONE 0x00000000 // No ADC trigger -#define COMP_TRIG_HIGH 0x00000880 // Trigger when high -#define COMP_TRIG_LOW 0x00000800 // Trigger when low -#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge -#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge -#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges -#define COMP_INT_HIGH 0x00000010 // Interrupt when high -#define COMP_INT_LOW 0x00000000 // Interrupt when low -#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge -#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge -#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges -#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin -#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin -#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference -#define COMP_OUTPUT_NONE 0x00000000 // No comparator output -#define COMP_OUTPUT_NORMAL 0x00000100 // Comparator output normal -#define COMP_OUTPUT_INVERT 0x00000102 // Comparator output inverted - -//***************************************************************************** -// -// Values that can be passed to ComparatorSetRef() as the ulRef parameter. -// -//***************************************************************************** -#define COMP_REF_OFF 0x00000000 // Turn off the internal reference -#define COMP_REF_0V 0x00000300 // Internal reference of 0V -#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V -#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V -#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V -#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V -#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V -#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V -#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V -#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V -#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V -#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V -#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V -#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V -#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V -#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V -#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V -#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V -#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V -#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V -#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V -#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V -#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V -#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V -#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V -#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V -#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V -#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V -#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp, - unsigned long ulConfig); -extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef); -extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp); -extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp, - void (*pfnHandler)(void)); -extern void ComparatorIntUnregister(unsigned long ulBase, - unsigned long ulComp); -extern void ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp); -extern void ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp); -extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp, - tBoolean bMasked); -extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp); - -#ifdef __cplusplus -} -#endif - -#endif // __COMP_H__ diff --git a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/cpu.h b/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/cpu.h deleted file mode 100644 index a71928c99..000000000 --- a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/cpu.h +++ /dev/null @@ -1,40 +0,0 @@ -//***************************************************************************** -// -// cpu.h - Prototypes for the CPU instruction wrapper functions. -// -// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 816 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __CPU_H__ -#define __CPU_H__ - -//***************************************************************************** -// -// Prototypes. -// -//***************************************************************************** -extern void CPUcpsid(void); -extern void CPUcpsie(void); -extern void CPUwfi(void); - -#endif // __CPU_H__ diff --git a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/debug.h b/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/debug.h deleted file mode 100644 index 0000ed346..000000000 --- a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/debug.h +++ /dev/null @@ -1,56 +0,0 @@ -//***************************************************************************** -// -// debug.h - Macros for assisting debug of the driver library. -// -// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 816 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __DEBUG_H__ -#define __DEBUG_H__ - -//***************************************************************************** -// -// Prototype for the function that is called when an invalid argument is passed -// to an API. This is only used when doing a DEBUG build. -// -//***************************************************************************** -extern void __error__(char *pcFilename, unsigned long ulLine); - -//***************************************************************************** -// -// The ASSERT macro, which does the actual assertion checking. Typically, this -// will be for procedure arguments. -// -//***************************************************************************** -#ifdef DEBUG -#define ASSERT(expr) { \ - if(!(expr)) \ - { \ - __error__(__FILE__, __LINE__); \ - } \ - } -#else -#define ASSERT(expr) -#endif - -#endif // __DEBUG_H__ diff --git a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/flash.h b/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/flash.h deleted file mode 100644 index f8ff60a12..000000000 --- a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/flash.h +++ /dev/null @@ -1,75 +0,0 @@ -//***************************************************************************** -// -// flash.h - Prototypes for the flash driver. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 816 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __FLASH_H__ -#define __FLASH_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to FlashProtectSet(), and returned by -// FlashProtectGet(). -// -//***************************************************************************** -typedef enum -{ - FlashReadWrite, // Flash can be read and written - FlashReadOnly, // Flash can only be read - FlashExecuteOnly // Flash can only be executed -} -tFlashProtection; - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern unsigned long FlashUsecGet(void); -extern void FlashUsecSet(unsigned long ulClocks); -extern long FlashErase(unsigned long ulAddress); -extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress, - unsigned long ulCount); -extern tFlashProtection FlashProtectGet(unsigned long ulAddress); -extern long FlashProtectSet(unsigned long ulAddress, - tFlashProtection eProtect); -extern long FlashProtectSave(void); -extern void FlashIntRegister(void (*pfnHandler)(void)); -extern void FlashIntUnregister(void); -extern void FlashIntEnable(unsigned long ulIntFlags); -extern void FlashIntDisable(unsigned long ulIntFlags); -extern unsigned long FlashIntGetStatus(tBoolean bMasked); -extern void FlashIntClear(unsigned long ulIntFlags); - -#ifdef __cplusplus -} -#endif - -#endif // __FLASH_H__ diff --git a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/gpio.h b/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/gpio.h deleted file mode 100644 index ec682b54d..000000000 --- a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/gpio.h +++ /dev/null @@ -1,137 +0,0 @@ -//***************************************************************************** -// -// gpio.h - Defines and Macros for GPIO API. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 816 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __GPIO_H__ -#define __GPIO_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following values define the bit field for the ucPins argument to several -// of the APIs. -// -//***************************************************************************** -#define GPIO_PIN_0 0x00000001 // GPIO pin 0 -#define GPIO_PIN_1 0x00000002 // GPIO pin 1 -#define GPIO_PIN_2 0x00000004 // GPIO pin 2 -#define GPIO_PIN_3 0x00000008 // GPIO pin 3 -#define GPIO_PIN_4 0x00000010 // GPIO pin 4 -#define GPIO_PIN_5 0x00000020 // GPIO pin 5 -#define GPIO_PIN_6 0x00000040 // GPIO pin 6 -#define GPIO_PIN_7 0x00000080 // GPIO pin 7 - -//***************************************************************************** -// -// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and -// returned from GPIODirModeGet. -// -//***************************************************************************** -#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input -#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output -#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function - -//***************************************************************************** -// -// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and -// returned from GPIOIntTypeGet. -// -//***************************************************************************** -#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge -#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge -#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges -#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level -#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level - -//***************************************************************************** -// -// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter, -// and returned by GPIOPadConfigGet in the *pulStrength parameter. -// -//***************************************************************************** -#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength -#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength -#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength -#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control - -//***************************************************************************** -// -// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter, -// and returned by GPIOPadConfigGet in the *pulPadType parameter. -// -//***************************************************************************** -#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull -#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up -#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down -#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain -#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up -#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down -#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulPinIO); -extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin); -extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulIntType); -extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin); -extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulStrength, - unsigned long ulPadType); -extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin, - unsigned long *pulStrength, - unsigned long *pulPadType); -extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins); -extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked); -extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPortIntRegister(unsigned long ulPort, - void (*pfIntHandler)(void)); -extern void GPIOPortIntUnregister(unsigned long ulPort); -extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, - unsigned char ucVal); -extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins); - -#ifdef __cplusplus -} -#endif - -#endif // __GPIO_H__ diff --git a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/i2c.h b/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/i2c.h deleted file mode 100644 index 88234a862..000000000 --- a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/i2c.h +++ /dev/null @@ -1,137 +0,0 @@ -//***************************************************************************** -// -// i2c.h - Prototypes for the I2C Driver. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 816 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __I2C_H__ -#define __I2C_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Defines for the API. -// -//***************************************************************************** -//***************************************************************************** -// -// Interrupt defines. -// -//***************************************************************************** -#define I2C_INT_MASTER 0x00000001 -#define I2C_INT_SLAVE 0x00000002 - -//***************************************************************************** -// -// I2C Master commands. -// -//***************************************************************************** -#define I2C_MASTER_CMD_SINGLE_SEND \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_SINGLE_RECEIVE \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_SEND_START \ - (I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_SEND_CONT \ - (I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_SEND_FINISH \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ - (I2C_MASTER_CS_STOP) -#define I2C_MASTER_CMD_BURST_RECEIVE_START \ - (I2C_MASTER_CS_ACK | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ - (I2C_MASTER_CS_ACK | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) -#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ - (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN) - -//***************************************************************************** -// -// I2C Master error status. -// -//***************************************************************************** -#define I2C_MASTER_ERR_NONE 0 -#define I2C_MASTER_ERR_ADDR_ACK 0x00000004 -#define I2C_MASTER_ERR_DATA_ACK 0x00000008 -#define I2C_MASTER_ERR_ARB_LOST 0x00000010 - -//***************************************************************************** -// -// I2C Slave action requests -// -//***************************************************************************** -#define I2C_SLAVE_ACT_NONE 0 -#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data -#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data - -//***************************************************************************** -// Miscellaneous I2C driver definitions. -//***************************************************************************** -#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void)); -extern void I2CIntUnregister(unsigned long ulBase); -extern tBoolean I2CMasterBusBusy(unsigned long ulBase); -extern tBoolean I2CMasterBusy(unsigned long ulBase); -extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd); -extern unsigned long I2CMasterDataGet(unsigned long ulBase); -extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData); -extern void I2CMasterDisable(unsigned long ulBase); -extern void I2CMasterEnable(unsigned long ulBase); -extern unsigned long I2CMasterErr(unsigned long ulBase); -extern void I2CMasterInit(unsigned long ulBase, tBoolean bFast); -extern void I2CMasterIntClear(unsigned long ulBase); -extern void I2CMasterIntDisable(unsigned long ulBase); -extern void I2CMasterIntEnable(unsigned long ulBase); -extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void I2CMasterSlaveAddrSet(unsigned long ulBase, - unsigned char ucSlaveAddr, - tBoolean bReceive); -extern unsigned long I2CSlaveDataGet(unsigned long ulBase); -extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData); -extern void I2CSlaveDisable(unsigned long ulBase); -extern void I2CSlaveEnable(unsigned long ulBase); -extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr); -extern void I2CSlaveIntClear(unsigned long ulBase); -extern void I2CSlaveIntDisable(unsigned long ulBase); -extern void I2CSlaveIntEnable(unsigned long ulBase); -extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked); -extern unsigned long I2CSlaveStatus(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __I2C_H__ diff --git a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/interrupt.h b/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/interrupt.h deleted file mode 100644 index edd8a0897..000000000 --- a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/interrupt.h +++ /dev/null @@ -1,57 +0,0 @@ -//***************************************************************************** -// -// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 816 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __INTERRUPT_H__ -#define __INTERRUPT_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void IntMasterEnable(void); -extern void IntMasterDisable(void); -extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)); -extern void IntUnregister(unsigned long ulInterrupt); -extern void IntPriorityGroupingSet(unsigned long ulBits); -extern unsigned long IntPriorityGroupingGet(void); -extern void IntPrioritySet(unsigned long ulInterrupt, - unsigned char ucPriority); -extern long IntPriorityGet(unsigned long ulInterrupt); -extern void IntEnable(unsigned long ulInterrupt); -extern void IntDisable(unsigned long ulInterrupt); - -#ifdef __cplusplus -} -#endif - -#endif // __INTERRUPT_H__ diff --git a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/pwm.h b/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/pwm.h deleted file mode 100644 index 0986833db..000000000 --- a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/pwm.h +++ /dev/null @@ -1,161 +0,0 @@ -//***************************************************************************** -// -// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 816 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __PWM_H__ -#define __PWM_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following defines are passed to PWMGenConfigure() as the ulConfig -// parameter and specify the configuration of the PWM generator. -// -//***************************************************************************** -#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode -#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode -#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates -#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates -#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode -#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode - -//***************************************************************************** -// -// Defines for enabling, disabling, and clearing PWM generator interrupts and -// triggers. -// -//***************************************************************************** -#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0 -#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD -#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U -#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D -#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U -#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D -#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0 -#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD -#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U -#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D -#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U -#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D - -//***************************************************************************** -// -// Defines for enabling, disabling, and clearing PWM interrupts. -// -//***************************************************************************** -#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt -#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt -#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt -#define PWM_INT_FAULT 0x00010000 // Fault interrupt - -//***************************************************************************** -// -// Defines to identify the generators within a module. -// -//***************************************************************************** -#define PWM_GEN_0 0x00000040 // Offset address of Gen0 -#define PWM_GEN_1 0x00000080 // Offset address of Gen1 -#define PWM_GEN_2 0x000000C0 // Offset address of Gen2 - -#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0 -#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1 -#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2 - -//***************************************************************************** -// -// Defines to identify the outputs within a module. -// -//***************************************************************************** -#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0 -#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1 -#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2 -#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3 -#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4 -#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5 - -#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0 -#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1 -#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2 -#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3 -#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4 -#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5 - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen, - unsigned long ulConfig); -extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen, - unsigned long ulPeriod); -extern unsigned long PWMGenPeriodGet(unsigned long ulBase, - unsigned long ulGen); -extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen); -extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen); -extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut, - unsigned long ulWidth); -extern unsigned long PWMPulseWidthGet(unsigned long ulBase, - unsigned long ulPWMOut); -extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen, - unsigned short usRise, unsigned short usFall); -extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen); -extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits); -extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits); -extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits, - tBoolean bEnable); -extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits, - tBoolean bInvert); -extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits, - tBoolean bFaultKill); -extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen, - void (*pfIntHandler)(void)); -extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen); -extern void PWMFaultIntRegister(unsigned long ulBase, - void (*pfIntHandler)(void)); -extern void PWMFaultIntUnregister(unsigned long ulBase); -extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen, - unsigned long ulIntTrig); -extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen, - unsigned long ulIntTrig); -extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen, - tBoolean bMasked); -extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen, - unsigned long ulInts); -extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault); -extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault); -extern void PWMFaultIntClear(unsigned long ulBase); -extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked); - -#ifdef __cplusplus -} -#endif - -#endif // __PWM_H__ diff --git a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/qei.h b/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/qei.h deleted file mode 100644 index 9cea48b89..000000000 --- a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/qei.h +++ /dev/null @@ -1,104 +0,0 @@ -//***************************************************************************** -// -// qei.h - Prototypes for the Quadrature Encoder Driver. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 816 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __QEI_H__ -#define __QEI_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to QEIConfigure as the ulConfig paramater. -// -//***************************************************************************** -#define QEI_CONFIG_CAPTURE_A 0x00000000 // Count on ChA edges only -#define QEI_CONFIG_CAPTURE_A_B 0x00000008 // Count on ChA and ChB edges -#define QEI_CONFIG_NO_RESET 0x00000000 // Do not reset on index pulse -#define QEI_CONFIG_RESET_IDX 0x00000010 // Reset position on index pulse -#define QEI_CONFIG_QUADRATURE 0x00000000 // ChA and ChB are quadrature -#define QEI_CONFIG_CLOCK_DIR 0x00000004 // ChA and ChB are clock and dir -#define QEI_CONFIG_NO_SWAP 0x00000000 // Do not swap ChA and ChB -#define QEI_CONFIG_SWAP 0x00000002 // Swap ChA and ChB - -//***************************************************************************** -// -// Values that can be passed to QEIVelocityConfigure as the ulPreDiv parameter. -// -//***************************************************************************** -#define QEI_VELDIV_1 0x00000000 // Predivide by 1 -#define QEI_VELDIV_2 0x00000040 // Predivide by 2 -#define QEI_VELDIV_4 0x00000080 // Predivide by 4 -#define QEI_VELDIV_8 0x000000C0 // Predivide by 8 -#define QEI_VELDIV_16 0x00000100 // Predivide by 16 -#define QEI_VELDIV_32 0x00000140 // Predivide by 32 -#define QEI_VELDIV_64 0x00000180 // Predivide by 64 -#define QEI_VELDIV_128 0x000001C0 // Predivide by 128 - -//***************************************************************************** -// -// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts -// as the ulIntFlags parameter, and returned by QEIGetIntStatus. -// -//***************************************************************************** -#define QEI_INTERROR 0x00000008 // Phase error detected -#define QEI_INTDIR 0x00000004 // Direction change -#define QEI_INTTIMER 0x00000002 // Velocity timer expired -#define QEI_INTINDEX 0x00000001 // Index pulse detected - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void QEIEnable(unsigned long ulBase); -extern void QEIDisable(unsigned long ulBase); -extern void QEIConfigure(unsigned long ulBase, unsigned long ulConfig, - unsigned long ulMaxPosition); -extern unsigned long QEIPositionGet(unsigned long ulBase); -extern void QEIPositionSet(unsigned long ulBase, unsigned long ulPosition); -extern long QEIDirectionGet(unsigned long ulBase); -extern tBoolean QEIErrorGet(unsigned long ulBase); -extern void QEIVelocityEnable(unsigned long ulBase); -extern void QEIVelocityDisable(unsigned long ulBase); -extern void QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv, - unsigned long ulPeriod); -extern unsigned long QEIVelocityGet(unsigned long ulBase); -extern void QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); -extern void QEIIntUnregister(unsigned long ulBase); -extern void QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long QEIIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags); - -#ifdef __cplusplus -} -#endif - -#endif // __QEI_H__ diff --git a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/ssi.h b/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/ssi.h deleted file mode 100644 index b697a1069..000000000 --- a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/ssi.h +++ /dev/null @@ -1,88 +0,0 @@ -//***************************************************************************** -// -// ssi.h - Prototypes for the Synchronous Serial Interface Driver. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 816 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __SSI_H__ -#define __SSI_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear -// as the ulIntFlags parameter, and returned by SSIIntStatus. -// -//***************************************************************************** -#define SSI_TXFF 0x00000008 // TX FIFO half empty or less -#define SSI_RXFF 0x00000004 // RX FIFO half full or less -#define SSI_RXTO 0x00000002 // RX timeout -#define SSI_RXOR 0x00000001 // RX overrun - -//***************************************************************************** -// -// Values that can be passed to SSIConfig. -// -//***************************************************************************** -#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 -#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 -#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 -#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 -#define SSI_FRF_TI 0x00000010 // TI frame format -#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format - -#define SSI_MODE_MASTER 0x00000000 // SSI master -#define SSI_MODE_SLAVE 0x00000001 // SSI slave -#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void SSIConfig(unsigned long ulBase, unsigned long ulProtocol, - unsigned long ulMode, unsigned long ulBitRate, - unsigned long ulDataWidth); -extern void SSIDataGet(unsigned long ulBase, unsigned long *ulData); -extern long SSIDataNonBlockingGet(unsigned long ulBase, unsigned long *ulData); -extern void SSIDataPut(unsigned long ulBase, unsigned long ulData); -extern long SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData); -extern void SSIDisable(unsigned long ulBase); -extern void SSIEnable(unsigned long ulBase); -extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags); -extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); -extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void SSIIntUnregister(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __SSI_H__ diff --git a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/sysctl.h b/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/sysctl.h deleted file mode 100644 index 098013d63..000000000 --- a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/sysctl.h +++ /dev/null @@ -1,285 +0,0 @@ -//***************************************************************************** -// -// sysctl.h - Prototypes for the system control driver. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 816 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __SYSCTL_H__ -#define __SYSCTL_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following are values that can be passed to the -// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(), -// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the -// ulPeripheral parameter. The peripherals in the fourth group (upper nibble -// is 3) can only be used with the SysCtlPeripheralPresent() API. -// -//***************************************************************************** -#define SYSCTL_PERIPH_PWM 0x00100000 // PWM -#define SYSCTL_PERIPH_ADC 0x00010000 // ADC -#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog -#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0 -#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1 -#define SYSCTL_PERIPH_SSI 0x10000010 // SSI -#define SYSCTL_PERIPH_QEI 0x10000100 // QEI -#define SYSCTL_PERIPH_I2C 0x10001000 // I2C -#define SYSCTL_PERIPH_TIMER0 0x10010000 // Timer 0 -#define SYSCTL_PERIPH_TIMER1 0x10020000 // Timer 1 -#define SYSCTL_PERIPH_TIMER2 0x10040000 // Timer 2 -#define SYSCTL_PERIPH_COMP0 0x11000000 // Analog comparator 0 -#define SYSCTL_PERIPH_COMP1 0x12000000 // Analog comparator 1 -#define SYSCTL_PERIPH_COMP2 0x14000000 // Analog comparator 2 -#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A -#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B -#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C -#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D -#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E -#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU -#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor -#define SYSCTL_PERIPH_PLL 0x30000010 // PLL - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlPinPresent() API -// as the ulPin parameter. -// -//***************************************************************************** -#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin -#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin -#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin -#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin -#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin -#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin -#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin -#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin -#define SYSCTL_PIN_C0O 0x00000100 // C0o pin -#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin -#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin -#define SYSCTL_PIN_C1O 0x00000800 // C1o pin -#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin -#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin -#define SYSCTL_PIN_C2O 0x00004000 // C2o pin -#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin -#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin -#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin -#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin -#define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin -#define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin -#define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin -#define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin -#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin -#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin -#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin -#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin -#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin -#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin -#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlLDOSet() API as -// the ulVoltage value, or returned by the SysCtlLDOGet() API. -// -//***************************************************************************** -#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V -#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V -#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V -#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V -#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V -#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V -#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V -#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V -#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V -#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V -#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlLDOConfigSet() API. -// -//***************************************************************************** -#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset -#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlIntEnable(), -// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask -// by the SysCtlIntStatus() API. -// -//***************************************************************************** -#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt -#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt -#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int -#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int -#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt -#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt -#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlResetCauseClear() -// API or returned by the SysCtlResetCauseGet() API. -// -//***************************************************************************** -#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset -#define SYSCTL_CAUSE_SW 0x00000010 // Software reset -#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset -#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset -#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset -#define SYSCTL_CAUSE_EXT 0x00000001 // External reset - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlBrownOutConfigSet() -// API as the ulConfig parameter. -// -//***************************************************************************** -#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting -#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlPWMClockSet() API -// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet() -// API. -// -//***************************************************************************** -#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1 -#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2 -#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4 -#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8 -#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16 -#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32 -#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64 - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlADCSpeedSet() API -// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet() -// API. -// -//***************************************************************************** -#define SYSCTL_ADCSPEED_1MSPS 0x00000300 // 1,000,000 samples per second -#define SYSCTL_ADCSPEED_500KSPS 0x00000200 // 500,000 samples per second -#define SYSCTL_ADCSPEED_250KSPS 0x00000100 // 250,000 samples per second -#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second - -//***************************************************************************** -// -// The following are values that can be passed to the SysCtlClockSet() API as -// the ulConfig parameter. -// -//***************************************************************************** -#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1 -#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2 -#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3 -#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4 -#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5 -#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6 -#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7 -#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8 -#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9 -#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10 -#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11 -#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12 -#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13 -#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14 -#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15 -#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16 -#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock -#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock -#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz -#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz -#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz -#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz -#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz -#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz -#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz -#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz -#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz -#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz -#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz -#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz -#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc -#define SYSCTL_OSC_INT 0x00000010 // Oscillator source is int. osc -#define SYSCTL_OSC_INT4 0x00000020 // Oscillator source is int. osc /4 -#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator -#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern unsigned long SysCtlSRAMSizeGet(void); -extern unsigned long SysCtlFlashSizeGet(void); -extern tBoolean SysCtlPinPresent(unsigned long ulPin); -extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral); -extern void SysCtlPeripheralReset(unsigned long ulPeripheral); -extern void SysCtlPeripheralEnable(unsigned long ulPeripheral); -extern void SysCtlPeripheralDisable(unsigned long ulPeripheral); -extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral); -extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral); -extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral); -extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral); -extern void SysCtlPeripheralClockGating(tBoolean bEnable); -extern void SysCtlIntRegister(void (*pfnHandler)(void)); -extern void SysCtlIntUnregister(void); -extern void SysCtlIntEnable(unsigned long ulInts); -extern void SysCtlIntDisable(unsigned long ulInts); -extern void SysCtlIntClear(unsigned long ulInts); -extern unsigned long SysCtlIntStatus(tBoolean bMasked); -extern void SysCtlLDOSet(unsigned long ulVoltage); -extern unsigned long SysCtlLDOGet(void); -extern void SysCtlLDOConfigSet(unsigned long ulConfig); -extern void SysCtlReset(void); -extern void SysCtlSleep(void); -extern void SysCtlDeepSleep(void); -extern unsigned long SysCtlResetCauseGet(void); -extern void SysCtlResetCauseClear(unsigned long ulCauses); -extern void SysCtlBrownOutConfigSet(unsigned long ulConfig, - unsigned long ulDelay); -extern void SysCtlClockSet(unsigned long ulConfig); -extern unsigned long SysCtlClockGet(void); -extern void SysCtlPWMClockSet(unsigned long ulConfig); -extern unsigned long SysCtlPWMClockGet(void); -extern void SysCtlADCSpeedSet(unsigned long ulSpeed); -extern unsigned long SysCtlADCSpeedGet(void); -extern void SysCtlIOSCVerificationSet(tBoolean bEnable); -extern void SysCtlMOSCVerificationSet(tBoolean bEnable); -extern void SysCtlPLLVerificationSet(tBoolean bEnable); -extern void SysCtlClkVerificationClear(void); - -#ifdef __cplusplus -} -#endif - -#endif // __SYSCTL_H__ diff --git a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/systick.h b/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/systick.h deleted file mode 100644 index beffd88b7..000000000 --- a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/systick.h +++ /dev/null @@ -1,55 +0,0 @@ -//***************************************************************************** -// -// systick.h - Prototypes for the SysTick driver. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 816 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __SYSTICK_H__ -#define __SYSTICK_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void SysTickEnable(void); -extern void SysTickDisable(void); -extern void SysTickIntRegister(void (*pfnHandler)(void)); -extern void SysTickIntUnregister(void); -extern void SysTickIntEnable(void); -extern void SysTickIntDisable(void); -extern void SysTickPeriodSet(unsigned long ulPeriod); -extern unsigned long SysTickPeriodGet(void); -extern unsigned long SysTickValueGet(void); - -#ifdef __cplusplus -} -#endif - -#endif // __SYSTICK_H__ diff --git a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/timer.h b/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/timer.h deleted file mode 100644 index ef98c0d71..000000000 --- a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/timer.h +++ /dev/null @@ -1,137 +0,0 @@ -//***************************************************************************** -// -// timer.h - Prototypes for the timer module -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 816 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __TIMER_H__ -#define __TIMER_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to TimerConfigure as the ulConfig parameter. -// -//***************************************************************************** -#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer -#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer -#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer -#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers -#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer -#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer -#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter -#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer -#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output -#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer -#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer -#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter -#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer -#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output - -//***************************************************************************** -// -// Values that can be passed to TimerIntEnable, TimerIntDisable, and -// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus. -// -//***************************************************************************** -#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt -#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt -#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt -#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask -#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt -#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt -#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt - -//***************************************************************************** -// -// Values that can be passed to TimerControlEvent as the ulEvent parameter. -// -//***************************************************************************** -#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges -#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges -#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges - -//***************************************************************************** -// -// Values that can be passed to most of the timer APIs as the ulTimer -// parameter. -// -//***************************************************************************** -#define TIMER_A 0x000000ff // Timer A -#define TIMER_B 0x0000ff00 // Timer B -#define TIMER_BOTH 0x0000ffff // Timer Both - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer); -extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer); -extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig); -extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, - tBoolean bInvert); -extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, - tBoolean bEnable); -extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulEvent); -extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer, - tBoolean bStall); -extern void TimerRTCEnable(unsigned long ulBase); -extern void TimerRTCDisable(unsigned long ulBase); -extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerPrescaleGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer); -extern unsigned long TimerValueGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerMatchGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, - void (*pfnHandler)(void)); -extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer); -extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags); -extern void TimerQuiesce(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __TIMER_H__ diff --git a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/uart.h b/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/uart.h deleted file mode 100644 index 43eb8d544..000000000 --- a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/uart.h +++ /dev/null @@ -1,102 +0,0 @@ -//***************************************************************************** -// -// uart.h - Defines and Macros for the UART. -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 816 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __UART_H__ -#define __UART_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear -// as the ulIntFlags parameter, and returned from UARTIntStatus. -// -//***************************************************************************** -#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask -#define UART_INT_BE 0x200 // Break Error Interrupt Mask -#define UART_INT_PE 0x100 // Parity Error Interrupt Mask -#define UART_INT_FE 0x080 // Framing Error Interrupt Mask -#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask -#define UART_INT_TX 0x020 // Transmit Interrupt Mask -#define UART_INT_RX 0x010 // Receive Interrupt Mask - -//***************************************************************************** -// -// Values that can be passed to UARTConfigSet as the ulConfig parameter and -// returned by UARTConfigGet in the pulConfig parameter. Additionally, the -// UART_CONFIG_PAR_* subset can be passed to UARTParityModeSet as the ulParity -// parameter, and are returned by UARTParityModeGet. -// -//***************************************************************************** -#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data -#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data -#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data -#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data -#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit -#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits -#define UART_CONFIG_PAR_NONE 0x00000000 // No parity -#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity -#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity -#define UART_CONFIG_PAR_ONE 0x00000086 // Parity bit is one -#define UART_CONFIG_PAR_ZERO 0x00000082 // Parity bit is zero - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity); -extern unsigned long UARTParityModeGet(unsigned long ulBase); -extern void UARTConfigSet(unsigned long ulBase, unsigned long ulBaud, - unsigned long ulConfig); -extern void UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud, - unsigned long *pulConfig); -extern void UARTEnable(unsigned long ulBase); -extern void UARTDisable(unsigned long ulBase); -extern tBoolean UARTCharsAvail(unsigned long ulBase); -extern tBoolean UARTSpaceAvail(unsigned long ulBase); -extern long UARTCharNonBlockingGet(unsigned long ulBase); -extern long UARTCharGet(unsigned long ulBase); -extern tBoolean UARTCharNonBlockingPut(unsigned long ulBase, - unsigned char ucData); -extern void UARTCharPut(unsigned long ulBase, unsigned char ucData); -extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState); -extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); -extern void UARTIntUnregister(unsigned long ulBase); -extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags); - -#ifdef __cplusplus -} -#endif - -#endif // __UART_H__ diff --git a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/watchdog.h b/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/watchdog.h deleted file mode 100644 index ad8bc45ef..000000000 --- a/Demo/CORTEX_LM3S811_KEIL/LuminaryCode/src/watchdog.h +++ /dev/null @@ -1,63 +0,0 @@ -//***************************************************************************** -// -// watchdog.h - Prototypes for the Watchdog Timer API -// -// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's Stellaris Family of microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. Any use in violation -// of the foregoing restrictions may subject the user to criminal sanctions -// under applicable laws, as well as to civil liability for the breach of the -// terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 816 of the Stellaris Driver Library. -// -//***************************************************************************** - -#ifndef __WATCHDOG_H__ -#define __WATCHDOG_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern tBoolean WatchdogRunning(unsigned long ulBase); -extern void WatchdogEnable(unsigned long ulBase); -extern void WatchdogResetEnable(unsigned long ulBase); -extern void WatchdogResetDisable(unsigned long ulBase); -extern void WatchdogLock(unsigned long ulBase); -extern void WatchdogUnlock(unsigned long ulBase); -extern tBoolean WatchdogLockState(unsigned long ulBase); -extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal); -extern unsigned long WatchdogReloadGet(unsigned long ulBase); -extern unsigned long WatchdogValueGet(unsigned long ulBase); -extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); -extern void WatchdogIntUnregister(unsigned long ulBase); -extern void WatchdogIntEnable(unsigned long ulBase); -extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void WatchdogIntClear(unsigned long ulBase); -extern void WatchdogStallDisable(unsigned long ulBase); -extern void WatchdogStallDisable(unsigned long ulBase); - -#ifdef __cplusplus -} -#endif - -#endif // __WATCHDOG_H__ diff --git a/Demo/CORTEX_LM3S811_KEIL/RTOSDemo.Opt b/Demo/CORTEX_LM3S811_KEIL/RTOSDemo.Opt deleted file mode 100644 index a78d564ce..000000000 --- a/Demo/CORTEX_LM3S811_KEIL/RTOSDemo.Opt +++ /dev/null @@ -1,54 +0,0 @@ -### uVision2 Project, (C) Keil Software -### Do not modify ! - - cExt (*.c) - aExt (*.s*; *.src; *.a*) - oExt (*.obj) - lExt (*.lib) - tExt (*.txt; *.h; *.inc) - pExt (*.plm) - CppX (*.cpp) - DaveTm { 0,0,0,0,0,0,0,0 } - -Target (FreeRTOS_Demo), 0x0004 // Tools: 'ARM-ADS' -GRPOPT 1,(Demo_Source),1,0,0 -GRPOPT 2,(Libraries),1,0,0 -GRPOPT 3,(RTOS_Source),1,0,0 -GRPOPT 4,(Documentation),1,0,0 - -OPTFFF 1,1,2,0,0,0,0,0,<.\startup_rvmdk.S> -OPTFFF 1,2,1,167772160,0,0,0,0,<.\LuminaryCode\osram96x16.c> -OPTFFF 1,3,1,0,0,0,0,0,<.\main.c> -OPTFFF 1,4,1,0,0,0,0,0,<..\Common\Minimal\semtest.c> -OPTFFF 1,5,1,989855744,0,0,0,0,<..\Common\Minimal\integer.c> -OPTFFF 1,6,1,939524096,0,0,0,0,<..\Common\Minimal\PollQ.c> -OPTFFF 1,7,1,201326592,0,0,0,0,<..\Common\Minimal\BlockQ.c> -OPTFFF 1,8,1,0,0,0,0,0,<.\heap\heap_1.c> -OPTFFF 2,9,4,0,0,0,0,0, -OPTFFF 3,10,1,0,0,0,0,0,<..\..\Source\tasks.c> -OPTFFF 3,11,1,0,0,0,0,0,<..\..\Source\list.c> -OPTFFF 3,12,1,0,0,0,0,0,<..\..\Source\queue.c> -OPTFFF 3,13,1,0,0,0,0,0,<..\..\Source\portable\RVDS\ARM_CM3\port.c> -OPTFFF 4,14,5,2,0,1,1,0,<.\readme.txt> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,66,0,0,0,99,0,0,0,22,4,0,0,64,2,0,0 } - -ExtF <.\readme.txt> 1,1,0,{ 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,66,0,0,0,99,0,0,0,22,4,0,0,64,2,0,0 } - -TARGOPT 1, (FreeRTOS_Demo) - ADSCLK=50000000 - OPTTT 1,1,1,0 - OPTHX 1,65535,0,0,0 - OPTLX 79,66,8,<.\rvmdk\> - OPTOX 16 - OPTLT 1,1,1,0,1,1,0,1,0,0,0,0 - OPTXL 1,1,1,1,1,1,1,0,0 - OPTFL 1,0,1 - OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S811)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S811) - OPTDBG 48126,4,()()()()()()()()()() (BIN\lmidk-agdi.dll)()()() - OPTKEY 0,(DLGTARM)() - OPTKEY 0,(ARMDBGFLAGS)(-T5F) - OPTKEY 0,(LMIDK-AGDI)(-B0 -O1792) - OPTDF 0x84 - OPTLE <> - OPTLC <> -EndOpt - diff --git a/Demo/CORTEX_LM3S811_KEIL/RTOSDemo.Uv2 b/Demo/CORTEX_LM3S811_KEIL/RTOSDemo.Uv2 deleted file mode 100644 index 737a39bf0..000000000 --- a/Demo/CORTEX_LM3S811_KEIL/RTOSDemo.Uv2 +++ /dev/null @@ -1,113 +0,0 @@ -### uVision2 Project, (C) Keil Software -### Do not modify ! - -Target (FreeRTOS_Demo), 0x0004 // Tools: 'ARM-ADS' - -Group (Demo_Source) -Group (Libraries) -Group (RTOS_Source) -Group (Documentation) - -File 1,2,<.\startup_rvmdk.S> 0x45431C95 -File 1,1,<.\LuminaryCode\osram96x16.c> 0x452BAD20 -File 1,1,<.\main.c> 0x452A35C1 -File 1,1,<..\Common\Minimal\semtest.c> 0x452A35D8 -File 1,1,<..\Common\Minimal\integer.c> 0x452A35D8 -File 1,1,<..\Common\Minimal\PollQ.c> 0x452A35D8 -File 1,1,<..\Common\Minimal\BlockQ.c> 0x4538ECC1 -File 1,1,<.\heap\heap_1.c> 0x45431CD6 -File 2,4, 0x44F892D1 -File 3,1,<..\..\Source\tasks.c> 0x452A35A8 -File 3,1,<..\..\Source\list.c> 0x452A35BA -File 3,1,<..\..\Source\queue.c> 0x452A35BA -File 3,1,<..\..\Source\portable\RVDS\ARM_CM3\port.c> 0x452A35FB -File 4,5,<.\readme.txt> 0x44FC00DA - - -Options 1,0,0 // Target 'FreeRTOS_Demo' - Device (LM3S811) - Vendor (Luminary Micro) - Cpu (IRAM(0x20000000-0x20001fff) IROM(0-0xffff) CLOCK(50000000) CPUTYPE("Cortex-M3")) - FlashUt () - StupF ("STARTUP\Luminary\Startup.s" ("Luminary Startup Code")) - FlashDR (LMIDK-AGDI(-U40296420 -O7 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0LM3S_8 -FS00 -FL02000)) - DevID (4079) - Rgf (LM3Sxxx.H) - Mem () - C () - A () - RL () - OH () - DBC_IFX () - DBC_CMS () - DBC_AMS () - DBC_LMS () - UseEnv=0 - EnvBin () - EnvInc () - EnvLib () - EnvReg (˙Luminary\) - OrgReg (˙Luminary\) - TgStat=16 - OutDir (.\rvmdk\) - OutName (RTOSDemo) - GenApp=1 - GenLib=0 - GenHex=0 - Debug=1 - Browse=1 - LstDir (.\rvmdk\) - HexSel=1 - MG32K=0 - TGMORE=0 - RunUsr 0 0 <> - RunUsr 1 0 <> - BrunUsr 0 0 <> - BrunUsr 1 0 <> - SVCSID <> - GLFLAGS=1790 - ADSFLGA { 176,3,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - ACPUTYP (Cortex-M3) - ADSTFLGA { 0,12,0,0,99,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - OCMADSIRAM { 0,0,0,0,32,0,32,0,0 } - OCMADSIROM { 1,0,0,0,0,0,0,1,0 } - OCMADSXRAM { 0,0,0,0,0,0,0,0,0 } - OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,32,0,0,0,0,0,0,0,0,0,0,0 } - RV_STAVEC () - ADSCCFLG { 9,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - ADSCMISC () - ADSCDEFN (RVDS_ARMCM3_LM3S102) - ADSCUDEF () - ADSCINCD (.;./LuminaryCode;..\..\Source\portable\RVDS\ARM_CM3;..\..\Source\include;..\Common\include) - ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - ADSAMISC () - ADSADEFN () - ADSAUDEF () - ADSAINCD () - PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - IncBld=1 - AlwaysBuild=0 - GenAsm=0 - AsmAsm=0 - PublicsOnly=0 - StopCode=3 - CustArgs () - LibMods () - ADSLDFG { 17,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - ADSLDTA (0x00000000) - ADSLDDA (0x20000000) - ADSLDSC () - ADSLDIB () - ADSLDIC () - ADSLDMC (--entry Reset_Handler --last xHeap) - ADSLDIF () - ADSLDDW () - OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S811)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S811) - OPTDBG 48126,4,()()()()()()()()()() (BIN\lmidk-agdi.dll)()()() - FLASH1 { 1,0,0,0,1,0,0,0,3,0,0,0,0,0,0,0,0,0,0,0 } - FLASH2 (BIN\LMIDK-AGDI.DLL) - FLASH3 ("" ()) - FLASH4 () -EndOpt - diff --git a/Demo/CORTEX_LM3S811_KEIL/heap/heap_1.c b/Demo/CORTEX_LM3S811_KEIL/heap/heap_1.c deleted file mode 100644 index 44b41a102..000000000 --- a/Demo/CORTEX_LM3S811_KEIL/heap/heap_1.c +++ /dev/null @@ -1,120 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - - -/* - * The simplest possible implementation of pvPortMalloc(). Note that this - * implementation does NOT allow allocated memory to be freed again. - * - * See heap_2.c and heap_3.c for alternative implementations, and the memory - * management pages of http://www.FreeRTOS.org for more information. - */ -#include -#include "FreeRTOS.h" -#include "task.h" - -/* Setup the correct byte alignment mask for the defined byte alignment. */ -#if portBYTE_ALIGNMENT == 4 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0003 ) -#endif - -#if portBYTE_ALIGNMENT == 2 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0001 ) -#endif - -#if portBYTE_ALIGNMENT == 1 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0000 ) -#endif - -#ifndef heapBYTE_ALIGNMENT_MASK - #error "Invalid portBYTE_ALIGNMENT definition" -#endif - -/* Allocate the memory for the heap. The struct is used to force byte -alignment without using any non-portable code. */ -extern struct xRTOS_HEAP -{ - unsigned portLONG ulDummy; - unsigned portCHAR ucHeap[ configTOTAL_HEAP_SIZE ]; -} xHeap; - -static size_t xNextFreeByte = ( size_t ) 0; -/*-----------------------------------------------------------*/ - -void *pvPortMalloc( size_t xWantedSize ) -{ -void *pvReturn = NULL; - - /* Ensure that blocks are always aligned to the required number of bytes. */ - #if portBYTE_ALIGNMENT != 1 - if( xWantedSize & heapBYTE_ALIGNMENT_MASK ) - { - /* Byte alignment required. */ - xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & heapBYTE_ALIGNMENT_MASK ) ); - } - #endif - - vTaskSuspendAll(); - { - /* Check there is enough room left for the allocation. */ - if( ( ( xNextFreeByte + xWantedSize ) < configTOTAL_HEAP_SIZE ) && - ( ( xNextFreeByte + xWantedSize ) > xNextFreeByte ) )/* Check for overflow. */ - { - /* Return the next free byte then increment the index past this - block. */ - pvReturn = &( xHeap.ucHeap[ xNextFreeByte ] ); - xNextFreeByte += xWantedSize; - } - } - xTaskResumeAll(); - - return pvReturn; -} -/*-----------------------------------------------------------*/ - -void vPortFree( void *pv ) -{ - /* Memory cannot be freed using this scheme. See heap_2.c and heap_3.c - for alternative implementations, and the memory management pages of - http://www.FreeRTOS.org for more information. */ - ( void ) pv; -} -/*-----------------------------------------------------------*/ - -void vPortInitialiseBlocks( void ) -{ - /* Only required when static memory is not cleared. */ - xNextFreeByte = ( size_t ) 0; -} - - diff --git a/Demo/CORTEX_LM3S811_KEIL/main.c b/Demo/CORTEX_LM3S811_KEIL/main.c deleted file mode 100644 index 9e03b9e03..000000000 --- a/Demo/CORTEX_LM3S811_KEIL/main.c +++ /dev/null @@ -1,362 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/* - * This project contains an application demonstrating the use of the - * FreeRTOS.org mini real time scheduler on the Luminary Micro LM3S811 Eval - * board. See http://www.FreeRTOS.org for more information. - * - * main() simply sets up the hardware, creates all the demo application tasks, - * then starts the scheduler. http://www.freertos.org/a00102.html provides - * more information on the standard demo tasks. - * - * In addition to a subset of the standard demo application tasks, main.c also - * defines the following tasks: - * - * + A 'Print' task. The print task is the only task permitted to access the - * LCD - thus ensuring mutual exclusion and consistent access to the resource. - * Other tasks do not access the LCD directly, but instead send the text they - * wish to display to the print task. The print task spends most of its time - * blocked - only waking when a message is queued for display. - * - * + A 'Button handler' task. The eval board contains a user push button that - * is configured to generate interrupts. The interrupt handler uses a - * semaphore to wake the button handler task - demonstrating how the priority - * mechanism can be used to defer interrupt processing to the task level. The - * button handler task sends a message both to the LCD (via the print task) and - * the UART where it can be viewed using a dumb terminal (via the UART to USB - * converter on the eval board). NOTES: The dumb terminal must be closed in - * order to reflash the microcontroller. A very basic interrupt driven UART - * driver is used that does not use the FIFO. 19200 baud is used. - * - * + A 'check' task. The check task only executes every five seconds but has a - * high priority so is guaranteed to get processor time. Its function is to - * check that all the other tasks are still operational and that no errors have - * been detected at any time. If no errors have every been detected 'PASS' is - * written to the display (via the print task) - if an error has ever been - * detected the message is changed to 'FAIL'. The position of the message is - * changed for each write. - */ - - - -/* Environment includes. */ -#include "DriverLib.h" - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" -#include "semphr.h" - -/* Demo app includes. */ -#include "integer.h" -#include "PollQ.h" -#include "semtest.h" -#include "BlockQ.h" - -/* Delay between cycles of the 'check' task. */ -#define mainCHECK_DELAY ( ( portTickType ) 5000 / portTICK_RATE_MS ) - -/* UART configuration - note this does not use the FIFO so is not very -efficient. */ -#define mainBAUD_RATE ( 19200 ) -#define mainFIFO_SET ( 0x10 ) - -/* Demo task priorities. */ -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) - -/* Demo board specifics. */ -#define mainPUSH_BUTTON GPIO_PIN_4 - -/* Misc. */ -#define mainQUEUE_SIZE ( 3 ) -#define mainDEBOUNCE_DELAY ( ( portTickType ) 150 / portTICK_RATE_MS ) -#define mainNO_DELAY ( ( portTickType ) 0 ) -/* - * Configure the processor and peripherals for this demo. - */ -static void prvSetupHardware( void ); - -/* - * The 'check' task, as described at the top of this file. - */ -static void vCheckTask( void *pvParameters ); - -/* - * The task that is woken by the ISR that processes GPIO interrupts originating - * from the push button. - */ -static void vButtonHandlerTask( void *pvParameters ); - -/* - * The task that controls access to the LCD. - */ -static void vPrintTask( void *pvParameter ); - -/* String that is transmitted on the UART. */ -static portCHAR *cMessage = "Task woken by button interrupt! --- "; -static volatile portCHAR *pcNextChar; - -/* The semaphore used to wake the button handler task from within the GPIO -interrupt handler. */ -xSemaphoreHandle xButtonSemaphore; - -/* The queue used to send strings to the print task for display on the LCD. */ -xQueueHandle xPrintQueue; - -/*-----------------------------------------------------------*/ - -int main( void ) -{ - /* Configure the clocks, UART and GPIO. */ - prvSetupHardware(); - - /* Create the semaphore used to wake the button handler task from the GPIO - ISR. */ - vSemaphoreCreateBinary( xButtonSemaphore ); - xSemaphoreTake( xButtonSemaphore, 0 ); - - /* Create the queue used to pass message to vPrintTask. */ - xPrintQueue = xQueueCreate( mainQUEUE_SIZE, sizeof( portCHAR * ) ); - - /* Start the standard demo tasks. */ - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - - /* Start the tasks defined within the file. */ - xTaskCreate( vCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - xTaskCreate( vButtonHandlerTask, "Status", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY + 1, NULL ); - xTaskCreate( vPrintTask, "Print", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL ); - - /* Start the scheduler. */ - vTaskStartScheduler(); - - /* Will only get here if there was insufficient heap to start the - scheduler. */ - - return 0; -} -/*-----------------------------------------------------------*/ - -static void vCheckTask( void *pvParameters ) -{ -portBASE_TYPE xErrorOccurred = pdFALSE; -portTickType xLastExecutionTime; -const portCHAR *pcPassMessage = "PASS"; -const portCHAR *pcFailMessage = "FAIL"; - - /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() - works correctly. */ - xLastExecutionTime = xTaskGetTickCount(); - - for( ;; ) - { - /* Perform this check every mainCHECK_DELAY milliseconds. */ - vTaskDelayUntil( &xLastExecutionTime, mainCHECK_DELAY ); - - /* Has an error been found in any task? */ - - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - xErrorOccurred = pdTRUE; - } - - if( xArePollingQueuesStillRunning() != pdTRUE ) - { - xErrorOccurred = pdTRUE; - } - - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - xErrorOccurred = pdTRUE; - } - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - xErrorOccurred = pdTRUE; - } - - /* Send either a pass or fail message. If an error is found it is - never cleared again. We do not write directly to the LCD, but instead - queue a message for display by the print task. */ - if( xErrorOccurred == pdTRUE ) - { - xQueueSend( xPrintQueue, &pcFailMessage, portMAX_DELAY ); - } - else - { - xQueueSend( xPrintQueue, &pcPassMessage, portMAX_DELAY ); - } - } -} -/*-----------------------------------------------------------*/ - -static void prvSetupHardware( void ) -{ - /* Setup the PLL. */ - SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ ); - - /* Setup the push button. */ - SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC); - GPIODirModeSet(GPIO_PORTC_BASE, mainPUSH_BUTTON, GPIO_DIR_MODE_IN); - GPIOIntTypeSet( GPIO_PORTC_BASE, mainPUSH_BUTTON,GPIO_FALLING_EDGE ); - GPIOPinIntEnable( GPIO_PORTC_BASE, mainPUSH_BUTTON ); - IntEnable( INT_GPIOC ); - - - - /* Enable the UART. */ - SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); - SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); - - /* Set GPIO A0 and A1 as peripheral function. They are used to output the - UART signals. */ - GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); - - /* Configure the UART for 8-N-1 operation. */ - UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); - - /* We don't want to use the fifo. This is for test purposes to generate - as many interrupts as possible. */ - HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET; - - /* Enable Tx interrupts. */ - HWREG( UART0_BASE + UART_O_IM ) |= UART_INT_TX; - IntEnable( INT_UART0 ); - - - /* Initialise the LCD> */ - OSRAMInit( false ); - OSRAMStringDraw("www.FreeRTOS.org", 0, 0); - OSRAMStringDraw("LM3S811 demo", 16, 1); -} -/*-----------------------------------------------------------*/ - -static void vButtonHandlerTask( void *pvParameters ) -{ -const portCHAR *pcInterruptMessage = "Int"; - - for( ;; ) - { - /* Wait for a GPIO interrupt to wake this task. */ - while( xSemaphoreTake( xButtonSemaphore, portMAX_DELAY ) != pdPASS ); - - /* Start the Tx of the message on the UART. */ - UARTIntDisable( UART0_BASE, UART_INT_TX ); - { - pcNextChar = cMessage; - - /* Send the first character. */ - if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) - { - HWREG( UART0_BASE + UART_O_DR ) = *pcNextChar; - } - - pcNextChar++; - } - UARTIntEnable(UART0_BASE, UART_INT_TX); - - /* Queue a message for the print task to display on the LCD. */ - xQueueSend( xPrintQueue, &pcInterruptMessage, portMAX_DELAY ); - - /* Make sure we don't process bounces. */ - vTaskDelay( mainDEBOUNCE_DELAY ); - xSemaphoreTake( xButtonSemaphore, mainNO_DELAY ); - } -} - -/*-----------------------------------------------------------*/ - -void vUART_ISR(void) -{ -unsigned portLONG ulStatus; - - /* What caused the interrupt. */ - ulStatus = UARTIntStatus( UART0_BASE, pdTRUE ); - - /* Clear the interrupt. */ - UARTIntClear( UART0_BASE, ulStatus ); - - /* Was a Tx interrupt pending? */ - if( ulStatus & UART_INT_TX ) - { - /* Send the next character in the string. We are not using the FIFO. */ - if( *pcNextChar != NULL ) - { - if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) ) - { - HWREG( UART0_BASE + UART_O_DR ) = *pcNextChar; - } - pcNextChar++; - } - } -} -/*-----------------------------------------------------------*/ - -void vGPIO_ISR( void ) -{ - /* Clear the interrupt. */ - GPIOPinIntClear(GPIO_PORTC_BASE, mainPUSH_BUTTON); - - /* Wake the button handler task. */ - if( xSemaphoreGiveFromISR( xButtonSemaphore, pdFALSE ) ) - { - portEND_SWITCHING_ISR( pdTRUE ); - } -} -/*-----------------------------------------------------------*/ - -static void vPrintTask( void *pvParameters ) -{ -portCHAR *pcMessage; -unsigned portBASE_TYPE uxLine = 0, uxRow = 0; - - for( ;; ) - { - /* Wait for a message to arrive. */ - xQueueReceive( xPrintQueue, &pcMessage, portMAX_DELAY ); - - /* Write the message to the LCD. */ - uxRow++; - uxLine++; - OSRAMClear(); - OSRAMStringDraw( pcMessage, uxLine & 0x3f, uxRow & 0x01); - } -} - diff --git a/Demo/CORTEX_LM3S811_KEIL/readme.txt b/Demo/CORTEX_LM3S811_KEIL/readme.txt deleted file mode 100644 index 371a25b70..000000000 --- a/Demo/CORTEX_LM3S811_KEIL/readme.txt +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This project contains an application demonstrating the use of the - * FreeRTOS.org mini real time scheduler on the Luminary Micro LM3S811 Eval - * board. See http://www.FreeRTOS.org for more information. - * - * main() simply sets up the hardware, creates all the demo application tasks, - * then starts the scheduler. http://www.freertos.org/a00102.html provides - * more information on the standard demo tasks. - * - * In addition to a subset of the standard demo application tasks, main.c also - * defines the following tasks: - * - * + A 'Print' task. The print task is the only task permitted to access the - * LCD - thus ensuring mutual exclusion and consistent access to the resource. - * Other tasks do not access the LCD directly, but instead send the text they - * wish to display to the print task. The print task spends most of its time - * blocked - only waking when a message is queued for display. - * - * + A 'Button handler' task. The eval board contains a user push button that - * is configured to generate interrupts. The interrupt handler uses a - * semaphore to wake the button handler task - demonstrating how the priority - * mechanism can be used to defer interrupt processing to the task level. The - * button handler task sends a message both to the LCD (via the print task) and - * the UART where it can be viewed using a dumb terminal (via the UART to USB - * converter on the eval board). NOTES: The dumb terminal must be closed in - * order to reflash the microcontroller. A very basic interrupt driven UART - * driver is used that does not use the FIFO. 19200 baud is used. - * - * + A 'check' task. The check task only executes every five seconds but has a - * high priority so is guaranteed to get processor time. Its function is to - * check that all the other tasks are still operational and that no errors have - * been detected at any time. If no errors have every been detected 'PASS' is - * written to the display (via the print task) - if an error has ever been - * detected the message is changed to 'FAIL'. The position of the message is - * changed for each write. - */ \ No newline at end of file diff --git a/Demo/CORTEX_LM3S811_KEIL/startup_rvmdk.S b/Demo/CORTEX_LM3S811_KEIL/startup_rvmdk.S deleted file mode 100644 index e22c13e83..000000000 --- a/Demo/CORTEX_LM3S811_KEIL/startup_rvmdk.S +++ /dev/null @@ -1,238 +0,0 @@ -; <<< Use Configuration Wizard in Context Menu >>> -;****************************************************************************** -; -; startup_rvmdk.S - Startup code for Stellaris. -; -; Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. -; -; Software License Agreement -; -; Luminary Micro, Inc. (LMI) is supplying this software for use solely and -; exclusively on LMI's Stellaris Family of microcontroller products. -; -; The software is owned by LMI and/or its suppliers, and is protected under -; applicable copyright laws. All rights are reserved. Any use in violation of -; the foregoing restrictions may subject the user to criminal sanctions under -; applicable laws, as well as to civil liability for the breach of the terms -; and conditions of this license. -; -; THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; -; This is part of revision 816 of the Stellaris Driver Library. -; -;****************************************************************************** - -;****************************************************************************** -; -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; -; -;****************************************************************************** -Stack EQU 0x00000100 - -;****************************************************************************** -; -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; -; -;****************************************************************************** -Heap EQU 0x00000000 - -;****************************************************************************** -; -; Allocate space for the stack. -; -;****************************************************************************** - AREA STACK, NOINIT, READWRITE, ALIGN=3 -StackMem - SPACE Stack - -;****************************************************************************** -; -; Allocate space for the heap. -; -;****************************************************************************** - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -HeapMem - SPACE Heap - -;****************************************************************************** -; -; Indicate that the code in this file preserves 8-byte alignment of the stack. -; -;****************************************************************************** - PRESERVE8 - -;****************************************************************************** -; -; Place code into the reset code section. -; -;****************************************************************************** - AREA RESET, CODE, READONLY - THUMB - -;****************************************************************************** -; -; The vector table. -; -;****************************************************************************** -Vectors - DCD StackMem + Stack ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NmiSR ; NMI Handler - DCD FaultISR ; Hard Fault Handler - DCD IntDefaultHandler ; MPU Fault Handler - DCD IntDefaultHandler ; Bus Fault Handler - DCD IntDefaultHandler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD IntDefaultHandler ; SVCall Handler - DCD IntDefaultHandler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD xPortPendSVHandler ; PendSV Handler - DCD xPortSysTickHandler ; SysTick Handler - DCD IntDefaultHandler ; GPIO Port A - DCD IntDefaultHandler ; GPIO Port B - DCD vGPIO_ISR ; GPIO Port C - DCD IntDefaultHandler ; GPIO Port D - DCD IntDefaultHandler ; GPIO Port E - DCD vUART_ISR ; UART0 - DCD IntDefaultHandler ; UART1 - DCD IntDefaultHandler ; SSI - DCD IntDefaultHandler ; I2C - DCD IntDefaultHandler ; PWM Fault - DCD IntDefaultHandler ; PWM Generator 0 - DCD IntDefaultHandler ; PWM Generator 1 - DCD IntDefaultHandler ; PWM Generator 2 - DCD IntDefaultHandler ; Quadrature Encoder - DCD IntDefaultHandler ; ADC Sequence 0 - DCD IntDefaultHandler ; ADC Sequence 1 - DCD IntDefaultHandler ; ADC Sequence 2 - DCD IntDefaultHandler ; ADC Sequence 3 - DCD IntDefaultHandler ; Watchdog - DCD IntDefaultHandler ; Timer 0A - DCD IntDefaultHandler ; Timer 0B - DCD IntDefaultHandler ; Timer 1A - DCD IntDefaultHandler ; Timer 1B - DCD IntDefaultHandler ; Timer 2A - DCD IntDefaultHandler ; Timer 2B - DCD IntDefaultHandler ; Comp 0 - DCD IntDefaultHandler ; Comp 1 - DCD IntDefaultHandler ; Comp 2 - DCD IntDefaultHandler ; System Control - DCD IntDefaultHandler ; Flash Control - -;****************************************************************************** -; -; This is the code that gets called when the processor first starts execution -; following a reset event. -; -;****************************************************************************** - EXPORT Reset_Handler -Reset_Handler - ; - ; Call __main() in the C library, which will call the application - ; supplied main(). - ; - IMPORT __main - IMPORT vGPIO_ISR - IMPORT vUART_ISR - IMPORT xPortPendSVHandler - IMPORT xPortSysTickHandler - - LDR R0, =__main - BX R0 - -;****************************************************************************** -; -; This is the code that gets called when the processor receives a NMI. This -; simply enters an infinite loop, preserving the system state for examination -; by a debugger. -; -;****************************************************************************** -NmiSR - B NmiSR - -;****************************************************************************** -; -; This is the code that gets called when the processor receives a fault -; interrupt. This simply enters an infinite loop, preserving the system state -; for examination by a debugger. -; -;****************************************************************************** -FaultISR - B FaultISR - -;****************************************************************************** -; -; This is the code that gets called when the processor receives an unexpected -; interrupt. This simply enters an infinite loop, preserving the system state -; for examination by a debugger. -; -;****************************************************************************** -IntDefaultHandler - B IntDefaultHandler - -;****************************************************************************** -; -; Make sure the end of this section is aligned. -; -;****************************************************************************** - ALIGN - -;****************************************************************************** -; -; Some code in the normal code section for initializing the heap and stack. -; -;****************************************************************************** - AREA |.text|, CODE, READONLY - -;****************************************************************************** -; -; The function expected of the C library startup code for defining the stack -; and heap memory locations. -; -;****************************************************************************** - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - LDR R0, =HeapMem - LDR R1, =(StackMem + Stack) - LDR R2, =(HeapMem + Heap) - LDR R3, =StackMem - BX LR - -;****************************************************************************** -; -; Make sure the end of this section is aligned. -; -;****************************************************************************** - ALIGN - -; Note: -; Using READWRITE places Section .RTOSHeap in Region ER_RW. -; Using NOINIT places Section .RTOSHeap in Region ER_ZI,which means -; "ZEROINITIALIZE" (sic), and which is the last region in memory. Then -; we need to make this section the last section, which is somewhat tricky, -; because we cannot use the sectionname, but need to use a defined symbol: -; Linker option: "--last xHeap" - - EXPORT xHeap - - AREA RTOSHeap, DATA, NOINIT -xHeap - -;****************************************************************************** -; -; Tell the assembler that we're done. -; -;****************************************************************************** - END diff --git a/Demo/Common/Full/BlockQ.c b/Demo/Common/Full/BlockQ.c deleted file mode 100644 index 1edcc2342..000000000 --- a/Demo/Common/Full/BlockQ.c +++ /dev/null @@ -1,313 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/** - * Creates six tasks that operate on three queues as follows: - * - * The first two tasks send and receive an incrementing number to/from a queue. - * One task acts as a producer and the other as the consumer. The consumer is a - * higher priority than the producer and is set to block on queue reads. The queue - * only has space for one item - as soon as the producer posts a message on the - * queue the consumer will unblock, pre-empt the producer, and remove the item. - * - * The second two tasks work the other way around. Again the queue used only has - * enough space for one item. This time the consumer has a lower priority than the - * producer. The producer will try to post on the queue blocking when the queue is - * full. When the consumer wakes it will remove the item from the queue, causing - * the producer to unblock, pre-empt the consumer, and immediately re-fill the - * queue. - * - * The last two tasks use the same queue producer and consumer functions. This time the queue has - * enough space for lots of items and the tasks operate at the same priority. The - * producer will execute, placing items into the queue. The consumer will start - * executing when either the queue becomes full (causing the producer to block) or - * a context switch occurs (tasks of the same priority will time slice). - * - * \page BlockQC blockQ.c - * \ingroup DemoFiles - *
- */ - -/* -Changes from V1.00: - - + Reversed the priority and block times of the second two demo tasks so - they operate as per the description above. - -Changes from V2.0.0 - - + Delay periods are now specified using variables and constants of - portTickType rather than unsigned portLONG. - -Changes from V4.0.2 - - + The second set of tasks were created the wrong way around. This has been - corrected. -*/ - - -#include - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" - -/* Demo program include files. */ -#include "BlockQ.h" -#include "print.h" - -#define blckqSTACK_SIZE ( ( unsigned portSHORT ) 128 ) -#define blckqNUM_TASK_SETS ( 3 ) - -/* Structure used to pass parameters to the blocking queue tasks. */ -typedef struct BLOCKING_QUEUE_PARAMETERS -{ - xQueueHandle xQueue; /*< The queue to be used by the task. */ - portTickType xBlockTime; /*< The block time to use on queue reads/writes. */ - volatile portSHORT *psCheckVariable; /*< Incremented on each successful cycle to check the task is still running. */ -} xBlockingQueueParameters; - -/* Task function that creates an incrementing number and posts it on a queue. */ -static void vBlockingQueueProducer( void *pvParameters ); - -/* Task function that removes the incrementing number from a queue and checks that -it is the expected number. */ -static void vBlockingQueueConsumer( void *pvParameters ); - -/* Variables which are incremented each time an item is removed from a queue, and -found to be the expected value. -These are used to check that the tasks are still running. */ -static volatile portSHORT sBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( portSHORT ) 0, ( portSHORT ) 0, ( portSHORT ) 0 }; - -/* Variable which are incremented each time an item is posted on a queue. These -are used to check that the tasks are still running. */ -static volatile portSHORT sBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( portSHORT ) 0, ( portSHORT ) 0, ( portSHORT ) 0 }; - -/*-----------------------------------------------------------*/ - -void vStartBlockingQueueTasks( unsigned portBASE_TYPE uxPriority ) -{ -xBlockingQueueParameters *pxQueueParameters1, *pxQueueParameters2; -xBlockingQueueParameters *pxQueueParameters3, *pxQueueParameters4; -xBlockingQueueParameters *pxQueueParameters5, *pxQueueParameters6; -const unsigned portBASE_TYPE uxQueueSize1 = 1, uxQueueSize5 = 5; -const portTickType xBlockTime = ( portTickType ) 1000 / portTICK_RATE_MS; -const portTickType xDontBlock = ( portTickType ) 0; - - /* Create the first two tasks as described at the top of the file. */ - - /* First create the structure used to pass parameters to the consumer tasks. */ - pxQueueParameters1 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); - - /* Create the queue used by the first two tasks to pass the incrementing number. - Pass a pointer to the queue in the parameter structure. */ - pxQueueParameters1->xQueue = xQueueCreate( uxQueueSize1, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) ); - - /* The consumer is created first so gets a block time as described above. */ - pxQueueParameters1->xBlockTime = xBlockTime; - - /* Pass in the variable that this task is going to increment so we can check it - is still running. */ - pxQueueParameters1->psCheckVariable = &( sBlockingConsumerCount[ 0 ] ); - - /* Create the structure used to pass parameters to the producer task. */ - pxQueueParameters2 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); - - /* Pass the queue to this task also, using the parameter structure. */ - pxQueueParameters2->xQueue = pxQueueParameters1->xQueue; - - /* The producer is not going to block - as soon as it posts the consumer will - wake and remove the item so the producer should always have room to post. */ - pxQueueParameters2->xBlockTime = xDontBlock; - - /* Pass in the variable that this task is going to increment so we can check - it is still running. */ - pxQueueParameters2->psCheckVariable = &( sBlockingProducerCount[ 0 ] ); - - - /* Note the producer has a lower priority than the consumer when the tasks are - spawned. */ - xTaskCreate( vBlockingQueueConsumer, "QConsB1", blckqSTACK_SIZE, ( void * ) pxQueueParameters1, uxPriority, NULL ); - xTaskCreate( vBlockingQueueProducer, "QProdB2", blckqSTACK_SIZE, ( void * ) pxQueueParameters2, tskIDLE_PRIORITY, NULL ); - - - - /* Create the second two tasks as described at the top of the file. This uses - the same mechanism but reverses the task priorities. */ - - pxQueueParameters3 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); - pxQueueParameters3->xQueue = xQueueCreate( uxQueueSize1, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) ); - pxQueueParameters3->xBlockTime = xDontBlock; - pxQueueParameters3->psCheckVariable = &( sBlockingProducerCount[ 1 ] ); - - pxQueueParameters4 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); - pxQueueParameters4->xQueue = pxQueueParameters3->xQueue; - pxQueueParameters4->xBlockTime = xBlockTime; - pxQueueParameters4->psCheckVariable = &( sBlockingConsumerCount[ 1 ] ); - - xTaskCreate( vBlockingQueueProducer, "QProdB3", blckqSTACK_SIZE, ( void * ) pxQueueParameters3, tskIDLE_PRIORITY, NULL ); - xTaskCreate( vBlockingQueueConsumer, "QConsB4", blckqSTACK_SIZE, ( void * ) pxQueueParameters4, uxPriority, NULL ); - - - - /* Create the last two tasks as described above. The mechanism is again just - the same. This time both parameter structures are given a block time. */ - pxQueueParameters5 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); - pxQueueParameters5->xQueue = xQueueCreate( uxQueueSize5, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) ); - pxQueueParameters5->xBlockTime = xBlockTime; - pxQueueParameters5->psCheckVariable = &( sBlockingProducerCount[ 2 ] ); - - pxQueueParameters6 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); - pxQueueParameters6->xQueue = pxQueueParameters5->xQueue; - pxQueueParameters6->xBlockTime = xBlockTime; - pxQueueParameters6->psCheckVariable = &( sBlockingConsumerCount[ 2 ] ); - - xTaskCreate( vBlockingQueueProducer, "QProdB5", blckqSTACK_SIZE, ( void * ) pxQueueParameters5, tskIDLE_PRIORITY, NULL ); - xTaskCreate( vBlockingQueueConsumer, "QConsB6", blckqSTACK_SIZE, ( void * ) pxQueueParameters6, tskIDLE_PRIORITY, NULL ); -} -/*-----------------------------------------------------------*/ - -static void vBlockingQueueProducer( void *pvParameters ) -{ -unsigned portSHORT usValue = 0; -xBlockingQueueParameters *pxQueueParameters; -const portCHAR * const pcTaskStartMsg = "Blocking queue producer started.\r\n"; -const portCHAR * const pcTaskErrorMsg = "Could not post on blocking queue\r\n"; -portSHORT sErrorEverOccurred = pdFALSE; - - pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters; - - /* Queue a message for printing to say the task has started. */ - vPrintDisplayMessage( &pcTaskStartMsg ); - - for( ;; ) - { - if( xQueueSend( pxQueueParameters->xQueue, ( void * ) &usValue, pxQueueParameters->xBlockTime ) != pdPASS ) - { - vPrintDisplayMessage( &pcTaskErrorMsg ); - sErrorEverOccurred = pdTRUE; - } - else - { - /* We have successfully posted a message, so increment the variable - used to check we are still running. */ - if( sErrorEverOccurred == pdFALSE ) - { - ( *pxQueueParameters->psCheckVariable )++; - } - - /* Increment the variable we are going to post next time round. The - consumer will expect the numbers to follow in numerical order. */ - ++usValue; - } - } -} -/*-----------------------------------------------------------*/ - -static void vBlockingQueueConsumer( void *pvParameters ) -{ -unsigned portSHORT usData, usExpectedValue = 0; -xBlockingQueueParameters *pxQueueParameters; -const portCHAR * const pcTaskStartMsg = "Blocking queue consumer started.\r\n"; -const portCHAR * const pcTaskErrorMsg = "Incorrect value received on blocking queue.\r\n"; -portSHORT sErrorEverOccurred = pdFALSE; - - /* Queue a message for printing to say the task has started. */ - vPrintDisplayMessage( &pcTaskStartMsg ); - - pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters; - - for( ;; ) - { - if( xQueueReceive( pxQueueParameters->xQueue, &usData, pxQueueParameters->xBlockTime ) == pdPASS ) - { - if( usData != usExpectedValue ) - { - vPrintDisplayMessage( &pcTaskErrorMsg ); - - /* Catch-up. */ - usExpectedValue = usData; - - sErrorEverOccurred = pdTRUE; - } - else - { - /* We have successfully received a message, so increment the - variable used to check we are still running. */ - if( sErrorEverOccurred == pdFALSE ) - { - ( *pxQueueParameters->psCheckVariable )++; - } - - /* Increment the value we expect to remove from the queue next time - round. */ - ++usExpectedValue; - } - } - } -} -/*-----------------------------------------------------------*/ - -/* This is called to check that all the created tasks are still running. */ -portBASE_TYPE xAreBlockingQueuesStillRunning( void ) -{ -static portSHORT sLastBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( portSHORT ) 0, ( portSHORT ) 0, ( portSHORT ) 0 }; -static portSHORT sLastBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( portSHORT ) 0, ( portSHORT ) 0, ( portSHORT ) 0 }; -portBASE_TYPE xReturn = pdPASS, xTasks; - - /* Not too worried about mutual exclusion on these variables as they are 16 - bits and we are only reading them. We also only care to see if they have - changed or not. - - Loop through each check variable and return pdFALSE if any are found not - to have changed since the last call. */ - - for( xTasks = 0; xTasks < blckqNUM_TASK_SETS; xTasks++ ) - { - if( sBlockingConsumerCount[ xTasks ] == sLastBlockingConsumerCount[ xTasks ] ) - { - xReturn = pdFALSE; - } - sLastBlockingConsumerCount[ xTasks ] = sBlockingConsumerCount[ xTasks ]; - - - if( sBlockingProducerCount[ xTasks ] == sLastBlockingProducerCount[ xTasks ] ) - { - xReturn = pdFALSE; - } - sLastBlockingProducerCount[ xTasks ] = sBlockingProducerCount[ xTasks ]; - } - - return xReturn; -} - diff --git a/Demo/Common/Full/PollQ.c b/Demo/Common/Full/PollQ.c deleted file mode 100644 index a384dea49..000000000 --- a/Demo/Common/Full/PollQ.c +++ /dev/null @@ -1,225 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/** - * This is a very simple queue test. See the BlockQ. c documentation for a more - * comprehensive version. - * - * Creates two tasks that communicate over a single queue. One task acts as a - * producer, the other a consumer. - * - * The producer loops for three iteration, posting an incrementing number onto the - * queue each cycle. It then delays for a fixed period before doing exactly the - * same again. - * - * The consumer loops emptying the queue. Each item removed from the queue is - * checked to ensure it contains the expected value. When the queue is empty it - * blocks for a fixed period, then does the same again. - * - * All queue access is performed without blocking. The consumer completely empties - * the queue each time it runs so the producer should never find the queue full. - * - * An error is flagged if the consumer obtains an unexpected value or the producer - * find the queue is full. - * - * \page PollQC pollQ.c - * \ingroup DemoFiles - *
- */ - -/* -Changes from V2.0.0 - - + Delay periods are now specified using variables and constants of - portTickType rather than unsigned portLONG. -*/ - -#include - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" -#include "print.h" - -/* Demo program include files. */ -#include "PollQ.h" - -#define pollqSTACK_SIZE ( ( unsigned portSHORT ) 128 ) - -/* The task that posts the incrementing number onto the queue. */ -static void vPolledQueueProducer( void *pvParameters ); - -/* The task that empties the queue. */ -static void vPolledQueueConsumer( void *pvParameters ); - -/* Variables that are used to check that the tasks are still running with no errors. */ -static volatile portSHORT sPollingConsumerCount = 0, sPollingProducerCount = 0; -/*-----------------------------------------------------------*/ - -void vStartPolledQueueTasks( unsigned portBASE_TYPE uxPriority ) -{ -static xQueueHandle xPolledQueue; -const unsigned portBASE_TYPE uxQueueSize = 10; - - /* Create the queue used by the producer and consumer. */ - xPolledQueue = xQueueCreate( uxQueueSize, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) ); - - /* Spawn the producer and consumer. */ - xTaskCreate( vPolledQueueConsumer, "QConsNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, NULL ); - xTaskCreate( vPolledQueueProducer, "QProdNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, NULL ); -} -/*-----------------------------------------------------------*/ - -static void vPolledQueueProducer( void *pvParameters ) -{ -unsigned portSHORT usValue = 0, usLoop; -xQueueHandle *pxQueue; -const portTickType xDelay = ( portTickType ) 200 / portTICK_RATE_MS; -const unsigned portSHORT usNumToProduce = 3; -const portCHAR * const pcTaskStartMsg = "Polled queue producer started.\r\n"; -const portCHAR * const pcTaskErrorMsg = "Could not post on polled queue.\r\n"; -portSHORT sError = pdFALSE; - - /* Queue a message for printing to say the task has started. */ - vPrintDisplayMessage( &pcTaskStartMsg ); - - /* The queue being used is passed in as the parameter. */ - pxQueue = ( xQueueHandle * ) pvParameters; - - for( ;; ) - { - for( usLoop = 0; usLoop < usNumToProduce; ++usLoop ) - { - /* Send an incrementing number on the queue without blocking. */ - if( xQueueSend( *pxQueue, ( void * ) &usValue, ( portTickType ) 0 ) != pdPASS ) - { - /* We should never find the queue full - this is an error. */ - vPrintDisplayMessage( &pcTaskErrorMsg ); - sError = pdTRUE; - } - else - { - if( sError == pdFALSE ) - { - /* If an error has ever been recorded we stop incrementing the - check variable. */ - ++sPollingProducerCount; - } - - /* Update the value we are going to post next time around. */ - ++usValue; - } - } - - /* Wait before we start posting again to ensure the consumer runs and - empties the queue. */ - vTaskDelay( xDelay ); - } -} -/*-----------------------------------------------------------*/ - -static void vPolledQueueConsumer( void *pvParameters ) -{ -unsigned portSHORT usData, usExpectedValue = 0; -xQueueHandle *pxQueue; -const portTickType xDelay = ( portTickType ) 200 / portTICK_RATE_MS; -const portCHAR * const pcTaskStartMsg = "Polled queue consumer started.\r\n"; -const portCHAR * const pcTaskErrorMsg = "Incorrect value received on polled queue.\r\n"; -portSHORT sError = pdFALSE; - - /* Queue a message for printing to say the task has started. */ - vPrintDisplayMessage( &pcTaskStartMsg ); - - /* The queue being used is passed in as the parameter. */ - pxQueue = ( xQueueHandle * ) pvParameters; - - for( ;; ) - { - /* Loop until the queue is empty. */ - while( uxQueueMessagesWaiting( *pxQueue ) ) - { - if( xQueueReceive( *pxQueue, &usData, ( portTickType ) 0 ) == pdPASS ) - { - if( usData != usExpectedValue ) - { - /* This is not what we expected to receive so an error has - occurred. */ - vPrintDisplayMessage( &pcTaskErrorMsg ); - sError = pdTRUE; - /* Catch-up to the value we received so our next expected value - should again be correct. */ - usExpectedValue = usData; - } - else - { - if( sError == pdFALSE ) - { - /* Only increment the check variable if no errors have - occurred. */ - ++sPollingConsumerCount; - } - } - ++usExpectedValue; - } - } - - /* Now the queue is empty we block, allowing the producer to place more - items in the queue. */ - vTaskDelay( xDelay ); - } -} -/*-----------------------------------------------------------*/ - -/* This is called to check that all the created tasks are still running with no errors. */ -portBASE_TYPE xArePollingQueuesStillRunning( void ) -{ -static portSHORT sLastPollingConsumerCount = 0, sLastPollingProducerCount = 0; -portBASE_TYPE xReturn; - - if( ( sLastPollingConsumerCount == sPollingConsumerCount ) || - ( sLastPollingProducerCount == sPollingProducerCount ) - ) - { - xReturn = pdFALSE; - } - else - { - xReturn = pdTRUE; - } - - sLastPollingConsumerCount = sPollingConsumerCount; - sLastPollingProducerCount = sPollingProducerCount; - - return xReturn; -} diff --git a/Demo/Common/Full/comtest.c b/Demo/Common/Full/comtest.c deleted file mode 100644 index bf35cbd96..000000000 --- a/Demo/Common/Full/comtest.c +++ /dev/null @@ -1,332 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/** - * Creates two tasks that operate on an interrupt driven serial port. A loopback - * connector should be used so that everything that is transmitted is also received. - * The serial port does not use any flow control. On a standard 9way 'D' connector - * pins two and three should be connected together. - * - * The first task repeatedly sends a string to a queue, character at a time. The - * serial port interrupt will empty the queue and transmit the characters. The - * task blocks for a pseudo random period before resending the string. - * - * The second task blocks on a queue waiting for a character to be received. - * Characters received by the serial port interrupt routine are posted onto the - * queue - unblocking the task making it ready to execute. If this is then the - * highest priority task ready to run it will run immediately - with a context - * switch occurring at the end of the interrupt service routine. The task - * receiving characters is spawned with a higher priority than the task - * transmitting the characters. - * - * With the loop back connector in place, one task will transmit a string and the - * other will immediately receive it. The receiving task knows the string it - * expects to receive so can detect an error. - * - * This also creates a third task. This is used to test semaphore usage from an - * ISR and does nothing interesting. - * - * \page ComTestC comtest.c - * \ingroup DemoFiles - *
- */ - -/* -Changes from V1.00: - - + The priority of the Rx task has been lowered. Received characters are - now processed (read from the queue) at the idle priority, allowing low - priority tasks to run evenly at times of a high communications overhead. - -Changes from V1.01: - - + The Tx task now waits a pseudo random time between transissions. - Previously a fixed period was used but this was not such a good test as - interrupts fired at regular intervals. - -Changes From V1.2.0: - - + Use vSerialPutString() instead of single character puts. - + Only stop the check variable incrementing after two consecutive errors. - -Changed from V1.2.5 - - + Made the Rx task 2 priorities higher than the Tx task. Previously it was - only 1. This is done to tie in better with the other demo application - tasks. - -Changes from V2.0.0 - - + Delay periods are now specified using variables and constants of - portTickType rather than unsigned portLONG. - + Slight modification to task priorities. - -*/ - - -/* Scheduler include files. */ -#include -#include -#include "FreeRTOS.h" -#include "task.h" - -/* Demo program include files. */ -#include "serial.h" -#include "comtest.h" -#include "print.h" - -/* The Tx task will transmit the sequence of characters at a pseudo random -interval. This is the maximum and minimum block time between sends. */ -#define comTX_MAX_BLOCK_TIME ( ( portTickType ) 0x15e ) -#define comTX_MIN_BLOCK_TIME ( ( portTickType ) 0xc8 ) - -#define comMAX_CONSECUTIVE_ERRORS ( 2 ) - -#define comSTACK_SIZE ( ( unsigned portSHORT ) 256 ) - -#define comRX_RELATIVE_PRIORITY ( 1 ) - -/* Handle to the com port used by both tasks. */ -static xComPortHandle xPort; - -/* The transmit function as described at the top of the file. */ -static void vComTxTask( void *pvParameters ); - -/* The receive function as described at the top of the file. */ -static void vComRxTask( void *pvParameters ); - -/* The semaphore test function as described at the top of the file. */ -static void vSemTestTask( void * pvParameters ); - -/* The string that is repeatedly transmitted. */ -const portCHAR * const pcMessageToExchange = "Send this message over and over again to check communications interrupts. " - "0123456789abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ\r\n"; - -/* Variables that are incremented on each cycle of each task. These are used to -check that both tasks are still executing. */ -volatile portSHORT sTxCount = 0, sRxCount = 0, sSemCount = 0; - - -/*-----------------------------------------------------------*/ - -void vStartComTestTasks( unsigned portBASE_TYPE uxPriority, eCOMPort ePort, eBaud eBaudRate ) -{ -const unsigned portBASE_TYPE uxBufferLength = 255; - - /* Initialise the com port then spawn both tasks. */ - xPort = xSerialPortInit( ePort, eBaudRate, serNO_PARITY, serBITS_8, serSTOP_1, uxBufferLength ); - xTaskCreate( vComTxTask, "COMTx", comSTACK_SIZE, NULL, uxPriority, NULL ); - xTaskCreate( vComRxTask, "COMRx", comSTACK_SIZE, NULL, uxPriority + comRX_RELATIVE_PRIORITY, NULL ); - xTaskCreate( vSemTestTask, "ISRSem", comSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); -} -/*-----------------------------------------------------------*/ - -static void vComTxTask( void *pvParameters ) -{ -const portCHAR * const pcTaskStartMsg = "COM Tx task started.\r\n"; -portTickType xTimeToWait; - - /* Stop warnings. */ - ( void ) pvParameters; - - /* Queue a message for printing to say the task has started. */ - vPrintDisplayMessage( &pcTaskStartMsg ); - - for( ;; ) - { - /* Send the string to the serial port. */ - vSerialPutString( xPort, pcMessageToExchange, strlen( pcMessageToExchange ) ); - - /* We have posted all the characters in the string - increment the variable - used to check that this task is still running, then wait before re-sending - the string. */ - sTxCount++; - - xTimeToWait = xTaskGetTickCount(); - - /* Make sure we don't wait too long... */ - xTimeToWait %= comTX_MAX_BLOCK_TIME; - - /* ...but we do want to wait. */ - if( xTimeToWait < comTX_MIN_BLOCK_TIME ) - { - xTimeToWait = comTX_MIN_BLOCK_TIME; - } - - vTaskDelay( xTimeToWait ); - } -} /*lint !e715 !e818 pvParameters is required for a task function even if it is not referenced. */ -/*-----------------------------------------------------------*/ - -static void vComRxTask( void *pvParameters ) -{ -const portCHAR * const pcTaskStartMsg = "COM Rx task started.\r\n"; -const portCHAR * const pcTaskErrorMsg = "COM read error\r\n"; -const portCHAR * const pcTaskRestartMsg = "COM resynced\r\n"; -const portCHAR * const pcTaskTimeoutMsg = "COM Rx timed out\r\n"; -const portTickType xBlockTime = ( portTickType ) 0xffff / portTICK_RATE_MS; -const portCHAR *pcExpectedChar; -portBASE_TYPE xGotChar; -portCHAR cRxedChar; -portSHORT sResyncRequired, sConsecutiveErrors, sLatchedError; - - /* Stop warnings. */ - ( void ) pvParameters; - - /* Queue a message for printing to say the task has started. */ - vPrintDisplayMessage( &pcTaskStartMsg ); - - /* The first expected character is the first character in the string. */ - pcExpectedChar = pcMessageToExchange; - sResyncRequired = pdFALSE; - sConsecutiveErrors = 0; - sLatchedError = pdFALSE; - - for( ;; ) - { - /* Receive a message from the com port interrupt routine. If a message is - not yet available the call will block the task. */ - xGotChar = xSerialGetChar( xPort, &cRxedChar, xBlockTime ); - if( xGotChar == pdTRUE ) - { - if( sResyncRequired == pdTRUE ) - { - /* We got out of sequence and are waiting for the start of the next - transmission of the string. */ - if( cRxedChar == '\n' ) - { - /* This is the end of the message so we can start again - with - the first character in the string being the next thing we expect - to receive. */ - pcExpectedChar = pcMessageToExchange; - sResyncRequired = pdFALSE; - - /* Queue a message for printing to say that we are going to try - again. */ - vPrintDisplayMessage( &pcTaskRestartMsg ); - - /* Stop incrementing the check variable, if consecutive errors occur. */ - sConsecutiveErrors++; - if( sConsecutiveErrors >= comMAX_CONSECUTIVE_ERRORS ) - { - sLatchedError = pdTRUE; - } - } - } - else - { - /* We have received a character, but is it the expected character? */ - if( cRxedChar != *pcExpectedChar ) - { - /* This was not the expected character so post a message for - printing to say that an error has occurred. We will then wait - to resynchronise. */ - vPrintDisplayMessage( &pcTaskErrorMsg ); - sResyncRequired = pdTRUE; - } - else - { - /* This was the expected character so next time we will expect - the next character in the string. Wrap back to the beginning - of the string when the null terminator has been reached. */ - pcExpectedChar++; - if( *pcExpectedChar == '\0' ) - { - pcExpectedChar = pcMessageToExchange; - - /* We have got through the entire string without error. */ - sConsecutiveErrors = 0; - } - } - } - - /* Increment the count that is used to check that this task is still - running. This is only done if an error has never occurred. */ - if( sLatchedError == pdFALSE ) - { - sRxCount++; - } - } - else - { - vPrintDisplayMessage( &pcTaskTimeoutMsg ); - } - } -} /*lint !e715 !e818 pvParameters is required for a task function even if it is not referenced. */ -/*-----------------------------------------------------------*/ - -static void vSemTestTask( void * pvParameters ) -{ -const portCHAR * const pcTaskStartMsg = "ISR Semaphore test started.\r\n"; - - /* Stop warnings. */ - ( void ) pvParameters; - - /* Queue a message for printing to say the task has started. */ - vPrintDisplayMessage( &pcTaskStartMsg ); - - for( ;; ) - { - if( xSerialWaitForSemaphore( xPort ) ) - { - sSemCount++; - } - } -} /*lint !e715 !e830 !e818 pvParameters not used but function prototype must be standard for task function. */ -/*-----------------------------------------------------------*/ - -/* This is called to check that all the created tasks are still running. */ -portBASE_TYPE xAreComTestTasksStillRunning( void ) -{ -static portSHORT sLastTxCount = 0, sLastRxCount = 0, sLastSemCount = 0; -portBASE_TYPE xReturn; - - /* Not too worried about mutual exclusion on these variables as they are 16 - bits and we are only reading them. We also only care to see if they have - changed or not. */ - - if( ( sTxCount == sLastTxCount ) || ( sRxCount == sLastRxCount ) || ( sSemCount == sLastSemCount ) ) - { - xReturn = pdFALSE; - } - else - { - xReturn = pdTRUE; - } - - sLastTxCount = sTxCount; - sLastRxCount = sRxCount; - sLastSemCount = sSemCount; - - return xReturn; -} - diff --git a/Demo/Common/Full/death.c b/Demo/Common/Full/death.c deleted file mode 100644 index e4d0690f8..000000000 --- a/Demo/Common/Full/death.c +++ /dev/null @@ -1,208 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/** - * Create a single persistent task which periodically dynamically creates another - * four tasks. The original task is called the creator task, the four tasks it - * creates are called suicidal tasks. - * - * Two of the created suicidal tasks kill one other suicidal task before killing - * themselves - leaving just the original task remaining. - * - * The creator task must be spawned after all of the other demo application tasks - * as it keeps a check on the number of tasks under the scheduler control. The - * number of tasks it expects to see running should never be greater than the - * number of tasks that were in existence when the creator task was spawned, plus - * one set of four suicidal tasks. If this number is exceeded an error is flagged. - * - * \page DeathC death.c - * \ingroup DemoFiles - *
- */ - -/* -Changes from V2.0.0 - - + Delay periods are now specified using variables and constants of - portTickType rather than unsigned portLONG. -*/ - -#include - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Demo program include files. */ -#include "death.h" -#include "print.h" - -#define deathSTACK_SIZE ( ( unsigned portSHORT ) 512 ) - -/* The task originally created which is responsible for periodically dynamically -creating another four tasks. */ -static void vCreateTasks( void *pvParameters ); - -/* The task function of the dynamically created tasks. */ -static void vSuicidalTask( void *pvParameters ); - -/* A variable which is incremented every time the dynamic tasks are created. This -is used to check that the task is still running. */ -static volatile portSHORT sCreationCount = 0; - -/* Used to store the number of tasks that were originally running so the creator -task can tell if any of the suicidal tasks have failed to die. */ -static volatile unsigned portBASE_TYPE uxTasksRunningAtStart = 0; -static const unsigned portBASE_TYPE uxMaxNumberOfExtraTasksRunning = 5; - -/* Used to store a handle to the tasks that should be killed by a suicidal task, -before it kills itself. */ -xTaskHandle xCreatedTask1, xCreatedTask2; - -/*-----------------------------------------------------------*/ - -void vCreateSuicidalTasks( unsigned portBASE_TYPE uxPriority ) -{ -unsigned portBASE_TYPE *puxPriority; - - /* Create the Creator tasks - passing in as a parameter the priority at which - the suicidal tasks should be created. */ - puxPriority = ( unsigned portBASE_TYPE * ) pvPortMalloc( sizeof( unsigned portBASE_TYPE ) ); - *puxPriority = uxPriority; - - xTaskCreate( vCreateTasks, "CREATOR", deathSTACK_SIZE, ( void * ) puxPriority, uxPriority, NULL ); - - /* Record the number of tasks that are running now so we know if any of the - suicidal tasks have failed to be killed. */ - uxTasksRunningAtStart = uxTaskGetNumberOfTasks(); -} -/*-----------------------------------------------------------*/ - -static void vSuicidalTask( void *pvParameters ) -{ -portDOUBLE d1, d2; -xTaskHandle xTaskToKill; -const portTickType xDelay = ( portTickType ) 500 / portTICK_RATE_MS; - - if( pvParameters != NULL ) - { - /* This task is periodically created four times. Tow created tasks are - passed a handle to the other task so it can kill it before killing itself. - The other task is passed in null. */ - xTaskToKill = *( xTaskHandle* )pvParameters; - } - else - { - xTaskToKill = NULL; - } - - for( ;; ) - { - /* Do something random just to use some stack and registers. */ - d1 = 2.4; - d2 = 89.2; - d2 *= d1; - vTaskDelay( xDelay ); - - if( xTaskToKill != NULL ) - { - /* Make sure the other task has a go before we delete it. */ - vTaskDelay( ( portTickType ) 0 ); - /* Kill the other task that was created by vCreateTasks(). */ - vTaskDelete( xTaskToKill ); - /* Kill ourselves. */ - vTaskDelete( NULL ); - } - } -}/*lint !e818 !e550 Function prototype must be as per standard for task functions. */ -/*-----------------------------------------------------------*/ - -static void vCreateTasks( void *pvParameters ) -{ -const portTickType xDelay = ( portTickType ) 1000 / portTICK_RATE_MS; -unsigned portBASE_TYPE uxPriority; -const portCHAR * const pcTaskStartMsg = "Create task started.\r\n"; - - /* Queue a message for printing to say the task has started. */ - vPrintDisplayMessage( &pcTaskStartMsg ); - - uxPriority = *( unsigned portBASE_TYPE * ) pvParameters; - vPortFree( pvParameters ); - - for( ;; ) - { - /* Just loop round, delaying then creating the four suicidal tasks. */ - vTaskDelay( xDelay ); - - xTaskCreate( vSuicidalTask, "SUICIDE1", deathSTACK_SIZE, NULL, uxPriority, &xCreatedTask1 ); - xTaskCreate( vSuicidalTask, "SUICIDE2", deathSTACK_SIZE, &xCreatedTask1, uxPriority, NULL ); - - xTaskCreate( vSuicidalTask, "SUICIDE1", deathSTACK_SIZE, NULL, uxPriority, &xCreatedTask2 ); - xTaskCreate( vSuicidalTask, "SUICIDE2", deathSTACK_SIZE, &xCreatedTask2, uxPriority, NULL ); - - ++sCreationCount; - } -} -/*-----------------------------------------------------------*/ - -/* This is called to check that the creator task is still running and that there -are not any more than four extra tasks. */ -portBASE_TYPE xIsCreateTaskStillRunning( void ) -{ -static portSHORT sLastCreationCount = 0; -portSHORT sReturn = pdTRUE; -unsigned portBASE_TYPE uxTasksRunningNow; - - if( sLastCreationCount == sCreationCount ) - { - sReturn = pdFALSE; - } - - uxTasksRunningNow = uxTaskGetNumberOfTasks(); - - if( uxTasksRunningNow < uxTasksRunningAtStart ) - { - sReturn = pdFALSE; - } - else if( ( uxTasksRunningNow - uxTasksRunningAtStart ) > uxMaxNumberOfExtraTasksRunning ) - { - sReturn = pdFALSE; - } - else - { - /* Everything is okay. */ - } - - return sReturn; -} - - diff --git a/Demo/Common/Full/dynamic.c b/Demo/Common/Full/dynamic.c deleted file mode 100644 index 81c13faaa..000000000 --- a/Demo/Common/Full/dynamic.c +++ /dev/null @@ -1,571 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/** - * The first test creates three tasks - two counter tasks (one continuous count - * and one limited count) and one controller. A "count" variable is shared - * between all three tasks. The two counter tasks should never be in a "ready" - * state at the same time. The controller task runs at the same priority as - * the continuous count task, and at a lower priority than the limited count - * task. - * - * One counter task loops indefinitely, incrementing the shared count variable - * on each iteration. To ensure it has exclusive access to the variable it - * raises it's priority above that of the controller task before each - * increment, lowering it again to it's original priority before starting the - * next iteration. - * - * The other counter task increments the shared count variable on each - * iteration of it's loop until the count has reached a limit of 0xff - at - * which point it suspends itself. It will not start a new loop until the - * controller task has made it "ready" again by calling vTaskResume (). - * This second counter task operates at a higher priority than controller - * task so does not need to worry about mutual exclusion of the counter - * variable. - * - * The controller task is in two sections. The first section controls and - * monitors the continuous count task. When this section is operational the - * limited count task is suspended. Likewise, the second section controls - * and monitors the limited count task. When this section is operational the - * continuous count task is suspended. - * - * In the first section the controller task first takes a copy of the shared - * count variable. To ensure mutual exclusion on the count variable it - * suspends the continuous count task, resuming it again when the copy has been - * taken. The controller task then sleeps for a fixed period - during which - * the continuous count task will execute and increment the shared variable. - * When the controller task wakes it checks that the continuous count task - * has executed by comparing the copy of the shared variable with its current - * value. This time, to ensure mutual exclusion, the scheduler itself is - * suspended with a call to vTaskSuspendAll (). This is for demonstration - * purposes only and is not a recommended technique due to its inefficiency. - * - * After a fixed number of iterations the controller task suspends the - * continuous count task, and moves on to its second section. - * - * At the start of the second section the shared variable is cleared to zero. - * The limited count task is then woken from it's suspension by a call to - * vTaskResume (). As this counter task operates at a higher priority than - * the controller task the controller task should not run again until the - * shared variable has been counted up to the limited value causing the counter - * task to suspend itself. The next line after vTaskResume () is therefore - * a check on the shared variable to ensure everything is as expected. - * - * - * The second test consists of a couple of very simple tasks that post onto a - * queue while the scheduler is suspended. This test was added to test parts - * of the scheduler not exercised by the first test. - * - * - * The final set of two tasks implements a third test. This simply raises the - * priority of a task while the scheduler is suspended. Again this test was - * added to exercise parts of the code not covered by the first test. - * - * \page Priorities dynamic.c - * \ingroup DemoFiles - *
- */ - -/* -Changes from V2.0.0 - - + Delay periods are now specified using variables and constants of - portTickType rather than unsigned portLONG. - + Added a second, simple test that uses the functions - vQueueReceiveWhenSuspendedTask() and vQueueSendWhenSuspendedTask(). - -Changes from V3.1.1 - - + Added a third simple test that uses the vTaskPrioritySet() function - while the scheduler is suspended. - + Modified the controller task slightly to test the calling of - vTaskResumeAll() while the scheduler is suspended. -*/ - -#include - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" -#include "semphr.h" - -/* Demo app include files. */ -#include "dynamic.h" -#include "print.h" - -/* Function that implements the "limited count" task as described above. */ -static void vLimitedIncrementTask( void * pvParameters ); - -/* Function that implements the "continuous count" task as described above. */ -static void vContinuousIncrementTask( void * pvParameters ); - -/* Function that implements the controller task as described above. */ -static void vCounterControlTask( void * pvParameters ); - -/* The simple test functions that check sending and receiving while the -scheduler is suspended. */ -static void vQueueReceiveWhenSuspendedTask( void *pvParameters ); -static void vQueueSendWhenSuspendedTask( void *pvParameters ); - -/* The simple test functions that check raising and lowering of task priorities -while the scheduler is suspended. */ -static void prvChangePriorityWhenSuspendedTask( void *pvParameters ); -static void prvChangePriorityHelperTask( void *pvParameters ); - - -/* Demo task specific constants. */ -#define priSTACK_SIZE ( ( unsigned portSHORT ) 128 ) -#define priSLEEP_TIME ( ( portTickType ) 50 ) -#define priLOOPS ( 5 ) -#define priMAX_COUNT ( ( unsigned portLONG ) 0xff ) -#define priNO_BLOCK ( ( portTickType ) 0 ) -#define priSUSPENDED_QUEUE_LENGTH ( 1 ) - -/*-----------------------------------------------------------*/ - -/* Handles to the two counter tasks. These could be passed in as parameters -to the controller task to prevent them having to be file scope. */ -static xTaskHandle xContinuousIncrementHandle, xLimitedIncrementHandle, xChangePriorityWhenSuspendedHandle; - -/* The shared counter variable. This is passed in as a parameter to the two -counter variables for demonstration purposes. */ -static unsigned portLONG ulCounter; - -/* Variable used in a similar way by the test that checks the raising and -lowering of task priorities while the scheduler is suspended. */ -static unsigned portLONG ulPrioritySetCounter; - -/* Variables used to check that the tasks are still operating without error. -Each complete iteration of the controller task increments this variable -provided no errors have been found. The variable maintaining the same value -is therefore indication of an error. */ -static unsigned portSHORT usCheckVariable = ( unsigned portSHORT ) 0; -static portBASE_TYPE xSuspendedQueueSendError = pdFALSE; -static portBASE_TYPE xSuspendedQueueReceiveError = pdFALSE; -static portBASE_TYPE xPriorityRaiseWhenSuspendedError = pdFALSE; - -/* Queue used by the second test. */ -xQueueHandle xSuspendedTestQueue; - -/*-----------------------------------------------------------*/ -/* - * Start the seven tasks as described at the top of the file. - * Note that the limited count task is given a higher priority. - */ -void vStartDynamicPriorityTasks( void ) -{ - xSuspendedTestQueue = xQueueCreate( priSUSPENDED_QUEUE_LENGTH, sizeof( unsigned portLONG ) ); - xTaskCreate( vContinuousIncrementTask, "CONT_INC", priSTACK_SIZE, ( void * ) &ulCounter, tskIDLE_PRIORITY, &xContinuousIncrementHandle ); - xTaskCreate( vLimitedIncrementTask, "LIM_INC", priSTACK_SIZE, ( void * ) &ulCounter, tskIDLE_PRIORITY + 1, &xLimitedIncrementHandle ); - xTaskCreate( vCounterControlTask, "C_CTRL", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); - xTaskCreate( vQueueSendWhenSuspendedTask, "SUSP_SEND", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); - xTaskCreate( vQueueReceiveWhenSuspendedTask, "SUSP_RECV", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); - xTaskCreate( prvChangePriorityWhenSuspendedTask, "1st_P_CHANGE", priSTACK_SIZE, NULL, tskIDLE_PRIORITY + 1, NULL ); - xTaskCreate( prvChangePriorityHelperTask, "2nt_P_CHANGE", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, &xChangePriorityWhenSuspendedHandle ); -} -/*-----------------------------------------------------------*/ - -/* - * Just loops around incrementing the shared variable until the limit has been - * reached. Once the limit has been reached it suspends itself. - */ -static void vLimitedIncrementTask( void * pvParameters ) -{ -unsigned portLONG *pulCounter; - - /* Take a pointer to the shared variable from the parameters passed into - the task. */ - pulCounter = ( unsigned portLONG * ) pvParameters; - - /* This will run before the control task, so the first thing it does is - suspend - the control task will resume it when ready. */ - vTaskSuspend( NULL ); - - for( ;; ) - { - /* Just count up to a value then suspend. */ - ( *pulCounter )++; - - if( *pulCounter >= priMAX_COUNT ) - { - vTaskSuspend( NULL ); - } - } -} -/*-----------------------------------------------------------*/ - -/* - * Just keep counting the shared variable up. The control task will suspend - * this task when it wants. - */ -static void vContinuousIncrementTask( void * pvParameters ) -{ -unsigned portLONG *pulCounter; -unsigned portBASE_TYPE uxOurPriority; - - /* Take a pointer to the shared variable from the parameters passed into - the task. */ - pulCounter = ( unsigned portLONG * ) pvParameters; - - /* Query our priority so we can raise it when exclusive access to the - shared variable is required. */ - uxOurPriority = uxTaskPriorityGet( NULL ); - - for( ;; ) - { - /* Raise our priority above the controller task to ensure a context - switch does not occur while we are accessing this variable. */ - vTaskPrioritySet( NULL, uxOurPriority + 1 ); - ( *pulCounter )++; - vTaskPrioritySet( NULL, uxOurPriority ); - } -} -/*-----------------------------------------------------------*/ - -/* - * Controller task as described above. - */ -static void vCounterControlTask( void * pvParameters ) -{ -unsigned portLONG ulLastCounter; -portSHORT sLoops; -portSHORT sError = pdFALSE; -const portCHAR * const pcTaskStartMsg = "Priority manipulation tasks started.\r\n"; -const portCHAR * const pcTaskFailMsg = "Priority manipulation Task Failed\r\n"; - - /* Just to stop warning messages. */ - ( void ) pvParameters; - - /* Queue a message for printing to say the task has started. */ - vPrintDisplayMessage( &pcTaskStartMsg ); - - for( ;; ) - { - /* Start with the counter at zero. */ - ulCounter = ( unsigned portLONG ) 0; - - /* First section : */ - - /* Check the continuous count task is running. */ - for( sLoops = 0; sLoops < priLOOPS; sLoops++ ) - { - /* Suspend the continuous count task so we can take a mirror of the - shared variable without risk of corruption. */ - vTaskSuspend( xContinuousIncrementHandle ); - ulLastCounter = ulCounter; - vTaskResume( xContinuousIncrementHandle ); - - /* Now delay to ensure the other task has processor time. */ - vTaskDelay( priSLEEP_TIME ); - - /* Check the shared variable again. This time to ensure mutual - exclusion the whole scheduler will be locked. This is just for - demo purposes! */ - vTaskSuspendAll(); - { - if( ulLastCounter == ulCounter ) - { - /* The shared variable has not changed. There is a problem - with the continuous count task so flag an error. */ - sError = pdTRUE; - xTaskResumeAll(); - vPrintDisplayMessage( &pcTaskFailMsg ); - vTaskSuspendAll(); - } - } - xTaskResumeAll(); - } - - - /* Second section: */ - - /* Suspend the continuous counter task so it stops accessing the shared variable. */ - vTaskSuspend( xContinuousIncrementHandle ); - - /* Reset the variable. */ - ulCounter = ( unsigned portLONG ) 0; - - /* Resume the limited count task which has a higher priority than us. - We should therefore not return from this call until the limited count - task has suspended itself with a known value in the counter variable. - The scheduler suspension is not necessary but is included for test - purposes. */ - vTaskSuspendAll(); - vTaskResume( xLimitedIncrementHandle ); - xTaskResumeAll(); - - /* Does the counter variable have the expected value? */ - if( ulCounter != priMAX_COUNT ) - { - sError = pdTRUE; - vPrintDisplayMessage( &pcTaskFailMsg ); - } - - if( sError == pdFALSE ) - { - /* If no errors have occurred then increment the check variable. */ - portENTER_CRITICAL(); - usCheckVariable++; - portEXIT_CRITICAL(); - } - - /* Resume the continuous count task and do it all again. */ - vTaskResume( xContinuousIncrementHandle ); - } -} -/*-----------------------------------------------------------*/ - -static void vQueueSendWhenSuspendedTask( void *pvParameters ) -{ -static unsigned portLONG ulValueToSend = ( unsigned portLONG ) 0; -const portCHAR * const pcTaskStartMsg = "Queue send while suspended task started.\r\n"; -const portCHAR * const pcTaskFailMsg = "Queue send while suspended failed.\r\n"; - - /* Just to stop warning messages. */ - ( void ) pvParameters; - - /* Queue a message for printing to say the task has started. */ - vPrintDisplayMessage( &pcTaskStartMsg ); - - for( ;; ) - { - vTaskSuspendAll(); - { - /* We must not block while the scheduler is suspended! */ - if( xQueueSend( xSuspendedTestQueue, ( void * ) &ulValueToSend, priNO_BLOCK ) != pdTRUE ) - { - if( xSuspendedQueueSendError == pdFALSE ) - { - xTaskResumeAll(); - vPrintDisplayMessage( &pcTaskFailMsg ); - vTaskSuspendAll(); - } - - xSuspendedQueueSendError = pdTRUE; - } - } - xTaskResumeAll(); - - vTaskDelay( priSLEEP_TIME ); - - ++ulValueToSend; - } -} -/*-----------------------------------------------------------*/ - -static void vQueueReceiveWhenSuspendedTask( void *pvParameters ) -{ -static unsigned portLONG ulExpectedValue = ( unsigned portLONG ) 0, ulReceivedValue; -const portCHAR * const pcTaskStartMsg = "Queue receive while suspended task started.\r\n"; -const portCHAR * const pcTaskFailMsg = "Queue receive while suspended failed.\r\n"; -portBASE_TYPE xGotValue; - - /* Just to stop warning messages. */ - ( void ) pvParameters; - - /* Queue a message for printing to say the task has started. */ - vPrintDisplayMessage( &pcTaskStartMsg ); - - for( ;; ) - { - do - { - /* Suspending the scheduler here is fairly pointless and - undesirable for a normal application. It is done here purely - to test the scheduler. The inner xTaskResumeAll() should - never return pdTRUE as the scheduler is still locked by the - outer call. */ - vTaskSuspendAll(); - { - vTaskSuspendAll(); - { - xGotValue = xQueueReceive( xSuspendedTestQueue, ( void * ) &ulReceivedValue, priNO_BLOCK ); - } - if( xTaskResumeAll() ) - { - xSuspendedQueueReceiveError = pdTRUE; - } - } - xTaskResumeAll(); - - } while( xGotValue == pdFALSE ); - - if( ulReceivedValue != ulExpectedValue ) - { - if( xSuspendedQueueReceiveError == pdFALSE ) - { - vPrintDisplayMessage( &pcTaskFailMsg ); - } - xSuspendedQueueReceiveError = pdTRUE; - } - - ++ulExpectedValue; - } -} -/*-----------------------------------------------------------*/ - -static void prvChangePriorityWhenSuspendedTask( void *pvParameters ) -{ -const portCHAR * const pcTaskStartMsg = "Priority change when suspended task started.\r\n"; -const portCHAR * const pcTaskFailMsg = "Priority change when suspended task failed.\r\n"; - - /* Just to stop warning messages. */ - ( void ) pvParameters; - - /* Queue a message for printing to say the task has started. */ - vPrintDisplayMessage( &pcTaskStartMsg ); - - for( ;; ) - { - /* Start with the counter at 0 so we know what the counter should be - when we check it next. */ - ulPrioritySetCounter = ( unsigned portLONG ) 0; - - /* Resume the helper task. At this time it has a priority lower than - ours so no context switch should occur. */ - vTaskResume( xChangePriorityWhenSuspendedHandle ); - - /* Check to ensure the task just resumed has not executed. */ - portENTER_CRITICAL(); - { - if( ulPrioritySetCounter != ( unsigned portLONG ) 0 ) - { - xPriorityRaiseWhenSuspendedError = pdTRUE; - vPrintDisplayMessage( &pcTaskFailMsg ); - } - } - portEXIT_CRITICAL(); - - /* Now try raising the priority while the scheduler is suspended. */ - vTaskSuspendAll(); - { - vTaskPrioritySet( xChangePriorityWhenSuspendedHandle, ( configMAX_PRIORITIES - 1 ) ); - - /* Again, even though the helper task has a priority greater than - ours, it should not have executed yet because the scheduler is - suspended. */ - portENTER_CRITICAL(); - { - if( ulPrioritySetCounter != ( unsigned portLONG ) 0 ) - { - xPriorityRaiseWhenSuspendedError = pdTRUE; - vPrintDisplayMessage( &pcTaskFailMsg ); - } - } - portEXIT_CRITICAL(); - } - xTaskResumeAll(); - - /* Now the scheduler has been resumed the helper task should - immediately preempt us and execute. When it executes it will increment - the ulPrioritySetCounter exactly once before suspending itself. - - We should now always find the counter set to 1. */ - portENTER_CRITICAL(); - { - if( ulPrioritySetCounter != ( unsigned portLONG ) 1 ) - { - xPriorityRaiseWhenSuspendedError = pdTRUE; - vPrintDisplayMessage( &pcTaskFailMsg ); - } - } - portEXIT_CRITICAL(); - - /* Delay until we try this again. */ - vTaskDelay( priSLEEP_TIME * 2 ); - - /* Set the priority of the helper task back ready for the next - execution of this task. */ - vTaskSuspendAll(); - vTaskPrioritySet( xChangePriorityWhenSuspendedHandle, tskIDLE_PRIORITY ); - xTaskResumeAll(); - } -} -/*-----------------------------------------------------------*/ - -static void prvChangePriorityHelperTask( void *pvParameters ) -{ - /* Just to stop warning messages. */ - ( void ) pvParameters; - - for( ;; ) - { - /* This is the helper task for prvChangePriorityWhenSuspendedTask(). - It has it's priority raised and lowered. When it runs it simply - increments the counter then suspends itself again. This allows - prvChangePriorityWhenSuspendedTask() to know how many times it has - executed. */ - ulPrioritySetCounter++; - vTaskSuspend( NULL ); - } -} -/*-----------------------------------------------------------*/ - -/* Called to check that all the created tasks are still running without error. */ -portBASE_TYPE xAreDynamicPriorityTasksStillRunning( void ) -{ -/* Keep a history of the check variables so we know if it has been incremented -since the last call. */ -static unsigned portSHORT usLastTaskCheck = ( unsigned portSHORT ) 0; -portBASE_TYPE xReturn = pdTRUE; - - /* Check the tasks are still running by ensuring the check variable - is still incrementing. */ - - if( usCheckVariable == usLastTaskCheck ) - { - /* The check has not incremented so an error exists. */ - xReturn = pdFALSE; - } - - if( xSuspendedQueueSendError == pdTRUE ) - { - xReturn = pdFALSE; - } - - if( xSuspendedQueueReceiveError == pdTRUE ) - { - xReturn = pdFALSE; - } - - if( xPriorityRaiseWhenSuspendedError == pdTRUE ) - { - xReturn = pdFALSE; - } - - usLastTaskCheck = usCheckVariable; - return xReturn; -} - - - - diff --git a/Demo/Common/Full/events.c b/Demo/Common/Full/events.c deleted file mode 100644 index 9d396cd3a..000000000 --- a/Demo/Common/Full/events.c +++ /dev/null @@ -1,379 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/** - * This file exercises the event mechanism whereby more than one task is - * blocked waiting for the same event. - * - * The demo creates five tasks - four 'event' tasks, and a controlling task. - * The event tasks have various different priorities and all block on reading - * the same queue. The controlling task writes data to the queue, then checks - * to see which of the event tasks read the data from the queue. The - * controlling task has the lowest priority of all the tasks so is guaranteed - * to always get preempted immediately upon writing to the queue. - * - * By selectively suspending and resuming the event tasks the controlling task - * can check that the highest priority task that is blocked on the queue is the - * task that reads the posted data from the queue. - * - * Two of the event tasks share the same priority. When neither of these tasks - * are suspended they should alternate - one reading one message from the queue, - * the other the next message, etc. - */ - -/* Standard includes. */ -#include -#include -#include - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" - -/* Demo program include files. */ -#include "mevents.h" -#include "print.h" - -/* Demo specific constants. */ -#define evtSTACK_SIZE ( ( unsigned portBASE_TYPE ) 128 ) -#define evtNUM_TASKS ( 4 ) -#define evtQUEUE_LENGTH ( ( unsigned portBASE_TYPE ) 3 ) -#define evtNO_DELAY 0 - -/* Just indexes used to uniquely identify the tasks. Note that two tasks are -'highest' priority. */ -#define evtHIGHEST_PRIORITY_INDEX_2 3 -#define evtHIGHEST_PRIORITY_INDEX_1 2 -#define evtMEDIUM_PRIORITY_INDEX 1 -#define evtLOWEST_PRIORITY_INDEX 0 - -/* Each event task increments one of these counters each time it reads data -from the queue. */ -static volatile portBASE_TYPE xTaskCounters[ evtNUM_TASKS ] = { 0, 0, 0, 0 }; - -/* Each time the controlling task posts onto the queue it increments the -expected count of the task that it expected to read the data from the queue -(i.e. the task with the highest priority that should be blocked on the queue). - -xExpectedTaskCounters are incremented from the controlling task, and -xTaskCounters are incremented from the individual event tasks - therefore -comparing xTaskCounters to xExpectedTaskCounters shows whether or not the -correct task was unblocked by the post. */ -static portBASE_TYPE xExpectedTaskCounters[ evtNUM_TASKS ] = { 0, 0, 0, 0 }; - -/* Handles to the four event tasks. These are required to suspend and resume -the tasks. */ -static xTaskHandle xCreatedTasks[ evtNUM_TASKS ]; - -/* The single queue onto which the controlling task posts, and the four event -tasks block. */ -static xQueueHandle xQueue; - -/* Flag used to indicate whether or not an error has occurred at any time. -An error is either the queue being full when not expected, or an unexpected -task reading data from the queue. */ -static portBASE_TYPE xHealthStatus = pdPASS; - -/*-----------------------------------------------------------*/ - -/* Function that implements the event task. This is created four times. */ -static void prvMultiEventTask( void *pvParameters ); - -/* Function that implements the controlling task. */ -static void prvEventControllerTask( void *pvParameters ); - -/* This is a utility function that posts data to the queue, then compares -xExpectedTaskCounters with xTaskCounters to ensure everything worked as -expected. - -The event tasks all have higher priorities the controlling task. Therefore -the controlling task will always get preempted between writhing to the queue -and checking the task counters. - -@param xExpectedTask The index to the task that the controlling task thinks - should be the highest priority task waiting for data, and - therefore the task that will unblock. - -@param xIncrement The number of items that should be written to the queue. -*/ -static void prvCheckTaskCounters( portBASE_TYPE xExpectedTask, portBASE_TYPE xIncrement ); - -/* This is just incremented each cycle of the controlling tasks function so -the main application can ensure the test is still running. */ -static portBASE_TYPE xCheckVariable = 0; - -/*-----------------------------------------------------------*/ - -void vStartMultiEventTasks( void ) -{ - /* Create the queue to be used for all the communications. */ - xQueue = xQueueCreate( evtQUEUE_LENGTH, ( unsigned portBASE_TYPE ) sizeof( unsigned portBASE_TYPE ) ); - - /* Start the controlling task. This has the idle priority to ensure it is - always preempted by the event tasks. */ - xTaskCreate( prvEventControllerTask, "EvntCTRL", evtSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); - - /* Start the four event tasks. Note that two have priority 3, one - priority 2 and the other priority 1. */ - xTaskCreate( prvMultiEventTask, "Event0", evtSTACK_SIZE, ( void * ) &( xTaskCounters[ 0 ] ), 1, &( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] ) ); - xTaskCreate( prvMultiEventTask, "Event1", evtSTACK_SIZE, ( void * ) &( xTaskCounters[ 1 ] ), 2, &( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] ) ); - xTaskCreate( prvMultiEventTask, "Event2", evtSTACK_SIZE, ( void * ) &( xTaskCounters[ 2 ] ), 3, &( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ) ); - xTaskCreate( prvMultiEventTask, "Event3", evtSTACK_SIZE, ( void * ) &( xTaskCounters[ 3 ] ), 3, &( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_2 ] ) ); -} -/*-----------------------------------------------------------*/ - -static void prvMultiEventTask( void *pvParameters ) -{ -portBASE_TYPE *pxCounter; -unsigned portBASE_TYPE uxDummy; -const portCHAR * const pcTaskStartMsg = "Multi event task started.\r\n"; - - /* The variable this task will increment is passed in as a parameter. */ - pxCounter = ( portBASE_TYPE * ) pvParameters; - - vPrintDisplayMessage( &pcTaskStartMsg ); - - for( ;; ) - { - /* Block on the queue. */ - if( xQueueReceive( xQueue, &uxDummy, portMAX_DELAY ) ) - { - /* We unblocked by reading the queue - so simply increment - the counter specific to this task instance. */ - ( *pxCounter )++; - } - else - { - xHealthStatus = pdFAIL; - } - } -} -/*-----------------------------------------------------------*/ - -static void prvEventControllerTask( void *pvParameters ) -{ -const portCHAR * const pcTaskStartMsg = "Multi event controller task started.\r\n"; -portBASE_TYPE xDummy = 0; - - /* Just to stop warnings. */ - ( void ) pvParameters; - - vPrintDisplayMessage( &pcTaskStartMsg ); - - for( ;; ) - { - /* All tasks are blocked on the queue. When a message is posted one of - the two tasks that share the highest priority should unblock to read - the queue. The next message written should unblock the other task with - the same high priority, and so on in order. No other task should - unblock to read data as they have lower priorities. */ - - prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 ); - prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_2, 1 ); - prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 ); - prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_2, 1 ); - prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 ); - - /* For the rest of these tests we don't need the second 'highest' - priority task - so it is suspended. */ - vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_2 ] ); - - - - /* Now suspend the other highest priority task. The medium priority - task will then be the task with the highest priority that remains - blocked on the queue. */ - vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ); - - /* This time, when we post onto the queue we will expect the medium - priority task to unblock and preempt us. */ - prvCheckTaskCounters( evtMEDIUM_PRIORITY_INDEX, 1 ); - - /* Now try resuming the highest priority task while the scheduler is - suspended. The task should start executing as soon as the scheduler - is resumed - therefore when we post to the queue again, the highest - priority task should again preempt us. */ - vTaskSuspendAll(); - vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ); - xTaskResumeAll(); - prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 ); - - /* Now we are going to suspend the high and medium priority tasks. The - low priority task should then preempt us. Again the task suspension is - done with the whole scheduler suspended just for test purposes. */ - vTaskSuspendAll(); - vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ); - vTaskSuspend( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] ); - xTaskResumeAll(); - prvCheckTaskCounters( evtLOWEST_PRIORITY_INDEX, 1 ); - - - - /* Do the same basic test another few times - selectively suspending - and resuming tasks and each time calling prvCheckTaskCounters() passing - to the function the number of the task we expected to be unblocked by - the post. */ - - vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ); - prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 ); - - vTaskSuspendAll(); /* Just for test. */ - vTaskSuspendAll(); /* Just for test. */ - vTaskSuspendAll(); /* Just for even more test. */ - vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ); - xTaskResumeAll(); - xTaskResumeAll(); - xTaskResumeAll(); - prvCheckTaskCounters( evtLOWEST_PRIORITY_INDEX, 1 ); - - vTaskResume( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] ); - prvCheckTaskCounters( evtMEDIUM_PRIORITY_INDEX, 1 ); - - vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ); - prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 ); - - - - - - /* Now a slight change, first suspend all tasks. */ - vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ); - vTaskSuspend( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] ); - vTaskSuspend( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] ); - - /* Now when we resume the low priority task and write to the queue 3 - times. We expect the low priority task to service the queue three - times. */ - vTaskResume( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] ); - prvCheckTaskCounters( evtLOWEST_PRIORITY_INDEX, evtQUEUE_LENGTH ); - - /* Again suspend all tasks (only the low priority task is not suspended - already). */ - vTaskSuspend( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] ); - - /* This time we are going to suspend the scheduler, resume the low - priority task, then resume the high priority task. In this state we - will write to the queue three times. When the scheduler is resumed - we expect the high priority task to service all three messages. */ - vTaskSuspendAll(); - { - vTaskResume( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] ); - vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ); - - for( xDummy = 0; xDummy < evtQUEUE_LENGTH; xDummy++ ) - { - if( xQueueSend( xQueue, &xDummy, evtNO_DELAY ) != pdTRUE ) - { - xHealthStatus = pdFAIL; - } - } - - /* The queue should not have been serviced yet!. The scheduler - is still suspended. */ - if( memcmp( ( void * ) xExpectedTaskCounters, ( void * ) xTaskCounters, sizeof( xExpectedTaskCounters ) ) ) - { - xHealthStatus = pdFAIL; - } - } - xTaskResumeAll(); - - /* We should have been preempted by resuming the scheduler - so by the - time we are running again we expect the high priority task to have - removed three items from the queue. */ - xExpectedTaskCounters[ evtHIGHEST_PRIORITY_INDEX_1 ] += evtQUEUE_LENGTH; - if( memcmp( ( void * ) xExpectedTaskCounters, ( void * ) xTaskCounters, sizeof( xExpectedTaskCounters ) ) ) - { - xHealthStatus = pdFAIL; - } - - /* The medium priority and second high priority tasks are still - suspended. Make sure to resume them before starting again. */ - vTaskResume( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] ); - vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_2 ] ); - - /* Just keep incrementing to show the task is still executing. */ - xCheckVariable++; - } -} -/*-----------------------------------------------------------*/ - -static void prvCheckTaskCounters( portBASE_TYPE xExpectedTask, portBASE_TYPE xIncrement ) -{ -portBASE_TYPE xDummy = 0; - - /* Write to the queue the requested number of times. The data written is - not important. */ - for( xDummy = 0; xDummy < xIncrement; xDummy++ ) - { - if( xQueueSend( xQueue, &xDummy, evtNO_DELAY ) != pdTRUE ) - { - /* Did not expect to ever find the queue full. */ - xHealthStatus = pdFAIL; - } - } - - /* All the tasks blocked on the queue have a priority higher than the - controlling task. Writing to the queue will therefore have caused this - task to be preempted. By the time this line executes the event task will - have executed and incremented its counter. Increment the expected counter - to the same value. */ - ( xExpectedTaskCounters[ xExpectedTask ] ) += xIncrement; - - /* Check the actual counts and expected counts really are the same. */ - if( memcmp( ( void * ) xExpectedTaskCounters, ( void * ) xTaskCounters, sizeof( xExpectedTaskCounters ) ) ) - { - /* The counters were not the same. This means a task we did not expect - to unblock actually did unblock. */ - xHealthStatus = pdFAIL; - } -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xAreMultiEventTasksStillRunning( void ) -{ -static portBASE_TYPE xPreviousCheckVariable = 0; - - /* Called externally to periodically check that this test is still - operational. */ - - if( xPreviousCheckVariable == xCheckVariable ) - { - xHealthStatus = pdFAIL; - } - - xPreviousCheckVariable = xCheckVariable; - - return xHealthStatus; -} - - diff --git a/Demo/Common/Full/flash.c b/Demo/Common/Full/flash.c deleted file mode 100644 index 153f713b4..000000000 --- a/Demo/Common/Full/flash.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/** - * Creates eight tasks, each of which flash an LED at a different rate. The first - * LED flashes every 125ms, the second every 250ms, the third every 375ms, etc. - * - * The LED flash tasks provide instant visual feedback. They show that the scheduler - * is still operational. - * - * The PC port uses the standard parallel port for outputs, the Flashlite 186 port - * uses IO port F. - * - * \page flashC flash.c - * \ingroup DemoFiles - *
- */ - -/* -Changes from V2.0.0 - - + Delay periods are now specified using variables and constants of - portTickType rather than unsigned portLONG. - -Changes from V2.1.1 - - + The stack size now uses configMINIMAL_STACK_SIZE. - + String constants made file scope to decrease stack depth on 8051 port. -*/ - -#include - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Demo program include files. */ -#include "partest.h" -#include "flash.h" -#include "print.h" - -#define ledSTACK_SIZE configMINIMAL_STACK_SIZE - -/* Structure used to pass parameters to the LED tasks. */ -typedef struct LED_PARAMETERS -{ - unsigned portBASE_TYPE uxLED; /*< The output the task should use. */ - portTickType xFlashRate; /*< The rate at which the LED should flash. */ -} xLEDParameters; - -/* The task that is created eight times - each time with a different xLEDParaemtes -structure passed in as the parameter. */ -static void vLEDFlashTask( void *pvParameters ); - -/* String to print if USE_STDIO is defined. */ -const portCHAR * const pcTaskStartMsg = "LED flash task started.\r\n"; - -/*-----------------------------------------------------------*/ - -void vStartLEDFlashTasks( unsigned portBASE_TYPE uxPriority ) -{ -unsigned portBASE_TYPE uxLEDTask; -xLEDParameters *pxLEDParameters; -const unsigned portBASE_TYPE uxNumOfLEDs = 8; -const portTickType xFlashRate = 125; - - /* Create the eight tasks. */ - for( uxLEDTask = 0; uxLEDTask < uxNumOfLEDs; ++uxLEDTask ) - { - /* Create and complete the structure used to pass parameters to the next - created task. */ - pxLEDParameters = ( xLEDParameters * ) pvPortMalloc( sizeof( xLEDParameters ) ); - pxLEDParameters->uxLED = uxLEDTask; - pxLEDParameters->xFlashRate = ( xFlashRate + ( xFlashRate * ( portTickType ) uxLEDTask ) ); - pxLEDParameters->xFlashRate /= portTICK_RATE_MS; - - /* Spawn the task. */ - xTaskCreate( vLEDFlashTask, "LEDx", ledSTACK_SIZE, ( void * ) pxLEDParameters, uxPriority, ( xTaskHandle * ) NULL ); - } -} -/*-----------------------------------------------------------*/ - -static void vLEDFlashTask( void *pvParameters ) -{ -xLEDParameters *pxParameters; - - /* Queue a message for printing to say the task has started. */ - vPrintDisplayMessage( &pcTaskStartMsg ); - - pxParameters = ( xLEDParameters * ) pvParameters; - - for(;;) - { - /* Delay for half the flash period then turn the LED on. */ - vTaskDelay( pxParameters->xFlashRate / ( portTickType ) 2 ); - vParTestToggleLED( pxParameters->uxLED ); - - /* Delay for half the flash period then turn the LED off. */ - vTaskDelay( pxParameters->xFlashRate / ( portTickType ) 2 ); - vParTestToggleLED( pxParameters->uxLED ); - } -} - diff --git a/Demo/Common/Full/flop.c b/Demo/Common/Full/flop.c deleted file mode 100644 index 896bcb037..000000000 --- a/Demo/Common/Full/flop.c +++ /dev/null @@ -1,336 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V1.2.3 - - + The created tasks now include calls to tskYIELD(), allowing them to be used - with the cooperative scheduler. -*/ - -/** - * Creates eight tasks, each of which loops continuously performing an (emulated) - * floating point calculation. - * - * All the tasks run at the idle priority and never block or yield. This causes - * all eight tasks to time slice with the idle task. Running at the idle priority - * means that these tasks will get pre-empted any time another task is ready to run - * or a time slice occurs. More often than not the pre-emption will occur mid - * calculation, creating a good test of the schedulers context switch mechanism - a - * calculation producing an unexpected result could be a symptom of a corruption in - * the context of a task. - * - * \page FlopC flop.c - * \ingroup DemoFiles - *
- */ - -#include -#include - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" -#include "print.h" - -/* Demo program include files. */ -#include "flop.h" - -#define mathSTACK_SIZE ( ( unsigned portSHORT ) 512 ) -#define mathNUMBER_OF_TASKS ( 8 ) - -/* Four tasks, each of which performs a different floating point calculation. -Each of the four is created twice. */ -static void vCompetingMathTask1( void *pvParameters ); -static void vCompetingMathTask2( void *pvParameters ); -static void vCompetingMathTask3( void *pvParameters ); -static void vCompetingMathTask4( void *pvParameters ); - -/* These variables are used to check that all the tasks are still running. If a -task gets a calculation wrong it will -stop incrementing its check variable. */ -static volatile unsigned portSHORT usTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned portSHORT ) 0 }; - -/*-----------------------------------------------------------*/ - -void vStartMathTasks( unsigned portBASE_TYPE uxPriority ) -{ - xTaskCreate( vCompetingMathTask1, "Math1", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 0 ] ), uxPriority, NULL ); - xTaskCreate( vCompetingMathTask2, "Math2", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 1 ] ), uxPriority, NULL ); - xTaskCreate( vCompetingMathTask3, "Math3", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 2 ] ), uxPriority, NULL ); - xTaskCreate( vCompetingMathTask4, "Math4", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 3 ] ), uxPriority, NULL ); - xTaskCreate( vCompetingMathTask1, "Math5", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 4 ] ), uxPriority, NULL ); - xTaskCreate( vCompetingMathTask2, "Math6", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 5 ] ), uxPriority, NULL ); - xTaskCreate( vCompetingMathTask3, "Math7", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 6 ] ), uxPriority, NULL ); - xTaskCreate( vCompetingMathTask4, "Math8", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 7 ] ), uxPriority, NULL ); -} -/*-----------------------------------------------------------*/ - -static void vCompetingMathTask1( void *pvParameters ) -{ -portDOUBLE d1, d2, d3, d4; -volatile unsigned portSHORT *pusTaskCheckVariable; -const portDOUBLE dAnswer = ( 123.4567 + 2345.6789 ) * -918.222; -const portCHAR * const pcTaskStartMsg = "Math task 1 started.\r\n"; -const portCHAR * const pcTaskFailMsg = "Math task 1 failed.\r\n"; -portSHORT sError = pdFALSE; - - /* Queue a message for printing to say the task has started. */ - vPrintDisplayMessage( &pcTaskStartMsg ); - - /* The variable this task increments to show it is still running is passed in - as the parameter. */ - pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters; - - /* Keep performing a calculation and checking the result against a constant. */ - for(;;) - { - d1 = 123.4567; - d2 = 2345.6789; - d3 = -918.222; - - d4 = ( d1 + d2 ) * d3; - - taskYIELD(); - - /* If the calculation does not match the expected constant, stop the - increment of the check variable. */ - if( fabs( d4 - dAnswer ) > 0.001 ) - { - vPrintDisplayMessage( &pcTaskFailMsg ); - sError = pdTRUE; - } - - if( sError == pdFALSE ) - { - /* If the calculation has always been correct, increment the check - variable so we know this task is still running okay. */ - ( *pusTaskCheckVariable )++; - } - - taskYIELD(); - } -} -/*-----------------------------------------------------------*/ - -static void vCompetingMathTask2( void *pvParameters ) -{ -portDOUBLE d1, d2, d3, d4; -volatile unsigned portSHORT *pusTaskCheckVariable; -const portDOUBLE dAnswer = ( -389.38 / 32498.2 ) * -2.0001; -const portCHAR * const pcTaskStartMsg = "Math task 2 started.\r\n"; -const portCHAR * const pcTaskFailMsg = "Math task 2 failed.\r\n"; -portSHORT sError = pdFALSE; - - /* Queue a message for printing to say the task has started. */ - vPrintDisplayMessage( &pcTaskStartMsg ); - - /* The variable this task increments to show it is still running is passed in - as the parameter. */ - pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters; - - /* Keep performing a calculation and checking the result against a constant. */ - for( ;; ) - { - d1 = -389.38; - d2 = 32498.2; - d3 = -2.0001; - - d4 = ( d1 / d2 ) * d3; - - taskYIELD(); - - /* If the calculation does not match the expected constant, stop the - increment of the check variable. */ - if( fabs( d4 - dAnswer ) > 0.001 ) - { - vPrintDisplayMessage( &pcTaskFailMsg ); - sError = pdTRUE; - } - - if( sError == pdFALSE ) - { - /* If the calculation has always been correct, increment the check - variable so we know - this task is still running okay. */ - ( *pusTaskCheckVariable )++; - } - - taskYIELD(); - } -} -/*-----------------------------------------------------------*/ - -static void vCompetingMathTask3( void *pvParameters ) -{ -portDOUBLE *pdArray, dTotal1, dTotal2, dDifference; -volatile unsigned portSHORT *pusTaskCheckVariable; -const unsigned portSHORT usArraySize = 250; -unsigned portSHORT usPosition; -const portCHAR * const pcTaskStartMsg = "Math task 3 started.\r\n"; -const portCHAR * const pcTaskFailMsg = "Math task 3 failed.\r\n"; -portSHORT sError = pdFALSE; - - /* Queue a message for printing to say the task has started. */ - vPrintDisplayMessage( &pcTaskStartMsg ); - - /* The variable this task increments to show it is still running is passed in - as the parameter. */ - pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters; - - pdArray = ( portDOUBLE * ) pvPortMalloc( ( size_t ) 250 * sizeof( portDOUBLE ) ); - - /* Keep filling an array, keeping a running total of the values placed in the - array. Then run through the array adding up all the values. If the two totals - do not match, stop the check variable from incrementing. */ - for( ;; ) - { - dTotal1 = 0.0; - dTotal2 = 0.0; - - for( usPosition = 0; usPosition < usArraySize; usPosition++ ) - { - pdArray[ usPosition ] = ( portDOUBLE ) usPosition + 5.5; - dTotal1 += ( portDOUBLE ) usPosition + 5.5; - } - - taskYIELD(); - - for( usPosition = 0; usPosition < usArraySize; usPosition++ ) - { - dTotal2 += pdArray[ usPosition ]; - } - - dDifference = dTotal1 - dTotal2; - if( fabs( dDifference ) > 0.001 ) - { - vPrintDisplayMessage( &pcTaskFailMsg ); - sError = pdTRUE; - } - - taskYIELD(); - - if( sError == pdFALSE ) - { - /* If the calculation has always been correct, increment the check - variable so we know this task is still running okay. */ - ( *pusTaskCheckVariable )++; - } - } -} -/*-----------------------------------------------------------*/ - -static void vCompetingMathTask4( void *pvParameters ) -{ -portDOUBLE *pdArray, dTotal1, dTotal2, dDifference; -volatile unsigned portSHORT *pusTaskCheckVariable; -const unsigned portSHORT usArraySize = 250; -unsigned portSHORT usPosition; -const portCHAR * const pcTaskStartMsg = "Math task 4 started.\r\n"; -const portCHAR * const pcTaskFailMsg = "Math task 4 failed.\r\n"; -portSHORT sError = pdFALSE; - - /* Queue a message for printing to say the task has started. */ - vPrintDisplayMessage( &pcTaskStartMsg ); - - /* The variable this task increments to show it is still running is passed in - as the parameter. */ - pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters; - - pdArray = ( portDOUBLE * ) pvPortMalloc( ( size_t ) 250 * sizeof( portDOUBLE ) ); - - /* Keep filling an array, keeping a running total of the values placed in the - array. Then run through the array adding up all the values. If the two totals - do not match, stop the check variable from incrementing. */ - for( ;; ) - { - dTotal1 = 0.0; - dTotal2 = 0.0; - - for( usPosition = 0; usPosition < usArraySize; usPosition++ ) - { - pdArray[ usPosition ] = ( portDOUBLE ) usPosition * 12.123; - dTotal1 += ( portDOUBLE ) usPosition * 12.123; - } - - taskYIELD(); - - for( usPosition = 0; usPosition < usArraySize; usPosition++ ) - { - dTotal2 += pdArray[ usPosition ]; - } - - dDifference = dTotal1 - dTotal2; - if( fabs( dDifference ) > 0.001 ) - { - vPrintDisplayMessage( &pcTaskFailMsg ); - sError = pdTRUE; - } - - taskYIELD(); - - if( sError == pdFALSE ) - { - /* If the calculation has always been correct, increment the check - variable so we know this task is still running okay. */ - ( *pusTaskCheckVariable )++; - } - } -} -/*-----------------------------------------------------------*/ - -/* This is called to check that all the created tasks are still running. */ -portBASE_TYPE xAreMathsTaskStillRunning( void ) -{ -/* Keep a history of the check variables so we know if they have been incremented -since the last call. */ -static unsigned portSHORT usLastTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned portSHORT ) 0 }; -portBASE_TYPE xReturn = pdTRUE, xTask; - - /* Check the maths tasks are still running by ensuring their check variables - are still incrementing. */ - for( xTask = 0; xTask < mathNUMBER_OF_TASKS; xTask++ ) - { - if( usTaskCheck[ xTask ] == usLastTaskCheck[ xTask ] ) - { - /* The check has not incremented so an error exists. */ - xReturn = pdFALSE; - } - - usLastTaskCheck[ xTask ] = usTaskCheck[ xTask ]; - } - - return xReturn; -} - - - diff --git a/Demo/Common/Full/integer.c b/Demo/Common/Full/integer.c deleted file mode 100644 index 3172faab1..000000000 --- a/Demo/Common/Full/integer.c +++ /dev/null @@ -1,332 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V1.2.3 - - + The created tasks now include calls to tskYIELD(), allowing them to be used - with the cooperative scheduler. -*/ - -/** - * This does the same as flop. c, but uses variables of type long instead of - * type double. - * - * As with flop. c, the tasks created in this file are a good test of the - * scheduler context switch mechanism. The processor has to access 32bit - * variables in two or four chunks (depending on the processor). The low - * priority of these tasks means there is a high probability that a context - * switch will occur mid calculation. See the flop. c documentation for - * more information. - * - * \page IntegerC integer.c - * \ingroup DemoFiles - *
- */ - -/* -Changes from V1.2.1 - - + The constants used in the calculations are larger to ensure the - optimiser does not truncate them to 16 bits. -*/ - -#include - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" -#include "print.h" - -/* Demo program include files. */ -#include "integer.h" - -#define intgSTACK_SIZE ( ( unsigned portSHORT ) 256 ) -#define intgNUMBER_OF_TASKS ( 8 ) - -/* Four tasks, each of which performs a different calculation on four byte -variables. Each of the four is created twice. */ -static void vCompeteingIntMathTask1( void *pvParameters ); -static void vCompeteingIntMathTask2( void *pvParameters ); -static void vCompeteingIntMathTask3( void *pvParameters ); -static void vCompeteingIntMathTask4( void *pvParameters ); - -/* These variables are used to check that all the tasks are still running. If a -task gets a calculation wrong it will stop incrementing its check variable. */ -static volatile unsigned portSHORT usTaskCheck[ intgNUMBER_OF_TASKS ] = { ( unsigned portSHORT ) 0 }; -/*-----------------------------------------------------------*/ - -void vStartIntegerMathTasks( unsigned portBASE_TYPE uxPriority ) -{ - xTaskCreate( vCompeteingIntMathTask1, "IntMath1", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 0 ] ), uxPriority, NULL ); - xTaskCreate( vCompeteingIntMathTask2, "IntMath2", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 1 ] ), uxPriority, NULL ); - xTaskCreate( vCompeteingIntMathTask3, "IntMath3", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 2 ] ), uxPriority, NULL ); - xTaskCreate( vCompeteingIntMathTask4, "IntMath4", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 3 ] ), uxPriority, NULL ); - xTaskCreate( vCompeteingIntMathTask1, "IntMath5", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 4 ] ), uxPriority, NULL ); - xTaskCreate( vCompeteingIntMathTask2, "IntMath6", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 5 ] ), uxPriority, NULL ); - xTaskCreate( vCompeteingIntMathTask3, "IntMath7", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 6 ] ), uxPriority, NULL ); - xTaskCreate( vCompeteingIntMathTask4, "IntMath8", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 7 ] ), uxPriority, NULL ); -} -/*-----------------------------------------------------------*/ - -static void vCompeteingIntMathTask1( void *pvParameters ) -{ -portLONG l1, l2, l3, l4; -portSHORT sError = pdFALSE; -volatile unsigned portSHORT *pusTaskCheckVariable; -const portLONG lAnswer = ( ( portLONG ) 74565L + ( portLONG ) 1234567L ) * ( portLONG ) -918L; -const portCHAR * const pcTaskStartMsg = "Integer math task 1 started.\r\n"; -const portCHAR * const pcTaskFailMsg = "Integer math task 1 failed.\r\n"; - - /* Queue a message for printing to say the task has started. */ - vPrintDisplayMessage( &pcTaskStartMsg ); - - /* The variable this task increments to show it is still running is passed in - as the parameter. */ - pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters; - - /* Keep performing a calculation and checking the result against a constant. */ - for(;;) - { - l1 = ( portLONG ) 74565L; - l2 = ( portLONG ) 1234567L; - l3 = ( portLONG ) -918L; - - l4 = ( l1 + l2 ) * l3; - - taskYIELD(); - - /* If the calculation does not match the expected constant, stop the - increment of the check variable. */ - if( l4 != lAnswer ) - { - vPrintDisplayMessage( &pcTaskFailMsg ); - sError = pdTRUE; - } - - if( sError == pdFALSE ) - { - /* If the calculation has always been correct, increment the check - variable so we know this task is still running okay. */ - ( *pusTaskCheckVariable )++; - } - } -} -/*-----------------------------------------------------------*/ - -static void vCompeteingIntMathTask2( void *pvParameters ) -{ -portLONG l1, l2, l3, l4; -portSHORT sError = pdFALSE; -volatile unsigned portSHORT *pusTaskCheckVariable; -const portLONG lAnswer = ( ( portLONG ) -389000L / ( portLONG ) 329999L ) * ( portLONG ) -89L; -const portCHAR * const pcTaskStartMsg = "Integer math task 2 started.\r\n"; -const portCHAR * const pcTaskFailMsg = "Integer math task 2 failed.\r\n"; - - /* Queue a message for printing to say the task has started. */ - vPrintDisplayMessage( &pcTaskStartMsg ); - - /* The variable this task increments to show it is still running is passed in - as the parameter. */ - pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters; - - /* Keep performing a calculation and checking the result against a constant. */ - for( ;; ) - { - l1 = -389000L; - l2 = 329999L; - l3 = -89L; - - l4 = ( l1 / l2 ) * l3; - - taskYIELD(); - - /* If the calculation does not match the expected constant, stop the - increment of the check variable. */ - if( l4 != lAnswer ) - { - vPrintDisplayMessage( &pcTaskFailMsg ); - sError = pdTRUE; - } - - if( sError == pdFALSE ) - { - /* If the calculation has always been correct, increment the check - variable so we know this task is still running okay. */ - ( *pusTaskCheckVariable )++; - } - } -} -/*-----------------------------------------------------------*/ - -static void vCompeteingIntMathTask3( void *pvParameters ) -{ -portLONG *plArray, lTotal1, lTotal2; -portSHORT sError = pdFALSE; -volatile unsigned portSHORT *pusTaskCheckVariable; -const unsigned portSHORT usArraySize = ( unsigned portSHORT ) 250; -unsigned portSHORT usPosition; -const portCHAR * const pcTaskStartMsg = "Integer math task 3 started.\r\n"; -const portCHAR * const pcTaskFailMsg = "Integer math task 3 failed.\r\n"; - - /* Queue a message for printing to say the task has started. */ - vPrintDisplayMessage( &pcTaskStartMsg ); - - /* The variable this task increments to show it is still running is passed in - as the parameter. */ - pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters; - - /* Create the array we are going to use for our check calculation. */ - plArray = ( portLONG * ) pvPortMalloc( ( size_t ) 250 * sizeof( portLONG ) ); - - /* Keep filling the array, keeping a running total of the values placed in the - array. Then run through the array adding up all the values. If the two totals - do not match, stop the check variable from incrementing. */ - for( ;; ) - { - lTotal1 = ( portLONG ) 0; - lTotal2 = ( portLONG ) 0; - - for( usPosition = 0; usPosition < usArraySize; usPosition++ ) - { - plArray[ usPosition ] = ( portLONG ) usPosition + ( portLONG ) 5; - lTotal1 += ( portLONG ) usPosition + ( portLONG ) 5; - } - - taskYIELD(); - - for( usPosition = 0; usPosition < usArraySize; usPosition++ ) - { - lTotal2 += plArray[ usPosition ]; - } - - if( lTotal1 != lTotal2 ) - { - vPrintDisplayMessage( &pcTaskFailMsg ); - sError = pdTRUE; - } - - taskYIELD(); - - if( sError == pdFALSE ) - { - /* If the calculation has always been correct, increment the check - variable so we know this task is still running okay. */ - ( *pusTaskCheckVariable )++; - } - } -} -/*-----------------------------------------------------------*/ - -static void vCompeteingIntMathTask4( void *pvParameters ) -{ -portLONG *plArray, lTotal1, lTotal2; -portSHORT sError = pdFALSE; -volatile unsigned portSHORT *pusTaskCheckVariable; -const unsigned portSHORT usArraySize = 250; -unsigned portSHORT usPosition; -const portCHAR * const pcTaskStartMsg = "Integer math task 4 started.\r\n"; -const portCHAR * const pcTaskFailMsg = "Integer math task 4 failed.\r\n"; - - /* Queue a message for printing to say the task has started. */ - vPrintDisplayMessage( &pcTaskStartMsg ); - - /* The variable this task increments to show it is still running is passed in - as the parameter. */ - pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters; - - /* Create the array we are going to use for our check calculation. */ - plArray = ( portLONG * ) pvPortMalloc( ( size_t ) 250 * sizeof( portLONG ) ); - - /* Keep filling the array, keeping a running total of the values placed in the - array. Then run through the array adding up all the values. If the two totals - do not match, stop the check variable from incrementing. */ - for( ;; ) - { - lTotal1 = ( portLONG ) 0; - lTotal2 = ( portLONG ) 0; - - for( usPosition = 0; usPosition < usArraySize; usPosition++ ) - { - plArray[ usPosition ] = ( portLONG ) usPosition * ( portLONG ) 12; - lTotal1 += ( portLONG ) usPosition * ( portLONG ) 12; - } - - taskYIELD(); - - for( usPosition = 0; usPosition < usArraySize; usPosition++ ) - { - lTotal2 += plArray[ usPosition ]; - } - - - if( lTotal1 != lTotal2 ) - { - vPrintDisplayMessage( &pcTaskFailMsg ); - sError = pdTRUE; - } - - taskYIELD(); - - if( sError == pdFALSE ) - { - /* If the calculation has always been correct, increment the check - variable so we know this task is still running okay. */ - ( *pusTaskCheckVariable )++; - } - } -} -/*-----------------------------------------------------------*/ - -/* This is called to check that all the created tasks are still running. */ -portBASE_TYPE xAreIntegerMathsTaskStillRunning( void ) -{ -/* Keep a history of the check variables so we know if they have been incremented -since the last call. */ -static unsigned portSHORT usLastTaskCheck[ intgNUMBER_OF_TASKS ] = { ( unsigned portSHORT ) 0 }; -portBASE_TYPE xReturn = pdTRUE, xTask; - - /* Check the maths tasks are still running by ensuring their check variables - are still incrementing. */ - for( xTask = 0; xTask < intgNUMBER_OF_TASKS; xTask++ ) - { - if( usTaskCheck[ xTask ] == usLastTaskCheck[ xTask ] ) - { - /* The check has not incremented so an error exists. */ - xReturn = pdFALSE; - } - - usLastTaskCheck[ xTask ] = usTaskCheck[ xTask ]; - } - - return xReturn; -} diff --git a/Demo/Common/Full/print.c b/Demo/Common/Full/print.c deleted file mode 100644 index 360547a47..000000000 --- a/Demo/Common/Full/print.c +++ /dev/null @@ -1,111 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/** - * Manages a queue of strings that are waiting to be displayed. This is used to - * ensure mutual exclusion of console output. - * - * A task wishing to display a message will call vPrintDisplayMessage (), with a - * pointer to the string as the parameter. The pointer is posted onto the - * xPrintQueue queue. - * - * The task spawned in main. c blocks on xPrintQueue. When a message becomes - * available it calls pcPrintGetNextMessage () to obtain a pointer to the next - * string, then uses the functions defined in the portable layer FileIO. c to - * display the message. - * - * NOTE: - * Using console IO can disrupt real time performance - depending on the port. - * Standard C IO routines are not designed for real time applications. While - * standard IO is useful for demonstration and debugging an alternative method - * should be used if you actually require console IO as part of your application. - * - * \page PrintC print.c - * \ingroup DemoFiles - *
- */ - -/* -Changes from V2.0.0 - - + Delay periods are now specified using variables and constants of - portTickType rather than unsigned portLONG. -*/ - -#include - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "queue.h" - -/* Demo program include files. */ -#include "print.h" - -static xQueueHandle xPrintQueue; - -/*-----------------------------------------------------------*/ - -void vPrintInitialise( void ) -{ -const unsigned portBASE_TYPE uxQueueSize = 20; - - /* Create the queue on which errors will be reported. */ - xPrintQueue = xQueueCreate( uxQueueSize, ( unsigned portBASE_TYPE ) sizeof( portCHAR * ) ); -} -/*-----------------------------------------------------------*/ - -void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend ) -{ - #ifdef USE_STDIO - xQueueSend( xPrintQueue, ( void * ) ppcMessageToSend, ( portTickType ) 0 ); - #else - /* Stop warnings. */ - ( void ) ppcMessageToSend; - #endif -} -/*-----------------------------------------------------------*/ - -const portCHAR *pcPrintGetNextMessage( portTickType xPrintRate ) -{ -portCHAR *pcMessage; - - if( xQueueReceive( xPrintQueue, &pcMessage, xPrintRate ) == pdPASS ) - { - return pcMessage; - } - else - { - return NULL; - } -} - - diff --git a/Demo/Common/Full/semtest.c b/Demo/Common/Full/semtest.c deleted file mode 100644 index eda4373c5..000000000 --- a/Demo/Common/Full/semtest.c +++ /dev/null @@ -1,290 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/** - * Creates two sets of two tasks. The tasks within a set share a variable, access - * to which is guarded by a semaphore. - * - * Each task starts by attempting to obtain the semaphore. On obtaining a - * semaphore a task checks to ensure that the guarded variable has an expected - * value. It then clears the variable to zero before counting it back up to the - * expected value in increments of 1. After each increment the variable is checked - * to ensure it contains the value to which it was just set. When the starting - * value is again reached the task releases the semaphore giving the other task in - * the set a chance to do exactly the same thing. The starting value is high - * enough to ensure that a tick is likely to occur during the incrementing loop. - * - * An error is flagged if at any time during the process a shared variable is - * found to have a value other than that expected. Such an occurrence would - * suggest an error in the mutual exclusion mechanism by which access to the - * variable is restricted. - * - * The first set of two tasks poll their semaphore. The second set use blocking - * calls. - * - * \page SemTestC semtest.c - * \ingroup DemoFiles - *
- */ - -/* -Changes from V1.2.0: - - + The tasks that operate at the idle priority now use a lower expected - count than those running at a higher priority. This prevents the low - priority tasks from signaling an error because they have not been - scheduled enough time for each of them to count the shared variable to - the high value. - -Changes from V2.0.0 - - + Delay periods are now specified using variables and constants of - portTickType rather than unsigned portLONG. - -Changes from V2.1.1 - - + The stack size now uses configMINIMAL_STACK_SIZE. - + String constants made file scope to decrease stack depth on 8051 port. -*/ - -#include - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" -#include "semphr.h" - -/* Demo app include files. */ -#include "semtest.h" -#include "print.h" - -/* The value to which the shared variables are counted. */ -#define semtstBLOCKING_EXPECTED_VALUE ( ( unsigned portLONG ) 0xfff ) -#define semtstNON_BLOCKING_EXPECTED_VALUE ( ( unsigned portLONG ) 0xff ) - -#define semtstSTACK_SIZE configMINIMAL_STACK_SIZE - -#define semtstNUM_TASKS ( 4 ) - -#define semtstDELAY_FACTOR ( ( portTickType ) 10 ) - -/* The task function as described at the top of the file. */ -static void prvSemaphoreTest( void *pvParameters ); - -/* Structure used to pass parameters to each task. */ -typedef struct SEMAPHORE_PARAMETERS -{ - xSemaphoreHandle xSemaphore; - volatile unsigned portLONG *pulSharedVariable; - portTickType xBlockTime; -} xSemaphoreParameters; - -/* Variables used to check that all the tasks are still running without errors. */ -static volatile portSHORT sCheckVariables[ semtstNUM_TASKS ] = { 0 }; -static volatile portSHORT sNextCheckVariable = 0; - -/* Strings to print if USE_STDIO is defined. */ -const portCHAR * const pcPollingSemaphoreTaskError = "Guarded shared variable in unexpected state.\r\n"; -const portCHAR * const pcSemaphoreTaskStart = "Guarded shared variable task started.\r\n"; - -/*-----------------------------------------------------------*/ - -void vStartSemaphoreTasks( unsigned portBASE_TYPE uxPriority ) -{ -xSemaphoreParameters *pxFirstSemaphoreParameters, *pxSecondSemaphoreParameters; -const portTickType xBlockTime = ( portTickType ) 100; - - /* Create the structure used to pass parameters to the first two tasks. */ - pxFirstSemaphoreParameters = ( xSemaphoreParameters * ) pvPortMalloc( sizeof( xSemaphoreParameters ) ); - - if( pxFirstSemaphoreParameters != NULL ) - { - /* Create the semaphore used by the first two tasks. */ - vSemaphoreCreateBinary( pxFirstSemaphoreParameters->xSemaphore ); - - if( pxFirstSemaphoreParameters->xSemaphore != NULL ) - { - /* Create the variable which is to be shared by the first two tasks. */ - pxFirstSemaphoreParameters->pulSharedVariable = ( unsigned portLONG * ) pvPortMalloc( sizeof( unsigned portLONG ) ); - - /* Initialise the share variable to the value the tasks expect. */ - *( pxFirstSemaphoreParameters->pulSharedVariable ) = semtstNON_BLOCKING_EXPECTED_VALUE; - - /* The first two tasks do not block on semaphore calls. */ - pxFirstSemaphoreParameters->xBlockTime = ( portTickType ) 0; - - /* Spawn the first two tasks. As they poll they operate at the idle priority. */ - xTaskCreate( prvSemaphoreTest, "PolSEM1", semtstSTACK_SIZE, ( void * ) pxFirstSemaphoreParameters, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL ); - xTaskCreate( prvSemaphoreTest, "PolSEM2", semtstSTACK_SIZE, ( void * ) pxFirstSemaphoreParameters, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL ); - } - } - - /* Do exactly the same to create the second set of tasks, only this time - provide a block time for the semaphore calls. */ - pxSecondSemaphoreParameters = ( xSemaphoreParameters * ) pvPortMalloc( sizeof( xSemaphoreParameters ) ); - if( pxSecondSemaphoreParameters != NULL ) - { - vSemaphoreCreateBinary( pxSecondSemaphoreParameters->xSemaphore ); - - if( pxSecondSemaphoreParameters->xSemaphore != NULL ) - { - pxSecondSemaphoreParameters->pulSharedVariable = ( unsigned portLONG * ) pvPortMalloc( sizeof( unsigned portLONG ) ); - *( pxSecondSemaphoreParameters->pulSharedVariable ) = semtstBLOCKING_EXPECTED_VALUE; - pxSecondSemaphoreParameters->xBlockTime = xBlockTime / portTICK_RATE_MS; - - xTaskCreate( prvSemaphoreTest, "BlkSEM1", semtstSTACK_SIZE, ( void * ) pxSecondSemaphoreParameters, uxPriority, ( xTaskHandle * ) NULL ); - xTaskCreate( prvSemaphoreTest, "BlkSEM2", semtstSTACK_SIZE, ( void * ) pxSecondSemaphoreParameters, uxPriority, ( xTaskHandle * ) NULL ); - } - } -} -/*-----------------------------------------------------------*/ - -static void prvSemaphoreTest( void *pvParameters ) -{ -xSemaphoreParameters *pxParameters; -volatile unsigned portLONG *pulSharedVariable, ulExpectedValue; -unsigned portLONG ulCounter; -portSHORT sError = pdFALSE, sCheckVariableToUse; - - /* See which check variable to use. sNextCheckVariable is not semaphore - protected! */ - portENTER_CRITICAL(); - sCheckVariableToUse = sNextCheckVariable; - sNextCheckVariable++; - portEXIT_CRITICAL(); - - /* Queue a message for printing to say the task has started. */ - vPrintDisplayMessage( &pcSemaphoreTaskStart ); - - /* A structure is passed in as the parameter. This contains the shared - variable being guarded. */ - pxParameters = ( xSemaphoreParameters * ) pvParameters; - pulSharedVariable = pxParameters->pulSharedVariable; - - /* If we are blocking we use a much higher count to ensure loads of context - switches occur during the count. */ - if( pxParameters->xBlockTime > ( portTickType ) 0 ) - { - ulExpectedValue = semtstBLOCKING_EXPECTED_VALUE; - } - else - { - ulExpectedValue = semtstNON_BLOCKING_EXPECTED_VALUE; - } - - for( ;; ) - { - /* Try to obtain the semaphore. */ - if( xSemaphoreTake( pxParameters->xSemaphore, pxParameters->xBlockTime ) == pdPASS ) - { - /* We have the semaphore and so expect any other tasks using the - shared variable to have left it in the state we expect to find - it. */ - if( *pulSharedVariable != ulExpectedValue ) - { - vPrintDisplayMessage( &pcPollingSemaphoreTaskError ); - sError = pdTRUE; - } - - /* Clear the variable, then count it back up to the expected value - before releasing the semaphore. Would expect a context switch or - two during this time. */ - for( ulCounter = ( unsigned portLONG ) 0; ulCounter <= ulExpectedValue; ulCounter++ ) - { - *pulSharedVariable = ulCounter; - if( *pulSharedVariable != ulCounter ) - { - if( sError == pdFALSE ) - { - vPrintDisplayMessage( &pcPollingSemaphoreTaskError ); - } - sError = pdTRUE; - } - } - - /* Release the semaphore, and if no errors have occurred increment the check - variable. */ - if( xSemaphoreGive( pxParameters->xSemaphore ) == pdFALSE ) - { - vPrintDisplayMessage( &pcPollingSemaphoreTaskError ); - sError = pdTRUE; - } - - if( sError == pdFALSE ) - { - if( sCheckVariableToUse < semtstNUM_TASKS ) - { - ( sCheckVariables[ sCheckVariableToUse ] )++; - } - } - - /* If we have a block time then we are running at a priority higher - than the idle priority. This task takes a long time to complete - a cycle (deliberately so to test the guarding) so will be starving - out lower priority tasks. Block for some time to allow give lower - priority tasks some processor time. */ - vTaskDelay( pxParameters->xBlockTime * semtstDELAY_FACTOR ); - } - else - { - if( pxParameters->xBlockTime == ( portTickType ) 0 ) - { - /* We have not got the semaphore yet, so no point using the - processor. We are not blocking when attempting to obtain the - semaphore. */ - taskYIELD(); - } - } - } -} -/*-----------------------------------------------------------*/ - -/* This is called to check that all the created tasks are still running. */ -portBASE_TYPE xAreSemaphoreTasksStillRunning( void ) -{ -static portSHORT sLastCheckVariables[ semtstNUM_TASKS ] = { 0 }; -portBASE_TYPE xTask, xReturn = pdTRUE; - - for( xTask = 0; xTask < semtstNUM_TASKS; xTask++ ) - { - if( sLastCheckVariables[ xTask ] == sCheckVariables[ xTask ] ) - { - xReturn = pdFALSE; - } - - sLastCheckVariables[ xTask ] = sCheckVariables[ xTask ]; - } - - return xReturn; -} - - diff --git a/Demo/Common/Minimal/BlockQ.c b/Demo/Common/Minimal/BlockQ.c deleted file mode 100644 index 2cb0f1d1f..000000000 --- a/Demo/Common/Minimal/BlockQ.c +++ /dev/null @@ -1,287 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * Creates six tasks that operate on three queues as follows: - * - * The first two tasks send and receive an incrementing number to/from a queue. - * One task acts as a producer and the other as the consumer. The consumer is a - * higher priority than the producer and is set to block on queue reads. The queue - * only has space for one item - as soon as the producer posts a message on the - * queue the consumer will unblock, pre-empt the producer, and remove the item. - * - * The second two tasks work the other way around. Again the queue used only has - * enough space for one item. This time the consumer has a lower priority than the - * producer. The producer will try to post on the queue blocking when the queue is - * full. When the consumer wakes it will remove the item from the queue, causing - * the producer to unblock, pre-empt the consumer, and immediately re-fill the - * queue. - * - * The last two tasks use the same queue producer and consumer functions. This time the queue has - * enough space for lots of items and the tasks operate at the same priority. The - * producer will execute, placing items into the queue. The consumer will start - * executing when either the queue becomes full (causing the producer to block) or - * a context switch occurs (tasks of the same priority will time slice). - * - */ - -/* - -Changes from V4.1.1 - - + The second set of tasks were created the wrong way around. This has been - corrected. -*/ - - -#include - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" - -/* Demo program include files. */ -#include "BlockQ.h" - -#define blckqSTACK_SIZE configMINIMAL_STACK_SIZE -#define blckqNUM_TASK_SETS ( 3 ) - -/* Structure used to pass parameters to the blocking queue tasks. */ -typedef struct BLOCKING_QUEUE_PARAMETERS -{ - xQueueHandle xQueue; /*< The queue to be used by the task. */ - portTickType xBlockTime; /*< The block time to use on queue reads/writes. */ - volatile portSHORT *psCheckVariable; /*< Incremented on each successful cycle to check the task is still running. */ -} xBlockingQueueParameters; - -/* Task function that creates an incrementing number and posts it on a queue. */ -static portTASK_FUNCTION_PROTO( vBlockingQueueProducer, pvParameters ); - -/* Task function that removes the incrementing number from a queue and checks that -it is the expected number. */ -static portTASK_FUNCTION_PROTO( vBlockingQueueConsumer, pvParameters ); - -/* Variables which are incremented each time an item is removed from a queue, and -found to be the expected value. -These are used to check that the tasks are still running. */ -static volatile portSHORT sBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0 }; - -/* Variable which are incremented each time an item is posted on a queue. These -are used to check that the tasks are still running. */ -static volatile portSHORT sBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0 }; - -/*-----------------------------------------------------------*/ - -void vStartBlockingQueueTasks( unsigned portBASE_TYPE uxPriority ) -{ -xBlockingQueueParameters *pxQueueParameters1, *pxQueueParameters2; -xBlockingQueueParameters *pxQueueParameters3, *pxQueueParameters4; -xBlockingQueueParameters *pxQueueParameters5, *pxQueueParameters6; -const unsigned portBASE_TYPE uxQueueSize1 = 1, uxQueueSize5 = 5; -const portTickType xBlockTime = ( portTickType ) 1000 / portTICK_RATE_MS; -const portTickType xDontBlock = ( portTickType ) 0; - - /* Create the first two tasks as described at the top of the file. */ - - /* First create the structure used to pass parameters to the consumer tasks. */ - pxQueueParameters1 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); - - /* Create the queue used by the first two tasks to pass the incrementing number. - Pass a pointer to the queue in the parameter structure. */ - pxQueueParameters1->xQueue = xQueueCreate( uxQueueSize1, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) ); - - /* The consumer is created first so gets a block time as described above. */ - pxQueueParameters1->xBlockTime = xBlockTime; - - /* Pass in the variable that this task is going to increment so we can check it - is still running. */ - pxQueueParameters1->psCheckVariable = &( sBlockingConsumerCount[ 0 ] ); - - /* Create the structure used to pass parameters to the producer task. */ - pxQueueParameters2 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); - - /* Pass the queue to this task also, using the parameter structure. */ - pxQueueParameters2->xQueue = pxQueueParameters1->xQueue; - - /* The producer is not going to block - as soon as it posts the consumer will - wake and remove the item so the producer should always have room to post. */ - pxQueueParameters2->xBlockTime = xDontBlock; - - /* Pass in the variable that this task is going to increment so we can check - it is still running. */ - pxQueueParameters2->psCheckVariable = &( sBlockingProducerCount[ 0 ] ); - - - /* Note the producer has a lower priority than the consumer when the tasks are - spawned. */ - xTaskCreate( vBlockingQueueConsumer, ( signed portCHAR * ) "QConsB1", blckqSTACK_SIZE, ( void * ) pxQueueParameters1, uxPriority, NULL ); - xTaskCreate( vBlockingQueueProducer, ( signed portCHAR * ) "QProdB2", blckqSTACK_SIZE, ( void * ) pxQueueParameters2, tskIDLE_PRIORITY, NULL ); - - - - /* Create the second two tasks as described at the top of the file. This uses - the same mechanism but reverses the task priorities. */ - - pxQueueParameters3 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); - pxQueueParameters3->xQueue = xQueueCreate( uxQueueSize1, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) ); - pxQueueParameters3->xBlockTime = xDontBlock; - pxQueueParameters3->psCheckVariable = &( sBlockingProducerCount[ 1 ] ); - - pxQueueParameters4 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); - pxQueueParameters4->xQueue = pxQueueParameters3->xQueue; - pxQueueParameters4->xBlockTime = xBlockTime; - pxQueueParameters4->psCheckVariable = &( sBlockingConsumerCount[ 1 ] ); - - xTaskCreate( vBlockingQueueConsumer, ( signed portCHAR * ) "QProdB3", blckqSTACK_SIZE, ( void * ) pxQueueParameters3, tskIDLE_PRIORITY, NULL ); - xTaskCreate( vBlockingQueueProducer, ( signed portCHAR * ) "QConsB4", blckqSTACK_SIZE, ( void * ) pxQueueParameters4, uxPriority, NULL ); - - - - /* Create the last two tasks as described above. The mechanism is again just - the same. This time both parameter structures are given a block time. */ - pxQueueParameters5 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); - pxQueueParameters5->xQueue = xQueueCreate( uxQueueSize5, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) ); - pxQueueParameters5->xBlockTime = xBlockTime; - pxQueueParameters5->psCheckVariable = &( sBlockingProducerCount[ 2 ] ); - - pxQueueParameters6 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) ); - pxQueueParameters6->xQueue = pxQueueParameters5->xQueue; - pxQueueParameters6->xBlockTime = xBlockTime; - pxQueueParameters6->psCheckVariable = &( sBlockingConsumerCount[ 2 ] ); - - xTaskCreate( vBlockingQueueProducer, ( signed portCHAR * ) "QProdB5", blckqSTACK_SIZE, ( void * ) pxQueueParameters5, tskIDLE_PRIORITY, NULL ); - xTaskCreate( vBlockingQueueConsumer, ( signed portCHAR * ) "QConsB6", blckqSTACK_SIZE, ( void * ) pxQueueParameters6, tskIDLE_PRIORITY, NULL ); -} -/*-----------------------------------------------------------*/ - -static portTASK_FUNCTION( vBlockingQueueProducer, pvParameters ) -{ -unsigned portSHORT usValue = 0; -xBlockingQueueParameters *pxQueueParameters; -portSHORT sErrorEverOccurred = pdFALSE; - - pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters; - - for( ;; ) - { - if( xQueueSend( pxQueueParameters->xQueue, ( void * ) &usValue, pxQueueParameters->xBlockTime ) != pdPASS ) - { - sErrorEverOccurred = pdTRUE; - } - else - { - /* We have successfully posted a message, so increment the variable - used to check we are still running. */ - if( sErrorEverOccurred == pdFALSE ) - { - ( *pxQueueParameters->psCheckVariable )++; - } - - /* Increment the variable we are going to post next time round. The - consumer will expect the numbers to follow in numerical order. */ - ++usValue; - } - } -} -/*-----------------------------------------------------------*/ - -static portTASK_FUNCTION( vBlockingQueueConsumer, pvParameters ) -{ -unsigned portSHORT usData, usExpectedValue = 0; -xBlockingQueueParameters *pxQueueParameters; -portSHORT sErrorEverOccurred = pdFALSE; - - pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters; - - for( ;; ) - { - if( xQueueReceive( pxQueueParameters->xQueue, &usData, pxQueueParameters->xBlockTime ) == pdPASS ) - { - if( usData != usExpectedValue ) - { - /* Catch-up. */ - usExpectedValue = usData; - - sErrorEverOccurred = pdTRUE; - } - else - { - /* We have successfully received a message, so increment the - variable used to check we are still running. */ - if( sErrorEverOccurred == pdFALSE ) - { - ( *pxQueueParameters->psCheckVariable )++; - } - - /* Increment the value we expect to remove from the queue next time - round. */ - ++usExpectedValue; - } - } - } -} -/*-----------------------------------------------------------*/ - -/* This is called to check that all the created tasks are still running. */ -portBASE_TYPE xAreBlockingQueuesStillRunning( void ) -{ -static portSHORT sLastBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0 }; -static portSHORT sLastBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0, ( unsigned portSHORT ) 0 }; -portBASE_TYPE xReturn = pdPASS, xTasks; - - /* Not too worried about mutual exclusion on these variables as they are 16 - bits and we are only reading them. We also only care to see if they have - changed or not. - - Loop through each check variable to and return pdFALSE if any are found not - to have changed since the last call. */ - - for( xTasks = 0; xTasks < blckqNUM_TASK_SETS; xTasks++ ) - { - if( sBlockingConsumerCount[ xTasks ] == sLastBlockingConsumerCount[ xTasks ] ) - { - xReturn = pdFALSE; - } - sLastBlockingConsumerCount[ xTasks ] = sBlockingConsumerCount[ xTasks ]; - - - if( sBlockingProducerCount[ xTasks ] == sLastBlockingProducerCount[ xTasks ] ) - { - xReturn = pdFALSE; - } - sLastBlockingProducerCount[ xTasks ] = sBlockingProducerCount[ xTasks ]; - } - - return xReturn; -} - diff --git a/Demo/Common/Minimal/PollQ.c b/Demo/Common/Minimal/PollQ.c deleted file mode 100644 index 65ba93371..000000000 --- a/Demo/Common/Minimal/PollQ.c +++ /dev/null @@ -1,217 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * This version of PollQ. c is for use on systems that have limited stack - * space and no display facilities. The complete version can be found in - * the Demo/Common/Full directory. - * - * Creates two tasks that communicate over a single queue. One task acts as a - * producer, the other a consumer. - * - * The producer loops for three iteration, posting an incrementing number onto the - * queue each cycle. It then delays for a fixed period before doing exactly the - * same again. - * - * The consumer loops emptying the queue. Each item removed from the queue is - * checked to ensure it contains the expected value. When the queue is empty it - * blocks for a fixed period, then does the same again. - * - * All queue access is performed without blocking. The consumer completely empties - * the queue each time it runs so the producer should never find the queue full. - * - * An error is flagged if the consumer obtains an unexpected value or the producer - * find the queue is full. - */ - -/* -Changes from V2.0.0 - - + Delay periods are now specified using variables and constants of - portTickType rather than unsigned portLONG. -*/ - -#include - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" - -/* Demo program include files. */ -#include "PollQ.h" - -#define pollqSTACK_SIZE configMINIMAL_STACK_SIZE -#define pollqQUEUE_SIZE ( 10 ) -#define pollqPRODUCER_DELAY ( ( portTickType ) 200 / portTICK_RATE_MS ) -#define pollqCONSUMER_DELAY ( pollqPRODUCER_DELAY - ( portTickType ) ( 20 / portTICK_RATE_MS ) ) -#define pollqNO_DELAY ( ( portTickType ) 0 ) -#define pollqVALUES_TO_PRODUCE ( ( signed portBASE_TYPE ) 3 ) -#define pollqINITIAL_VALUE ( ( signed portBASE_TYPE ) 0 ) - -/* The task that posts the incrementing number onto the queue. */ -static portTASK_FUNCTION_PROTO( vPolledQueueProducer, pvParameters ); - -/* The task that empties the queue. */ -static portTASK_FUNCTION_PROTO( vPolledQueueConsumer, pvParameters ); - -/* Variables that are used to check that the tasks are still running with no -errors. */ -static volatile signed portBASE_TYPE xPollingConsumerCount = pollqINITIAL_VALUE, xPollingProducerCount = pollqINITIAL_VALUE; - -/*-----------------------------------------------------------*/ - -void vStartPolledQueueTasks( unsigned portBASE_TYPE uxPriority ) -{ -static xQueueHandle xPolledQueue; - - /* Create the queue used by the producer and consumer. */ - xPolledQueue = xQueueCreate( pollqQUEUE_SIZE, ( unsigned portBASE_TYPE ) sizeof( unsigned portSHORT ) ); - - /* Spawn the producer and consumer. */ - xTaskCreate( vPolledQueueConsumer, ( signed portCHAR * ) "QConsNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, ( xTaskHandle * ) NULL ); - xTaskCreate( vPolledQueueProducer, ( signed portCHAR * ) "QProdNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, ( xTaskHandle * ) NULL ); -} -/*-----------------------------------------------------------*/ - -static portTASK_FUNCTION( vPolledQueueProducer, pvParameters ) -{ -unsigned portSHORT usValue = ( unsigned portSHORT ) 0; -signed portBASE_TYPE xError = pdFALSE, xLoop; - - for( ;; ) - { - for( xLoop = 0; xLoop < pollqVALUES_TO_PRODUCE; xLoop++ ) - { - /* Send an incrementing number on the queue without blocking. */ - if( xQueueSend( *( ( xQueueHandle * ) pvParameters ), ( void * ) &usValue, pollqNO_DELAY ) != pdPASS ) - { - /* We should never find the queue full so if we get here there - has been an error. */ - xError = pdTRUE; - } - else - { - if( xError == pdFALSE ) - { - /* If an error has ever been recorded we stop incrementing the - check variable. */ - portENTER_CRITICAL(); - xPollingProducerCount++; - portEXIT_CRITICAL(); - } - - /* Update the value we are going to post next time around. */ - usValue++; - } - } - - /* Wait before we start posting again to ensure the consumer runs and - empties the queue. */ - vTaskDelay( pollqPRODUCER_DELAY ); - } -} /*lint !e818 Function prototype must conform to API. */ -/*-----------------------------------------------------------*/ - -static portTASK_FUNCTION( vPolledQueueConsumer, pvParameters ) -{ -unsigned portSHORT usData, usExpectedValue = ( unsigned portSHORT ) 0; -signed portBASE_TYPE xError = pdFALSE; - - for( ;; ) - { - /* Loop until the queue is empty. */ - while( uxQueueMessagesWaiting( *( ( xQueueHandle * ) pvParameters ) ) ) - { - if( xQueueReceive( *( ( xQueueHandle * ) pvParameters ), &usData, pollqNO_DELAY ) == pdPASS ) - { - if( usData != usExpectedValue ) - { - /* This is not what we expected to receive so an error has - occurred. */ - xError = pdTRUE; - - /* Catch-up to the value we received so our next expected - value should again be correct. */ - usExpectedValue = usData; - } - else - { - if( xError == pdFALSE ) - { - /* Only increment the check variable if no errors have - occurred. */ - portENTER_CRITICAL(); - xPollingConsumerCount++; - portEXIT_CRITICAL(); - } - } - - /* Next time round we would expect the number to be one higher. */ - usExpectedValue++; - } - } - - /* Now the queue is empty we block, allowing the producer to place more - items in the queue. */ - vTaskDelay( pollqCONSUMER_DELAY ); - } -} /*lint !e818 Function prototype must conform to API. */ -/*-----------------------------------------------------------*/ - -/* This is called to check that all the created tasks are still running with no errors. */ -portBASE_TYPE xArePollingQueuesStillRunning( void ) -{ -portBASE_TYPE xReturn; - - /* Check both the consumer and producer poll count to check they have both - been changed since out last trip round. We do not need a critical section - around the check variables as this is called from a higher priority than - the other tasks that access the same variables. */ - if( ( xPollingConsumerCount == pollqINITIAL_VALUE ) || - ( xPollingProducerCount == pollqINITIAL_VALUE ) - ) - { - xReturn = pdFALSE; - } - else - { - xReturn = pdTRUE; - } - - /* Set the check variables back down so we know if they have been - incremented the next time around. */ - xPollingConsumerCount = pollqINITIAL_VALUE; - xPollingProducerCount = pollqINITIAL_VALUE; - - return xReturn; -} diff --git a/Demo/Common/Minimal/blocktim.c b/Demo/Common/Minimal/blocktim.c deleted file mode 100644 index 5e1be5651..000000000 --- a/Demo/Common/Minimal/blocktim.c +++ /dev/null @@ -1,467 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * This file contains some test scenarios that ensure tasks do not exit queue - * send or receive functions prematurely. A description of the tests is - * included within the code. - */ - -/* Kernel includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" - -/* Task priorities. */ -#define bktPRIMARY_PRIORITY ( 3 ) -#define bktSECONDARY_PRIORITY ( 2 ) - -/* Task behaviour. */ -#define bktQUEUE_LENGTH ( 5 ) -#define bktSHORT_WAIT ( ( ( portTickType ) 20 ) / portTICK_RATE_MS ) -#define bktPRIMARY_BLOCK_TIME ( 10 ) -#define bktALLOWABLE_MARGIN ( 12 ) -#define bktTIME_TO_BLOCK ( 175 ) -#define bktDONT_BLOCK ( ( portTickType ) 0 ) -#define bktRUN_INDICATOR ( ( unsigned portBASE_TYPE ) 0x55 ) - -/* The queue on which the tasks block. */ -static xQueueHandle xTestQueue; - -/* Handle to the secondary task is required by the primary task for calls -to vTaskSuspend/Resume(). */ -static xTaskHandle xSecondary; - -/* Used to ensure that tasks are still executing without error. */ -static portBASE_TYPE xPrimaryCycles = 0, xSecondaryCycles = 0; -static portBASE_TYPE xErrorOccurred = pdFALSE; - -/* Provides a simple mechanism for the primary task to know when the -secondary task has executed. */ -static volatile unsigned portBASE_TYPE xRunIndicator; - -/* The two test tasks. Their behaviour is commented within the files. */ -static void vPrimaryBlockTimeTestTask( void *pvParameters ); -static void vSecondaryBlockTimeTestTask( void *pvParameters ); - -/*-----------------------------------------------------------*/ - -void vCreateBlockTimeTasks( void ) -{ - /* Create the queue on which the two tasks block. */ - xTestQueue = xQueueCreate( bktQUEUE_LENGTH, sizeof( portBASE_TYPE ) ); - - /* Create the two test tasks. */ - xTaskCreate( vPrimaryBlockTimeTestTask, ( signed portCHAR * )"BTest1", configMINIMAL_STACK_SIZE, NULL, bktPRIMARY_PRIORITY, NULL ); - xTaskCreate( vSecondaryBlockTimeTestTask, ( signed portCHAR * )"BTest2", configMINIMAL_STACK_SIZE, NULL, bktSECONDARY_PRIORITY, &xSecondary ); -} -/*-----------------------------------------------------------*/ - -static void vPrimaryBlockTimeTestTask( void *pvParameters ) -{ -portBASE_TYPE xItem, xData; -portTickType xTimeWhenBlocking; -portTickType xTimeToBlock, xBlockedTime; - - for( ;; ) - { - /********************************************************************* - Test 1 - - Simple block time wakeup test on queue receives. */ - for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ ) - { - /* The queue is empty. Attempt to read from the queue using a block - time. When we wake, ensure the delta in time is as expected. */ - xTimeToBlock = bktPRIMARY_BLOCK_TIME << xItem; - - /* A critical section is used to minimise the jitter in the time - measurements. */ - portENTER_CRITICAL(); - { - xTimeWhenBlocking = xTaskGetTickCount(); - - /* We should unblock after xTimeToBlock having not received - anything on the queue. */ - if( xQueueReceive( xTestQueue, &xData, xTimeToBlock ) != errQUEUE_EMPTY ) - { - xErrorOccurred = pdTRUE; - } - - /* How long were we blocked for? */ - xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking; - } - portEXIT_CRITICAL(); - - if( xBlockedTime < xTimeToBlock ) - { - /* Should not have blocked for less than we requested. */ - xErrorOccurred = pdTRUE; - } - - if( xBlockedTime > ( xTimeToBlock + bktALLOWABLE_MARGIN ) ) - { - /* Should not have blocked for longer than we requested, - although we would not necessarily run as soon as we were - unblocked so a margin is allowed. */ - xErrorOccurred = pdTRUE; - } - } - - /********************************************************************* - Test 2 - - Simple block time wakeup test on queue sends. - - First fill the queue. It should be empty so all sends should pass. */ - for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ ) - { - if( xQueueSend( xTestQueue, &xItem, bktDONT_BLOCK ) != pdPASS ) - { - xErrorOccurred = pdTRUE; - } - } - - for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ ) - { - /* The queue is full. Attempt to write to the queue using a block - time. When we wake, ensure the delta in time is as expected. */ - xTimeToBlock = bktPRIMARY_BLOCK_TIME << xItem; - - portENTER_CRITICAL(); - { - xTimeWhenBlocking = xTaskGetTickCount(); - - /* We should unblock after xTimeToBlock having not received - anything on the queue. */ - if( xQueueSend( xTestQueue, &xItem, xTimeToBlock ) != errQUEUE_FULL ) - { - xErrorOccurred = pdTRUE; - } - - /* How long were we blocked for? */ - xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking; - } - portEXIT_CRITICAL(); - - if( xBlockedTime < xTimeToBlock ) - { - /* Should not have blocked for less than we requested. */ - xErrorOccurred = pdTRUE; - } - - if( xBlockedTime > ( xTimeToBlock + bktALLOWABLE_MARGIN ) ) - { - /* Should not have blocked for longer than we requested, - although we would not necessarily run as soon as we were - unblocked so a margin is allowed. */ - xErrorOccurred = pdTRUE; - } - } - - - /********************************************************************* - Test 3 - - Wake the other task, it will block attempting to post to the queue. - When we read from the queue the other task will wake, but before it - can run we will post to the queue again. When the other task runs it - will find the queue still full, even though it was woken. It should - recognise that its block time has not expired and return to block for - the remains of its block time. - - Wake the other task so it blocks attempting to post to the already - full queue. */ - xRunIndicator = 0; - vTaskResume( xSecondary ); - - /* We need to wait a little to ensure the other task executes. */ - while( xRunIndicator != bktRUN_INDICATOR ) - { - /* The other task has not yet executed. */ - vTaskDelay( bktSHORT_WAIT ); - } - /* Make sure the other task is blocked on the queue. */ - vTaskDelay( bktSHORT_WAIT ); - xRunIndicator = 0; - - for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ ) - { - /* Now when we make space on the queue the other task should wake - but not execute as this task has higher priority. */ - if( xQueueReceive( xTestQueue, &xData, bktDONT_BLOCK ) != pdPASS ) - { - xErrorOccurred = pdTRUE; - } - - /* Now fill the queue again before the other task gets a chance to - execute. If the other task had executed we would find the queue - full ourselves, and the other task have set xRunIndicator. */ - if( xQueueSend( xTestQueue, &xItem, bktDONT_BLOCK ) != pdPASS ) - { - xErrorOccurred = pdTRUE; - } - - if( xRunIndicator == bktRUN_INDICATOR ) - { - /* The other task should not have executed. */ - xErrorOccurred = pdTRUE; - } - - /* Raise the priority of the other task so it executes and blocks - on the queue again. */ - vTaskPrioritySet( xSecondary, bktPRIMARY_PRIORITY + 2 ); - - /* The other task should now have re-blocked without exiting the - queue function. */ - if( xRunIndicator == bktRUN_INDICATOR ) - { - /* The other task should not have executed outside of the - queue function. */ - xErrorOccurred = pdTRUE; - } - - /* Set the priority back down. */ - vTaskPrioritySet( xSecondary, bktSECONDARY_PRIORITY ); - } - - /* Let the other task timeout. When it unblockes it will check that it - unblocked at the correct time, then suspend itself. */ - while( xRunIndicator != bktRUN_INDICATOR ) - { - vTaskDelay( bktSHORT_WAIT ); - } - vTaskDelay( bktSHORT_WAIT ); - xRunIndicator = 0; - - - /********************************************************************* - Test 4 - - As per test 3 - but with the send and receive the other way around. - The other task blocks attempting to read from the queue. - - Empty the queue. We should find that it is full. */ - for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ ) - { - if( xQueueReceive( xTestQueue, &xData, bktDONT_BLOCK ) != pdPASS ) - { - xErrorOccurred = pdTRUE; - } - } - - /* Wake the other task so it blocks attempting to read from the - already empty queue. */ - vTaskResume( xSecondary ); - - /* We need to wait a little to ensure the other task executes. */ - while( xRunIndicator != bktRUN_INDICATOR ) - { - vTaskDelay( bktSHORT_WAIT ); - } - vTaskDelay( bktSHORT_WAIT ); - xRunIndicator = 0; - - for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ ) - { - /* Now when we place an item on the queue the other task should - wake but not execute as this task has higher priority. */ - if( xQueueSend( xTestQueue, &xItem, bktDONT_BLOCK ) != pdPASS ) - { - xErrorOccurred = pdTRUE; - } - - /* Now empty the queue again before the other task gets a chance to - execute. If the other task had executed we would find the queue - empty ourselves, and the other task would be suspended. */ - if( xQueueReceive( xTestQueue, &xData, bktDONT_BLOCK ) != pdPASS ) - { - xErrorOccurred = pdTRUE; - } - - if( xRunIndicator == bktRUN_INDICATOR ) - { - /* The other task should not have executed. */ - xErrorOccurred = pdTRUE; - } - - /* Raise the priority of the other task so it executes and blocks - on the queue again. */ - vTaskPrioritySet( xSecondary, bktPRIMARY_PRIORITY + 2 ); - - /* The other task should now have re-blocked without exiting the - queue function. */ - if( xRunIndicator == bktRUN_INDICATOR ) - { - /* The other task should not have executed outside of the - queue function. */ - xErrorOccurred = pdTRUE; - } - vTaskPrioritySet( xSecondary, bktSECONDARY_PRIORITY ); - } - - /* Let the other task timeout. When it unblockes it will check that it - unblocked at the correct time, then suspend itself. */ - while( xRunIndicator != bktRUN_INDICATOR ) - { - vTaskDelay( bktSHORT_WAIT ); - } - vTaskDelay( bktSHORT_WAIT ); - - xPrimaryCycles++; - } -} -/*-----------------------------------------------------------*/ - -static void vSecondaryBlockTimeTestTask( void *pvParameters ) -{ -portTickType xTimeWhenBlocking, xBlockedTime; -portBASE_TYPE xData; - - for( ;; ) - { - /********************************************************************* - Test 1 and 2 - - This task does does not participate in these tests. */ - vTaskSuspend( NULL ); - - /********************************************************************* - Test 3 - - The first thing we do is attempt to read from the queue. It should be - full so we block. Note the time before we block so we can check the - wake time is as per that expected. */ - portENTER_CRITICAL(); - { - xTimeWhenBlocking = xTaskGetTickCount(); - - /* We should unblock after bktTIME_TO_BLOCK having not received - anything on the queue. */ - xData = 0; - xRunIndicator = bktRUN_INDICATOR; - if( xQueueSend( xTestQueue, &xData, bktTIME_TO_BLOCK ) != errQUEUE_FULL ) - { - xErrorOccurred = pdTRUE; - } - - /* How long were we inside the send function? */ - xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking; - } - portEXIT_CRITICAL(); - - /* We should not have blocked for less time than bktTIME_TO_BLOCK. */ - if( xBlockedTime < bktTIME_TO_BLOCK ) - { - xErrorOccurred = pdTRUE; - } - - /* We should of not blocked for much longer than bktALLOWABLE_MARGIN - either. A margin is permitted as we would not necessarily run as - soon as we unblocked. */ - if( xBlockedTime > ( bktTIME_TO_BLOCK + bktALLOWABLE_MARGIN ) ) - { - xErrorOccurred = pdTRUE; - } - - /* Suspend ready for test 3. */ - xRunIndicator = bktRUN_INDICATOR; - vTaskSuspend( NULL ); - - /********************************************************************* - Test 4 - - As per test three, but with the send and receive reversed. */ - portENTER_CRITICAL(); - { - xTimeWhenBlocking = xTaskGetTickCount(); - - /* We should unblock after bktTIME_TO_BLOCK having not received - anything on the queue. */ - xRunIndicator = bktRUN_INDICATOR; - if( xQueueReceive( xTestQueue, &xData, bktTIME_TO_BLOCK ) != errQUEUE_EMPTY ) - { - xErrorOccurred = pdTRUE; - } - - xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking; - } - portEXIT_CRITICAL(); - - /* We should not have blocked for less time than bktTIME_TO_BLOCK. */ - if( xBlockedTime < bktTIME_TO_BLOCK ) - { - xErrorOccurred = pdTRUE; - } - - /* We should of not blocked for much longer than bktALLOWABLE_MARGIN - either. A margin is permitted as we would not necessarily run as soon - as we unblocked. */ - if( xBlockedTime > ( bktTIME_TO_BLOCK + bktALLOWABLE_MARGIN ) ) - { - xErrorOccurred = pdTRUE; - } - - xRunIndicator = bktRUN_INDICATOR; - - xSecondaryCycles++; - } -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xAreBlockTimeTestTasksStillRunning( void ) -{ -static portBASE_TYPE xLastPrimaryCycleCount = 0, xLastSecondaryCycleCount = 0; -portBASE_TYPE xReturn = pdPASS; - - /* Have both tasks performed at least one cycle since this function was - last called? */ - if( xPrimaryCycles == xLastPrimaryCycleCount ) - { - xReturn = pdFAIL; - } - - if( xSecondaryCycles == xLastSecondaryCycleCount ) - { - xReturn = pdFAIL; - } - - if( xErrorOccurred == pdTRUE ) - { - xReturn = pdFAIL; - } - - xLastSecondaryCycleCount = xSecondaryCycles; - xLastPrimaryCycleCount = xPrimaryCycles; - - return xReturn; -} diff --git a/Demo/Common/Minimal/comtest.c b/Demo/Common/Minimal/comtest.c deleted file mode 100644 index 68e7f9d49..000000000 --- a/Demo/Common/Minimal/comtest.c +++ /dev/null @@ -1,287 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/* - * This version of comtest. c is for use on systems that have limited stack - * space and no display facilities. The complete version can be found in - * the Demo/Common/Full directory. - * - * Creates two tasks that operate on an interrupt driven serial port. A - * loopback connector should be used so that everything that is transmitted is - * also received. The serial port does not use any flow control. On a - * standard 9way 'D' connector pins two and three should be connected together. - * - * The first task posts a sequence of characters to the Tx queue, toggling an - * LED on each successful post. At the end of the sequence it sleeps for a - * pseudo-random period before resending the same sequence. - * - * The UART Tx end interrupt is enabled whenever data is available in the Tx - * queue. The Tx end ISR removes a single character from the Tx queue and - * passes it to the UART for transmission. - * - * The second task blocks on the Rx queue waiting for a character to become - * available. When the UART Rx end interrupt receives a character it places - * it in the Rx queue, waking the second task. The second task checks that the - * characters removed from the Rx queue form the same sequence as those posted - * to the Tx queue, and toggles an LED for each correct character. - * - * The receiving task is spawned with a higher priority than the transmitting - * task. The receiver will therefore wake every time a character is - * transmitted so neither the Tx or Rx queue should ever hold more than a few - * characters. - * - */ - -/* -Changes from V1.2.0: - - + Reduced the maximum time between successive transmissions. This provides - for a more rigorous test. - -Changes from V2.0.0 - - + Delay periods are now specified using variables and constants of - portTickType rather than unsigned portLONG. - -Changes from V2.5.1 - - + The constant comOFFSET_TIME added to the delay period to ensure a more - random delay period is used. -*/ - -/* Scheduler include files. */ -#include -#include "FreeRTOS.h" -#include "task.h" - -/* Demo program include files. */ -#include "serial.h" -#include "comtest.h" -#include "partest.h" - -#define comSTACK_SIZE configMINIMAL_STACK_SIZE -#define comTX_LED_OFFSET ( 0 ) -#define comRX_LED_OFFSET ( 1 ) -#define comTOTAL_PERMISSIBLE_ERRORS ( 2 ) - -/* The Tx task will transmit the sequence of characters at a pseudo random -interval. This is the maximum and minimum block time between sends. */ -#define comTX_MAX_BLOCK_TIME ( ( portTickType ) 0x96 ) -#define comTX_MIN_BLOCK_TIME ( ( portTickType ) 0x32 ) -#define comOFFSET_TIME ( ( portTickType ) 3 ) - -/* We should find that each character can be queued for Tx immediately and we -don't have to block to send. */ -#define comNO_BLOCK ( ( portTickType ) 0 ) - -/* The Rx task will block on the Rx queue for a long period. */ -#define comRX_BLOCK_TIME ( ( portTickType ) 0xffff ) - -/* The sequence transmitted is from comFIRST_BYTE to and including comLAST_BYTE. */ -#define comFIRST_BYTE ( 'A' ) -#define comLAST_BYTE ( 'X' ) - -#define comBUFFER_LEN ( ( unsigned portBASE_TYPE ) ( comLAST_BYTE - comFIRST_BYTE ) + ( unsigned portBASE_TYPE ) 1 ) -#define comINITIAL_RX_COUNT_VALUE ( 0 ) - -/* Handle to the com port used by both tasks. */ -static xComPortHandle xPort = NULL; - -/* The transmit task as described at the top of the file. */ -static portTASK_FUNCTION_PROTO( vComTxTask, pvParameters ); - -/* The receive task as described at the top of the file. */ -static portTASK_FUNCTION_PROTO( vComRxTask, pvParameters ); - -/* The LED that should be toggled by the Rx and Tx tasks. The Rx task will -toggle LED ( uxBaseLED + comRX_LED_OFFSET). The Tx task will toggle LED -( uxBaseLED + comTX_LED_OFFSET ). */ -static unsigned portBASE_TYPE uxBaseLED = 0; - -/* Check variable used to ensure no error have occurred. The Rx task will -increment this variable after every successfully received sequence. If at any -time the sequence is incorrect the the variable will stop being incremented. */ -static volatile unsigned portBASE_TYPE uxRxLoops = comINITIAL_RX_COUNT_VALUE; - -/*-----------------------------------------------------------*/ - -void vAltStartComTestTasks( unsigned portBASE_TYPE uxPriority, unsigned portLONG ulBaudRate, unsigned portBASE_TYPE uxLED ) -{ - /* Initialise the com port then spawn the Rx and Tx tasks. */ - uxBaseLED = uxLED; - xSerialPortInitMinimal( ulBaudRate, comBUFFER_LEN ); - - /* The Tx task is spawned with a lower priority than the Rx task. */ - xTaskCreate( vComTxTask, ( const signed portCHAR * const ) "COMTx", comSTACK_SIZE, NULL, uxPriority - 1, ( xTaskHandle * ) NULL ); - xTaskCreate( vComRxTask, ( const signed portCHAR * const ) "COMRx", comSTACK_SIZE, NULL, uxPriority, ( xTaskHandle * ) NULL ); -} -/*-----------------------------------------------------------*/ - -static portTASK_FUNCTION( vComTxTask, pvParameters ) -{ -signed portCHAR cByteToSend; -portTickType xTimeToWait; - - /* Just to stop compiler warnings. */ - ( void ) pvParameters; - - for( ;; ) - { - /* Simply transmit a sequence of characters from comFIRST_BYTE to - comLAST_BYTE. */ - for( cByteToSend = comFIRST_BYTE; cByteToSend <= comLAST_BYTE; cByteToSend++ ) - { - if( xSerialPutChar( xPort, cByteToSend, comNO_BLOCK ) == pdPASS ) - { - vParTestToggleLED( uxBaseLED + comTX_LED_OFFSET ); - } - } - - /* Turn the LED off while we are not doing anything. */ - vParTestSetLED( uxBaseLED + comTX_LED_OFFSET, pdFALSE ); - - /* We have posted all the characters in the string - wait before - re-sending. Wait a pseudo-random time as this will provide a better - test. */ - xTimeToWait = xTaskGetTickCount() + comOFFSET_TIME; - - /* Make sure we don't wait too long... */ - xTimeToWait %= comTX_MAX_BLOCK_TIME; - - /* ...but we do want to wait. */ - if( xTimeToWait < comTX_MIN_BLOCK_TIME ) - { - xTimeToWait = comTX_MIN_BLOCK_TIME; - } - - vTaskDelay( xTimeToWait ); - } -} /*lint !e715 !e818 pvParameters is required for a task function even if it is not referenced. */ -/*-----------------------------------------------------------*/ - -static portTASK_FUNCTION( vComRxTask, pvParameters ) -{ -signed portCHAR cExpectedByte, cByteRxed; -portBASE_TYPE xResyncRequired = pdFALSE, xErrorOccurred = pdFALSE; - - /* Just to stop compiler warnings. */ - ( void ) pvParameters; - - for( ;; ) - { - /* We expect to receive the characters from comFIRST_BYTE to - comLAST_BYTE in an incrementing order. Loop to receive each byte. */ - for( cExpectedByte = comFIRST_BYTE; cExpectedByte <= comLAST_BYTE; cExpectedByte++ ) - { - /* Block on the queue that contains received bytes until a byte is - available. */ - if( xSerialGetChar( xPort, &cByteRxed, comRX_BLOCK_TIME ) ) - { - /* Was this the byte we were expecting? If so, toggle the LED, - otherwise we are out on sync and should break out of the loop - until the expected character sequence is about to restart. */ - if( cByteRxed == cExpectedByte ) - { - vParTestToggleLED( uxBaseLED + comRX_LED_OFFSET ); - } - else - { - xResyncRequired = pdTRUE; - break; /*lint !e960 Non-switch break allowed. */ - } - } - } - - /* Turn the LED off while we are not doing anything. */ - vParTestSetLED( uxBaseLED + comRX_LED_OFFSET, pdFALSE ); - - /* Did we break out of the loop because the characters were received in - an unexpected order? If so wait here until the character sequence is - about to restart. */ - if( xResyncRequired == pdTRUE ) - { - while( cByteRxed != comLAST_BYTE ) - { - /* Block until the next char is available. */ - xSerialGetChar( xPort, &cByteRxed, comRX_BLOCK_TIME ); - } - - /* Note that an error occurred which caused us to have to resync. - We use this to stop incrementing the loop counter so - sAreComTestTasksStillRunning() will return false - indicating an - error. */ - xErrorOccurred++; - - /* We have now resynced with the Tx task and can continue. */ - xResyncRequired = pdFALSE; - } - else - { - if( xErrorOccurred < comTOTAL_PERMISSIBLE_ERRORS ) - { - /* Increment the count of successful loops. As error - occurring (i.e. an unexpected character being received) will - prevent this counter being incremented for the rest of the - execution. Don't worry about mutual exclusion on this - variable - it doesn't really matter as we just want it - to change. */ - uxRxLoops++; - } - } - } -} /*lint !e715 !e818 pvParameters is required for a task function even if it is not referenced. */ -/*-----------------------------------------------------------*/ - -portBASE_TYPE xAreComTestTasksStillRunning( void ) -{ -portBASE_TYPE xReturn; - - /* If the count of successful reception loops has not changed than at - some time an error occurred (i.e. a character was received out of sequence) - and we will return false. */ - if( uxRxLoops == comINITIAL_RX_COUNT_VALUE ) - { - xReturn = pdFALSE; - } - else - { - xReturn = pdTRUE; - } - - /* Reset the count of successful Rx loops. When this function is called - again we expect this to have been incremented. */ - uxRxLoops = comINITIAL_RX_COUNT_VALUE; - - return xReturn; -} - diff --git a/Demo/Common/Minimal/crflash.c b/Demo/Common/Minimal/crflash.c deleted file mode 100644 index 1fc801d43..000000000 --- a/Demo/Common/Minimal/crflash.c +++ /dev/null @@ -1,213 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * This demo application file demonstrates the use of queues to pass data - * between co-routines. - * - * N represents the number of 'fixed delay' co-routines that are created and - * is set during initialisation. - * - * N 'fixed delay' co-routines are created that just block for a fixed - * period then post the number of an LED onto a queue. Each such co-routine - * uses a different block period. A single 'flash' co-routine is also created - * that blocks on the same queue, waiting for the number of the next LED it - * should flash. Upon receiving a number it simply toggle the instructed LED - * then blocks on the queue once more. In this manner each LED from LED 0 to - * LED N-1 is caused to flash at a different rate. - * - * The 'fixed delay' co-routines are created with co-routine priority 0. The - * flash co-routine is created with co-routine priority 1. This means that - * the queue should never contain more than a single item. This is because - * posting to the queue will unblock the 'flash' co-routine, and as this has - * a priority greater than the tasks posting to the queue it is guaranteed to - * have emptied the queue and blocked once again before the queue can contain - * any more date. An error is indicated if an attempt to post data to the - * queue fails - indicating that the queue is already full. - * - */ - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "croutine.h" -#include "queue.h" - -/* Demo application includes. */ -#include "partest.h" -#include "crflash.h" - -/* The queue should only need to be of length 1. See the description at the -top of the file. */ -#define crfQUEUE_LENGTH 1 - -#define crfFIXED_DELAY_PRIORITY 0 -#define crfFLASH_PRIORITY 1 - -/* Only one flash co-routine is created so the index is not significant. */ -#define crfFLASH_INDEX 0 - -/* Don't allow more than crfMAX_FLASH_TASKS 'fixed delay' co-routines to be -created. */ -#define crfMAX_FLASH_TASKS 8 - -/* We don't want to block when posting to the queue. */ -#define crfPOSTING_BLOCK_TIME 0 - -/* - * The 'fixed delay' co-routine as described at the top of the file. - */ -static void prvFixedDelayCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); - -/* - * The 'flash' co-routine as described at the top of the file. - */ -static void prvFlashCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); - -/* The queue used to pass data between the 'fixed delay' co-routines and the -'flash' co-routine. */ -static xQueueHandle xFlashQueue; - -/* This will be set to pdFALSE if we detect an error. */ -static unsigned portBASE_TYPE uxCoRoutineFlashStatus = pdPASS; - -/*-----------------------------------------------------------*/ - -/* - * See the header file for details. - */ -void vStartFlashCoRoutines( unsigned portBASE_TYPE uxNumberToCreate ) -{ -unsigned portBASE_TYPE uxIndex; - - if( uxNumberToCreate > crfMAX_FLASH_TASKS ) - { - uxNumberToCreate = crfMAX_FLASH_TASKS; - } - - /* Create the queue used to pass data between the co-routines. */ - xFlashQueue = xQueueCreate( crfQUEUE_LENGTH, sizeof( unsigned portBASE_TYPE ) ); - - if( xFlashQueue ) - { - /* Create uxNumberToCreate 'fixed delay' co-routines. */ - for( uxIndex = 0; uxIndex < uxNumberToCreate; uxIndex++ ) - { - xCoRoutineCreate( prvFixedDelayCoRoutine, crfFIXED_DELAY_PRIORITY, uxIndex ); - } - - /* Create the 'flash' co-routine. */ - xCoRoutineCreate( prvFlashCoRoutine, crfFLASH_PRIORITY, crfFLASH_INDEX ); - } -} -/*-----------------------------------------------------------*/ - -static void prvFixedDelayCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) -{ -/* Even though this is a co-routine the xResult variable does not need to be -static as we do not need it to maintain its state between blocks. */ -signed portBASE_TYPE xResult; -/* The uxIndex parameter of the co-routine function is used as an index into -the xFlashRates array to obtain the delay period to use. */ -static const portTickType xFlashRates[ crfMAX_FLASH_TASKS ] = { 150 / portTICK_RATE_MS, - 200 / portTICK_RATE_MS, - 250 / portTICK_RATE_MS, - 300 / portTICK_RATE_MS, - 350 / portTICK_RATE_MS, - 400 / portTICK_RATE_MS, - 450 / portTICK_RATE_MS, - 500 / portTICK_RATE_MS }; - - /* Co-routines MUST start with a call to crSTART. */ - crSTART( xHandle ); - - for( ;; ) - { - /* Post our uxIndex value onto the queue. This is used as the LED to - flash. */ - crQUEUE_SEND( xHandle, xFlashQueue, ( void * ) &uxIndex, crfPOSTING_BLOCK_TIME, &xResult ); - - if( xResult != pdPASS ) - { - /* For the reasons stated at the top of the file we should always - find that we can post to the queue. If we could not then an error - has occurred. */ - uxCoRoutineFlashStatus = pdFAIL; - } - - crDELAY( xHandle, xFlashRates[ uxIndex ] ); - } - - /* Co-routines MUST end with a call to crEND. */ - crEND(); -} -/*-----------------------------------------------------------*/ - -static void prvFlashCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) -{ -/* Even though this is a co-routine the variable do not need to be -static as we do not need it to maintain their state between blocks. */ -signed portBASE_TYPE xResult; -unsigned portBASE_TYPE uxLEDToFlash; - - /* Co-routines MUST start with a call to crSTART. */ - crSTART( xHandle ); - ( void ) uxIndex; - - for( ;; ) - { - /* Block to wait for the number of the LED to flash. */ - crQUEUE_RECEIVE( xHandle, xFlashQueue, &uxLEDToFlash, portMAX_DELAY, &xResult ); - - if( xResult != pdPASS ) - { - /* We would not expect to wake unless we received something. */ - uxCoRoutineFlashStatus = pdFAIL; - } - else - { - /* We received the number of an LED to flash - flash it! */ - vParTestToggleLED( uxLEDToFlash ); - } - } - - /* Co-routines MUST end with a call to crEND. */ - crEND(); -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xAreFlashCoRoutinesStillRunning( void ) -{ - /* Return pdPASS or pdFAIL depending on whether an error has been detected - or not. */ - return uxCoRoutineFlashStatus; -} - diff --git a/Demo/Common/Minimal/crhook.c b/Demo/Common/Minimal/crhook.c deleted file mode 100644 index 53308d0de..000000000 --- a/Demo/Common/Minimal/crhook.c +++ /dev/null @@ -1,237 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * This demo file demonstrates how to send data between an ISR and a - * co-routine. A tick hook function is used to periodically pass data between - * the RTOS tick and a set of 'hook' co-routines. - * - * hookNUM_HOOK_CO_ROUTINES co-routines are created. Each co-routine blocks - * to wait for a character to be received on a queue from the tick ISR, checks - * to ensure the character received was that expected, then sends the number - * back to the tick ISR on a different queue. - * - * The tick ISR checks the numbers received back from the 'hook' co-routines - * matches the number previously sent. - * - * If at any time a queue function returns unexpectedly, or an incorrect value - * is received either by the tick hook or a co-routine then an error is - * latched. - * - * This demo relies on each 'hook' co-routine to execute between each - * hookTICK_CALLS_BEFORE_POST tick interrupts. This and the heavy use of - * queues from within an interrupt may result in an error being detected on - * slower targets simply due to timing. - */ - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "croutine.h" -#include "queue.h" - -/* Demo application includes. */ -#include "crhook.h" - -/* The number of 'hook' co-routines that are to be created. */ -#define hookNUM_HOOK_CO_ROUTINES ( 4 ) - -/* The number of times the tick hook should be called before a character is -posted to the 'hook' co-routines. */ -#define hookTICK_CALLS_BEFORE_POST ( 250 ) - -/* There should never be more than one item in any queue at any time. */ -#define hookHOOK_QUEUE_LENGTH ( 1 ) - -/* Don't block when initially posting to the queue. */ -#define hookNO_BLOCK_TIME ( 0 ) - -/* The priority relative to other co-routines (rather than tasks) that the -'hook' co-routines should take. */ -#define mainHOOK_CR_PRIORITY ( 1 ) -/*-----------------------------------------------------------*/ - -/* - * The co-routine function itself. - */ -static void prvHookCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ); - - -/* - * The tick hook function. This receives a number from each 'hook' co-routine - * then sends a number to each co-routine. An error is flagged if a send or - * receive fails, or an unexpected number is received. - */ -void vApplicationTickHook( void ); - -/*-----------------------------------------------------------*/ - -/* Queues used to send data FROM a co-routine TO the tick hook function. -The hook functions received (Rx's) on these queues. One queue per -'hook' co-routine. */ -static xQueueHandle xHookRxQueues[ hookNUM_HOOK_CO_ROUTINES ]; - -/* Queues used to send data FROM the tick hook TO a co-routine function. -The hood function transmits (Tx's) on these queues. One queue per -'hook' co-routine. */ -static xQueueHandle xHookTxQueues[ hookNUM_HOOK_CO_ROUTINES ]; - -/* Set to true if an error is detected at any time. */ -static portBASE_TYPE xCoRoutineErrorDetected = pdFALSE; - -/*-----------------------------------------------------------*/ - -void vStartHookCoRoutines( void ) -{ -unsigned portBASE_TYPE uxIndex, uxValueToPost = 0; - - for( uxIndex = 0; uxIndex < hookNUM_HOOK_CO_ROUTINES; uxIndex++ ) - { - /* Create a queue to transmit to and receive from each 'hook' - co-routine. */ - xHookRxQueues[ uxIndex ] = xQueueCreate( hookHOOK_QUEUE_LENGTH, sizeof( unsigned portBASE_TYPE ) ); - xHookTxQueues[ uxIndex ] = xQueueCreate( hookHOOK_QUEUE_LENGTH, sizeof( unsigned portBASE_TYPE ) ); - - /* To start things off the tick hook function expects the queue it - uses to receive data to contain a value. */ - xQueueSend( xHookRxQueues[ uxIndex ], &uxValueToPost, hookNO_BLOCK_TIME ); - - /* Create the 'hook' co-routine itself. */ - xCoRoutineCreate( prvHookCoRoutine, mainHOOK_CR_PRIORITY, uxIndex ); - } -} -/*-----------------------------------------------------------*/ - -static unsigned portBASE_TYPE uxCallCounter = 0, uxNumberToPost = 0; -void vApplicationTickHook( void ) -{ -unsigned portBASE_TYPE uxReceivedNumber; -signed portBASE_TYPE xIndex, xCoRoutineWoken; - - /* Is it time to talk to the 'hook' co-routines again? */ - uxCallCounter++; - if( uxCallCounter >= hookTICK_CALLS_BEFORE_POST ) - { - uxCallCounter = 0; - - for( xIndex = 0; xIndex < hookNUM_HOOK_CO_ROUTINES; xIndex++ ) - { - xCoRoutineWoken = pdFALSE; - if( crQUEUE_RECEIVE_FROM_ISR( xHookRxQueues[ xIndex ], &uxReceivedNumber, &xCoRoutineWoken ) != pdPASS ) - { - /* There is no reason why we would not expect the queue to - contain a value. */ - xCoRoutineErrorDetected = pdTRUE; - } - else - { - /* Each queue used to receive data from the 'hook' co-routines - should contain the number we last posted to the same co-routine. */ - if( uxReceivedNumber != uxNumberToPost ) - { - xCoRoutineErrorDetected = pdTRUE; - } - - /* Nothing should be blocked waiting to post to the queue. */ - if( xCoRoutineWoken != pdFALSE ) - { - xCoRoutineErrorDetected = pdTRUE; - } - } - } - - /* Start the next cycle by posting the next number onto each Tx queue. */ - uxNumberToPost++; - - for( xIndex = 0; xIndex < hookNUM_HOOK_CO_ROUTINES; xIndex++ ) - { - if( crQUEUE_SEND_FROM_ISR( xHookTxQueues[ xIndex ], &uxNumberToPost, pdFALSE ) != pdTRUE ) - { - /* Posting to the queue should have woken the co-routine that - was blocked on the queue. */ - xCoRoutineErrorDetected = pdTRUE; - } - } - } -} -/*-----------------------------------------------------------*/ - -static void prvHookCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ) -{ -static unsigned portBASE_TYPE uxReceivedValue[ hookNUM_HOOK_CO_ROUTINES ]; -portBASE_TYPE xResult; - - /* Each co-routine MUST start with a call to crSTART(); */ - crSTART( xHandle ); - - for( ;; ) - { - /* Wait to receive a value from the tick hook. */ - xResult = pdFAIL; - crQUEUE_RECEIVE( xHandle, xHookTxQueues[ uxIndex ], &( uxReceivedValue[ uxIndex ] ), portMAX_DELAY, &xResult ); - - /* There is no reason why we should not have received something on - the queue. */ - if( xResult != pdPASS ) - { - xCoRoutineErrorDetected = pdTRUE; - } - - /* Send the same number back to the idle hook so it can verify it. */ - xResult = pdFAIL; - crQUEUE_SEND( xHandle, xHookRxQueues[ uxIndex ], &( uxReceivedValue[ uxIndex ] ), hookNO_BLOCK_TIME, &xResult ); - if( xResult != pdPASS ) - { - /* There is no reason why we should not have been able to post to - the queue. */ - xCoRoutineErrorDetected = pdTRUE; - } - } - - /* Each co-routine MUST end with a call to crEND(). */ - crEND(); -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xAreHookCoRoutinesStillRunning( void ) -{ - if( xCoRoutineErrorDetected ) - { - return pdFALSE; - } - else - { - return pdTRUE; - } -} - - - diff --git a/Demo/Common/Minimal/death.c b/Demo/Common/Minimal/death.c deleted file mode 100644 index a3d849e97..000000000 --- a/Demo/Common/Minimal/death.c +++ /dev/null @@ -1,226 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/** - * Create a single persistent task which periodically dynamically creates another - * four tasks. The original task is called the creator task, the four tasks it - * creates are called suicidal tasks. - * - * Two of the created suicidal tasks kill one other suicidal task before killing - * themselves - leaving just the original task remaining. - * - * The creator task must be spawned after all of the other demo application tasks - * as it keeps a check on the number of tasks under the scheduler control. The - * number of tasks it expects to see running should never be greater than the - * number of tasks that were in existence when the creator task was spawned, plus - * one set of four suicidal tasks. If this number is exceeded an error is flagged. - * - * \page DeathC death.c - * \ingroup DemoFiles - *
- */ - -/* -Changes from V3.0.0 - + CreationCount sizes changed from unsigned portBASE_TYPE to - unsigned portSHORT to minimize the risk of overflowing. - - + Reset of usLastCreationCount added - -Changes from V3.1.0 - + Changed the dummy calculation to use variables of type long, rather than - float. This allows the file to be used with ports that do not support - floating point. - -*/ - -#include - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Demo program include files. */ -#include "death.h" - -#define deathSTACK_SIZE ( configMINIMAL_STACK_SIZE + 24 ) - -/* The task originally created which is responsible for periodically dynamically -creating another four tasks. */ -static portTASK_FUNCTION_PROTO( vCreateTasks, pvParameters ); - -/* The task function of the dynamically created tasks. */ -static portTASK_FUNCTION_PROTO( vSuicidalTask, pvParameters ); - -/* A variable which is incremented every time the dynamic tasks are created. This -is used to check that the task is still running. */ -static volatile unsigned portSHORT usCreationCount = 0; - -/* Used to store the number of tasks that were originally running so the creator -task can tell if any of the suicidal tasks have failed to die. -*/ -static volatile unsigned portBASE_TYPE uxTasksRunningAtStart = 0; - -/* Tasks are deleted by the idle task. Under heavy load the idle task might -not get much processing time, so it would be legitimate for several tasks to -remain undeleted for a short period. */ -static const unsigned portBASE_TYPE uxMaxNumberOfExtraTasksRunning = 4; - -/* Used to store a handle to the tasks that should be killed by a suicidal task, -before it kills itself. */ -xTaskHandle xCreatedTask1, xCreatedTask2; - -/*-----------------------------------------------------------*/ - -void vCreateSuicidalTasks( unsigned portBASE_TYPE uxPriority ) -{ -unsigned portBASE_TYPE *puxPriority; - - /* Create the Creator tasks - passing in as a parameter the priority at which - the suicidal tasks should be created. */ - puxPriority = ( unsigned portBASE_TYPE * ) pvPortMalloc( sizeof( unsigned portBASE_TYPE ) ); - *puxPriority = uxPriority; - - xTaskCreate( vCreateTasks, "CREATOR", deathSTACK_SIZE, ( void * ) puxPriority, uxPriority, NULL ); - - /* Record the number of tasks that are running now so we know if any of the - suicidal tasks have failed to be killed. */ - uxTasksRunningAtStart = ( unsigned portBASE_TYPE ) uxTaskGetNumberOfTasks(); - - /* FreeRTOS.org versions before V3.0 started the idle-task as the very - first task. The idle task was then already included in uxTasksRunningAtStart. - From FreeRTOS V3.0 on, the idle task is started when the scheduler is - started. Therefore the idle task is not yet accounted for. We correct - this by increasing uxTasksRunningAtStart by 1. */ - uxTasksRunningAtStart++; -} -/*-----------------------------------------------------------*/ - -static portTASK_FUNCTION( vSuicidalTask, pvParameters ) -{ -volatile portLONG l1, l2; -xTaskHandle xTaskToKill; -const portTickType xDelay = ( portTickType ) 200 / portTICK_RATE_MS; - - if( pvParameters != NULL ) - { - /* This task is periodically created four times. Two created tasks are - passed a handle to the other task so it can kill it before killing itself. - The other task is passed in null. */ - xTaskToKill = *( xTaskHandle* )pvParameters; - } - else - { - xTaskToKill = NULL; - } - - for( ;; ) - { - /* Do something random just to use some stack and registers. */ - l1 = 2; - l2 = 89; - l2 *= l1; - vTaskDelay( xDelay ); - - if( xTaskToKill != NULL ) - { - /* Make sure the other task has a go before we delete it. */ - vTaskDelay( ( portTickType ) 0 ); - /* Kill the other task that was created by vCreateTasks(). */ - vTaskDelete( xTaskToKill ); - /* Kill ourselves. */ - vTaskDelete( NULL ); - } - } -}/*lint !e818 !e550 Function prototype must be as per standard for task functions. */ -/*-----------------------------------------------------------*/ - -static portTASK_FUNCTION( vCreateTasks, pvParameters ) -{ -const portTickType xDelay = ( portTickType ) 1000 / portTICK_RATE_MS; -unsigned portBASE_TYPE uxPriority; - - uxPriority = *( unsigned portBASE_TYPE * ) pvParameters; - vPortFree( pvParameters ); - - for( ;; ) - { - /* Just loop round, delaying then creating the four suicidal tasks. */ - vTaskDelay( xDelay ); - - xTaskCreate( vSuicidalTask, "SUICID1", deathSTACK_SIZE, NULL, uxPriority, &xCreatedTask1 ); - xTaskCreate( vSuicidalTask, "SUICID2", deathSTACK_SIZE, &xCreatedTask1, uxPriority, NULL ); - - xTaskCreate( vSuicidalTask, "SUICID1", deathSTACK_SIZE, NULL, uxPriority, &xCreatedTask2 ); - xTaskCreate( vSuicidalTask, "SUICID2", deathSTACK_SIZE, &xCreatedTask2, uxPriority, NULL ); - - ++usCreationCount; - } -} -/*-----------------------------------------------------------*/ - -/* This is called to check that the creator task is still running and that there -are not any more than four extra tasks. */ -portBASE_TYPE xIsCreateTaskStillRunning( void ) -{ -static portSHORT usLastCreationCount = -1; -portBASE_TYPE xReturn = pdTRUE; -static unsigned portBASE_TYPE uxTasksRunningNow; - - if( usLastCreationCount == usCreationCount ) - { - xReturn = pdFALSE; - } - else - { - usLastCreationCount = usCreationCount; - } - - uxTasksRunningNow = ( unsigned portBASE_TYPE ) uxTaskGetNumberOfTasks(); - - if( uxTasksRunningNow < uxTasksRunningAtStart ) - { - xReturn = pdFALSE; - } - else if( ( uxTasksRunningNow - uxTasksRunningAtStart ) > uxMaxNumberOfExtraTasksRunning ) - { - xReturn = pdFALSE; - } - else - { - /* Everything is okay. */ - } - - return xReturn; -} - - diff --git a/Demo/Common/Minimal/dynamic.c b/Demo/Common/Minimal/dynamic.c deleted file mode 100644 index fb8b80c2d..000000000 --- a/Demo/Common/Minimal/dynamic.c +++ /dev/null @@ -1,391 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * The first test creates three tasks - two counter tasks (one continuous count - * and one limited count) and one controller. A "count" variable is shared - * between all three tasks. The two counter tasks should never be in a "ready" - * state at the same time. The controller task runs at the same priority as - * the continuous count task, and at a lower priority than the limited count - * task. - * - * One counter task loops indefinitely, incrementing the shared count variable - * on each iteration. To ensure it has exclusive access to the variable it - * raises it's priority above that of the controller task before each - * increment, lowering it again to it's original priority before starting the - * next iteration. - * - * The other counter task increments the shared count variable on each - * iteration of it's loop until the count has reached a limit of 0xff - at - * which point it suspends itself. It will not start a new loop until the - * controller task has made it "ready" again by calling vTaskResume (). - * This second counter task operates at a higher priority than controller - * task so does not need to worry about mutual exclusion of the counter - * variable. - * - * The controller task is in two sections. The first section controls and - * monitors the continuous count task. When this section is operational the - * limited count task is suspended. Likewise, the second section controls - * and monitors the limited count task. When this section is operational the - * continuous count task is suspended. - * - * In the first section the controller task first takes a copy of the shared - * count variable. To ensure mutual exclusion on the count variable it - * suspends the continuous count task, resuming it again when the copy has been - * taken. The controller task then sleeps for a fixed period - during which - * the continuous count task will execute and increment the shared variable. - * When the controller task wakes it checks that the continuous count task - * has executed by comparing the copy of the shared variable with its current - * value. This time, to ensure mutual exclusion, the scheduler itself is - * suspended with a call to vTaskSuspendAll (). This is for demonstration - * purposes only and is not a recommended technique due to its inefficiency. - * - * After a fixed number of iterations the controller task suspends the - * continuous count task, and moves on to its second section. - * - * At the start of the second section the shared variable is cleared to zero. - * The limited count task is then woken from it's suspension by a call to - * vTaskResume (). As this counter task operates at a higher priority than - * the controller task the controller task should not run again until the - * shared variable has been counted up to the limited value causing the counter - * task to suspend itself. The next line after vTaskResume () is therefore - * a check on the shared variable to ensure everything is as expected. - * - * - * The second test consists of a couple of very simple tasks that post onto a - * queue while the scheduler is suspended. This test was added to test parts - * of the scheduler not exercised by the first test. - * - */ - -#include - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" -#include "semphr.h" - -/* Demo app include files. */ -#include "dynamic.h" - -/* Function that implements the "limited count" task as described above. */ -static portTASK_FUNCTION_PROTO( vLimitedIncrementTask, pvParameters ); - -/* Function that implements the "continuous count" task as described above. */ -static portTASK_FUNCTION_PROTO( vContinuousIncrementTask, pvParameters ); - -/* Function that implements the controller task as described above. */ -static portTASK_FUNCTION_PROTO( vCounterControlTask, pvParameters ); - -static portTASK_FUNCTION_PROTO( vQueueReceiveWhenSuspendedTask, pvParameters ); -static portTASK_FUNCTION_PROTO( vQueueSendWhenSuspendedTask, pvParameters ); - -/* Demo task specific constants. */ -#define priSTACK_SIZE ( ( unsigned portSHORT ) 128 ) -#define priSLEEP_TIME ( ( portTickType ) 100 ) -#define priLOOPS ( 5 ) -#define priMAX_COUNT ( ( unsigned portLONG ) 0xff ) -#define priNO_BLOCK ( ( portTickType ) 0 ) -#define priSUSPENDED_QUEUE_LENGTH ( 1 ) - -/*-----------------------------------------------------------*/ - -/* Handles to the two counter tasks. These could be passed in as parameters -to the controller task to prevent them having to be file scope. */ -static xTaskHandle xContinousIncrementHandle, xLimitedIncrementHandle; - -/* The shared counter variable. This is passed in as a parameter to the two -counter variables for demonstration purposes. */ -static unsigned portLONG ulCounter; - -/* Variables used to check that the tasks are still operating without error. -Each complete iteration of the controller task increments this variable -provided no errors have been found. The variable maintaining the same value -is therefore indication of an error. */ -static unsigned portSHORT usCheckVariable = ( unsigned portSHORT ) 0; -static portBASE_TYPE xSuspendedQueueSendError = pdFALSE; -static portBASE_TYPE xSuspendedQueueReceiveError = pdFALSE; - -/* Queue used by the second test. */ -xQueueHandle xSuspendedTestQueue; - -/*-----------------------------------------------------------*/ -/* - * Start the three tasks as described at the top of the file. - * Note that the limited count task is given a higher priority. - */ -void vStartDynamicPriorityTasks( void ) -{ - xSuspendedTestQueue = xQueueCreate( priSUSPENDED_QUEUE_LENGTH, sizeof( unsigned portLONG ) ); - xTaskCreate( vContinuousIncrementTask, ( signed portCHAR * ) "CNT_INC", priSTACK_SIZE, ( void * ) &ulCounter, tskIDLE_PRIORITY, &xContinousIncrementHandle ); - xTaskCreate( vLimitedIncrementTask, ( signed portCHAR * ) "LIM_INC", priSTACK_SIZE, ( void * ) &ulCounter, tskIDLE_PRIORITY + 1, &xLimitedIncrementHandle ); - xTaskCreate( vCounterControlTask, ( signed portCHAR * ) "C_CTRL", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); - xTaskCreate( vQueueSendWhenSuspendedTask, ( signed portCHAR * ) "SUSP_TX", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); - xTaskCreate( vQueueReceiveWhenSuspendedTask, ( signed portCHAR * ) "SUSP_RX", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); -} -/*-----------------------------------------------------------*/ - -/* - * Just loops around incrementing the shared variable until the limit has been - * reached. Once the limit has been reached it suspends itself. - */ -static portTASK_FUNCTION( vLimitedIncrementTask, pvParameters ) -{ -unsigned portLONG *pulCounter; - - /* Take a pointer to the shared variable from the parameters passed into - the task. */ - pulCounter = ( unsigned portLONG * ) pvParameters; - - /* This will run before the control task, so the first thing it does is - suspend - the control task will resume it when ready. */ - vTaskSuspend( NULL ); - - for( ;; ) - { - /* Just count up to a value then suspend. */ - ( *pulCounter )++; - - if( *pulCounter >= priMAX_COUNT ) - { - vTaskSuspend( NULL ); - } - } -} -/*-----------------------------------------------------------*/ - -/* - * Just keep counting the shared variable up. The control task will suspend - * this task when it wants. - */ -static portTASK_FUNCTION( vContinuousIncrementTask, pvParameters ) -{ -unsigned portLONG *pulCounter; -unsigned portBASE_TYPE uxOurPriority; - - /* Take a pointer to the shared variable from the parameters passed into - the task. */ - pulCounter = ( unsigned portLONG * ) pvParameters; - - /* Query our priority so we can raise it when exclusive access to the - shared variable is required. */ - uxOurPriority = uxTaskPriorityGet( NULL ); - - for( ;; ) - { - /* Raise our priority above the controller task to ensure a context - switch does not occur while we are accessing this variable. */ - vTaskPrioritySet( NULL, uxOurPriority + 1 ); - ( *pulCounter )++; - vTaskPrioritySet( NULL, uxOurPriority ); - } -} -/*-----------------------------------------------------------*/ - -/* - * Controller task as described above. - */ -static portTASK_FUNCTION( vCounterControlTask, pvParameters ) -{ -unsigned portLONG ulLastCounter; -portSHORT sLoops; -portSHORT sError = pdFALSE; - - /* Just to stop warning messages. */ - ( void ) pvParameters; - - for( ;; ) - { - /* Start with the counter at zero. */ - ulCounter = ( unsigned portLONG ) 0; - - /* First section : */ - - /* Check the continuous count task is running. */ - for( sLoops = 0; sLoops < priLOOPS; sLoops++ ) - { - /* Suspend the continuous count task so we can take a mirror of the - shared variable without risk of corruption. */ - vTaskSuspend( xContinousIncrementHandle ); - ulLastCounter = ulCounter; - vTaskResume( xContinousIncrementHandle ); - - /* Now delay to ensure the other task has processor time. */ - vTaskDelay( priSLEEP_TIME ); - - /* Check the shared variable again. This time to ensure mutual - exclusion the whole scheduler will be locked. This is just for - demo purposes! */ - vTaskSuspendAll(); - { - if( ulLastCounter == ulCounter ) - { - /* The shared variable has not changed. There is a problem - with the continuous count task so flag an error. */ - sError = pdTRUE; - } - } - xTaskResumeAll(); - } - - - /* Second section: */ - - /* Suspend the continuous counter task so it stops accessing the shared variable. */ - vTaskSuspend( xContinousIncrementHandle ); - - /* Reset the variable. */ - ulCounter = ( unsigned portLONG ) 0; - - /* Resume the limited count task which has a higher priority than us. - We should therefore not return from this call until the limited count - task has suspended itself with a known value in the counter variable. */ - vTaskResume( xLimitedIncrementHandle ); - - /* Does the counter variable have the expected value? */ - if( ulCounter != priMAX_COUNT ) - { - sError = pdTRUE; - } - - if( sError == pdFALSE ) - { - /* If no errors have occurred then increment the check variable. */ - portENTER_CRITICAL(); - usCheckVariable++; - portEXIT_CRITICAL(); - } - - /* Resume the continuous count task and do it all again. */ - vTaskResume( xContinousIncrementHandle ); - } -} -/*-----------------------------------------------------------*/ - -static portTASK_FUNCTION( vQueueSendWhenSuspendedTask, pvParameters ) -{ -static unsigned portLONG ulValueToSend = ( unsigned portLONG ) 0; - - /* Just to stop warning messages. */ - ( void ) pvParameters; - - for( ;; ) - { - vTaskSuspendAll(); - { - /* We must not block while the scheduler is suspended! */ - if( xQueueSend( xSuspendedTestQueue, ( void * ) &ulValueToSend, priNO_BLOCK ) != pdTRUE ) - { - xSuspendedQueueSendError = pdTRUE; - } - } - xTaskResumeAll(); - - vTaskDelay( priSLEEP_TIME ); - - ++ulValueToSend; - } -} -/*-----------------------------------------------------------*/ - -static portTASK_FUNCTION( vQueueReceiveWhenSuspendedTask, pvParameters ) -{ -static unsigned portLONG ulExpectedValue = ( unsigned portLONG ) 0, ulReceivedValue; -portBASE_TYPE xGotValue; - - /* Just to stop warning messages. */ - ( void ) pvParameters; - - for( ;; ) - { - do - { - /* Suspending the scheduler here is fairly pointless and - undesirable for a normal application. It is done here purely - to test the scheduler. The inner xTaskResumeAll() should - never return pdTRUE as the scheduler is still locked by the - outer call. */ - vTaskSuspendAll(); - { - vTaskSuspendAll(); - { - xGotValue = xQueueReceive( xSuspendedTestQueue, ( void * ) &ulReceivedValue, priNO_BLOCK ); - } - if( xTaskResumeAll() ) - { - xSuspendedQueueReceiveError = pdTRUE; - } - } - xTaskResumeAll(); - - } while( xGotValue == pdFALSE ); - - if( ulReceivedValue != ulExpectedValue ) - { - xSuspendedQueueReceiveError = pdTRUE; - } - - ++ulExpectedValue; - } -} -/*-----------------------------------------------------------*/ - -/* Called to check that all the created tasks are still running without error. */ -portBASE_TYPE xAreDynamicPriorityTasksStillRunning( void ) -{ -/* Keep a history of the check variables so we know if it has been incremented -since the last call. */ -static unsigned portSHORT usLastTaskCheck = ( unsigned portSHORT ) 0; -portBASE_TYPE xReturn = pdTRUE; - - /* Check the tasks are still running by ensuring the check variable - is still incrementing. */ - - if( usCheckVariable == usLastTaskCheck ) - { - /* The check has not incremented so an error exists. */ - xReturn = pdFALSE; - } - - if( xSuspendedQueueSendError == pdTRUE ) - { - xReturn = pdFALSE; - } - - if( xSuspendedQueueReceiveError == pdTRUE ) - { - xReturn = pdFALSE; - } - - usLastTaskCheck = usCheckVariable; - return xReturn; -} diff --git a/Demo/Common/Minimal/flash.c b/Demo/Common/Minimal/flash.c deleted file mode 100644 index 80aa223c3..000000000 --- a/Demo/Common/Minimal/flash.c +++ /dev/null @@ -1,138 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/** - * This version of flash .c is for use on systems that have limited stack space - * and no display facilities. The complete version can be found in the - * Demo/Common/Full directory. - * - * Three tasks are created, each of which flash an LED at a different rate. The first - * LED flashes every 200ms, the second every 400ms, the third every 600ms. - * - * The LED flash tasks provide instant visual feedback. They show that the scheduler - * is still operational. - * - * The PC port uses the standard parallel port for outputs, the Flashlite 186 port - * uses IO port F and the AVR port port B. - * - */ - -/* -Changes from V2.0.0 - - + Delay periods are now specified using variables and constants of - portTickType rather than unsigned portLONG. - -Changes from V2.5.5 - - + Calls to vTaskDelay() have been replaced with vTaskDelayUntil(). - -*/ - -#include - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Demo program include files. */ -#include "partest.h" -#include "flash.h" - -#define ledSTACK_SIZE configMINIMAL_STACK_SIZE -#define ledNUMBER_OF_LEDS ( 3 ) -#define ledFLASH_RATE_BASE ( ( portTickType ) 333 ) - -/* Variable used by the created tasks to calculate the LED number to use, and -the rate at which they should flash the LED. */ -static volatile unsigned portBASE_TYPE uxFlashTaskNumber = 0; - -/* The task that is created three times. */ -static portTASK_FUNCTION_PROTO( vLEDFlashTask, pvParameters ); - -/*-----------------------------------------------------------*/ - -void vStartLEDFlashTasks( unsigned portBASE_TYPE uxPriority ) -{ -signed portBASE_TYPE xLEDTask; - - /* Create the three tasks. */ - for( xLEDTask = 0; xLEDTask < ledNUMBER_OF_LEDS; ++xLEDTask ) - { - /* Spawn the task. */ - xTaskCreate( vLEDFlashTask, ( const signed portCHAR * const ) "LEDx", ledSTACK_SIZE, NULL, uxPriority, ( xTaskHandle * ) NULL ); - } -} -/*-----------------------------------------------------------*/ - -static portTASK_FUNCTION( vLEDFlashTask, pvParameters ) -{ -portTickType xFlashRate, xLastFlashTime; -unsigned portBASE_TYPE uxLED; - - /* The parameters are not used. */ - ( void ) pvParameters; - - /* Calculate the LED and flash rate. */ - portENTER_CRITICAL(); - { - /* See which of the eight LED's we should use. */ - uxLED = uxFlashTaskNumber; - - /* Update so the next task uses the next LED. */ - uxFlashTaskNumber++; - } - portEXIT_CRITICAL(); - - xFlashRate = ledFLASH_RATE_BASE + ( ledFLASH_RATE_BASE * ( portTickType ) uxLED ); - xFlashRate /= portTICK_RATE_MS; - - /* We will turn the LED on and off again in the delay period, so each - delay is only half the total period. */ - xFlashRate /= ( portTickType ) 2; - - /* We need to initialise xLastFlashTime prior to the first call to - vTaskDelayUntil(). */ - xLastFlashTime = xTaskGetTickCount(); - - for(;;) - { - /* Delay for half the flash period then turn the LED on. */ - vTaskDelayUntil( &xLastFlashTime, xFlashRate ); - vParTestToggleLED( uxLED ); - - /* Delay for half the flash period then turn the LED off. */ - vTaskDelayUntil( &xLastFlashTime, xFlashRate ); - vParTestToggleLED( uxLED ); - } -} /*lint !e715 !e818 !e830 Function definition must be standard for task creation. */ - diff --git a/Demo/Common/Minimal/flop.c b/Demo/Common/Minimal/flop.c deleted file mode 100644 index ccc5cffd7..000000000 --- a/Demo/Common/Minimal/flop.c +++ /dev/null @@ -1,330 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * Creates eight tasks, each of which loops continuously performing an (emulated) - * floating point calculation. - * - * All the tasks run at the idle priority and never block or yield. This causes - * all eight tasks to time slice with the idle task. Running at the idle priority - * means that these tasks will get pre-empted any time another task is ready to run - * or a time slice occurs. More often than not the pre-emption will occur mid - * calculation, creating a good test of the schedulers context switch mechanism - a - * calculation producing an unexpected result could be a symptom of a corruption in - * the context of a task. - */ - -#include -#include - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Demo program include files. */ -#include "flop.h" - -#define mathSTACK_SIZE configMINIMAL_STACK_SIZE -#define mathNUMBER_OF_TASKS ( 8 ) - -/* Four tasks, each of which performs a different floating point calculation. -Each of the four is created twice. */ -static portTASK_FUNCTION_PROTO( vCompetingMathTask1, pvParameters ); -static portTASK_FUNCTION_PROTO( vCompetingMathTask2, pvParameters ); -static portTASK_FUNCTION_PROTO( vCompetingMathTask3, pvParameters ); -static portTASK_FUNCTION_PROTO( vCompetingMathTask4, pvParameters ); - -/* These variables are used to check that all the tasks are still running. If a -task gets a calculation wrong it will -stop incrementing its check variable. */ -static volatile unsigned portSHORT usTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned portSHORT ) 0 }; - -/*-----------------------------------------------------------*/ - -void vStartMathTasks( unsigned portBASE_TYPE uxPriority ) -{ - xTaskCreate( vCompetingMathTask1, ( signed portCHAR * ) "Math1", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 0 ] ), uxPriority, NULL ); - xTaskCreate( vCompetingMathTask2, ( signed portCHAR * ) "Math2", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 1 ] ), uxPriority, NULL ); - xTaskCreate( vCompetingMathTask3, ( signed portCHAR * ) "Math3", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 2 ] ), uxPriority, NULL ); - xTaskCreate( vCompetingMathTask4, ( signed portCHAR * ) "Math4", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 3 ] ), uxPriority, NULL ); - xTaskCreate( vCompetingMathTask1, ( signed portCHAR * ) "Math5", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 4 ] ), uxPriority, NULL ); - xTaskCreate( vCompetingMathTask2, ( signed portCHAR * ) "Math6", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 5 ] ), uxPriority, NULL ); - xTaskCreate( vCompetingMathTask3, ( signed portCHAR * ) "Math7", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 6 ] ), uxPriority, NULL ); - xTaskCreate( vCompetingMathTask4, ( signed portCHAR * ) "Math8", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 7 ] ), uxPriority, NULL ); -} -/*-----------------------------------------------------------*/ - -static portTASK_FUNCTION( vCompetingMathTask1, pvParameters ) -{ -volatile portDOUBLE d1, d2, d3, d4; -volatile unsigned portSHORT *pusTaskCheckVariable; -volatile portDOUBLE dAnswer; -portSHORT sError = pdFALSE; - - d1 = 123.4567; - d2 = 2345.6789; - d3 = -918.222; - - dAnswer = ( d1 + d2 ) * d3; - - /* The variable this task increments to show it is still running is passed in - as the parameter. */ - pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters; - - /* Keep performing a calculation and checking the result against a constant. */ - for(;;) - { - d1 = 123.4567; - d2 = 2345.6789; - d3 = -918.222; - - d4 = ( d1 + d2 ) * d3; - - #if configUSE_PREEMPTION == 0 - taskYIELD(); - #endif - - /* If the calculation does not match the expected constant, stop the - increment of the check variable. */ - if( fabs( d4 - dAnswer ) > 0.001 ) - { - sError = pdTRUE; - } - - if( sError == pdFALSE ) - { - /* If the calculation has always been correct, increment the check - variable so we know this task is still running okay. */ - ( *pusTaskCheckVariable )++; - } - - #if configUSE_PREEMPTION == 0 - taskYIELD(); - #endif - - } -} -/*-----------------------------------------------------------*/ - -static portTASK_FUNCTION( vCompetingMathTask2, pvParameters ) -{ -volatile portDOUBLE d1, d2, d3, d4; -volatile unsigned portSHORT *pusTaskCheckVariable; -volatile portDOUBLE dAnswer; -portSHORT sError = pdFALSE; - - d1 = -389.38; - d2 = 32498.2; - d3 = -2.0001; - - dAnswer = ( d1 / d2 ) * d3; - - - /* The variable this task increments to show it is still running is passed in - as the parameter. */ - pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters; - - /* Keep performing a calculation and checking the result against a constant. */ - for( ;; ) - { - d1 = -389.38; - d2 = 32498.2; - d3 = -2.0001; - - d4 = ( d1 / d2 ) * d3; - - #if configUSE_PREEMPTION == 0 - taskYIELD(); - #endif - - /* If the calculation does not match the expected constant, stop the - increment of the check variable. */ - if( fabs( d4 - dAnswer ) > 0.001 ) - { - sError = pdTRUE; - } - - if( sError == pdFALSE ) - { - /* If the calculation has always been correct, increment the check - variable so we know - this task is still running okay. */ - ( *pusTaskCheckVariable )++; - } - - #if configUSE_PREEMPTION == 0 - taskYIELD(); - #endif - } -} -/*-----------------------------------------------------------*/ - -static portTASK_FUNCTION( vCompetingMathTask3, pvParameters ) -{ -volatile portDOUBLE *pdArray, dTotal1, dTotal2, dDifference; -volatile unsigned portSHORT *pusTaskCheckVariable; -const size_t xArraySize = 10; -size_t xPosition; -portSHORT sError = pdFALSE; - - /* The variable this task increments to show it is still running is passed in - as the parameter. */ - pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters; - - pdArray = ( portDOUBLE * ) pvPortMalloc( xArraySize * sizeof( portDOUBLE ) ); - - /* Keep filling an array, keeping a running total of the values placed in the - array. Then run through the array adding up all the values. If the two totals - do not match, stop the check variable from incrementing. */ - for( ;; ) - { - dTotal1 = 0.0; - dTotal2 = 0.0; - - for( xPosition = 0; xPosition < xArraySize; xPosition++ ) - { - pdArray[ xPosition ] = ( portDOUBLE ) xPosition + 5.5; - dTotal1 += ( portDOUBLE ) xPosition + 5.5; - } - - #if configUSE_PREEMPTION == 0 - taskYIELD(); - #endif - - for( xPosition = 0; xPosition < xArraySize; xPosition++ ) - { - dTotal2 += pdArray[ xPosition ]; - } - - dDifference = dTotal1 - dTotal2; - if( fabs( dDifference ) > 0.001 ) - { - sError = pdTRUE; - } - - #if configUSE_PREEMPTION == 0 - taskYIELD(); - #endif - - if( sError == pdFALSE ) - { - /* If the calculation has always been correct, increment the check - variable so we know this task is still running okay. */ - ( *pusTaskCheckVariable )++; - } - } -} -/*-----------------------------------------------------------*/ - -static portTASK_FUNCTION( vCompetingMathTask4, pvParameters ) -{ -volatile portDOUBLE *pdArray, dTotal1, dTotal2, dDifference; -volatile unsigned portSHORT *pusTaskCheckVariable; -const size_t xArraySize = 10; -size_t xPosition; -portSHORT sError = pdFALSE; - - /* The variable this task increments to show it is still running is passed in - as the parameter. */ - pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters; - - pdArray = ( portDOUBLE * ) pvPortMalloc( xArraySize * sizeof( portDOUBLE ) ); - - /* Keep filling an array, keeping a running total of the values placed in the - array. Then run through the array adding up all the values. If the two totals - do not match, stop the check variable from incrementing. */ - for( ;; ) - { - dTotal1 = 0.0; - dTotal2 = 0.0; - - for( xPosition = 0; xPosition < xArraySize; xPosition++ ) - { - pdArray[ xPosition ] = ( portDOUBLE ) xPosition * 12.123; - dTotal1 += ( portDOUBLE ) xPosition * 12.123; - } - - #if configUSE_PREEMPTION == 0 - taskYIELD(); - #endif - - for( xPosition = 0; xPosition < xArraySize; xPosition++ ) - { - dTotal2 += pdArray[ xPosition ]; - } - - dDifference = dTotal1 - dTotal2; - if( fabs( dDifference ) > 0.001 ) - { - sError = pdTRUE; - } - - #if configUSE_PREEMPTION == 0 - taskYIELD(); - #endif - - if( sError == pdFALSE ) - { - /* If the calculation has always been correct, increment the check - variable so we know this task is still running okay. */ - ( *pusTaskCheckVariable )++; - } - } -} -/*-----------------------------------------------------------*/ - -/* This is called to check that all the created tasks are still running. */ -portBASE_TYPE xAreMathsTaskStillRunning( void ) -{ -/* Keep a history of the check variables so we know if they have been incremented -since the last call. */ -static unsigned portSHORT usLastTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned portSHORT ) 0 }; -portBASE_TYPE xReturn = pdTRUE, xTask; - - /* Check the maths tasks are still running by ensuring their check variables - are still incrementing. */ - for( xTask = 0; xTask < mathNUMBER_OF_TASKS; xTask++ ) - { - if( usTaskCheck[ xTask ] == usLastTaskCheck[ xTask ] ) - { - /* The check has not incremented so an error exists. */ - xReturn = pdFALSE; - } - - usLastTaskCheck[ xTask ] = usTaskCheck[ xTask ]; - } - - return xReturn; -} - - - diff --git a/Demo/Common/Minimal/integer.c b/Demo/Common/Minimal/integer.c deleted file mode 100644 index 340021f4b..000000000 --- a/Demo/Common/Minimal/integer.c +++ /dev/null @@ -1,191 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * This version of integer. c is for use on systems that have limited stack - * space and no display facilities. The complete version can be found in - * the Demo/Common/Full directory. - * - * As with the full version, the tasks created in this file are a good test - * of the scheduler context switch mechanism. The processor has to access - * 32bit variables in two or four chunks (depending on the processor). The low - * priority of these tasks means there is a high probability that a context - * switch will occur mid calculation. See flop. c documentation for - * more information. - * - */ - -/* -Changes from V1.2.1 - - + The constants used in the calculations are larger to ensure the - optimiser does not truncate them to 16 bits. - -Changes from V1.2.3 - - + uxTaskCheck is now just used as a boolean. Instead of incrementing - the variable each cycle of the task, the variable is simply set to - true. sAreIntegerMathsTaskStillRunning() sets it back to false and - expects it to have been set back to true by the time it is called - again. - + A division has been included in the calculation. -*/ - -#include - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Demo program include files. */ -#include "integer.h" - -/* The constants used in the calculation. */ -#define intgCONST1 ( ( portLONG ) 123 ) -#define intgCONST2 ( ( portLONG ) 234567 ) -#define intgCONST3 ( ( portLONG ) -3 ) -#define intgCONST4 ( ( portLONG ) 7 ) -#define intgEXPECTED_ANSWER ( ( ( intgCONST1 + intgCONST2 ) * intgCONST3 ) / intgCONST4 ) - -#define intgSTACK_SIZE configMINIMAL_STACK_SIZE - -/* As this is the minimal version, we will only create one task. */ -#define intgNUMBER_OF_TASKS ( 1 ) - -/* The task function. Repeatedly performs a 32 bit calculation, checking the -result against the expected result. If the result is incorrect then the -context switch must have caused some corruption. */ -static portTASK_FUNCTION_PROTO( vCompeteingIntMathTask, pvParameters ); - -/* Variables that are set to true within the calculation task to indicate -that the task is still executing. The check task sets the variable back to -false, flagging an error if the variable is still false the next time it -is called. */ -static volatile signed portBASE_TYPE xTaskCheck[ intgNUMBER_OF_TASKS ] = { ( signed portBASE_TYPE ) pdFALSE }; - -/*-----------------------------------------------------------*/ - -void vStartIntegerMathTasks( unsigned portBASE_TYPE uxPriority ) -{ -portSHORT sTask; - - for( sTask = 0; sTask < intgNUMBER_OF_TASKS; sTask++ ) - { - xTaskCreate( vCompeteingIntMathTask, ( signed portCHAR * ) "IntMath", intgSTACK_SIZE, ( void * ) &( xTaskCheck[ sTask ] ), uxPriority, ( xTaskHandle * ) NULL ); - } -} -/*-----------------------------------------------------------*/ - -static portTASK_FUNCTION( vCompeteingIntMathTask, pvParameters ) -{ -/* These variables are all effectively set to constants so they are volatile to -ensure the compiler does not just get rid of them. */ -volatile portLONG lValue; -portSHORT sError = pdFALSE; -volatile signed portBASE_TYPE *pxTaskHasExecuted; - - /* Set a pointer to the variable we are going to set to true each - iteration. This is also a good test of the parameter passing mechanism - within each port. */ - pxTaskHasExecuted = ( volatile signed portBASE_TYPE * ) pvParameters; - - /* Keep performing a calculation and checking the result against a constant. */ - for( ;; ) - { - /* Perform the calculation. This will store partial value in - registers, resulting in a good test of the context switch mechanism. */ - lValue = intgCONST1; - lValue += intgCONST2; - - /* Yield in case cooperative scheduling is being used. */ - #if configUSE_PREEMPTION == 0 - { - taskYIELD(); - } - #endif - - /* Finish off the calculation. */ - lValue *= intgCONST3; - lValue /= intgCONST4; - - /* If the calculation is found to be incorrect we stop setting the - TaskHasExecuted variable so the check task can see an error has - occurred. */ - if( lValue != intgEXPECTED_ANSWER ) /*lint !e774 volatile used to prevent this being optimised out. */ - { - sError = pdTRUE; - } - - if( sError == pdFALSE ) - { - /* We have not encountered any errors, so set the flag that show - we are still executing. This will be periodically cleared by - the check task. */ - portENTER_CRITICAL(); - *pxTaskHasExecuted = pdTRUE; - portEXIT_CRITICAL(); - } - - /* Yield in case cooperative scheduling is being used. */ - #if configUSE_PREEMPTION == 0 - { - taskYIELD(); - } - #endif - } -} -/*-----------------------------------------------------------*/ - -/* This is called to check that all the created tasks are still running. */ -portBASE_TYPE xAreIntegerMathsTaskStillRunning( void ) -{ -portBASE_TYPE xReturn = pdTRUE; -portSHORT sTask; - - /* Check the maths tasks are still running by ensuring their check variables - are still being set to true. */ - for( sTask = 0; sTask < intgNUMBER_OF_TASKS; sTask++ ) - { - if( xTaskCheck[ sTask ] == pdFALSE ) - { - /* The check has not incremented so an error exists. */ - xReturn = pdFALSE; - } - - /* Reset the check variable so we can tell if it has been set by - the next time around. */ - xTaskCheck[ sTask ] = pdFALSE; - } - - return xReturn; -} - diff --git a/Demo/Common/Minimal/semtest.c b/Demo/Common/Minimal/semtest.c deleted file mode 100644 index 7ead84252..000000000 --- a/Demo/Common/Minimal/semtest.c +++ /dev/null @@ -1,254 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * Creates two sets of two tasks. The tasks within a set share a variable, access - * to which is guarded by a semaphore. - * - * Each task starts by attempting to obtain the semaphore. On obtaining a - * semaphore a task checks to ensure that the guarded variable has an expected - * value. It then clears the variable to zero before counting it back up to the - * expected value in increments of 1. After each increment the variable is checked - * to ensure it contains the value to which it was just set. When the starting - * value is again reached the task releases the semaphore giving the other task in - * the set a chance to do exactly the same thing. The starting value is high - * enough to ensure that a tick is likely to occur during the incrementing loop. - * - * An error is flagged if at any time during the process a shared variable is - * found to have a value other than that expected. Such an occurrence would - * suggest an error in the mutual exclusion mechanism by which access to the - * variable is restricted. - * - * The first set of two tasks poll their semaphore. The second set use blocking - * calls. - * - */ - - -#include - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" -#include "semphr.h" - -/* Demo app include files. */ -#include "semtest.h" - -/* The value to which the shared variables are counted. */ -#define semtstBLOCKING_EXPECTED_VALUE ( ( unsigned portLONG ) 0xfff ) -#define semtstNON_BLOCKING_EXPECTED_VALUE ( ( unsigned portLONG ) 0xff ) - -#define semtstSTACK_SIZE configMINIMAL_STACK_SIZE - -#define semtstNUM_TASKS ( 4 ) - -#define semtstDELAY_FACTOR ( ( portTickType ) 10 ) - -/* The task function as described at the top of the file. */ -static portTASK_FUNCTION_PROTO( prvSemaphoreTest, pvParameters ); - -/* Structure used to pass parameters to each task. */ -typedef struct SEMAPHORE_PARAMETERS -{ - xSemaphoreHandle xSemaphore; - volatile unsigned portLONG *pulSharedVariable; - portTickType xBlockTime; -} xSemaphoreParameters; - -/* Variables used to check that all the tasks are still running without errors. */ -static volatile portSHORT sCheckVariables[ semtstNUM_TASKS ] = { 0 }; -static volatile portSHORT sNextCheckVariable = 0; - -/*-----------------------------------------------------------*/ - -void vStartSemaphoreTasks( unsigned portBASE_TYPE uxPriority ) -{ -xSemaphoreParameters *pxFirstSemaphoreParameters, *pxSecondSemaphoreParameters; -const portTickType xBlockTime = ( portTickType ) 100; - - /* Create the structure used to pass parameters to the first two tasks. */ - pxFirstSemaphoreParameters = ( xSemaphoreParameters * ) pvPortMalloc( sizeof( xSemaphoreParameters ) ); - - if( pxFirstSemaphoreParameters != NULL ) - { - /* Create the semaphore used by the first two tasks. */ - vSemaphoreCreateBinary( pxFirstSemaphoreParameters->xSemaphore ); - - if( pxFirstSemaphoreParameters->xSemaphore != NULL ) - { - /* Create the variable which is to be shared by the first two tasks. */ - pxFirstSemaphoreParameters->pulSharedVariable = ( unsigned portLONG * ) pvPortMalloc( sizeof( unsigned portLONG ) ); - - /* Initialise the share variable to the value the tasks expect. */ - *( pxFirstSemaphoreParameters->pulSharedVariable ) = semtstNON_BLOCKING_EXPECTED_VALUE; - - /* The first two tasks do not block on semaphore calls. */ - pxFirstSemaphoreParameters->xBlockTime = ( portTickType ) 0; - - /* Spawn the first two tasks. As they poll they operate at the idle priority. */ - xTaskCreate( prvSemaphoreTest, ( signed portCHAR * ) "PolSEM1", semtstSTACK_SIZE, ( void * ) pxFirstSemaphoreParameters, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL ); - xTaskCreate( prvSemaphoreTest, ( signed portCHAR * ) "PolSEM2", semtstSTACK_SIZE, ( void * ) pxFirstSemaphoreParameters, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL ); - } - } - - /* Do exactly the same to create the second set of tasks, only this time - provide a block time for the semaphore calls. */ - pxSecondSemaphoreParameters = ( xSemaphoreParameters * ) pvPortMalloc( sizeof( xSemaphoreParameters ) ); - if( pxSecondSemaphoreParameters != NULL ) - { - vSemaphoreCreateBinary( pxSecondSemaphoreParameters->xSemaphore ); - - if( pxSecondSemaphoreParameters->xSemaphore != NULL ) - { - pxSecondSemaphoreParameters->pulSharedVariable = ( unsigned portLONG * ) pvPortMalloc( sizeof( unsigned portLONG ) ); - *( pxSecondSemaphoreParameters->pulSharedVariable ) = semtstBLOCKING_EXPECTED_VALUE; - pxSecondSemaphoreParameters->xBlockTime = xBlockTime / portTICK_RATE_MS; - - xTaskCreate( prvSemaphoreTest, ( signed portCHAR * ) "BlkSEM1", semtstSTACK_SIZE, ( void * ) pxSecondSemaphoreParameters, uxPriority, ( xTaskHandle * ) NULL ); - xTaskCreate( prvSemaphoreTest, ( signed portCHAR * ) "BlkSEM2", semtstSTACK_SIZE, ( void * ) pxSecondSemaphoreParameters, uxPriority, ( xTaskHandle * ) NULL ); - } - } -} -/*-----------------------------------------------------------*/ - -static portTASK_FUNCTION( prvSemaphoreTest, pvParameters ) -{ -xSemaphoreParameters *pxParameters; -volatile unsigned portLONG *pulSharedVariable, ulExpectedValue; -unsigned portLONG ulCounter; -portSHORT sError = pdFALSE, sCheckVariableToUse; - - /* See which check variable to use. sNextCheckVariable is not semaphore - protected! */ - portENTER_CRITICAL(); - sCheckVariableToUse = sNextCheckVariable; - sNextCheckVariable++; - portEXIT_CRITICAL(); - - /* A structure is passed in as the parameter. This contains the shared - variable being guarded. */ - pxParameters = ( xSemaphoreParameters * ) pvParameters; - pulSharedVariable = pxParameters->pulSharedVariable; - - /* If we are blocking we use a much higher count to ensure loads of context - switches occur during the count. */ - if( pxParameters->xBlockTime > ( portTickType ) 0 ) - { - ulExpectedValue = semtstBLOCKING_EXPECTED_VALUE; - } - else - { - ulExpectedValue = semtstNON_BLOCKING_EXPECTED_VALUE; - } - - for( ;; ) - { - /* Try to obtain the semaphore. */ - if( xSemaphoreTake( pxParameters->xSemaphore, pxParameters->xBlockTime ) == pdPASS ) - { - /* We have the semaphore and so expect any other tasks using the - shared variable to have left it in the state we expect to find - it. */ - if( *pulSharedVariable != ulExpectedValue ) - { - sError = pdTRUE; - } - - /* Clear the variable, then count it back up to the expected value - before releasing the semaphore. Would expect a context switch or - two during this time. */ - for( ulCounter = ( unsigned portLONG ) 0; ulCounter <= ulExpectedValue; ulCounter++ ) - { - *pulSharedVariable = ulCounter; - if( *pulSharedVariable != ulCounter ) - { - sError = pdTRUE; - } - } - - /* Release the semaphore, and if no errors have occurred increment the check - variable. */ - if( xSemaphoreGive( pxParameters->xSemaphore ) == pdFALSE ) - { - sError = pdTRUE; - } - - if( sError == pdFALSE ) - { - if( sCheckVariableToUse < semtstNUM_TASKS ) - { - ( sCheckVariables[ sCheckVariableToUse ] )++; - } - } - - /* If we have a block time then we are running at a priority higher - than the idle priority. This task takes a long time to complete - a cycle (deliberately so to test the guarding) so will be starving - out lower priority tasks. Block for some time to allow give lower - priority tasks some processor time. */ - vTaskDelay( pxParameters->xBlockTime * semtstDELAY_FACTOR ); - } - else - { - if( pxParameters->xBlockTime == ( portTickType ) 0 ) - { - /* We have not got the semaphore yet, so no point using the - processor. We are not blocking when attempting to obtain the - semaphore. */ - taskYIELD(); - } - } - } -} -/*-----------------------------------------------------------*/ - -/* This is called to check that all the created tasks are still running. */ -portBASE_TYPE xAreSemaphoreTasksStillRunning( void ) -{ -static portSHORT sLastCheckVariables[ semtstNUM_TASKS ] = { 0 }; -portBASE_TYPE xTask, xReturn = pdTRUE; - - for( xTask = 0; xTask < semtstNUM_TASKS; xTask++ ) - { - if( sLastCheckVariables[ xTask ] == sCheckVariables[ xTask ] ) - { - xReturn = pdFALSE; - } - - sLastCheckVariables[ xTask ] = sCheckVariables[ xTask ]; - } - - return xReturn; -} - - diff --git a/Demo/Common/ethernet/uIP/uip-1.0/README b/Demo/Common/ethernet/uIP/uip-1.0/README deleted file mode 100644 index 909f6520f..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/README +++ /dev/null @@ -1,13 +0,0 @@ -uIP is a very small implementation of the TCP/IP stack that is written -by Adam Dunkels . More information can be obtained -at the uIP homepage at http://www.sics.se/~adam/uip/. - -This is version $Name: uip-1-0 $. - -The directory structure look as follows: - -apps/ - Example applications -doc/ - Documentation -lib/ - Library code used by some applications -uip/ - uIP TCP/IP stack code -unix/ - uIP as a user space process under FreeBSD or Linux diff --git a/Demo/Common/ethernet/uIP/uip-1.0/apps/README b/Demo/Common/ethernet/uIP/uip-1.0/apps/README deleted file mode 100644 index f88920952..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/apps/README +++ /dev/null @@ -1,2 +0,0 @@ -This directory contains a few example applications. They are not all -heavily tested, however. diff --git a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/Makefile.webserver b/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/Makefile.webserver deleted file mode 100644 index f38c47a72..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/Makefile.webserver +++ /dev/null @@ -1 +0,0 @@ -APP_SOURCES += httpd.c http-strings.c httpd-fs.c httpd-cgi.c diff --git a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/http-strings b/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/http-strings deleted file mode 100644 index 0d3c30cdd..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/http-strings +++ /dev/null @@ -1,35 +0,0 @@ -http_http "http://" -http_200 "200 " -http_301 "301 " -http_302 "302 " -http_get "GET " -http_10 "HTTP/1.0" -http_11 "HTTP/1.1" -http_content_type "content-type: " -http_texthtml "text/html" -http_location "location: " -http_host "host: " -http_crnl "\r\n" -http_index_html "/index.html" -http_404_html "/404.html" -http_referer "Referer:" -http_header_200 "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" -http_header_404 "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" -http_content_type_plain "Content-type: text/plain\r\n\r\n" -http_content_type_html "Content-type: text/html\r\n\r\n" -http_content_type_css "Content-type: text/css\r\n\r\n" -http_content_type_text "Content-type: text/text\r\n\r\n" -http_content_type_png "Content-type: image/png\r\n\r\n" -http_content_type_gif "Content-type: image/gif\r\n\r\n" -http_content_type_jpg "Content-type: image/jpeg\r\n\r\n" -http_content_type_binary "Content-type: application/octet-stream\r\n\r\n" -http_html ".html" -http_shtml ".shtml" -http_htm ".htm" -http_css ".css" -http_png ".png" -http_gif ".gif" -http_jpg ".jpg" -http_text ".txt" -http_txt ".txt" - diff --git a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/http-strings.c b/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/http-strings.c deleted file mode 100644 index ef7a41c7d..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/http-strings.c +++ /dev/null @@ -1,102 +0,0 @@ -const char http_http[8] = -/* "http://" */ -{0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, }; -const char http_200[5] = -/* "200 " */ -{0x32, 0x30, 0x30, 0x20, }; -const char http_301[5] = -/* "301 " */ -{0x33, 0x30, 0x31, 0x20, }; -const char http_302[5] = -/* "302 " */ -{0x33, 0x30, 0x32, 0x20, }; -const char http_get[5] = -/* "GET " */ -{0x47, 0x45, 0x54, 0x20, }; -const char http_10[9] = -/* "HTTP/1.0" */ -{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, }; -const char http_11[9] = -/* "HTTP/1.1" */ -{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x31, }; -const char http_content_type[15] = -/* "content-type: " */ -{0x63, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, }; -const char http_texthtml[10] = -/* "text/html" */ -{0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, }; -const char http_location[11] = -/* "location: " */ -{0x6c, 0x6f, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, }; -const char http_host[7] = -/* "host: " */ -{0x68, 0x6f, 0x73, 0x74, 0x3a, 0x20, }; -const char http_crnl[3] = -/* "\r\n" */ -{0xd, 0xa, }; -const char http_index_html[12] = -/* "/index.html" */ -{0x2f, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x68, 0x74, 0x6d, 0x6c, }; -const char http_404_html[10] = -/* "/404.html" */ -{0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, }; -const char http_referer[9] = -/* "Referer:" */ -{0x52, 0x65, 0x66, 0x65, 0x72, 0x65, 0x72, 0x3a, }; -const char http_header_200[84] = -/* "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */ -{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x32, 0x30, 0x30, 0x20, 0x4f, 0x4b, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, }; -const char http_header_404[91] = -/* "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */ -{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x34, 0x30, 0x34, 0x20, 0x4e, 0x6f, 0x74, 0x20, 0x66, 0x6f, 0x75, 0x6e, 0x64, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, }; -const char http_content_type_plain[29] = -/* "Content-type: text/plain\r\n\r\n" */ -{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x70, 0x6c, 0x61, 0x69, 0x6e, 0xd, 0xa, 0xd, 0xa, }; -const char http_content_type_html[28] = -/* "Content-type: text/html\r\n\r\n" */ -{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0xd, 0xa, 0xd, 0xa, }; -const char http_content_type_css [27] = -/* "Content-type: text/css\r\n\r\n" */ -{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x63, 0x73, 0x73, 0xd, 0xa, 0xd, 0xa, }; -const char http_content_type_text[28] = -/* "Content-type: text/text\r\n\r\n" */ -{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x74, 0x65, 0x78, 0x74, 0xd, 0xa, 0xd, 0xa, }; -const char http_content_type_png [28] = -/* "Content-type: image/png\r\n\r\n" */ -{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x70, 0x6e, 0x67, 0xd, 0xa, 0xd, 0xa, }; -const char http_content_type_gif [28] = -/* "Content-type: image/gif\r\n\r\n" */ -{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x67, 0x69, 0x66, 0xd, 0xa, 0xd, 0xa, }; -const char http_content_type_jpg [29] = -/* "Content-type: image/jpeg\r\n\r\n" */ -{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x6a, 0x70, 0x65, 0x67, 0xd, 0xa, 0xd, 0xa, }; -const char http_content_type_binary[43] = -/* "Content-type: application/octet-stream\r\n\r\n" */ -{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x2f, 0x6f, 0x63, 0x74, 0x65, 0x74, 0x2d, 0x73, 0x74, 0x72, 0x65, 0x61, 0x6d, 0xd, 0xa, 0xd, 0xa, }; -const char http_html[6] = -/* ".html" */ -{0x2e, 0x68, 0x74, 0x6d, 0x6c, }; -const char http_shtml[7] = -/* ".shtml" */ -{0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, }; -const char http_htm[5] = -/* ".htm" */ -{0x2e, 0x68, 0x74, 0x6d, }; -const char http_css[5] = -/* ".css" */ -{0x2e, 0x63, 0x73, 0x73, }; -const char http_png[5] = -/* ".png" */ -{0x2e, 0x70, 0x6e, 0x67, }; -const char http_gif[5] = -/* ".gif" */ -{0x2e, 0x67, 0x69, 0x66, }; -const char http_jpg[5] = -/* ".jpg" */ -{0x2e, 0x6a, 0x70, 0x67, }; -const char http_text[5] = -/* ".txt" */ -{0x2e, 0x74, 0x78, 0x74, }; -const char http_txt[5] = -/* ".txt" */ -{0x2e, 0x74, 0x78, 0x74, }; diff --git a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/http-strings.h b/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/http-strings.h deleted file mode 100644 index acbe7e17f..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/http-strings.h +++ /dev/null @@ -1,34 +0,0 @@ -extern const char http_http[8]; -extern const char http_200[5]; -extern const char http_301[5]; -extern const char http_302[5]; -extern const char http_get[5]; -extern const char http_10[9]; -extern const char http_11[9]; -extern const char http_content_type[15]; -extern const char http_texthtml[10]; -extern const char http_location[11]; -extern const char http_host[7]; -extern const char http_crnl[3]; -extern const char http_index_html[12]; -extern const char http_404_html[10]; -extern const char http_referer[9]; -extern const char http_header_200[84]; -extern const char http_header_404[91]; -extern const char http_content_type_plain[29]; -extern const char http_content_type_html[28]; -extern const char http_content_type_css [27]; -extern const char http_content_type_text[28]; -extern const char http_content_type_png [28]; -extern const char http_content_type_gif [28]; -extern const char http_content_type_jpg [29]; -extern const char http_content_type_binary[43]; -extern const char http_html[6]; -extern const char http_shtml[7]; -extern const char http_htm[5]; -extern const char http_css[5]; -extern const char http_png[5]; -extern const char http_gif[5]; -extern const char http_jpg[5]; -extern const char http_text[5]; -extern const char http_txt[5]; diff --git a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-cgi.c b/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-cgi.c deleted file mode 100644 index f845c7aa8..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-cgi.c +++ /dev/null @@ -1,203 +0,0 @@ -/** - * \addtogroup httpd - * @{ - */ - -/** - * \file - * Web server script interface - * \author - * Adam Dunkels - * - */ - -/* - * Copyright (c) 2001-2006, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: httpd-cgi.c,v 1.2 2006/06/11 21:46:37 adam Exp $ - * - */ - -#include "uip.h" -#include "psock.h" -#include "httpd.h" -#include "httpd-cgi.h" -#include "httpd-fs.h" - -#include -#include - -HTTPD_CGI_CALL(file, "file-stats", file_stats); -HTTPD_CGI_CALL(tcp, "tcp-connections", tcp_stats); -HTTPD_CGI_CALL(net, "net-stats", net_stats); - -static const struct httpd_cgi_call *calls[] = { &file, &tcp, &net, NULL }; - -/*---------------------------------------------------------------------------*/ -static -PT_THREAD(nullfunction(struct httpd_state *s, char *ptr)) -{ - PSOCK_BEGIN(&s->sout); - PSOCK_END(&s->sout); -} -/*---------------------------------------------------------------------------*/ -httpd_cgifunction -httpd_cgi(char *name) -{ - const struct httpd_cgi_call **f; - - /* Find the matching name in the table, return the function. */ - for(f = calls; *f != NULL; ++f) { - if(strncmp((*f)->name, name, strlen((*f)->name)) == 0) { - return (*f)->function; - } - } - return nullfunction; -} -/*---------------------------------------------------------------------------*/ -static unsigned short -generate_file_stats(void *arg) -{ - char *f = (char *)arg; - return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, "%5u", httpd_fs_count(f)); -} -/*---------------------------------------------------------------------------*/ -static -PT_THREAD(file_stats(struct httpd_state *s, char *ptr)) -{ - PSOCK_BEGIN(&s->sout); - - PSOCK_GENERATOR_SEND(&s->sout, generate_file_stats, strchr(ptr, ' ') + 1); - - PSOCK_END(&s->sout); -} -/*---------------------------------------------------------------------------*/ -static const char closed[] = /* "CLOSED",*/ -{0x43, 0x4c, 0x4f, 0x53, 0x45, 0x44, 0}; -static const char syn_rcvd[] = /* "SYN-RCVD",*/ -{0x53, 0x59, 0x4e, 0x2d, 0x52, 0x43, 0x56, - 0x44, 0}; -static const char syn_sent[] = /* "SYN-SENT",*/ -{0x53, 0x59, 0x4e, 0x2d, 0x53, 0x45, 0x4e, - 0x54, 0}; -static const char established[] = /* "ESTABLISHED",*/ -{0x45, 0x53, 0x54, 0x41, 0x42, 0x4c, 0x49, 0x53, 0x48, - 0x45, 0x44, 0}; -static const char fin_wait_1[] = /* "FIN-WAIT-1",*/ -{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, - 0x54, 0x2d, 0x31, 0}; -static const char fin_wait_2[] = /* "FIN-WAIT-2",*/ -{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, - 0x54, 0x2d, 0x32, 0}; -static const char closing[] = /* "CLOSING",*/ -{0x43, 0x4c, 0x4f, 0x53, 0x49, - 0x4e, 0x47, 0}; -static const char time_wait[] = /* "TIME-WAIT,"*/ -{0x54, 0x49, 0x4d, 0x45, 0x2d, 0x57, 0x41, - 0x49, 0x54, 0}; -static const char last_ack[] = /* "LAST-ACK"*/ -{0x4c, 0x41, 0x53, 0x54, 0x2d, 0x41, 0x43, - 0x4b, 0}; - -static const char *states[] = { - closed, - syn_rcvd, - syn_sent, - established, - fin_wait_1, - fin_wait_2, - closing, - time_wait, - last_ack}; - - -static unsigned short -generate_tcp_stats(void *arg) -{ - struct uip_conn *conn; - struct httpd_state *s = (struct httpd_state *)arg; - - conn = &uip_conns[s->count]; - return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, - "\r\n", - htons(conn->lport), - htons(conn->ripaddr[0]) >> 8, - htons(conn->ripaddr[0]) & 0xff, - htons(conn->ripaddr[1]) >> 8, - htons(conn->ripaddr[1]) & 0xff, - htons(conn->rport), - states[conn->tcpstateflags & UIP_TS_MASK], - conn->nrtx, - conn->timer, - (uip_outstanding(conn))? '*':' ', - (uip_stopped(conn))? '!':' '); -} -/*---------------------------------------------------------------------------*/ -static -PT_THREAD(tcp_stats(struct httpd_state *s, char *ptr)) -{ - - PSOCK_BEGIN(&s->sout); - - for(s->count = 0; s->count < UIP_CONNS; ++s->count) { - if((uip_conns[s->count].tcpstateflags & UIP_TS_MASK) != UIP_CLOSED) { - PSOCK_GENERATOR_SEND(&s->sout, generate_tcp_stats, s); - } - } - - PSOCK_END(&s->sout); -} -/*---------------------------------------------------------------------------*/ -static unsigned short -generate_net_stats(void *arg) -{ - struct httpd_state *s = (struct httpd_state *)arg; - return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, - "%5u\n", ((uip_stats_t *)&uip_stat)[s->count]); -} - -static -PT_THREAD(net_stats(struct httpd_state *s, char *ptr)) -{ - PSOCK_BEGIN(&s->sout); - -#if UIP_STATISTICS - - for(s->count = 0; s->count < sizeof(uip_stat) / sizeof(uip_stats_t); - ++s->count) { - PSOCK_GENERATOR_SEND(&s->sout, generate_net_stats, s); - } - -#endif /* UIP_STATISTICS */ - - PSOCK_END(&s->sout); -} -/*---------------------------------------------------------------------------*/ -/** @} */ diff --git a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-cgi.h b/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-cgi.h deleted file mode 100644 index 7ae928321..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-cgi.h +++ /dev/null @@ -1,84 +0,0 @@ -/** - * \addtogroup httpd - * @{ - */ - -/** - * \file - * Web server script interface header file - * \author - * Adam Dunkels - * - */ - - - -/* - * Copyright (c) 2001, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: httpd-cgi.h,v 1.2 2006/06/11 21:46:38 adam Exp $ - * - */ - -#ifndef __HTTPD_CGI_H__ -#define __HTTPD_CGI_H__ - -#include "psock.h" -#include "httpd.h" - -typedef PT_THREAD((* httpd_cgifunction)(struct httpd_state *, char *)); - -httpd_cgifunction httpd_cgi(char *name); - -struct httpd_cgi_call { - const char *name; - const httpd_cgifunction function; -}; - -/** - * \brief HTTPD CGI function declaration - * \param name The C variable name of the function - * \param str The string name of the function, used in the script file - * \param function A pointer to the function that implements it - * - * This macro is used for declaring a HTTPD CGI - * function. This function is then added to the list of - * HTTPD CGI functions with the httpd_cgi_add() function. - * - * \hideinitializer - */ -#define HTTPD_CGI_CALL(name, str, function) \ -static PT_THREAD(function(struct httpd_state *, char *)); \ -static const struct httpd_cgi_call name = {str, function} - -void httpd_cgi_init(void); -#endif /* __HTTPD_CGI_H__ */ - -/** @} */ diff --git a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs.c b/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs.c deleted file mode 100644 index dc4aef011..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs.c +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright (c) 2001, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - * $Id: httpd-fs.c,v 1.1 2006/06/07 09:13:08 adam Exp $ - */ - -#include "httpd.h" -#include "httpd-fs.h" -#include "httpd-fsdata.h" - -#ifndef NULL -#define NULL 0 -#endif /* NULL */ - -#include "httpd-fsdata.c" - -#if HTTPD_FS_STATISTICS -static u16_t count[HTTPD_FS_NUMFILES]; -#endif /* HTTPD_FS_STATISTICS */ - -/*-----------------------------------------------------------------------------------*/ -static u8_t -httpd_fs_strcmp(const char *str1, const char *str2) -{ - u8_t i; - i = 0; - loop: - - if(str2[i] == 0 || - str1[i] == '\r' || - str1[i] == '\n') { - return 0; - } - - if(str1[i] != str2[i]) { - return 1; - } - - - ++i; - goto loop; -} -/*-----------------------------------------------------------------------------------*/ -int -httpd_fs_open(const char *name, struct httpd_fs_file *file) -{ -#if HTTPD_FS_STATISTICS - u16_t i = 0; -#endif /* HTTPD_FS_STATISTICS */ - struct httpd_fsdata_file_noconst *f; - - for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT; - f != NULL; - f = (struct httpd_fsdata_file_noconst *)f->next) { - - if(httpd_fs_strcmp(name, f->name) == 0) { - file->data = f->data; - file->len = f->len; -#if HTTPD_FS_STATISTICS - ++count[i]; -#endif /* HTTPD_FS_STATISTICS */ - return 1; - } -#if HTTPD_FS_STATISTICS - ++i; -#endif /* HTTPD_FS_STATISTICS */ - - } - return 0; -} -/*-----------------------------------------------------------------------------------*/ -void -httpd_fs_init(void) -{ -#if HTTPD_FS_STATISTICS - u16_t i; - for(i = 0; i < HTTPD_FS_NUMFILES; i++) { - count[i] = 0; - } -#endif /* HTTPD_FS_STATISTICS */ -} -/*-----------------------------------------------------------------------------------*/ -#if HTTPD_FS_STATISTICS -u16_t httpd_fs_count -(char *name) -{ - struct httpd_fsdata_file_noconst *f; - u16_t i; - - i = 0; - for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT; - f != NULL; - f = (struct httpd_fsdata_file_noconst *)f->next) { - - if(httpd_fs_strcmp(name, f->name) == 0) { - return count[i]; - } - ++i; - } - return 0; -} -#endif /* HTTPD_FS_STATISTICS */ -/*-----------------------------------------------------------------------------------*/ diff --git a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs.h b/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs.h deleted file mode 100644 index b594eea56..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (c) 2001, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - * $Id: httpd-fs.h,v 1.1 2006/06/07 09:13:08 adam Exp $ - */ -#ifndef __HTTPD_FS_H__ -#define __HTTPD_FS_H__ - -#define HTTPD_FS_STATISTICS 1 - -struct httpd_fs_file { - char *data; - int len; -}; - -/* file must be allocated by caller and will be filled in - by the function. */ -int httpd_fs_open(const char *name, struct httpd_fs_file *file); - -#ifdef HTTPD_FS_STATISTICS -#if HTTPD_FS_STATISTICS == 1 -u16_t httpd_fs_count(char *name); -#endif /* HTTPD_FS_STATISTICS */ -#endif /* HTTPD_FS_STATISTICS */ - -void httpd_fs_init(void); - -#endif /* __HTTPD_FS_H__ */ diff --git a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/404.html b/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/404.html deleted file mode 100644 index 43e7f4cad..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/404.html +++ /dev/null @@ -1,8 +0,0 @@ - - -
-

404 - file not found

-

Go here instead.

-
- - \ No newline at end of file diff --git a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/fade.png b/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/fade.png deleted file mode 100644 index a9e69f75d..000000000 Binary files a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/fade.png and /dev/null differ diff --git a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/files.shtml b/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/files.shtml deleted file mode 100644 index 361cc1dc1..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/files.shtml +++ /dev/null @@ -1,35 +0,0 @@ -%!: /header.html -

File statistics

-
-
LocalRemoteStateRetransmissionsTimerFlags
%d%u.%u.%u.%u:%u%s%u%u%c %c
- - - - - - - - - - - - - - -
/index.html%! file-stats /index.html -
/files.shtml%! file-stats /files.shtml -
/tcp.shtml%! file-stats /tcp.shtml -
/stats.shtml%! file-stats /stats.shtml -
/style.css%! file-stats /style.css -
/404.html%! file-stats /404.html -
/fade.png%! file-stats /fade.png -
- -%!: /footer.html diff --git a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/footer.html b/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/footer.html deleted file mode 100644 index 290832ddc..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/footer.html +++ /dev/null @@ -1,2 +0,0 @@ - - \ No newline at end of file diff --git a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/header.html b/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/header.html deleted file mode 100644 index 0c3c4efa9..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/header.html +++ /dev/null @@ -1,18 +0,0 @@ - - - - Welcome to the uIP web server! - - - - -

-
Front page
-
File statistics
-
Network statistics
-
Network - connections
-
-
- -
diff --git a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/index.html b/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/index.html deleted file mode 100644 index 7af64c8df..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/index.html +++ /dev/null @@ -1,29 +0,0 @@ - - - - Welcome to the uIP web server! - - - - -
-
Front page
-
File statistics
-
Network statistics
-
Network - connections
-
-
- -
-

- These web pages are served by a small web server running on top of - the uIP embedded TCP/IP - stack. -

-

- Click on the links above for web server statistics. -

- - - diff --git a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/processes.shtml b/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/processes.shtml deleted file mode 100644 index be857f9eb..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/processes.shtml +++ /dev/null @@ -1,5 +0,0 @@ -%!: /header.html -

System processes


- -%! processes -%!: /footer.html \ No newline at end of file diff --git a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/stats.shtml b/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/stats.shtml deleted file mode 100644 index 7eb381af9..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/stats.shtml +++ /dev/null @@ -1,31 +0,0 @@ -%!: /header.html -

Network statistics

-
-
IDNamePriorityPoll handlerEvent handlerProcstate
-
-IP           Packets received
-             Packets sent
-	     Packets dropped
-IP errors    IP version/header length
-             IP length, high byte
-             IP length, low byte
-             IP fragments
-             Header checksum
-             Wrong protocol
-ICMP	     Packets received
-             Packets sent
-             Packets dropped
-             Type errors
-TCP          Packets received
-             Packets sent
-             Packets dropped
-             Checksum errors
-             Data packets without ACKs
-             Resets
-             Retransmissions
-	     No connection avaliable
-	     Connection attempts to closed ports
-
%! net-stats
-
- -%!: /footer.html diff --git a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/style.css b/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/style.css deleted file mode 100644 index 089fe84f2..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/style.css +++ /dev/null @@ -1,92 +0,0 @@ -h1 -{ - text-align: center; - font-size:14pt; - font-family:arial,helvetica; - font-weight:bold; - padding:10px; -} - -body -{ - - background-color: #fffeec; - color:black; - - font-size:8pt; - font-family:arial,helvetica; -} - -.menu -{ - margin: 4px; - width:60%; - - padding:2px; - - border: solid 1px; - background-color: #fffcd2; - text-align:left; - - font-size:9pt; - font-family:arial,helvetica; -} - -div.menubox -{ - width: 25%; - border: 0; - float: left; -text-align: center; -} - -.contentblock -{ - margin: 4px; - width:60%; - - padding:2px; - - border: 1px dotted; - background-color: white; - - font-size:8pt; - font-family:arial,helvetica; - -} - -p.intro -{ - margin-left:20px; - margin-right:20px; - - font-size:10pt; -/* font-weight:bold; */ - font-family:arial,helvetica; -} - -p.clink -{ - font-size:12pt; - font-family:courier,monospace; - text-align:center; -} - -p.clink9 -{ - font-size:9pt; - font-family:courier,monospace; - text-align:center; -} - - -p -{ - padding-left:10px; -} - -p.right -{ - text-align:right; -} - diff --git a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/tcp.shtml b/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/tcp.shtml deleted file mode 100644 index 2404aedf0..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fs/tcp.shtml +++ /dev/null @@ -1,5 +0,0 @@ -%!: /header.html -

Current connections


- -%! tcp-connections -%!: /footer.html \ No newline at end of file diff --git a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fsdata.c b/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fsdata.c deleted file mode 100644 index 29e5a1b96..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fsdata.c +++ /dev/null @@ -1,607 +0,0 @@ -static const unsigned char data_processes_shtml[] = { - /* /processes.shtml */ - 0x2f, 0x70, 0x72, 0x6f, 0x63, 0x65, 0x73, 0x73, 0x65, 0x73, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0, - 0x25, 0x21, 0x3a, 0x20, 0x2f, 0x68, 0x65, 0x61, 0x64, 0x65, - 0x72, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0xa, 0x3c, 0x68, 0x31, - 0x3e, 0x53, 0x79, 0x73, 0x74, 0x65, 0x6d, 0x20, 0x70, 0x72, - 0x6f, 0x63, 0x65, 0x73, 0x73, 0x65, 0x73, 0x3c, 0x2f, 0x68, - 0x31, 0x3e, 0x3c, 0x62, 0x72, 0x3e, 0x3c, 0x74, 0x61, 0x62, - 0x6c, 0x65, 0x20, 0x77, 0x69, 0x64, 0x74, 0x68, 0x3d, 0x22, - 0x31, 0x30, 0x30, 0x25, 0x22, 0x3e, 0xa, 0x3c, 0x74, 0x72, - 0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x49, 0x44, 0x3c, 0x2f, 0x74, - 0x68, 0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x4e, 0x61, 0x6d, 0x65, - 0x3c, 0x2f, 0x74, 0x68, 0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x50, - 0x72, 0x69, 0x6f, 0x72, 0x69, 0x74, 0x79, 0x3c, 0x2f, 0x74, - 0x68, 0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x50, 0x6f, 0x6c, 0x6c, - 0x20, 0x68, 0x61, 0x6e, 0x64, 0x6c, 0x65, 0x72, 0x3c, 0x2f, - 0x74, 0x68, 0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x45, 0x76, 0x65, - 0x6e, 0x74, 0x20, 0x68, 0x61, 0x6e, 0x64, 0x6c, 0x65, 0x72, - 0x3c, 0x2f, 0x74, 0x68, 0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x50, - 0x72, 0x6f, 0x63, 0x73, 0x74, 0x61, 0x74, 0x65, 0x3c, 0x2f, - 0x74, 0x68, 0x3e, 0x3c, 0x2f, 0x74, 0x72, 0x3e, 0xa, 0x25, - 0x21, 0x20, 0x70, 0x72, 0x6f, 0x63, 0x65, 0x73, 0x73, 0x65, - 0x73, 0xa, 0x25, 0x21, 0x3a, 0x20, 0x2f, 0x66, 0x6f, 0x6f, - 0x74, 0x65, 0x72, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0}; - -static const unsigned char data_404_html[] = { - /* /404.html */ - 0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0, - 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xa, 0x20, 0x20, 0x3c, - 0x62, 0x6f, 0x64, 0x79, 0x20, 0x62, 0x67, 0x63, 0x6f, 0x6c, - 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0x65, 0x3e, 0x3c, 0x2f, 0x74, 0x64, 0x3e, 0x3c, 0x74, 0x64, - 0x3e, 0x3c, 0x70, 0x72, 0x65, 0x3e, 0x25, 0x21, 0x20, 0x6e, - 0x65, 0x74, 0x2d, 0x73, 0x74, 0x61, 0x74, 0x73, 0xa, 0x3c, - 0x2f, 0x70, 0x72, 0x65, 0x3e, 0x3c, 0x2f, 0x74, 0x61, 0x62, - 0x6c, 0x65, 0x3e, 0xa, 0x3c, 0x2f, 0x63, 0x65, 0x6e, 0x74, - 0x65, 0x72, 0x3e, 0xa, 0x25, 0x21, 0x3a, 0x20, 0x2f, 0x66, - 0x6f, 0x6f, 0x74, 0x65, 0x72, 0x2e, 0x68, 0x74, 0x6d, 0x6c, - 0xa, 0}; - -const struct httpd_fsdata_file file_processes_shtml[] = {{NULL, data_processes_shtml, data_processes_shtml + 17, sizeof(data_processes_shtml) - 17}}; - -const struct httpd_fsdata_file file_404_html[] = {{file_processes_shtml, data_404_html, data_404_html + 10, sizeof(data_404_html) - 10}}; - -const struct httpd_fsdata_file file_files_shtml[] = {{file_404_html, data_files_shtml, data_files_shtml + 13, sizeof(data_files_shtml) - 13}}; - -const struct httpd_fsdata_file file_footer_html[] = {{file_files_shtml, data_footer_html, data_footer_html + 13, sizeof(data_footer_html) - 13}}; - -const struct httpd_fsdata_file file_header_html[] = {{file_footer_html, data_header_html, data_header_html + 13, sizeof(data_header_html) - 13}}; - -const struct httpd_fsdata_file file_index_html[] = {{file_header_html, data_index_html, data_index_html + 12, sizeof(data_index_html) - 12}}; - -const struct httpd_fsdata_file file_style_css[] = {{file_index_html, data_style_css, data_style_css + 11, sizeof(data_style_css) - 11}}; - -const struct httpd_fsdata_file file_tcp_shtml[] = {{file_style_css, data_tcp_shtml, data_tcp_shtml + 11, sizeof(data_tcp_shtml) - 11}}; - -const struct httpd_fsdata_file file_fade_png[] = {{file_tcp_shtml, data_fade_png, data_fade_png + 10, sizeof(data_fade_png) - 10}}; - -const struct httpd_fsdata_file file_stats_shtml[] = {{file_fade_png, data_stats_shtml, data_stats_shtml + 13, sizeof(data_stats_shtml) - 13}}; - -#define HTTPD_FS_ROOT file_stats_shtml - -#define HTTPD_FS_NUMFILES 10 diff --git a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fsdata.h b/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fsdata.h deleted file mode 100644 index 52d35c265..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd-fsdata.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2001, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - * $Id: httpd-fsdata.h,v 1.1 2006/06/07 09:13:08 adam Exp $ - */ -#ifndef __HTTPD_FSDATA_H__ -#define __HTTPD_FSDATA_H__ - -#include "uip.h" - -struct httpd_fsdata_file { - const struct httpd_fsdata_file *next; - const char *name; - const char *data; - const int len; -#ifdef HTTPD_FS_STATISTICS -#if HTTPD_FS_STATISTICS == 1 - u16_t count; -#endif /* HTTPD_FS_STATISTICS */ -#endif /* HTTPD_FS_STATISTICS */ -}; - -struct httpd_fsdata_file_noconst { - struct httpd_fsdata_file *next; - char *name; - char *data; - int len; -#ifdef HTTPD_FS_STATISTICS -#if HTTPD_FS_STATISTICS == 1 - u16_t count; -#endif /* HTTPD_FS_STATISTICS */ -#endif /* HTTPD_FS_STATISTICS */ -}; - -#endif /* __HTTPD_FSDATA_H__ */ diff --git a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd.c b/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd.c deleted file mode 100644 index e808688d2..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd.c +++ /dev/null @@ -1,338 +0,0 @@ -/** - * \addtogroup apps - * @{ - */ - -/** - * \defgroup httpd Web server - * @{ - * The uIP web server is a very simplistic implementation of an HTTP - * server. It can serve web pages and files from a read-only ROM - * filesystem, and provides a very small scripting language. - - */ - -/** - * \file - * Web server - * \author - * Adam Dunkels - */ - - -/* - * Copyright (c) 2004, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * Author: Adam Dunkels - * - * $Id: httpd.c,v 1.2 2006/06/11 21:46:38 adam Exp $ - */ - -#include "uip.h" -#include "httpd.h" -#include "httpd-fs.h" -#include "httpd-cgi.h" -#include "http-strings.h" - -#include - -#define STATE_WAITING 0 -#define STATE_OUTPUT 1 - -#define ISO_nl 0x0a -#define ISO_space 0x20 -#define ISO_bang 0x21 -#define ISO_percent 0x25 -#define ISO_period 0x2e -#define ISO_slash 0x2f -#define ISO_colon 0x3a - - -/*---------------------------------------------------------------------------*/ -static unsigned short -generate_part_of_file(void *state) -{ - struct httpd_state *s = (struct httpd_state *)state; - - if(s->file.len > uip_mss()) { - s->len = uip_mss(); - } else { - s->len = s->file.len; - } - memcpy(uip_appdata, s->file.data, s->len); - - return s->len; -} -/*---------------------------------------------------------------------------*/ -static -PT_THREAD(send_file(struct httpd_state *s)) -{ - PSOCK_BEGIN(&s->sout); - - do { - PSOCK_GENERATOR_SEND(&s->sout, generate_part_of_file, s); - s->file.len -= s->len; - s->file.data += s->len; - } while(s->file.len > 0); - - PSOCK_END(&s->sout); -} -/*---------------------------------------------------------------------------*/ -static -PT_THREAD(send_part_of_file(struct httpd_state *s)) -{ - PSOCK_BEGIN(&s->sout); - - PSOCK_SEND(&s->sout, s->file.data, s->len); - - PSOCK_END(&s->sout); -} -/*---------------------------------------------------------------------------*/ -static void -next_scriptstate(struct httpd_state *s) -{ - char *p; - p = strchr(s->scriptptr, ISO_nl) + 1; - s->scriptlen -= (unsigned short)(p - s->scriptptr); - s->scriptptr = p; -} -/*---------------------------------------------------------------------------*/ -static -PT_THREAD(handle_script(struct httpd_state *s)) -{ - char *ptr; - - PT_BEGIN(&s->scriptpt); - - - while(s->file.len > 0) { - - /* Check if we should start executing a script. */ - if(*s->file.data == ISO_percent && - *(s->file.data + 1) == ISO_bang) { - s->scriptptr = s->file.data + 3; - s->scriptlen = s->file.len - 3; - if(*(s->scriptptr - 1) == ISO_colon) { - httpd_fs_open(s->scriptptr + 1, &s->file); - PT_WAIT_THREAD(&s->scriptpt, send_file(s)); - } else { - PT_WAIT_THREAD(&s->scriptpt, - httpd_cgi(s->scriptptr)(s, s->scriptptr)); - } - next_scriptstate(s); - - /* The script is over, so we reset the pointers and continue - sending the rest of the file. */ - s->file.data = s->scriptptr; - s->file.len = s->scriptlen; - } else { - /* See if we find the start of script marker in the block of HTML - to be sent. */ - - if(s->file.len > uip_mss()) { - s->len = uip_mss(); - } else { - s->len = s->file.len; - } - - if(*s->file.data == ISO_percent) { - ptr = strchr(s->file.data + 1, ISO_percent); - } else { - ptr = strchr(s->file.data, ISO_percent); - } - if(ptr != NULL && - ptr != s->file.data) { - s->len = (int)(ptr - s->file.data); - if(s->len >= uip_mss()) { - s->len = uip_mss(); - } - } - PT_WAIT_THREAD(&s->scriptpt, send_part_of_file(s)); - s->file.data += s->len; - s->file.len -= s->len; - - } - } - - PT_END(&s->scriptpt); -} -/*---------------------------------------------------------------------------*/ -static -PT_THREAD(send_headers(struct httpd_state *s, const char *statushdr)) -{ - char *ptr; - - PSOCK_BEGIN(&s->sout); - - PSOCK_SEND_STR(&s->sout, statushdr); - - ptr = strrchr(s->filename, ISO_period); - if(ptr == NULL) { - PSOCK_SEND_STR(&s->sout, http_content_type_binary); - } else if(strncmp(http_html, ptr, 5) == 0 || - strncmp(http_shtml, ptr, 6) == 0) { - PSOCK_SEND_STR(&s->sout, http_content_type_html); - } else if(strncmp(http_css, ptr, 4) == 0) { - PSOCK_SEND_STR(&s->sout, http_content_type_css); - } else if(strncmp(http_png, ptr, 4) == 0) { - PSOCK_SEND_STR(&s->sout, http_content_type_png); - } else if(strncmp(http_gif, ptr, 4) == 0) { - PSOCK_SEND_STR(&s->sout, http_content_type_gif); - } else if(strncmp(http_jpg, ptr, 4) == 0) { - PSOCK_SEND_STR(&s->sout, http_content_type_jpg); - } else { - PSOCK_SEND_STR(&s->sout, http_content_type_plain); - } - PSOCK_END(&s->sout); -} -/*---------------------------------------------------------------------------*/ -static -PT_THREAD(handle_output(struct httpd_state *s)) -{ - char *ptr; - - PT_BEGIN(&s->outputpt); - - if(!httpd_fs_open(s->filename, &s->file)) { - httpd_fs_open(http_404_html, &s->file); - strcpy(s->filename, http_404_html); - PT_WAIT_THREAD(&s->outputpt, - send_headers(s, - http_header_404)); - PT_WAIT_THREAD(&s->outputpt, - send_file(s)); - } else { - PT_WAIT_THREAD(&s->outputpt, - send_headers(s, - http_header_200)); - ptr = strchr(s->filename, ISO_period); - if(ptr != NULL && strncmp(ptr, http_shtml, 6) == 0) { - PT_INIT(&s->scriptpt); - PT_WAIT_THREAD(&s->outputpt, handle_script(s)); - } else { - PT_WAIT_THREAD(&s->outputpt, - send_file(s)); - } - } - PSOCK_CLOSE(&s->sout); - PT_END(&s->outputpt); -} -/*---------------------------------------------------------------------------*/ -static -PT_THREAD(handle_input(struct httpd_state *s)) -{ - PSOCK_BEGIN(&s->sin); - - PSOCK_READTO(&s->sin, ISO_space); - - - if(strncmp(s->inputbuf, http_get, 4) != 0) { - PSOCK_CLOSE_EXIT(&s->sin); - } - PSOCK_READTO(&s->sin, ISO_space); - - if(s->inputbuf[0] != ISO_slash) { - PSOCK_CLOSE_EXIT(&s->sin); - } - - if(s->inputbuf[1] == ISO_space) { - strncpy(s->filename, http_index_html, sizeof(s->filename)); - } else { - s->inputbuf[PSOCK_DATALEN(&s->sin) - 1] = 0; - strncpy(s->filename, &s->inputbuf[0], sizeof(s->filename)); - } - - /* httpd_log_file(uip_conn->ripaddr, s->filename);*/ - - s->state = STATE_OUTPUT; - - while(1) { - PSOCK_READTO(&s->sin, ISO_nl); - - if(strncmp(s->inputbuf, http_referer, 8) == 0) { - s->inputbuf[PSOCK_DATALEN(&s->sin) - 2] = 0; - /* httpd_log(&s->inputbuf[9]);*/ - } - } - - PSOCK_END(&s->sin); -} -/*---------------------------------------------------------------------------*/ -static void -handle_connection(struct httpd_state *s) -{ - handle_input(s); - if(s->state == STATE_OUTPUT) { - handle_output(s); - } -} -/*---------------------------------------------------------------------------*/ -void -httpd_appcall(void) -{ - struct httpd_state *s = (struct httpd_state *)&(uip_conn->appstate); - - if(uip_closed() || uip_aborted() || uip_timedout()) { - } else if(uip_connected()) { - PSOCK_INIT(&s->sin, s->inputbuf, sizeof(s->inputbuf) - 1); - PSOCK_INIT(&s->sout, s->inputbuf, sizeof(s->inputbuf) - 1); - PT_INIT(&s->outputpt); - s->state = STATE_WAITING; - /* timer_set(&s->timer, CLOCK_SECOND * 100);*/ - s->timer = 0; - handle_connection(s); - } else if(s != NULL) { - if(uip_poll()) { - ++s->timer; - if(s->timer >= 20) { - uip_abort(); - } - } else { - s->timer = 0; - } - handle_connection(s); - } else { - uip_abort(); - } -} -/*---------------------------------------------------------------------------*/ -/** - * \brief Initialize the web server - * - * This function initializes the web server and should be - * called at system boot-up. - */ -void -httpd_init(void) -{ - uip_listen(HTONS(80)); -} -/*---------------------------------------------------------------------------*/ -/** @} */ diff --git a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd.h b/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd.h deleted file mode 100644 index 7f7a6666e..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/httpd.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (c) 2001-2005, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: httpd.h,v 1.2 2006/06/11 21:46:38 adam Exp $ - * - */ - -#ifndef __HTTPD_H__ -#define __HTTPD_H__ - -#include "psock.h" -#include "httpd-fs.h" - -struct httpd_state { - unsigned char timer; - struct psock sin, sout; - struct pt outputpt, scriptpt; - char inputbuf[50]; - char filename[20]; - char state; - struct httpd_fs_file file; - int len; - char *scriptptr; - int scriptlen; - - unsigned short count; -}; - -void httpd_init(void); -void httpd_appcall(void); - -void httpd_log(char *msg); -void httpd_log_file(u16_t *requester, char *file); - -#endif /* __HTTPD_H__ */ diff --git a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/makefsdata b/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/makefsdata deleted file mode 100644 index 8d2715a8a..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/makefsdata +++ /dev/null @@ -1,78 +0,0 @@ -#!/usr/bin/perl - -open(OUTPUT, "> httpd-fsdata.c"); - -chdir("httpd-fs"); - -opendir(DIR, "."); -@files = grep { !/^\./ && !/(CVS|~)/ } readdir(DIR); -closedir(DIR); - -foreach $file (@files) { - - if(-d $file && $file !~ /^\./) { - print "Processing directory $file\n"; - opendir(DIR, $file); - @newfiles = grep { !/^\./ && !/(CVS|~)/ } readdir(DIR); - closedir(DIR); - printf "Adding files @newfiles\n"; - @files = (@files, map { $_ = "$file/$_" } @newfiles); - next; - } -} - -foreach $file (@files) { - if(-f $file) { - - print "Adding file $file\n"; - - open(FILE, $file) || die "Could not open file $file\n"; - - $file =~ s-^-/-; - $fvar = $file; - $fvar =~ s-/-_-g; - $fvar =~ s-\.-_-g; - # for AVR, add PROGMEM here - print(OUTPUT "static const unsigned char data".$fvar."[] = {\n"); - print(OUTPUT "\t/* $file */\n\t"); - for($j = 0; $j < length($file); $j++) { - printf(OUTPUT "%#02x, ", unpack("C", substr($file, $j, 1))); - } - printf(OUTPUT "0,\n"); - - - $i = 0; - while(read(FILE, $data, 1)) { - if($i == 0) { - print(OUTPUT "\t"); - } - printf(OUTPUT "%#02x, ", unpack("C", $data)); - $i++; - if($i == 10) { - print(OUTPUT "\n"); - $i = 0; - } - } - print(OUTPUT "0};\n\n"); - close(FILE); - push(@fvars, $fvar); - push(@pfiles, $file); - } -} - -for($i = 0; $i < @fvars; $i++) { - $file = $pfiles[$i]; - $fvar = $fvars[$i]; - - if($i == 0) { - $prevfile = "NULL"; - } else { - $prevfile = "file" . $fvars[$i - 1]; - } - print(OUTPUT "const struct httpd_fsdata_file file".$fvar."[] = {{$prevfile, data$fvar, "); - print(OUTPUT "data$fvar + ". (length($file) + 1) .", "); - print(OUTPUT "sizeof(data$fvar) - ". (length($file) + 1) ."}};\n\n"); -} - -print(OUTPUT "#define HTTPD_FS_ROOT file$fvars[$i - 1]\n\n"); -print(OUTPUT "#define HTTPD_FS_NUMFILES $i\n"); diff --git a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/makestrings b/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/makestrings deleted file mode 100644 index 8a13c6d29..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/makestrings +++ /dev/null @@ -1,40 +0,0 @@ -#!/usr/bin/perl - - -sub stringify { - my $name = shift(@_); - open(OUTPUTC, "> $name.c"); - open(OUTPUTH, "> $name.h"); - - open(FILE, "$name"); - - while() { - if(/(.+) "(.+)"/) { - $var = $1; - $data = $2; - - $datan = $data; - $datan =~ s/\\r/\r/g; - $datan =~ s/\\n/\n/g; - $datan =~ s/\\01/\01/g; - $datan =~ s/\\0/\0/g; - - printf(OUTPUTC "const char $var\[%d] = \n", length($datan) + 1); - printf(OUTPUTC "/* \"$data\" */\n"); - printf(OUTPUTC "{"); - for($j = 0; $j < length($datan); $j++) { - printf(OUTPUTC "%#02x, ", unpack("C", substr($datan, $j, 1))); - } - printf(OUTPUTC "};\n"); - - printf(OUTPUTH "extern const char $var\[%d];\n", length($datan) + 1); - - } - } - close(OUTPUTC); - close(OUTPUTH); -} -stringify("http-strings"); - -exit 0; - diff --git a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/webserver.h b/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/webserver.h deleted file mode 100644 index 1acb290b8..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/apps/webserver/webserver.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2002, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack - * - * $Id: webserver.h,v 1.2 2006/06/11 21:46:38 adam Exp $ - * - */ -#ifndef __WEBSERVER_H__ -#define __WEBSERVER_H__ - -#include "httpd.h" - -typedef struct httpd_state uip_tcp_appstate_t; -/* UIP_APPCALL: the name of the application function. This function - must return void and take no arguments (i.e., C type "void - appfunc(void)"). */ -#ifndef UIP_APPCALL -#define UIP_APPCALL httpd_appcall -#endif - - -#endif /* __WEBSERVER_H__ */ diff --git a/Demo/Common/ethernet/uIP/uip-1.0/uip-1.0-changelog.txt b/Demo/Common/ethernet/uIP/uip-1.0/uip-1.0-changelog.txt deleted file mode 100644 index 7a97704ea..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/uip-1.0-changelog.txt +++ /dev/null @@ -1,98 +0,0 @@ -* A new API: protosockets that are similar to BSD sockets but does not - require any underlying multithreading system. - -* Very rudimentary IPv6 support - -* New application: DHCP client. Web server rewritten with protosockets. - -* Removed uIP zero-copy functionality in order to simplify uIP device - driver coding: outbound packets are now *always* stored in full in - the uip_buf buffer. - -* Checksum computation is now part of uip.c, but it still is possible - to implement them in assembly code by specifying a configuration - option. Checksum code now runs on architectures with 2-byte alignment. - -* Added TCP persistent timer. - -* Made all IP address representations use the new uip_ipaddr_ip - datatype for clarity. - -* Updated window behavior so that sending to a host with a small open - window works better now. - -* UDP API change: uip_udp_new() now takes port numbers in network byte - order like TCP functions. - -* Allow reception of packets when no IP address is configured to make - DHCP work. - -* Moved Ethernet address into main uIP module from ARP module. - -* Made constants explicit #defines and moved them out of the code - (header sizes, TCP options, TCP header length field). - -* If uip_len is less than that reported by the IP header, the packet - is discarded. If uip_len is greater than the length reported by the - IP header, uip_len is adjusted. - -* Moved header size definitions into header file. - -* Added uIP call for polling an application without triggering any - timer events. Removed redundant assignments of uip_len and uip_slen. - -* Removed compiler warning about icmp_input label being defined when - UIP_PINGADDRCONF was not used. - -* Added UIP_APPDATA_SIZE macro that holds the available buffer size - for user data. - -* Added uip_udp_bind() call. - -* Moved checksum code into main uIP module. - -* Switched the TCP, UDP and IP header structures to be structs rather - than typedefs. - -* Prefixed TCP state names with UIP_ to avoid name space - contamination. - -* Changed declarations of uip_appdatap and friends to void * to avoid - explicit typecasts. - -* Bugfixes - - o TCP: Fixed bug with high byte of peer window size. - - o TCP: Fixed bug that in some cases prevented concurrent reception and - transmission of TCP data. - - o TCP: uip_connect() didn't correctly calculate age of TIME_WAIT - connections. - - o TCP: Array index for uip_conns[] array was out of bounds in - comparison. Comparison changed to make index within bounds. - - o TCP: if the remote host crashes and tries to reestablish an old - connection, uIP should respond with an ACK with the correct - sequence and acknowledgment numbers, to which the remote host - should respond with an ACK. uIP did not respond with the correct - ACK. - - o TCP: Fixed check for SYNACK segment: now checks only relevant TCP - control flags and discards flags reserved for future expansion. - - o TCP: Fixed bug where uIP did not inform application that a connection - had been aborted during an active open. - - o TCP: FIN segment was accepted even though application had stopped - incoming data with uip_stop(). - - o TCP: A FINACK segment would not always correctly acknowledge data. - - o UDP: checksums are now calculated after all fields have been - filled in. - - o UDP: network byte order on lastport in uip_udp_new(). - - o IP: memset() bugs in IP fragment reassembly code fixed. diff --git a/Demo/Common/ethernet/uIP/uip-1.0/uip/Makefile.include b/Demo/Common/ethernet/uIP/uip-1.0/uip/Makefile.include deleted file mode 100644 index 43ba24744..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/uip/Makefile.include +++ /dev/null @@ -1,47 +0,0 @@ - - -ifdef APPS - APPDIRS = $(foreach APP, $(APPS), ../apps/$(APP)) - -include $(foreach APP, $(APPS), ../apps/$(APP)/Makefile.$(APP)) - CFLAGS += $(addprefix -I../apps/,$(APPS)) -endif - -ifndef CCDEP - CCDEP = $(CC) -endif -ifndef CCDEPCFLAGS - CCDEPCFLAGS = $(CFLAGS) -endif -ifndef OBJECTDIR - OBJECTDIR = obj -endif - -ifeq (${wildcard $(OBJECTDIR)},) - DUMMY := ${shell mkdir $(OBJECTDIR)} -endif - - -vpath %.c . ../uip ../lib $(APPDIRS) - -$(OBJECTDIR)/%.o: %.c - $(CC) $(CFLAGS) -c $< -o $@ - -$(OBJECTDIR)/%.d: %.c - @set -e; rm -f $@; \ - $(CCDEP) -MM $(CCDEPCFLAGS) $< > $@.$$$$; \ - sed 's,\($*\)\.o[ :]*,$(OBJECTDIR)/\1.o $@ : ,g' < $@.$$$$ > $@; \ - rm -f $@.$$$$ - -UIP_SOURCES=uip.c uip_arp.c uiplib.c psock.c timer.c uip-neighbor.c - - -ifneq ($(MAKECMDGOALS),clean) --include $(addprefix $(OBJECTDIR)/,$(UIP_SOURCES:.c=.d) \ - $(APP_SOURCES:.c=.d)) -endif - -uip.a: ${addprefix $(OBJECTDIR)/, $(UIP_SOURCES:.c=.o)} - $(AR) rcf $@ $^ - -apps.a: ${addprefix $(OBJECTDIR)/, $(APP_SOURCES:.c=.o)} - $(AR) rcf $@ $^ diff --git a/Demo/Common/ethernet/uIP/uip-1.0/uip/clock.h b/Demo/Common/ethernet/uIP/uip-1.0/uip/clock.h deleted file mode 100644 index dae68745f..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/uip/clock.h +++ /dev/null @@ -1,88 +0,0 @@ -/** - * \defgroup clock Clock interface - * - * The clock interface is the interface between the \ref timer "timer library" - * and the platform specific clock functionality. The clock - * interface must be implemented for each platform that uses the \ref - * timer "timer library". - * - * The clock interface does only one this: it measures time. The clock - * interface provides a macro, CLOCK_SECOND, which corresponds to one - * second of system time. - * - * \sa \ref timer "Timer library" - * - * @{ - */ - -/* - * Copyright (c) 2004, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack - * - * Author: Adam Dunkels - * - * $Id: clock.h,v 1.3 2006/06/11 21:46:39 adam Exp $ - */ -#ifndef __CLOCK_H__ -#define __CLOCK_H__ - -#include "clock-arch.h" - -/** - * Initialize the clock library. - * - * This function initializes the clock library and should be called - * from the main() function of the system. - * - */ -void clock_init(void); - -/** - * Get the current clock time. - * - * This function returns the current system clock time. - * - * \return The current clock time, measured in system ticks. - */ -clock_time_t clock_time(void); - -/** - * A second, measured in system clock time. - * - * \hideinitializer - */ -#ifdef CLOCK_CONF_SECOND -#define CLOCK_SECOND CLOCK_CONF_SECOND -#else -#define CLOCK_SECOND (clock_time_t)32 -#endif - -#endif /* __CLOCK_H__ */ - -/** @} */ diff --git a/Demo/Common/ethernet/uIP/uip-1.0/uip/lc-addrlabels.h b/Demo/Common/ethernet/uIP/uip-1.0/uip/lc-addrlabels.h deleted file mode 100644 index 9dff03d09..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/uip/lc-addrlabels.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright (c) 2004-2005, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack - * - * Author: Adam Dunkels - * - * $Id: lc-addrlabels.h,v 1.3 2006/06/12 08:00:30 adam Exp $ - */ - -/** - * \addtogroup lc - * @{ - */ - -/** - * \file - * Implementation of local continuations based on the "Labels as - * values" feature of gcc - * \author - * Adam Dunkels - * - * This implementation of local continuations is based on a special - * feature of the GCC C compiler called "labels as values". This - * feature allows assigning pointers with the address of the code - * corresponding to a particular C label. - * - * For more information, see the GCC documentation: - * http://gcc.gnu.org/onlinedocs/gcc/Labels-as-Values.html - * - * Thanks to dividuum for finding the nice local scope label - * implementation. - */ - -#ifndef __LC_ADDRLABELS_H__ -#define __LC_ADDRLABELS_H__ - -/** \hideinitializer */ -typedef void * lc_t; - -#define LC_INIT(s) s = NULL - - -#define LC_RESUME(s) \ - do { \ - if(s != NULL) { \ - goto *s; \ - } \ - } while(0) - -#define LC_SET(s) \ - do { ({ __label__ resume; resume: (s) = &&resume; }); }while(0) - -#define LC_END(s) - -#endif /* __LC_ADDRLABELS_H__ */ - -/** @} */ diff --git a/Demo/Common/ethernet/uIP/uip-1.0/uip/lc-switch.h b/Demo/Common/ethernet/uIP/uip-1.0/uip/lc-switch.h deleted file mode 100644 index 17c881161..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/uip/lc-switch.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright (c) 2004-2005, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack - * - * Author: Adam Dunkels - * - * $Id: lc-switch.h,v 1.2 2006/06/12 08:00:30 adam Exp $ - */ - -/** - * \addtogroup lc - * @{ - */ - -/** - * \file - * Implementation of local continuations based on switch() statment - * \author Adam Dunkels - * - * This implementation of local continuations uses the C switch() - * statement to resume execution of a function somewhere inside the - * function's body. The implementation is based on the fact that - * switch() statements are able to jump directly into the bodies of - * control structures such as if() or while() statmenets. - * - * This implementation borrows heavily from Simon Tatham's coroutines - * implementation in C: - * http://www.chiark.greenend.org.uk/~sgtatham/coroutines.html - */ - -#ifndef __LC_SWITCH_H__ -#define __LC_SWTICH_H__ - -/* WARNING! lc implementation using switch() does not work if an - LC_SET() is done within another switch() statement! */ - -/** \hideinitializer */ -typedef unsigned short lc_t; - -#define LC_INIT(s) s = 0; - -#define LC_RESUME(s) switch(s) { case 0: - -#define LC_SET(s) s = __LINE__; case __LINE__: - -#define LC_END(s) } - -#endif /* __LC_SWITCH_H__ */ - -/** @} */ diff --git a/Demo/Common/ethernet/uIP/uip-1.0/uip/lc.h b/Demo/Common/ethernet/uIP/uip-1.0/uip/lc.h deleted file mode 100644 index 3ad83cd0a..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/uip/lc.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * Copyright (c) 2004-2005, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack - * - * Author: Adam Dunkels - * - * $Id: lc.h,v 1.2 2006/06/12 08:00:30 adam Exp $ - */ - -/** - * \addtogroup pt - * @{ - */ - -/** - * \defgroup lc Local continuations - * @{ - * - * Local continuations form the basis for implementing protothreads. A - * local continuation can be set in a specific function to - * capture the state of the function. After a local continuation has - * been set can be resumed in order to restore the state of the - * function at the point where the local continuation was set. - * - * - */ - -/** - * \file lc.h - * Local continuations - * \author - * Adam Dunkels - * - */ - -#ifdef DOXYGEN -/** - * Initialize a local continuation. - * - * This operation initializes the local continuation, thereby - * unsetting any previously set continuation state. - * - * \hideinitializer - */ -#define LC_INIT(lc) - -/** - * Set a local continuation. - * - * The set operation saves the state of the function at the point - * where the operation is executed. As far as the set operation is - * concerned, the state of the function does not include the - * call-stack or local (automatic) variables, but only the program - * counter and such CPU registers that needs to be saved. - * - * \hideinitializer - */ -#define LC_SET(lc) - -/** - * Resume a local continuation. - * - * The resume operation resumes a previously set local continuation, thus - * restoring the state in which the function was when the local - * continuation was set. If the local continuation has not been - * previously set, the resume operation does nothing. - * - * \hideinitializer - */ -#define LC_RESUME(lc) - -/** - * Mark the end of local continuation usage. - * - * The end operation signifies that local continuations should not be - * used any more in the function. This operation is not needed for - * most implementations of local continuation, but is required by a - * few implementations. - * - * \hideinitializer - */ -#define LC_END(lc) - -/** - * \var typedef lc_t; - * - * The local continuation type. - * - * \hideinitializer - */ -#endif /* DOXYGEN */ - -#ifndef __LC_H__ -#define __LC_H__ - -#ifdef LC_CONF_INCLUDE -#include LC_CONF_INCLUDE -#else -#include "lc-switch.h" -#endif /* LC_CONF_INCLUDE */ - -#endif /* __LC_H__ */ - -/** @} */ -/** @} */ diff --git a/Demo/Common/ethernet/uIP/uip-1.0/uip/psock.c b/Demo/Common/ethernet/uIP/uip-1.0/uip/psock.c deleted file mode 100644 index 6b5920f78..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/uip/psock.c +++ /dev/null @@ -1,338 +0,0 @@ -/* - * Copyright (c) 2004, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack - * - * Author: Adam Dunkels - * - * $Id: psock.c,v 1.2 2006/06/12 08:00:30 adam Exp $ - */ - -#include -#include - -#include "uipopt.h" -#include "psock.h" -#include "uip.h" - -#define STATE_NONE 0 -#define STATE_ACKED 1 -#define STATE_READ 2 -#define STATE_BLOCKED_NEWDATA 3 -#define STATE_BLOCKED_CLOSE 4 -#define STATE_BLOCKED_SEND 5 -#define STATE_DATA_SENT 6 - -/* - * Return value of the buffering functions that indicates that a - * buffer was not filled by incoming data. - * - */ -#define BUF_NOT_FULL 0 -#define BUF_NOT_FOUND 0 - -/* - * Return value of the buffering functions that indicates that a - * buffer was completely filled by incoming data. - * - */ -#define BUF_FULL 1 - -/* - * Return value of the buffering functions that indicates that an - * end-marker byte was found. - * - */ -#define BUF_FOUND 2 - -/*---------------------------------------------------------------------------*/ -static void -buf_setup(struct psock_buf *buf, - u8_t *bufptr, u16_t bufsize) -{ - buf->ptr = bufptr; - buf->left = bufsize; -} -/*---------------------------------------------------------------------------*/ -static u8_t -buf_bufdata(struct psock_buf *buf, u16_t len, - u8_t **dataptr, u16_t *datalen) -{ - if(*datalen < buf->left) { - memcpy(buf->ptr, *dataptr, *datalen); - buf->ptr += *datalen; - buf->left -= *datalen; - *dataptr += *datalen; - *datalen = 0; - return BUF_NOT_FULL; - } else if(*datalen == buf->left) { - memcpy(buf->ptr, *dataptr, *datalen); - buf->ptr += *datalen; - buf->left = 0; - *dataptr += *datalen; - *datalen = 0; - return BUF_FULL; - } else { - memcpy(buf->ptr, *dataptr, buf->left); - buf->ptr += buf->left; - *datalen -= buf->left; - *dataptr += buf->left; - buf->left = 0; - return BUF_FULL; - } -} -/*---------------------------------------------------------------------------*/ -static u8_t -buf_bufto(register struct psock_buf *buf, u8_t endmarker, - register u8_t **dataptr, register u16_t *datalen) -{ - u8_t c; - while(buf->left > 0 && *datalen > 0) { - c = *buf->ptr = **dataptr; - ++*dataptr; - ++buf->ptr; - --*datalen; - --buf->left; - - if(c == endmarker) { - return BUF_FOUND; - } - } - - if(*datalen == 0) { - return BUF_NOT_FOUND; - } - - while(*datalen > 0) { - c = **dataptr; - --*datalen; - ++*dataptr; - - if(c == endmarker) { - return BUF_FOUND | BUF_FULL; - } - } - - return BUF_FULL; -} -/*---------------------------------------------------------------------------*/ -static char -send_data(register struct psock *s) -{ - if(s->state != STATE_DATA_SENT || uip_rexmit()) { - if(s->sendlen > uip_mss()) { - uip_send(s->sendptr, uip_mss()); - } else { - uip_send(s->sendptr, s->sendlen); - } - s->state = STATE_DATA_SENT; - return 1; - } - return 0; -} -/*---------------------------------------------------------------------------*/ -static char -data_acked(register struct psock *s) -{ - if(s->state == STATE_DATA_SENT && uip_acked()) { - if(s->sendlen > uip_mss()) { - s->sendlen -= uip_mss(); - s->sendptr += uip_mss(); - } else { - s->sendptr += s->sendlen; - s->sendlen = 0; - } - s->state = STATE_ACKED; - return 1; - } - return 0; -} -/*---------------------------------------------------------------------------*/ -PT_THREAD(psock_send(register struct psock *s, const char *buf, - unsigned int len)) -{ - PT_BEGIN(&s->psockpt); - - /* If there is no data to send, we exit immediately. */ - if(len == 0) { - PT_EXIT(&s->psockpt); - } - - /* Save the length of and a pointer to the data that is to be - sent. */ - s->sendptr = buf; - s->sendlen = len; - - s->state = STATE_NONE; - - /* We loop here until all data is sent. The s->sendlen variable is - updated by the data_sent() function. */ - while(s->sendlen > 0) { - - /* - * The condition for this PT_WAIT_UNTIL is a little tricky: the - * protothread will wait here until all data has been acknowledged - * (data_acked() returns true) and until all data has been sent - * (send_data() returns true). The two functions data_acked() and - * send_data() must be called in succession to ensure that all - * data is sent. Therefore the & operator is used instead of the - * && operator, which would cause only the data_acked() function - * to be called when it returns false. - */ - PT_WAIT_UNTIL(&s->psockpt, data_acked(s) & send_data(s)); - } - - s->state = STATE_NONE; - - PT_END(&s->psockpt); -} -/*---------------------------------------------------------------------------*/ -PT_THREAD(psock_generator_send(register struct psock *s, - unsigned short (*generate)(void *), void *arg)) -{ - PT_BEGIN(&s->psockpt); - - /* Ensure that there is a generator function to call. */ - if(generate == NULL) { - PT_EXIT(&s->psockpt); - } - - /* Call the generator function to generate the data in the - uip_appdata buffer. */ - s->sendlen = generate(arg); - s->sendptr = uip_appdata; - - s->state = STATE_NONE; - do { - /* Call the generator function again if we are called to perform a - retransmission. */ - if(uip_rexmit()) { - generate(arg); - } - /* Wait until all data is sent and acknowledged. */ - PT_WAIT_UNTIL(&s->psockpt, data_acked(s) & send_data(s)); - } while(s->sendlen > 0); - - s->state = STATE_NONE; - - PT_END(&s->psockpt); -} -/*---------------------------------------------------------------------------*/ -u16_t -psock_datalen(struct psock *psock) -{ - return psock->bufsize - psock->buf.left; -} -/*---------------------------------------------------------------------------*/ -char -psock_newdata(struct psock *s) -{ - if(s->readlen > 0) { - /* There is data in the uip_appdata buffer that has not yet been - read with the PSOCK_READ functions. */ - return 1; - } else if(s->state == STATE_READ) { - /* All data in uip_appdata buffer already consumed. */ - s->state = STATE_BLOCKED_NEWDATA; - return 0; - } else if(uip_newdata()) { - /* There is new data that has not been consumed. */ - return 1; - } else { - /* There is no new data. */ - return 0; - } -} -/*---------------------------------------------------------------------------*/ -PT_THREAD(psock_readto(register struct psock *psock, unsigned char c)) -{ - PT_BEGIN(&psock->psockpt); - - buf_setup(&psock->buf, psock->bufptr, psock->bufsize); - - /* XXX: Should add buf_checkmarker() before do{} loop, if - incoming data has been handled while waiting for a write. */ - - do { - if(psock->readlen == 0) { - PT_WAIT_UNTIL(&psock->psockpt, psock_newdata(psock)); - psock->state = STATE_READ; - psock->readptr = (u8_t *)uip_appdata; - psock->readlen = uip_datalen(); - } - } while((buf_bufto(&psock->buf, c, - &psock->readptr, - &psock->readlen) & BUF_FOUND) == 0); - - if(psock_datalen(psock) == 0) { - psock->state = STATE_NONE; - PT_RESTART(&psock->psockpt); - } - PT_END(&psock->psockpt); -} -/*---------------------------------------------------------------------------*/ -PT_THREAD(psock_readbuf(register struct psock *psock)) -{ - PT_BEGIN(&psock->psockpt); - - buf_setup(&psock->buf, psock->bufptr, psock->bufsize); - - /* XXX: Should add buf_checkmarker() before do{} loop, if - incoming data has been handled while waiting for a write. */ - - do { - if(psock->readlen == 0) { - PT_WAIT_UNTIL(&psock->psockpt, psock_newdata(psock)); - printf("Waited for newdata\n"); - psock->state = STATE_READ; - psock->readptr = (u8_t *)uip_appdata; - psock->readlen = uip_datalen(); - } - } while(buf_bufdata(&psock->buf, psock->bufsize, - &psock->readptr, - &psock->readlen) != BUF_FULL); - - if(psock_datalen(psock) == 0) { - psock->state = STATE_NONE; - PT_RESTART(&psock->psockpt); - } - PT_END(&psock->psockpt); -} -/*---------------------------------------------------------------------------*/ -void -psock_init(register struct psock *psock, char *buffer, unsigned int buffersize) -{ - psock->state = STATE_NONE; - psock->readlen = 0; - psock->bufptr = buffer; - psock->bufsize = buffersize; - buf_setup(&psock->buf, buffer, buffersize); - PT_INIT(&psock->pt); - PT_INIT(&psock->psockpt); -} -/*---------------------------------------------------------------------------*/ diff --git a/Demo/Common/ethernet/uIP/uip-1.0/uip/psock.h b/Demo/Common/ethernet/uIP/uip-1.0/uip/psock.h deleted file mode 100644 index 8d4125878..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/uip/psock.h +++ /dev/null @@ -1,380 +0,0 @@ -/* - * Copyright (c) 2004, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack - * - * Author: Adam Dunkels - * - * $Id: psock.h,v 1.3 2006/06/12 08:00:30 adam Exp $ - */ - -/** - * \defgroup psock Protosockets library - * @{ - * - * The protosocket library provides an interface to the uIP stack that is - * similar to the traditional BSD socket interface. Unlike programs - * written for the ordinary uIP event-driven interface, programs - * written with the protosocket library are executed in a sequential - * fashion and does not have to be implemented as explicit state - * machines. - * - * Protosockets only work with TCP connections. - * - * The protosocket library uses \ref pt protothreads to provide - * sequential control flow. This makes the protosockets lightweight in - * terms of memory, but also means that protosockets inherits the - * functional limitations of protothreads. Each protosocket lives only - * within a single function. Automatic variables (stack variables) are - * not retained across a protosocket library function call. - * - * \note Because the protosocket library uses protothreads, local - * variables will not always be saved across a call to a protosocket - * library function. It is therefore advised that local variables are - * used with extreme care. - * - * The protosocket library provides functions for sending data without - * having to deal with retransmissions and acknowledgements, as well - * as functions for reading data without having to deal with data - * being split across more than one TCP segment. - * - * Because each protosocket runs as a protothread, the protosocket has to be - * started with a call to PSOCK_BEGIN() at the start of the function - * in which the protosocket is used. Similarly, the protosocket protothread can - * be terminated by a call to PSOCK_EXIT(). - * - */ - -/** - * \file - * Protosocket library header file - * \author - * Adam Dunkels - * - */ - -#ifndef __PSOCK_H__ -#define __PSOCK_H__ - -#include "uipopt.h" -#include "pt.h" - - /* - * The structure that holds the state of a buffer. - * - * This structure holds the state of a uIP buffer. The structure has - * no user-visible elements, but is used through the functions - * provided by the library. - * - */ -struct psock_buf { - u8_t *ptr; - unsigned short left; -}; - -/** - * The representation of a protosocket. - * - * The protosocket structrure is an opaque structure with no user-visible - * elements. - */ -struct psock { - struct pt pt, psockpt; /* Protothreads - one that's using the psock - functions, and one that runs inside the - psock functions. */ - const u8_t *sendptr; /* Pointer to the next data to be sent. */ - u8_t *readptr; /* Pointer to the next data to be read. */ - - char *bufptr; /* Pointer to the buffer used for buffering - incoming data. */ - - u16_t sendlen; /* The number of bytes left to be sent. */ - u16_t readlen; /* The number of bytes left to be read. */ - - struct psock_buf buf; /* The structure holding the state of the - input buffer. */ - unsigned int bufsize; /* The size of the input buffer. */ - - unsigned char state; /* The state of the protosocket. */ -}; - -void psock_init(struct psock *psock, char *buffer, unsigned int buffersize); -/** - * Initialize a protosocket. - * - * This macro initializes a protosocket and must be called before the - * protosocket is used. The initialization also specifies the input buffer - * for the protosocket. - * - * \param psock (struct psock *) A pointer to the protosocket to be - * initialized - * - * \param buffer (char *) A pointer to the input buffer for the - * protosocket. - * - * \param buffersize (unsigned int) The size of the input buffer. - * - * \hideinitializer - */ -#define PSOCK_INIT(psock, buffer, buffersize) \ - psock_init(psock, buffer, buffersize) - -/** - * Start the protosocket protothread in a function. - * - * This macro starts the protothread associated with the protosocket and - * must come before other protosocket calls in the function it is used. - * - * \param psock (struct psock *) A pointer to the protosocket to be - * started. - * - * \hideinitializer - */ -#define PSOCK_BEGIN(psock) PT_BEGIN(&((psock)->pt)) - -PT_THREAD(psock_send(struct psock *psock, const char *buf, unsigned int len)); -/** - * Send data. - * - * This macro sends data over a protosocket. The protosocket protothread blocks - * until all data has been sent and is known to have been received by - * the remote end of the TCP connection. - * - * \param psock (struct psock *) A pointer to the protosocket over which - * data is to be sent. - * - * \param data (char *) A pointer to the data that is to be sent. - * - * \param datalen (unsigned int) The length of the data that is to be - * sent. - * - * \hideinitializer - */ -#define PSOCK_SEND(psock, data, datalen) \ - PT_WAIT_THREAD(&((psock)->pt), psock_send(psock, data, datalen)) - -/** - * \brief Send a null-terminated string. - * \param psock Pointer to the protosocket. - * \param str The string to be sent. - * - * This function sends a null-terminated string over the - * protosocket. - * - * \hideinitializer - */ -#define PSOCK_SEND_STR(psock, str) \ - PT_WAIT_THREAD(&((psock)->pt), psock_send(psock, str, strlen(str))) - -PT_THREAD(psock_generator_send(struct psock *psock, - unsigned short (*f)(void *), void *arg)); - -/** - * \brief Generate data with a function and send it - * \param psock Pointer to the protosocket. - * \param generator Pointer to the generator function - * \param arg Argument to the generator function - * - * This function generates data and sends it over the - * protosocket. This can be used to dynamically generate - * data for a transmission, instead of generating the data - * in a buffer beforehand. This function reduces the need for - * buffer memory. The generator function is implemented by - * the application, and a pointer to the function is given - * as an argument with the call to PSOCK_GENERATOR_SEND(). - * - * The generator function should place the generated data - * directly in the uip_appdata buffer, and return the - * length of the generated data. The generator function is - * called by the protosocket layer when the data first is - * sent, and once for every retransmission that is needed. - * - * \hideinitializer - */ -#define PSOCK_GENERATOR_SEND(psock, generator, arg) \ - PT_WAIT_THREAD(&((psock)->pt), \ - psock_generator_send(psock, generator, arg)) - - -/** - * Close a protosocket. - * - * This macro closes a protosocket and can only be called from within the - * protothread in which the protosocket lives. - * - * \param psock (struct psock *) A pointer to the protosocket that is to - * be closed. - * - * \hideinitializer - */ -#define PSOCK_CLOSE(psock) uip_close() - -PT_THREAD(psock_readbuf(struct psock *psock)); -/** - * Read data until the buffer is full. - * - * This macro will block waiting for data and read the data into the - * input buffer specified with the call to PSOCK_INIT(). Data is read - * until the buffer is full.. - * - * \param psock (struct psock *) A pointer to the protosocket from which - * data should be read. - * - * \hideinitializer - */ -#define PSOCK_READBUF(psock) \ - PT_WAIT_THREAD(&((psock)->pt), psock_readbuf(psock)) - -PT_THREAD(psock_readto(struct psock *psock, unsigned char c)); -/** - * Read data up to a specified character. - * - * This macro will block waiting for data and read the data into the - * input buffer specified with the call to PSOCK_INIT(). Data is only - * read until the specifieed character appears in the data stream. - * - * \param psock (struct psock *) A pointer to the protosocket from which - * data should be read. - * - * \param c (char) The character at which to stop reading. - * - * \hideinitializer - */ -#define PSOCK_READTO(psock, c) \ - PT_WAIT_THREAD(&((psock)->pt), psock_readto(psock, c)) - -/** - * The length of the data that was previously read. - * - * This macro returns the length of the data that was previously read - * using PSOCK_READTO() or PSOCK_READ(). - * - * \param psock (struct psock *) A pointer to the protosocket holding the data. - * - * \hideinitializer - */ -#define PSOCK_DATALEN(psock) psock_datalen(psock) - -u16_t psock_datalen(struct psock *psock); - -/** - * Exit the protosocket's protothread. - * - * This macro terminates the protothread of the protosocket and should - * almost always be used in conjunction with PSOCK_CLOSE(). - * - * \sa PSOCK_CLOSE_EXIT() - * - * \param psock (struct psock *) A pointer to the protosocket. - * - * \hideinitializer - */ -#define PSOCK_EXIT(psock) PT_EXIT(&((psock)->pt)) - -/** - * Close a protosocket and exit the protosocket's protothread. - * - * This macro closes a protosocket and exits the protosocket's protothread. - * - * \param psock (struct psock *) A pointer to the protosocket. - * - * \hideinitializer - */ -#define PSOCK_CLOSE_EXIT(psock) \ - do { \ - PSOCK_CLOSE(psock); \ - PSOCK_EXIT(psock); \ - } while(0) - -/** - * Declare the end of a protosocket's protothread. - * - * This macro is used for declaring that the protosocket's protothread - * ends. It must always be used together with a matching PSOCK_BEGIN() - * macro. - * - * \param psock (struct psock *) A pointer to the protosocket. - * - * \hideinitializer - */ -#define PSOCK_END(psock) PT_END(&((psock)->pt)) - -char psock_newdata(struct psock *s); - -/** - * Check if new data has arrived on a protosocket. - * - * This macro is used in conjunction with the PSOCK_WAIT_UNTIL() - * macro to check if data has arrived on a protosocket. - * - * \param psock (struct psock *) A pointer to the protosocket. - * - * \hideinitializer - */ -#define PSOCK_NEWDATA(psock) psock_newdata(psock) - -/** - * Wait until a condition is true. - * - * This macro blocks the protothread until the specified condition is - * true. The macro PSOCK_NEWDATA() can be used to check if new data - * arrives when the protosocket is waiting. - * - * Typically, this macro is used as follows: - * - \code - PT_THREAD(thread(struct psock *s, struct timer *t)) - { - PSOCK_BEGIN(s); - - PSOCK_WAIT_UNTIL(s, PSOCK_NEWADATA(s) || timer_expired(t)); - - if(PSOCK_NEWDATA(s)) { - PSOCK_READTO(s, '\n'); - } else { - handle_timed_out(s); - } - - PSOCK_END(s); - } - \endcode - * - * \param psock (struct psock *) A pointer to the protosocket. - * \param condition The condition to wait for. - * - * \hideinitializer - */ -#define PSOCK_WAIT_UNTIL(psock, condition) \ - PT_WAIT_UNTIL(&((psock)->pt), (condition)); - -#define PSOCK_WAIT_THREAD(psock, condition) \ - PT_WAIT_THREAD(&((psock)->pt), (condition)) - -#endif /* __PSOCK_H__ */ - -/** @} */ diff --git a/Demo/Common/ethernet/uIP/uip-1.0/uip/pt.h b/Demo/Common/ethernet/uIP/uip-1.0/uip/pt.h deleted file mode 100644 index 00ddd4429..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/uip/pt.h +++ /dev/null @@ -1,323 +0,0 @@ -/* - * Copyright (c) 2004-2005, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack - * - * Author: Adam Dunkels - * - * $Id: pt.h,v 1.2 2006/06/12 08:00:30 adam Exp $ - */ - -/** - * \addtogroup pt - * @{ - */ - -/** - * \file - * Protothreads implementation. - * \author - * Adam Dunkels - * - */ - -#ifndef __PT_H__ -#define __PT_H__ - -#include "lc.h" - -struct pt { - lc_t lc; -}; - -#define PT_WAITING 0 -#define PT_EXITED 1 -#define PT_ENDED 2 -#define PT_YIELDED 3 - -/** - * \name Initialization - * @{ - */ - -/** - * Initialize a protothread. - * - * Initializes a protothread. Initialization must be done prior to - * starting to execute the protothread. - * - * \param pt A pointer to the protothread control structure. - * - * \sa PT_SPAWN() - * - * \hideinitializer - */ -#define PT_INIT(pt) LC_INIT((pt)->lc) - -/** @} */ - -/** - * \name Declaration and definition - * @{ - */ - -/** - * Declaration of a protothread. - * - * This macro is used to declare a protothread. All protothreads must - * be declared with this macro. - * - * \param name_args The name and arguments of the C function - * implementing the protothread. - * - * \hideinitializer - */ -#define PT_THREAD(name_args) char name_args - -/** - * Declare the start of a protothread inside the C function - * implementing the protothread. - * - * This macro is used to declare the starting point of a - * protothread. It should be placed at the start of the function in - * which the protothread runs. All C statements above the PT_BEGIN() - * invokation will be executed each time the protothread is scheduled. - * - * \param pt A pointer to the protothread control structure. - * - * \hideinitializer - */ -#define PT_BEGIN(pt) { char PT_YIELD_FLAG = 1; LC_RESUME((pt)->lc) - -/** - * Declare the end of a protothread. - * - * This macro is used for declaring that a protothread ends. It must - * always be used together with a matching PT_BEGIN() macro. - * - * \param pt A pointer to the protothread control structure. - * - * \hideinitializer - */ -#define PT_END(pt) LC_END((pt)->lc); PT_YIELD_FLAG = 0; \ - PT_INIT(pt); return PT_ENDED; } - -/** @} */ - -/** - * \name Blocked wait - * @{ - */ - -/** - * Block and wait until condition is true. - * - * This macro blocks the protothread until the specified condition is - * true. - * - * \param pt A pointer to the protothread control structure. - * \param condition The condition. - * - * \hideinitializer - */ -#define PT_WAIT_UNTIL(pt, condition) \ - do { \ - LC_SET((pt)->lc); \ - if(!(condition)) { \ - return PT_WAITING; \ - } \ - } while(0) - -/** - * Block and wait while condition is true. - * - * This function blocks and waits while condition is true. See - * PT_WAIT_UNTIL(). - * - * \param pt A pointer to the protothread control structure. - * \param cond The condition. - * - * \hideinitializer - */ -#define PT_WAIT_WHILE(pt, cond) PT_WAIT_UNTIL((pt), !(cond)) - -/** @} */ - -/** - * \name Hierarchical protothreads - * @{ - */ - -/** - * Block and wait until a child protothread completes. - * - * This macro schedules a child protothread. The current protothread - * will block until the child protothread completes. - * - * \note The child protothread must be manually initialized with the - * PT_INIT() function before this function is used. - * - * \param pt A pointer to the protothread control structure. - * \param thread The child protothread with arguments - * - * \sa PT_SPAWN() - * - * \hideinitializer - */ -#define PT_WAIT_THREAD(pt, thread) PT_WAIT_WHILE((pt), PT_SCHEDULE(thread)) - -/** - * Spawn a child protothread and wait until it exits. - * - * This macro spawns a child protothread and waits until it exits. The - * macro can only be used within a protothread. - * - * \param pt A pointer to the protothread control structure. - * \param child A pointer to the child protothread's control structure. - * \param thread The child protothread with arguments - * - * \hideinitializer - */ -#define PT_SPAWN(pt, child, thread) \ - do { \ - PT_INIT((child)); \ - PT_WAIT_THREAD((pt), (thread)); \ - } while(0) - -/** @} */ - -/** - * \name Exiting and restarting - * @{ - */ - -/** - * Restart the protothread. - * - * This macro will block and cause the running protothread to restart - * its execution at the place of the PT_BEGIN() call. - * - * \param pt A pointer to the protothread control structure. - * - * \hideinitializer - */ -#define PT_RESTART(pt) \ - do { \ - PT_INIT(pt); \ - return PT_WAITING; \ - } while(0) - -/** - * Exit the protothread. - * - * This macro causes the protothread to exit. If the protothread was - * spawned by another protothread, the parent protothread will become - * unblocked and can continue to run. - * - * \param pt A pointer to the protothread control structure. - * - * \hideinitializer - */ -#define PT_EXIT(pt) \ - do { \ - PT_INIT(pt); \ - return PT_EXITED; \ - } while(0) - -/** @} */ - -/** - * \name Calling a protothread - * @{ - */ - -/** - * Schedule a protothread. - * - * This function shedules a protothread. The return value of the - * function is non-zero if the protothread is running or zero if the - * protothread has exited. - * - * \param f The call to the C function implementing the protothread to - * be scheduled - * - * \hideinitializer - */ -#define PT_SCHEDULE(f) ((f) == PT_WAITING) - -/** @} */ - -/** - * \name Yielding from a protothread - * @{ - */ - -/** - * Yield from the current protothread. - * - * This function will yield the protothread, thereby allowing other - * processing to take place in the system. - * - * \param pt A pointer to the protothread control structure. - * - * \hideinitializer - */ -#define PT_YIELD(pt) \ - do { \ - PT_YIELD_FLAG = 0; \ - LC_SET((pt)->lc); \ - if(PT_YIELD_FLAG == 0) { \ - return PT_YIELDED; \ - } \ - } while(0) - -/** - * \brief Yield from the protothread until a condition occurs. - * \param pt A pointer to the protothread control structure. - * \param cond The condition. - * - * This function will yield the protothread, until the - * specified condition evaluates to true. - * - * - * \hideinitializer - */ -#define PT_YIELD_UNTIL(pt, cond) \ - do { \ - PT_YIELD_FLAG = 0; \ - LC_SET((pt)->lc); \ - if((PT_YIELD_FLAG == 0) || !(cond)) { \ - return PT_YIELDED; \ - } \ - } while(0) - -/** @} */ - -#endif /* __PT_H__ */ - -/** @} */ diff --git a/Demo/Common/ethernet/uIP/uip-1.0/uip/timer.c b/Demo/Common/ethernet/uIP/uip-1.0/uip/timer.c deleted file mode 100644 index 8c270b233..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/uip/timer.c +++ /dev/null @@ -1,127 +0,0 @@ -/** - * \addtogroup timer - * @{ - */ - -/** - * \file - * Timer library implementation. - * \author - * Adam Dunkels - */ - -/* - * Copyright (c) 2004, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack - * - * Author: Adam Dunkels - * - * $Id: timer.c,v 1.2 2006/06/12 08:00:30 adam Exp $ - */ - -#include "clock.h" -#include "timer.h" - -/*---------------------------------------------------------------------------*/ -/** - * Set a timer. - * - * This function is used to set a timer for a time sometime in the - * future. The function timer_expired() will evaluate to true after - * the timer has expired. - * - * \param t A pointer to the timer - * \param interval The interval before the timer expires. - * - */ -void -timer_set(struct timer *t, clock_time_t interval) -{ - t->interval = interval; - t->start = clock_time(); -} -/*---------------------------------------------------------------------------*/ -/** - * Reset the timer with the same interval. - * - * This function resets the timer with the same interval that was - * given to the timer_set() function. The start point of the interval - * is the exact time that the timer last expired. Therefore, this - * function will cause the timer to be stable over time, unlike the - * timer_rester() function. - * - * \param t A pointer to the timer. - * - * \sa timer_restart() - */ -void -timer_reset(struct timer *t) -{ - t->start += t->interval; -} -/*---------------------------------------------------------------------------*/ -/** - * Restart the timer from the current point in time - * - * This function restarts a timer with the same interval that was - * given to the timer_set() function. The timer will start at the - * current time. - * - * \note A periodic timer will drift if this function is used to reset - * it. For preioric timers, use the timer_reset() function instead. - * - * \param t A pointer to the timer. - * - * \sa timer_reset() - */ -void -timer_restart(struct timer *t) -{ - t->start = clock_time(); -} -/*---------------------------------------------------------------------------*/ -/** - * Check if a timer has expired. - * - * This function tests if a timer has expired and returns true or - * false depending on its status. - * - * \param t A pointer to the timer - * - * \return Non-zero if the timer has expired, zero otherwise. - * - */ -int -timer_expired(struct timer *t) -{ - return (clock_time_t)(clock_time() - t->start) >= (clock_time_t)t->interval; -} -/*---------------------------------------------------------------------------*/ - -/** @} */ diff --git a/Demo/Common/ethernet/uIP/uip-1.0/uip/timer.h b/Demo/Common/ethernet/uIP/uip-1.0/uip/timer.h deleted file mode 100644 index e28e3ca5f..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/uip/timer.h +++ /dev/null @@ -1,86 +0,0 @@ -/** - * \defgroup timer Timer library - * - * The timer library provides functions for setting, resetting and - * restarting timers, and for checking if a timer has expired. An - * application must "manually" check if its timers have expired; this - * is not done automatically. - * - * A timer is declared as a \c struct \c timer and all access to the - * timer is made by a pointer to the declared timer. - * - * \note The timer library uses the \ref clock "Clock library" to - * measure time. Intervals should be specified in the format used by - * the clock library. - * - * @{ - */ - - -/** - * \file - * Timer library header file. - * \author - * Adam Dunkels - */ - -/* - * Copyright (c) 2004, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack - * - * Author: Adam Dunkels - * - * $Id: timer.h,v 1.3 2006/06/11 21:46:39 adam Exp $ - */ -#ifndef __TIMER_H__ -#define __TIMER_H__ - -#include "clock.h" - -/** - * A timer. - * - * This structure is used for declaring a timer. The timer must be set - * with timer_set() before it can be used. - * - * \hideinitializer - */ -struct timer { - clock_time_t start; - clock_time_t interval; -}; - -void timer_set(struct timer *t, clock_time_t interval); -void timer_reset(struct timer *t); -void timer_restart(struct timer *t); -int timer_expired(struct timer *t); - -#endif /* __TIMER_H__ */ - -/** @} */ diff --git a/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-fw.c b/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-fw.c deleted file mode 100644 index 33767401b..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-fw.c +++ /dev/null @@ -1,532 +0,0 @@ -/* - * Copyright (c) 2004, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack - * - * Author: Adam Dunkels - * - * $Id: uip-fw.c,v 1.2 2006/06/12 08:00:30 adam Exp $ - */ -/** - * \addtogroup uip - * @{ - */ - -/** - * \defgroup uipfw uIP packet forwarding - * @{ - * - */ - -/** - * \file - * uIP packet forwarding. - * \author Adam Dunkels - * - * This file implements a number of simple functions which do packet - * forwarding over multiple network interfaces with uIP. - * - */ - -#include "uip.h" -#include "uip_arch.h" -#include "uip-fw.h" - -#include /* for memcpy() */ - -/* - * The list of registered network interfaces. - */ -static struct uip_fw_netif *netifs = NULL; - -/* - * A pointer to the default network interface. - */ -static struct uip_fw_netif *defaultnetif = NULL; - -struct tcpip_hdr { - /* IP header. */ - u8_t vhl, - tos; - u16_t len, - ipid, - ipoffset; - u8_t ttl, - proto; - u16_t ipchksum; - u16_t srcipaddr[2], - destipaddr[2]; - - /* TCP header. */ - u16_t srcport, - destport; - u8_t seqno[4], - ackno[4], - tcpoffset, - flags, - wnd[2]; - u16_t tcpchksum; - u8_t urgp[2]; - u8_t optdata[4]; -}; - -struct icmpip_hdr { - /* IP header. */ - u8_t vhl, - tos, - len[2], - ipid[2], - ipoffset[2], - ttl, - proto; - u16_t ipchksum; - u16_t srcipaddr[2], - destipaddr[2]; - /* ICMP (echo) header. */ - u8_t type, icode; - u16_t icmpchksum; - u16_t id, seqno; - u8_t payload[1]; -}; - -/* ICMP ECHO. */ -#define ICMP_ECHO 8 - -/* ICMP TIME-EXCEEDED. */ -#define ICMP_TE 11 - -/* - * Pointer to the TCP/IP headers of the packet in the uip_buf buffer. - */ -#define BUF ((struct tcpip_hdr *)&uip_buf[UIP_LLH_LEN]) - -/* - * Pointer to the ICMP/IP headers of the packet in the uip_buf buffer. - */ -#define ICMPBUF ((struct icmpip_hdr *)&uip_buf[UIP_LLH_LEN]) - -/* - * Certain fields of an IP packet that are used for identifying - * duplicate packets. - */ -struct fwcache_entry { - u16_t timer; - - u16_t srcipaddr[2]; - u16_t destipaddr[2]; - u16_t ipid; - u8_t proto; - u8_t unused; - -#if notdef - u16_t payload[2]; -#endif - -#if UIP_REASSEMBLY > 0 - u16_t len, offset; -#endif -}; - -/* - * The number of packets to remember when looking for duplicates. - */ -#ifdef UIP_CONF_FWCACHE_SIZE -#define FWCACHE_SIZE UIP_CONF_FWCACHE_SIZE -#else -#define FWCACHE_SIZE 2 -#endif - - -/* - * A cache of packet header fields which are used for - * identifying duplicate packets. - */ -static struct fwcache_entry fwcache[FWCACHE_SIZE]; - -/** - * \internal - * The time that a packet cache is active. - */ -#define FW_TIME 20 - -/*------------------------------------------------------------------------------*/ -/** - * Initialize the uIP packet forwarding module. - */ -/*------------------------------------------------------------------------------*/ -void -uip_fw_init(void) -{ - struct uip_fw_netif *t; - defaultnetif = NULL; - while(netifs != NULL) { - t = netifs; - netifs = netifs->next; - t->next = NULL; - } -} -/*------------------------------------------------------------------------------*/ -/** - * \internal - * Check if an IP address is within the network defined by an IP - * address and a netmask. - * - * \param ipaddr The IP address to be checked. - * \param netipaddr The IP address of the network. - * \param netmask The netmask of the network. - * - * \return Non-zero if IP address is in network, zero otherwise. - */ -/*------------------------------------------------------------------------------*/ -static unsigned char -ipaddr_maskcmp(u16_t *ipaddr, u16_t *netipaddr, u16_t *netmask) -{ - return (ipaddr[0] & netmask [0]) == (netipaddr[0] & netmask[0]) && - (ipaddr[1] & netmask[1]) == (netipaddr[1] & netmask[1]); -} -/*------------------------------------------------------------------------------*/ -/** - * \internal - * Send out an ICMP TIME-EXCEEDED message. - * - * This function replaces the packet in the uip_buf buffer with the - * ICMP packet. - */ -/*------------------------------------------------------------------------------*/ -static void -time_exceeded(void) -{ - u16_t tmp16; - - /* We don't send out ICMP errors for ICMP messages. */ - if(ICMPBUF->proto == UIP_PROTO_ICMP) { - uip_len = 0; - return; - } - /* Copy fields from packet header into payload of this ICMP packet. */ - memcpy(&(ICMPBUF->payload[0]), ICMPBUF, 28); - - /* Set the ICMP type and code. */ - ICMPBUF->type = ICMP_TE; - ICMPBUF->icode = 0; - - /* Calculate the ICMP checksum. */ - ICMPBUF->icmpchksum = 0; - ICMPBUF->icmpchksum = ~uip_chksum((u16_t *)&(ICMPBUF->type), 36); - - /* Set the IP destination address to be the source address of the - original packet. */ - tmp16= BUF->destipaddr[0]; - BUF->destipaddr[0] = BUF->srcipaddr[0]; - BUF->srcipaddr[0] = tmp16; - tmp16 = BUF->destipaddr[1]; - BUF->destipaddr[1] = BUF->srcipaddr[1]; - BUF->srcipaddr[1] = tmp16; - - /* Set our IP address as the source address. */ - BUF->srcipaddr[0] = uip_hostaddr[0]; - BUF->srcipaddr[1] = uip_hostaddr[1]; - - /* The size of the ICMP time exceeded packet is 36 + the size of the - IP header (20) = 56. */ - uip_len = 56; - ICMPBUF->len[0] = 0; - ICMPBUF->len[1] = uip_len; - - /* Fill in the other fields in the IP header. */ - ICMPBUF->vhl = 0x45; - ICMPBUF->tos = 0; - ICMPBUF->ipoffset[0] = ICMPBUF->ipoffset[1] = 0; - ICMPBUF->ttl = UIP_TTL; - ICMPBUF->proto = UIP_PROTO_ICMP; - - /* Calculate IP checksum. */ - ICMPBUF->ipchksum = 0; - ICMPBUF->ipchksum = ~(uip_ipchksum()); - - -} -/*------------------------------------------------------------------------------*/ -/** - * \internal - * Register a packet in the forwarding cache so that it won't be - * forwarded again. - */ -/*------------------------------------------------------------------------------*/ -static void -fwcache_register(void) -{ - struct fwcache_entry *fw; - int i, oldest; - - oldest = FW_TIME; - fw = NULL; - - /* Find the oldest entry in the cache. */ - for(i = 0; i < FWCACHE_SIZE; ++i) { - if(fwcache[i].timer == 0) { - fw = &fwcache[i]; - break; - } else if(fwcache[i].timer <= oldest) { - fw = &fwcache[i]; - oldest = fwcache[i].timer; - } - } - - fw->timer = FW_TIME; - fw->ipid = BUF->ipid; - fw->srcipaddr[0] = BUF->srcipaddr[0]; - fw->srcipaddr[1] = BUF->srcipaddr[1]; - fw->destipaddr[0] = BUF->destipaddr[0]; - fw->destipaddr[1] = BUF->destipaddr[1]; - fw->proto = BUF->proto; -#if notdef - fw->payload[0] = BUF->srcport; - fw->payload[1] = BUF->destport; -#endif -#if UIP_REASSEMBLY > 0 - fw->len = BUF->len; - fw->offset = BUF->ipoffset; -#endif -} -/*------------------------------------------------------------------------------*/ -/** - * \internal - * Find a network interface for the IP packet in uip_buf. - */ -/*------------------------------------------------------------------------------*/ -static struct uip_fw_netif * -find_netif(void) -{ - struct uip_fw_netif *netif; - - /* Walk through every network interface to check for a match. */ - for(netif = netifs; netif != NULL; netif = netif->next) { - if(ipaddr_maskcmp(BUF->destipaddr, netif->ipaddr, - netif->netmask)) { - /* If there was a match, we break the loop. */ - return netif; - } - } - - /* If no matching netif was found, we use default netif. */ - return defaultnetif; -} -/*------------------------------------------------------------------------------*/ -/** - * Output an IP packet on the correct network interface. - * - * The IP packet should be present in the uip_buf buffer and its - * length in the global uip_len variable. - * - * \retval UIP_FW_ZEROLEN Indicates that a zero-length packet - * transmission was attempted and that no packet was sent. - * - * \retval UIP_FW_NOROUTE No suitable network interface could be found - * for the outbound packet, and the packet was not sent. - * - * \return The return value from the actual network interface output - * function is passed unmodified as a return value. - */ -/*------------------------------------------------------------------------------*/ -u8_t -uip_fw_output(void) -{ - struct uip_fw_netif *netif; - - if(uip_len == 0) { - return UIP_FW_ZEROLEN; - } - - fwcache_register(); - -#if UIP_BROADCAST - /* Link local broadcasts go out on all interfaces. */ - if(/*BUF->proto == UIP_PROTO_UDP &&*/ - BUF->destipaddr[0] == 0xffff && - BUF->destipaddr[1] == 0xffff) { - if(defaultnetif != NULL) { - defaultnetif->output(); - } - for(netif = netifs; netif != NULL; netif = netif->next) { - netif->output(); - } - return UIP_FW_OK; - } -#endif /* UIP_BROADCAST */ - - netif = find_netif(); - /* printf("uip_fw_output: netif %p ->output %p len %d\n", netif, - netif->output, - uip_len);*/ - - if(netif == NULL) { - return UIP_FW_NOROUTE; - } - /* If we now have found a suitable network interface, we call its - output function to send out the packet. */ - return netif->output(); -} -/*------------------------------------------------------------------------------*/ -/** - * Forward an IP packet in the uip_buf buffer. - * - * - * - * \return UIP_FW_FORWARDED if the packet was forwarded, UIP_FW_LOCAL if - * the packet should be processed locally. - */ -/*------------------------------------------------------------------------------*/ -u8_t -uip_fw_forward(void) -{ - struct fwcache_entry *fw; - - /* First check if the packet is destined for ourselves and return 0 - to indicate that the packet should be processed locally. */ - if(BUF->destipaddr[0] == uip_hostaddr[0] && - BUF->destipaddr[1] == uip_hostaddr[1]) { - return UIP_FW_LOCAL; - } - - /* If we use ping IP address configuration, and our IP address is - not yet configured, we should intercept all ICMP echo packets. */ -#if UIP_PINGADDRCONF - if((uip_hostaddr[0] | uip_hostaddr[1]) == 0 && - BUF->proto == UIP_PROTO_ICMP && - ICMPBUF->type == ICMP_ECHO) { - return UIP_FW_LOCAL; - } -#endif /* UIP_PINGADDRCONF */ - - /* Check if the packet is in the forwarding cache already, and if so - we drop it. */ - - for(fw = fwcache; fw < &fwcache[FWCACHE_SIZE]; ++fw) { - if(fw->timer != 0 && -#if UIP_REASSEMBLY > 0 - fw->len == BUF->len && - fw->offset == BUF->ipoffset && -#endif - fw->ipid == BUF->ipid && - fw->srcipaddr[0] == BUF->srcipaddr[0] && - fw->srcipaddr[1] == BUF->srcipaddr[1] && - fw->destipaddr[0] == BUF->destipaddr[0] && - fw->destipaddr[1] == BUF->destipaddr[1] && -#if notdef - fw->payload[0] == BUF->srcport && - fw->payload[1] == BUF->destport && -#endif - fw->proto == BUF->proto) { - /* Drop packet. */ - return UIP_FW_FORWARDED; - } - } - - /* If the TTL reaches zero we produce an ICMP time exceeded message - in the uip_buf buffer and forward that packet back to the sender - of the packet. */ - if(BUF->ttl <= 1) { - /* No time exceeded for broadcasts and multicasts! */ - if(BUF->destipaddr[0] == 0xffff && BUF->destipaddr[1] == 0xffff) { - return UIP_FW_LOCAL; - } - time_exceeded(); - } - - /* Decrement the TTL (time-to-live) value in the IP header */ - BUF->ttl = BUF->ttl - 1; - - /* Update the IP checksum. */ - if(BUF->ipchksum >= HTONS(0xffff - 0x0100)) { - BUF->ipchksum = BUF->ipchksum + HTONS(0x0100) + 1; - } else { - BUF->ipchksum = BUF->ipchksum + HTONS(0x0100); - } - - if(uip_len > 0) { - uip_appdata = &uip_buf[UIP_LLH_LEN + UIP_TCPIP_HLEN]; - uip_fw_output(); - } - -#if UIP_BROADCAST - if(BUF->destipaddr[0] == 0xffff && BUF->destipaddr[1] == 0xffff) { - return UIP_FW_LOCAL; - } -#endif /* UIP_BROADCAST */ - - /* Return non-zero to indicate that the packet was forwarded and that no - other processing should be made. */ - return UIP_FW_FORWARDED; -} -/*------------------------------------------------------------------------------*/ -/** - * Register a network interface with the forwarding module. - * - * \param netif A pointer to the network interface that is to be - * registered. - */ -/*------------------------------------------------------------------------------*/ -void -uip_fw_register(struct uip_fw_netif *netif) -{ - netif->next = netifs; - netifs = netif; -} -/*------------------------------------------------------------------------------*/ -/** - * Register a default network interface. - * - * All packets that don't go out on any of the other interfaces will - * be routed to the default interface. - * - * \param netif A pointer to the network interface that is to be - * registered. - */ -/*------------------------------------------------------------------------------*/ -void -uip_fw_default(struct uip_fw_netif *netif) -{ - defaultnetif = netif; -} -/*------------------------------------------------------------------------------*/ -/** - * Perform periodic processing. - */ -/*------------------------------------------------------------------------------*/ -void -uip_fw_periodic(void) -{ - struct fwcache_entry *fw; - for(fw = fwcache; fw < &fwcache[FWCACHE_SIZE]; ++fw) { - if(fw->timer > 0) { - --fw->timer; - } - } -} -/*------------------------------------------------------------------------------*/ diff --git a/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-fw.h b/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-fw.h deleted file mode 100644 index e854ecefe..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-fw.h +++ /dev/null @@ -1,176 +0,0 @@ -/** - * \addtogroup uipfw - * @{ - */ - -/** - * \file - * uIP packet forwarding header file. - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2004, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack - * - * Author: Adam Dunkels - * - * $Id: uip-fw.h,v 1.2 2006/06/12 08:00:30 adam Exp $ - */ -#ifndef __UIP_FW_H__ -#define __UIP_FW_H__ - -#include "uip.h" - -/** - * Representation of a uIP network interface. - */ -struct uip_fw_netif { - struct uip_fw_netif *next; /**< Pointer to the next interface when - linked in a list. */ - u16_t ipaddr[2]; /**< The IP address of this interface. */ - u16_t netmask[2]; /**< The netmask of the interface. */ - u8_t (* output)(void); - /**< A pointer to the function that - sends a packet. */ -}; - -/** - * Intantiating macro for a uIP network interface. - * - * Example: - \code - struct uip_fw_netif slipnetif = - {UIP_FW_NETIF(192,168,76,1, 255,255,255,0, slip_output)}; - \endcode - * \param ip1,ip2,ip3,ip4 The IP address of the network interface. - * - * \param nm1,nm2,nm3,nm4 The netmask of the network interface. - * - * \param outputfunc A pointer to the output function of the network interface. - * - * \hideinitializer - */ -#define UIP_FW_NETIF(ip1,ip2,ip3,ip4, nm1,nm2,nm3,nm4, outputfunc) \ - NULL, \ - {HTONS((ip1 << 8) | ip2), HTONS((ip3 << 8) | ip4)}, \ - {HTONS((nm1 << 8) | nm2), HTONS((nm3 << 8) | nm4)}, \ - outputfunc - -/** - * Set the IP address of a network interface. - * - * \param netif A pointer to the uip_fw_netif structure for the network interface. - * - * \param addr A pointer to an IP address. - * - * \hideinitializer - */ -#define uip_fw_setipaddr(netif, addr) \ - do { (netif)->ipaddr[0] = ((u16_t *)(addr))[0]; \ - (netif)->ipaddr[1] = ((u16_t *)(addr))[1]; } while(0) -/** - * Set the netmask of a network interface. - * - * \param netif A pointer to the uip_fw_netif structure for the network interface. - * - * \param addr A pointer to an IP address representing the netmask. - * - * \hideinitializer - */ -#define uip_fw_setnetmask(netif, addr) \ - do { (netif)->netmask[0] = ((u16_t *)(addr))[0]; \ - (netif)->netmask[1] = ((u16_t *)(addr))[1]; } while(0) - -void uip_fw_init(void); -u8_t uip_fw_forward(void); -u8_t uip_fw_output(void); -void uip_fw_register(struct uip_fw_netif *netif); -void uip_fw_default(struct uip_fw_netif *netif); -void uip_fw_periodic(void); - - -/** - * A non-error message that indicates that a packet should be - * processed locally. - * - * \hideinitializer - */ -#define UIP_FW_LOCAL 0 - -/** - * A non-error message that indicates that something went OK. - * - * \hideinitializer - */ -#define UIP_FW_OK 0 - -/** - * A non-error message that indicates that a packet was forwarded. - * - * \hideinitializer - */ -#define UIP_FW_FORWARDED 1 - -/** - * A non-error message that indicates that a zero-length packet - * transmission was attempted, and that no packet was sent. - * - * \hideinitializer - */ -#define UIP_FW_ZEROLEN 2 - -/** - * An error message that indicates that a packet that was too large - * for the outbound network interface was detected. - * - * \hideinitializer - */ -#define UIP_FW_TOOLARGE 3 - -/** - * An error message that indicates that no suitable interface could be - * found for an outbound packet. - * - * \hideinitializer - */ -#define UIP_FW_NOROUTE 4 - -/** - * An error message that indicates that a packet that should be - * forwarded or output was dropped. - * - * \hideinitializer - */ -#define UIP_FW_DROPPED 5 - - -#endif /* __UIP_FW_H__ */ - -/** @} */ diff --git a/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-neighbor.c b/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-neighbor.c deleted file mode 100644 index 6920960f6..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-neighbor.c +++ /dev/null @@ -1,159 +0,0 @@ -/* - * Copyright (c) 2006, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack - * - * $Id: uip-neighbor.c,v 1.2 2006/06/12 08:00:30 adam Exp $ - */ - -/** - * \file - * Database of link-local neighbors, used by IPv6 code and - * to be used by a future ARP code rewrite. - * \author - * Adam Dunkels - */ - -#include "uip-neighbor.h" - -#include -#include - -#define MAX_TIME 128 - -#ifdef UIP_NEIGHBOR_CONF_ENTRIES -#define ENTRIES UIP_NEIGHBOR_CONF_ENTRIES -#else /* UIP_NEIGHBOR_CONF_ENTRIES */ -#define ENTRIES 8 -#endif /* UIP_NEIGHBOR_CONF_ENTRIES */ - -struct neighbor_entry { - uip_ipaddr_t ipaddr; - struct uip_neighbor_addr addr; - u8_t time; -}; -static struct neighbor_entry entries[ENTRIES]; - -/*---------------------------------------------------------------------------*/ -void -uip_neighbor_init(void) -{ - int i; - - for(i = 0; i < ENTRIES; ++i) { - entries[i].time = MAX_TIME; - } -} -/*---------------------------------------------------------------------------*/ -void -uip_neighbor_periodic(void) -{ - int i; - - for(i = 0; i < ENTRIES; ++i) { - if(entries[i].time < MAX_TIME) { - entries[i].time++; - } - } -} -/*---------------------------------------------------------------------------*/ -void -uip_neighbor_add(uip_ipaddr_t ipaddr, struct uip_neighbor_addr *addr) -{ - int i, oldest; - u8_t oldest_time; - - printf("Adding neighbor with link address %02x:%02x:%02x:%02x:%02x:%02x\n", - addr->addr.addr[0], addr->addr.addr[1], addr->addr.addr[2], addr->addr.addr[3], - addr->addr.addr[4], addr->addr.addr[5]); - - /* Find the first unused entry or the oldest used entry. */ - oldest_time = 0; - oldest = 0; - for(i = 0; i < ENTRIES; ++i) { - if(entries[i].time == MAX_TIME) { - oldest = i; - break; - } - if(uip_ipaddr_cmp(entries[i].ipaddr, addr)) { - oldest = i; - break; - } - if(entries[i].time > oldest_time) { - oldest = i; - oldest_time = entries[i].time; - } - } - - /* Use the oldest or first free entry (either pointed to by the - "oldest" variable). */ - entries[oldest].time = 0; - uip_ipaddr_copy(entries[oldest].ipaddr, ipaddr); - memcpy(&entries[oldest].addr, addr, sizeof(struct uip_neighbor_addr)); -} -/*---------------------------------------------------------------------------*/ -static struct neighbor_entry * -find_entry(uip_ipaddr_t ipaddr) -{ - int i; - - for(i = 0; i < ENTRIES; ++i) { - if(uip_ipaddr_cmp(entries[i].ipaddr, ipaddr)) { - return &entries[i]; - } - } - return NULL; -} -/*---------------------------------------------------------------------------*/ -void -uip_neighbor_update(uip_ipaddr_t ipaddr) -{ - struct neighbor_entry *e; - - e = find_entry(ipaddr); - if(e != NULL) { - e->time = 0; - } -} -/*---------------------------------------------------------------------------*/ -struct uip_neighbor_addr * -uip_neighbor_lookup(uip_ipaddr_t ipaddr) -{ - struct neighbor_entry *e; - - e = find_entry(ipaddr); - if(e != NULL) { - /* printf("Lookup neighbor with link address %02x:%02x:%02x:%02x:%02x:%02x\n", - e->addr.addr.addr[0], e->addr.addr.addr[1], e->addr.addr.addr[2], e->addr.addr.addr[3], - e->addr.addr.addr[4], e->addr.addr.addr[5]);*/ - - return &e->addr; - } - return NULL; -} -/*---------------------------------------------------------------------------*/ diff --git a/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-neighbor.h b/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-neighbor.h deleted file mode 100644 index aca096f2c..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-neighbor.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2006, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack - * - * $Id: uip-neighbor.h,v 1.2 2006/06/12 08:00:30 adam Exp $ - */ - -/** - * \file - * Header file for database of link-local neighbors, used by - * IPv6 code and to be used by future ARP code. - * \author - * Adam Dunkels - */ - -#ifndef __UIP_NEIGHBOR_H__ -#define __UIP_NEIGHBOR_H__ - -#include "uip.h" - -struct uip_neighbor_addr { -#if UIP_NEIGHBOR_CONF_ADDRTYPE - UIP_NEIGHBOR_CONF_ADDRTYPE addr; -#else - struct uip_eth_addr addr; -#endif -}; - -void uip_neighbor_init(void); -void uip_neighbor_add(uip_ipaddr_t ipaddr, struct uip_neighbor_addr *addr); -void uip_neighbor_update(uip_ipaddr_t ipaddr); -struct uip_neighbor_addr *uip_neighbor_lookup(uip_ipaddr_t ipaddr); -void uip_neighbor_periodic(void); - -#endif /* __UIP-NEIGHBOR_H__ */ diff --git a/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-split.c b/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-split.c deleted file mode 100644 index 639b9fcd5..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-split.c +++ /dev/null @@ -1,136 +0,0 @@ -/* - * Copyright (c) 2004, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack - * - * Author: Adam Dunkels - * - * $Id: uip-split.c,v 1.2 2006/06/12 08:00:30 adam Exp $ - */ - -#include - -#include "uip-split.h" -#include "uip.h" -#include "uip-fw.h" -#include "uip_arch.h" - - - -#define BUF ((struct uip_tcpip_hdr *)&uip_buf[UIP_LLH_LEN]) - -/*-----------------------------------------------------------------------------*/ -void -uip_split_output(void) -{ - u16_t tcplen, len1, len2; - - /* We only try to split maximum sized TCP segments. */ - if(BUF->proto == UIP_PROTO_TCP && - uip_len == UIP_BUFSIZE - UIP_LLH_LEN) { - - tcplen = uip_len - UIP_TCPIP_HLEN; - /* Split the segment in two. If the original packet length was - odd, we make the second packet one byte larger. */ - len1 = len2 = tcplen / 2; - if(len1 + len2 < tcplen) { - ++len2; - } - - /* Create the first packet. This is done by altering the length - field of the IP header and updating the checksums. */ - uip_len = len1 + UIP_TCPIP_HLEN; -#if UIP_CONF_IPV6 - /* For IPv6, the IP length field does not include the IPv6 IP header - length. */ - BUF->len[0] = ((uip_len - UIP_IPH_LEN) >> 8); - BUF->len[1] = ((uip_len - UIP_IPH_LEN) & 0xff); -#else /* UIP_CONF_IPV6 */ - BUF->len[0] = uip_len >> 8; - BUF->len[1] = uip_len & 0xff; -#endif /* UIP_CONF_IPV6 */ - - /* Recalculate the TCP checksum. */ - BUF->tcpchksum = 0; - BUF->tcpchksum = ~(uip_tcpchksum()); - -#if !UIP_CONF_IPV6 - /* Recalculate the IP checksum. */ - BUF->ipchksum = 0; - BUF->ipchksum = ~(uip_ipchksum()); -#endif /* UIP_CONF_IPV6 */ - - /* Transmit the first packet. */ - /* uip_fw_output();*/ - tcpip_output(); - - /* Now, create the second packet. To do this, it is not enough to - just alter the length field, but we must also update the TCP - sequence number and point the uip_appdata to a new place in - memory. This place is detemined by the length of the first - packet (len1). */ - uip_len = len2 + UIP_TCPIP_HLEN; -#if UIP_CONF_IPV6 - /* For IPv6, the IP length field does not include the IPv6 IP header - length. */ - BUF->len[0] = ((uip_len - UIP_IPH_LEN) >> 8); - BUF->len[1] = ((uip_len - UIP_IPH_LEN) & 0xff); -#else /* UIP_CONF_IPV6 */ - BUF->len[0] = uip_len >> 8; - BUF->len[1] = uip_len & 0xff; -#endif /* UIP_CONF_IPV6 */ - - /* uip_appdata += len1;*/ - memcpy(uip_appdata, (u8_t *)uip_appdata + len1, len2); - - uip_add32(BUF->seqno, len1); - BUF->seqno[0] = uip_acc32[0]; - BUF->seqno[1] = uip_acc32[1]; - BUF->seqno[2] = uip_acc32[2]; - BUF->seqno[3] = uip_acc32[3]; - - /* Recalculate the TCP checksum. */ - BUF->tcpchksum = 0; - BUF->tcpchksum = ~(uip_tcpchksum()); - -#if !UIP_CONF_IPV6 - /* Recalculate the IP checksum. */ - BUF->ipchksum = 0; - BUF->ipchksum = ~(uip_ipchksum()); -#endif /* UIP_CONF_IPV6 */ - - /* Transmit the second packet. */ - /* uip_fw_output();*/ - tcpip_output(); - } else { - /* uip_fw_output();*/ - tcpip_output(); - } - -} -/*-----------------------------------------------------------------------------*/ diff --git a/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-split.h b/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-split.h deleted file mode 100644 index 446e19200..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/uip/uip-split.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (c) 2004, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack - * - * Author: Adam Dunkels - * - * $Id: uip-split.h,v 1.2 2006/06/12 08:00:30 adam Exp $ - */ -/** - * \addtogroup uip - * @{ - */ - -/** - * \defgroup uipsplit uIP TCP throughput booster hack - * @{ - * - * The basic uIP TCP implementation only allows each TCP connection to - * have a single TCP segment in flight at any given time. Because of - * the delayed ACK algorithm employed by most TCP receivers, uIP's - * limit on the amount of in-flight TCP segments seriously reduces the - * maximum achievable throughput for sending data from uIP. - * - * The uip-split module is a hack which tries to remedy this - * situation. By splitting maximum sized outgoing TCP segments into - * two, the delayed ACK algorithm is not invoked at TCP - * receivers. This improves the throughput when sending data from uIP - * by orders of magnitude. - * - * The uip-split module uses the uip-fw module (uIP IP packet - * forwarding) for sending packets. Therefore, the uip-fw module must - * be set up with the appropriate network interfaces for this module - * to work. - */ - - -/** - * \file - * Module for splitting outbound TCP segments in two to avoid the - * delayed ACK throughput degradation. - * \author - * Adam Dunkels - * - */ - -#ifndef __UIP_SPLIT_H__ -#define __UIP_SPLIT_H__ - -/** - * Handle outgoing packets. - * - * This function inspects an outgoing packet in the uip_buf buffer and - * sends it out using the uip_fw_output() function. If the packet is a - * full-sized TCP segment it will be split into two segments and - * transmitted separately. This function should be called instead of - * the actual device driver output function, or the uip_fw_output() - * function. - * - * The headers of the outgoing packet is assumed to be in the uip_buf - * buffer and the payload is assumed to be wherever uip_appdata - * points. The length of the outgoing packet is assumed to be in the - * uip_len variable. - * - */ -void uip_split_output(void); - -#endif /* __UIP_SPLIT_H__ */ - -/** @} */ -/** @} */ diff --git a/Demo/Common/ethernet/uIP/uip-1.0/uip/uip.c b/Demo/Common/ethernet/uIP/uip-1.0/uip/uip.c deleted file mode 100644 index 2843539c5..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/uip/uip.c +++ /dev/null @@ -1,1896 +0,0 @@ -#define DEBUG_PRINTF(...) /*printf(__VA_ARGS__)*/ - -/** - * \defgroup uip The uIP TCP/IP stack - * @{ - * - * uIP is an implementation of the TCP/IP protocol stack intended for - * small 8-bit and 16-bit microcontrollers. - * - * uIP provides the necessary protocols for Internet communication, - * with a very small code footprint and RAM requirements - the uIP - * code size is on the order of a few kilobytes and RAM usage is on - * the order of a few hundred bytes. - */ - -/** - * \file - * The uIP TCP/IP stack code. - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2001-2003, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: uip.c,v 1.65 2006/06/11 21:46:39 adam Exp $ - * - */ - -/* - * uIP is a small implementation of the IP, UDP and TCP protocols (as - * well as some basic ICMP stuff). The implementation couples the IP, - * UDP, TCP and the application layers very tightly. To keep the size - * of the compiled code down, this code frequently uses the goto - * statement. While it would be possible to break the uip_process() - * function into many smaller functions, this would increase the code - * size because of the overhead of parameter passing and the fact that - * the optimier would not be as efficient. - * - * The principle is that we have a small buffer, called the uip_buf, - * in which the device driver puts an incoming packet. The TCP/IP - * stack parses the headers in the packet, and calls the - * application. If the remote host has sent data to the application, - * this data is present in the uip_buf and the application read the - * data from there. It is up to the application to put this data into - * a byte stream if needed. The application will not be fed with data - * that is out of sequence. - * - * If the application whishes to send data to the peer, it should put - * its data into the uip_buf. The uip_appdata pointer points to the - * first available byte. The TCP/IP stack will calculate the - * checksums, and fill in the necessary header fields and finally send - * the packet back to the peer. -*/ - -#include "uip.h" -#include "uipopt.h" -#include "uip_arch.h" - -#if UIP_CONF_IPV6 -#include "uip-neighbor.h" -#endif /* UIP_CONF_IPV6 */ - -#include - -/*---------------------------------------------------------------------------*/ -/* Variable definitions. */ - - -/* The IP address of this host. If it is defined to be fixed (by - setting UIP_FIXEDADDR to 1 in uipopt.h), the address is set - here. Otherwise, the address */ -#if UIP_FIXEDADDR > 0 -const uip_ipaddr_t uip_hostaddr = - {HTONS((UIP_IPADDR0 << 8) | UIP_IPADDR1), - HTONS((UIP_IPADDR2 << 8) | UIP_IPADDR3)}; -const uip_ipaddr_t uip_draddr = - {HTONS((UIP_DRIPADDR0 << 8) | UIP_DRIPADDR1), - HTONS((UIP_DRIPADDR2 << 8) | UIP_DRIPADDR3)}; -const uip_ipaddr_t uip_netmask = - {HTONS((UIP_NETMASK0 << 8) | UIP_NETMASK1), - HTONS((UIP_NETMASK2 << 8) | UIP_NETMASK3)}; -#else -uip_ipaddr_t uip_hostaddr, uip_draddr, uip_netmask; -#endif /* UIP_FIXEDADDR */ - -static const uip_ipaddr_t all_ones_addr = -#if UIP_CONF_IPV6 - {0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff,0xffff}; -#else /* UIP_CONF_IPV6 */ - {0xffff,0xffff}; -#endif /* UIP_CONF_IPV6 */ -static const uip_ipaddr_t all_zeroes_addr = -#if UIP_CONF_IPV6 - {0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000}; -#else /* UIP_CONF_IPV6 */ - {0x0000,0x0000}; -#endif /* UIP_CONF_IPV6 */ - -#if UIP_FIXEDETHADDR -const struct uip_eth_addr uip_ethaddr = {{UIP_ETHADDR0, - UIP_ETHADDR1, - UIP_ETHADDR2, - UIP_ETHADDR3, - UIP_ETHADDR4, - UIP_ETHADDR5}}; -#else -struct uip_eth_addr uip_ethaddr = {{0,0,0,0,0,0}}; -#endif - -#ifndef UIP_CONF_EXTERNAL_BUFFER -u8_t uip_buf[UIP_BUFSIZE + 2]; /* The packet buffer that contains - incoming packets. */ -#endif /* UIP_CONF_EXTERNAL_BUFFER */ - -void *uip_appdata; /* The uip_appdata pointer points to - application data. */ -void *uip_sappdata; /* The uip_appdata pointer points to - the application data which is to - be sent. */ -#if UIP_URGDATA > 0 -void *uip_urgdata; /* The uip_urgdata pointer points to - urgent data (out-of-band data), if - present. */ -u16_t uip_urglen, uip_surglen; -#endif /* UIP_URGDATA > 0 */ - -u16_t uip_len, uip_slen; - /* The uip_len is either 8 or 16 bits, - depending on the maximum packet - size. */ - -u8_t uip_flags; /* The uip_flags variable is used for - communication between the TCP/IP stack - and the application program. */ -struct uip_conn *uip_conn; /* uip_conn always points to the current - connection. */ - -struct uip_conn uip_conns[UIP_CONNS]; - /* The uip_conns array holds all TCP - connections. */ -u16_t uip_listenports[UIP_LISTENPORTS]; - /* The uip_listenports list all currently - listning ports. */ -#if UIP_UDP -struct uip_udp_conn *uip_udp_conn; -struct uip_udp_conn uip_udp_conns[UIP_UDP_CONNS]; -#endif /* UIP_UDP */ - -static u16_t ipid; /* Ths ipid variable is an increasing - number that is used for the IP ID - field. */ - -void uip_setipid(u16_t id) { ipid = id; } - -static u8_t iss[4]; /* The iss variable is used for the TCP - initial sequence number. */ - -#if UIP_ACTIVE_OPEN -static u16_t lastport; /* Keeps track of the last port used for - a new connection. */ -#endif /* UIP_ACTIVE_OPEN */ - -/* Temporary variables. */ -u8_t uip_acc32[4]; -static u8_t c, opt; -static u16_t tmp16; - -/* Structures and definitions. */ -#define TCP_FIN 0x01 -#define TCP_SYN 0x02 -#define TCP_RST 0x04 -#define TCP_PSH 0x08 -#define TCP_ACK 0x10 -#define TCP_URG 0x20 -#define TCP_CTL 0x3f - -#define TCP_OPT_END 0 /* End of TCP options list */ -#define TCP_OPT_NOOP 1 /* "No-operation" TCP option */ -#define TCP_OPT_MSS 2 /* Maximum segment size TCP option */ - -#define TCP_OPT_MSS_LEN 4 /* Length of TCP MSS option. */ - -#define ICMP_ECHO_REPLY 0 -#define ICMP_ECHO 8 - -#define ICMP6_ECHO_REPLY 129 -#define ICMP6_ECHO 128 -#define ICMP6_NEIGHBOR_SOLICITATION 135 -#define ICMP6_NEIGHBOR_ADVERTISEMENT 136 - -#define ICMP6_FLAG_S (1 << 6) - -#define ICMP6_OPTION_SOURCE_LINK_ADDRESS 1 -#define ICMP6_OPTION_TARGET_LINK_ADDRESS 2 - - -/* Macros. */ -#define BUF ((struct uip_tcpip_hdr *)&uip_buf[UIP_LLH_LEN]) -#define FBUF ((struct uip_tcpip_hdr *)&uip_reassbuf[0]) -#define ICMPBUF ((struct uip_icmpip_hdr *)&uip_buf[UIP_LLH_LEN]) -#define UDPBUF ((struct uip_udpip_hdr *)&uip_buf[UIP_LLH_LEN]) - - -#if UIP_STATISTICS == 1 -struct uip_stats uip_stat; -#define UIP_STAT(s) s -#else -#define UIP_STAT(s) -#endif /* UIP_STATISTICS == 1 */ - -#if UIP_LOGGING == 1 -#include -void uip_log(char *msg); -#define UIP_LOG(m) uip_log(m) -#else -#define UIP_LOG(m) -#endif /* UIP_LOGGING == 1 */ - -#if ! UIP_ARCH_ADD32 -void -uip_add32(u8_t *op32, u16_t op16) -{ - uip_acc32[3] = op32[3] + (op16 & 0xff); - uip_acc32[2] = op32[2] + (op16 >> 8); - uip_acc32[1] = op32[1]; - uip_acc32[0] = op32[0]; - - if(uip_acc32[2] < (op16 >> 8)) { - ++uip_acc32[1]; - if(uip_acc32[1] == 0) { - ++uip_acc32[0]; - } - } - - - if(uip_acc32[3] < (op16 & 0xff)) { - ++uip_acc32[2]; - if(uip_acc32[2] == 0) { - ++uip_acc32[1]; - if(uip_acc32[1] == 0) { - ++uip_acc32[0]; - } - } - } -} - -#endif /* UIP_ARCH_ADD32 */ - -#if ! UIP_ARCH_CHKSUM -/*---------------------------------------------------------------------------*/ -static u16_t -chksum(u16_t sum, const u8_t *data, u16_t len) -{ - u16_t t; - const u8_t *dataptr; - const u8_t *last_byte; - - dataptr = data; - last_byte = data + len - 1; - - while(dataptr < last_byte) { /* At least two more bytes */ - t = (dataptr[0] << 8) + dataptr[1]; - sum += t; - if(sum < t) { - sum++; /* carry */ - } - dataptr += 2; - } - - if(dataptr == last_byte) { - t = (dataptr[0] << 8) + 0; - sum += t; - if(sum < t) { - sum++; /* carry */ - } - } - - /* Return sum in host byte order. */ - return sum; -} -/*---------------------------------------------------------------------------*/ -u16_t -uip_chksum(u16_t *data, u16_t len) -{ - return htons(chksum(0, (u8_t *)data, len)); -} -/*---------------------------------------------------------------------------*/ -#ifndef UIP_ARCH_IPCHKSUM -u16_t -uip_ipchksum(void) -{ - u16_t sum; - - sum = chksum(0, &uip_buf[UIP_LLH_LEN], UIP_IPH_LEN); - DEBUG_PRINTF("uip_ipchksum: sum 0x%04x\n", sum); - return (sum == 0) ? 0xffff : htons(sum); -} -#endif -/*---------------------------------------------------------------------------*/ -static u16_t -upper_layer_chksum(u8_t proto) -{ - u16_t upper_layer_len; - u16_t sum; - -#if UIP_CONF_IPV6 - upper_layer_len = (((u16_t)(BUF->len[0]) << 8) + BUF->len[1]); -#else /* UIP_CONF_IPV6 */ - upper_layer_len = (((u16_t)(BUF->len[0]) << 8) + BUF->len[1]) - UIP_IPH_LEN; -#endif /* UIP_CONF_IPV6 */ - - /* First sum pseudoheader. */ - - /* IP protocol and length fields. This addition cannot carry. */ - sum = upper_layer_len + proto; - /* Sum IP source and destination addresses. */ - sum = chksum(sum, (u8_t *)&BUF->srcipaddr[0], 2 * sizeof(uip_ipaddr_t)); - - /* Sum TCP header and data. */ - sum = chksum(sum, &uip_buf[UIP_IPH_LEN + UIP_LLH_LEN], - upper_layer_len); - - return (sum == 0) ? 0xffff : htons(sum); -} -/*---------------------------------------------------------------------------*/ -#if UIP_CONF_IPV6 -u16_t -uip_icmp6chksum(void) -{ - return upper_layer_chksum(UIP_PROTO_ICMP6); - -} -#endif /* UIP_CONF_IPV6 */ -/*---------------------------------------------------------------------------*/ -u16_t -uip_tcpchksum(void) -{ - return upper_layer_chksum(UIP_PROTO_TCP); -} -/*---------------------------------------------------------------------------*/ -#if UIP_UDP_CHECKSUMS -u16_t -uip_udpchksum(void) -{ - return upper_layer_chksum(UIP_PROTO_UDP); -} -#endif /* UIP_UDP_CHECKSUMS */ -#endif /* UIP_ARCH_CHKSUM */ -/*---------------------------------------------------------------------------*/ -void -uip_init(void) -{ - for(c = 0; c < UIP_LISTENPORTS; ++c) { - uip_listenports[c] = 0; - } - for(c = 0; c < UIP_CONNS; ++c) { - uip_conns[c].tcpstateflags = UIP_CLOSED; - } -#if UIP_ACTIVE_OPEN - lastport = 1024; -#endif /* UIP_ACTIVE_OPEN */ - -#if UIP_UDP - for(c = 0; c < UIP_UDP_CONNS; ++c) { - uip_udp_conns[c].lport = 0; - } -#endif /* UIP_UDP */ - - - /* IPv4 initialization. */ -#if UIP_FIXEDADDR == 0 - /* uip_hostaddr[0] = uip_hostaddr[1] = 0;*/ -#endif /* UIP_FIXEDADDR */ - -} -/*---------------------------------------------------------------------------*/ -#if UIP_ACTIVE_OPEN -struct uip_conn * -uip_connect(uip_ipaddr_t *ripaddr, u16_t rport) -{ - register struct uip_conn *conn, *cconn; - - /* Find an unused local port. */ - again: - ++lastport; - - if(lastport >= 32000) { - lastport = 4096; - } - - /* Check if this port is already in use, and if so try to find - another one. */ - for(c = 0; c < UIP_CONNS; ++c) { - conn = &uip_conns[c]; - if(conn->tcpstateflags != UIP_CLOSED && - conn->lport == htons(lastport)) { - goto again; - } - } - - conn = 0; - for(c = 0; c < UIP_CONNS; ++c) { - cconn = &uip_conns[c]; - if(cconn->tcpstateflags == UIP_CLOSED) { - conn = cconn; - break; - } - if(cconn->tcpstateflags == UIP_TIME_WAIT) { - if(conn == 0 || - cconn->timer > conn->timer) { - conn = cconn; - } - } - } - - if(conn == 0) { - return 0; - } - - conn->tcpstateflags = UIP_SYN_SENT; - - conn->snd_nxt[0] = iss[0]; - conn->snd_nxt[1] = iss[1]; - conn->snd_nxt[2] = iss[2]; - conn->snd_nxt[3] = iss[3]; - - conn->initialmss = conn->mss = UIP_TCP_MSS; - - conn->len = 1; /* TCP length of the SYN is one. */ - conn->nrtx = 0; - conn->timer = 1; /* Send the SYN next time around. */ - conn->rto = UIP_RTO; - conn->sa = 0; - conn->sv = 16; /* Initial value of the RTT variance. */ - conn->lport = htons(lastport); - conn->rport = rport; - uip_ipaddr_copy(&conn->ripaddr, ripaddr); - - return conn; -} -#endif /* UIP_ACTIVE_OPEN */ -/*---------------------------------------------------------------------------*/ -#if UIP_UDP -struct uip_udp_conn * -uip_udp_new(uip_ipaddr_t *ripaddr, u16_t rport) -{ - register struct uip_udp_conn *conn; - - /* Find an unused local port. */ - again: - ++lastport; - - if(lastport >= 32000) { - lastport = 4096; - } - - for(c = 0; c < UIP_UDP_CONNS; ++c) { - if(uip_udp_conns[c].lport == htons(lastport)) { - goto again; - } - } - - - conn = 0; - for(c = 0; c < UIP_UDP_CONNS; ++c) { - if(uip_udp_conns[c].lport == 0) { - conn = &uip_udp_conns[c]; - break; - } - } - - if(conn == 0) { - return 0; - } - - conn->lport = HTONS(lastport); - conn->rport = rport; - if(ripaddr == NULL) { - memset(conn->ripaddr, 0, sizeof(uip_ipaddr_t)); - } else { - uip_ipaddr_copy(&conn->ripaddr, ripaddr); - } - conn->ttl = UIP_TTL; - - return conn; -} -#endif /* UIP_UDP */ -/*---------------------------------------------------------------------------*/ -void -uip_unlisten(u16_t port) -{ - for(c = 0; c < UIP_LISTENPORTS; ++c) { - if(uip_listenports[c] == port) { - uip_listenports[c] = 0; - return; - } - } -} -/*---------------------------------------------------------------------------*/ -void -uip_listen(u16_t port) -{ - for(c = 0; c < UIP_LISTENPORTS; ++c) { - if(uip_listenports[c] == 0) { - uip_listenports[c] = port; - return; - } - } -} -/*---------------------------------------------------------------------------*/ -/* XXX: IP fragment reassembly: not well-tested. */ - -#if UIP_REASSEMBLY && !UIP_CONF_IPV6 -#define UIP_REASS_BUFSIZE (UIP_BUFSIZE - UIP_LLH_LEN) -static u8_t uip_reassbuf[UIP_REASS_BUFSIZE]; -static u8_t uip_reassbitmap[UIP_REASS_BUFSIZE / (8 * 8)]; -static const u8_t bitmap_bits[8] = {0xff, 0x7f, 0x3f, 0x1f, - 0x0f, 0x07, 0x03, 0x01}; -static u16_t uip_reasslen; -static u8_t uip_reassflags; -#define UIP_REASS_FLAG_LASTFRAG 0x01 -static u8_t uip_reasstmr; - -#define IP_MF 0x20 - -static u8_t -uip_reass(void) -{ - u16_t offset, len; - u16_t i; - - /* If ip_reasstmr is zero, no packet is present in the buffer, so we - write the IP header of the fragment into the reassembly - buffer. The timer is updated with the maximum age. */ - if(uip_reasstmr == 0) { - memcpy(uip_reassbuf, &BUF->vhl, UIP_IPH_LEN); - uip_reasstmr = UIP_REASS_MAXAGE; - uip_reassflags = 0; - /* Clear the bitmap. */ - memset(uip_reassbitmap, 0, sizeof(uip_reassbitmap)); - } - - /* Check if the incoming fragment matches the one currently present - in the reasembly buffer. If so, we proceed with copying the - fragment into the buffer. */ - if(BUF->srcipaddr[0] == FBUF->srcipaddr[0] && - BUF->srcipaddr[1] == FBUF->srcipaddr[1] && - BUF->destipaddr[0] == FBUF->destipaddr[0] && - BUF->destipaddr[1] == FBUF->destipaddr[1] && - BUF->ipid[0] == FBUF->ipid[0] && - BUF->ipid[1] == FBUF->ipid[1]) { - - len = (BUF->len[0] << 8) + BUF->len[1] - (BUF->vhl & 0x0f) * 4; - offset = (((BUF->ipoffset[0] & 0x3f) << 8) + BUF->ipoffset[1]) * 8; - - /* If the offset or the offset + fragment length overflows the - reassembly buffer, we discard the entire packet. */ - if(offset > UIP_REASS_BUFSIZE || - offset + len > UIP_REASS_BUFSIZE) { - uip_reasstmr = 0; - goto nullreturn; - } - - /* Copy the fragment into the reassembly buffer, at the right - offset. */ - memcpy(&uip_reassbuf[UIP_IPH_LEN + offset], - (char *)BUF + (int)((BUF->vhl & 0x0f) * 4), - len); - - /* Update the bitmap. */ - if(offset / (8 * 8) == (offset + len) / (8 * 8)) { - /* If the two endpoints are in the same byte, we only update - that byte. */ - - uip_reassbitmap[offset / (8 * 8)] |= - bitmap_bits[(offset / 8 ) & 7] & - ~bitmap_bits[((offset + len) / 8 ) & 7]; - } else { - /* If the two endpoints are in different bytes, we update the - bytes in the endpoints and fill the stuff inbetween with - 0xff. */ - uip_reassbitmap[offset / (8 * 8)] |= - bitmap_bits[(offset / 8 ) & 7]; - for(i = 1 + offset / (8 * 8); i < (offset + len) / (8 * 8); ++i) { - uip_reassbitmap[i] = 0xff; - } - uip_reassbitmap[(offset + len) / (8 * 8)] |= - ~bitmap_bits[((offset + len) / 8 ) & 7]; - } - - /* If this fragment has the More Fragments flag set to zero, we - know that this is the last fragment, so we can calculate the - size of the entire packet. We also set the - IP_REASS_FLAG_LASTFRAG flag to indicate that we have received - the final fragment. */ - - if((BUF->ipoffset[0] & IP_MF) == 0) { - uip_reassflags |= UIP_REASS_FLAG_LASTFRAG; - uip_reasslen = offset + len; - } - - /* Finally, we check if we have a full packet in the buffer. We do - this by checking if we have the last fragment and if all bits - in the bitmap are set. */ - if(uip_reassflags & UIP_REASS_FLAG_LASTFRAG) { - /* Check all bytes up to and including all but the last byte in - the bitmap. */ - for(i = 0; i < uip_reasslen / (8 * 8) - 1; ++i) { - if(uip_reassbitmap[i] != 0xff) { - goto nullreturn; - } - } - /* Check the last byte in the bitmap. It should contain just the - right amount of bits. */ - if(uip_reassbitmap[uip_reasslen / (8 * 8)] != - (u8_t)~bitmap_bits[uip_reasslen / 8 & 7]) { - goto nullreturn; - } - - /* If we have come this far, we have a full packet in the - buffer, so we allocate a pbuf and copy the packet into it. We - also reset the timer. */ - uip_reasstmr = 0; - memcpy(BUF, FBUF, uip_reasslen); - - /* Pretend to be a "normal" (i.e., not fragmented) IP packet - from now on. */ - BUF->ipoffset[0] = BUF->ipoffset[1] = 0; - BUF->len[0] = uip_reasslen >> 8; - BUF->len[1] = uip_reasslen & 0xff; - BUF->ipchksum = 0; - BUF->ipchksum = ~(uip_ipchksum()); - - return uip_reasslen; - } - } - - nullreturn: - return 0; -} -#endif /* UIP_REASSEMBLY */ -/*---------------------------------------------------------------------------*/ -static void -uip_add_rcv_nxt(u16_t n) -{ - uip_add32(uip_conn->rcv_nxt, n); - uip_conn->rcv_nxt[0] = uip_acc32[0]; - uip_conn->rcv_nxt[1] = uip_acc32[1]; - uip_conn->rcv_nxt[2] = uip_acc32[2]; - uip_conn->rcv_nxt[3] = uip_acc32[3]; -} -/*---------------------------------------------------------------------------*/ -void -uip_process(u8_t flag) -{ - register struct uip_conn *uip_connr = uip_conn; - -#if UIP_UDP - if(flag == UIP_UDP_SEND_CONN) { - goto udp_send; - } -#endif /* UIP_UDP */ - - uip_sappdata = uip_appdata = &uip_buf[UIP_IPTCPH_LEN + UIP_LLH_LEN]; - - /* Check if we were invoked because of a poll request for a - particular connection. */ - if(flag == UIP_POLL_REQUEST) { - if((uip_connr->tcpstateflags & UIP_TS_MASK) == UIP_ESTABLISHED && - !uip_outstanding(uip_connr)) { - uip_flags = UIP_POLL; - UIP_APPCALL(); - goto appsend; - } - goto drop; - - /* Check if we were invoked because of the perodic timer fireing. */ - } else if(flag == UIP_TIMER) { -#if UIP_REASSEMBLY - if(uip_reasstmr != 0) { - --uip_reasstmr; - } -#endif /* UIP_REASSEMBLY */ - /* Increase the initial sequence number. */ - if(++iss[3] == 0) { - if(++iss[2] == 0) { - if(++iss[1] == 0) { - ++iss[0]; - } - } - } - - /* Reset the length variables. */ - uip_len = 0; - uip_slen = 0; - - /* Check if the connection is in a state in which we simply wait - for the connection to time out. If so, we increase the - connection's timer and remove the connection if it times - out. */ - if(uip_connr->tcpstateflags == UIP_TIME_WAIT || - uip_connr->tcpstateflags == UIP_FIN_WAIT_2) { - ++(uip_connr->timer); - if(uip_connr->timer == UIP_TIME_WAIT_TIMEOUT) { - uip_connr->tcpstateflags = UIP_CLOSED; - } - } else if(uip_connr->tcpstateflags != UIP_CLOSED) { - /* If the connection has outstanding data, we increase the - connection's timer and see if it has reached the RTO value - in which case we retransmit. */ - if(uip_outstanding(uip_connr)) { - if(uip_connr->timer-- == 0) { - if(uip_connr->nrtx == UIP_MAXRTX || - ((uip_connr->tcpstateflags == UIP_SYN_SENT || - uip_connr->tcpstateflags == UIP_SYN_RCVD) && - uip_connr->nrtx == UIP_MAXSYNRTX)) { - uip_connr->tcpstateflags = UIP_CLOSED; - - /* We call UIP_APPCALL() with uip_flags set to - UIP_TIMEDOUT to inform the application that the - connection has timed out. */ - uip_flags = UIP_TIMEDOUT; - UIP_APPCALL(); - - /* We also send a reset packet to the remote host. */ - BUF->flags = TCP_RST | TCP_ACK; - goto tcp_send_nodata; - } - - /* Exponential backoff. */ - uip_connr->timer = UIP_RTO << (uip_connr->nrtx > 4? - 4: - uip_connr->nrtx); - ++(uip_connr->nrtx); - - /* Ok, so we need to retransmit. We do this differently - depending on which state we are in. In ESTABLISHED, we - call upon the application so that it may prepare the - data for the retransmit. In SYN_RCVD, we resend the - SYNACK that we sent earlier and in LAST_ACK we have to - retransmit our FINACK. */ - UIP_STAT(++uip_stat.tcp.rexmit); - switch(uip_connr->tcpstateflags & UIP_TS_MASK) { - case UIP_SYN_RCVD: - /* In the SYN_RCVD state, we should retransmit our - SYNACK. */ - goto tcp_send_synack; - -#if UIP_ACTIVE_OPEN - case UIP_SYN_SENT: - /* In the SYN_SENT state, we retransmit out SYN. */ - BUF->flags = 0; - goto tcp_send_syn; -#endif /* UIP_ACTIVE_OPEN */ - - case UIP_ESTABLISHED: - /* In the ESTABLISHED state, we call upon the application - to do the actual retransmit after which we jump into - the code for sending out the packet (the apprexmit - label). */ - uip_flags = UIP_REXMIT; - UIP_APPCALL(); - goto apprexmit; - - case UIP_FIN_WAIT_1: - case UIP_CLOSING: - case UIP_LAST_ACK: - /* In all these states we should retransmit a FINACK. */ - goto tcp_send_finack; - - } - } - } else if((uip_connr->tcpstateflags & UIP_TS_MASK) == UIP_ESTABLISHED) { - /* If there was no need for a retransmission, we poll the - application for new data. */ - uip_flags = UIP_POLL; - UIP_APPCALL(); - goto appsend; - } - } - goto drop; - } -#if UIP_UDP - if(flag == UIP_UDP_TIMER) { - if(uip_udp_conn->lport != 0) { - uip_conn = NULL; - uip_sappdata = uip_appdata = &uip_buf[UIP_LLH_LEN + UIP_IPUDPH_LEN]; - uip_len = uip_slen = 0; - uip_flags = UIP_POLL; - UIP_UDP_APPCALL(); - goto udp_send; - } else { - goto drop; - } - } -#endif - - /* This is where the input processing starts. */ - UIP_STAT(++uip_stat.ip.recv); - - /* Start of IP input header processing code. */ - -#if UIP_CONF_IPV6 - /* Check validity of the IP header. */ - if((BUF->vtc & 0xf0) != 0x60) { /* IP version and header length. */ - UIP_STAT(++uip_stat.ip.drop); - UIP_STAT(++uip_stat.ip.vhlerr); - UIP_LOG("ipv6: invalid version."); - goto drop; - } -#else /* UIP_CONF_IPV6 */ - /* Check validity of the IP header. */ - if(BUF->vhl != 0x45) { /* IP version and header length. */ - UIP_STAT(++uip_stat.ip.drop); - UIP_STAT(++uip_stat.ip.vhlerr); - UIP_LOG("ip: invalid version or header length."); - goto drop; - } -#endif /* UIP_CONF_IPV6 */ - - /* Check the size of the packet. If the size reported to us in - uip_len is smaller the size reported in the IP header, we assume - that the packet has been corrupted in transit. If the size of - uip_len is larger than the size reported in the IP packet header, - the packet has been padded and we set uip_len to the correct - value.. */ - - if((BUF->len[0] << 8) + BUF->len[1] <= uip_len) { - uip_len = (BUF->len[0] << 8) + BUF->len[1]; -#if UIP_CONF_IPV6 - uip_len += 40; /* The length reported in the IPv6 header is the - length of the payload that follows the - header. However, uIP uses the uip_len variable - for holding the size of the entire packet, - including the IP header. For IPv4 this is not a - problem as the length field in the IPv4 header - contains the length of the entire packet. But - for IPv6 we need to add the size of the IPv6 - header (40 bytes). */ -#endif /* UIP_CONF_IPV6 */ - } else { - UIP_LOG("ip: packet shorter than reported in IP header."); - goto drop; - } - -#if !UIP_CONF_IPV6 - /* Check the fragment flag. */ - if((BUF->ipoffset[0] & 0x3f) != 0 || - BUF->ipoffset[1] != 0) { -#if UIP_REASSEMBLY - uip_len = uip_reass(); - if(uip_len == 0) { - goto drop; - } -#else /* UIP_REASSEMBLY */ - UIP_STAT(++uip_stat.ip.drop); - UIP_STAT(++uip_stat.ip.fragerr); - UIP_LOG("ip: fragment dropped."); - goto drop; -#endif /* UIP_REASSEMBLY */ - } -#endif /* UIP_CONF_IPV6 */ - - if(uip_ipaddr_cmp(uip_hostaddr, all_zeroes_addr)) { - /* If we are configured to use ping IP address configuration and - hasn't been assigned an IP address yet, we accept all ICMP - packets. */ -#if UIP_PINGADDRCONF && !UIP_CONF_IPV6 - if(BUF->proto == UIP_PROTO_ICMP) { - UIP_LOG("ip: possible ping config packet received."); - goto icmp_input; - } else { - UIP_LOG("ip: packet dropped since no address assigned."); - goto drop; - } -#endif /* UIP_PINGADDRCONF */ - - } else { - /* If IP broadcast support is configured, we check for a broadcast - UDP packet, which may be destined to us. */ -#if UIP_BROADCAST - DEBUG_PRINTF("UDP IP checksum 0x%04x\n", uip_ipchksum()); - if(BUF->proto == UIP_PROTO_UDP && - uip_ipaddr_cmp(BUF->destipaddr, all_ones_addr) - /*&& - uip_ipchksum() == 0xffff*/) { - goto udp_input; - } -#endif /* UIP_BROADCAST */ - - /* Check if the packet is destined for our IP address. */ -#if !UIP_CONF_IPV6 - if(!uip_ipaddr_cmp(BUF->destipaddr, uip_hostaddr)) { - UIP_STAT(++uip_stat.ip.drop); - goto drop; - } -#else /* UIP_CONF_IPV6 */ - /* For IPv6, packet reception is a little trickier as we need to - make sure that we listen to certain multicast addresses (all - hosts multicast address, and the solicited-node multicast - address) as well. However, we will cheat here and accept all - multicast packets that are sent to the ff02::/16 addresses. */ - if(!uip_ipaddr_cmp(BUF->destipaddr, uip_hostaddr) && - BUF->destipaddr[0] != HTONS(0xff02)) { - UIP_STAT(++uip_stat.ip.drop); - goto drop; - } -#endif /* UIP_CONF_IPV6 */ - } - -#if !UIP_CONF_IPV6 - if(uip_ipchksum() != 0xffff) { /* Compute and check the IP header - checksum. */ - UIP_STAT(++uip_stat.ip.drop); - UIP_STAT(++uip_stat.ip.chkerr); - UIP_LOG("ip: bad checksum."); - goto drop; - } -#endif /* UIP_CONF_IPV6 */ - - if(BUF->proto == UIP_PROTO_TCP) { /* Check for TCP packet. If so, - proceed with TCP input - processing. */ - goto tcp_input; - } - -#if UIP_UDP - if(BUF->proto == UIP_PROTO_UDP) { - goto udp_input; - } -#endif /* UIP_UDP */ - -#if !UIP_CONF_IPV6 - /* ICMPv4 processing code follows. */ - if(BUF->proto != UIP_PROTO_ICMP) { /* We only allow ICMP packets from - here. */ - UIP_STAT(++uip_stat.ip.drop); - UIP_STAT(++uip_stat.ip.protoerr); - UIP_LOG("ip: neither tcp nor icmp."); - goto drop; - } - -#if UIP_PINGADDRCONF - icmp_input: -#endif /* UIP_PINGADDRCONF */ - UIP_STAT(++uip_stat.icmp.recv); - - /* ICMP echo (i.e., ping) processing. This is simple, we only change - the ICMP type from ECHO to ECHO_REPLY and adjust the ICMP - checksum before we return the packet. */ - if(ICMPBUF->type != ICMP_ECHO) { - UIP_STAT(++uip_stat.icmp.drop); - UIP_STAT(++uip_stat.icmp.typeerr); - UIP_LOG("icmp: not icmp echo."); - goto drop; - } - - /* If we are configured to use ping IP address assignment, we use - the destination IP address of this ping packet and assign it to - ourself. */ -#if UIP_PINGADDRCONF - if((uip_hostaddr[0] | uip_hostaddr[1]) == 0) { - uip_hostaddr[0] = BUF->destipaddr[0]; - uip_hostaddr[1] = BUF->destipaddr[1]; - } -#endif /* UIP_PINGADDRCONF */ - - ICMPBUF->type = ICMP_ECHO_REPLY; - - if(ICMPBUF->icmpchksum >= HTONS(0xffff - (ICMP_ECHO << 8))) { - ICMPBUF->icmpchksum += HTONS(ICMP_ECHO << 8) + 1; - } else { - ICMPBUF->icmpchksum += HTONS(ICMP_ECHO << 8); - } - - /* Swap IP addresses. */ - uip_ipaddr_copy(BUF->destipaddr, BUF->srcipaddr); - uip_ipaddr_copy(BUF->srcipaddr, uip_hostaddr); - - UIP_STAT(++uip_stat.icmp.sent); - goto send; - - /* End of IPv4 input header processing code. */ -#else /* !UIP_CONF_IPV6 */ - - /* This is IPv6 ICMPv6 processing code. */ - DEBUG_PRINTF("icmp6_input: length %d\n", uip_len); - - if(BUF->proto != UIP_PROTO_ICMP6) { /* We only allow ICMPv6 packets from - here. */ - UIP_STAT(++uip_stat.ip.drop); - UIP_STAT(++uip_stat.ip.protoerr); - UIP_LOG("ip: neither tcp nor icmp6."); - goto drop; - } - - UIP_STAT(++uip_stat.icmp.recv); - - /* If we get a neighbor solicitation for our address we should send - a neighbor advertisement message back. */ - if(ICMPBUF->type == ICMP6_NEIGHBOR_SOLICITATION) { - if(uip_ipaddr_cmp(ICMPBUF->icmp6data, uip_hostaddr)) { - - if(ICMPBUF->options[0] == ICMP6_OPTION_SOURCE_LINK_ADDRESS) { - /* Save the sender's address in our neighbor list. */ - uip_neighbor_add(ICMPBUF->srcipaddr, &(ICMPBUF->options[2])); - } - - /* We should now send a neighbor advertisement back to where the - neighbor solicication came from. */ - ICMPBUF->type = ICMP6_NEIGHBOR_ADVERTISEMENT; - ICMPBUF->flags = ICMP6_FLAG_S; /* Solicited flag. */ - - ICMPBUF->reserved1 = ICMPBUF->reserved2 = ICMPBUF->reserved3 = 0; - - uip_ipaddr_copy(ICMPBUF->destipaddr, ICMPBUF->srcipaddr); - uip_ipaddr_copy(ICMPBUF->srcipaddr, uip_hostaddr); - ICMPBUF->options[0] = ICMP6_OPTION_TARGET_LINK_ADDRESS; - ICMPBUF->options[1] = 1; /* Options length, 1 = 8 bytes. */ - memcpy(&(ICMPBUF->options[2]), &uip_ethaddr, sizeof(uip_ethaddr)); - ICMPBUF->icmpchksum = 0; - ICMPBUF->icmpchksum = ~uip_icmp6chksum(); - goto send; - - } - goto drop; - } else if(ICMPBUF->type == ICMP6_ECHO) { - /* ICMP echo (i.e., ping) processing. This is simple, we only - change the ICMP type from ECHO to ECHO_REPLY and update the - ICMP checksum before we return the packet. */ - - ICMPBUF->type = ICMP6_ECHO_REPLY; - - uip_ipaddr_copy(BUF->destipaddr, BUF->srcipaddr); - uip_ipaddr_copy(BUF->srcipaddr, uip_hostaddr); - ICMPBUF->icmpchksum = 0; - ICMPBUF->icmpchksum = ~uip_icmp6chksum(); - - UIP_STAT(++uip_stat.icmp.sent); - goto send; - } else { - DEBUG_PRINTF("Unknown icmp6 message type %d\n", ICMPBUF->type); - UIP_STAT(++uip_stat.icmp.drop); - UIP_STAT(++uip_stat.icmp.typeerr); - UIP_LOG("icmp: unknown ICMP message."); - goto drop; - } - - /* End of IPv6 ICMP processing. */ - -#endif /* !UIP_CONF_IPV6 */ - -#if UIP_UDP - /* UDP input processing. */ - udp_input: - /* UDP processing is really just a hack. We don't do anything to the - UDP/IP headers, but let the UDP application do all the hard - work. If the application sets uip_slen, it has a packet to - send. */ -#if UIP_UDP_CHECKSUMS - uip_len = uip_len - UIP_IPUDPH_LEN; - uip_appdata = &uip_buf[UIP_LLH_LEN + UIP_IPUDPH_LEN]; - if(UDPBUF->udpchksum != 0 && uip_udpchksum() != 0xffff) { - UIP_STAT(++uip_stat.udp.drop); - UIP_STAT(++uip_stat.udp.chkerr); - UIP_LOG("udp: bad checksum."); - goto drop; - } -#else /* UIP_UDP_CHECKSUMS */ - uip_len = uip_len - UIP_IPUDPH_LEN; -#endif /* UIP_UDP_CHECKSUMS */ - - /* Demultiplex this UDP packet between the UDP "connections". */ - for(uip_udp_conn = &uip_udp_conns[0]; - uip_udp_conn < &uip_udp_conns[UIP_UDP_CONNS]; - ++uip_udp_conn) { - /* If the local UDP port is non-zero, the connection is considered - to be used. If so, the local port number is checked against the - destination port number in the received packet. If the two port - numbers match, the remote port number is checked if the - connection is bound to a remote port. Finally, if the - connection is bound to a remote IP address, the source IP - address of the packet is checked. */ - if(uip_udp_conn->lport != 0 && - UDPBUF->destport == uip_udp_conn->lport && - (uip_udp_conn->rport == 0 || - UDPBUF->srcport == uip_udp_conn->rport) && - (uip_ipaddr_cmp(uip_udp_conn->ripaddr, all_zeroes_addr) || - uip_ipaddr_cmp(uip_udp_conn->ripaddr, all_ones_addr) || - uip_ipaddr_cmp(BUF->srcipaddr, uip_udp_conn->ripaddr))) { - goto udp_found; - } - } - UIP_LOG("udp: no matching connection found"); - goto drop; - - udp_found: - uip_conn = NULL; - uip_flags = UIP_NEWDATA; - uip_sappdata = uip_appdata = &uip_buf[UIP_LLH_LEN + UIP_IPUDPH_LEN]; - uip_slen = 0; - UIP_UDP_APPCALL(); - udp_send: - if(uip_slen == 0) { - goto drop; - } - uip_len = uip_slen + UIP_IPUDPH_LEN; - -#if UIP_CONF_IPV6 - /* For IPv6, the IP length field does not include the IPv6 IP header - length. */ - BUF->len[0] = ((uip_len - UIP_IPH_LEN) >> 8); - BUF->len[1] = ((uip_len - UIP_IPH_LEN) & 0xff); -#else /* UIP_CONF_IPV6 */ - BUF->len[0] = (uip_len >> 8); - BUF->len[1] = (uip_len & 0xff); -#endif /* UIP_CONF_IPV6 */ - - BUF->ttl = uip_udp_conn->ttl; - BUF->proto = UIP_PROTO_UDP; - - UDPBUF->udplen = HTONS(uip_slen + UIP_UDPH_LEN); - UDPBUF->udpchksum = 0; - - BUF->srcport = uip_udp_conn->lport; - BUF->destport = uip_udp_conn->rport; - - uip_ipaddr_copy(BUF->srcipaddr, uip_hostaddr); - uip_ipaddr_copy(BUF->destipaddr, uip_udp_conn->ripaddr); - - uip_appdata = &uip_buf[UIP_LLH_LEN + UIP_IPTCPH_LEN]; - -#if UIP_UDP_CHECKSUMS - /* Calculate UDP checksum. */ - UDPBUF->udpchksum = ~(uip_udpchksum()); - if(UDPBUF->udpchksum == 0) { - UDPBUF->udpchksum = 0xffff; - } -#endif /* UIP_UDP_CHECKSUMS */ - - goto ip_send_nolen; -#endif /* UIP_UDP */ - - /* TCP input processing. */ - tcp_input: - UIP_STAT(++uip_stat.tcp.recv); - - /* Start of TCP input header processing code. */ - - if(uip_tcpchksum() != 0xffff) { /* Compute and check the TCP - checksum. */ - UIP_STAT(++uip_stat.tcp.drop); - UIP_STAT(++uip_stat.tcp.chkerr); - UIP_LOG("tcp: bad checksum."); - goto drop; - } - - - /* Demultiplex this segment. */ - /* First check any active connections. */ - for(uip_connr = &uip_conns[0]; uip_connr <= &uip_conns[UIP_CONNS - 1]; - ++uip_connr) { - if(uip_connr->tcpstateflags != UIP_CLOSED && - BUF->destport == uip_connr->lport && - BUF->srcport == uip_connr->rport && - uip_ipaddr_cmp(BUF->srcipaddr, uip_connr->ripaddr)) { - goto found; - } - } - - /* If we didn't find and active connection that expected the packet, - either this packet is an old duplicate, or this is a SYN packet - destined for a connection in LISTEN. If the SYN flag isn't set, - it is an old packet and we send a RST. */ - if((BUF->flags & TCP_CTL) != TCP_SYN) { - goto reset; - } - - tmp16 = BUF->destport; - /* Next, check listening connections. */ - for(c = 0; c < UIP_LISTENPORTS; ++c) { - if(tmp16 == uip_listenports[c]) - goto found_listen; - } - - /* No matching connection found, so we send a RST packet. */ - UIP_STAT(++uip_stat.tcp.synrst); - reset: - - /* We do not send resets in response to resets. */ - if(BUF->flags & TCP_RST) { - goto drop; - } - - UIP_STAT(++uip_stat.tcp.rst); - - BUF->flags = TCP_RST | TCP_ACK; - uip_len = UIP_IPTCPH_LEN; - BUF->tcpoffset = 5 << 4; - - /* Flip the seqno and ackno fields in the TCP header. */ - c = BUF->seqno[3]; - BUF->seqno[3] = BUF->ackno[3]; - BUF->ackno[3] = c; - - c = BUF->seqno[2]; - BUF->seqno[2] = BUF->ackno[2]; - BUF->ackno[2] = c; - - c = BUF->seqno[1]; - BUF->seqno[1] = BUF->ackno[1]; - BUF->ackno[1] = c; - - c = BUF->seqno[0]; - BUF->seqno[0] = BUF->ackno[0]; - BUF->ackno[0] = c; - - /* We also have to increase the sequence number we are - acknowledging. If the least significant byte overflowed, we need - to propagate the carry to the other bytes as well. */ - if(++BUF->ackno[3] == 0) { - if(++BUF->ackno[2] == 0) { - if(++BUF->ackno[1] == 0) { - ++BUF->ackno[0]; - } - } - } - - /* Swap port numbers. */ - tmp16 = BUF->srcport; - BUF->srcport = BUF->destport; - BUF->destport = tmp16; - - /* Swap IP addresses. */ - uip_ipaddr_copy(BUF->destipaddr, BUF->srcipaddr); - uip_ipaddr_copy(BUF->srcipaddr, uip_hostaddr); - - /* And send out the RST packet! */ - goto tcp_send_noconn; - - /* This label will be jumped to if we matched the incoming packet - with a connection in LISTEN. In that case, we should create a new - connection and send a SYNACK in return. */ - found_listen: - /* First we check if there are any connections avaliable. Unused - connections are kept in the same table as used connections, but - unused ones have the tcpstate set to CLOSED. Also, connections in - TIME_WAIT are kept track of and we'll use the oldest one if no - CLOSED connections are found. Thanks to Eddie C. Dost for a very - nice algorithm for the TIME_WAIT search. */ - uip_connr = 0; - for(c = 0; c < UIP_CONNS; ++c) { - if(uip_conns[c].tcpstateflags == UIP_CLOSED) { - uip_connr = &uip_conns[c]; - break; - } - if(uip_conns[c].tcpstateflags == UIP_TIME_WAIT) { - if(uip_connr == 0 || - uip_conns[c].timer > uip_connr->timer) { - uip_connr = &uip_conns[c]; - } - } - } - - if(uip_connr == 0) { - /* All connections are used already, we drop packet and hope that - the remote end will retransmit the packet at a time when we - have more spare connections. */ - UIP_STAT(++uip_stat.tcp.syndrop); - UIP_LOG("tcp: found no unused connections."); - goto drop; - } - uip_conn = uip_connr; - - /* Fill in the necessary fields for the new connection. */ - uip_connr->rto = uip_connr->timer = UIP_RTO; - uip_connr->sa = 0; - uip_connr->sv = 4; - uip_connr->nrtx = 0; - uip_connr->lport = BUF->destport; - uip_connr->rport = BUF->srcport; - uip_ipaddr_copy(uip_connr->ripaddr, BUF->srcipaddr); - uip_connr->tcpstateflags = UIP_SYN_RCVD; - - uip_connr->snd_nxt[0] = iss[0]; - uip_connr->snd_nxt[1] = iss[1]; - uip_connr->snd_nxt[2] = iss[2]; - uip_connr->snd_nxt[3] = iss[3]; - uip_connr->len = 1; - - /* rcv_nxt should be the seqno from the incoming packet + 1. */ - uip_connr->rcv_nxt[3] = BUF->seqno[3]; - uip_connr->rcv_nxt[2] = BUF->seqno[2]; - uip_connr->rcv_nxt[1] = BUF->seqno[1]; - uip_connr->rcv_nxt[0] = BUF->seqno[0]; - uip_add_rcv_nxt(1); - - /* Parse the TCP MSS option, if present. */ - if((BUF->tcpoffset & 0xf0) > 0x50) { - for(c = 0; c < ((BUF->tcpoffset >> 4) - 5) << 2 ;) { - opt = uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + c]; - if(opt == TCP_OPT_END) { - /* End of options. */ - break; - } else if(opt == TCP_OPT_NOOP) { - ++c; - /* NOP option. */ - } else if(opt == TCP_OPT_MSS && - uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == TCP_OPT_MSS_LEN) { - /* An MSS option with the right option length. */ - tmp16 = ((u16_t)uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 2 + c] << 8) | - (u16_t)uip_buf[UIP_IPTCPH_LEN + UIP_LLH_LEN + 3 + c]; - uip_connr->initialmss = uip_connr->mss = - tmp16 > UIP_TCP_MSS? UIP_TCP_MSS: tmp16; - - /* And we are done processing options. */ - break; - } else { - /* All other options have a length field, so that we easily - can skip past them. */ - if(uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0) { - /* If the length field is zero, the options are malformed - and we don't process them further. */ - break; - } - c += uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c]; - } - } - } - - /* Our response will be a SYNACK. */ -#if UIP_ACTIVE_OPEN - tcp_send_synack: - BUF->flags = TCP_ACK; - - tcp_send_syn: - BUF->flags |= TCP_SYN; -#else /* UIP_ACTIVE_OPEN */ - tcp_send_synack: - BUF->flags = TCP_SYN | TCP_ACK; -#endif /* UIP_ACTIVE_OPEN */ - - /* We send out the TCP Maximum Segment Size option with our - SYNACK. */ - BUF->optdata[0] = TCP_OPT_MSS; - BUF->optdata[1] = TCP_OPT_MSS_LEN; - BUF->optdata[2] = (UIP_TCP_MSS) / 256; - BUF->optdata[3] = (UIP_TCP_MSS) & 255; - uip_len = UIP_IPTCPH_LEN + TCP_OPT_MSS_LEN; - BUF->tcpoffset = ((UIP_TCPH_LEN + TCP_OPT_MSS_LEN) / 4) << 4; - goto tcp_send; - - /* This label will be jumped to if we found an active connection. */ - found: - uip_conn = uip_connr; - uip_flags = 0; - /* We do a very naive form of TCP reset processing; we just accept - any RST and kill our connection. We should in fact check if the - sequence number of this reset is wihtin our advertised window - before we accept the reset. */ - if(BUF->flags & TCP_RST) { - uip_connr->tcpstateflags = UIP_CLOSED; - UIP_LOG("tcp: got reset, aborting connection."); - uip_flags = UIP_ABORT; - UIP_APPCALL(); - goto drop; - } - /* Calculated the length of the data, if the application has sent - any data to us. */ - c = (BUF->tcpoffset >> 4) << 2; - /* uip_len will contain the length of the actual TCP data. This is - calculated by subtracing the length of the TCP header (in - c) and the length of the IP header (20 bytes). */ - uip_len = uip_len - c - UIP_IPH_LEN; - - /* First, check if the sequence number of the incoming packet is - what we're expecting next. If not, we send out an ACK with the - correct numbers in. */ - if(!(((uip_connr->tcpstateflags & UIP_TS_MASK) == UIP_SYN_SENT) && - ((BUF->flags & TCP_CTL) == (TCP_SYN | TCP_ACK)))) { - if((uip_len > 0 || ((BUF->flags & (TCP_SYN | TCP_FIN)) != 0)) && - (BUF->seqno[0] != uip_connr->rcv_nxt[0] || - BUF->seqno[1] != uip_connr->rcv_nxt[1] || - BUF->seqno[2] != uip_connr->rcv_nxt[2] || - BUF->seqno[3] != uip_connr->rcv_nxt[3])) { - goto tcp_send_ack; - } - } - - /* Next, check if the incoming segment acknowledges any outstanding - data. If so, we update the sequence number, reset the length of - the outstanding data, calculate RTT estimations, and reset the - retransmission timer. */ - if((BUF->flags & TCP_ACK) && uip_outstanding(uip_connr)) { - uip_add32(uip_connr->snd_nxt, uip_connr->len); - - if(BUF->ackno[0] == uip_acc32[0] && - BUF->ackno[1] == uip_acc32[1] && - BUF->ackno[2] == uip_acc32[2] && - BUF->ackno[3] == uip_acc32[3]) { - /* Update sequence number. */ - uip_connr->snd_nxt[0] = uip_acc32[0]; - uip_connr->snd_nxt[1] = uip_acc32[1]; - uip_connr->snd_nxt[2] = uip_acc32[2]; - uip_connr->snd_nxt[3] = uip_acc32[3]; - - - /* Do RTT estimation, unless we have done retransmissions. */ - if(uip_connr->nrtx == 0) { - signed char m; - m = uip_connr->rto - uip_connr->timer; - /* This is taken directly from VJs original code in his paper */ - m = m - (uip_connr->sa >> 3); - uip_connr->sa += m; - if(m < 0) { - m = -m; - } - m = m - (uip_connr->sv >> 2); - uip_connr->sv += m; - uip_connr->rto = (uip_connr->sa >> 3) + uip_connr->sv; - - } - /* Set the acknowledged flag. */ - uip_flags = UIP_ACKDATA; - /* Reset the retransmission timer. */ - uip_connr->timer = uip_connr->rto; - - /* Reset length of outstanding data. */ - uip_connr->len = 0; - } - - } - - /* Do different things depending on in what state the connection is. */ - switch(uip_connr->tcpstateflags & UIP_TS_MASK) { - /* CLOSED and LISTEN are not handled here. CLOSE_WAIT is not - implemented, since we force the application to close when the - peer sends a FIN (hence the application goes directly from - ESTABLISHED to LAST_ACK). */ - case UIP_SYN_RCVD: - /* In SYN_RCVD we have sent out a SYNACK in response to a SYN, and - we are waiting for an ACK that acknowledges the data we sent - out the last time. Therefore, we want to have the UIP_ACKDATA - flag set. If so, we enter the ESTABLISHED state. */ - if(uip_flags & UIP_ACKDATA) { - uip_connr->tcpstateflags = UIP_ESTABLISHED; - uip_flags = UIP_CONNECTED; - uip_connr->len = 0; - if(uip_len > 0) { - uip_flags |= UIP_NEWDATA; - uip_add_rcv_nxt(uip_len); - } - uip_slen = 0; - UIP_APPCALL(); - goto appsend; - } - goto drop; -#if UIP_ACTIVE_OPEN - case UIP_SYN_SENT: - /* In SYN_SENT, we wait for a SYNACK that is sent in response to - our SYN. The rcv_nxt is set to sequence number in the SYNACK - plus one, and we send an ACK. We move into the ESTABLISHED - state. */ - if((uip_flags & UIP_ACKDATA) && - (BUF->flags & TCP_CTL) == (TCP_SYN | TCP_ACK)) { - - /* Parse the TCP MSS option, if present. */ - if((BUF->tcpoffset & 0xf0) > 0x50) { - for(c = 0; c < ((BUF->tcpoffset >> 4) - 5) << 2 ;) { - opt = uip_buf[UIP_IPTCPH_LEN + UIP_LLH_LEN + c]; - if(opt == TCP_OPT_END) { - /* End of options. */ - break; - } else if(opt == TCP_OPT_NOOP) { - ++c; - /* NOP option. */ - } else if(opt == TCP_OPT_MSS && - uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == TCP_OPT_MSS_LEN) { - /* An MSS option with the right option length. */ - tmp16 = (uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 2 + c] << 8) | - uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 3 + c]; - uip_connr->initialmss = - uip_connr->mss = tmp16 > UIP_TCP_MSS? UIP_TCP_MSS: tmp16; - - /* And we are done processing options. */ - break; - } else { - /* All other options have a length field, so that we easily - can skip past them. */ - if(uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0) { - /* If the length field is zero, the options are malformed - and we don't process them further. */ - break; - } - c += uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c]; - } - } - } - uip_connr->tcpstateflags = UIP_ESTABLISHED; - uip_connr->rcv_nxt[0] = BUF->seqno[0]; - uip_connr->rcv_nxt[1] = BUF->seqno[1]; - uip_connr->rcv_nxt[2] = BUF->seqno[2]; - uip_connr->rcv_nxt[3] = BUF->seqno[3]; - uip_add_rcv_nxt(1); - uip_flags = UIP_CONNECTED | UIP_NEWDATA; - uip_connr->len = 0; - uip_len = 0; - uip_slen = 0; - UIP_APPCALL(); - goto appsend; - } - /* Inform the application that the connection failed */ - uip_flags = UIP_ABORT; - UIP_APPCALL(); - /* The connection is closed after we send the RST */ - uip_conn->tcpstateflags = UIP_CLOSED; - goto reset; -#endif /* UIP_ACTIVE_OPEN */ - - case UIP_ESTABLISHED: - /* In the ESTABLISHED state, we call upon the application to feed - data into the uip_buf. If the UIP_ACKDATA flag is set, the - application should put new data into the buffer, otherwise we are - retransmitting an old segment, and the application should put that - data into the buffer. - - If the incoming packet is a FIN, we should close the connection on - this side as well, and we send out a FIN and enter the LAST_ACK - state. We require that there is no outstanding data; otherwise the - sequence numbers will be screwed up. */ - - if(BUF->flags & TCP_FIN && !(uip_connr->tcpstateflags & UIP_STOPPED)) { - if(uip_outstanding(uip_connr)) { - goto drop; - } - uip_add_rcv_nxt(1 + uip_len); - uip_flags |= UIP_CLOSE; - if(uip_len > 0) { - uip_flags |= UIP_NEWDATA; - } - UIP_APPCALL(); - uip_connr->len = 1; - uip_connr->tcpstateflags = UIP_LAST_ACK; - uip_connr->nrtx = 0; - tcp_send_finack: - BUF->flags = TCP_FIN | TCP_ACK; - goto tcp_send_nodata; - } - - /* Check the URG flag. If this is set, the segment carries urgent - data that we must pass to the application. */ - if((BUF->flags & TCP_URG) != 0) { -#if UIP_URGDATA > 0 - uip_urglen = (BUF->urgp[0] << 8) | BUF->urgp[1]; - if(uip_urglen > uip_len) { - /* There is more urgent data in the next segment to come. */ - uip_urglen = uip_len; - } - uip_add_rcv_nxt(uip_urglen); - uip_len -= uip_urglen; - uip_urgdata = uip_appdata; - uip_appdata += uip_urglen; - } else { - uip_urglen = 0; -#else /* UIP_URGDATA > 0 */ - uip_appdata = ((char *)uip_appdata) + ((BUF->urgp[0] << 8) | BUF->urgp[1]); - uip_len -= (BUF->urgp[0] << 8) | BUF->urgp[1]; -#endif /* UIP_URGDATA > 0 */ - } - - /* If uip_len > 0 we have TCP data in the packet, and we flag this - by setting the UIP_NEWDATA flag and update the sequence number - we acknowledge. If the application has stopped the dataflow - using uip_stop(), we must not accept any data packets from the - remote host. */ - if(uip_len > 0 && !(uip_connr->tcpstateflags & UIP_STOPPED)) { - uip_flags |= UIP_NEWDATA; - uip_add_rcv_nxt(uip_len); - } - - /* Check if the available buffer space advertised by the other end - is smaller than the initial MSS for this connection. If so, we - set the current MSS to the window size to ensure that the - application does not send more data than the other end can - handle. - - If the remote host advertises a zero window, we set the MSS to - the initial MSS so that the application will send an entire MSS - of data. This data will not be acknowledged by the receiver, - and the application will retransmit it. This is called the - "persistent timer" and uses the retransmission mechanim. - */ - tmp16 = ((u16_t)BUF->wnd[0] << 8) + (u16_t)BUF->wnd[1]; - if(tmp16 > uip_connr->initialmss || - tmp16 == 0) { - tmp16 = uip_connr->initialmss; - } - uip_connr->mss = tmp16; - - /* If this packet constitutes an ACK for outstanding data (flagged - by the UIP_ACKDATA flag, we should call the application since it - might want to send more data. If the incoming packet had data - from the peer (as flagged by the UIP_NEWDATA flag), the - application must also be notified. - - When the application is called, the global variable uip_len - contains the length of the incoming data. The application can - access the incoming data through the global pointer - uip_appdata, which usually points UIP_IPTCPH_LEN + UIP_LLH_LEN - bytes into the uip_buf array. - - If the application wishes to send any data, this data should be - put into the uip_appdata and the length of the data should be - put into uip_len. If the application don't have any data to - send, uip_len must be set to 0. */ - if(uip_flags & (UIP_NEWDATA | UIP_ACKDATA)) { - uip_slen = 0; - UIP_APPCALL(); - - appsend: - - if(uip_flags & UIP_ABORT) { - uip_slen = 0; - uip_connr->tcpstateflags = UIP_CLOSED; - BUF->flags = TCP_RST | TCP_ACK; - goto tcp_send_nodata; - } - - if(uip_flags & UIP_CLOSE) { - uip_slen = 0; - uip_connr->len = 1; - uip_connr->tcpstateflags = UIP_FIN_WAIT_1; - uip_connr->nrtx = 0; - BUF->flags = TCP_FIN | TCP_ACK; - goto tcp_send_nodata; - } - - /* If uip_slen > 0, the application has data to be sent. */ - if(uip_slen > 0) { - - /* If the connection has acknowledged data, the contents of - the ->len variable should be discarded. */ - if((uip_flags & UIP_ACKDATA) != 0) { - uip_connr->len = 0; - } - - /* If the ->len variable is non-zero the connection has - already data in transit and cannot send anymore right - now. */ - if(uip_connr->len == 0) { - - /* The application cannot send more than what is allowed by - the mss (the minumum of the MSS and the available - window). */ - if(uip_slen > uip_connr->mss) { - uip_slen = uip_connr->mss; - } - - /* Remember how much data we send out now so that we know - when everything has been acknowledged. */ - uip_connr->len = uip_slen; - } else { - - /* If the application already had unacknowledged data, we - make sure that the application does not send (i.e., - retransmit) out more than it previously sent out. */ - uip_slen = uip_connr->len; - } - } - uip_connr->nrtx = 0; - apprexmit: - uip_appdata = uip_sappdata; - - /* If the application has data to be sent, or if the incoming - packet had new data in it, we must send out a packet. */ - if(uip_slen > 0 && uip_connr->len > 0) { - /* Add the length of the IP and TCP headers. */ - uip_len = uip_connr->len + UIP_TCPIP_HLEN; - /* We always set the ACK flag in response packets. */ - BUF->flags = TCP_ACK | TCP_PSH; - /* Send the packet. */ - goto tcp_send_noopts; - } - /* If there is no data to send, just send out a pure ACK if - there is newdata. */ - if(uip_flags & UIP_NEWDATA) { - uip_len = UIP_TCPIP_HLEN; - BUF->flags = TCP_ACK; - goto tcp_send_noopts; - } - } - goto drop; - case UIP_LAST_ACK: - /* We can close this connection if the peer has acknowledged our - FIN. This is indicated by the UIP_ACKDATA flag. */ - if(uip_flags & UIP_ACKDATA) { - uip_connr->tcpstateflags = UIP_CLOSED; - uip_flags = UIP_CLOSE; - UIP_APPCALL(); - } - break; - - case UIP_FIN_WAIT_1: - /* The application has closed the connection, but the remote host - hasn't closed its end yet. Thus we do nothing but wait for a - FIN from the other side. */ - if(uip_len > 0) { - uip_add_rcv_nxt(uip_len); - } - if(BUF->flags & TCP_FIN) { - if(uip_flags & UIP_ACKDATA) { - uip_connr->tcpstateflags = UIP_TIME_WAIT; - uip_connr->timer = 0; - uip_connr->len = 0; - } else { - uip_connr->tcpstateflags = UIP_CLOSING; - } - uip_add_rcv_nxt(1); - uip_flags = UIP_CLOSE; - UIP_APPCALL(); - goto tcp_send_ack; - } else if(uip_flags & UIP_ACKDATA) { - uip_connr->tcpstateflags = UIP_FIN_WAIT_2; - uip_connr->len = 0; - goto drop; - } - if(uip_len > 0) { - goto tcp_send_ack; - } - goto drop; - - case UIP_FIN_WAIT_2: - if(uip_len > 0) { - uip_add_rcv_nxt(uip_len); - } - if(BUF->flags & TCP_FIN) { - uip_connr->tcpstateflags = UIP_TIME_WAIT; - uip_connr->timer = 0; - uip_add_rcv_nxt(1); - uip_flags = UIP_CLOSE; - UIP_APPCALL(); - goto tcp_send_ack; - } - if(uip_len > 0) { - goto tcp_send_ack; - } - goto drop; - - case UIP_TIME_WAIT: - goto tcp_send_ack; - - case UIP_CLOSING: - if(uip_flags & UIP_ACKDATA) { - uip_connr->tcpstateflags = UIP_TIME_WAIT; - uip_connr->timer = 0; - } - } - goto drop; - - - /* We jump here when we are ready to send the packet, and just want - to set the appropriate TCP sequence numbers in the TCP header. */ - tcp_send_ack: - BUF->flags = TCP_ACK; - tcp_send_nodata: - uip_len = UIP_IPTCPH_LEN; - tcp_send_noopts: - BUF->tcpoffset = (UIP_TCPH_LEN / 4) << 4; - tcp_send: - /* We're done with the input processing. We are now ready to send a - reply. Our job is to fill in all the fields of the TCP and IP - headers before calculating the checksum and finally send the - packet. */ - BUF->ackno[0] = uip_connr->rcv_nxt[0]; - BUF->ackno[1] = uip_connr->rcv_nxt[1]; - BUF->ackno[2] = uip_connr->rcv_nxt[2]; - BUF->ackno[3] = uip_connr->rcv_nxt[3]; - - BUF->seqno[0] = uip_connr->snd_nxt[0]; - BUF->seqno[1] = uip_connr->snd_nxt[1]; - BUF->seqno[2] = uip_connr->snd_nxt[2]; - BUF->seqno[3] = uip_connr->snd_nxt[3]; - - BUF->proto = UIP_PROTO_TCP; - - BUF->srcport = uip_connr->lport; - BUF->destport = uip_connr->rport; - - uip_ipaddr_copy(BUF->srcipaddr, uip_hostaddr); - uip_ipaddr_copy(BUF->destipaddr, uip_connr->ripaddr); - - if(uip_connr->tcpstateflags & UIP_STOPPED) { - /* If the connection has issued uip_stop(), we advertise a zero - window so that the remote host will stop sending data. */ - BUF->wnd[0] = BUF->wnd[1] = 0; - } else { - BUF->wnd[0] = ((UIP_RECEIVE_WINDOW) >> 8); - BUF->wnd[1] = ((UIP_RECEIVE_WINDOW) & 0xff); - } - - tcp_send_noconn: - BUF->ttl = UIP_TTL; -#if UIP_CONF_IPV6 - /* For IPv6, the IP length field does not include the IPv6 IP header - length. */ - BUF->len[0] = ((uip_len - UIP_IPH_LEN) >> 8); - BUF->len[1] = ((uip_len - UIP_IPH_LEN) & 0xff); -#else /* UIP_CONF_IPV6 */ - BUF->len[0] = (uip_len >> 8); - BUF->len[1] = (uip_len & 0xff); -#endif /* UIP_CONF_IPV6 */ - - BUF->urgp[0] = BUF->urgp[1] = 0; - - /* Calculate TCP checksum. */ - BUF->tcpchksum = 0; - BUF->tcpchksum = ~(uip_tcpchksum()); - - ip_send_nolen: - -#if UIP_CONF_IPV6 - BUF->vtc = 0x60; - BUF->tcflow = 0x00; - BUF->flow = 0x00; -#else /* UIP_CONF_IPV6 */ - BUF->vhl = 0x45; - BUF->tos = 0; - BUF->ipoffset[0] = BUF->ipoffset[1] = 0; - ++ipid; - BUF->ipid[0] = ipid >> 8; - BUF->ipid[1] = ipid & 0xff; - /* Calculate IP checksum. */ - BUF->ipchksum = 0; - BUF->ipchksum = ~(uip_ipchksum()); - DEBUG_PRINTF("uip ip_send_nolen: chkecum 0x%04x\n", uip_ipchksum()); -#endif /* UIP_CONF_IPV6 */ - - UIP_STAT(++uip_stat.tcp.sent); - send: - DEBUG_PRINTF("Sending packet with length %d (%d)\n", uip_len, - (BUF->len[0] << 8) | BUF->len[1]); - - UIP_STAT(++uip_stat.ip.sent); - /* Return and let the caller do the actual transmission. */ - uip_flags = 0; - return; - drop: - uip_len = 0; - uip_flags = 0; - return; -} -/*---------------------------------------------------------------------------*/ -u16_t -htons(u16_t val) -{ - return HTONS(val); -} -/*---------------------------------------------------------------------------*/ -void -uip_send(const void *data, int len) -{ - if(len > 0) { - uip_slen = len; - if(data != uip_sappdata) { - memcpy(uip_sappdata, (data), uip_slen); - } - } -} -/** @} */ diff --git a/Demo/Common/ethernet/uIP/uip-1.0/uip/uip.h b/Demo/Common/ethernet/uIP/uip-1.0/uip/uip.h deleted file mode 100644 index 92f3ff393..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/uip/uip.h +++ /dev/null @@ -1,1601 +0,0 @@ - -/** - * \addtogroup uip - * @{ - */ - -/** - * \file - * Header file for the uIP TCP/IP stack. - * \author Adam Dunkels - * - * The uIP TCP/IP stack header file contains definitions for a number - * of C macros that are used by uIP programs as well as internal uIP - * structures, TCP/IP header structures and function declarations. - * - */ - - -/* - * Copyright (c) 2001-2003, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: uip.h,v 1.40 2006/06/08 07:12:07 adam Exp $ - * - */ - -#ifndef __UIP_H__ -#define __UIP_H__ - -#include "uipopt.h" - -/** - * Repressentation of an IP address. - * - */ -typedef u16_t uip_ip4addr_t[2]; -typedef u16_t uip_ip6addr_t[8]; -#if UIP_CONF_IPV6 -typedef uip_ip6addr_t uip_ipaddr_t; -#else /* UIP_CONF_IPV6 */ -typedef uip_ip4addr_t uip_ipaddr_t; -#endif /* UIP_CONF_IPV6 */ - -/*---------------------------------------------------------------------------*/ -/* First, the functions that should be called from the - * system. Initialization, the periodic timer and incoming packets are - * handled by the following three functions. - */ - -/** - * \defgroup uipconffunc uIP configuration functions - * @{ - * - * The uIP configuration functions are used for setting run-time - * parameters in uIP such as IP addresses. - */ - -/** - * Set the IP address of this host. - * - * The IP address is represented as a 4-byte array where the first - * octet of the IP address is put in the first member of the 4-byte - * array. - * - * Example: - \code - - uip_ipaddr_t addr; - - uip_ipaddr(&addr, 192,168,1,2); - uip_sethostaddr(&addr); - - \endcode - * \param addr A pointer to an IP address of type uip_ipaddr_t; - * - * \sa uip_ipaddr() - * - * \hideinitializer - */ -#define uip_sethostaddr(addr) uip_ipaddr_copy(uip_hostaddr, (addr)) - -/** - * Get the IP address of this host. - * - * The IP address is represented as a 4-byte array where the first - * octet of the IP address is put in the first member of the 4-byte - * array. - * - * Example: - \code - uip_ipaddr_t hostaddr; - - uip_gethostaddr(&hostaddr); - \endcode - * \param addr A pointer to a uip_ipaddr_t variable that will be - * filled in with the currently configured IP address. - * - * \hideinitializer - */ -#define uip_gethostaddr(addr) uip_ipaddr_copy((addr), uip_hostaddr) - -/** - * Set the default router's IP address. - * - * \param addr A pointer to a uip_ipaddr_t variable containing the IP - * address of the default router. - * - * \sa uip_ipaddr() - * - * \hideinitializer - */ -#define uip_setdraddr(addr) uip_ipaddr_copy(uip_draddr, (addr)) - -/** - * Set the netmask. - * - * \param addr A pointer to a uip_ipaddr_t variable containing the IP - * address of the netmask. - * - * \sa uip_ipaddr() - * - * \hideinitializer - */ -#define uip_setnetmask(addr) uip_ipaddr_copy(uip_netmask, (addr)) - - -/** - * Get the default router's IP address. - * - * \param addr A pointer to a uip_ipaddr_t variable that will be - * filled in with the IP address of the default router. - * - * \hideinitializer - */ -#define uip_getdraddr(addr) uip_ipaddr_copy((addr), uip_draddr) - -/** - * Get the netmask. - * - * \param addr A pointer to a uip_ipaddr_t variable that will be - * filled in with the value of the netmask. - * - * \hideinitializer - */ -#define uip_getnetmask(addr) uip_ipaddr_copy((addr), uip_netmask) - -/** @} */ - -/** - * \defgroup uipinit uIP initialization functions - * @{ - * - * The uIP initialization functions are used for booting uIP. - */ - -/** - * uIP initialization function. - * - * This function should be called at boot up to initilize the uIP - * TCP/IP stack. - */ -void uip_init(void); - -/** - * uIP initialization function. - * - * This function may be used at boot time to set the initial ip_id. - */ -void uip_setipid(u16_t id); - -/** @} */ - -/** - * \defgroup uipdevfunc uIP device driver functions - * @{ - * - * These functions are used by a network device driver for interacting - * with uIP. - */ - -/** - * Process an incoming packet. - * - * This function should be called when the device driver has received - * a packet from the network. The packet from the device driver must - * be present in the uip_buf buffer, and the length of the packet - * should be placed in the uip_len variable. - * - * When the function returns, there may be an outbound packet placed - * in the uip_buf packet buffer. If so, the uip_len variable is set to - * the length of the packet. If no packet is to be sent out, the - * uip_len variable is set to 0. - * - * The usual way of calling the function is presented by the source - * code below. - \code - uip_len = devicedriver_poll(); - if(uip_len > 0) { - uip_input(); - if(uip_len > 0) { - devicedriver_send(); - } - } - \endcode - * - * \note If you are writing a uIP device driver that needs ARP - * (Address Resolution Protocol), e.g., when running uIP over - * Ethernet, you will need to call the uIP ARP code before calling - * this function: - \code - #define BUF ((struct uip_eth_hdr *)&uip_buf[0]) - uip_len = ethernet_devicedrver_poll(); - if(uip_len > 0) { - if(BUF->type == HTONS(UIP_ETHTYPE_IP)) { - uip_arp_ipin(); - uip_input(); - if(uip_len > 0) { - uip_arp_out(); - ethernet_devicedriver_send(); - } - } else if(BUF->type == HTONS(UIP_ETHTYPE_ARP)) { - uip_arp_arpin(); - if(uip_len > 0) { - ethernet_devicedriver_send(); - } - } - \endcode - * - * \hideinitializer - */ -#define uip_input() uip_process(UIP_DATA) - -/** - * Periodic processing for a connection identified by its number. - * - * This function does the necessary periodic processing (timers, - * polling) for a uIP TCP conneciton, and should be called when the - * periodic uIP timer goes off. It should be called for every - * connection, regardless of whether they are open of closed. - * - * When the function returns, it may have an outbound packet waiting - * for service in the uIP packet buffer, and if so the uip_len - * variable is set to a value larger than zero. The device driver - * should be called to send out the packet. - * - * The ususal way of calling the function is through a for() loop like - * this: - \code - for(i = 0; i < UIP_CONNS; ++i) { - uip_periodic(i); - if(uip_len > 0) { - devicedriver_send(); - } - } - \endcode - * - * \note If you are writing a uIP device driver that needs ARP - * (Address Resolution Protocol), e.g., when running uIP over - * Ethernet, you will need to call the uip_arp_out() function before - * calling the device driver: - \code - for(i = 0; i < UIP_CONNS; ++i) { - uip_periodic(i); - if(uip_len > 0) { - uip_arp_out(); - ethernet_devicedriver_send(); - } - } - \endcode - * - * \param conn The number of the connection which is to be periodically polled. - * - * \hideinitializer - */ -#define uip_periodic(conn) do { uip_conn = &uip_conns[conn]; \ - uip_process(UIP_TIMER); } while (0) - -/** - * - * - */ -#define uip_conn_active(conn) (uip_conns[conn].tcpstateflags != UIP_CLOSED) - -/** - * Perform periodic processing for a connection identified by a pointer - * to its structure. - * - * Same as uip_periodic() but takes a pointer to the actual uip_conn - * struct instead of an integer as its argument. This function can be - * used to force periodic processing of a specific connection. - * - * \param conn A pointer to the uip_conn struct for the connection to - * be processed. - * - * \hideinitializer - */ -#define uip_periodic_conn(conn) do { uip_conn = conn; \ - uip_process(UIP_TIMER); } while (0) - -/** - * Reuqest that a particular connection should be polled. - * - * Similar to uip_periodic_conn() but does not perform any timer - * processing. The application is polled for new data. - * - * \param conn A pointer to the uip_conn struct for the connection to - * be processed. - * - * \hideinitializer - */ -#define uip_poll_conn(conn) do { uip_conn = conn; \ - uip_process(UIP_POLL_REQUEST); } while (0) - - -#if UIP_UDP -/** - * Periodic processing for a UDP connection identified by its number. - * - * This function is essentially the same as uip_periodic(), but for - * UDP connections. It is called in a similar fashion as the - * uip_periodic() function: - \code - for(i = 0; i < UIP_UDP_CONNS; i++) { - uip_udp_periodic(i); - if(uip_len > 0) { - devicedriver_send(); - } - } - \endcode - * - * \note As for the uip_periodic() function, special care has to be - * taken when using uIP together with ARP and Ethernet: - \code - for(i = 0; i < UIP_UDP_CONNS; i++) { - uip_udp_periodic(i); - if(uip_len > 0) { - uip_arp_out(); - ethernet_devicedriver_send(); - } - } - \endcode - * - * \param conn The number of the UDP connection to be processed. - * - * \hideinitializer - */ -#define uip_udp_periodic(conn) do { uip_udp_conn = &uip_udp_conns[conn]; \ - uip_process(UIP_UDP_TIMER); } while (0) - -/** - * Periodic processing for a UDP connection identified by a pointer to - * its structure. - * - * Same as uip_udp_periodic() but takes a pointer to the actual - * uip_conn struct instead of an integer as its argument. This - * function can be used to force periodic processing of a specific - * connection. - * - * \param conn A pointer to the uip_udp_conn struct for the connection - * to be processed. - * - * \hideinitializer - */ -#define uip_udp_periodic_conn(conn) do { uip_udp_conn = conn; \ - uip_process(UIP_UDP_TIMER); } while (0) - - -#endif /* UIP_UDP */ - -/** - * The uIP packet buffer. - * - * The uip_buf array is used to hold incoming and outgoing - * packets. The device driver should place incoming data into this - * buffer. When sending data, the device driver should read the link - * level headers and the TCP/IP headers from this buffer. The size of - * the link level headers is configured by the UIP_LLH_LEN define. - * - * \note The application data need not be placed in this buffer, so - * the device driver must read it from the place pointed to by the - * uip_appdata pointer as illustrated by the following example: - \code - void - devicedriver_send(void) - { - hwsend(&uip_buf[0], UIP_LLH_LEN); - if(uip_len <= UIP_LLH_LEN + UIP_TCPIP_HLEN) { - hwsend(&uip_buf[UIP_LLH_LEN], uip_len - UIP_LLH_LEN); - } else { - hwsend(&uip_buf[UIP_LLH_LEN], UIP_TCPIP_HLEN); - hwsend(uip_appdata, uip_len - UIP_TCPIP_HLEN - UIP_LLH_LEN); - } - } - \endcode - */ -extern u8_t uip_buf[UIP_BUFSIZE+2]; - -/** @} */ - -/*---------------------------------------------------------------------------*/ -/* Functions that are used by the uIP application program. Opening and - * closing connections, sending and receiving data, etc. is all - * handled by the functions below. -*/ -/** - * \defgroup uipappfunc uIP application functions - * @{ - * - * Functions used by an application running of top of uIP. - */ - -/** - * Start listening to the specified port. - * - * \note Since this function expects the port number in network byte - * order, a conversion using HTONS() or htons() is necessary. - * - \code - uip_listen(HTONS(80)); - \endcode - * - * \param port A 16-bit port number in network byte order. - */ -void uip_listen(u16_t port); - -/** - * Stop listening to the specified port. - * - * \note Since this function expects the port number in network byte - * order, a conversion using HTONS() or htons() is necessary. - * - \code - uip_unlisten(HTONS(80)); - \endcode - * - * \param port A 16-bit port number in network byte order. - */ -void uip_unlisten(u16_t port); - -/** - * Connect to a remote host using TCP. - * - * This function is used to start a new connection to the specified - * port on the specied host. It allocates a new connection identifier, - * sets the connection to the SYN_SENT state and sets the - * retransmission timer to 0. This will cause a TCP SYN segment to be - * sent out the next time this connection is periodically processed, - * which usually is done within 0.5 seconds after the call to - * uip_connect(). - * - * \note This function is avaliable only if support for active open - * has been configured by defining UIP_ACTIVE_OPEN to 1 in uipopt.h. - * - * \note Since this function requires the port number to be in network - * byte order, a conversion using HTONS() or htons() is necessary. - * - \code - uip_ipaddr_t ipaddr; - - uip_ipaddr(&ipaddr, 192,168,1,2); - uip_connect(&ipaddr, HTONS(80)); - \endcode - * - * \param ripaddr The IP address of the remote hot. - * - * \param port A 16-bit port number in network byte order. - * - * \return A pointer to the uIP connection identifier for the new connection, - * or NULL if no connection could be allocated. - * - */ -struct uip_conn *uip_connect(uip_ipaddr_t *ripaddr, u16_t port); - - - -/** - * \internal - * - * Check if a connection has outstanding (i.e., unacknowledged) data. - * - * \param conn A pointer to the uip_conn structure for the connection. - * - * \hideinitializer - */ -#define uip_outstanding(conn) ((conn)->len) - -/** - * Send data on the current connection. - * - * This function is used to send out a single segment of TCP - * data. Only applications that have been invoked by uIP for event - * processing can send data. - * - * The amount of data that actually is sent out after a call to this - * funcion is determined by the maximum amount of data TCP allows. uIP - * will automatically crop the data so that only the appropriate - * amount of data is sent. The function uip_mss() can be used to query - * uIP for the amount of data that actually will be sent. - * - * \note This function does not guarantee that the sent data will - * arrive at the destination. If the data is lost in the network, the - * application will be invoked with the uip_rexmit() event being - * set. The application will then have to resend the data using this - * function. - * - * \param data A pointer to the data which is to be sent. - * - * \param len The maximum amount of data bytes to be sent. - * - * \hideinitializer - */ -void uip_send(const void *data, int len); - -/** - * The length of any incoming data that is currently avaliable (if avaliable) - * in the uip_appdata buffer. - * - * The test function uip_data() must first be used to check if there - * is any data available at all. - * - * \hideinitializer - */ -/*void uip_datalen(void);*/ -#define uip_datalen() uip_len - -/** - * The length of any out-of-band data (urgent data) that has arrived - * on the connection. - * - * \note The configuration parameter UIP_URGDATA must be set for this - * function to be enabled. - * - * \hideinitializer - */ -#define uip_urgdatalen() uip_urglen - -/** - * Close the current connection. - * - * This function will close the current connection in a nice way. - * - * \hideinitializer - */ -#define uip_close() (uip_flags = UIP_CLOSE) - -/** - * Abort the current connection. - * - * This function will abort (reset) the current connection, and is - * usually used when an error has occured that prevents using the - * uip_close() function. - * - * \hideinitializer - */ -#define uip_abort() (uip_flags = UIP_ABORT) - -/** - * Tell the sending host to stop sending data. - * - * This function will close our receiver's window so that we stop - * receiving data for the current connection. - * - * \hideinitializer - */ -#define uip_stop() (uip_conn->tcpstateflags |= UIP_STOPPED) - -/** - * Find out if the current connection has been previously stopped with - * uip_stop(). - * - * \hideinitializer - */ -#define uip_stopped(conn) ((conn)->tcpstateflags & UIP_STOPPED) - -/** - * Restart the current connection, if is has previously been stopped - * with uip_stop(). - * - * This function will open the receiver's window again so that we - * start receiving data for the current connection. - * - * \hideinitializer - */ -#define uip_restart() do { uip_flags |= UIP_NEWDATA; \ - uip_conn->tcpstateflags &= ~UIP_STOPPED; \ - } while(0) - - -/* uIP tests that can be made to determine in what state the current - connection is, and what the application function should do. */ - -/** - * Is the current connection a UDP connection? - * - * This function checks whether the current connection is a UDP connection. - * - * \hideinitializer - * - */ -#define uip_udpconnection() (uip_conn == NULL) - -/** - * Is new incoming data available? - * - * Will reduce to non-zero if there is new data for the application - * present at the uip_appdata pointer. The size of the data is - * avaliable through the uip_len variable. - * - * \hideinitializer - */ -#define uip_newdata() (uip_flags & UIP_NEWDATA) - -/** - * Has previously sent data been acknowledged? - * - * Will reduce to non-zero if the previously sent data has been - * acknowledged by the remote host. This means that the application - * can send new data. - * - * \hideinitializer - */ -#define uip_acked() (uip_flags & UIP_ACKDATA) - -/** - * Has the connection just been connected? - * - * Reduces to non-zero if the current connection has been connected to - * a remote host. This will happen both if the connection has been - * actively opened (with uip_connect()) or passively opened (with - * uip_listen()). - * - * \hideinitializer - */ -#define uip_connected() (uip_flags & UIP_CONNECTED) - -/** - * Has the connection been closed by the other end? - * - * Is non-zero if the connection has been closed by the remote - * host. The application may then do the necessary clean-ups. - * - * \hideinitializer - */ -#define uip_closed() (uip_flags & UIP_CLOSE) - -/** - * Has the connection been aborted by the other end? - * - * Non-zero if the current connection has been aborted (reset) by the - * remote host. - * - * \hideinitializer - */ -#define uip_aborted() (uip_flags & UIP_ABORT) - -/** - * Has the connection timed out? - * - * Non-zero if the current connection has been aborted due to too many - * retransmissions. - * - * \hideinitializer - */ -#define uip_timedout() (uip_flags & UIP_TIMEDOUT) - -/** - * Do we need to retransmit previously data? - * - * Reduces to non-zero if the previously sent data has been lost in - * the network, and the application should retransmit it. The - * application should send the exact same data as it did the last - * time, using the uip_send() function. - * - * \hideinitializer - */ -#define uip_rexmit() (uip_flags & UIP_REXMIT) - -/** - * Is the connection being polled by uIP? - * - * Is non-zero if the reason the application is invoked is that the - * current connection has been idle for a while and should be - * polled. - * - * The polling event can be used for sending data without having to - * wait for the remote host to send data. - * - * \hideinitializer - */ -#define uip_poll() (uip_flags & UIP_POLL) - -/** - * Get the initial maxium segment size (MSS) of the current - * connection. - * - * \hideinitializer - */ -#define uip_initialmss() (uip_conn->initialmss) - -/** - * Get the current maxium segment size that can be sent on the current - * connection. - * - * The current maxiumum segment size that can be sent on the - * connection is computed from the receiver's window and the MSS of - * the connection (which also is available by calling - * uip_initialmss()). - * - * \hideinitializer - */ -#define uip_mss() (uip_conn->mss) - -/** - * Set up a new UDP connection. - * - * This function sets up a new UDP connection. The function will - * automatically allocate an unused local port for the new - * connection. However, another port can be chosen by using the - * uip_udp_bind() call, after the uip_udp_new() function has been - * called. - * - * Example: - \code - uip_ipaddr_t addr; - struct uip_udp_conn *c; - - uip_ipaddr(&addr, 192,168,2,1); - c = uip_udp_new(&addr, HTONS(12345)); - if(c != NULL) { - uip_udp_bind(c, HTONS(12344)); - } - \endcode - * \param ripaddr The IP address of the remote host. - * - * \param rport The remote port number in network byte order. - * - * \return The uip_udp_conn structure for the new connection or NULL - * if no connection could be allocated. - */ -struct uip_udp_conn *uip_udp_new(uip_ipaddr_t *ripaddr, u16_t rport); - -/** - * Removed a UDP connection. - * - * \param conn A pointer to the uip_udp_conn structure for the connection. - * - * \hideinitializer - */ -#define uip_udp_remove(conn) (conn)->lport = 0 - -/** - * Bind a UDP connection to a local port. - * - * \param conn A pointer to the uip_udp_conn structure for the - * connection. - * - * \param port The local port number, in network byte order. - * - * \hideinitializer - */ -#define uip_udp_bind(conn, port) (conn)->lport = port - -/** - * Send a UDP datagram of length len on the current connection. - * - * This function can only be called in response to a UDP event (poll - * or newdata). The data must be present in the uip_buf buffer, at the - * place pointed to by the uip_appdata pointer. - * - * \param len The length of the data in the uip_buf buffer. - * - * \hideinitializer - */ -#define uip_udp_send(len) uip_send((char *)uip_appdata, len) - -/** @} */ - -/* uIP convenience and converting functions. */ - -/** - * \defgroup uipconvfunc uIP conversion functions - * @{ - * - * These functions can be used for converting between different data - * formats used by uIP. - */ - -/** - * Construct an IP address from four bytes. - * - * This function constructs an IP address of the type that uIP handles - * internally from four bytes. The function is handy for specifying IP - * addresses to use with e.g. the uip_connect() function. - * - * Example: - \code - uip_ipaddr_t ipaddr; - struct uip_conn *c; - - uip_ipaddr(&ipaddr, 192,168,1,2); - c = uip_connect(&ipaddr, HTONS(80)); - \endcode - * - * \param addr A pointer to a uip_ipaddr_t variable that will be - * filled in with the IP address. - * - * \param addr0 The first octet of the IP address. - * \param addr1 The second octet of the IP address. - * \param addr2 The third octet of the IP address. - * \param addr3 The forth octet of the IP address. - * - * \hideinitializer - */ -#define uip_ipaddr(addr, addr0,addr1,addr2,addr3) do { \ - ((u16_t *)(addr))[0] = HTONS(((addr0) << 8) | (addr1)); \ - ((u16_t *)(addr))[1] = HTONS(((addr2) << 8) | (addr3)); \ - } while(0) - -/** - * Construct an IPv6 address from eight 16-bit words. - * - * This function constructs an IPv6 address. - * - * \hideinitializer - */ -#define uip_ip6addr(addr, addr0,addr1,addr2,addr3,addr4,addr5,addr6,addr7) do { \ - ((u16_t *)(addr))[0] = HTONS((addr0)); \ - ((u16_t *)(addr))[1] = HTONS((addr1)); \ - ((u16_t *)(addr))[2] = HTONS((addr2)); \ - ((u16_t *)(addr))[3] = HTONS((addr3)); \ - ((u16_t *)(addr))[4] = HTONS((addr4)); \ - ((u16_t *)(addr))[5] = HTONS((addr5)); \ - ((u16_t *)(addr))[6] = HTONS((addr6)); \ - ((u16_t *)(addr))[7] = HTONS((addr7)); \ - } while(0) - -/** - * Copy an IP address to another IP address. - * - * Copies an IP address from one place to another. - * - * Example: - \code - uip_ipaddr_t ipaddr1, ipaddr2; - - uip_ipaddr(&ipaddr1, 192,16,1,2); - uip_ipaddr_copy(&ipaddr2, &ipaddr1); - \endcode - * - * \param dest The destination for the copy. - * \param src The source from where to copy. - * - * \hideinitializer - */ -#if !UIP_CONF_IPV6 -#define uip_ipaddr_copy(dest, src) do { \ - ((u16_t *)dest)[0] = ((u16_t *)src)[0]; \ - ((u16_t *)dest)[1] = ((u16_t *)src)[1]; \ - } while(0) -#else /* !UIP_CONF_IPV6 */ -#define uip_ipaddr_copy(dest, src) memcpy(dest, src, sizeof(uip_ip6addr_t)) -#endif /* !UIP_CONF_IPV6 */ - -/** - * Compare two IP addresses - * - * Compares two IP addresses. - * - * Example: - \code - uip_ipaddr_t ipaddr1, ipaddr2; - - uip_ipaddr(&ipaddr1, 192,16,1,2); - if(uip_ipaddr_cmp(&ipaddr2, &ipaddr1)) { - printf("They are the same"); - } - \endcode - * - * \param addr1 The first IP address. - * \param addr2 The second IP address. - * - * \hideinitializer - */ -#if !UIP_CONF_IPV6 -#define uip_ipaddr_cmp(addr1, addr2) (((u16_t *)addr1)[0] == ((u16_t *)addr2)[0] && \ - ((u16_t *)addr1)[1] == ((u16_t *)addr2)[1]) -#else /* !UIP_CONF_IPV6 */ -#define uip_ipaddr_cmp(addr1, addr2) (memcmp(addr1, addr2, sizeof(uip_ip6addr_t)) == 0) -#endif /* !UIP_CONF_IPV6 */ - -/** - * Compare two IP addresses with netmasks - * - * Compares two IP addresses with netmasks. The masks are used to mask - * out the bits that are to be compared. - * - * Example: - \code - uip_ipaddr_t ipaddr1, ipaddr2, mask; - - uip_ipaddr(&mask, 255,255,255,0); - uip_ipaddr(&ipaddr1, 192,16,1,2); - uip_ipaddr(&ipaddr2, 192,16,1,3); - if(uip_ipaddr_maskcmp(&ipaddr1, &ipaddr2, &mask)) { - printf("They are the same"); - } - \endcode - * - * \param addr1 The first IP address. - * \param addr2 The second IP address. - * \param mask The netmask. - * - * \hideinitializer - */ -#define uip_ipaddr_maskcmp(addr1, addr2, mask) \ - (((((u16_t *)addr1)[0] & ((u16_t *)mask)[0]) == \ - (((u16_t *)addr2)[0] & ((u16_t *)mask)[0])) && \ - ((((u16_t *)addr1)[1] & ((u16_t *)mask)[1]) == \ - (((u16_t *)addr2)[1] & ((u16_t *)mask)[1]))) - - -/** - * Mask out the network part of an IP address. - * - * Masks out the network part of an IP address, given the address and - * the netmask. - * - * Example: - \code - uip_ipaddr_t ipaddr1, ipaddr2, netmask; - - uip_ipaddr(&ipaddr1, 192,16,1,2); - uip_ipaddr(&netmask, 255,255,255,0); - uip_ipaddr_mask(&ipaddr2, &ipaddr1, &netmask); - \endcode - * - * In the example above, the variable "ipaddr2" will contain the IP - * address 192.168.1.0. - * - * \param dest Where the result is to be placed. - * \param src The IP address. - * \param mask The netmask. - * - * \hideinitializer - */ -#define uip_ipaddr_mask(dest, src, mask) do { \ - ((u16_t *)dest)[0] = ((u16_t *)src)[0] & ((u16_t *)mask)[0]; \ - ((u16_t *)dest)[1] = ((u16_t *)src)[1] & ((u16_t *)mask)[1]; \ - } while(0) - -/** - * Pick the first octet of an IP address. - * - * Picks out the first octet of an IP address. - * - * Example: - \code - uip_ipaddr_t ipaddr; - u8_t octet; - - uip_ipaddr(&ipaddr, 1,2,3,4); - octet = uip_ipaddr1(&ipaddr); - \endcode - * - * In the example above, the variable "octet" will contain the value 1. - * - * \hideinitializer - */ -#define uip_ipaddr1(addr) (htons(((u16_t *)(addr))[0]) >> 8) - -/** - * Pick the second octet of an IP address. - * - * Picks out the second octet of an IP address. - * - * Example: - \code - uip_ipaddr_t ipaddr; - u8_t octet; - - uip_ipaddr(&ipaddr, 1,2,3,4); - octet = uip_ipaddr2(&ipaddr); - \endcode - * - * In the example above, the variable "octet" will contain the value 2. - * - * \hideinitializer - */ -#define uip_ipaddr2(addr) (htons(((u16_t *)(addr))[0]) & 0xff) - -/** - * Pick the third octet of an IP address. - * - * Picks out the third octet of an IP address. - * - * Example: - \code - uip_ipaddr_t ipaddr; - u8_t octet; - - uip_ipaddr(&ipaddr, 1,2,3,4); - octet = uip_ipaddr3(&ipaddr); - \endcode - * - * In the example above, the variable "octet" will contain the value 3. - * - * \hideinitializer - */ -#define uip_ipaddr3(addr) (htons(((u16_t *)(addr))[1]) >> 8) - -/** - * Pick the fourth octet of an IP address. - * - * Picks out the fourth octet of an IP address. - * - * Example: - \code - uip_ipaddr_t ipaddr; - u8_t octet; - - uip_ipaddr(&ipaddr, 1,2,3,4); - octet = uip_ipaddr4(&ipaddr); - \endcode - * - * In the example above, the variable "octet" will contain the value 4. - * - * \hideinitializer - */ -#define uip_ipaddr4(addr) (htons(((u16_t *)(addr))[1]) & 0xff) - -/** - * Convert 16-bit quantity from host byte order to network byte order. - * - * This macro is primarily used for converting constants from host - * byte order to network byte order. For converting variables to - * network byte order, use the htons() function instead. - * - * \hideinitializer - */ -#ifndef HTONS -# if UIP_BYTE_ORDER == UIP_BIG_ENDIAN -# define HTONS(n) (n) -# else /* UIP_BYTE_ORDER == UIP_BIG_ENDIAN */ -# define HTONS(n) (u16_t)((((u16_t) (n)) << 8) | (((u16_t) (n)) >> 8)) -# endif /* UIP_BYTE_ORDER == UIP_BIG_ENDIAN */ -#else -#error "HTONS already defined!" -#endif /* HTONS */ - -/** - * Convert 16-bit quantity from host byte order to network byte order. - * - * This function is primarily used for converting variables from host - * byte order to network byte order. For converting constants to - * network byte order, use the HTONS() macro instead. - */ -#ifndef htons -u16_t htons(u16_t val); -#endif /* htons */ -#ifndef ntohs -#define ntohs htons -#endif - -/** @} */ - -/** - * Pointer to the application data in the packet buffer. - * - * This pointer points to the application data when the application is - * called. If the application wishes to send data, the application may - * use this space to write the data into before calling uip_send(). - */ -extern void *uip_appdata; - -#if UIP_URGDATA > 0 -/* u8_t *uip_urgdata: - * - * This pointer points to any urgent data that has been received. Only - * present if compiled with support for urgent data (UIP_URGDATA). - */ -extern void *uip_urgdata; -#endif /* UIP_URGDATA > 0 */ - - -/** - * \defgroup uipdrivervars Variables used in uIP device drivers - * @{ - * - * uIP has a few global variables that are used in device drivers for - * uIP. - */ - -/** - * The length of the packet in the uip_buf buffer. - * - * The global variable uip_len holds the length of the packet in the - * uip_buf buffer. - * - * When the network device driver calls the uIP input function, - * uip_len should be set to the length of the packet in the uip_buf - * buffer. - * - * When sending packets, the device driver should use the contents of - * the uip_len variable to determine the length of the outgoing - * packet. - * - */ -extern u16_t uip_len; - -/** @} */ - -#if UIP_URGDATA > 0 -extern u16_t uip_urglen, uip_surglen; -#endif /* UIP_URGDATA > 0 */ - - -/** - * Representation of a uIP TCP connection. - * - * The uip_conn structure is used for identifying a connection. All - * but one field in the structure are to be considered read-only by an - * application. The only exception is the appstate field whos purpose - * is to let the application store application-specific state (e.g., - * file pointers) for the connection. The type of this field is - * configured in the "uipopt.h" header file. - */ -struct uip_conn { - uip_ipaddr_t ripaddr; /**< The IP address of the remote host. */ - - u16_t lport; /**< The local TCP port, in network byte order. */ - u16_t rport; /**< The local remote TCP port, in network byte - order. */ - - u8_t rcv_nxt[4]; /**< The sequence number that we expect to - receive next. */ - u8_t snd_nxt[4]; /**< The sequence number that was last sent by - us. */ - u16_t len; /**< Length of the data that was previously sent. */ - u16_t mss; /**< Current maximum segment size for the - connection. */ - u16_t initialmss; /**< Initial maximum segment size for the - connection. */ - u8_t sa; /**< Retransmission time-out calculation state - variable. */ - u8_t sv; /**< Retransmission time-out calculation state - variable. */ - u8_t rto; /**< Retransmission time-out. */ - u8_t tcpstateflags; /**< TCP state and flags. */ - u8_t timer; /**< The retransmission timer. */ - u8_t nrtx; /**< The number of retransmissions for the last - segment sent. */ - - /** The application state. */ - uip_tcp_appstate_t appstate; -}; - - -/** - * Pointer to the current TCP connection. - * - * The uip_conn pointer can be used to access the current TCP - * connection. - */ -extern struct uip_conn *uip_conn; -/* The array containing all uIP connections. */ -extern struct uip_conn uip_conns[UIP_CONNS]; -/** - * \addtogroup uiparch - * @{ - */ - -/** - * 4-byte array used for the 32-bit sequence number calculations. - */ -extern u8_t uip_acc32[4]; - -/** @} */ - - -#if UIP_UDP -/** - * Representation of a uIP UDP connection. - */ -struct uip_udp_conn { - uip_ipaddr_t ripaddr; /**< The IP address of the remote peer. */ - u16_t lport; /**< The local port number in network byte order. */ - u16_t rport; /**< The remote port number in network byte order. */ - u8_t ttl; /**< Default time-to-live. */ - - /** The application state. */ - uip_udp_appstate_t appstate; -}; - -/** - * The current UDP connection. - */ -extern struct uip_udp_conn *uip_udp_conn; -extern struct uip_udp_conn uip_udp_conns[UIP_UDP_CONNS]; -#endif /* UIP_UDP */ - -/** - * The structure holding the TCP/IP statistics that are gathered if - * UIP_STATISTICS is set to 1. - * - */ -struct uip_stats { - struct { - uip_stats_t drop; /**< Number of dropped packets at the IP - layer. */ - uip_stats_t recv; /**< Number of received packets at the IP - layer. */ - uip_stats_t sent; /**< Number of sent packets at the IP - layer. */ - uip_stats_t vhlerr; /**< Number of packets dropped due to wrong - IP version or header length. */ - uip_stats_t hblenerr; /**< Number of packets dropped due to wrong - IP length, high byte. */ - uip_stats_t lblenerr; /**< Number of packets dropped due to wrong - IP length, low byte. */ - uip_stats_t fragerr; /**< Number of packets dropped since they - were IP fragments. */ - uip_stats_t chkerr; /**< Number of packets dropped due to IP - checksum errors. */ - uip_stats_t protoerr; /**< Number of packets dropped since they - were neither ICMP, UDP nor TCP. */ - } ip; /**< IP statistics. */ - struct { - uip_stats_t drop; /**< Number of dropped ICMP packets. */ - uip_stats_t recv; /**< Number of received ICMP packets. */ - uip_stats_t sent; /**< Number of sent ICMP packets. */ - uip_stats_t typeerr; /**< Number of ICMP packets with a wrong - type. */ - } icmp; /**< ICMP statistics. */ - struct { - uip_stats_t drop; /**< Number of dropped TCP segments. */ - uip_stats_t recv; /**< Number of recived TCP segments. */ - uip_stats_t sent; /**< Number of sent TCP segments. */ - uip_stats_t chkerr; /**< Number of TCP segments with a bad - checksum. */ - uip_stats_t ackerr; /**< Number of TCP segments with a bad ACK - number. */ - uip_stats_t rst; /**< Number of recevied TCP RST (reset) segments. */ - uip_stats_t rexmit; /**< Number of retransmitted TCP segments. */ - uip_stats_t syndrop; /**< Number of dropped SYNs due to too few - connections was avaliable. */ - uip_stats_t synrst; /**< Number of SYNs for closed ports, - triggering a RST. */ - } tcp; /**< TCP statistics. */ -#if UIP_UDP - struct { - uip_stats_t drop; /**< Number of dropped UDP segments. */ - uip_stats_t recv; /**< Number of recived UDP segments. */ - uip_stats_t sent; /**< Number of sent UDP segments. */ - uip_stats_t chkerr; /**< Number of UDP segments with a bad - checksum. */ - } udp; /**< UDP statistics. */ -#endif /* UIP_UDP */ -}; - -/** - * The uIP TCP/IP statistics. - * - * This is the variable in which the uIP TCP/IP statistics are gathered. - */ -extern struct uip_stats uip_stat; - - -/*---------------------------------------------------------------------------*/ -/* All the stuff below this point is internal to uIP and should not be - * used directly by an application or by a device driver. - */ -/*---------------------------------------------------------------------------*/ -/* u8_t uip_flags: - * - * When the application is called, uip_flags will contain the flags - * that are defined in this file. Please read below for more - * infomation. - */ -extern u8_t uip_flags; - -/* The following flags may be set in the global variable uip_flags - before calling the application callback. The UIP_ACKDATA, - UIP_NEWDATA, and UIP_CLOSE flags may both be set at the same time, - whereas the others are mutualy exclusive. Note that these flags - should *NOT* be accessed directly, but only through the uIP - functions/macros. */ - -#define UIP_ACKDATA 1 /* Signifies that the outstanding data was - acked and the application should send - out new data instead of retransmitting - the last data. */ -#define UIP_NEWDATA 2 /* Flags the fact that the peer has sent - us new data. */ -#define UIP_REXMIT 4 /* Tells the application to retransmit the - data that was last sent. */ -#define UIP_POLL 8 /* Used for polling the application, to - check if the application has data that - it wants to send. */ -#define UIP_CLOSE 16 /* The remote host has closed the - connection, thus the connection has - gone away. Or the application signals - that it wants to close the - connection. */ -#define UIP_ABORT 32 /* The remote host has aborted the - connection, thus the connection has - gone away. Or the application signals - that it wants to abort the - connection. */ -#define UIP_CONNECTED 64 /* We have got a connection from a remote - host and have set up a new connection - for it, or an active connection has - been successfully established. */ - -#define UIP_TIMEDOUT 128 /* The connection has been aborted due to - too many retransmissions. */ - -/* uip_process(flag): - * - * The actual uIP function which does all the work. - */ -void uip_process(u8_t flag); - -/* The following flags are passed as an argument to the uip_process() - function. They are used to distinguish between the two cases where - uip_process() is called. It can be called either because we have - incoming data that should be processed, or because the periodic - timer has fired. These values are never used directly, but only in - the macrose defined in this file. */ - -#define UIP_DATA 1 /* Tells uIP that there is incoming - data in the uip_buf buffer. The - length of the data is stored in the - global variable uip_len. */ -#define UIP_TIMER 2 /* Tells uIP that the periodic timer - has fired. */ -#define UIP_POLL_REQUEST 3 /* Tells uIP that a connection should - be polled. */ -#define UIP_UDP_SEND_CONN 4 /* Tells uIP that a UDP datagram - should be constructed in the - uip_buf buffer. */ -#if UIP_UDP -#define UIP_UDP_TIMER 5 -#endif /* UIP_UDP */ - -/* The TCP states used in the uip_conn->tcpstateflags. */ -#define UIP_CLOSED 0 -#define UIP_SYN_RCVD 1 -#define UIP_SYN_SENT 2 -#define UIP_ESTABLISHED 3 -#define UIP_FIN_WAIT_1 4 -#define UIP_FIN_WAIT_2 5 -#define UIP_CLOSING 6 -#define UIP_TIME_WAIT 7 -#define UIP_LAST_ACK 8 -#define UIP_TS_MASK 15 - -#define UIP_STOPPED 16 - -/* The TCP and IP headers. */ -struct uip_tcpip_hdr { -#if UIP_CONF_IPV6 - /* IPv6 header. */ - u8_t vtc, - tcflow; - u16_t flow; - u8_t len[2]; - u8_t proto, ttl; - uip_ip6addr_t srcipaddr, destipaddr; -#else /* UIP_CONF_IPV6 */ - /* IPv4 header. */ - u8_t vhl, - tos, - len[2], - ipid[2], - ipoffset[2], - ttl, - proto; - u16_t ipchksum; - u16_t srcipaddr[2], - destipaddr[2]; -#endif /* UIP_CONF_IPV6 */ - - /* TCP header. */ - u16_t srcport, - destport; - u8_t seqno[4], - ackno[4], - tcpoffset, - flags, - wnd[2]; - u16_t tcpchksum; - u8_t urgp[2]; - u8_t optdata[4]; -}; - -/* The ICMP and IP headers. */ -struct uip_icmpip_hdr { -#if UIP_CONF_IPV6 - /* IPv6 header. */ - u8_t vtc, - tcf; - u16_t flow; - u8_t len[2]; - u8_t proto, ttl; - uip_ip6addr_t srcipaddr, destipaddr; -#else /* UIP_CONF_IPV6 */ - /* IPv4 header. */ - u8_t vhl, - tos, - len[2], - ipid[2], - ipoffset[2], - ttl, - proto; - u16_t ipchksum; - u16_t srcipaddr[2], - destipaddr[2]; -#endif /* UIP_CONF_IPV6 */ - - /* ICMP (echo) header. */ - u8_t type, icode; - u16_t icmpchksum; -#if !UIP_CONF_IPV6 - u16_t id, seqno; -#else /* !UIP_CONF_IPV6 */ - u8_t flags, reserved1, reserved2, reserved3; - u8_t icmp6data[16]; - u8_t options[1]; -#endif /* !UIP_CONF_IPV6 */ -}; - - -/* The UDP and IP headers. */ -struct uip_udpip_hdr { -#if UIP_CONF_IPV6 - /* IPv6 header. */ - u8_t vtc, - tcf; - u16_t flow; - u8_t len[2]; - u8_t proto, ttl; - uip_ip6addr_t srcipaddr, destipaddr; -#else /* UIP_CONF_IPV6 */ - /* IP header. */ - u8_t vhl, - tos, - len[2], - ipid[2], - ipoffset[2], - ttl, - proto; - u16_t ipchksum; - u16_t srcipaddr[2], - destipaddr[2]; -#endif /* UIP_CONF_IPV6 */ - - /* UDP header. */ - u16_t srcport, - destport; - u16_t udplen; - u16_t udpchksum; -}; - - - -/** - * The buffer size available for user data in the \ref uip_buf buffer. - * - * This macro holds the available size for user data in the \ref - * uip_buf buffer. The macro is intended to be used for checking - * bounds of available user data. - * - * Example: - \code - snprintf(uip_appdata, UIP_APPDATA_SIZE, "%u\n", i); - \endcode - * - * \hideinitializer - */ -#define UIP_APPDATA_SIZE (UIP_BUFSIZE - UIP_LLH_LEN - UIP_TCPIP_HLEN) - - -#define UIP_PROTO_ICMP 1 -#define UIP_PROTO_TCP 6 -#define UIP_PROTO_UDP 17 -#define UIP_PROTO_ICMP6 58 - -/* Header sizes. */ -#if UIP_CONF_IPV6 -#define UIP_IPH_LEN 40 -#else /* UIP_CONF_IPV6 */ -#define UIP_IPH_LEN 20 /* Size of IP header */ -#endif /* UIP_CONF_IPV6 */ -#define UIP_UDPH_LEN 8 /* Size of UDP header */ -#define UIP_TCPH_LEN 20 /* Size of TCP header */ -#define UIP_IPUDPH_LEN (UIP_UDPH_LEN + UIP_IPH_LEN) /* Size of IP + - UDP - header */ -#define UIP_IPTCPH_LEN (UIP_TCPH_LEN + UIP_IPH_LEN) /* Size of IP + - TCP - header */ -#define UIP_TCPIP_HLEN UIP_IPTCPH_LEN - - -#if UIP_FIXEDADDR -extern const uip_ipaddr_t uip_hostaddr, uip_netmask, uip_draddr; -#else /* UIP_FIXEDADDR */ -extern uip_ipaddr_t uip_hostaddr, uip_netmask, uip_draddr; -#endif /* UIP_FIXEDADDR */ - - - -/** - * Representation of a 48-bit Ethernet address. - */ -struct uip_eth_addr { - u8_t addr[6]; -}; - -/** - * Calculate the Internet checksum over a buffer. - * - * The Internet checksum is the one's complement of the one's - * complement sum of all 16-bit words in the buffer. - * - * See RFC1071. - * - * \param buf A pointer to the buffer over which the checksum is to be - * computed. - * - * \param len The length of the buffer over which the checksum is to - * be computed. - * - * \return The Internet checksum of the buffer. - */ -u16_t uip_chksum(u16_t *buf, u16_t len); - -/** - * Calculate the IP header checksum of the packet header in uip_buf. - * - * The IP header checksum is the Internet checksum of the 20 bytes of - * the IP header. - * - * \return The IP header checksum of the IP header in the uip_buf - * buffer. - */ -u16_t uip_ipchksum(void); - -/** - * Calculate the TCP checksum of the packet in uip_buf and uip_appdata. - * - * The TCP checksum is the Internet checksum of data contents of the - * TCP segment, and a pseudo-header as defined in RFC793. - * - * \return The TCP checksum of the TCP segment in uip_buf and pointed - * to by uip_appdata. - */ -u16_t uip_tcpchksum(void); - -/** - * Calculate the UDP checksum of the packet in uip_buf and uip_appdata. - * - * The UDP checksum is the Internet checksum of data contents of the - * UDP segment, and a pseudo-header as defined in RFC768. - * - * \return The UDP checksum of the UDP segment in uip_buf and pointed - * to by uip_appdata. - */ -u16_t uip_udpchksum(void); - - -#endif /* __UIP_H__ */ - - -/** @} */ diff --git a/Demo/Common/ethernet/uIP/uip-1.0/uip/uip_arch.h b/Demo/Common/ethernet/uIP/uip-1.0/uip/uip_arch.h deleted file mode 100644 index 5ea45787c..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/uip/uip_arch.h +++ /dev/null @@ -1,138 +0,0 @@ -/** - * \addtogroup uip - * {@ - */ - -/** - * \defgroup uiparch Architecture specific uIP functions - * @{ - * - * The functions in the architecture specific module implement the IP - * check sum and 32-bit additions. - * - * The IP checksum calculation is the most computationally expensive - * operation in the TCP/IP stack and it therefore pays off to - * implement this in efficient assembler. The purpose of the uip-arch - * module is to let the checksum functions to be implemented in - * architecture specific assembler. - * - */ - -/** - * \file - * Declarations of architecture specific functions. - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2001, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: uip_arch.h,v 1.2 2006/06/07 09:15:19 adam Exp $ - * - */ - -#ifndef __UIP_ARCH_H__ -#define __UIP_ARCH_H__ - -#include "uip.h" - -/** - * Carry out a 32-bit addition. - * - * Because not all architectures for which uIP is intended has native - * 32-bit arithmetic, uIP uses an external C function for doing the - * required 32-bit additions in the TCP protocol processing. This - * function should add the two arguments and place the result in the - * global variable uip_acc32. - * - * \note The 32-bit integer pointed to by the op32 parameter and the - * result in the uip_acc32 variable are in network byte order (big - * endian). - * - * \param op32 A pointer to a 4-byte array representing a 32-bit - * integer in network byte order (big endian). - * - * \param op16 A 16-bit integer in host byte order. - */ -void uip_add32(u8_t *op32, u16_t op16); - -/** - * Calculate the Internet checksum over a buffer. - * - * The Internet checksum is the one's complement of the one's - * complement sum of all 16-bit words in the buffer. - * - * See RFC1071. - * - * \note This function is not called in the current version of uIP, - * but future versions might make use of it. - * - * \param buf A pointer to the buffer over which the checksum is to be - * computed. - * - * \param len The length of the buffer over which the checksum is to - * be computed. - * - * \return The Internet checksum of the buffer. - */ -u16_t uip_chksum(u16_t *buf, u16_t len); - -/** - * Calculate the IP header checksum of the packet header in uip_buf. - * - * The IP header checksum is the Internet checksum of the 20 bytes of - * the IP header. - * - * \return The IP header checksum of the IP header in the uip_buf - * buffer. - */ -u16_t uip_ipchksum(void); - -/** - * Calculate the TCP checksum of the packet in uip_buf and uip_appdata. - * - * The TCP checksum is the Internet checksum of data contents of the - * TCP segment, and a pseudo-header as defined in RFC793. - * - * \note The uip_appdata pointer that points to the packet data may - * point anywhere in memory, so it is not possible to simply calculate - * the Internet checksum of the contents of the uip_buf buffer. - * - * \return The TCP checksum of the TCP segment in uip_buf and pointed - * to by uip_appdata. - */ -u16_t uip_tcpchksum(void); - -u16_t uip_udpchksum(void); - -/** @} */ -/** @} */ - -#endif /* __UIP_ARCH_H__ */ diff --git a/Demo/Common/ethernet/uIP/uip-1.0/uip/uip_arp.c b/Demo/Common/ethernet/uIP/uip-1.0/uip/uip_arp.c deleted file mode 100644 index 96cea8bac..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/uip/uip_arp.c +++ /dev/null @@ -1,423 +0,0 @@ -/** - * \addtogroup uip - * @{ - */ - -/** - * \defgroup uiparp uIP Address Resolution Protocol - * @{ - * - * The Address Resolution Protocol ARP is used for mapping between IP - * addresses and link level addresses such as the Ethernet MAC - * addresses. ARP uses broadcast queries to ask for the link level - * address of a known IP address and the host which is configured with - * the IP address for which the query was meant, will respond with its - * link level address. - * - * \note This ARP implementation only supports Ethernet. - */ - -/** - * \file - * Implementation of the ARP Address Resolution Protocol. - * \author Adam Dunkels - * - */ - -/* - * Copyright (c) 2001-2003, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: uip_arp.c,v 1.8 2006/06/02 23:36:21 adam Exp $ - * - */ - - -#include "uip_arp.h" - -#include - -struct arp_hdr { - struct uip_eth_hdr ethhdr; - u16_t hwtype; - u16_t protocol; - u8_t hwlen; - u8_t protolen; - u16_t opcode; - struct uip_eth_addr shwaddr; - u16_t sipaddr[2]; - struct uip_eth_addr dhwaddr; - u16_t dipaddr[2]; -}; - -struct ethip_hdr { - struct uip_eth_hdr ethhdr; - /* IP header. */ - u8_t vhl, - tos, - len[2], - ipid[2], - ipoffset[2], - ttl, - proto; - u16_t ipchksum; - u16_t srcipaddr[2], - destipaddr[2]; -}; - -#define ARP_REQUEST 1 -#define ARP_REPLY 2 - -#define ARP_HWTYPE_ETH 1 - -struct arp_entry { - u16_t ipaddr[2]; - struct uip_eth_addr ethaddr; - u8_t time; -}; - -static const struct uip_eth_addr broadcast_ethaddr = - {{0xff,0xff,0xff,0xff,0xff,0xff}}; -static const u16_t broadcast_ipaddr[2] = {0xffff,0xffff}; - -static struct arp_entry arp_table[UIP_ARPTAB_SIZE]; -static u16_t ipaddr[2]; -static u8_t i, c; - -static u8_t arptime; -static u8_t tmpage; - -#define BUF ((struct arp_hdr *)&uip_buf[0]) -#define IPBUF ((struct ethip_hdr *)&uip_buf[0]) -/*-----------------------------------------------------------------------------------*/ -/** - * Initialize the ARP module. - * - */ -/*-----------------------------------------------------------------------------------*/ -void -uip_arp_init(void) -{ - for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { - memset(arp_table[i].ipaddr, 0, 4); - } -} -/*-----------------------------------------------------------------------------------*/ -/** - * Periodic ARP processing function. - * - * This function performs periodic timer processing in the ARP module - * and should be called at regular intervals. The recommended interval - * is 10 seconds between the calls. - * - */ -/*-----------------------------------------------------------------------------------*/ -void -uip_arp_timer(void) -{ - struct arp_entry *tabptr; - - ++arptime; - for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { - tabptr = &arp_table[i]; - if((tabptr->ipaddr[0] | tabptr->ipaddr[1]) != 0 && - arptime - tabptr->time >= UIP_ARP_MAXAGE) { - memset(tabptr->ipaddr, 0, 4); - } - } - -} -/*-----------------------------------------------------------------------------------*/ -static void -uip_arp_update(u16_t *ipaddr, struct uip_eth_addr *ethaddr) -{ - register struct arp_entry *tabptr; - /* Walk through the ARP mapping table and try to find an entry to - update. If none is found, the IP -> MAC address mapping is - inserted in the ARP table. */ - for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { - - tabptr = &arp_table[i]; - /* Only check those entries that are actually in use. */ - if(tabptr->ipaddr[0] != 0 && - tabptr->ipaddr[1] != 0) { - - /* Check if the source IP address of the incoming packet matches - the IP address in this ARP table entry. */ - if(ipaddr[0] == tabptr->ipaddr[0] && - ipaddr[1] == tabptr->ipaddr[1]) { - - /* An old entry found, update this and return. */ - memcpy(tabptr->ethaddr.addr, ethaddr->addr, 6); - tabptr->time = arptime; - - return; - } - } - } - - /* If we get here, no existing ARP table entry was found, so we - create one. */ - - /* First, we try to find an unused entry in the ARP table. */ - for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { - tabptr = &arp_table[i]; - if(tabptr->ipaddr[0] == 0 && - tabptr->ipaddr[1] == 0) { - break; - } - } - - /* If no unused entry is found, we try to find the oldest entry and - throw it away. */ - if(i == UIP_ARPTAB_SIZE) { - tmpage = 0; - c = 0; - for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { - tabptr = &arp_table[i]; - if(arptime - tabptr->time > tmpage) { - tmpage = arptime - tabptr->time; - c = i; - } - } - i = c; - tabptr = &arp_table[i]; - } - - /* Now, i is the ARP table entry which we will fill with the new - information. */ - memcpy(tabptr->ipaddr, ipaddr, 4); - memcpy(tabptr->ethaddr.addr, ethaddr->addr, 6); - tabptr->time = arptime; -} -/*-----------------------------------------------------------------------------------*/ -/** - * ARP processing for incoming IP packets - * - * This function should be called by the device driver when an IP - * packet has been received. The function will check if the address is - * in the ARP cache, and if so the ARP cache entry will be - * refreshed. If no ARP cache entry was found, a new one is created. - * - * This function expects an IP packet with a prepended Ethernet header - * in the uip_buf[] buffer, and the length of the packet in the global - * variable uip_len. - */ -/*-----------------------------------------------------------------------------------*/ -#if 0 -void -uip_arp_ipin(void) -{ - uip_len -= sizeof(struct uip_eth_hdr); - - /* Only insert/update an entry if the source IP address of the - incoming IP packet comes from a host on the local network. */ - if((IPBUF->srcipaddr[0] & uip_netmask[0]) != - (uip_hostaddr[0] & uip_netmask[0])) { - return; - } - if((IPBUF->srcipaddr[1] & uip_netmask[1]) != - (uip_hostaddr[1] & uip_netmask[1])) { - return; - } - uip_arp_update(IPBUF->srcipaddr, &(IPBUF->ethhdr.src)); - - return; -} -#endif /* 0 */ -/*-----------------------------------------------------------------------------------*/ -/** - * ARP processing for incoming ARP packets. - * - * This function should be called by the device driver when an ARP - * packet has been received. The function will act differently - * depending on the ARP packet type: if it is a reply for a request - * that we previously sent out, the ARP cache will be filled in with - * the values from the ARP reply. If the incoming ARP packet is an ARP - * request for our IP address, an ARP reply packet is created and put - * into the uip_buf[] buffer. - * - * When the function returns, the value of the global variable uip_len - * indicates whether the device driver should send out a packet or - * not. If uip_len is zero, no packet should be sent. If uip_len is - * non-zero, it contains the length of the outbound packet that is - * present in the uip_buf[] buffer. - * - * This function expects an ARP packet with a prepended Ethernet - * header in the uip_buf[] buffer, and the length of the packet in the - * global variable uip_len. - */ -/*-----------------------------------------------------------------------------------*/ -void -uip_arp_arpin(void) -{ - - if(uip_len < sizeof(struct arp_hdr)) { - uip_len = 0; - return; - } - uip_len = 0; - - switch(BUF->opcode) { - case HTONS(ARP_REQUEST): - /* ARP request. If it asked for our address, we send out a - reply. */ - if(uip_ipaddr_cmp(BUF->dipaddr, uip_hostaddr)) { - /* First, we register the one who made the request in our ARP - table, since it is likely that we will do more communication - with this host in the future. */ - uip_arp_update(BUF->sipaddr, &BUF->shwaddr); - - /* The reply opcode is 2. */ - BUF->opcode = HTONS(2); - - memcpy(BUF->dhwaddr.addr, BUF->shwaddr.addr, 6); - memcpy(BUF->shwaddr.addr, uip_ethaddr.addr, 6); - memcpy(BUF->ethhdr.src.addr, uip_ethaddr.addr, 6); - memcpy(BUF->ethhdr.dest.addr, BUF->dhwaddr.addr, 6); - - BUF->dipaddr[0] = BUF->sipaddr[0]; - BUF->dipaddr[1] = BUF->sipaddr[1]; - BUF->sipaddr[0] = uip_hostaddr[0]; - BUF->sipaddr[1] = uip_hostaddr[1]; - - BUF->ethhdr.type = HTONS(UIP_ETHTYPE_ARP); - uip_len = sizeof(struct arp_hdr); - } - break; - case HTONS(ARP_REPLY): - /* ARP reply. We insert or update the ARP table if it was meant - for us. */ - if(uip_ipaddr_cmp(BUF->dipaddr, uip_hostaddr)) { - uip_arp_update(BUF->sipaddr, &BUF->shwaddr); - } - break; - } - - return; -} -/*-----------------------------------------------------------------------------------*/ -/** - * Prepend Ethernet header to an outbound IP packet and see if we need - * to send out an ARP request. - * - * This function should be called before sending out an IP packet. The - * function checks the destination IP address of the IP packet to see - * what Ethernet MAC address that should be used as a destination MAC - * address on the Ethernet. - * - * If the destination IP address is in the local network (determined - * by logical ANDing of netmask and our IP address), the function - * checks the ARP cache to see if an entry for the destination IP - * address is found. If so, an Ethernet header is prepended and the - * function returns. If no ARP cache entry is found for the - * destination IP address, the packet in the uip_buf[] is replaced by - * an ARP request packet for the IP address. The IP packet is dropped - * and it is assumed that they higher level protocols (e.g., TCP) - * eventually will retransmit the dropped packet. - * - * If the destination IP address is not on the local network, the IP - * address of the default router is used instead. - * - * When the function returns, a packet is present in the uip_buf[] - * buffer, and the length of the packet is in the global variable - * uip_len. - */ -/*-----------------------------------------------------------------------------------*/ -void -uip_arp_out(void) -{ - struct arp_entry *tabptr; - - /* Find the destination IP address in the ARP table and construct - the Ethernet header. If the destination IP addres isn't on the - local network, we use the default router's IP address instead. - - If not ARP table entry is found, we overwrite the original IP - packet with an ARP request for the IP address. */ - - /* First check if destination is a local broadcast. */ - if(uip_ipaddr_cmp(IPBUF->destipaddr, broadcast_ipaddr)) { - memcpy(IPBUF->ethhdr.dest.addr, broadcast_ethaddr.addr, 6); - } else { - /* Check if the destination address is on the local network. */ - if(!uip_ipaddr_maskcmp(IPBUF->destipaddr, uip_hostaddr, uip_netmask)) { - /* Destination address was not on the local network, so we need to - use the default router's IP address instead of the destination - address when determining the MAC address. */ - uip_ipaddr_copy(ipaddr, uip_draddr); - } else { - /* Else, we use the destination IP address. */ - uip_ipaddr_copy(ipaddr, IPBUF->destipaddr); - } - - for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { - tabptr = &arp_table[i]; - if(uip_ipaddr_cmp(ipaddr, tabptr->ipaddr)) { - break; - } - } - - if(i == UIP_ARPTAB_SIZE) { - /* The destination address was not in our ARP table, so we - overwrite the IP packet with an ARP request. */ - - memset(BUF->ethhdr.dest.addr, 0xff, 6); - memset(BUF->dhwaddr.addr, 0x00, 6); - memcpy(BUF->ethhdr.src.addr, uip_ethaddr.addr, 6); - memcpy(BUF->shwaddr.addr, uip_ethaddr.addr, 6); - - uip_ipaddr_copy(BUF->dipaddr, ipaddr); - uip_ipaddr_copy(BUF->sipaddr, uip_hostaddr); - BUF->opcode = HTONS(ARP_REQUEST); /* ARP request. */ - BUF->hwtype = HTONS(ARP_HWTYPE_ETH); - BUF->protocol = HTONS(UIP_ETHTYPE_IP); - BUF->hwlen = 6; - BUF->protolen = 4; - BUF->ethhdr.type = HTONS(UIP_ETHTYPE_ARP); - - uip_appdata = &uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN]; - - uip_len = sizeof(struct arp_hdr); - return; - } - - /* Build an ethernet header. */ - memcpy(IPBUF->ethhdr.dest.addr, tabptr->ethaddr.addr, 6); - } - memcpy(IPBUF->ethhdr.src.addr, uip_ethaddr.addr, 6); - - IPBUF->ethhdr.type = HTONS(UIP_ETHTYPE_IP); - - uip_len += sizeof(struct uip_eth_hdr); -} -/*-----------------------------------------------------------------------------------*/ - -/** @} */ -/** @} */ diff --git a/Demo/Common/ethernet/uIP/uip-1.0/uip/uip_arp.h b/Demo/Common/ethernet/uIP/uip-1.0/uip/uip_arp.h deleted file mode 100644 index dc829e062..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/uip/uip_arp.h +++ /dev/null @@ -1,144 +0,0 @@ -/** - * \addtogroup uip - * @{ - */ - -/** - * \addtogroup uiparp - * @{ - */ - -/** - * \file - * Macros and definitions for the ARP module. - * \author Adam Dunkels - */ - - -/* - * Copyright (c) 2001-2003, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: uip_arp.h,v 1.5 2006/06/11 21:46:39 adam Exp $ - * - */ - -#ifndef __UIP_ARP_H__ -#define __UIP_ARP_H__ - -#include "uip.h" - - -extern struct uip_eth_addr uip_ethaddr; - -/** - * The Ethernet header. - */ -struct uip_eth_hdr { - struct uip_eth_addr dest; - struct uip_eth_addr src; - u16_t type; -}; - -#define UIP_ETHTYPE_ARP 0x0806 -#define UIP_ETHTYPE_IP 0x0800 -#define UIP_ETHTYPE_IP6 0x86dd - - -/* The uip_arp_init() function must be called before any of the other - ARP functions. */ -void uip_arp_init(void); - -/* The uip_arp_ipin() function should be called whenever an IP packet - arrives from the Ethernet. This function refreshes the ARP table or - inserts a new mapping if none exists. The function assumes that an - IP packet with an Ethernet header is present in the uip_buf buffer - and that the length of the packet is in the uip_len variable. */ -/*void uip_arp_ipin(void);*/ -#define uip_arp_ipin() - -/* The uip_arp_arpin() should be called when an ARP packet is received - by the Ethernet driver. This function also assumes that the - Ethernet frame is present in the uip_buf buffer. When the - uip_arp_arpin() function returns, the contents of the uip_buf - buffer should be sent out on the Ethernet if the uip_len variable - is > 0. */ -void uip_arp_arpin(void); - -/* The uip_arp_out() function should be called when an IP packet - should be sent out on the Ethernet. This function creates an - Ethernet header before the IP header in the uip_buf buffer. The - Ethernet header will have the correct Ethernet MAC destination - address filled in if an ARP table entry for the destination IP - address (or the IP address of the default router) is present. If no - such table entry is found, the IP packet is overwritten with an ARP - request and we rely on TCP to retransmit the packet that was - overwritten. In any case, the uip_len variable holds the length of - the Ethernet frame that should be transmitted. */ -void uip_arp_out(void); - -/* The uip_arp_timer() function should be called every ten seconds. It - is responsible for flushing old entries in the ARP table. */ -void uip_arp_timer(void); - -/** @} */ - -/** - * \addtogroup uipconffunc - * @{ - */ - - -/** - * Specifiy the Ethernet MAC address. - * - * The ARP code needs to know the MAC address of the Ethernet card in - * order to be able to respond to ARP queries and to generate working - * Ethernet headers. - * - * \note This macro only specifies the Ethernet MAC address to the ARP - * code. It cannot be used to change the MAC address of the Ethernet - * card. - * - * \param eaddr A pointer to a struct uip_eth_addr containing the - * Ethernet MAC address of the Ethernet card. - * - * \hideinitializer - */ -#define uip_setethaddr(eaddr) do {uip_ethaddr.addr[0] = eaddr.addr[0]; \ - uip_ethaddr.addr[1] = eaddr.addr[1];\ - uip_ethaddr.addr[2] = eaddr.addr[2];\ - uip_ethaddr.addr[3] = eaddr.addr[3];\ - uip_ethaddr.addr[4] = eaddr.addr[4];\ - uip_ethaddr.addr[5] = eaddr.addr[5];} while(0) - -/** @} */ -/** @} */ - -#endif /* __UIP_ARP_H__ */ diff --git a/Demo/Common/ethernet/uIP/uip-1.0/uip/uiplib.c b/Demo/Common/ethernet/uIP/uip-1.0/uip/uiplib.c deleted file mode 100644 index 647b0b270..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/uip/uiplib.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (c) 2004, Adam Dunkels and the Swedish Institute of - * Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack - * - * $Id: uiplib.c,v 1.2 2006/06/12 08:00:31 adam Exp $ - * - */ - - -#include "uip.h" -#include "uiplib.h" - - -/*-----------------------------------------------------------------------------------*/ -unsigned char -uiplib_ipaddrconv(char *addrstr, unsigned char *ipaddr) -{ - unsigned char tmp; - char c; - unsigned char i, j; - - tmp = 0; - - for(i = 0; i < 4; ++i) { - j = 0; - do { - c = *addrstr; - ++j; - if(j > 4) { - return 0; - } - if(c == '.' || c == 0) { - *ipaddr = tmp; - ++ipaddr; - tmp = 0; - } else if(c >= '0' && c <= '9') { - tmp = (tmp * 10) + (c - '0'); - } else { - return 0; - } - ++addrstr; - } while(c != '.' && c != 0); - } - return 1; -} - -/*-----------------------------------------------------------------------------------*/ diff --git a/Demo/Common/ethernet/uIP/uip-1.0/uip/uiplib.h b/Demo/Common/ethernet/uIP/uip-1.0/uip/uiplib.h deleted file mode 100644 index 6eb0c66f5..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/uip/uiplib.h +++ /dev/null @@ -1,71 +0,0 @@ -/** - * \file - * Various uIP library functions. - * \author - * Adam Dunkels - * - */ - -/* - * Copyright (c) 2002, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack - * - * $Id: uiplib.h,v 1.1 2006/06/07 09:15:19 adam Exp $ - * - */ -#ifndef __UIPLIB_H__ -#define __UIPLIB_H__ - -/** - * \addtogroup uipconvfunc - * @{ - */ - -/** - * Convert a textual representation of an IP address to a numerical representation. - * - * This function takes a textual representation of an IP address in - * the form a.b.c.d and converts it into a 4-byte array that can be - * used by other uIP functions. - * - * \param addrstr A pointer to a string containing the IP address in - * textual form. - * - * \param addr A pointer to a 4-byte array that will be filled in with - * the numerical representation of the address. - * - * \retval 0 If the IP address could not be parsed. - * \retval Non-zero If the IP address was parsed. - */ -unsigned char uiplib_ipaddrconv(char *addrstr, unsigned char *addr); - -/** @} */ - -#endif /* __UIPLIB_H__ */ diff --git a/Demo/Common/ethernet/uIP/uip-1.0/uip/uipopt.h b/Demo/Common/ethernet/uIP/uip-1.0/uip/uipopt.h deleted file mode 100644 index f7c3e0f80..000000000 --- a/Demo/Common/ethernet/uIP/uip-1.0/uip/uipopt.h +++ /dev/null @@ -1,539 +0,0 @@ -/** - * \defgroup uipopt Configuration options for uIP - * @{ - * - * uIP is configured using the per-project configuration file - * uipopt.h. This file contains all compile-time options for uIP and - * should be tweaked to match each specific project. The uIP - * distribution contains a documented example "uipopt.h" that can be - * copied and modified for each project. - * - * \note Most of the configuration options in the uipopt.h should not - * be changed, but rather the per-project uip-conf.h file. - */ - -/** - * \file - * Configuration options for uIP. - * \author Adam Dunkels - * - * This file is used for tweaking various configuration options for - * uIP. You should make a copy of this file into one of your project's - * directories instead of editing this example "uipopt.h" file that - * comes with the uIP distribution. - */ - -/* - * Copyright (c) 2001-2003, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: uipopt.h,v 1.4 2006/06/12 08:00:31 adam Exp $ - * - */ - -#ifndef __UIPOPT_H__ -#define __UIPOPT_H__ - -#ifndef UIP_LITTLE_ENDIAN -#define UIP_LITTLE_ENDIAN 3412 -#endif /* UIP_LITTLE_ENDIAN */ -#ifndef UIP_BIG_ENDIAN -#define UIP_BIG_ENDIAN 1234 -#endif /* UIP_BIG_ENDIAN */ - -#include "uip-conf.h" - -/*------------------------------------------------------------------------------*/ - -/** - * \name Static configuration options - * @{ - * - * These configuration options can be used for setting the IP address - * settings statically, but only if UIP_FIXEDADDR is set to 1. The - * configuration options for a specific node includes IP address, - * netmask and default router as well as the Ethernet address. The - * netmask, default router and Ethernet address are appliciable only - * if uIP should be run over Ethernet. - * - * All of these should be changed to suit your project. -*/ - -/** - * Determines if uIP should use a fixed IP address or not. - * - * If uIP should use a fixed IP address, the settings are set in the - * uipopt.h file. If not, the macros uip_sethostaddr(), - * uip_setdraddr() and uip_setnetmask() should be used instead. - * - * \hideinitializer - */ -#define UIP_FIXEDADDR 0 - -/** - * Ping IP address asignment. - * - * uIP uses a "ping" packets for setting its own IP address if this - * option is set. If so, uIP will start with an empty IP address and - * the destination IP address of the first incoming "ping" (ICMP echo) - * packet will be used for setting the hosts IP address. - * - * \note This works only if UIP_FIXEDADDR is 0. - * - * \hideinitializer - */ -#ifdef UIP_CONF_PINGADDRCONF -#define UIP_PINGADDRCONF UIP_CONF_PINGADDRCONF -#else /* UIP_CONF_PINGADDRCONF */ -#define UIP_PINGADDRCONF 0 -#endif /* UIP_CONF_PINGADDRCONF */ - - -/** - * Specifies if the uIP ARP module should be compiled with a fixed - * Ethernet MAC address or not. - * - * If this configuration option is 0, the macro uip_setethaddr() can - * be used to specify the Ethernet address at run-time. - * - * \hideinitializer - */ -#define UIP_FIXEDETHADDR 0 - -/** @} */ -/*------------------------------------------------------------------------------*/ -/** - * \name IP configuration options - * @{ - * - */ -/** - * The IP TTL (time to live) of IP packets sent by uIP. - * - * This should normally not be changed. - */ -#define UIP_TTL 64 - -/** - * Turn on support for IP packet reassembly. - * - * uIP supports reassembly of fragmented IP packets. This features - * requires an additonal amount of RAM to hold the reassembly buffer - * and the reassembly code size is approximately 700 bytes. The - * reassembly buffer is of the same size as the uip_buf buffer - * (configured by UIP_BUFSIZE). - * - * \note IP packet reassembly is not heavily tested. - * - * \hideinitializer - */ -#define UIP_REASSEMBLY 0 - -/** - * The maximum time an IP fragment should wait in the reassembly - * buffer before it is dropped. - * - */ -#define UIP_REASS_MAXAGE 40 - -/** @} */ - -/*------------------------------------------------------------------------------*/ -/** - * \name UDP configuration options - * @{ - */ - -/** - * Toggles wether UDP support should be compiled in or not. - * - * \hideinitializer - */ -#ifdef UIP_CONF_UDP -#define UIP_UDP UIP_CONF_UDP -#else /* UIP_CONF_UDP */ -#define UIP_UDP 0 -#endif /* UIP_CONF_UDP */ - -/** - * Toggles if UDP checksums should be used or not. - * - * \note Support for UDP checksums is currently not included in uIP, - * so this option has no function. - * - * \hideinitializer - */ -#ifdef UIP_CONF_UDP_CHECKSUMS -#define UIP_UDP_CHECKSUMS UIP_CONF_UDP_CHECKSUMS -#else -#define UIP_UDP_CHECKSUMS 0 -#endif - -/** - * The maximum amount of concurrent UDP connections. - * - * \hideinitializer - */ -#ifdef UIP_CONF_UDP_CONNS -#define UIP_UDP_CONNS UIP_CONF_UDP_CONNS -#else /* UIP_CONF_UDP_CONNS */ -#define UIP_UDP_CONNS 10 -#endif /* UIP_CONF_UDP_CONNS */ - -/** - * The name of the function that should be called when UDP datagrams arrive. - * - * \hideinitializer - */ - - -/** @} */ -/*------------------------------------------------------------------------------*/ -/** - * \name TCP configuration options - * @{ - */ - -/** - * Determines if support for opening connections from uIP should be - * compiled in. - * - * If the applications that are running on top of uIP for this project - * do not need to open outgoing TCP connections, this configration - * option can be turned off to reduce the code size of uIP. - * - * \hideinitializer - */ -#define UIP_ACTIVE_OPEN 1 - -/** - * The maximum number of simultaneously open TCP connections. - * - * Since the TCP connections are statically allocated, turning this - * configuration knob down results in less RAM used. Each TCP - * connection requires approximatly 30 bytes of memory. - * - * \hideinitializer - */ -#ifndef UIP_CONF_MAX_CONNECTIONS -#define UIP_CONNS 10 -#else /* UIP_CONF_MAX_CONNECTIONS */ -#define UIP_CONNS UIP_CONF_MAX_CONNECTIONS -#endif /* UIP_CONF_MAX_CONNECTIONS */ - - -/** - * The maximum number of simultaneously listening TCP ports. - * - * Each listening TCP port requires 2 bytes of memory. - * - * \hideinitializer - */ -#ifndef UIP_CONF_MAX_LISTENPORTS -#define UIP_LISTENPORTS 20 -#else /* UIP_CONF_MAX_LISTENPORTS */ -#define UIP_LISTENPORTS UIP_CONF_MAX_LISTENPORTS -#endif /* UIP_CONF_MAX_LISTENPORTS */ - -/** - * Determines if support for TCP urgent data notification should be - * compiled in. - * - * Urgent data (out-of-band data) is a rarely used TCP feature that - * very seldom would be required. - * - * \hideinitializer - */ -#define UIP_URGDATA 0 - -/** - * The initial retransmission timeout counted in timer pulses. - * - * This should not be changed. - */ -#define UIP_RTO 3 - -/** - * The maximum number of times a segment should be retransmitted - * before the connection should be aborted. - * - * This should not be changed. - */ -#define UIP_MAXRTX 8 - -/** - * The maximum number of times a SYN segment should be retransmitted - * before a connection request should be deemed to have been - * unsuccessful. - * - * This should not need to be changed. - */ -#define UIP_MAXSYNRTX 5 - -/** - * The TCP maximum segment size. - * - * This is should not be to set to more than - * UIP_BUFSIZE - UIP_LLH_LEN - UIP_TCPIP_HLEN. - */ -#define UIP_TCP_MSS (UIP_BUFSIZE - UIP_LLH_LEN - UIP_TCPIP_HLEN) - -/** - * The size of the advertised receiver's window. - * - * Should be set low (i.e., to the size of the uip_buf buffer) is the - * application is slow to process incoming data, or high (32768 bytes) - * if the application processes data quickly. - * - * \hideinitializer - */ -#ifndef UIP_CONF_RECEIVE_WINDOW -#define UIP_RECEIVE_WINDOW UIP_TCP_MSS -#else -#define UIP_RECEIVE_WINDOW UIP_CONF_RECEIVE_WINDOW -#endif - -/** - * How long a connection should stay in the TIME_WAIT state. - * - * This configiration option has no real implication, and it should be - * left untouched. - */ -#define UIP_TIME_WAIT_TIMEOUT 120 - - -/** @} */ -/*------------------------------------------------------------------------------*/ -/** - * \name ARP configuration options - * @{ - */ - -/** - * The size of the ARP table. - * - * This option should be set to a larger value if this uIP node will - * have many connections from the local network. - * - * \hideinitializer - */ -#ifdef UIP_CONF_ARPTAB_SIZE -#define UIP_ARPTAB_SIZE UIP_CONF_ARPTAB_SIZE -#else -#define UIP_ARPTAB_SIZE 8 -#endif - -/** - * The maxium age of ARP table entries measured in 10ths of seconds. - * - * An UIP_ARP_MAXAGE of 120 corresponds to 20 minutes (BSD - * default). - */ -#define UIP_ARP_MAXAGE 120 - -/** @} */ - -/*------------------------------------------------------------------------------*/ - -/** - * \name General configuration options - * @{ - */ - -/** - * The size of the uIP packet buffer. - * - * The uIP packet buffer should not be smaller than 60 bytes, and does - * not need to be larger than 1500 bytes. Lower size results in lower - * TCP throughput, larger size results in higher TCP throughput. - * - * \hideinitializer - */ -#ifndef UIP_CONF_BUFFER_SIZE -#define UIP_BUFSIZE 1500 -#else /* UIP_CONF_BUFFER_SIZE */ -#define UIP_BUFSIZE UIP_CONF_BUFFER_SIZE -#endif /* UIP_CONF_BUFFER_SIZE */ - - -/** - * Determines if statistics support should be compiled in. - * - * The statistics is useful for debugging and to show the user. - * - * \hideinitializer - */ -#ifndef UIP_CONF_STATISTICS -#define UIP_STATISTICS 0 -#else /* UIP_CONF_STATISTICS */ -#define UIP_STATISTICS UIP_CONF_STATISTICS -#endif /* UIP_CONF_STATISTICS */ - -/** - * Determines if logging of certain events should be compiled in. - * - * This is useful mostly for debugging. The function uip_log() - * must be implemented to suit the architecture of the project, if - * logging is turned on. - * - * \hideinitializer - */ -#ifndef UIP_CONF_LOGGING -#define UIP_LOGGING 0 -#else /* UIP_CONF_LOGGING */ -#define UIP_LOGGING UIP_CONF_LOGGING -#endif /* UIP_CONF_LOGGING */ - -/** - * Broadcast support. - * - * This flag configures IP broadcast support. This is useful only - * together with UDP. - * - * \hideinitializer - * - */ -#ifndef UIP_CONF_BROADCAST -#define UIP_BROADCAST 0 -#else /* UIP_CONF_BROADCAST */ -#define UIP_BROADCAST UIP_CONF_BROADCAST -#endif /* UIP_CONF_BROADCAST */ - -/** - * Print out a uIP log message. - * - * This function must be implemented by the module that uses uIP, and - * is called by uIP whenever a log message is generated. - */ -void uip_log(char *msg); - -/** - * The link level header length. - * - * This is the offset into the uip_buf where the IP header can be - * found. For Ethernet, this should be set to 14. For SLIP, this - * should be set to 0. - * - * \hideinitializer - */ -#ifdef UIP_CONF_LLH_LEN -#define UIP_LLH_LEN UIP_CONF_LLH_LEN -#else /* UIP_CONF_LLH_LEN */ -#define UIP_LLH_LEN 14 -#endif /* UIP_CONF_LLH_LEN */ - -/** @} */ -/*------------------------------------------------------------------------------*/ -/** - * \name CPU architecture configuration - * @{ - * - * The CPU architecture configuration is where the endianess of the - * CPU on which uIP is to be run is specified. Most CPUs today are - * little endian, and the most notable exception are the Motorolas - * which are big endian. The BYTE_ORDER macro should be changed to - * reflect the CPU architecture on which uIP is to be run. - */ - -/** - * The byte order of the CPU architecture on which uIP is to be run. - * - * This option can be either BIG_ENDIAN (Motorola byte order) or - * LITTLE_ENDIAN (Intel byte order). - * - * \hideinitializer - */ -#ifdef UIP_CONF_BYTE_ORDER -#define UIP_BYTE_ORDER UIP_CONF_BYTE_ORDER -#else /* UIP_CONF_BYTE_ORDER */ -#define UIP_BYTE_ORDER UIP_LITTLE_ENDIAN -#endif /* UIP_CONF_BYTE_ORDER */ - -/** @} */ -/*------------------------------------------------------------------------------*/ - -/** - * \name Appication specific configurations - * @{ - * - * An uIP application is implemented using a single application - * function that is called by uIP whenever a TCP/IP event occurs. The - * name of this function must be registered with uIP at compile time - * using the UIP_APPCALL definition. - * - * uIP applications can store the application state within the - * uip_conn structure by specifying the type of the application - * structure by typedef:ing the type uip_tcp_appstate_t and uip_udp_appstate_t. - * - * The file containing the definitions must be included in the - * uipopt.h file. - * - * The following example illustrates how this can look. - \code - -void httpd_appcall(void); -#define UIP_APPCALL httpd_appcall - -struct httpd_state { - u8_t state; - u16_t count; - char *dataptr; - char *script; -}; -typedef struct httpd_state uip_tcp_appstate_t - \endcode - */ - -/** - * \var #define UIP_APPCALL - * - * The name of the application function that uIP should call in - * response to TCP/IP events. - * - */ - -/** - * \var typedef uip_tcp_appstate_t - * - * The type of the application state that is to be stored in the - * uip_conn structure. This usually is typedef:ed to a struct holding - * application state information. - */ - -/** - * \var typedef uip_udp_appstate_t - * - * The type of the application state that is to be stored in the - * uip_conn structure. This usually is typedef:ed to a struct holding - * application state information. - */ -/** @} */ -/** @} */ - -#endif /* __UIPOPT_H__ */ diff --git a/Demo/Common/include/BlockQ.h b/Demo/Common/include/BlockQ.h deleted file mode 100644 index e27ea49c7..000000000 --- a/Demo/Common/include/BlockQ.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef BLOCK_Q_H -#define BLOCK_Q_H - -void vStartBlockingQueueTasks( unsigned portBASE_TYPE uxPriority ); -portBASE_TYPE xAreBlockingQueuesStillRunning( void ); - -#endif - - diff --git a/Demo/Common/include/PollQ.h b/Demo/Common/include/PollQ.h deleted file mode 100644 index c30d484e9..000000000 --- a/Demo/Common/include/PollQ.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef POLLED_Q_H -#define POLLED_Q_H - -void vStartPolledQueueTasks( unsigned portBASE_TYPE uxPriority ); -portBASE_TYPE xArePollingQueuesStillRunning( void ); - -#endif - - diff --git a/Demo/Common/include/blocktim.h b/Demo/Common/include/blocktim.h deleted file mode 100644 index b48ea27e1..000000000 --- a/Demo/Common/include/blocktim.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef BLOCK_TIME_TEST_H -#define BLOCK_TIME_TEST_H - -void vCreateBlockTimeTasks( void ); -portBASE_TYPE xAreBlockTimeTestTasksStillRunning( void ); - -#endif - - diff --git a/Demo/Common/include/comtest.h b/Demo/Common/include/comtest.h deleted file mode 100644 index fab7493a9..000000000 --- a/Demo/Common/include/comtest.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef COMTEST_H -#define COMTEST_H - -void vAltStartComTestTasks( unsigned portBASE_TYPE uxPriority, unsigned portLONG ulBaudRate, unsigned portBASE_TYPE uxLED ); -void vStartComTestTasks( unsigned portBASE_TYPE uxPriority, eCOMPort ePort, eBaud eBaudRate ); -portBASE_TYPE xAreComTestTasksStillRunning( void ); - -#endif - diff --git a/Demo/Common/include/comtest2.h b/Demo/Common/include/comtest2.h deleted file mode 100644 index 92109dde0..000000000 --- a/Demo/Common/include/comtest2.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef COMTEST_H -#define COMTEST_H - -void vAltStartComTestTasks( unsigned portBASE_TYPE uxPriority, unsigned portLONG ulBaudRate, unsigned portBASE_TYPE uxLED ); -portBASE_TYPE xAreComTestTasksStillRunning( void ); - -#endif - diff --git a/Demo/Common/include/crflash.h b/Demo/Common/include/crflash.h deleted file mode 100644 index 2665b774c..000000000 --- a/Demo/Common/include/crflash.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef CRFLASH_LED_H -#define CRFLASH_LED_H - -/* - * Create the co-routines used to flash the LED's at different rates. - * - * @param uxPriority The number of 'fixed delay' co-routines to create. This - * also effects the number of LED's that will be utilised. For example, - * passing in 3 will cause LED's 0 to 2 to be utilised. - */ -void vStartFlashCoRoutines( unsigned portBASE_TYPE uxPriority ); - -/* - * Return pdPASS or pdFAIL depending on whether an error has been detected - * or not. - */ -portBASE_TYPE xAreFlashCoRoutinesStillRunning( void ); - -#endif - diff --git a/Demo/Common/include/crhook.h b/Demo/Common/include/crhook.h deleted file mode 100644 index c65768ba4..000000000 --- a/Demo/Common/include/crhook.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef CRHOOK_H -#define CRHOOK_H - -/* - * Create the co-routines used to communicate wit the tick hook. - */ -void vStartHookCoRoutines( void ); - -/* - * Return pdPASS or pdFAIL depending on whether an error has been detected - * or not. - */ -portBASE_TYPE xAreHookCoRoutinesStillRunning( void ); - -#endif - diff --git a/Demo/Common/include/death.h b/Demo/Common/include/death.h deleted file mode 100644 index f5a33b434..000000000 --- a/Demo/Common/include/death.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef SUICIDE_TASK_H -#define SUICIDE_TASK_H - -void vCreateSuicidalTasks( unsigned portBASE_TYPE uxPriority ); -portBASE_TYPE xIsCreateTaskStillRunning( void ); - -#endif - - diff --git a/Demo/Common/include/dynamic.h b/Demo/Common/include/dynamic.h deleted file mode 100644 index bcd87273f..000000000 --- a/Demo/Common/include/dynamic.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef DYNAMIC_MANIPULATION_H -#define DYNAMIC_MANIPULATION_H - -void vStartDynamicPriorityTasks( void ); -portBASE_TYPE xAreDynamicPriorityTasksStillRunning( void ); - -#endif - - diff --git a/Demo/Common/include/fileIO.h b/Demo/Common/include/fileIO.h deleted file mode 100644 index 6d9f43bf1..000000000 --- a/Demo/Common/include/fileIO.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FILE_IO_H -#define FILE_OI_H - -void vDisplayMessage( const portCHAR * const pcMessageToPrint ); -void vWriteMessageToDisk( const portCHAR * const pcMessage ); -void vWriteBufferToDisk( const portCHAR * const pcBuffer, unsigned portLONG ulBufferLength ); - -#endif - diff --git a/Demo/Common/include/flash.h b/Demo/Common/include/flash.h deleted file mode 100644 index 646e97329..000000000 --- a/Demo/Common/include/flash.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FLASH_LED_H -#define FLASH_LED_H - -void vStartLEDFlashTasks( unsigned portBASE_TYPE uxPriority ); - -#endif - diff --git a/Demo/Common/include/flop.h b/Demo/Common/include/flop.h deleted file mode 100644 index 2cbfec71c..000000000 --- a/Demo/Common/include/flop.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FLOP_TASKS_H -#define FLOP_TASKS_H - -void vStartMathTasks( unsigned portBASE_TYPE uxPriority ); -portBASE_TYPE xAreMathsTaskStillRunning( void ); - -#endif - - diff --git a/Demo/Common/include/integer.h b/Demo/Common/include/integer.h deleted file mode 100644 index 73684b7ad..000000000 --- a/Demo/Common/include/integer.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef INTEGER_TASKS_H -#define INTEGER_TASKS_H - -void vStartIntegerMathTasks( unsigned portBASE_TYPE uxPriority ); -portBASE_TYPE xAreIntegerMathsTaskStillRunning( void ); - -#endif - - diff --git a/Demo/Common/include/mevents.h b/Demo/Common/include/mevents.h deleted file mode 100644 index e78cc5655..000000000 --- a/Demo/Common/include/mevents.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef EVENTS_TEST_H -#define EVENTS_TEST_H - -void vStartMultiEventTasks( void ); -portBASE_TYPE xAreMultiEventTasksStillRunning( void ); - -#endif - - diff --git a/Demo/Common/include/partest.h b/Demo/Common/include/partest.h deleted file mode 100644 index e17ff7579..000000000 --- a/Demo/Common/include/partest.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef PARTEST_H -#define PARTEST_H - -#define partstDEFAULT_PORT_ADDRESS ( ( unsigned portSHORT ) 0x378 ) - -void vParTestInitialise( void ); -void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ); -void vParTestToggleLED( unsigned portBASE_TYPE uxLED ); - -#endif - diff --git a/Demo/Common/include/print.h b/Demo/Common/include/print.h deleted file mode 100644 index c8a13e389..000000000 --- a/Demo/Common/include/print.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef PRINT_H -#define PRINT_H - -void vPrintInitialise( void ); -void vPrintDisplayMessage( const portCHAR * const * pcMessageToSend ); -const portCHAR *pcPrintGetNextMessage( portTickType xPrintRate ); - -#endif - - diff --git a/Demo/Common/include/semtest.h b/Demo/Common/include/semtest.h deleted file mode 100644 index 5f7d83c98..000000000 --- a/Demo/Common/include/semtest.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef SEMAPHORE_TEST_H -#define SEMAPHORE_TEST_H - -void vStartSemaphoreTasks( unsigned portBASE_TYPE uxPriority ); -portBASE_TYPE xAreSemaphoreTasksStillRunning( void ); - -#endif - diff --git a/Demo/Common/include/serial.h b/Demo/Common/include/serial.h deleted file mode 100644 index db26bd43a..000000000 --- a/Demo/Common/include/serial.h +++ /dev/null @@ -1,103 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef SERIAL_COMMS_H -#define SERIAL_COMMS_H - -typedef void * xComPortHandle; - -typedef enum -{ - serCOM1, - serCOM2, - serCOM3, - serCOM4, - serCOM5, - serCOM6, - serCOM7, - serCOM8 -} eCOMPort; - -typedef enum -{ - serNO_PARITY, - serODD_PARITY, - serEVEN_PARITY, - serMARK_PARITY, - serSPACE_PARITY -} eParity; - -typedef enum -{ - serSTOP_1, - serSTOP_2 -} eStopBits; - -typedef enum -{ - serBITS_5, - serBITS_6, - serBITS_7, - serBITS_8 -} eDataBits; - -typedef enum -{ - ser50, - ser75, - ser110, - ser134, - ser150, - ser200, - ser300, - ser600, - ser1200, - ser1800, - ser2400, - ser4800, - ser9600, - ser19200, - ser38400, - ser57600, - ser115200 -} eBaud; - -xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ); -xComPortHandle xSerialPortInit( eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits, unsigned portBASE_TYPE uxBufferLength ); -void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength ); -signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ); -signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ); -portBASE_TYPE xSerialWaitForSemaphore( xComPortHandle xPort ); -void vSerialClose( xComPortHandle xPort ); - -#endif - diff --git a/Demo/Cygnal/FreeRTOSConfig.h b/Demo/Cygnal/FreeRTOSConfig.h deleted file mode 100644 index 93db042a0..000000000 --- a/Demo/Cygnal/FreeRTOSConfig.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -#include "c8051f120.h" - -/* THE VALUE FOR configSTACK_START MUST BE OBTAINED FROM THE .MEM FILE. */ -#define configSTACK_START ( 0x0e ) - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 98000000 ) -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 200 - ( unsigned portSHORT ) configSTACK_START ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 6 * 1024 ) ) -#define configMAX_TASK_NAME_LEN ( 8 ) -#define configUSE_TRACE_FACILITY 0 -#define configUSE_16_BIT_TICKS 1 -#define configIDLE_SHOULD_YIELD 1 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 0 -#define INCLUDE_uxTaskPriorityGet 0 -#define INCLUDE_vTaskDelete 0 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 0 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 - - - - - - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/Cygnal/Makefile b/Demo/Cygnal/Makefile deleted file mode 100644 index fc340735a..000000000 --- a/Demo/Cygnal/Makefile +++ /dev/null @@ -1,101 +0,0 @@ -# FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. -# -# This file is part of the FreeRTOS.org distribution. -# -# FreeRTOS.org is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# FreeRTOS.org is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with FreeRTOS.org; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -# -# A special exception to the GPL can be applied should you wish to distribute -# a combined work that includes FreeRTOS.org, without being obliged to provide -# the source code for any proprietary components. See the licensing section -# of http://www.FreeRTOS.org for full details of how and when the exception -# can be applied. -# -# *************************************************************************** -# See http://www.FreeRTOS.org for documentation, latest information, license -# and contact details. Please ensure to read the configuration and relevant -# port sections of the online documentation. -# *************************************************************************** - - -CC=sdcc -NO_OPT=--nogcse --noinvariant --noinduction --nojtbound --noloopreverse --nolabelopt --nooverlay --peep-asm -DEBUG=--debug - -CFLAGS=--model-large -I. -I../Common/include -I../include -I../../Source/include \ - -DSDCC_CYGNAL $(DEBUG) --less-pedantic --xram-size 8448 --stack-auto \ - --no-peep --int-long-reent --float-reent - -DEMO_DIR = ../Common -SOURCE_DIR = ../../Source -PORT_DIR = ../../Source/portable/SDCC/Cygnal - -SRC = \ -ParTest/ParTest.c \ -serial/serial.c \ -$(DEMO_DIR)/Full/flash.c \ -$(DEMO_DIR)/Full/print.c \ -$(DEMO_DIR)/Minimal/integer.c \ -$(DEMO_DIR)/Minimal/PollQ.c \ -$(DEMO_DIR)/Minimal/comtest.c \ -$(DEMO_DIR)/Full/semtest.c \ -$(SOURCE_DIR)/tasks.c \ -$(SOURCE_DIR)/queue.c \ -$(SOURCE_DIR)/list.c \ -$(SOURCE_DIR)/portable/MemMang/heap_1.c \ -$(PORT_DIR)/port.c - - -# Define all object files. -OBJ = $(SRC:.c=.rel) - - - - - -###################################### -# THIS VERSION WILL ONLY BUILD FILES THAT HAVE CHANGED, BUT MAY HAVE A DANGEROUS -# COMMAND LINE. IT WORKS FINE UNDER WINDOWS, BUT I HAVE COMMENTED IT OUT IN -# CASE IT CAUSES PROBLEMS ON OTHER SYSTEMS. - -#main : main.c Makefile ../../Source/portable/SDCC/Cygnal/portmacro.h $(OBJ) -# $(CC) $(CFLAGS) main.c $(OBJ) - -#%.rel : %.c Makefile ../../Source/portable/SDCC/Cygnal/portmacro.h -# $(CC) -c $(CFLAGS) -o$< $< - - - - - -###################################### -# INSTEAD OF THE FOUR LINES ABOVE, THIS VERSION CAN BE USED BUT WILL CAUSE ALL -# FILES TO BUILD EVERY TIME. - -main : main.c Makefile ../../Source/portable/SDCC/Cygnal/portmacro.h $(OBJ) - $(CC) $(CFLAGS) main.c $(OBJ) - -%.rel : %.c Makefile ../../Source/portable/SDCC/Cygnal/portmacro.h - $(CC) -c $(CFLAGS) $< - - - - - - - - - - - diff --git a/Demo/Cygnal/ParTest/ParTest.c b/Demo/Cygnal/ParTest/ParTest.c deleted file mode 100644 index c1098d6de..000000000 --- a/Demo/Cygnal/ParTest/ParTest.c +++ /dev/null @@ -1,181 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ -#include - -#include "FreeRTOS.h" -#include "task.h" -#include "partest.h" - -#define partstPUSH_PULL ( ( unsigned portCHAR ) 0xff ) -#define partstALL_OUTPUTS_OFF ( ( unsigned portCHAR ) 0xff ) - -/* LED to output is dependent on how the LED's are wired. */ -#define partstOUTPUT_0 ( ( unsigned portCHAR ) 0x02 ) -#define partstOUTPUT_1 ( ( unsigned portCHAR ) 0x08 ) -#define partstOUTPUT_2 ( ( unsigned portCHAR ) 0x20 ) -#define partstOUTPUT_3 ( ( unsigned portCHAR ) 0x01 ) -#define partstOUTPUT_4 ( ( unsigned portCHAR ) 0x04 ) -#define partstOUTPUT_5 ( ( unsigned portCHAR ) 0x10 ) -#define partstOUTPUT_6 ( ( unsigned portCHAR ) 0x40 ) -#define partstOUTPUT_7 ( ( unsigned portCHAR ) 0x80 ) - -/*----------------------------------------------------------- - * Simple parallel port IO routines. - *-----------------------------------------------------------*/ - -void vParTestInitialise( void ) -{ -unsigned portCHAR ucOriginalSFRPage; - - /* Remember the SFR page before it is changed so it can get set back - before the function exits. */ - ucOriginalSFRPage = SFRPAGE; - - /* Setup the SFR page to access the config SFR's. */ - SFRPAGE = CONFIG_PAGE; - - /* Set the on board LED to push pull. */ - P3MDOUT |= partstPUSH_PULL; - - /* Return the SFR page. */ - SFRPAGE = ucOriginalSFRPage; - - P3 = partstALL_OUTPUTS_OFF; -} -/*-----------------------------------------------------------*/ - -void vParTestSetLED( unsigned portBASE_TYPE uxLED, portBASE_TYPE xValue ) -{ -portBASE_TYPE xError = pdFALSE; - - vTaskSuspendAll(); - { - if( xValue == pdFALSE ) - { - switch( uxLED ) - { - case 0 : P3 |= partstOUTPUT_0; - break; - case 1 : P3 |= partstOUTPUT_1; - break; - case 2 : P3 |= partstOUTPUT_2; - break; - case 3 : P3 |= partstOUTPUT_3; - break; - case 4 : P3 |= partstOUTPUT_4; - break; - case 5 : P3 |= partstOUTPUT_5; - break; - case 6 : P3 |= partstOUTPUT_6; - break; - case 7 : P3 |= partstOUTPUT_7; - break; - default : /* There are no other LED's wired in. */ - xError = pdTRUE; - break; - } - } - else - { - switch( uxLED ) - { - case 0 : P3 &= ~partstOUTPUT_0; - break; - case 1 : P3 &= ~partstOUTPUT_1; - break; - case 2 : P3 &= ~partstOUTPUT_2; - break; - case 3 : P3 &= ~partstOUTPUT_3; - break; - case 4 : P3 &= ~partstOUTPUT_4; - break; - case 5 : P3 &= ~partstOUTPUT_5; - break; - case 6 : P3 &= ~partstOUTPUT_6; - break; - case 7 : P3 &= ~partstOUTPUT_7; - break; - default : /* There are no other LED's wired in. */ - break; - } - } - } - xTaskResumeAll(); -} -/*-----------------------------------------------------------*/ - -void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) -{ -unsigned portCHAR ucBit; -portBASE_TYPE xError = pdFALSE; - - vTaskSuspendAll(); - { - switch( uxLED ) - { - case 0 : ucBit = partstOUTPUT_0; - break; - case 1 : ucBit = partstOUTPUT_1; - break; - case 2 : ucBit = partstOUTPUT_2; - break; - case 3 : ucBit = partstOUTPUT_3; - break; - case 4 : ucBit = partstOUTPUT_4; - break; - case 5 : ucBit = partstOUTPUT_5; - break; - case 6 : ucBit = partstOUTPUT_6; - break; - case 7 : ucBit = partstOUTPUT_7; - break; - default : /* There are no other LED's wired in. */ - xError = pdTRUE; - break; - } - - if( xError != pdTRUE ) - { - if( P3 & ucBit ) - { - P3 &= ~ucBit; - } - else - { - P3 |= ucBit; - } - } - } - xTaskResumeAll(); -} - - diff --git a/Demo/Cygnal/c8051f120.h b/Demo/Cygnal/c8051f120.h deleted file mode 100644 index ef9df9ad8..000000000 --- a/Demo/Cygnal/c8051f120.h +++ /dev/null @@ -1,456 +0,0 @@ -/*------------------------------------------------------------------------- - Register Declarations for the Cygnal C8051F12x Processor Range - - Copyright (C) 2003 - Maarten Brock, sourceforge.brock@dse.nl - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --------------------------------------------------------------------------*/ - -#ifndef C8051F120_H -#define C8051F120_H - - -/* BYTE Registers */ - -/* All Pages */ -sfr at 0x80 P0 ; /* PORT 0 */ -sfr at 0x81 SP ; /* STACK POINTER */ -sfr at 0x82 DPL ; /* DATA POINTER - LOW BYTE */ -sfr at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */ -sfr at 0x84 SFRPAGE ; /* SFR PAGE SELECT */ -sfr at 0x85 SFRNEXT ; /* SFR STACK NEXT PAGE */ -sfr at 0x86 SFRLAST ; /* SFR STACK LAST PAGE */ -sfr at 0x87 PCON ; /* POWER CONTROL */ -sfr at 0x90 P1 ; /* PORT 1 */ -sfr at 0xA0 P2 ; /* PORT 2 */ -sfr at 0xA8 IE ; /* INTERRUPT ENABLE */ -sfr at 0xB0 P3 ; /* PORT 3 */ -sfr at 0xB1 PSBANK ; /* FLASH BANK SELECT */ -sfr at 0xB8 IP ; /* INTERRUPT PRIORITY */ -sfr at 0xD0 PSW ; /* PROGRAM STATUS WORD */ -sfr at 0xE0 ACC ; /* ACCUMULATOR */ -sfr at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */ -sfr at 0xE7 EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */ -sfr at 0xF0 B ; /* B REGISTER */ -sfr at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */ -sfr at 0xF7 EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */ -sfr at 0xFF WDTCN ; /* WATCHDOG TIMER CONTROL */ - -/* Page 0x00 */ -sfr at 0x88 TCON ; /* TIMER CONTROL */ -sfr at 0x89 TMOD ; /* TIMER MODE */ -sfr at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */ -sfr at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */ -sfr at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */ -sfr at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */ -sfr at 0x8E CKCON ; /* TIMER 0/1 CLOCK CONTROL */ -sfr at 0x8F PSCTL ; /* FLASH WRITE/ERASE CONTROL */ -sfr at 0x91 SSTA0 ; /* UART 0 STATUS */ -sfr at 0x98 SCON0 ; /* UART 0 CONTROL */ -sfr at 0x98 SCON ; /* UART 0 CONTROL */ -sfr at 0x99 SBUF0 ; /* UART 0 BUFFER */ -sfr at 0x99 SBUF ; /* UART 0 BUFFER */ -sfr at 0x9A SPI0CFG ; /* SPI 0 CONFIGURATION */ -sfr at 0x9B SPI0DAT ; /* SPI 0 DATA */ -sfr at 0x9D SPI0CKR ; /* SPI 0 CLOCK RATE CONTROL */ -sfr at 0xA1 EMI0TC ; /* EMIF TIMING CONTROL */ -sfr at 0xA2 EMI0CN ; /* EMIF CONTROL */ -sfr at 0xA2 _XPAGE ; /* XDATA/PDATA PAGE */ -sfr at 0xA3 EMI0CF ; /* EMIF CONFIGURATION */ -sfr at 0xA9 SADDR0 ; /* UART 0 SLAVE ADDRESS */ -sfr at 0xB7 FLSCL ; /* FLASH SCALE */ -sfr at 0xB9 SADEN0 ; /* UART 0 SLAVE ADDRESS MASK */ -sfr at 0xBA AMX0CF ; /* ADC 0 MUX CONFIGURATION */ -sfr at 0xBB AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */ -sfr at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */ -sfr at 0xBE ADC0L ; /* ADC 0 DATA - LOW BYTE */ -sfr at 0xBF ADC0H ; /* ADC 0 DATA - HIGH BYTE */ -sfr at 0xC0 SMB0CN ; /* SMBUS 0 CONTROL */ -sfr at 0xC1 SMB0STA ; /* SMBUS 0 STATUS */ -sfr at 0xC2 SMB0DAT ; /* SMBUS 0 DATA */ -sfr at 0xC3 SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */ -sfr at 0xC4 ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */ -sfr at 0xC5 ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */ -sfr at 0xC6 ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */ -sfr at 0xC7 ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */ -sfr at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */ -sfr at 0xC9 TMR2CF ; /* TIMER 2 CONFIGURATION */ -sfr at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ -sfr at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ -sfr at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */ -sfr at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */ -sfr at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */ -sfr at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */ -sfr at 0xCF SMB0CR ; /* SMBUS 0 CLOCK RATE */ -sfr at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */ -sfr at 0xD2 DAC0L ; /* DAC 0 REGISTER - LOW BYTE */ -sfr at 0xD3 DAC0H ; /* DAC 0 REGISTER - HIGH BYTE */ -sfr at 0xD4 DAC0CN ; /* DAC 0 CONTROL */ -sfr at 0xD8 PCA0CN ; /* PCA 0 COUNTER CONTROL */ -sfr at 0xD9 PCA0MD ; /* PCA 0 COUNTER MODE */ -sfr at 0xDA PCA0CPM0 ; /* PCA 0 MODULE 0 CONTROL */ -sfr at 0xDB PCA0CPM1 ; /* PCA 0 MODULE 1 CONTROL */ -sfr at 0xDC PCA0CPM2 ; /* PCA 0 MODULE 2 CONTROL */ -sfr at 0xDD PCA0CPM3 ; /* PCA 0 MODULE 3 CONTROL */ -sfr at 0xDE PCA0CPM4 ; /* PCA 0 MODULE 4 CONTROL */ -sfr at 0xDF PCA0CPM5 ; /* PCA 0 MODULE 5 CONTROL */ -sfr at 0xE1 PCA0CPL5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - LOW BYTE */ -sfr at 0xE2 PCA0CPH5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - HIGH BYTE */ -sfr at 0xE8 ADC0CN ; /* ADC 0 CONTROL */ -sfr at 0xE9 PCA0CPL2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - LOW BYTE */ -sfr at 0xEA PCA0CPH2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - HIGH BYTE */ -sfr at 0xEB PCA0CPL3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - LOW BYTE */ -sfr at 0xEC PCA0CPH3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - HIGH BYTE */ -sfr at 0xED PCA0CPL4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - LOW BYTE */ -sfr at 0xEE PCA0CPH4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - HIGH BYTE */ -sfr at 0xEF RSTSRC ; /* RESET SOURCE */ -sfr at 0xF8 SPI0CN ; /* SPI 0 CONTROL */ -sfr at 0xF9 PCA0L ; /* PCA 0 TIMER - LOW BYTE */ -sfr at 0xFA PCA0H ; /* PCA 0 TIMER - HIGH BYTE */ -sfr at 0xFB PCA0CPL0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - LOW BYTE */ -sfr at 0xFC PCA0CPH0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - HIGH BYTE */ -sfr at 0xFD PCA0CPL1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - LOW BYTE */ -sfr at 0xFE PCA0CPH1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - HIGH BYTE */ - -/* Page 0x01 */ -sfr at 0x88 CPT0CN ; /* COMPARATOR 0 CONTROL */ -sfr at 0x89 CPT0MD ; /* COMPARATOR 0 CONFIGURATION */ -sfr at 0x98 SCON1 ; /* UART 1 CONTROL */ -sfr at 0x99 SBUF1 ; /* UART 1 BUFFER */ -sfr at 0xC8 TMR3CN ; /* TIMER 3 CONTROL */ -sfr at 0xC9 TMR3CF ; /* TIMER 3 CONFIGURATION */ -sfr at 0xCA RCAP3L ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */ -sfr at 0xCB RCAP3H ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */ -sfr at 0xCC TMR3L ; /* TIMER 3 - LOW BYTE */ -sfr at 0xCD TMR3H ; /* TIMER 3 - HIGH BYTE */ -sfr at 0xD2 DAC1L ; /* DAC 1 REGISTER - LOW BYTE */ -sfr at 0xD3 DAC1H ; /* DAC 1 REGISTER - HIGH BYTE */ -sfr at 0xD4 DAC1CN ; /* DAC 1 CONTROL */ - -/* Page 0x02 */ -sfr at 0x88 CPT1CN ; /* COMPARATOR 1 CONTROL */ -sfr at 0x89 CPT1MD ; /* COMPARATOR 1 CONFIGURATION */ -sfr at 0xBA AMX2CF ; /* ADC 2 MUX CONFIGURATION */ -sfr at 0xBB AMX2SL ; /* ADC 2 MUX CHANNEL SELECTION */ -sfr at 0xBC ADC2CF ; /* ADC 2 CONFIGURATION */ -sfr at 0xBE ADC2 ; /* ADC 2 DATA */ -sfr at 0xC4 ADC2GT ; /* ADC 2 GREATER-THAN REGISTER */ -sfr at 0xC6 ADC2LT ; /* ADC 2 LESS-THAN REGISTER */ -sfr at 0xC8 TMR4CN ; /* TIMER 4 CONTROL */ -sfr at 0xC9 TMR4CF ; /* TIMER 4 CONFIGURATION */ -sfr at 0xCA RCAP4L ; /* TIMER 4 CAPTURE REGISTER - LOW BYTE */ -sfr at 0xCB RCAP4H ; /* TIMER 4 CAPTURE REGISTER - HIGH BYTE */ -sfr at 0xCC TMR4L ; /* TIMER 4 - LOW BYTE */ -sfr at 0xCD TMR4H ; /* TIMER 4 - HIGH BYTE */ - -/* Page 0x02 */ -sfr at 0x91 MAC0BL ; /* MAC0 B Register Low Byte */ -sfr at 0x92 MAC0BH ; /* MAC0 B Register High Byte */ -sfr at 0x93 MAC0ACC0 ; /* MAC0 Accumulator Byte 0 (LSB) */ -sfr at 0x94 MAC0ACC1 ; /* MAC0 Accumulator Byte 1 */ -sfr at 0x95 MAC0ACC2 ; /* MAC0 Accumulator Byte 2 */ -sfr at 0x96 MAC0ACC3 ; /* MAC0 Accumulator Byte 3 (MSB) */ -sfr at 0x97 MAC0OVR ; /* MAC0 Accumulator Overflow */ -sfr at 0xC0 MAC0STA ; /* MAC0 Status Register */ -sfr at 0xC1 MAC0AL ; /* MAC0 A Register Low Byte */ -sfr at 0xC2 MAC0AH ; /* MAC0 A Register High Byte */ -sfr at 0xC3 MAC0CF ; /* MAC0 Configuration */ -sfr at 0xCE MAC0RNDL ; /* MAC0 Rounding Register Low Byte */ -sfr at 0xCF MAC0RNDH ; /* MAC0 Rounding Register High Byte */ - -/* Page 0x0F */ -sfr at 0x88 FLSTAT ; /* FLASH STATUS */ -sfr at 0x89 PLL0CN ; /* PLL 0 CONTROL */ -sfr at 0x8A OSCICN ; /* INTERNAL OSCILLATOR CONTROL */ -sfr at 0x8B OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */ -sfr at 0x8C OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */ -sfr at 0x8D PLL0DIV ; /* PLL 0 DIVIDER */ -sfr at 0x8E PLL0MUL ; /* PLL 0 MULTIPLIER */ -sfr at 0x8F PLL0FLT ; /* PLL 0 FILTER */ -sfr at 0x96 SFRPGCN ; /* SFR PAGE CONTROL */ -sfr at 0x97 CLKSEL ; /* SYSTEM CLOCK SELECT */ -sfr at 0x9A CCH0MA ; /* CACHE MISS ACCUMULATOR */ -sfr at 0x9C P4MDOUT ; /* PORT 4 OUTPUT MODE */ -sfr at 0x9D P5MDOUT ; /* PORT 5 OUTPUT MODE */ -sfr at 0x9E P6MDOUT ; /* PORT 6 OUTPUT MODE */ -sfr at 0x9F P7MDOUT ; /* PORT 7 OUTPUT MODE */ -sfr at 0xA1 CCH0CN ; /* CACHE CONTROL */ -sfr at 0xA2 CCH0TN ; /* CACHE TUNING REGISTER */ -sfr at 0xA3 CCH0LC ; /* CACHE LOCK */ -sfr at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE */ -sfr at 0xA5 P1MDOUT ; /* PORT 1 OUTPUT MODE */ -sfr at 0xA6 P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */ -sfr at 0xA7 P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */ -sfr at 0xAD P1MDIN ; /* PORT 1 INPUT MODE */ -sfr at 0xB7 FLACL ; /* FLASH ACCESS LIMIT */ -sfr at 0xC8 P4 ; /* PORT 4 */ -sfr at 0xD8 P5 ; /* PORT 5 */ -sfr at 0xE1 XBR0 ; /* CROSSBAR CONFIGURATION REGISTER 0 */ -sfr at 0xE2 XBR1 ; /* CROSSBAR CONFIGURATION REGISTER 1 */ -sfr at 0xE3 XBR2 ; /* CROSSBAR CONFIGURATION REGISTER 2 */ -sfr at 0xE8 ADC2CN ; /* ADC 2 CONTROL */ -sfr at 0xE8 P6 ; /* PORT 6 */ -sfr at 0xF8 P7 ; /* PORT 7 */ - - -/* BIT Registers */ - -/* P0 0x80 */ -sbit at 0x80 P0_0 ; -sbit at 0x81 P0_1 ; -sbit at 0x82 P0_2 ; -sbit at 0x83 P0_3 ; -sbit at 0x84 P0_4 ; -sbit at 0x85 P0_5 ; -sbit at 0x86 P0_6 ; -sbit at 0x87 P0_7 ; - -/* TCON 0x88 */ -sbit at 0x88 IT0 ; /* EXT. INTERRUPT 0 TYPE */ -sbit at 0x89 IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */ -sbit at 0x8A IT1 ; /* EXT. INTERRUPT 1 TYPE */ -sbit at 0x8B IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */ -sbit at 0x8C TR0 ; /* TIMER 0 ON/OFF CONTROL */ -sbit at 0x8D TF0 ; /* TIMER 0 OVERFLOW FLAG */ -sbit at 0x8E TR1 ; /* TIMER 1 ON/OFF CONTROL */ -sbit at 0x8F TF1 ; /* TIMER 1 OVERFLOW FLAG */ - -/* CPT0CN 0x88 */ -sbit at 0x88 CP0HYN0 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 0 */ -sbit at 0x89 CP0HYN1 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 1 */ -sbit at 0x8A CP0HYP0 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 0 */ -sbit at 0x8B CP0HYP1 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 1 */ -sbit at 0x8C CP0FIF ; /* COMPARATOR 0 FALLING EDGE INTERRUPT */ -sbit at 0x8D CP0RIF ; /* COMPARATOR 0 RISING EDGE INTERRUPT */ -sbit at 0x8E CP0OUT ; /* COMPARATOR 0 OUTPUT */ -sbit at 0x8F CP0EN ; /* COMPARATOR 0 ENABLE */ - -/* CPT1CN 0x88 */ -sbit at 0x88 CP1HYN0 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 0 */ -sbit at 0x89 CP1HYN1 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 1 */ -sbit at 0x8A CP1HYP0 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 0 */ -sbit at 0x8B CP1HYP1 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 1 */ -sbit at 0x8C CP1FIF ; /* COMPARATOR 1 FALLING EDGE INTERRUPT */ -sbit at 0x8D CP1RIF ; /* COMPARATOR 1 RISING EDGE INTERRUPT */ -sbit at 0x8E CP1OUT ; /* COMPARATOR 1 OUTPUT */ -sbit at 0x8F CP1EN ; /* COMPARATOR 1 ENABLE */ - -/* FLSTAT 0x88 */ -sbit at 0x88 FLHBUSY ; /* FLASH BUSY */ - -/* SCON0 0x98 */ -sbit at 0x98 RI0 ; /* UART 0 RX INTERRUPT FLAG */ -sbit at 0x98 RI ; /* UART 0 RX INTERRUPT FLAG */ -sbit at 0x99 TI0 ; /* UART 0 TX INTERRUPT FLAG */ -sbit at 0x99 TI ; /* UART 0 TX INTERRUPT FLAG */ -sbit at 0x9A RB80 ; /* UART 0 RX BIT 8 */ -sbit at 0x9B TB80 ; /* UART 0 TX BIT 8 */ -sbit at 0x9C REN0 ; /* UART 0 RX ENABLE */ -sbit at 0x9C REN ; /* UART 0 RX ENABLE */ -sbit at 0x9D SM20 ; /* UART 0 MULTIPROCESSOR EN */ -sbit at 0x9E SM10 ; /* UART 0 MODE 1 */ -sbit at 0x9F SM00 ; /* UART 0 MODE 0 */ - -/* SCON1 0x98 */ -sbit at 0x98 RI1 ; /* UART 1 RX INTERRUPT FLAG */ -sbit at 0x99 TI1 ; /* UART 1 TX INTERRUPT FLAG */ -sbit at 0x9A RB81 ; /* UART 1 RX BIT 8 */ -sbit at 0x9B TB81 ; /* UART 1 TX BIT 8 */ -sbit at 0x9C REN1 ; /* UART 1 RX ENABLE */ -sbit at 0x9D MCE1 ; /* UART 1 MCE */ -sbit at 0x9F S1MODE ; /* UART 1 MODE */ - -/* IE 0xA8 */ -sbit at 0xA8 EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */ -sbit at 0xA9 ET0 ; /* TIMER 0 INTERRUPT ENABLE */ -sbit at 0xAA EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */ -sbit at 0xAB ET1 ; /* TIMER 1 INTERRUPT ENABLE */ -sbit at 0xAC ES0 ; /* UART0 INTERRUPT ENABLE */ -sbit at 0xAC ES ; /* UART0 INTERRUPT ENABLE */ -sbit at 0xAD ET2 ; /* TIMER 2 INTERRUPT ENABLE */ -sbit at 0xAF EA ; /* GLOBAL INTERRUPT ENABLE */ - -/* IP 0xB8 */ -sbit at 0xB8 PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */ -sbit at 0xB9 PT0 ; /* TIMER 0 PRIORITY */ -sbit at 0xBA PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */ -sbit at 0xBB PT1 ; /* TIMER 1 PRIORITY */ -sbit at 0xBC PS ; /* SERIAL PORT PRIORITY */ -sbit at 0xBD PT2 ; /* TIMER 2 PRIORITY */ - -/* SMB0CN 0xC0 */ -sbit at 0xC0 SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */ -sbit at 0xC1 SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */ -sbit at 0xC2 AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */ -sbit at 0xC3 SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */ -sbit at 0xC4 STO ; /* SMBUS 0 STOP FLAG */ -sbit at 0xC5 STA ; /* SMBUS 0 START FLAG */ -sbit at 0xC6 ENSMB ; /* SMBUS 0 ENABLE */ -sbit at 0xC7 BUSY ; /* SMBUS 0 BUSY */ - -/* TMR2CN 0xC8 */ -sbit at 0xC8 CPRL2 ; /* TIMER 2 CAPTURE SELECT */ -sbit at 0xC9 CT2 ; /* TIMER 2 COUNTER SELECT */ -sbit at 0xCA TR2 ; /* TIMER 2 ON/OFF CONTROL */ -sbit at 0xCB EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */ -sbit at 0xCE EXF2 ; /* TIMER 2 EXTERNAL FLAG */ -sbit at 0xCF TF2 ; /* TIMER 2 OVERFLOW FLAG */ - -/* TMR3CN 0xC8 */ -sbit at 0xC8 CPRL3 ; /* TIMER 3 CAPTURE SELECT */ -sbit at 0xC9 CT3 ; /* TIMER 3 COUNTER SELECT */ -sbit at 0xCA TR3 ; /* TIMER 3 ON/OFF CONTROL */ -sbit at 0xCB EXEN3 ; /* TIMER 3 EXTERNAL ENABLE FLAG */ -sbit at 0xCE EXF3 ; /* TIMER 3 EXTERNAL FLAG */ -sbit at 0xCF TF3 ; /* TIMER 3 OVERFLOW FLAG */ - -/* TMR4CN 0xC8 */ -sbit at 0xC8 CPRL4 ; /* TIMER 4 CAPTURE SELECT */ -sbit at 0xC9 CT4 ; /* TIMER 4 COUNTER SELECT */ -sbit at 0xCA TR4 ; /* TIMER 4 ON/OFF CONTROL */ -sbit at 0xCB EXEN4 ; /* TIMER 4 EXTERNAL ENABLE FLAG */ -sbit at 0xCE EXF4 ; /* TIMER 4 EXTERNAL FLAG */ -sbit at 0xCF TF4 ; /* TIMER 4 OVERFLOW FLAG */ - -/* P4 0xC8 */ -sbit at 0xC8 P4_0 ; -sbit at 0xC9 P4_1 ; -sbit at 0xCA P4_2 ; -sbit at 0xCB P4_3 ; -sbit at 0xCC P4_4 ; -sbit at 0xCD P4_5 ; -sbit at 0xCE P4_6 ; -sbit at 0xCF P4_7 ; - -/* PSW 0xD0 */ -sbit at 0xD0 P ; /* ACCUMULATOR PARITY FLAG */ -sbit at 0xD1 F1 ; /* USER FLAG 1 */ -sbit at 0xD2 OV ; /* OVERFLOW FLAG */ -sbit at 0xD3 RS0 ; /* REGISTER BANK SELECT 0 */ -sbit at 0xD4 RS1 ; /* REGISTER BANK SELECT 1 */ -sbit at 0xD5 F0 ; /* USER FLAG 0 */ -sbit at 0xD6 AC ; /* AUXILIARY CARRY FLAG */ -sbit at 0xD7 CY ; /* CARRY FLAG */ - -/* PCA0CN D8H */ -sbit at 0xD8 CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */ -sbit at 0xD9 CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */ -sbit at 0xDA CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */ -sbit at 0xDB CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */ -sbit at 0xDC CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */ -sbit at 0xDD CCF5 ; /* PCA 0 MODULE 5 INTERRUPT FLAG */ -sbit at 0xDE CR ; /* PCA 0 COUNTER RUN CONTROL BIT */ -sbit at 0xDF CF ; /* PCA 0 COUNTER OVERFLOW FLAG */ - -/* P5 0xD8 */ -sbit at 0xD8 P5_0 ; -sbit at 0xD9 P5_1 ; -sbit at 0xDA P5_2 ; -sbit at 0xDB P5_3 ; -sbit at 0xDC P5_4 ; -sbit at 0xDD P5_5 ; -sbit at 0xDE P5_6 ; -sbit at 0xDF P5_7 ; - -/* ADC0CN E8H */ -sbit at 0xE8 AD0LJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */ -sbit at 0xE9 AD0WINT ; /* ADC 0 WINDOW INTERRUPT FLAG */ -sbit at 0xEA AD0CM0 ; /* ADC 0 CONVERT START MODE BIT 0 */ -sbit at 0xEB AD0CM1 ; /* ADC 0 CONVERT START MODE BIT 1 */ -sbit at 0xEC AD0BUSY ; /* ADC 0 BUSY FLAG */ -sbit at 0xED AD0INT ; /* ADC 0 EOC INTERRUPT FLAG */ -sbit at 0xEE AD0TM ; /* ADC 0 TRACK MODE */ -sbit at 0xEF AD0EN ; /* ADC 0 ENABLE */ - -/* ADC2CN E8H */ -sbit at 0xE8 AD2WINT ; /* ADC 2 WINDOW INTERRUPT FLAG */ -sbit at 0xE9 AD2CM0 ; /* ADC 2 CONVERT START MODE BIT 0 */ -sbit at 0xEA AD2CM1 ; /* ADC 2 CONVERT START MODE BIT 1 */ -sbit at 0xEB AD2CM2 ; /* ADC 2 CONVERT START MODE BIT 2 */ -sbit at 0xEC AD2BUSY ; /* ADC 2 BUSY FLAG */ -sbit at 0xED AD2INT ; /* ADC 2 EOC INTERRUPT FLAG */ -sbit at 0xEE AD2TM ; /* ADC 2 TRACK MODE */ -sbit at 0xEF AD2EN ; /* ADC 2 ENABLE */ - -/* P6 0xE8 */ -sbit at 0xE8 P6_0 ; -sbit at 0xE9 P6_1 ; -sbit at 0xEA P6_2 ; -sbit at 0xEB P6_3 ; -sbit at 0xEC P6_4 ; -sbit at 0xED P6_5 ; -sbit at 0xEE P6_6 ; -sbit at 0xEF P6_7 ; - -/* SPI0CN F8H */ -sbit at 0xF8 SPIEN ; /* SPI 0 SPI ENABLE */ -sbit at 0xF9 TXBMT ; /* SPI 0 TX BUFFER EMPTY FLAG */ -sbit at 0xFA NSSMD0 ; /* SPI 0 SLAVE SELECT MODE 0 */ -sbit at 0xFB NSSMD1 ; /* SPI 0 SLAVE SELECT MODE 1 */ -sbit at 0xFC RXOVRN ; /* SPI 0 RX OVERRUN FLAG */ -sbit at 0xFD MODF ; /* SPI 0 MODE FAULT FLAG */ -sbit at 0xFE WCOL ; /* SPI 0 WRITE COLLISION FLAG */ -sbit at 0xFF SPIF ; /* SPI 0 INTERRUPT FLAG */ - -/* P7 0xF8 */ -sbit at 0xF8 P7_0 ; -sbit at 0xF9 P7_1 ; -sbit at 0xFA P7_2 ; -sbit at 0xFB P7_3 ; -sbit at 0xFC P7_4 ; -sbit at 0xFD P7_5 ; -sbit at 0xFE P7_6 ; -sbit at 0xFF P7_7 ; - - -/* Predefined SFR Bit Masks */ - -#define IDLE 0x01 /* PCON */ -#define STOP 0x02 /* PCON */ -#define ECCF 0x01 /* PCA0CPMn */ -#define PWM 0x02 /* PCA0CPMn */ -#define TOG 0x04 /* PCA0CPMn */ -#define MAT 0x08 /* PCA0CPMn */ -#define CAPN 0x10 /* PCA0CPMn */ -#define CAPP 0x20 /* PCA0CPMn */ -#define ECOM 0x40 /* PCA0CPMn */ -#define PWM16 0x80 /* PCA0CPMn */ -#define PORSF 0x02 /* RSTSRC */ -#define SWRSF 0x10 /* RSTSRC */ - - -/* SFR PAGE DEFINITIONS */ - -#define CONFIG_PAGE 0x0F /* SYSTEM AND PORT CONFIGURATION PAGE */ -#define LEGACY_PAGE 0x00 /* LEGACY SFR PAGE */ -#define TIMER01_PAGE 0x00 /* TIMER 0 AND TIMER 1 */ -#define CPT0_PAGE 0x01 /* COMPARATOR 0 */ -#define CPT1_PAGE 0x02 /* COMPARATOR 1 */ -#define UART0_PAGE 0x00 /* UART 0 */ -#define UART1_PAGE 0x01 /* UART 1 */ -#define SPI0_PAGE 0x00 /* SPI 0 */ -#define EMI0_PAGE 0x00 /* EXTERNAL MEMORY INTERFACE */ -#define ADC0_PAGE 0x00 /* ADC 0 */ -#define ADC2_PAGE 0x02 /* ADC 2 */ -#define SMB0_PAGE 0x00 /* SMBUS 0 */ -#define TMR2_PAGE 0x00 /* TIMER 2 */ -#define TMR3_PAGE 0x01 /* TIMER 3 */ -#define TMR4_PAGE 0x02 /* TIMER 4 */ -#define DAC0_PAGE 0x00 /* DAC 0 */ -#define DAC1_PAGE 0x01 /* DAC 1 */ -#define PCA0_PAGE 0x00 /* PCA 0 */ -#define PLL0_PAGE 0x0F /* PLL 0 */ - -#endif diff --git a/Demo/Cygnal/main.c b/Demo/Cygnal/main.c deleted file mode 100644 index 6e0e822d4..000000000 --- a/Demo/Cygnal/main.c +++ /dev/null @@ -1,563 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * Creates the demo application tasks, then starts the scheduler. The WEB - * documentation provides more details of the demo application tasks. - * - * Main. c also creates four other tasks: - * - * 1) vErrorChecks() - * This only executes every few seconds but has the highest priority so is - * guaranteed to get processor time. Its main function is to check that all - * the standard demo application tasks are still operational and have not - * experienced any errors. vErrorChecks() will toggle the on board LED - * every mainNO_ERROR_FLASH_PERIOD milliseconds if none of the demo application - * tasks have reported an error. Should any task report an error at any time - * the rate at which the on board LED is toggled is increased to - * mainERROR_FLASH_PERIOD - providing visual feedback that something has gone - * wrong. - * - * 2) vRegisterCheck() - * This is a very simple task that checks that all the registers are always - * in their expected state. The task only makes use of the A register, so - * all the other registers should always contain their initial values. - * An incorrect value indicates an error in the context switch mechanism. - * The task operates at the idle priority so will be preempted regularly. - * Any error will cause the toggle rate of the on board LED to increase to - * mainERROR_FLASH_PERIOD milliseconds. - * - * 3 and 4) vFLOPCheck1() and vFLOPCheck2() - * These are very basic versions of the standard FLOP tasks. They are good - * at detecting errors in the context switch mechanism, and also check that - * the floating point libraries are correctly built to be re-enterant. The - * stack restrictions of the 8051 prevent the use of the standard FLOP demo - * tasks. - */ - -/* Standard includes. */ -#include - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Demo application includes. */ -#include "partest.h" -#include "flash.h" -#include "integer.h" -#include "PollQ.h" -#include "comtest2.h" -#include "semtest.h" - -/* Demo task priorities. */ -#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainINTEGER_PRIORITY tskIDLE_PRIORITY - -/* Constants required to disable the watchdog. */ -#define mainDISABLE_BYTE_1 ( ( unsigned portCHAR ) 0xde ) -#define mainDISABLE_BYTE_2 ( ( unsigned portCHAR ) 0xad ) - -/* Constants to setup and use the on board LED. */ -#define ucLED_BIT ( ( unsigned portCHAR ) 0x40 ) -#define mainPORT_1_BIT_6 ( ( unsigned portCHAR ) 0x40 ) -#define mainENABLE_CROSS_BAR ( ( unsigned portCHAR ) 0x40 ) - -/* Constants to set the clock frequency. */ -#define mainSELECT_INTERNAL_OSC ( ( unsigned portCHAR ) 0x80 ) -#define mainDIVIDE_CLOCK_BY_1 ( ( unsigned portCHAR ) 0x03 ) -#define mainPLL_USES_INTERNAL_OSC ( ( unsigned portCHAR ) 0x04 ) -#define mainFLASH_READ_TIMING ( ( unsigned portCHAR ) 0x30 ) -#define mainPLL_POWER_ON ( ( unsigned portCHAR ) 0x01 ) -#define mainPLL_NO_PREDIVIDE ( ( unsigned portCHAR ) 0x01 ) -#define mainPLL_FILTER ( ( unsigned portCHAR ) 0x01 ) -#define mainPLL_MULTIPLICATION ( ( unsigned portCHAR ) 0x04 ) -#define mainENABLE_PLL ( ( unsigned portCHAR ) 0x02 ) -#define mainPLL_LOCKED ( ( unsigned portCHAR ) 0x10 ) -#define mainSELECT_PLL_AS_SOURCE ( ( unsigned portCHAR ) 0x02 ) - -/* Toggle rate for the on board LED - which is dependent on whether or not -an error has been detected. */ -#define mainNO_ERROR_FLASH_PERIOD ( ( portTickType ) 5000 ) -#define mainERROR_FLASH_PERIOD ( ( portTickType ) 250 ) - -/* Baud rate used by the serial port tasks. */ -#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 115200 ) - -/* Pass an invalid LED number to the COM test task as we don't want it to flash -an LED. There are only 8 LEDs (excluding the on board LED) wired in and these -are all used by the flash tasks. */ -#define mainCOM_TEST_LED ( 200 ) - -/* We want the Cygnal to act as much as possible as a standard 8052. */ -#define mainAUTO_SFR_OFF ( ( unsigned portCHAR ) 0 ) - -/* Constants required to setup the IO pins for serial comms. */ -#define mainENABLE_COMS ( ( unsigned portCHAR ) 0x04 ) -#define mainCOMS_LINES_TO_PUSH_PULL ( ( unsigned portCHAR ) 0x03 ) - -/* Pointer passed as a parameter to vRegisterCheck() just so it has some know -values to check for in the DPH, DPL and B registers. */ -#define mainDUMMY_POINTER ( ( xdata void * ) 0xabcd ) - -/* Macro that lets vErrorChecks() know that one of the tasks defined in -main. c has detected an error. A critical region is used around xLatchError -as it is accessed from vErrorChecks(), which has a higher priority. */ -#define mainLATCH_ERROR() \ -{ \ - portENTER_CRITICAL(); \ - xLatchedError = pdTRUE; \ - portEXIT_CRITICAL(); \ -} - -/* - * Setup the Cygnal microcontroller for its fastest operation. - */ -static void prvSetupSystemClock( void ); - -/* - * Setup the peripherals, including the on board LED. - */ -static void prvSetupHardware( void ); - -/* - * Toggle the state of the on board LED. - */ -static void prvToggleOnBoardLED( void ); - -/* - * See comments at the top of the file for details. - */ -static void vErrorChecks( void *pvParameters ); - -/* - * See comments at the top of the file for details. - */ -static void vRegisterCheck( void *pvParameters ); - -/* - * See comments at the top of the file for details. - */ -static void vFLOPCheck1( void *pvParameters ); - -/* - * See comments at the top of the file for details. - */ -static void vFLOPCheck2( void *pvParameters ); - -/* File scope variable used to communicate the occurrence of an error between -tasks. */ -static portBASE_TYPE xLatchedError = pdFALSE; - -/*-----------------------------------------------------------*/ - -/* - * Starts all the other tasks, then starts the scheduler. - */ -void main( void ) -{ - /* Initialise the hardware including the system clock and on board - LED. */ - prvSetupHardware(); - - /* Initialise the port that controls the external LED's utilized by the - flash tasks. */ - vParTestInitialise(); - - /* Start the used standard demo tasks. */ - vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartIntegerMathTasks( mainINTEGER_PRIORITY ); - vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - - /* Start the tasks defined in this file. The first three never block so - must not be used with the co-operative scheduler. */ - #if configUSE_PREEMPTION == 1 - { - xTaskCreate( vRegisterCheck, "RegChck", configMINIMAL_STACK_SIZE, mainDUMMY_POINTER, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL ); - xTaskCreate( vFLOPCheck1, "FLOP", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL ); - xTaskCreate( vFLOPCheck2, "FLOP", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL ); - } - #endif - - xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, ( xTaskHandle * ) NULL ); - - /* Finally kick off the scheduler. This function should never return. */ - vTaskStartScheduler(); - - /* Should never reach here as the tasks will now be executing under control - of the scheduler. */ -} -/*-----------------------------------------------------------*/ - -/* - * Setup the hardware prior to using the scheduler. Most of the Cygnal - * specific initialisation is performed here leaving standard 8052 setup - * only in the driver code. - */ -static void prvSetupHardware( void ) -{ -unsigned portCHAR ucOriginalSFRPage; - - /* Remember the SFR page before it is changed so it can get set back - before the function exits. */ - ucOriginalSFRPage = SFRPAGE; - - /* Setup the SFR page to access the config SFR's. */ - SFRPAGE = CONFIG_PAGE; - - /* Don't allow the microcontroller to automatically switch SFR page, as the - SFR page is not stored as part of the task context. */ - SFRPGCN = mainAUTO_SFR_OFF; - - /* Disable the watchdog. */ - WDTCN = mainDISABLE_BYTE_1; - WDTCN = mainDISABLE_BYTE_2; - - /* Set the on board LED to push pull. */ - P1MDOUT |= mainPORT_1_BIT_6; - - /* Setup the cross bar to enable serial comms here as it is not part of the - standard 8051 setup and therefore is not in the driver code. */ - XBR0 |= mainENABLE_COMS; - P0MDOUT |= mainCOMS_LINES_TO_PUSH_PULL; - - /* Enable the cross bar so our hardware setup takes effect. */ - XBR2 = mainENABLE_CROSS_BAR; - - /* Setup a fast system clock. */ - prvSetupSystemClock(); - - /* Return the SFR page. */ - SFRPAGE = ucOriginalSFRPage; -} -/*-----------------------------------------------------------*/ - -static void prvSetupSystemClock( void ) -{ -volatile unsigned portSHORT usWait; -const unsigned portSHORT usWaitTime = ( unsigned portSHORT ) 0x2ff; -unsigned portCHAR ucOriginalSFRPage; - - /* Remember the SFR page so we can set it back at the end. */ - ucOriginalSFRPage = SFRPAGE; - SFRPAGE = CONFIG_PAGE; - - /* Use the internal oscillator set to its fasted frequency. */ - OSCICN = mainSELECT_INTERNAL_OSC | mainDIVIDE_CLOCK_BY_1; - - /* Ensure the clock is stable. */ - for( usWait = 0; usWait < usWaitTime; usWait++ ); - - /* Setup the clock source for the PLL. */ - PLL0CN &= ~mainPLL_USES_INTERNAL_OSC; - - /* Change the read timing for the flash ready for the fast clock. */ - SFRPAGE = LEGACY_PAGE; - FLSCL |= mainFLASH_READ_TIMING; - - /* Turn on the PLL power. */ - SFRPAGE = CONFIG_PAGE; - PLL0CN |= mainPLL_POWER_ON; - - /* Don't predivide the clock. */ - PLL0DIV = mainPLL_NO_PREDIVIDE; - - /* Set filter for fastest clock. */ - PLL0FLT = mainPLL_FILTER; - PLL0MUL = mainPLL_MULTIPLICATION; - - /* Ensure the clock is stable. */ - for( usWait = 0; usWait < usWaitTime; usWait++ ); - - /* Enable the PLL and wait for it to lock. */ - PLL0CN |= mainENABLE_PLL; - for( usWait = 0; usWait < usWaitTime; usWait++ ) - { - if( PLL0CN & mainPLL_LOCKED ) - { - break; - } - } - - /* Select the PLL as the clock source. */ - CLKSEL |= mainSELECT_PLL_AS_SOURCE; - - /* Return the SFR back to its original value. */ - SFRPAGE = ucOriginalSFRPage; -} -/*-----------------------------------------------------------*/ - -static void prvToggleOnBoardLED( void ) -{ - /* If the on board LED is on, turn it off and visa versa. */ - if( P1 & ucLED_BIT ) - { - P1 &= ~ucLED_BIT; - } - else - { - P1 |= ucLED_BIT; - } -} -/*-----------------------------------------------------------*/ - -/* - * See the documentation at the top of this file. - */ -static void vErrorChecks( void *pvParameters ) -{ -portBASE_TYPE xErrorHasOccurred = pdFALSE; - - /* Just to prevent compiler warnings. */ - ( void ) pvParameters; - - /* Cycle for ever, delaying then checking all the other tasks are still - operating without error. The delay period depends on whether an error - has ever been detected. */ - for( ;; ) - { - if( xLatchedError == pdFALSE ) - { - /* No errors have been detected so delay for a longer period. The - on board LED will get toggled every mainNO_ERROR_FLASH_PERIOD ms. */ - vTaskDelay( mainNO_ERROR_FLASH_PERIOD ); - } - else - { - /* We have at some time recognised an error in one of the demo - application tasks, delay for a shorter period. The on board LED - will get toggled every mainERROR_FLASH_PERIOD ms. */ - vTaskDelay( mainERROR_FLASH_PERIOD ); - } - - - - /* Check the demo application tasks for errors. */ - - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - xErrorHasOccurred = pdTRUE; - } - - if( xArePollingQueuesStillRunning() != pdTRUE ) - { - xErrorHasOccurred = pdTRUE; - } - - if( xAreComTestTasksStillRunning() != pdTRUE ) - { - xErrorHasOccurred = pdTRUE; - } - - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - xErrorHasOccurred = pdTRUE; - } - - /* If an error has occurred, latch it to cause the LED flash rate to - increase. */ - if( xErrorHasOccurred == pdTRUE ) - { - xLatchedError = pdTRUE; - } - - /* Toggle the LED to indicate the completion of a check cycle. The - frequency of check cycles is dependent on whether or not we have - latched an error. */ - prvToggleOnBoardLED(); - } -} -/*-----------------------------------------------------------*/ - -/* - * See the documentation at the top of this file. Also see the standard FLOP - * demo task documentation for the rationale of these tasks. - */ -static void vFLOPCheck1( void *pvParameters ) -{ -volatile portFLOAT fVal1, fVal2, fResult; - - ( void ) pvParameters; - - for( ;; ) - { - fVal1 = ( portFLOAT ) -1234.5678; - fVal2 = ( portFLOAT ) 2345.6789; - - fResult = fVal1 + fVal2; - if( ( fResult > ( portFLOAT ) 1111.15 ) || ( fResult < ( portFLOAT ) 1111.05 ) ) - { - mainLATCH_ERROR(); - } - - fResult = fVal1 / fVal2; - if( ( fResult > ( portFLOAT ) -0.51 ) || ( fResult < ( portFLOAT ) -0.53 ) ) - { - mainLATCH_ERROR(); - } - } -} -/*-----------------------------------------------------------*/ - -/* - * See the documentation at the top of this file. - */ -static void vFLOPCheck2( void *pvParameters ) -{ -volatile portFLOAT fVal1, fVal2, fResult; - - ( void ) pvParameters; - - for( ;; ) - { - fVal1 = ( portFLOAT ) -12340.5678; - fVal2 = ( portFLOAT ) 23450.6789; - - fResult = fVal1 + fVal2; - if( ( fResult > ( portFLOAT ) 11110.15 ) || ( fResult < ( portFLOAT ) 11110.05 ) ) - { - mainLATCH_ERROR(); - } - - fResult = fVal1 / -fVal2; - if( ( fResult > ( portFLOAT ) 0.53 ) || ( fResult < ( portFLOAT ) 0.51 ) ) - { - mainLATCH_ERROR(); - } - } -} -/*-----------------------------------------------------------*/ - -/* - * See the documentation at the top of this file. - */ -static void vRegisterCheck( void *pvParameters ) -{ - ( void ) pvParameters; - - for( ;; ) - { - if( SP != configSTACK_START ) - { - mainLATCH_ERROR(); - } - - _asm - MOV ACC, ar0 - _endasm; - - if( ACC != 0 ) - { - mainLATCH_ERROR(); - } - - _asm - MOV ACC, ar1 - _endasm; - - if( ACC != 1 ) - { - mainLATCH_ERROR(); - } - _asm - MOV ACC, ar2 - _endasm; - - if( ACC != 2 ) - { - mainLATCH_ERROR(); - } - _asm - MOV ACC, ar3 - _endasm; - - if( ACC != 3 ) - { - mainLATCH_ERROR(); - } - _asm - MOV ACC, ar4 - _endasm; - - if( ACC != 4 ) - { - mainLATCH_ERROR(); - } - _asm - MOV ACC, ar5 - _endasm; - - if( ACC != 5 ) - { - mainLATCH_ERROR(); - } - _asm - MOV ACC, ar6 - _endasm; - - if( ACC != 6 ) - { - mainLATCH_ERROR(); - } - _asm - MOV ACC, ar7 - _endasm; - - if( ACC != 7 ) - { - mainLATCH_ERROR(); - } - - if( DPL != 0xcd ) - { - mainLATCH_ERROR(); - } - - if( DPH != 0xab ) - { - mainLATCH_ERROR(); - } - - if( B != 0x01 ) - { - mainLATCH_ERROR(); - } - } -} - - diff --git a/Demo/Cygnal/sdcc.wsp b/Demo/Cygnal/sdcc.wsp deleted file mode 100644 index 6cfbb7861..000000000 --- a/Demo/Cygnal/sdcc.wsp +++ /dev/null @@ -1,1670 +0,0 @@ -[WorkState_v1_1] -ptn_Child1=DockState -ptn_Child2=ToolBarMgr -ptn_Child3=Frames -ptn_Child4=ProjectTarget -ptn_Child5=WorkSpaceName -ptn_Child6=SerialPort -ptn_Child7=StepInc -ptn_Child8=DisassemblyAutoView -ptn_Child9=Watch0Base -ptn_Child10=Watch1Base -ptn_Child11=Vendor -ptn_Child12=Assembler -ptn_Child13=AssFlag -ptn_Child14=AssFormat -ptn_Child15=Compiler -ptn_Child16=CompFlag -ptn_Child17=CompFormat -ptn_Child18=RunOptimizer -ptn_Child19=Linker -ptn_Child20=LinkFlag -ptn_Child21=LinkFormat -ptn_Child22=PreprocFlag -ptn_Child23=PreprocFormat -ptn_Child24=DisList -ptn_Child25=DisOP -ptn_Child26=ParseErr -ptn_Child27=Download -ptn_Child28=AutoSave -ptn_Child29=UseMake -ptn_Child30=ErrorFormat -ptn_Child31=ErrorString -ptn_Child32=MultiDeviceJTAG -ptn_Child33=BankingPN -ptn_Child34=OutputFile -ptn_Child35=MakeFile -ptn_Child36=CExt -ptn_Child37=IDEVer -ptn_Child38=ECProtocol -ptn_Child39=Adapter -ptn_Child40=PFiles -ptn_Child41=AFiles -ptn_Child42=CFiles -ptn_Child43=LFiles -ptn_Child44=BankMap -ptn_Child45=Folders -ptn_Child46=Demo App Files -ptn_Child47=FreeRTOS Files -ptn_Child48=CygnalCloseFileFlag -[WorkState_v1_1.DockState] -Bars=44 -ScreenCX=1600 -ScreenCY=1200 -ptn_Child1=Bar-0 -ptn_Child2=Bar-1 -ptn_Child3=Bar-2 -ptn_Child4=Bar-3 -ptn_Child5=Bar-4 -ptn_Child6=Bar-5 -ptn_Child7=Bar-6 -ptn_Child8=Bar-7 -ptn_Child9=Bar-8 -ptn_Child10=Bar-9 -ptn_Child11=Bar-10 -ptn_Child12=Bar-11 -ptn_Child13=Bar-12 -ptn_Child14=Bar-13 -ptn_Child15=Bar-14 -ptn_Child16=Bar-15 -ptn_Child17=Bar-16 -ptn_Child18=Bar-17 -ptn_Child19=Bar-18 -ptn_Child20=Bar-19 -ptn_Child21=Bar-20 -ptn_Child22=Bar-21 -ptn_Child23=Bar-22 -ptn_Child24=Bar-23 -ptn_Child25=Bar-24 -ptn_Child26=Bar-25 -ptn_Child27=Bar-26 -ptn_Child28=Bar-27 -ptn_Child29=Bar-28 -ptn_Child30=Bar-29 -ptn_Child31=Bar-30 -ptn_Child32=Bar-31 -ptn_Child33=Bar-32 -ptn_Child34=Bar-33 -ptn_Child35=Bar-34 -ptn_Child36=Bar-35 -ptn_Child37=Bar-36 -ptn_Child38=Bar-37 -ptn_Child39=Bar-38 -ptn_Child40=Bar-39 -ptn_Child41=Bar-40 -ptn_Child42=Bar-41 -ptn_Child43=Bar-42 -ptn_Child44=Bar-43 -[WorkState_v1_1.DockState.Bar-0] -BarID=59393 -Style=32768 -ExStyle=0 -PrevFloating=False -MDIChild=False -PctWidth=1000000 -MRUFloatCX=0 -MRUFloatCY=0 -MRUHorzDockCX=0 -MRUHorzDockCY=0 -MRUVertDockCX=0 -MRUVertDockCY=0 -MRUDockingState=0 -DockingStyle=0 -TypeID=0 -ClassName=SECStatusBar -WindowName=Ready -ResourceID=0 -[WorkState_v1_1.DockState.Bar-1] -BarID=59419 -Bars=9 -Bar#0=0 -Bar#1=59647 -Bar#2=0 -Bar#3=59392 -Bar#4=59399 -Bar#5=59398 -Bar#6=59400 -Bar#7=59397 -Bar#8=0 -Style=0 -ExStyle=0 -PrevFloating=False -MDIChild=False -PctWidth=0 -MRUFloatCX=0 -MRUFloatCY=0 -MRUHorzDockCX=0 -MRUHorzDockCY=0 -MRUVertDockCX=0 -MRUVertDockCY=0 -MRUDockingState=0 -DockingStyle=0 -TypeID=0 -ClassName= -WindowName= -ResourceID=0 -[WorkState_v1_1.DockState.Bar-2] -BarID=59422 -Bars=3 -Bar#0=0 -Bar#1=59139 -Bar#2=0 -Style=0 -ExStyle=0 -PrevFloating=False -MDIChild=False -PctWidth=0 -MRUFloatCX=0 -MRUFloatCY=0 -MRUHorzDockCX=0 -MRUHorzDockCY=0 -MRUVertDockCX=0 -MRUVertDockCY=0 -MRUDockingState=0 -DockingStyle=0 -TypeID=0 -ClassName= -WindowName= -ResourceID=0 -[WorkState_v1_1.DockState.Bar-3] -BarID=59420 -Bars=3 -Bar#0=0 -Bar#1=59140 -Bar#2=0 -Style=0 -ExStyle=0 -PrevFloating=False -MDIChild=False -PctWidth=0 -MRUFloatCX=0 -MRUFloatCY=0 -MRUHorzDockCX=0 -MRUHorzDockCY=0 -MRUVertDockCX=0 -MRUVertDockCY=0 -MRUDockingState=0 -DockingStyle=0 -TypeID=0 -ClassName= -WindowName= -ResourceID=0 -[WorkState_v1_1.DockState.Bar-4] -BarID=59421 -Bars=82 -Bar#0=0 -Bar#1=271 -Bar#2=270 -Bar#3=269 -Bar#4=268 -Bar#5=267 -Bar#6=266 -Bar#7=265 -Bar#8=264 -Bar#9=263 -Bar#10=262 -Bar#11=261 -Bar#12=260 -Bar#13=259 -Bar#14=258 -Bar#15=257 -Bar#16=256 -Bar#17=0 -Bar#18=0 -Bar#19=0 -Bar#20=0 -Bar#21=0 -Bar#22=0 -Bar#23=0 -Bar#24=0 -Bar#25=0 -Bar#26=0 -Bar#27=0 -Bar#28=0 -Bar#29=0 -Bar#30=0 -Bar#31=0 -Bar#32=0 -Bar#33=0 -Bar#34=0 -Bar#35=0 -Bar#36=0 -Bar#37=0 -Bar#38=0 -Bar#39=0 -Bar#40=0 -Bar#41=0 -Bar#42=0 -Bar#43=0 -Bar#44=0 -Bar#45=0 -Bar#46=0 -Bar#47=0 -Bar#48=0 -Bar#49=0 -Bar#50=0 -Bar#51=0 -Bar#52=0 -Bar#53=0 -Bar#54=0 -Bar#55=0 -Bar#56=0 -Bar#57=0 -Bar#58=0 -Bar#59=0 -Bar#60=0 -Bar#61=0 -Bar#62=0 -Bar#63=0 -Bar#64=0 -Bar#65=0 -Bar#66=62088 -Bar#67=62083 -Bar#68=62077 -Bar#69=62089 -Bar#70=62063 -Bar#71=62062 -Bar#72=62007 -Bar#73=61891 -Bar#74=61875 -Bar#75=61905 -Bar#76=62014 -Bar#77=61939 -Bar#78=61956 -Bar#79=61871 -Bar#80=59141 -Bar#81=0 -Style=0 -ExStyle=0 -PrevFloating=False -MDIChild=False -PctWidth=0 -MRUFloatCX=0 -MRUFloatCY=0 -MRUHorzDockCX=0 -MRUHorzDockCY=0 -MRUVertDockCX=0 -MRUVertDockCY=0 -MRUDockingState=0 -DockingStyle=0 -TypeID=0 -ClassName= -WindowName= -ResourceID=0 -[WorkState_v1_1.DockState.Bar-5] -BarID=59139 -XPos=1 -YPos=5 -Docking=True -MRUDockID=0 -MRUDockLeftPos=1 -MRUDockTopPos=5 -MRUDockRightPos=1600 -MRUDockBottomPos=193 -MRUFloatStyle=4 -MRUFloatXPos=-1 -MRUFloatYPos=0 -Style=36756 -ExStyle=3857 -PrevFloating=False -MDIChild=False -PctWidth=1000000 -MRUFloatCX=300 -MRUFloatCY=180 -MRUHorzDockCX=1599 -MRUHorzDockCY=188 -MRUVertDockCX=300 -MRUVertDockCY=180 -MRUDockingState=0 -DockingStyle=61440 -TypeID=0 -ClassName=OutputControlBar -WindowName=Output Window -ResourceID=0 -[WorkState_v1_1.DockState.Bar-6] -BarID=59141 -Visible=False -XPos=5 -YPos=-2 -Docking=True -MRUDockID=59421 -MRUDockLeftPos=5 -MRUDockTopPos=-2 -MRUDockRightPos=388 -MRUDockBottomPos=866 -MRUFloatStyle=4 -MRUFloatXPos=-1 -MRUFloatYPos=0 -Style=20372 -ExStyle=3857 -PrevFloating=False -MDIChild=False -PctWidth=1000000 -MRUFloatCX=300 -MRUFloatCY=180 -MRUHorzDockCX=300 -MRUHorzDockCY=180 -MRUVertDockCX=383 -MRUVertDockCY=868 -MRUDockingState=0 -DockingStyle=61440 -TypeID=0 -ClassName=WatchControlBar -WindowName=Watch Window -ResourceID=0 -[WorkState_v1_1.DockState.Bar-7] -BarID=59140 -XPos=0 -YPos=-2 -Docking=True -MRUDockID=0 -MRUDockLeftPos=0 -MRUDockTopPos=-2 -MRUDockRightPos=328 -MRUDockBottomPos=866 -MRUFloatStyle=4 -MRUFloatXPos=-1 -MRUFloatYPos=0 -Style=8084 -ExStyle=3857 -PrevFloating=False -MDIChild=False -PctWidth=1000000 -MRUFloatCX=300 -MRUFloatCY=180 -MRUHorzDockCX=300 -MRUHorzDockCY=180 -MRUVertDockCX=328 -MRUVertDockCY=868 -MRUDockingState=0 -DockingStyle=61440 -TypeID=0 -ClassName=ProjectWorkspaceWnd -WindowName=Project Workspace -ResourceID=0 -[WorkState_v1_1.DockState.Bar-8] -BarID=61871 -Visible=False -XPos=161 -YPos=718 -Docking=True -MRUDockID=59421 -MRUDockLeftPos=161 -MRUDockTopPos=718 -MRUDockRightPos=704 -MRUDockBottomPos=866 -MRUFloatStyle=4 -MRUFloatXPos=-1 -MRUFloatYPos=1160 -Style=20372 -ExStyle=3857 -PrevFloating=False -MDIChild=False -PctWidth=170523 -MRUFloatCX=300 -MRUFloatCY=180 -MRUHorzDockCX=300 -MRUHorzDockCY=180 -MRUVertDockCX=383 -MRUVertDockCY=148 -MRUDockingState=0 -DockingStyle=61440 -TypeID=0 -ClassName=MemWnd -WindowName=Memory Viewer -ResourceID=0 -[WorkState_v1_1.DockState.Bar-9] -BarID=61875 -Visible=False -XPos=207 -YPos=-2 -Docking=True -MRUDockID=59421 -MRUDockLeftPos=207 -MRUDockTopPos=-2 -MRUDockRightPos=532 -MRUDockBottomPos=428 -MRUFloatStyle=4 -MRUFloatXPos=-1 -MRUFloatYPos=1160 -Style=20372 -ExStyle=3857 -PrevFloating=False -MDIChild=False -PctWidth=500000 -MRUFloatCX=300 -MRUFloatCY=180 -MRUHorzDockCX=300 -MRUHorzDockCY=180 -MRUVertDockCX=383 -MRUVertDockCY=430 -MRUDockingState=0 -DockingStyle=61440 -TypeID=0 -ClassName=MemWnd -WindowName=Ram Viewer -ResourceID=0 -[WorkState_v1_1.DockState.Bar-10] -BarID=61956 -Visible=False -XPos=5 -YPos=-2 -Docking=True -MRUDockID=0 -MRUDockLeftPos=5 -MRUDockTopPos=-2 -MRUDockRightPos=388 -MRUDockBottomPos=284 -MRUFloatStyle=4 -MRUFloatXPos=-1 -MRUFloatYPos=1160 -Style=20372 -ExStyle=3857 -PrevFloating=False -MDIChild=False -PctWidth=333332 -MRUFloatCX=300 -MRUFloatCY=180 -MRUHorzDockCX=300 -MRUHorzDockCY=180 -MRUVertDockCX=383 -MRUVertDockCY=286 -MRUDockingState=0 -DockingStyle=61440 -TypeID=0 -ClassName=MemWnd -WindowName=External Ram Viewer -ResourceID=0 -[WorkState_v1_1.DockState.Bar-11] -BarID=61939 -Visible=False -XPos=0 -YPos=0 -Docking=True -MRUDockID=0 -MRUDockLeftPos=0 -MRUDockTopPos=0 -MRUDockRightPos=808464432 -MRUDockBottomPos=808464432 -MRUFloatStyle=4 -MRUFloatXPos=-1 -MRUFloatYPos=1160 -Style=20372 -ExStyle=3857 -PrevFloating=False -MDIChild=False -PctWidth=1000000 -MRUFloatCX=300 -MRUFloatCY=180 -MRUHorzDockCX=300 -MRUHorzDockCY=180 -MRUVertDockCX=383 -MRUVertDockCY=180 -MRUDockingState=0 -DockingStyle=61440 -TypeID=0 -ClassName=MemWnd -WindowName=Private Ram Viewer -ResourceID=0 -[WorkState_v1_1.DockState.Bar-12] -BarID=62014 -Visible=False -XPos=0 -YPos=0 -Docking=True -MRUDockID=0 -MRUDockLeftPos=0 -MRUDockTopPos=0 -MRUDockRightPos=808464432 -MRUDockBottomPos=808464432 -MRUFloatStyle=4 -MRUFloatXPos=-1 -MRUFloatYPos=1160 -Style=20372 -ExStyle=3857 -PrevFloating=False -MDIChild=False -PctWidth=1000000 -MRUFloatCX=300 -MRUFloatCY=180 -MRUHorzDockCX=300 -MRUHorzDockCY=180 -MRUVertDockCX=383 -MRUVertDockCY=180 -MRUDockingState=0 -DockingStyle=61440 -TypeID=0 -ClassName=MemWnd -WindowName=Scratch Pad Viewer -ResourceID=0 -[WorkState_v1_1.DockState.Bar-13] -BarID=61905 -Visible=False -XPos=5 -YPos=-2 -Docking=True -MRUDockID=0 -MRUDockLeftPos=5 -MRUDockTopPos=-2 -MRUDockRightPos=388 -MRUDockBottomPos=211 -MRUFloatStyle=4 -MRUFloatXPos=-1 -MRUFloatYPos=0 -Style=20372 -ExStyle=3857 -PrevFloating=False -MDIChild=False -PctWidth=250000 -MRUFloatCX=300 -MRUFloatCY=180 -MRUHorzDockCX=300 -MRUHorzDockCY=180 -MRUVertDockCX=383 -MRUVertDockCY=213 -MRUDockingState=0 -DockingStyle=61440 -TypeID=0 -ClassName=DissMemWnd -WindowName=Disassembly Window -ResourceID=0 -[WorkState_v1_1.DockState.Bar-14] -BarID=61891 -Visible=False -XPos=0 -YPos=0 -Docking=True -MRUDockID=0 -MRUDockLeftPos=0 -MRUDockTopPos=0 -MRUDockRightPos=0 -MRUDockBottomPos=0 -MRUFloatStyle=4 -MRUFloatXPos=-1 -MRUFloatYPos=0 -Style=20372 -ExStyle=3857 -PrevFloating=False -MDIChild=False -PctWidth=1000000 -MRUFloatCX=300 -MRUFloatCY=180 -MRUHorzDockCX=300 -MRUHorzDockCY=180 -MRUVertDockCX=353 -MRUVertDockCY=180 -MRUDockingState=0 -DockingStyle=61440 -TypeID=0 -ClassName=StackRegWnd -WindowName=Stack Viewer -ResourceID=0 -[WorkState_v1_1.DockState.Bar-15] -BarID=62007 -Visible=False -XPos=207 -YPos=-2 -Docking=True -MRUDockID=0 -MRUDockLeftPos=207 -MRUDockTopPos=-2 -MRUDockRightPos=578 -MRUDockBottomPos=866 -MRUFloatStyle=4 -MRUFloatXPos=-1 -MRUFloatYPos=0 -Style=20372 -ExStyle=3857 -PrevFloating=False -MDIChild=False -PctWidth=1000000 -MRUFloatCX=300 -MRUFloatCY=180 -MRUHorzDockCX=300 -MRUHorzDockCY=180 -MRUVertDockCX=383 -MRUVertDockCY=868 -MRUDockingState=0 -DockingStyle=61440 -TypeID=0 -ClassName=RnRegWnd -WindowName=Register Viewer -ResourceID=0 -[WorkState_v1_1.DockState.Bar-16] -BarID=62062 -Visible=False -XPos=0 -YPos=0 -Docking=True -MRUDockID=0 -MRUDockLeftPos=0 -MRUDockTopPos=0 -MRUDockRightPos=0 -MRUDockBottomPos=0 -MRUFloatStyle=4 -MRUFloatXPos=-1 -MRUFloatYPos=0 -Style=20372 -ExStyle=3857 -PrevFloating=False -MDIChild=False -PctWidth=1000000 -MRUFloatCX=300 -MRUFloatCY=180 -MRUHorzDockCX=300 -MRUHorzDockCY=180 -MRUVertDockCX=353 -MRUVertDockCY=180 -MRUDockingState=0 -DockingStyle=61440 -TypeID=0 -ClassName=CANRegWnd -WindowName=CAN SFR's -ResourceID=0 -[WorkState_v1_1.DockState.Bar-17] -BarID=62063 -Visible=False -XPos=0 -YPos=0 -Docking=True -MRUDockID=0 -MRUDockLeftPos=0 -MRUDockTopPos=0 -MRUDockRightPos=0 -MRUDockBottomPos=0 -MRUFloatStyle=4 -MRUFloatXPos=-1 -MRUFloatYPos=0 -Style=20372 -ExStyle=3857 -PrevFloating=False -MDIChild=False -PctWidth=1000000 -MRUFloatCX=300 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-DocPathName=E:\Dev\FreeRTOS\Demo\Cygnal\main.c -DocumentString=ide Document -DocTemplateIndex=0 -WindowPlacement=MCAAAAAAAAAAAAAABAAAAAAAPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPGDAAAAAAGDAAAAAAMPDAAAAAIFCAAAAA -IsActiveChildFrame=True -[WorkState_v1_1.ProjectTarget] -ProjectTarget=SC88F000 -[WorkState_v1_1.WorkSpaceName] -WorkSpaceName=E:\Dev\FreeRTOS\Demo\Cygnal\sdcc.wsp -[WorkState_v1_1.SerialPort] -SerialPort=1 -[WorkState_v1_1.StepInc] -StepInc=0 -[WorkState_v1_1.DisassemblyAutoView] -DisassemblyAutoView=0 -[WorkState_v1_1.Watch0Base] -Watch0Base=1 -[WorkState_v1_1.Watch1Base] -Watch1Base=1 -[WorkState_v1_1.Vendor] -Vendor=3 -[WorkState_v1_1.Assembler] -Assembler=D:\devtools\Cygnal\IDEfiles\C51\BIN\a51.exe -[WorkState_v1_1.AssFlag] -AssFlag=-f -i -s -[WorkState_v1_1.AssFormat] -AssFormat= -[WorkState_v1_1.Compiler] -Compiler=D:\devtools\Cygnal\IDEfiles\C51\BIN\C51.exe -[WorkState_v1_1.CompFlag] -CompFlag=-c -l -s m=3 -[WorkState_v1_1.CompFormat] -CompFormat= -[WorkState_v1_1.RunOptimizer] -RunOptimizer=0 -[WorkState_v1_1.Linker] -Linker=D:\devtools\Cygnal\IDEfiles\C51\BIN\bl51.exe -[WorkState_v1_1.LinkFlag] -LinkFlag=i=\mc\lib51\medium.lib -l l=\mc\lib51 -s -[WorkState_v1_1.LinkFormat] -LinkFormat= -[WorkState_v1_1.PreprocFlag] -PreprocFlag=-c -l -[WorkState_v1_1.PreprocFormat] -PreprocFormat= -[WorkState_v1_1.DisList] -DisList=1 -[WorkState_v1_1.DisOP] -DisOP=1 -[WorkState_v1_1.ParseErr] -ParseErr=1 -[WorkState_v1_1.Download] -Download=0 -[WorkState_v1_1.AutoSave] -AutoSave=1 -[WorkState_v1_1.UseMake] -UseMake=1 -[WorkState_v1_1.ErrorFormat] -ErrorFormat=CS CS CS CS CS LN -[WorkState_v1_1.ErrorString] -ErrorString=%s %s %s %s %s %d -[WorkState_v1_1.MultiDeviceJTAG] -DevicesAfterTarget=0 -DevicesBeforeTarget=0 -BitsAfterTargetIR=0 -BitsBeforeTargetIR=0 -[WorkState_v1_1.BankingPN] -BankingPN=32767 -[WorkState_v1_1.OutputFile] -OutputFile=main. -[WorkState_v1_1.MakeFile] -MakeFile= -[WorkState_v1_1.CExt] -CExt=.obj -[WorkState_v1_1.IDEVer] -IDEVer=2.3 -[WorkState_v1_1.ECProtocol] -ECProtocol=0 -[WorkState_v1_1.Adapter] -Adapter=2 -[WorkState_v1_1.PFiles] -[WorkState_v1_1.AFiles] -[WorkState_v1_1.CFiles] -[WorkState_v1_1.LFiles] -[WorkState_v1_1.BankMap] -[WorkState_v1_1.Folders] -ptn_Child1=FolderName -[WorkState_v1_1.Folders.FolderName] -FolderName=Demo App Files -ptn_Child1=FolderName -[WorkState_v1_1.Folders.FolderName.FolderName] -FolderName=FreeRTOS Files -[WorkState_v1_1.Demo App Files] -ptn_Child1=FileName -[WorkState_v1_1.Demo App Files.FileName] -FileName=main.c -ptn_Child1=FileName -[WorkState_v1_1.Demo App Files.FileName.FileName] -FileName=serial\serial.c -ptn_Child1=FileName -[WorkState_v1_1.Demo App Files.FileName.FileName.FileName] -FileName=ParTest\ParTest.c -ptn_Child1=FileName -[WorkState_v1_1.Demo App Files.FileName.FileName.FileName.FileName] -FileName=E:\Dev\FreeRTOS\Demo\Common\Full\semtest.c -ptn_Child1=FileName -[WorkState_v1_1.Demo App Files.FileName.FileName.FileName.FileName.FileName] -FileName=E:\Dev\FreeRTOS\Demo\Common\Full\print.c -ptn_Child1=FileName -[WorkState_v1_1.Demo App Files.FileName.FileName.FileName.FileName.FileName.FileName] -FileName=E:\Dev\FreeRTOS\Demo\Common\Full\flash.c -ptn_Child1=FileName -[WorkState_v1_1.Demo App Files.FileName.FileName.FileName.FileName.FileName.FileName.FileName] -FileName=E:\Dev\FreeRTOS\Demo\Common\Minimal\comtest.c -ptn_Child1=FileName -[WorkState_v1_1.Demo App Files.FileName.FileName.FileName.FileName.FileName.FileName.FileName.FileName] -FileName=E:\Dev\FreeRTOS\Demo\Common\Minimal\integer.c -ptn_Child1=FileName -[WorkState_v1_1.Demo App Files.FileName.FileName.FileName.FileName.FileName.FileName.FileName.FileName.FileName] -FileName=E:\Dev\FreeRTOS\Demo\Common\Minimal\PollQ.c -[WorkState_v1_1.FreeRTOS Files] -ptn_Child1=FileName -[WorkState_v1_1.FreeRTOS Files.FileName] -FileName=E:\Dev\FreeRTOS\Source\tasks.c -ptn_Child1=FileName -[WorkState_v1_1.FreeRTOS Files.FileName.FileName] -FileName=E:\Dev\FreeRTOS\Source\queue.c -ptn_Child1=FileName -[WorkState_v1_1.FreeRTOS Files.FileName.FileName.FileName] -FileName=E:\Dev\FreeRTOS\Source\list.c -ptn_Child1=FileName -[WorkState_v1_1.FreeRTOS Files.FileName.FileName.FileName.FileName] -FileName=E:\Dev\FreeRTOS\Source\portable\MemMang\heap_1.c -ptn_Child1=FileName -[WorkState_v1_1.FreeRTOS Files.FileName.FileName.FileName.FileName.FileName] -FileName=E:\Dev\FreeRTOS\Source\portable\SDCC\Cygnal\port.c diff --git a/Demo/Cygnal/serial/serial.c b/Demo/Cygnal/serial/serial.c deleted file mode 100644 index 98faf94b5..000000000 --- a/Demo/Cygnal/serial/serial.c +++ /dev/null @@ -1,215 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR DEMO PURPOSES */ -#include -#include "FreeRTOS.h" -#include "queue.h" -#include "task.h" -#include "serial.h" - -/* Constants required to setup the serial control register. */ -#define ser8_BIT_MODE ( ( unsigned portCHAR ) 0x40 ) -#define serRX_ENABLE ( ( unsigned portCHAR ) 0x10 ) - -/* Constants to setup the timer used to generate the baud rate. */ -#define serCLOCK_DIV_48 ( ( unsigned portCHAR ) 0x03 ) -#define serUSE_PRESCALED_CLOCK ( ( unsigned portCHAR ) 0x10 ) -#define ser8BIT_WITH_RELOAD ( ( unsigned portCHAR ) 0x20 ) -#define serSMOD ( ( unsigned portCHAR ) 0x10 ) - -static xQueueHandle xRxedChars; -static xQueueHandle xCharsForTx; - -data static unsigned portBASE_TYPE uxTxEmpty; - -/*-----------------------------------------------------------*/ - -xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) -{ -unsigned portLONG ulReloadValue; -const portFLOAT fBaudConst = ( portFLOAT ) configCPU_CLOCK_HZ * ( portFLOAT ) 2.0; -unsigned portCHAR ucOriginalSFRPage; - - portENTER_CRITICAL(); - { - ucOriginalSFRPage = SFRPAGE; - SFRPAGE = 0; - - uxTxEmpty = pdTRUE; - - /* Create the queues used by the com test task. */ - xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( portCHAR ) ); - xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( portCHAR ) ); - - /* Calculate the baud rate to use timer 1. */ - ulReloadValue = ( unsigned portLONG ) ( ( ( portFLOAT ) 256 - ( fBaudConst / ( portFLOAT ) ( 32 * ulWantedBaud ) ) ) + ( portFLOAT ) 0.5 ); - - /* Set timer one for desired mode of operation. */ - TMOD &= 0x08; - TMOD |= ser8BIT_WITH_RELOAD; - SSTA0 |= serSMOD; - - /* Set the reload and start values for the time. */ - TL1 = ( unsigned portCHAR ) ulReloadValue; - TH1 = ( unsigned portCHAR ) ulReloadValue; - - /* Setup the control register for standard n, 8, 1 - variable baud rate. */ - SCON = ser8_BIT_MODE | serRX_ENABLE; - - /* Enable the serial port interrupts */ - ES = 1; - - /* Start the timer. */ - TR1 = 1; - - SFRPAGE = ucOriginalSFRPage; - } - portEXIT_CRITICAL(); - - /* Unlike some ports, this serial code does not allow for more than one - com port. We therefore don't return a pointer to a port structure and can - instead just return NULL. */ - return NULL; -} -/*-----------------------------------------------------------*/ - -void vSerialISR( void ) interrupt 4 -{ -portCHAR cChar; -portBASE_TYPE xTaskWokenByRx = pdFALSE, xTaskWokenByTx = pdFALSE; - - /* 8051 port interrupt routines MUST be placed within a critical section - if taskYIELD() is used within the ISR! */ - - portENTER_CRITICAL(); - { - if( RI ) - { - /* Get the character and post it on the queue of Rxed characters. - If the post causes a task to wake force a context switch as the woken task - may have a higher priority than the task we have interrupted. */ - cChar = SBUF; - RI = 0; - - if( xQueueSendFromISR( xRxedChars, &cChar, pdFALSE ) ) - { - xTaskWokenByRx = ( portBASE_TYPE ) pdTRUE; - } - } - - if( TI ) - { - if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == ( portBASE_TYPE ) pdTRUE ) - { - /* Send the next character queued for Tx. */ - SBUF = cChar; - } - else - { - /* Queue empty, nothing to send. */ - uxTxEmpty = pdTRUE; - } - - TI = 0; - } - - if( xTaskWokenByRx || xTaskWokenByTx ) - { - portYIELD(); - } - } - portEXIT_CRITICAL(); -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) -{ - /* There is only one port supported. */ - ( void ) pxPort; - - /* Get the next character from the buffer. Return false if no characters - are available, or arrive before xBlockTime expires. */ - if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) - { - return ( portBASE_TYPE ) pdTRUE; - } - else - { - return ( portBASE_TYPE ) pdFALSE; - } -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) -{ -portBASE_TYPE xReturn; - - /* There is only one port supported. */ - ( void ) pxPort; - - portENTER_CRITICAL(); - { - if( uxTxEmpty == pdTRUE ) - { - SBUF = cOutChar; - uxTxEmpty = pdFALSE; - xReturn = ( portBASE_TYPE ) pdTRUE; - } - else - { - xReturn = xQueueSend( xCharsForTx, &cOutChar, xBlockTime ); - - if( xReturn == ( portBASE_TYPE ) pdFALSE ) - { - xReturn = ( portBASE_TYPE ) pdTRUE; - } - } - } - portEXIT_CRITICAL(); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -void vSerialClose( xComPortHandle xPort ) -{ - /* Not implemented in this port. */ - ( void ) xPort; -} -/*-----------------------------------------------------------*/ - - - - - diff --git a/Demo/Flshlite/FRConfig.h b/Demo/Flshlite/FRConfig.h deleted file mode 100644 index dde46f067..000000000 --- a/Demo/Flshlite/FRConfig.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -#include - -/*----------------------------------------------------------- - * Application specific definitions for the x86 port. - *----------------------------------------------------------*/ - -/* These are the only definitions that can be modified!. */ -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 10 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 ) /* This can be made smaller if required. */ -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 32 * 1024 ) ) -#define configMAX_TASK_NAME_LEN ( 16 ) -#define configUSE_TRACE_FACILITY 0 -#define configUSE_16_BIT_TICKS 1 -#define configIDLE_SHOULD_YIELD 1 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* The maximum number of characters a task name can take, -including the null terminator. */ -#define configMAX_TASK_NAME_LEN ( 16 ) - -/* Set the following definitions to 1 to include the component, or zero -to exclude the component. */ - -/* Include/exclude the stated API function. */ -#define INCLUDE_vTaskPrioritySet 0 -#define INCLUDE_uxTaskPriorityGet 0 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 1 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 - - -/* Use/don't use the trace visualisation. */ -#define configUSE_TRACE_FACILITY 0 - -/* - * The tick count (and times defined in tick count units) can be either a 16bit - * or a 32 bit value. See documentation on http://www.FreeRTOS.org to decide - * which to use. - */ -#define configUSE_16_BIT_TICKS 1 - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/Flshlite/FileIO/fileIO.c b/Demo/Flshlite/FileIO/fileIO.c deleted file mode 100644 index 73e97da74..000000000 --- a/Demo/Flshlite/FileIO/fileIO.c +++ /dev/null @@ -1,106 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#include -#include -#include - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Demo program include files. */ -#include "fileio.h" - -void vDisplayMessage( const portCHAR * const pcMessageToPrint ) -{ - #ifdef USE_STDIO - taskENTER_CRITICAL(); - printf( "%s", pcMessageToPrint ); - fflush( stdout ); - taskEXIT_CRITICAL(); - #else - /* Stop warnings. */ - ( void ) pcMessageToPrint; - #endif -} -/*-----------------------------------------------------------*/ - -void vWriteMessageToDisk( const portCHAR * const pcMessage ) -{ -#ifdef USE_STDIO -const portCHAR * const pcFileName = "c:\\RTOSlog.txt"; -const portCHAR * const pcSeparator = "\r\n-----------------------\r\n"; -FILE *pf; - - taskENTER_CRITICAL(); - { - pf = fopen( pcFileName, "a" ); - if( pf != NULL ) - { - fwrite( pcMessage, strlen( pcMessage ), ( unsigned portSHORT ) 1, pf ); - fwrite( pcSeparator, strlen( pcSeparator ), ( unsigned portSHORT ) 1, pf ); - fclose( pf ); - } - } - taskEXIT_CRITICAL(); -#else - /* Stop warnings. */ - ( void ) pcMessage; -#endif /*USE_STDIO*/ -} -/*-----------------------------------------------------------*/ - -void vWriteBufferToDisk( const portCHAR * const pcBuffer, unsigned portLONG ulBufferLength ) -{ -#ifdef USE_STDIO -const portCHAR * const pcFileName = "c:\\trace.bin"; -FILE *pf; - - taskENTER_CRITICAL(); - { - pf = fopen( pcFileName, "wb" ); - if( pf ) - { - fwrite( pcBuffer, ( size_t ) ulBufferLength, ( unsigned portSHORT ) 1, pf ); - fclose( pf ); - } - } - taskEXIT_CRITICAL(); -#else - /* Stop warnings. */ - ( void ) pcBuffer; - ( void ) ulBufferLength; -#endif /*USE_STDIO*/ -} - - diff --git a/Demo/Flshlite/FreeRTOSConfig.h b/Demo/Flshlite/FreeRTOSConfig.h deleted file mode 100644 index b2609b73d..000000000 --- a/Demo/Flshlite/FreeRTOSConfig.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -#include -#include - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 10 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 ) /* This can be made smaller if required. */ -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 32 * 1024 ) ) -#define configMAX_TASK_NAME_LEN ( 16 ) -#define configUSE_TRACE_FACILITY 0 -#define configUSE_16_BIT_TICKS 1 -#define configIDLE_SHOULD_YIELD 1 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 0 -#define INCLUDE_uxTaskPriorityGet 0 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 1 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 - - - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/Flshlite/ParTest/ParTest.c b/Demo/Flshlite/ParTest/ParTest.c deleted file mode 100644 index 6c38feecd..000000000 --- a/Demo/Flshlite/ParTest/ParTest.c +++ /dev/null @@ -1,130 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V1.01: - - + Types used updated. - + Add vParTestToggleLED(); - -Changes from V2.0.0 - - + Use scheduler suspends in place of critical sections. -*/ - - -#include "FreeRTOS.h" -#include "task.h" -#include "partest.h" - -#define partstALL_OUTPUTS_OFF ( ( unsigned portSHORT) 0x00 ) -#define partstMAX_OUTPUT_LED ( ( unsigned portCHAR ) 7 ) -#define partstPORT_F_ADDR ( ( unsigned portSHORT ) 0x605 ) -#define partstPORT_DIRECTION_REG ( ( unsigned portSHORT ) 0x606 ) -#define partstPORT_F_DIR_BIT ( ( unsigned portSHORT ) 0x20 ) - -/*lint -e956 File scope parameters okay here. */ -static volatile unsigned portCHAR ucCurrentOutputValue = partstALL_OUTPUTS_OFF; -/*lint +e956 */ - -/*----------------------------------------------------------- - * Simple parallel port IO routines. - *-----------------------------------------------------------*/ - -void vParTestInitialise( void ) -{ -unsigned portSHORT usInput; - - ucCurrentOutputValue = partstALL_OUTPUTS_OFF; - - /* Set the direction to output for port F. */ - usInput = portINPUT_BYTE( partstPORT_DIRECTION_REG ); - usInput |= partstPORT_F_DIR_BIT; - portOUTPUT_BYTE( partstPORT_DIRECTION_REG, usInput ); - - /* Start with all outputs off. */ - portOUTPUT_BYTE( partstPORT_F_ADDR, partstALL_OUTPUTS_OFF ); -} -/*-----------------------------------------------------------*/ - -void vParTestSetLED( unsigned portBASE_TYPE uxLED, portBASE_TYPE xValue ) -{ -unsigned portCHAR ucBit = ( unsigned portCHAR ) 1; - - if( uxLED <= partstMAX_OUTPUT_LED ) - { - ucBit <<= uxLED; - } - - vTaskSuspendAll(); - { - if( xValue == pdTRUE ) - { - ucBit ^= ( unsigned portCHAR ) 0xff; - ucCurrentOutputValue &= ucBit; - } - else - { - ucCurrentOutputValue |= ucBit; - } - - portOUTPUT_BYTE( partstPORT_F_ADDR, ( unsigned ) ucCurrentOutputValue ); - } - xTaskResumeAll(); -} -/*-----------------------------------------------------------*/ - -void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) -{ -unsigned portCHAR ucBit; - - if( uxLED <= partstMAX_OUTPUT_LED ) - { - ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED; - - vTaskSuspendAll(); - { - if( ucCurrentOutputValue & ucBit ) - { - ucCurrentOutputValue &= ~ucBit; - } - else - { - ucCurrentOutputValue |= ucBit; - } - - portOUTPUT_BYTE( partstPORT_F_ADDR, ( unsigned ) ucCurrentOutputValue ); - } - xTaskResumeAll(); - } -} - diff --git a/Demo/Flshlite/RTOSDEMO.IDE b/Demo/Flshlite/RTOSDEMO.IDE deleted file mode 100644 index 00741f4b4..000000000 Binary files a/Demo/Flshlite/RTOSDEMO.IDE and /dev/null differ diff --git a/Demo/Flshlite/main.c b/Demo/Flshlite/main.c deleted file mode 100644 index 8f2633cdc..000000000 --- a/Demo/Flshlite/main.c +++ /dev/null @@ -1,385 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * Creates all the demo application tasks, then starts the scheduler. - * - * Main. c also creates a task called "Print". This only executes every five - * seconds but has the highest priority so is guaranteed to get processor time. - * Its main function is to check that all the other tasks are still operational. - * Nearly all the tasks in the demo application maintain a unique count that is - * incremented each time the task successfully completes its function. Should any - * error occur within the task the count is permanently halted. The print task - * checks the count of each task to ensure it has changed since the last time the - * print task executed. If any count is found not to have changed the print task - * displays an appropriate message, halts, and flashes the on board LED rapidly. - * If all the tasks are still incrementing their unique counts the print task - * displays an "OK" message. - * - * The LED flash tasks do not maintain a count as they already provide visual - * feedback of their status. - * - * The print task blocks on the queue into which messages that require displaying - * are posted. It will therefore only block for the full 5 seconds if no messages - * are posted onto the queue. - * - * Main. c also provides a demonstration of how the trace visualisation utility can - * be used, and how the scheduler can be stopped. - * - * On the Flashlite it is preferable not to try to write to the console during - * real time operation. The built in LED is toggled every cycle of the print task - * that does not encounter any errors, so the console IO may be removed if required. - * The build in LED will start flashing rapidly if any task reports an error. - */ - -/* -Changes from V1.01: - - + Previously, if an error occurred in a task the on board LED was stopped from - toggling. Now if an error occurs the check task enters an infinite loop, - toggling the LED rapidly. - -Changes from V1.2.3 - - + The integer and comtest tasks are now used when the cooperative scheduler - is being used. Previously they were only used with the preemptive - scheduler. - -Changes from V1.2.5 - - + Made the communications RX task a higher priority. - -Changes from V2.0.0 - - + Delay periods are now specified using variables and constants of - portTickType rather than unsigned portLONG. -*/ - -#include -#include -#include "FreeRTOS.h" -#include "task.h" -#include "partest.h" -#include "serial.h" - -/* Demo file headers. */ -#include "BlockQ.h" -#include "PollQ.h" -#include "death.h" -#include "flash.h" -#include "integer.h" -#include "print.h" -#include "comtest.h" -#include "fileio.h" -#include "semtest.h" - -/* Priority definitions for all the tasks in the demo application. */ -#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainPRINT_TASK_PRIORITY ( tskIDLE_PRIORITY + 5 ) -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_BLOCK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainSEMAPHORE_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) - -#define mainPRINT_STACK_SIZE ( ( unsigned portSHORT ) 256 ) -#define mainDEBUG_LOG_BUFFER_SIZE ( ( unsigned portSHORT ) 20480 ) - -/* Constant definitions for accessing the build in LED on the Flashlite 186. */ -#define mainLED_REG_DIR ( ( unsigned portSHORT ) 0xff78 ) -#define mainLED_REG ( ( unsigned portSHORT ) 0xff7a ) - -/* If an error is detected in a task then the vErrorChecks() task will enter -an infinite loop flashing the LED at this rate. */ -#define mainERROR_FLASH_RATE ( ( portTickType ) 100 / portTICK_RATE_MS ) - -/* Task function for the "Print" task as described at the top of the file. */ -static void vErrorChecks( void *pvParameters ); - -/* Function that checks the unique count of all the other tasks as described at -the top of the file. */ -static void prvCheckOtherTasksAreStillRunning( void ); - -/* Functions to setup and use the built in LED on the Flashlite 186 board. */ -static void prvToggleLED( void ); -static void prvInitLED( void ); - -/* Key presses can be used to start/stop the trace visualisation utility or stop -the scheduler. */ -static void prvCheckForKeyPresses( void ); - -/* Buffer used by the trace visualisation utility. */ -static portCHAR pcWriteBuffer[ mainDEBUG_LOG_BUFFER_SIZE ]; - -/*-----------------------------------------------------------*/ -portSHORT main( void ) -{ - /* Initialise hardware and utilities. */ - vParTestInitialise(); - vPrintInitialise(); - prvInitLED(); - - /* CREATE ALL THE DEMO APPLICATION TASKS. */ - - vStartComTestTasks( mainCOM_TEST_PRIORITY, serCOM2, ser38400 ); - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartBlockingQueueTasks( mainQUEUE_BLOCK_PRIORITY ); - vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); - vStartSemaphoreTasks( mainSEMAPHORE_TASK_PRIORITY ); - - /* Create the "Print" task as described at the top of the file. */ - xTaskCreate( vErrorChecks, "Print", mainPRINT_STACK_SIZE, NULL, mainPRINT_TASK_PRIORITY, NULL ); - - /* This task has to be created last as it keeps account of the number of tasks - it expects to see running. */ - vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); - - /* Set the scheduler running. This function will not return unless a task - calls vTaskEndScheduler(). */ - vTaskStartScheduler(); - - return 1; -} -/*-----------------------------------------------------------*/ - -static void vErrorChecks( void *pvParameters ) -{ -portTickType xExpectedWakeTime; -const portTickType xPrintRate = ( portTickType ) 5000 / portTICK_RATE_MS; -const portLONG lMaxAllowableTimeDifference = ( portLONG ) 0; -portTickType xWakeTime; -portLONG lTimeDifference; -const portCHAR *pcReceivedMessage; -const portCHAR * const pcTaskBlockedTooLongMsg = "Print task blocked too long!\r\n"; - - /* Stop warnings. */ - ( void ) pvParameters; - - /* Loop continuously, blocking, then checking all the other tasks are still - running, before blocking once again. This task blocks on the queue of messages - that require displaying so will wake either by its time out expiring, or a - message becoming available. */ - for( ;; ) - { - /* Calculate the time we will unblock if no messages are received - on the queue. This is used to check that we have not blocked for too long. */ - xExpectedWakeTime = xTaskGetTickCount(); - xExpectedWakeTime += xPrintRate; - - /* Block waiting for either a time out or a message to be posted that - required displaying. */ - pcReceivedMessage = pcPrintGetNextMessage( xPrintRate ); - - /* Was a message received? */ - if( pcReceivedMessage == NULL ) - { - /* A message was not received so we timed out, did we unblock at the - expected time? */ - xWakeTime = xTaskGetTickCount(); - - /* Calculate the difference between the time we unblocked and the - time we should have unblocked. */ - if( xWakeTime > xExpectedWakeTime ) - { - lTimeDifference = ( portLONG ) ( xWakeTime - xExpectedWakeTime ); - } - else - { - lTimeDifference = ( portLONG ) ( xExpectedWakeTime - xWakeTime ); - } - - if( lTimeDifference > lMaxAllowableTimeDifference ) - { - /* We blocked too long - create a message that will get - printed out the next time around. */ - vPrintDisplayMessage( &pcTaskBlockedTooLongMsg ); - } - - /* Check the other tasks are still running, just in case. */ - prvCheckOtherTasksAreStillRunning(); - } - else - { - /* We unblocked due to a message becoming available. Send the message - for printing. */ - vDisplayMessage( pcReceivedMessage ); - } - - /* Key presses are used to invoke the trace visualisation utility, or - end the program. */ - prvCheckForKeyPresses(); - } -} /*lint !e715 !e818 pvParameters is not used but all task functions must take this form. */ -/*-----------------------------------------------------------*/ - -static void prvCheckForKeyPresses( void ) -{ - #ifdef USE_STDIO - - portSHORT sIn; - - - taskENTER_CRITICAL(); - sIn = kbhit(); - taskEXIT_CRITICAL(); - - if( sIn ) - { - unsigned portLONG ulBufferLength; - - /* Key presses can be used to start/stop the trace utility, or end the - program. */ - sIn = getch(); - switch( sIn ) - { - /* Only define keys for turning on and off the trace if the trace - is being used. */ - #if configUSE_TRACE_FACILITY == 1 - case 't' : vTaskList( pcWriteBuffer ); - vWriteMessageToDisk( pcWriteBuffer ); - break; - - case 's' : vTaskStartTrace( pcWriteBuffer, mainDEBUG_LOG_BUFFER_SIZE ); - break; - - case 'e' : ulBufferLength = ulTaskEndTrace(); - vWriteBufferToDisk( pcWriteBuffer, ulBufferLength ); - break; - #endif - - default : vTaskEndScheduler(); - break; - } - } - - #else - ( void ) pcWriteBuffer; - #endif -} -/*-----------------------------------------------------------*/ - -static void prvCheckOtherTasksAreStillRunning( void ) -{ -portSHORT sErrorHasOccurred = pdFALSE; - - if( xAreComTestTasksStillRunning() != pdTRUE ) - { - vDisplayMessage( "Com test count unchanged!\r\n" ); - sErrorHasOccurred = pdTRUE; - } - - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - vDisplayMessage( "Integer maths task count unchanged!\r\n" ); - sErrorHasOccurred = pdTRUE; - } - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - vDisplayMessage( "Blocking queues count unchanged!\r\n" ); - sErrorHasOccurred = pdTRUE; - } - - if( xArePollingQueuesStillRunning() != pdTRUE ) - { - vDisplayMessage( "Polling queue count unchanged!\r\n" ); - sErrorHasOccurred = pdTRUE; - } - - if( xIsCreateTaskStillRunning() != pdTRUE ) - { - vDisplayMessage( "Incorrect number of tasks running!\r\n" ); - sErrorHasOccurred = pdTRUE; - } - - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - vDisplayMessage( "Semaphore take count unchanged!\r\n" ); - sErrorHasOccurred = pdTRUE; - } - - if( sErrorHasOccurred == pdFALSE ) - { - vDisplayMessage( "OK " ); - /* Toggle the LED if everything is okay so we know if an error occurs even if not - using console IO. */ - prvToggleLED(); - } - else - { - for( ;; ) - { - /* An error has occurred in one of the tasks. Don't go any further and - flash the LED rapidly in case console IO is not being used. */ - prvToggleLED(); - vTaskDelay( mainERROR_FLASH_RATE ); - } - } -} -/*-----------------------------------------------------------*/ - -static void prvInitLED( void ) -{ -unsigned portSHORT usPortDirection; -const unsigned portSHORT usLEDOut = 0x400; - - /* Set the LED bit to an output. */ - - usPortDirection = inpw( mainLED_REG_DIR ); - usPortDirection &= ~usLEDOut; - outpw( mainLED_REG_DIR, usPortDirection ); -} -/*-----------------------------------------------------------*/ - -static void prvToggleLED( void ) -{ -static portSHORT sLED = pdTRUE; -unsigned portSHORT usLEDState; -const unsigned portSHORT usLEDBit = 0x400; - - /* Flip the state of the LED. */ - usLEDState = inpw( mainLED_REG ); - if( sLED ) - { - usLEDState &= ~usLEDBit; - } - else - { - usLEDState |= usLEDBit; - } - outpw( mainLED_REG, usLEDState ); - - sLED = !sLED; -} - - diff --git a/Demo/Flshlite/rtosdemo.DSW b/Demo/Flshlite/rtosdemo.DSW deleted file mode 100644 index 003116e97..000000000 Binary files a/Demo/Flshlite/rtosdemo.DSW and /dev/null differ diff --git a/Demo/Flshlite/rtosdemo.lk1 b/Demo/Flshlite/rtosdemo.lk1 deleted file mode 100644 index 9ce583f24..000000000 --- a/Demo/Flshlite/rtosdemo.lk1 +++ /dev/null @@ -1,2 +0,0 @@ -FIL list.obj,heap_2.obj,portcomn.obj,port.obj,queue.obj,tasks.obj,blockq.obj,comtest.obj,death.obj,flash.obj,integer.obj,pollq.obj,print.obj,semtest.obj,fileio.obj,main.obj,partest.obj,serial.obj - diff --git a/Demo/Flshlite/rtosdemo.mk b/Demo/Flshlite/rtosdemo.mk deleted file mode 100644 index cc665e818..000000000 --- a/Demo/Flshlite/rtosdemo.mk +++ /dev/null @@ -1,3 +0,0 @@ -project : E:\Dev\FreeRTOS\Demo\Flshlite\rtosdemo.exe .SYMBOLIC - -!include E:\Dev\FreeRTOS\Demo\Flshlite\rtosdemo.mk1 diff --git a/Demo/Flshlite/rtosdemo.mk1 b/Demo/Flshlite/rtosdemo.mk1 deleted file mode 100644 index 789b4302e..000000000 --- a/Demo/Flshlite/rtosdemo.mk1 +++ /dev/null @@ -1,191 +0,0 @@ -!define BLANK "" -E:\Dev\FreeRTOS\Demo\Flshlite\list.obj : E:\Dev\FreeRTOS\source\list.c .AUTO& -DEPEND - @E: - cd E:\Dev\FreeRTOS\Demo\Flshlite - *wcc ..\..\source\list.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..\..\& -source\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -za -s& - -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=dos -m& -l - -E:\Dev\FreeRTOS\Demo\Flshlite\heap_2.obj : E:\Dev\FreeRTOS\SOURCE\PORTABLE\M& -EMMANG\heap_2.c .AUTODEPEND - @E: - cd E:\Dev\FreeRTOS\Demo\Flshlite - *wcc ..\..\SOURCE\PORTABLE\MEMMANG\heap_2.c -i=D:\DEVTOOLS\OPENWA~1\h;..\co& -mmon\include;..\..\source\include;..\..\source\portable\owatcom\16bitdos\com& -mon -w4 -e25 -za -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fp& -c -zu -1 -bt=dos -ml - -E:\Dev\FreeRTOS\Demo\Flshlite\portcomn.obj : E:\Dev\FreeRTOS\source\portable& -\owatcom\16bitdos\common\portcomn.c .AUTODEPEND - @E: - cd E:\Dev\FreeRTOS\Demo\Flshlite - *wcc ..\..\source\portable\owatcom\16bitdos\common\portcomn.c -i=D:\DEVTOOL& -S\OPENWA~1\h;..\common\include;..\..\source\include;..\..\source\portable\ow& -atcom\16bitdos\common -w4 -e25 -za -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -& -zq -otexan -of -fpc -zu -1 -bt=dos -ml - -E:\Dev\FreeRTOS\Demo\Flshlite\port.obj : E:\Dev\FreeRTOS\source\portable\owa& -tcom\16bitdos\flsh186\port.c .AUTODEPEND - @E: - cd E:\Dev\FreeRTOS\Demo\Flshlite - *wcc ..\..\source\portable\owatcom\16bitdos\flsh186\port.c -i=D:\DEVTOOLS\O& -PENWA~1\h;..\common\include;..\..\source\include;..\..\source\portable\owatc& -om\16bitdos\common -w4 -e25 -za -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq & --otexan -of -fpc -zu -1 -bt=dos -ml - -E:\Dev\FreeRTOS\Demo\Flshlite\queue.obj : E:\Dev\FreeRTOS\source\queue.c .AU& -TODEPEND - @E: - cd E:\Dev\FreeRTOS\Demo\Flshlite - *wcc ..\..\source\queue.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..\..& -\source\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -za -& -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=dos -& -ml - -E:\Dev\FreeRTOS\Demo\Flshlite\tasks.obj : E:\Dev\FreeRTOS\source\tasks.c .AU& -TODEPEND - @E: - cd E:\Dev\FreeRTOS\Demo\Flshlite - *wcc ..\..\source\tasks.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..\..& -\source\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -za -& -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=dos -& -ml - -E:\Dev\FreeRTOS\Demo\Flshlite\blockq.obj : E:\Dev\FreeRTOS\Demo\common\full\& -blockq.c .AUTODEPEND - @E: - cd E:\Dev\FreeRTOS\Demo\Flshlite - *wcc ..\common\full\blockq.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..& -\..\source\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -z& -a -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=do& -s -ml - -E:\Dev\FreeRTOS\Demo\Flshlite\comtest.obj : E:\Dev\FreeRTOS\Demo\common\full& -\comtest.c .AUTODEPEND - @E: - cd E:\Dev\FreeRTOS\Demo\Flshlite - *wcc ..\common\full\comtest.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;.& -.\..\source\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -& -za -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=d& -os -ml - -E:\Dev\FreeRTOS\Demo\Flshlite\death.obj : E:\Dev\FreeRTOS\Demo\common\full\d& -eath.c .AUTODEPEND - @E: - cd E:\Dev\FreeRTOS\Demo\Flshlite - *wcc ..\common\full\death.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..\& -..\source\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -za& - -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=dos& - -ml - -E:\Dev\FreeRTOS\Demo\Flshlite\flash.obj : E:\Dev\FreeRTOS\Demo\common\full\f& -lash.c .AUTODEPEND - @E: - cd E:\Dev\FreeRTOS\Demo\Flshlite - *wcc ..\common\full\flash.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..\& -..\source\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -za& - -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=dos& - -ml - -E:\Dev\FreeRTOS\Demo\Flshlite\integer.obj : E:\Dev\FreeRTOS\Demo\common\full& -\integer.c .AUTODEPEND - @E: - cd E:\Dev\FreeRTOS\Demo\Flshlite - *wcc ..\common\full\integer.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;.& -.\..\source\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -& -za -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=d& -os -ml - -E:\Dev\FreeRTOS\Demo\Flshlite\pollq.obj : E:\Dev\FreeRTOS\Demo\common\full\p& -ollq.c .AUTODEPEND - @E: - cd E:\Dev\FreeRTOS\Demo\Flshlite - *wcc ..\common\full\pollq.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..\& -..\source\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -za& - -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=dos& - -ml - -E:\Dev\FreeRTOS\Demo\Flshlite\print.obj : E:\Dev\FreeRTOS\Demo\common\full\p& -rint.c .AUTODEPEND - @E: - cd E:\Dev\FreeRTOS\Demo\Flshlite - *wcc ..\common\full\print.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..\& -..\source\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -za& - -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=dos& - -ml - -E:\Dev\FreeRTOS\Demo\Flshlite\semtest.obj : E:\Dev\FreeRTOS\Demo\common\full& -\semtest.c .AUTODEPEND - @E: - cd E:\Dev\FreeRTOS\Demo\Flshlite - *wcc ..\common\full\semtest.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;.& -.\..\source\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -& -za -s -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=d& -os -ml - -E:\Dev\FreeRTOS\Demo\Flshlite\fileio.obj : E:\Dev\FreeRTOS\Demo\Flshlite\fil& -eio\fileio.c .AUTODEPEND - @E: - cd E:\Dev\FreeRTOS\Demo\Flshlite - *wcc fileio\fileio.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..\..\sour& -ce\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -za -s -dO& -PEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=dos -ml - -E:\Dev\FreeRTOS\Demo\Flshlite\main.obj : E:\Dev\FreeRTOS\Demo\Flshlite\main.& -c .AUTODEPEND - @E: - cd E:\Dev\FreeRTOS\Demo\Flshlite - *wcc main.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..\..\source\includ& -e;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -za -s -dOPEN_WATCO& -M_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=dos -ml - -E:\Dev\FreeRTOS\Demo\Flshlite\partest.obj : E:\Dev\FreeRTOS\Demo\Flshlite\pa& -rtest\partest.c .AUTODEPEND - @E: - cd E:\Dev\FreeRTOS\Demo\Flshlite - *wcc partest\partest.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..\..\so& -urce\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -za -s -& -dOPEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=dos -ml - -E:\Dev\FreeRTOS\Demo\Flshlite\serial.obj : E:\Dev\FreeRTOS\Demo\Flshlite\ser& -ial\serial.c .AUTODEPEND - @E: - cd E:\Dev\FreeRTOS\Demo\Flshlite - *wcc serial\serial.c -i=D:\DEVTOOLS\OPENWA~1\h;..\common\include;..\..\sour& -ce\include;..\..\source\portable\owatcom\16bitdos\common -w4 -e25 -za -s -dO& -PEN_WATCOM_FLASH_LITE_186_PORT -j -zq -otexan -of -fpc -zu -1 -bt=dos -ml - -E:\Dev\FreeRTOS\Demo\Flshlite\rtosdemo.exe : E:\Dev\FreeRTOS\Demo\Flshlite\l& -ist.obj E:\Dev\FreeRTOS\Demo\Flshlite\heap_2.obj E:\Dev\FreeRTOS\Demo\Flshli& -te\portcomn.obj E:\Dev\FreeRTOS\Demo\Flshlite\port.obj E:\Dev\FreeRTOS\Demo\& -Flshlite\queue.obj E:\Dev\FreeRTOS\Demo\Flshlite\tasks.obj E:\Dev\FreeRTOS\D& -emo\Flshlite\blockq.obj E:\Dev\FreeRTOS\Demo\Flshlite\comtest.obj E:\Dev\Fre& -eRTOS\Demo\Flshlite\death.obj E:\Dev\FreeRTOS\Demo\Flshlite\flash.obj E:\Dev& -\FreeRTOS\Demo\Flshlite\integer.obj E:\Dev\FreeRTOS\Demo\Flshlite\pollq.obj & -E:\Dev\FreeRTOS\Demo\Flshlite\print.obj E:\Dev\FreeRTOS\Demo\Flshlite\semtes& -t.obj E:\Dev\FreeRTOS\Demo\Flshlite\fileio.obj E:\Dev\FreeRTOS\Demo\Flshlite& -\main.obj E:\Dev\FreeRTOS\Demo\Flshlite\partest.obj E:\Dev\FreeRTOS\Demo\Fls& -hlite\serial.obj E:\Dev\FreeRTOS\source\include\list.h E:\Dev\FreeRTOS\sourc& -e\include\portable.h E:\Dev\FreeRTOS\source\include\projdefs.h E:\Dev\FreeRT& -OS\source\include\queue.h E:\Dev\FreeRTOS\source\include\semphr.h E:\Dev\Fre& -eRTOS\source\include\task.h E:\Dev\FreeRTOS\source\portable\owatcom\16bitdos& -\common\portasm.h E:\Dev\FreeRTOS\source\portable\owatcom\16bitdos\flsh186\p& -ortmacro.h E:\Dev\FreeRTOS\Demo\common\include\blockq.h E:\Dev\FreeRTOS\Demo& -\common\include\comtest.h E:\Dev\FreeRTOS\Demo\common\include\death.h E:\Dev& -\FreeRTOS\Demo\common\include\fileio.h E:\Dev\FreeRTOS\Demo\common\include\f& -lash.h E:\Dev\FreeRTOS\Demo\common\include\flop.h E:\Dev\FreeRTOS\Demo\commo& -n\include\partest.h E:\Dev\FreeRTOS\Demo\common\include\pollq.h E:\Dev\FreeR& -TOS\Demo\common\include\print.h E:\Dev\FreeRTOS\Demo\common\include\semtest.& -h E:\Dev\FreeRTOS\Demo\common\include\serial.h E:\Dev\FreeRTOS\Demo\Flshlite& -\FreeRTOSConfig.h .AUTODEPEND - @E: - cd E:\Dev\FreeRTOS\Demo\Flshlite - @%write rtosdemo.lk1 FIL list.obj,heap_2.obj,portcomn.obj,port.obj,queue.ob& -j,tasks.obj,blockq.obj,comtest.obj,death.obj,flash.obj,integer.obj,pollq.obj& -,print.obj,semtest.obj,fileio.obj,main.obj,partest.obj,serial.obj - @%append rtosdemo.lk1 - *wlink name rtosdemo SYS dos op m op maxe=25 op d op q op symf op el @rtosd& -emo.lk1 - diff --git a/Demo/Flshlite/rtosdemo.tgt b/Demo/Flshlite/rtosdemo.tgt deleted file mode 100644 index 367e27550..000000000 --- a/Demo/Flshlite/rtosdemo.tgt +++ /dev/null @@ -1,1159 +0,0 @@ -40 -targetIdent -0 -MProject -1 -MComponent -0 -2 -WString -3 -EXE -3 -WString -5 -de6en -1 -0 -0 -4 -MCommand -0 -5 -MCommand -0 -6 -MItem -12 -rtosdemo.exe -7 -WString -3 -EXE -8 -WVList -4 -9 -MRState -10 -WString -5 -WLINK -11 -WString -14 -?????Debug All -1 -0 -12 -MRState -13 -WString -5 -WLINK -14 -WString -16 -?????Debug Dwarf -1 -1 -15 -MCState -16 -WString -5 -WLINK -17 -WString -11 -?????Dosseg -0 -1 -18 -MCState -19 -WString -5 -WLINK -20 -WString -24 -?????Eliminate dead code -0 -1 -21 -WVList -2 -22 -ActionStates -23 -WString -6 -&Debug -24 -WVList -0 -25 -ActionStates -26 -WString -5 -&Make -27 -WVList -0 --1 -1 -1 -0 -28 -WPickList -40 -29 -MItem -3 -*.c -30 -WString -4 -COBJ -31 -WVList -26 -32 -MVState -33 -WString -3 -WCC -34 -WString -25 -d????Include directories: -1 -35 -WString -97 -$(%watcom)\h;..\common\include;..\..\source\include;..\..\source\portable\owatcom\16bitdos\common -0 -36 -MCState -37 -WString -3 -WCC -38 -WString -26 -?????Force ANSI compliance -1 -1 -39 -MCState -40 -WString -3 -WCC -41 -WString -33 -?????Disable stack depth checking -1 -1 -42 -MVState -43 -WString -3 -WCC -44 -WString -23 -?????Macro definitions: -1 -45 -WString -43 -OPEN_WATCOM_FLASH_LITE_186_PORT DEBUG_BUILD -0 -46 -MCState -47 -WString -3 -WCC -48 -WString -34 -?????Change char default to signed -1 -1 -49 -MRState -50 -WString -3 -WCC -51 -WString -21 -?????Compiler default -1 -0 -52 -MRState -53 -WString -3 -WCC -54 -WString -21 -?????Compiler default -1 -0 -55 -MRState -56 -WString -3 -WCC -57 -WString -25 -?????Floating-point calls -1 -1 -58 -MCState -59 -WString -3 -WCC -60 -WString -31 -???e?SS not assumed equal to DS -1 -1 -61 -MRState -62 -WString -3 -WCC -63 -WString -9 -??6??8086 -1 -0 -64 -MRState -65 -WString -3 -WCC -66 -WString -10 -??6??80186 -1 -1 -67 -MVState -68 -WString -3 -WCC -69 -WString -25 -d????Include directories: -0 -70 -WString -97 -$(%watcom)\h;..\common\include;..\..\source\include;..\..\source\portable\owatcom\16bitdos\common -0 -71 -MCState -72 -WString -3 -WCC -73 -WString -26 -?????Force ANSI compliance -0 -1 -74 -MCState -75 -WString -3 -WCC -76 -WString -33 -?????Disable stack depth checking -0 -1 -77 -MVState -78 -WString -3 -WCC -79 -WString -23 -?????Macro definitions: -0 -80 -WString -31 -OPEN_WATCOM_FLASH_LITE_186_PORT -0 -81 -MCState -82 -WString -3 -WCC -83 -WString -34 -?????Change char default to signed -0 -1 -84 -MRState -85 -WString -3 -WCC -86 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-263 -MItem -26 -..\common\include\serial.h -264 -WString -3 -NIL -265 -WVList -0 -266 -WVList -0 -187 -1 -1 -0 -267 -MItem -16 -FreeRTOSConfig.h -268 -WString -3 -NIL -269 -WVList -0 -270 -WVList -0 -187 -1 -1 -0 diff --git a/Demo/Flshlite/rtosdemo.wpj b/Demo/Flshlite/rtosdemo.wpj deleted file mode 100644 index c6a320465..000000000 --- a/Demo/Flshlite/rtosdemo.wpj +++ /dev/null @@ -1,43 +0,0 @@ -40 -projectIdent -0 -VpeMain -1 -WRect --25 --34 -10291 -10026 -2 -MProject -3 -MCommand -0 -4 -MCommand -0 -1 -5 -WFileName -12 -rtosdemo.tgt -6 -WVList -1 -7 -VComponent -8 -WRect -0 -0 -7200 -5888 -0 -0 -9 -WFileName -12 -rtosdemo.tgt -0 -19 -7 diff --git a/Demo/Flshlite/serial/serial.c b/Demo/Flshlite/serial/serial.c deleted file mode 100644 index ae61ded58..000000000 --- a/Demo/Flshlite/serial/serial.c +++ /dev/null @@ -1,480 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V1.00: - - + Call to the more efficient portSWITCH_CONTEXT() replaces the call to - taskYIELD() in the ISR. - -Changes from V1.01: - - + The semaphore task is not operational. This does nothing but check - the semaphore from ISR functionality. - + ISR modified slightly so only Rx or Tx is serviced per ISR - not both. - -Changes from V1.2.0: - - + Change so Tx uses a DMA channel, and Rx uses an interrupt. - -Changes from V1.2.3 - - + The function xPortInitMinimal() has been renamed to - xSerialPortInitMinimal() and the function xPortInit() has been renamed - to xSerialPortInit(). - -Changes from V1.2.5 - - + Reverted back to the non-DMA serial port driver, with a slightly modified - ISR. This is a better test of the scheduler mechanisms. - + A critical section is now used in vInterruptOn(). - + Flag sTxInterruptOn has been added to the port structure. This allows - checking of the interrupt enable status without performing any IO. - -Changes from V2.0.0 - - + Use portTickType in place of unsigned pdLONG for delay periods. - + Slightly more efficient vSerialSendString() implementation. - + cQueueReieveFromISR() used in place of xQueueReceive() in ISR. -*/ - -#include -#include -#include "FreeRTOS.h" -#include "queue.h" -#include "task.h" -#include "portasm.h" -#include "semphr.h" - -#define serMAX_PORTS ( ( unsigned portSHORT ) 2 ) - -#define serPORT_0_INT_REG ( 0xff44 ) -#define serPORT_0_BAUD_REG ( 0xff88 ) -#define serPORT_0_RX_REG ( 0xff86 ) -#define serPORT_0_TX_REG ( 0xff84 ) -#define serPORT_0_STATUS_REG ( 0xff82 ) -#define serPORT_0_CTRL_REG ( 0xff80 ) -#define serPORT_0_IRQ ( 0x14 ) - -#define serPORT_1_INT_REG ( 0xff42 ) -#define serPORT_1_BAUD_REG ( 0xff18 ) -#define serPORT_1_RX_REG ( 0xff16 ) -#define serPORT_1_TX_REG ( 0xff14 ) -#define serPORT_1_STATUS_REG ( 0xff12 ) -#define serPORT_1_CTRL_REG ( 0xff10 ) -#define serPORT_1_IRQ ( 0x11 ) - -#define serTX_EMPTY ( ( unsigned portSHORT ) 0x40 ) -#define serRX_READY ( ( unsigned portSHORT ) 0x80 ) - -#define serRESET_PIC( usEOI_TYPE ) portOUTPUT_WORD( ( unsigned portSHORT ) 0xff22, usEOI_TYPE ) -#define serTX_HOLD_EMPTY_INT ( ( unsigned portSHORT ) 0x100 ) - -#define serENABLE_INTERRUPTS ( ( unsigned portSHORT ) 0x80 ) -#define serMODE ( ( unsigned portSHORT ) 0x01 ) -#define serENABLE_TX_MACHINES ( ( unsigned portSHORT ) 0x40 ) -#define serENABLE_RX_MACHINES ( ( unsigned portSHORT ) 0x20 ) -#define serINTERRUPT_MASK ( ( unsigned portSHORT ) 0x08 ) -#define serCLEAR_ALL_STATUS_BITS ( ( unsigned portSHORT ) 0x00 ) -#define serINTERRUPT_PRIORITY ( ( unsigned portSHORT ) 0x01 ) /*< Just below the scheduler priority. */ - -#define serDONT_BLOCK ( ( portTickType ) 0 ) - -typedef enum -{ - serCOM1 = 0, - serCOM2, - serCOM3, - serCOM4, - serCOM5, - serCOM6, - serCOM7, - serCOM8 -} eCOMPort; - -typedef enum -{ - serNO_PARITY, - serODD_PARITY, - serEVEN_PARITY, - serMARK_PARITY, - serSPACE_PARITY -} eParity; - -typedef enum -{ - serSTOP_1, - serSTOP_2 -} eStopBits; - -typedef enum -{ - serBITS_5, - serBITS_6, - serBITS_7, - serBITS_8 -} eDataBits; - -typedef enum -{ - ser50 = 0, - ser75, - ser110, - ser134, - ser150, - ser200, - ser300, - ser600, - ser1200, - ser1800, - ser2400, - ser4800, - ser9600, - ser19200, - ser38400, - ser57600, - ser115200 -} eBaud; - -/* Must be same order as eBaud definitions. */ -static const unsigned portSHORT usBaudRateDivisor[] = -{ - 0, /* Not sure if the first 6 are correct. First cannot be used. */ - 29127, - 19859, - 16302, - 14564, - 10923, - 6879, - 3437, - 1718, - 1145, - 859, - 429, - 214, - 107, - 54, - 35, - 18 -}; - - -typedef struct xCOM_PORT -{ - /* Hardware parameters for this port. */ - portSHORT sTxInterruptOn; - unsigned portSHORT usIntReg; - unsigned portSHORT usBaudReg; - unsigned portSHORT usRxReg; - unsigned portSHORT usTxReg; - unsigned portSHORT usStatusReg; - unsigned portSHORT usCtrlReg; - - unsigned portSHORT usIRQVector; - - /* Queues used for communications with com test task. */ - xQueueHandle xRxedChars; - xQueueHandle xCharsForTx; - - /* This semaphore does nothing useful except test a feature of the - scheduler. */ - xSemaphoreHandle xTestSem; - -} xComPort; - -static xComPort xPorts[ serMAX_PORTS ] = -{ - { pdFALSE, serPORT_0_INT_REG, serPORT_0_BAUD_REG, serPORT_0_RX_REG, serPORT_0_TX_REG, serPORT_0_STATUS_REG, serPORT_0_CTRL_REG, serPORT_0_IRQ, NULL, NULL, NULL }, - { pdFALSE, serPORT_1_INT_REG, serPORT_1_BAUD_REG, serPORT_1_RX_REG, serPORT_1_TX_REG, serPORT_1_STATUS_REG, serPORT_1_CTRL_REG, serPORT_1_IRQ, NULL, NULL, NULL } -}; - -typedef xComPort * xComPortHandle; - -/* These prototypes are repeated here so we don't have to include the serial header. This allows -the xComPortHandle structure details to be private to this file. */ -xComPortHandle xSerialPortInit( eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits, unsigned portBASE_TYPE uxBufferLength ); -portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, portCHAR *pcRxedChar, portTickType xBlockTime ); -portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, portCHAR cOutChar, portTickType xBlockTime ); -void vSerialClose( xComPortHandle xPort ); -portSHORT sSerialWaitForSemaphore( xComPortHandle xPort ); -/*-----------------------------------------------------------*/ - -static portSHORT xComPortISR( xComPort * const pxPort ); - -#define vInterruptOn( pxPort, usInterrupt ) \ -{ \ -unsigned portSHORT usIn; \ - \ - portENTER_CRITICAL(); \ - { \ - if( pxPort->sTxInterruptOn == pdFALSE ) \ - { \ - usIn = portINPUT_WORD( pxPort->usCtrlReg ); \ - portOUTPUT_WORD( pxPort->usCtrlReg, usIn | usInterrupt ); \ - \ - pxPort->sTxInterruptOn = pdTRUE; \ - } \ - } \ - portEXIT_CRITICAL(); \ -} -/*-----------------------------------------------------------*/ - -#define vInterruptOff( pxPort, usInterrupt ) \ -{ \ - unsigned portSHORT usIn = portINPUT_WORD( pxPort->usCtrlReg ); \ - if( usIn & usInterrupt ) \ - { \ - portOUTPUT_WORD( pxPort->usCtrlReg, usIn & ~usInterrupt); \ - pxPort->sTxInterruptOn = pdFALSE; \ - } \ -} -/*-----------------------------------------------------------*/ - - -/* Define an interrupt handler for each port */ -#define COM_IRQ_WRAPPER(N) \ - static void __interrupt COM_IRQ##N##_WRAPPER( void ) \ - { \ - if( xComPortISR( &( xPorts[##N##] ) ) ) \ - { \ - portSWITCH_CONTEXT(); \ - } \ - } - - - -COM_IRQ_WRAPPER( 0 ) -COM_IRQ_WRAPPER( 1 ) - -static pxISR xISRs[ serMAX_PORTS ] = -{ - COM_IRQ0_WRAPPER, - COM_IRQ1_WRAPPER -}; - -/*-----------------------------------------------------------*/ - -xComPortHandle xSerialPortInit( eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits, unsigned portBASE_TYPE uxBufferLength ) -{ -unsigned portSHORT usPort; -xComPortHandle pxPort = NULL; - -/* BAUDDIV = ( Microprocessor Clock / Baud Rate ) / 16 */ - - /* Only n, 8, 1 is supported so these parameters are not required for this - port. */ - ( void ) eWantedParity; - ( void ) eWantedDataBits; - ( void ) eWantedStopBits; - - /* Currently only n,8,1 is supported. */ - - usPort = ( unsigned portSHORT ) ePort; - - if( usPort < serMAX_PORTS ) - { - pxPort = &( xPorts[ usPort ] ); - - portENTER_CRITICAL(); - { - unsigned portSHORT usInWord; - - /* Create the queues used by the com test task. */ - pxPort->xRxedChars = xQueueCreate( uxBufferLength, ( unsigned portBASE_TYPE ) sizeof( portCHAR ) ); - pxPort->xCharsForTx = xQueueCreate( uxBufferLength, ( unsigned portBASE_TYPE ) sizeof( portCHAR ) ); - - /* Create the test semaphore. This does nothing useful except test a feature of the scheduler. */ - vSemaphoreCreateBinary( pxPort->xTestSem ); - - /* There is no ISR here already to restore later. */ - _dos_setvect( ( portSHORT ) pxPort->usIRQVector, xISRs[ usPort ] ); - - usInWord = portINPUT_WORD( pxPort->usIntReg ); - usInWord &= ~serINTERRUPT_MASK; - usInWord |= serINTERRUPT_PRIORITY; - portOUTPUT_WORD( pxPort->usIntReg, usInWord ); - - portOUTPUT_WORD( pxPort->usBaudReg, usBaudRateDivisor[ eWantedBaud ] ); - portOUTPUT_WORD( pxPort->usCtrlReg, serENABLE_INTERRUPTS | serMODE | serENABLE_TX_MACHINES | serENABLE_RX_MACHINES ); - - portOUTPUT_WORD( pxPort->usStatusReg, serCLEAR_ALL_STATUS_BITS ); - } - portEXIT_CRITICAL(); - } - - return pxPort; -} /*lint !e715 Some parameters are not used as only a subset of the serial port functionality is currently implemented. */ -/*-----------------------------------------------------------*/ - -void vSerialPutString( xComPortHandle pxPort, const portCHAR * const pcString, unsigned portSHORT usStringLength ) -{ -unsigned portSHORT usByte; -portCHAR *pcNextChar; - - pcNextChar = ( portCHAR * ) pcString; - - for( usByte = 0; usByte < usStringLength; usByte++ ) - { - xQueueSend( pxPort->xCharsForTx, pcNextChar, serDONT_BLOCK ); - pcNextChar++; - } - - vInterruptOn( pxPort, serTX_HOLD_EMPTY_INT ); -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, portCHAR *pcRxedChar, portTickType xBlockTime ) -{ - /* Get the next character from the buffer, note that this routine is only - called having checked that the is (at least) one to get */ - if( xQueueReceive( pxPort->xRxedChars, pcRxedChar, xBlockTime ) ) - { - return pdTRUE; - } - else - { - return pdFALSE; - } -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, portCHAR cOutChar, portTickType xBlockTime ) -{ - if( xQueueSend( pxPort->xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) - { - return pdFAIL; - } - - vInterruptOn( pxPort, serTX_HOLD_EMPTY_INT ); - - return pdPASS; -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xSerialWaitForSemaphore( xComPortHandle xPort ) -{ -const portTickType xBlockTime = ( portTickType ) 0xffff; - - /* This function does nothing interesting, but test the - semaphore from ISR mechanism. */ - return xSemaphoreTake( xPort->xTestSem, xBlockTime ); -} -/*-----------------------------------------------------------*/ - -void vSerialClose( xComPortHandle xPort ) -{ -unsigned portSHORT usOutput; - - /* Turn off the interrupts. We may also want to delete the queues and/or - re-install the original ISR. */ - - portENTER_CRITICAL(); - { - usOutput = portINPUT_WORD( xPort->usCtrlReg ); - - usOutput &= ~serENABLE_INTERRUPTS; - usOutput &= ~serENABLE_TX_MACHINES; - usOutput &= ~serENABLE_RX_MACHINES; - portOUTPUT_WORD( xPort->usCtrlReg, usOutput ); - - usOutput = portINPUT_WORD( xPort->usIntReg ); - usOutput |= serINTERRUPT_MASK; - portOUTPUT_WORD( xPort->usIntReg, usOutput ); - } - portEXIT_CRITICAL(); -} -/*-----------------------------------------------------------*/ - -static portBASE_TYPE xComPortISR( xComPort * const pxPort ) -{ -unsigned portSHORT usStatusRegister; -portCHAR cChar; -portBASE_TYPE xTaskWokenByPost = pdFALSE, xAnotherTaskWokenByPost = pdFALSE, xTaskWokenByTx = pdFALSE, xContinue = pdTRUE; - - /* NOTE: THIS IS NOT AN EFFICIENT ISR AS IT IS DESIGNED SOLELY TO TEST - THE SCHEDULER FUNCTIONALITY. REAL APPLICATIONS SHOULD NOT USE THIS - FUNCTION. */ - - - while( xContinue == pdTRUE ) - { - xContinue = pdFALSE; - usStatusRegister = portINPUT_WORD( pxPort->usStatusReg ); - - if( usStatusRegister & serRX_READY ) - { - cChar = ( portCHAR ) portINPUT_WORD( pxPort->usRxReg ); - xTaskWokenByPost = xQueueSendFromISR( pxPort->xRxedChars, &cChar, xTaskWokenByPost ); - - /* Also release the semaphore - this does nothing interesting and is just a test. */ - xAnotherTaskWokenByPost = xSemaphoreGiveFromISR( pxPort->xTestSem, xAnotherTaskWokenByPost ); - - /* We have performed an action this cycle - there may be other to perform. */ - xContinue = pdTRUE; - } - - if( pxPort->sTxInterruptOn && ( usStatusRegister & serTX_EMPTY ) ) - { - if( xQueueReceiveFromISR( pxPort->xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE ) - { - portOUTPUT_WORD( pxPort->usTxReg, ( unsigned portSHORT ) cChar ); - - /* We have performed an action this cycle - there may be others to perform. */ - xContinue = pdTRUE; - } - else - { - /* Queue empty, nothing to send */ - vInterruptOff( pxPort, serTX_HOLD_EMPTY_INT ); - } - } - } - - serRESET_PIC( pxPort->usIRQVector ); - - /* If posting to the queue woke a task that was blocked on the queue we may - want to switch to the woken task - depending on its priority relative to - the task interrupted by this ISR. */ - if( xTaskWokenByPost || xAnotherTaskWokenByPost || xTaskWokenByTx) - { - return pdTRUE; - } - else - { - return pdFALSE; - } -} - - - - - diff --git a/Demo/H8S/RTOSDemo.hws b/Demo/H8S/RTOSDemo.hws deleted file mode 100644 index 8899830b2..000000000 --- a/Demo/H8S/RTOSDemo.hws +++ /dev/null @@ -1,38 +0,0 @@ -[HIMDBVersion] -2.0 -[DATABASE_VERSION] -"7.0" -[WORKSPACE_DETAILS] -"RTOSDemo" "C:\E\Dev\FreeRTOS\Demo\H8S" "C:\E\Dev\FreeRTOS\Demo\H8S\RTOSDemo.hws" "H8S,H8/300" "KPIT GNUH8 [ELF]" -[SHARED_WORKSPACE_CONTROL_STATUS] -"" "" "" -"" "" "" -[PROJECTS] -"RTOSDemo" "C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo" "C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\rtosdemo.hwp" 0 -[INFORMATION] -"No workspace information available" -[SCRAP] -[PROJECT_DEPENDENCY] -[WORKSPACE_PROPERTIES] -[VCS] -"" "" "" 0 -[VCS_PROJECT] -[HELP_FILES] -[GENERAL_DATA_PROJECT] -[SYSMENUTOOLS] -"GNUH8 Archive Editor" "1.1" -"Hitachi Mapview" "1.0" -"Hitachi H Series Librarian Interface" "1.1" -"Hitachi Call Walker" "1.1" -[USERMENUTOOLS] -[CUSTOMPLACEHOLDERS] -[MAKEFILE_BUILD_INFO] -"$(WORKSPDIR)\make\$(WORKSPNAME).mak" "" 0 0 -[VD_CONFIGURATION_OPTIONS] -"ACTIVE_DESKTOP" "0" -[VD_CONFIGURATIONS] -"0" "Default1" "1" -"1" "Default2" "1" -"2" "Default3" "1" -"3" "Default4" "1" -[END] diff --git a/Demo/H8S/RTOSDemo.tws b/Demo/H8S/RTOSDemo.tws deleted file mode 100644 index 8815cdd95..000000000 --- a/Demo/H8S/RTOSDemo.tws +++ /dev/null @@ -1,28 +0,0 @@ -[HIMDBVersion] -2.0 -[DATABASE_VERSION] -"1.0" -[CURRENT_PROJECT] -"RTOSDemo" -[GENERAL_DATA] -"EDITOR_WINDOWS_MAXIMISED" "1" -[BREAKPOINTS] -[OPEN_WORKSPACE_FILES] -"C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\partest\partest.c" -"c:\e\Dev\FreeRTOS\Source\queue.c" -"C:\E\Dev\FreeRTOS\Source\portable\GCC\H8S2329\portmacro.h" -"C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\serial\serial.c" -"c:\e\Dev\FreeRTOS\Source\portable\GCC\H8S2329\port.c" -"C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\main.c" -"C:\E\Dev\FreeRTOS\Source\include\portable.h" -"c:\e\Dev\FreeRTOS\Demo\Common\Minimal\BlockQ.c" -[WORKSPACE_FILE_STATES] -"c:\e\Dev\FreeRTOS\Demo\Common\Minimal\BlockQ.c" "0,0,954,459,0" -"C:\E\Dev\FreeRTOS\Source\include\portable.h" "44,66,958,463,0" -"C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\partest\partest.c" "-4,-34,1098,699,1" -"C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\main.c" "66,99,958,463,0" -"c:\e\Dev\FreeRTOS\Source\portable\GCC\H8S2329\port.c" "88,132,958,463,0" -"C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\serial\serial.c" "110,165,958,463,0" -"C:\E\Dev\FreeRTOS\Source\portable\GCC\H8S2329\portmacro.h" "132,198,958,463,0" -"c:\e\Dev\FreeRTOS\Source\queue.c" "0,0,958,463,0" -[END] diff --git a/Demo/H8S/RTOSDemo/2329S.h b/Demo/H8S/RTOSDemo/2329S.h deleted file mode 100644 index eafb53788..000000000 --- a/Demo/H8S/RTOSDemo/2329S.h +++ /dev/null @@ -1,142 +0,0 @@ -#ifndef INC_2329_H -#define INC_2329_H - -/* DATA TYPES MIGHT NOT BE CORRECT. */ - -#define BASE2329 0xFF0000 - -/* Definitions for GPIO. */ - -#define P1DDR ( *( ( volatile unsigned char * ) 0xFFFEB0 ) ) -#define P1DR ( *( ( volatile unsigned char * ) 0xFFFF60 ) ) -#define PORT1 ( *( ( volatile unsigned char * ) 0xFFFF50 ) ) -#define P2DDR ( *( ( volatile unsigned char * ) 0xFFFEB1 ) ) -#define P2DR ( *( ( volatile unsigned char * ) 0xFFFF61 ) ) -#define PORT2 ( *( ( volatile unsigned char * ) 0xFFFF51 ) ) -#define P3DDR ( *( ( volatile unsigned char * ) 0xFFFEB2 ) ) -#define P3DR ( *( ( volatile unsigned char * ) 0xFFFF62 ) ) -#define PORT3 ( *( ( volatile unsigned char * ) 0xFFFF52 ) ) -#define P3ODR ( *( ( volatile unsigned char * ) 0xFFFF76 ) ) -#define PORT4 ( *( ( volatile unsigned char * ) 0xFFFF53 ) ) -#define P5DDR ( *( ( volatile unsigned char * ) 0xFFFEB4 ) ) -#define P5DR ( *( ( volatile unsigned char * ) 0xFFFF64 ) ) -#define PORT5 ( *( ( volatile unsigned char * ) 0xFFFF54 ) ) -#define PFCR2 ( *( ( volatile unsigned char * ) 0xFFFFAC ) ) -#define SYSCR ( *( ( volatile unsigned char * ) 0xFFFF39 ) ) -#define P6DDR ( *( ( volatile unsigned char * ) 0xFFFEB5 ) ) -#define P6DR ( *( ( volatile unsigned char * ) 0xFFFF65 ) ) -#define PORT6 ( *( ( volatile unsigned char * ) 0xFFFF55 ) ) -#define PFCR2 ( *( ( volatile unsigned char * ) 0xFFFFAC ) ) -#define PADDR ( *( ( volatile unsigned char * ) 0xFFFEB9 ) ) -#define PADR ( *( ( volatile unsigned char * ) 0xFFFF69 ) ) -#define PORTA ( *( ( volatile unsigned char * ) 0xFFFF59 ) ) -#define PAPCR ( *( ( volatile unsigned char * ) 0xFFFF70 ) ) -#define PAODR ( *( ( volatile unsigned char * ) 0xFFFF77 ) ) -#define PFCR1 ( *( ( volatile unsigned char * ) 0xFFFF45 ) ) -#define PBDDR ( *( ( volatile unsigned char * ) 0xFFFEBA ) ) -#define PBDR ( *( ( volatile unsigned char * ) 0xFFFF6A ) ) -#define PORTB ( *( ( volatile unsigned char * ) 0xFFFF5A ) ) -#define PBPCR ( *( ( volatile unsigned char * ) 0xFFFF71 ) ) -#define PCDDR ( *( ( volatile unsigned char * ) 0xFFFEBB ) ) -#define PCDR ( *( ( volatile unsigned char * ) 0xFFFF6B ) ) -#define PORTC ( *( ( volatile unsigned char * ) 0xFFFF5B ) ) -#define PCPCR ( *( ( volatile unsigned char * ) 0xFFFF72 ) ) -#define PDDDR ( *( ( volatile unsigned char * ) 0xFFFEBC ) ) -#define PDDR ( *( ( volatile unsigned char * ) 0xFFFF6C ) ) -#define PORTD ( *( ( volatile unsigned char * ) 0xFFFF5C ) ) -#define PDPCR ( *( ( volatile unsigned char * ) 0xFFFF73 ) ) -#define PEDDR ( *( ( volatile unsigned char * ) 0xFFFEBD ) ) -#define PEDR ( *( ( volatile unsigned char * ) 0xFFFF6D ) ) -#define PORTE ( *( ( volatile unsigned char * ) 0xFFFF5D ) ) -#define PEPCR ( *( ( volatile unsigned char * ) 0xFFFF74 ) ) -#define PFDDR ( *( ( volatile unsigned char * ) 0xFFFEBE ) ) -#define PFDR ( *( ( volatile unsigned char * ) 0xFFFF6E ) ) -#define PORTF ( *( ( volatile unsigned char * ) 0xFFFF5E ) ) -#define PFCR2 ( *( ( volatile unsigned char * ) 0xFFFFAC ) ) -#define SYSCR ( *( ( volatile unsigned char * ) 0xFFFF39 ) ) -#define PGDDR ( *( ( volatile unsigned char * ) 0xFFFEBF ) ) -#define PGDR ( *( ( volatile unsigned char * ) 0xFFFF6F ) ) -#define PORTG ( *( ( volatile unsigned char * ) 0xFFFF5F ) ) -#define PFCR2 ( *( ( volatile unsigned char * ) 0xFFFFAC ) ) - - -/* Definitions for TPU. */ - -#define TCR0 ( *( ( volatile unsigned char * ) 0xFFFFD0 ) ) -#define TMDR0 ( *( ( volatile unsigned char * ) 0xFFFFD1 ) ) -#define TIOR0H ( *( ( volatile unsigned char * ) 0xFFFFD2 ) ) -#define TIOR0L ( *( ( volatile unsigned char * ) 0xFFFFD3 ) ) -#define TIER0 ( *( ( volatile unsigned char * ) 0xFFFFD4 ) ) -#define TSR0 ( *( ( volatile unsigned char * ) 0xFFFFD5 ) ) -#define TCNT0 ( *( ( volatile unsigned short * ) 0xFFFFD6 ) ) -#define TGR0A ( *( ( volatile unsigned short * ) 0xFFFFD8 ) ) -#define TGR0B ( *( ( volatile unsigned short * ) 0xFFFFDA ) ) -#define TGR0C ( *( ( volatile unsigned short * ) 0xFFFFDC ) ) -#define TGR0D ( *( ( volatile unsigned short * ) 0xFFFFDE ) ) -#define TCR1 ( *( ( volatile unsigned char * ) 0xFFFFE0 ) ) -#define TMDR1 ( *( ( volatile unsigned char * ) 0xFFFFE1 ) ) -#define TIOR1 ( *( ( volatile unsigned char * ) 0xFFFFE2 ) ) -#define TIER1 ( *( ( volatile unsigned char * ) 0xFFFFE4 ) ) -#define TSR1 ( *( ( volatile unsigned char * ) 0xFFFFE5 ) ) -#define TCNT1 ( *( ( volatile unsigned short * ) 0xFFFFE6 ) ) -#define TGR1A ( *( ( volatile unsigned short * ) 0xFFFFE8 ) ) -#define TGR1B ( *( ( volatile unsigned short * ) 0xFFFFEA ) ) -#define TCR2 ( *( ( volatile unsigned char * ) 0xFFFFF0 ) ) -#define TMDR2 ( *( ( volatile unsigned char * ) 0xFFFFF1 ) ) -#define TIOR2 ( *( ( volatile unsigned char * ) 0xFFFFF2 ) ) -#define TIER2 ( *( ( volatile unsigned char * ) 0xFFFFF4 ) ) -#define TSR2 ( *( ( volatile unsigned char * ) 0xFFFFF5 ) ) -#define TCNT2 ( *( ( volatile unsigned short * ) 0xFFFFF6 ) ) -#define TGR2A ( *( ( volatile unsigned short * ) 0xFFFFF8 ) ) -#define TGR2B ( *( ( volatile unsigned short * ) 0xFFFFFA ) ) -#define TCR3 ( *( ( volatile unsigned char * ) 0xFFFE80 ) ) -#define TMDR3 ( *( ( volatile unsigned char * ) 0xFFFE81 ) ) -#define TIOR3H ( *( ( volatile unsigned char * ) 0xFFFE82 ) ) -#define TIOR3L ( *( ( volatile unsigned char * ) 0xFFFE83 ) ) -#define TIER3 ( *( ( volatile unsigned char * ) 0xFFFE84 ) ) -#define TSR3 ( *( ( volatile unsigned char * ) 0xFFFE85 ) ) -#define TCNT3 ( *( ( volatile unsigned short * ) 0xFFFE86 ) ) -#define TGR3A ( *( ( volatile unsigned short * ) 0xFFFE88 ) ) -#define TGR3B ( *( ( volatile unsigned short * ) 0xFFFE8A ) ) -#define TGR3C ( *( ( volatile unsigned short * ) 0xFFFE8C ) ) -#define TGR3D ( *( ( volatile unsigned short * ) 0xFFFE8E ) ) -#define TCR4 ( *( ( volatile unsigned char * ) 0xFFFE90 ) ) -#define TMDR4 ( *( ( volatile unsigned char * ) 0xFFFE91 ) ) -#define TIOR4 ( *( ( volatile unsigned char * ) 0xFFFE92 ) ) -#define TIER4 ( *( ( volatile unsigned char * ) 0xFFFE94 ) ) -#define TSR4 ( *( ( volatile unsigned char * ) 0xFFFE95 ) ) -#define TCNT4 ( *( ( volatile unsigned short * ) 0xFFFE96 ) ) -#define TGR4A ( *( ( volatile unsigned short * ) 0xFFFE98 ) ) -#define TGR4B ( *( ( volatile unsigned short * ) 0xFFFE9A ) ) -#define TCR5 ( *( ( volatile unsigned char * ) 0xFFFEA0 ) ) -#define TMDR5 ( *( ( volatile unsigned char * ) 0xFFFEA1 ) ) -#define TIOR5 ( *( ( volatile unsigned char * ) 0xFFFEA2 ) ) -#define TIER5 ( *( ( volatile unsigned char * ) 0xFFFEA4 ) ) -#define TSR5 ( *( ( volatile unsigned char * ) 0xFFFEA5 ) ) -#define TCNT5 ( *( ( volatile unsigned short * ) 0xFFFEA6 ) ) -#define TGR5A ( *( ( volatile unsigned short * ) 0xFFFEA8 ) ) -#define TGR5B ( *( ( volatile unsigned short * ) 0xFFFEAA ) ) -#define TSTR ( *( ( volatile unsigned char * ) 0xFFFFC0 ) ) -#define TSYR ( *( ( volatile unsigned char * ) 0xFFFFC1 ) ) - - -#define MSTPCR ( *( ( volatile unsigned short * ) 0xFFFF3C ) ) -#define SCKCR ( *( ( volatile unsigned short * ) 0xFFFF3A ) ) - -/* Serial port. */ - -#define SMR0 ( *( ( volatile unsigned char * ) 0xFFFF78 ) ) -#define BRR0 ( *( ( volatile unsigned char * ) 0xFFFF79 ) ) -#define SCR0 ( *( ( volatile unsigned char * ) 0xFFFF7A ) ) -#define TDR0 ( *( ( volatile unsigned char * ) 0xFFFF7B ) ) -#define SSR0 ( *( ( volatile unsigned char * ) 0xFFFF7C ) ) -#define RDR0 ( *( ( volatile unsigned char * ) 0xFFFF7D ) ) -#define SCMR0 ( *( ( volatile unsigned char * ) 0xFFFF7E ) ) -#define SMR1 ( *( ( volatile unsigned char * ) 0xFFFF80 ) ) -#define BRR1 ( *( ( volatile unsigned char * ) 0xFFFF81 ) ) -#define SCR1 ( *( ( volatile unsigned char * ) 0xFFFF82 ) ) -#define TDR1 ( *( ( volatile unsigned char * ) 0xFFFF83 ) ) -#define SSR1 ( *( ( volatile unsigned char * ) 0xFFFF84 ) ) -#define RDR1 ( *( ( volatile unsigned char * ) 0xFFFF85 ) ) - -#endif diff --git a/Demo/H8S/RTOSDemo/Debug/Debug.hdp b/Demo/H8S/RTOSDemo/Debug/Debug.hdp deleted file mode 100644 index cb97e96b1..000000000 Binary files a/Demo/H8S/RTOSDemo/Debug/Debug.hdp and /dev/null differ diff --git a/Demo/H8S/RTOSDemo/Debug/RTOSDemo.x b/Demo/H8S/RTOSDemo/Debug/RTOSDemo.x deleted file mode 100644 index 83575eff8..000000000 Binary files a/Demo/H8S/RTOSDemo/Debug/RTOSDemo.x and /dev/null differ diff --git a/Demo/H8S/RTOSDemo/Debug/gnuconfig.ini b/Demo/H8S/RTOSDemo/Debug/gnuconfig.ini deleted file mode 100644 index 894ac975f..000000000 --- a/Demo/H8S/RTOSDemo/Debug/gnuconfig.ini +++ /dev/null @@ -1,6 +0,0 @@ -[HEWGNUBARNEYMCGREW] -SELECTEDCPU=H8/S2000 -SELECTEDMODE=Advanced -INT32=N -SELECTEDRENESAS=N -SELECTEDENDIAN=Big endian diff --git a/Demo/H8S/RTOSDemo/FreeRTOSConfig.h b/Demo/H8S/RTOSDemo/FreeRTOSConfig.h deleted file mode 100644 index 32f71fac4..000000000 --- a/Demo/H8S/RTOSDemo/FreeRTOSConfig.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/* IO definitions for the chosen device. */ -#include <2329S.h> - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 22118400 ) -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 200 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 15 * 1024 ) ) -#define configMAX_TASK_NAME_LEN ( 8 ) -#define configUSE_TRACE_FACILITY 0 -#define configUSE_16_BIT_TICKS 1 -#define configIDLE_SHOULD_YIELD 1 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 - - - - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/H8S/RTOSDemo/ParTest/ParTest.c b/Demo/H8S/RTOSDemo/ParTest/ParTest.c deleted file mode 100644 index 8949e9327..000000000 --- a/Demo/H8S/RTOSDemo/ParTest/ParTest.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "portable.h" - -/* Demo application include files. */ -#include "partest.h" - -/*----------------------------------------------------------- - * Simple parallel port IO routines. - * - * This is for the demo application which uses port 2 for LED outputs. - *-----------------------------------------------------------*/ - -/* Value for the LED to be off. */ -#define partstLED_OUTPUTS ( ( unsigned portCHAR ) 0xff ) - -/* P2.0 is not used as an output so there are only 7 LEDs on port 2. */ -#define partstMAX_LEDs ( 7 ) -#define partstALL_OUTPUTS_OFF ( ( unsigned portCHAR ) 0 ) - -/* Maps the LED outputs used by the standard demo application files to -convenient outputs for the EDK2329. Mainly this insures that the LED -used by the Check task is one of the on board LEDs so the demo can be -executed on an EDK without any modification. */ -static inline unsigned portCHAR prvMapLED( unsigned portBASE_TYPE uxLED ); - -/*-----------------------------------------------------------*/ - -void vParTestInitialise( void ) -{ - /* LED's are connected to port 2. P2.1 and P2.2 are built onto the EDK. - P2.3 to P2.7 are soldered onto the expansion port. */ - P2DDR = partstLED_OUTPUTS; - P2DR = partstALL_OUTPUTS_OFF; -} -/*-----------------------------------------------------------*/ - -/* - * Described at the top of the file. - */ -static inline unsigned portCHAR prvMapLED( unsigned portBASE_TYPE uxLED ) -{ - switch( uxLED ) - { - case 0 : return ( unsigned portCHAR ) 2; - case 1 : return ( unsigned portCHAR ) 3; - case 2 : return ( unsigned portCHAR ) 4; - case 3 : return ( unsigned portCHAR ) 5; - case 4 : return ( unsigned portCHAR ) 6; - case 5 : return ( unsigned portCHAR ) 0; - case 6 : return ( unsigned portCHAR ) 1; - default : return 0; - } -} -/*-----------------------------------------------------------*/ - -/* - * Turn an LED on or off. - */ -void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) -{ -unsigned portCHAR ucLED; - - if( uxLED < partstMAX_LEDs ) - { - ucLED = prvMapLED( uxLED ); - - /* Set a bit in the required LED position. LED 0 is bit 1. */ - ucLED = ( unsigned portCHAR ) 1 << ( ucLED + 1 ); - - if( xValue ) - { - portENTER_CRITICAL(); - P2DR |= ucLED; - portEXIT_CRITICAL(); - } - else - { - portENTER_CRITICAL(); - P2DR &= ~ucLED; - portEXIT_CRITICAL(); - } - } -} -/*-----------------------------------------------------------*/ - -void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) -{ -unsigned portCHAR ucLED; - - if( uxLED < partstMAX_LEDs ) - { - ucLED = prvMapLED( uxLED ); - - /* Set a bit in the required LED position. LED 0 is bit 1. */ - ucLED = ( unsigned portCHAR ) 1 << ( ucLED + 1 ); - - portENTER_CRITICAL(); - { - if( P2DR & ucLED ) - { - P2DR &= ~ucLED; - } - else - { - P2DR |= ucLED; - } - } - portEXIT_CRITICAL(); - } -} - - - diff --git a/Demo/H8S/RTOSDemo/RTOSDemo.hwp b/Demo/H8S/RTOSDemo/RTOSDemo.hwp deleted file mode 100644 index 0181e689d..000000000 --- a/Demo/H8S/RTOSDemo/RTOSDemo.hwp +++ /dev/null @@ -1,243 +0,0 @@ -[HIMDBVersion] -2.0 -[DATABASE_VERSION] -"2.7" -[PROJECT_DETAILS] -"RTOSDemo" "C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo" "C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\rtosdemo.hwp" "H8S,H8/300" "KPIT GNUH8 [ELF]" "C Application" "" "" -[INFORMATION] -"No project information available" -[TOOL_CHAIN] -"KPIT GNUH8 [ELF] Toolchain" "v0601" -[CONFIGURATIONS] -"Release" "C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\release" -"Debug" "C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\debug" -[BUILD_PHASES] -"GNU Assembler" 1 -"GNU Compiler" 1 -"GNU Linker" 1 -[DEFINITION_PARSERS] -[TOOL_ENVIRONMENT] -[EXTENSIONS] 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-[CURRENT_SESSION] -"Release session" -[GENERAL_DATA_PROJECT] -"FDT_UserBootAreaFiles" "" -[GENERAL_DATA_CONFIGURATION_Debug] -"PROJECT_FILES_MODIFIED_DATA_TAG" "TRUE" -[SESSIONS_Debug] -"Release session" -"Simulator" -[GENERAL_DATA_CONFIGURATION_Release] -"PROJECT_FILES_MODIFIED_DATA_TAG" "FALSE" -[SESSIONS_Release] -"Release session" -"Simulator" -[GENERAL_DATA_CONFIGURATION_SESSION_Debug_Simulator] -[GENERAL_DATA_SESSION_Release session] -[GENERAL_DATA_CONFIGURATION_SESSION_Release_Release session] -[GENERAL_DATA_CONFIGURATION_SESSION_Release_Simulator] -[GENERAL_DATA_SESSION_Simulator] -[GENERAL_DATA_CONFIGURATION_SESSION_Debug_Release session] -[END] diff --git a/Demo/H8S/RTOSDemo/Release session.hsf b/Demo/H8S/RTOSDemo/Release session.hsf deleted file mode 100644 index 496933dae..000000000 --- a/Demo/H8S/RTOSDemo/Release session.hsf +++ /dev/null @@ -1,247 +0,0 @@ -[HIMDBVersion] -2.0 -[DATABASE_VERSION] -"2.0" -[SESSION_DETAILS] -"" -[INFORMATION] -"" -[GENERAL_DATA] -"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth1" "200" -"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewAInstanceKey0" "{WK_00000001_MEMORY}" -"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_BREAK_BREAK_SEQUENCE_COUNT" "0" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MEMORY_MODE" "0" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONTROL_REGS_CREG1" "0x00FFFF32,1,0x00000000" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_RESOURCE_MEMORY_RESOURCE_COUNT" "1" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_BREAK_BREAK_REGISTER_COUNT" "0" -"{2BA6A3EE-6488-11D5-80D4-00C04F68EAD7}LabelCtrlViews" "0" -"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd2ScrollVert" "0" -"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_COLOR" "0,0,0,0" -"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ScrollHorz" "0" -"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth2" "200" -"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWndInstanceKey0" "{WK_00000001_WATCH}" -"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWnd0ECX_REGISTER_DISPLAYED" "1,1,1,1,1,1,1,1,1,1,1" -"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_PRG_WIDTH" "24" -"{313F4FC1-6566-11D5-8BBE-0004E2013C71}TclTkCtrlLogFileName" "" -"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_0" "0000000000000000" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONFIG_DIVISOR" "DISABLE" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONTROL_REGS_CREG2" "0x00FFFD95,1,0x00000000" -"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlViews" "0" -"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd2ColWidth0" "250" -"{633553C0-6FE9-11D5-B7CE-00E029352378}ProfileCtrlChartMultiOpen" "0" -"{7FA2E460-7EC0-11D5-8EB6-00004CC34E9D}SimIOWndInstanceKey0" "{WK_00000001_SIMIO}RTOSDemoSimulator" -"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_BREAK_BREAK_ACCESS_COUNT" "0" -"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_1" "0000000011111111" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_SYSTEM_CALL_SYSTEM_CALL_FLAG" "OFF" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_BREAK_BREAK_DATA_COUNT" "0" -"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd1ScrollHorz" "0" -"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd2ColWidth1" "250" -"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_VIEW" "0,0,0,0,0,0" -"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE" "00000000,00000000,0,0" -"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ECX_WATCH" "" -"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWnd0ColWidth0" "100" -"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_BREAK_BREAK_REGISTER_COUNT" "0" -"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_MAP0" "0x00000000,0x0005FFFF,16, 2,ROM" -"{287A8023-99B5-49E1-A54E-4DDCA43D7959}MapCtrlViews" "0" -"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_2" "0000000000000000" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_EXEC_STEP_RATE" "40000" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_EXEC_MULT_VAL" "00000000" -"{EEDC9300-6FBE-11D5-8613-00A024591A38}LocalsCtrlViews" "0" -"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ScrollVert" "0" -"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth0" "200" -"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWnd0ColWidth1" "1600" -"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_MAP1" "0x00FF7C00,0x00FFFBFF,16, 2,RAM" -"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_3" "0000000033333333" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONTROL_REGS_SYSCR_ADR" "0x00FFFF39" -"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth1" "200" -"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ScrollVert" "0" -"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndViewB0ScrollHorz" "0" -"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_MEMORY_MODE" "0" -"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_4" "0000000044444444" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_EXEC_EXEC_MODE" "STOP" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_BUS_WIDTH" "24" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_ADDRESS_MAP" "24" -"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusCtrlViews" "1" -"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_COMB_ADDRESS" ",,,," -"{48FF5DA0-6FFA-11D5-B7CE-00E029352378}CoverageFileName" "0" -"{85AC95E0-0CE6-11D6-8EB6-00004CC34E9D}TriggerCtrlViews" "0" -"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_MAP2" "0x00FFFE50,0x00FFFF07,16, 2,I/O" -"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth2" "200" -"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ScrollHorz" "0" -"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewBInstanceKey0" "{WK_00000001_MEMORY}ViewB" -"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlViews0" "16743424" -"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_BREAK_BREAK_DATA_COUNT" "0" -"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlViews" "0" -"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_5" "0000000055555555" -"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_10" "000000000000007F" -"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd1ScrollVert" "0" -"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_COMB_PALETTE" ",,,," -"{7FA2E460-7EC0-11D5-8EB6-00004CC34E9D}SimIOCtrlViews" "1" -"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_MAP3" "0x00FFFF28,0x00FFFFFF,16, 2,I/O" -"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ScrollHorz" "0" -"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0Exp0" "0" -"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlOneLineBytesCount0" "16" -"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndViewB0ColWidth0" "100" -"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_MEMORY_MAP_COUNT" "4" -"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_6" "0000000000FF820C" -"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_11" "0000000000000000" -"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd0ScrollHorz" "0" -"{5F75FDA0-6FF0-11D5-B7CE-00E029352378}PACtrlViews" "0" -"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ColWidth0" "200" -"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ECX_WATCH" "" -"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndViewB0ColWidth1" "1600" -"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_SESSION_IS_SAVED" "YES" -"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_BUS_WIDTH" "24" -"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_7" "0000000000FF8200" -"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_12" "00000000FFFFFF00" -"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOCtrlViews" "1" -"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_BUFFER" "00000000,00000000,0,0" -"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ColWidth1" "200" -"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlProperty0" "5" -"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndViewB0ScrollVert" "0" -"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndViewB0ECX_REGISTER_DISPLAYED" "1,1,1,1,1,1,1,1,1,1,1" -"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndViewB0ECX_REGISTER_COUNT" "11" -"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_RESOURCE_MEMORY_RESOURCE_COUNT" "4" -"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_8" "0000000000004E9C" -"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_13" "0000000000000000" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONFIG_FETCH_MODE" "32" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_RESOURCE_MEMRES0" "0x00000000,0x0005FFFF,14" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_TRACE_TRACE_ACQUISITION" "0,1024,0,0" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_SESSION_IS_SAVED" "YES" -"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd0ColWidth0" "250" -"{D595F9C0-EF22-11D5-B7DB-0000E10B3DA9}EventCtrlViews" "0" -"{B266D880-6FA1-11D5-8613-00A024591A38}WatchCtrlViews" "0" -"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ColWidth2" "200" -"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ScrollVert" "0" -"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_TRACE_TRACE_ACQUISITION" "0,1024,0,0" -"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_RESOURCE_MEMRES0" "0x00000000,0x00005FFF,14" -"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_SYSTEM_CALL_SYSTEM_CALL_FLAG" "OFF" -"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_9" "0000000000000080" -"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_14" "0000000000000000" -"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd0ColWidth1" "250" -"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE_COMB_ADDRESS" ",,,," -"{5F75FDA0-6FF0-11D5-B7CE-00E029352378}PACtrlPAState" "0" -"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ScrollVert" "0" -"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth0" "200" -"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlViews30" "16776191" -"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_RESOURCE_MEMRES1" "0x00FF7C00,0x00FFFBFF,15" -"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_CONTROL_REGS_CREG_CNT" "0" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONFIG_ENDIAN" "BIG" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONFIG_MULTIPLIER" "DISABLE" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_BREAK_PC_BREAK_COUNT" "0" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_BREAK_BREAK_CYCLE_COUNT" "0" -"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd0ScrollVert" "0" -"{30F726A1-F13D-4E21-9A4F-FD7FF70EDFDA}TraceCtrlViews" "0" -"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ScrollHorz" "0" -"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth1" "200" -"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlViews20" "16743424" -"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWnd0ScrollHorz" "0" -"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWnd0ECX_REGISTER_COUNT" "11" -"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_BREAK_BREAK_CYCLE_COUNT" "0" -"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBatchFileName" "" -"{313F4FC0-6566-11D5-8BBE-0004E2013C71}DisassemblyCtrlViews" "0" -"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}WaveformCtrlViews" "0" -"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_RESOURCE_MEMRES2" "0x00FFFE50,0x00FFFF07,7" -"{7943C44E-7D44-422A-9140-4CF55C88F7D3}DifferenceCtrlViews" "0" -"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ECX_WATCH" "" -"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth2" "200" -"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_EXEC_STEP_RATE" "40000" -"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterCtrlViews" "0" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONFIG_ROUND" "RM_NEAR" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP0" "0x00000000,0x0005FFFF, 8, 3,ROM" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONTROL_REGS_CREG_CNT" "3" -"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd1ColWidth0" "250" -"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd2ScrollHorz" "0" -"{633553C0-6FE9-11D5-B7CE-00E029352378}ProfileCtrlEnable" "0" -"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_RESOURCE_MEMRES3" "0x00FFFF28,0x00FFFFFF,7" -"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ColWidth0" "200" -"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlDataCount0" "4" -"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndViewBInstanceKey0" "{WK_00000001_REGISTER}ViewB" -"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_BREAK_PC_BREAK_COUNT" "0" -"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_SYSTEM_CALL_SYSTEM_CALL_ADDRESS" "0x00000000" -"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_CONFIG_ENDIAN" "BIG" -"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_COUNT" "11" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP1" "0x00FF7C00,0x00FFFBFF, 8, 3,RAM" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_BREAK_BREAK_SEQUENCE_COUNT" "0" -"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd1ColWidth1" "250" -"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE_COMB_BUFFER" ",,,," -"{48FF5DA0-6FFA-11D5-B7CE-00E029352378}CoverageCtrlViews" "0" -"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ColWidth1" "100" -"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH" "pxCreatedTask," -"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_EXEC_EXEC_MODE" "STOP" -"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlLogFileName" "" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_PRG_WIDTH" "24" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MEMORY_MAP_COUNT" "4" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP2" "0x00FFFE50,0x00FFFF07, 8, 2,RAM" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_BREAK_BREAK_ACCESS_COUNT" "0" -"{633553C0-6FE9-11D5-B7CE-00E029352378}ProfileCtrlViews" "0" -"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ColWidth2" "100" -"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ScrollVert" "0" -"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth0" "200" -"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndInstanceKey0" "{WK_00000001_REGISTER}" -"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWnd0ScrollVert" "0" -"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_CONFIG_ROUND" "RM_NEAR" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_SYSTEM_CALL_SYSTEM_CALL_ADDRESS" "0x00000000" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP3" "0x00FFFF28,0x00FFFFFF, 8, 2,RAM" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONTROL_REGS_CREG0" "0x00FFFF39,2,0x00000101" -"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ImageCtrlViews" "0" -"{48FF5DA0-6FFA-11D5-B7CE-00E029352378}CoverageCtrlViewsFromDiffFile" "0" -"{EEDC9301-6FBE-11D5-8613-00A024591A38}StackTraceCtrlViews" "0" -"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ColWidth3" "100" -"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ScrollHorz" "0" -[LANGUAGE] -"English" -[CONFIG_INFO_VD1] -1 -[CONFIG_INFO_VD2] -0 -[CONFIG_INFO_VD3] -0 -[CONFIG_INFO_VD4] -0 -[WINDOW_POSITION_STATE_DATA_VD1] -"{WK_TB00000009_VERSIONCONTROL}" "TOOLBAR 0" 59419 0 4 "0.00" 0 0 0 0 0 17 0 "" "0.0" -"{WK_TB00000004_TEMPLATES}" "TOOLBAR 0" 59419 0 8 "0.00" 0 0 0 0 0 18 0 "" "0.0" -"TCL Toolkit" "WINDOW" 59422 1 0 "-1.000000" -1 -1000 -1000 -1 -1 17 0 "" "-1" -"{WK_TB00000002_EDITOR}" "TOOLBAR 0" 59419 0 2 "0.00" 0 0 0 0 0 18 0 "" "0.0" -"{WK_TB00000012_MAP}" "TOOLBAR 0" 59419 0 3 "0.00" 0 0 0 0 0 18 0 "" "0.0" -"{WK_TB00000017_FDT}" "TOOLBAR 0" 59419 0 1 "0.00" 0 0 0 0 0 18 0 "" "0.0" -"{WK_00000001_MAP}RTOSDemoRelease session" "WINDOW" 59421 -1 -1 "-1.000000" -1 -1000 -1000 -1 -1 18 0 "" "-1" -"{WK_TB00000003_BOOKMARKS}" "TOOLBAR 0" 59419 1 0 "0.00" 0 0 0 0 0 18 0 "" "0.0" -"{WK_TB00000018_DEFAULTWINDOW}" "TOOLBAR 0" 59419 1 1 "0.00" 0 0 0 0 0 17 0 "" "0.0" -"{WK_TB00000008_DEBUGRUN}" "TOOLBAR 0" 59419 0 5 "0.00" 0 0 0 0 0 17 0 "" "0.0" -"{WK_TB00000005_SEARCH}" "TOOLBAR 0" 59419 0 7 "0.00" 0 0 0 0 0 18 0 "" "0.0" -"{WK_00000001_OUTPUT}" "WINDOW" 59422 0 0 "1.00" 180 0 0 350 200 18 0 "" "0.0" -"{WK_00000002_WORKSPACE}" "WINDOW" 59420 0 0 "1.00" 280 0 0 350 200 18 0 "" "0.0" -"{WK_TB00000001_STANDARD}" "TOOLBAR 0" 59419 0 0 "0.00" 0 0 0 0 0 18 0 "" "0.0" -"{WK_TB00000007_DEBUG}" "TOOLBAR 0" 59419 0 6 "0.00" 0 0 0 0 0 17 0 "" "0.0" -[WINDOW_POSITION_STATE_DATA_VD2] -[WINDOW_POSITION_STATE_DATA_VD3] -[WINDOW_POSITION_STATE_DATA_VD4] -[WINDOW_Z_ORDER] -"C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\partest\partest.c" -"C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\serial\serial.c" -"c:\e\Dev\FreeRTOS\Source\queue.c" -"C:\E\Dev\FreeRTOS\Source\portable\GCC\H8S2329\portmacro.h" -"c:\e\Dev\FreeRTOS\Source\portable\GCC\H8S2329\port.c" -"C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\main.c" -"C:\E\Dev\FreeRTOS\Source\include\portable.h" -"c:\e\Dev\FreeRTOS\Demo\Common\Minimal\BlockQ.c" -[TARGET_NAME] -"" -[DEBUGGER_OPTIONS] -"" -[DOWNLOAD_MODULES] -[CONNECT_ON_GO] -"TRUE" -[DOWNLOAD_MODULES_AFTER_BUILD] -"TRUE" -[REMOVE_BREAKPOINTS_ON_DOWNLOAD] -"FALSE" -[COMMAND_FILES] -[DEFAULT_DEBUG_FORMAT] -"" -[FLASH_DETAILS] -"2212.000000" 1 -127 "B" 0 "COM1" 115200 1 "H8S/2329BF" 1 0 0 0 1 0 0 "D:\DevTools\Hitachi\FDT2.2\Kernels\ProtB\2329\hitachi\1_1_00\" "" "" "" "" -[BREAKPOINTS] -[END] diff --git a/Demo/H8S/RTOSDemo/Release/gnuconfig.ini b/Demo/H8S/RTOSDemo/Release/gnuconfig.ini deleted file mode 100644 index 894ac975f..000000000 --- a/Demo/H8S/RTOSDemo/Release/gnuconfig.ini +++ /dev/null @@ -1,6 +0,0 @@ -[HEWGNUBARNEYMCGREW] -SELECTEDCPU=H8/S2000 -SELECTEDMODE=Advanced -INT32=N -SELECTEDRENESAS=N -SELECTEDENDIAN=Big endian diff --git a/Demo/H8S/RTOSDemo/Simulator sessions.hsf b/Demo/H8S/RTOSDemo/Simulator sessions.hsf deleted file mode 100644 index 96edb92f7..000000000 --- a/Demo/H8S/RTOSDemo/Simulator sessions.hsf +++ /dev/null @@ -1,245 +0,0 @@ -[HIMDBVersion] -2.0 -[DATABASE_VERSION] -"2.0" -[SESSION_DETAILS] -"" -[INFORMATION] -"" -[GENERAL_DATA] -"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth1" "200" -"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewAInstanceKey0" "{WK_00000001_MEMORY}RTOSDemoSimulator" -"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd2ScrollVert" "0" -"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_COLOR" "0,0,0,0" -"{2BA6A3EE-6488-11D5-80D4-00C04F68EAD7}LabelCtrlViews" "0" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_BREAK_BREAK_REGISTER_COUNT" "0" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_RESOURCE_MEMORY_RESOURCE_COUNT" "1" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONTROL_REGS_CREG1" "0x00FFFF32,1,0x00000000" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP4" "0x00E00000,0x00EFFFFF, 8, 3,EXT" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MEMORY_MODE" "0" -"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_BREAK_BREAK_SEQUENCE_COUNT" "0" -"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ScrollHorz" "0" -"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth2" "200" -"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWndInstanceKey0" "{WK_00000001_WATCH}RTOSDemoSimulator" -"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWnd0ECX_REGISTER_DISPLAYED" "1,1,1,1,1,1,1,1,1,1,1" -"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd2ColWidth0" "250" -"{633553C0-6FE9-11D5-B7CE-00E029352378}ProfileCtrlChartMultiOpen" "0" -"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlViews" "0" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONTROL_REGS_CREG2" "0x00FFFD95,1,0x00000000" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP5" "0x00F00000,0x00FDBFFF, 8, 3,EXT" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONFIG_DIVISOR" "DISABLE" -"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_0" "0000000000000000" -"{313F4FC1-6566-11D5-8BBE-0004E2013C71}TclTkCtrlLogFileName" "" -"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_PRG_WIDTH" "24" -"{7FA2E460-7EC0-11D5-8EB6-00004CC34E9D}SimIOWndInstanceKey0" "{WK_00000001_SIMIO}RTOSDemoSimulator" -"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd2ColWidth1" "250" -"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd1ScrollHorz" "0" -"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE" "00000000,00000000,0,0" -"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_VIEW" "0,0,0,0,0,0" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_BREAK_BREAK_DATA_COUNT" "0" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP6" "0x00FDC000,0x00FEBFFF,16, 3,RAM" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_SYSTEM_CALL_SYSTEM_CALL_FLAG" "OFF" -"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_1" "0000000011111111" -"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_BREAK_BREAK_ACCESS_COUNT" "0" -"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ECX_WATCH" "" -"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWnd0ColWidth0" "100" -"{EEDC9300-6FBE-11D5-8613-00A024591A38}LocalsCtrlViews" "0" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP7" "0x00FEC000,0x00FFBFFF,16, 1,RAM" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_EXEC_MULT_VAL" "00000000" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_EXEC_STEP_RATE" "40000" -"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_2" "0000000000000001" -"{287A8023-99B5-49E1-A54E-4DDCA43D7959}MapCtrlViews" "0" -"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_MAP0" "0x00000000,0x0005FFFF,16, 2,ROM" -"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_BREAK_BREAK_REGISTER_COUNT" "0" -"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ScrollVert" "0" -"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth0" "200" -"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWnd0ColWidth1" "1600" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONTROL_REGS_SYSCR_ADR" "0x00FFFF39" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP8" "0x00FFC000,0x00FFDFFF, 8, 3,EXT" -"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_3" "0000000033333333" -"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_MAP1" "0x00FF7C00,0x00FFFBFF,16, 2,RAM" -"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth1" "200" -"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ScrollVert" "0" -"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndViewB0ScrollHorz" "0" -"{85AC95E0-0CE6-11D6-8EB6-00004CC34E9D}TriggerCtrlViews" "0" -"{48FF5DA0-6FFA-11D5-B7CE-00E029352378}CoverageFileName" "0" -"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_COMB_ADDRESS" ",,,," -"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusCtrlViews" "1" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_ADDRESS_MAP" "24" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP9" "0x00FFE000,0x00FFE9FF, 8, 3,EXT" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_BUS_WIDTH" "24" -"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_EXEC_EXEC_MODE" "STOP" -"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_4" "0000000044444444" -"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_MEMORY_MODE" "0" -"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_MAP2" "0x00FFFE50,0x00FFFF07,16, 2,I/O" -"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth2" "200" -"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ScrollHorz" "0" -"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewBInstanceKey0" "{WK_00000001_MEMORY}RTOSDemoSimulatorViewB" -"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlViews0" "16756480" -"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd1ScrollVert" "0" -"{7FA2E460-7EC0-11D5-8EB6-00004CC34E9D}SimIOCtrlViews" "1" -"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_COMB_PALETTE" ",,,," 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1 -127 "B" 0 "COM1" 115200 1 "H8S/2329BF" 1 0 0 0 1 0 0 "D:\DevTools\Hitachi\FDT2.2\Kernels\ProtB\2329\hitachi\1_1_00\" "" "" "" "" -[BREAKPOINTS] -[END] diff --git a/Demo/H8S/RTOSDemo/main.c b/Demo/H8S/RTOSDemo/main.c deleted file mode 100644 index aad870af3..000000000 --- a/Demo/H8S/RTOSDemo/main.c +++ /dev/null @@ -1,372 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * Creates all the demo application tasks, then starts the scheduler. The WEB - * documentation provides more details of the demo application tasks. - * - * Main.c also creates a task called "Check". This only executes every three - * seconds but has the highest priority so is guaranteed to get processor time. - * Its main function is to check that all the other tasks are still operational. - * Each task (other than the "flash" tasks) maintains a unique count that is - * incremented each time the task successfully completes its function. Should - * any error occur within such a task the count is permanently halted. The - * check task inspects the count of each task to ensure it has changed since - * the last time the check task executed. If all the count variables have - * changed all the tasks are still executing error free, and the check task - * toggles the onboard LED. Should any task contain an error at any time - * the LED toggle rate will change from 3 seconds to 500ms. - * - * To check the operation of the memory allocator the check task also - * dynamically creates a task before delaying, and deletes it again when it - * wakes. If memory cannot be allocated for the new task the call to xTaskCreate - * will fail and an error is signalled. The dynamically created task itself - * allocates and frees memory just to give the allocator a bit more exercise. - * - */ - -/* Standard includes. */ -#include -#include - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Demo application file headers. */ -#include "flash.h" -#include "integer.h" -#include "PollQ.h" -#include "comtest2.h" -#include "semtest.h" -#include "flop.h" -#include "dynamic.h" -#include "BlockQ.h" -#include "serial.h" -#include "partest.h" - -/* Priority definitions for most of the tasks in the demo application. Some -tasks just use the idle priority. */ -#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) - -/* Baud rate used by the serial port tasks (ComTest tasks). */ -#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 115200 ) - -/* LED used by the serial port tasks. This is toggled on each character Tx, -and mainCOM_TEST_LED + 1 is toggles on each character Rx. */ -#define mainCOM_TEST_LED ( 3 ) - -/* LED that is toggled by the check task. The check task periodically checks -that all the other tasks are operating without error. If no errors are found -the LED is toggled with mainCHECK_PERIOD frequency. If an error is found -the the toggle rate increases to mainERROR_CHECK_PERIOD. */ -#define mainCHECK_TASK_LED ( 5 ) -#define mainCHECK_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS ) -#define mainERROR_CHECK_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS ) - -/* Constants used by the vMemCheckTask() task. */ -#define mainCOUNT_INITIAL_VALUE ( ( unsigned portLONG ) 0 ) -#define mainNO_TASK ( 0 ) - -/* The size of the memory blocks allocated by the vMemCheckTask() task. */ -#define mainMEM_CHECK_SIZE_1 ( ( size_t ) 51 ) -#define mainMEM_CHECK_SIZE_2 ( ( size_t ) 52 ) -#define mainMEM_CHECK_SIZE_3 ( ( size_t ) 151 ) - -/* - * The 'Check' task. - */ -static void vErrorChecks( void *pvParameters ); - -/* - * Checks the unique counts of other tasks to ensure they are still operational. - */ -static portLONG prvCheckOtherTasksAreStillRunning( unsigned portLONG ulMemCheckTaskCount ); - -/* - * Dynamically created and deleted during each cycle of the vErrorChecks() - * task. This is done to check the operation of the memory allocator. - * See the top of vErrorChecks for more details. - */ -static void vMemCheckTask( void *pvParameters ); - -/*-----------------------------------------------------------*/ - -/* - * Start all the tasks then start the scheduler. - */ -int main( void ) -{ - /* Setup the LED's for output. */ - vParTestInitialise(); - - /* Start the various standard demo application tasks. */ - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); - vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartMathTasks( tskIDLE_PRIORITY ); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartDynamicPriorityTasks(); - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - - /* Start the 'Check' task. */ - xTaskCreate( vErrorChecks, ( signed portCHAR * )"Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - - /* In this port, to use preemptive scheduler define configUSE_PREEMPTION - as 1 in portmacro.h. To use the cooperative scheduler define - configUSE_PREEMPTION as 0. */ - vTaskStartScheduler(); - - /* Should never get here! */ - return 0; -} -/*-----------------------------------------------------------*/ - -/* - * Cycle for ever, delaying then checking all the other tasks are still - * operating without error. If an error is detected then the delay period - * is decreased from mainCHECK_PERIOD to mainERROR_CHECK_PERIOD so - * the on board LED flash rate will increase. - * - * In addition to the standard tests the memory allocator is tested through - * the dynamic creation and deletion of a task each cycle. Each time the - * task is created memory must be allocated for its stack. When the task is - * deleted this memory is returned to the heap. If the task cannot be created - * then it is likely that the memory allocation failed. In addition the - * dynamically created task allocates and frees memory while it runs. - */ -static void vErrorChecks( void *pvParameters ) -{ -portTickType xDelayPeriod = mainCHECK_PERIOD; -volatile unsigned portLONG ulMemCheckTaskRunningCount; -xTaskHandle xCreatedTask; -portTickType xLastWakeTime; - - /* Initialise xLastWakeTime to ensure the first call to vTaskDelayUntil() - functions correctly. */ - xLastWakeTime = xTaskGetTickCount(); - - for( ;; ) - { - /* Set ulMemCheckTaskRunningCount to a known value so we can check - later that it has changed. */ - ulMemCheckTaskRunningCount = mainCOUNT_INITIAL_VALUE; - - /* Dynamically create a task - passing ulMemCheckTaskRunningCount as a - parameter. */ - xCreatedTask = mainNO_TASK; - if( xTaskCreate( vMemCheckTask, ( signed portCHAR * ) "MEM_CHECK", configMINIMAL_STACK_SIZE, ( void * ) &ulMemCheckTaskRunningCount, tskIDLE_PRIORITY, &xCreatedTask ) != pdPASS ) - { - /* Could not create the task - we have probably run out of heap. */ - xDelayPeriod = mainERROR_CHECK_PERIOD; - } - - - /* Delay until it is time to execute again. The delay period is - shorter following an error. */ - vTaskDelayUntil( &xLastWakeTime, xDelayPeriod ); - - - /* Delete the dynamically created task. */ - if( xCreatedTask != mainNO_TASK ) - { - vTaskDelete( xCreatedTask ); - } - - /* Check all the standard demo application tasks are executing without - error. ulMemCheckTaskRunningCount is checked to ensure it was - modified by the task just deleted. */ - if( prvCheckOtherTasksAreStillRunning( ulMemCheckTaskRunningCount ) != pdPASS ) - { - /* An error has been detected in one of the tasks - flash faster. */ - xDelayPeriod = mainERROR_CHECK_PERIOD; - } - - vParTestToggleLED( mainCHECK_TASK_LED ); - } -} -/*-----------------------------------------------------------*/ - -/* - * Check each set of tasks in turn to see if they have experienced any - * error conditions. - */ -static portLONG prvCheckOtherTasksAreStillRunning( unsigned portLONG ulMemCheckTaskCount ) -{ -portLONG lNoErrorsDiscovered = ( portLONG ) pdTRUE; - - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - lNoErrorsDiscovered = pdFALSE; - } - - if( xAreComTestTasksStillRunning() != pdTRUE ) - { - lNoErrorsDiscovered = pdFALSE; - } - - if( xArePollingQueuesStillRunning() != pdTRUE ) - { - lNoErrorsDiscovered = pdFALSE; - } - - if( xAreMathsTaskStillRunning() != pdTRUE ) - { - lNoErrorsDiscovered = pdFALSE; - } - - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - lNoErrorsDiscovered = pdFALSE; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - lNoErrorsDiscovered = pdFALSE; - } - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - lNoErrorsDiscovered = pdFALSE; - } - - if( ulMemCheckTaskCount == mainCOUNT_INITIAL_VALUE ) - { - /* The vMemCheckTask task did not increment the counter - it must - have failed. */ - lNoErrorsDiscovered = pdFALSE; - } - - return lNoErrorsDiscovered; -} -/*-----------------------------------------------------------*/ - -static void vMemCheckTask( void *pvParameters ) -{ -unsigned portLONG *pulMemCheckTaskRunningCounter; -void *pvMem1, *pvMem2, *pvMem3; -static portLONG lErrorOccurred = pdFALSE; - - /* This task is dynamically created then deleted during each cycle of the - vErrorChecks task to check the operation of the memory allocator. Each time - the task is created memory is allocated for the stack and TCB. Each time - the task is deleted this memory is returned to the heap. This task itself - exercises the allocator by allocating and freeing blocks. - - The task executes at the idle priority so does not require a delay. - - pulMemCheckTaskRunningCounter is incremented each cycle to indicate to the - vErrorChecks() task that this task is still executing without error. */ - - pulMemCheckTaskRunningCounter = ( unsigned portLONG * ) pvParameters; - - for( ;; ) - { - if( lErrorOccurred == pdFALSE ) - { - /* We have never seen an error so increment the counter. */ - ( *pulMemCheckTaskRunningCounter )++; - } - else - { - /* Reset the count so an error is detected by the - prvCheckOtherTasksAreStillRunning() function. */ - *pulMemCheckTaskRunningCounter = mainCOUNT_INITIAL_VALUE; - } - - /* Allocate some memory - just to give the allocator some extra - exercise. This has to be in a critical section to ensure the - task does not get deleted while it has memory allocated. */ - vTaskSuspendAll(); - { - pvMem1 = pvPortMalloc( mainMEM_CHECK_SIZE_1 ); - if( pvMem1 == NULL ) - { - lErrorOccurred = pdTRUE; - } - else - { - memset( pvMem1, 0xaa, mainMEM_CHECK_SIZE_1 ); - vPortFree( pvMem1 ); - } - } - xTaskResumeAll(); - - /* Again - with a different size block. */ - vTaskSuspendAll(); - { - pvMem2 = pvPortMalloc( mainMEM_CHECK_SIZE_2 ); - if( pvMem2 == NULL ) - { - lErrorOccurred = pdTRUE; - } - else - { - memset( pvMem2, 0xaa, mainMEM_CHECK_SIZE_2 ); - vPortFree( pvMem2 ); - } - } - xTaskResumeAll(); - - /* Again - with a different size block. */ - vTaskSuspendAll(); - { - pvMem3 = pvPortMalloc( mainMEM_CHECK_SIZE_3 ); - if( pvMem3 == NULL ) - { - lErrorOccurred = pdTRUE; - } - else - { - memset( pvMem3, 0xaa, mainMEM_CHECK_SIZE_3 ); - vPortFree( pvMem3 ); - } - } - xTaskResumeAll(); - } -} -/*-----------------------------------------------------------*/ - -/* - * Called by the startup code. Initial processor setup can be placed in this - * function. - */ -void hw_initialise (void) -{ -} - diff --git a/Demo/H8S/RTOSDemo/serial/serial.c b/Demo/H8S/RTOSDemo/serial/serial.c deleted file mode 100644 index 0d4e14305..000000000 --- a/Demo/H8S/RTOSDemo/serial/serial.c +++ /dev/null @@ -1,260 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER for port 1. - -Note that this driver is written to test the RTOS port and is not intended -to represent an optimised solution. In particular no use is made of the DMA -peripheral. */ - -/* Standard include files. */ -#include - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "queue.h" -#include "task.h" - -/* Demo application include files. */ -#include "serial.h" - -/* The queues used to communicate between the task code and the interrupt -service routines. */ -static xQueueHandle xRxedChars; -static xQueueHandle xCharsForTx; - -/* Hardware specific constants. */ -#define serTX_INTERRUPT ( ( unsigned portCHAR ) 0x80 ) -#define serRX_INTERRUPT ( ( unsigned portCHAR ) 0x40 ) -#define serTX_ENABLE ( ( unsigned portCHAR ) 0x20 ) -#define serRX_ENABLE ( ( unsigned portCHAR ) 0x10 ) - -/* Macros to turn on and off the serial port THRE interrupt while leaving the -other register bits in their correct state. The Rx interrupt is always -enabled. */ -#define serTX_INTERRUPT_ON() SCR1 = serTX_INTERRUPT | serRX_INTERRUPT | serTX_ENABLE | serRX_ENABLE; -#define serTX_INTERRUPT_OFF() SCR1 = serRX_INTERRUPT | serTX_ENABLE | serRX_ENABLE; - -/* Bit used to switch on the channel 1 serial port in the module stop -register. */ -#define serMSTP6 ( ( unsigned portSHORT ) 0x0040 ) - -/* Interrupt service routines. Note that the Rx and Tx service routines can -cause a context switch and are therefore defined with the saveall attribute in -addition to the interrupt_handler attribute. See the FreeRTOS.org WEB site -documentation for a full explanation.*/ -void vCOM_1_Rx_ISR( void ) __attribute__ ( ( saveall, interrupt_handler ) ); -void vCOM_1_Tx_ISR( void ) __attribute__ ( ( saveall, interrupt_handler ) ); -void vCOM_1_Error_ISR( void ) __attribute__ ( ( interrupt_handler ) ); - -/*-----------------------------------------------------------*/ - -/* - * Initialise port 1 for interrupt driven communications. - */ -xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) -{ - /* Create the queues used to communicate between the tasks and the - interrupt service routines. */ - xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); - xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); - - /* No parity, 8 data bits and 1 stop bit is the default so does not require - configuration - setup the remains of the hardware. */ - portENTER_CRITICAL(); - { - /* Turn channel 1 on. */ - MSTPCR &= ~serMSTP6; - - /* Enable the channels and the Rx interrupt. The Tx interrupt is only - enabled when data is being transmitted. */ - SCR1 = serRX_INTERRUPT | serTX_ENABLE | serRX_ENABLE; - - /* Bit rate settings for 22.1184MHz clock only!. */ - switch( ulWantedBaud ) - { - case 4800 : BRR1 = 143; - break; - case 9600 : BRR1 = 71; - break; - case 19200 : BRR1 = 35; - break; - case 38400 : BRR1 = 17; - break; - case 57600 : BRR1 = 11; - break; - case 115200 : BRR1 = 5; - break; - default : BRR1 = 5; - break; - } - } - portEXIT_CRITICAL(); - - /* Unlike some ports, this driver code does not allow for more than one - com port. We therefore don't return a pointer to a port structure and can - instead just return NULL. */ - return NULL; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) -{ - /* Get the next character from the buffer queue. Return false if no characters - are available, or arrive before xBlockTime expires. */ - if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) - { - return pdTRUE; - } - else - { - return pdFALSE; - } -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) -{ -signed portBASE_TYPE xReturn = pdPASS; - - /* Return false if after the block time there is no room on the Tx queue. */ - portENTER_CRITICAL(); - { - /* Send a character to the queue of characters waiting transmission. - The queue is serviced by the Tx ISR. */ - if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) - { - /* Could not post onto the queue. */ - xReturn = pdFAIL; - } - else - { - /* The message was posted onto the queue so we turn on the Tx - interrupt to allow the Tx ISR to remove the character from the - queue. */ - serTX_INTERRUPT_ON(); - } - } - portEXIT_CRITICAL(); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -void vSerialClose( xComPortHandle xPort ) -{ - /* Not supported. */ - ( void ) xPort; -} -/*-----------------------------------------------------------*/ - -void vCOM_1_Rx_ISR( void ) -{ - /* This can cause a context switch so this macro must be the first line - in the function. */ - portENTER_SWITCHING_ISR(); - - /* As this is a switching ISR the local variables must be declared as - static. */ - static portCHAR cRxByte; - static portBASE_TYPE xTaskWokenByPost; - - /* Get the character. */ - cRxByte = RDR1; - - /* Post the character onto the queue of received characters - noting - whether or not this wakes a task. */ - xTaskWokenByPost = xQueueSendFromISR( xRxedChars, &cRxByte, pdFALSE ); - - /* Clear the interrupt. */ - SSR1 &= ~serRX_INTERRUPT; - - /* This must be the last line in the function. We pass cTaskWokenByPost so - a context switch will occur if the received character woke a task that has - a priority higher than the task we interrupted. */ - portEXIT_SWITCHING_ISR( xTaskWokenByPost ); -} -/*-----------------------------------------------------------*/ - -void vCOM_1_Tx_ISR( void ) -{ - /* This can cause a context switch so this macro must be the first line - in the function. */ - portENTER_SWITCHING_ISR(); - - /* As this is a switching ISR the local variables must be declared as - static. */ - static portCHAR cTxByte; - static signed portBASE_TYPE xTaskWokenByTx; - - /* This variable is static so must be explicitly reinitialised each - time the function executes. */ - xTaskWokenByTx = pdFALSE; - - /* The interrupt was caused by the THR becoming empty. Are there any - more characters to transmit? Note whether or not the Tx interrupt has - woken a task. */ - if( xQueueReceiveFromISR( xCharsForTx, &cTxByte, &xTaskWokenByTx ) == pdTRUE ) - { - /* A character was retrieved from the queue so can be sent to the - THR now. */ - TDR1 = cTxByte; - - /* Clear the interrupt. */ - SSR1 &= ~serTX_INTERRUPT; - } - else - { - /* Queue empty, nothing to send so turn off the Tx interrupt. */ - serTX_INTERRUPT_OFF(); - } - - /* This must be the last line in the function. We pass cTaskWokenByTx so - a context switch will occur if the Tx'ed character woke a task that has - a priority higher than the task we interrupted. */ - portEXIT_SWITCHING_ISR( xTaskWokenByTx ); -} -/*-----------------------------------------------------------*/ - -/* - * This ISR cannot cause a context switch so requires no special - * considerations. - */ -void vCOM_1_Error_ISR( void ) -{ -volatile unsigned portCHAR ucIn; - - ucIn = SSR1; - SSR1 = 0; -} - diff --git a/Demo/H8S/RTOSDemo/start.asm b/Demo/H8S/RTOSDemo/start.asm deleted file mode 100644 index be99b2108..000000000 --- a/Demo/H8S/RTOSDemo/start.asm +++ /dev/null @@ -1,115 +0,0 @@ -;/**************************************************************** -;KPIT Cummins Infosystems Ltd, Pune, India. - 4th September 2003. -; -;This program is distributed in the hope that it will be useful, -;but WITHOUT ANY WARRANTY; without even the implied warranty of -;MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE -; -;*****************************************************************/ - - -;********************************************************************* -; File: start.asm -; -; -; desc: -; -; System initialisation routine - entry point for the application. -; The stack pointer is initialised, then the hardware initialisation -; routine called. The static data areas are then initialised, before -; the main function is executed. A simple exit funtion is also -; supplied -; -;********************************************************************* - -#ifdef __H8300H__ - -#ifdef __NORMAL_MODE__ - .h8300hn -#else - .h8300h -#endif - -#endif /*_H8300H_ */ - -#ifdef __H8300S__ - -#ifdef __NORMAL_MODE__ - .h8300sn -#else - .h8300s -#endif - -#endif /* __H8300S__ */ - - .section .text - .global _start -#if DEBUG - .extern _exit -#endif - - .extern _hw_initialise - .extern _main - - .extern _data - .extern _mdata - .extern _edata - .extern _bss - .extern _ebss - .extern _stack - -_start: - ; initialise the SP for non-vectored code - mov.l #_stack,er7 - ; call the hardware initialiser - jsr @_hw_initialise -#ifdef ROMSTART - ; get the boundaries for the .data section initialisation - mov.l #_data,er0 - mov.l #_edata,er1 - mov.l #_mdata,er2 - cmp.l er0,er1 - beq start_1 -start_l: - mov.b @er2,r3l ;get from src - mov.b r3l,@er0 ;place in dest - inc.l #1,er2 ;inc src - inc.l #1,er0 ;inc dest - cmp.l er0,er1 ;dest == edata? - bne start_l -start_1: -#endif //ROMSTART - ; zero out bss - mov.l #_bss,er0 - mov.l #_ebss,er1 - cmp.l er0,er1 - beq start_3 - sub.b r2l,r2l -start_2: - mov.b r2l,@er0 - inc.l #1,er0 - cmp.l er0,er1 - bne start_2 -start_3: -#ifdef CPPAPP - ;Initialize global constructor - jsr @___main -#endif - - ; call the mainline - jsr @_main - - - mov.l er0,er4 - - ;call to exit -#if DEBUG - jsr @_exit -#endif -#if RELEASE - exit: - bra exit -#endif - - - diff --git a/Demo/H8S/RTOSDemo/vects.c b/Demo/H8S/RTOSDemo/vects.c deleted file mode 100644 index f220983a9..000000000 --- a/Demo/H8S/RTOSDemo/vects.c +++ /dev/null @@ -1,137 +0,0 @@ -/**************************************************************** -KPIT Cummins Infosystems Ltd, Pune, India. - 19-June-2003. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -*****************************************************************/ - -void start(void); /* Startup code (in start.asm) */ - -/* - * Manual context switch trap function. - */ -void vPortYield( void ); - -/* - * The RTOS tick ISR. - */ -void vTickISR( void ); - -/* - * Serial port ISR functions. - */ -void vCOM_1_Rx_ISR( void ); -void vCOM_1_Tx_ISR( void ); -void vCOM_1_Error_ISR( void ); - - -typedef void (*fp) (void); -#define VECT_SECT __attribute__ ((section (".vects"))) - -const fp HardwareVectors[] VECT_SECT = { -start, /* vector 0 */ -(fp)(0), /* vector 1 */ -(fp)(0), /* vector 2 */ -(fp)(0), /* vector 3 */ -(fp)(0), /* vector 4 */ -(fp)(0), /* vector 5 */ -(fp)(0), /* vector 6 */ -(fp)(0), /* vector 7 */ -vPortYield, /* vector 8 */ -(fp)(0), /* vector 9 */ -(fp)(0), /* vector 10 */ -(fp)(0), /* vector 11 */ -(fp)(0), /* vector 12 */ -(fp)(0), /* vector 13 */ -(fp)(0), /* vector 14 */ -(fp)(0), /* vector 15 */ -(fp)(0), /* vector 16 */ -(fp)(0), /* vector 17 */ -(fp)(0), /* vector 18 */ -(fp)(0), /* vector 19 */ -(fp)(0), /* vector 20 */ -(fp)(0), /* vector 21 */ -(fp)(0), /* vector 22 */ -(fp)(0), /* vector 23 */ -(fp)(0), /* vector 24 */ -(fp)(0), /* vector 25 */ -(fp)(0), /* vector 26 */ -(fp)(0), /* vector 27 */ -(fp)(0), /* vector 28 */ -(fp)(0), /* vector 29 */ -(fp)(0), /* vector 30 */ -(fp)(0), /* vector 31 */ -(fp)(0), /* vector 32 */ -(fp)(0), /* vector 33 */ -(fp)(0), /* vector 34 */ -(fp)(0), /* vector 35 */ -(fp)(0), /* vector 36 */ -(fp)(0), /* vector 37 */ -(fp)(0), /* vector 38 */ -(fp)(0), /* vector 39 */ -vTickISR, /* vector 40 */ -(fp)(0), /* vector 41 */ -(fp)(0), /* vector 42 */ -(fp)(0), /* vector 43 */ -(fp)(0), /* vector 44 */ -(fp)(0), /* vector 45 */ -(fp)(0), /* vector 46 */ -(fp)(0), /* vector 47 */ -(fp)(0), /* vector 48 */ -(fp)(0), /* vector 49 */ -(fp)(0), /* vector 50 */ -(fp)(0), /* vector 51 */ -(fp)(0), /* vector 52 */ -(fp)(0), /* vector 53 */ -(fp)(0), /* vector 54 */ -(fp)(0), /* vector 55 */ -(fp)(0), /* vector 56 */ -(fp)(0), /* vector 57 */ -(fp)(0), /* vector 58 */ -(fp)(0), /* vector 59 */ -(fp)(0), /* vector 60 */ -(fp)(0), /* vector 61 */ -(fp)(0), /* vector 62 */ -(fp)(0), /* vector 63 */ -(fp)(0), /* vector 64 */ -(fp)(0), /* vector 65 */ -(fp)(0), /* vector 66 */ -(fp)(0), /* vector 67 */ -(fp)(0), /* vector 68 */ -(fp)(0), /* vector 69 */ -(fp)(0), /* vector 70 */ -(fp)(0), /* vector 71 */ -(fp)(0), /* vector 72 */ -(fp)(0), /* vector 73 */ -(fp)(0), /* vector 74 */ -(fp)(0), /* vector 75 */ -(fp)(0), /* vector 76 */ -(fp)(0), /* vector 77 */ -(fp)(0), /* vector 78 */ -(fp)(0), /* vector 79 */ -(fp)(0), /* vector 80 */ -(fp)(0), /* vector 81 */ -(fp)(0), /* vector 82 */ -(fp)(0), /* vector 83 */ -vCOM_1_Error_ISR, /* vector 84 */ -vCOM_1_Rx_ISR, /* vector 85 */ -vCOM_1_Tx_ISR, /* vector 86 */ -(fp)(0), /* vector 87 */ -(fp)(0), /* vector 88 */ -(fp)(0), /* vector 89 */ -(fp)(0), /* vector 90 */ -(fp)(0), /* vector 91 */ -(fp)(0), /* vector 92 */ -(fp)(0), /* vector 93 */ -(fp)(0), /* vector 94 */ -(fp)(0), /* vector 95 */ -(fp)(0), /* vector 96 */ -(fp)(0), /* vector 97 */ -(fp)(0), /* vector 98 */ -(fp)(0), /* vector 99 */ -(fp)(0), /* vector 100 */ -(fp)(0), /* vector 101 */ -(fp)(0), /* vector 102 */ -(fp)(0) /* vector 103 */ -}; diff --git a/Demo/HCS12_CodeWarrior_banked/CODE/Byte1.C b/Demo/HCS12_CodeWarrior_banked/CODE/Byte1.C deleted file mode 100644 index 7acd81842..000000000 --- a/Demo/HCS12_CodeWarrior_banked/CODE/Byte1.C +++ /dev/null @@ -1,145 +0,0 @@ -/** ################################################################### -** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. -** Filename : Byte1.C -** Project : RTOSDemo -** Processor : MC9S12DP256BCPV -** Beantype : ByteIO -** Version : Bean 02.019, Driver 01.03, CPU db: 2.87.283 -** Compiler : Metrowerks HC12 C Compiler -** Date/Time : 16/06/2005, 21:10 -** Abstract : -** This bean "ByteIO" implements an one-byte input/output. -** It uses one 8-bit port. -** Note: This bean is set to work in Output direction only. -** Methods of this bean are mostly implemented as a macros -** (if supported by target langauage and compiler). -** Settings : -** Port name : B -** -** Initial direction : Output (direction cannot be changed) -** Initial output value : 255 = 0FFH -** Initial pull option : off -** -** 8-bit data register : PORTB [1] -** 8-bit control register : DDRB [3] -** -** ---------------------------------------------------- -** Bit | Pin | Name -** ---------------------------------------------------- -** 0 | 24 | PB0_ADDR0_DATA0 -** 1 | 25 | PB1_ADDR1_DATA1 -** 2 | 26 | PB2_ADDR2_DATA2 -** 3 | 27 | PB3_ADDR3_DATA3 -** 4 | 28 | PB4_ADDR4_DATA4 -** 5 | 29 | PB5_ADDR5_DATA5 -** 6 | 30 | PB6_ADDR6_DATA6 -** 7 | 31 | PB7_ADDR7_DATA7 -** ---------------------------------------------------- -** Contents : -** PutBit - void Byte1_PutBit(byte Bit,bool Val); -** NegBit - void Byte1_NegBit(byte Bit); -** -** (c) Copyright UNIS, spol. s r.o. 1997-2002 -** UNIS, spol. s r.o. -** Jundrovska 33 -** 624 00 Brno -** Czech Republic -** http : www.processorexpert.com -** mail : info@processorexpert.com -** ###################################################################*/ - - -/* MODULE Byte1. */ - -#include "Byte1.h" -/*Including shared modules, which are used for all project*/ -#include "PE_Types.h" -#include "PE_Error.h" -#include "PE_Const.h" -#include "IO_Map.h" -#include "PE_Timer.h" - -#include "Cpu.h" - -/* Definition of DATA and CODE segments for this bean. User can specify where - these segments will be located on "Build options" tab of the selected CPU bean. */ -#pragma DATA_SEG Byte1_DATA /* Data section for this module. */ -#pragma CODE_SEG Byte1_CODE /* Code section for this module. */ - -/* -** =================================================================== -** Method : Byte1_GetMsk (bean ByteIO) -** -** Description : -** This method is internal. It is used by Processor Expert -** only. -** =================================================================== -*/ -byte Byte1_Table[8]={ 1, 2, 4, 8, 16, 32, 64, 128 }; /* Table of mask constants */ - -byte Byte1_GetMsk(byte Value) -{ - return((Value<8)?Byte1_Table[Value]:0); /* Return appropriate bit mask */ -} - -/* -** =================================================================== -** Method : Byte1_PutBit (bean ByteIO) -** -** Description : -** This method writes the new value to the specified bit -** of the output value. -** Parameters : -** NAME - DESCRIPTION -** Bitnum - Number of the bit (0 to 7) -** Val - New value of the bit (FALSE or TRUE) -** FALSE = "0" or "Low", TRUE = "1" or "High" -** Returns : Nothing -** =================================================================== -*/ -void Byte1_PutBit(byte BitNum, byte Value) -{ - byte Mask=Byte1_GetMsk(BitNum); /* Temporary variable - bit mask */ - - if (Mask) /* Is bit mask correct? */ - if (Value) { /* Is it one to be written? */ - PORTB |= Mask; /* Set appropriate bit on port */ - } - else { /* Is it zero to be written? */ - PORTB &= ~Mask; /* Clear appropriate bit on port */ - } -} - -/* -** =================================================================== -** Method : Byte1_NegBit (bean ByteIO) -** -** Description : -** This method negates (invertes) the specified bit of the -** output value. -** Parameters : -** NAME - DESCRIPTION -** Bit - Number of the bit to invert (0 to 7) -** Returns : Nothing -** =================================================================== -*/ -void Byte1_NegBit(byte BitNum) -{ - byte Mask=Byte1_GetMsk(BitNum); /* Temporary variable - bit mask */ - - if (Mask) { /* Is bit mask correct? */ - PORTB ^= Mask; /* Negate appropriate bit on port */ - } -} - - -/* END Byte1. */ - -/* -** ################################################################### -** -** This file was created by UNIS Processor Expert 03.33 for -** the Motorola HCS12 series of microcontrollers. -** -** ################################################################### -*/ diff --git a/Demo/HCS12_CodeWarrior_banked/CODE/Byte1.H b/Demo/HCS12_CodeWarrior_banked/CODE/Byte1.H deleted file mode 100644 index 028d1e3c1..000000000 --- a/Demo/HCS12_CodeWarrior_banked/CODE/Byte1.H +++ /dev/null @@ -1,111 +0,0 @@ -/** ################################################################### -** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. -** Filename : Byte1.H -** Project : RTOSDemo -** Processor : MC9S12DP256BCPV -** Beantype : ByteIO -** Version : Bean 02.019, Driver 01.03, CPU db: 2.87.283 -** Compiler : Metrowerks HC12 C Compiler -** Date/Time : 16/06/2005, 21:10 -** Abstract : -** This bean "ByteIO" implements an one-byte input/output. -** It uses one 8-bit port. -** Note: This bean is set to work in Output direction only. -** Methods of this bean are mostly implemented as a macros -** (if supported by target langauage and compiler). -** Settings : -** Port name : B -** -** Initial direction : Output (direction cannot be changed) -** Initial output value : 255 = 0FFH -** Initial pull option : off -** -** 8-bit data register : PORTB [1] -** 8-bit control register : DDRB [3] -** -** ---------------------------------------------------- -** Bit | Pin | Name -** ---------------------------------------------------- -** 0 | 24 | PB0_ADDR0_DATA0 -** 1 | 25 | PB1_ADDR1_DATA1 -** 2 | 26 | PB2_ADDR2_DATA2 -** 3 | 27 | PB3_ADDR3_DATA3 -** 4 | 28 | PB4_ADDR4_DATA4 -** 5 | 29 | PB5_ADDR5_DATA5 -** 6 | 30 | PB6_ADDR6_DATA6 -** 7 | 31 | PB7_ADDR7_DATA7 -** ---------------------------------------------------- -** Contents : -** PutBit - void Byte1_PutBit(byte Bit,bool Val); -** NegBit - void Byte1_NegBit(byte Bit); -** -** (c) Copyright UNIS, spol. s r.o. 1997-2002 -** UNIS, spol. s r.o. -** Jundrovska 33 -** 624 00 Brno -** Czech Republic -** http : www.processorexpert.com -** mail : info@processorexpert.com -** ###################################################################*/ - -#ifndef __Byte1_H -#define __Byte1_H - -/* MODULE Byte1. */ - -/*Including shared modules, which are used in the whole project*/ -#include "PE_Types.h" -#include "PE_Error.h" -#include "PE_Const.h" -#include "IO_Map.h" -#include "PE_Timer.h" - -#include "Cpu.h" - -#pragma CODE_SEG Byte1_CODE /* Code section for this module. */ - -/* -** =================================================================== -** Method : Byte1_PutBit (bean ByteIO) -** -** Description : -** This method writes the new value to the specified bit -** of the output value. -** Parameters : -** NAME - DESCRIPTION -** BitNum - Number of the bit (0 to 7) -** Val - New value of the bit (FALSE or TRUE) -** FALSE = "0" or "Low", TRUE = "1" or "High" -** Returns : Nothing -** =================================================================== -*/ -void Byte1_PutBit(byte BitNum, byte Value); - -/* -** =================================================================== -** Method : Byte1_NegBit (bean ByteIO) -** -** Description : -** This method negates (invertes) the specified bit of the -** output value. -** Parameters : -** NAME - DESCRIPTION -** BitNum - Number of the bit to invert (0 to 7) -** Returns : Nothing -** =================================================================== -*/ -void Byte1_NegBit(byte BitNum); - -#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */ - -/* END Byte1. */ - -#endif /* __Byte1_H*/ -/* -** ################################################################### -** -** This file was created by UNIS Processor Expert 03.33 for -** the Motorola HCS12 series of microcontrollers. -** -** ################################################################### -*/ diff --git a/Demo/HCS12_CodeWarrior_banked/CODE/COM0.C b/Demo/HCS12_CodeWarrior_banked/CODE/COM0.C deleted file mode 100644 index e575af48c..000000000 --- a/Demo/HCS12_CodeWarrior_banked/CODE/COM0.C +++ /dev/null @@ -1,205 +0,0 @@ -/** ################################################################### -** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. -** Filename : COM0.C -** Project : RTOSDemo -** Processor : MC9S12DP256BCPV -** Beantype : AsynchroSerial -** Version : Bean 02.231, Driver 01.08, CPU db: 2.87.283 -** Compiler : Metrowerks HC12 C Compiler -** Date/Time : 19/06/2005, 15:07 -** Abstract : -** This bean "AsynchroSerial" implements an asynchronous serial -** communication. The bean supports different settings of -** parity, word width, stop-bit and communication speed, -** user can select interrupt or polling handler. -** Communication speed can be changed also in runtime. -** The bean requires one on-chip asynchronous serial channel. -** Settings : -** Serial channel : SCI0 -** -** Protocol -** Init baud rate : 38400baud -** Width : 8 bits -** Stop bits : 1 -** Parity : none -** Breaks : Disabled -** -** Registers -** Input buffer : SCI0DRL [207] -** Output buffer : SCI0DRL [207] -** Control register : SCI0CR1 [202] -** Mode register : SCI0CR2 [203] -** Baud setting reg. : SCI0BD [200] -** Special register : SCI0SR1 [204] -** -** Input interrupt -** Vector name : INT_SCI0 -** Priority : 1 -** -** Output interrupt -** Vector name : INT_SCI0 -** Priority : 1 -** -** Used pins : -** ---------------------------------------------------- -** Function | On package | Name -** ---------------------------------------------------- -** Input | 89 | PS0_RxD0 -** Output | 90 | PS1_TxD0 -** ---------------------------------------------------- -** -** -** Used baud modes : -** ---------------------------------------------------- -** No. | Mode ID | Baud rate -** ---------------------------------------------------- -** 0 | Bm_38400baud | 38400baud -** 1 | Bm_19200baud | 19200baud -** 2 | Bm_9600baud | 9600baud -** 3 | Bm_4800baud | 4800baud -** ---------------------------------------------------- -** Contents : -** SetBaudRateMode - byte COM0_SetBaudRateMode(byte Mod); -** -** (c) Copyright UNIS, spol. s r.o. 1997-2002 -** UNIS, spol. s r.o. -** Jundrovska 33 -** 624 00 Brno -** Czech Republic -** http : www.processorexpert.com -** mail : info@processorexpert.com -** ###################################################################*/ - -/* MODULE COM0. */ - -#pragma MESSAGE DISABLE C4002 /* WARNING C4002: Result not used is ignored */ -#pragma MESSAGE DISABLE C4301 /* INFORMATION C4301: Inline expansion done for function call */ - -#include "COM0.h" -#include "TickTimer.h" -#include "Byte1.h" - -/* Definition of DATA and CODE segments for this bean. User can specify where - these segments will be located on "Build options" tab of the selected CPU bean. */ -#pragma DATA_SEG COM0_DATA /* Data section for this module. */ -#pragma CODE_SEG COM0_CODE /* Code section for this module. */ - - -#define OVERRUN_ERR 1 /* Overrun error flag bit */ -#define FRAMING_ERR 2 /* Framing error flag bit */ -#define PARITY_ERR 4 /* Parity error flag bit */ -#define CHAR_IN_RX 8 /* Char is in RX buffer */ -#define FULL_TX 16 /* Full transmit buffer */ -#define RUNINT_FROM_TX 32 /* Interrupt is in progress */ -#define FULL_RX 64 /* Full receive buffer */ -#define NOISE_ERR 128 /* Noise erorr flag bit */ -#define IDLE_ERR 256 /* Idle character flag bit */ -#define BREAK_ERR 512 /* Break detect */ - -static word SerFlag; /* Flags for serial communication */ - /* Bits: 0 - OverRun error */ - /* 1 - Framing error */ - /* 2 - Parity error */ - /* 3 - Char in RX buffer */ - /* 4 - Full TX buffer */ - /* 5 - Running int from TX */ - /* 6 - Full RX buffer */ - /* 7 - Noise error */ - /* 8 - Idle character */ - /* 9 - Break detected */ - /* 10 - Unused */ -static word PrescHigh; -static byte NumMode; /* Number of selected baud mode */ - - -/* -** =================================================================== -** Method : HWEnDi (bean AsynchroSerial) -** -** Description : -** This method is internal. It is used by Processor Expert -** only. -** =================================================================== -*/ -static void HWEnDi(void) -{ - SCI0CR2_TE = 1; /* Enable transmitter */ - SCI0CR2_RE = 1; /* Enable receiver */ - SCI0CR2_RIE = 1; /* Enable recieve interrupt */ -} - -/* -** =================================================================== -** Method : COM0_SetBaudRateMode (bean AsynchroSerial) -** -** Description : -** This method changes the channel communication speed (baud -** rate). This method can be used only if you specify a list -** of possible period settings at design time (see - Runtime setting - from a list of values). -** Each of these settings constitutes a mode and Processor -** Expert^[TM] assigns them a mode identifier. The prescaler -** and compare values corresponding to each mode are -** calculated at design time. You may switch modes at -** runtime by referring only to a mode identifier. No -** run-time calculations are performed, all the calculations -** are performed at design time. -** Parameters : -** NAME - DESCRIPTION -** Mod - Timing mode to set -** Returns : -** --- - Error code, possible codes: -** ERR_OK - OK -** ERR_SPEED - This device does not work in -** the active speed mode -** =================================================================== -*/ -byte COM0_SetBaudRateMode(byte Mod) -{ - static const word COM0_PrescHigh[4] = {41,81,163,326}; - - if(Mod >= 4) /* Is mode in baud mode list */ - return ERR_VALUE; /* If no then error */ - NumMode = Mod; /* New baud mode */ - PrescHigh = COM0_PrescHigh[Mod]; /* Prescaler in high speed mode */ - SCI0BD = PrescHigh; /* Set prescaler bits */ - return ERR_OK; /* OK */ -} - -/* -** =================================================================== -** Method : COM0_Init (bean AsynchroSerial) -** -** Description : -** This method is internal. It is used by Processor Expert -** only. -** =================================================================== -*/ -void COM0_Init(void) -{ - PrescHigh = 41; /* Precaler in high speed mode */ - SerFlag = 0; /* Reset flags */ - NumMode = 0; /* Number of selected baud mode */ - /* SCI0CR1: LOOPS=0,SCISWAI=1,RSRC=0,M=0,WAKE=0,ILT=0,PE=0,PT=0 */ - SCI0CR1 = 64; /* Set the SCI configuration */ - /* SCI0SR2: ??=0,??=0,??=0,??=0,??=0,BRK13=0,TXDIR=0,RAF=0 */ - SCI0SR2 = 0; /* Set the Break Character Length and Transmitter pin data direction in Single-wire mode */ - SCI0SR1; /* Reset interrupt request flags */ - /* SCI0CR2: SCTIE=0,TCIE=0,RIE=0,ILIE=0,TE=0,RE=0,RWU=0,SBK=0 */ - SCI0CR2 = 0; /* Disable error interrupts */ - SCI0BD = PrescHigh; /* Set prescaler bits */ - HWEnDi(); /* Enable/disable device according to status flags */ -} - - -/* END COM0. */ - - -/* -** ################################################################### -** -** This file was created by UNIS Processor Expert 03.33 for -** the Motorola HCS12 series of microcontrollers. -** -** ################################################################### -*/ diff --git a/Demo/HCS12_CodeWarrior_banked/CODE/COM0.H b/Demo/HCS12_CodeWarrior_banked/CODE/COM0.H deleted file mode 100644 index 3f0e99a23..000000000 --- a/Demo/HCS12_CodeWarrior_banked/CODE/COM0.H +++ /dev/null @@ -1,191 +0,0 @@ -/** ################################################################### -** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. -** Filename : COM0.H -** Project : RTOSDemo -** Processor : MC9S12DP256BCPV -** Beantype : AsynchroSerial -** Version : Bean 02.231, Driver 01.08, CPU db: 2.87.283 -** Compiler : Metrowerks HC12 C Compiler -** Date/Time : 19/06/2005, 15:07 -** Abstract : -** This bean "AsynchroSerial" implements an asynchronous serial -** communication. The bean supports different settings of -** parity, word width, stop-bit and communication speed, -** user can select interrupt or polling handler. -** Communication speed can be changed also in runtime. -** The bean requires one on-chip asynchronous serial channel. -** Settings : -** Serial channel : SCI0 -** -** Protocol -** Init baud rate : 38400baud -** Width : 8 bits -** Stop bits : 1 -** Parity : none -** Breaks : Disabled -** -** Registers -** Input buffer : SCI0DRL [207] -** Output buffer : SCI0DRL [207] -** Control register : SCI0CR1 [202] -** Mode register : SCI0CR2 [203] -** Baud setting reg. : SCI0BD [200] -** Special register : SCI0SR1 [204] -** -** Input interrupt -** Vector name : INT_SCI0 -** Priority : 1 -** -** Output interrupt -** Vector name : INT_SCI0 -** Priority : 1 -** -** Used pins : -** ---------------------------------------------------- -** Function | On package | Name -** ---------------------------------------------------- -** Input | 89 | PS0_RxD0 -** Output | 90 | PS1_TxD0 -** ---------------------------------------------------- -** -** -** Used baud modes : -** ---------------------------------------------------- -** No. | Mode ID | Baud rate -** ---------------------------------------------------- -** 0 | Bm_38400baud | 38400baud -** 1 | Bm_19200baud | 19200baud -** 2 | Bm_9600baud | 9600baud -** 3 | Bm_4800baud | 4800baud -** ---------------------------------------------------- -** Contents : -** SetBaudRateMode - byte COM0_SetBaudRateMode(byte Mod); -** -** (c) Copyright UNIS, spol. s r.o. 1997-2002 -** UNIS, spol. s r.o. -** Jundrovska 33 -** 624 00 Brno -** Czech Republic -** http : www.processorexpert.com -** mail : info@processorexpert.com -** ###################################################################*/ - -#ifndef __COM0 -#define __COM0 - -/* MODULE COM0. */ - -#include "Cpu.h" - -#define COM0_Bm_38400baud 0 /* Constant for switch to mode 0 */ -#define COM0_Bm_19200baud 1 /* Constant for switch to mode 1 */ -#define COM0_Bm_9600baud 2 /* Constant for switch to mode 2 */ -#define COM0_Bm_4800baud 3 /* Constant for switch to mode 3 */ - - - -#ifndef __BWUserType_tItem -#define __BWUserType_tItem - typedef struct { /* Item of the index table for possible baudrates */ - word div; /* divisior */ - byte val; /* values of the prescalers */ - } tItem; -#endif -#ifndef __BWUserType_COM0_TError -#define __BWUserType_COM0_TError -typedef union { - byte err; - struct { - bool OverRun : 1; /* OverRun error flag */ - bool Framing : 1; /* Framing error flag */ - bool Parity : 1; /* Parity error flag */ - bool RxBufOvf : 1; /* Rx buffer full error flag */ - bool Noise : 1; /* Noise error */ - bool Break : 1; /* Break detect */ - bool Idle : 1; /* Idle characted */ - }errName; -} COM0_TError; -#endif -#ifndef __BWUserType_TDirection -#define __BWUserType_TDirection - typedef enum { /* */ - TXD_INPUT, - TXD_OUTPUT - } TDirection; -#endif - -#ifndef __BWUserType_COM0_TComData -#define __BWUserType_COM0_TComData - typedef byte COM0_TComData ; /* User type for communication. Size of this type depends on the communication data witdh. */ -#endif - -#pragma CODE_SEG COM0_CODE /* Code section for this module. */ - -byte COM0_SetBaudRateMode(byte Mod); -/* -** =================================================================== -** Method : COM0_SetBaudRateMode (bean AsynchroSerial) -** -** Description : -** This method changes the channel communication speed (baud -** rate). This method can be used only if you specify a list -** of possible period settings at design time (see - Runtime setting - from a list of values). -** Each of these settings constitutes a mode and Processor -** Expert^[TM] assigns them a mode identifier. The prescaler -** and compare values corresponding to each mode are -** calculated at design time. You may switch modes at -** runtime by referring only to a mode identifier. No -** run-time calculations are performed, all the calculations -** are performed at design time. -** Parameters : -** NAME - DESCRIPTION -** Mod - Timing mode to set -** Returns : -** --- - Error code, possible codes: -** ERR_OK - OK -** ERR_SPEED - This device does not work in -** the active speed mode -** =================================================================== -*/ - -#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */ -__interrupt void COM0_Interrupt(void); -#pragma CODE_SEG COM0_CODE /* Code section for this module. */ -/* -** =================================================================== -** Method : COM0_Interrupt (bean AsynchroSerial) -** -** Description : -** This method is internal. It is used by Processor Expert -** only. -** =================================================================== -*/ - - -void COM0_Init(void); -/* -** =================================================================== -** Method : COM0_Init (bean AsynchroSerial) -** -** Description : -** This method is internal. It is used by Processor Expert -** only. -** =================================================================== -*/ - - -#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */ - -/* END COM0. */ - -/* -** ################################################################### -** -** This file was created by UNIS Processor Expert 03.33 for -** the Motorola HCS12 series of microcontrollers. -** -** ################################################################### -*/ - -#endif /* ifndef __COM0 */ diff --git a/Demo/HCS12_CodeWarrior_banked/CODE/Copy of Vectors.c b/Demo/HCS12_CodeWarrior_banked/CODE/Copy of Vectors.c deleted file mode 100644 index 7842537ce..000000000 --- a/Demo/HCS12_CodeWarrior_banked/CODE/Copy of Vectors.c +++ /dev/null @@ -1,112 +0,0 @@ -/** ################################################################### -** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. -** Filename : Cpu.C -** Project : RTOSDemo -** Processor : MC9S12DP256BCPV -** Beantype : MC9S12DP256_112 -** Version : Bean 01.148, Driver 01.09, CPU db: 2.87.283 -** Compiler : Metrowerks HC12 C Compiler -** Date/Time : 16/06/2005, 19:18 -** Abstract : -** This bean "MC9S12DP256_112" implements properties, methods, -** and events of the CPU. -** Settings : -** -** Contents : -** EnableInt - void Cpu_EnableInt(void); -** DisableInt - void Cpu_DisableInt(void); -** -** (c) Copyright UNIS, spol. s r.o. 1997-2002 -** UNIS, spol. s r.o. -** Jundrovska 33 -** 624 00 Brno -** Czech Republic -** http : www.processorexpert.com -** mail : info@processorexpert.com -** ###################################################################*/ - - -#include "Cpu.h" -#include "TickTimer.h" -#include "Byte1.h" - -extern void near _EntryPoint(void); /* Startup routine */ -extern void near vPortTickInterrupt( void ); -extern void near vPortYield( void ); -extern void near vCOM0_ISR( void ); - -typedef void (*near tIsrFunc)(void); -const tIsrFunc _vect[] @0xFF80 = { /* Interrupt table */ - Cpu_Interrupt, /* 0 Default (unused) interrupt */ - Cpu_Interrupt, /* 1 Default (unused) interrupt */ - Cpu_Interrupt, /* 2 Default (unused) interrupt */ - Cpu_Interrupt, /* 3 Default (unused) interrupt */ - Cpu_Interrupt, /* 4 Default (unused) interrupt */ - Cpu_Interrupt, /* 5 Default (unused) interrupt */ - Cpu_Interrupt, /* 6 Default (unused) interrupt */ - Cpu_Interrupt, /* 7 Default (unused) interrupt */ - Cpu_Interrupt, /* 8 Default (unused) interrupt */ - Cpu_Interrupt, /* 9 Default (unused) interrupt */ - Cpu_Interrupt, /* 10 Default (unused) interrupt */ - Cpu_Interrupt, /* 11 Default (unused) interrupt */ - Cpu_Interrupt, /* 12 Default (unused) interrupt */ - Cpu_Interrupt, /* 13 Default (unused) interrupt */ - Cpu_Interrupt, /* 14 Default (unused) interrupt */ - Cpu_Interrupt, /* 15 Default (unused) interrupt */ - Cpu_Interrupt, /* 16 Default (unused) interrupt */ - Cpu_Interrupt, /* 17 Default (unused) interrupt */ - Cpu_Interrupt, /* 18 Default (unused) interrupt */ - Cpu_Interrupt, /* 19 Default (unused) interrupt */ - Cpu_Interrupt, /* 20 Default (unused) interrupt */ - Cpu_Interrupt, /* 21 Default (unused) interrupt */ - Cpu_Interrupt, /* 22 Default (unused) interrupt */ - Cpu_Interrupt, /* 23 Default (unused) interrupt */ - Cpu_Interrupt, /* 24 Default (unused) interrupt */ - Cpu_Interrupt, /* 25 Default (unused) interrupt */ - Cpu_Interrupt, /* 26 Default (unused) interrupt */ - Cpu_Interrupt, /* 27 Default (unused) interrupt */ - Cpu_Interrupt, /* 28 Default (unused) interrupt */ - Cpu_Interrupt, /* 29 Default (unused) interrupt */ - Cpu_Interrupt, /* 30 Default (unused) interrupt */ - Cpu_Interrupt, /* 31 Default (unused) interrupt */ - Cpu_Interrupt, /* 32 Default (unused) interrupt */ - Cpu_Interrupt, /* 33 Default (unused) interrupt */ - Cpu_Interrupt, /* 34 Default (unused) interrupt */ - Cpu_Interrupt, /* 35 Default (unused) interrupt */ - Cpu_Interrupt, /* 36 Default (unused) interrupt */ - Cpu_Interrupt, /* 37 Default (unused) interrupt */ - Cpu_Interrupt, /* 38 Default (unused) interrupt */ - Cpu_Interrupt, /* 39 Default (unused) interrupt */ - Cpu_Interrupt, /* 40 Default (unused) interrupt */ - Cpu_Interrupt, /* 41 Default (unused) interrupt */ - Cpu_Interrupt, /* 42 Default (unused) interrupt */ - vCOM0_ISR, - Cpu_Interrupt, /* 44 Default (unused) interrupt */ - Cpu_Interrupt, /* 45 Default (unused) interrupt */ - Cpu_Interrupt, /* 46 Default (unused) interrupt */ - Cpu_Interrupt, /* 47 Default (unused) interrupt */ - Cpu_Interrupt, /* 48 Default (unused) interrupt */ - Cpu_Interrupt, /* 49 Default (unused) interrupt */ - Cpu_Interrupt, /* 50 Default (unused) interrupt */ - Cpu_Interrupt, /* 51 Default (unused) interrupt */ - Cpu_Interrupt, /* 52 Default (unused) interrupt */ - Cpu_Interrupt, /* 53 Default (unused) interrupt */ - Cpu_Interrupt, /* 54 Default (unused) interrupt */ - vPortTickInterrupt, - Cpu_Interrupt, /* 56 Default (unused) interrupt */ - Cpu_Interrupt, /* 57 Default (unused) interrupt */ - Cpu_Interrupt, /* 58 Default (unused) interrupt */ - vPortYield, /* 59 Default (unused) interrupt */ - Cpu_Interrupt, /* 60 Default (unused) interrupt */ - Cpu_Interrupt, /* 61 Default (unused) interrupt */ - Cpu_Interrupt, /* 62 Default (unused) interrupt */ - _EntryPoint /* Reset vector */ - }; -/* -** ################################################################### -** -** This file was created by UNIS Processor Expert 03.33 for -** the Motorola HCS12 series of microcontrollers. -** -** ################################################################### -*/ diff --git a/Demo/HCS12_CodeWarrior_banked/CODE/Cpu.C b/Demo/HCS12_CodeWarrior_banked/CODE/Cpu.C deleted file mode 100644 index a204a0b7c..000000000 --- a/Demo/HCS12_CodeWarrior_banked/CODE/Cpu.C +++ /dev/null @@ -1,198 +0,0 @@ -/** ################################################################### -** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. -** Filename : Cpu.C -** Project : RTOSDemo -** Processor : MC9S12DP256BCPV -** Beantype : MC9S12DP256_112 -** Version : Bean 01.148, Driver 01.09, CPU db: 2.87.283 -** Compiler : Metrowerks HC12 C Compiler -** Date/Time : 18/06/2005, 16:21 -** Abstract : -** This bean "MC9S12DP256_112" implements properties, methods, -** and events of the CPU. -** Settings : -** -** Contents : -** EnableInt - void Cpu_EnableInt(void); -** DisableInt - void Cpu_DisableInt(void); -** -** (c) Copyright UNIS, spol. s r.o. 1997-2002 -** UNIS, spol. s r.o. -** Jundrovska 33 -** 624 00 Brno -** Czech Republic -** http : www.processorexpert.com -** mail : info@processorexpert.com -** ###################################################################*/ - -/* MODULE Cpu. */ - -#include "TickTimer.h" -#include "Byte1.h" -#include "COM0.h" -#include "PE_Types.h" -#include "PE_Error.h" -#include "PE_Const.h" -#include "IO_Map.h" -#include "PE_Timer.h" -#include "Events.h" -#include "Cpu.h" - -#define CGM_DELAY 3071UL - - -/* Global variables */ -volatile byte CCR_reg; /* Current CCR reegister */ -byte CpuMode = HIGH_SPEED; /* Current speed mode */ - - -/* -** =================================================================== -** Method : Cpu_Interrupt (bean MC9S12DP256_112) -** -** Description : -** This method is internal. It is used by Processor Expert -** only. -** =================================================================== -*/ -#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */ - -__interrupt void Cpu_Interrupt(void) -{ -} - -#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */ - -/* -** =================================================================== -** Method : Cpu_DisableInt (bean MC9S12DP256_112) -** -** Description : -** Disable maskable interrupts -** Parameters : None -** Returns : Nothing -** =================================================================== -*/ -/* -void Cpu_DisableInt(void) - -** This method is implemented as macro in the header module. ** -*/ - -/* -** =================================================================== -** Method : Cpu_EnableInt (bean MC9S12DP256_112) -** -** Description : -** Enable maskable interrupts -** Parameters : None -** Returns : Nothing -** =================================================================== -*/ -/* -void Cpu_EnableInt(void) - -** This method is implemented as macro in the header module. ** -*/ - -/* -** =================================================================== -** Method : _EntryPoint (bean MC9S12DP256_112) -** -** Description : -** This method is internal. It is used by Processor Expert -** only. -** =================================================================== -*/ -extern void _Startup(void); /* Forward declaration of external startup function declared in file Start12.c */ -#define INITRG_ADR 0x0011 /* Register map position register */ -#pragma NO_FRAME -#pragma NO_EXIT -void _EntryPoint(void) -{ - /*** ### MC9S12DP256_112 "Cpu" init code ... ***/ - /*** PE initialization code after reset ***/ - /* Initialization of the registers INITRG, INITRM, INITEE is done to protect them to be written accidentally later by the application */ - *(byte*)INITRG_ADR = 0; /* Set the register map position */ - asm nop; /* nop instruction */ - INITRM=1; /* Set the RAM map position */ - INITEE=1; /* Set the EEPROM map position */ - /* MISC: ??=0,??=0,??=0,??=0,EXSTR1=0,EXSTR0=0,ROMHM=0,ROMON=1 */ - MISC=1; - /* System clock initialization */ - CLKSEL=0; - CLKSEL_PLLSEL = 0; /* Select clock source from XTAL */ - PLLCTL_PLLON = 0; /* Disable the PLL */ - SYNR = 24; /* Set the multiplier register */ - REFDV = 15; /* Set the divider register */ - PLLCTL = 192; - PLLCTL_PLLON = 1; /* Enable the PLL */ - while(!CRGFLG_LOCK); /* Wait */ - CLKSEL_PLLSEL = 1; /* Select clock source from PLL */ - /*** End of PE initialization code after reset ***/ - - __asm jmp _Startup; /* Jump to C startup code */ -} - -/* -** =================================================================== -** Method : PE_low_level_init (bean MC9S12DP256_112) -** -** Description : -** This method is internal. It is used by Processor Expert -** only. -** =================================================================== -*/ -void PE_low_level_init(void) -{ - /* Common initialization of the CPU registers */ -/* TSCR1: TEN=0,TSWAI=0,TSFRZ=1 */ - output( TSCR1, input( TSCR1 ) & ~192 | 32 ); -/* TCTL2: OM0=0,OL0=0 */ - output( TCTL2, input( TCTL2 ) & ~3 ); -/* TCTL1: OM7=0,OL7=0 */ - output( TCTL1, input( TCTL1 ) & ~192 ); -/* TIE: C0I=0 */ - output( TIE, input( TIE ) & ~1 ); -/* TTOV: TOV0=0 */ - output( TTOV, input( TTOV ) & ~1 ); -/* TSCR2: TOI=0,TCRE=1 */ - output( TSCR2, input( TSCR2 ) & ~128 | 8 ); -/* TIOS: IOS7=1,IOS0=1 */ - output( TIOS, input( TIOS ) | 129 ); -/* PWMCTL: PSWAI=0,PFRZ=0 */ - output( PWMCTL, input( PWMCTL ) & ~12 ); -/* PWMSDN: PWMIF=0,PWMIE=0,PWMRSTRT=0,PWMLVL=0,??=0,PWM7IN=0,PWM7INL=0,PWM7ENA=0 */ - output( PWMSDN, 0 ); -/* ICSYS: SH37=0,SH26=0,SH15=0,SH04=0,TFMOD=0,PACMX=0,BUFEN=0,LATQ=0 */ - output( ICSYS, 0 ); -/* MCCTL: MODMC=1 */ - output( MCCTL, input( MCCTL ) | 64 ); - /* ### MC9S12DP256_112 "Cpu" init code ... */ - /* ### TimerInt "TickTimer" init code ... */ - TickTimer_Init(); - /* ### ByteIO "Byte1" init code ... */ - PORTB = 255; /* Prepare value for output */ - DDRB = 255; /* Set direction to output */ - /* ### Asynchro serial "COM0" init code ... */ - DDRS &= ~1; - PTS |= 2; - DDRS |= 2; - COM0_Init(); - /* Common peripheral initialization - ENABLE */ -/* TSCR1: TEN=1 */ - output( TSCR1, input( TSCR1 ) | 128 ); - INTCR_IRQEN = 0; /* Disable the IRQ interrupt. IRQ interrupt is enabled after CPU reset by default. */ - __DI(); /* Disable interrupts */ -} - -/* END Cpu. */ - -/* -** ################################################################### -** -** This file was created by UNIS Processor Expert 03.33 for -** the Motorola HCS12 series of microcontrollers. -** -** ################################################################### -*/ diff --git a/Demo/HCS12_CodeWarrior_banked/CODE/Cpu.H b/Demo/HCS12_CodeWarrior_banked/CODE/Cpu.H deleted file mode 100644 index 2c554db7f..000000000 --- a/Demo/HCS12_CodeWarrior_banked/CODE/Cpu.H +++ /dev/null @@ -1,111 +0,0 @@ -/** ################################################################### -** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. -** Filename : Cpu.H -** Project : RTOSDemo -** Processor : MC9S12DP256BCPV -** Beantype : MC9S12DP256_112 -** Version : Bean 01.148, Driver 01.09, CPU db: 2.87.283 -** Compiler : Metrowerks HC12 C Compiler -** Date/Time : 14/06/2005, 16:34 -** Abstract : -** This bean "MC9S12DP256_112" implements properties, methods, -** and events of the CPU. -** Settings : -** -** Contents : -** EnableInt - void Cpu_EnableInt(void); -** DisableInt - void Cpu_DisableInt(void); -** -** (c) Copyright UNIS, spol. s r.o. 1997-2002 -** UNIS, spol. s r.o. -** Jundrovska 33 -** 624 00 Brno -** Czech Republic -** http : www.processorexpert.com -** mail : info@processorexpert.com -** ###################################################################*/ - -#ifndef __Cpu -#define __Cpu - -/* Active configuration define symbol */ -#define PEcfg_112pin 1 - -/*Include shared modules, which are used for whole project*/ -#include "PE_Types.h" -#include "PE_Error.h" -#include "PE_Const.h" -#include "IO_Map.h" -#include "PE_Timer.h" - -/* MODULE Cpu. */ - - -/* Global variables */ -extern volatile byte CCR_reg; /* Current CCR reegister */ -extern byte CpuMode; /* Current speed mode */ - - - - -#define Cpu_DisableInt() __DI() /* Disable interrupts */ -/* -** =================================================================== -** Method : Cpu_DisableInt (bean MC9S12DP256_112) -** -** Description : -** Disable maskable interrupts -** Parameters : None -** Returns : Nothing -** =================================================================== -*/ - -#define Cpu_EnableInt() __EI() /* Enable interrupts */ -/* -** =================================================================== -** Method : Cpu_EnableInt (bean MC9S12DP256_112) -** -** Description : -** Enable maskable interrupts -** Parameters : None -** Returns : Nothing -** =================================================================== -*/ - -#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */ - -__interrupt void Cpu_Interrupt(void); -/* -** =================================================================== -** Method : Cpu_Interrupt (bean MC9S12DP256_112) -** -** Description : -** This method is internal. It is used by Processor Expert -** only. -** =================================================================== -*/ - -#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */ - -void PE_low_level_init(void); -/* -** =================================================================== -** Method : PE_low_level_init (bean MC9S12DP256_112) -** -** Description : -** This method is internal. It is used by Processor Expert -** only. -** =================================================================== -*/ - -/* END Cpu. */ - -#endif /* ifndef __Cpu */ -/* -** ################################################################### -** -** This file was created by UNIS Processor Expert 03.33 for -** the Motorola HCS12 series of microcontrollers. -** -** ################################################################### -*/ diff --git a/Demo/HCS12_CodeWarrior_banked/CODE/Events.C b/Demo/HCS12_CodeWarrior_banked/CODE/Events.C deleted file mode 100644 index de1680f54..000000000 --- a/Demo/HCS12_CodeWarrior_banked/CODE/Events.C +++ /dev/null @@ -1,153 +0,0 @@ -/** ################################################################### -** Filename : Events.C -** Project : RTOSDemo -** Processor : MC9S12DP256BCPV -** Beantype : Events -** Version : Driver 01.01 -** Compiler : Metrowerks HC12 C Compiler -** Date/Time : 14/06/2005, 16:34 -** Abstract : -** This is user's event module. -** Put your event handler code here. -** Settings : -** Contents : -** TickTimer_OnInterrupt - void TickTimer_OnInterrupt(void); -** -** (c) Copyright UNIS, spol. s r.o. 1997-2002 -** UNIS, spol. s r.o. -** Jundrovska 33 -** 624 00 Brno -** Czech Republic -** http : www.processorexpert.com -** mail : info@processorexpert.com -** ###################################################################*/ -/* MODULE Events */ - - -/*Including used modules for compilling procedure*/ -#include "Cpu.h" -#include "Events.h" -#include "TickTimer.h" -#include "Byte1.h" -#include "COM0.h" - -/*Include shared modules, which are used for whole project*/ -#include "PE_Types.h" -#include "PE_Error.h" -#include "PE_Const.h" -#include "IO_Map.h" -#include "PE_Timer.h" - -/* -** =================================================================== -** Event : TickTimer_OnInterrupt (module Events) -** -** From bean : TickTimer [TimerInt] -** Description : -** When a timer interrupt occurs this event is called (only -** when the bean is enabled - "Enable" and the events are -** enabled - "EnableEvent"). -** Parameters : None -** Returns : Nothing -** =================================================================== -*/ -void TickTimer_OnInterrupt(void) -{ - /* Write your code here ... */ -} - - -/* -** =================================================================== -** Event : COM0_OnError (module Events) -** -** From bean : COM0 [AsynchroSerial] -** Description : -** This event is called when a channel error (not the error -** returned by a given method) occurs. The errors can be -** read using method. -** Parameters : None -** Returns : Nothing -** =================================================================== -*/ -void COM0_OnError(void) -{ - /* Write your code here ... */ -} - -/* -** =================================================================== -** Event : COM0_OnRxChar (module Events) -** -** From bean : COM0 [AsynchroSerial] -** Description : -** This event is called after a correct character is -** received. This -** Parameters : None -** Returns : Nothing -** =================================================================== -*/ -void COM0_OnRxChar(void) -{ - /* Write your code here ... */ -} - -/* -** =================================================================== -** Event : COM0_OnTxChar (module Events) -** -** From bean : COM0 [AsynchroSerial] -** Description : -** This event is called after a character is transmitted. -** Parameters : None -** Returns : Nothing -** =================================================================== -*/ -void COM0_OnTxChar(void) -{ - /* Write your code here ... */ -} - -/* -** =================================================================== -** Event : COM0_OnFullRxBuf (module Events) -** -** From bean : COM0 [AsynchroSerial] -** Description : -** This event is called when the input buffer is full. -** Parameters : None -** Returns : Nothing -** =================================================================== -*/ -void COM0_OnFullRxBuf(void) -{ - /* Write your code here ... */ -} - -/* -** =================================================================== -** Event : COM0_OnFreeTxBuf (module Events) -** -** From bean : COM0 [AsynchroSerial] -** Description : -** This event is called after the last character in output -** buffer is transmitted. -** Parameters : None -** Returns : Nothing -** =================================================================== -*/ -void COM0_OnFreeTxBuf(void) -{ - /* Write your code here ... */ -} - -/* END Events */ - -/* -** ################################################################### -** -** This file was created by UNIS Processor Expert 03.33 for -** the Motorola HCS12 series of microcontrollers. -** -** ################################################################### -*/ diff --git a/Demo/HCS12_CodeWarrior_banked/CODE/Events.H b/Demo/HCS12_CodeWarrior_banked/CODE/Events.H deleted file mode 100644 index f8f27b947..000000000 --- a/Demo/HCS12_CodeWarrior_banked/CODE/Events.H +++ /dev/null @@ -1,130 +0,0 @@ -/** ################################################################### -** Filename : Events.H -** Project : RTOSDemo -** Processor : MC9S12DP256BCPV -** Beantype : Events -** Version : Driver 01.01 -** Compiler : Metrowerks HC12 C Compiler -** Date/Time : 14/06/2005, 16:34 -** Abstract : -** This is user's event module. -** Put your event handler code here. -** Settings : -** Contents : -** TickTimer_OnInterrupt - void TickTimer_OnInterrupt(void); -** -** (c) Copyright UNIS, spol. s r.o. 1997-2002 -** UNIS, spol. s r.o. -** Jundrovska 33 -** 624 00 Brno -** Czech Republic -** http : www.processorexpert.com -** mail : info@processorexpert.com -** ###################################################################*/ - -#ifndef __Events_H -#define __Events_H -/* MODULE Events */ - -#include "PE_Types.h" -#include "PE_Error.h" -#include "PE_Const.h" -#include "IO_Map.h" -#include "PE_Timer.h" - -void TickTimer_OnInterrupt(void); -/* -** =================================================================== -** Event : TickTimer_OnInterrupt (module Events) -** -** From bean : TickTimer [TimerInt] -** Description : -** When a timer interrupt occurs this event is called (only -** when the bean is enabled - "Enable" and the events are -** enabled - "EnableEvent"). -** Parameters : None -** Returns : Nothing -** =================================================================== -*/ - - -void COM0_OnError(void); -/* -** =================================================================== -** Event : COM0_OnError (module Events) -** -** From bean : COM0 [AsynchroSerial] -** Description : -** This event is called when a channel error (not the error -** returned by a given method) occurs. The errors can be -** read using method. -** Parameters : None -** Returns : Nothing -** =================================================================== -*/ - -void COM0_OnRxChar(void); -/* -** =================================================================== -** Event : COM0_OnRxChar (module Events) -** -** From bean : COM0 [AsynchroSerial] -** Description : -** This event is called after a correct character is -** received. This -** Parameters : None -** Returns : Nothing -** =================================================================== -*/ - -void COM0_OnTxChar(void); -/* -** =================================================================== -** Event : COM0_OnTxChar (module Events) -** -** From bean : COM0 [AsynchroSerial] -** Description : -** This event is called after a character is transmitted. -** Parameters : None -** Returns : Nothing -** =================================================================== -*/ - -void COM0_OnFullRxBuf(void); -/* -** =================================================================== -** Event : COM0_OnFullRxBuf (module Events) -** -** From bean : COM0 [AsynchroSerial] -** Description : -** This event is called when the input buffer is full. -** Parameters : None -** Returns : Nothing -** =================================================================== -*/ - -void COM0_OnFreeTxBuf(void); -/* -** =================================================================== -** Event : COM0_OnFreeTxBuf (module Events) -** -** From bean : COM0 [AsynchroSerial] -** Description : -** This event is called after the last character in output -** buffer is transmitted. -** Parameters : None -** Returns : Nothing -** =================================================================== -*/ - -/* END Events */ -#endif /* __Events_H*/ - -/* -** ################################################################### -** -** This file was created by UNIS Processor Expert 03.33 for -** the Motorola HCS12 series of microcontrollers. -** -** ################################################################### -*/ diff --git a/Demo/HCS12_CodeWarrior_banked/CODE/IO_Map.C b/Demo/HCS12_CodeWarrior_banked/CODE/IO_Map.C deleted file mode 100644 index 549a0292f..000000000 --- a/Demo/HCS12_CodeWarrior_banked/CODE/IO_Map.C +++ /dev/null @@ -1,559 +0,0 @@ -/** ################################################################### -** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. -** Filename : IO_Map.C -** Project : RTOSDemo -** Processor : MC9S12DP256BCPV -** Beantype : IO_Map -** Version : Driver 01.01 -** Compiler : Metrowerks HC12 C Compiler -** Date/Time : 13/06/2005, 20:14 -** Abstract : -** This bean "IO_Map" implements an IO devices mapping. -** Settings : -** -** Contents : -** No public methods -** -** (c) Copyright UNIS, spol. s r.o. 1997-2002 -** UNIS, spol. s r.o. -** Jundrovska 33 -** 624 00 Brno -** Czech Republic -** http : www.processorexpert.com -** mail : info@processorexpert.com -** ###################################################################*/ -/* Based on CPU DB MC9S12DP256_112, version 2.87.278 */ -#include "PE_types.h" -#include "IO_Map.h" - -volatile ARMCOPSTR _ARMCOP; /* CRG COP Timer Arm/Reset Register */ -volatile ATD0DIENSTR _ATD0DIEN; /* ATD 0 Input Enable Mask Register */ -volatile ATD0STAT0STR _ATD0STAT0; /* ATD 0 Status Register 0 */ -volatile ATD0STAT1STR _ATD0STAT1; /* ATD 0 Status Register 1 */ -volatile ATD1DIENSTR _ATD1DIEN; /* ATD 1 Input Enable Mask Register */ -volatile ATD1STAT0STR _ATD1STAT0; /* ATD 1 Status Register 0 */ -volatile ATD1STAT1STR _ATD1STAT1; /* ATD 1 Status Register 1 */ -volatile BDMCCRSTR _BDMCCR; /* BDM CCR Holding Register */ -volatile BDMINRSTR _BDMINR; /* BDM Internal Register Position Register */ -volatile BDMSTSSTR _BDMSTS; /* BDM Status Register */ -volatile BKP0HSTR _BKP0H; /* First Address High Byte Breakpoint Register */ -volatile BKP0LSTR _BKP0L; /* First Address Low Byte Breakpoint Register */ -volatile BKP0XSTR _BKP0X; /* First Address Memory Expansion Breakpoint Register */ -volatile BKP1HSTR _BKP1H; /* Data (Second Address) High Byte Breakpoint Register */ -volatile BKP1LSTR _BKP1L; /* Data (Second Address) Low Byte Breakpoint Register */ -volatile BKP1XSTR _BKP1X; /* Second Address Memory Expansion Breakpoint Register */ -volatile BKPCT0STR _BKPCT0; /* Breakpoint Control Register 0 */ -volatile BKPCT1STR _BKPCT1; /* Breakpoint Control Register 1 */ -volatile CAN0BTR0STR _CAN0BTR0; /* MSCAN 0 Bus Timing Register 0 */ -volatile CAN0BTR1STR _CAN0BTR1; /* MSCAN 0 Bus Timing Register 1 */ -volatile CAN0CTL0STR _CAN0CTL0; /* MSCAN 0 Control 0 Register */ -volatile CAN0CTL1STR _CAN0CTL1; /* MSCAN 0 Control 1 Register */ -volatile CAN0IDACSTR _CAN0IDAC; /* MSCAN 0 Identifier Acceptance Control Register */ -volatile CAN0IDAR0STR _CAN0IDAR0; /* MSCAN 0 Identifier Acceptance Register 0 */ -volatile CAN0IDAR1STR _CAN0IDAR1; /* MSCAN 0 Identifier Acceptance Register 1 */ -volatile CAN0IDAR2STR _CAN0IDAR2; /* MSCAN 0 Identifier Acceptance Register 2 */ -volatile CAN0IDAR3STR _CAN0IDAR3; /* MSCAN 0 Identifier Acceptance Register 3 */ -volatile CAN0IDAR4STR _CAN0IDAR4; /* MSCAN 0 Identifier Acceptance Register 4 */ -volatile CAN0IDAR5STR _CAN0IDAR5; /* MSCAN 0 Identifier Acceptance Register 5 */ -volatile CAN0IDAR6STR _CAN0IDAR6; /* MSCAN 0 Identifier Acceptance Register 6 */ -volatile CAN0IDAR7STR _CAN0IDAR7; /* MSCAN 0 Identifier Acceptance Register 7 */ -volatile CAN0IDMR0STR _CAN0IDMR0; /* MSCAN 0 Identifier Mask Register 0 */ -volatile CAN0IDMR1STR _CAN0IDMR1; /* MSCAN 0 Identifier Mask Register 1 */ -volatile CAN0IDMR2STR _CAN0IDMR2; /* MSCAN 0 Identifier Mask Register 2 */ -volatile CAN0IDMR3STR _CAN0IDMR3; /* MSCAN 0 Identifier Mask Register 3 */ -volatile CAN0IDMR4STR _CAN0IDMR4; /* MSCAN 0 Identifier Mask Register 4 */ -volatile CAN0IDMR5STR _CAN0IDMR5; /* MSCAN 0 Identifier Mask Register 5 */ -volatile CAN0IDMR6STR _CAN0IDMR6; /* MSCAN 0 Identifier Mask Register 6 */ -volatile CAN0IDMR7STR _CAN0IDMR7; /* MSCAN 0 Identifier Mask Register 7 */ -volatile CAN0RFLGSTR _CAN0RFLG; /* MSCAN 0 Receiver Flag Register */ -volatile CAN0RIERSTR _CAN0RIER; /* MSCAN 0 Receiver Interrupt Enable Register */ -volatile CAN0RXDLRSTR _CAN0RXDLR; /* MSCAN 0 Receive Data Length Register */ -volatile CAN0RXDSR0STR _CAN0RXDSR0; /* MSCAN 0 Receive Data Segment Register 0 */ -volatile CAN0RXDSR1STR _CAN0RXDSR1; /* MSCAN 0 Receive Data Segment Register 1 */ -volatile CAN0RXDSR2STR _CAN0RXDSR2; /* MSCAN 0 Receive Data Segment Register 2 */ -volatile CAN0RXDSR3STR _CAN0RXDSR3; /* MSCAN 0 Receive Data Segment Register 3 */ -volatile CAN0RXDSR4STR _CAN0RXDSR4; /* MSCAN 0 Receive Data Segment Register 4 */ -volatile CAN0RXDSR5STR _CAN0RXDSR5; /* MSCAN 0 Receive Data Segment Register 5 */ -volatile CAN0RXDSR6STR _CAN0RXDSR6; /* MSCAN 0 Receive Data Segment Register 6 */ -volatile CAN0RXDSR7STR _CAN0RXDSR7; /* MSCAN 0 Receive Data Segment Register 7 */ -volatile CAN0RXERRSTR _CAN0RXERR; /* MSCAN 0 Receive Error Counter Register */ -volatile CAN0RXIDR0STR _CAN0RXIDR0; /* MSCAN 0 Receive Identifier Register 0 */ -volatile CAN0RXIDR1STR _CAN0RXIDR1; /* MSCAN 0 Receive Identifier Register 1 */ -volatile CAN0RXIDR2STR _CAN0RXIDR2; /* MSCAN 0 Receive Identifier Register 2 */ -volatile CAN0RXIDR3STR _CAN0RXIDR3; /* MSCAN 0 Receive Identifier Register 3 */ -volatile CAN0TAAKSTR _CAN0TAAK; /* MSCAN 0 Transmitter Message Abort Control */ -volatile CAN0TARQSTR _CAN0TARQ; /* MSCAN 0 Transmitter Message Abort Request */ -volatile CAN0TBSELSTR _CAN0TBSEL; /* MSCAN 0 Transmit Buffer Selection */ -volatile CAN0TFLGSTR _CAN0TFLG; /* MSCAN 0 Transmitter Flag Register */ -volatile CAN0TIERSTR _CAN0TIER; /* MSCAN 0 Transmitter Interrupt Enable Register */ -volatile CAN0TXDLRSTR _CAN0TXDLR; /* MSCAN 0 Transmit Data Length Register */ -volatile CAN0TXDSR0STR _CAN0TXDSR0; /* MSCAN 0 Transmit Data Segment Register 0 */ -volatile CAN0TXDSR1STR _CAN0TXDSR1; /* MSCAN 0 Transmit Data Segment Register 1 */ -volatile CAN0TXDSR2STR _CAN0TXDSR2; /* MSCAN 0 Transmit Data Segment Register 2 */ -volatile CAN0TXDSR3STR _CAN0TXDSR3; /* MSCAN 0 Transmit Data Segment Register 3 */ -volatile CAN0TXDSR4STR _CAN0TXDSR4; /* MSCAN 0 Transmit Data Segment Register 4 */ -volatile CAN0TXDSR5STR _CAN0TXDSR5; /* MSCAN 0 Transmit Data Segment Register 5 */ -volatile CAN0TXDSR6STR _CAN0TXDSR6; /* MSCAN 0 Transmit Data Segment Register 6 */ -volatile CAN0TXDSR7STR _CAN0TXDSR7; /* MSCAN 0 Transmit Data Segment Register 7 */ -volatile CAN0TXERRSTR _CAN0TXERR; /* MSCAN 0 Transmit Error Counter Register */ -volatile CAN0TXIDR0STR _CAN0TXIDR0; /* MSCAN 0 Transmit Identifier Register 0 */ -volatile CAN0TXIDR1STR _CAN0TXIDR1; /* MSCAN 0 Transmit Identifier Register 1 */ -volatile CAN0TXIDR2STR _CAN0TXIDR2; /* MSCAN 0 Transmit Identifier Register 2 */ -volatile CAN0TXIDR3STR _CAN0TXIDR3; /* MSCAN 0 Transmit Identifier Register 3 */ -volatile CAN0TXTBPRSTR _CAN0TXTBPR; /* MSCAN 0 Transmit Buffer Priority */ -volatile CAN1BTR0STR _CAN1BTR0; /* MSCAN 1 Bus Timing Register 0 */ -volatile CAN1BTR1STR _CAN1BTR1; /* MSCAN 1 Bus Timing Register 1 */ -volatile CAN1CTL0STR _CAN1CTL0; /* MSCAN 1 Control 0 Register */ -volatile CAN1CTL1STR _CAN1CTL1; /* MSCAN 1 Control 1 Register */ -volatile CAN1IDACSTR _CAN1IDAC; /* MSCAN 1 Identifier Acceptance Control Register */ -volatile CAN1IDAR0STR _CAN1IDAR0; /* MSCAN 1 Identifier Acceptance Register 0 */ -volatile CAN1IDAR1STR _CAN1IDAR1; /* MSCAN 1 Identifier Acceptance Register 1 */ -volatile CAN1IDAR2STR _CAN1IDAR2; /* MSCAN 1 Identifier Acceptance Register 2 */ -volatile CAN1IDAR3STR _CAN1IDAR3; /* MSCAN 1 Identifier Acceptance Register 3 */ -volatile CAN1IDAR4STR _CAN1IDAR4; /* MSCAN 1 Identifier Acceptance Register 4 */ -volatile CAN1IDAR5STR _CAN1IDAR5; /* MSCAN 1 Identifier Acceptance Register 5 */ -volatile CAN1IDAR6STR _CAN1IDAR6; /* MSCAN 1 Identifier Acceptance Register 6 */ -volatile CAN1IDAR7STR _CAN1IDAR7; /* MSCAN 1 Identifier Acceptance Register 7 */ -volatile CAN1IDMR0STR _CAN1IDMR0; /* MSCAN 1 Identifier Mask Register 0 */ -volatile CAN1IDMR1STR _CAN1IDMR1; /* MSCAN 1 Identifier Mask Register 1 */ -volatile CAN1IDMR2STR _CAN1IDMR2; /* MSCAN 1 Identifier Mask Register 2 */ -volatile CAN1IDMR3STR _CAN1IDMR3; /* MSCAN 1 Identifier Mask Register 3 */ -volatile CAN1IDMR4STR _CAN1IDMR4; /* MSCAN 1 Identifier Mask Register 4 */ -volatile CAN1IDMR5STR _CAN1IDMR5; /* MSCAN 1 Identifier Mask Register 5 */ -volatile CAN1IDMR6STR _CAN1IDMR6; /* MSCAN 1 Identifier Mask Register 6 */ -volatile CAN1IDMR7STR _CAN1IDMR7; /* MSCAN 1 Identifier Mask Register 7 */ -volatile CAN1RFLGSTR _CAN1RFLG; /* MSCAN 1 Receiver Flag Register */ -volatile CAN1RIERSTR _CAN1RIER; /* MSCAN 1 Receiver Interrupt Enable Register */ -volatile CAN1RXDLRSTR _CAN1RXDLR; /* MSCAN 1 Receive Data Length Register */ -volatile CAN1RXDSR0STR _CAN1RXDSR0; /* MSCAN 1 Receive Data Segment Register 0 */ -volatile CAN1RXDSR1STR _CAN1RXDSR1; /* MSCAN 1 Receive Data Segment Register 1 */ -volatile CAN1RXDSR2STR _CAN1RXDSR2; /* MSCAN 1 Receive Data Segment Register 2 */ -volatile CAN1RXDSR3STR _CAN1RXDSR3; /* MSCAN 1 Receive Data Segment Register 3 */ -volatile CAN1RXDSR4STR _CAN1RXDSR4; /* MSCAN 1 Receive Data Segment Register 4 */ -volatile CAN1RXDSR5STR _CAN1RXDSR5; /* MSCAN 1 Receive Data Segment Register 5 */ -volatile CAN1RXDSR6STR _CAN1RXDSR6; /* MSCAN 1 Receive Data Segment Register 6 */ -volatile CAN1RXDSR7STR _CAN1RXDSR7; /* MSCAN 1 Receive Data Segment Register 7 */ -volatile CAN1RXERRSTR _CAN1RXERR; /* MSCAN 1 Receive Error Counter Register */ -volatile CAN1RXIDR0STR _CAN1RXIDR0; /* MSCAN 1 Receive Identifier Register 0 */ -volatile CAN1RXIDR1STR _CAN1RXIDR1; /* MSCAN 1 Receive Identifier Register 1 */ -volatile CAN1RXIDR2STR _CAN1RXIDR2; /* MSCAN 1 Receive Identifier Register 2 */ -volatile CAN1RXIDR3STR _CAN1RXIDR3; /* MSCAN 1 Receive Identifier Register 3 */ -volatile CAN1TAAKSTR _CAN1TAAK; /* MSCAN 1 Transmitter Message Abort Control */ -volatile CAN1TARQSTR _CAN1TARQ; /* MSCAN 1 Transmitter Message Abort Request */ -volatile CAN1TBSELSTR _CAN1TBSEL; /* MSCAN 1 Transmit Buffer Selection */ -volatile CAN1TFLGSTR _CAN1TFLG; /* MSCAN 1 Transmitter Flag Register */ -volatile CAN1TIERSTR _CAN1TIER; /* MSCAN 1 Transmitter Interrupt Enable Register */ -volatile CAN1TXDLRSTR _CAN1TXDLR; /* MSCAN 1 Transmit Data Length Register */ -volatile CAN1TXDSR0STR _CAN1TXDSR0; /* MSCAN 1 Transmit Data Segment Register 0 */ -volatile CAN1TXDSR1STR _CAN1TXDSR1; /* MSCAN 1 Transmit Data Segment Register 1 */ -volatile CAN1TXDSR2STR _CAN1TXDSR2; /* MSCAN 1 Transmit Data Segment Register 2 */ -volatile CAN1TXDSR3STR _CAN1TXDSR3; /* MSCAN 1 Transmit Data Segment Register 3 */ -volatile CAN1TXDSR4STR _CAN1TXDSR4; /* MSCAN 1 Transmit Data Segment Register 4 */ -volatile CAN1TXDSR5STR _CAN1TXDSR5; /* MSCAN 1 Transmit Data Segment Register 5 */ -volatile CAN1TXDSR6STR _CAN1TXDSR6; /* MSCAN 1 Transmit Data Segment Register 6 */ -volatile CAN1TXDSR7STR _CAN1TXDSR7; /* MSCAN 1 Transmit Data Segment Register 7 */ -volatile CAN1TXERRSTR _CAN1TXERR; /* MSCAN 1 Transmit Error Counter Register */ -volatile CAN1TXIDR0STR _CAN1TXIDR0; /* MSCAN 1 Transmit Identifier Register 0 */ -volatile CAN1TXIDR1STR _CAN1TXIDR1; /* MSCAN 1 Transmit Identifier Register 1 */ -volatile CAN1TXIDR2STR _CAN1TXIDR2; /* MSCAN 1 Transmit Identifier Register 2 */ -volatile CAN1TXIDR3STR _CAN1TXIDR3; /* MSCAN 1 Transmit Identifier Register 3 */ -volatile CAN1TXTBPRSTR _CAN1TXTBPR; /* MSCAN 1 Transmit Buffer Priority */ -volatile CAN2BTR0STR _CAN2BTR0; /* MSCAN 2 Bus Timing Register 0 */ -volatile CAN2BTR1STR _CAN2BTR1; /* MSCAN 2 Bus Timing Register 1 */ -volatile CAN2CTL0STR _CAN2CTL0; /* MSCAN 2 Control 0 Register */ -volatile CAN2CTL1STR _CAN2CTL1; /* MSCAN 2 Control 1 Register */ -volatile CAN2IDACSTR _CAN2IDAC; /* MSCAN 2 Identifier Acceptance Control Register */ -volatile CAN2IDAR0STR _CAN2IDAR0; /* MSCAN 2 Identifier Acceptance Register 0 */ -volatile CAN2IDAR1STR _CAN2IDAR1; /* MSCAN 2 Identifier Acceptance Register 1 */ -volatile CAN2IDAR2STR _CAN2IDAR2; /* MSCAN 2 Identifier Acceptance Register 2 */ -volatile CAN2IDAR3STR _CAN2IDAR3; /* MSCAN 2 Identifier Acceptance Register 3 */ -volatile CAN2IDAR4STR _CAN2IDAR4; /* MSCAN 2 Identifier Acceptance Register 4 */ -volatile CAN2IDAR5STR _CAN2IDAR5; /* MSCAN 2 Identifier Acceptance Register 5 */ -volatile CAN2IDAR6STR _CAN2IDAR6; /* MSCAN 2 Identifier Acceptance Register 6 */ -volatile CAN2IDAR7STR _CAN2IDAR7; /* MSCAN 2 Identifier Acceptance Register 7 */ -volatile CAN2IDMR0STR _CAN2IDMR0; /* MSCAN 2 Identifier Mask Register 0 */ -volatile CAN2IDMR1STR _CAN2IDMR1; /* MSCAN 2 Identifier Mask Register 1 */ -volatile CAN2IDMR2STR _CAN2IDMR2; /* MSCAN 2 Identifier Mask Register 2 */ -volatile CAN2IDMR3STR _CAN2IDMR3; /* MSCAN 2 Identifier Mask Register 3 */ -volatile CAN2IDMR4STR _CAN2IDMR4; /* MSCAN 2 Identifier Mask Register 4 */ -volatile CAN2IDMR5STR _CAN2IDMR5; /* MSCAN 2 Identifier Mask Register 5 */ -volatile CAN2IDMR6STR _CAN2IDMR6; /* MSCAN 2 Identifier Mask Register 6 */ -volatile CAN2IDMR7STR _CAN2IDMR7; /* MSCAN 2 Identifier Mask Register 7 */ -volatile CAN2RFLGSTR _CAN2RFLG; /* MSCAN 2 Receiver Flag Register */ -volatile CAN2RIERSTR _CAN2RIER; /* MSCAN 2 Receiver Interrupt Enable Register */ -volatile CAN2RXDLRSTR _CAN2RXDLR; /* MSCAN 2 Receive Data Length Register */ -volatile CAN2RXDSR0STR _CAN2RXDSR0; /* MSCAN 2 Receive Data Segment Register 0 */ -volatile CAN2RXDSR1STR _CAN2RXDSR1; /* MSCAN 2 Receive Data Segment Register 1 */ -volatile CAN2RXDSR2STR _CAN2RXDSR2; /* MSCAN 2 Receive Data Segment Register 2 */ -volatile CAN2RXDSR3STR _CAN2RXDSR3; /* MSCAN 2 Receive Data Segment Register 3 */ -volatile CAN2RXDSR4STR _CAN2RXDSR4; /* MSCAN 2 Receive Data Segment Register 4 */ -volatile CAN2RXDSR5STR _CAN2RXDSR5; /* MSCAN 2 Receive Data Segment Register 5 */ -volatile CAN2RXDSR6STR _CAN2RXDSR6; /* MSCAN 2 Receive Data Segment Register 6 */ -volatile CAN2RXDSR7STR _CAN2RXDSR7; /* MSCAN 2 Receive Data Segment Register 7 */ -volatile CAN2RXERRSTR _CAN2RXERR; /* MSCAN 2 Receive Error Counter Register */ -volatile CAN2RXIDR0STR _CAN2RXIDR0; /* MSCAN 2 Receive Identifier Register 0 */ -volatile CAN2RXIDR1STR _CAN2RXIDR1; /* MSCAN 2 Receive Identifier Register 1 */ -volatile CAN2RXIDR2STR _CAN2RXIDR2; /* MSCAN 2 Receive Identifier Register 2 */ -volatile CAN2RXIDR3STR _CAN2RXIDR3; /* MSCAN 2 Receive Identifier Register 3 */ -volatile CAN2TAAKSTR _CAN2TAAK; /* MSCAN 2 Transmitter Message Abort Control */ -volatile CAN2TARQSTR _CAN2TARQ; /* MSCAN 2 Transmitter Message Abort Request */ -volatile CAN2TBSELSTR _CAN2TBSEL; /* MSCAN 2 Transmit Buffer Selection */ -volatile CAN2TFLGSTR _CAN2TFLG; /* MSCAN 2 Transmitter Flag Register */ -volatile CAN2TIERSTR _CAN2TIER; /* MSCAN 2 Transmitter Interrupt Enable Register */ -volatile CAN2TXDLRSTR _CAN2TXDLR; /* MSCAN 2 Transmit Data Length Register */ -volatile CAN2TXDSR0STR _CAN2TXDSR0; /* MSCAN 2 Transmit Data Segment Register 0 */ -volatile CAN2TXDSR1STR _CAN2TXDSR1; /* MSCAN 2 Transmit Data Segment Register 1 */ -volatile CAN2TXDSR2STR _CAN2TXDSR2; /* MSCAN 2 Transmit Data Segment Register 2 */ -volatile CAN2TXDSR3STR _CAN2TXDSR3; /* MSCAN 2 Transmit Data Segment Register 3 */ -volatile CAN2TXDSR4STR _CAN2TXDSR4; /* MSCAN 2 Transmit Data Segment Register 4 */ -volatile CAN2TXDSR5STR _CAN2TXDSR5; /* MSCAN 2 Transmit Data Segment Register 5 */ -volatile CAN2TXDSR6STR _CAN2TXDSR6; /* MSCAN 2 Transmit Data Segment Register 6 */ -volatile CAN2TXDSR7STR _CAN2TXDSR7; /* MSCAN 2 Transmit Data Segment Register 7 */ -volatile CAN2TXERRSTR _CAN2TXERR; /* MSCAN 2 Transmit Error Counter Register */ -volatile CAN2TXIDR0STR _CAN2TXIDR0; /* MSCAN 2 Transmit Identifier Register 0 */ -volatile CAN2TXIDR1STR _CAN2TXIDR1; /* MSCAN 2 Transmit Identifier Register 1 */ -volatile CAN2TXIDR2STR _CAN2TXIDR2; /* MSCAN 2 Transmit Identifier Register 2 */ -volatile CAN2TXIDR3STR _CAN2TXIDR3; /* MSCAN 2 Transmit Identifier Register 3 */ -volatile CAN2TXTBPRSTR _CAN2TXTBPR; /* MSCAN 2 Transmit Buffer Priority */ -volatile CAN3BTR0STR _CAN3BTR0; /* MSCAN 3 Bus Timing Register 0 */ -volatile CAN3BTR1STR _CAN3BTR1; /* MSCAN 3 Bus Timing Register 1 */ -volatile CAN3CTL0STR _CAN3CTL0; /* MSCAN 3 Control 0 Register */ -volatile CAN3CTL1STR _CAN3CTL1; /* MSCAN 3 Control 1 Register */ -volatile CAN3IDACSTR _CAN3IDAC; /* MSCAN 3 Identifier Acceptance Control Register */ -volatile CAN3IDAR0STR _CAN3IDAR0; /* MSCAN 3 Identifier Acceptance Register 0 */ -volatile CAN3IDAR1STR _CAN3IDAR1; /* MSCAN 3 Identifier Acceptance Register 1 */ -volatile CAN3IDAR2STR _CAN3IDAR2; /* MSCAN 3 Identifier Acceptance Register 2 */ -volatile CAN3IDAR3STR _CAN3IDAR3; /* MSCAN 3 Identifier Acceptance Register 3 */ -volatile CAN3IDAR4STR _CAN3IDAR4; /* MSCAN 3 Identifier Acceptance Register 4 */ -volatile CAN3IDAR5STR _CAN3IDAR5; /* MSCAN 3 Identifier Acceptance Register 5 */ -volatile CAN3IDAR6STR _CAN3IDAR6; /* MSCAN 3 Identifier Acceptance Register 6 */ -volatile CAN3IDAR7STR _CAN3IDAR7; /* MSCAN 3 Identifier Acceptance Register 7 */ -volatile CAN3IDMR0STR _CAN3IDMR0; /* MSCAN 3 Identifier Mask Register 0 */ -volatile CAN3IDMR1STR _CAN3IDMR1; /* MSCAN 3 Identifier Mask Register 1 */ -volatile CAN3IDMR2STR _CAN3IDMR2; /* MSCAN 3 Identifier Mask Register 2 */ -volatile CAN3IDMR3STR _CAN3IDMR3; /* MSCAN 3 Identifier Mask Register 3 */ -volatile CAN3IDMR4STR _CAN3IDMR4; /* MSCAN 3 Identifier Mask Register 4 */ -volatile CAN3IDMR5STR _CAN3IDMR5; /* MSCAN 3 Identifier Mask Register 5 */ -volatile CAN3IDMR6STR _CAN3IDMR6; /* MSCAN 3 Identifier Mask Register 6 */ -volatile CAN3IDMR7STR _CAN3IDMR7; /* MSCAN 3 Identifier Mask Register 7 */ -volatile CAN3RFLGSTR _CAN3RFLG; /* MSCAN 3 Receiver Flag Register */ -volatile CAN3RIERSTR _CAN3RIER; /* MSCAN 3 Receiver Interrupt Enable Register */ -volatile CAN3RXDLRSTR _CAN3RXDLR; /* MSCAN 3 Receive Data Length Register */ -volatile CAN3RXDSR0STR _CAN3RXDSR0; /* MSCAN 3 Receive Data Segment Register 0 */ -volatile CAN3RXDSR1STR _CAN3RXDSR1; /* MSCAN 3 Receive Data Segment Register 1 */ -volatile CAN3RXDSR2STR _CAN3RXDSR2; /* MSCAN 3 Receive Data Segment Register 2 */ -volatile CAN3RXDSR3STR _CAN3RXDSR3; /* MSCAN 3 Receive Data Segment Register 3 */ -volatile CAN3RXDSR4STR _CAN3RXDSR4; /* MSCAN 3 Receive Data Segment Register 4 */ -volatile CAN3RXDSR5STR _CAN3RXDSR5; /* MSCAN 3 Receive Data Segment Register 5 */ -volatile CAN3RXDSR6STR _CAN3RXDSR6; /* MSCAN 3 Receive Data Segment Register 6 */ -volatile CAN3RXDSR7STR _CAN3RXDSR7; /* MSCAN 3 Receive Data Segment Register 7 */ -volatile CAN3RXERRSTR _CAN3RXERR; /* MSCAN 3 Receive Error Counter Register */ -volatile CAN3RXIDR0STR _CAN3RXIDR0; /* MSCAN 3 Receive Identifier Register 0 */ -volatile CAN3RXIDR1STR _CAN3RXIDR1; /* MSCAN 3 Receive Identifier Register 1 */ -volatile CAN3RXIDR2STR _CAN3RXIDR2; /* MSCAN 3 Receive Identifier Register 2 */ -volatile CAN3RXIDR3STR _CAN3RXIDR3; /* MSCAN 3 Receive Identifier Register 3 */ -volatile CAN3TAAKSTR _CAN3TAAK; /* MSCAN 3 Transmitter Message Abort Control */ -volatile CAN3TARQSTR _CAN3TARQ; /* MSCAN 3 Transmitter Message Abort Request */ -volatile CAN3TBSELSTR _CAN3TBSEL; /* MSCAN 3 Transmit Buffer Selection */ -volatile CAN3TFLGSTR _CAN3TFLG; /* MSCAN 3 Transmitter Flag Register */ -volatile CAN3TIERSTR _CAN3TIER; /* MSCAN 3 Transmitter Interrupt Enable Register */ -volatile CAN3TXDLRSTR _CAN3TXDLR; /* MSCAN 3 Transmit Data Length Register */ -volatile CAN3TXDSR0STR _CAN3TXDSR0; /* MSCAN 3 Transmit Data Segment Register 0 */ -volatile CAN3TXDSR1STR _CAN3TXDSR1; /* MSCAN 3 Transmit Data Segment Register 1 */ -volatile CAN3TXDSR2STR _CAN3TXDSR2; /* MSCAN 3 Transmit Data Segment Register 2 */ -volatile CAN3TXDSR3STR _CAN3TXDSR3; /* MSCAN 3 Transmit Data Segment Register 3 */ -volatile CAN3TXDSR4STR _CAN3TXDSR4; /* MSCAN 3 Transmit Data Segment Register 4 */ -volatile CAN3TXDSR5STR _CAN3TXDSR5; /* MSCAN 3 Transmit Data Segment Register 5 */ -volatile CAN3TXDSR6STR _CAN3TXDSR6; /* MSCAN 3 Transmit Data Segment Register 6 */ -volatile CAN3TXDSR7STR _CAN3TXDSR7; /* MSCAN 3 Transmit Data Segment Register 7 */ -volatile CAN3TXERRSTR _CAN3TXERR; /* MSCAN 3 Transmit Error Counter Register */ -volatile CAN3TXIDR0STR _CAN3TXIDR0; /* MSCAN 3 Transmit Identifier Register 0 */ -volatile CAN3TXIDR1STR _CAN3TXIDR1; /* MSCAN 3 Transmit Identifier Register 1 */ -volatile CAN3TXIDR2STR _CAN3TXIDR2; /* MSCAN 3 Transmit Identifier Register 2 */ -volatile CAN3TXIDR3STR _CAN3TXIDR3; /* MSCAN 3 Transmit Identifier Register 3 */ -volatile CAN3TXTBPRSTR _CAN3TXTBPR; /* MSCAN 3 Transmit Buffer Priority */ -volatile CAN4BTR0STR _CAN4BTR0; /* MSCAN4 Bus Timing Register 0 */ -volatile CAN4BTR1STR _CAN4BTR1; /* MSCAN4 Bus Timing Register 1 */ -volatile CAN4CTL0STR _CAN4CTL0; /* MSCAN4 Control 0 Register */ -volatile CAN4CTL1STR _CAN4CTL1; /* MSCAN4 Control 1 Register */ -volatile CAN4IDACSTR _CAN4IDAC; /* MSCAN4 Identifier Acceptance Control Register */ -volatile CAN4IDAR0STR _CAN4IDAR0; /* MSCAN4 Identifier Acceptance Register 0 */ -volatile CAN4IDAR1STR _CAN4IDAR1; /* MSCAN4 Identifier Acceptance Register 1 */ -volatile CAN4IDAR2STR _CAN4IDAR2; /* MSCAN4 Identifier Acceptance Register 2 */ -volatile CAN4IDAR3STR _CAN4IDAR3; /* MSCAN4 Identifier Acceptance Register 3 */ -volatile CAN4IDAR4STR _CAN4IDAR4; /* MSCAN4 Identifier Acceptance Register 4 */ -volatile CAN4IDAR5STR _CAN4IDAR5; /* MSCAN4 Identifier Acceptance Register 5 */ -volatile CAN4IDAR6STR _CAN4IDAR6; /* MSCAN4 Identifier Acceptance Register 6 */ -volatile CAN4IDAR7STR _CAN4IDAR7; /* MSCAN4 Identifier Acceptance Register 7 */ -volatile CAN4IDMR0STR _CAN4IDMR0; /* MSCAN4 Identifier Mask Register 0 */ -volatile CAN4IDMR1STR _CAN4IDMR1; /* MSCAN4 Identifier Mask Register 1 */ -volatile CAN4IDMR2STR _CAN4IDMR2; /* MSCAN4 Identifier Mask Register 2 */ -volatile CAN4IDMR3STR _CAN4IDMR3; /* MSCAN4 Identifier Mask Register 3 */ -volatile CAN4IDMR4STR _CAN4IDMR4; /* MSCAN4 Identifier Mask Register 4 */ -volatile CAN4IDMR5STR _CAN4IDMR5; /* MSCAN4 Identifier Mask Register 5 */ -volatile CAN4IDMR6STR _CAN4IDMR6; /* MSCAN4 Identifier Mask Register 6 */ -volatile CAN4IDMR7STR _CAN4IDMR7; /* MSCAN4 Identifier Mask Register 7 */ -volatile CAN4RFLGSTR _CAN4RFLG; /* MSCAN4 Receiver Flag Register */ -volatile CAN4RIERSTR _CAN4RIER; /* MSCAN4 Receiver Interrupt Enable Register */ -volatile CAN4RXDLRSTR _CAN4RXDLR; /* MSCAN4 Receive Data Length Register */ -volatile CAN4RXDSR0STR _CAN4RXDSR0; /* MSCAN4 Receive Data Segment Register 0 */ -volatile CAN4RXDSR1STR _CAN4RXDSR1; /* MSCAN4 Receive Data Segment Register 1 */ -volatile CAN4RXDSR2STR _CAN4RXDSR2; /* MSCAN4 Receive Data Segment Register 2 */ -volatile CAN4RXDSR3STR _CAN4RXDSR3; /* MSCAN4 Receive Data Segment Register 3 */ -volatile CAN4RXDSR4STR _CAN4RXDSR4; /* MSCAN4 Receive Data Segment Register 4 */ -volatile CAN4RXDSR5STR _CAN4RXDSR5; /* MSCAN4 Receive Data Segment Register 5 */ -volatile CAN4RXDSR6STR _CAN4RXDSR6; /* MSCAN4 Receive Data Segment Register 6 */ -volatile CAN4RXDSR7STR _CAN4RXDSR7; /* MSCAN4 Receive Data Segment Register 7 */ -volatile CAN4RXERRSTR _CAN4RXERR; /* MSCAN4 Receive Error Counter Register */ -volatile CAN4RXIDR0STR _CAN4RXIDR0; /* MSCAN4 Receive Identifier Register 0 */ -volatile CAN4RXIDR1STR _CAN4RXIDR1; /* MSCAN4 Receive Identifier Register 1 */ -volatile CAN4RXIDR2STR _CAN4RXIDR2; /* MSCAN4 Receive Identifier Register 2 */ -volatile CAN4RXIDR3STR _CAN4RXIDR3; /* MSCAN4 Receive Identifier Register 3 */ -volatile CAN4TAAKSTR _CAN4TAAK; /* MSCAN4 Transmitter Message Abort Control */ -volatile CAN4TARQSTR _CAN4TARQ; /* MSCAN 4 Transmitter Message Abort Request */ -volatile CAN4TBSELSTR _CAN4TBSEL; /* MSCAN4 Transmit Buffer Selection */ -volatile CAN4TFLGSTR _CAN4TFLG; /* MSCAN4 Transmitter Flag Register */ -volatile CAN4TIERSTR _CAN4TIER; /* MSCAN4 Transmitter Interrupt Enable Register */ -volatile CAN4TXDLRSTR _CAN4TXDLR; /* MSCAN4 Transmit Data Length Register */ -volatile CAN4TXDSR0STR _CAN4TXDSR0; /* MSCAN4 Transmit Data Segment Register 0 */ -volatile CAN4TXDSR1STR _CAN4TXDSR1; /* MSCAN4 Transmit Data Segment Register 1 */ -volatile CAN4TXDSR2STR _CAN4TXDSR2; /* MSCAN4 Transmit Data Segment Register 2 */ -volatile CAN4TXDSR3STR _CAN4TXDSR3; /* MSCAN4 Transmit Data Segment Register 3 */ -volatile CAN4TXDSR4STR _CAN4TXDSR4; /* MSCAN4 Transmit Data Segment Register 4 */ -volatile CAN4TXDSR5STR _CAN4TXDSR5; /* MSCAN4 Transmit Data Segment Register 5 */ -volatile CAN4TXDSR6STR _CAN4TXDSR6; /* MSCAN4 Transmit Data Segment Register 6 */ -volatile CAN4TXDSR7STR _CAN4TXDSR7; /* MSCAN4 Transmit Data Segment Register 7 */ -volatile CAN4TXERRSTR _CAN4TXERR; /* MSCAN4 Transmit Error Counter Register */ -volatile CAN4TXIDR0STR _CAN4TXIDR0; /* MSCAN4 Transmit Identifier Register 0 */ -volatile CAN4TXIDR1STR _CAN4TXIDR1; /* MSCAN4 Transmit Identifier Register 1 */ -volatile CAN4TXIDR2STR _CAN4TXIDR2; /* MSCAN4 Transmit Identifier Register 2 */ -volatile CAN4TXIDR3STR _CAN4TXIDR3; /* MSCAN4 Transmit Identifier Register 3 */ -volatile CAN4TXTBPRSTR _CAN4TXTBPR; /* MSCAN4 Transmit Transmit Buffer Priority */ -volatile CFORCSTR _CFORC; /* Timer Compare Force Register */ -volatile CLKSELSTR _CLKSEL; /* CRG Clock Select Register */ -volatile COPCTLSTR _COPCTL; /* CRG COP Control Register */ -volatile CRGFLGSTR _CRGFLG; /* CRG Flags Register */ -volatile CRGINTSTR _CRGINT; /* CRG Interrupt Enable Register */ -volatile CTCTLSTR _CTCTL; /* CRG Test Control Register */ -volatile CTFLGSTR _CTFLG; /* CRG Test Flags Register */ -volatile DDRESTR _DDRE; /* Port E Data Direction Register */ -volatile DDRHSTR _DDRH; /* Port H Data Direction Register */ -volatile DDRJSTR _DDRJ; /* Port J Data Direction Register */ -volatile DDRKSTR _DDRK; /* Port K Data Direction Register */ -volatile DDRMSTR _DDRM; /* Port M Data Direction Register */ -volatile DDRPSTR _DDRP; /* Port P Data Direction Register */ -volatile DDRSSTR _DDRS; /* Port S Data Direction Register */ -volatile DDRTSTR _DDRT; /* Port T Data Direction Register */ -volatile DLCBARDSTR _DLCBARD; /* BDLC Analog Round Trip Delay Register */ -volatile DLCBCR1STR _DLCBCR1; /* BDLC Control Register 1 */ -volatile DLCBCR2STR _DLCBCR2; /* BDLC Control Register 2 */ -volatile DLCBDRSTR _DLCBDR; /* BDLC Data Register */ -volatile DLCBRSRSTR _DLCBRSR; /* BDLC Rate Select Register */ -volatile DLCBSVRSTR _DLCBSVR; /* BDLC State Vector Register */ -volatile DLCSCRSTR _DLCSCR; /* BDLC Control Register */ -volatile DLYCTSTR _DLYCT; /* Delay Counter Control Register */ -volatile EBICTLSTR _EBICTL; /* External Bus Interface Control */ -volatile ECLKDIVSTR _ECLKDIV; /* EEPROM Clock Divider Register */ -volatile ECMDSTR _ECMD; /* EEPROM Command Buffer and Register */ -volatile ECNFGSTR _ECNFG; /* EEPROM Configuration Register */ -volatile EPROTSTR _EPROT; /* EEPROM Protection Register */ -volatile ESTATSTR _ESTAT; /* EEPROM Status Register */ -volatile FCLKDIVSTR _FCLKDIV; /* Flash Clock Divider Register */ -volatile FCMDSTR _FCMD; /* Flash Command Buffer and Register */ -volatile FCNFGSTR _FCNFG; /* Flash Configuration Register */ -volatile FORBYPSTR _FORBYP; /* Crg force and bypass test register */ -volatile FPROTSTR _FPROT; /* Flash Protection Register */ -volatile FSECSTR _FSEC; /* Flash Security Register */ -volatile FSTATSTR _FSTAT; /* Flash Status Register */ -volatile HPRIOSTR _HPRIO; /* Highest Priority I Interrupt */ -volatile IBADSTR _IBAD; /* IIC Address Register */ -volatile IBCRSTR _IBCR; /* IIC Control Register */ -volatile IBDRSTR _IBDR; /* IIC Data I/O Register */ -volatile IBFDSTR _IBFD; /* IIC Frequency Divider Register */ -volatile IBSRSTR _IBSR; /* IIC Status Register */ -volatile ICOVWSTR _ICOVW; /* Input Control Overwrite Register */ -volatile ICPARSTR _ICPAR; /* Input Control Pulse Accumulator Register */ -volatile ICSYSSTR _ICSYS; /* Input Control System Control Register */ -volatile INITEESTR _INITEE; /* Initialization of Internal EEPROM Position Register */ -volatile INITRGSTR _INITRG; /* Initialization of Internal Register Position Register */ -volatile INITRMSTR _INITRM; /* Initialization of Internal RAM Position Register */ -volatile INTCRSTR _INTCR; /* Interrupt Control Register */ -volatile ITCRSTR _ITCR; /* Interrupt Test Control Register */ -volatile ITESTSTR _ITEST; /* Interrupt Test Register */ -volatile MCCTLSTR _MCCTL; /* Modulus Down Counter underflow */ -volatile MCFLGSTR _MCFLG; /* 16-Bit Modulus Down Counter Flag Register */ -volatile MEMSIZ0STR _MEMSIZ0; /* Memory Size Register Zero */ -volatile MEMSIZ1STR _MEMSIZ1; /* Memory Size Register One */ -volatile MISCSTR _MISC; /* Miscellaneous Mapping Control Register */ -volatile MODESTR _MODE; /* Mode Register */ -volatile MODRRSTR _MODRR; /* Module Routing Register */ -volatile MTST0STR _MTST0; /* MTST0 */ -volatile MTST1STR _MTST1; /* MTST1 */ -volatile OC7DSTR _OC7D; /* Output Compare 7 Data Register */ -volatile OC7MSTR _OC7M; /* Output Compare 7 Mask Register */ -volatile PACTLSTR _PACTL; /* 16-Bit Pulse Accumulator A Control Register */ -volatile PAFLGSTR _PAFLG; /* Pulse Accumulator A Flag Register */ -volatile PARTIDHSTR _PARTIDH; /* Part ID Register High */ -volatile PARTIDLSTR _PARTIDL; /* Part ID Register Low */ -volatile PBCTLSTR _PBCTL; /* 16-Bit Pulse Accumulator B Control Register */ -volatile PBFLGSTR _PBFLG; /* Pulse Accumulator B Flag Register */ -volatile PEARSTR _PEAR; /* Port E Assignment Register */ -volatile PERHSTR _PERH; /* Port H Pull Device Enable Register */ -volatile PERJSTR _PERJ; /* Port J Pull Device Enable Register */ -volatile PERMSTR _PERM; /* Port M Pull Device Enable Register */ -volatile PERPSTR _PERP; /* Port P Pull Device Enable Register */ -volatile PERSSTR _PERS; /* Port S Pull Device Enable Register */ -volatile PERTSTR _PERT; /* Port T Pull Device Enable Register */ -volatile PIEHSTR _PIEH; /* Port H Interrupt Enable Register */ -volatile PIEJSTR _PIEJ; /* Port J Interrupt Enable Register */ -volatile PIEPSTR _PIEP; /* Port P Interrupt Enable Register */ -volatile PIFHSTR _PIFH; /* Port H Interrupt Flag Register */ -volatile PIFJSTR _PIFJ; /* Port J Interrupt Flag Register */ -volatile PIFPSTR _PIFP; /* Port P Interrupt Flag Register */ -volatile PLLCTLSTR _PLLCTL; /* CRG PLL Control Register */ -volatile PORTAD0STR _PORTAD0; /* Port AD0 Register */ -volatile PORTAD1STR _PORTAD1; /* Port AD1 Register */ -volatile PORTESTR _PORTE; /* Port E Register */ -volatile PORTKSTR _PORTK; /* Port K Data Register */ -volatile PPAGESTR _PPAGE; /* Page Index Register */ -volatile PPSHSTR _PPSH; /* Port H Polarity Select Register */ -volatile PPSJSTR _PPSJ; /* PortJP Polarity Select Register */ -volatile PPSMSTR _PPSM; /* Port M Polarity Select Register */ -volatile PPSPSTR _PPSP; /* Port P Polarity Select Register */ -volatile PPSSSTR _PPSS; /* Port S Polarity Select Register */ -volatile PPSTSTR _PPST; /* Port T Polarity Select Register */ -volatile PTHSTR _PTH; /* Port H I/O Register */ -volatile PTIHSTR _PTIH; /* Port H Input Register */ -volatile PTIJSTR _PTIJ; /* Port J Input Register */ -volatile PTIMSTR _PTIM; /* Port M Input */ -volatile PTIPSTR _PTIP; /* Port P Input */ -volatile PTISSTR _PTIS; /* Port S Input */ -volatile PTITSTR _PTIT; /* Port T Input */ -volatile PTJSTR _PTJ; /* Port J I/O Register */ -volatile PTMSTR _PTM; /* Port M I/O Register */ -volatile PTPSTR _PTP; /* Port P I/O Register */ -volatile PTSSTR _PTS; /* Port S I/O Register */ -volatile PTTSTR _PTT; /* Port T I/O Register */ -volatile PUCRSTR _PUCR; /* Pull-Up Control Register */ -volatile PWMCAESTR _PWMCAE; /* PWM Center Align Enable Register */ -volatile PWMCLKSTR _PWMCLK; /* PWM Clock Select Register */ -volatile PWMCTLSTR _PWMCTL; /* PWM Control Register */ -volatile PWMESTR _PWME; /* PWM Enable Register */ -volatile PWMPOLSTR _PWMPOL; /* PWM Polarity Register */ -volatile PWMPRCLKSTR _PWMPRCLK; /* PWM Prescale Clock Select Register */ -volatile PWMSCLASTR _PWMSCLA; /* PWM Scale A Register */ -volatile PWMSCLBSTR _PWMSCLB; /* PWM Scale B Register */ -volatile PWMSDNSTR _PWMSDN; /* PWM Shutdown Register */ -volatile RDRHSTR _RDRH; /* Port H Reduced Drive Register */ -volatile RDRIVSTR _RDRIV; /* Reduced Drive of I/O Lines */ -volatile RDRJSTR _RDRJ; /* Port J Reduced Drive Register */ -volatile RDRMSTR _RDRM; /* Port M Reduced Drive Register */ -volatile RDRPSTR _RDRP; /* Port P Reduced Drive Register */ -volatile RDRSSTR _RDRS; /* Port S Reduced Drive Register */ -volatile RDRTSTR _RDRT; /* Port T Reduced Drive Register */ -volatile REFDVSTR _REFDV; /* CRG Reference Divider Register */ -volatile RTICTLSTR _RTICTL; /* CRG RTI Control Register */ -volatile SCI0CR1STR _SCI0CR1; /* SCI 0 Control Register 1 */ -volatile SCI0CR2STR _SCI0CR2; /* SCI 0 Control Register 2 */ -volatile SCI0DRHSTR _SCI0DRH; /* SCI 0 Data Register High */ -volatile SCI0DRLSTR _SCI0DRL; /* SCI 0 Data Register Low */ -volatile SCI0SR1STR _SCI0SR1; /* SCI 0 Status Register 1 */ -volatile SCI0SR2STR _SCI0SR2; /* SCI 0 Status Register 2 */ -volatile SCI1CR1STR _SCI1CR1; /* SCI 1 Control Register 1 */ -volatile SCI1CR2STR _SCI1CR2; /* SCI 1 Control Register 2 */ -volatile SCI1DRHSTR _SCI1DRH; /* SCI 1 Data Register High */ -volatile SCI1DRLSTR _SCI1DRL; /* SCI 1 Data Register Low */ -volatile SCI1SR1STR _SCI1SR1; /* SCI 1 Status Register 1 */ -volatile SCI1SR2STR _SCI1SR2; /* SCI 1 Status Register 2 */ -volatile SPI0BRSTR _SPI0BR; /* SPI 0 Baud Rate Register */ -volatile SPI0CR1STR _SPI0CR1; /* SPI 0 Control Register */ -volatile SPI0CR2STR _SPI0CR2; /* SPI 0 Control Register 2 */ -volatile SPI0DRSTR _SPI0DR; /* SPI 0 Data Register */ -volatile SPI0SRSTR _SPI0SR; /* SPI 0 Status Register */ -volatile SPI1BRSTR _SPI1BR; /* SPI 1 Baud Rate Register */ -volatile SPI1CR1STR _SPI1CR1; /* SPI 1 Control Register */ -volatile SPI1CR2STR _SPI1CR2; /* SPI 1 Control Register 2 */ -volatile SPI1DRSTR _SPI1DR; /* SPI 1 Data Register */ -volatile SPI1SRSTR _SPI1SR; /* SPI 1 Status Register */ -volatile SPI2BRSTR _SPI2BR; /* SPI 2 Baud Rate Register */ -volatile SPI2CR1STR _SPI2CR1; /* SPI 2 Control Register */ -volatile SPI2CR2STR _SPI2CR2; /* SPI 2 Control Register 2 */ -volatile SPI2DRSTR _SPI2DR; /* SPI 2 Data Register */ -volatile SPI2SRSTR _SPI2SR; /* SPI 2 Status Register */ -volatile SYNRSTR _SYNR; /* CRG Synthesizer Register */ -volatile TCTL1STR _TCTL1; /* Timer Control Registers 1 */ -volatile TCTL2STR _TCTL2; /* Timer Control Registers 2 */ -volatile TCTL3STR _TCTL3; /* Timer Control Register 3 */ -volatile TCTL4STR _TCTL4; /* Timer Control Register 4 */ -volatile TFLG1STR _TFLG1; /* Main Timer Interrupt Flag 1 */ -volatile TFLG2STR _TFLG2; /* Main Timer Interrupt Flag 2 */ -volatile TIESTR _TIE; /* Timer Interrupt Enable Register */ -volatile TIMTSTSTR _TIMTST; /* Timer Test Register */ -volatile TIOSSTR _TIOS; /* Timer Input Capture/Output Compare Select */ -volatile TSCR1STR _TSCR1; /* Timer System Control Register1 */ -volatile TSCR2STR _TSCR2; /* Timer System Control Register 2 */ -volatile TTOVSTR _TTOV; /* Timer Toggle On Overflow Register */ -volatile WOMMSTR _WOMM; /* Port M Wired-Or Mode Register */ -volatile WOMSSTR _WOMS; /* Port S Wired-Or Mode Register */ -volatile ATD0CTL23STR _ATD0CTL23; /* ATD 0 Control Register 23 */ -volatile ATD0CTL45STR _ATD0CTL45; /* ATD 0 Control Register 45 */ -volatile ATD0DR0STR _ATD0DR0; /* ATD 0 Conversion Result Register 0 */ -volatile ATD0DR1STR _ATD0DR1; /* ATD 0 Conversion Result Register 1 */ -volatile ATD0DR2STR _ATD0DR2; /* ATD 0 Conversion Result Register 2 */ -volatile ATD0DR3STR _ATD0DR3; /* ATD 0 Conversion Result Register 3 */ -volatile ATD0DR4STR _ATD0DR4; /* ATD 0 Conversion Result Register 4 */ -volatile ATD0DR5STR _ATD0DR5; /* ATD 0 Conversion Result Register 5 */ -volatile ATD0DR6STR _ATD0DR6; /* ATD 0 Conversion Result Register 6 */ -volatile ATD0DR7STR _ATD0DR7; /* ATD 0 Conversion Result Register 7 */ -volatile ATD1CTL23STR _ATD1CTL23; /* ATD 1 Control Register 23 */ -volatile ATD1CTL45STR _ATD1CTL45; /* ATD 1 Control Register 45 */ -volatile ATD1DR0STR _ATD1DR0; /* ATD 1 Conversion Result Register 0 */ -volatile ATD1DR1STR _ATD1DR1; /* ATD 1 Conversion Result Register 1 */ -volatile ATD1DR2STR _ATD1DR2; /* ATD 1 Conversion Result Register 2 */ -volatile ATD1DR3STR _ATD1DR3; /* ATD 1 Conversion Result Register 3 */ -volatile ATD1DR4STR _ATD1DR4; /* ATD 1 Conversion Result Register 4 */ -volatile ATD1DR5STR _ATD1DR5; /* ATD 1 Conversion Result Register 5 */ -volatile ATD1DR6STR _ATD1DR6; /* ATD 1 Conversion Result Register 6 */ -volatile ATD1DR7STR _ATD1DR7; /* ATD 1 Conversion Result Register 7 */ -volatile DDRABSTR _DDRAB; /* Port AB Data Direction Register */ -volatile MCCNTSTR _MCCNT; /* Modulus Down-Counter Count Register */ -volatile PA10HSTR _PA10H; /* 8-Bit Pulse Accumulators Holding 10 Register */ -volatile PA32HSTR _PA32H; /* 8-Bit Pulse Accumulators Holding 32 Register */ -volatile PACN10STR _PACN10; /* Pulse Accumulators Count 10 Register */ -volatile PACN32STR _PACN32; /* Pulse Accumulators Count 32 Register */ -volatile PORTABSTR _PORTAB; /* Port AB Register */ -volatile PWMCNT01STR _PWMCNT01; /* PWM Channel Counter 01 Register */ -volatile PWMCNT23STR _PWMCNT23; /* PWM Channel Counter 23 Register */ -volatile PWMCNT45STR _PWMCNT45; /* PWM Channel Counter 45 Register */ -volatile PWMCNT67STR _PWMCNT67; /* PWM Channel Counter 67 Register */ -volatile PWMDTY01STR _PWMDTY01; /* PWM Channel Duty 01 Register */ -volatile PWMDTY23STR _PWMDTY23; /* PWM Channel Duty 23 Register */ -volatile PWMDTY45STR _PWMDTY45; /* PWM Channel Duty 45 Register */ -volatile PWMDTY67STR _PWMDTY67; /* PWM Channel Duty 67 Register */ -volatile PWMPER01STR _PWMPER01; /* PWM Channel Period 01 Register */ -volatile PWMPER23STR _PWMPER23; /* PWM Channel Period 23 Register */ -volatile PWMPER45STR _PWMPER45; /* PWM Channel Period 45 Register */ -volatile PWMPER67STR _PWMPER67; /* PWM Channel Period 67 Register */ -volatile SCI0BDSTR _SCI0BD; /* SCI 0 Baud Rate Register */ -volatile SCI1BDSTR _SCI1BD; /* SCI 1 Baud Rate Register */ -volatile TC0STR _TC0; /* Timer Input Capture/Output Compare Register 0 */ -volatile TC0HSTR _TC0H; /* Timer Input Capture Holding Registers 0 */ -volatile TC1STR _TC1; /* Timer Input Capture/Output Compare Register 1 */ -volatile TC1HSTR _TC1H; /* Timer Input Capture Holding Registers 1 */ -volatile TC2STR _TC2; /* Timer Input Capture/Output Compare Register 2 */ -volatile TC2HSTR _TC2H; /* Timer Input Capture Holding Registers 2 */ -volatile TC3STR _TC3; /* Timer Input Capture/Output Compare Register 3 */ -volatile TC3HSTR _TC3H; /* Timer Input Capture Holding Registers 3 */ -volatile TC4STR _TC4; /* Timer Input Capture/Output Compare Register 4 */ -volatile TC5STR _TC5; /* Timer Input Capture/Output Compare Register 5 */ -volatile TC6STR _TC6; /* Timer Input Capture/Output Compare Register 6 */ -volatile TC7STR _TC7; /* Timer Input Capture/Output Compare Register 7 */ -volatile TCNTSTR _TCNT; /* Timer Count Register */ -/* -** ################################################################### -** -** This file was created by UNIS Processor Expert 03.33 for -** the Motorola HCS12 series of microcontrollers. -** -** ################################################################### -*/ diff --git a/Demo/HCS12_CodeWarrior_banked/CODE/IO_Map.H b/Demo/HCS12_CodeWarrior_banked/CODE/IO_Map.H deleted file mode 100644 index 678b0b350..000000000 --- a/Demo/HCS12_CodeWarrior_banked/CODE/IO_Map.H +++ /dev/null @@ -1,18408 +0,0 @@ -/** ################################################################### -** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. -** Filename : IO_Map.H -** Project : RTOSDemo -** Processor : MC9S12DP256BCPV -** Beantype : IO_Map -** Version : Driver 01.01 -** Compiler : Metrowerks HC12 C Compiler -** Date/Time : 13/06/2005, 20:14 -** Abstract : -** This bean "IO_Map" implements an IO devices mapping. -** Settings : -** -** Contents : -** No public methods -** -** (c) Copyright UNIS, spol. s r.o. 1997-2002 -** UNIS, spol. s r.o. -** Jundrovska 33 -** 624 00 Brno -** Czech Republic -** http : www.processorexpert.com -** mail : info@processorexpert.com -** ###################################################################*/ - -/* Linker pragmas */ -#pragma LINK_INFO DERIVATIVE "MC9S12DP256B" -#pragma LINK_INFO OSCFREQUENCY "16000000" - - -#define REG_BASE 0x0000 /* Base address for the I/O register block */ - -/* Based on CPU DB MC9S12DP256_112, version 2.87.278 (RegistersPrg V1.027) */ -#ifndef _MC9S12DP256_112_H -#define _MC9S12DP256_112_H - -#include "PE_Types.h" - -#pragma MESSAGE DISABLE C1106 /* WARNING C1106: Non-standard bitfield type */ - -/*********************************************/ -/* */ -/* PE I/O map format */ -/* */ -/*********************************************/ - -/*** PORTAB - Port AB Register; 0x00000000 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** PORTA - Port A Register; 0x00000000 ***/ - union { - byte Byte; - struct { - byte BIT0 :1; /* Port A Bit0, ADDR8, DATA8, DATA0 */ - byte BIT1 :1; /* Port A Bit1, ADDR9, DATA9 DATA1 */ - byte BIT2 :1; /* Port A Bit2, ADDR10, DATA10, DATA2 */ - byte BIT3 :1; /* Port A Bit3, ADDR11, DATA11, DATA3 */ - byte BIT4 :1; /* Port A Bit4, ADDR12, DATA12, DATA4 */ - byte BIT5 :1; /* Port A Bit5, ADDR13, DATA13, DATA5 */ - byte BIT6 :1; /* Port A Bit6, ADDR14, DATA14, DATA6 */ - byte BIT7 :1; /* Port A Bit7, ADDR15, DATA15, DATA7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; - } PORTASTR; - #define PORTA _PORTAB.Overlap_STR.PORTASTR.Byte - #define PORTA_BIT0 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT0 - #define PORTA_BIT1 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT1 - #define PORTA_BIT2 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT2 - #define PORTA_BIT3 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT3 - #define PORTA_BIT4 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT4 - #define PORTA_BIT5 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT5 - #define PORTA_BIT6 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT6 - #define PORTA_BIT7 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT7 - #define PORTA_BIT _PORTAB.Overlap_STR.PORTASTR.MergedBits.grpBIT - - /*** PORTB - Port B Register; 0x00000001 ***/ - union { - byte Byte; - struct { - byte BIT0 :1; /* Port B Bit 0, ADDR0, DATA0 */ - byte BIT1 :1; /* Port B Bit1, ADDR1, DATA1 */ - byte BIT2 :1; /* Port B Bit2, ADDR2, DATA2 */ - byte BIT3 :1; /* Port B Bit3, ADDR3, DATA3 */ - byte BIT4 :1; /* Port B Bit4, ADDR4, DATA4 */ - byte BIT5 :1; /* Port B Bit5, ADDR5, DATA5 */ - byte BIT6 :1; /* Port B Bit6, ADDR6, DATA6 */ - byte BIT7 :1; /* Port B Bit7, ADDR7, DATA7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; - } PORTBSTR; - #define PORTB _PORTAB.Overlap_STR.PORTBSTR.Byte - #define PORTB_BIT0 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT0 - #define PORTB_BIT1 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT1 - #define PORTB_BIT2 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT2 - #define PORTB_BIT3 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT3 - #define PORTB_BIT4 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT4 - #define PORTB_BIT5 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT5 - #define PORTB_BIT6 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT6 - #define PORTB_BIT7 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT7 - #define PORTB_BIT _PORTAB.Overlap_STR.PORTBSTR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word BIT0 :1; /* Port B Bit 0, ADDR0, DATA0 */ - word BIT1 :1; /* Port B Bit1, ADDR1, DATA1 */ - word BIT2 :1; /* Port B Bit2, ADDR2, DATA2 */ - word BIT3 :1; /* Port B Bit3, ADDR3, DATA3 */ - word BIT4 :1; /* Port B Bit4, ADDR4, DATA4 */ - word BIT5 :1; /* Port B Bit5, ADDR5, DATA5 */ - word BIT6 :1; /* Port B Bit6, ADDR6, DATA6 */ - word BIT7 :1; /* Port B Bit7, ADDR7, DATA7 */ - word BIT8 :1; /* Port A Bit0, ADDR8, DATA8, DATA0 */ - word BIT9 :1; /* Port A Bit1, ADDR9, DATA9 DATA1 */ - word BIT10 :1; /* Port A Bit2, ADDR10, DATA10, DATA2 */ - word BIT11 :1; /* Port A Bit3, ADDR11, DATA11, DATA3 */ - word BIT12 :1; /* Port A Bit4, ADDR12, DATA12, DATA4 */ - word BIT13 :1; /* Port A Bit5, ADDR13, DATA13, DATA5 */ - word BIT14 :1; /* Port A Bit6, ADDR14, DATA14, DATA6 */ - word BIT15 :1; /* Port A Bit7, ADDR15, DATA15, DATA7 */ - } Bits; - struct { - word grpBIT :16; - } MergedBits; -} PORTABSTR; -extern volatile PORTABSTR _PORTAB @(REG_BASE + 0x00000000); -#define PORTAB _PORTAB.Word -#define PORTAB_BIT0 _PORTAB.Bits.BIT0 -#define PORTAB_BIT1 _PORTAB.Bits.BIT1 -#define PORTAB_BIT2 _PORTAB.Bits.BIT2 -#define PORTAB_BIT3 _PORTAB.Bits.BIT3 -#define PORTAB_BIT4 _PORTAB.Bits.BIT4 -#define PORTAB_BIT5 _PORTAB.Bits.BIT5 -#define PORTAB_BIT6 _PORTAB.Bits.BIT6 -#define PORTAB_BIT7 _PORTAB.Bits.BIT7 -#define PORTAB_BIT8 _PORTAB.Bits.BIT8 -#define PORTAB_BIT9 _PORTAB.Bits.BIT9 -#define PORTAB_BIT10 _PORTAB.Bits.BIT10 -#define PORTAB_BIT11 _PORTAB.Bits.BIT11 -#define PORTAB_BIT12 _PORTAB.Bits.BIT12 -#define PORTAB_BIT13 _PORTAB.Bits.BIT13 -#define PORTAB_BIT14 _PORTAB.Bits.BIT14 -#define PORTAB_BIT15 _PORTAB.Bits.BIT15 -#define PORTAB_BIT _PORTAB.MergedBits.grpBIT - - -/*** DDRAB - Port AB Data Direction Register; 0x00000002 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** DDRA - Port A Data Direction Register; 0x00000002 ***/ - union { - byte Byte; - struct { - byte BIT0 :1; /* Data Direction Port A Bit 0 */ - byte BIT1 :1; /* Data Direction Port A Bit 1 */ - byte BIT2 :1; /* Data Direction Port A Bit 2 */ - byte BIT3 :1; /* Data Direction Port A Bit 3 */ - byte BIT4 :1; /* Data Direction Port A Bit 4 */ - byte BIT5 :1; /* Data Direction Port A Bit 5 */ - byte BIT6 :1; /* Data Direction Port A Bit 6 */ - byte BIT7 :1; /* Data Direction Port A Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; - } DDRASTR; - #define DDRA _DDRAB.Overlap_STR.DDRASTR.Byte - #define DDRA_BIT0 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT0 - #define DDRA_BIT1 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT1 - #define DDRA_BIT2 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT2 - #define DDRA_BIT3 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT3 - #define DDRA_BIT4 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT4 - #define DDRA_BIT5 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT5 - #define DDRA_BIT6 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT6 - #define DDRA_BIT7 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT7 - #define DDRA_BIT _DDRAB.Overlap_STR.DDRASTR.MergedBits.grpBIT - - /*** DDRB - Port B Data Direction Register; 0x00000003 ***/ - union { - byte Byte; - struct { - byte BIT0 :1; /* Data Direction Port B Bit 0 */ - byte BIT1 :1; /* Data Direction Port B Bit 1 */ - byte BIT2 :1; /* Data Direction Port B Bit 2 */ - byte BIT3 :1; /* Data Direction Port B Bit 3 */ - byte BIT4 :1; /* Data Direction Port B Bit 4 */ - byte BIT5 :1; /* Data Direction Port B Bit 5 */ - byte BIT6 :1; /* Data Direction Port B Bit 6 */ - byte BIT7 :1; /* Data Direction Port B Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; - } DDRBSTR; - #define DDRB _DDRAB.Overlap_STR.DDRBSTR.Byte - #define DDRB_BIT0 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT0 - #define DDRB_BIT1 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT1 - #define DDRB_BIT2 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT2 - #define DDRB_BIT3 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT3 - #define DDRB_BIT4 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT4 - #define DDRB_BIT5 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT5 - #define DDRB_BIT6 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT6 - #define DDRB_BIT7 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT7 - #define DDRB_BIT _DDRAB.Overlap_STR.DDRBSTR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word BIT0 :1; /* Data Direction Port B Bit 0 */ - word BIT1 :1; /* Data Direction Port B Bit 1 */ - word BIT2 :1; /* Data Direction Port B Bit 2 */ - word BIT3 :1; /* Data Direction Port B Bit 3 */ - word BIT4 :1; /* Data Direction Port B Bit 4 */ - word BIT5 :1; /* Data Direction Port B Bit 5 */ - word BIT6 :1; /* Data Direction Port B Bit 6 */ - word BIT7 :1; /* Data Direction Port B Bit 7 */ - word BIT8 :1; /* Data Direction Port A Bit 8 */ - word BIT9 :1; /* Data Direction Port A Bit 9 */ - word BIT10 :1; /* Data Direction Port A Bit 10 */ - word BIT11 :1; /* Data Direction Port A Bit 11 */ - word BIT12 :1; /* Data Direction Port A Bit 12 */ - word BIT13 :1; /* Data Direction Port A Bit 13 */ - word BIT14 :1; /* Data Direction Port A Bit 14 */ - word BIT15 :1; /* Data Direction Port A Bit 15 */ - } Bits; - struct { - word grpBIT :16; - } MergedBits; -} DDRABSTR; -extern volatile DDRABSTR _DDRAB @(REG_BASE + 0x00000002); -#define DDRAB _DDRAB.Word -#define DDRAB_BIT0 _DDRAB.Bits.BIT0 -#define DDRAB_BIT1 _DDRAB.Bits.BIT1 -#define DDRAB_BIT2 _DDRAB.Bits.BIT2 -#define DDRAB_BIT3 _DDRAB.Bits.BIT3 -#define DDRAB_BIT4 _DDRAB.Bits.BIT4 -#define DDRAB_BIT5 _DDRAB.Bits.BIT5 -#define DDRAB_BIT6 _DDRAB.Bits.BIT6 -#define DDRAB_BIT7 _DDRAB.Bits.BIT7 -#define DDRAB_BIT8 _DDRAB.Bits.BIT8 -#define DDRAB_BIT9 _DDRAB.Bits.BIT9 -#define DDRAB_BIT10 _DDRAB.Bits.BIT10 -#define DDRAB_BIT11 _DDRAB.Bits.BIT11 -#define DDRAB_BIT12 _DDRAB.Bits.BIT12 -#define DDRAB_BIT13 _DDRAB.Bits.BIT13 -#define DDRAB_BIT14 _DDRAB.Bits.BIT14 -#define DDRAB_BIT15 _DDRAB.Bits.BIT15 -#define DDRAB_BIT _DDRAB.MergedBits.grpBIT - - -/*** TCNT - Timer Count Register; 0x00000044 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** TCNTHi - Timer Count Register High; 0x00000044 ***/ - union { - byte Byte; - struct { - byte BIT15 :1; /* Timer Count Register Bit 15 */ - byte BIT14 :1; /* Timer Count Register Bit 14 */ - byte BIT13 :1; /* Timer Count Register Bit 13 */ - byte BIT12 :1; /* Timer Count Register Bit 12 */ - byte BIT11 :1; /* Timer Count Register Bit 11 */ - byte BIT10 :1; /* Timer Count Register Bit 10 */ - byte BIT9 :1; /* Timer Count Register Bit 9 */ - byte BIT8 :1; /* Timer Count Register Bit 8 */ - } Bits; - } TCNTHiSTR; - #define TCNTHi _TCNT.Overlap_STR.TCNTHiSTR.Byte - #define TCNTHi_BIT15 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT15 - #define TCNTHi_BIT14 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT14 - #define TCNTHi_BIT13 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT13 - #define TCNTHi_BIT12 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT12 - #define TCNTHi_BIT11 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT11 - #define TCNTHi_BIT10 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT10 - #define TCNTHi_BIT9 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT9 - #define TCNTHi_BIT8 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT8 - - /*** TCNTLo - Timer Count Register Low; 0x00000045 ***/ - union { - byte Byte; - struct { - byte BIT0 :1; /* Timer Count Register Bit 0 */ - byte BIT1 :1; /* Timer Count Register Bit 1 */ - byte BIT2 :1; /* Timer Count Register Bit 2 */ - byte BIT3 :1; /* Timer Count Register Bit 3 */ - byte BIT4 :1; /* Timer Count Bit Register 4 */ - byte BIT5 :1; /* Timer Count Bit Register 5 */ - byte BIT6 :1; /* Timer Count Bit Register 6 */ - byte BIT7 :1; /* Timer Count Bit Register 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; - } TCNTLoSTR; - #define TCNTLo _TCNT.Overlap_STR.TCNTLoSTR.Byte - #define TCNTLo_BIT0 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT0 - #define TCNTLo_BIT1 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT1 - #define TCNTLo_BIT2 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT2 - #define TCNTLo_BIT3 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT3 - #define TCNTLo_BIT4 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT4 - #define TCNTLo_BIT5 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT5 - #define TCNTLo_BIT6 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT6 - #define TCNTLo_BIT7 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT7 - #define TCNTLo_BIT _TCNT.Overlap_STR.TCNTLoSTR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word grpBIT :16; - } MergedBits; -} TCNTSTR; -extern volatile TCNTSTR _TCNT @(REG_BASE + 0x00000044); -#define TCNT _TCNT.Word -#define TCNT_BIT _TCNT.MergedBits.grpBIT - - -/*** TC0 - Timer Input Capture/Output Compare Register 0; 0x00000050 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** TC0Hi - Timer Input Capture/Output Compare Register 0 High; 0x00000050 ***/ - union { - byte Byte; - struct { - byte BIT8 :1; /* Timer Input Capture/Output Compare Register 0 Bit 8 */ - byte BIT9 :1; /* Timer Input Capture/Output Compare Register 0 Bit 9 */ - byte BIT10 :1; /* Timer Input Capture/Output Compare Register 0 Bit 10 */ - byte BIT11 :1; /* Timer Input Capture/Output Compare Register 0 Bit 11 */ - byte BIT12 :1; /* Timer Input Capture/Output Compare Register 0 Bit 12 */ - byte BIT13 :1; /* Timer Input Capture/Output Compare Register 0 Bit 13 */ - byte BIT14 :1; /* Timer Input Capture/Output Compare Register 0 Bit 14 */ - byte BIT15 :1; /* Timer Input Capture/Output Compare Register 0 Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; - } TC0HiSTR; - #define TC0Hi _TC0.Overlap_STR.TC0HiSTR.Byte - #define TC0Hi_BIT8 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT8 - #define TC0Hi_BIT9 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT9 - #define TC0Hi_BIT10 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT10 - #define TC0Hi_BIT11 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT11 - #define TC0Hi_BIT12 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT12 - #define TC0Hi_BIT13 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT13 - #define TC0Hi_BIT14 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT14 - #define TC0Hi_BIT15 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT15 - #define TC0Hi_BIT_8 _TC0.Overlap_STR.TC0HiSTR.MergedBits.grpBIT_8 - #define TC0Hi_BIT TC0Hi_BIT_8 - - /*** TC0Lo - Timer Input Capture/Output Compare Register 0 Low; 0x00000051 ***/ - union { - byte Byte; - struct { - byte BIT0 :1; /* Timer Input Capture/Output Compare Register 0 Bit 0 */ - byte BIT1 :1; /* Timer Input Capture/Output Compare Register 0 Bit 1 */ - byte BIT2 :1; /* Timer Input Capture/Output Compare Register 0 Bit 2 */ - byte BIT3 :1; /* Timer Input Capture/Output Compare Register 0 Bit 3 */ - byte BIT4 :1; /* Timer Input Capture/Output Compare Register 0 Bit 4 */ - byte BIT5 :1; /* Timer Input Capture/Output Compare Register 0 Bit 5 */ - byte BIT6 :1; /* Timer Input Capture/Output Compare Register 0 Bit 6 */ - byte BIT7 :1; /* Timer Input Capture/Output Compare Register 0 Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; - } TC0LoSTR; - #define TC0Lo _TC0.Overlap_STR.TC0LoSTR.Byte - #define TC0Lo_BIT0 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT0 - #define TC0Lo_BIT1 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT1 - #define TC0Lo_BIT2 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT2 - #define TC0Lo_BIT3 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT3 - #define TC0Lo_BIT4 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT4 - #define TC0Lo_BIT5 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT5 - #define TC0Lo_BIT6 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT6 - #define TC0Lo_BIT7 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT7 - #define TC0Lo_BIT _TC0.Overlap_STR.TC0LoSTR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word grpBIT :16; - } MergedBits; -} TC0STR; -extern volatile TC0STR _TC0 @(REG_BASE + 0x00000050); -#define TC0 _TC0.Word -#define TC0_BIT _TC0.MergedBits.grpBIT - - -/*** TC1 - Timer Input Capture/Output Compare Register 1; 0x00000052 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** TC1Hi - Timer Input Capture/Output Compare Register 1 High; 0x00000052 ***/ - union { - byte Byte; - struct { - byte BIT8 :1; /* Timer Input Capture/Output Compare Register 1 Bit 8 */ - byte BIT9 :1; /* Timer Input Capture/Output Compare Register 1 Bit 9 */ - byte BIT10 :1; /* Timer Input Capture/Output Compare Register 1 Bit 10 */ - byte BIT11 :1; /* Timer Input Capture/Output Compare Register 1 Bit 11 */ - byte BIT12 :1; /* Timer Input Capture/Output Compare Register 1 Bit 12 */ - byte BIT13 :1; /* Timer Input Capture/Output Compare Register 1 Bit 13 */ - byte BIT14 :1; /* Timer Input Capture/Output Compare Register 1 Bit 14 */ - byte BIT15 :1; /* Timer Input Capture/Output Compare Register 1 Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; - } TC1HiSTR; - #define TC1Hi _TC1.Overlap_STR.TC1HiSTR.Byte - #define TC1Hi_BIT8 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT8 - #define TC1Hi_BIT9 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT9 - #define TC1Hi_BIT10 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT10 - #define TC1Hi_BIT11 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT11 - #define TC1Hi_BIT12 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT12 - #define TC1Hi_BIT13 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT13 - #define TC1Hi_BIT14 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT14 - #define TC1Hi_BIT15 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT15 - #define TC1Hi_BIT_8 _TC1.Overlap_STR.TC1HiSTR.MergedBits.grpBIT_8 - #define TC1Hi_BIT TC1Hi_BIT_8 - - /*** TC1Lo - Timer Input Capture/Output Compare Register 1 Low; 0x00000053 ***/ - union { - byte Byte; - struct { - byte BIT0 :1; /* Timer Input Capture/Output Compare Register 1 Bit 0 */ - byte BIT1 :1; /* Timer Input Capture/Output Compare Register 1 Bit 1 */ - byte BIT2 :1; /* Timer Input Capture/Output Compare Register 1 Bit 2 */ - byte BIT3 :1; /* Timer Input Capture/Output Compare Register 1 Bit 3 */ - byte BIT4 :1; /* Timer Input Capture/Output Compare Register 1 Bit 4 */ - byte BIT5 :1; /* Timer Input Capture/Output Compare Register 1 Bit 5 */ - byte BIT6 :1; /* Timer Input Capture/Output Compare Register 1 Bit 6 */ - byte BIT7 :1; /* Timer Input Capture/Output Compare Register 1 Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; - } TC1LoSTR; - #define TC1Lo _TC1.Overlap_STR.TC1LoSTR.Byte - #define TC1Lo_BIT0 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT0 - #define TC1Lo_BIT1 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT1 - #define TC1Lo_BIT2 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT2 - #define TC1Lo_BIT3 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT3 - #define TC1Lo_BIT4 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT4 - #define TC1Lo_BIT5 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT5 - #define TC1Lo_BIT6 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT6 - #define TC1Lo_BIT7 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT7 - #define TC1Lo_BIT _TC1.Overlap_STR.TC1LoSTR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word grpBIT :16; - } MergedBits; -} TC1STR; -extern volatile TC1STR _TC1 @(REG_BASE + 0x00000052); -#define TC1 _TC1.Word -#define TC1_BIT _TC1.MergedBits.grpBIT - - -/*** TC2 - Timer Input Capture/Output Compare Register 2; 0x00000054 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** TC2Hi - Timer Input Capture/Output Compare Register 2 High; 0x00000054 ***/ - union { - byte Byte; - struct { - byte BIT8 :1; /* Timer Input Capture/Output Compare Register 2 Bit 8 */ - byte BIT9 :1; /* Timer Input Capture/Output Compare Register 2 Bit 9 */ - byte BIT10 :1; /* Timer Input Capture/Output Compare Register 2 Bit 10 */ - byte BIT11 :1; /* Timer Input Capture/Output Compare Register 2 Bit 11 */ - byte BIT12 :1; /* Timer Input Capture/Output Compare Register 2 Bit 12 */ - byte BIT13 :1; /* Timer Input Capture/Output Compare Register 2 Bit 13 */ - byte BIT14 :1; /* Timer Input Capture/Output Compare Register 2 Bit 14 */ - byte BIT15 :1; /* Timer Input Capture/Output Compare Register 2 Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; - } TC2HiSTR; - #define TC2Hi _TC2.Overlap_STR.TC2HiSTR.Byte - #define TC2Hi_BIT8 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT8 - #define TC2Hi_BIT9 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT9 - #define TC2Hi_BIT10 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT10 - #define TC2Hi_BIT11 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT11 - #define TC2Hi_BIT12 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT12 - #define TC2Hi_BIT13 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT13 - #define TC2Hi_BIT14 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT14 - #define TC2Hi_BIT15 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT15 - #define TC2Hi_BIT_8 _TC2.Overlap_STR.TC2HiSTR.MergedBits.grpBIT_8 - #define TC2Hi_BIT TC2Hi_BIT_8 - - /*** TC2Lo - Timer Input Capture/Output Compare Register 2 Low; 0x00000055 ***/ - union { - byte Byte; - struct { - byte BIT0 :1; /* Timer Input Capture/Output Compare Register 2 Bit 0 */ - byte BIT1 :1; /* Timer Input Capture/Output Compare Register 2 Bit 1 */ - byte BIT2 :1; /* Timer Input Capture/Output Compare Register 2 Bit 2 */ - byte BIT3 :1; /* Timer Input Capture/Output Compare Register 2 Bit 3 */ - byte BIT4 :1; /* Timer Input Capture/Output Compare Register 2 Bit 4 */ - byte BIT5 :1; /* Timer Input Capture/Output Compare Register 2 Bit 5 */ - byte BIT6 :1; /* Timer Input Capture/Output Compare Register 2 Bit 6 */ - byte BIT7 :1; /* Timer Input Capture/Output Compare Register 2 Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; - } TC2LoSTR; - #define TC2Lo _TC2.Overlap_STR.TC2LoSTR.Byte - #define TC2Lo_BIT0 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT0 - #define TC2Lo_BIT1 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT1 - #define TC2Lo_BIT2 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT2 - #define TC2Lo_BIT3 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT3 - #define TC2Lo_BIT4 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT4 - #define TC2Lo_BIT5 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT5 - #define TC2Lo_BIT6 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT6 - #define TC2Lo_BIT7 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT7 - #define TC2Lo_BIT _TC2.Overlap_STR.TC2LoSTR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word grpBIT :16; - } MergedBits; -} TC2STR; -extern volatile TC2STR _TC2 @(REG_BASE + 0x00000054); -#define TC2 _TC2.Word -#define TC2_BIT _TC2.MergedBits.grpBIT - - -/*** TC3 - Timer Input Capture/Output Compare Register 3; 0x00000056 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** TC3Hi - Timer Input Capture/Output Compare Register 3 High; 0x00000056 ***/ - union { - byte Byte; - struct { - byte BIT8 :1; /* Timer Input Capture/Output Compare Register 3 Bit 8 */ - byte BIT9 :1; /* Timer Input Capture/Output Compare Register 3 Bit 9 */ - byte BIT10 :1; /* Timer Input Capture/Output Compare Register 3 Bit 10 */ - byte BIT11 :1; /* Timer Input Capture/Output Compare Register 3 Bit 11 */ - byte BIT12 :1; /* Timer Input Capture/Output Compare Register 3 Bit 12 */ - byte BIT13 :1; /* Timer Input Capture/Output Compare Register 3 Bit 13 */ - byte BIT14 :1; /* Timer Input Capture/Output Compare Register 3 Bit 14 */ - byte BIT15 :1; /* Timer Input Capture/Output Compare Register 3 Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; - } TC3HiSTR; - #define TC3Hi _TC3.Overlap_STR.TC3HiSTR.Byte - #define TC3Hi_BIT8 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT8 - #define TC3Hi_BIT9 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT9 - #define TC3Hi_BIT10 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT10 - #define TC3Hi_BIT11 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT11 - #define TC3Hi_BIT12 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT12 - #define TC3Hi_BIT13 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT13 - #define TC3Hi_BIT14 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT14 - #define TC3Hi_BIT15 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT15 - #define TC3Hi_BIT_8 _TC3.Overlap_STR.TC3HiSTR.MergedBits.grpBIT_8 - #define TC3Hi_BIT TC3Hi_BIT_8 - - /*** TC3Lo - Timer Input Capture/Output Compare Register 3 Low; 0x00000057 ***/ - union { - byte Byte; - struct { - byte BIT0 :1; /* Timer Input Capture/Output Compare Register 3 Bit 0 */ - byte BIT1 :1; /* Timer Input Capture/Output Compare Register 3 Bit 1 */ - byte BIT2 :1; /* Timer Input Capture/Output Compare Register 3 Bit 2 */ - byte BIT3 :1; /* Timer Input Capture/Output Compare Register 3 Bit 3 */ - byte BIT4 :1; /* Timer Input Capture/Output Compare Register 3 Bit 4 */ - byte BIT5 :1; /* Timer Input Capture/Output Compare Register 3 Bit 5 */ - byte BIT6 :1; /* Timer Input Capture/Output Compare Register 3 Bit 6 */ - byte BIT7 :1; /* Timer Input Capture/Output Compare Register 3 Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; - } TC3LoSTR; - #define TC3Lo _TC3.Overlap_STR.TC3LoSTR.Byte - #define TC3Lo_BIT0 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT0 - #define TC3Lo_BIT1 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT1 - #define TC3Lo_BIT2 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT2 - #define TC3Lo_BIT3 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT3 - #define TC3Lo_BIT4 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT4 - #define TC3Lo_BIT5 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT5 - #define TC3Lo_BIT6 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT6 - #define TC3Lo_BIT7 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT7 - #define TC3Lo_BIT _TC3.Overlap_STR.TC3LoSTR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word grpBIT :16; - } MergedBits; -} TC3STR; -extern volatile TC3STR _TC3 @(REG_BASE + 0x00000056); -#define TC3 _TC3.Word -#define TC3_BIT _TC3.MergedBits.grpBIT - - -/*** TC4 - Timer Input Capture/Output Compare Register 4; 0x00000058 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** TC4Hi - Timer Input Capture/Output Compare Register 4 High; 0x00000058 ***/ - union { - byte Byte; - struct { - byte BIT8 :1; /* Timer Input Capture/Output Compare Register 4 Bit 8 */ - byte BIT9 :1; /* Timer Input Capture/Output Compare Register 4 Bit 9 */ - byte BIT10 :1; /* Timer Input Capture/Output Compare Register 4 Bit 10 */ - byte BIT11 :1; /* Timer Input Capture/Output Compare Register 4 Bit 11 */ - byte BIT12 :1; /* Timer Input Capture/Output Compare Register 4 Bit 12 */ - byte BIT13 :1; /* Timer Input Capture/Output Compare Register 4 Bit 13 */ - byte BIT14 :1; /* Timer Input Capture/Output Compare Register 4 Bit 14 */ - byte BIT15 :1; /* Timer Input Capture/Output Compare Register 4 Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; - } TC4HiSTR; - #define TC4Hi _TC4.Overlap_STR.TC4HiSTR.Byte - #define TC4Hi_BIT8 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT8 - #define TC4Hi_BIT9 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT9 - #define TC4Hi_BIT10 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT10 - #define TC4Hi_BIT11 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT11 - #define TC4Hi_BIT12 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT12 - #define TC4Hi_BIT13 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT13 - #define TC4Hi_BIT14 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT14 - #define TC4Hi_BIT15 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT15 - #define TC4Hi_BIT_8 _TC4.Overlap_STR.TC4HiSTR.MergedBits.grpBIT_8 - #define TC4Hi_BIT TC4Hi_BIT_8 - - /*** TC4Lo - Timer Input Capture/Output Compare Register 4 Low; 0x00000059 ***/ - union { - byte Byte; - struct { - byte BIT0 :1; /* Timer Input Capture/Output Compare Register 4 Bit 0 */ - byte BIT1 :1; /* Timer Input Capture/Output Compare Register 4 Bit 1 */ - byte BIT2 :1; /* Timer Input Capture/Output Compare Register 4 Bit 2 */ - byte BIT3 :1; /* Timer Input Capture/Output Compare Register 4 Bit 3 */ - byte BIT4 :1; /* Timer Input Capture/Output Compare Register 4 Bit 4 */ - byte BIT5 :1; /* Timer Input Capture/Output Compare Register 4 Bit 5 */ - byte BIT6 :1; /* Timer Input Capture/Output Compare Register 4 Bit 6 */ - byte BIT7 :1; /* Timer Input Capture/Output Compare Register 4 Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; - } TC4LoSTR; - #define TC4Lo _TC4.Overlap_STR.TC4LoSTR.Byte - #define TC4Lo_BIT0 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT0 - #define TC4Lo_BIT1 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT1 - #define TC4Lo_BIT2 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT2 - #define TC4Lo_BIT3 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT3 - #define TC4Lo_BIT4 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT4 - #define TC4Lo_BIT5 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT5 - #define TC4Lo_BIT6 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT6 - #define TC4Lo_BIT7 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT7 - #define TC4Lo_BIT _TC4.Overlap_STR.TC4LoSTR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word grpBIT :16; - } MergedBits; -} TC4STR; -extern volatile TC4STR _TC4 @(REG_BASE + 0x00000058); -#define TC4 _TC4.Word -#define TC4_BIT _TC4.MergedBits.grpBIT - - -/*** TC5 - Timer Input Capture/Output Compare Register 5; 0x0000005A ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** TC5Hi - Timer Input Capture/Output Compare Register 5 High; 0x0000005A ***/ - union { - byte Byte; - struct { - byte BIT8 :1; /* Timer Input Capture/Output Compare Register 5 Bit 8 */ - byte BIT9 :1; /* Timer Input Capture/Output Compare Register 5 Bit 9 */ - byte BIT10 :1; /* Timer Input Capture/Output Compare Register 5 Bit 10 */ - byte BIT11 :1; /* Timer Input Capture/Output Compare Register 5 Bit 11 */ - byte BIT12 :1; /* Timer Input Capture/Output Compare Register 5 Bit 12 */ - byte BIT13 :1; /* Timer Input Capture/Output Compare Register 5 Bit 13 */ - byte BIT14 :1; /* Timer Input Capture/Output Compare Register 5 Bit 14 */ - byte BIT15 :1; /* Timer Input Capture/Output Compare Register 5 Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; - } TC5HiSTR; - #define TC5Hi _TC5.Overlap_STR.TC5HiSTR.Byte - #define TC5Hi_BIT8 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT8 - #define TC5Hi_BIT9 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT9 - #define TC5Hi_BIT10 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT10 - #define TC5Hi_BIT11 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT11 - #define TC5Hi_BIT12 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT12 - #define TC5Hi_BIT13 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT13 - #define TC5Hi_BIT14 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT14 - #define TC5Hi_BIT15 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT15 - #define TC5Hi_BIT_8 _TC5.Overlap_STR.TC5HiSTR.MergedBits.grpBIT_8 - #define TC5Hi_BIT TC5Hi_BIT_8 - - /*** TC5Lo - Timer Input Capture/Output Compare Register 5 Low; 0x0000005B ***/ - union { - byte Byte; - struct { - byte BIT0 :1; /* Timer Input Capture/Output Compare Register 5 Bit 0 */ - byte BIT1 :1; /* Timer Input Capture/Output Compare Register 5 Bit 1 */ - byte BIT2 :1; /* Timer Input Capture/Output Compare Register 5 Bit 2 */ - byte BIT3 :1; /* Timer Input Capture/Output Compare Register 5 Bit 3 */ - byte BIT4 :1; /* Timer Input Capture/Output Compare Register 5 Bit 4 */ - byte BIT5 :1; /* Timer Input Capture/Output Compare Register 5 Bit 5 */ - byte BIT6 :1; /* Timer Input Capture/Output Compare Register 5 Bit 6 */ - byte BIT7 :1; /* Timer Input Capture/Output Compare Register 5 Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; - } TC5LoSTR; - #define TC5Lo _TC5.Overlap_STR.TC5LoSTR.Byte - #define TC5Lo_BIT0 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT0 - #define TC5Lo_BIT1 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT1 - #define TC5Lo_BIT2 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT2 - #define TC5Lo_BIT3 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT3 - #define TC5Lo_BIT4 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT4 - #define TC5Lo_BIT5 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT5 - #define TC5Lo_BIT6 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT6 - #define TC5Lo_BIT7 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT7 - #define TC5Lo_BIT _TC5.Overlap_STR.TC5LoSTR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word grpBIT :16; - } MergedBits; -} TC5STR; -extern volatile TC5STR _TC5 @(REG_BASE + 0x0000005A); -#define TC5 _TC5.Word -#define TC5_BIT _TC5.MergedBits.grpBIT - - -/*** TC6 - Timer Input Capture/Output Compare Register 6; 0x0000005C ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** TC6Hi - Timer Input Capture/Output Compare Register 6 High; 0x0000005C ***/ - union { - byte Byte; - struct { - byte BIT8 :1; /* Timer Input Capture/Output Compare Register 6 Bit 8 */ - byte BIT9 :1; /* Timer Input Capture/Output Compare Register 6 Bit 9 */ - byte BIT10 :1; /* Timer Input Capture/Output Compare Register 6 Bit 10 */ - byte BIT11 :1; /* Timer Input Capture/Output Compare Register 6 Bit 11 */ - byte BIT12 :1; /* Timer Input Capture/Output Compare Register 6 Bit 12 */ - byte BIT13 :1; /* Timer Input Capture/Output Compare Register 6 Bit 13 */ - byte BIT14 :1; /* Timer Input Capture/Output Compare Register 6 Bit 14 */ - byte BIT15 :1; /* Timer Input Capture/Output Compare Register 6 Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; - } TC6HiSTR; - #define TC6Hi _TC6.Overlap_STR.TC6HiSTR.Byte - #define TC6Hi_BIT8 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT8 - #define TC6Hi_BIT9 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT9 - #define TC6Hi_BIT10 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT10 - #define TC6Hi_BIT11 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT11 - #define TC6Hi_BIT12 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT12 - #define TC6Hi_BIT13 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT13 - #define TC6Hi_BIT14 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT14 - #define TC6Hi_BIT15 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT15 - #define TC6Hi_BIT_8 _TC6.Overlap_STR.TC6HiSTR.MergedBits.grpBIT_8 - #define TC6Hi_BIT TC6Hi_BIT_8 - - /*** TC6Lo - Timer Input Capture/Output Compare Register 6 Low; 0x0000005D ***/ - union { - byte Byte; - struct { - byte BIT0 :1; /* Timer Input Capture/Output Compare Register 6 Bit 0 */ - byte BIT1 :1; /* Timer Input Capture/Output Compare Register 6 Bit 1 */ - byte BIT2 :1; /* Timer Input Capture/Output Compare Register 6 Bit 2 */ - byte BIT3 :1; /* Timer Input Capture/Output Compare Register 6 Bit 3 */ - byte BIT4 :1; /* Timer Input Capture/Output Compare Register 6 Bit 4 */ - byte BIT5 :1; /* Timer Input Capture/Output Compare Register 6 Bit 5 */ - byte BIT6 :1; /* Timer Input Capture/Output Compare Register 6 Bit 6 */ - byte BIT7 :1; /* Timer Input Capture/Output Compare Register 6 Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; - } TC6LoSTR; - #define TC6Lo _TC6.Overlap_STR.TC6LoSTR.Byte - #define TC6Lo_BIT0 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT0 - #define TC6Lo_BIT1 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT1 - #define TC6Lo_BIT2 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT2 - #define TC6Lo_BIT3 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT3 - #define TC6Lo_BIT4 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT4 - #define TC6Lo_BIT5 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT5 - #define TC6Lo_BIT6 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT6 - #define TC6Lo_BIT7 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT7 - #define TC6Lo_BIT _TC6.Overlap_STR.TC6LoSTR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word grpBIT :16; - } MergedBits; -} TC6STR; -extern volatile TC6STR _TC6 @(REG_BASE + 0x0000005C); -#define TC6 _TC6.Word -#define TC6_BIT _TC6.MergedBits.grpBIT - - -/*** TC7 - Timer Input Capture/Output Compare Register 7; 0x0000005E ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** TC7Hi - Timer Input Capture/Output Compare Register 7 High; 0x0000005E ***/ - union { - byte Byte; - struct { - byte BIT8 :1; /* Timer Input Capture/Output Compare Register 7 Bit 8 */ - byte BIT9 :1; /* Timer Input Capture/Output Compare Register 7 Bit 9 */ - byte BIT10 :1; /* Timer Input Capture/Output Compare Register 7 Bit 10 */ - byte BIT11 :1; /* Timer Input Capture/Output Compare Register 7 Bit 11 */ - byte BIT12 :1; /* Timer Input Capture/Output Compare Register 7 Bit 12 */ - byte BIT13 :1; /* Timer Input Capture/Output Compare Register 7 Bit 13 */ - byte BIT14 :1; /* Timer Input Capture/Output Compare Register 7 Bit 14 */ - byte BIT15 :1; /* Timer Input Capture/Output Compare Register 7 Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; - } TC7HiSTR; - #define TC7Hi _TC7.Overlap_STR.TC7HiSTR.Byte - #define TC7Hi_BIT8 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT8 - #define TC7Hi_BIT9 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT9 - #define TC7Hi_BIT10 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT10 - #define TC7Hi_BIT11 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT11 - #define TC7Hi_BIT12 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT12 - #define TC7Hi_BIT13 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT13 - #define TC7Hi_BIT14 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT14 - #define TC7Hi_BIT15 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT15 - #define TC7Hi_BIT_8 _TC7.Overlap_STR.TC7HiSTR.MergedBits.grpBIT_8 - #define TC7Hi_BIT TC7Hi_BIT_8 - - /*** TC7Lo - Timer Input Capture/Output Compare Register 7 Low; 0x0000005F ***/ - union { - byte Byte; - struct { - byte BIT0 :1; /* Timer Input Capture/Output Compare Register 7 Bit 0 */ - byte BIT1 :1; /* Timer Input Capture/Output Compare Register 7 Bit 1 */ - byte BIT2 :1; /* Timer Input Capture/Output Compare Register 7 Bit 2 */ - byte BIT3 :1; /* Timer Input Capture/Output Compare Register 7 Bit 3 */ - byte BIT4 :1; /* Timer Input Capture/Output Compare Register 7 Bit 4 */ - byte BIT5 :1; /* Timer Input Capture/Output Compare Register 7 Bit 5 */ - byte BIT6 :1; /* Timer Input Capture/Output Compare Register 7 Bit 6 */ - byte BIT7 :1; /* Timer Input Capture/Output Compare Register 7 Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; - } TC7LoSTR; - #define TC7Lo _TC7.Overlap_STR.TC7LoSTR.Byte - #define TC7Lo_BIT0 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT0 - #define TC7Lo_BIT1 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT1 - #define TC7Lo_BIT2 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT2 - #define TC7Lo_BIT3 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT3 - #define TC7Lo_BIT4 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT4 - #define TC7Lo_BIT5 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT5 - #define TC7Lo_BIT6 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT6 - #define TC7Lo_BIT7 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT7 - #define TC7Lo_BIT _TC7.Overlap_STR.TC7LoSTR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word grpBIT :16; - } MergedBits; -} TC7STR; -extern volatile TC7STR _TC7 @(REG_BASE + 0x0000005E); -#define TC7 _TC7.Word -#define TC7_BIT _TC7.MergedBits.grpBIT - - -/*** PACN32 - Pulse Accumulators Count 32 Register; 0x00000062 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** PACN3 - Pulse Accumulators Count 3 Register; 0x00000062 ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PACN3STR; - #define PACN3 _PACN32.Overlap_STR.PACN3STR.Byte - #define PACN3_BIT _PACN32.Overlap_STR.PACN3STR.MergedBits.grpBIT - - /*** PACN2 - Pulse Accumulators Count 2 Register; 0x00000063 ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PACN2STR; - #define PACN2 _PACN32.Overlap_STR.PACN2STR.Byte - #define PACN2_BIT _PACN32.Overlap_STR.PACN2STR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word grpBIT :16; - } MergedBits; -} PACN32STR; -extern volatile PACN32STR _PACN32 @(REG_BASE + 0x00000062); -#define PACN32 _PACN32.Word -#define PACN32_BIT _PACN32.MergedBits.grpBIT - - -/*** PACN10 - Pulse Accumulators Count 10 Register; 0x00000064 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** PACN1 - Pulse Accumulators Count 1 Register; 0x00000064 ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PACN1STR; - #define PACN1 _PACN10.Overlap_STR.PACN1STR.Byte - #define PACN1_BIT _PACN10.Overlap_STR.PACN1STR.MergedBits.grpBIT - - /*** PACN0 - Pulse Accumulators Count 0 Register; 0x00000065 ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PACN0STR; - #define PACN0 _PACN10.Overlap_STR.PACN0STR.Byte - #define PACN0_BIT _PACN10.Overlap_STR.PACN0STR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word grpBIT :16; - } MergedBits; -} PACN10STR; -extern volatile PACN10STR _PACN10 @(REG_BASE + 0x00000064); -#define PACN10 _PACN10.Word -#define PACN10_BIT _PACN10.MergedBits.grpBIT - - -/*** PA32H - 8-Bit Pulse Accumulators Holding 32 Register; 0x00000072 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** PA3H - 8-Bit Pulse Accumulators Holding 3 Register; 0x00000072 ***/ - union { - byte Byte; - struct { - byte BIT0 :1; /* Pulse Accumulator Bit 0 */ - byte BIT1 :1; /* Pulse Accumulator Bit 1 */ - byte BIT2 :1; /* Pulse Accumulator Bit 2 */ - byte BIT3 :1; /* Pulse Accumulator Bit 3 */ - byte BIT4 :1; /* Pulse Accumulator Bit 4 */ - byte BIT5 :1; /* Pulse Accumulator Bit 5 */ - byte BIT6 :1; /* Pulse Accumulator Bit 6 */ - byte BIT7 :1; /* Pulse Accumulator Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; - } PA3HSTR; - #define PA3H _PA32H.Overlap_STR.PA3HSTR.Byte - #define PA3H_BIT0 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT0 - #define PA3H_BIT1 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT1 - #define PA3H_BIT2 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT2 - #define PA3H_BIT3 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT3 - #define PA3H_BIT4 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT4 - #define PA3H_BIT5 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT5 - #define PA3H_BIT6 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT6 - #define PA3H_BIT7 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT7 - #define PA3H_BIT _PA32H.Overlap_STR.PA3HSTR.MergedBits.grpBIT - - /*** PA2H - 8-Bit Pulse Accumulators Holding 2 Register; 0x00000073 ***/ - union { - byte Byte; - struct { - byte BIT0 :1; /* Pulse Accumulator Bit 0 */ - byte BIT1 :1; /* Pulse Accumulator Bit 1 */ - byte BIT2 :1; /* Pulse Accumulator Bit 2 */ - byte BIT3 :1; /* Pulse Accumulator Bit 3 */ - byte BIT4 :1; /* Pulse Accumulator Bit 4 */ - byte BIT5 :1; /* Pulse Accumulator Bit 5 */ - byte BIT6 :1; /* Pulse Accumulator Bit 6 */ - byte BIT7 :1; /* Pulse Accumulator Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; - } PA2HSTR; - #define PA2H _PA32H.Overlap_STR.PA2HSTR.Byte - #define PA2H_BIT0 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT0 - #define PA2H_BIT1 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT1 - #define PA2H_BIT2 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT2 - #define PA2H_BIT3 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT3 - #define PA2H_BIT4 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT4 - #define PA2H_BIT5 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT5 - #define PA2H_BIT6 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT6 - #define PA2H_BIT7 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT7 - #define PA2H_BIT _PA32H.Overlap_STR.PA2HSTR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word BIT0 :1; /* Pulse Accumulator Bit 0 */ - word BIT1 :1; /* Pulse Accumulator Bit 1 */ - word BIT2 :1; /* Pulse Accumulator Bit 2 */ - word BIT3 :1; /* Pulse Accumulator Bit 3 */ - word BIT4 :1; /* Pulse Accumulator Bit 4 */ - word BIT5 :1; /* Pulse Accumulator Bit 5 */ - word BIT6 :1; /* Pulse Accumulator Bit 6 */ - word BIT7 :1; /* Pulse Accumulator Bit 7 */ - word BIT8 :1; /* Pulse Accumulator Bit 8 */ - word BIT9 :1; /* Pulse Accumulator Bit 9 */ - word BIT10 :1; /* Pulse Accumulator Bit 10 */ - word BIT11 :1; /* Pulse Accumulator Bit 11 */ - word BIT12 :1; /* Pulse Accumulator Bit 12 */ - word BIT13 :1; /* Pulse Accumulator Bit 13 */ - word BIT14 :1; /* Pulse Accumulator Bit 14 */ - word BIT15 :1; /* Pulse Accumulator Bit 15 */ - } Bits; - struct { - word grpBIT :16; - } MergedBits; -} PA32HSTR; -extern volatile PA32HSTR _PA32H @(REG_BASE + 0x00000072); -#define PA32H _PA32H.Word -#define PA32H_BIT0 _PA32H.Bits.BIT0 -#define PA32H_BIT1 _PA32H.Bits.BIT1 -#define PA32H_BIT2 _PA32H.Bits.BIT2 -#define PA32H_BIT3 _PA32H.Bits.BIT3 -#define PA32H_BIT4 _PA32H.Bits.BIT4 -#define PA32H_BIT5 _PA32H.Bits.BIT5 -#define PA32H_BIT6 _PA32H.Bits.BIT6 -#define PA32H_BIT7 _PA32H.Bits.BIT7 -#define PA32H_BIT8 _PA32H.Bits.BIT8 -#define PA32H_BIT9 _PA32H.Bits.BIT9 -#define PA32H_BIT10 _PA32H.Bits.BIT10 -#define PA32H_BIT11 _PA32H.Bits.BIT11 -#define PA32H_BIT12 _PA32H.Bits.BIT12 -#define PA32H_BIT13 _PA32H.Bits.BIT13 -#define PA32H_BIT14 _PA32H.Bits.BIT14 -#define PA32H_BIT15 _PA32H.Bits.BIT15 -#define PA32H_BIT _PA32H.MergedBits.grpBIT - - -/*** PA10H - 8-Bit Pulse Accumulators Holding 10 Register; 0x00000074 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** PA1H - 8-Bit Pulse Accumulators Holding 1 Register; 0x00000074 ***/ - union { - byte Byte; - struct { - byte BIT0 :1; /* Pulse Accumulator Bit 0 */ - byte BIT1 :1; /* Pulse Accumulator Bit 1 */ - byte BIT2 :1; /* Pulse Accumulator Bit 2 */ - byte BIT3 :1; /* Pulse Accumulator Bit 3 */ - byte BIT4 :1; /* Pulse Accumulator Bit 4 */ - byte BIT5 :1; /* Pulse Accumulator Bit 5 */ - byte BIT6 :1; /* Pulse Accumulator Bit 6 */ - byte BIT7 :1; /* Pulse Accumulator Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; - } PA1HSTR; - #define PA1H _PA10H.Overlap_STR.PA1HSTR.Byte - #define PA1H_BIT0 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT0 - #define PA1H_BIT1 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT1 - #define PA1H_BIT2 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT2 - #define PA1H_BIT3 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT3 - #define PA1H_BIT4 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT4 - #define PA1H_BIT5 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT5 - #define PA1H_BIT6 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT6 - #define PA1H_BIT7 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT7 - #define PA1H_BIT _PA10H.Overlap_STR.PA1HSTR.MergedBits.grpBIT - - /*** PA0H - 8-Bit Pulse Accumulators Holding 0 Register; 0x00000075 ***/ - union { - byte Byte; - struct { - byte BIT0 :1; /* Pulse Accumulator Bit 0 */ - byte BIT1 :1; /* Pulse Accumulator Bit 1 */ - byte BIT2 :1; /* Pulse Accumulator Bit 2 */ - byte BIT3 :1; /* Pulse Accumulator Bit 3 */ - byte BIT4 :1; /* Pulse Accumulator Bit 4 */ - byte BIT5 :1; /* Pulse Accumulator Bit 5 */ - byte BIT6 :1; /* Pulse Accumulator Bit 6 */ - byte BIT7 :1; /* Pulse Accumulator Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; - } PA0HSTR; - #define PA0H _PA10H.Overlap_STR.PA0HSTR.Byte - #define PA0H_BIT0 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT0 - #define PA0H_BIT1 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT1 - #define PA0H_BIT2 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT2 - #define PA0H_BIT3 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT3 - #define PA0H_BIT4 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT4 - #define PA0H_BIT5 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT5 - #define PA0H_BIT6 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT6 - #define PA0H_BIT7 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT7 - #define PA0H_BIT _PA10H.Overlap_STR.PA0HSTR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word BIT0 :1; /* Pulse Accumulator Bit 0 */ - word BIT1 :1; /* Pulse Accumulator Bit 1 */ - word BIT2 :1; /* Pulse Accumulator Bit 2 */ - word BIT3 :1; /* Pulse Accumulator Bit 3 */ - word BIT4 :1; /* Pulse Accumulator Bit 4 */ - word BIT5 :1; /* Pulse Accumulator Bit 5 */ - word BIT6 :1; /* Pulse Accumulator Bit 6 */ - word BIT7 :1; /* Pulse Accumulator Bit 7 */ - word BIT8 :1; /* Pulse Accumulator Bit 8 */ - word BIT9 :1; /* Pulse Accumulator Bit 9 */ - word BIT10 :1; /* Pulse Accumulator Bit 10 */ - word BIT11 :1; /* Pulse Accumulator Bit 11 */ - word BIT12 :1; /* Pulse Accumulator Bit 12 */ - word BIT13 :1; /* Pulse Accumulator Bit 13 */ - word BIT14 :1; /* Pulse Accumulator Bit 14 */ - word BIT15 :1; /* Pulse Accumulator Bit 15 */ - } Bits; - struct { - word grpBIT :16; - } MergedBits; -} PA10HSTR; -extern volatile PA10HSTR _PA10H @(REG_BASE + 0x00000074); -#define PA10H _PA10H.Word -#define PA10H_BIT0 _PA10H.Bits.BIT0 -#define PA10H_BIT1 _PA10H.Bits.BIT1 -#define PA10H_BIT2 _PA10H.Bits.BIT2 -#define PA10H_BIT3 _PA10H.Bits.BIT3 -#define PA10H_BIT4 _PA10H.Bits.BIT4 -#define PA10H_BIT5 _PA10H.Bits.BIT5 -#define PA10H_BIT6 _PA10H.Bits.BIT6 -#define PA10H_BIT7 _PA10H.Bits.BIT7 -#define PA10H_BIT8 _PA10H.Bits.BIT8 -#define PA10H_BIT9 _PA10H.Bits.BIT9 -#define PA10H_BIT10 _PA10H.Bits.BIT10 -#define PA10H_BIT11 _PA10H.Bits.BIT11 -#define PA10H_BIT12 _PA10H.Bits.BIT12 -#define PA10H_BIT13 _PA10H.Bits.BIT13 -#define PA10H_BIT14 _PA10H.Bits.BIT14 -#define PA10H_BIT15 _PA10H.Bits.BIT15 -#define PA10H_BIT _PA10H.MergedBits.grpBIT - - -/*** MCCNT - Modulus Down-Counter Count Register; 0x00000076 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** MCCNThi - Modulus Down-Counter Count Register High; 0x00000076 ***/ - union { - byte Byte; - struct { - byte BIT8 :1; /* Modulus Down-Counter Bit 8 */ - byte BIT9 :1; /* Modulus Down-Counter Bit 9 */ - byte BIT10 :1; /* Modulus Down-Counter Bit 10 */ - byte BIT11 :1; /* Modulus Down-Counter Bit 11 */ - byte BIT12 :1; /* Modulus Down-Counter Bit 12 */ - byte BIT13 :1; /* Modulus Down-Counter Bit 13 */ - byte BIT14 :1; /* Modulus Down-Counter Bit 14 */ - byte BIT15 :1; /* Modulus Down-Counter Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; - } MCCNThiSTR; - #define MCCNThi _MCCNT.Overlap_STR.MCCNThiSTR.Byte - #define MCCNThi_BIT8 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT8 - #define MCCNThi_BIT9 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT9 - #define MCCNThi_BIT10 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT10 - #define MCCNThi_BIT11 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT11 - #define MCCNThi_BIT12 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT12 - #define MCCNThi_BIT13 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT13 - #define MCCNThi_BIT14 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT14 - #define MCCNThi_BIT15 _MCCNT.Overlap_STR.MCCNThiSTR.Bits.BIT15 - #define MCCNThi_BIT_8 _MCCNT.Overlap_STR.MCCNThiSTR.MergedBits.grpBIT_8 - #define MCCNThi_BIT MCCNThi_BIT_8 - - /*** MCCNTlo - Modulus Down-Counter Count Register Low; 0x00000077 ***/ - union { - byte Byte; - struct { - byte BIT0 :1; /* Modulus Down-Counter Bit 0 */ - byte BIT1 :1; /* Modulus Down-Counter Bit 1 */ - byte BIT2 :1; /* Modulus Down-Counter Bit 2 */ - byte BIT3 :1; /* Modulus Down-Counter Bit 3 */ - byte BIT4 :1; /* Modulus Down-Counter Bit 4 */ - byte BIT5 :1; /* Modulus Down-Counter Bit 5 */ - byte BIT6 :1; /* Modulus Down-Counter Bit 6 */ - byte BIT7 :1; /* Modulus Down-Counter Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; - } MCCNTloSTR; - #define MCCNTlo _MCCNT.Overlap_STR.MCCNTloSTR.Byte - #define MCCNTlo_BIT0 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT0 - #define MCCNTlo_BIT1 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT1 - #define MCCNTlo_BIT2 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT2 - #define MCCNTlo_BIT3 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT3 - #define MCCNTlo_BIT4 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT4 - #define MCCNTlo_BIT5 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT5 - #define MCCNTlo_BIT6 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT6 - #define MCCNTlo_BIT7 _MCCNT.Overlap_STR.MCCNTloSTR.Bits.BIT7 - #define MCCNTlo_BIT _MCCNT.Overlap_STR.MCCNTloSTR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word grpBIT :16; - } MergedBits; -} MCCNTSTR; -extern volatile MCCNTSTR _MCCNT @(REG_BASE + 0x00000076); -#define MCCNT _MCCNT.Word -#define MCCNT_BIT _MCCNT.MergedBits.grpBIT - - -/*** TC0H - Timer Input Capture Holding Registers 0; 0x00000078 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** TC0Hhi - Timer Input Capture Holding Registers 0 High; 0x00000078 ***/ - union { - byte Byte; - struct { - byte BIT8 :1; /* Timer Input Capture Holding Bit 8 */ - byte BIT9 :1; /* Timer Input Capture Holding Bit 9 */ - byte BIT10 :1; /* Timer Input Capture Holding Bit 10 */ - byte BIT11 :1; /* Timer Input Capture Holding Bit 11 */ - byte BIT12 :1; /* Timer Input Capture Holding Bit 12 */ - byte BIT13 :1; /* Timer Input Capture Holding Bit 13 */ - byte BIT14 :1; /* Timer Input Capture Holding Bit 14 */ - byte BIT15 :1; /* Timer Input Capture Holding Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; - } TC0HhiSTR; - #define TC0Hhi _TC0H.Overlap_STR.TC0HhiSTR.Byte - #define TC0Hhi_BIT8 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT8 - #define TC0Hhi_BIT9 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT9 - #define TC0Hhi_BIT10 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT10 - #define TC0Hhi_BIT11 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT11 - #define TC0Hhi_BIT12 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT12 - #define TC0Hhi_BIT13 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT13 - #define TC0Hhi_BIT14 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT14 - #define TC0Hhi_BIT15 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT15 - #define TC0Hhi_BIT_8 _TC0H.Overlap_STR.TC0HhiSTR.MergedBits.grpBIT_8 - #define TC0Hhi_BIT TC0Hhi_BIT_8 - - /*** TC0Hlo - Timer Input Capture Holding Registers 0 Low; 0x00000079 ***/ - union { - byte Byte; - struct { - byte BIT0 :1; /* Timer Input Capture Holding Bit 0 */ - byte BIT1 :1; /* Timer Input Capture Holding Bit 1 */ - byte BIT2 :1; /* Timer Input Capture Holding Bit 2 */ - byte BIT3 :1; /* Timer Input Capture Holding Bit 3 */ - byte BIT4 :1; /* Timer Input Capture Holding Bit 4 */ - byte BIT5 :1; /* Timer Input Capture Holding Bit 5 */ - byte BIT6 :1; /* Timer Input Capture Holding Bit 6 */ - byte BIT7 :1; /* Timer Input Capture Holding Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; - } TC0HloSTR; - #define TC0Hlo _TC0H.Overlap_STR.TC0HloSTR.Byte - #define TC0Hlo_BIT0 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT0 - #define TC0Hlo_BIT1 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT1 - #define TC0Hlo_BIT2 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT2 - #define TC0Hlo_BIT3 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT3 - #define TC0Hlo_BIT4 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT4 - #define TC0Hlo_BIT5 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT5 - #define TC0Hlo_BIT6 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT6 - #define TC0Hlo_BIT7 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT7 - #define TC0Hlo_BIT _TC0H.Overlap_STR.TC0HloSTR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word BIT0 :1; /* Timer Input Capture Holding Bit 0 */ - word BIT1 :1; /* Timer Input Capture Holding Bit 1 */ - word BIT2 :1; /* Timer Input Capture Holding Bit 2 */ - word BIT3 :1; /* Timer Input Capture Holding Bit 3 */ - word BIT4 :1; /* Timer Input Capture Holding Bit 4 */ - word BIT5 :1; /* Timer Input Capture Holding Bit 5 */ - word BIT6 :1; /* Timer Input Capture Holding Bit 6 */ - word BIT7 :1; /* Timer Input Capture Holding Bit 7 */ - word BIT8 :1; /* Timer Input Capture Holding Bit 8 */ - word BIT9 :1; /* Timer Input Capture Holding Bit 9 */ - word BIT10 :1; /* Timer Input Capture Holding Bit 10 */ - word BIT11 :1; /* Timer Input Capture Holding Bit 11 */ - word BIT12 :1; /* Timer Input Capture Holding Bit 12 */ - word BIT13 :1; /* Timer Input Capture Holding Bit 13 */ - word BIT14 :1; /* Timer Input Capture Holding Bit 14 */ - word BIT15 :1; /* Timer Input Capture Holding Bit 15 */ - } Bits; - struct { - word grpBIT :16; - } MergedBits; -} TC0HSTR; -extern volatile TC0HSTR _TC0H @(REG_BASE + 0x00000078); -#define TC0H _TC0H.Word -#define TC0H_BIT0 _TC0H.Bits.BIT0 -#define TC0H_BIT1 _TC0H.Bits.BIT1 -#define TC0H_BIT2 _TC0H.Bits.BIT2 -#define TC0H_BIT3 _TC0H.Bits.BIT3 -#define TC0H_BIT4 _TC0H.Bits.BIT4 -#define TC0H_BIT5 _TC0H.Bits.BIT5 -#define TC0H_BIT6 _TC0H.Bits.BIT6 -#define TC0H_BIT7 _TC0H.Bits.BIT7 -#define TC0H_BIT8 _TC0H.Bits.BIT8 -#define TC0H_BIT9 _TC0H.Bits.BIT9 -#define TC0H_BIT10 _TC0H.Bits.BIT10 -#define TC0H_BIT11 _TC0H.Bits.BIT11 -#define TC0H_BIT12 _TC0H.Bits.BIT12 -#define TC0H_BIT13 _TC0H.Bits.BIT13 -#define TC0H_BIT14 _TC0H.Bits.BIT14 -#define TC0H_BIT15 _TC0H.Bits.BIT15 -#define TC0H_BIT _TC0H.MergedBits.grpBIT - - -/*** TC1H - Timer Input Capture Holding Registers 1; 0x0000007A ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** TC1Hhi - Timer Input Capture Holding Registers 1 High; 0x0000007A ***/ - union { - byte Byte; - struct { - byte BIT8 :1; /* Timer Input Capture Holding Bit 8 */ - byte BIT9 :1; /* Timer Input Capture Holding Bit 9 */ - byte BIT10 :1; /* Timer Input Capture Holding Bit 10 */ - byte BIT11 :1; /* Timer Input Capture Holding Bit 11 */ - byte BIT12 :1; /* Timer Input Capture Holding Bit 12 */ - byte BIT13 :1; /* Timer Input Capture Holding Bit 13 */ - byte BIT14 :1; /* Timer Input Capture Holding Bit 14 */ - byte BIT15 :1; /* Timer Input Capture Holding Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; - } TC1HhiSTR; - #define TC1Hhi _TC1H.Overlap_STR.TC1HhiSTR.Byte - #define TC1Hhi_BIT8 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT8 - #define TC1Hhi_BIT9 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT9 - #define TC1Hhi_BIT10 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT10 - #define TC1Hhi_BIT11 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT11 - #define TC1Hhi_BIT12 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT12 - #define TC1Hhi_BIT13 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT13 - #define TC1Hhi_BIT14 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT14 - #define TC1Hhi_BIT15 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT15 - #define TC1Hhi_BIT_8 _TC1H.Overlap_STR.TC1HhiSTR.MergedBits.grpBIT_8 - #define TC1Hhi_BIT TC1Hhi_BIT_8 - - /*** TC1Hlo - Timer Input Capture Holding Registers 1 Low; 0x0000007B ***/ - union { - byte Byte; - struct { - byte BIT0 :1; /* Timer Input Capture Holding Bit 0 */ - byte BIT1 :1; /* Timer Input Capture Holding Bit 1 */ - byte BIT2 :1; /* Timer Input Capture Holding Bit 2 */ - byte BIT3 :1; /* Timer Input Capture Holding Bit 3 */ - byte BIT4 :1; /* Timer Input Capture Holding Bit 4 */ - byte BIT5 :1; /* Timer Input Capture Holding Bit 5 */ - byte BIT6 :1; /* Timer Input Capture Holding Bit 6 */ - byte BIT7 :1; /* Timer Input Capture Holding Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; - } TC1HloSTR; - #define TC1Hlo _TC1H.Overlap_STR.TC1HloSTR.Byte - #define TC1Hlo_BIT0 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT0 - #define TC1Hlo_BIT1 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT1 - #define TC1Hlo_BIT2 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT2 - #define TC1Hlo_BIT3 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT3 - #define TC1Hlo_BIT4 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT4 - #define TC1Hlo_BIT5 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT5 - #define TC1Hlo_BIT6 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT6 - #define TC1Hlo_BIT7 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT7 - #define TC1Hlo_BIT _TC1H.Overlap_STR.TC1HloSTR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word BIT0 :1; /* Timer Input Capture Holding Bit 0 */ - word BIT1 :1; /* Timer Input Capture Holding Bit 1 */ - word BIT2 :1; /* Timer Input Capture Holding Bit 2 */ - word BIT3 :1; /* Timer Input Capture Holding Bit 3 */ - word BIT4 :1; /* Timer Input Capture Holding Bit 4 */ - word BIT5 :1; /* Timer Input Capture Holding Bit 5 */ - word BIT6 :1; /* Timer Input Capture Holding Bit 6 */ - word BIT7 :1; /* Timer Input Capture Holding Bit 7 */ - word BIT8 :1; /* Timer Input Capture Holding Bit 8 */ - word BIT9 :1; /* Timer Input Capture Holding Bit 9 */ - word BIT10 :1; /* Timer Input Capture Holding Bit 10 */ - word BIT11 :1; /* Timer Input Capture Holding Bit 11 */ - word BIT12 :1; /* Timer Input Capture Holding Bit 12 */ - word BIT13 :1; /* Timer Input Capture Holding Bit 13 */ - word BIT14 :1; /* Timer Input Capture Holding Bit 14 */ - word BIT15 :1; /* Timer Input Capture Holding Bit 15 */ - } Bits; - struct { - word grpBIT :16; - } MergedBits; -} TC1HSTR; -extern volatile TC1HSTR _TC1H @(REG_BASE + 0x0000007A); -#define TC1H _TC1H.Word -#define TC1H_BIT0 _TC1H.Bits.BIT0 -#define TC1H_BIT1 _TC1H.Bits.BIT1 -#define TC1H_BIT2 _TC1H.Bits.BIT2 -#define TC1H_BIT3 _TC1H.Bits.BIT3 -#define TC1H_BIT4 _TC1H.Bits.BIT4 -#define TC1H_BIT5 _TC1H.Bits.BIT5 -#define TC1H_BIT6 _TC1H.Bits.BIT6 -#define TC1H_BIT7 _TC1H.Bits.BIT7 -#define TC1H_BIT8 _TC1H.Bits.BIT8 -#define TC1H_BIT9 _TC1H.Bits.BIT9 -#define TC1H_BIT10 _TC1H.Bits.BIT10 -#define TC1H_BIT11 _TC1H.Bits.BIT11 -#define TC1H_BIT12 _TC1H.Bits.BIT12 -#define TC1H_BIT13 _TC1H.Bits.BIT13 -#define TC1H_BIT14 _TC1H.Bits.BIT14 -#define TC1H_BIT15 _TC1H.Bits.BIT15 -#define TC1H_BIT _TC1H.MergedBits.grpBIT - - -/*** TC2H - Timer Input Capture Holding Registers 2; 0x0000007C ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** TC2Hhi - Timer Input Capture Holding Registers 2 High; 0x0000007C ***/ - union { - byte Byte; - struct { - byte BIT8 :1; /* Timer Input Capture Holding Bit 8 */ - byte BIT9 :1; /* Timer Input Capture Holding Bit 9 */ - byte BIT10 :1; /* Timer Input Capture Holding Bit 10 */ - byte BIT11 :1; /* Timer Input Capture Holding Bit 11 */ - byte BIT12 :1; /* Timer Input Capture Holding Bit 12 */ - byte BIT13 :1; /* Timer Input Capture Holding Bit 13 */ - byte BIT14 :1; /* Timer Input Capture Holding Bit 14 */ - byte BIT15 :1; /* Timer Input Capture Holding Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; - } TC2HhiSTR; - #define TC2Hhi _TC2H.Overlap_STR.TC2HhiSTR.Byte - #define TC2Hhi_BIT8 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT8 - #define TC2Hhi_BIT9 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT9 - #define TC2Hhi_BIT10 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT10 - #define TC2Hhi_BIT11 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT11 - #define TC2Hhi_BIT12 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT12 - #define TC2Hhi_BIT13 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT13 - #define TC2Hhi_BIT14 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT14 - #define TC2Hhi_BIT15 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT15 - #define TC2Hhi_BIT_8 _TC2H.Overlap_STR.TC2HhiSTR.MergedBits.grpBIT_8 - #define TC2Hhi_BIT TC2Hhi_BIT_8 - - /*** TC2Hlo - Timer Input Capture Holding Registers 2 Low; 0x0000007D ***/ - union { - byte Byte; - struct { - byte BIT0 :1; /* Timer Input Capture Holding Bit 0 */ - byte BIT1 :1; /* Timer Input Capture Holding Bit 1 */ - byte BIT2 :1; /* Timer Input Capture Holding Bit 2 */ - byte BIT3 :1; /* Timer Input Capture Holding Bit 3 */ - byte BIT4 :1; /* Timer Input Capture Holding Bit 4 */ - byte BIT5 :1; /* Timer Input Capture Holding Bit 5 */ - byte BIT6 :1; /* Timer Input Capture Holding Bit 6 */ - byte BIT7 :1; /* Timer Input Capture Holding Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; - } TC2HloSTR; - #define TC2Hlo _TC2H.Overlap_STR.TC2HloSTR.Byte - #define TC2Hlo_BIT0 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT0 - #define TC2Hlo_BIT1 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT1 - #define TC2Hlo_BIT2 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT2 - #define TC2Hlo_BIT3 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT3 - #define TC2Hlo_BIT4 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT4 - #define TC2Hlo_BIT5 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT5 - #define TC2Hlo_BIT6 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT6 - #define TC2Hlo_BIT7 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT7 - #define TC2Hlo_BIT _TC2H.Overlap_STR.TC2HloSTR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word BIT0 :1; /* Timer Input Capture Holding Bit 0 */ - word BIT1 :1; /* Timer Input Capture Holding Bit 1 */ - word BIT2 :1; /* Timer Input Capture Holding Bit 2 */ - word BIT3 :1; /* Timer Input Capture Holding Bit 3 */ - word BIT4 :1; /* Timer Input Capture Holding Bit 4 */ - word BIT5 :1; /* Timer Input Capture Holding Bit 5 */ - word BIT6 :1; /* Timer Input Capture Holding Bit 6 */ - word BIT7 :1; /* Timer Input Capture Holding Bit 7 */ - word BIT8 :1; /* Timer Input Capture Holding Bit 8 */ - word BIT9 :1; /* Timer Input Capture Holding Bit 9 */ - word BIT10 :1; /* Timer Input Capture Holding Bit 10 */ - word BIT11 :1; /* Timer Input Capture Holding Bit 11 */ - word BIT12 :1; /* Timer Input Capture Holding Bit 12 */ - word BIT13 :1; /* Timer Input Capture Holding Bit 13 */ - word BIT14 :1; /* Timer Input Capture Holding Bit 14 */ - word BIT15 :1; /* Timer Input Capture Holding Bit 15 */ - } Bits; - struct { - word grpBIT :16; - } MergedBits; -} TC2HSTR; -extern volatile TC2HSTR _TC2H @(REG_BASE + 0x0000007C); -#define TC2H _TC2H.Word -#define TC2H_BIT0 _TC2H.Bits.BIT0 -#define TC2H_BIT1 _TC2H.Bits.BIT1 -#define TC2H_BIT2 _TC2H.Bits.BIT2 -#define TC2H_BIT3 _TC2H.Bits.BIT3 -#define TC2H_BIT4 _TC2H.Bits.BIT4 -#define TC2H_BIT5 _TC2H.Bits.BIT5 -#define TC2H_BIT6 _TC2H.Bits.BIT6 -#define TC2H_BIT7 _TC2H.Bits.BIT7 -#define TC2H_BIT8 _TC2H.Bits.BIT8 -#define TC2H_BIT9 _TC2H.Bits.BIT9 -#define TC2H_BIT10 _TC2H.Bits.BIT10 -#define TC2H_BIT11 _TC2H.Bits.BIT11 -#define TC2H_BIT12 _TC2H.Bits.BIT12 -#define TC2H_BIT13 _TC2H.Bits.BIT13 -#define TC2H_BIT14 _TC2H.Bits.BIT14 -#define TC2H_BIT15 _TC2H.Bits.BIT15 -#define TC2H_BIT _TC2H.MergedBits.grpBIT - - -/*** TC3H - Timer Input Capture Holding Registers 3; 0x0000007E ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** TC3Hhi - Timer Input Capture Holding Registers 3 High; 0x0000007E ***/ - union { - byte Byte; - struct { - byte BIT8 :1; /* Timer Input Capture Holding Bit 8 */ - byte BIT9 :1; /* Timer Input Capture Holding Bit 9 */ - byte BIT10 :1; /* Timer Input Capture Holding Bit 10 */ - byte BIT11 :1; /* Timer Input Capture Holding Bit 11 */ - byte BIT12 :1; /* Timer Input Capture Holding Bit 12 */ - byte BIT13 :1; /* Timer Input Capture Holding Bit 13 */ - byte BIT14 :1; /* Timer Input Capture Holding Bit 14 */ - byte BIT15 :1; /* Timer Input Capture Holding Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; - } TC3HhiSTR; - #define TC3Hhi _TC3H.Overlap_STR.TC3HhiSTR.Byte - #define TC3Hhi_BIT8 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT8 - #define TC3Hhi_BIT9 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT9 - #define TC3Hhi_BIT10 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT10 - #define TC3Hhi_BIT11 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT11 - #define TC3Hhi_BIT12 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT12 - #define TC3Hhi_BIT13 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT13 - #define TC3Hhi_BIT14 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT14 - #define TC3Hhi_BIT15 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT15 - #define TC3Hhi_BIT_8 _TC3H.Overlap_STR.TC3HhiSTR.MergedBits.grpBIT_8 - #define TC3Hhi_BIT TC3Hhi_BIT_8 - - /*** TC3Hlo - Timer Input Capture Holding Registers 3 Low; 0x0000007F ***/ - union { - byte Byte; - struct { - byte BIT0 :1; /* Timer Input Capture Holding Bit 0 */ - byte BIT1 :1; /* Timer Input Capture Holding Bit 1 */ - byte BIT2 :1; /* Timer Input Capture Holding Bit 2 */ - byte BIT3 :1; /* Timer Input Capture Holding Bit 3 */ - byte BIT4 :1; /* Timer Input Capture Holding Bit 4 */ - byte BIT5 :1; /* Timer Input Capture Holding Bit 5 */ - byte BIT6 :1; /* Timer Input Capture Holding Bit 6 */ - byte BIT7 :1; /* Timer Input Capture Holding Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; - } TC3HloSTR; - #define TC3Hlo _TC3H.Overlap_STR.TC3HloSTR.Byte - #define TC3Hlo_BIT0 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT0 - #define TC3Hlo_BIT1 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT1 - #define TC3Hlo_BIT2 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT2 - #define TC3Hlo_BIT3 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT3 - #define TC3Hlo_BIT4 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT4 - #define TC3Hlo_BIT5 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT5 - #define TC3Hlo_BIT6 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT6 - #define TC3Hlo_BIT7 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT7 - #define TC3Hlo_BIT _TC3H.Overlap_STR.TC3HloSTR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word BIT0 :1; /* Timer Input Capture Holding Bit 0 */ - word BIT1 :1; /* Timer Input Capture Holding Bit 1 */ - word BIT2 :1; /* Timer Input Capture Holding Bit 2 */ - word BIT3 :1; /* Timer Input Capture Holding Bit 3 */ - word BIT4 :1; /* Timer Input Capture Holding Bit 4 */ - word BIT5 :1; /* Timer Input Capture Holding Bit 5 */ - word BIT6 :1; /* Timer Input Capture Holding Bit 6 */ - word BIT7 :1; /* Timer Input Capture Holding Bit 7 */ - word BIT8 :1; /* Timer Input Capture Holding Bit 8 */ - word BIT9 :1; /* Timer Input Capture Holding Bit 9 */ - word BIT10 :1; /* Timer Input Capture Holding Bit 10 */ - word BIT11 :1; /* Timer Input Capture Holding Bit 11 */ - word BIT12 :1; /* Timer Input Capture Holding Bit 12 */ - word BIT13 :1; /* Timer Input Capture Holding Bit 13 */ - word BIT14 :1; /* Timer Input Capture Holding Bit 14 */ - word BIT15 :1; /* Timer Input Capture Holding Bit 15 */ - } Bits; - struct { - word grpBIT :16; - } MergedBits; -} TC3HSTR; -extern volatile TC3HSTR _TC3H @(REG_BASE + 0x0000007E); -#define TC3H _TC3H.Word -#define TC3H_BIT0 _TC3H.Bits.BIT0 -#define TC3H_BIT1 _TC3H.Bits.BIT1 -#define TC3H_BIT2 _TC3H.Bits.BIT2 -#define TC3H_BIT3 _TC3H.Bits.BIT3 -#define TC3H_BIT4 _TC3H.Bits.BIT4 -#define TC3H_BIT5 _TC3H.Bits.BIT5 -#define TC3H_BIT6 _TC3H.Bits.BIT6 -#define TC3H_BIT7 _TC3H.Bits.BIT7 -#define TC3H_BIT8 _TC3H.Bits.BIT8 -#define TC3H_BIT9 _TC3H.Bits.BIT9 -#define TC3H_BIT10 _TC3H.Bits.BIT10 -#define TC3H_BIT11 _TC3H.Bits.BIT11 -#define TC3H_BIT12 _TC3H.Bits.BIT12 -#define TC3H_BIT13 _TC3H.Bits.BIT13 -#define TC3H_BIT14 _TC3H.Bits.BIT14 -#define TC3H_BIT15 _TC3H.Bits.BIT15 -#define TC3H_BIT _TC3H.MergedBits.grpBIT - - -/*** ATD0CTL23 - ATD 0 Control Register 23; 0x00000082 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** ATD0CTL2 - ATD 0 Control Register 2; 0x00000082 ***/ - union { - byte Byte; - struct { - byte ASCIF :1; /* ATD 0 Sequence Complete Interrupt Flag */ - byte ASCIE :1; /* ATD 0 Sequence Complete Interrupt Enable */ - byte ETRIGE :1; /* External Trigger Mode enable */ - byte ETRIGP :1; /* External Trigger Polarity */ - byte ETRIGLE :1; /* External Trigger Level/Edge control */ - byte AWAI :1; /* ATD 0 Wait Mode */ - byte AFFC :1; /* ATD 0 Fast Conversion Complete Flag Clear */ - byte ADPU :1; /* ATD 0 Disable / Power Down */ - } Bits; - } ATD0CTL2STR; - #define ATD0CTL2 _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Byte - #define ATD0CTL2_ASCIF _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ASCIF - #define ATD0CTL2_ASCIE _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ASCIE - #define ATD0CTL2_ETRIGE _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ETRIGE - #define ATD0CTL2_ETRIGP _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ETRIGP - #define ATD0CTL2_ETRIGLE _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ETRIGLE - #define ATD0CTL2_AWAI _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.AWAI - #define ATD0CTL2_AFFC _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.AFFC - #define ATD0CTL2_ADPU _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ADPU - - /*** ATD0CTL3 - ATD 0 Control Register 3; 0x00000083 ***/ - union { - byte Byte; - struct { - byte FRZ0 :1; /* Background Debug Freeze Enable */ - byte FRZ1 :1; /* Background Debug Freeze Enable */ - byte FIFO :1; /* Result Register FIFO Mode */ - byte S1C :1; /* Conversion Sequence Length 1 */ - byte S2C :1; /* Conversion Sequence Length 2 */ - byte S4C :1; /* Conversion Sequence Length 4 */ - byte S8C :1; /* Conversion Sequence Length 8 */ - byte :1; - } Bits; - struct { - byte grpFRZ :2; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; - } ATD0CTL3STR; - #define ATD0CTL3 _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Byte - #define ATD0CTL3_FRZ0 _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.FRZ0 - #define ATD0CTL3_FRZ1 _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.FRZ1 - #define ATD0CTL3_FIFO _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.FIFO - #define ATD0CTL3_S1C _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.S1C - #define ATD0CTL3_S2C _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.S2C - #define ATD0CTL3_S4C _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.S4C - #define ATD0CTL3_S8C _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.S8C - #define ATD0CTL3_FRZ _ATD0CTL23.Overlap_STR.ATD0CTL3STR.MergedBits.grpFRZ - - } Overlap_STR; - - struct { - word FRZ0 :1; /* Background Debug Freeze Enable */ - word FRZ1 :1; /* Background Debug Freeze Enable */ - word FIFO :1; /* Result Register FIFO Mode */ - word S1C :1; /* Conversion Sequence Length 1 */ - word S2C :1; /* Conversion Sequence Length 2 */ - word S4C :1; /* Conversion Sequence Length 4 */ - word S8C :1; /* Conversion Sequence Length 8 */ - word :1; - word ASCIF :1; /* ATD 0 Sequence Complete Interrupt Flag */ - word ASCIE :1; /* ATD 0 Sequence Complete Interrupt Enable */ - word ETRIGE :1; /* External Trigger Mode enable */ - word ETRIGP :1; /* External Trigger Polarity */ - word ETRIGLE :1; /* External Trigger Level/Edge control */ - word AWAI :1; /* ATD 0 Wait Mode */ - word AFFC :1; /* ATD 0 Fast Conversion Complete Flag Clear */ - word ADPU :1; /* ATD 0 Disable / Power Down */ - } Bits; - struct { - word grpFRZ :2; - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - } MergedBits; -} ATD0CTL23STR; -extern volatile ATD0CTL23STR _ATD0CTL23 @(REG_BASE + 0x00000082); -#define ATD0CTL23 _ATD0CTL23.Word -#define ATD0CTL23_FRZ0 _ATD0CTL23.Bits.FRZ0 -#define ATD0CTL23_FRZ1 _ATD0CTL23.Bits.FRZ1 -#define ATD0CTL23_FIFO _ATD0CTL23.Bits.FIFO -#define ATD0CTL23_S1C _ATD0CTL23.Bits.S1C -#define ATD0CTL23_S2C _ATD0CTL23.Bits.S2C -#define ATD0CTL23_S4C _ATD0CTL23.Bits.S4C -#define ATD0CTL23_S8C _ATD0CTL23.Bits.S8C -#define ATD0CTL23_ASCIF _ATD0CTL23.Bits.ASCIF -#define ATD0CTL23_ASCIE _ATD0CTL23.Bits.ASCIE -#define ATD0CTL23_ETRIGE _ATD0CTL23.Bits.ETRIGE -#define ATD0CTL23_ETRIGP _ATD0CTL23.Bits.ETRIGP -#define ATD0CTL23_ETRIGLE _ATD0CTL23.Bits.ETRIGLE -#define ATD0CTL23_AWAI _ATD0CTL23.Bits.AWAI -#define ATD0CTL23_AFFC _ATD0CTL23.Bits.AFFC -#define ATD0CTL23_ADPU _ATD0CTL23.Bits.ADPU -#define ATD0CTL23_FRZ _ATD0CTL23.MergedBits.grpFRZ - - -/*** ATD0CTL45 - ATD 0 Control Register 45; 0x00000084 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** ATD0CTL4 - ATD 0 Control Register 4; 0x00000084 ***/ - union { - byte Byte; - struct { - byte PRS0 :1; /* ATD 0 Clock Prescaler 0 */ - byte PRS1 :1; /* ATD 0 Clock Prescaler 1 */ - byte PRS2 :1; /* ATD 0 Clock Prescaler 2 */ - byte PRS3 :1; /* ATD 0 Clock Prescaler 3 */ - byte PRS4 :1; /* ATD 0 Clock Prescaler 4 */ - byte SMP0 :1; /* Sample Time Select 0 */ - byte SMP1 :1; /* Sample Time Select 1 */ - byte SRES8 :1; /* ATD 0 Resolution Select */ - } Bits; - struct { - byte grpPRS :5; - byte grpSMP :2; - byte grpSRES_8 :1; - } MergedBits; - } ATD0CTL4STR; - #define ATD0CTL4 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Byte - #define ATD0CTL4_PRS0 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.PRS0 - #define ATD0CTL4_PRS1 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.PRS1 - #define ATD0CTL4_PRS2 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.PRS2 - #define ATD0CTL4_PRS3 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.PRS3 - #define ATD0CTL4_PRS4 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.PRS4 - #define ATD0CTL4_SMP0 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.SMP0 - #define ATD0CTL4_SMP1 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.SMP1 - #define ATD0CTL4_SRES8 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.SRES8 - #define ATD0CTL4_PRS _ATD0CTL45.Overlap_STR.ATD0CTL4STR.MergedBits.grpPRS - #define ATD0CTL4_SMP _ATD0CTL45.Overlap_STR.ATD0CTL4STR.MergedBits.grpSMP - - /*** ATD0CTL5 - ATD 0 Control Register 5; 0x00000085 ***/ - union { - byte Byte; - struct { - byte CA :1; /* Analog Input Channel Select Code A */ - byte CB :1; /* Analog Input Channel Select Code B */ - byte CC :1; /* Analog Input Channel Select Code C */ - byte :1; - byte MULT :1; /* Multi-Channel Sample Mode */ - byte SCAN :1; /* Continuous Conversion Sequence Mode */ - byte DSGN :1; /* Signed/Unsigned Result Data Mode */ - byte DJM :1; /* Result Register Data Justification Mode */ - } Bits; - } ATD0CTL5STR; - #define ATD0CTL5 _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Byte - #define ATD0CTL5_CA _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.CA - #define ATD0CTL5_CB _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.CB - #define ATD0CTL5_CC _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.CC - #define ATD0CTL5_MULT _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.MULT - #define ATD0CTL5_SCAN _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.SCAN - #define ATD0CTL5_DSGN _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.DSGN - #define ATD0CTL5_DJM _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.DJM - - } Overlap_STR; - - struct { - word CA :1; /* Analog Input Channel Select Code A */ - word CB :1; /* Analog Input Channel Select Code B */ - word CC :1; /* Analog Input Channel Select Code C */ - word :1; - word MULT :1; /* Multi-Channel Sample Mode */ - word SCAN :1; /* Continuous Conversion Sequence Mode */ - word DSGN :1; /* Signed/Unsigned Result Data Mode */ - word DJM :1; /* Result Register Data Justification Mode */ - word PRS0 :1; /* ATD 0 Clock Prescaler 0 */ - word PRS1 :1; /* ATD 0 Clock Prescaler 1 */ - word PRS2 :1; /* ATD 0 Clock Prescaler 2 */ - word PRS3 :1; /* ATD 0 Clock Prescaler 3 */ - word PRS4 :1; /* ATD 0 Clock Prescaler 4 */ - word SMP0 :1; /* Sample Time Select 0 */ - word SMP1 :1; /* Sample Time Select 1 */ - word SRES8 :1; /* ATD 0 Resolution Select */ - } Bits; - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word grpPRS :5; - word grpSMP :2; - word grpSRES_8 :1; - } MergedBits; -} ATD0CTL45STR; -extern volatile ATD0CTL45STR _ATD0CTL45 @(REG_BASE + 0x00000084); -#define ATD0CTL45 _ATD0CTL45.Word -#define ATD0CTL45_CA _ATD0CTL45.Bits.CA -#define ATD0CTL45_CB _ATD0CTL45.Bits.CB -#define ATD0CTL45_CC _ATD0CTL45.Bits.CC -#define ATD0CTL45_MULT _ATD0CTL45.Bits.MULT -#define ATD0CTL45_SCAN _ATD0CTL45.Bits.SCAN -#define ATD0CTL45_DSGN _ATD0CTL45.Bits.DSGN -#define ATD0CTL45_DJM _ATD0CTL45.Bits.DJM -#define ATD0CTL45_PRS0 _ATD0CTL45.Bits.PRS0 -#define ATD0CTL45_PRS1 _ATD0CTL45.Bits.PRS1 -#define ATD0CTL45_PRS2 _ATD0CTL45.Bits.PRS2 -#define ATD0CTL45_PRS3 _ATD0CTL45.Bits.PRS3 -#define ATD0CTL45_PRS4 _ATD0CTL45.Bits.PRS4 -#define ATD0CTL45_SMP0 _ATD0CTL45.Bits.SMP0 -#define ATD0CTL45_SMP1 _ATD0CTL45.Bits.SMP1 -#define ATD0CTL45_SRES8 _ATD0CTL45.Bits.SRES8 -#define ATD0CTL45_PRS _ATD0CTL45.MergedBits.grpPRS -#define ATD0CTL45_SMP _ATD0CTL45.MergedBits.grpSMP - - -/*** ATD0DR0 - ATD 0 Conversion Result Register 0; 0x00000090 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** ATD0DR0H - ATD 0 Conversion Result Register 0 High; 0x00000090 ***/ - union { - byte Byte; - struct { - byte BIT8 :1; /* Bit 8 */ - byte BIT9 :1; /* Bit 9 */ - byte BIT10 :1; /* Bit 10 */ - byte BIT11 :1; /* Bit 11 */ - byte BIT12 :1; /* Bit 12 */ - byte BIT13 :1; /* Bit 13 */ - byte BIT14 :1; /* Bit 14 */ - byte BIT15 :1; /* Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; - } ATD0DR0HSTR; - #define ATD0DR0H _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Byte - #define ATD0DR0H_BIT8 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT8 - #define ATD0DR0H_BIT9 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT9 - #define ATD0DR0H_BIT10 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT10 - #define ATD0DR0H_BIT11 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT11 - #define ATD0DR0H_BIT12 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT12 - #define ATD0DR0H_BIT13 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT13 - #define ATD0DR0H_BIT14 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT14 - #define ATD0DR0H_BIT15 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT15 - #define ATD0DR0H_BIT_8 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.MergedBits.grpBIT_8 - #define ATD0DR0H_BIT ATD0DR0H_BIT_8 - - /*** ATD0DR0L - ATD 0 Conversion Result Register 0 Low; 0x00000091 ***/ - union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte BIT6 :1; /* Bit 6 */ - byte BIT7 :1; /* Bit 7 */ - } Bits; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte grpBIT_6 :2; - } MergedBits; - } ATD0DR0LSTR; - #define ATD0DR0L _ATD0DR0.Overlap_STR.ATD0DR0LSTR.Byte - #define ATD0DR0L_BIT6 _ATD0DR0.Overlap_STR.ATD0DR0LSTR.Bits.BIT6 - #define ATD0DR0L_BIT7 _ATD0DR0.Overlap_STR.ATD0DR0LSTR.Bits.BIT7 - #define ATD0DR0L_BIT_6 _ATD0DR0.Overlap_STR.ATD0DR0LSTR.MergedBits.grpBIT_6 - #define ATD0DR0L_BIT ATD0DR0L_BIT_6 - - } Overlap_STR; - - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word BIT6 :1; /* Bit 6 */ - word BIT7 :1; /* Bit 7 */ - word BIT8 :1; /* Bit 8 */ - word BIT9 :1; /* Bit 9 */ - word BIT10 :1; /* Bit 10 */ - word BIT11 :1; /* Bit 11 */ - word BIT12 :1; /* Bit 12 */ - word BIT13 :1; /* Bit 13 */ - word BIT14 :1; /* Bit 14 */ - word BIT15 :1; /* Bit 15 */ - } Bits; - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word grpBIT_6 :10; - } MergedBits; -} ATD0DR0STR; -extern volatile ATD0DR0STR _ATD0DR0 @(REG_BASE + 0x00000090); -#define ATD0DR0 _ATD0DR0.Word -#define ATD0DR0_BIT6 _ATD0DR0.Bits.BIT6 -#define ATD0DR0_BIT7 _ATD0DR0.Bits.BIT7 -#define ATD0DR0_BIT8 _ATD0DR0.Bits.BIT8 -#define ATD0DR0_BIT9 _ATD0DR0.Bits.BIT9 -#define ATD0DR0_BIT10 _ATD0DR0.Bits.BIT10 -#define ATD0DR0_BIT11 _ATD0DR0.Bits.BIT11 -#define ATD0DR0_BIT12 _ATD0DR0.Bits.BIT12 -#define ATD0DR0_BIT13 _ATD0DR0.Bits.BIT13 -#define ATD0DR0_BIT14 _ATD0DR0.Bits.BIT14 -#define ATD0DR0_BIT15 _ATD0DR0.Bits.BIT15 -#define ATD0DR0_BIT_6 _ATD0DR0.MergedBits.grpBIT_6 -#define ATD0DR0_BIT ATD0DR0_BIT_6 - - -/*** ATD0DR1 - ATD 0 Conversion Result Register 1; 0x00000092 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** ATD0DR1H - ATD 0 Conversion Result Register 1 High; 0x00000092 ***/ - union { - byte Byte; - struct { - byte BIT8 :1; /* Bit 8 */ - byte BIT9 :1; /* Bit 9 */ - byte BIT10 :1; /* Bit 10 */ - byte BIT11 :1; /* Bit 11 */ - byte BIT12 :1; /* Bit 12 */ - byte BIT13 :1; /* Bit 13 */ - byte BIT14 :1; /* Bit 14 */ - byte BIT15 :1; /* Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; - } ATD0DR1HSTR; - #define ATD0DR1H _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Byte - #define ATD0DR1H_BIT8 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT8 - #define ATD0DR1H_BIT9 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT9 - #define ATD0DR1H_BIT10 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT10 - #define ATD0DR1H_BIT11 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT11 - #define ATD0DR1H_BIT12 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT12 - #define ATD0DR1H_BIT13 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT13 - #define ATD0DR1H_BIT14 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT14 - #define ATD0DR1H_BIT15 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT15 - #define ATD0DR1H_BIT_8 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.MergedBits.grpBIT_8 - #define ATD0DR1H_BIT ATD0DR1H_BIT_8 - - /*** ATD0DR1L - ATD 0 Conversion Result Register 1 Low; 0x00000093 ***/ - union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte BIT6 :1; /* Bit 6 */ - byte BIT7 :1; /* Bit 7 */ - } Bits; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte grpBIT_6 :2; - } MergedBits; - } ATD0DR1LSTR; - #define ATD0DR1L _ATD0DR1.Overlap_STR.ATD0DR1LSTR.Byte - #define ATD0DR1L_BIT6 _ATD0DR1.Overlap_STR.ATD0DR1LSTR.Bits.BIT6 - #define ATD0DR1L_BIT7 _ATD0DR1.Overlap_STR.ATD0DR1LSTR.Bits.BIT7 - #define ATD0DR1L_BIT_6 _ATD0DR1.Overlap_STR.ATD0DR1LSTR.MergedBits.grpBIT_6 - #define ATD0DR1L_BIT ATD0DR1L_BIT_6 - - } Overlap_STR; - - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word BIT6 :1; /* Bit 6 */ - word BIT7 :1; /* Bit 7 */ - word BIT8 :1; /* Bit 8 */ - word BIT9 :1; /* Bit 9 */ - word BIT10 :1; /* Bit 10 */ - word BIT11 :1; /* Bit 11 */ - word BIT12 :1; /* Bit 12 */ - word BIT13 :1; /* Bit 13 */ - word BIT14 :1; /* Bit 14 */ - word BIT15 :1; /* Bit 15 */ - } Bits; - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word grpBIT_6 :10; - } MergedBits; -} ATD0DR1STR; -extern volatile ATD0DR1STR _ATD0DR1 @(REG_BASE + 0x00000092); -#define ATD0DR1 _ATD0DR1.Word -#define ATD0DR1_BIT6 _ATD0DR1.Bits.BIT6 -#define ATD0DR1_BIT7 _ATD0DR1.Bits.BIT7 -#define ATD0DR1_BIT8 _ATD0DR1.Bits.BIT8 -#define ATD0DR1_BIT9 _ATD0DR1.Bits.BIT9 -#define ATD0DR1_BIT10 _ATD0DR1.Bits.BIT10 -#define ATD0DR1_BIT11 _ATD0DR1.Bits.BIT11 -#define ATD0DR1_BIT12 _ATD0DR1.Bits.BIT12 -#define ATD0DR1_BIT13 _ATD0DR1.Bits.BIT13 -#define ATD0DR1_BIT14 _ATD0DR1.Bits.BIT14 -#define ATD0DR1_BIT15 _ATD0DR1.Bits.BIT15 -#define ATD0DR1_BIT_6 _ATD0DR1.MergedBits.grpBIT_6 -#define ATD0DR1_BIT ATD0DR1_BIT_6 - - -/*** ATD0DR2 - ATD 0 Conversion Result Register 2; 0x00000094 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** ATD0DR2H - ATD 0 Conversion Result Register 2 High; 0x00000094 ***/ - union { - byte Byte; - struct { - byte BIT8 :1; /* Bit 8 */ - byte BIT9 :1; /* Bit 9 */ - byte BIT10 :1; /* Bit 10 */ - byte BIT11 :1; /* Bit 11 */ - byte BIT12 :1; /* Bit 12 */ - byte BIT13 :1; /* Bit 13 */ - byte BIT14 :1; /* Bit 14 */ - byte BIT15 :1; /* Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; - } ATD0DR2HSTR; - #define ATD0DR2H _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Byte - #define ATD0DR2H_BIT8 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT8 - #define ATD0DR2H_BIT9 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT9 - #define ATD0DR2H_BIT10 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT10 - #define ATD0DR2H_BIT11 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT11 - #define ATD0DR2H_BIT12 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT12 - #define ATD0DR2H_BIT13 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT13 - #define ATD0DR2H_BIT14 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT14 - #define ATD0DR2H_BIT15 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT15 - #define ATD0DR2H_BIT_8 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.MergedBits.grpBIT_8 - #define ATD0DR2H_BIT ATD0DR2H_BIT_8 - - /*** ATD0DR2L - ATD 0 Conversion Result Register 2 Low; 0x00000095 ***/ - union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte BIT6 :1; /* Bit 6 */ - byte BIT7 :1; /* Bit 7 */ - } Bits; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte grpBIT_6 :2; - } MergedBits; - } ATD0DR2LSTR; - #define ATD0DR2L _ATD0DR2.Overlap_STR.ATD0DR2LSTR.Byte - #define ATD0DR2L_BIT6 _ATD0DR2.Overlap_STR.ATD0DR2LSTR.Bits.BIT6 - #define ATD0DR2L_BIT7 _ATD0DR2.Overlap_STR.ATD0DR2LSTR.Bits.BIT7 - #define ATD0DR2L_BIT_6 _ATD0DR2.Overlap_STR.ATD0DR2LSTR.MergedBits.grpBIT_6 - #define ATD0DR2L_BIT ATD0DR2L_BIT_6 - - } Overlap_STR; - - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word BIT6 :1; /* Bit 6 */ - word BIT7 :1; /* Bit 7 */ - word BIT8 :1; /* Bit 8 */ - word BIT9 :1; /* Bit 9 */ - word BIT10 :1; /* Bit 10 */ - word BIT11 :1; /* Bit 11 */ - word BIT12 :1; /* Bit 12 */ - word BIT13 :1; /* Bit 13 */ - word BIT14 :1; /* Bit 14 */ - word BIT15 :1; /* Bit 15 */ - } Bits; - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word grpBIT_6 :10; - } MergedBits; -} ATD0DR2STR; -extern volatile ATD0DR2STR _ATD0DR2 @(REG_BASE + 0x00000094); -#define ATD0DR2 _ATD0DR2.Word -#define ATD0DR2_BIT6 _ATD0DR2.Bits.BIT6 -#define ATD0DR2_BIT7 _ATD0DR2.Bits.BIT7 -#define ATD0DR2_BIT8 _ATD0DR2.Bits.BIT8 -#define ATD0DR2_BIT9 _ATD0DR2.Bits.BIT9 -#define ATD0DR2_BIT10 _ATD0DR2.Bits.BIT10 -#define ATD0DR2_BIT11 _ATD0DR2.Bits.BIT11 -#define ATD0DR2_BIT12 _ATD0DR2.Bits.BIT12 -#define ATD0DR2_BIT13 _ATD0DR2.Bits.BIT13 -#define ATD0DR2_BIT14 _ATD0DR2.Bits.BIT14 -#define ATD0DR2_BIT15 _ATD0DR2.Bits.BIT15 -#define ATD0DR2_BIT_6 _ATD0DR2.MergedBits.grpBIT_6 -#define ATD0DR2_BIT ATD0DR2_BIT_6 - - -/*** ATD0DR3 - ATD 0 Conversion Result Register 3; 0x00000096 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** ATD0DR3H - ATD 0 Conversion Result Register 3 High; 0x00000096 ***/ - union { - byte Byte; - struct { - byte BIT8 :1; /* Bit 8 */ - byte BIT9 :1; /* Bit 9 */ - byte BIT10 :1; /* Bit 10 */ - byte BIT11 :1; /* Bit 11 */ - byte BIT12 :1; /* Bit 12 */ - byte BIT13 :1; /* Bit 13 */ - byte BIT14 :1; /* Bit 14 */ - byte BIT15 :1; /* Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; - } ATD0DR3HSTR; - #define ATD0DR3H _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Byte - #define ATD0DR3H_BIT8 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT8 - #define ATD0DR3H_BIT9 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT9 - #define ATD0DR3H_BIT10 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT10 - #define ATD0DR3H_BIT11 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT11 - #define ATD0DR3H_BIT12 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT12 - #define ATD0DR3H_BIT13 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT13 - #define ATD0DR3H_BIT14 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT14 - #define ATD0DR3H_BIT15 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT15 - #define ATD0DR3H_BIT_8 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.MergedBits.grpBIT_8 - #define ATD0DR3H_BIT ATD0DR3H_BIT_8 - - /*** ATD0DR3L - ATD 0 Conversion Result Register 3 Low; 0x00000097 ***/ - union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte BIT6 :1; /* Bit 6 */ - byte BIT7 :1; /* Bit 7 */ - } Bits; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte grpBIT_6 :2; - } MergedBits; - } ATD0DR3LSTR; - #define ATD0DR3L _ATD0DR3.Overlap_STR.ATD0DR3LSTR.Byte - #define ATD0DR3L_BIT6 _ATD0DR3.Overlap_STR.ATD0DR3LSTR.Bits.BIT6 - #define ATD0DR3L_BIT7 _ATD0DR3.Overlap_STR.ATD0DR3LSTR.Bits.BIT7 - #define ATD0DR3L_BIT_6 _ATD0DR3.Overlap_STR.ATD0DR3LSTR.MergedBits.grpBIT_6 - #define ATD0DR3L_BIT ATD0DR3L_BIT_6 - - } Overlap_STR; - - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word BIT6 :1; /* Bit 6 */ - word BIT7 :1; /* Bit 7 */ - word BIT8 :1; /* Bit 8 */ - word BIT9 :1; /* Bit 9 */ - word BIT10 :1; /* Bit 10 */ - word BIT11 :1; /* Bit 11 */ - word BIT12 :1; /* Bit 12 */ - word BIT13 :1; /* Bit 13 */ - word BIT14 :1; /* Bit 14 */ - word BIT15 :1; /* Bit 15 */ - } Bits; - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word grpBIT_6 :10; - } MergedBits; -} ATD0DR3STR; -extern volatile ATD0DR3STR _ATD0DR3 @(REG_BASE + 0x00000096); -#define ATD0DR3 _ATD0DR3.Word -#define ATD0DR3_BIT6 _ATD0DR3.Bits.BIT6 -#define ATD0DR3_BIT7 _ATD0DR3.Bits.BIT7 -#define ATD0DR3_BIT8 _ATD0DR3.Bits.BIT8 -#define ATD0DR3_BIT9 _ATD0DR3.Bits.BIT9 -#define ATD0DR3_BIT10 _ATD0DR3.Bits.BIT10 -#define ATD0DR3_BIT11 _ATD0DR3.Bits.BIT11 -#define ATD0DR3_BIT12 _ATD0DR3.Bits.BIT12 -#define ATD0DR3_BIT13 _ATD0DR3.Bits.BIT13 -#define ATD0DR3_BIT14 _ATD0DR3.Bits.BIT14 -#define ATD0DR3_BIT15 _ATD0DR3.Bits.BIT15 -#define ATD0DR3_BIT_6 _ATD0DR3.MergedBits.grpBIT_6 -#define ATD0DR3_BIT ATD0DR3_BIT_6 - - -/*** ATD0DR4 - ATD 0 Conversion Result Register 4; 0x00000098 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** ATD0DR4H - ATD 0 Conversion Result Register 4 High; 0x00000098 ***/ - union { - byte Byte; - struct { - byte BIT8 :1; /* Bit 8 */ - byte BIT9 :1; /* Bit 9 */ - byte BIT10 :1; /* Bit 10 */ - byte BIT11 :1; /* Bit 11 */ - byte BIT12 :1; /* Bit 12 */ - byte BIT13 :1; /* Bit 13 */ - byte BIT14 :1; /* Bit 14 */ - byte BIT15 :1; /* Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; - } ATD0DR4HSTR; - #define ATD0DR4H _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Byte - #define ATD0DR4H_BIT8 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT8 - #define ATD0DR4H_BIT9 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT9 - #define ATD0DR4H_BIT10 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT10 - #define ATD0DR4H_BIT11 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT11 - #define ATD0DR4H_BIT12 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT12 - #define ATD0DR4H_BIT13 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT13 - #define ATD0DR4H_BIT14 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT14 - #define ATD0DR4H_BIT15 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT15 - #define ATD0DR4H_BIT_8 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.MergedBits.grpBIT_8 - #define ATD0DR4H_BIT ATD0DR4H_BIT_8 - - /*** ATD0DR4L - ATD 0 Conversion Result Register 4 Low; 0x00000099 ***/ - union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte BIT6 :1; /* Bit 6 */ - byte BIT7 :1; /* Bit 7 */ - } Bits; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte grpBIT_6 :2; - } MergedBits; - } ATD0DR4LSTR; - #define ATD0DR4L _ATD0DR4.Overlap_STR.ATD0DR4LSTR.Byte - #define ATD0DR4L_BIT6 _ATD0DR4.Overlap_STR.ATD0DR4LSTR.Bits.BIT6 - #define ATD0DR4L_BIT7 _ATD0DR4.Overlap_STR.ATD0DR4LSTR.Bits.BIT7 - #define ATD0DR4L_BIT_6 _ATD0DR4.Overlap_STR.ATD0DR4LSTR.MergedBits.grpBIT_6 - #define ATD0DR4L_BIT ATD0DR4L_BIT_6 - - } Overlap_STR; - - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word BIT6 :1; /* Bit 6 */ - word BIT7 :1; /* Bit 7 */ - word BIT8 :1; /* Bit 8 */ - word BIT9 :1; /* Bit 9 */ - word BIT10 :1; /* Bit 10 */ - word BIT11 :1; /* Bit 11 */ - word BIT12 :1; /* Bit 12 */ - word BIT13 :1; /* Bit 13 */ - word BIT14 :1; /* Bit 14 */ - word BIT15 :1; /* Bit 15 */ - } Bits; - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word grpBIT_6 :10; - } MergedBits; -} ATD0DR4STR; -extern volatile ATD0DR4STR _ATD0DR4 @(REG_BASE + 0x00000098); -#define ATD0DR4 _ATD0DR4.Word -#define ATD0DR4_BIT6 _ATD0DR4.Bits.BIT6 -#define ATD0DR4_BIT7 _ATD0DR4.Bits.BIT7 -#define ATD0DR4_BIT8 _ATD0DR4.Bits.BIT8 -#define ATD0DR4_BIT9 _ATD0DR4.Bits.BIT9 -#define ATD0DR4_BIT10 _ATD0DR4.Bits.BIT10 -#define ATD0DR4_BIT11 _ATD0DR4.Bits.BIT11 -#define ATD0DR4_BIT12 _ATD0DR4.Bits.BIT12 -#define ATD0DR4_BIT13 _ATD0DR4.Bits.BIT13 -#define ATD0DR4_BIT14 _ATD0DR4.Bits.BIT14 -#define ATD0DR4_BIT15 _ATD0DR4.Bits.BIT15 -#define ATD0DR4_BIT_6 _ATD0DR4.MergedBits.grpBIT_6 -#define ATD0DR4_BIT ATD0DR4_BIT_6 - - -/*** ATD0DR5 - ATD 0 Conversion Result Register 5; 0x0000009A ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** ATD0DR5H - ATD 0 Conversion Result Register 5 High; 0x0000009A ***/ - union { - byte Byte; - struct { - byte BIT8 :1; /* Bit 8 */ - byte BIT9 :1; /* Bit 9 */ - byte BIT10 :1; /* Bit 10 */ - byte BIT11 :1; /* Bit 11 */ - byte BIT12 :1; /* Bit 12 */ - byte BIT13 :1; /* Bit 13 */ - byte BIT14 :1; /* Bit 14 */ - byte BIT15 :1; /* Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; - } ATD0DR5HSTR; - #define ATD0DR5H _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Byte - #define ATD0DR5H_BIT8 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT8 - #define ATD0DR5H_BIT9 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT9 - #define ATD0DR5H_BIT10 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT10 - #define ATD0DR5H_BIT11 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT11 - #define ATD0DR5H_BIT12 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT12 - #define ATD0DR5H_BIT13 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT13 - #define ATD0DR5H_BIT14 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT14 - #define ATD0DR5H_BIT15 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT15 - #define ATD0DR5H_BIT_8 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.MergedBits.grpBIT_8 - #define ATD0DR5H_BIT ATD0DR5H_BIT_8 - - /*** ATD0DR5L - ATD 0 Conversion Result Register 5 Low; 0x0000009B ***/ - union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte BIT6 :1; /* Bit 6 */ - byte BIT7 :1; /* Bit 7 */ - } Bits; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte grpBIT_6 :2; - } MergedBits; - } ATD0DR5LSTR; - #define ATD0DR5L _ATD0DR5.Overlap_STR.ATD0DR5LSTR.Byte - #define ATD0DR5L_BIT6 _ATD0DR5.Overlap_STR.ATD0DR5LSTR.Bits.BIT6 - #define ATD0DR5L_BIT7 _ATD0DR5.Overlap_STR.ATD0DR5LSTR.Bits.BIT7 - #define ATD0DR5L_BIT_6 _ATD0DR5.Overlap_STR.ATD0DR5LSTR.MergedBits.grpBIT_6 - #define ATD0DR5L_BIT ATD0DR5L_BIT_6 - - } Overlap_STR; - - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word BIT6 :1; /* Bit 6 */ - word BIT7 :1; /* Bit 7 */ - word BIT8 :1; /* Bit 8 */ - word BIT9 :1; /* Bit 9 */ - word BIT10 :1; /* Bit 10 */ - word BIT11 :1; /* Bit 11 */ - word BIT12 :1; /* Bit 12 */ - word BIT13 :1; /* Bit 13 */ - word BIT14 :1; /* Bit 14 */ - word BIT15 :1; /* Bit 15 */ - } Bits; - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word grpBIT_6 :10; - } MergedBits; -} ATD0DR5STR; -extern volatile ATD0DR5STR _ATD0DR5 @(REG_BASE + 0x0000009A); -#define ATD0DR5 _ATD0DR5.Word -#define ATD0DR5_BIT6 _ATD0DR5.Bits.BIT6 -#define ATD0DR5_BIT7 _ATD0DR5.Bits.BIT7 -#define ATD0DR5_BIT8 _ATD0DR5.Bits.BIT8 -#define ATD0DR5_BIT9 _ATD0DR5.Bits.BIT9 -#define ATD0DR5_BIT10 _ATD0DR5.Bits.BIT10 -#define ATD0DR5_BIT11 _ATD0DR5.Bits.BIT11 -#define ATD0DR5_BIT12 _ATD0DR5.Bits.BIT12 -#define ATD0DR5_BIT13 _ATD0DR5.Bits.BIT13 -#define ATD0DR5_BIT14 _ATD0DR5.Bits.BIT14 -#define ATD0DR5_BIT15 _ATD0DR5.Bits.BIT15 -#define ATD0DR5_BIT_6 _ATD0DR5.MergedBits.grpBIT_6 -#define ATD0DR5_BIT ATD0DR5_BIT_6 - - -/*** ATD0DR6 - ATD 0 Conversion Result Register 6; 0x0000009C ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** ATD0DR6H - ATD 0 Conversion Result Register 6 High; 0x0000009C ***/ - union { - byte Byte; - struct { - byte BIT8 :1; /* Bit 8 */ - byte BIT9 :1; /* Bit 9 */ - byte BIT10 :1; /* Bit 10 */ - byte BIT11 :1; /* Bit 11 */ - byte BIT12 :1; /* Bit 12 */ - byte BIT13 :1; /* Bit 13 */ - byte BIT14 :1; /* Bit 14 */ - byte BIT15 :1; /* Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; - } ATD0DR6HSTR; - #define ATD0DR6H _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Byte - #define ATD0DR6H_BIT8 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT8 - #define ATD0DR6H_BIT9 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT9 - #define ATD0DR6H_BIT10 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT10 - #define ATD0DR6H_BIT11 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT11 - #define ATD0DR6H_BIT12 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT12 - #define ATD0DR6H_BIT13 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT13 - #define ATD0DR6H_BIT14 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT14 - #define ATD0DR6H_BIT15 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT15 - #define ATD0DR6H_BIT_8 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.MergedBits.grpBIT_8 - #define ATD0DR6H_BIT ATD0DR6H_BIT_8 - - /*** ATD0DR6L - ATD 0 Conversion Result Register 6 Low; 0x0000009D ***/ - union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte BIT6 :1; /* Bit 6 */ - byte BIT7 :1; /* Bit 7 */ - } Bits; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte grpBIT_6 :2; - } MergedBits; - } ATD0DR6LSTR; - #define ATD0DR6L _ATD0DR6.Overlap_STR.ATD0DR6LSTR.Byte - #define ATD0DR6L_BIT6 _ATD0DR6.Overlap_STR.ATD0DR6LSTR.Bits.BIT6 - #define ATD0DR6L_BIT7 _ATD0DR6.Overlap_STR.ATD0DR6LSTR.Bits.BIT7 - #define ATD0DR6L_BIT_6 _ATD0DR6.Overlap_STR.ATD0DR6LSTR.MergedBits.grpBIT_6 - #define ATD0DR6L_BIT ATD0DR6L_BIT_6 - - } Overlap_STR; - - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word BIT6 :1; /* Bit 6 */ - word BIT7 :1; /* Bit 7 */ - word BIT8 :1; /* Bit 8 */ - word BIT9 :1; /* Bit 9 */ - word BIT10 :1; /* Bit 10 */ - word BIT11 :1; /* Bit 11 */ - word BIT12 :1; /* Bit 12 */ - word BIT13 :1; /* Bit 13 */ - word BIT14 :1; /* Bit 14 */ - word BIT15 :1; /* Bit 15 */ - } Bits; - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word grpBIT_6 :10; - } MergedBits; -} ATD0DR6STR; -extern volatile ATD0DR6STR _ATD0DR6 @(REG_BASE + 0x0000009C); -#define ATD0DR6 _ATD0DR6.Word -#define ATD0DR6_BIT6 _ATD0DR6.Bits.BIT6 -#define ATD0DR6_BIT7 _ATD0DR6.Bits.BIT7 -#define ATD0DR6_BIT8 _ATD0DR6.Bits.BIT8 -#define ATD0DR6_BIT9 _ATD0DR6.Bits.BIT9 -#define ATD0DR6_BIT10 _ATD0DR6.Bits.BIT10 -#define ATD0DR6_BIT11 _ATD0DR6.Bits.BIT11 -#define ATD0DR6_BIT12 _ATD0DR6.Bits.BIT12 -#define ATD0DR6_BIT13 _ATD0DR6.Bits.BIT13 -#define ATD0DR6_BIT14 _ATD0DR6.Bits.BIT14 -#define ATD0DR6_BIT15 _ATD0DR6.Bits.BIT15 -#define ATD0DR6_BIT_6 _ATD0DR6.MergedBits.grpBIT_6 -#define ATD0DR6_BIT ATD0DR6_BIT_6 - - -/*** ATD0DR7 - ATD 0 Conversion Result Register 7; 0x0000009E ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** ATD0DR7H - ATD 0 Conversion Result Register 7 High; 0x0000009E ***/ - union { - byte Byte; - struct { - byte BIT8 :1; /* Bit 8 */ - byte BIT9 :1; /* Bit 9 */ - byte BIT10 :1; /* Bit 10 */ - byte BIT11 :1; /* Bit 11 */ - byte BIT12 :1; /* Bit 12 */ - byte BIT13 :1; /* Bit 13 */ - byte BIT14 :1; /* Bit 14 */ - byte BIT15 :1; /* Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; - } ATD0DR7HSTR; - #define ATD0DR7H _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Byte - #define ATD0DR7H_BIT8 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT8 - #define ATD0DR7H_BIT9 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT9 - #define ATD0DR7H_BIT10 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT10 - #define ATD0DR7H_BIT11 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT11 - #define ATD0DR7H_BIT12 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT12 - #define ATD0DR7H_BIT13 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT13 - #define ATD0DR7H_BIT14 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT14 - #define ATD0DR7H_BIT15 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT15 - #define ATD0DR7H_BIT_8 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.MergedBits.grpBIT_8 - #define ATD0DR7H_BIT ATD0DR7H_BIT_8 - - /*** ATD0DR7L - ATD 0 Conversion Result Register 7 Low; 0x0000009F ***/ - union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte BIT6 :1; /* Bit 6 */ - byte BIT7 :1; /* Bit 7 */ - } Bits; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte grpBIT_6 :2; - } MergedBits; - } ATD0DR7LSTR; - #define ATD0DR7L _ATD0DR7.Overlap_STR.ATD0DR7LSTR.Byte - #define ATD0DR7L_BIT6 _ATD0DR7.Overlap_STR.ATD0DR7LSTR.Bits.BIT6 - #define ATD0DR7L_BIT7 _ATD0DR7.Overlap_STR.ATD0DR7LSTR.Bits.BIT7 - #define ATD0DR7L_BIT_6 _ATD0DR7.Overlap_STR.ATD0DR7LSTR.MergedBits.grpBIT_6 - #define ATD0DR7L_BIT ATD0DR7L_BIT_6 - - } Overlap_STR; - - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word BIT6 :1; /* Bit 6 */ - word BIT7 :1; /* Bit 7 */ - word BIT8 :1; /* Bit 8 */ - word BIT9 :1; /* Bit 9 */ - word BIT10 :1; /* Bit 10 */ - word BIT11 :1; /* Bit 11 */ - word BIT12 :1; /* Bit 12 */ - word BIT13 :1; /* Bit 13 */ - word BIT14 :1; /* Bit 14 */ - word BIT15 :1; /* Bit 15 */ - } Bits; - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word grpBIT_6 :10; - } MergedBits; -} ATD0DR7STR; -extern volatile ATD0DR7STR _ATD0DR7 @(REG_BASE + 0x0000009E); -#define ATD0DR7 _ATD0DR7.Word -#define ATD0DR7_BIT6 _ATD0DR7.Bits.BIT6 -#define ATD0DR7_BIT7 _ATD0DR7.Bits.BIT7 -#define ATD0DR7_BIT8 _ATD0DR7.Bits.BIT8 -#define ATD0DR7_BIT9 _ATD0DR7.Bits.BIT9 -#define ATD0DR7_BIT10 _ATD0DR7.Bits.BIT10 -#define ATD0DR7_BIT11 _ATD0DR7.Bits.BIT11 -#define ATD0DR7_BIT12 _ATD0DR7.Bits.BIT12 -#define ATD0DR7_BIT13 _ATD0DR7.Bits.BIT13 -#define ATD0DR7_BIT14 _ATD0DR7.Bits.BIT14 -#define ATD0DR7_BIT15 _ATD0DR7.Bits.BIT15 -#define ATD0DR7_BIT_6 _ATD0DR7.MergedBits.grpBIT_6 -#define ATD0DR7_BIT ATD0DR7_BIT_6 - - -/*** PWMCNT01 - PWM Channel Counter 01 Register; 0x000000AC ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** PWMCNT0 - PWM Channel Counter 0 Register; 0x000000AC ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PWMCNT0STR; - #define PWMCNT0 _PWMCNT01.Overlap_STR.PWMCNT0STR.Byte - #define PWMCNT0_BIT _PWMCNT01.Overlap_STR.PWMCNT0STR.MergedBits.grpBIT - - /*** PWMCNT1 - PWM Channel Counter 1 Register; 0x000000AD ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PWMCNT1STR; - #define PWMCNT1 _PWMCNT01.Overlap_STR.PWMCNT1STR.Byte - #define PWMCNT1_BIT _PWMCNT01.Overlap_STR.PWMCNT1STR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word grpBIT :16; - } MergedBits; -} PWMCNT01STR; -extern volatile PWMCNT01STR _PWMCNT01 @(REG_BASE + 0x000000AC); -#define PWMCNT01 _PWMCNT01.Word -#define PWMCNT01_BIT _PWMCNT01.MergedBits.grpBIT - - -/*** PWMCNT23 - PWM Channel Counter 23 Register; 0x000000AE ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** PWMCNT2 - PWM Channel Counter 2 Register; 0x000000AE ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PWMCNT2STR; - #define PWMCNT2 _PWMCNT23.Overlap_STR.PWMCNT2STR.Byte - #define PWMCNT2_BIT _PWMCNT23.Overlap_STR.PWMCNT2STR.MergedBits.grpBIT - - /*** PWMCNT3 - PWM Channel Counter 3 Register; 0x000000AF ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PWMCNT3STR; - #define PWMCNT3 _PWMCNT23.Overlap_STR.PWMCNT3STR.Byte - #define PWMCNT3_BIT _PWMCNT23.Overlap_STR.PWMCNT3STR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word grpBIT :16; - } MergedBits; -} PWMCNT23STR; -extern volatile PWMCNT23STR _PWMCNT23 @(REG_BASE + 0x000000AE); -#define PWMCNT23 _PWMCNT23.Word -#define PWMCNT23_BIT _PWMCNT23.MergedBits.grpBIT - - -/*** PWMCNT45 - PWM Channel Counter 45 Register; 0x000000B0 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** PWMCNT4 - PWM Channel Counter 4 Register; 0x000000B0 ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PWMCNT4STR; - #define PWMCNT4 _PWMCNT45.Overlap_STR.PWMCNT4STR.Byte - #define PWMCNT4_BIT _PWMCNT45.Overlap_STR.PWMCNT4STR.MergedBits.grpBIT - - /*** PWMCNT5 - PWM Channel Counter 5 Register; 0x000000B1 ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PWMCNT5STR; - #define PWMCNT5 _PWMCNT45.Overlap_STR.PWMCNT5STR.Byte - #define PWMCNT5_BIT _PWMCNT45.Overlap_STR.PWMCNT5STR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word grpBIT :16; - } MergedBits; -} PWMCNT45STR; -extern volatile PWMCNT45STR _PWMCNT45 @(REG_BASE + 0x000000B0); -#define PWMCNT45 _PWMCNT45.Word -#define PWMCNT45_BIT _PWMCNT45.MergedBits.grpBIT - - -/*** PWMCNT67 - PWM Channel Counter 67 Register; 0x000000B2 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** PWMCNT6 - PWM Channel Counter 6 Register; 0x000000B2 ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PWMCNT6STR; - #define PWMCNT6 _PWMCNT67.Overlap_STR.PWMCNT6STR.Byte - #define PWMCNT6_BIT _PWMCNT67.Overlap_STR.PWMCNT6STR.MergedBits.grpBIT - - /*** PWMCNT7 - PWM Channel Counter 7 Register; 0x000000B3 ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PWMCNT7STR; - #define PWMCNT7 _PWMCNT67.Overlap_STR.PWMCNT7STR.Byte - #define PWMCNT7_BIT _PWMCNT67.Overlap_STR.PWMCNT7STR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word grpBIT :16; - } MergedBits; -} PWMCNT67STR; -extern volatile PWMCNT67STR _PWMCNT67 @(REG_BASE + 0x000000B2); -#define PWMCNT67 _PWMCNT67.Word -#define PWMCNT67_BIT _PWMCNT67.MergedBits.grpBIT - - -/*** PWMPER01 - PWM Channel Period 01 Register; 0x000000B4 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** PWMPER0 - PWM Channel Period 0 Register; 0x000000B4 ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PWMPER0STR; - #define PWMPER0 _PWMPER01.Overlap_STR.PWMPER0STR.Byte - #define PWMPER0_BIT _PWMPER01.Overlap_STR.PWMPER0STR.MergedBits.grpBIT - - /*** PWMPER1 - PWM Channel Period 1 Register; 0x000000B5 ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PWMPER1STR; - #define PWMPER1 _PWMPER01.Overlap_STR.PWMPER1STR.Byte - #define PWMPER1_BIT _PWMPER01.Overlap_STR.PWMPER1STR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word grpBIT :16; - } MergedBits; -} PWMPER01STR; -extern volatile PWMPER01STR _PWMPER01 @(REG_BASE + 0x000000B4); -#define PWMPER01 _PWMPER01.Word -#define PWMPER01_BIT _PWMPER01.MergedBits.grpBIT - - -/*** PWMPER23 - PWM Channel Period 23 Register; 0x000000B6 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** PWMPER2 - PWM Channel Period 2 Register; 0x000000B6 ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PWMPER2STR; - #define PWMPER2 _PWMPER23.Overlap_STR.PWMPER2STR.Byte - #define PWMPER2_BIT _PWMPER23.Overlap_STR.PWMPER2STR.MergedBits.grpBIT - - /*** PWMPER3 - PWM Channel Period 3 Register; 0x000000B7 ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PWMPER3STR; - #define PWMPER3 _PWMPER23.Overlap_STR.PWMPER3STR.Byte - #define PWMPER3_BIT _PWMPER23.Overlap_STR.PWMPER3STR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word grpBIT :16; - } MergedBits; -} PWMPER23STR; -extern volatile PWMPER23STR _PWMPER23 @(REG_BASE + 0x000000B6); -#define PWMPER23 _PWMPER23.Word -#define PWMPER23_BIT _PWMPER23.MergedBits.grpBIT - - -/*** PWMPER45 - PWM Channel Period 45 Register; 0x000000B8 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** PWMPER4 - PWM Channel Period 4 Register; 0x000000B8 ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PWMPER4STR; - #define PWMPER4 _PWMPER45.Overlap_STR.PWMPER4STR.Byte - #define PWMPER4_BIT _PWMPER45.Overlap_STR.PWMPER4STR.MergedBits.grpBIT - - /*** PWMPER5 - PWM Channel Period 5 Register; 0x000000B9 ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PWMPER5STR; - #define PWMPER5 _PWMPER45.Overlap_STR.PWMPER5STR.Byte - #define PWMPER5_BIT _PWMPER45.Overlap_STR.PWMPER5STR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word grpBIT :16; - } MergedBits; -} PWMPER45STR; -extern volatile PWMPER45STR _PWMPER45 @(REG_BASE + 0x000000B8); -#define PWMPER45 _PWMPER45.Word -#define PWMPER45_BIT _PWMPER45.MergedBits.grpBIT - - -/*** PWMPER67 - PWM Channel Period 67 Register; 0x000000BA ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** PWMPER6 - PWM Channel Period 6 Register; 0x000000BA ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PWMPER6STR; - #define PWMPER6 _PWMPER67.Overlap_STR.PWMPER6STR.Byte - #define PWMPER6_BIT _PWMPER67.Overlap_STR.PWMPER6STR.MergedBits.grpBIT - - /*** PWMPER7 - PWM Channel Period 7 Register; 0x000000BB ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PWMPER7STR; - #define PWMPER7 _PWMPER67.Overlap_STR.PWMPER7STR.Byte - #define PWMPER7_BIT _PWMPER67.Overlap_STR.PWMPER7STR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word grpBIT :16; - } MergedBits; -} PWMPER67STR; -extern volatile PWMPER67STR _PWMPER67 @(REG_BASE + 0x000000BA); -#define PWMPER67 _PWMPER67.Word -#define PWMPER67_BIT _PWMPER67.MergedBits.grpBIT - - -/*** PWMDTY01 - PWM Channel Duty 01 Register; 0x000000BC ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** PWMDTY0 - PWM Channel Duty 0 Register; 0x000000BC ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PWMDTY0STR; - #define PWMDTY0 _PWMDTY01.Overlap_STR.PWMDTY0STR.Byte - #define PWMDTY0_BIT _PWMDTY01.Overlap_STR.PWMDTY0STR.MergedBits.grpBIT - - /*** PWMDTY1 - PWM Channel Duty 1 Register; 0x000000BD ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PWMDTY1STR; - #define PWMDTY1 _PWMDTY01.Overlap_STR.PWMDTY1STR.Byte - #define PWMDTY1_BIT _PWMDTY01.Overlap_STR.PWMDTY1STR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word grpBIT :16; - } MergedBits; -} PWMDTY01STR; -extern volatile PWMDTY01STR _PWMDTY01 @(REG_BASE + 0x000000BC); -#define PWMDTY01 _PWMDTY01.Word -#define PWMDTY01_BIT _PWMDTY01.MergedBits.grpBIT - - -/*** PWMDTY23 - PWM Channel Duty 23 Register; 0x000000BE ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** PWMDTY2 - PWM Channel Duty 2 Register; 0x000000BE ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PWMDTY2STR; - #define PWMDTY2 _PWMDTY23.Overlap_STR.PWMDTY2STR.Byte - #define PWMDTY2_BIT _PWMDTY23.Overlap_STR.PWMDTY2STR.MergedBits.grpBIT - - /*** PWMDTY3 - PWM Channel Duty 3 Register; 0x000000BF ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PWMDTY3STR; - #define PWMDTY3 _PWMDTY23.Overlap_STR.PWMDTY3STR.Byte - #define PWMDTY3_BIT _PWMDTY23.Overlap_STR.PWMDTY3STR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word grpBIT :16; - } MergedBits; -} PWMDTY23STR; -extern volatile PWMDTY23STR _PWMDTY23 @(REG_BASE + 0x000000BE); -#define PWMDTY23 _PWMDTY23.Word -#define PWMDTY23_BIT _PWMDTY23.MergedBits.grpBIT - - -/*** PWMDTY45 - PWM Channel Duty 45 Register; 0x000000C0 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** PWMDTY4 - PWM Channel Duty 4 Register; 0x000000C0 ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PWMDTY4STR; - #define PWMDTY4 _PWMDTY45.Overlap_STR.PWMDTY4STR.Byte - #define PWMDTY4_BIT _PWMDTY45.Overlap_STR.PWMDTY4STR.MergedBits.grpBIT - - /*** PWMDTY5 - PWM Channel Duty 5 Register; 0x000000C1 ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PWMDTY5STR; - #define PWMDTY5 _PWMDTY45.Overlap_STR.PWMDTY5STR.Byte - #define PWMDTY5_BIT _PWMDTY45.Overlap_STR.PWMDTY5STR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word grpBIT :16; - } MergedBits; -} PWMDTY45STR; -extern volatile PWMDTY45STR _PWMDTY45 @(REG_BASE + 0x000000C0); -#define PWMDTY45 _PWMDTY45.Word -#define PWMDTY45_BIT _PWMDTY45.MergedBits.grpBIT - - -/*** PWMDTY67 - PWM Channel Duty 67 Register; 0x000000C2 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** PWMDTY6 - PWM Channel Duty 6 Register; 0x000000C2 ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PWMDTY6STR; - #define PWMDTY6 _PWMDTY67.Overlap_STR.PWMDTY6STR.Byte - #define PWMDTY6_BIT _PWMDTY67.Overlap_STR.PWMDTY6STR.MergedBits.grpBIT - - /*** PWMDTY7 - PWM Channel Duty 7 Register; 0x000000C3 ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PWMDTY7STR; - #define PWMDTY7 _PWMDTY67.Overlap_STR.PWMDTY7STR.Byte - #define PWMDTY7_BIT _PWMDTY67.Overlap_STR.PWMDTY7STR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word grpBIT :16; - } MergedBits; -} PWMDTY67STR; -extern volatile PWMDTY67STR _PWMDTY67 @(REG_BASE + 0x000000C2); -#define PWMDTY67 _PWMDTY67.Word -#define PWMDTY67_BIT _PWMDTY67.MergedBits.grpBIT - - -/*** SCI0BD - SCI 0 Baud Rate Register; 0x000000C8 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** SCI0BDH - SCI 0 Baud Rate Register High; 0x000000C8 ***/ - union { - byte Byte; - struct { - byte SBR8 :1; /* SCI 0 baud rate Bit 8 */ - byte SBR9 :1; /* SCI 0 baud rate Bit 9 */ - byte SBR10 :1; /* SCI 0 baud rate Bit 10 */ - byte SBR11 :1; /* SCI 0 baud rate Bit 11 */ - byte SBR12 :1; /* SCI 0 baud rate Bit 12 */ - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpSBR_8 :5; - byte :1; - byte :1; - byte :1; - } MergedBits; - } SCI0BDHSTR; - #define SCI0BDH _SCI0BD.Overlap_STR.SCI0BDHSTR.Byte - #define SCI0BDH_SBR8 _SCI0BD.Overlap_STR.SCI0BDHSTR.Bits.SBR8 - #define SCI0BDH_SBR9 _SCI0BD.Overlap_STR.SCI0BDHSTR.Bits.SBR9 - #define SCI0BDH_SBR10 _SCI0BD.Overlap_STR.SCI0BDHSTR.Bits.SBR10 - #define SCI0BDH_SBR11 _SCI0BD.Overlap_STR.SCI0BDHSTR.Bits.SBR11 - #define SCI0BDH_SBR12 _SCI0BD.Overlap_STR.SCI0BDHSTR.Bits.SBR12 - #define SCI0BDH_SBR_8 _SCI0BD.Overlap_STR.SCI0BDHSTR.MergedBits.grpSBR_8 - #define SCI0BDH_SBR SCI0BDH_SBR_8 - - /*** SCI0BDL - SCI 0 Baud Rate Register Low; 0x000000C9 ***/ - union { - byte Byte; - struct { - byte SBR0 :1; /* SCI 0 baud rate Bit 0 */ - byte SBR1 :1; /* SCI 0 baud rate Bit 1 */ - byte SBR2 :1; /* SCI 0 baud rate Bit 2 */ - byte SBR3 :1; /* SCI 0 baud rate Bit 3 */ - byte SBR4 :1; /* SCI 0 baud rate Bit 4 */ - byte SBR5 :1; /* SCI 0 baud rate Bit 5 */ - byte SBR6 :1; /* SCI 0 baud rate Bit 6 */ - byte SBR7 :1; /* SCI 0 baud rate Bit 7 */ - } Bits; - struct { - byte grpSBR :8; - } MergedBits; - } SCI0BDLSTR; - #define SCI0BDL _SCI0BD.Overlap_STR.SCI0BDLSTR.Byte - #define SCI0BDL_SBR0 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR0 - #define SCI0BDL_SBR1 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR1 - #define SCI0BDL_SBR2 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR2 - #define SCI0BDL_SBR3 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR3 - #define SCI0BDL_SBR4 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR4 - #define SCI0BDL_SBR5 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR5 - #define SCI0BDL_SBR6 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR6 - #define SCI0BDL_SBR7 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR7 - #define SCI0BDL_SBR _SCI0BD.Overlap_STR.SCI0BDLSTR.MergedBits.grpSBR - - } Overlap_STR; - - struct { - word SBR0 :1; /* SCI 0 baud rate Bit 0 */ - word SBR1 :1; /* SCI 0 baud rate Bit 1 */ - word SBR2 :1; /* SCI 0 baud rate Bit 2 */ - word SBR3 :1; /* SCI 0 baud rate Bit 3 */ - word SBR4 :1; /* SCI 0 baud rate Bit 4 */ - word SBR5 :1; /* SCI 0 baud rate Bit 5 */ - word SBR6 :1; /* SCI 0 baud rate Bit 6 */ - word SBR7 :1; /* SCI 0 baud rate Bit 7 */ - word SBR8 :1; /* SCI 0 baud rate Bit 8 */ - word SBR9 :1; /* SCI 0 baud rate Bit 9 */ - word SBR10 :1; /* SCI 0 baud rate Bit 10 */ - word SBR11 :1; /* SCI 0 baud rate Bit 11 */ - word SBR12 :1; /* SCI 0 baud rate Bit 12 */ - word :1; - word :1; - word :1; - } Bits; - struct { - word grpSBR :13; - word :1; - word :1; - word :1; - } MergedBits; -} SCI0BDSTR; -extern volatile SCI0BDSTR _SCI0BD @(REG_BASE + 0x000000C8); -#define SCI0BD _SCI0BD.Word -#define SCI0BD_SBR0 _SCI0BD.Bits.SBR0 -#define SCI0BD_SBR1 _SCI0BD.Bits.SBR1 -#define SCI0BD_SBR2 _SCI0BD.Bits.SBR2 -#define SCI0BD_SBR3 _SCI0BD.Bits.SBR3 -#define SCI0BD_SBR4 _SCI0BD.Bits.SBR4 -#define SCI0BD_SBR5 _SCI0BD.Bits.SBR5 -#define SCI0BD_SBR6 _SCI0BD.Bits.SBR6 -#define SCI0BD_SBR7 _SCI0BD.Bits.SBR7 -#define SCI0BD_SBR8 _SCI0BD.Bits.SBR8 -#define SCI0BD_SBR9 _SCI0BD.Bits.SBR9 -#define SCI0BD_SBR10 _SCI0BD.Bits.SBR10 -#define SCI0BD_SBR11 _SCI0BD.Bits.SBR11 -#define SCI0BD_SBR12 _SCI0BD.Bits.SBR12 -#define SCI0BD_SBR _SCI0BD.MergedBits.grpSBR - - -/*** SCI1BD - SCI 1 Baud Rate Register; 0x000000D0 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** SCI1BDH - SCI 1 Baud Rate Register High; 0x000000D0 ***/ - union { - byte Byte; - struct { - byte SBR8 :1; /* SCI 1 baud rate Bit 8 */ - byte SBR9 :1; /* SCI 1 baud rate Bit 9 */ - byte SBR10 :1; /* SCI 1 baud rate Bit 10 */ - byte SBR11 :1; /* SCI 1 baud rate Bit 11 */ - byte SBR12 :1; /* SCI 1 baud rate Bit 12 */ - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpSBR_8 :5; - byte :1; - byte :1; - byte :1; - } MergedBits; - } SCI1BDHSTR; - #define SCI1BDH _SCI1BD.Overlap_STR.SCI1BDHSTR.Byte - #define SCI1BDH_SBR8 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR8 - #define SCI1BDH_SBR9 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR9 - #define SCI1BDH_SBR10 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR10 - #define SCI1BDH_SBR11 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR11 - #define SCI1BDH_SBR12 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR12 - #define SCI1BDH_SBR_8 _SCI1BD.Overlap_STR.SCI1BDHSTR.MergedBits.grpSBR_8 - #define SCI1BDH_SBR SCI1BDH_SBR_8 - - /*** SCI1BDL - SCI 1 Baud Rate Register Low; 0x000000D1 ***/ - union { - byte Byte; - struct { - byte SBR0 :1; /* SCI 1 baud rate Bit 0 */ - byte SBR1 :1; /* SCI 1 baud rate Bit 1 */ - byte SBR2 :1; /* SCI 1 baud rate Bit 2 */ - byte SBR3 :1; /* SCI 1 baud rate Bit 3 */ - byte SBR4 :1; /* SCI 1 baud rate Bit 4 */ - byte SBR5 :1; /* SCI 1 baud rate Bit 5 */ - byte SBR6 :1; /* SCI 1 baud rate Bit 6 */ - byte SBR7 :1; /* SCI 1 baud rate Bit 7 */ - } Bits; - struct { - byte grpSBR :8; - } MergedBits; - } SCI1BDLSTR; - #define SCI1BDL _SCI1BD.Overlap_STR.SCI1BDLSTR.Byte - #define SCI1BDL_SBR0 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR0 - #define SCI1BDL_SBR1 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR1 - #define SCI1BDL_SBR2 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR2 - #define SCI1BDL_SBR3 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR3 - #define SCI1BDL_SBR4 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR4 - #define SCI1BDL_SBR5 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR5 - #define SCI1BDL_SBR6 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR6 - #define SCI1BDL_SBR7 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR7 - #define SCI1BDL_SBR _SCI1BD.Overlap_STR.SCI1BDLSTR.MergedBits.grpSBR - - } Overlap_STR; - - struct { - word SBR0 :1; /* SCI 1 baud rate Bit 0 */ - word SBR1 :1; /* SCI 1 baud rate Bit 1 */ - word SBR2 :1; /* SCI 1 baud rate Bit 2 */ - word SBR3 :1; /* SCI 1 baud rate Bit 3 */ - word SBR4 :1; /* SCI 1 baud rate Bit 4 */ - word SBR5 :1; /* SCI 1 baud rate Bit 5 */ - word SBR6 :1; /* SCI 1 baud rate Bit 6 */ - word SBR7 :1; /* SCI 1 baud rate Bit 7 */ - word SBR8 :1; /* SCI 1 baud rate Bit 8 */ - word SBR9 :1; /* SCI 1 baud rate Bit 9 */ - word SBR10 :1; /* SCI 1 baud rate Bit 10 */ - word SBR11 :1; /* SCI 1 baud rate Bit 11 */ - word SBR12 :1; /* SCI 1 baud rate Bit 12 */ - word :1; - word :1; - word :1; - } Bits; - struct { - word grpSBR :13; - word :1; - word :1; - word :1; - } MergedBits; -} SCI1BDSTR; -extern volatile SCI1BDSTR _SCI1BD @(REG_BASE + 0x000000D0); -#define SCI1BD _SCI1BD.Word -#define SCI1BD_SBR0 _SCI1BD.Bits.SBR0 -#define SCI1BD_SBR1 _SCI1BD.Bits.SBR1 -#define SCI1BD_SBR2 _SCI1BD.Bits.SBR2 -#define SCI1BD_SBR3 _SCI1BD.Bits.SBR3 -#define SCI1BD_SBR4 _SCI1BD.Bits.SBR4 -#define SCI1BD_SBR5 _SCI1BD.Bits.SBR5 -#define SCI1BD_SBR6 _SCI1BD.Bits.SBR6 -#define SCI1BD_SBR7 _SCI1BD.Bits.SBR7 -#define SCI1BD_SBR8 _SCI1BD.Bits.SBR8 -#define SCI1BD_SBR9 _SCI1BD.Bits.SBR9 -#define SCI1BD_SBR10 _SCI1BD.Bits.SBR10 -#define SCI1BD_SBR11 _SCI1BD.Bits.SBR11 -#define SCI1BD_SBR12 _SCI1BD.Bits.SBR12 -#define SCI1BD_SBR _SCI1BD.MergedBits.grpSBR - - -/*** ATD1CTL23 - ATD 1 Control Register 23; 0x00000122 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** ATD1CTL2 - ATD 1 Control Register 2; 0x00000122 ***/ - union { - byte Byte; - struct { - byte ASCIF :1; /* ATD 1 Sequence Complete Interrupt Flag */ - byte ASCIE :1; /* ATD 1 Sequence Complete Interrupt Enable */ - byte ETRIGE :1; /* External Trigger Mode enable */ - byte ETRIGP :1; /* External Trigger Polarity */ - byte ETRIGLE :1; /* External Trigger Level/Edge control */ - byte AWAI :1; /* ATD 1 Wait Mode */ - byte AFFC :1; /* ATD 1 Fast Conversion Complete Flag Clear */ - byte ADPU :1; /* ATD 1 Disable / Power Down */ - } Bits; - } ATD1CTL2STR; - #define ATD1CTL2 _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Byte - #define ATD1CTL2_ASCIF _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ASCIF - #define ATD1CTL2_ASCIE _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ASCIE - #define ATD1CTL2_ETRIGE _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ETRIGE - #define ATD1CTL2_ETRIGP _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ETRIGP - #define ATD1CTL2_ETRIGLE _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ETRIGLE - #define ATD1CTL2_AWAI _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.AWAI - #define ATD1CTL2_AFFC _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.AFFC - #define ATD1CTL2_ADPU _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ADPU - - /*** ATD1CTL3 - ATD 1 Control Register 3; 0x00000123 ***/ - union { - byte Byte; - struct { - byte FRZ0 :1; /* Background Debug Freeze Enable */ - byte FRZ1 :1; /* Background Debug Freeze Enable */ - byte FIFO :1; /* Result Register FIFO Mode */ - byte S1C :1; /* Conversion Sequence Length 1 */ - byte S2C :1; /* Conversion Sequence Length 2 */ - byte S4C :1; /* Conversion Sequence Length 4 */ - byte S8C :1; /* Conversion Sequence Length 8 */ - byte :1; - } Bits; - struct { - byte grpFRZ :2; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; - } ATD1CTL3STR; - #define ATD1CTL3 _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Byte - #define ATD1CTL3_FRZ0 _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.FRZ0 - #define ATD1CTL3_FRZ1 _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.FRZ1 - #define ATD1CTL3_FIFO _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.FIFO - #define ATD1CTL3_S1C _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.S1C - #define ATD1CTL3_S2C _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.S2C - #define ATD1CTL3_S4C _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.S4C - #define ATD1CTL3_S8C _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.S8C - #define ATD1CTL3_FRZ _ATD1CTL23.Overlap_STR.ATD1CTL3STR.MergedBits.grpFRZ - - } Overlap_STR; - - struct { - word FRZ0 :1; /* Background Debug Freeze Enable */ - word FRZ1 :1; /* Background Debug Freeze Enable */ - word FIFO :1; /* Result Register FIFO Mode */ - word S1C :1; /* Conversion Sequence Length 1 */ - word S2C :1; /* Conversion Sequence Length 2 */ - word S4C :1; /* Conversion Sequence Length 4 */ - word S8C :1; /* Conversion Sequence Length 8 */ - word :1; - word ASCIF :1; /* ATD 1 Sequence Complete Interrupt Flag */ - word ASCIE :1; /* ATD 1 Sequence Complete Interrupt Enable */ - word ETRIGE :1; /* External Trigger Mode enable */ - word ETRIGP :1; /* External Trigger Polarity */ - word ETRIGLE :1; /* External Trigger Level/Edge control */ - word AWAI :1; /* ATD 1 Wait Mode */ - word AFFC :1; /* ATD 1 Fast Conversion Complete Flag Clear */ - word ADPU :1; /* ATD 1 Disable / Power Down */ - } Bits; - struct { - word grpFRZ :2; - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - } MergedBits; -} ATD1CTL23STR; -extern volatile ATD1CTL23STR _ATD1CTL23 @(REG_BASE + 0x00000122); -#define ATD1CTL23 _ATD1CTL23.Word -#define ATD1CTL23_FRZ0 _ATD1CTL23.Bits.FRZ0 -#define ATD1CTL23_FRZ1 _ATD1CTL23.Bits.FRZ1 -#define ATD1CTL23_FIFO _ATD1CTL23.Bits.FIFO -#define ATD1CTL23_S1C _ATD1CTL23.Bits.S1C -#define ATD1CTL23_S2C _ATD1CTL23.Bits.S2C -#define ATD1CTL23_S4C _ATD1CTL23.Bits.S4C -#define ATD1CTL23_S8C _ATD1CTL23.Bits.S8C -#define ATD1CTL23_ASCIF _ATD1CTL23.Bits.ASCIF -#define ATD1CTL23_ASCIE _ATD1CTL23.Bits.ASCIE -#define ATD1CTL23_ETRIGE _ATD1CTL23.Bits.ETRIGE -#define ATD1CTL23_ETRIGP _ATD1CTL23.Bits.ETRIGP -#define ATD1CTL23_ETRIGLE _ATD1CTL23.Bits.ETRIGLE -#define ATD1CTL23_AWAI _ATD1CTL23.Bits.AWAI -#define ATD1CTL23_AFFC _ATD1CTL23.Bits.AFFC -#define ATD1CTL23_ADPU _ATD1CTL23.Bits.ADPU -#define ATD1CTL23_FRZ _ATD1CTL23.MergedBits.grpFRZ - - -/*** ATD1CTL45 - ATD 1 Control Register 45; 0x00000124 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** ATD1CTL4 - ATD 1 Control Register 4; 0x00000124 ***/ - union { - byte Byte; - struct { - byte PRS0 :1; /* ATD 1 Clock Prescaler 0 */ - byte PRS1 :1; /* ATD 1 Clock Prescaler 1 */ - byte PRS2 :1; /* ATD 1 Clock Prescaler 2 */ - byte PRS3 :1; /* ATD 1 Clock Prescaler 3 */ - byte PRS4 :1; /* ATD 1 Clock Prescaler 4 */ - byte SMP0 :1; /* Sample Time Select 0 */ - byte SMP1 :1; /* Sample Time Select 1 */ - byte SRES8 :1; /* ATD 1 Resolution Select */ - } Bits; - struct { - byte grpPRS :5; - byte grpSMP :2; - byte grpSRES_8 :1; - } MergedBits; - } ATD1CTL4STR; - #define ATD1CTL4 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Byte - #define ATD1CTL4_PRS0 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.PRS0 - #define ATD1CTL4_PRS1 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.PRS1 - #define ATD1CTL4_PRS2 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.PRS2 - #define ATD1CTL4_PRS3 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.PRS3 - #define ATD1CTL4_PRS4 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.PRS4 - #define ATD1CTL4_SMP0 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.SMP0 - #define ATD1CTL4_SMP1 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.SMP1 - #define ATD1CTL4_SRES8 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.SRES8 - #define ATD1CTL4_PRS _ATD1CTL45.Overlap_STR.ATD1CTL4STR.MergedBits.grpPRS - #define ATD1CTL4_SMP _ATD1CTL45.Overlap_STR.ATD1CTL4STR.MergedBits.grpSMP - - /*** ATD1CTL5 - ATD 1 Control Register 5; 0x00000125 ***/ - union { - byte Byte; - struct { - byte CA :1; /* Analog Input Channel Select Code A */ - byte CB :1; /* Analog Input Channel Select Code B */ - byte CC :1; /* Analog Input Channel Select Code C */ - byte :1; - byte MULT :1; /* Multi-Channel Sample Mode */ - byte SCAN :1; /* Continuous Conversion Sequence Mode */ - byte DSGN :1; /* Signed/Unsigned Result Data Mode */ - byte DJM :1; /* Result Register Data Justification Mode */ - } Bits; - } ATD1CTL5STR; - #define ATD1CTL5 _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Byte - #define ATD1CTL5_CA _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.CA - #define ATD1CTL5_CB _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.CB - #define ATD1CTL5_CC _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.CC - #define ATD1CTL5_MULT _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.MULT - #define ATD1CTL5_SCAN _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.SCAN - #define ATD1CTL5_DSGN _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.DSGN - #define ATD1CTL5_DJM _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.DJM - - } Overlap_STR; - - struct { - word CA :1; /* Analog Input Channel Select Code A */ - word CB :1; /* Analog Input Channel Select Code B */ - word CC :1; /* Analog Input Channel Select Code C */ - word :1; - word MULT :1; /* Multi-Channel Sample Mode */ - word SCAN :1; /* Continuous Conversion Sequence Mode */ - word DSGN :1; /* Signed/Unsigned Result Data Mode */ - word DJM :1; /* Result Register Data Justification Mode */ - word PRS0 :1; /* ATD 1 Clock Prescaler 0 */ - word PRS1 :1; /* ATD 1 Clock Prescaler 1 */ - word PRS2 :1; /* ATD 1 Clock Prescaler 2 */ - word PRS3 :1; /* ATD 1 Clock Prescaler 3 */ - word PRS4 :1; /* ATD 1 Clock Prescaler 4 */ - word SMP0 :1; /* Sample Time Select 0 */ - word SMP1 :1; /* Sample Time Select 1 */ - word SRES8 :1; /* ATD 1 Resolution Select */ - } Bits; - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word grpPRS :5; - word grpSMP :2; - word grpSRES_8 :1; - } MergedBits; -} ATD1CTL45STR; -extern volatile ATD1CTL45STR _ATD1CTL45 @(REG_BASE + 0x00000124); -#define ATD1CTL45 _ATD1CTL45.Word -#define ATD1CTL45_CA _ATD1CTL45.Bits.CA -#define ATD1CTL45_CB _ATD1CTL45.Bits.CB -#define ATD1CTL45_CC _ATD1CTL45.Bits.CC -#define ATD1CTL45_MULT _ATD1CTL45.Bits.MULT -#define ATD1CTL45_SCAN _ATD1CTL45.Bits.SCAN -#define ATD1CTL45_DSGN _ATD1CTL45.Bits.DSGN -#define ATD1CTL45_DJM _ATD1CTL45.Bits.DJM -#define ATD1CTL45_PRS0 _ATD1CTL45.Bits.PRS0 -#define ATD1CTL45_PRS1 _ATD1CTL45.Bits.PRS1 -#define ATD1CTL45_PRS2 _ATD1CTL45.Bits.PRS2 -#define ATD1CTL45_PRS3 _ATD1CTL45.Bits.PRS3 -#define ATD1CTL45_PRS4 _ATD1CTL45.Bits.PRS4 -#define ATD1CTL45_SMP0 _ATD1CTL45.Bits.SMP0 -#define ATD1CTL45_SMP1 _ATD1CTL45.Bits.SMP1 -#define ATD1CTL45_SRES8 _ATD1CTL45.Bits.SRES8 -#define ATD1CTL45_PRS _ATD1CTL45.MergedBits.grpPRS -#define ATD1CTL45_SMP _ATD1CTL45.MergedBits.grpSMP - - -/*** ATD1DR0 - ATD 1 Conversion Result Register 0; 0x00000130 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** ATD1DR0H - ATD 1 Conversion Result Register 0 High; 0x00000130 ***/ - union { - byte Byte; - struct { - byte BIT8 :1; /* Bit 8 */ - byte BIT9 :1; /* Bit 9 */ - byte BIT10 :1; /* Bit 10 */ - byte BIT11 :1; /* Bit 11 */ - byte BIT12 :1; /* Bit 12 */ - byte BIT13 :1; /* Bit 13 */ - byte BIT14 :1; /* Bit 14 */ - byte BIT15 :1; /* Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; - } ATD1DR0HSTR; - #define ATD1DR0H _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Byte - #define ATD1DR0H_BIT8 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT8 - #define ATD1DR0H_BIT9 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT9 - #define ATD1DR0H_BIT10 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT10 - #define ATD1DR0H_BIT11 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT11 - #define ATD1DR0H_BIT12 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT12 - #define ATD1DR0H_BIT13 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT13 - #define ATD1DR0H_BIT14 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT14 - #define ATD1DR0H_BIT15 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT15 - #define ATD1DR0H_BIT_8 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.MergedBits.grpBIT_8 - #define ATD1DR0H_BIT ATD1DR0H_BIT_8 - - /*** ATD1DR0L - ATD 1 Conversion Result Register 0 Low; 0x00000131 ***/ - union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte BIT6 :1; /* Bit 6 */ - byte BIT7 :1; /* Bit 7 */ - } Bits; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte grpBIT_6 :2; - } MergedBits; - } ATD1DR0LSTR; - #define ATD1DR0L _ATD1DR0.Overlap_STR.ATD1DR0LSTR.Byte - #define ATD1DR0L_BIT6 _ATD1DR0.Overlap_STR.ATD1DR0LSTR.Bits.BIT6 - #define ATD1DR0L_BIT7 _ATD1DR0.Overlap_STR.ATD1DR0LSTR.Bits.BIT7 - #define ATD1DR0L_BIT_6 _ATD1DR0.Overlap_STR.ATD1DR0LSTR.MergedBits.grpBIT_6 - #define ATD1DR0L_BIT ATD1DR0L_BIT_6 - - } Overlap_STR; - - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word BIT6 :1; /* Bit 6 */ - word BIT7 :1; /* Bit 7 */ - word BIT8 :1; /* Bit 8 */ - word BIT9 :1; /* Bit 9 */ - word BIT10 :1; /* Bit 10 */ - word BIT11 :1; /* Bit 11 */ - word BIT12 :1; /* Bit 12 */ - word BIT13 :1; /* Bit 13 */ - word BIT14 :1; /* Bit 14 */ - word BIT15 :1; /* Bit 15 */ - } Bits; - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word grpBIT_6 :10; - } MergedBits; -} ATD1DR0STR; -extern volatile ATD1DR0STR _ATD1DR0 @(REG_BASE + 0x00000130); -#define ATD1DR0 _ATD1DR0.Word -#define ATD1DR0_BIT6 _ATD1DR0.Bits.BIT6 -#define ATD1DR0_BIT7 _ATD1DR0.Bits.BIT7 -#define ATD1DR0_BIT8 _ATD1DR0.Bits.BIT8 -#define ATD1DR0_BIT9 _ATD1DR0.Bits.BIT9 -#define ATD1DR0_BIT10 _ATD1DR0.Bits.BIT10 -#define ATD1DR0_BIT11 _ATD1DR0.Bits.BIT11 -#define ATD1DR0_BIT12 _ATD1DR0.Bits.BIT12 -#define ATD1DR0_BIT13 _ATD1DR0.Bits.BIT13 -#define ATD1DR0_BIT14 _ATD1DR0.Bits.BIT14 -#define ATD1DR0_BIT15 _ATD1DR0.Bits.BIT15 -#define ATD1DR0_BIT_6 _ATD1DR0.MergedBits.grpBIT_6 -#define ATD1DR0_BIT ATD1DR0_BIT_6 - - -/*** ATD1DR1 - ATD 1 Conversion Result Register 1; 0x00000132 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** ATD1DR1H - ATD 1 Conversion Result Register 1 High; 0x00000132 ***/ - union { - byte Byte; - struct { - byte BIT8 :1; /* Bit 8 */ - byte BIT9 :1; /* Bit 9 */ - byte BIT10 :1; /* Bit 10 */ - byte BIT11 :1; /* Bit 11 */ - byte BIT12 :1; /* Bit 12 */ - byte BIT13 :1; /* Bit 13 */ - byte BIT14 :1; /* Bit 14 */ - byte BIT15 :1; /* Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; - } ATD1DR1HSTR; - #define ATD1DR1H _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Byte - #define ATD1DR1H_BIT8 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT8 - #define ATD1DR1H_BIT9 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT9 - #define ATD1DR1H_BIT10 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT10 - #define ATD1DR1H_BIT11 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT11 - #define ATD1DR1H_BIT12 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT12 - #define ATD1DR1H_BIT13 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT13 - #define ATD1DR1H_BIT14 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT14 - #define ATD1DR1H_BIT15 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT15 - #define ATD1DR1H_BIT_8 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.MergedBits.grpBIT_8 - #define ATD1DR1H_BIT ATD1DR1H_BIT_8 - - /*** ATD1DR1L - ATD 1 Conversion Result Register 1 Low; 0x00000133 ***/ - union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte BIT6 :1; /* Bit 6 */ - byte BIT7 :1; /* Bit 7 */ - } Bits; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte grpBIT_6 :2; - } MergedBits; - } ATD1DR1LSTR; - #define ATD1DR1L _ATD1DR1.Overlap_STR.ATD1DR1LSTR.Byte - #define ATD1DR1L_BIT6 _ATD1DR1.Overlap_STR.ATD1DR1LSTR.Bits.BIT6 - #define ATD1DR1L_BIT7 _ATD1DR1.Overlap_STR.ATD1DR1LSTR.Bits.BIT7 - #define ATD1DR1L_BIT_6 _ATD1DR1.Overlap_STR.ATD1DR1LSTR.MergedBits.grpBIT_6 - #define ATD1DR1L_BIT ATD1DR1L_BIT_6 - - } Overlap_STR; - - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word BIT6 :1; /* Bit 6 */ - word BIT7 :1; /* Bit 7 */ - word BIT8 :1; /* Bit 8 */ - word BIT9 :1; /* Bit 9 */ - word BIT10 :1; /* Bit 10 */ - word BIT11 :1; /* Bit 11 */ - word BIT12 :1; /* Bit 12 */ - word BIT13 :1; /* Bit 13 */ - word BIT14 :1; /* Bit 14 */ - word BIT15 :1; /* Bit 15 */ - } Bits; - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word grpBIT_6 :10; - } MergedBits; -} ATD1DR1STR; -extern volatile ATD1DR1STR _ATD1DR1 @(REG_BASE + 0x00000132); -#define ATD1DR1 _ATD1DR1.Word -#define ATD1DR1_BIT6 _ATD1DR1.Bits.BIT6 -#define ATD1DR1_BIT7 _ATD1DR1.Bits.BIT7 -#define ATD1DR1_BIT8 _ATD1DR1.Bits.BIT8 -#define ATD1DR1_BIT9 _ATD1DR1.Bits.BIT9 -#define ATD1DR1_BIT10 _ATD1DR1.Bits.BIT10 -#define ATD1DR1_BIT11 _ATD1DR1.Bits.BIT11 -#define ATD1DR1_BIT12 _ATD1DR1.Bits.BIT12 -#define ATD1DR1_BIT13 _ATD1DR1.Bits.BIT13 -#define ATD1DR1_BIT14 _ATD1DR1.Bits.BIT14 -#define ATD1DR1_BIT15 _ATD1DR1.Bits.BIT15 -#define ATD1DR1_BIT_6 _ATD1DR1.MergedBits.grpBIT_6 -#define ATD1DR1_BIT ATD1DR1_BIT_6 - - -/*** ATD1DR2 - ATD 1 Conversion Result Register 2; 0x00000134 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** ATD1DR2H - ATD 1 Conversion Result Register 2 High; 0x00000134 ***/ - union { - byte Byte; - struct { - byte BIT8 :1; /* Bit 8 */ - byte BIT9 :1; /* Bit 9 */ - byte BIT10 :1; /* Bit 10 */ - byte BIT11 :1; /* Bit 11 */ - byte BIT12 :1; /* Bit 12 */ - byte BIT13 :1; /* Bit 13 */ - byte BIT14 :1; /* Bit 14 */ - byte BIT15 :1; /* Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; - } ATD1DR2HSTR; - #define ATD1DR2H _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Byte - #define ATD1DR2H_BIT8 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT8 - #define ATD1DR2H_BIT9 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT9 - #define ATD1DR2H_BIT10 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT10 - #define ATD1DR2H_BIT11 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT11 - #define ATD1DR2H_BIT12 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT12 - #define ATD1DR2H_BIT13 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT13 - #define ATD1DR2H_BIT14 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT14 - #define ATD1DR2H_BIT15 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT15 - #define ATD1DR2H_BIT_8 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.MergedBits.grpBIT_8 - #define ATD1DR2H_BIT ATD1DR2H_BIT_8 - - /*** ATD1DR2L - ATD 1 Conversion Result Register 2 Low; 0x00000135 ***/ - union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte BIT6 :1; /* Bit 6 */ - byte BIT7 :1; /* Bit 7 */ - } Bits; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte grpBIT_6 :2; - } MergedBits; - } ATD1DR2LSTR; - #define ATD1DR2L _ATD1DR2.Overlap_STR.ATD1DR2LSTR.Byte - #define ATD1DR2L_BIT6 _ATD1DR2.Overlap_STR.ATD1DR2LSTR.Bits.BIT6 - #define ATD1DR2L_BIT7 _ATD1DR2.Overlap_STR.ATD1DR2LSTR.Bits.BIT7 - #define ATD1DR2L_BIT_6 _ATD1DR2.Overlap_STR.ATD1DR2LSTR.MergedBits.grpBIT_6 - #define ATD1DR2L_BIT ATD1DR2L_BIT_6 - - } Overlap_STR; - - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word BIT6 :1; /* Bit 6 */ - word BIT7 :1; /* Bit 7 */ - word BIT8 :1; /* Bit 8 */ - word BIT9 :1; /* Bit 9 */ - word BIT10 :1; /* Bit 10 */ - word BIT11 :1; /* Bit 11 */ - word BIT12 :1; /* Bit 12 */ - word BIT13 :1; /* Bit 13 */ - word BIT14 :1; /* Bit 14 */ - word BIT15 :1; /* Bit 15 */ - } Bits; - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word grpBIT_6 :10; - } MergedBits; -} ATD1DR2STR; -extern volatile ATD1DR2STR _ATD1DR2 @(REG_BASE + 0x00000134); -#define ATD1DR2 _ATD1DR2.Word -#define ATD1DR2_BIT6 _ATD1DR2.Bits.BIT6 -#define ATD1DR2_BIT7 _ATD1DR2.Bits.BIT7 -#define ATD1DR2_BIT8 _ATD1DR2.Bits.BIT8 -#define ATD1DR2_BIT9 _ATD1DR2.Bits.BIT9 -#define ATD1DR2_BIT10 _ATD1DR2.Bits.BIT10 -#define ATD1DR2_BIT11 _ATD1DR2.Bits.BIT11 -#define ATD1DR2_BIT12 _ATD1DR2.Bits.BIT12 -#define ATD1DR2_BIT13 _ATD1DR2.Bits.BIT13 -#define ATD1DR2_BIT14 _ATD1DR2.Bits.BIT14 -#define ATD1DR2_BIT15 _ATD1DR2.Bits.BIT15 -#define ATD1DR2_BIT_6 _ATD1DR2.MergedBits.grpBIT_6 -#define ATD1DR2_BIT ATD1DR2_BIT_6 - - -/*** ATD1DR3 - ATD 1 Conversion Result Register 3; 0x00000136 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** ATD1DR3H - ATD 1 Conversion Result Register 3 High; 0x00000136 ***/ - union { - byte Byte; - struct { - byte BIT8 :1; /* Bit 8 */ - byte BIT9 :1; /* Bit 9 */ - byte BIT10 :1; /* Bit 10 */ - byte BIT11 :1; /* Bit 11 */ - byte BIT12 :1; /* Bit 12 */ - byte BIT13 :1; /* Bit 13 */ - byte BIT14 :1; /* Bit 14 */ - byte BIT15 :1; /* Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; - } ATD1DR3HSTR; - #define ATD1DR3H _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Byte - #define ATD1DR3H_BIT8 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT8 - #define ATD1DR3H_BIT9 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT9 - #define ATD1DR3H_BIT10 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT10 - #define ATD1DR3H_BIT11 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT11 - #define ATD1DR3H_BIT12 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT12 - #define ATD1DR3H_BIT13 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT13 - #define ATD1DR3H_BIT14 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT14 - #define ATD1DR3H_BIT15 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT15 - #define ATD1DR3H_BIT_8 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.MergedBits.grpBIT_8 - #define ATD1DR3H_BIT ATD1DR3H_BIT_8 - - /*** ATD1DR3L - ATD 1 Conversion Result Register 3 Low; 0x00000137 ***/ - union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte BIT6 :1; /* Bit 6 */ - byte BIT7 :1; /* Bit 7 */ - } Bits; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte grpBIT_6 :2; - } MergedBits; - } ATD1DR3LSTR; - #define ATD1DR3L _ATD1DR3.Overlap_STR.ATD1DR3LSTR.Byte - #define ATD1DR3L_BIT6 _ATD1DR3.Overlap_STR.ATD1DR3LSTR.Bits.BIT6 - #define ATD1DR3L_BIT7 _ATD1DR3.Overlap_STR.ATD1DR3LSTR.Bits.BIT7 - #define ATD1DR3L_BIT_6 _ATD1DR3.Overlap_STR.ATD1DR3LSTR.MergedBits.grpBIT_6 - #define ATD1DR3L_BIT ATD1DR3L_BIT_6 - - } Overlap_STR; - - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word BIT6 :1; /* Bit 6 */ - word BIT7 :1; /* Bit 7 */ - word BIT8 :1; /* Bit 8 */ - word BIT9 :1; /* Bit 9 */ - word BIT10 :1; /* Bit 10 */ - word BIT11 :1; /* Bit 11 */ - word BIT12 :1; /* Bit 12 */ - word BIT13 :1; /* Bit 13 */ - word BIT14 :1; /* Bit 14 */ - word BIT15 :1; /* Bit 15 */ - } Bits; - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word grpBIT_6 :10; - } MergedBits; -} ATD1DR3STR; -extern volatile ATD1DR3STR _ATD1DR3 @(REG_BASE + 0x00000136); -#define ATD1DR3 _ATD1DR3.Word -#define ATD1DR3_BIT6 _ATD1DR3.Bits.BIT6 -#define ATD1DR3_BIT7 _ATD1DR3.Bits.BIT7 -#define ATD1DR3_BIT8 _ATD1DR3.Bits.BIT8 -#define ATD1DR3_BIT9 _ATD1DR3.Bits.BIT9 -#define ATD1DR3_BIT10 _ATD1DR3.Bits.BIT10 -#define ATD1DR3_BIT11 _ATD1DR3.Bits.BIT11 -#define ATD1DR3_BIT12 _ATD1DR3.Bits.BIT12 -#define ATD1DR3_BIT13 _ATD1DR3.Bits.BIT13 -#define ATD1DR3_BIT14 _ATD1DR3.Bits.BIT14 -#define ATD1DR3_BIT15 _ATD1DR3.Bits.BIT15 -#define ATD1DR3_BIT_6 _ATD1DR3.MergedBits.grpBIT_6 -#define ATD1DR3_BIT ATD1DR3_BIT_6 - - -/*** ATD1DR4 - ATD 1 Conversion Result Register 4; 0x00000138 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** ATD1DR4H - ATD 1 Conversion Result Register 4 High; 0x00000138 ***/ - union { - byte Byte; - struct { - byte BIT8 :1; /* Bit 8 */ - byte BIT9 :1; /* Bit 9 */ - byte BIT10 :1; /* Bit 10 */ - byte BIT11 :1; /* Bit 11 */ - byte BIT12 :1; /* Bit 12 */ - byte BIT13 :1; /* Bit 13 */ - byte BIT14 :1; /* Bit 14 */ - byte BIT15 :1; /* Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; - } ATD1DR4HSTR; - #define ATD1DR4H _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Byte - #define ATD1DR4H_BIT8 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT8 - #define ATD1DR4H_BIT9 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT9 - #define ATD1DR4H_BIT10 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT10 - #define ATD1DR4H_BIT11 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT11 - #define ATD1DR4H_BIT12 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT12 - #define ATD1DR4H_BIT13 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT13 - #define ATD1DR4H_BIT14 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT14 - #define ATD1DR4H_BIT15 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT15 - #define ATD1DR4H_BIT_8 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.MergedBits.grpBIT_8 - #define ATD1DR4H_BIT ATD1DR4H_BIT_8 - - /*** ATD1DR4L - ATD 1 Conversion Result Register 4 Low; 0x00000139 ***/ - union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte BIT6 :1; /* Bit 6 */ - byte BIT7 :1; /* Bit 7 */ - } Bits; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte grpBIT_6 :2; - } MergedBits; - } ATD1DR4LSTR; - #define ATD1DR4L _ATD1DR4.Overlap_STR.ATD1DR4LSTR.Byte - #define ATD1DR4L_BIT6 _ATD1DR4.Overlap_STR.ATD1DR4LSTR.Bits.BIT6 - #define ATD1DR4L_BIT7 _ATD1DR4.Overlap_STR.ATD1DR4LSTR.Bits.BIT7 - #define ATD1DR4L_BIT_6 _ATD1DR4.Overlap_STR.ATD1DR4LSTR.MergedBits.grpBIT_6 - #define ATD1DR4L_BIT ATD1DR4L_BIT_6 - - } Overlap_STR; - - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word BIT6 :1; /* Bit 6 */ - word BIT7 :1; /* Bit 7 */ - word BIT8 :1; /* Bit 8 */ - word BIT9 :1; /* Bit 9 */ - word BIT10 :1; /* Bit 10 */ - word BIT11 :1; /* Bit 11 */ - word BIT12 :1; /* Bit 12 */ - word BIT13 :1; /* Bit 13 */ - word BIT14 :1; /* Bit 14 */ - word BIT15 :1; /* Bit 15 */ - } Bits; - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word grpBIT_6 :10; - } MergedBits; -} ATD1DR4STR; -extern volatile ATD1DR4STR _ATD1DR4 @(REG_BASE + 0x00000138); -#define ATD1DR4 _ATD1DR4.Word -#define ATD1DR4_BIT6 _ATD1DR4.Bits.BIT6 -#define ATD1DR4_BIT7 _ATD1DR4.Bits.BIT7 -#define ATD1DR4_BIT8 _ATD1DR4.Bits.BIT8 -#define ATD1DR4_BIT9 _ATD1DR4.Bits.BIT9 -#define ATD1DR4_BIT10 _ATD1DR4.Bits.BIT10 -#define ATD1DR4_BIT11 _ATD1DR4.Bits.BIT11 -#define ATD1DR4_BIT12 _ATD1DR4.Bits.BIT12 -#define ATD1DR4_BIT13 _ATD1DR4.Bits.BIT13 -#define ATD1DR4_BIT14 _ATD1DR4.Bits.BIT14 -#define ATD1DR4_BIT15 _ATD1DR4.Bits.BIT15 -#define ATD1DR4_BIT_6 _ATD1DR4.MergedBits.grpBIT_6 -#define ATD1DR4_BIT ATD1DR4_BIT_6 - - -/*** ATD1DR5 - ATD 1 Conversion Result Register 5; 0x0000013A ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** ATD1DR5H - ATD 1 Conversion Result Register 5 High; 0x0000013A ***/ - union { - byte Byte; - struct { - byte BIT8 :1; /* Bit 8 */ - byte BIT9 :1; /* Bit 9 */ - byte BIT10 :1; /* Bit 10 */ - byte BIT11 :1; /* Bit 11 */ - byte BIT12 :1; /* Bit 12 */ - byte BIT13 :1; /* Bit 13 */ - byte BIT14 :1; /* Bit 14 */ - byte BIT15 :1; /* Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; - } ATD1DR5HSTR; - #define ATD1DR5H _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Byte - #define ATD1DR5H_BIT8 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT8 - #define ATD1DR5H_BIT9 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT9 - #define ATD1DR5H_BIT10 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT10 - #define ATD1DR5H_BIT11 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT11 - #define ATD1DR5H_BIT12 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT12 - #define ATD1DR5H_BIT13 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT13 - #define ATD1DR5H_BIT14 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT14 - #define ATD1DR5H_BIT15 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT15 - #define ATD1DR5H_BIT_8 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.MergedBits.grpBIT_8 - #define ATD1DR5H_BIT ATD1DR5H_BIT_8 - - /*** ATD1DR5L - ATD 1 Conversion Result Register 5 Low; 0x0000013B ***/ - union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte BIT6 :1; /* Bit 6 */ - byte BIT7 :1; /* Bit 7 */ - } Bits; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte grpBIT_6 :2; - } MergedBits; - } ATD1DR5LSTR; - #define ATD1DR5L _ATD1DR5.Overlap_STR.ATD1DR5LSTR.Byte - #define ATD1DR5L_BIT6 _ATD1DR5.Overlap_STR.ATD1DR5LSTR.Bits.BIT6 - #define ATD1DR5L_BIT7 _ATD1DR5.Overlap_STR.ATD1DR5LSTR.Bits.BIT7 - #define ATD1DR5L_BIT_6 _ATD1DR5.Overlap_STR.ATD1DR5LSTR.MergedBits.grpBIT_6 - #define ATD1DR5L_BIT ATD1DR5L_BIT_6 - - } Overlap_STR; - - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word BIT6 :1; /* Bit 6 */ - word BIT7 :1; /* Bit 7 */ - word BIT8 :1; /* Bit 8 */ - word BIT9 :1; /* Bit 9 */ - word BIT10 :1; /* Bit 10 */ - word BIT11 :1; /* Bit 11 */ - word BIT12 :1; /* Bit 12 */ - word BIT13 :1; /* Bit 13 */ - word BIT14 :1; /* Bit 14 */ - word BIT15 :1; /* Bit 15 */ - } Bits; - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word grpBIT_6 :10; - } MergedBits; -} ATD1DR5STR; -extern volatile ATD1DR5STR _ATD1DR5 @(REG_BASE + 0x0000013A); -#define ATD1DR5 _ATD1DR5.Word -#define ATD1DR5_BIT6 _ATD1DR5.Bits.BIT6 -#define ATD1DR5_BIT7 _ATD1DR5.Bits.BIT7 -#define ATD1DR5_BIT8 _ATD1DR5.Bits.BIT8 -#define ATD1DR5_BIT9 _ATD1DR5.Bits.BIT9 -#define ATD1DR5_BIT10 _ATD1DR5.Bits.BIT10 -#define ATD1DR5_BIT11 _ATD1DR5.Bits.BIT11 -#define ATD1DR5_BIT12 _ATD1DR5.Bits.BIT12 -#define ATD1DR5_BIT13 _ATD1DR5.Bits.BIT13 -#define ATD1DR5_BIT14 _ATD1DR5.Bits.BIT14 -#define ATD1DR5_BIT15 _ATD1DR5.Bits.BIT15 -#define ATD1DR5_BIT_6 _ATD1DR5.MergedBits.grpBIT_6 -#define ATD1DR5_BIT ATD1DR5_BIT_6 - - -/*** ATD1DR6 - ATD 1 Conversion Result Register 6; 0x0000013C ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** ATD1DR6H - ATD 1 Conversion Result Register 6 High; 0x0000013C ***/ - union { - byte Byte; - struct { - byte BIT8 :1; /* Bit 8 */ - byte BIT9 :1; /* Bit 9 */ - byte BIT10 :1; /* Bit 10 */ - byte BIT11 :1; /* Bit 11 */ - byte BIT12 :1; /* Bit 12 */ - byte BIT13 :1; /* Bit 13 */ - byte BIT14 :1; /* Bit 14 */ - byte BIT15 :1; /* Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; - } ATD1DR6HSTR; - #define ATD1DR6H _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Byte - #define ATD1DR6H_BIT8 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT8 - #define ATD1DR6H_BIT9 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT9 - #define ATD1DR6H_BIT10 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT10 - #define ATD1DR6H_BIT11 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT11 - #define ATD1DR6H_BIT12 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT12 - #define ATD1DR6H_BIT13 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT13 - #define ATD1DR6H_BIT14 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT14 - #define ATD1DR6H_BIT15 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT15 - #define ATD1DR6H_BIT_8 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.MergedBits.grpBIT_8 - #define ATD1DR6H_BIT ATD1DR6H_BIT_8 - - /*** ATD1DR6L - ATD 1 Conversion Result Register 6 Low; 0x0000013D ***/ - union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte BIT6 :1; /* Bit 6 */ - byte BIT7 :1; /* Bit 7 */ - } Bits; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte grpBIT_6 :2; - } MergedBits; - } ATD1DR6LSTR; - #define ATD1DR6L _ATD1DR6.Overlap_STR.ATD1DR6LSTR.Byte - #define ATD1DR6L_BIT6 _ATD1DR6.Overlap_STR.ATD1DR6LSTR.Bits.BIT6 - #define ATD1DR6L_BIT7 _ATD1DR6.Overlap_STR.ATD1DR6LSTR.Bits.BIT7 - #define ATD1DR6L_BIT_6 _ATD1DR6.Overlap_STR.ATD1DR6LSTR.MergedBits.grpBIT_6 - #define ATD1DR6L_BIT ATD1DR6L_BIT_6 - - } Overlap_STR; - - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word BIT6 :1; /* Bit 6 */ - word BIT7 :1; /* Bit 7 */ - word BIT8 :1; /* Bit 8 */ - word BIT9 :1; /* Bit 9 */ - word BIT10 :1; /* Bit 10 */ - word BIT11 :1; /* Bit 11 */ - word BIT12 :1; /* Bit 12 */ - word BIT13 :1; /* Bit 13 */ - word BIT14 :1; /* Bit 14 */ - word BIT15 :1; /* Bit 15 */ - } Bits; - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word grpBIT_6 :10; - } MergedBits; -} ATD1DR6STR; -extern volatile ATD1DR6STR _ATD1DR6 @(REG_BASE + 0x0000013C); -#define ATD1DR6 _ATD1DR6.Word -#define ATD1DR6_BIT6 _ATD1DR6.Bits.BIT6 -#define ATD1DR6_BIT7 _ATD1DR6.Bits.BIT7 -#define ATD1DR6_BIT8 _ATD1DR6.Bits.BIT8 -#define ATD1DR6_BIT9 _ATD1DR6.Bits.BIT9 -#define ATD1DR6_BIT10 _ATD1DR6.Bits.BIT10 -#define ATD1DR6_BIT11 _ATD1DR6.Bits.BIT11 -#define ATD1DR6_BIT12 _ATD1DR6.Bits.BIT12 -#define ATD1DR6_BIT13 _ATD1DR6.Bits.BIT13 -#define ATD1DR6_BIT14 _ATD1DR6.Bits.BIT14 -#define ATD1DR6_BIT15 _ATD1DR6.Bits.BIT15 -#define ATD1DR6_BIT_6 _ATD1DR6.MergedBits.grpBIT_6 -#define ATD1DR6_BIT ATD1DR6_BIT_6 - - -/*** ATD1DR7 - ATD 1 Conversion Result Register 7; 0x0000013E ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** ATD1DR7H - ATD 1 Conversion Result Register 7 High; 0x0000013E ***/ - union { - byte Byte; - struct { - byte BIT8 :1; /* Bit 8 */ - byte BIT9 :1; /* Bit 9 */ - byte BIT10 :1; /* Bit 10 */ - byte BIT11 :1; /* Bit 11 */ - byte BIT12 :1; /* Bit 12 */ - byte BIT13 :1; /* Bit 13 */ - byte BIT14 :1; /* Bit 14 */ - byte BIT15 :1; /* Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; - } ATD1DR7HSTR; - #define ATD1DR7H _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Byte - #define ATD1DR7H_BIT8 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT8 - #define ATD1DR7H_BIT9 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT9 - #define ATD1DR7H_BIT10 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT10 - #define ATD1DR7H_BIT11 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT11 - #define ATD1DR7H_BIT12 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT12 - #define ATD1DR7H_BIT13 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT13 - #define ATD1DR7H_BIT14 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT14 - #define ATD1DR7H_BIT15 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT15 - #define ATD1DR7H_BIT_8 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.MergedBits.grpBIT_8 - #define ATD1DR7H_BIT ATD1DR7H_BIT_8 - - /*** ATD1DR7L - ATD 1 Conversion Result Register 7 Low; 0x0000013F ***/ - union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte BIT6 :1; /* Bit 6 */ - byte BIT7 :1; /* Bit 7 */ - } Bits; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte grpBIT_6 :2; - } MergedBits; - } ATD1DR7LSTR; - #define ATD1DR7L _ATD1DR7.Overlap_STR.ATD1DR7LSTR.Byte - #define ATD1DR7L_BIT6 _ATD1DR7.Overlap_STR.ATD1DR7LSTR.Bits.BIT6 - #define ATD1DR7L_BIT7 _ATD1DR7.Overlap_STR.ATD1DR7LSTR.Bits.BIT7 - #define ATD1DR7L_BIT_6 _ATD1DR7.Overlap_STR.ATD1DR7LSTR.MergedBits.grpBIT_6 - #define ATD1DR7L_BIT ATD1DR7L_BIT_6 - - } Overlap_STR; - - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word BIT6 :1; /* Bit 6 */ - word BIT7 :1; /* Bit 7 */ - word BIT8 :1; /* Bit 8 */ - word BIT9 :1; /* Bit 9 */ - word BIT10 :1; /* Bit 10 */ - word BIT11 :1; /* Bit 11 */ - word BIT12 :1; /* Bit 12 */ - word BIT13 :1; /* Bit 13 */ - word BIT14 :1; /* Bit 14 */ - word BIT15 :1; /* Bit 15 */ - } Bits; - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word grpBIT_6 :10; - } MergedBits; -} ATD1DR7STR; -extern volatile ATD1DR7STR _ATD1DR7 @(REG_BASE + 0x0000013E); -#define ATD1DR7 _ATD1DR7.Word -#define ATD1DR7_BIT6 _ATD1DR7.Bits.BIT6 -#define ATD1DR7_BIT7 _ATD1DR7.Bits.BIT7 -#define ATD1DR7_BIT8 _ATD1DR7.Bits.BIT8 -#define ATD1DR7_BIT9 _ATD1DR7.Bits.BIT9 -#define ATD1DR7_BIT10 _ATD1DR7.Bits.BIT10 -#define ATD1DR7_BIT11 _ATD1DR7.Bits.BIT11 -#define ATD1DR7_BIT12 _ATD1DR7.Bits.BIT12 -#define ATD1DR7_BIT13 _ATD1DR7.Bits.BIT13 -#define ATD1DR7_BIT14 _ATD1DR7.Bits.BIT14 -#define ATD1DR7_BIT15 _ATD1DR7.Bits.BIT15 -#define ATD1DR7_BIT_6 _ATD1DR7.MergedBits.grpBIT_6 -#define ATD1DR7_BIT ATD1DR7_BIT_6 - - -/*** PORTE - Port E Register; 0x00000008 ***/ -typedef union { - byte Byte; - struct { - byte BIT0 :1; /* Port E Bit 0, XIRQ */ - byte BIT1 :1; /* Port E Bit 1, IRQ */ - byte BIT2 :1; /* Port E Bit 2, R/W */ - byte BIT3 :1; /* Port E Bit 3, LSTRB, TAGLO */ - byte BIT4 :1; /* Port E Bit 4, ECLK */ - byte BIT5 :1; /* Port E Bit 5, MODA, IPIPE0, RCRTO */ - byte BIT6 :1; /* Port E Bit 6, MODB, IPIPE1, SCGTO */ - byte BIT7 :1; /* Port E Bit 7, XCLKS, NOACC */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; -} PORTESTR; -extern volatile PORTESTR _PORTE @(REG_BASE + 0x00000008); -#define PORTE _PORTE.Byte -#define PORTE_BIT0 _PORTE.Bits.BIT0 -#define PORTE_BIT1 _PORTE.Bits.BIT1 -#define PORTE_BIT2 _PORTE.Bits.BIT2 -#define PORTE_BIT3 _PORTE.Bits.BIT3 -#define PORTE_BIT4 _PORTE.Bits.BIT4 -#define PORTE_BIT5 _PORTE.Bits.BIT5 -#define PORTE_BIT6 _PORTE.Bits.BIT6 -#define PORTE_BIT7 _PORTE.Bits.BIT7 -#define PORTE_BIT _PORTE.MergedBits.grpBIT - - -/*** DDRE - Port E Data Direction Register; 0x00000009 ***/ -typedef union { - byte Byte; - struct { - byte BIT0 :1; /* Data Direction Port A Bit 0 */ - byte BIT1 :1; /* Data Direction Port A Bit 1 */ - byte BIT2 :1; /* Data Direction Port A Bit 2 */ - byte BIT3 :1; /* Data Direction Port A Bit 3 */ - byte BIT4 :1; /* Data Direction Port A Bit 4 */ - byte BIT5 :1; /* Data Direction Port A Bit 5 */ - byte BIT6 :1; /* Data Direction Port A Bit 6 */ - byte BIT7 :1; /* Data Direction Port A Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; -} DDRESTR; -extern volatile DDRESTR _DDRE @(REG_BASE + 0x00000009); -#define DDRE _DDRE.Byte -#define DDRE_BIT0 _DDRE.Bits.BIT0 -#define DDRE_BIT1 _DDRE.Bits.BIT1 -#define DDRE_BIT2 _DDRE.Bits.BIT2 -#define DDRE_BIT3 _DDRE.Bits.BIT3 -#define DDRE_BIT4 _DDRE.Bits.BIT4 -#define DDRE_BIT5 _DDRE.Bits.BIT5 -#define DDRE_BIT6 _DDRE.Bits.BIT6 -#define DDRE_BIT7 _DDRE.Bits.BIT7 -#define DDRE_BIT _DDRE.MergedBits.grpBIT - - -/*** PEAR - Port E Assignment Register; 0x0000000A ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte :1; - byte RDWE :1; /* Read / Write Enable */ - byte LSTRE :1; /* Low Strobe (LSTRB) Enable */ - byte NECLK :1; /* No External E Clock */ - byte PIPOE :1; /* Pipe Status Signal Output Enable */ - byte :1; - byte NOACCE :1; /* CPU No Access Output Enable */ - } Bits; -} PEARSTR; -extern volatile PEARSTR _PEAR @(REG_BASE + 0x0000000A); -#define PEAR _PEAR.Byte -#define PEAR_RDWE _PEAR.Bits.RDWE -#define PEAR_LSTRE _PEAR.Bits.LSTRE -#define PEAR_NECLK _PEAR.Bits.NECLK -#define PEAR_PIPOE _PEAR.Bits.PIPOE -#define PEAR_NOACCE _PEAR.Bits.NOACCE - - -/*** MODE - Mode Register; 0x0000000B ***/ -typedef union { - byte Byte; - struct { - byte EME :1; /* Emulate Port E */ - byte EMK :1; /* Emulate Port K */ - byte :1; - byte IVIS :1; /* Internal Visibility */ - byte :1; - byte MODA :1; /* Mode Select Bit A */ - byte MODB :1; /* Mode Select Bit B */ - byte MODC :1; /* Mode Select Bit C */ - } Bits; -} MODESTR; -extern volatile MODESTR _MODE @(REG_BASE + 0x0000000B); -#define MODE _MODE.Byte -#define MODE_EME _MODE.Bits.EME -#define MODE_EMK _MODE.Bits.EMK -#define MODE_IVIS _MODE.Bits.IVIS -#define MODE_MODA _MODE.Bits.MODA -#define MODE_MODB _MODE.Bits.MODB -#define MODE_MODC _MODE.Bits.MODC - - -/*** PUCR - Pull-Up Control Register; 0x0000000C ***/ -typedef union { - byte Byte; - struct { - byte PUPAE :1; /* Pull-Up Port A Enable */ - byte PUPBE :1; /* Pull-Up Port B Enable */ - byte :1; - byte :1; - byte PUPEE :1; /* Pull-Up Port E Enable */ - byte :1; - byte :1; - byte PUPKE :1; /* Pull-Up Port K Enable */ - } Bits; -} PUCRSTR; -extern volatile PUCRSTR _PUCR @(REG_BASE + 0x0000000C); -#define PUCR _PUCR.Byte -#define PUCR_PUPAE _PUCR.Bits.PUPAE -#define PUCR_PUPBE _PUCR.Bits.PUPBE -#define PUCR_PUPEE _PUCR.Bits.PUPEE -#define PUCR_PUPKE _PUCR.Bits.PUPKE - - -/*** RDRIV - Reduced Drive of I/O Lines; 0x0000000D ***/ -typedef union { - byte Byte; - struct { - byte RDPA :1; /* Reduced Drive of Port A */ - byte RDPB :1; /* Reduced Drive of Port B */ - byte :1; - byte :1; - byte RDPE :1; /* Reduced Drive of Port E */ - byte :1; - byte :1; - byte RDPK :1; /* Reduced Drive of Port K */ - } Bits; -} RDRIVSTR; -extern volatile RDRIVSTR _RDRIV @(REG_BASE + 0x0000000D); -#define RDRIV _RDRIV.Byte -#define RDRIV_RDPA _RDRIV.Bits.RDPA -#define RDRIV_RDPB _RDRIV.Bits.RDPB -#define RDRIV_RDPE _RDRIV.Bits.RDPE -#define RDRIV_RDPK _RDRIV.Bits.RDPK - - -/*** EBICTL - External Bus Interface Control; 0x0000000E ***/ -typedef union { - byte Byte; - struct { - byte ESTR :1; /* E Stretches */ - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; -} EBICTLSTR; -extern volatile EBICTLSTR _EBICTL @(REG_BASE + 0x0000000E); -#define EBICTL _EBICTL.Byte -#define EBICTL_ESTR _EBICTL.Bits.ESTR - - -/*** INITRM - Initialization of Internal RAM Position Register; 0x00000010 ***/ -typedef union { - byte Byte; - struct { - byte RAMHAL :1; /* Internal RAM map alignment */ - byte :1; - byte :1; - byte RAM11 :1; /* Internal RAM map position Bit 11 */ - byte RAM12 :1; /* Internal RAM map position Bit 12 */ - byte RAM13 :1; /* Internal RAM map position Bit 13 */ - byte RAM14 :1; /* Internal RAM map position Bit 14 */ - byte RAM15 :1; /* Internal RAM map position Bit 15 */ - } Bits; - struct { - byte :1; - byte :1; - byte :1; - byte grpRAM_11 :5; - } MergedBits; -} INITRMSTR; -extern volatile INITRMSTR _INITRM @(REG_BASE + 0x00000010); -#define INITRM _INITRM.Byte -#define INITRM_RAMHAL _INITRM.Bits.RAMHAL -#define INITRM_RAM11 _INITRM.Bits.RAM11 -#define INITRM_RAM12 _INITRM.Bits.RAM12 -#define INITRM_RAM13 _INITRM.Bits.RAM13 -#define INITRM_RAM14 _INITRM.Bits.RAM14 -#define INITRM_RAM15 _INITRM.Bits.RAM15 -#define INITRM_RAM_11 _INITRM.MergedBits.grpRAM_11 -#define INITRM_RAM INITRM_RAM_11 - - -/*** INITRG - Initialization of Internal Register Position Register; 0x00000011 ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte REG11 :1; /* Internal register map position REG11 */ - byte REG12 :1; /* Internal register map position REG12 */ - byte REG13 :1; /* Internal register map position REG13 */ - byte REG14 :1; /* Internal register map position REG14 */ - byte :1; - } Bits; - struct { - byte :1; - byte :1; - byte :1; - byte grpREG_11 :4; - byte :1; - } MergedBits; -} INITRGSTR; -extern volatile INITRGSTR _INITRG @(REG_BASE + 0x00000011); -#define INITRG _INITRG.Byte -#define INITRG_REG11 _INITRG.Bits.REG11 -#define INITRG_REG12 _INITRG.Bits.REG12 -#define INITRG_REG13 _INITRG.Bits.REG13 -#define INITRG_REG14 _INITRG.Bits.REG14 -#define INITRG_REG_11 _INITRG.MergedBits.grpREG_11 -#define INITRG_REG INITRG_REG_11 - - -/*** INITEE - Initialization of Internal EEPROM Position Register; 0x00000012 ***/ -typedef union { - byte Byte; - struct { - byte EEON :1; /* Internal EEPROM On */ - byte :1; - byte :1; - byte :1; - byte EE12 :1; /* Internal EEPROM map position Bit 12 */ - byte EE13 :1; /* Internal EEPROM map position Bit 13 */ - byte EE14 :1; /* Internal EEPROM map position Bit 14 */ - byte EE15 :1; /* Internal EEPROM map position Bit 15 */ - } Bits; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte grpEE_12 :4; - } MergedBits; -} INITEESTR; -extern volatile INITEESTR _INITEE @(REG_BASE + 0x00000012); -#define INITEE _INITEE.Byte -#define INITEE_EEON _INITEE.Bits.EEON -#define INITEE_EE12 _INITEE.Bits.EE12 -#define INITEE_EE13 _INITEE.Bits.EE13 -#define INITEE_EE14 _INITEE.Bits.EE14 -#define INITEE_EE15 _INITEE.Bits.EE15 -#define INITEE_EE_12 _INITEE.MergedBits.grpEE_12 -#define INITEE_EE INITEE_EE_12 - - -/*** MISC - Miscellaneous Mapping Control Register; 0x00000013 ***/ -typedef union { - byte Byte; - struct { - byte ROMON :1; /* Enable Flash EEPROM */ - byte ROMHM :1; /* Flash EEPROM only in second half of memory map */ - byte EXSTR0 :1; /* External Access Stretch Bit 0 */ - byte EXSTR1 :1; /* External Access Stretch Bit 1 */ - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte :1; - byte :1; - byte grpEXSTR :2; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} MISCSTR; -extern volatile MISCSTR _MISC @(REG_BASE + 0x00000013); -#define MISC _MISC.Byte -#define MISC_ROMON _MISC.Bits.ROMON -#define MISC_ROMHM _MISC.Bits.ROMHM -#define MISC_EXSTR0 _MISC.Bits.EXSTR0 -#define MISC_EXSTR1 _MISC.Bits.EXSTR1 -#define MISC_EXSTR _MISC.MergedBits.grpEXSTR - - -/*** MTST0 - MTST0; 0x00000014 ***/ -typedef union { - byte Byte; - struct { - byte BIT0 :1; /* MTST0 Bit 0 */ - byte BIT1 :1; /* MTST0 Bit 1 */ - byte BIT2 :1; /* MTST0 Bit 2 */ - byte BIT3 :1; /* MTST0 Bit 3 */ - byte BIT4 :1; /* MTST0 Bit 4 */ - byte BIT5 :1; /* MTST0 Bit 5 */ - byte BIT6 :1; /* MTST0 Bit 6 */ - byte BIT7 :1; /* MTST0 Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; -} MTST0STR; -extern volatile MTST0STR _MTST0 @(REG_BASE + 0x00000014); -#define MTST0 _MTST0.Byte -#define MTST0_BIT0 _MTST0.Bits.BIT0 -#define MTST0_BIT1 _MTST0.Bits.BIT1 -#define MTST0_BIT2 _MTST0.Bits.BIT2 -#define MTST0_BIT3 _MTST0.Bits.BIT3 -#define MTST0_BIT4 _MTST0.Bits.BIT4 -#define MTST0_BIT5 _MTST0.Bits.BIT5 -#define MTST0_BIT6 _MTST0.Bits.BIT6 -#define MTST0_BIT7 _MTST0.Bits.BIT7 -#define MTST0_BIT _MTST0.MergedBits.grpBIT - - -/*** ITCR - Interrupt Test Control Register; 0x00000015 ***/ -typedef union { - byte Byte; - struct { - byte ADR0 :1; /* Test register select Bit 0 */ - byte ADR1 :1; /* Test register select Bit 1 */ - byte ADR2 :1; /* Test register select Bit 2 */ - byte ADR3 :1; /* Test register select Bit 3 */ - byte WRTINT :1; /* Write to the Interrupt Test Registers */ - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpADR :4; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} ITCRSTR; -extern volatile ITCRSTR _ITCR @(REG_BASE + 0x00000015); -#define ITCR _ITCR.Byte -#define ITCR_ADR0 _ITCR.Bits.ADR0 -#define ITCR_ADR1 _ITCR.Bits.ADR1 -#define ITCR_ADR2 _ITCR.Bits.ADR2 -#define ITCR_ADR3 _ITCR.Bits.ADR3 -#define ITCR_WRTINT _ITCR.Bits.WRTINT -#define ITCR_ADR _ITCR.MergedBits.grpADR - - -/*** ITEST - Interrupt Test Register; 0x00000016 ***/ -typedef union { - byte Byte; - struct { - byte INT0 :1; /* Interrupt Test Register Bit 0 */ - byte INT2 :1; /* Interrupt Test Register Bit 1 */ - byte INT4 :1; /* Interrupt Test Register Bit 2 */ - byte INT6 :1; /* Interrupt Test Register Bit 3 */ - byte INT8 :1; /* Interrupt Test Register Bit 4 */ - byte INTA :1; /* Interrupt Test Register Bit 5 */ - byte INTC :1; /* Interrupt Test Register Bit 6 */ - byte INTE :1; /* Interrupt Test Register Bit 7 */ - } Bits; -} ITESTSTR; -extern volatile ITESTSTR _ITEST @(REG_BASE + 0x00000016); -#define ITEST _ITEST.Byte -#define ITEST_INT0 _ITEST.Bits.INT0 -#define ITEST_INT2 _ITEST.Bits.INT2 -#define ITEST_INT4 _ITEST.Bits.INT4 -#define ITEST_INT6 _ITEST.Bits.INT6 -#define ITEST_INT8 _ITEST.Bits.INT8 -#define ITEST_INTA _ITEST.Bits.INTA -#define ITEST_INTC _ITEST.Bits.INTC -#define ITEST_INTE _ITEST.Bits.INTE - - -/*** MTST1 - MTST1; 0x00000017 ***/ -typedef union { - byte Byte; - struct { - byte BIT0 :1; /* MTST1 Bit 0 */ - byte BIT1 :1; /* MTST1 Bit 1 */ - byte BIT2 :1; /* MTST1 Bit 2 */ - byte BIT3 :1; /* MTST1 Bit 3 */ - byte BIT4 :1; /* MTST1 Bit 4 */ - byte BIT5 :1; /* MTST1 Bit 5 */ - byte BIT6 :1; /* MTST1 Bit 6 */ - byte BIT7 :1; /* MTST1 Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; -} MTST1STR; -extern volatile MTST1STR _MTST1 @(REG_BASE + 0x00000017); -#define MTST1 _MTST1.Byte -#define MTST1_BIT0 _MTST1.Bits.BIT0 -#define MTST1_BIT1 _MTST1.Bits.BIT1 -#define MTST1_BIT2 _MTST1.Bits.BIT2 -#define MTST1_BIT3 _MTST1.Bits.BIT3 -#define MTST1_BIT4 _MTST1.Bits.BIT4 -#define MTST1_BIT5 _MTST1.Bits.BIT5 -#define MTST1_BIT6 _MTST1.Bits.BIT6 -#define MTST1_BIT7 _MTST1.Bits.BIT7 -#define MTST1_BIT _MTST1.MergedBits.grpBIT - - -/*** PARTIDH - Part ID Register High; 0x0000001A ***/ -typedef union { - byte Byte; - struct { - byte ID15 :1; /* Part ID Register Bit 15 */ - byte ID14 :1; /* Part ID Register Bit 14 */ - byte ID13 :1; /* Part ID Register Bit 13 */ - byte ID12 :1; /* Part ID Register Bit 12 */ - byte ID11 :1; /* Part ID Register Bit 11 */ - byte ID10 :1; /* Part ID Register Bit 10 */ - byte ID9 :1; /* Part ID Register Bit 9 */ - byte ID8 :1; /* Part ID Register Bit 8 */ - } Bits; -} PARTIDHSTR; -extern volatile PARTIDHSTR _PARTIDH @(REG_BASE + 0x0000001A); -#define PARTIDH _PARTIDH.Byte -#define PARTIDH_ID15 _PARTIDH.Bits.ID15 -#define PARTIDH_ID14 _PARTIDH.Bits.ID14 -#define PARTIDH_ID13 _PARTIDH.Bits.ID13 -#define PARTIDH_ID12 _PARTIDH.Bits.ID12 -#define PARTIDH_ID11 _PARTIDH.Bits.ID11 -#define PARTIDH_ID10 _PARTIDH.Bits.ID10 -#define PARTIDH_ID9 _PARTIDH.Bits.ID9 -#define PARTIDH_ID8 _PARTIDH.Bits.ID8 - - -/*** PARTIDL - Part ID Register Low; 0x0000001B ***/ -typedef union { - byte Byte; - struct { - byte ID0 :1; /* Part ID Register Bit 0 */ - byte ID1 :1; /* Part ID Register Bit 1 */ - byte ID2 :1; /* Part ID Register Bit 2 */ - byte ID3 :1; /* Part ID Register Bit 3 */ - byte ID4 :1; /* Part ID Register Bit 4 */ - byte ID5 :1; /* Part ID Register Bit 5 */ - byte ID6 :1; /* Part ID Register Bit 6 */ - byte ID7 :1; /* Part ID Register Bit 7 */ - } Bits; - struct { - byte grpID :8; - } MergedBits; -} PARTIDLSTR; -extern volatile PARTIDLSTR _PARTIDL @(REG_BASE + 0x0000001B); -#define PARTIDL _PARTIDL.Byte -#define PARTIDL_ID0 _PARTIDL.Bits.ID0 -#define PARTIDL_ID1 _PARTIDL.Bits.ID1 -#define PARTIDL_ID2 _PARTIDL.Bits.ID2 -#define PARTIDL_ID3 _PARTIDL.Bits.ID3 -#define PARTIDL_ID4 _PARTIDL.Bits.ID4 -#define PARTIDL_ID5 _PARTIDL.Bits.ID5 -#define PARTIDL_ID6 _PARTIDL.Bits.ID6 -#define PARTIDL_ID7 _PARTIDL.Bits.ID7 -#define PARTIDL_ID _PARTIDL.MergedBits.grpID - - -/*** MEMSIZ0 - Memory Size Register Zero; 0x0000001C ***/ -typedef union { - byte Byte; - struct { - byte ram_sw0 :1; /* Allocated RAM Memory Space Bit 0 */ - byte ram_sw1 :1; /* Allocated RAM Memory Space Bit 1 */ - byte ram_sw2 :1; /* Allocated RAM Memory Space Bit 2 */ - byte :1; - byte eep_sw0 :1; /* Allocated EEPROM Memory Space Bit 0 */ - byte eep_sw1 :1; /* Allocated EEPROM Memory Space Bit 1 */ - byte :1; - byte reg_sw0 :1; /* Allocated System Register Space */ - } Bits; - struct { - byte grpram_sw :3; - byte :1; - byte grpeep_sw :2; - byte :1; - byte grpreg_sw :1; - } MergedBits; -} MEMSIZ0STR; -extern volatile MEMSIZ0STR _MEMSIZ0 @(REG_BASE + 0x0000001C); -#define MEMSIZ0 _MEMSIZ0.Byte -#define MEMSIZ0_ram_sw0 _MEMSIZ0.Bits.ram_sw0 -#define MEMSIZ0_ram_sw1 _MEMSIZ0.Bits.ram_sw1 -#define MEMSIZ0_ram_sw2 _MEMSIZ0.Bits.ram_sw2 -#define MEMSIZ0_eep_sw0 _MEMSIZ0.Bits.eep_sw0 -#define MEMSIZ0_eep_sw1 _MEMSIZ0.Bits.eep_sw1 -#define MEMSIZ0_reg_sw0 _MEMSIZ0.Bits.reg_sw0 -#define MEMSIZ0_ram_sw _MEMSIZ0.MergedBits.grpram_sw -#define MEMSIZ0_eep_sw _MEMSIZ0.MergedBits.grpeep_sw - - -/*** MEMSIZ1 - Memory Size Register One; 0x0000001D ***/ -typedef union { - byte Byte; - struct { - byte pag_sw0 :1; /* Allocated Off-Chip Memory Options Bit 0 */ - byte pag_sw1 :1; /* Allocated Off-Chip Memory Options Bit 1 */ - byte :1; - byte :1; - byte :1; - byte :1; - byte rom_sw0 :1; /* Allocated Flash EEPROM/ROM Physical Memory Space Bit 0 */ - byte rom_sw1 :1; /* Allocated Flash EEPROM/ROM Physical Memory Space Bit 1 */ - } Bits; - struct { - byte grppag_sw :2; - byte :1; - byte :1; - byte :1; - byte :1; - byte grprom_sw :2; - } MergedBits; -} MEMSIZ1STR; -extern volatile MEMSIZ1STR _MEMSIZ1 @(REG_BASE + 0x0000001D); -#define MEMSIZ1 _MEMSIZ1.Byte -#define MEMSIZ1_pag_sw0 _MEMSIZ1.Bits.pag_sw0 -#define MEMSIZ1_pag_sw1 _MEMSIZ1.Bits.pag_sw1 -#define MEMSIZ1_rom_sw0 _MEMSIZ1.Bits.rom_sw0 -#define MEMSIZ1_rom_sw1 _MEMSIZ1.Bits.rom_sw1 -#define MEMSIZ1_pag_sw _MEMSIZ1.MergedBits.grppag_sw -#define MEMSIZ1_rom_sw _MEMSIZ1.MergedBits.grprom_sw - - -/*** INTCR - Interrupt Control Register; 0x0000001E ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte IRQEN :1; /* External IRQ Enable */ - byte IRQE :1; /* IRQ Select Edge Sensitive Only */ - } Bits; -} INTCRSTR; -extern volatile INTCRSTR _INTCR @(REG_BASE + 0x0000001E); -#define INTCR _INTCR.Byte -#define INTCR_IRQEN _INTCR.Bits.IRQEN -#define INTCR_IRQE _INTCR.Bits.IRQE - - -/*** HPRIO - Highest Priority I Interrupt; 0x0000001F ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte PSEL1 :1; /* Highest Priority I Interrupt Bit 1 */ - byte PSEL2 :1; /* Highest Priority I Interrupt Bit 2 */ - byte PSEL3 :1; /* Highest Priority I Interrupt Bit 3 */ - byte PSEL4 :1; /* Highest Priority I Interrupt Bit 4 */ - byte PSEL5 :1; /* Highest Priority I Interrupt Bit 5 */ - byte PSEL6 :1; /* Highest Priority I Interrupt Bit 6 */ - byte PSEL7 :1; /* Highest Priority I Interrupt Bit 7 */ - } Bits; - struct { - byte :1; - byte grpPSEL_1 :7; - } MergedBits; -} HPRIOSTR; -extern volatile HPRIOSTR _HPRIO @(REG_BASE + 0x0000001F); -#define HPRIO _HPRIO.Byte -#define HPRIO_PSEL1 _HPRIO.Bits.PSEL1 -#define HPRIO_PSEL2 _HPRIO.Bits.PSEL2 -#define HPRIO_PSEL3 _HPRIO.Bits.PSEL3 -#define HPRIO_PSEL4 _HPRIO.Bits.PSEL4 -#define HPRIO_PSEL5 _HPRIO.Bits.PSEL5 -#define HPRIO_PSEL6 _HPRIO.Bits.PSEL6 -#define HPRIO_PSEL7 _HPRIO.Bits.PSEL7 -#define HPRIO_PSEL_1 _HPRIO.MergedBits.grpPSEL_1 -#define HPRIO_PSEL HPRIO_PSEL_1 - - -/*** BKPCT0 - Breakpoint Control Register 0; 0x00000028 ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte BKTAG :1; /* Breakpoint on Tag */ - byte BKBDM :1; /* Breakpoint Background Debug Mode Enable */ - byte BKFULL :1; /* Full Breakpoint Mode Enable */ - byte BKEN :1; /* Breakpoint Enable */ - } Bits; -} BKPCT0STR; -extern volatile BKPCT0STR _BKPCT0 @(REG_BASE + 0x00000028); -#define BKPCT0 _BKPCT0.Byte -#define BKPCT0_BKTAG _BKPCT0.Bits.BKTAG -#define BKPCT0_BKBDM _BKPCT0.Bits.BKBDM -#define BKPCT0_BKFULL _BKPCT0.Bits.BKFULL -#define BKPCT0_BKEN _BKPCT0.Bits.BKEN - - -/*** BKPCT1 - Breakpoint Control Register 1; 0x00000029 ***/ -typedef union { - byte Byte; - struct { - byte BK1RW :1; /* R/W Compare Value 1 */ - byte BK1RWE :1; /* R/W Compare Enable 1 */ - byte BK0RW :1; /* R/W Compare Value 0 */ - byte BK0RWE :1; /* R/W Compare Enable 0 */ - byte BK1MBL :1; /* Breakpoint Mask Low Byte for Second Address */ - byte BK1MBH :1; /* Breakpoint Mask High Byte for Second Address */ - byte BK0MBL :1; /* Breakpoint Mask Low Byte for First Address */ - byte BK0MBH :1; /* Breakpoint Mask High Byte for First Address */ - } Bits; -} BKPCT1STR; -extern volatile BKPCT1STR _BKPCT1 @(REG_BASE + 0x00000029); -#define BKPCT1 _BKPCT1.Byte -#define BKPCT1_BK1RW _BKPCT1.Bits.BK1RW -#define BKPCT1_BK1RWE _BKPCT1.Bits.BK1RWE -#define BKPCT1_BK0RW _BKPCT1.Bits.BK0RW -#define BKPCT1_BK0RWE _BKPCT1.Bits.BK0RWE -#define BKPCT1_BK1MBL _BKPCT1.Bits.BK1MBL -#define BKPCT1_BK1MBH _BKPCT1.Bits.BK1MBH -#define BKPCT1_BK0MBL _BKPCT1.Bits.BK0MBL -#define BKPCT1_BK0MBH _BKPCT1.Bits.BK0MBH - - -/*** BKP0X - First Address Memory Expansion Breakpoint Register; 0x0000002A ***/ -typedef union { - byte Byte; - struct { - byte BK0V0 :1; /* First Address Breakpoint Expansion Address Value Bit 0 */ - byte BK0V1 :1; /* First Address Breakpoint Expansion Address Value Bit 1 */ - byte BK0V2 :1; /* First Address Breakpoint Expansion Address Value Bit 2 */ - byte BK0V3 :1; /* First Address Breakpoint Expansion Address Value Bit 3 */ - byte BK0V4 :1; /* First Address Breakpoint Expansion Address Value Bit 4 */ - byte BK0V5 :1; /* First Address Breakpoint Expansion Address Value Bit 5 */ - byte :1; - byte :1; - } Bits; - struct { - byte grpBK0V :6; - byte :1; - byte :1; - } MergedBits; -} BKP0XSTR; -extern volatile BKP0XSTR _BKP0X @(REG_BASE + 0x0000002A); -#define BKP0X _BKP0X.Byte -#define BKP0X_BK0V0 _BKP0X.Bits.BK0V0 -#define BKP0X_BK0V1 _BKP0X.Bits.BK0V1 -#define BKP0X_BK0V2 _BKP0X.Bits.BK0V2 -#define BKP0X_BK0V3 _BKP0X.Bits.BK0V3 -#define BKP0X_BK0V4 _BKP0X.Bits.BK0V4 -#define BKP0X_BK0V5 _BKP0X.Bits.BK0V5 -#define BKP0X_BK0V _BKP0X.MergedBits.grpBK0V - - -/*** BKP0H - First Address High Byte Breakpoint Register; 0x0000002B ***/ -typedef union { - byte Byte; - struct { - byte BIT8 :1; /* First Address Breakpoint Register Bit 8 */ - byte BIT9 :1; /* First Address Breakpoint Register Bit 9 */ - byte BIT10 :1; /* First Address Breakpoint Register Bit 10 */ - byte BIT11 :1; /* First Address Breakpoint Register Bit 11 */ - byte BIT12 :1; /* First Address Breakpoint Register Bit 12 */ - byte BIT13 :1; /* First Address Breakpoint Register Bit 13 */ - byte BIT14 :1; /* First Address Breakpoint Register Bit 14 */ - byte BIT15 :1; /* First Address Breakpoint Register Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; -} BKP0HSTR; -extern volatile BKP0HSTR _BKP0H @(REG_BASE + 0x0000002B); -#define BKP0H _BKP0H.Byte -#define BKP0H_BIT8 _BKP0H.Bits.BIT8 -#define BKP0H_BIT9 _BKP0H.Bits.BIT9 -#define BKP0H_BIT10 _BKP0H.Bits.BIT10 -#define BKP0H_BIT11 _BKP0H.Bits.BIT11 -#define BKP0H_BIT12 _BKP0H.Bits.BIT12 -#define BKP0H_BIT13 _BKP0H.Bits.BIT13 -#define BKP0H_BIT14 _BKP0H.Bits.BIT14 -#define BKP0H_BIT15 _BKP0H.Bits.BIT15 -#define BKP0H_BIT_8 _BKP0H.MergedBits.grpBIT_8 -#define BKP0H_BIT BKP0H_BIT_8 - - -/*** BKP0L - First Address Low Byte Breakpoint Register; 0x0000002C ***/ -typedef union { - byte Byte; - struct { - byte BIT0 :1; /* First Address Breakpoint Register Bit 0 */ - byte BIT1 :1; /* First Address Breakpoint Register Bit 1 */ - byte BIT2 :1; /* First Address Breakpoint Register Bit 2 */ - byte BIT3 :1; /* First Address Breakpoint Register Bit 3 */ - byte BIT4 :1; /* First Address Breakpoint Register Bit 4 */ - byte BIT5 :1; /* First Address Breakpoint Register Bit 5 */ - byte BIT6 :1; /* First Address Breakpoint Register Bit 6 */ - byte BIT7 :1; /* First Address Breakpoint Register Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; -} BKP0LSTR; -extern volatile BKP0LSTR _BKP0L @(REG_BASE + 0x0000002C); -#define BKP0L _BKP0L.Byte -#define BKP0L_BIT0 _BKP0L.Bits.BIT0 -#define BKP0L_BIT1 _BKP0L.Bits.BIT1 -#define BKP0L_BIT2 _BKP0L.Bits.BIT2 -#define BKP0L_BIT3 _BKP0L.Bits.BIT3 -#define BKP0L_BIT4 _BKP0L.Bits.BIT4 -#define BKP0L_BIT5 _BKP0L.Bits.BIT5 -#define BKP0L_BIT6 _BKP0L.Bits.BIT6 -#define BKP0L_BIT7 _BKP0L.Bits.BIT7 -#define BKP0L_BIT _BKP0L.MergedBits.grpBIT - - -/*** BKP1X - Second Address Memory Expansion Breakpoint Register; 0x0000002D ***/ -typedef union { - byte Byte; - struct { - byte BK1V0 :1; /* Second Address Breakpoint Expansion Address Value Bit 0 */ - byte BK1V1 :1; /* Second Address Breakpoint Expansion Address Value Bit 1 */ - byte BK1V2 :1; /* Second Address Breakpoint Expansion Address Value Bit 2 */ - byte BK1V3 :1; /* Second Address Breakpoint Expansion Address Value Bit 3 */ - byte BK1V4 :1; /* Second Address Breakpoint Expansion Address Value Bit 4 */ - byte BK1V5 :1; /* Second Address Breakpoint Expansion Address Value Bit 5 */ - byte :1; - byte :1; - } Bits; - struct { - byte grpBK1V :6; - byte :1; - byte :1; - } MergedBits; -} BKP1XSTR; -extern volatile BKP1XSTR _BKP1X @(REG_BASE + 0x0000002D); -#define BKP1X _BKP1X.Byte -#define BKP1X_BK1V0 _BKP1X.Bits.BK1V0 -#define BKP1X_BK1V1 _BKP1X.Bits.BK1V1 -#define BKP1X_BK1V2 _BKP1X.Bits.BK1V2 -#define BKP1X_BK1V3 _BKP1X.Bits.BK1V3 -#define BKP1X_BK1V4 _BKP1X.Bits.BK1V4 -#define BKP1X_BK1V5 _BKP1X.Bits.BK1V5 -#define BKP1X_BK1V _BKP1X.MergedBits.grpBK1V - - -/*** BKP1H - Data (Second Address) High Byte Breakpoint Register; 0x0000002E ***/ -typedef union { - byte Byte; - struct { - byte BIT8 :1; /* Data (Second Address) Breakpoint Register Bit 8 */ - byte BIT9 :1; /* Data (Second Address) Breakpoint Register Bit 9 */ - byte BIT10 :1; /* Data (Second Address) Breakpoint Register Bit 10 */ - byte BIT11 :1; /* Data (Second Address) Breakpoint Register Bit 11 */ - byte BIT12 :1; /* Data (Second Address) Breakpoint Register Bit 12 */ - byte BIT13 :1; /* Data (Second Address) Breakpoint Register Bit 13 */ - byte BIT14 :1; /* Data (Second Address) Breakpoint Register Bit 14 */ - byte BIT15 :1; /* Data (Second Address) Breakpoint Register Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; -} BKP1HSTR; -extern volatile BKP1HSTR _BKP1H @(REG_BASE + 0x0000002E); -#define BKP1H _BKP1H.Byte -#define BKP1H_BIT8 _BKP1H.Bits.BIT8 -#define BKP1H_BIT9 _BKP1H.Bits.BIT9 -#define BKP1H_BIT10 _BKP1H.Bits.BIT10 -#define BKP1H_BIT11 _BKP1H.Bits.BIT11 -#define BKP1H_BIT12 _BKP1H.Bits.BIT12 -#define BKP1H_BIT13 _BKP1H.Bits.BIT13 -#define BKP1H_BIT14 _BKP1H.Bits.BIT14 -#define BKP1H_BIT15 _BKP1H.Bits.BIT15 -#define BKP1H_BIT_8 _BKP1H.MergedBits.grpBIT_8 -#define BKP1H_BIT BKP1H_BIT_8 - - -/*** BKP1L - Data (Second Address) Low Byte Breakpoint Register; 0x0000002F ***/ -typedef union { - byte Byte; - struct { - byte BIT0 :1; /* Data (Second Address) Breakpoint Register Bit 0 */ - byte BIT1 :1; /* Data (Second Address) Breakpoint Register Bit 1 */ - byte BIT2 :1; /* Data (Second Address) Breakpoint Register Bit 2 */ - byte BIT3 :1; /* Data (Second Address) Breakpoint Register Bit 3 */ - byte BIT4 :1; /* Data (Second Address) Breakpoint Register Bit 4 */ - byte BIT5 :1; /* Data (Second Address) Breakpoint Register Bit 5 */ - byte BIT6 :1; /* Data (Second Address) Breakpoint Register Bit 6 */ - byte BIT7 :1; /* Data (Second Address) Breakpoint Register Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; -} BKP1LSTR; -extern volatile BKP1LSTR _BKP1L @(REG_BASE + 0x0000002F); -#define BKP1L _BKP1L.Byte -#define BKP1L_BIT0 _BKP1L.Bits.BIT0 -#define BKP1L_BIT1 _BKP1L.Bits.BIT1 -#define BKP1L_BIT2 _BKP1L.Bits.BIT2 -#define BKP1L_BIT3 _BKP1L.Bits.BIT3 -#define BKP1L_BIT4 _BKP1L.Bits.BIT4 -#define BKP1L_BIT5 _BKP1L.Bits.BIT5 -#define BKP1L_BIT6 _BKP1L.Bits.BIT6 -#define BKP1L_BIT7 _BKP1L.Bits.BIT7 -#define BKP1L_BIT _BKP1L.MergedBits.grpBIT - - -/*** PPAGE - Page Index Register; 0x00000030 ***/ -typedef union { - byte Byte; - struct { - byte PIX0 :1; /* Page Index Register Bit 0 */ - byte PIX1 :1; /* Page Index Register Bit 1 */ - byte PIX2 :1; /* Page Index Register Bit 2 */ - byte PIX3 :1; /* Page Index Register Bit 3 */ - byte PIX4 :1; /* Page Index Register Bit 4 */ - byte PIX5 :1; /* Page Index Register Bit 5 */ - byte :1; - byte :1; - } Bits; - struct { - byte grpPIX :6; - byte :1; - byte :1; - } MergedBits; -} PPAGESTR; -extern volatile PPAGESTR _PPAGE @(REG_BASE + 0x00000030); -#define PPAGE _PPAGE.Byte -#define PPAGE_PIX0 _PPAGE.Bits.PIX0 -#define PPAGE_PIX1 _PPAGE.Bits.PIX1 -#define PPAGE_PIX2 _PPAGE.Bits.PIX2 -#define PPAGE_PIX3 _PPAGE.Bits.PIX3 -#define PPAGE_PIX4 _PPAGE.Bits.PIX4 -#define PPAGE_PIX5 _PPAGE.Bits.PIX5 -#define PPAGE_PIX _PPAGE.MergedBits.grpPIX - - -/*** PORTK - Port K Data Register; 0x00000032 ***/ -typedef union { - byte Byte; - struct { - byte BIT0 :1; /* Port K Bit 0 */ - byte BIT1 :1; /* Port K Bit 1 */ - byte BIT2 :1; /* Port K Bit 2 */ - byte BIT3 :1; /* Port K Bit 3 */ - byte BIT4 :1; /* Port K Bit 4 */ - byte BIT5 :1; /* Port K Bit 5 */ - byte :1; - byte BIT7 :1; /* Port K Bit 7 */ - } Bits; - struct { - byte grpBIT :6; - byte :1; - byte grpBIT_7 :1; - } MergedBits; -} PORTKSTR; -extern volatile PORTKSTR _PORTK @(REG_BASE + 0x00000032); -#define PORTK _PORTK.Byte -#define PORTK_BIT0 _PORTK.Bits.BIT0 -#define PORTK_BIT1 _PORTK.Bits.BIT1 -#define PORTK_BIT2 _PORTK.Bits.BIT2 -#define PORTK_BIT3 _PORTK.Bits.BIT3 -#define PORTK_BIT4 _PORTK.Bits.BIT4 -#define PORTK_BIT5 _PORTK.Bits.BIT5 -#define PORTK_BIT7 _PORTK.Bits.BIT7 -#define PORTK_BIT _PORTK.MergedBits.grpBIT - - -/*** DDRK - Port K Data Direction Register; 0x00000033 ***/ -typedef union { - byte Byte; - struct { - byte DDK0 :1; /* Port K Data Direction Bit 0 */ - byte DDK1 :1; /* Port K Data Direction Bit 1 */ - byte DDK2 :1; /* Port K Data Direction Bit 2 */ - byte DDK3 :1; /* Port K Data Direction Bit 3 */ - byte DDK4 :1; /* Port K Data Direction Bit 4 */ - byte DDK5 :1; /* Port K Data Direction Bit 5 */ - byte :1; - byte DDK7 :1; /* Port K Data Direction Bit 7 */ - } Bits; - struct { - byte grpDDK :6; - byte :1; - byte grpDDK_7 :1; - } MergedBits; -} DDRKSTR; -extern volatile DDRKSTR _DDRK @(REG_BASE + 0x00000033); -#define DDRK _DDRK.Byte -#define DDRK_DDK0 _DDRK.Bits.DDK0 -#define DDRK_DDK1 _DDRK.Bits.DDK1 -#define DDRK_DDK2 _DDRK.Bits.DDK2 -#define DDRK_DDK3 _DDRK.Bits.DDK3 -#define DDRK_DDK4 _DDRK.Bits.DDK4 -#define DDRK_DDK5 _DDRK.Bits.DDK5 -#define DDRK_DDK7 _DDRK.Bits.DDK7 -#define DDRK_DDK _DDRK.MergedBits.grpDDK - - -/*** SYNR - CRG Synthesizer Register; 0x00000034 ***/ -typedef union { - byte Byte; - struct { - byte SYN0 :1; /* CRG Synthesizer Bit 0 */ - byte SYN1 :1; /* CRG Synthesizer Bit 1 */ - byte SYN2 :1; /* CRG Synthesizer Bit 2 */ - byte SYN3 :1; /* CRG Synthesizer Bit 3 */ - byte SYN4 :1; /* CRG Synthesizer Bit 4 */ - byte SYN5 :1; /* CRG Synthesizer Bit 5 */ - byte :1; - byte :1; - } Bits; - struct { - byte grpSYN :6; - byte :1; - byte :1; - } MergedBits; -} SYNRSTR; -extern volatile SYNRSTR _SYNR @(REG_BASE + 0x00000034); -#define SYNR _SYNR.Byte -#define SYNR_SYN0 _SYNR.Bits.SYN0 -#define SYNR_SYN1 _SYNR.Bits.SYN1 -#define SYNR_SYN2 _SYNR.Bits.SYN2 -#define SYNR_SYN3 _SYNR.Bits.SYN3 -#define SYNR_SYN4 _SYNR.Bits.SYN4 -#define SYNR_SYN5 _SYNR.Bits.SYN5 -#define SYNR_SYN _SYNR.MergedBits.grpSYN - - -/*** REFDV - CRG Reference Divider Register; 0x00000035 ***/ -typedef union { - byte Byte; - struct { - byte REFDV0 :1; /* CRG Reference Divider Bit 0 */ - byte REFDV1 :1; /* CRG Reference Divider Bit 1 */ - byte REFDV2 :1; /* CRG Reference Divider Bit 2 */ - byte REFDV3 :1; /* CRG Reference Divider Bit 3 */ - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpREFDV :4; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} REFDVSTR; -extern volatile REFDVSTR _REFDV @(REG_BASE + 0x00000035); -#define REFDV _REFDV.Byte -#define REFDV_REFDV0 _REFDV.Bits.REFDV0 -#define REFDV_REFDV1 _REFDV.Bits.REFDV1 -#define REFDV_REFDV2 _REFDV.Bits.REFDV2 -#define REFDV_REFDV3 _REFDV.Bits.REFDV3 -#define REFDV_REFDV _REFDV.MergedBits.grpREFDV - - -/*** CTFLG - CRG Test Flags Register; 0x00000036 ***/ -typedef union { - byte Byte; - struct { - byte TOUT0 :1; /* CRG Test Flags Bit 0 */ - byte TOUT1 :1; /* CRG Test Flags Bit 1 */ - byte TOUT2 :1; /* CRG Test Flags Bit 2 */ - byte TOUT3 :1; /* CRG Test Flags Bit 3 */ - byte TOUT4 :1; /* CRG Test Flags Bit 4 */ - byte TOUT5 :1; /* CRG Test Flags Bit 5 */ - byte TOUT6 :1; /* CRG Test Flags Bit 6 */ - byte TOUT7 :1; /* CRG Test Flags Bit 7 */ - } Bits; - struct { - byte grpTOUT :8; - } MergedBits; -} CTFLGSTR; -extern volatile CTFLGSTR _CTFLG @(REG_BASE + 0x00000036); -#define CTFLG _CTFLG.Byte -#define CTFLG_TOUT0 _CTFLG.Bits.TOUT0 -#define CTFLG_TOUT1 _CTFLG.Bits.TOUT1 -#define CTFLG_TOUT2 _CTFLG.Bits.TOUT2 -#define CTFLG_TOUT3 _CTFLG.Bits.TOUT3 -#define CTFLG_TOUT4 _CTFLG.Bits.TOUT4 -#define CTFLG_TOUT5 _CTFLG.Bits.TOUT5 -#define CTFLG_TOUT6 _CTFLG.Bits.TOUT6 -#define CTFLG_TOUT7 _CTFLG.Bits.TOUT7 -#define CTFLG_TOUT _CTFLG.MergedBits.grpTOUT - - -/*** CRGFLG - CRG Flags Register; 0x00000037 ***/ -typedef union { - byte Byte; - struct { - byte SCM :1; /* Self-clock mode Status */ - byte SCMIF :1; /* Self-clock mode Interrupt Flag */ - byte TRACK :1; /* Track Status */ - byte LOCK :1; /* Lock Status */ - byte LOCKIF :1; /* PLL Lock Interrupt Flag */ - byte :1; - byte PORF :1; /* Power on Reset Flag */ - byte RTIF :1; /* Real Time Interrupt Flag */ - } Bits; -} CRGFLGSTR; -extern volatile CRGFLGSTR _CRGFLG @(REG_BASE + 0x00000037); -#define CRGFLG _CRGFLG.Byte -#define CRGFLG_SCM _CRGFLG.Bits.SCM -#define CRGFLG_SCMIF _CRGFLG.Bits.SCMIF -#define CRGFLG_TRACK _CRGFLG.Bits.TRACK -#define CRGFLG_LOCK _CRGFLG.Bits.LOCK -#define CRGFLG_LOCKIF _CRGFLG.Bits.LOCKIF -#define CRGFLG_PORF _CRGFLG.Bits.PORF -#define CRGFLG_RTIF _CRGFLG.Bits.RTIF - - -/*** CRGINT - CRG Interrupt Enable Register; 0x00000038 ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte SCMIE :1; /* Self-clock mode Interrupt Enable */ - byte :1; - byte :1; - byte LOCKIE :1; /* Lock Interrupt Enable */ - byte :1; - byte :1; - byte RTIE :1; /* Real Time Interrupt Enable */ - } Bits; -} CRGINTSTR; -extern volatile CRGINTSTR _CRGINT @(REG_BASE + 0x00000038); -#define CRGINT _CRGINT.Byte -#define CRGINT_SCMIE _CRGINT.Bits.SCMIE -#define CRGINT_LOCKIE _CRGINT.Bits.LOCKIE -#define CRGINT_RTIE _CRGINT.Bits.RTIE - - -/*** CLKSEL - CRG Clock Select Register; 0x00000039 ***/ -typedef union { - byte Byte; - struct { - byte COPWAI :1; /* COP stops in WAIT mode */ - byte RTIWAI :1; /* RTI stops in WAIT mode */ - byte CWAI :1; /* CLK24 and CLK23 stop in WAIT mode */ - byte PLLWAI :1; /* PLL stops in WAIT mode */ - byte ROAWAI :1; /* Reduced Oscillator Amplitude in WAIT mode */ - byte SYSWAI :1; /* System clocks stop in WAIT mode */ - byte PSTP :1; /* Pseudo Stop */ - byte PLLSEL :1; /* PLL selected for system clock */ - } Bits; -} CLKSELSTR; -extern volatile CLKSELSTR _CLKSEL @(REG_BASE + 0x00000039); -#define CLKSEL _CLKSEL.Byte -#define CLKSEL_COPWAI _CLKSEL.Bits.COPWAI -#define CLKSEL_RTIWAI _CLKSEL.Bits.RTIWAI -#define CLKSEL_CWAI _CLKSEL.Bits.CWAI -#define CLKSEL_PLLWAI _CLKSEL.Bits.PLLWAI -#define CLKSEL_ROAWAI _CLKSEL.Bits.ROAWAI -#define CLKSEL_SYSWAI _CLKSEL.Bits.SYSWAI -#define CLKSEL_PSTP _CLKSEL.Bits.PSTP -#define CLKSEL_PLLSEL _CLKSEL.Bits.PLLSEL - - -/*** PLLCTL - CRG PLL Control Register; 0x0000003A ***/ -typedef union { - byte Byte; - struct { - byte SCME :1; /* Self-clock mode enable */ - byte :1; - byte :1; - byte :1; - byte ACQ :1; /* Acquisition */ - byte AUTO :1; /* Automatic Bandwidth Control */ - byte PLLON :1; /* Phase Lock Loop On */ - byte CME :1; /* Crystal Monitor Enable */ - } Bits; -} PLLCTLSTR; -extern volatile PLLCTLSTR _PLLCTL @(REG_BASE + 0x0000003A); -#define PLLCTL _PLLCTL.Byte -#define PLLCTL_SCME _PLLCTL.Bits.SCME -#define PLLCTL_ACQ _PLLCTL.Bits.ACQ -#define PLLCTL_AUTO _PLLCTL.Bits.AUTO -#define PLLCTL_PLLON _PLLCTL.Bits.PLLON -#define PLLCTL_CME _PLLCTL.Bits.CME - - -/*** RTICTL - CRG RTI Control Register; 0x0000003B ***/ -typedef union { - byte Byte; - struct { - byte RTR0 :1; /* Real Time Interrupt Modulus Counter Select */ - byte RTR1 :1; /* Real Time Interrupt Modulus Counter Select */ - byte RTR2 :1; /* Real Time Interrupt Modulus Counter Select */ - byte RTR3 :1; /* Real Time Interrupt Modulus Counter Select */ - byte RTR4 :1; /* Real Time Interrupt Prescale Rate Select */ - byte RTR5 :1; /* Real Time Interrupt Prescale Rate Select */ - byte RTR6 :1; /* Real Time Interrupt Prescale Rate Select */ - byte :1; - } Bits; - struct { - byte grpRTR :7; - byte :1; - } MergedBits; -} RTICTLSTR; -extern volatile RTICTLSTR _RTICTL @(REG_BASE + 0x0000003B); -#define RTICTL _RTICTL.Byte -#define RTICTL_RTR0 _RTICTL.Bits.RTR0 -#define RTICTL_RTR1 _RTICTL.Bits.RTR1 -#define RTICTL_RTR2 _RTICTL.Bits.RTR2 -#define RTICTL_RTR3 _RTICTL.Bits.RTR3 -#define RTICTL_RTR4 _RTICTL.Bits.RTR4 -#define RTICTL_RTR5 _RTICTL.Bits.RTR5 -#define RTICTL_RTR6 _RTICTL.Bits.RTR6 -#define RTICTL_RTR _RTICTL.MergedBits.grpRTR - - -/*** COPCTL - CRG COP Control Register; 0x0000003C ***/ -typedef union { - byte Byte; - struct { - byte CR0 :1; /* COP Watchdog Timer Rate select Bit 0 */ - byte CR1 :1; /* COP Watchdog Timer Rate select Bit 1 */ - byte CR2 :1; /* COP Watchdog Timer Rate select Bit 2 */ - byte :1; - byte :1; - byte :1; - byte RSBCK :1; /* COP and RTI stop in Active BDM mode Bit */ - byte WCOP :1; /* Window COP mode */ - } Bits; - struct { - byte grpCR :3; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} COPCTLSTR; -extern volatile COPCTLSTR _COPCTL @(REG_BASE + 0x0000003C); -#define COPCTL _COPCTL.Byte -#define COPCTL_CR0 _COPCTL.Bits.CR0 -#define COPCTL_CR1 _COPCTL.Bits.CR1 -#define COPCTL_CR2 _COPCTL.Bits.CR2 -#define COPCTL_RSBCK _COPCTL.Bits.RSBCK -#define COPCTL_WCOP _COPCTL.Bits.WCOP -#define COPCTL_CR _COPCTL.MergedBits.grpCR - - -/*** FORBYP - Crg force and bypass test register; 0x0000003D ***/ -typedef union { - byte Byte; - struct { - byte BIT0 :1; /* Bit 0 */ - byte BIT1 :1; /* Bit 1 */ - byte BIT2 :1; /* Bit 2 */ - byte BIT3 :1; /* Bit 3 */ - byte BIT4 :1; /* Bit 4 */ - byte BIT5 :1; /* Bit 5 */ - byte BIT6 :1; /* Bit 6 */ - byte BIT7 :1; /* Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; -} FORBYPSTR; -extern volatile FORBYPSTR _FORBYP @(REG_BASE + 0x0000003D); -#define FORBYP _FORBYP.Byte -#define FORBYP_BIT0 _FORBYP.Bits.BIT0 -#define FORBYP_BIT1 _FORBYP.Bits.BIT1 -#define FORBYP_BIT2 _FORBYP.Bits.BIT2 -#define FORBYP_BIT3 _FORBYP.Bits.BIT3 -#define FORBYP_BIT4 _FORBYP.Bits.BIT4 -#define FORBYP_BIT5 _FORBYP.Bits.BIT5 -#define FORBYP_BIT6 _FORBYP.Bits.BIT6 -#define FORBYP_BIT7 _FORBYP.Bits.BIT7 -#define FORBYP_BIT _FORBYP.MergedBits.grpBIT - - -/*** CTCTL - CRG Test Control Register; 0x0000003E ***/ -typedef union { - byte Byte; - struct { - byte TCTL0 :1; /* CRG Test Control Bit 0 */ - byte TCTL1 :1; /* CRG Test Control Bit 1 */ - byte TCTL2 :1; /* CRG Test Control Bit 2 */ - byte TCTL3 :1; /* CRG Test Control Bit 3 */ - byte TCTL4 :1; /* CRG Test Control Bit 4 */ - byte TCTL5 :1; /* CRG Test Control Bit 5 */ - byte TCTL6 :1; /* CRG Test Control Bit 6 */ - byte TCTL7 :1; /* CRG Test Control Bit 7 */ - } Bits; - struct { - byte grpTCTL :8; - } MergedBits; -} CTCTLSTR; -extern volatile CTCTLSTR _CTCTL @(REG_BASE + 0x0000003E); -#define CTCTL _CTCTL.Byte -#define CTCTL_TCTL0 _CTCTL.Bits.TCTL0 -#define CTCTL_TCTL1 _CTCTL.Bits.TCTL1 -#define CTCTL_TCTL2 _CTCTL.Bits.TCTL2 -#define CTCTL_TCTL3 _CTCTL.Bits.TCTL3 -#define CTCTL_TCTL4 _CTCTL.Bits.TCTL4 -#define CTCTL_TCTL5 _CTCTL.Bits.TCTL5 -#define CTCTL_TCTL6 _CTCTL.Bits.TCTL6 -#define CTCTL_TCTL7 _CTCTL.Bits.TCTL7 -#define CTCTL_TCTL _CTCTL.MergedBits.grpTCTL - - -/*** ARMCOP - CRG COP Timer Arm/Reset Register; 0x0000003F ***/ -typedef union { - byte Byte; - struct { - byte BIT0 :1; /* CRG COP Timer Arm/Reset Bit 0 */ - byte BIT1 :1; /* CRG COP Timer Arm/Reset Bit 1 */ - byte BIT2 :1; /* CRG COP Timer Arm/Reset Bit 2 */ - byte BIT3 :1; /* CRG COP Timer Arm/Reset Bit 3 */ - byte BIT4 :1; /* CRG COP Timer Arm/Reset Bit 4 */ - byte BIT5 :1; /* CRG COP Timer Arm/Reset Bit 5 */ - byte BIT6 :1; /* CRG COP Timer Arm/Reset Bit 6 */ - byte BIT7 :1; /* CRG COP Timer Arm/Reset Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; -} ARMCOPSTR; -extern volatile ARMCOPSTR _ARMCOP @(REG_BASE + 0x0000003F); -#define ARMCOP _ARMCOP.Byte -#define ARMCOP_BIT0 _ARMCOP.Bits.BIT0 -#define ARMCOP_BIT1 _ARMCOP.Bits.BIT1 -#define ARMCOP_BIT2 _ARMCOP.Bits.BIT2 -#define ARMCOP_BIT3 _ARMCOP.Bits.BIT3 -#define ARMCOP_BIT4 _ARMCOP.Bits.BIT4 -#define ARMCOP_BIT5 _ARMCOP.Bits.BIT5 -#define ARMCOP_BIT6 _ARMCOP.Bits.BIT6 -#define ARMCOP_BIT7 _ARMCOP.Bits.BIT7 -#define ARMCOP_BIT _ARMCOP.MergedBits.grpBIT - - -/*** TIOS - Timer Input Capture/Output Compare Select; 0x00000040 ***/ -typedef union { - byte Byte; - struct { - byte IOS0 :1; /* Input Capture or Output Compare Channel Configuration Bit 0 */ - byte IOS1 :1; /* Input Capture or Output Compare Channel Configuration Bit 1 */ - byte IOS2 :1; /* Input Capture or Output Compare Channel Configuration Bit 2 */ - byte IOS3 :1; /* Input Capture or Output Compare Channel Configuration Bit 3 */ - byte IOS4 :1; /* Input Capture or Output Compare Channel Configuration Bit 4 */ - byte IOS5 :1; /* Input Capture or Output Compare Channel Configuration Bit 5 */ - byte IOS6 :1; /* Input Capture or Output Compare Channel Configuration Bit 6 */ - byte IOS7 :1; /* Input Capture or Output Compare Channel Configuration Bit 7 */ - } Bits; - struct { - byte grpIOS :8; - } MergedBits; -} TIOSSTR; -extern volatile TIOSSTR _TIOS @(REG_BASE + 0x00000040); -#define TIOS _TIOS.Byte -#define TIOS_IOS0 _TIOS.Bits.IOS0 -#define TIOS_IOS1 _TIOS.Bits.IOS1 -#define TIOS_IOS2 _TIOS.Bits.IOS2 -#define TIOS_IOS3 _TIOS.Bits.IOS3 -#define TIOS_IOS4 _TIOS.Bits.IOS4 -#define TIOS_IOS5 _TIOS.Bits.IOS5 -#define TIOS_IOS6 _TIOS.Bits.IOS6 -#define TIOS_IOS7 _TIOS.Bits.IOS7 -#define TIOS_IOS _TIOS.MergedBits.grpIOS - - -/*** CFORC - Timer Compare Force Register; 0x00000041 ***/ -typedef union { - byte Byte; - struct { - byte FOC0 :1; /* Force Output Compare Action for Channel 0 */ - byte FOC1 :1; /* Force Output Compare Action for Channel 1 */ - byte FOC2 :1; /* Force Output Compare Action for Channel 2 */ - byte FOC3 :1; /* Force Output Compare Action for Channel 3 */ - byte FOC4 :1; /* Force Output Compare Action for Channel 4 */ - byte FOC5 :1; /* Force Output Compare Action for Channel 5 */ - byte FOC6 :1; /* Force Output Compare Action for Channel 6 */ - byte FOC7 :1; /* Force Output Compare Action for Channel 7 */ - } Bits; - struct { - byte grpFOC :8; - } MergedBits; -} CFORCSTR; -extern volatile CFORCSTR _CFORC @(REG_BASE + 0x00000041); -#define CFORC _CFORC.Byte -#define CFORC_FOC0 _CFORC.Bits.FOC0 -#define CFORC_FOC1 _CFORC.Bits.FOC1 -#define CFORC_FOC2 _CFORC.Bits.FOC2 -#define CFORC_FOC3 _CFORC.Bits.FOC3 -#define CFORC_FOC4 _CFORC.Bits.FOC4 -#define CFORC_FOC5 _CFORC.Bits.FOC5 -#define CFORC_FOC6 _CFORC.Bits.FOC6 -#define CFORC_FOC7 _CFORC.Bits.FOC7 -#define CFORC_FOC _CFORC.MergedBits.grpFOC - - -/*** OC7M - Output Compare 7 Mask Register; 0x00000042 ***/ -typedef union { - byte Byte; - struct { - byte OC7M0 :1; /* Output Compare 7 Mask Bit 0 */ - byte OC7M1 :1; /* Output Compare 7 Mask Bit 1 */ - byte OC7M2 :1; /* Output Compare 7 Mask Bit 2 */ - byte OC7M3 :1; /* Output Compare 7 Mask Bit 3 */ - byte OC7M4 :1; /* Output Compare 7 Mask Bit 4 */ - byte OC7M5 :1; /* Output Compare 7 Mask Bit 5 */ - byte OC7M6 :1; /* Output Compare 7 Mask Bit 6 */ - byte OC7M7 :1; /* Output Compare 7 Mask Bit 7 */ - } Bits; - struct { - byte grpOC7M :8; - } MergedBits; -} OC7MSTR; -extern volatile OC7MSTR _OC7M @(REG_BASE + 0x00000042); -#define OC7M _OC7M.Byte -#define OC7M_OC7M0 _OC7M.Bits.OC7M0 -#define OC7M_OC7M1 _OC7M.Bits.OC7M1 -#define OC7M_OC7M2 _OC7M.Bits.OC7M2 -#define OC7M_OC7M3 _OC7M.Bits.OC7M3 -#define OC7M_OC7M4 _OC7M.Bits.OC7M4 -#define OC7M_OC7M5 _OC7M.Bits.OC7M5 -#define OC7M_OC7M6 _OC7M.Bits.OC7M6 -#define OC7M_OC7M7 _OC7M.Bits.OC7M7 -#define OC7M_OC7M _OC7M.MergedBits.grpOC7M - - -/*** OC7D - Output Compare 7 Data Register; 0x00000043 ***/ -typedef union { - byte Byte; - struct { - byte grpOC7D :8; - } MergedBits; -} OC7DSTR; -extern volatile OC7DSTR _OC7D @(REG_BASE + 0x00000043); -#define OC7D _OC7D.Byte -#define OC7D_OC7D _OC7D.MergedBits.grpOC7D - - -/*** TSCR1 - Timer System Control Register1; 0x00000046 ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte TFFCA :1; /* Timer Fast Flag Clear All */ - byte TSFRZ :1; /* Timer and Modulus Counter Stop While in Freeze Mode */ - byte TSWAI :1; /* Timer Module Stops While in Wait */ - byte TEN :1; /* Timer Enable */ - } Bits; -} TSCR1STR; -extern volatile TSCR1STR _TSCR1 @(REG_BASE + 0x00000046); -#define TSCR1 _TSCR1.Byte -#define TSCR1_TFFCA _TSCR1.Bits.TFFCA -#define TSCR1_TSFRZ _TSCR1.Bits.TSFRZ -#define TSCR1_TSWAI _TSCR1.Bits.TSWAI -#define TSCR1_TEN _TSCR1.Bits.TEN - - -/*** TTOV - Timer Toggle On Overflow Register; 0x00000047 ***/ -typedef union { - byte Byte; - struct { - byte TOV0 :1; /* Toggle On Overflow Bit 0 */ - byte TOV1 :1; /* Toggle On Overflow Bit 1 */ - byte TOV2 :1; /* Toggle On Overflow Bit 2 */ - byte TOV3 :1; /* Toggle On Overflow Bit 3 */ - byte TOV4 :1; /* Toggle On Overflow Bit 4 */ - byte TOV5 :1; /* Toggle On Overflow Bit 5 */ - byte TOV6 :1; /* Toggle On Overflow Bit 6 */ - byte TOV7 :1; /* Toggle On Overflow Bit 7 */ - } Bits; - struct { - byte grpTOV :8; - } MergedBits; -} TTOVSTR; -extern volatile TTOVSTR _TTOV @(REG_BASE + 0x00000047); -#define TTOV _TTOV.Byte -#define TTOV_TOV0 _TTOV.Bits.TOV0 -#define TTOV_TOV1 _TTOV.Bits.TOV1 -#define TTOV_TOV2 _TTOV.Bits.TOV2 -#define TTOV_TOV3 _TTOV.Bits.TOV3 -#define TTOV_TOV4 _TTOV.Bits.TOV4 -#define TTOV_TOV5 _TTOV.Bits.TOV5 -#define TTOV_TOV6 _TTOV.Bits.TOV6 -#define TTOV_TOV7 _TTOV.Bits.TOV7 -#define TTOV_TOV _TTOV.MergedBits.grpTOV - - -/*** TCTL1 - Timer Control Registers 1; 0x00000048 ***/ -typedef union { - byte Byte; - struct { - byte OL4 :1; /* Output Level Bit 4 */ - byte OM4 :1; /* Output Mode Bit 4 */ - byte OL5 :1; /* Output Level Bit 5 */ - byte OM5 :1; /* Output Mode Bit 5 */ - byte OL6 :1; /* Output Level Bit 6 */ - byte OM6 :1; /* Output Mode Bit 6 */ - byte OL7 :1; /* Output Level Bit 7 */ - byte OM7 :1; /* Output Mode Bit 7 */ - } Bits; -} TCTL1STR; -extern volatile TCTL1STR _TCTL1 @(REG_BASE + 0x00000048); -#define TCTL1 _TCTL1.Byte -#define TCTL1_OL4 _TCTL1.Bits.OL4 -#define TCTL1_OM4 _TCTL1.Bits.OM4 -#define TCTL1_OL5 _TCTL1.Bits.OL5 -#define TCTL1_OM5 _TCTL1.Bits.OM5 -#define TCTL1_OL6 _TCTL1.Bits.OL6 -#define TCTL1_OM6 _TCTL1.Bits.OM6 -#define TCTL1_OL7 _TCTL1.Bits.OL7 -#define TCTL1_OM7 _TCTL1.Bits.OM7 - - -/*** TCTL2 - Timer Control Registers 2; 0x00000049 ***/ -typedef union { - byte Byte; - struct { - byte OL0 :1; /* Output Level Bit 0 */ - byte OM0 :1; /* Output Mode Bit 0 */ - byte OL1 :1; /* Output Level Bit 1 */ - byte OM1 :1; /* Output Mode Bit 1 */ - byte OL2 :1; /* Output Level Bit 2 */ - byte OM2 :1; /* Output Mode Bit 2 */ - byte OL3 :1; /* Output Level Bit 3 */ - byte OM3 :1; /* Output Mode Bit 3 */ - } Bits; -} TCTL2STR; -extern volatile TCTL2STR _TCTL2 @(REG_BASE + 0x00000049); -#define TCTL2 _TCTL2.Byte -#define TCTL2_OL0 _TCTL2.Bits.OL0 -#define TCTL2_OM0 _TCTL2.Bits.OM0 -#define TCTL2_OL1 _TCTL2.Bits.OL1 -#define TCTL2_OM1 _TCTL2.Bits.OM1 -#define TCTL2_OL2 _TCTL2.Bits.OL2 -#define TCTL2_OM2 _TCTL2.Bits.OM2 -#define TCTL2_OL3 _TCTL2.Bits.OL3 -#define TCTL2_OM3 _TCTL2.Bits.OM3 - - -/*** TCTL3 - Timer Control Register 3; 0x0000004A ***/ -typedef union { - byte Byte; - struct { - byte EDG4A :1; /* Input Capture Edge Control 4A */ - byte EDG4B :1; /* Input Capture Edge Control 4B */ - byte EDG5A :1; /* Input Capture Edge Control 5A */ - byte EDG5B :1; /* Input Capture Edge Control 5B */ - byte EDG6A :1; /* Input Capture Edge Control 6A */ - byte EDG6B :1; /* Input Capture Edge Control 6B */ - byte EDG7A :1; /* Input Capture Edge Control 7A */ - byte EDG7B :1; /* Input Capture Edge Control 7B */ - } Bits; -} TCTL3STR; -extern volatile TCTL3STR _TCTL3 @(REG_BASE + 0x0000004A); -#define TCTL3 _TCTL3.Byte -#define TCTL3_EDG4A _TCTL3.Bits.EDG4A -#define TCTL3_EDG4B _TCTL3.Bits.EDG4B -#define TCTL3_EDG5A _TCTL3.Bits.EDG5A -#define TCTL3_EDG5B _TCTL3.Bits.EDG5B -#define TCTL3_EDG6A _TCTL3.Bits.EDG6A -#define TCTL3_EDG6B _TCTL3.Bits.EDG6B -#define TCTL3_EDG7A _TCTL3.Bits.EDG7A -#define TCTL3_EDG7B _TCTL3.Bits.EDG7B - - -/*** TCTL4 - Timer Control Register 4; 0x0000004B ***/ -typedef union { - byte Byte; - struct { - byte EDG0A :1; /* Input Capture Edge Control 0A */ - byte EDG0B :1; /* Input Capture Edge Control 0B */ - byte EDG1A :1; /* Input Capture Edge Control 1A */ - byte EDG1B :1; /* Input Capture Edge Control 1B */ - byte EDG2A :1; /* Input Capture Edge Control 2A */ - byte EDG2B :1; /* Input Capture Edge Control 2B */ - byte EDG3A :1; /* Input Capture Edge Control 3A */ - byte EDG3B :1; /* Input Capture Edge Control 3B */ - } Bits; -} TCTL4STR; -extern volatile TCTL4STR _TCTL4 @(REG_BASE + 0x0000004B); -#define TCTL4 _TCTL4.Byte -#define TCTL4_EDG0A _TCTL4.Bits.EDG0A -#define TCTL4_EDG0B _TCTL4.Bits.EDG0B -#define TCTL4_EDG1A _TCTL4.Bits.EDG1A -#define TCTL4_EDG1B _TCTL4.Bits.EDG1B -#define TCTL4_EDG2A _TCTL4.Bits.EDG2A -#define TCTL4_EDG2B _TCTL4.Bits.EDG2B -#define TCTL4_EDG3A _TCTL4.Bits.EDG3A -#define TCTL4_EDG3B _TCTL4.Bits.EDG3B - - -/*** TIE - Timer Interrupt Enable Register; 0x0000004C ***/ -typedef union { - byte Byte; - struct { - byte C0I :1; /* Input Capture/Output Compare Interrupt Enable Bit 0 */ - byte C1I :1; /* Input Capture/Output Compare Interrupt Enable Bit 1 */ - byte C2I :1; /* Input Capture/Output Compare Interrupt Enable Bit 2 */ - byte C3I :1; /* Input Capture/Output Compare Interrupt Enable Bit 3 */ - byte C4I :1; /* Input Capture/Output Compare Interrupt Enable Bit 4 */ - byte C5I :1; /* Input Capture/Output Compare Interrupt Enable Bit 5 */ - byte C6I :1; /* Input Capture/Output Compare Interrupt Enable Bit 6 */ - byte C7I :1; /* Input Capture/Output Compare Interrupt Enable Bit 7 */ - } Bits; -} TIESTR; -extern volatile TIESTR _TIE @(REG_BASE + 0x0000004C); -#define TIE _TIE.Byte -#define TIE_C0I _TIE.Bits.C0I -#define TIE_C1I _TIE.Bits.C1I -#define TIE_C2I _TIE.Bits.C2I -#define TIE_C3I _TIE.Bits.C3I -#define TIE_C4I _TIE.Bits.C4I -#define TIE_C5I _TIE.Bits.C5I -#define TIE_C6I _TIE.Bits.C6I -#define TIE_C7I _TIE.Bits.C7I - - -/*** TSCR2 - Timer System Control Register 2; 0x0000004D ***/ -typedef union { - byte Byte; - struct { - byte PR0 :1; /* Timer Prescaler Select Bit 0 */ - byte PR1 :1; /* Timer Prescaler Select Bit 1 */ - byte PR2 :1; /* Timer Prescaler Select Bit 2 */ - byte TCRE :1; /* Timer Counter Reset Enable */ - byte :1; - byte :1; - byte :1; - byte TOI :1; /* Timer Overflow Interrupt Enable */ - } Bits; - struct { - byte grpPR :3; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} TSCR2STR; -extern volatile TSCR2STR _TSCR2 @(REG_BASE + 0x0000004D); -#define TSCR2 _TSCR2.Byte -#define TSCR2_PR0 _TSCR2.Bits.PR0 -#define TSCR2_PR1 _TSCR2.Bits.PR1 -#define TSCR2_PR2 _TSCR2.Bits.PR2 -#define TSCR2_TCRE _TSCR2.Bits.TCRE -#define TSCR2_TOI _TSCR2.Bits.TOI -#define TSCR2_PR _TSCR2.MergedBits.grpPR - - -/*** TFLG1 - Main Timer Interrupt Flag 1; 0x0000004E ***/ -typedef union { - byte Byte; - struct { - byte C0F :1; /* Input Capture/Output Compare Channel Flag 0 */ - byte C1F :1; /* Input Capture/Output Compare Channel Flag 1 */ - byte C2F :1; /* Input Capture/Output Compare Channel Flag 2 */ - byte C3F :1; /* Input Capture/Output Compare Channel Flag 3 */ - byte C4F :1; /* Input Capture/Output Compare Channel Flag 4 */ - byte C5F :1; /* Input Capture/Output Compare Channel Flag 5 */ - byte C6F :1; /* Input Capture/Output Compare Channel Flag 6 */ - byte C7F :1; /* Input Capture/Output Compare Channel Flag 7 */ - } Bits; -} TFLG1STR; -extern volatile TFLG1STR _TFLG1 @(REG_BASE + 0x0000004E); -#define TFLG1 _TFLG1.Byte -#define TFLG1_C0F _TFLG1.Bits.C0F -#define TFLG1_C1F _TFLG1.Bits.C1F -#define TFLG1_C2F _TFLG1.Bits.C2F -#define TFLG1_C3F _TFLG1.Bits.C3F -#define TFLG1_C4F _TFLG1.Bits.C4F -#define TFLG1_C5F _TFLG1.Bits.C5F -#define TFLG1_C6F _TFLG1.Bits.C6F -#define TFLG1_C7F _TFLG1.Bits.C7F - - -/*** TFLG2 - Main Timer Interrupt Flag 2; 0x0000004F ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte TOF :1; /* Timer Overflow Flag */ - } Bits; -} TFLG2STR; -extern volatile TFLG2STR _TFLG2 @(REG_BASE + 0x0000004F); -#define TFLG2 _TFLG2.Byte -#define TFLG2_TOF _TFLG2.Bits.TOF - - -/*** PACTL - 16-Bit Pulse Accumulator A Control Register; 0x00000060 ***/ -typedef union { - byte Byte; - struct { - byte PAI :1; /* Pulse Accumulator Input Interrupt enable */ - byte PAOVI :1; /* Pulse Accumulator A Overflow Interrupt enable */ - byte CLK0 :1; /* Clock Select Bit 0 */ - byte CLK1 :1; /* Clock Select Bit 1 */ - byte PEDGE :1; /* Pulse Accumulator Edge Control */ - byte PAMOD :1; /* Pulse Accumulator Mode */ - byte PAEN :1; /* Pulse Accumulator A System Enable */ - byte :1; - } Bits; - struct { - byte :1; - byte :1; - byte grpCLK :2; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} PACTLSTR; -extern volatile PACTLSTR _PACTL @(REG_BASE + 0x00000060); -#define PACTL _PACTL.Byte -#define PACTL_PAI _PACTL.Bits.PAI -#define PACTL_PAOVI _PACTL.Bits.PAOVI -#define PACTL_CLK0 _PACTL.Bits.CLK0 -#define PACTL_CLK1 _PACTL.Bits.CLK1 -#define PACTL_PEDGE _PACTL.Bits.PEDGE -#define PACTL_PAMOD _PACTL.Bits.PAMOD -#define PACTL_PAEN _PACTL.Bits.PAEN -#define PACTL_CLK _PACTL.MergedBits.grpCLK - - -/*** PAFLG - Pulse Accumulator A Flag Register; 0x00000061 ***/ -typedef union { - byte Byte; - struct { - byte PAIF :1; /* Pulse Accumulator Input edge Flag */ - byte PAOVF :1; /* Pulse Accumulator A Overflow Flag */ - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; -} PAFLGSTR; -extern volatile PAFLGSTR _PAFLG @(REG_BASE + 0x00000061); -#define PAFLG _PAFLG.Byte -#define PAFLG_PAIF _PAFLG.Bits.PAIF -#define PAFLG_PAOVF _PAFLG.Bits.PAOVF - - -/*** MCCTL - Modulus Down Counter underflow; 0x00000066 ***/ -typedef union { - byte Byte; - struct { - byte MCPR0 :1; /* Modulus Counter Prescaler select 0 */ - byte MCPR1 :1; /* Modulus Counter Prescaler select 1 */ - byte MCEN :1; /* Modulus Down-Counter Enable */ - byte FLMC :1; /* Force Load Register into the Modulus Counter Count Register */ - byte ICLAT :1; /* Input Capture Force Latch Action */ - byte RDMCL :1; /* Read Modulus Down-Counter Load */ - byte MODMC :1; /* Modulus Mode Enable */ - byte MCZI :1; /* Modulus Counter Underflow Interrupt Enable */ - } Bits; - struct { - byte grpMCPR :2; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} MCCTLSTR; -extern volatile MCCTLSTR _MCCTL @(REG_BASE + 0x00000066); -#define MCCTL _MCCTL.Byte -#define MCCTL_MCPR0 _MCCTL.Bits.MCPR0 -#define MCCTL_MCPR1 _MCCTL.Bits.MCPR1 -#define MCCTL_MCEN _MCCTL.Bits.MCEN -#define MCCTL_FLMC _MCCTL.Bits.FLMC -#define MCCTL_ICLAT _MCCTL.Bits.ICLAT -#define MCCTL_RDMCL _MCCTL.Bits.RDMCL -#define MCCTL_MODMC _MCCTL.Bits.MODMC -#define MCCTL_MCZI _MCCTL.Bits.MCZI -#define MCCTL_MCPR _MCCTL.MergedBits.grpMCPR - - -/*** MCFLG - 16-Bit Modulus Down Counter Flag Register; 0x00000067 ***/ -typedef union { - byte Byte; - struct { - byte POLF0 :1; /* First Input Capture Polarity Status 0 */ - byte POLF1 :1; /* First Input Capture Polarity Status 1 */ - byte POLF2 :1; /* First Input Capture Polarity Status 2 */ - byte POLF3 :1; /* First Input Capture Polarity Status 3 */ - byte :1; - byte :1; - byte :1; - byte MCZF :1; /* Modulus Counter Underflow Flag */ - } Bits; - struct { - byte grpPOLF :4; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} MCFLGSTR; -extern volatile MCFLGSTR _MCFLG @(REG_BASE + 0x00000067); -#define MCFLG _MCFLG.Byte -#define MCFLG_POLF0 _MCFLG.Bits.POLF0 -#define MCFLG_POLF1 _MCFLG.Bits.POLF1 -#define MCFLG_POLF2 _MCFLG.Bits.POLF2 -#define MCFLG_POLF3 _MCFLG.Bits.POLF3 -#define MCFLG_MCZF _MCFLG.Bits.MCZF -#define MCFLG_POLF _MCFLG.MergedBits.grpPOLF - - -/*** ICPAR - Input Control Pulse Accumulator Register; 0x00000068 ***/ -typedef union { - byte Byte; - struct { - byte PA0EN :1; /* 8-Bit Pulse Accumulator 0 Enable */ - byte PA1EN :1; /* 8-Bit Pulse Accumulator 1 Enable */ - byte PA2EN :1; /* 8-Bit Pulse Accumulator 2 Enable */ - byte PA3EN :1; /* 8-Bit Pulse Accumulator 3 Enable */ - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; -} ICPARSTR; -extern volatile ICPARSTR _ICPAR @(REG_BASE + 0x00000068); -#define ICPAR _ICPAR.Byte -#define ICPAR_PA0EN _ICPAR.Bits.PA0EN -#define ICPAR_PA1EN _ICPAR.Bits.PA1EN -#define ICPAR_PA2EN _ICPAR.Bits.PA2EN -#define ICPAR_PA3EN _ICPAR.Bits.PA3EN - - -/*** DLYCT - Delay Counter Control Register; 0x00000069 ***/ -typedef union { - byte Byte; - struct { - byte DLY0 :1; /* Delay Counter Select 0 */ - byte DLY1 :1; /* Delay Counter Select 1 */ - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpDLY :2; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} DLYCTSTR; -extern volatile DLYCTSTR _DLYCT @(REG_BASE + 0x00000069); -#define DLYCT _DLYCT.Byte -#define DLYCT_DLY0 _DLYCT.Bits.DLY0 -#define DLYCT_DLY1 _DLYCT.Bits.DLY1 -#define DLYCT_DLY _DLYCT.MergedBits.grpDLY - - -/*** ICOVW - Input Control Overwrite Register; 0x0000006A ***/ -typedef union { - byte Byte; - struct { - byte NOVW0 :1; /* No Input Capture Overwrite 0 */ - byte NOVW1 :1; /* No Input Capture Overwrite 1 */ - byte NOVW2 :1; /* No Input Capture Overwrite 2 */ - byte NOVW3 :1; /* No Input Capture Overwrite 3 */ - byte NOVW4 :1; /* No Input Capture Overwrite 4 */ - byte NOVW5 :1; /* No Input Capture Overwrite 5 */ - byte NOVW6 :1; /* No Input Capture Overwrite 6 */ - byte NOVW7 :1; /* No Input Capture Overwrite 7 */ - } Bits; - struct { - byte grpNOVW :8; - } MergedBits; -} ICOVWSTR; -extern volatile ICOVWSTR _ICOVW @(REG_BASE + 0x0000006A); -#define ICOVW _ICOVW.Byte -#define ICOVW_NOVW0 _ICOVW.Bits.NOVW0 -#define ICOVW_NOVW1 _ICOVW.Bits.NOVW1 -#define ICOVW_NOVW2 _ICOVW.Bits.NOVW2 -#define ICOVW_NOVW3 _ICOVW.Bits.NOVW3 -#define ICOVW_NOVW4 _ICOVW.Bits.NOVW4 -#define ICOVW_NOVW5 _ICOVW.Bits.NOVW5 -#define ICOVW_NOVW6 _ICOVW.Bits.NOVW6 -#define ICOVW_NOVW7 _ICOVW.Bits.NOVW7 -#define ICOVW_NOVW _ICOVW.MergedBits.grpNOVW - - -/*** ICSYS - Input Control System Control Register; 0x0000006B ***/ -typedef union { - byte Byte; - struct { - byte LATQ :1; /* Input Control Latch or Queue Mode Enable */ - byte BUFEN :1; /* IC Buffer Enable */ - byte PACMX :1; /* 8-Bit Pulse Accumulators Maximum Count */ - byte TFMOD :1; /* Timer Flag-setting Mode */ - byte SH04 :1; /* Share Input action of Input Capture Channels 0 and 4 */ - byte SH15 :1; /* Share Input action of Input Capture Channels 1 and 5 */ - byte SH26 :1; /* Share Input action of Input Capture Channels 2 and 6 */ - byte SH37 :1; /* Share Input action of Input Capture Channels 3 and 7 */ - } Bits; -} ICSYSSTR; -extern volatile ICSYSSTR _ICSYS @(REG_BASE + 0x0000006B); -#define ICSYS _ICSYS.Byte -#define ICSYS_LATQ _ICSYS.Bits.LATQ -#define ICSYS_BUFEN _ICSYS.Bits.BUFEN -#define ICSYS_PACMX _ICSYS.Bits.PACMX -#define ICSYS_TFMOD _ICSYS.Bits.TFMOD -#define ICSYS_SH04 _ICSYS.Bits.SH04 -#define ICSYS_SH15 _ICSYS.Bits.SH15 -#define ICSYS_SH26 _ICSYS.Bits.SH26 -#define ICSYS_SH37 _ICSYS.Bits.SH37 - - -/*** TIMTST - Timer Test Register; 0x0000006D ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte TCBYP :1; /* Main Timer Divider Chain Bypass */ - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; -} TIMTSTSTR; -extern volatile TIMTSTSTR _TIMTST @(REG_BASE + 0x0000006D); -#define TIMTST _TIMTST.Byte -#define TIMTST_TCBYP _TIMTST.Bits.TCBYP - - -/*** PBCTL - 16-Bit Pulse Accumulator B Control Register; 0x00000070 ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte PBOVI :1; /* Pulse Accumulator B Overflow Interrupt enable */ - byte :1; - byte :1; - byte :1; - byte :1; - byte PBEN :1; /* Pulse Accumulator B System Enable */ - byte :1; - } Bits; -} PBCTLSTR; -extern volatile PBCTLSTR _PBCTL @(REG_BASE + 0x00000070); -#define PBCTL _PBCTL.Byte -#define PBCTL_PBOVI _PBCTL.Bits.PBOVI -#define PBCTL_PBEN _PBCTL.Bits.PBEN - - -/*** PBFLG - Pulse Accumulator B Flag Register; 0x00000071 ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte PBOVF :1; /* Pulse Accumulator B Overflow Flag */ - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; -} PBFLGSTR; -extern volatile PBFLGSTR _PBFLG @(REG_BASE + 0x00000071); -#define PBFLG _PBFLG.Byte -#define PBFLG_PBOVF _PBFLG.Bits.PBOVF - - -/*** ATD0STAT0 - ATD 0 Status Register 0; 0x00000086 ***/ -typedef union { - byte Byte; - struct { - byte CC0 :1; /* Conversion Counter 0 */ - byte CC1 :1; /* Conversion Counter 1 */ - byte CC2 :1; /* Conversion Counter 2 */ - byte :1; - byte FIFOR :1; /* FIFO Over Run Flag */ - byte ETORF :1; /* External Trigger Overrun Flag */ - byte :1; - byte SCF :1; /* Sequence Complete Flag */ - } Bits; - struct { - byte grpCC :3; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} ATD0STAT0STR; -extern volatile ATD0STAT0STR _ATD0STAT0 @(REG_BASE + 0x00000086); -#define ATD0STAT0 _ATD0STAT0.Byte -#define ATD0STAT0_CC0 _ATD0STAT0.Bits.CC0 -#define ATD0STAT0_CC1 _ATD0STAT0.Bits.CC1 -#define ATD0STAT0_CC2 _ATD0STAT0.Bits.CC2 -#define ATD0STAT0_FIFOR _ATD0STAT0.Bits.FIFOR -#define ATD0STAT0_ETORF _ATD0STAT0.Bits.ETORF -#define ATD0STAT0_SCF _ATD0STAT0.Bits.SCF -#define ATD0STAT0_CC _ATD0STAT0.MergedBits.grpCC - - -/*** ATD0STAT1 - ATD 0 Status Register 1; 0x0000008B ***/ -typedef union { - byte Byte; - struct { - byte CCF0 :1; /* Conversion Complete Flag 0 */ - byte CCF1 :1; /* Conversion Complete Flag 1 */ - byte CCF2 :1; /* Conversion Complete Flag 2 */ - byte CCF3 :1; /* Conversion Complete Flag 3 */ - byte CCF4 :1; /* Conversion Complete Flag 4 */ - byte CCF5 :1; /* Conversion Complete Flag 5 */ - byte CCF6 :1; /* Conversion Complete Flag 6 */ - byte CCF7 :1; /* Conversion Complete Flag 7 */ - } Bits; - struct { - byte grpCCF :8; - } MergedBits; -} ATD0STAT1STR; -extern volatile ATD0STAT1STR _ATD0STAT1 @(REG_BASE + 0x0000008B); -#define ATD0STAT1 _ATD0STAT1.Byte -#define ATD0STAT1_CCF0 _ATD0STAT1.Bits.CCF0 -#define ATD0STAT1_CCF1 _ATD0STAT1.Bits.CCF1 -#define ATD0STAT1_CCF2 _ATD0STAT1.Bits.CCF2 -#define ATD0STAT1_CCF3 _ATD0STAT1.Bits.CCF3 -#define ATD0STAT1_CCF4 _ATD0STAT1.Bits.CCF4 -#define ATD0STAT1_CCF5 _ATD0STAT1.Bits.CCF5 -#define ATD0STAT1_CCF6 _ATD0STAT1.Bits.CCF6 -#define ATD0STAT1_CCF7 _ATD0STAT1.Bits.CCF7 -#define ATD0STAT1_CCF _ATD0STAT1.MergedBits.grpCCF - - -/*** ATD0DIEN - ATD 0 Input Enable Mask Register; 0x0000008D ***/ -typedef union { - byte Byte; - struct { - byte BIT0 :1; /* Disable/Enable Digital Input Buffer Bit 0 */ - byte BIT1 :1; /* Disable/Enable Digital Input Buffer Bit 1 */ - byte BIT2 :1; /* Disable/Enable Digital Input Buffer Bit 2 */ - byte BIT3 :1; /* Disable/Enable Digital Input Buffer Bit 3 */ - byte BIT4 :1; /* Disable/Enable Digital Input Buffer Bit 4 */ - byte BIT5 :1; /* Disable/Enable Digital Input Buffer Bit 5 */ - byte BIT6 :1; /* Disable/Enable Digital Input Buffer Bit 6 */ - byte BIT7 :1; /* Disable/Enable Digital Input Buffer Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; -} ATD0DIENSTR; -extern volatile ATD0DIENSTR _ATD0DIEN @(REG_BASE + 0x0000008D); -#define ATD0DIEN _ATD0DIEN.Byte -#define ATD0DIEN_BIT0 _ATD0DIEN.Bits.BIT0 -#define ATD0DIEN_BIT1 _ATD0DIEN.Bits.BIT1 -#define ATD0DIEN_BIT2 _ATD0DIEN.Bits.BIT2 -#define ATD0DIEN_BIT3 _ATD0DIEN.Bits.BIT3 -#define ATD0DIEN_BIT4 _ATD0DIEN.Bits.BIT4 -#define ATD0DIEN_BIT5 _ATD0DIEN.Bits.BIT5 -#define ATD0DIEN_BIT6 _ATD0DIEN.Bits.BIT6 -#define ATD0DIEN_BIT7 _ATD0DIEN.Bits.BIT7 -#define ATD0DIEN_BIT _ATD0DIEN.MergedBits.grpBIT - - -/*** PORTAD0 - Port AD0 Register; 0x0000008F ***/ -typedef union { - byte Byte; - struct { - byte BIT0 :1; /* AN0 */ - byte BIT1 :1; /* AN1 */ - byte BIT2 :1; /* AN2 */ - byte BIT3 :1; /* AN3 */ - byte BIT4 :1; /* AN4 */ - byte BIT5 :1; /* AN5 */ - byte BIT6 :1; /* AN6 */ - byte BIT7 :1; /* AN7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; -} PORTAD0STR; -extern volatile PORTAD0STR _PORTAD0 @(REG_BASE + 0x0000008F); -#define PORTAD0 _PORTAD0.Byte -#define PORTAD0_BIT0 _PORTAD0.Bits.BIT0 -#define PORTAD0_BIT1 _PORTAD0.Bits.BIT1 -#define PORTAD0_BIT2 _PORTAD0.Bits.BIT2 -#define PORTAD0_BIT3 _PORTAD0.Bits.BIT3 -#define PORTAD0_BIT4 _PORTAD0.Bits.BIT4 -#define PORTAD0_BIT5 _PORTAD0.Bits.BIT5 -#define PORTAD0_BIT6 _PORTAD0.Bits.BIT6 -#define PORTAD0_BIT7 _PORTAD0.Bits.BIT7 -#define PORTAD0_BIT _PORTAD0.MergedBits.grpBIT - - -/*** PWME - PWM Enable Register; 0x000000A0 ***/ -typedef union { - byte Byte; - struct { - byte PWME0 :1; /* Pulse Width Channel 0 Enable */ - byte PWME1 :1; /* Pulse Width Channel 1 Enable */ - byte PWME2 :1; /* Pulse Width Channel 2 Enable */ - byte PWME3 :1; /* Pulse Width Channel 3 Enable */ - byte PWME4 :1; /* Pulse Width Channel 4 Enable */ - byte PWME5 :1; /* Pulse Width Channel 5 Enable */ - byte PWME6 :1; /* Pulse Width Channel 6 Enable */ - byte PWME7 :1; /* Pulse Width Channel 7 Enable */ - } Bits; - struct { - byte grpPWME :8; - } MergedBits; -} PWMESTR; -extern volatile PWMESTR _PWME @(REG_BASE + 0x000000A0); -#define PWME _PWME.Byte -#define PWME_PWME0 _PWME.Bits.PWME0 -#define PWME_PWME1 _PWME.Bits.PWME1 -#define PWME_PWME2 _PWME.Bits.PWME2 -#define PWME_PWME3 _PWME.Bits.PWME3 -#define PWME_PWME4 _PWME.Bits.PWME4 -#define PWME_PWME5 _PWME.Bits.PWME5 -#define PWME_PWME6 _PWME.Bits.PWME6 -#define PWME_PWME7 _PWME.Bits.PWME7 -#define PWME_PWME _PWME.MergedBits.grpPWME - - -/*** PWMPOL - PWM Polarity Register; 0x000000A1 ***/ -typedef union { - byte Byte; - struct { - byte PPOL0 :1; /* Pulse Width Channel 0 Polarity */ - byte PPOL1 :1; /* Pulse Width Channel 1 Polarity */ - byte PPOL2 :1; /* Pulse Width Channel 2 Polarity */ - byte PPOL3 :1; /* Pulse Width Channel 3 Polarity */ - byte PPOL4 :1; /* Pulse Width Channel 4 Polarity */ - byte PPOL5 :1; /* Pulse Width Channel 5 Polarity */ - byte PPOL6 :1; /* Pulse Width Channel 6 Polarity */ - byte PPOL7 :1; /* Pulse Width Channel 7 Polarity */ - } Bits; - struct { - byte grpPPOL :8; - } MergedBits; -} PWMPOLSTR; -extern volatile PWMPOLSTR _PWMPOL @(REG_BASE + 0x000000A1); -#define PWMPOL _PWMPOL.Byte -#define PWMPOL_PPOL0 _PWMPOL.Bits.PPOL0 -#define PWMPOL_PPOL1 _PWMPOL.Bits.PPOL1 -#define PWMPOL_PPOL2 _PWMPOL.Bits.PPOL2 -#define PWMPOL_PPOL3 _PWMPOL.Bits.PPOL3 -#define PWMPOL_PPOL4 _PWMPOL.Bits.PPOL4 -#define PWMPOL_PPOL5 _PWMPOL.Bits.PPOL5 -#define PWMPOL_PPOL6 _PWMPOL.Bits.PPOL6 -#define PWMPOL_PPOL7 _PWMPOL.Bits.PPOL7 -#define PWMPOL_PPOL _PWMPOL.MergedBits.grpPPOL - - -/*** PWMCLK - PWM Clock Select Register; 0x000000A2 ***/ -typedef union { - byte Byte; - struct { - byte PCLK0 :1; /* Pulse Width Channel 0 Clock Select */ - byte PCLK1 :1; /* Pulse Width Channel 1 Clock Select */ - byte PCLK2 :1; /* Pulse Width Channel 2 Clock Select */ - byte PCLK3 :1; /* Pulse Width Channel 3 Clock Select */ - byte PCLK4 :1; /* Pulse Width Channel 4 Clock Select */ - byte PCLK5 :1; /* Pulse Width Channel 5 Clock Select */ - byte PCLK6 :1; /* Pulse Width Channel 6 Clock Select */ - byte PCLK7 :1; /* Pulse Width Channel 7 Clock Select */ - } Bits; - struct { - byte grpPCLK :8; - } MergedBits; -} PWMCLKSTR; -extern volatile PWMCLKSTR _PWMCLK @(REG_BASE + 0x000000A2); -#define PWMCLK _PWMCLK.Byte -#define PWMCLK_PCLK0 _PWMCLK.Bits.PCLK0 -#define PWMCLK_PCLK1 _PWMCLK.Bits.PCLK1 -#define PWMCLK_PCLK2 _PWMCLK.Bits.PCLK2 -#define PWMCLK_PCLK3 _PWMCLK.Bits.PCLK3 -#define PWMCLK_PCLK4 _PWMCLK.Bits.PCLK4 -#define PWMCLK_PCLK5 _PWMCLK.Bits.PCLK5 -#define PWMCLK_PCLK6 _PWMCLK.Bits.PCLK6 -#define PWMCLK_PCLK7 _PWMCLK.Bits.PCLK7 -#define PWMCLK_PCLK _PWMCLK.MergedBits.grpPCLK - - -/*** PWMPRCLK - PWM Prescale Clock Select Register; 0x000000A3 ***/ -typedef union { - byte Byte; - struct { - byte PCKA0 :1; /* Prescaler Select for Clock A 0 */ - byte PCKA1 :1; /* Prescaler Select for Clock A 1 */ - byte PCKA2 :1; /* Prescaler Select for Clock A 2 */ - byte :1; - byte PCKB0 :1; /* Prescaler Select for Clock B 0 */ - byte PCKB1 :1; /* Prescaler Select for Clock B 1 */ - byte PCKB2 :1; /* Prescaler Select for Clock B 2 */ - byte :1; - } Bits; - struct { - byte grpPCKA :3; - byte :1; - byte grpPCKB :3; - byte :1; - } MergedBits; -} PWMPRCLKSTR; -extern volatile PWMPRCLKSTR _PWMPRCLK @(REG_BASE + 0x000000A3); -#define PWMPRCLK _PWMPRCLK.Byte -#define PWMPRCLK_PCKA0 _PWMPRCLK.Bits.PCKA0 -#define PWMPRCLK_PCKA1 _PWMPRCLK.Bits.PCKA1 -#define PWMPRCLK_PCKA2 _PWMPRCLK.Bits.PCKA2 -#define PWMPRCLK_PCKB0 _PWMPRCLK.Bits.PCKB0 -#define PWMPRCLK_PCKB1 _PWMPRCLK.Bits.PCKB1 -#define PWMPRCLK_PCKB2 _PWMPRCLK.Bits.PCKB2 -#define PWMPRCLK_PCKA _PWMPRCLK.MergedBits.grpPCKA -#define PWMPRCLK_PCKB _PWMPRCLK.MergedBits.grpPCKB - - -/*** PWMCAE - PWM Center Align Enable Register; 0x000000A4 ***/ -typedef union { - byte Byte; - struct { - byte CAE0 :1; /* Center Aligned Output Mode on channel 0 */ - byte CAE1 :1; /* Center Aligned Output Mode on channel 1 */ - byte CAE2 :1; /* Center Aligned Output Mode on channel 2 */ - byte CAE3 :1; /* Center Aligned Output Mode on channel 3 */ - byte CAE4 :1; /* Center Aligned Output Mode on channel 4 */ - byte CAE5 :1; /* Center Aligned Output Mode on channel 5 */ - byte CAE6 :1; /* Center Aligned Output Mode on channel 6 */ - byte CAE7 :1; /* Center Aligned Output Mode on channel 7 */ - } Bits; - struct { - byte grpCAE :8; - } MergedBits; -} PWMCAESTR; -extern volatile PWMCAESTR _PWMCAE @(REG_BASE + 0x000000A4); -#define PWMCAE _PWMCAE.Byte -#define PWMCAE_CAE0 _PWMCAE.Bits.CAE0 -#define PWMCAE_CAE1 _PWMCAE.Bits.CAE1 -#define PWMCAE_CAE2 _PWMCAE.Bits.CAE2 -#define PWMCAE_CAE3 _PWMCAE.Bits.CAE3 -#define PWMCAE_CAE4 _PWMCAE.Bits.CAE4 -#define PWMCAE_CAE5 _PWMCAE.Bits.CAE5 -#define PWMCAE_CAE6 _PWMCAE.Bits.CAE6 -#define PWMCAE_CAE7 _PWMCAE.Bits.CAE7 -#define PWMCAE_CAE _PWMCAE.MergedBits.grpCAE - - -/*** PWMCTL - PWM Control Register; 0x000000A5 ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte :1; - byte PFRZ :1; /* PWM Counters Stop in Freeze Mode */ - byte PSWAI :1; /* PWM Stops in Wait Mode */ - byte CON01 :1; /* Concatenate channels 0 and 1 */ - byte CON23 :1; /* Concatenate channels 2 and 3 */ - byte CON45 :1; /* Concatenate channels 4 and 5 */ - byte CON67 :1; /* Concatenate channels 6 and 7 */ - } Bits; -} PWMCTLSTR; -extern volatile PWMCTLSTR _PWMCTL @(REG_BASE + 0x000000A5); -#define PWMCTL _PWMCTL.Byte -#define PWMCTL_PFRZ _PWMCTL.Bits.PFRZ -#define PWMCTL_PSWAI _PWMCTL.Bits.PSWAI -#define PWMCTL_CON01 _PWMCTL.Bits.CON01 -#define PWMCTL_CON23 _PWMCTL.Bits.CON23 -#define PWMCTL_CON45 _PWMCTL.Bits.CON45 -#define PWMCTL_CON67 _PWMCTL.Bits.CON67 - - -/*** PWMSCLA - PWM Scale A Register; 0x000000A8 ***/ -typedef union { - byte Byte; - struct { - byte BIT0 :1; /* PWM Scale A Bit 0 */ - byte BIT1 :1; /* PWM Scale A Bit 1 */ - byte BIT2 :1; /* PWM Scale A Bit 2 */ - byte BIT3 :1; /* PWM Scale A Bit 3 */ - byte BIT4 :1; /* PWM Scale A Bit 4 */ - byte BIT5 :1; /* PWM Scale A Bit 5 */ - byte BIT6 :1; /* PWM Scale A Bit 6 */ - byte BIT7 :1; /* PWM Scale A Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; -} PWMSCLASTR; -extern volatile PWMSCLASTR _PWMSCLA @(REG_BASE + 0x000000A8); -#define PWMSCLA _PWMSCLA.Byte -#define PWMSCLA_BIT0 _PWMSCLA.Bits.BIT0 -#define PWMSCLA_BIT1 _PWMSCLA.Bits.BIT1 -#define PWMSCLA_BIT2 _PWMSCLA.Bits.BIT2 -#define PWMSCLA_BIT3 _PWMSCLA.Bits.BIT3 -#define PWMSCLA_BIT4 _PWMSCLA.Bits.BIT4 -#define PWMSCLA_BIT5 _PWMSCLA.Bits.BIT5 -#define PWMSCLA_BIT6 _PWMSCLA.Bits.BIT6 -#define PWMSCLA_BIT7 _PWMSCLA.Bits.BIT7 -#define PWMSCLA_BIT _PWMSCLA.MergedBits.grpBIT - - -/*** PWMSCLB - PWM Scale B Register; 0x000000A9 ***/ -typedef union { - byte Byte; - struct { - byte BIT0 :1; /* PWM Scale B Bit 0 */ - byte BIT1 :1; /* PWM Scale B Bit 1 */ - byte BIT2 :1; /* PWM Scale B Bit 2 */ - byte BIT3 :1; /* PWM Scale B Bit 3 */ - byte BIT4 :1; /* PWM Scale B Bit 4 */ - byte BIT5 :1; /* PWM Scale B Bit 5 */ - byte BIT6 :1; /* PWM Scale B Bit 6 */ - byte BIT7 :1; /* PWM Scale B Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; -} PWMSCLBSTR; -extern volatile PWMSCLBSTR _PWMSCLB @(REG_BASE + 0x000000A9); -#define PWMSCLB _PWMSCLB.Byte -#define PWMSCLB_BIT0 _PWMSCLB.Bits.BIT0 -#define PWMSCLB_BIT1 _PWMSCLB.Bits.BIT1 -#define PWMSCLB_BIT2 _PWMSCLB.Bits.BIT2 -#define PWMSCLB_BIT3 _PWMSCLB.Bits.BIT3 -#define PWMSCLB_BIT4 _PWMSCLB.Bits.BIT4 -#define PWMSCLB_BIT5 _PWMSCLB.Bits.BIT5 -#define PWMSCLB_BIT6 _PWMSCLB.Bits.BIT6 -#define PWMSCLB_BIT7 _PWMSCLB.Bits.BIT7 -#define PWMSCLB_BIT _PWMSCLB.MergedBits.grpBIT - - -/*** PWMSDN - PWM Shutdown Register; 0x000000C4 ***/ -typedef union { - byte Byte; - struct { - byte PWM7ENA :1; /* PWM emergency shutdown Enable */ - byte PWM7INL :1; /* PWM shutdown active input level for ch. 7 */ - byte PWM7IN :1; /* PWM channel 7 input status */ - byte :1; - byte PWMLVL :1; /* PWM shutdown output Level */ - byte PWMRSTRT :1; /* PWM Restart */ - byte PWMIE :1; /* PWM Interrupt Enable */ - byte PWMIF :1; /* PWM Interrupt Flag */ - } Bits; -} PWMSDNSTR; -extern volatile PWMSDNSTR _PWMSDN @(REG_BASE + 0x000000C4); -#define PWMSDN _PWMSDN.Byte -#define PWMSDN_PWM7ENA _PWMSDN.Bits.PWM7ENA -#define PWMSDN_PWM7INL _PWMSDN.Bits.PWM7INL -#define PWMSDN_PWM7IN _PWMSDN.Bits.PWM7IN -#define PWMSDN_PWMLVL _PWMSDN.Bits.PWMLVL -#define PWMSDN_PWMRSTRT _PWMSDN.Bits.PWMRSTRT -#define PWMSDN_PWMIE _PWMSDN.Bits.PWMIE -#define PWMSDN_PWMIF _PWMSDN.Bits.PWMIF - - -/*** SCI0CR1 - SCI 0 Control Register 1; 0x000000CA ***/ -typedef union { - byte Byte; - struct { - byte PT :1; /* Parity Type Bit */ - byte PE :1; /* Parity Enable Bit */ - byte ILT :1; /* Idle Line Type Bit */ - byte WAKE :1; /* Wakeup Condition Bit */ - byte M :1; /* Data Format Mode Bit */ - byte RSRC :1; /* Receiver Source Bit */ - byte SCISWAI :1; /* SCI 0 Stop in Wait Mode Bit */ - byte LOOPS :1; /* Loop Select Bit */ - } Bits; -} SCI0CR1STR; -extern volatile SCI0CR1STR _SCI0CR1 @(REG_BASE + 0x000000CA); -#define SCI0CR1 _SCI0CR1.Byte -#define SCI0CR1_PT _SCI0CR1.Bits.PT -#define SCI0CR1_PE _SCI0CR1.Bits.PE -#define SCI0CR1_ILT _SCI0CR1.Bits.ILT -#define SCI0CR1_WAKE _SCI0CR1.Bits.WAKE -#define SCI0CR1_M _SCI0CR1.Bits.M -#define SCI0CR1_RSRC _SCI0CR1.Bits.RSRC -#define SCI0CR1_SCISWAI _SCI0CR1.Bits.SCISWAI -#define SCI0CR1_LOOPS _SCI0CR1.Bits.LOOPS - - -/*** SCI0CR2 - SCI 0 Control Register 2; 0x000000CB ***/ -typedef union { - byte Byte; - struct { - byte SBK :1; /* Send Break Bit */ - byte RWU :1; /* Receiver Wakeup Bit */ - byte RE :1; /* Receiver Enable Bit */ - byte TE :1; /* Transmitter Enable Bit */ - byte ILIE :1; /* Idle Line Interrupt Enable Bit */ - byte RIE :1; /* Receiver Full Interrupt Enable Bit */ - byte TCIE :1; /* Transmission Complete Interrupt Enable Bit */ - byte SCTIE :1; /* Transmitter Interrupt Enable Bit */ - } Bits; -} SCI0CR2STR; -extern volatile SCI0CR2STR _SCI0CR2 @(REG_BASE + 0x000000CB); -#define SCI0CR2 _SCI0CR2.Byte -#define SCI0CR2_SBK _SCI0CR2.Bits.SBK -#define SCI0CR2_RWU _SCI0CR2.Bits.RWU -#define SCI0CR2_RE _SCI0CR2.Bits.RE -#define SCI0CR2_TE _SCI0CR2.Bits.TE -#define SCI0CR2_ILIE _SCI0CR2.Bits.ILIE -#define SCI0CR2_RIE _SCI0CR2.Bits.RIE -#define SCI0CR2_TCIE _SCI0CR2.Bits.TCIE -#define SCI0CR2_SCTIE _SCI0CR2.Bits.SCTIE - - -/*** SCI0SR1 - SCI 0 Status Register 1; 0x000000CC ***/ -typedef union { - byte Byte; - struct { - byte PF :1; /* Parity Error Flag */ - byte FE :1; /* Framing Error Flag */ - byte NF :1; /* Noise Flag */ - byte OR :1; /* Overrun Flag */ - byte IDLE :1; /* Idle Line Flag */ - byte RDRF :1; /* Receive Data Register Full Flag */ - byte TC :1; /* Transmit Complete Flag */ - byte TDRE :1; /* Transmit Data Register Empty Flag */ - } Bits; -} SCI0SR1STR; -extern volatile SCI0SR1STR _SCI0SR1 @(REG_BASE + 0x000000CC); -#define SCI0SR1 _SCI0SR1.Byte -#define SCI0SR1_PF _SCI0SR1.Bits.PF -#define SCI0SR1_FE _SCI0SR1.Bits.FE -#define SCI0SR1_NF _SCI0SR1.Bits.NF -#define SCI0SR1_OR _SCI0SR1.Bits.OR -#define SCI0SR1_IDLE _SCI0SR1.Bits.IDLE -#define SCI0SR1_RDRF _SCI0SR1.Bits.RDRF -#define SCI0SR1_TC _SCI0SR1.Bits.TC -#define SCI0SR1_TDRE _SCI0SR1.Bits.TDRE - - -/*** SCI0SR2 - SCI 0 Status Register 2; 0x000000CD ***/ -typedef union { - byte Byte; - struct { - byte RAF :1; /* Receiver Active Flag */ - byte TXDIR :1; /* Transmitter pin data direction in Single-Wire mode */ - byte BRK13 :1; /* Break Transmit character length */ - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; -} SCI0SR2STR; -extern volatile SCI0SR2STR _SCI0SR2 @(REG_BASE + 0x000000CD); -#define SCI0SR2 _SCI0SR2.Byte -#define SCI0SR2_RAF _SCI0SR2.Bits.RAF -#define SCI0SR2_TXDIR _SCI0SR2.Bits.TXDIR -#define SCI0SR2_BRK13 _SCI0SR2.Bits.BRK13 - - -/*** SCI0DRH - SCI 0 Data Register High; 0x000000CE ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte T8 :1; /* Transmit Bit 8 */ - byte R8 :1; /* Received Bit 8 */ - } Bits; -} SCI0DRHSTR; -extern volatile SCI0DRHSTR _SCI0DRH @(REG_BASE + 0x000000CE); -#define SCI0DRH _SCI0DRH.Byte -#define SCI0DRH_T8 _SCI0DRH.Bits.T8 -#define SCI0DRH_R8 _SCI0DRH.Bits.R8 - - -/*** SCI0DRL - SCI 0 Data Register Low; 0x000000CF ***/ -typedef union { - byte Byte; - struct { - byte R0_T0 :1; /* Received bit 0 or Transmit bit 0 */ - byte R1_T1 :1; /* Received bit 1 or Transmit bit 1 */ - byte R2_T2 :1; /* Received bit 2 or Transmit bit 2 */ - byte R3_T3 :1; /* Received bit 3 or Transmit bit 3 */ - byte R4_T4 :1; /* Received bit 4 or Transmit bit 4 */ - byte R5_T5 :1; /* Received bit 5 or Transmit bit 5 */ - byte R6_T6 :1; /* Received bit 6 or Transmit bit 6 */ - byte R7_T7 :1; /* Received bit 7 or Transmit bit 7 */ - } Bits; -} SCI0DRLSTR; -extern volatile SCI0DRLSTR _SCI0DRL @(REG_BASE + 0x000000CF); -#define SCI0DRL _SCI0DRL.Byte -#define SCI0DRL_R0_T0 _SCI0DRL.Bits.R0_T0 -#define SCI0DRL_R1_T1 _SCI0DRL.Bits.R1_T1 -#define SCI0DRL_R2_T2 _SCI0DRL.Bits.R2_T2 -#define SCI0DRL_R3_T3 _SCI0DRL.Bits.R3_T3 -#define SCI0DRL_R4_T4 _SCI0DRL.Bits.R4_T4 -#define SCI0DRL_R5_T5 _SCI0DRL.Bits.R5_T5 -#define SCI0DRL_R6_T6 _SCI0DRL.Bits.R6_T6 -#define SCI0DRL_R7_T7 _SCI0DRL.Bits.R7_T7 - - -/*** SCI1CR1 - SCI 1 Control Register 1; 0x000000D2 ***/ -typedef union { - byte Byte; - struct { - byte PT :1; /* Parity Type Bit */ - byte PE :1; /* Parity Enable Bit */ - byte ILT :1; /* Idle Line Type Bit */ - byte WAKE :1; /* Wakeup Condition Bit */ - byte M :1; /* Data Format Mode Bit */ - byte RSRC :1; /* Receiver Source Bit */ - byte SCISWAI :1; /* SCI 1 Stop in Wait Mode Bit */ - byte LOOPS :1; /* Loop Select Bit */ - } Bits; -} SCI1CR1STR; -extern volatile SCI1CR1STR _SCI1CR1 @(REG_BASE + 0x000000D2); -#define SCI1CR1 _SCI1CR1.Byte -#define SCI1CR1_PT _SCI1CR1.Bits.PT -#define SCI1CR1_PE _SCI1CR1.Bits.PE -#define SCI1CR1_ILT _SCI1CR1.Bits.ILT -#define SCI1CR1_WAKE _SCI1CR1.Bits.WAKE -#define SCI1CR1_M _SCI1CR1.Bits.M -#define SCI1CR1_RSRC _SCI1CR1.Bits.RSRC -#define SCI1CR1_SCISWAI _SCI1CR1.Bits.SCISWAI -#define SCI1CR1_LOOPS _SCI1CR1.Bits.LOOPS - - -/*** SCI1CR2 - SCI 1 Control Register 2; 0x000000D3 ***/ -typedef union { - byte Byte; - struct { - byte SBK :1; /* Send Break Bit */ - byte RWU :1; /* Receiver Wakeup Bit */ - byte RE :1; /* Receiver Enable Bit */ - byte TE :1; /* Transmitter Enable Bit */ - byte ILIE :1; /* Idle Line Interrupt Enable Bit */ - byte RIE :1; /* Receiver Full Interrupt Enable Bit */ - byte TCIE :1; /* Transmission Complete Interrupt Enable Bit */ - byte SCTIE :1; /* Transmitter Interrupt Enable Bit */ - } Bits; -} SCI1CR2STR; -extern volatile SCI1CR2STR _SCI1CR2 @(REG_BASE + 0x000000D3); -#define SCI1CR2 _SCI1CR2.Byte -#define SCI1CR2_SBK _SCI1CR2.Bits.SBK -#define SCI1CR2_RWU _SCI1CR2.Bits.RWU -#define SCI1CR2_RE _SCI1CR2.Bits.RE -#define SCI1CR2_TE _SCI1CR2.Bits.TE -#define SCI1CR2_ILIE _SCI1CR2.Bits.ILIE -#define SCI1CR2_RIE _SCI1CR2.Bits.RIE -#define SCI1CR2_TCIE _SCI1CR2.Bits.TCIE -#define SCI1CR2_SCTIE _SCI1CR2.Bits.SCTIE - - -/*** SCI1SR1 - SCI 1 Status Register 1; 0x000000D4 ***/ -typedef union { - byte Byte; - struct { - byte PF :1; /* Parity Error Flag */ - byte FE :1; /* Framing Error Flag */ - byte NF :1; /* Noise Flag */ - byte OR :1; /* Overrun Flag */ - byte IDLE :1; /* Idle Line Flag */ - byte RDRF :1; /* Receive Data Register Full Flag */ - byte TC :1; /* Transmit Complete Flag */ - byte TDRE :1; /* Transmit Data Register Empty Flag */ - } Bits; -} SCI1SR1STR; -extern volatile SCI1SR1STR _SCI1SR1 @(REG_BASE + 0x000000D4); -#define SCI1SR1 _SCI1SR1.Byte -#define SCI1SR1_PF _SCI1SR1.Bits.PF -#define SCI1SR1_FE _SCI1SR1.Bits.FE -#define SCI1SR1_NF _SCI1SR1.Bits.NF -#define SCI1SR1_OR _SCI1SR1.Bits.OR -#define SCI1SR1_IDLE _SCI1SR1.Bits.IDLE -#define SCI1SR1_RDRF _SCI1SR1.Bits.RDRF -#define SCI1SR1_TC _SCI1SR1.Bits.TC -#define SCI1SR1_TDRE _SCI1SR1.Bits.TDRE - - -/*** SCI1SR2 - SCI 1 Status Register 2; 0x000000D5 ***/ -typedef union { - byte Byte; - struct { - byte RAF :1; /* Receiver Active Flag */ - byte TXDIR :1; /* Transmitter pin data direction in Single-Wire mode */ - byte BRK13 :1; /* Break Transmit character length */ - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; -} SCI1SR2STR; -extern volatile SCI1SR2STR _SCI1SR2 @(REG_BASE + 0x000000D5); -#define SCI1SR2 _SCI1SR2.Byte -#define SCI1SR2_RAF _SCI1SR2.Bits.RAF -#define SCI1SR2_TXDIR _SCI1SR2.Bits.TXDIR -#define SCI1SR2_BRK13 _SCI1SR2.Bits.BRK13 - - -/*** SCI1DRH - SCI 1 Data Register High; 0x000000D6 ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte T8 :1; /* Transmit Bit 8 */ - byte R8 :1; /* Received Bit 8 */ - } Bits; -} SCI1DRHSTR; -extern volatile SCI1DRHSTR _SCI1DRH @(REG_BASE + 0x000000D6); -#define SCI1DRH _SCI1DRH.Byte -#define SCI1DRH_T8 _SCI1DRH.Bits.T8 -#define SCI1DRH_R8 _SCI1DRH.Bits.R8 - - -/*** SCI1DRL - SCI 1 Data Register Low; 0x000000D7 ***/ -typedef union { - byte Byte; - struct { - byte R0_T0 :1; /* Received bit 0 or Transmit bit 0 */ - byte R1_T1 :1; /* Received bit 1 or Transmit bit 1 */ - byte R2_T2 :1; /* Received bit 2 or Transmit bit 2 */ - byte R3_T3 :1; /* Received bit 3 or Transmit bit 3 */ - byte R4_T4 :1; /* Received bit 4 or Transmit bit 4 */ - byte R5_T5 :1; /* Received bit 5 or Transmit bit 5 */ - byte R6_T6 :1; /* Received bit 6 or Transmit bit 6 */ - byte R7_T7 :1; /* Received bit 7 or Transmit bit 7 */ - } Bits; -} SCI1DRLSTR; -extern volatile SCI1DRLSTR _SCI1DRL @(REG_BASE + 0x000000D7); -#define SCI1DRL _SCI1DRL.Byte -#define SCI1DRL_R0_T0 _SCI1DRL.Bits.R0_T0 -#define SCI1DRL_R1_T1 _SCI1DRL.Bits.R1_T1 -#define SCI1DRL_R2_T2 _SCI1DRL.Bits.R2_T2 -#define SCI1DRL_R3_T3 _SCI1DRL.Bits.R3_T3 -#define SCI1DRL_R4_T4 _SCI1DRL.Bits.R4_T4 -#define SCI1DRL_R5_T5 _SCI1DRL.Bits.R5_T5 -#define SCI1DRL_R6_T6 _SCI1DRL.Bits.R6_T6 -#define SCI1DRL_R7_T7 _SCI1DRL.Bits.R7_T7 - - -/*** SPI0CR1 - SPI 0 Control Register; 0x000000D8 ***/ -typedef union { - byte Byte; - struct { - byte LSBFE :1; /* SPI 0 LSB-First Enable */ - byte SSOE :1; /* Slave Select Output Enable */ - byte CPHA :1; /* SPI 0 Clock Phase Bit */ - byte CPOL :1; /* SPI 0 Clock Polarity Bit */ - byte MSTR :1; /* SPI 0 Master/Slave Mode Select Bit */ - byte SPTIE :1; /* SPI 0 Transmit Interrupt Enable */ - byte SPE :1; /* SPI 0 System Enable Bit */ - byte SPIE :1; /* SPI 0 Interrupt Enable Bit */ - } Bits; -} SPI0CR1STR; -extern volatile SPI0CR1STR _SPI0CR1 @(REG_BASE + 0x000000D8); -#define SPI0CR1 _SPI0CR1.Byte -#define SPI0CR1_LSBFE _SPI0CR1.Bits.LSBFE -#define SPI0CR1_SSOE _SPI0CR1.Bits.SSOE -#define SPI0CR1_CPHA _SPI0CR1.Bits.CPHA -#define SPI0CR1_CPOL _SPI0CR1.Bits.CPOL -#define SPI0CR1_MSTR _SPI0CR1.Bits.MSTR -#define SPI0CR1_SPTIE _SPI0CR1.Bits.SPTIE -#define SPI0CR1_SPE _SPI0CR1.Bits.SPE -#define SPI0CR1_SPIE _SPI0CR1.Bits.SPIE - - -/*** SPI0CR2 - SPI 0 Control Register 2; 0x000000D9 ***/ -typedef union { - byte Byte; - struct { - byte SPC0 :1; /* Serial Pin Control Bit 0 */ - byte SPISWAI :1; /* SPI 0 Stop in Wait Mode Bit */ - byte :1; - byte BIDIROE :1; /* Output enable in the Bidirectional mode of operation */ - byte MODFEN :1; /* Mode Fault Enable Bit */ - byte :1; - byte :1; - byte :1; - } Bits; -} SPI0CR2STR; -extern volatile SPI0CR2STR _SPI0CR2 @(REG_BASE + 0x000000D9); -#define SPI0CR2 _SPI0CR2.Byte -#define SPI0CR2_SPC0 _SPI0CR2.Bits.SPC0 -#define SPI0CR2_SPISWAI _SPI0CR2.Bits.SPISWAI -#define SPI0CR2_BIDIROE _SPI0CR2.Bits.BIDIROE -#define SPI0CR2_MODFEN _SPI0CR2.Bits.MODFEN - - -/*** SPI0BR - SPI 0 Baud Rate Register; 0x000000DA ***/ -typedef union { - byte Byte; - struct { - byte SPR0 :1; /* SPI 0 Baud Rate Selection Bit 0 */ - byte SPR1 :1; /* SPI 0 Baud Rate Selection Bit 1 */ - byte SPR2 :1; /* SPI 0 Baud Rate Selection Bit 2 */ - byte :1; - byte SPPR0 :1; /* SPI 0 Baud Rate Preselection Bits 0 */ - byte SPPR1 :1; /* SPI 0 Baud Rate Preselection Bits 1 */ - byte SPPR2 :1; /* SPI 0 Baud Rate Preselection Bits 2 */ - byte :1; - } Bits; - struct { - byte grpSPR :3; - byte :1; - byte grpSPPR :3; - byte :1; - } MergedBits; -} SPI0BRSTR; -extern volatile SPI0BRSTR _SPI0BR @(REG_BASE + 0x000000DA); -#define SPI0BR _SPI0BR.Byte -#define SPI0BR_SPR0 _SPI0BR.Bits.SPR0 -#define SPI0BR_SPR1 _SPI0BR.Bits.SPR1 -#define SPI0BR_SPR2 _SPI0BR.Bits.SPR2 -#define SPI0BR_SPPR0 _SPI0BR.Bits.SPPR0 -#define SPI0BR_SPPR1 _SPI0BR.Bits.SPPR1 -#define SPI0BR_SPPR2 _SPI0BR.Bits.SPPR2 -#define SPI0BR_SPR _SPI0BR.MergedBits.grpSPR -#define SPI0BR_SPPR _SPI0BR.MergedBits.grpSPPR - - -/*** SPI0SR - SPI 0 Status Register; 0x000000DB ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte MODF :1; /* Mode Fault Flag */ - byte SPTEF :1; /* SPI 0 Transmit Empty Interrupt Flag */ - byte :1; - byte SPIF :1; /* SPIF Receive Interrupt Flag */ - } Bits; -} SPI0SRSTR; -extern volatile SPI0SRSTR _SPI0SR @(REG_BASE + 0x000000DB); -#define SPI0SR _SPI0SR.Byte -#define SPI0SR_MODF _SPI0SR.Bits.MODF -#define SPI0SR_SPTEF _SPI0SR.Bits.SPTEF -#define SPI0SR_SPIF _SPI0SR.Bits.SPIF - - -/*** SPI0DR - SPI 0 Data Register; 0x000000DD ***/ -typedef union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; -} SPI0DRSTR; -extern volatile SPI0DRSTR _SPI0DR @(REG_BASE + 0x000000DD); -#define SPI0DR _SPI0DR.Byte -#define SPI0DR_BIT _SPI0DR.MergedBits.grpBIT - - -/*** IBAD - IIC Address Register; 0x000000E0 ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte ADR1 :1; /* Slave Address Bit 1 */ - byte ADR2 :1; /* Slave Address Bit 2 */ - byte ADR3 :1; /* Slave Address Bit 3 */ - byte ADR4 :1; /* Slave Address Bit 4 */ - byte ADR5 :1; /* Slave Address Bit 5 */ - byte ADR6 :1; /* Slave Address Bit 6 */ - byte ADR7 :1; /* Slave Address Bit 7 */ - } Bits; - struct { - byte :1; - byte grpADR_1 :7; - } MergedBits; -} IBADSTR; -extern volatile IBADSTR _IBAD @(REG_BASE + 0x000000E0); -#define IBAD _IBAD.Byte -#define IBAD_ADR1 _IBAD.Bits.ADR1 -#define IBAD_ADR2 _IBAD.Bits.ADR2 -#define IBAD_ADR3 _IBAD.Bits.ADR3 -#define IBAD_ADR4 _IBAD.Bits.ADR4 -#define IBAD_ADR5 _IBAD.Bits.ADR5 -#define IBAD_ADR6 _IBAD.Bits.ADR6 -#define IBAD_ADR7 _IBAD.Bits.ADR7 -#define IBAD_ADR_1 _IBAD.MergedBits.grpADR_1 -#define IBAD_ADR IBAD_ADR_1 - - -/*** IBFD - IIC Frequency Divider Register; 0x000000E1 ***/ -typedef union { - byte Byte; - struct { - byte IBC0 :1; /* I-Bus Clock Rate 0 */ - byte IBC1 :1; /* I-Bus Clock Rate 1 */ - byte IBC2 :1; /* I-Bus Clock Rate 2 */ - byte IBC3 :1; /* I-Bus Clock Rate 3 */ - byte IBC4 :1; /* I-Bus Clock Rate 4 */ - byte IBC5 :1; /* I-Bus Clock Rate 5 */ - byte IBC6 :1; /* I-Bus Clock Rate 6 */ - byte IBC7 :1; /* I-Bus Clock Rate 7 */ - } Bits; - struct { - byte grpIBC :8; - } MergedBits; -} IBFDSTR; -extern volatile IBFDSTR _IBFD @(REG_BASE + 0x000000E1); -#define IBFD _IBFD.Byte -#define IBFD_IBC0 _IBFD.Bits.IBC0 -#define IBFD_IBC1 _IBFD.Bits.IBC1 -#define IBFD_IBC2 _IBFD.Bits.IBC2 -#define IBFD_IBC3 _IBFD.Bits.IBC3 -#define IBFD_IBC4 _IBFD.Bits.IBC4 -#define IBFD_IBC5 _IBFD.Bits.IBC5 -#define IBFD_IBC6 _IBFD.Bits.IBC6 -#define IBFD_IBC7 _IBFD.Bits.IBC7 -#define IBFD_IBC _IBFD.MergedBits.grpIBC - - -/*** IBCR - IIC Control Register; 0x000000E2 ***/ -typedef union { - byte Byte; - struct { - byte IBSWAI :1; /* I-Bus Interface Stop in WAIT mode */ - byte :1; - byte RSTA :1; /* Repeat Start */ - byte TXAK :1; /* Transmit Acknowledge enable */ - byte TX_RX :1; /* Transmit/Receive mode select bit */ - byte MS_SL :1; /* Master/Slave mode select bit */ - byte IBIE :1; /* I-Bus Interrupt Enable */ - byte IBEN :1; /* I-Bus Enable */ - } Bits; -} IBCRSTR; -extern volatile IBCRSTR _IBCR @(REG_BASE + 0x000000E2); -#define IBCR _IBCR.Byte -#define IBCR_IBSWAI _IBCR.Bits.IBSWAI -#define IBCR_RSTA _IBCR.Bits.RSTA -#define IBCR_TXAK _IBCR.Bits.TXAK -#define IBCR_TX_RX _IBCR.Bits.TX_RX -#define IBCR_MS_SL _IBCR.Bits.MS_SL -#define IBCR_IBIE _IBCR.Bits.IBIE -#define IBCR_IBEN _IBCR.Bits.IBEN - - -/*** IBSR - IIC Status Register; 0x000000E3 ***/ -typedef union { - byte Byte; - struct { - byte RXAK :1; /* Received Acknowledge */ - byte IBIF :1; /* I-Bus Interrupt */ - byte SRW :1; /* Slave Read/Write */ - byte :1; - byte IBAL :1; /* Arbitration Lost */ - byte IBB :1; /* Bus busy bit */ - byte IAAS :1; /* Addressed as a slave bit */ - byte TCF :1; /* Data transferring bit */ - } Bits; -} IBSRSTR; -extern volatile IBSRSTR _IBSR @(REG_BASE + 0x000000E3); -#define IBSR _IBSR.Byte -#define IBSR_RXAK _IBSR.Bits.RXAK -#define IBSR_IBIF _IBSR.Bits.IBIF -#define IBSR_SRW _IBSR.Bits.SRW -#define IBSR_IBAL _IBSR.Bits.IBAL -#define IBSR_IBB _IBSR.Bits.IBB -#define IBSR_IAAS _IBSR.Bits.IAAS -#define IBSR_TCF _IBSR.Bits.TCF - - -/*** IBDR - IIC Data I/O Register; 0x000000E4 ***/ -typedef union { - byte Byte; - struct { - byte D0 :1; /* IIC Data Bit 0 */ - byte D1 :1; /* IIC Data Bit 1 */ - byte D2 :1; /* IIC Data Bit 2 */ - byte D3 :1; /* IIC Data Bit 3 */ - byte D4 :1; /* IIC Data Bit 4 */ - byte D5 :1; /* IIC Data Bit 5 */ - byte D6 :1; /* IIC Data Bit 6 */ - byte D7 :1; /* IIC Data Bit 7 */ - } Bits; - struct { - byte grpD :8; - } MergedBits; -} IBDRSTR; -extern volatile IBDRSTR _IBDR @(REG_BASE + 0x000000E4); -#define IBDR _IBDR.Byte -#define IBDR_D0 _IBDR.Bits.D0 -#define IBDR_D1 _IBDR.Bits.D1 -#define IBDR_D2 _IBDR.Bits.D2 -#define IBDR_D3 _IBDR.Bits.D3 -#define IBDR_D4 _IBDR.Bits.D4 -#define IBDR_D5 _IBDR.Bits.D5 -#define IBDR_D6 _IBDR.Bits.D6 -#define IBDR_D7 _IBDR.Bits.D7 -#define IBDR_D _IBDR.MergedBits.grpD - - -/*** DLCBCR1 - BDLC Control Register 1; 0x000000E8 ***/ -typedef union { - byte Byte; - struct { - byte WCM :1; /* Wait Clock Mode */ - byte IE :1; /* Interrupt Enable */ - byte :1; - byte :1; - byte :1; - byte :1; - byte CLKS :1; /* Clock Select */ - byte IMSG :1; /* Ignore Message */ - } Bits; -} DLCBCR1STR; -extern volatile DLCBCR1STR _DLCBCR1 @(REG_BASE + 0x000000E8); -#define DLCBCR1 _DLCBCR1.Byte -#define DLCBCR1_WCM _DLCBCR1.Bits.WCM -#define DLCBCR1_IE _DLCBCR1.Bits.IE -#define DLCBCR1_CLKS _DLCBCR1.Bits.CLKS -#define DLCBCR1_IMSG _DLCBCR1.Bits.IMSG - - -/*** DLCBSVR - BDLC State Vector Register; 0x000000E9 ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte :1; - byte I0 :1; /* Interrupt State Vector Bit 0 */ - byte I1 :1; /* Interrupt State Vector Bit 1 */ - byte I2 :1; /* Interrupt State Vector Bit 2 */ - byte I3 :1; /* Interrupt State Vector Bit 3 */ - byte :1; - byte :1; - } Bits; - struct { - byte :1; - byte :1; - byte grpI :4; - byte :1; - byte :1; - } MergedBits; -} DLCBSVRSTR; -extern volatile DLCBSVRSTR _DLCBSVR @(REG_BASE + 0x000000E9); -#define DLCBSVR _DLCBSVR.Byte -#define DLCBSVR_I0 _DLCBSVR.Bits.I0 -#define DLCBSVR_I1 _DLCBSVR.Bits.I1 -#define DLCBSVR_I2 _DLCBSVR.Bits.I2 -#define DLCBSVR_I3 _DLCBSVR.Bits.I3 -#define DLCBSVR_I _DLCBSVR.MergedBits.grpI - - -/*** DLCBCR2 - BDLC Control Register 2; 0x000000EA ***/ -typedef union { - byte Byte; - struct { - byte TMIFR0 :1; /* Transmit In-Frame Response Control 0 */ - byte TMIFR1 :1; /* Transmit In-Frame Response Control 1 */ - byte TSIFR :1; /* Transmit In-Frame Response Control 2 */ - byte TEOD :1; /* Transmit End of Data */ - byte NBFS :1; /* Normalization Bit Format Select */ - byte RX4XE :1; /* Receive 4X Enable */ - byte DLOOP :1; /* Digital Loopback Mode */ - byte SMRST :1; /* State Machine Reset */ - } Bits; - struct { - byte grpTMIFR :2; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} DLCBCR2STR; -extern volatile DLCBCR2STR _DLCBCR2 @(REG_BASE + 0x000000EA); -#define DLCBCR2 _DLCBCR2.Byte -#define DLCBCR2_TMIFR0 _DLCBCR2.Bits.TMIFR0 -#define DLCBCR2_TMIFR1 _DLCBCR2.Bits.TMIFR1 -#define DLCBCR2_TSIFR _DLCBCR2.Bits.TSIFR -#define DLCBCR2_TEOD _DLCBCR2.Bits.TEOD -#define DLCBCR2_NBFS _DLCBCR2.Bits.NBFS -#define DLCBCR2_RX4XE _DLCBCR2.Bits.RX4XE -#define DLCBCR2_DLOOP _DLCBCR2.Bits.DLOOP -#define DLCBCR2_SMRST _DLCBCR2.Bits.SMRST -#define DLCBCR2_TMIFR _DLCBCR2.MergedBits.grpTMIFR - - -/*** DLCBDR - BDLC Data Register; 0x000000EB ***/ -typedef union { - byte Byte; - struct { - byte D0 :1; /* Receive/Transmit Data Bit 0 */ - byte D1 :1; /* Receive/Transmit Data Bit 1 */ - byte D2 :1; /* Receive/Transmit Data Bit 2 */ - byte D3 :1; /* Receive/Transmit Data Bit 3 */ - byte D4 :1; /* Receive/Transmit Data Bit 4 */ - byte D5 :1; /* Receive/Transmit Data Bit 5 */ - byte D6 :1; /* Receive/Transmit Data Bit 6 */ - byte D7 :1; /* Receive/Transmit Data Bit 7 */ - } Bits; - struct { - byte grpD :8; - } MergedBits; -} DLCBDRSTR; -extern volatile DLCBDRSTR _DLCBDR @(REG_BASE + 0x000000EB); -#define DLCBDR _DLCBDR.Byte -#define DLCBDR_D0 _DLCBDR.Bits.D0 -#define DLCBDR_D1 _DLCBDR.Bits.D1 -#define DLCBDR_D2 _DLCBDR.Bits.D2 -#define DLCBDR_D3 _DLCBDR.Bits.D3 -#define DLCBDR_D4 _DLCBDR.Bits.D4 -#define DLCBDR_D5 _DLCBDR.Bits.D5 -#define DLCBDR_D6 _DLCBDR.Bits.D6 -#define DLCBDR_D7 _DLCBDR.Bits.D7 -#define DLCBDR_D _DLCBDR.MergedBits.grpD - - -/*** DLCBARD - BDLC Analog Round Trip Delay Register; 0x000000EC ***/ -typedef union { - byte Byte; - struct { - byte BO0 :1; /* BDLC Analog Roundtrip Delay Offset Field 0 */ - byte BO1 :1; /* BDLC Analog Roundtrip Delay Offset Field 1 */ - byte BO2 :1; /* BDLC Analog Roundtrip Delay Offset Field 2 */ - byte BO3 :1; /* BDLC Analog Roundtrip Delay Offset Field 3 */ - byte :1; - byte :1; - byte RXPOL :1; /* Receive Pin Polarity */ - byte :1; - } Bits; - struct { - byte grpBO :4; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} DLCBARDSTR; -extern volatile DLCBARDSTR _DLCBARD @(REG_BASE + 0x000000EC); -#define DLCBARD _DLCBARD.Byte -#define DLCBARD_BO0 _DLCBARD.Bits.BO0 -#define DLCBARD_BO1 _DLCBARD.Bits.BO1 -#define DLCBARD_BO2 _DLCBARD.Bits.BO2 -#define DLCBARD_BO3 _DLCBARD.Bits.BO3 -#define DLCBARD_RXPOL _DLCBARD.Bits.RXPOL -#define DLCBARD_BO _DLCBARD.MergedBits.grpBO - - -/*** DLCBRSR - BDLC Rate Select Register; 0x000000ED ***/ -typedef union { - byte Byte; - struct { - byte R0 :1; /* Rate Select 0 */ - byte R1 :1; /* Rate Select 1 */ - byte R2 :1; /* Rate Select 2 */ - byte R3 :1; /* Rate Select 3 */ - byte R4 :1; /* Rate Select 4 */ - byte R5 :1; /* Rate Select 5 */ - byte :1; - byte :1; - } Bits; - struct { - byte grpR :6; - byte :1; - byte :1; - } MergedBits; -} DLCBRSRSTR; -extern volatile DLCBRSRSTR _DLCBRSR @(REG_BASE + 0x000000ED); -#define DLCBRSR _DLCBRSR.Byte -#define DLCBRSR_R0 _DLCBRSR.Bits.R0 -#define DLCBRSR_R1 _DLCBRSR.Bits.R1 -#define DLCBRSR_R2 _DLCBRSR.Bits.R2 -#define DLCBRSR_R3 _DLCBRSR.Bits.R3 -#define DLCBRSR_R4 _DLCBRSR.Bits.R4 -#define DLCBRSR_R5 _DLCBRSR.Bits.R5 -#define DLCBRSR_R _DLCBRSR.MergedBits.grpR - - -/*** DLCSCR - BDLC Control Register; 0x000000EE ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte BDLCE :1; /* BDLC Enable */ - byte :1; - byte :1; - byte :1; - } Bits; -} DLCSCRSTR; -extern volatile DLCSCRSTR _DLCSCR @(REG_BASE + 0x000000EE); -#define DLCSCR _DLCSCR.Byte -#define DLCSCR_BDLCE _DLCSCR.Bits.BDLCE - - -/*** SPI1CR1 - SPI 1 Control Register; 0x000000F0 ***/ -typedef union { - byte Byte; - struct { - byte LSBFE :1; /* SPI 1 LSB-First Enable */ - byte SSOE :1; /* Slave Select Output Enable */ - byte CPHA :1; /* SPI 1 Clock Phase Bit */ - byte CPOL :1; /* SPI 1 Clock Polarity Bit */ - byte MSTR :1; /* SPI 1 Master/Slave Mode Select Bit */ - byte SPTIE :1; /* SPI 1 Transmit Interrupt Enable */ - byte SPE :1; /* SPI 1 System Enable Bit */ - byte SPIE :1; /* SPI 1 Interrupt Enable Bit */ - } Bits; -} SPI1CR1STR; -extern volatile SPI1CR1STR _SPI1CR1 @(REG_BASE + 0x000000F0); -#define SPI1CR1 _SPI1CR1.Byte -#define SPI1CR1_LSBFE _SPI1CR1.Bits.LSBFE -#define SPI1CR1_SSOE _SPI1CR1.Bits.SSOE -#define SPI1CR1_CPHA _SPI1CR1.Bits.CPHA -#define SPI1CR1_CPOL _SPI1CR1.Bits.CPOL -#define SPI1CR1_MSTR _SPI1CR1.Bits.MSTR -#define SPI1CR1_SPTIE _SPI1CR1.Bits.SPTIE -#define SPI1CR1_SPE _SPI1CR1.Bits.SPE -#define SPI1CR1_SPIE _SPI1CR1.Bits.SPIE - - -/*** SPI1CR2 - SPI 1 Control Register 2; 0x000000F1 ***/ -typedef union { - byte Byte; - struct { - byte SPC0 :1; /* Serial Pin Control Bit 0 */ - byte SPISWAI :1; /* SPI 1 Stop in Wait Mode Bit */ - byte :1; - byte BIDIROE :1; /* Output enable in the Bidirectional mode of operation */ - byte MODFEN :1; /* Mode Fault Enable Bit */ - byte :1; - byte :1; - byte :1; - } Bits; -} SPI1CR2STR; -extern volatile SPI1CR2STR _SPI1CR2 @(REG_BASE + 0x000000F1); -#define SPI1CR2 _SPI1CR2.Byte -#define SPI1CR2_SPC0 _SPI1CR2.Bits.SPC0 -#define SPI1CR2_SPISWAI _SPI1CR2.Bits.SPISWAI -#define SPI1CR2_BIDIROE _SPI1CR2.Bits.BIDIROE -#define SPI1CR2_MODFEN _SPI1CR2.Bits.MODFEN - - -/*** SPI1BR - SPI 1 Baud Rate Register; 0x000000F2 ***/ -typedef union { - byte Byte; - struct { - byte SPR0 :1; /* SPI 1 Baud Rate Selection Bit 0 */ - byte SPR1 :1; /* SPI 1 Baud Rate Selection Bit 1 */ - byte SPR2 :1; /* SPI 1 Baud Rate Selection Bit 2 */ - byte :1; - byte SPPR0 :1; /* SPI 1 Baud Rate Preselection Bits 0 */ - byte SPPR1 :1; /* SPI 1 Baud Rate Preselection Bits 1 */ - byte SPPR2 :1; /* SPI 1 Baud Rate Preselection Bits 2 */ - byte :1; - } Bits; - struct { - byte grpSPR :3; - byte :1; - byte grpSPPR :3; - byte :1; - } MergedBits; -} SPI1BRSTR; -extern volatile SPI1BRSTR _SPI1BR @(REG_BASE + 0x000000F2); -#define SPI1BR _SPI1BR.Byte -#define SPI1BR_SPR0 _SPI1BR.Bits.SPR0 -#define SPI1BR_SPR1 _SPI1BR.Bits.SPR1 -#define SPI1BR_SPR2 _SPI1BR.Bits.SPR2 -#define SPI1BR_SPPR0 _SPI1BR.Bits.SPPR0 -#define SPI1BR_SPPR1 _SPI1BR.Bits.SPPR1 -#define SPI1BR_SPPR2 _SPI1BR.Bits.SPPR2 -#define SPI1BR_SPR _SPI1BR.MergedBits.grpSPR -#define SPI1BR_SPPR _SPI1BR.MergedBits.grpSPPR - - -/*** SPI1SR - SPI 1 Status Register; 0x000000F3 ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte MODF :1; /* Mode Fault Flag */ - byte SPTEF :1; /* SPI 1 Transmit Empty Interrupt Flag */ - byte :1; - byte SPIF :1; /* SPIF Receive Interrupt Flag */ - } Bits; -} SPI1SRSTR; -extern volatile SPI1SRSTR _SPI1SR @(REG_BASE + 0x000000F3); -#define SPI1SR _SPI1SR.Byte -#define SPI1SR_MODF _SPI1SR.Bits.MODF -#define SPI1SR_SPTEF _SPI1SR.Bits.SPTEF -#define SPI1SR_SPIF _SPI1SR.Bits.SPIF - - -/*** SPI1DR - SPI 1 Data Register; 0x000000F5 ***/ -typedef union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; -} SPI1DRSTR; -extern volatile SPI1DRSTR _SPI1DR @(REG_BASE + 0x000000F5); -#define SPI1DR _SPI1DR.Byte -#define SPI1DR_BIT _SPI1DR.MergedBits.grpBIT - - -/*** SPI2CR1 - SPI 2 Control Register; 0x000000F8 ***/ -typedef union { - byte Byte; - struct { - byte LSBFE :1; /* SPI 2 LSB-First Enable */ - byte SSOE :1; /* Slave Select Output Enable */ - byte CPHA :1; /* SPI 2 Clock Phase Bit */ - byte CPOL :1; /* SPI 2 Clock Polarity Bit */ - byte MSTR :1; /* SPI 2 Master/Slave Mode Select Bit */ - byte SPTIE :1; /* SPI 2 Transmit Interrupt Enable */ - byte SPE :1; /* SPI 2 System Enable Bit */ - byte SPIE :1; /* SPI 2 Interrupt Enable Bit */ - } Bits; -} SPI2CR1STR; -extern volatile SPI2CR1STR _SPI2CR1 @(REG_BASE + 0x000000F8); -#define SPI2CR1 _SPI2CR1.Byte -#define SPI2CR1_LSBFE _SPI2CR1.Bits.LSBFE -#define SPI2CR1_SSOE _SPI2CR1.Bits.SSOE -#define SPI2CR1_CPHA _SPI2CR1.Bits.CPHA -#define SPI2CR1_CPOL _SPI2CR1.Bits.CPOL -#define SPI2CR1_MSTR _SPI2CR1.Bits.MSTR -#define SPI2CR1_SPTIE _SPI2CR1.Bits.SPTIE -#define SPI2CR1_SPE _SPI2CR1.Bits.SPE -#define SPI2CR1_SPIE _SPI2CR1.Bits.SPIE - - -/*** SPI2CR2 - SPI 2 Control Register 2; 0x000000F9 ***/ -typedef union { - byte Byte; - struct { - byte SPC0 :1; /* Serial Pin Control Bit 0 */ - byte SPISWAI :1; /* SPI 2 Stop in Wait Mode Bit */ - byte :1; - byte BIDIROE :1; /* Output enable in the Bidirectional mode of operation */ - byte MODFEN :1; /* Mode Fault Enable Bit */ - byte :1; - byte :1; - byte :1; - } Bits; -} SPI2CR2STR; -extern volatile SPI2CR2STR _SPI2CR2 @(REG_BASE + 0x000000F9); -#define SPI2CR2 _SPI2CR2.Byte -#define SPI2CR2_SPC0 _SPI2CR2.Bits.SPC0 -#define SPI2CR2_SPISWAI _SPI2CR2.Bits.SPISWAI -#define SPI2CR2_BIDIROE _SPI2CR2.Bits.BIDIROE -#define SPI2CR2_MODFEN _SPI2CR2.Bits.MODFEN - - -/*** SPI2BR - SPI 2 Baud Rate Register; 0x000000FA ***/ -typedef union { - byte Byte; - struct { - byte SPR0 :1; /* SPI 2 Baud Rate Selection Bit 0 */ - byte SPR1 :1; /* SPI 2 Baud Rate Selection Bit 1 */ - byte SPR2 :1; /* SPI 2 Baud Rate Selection Bit 2 */ - byte :1; - byte SPPR0 :1; /* SPI 2 Baud Rate Preselection Bits 0 */ - byte SPPR1 :1; /* SPI 2 Baud Rate Preselection Bits 1 */ - byte SPPR2 :1; /* SPI 2 Baud Rate Preselection Bits 2 */ - byte :1; - } Bits; - struct { - byte grpSPR :3; - byte :1; - byte grpSPPR :3; - byte :1; - } MergedBits; -} SPI2BRSTR; -extern volatile SPI2BRSTR _SPI2BR @(REG_BASE + 0x000000FA); -#define SPI2BR _SPI2BR.Byte -#define SPI2BR_SPR0 _SPI2BR.Bits.SPR0 -#define SPI2BR_SPR1 _SPI2BR.Bits.SPR1 -#define SPI2BR_SPR2 _SPI2BR.Bits.SPR2 -#define SPI2BR_SPPR0 _SPI2BR.Bits.SPPR0 -#define SPI2BR_SPPR1 _SPI2BR.Bits.SPPR1 -#define SPI2BR_SPPR2 _SPI2BR.Bits.SPPR2 -#define SPI2BR_SPR _SPI2BR.MergedBits.grpSPR -#define SPI2BR_SPPR _SPI2BR.MergedBits.grpSPPR - - -/*** SPI2SR - SPI 2 Status Register; 0x000000FB ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte MODF :1; /* Mode Fault Flag */ - byte SPTEF :1; /* SPI 2 Transmit Empty Interrupt Flag */ - byte :1; - byte SPIF :1; /* SPIF Receive Interrupt Flag */ - } Bits; -} SPI2SRSTR; -extern volatile SPI2SRSTR _SPI2SR @(REG_BASE + 0x000000FB); -#define SPI2SR _SPI2SR.Byte -#define SPI2SR_MODF _SPI2SR.Bits.MODF -#define SPI2SR_SPTEF _SPI2SR.Bits.SPTEF -#define SPI2SR_SPIF _SPI2SR.Bits.SPIF - - -/*** SPI2DR - SPI 2 Data Register; 0x000000FD ***/ -typedef union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; -} SPI2DRSTR; -extern volatile SPI2DRSTR _SPI2DR @(REG_BASE + 0x000000FD); -#define SPI2DR _SPI2DR.Byte -#define SPI2DR_BIT _SPI2DR.MergedBits.grpBIT - - -/*** FCLKDIV - Flash Clock Divider Register; 0x00000100 ***/ -typedef union { - byte Byte; - struct { - byte FDIV0 :1; /* Flash Clock Divider Bit 0 */ - byte FDIV1 :1; /* Flash Clock Divider Bit 1 */ - byte FDIV2 :1; /* Flash Clock Divider Bit 2 */ - byte FDIV3 :1; /* Flash Clock Divider Bit 3 */ - byte FDIV4 :1; /* Flash Clock Divider Bit 4 */ - byte FDIV5 :1; /* Flash Clock Divider Bit 5 */ - byte PRDIV8 :1; /* Enable Prescaler by 8 */ - byte FDIVLD :1; /* Flash Clock Divider Loaded */ - } Bits; - struct { - byte grpFDIV :6; - byte grpPRDIV_8 :1; - byte :1; - } MergedBits; -} FCLKDIVSTR; -extern volatile FCLKDIVSTR _FCLKDIV @(REG_BASE + 0x00000100); -#define FCLKDIV _FCLKDIV.Byte -#define FCLKDIV_FDIV0 _FCLKDIV.Bits.FDIV0 -#define FCLKDIV_FDIV1 _FCLKDIV.Bits.FDIV1 -#define FCLKDIV_FDIV2 _FCLKDIV.Bits.FDIV2 -#define FCLKDIV_FDIV3 _FCLKDIV.Bits.FDIV3 -#define FCLKDIV_FDIV4 _FCLKDIV.Bits.FDIV4 -#define FCLKDIV_FDIV5 _FCLKDIV.Bits.FDIV5 -#define FCLKDIV_PRDIV8 _FCLKDIV.Bits.PRDIV8 -#define FCLKDIV_FDIVLD _FCLKDIV.Bits.FDIVLD -#define FCLKDIV_FDIV _FCLKDIV.MergedBits.grpFDIV - - -/*** FSEC - Flash Security Register; 0x00000101 ***/ -typedef union { - byte Byte; - struct { - byte SEC0 :1; /* Memory security bit 0 */ - byte SEC1 :1; /* Memory security bit 1 */ - byte NV2 :1; /* Non Volatile flag bit 2 */ - byte NV3 :1; /* Non Volatile flag bit 3 */ - byte NV4 :1; /* Non Volatile flag bit 4 */ - byte NV5 :1; /* Non Volatile flag bit 5 */ - byte NV6 :1; /* Non Volatile flag bit 6 */ - byte KEYEN :1; /* Enable backdoor key to security */ - } Bits; - struct { - byte grpSEC :2; - byte grpNV_2 :5; - byte :1; - } MergedBits; -} FSECSTR; -extern volatile FSECSTR _FSEC @(REG_BASE + 0x00000101); -#define FSEC _FSEC.Byte -#define FSEC_SEC0 _FSEC.Bits.SEC0 -#define FSEC_SEC1 _FSEC.Bits.SEC1 -#define FSEC_NV2 _FSEC.Bits.NV2 -#define FSEC_NV3 _FSEC.Bits.NV3 -#define FSEC_NV4 _FSEC.Bits.NV4 -#define FSEC_NV5 _FSEC.Bits.NV5 -#define FSEC_NV6 _FSEC.Bits.NV6 -#define FSEC_KEYEN _FSEC.Bits.KEYEN -#define FSEC_SEC _FSEC.MergedBits.grpSEC -#define FSEC_NV_2 _FSEC.MergedBits.grpNV_2 -#define FSEC_NV FSEC_NV_2 - - -/*** FCNFG - Flash Configuration Register; 0x00000103 ***/ -typedef union { - byte Byte; - struct { - byte BKSEL0 :1; /* Register bank select 0 */ - byte BKSEL1 :1; /* Register bank select 1 */ - byte :1; - byte :1; - byte :1; - byte KEYACC :1; /* Enable Security Key Writing */ - byte CCIE :1; /* Command Complete Interrupt Enable */ - byte CBEIE :1; /* Command Buffers Empty Interrupt Enable */ - } Bits; - struct { - byte grpBKSEL :2; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} FCNFGSTR; -extern volatile FCNFGSTR _FCNFG @(REG_BASE + 0x00000103); -#define FCNFG _FCNFG.Byte -#define FCNFG_BKSEL0 _FCNFG.Bits.BKSEL0 -#define FCNFG_BKSEL1 _FCNFG.Bits.BKSEL1 -#define FCNFG_KEYACC _FCNFG.Bits.KEYACC -#define FCNFG_CCIE _FCNFG.Bits.CCIE -#define FCNFG_CBEIE _FCNFG.Bits.CBEIE -#define FCNFG_BKSEL _FCNFG.MergedBits.grpBKSEL - - -/*** FPROT - Flash Protection Register; 0x00000104 ***/ -typedef union { - byte Byte; - struct { - byte FPLS0 :1; /* Flash Protection Lower Address size 0 */ - byte FPLS1 :1; /* Flash Protection Lower Address size 1 */ - byte FPLDIS :1; /* Flash Protection Lower address range disable */ - byte FPHS0 :1; /* Flash Protection Higher address size 0 */ - byte FPHS1 :1; /* Flash Protection Higher address size 1 */ - byte FPHDIS :1; /* Flash Protection Higher address range disable */ - byte NV6 :1; /* Non Volatile Flag Bit */ - byte FPOPEN :1; /* Opens the flash block or subsections of it for program or erase */ - } Bits; - struct { - byte grpFPLS :2; - byte :1; - byte grpFPHS :2; - byte :1; - byte grpNV_6 :1; - byte :1; - } MergedBits; -} FPROTSTR; -extern volatile FPROTSTR _FPROT @(REG_BASE + 0x00000104); -#define FPROT _FPROT.Byte -#define FPROT_FPLS0 _FPROT.Bits.FPLS0 -#define FPROT_FPLS1 _FPROT.Bits.FPLS1 -#define FPROT_FPLDIS _FPROT.Bits.FPLDIS -#define FPROT_FPHS0 _FPROT.Bits.FPHS0 -#define FPROT_FPHS1 _FPROT.Bits.FPHS1 -#define FPROT_FPHDIS _FPROT.Bits.FPHDIS -#define FPROT_NV6 _FPROT.Bits.NV6 -#define FPROT_FPOPEN _FPROT.Bits.FPOPEN -#define FPROT_FPLS _FPROT.MergedBits.grpFPLS -#define FPROT_FPHS _FPROT.MergedBits.grpFPHS - - -/*** FSTAT - Flash Status Register; 0x00000105 ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte :1; - byte BLANK :1; /* Blank Verify Flag */ - byte :1; - byte ACCERR :1; /* Access error */ - byte PVIOL :1; /* Protection violation */ - byte CCIF :1; /* Command Complete Interrupt Flag */ - byte CBEIF :1; /* Command Buffers Empty Interrupt Flag */ - } Bits; -} FSTATSTR; -extern volatile FSTATSTR _FSTAT @(REG_BASE + 0x00000105); -#define FSTAT _FSTAT.Byte -#define FSTAT_BLANK _FSTAT.Bits.BLANK -#define FSTAT_ACCERR _FSTAT.Bits.ACCERR -#define FSTAT_PVIOL _FSTAT.Bits.PVIOL -#define FSTAT_CCIF _FSTAT.Bits.CCIF -#define FSTAT_CBEIF _FSTAT.Bits.CBEIF - - -/*** FCMD - Flash Command Buffer and Register; 0x00000106 ***/ -typedef union { - byte Byte; - struct { - byte CMDB0 :1; /* NVM User Mode Command Bit 0 */ - byte :1; - byte CMDB2 :1; /* NVM User Mode Command Bit 2 */ - byte :1; - byte :1; - byte CMDB5 :1; /* NVM User Mode Command Bit 5 */ - byte CMDB6 :1; /* NVM User Mode Command Bit 6 */ - byte :1; - } Bits; - struct { - byte grpCMDB :1; - byte :1; - byte grpCMDB_2 :1; - byte :1; - byte :1; - byte grpCMDB_5 :2; - byte :1; - } MergedBits; -} FCMDSTR; -extern volatile FCMDSTR _FCMD @(REG_BASE + 0x00000106); -#define FCMD _FCMD.Byte -#define FCMD_CMDB0 _FCMD.Bits.CMDB0 -#define FCMD_CMDB2 _FCMD.Bits.CMDB2 -#define FCMD_CMDB5 _FCMD.Bits.CMDB5 -#define FCMD_CMDB6 _FCMD.Bits.CMDB6 -#define FCMD_CMDB_5 _FCMD.MergedBits.grpCMDB_5 -#define FCMD_CMDB FCMD_CMDB_5 - - -/*** ECLKDIV - EEPROM Clock Divider Register; 0x00000110 ***/ -typedef union { - byte Byte; - struct { - byte EDIV0 :1; /* EEPROM Clock Divider 0 */ - byte EDIV1 :1; /* EEPROM Clock Divider 1 */ - byte EDIV2 :1; /* EEPROM Clock Divider 2 */ - byte EDIV3 :1; /* EEPROM Clock Divider 3 */ - byte EDIV4 :1; /* EEPROM Clock Divider 4 */ - byte EDIV5 :1; /* EEPROM Clock Divider 5 */ - byte PRDIV8 :1; /* Enable Prescaler by 8 */ - byte EDIVLD :1; /* EEPROM Clock Divider Loaded */ - } Bits; - struct { - byte grpEDIV :6; - byte grpPRDIV_8 :1; - byte :1; - } MergedBits; -} ECLKDIVSTR; -extern volatile ECLKDIVSTR _ECLKDIV @(REG_BASE + 0x00000110); -#define ECLKDIV _ECLKDIV.Byte -#define ECLKDIV_EDIV0 _ECLKDIV.Bits.EDIV0 -#define ECLKDIV_EDIV1 _ECLKDIV.Bits.EDIV1 -#define ECLKDIV_EDIV2 _ECLKDIV.Bits.EDIV2 -#define ECLKDIV_EDIV3 _ECLKDIV.Bits.EDIV3 -#define ECLKDIV_EDIV4 _ECLKDIV.Bits.EDIV4 -#define ECLKDIV_EDIV5 _ECLKDIV.Bits.EDIV5 -#define ECLKDIV_PRDIV8 _ECLKDIV.Bits.PRDIV8 -#define ECLKDIV_EDIVLD _ECLKDIV.Bits.EDIVLD -#define ECLKDIV_EDIV _ECLKDIV.MergedBits.grpEDIV - - -/*** ECNFG - EEPROM Configuration Register; 0x00000113 ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte CCIE :1; /* Command Complete Interrupt Enable */ - byte CBEIE :1; /* Command Buffers Empty Interrupt Enable */ - } Bits; -} ECNFGSTR; -extern volatile ECNFGSTR _ECNFG @(REG_BASE + 0x00000113); -#define ECNFG _ECNFG.Byte -#define ECNFG_CCIE _ECNFG.Bits.CCIE -#define ECNFG_CBEIE _ECNFG.Bits.CBEIE - - -/*** EPROT - EEPROM Protection Register; 0x00000114 ***/ -typedef union { - byte Byte; - struct { - byte EP0 :1; /* EEPROM Protection address size 0 */ - byte EP1 :1; /* EEPROM Protection address size 1 */ - byte EP2 :1; /* EEPROM Protection address size 2 */ - byte EPDIS :1; /* EEPROM Protection disable */ - byte :1; - byte :1; - byte :1; - byte EPOPEN :1; /* Opens the EEPROM block or a subsection of it for program or erase */ - } Bits; - struct { - byte grpEP :3; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} EPROTSTR; -extern volatile EPROTSTR _EPROT @(REG_BASE + 0x00000114); -#define EPROT _EPROT.Byte -#define EPROT_EP0 _EPROT.Bits.EP0 -#define EPROT_EP1 _EPROT.Bits.EP1 -#define EPROT_EP2 _EPROT.Bits.EP2 -#define EPROT_EPDIS _EPROT.Bits.EPDIS -#define EPROT_EPOPEN _EPROT.Bits.EPOPEN -#define EPROT_EP _EPROT.MergedBits.grpEP - - -/*** ESTAT - EEPROM Status Register; 0x00000115 ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte :1; - byte BLANK :1; /* Blank Verify Flag */ - byte :1; - byte ACCERR :1; /* Access error */ - byte PVIOL :1; /* Protection violation */ - byte CCIF :1; /* Command Complete Interrupt Flag */ - byte CBEIF :1; /* Command Buffer Empty Interrupt Flag */ - } Bits; -} ESTATSTR; -extern volatile ESTATSTR _ESTAT @(REG_BASE + 0x00000115); -#define ESTAT _ESTAT.Byte -#define ESTAT_BLANK _ESTAT.Bits.BLANK -#define ESTAT_ACCERR _ESTAT.Bits.ACCERR -#define ESTAT_PVIOL _ESTAT.Bits.PVIOL -#define ESTAT_CCIF _ESTAT.Bits.CCIF -#define ESTAT_CBEIF _ESTAT.Bits.CBEIF - - -/*** ECMD - EEPROM Command Buffer and Register; 0x00000116 ***/ -typedef union { - byte Byte; - struct { - byte CMDB0 :1; /* EEPROM User Mode Command 0 */ - byte :1; - byte CMDB2 :1; /* EEPROM User Mode Command 2 */ - byte :1; - byte :1; - byte CMDB5 :1; /* EEPROM User Mode Command 5 */ - byte CMDB6 :1; /* EEPROM User Mode Command 6 */ - byte :1; - } Bits; - struct { - byte grpCMDB :1; - byte :1; - byte grpCMDB_2 :1; - byte :1; - byte :1; - byte grpCMDB_5 :2; - byte :1; - } MergedBits; -} ECMDSTR; -extern volatile ECMDSTR _ECMD @(REG_BASE + 0x00000116); -#define ECMD _ECMD.Byte -#define ECMD_CMDB0 _ECMD.Bits.CMDB0 -#define ECMD_CMDB2 _ECMD.Bits.CMDB2 -#define ECMD_CMDB5 _ECMD.Bits.CMDB5 -#define ECMD_CMDB6 _ECMD.Bits.CMDB6 -#define ECMD_CMDB_5 _ECMD.MergedBits.grpCMDB_5 -#define ECMD_CMDB ECMD_CMDB_5 - - -/*** ATD1STAT0 - ATD 1 Status Register 0; 0x00000126 ***/ -typedef union { - byte Byte; - struct { - byte CC0 :1; /* Conversion Counter 0 */ - byte CC1 :1; /* Conversion Counter 1 */ - byte CC2 :1; /* Conversion Counter 2 */ - byte :1; - byte FIFOR :1; /* FIFO Over Run Flag */ - byte ETORF :1; /* External Trigger Overrun Flag */ - byte :1; - byte SCF :1; /* Sequence Complete Flag */ - } Bits; - struct { - byte grpCC :3; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} ATD1STAT0STR; -extern volatile ATD1STAT0STR _ATD1STAT0 @(REG_BASE + 0x00000126); -#define ATD1STAT0 _ATD1STAT0.Byte -#define ATD1STAT0_CC0 _ATD1STAT0.Bits.CC0 -#define ATD1STAT0_CC1 _ATD1STAT0.Bits.CC1 -#define ATD1STAT0_CC2 _ATD1STAT0.Bits.CC2 -#define ATD1STAT0_FIFOR _ATD1STAT0.Bits.FIFOR -#define ATD1STAT0_ETORF _ATD1STAT0.Bits.ETORF -#define ATD1STAT0_SCF _ATD1STAT0.Bits.SCF -#define ATD1STAT0_CC _ATD1STAT0.MergedBits.grpCC - - -/*** ATD1STAT1 - ATD 1 Status Register 1; 0x0000012B ***/ -typedef union { - byte Byte; - struct { - byte CCF0 :1; /* Conversion Complete Flag 0 */ - byte CCF1 :1; /* Conversion Complete Flag 1 */ - byte CCF2 :1; /* Conversion Complete Flag 2 */ - byte CCF3 :1; /* Conversion Complete Flag 3 */ - byte CCF4 :1; /* Conversion Complete Flag 4 */ - byte CCF5 :1; /* Conversion Complete Flag 5 */ - byte CCF6 :1; /* Conversion Complete Flag 6 */ - byte CCF7 :1; /* Conversion Complete Flag 7 */ - } Bits; - struct { - byte grpCCF :8; - } MergedBits; -} ATD1STAT1STR; -extern volatile ATD1STAT1STR _ATD1STAT1 @(REG_BASE + 0x0000012B); -#define ATD1STAT1 _ATD1STAT1.Byte -#define ATD1STAT1_CCF0 _ATD1STAT1.Bits.CCF0 -#define ATD1STAT1_CCF1 _ATD1STAT1.Bits.CCF1 -#define ATD1STAT1_CCF2 _ATD1STAT1.Bits.CCF2 -#define ATD1STAT1_CCF3 _ATD1STAT1.Bits.CCF3 -#define ATD1STAT1_CCF4 _ATD1STAT1.Bits.CCF4 -#define ATD1STAT1_CCF5 _ATD1STAT1.Bits.CCF5 -#define ATD1STAT1_CCF6 _ATD1STAT1.Bits.CCF6 -#define ATD1STAT1_CCF7 _ATD1STAT1.Bits.CCF7 -#define ATD1STAT1_CCF _ATD1STAT1.MergedBits.grpCCF - - -/*** ATD1DIEN - ATD 1 Input Enable Mask Register; 0x0000012D ***/ -typedef union { - byte Byte; - struct { - byte BIT0 :1; /* Disable/Enable Digital Input Buffer Bit 0 */ - byte BIT1 :1; /* Disable/Enable Digital Input Buffer Bit 1 */ - byte BIT2 :1; /* Disable/Enable Digital Input Buffer Bit 2 */ - byte BIT3 :1; /* Disable/Enable Digital Input Buffer Bit 3 */ - byte BIT4 :1; /* Disable/Enable Digital Input Buffer Bit 4 */ - byte BIT5 :1; /* Disable/Enable Digital Input Buffer Bit 5 */ - byte BIT6 :1; /* Disable/Enable Digital Input Buffer Bit 6 */ - byte BIT7 :1; /* Disable/Enable Digital Input Buffer Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; -} ATD1DIENSTR; -extern volatile ATD1DIENSTR _ATD1DIEN @(REG_BASE + 0x0000012D); -#define ATD1DIEN _ATD1DIEN.Byte -#define ATD1DIEN_BIT0 _ATD1DIEN.Bits.BIT0 -#define ATD1DIEN_BIT1 _ATD1DIEN.Bits.BIT1 -#define ATD1DIEN_BIT2 _ATD1DIEN.Bits.BIT2 -#define ATD1DIEN_BIT3 _ATD1DIEN.Bits.BIT3 -#define ATD1DIEN_BIT4 _ATD1DIEN.Bits.BIT4 -#define ATD1DIEN_BIT5 _ATD1DIEN.Bits.BIT5 -#define ATD1DIEN_BIT6 _ATD1DIEN.Bits.BIT6 -#define ATD1DIEN_BIT7 _ATD1DIEN.Bits.BIT7 -#define ATD1DIEN_BIT _ATD1DIEN.MergedBits.grpBIT - - -/*** PORTAD1 - Port AD1 Register; 0x0000012F ***/ -typedef union { - byte Byte; - struct { - byte BIT0 :1; /* AN0 */ - byte BIT1 :1; /* AN1 */ - byte BIT2 :1; /* AN2 */ - byte BIT3 :1; /* AN3 */ - byte BIT4 :1; /* AN4 */ - byte BIT5 :1; /* AN5 */ - byte BIT6 :1; /* AN6 */ - byte BIT7 :1; /* AN7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; -} PORTAD1STR; -extern volatile PORTAD1STR _PORTAD1 @(REG_BASE + 0x0000012F); -#define PORTAD1 _PORTAD1.Byte -#define PORTAD1_BIT0 _PORTAD1.Bits.BIT0 -#define PORTAD1_BIT1 _PORTAD1.Bits.BIT1 -#define PORTAD1_BIT2 _PORTAD1.Bits.BIT2 -#define PORTAD1_BIT3 _PORTAD1.Bits.BIT3 -#define PORTAD1_BIT4 _PORTAD1.Bits.BIT4 -#define PORTAD1_BIT5 _PORTAD1.Bits.BIT5 -#define PORTAD1_BIT6 _PORTAD1.Bits.BIT6 -#define PORTAD1_BIT7 _PORTAD1.Bits.BIT7 -#define PORTAD1_BIT _PORTAD1.MergedBits.grpBIT - - -/*** CAN0CTL0 - MSCAN 0 Control 0 Register; 0x00000140 ***/ -typedef union { - byte Byte; - struct { - byte INITRQ :1; /* Initialization Mode Request */ - byte SLPRQ :1; /* Sleep Mode Request */ - byte WUPE :1; /* Wake-Up Enable */ - byte TIME :1; /* Timer Enable */ - byte SYNCH :1; /* Synchronized Status */ - byte CSWAI :1; /* CAN Stops in Wait Mode */ - byte RXACT :1; /* Receiver Active Status */ - byte RXFRM :1; /* Received Frame Flag */ - } Bits; -} CAN0CTL0STR; -extern volatile CAN0CTL0STR _CAN0CTL0 @(REG_BASE + 0x00000140); -#define CAN0CTL0 _CAN0CTL0.Byte -#define CAN0CTL0_INITRQ _CAN0CTL0.Bits.INITRQ -#define CAN0CTL0_SLPRQ _CAN0CTL0.Bits.SLPRQ -#define CAN0CTL0_WUPE _CAN0CTL0.Bits.WUPE -#define CAN0CTL0_TIME _CAN0CTL0.Bits.TIME -#define CAN0CTL0_SYNCH _CAN0CTL0.Bits.SYNCH -#define CAN0CTL0_CSWAI _CAN0CTL0.Bits.CSWAI -#define CAN0CTL0_RXACT _CAN0CTL0.Bits.RXACT -#define CAN0CTL0_RXFRM _CAN0CTL0.Bits.RXFRM - - -/*** CAN0CTL1 - MSCAN 0 Control 1 Register; 0x00000141 ***/ -typedef union { - byte Byte; - struct { - byte INITAK :1; /* Initialization Mode Acknowledge */ - byte SLPAK :1; /* Sleep Mode Acknowledge */ - byte WUPM :1; /* Wake-Up Mode */ - byte :1; - byte LISTEN :1; /* Listen Only Mode */ - byte LOOPB :1; /* Loop Back Self Test Mode */ - byte CLKSRC :1; /* MSCAN 0 Clock Source */ - byte CANE :1; /* MSCAN 0 Enable */ - } Bits; -} CAN0CTL1STR; -extern volatile CAN0CTL1STR _CAN0CTL1 @(REG_BASE + 0x00000141); -#define CAN0CTL1 _CAN0CTL1.Byte -#define CAN0CTL1_INITAK _CAN0CTL1.Bits.INITAK -#define CAN0CTL1_SLPAK _CAN0CTL1.Bits.SLPAK -#define CAN0CTL1_WUPM _CAN0CTL1.Bits.WUPM -#define CAN0CTL1_LISTEN _CAN0CTL1.Bits.LISTEN -#define CAN0CTL1_LOOPB _CAN0CTL1.Bits.LOOPB -#define CAN0CTL1_CLKSRC _CAN0CTL1.Bits.CLKSRC -#define CAN0CTL1_CANE _CAN0CTL1.Bits.CANE - - -/*** CAN0BTR0 - MSCAN 0 Bus Timing Register 0; 0x00000142 ***/ -typedef union { - byte Byte; - struct { - byte BRP0 :1; /* Baud Rate Prescaler 0 */ - byte BRP1 :1; /* Baud Rate Prescaler 1 */ - byte BRP2 :1; /* Baud Rate Prescaler 2 */ - byte BRP3 :1; /* Baud Rate Prescaler 3 */ - byte BRP4 :1; /* Baud Rate Prescaler 4 */ - byte BRP5 :1; /* Baud Rate Prescaler 5 */ - byte SJW0 :1; /* Synchronization Jump Width 0 */ - byte SJW1 :1; /* Synchronization Jump Width 1 */ - } Bits; - struct { - byte grpBRP :6; - byte grpSJW :2; - } MergedBits; -} CAN0BTR0STR; -extern volatile CAN0BTR0STR _CAN0BTR0 @(REG_BASE + 0x00000142); -#define CAN0BTR0 _CAN0BTR0.Byte -#define CAN0BTR0_BRP0 _CAN0BTR0.Bits.BRP0 -#define CAN0BTR0_BRP1 _CAN0BTR0.Bits.BRP1 -#define CAN0BTR0_BRP2 _CAN0BTR0.Bits.BRP2 -#define CAN0BTR0_BRP3 _CAN0BTR0.Bits.BRP3 -#define CAN0BTR0_BRP4 _CAN0BTR0.Bits.BRP4 -#define CAN0BTR0_BRP5 _CAN0BTR0.Bits.BRP5 -#define CAN0BTR0_SJW0 _CAN0BTR0.Bits.SJW0 -#define CAN0BTR0_SJW1 _CAN0BTR0.Bits.SJW1 -#define CAN0BTR0_BRP _CAN0BTR0.MergedBits.grpBRP -#define CAN0BTR0_SJW _CAN0BTR0.MergedBits.grpSJW - - -/*** CAN0BTR1 - MSCAN 0 Bus Timing Register 1; 0x00000143 ***/ -typedef union { - byte Byte; - struct { - byte TSEG10 :1; /* Time Segment 1 */ - byte TSEG11 :1; /* Time Segment 1 */ - byte TSEG12 :1; /* Time Segment 1 */ - byte TSEG13 :1; /* Time Segment 1 */ - byte TSEG20 :1; /* Time Segment 2 */ - byte TSEG21 :1; /* Time Segment 2 */ - byte TSEG22 :1; /* Time Segment 2 */ - byte SAMP :1; /* Sampling */ - } Bits; - struct { - byte grpTSEG_10 :4; - byte grpTSEG_20 :3; - byte :1; - } MergedBits; -} CAN0BTR1STR; -extern volatile CAN0BTR1STR _CAN0BTR1 @(REG_BASE + 0x00000143); -#define CAN0BTR1 _CAN0BTR1.Byte -#define CAN0BTR1_TSEG10 _CAN0BTR1.Bits.TSEG10 -#define CAN0BTR1_TSEG11 _CAN0BTR1.Bits.TSEG11 -#define CAN0BTR1_TSEG12 _CAN0BTR1.Bits.TSEG12 -#define CAN0BTR1_TSEG13 _CAN0BTR1.Bits.TSEG13 -#define CAN0BTR1_TSEG20 _CAN0BTR1.Bits.TSEG20 -#define CAN0BTR1_TSEG21 _CAN0BTR1.Bits.TSEG21 -#define CAN0BTR1_TSEG22 _CAN0BTR1.Bits.TSEG22 -#define CAN0BTR1_SAMP _CAN0BTR1.Bits.SAMP -#define CAN0BTR1_TSEG_10 _CAN0BTR1.MergedBits.grpTSEG_10 -#define CAN0BTR1_TSEG_20 _CAN0BTR1.MergedBits.grpTSEG_20 -#define CAN0BTR1_TSEG CAN0BTR1_TSEG_10 - - -/*** CAN0RFLG - MSCAN 0 Receiver Flag Register; 0x00000144 ***/ -typedef union { - byte Byte; - struct { - byte RXF :1; /* Receive Buffer Full */ - byte OVRIF :1; /* Overrun Interrupt Flag */ - byte TSTAT0 :1; /* Transmitter Status Bit 0 */ - byte TSTAT1 :1; /* Transmitter Status Bit 1 */ - byte RSTAT0 :1; /* Receiver Status Bit 0 */ - byte RSTAT1 :1; /* Receiver Status Bit 1 */ - byte CSCIF :1; /* CAN Status Change Interrupt Flag */ - byte WUPIF :1; /* Wake-up Interrupt Flag */ - } Bits; - struct { - byte :1; - byte :1; - byte grpTSTAT :2; - byte grpRSTAT :2; - byte :1; - byte :1; - } MergedBits; -} CAN0RFLGSTR; -extern volatile CAN0RFLGSTR _CAN0RFLG @(REG_BASE + 0x00000144); -#define CAN0RFLG _CAN0RFLG.Byte -#define CAN0RFLG_RXF _CAN0RFLG.Bits.RXF -#define CAN0RFLG_OVRIF _CAN0RFLG.Bits.OVRIF -#define CAN0RFLG_TSTAT0 _CAN0RFLG.Bits.TSTAT0 -#define CAN0RFLG_TSTAT1 _CAN0RFLG.Bits.TSTAT1 -#define CAN0RFLG_RSTAT0 _CAN0RFLG.Bits.RSTAT0 -#define CAN0RFLG_RSTAT1 _CAN0RFLG.Bits.RSTAT1 -#define CAN0RFLG_CSCIF _CAN0RFLG.Bits.CSCIF -#define CAN0RFLG_WUPIF _CAN0RFLG.Bits.WUPIF -#define CAN0RFLG_TSTAT _CAN0RFLG.MergedBits.grpTSTAT -#define CAN0RFLG_RSTAT _CAN0RFLG.MergedBits.grpRSTAT - - -/*** CAN0RIER - MSCAN 0 Receiver Interrupt Enable Register; 0x00000145 ***/ -typedef union { - byte Byte; - struct { - byte RXFIE :1; /* Receiver Full Interrupt Enable */ - byte OVRIE :1; /* Overrun Interrupt Enable */ - byte TSTATE0 :1; /* Transmitter Status Change Enable 0 */ - byte TSTATE1 :1; /* Transmitter Status Change Enable 1 */ - byte RSTATE0 :1; /* Receiver Status Change Enable 0 */ - byte RSTATE1 :1; /* Receiver Status Change Enable 1 */ - byte CSCIE :1; /* CAN Status Change Interrupt Enable */ - byte WUPIE :1; /* Wake-up Interrupt Enable */ - } Bits; - struct { - byte :1; - byte :1; - byte grpTSTATE :2; - byte grpRSTATE :2; - byte :1; - byte :1; - } MergedBits; -} CAN0RIERSTR; -extern volatile CAN0RIERSTR _CAN0RIER @(REG_BASE + 0x00000145); -#define CAN0RIER _CAN0RIER.Byte -#define CAN0RIER_RXFIE _CAN0RIER.Bits.RXFIE -#define CAN0RIER_OVRIE _CAN0RIER.Bits.OVRIE -#define CAN0RIER_TSTATE0 _CAN0RIER.Bits.TSTATE0 -#define CAN0RIER_TSTATE1 _CAN0RIER.Bits.TSTATE1 -#define CAN0RIER_RSTATE0 _CAN0RIER.Bits.RSTATE0 -#define CAN0RIER_RSTATE1 _CAN0RIER.Bits.RSTATE1 -#define CAN0RIER_CSCIE _CAN0RIER.Bits.CSCIE -#define CAN0RIER_WUPIE _CAN0RIER.Bits.WUPIE -#define CAN0RIER_TSTATE _CAN0RIER.MergedBits.grpTSTATE -#define CAN0RIER_RSTATE _CAN0RIER.MergedBits.grpRSTATE - - -/*** CAN0TFLG - MSCAN 0 Transmitter Flag Register; 0x00000146 ***/ -typedef union { - byte Byte; - struct { - byte TXE0 :1; /* Transmitter Buffer Empty 0 */ - byte TXE1 :1; /* Transmitter Buffer Empty 1 */ - byte TXE2 :1; /* Transmitter Buffer Empty 2 */ - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpTXE :3; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} CAN0TFLGSTR; -extern volatile CAN0TFLGSTR _CAN0TFLG @(REG_BASE + 0x00000146); -#define CAN0TFLG _CAN0TFLG.Byte -#define CAN0TFLG_TXE0 _CAN0TFLG.Bits.TXE0 -#define CAN0TFLG_TXE1 _CAN0TFLG.Bits.TXE1 -#define CAN0TFLG_TXE2 _CAN0TFLG.Bits.TXE2 -#define CAN0TFLG_TXE _CAN0TFLG.MergedBits.grpTXE - - -/*** CAN0TIER - MSCAN 0 Transmitter Interrupt Enable Register; 0x00000147 ***/ -typedef union { - byte Byte; - struct { - byte TXEIE0 :1; /* Transmitter Empty Interrupt Enable 0 */ - byte TXEIE1 :1; /* Transmitter Empty Interrupt Enable 1 */ - byte TXEIE2 :1; /* Transmitter Empty Interrupt Enable 2 */ - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpTXEIE :3; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} CAN0TIERSTR; -extern volatile CAN0TIERSTR _CAN0TIER @(REG_BASE + 0x00000147); -#define CAN0TIER _CAN0TIER.Byte -#define CAN0TIER_TXEIE0 _CAN0TIER.Bits.TXEIE0 -#define CAN0TIER_TXEIE1 _CAN0TIER.Bits.TXEIE1 -#define CAN0TIER_TXEIE2 _CAN0TIER.Bits.TXEIE2 -#define CAN0TIER_TXEIE _CAN0TIER.MergedBits.grpTXEIE - - -/*** CAN0TARQ - MSCAN 0 Transmitter Message Abort Request; 0x00000148 ***/ -typedef union { - byte Byte; - struct { - byte ABTRQ0 :1; /* Abort Request 0 */ - byte ABTRQ1 :1; /* Abort Request 1 */ - byte ABTRQ2 :1; /* Abort Request 2 */ - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpABTRQ :3; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} CAN0TARQSTR; -extern volatile CAN0TARQSTR _CAN0TARQ @(REG_BASE + 0x00000148); -#define CAN0TARQ _CAN0TARQ.Byte -#define CAN0TARQ_ABTRQ0 _CAN0TARQ.Bits.ABTRQ0 -#define CAN0TARQ_ABTRQ1 _CAN0TARQ.Bits.ABTRQ1 -#define CAN0TARQ_ABTRQ2 _CAN0TARQ.Bits.ABTRQ2 -#define CAN0TARQ_ABTRQ _CAN0TARQ.MergedBits.grpABTRQ - - -/*** CAN0TAAK - MSCAN 0 Transmitter Message Abort Control; 0x00000149 ***/ -typedef union { - byte Byte; - struct { - byte ABTAK0 :1; /* Abort Acknowledge 0 */ - byte ABTAK1 :1; /* Abort Acknowledge 1 */ - byte ABTAK2 :1; /* Abort Acknowledge 2 */ - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpABTAK :3; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} CAN0TAAKSTR; -extern volatile CAN0TAAKSTR _CAN0TAAK @(REG_BASE + 0x00000149); -#define CAN0TAAK _CAN0TAAK.Byte -#define CAN0TAAK_ABTAK0 _CAN0TAAK.Bits.ABTAK0 -#define CAN0TAAK_ABTAK1 _CAN0TAAK.Bits.ABTAK1 -#define CAN0TAAK_ABTAK2 _CAN0TAAK.Bits.ABTAK2 -#define CAN0TAAK_ABTAK _CAN0TAAK.MergedBits.grpABTAK - - -/*** CAN0TBSEL - MSCAN 0 Transmit Buffer Selection; 0x0000014A ***/ -typedef union { - byte Byte; - struct { - byte TX0 :1; /* Transmit Buffer Select 0 */ - byte TX1 :1; /* Transmit Buffer Select 1 */ - byte TX2 :1; /* Transmit Buffer Select 2 */ - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpTX :3; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} CAN0TBSELSTR; -extern volatile CAN0TBSELSTR _CAN0TBSEL @(REG_BASE + 0x0000014A); -#define CAN0TBSEL _CAN0TBSEL.Byte -#define CAN0TBSEL_TX0 _CAN0TBSEL.Bits.TX0 -#define CAN0TBSEL_TX1 _CAN0TBSEL.Bits.TX1 -#define CAN0TBSEL_TX2 _CAN0TBSEL.Bits.TX2 -#define CAN0TBSEL_TX _CAN0TBSEL.MergedBits.grpTX - - -/*** CAN0IDAC - MSCAN 0 Identifier Acceptance Control Register; 0x0000014B ***/ -typedef union { - byte Byte; - struct { - byte IDHIT0 :1; /* Identifier Acceptance Hit Indicator 0 */ - byte IDHIT1 :1; /* Identifier Acceptance Hit Indicator 1 */ - byte IDHIT2 :1; /* Identifier Acceptance Hit Indicator 2 */ - byte :1; - byte IDAM0 :1; /* Identifier Acceptance Mode 0 */ - byte IDAM1 :1; /* Identifier Acceptance Mode 1 */ - byte :1; - byte :1; - } Bits; - struct { - byte grpIDHIT :3; - byte :1; - byte grpIDAM :2; - byte :1; - byte :1; - } MergedBits; -} CAN0IDACSTR; -extern volatile CAN0IDACSTR _CAN0IDAC @(REG_BASE + 0x0000014B); -#define CAN0IDAC _CAN0IDAC.Byte -#define CAN0IDAC_IDHIT0 _CAN0IDAC.Bits.IDHIT0 -#define CAN0IDAC_IDHIT1 _CAN0IDAC.Bits.IDHIT1 -#define CAN0IDAC_IDHIT2 _CAN0IDAC.Bits.IDHIT2 -#define CAN0IDAC_IDAM0 _CAN0IDAC.Bits.IDAM0 -#define CAN0IDAC_IDAM1 _CAN0IDAC.Bits.IDAM1 -#define CAN0IDAC_IDHIT _CAN0IDAC.MergedBits.grpIDHIT -#define CAN0IDAC_IDAM _CAN0IDAC.MergedBits.grpIDAM - - -/*** CAN0RXERR - MSCAN 0 Receive Error Counter Register; 0x0000014E ***/ -typedef union { - byte Byte; - struct { - byte RXERR0 :1; /* Bit 0 */ - byte RXERR1 :1; /* Bit 1 */ - byte RXERR2 :1; /* Bit 2 */ - byte RXERR3 :1; /* Bit 3 */ - byte RXERR4 :1; /* Bit 4 */ - byte RXERR5 :1; /* Bit 5 */ - byte RXERR6 :1; /* Bit 6 */ - byte RXERR7 :1; /* Bit 7 */ - } Bits; - struct { - byte grpRXERR :8; - } MergedBits; -} CAN0RXERRSTR; -extern volatile CAN0RXERRSTR _CAN0RXERR @(REG_BASE + 0x0000014E); -#define CAN0RXERR _CAN0RXERR.Byte -#define CAN0RXERR_RXERR0 _CAN0RXERR.Bits.RXERR0 -#define CAN0RXERR_RXERR1 _CAN0RXERR.Bits.RXERR1 -#define CAN0RXERR_RXERR2 _CAN0RXERR.Bits.RXERR2 -#define CAN0RXERR_RXERR3 _CAN0RXERR.Bits.RXERR3 -#define CAN0RXERR_RXERR4 _CAN0RXERR.Bits.RXERR4 -#define CAN0RXERR_RXERR5 _CAN0RXERR.Bits.RXERR5 -#define CAN0RXERR_RXERR6 _CAN0RXERR.Bits.RXERR6 -#define CAN0RXERR_RXERR7 _CAN0RXERR.Bits.RXERR7 -#define CAN0RXERR_RXERR _CAN0RXERR.MergedBits.grpRXERR - - -/*** CAN0TXERR - MSCAN 0 Transmit Error Counter Register; 0x0000014F ***/ -typedef union { - byte Byte; - struct { - byte TXERR0 :1; /* Bit 0 */ - byte TXERR1 :1; /* Bit 1 */ - byte TXERR2 :1; /* Bit 2 */ - byte TXERR3 :1; /* Bit 3 */ - byte TXERR4 :1; /* Bit 4 */ - byte TXERR5 :1; /* Bit 5 */ - byte TXERR6 :1; /* Bit 6 */ - byte TXERR7 :1; /* Bit 7 */ - } Bits; - struct { - byte grpTXERR :8; - } MergedBits; -} CAN0TXERRSTR; -extern volatile CAN0TXERRSTR _CAN0TXERR @(REG_BASE + 0x0000014F); -#define CAN0TXERR _CAN0TXERR.Byte -#define CAN0TXERR_TXERR0 _CAN0TXERR.Bits.TXERR0 -#define CAN0TXERR_TXERR1 _CAN0TXERR.Bits.TXERR1 -#define CAN0TXERR_TXERR2 _CAN0TXERR.Bits.TXERR2 -#define CAN0TXERR_TXERR3 _CAN0TXERR.Bits.TXERR3 -#define CAN0TXERR_TXERR4 _CAN0TXERR.Bits.TXERR4 -#define CAN0TXERR_TXERR5 _CAN0TXERR.Bits.TXERR5 -#define CAN0TXERR_TXERR6 _CAN0TXERR.Bits.TXERR6 -#define CAN0TXERR_TXERR7 _CAN0TXERR.Bits.TXERR7 -#define CAN0TXERR_TXERR _CAN0TXERR.MergedBits.grpTXERR - - -/*** CAN0IDAR0 - MSCAN 0 Identifier Acceptance Register 0; 0x00000150 ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CAN0IDAR0STR; -extern volatile CAN0IDAR0STR _CAN0IDAR0 @(REG_BASE + 0x00000150); -#define CAN0IDAR0 _CAN0IDAR0.Byte -#define CAN0IDAR0_AC0 _CAN0IDAR0.Bits.AC0 -#define CAN0IDAR0_AC1 _CAN0IDAR0.Bits.AC1 -#define CAN0IDAR0_AC2 _CAN0IDAR0.Bits.AC2 -#define CAN0IDAR0_AC3 _CAN0IDAR0.Bits.AC3 -#define CAN0IDAR0_AC4 _CAN0IDAR0.Bits.AC4 -#define CAN0IDAR0_AC5 _CAN0IDAR0.Bits.AC5 -#define CAN0IDAR0_AC6 _CAN0IDAR0.Bits.AC6 -#define CAN0IDAR0_AC7 _CAN0IDAR0.Bits.AC7 -#define CAN0IDAR0_AC _CAN0IDAR0.MergedBits.grpAC - - -/*** CAN0IDAR1 - MSCAN 0 Identifier Acceptance Register 1; 0x00000151 ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CAN0IDAR1STR; -extern volatile CAN0IDAR1STR _CAN0IDAR1 @(REG_BASE + 0x00000151); -#define CAN0IDAR1 _CAN0IDAR1.Byte -#define CAN0IDAR1_AC0 _CAN0IDAR1.Bits.AC0 -#define CAN0IDAR1_AC1 _CAN0IDAR1.Bits.AC1 -#define CAN0IDAR1_AC2 _CAN0IDAR1.Bits.AC2 -#define CAN0IDAR1_AC3 _CAN0IDAR1.Bits.AC3 -#define CAN0IDAR1_AC4 _CAN0IDAR1.Bits.AC4 -#define CAN0IDAR1_AC5 _CAN0IDAR1.Bits.AC5 -#define CAN0IDAR1_AC6 _CAN0IDAR1.Bits.AC6 -#define CAN0IDAR1_AC7 _CAN0IDAR1.Bits.AC7 -#define CAN0IDAR1_AC _CAN0IDAR1.MergedBits.grpAC - - -/*** CAN0IDAR2 - MSCAN 0 Identifier Acceptance Register 2; 0x00000152 ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CAN0IDAR2STR; -extern volatile CAN0IDAR2STR _CAN0IDAR2 @(REG_BASE + 0x00000152); -#define CAN0IDAR2 _CAN0IDAR2.Byte -#define CAN0IDAR2_AC0 _CAN0IDAR2.Bits.AC0 -#define CAN0IDAR2_AC1 _CAN0IDAR2.Bits.AC1 -#define CAN0IDAR2_AC2 _CAN0IDAR2.Bits.AC2 -#define CAN0IDAR2_AC3 _CAN0IDAR2.Bits.AC3 -#define CAN0IDAR2_AC4 _CAN0IDAR2.Bits.AC4 -#define CAN0IDAR2_AC5 _CAN0IDAR2.Bits.AC5 -#define CAN0IDAR2_AC6 _CAN0IDAR2.Bits.AC6 -#define CAN0IDAR2_AC7 _CAN0IDAR2.Bits.AC7 -#define CAN0IDAR2_AC _CAN0IDAR2.MergedBits.grpAC - - -/*** CAN0IDAR3 - MSCAN 0 Identifier Acceptance Register 3; 0x00000153 ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CAN0IDAR3STR; -extern volatile CAN0IDAR3STR _CAN0IDAR3 @(REG_BASE + 0x00000153); -#define CAN0IDAR3 _CAN0IDAR3.Byte -#define CAN0IDAR3_AC0 _CAN0IDAR3.Bits.AC0 -#define CAN0IDAR3_AC1 _CAN0IDAR3.Bits.AC1 -#define CAN0IDAR3_AC2 _CAN0IDAR3.Bits.AC2 -#define CAN0IDAR3_AC3 _CAN0IDAR3.Bits.AC3 -#define CAN0IDAR3_AC4 _CAN0IDAR3.Bits.AC4 -#define CAN0IDAR3_AC5 _CAN0IDAR3.Bits.AC5 -#define CAN0IDAR3_AC6 _CAN0IDAR3.Bits.AC6 -#define CAN0IDAR3_AC7 _CAN0IDAR3.Bits.AC7 -#define CAN0IDAR3_AC _CAN0IDAR3.MergedBits.grpAC - - -/*** CAN0IDMR0 - MSCAN 0 Identifier Mask Register 0; 0x00000154 ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CAN0IDMR0STR; -extern volatile CAN0IDMR0STR _CAN0IDMR0 @(REG_BASE + 0x00000154); -#define CAN0IDMR0 _CAN0IDMR0.Byte -#define CAN0IDMR0_AM0 _CAN0IDMR0.Bits.AM0 -#define CAN0IDMR0_AM1 _CAN0IDMR0.Bits.AM1 -#define CAN0IDMR0_AM2 _CAN0IDMR0.Bits.AM2 -#define CAN0IDMR0_AM3 _CAN0IDMR0.Bits.AM3 -#define CAN0IDMR0_AM4 _CAN0IDMR0.Bits.AM4 -#define CAN0IDMR0_AM5 _CAN0IDMR0.Bits.AM5 -#define CAN0IDMR0_AM6 _CAN0IDMR0.Bits.AM6 -#define CAN0IDMR0_AM7 _CAN0IDMR0.Bits.AM7 -#define CAN0IDMR0_AM _CAN0IDMR0.MergedBits.grpAM - - -/*** CAN0IDMR1 - MSCAN 0 Identifier Mask Register 1; 0x00000155 ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CAN0IDMR1STR; -extern volatile CAN0IDMR1STR _CAN0IDMR1 @(REG_BASE + 0x00000155); -#define CAN0IDMR1 _CAN0IDMR1.Byte -#define CAN0IDMR1_AM0 _CAN0IDMR1.Bits.AM0 -#define CAN0IDMR1_AM1 _CAN0IDMR1.Bits.AM1 -#define CAN0IDMR1_AM2 _CAN0IDMR1.Bits.AM2 -#define CAN0IDMR1_AM3 _CAN0IDMR1.Bits.AM3 -#define CAN0IDMR1_AM4 _CAN0IDMR1.Bits.AM4 -#define CAN0IDMR1_AM5 _CAN0IDMR1.Bits.AM5 -#define CAN0IDMR1_AM6 _CAN0IDMR1.Bits.AM6 -#define CAN0IDMR1_AM7 _CAN0IDMR1.Bits.AM7 -#define CAN0IDMR1_AM _CAN0IDMR1.MergedBits.grpAM - - -/*** CAN0IDMR2 - MSCAN 0 Identifier Mask Register 2; 0x00000156 ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CAN0IDMR2STR; -extern volatile CAN0IDMR2STR _CAN0IDMR2 @(REG_BASE + 0x00000156); -#define CAN0IDMR2 _CAN0IDMR2.Byte -#define CAN0IDMR2_AM0 _CAN0IDMR2.Bits.AM0 -#define CAN0IDMR2_AM1 _CAN0IDMR2.Bits.AM1 -#define CAN0IDMR2_AM2 _CAN0IDMR2.Bits.AM2 -#define CAN0IDMR2_AM3 _CAN0IDMR2.Bits.AM3 -#define CAN0IDMR2_AM4 _CAN0IDMR2.Bits.AM4 -#define CAN0IDMR2_AM5 _CAN0IDMR2.Bits.AM5 -#define CAN0IDMR2_AM6 _CAN0IDMR2.Bits.AM6 -#define CAN0IDMR2_AM7 _CAN0IDMR2.Bits.AM7 -#define CAN0IDMR2_AM _CAN0IDMR2.MergedBits.grpAM - - -/*** CAN0IDMR3 - MSCAN 0 Identifier Mask Register 3; 0x00000157 ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CAN0IDMR3STR; -extern volatile CAN0IDMR3STR _CAN0IDMR3 @(REG_BASE + 0x00000157); -#define CAN0IDMR3 _CAN0IDMR3.Byte -#define CAN0IDMR3_AM0 _CAN0IDMR3.Bits.AM0 -#define CAN0IDMR3_AM1 _CAN0IDMR3.Bits.AM1 -#define CAN0IDMR3_AM2 _CAN0IDMR3.Bits.AM2 -#define CAN0IDMR3_AM3 _CAN0IDMR3.Bits.AM3 -#define CAN0IDMR3_AM4 _CAN0IDMR3.Bits.AM4 -#define CAN0IDMR3_AM5 _CAN0IDMR3.Bits.AM5 -#define CAN0IDMR3_AM6 _CAN0IDMR3.Bits.AM6 -#define CAN0IDMR3_AM7 _CAN0IDMR3.Bits.AM7 -#define CAN0IDMR3_AM _CAN0IDMR3.MergedBits.grpAM - - -/*** CAN0IDAR4 - MSCAN 0 Identifier Acceptance Register 4; 0x00000158 ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CAN0IDAR4STR; -extern volatile CAN0IDAR4STR _CAN0IDAR4 @(REG_BASE + 0x00000158); -#define CAN0IDAR4 _CAN0IDAR4.Byte -#define CAN0IDAR4_AC0 _CAN0IDAR4.Bits.AC0 -#define CAN0IDAR4_AC1 _CAN0IDAR4.Bits.AC1 -#define CAN0IDAR4_AC2 _CAN0IDAR4.Bits.AC2 -#define CAN0IDAR4_AC3 _CAN0IDAR4.Bits.AC3 -#define CAN0IDAR4_AC4 _CAN0IDAR4.Bits.AC4 -#define CAN0IDAR4_AC5 _CAN0IDAR4.Bits.AC5 -#define CAN0IDAR4_AC6 _CAN0IDAR4.Bits.AC6 -#define CAN0IDAR4_AC7 _CAN0IDAR4.Bits.AC7 -#define CAN0IDAR4_AC _CAN0IDAR4.MergedBits.grpAC - - -/*** CAN0IDAR5 - MSCAN 0 Identifier Acceptance Register 5; 0x00000159 ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CAN0IDAR5STR; -extern volatile CAN0IDAR5STR _CAN0IDAR5 @(REG_BASE + 0x00000159); -#define CAN0IDAR5 _CAN0IDAR5.Byte -#define CAN0IDAR5_AC0 _CAN0IDAR5.Bits.AC0 -#define CAN0IDAR5_AC1 _CAN0IDAR5.Bits.AC1 -#define CAN0IDAR5_AC2 _CAN0IDAR5.Bits.AC2 -#define CAN0IDAR5_AC3 _CAN0IDAR5.Bits.AC3 -#define CAN0IDAR5_AC4 _CAN0IDAR5.Bits.AC4 -#define CAN0IDAR5_AC5 _CAN0IDAR5.Bits.AC5 -#define CAN0IDAR5_AC6 _CAN0IDAR5.Bits.AC6 -#define CAN0IDAR5_AC7 _CAN0IDAR5.Bits.AC7 -#define CAN0IDAR5_AC _CAN0IDAR5.MergedBits.grpAC - - -/*** CAN0IDAR6 - MSCAN 0 Identifier Acceptance Register 6; 0x0000015A ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CAN0IDAR6STR; -extern volatile CAN0IDAR6STR _CAN0IDAR6 @(REG_BASE + 0x0000015A); -#define CAN0IDAR6 _CAN0IDAR6.Byte -#define CAN0IDAR6_AC0 _CAN0IDAR6.Bits.AC0 -#define CAN0IDAR6_AC1 _CAN0IDAR6.Bits.AC1 -#define CAN0IDAR6_AC2 _CAN0IDAR6.Bits.AC2 -#define CAN0IDAR6_AC3 _CAN0IDAR6.Bits.AC3 -#define CAN0IDAR6_AC4 _CAN0IDAR6.Bits.AC4 -#define CAN0IDAR6_AC5 _CAN0IDAR6.Bits.AC5 -#define CAN0IDAR6_AC6 _CAN0IDAR6.Bits.AC6 -#define CAN0IDAR6_AC7 _CAN0IDAR6.Bits.AC7 -#define CAN0IDAR6_AC _CAN0IDAR6.MergedBits.grpAC - - -/*** CAN0IDAR7 - MSCAN 0 Identifier Acceptance Register 7; 0x0000015B ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CAN0IDAR7STR; -extern volatile CAN0IDAR7STR _CAN0IDAR7 @(REG_BASE + 0x0000015B); -#define CAN0IDAR7 _CAN0IDAR7.Byte -#define CAN0IDAR7_AC0 _CAN0IDAR7.Bits.AC0 -#define CAN0IDAR7_AC1 _CAN0IDAR7.Bits.AC1 -#define CAN0IDAR7_AC2 _CAN0IDAR7.Bits.AC2 -#define CAN0IDAR7_AC3 _CAN0IDAR7.Bits.AC3 -#define CAN0IDAR7_AC4 _CAN0IDAR7.Bits.AC4 -#define CAN0IDAR7_AC5 _CAN0IDAR7.Bits.AC5 -#define CAN0IDAR7_AC6 _CAN0IDAR7.Bits.AC6 -#define CAN0IDAR7_AC7 _CAN0IDAR7.Bits.AC7 -#define CAN0IDAR7_AC _CAN0IDAR7.MergedBits.grpAC - - -/*** CAN0IDMR4 - MSCAN 0 Identifier Mask Register 4; 0x0000015C ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CAN0IDMR4STR; -extern volatile CAN0IDMR4STR _CAN0IDMR4 @(REG_BASE + 0x0000015C); -#define CAN0IDMR4 _CAN0IDMR4.Byte -#define CAN0IDMR4_AM0 _CAN0IDMR4.Bits.AM0 -#define CAN0IDMR4_AM1 _CAN0IDMR4.Bits.AM1 -#define CAN0IDMR4_AM2 _CAN0IDMR4.Bits.AM2 -#define CAN0IDMR4_AM3 _CAN0IDMR4.Bits.AM3 -#define CAN0IDMR4_AM4 _CAN0IDMR4.Bits.AM4 -#define CAN0IDMR4_AM5 _CAN0IDMR4.Bits.AM5 -#define CAN0IDMR4_AM6 _CAN0IDMR4.Bits.AM6 -#define CAN0IDMR4_AM7 _CAN0IDMR4.Bits.AM7 -#define CAN0IDMR4_AM _CAN0IDMR4.MergedBits.grpAM - - -/*** CAN0IDMR5 - MSCAN 0 Identifier Mask Register 5; 0x0000015D ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CAN0IDMR5STR; -extern volatile CAN0IDMR5STR _CAN0IDMR5 @(REG_BASE + 0x0000015D); -#define CAN0IDMR5 _CAN0IDMR5.Byte -#define CAN0IDMR5_AM0 _CAN0IDMR5.Bits.AM0 -#define CAN0IDMR5_AM1 _CAN0IDMR5.Bits.AM1 -#define CAN0IDMR5_AM2 _CAN0IDMR5.Bits.AM2 -#define CAN0IDMR5_AM3 _CAN0IDMR5.Bits.AM3 -#define CAN0IDMR5_AM4 _CAN0IDMR5.Bits.AM4 -#define CAN0IDMR5_AM5 _CAN0IDMR5.Bits.AM5 -#define CAN0IDMR5_AM6 _CAN0IDMR5.Bits.AM6 -#define CAN0IDMR5_AM7 _CAN0IDMR5.Bits.AM7 -#define CAN0IDMR5_AM _CAN0IDMR5.MergedBits.grpAM - - -/*** CAN0IDMR6 - MSCAN 0 Identifier Mask Register 6; 0x0000015E ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CAN0IDMR6STR; -extern volatile CAN0IDMR6STR _CAN0IDMR6 @(REG_BASE + 0x0000015E); -#define CAN0IDMR6 _CAN0IDMR6.Byte -#define CAN0IDMR6_AM0 _CAN0IDMR6.Bits.AM0 -#define CAN0IDMR6_AM1 _CAN0IDMR6.Bits.AM1 -#define CAN0IDMR6_AM2 _CAN0IDMR6.Bits.AM2 -#define CAN0IDMR6_AM3 _CAN0IDMR6.Bits.AM3 -#define CAN0IDMR6_AM4 _CAN0IDMR6.Bits.AM4 -#define CAN0IDMR6_AM5 _CAN0IDMR6.Bits.AM5 -#define CAN0IDMR6_AM6 _CAN0IDMR6.Bits.AM6 -#define CAN0IDMR6_AM7 _CAN0IDMR6.Bits.AM7 -#define CAN0IDMR6_AM _CAN0IDMR6.MergedBits.grpAM - - -/*** CAN0IDMR7 - MSCAN 0 Identifier Mask Register 7; 0x0000015F ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CAN0IDMR7STR; -extern volatile CAN0IDMR7STR _CAN0IDMR7 @(REG_BASE + 0x0000015F); -#define CAN0IDMR7 _CAN0IDMR7.Byte -#define CAN0IDMR7_AM0 _CAN0IDMR7.Bits.AM0 -#define CAN0IDMR7_AM1 _CAN0IDMR7.Bits.AM1 -#define CAN0IDMR7_AM2 _CAN0IDMR7.Bits.AM2 -#define CAN0IDMR7_AM3 _CAN0IDMR7.Bits.AM3 -#define CAN0IDMR7_AM4 _CAN0IDMR7.Bits.AM4 -#define CAN0IDMR7_AM5 _CAN0IDMR7.Bits.AM5 -#define CAN0IDMR7_AM6 _CAN0IDMR7.Bits.AM6 -#define CAN0IDMR7_AM7 _CAN0IDMR7.Bits.AM7 -#define CAN0IDMR7_AM _CAN0IDMR7.MergedBits.grpAM - - -/*** CAN0RXIDR0 - MSCAN 0 Receive Identifier Register 0; 0x00000160 ***/ -typedef union { - byte Byte; - struct { - byte ID21 :1; /* Extended format identifier Bit 21 */ - byte ID22 :1; /* Extended format identifier Bit 22 */ - byte ID23 :1; /* Extended format identifier Bit 23 */ - byte ID24 :1; /* Extended format identifier Bit 24 */ - byte ID25 :1; /* Extended format identifier Bit 25 */ - byte ID26 :1; /* Extended format identifier Bit 26 */ - byte ID27 :1; /* Extended format identifier Bit 27 */ - byte ID28 :1; /* Extended format identifier Bit 28 */ - } Bits; - struct { - byte grpID_21 :8; - } MergedBits; -} CAN0RXIDR0STR; -extern volatile CAN0RXIDR0STR _CAN0RXIDR0 @(REG_BASE + 0x00000160); -#define CAN0RXIDR0 _CAN0RXIDR0.Byte -#define CAN0RXIDR0_ID21 _CAN0RXIDR0.Bits.ID21 -#define CAN0RXIDR0_ID22 _CAN0RXIDR0.Bits.ID22 -#define CAN0RXIDR0_ID23 _CAN0RXIDR0.Bits.ID23 -#define CAN0RXIDR0_ID24 _CAN0RXIDR0.Bits.ID24 -#define CAN0RXIDR0_ID25 _CAN0RXIDR0.Bits.ID25 -#define CAN0RXIDR0_ID26 _CAN0RXIDR0.Bits.ID26 -#define CAN0RXIDR0_ID27 _CAN0RXIDR0.Bits.ID27 -#define CAN0RXIDR0_ID28 _CAN0RXIDR0.Bits.ID28 -#define CAN0RXIDR0_ID_21 _CAN0RXIDR0.MergedBits.grpID_21 -#define CAN0RXIDR0_ID CAN0RXIDR0_ID_21 - - -/*** CAN0RXIDR1 - MSCAN 0 Receive Identifier Register 1; 0x00000161 ***/ -typedef union { - byte Byte; - struct { - byte ID15 :1; /* Extended format identifier Bit 15 */ - byte ID16 :1; /* Extended format identifier Bit 16 */ - byte ID17 :1; /* Extended format identifier Bit 17 */ - byte IDE :1; /* ID Extended */ - byte SRR :1; /* Substitute Remote Request */ - byte ID18 :1; /* Extended format identifier Bit 18 */ - byte ID19 :1; /* Extended format identifier Bit 19 */ - byte ID20 :1; /* Extended format identifier Bit 20 */ - } Bits; - struct { - byte grpID_15 :3; - byte :1; - byte :1; - byte grpID_18 :3; - } MergedBits; -} CAN0RXIDR1STR; -extern volatile CAN0RXIDR1STR _CAN0RXIDR1 @(REG_BASE + 0x00000161); -#define CAN0RXIDR1 _CAN0RXIDR1.Byte -#define CAN0RXIDR1_ID15 _CAN0RXIDR1.Bits.ID15 -#define CAN0RXIDR1_ID16 _CAN0RXIDR1.Bits.ID16 -#define CAN0RXIDR1_ID17 _CAN0RXIDR1.Bits.ID17 -#define CAN0RXIDR1_IDE _CAN0RXIDR1.Bits.IDE -#define CAN0RXIDR1_SRR _CAN0RXIDR1.Bits.SRR -#define CAN0RXIDR1_ID18 _CAN0RXIDR1.Bits.ID18 -#define CAN0RXIDR1_ID19 _CAN0RXIDR1.Bits.ID19 -#define CAN0RXIDR1_ID20 _CAN0RXIDR1.Bits.ID20 -#define CAN0RXIDR1_ID_15 _CAN0RXIDR1.MergedBits.grpID_15 -#define CAN0RXIDR1_ID_18 _CAN0RXIDR1.MergedBits.grpID_18 -#define CAN0RXIDR1_ID CAN0RXIDR1_ID_15 - - -/*** CAN0RXIDR2 - MSCAN 0 Receive Identifier Register 2; 0x00000162 ***/ -typedef union { - byte Byte; - struct { - byte ID7 :1; /* Extended format identifier Bit 7 */ - byte ID8 :1; /* Extended format identifier Bit 8 */ - byte ID9 :1; /* Extended format identifier Bit 9 */ - byte ID10 :1; /* Extended format identifier Bit 10 */ - byte ID11 :1; /* Extended format identifier Bit 11 */ - byte ID12 :1; /* Extended format identifier Bit 12 */ - byte ID13 :1; /* Extended format identifier Bit 13 */ - byte ID14 :1; /* Extended format identifier Bit 14 */ - } Bits; - struct { - byte grpID_7 :8; - } MergedBits; -} CAN0RXIDR2STR; -extern volatile CAN0RXIDR2STR _CAN0RXIDR2 @(REG_BASE + 0x00000162); -#define CAN0RXIDR2 _CAN0RXIDR2.Byte -#define CAN0RXIDR2_ID7 _CAN0RXIDR2.Bits.ID7 -#define CAN0RXIDR2_ID8 _CAN0RXIDR2.Bits.ID8 -#define CAN0RXIDR2_ID9 _CAN0RXIDR2.Bits.ID9 -#define CAN0RXIDR2_ID10 _CAN0RXIDR2.Bits.ID10 -#define CAN0RXIDR2_ID11 _CAN0RXIDR2.Bits.ID11 -#define CAN0RXIDR2_ID12 _CAN0RXIDR2.Bits.ID12 -#define CAN0RXIDR2_ID13 _CAN0RXIDR2.Bits.ID13 -#define CAN0RXIDR2_ID14 _CAN0RXIDR2.Bits.ID14 -#define CAN0RXIDR2_ID_7 _CAN0RXIDR2.MergedBits.grpID_7 -#define CAN0RXIDR2_ID CAN0RXIDR2_ID_7 - - -/*** CAN0RXIDR3 - MSCAN 0 Receive Identifier Register 3; 0x00000163 ***/ -typedef union { - byte Byte; - struct { - byte RTR :1; /* Remote Transmission Request */ - byte ID0 :1; /* Extended format identifier Bit 0 */ - byte ID1 :1; /* Extended format identifier Bit 1 */ - byte ID2 :1; /* Extended format identifier Bit 2 */ - byte ID3 :1; /* Extended format identifier Bit 3 */ - byte ID4 :1; /* Extended format identifier Bit 4 */ - byte ID5 :1; /* Extended format identifier Bit 5 */ - byte ID6 :1; /* Extended format identifier Bit 6 */ - } Bits; - struct { - byte :1; - byte grpID :7; - } MergedBits; -} CAN0RXIDR3STR; -extern volatile CAN0RXIDR3STR _CAN0RXIDR3 @(REG_BASE + 0x00000163); -#define CAN0RXIDR3 _CAN0RXIDR3.Byte -#define CAN0RXIDR3_RTR _CAN0RXIDR3.Bits.RTR -#define CAN0RXIDR3_ID0 _CAN0RXIDR3.Bits.ID0 -#define CAN0RXIDR3_ID1 _CAN0RXIDR3.Bits.ID1 -#define CAN0RXIDR3_ID2 _CAN0RXIDR3.Bits.ID2 -#define CAN0RXIDR3_ID3 _CAN0RXIDR3.Bits.ID3 -#define CAN0RXIDR3_ID4 _CAN0RXIDR3.Bits.ID4 -#define CAN0RXIDR3_ID5 _CAN0RXIDR3.Bits.ID5 -#define CAN0RXIDR3_ID6 _CAN0RXIDR3.Bits.ID6 -#define CAN0RXIDR3_ID _CAN0RXIDR3.MergedBits.grpID - - -/*** CAN0RXDSR0 - MSCAN 0 Receive Data Segment Register 0; 0x00000164 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN0RXDSR0STR; -extern volatile CAN0RXDSR0STR _CAN0RXDSR0 @(REG_BASE + 0x00000164); -#define CAN0RXDSR0 _CAN0RXDSR0.Byte -#define CAN0RXDSR0_DB0 _CAN0RXDSR0.Bits.DB0 -#define CAN0RXDSR0_DB1 _CAN0RXDSR0.Bits.DB1 -#define CAN0RXDSR0_DB2 _CAN0RXDSR0.Bits.DB2 -#define CAN0RXDSR0_DB3 _CAN0RXDSR0.Bits.DB3 -#define CAN0RXDSR0_DB4 _CAN0RXDSR0.Bits.DB4 -#define CAN0RXDSR0_DB5 _CAN0RXDSR0.Bits.DB5 -#define CAN0RXDSR0_DB6 _CAN0RXDSR0.Bits.DB6 -#define CAN0RXDSR0_DB7 _CAN0RXDSR0.Bits.DB7 -#define CAN0RXDSR0_DB _CAN0RXDSR0.MergedBits.grpDB - - -/*** CAN0RXDSR1 - MSCAN 0 Receive Data Segment Register 1; 0x00000165 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN0RXDSR1STR; -extern volatile CAN0RXDSR1STR _CAN0RXDSR1 @(REG_BASE + 0x00000165); -#define CAN0RXDSR1 _CAN0RXDSR1.Byte -#define CAN0RXDSR1_DB0 _CAN0RXDSR1.Bits.DB0 -#define CAN0RXDSR1_DB1 _CAN0RXDSR1.Bits.DB1 -#define CAN0RXDSR1_DB2 _CAN0RXDSR1.Bits.DB2 -#define CAN0RXDSR1_DB3 _CAN0RXDSR1.Bits.DB3 -#define CAN0RXDSR1_DB4 _CAN0RXDSR1.Bits.DB4 -#define CAN0RXDSR1_DB5 _CAN0RXDSR1.Bits.DB5 -#define CAN0RXDSR1_DB6 _CAN0RXDSR1.Bits.DB6 -#define CAN0RXDSR1_DB7 _CAN0RXDSR1.Bits.DB7 -#define CAN0RXDSR1_DB _CAN0RXDSR1.MergedBits.grpDB - - -/*** CAN0RXDSR2 - MSCAN 0 Receive Data Segment Register 2; 0x00000166 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN0RXDSR2STR; -extern volatile CAN0RXDSR2STR _CAN0RXDSR2 @(REG_BASE + 0x00000166); -#define CAN0RXDSR2 _CAN0RXDSR2.Byte -#define CAN0RXDSR2_DB0 _CAN0RXDSR2.Bits.DB0 -#define CAN0RXDSR2_DB1 _CAN0RXDSR2.Bits.DB1 -#define CAN0RXDSR2_DB2 _CAN0RXDSR2.Bits.DB2 -#define CAN0RXDSR2_DB3 _CAN0RXDSR2.Bits.DB3 -#define CAN0RXDSR2_DB4 _CAN0RXDSR2.Bits.DB4 -#define CAN0RXDSR2_DB5 _CAN0RXDSR2.Bits.DB5 -#define CAN0RXDSR2_DB6 _CAN0RXDSR2.Bits.DB6 -#define CAN0RXDSR2_DB7 _CAN0RXDSR2.Bits.DB7 -#define CAN0RXDSR2_DB _CAN0RXDSR2.MergedBits.grpDB - - -/*** CAN0RXDSR3 - MSCAN 0 Receive Data Segment Register 3; 0x00000167 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN0RXDSR3STR; -extern volatile CAN0RXDSR3STR _CAN0RXDSR3 @(REG_BASE + 0x00000167); -#define CAN0RXDSR3 _CAN0RXDSR3.Byte -#define CAN0RXDSR3_DB0 _CAN0RXDSR3.Bits.DB0 -#define CAN0RXDSR3_DB1 _CAN0RXDSR3.Bits.DB1 -#define CAN0RXDSR3_DB2 _CAN0RXDSR3.Bits.DB2 -#define CAN0RXDSR3_DB3 _CAN0RXDSR3.Bits.DB3 -#define CAN0RXDSR3_DB4 _CAN0RXDSR3.Bits.DB4 -#define CAN0RXDSR3_DB5 _CAN0RXDSR3.Bits.DB5 -#define CAN0RXDSR3_DB6 _CAN0RXDSR3.Bits.DB6 -#define CAN0RXDSR3_DB7 _CAN0RXDSR3.Bits.DB7 -#define CAN0RXDSR3_DB _CAN0RXDSR3.MergedBits.grpDB - - -/*** CAN0RXDSR4 - MSCAN 0 Receive Data Segment Register 4; 0x00000168 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN0RXDSR4STR; -extern volatile CAN0RXDSR4STR _CAN0RXDSR4 @(REG_BASE + 0x00000168); -#define CAN0RXDSR4 _CAN0RXDSR4.Byte -#define CAN0RXDSR4_DB0 _CAN0RXDSR4.Bits.DB0 -#define CAN0RXDSR4_DB1 _CAN0RXDSR4.Bits.DB1 -#define CAN0RXDSR4_DB2 _CAN0RXDSR4.Bits.DB2 -#define CAN0RXDSR4_DB3 _CAN0RXDSR4.Bits.DB3 -#define CAN0RXDSR4_DB4 _CAN0RXDSR4.Bits.DB4 -#define CAN0RXDSR4_DB5 _CAN0RXDSR4.Bits.DB5 -#define CAN0RXDSR4_DB6 _CAN0RXDSR4.Bits.DB6 -#define CAN0RXDSR4_DB7 _CAN0RXDSR4.Bits.DB7 -#define CAN0RXDSR4_DB _CAN0RXDSR4.MergedBits.grpDB - - -/*** CAN0RXDSR5 - MSCAN 0 Receive Data Segment Register 5; 0x00000169 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN0RXDSR5STR; -extern volatile CAN0RXDSR5STR _CAN0RXDSR5 @(REG_BASE + 0x00000169); -#define CAN0RXDSR5 _CAN0RXDSR5.Byte -#define CAN0RXDSR5_DB0 _CAN0RXDSR5.Bits.DB0 -#define CAN0RXDSR5_DB1 _CAN0RXDSR5.Bits.DB1 -#define CAN0RXDSR5_DB2 _CAN0RXDSR5.Bits.DB2 -#define CAN0RXDSR5_DB3 _CAN0RXDSR5.Bits.DB3 -#define CAN0RXDSR5_DB4 _CAN0RXDSR5.Bits.DB4 -#define CAN0RXDSR5_DB5 _CAN0RXDSR5.Bits.DB5 -#define CAN0RXDSR5_DB6 _CAN0RXDSR5.Bits.DB6 -#define CAN0RXDSR5_DB7 _CAN0RXDSR5.Bits.DB7 -#define CAN0RXDSR5_DB _CAN0RXDSR5.MergedBits.grpDB - - -/*** CAN0RXDSR6 - MSCAN 0 Receive Data Segment Register 6; 0x0000016A ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN0RXDSR6STR; -extern volatile CAN0RXDSR6STR _CAN0RXDSR6 @(REG_BASE + 0x0000016A); -#define CAN0RXDSR6 _CAN0RXDSR6.Byte -#define CAN0RXDSR6_DB0 _CAN0RXDSR6.Bits.DB0 -#define CAN0RXDSR6_DB1 _CAN0RXDSR6.Bits.DB1 -#define CAN0RXDSR6_DB2 _CAN0RXDSR6.Bits.DB2 -#define CAN0RXDSR6_DB3 _CAN0RXDSR6.Bits.DB3 -#define CAN0RXDSR6_DB4 _CAN0RXDSR6.Bits.DB4 -#define CAN0RXDSR6_DB5 _CAN0RXDSR6.Bits.DB5 -#define CAN0RXDSR6_DB6 _CAN0RXDSR6.Bits.DB6 -#define CAN0RXDSR6_DB7 _CAN0RXDSR6.Bits.DB7 -#define CAN0RXDSR6_DB _CAN0RXDSR6.MergedBits.grpDB - - -/*** CAN0RXDSR7 - MSCAN 0 Receive Data Segment Register 7; 0x0000016B ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN0RXDSR7STR; -extern volatile CAN0RXDSR7STR _CAN0RXDSR7 @(REG_BASE + 0x0000016B); -#define CAN0RXDSR7 _CAN0RXDSR7.Byte -#define CAN0RXDSR7_DB0 _CAN0RXDSR7.Bits.DB0 -#define CAN0RXDSR7_DB1 _CAN0RXDSR7.Bits.DB1 -#define CAN0RXDSR7_DB2 _CAN0RXDSR7.Bits.DB2 -#define CAN0RXDSR7_DB3 _CAN0RXDSR7.Bits.DB3 -#define CAN0RXDSR7_DB4 _CAN0RXDSR7.Bits.DB4 -#define CAN0RXDSR7_DB5 _CAN0RXDSR7.Bits.DB5 -#define CAN0RXDSR7_DB6 _CAN0RXDSR7.Bits.DB6 -#define CAN0RXDSR7_DB7 _CAN0RXDSR7.Bits.DB7 -#define CAN0RXDSR7_DB _CAN0RXDSR7.MergedBits.grpDB - - -/*** CAN0RXDLR - MSCAN 0 Receive Data Length Register; 0x0000016C ***/ -typedef union { - byte Byte; - struct { - byte DLC0 :1; /* Data Length Code Bit 0 */ - byte DLC1 :1; /* Data Length Code Bit 1 */ - byte DLC2 :1; /* Data Length Code Bit 2 */ - byte DLC3 :1; /* Data Length Code Bit 3 */ - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpDLC :4; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} CAN0RXDLRSTR; -extern volatile CAN0RXDLRSTR _CAN0RXDLR @(REG_BASE + 0x0000016C); -#define CAN0RXDLR _CAN0RXDLR.Byte -#define CAN0RXDLR_DLC0 _CAN0RXDLR.Bits.DLC0 -#define CAN0RXDLR_DLC1 _CAN0RXDLR.Bits.DLC1 -#define CAN0RXDLR_DLC2 _CAN0RXDLR.Bits.DLC2 -#define CAN0RXDLR_DLC3 _CAN0RXDLR.Bits.DLC3 -#define CAN0RXDLR_DLC _CAN0RXDLR.MergedBits.grpDLC - - -/*** CAN0TXIDR0 - MSCAN 0 Transmit Identifier Register 0; 0x00000170 ***/ -typedef union { - byte Byte; - struct { - byte ID21 :1; /* Extended format identifier Bit 21 */ - byte ID22 :1; /* Extended format identifier Bit 22 */ - byte ID23 :1; /* Extended format identifier Bit 23 */ - byte ID24 :1; /* Extended format identifier Bit 24 */ - byte ID25 :1; /* Extended format identifier Bit 25 */ - byte ID26 :1; /* Extended format identifier Bit 26 */ - byte ID27 :1; /* Extended format identifier Bit 27 */ - byte ID28 :1; /* Extended format identifier Bit 28 */ - } Bits; - struct { - byte grpID_21 :8; - } MergedBits; -} CAN0TXIDR0STR; -extern volatile CAN0TXIDR0STR _CAN0TXIDR0 @(REG_BASE + 0x00000170); -#define CAN0TXIDR0 _CAN0TXIDR0.Byte -#define CAN0TXIDR0_ID21 _CAN0TXIDR0.Bits.ID21 -#define CAN0TXIDR0_ID22 _CAN0TXIDR0.Bits.ID22 -#define CAN0TXIDR0_ID23 _CAN0TXIDR0.Bits.ID23 -#define CAN0TXIDR0_ID24 _CAN0TXIDR0.Bits.ID24 -#define CAN0TXIDR0_ID25 _CAN0TXIDR0.Bits.ID25 -#define CAN0TXIDR0_ID26 _CAN0TXIDR0.Bits.ID26 -#define CAN0TXIDR0_ID27 _CAN0TXIDR0.Bits.ID27 -#define CAN0TXIDR0_ID28 _CAN0TXIDR0.Bits.ID28 -#define CAN0TXIDR0_ID_21 _CAN0TXIDR0.MergedBits.grpID_21 -#define CAN0TXIDR0_ID CAN0TXIDR0_ID_21 - - -/*** CAN0TXIDR1 - MSCAN 0 Transmit Identifier Register 1; 0x00000171 ***/ -typedef union { - byte Byte; - struct { - byte ID15 :1; /* Extended format identifier Bit 15 */ - byte ID16 :1; /* Extended format identifier Bit 16 */ - byte ID17 :1; /* Extended format identifier Bit 17 */ - byte IDE :1; /* ID Extended */ - byte SRR :1; /* Substitute Remote Request */ - byte ID18 :1; /* Extended format identifier Bit 18 */ - byte ID19 :1; /* Extended format identifier Bit 19 */ - byte ID20 :1; /* Extended format identifier Bit 20 */ - } Bits; - struct { - byte grpID_15 :3; - byte :1; - byte :1; - byte grpID_18 :3; - } MergedBits; -} CAN0TXIDR1STR; -extern volatile CAN0TXIDR1STR _CAN0TXIDR1 @(REG_BASE + 0x00000171); -#define CAN0TXIDR1 _CAN0TXIDR1.Byte -#define CAN0TXIDR1_ID15 _CAN0TXIDR1.Bits.ID15 -#define CAN0TXIDR1_ID16 _CAN0TXIDR1.Bits.ID16 -#define CAN0TXIDR1_ID17 _CAN0TXIDR1.Bits.ID17 -#define CAN0TXIDR1_IDE _CAN0TXIDR1.Bits.IDE -#define CAN0TXIDR1_SRR _CAN0TXIDR1.Bits.SRR -#define CAN0TXIDR1_ID18 _CAN0TXIDR1.Bits.ID18 -#define CAN0TXIDR1_ID19 _CAN0TXIDR1.Bits.ID19 -#define CAN0TXIDR1_ID20 _CAN0TXIDR1.Bits.ID20 -#define CAN0TXIDR1_ID_15 _CAN0TXIDR1.MergedBits.grpID_15 -#define CAN0TXIDR1_ID_18 _CAN0TXIDR1.MergedBits.grpID_18 -#define CAN0TXIDR1_ID CAN0TXIDR1_ID_15 - - -/*** CAN0TXIDR2 - MSCAN 0 Transmit Identifier Register 2; 0x00000172 ***/ -typedef union { - byte Byte; - struct { - byte ID7 :1; /* Extended format identifier Bit 7 */ - byte ID8 :1; /* Extended format identifier Bit 8 */ - byte ID9 :1; /* Extended format identifier Bit 9 */ - byte ID10 :1; /* Extended format identifier Bit 10 */ - byte ID11 :1; /* Extended format identifier Bit 11 */ - byte ID12 :1; /* Extended format identifier Bit 12 */ - byte ID13 :1; /* Extended format identifier Bit 13 */ - byte ID14 :1; /* Extended format identifier Bit 14 */ - } Bits; - struct { - byte grpID_7 :8; - } MergedBits; -} CAN0TXIDR2STR; -extern volatile CAN0TXIDR2STR _CAN0TXIDR2 @(REG_BASE + 0x00000172); -#define CAN0TXIDR2 _CAN0TXIDR2.Byte -#define CAN0TXIDR2_ID7 _CAN0TXIDR2.Bits.ID7 -#define CAN0TXIDR2_ID8 _CAN0TXIDR2.Bits.ID8 -#define CAN0TXIDR2_ID9 _CAN0TXIDR2.Bits.ID9 -#define CAN0TXIDR2_ID10 _CAN0TXIDR2.Bits.ID10 -#define CAN0TXIDR2_ID11 _CAN0TXIDR2.Bits.ID11 -#define CAN0TXIDR2_ID12 _CAN0TXIDR2.Bits.ID12 -#define CAN0TXIDR2_ID13 _CAN0TXIDR2.Bits.ID13 -#define CAN0TXIDR2_ID14 _CAN0TXIDR2.Bits.ID14 -#define CAN0TXIDR2_ID_7 _CAN0TXIDR2.MergedBits.grpID_7 -#define CAN0TXIDR2_ID CAN0TXIDR2_ID_7 - - -/*** CAN0TXIDR3 - MSCAN 0 Transmit Identifier Register 3; 0x00000173 ***/ -typedef union { - byte Byte; - struct { - byte RTR :1; /* Remote Transmission Request */ - byte ID0 :1; /* Extended format identifier Bit 0 */ - byte ID1 :1; /* Extended format identifier Bit 1 */ - byte ID2 :1; /* Extended format identifier Bit 2 */ - byte ID3 :1; /* Extended format identifier Bit 3 */ - byte ID4 :1; /* Extended format identifier Bit 4 */ - byte ID5 :1; /* Extended format identifier Bit 5 */ - byte ID6 :1; /* Extended format identifier Bit 6 */ - } Bits; - struct { - byte :1; - byte grpID :7; - } MergedBits; -} CAN0TXIDR3STR; -extern volatile CAN0TXIDR3STR _CAN0TXIDR3 @(REG_BASE + 0x00000173); -#define CAN0TXIDR3 _CAN0TXIDR3.Byte -#define CAN0TXIDR3_RTR _CAN0TXIDR3.Bits.RTR -#define CAN0TXIDR3_ID0 _CAN0TXIDR3.Bits.ID0 -#define CAN0TXIDR3_ID1 _CAN0TXIDR3.Bits.ID1 -#define CAN0TXIDR3_ID2 _CAN0TXIDR3.Bits.ID2 -#define CAN0TXIDR3_ID3 _CAN0TXIDR3.Bits.ID3 -#define CAN0TXIDR3_ID4 _CAN0TXIDR3.Bits.ID4 -#define CAN0TXIDR3_ID5 _CAN0TXIDR3.Bits.ID5 -#define CAN0TXIDR3_ID6 _CAN0TXIDR3.Bits.ID6 -#define CAN0TXIDR3_ID _CAN0TXIDR3.MergedBits.grpID - - -/*** CAN0TXDSR0 - MSCAN 0 Transmit Data Segment Register 0; 0x00000174 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN0TXDSR0STR; -extern volatile CAN0TXDSR0STR _CAN0TXDSR0 @(REG_BASE + 0x00000174); -#define CAN0TXDSR0 _CAN0TXDSR0.Byte -#define CAN0TXDSR0_DB0 _CAN0TXDSR0.Bits.DB0 -#define CAN0TXDSR0_DB1 _CAN0TXDSR0.Bits.DB1 -#define CAN0TXDSR0_DB2 _CAN0TXDSR0.Bits.DB2 -#define CAN0TXDSR0_DB3 _CAN0TXDSR0.Bits.DB3 -#define CAN0TXDSR0_DB4 _CAN0TXDSR0.Bits.DB4 -#define CAN0TXDSR0_DB5 _CAN0TXDSR0.Bits.DB5 -#define CAN0TXDSR0_DB6 _CAN0TXDSR0.Bits.DB6 -#define CAN0TXDSR0_DB7 _CAN0TXDSR0.Bits.DB7 -#define CAN0TXDSR0_DB _CAN0TXDSR0.MergedBits.grpDB - - -/*** CAN0TXDSR1 - MSCAN 0 Transmit Data Segment Register 1; 0x00000175 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN0TXDSR1STR; -extern volatile CAN0TXDSR1STR _CAN0TXDSR1 @(REG_BASE + 0x00000175); -#define CAN0TXDSR1 _CAN0TXDSR1.Byte -#define CAN0TXDSR1_DB0 _CAN0TXDSR1.Bits.DB0 -#define CAN0TXDSR1_DB1 _CAN0TXDSR1.Bits.DB1 -#define CAN0TXDSR1_DB2 _CAN0TXDSR1.Bits.DB2 -#define CAN0TXDSR1_DB3 _CAN0TXDSR1.Bits.DB3 -#define CAN0TXDSR1_DB4 _CAN0TXDSR1.Bits.DB4 -#define CAN0TXDSR1_DB5 _CAN0TXDSR1.Bits.DB5 -#define CAN0TXDSR1_DB6 _CAN0TXDSR1.Bits.DB6 -#define CAN0TXDSR1_DB7 _CAN0TXDSR1.Bits.DB7 -#define CAN0TXDSR1_DB _CAN0TXDSR1.MergedBits.grpDB - - -/*** CAN0TXDSR2 - MSCAN 0 Transmit Data Segment Register 2; 0x00000176 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN0TXDSR2STR; -extern volatile CAN0TXDSR2STR _CAN0TXDSR2 @(REG_BASE + 0x00000176); -#define CAN0TXDSR2 _CAN0TXDSR2.Byte -#define CAN0TXDSR2_DB0 _CAN0TXDSR2.Bits.DB0 -#define CAN0TXDSR2_DB1 _CAN0TXDSR2.Bits.DB1 -#define CAN0TXDSR2_DB2 _CAN0TXDSR2.Bits.DB2 -#define CAN0TXDSR2_DB3 _CAN0TXDSR2.Bits.DB3 -#define CAN0TXDSR2_DB4 _CAN0TXDSR2.Bits.DB4 -#define CAN0TXDSR2_DB5 _CAN0TXDSR2.Bits.DB5 -#define CAN0TXDSR2_DB6 _CAN0TXDSR2.Bits.DB6 -#define CAN0TXDSR2_DB7 _CAN0TXDSR2.Bits.DB7 -#define CAN0TXDSR2_DB _CAN0TXDSR2.MergedBits.grpDB - - -/*** CAN0TXDSR3 - MSCAN 0 Transmit Data Segment Register 3; 0x00000177 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN0TXDSR3STR; -extern volatile CAN0TXDSR3STR _CAN0TXDSR3 @(REG_BASE + 0x00000177); -#define CAN0TXDSR3 _CAN0TXDSR3.Byte -#define CAN0TXDSR3_DB0 _CAN0TXDSR3.Bits.DB0 -#define CAN0TXDSR3_DB1 _CAN0TXDSR3.Bits.DB1 -#define CAN0TXDSR3_DB2 _CAN0TXDSR3.Bits.DB2 -#define CAN0TXDSR3_DB3 _CAN0TXDSR3.Bits.DB3 -#define CAN0TXDSR3_DB4 _CAN0TXDSR3.Bits.DB4 -#define CAN0TXDSR3_DB5 _CAN0TXDSR3.Bits.DB5 -#define CAN0TXDSR3_DB6 _CAN0TXDSR3.Bits.DB6 -#define CAN0TXDSR3_DB7 _CAN0TXDSR3.Bits.DB7 -#define CAN0TXDSR3_DB _CAN0TXDSR3.MergedBits.grpDB - - -/*** CAN0TXDSR4 - MSCAN 0 Transmit Data Segment Register 4; 0x00000178 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN0TXDSR4STR; -extern volatile CAN0TXDSR4STR _CAN0TXDSR4 @(REG_BASE + 0x00000178); -#define CAN0TXDSR4 _CAN0TXDSR4.Byte -#define CAN0TXDSR4_DB0 _CAN0TXDSR4.Bits.DB0 -#define CAN0TXDSR4_DB1 _CAN0TXDSR4.Bits.DB1 -#define CAN0TXDSR4_DB2 _CAN0TXDSR4.Bits.DB2 -#define CAN0TXDSR4_DB3 _CAN0TXDSR4.Bits.DB3 -#define CAN0TXDSR4_DB4 _CAN0TXDSR4.Bits.DB4 -#define CAN0TXDSR4_DB5 _CAN0TXDSR4.Bits.DB5 -#define CAN0TXDSR4_DB6 _CAN0TXDSR4.Bits.DB6 -#define CAN0TXDSR4_DB7 _CAN0TXDSR4.Bits.DB7 -#define CAN0TXDSR4_DB _CAN0TXDSR4.MergedBits.grpDB - - -/*** CAN0TXDSR5 - MSCAN 0 Transmit Data Segment Register 5; 0x00000179 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN0TXDSR5STR; -extern volatile CAN0TXDSR5STR _CAN0TXDSR5 @(REG_BASE + 0x00000179); -#define CAN0TXDSR5 _CAN0TXDSR5.Byte -#define CAN0TXDSR5_DB0 _CAN0TXDSR5.Bits.DB0 -#define CAN0TXDSR5_DB1 _CAN0TXDSR5.Bits.DB1 -#define CAN0TXDSR5_DB2 _CAN0TXDSR5.Bits.DB2 -#define CAN0TXDSR5_DB3 _CAN0TXDSR5.Bits.DB3 -#define CAN0TXDSR5_DB4 _CAN0TXDSR5.Bits.DB4 -#define CAN0TXDSR5_DB5 _CAN0TXDSR5.Bits.DB5 -#define CAN0TXDSR5_DB6 _CAN0TXDSR5.Bits.DB6 -#define CAN0TXDSR5_DB7 _CAN0TXDSR5.Bits.DB7 -#define CAN0TXDSR5_DB _CAN0TXDSR5.MergedBits.grpDB - - -/*** CAN0TXDSR6 - MSCAN 0 Transmit Data Segment Register 6; 0x0000017A ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN0TXDSR6STR; -extern volatile CAN0TXDSR6STR _CAN0TXDSR6 @(REG_BASE + 0x0000017A); -#define CAN0TXDSR6 _CAN0TXDSR6.Byte -#define CAN0TXDSR6_DB0 _CAN0TXDSR6.Bits.DB0 -#define CAN0TXDSR6_DB1 _CAN0TXDSR6.Bits.DB1 -#define CAN0TXDSR6_DB2 _CAN0TXDSR6.Bits.DB2 -#define CAN0TXDSR6_DB3 _CAN0TXDSR6.Bits.DB3 -#define CAN0TXDSR6_DB4 _CAN0TXDSR6.Bits.DB4 -#define CAN0TXDSR6_DB5 _CAN0TXDSR6.Bits.DB5 -#define CAN0TXDSR6_DB6 _CAN0TXDSR6.Bits.DB6 -#define CAN0TXDSR6_DB7 _CAN0TXDSR6.Bits.DB7 -#define CAN0TXDSR6_DB _CAN0TXDSR6.MergedBits.grpDB - - -/*** CAN0TXDSR7 - MSCAN 0 Transmit Data Segment Register 7; 0x0000017B ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN0TXDSR7STR; -extern volatile CAN0TXDSR7STR _CAN0TXDSR7 @(REG_BASE + 0x0000017B); -#define CAN0TXDSR7 _CAN0TXDSR7.Byte -#define CAN0TXDSR7_DB0 _CAN0TXDSR7.Bits.DB0 -#define CAN0TXDSR7_DB1 _CAN0TXDSR7.Bits.DB1 -#define CAN0TXDSR7_DB2 _CAN0TXDSR7.Bits.DB2 -#define CAN0TXDSR7_DB3 _CAN0TXDSR7.Bits.DB3 -#define CAN0TXDSR7_DB4 _CAN0TXDSR7.Bits.DB4 -#define CAN0TXDSR7_DB5 _CAN0TXDSR7.Bits.DB5 -#define CAN0TXDSR7_DB6 _CAN0TXDSR7.Bits.DB6 -#define CAN0TXDSR7_DB7 _CAN0TXDSR7.Bits.DB7 -#define CAN0TXDSR7_DB _CAN0TXDSR7.MergedBits.grpDB - - -/*** CAN0TXDLR - MSCAN 0 Transmit Data Length Register; 0x0000017C ***/ -typedef union { - byte Byte; - struct { - byte DLC0 :1; /* Data Length Code Bit 0 */ - byte DLC1 :1; /* Data Length Code Bit 1 */ - byte DLC2 :1; /* Data Length Code Bit 2 */ - byte DLC3 :1; /* Data Length Code Bit 3 */ - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpDLC :4; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} CAN0TXDLRSTR; -extern volatile CAN0TXDLRSTR _CAN0TXDLR @(REG_BASE + 0x0000017C); -#define CAN0TXDLR _CAN0TXDLR.Byte -#define CAN0TXDLR_DLC0 _CAN0TXDLR.Bits.DLC0 -#define CAN0TXDLR_DLC1 _CAN0TXDLR.Bits.DLC1 -#define CAN0TXDLR_DLC2 _CAN0TXDLR.Bits.DLC2 -#define CAN0TXDLR_DLC3 _CAN0TXDLR.Bits.DLC3 -#define CAN0TXDLR_DLC _CAN0TXDLR.MergedBits.grpDLC - - -/*** CAN0TXTBPR - MSCAN 0 Transmit Buffer Priority; 0x0000017F ***/ -typedef union { - byte Byte; - struct { - byte PRIO0 :1; /* Transmit Buffer Priority Bit 0 */ - byte PRIO1 :1; /* Transmit Buffer Priority Bit 1 */ - byte PRIO2 :1; /* Transmit Buffer Priority Bit 2 */ - byte PRIO3 :1; /* Transmit Buffer Priority Bit 3 */ - byte PRIO4 :1; /* Transmit Buffer Priority Bit 4 */ - byte PRIO5 :1; /* Transmit Buffer Priority Bit 5 */ - byte PRIO6 :1; /* Transmit Buffer Priority Bit 6 */ - byte PRIO7 :1; /* Transmit Buffer Priority Bit 7 */ - } Bits; - struct { - byte grpPRIO :8; - } MergedBits; -} CAN0TXTBPRSTR; -extern volatile CAN0TXTBPRSTR _CAN0TXTBPR @(REG_BASE + 0x0000017F); -#define CAN0TXTBPR _CAN0TXTBPR.Byte -#define CAN0TXTBPR_PRIO0 _CAN0TXTBPR.Bits.PRIO0 -#define CAN0TXTBPR_PRIO1 _CAN0TXTBPR.Bits.PRIO1 -#define CAN0TXTBPR_PRIO2 _CAN0TXTBPR.Bits.PRIO2 -#define CAN0TXTBPR_PRIO3 _CAN0TXTBPR.Bits.PRIO3 -#define CAN0TXTBPR_PRIO4 _CAN0TXTBPR.Bits.PRIO4 -#define CAN0TXTBPR_PRIO5 _CAN0TXTBPR.Bits.PRIO5 -#define CAN0TXTBPR_PRIO6 _CAN0TXTBPR.Bits.PRIO6 -#define CAN0TXTBPR_PRIO7 _CAN0TXTBPR.Bits.PRIO7 -#define CAN0TXTBPR_PRIO _CAN0TXTBPR.MergedBits.grpPRIO - - -/*** CAN1CTL0 - MSCAN 1 Control 0 Register; 0x00000180 ***/ -typedef union { - byte Byte; - struct { - byte INITRQ :1; /* Initialization Mode Request */ - byte SLPRQ :1; /* Sleep Mode Request */ - byte WUPE :1; /* Wake-Up Enable */ - byte TIME :1; /* Timer Enable */ - byte SYNCH :1; /* Synchronized Status */ - byte CSWAI :1; /* CAN Stops in Wait Mode */ - byte RXACT :1; /* Receiver Active Status */ - byte RXFRM :1; /* Received Frame Flag */ - } Bits; -} CAN1CTL0STR; -extern volatile CAN1CTL0STR _CAN1CTL0 @(REG_BASE + 0x00000180); -#define CAN1CTL0 _CAN1CTL0.Byte -#define CAN1CTL0_INITRQ _CAN1CTL0.Bits.INITRQ -#define CAN1CTL0_SLPRQ _CAN1CTL0.Bits.SLPRQ -#define CAN1CTL0_WUPE _CAN1CTL0.Bits.WUPE -#define CAN1CTL0_TIME _CAN1CTL0.Bits.TIME -#define CAN1CTL0_SYNCH _CAN1CTL0.Bits.SYNCH -#define CAN1CTL0_CSWAI _CAN1CTL0.Bits.CSWAI -#define CAN1CTL0_RXACT _CAN1CTL0.Bits.RXACT -#define CAN1CTL0_RXFRM _CAN1CTL0.Bits.RXFRM - - -/*** CAN1CTL1 - MSCAN 1 Control 1 Register; 0x00000181 ***/ -typedef union { - byte Byte; - struct { - byte INITAK :1; /* Initialization Mode Acknowledge */ - byte SLPAK :1; /* Sleep Mode Acknowledge */ - byte WUPM :1; /* Wake-Up Mode */ - byte :1; - byte LISTEN :1; /* Listen Only Mode */ - byte LOOPB :1; /* Loop Back Self Test Mode */ - byte CLKSRC :1; /* MSCAN 1 Clock Source */ - byte CANE :1; /* MSCAN 1 Enable */ - } Bits; -} CAN1CTL1STR; -extern volatile CAN1CTL1STR _CAN1CTL1 @(REG_BASE + 0x00000181); -#define CAN1CTL1 _CAN1CTL1.Byte -#define CAN1CTL1_INITAK _CAN1CTL1.Bits.INITAK -#define CAN1CTL1_SLPAK _CAN1CTL1.Bits.SLPAK -#define CAN1CTL1_WUPM _CAN1CTL1.Bits.WUPM -#define CAN1CTL1_LISTEN _CAN1CTL1.Bits.LISTEN -#define CAN1CTL1_LOOPB _CAN1CTL1.Bits.LOOPB -#define CAN1CTL1_CLKSRC _CAN1CTL1.Bits.CLKSRC -#define CAN1CTL1_CANE _CAN1CTL1.Bits.CANE - - -/*** CAN1BTR0 - MSCAN 1 Bus Timing Register 0; 0x00000182 ***/ -typedef union { - byte Byte; - struct { - byte BRP0 :1; /* Baud Rate Prescaler 0 */ - byte BRP1 :1; /* Baud Rate Prescaler 1 */ - byte BRP2 :1; /* Baud Rate Prescaler 2 */ - byte BRP3 :1; /* Baud Rate Prescaler 3 */ - byte BRP4 :1; /* Baud Rate Prescaler 4 */ - byte BRP5 :1; /* Baud Rate Prescaler 5 */ - byte SJW0 :1; /* Synchronization Jump Width 0 */ - byte SJW1 :1; /* Synchronization Jump Width 1 */ - } Bits; - struct { - byte grpBRP :6; - byte grpSJW :2; - } MergedBits; -} CAN1BTR0STR; -extern volatile CAN1BTR0STR _CAN1BTR0 @(REG_BASE + 0x00000182); -#define CAN1BTR0 _CAN1BTR0.Byte -#define CAN1BTR0_BRP0 _CAN1BTR0.Bits.BRP0 -#define CAN1BTR0_BRP1 _CAN1BTR0.Bits.BRP1 -#define CAN1BTR0_BRP2 _CAN1BTR0.Bits.BRP2 -#define CAN1BTR0_BRP3 _CAN1BTR0.Bits.BRP3 -#define CAN1BTR0_BRP4 _CAN1BTR0.Bits.BRP4 -#define CAN1BTR0_BRP5 _CAN1BTR0.Bits.BRP5 -#define CAN1BTR0_SJW0 _CAN1BTR0.Bits.SJW0 -#define CAN1BTR0_SJW1 _CAN1BTR0.Bits.SJW1 -#define CAN1BTR0_BRP _CAN1BTR0.MergedBits.grpBRP -#define CAN1BTR0_SJW _CAN1BTR0.MergedBits.grpSJW - - -/*** CAN1BTR1 - MSCAN 1 Bus Timing Register 1; 0x00000183 ***/ -typedef union { - byte Byte; - struct { - byte TSEG10 :1; /* Time Segment 1 */ - byte TSEG11 :1; /* Time Segment 1 */ - byte TSEG12 :1; /* Time Segment 1 */ - byte TSEG13 :1; /* Time Segment 1 */ - byte TSEG20 :1; /* Time Segment 2 */ - byte TSEG21 :1; /* Time Segment 2 */ - byte TSEG22 :1; /* Time Segment 2 */ - byte SAMP :1; /* Sampling */ - } Bits; - struct { - byte grpTSEG_10 :4; - byte grpTSEG_20 :3; - byte :1; - } MergedBits; -} CAN1BTR1STR; -extern volatile CAN1BTR1STR _CAN1BTR1 @(REG_BASE + 0x00000183); -#define CAN1BTR1 _CAN1BTR1.Byte -#define CAN1BTR1_TSEG10 _CAN1BTR1.Bits.TSEG10 -#define CAN1BTR1_TSEG11 _CAN1BTR1.Bits.TSEG11 -#define CAN1BTR1_TSEG12 _CAN1BTR1.Bits.TSEG12 -#define CAN1BTR1_TSEG13 _CAN1BTR1.Bits.TSEG13 -#define CAN1BTR1_TSEG20 _CAN1BTR1.Bits.TSEG20 -#define CAN1BTR1_TSEG21 _CAN1BTR1.Bits.TSEG21 -#define CAN1BTR1_TSEG22 _CAN1BTR1.Bits.TSEG22 -#define CAN1BTR1_SAMP _CAN1BTR1.Bits.SAMP -#define CAN1BTR1_TSEG_10 _CAN1BTR1.MergedBits.grpTSEG_10 -#define CAN1BTR1_TSEG_20 _CAN1BTR1.MergedBits.grpTSEG_20 -#define CAN1BTR1_TSEG CAN1BTR1_TSEG_10 - - -/*** CAN1RFLG - MSCAN 1 Receiver Flag Register; 0x00000184 ***/ -typedef union { - byte Byte; - struct { - byte RXF :1; /* Receive Buffer Full */ - byte OVRIF :1; /* Overrun Interrupt Flag */ - byte TSTAT0 :1; /* Transmitter Status Bit 0 */ - byte TSTAT1 :1; /* Transmitter Status Bit 1 */ - byte RSTAT0 :1; /* Receiver Status Bit 0 */ - byte RSTAT1 :1; /* Receiver Status Bit 1 */ - byte CSCIF :1; /* CAN Status Change Interrupt Flag */ - byte WUPIF :1; /* Wake-up Interrupt Flag */ - } Bits; - struct { - byte :1; - byte :1; - byte grpTSTAT :2; - byte grpRSTAT :2; - byte :1; - byte :1; - } MergedBits; -} CAN1RFLGSTR; -extern volatile CAN1RFLGSTR _CAN1RFLG @(REG_BASE + 0x00000184); -#define CAN1RFLG _CAN1RFLG.Byte -#define CAN1RFLG_RXF _CAN1RFLG.Bits.RXF -#define CAN1RFLG_OVRIF _CAN1RFLG.Bits.OVRIF -#define CAN1RFLG_TSTAT0 _CAN1RFLG.Bits.TSTAT0 -#define CAN1RFLG_TSTAT1 _CAN1RFLG.Bits.TSTAT1 -#define CAN1RFLG_RSTAT0 _CAN1RFLG.Bits.RSTAT0 -#define CAN1RFLG_RSTAT1 _CAN1RFLG.Bits.RSTAT1 -#define CAN1RFLG_CSCIF _CAN1RFLG.Bits.CSCIF -#define CAN1RFLG_WUPIF _CAN1RFLG.Bits.WUPIF -#define CAN1RFLG_TSTAT _CAN1RFLG.MergedBits.grpTSTAT -#define CAN1RFLG_RSTAT _CAN1RFLG.MergedBits.grpRSTAT - - -/*** CAN1RIER - MSCAN 1 Receiver Interrupt Enable Register; 0x00000185 ***/ -typedef union { - byte Byte; - struct { - byte RXFIE :1; /* Receiver Full Interrupt Enable */ - byte OVRIE :1; /* Overrun Interrupt Enable */ - byte TSTATE0 :1; /* Transmitter Status Change Enable 0 */ - byte TSTATE1 :1; /* Transmitter Status Change Enable 1 */ - byte RSTATE0 :1; /* Receiver Status Change Enable 0 */ - byte RSTATE1 :1; /* Receiver Status Change Enable 1 */ - byte CSCIE :1; /* CAN Status Change Interrupt Enable */ - byte WUPIE :1; /* Wake-up Interrupt Enable */ - } Bits; - struct { - byte :1; - byte :1; - byte grpTSTATE :2; - byte grpRSTATE :2; - byte :1; - byte :1; - } MergedBits; -} CAN1RIERSTR; -extern volatile CAN1RIERSTR _CAN1RIER @(REG_BASE + 0x00000185); -#define CAN1RIER _CAN1RIER.Byte -#define CAN1RIER_RXFIE _CAN1RIER.Bits.RXFIE -#define CAN1RIER_OVRIE _CAN1RIER.Bits.OVRIE -#define CAN1RIER_TSTATE0 _CAN1RIER.Bits.TSTATE0 -#define CAN1RIER_TSTATE1 _CAN1RIER.Bits.TSTATE1 -#define CAN1RIER_RSTATE0 _CAN1RIER.Bits.RSTATE0 -#define CAN1RIER_RSTATE1 _CAN1RIER.Bits.RSTATE1 -#define CAN1RIER_CSCIE _CAN1RIER.Bits.CSCIE -#define CAN1RIER_WUPIE _CAN1RIER.Bits.WUPIE -#define CAN1RIER_TSTATE _CAN1RIER.MergedBits.grpTSTATE -#define CAN1RIER_RSTATE _CAN1RIER.MergedBits.grpRSTATE - - -/*** CAN1TFLG - MSCAN 1 Transmitter Flag Register; 0x00000186 ***/ -typedef union { - byte Byte; - struct { - byte TXE0 :1; /* Transmitter Buffer Empty 0 */ - byte TXE1 :1; /* Transmitter Buffer Empty 1 */ - byte TXE2 :1; /* Transmitter Buffer Empty 2 */ - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpTXE :3; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} CAN1TFLGSTR; -extern volatile CAN1TFLGSTR _CAN1TFLG @(REG_BASE + 0x00000186); -#define CAN1TFLG _CAN1TFLG.Byte -#define CAN1TFLG_TXE0 _CAN1TFLG.Bits.TXE0 -#define CAN1TFLG_TXE1 _CAN1TFLG.Bits.TXE1 -#define CAN1TFLG_TXE2 _CAN1TFLG.Bits.TXE2 -#define CAN1TFLG_TXE _CAN1TFLG.MergedBits.grpTXE - - -/*** CAN1TIER - MSCAN 1 Transmitter Interrupt Enable Register; 0x00000187 ***/ -typedef union { - byte Byte; - struct { - byte TXEIE0 :1; /* Transmitter Empty Interrupt Enable 0 */ - byte TXEIE1 :1; /* Transmitter Empty Interrupt Enable 1 */ - byte TXEIE2 :1; /* Transmitter Empty Interrupt Enable 2 */ - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpTXEIE :3; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} CAN1TIERSTR; -extern volatile CAN1TIERSTR _CAN1TIER @(REG_BASE + 0x00000187); -#define CAN1TIER _CAN1TIER.Byte -#define CAN1TIER_TXEIE0 _CAN1TIER.Bits.TXEIE0 -#define CAN1TIER_TXEIE1 _CAN1TIER.Bits.TXEIE1 -#define CAN1TIER_TXEIE2 _CAN1TIER.Bits.TXEIE2 -#define CAN1TIER_TXEIE _CAN1TIER.MergedBits.grpTXEIE - - -/*** CAN1TARQ - MSCAN 1 Transmitter Message Abort Request; 0x00000188 ***/ -typedef union { - byte Byte; - struct { - byte ABTRQ0 :1; /* Abort Request 0 */ - byte ABTRQ1 :1; /* Abort Request 1 */ - byte ABTRQ2 :1; /* Abort Request 2 */ - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpABTRQ :3; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} CAN1TARQSTR; -extern volatile CAN1TARQSTR _CAN1TARQ @(REG_BASE + 0x00000188); -#define CAN1TARQ _CAN1TARQ.Byte -#define CAN1TARQ_ABTRQ0 _CAN1TARQ.Bits.ABTRQ0 -#define CAN1TARQ_ABTRQ1 _CAN1TARQ.Bits.ABTRQ1 -#define CAN1TARQ_ABTRQ2 _CAN1TARQ.Bits.ABTRQ2 -#define CAN1TARQ_ABTRQ _CAN1TARQ.MergedBits.grpABTRQ - - -/*** CAN1TAAK - MSCAN 1 Transmitter Message Abort Control; 0x00000189 ***/ -typedef union { - byte Byte; - struct { - byte ABTAK0 :1; /* Abort Acknowledge 0 */ - byte ABTAK1 :1; /* Abort Acknowledge 1 */ - byte ABTAK2 :1; /* Abort Acknowledge 2 */ - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpABTAK :3; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} CAN1TAAKSTR; -extern volatile CAN1TAAKSTR _CAN1TAAK @(REG_BASE + 0x00000189); -#define CAN1TAAK _CAN1TAAK.Byte -#define CAN1TAAK_ABTAK0 _CAN1TAAK.Bits.ABTAK0 -#define CAN1TAAK_ABTAK1 _CAN1TAAK.Bits.ABTAK1 -#define CAN1TAAK_ABTAK2 _CAN1TAAK.Bits.ABTAK2 -#define CAN1TAAK_ABTAK _CAN1TAAK.MergedBits.grpABTAK - - -/*** CAN1TBSEL - MSCAN 1 Transmit Buffer Selection; 0x0000018A ***/ -typedef union { - byte Byte; - struct { - byte TX0 :1; /* Transmit Buffer Select 0 */ - byte TX1 :1; /* Transmit Buffer Select 1 */ - byte TX2 :1; /* Transmit Buffer Select 2 */ - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpTX :3; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} CAN1TBSELSTR; -extern volatile CAN1TBSELSTR _CAN1TBSEL @(REG_BASE + 0x0000018A); -#define CAN1TBSEL _CAN1TBSEL.Byte -#define CAN1TBSEL_TX0 _CAN1TBSEL.Bits.TX0 -#define CAN1TBSEL_TX1 _CAN1TBSEL.Bits.TX1 -#define CAN1TBSEL_TX2 _CAN1TBSEL.Bits.TX2 -#define CAN1TBSEL_TX _CAN1TBSEL.MergedBits.grpTX - - -/*** CAN1IDAC - MSCAN 1 Identifier Acceptance Control Register; 0x0000018B ***/ -typedef union { - byte Byte; - struct { - byte IDHIT0 :1; /* Identifier Acceptance Hit Indicator 0 */ - byte IDHIT1 :1; /* Identifier Acceptance Hit Indicator 1 */ - byte IDHIT2 :1; /* Identifier Acceptance Hit Indicator 2 */ - byte :1; - byte IDAM0 :1; /* Identifier Acceptance Mode 0 */ - byte IDAM1 :1; /* Identifier Acceptance Mode 1 */ - byte :1; - byte :1; - } Bits; - struct { - byte grpIDHIT :3; - byte :1; - byte grpIDAM :2; - byte :1; - byte :1; - } MergedBits; -} CAN1IDACSTR; -extern volatile CAN1IDACSTR _CAN1IDAC @(REG_BASE + 0x0000018B); -#define CAN1IDAC _CAN1IDAC.Byte -#define CAN1IDAC_IDHIT0 _CAN1IDAC.Bits.IDHIT0 -#define CAN1IDAC_IDHIT1 _CAN1IDAC.Bits.IDHIT1 -#define CAN1IDAC_IDHIT2 _CAN1IDAC.Bits.IDHIT2 -#define CAN1IDAC_IDAM0 _CAN1IDAC.Bits.IDAM0 -#define CAN1IDAC_IDAM1 _CAN1IDAC.Bits.IDAM1 -#define CAN1IDAC_IDHIT _CAN1IDAC.MergedBits.grpIDHIT -#define CAN1IDAC_IDAM _CAN1IDAC.MergedBits.grpIDAM - - -/*** CAN1RXERR - MSCAN 1 Receive Error Counter Register; 0x0000018E ***/ -typedef union { - byte Byte; - struct { - byte RXERR0 :1; /* Bit 0 */ - byte RXERR1 :1; /* Bit 1 */ - byte RXERR2 :1; /* Bit 2 */ - byte RXERR3 :1; /* Bit 3 */ - byte RXERR4 :1; /* Bit 4 */ - byte RXERR5 :1; /* Bit 5 */ - byte RXERR6 :1; /* Bit 6 */ - byte RXERR7 :1; /* Bit 7 */ - } Bits; - struct { - byte grpRXERR :8; - } MergedBits; -} CAN1RXERRSTR; -extern volatile CAN1RXERRSTR _CAN1RXERR @(REG_BASE + 0x0000018E); -#define CAN1RXERR _CAN1RXERR.Byte -#define CAN1RXERR_RXERR0 _CAN1RXERR.Bits.RXERR0 -#define CAN1RXERR_RXERR1 _CAN1RXERR.Bits.RXERR1 -#define CAN1RXERR_RXERR2 _CAN1RXERR.Bits.RXERR2 -#define CAN1RXERR_RXERR3 _CAN1RXERR.Bits.RXERR3 -#define CAN1RXERR_RXERR4 _CAN1RXERR.Bits.RXERR4 -#define CAN1RXERR_RXERR5 _CAN1RXERR.Bits.RXERR5 -#define CAN1RXERR_RXERR6 _CAN1RXERR.Bits.RXERR6 -#define CAN1RXERR_RXERR7 _CAN1RXERR.Bits.RXERR7 -#define CAN1RXERR_RXERR _CAN1RXERR.MergedBits.grpRXERR - - -/*** CAN1TXERR - MSCAN 1 Transmit Error Counter Register; 0x0000018F ***/ -typedef union { - byte Byte; - struct { - byte TXERR0 :1; /* Bit 0 */ - byte TXERR1 :1; /* Bit 1 */ - byte TXERR2 :1; /* Bit 2 */ - byte TXERR3 :1; /* Bit 3 */ - byte TXERR4 :1; /* Bit 4 */ - byte TXERR5 :1; /* Bit 5 */ - byte TXERR6 :1; /* Bit 6 */ - byte TXERR7 :1; /* Bit 7 */ - } Bits; - struct { - byte grpTXERR :8; - } MergedBits; -} CAN1TXERRSTR; -extern volatile CAN1TXERRSTR _CAN1TXERR @(REG_BASE + 0x0000018F); -#define CAN1TXERR _CAN1TXERR.Byte -#define CAN1TXERR_TXERR0 _CAN1TXERR.Bits.TXERR0 -#define CAN1TXERR_TXERR1 _CAN1TXERR.Bits.TXERR1 -#define CAN1TXERR_TXERR2 _CAN1TXERR.Bits.TXERR2 -#define CAN1TXERR_TXERR3 _CAN1TXERR.Bits.TXERR3 -#define CAN1TXERR_TXERR4 _CAN1TXERR.Bits.TXERR4 -#define CAN1TXERR_TXERR5 _CAN1TXERR.Bits.TXERR5 -#define CAN1TXERR_TXERR6 _CAN1TXERR.Bits.TXERR6 -#define CAN1TXERR_TXERR7 _CAN1TXERR.Bits.TXERR7 -#define CAN1TXERR_TXERR _CAN1TXERR.MergedBits.grpTXERR - - -/*** CAN1IDAR0 - MSCAN 1 Identifier Acceptance Register 0; 0x00000190 ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CAN1IDAR0STR; -extern volatile CAN1IDAR0STR _CAN1IDAR0 @(REG_BASE + 0x00000190); -#define CAN1IDAR0 _CAN1IDAR0.Byte -#define CAN1IDAR0_AC0 _CAN1IDAR0.Bits.AC0 -#define CAN1IDAR0_AC1 _CAN1IDAR0.Bits.AC1 -#define CAN1IDAR0_AC2 _CAN1IDAR0.Bits.AC2 -#define CAN1IDAR0_AC3 _CAN1IDAR0.Bits.AC3 -#define CAN1IDAR0_AC4 _CAN1IDAR0.Bits.AC4 -#define CAN1IDAR0_AC5 _CAN1IDAR0.Bits.AC5 -#define CAN1IDAR0_AC6 _CAN1IDAR0.Bits.AC6 -#define CAN1IDAR0_AC7 _CAN1IDAR0.Bits.AC7 -#define CAN1IDAR0_AC _CAN1IDAR0.MergedBits.grpAC - - -/*** CAN1IDAR1 - MSCAN 1 Identifier Acceptance Register 1; 0x00000191 ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CAN1IDAR1STR; -extern volatile CAN1IDAR1STR _CAN1IDAR1 @(REG_BASE + 0x00000191); -#define CAN1IDAR1 _CAN1IDAR1.Byte -#define CAN1IDAR1_AC0 _CAN1IDAR1.Bits.AC0 -#define CAN1IDAR1_AC1 _CAN1IDAR1.Bits.AC1 -#define CAN1IDAR1_AC2 _CAN1IDAR1.Bits.AC2 -#define CAN1IDAR1_AC3 _CAN1IDAR1.Bits.AC3 -#define CAN1IDAR1_AC4 _CAN1IDAR1.Bits.AC4 -#define CAN1IDAR1_AC5 _CAN1IDAR1.Bits.AC5 -#define CAN1IDAR1_AC6 _CAN1IDAR1.Bits.AC6 -#define CAN1IDAR1_AC7 _CAN1IDAR1.Bits.AC7 -#define CAN1IDAR1_AC _CAN1IDAR1.MergedBits.grpAC - - -/*** CAN1IDAR2 - MSCAN 1 Identifier Acceptance Register 2; 0x00000192 ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CAN1IDAR2STR; -extern volatile CAN1IDAR2STR _CAN1IDAR2 @(REG_BASE + 0x00000192); -#define CAN1IDAR2 _CAN1IDAR2.Byte -#define CAN1IDAR2_AC0 _CAN1IDAR2.Bits.AC0 -#define CAN1IDAR2_AC1 _CAN1IDAR2.Bits.AC1 -#define CAN1IDAR2_AC2 _CAN1IDAR2.Bits.AC2 -#define CAN1IDAR2_AC3 _CAN1IDAR2.Bits.AC3 -#define CAN1IDAR2_AC4 _CAN1IDAR2.Bits.AC4 -#define CAN1IDAR2_AC5 _CAN1IDAR2.Bits.AC5 -#define CAN1IDAR2_AC6 _CAN1IDAR2.Bits.AC6 -#define CAN1IDAR2_AC7 _CAN1IDAR2.Bits.AC7 -#define CAN1IDAR2_AC _CAN1IDAR2.MergedBits.grpAC - - -/*** CAN1IDAR3 - MSCAN 1 Identifier Acceptance Register 3; 0x00000193 ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CAN1IDAR3STR; -extern volatile CAN1IDAR3STR _CAN1IDAR3 @(REG_BASE + 0x00000193); -#define CAN1IDAR3 _CAN1IDAR3.Byte -#define CAN1IDAR3_AC0 _CAN1IDAR3.Bits.AC0 -#define CAN1IDAR3_AC1 _CAN1IDAR3.Bits.AC1 -#define CAN1IDAR3_AC2 _CAN1IDAR3.Bits.AC2 -#define CAN1IDAR3_AC3 _CAN1IDAR3.Bits.AC3 -#define CAN1IDAR3_AC4 _CAN1IDAR3.Bits.AC4 -#define CAN1IDAR3_AC5 _CAN1IDAR3.Bits.AC5 -#define CAN1IDAR3_AC6 _CAN1IDAR3.Bits.AC6 -#define CAN1IDAR3_AC7 _CAN1IDAR3.Bits.AC7 -#define CAN1IDAR3_AC _CAN1IDAR3.MergedBits.grpAC - - -/*** CAN1IDMR0 - MSCAN 1 Identifier Mask Register 0; 0x00000194 ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CAN1IDMR0STR; -extern volatile CAN1IDMR0STR _CAN1IDMR0 @(REG_BASE + 0x00000194); -#define CAN1IDMR0 _CAN1IDMR0.Byte -#define CAN1IDMR0_AM0 _CAN1IDMR0.Bits.AM0 -#define CAN1IDMR0_AM1 _CAN1IDMR0.Bits.AM1 -#define CAN1IDMR0_AM2 _CAN1IDMR0.Bits.AM2 -#define CAN1IDMR0_AM3 _CAN1IDMR0.Bits.AM3 -#define CAN1IDMR0_AM4 _CAN1IDMR0.Bits.AM4 -#define CAN1IDMR0_AM5 _CAN1IDMR0.Bits.AM5 -#define CAN1IDMR0_AM6 _CAN1IDMR0.Bits.AM6 -#define CAN1IDMR0_AM7 _CAN1IDMR0.Bits.AM7 -#define CAN1IDMR0_AM _CAN1IDMR0.MergedBits.grpAM - - -/*** CAN1IDMR1 - MSCAN 1 Identifier Mask Register 1; 0x00000195 ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CAN1IDMR1STR; -extern volatile CAN1IDMR1STR _CAN1IDMR1 @(REG_BASE + 0x00000195); -#define CAN1IDMR1 _CAN1IDMR1.Byte -#define CAN1IDMR1_AM0 _CAN1IDMR1.Bits.AM0 -#define CAN1IDMR1_AM1 _CAN1IDMR1.Bits.AM1 -#define CAN1IDMR1_AM2 _CAN1IDMR1.Bits.AM2 -#define CAN1IDMR1_AM3 _CAN1IDMR1.Bits.AM3 -#define CAN1IDMR1_AM4 _CAN1IDMR1.Bits.AM4 -#define CAN1IDMR1_AM5 _CAN1IDMR1.Bits.AM5 -#define CAN1IDMR1_AM6 _CAN1IDMR1.Bits.AM6 -#define CAN1IDMR1_AM7 _CAN1IDMR1.Bits.AM7 -#define CAN1IDMR1_AM _CAN1IDMR1.MergedBits.grpAM - - -/*** CAN1IDMR2 - MSCAN 1 Identifier Mask Register 2; 0x00000196 ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CAN1IDMR2STR; -extern volatile CAN1IDMR2STR _CAN1IDMR2 @(REG_BASE + 0x00000196); -#define CAN1IDMR2 _CAN1IDMR2.Byte -#define CAN1IDMR2_AM0 _CAN1IDMR2.Bits.AM0 -#define CAN1IDMR2_AM1 _CAN1IDMR2.Bits.AM1 -#define CAN1IDMR2_AM2 _CAN1IDMR2.Bits.AM2 -#define CAN1IDMR2_AM3 _CAN1IDMR2.Bits.AM3 -#define CAN1IDMR2_AM4 _CAN1IDMR2.Bits.AM4 -#define CAN1IDMR2_AM5 _CAN1IDMR2.Bits.AM5 -#define CAN1IDMR2_AM6 _CAN1IDMR2.Bits.AM6 -#define CAN1IDMR2_AM7 _CAN1IDMR2.Bits.AM7 -#define CAN1IDMR2_AM _CAN1IDMR2.MergedBits.grpAM - - -/*** CAN1IDMR3 - MSCAN 1 Identifier Mask Register 3; 0x00000197 ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CAN1IDMR3STR; -extern volatile CAN1IDMR3STR _CAN1IDMR3 @(REG_BASE + 0x00000197); -#define CAN1IDMR3 _CAN1IDMR3.Byte -#define CAN1IDMR3_AM0 _CAN1IDMR3.Bits.AM0 -#define CAN1IDMR3_AM1 _CAN1IDMR3.Bits.AM1 -#define CAN1IDMR3_AM2 _CAN1IDMR3.Bits.AM2 -#define CAN1IDMR3_AM3 _CAN1IDMR3.Bits.AM3 -#define CAN1IDMR3_AM4 _CAN1IDMR3.Bits.AM4 -#define CAN1IDMR3_AM5 _CAN1IDMR3.Bits.AM5 -#define CAN1IDMR3_AM6 _CAN1IDMR3.Bits.AM6 -#define CAN1IDMR3_AM7 _CAN1IDMR3.Bits.AM7 -#define CAN1IDMR3_AM _CAN1IDMR3.MergedBits.grpAM - - -/*** CAN1IDAR4 - MSCAN 1 Identifier Acceptance Register 4; 0x00000198 ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CAN1IDAR4STR; -extern volatile CAN1IDAR4STR _CAN1IDAR4 @(REG_BASE + 0x00000198); -#define CAN1IDAR4 _CAN1IDAR4.Byte -#define CAN1IDAR4_AC0 _CAN1IDAR4.Bits.AC0 -#define CAN1IDAR4_AC1 _CAN1IDAR4.Bits.AC1 -#define CAN1IDAR4_AC2 _CAN1IDAR4.Bits.AC2 -#define CAN1IDAR4_AC3 _CAN1IDAR4.Bits.AC3 -#define CAN1IDAR4_AC4 _CAN1IDAR4.Bits.AC4 -#define CAN1IDAR4_AC5 _CAN1IDAR4.Bits.AC5 -#define CAN1IDAR4_AC6 _CAN1IDAR4.Bits.AC6 -#define CAN1IDAR4_AC7 _CAN1IDAR4.Bits.AC7 -#define CAN1IDAR4_AC _CAN1IDAR4.MergedBits.grpAC - - -/*** CAN1IDAR5 - MSCAN 1 Identifier Acceptance Register 5; 0x00000199 ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CAN1IDAR5STR; -extern volatile CAN1IDAR5STR _CAN1IDAR5 @(REG_BASE + 0x00000199); -#define CAN1IDAR5 _CAN1IDAR5.Byte -#define CAN1IDAR5_AC0 _CAN1IDAR5.Bits.AC0 -#define CAN1IDAR5_AC1 _CAN1IDAR5.Bits.AC1 -#define CAN1IDAR5_AC2 _CAN1IDAR5.Bits.AC2 -#define CAN1IDAR5_AC3 _CAN1IDAR5.Bits.AC3 -#define CAN1IDAR5_AC4 _CAN1IDAR5.Bits.AC4 -#define CAN1IDAR5_AC5 _CAN1IDAR5.Bits.AC5 -#define CAN1IDAR5_AC6 _CAN1IDAR5.Bits.AC6 -#define CAN1IDAR5_AC7 _CAN1IDAR5.Bits.AC7 -#define CAN1IDAR5_AC _CAN1IDAR5.MergedBits.grpAC - - -/*** CAN1IDAR6 - MSCAN 1 Identifier Acceptance Register 6; 0x0000019A ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CAN1IDAR6STR; -extern volatile CAN1IDAR6STR _CAN1IDAR6 @(REG_BASE + 0x0000019A); -#define CAN1IDAR6 _CAN1IDAR6.Byte -#define CAN1IDAR6_AC0 _CAN1IDAR6.Bits.AC0 -#define CAN1IDAR6_AC1 _CAN1IDAR6.Bits.AC1 -#define CAN1IDAR6_AC2 _CAN1IDAR6.Bits.AC2 -#define CAN1IDAR6_AC3 _CAN1IDAR6.Bits.AC3 -#define CAN1IDAR6_AC4 _CAN1IDAR6.Bits.AC4 -#define CAN1IDAR6_AC5 _CAN1IDAR6.Bits.AC5 -#define CAN1IDAR6_AC6 _CAN1IDAR6.Bits.AC6 -#define CAN1IDAR6_AC7 _CAN1IDAR6.Bits.AC7 -#define CAN1IDAR6_AC _CAN1IDAR6.MergedBits.grpAC - - -/*** CAN1IDAR7 - MSCAN 1 Identifier Acceptance Register 7; 0x0000019B ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CAN1IDAR7STR; -extern volatile CAN1IDAR7STR _CAN1IDAR7 @(REG_BASE + 0x0000019B); -#define CAN1IDAR7 _CAN1IDAR7.Byte -#define CAN1IDAR7_AC0 _CAN1IDAR7.Bits.AC0 -#define CAN1IDAR7_AC1 _CAN1IDAR7.Bits.AC1 -#define CAN1IDAR7_AC2 _CAN1IDAR7.Bits.AC2 -#define CAN1IDAR7_AC3 _CAN1IDAR7.Bits.AC3 -#define CAN1IDAR7_AC4 _CAN1IDAR7.Bits.AC4 -#define CAN1IDAR7_AC5 _CAN1IDAR7.Bits.AC5 -#define CAN1IDAR7_AC6 _CAN1IDAR7.Bits.AC6 -#define CAN1IDAR7_AC7 _CAN1IDAR7.Bits.AC7 -#define CAN1IDAR7_AC _CAN1IDAR7.MergedBits.grpAC - - -/*** CAN1IDMR4 - MSCAN 1 Identifier Mask Register 4; 0x0000019C ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CAN1IDMR4STR; -extern volatile CAN1IDMR4STR _CAN1IDMR4 @(REG_BASE + 0x0000019C); -#define CAN1IDMR4 _CAN1IDMR4.Byte -#define CAN1IDMR4_AM0 _CAN1IDMR4.Bits.AM0 -#define CAN1IDMR4_AM1 _CAN1IDMR4.Bits.AM1 -#define CAN1IDMR4_AM2 _CAN1IDMR4.Bits.AM2 -#define CAN1IDMR4_AM3 _CAN1IDMR4.Bits.AM3 -#define CAN1IDMR4_AM4 _CAN1IDMR4.Bits.AM4 -#define CAN1IDMR4_AM5 _CAN1IDMR4.Bits.AM5 -#define CAN1IDMR4_AM6 _CAN1IDMR4.Bits.AM6 -#define CAN1IDMR4_AM7 _CAN1IDMR4.Bits.AM7 -#define CAN1IDMR4_AM _CAN1IDMR4.MergedBits.grpAM - - -/*** CAN1IDMR5 - MSCAN 1 Identifier Mask Register 5; 0x0000019D ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CAN1IDMR5STR; -extern volatile CAN1IDMR5STR _CAN1IDMR5 @(REG_BASE + 0x0000019D); -#define CAN1IDMR5 _CAN1IDMR5.Byte -#define CAN1IDMR5_AM0 _CAN1IDMR5.Bits.AM0 -#define CAN1IDMR5_AM1 _CAN1IDMR5.Bits.AM1 -#define CAN1IDMR5_AM2 _CAN1IDMR5.Bits.AM2 -#define CAN1IDMR5_AM3 _CAN1IDMR5.Bits.AM3 -#define CAN1IDMR5_AM4 _CAN1IDMR5.Bits.AM4 -#define CAN1IDMR5_AM5 _CAN1IDMR5.Bits.AM5 -#define CAN1IDMR5_AM6 _CAN1IDMR5.Bits.AM6 -#define CAN1IDMR5_AM7 _CAN1IDMR5.Bits.AM7 -#define CAN1IDMR5_AM _CAN1IDMR5.MergedBits.grpAM - - -/*** CAN1IDMR6 - MSCAN 1 Identifier Mask Register 6; 0x0000019E ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CAN1IDMR6STR; -extern volatile CAN1IDMR6STR _CAN1IDMR6 @(REG_BASE + 0x0000019E); -#define CAN1IDMR6 _CAN1IDMR6.Byte -#define CAN1IDMR6_AM0 _CAN1IDMR6.Bits.AM0 -#define CAN1IDMR6_AM1 _CAN1IDMR6.Bits.AM1 -#define CAN1IDMR6_AM2 _CAN1IDMR6.Bits.AM2 -#define CAN1IDMR6_AM3 _CAN1IDMR6.Bits.AM3 -#define CAN1IDMR6_AM4 _CAN1IDMR6.Bits.AM4 -#define CAN1IDMR6_AM5 _CAN1IDMR6.Bits.AM5 -#define CAN1IDMR6_AM6 _CAN1IDMR6.Bits.AM6 -#define CAN1IDMR6_AM7 _CAN1IDMR6.Bits.AM7 -#define CAN1IDMR6_AM _CAN1IDMR6.MergedBits.grpAM - - -/*** CAN1IDMR7 - MSCAN 1 Identifier Mask Register 7; 0x0000019F ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CAN1IDMR7STR; -extern volatile CAN1IDMR7STR _CAN1IDMR7 @(REG_BASE + 0x0000019F); -#define CAN1IDMR7 _CAN1IDMR7.Byte -#define CAN1IDMR7_AM0 _CAN1IDMR7.Bits.AM0 -#define CAN1IDMR7_AM1 _CAN1IDMR7.Bits.AM1 -#define CAN1IDMR7_AM2 _CAN1IDMR7.Bits.AM2 -#define CAN1IDMR7_AM3 _CAN1IDMR7.Bits.AM3 -#define CAN1IDMR7_AM4 _CAN1IDMR7.Bits.AM4 -#define CAN1IDMR7_AM5 _CAN1IDMR7.Bits.AM5 -#define CAN1IDMR7_AM6 _CAN1IDMR7.Bits.AM6 -#define CAN1IDMR7_AM7 _CAN1IDMR7.Bits.AM7 -#define CAN1IDMR7_AM _CAN1IDMR7.MergedBits.grpAM - - -/*** CAN1RXIDR0 - MSCAN 1 Receive Identifier Register 0; 0x000001A0 ***/ -typedef union { - byte Byte; - struct { - byte ID21 :1; /* Extended format identifier Bit 21 */ - byte ID22 :1; /* Extended format identifier Bit 22 */ - byte ID23 :1; /* Extended format identifier Bit 23 */ - byte ID24 :1; /* Extended format identifier Bit 24 */ - byte ID25 :1; /* Extended format identifier Bit 25 */ - byte ID26 :1; /* Extended format identifier Bit 26 */ - byte ID27 :1; /* Extended format identifier Bit 27 */ - byte ID28 :1; /* Extended format identifier Bit 28 */ - } Bits; - struct { - byte grpID_21 :8; - } MergedBits; -} CAN1RXIDR0STR; -extern volatile CAN1RXIDR0STR _CAN1RXIDR0 @(REG_BASE + 0x000001A0); -#define CAN1RXIDR0 _CAN1RXIDR0.Byte -#define CAN1RXIDR0_ID21 _CAN1RXIDR0.Bits.ID21 -#define CAN1RXIDR0_ID22 _CAN1RXIDR0.Bits.ID22 -#define CAN1RXIDR0_ID23 _CAN1RXIDR0.Bits.ID23 -#define CAN1RXIDR0_ID24 _CAN1RXIDR0.Bits.ID24 -#define CAN1RXIDR0_ID25 _CAN1RXIDR0.Bits.ID25 -#define CAN1RXIDR0_ID26 _CAN1RXIDR0.Bits.ID26 -#define CAN1RXIDR0_ID27 _CAN1RXIDR0.Bits.ID27 -#define CAN1RXIDR0_ID28 _CAN1RXIDR0.Bits.ID28 -#define CAN1RXIDR0_ID_21 _CAN1RXIDR0.MergedBits.grpID_21 -#define CAN1RXIDR0_ID CAN1RXIDR0_ID_21 - - -/*** CAN1RXIDR1 - MSCAN 1 Receive Identifier Register 1; 0x000001A1 ***/ -typedef union { - byte Byte; - struct { - byte ID15 :1; /* Extended format identifier Bit 15 */ - byte ID16 :1; /* Extended format identifier Bit 16 */ - byte ID17 :1; /* Extended format identifier Bit 17 */ - byte IDE :1; /* ID Extended */ - byte SRR :1; /* Substitute Remote Request */ - byte ID18 :1; /* Extended format identifier Bit 18 */ - byte ID19 :1; /* Extended format identifier Bit 19 */ - byte ID20 :1; /* Extended format identifier Bit 20 */ - } Bits; - struct { - byte grpID_15 :3; - byte :1; - byte :1; - byte grpID_18 :3; - } MergedBits; -} CAN1RXIDR1STR; -extern volatile CAN1RXIDR1STR _CAN1RXIDR1 @(REG_BASE + 0x000001A1); -#define CAN1RXIDR1 _CAN1RXIDR1.Byte -#define CAN1RXIDR1_ID15 _CAN1RXIDR1.Bits.ID15 -#define CAN1RXIDR1_ID16 _CAN1RXIDR1.Bits.ID16 -#define CAN1RXIDR1_ID17 _CAN1RXIDR1.Bits.ID17 -#define CAN1RXIDR1_IDE _CAN1RXIDR1.Bits.IDE -#define CAN1RXIDR1_SRR _CAN1RXIDR1.Bits.SRR -#define CAN1RXIDR1_ID18 _CAN1RXIDR1.Bits.ID18 -#define CAN1RXIDR1_ID19 _CAN1RXIDR1.Bits.ID19 -#define CAN1RXIDR1_ID20 _CAN1RXIDR1.Bits.ID20 -#define CAN1RXIDR1_ID_15 _CAN1RXIDR1.MergedBits.grpID_15 -#define CAN1RXIDR1_ID_18 _CAN1RXIDR1.MergedBits.grpID_18 -#define CAN1RXIDR1_ID CAN1RXIDR1_ID_15 - - -/*** CAN1RXIDR2 - MSCAN 1 Receive Identifier Register 2; 0x000001A2 ***/ -typedef union { - byte Byte; - struct { - byte ID7 :1; /* Extended format identifier Bit 7 */ - byte ID8 :1; /* Extended format identifier Bit 8 */ - byte ID9 :1; /* Extended format identifier Bit 9 */ - byte ID10 :1; /* Extended format identifier Bit 10 */ - byte ID11 :1; /* Extended format identifier Bit 11 */ - byte ID12 :1; /* Extended format identifier Bit 12 */ - byte ID13 :1; /* Extended format identifier Bit 13 */ - byte ID14 :1; /* Extended format identifier Bit 14 */ - } Bits; - struct { - byte grpID_7 :8; - } MergedBits; -} CAN1RXIDR2STR; -extern volatile CAN1RXIDR2STR _CAN1RXIDR2 @(REG_BASE + 0x000001A2); -#define CAN1RXIDR2 _CAN1RXIDR2.Byte -#define CAN1RXIDR2_ID7 _CAN1RXIDR2.Bits.ID7 -#define CAN1RXIDR2_ID8 _CAN1RXIDR2.Bits.ID8 -#define CAN1RXIDR2_ID9 _CAN1RXIDR2.Bits.ID9 -#define CAN1RXIDR2_ID10 _CAN1RXIDR2.Bits.ID10 -#define CAN1RXIDR2_ID11 _CAN1RXIDR2.Bits.ID11 -#define CAN1RXIDR2_ID12 _CAN1RXIDR2.Bits.ID12 -#define CAN1RXIDR2_ID13 _CAN1RXIDR2.Bits.ID13 -#define CAN1RXIDR2_ID14 _CAN1RXIDR2.Bits.ID14 -#define CAN1RXIDR2_ID_7 _CAN1RXIDR2.MergedBits.grpID_7 -#define CAN1RXIDR2_ID CAN1RXIDR2_ID_7 - - -/*** CAN1RXIDR3 - MSCAN 1 Receive Identifier Register 3; 0x000001A3 ***/ -typedef union { - byte Byte; - struct { - byte RTR :1; /* Remote Transmission Request */ - byte ID0 :1; /* Extended format identifier Bit 0 */ - byte ID1 :1; /* Extended format identifier Bit 1 */ - byte ID2 :1; /* Extended format identifier Bit 2 */ - byte ID3 :1; /* Extended format identifier Bit 3 */ - byte ID4 :1; /* Extended format identifier Bit 4 */ - byte ID5 :1; /* Extended format identifier Bit 5 */ - byte ID6 :1; /* Extended format identifier Bit 6 */ - } Bits; - struct { - byte :1; - byte grpID :7; - } MergedBits; -} CAN1RXIDR3STR; -extern volatile CAN1RXIDR3STR _CAN1RXIDR3 @(REG_BASE + 0x000001A3); -#define CAN1RXIDR3 _CAN1RXIDR3.Byte -#define CAN1RXIDR3_RTR _CAN1RXIDR3.Bits.RTR -#define CAN1RXIDR3_ID0 _CAN1RXIDR3.Bits.ID0 -#define CAN1RXIDR3_ID1 _CAN1RXIDR3.Bits.ID1 -#define CAN1RXIDR3_ID2 _CAN1RXIDR3.Bits.ID2 -#define CAN1RXIDR3_ID3 _CAN1RXIDR3.Bits.ID3 -#define CAN1RXIDR3_ID4 _CAN1RXIDR3.Bits.ID4 -#define CAN1RXIDR3_ID5 _CAN1RXIDR3.Bits.ID5 -#define CAN1RXIDR3_ID6 _CAN1RXIDR3.Bits.ID6 -#define CAN1RXIDR3_ID _CAN1RXIDR3.MergedBits.grpID - - -/*** CAN1RXDSR0 - MSCAN 1 Receive Data Segment Register 0; 0x000001A4 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN1RXDSR0STR; -extern volatile CAN1RXDSR0STR _CAN1RXDSR0 @(REG_BASE + 0x000001A4); -#define CAN1RXDSR0 _CAN1RXDSR0.Byte -#define CAN1RXDSR0_DB0 _CAN1RXDSR0.Bits.DB0 -#define CAN1RXDSR0_DB1 _CAN1RXDSR0.Bits.DB1 -#define CAN1RXDSR0_DB2 _CAN1RXDSR0.Bits.DB2 -#define CAN1RXDSR0_DB3 _CAN1RXDSR0.Bits.DB3 -#define CAN1RXDSR0_DB4 _CAN1RXDSR0.Bits.DB4 -#define CAN1RXDSR0_DB5 _CAN1RXDSR0.Bits.DB5 -#define CAN1RXDSR0_DB6 _CAN1RXDSR0.Bits.DB6 -#define CAN1RXDSR0_DB7 _CAN1RXDSR0.Bits.DB7 -#define CAN1RXDSR0_DB _CAN1RXDSR0.MergedBits.grpDB - - -/*** CAN1RXDSR1 - MSCAN 1 Receive Data Segment Register 1; 0x000001A5 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN1RXDSR1STR; -extern volatile CAN1RXDSR1STR _CAN1RXDSR1 @(REG_BASE + 0x000001A5); -#define CAN1RXDSR1 _CAN1RXDSR1.Byte -#define CAN1RXDSR1_DB0 _CAN1RXDSR1.Bits.DB0 -#define CAN1RXDSR1_DB1 _CAN1RXDSR1.Bits.DB1 -#define CAN1RXDSR1_DB2 _CAN1RXDSR1.Bits.DB2 -#define CAN1RXDSR1_DB3 _CAN1RXDSR1.Bits.DB3 -#define CAN1RXDSR1_DB4 _CAN1RXDSR1.Bits.DB4 -#define CAN1RXDSR1_DB5 _CAN1RXDSR1.Bits.DB5 -#define CAN1RXDSR1_DB6 _CAN1RXDSR1.Bits.DB6 -#define CAN1RXDSR1_DB7 _CAN1RXDSR1.Bits.DB7 -#define CAN1RXDSR1_DB _CAN1RXDSR1.MergedBits.grpDB - - -/*** CAN1RXDSR2 - MSCAN 1 Receive Data Segment Register 2; 0x000001A6 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN1RXDSR2STR; -extern volatile CAN1RXDSR2STR _CAN1RXDSR2 @(REG_BASE + 0x000001A6); -#define CAN1RXDSR2 _CAN1RXDSR2.Byte -#define CAN1RXDSR2_DB0 _CAN1RXDSR2.Bits.DB0 -#define CAN1RXDSR2_DB1 _CAN1RXDSR2.Bits.DB1 -#define CAN1RXDSR2_DB2 _CAN1RXDSR2.Bits.DB2 -#define CAN1RXDSR2_DB3 _CAN1RXDSR2.Bits.DB3 -#define CAN1RXDSR2_DB4 _CAN1RXDSR2.Bits.DB4 -#define CAN1RXDSR2_DB5 _CAN1RXDSR2.Bits.DB5 -#define CAN1RXDSR2_DB6 _CAN1RXDSR2.Bits.DB6 -#define CAN1RXDSR2_DB7 _CAN1RXDSR2.Bits.DB7 -#define CAN1RXDSR2_DB _CAN1RXDSR2.MergedBits.grpDB - - -/*** CAN1RXDSR3 - MSCAN 1 Receive Data Segment Register 3; 0x000001A7 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN1RXDSR3STR; -extern volatile CAN1RXDSR3STR _CAN1RXDSR3 @(REG_BASE + 0x000001A7); -#define CAN1RXDSR3 _CAN1RXDSR3.Byte -#define CAN1RXDSR3_DB0 _CAN1RXDSR3.Bits.DB0 -#define CAN1RXDSR3_DB1 _CAN1RXDSR3.Bits.DB1 -#define CAN1RXDSR3_DB2 _CAN1RXDSR3.Bits.DB2 -#define CAN1RXDSR3_DB3 _CAN1RXDSR3.Bits.DB3 -#define CAN1RXDSR3_DB4 _CAN1RXDSR3.Bits.DB4 -#define CAN1RXDSR3_DB5 _CAN1RXDSR3.Bits.DB5 -#define CAN1RXDSR3_DB6 _CAN1RXDSR3.Bits.DB6 -#define CAN1RXDSR3_DB7 _CAN1RXDSR3.Bits.DB7 -#define CAN1RXDSR3_DB _CAN1RXDSR3.MergedBits.grpDB - - -/*** CAN1RXDSR4 - MSCAN 1 Receive Data Segment Register 4; 0x000001A8 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN1RXDSR4STR; -extern volatile CAN1RXDSR4STR _CAN1RXDSR4 @(REG_BASE + 0x000001A8); -#define CAN1RXDSR4 _CAN1RXDSR4.Byte -#define CAN1RXDSR4_DB0 _CAN1RXDSR4.Bits.DB0 -#define CAN1RXDSR4_DB1 _CAN1RXDSR4.Bits.DB1 -#define CAN1RXDSR4_DB2 _CAN1RXDSR4.Bits.DB2 -#define CAN1RXDSR4_DB3 _CAN1RXDSR4.Bits.DB3 -#define CAN1RXDSR4_DB4 _CAN1RXDSR4.Bits.DB4 -#define CAN1RXDSR4_DB5 _CAN1RXDSR4.Bits.DB5 -#define CAN1RXDSR4_DB6 _CAN1RXDSR4.Bits.DB6 -#define CAN1RXDSR4_DB7 _CAN1RXDSR4.Bits.DB7 -#define CAN1RXDSR4_DB _CAN1RXDSR4.MergedBits.grpDB - - -/*** CAN1RXDSR5 - MSCAN 1 Receive Data Segment Register 5; 0x000001A9 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN1RXDSR5STR; -extern volatile CAN1RXDSR5STR _CAN1RXDSR5 @(REG_BASE + 0x000001A9); -#define CAN1RXDSR5 _CAN1RXDSR5.Byte -#define CAN1RXDSR5_DB0 _CAN1RXDSR5.Bits.DB0 -#define CAN1RXDSR5_DB1 _CAN1RXDSR5.Bits.DB1 -#define CAN1RXDSR5_DB2 _CAN1RXDSR5.Bits.DB2 -#define CAN1RXDSR5_DB3 _CAN1RXDSR5.Bits.DB3 -#define CAN1RXDSR5_DB4 _CAN1RXDSR5.Bits.DB4 -#define CAN1RXDSR5_DB5 _CAN1RXDSR5.Bits.DB5 -#define CAN1RXDSR5_DB6 _CAN1RXDSR5.Bits.DB6 -#define CAN1RXDSR5_DB7 _CAN1RXDSR5.Bits.DB7 -#define CAN1RXDSR5_DB _CAN1RXDSR5.MergedBits.grpDB - - -/*** CAN1RXDSR6 - MSCAN 1 Receive Data Segment Register 6; 0x000001AA ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN1RXDSR6STR; -extern volatile CAN1RXDSR6STR _CAN1RXDSR6 @(REG_BASE + 0x000001AA); -#define CAN1RXDSR6 _CAN1RXDSR6.Byte -#define CAN1RXDSR6_DB0 _CAN1RXDSR6.Bits.DB0 -#define CAN1RXDSR6_DB1 _CAN1RXDSR6.Bits.DB1 -#define CAN1RXDSR6_DB2 _CAN1RXDSR6.Bits.DB2 -#define CAN1RXDSR6_DB3 _CAN1RXDSR6.Bits.DB3 -#define CAN1RXDSR6_DB4 _CAN1RXDSR6.Bits.DB4 -#define CAN1RXDSR6_DB5 _CAN1RXDSR6.Bits.DB5 -#define CAN1RXDSR6_DB6 _CAN1RXDSR6.Bits.DB6 -#define CAN1RXDSR6_DB7 _CAN1RXDSR6.Bits.DB7 -#define CAN1RXDSR6_DB _CAN1RXDSR6.MergedBits.grpDB - - -/*** CAN1RXDSR7 - MSCAN 1 Receive Data Segment Register 7; 0x000001AB ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN1RXDSR7STR; -extern volatile CAN1RXDSR7STR _CAN1RXDSR7 @(REG_BASE + 0x000001AB); -#define CAN1RXDSR7 _CAN1RXDSR7.Byte -#define CAN1RXDSR7_DB0 _CAN1RXDSR7.Bits.DB0 -#define CAN1RXDSR7_DB1 _CAN1RXDSR7.Bits.DB1 -#define CAN1RXDSR7_DB2 _CAN1RXDSR7.Bits.DB2 -#define CAN1RXDSR7_DB3 _CAN1RXDSR7.Bits.DB3 -#define CAN1RXDSR7_DB4 _CAN1RXDSR7.Bits.DB4 -#define CAN1RXDSR7_DB5 _CAN1RXDSR7.Bits.DB5 -#define CAN1RXDSR7_DB6 _CAN1RXDSR7.Bits.DB6 -#define CAN1RXDSR7_DB7 _CAN1RXDSR7.Bits.DB7 -#define CAN1RXDSR7_DB _CAN1RXDSR7.MergedBits.grpDB - - -/*** CAN1RXDLR - MSCAN 1 Receive Data Length Register; 0x000001AC ***/ -typedef union { - byte Byte; - struct { - byte DLC0 :1; /* Data Length Code Bit 0 */ - byte DLC1 :1; /* Data Length Code Bit 1 */ - byte DLC2 :1; /* Data Length Code Bit 2 */ - byte DLC3 :1; /* Data Length Code Bit 3 */ - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpDLC :4; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} CAN1RXDLRSTR; -extern volatile CAN1RXDLRSTR _CAN1RXDLR @(REG_BASE + 0x000001AC); -#define CAN1RXDLR _CAN1RXDLR.Byte -#define CAN1RXDLR_DLC0 _CAN1RXDLR.Bits.DLC0 -#define CAN1RXDLR_DLC1 _CAN1RXDLR.Bits.DLC1 -#define CAN1RXDLR_DLC2 _CAN1RXDLR.Bits.DLC2 -#define CAN1RXDLR_DLC3 _CAN1RXDLR.Bits.DLC3 -#define CAN1RXDLR_DLC _CAN1RXDLR.MergedBits.grpDLC - - -/*** CAN1TXIDR0 - MSCAN 1 Transmit Identifier Register 0; 0x000001B0 ***/ -typedef union { - byte Byte; - struct { - byte ID21 :1; /* Extended format identifier Bit 21 */ - byte ID22 :1; /* Extended format identifier Bit 22 */ - byte ID23 :1; /* Extended format identifier Bit 23 */ - byte ID24 :1; /* Extended format identifier Bit 24 */ - byte ID25 :1; /* Extended format identifier Bit 25 */ - byte ID26 :1; /* Extended format identifier Bit 26 */ - byte ID27 :1; /* Extended format identifier Bit 27 */ - byte ID28 :1; /* Extended format identifier Bit 28 */ - } Bits; - struct { - byte grpID_21 :8; - } MergedBits; -} CAN1TXIDR0STR; -extern volatile CAN1TXIDR0STR _CAN1TXIDR0 @(REG_BASE + 0x000001B0); -#define CAN1TXIDR0 _CAN1TXIDR0.Byte -#define CAN1TXIDR0_ID21 _CAN1TXIDR0.Bits.ID21 -#define CAN1TXIDR0_ID22 _CAN1TXIDR0.Bits.ID22 -#define CAN1TXIDR0_ID23 _CAN1TXIDR0.Bits.ID23 -#define CAN1TXIDR0_ID24 _CAN1TXIDR0.Bits.ID24 -#define CAN1TXIDR0_ID25 _CAN1TXIDR0.Bits.ID25 -#define CAN1TXIDR0_ID26 _CAN1TXIDR0.Bits.ID26 -#define CAN1TXIDR0_ID27 _CAN1TXIDR0.Bits.ID27 -#define CAN1TXIDR0_ID28 _CAN1TXIDR0.Bits.ID28 -#define CAN1TXIDR0_ID_21 _CAN1TXIDR0.MergedBits.grpID_21 -#define CAN1TXIDR0_ID CAN1TXIDR0_ID_21 - - -/*** CAN1TXIDR1 - MSCAN 1 Transmit Identifier Register 1; 0x000001B1 ***/ -typedef union { - byte Byte; - struct { - byte ID15 :1; /* Extended format identifier Bit 15 */ - byte ID16 :1; /* Extended format identifier Bit 16 */ - byte ID17 :1; /* Extended format identifier Bit 17 */ - byte IDE :1; /* ID Extended */ - byte SRR :1; /* Substitute Remote Request */ - byte ID18 :1; /* Extended format identifier Bit 18 */ - byte ID19 :1; /* Extended format identifier Bit 19 */ - byte ID20 :1; /* Extended format identifier Bit 20 */ - } Bits; - struct { - byte grpID_15 :3; - byte :1; - byte :1; - byte grpID_18 :3; - } MergedBits; -} CAN1TXIDR1STR; -extern volatile CAN1TXIDR1STR _CAN1TXIDR1 @(REG_BASE + 0x000001B1); -#define CAN1TXIDR1 _CAN1TXIDR1.Byte -#define CAN1TXIDR1_ID15 _CAN1TXIDR1.Bits.ID15 -#define CAN1TXIDR1_ID16 _CAN1TXIDR1.Bits.ID16 -#define CAN1TXIDR1_ID17 _CAN1TXIDR1.Bits.ID17 -#define CAN1TXIDR1_IDE _CAN1TXIDR1.Bits.IDE -#define CAN1TXIDR1_SRR _CAN1TXIDR1.Bits.SRR -#define CAN1TXIDR1_ID18 _CAN1TXIDR1.Bits.ID18 -#define CAN1TXIDR1_ID19 _CAN1TXIDR1.Bits.ID19 -#define CAN1TXIDR1_ID20 _CAN1TXIDR1.Bits.ID20 -#define CAN1TXIDR1_ID_15 _CAN1TXIDR1.MergedBits.grpID_15 -#define CAN1TXIDR1_ID_18 _CAN1TXIDR1.MergedBits.grpID_18 -#define CAN1TXIDR1_ID CAN1TXIDR1_ID_15 - - -/*** CAN1TXIDR2 - MSCAN 1 Transmit Identifier Register 2; 0x000001B2 ***/ -typedef union { - byte Byte; - struct { - byte ID7 :1; /* Extended format identifier Bit 7 */ - byte ID8 :1; /* Extended format identifier Bit 8 */ - byte ID9 :1; /* Extended format identifier Bit 9 */ - byte ID10 :1; /* Extended format identifier Bit 10 */ - byte ID11 :1; /* Extended format identifier Bit 11 */ - byte ID12 :1; /* Extended format identifier Bit 12 */ - byte ID13 :1; /* Extended format identifier Bit 13 */ - byte ID14 :1; /* Extended format identifier Bit 14 */ - } Bits; - struct { - byte grpID_7 :8; - } MergedBits; -} CAN1TXIDR2STR; -extern volatile CAN1TXIDR2STR _CAN1TXIDR2 @(REG_BASE + 0x000001B2); -#define CAN1TXIDR2 _CAN1TXIDR2.Byte -#define CAN1TXIDR2_ID7 _CAN1TXIDR2.Bits.ID7 -#define CAN1TXIDR2_ID8 _CAN1TXIDR2.Bits.ID8 -#define CAN1TXIDR2_ID9 _CAN1TXIDR2.Bits.ID9 -#define CAN1TXIDR2_ID10 _CAN1TXIDR2.Bits.ID10 -#define CAN1TXIDR2_ID11 _CAN1TXIDR2.Bits.ID11 -#define CAN1TXIDR2_ID12 _CAN1TXIDR2.Bits.ID12 -#define CAN1TXIDR2_ID13 _CAN1TXIDR2.Bits.ID13 -#define CAN1TXIDR2_ID14 _CAN1TXIDR2.Bits.ID14 -#define CAN1TXIDR2_ID_7 _CAN1TXIDR2.MergedBits.grpID_7 -#define CAN1TXIDR2_ID CAN1TXIDR2_ID_7 - - -/*** CAN1TXIDR3 - MSCAN 1 Transmit Identifier Register 3; 0x000001B3 ***/ -typedef union { - byte Byte; - struct { - byte RTR :1; /* Remote Transmission Request */ - byte ID0 :1; /* Extended format identifier Bit 0 */ - byte ID1 :1; /* Extended format identifier Bit 1 */ - byte ID2 :1; /* Extended format identifier Bit 2 */ - byte ID3 :1; /* Extended format identifier Bit 3 */ - byte ID4 :1; /* Extended format identifier Bit 4 */ - byte ID5 :1; /* Extended format identifier Bit 5 */ - byte ID6 :1; /* Extended format identifier Bit 6 */ - } Bits; - struct { - byte :1; - byte grpID :7; - } MergedBits; -} CAN1TXIDR3STR; -extern volatile CAN1TXIDR3STR _CAN1TXIDR3 @(REG_BASE + 0x000001B3); -#define CAN1TXIDR3 _CAN1TXIDR3.Byte -#define CAN1TXIDR3_RTR _CAN1TXIDR3.Bits.RTR -#define CAN1TXIDR3_ID0 _CAN1TXIDR3.Bits.ID0 -#define CAN1TXIDR3_ID1 _CAN1TXIDR3.Bits.ID1 -#define CAN1TXIDR3_ID2 _CAN1TXIDR3.Bits.ID2 -#define CAN1TXIDR3_ID3 _CAN1TXIDR3.Bits.ID3 -#define CAN1TXIDR3_ID4 _CAN1TXIDR3.Bits.ID4 -#define CAN1TXIDR3_ID5 _CAN1TXIDR3.Bits.ID5 -#define CAN1TXIDR3_ID6 _CAN1TXIDR3.Bits.ID6 -#define CAN1TXIDR3_ID _CAN1TXIDR3.MergedBits.grpID - - -/*** CAN1TXDSR0 - MSCAN 1 Transmit Data Segment Register 0; 0x000001B4 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN1TXDSR0STR; -extern volatile CAN1TXDSR0STR _CAN1TXDSR0 @(REG_BASE + 0x000001B4); -#define CAN1TXDSR0 _CAN1TXDSR0.Byte -#define CAN1TXDSR0_DB0 _CAN1TXDSR0.Bits.DB0 -#define CAN1TXDSR0_DB1 _CAN1TXDSR0.Bits.DB1 -#define CAN1TXDSR0_DB2 _CAN1TXDSR0.Bits.DB2 -#define CAN1TXDSR0_DB3 _CAN1TXDSR0.Bits.DB3 -#define CAN1TXDSR0_DB4 _CAN1TXDSR0.Bits.DB4 -#define CAN1TXDSR0_DB5 _CAN1TXDSR0.Bits.DB5 -#define CAN1TXDSR0_DB6 _CAN1TXDSR0.Bits.DB6 -#define CAN1TXDSR0_DB7 _CAN1TXDSR0.Bits.DB7 -#define CAN1TXDSR0_DB _CAN1TXDSR0.MergedBits.grpDB - - -/*** CAN1TXDSR1 - MSCAN 1 Transmit Data Segment Register 1; 0x000001B5 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN1TXDSR1STR; -extern volatile CAN1TXDSR1STR _CAN1TXDSR1 @(REG_BASE + 0x000001B5); -#define CAN1TXDSR1 _CAN1TXDSR1.Byte -#define CAN1TXDSR1_DB0 _CAN1TXDSR1.Bits.DB0 -#define CAN1TXDSR1_DB1 _CAN1TXDSR1.Bits.DB1 -#define CAN1TXDSR1_DB2 _CAN1TXDSR1.Bits.DB2 -#define CAN1TXDSR1_DB3 _CAN1TXDSR1.Bits.DB3 -#define CAN1TXDSR1_DB4 _CAN1TXDSR1.Bits.DB4 -#define CAN1TXDSR1_DB5 _CAN1TXDSR1.Bits.DB5 -#define CAN1TXDSR1_DB6 _CAN1TXDSR1.Bits.DB6 -#define CAN1TXDSR1_DB7 _CAN1TXDSR1.Bits.DB7 -#define CAN1TXDSR1_DB _CAN1TXDSR1.MergedBits.grpDB - - -/*** CAN1TXDSR2 - MSCAN 1 Transmit Data Segment Register 2; 0x000001B6 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN1TXDSR2STR; -extern volatile CAN1TXDSR2STR _CAN1TXDSR2 @(REG_BASE + 0x000001B6); -#define CAN1TXDSR2 _CAN1TXDSR2.Byte -#define CAN1TXDSR2_DB0 _CAN1TXDSR2.Bits.DB0 -#define CAN1TXDSR2_DB1 _CAN1TXDSR2.Bits.DB1 -#define CAN1TXDSR2_DB2 _CAN1TXDSR2.Bits.DB2 -#define CAN1TXDSR2_DB3 _CAN1TXDSR2.Bits.DB3 -#define CAN1TXDSR2_DB4 _CAN1TXDSR2.Bits.DB4 -#define CAN1TXDSR2_DB5 _CAN1TXDSR2.Bits.DB5 -#define CAN1TXDSR2_DB6 _CAN1TXDSR2.Bits.DB6 -#define CAN1TXDSR2_DB7 _CAN1TXDSR2.Bits.DB7 -#define CAN1TXDSR2_DB _CAN1TXDSR2.MergedBits.grpDB - - -/*** CAN1TXDSR3 - MSCAN 1 Transmit Data Segment Register 3; 0x000001B7 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN1TXDSR3STR; -extern volatile CAN1TXDSR3STR _CAN1TXDSR3 @(REG_BASE + 0x000001B7); -#define CAN1TXDSR3 _CAN1TXDSR3.Byte -#define CAN1TXDSR3_DB0 _CAN1TXDSR3.Bits.DB0 -#define CAN1TXDSR3_DB1 _CAN1TXDSR3.Bits.DB1 -#define CAN1TXDSR3_DB2 _CAN1TXDSR3.Bits.DB2 -#define CAN1TXDSR3_DB3 _CAN1TXDSR3.Bits.DB3 -#define CAN1TXDSR3_DB4 _CAN1TXDSR3.Bits.DB4 -#define CAN1TXDSR3_DB5 _CAN1TXDSR3.Bits.DB5 -#define CAN1TXDSR3_DB6 _CAN1TXDSR3.Bits.DB6 -#define CAN1TXDSR3_DB7 _CAN1TXDSR3.Bits.DB7 -#define CAN1TXDSR3_DB _CAN1TXDSR3.MergedBits.grpDB - - -/*** CAN1TXDSR4 - MSCAN 1 Transmit Data Segment Register 4; 0x000001B8 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN1TXDSR4STR; -extern volatile CAN1TXDSR4STR _CAN1TXDSR4 @(REG_BASE + 0x000001B8); -#define CAN1TXDSR4 _CAN1TXDSR4.Byte -#define CAN1TXDSR4_DB0 _CAN1TXDSR4.Bits.DB0 -#define CAN1TXDSR4_DB1 _CAN1TXDSR4.Bits.DB1 -#define CAN1TXDSR4_DB2 _CAN1TXDSR4.Bits.DB2 -#define CAN1TXDSR4_DB3 _CAN1TXDSR4.Bits.DB3 -#define CAN1TXDSR4_DB4 _CAN1TXDSR4.Bits.DB4 -#define CAN1TXDSR4_DB5 _CAN1TXDSR4.Bits.DB5 -#define CAN1TXDSR4_DB6 _CAN1TXDSR4.Bits.DB6 -#define CAN1TXDSR4_DB7 _CAN1TXDSR4.Bits.DB7 -#define CAN1TXDSR4_DB _CAN1TXDSR4.MergedBits.grpDB - - -/*** CAN1TXDSR5 - MSCAN 1 Transmit Data Segment Register 5; 0x000001B9 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN1TXDSR5STR; -extern volatile CAN1TXDSR5STR _CAN1TXDSR5 @(REG_BASE + 0x000001B9); -#define CAN1TXDSR5 _CAN1TXDSR5.Byte -#define CAN1TXDSR5_DB0 _CAN1TXDSR5.Bits.DB0 -#define CAN1TXDSR5_DB1 _CAN1TXDSR5.Bits.DB1 -#define CAN1TXDSR5_DB2 _CAN1TXDSR5.Bits.DB2 -#define CAN1TXDSR5_DB3 _CAN1TXDSR5.Bits.DB3 -#define CAN1TXDSR5_DB4 _CAN1TXDSR5.Bits.DB4 -#define CAN1TXDSR5_DB5 _CAN1TXDSR5.Bits.DB5 -#define CAN1TXDSR5_DB6 _CAN1TXDSR5.Bits.DB6 -#define CAN1TXDSR5_DB7 _CAN1TXDSR5.Bits.DB7 -#define CAN1TXDSR5_DB _CAN1TXDSR5.MergedBits.grpDB - - -/*** CAN1TXDSR6 - MSCAN 1 Transmit Data Segment Register 6; 0x000001BA ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN1TXDSR6STR; -extern volatile CAN1TXDSR6STR _CAN1TXDSR6 @(REG_BASE + 0x000001BA); -#define CAN1TXDSR6 _CAN1TXDSR6.Byte -#define CAN1TXDSR6_DB0 _CAN1TXDSR6.Bits.DB0 -#define CAN1TXDSR6_DB1 _CAN1TXDSR6.Bits.DB1 -#define CAN1TXDSR6_DB2 _CAN1TXDSR6.Bits.DB2 -#define CAN1TXDSR6_DB3 _CAN1TXDSR6.Bits.DB3 -#define CAN1TXDSR6_DB4 _CAN1TXDSR6.Bits.DB4 -#define CAN1TXDSR6_DB5 _CAN1TXDSR6.Bits.DB5 -#define CAN1TXDSR6_DB6 _CAN1TXDSR6.Bits.DB6 -#define CAN1TXDSR6_DB7 _CAN1TXDSR6.Bits.DB7 -#define CAN1TXDSR6_DB _CAN1TXDSR6.MergedBits.grpDB - - -/*** CAN1TXDSR7 - MSCAN 1 Transmit Data Segment Register 7; 0x000001BB ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN1TXDSR7STR; -extern volatile CAN1TXDSR7STR _CAN1TXDSR7 @(REG_BASE + 0x000001BB); -#define CAN1TXDSR7 _CAN1TXDSR7.Byte -#define CAN1TXDSR7_DB0 _CAN1TXDSR7.Bits.DB0 -#define CAN1TXDSR7_DB1 _CAN1TXDSR7.Bits.DB1 -#define CAN1TXDSR7_DB2 _CAN1TXDSR7.Bits.DB2 -#define CAN1TXDSR7_DB3 _CAN1TXDSR7.Bits.DB3 -#define CAN1TXDSR7_DB4 _CAN1TXDSR7.Bits.DB4 -#define CAN1TXDSR7_DB5 _CAN1TXDSR7.Bits.DB5 -#define CAN1TXDSR7_DB6 _CAN1TXDSR7.Bits.DB6 -#define CAN1TXDSR7_DB7 _CAN1TXDSR7.Bits.DB7 -#define CAN1TXDSR7_DB _CAN1TXDSR7.MergedBits.grpDB - - -/*** CAN1TXDLR - MSCAN 1 Transmit Data Length Register; 0x000001BC ***/ -typedef union { - byte Byte; - struct { - byte DLC0 :1; /* Data Length Code Bit 0 */ - byte DLC1 :1; /* Data Length Code Bit 1 */ - byte DLC2 :1; /* Data Length Code Bit 2 */ - byte DLC3 :1; /* Data Length Code Bit 3 */ - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpDLC :4; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} CAN1TXDLRSTR; -extern volatile CAN1TXDLRSTR _CAN1TXDLR @(REG_BASE + 0x000001BC); -#define CAN1TXDLR _CAN1TXDLR.Byte -#define CAN1TXDLR_DLC0 _CAN1TXDLR.Bits.DLC0 -#define CAN1TXDLR_DLC1 _CAN1TXDLR.Bits.DLC1 -#define CAN1TXDLR_DLC2 _CAN1TXDLR.Bits.DLC2 -#define CAN1TXDLR_DLC3 _CAN1TXDLR.Bits.DLC3 -#define CAN1TXDLR_DLC _CAN1TXDLR.MergedBits.grpDLC - - -/*** CAN1TXTBPR - MSCAN 1 Transmit Buffer Priority; 0x000001BF ***/ -typedef union { - byte Byte; - struct { - byte PRIO0 :1; /* Transmit Buffer Priority Bit 0 */ - byte PRIO1 :1; /* Transmit Buffer Priority Bit 1 */ - byte PRIO2 :1; /* Transmit Buffer Priority Bit 2 */ - byte PRIO3 :1; /* Transmit Buffer Priority Bit 3 */ - byte PRIO4 :1; /* Transmit Buffer Priority Bit 4 */ - byte PRIO5 :1; /* Transmit Buffer Priority Bit 5 */ - byte PRIO6 :1; /* Transmit Buffer Priority Bit 6 */ - byte PRIO7 :1; /* Transmit Buffer Priority Bit 7 */ - } Bits; - struct { - byte grpPRIO :8; - } MergedBits; -} CAN1TXTBPRSTR; -extern volatile CAN1TXTBPRSTR _CAN1TXTBPR @(REG_BASE + 0x000001BF); -#define CAN1TXTBPR _CAN1TXTBPR.Byte -#define CAN1TXTBPR_PRIO0 _CAN1TXTBPR.Bits.PRIO0 -#define CAN1TXTBPR_PRIO1 _CAN1TXTBPR.Bits.PRIO1 -#define CAN1TXTBPR_PRIO2 _CAN1TXTBPR.Bits.PRIO2 -#define CAN1TXTBPR_PRIO3 _CAN1TXTBPR.Bits.PRIO3 -#define CAN1TXTBPR_PRIO4 _CAN1TXTBPR.Bits.PRIO4 -#define CAN1TXTBPR_PRIO5 _CAN1TXTBPR.Bits.PRIO5 -#define CAN1TXTBPR_PRIO6 _CAN1TXTBPR.Bits.PRIO6 -#define CAN1TXTBPR_PRIO7 _CAN1TXTBPR.Bits.PRIO7 -#define CAN1TXTBPR_PRIO _CAN1TXTBPR.MergedBits.grpPRIO - - -/*** CAN2CTL0 - MSCAN 2 Control 0 Register; 0x000001C0 ***/ -typedef union { - byte Byte; - struct { - byte INITRQ :1; /* Initialization Mode Request */ - byte SLPRQ :1; /* Sleep Mode Request */ - byte WUPE :1; /* Wake-Up Enable */ - byte TIME :1; /* Timer Enable */ - byte SYNCH :1; /* Synchronized Status */ - byte CSWAI :1; /* CAN Stops in Wait Mode */ - byte RXACT :1; /* Receiver Active Status */ - byte RXFRM :1; /* Received Frame Flag */ - } Bits; -} CAN2CTL0STR; -extern volatile CAN2CTL0STR _CAN2CTL0 @(REG_BASE + 0x000001C0); -#define CAN2CTL0 _CAN2CTL0.Byte -#define CAN2CTL0_INITRQ _CAN2CTL0.Bits.INITRQ -#define CAN2CTL0_SLPRQ _CAN2CTL0.Bits.SLPRQ -#define CAN2CTL0_WUPE _CAN2CTL0.Bits.WUPE -#define CAN2CTL0_TIME _CAN2CTL0.Bits.TIME -#define CAN2CTL0_SYNCH _CAN2CTL0.Bits.SYNCH -#define CAN2CTL0_CSWAI _CAN2CTL0.Bits.CSWAI -#define CAN2CTL0_RXACT _CAN2CTL0.Bits.RXACT -#define CAN2CTL0_RXFRM _CAN2CTL0.Bits.RXFRM - - -/*** CAN2CTL1 - MSCAN 2 Control 1 Register; 0x000001C1 ***/ -typedef union { - byte Byte; - struct { - byte INITAK :1; /* Initialization Mode Acknowledge */ - byte SLPAK :1; /* Sleep Mode Acknowledge */ - byte WUPM :1; /* Wake-Up Mode */ - byte :1; - byte LISTEN :1; /* Listen Only Mode */ - byte LOOPB :1; /* Loop Back Self Test Mode */ - byte CLKSRC :1; /* MSCAN 2 Clock Source */ - byte CANE :1; /* MSCAN 2 Enable */ - } Bits; -} CAN2CTL1STR; -extern volatile CAN2CTL1STR _CAN2CTL1 @(REG_BASE + 0x000001C1); -#define CAN2CTL1 _CAN2CTL1.Byte -#define CAN2CTL1_INITAK _CAN2CTL1.Bits.INITAK -#define CAN2CTL1_SLPAK _CAN2CTL1.Bits.SLPAK -#define CAN2CTL1_WUPM _CAN2CTL1.Bits.WUPM -#define CAN2CTL1_LISTEN _CAN2CTL1.Bits.LISTEN -#define CAN2CTL1_LOOPB _CAN2CTL1.Bits.LOOPB -#define CAN2CTL1_CLKSRC _CAN2CTL1.Bits.CLKSRC -#define CAN2CTL1_CANE _CAN2CTL1.Bits.CANE - - -/*** CAN2BTR0 - MSCAN 2 Bus Timing Register 0; 0x000001C2 ***/ -typedef union { - byte Byte; - struct { - byte BRP0 :1; /* Baud Rate Prescaler 0 */ - byte BRP1 :1; /* Baud Rate Prescaler 1 */ - byte BRP2 :1; /* Baud Rate Prescaler 2 */ - byte BRP3 :1; /* Baud Rate Prescaler 3 */ - byte BRP4 :1; /* Baud Rate Prescaler 4 */ - byte BRP5 :1; /* Baud Rate Prescaler 5 */ - byte SJW0 :1; /* Synchronization Jump Width 0 */ - byte SJW1 :1; /* Synchronization Jump Width 1 */ - } Bits; - struct { - byte grpBRP :6; - byte grpSJW :2; - } MergedBits; -} CAN2BTR0STR; -extern volatile CAN2BTR0STR _CAN2BTR0 @(REG_BASE + 0x000001C2); -#define CAN2BTR0 _CAN2BTR0.Byte -#define CAN2BTR0_BRP0 _CAN2BTR0.Bits.BRP0 -#define CAN2BTR0_BRP1 _CAN2BTR0.Bits.BRP1 -#define CAN2BTR0_BRP2 _CAN2BTR0.Bits.BRP2 -#define CAN2BTR0_BRP3 _CAN2BTR0.Bits.BRP3 -#define CAN2BTR0_BRP4 _CAN2BTR0.Bits.BRP4 -#define CAN2BTR0_BRP5 _CAN2BTR0.Bits.BRP5 -#define CAN2BTR0_SJW0 _CAN2BTR0.Bits.SJW0 -#define CAN2BTR0_SJW1 _CAN2BTR0.Bits.SJW1 -#define CAN2BTR0_BRP _CAN2BTR0.MergedBits.grpBRP -#define CAN2BTR0_SJW _CAN2BTR0.MergedBits.grpSJW - - -/*** CAN2BTR1 - MSCAN 2 Bus Timing Register 1; 0x000001C3 ***/ -typedef union { - byte Byte; - struct { - byte TSEG10 :1; /* Time Segment 1 */ - byte TSEG11 :1; /* Time Segment 1 */ - byte TSEG12 :1; /* Time Segment 1 */ - byte TSEG13 :1; /* Time Segment 1 */ - byte TSEG20 :1; /* Time Segment 2 */ - byte TSEG21 :1; /* Time Segment 2 */ - byte TSEG22 :1; /* Time Segment 2 */ - byte SAMP :1; /* Sampling */ - } Bits; - struct { - byte grpTSEG_10 :4; - byte grpTSEG_20 :3; - byte :1; - } MergedBits; -} CAN2BTR1STR; -extern volatile CAN2BTR1STR _CAN2BTR1 @(REG_BASE + 0x000001C3); -#define CAN2BTR1 _CAN2BTR1.Byte -#define CAN2BTR1_TSEG10 _CAN2BTR1.Bits.TSEG10 -#define CAN2BTR1_TSEG11 _CAN2BTR1.Bits.TSEG11 -#define CAN2BTR1_TSEG12 _CAN2BTR1.Bits.TSEG12 -#define CAN2BTR1_TSEG13 _CAN2BTR1.Bits.TSEG13 -#define CAN2BTR1_TSEG20 _CAN2BTR1.Bits.TSEG20 -#define CAN2BTR1_TSEG21 _CAN2BTR1.Bits.TSEG21 -#define CAN2BTR1_TSEG22 _CAN2BTR1.Bits.TSEG22 -#define CAN2BTR1_SAMP _CAN2BTR1.Bits.SAMP -#define CAN2BTR1_TSEG_10 _CAN2BTR1.MergedBits.grpTSEG_10 -#define CAN2BTR1_TSEG_20 _CAN2BTR1.MergedBits.grpTSEG_20 -#define CAN2BTR1_TSEG CAN2BTR1_TSEG_10 - - -/*** CAN2RFLG - MSCAN 2 Receiver Flag Register; 0x000001C4 ***/ -typedef union { - byte Byte; - struct { - byte RXF :1; /* Receive Buffer Full */ - byte OVRIF :1; /* Overrun Interrupt Flag */ - byte TSTAT0 :1; /* Transmitter Status Bit 0 */ - byte TSTAT1 :1; /* Transmitter Status Bit 1 */ - byte RSTAT0 :1; /* Receiver Status Bit 0 */ - byte RSTAT1 :1; /* Receiver Status Bit 1 */ - byte CSCIF :1; /* CAN Status Change Interrupt Flag */ - byte WUPIF :1; /* Wake-up Interrupt Flag */ - } Bits; - struct { - byte :1; - byte :1; - byte grpTSTAT :2; - byte grpRSTAT :2; - byte :1; - byte :1; - } MergedBits; -} CAN2RFLGSTR; -extern volatile CAN2RFLGSTR _CAN2RFLG @(REG_BASE + 0x000001C4); -#define CAN2RFLG _CAN2RFLG.Byte -#define CAN2RFLG_RXF _CAN2RFLG.Bits.RXF -#define CAN2RFLG_OVRIF _CAN2RFLG.Bits.OVRIF -#define CAN2RFLG_TSTAT0 _CAN2RFLG.Bits.TSTAT0 -#define CAN2RFLG_TSTAT1 _CAN2RFLG.Bits.TSTAT1 -#define CAN2RFLG_RSTAT0 _CAN2RFLG.Bits.RSTAT0 -#define CAN2RFLG_RSTAT1 _CAN2RFLG.Bits.RSTAT1 -#define CAN2RFLG_CSCIF _CAN2RFLG.Bits.CSCIF -#define CAN2RFLG_WUPIF _CAN2RFLG.Bits.WUPIF -#define CAN2RFLG_TSTAT _CAN2RFLG.MergedBits.grpTSTAT -#define CAN2RFLG_RSTAT _CAN2RFLG.MergedBits.grpRSTAT - - -/*** CAN2RIER - MSCAN 2 Receiver Interrupt Enable Register; 0x000001C5 ***/ -typedef union { - byte Byte; - struct { - byte RXFIE :1; /* Receiver Full Interrupt Enable */ - byte OVRIE :1; /* Overrun Interrupt Enable */ - byte TSTATE0 :1; /* Transmitter Status Change Enable 0 */ - byte TSTATE1 :1; /* Transmitter Status Change Enable 1 */ - byte RSTATE0 :1; /* Receiver Status Change Enable 0 */ - byte RSTATE1 :1; /* Receiver Status Change Enable 1 */ - byte CSCIE :1; /* CAN Status Change Interrupt Enable */ - byte WUPIE :1; /* Wake-up Interrupt Enable */ - } Bits; - struct { - byte :1; - byte :1; - byte grpTSTATE :2; - byte grpRSTATE :2; - byte :1; - byte :1; - } MergedBits; -} CAN2RIERSTR; -extern volatile CAN2RIERSTR _CAN2RIER @(REG_BASE + 0x000001C5); -#define CAN2RIER _CAN2RIER.Byte -#define CAN2RIER_RXFIE _CAN2RIER.Bits.RXFIE -#define CAN2RIER_OVRIE _CAN2RIER.Bits.OVRIE -#define CAN2RIER_TSTATE0 _CAN2RIER.Bits.TSTATE0 -#define CAN2RIER_TSTATE1 _CAN2RIER.Bits.TSTATE1 -#define CAN2RIER_RSTATE0 _CAN2RIER.Bits.RSTATE0 -#define CAN2RIER_RSTATE1 _CAN2RIER.Bits.RSTATE1 -#define CAN2RIER_CSCIE _CAN2RIER.Bits.CSCIE -#define CAN2RIER_WUPIE _CAN2RIER.Bits.WUPIE -#define CAN2RIER_TSTATE _CAN2RIER.MergedBits.grpTSTATE -#define CAN2RIER_RSTATE _CAN2RIER.MergedBits.grpRSTATE - - -/*** CAN2TFLG - MSCAN 2 Transmitter Flag Register; 0x000001C6 ***/ -typedef union { - byte Byte; - struct { - byte TXE0 :1; /* Transmitter Buffer Empty 0 */ - byte TXE1 :1; /* Transmitter Buffer Empty 1 */ - byte TXE2 :1; /* Transmitter Buffer Empty 2 */ - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpTXE :3; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} CAN2TFLGSTR; -extern volatile CAN2TFLGSTR _CAN2TFLG @(REG_BASE + 0x000001C6); -#define CAN2TFLG _CAN2TFLG.Byte -#define CAN2TFLG_TXE0 _CAN2TFLG.Bits.TXE0 -#define CAN2TFLG_TXE1 _CAN2TFLG.Bits.TXE1 -#define CAN2TFLG_TXE2 _CAN2TFLG.Bits.TXE2 -#define CAN2TFLG_TXE _CAN2TFLG.MergedBits.grpTXE - - -/*** CAN2TIER - MSCAN 2 Transmitter Interrupt Enable Register; 0x000001C7 ***/ -typedef union { - byte Byte; - struct { - byte TXEIE0 :1; /* Transmitter Empty Interrupt Enable 0 */ - byte TXEIE1 :1; /* Transmitter Empty Interrupt Enable 1 */ - byte TXEIE2 :1; /* Transmitter Empty Interrupt Enable 2 */ - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpTXEIE :3; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} CAN2TIERSTR; -extern volatile CAN2TIERSTR _CAN2TIER @(REG_BASE + 0x000001C7); -#define CAN2TIER _CAN2TIER.Byte -#define CAN2TIER_TXEIE0 _CAN2TIER.Bits.TXEIE0 -#define CAN2TIER_TXEIE1 _CAN2TIER.Bits.TXEIE1 -#define CAN2TIER_TXEIE2 _CAN2TIER.Bits.TXEIE2 -#define CAN2TIER_TXEIE _CAN2TIER.MergedBits.grpTXEIE - - -/*** CAN2TARQ - MSCAN 2 Transmitter Message Abort Request; 0x000001C8 ***/ -typedef union { - byte Byte; - struct { - byte ABTRQ0 :1; /* Abort Request 0 */ - byte ABTRQ1 :1; /* Abort Request 1 */ - byte ABTRQ2 :1; /* Abort Request 2 */ - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpABTRQ :3; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} CAN2TARQSTR; -extern volatile CAN2TARQSTR _CAN2TARQ @(REG_BASE + 0x000001C8); -#define CAN2TARQ _CAN2TARQ.Byte -#define CAN2TARQ_ABTRQ0 _CAN2TARQ.Bits.ABTRQ0 -#define CAN2TARQ_ABTRQ1 _CAN2TARQ.Bits.ABTRQ1 -#define CAN2TARQ_ABTRQ2 _CAN2TARQ.Bits.ABTRQ2 -#define CAN2TARQ_ABTRQ _CAN2TARQ.MergedBits.grpABTRQ - - -/*** CAN2TAAK - MSCAN 2 Transmitter Message Abort Control; 0x000001C9 ***/ -typedef union { - byte Byte; - struct { - byte ABTAK0 :1; /* Abort Acknowledge 0 */ - byte ABTAK1 :1; /* Abort Acknowledge 1 */ - byte ABTAK2 :1; /* Abort Acknowledge 2 */ - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpABTAK :3; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} CAN2TAAKSTR; -extern volatile CAN2TAAKSTR _CAN2TAAK @(REG_BASE + 0x000001C9); -#define CAN2TAAK _CAN2TAAK.Byte -#define CAN2TAAK_ABTAK0 _CAN2TAAK.Bits.ABTAK0 -#define CAN2TAAK_ABTAK1 _CAN2TAAK.Bits.ABTAK1 -#define CAN2TAAK_ABTAK2 _CAN2TAAK.Bits.ABTAK2 -#define CAN2TAAK_ABTAK _CAN2TAAK.MergedBits.grpABTAK - - -/*** CAN2TBSEL - MSCAN 2 Transmit Buffer Selection; 0x000001CA ***/ -typedef union { - byte Byte; - struct { - byte TX0 :1; /* Transmit Buffer Select 0 */ - byte TX1 :1; /* Transmit Buffer Select 1 */ - byte TX2 :1; /* Transmit Buffer Select 2 */ - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpTX :3; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} CAN2TBSELSTR; -extern volatile CAN2TBSELSTR _CAN2TBSEL @(REG_BASE + 0x000001CA); -#define CAN2TBSEL _CAN2TBSEL.Byte -#define CAN2TBSEL_TX0 _CAN2TBSEL.Bits.TX0 -#define CAN2TBSEL_TX1 _CAN2TBSEL.Bits.TX1 -#define CAN2TBSEL_TX2 _CAN2TBSEL.Bits.TX2 -#define CAN2TBSEL_TX _CAN2TBSEL.MergedBits.grpTX - - -/*** CAN2IDAC - MSCAN 2 Identifier Acceptance Control Register; 0x000001CB ***/ -typedef union { - byte Byte; - struct { - byte IDHIT0 :1; /* Identifier Acceptance Hit Indicator 0 */ - byte IDHIT1 :1; /* Identifier Acceptance Hit Indicator 1 */ - byte IDHIT2 :1; /* Identifier Acceptance Hit Indicator 2 */ - byte :1; - byte IDAM0 :1; /* Identifier Acceptance Mode 0 */ - byte IDAM1 :1; /* Identifier Acceptance Mode 1 */ - byte :1; - byte :1; - } Bits; - struct { - byte grpIDHIT :3; - byte :1; - byte grpIDAM :2; - byte :1; - byte :1; - } MergedBits; -} CAN2IDACSTR; -extern volatile CAN2IDACSTR _CAN2IDAC @(REG_BASE + 0x000001CB); -#define CAN2IDAC _CAN2IDAC.Byte -#define CAN2IDAC_IDHIT0 _CAN2IDAC.Bits.IDHIT0 -#define CAN2IDAC_IDHIT1 _CAN2IDAC.Bits.IDHIT1 -#define CAN2IDAC_IDHIT2 _CAN2IDAC.Bits.IDHIT2 -#define CAN2IDAC_IDAM0 _CAN2IDAC.Bits.IDAM0 -#define CAN2IDAC_IDAM1 _CAN2IDAC.Bits.IDAM1 -#define CAN2IDAC_IDHIT _CAN2IDAC.MergedBits.grpIDHIT -#define CAN2IDAC_IDAM _CAN2IDAC.MergedBits.grpIDAM - - -/*** CAN2RXERR - MSCAN 2 Receive Error Counter Register; 0x000001CE ***/ -typedef union { - byte Byte; - struct { - byte RXERR0 :1; /* Bit 0 */ - byte RXERR1 :1; /* Bit 1 */ - byte RXERR2 :1; /* Bit 2 */ - byte RXERR3 :1; /* Bit 3 */ - byte RXERR4 :1; /* Bit 4 */ - byte RXERR5 :1; /* Bit 5 */ - byte RXERR6 :1; /* Bit 6 */ - byte RXERR7 :1; /* Bit 7 */ - } Bits; - struct { - byte grpRXERR :8; - } MergedBits; -} CAN2RXERRSTR; -extern volatile CAN2RXERRSTR _CAN2RXERR @(REG_BASE + 0x000001CE); -#define CAN2RXERR _CAN2RXERR.Byte -#define CAN2RXERR_RXERR0 _CAN2RXERR.Bits.RXERR0 -#define CAN2RXERR_RXERR1 _CAN2RXERR.Bits.RXERR1 -#define CAN2RXERR_RXERR2 _CAN2RXERR.Bits.RXERR2 -#define CAN2RXERR_RXERR3 _CAN2RXERR.Bits.RXERR3 -#define CAN2RXERR_RXERR4 _CAN2RXERR.Bits.RXERR4 -#define CAN2RXERR_RXERR5 _CAN2RXERR.Bits.RXERR5 -#define CAN2RXERR_RXERR6 _CAN2RXERR.Bits.RXERR6 -#define CAN2RXERR_RXERR7 _CAN2RXERR.Bits.RXERR7 -#define CAN2RXERR_RXERR _CAN2RXERR.MergedBits.grpRXERR - - -/*** CAN2TXERR - MSCAN 2 Transmit Error Counter Register; 0x000001CF ***/ -typedef union { - byte Byte; - struct { - byte TXERR0 :1; /* Bit 0 */ - byte TXERR1 :1; /* Bit 1 */ - byte TXERR2 :1; /* Bit 2 */ - byte TXERR3 :1; /* Bit 3 */ - byte TXERR4 :1; /* Bit 4 */ - byte TXERR5 :1; /* Bit 5 */ - byte TXERR6 :1; /* Bit 6 */ - byte TXERR7 :1; /* Bit 7 */ - } Bits; - struct { - byte grpTXERR :8; - } MergedBits; -} CAN2TXERRSTR; -extern volatile CAN2TXERRSTR _CAN2TXERR @(REG_BASE + 0x000001CF); -#define CAN2TXERR _CAN2TXERR.Byte -#define CAN2TXERR_TXERR0 _CAN2TXERR.Bits.TXERR0 -#define CAN2TXERR_TXERR1 _CAN2TXERR.Bits.TXERR1 -#define CAN2TXERR_TXERR2 _CAN2TXERR.Bits.TXERR2 -#define CAN2TXERR_TXERR3 _CAN2TXERR.Bits.TXERR3 -#define CAN2TXERR_TXERR4 _CAN2TXERR.Bits.TXERR4 -#define CAN2TXERR_TXERR5 _CAN2TXERR.Bits.TXERR5 -#define CAN2TXERR_TXERR6 _CAN2TXERR.Bits.TXERR6 -#define CAN2TXERR_TXERR7 _CAN2TXERR.Bits.TXERR7 -#define CAN2TXERR_TXERR _CAN2TXERR.MergedBits.grpTXERR - - -/*** CAN2IDAR0 - MSCAN 2 Identifier Acceptance Register 0; 0x000001D0 ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CAN2IDAR0STR; -extern volatile CAN2IDAR0STR _CAN2IDAR0 @(REG_BASE + 0x000001D0); -#define CAN2IDAR0 _CAN2IDAR0.Byte -#define CAN2IDAR0_AC0 _CAN2IDAR0.Bits.AC0 -#define CAN2IDAR0_AC1 _CAN2IDAR0.Bits.AC1 -#define CAN2IDAR0_AC2 _CAN2IDAR0.Bits.AC2 -#define CAN2IDAR0_AC3 _CAN2IDAR0.Bits.AC3 -#define CAN2IDAR0_AC4 _CAN2IDAR0.Bits.AC4 -#define CAN2IDAR0_AC5 _CAN2IDAR0.Bits.AC5 -#define CAN2IDAR0_AC6 _CAN2IDAR0.Bits.AC6 -#define CAN2IDAR0_AC7 _CAN2IDAR0.Bits.AC7 -#define CAN2IDAR0_AC _CAN2IDAR0.MergedBits.grpAC - - -/*** CAN2IDAR1 - MSCAN 2 Identifier Acceptance Register 1; 0x000001D1 ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CAN2IDAR1STR; -extern volatile CAN2IDAR1STR _CAN2IDAR1 @(REG_BASE + 0x000001D1); -#define CAN2IDAR1 _CAN2IDAR1.Byte -#define CAN2IDAR1_AC0 _CAN2IDAR1.Bits.AC0 -#define CAN2IDAR1_AC1 _CAN2IDAR1.Bits.AC1 -#define CAN2IDAR1_AC2 _CAN2IDAR1.Bits.AC2 -#define CAN2IDAR1_AC3 _CAN2IDAR1.Bits.AC3 -#define CAN2IDAR1_AC4 _CAN2IDAR1.Bits.AC4 -#define CAN2IDAR1_AC5 _CAN2IDAR1.Bits.AC5 -#define CAN2IDAR1_AC6 _CAN2IDAR1.Bits.AC6 -#define CAN2IDAR1_AC7 _CAN2IDAR1.Bits.AC7 -#define CAN2IDAR1_AC _CAN2IDAR1.MergedBits.grpAC - - -/*** CAN2IDAR2 - MSCAN 2 Identifier Acceptance Register 2; 0x000001D2 ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CAN2IDAR2STR; -extern volatile CAN2IDAR2STR _CAN2IDAR2 @(REG_BASE + 0x000001D2); -#define CAN2IDAR2 _CAN2IDAR2.Byte -#define CAN2IDAR2_AC0 _CAN2IDAR2.Bits.AC0 -#define CAN2IDAR2_AC1 _CAN2IDAR2.Bits.AC1 -#define CAN2IDAR2_AC2 _CAN2IDAR2.Bits.AC2 -#define CAN2IDAR2_AC3 _CAN2IDAR2.Bits.AC3 -#define CAN2IDAR2_AC4 _CAN2IDAR2.Bits.AC4 -#define CAN2IDAR2_AC5 _CAN2IDAR2.Bits.AC5 -#define CAN2IDAR2_AC6 _CAN2IDAR2.Bits.AC6 -#define CAN2IDAR2_AC7 _CAN2IDAR2.Bits.AC7 -#define CAN2IDAR2_AC _CAN2IDAR2.MergedBits.grpAC - - -/*** CAN2IDAR3 - MSCAN 2 Identifier Acceptance Register 3; 0x000001D3 ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CAN2IDAR3STR; -extern volatile CAN2IDAR3STR _CAN2IDAR3 @(REG_BASE + 0x000001D3); -#define CAN2IDAR3 _CAN2IDAR3.Byte -#define CAN2IDAR3_AC0 _CAN2IDAR3.Bits.AC0 -#define CAN2IDAR3_AC1 _CAN2IDAR3.Bits.AC1 -#define CAN2IDAR3_AC2 _CAN2IDAR3.Bits.AC2 -#define CAN2IDAR3_AC3 _CAN2IDAR3.Bits.AC3 -#define CAN2IDAR3_AC4 _CAN2IDAR3.Bits.AC4 -#define CAN2IDAR3_AC5 _CAN2IDAR3.Bits.AC5 -#define CAN2IDAR3_AC6 _CAN2IDAR3.Bits.AC6 -#define CAN2IDAR3_AC7 _CAN2IDAR3.Bits.AC7 -#define CAN2IDAR3_AC _CAN2IDAR3.MergedBits.grpAC - - -/*** CAN2IDMR0 - MSCAN 2 Identifier Mask Register 0; 0x000001D4 ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CAN2IDMR0STR; -extern volatile CAN2IDMR0STR _CAN2IDMR0 @(REG_BASE + 0x000001D4); -#define CAN2IDMR0 _CAN2IDMR0.Byte -#define CAN2IDMR0_AM0 _CAN2IDMR0.Bits.AM0 -#define CAN2IDMR0_AM1 _CAN2IDMR0.Bits.AM1 -#define CAN2IDMR0_AM2 _CAN2IDMR0.Bits.AM2 -#define CAN2IDMR0_AM3 _CAN2IDMR0.Bits.AM3 -#define CAN2IDMR0_AM4 _CAN2IDMR0.Bits.AM4 -#define CAN2IDMR0_AM5 _CAN2IDMR0.Bits.AM5 -#define CAN2IDMR0_AM6 _CAN2IDMR0.Bits.AM6 -#define CAN2IDMR0_AM7 _CAN2IDMR0.Bits.AM7 -#define CAN2IDMR0_AM _CAN2IDMR0.MergedBits.grpAM - - -/*** CAN2IDMR1 - MSCAN 2 Identifier Mask Register 1; 0x000001D5 ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CAN2IDMR1STR; -extern volatile CAN2IDMR1STR _CAN2IDMR1 @(REG_BASE + 0x000001D5); -#define CAN2IDMR1 _CAN2IDMR1.Byte -#define CAN2IDMR1_AM0 _CAN2IDMR1.Bits.AM0 -#define CAN2IDMR1_AM1 _CAN2IDMR1.Bits.AM1 -#define CAN2IDMR1_AM2 _CAN2IDMR1.Bits.AM2 -#define CAN2IDMR1_AM3 _CAN2IDMR1.Bits.AM3 -#define CAN2IDMR1_AM4 _CAN2IDMR1.Bits.AM4 -#define CAN2IDMR1_AM5 _CAN2IDMR1.Bits.AM5 -#define CAN2IDMR1_AM6 _CAN2IDMR1.Bits.AM6 -#define CAN2IDMR1_AM7 _CAN2IDMR1.Bits.AM7 -#define CAN2IDMR1_AM _CAN2IDMR1.MergedBits.grpAM - - -/*** CAN2IDMR2 - MSCAN 2 Identifier Mask Register 2; 0x000001D6 ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CAN2IDMR2STR; -extern volatile CAN2IDMR2STR _CAN2IDMR2 @(REG_BASE + 0x000001D6); -#define CAN2IDMR2 _CAN2IDMR2.Byte -#define CAN2IDMR2_AM0 _CAN2IDMR2.Bits.AM0 -#define CAN2IDMR2_AM1 _CAN2IDMR2.Bits.AM1 -#define CAN2IDMR2_AM2 _CAN2IDMR2.Bits.AM2 -#define CAN2IDMR2_AM3 _CAN2IDMR2.Bits.AM3 -#define CAN2IDMR2_AM4 _CAN2IDMR2.Bits.AM4 -#define CAN2IDMR2_AM5 _CAN2IDMR2.Bits.AM5 -#define CAN2IDMR2_AM6 _CAN2IDMR2.Bits.AM6 -#define CAN2IDMR2_AM7 _CAN2IDMR2.Bits.AM7 -#define CAN2IDMR2_AM _CAN2IDMR2.MergedBits.grpAM - - -/*** CAN2IDMR3 - MSCAN 2 Identifier Mask Register 3; 0x000001D7 ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CAN2IDMR3STR; -extern volatile CAN2IDMR3STR _CAN2IDMR3 @(REG_BASE + 0x000001D7); -#define CAN2IDMR3 _CAN2IDMR3.Byte -#define CAN2IDMR3_AM0 _CAN2IDMR3.Bits.AM0 -#define CAN2IDMR3_AM1 _CAN2IDMR3.Bits.AM1 -#define CAN2IDMR3_AM2 _CAN2IDMR3.Bits.AM2 -#define CAN2IDMR3_AM3 _CAN2IDMR3.Bits.AM3 -#define CAN2IDMR3_AM4 _CAN2IDMR3.Bits.AM4 -#define CAN2IDMR3_AM5 _CAN2IDMR3.Bits.AM5 -#define CAN2IDMR3_AM6 _CAN2IDMR3.Bits.AM6 -#define CAN2IDMR3_AM7 _CAN2IDMR3.Bits.AM7 -#define CAN2IDMR3_AM _CAN2IDMR3.MergedBits.grpAM - - -/*** CAN2IDAR4 - MSCAN 2 Identifier Acceptance Register 4; 0x000001D8 ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CAN2IDAR4STR; -extern volatile CAN2IDAR4STR _CAN2IDAR4 @(REG_BASE + 0x000001D8); -#define CAN2IDAR4 _CAN2IDAR4.Byte -#define CAN2IDAR4_AC0 _CAN2IDAR4.Bits.AC0 -#define CAN2IDAR4_AC1 _CAN2IDAR4.Bits.AC1 -#define CAN2IDAR4_AC2 _CAN2IDAR4.Bits.AC2 -#define CAN2IDAR4_AC3 _CAN2IDAR4.Bits.AC3 -#define CAN2IDAR4_AC4 _CAN2IDAR4.Bits.AC4 -#define CAN2IDAR4_AC5 _CAN2IDAR4.Bits.AC5 -#define CAN2IDAR4_AC6 _CAN2IDAR4.Bits.AC6 -#define CAN2IDAR4_AC7 _CAN2IDAR4.Bits.AC7 -#define CAN2IDAR4_AC _CAN2IDAR4.MergedBits.grpAC - - -/*** CAN2IDAR5 - MSCAN 2 Identifier Acceptance Register 5; 0x000001D9 ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CAN2IDAR5STR; -extern volatile CAN2IDAR5STR _CAN2IDAR5 @(REG_BASE + 0x000001D9); -#define CAN2IDAR5 _CAN2IDAR5.Byte -#define CAN2IDAR5_AC0 _CAN2IDAR5.Bits.AC0 -#define CAN2IDAR5_AC1 _CAN2IDAR5.Bits.AC1 -#define CAN2IDAR5_AC2 _CAN2IDAR5.Bits.AC2 -#define CAN2IDAR5_AC3 _CAN2IDAR5.Bits.AC3 -#define CAN2IDAR5_AC4 _CAN2IDAR5.Bits.AC4 -#define CAN2IDAR5_AC5 _CAN2IDAR5.Bits.AC5 -#define CAN2IDAR5_AC6 _CAN2IDAR5.Bits.AC6 -#define CAN2IDAR5_AC7 _CAN2IDAR5.Bits.AC7 -#define CAN2IDAR5_AC _CAN2IDAR5.MergedBits.grpAC - - -/*** CAN2IDAR6 - MSCAN 2 Identifier Acceptance Register 6; 0x000001DA ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CAN2IDAR6STR; -extern volatile CAN2IDAR6STR _CAN2IDAR6 @(REG_BASE + 0x000001DA); -#define CAN2IDAR6 _CAN2IDAR6.Byte -#define CAN2IDAR6_AC0 _CAN2IDAR6.Bits.AC0 -#define CAN2IDAR6_AC1 _CAN2IDAR6.Bits.AC1 -#define CAN2IDAR6_AC2 _CAN2IDAR6.Bits.AC2 -#define CAN2IDAR6_AC3 _CAN2IDAR6.Bits.AC3 -#define CAN2IDAR6_AC4 _CAN2IDAR6.Bits.AC4 -#define CAN2IDAR6_AC5 _CAN2IDAR6.Bits.AC5 -#define CAN2IDAR6_AC6 _CAN2IDAR6.Bits.AC6 -#define CAN2IDAR6_AC7 _CAN2IDAR6.Bits.AC7 -#define CAN2IDAR6_AC _CAN2IDAR6.MergedBits.grpAC - - -/*** CAN2IDAR7 - MSCAN 2 Identifier Acceptance Register 7; 0x000001DB ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CAN2IDAR7STR; -extern volatile CAN2IDAR7STR _CAN2IDAR7 @(REG_BASE + 0x000001DB); -#define CAN2IDAR7 _CAN2IDAR7.Byte -#define CAN2IDAR7_AC0 _CAN2IDAR7.Bits.AC0 -#define CAN2IDAR7_AC1 _CAN2IDAR7.Bits.AC1 -#define CAN2IDAR7_AC2 _CAN2IDAR7.Bits.AC2 -#define CAN2IDAR7_AC3 _CAN2IDAR7.Bits.AC3 -#define CAN2IDAR7_AC4 _CAN2IDAR7.Bits.AC4 -#define CAN2IDAR7_AC5 _CAN2IDAR7.Bits.AC5 -#define CAN2IDAR7_AC6 _CAN2IDAR7.Bits.AC6 -#define CAN2IDAR7_AC7 _CAN2IDAR7.Bits.AC7 -#define CAN2IDAR7_AC _CAN2IDAR7.MergedBits.grpAC - - -/*** CAN2IDMR4 - MSCAN 2 Identifier Mask Register 4; 0x000001DC ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CAN2IDMR4STR; -extern volatile CAN2IDMR4STR _CAN2IDMR4 @(REG_BASE + 0x000001DC); -#define CAN2IDMR4 _CAN2IDMR4.Byte -#define CAN2IDMR4_AM0 _CAN2IDMR4.Bits.AM0 -#define CAN2IDMR4_AM1 _CAN2IDMR4.Bits.AM1 -#define CAN2IDMR4_AM2 _CAN2IDMR4.Bits.AM2 -#define CAN2IDMR4_AM3 _CAN2IDMR4.Bits.AM3 -#define CAN2IDMR4_AM4 _CAN2IDMR4.Bits.AM4 -#define CAN2IDMR4_AM5 _CAN2IDMR4.Bits.AM5 -#define CAN2IDMR4_AM6 _CAN2IDMR4.Bits.AM6 -#define CAN2IDMR4_AM7 _CAN2IDMR4.Bits.AM7 -#define CAN2IDMR4_AM _CAN2IDMR4.MergedBits.grpAM - - -/*** CAN2IDMR5 - MSCAN 2 Identifier Mask Register 5; 0x000001DD ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CAN2IDMR5STR; -extern volatile CAN2IDMR5STR _CAN2IDMR5 @(REG_BASE + 0x000001DD); -#define CAN2IDMR5 _CAN2IDMR5.Byte -#define CAN2IDMR5_AM0 _CAN2IDMR5.Bits.AM0 -#define CAN2IDMR5_AM1 _CAN2IDMR5.Bits.AM1 -#define CAN2IDMR5_AM2 _CAN2IDMR5.Bits.AM2 -#define CAN2IDMR5_AM3 _CAN2IDMR5.Bits.AM3 -#define CAN2IDMR5_AM4 _CAN2IDMR5.Bits.AM4 -#define CAN2IDMR5_AM5 _CAN2IDMR5.Bits.AM5 -#define CAN2IDMR5_AM6 _CAN2IDMR5.Bits.AM6 -#define CAN2IDMR5_AM7 _CAN2IDMR5.Bits.AM7 -#define CAN2IDMR5_AM _CAN2IDMR5.MergedBits.grpAM - - -/*** CAN2IDMR6 - MSCAN 2 Identifier Mask Register 6; 0x000001DE ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CAN2IDMR6STR; -extern volatile CAN2IDMR6STR _CAN2IDMR6 @(REG_BASE + 0x000001DE); -#define CAN2IDMR6 _CAN2IDMR6.Byte -#define CAN2IDMR6_AM0 _CAN2IDMR6.Bits.AM0 -#define CAN2IDMR6_AM1 _CAN2IDMR6.Bits.AM1 -#define CAN2IDMR6_AM2 _CAN2IDMR6.Bits.AM2 -#define CAN2IDMR6_AM3 _CAN2IDMR6.Bits.AM3 -#define CAN2IDMR6_AM4 _CAN2IDMR6.Bits.AM4 -#define CAN2IDMR6_AM5 _CAN2IDMR6.Bits.AM5 -#define CAN2IDMR6_AM6 _CAN2IDMR6.Bits.AM6 -#define CAN2IDMR6_AM7 _CAN2IDMR6.Bits.AM7 -#define CAN2IDMR6_AM _CAN2IDMR6.MergedBits.grpAM - - -/*** CAN2IDMR7 - MSCAN 2 Identifier Mask Register 7; 0x000001DF ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CAN2IDMR7STR; -extern volatile CAN2IDMR7STR _CAN2IDMR7 @(REG_BASE + 0x000001DF); -#define CAN2IDMR7 _CAN2IDMR7.Byte -#define CAN2IDMR7_AM0 _CAN2IDMR7.Bits.AM0 -#define CAN2IDMR7_AM1 _CAN2IDMR7.Bits.AM1 -#define CAN2IDMR7_AM2 _CAN2IDMR7.Bits.AM2 -#define CAN2IDMR7_AM3 _CAN2IDMR7.Bits.AM3 -#define CAN2IDMR7_AM4 _CAN2IDMR7.Bits.AM4 -#define CAN2IDMR7_AM5 _CAN2IDMR7.Bits.AM5 -#define CAN2IDMR7_AM6 _CAN2IDMR7.Bits.AM6 -#define CAN2IDMR7_AM7 _CAN2IDMR7.Bits.AM7 -#define CAN2IDMR7_AM _CAN2IDMR7.MergedBits.grpAM - - -/*** CAN2RXIDR0 - MSCAN 2 Receive Identifier Register 0; 0x000001E0 ***/ -typedef union { - byte Byte; - struct { - byte ID21 :1; /* Extended format identifier Bit 21 */ - byte ID22 :1; /* Extended format identifier Bit 22 */ - byte ID23 :1; /* Extended format identifier Bit 23 */ - byte ID24 :1; /* Extended format identifier Bit 24 */ - byte ID25 :1; /* Extended format identifier Bit 25 */ - byte ID26 :1; /* Extended format identifier Bit 26 */ - byte ID27 :1; /* Extended format identifier Bit 27 */ - byte ID28 :1; /* Extended format identifier Bit 28 */ - } Bits; - struct { - byte grpID_21 :8; - } MergedBits; -} CAN2RXIDR0STR; -extern volatile CAN2RXIDR0STR _CAN2RXIDR0 @(REG_BASE + 0x000001E0); -#define CAN2RXIDR0 _CAN2RXIDR0.Byte -#define CAN2RXIDR0_ID21 _CAN2RXIDR0.Bits.ID21 -#define CAN2RXIDR0_ID22 _CAN2RXIDR0.Bits.ID22 -#define CAN2RXIDR0_ID23 _CAN2RXIDR0.Bits.ID23 -#define CAN2RXIDR0_ID24 _CAN2RXIDR0.Bits.ID24 -#define CAN2RXIDR0_ID25 _CAN2RXIDR0.Bits.ID25 -#define CAN2RXIDR0_ID26 _CAN2RXIDR0.Bits.ID26 -#define CAN2RXIDR0_ID27 _CAN2RXIDR0.Bits.ID27 -#define CAN2RXIDR0_ID28 _CAN2RXIDR0.Bits.ID28 -#define CAN2RXIDR0_ID_21 _CAN2RXIDR0.MergedBits.grpID_21 -#define CAN2RXIDR0_ID CAN2RXIDR0_ID_21 - - -/*** CAN2RXIDR1 - MSCAN 2 Receive Identifier Register 1; 0x000001E1 ***/ -typedef union { - byte Byte; - struct { - byte ID15 :1; /* Extended format identifier Bit 15 */ - byte ID16 :1; /* Extended format identifier Bit 16 */ - byte ID17 :1; /* Extended format identifier Bit 17 */ - byte IDE :1; /* ID Extended */ - byte SRR :1; /* Substitute Remote Request */ - byte ID18 :1; /* Extended format identifier Bit 18 */ - byte ID19 :1; /* Extended format identifier Bit 19 */ - byte ID20 :1; /* Extended format identifier Bit 20 */ - } Bits; - struct { - byte grpID_15 :3; - byte :1; - byte :1; - byte grpID_18 :3; - } MergedBits; -} CAN2RXIDR1STR; -extern volatile CAN2RXIDR1STR _CAN2RXIDR1 @(REG_BASE + 0x000001E1); -#define CAN2RXIDR1 _CAN2RXIDR1.Byte -#define CAN2RXIDR1_ID15 _CAN2RXIDR1.Bits.ID15 -#define CAN2RXIDR1_ID16 _CAN2RXIDR1.Bits.ID16 -#define CAN2RXIDR1_ID17 _CAN2RXIDR1.Bits.ID17 -#define CAN2RXIDR1_IDE _CAN2RXIDR1.Bits.IDE -#define CAN2RXIDR1_SRR _CAN2RXIDR1.Bits.SRR -#define CAN2RXIDR1_ID18 _CAN2RXIDR1.Bits.ID18 -#define CAN2RXIDR1_ID19 _CAN2RXIDR1.Bits.ID19 -#define CAN2RXIDR1_ID20 _CAN2RXIDR1.Bits.ID20 -#define CAN2RXIDR1_ID_15 _CAN2RXIDR1.MergedBits.grpID_15 -#define CAN2RXIDR1_ID_18 _CAN2RXIDR1.MergedBits.grpID_18 -#define CAN2RXIDR1_ID CAN2RXIDR1_ID_15 - - -/*** CAN2RXIDR2 - MSCAN 2 Receive Identifier Register 2; 0x000001E2 ***/ -typedef union { - byte Byte; - struct { - byte ID7 :1; /* Extended format identifier Bit 7 */ - byte ID8 :1; /* Extended format identifier Bit 8 */ - byte ID9 :1; /* Extended format identifier Bit 9 */ - byte ID10 :1; /* Extended format identifier Bit 10 */ - byte ID11 :1; /* Extended format identifier Bit 11 */ - byte ID12 :1; /* Extended format identifier Bit 12 */ - byte ID13 :1; /* Extended format identifier Bit 13 */ - byte ID14 :1; /* Extended format identifier Bit 14 */ - } Bits; - struct { - byte grpID_7 :8; - } MergedBits; -} CAN2RXIDR2STR; -extern volatile CAN2RXIDR2STR _CAN2RXIDR2 @(REG_BASE + 0x000001E2); -#define CAN2RXIDR2 _CAN2RXIDR2.Byte -#define CAN2RXIDR2_ID7 _CAN2RXIDR2.Bits.ID7 -#define CAN2RXIDR2_ID8 _CAN2RXIDR2.Bits.ID8 -#define CAN2RXIDR2_ID9 _CAN2RXIDR2.Bits.ID9 -#define CAN2RXIDR2_ID10 _CAN2RXIDR2.Bits.ID10 -#define CAN2RXIDR2_ID11 _CAN2RXIDR2.Bits.ID11 -#define CAN2RXIDR2_ID12 _CAN2RXIDR2.Bits.ID12 -#define CAN2RXIDR2_ID13 _CAN2RXIDR2.Bits.ID13 -#define CAN2RXIDR2_ID14 _CAN2RXIDR2.Bits.ID14 -#define CAN2RXIDR2_ID_7 _CAN2RXIDR2.MergedBits.grpID_7 -#define CAN2RXIDR2_ID CAN2RXIDR2_ID_7 - - -/*** CAN2RXIDR3 - MSCAN 2 Receive Identifier Register 3; 0x000001E3 ***/ -typedef union { - byte Byte; - struct { - byte RTR :1; /* Remote Transmission Request */ - byte ID0 :1; /* Extended format identifier Bit 0 */ - byte ID1 :1; /* Extended format identifier Bit 1 */ - byte ID2 :1; /* Extended format identifier Bit 2 */ - byte ID3 :1; /* Extended format identifier Bit 3 */ - byte ID4 :1; /* Extended format identifier Bit 4 */ - byte ID5 :1; /* Extended format identifier Bit 5 */ - byte ID6 :1; /* Extended format identifier Bit 6 */ - } Bits; - struct { - byte :1; - byte grpID :7; - } MergedBits; -} CAN2RXIDR3STR; -extern volatile CAN2RXIDR3STR _CAN2RXIDR3 @(REG_BASE + 0x000001E3); -#define CAN2RXIDR3 _CAN2RXIDR3.Byte -#define CAN2RXIDR3_RTR _CAN2RXIDR3.Bits.RTR -#define CAN2RXIDR3_ID0 _CAN2RXIDR3.Bits.ID0 -#define CAN2RXIDR3_ID1 _CAN2RXIDR3.Bits.ID1 -#define CAN2RXIDR3_ID2 _CAN2RXIDR3.Bits.ID2 -#define CAN2RXIDR3_ID3 _CAN2RXIDR3.Bits.ID3 -#define CAN2RXIDR3_ID4 _CAN2RXIDR3.Bits.ID4 -#define CAN2RXIDR3_ID5 _CAN2RXIDR3.Bits.ID5 -#define CAN2RXIDR3_ID6 _CAN2RXIDR3.Bits.ID6 -#define CAN2RXIDR3_ID _CAN2RXIDR3.MergedBits.grpID - - -/*** CAN2RXDSR0 - MSCAN 2 Receive Data Segment Register 0; 0x000001E4 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN2RXDSR0STR; -extern volatile CAN2RXDSR0STR _CAN2RXDSR0 @(REG_BASE + 0x000001E4); -#define CAN2RXDSR0 _CAN2RXDSR0.Byte -#define CAN2RXDSR0_DB0 _CAN2RXDSR0.Bits.DB0 -#define CAN2RXDSR0_DB1 _CAN2RXDSR0.Bits.DB1 -#define CAN2RXDSR0_DB2 _CAN2RXDSR0.Bits.DB2 -#define CAN2RXDSR0_DB3 _CAN2RXDSR0.Bits.DB3 -#define CAN2RXDSR0_DB4 _CAN2RXDSR0.Bits.DB4 -#define CAN2RXDSR0_DB5 _CAN2RXDSR0.Bits.DB5 -#define CAN2RXDSR0_DB6 _CAN2RXDSR0.Bits.DB6 -#define CAN2RXDSR0_DB7 _CAN2RXDSR0.Bits.DB7 -#define CAN2RXDSR0_DB _CAN2RXDSR0.MergedBits.grpDB - - -/*** CAN2RXDSR1 - MSCAN 2 Receive Data Segment Register 1; 0x000001E5 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN2RXDSR1STR; -extern volatile CAN2RXDSR1STR _CAN2RXDSR1 @(REG_BASE + 0x000001E5); -#define CAN2RXDSR1 _CAN2RXDSR1.Byte -#define CAN2RXDSR1_DB0 _CAN2RXDSR1.Bits.DB0 -#define CAN2RXDSR1_DB1 _CAN2RXDSR1.Bits.DB1 -#define CAN2RXDSR1_DB2 _CAN2RXDSR1.Bits.DB2 -#define CAN2RXDSR1_DB3 _CAN2RXDSR1.Bits.DB3 -#define CAN2RXDSR1_DB4 _CAN2RXDSR1.Bits.DB4 -#define CAN2RXDSR1_DB5 _CAN2RXDSR1.Bits.DB5 -#define CAN2RXDSR1_DB6 _CAN2RXDSR1.Bits.DB6 -#define CAN2RXDSR1_DB7 _CAN2RXDSR1.Bits.DB7 -#define CAN2RXDSR1_DB _CAN2RXDSR1.MergedBits.grpDB - - -/*** CAN2RXDSR2 - MSCAN 2 Receive Data Segment Register 2; 0x000001E6 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN2RXDSR2STR; -extern volatile CAN2RXDSR2STR _CAN2RXDSR2 @(REG_BASE + 0x000001E6); -#define CAN2RXDSR2 _CAN2RXDSR2.Byte -#define CAN2RXDSR2_DB0 _CAN2RXDSR2.Bits.DB0 -#define CAN2RXDSR2_DB1 _CAN2RXDSR2.Bits.DB1 -#define CAN2RXDSR2_DB2 _CAN2RXDSR2.Bits.DB2 -#define CAN2RXDSR2_DB3 _CAN2RXDSR2.Bits.DB3 -#define CAN2RXDSR2_DB4 _CAN2RXDSR2.Bits.DB4 -#define CAN2RXDSR2_DB5 _CAN2RXDSR2.Bits.DB5 -#define CAN2RXDSR2_DB6 _CAN2RXDSR2.Bits.DB6 -#define CAN2RXDSR2_DB7 _CAN2RXDSR2.Bits.DB7 -#define CAN2RXDSR2_DB _CAN2RXDSR2.MergedBits.grpDB - - -/*** CAN2RXDSR3 - MSCAN 2 Receive Data Segment Register 3; 0x000001E7 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN2RXDSR3STR; -extern volatile CAN2RXDSR3STR _CAN2RXDSR3 @(REG_BASE + 0x000001E7); -#define CAN2RXDSR3 _CAN2RXDSR3.Byte -#define CAN2RXDSR3_DB0 _CAN2RXDSR3.Bits.DB0 -#define CAN2RXDSR3_DB1 _CAN2RXDSR3.Bits.DB1 -#define CAN2RXDSR3_DB2 _CAN2RXDSR3.Bits.DB2 -#define CAN2RXDSR3_DB3 _CAN2RXDSR3.Bits.DB3 -#define CAN2RXDSR3_DB4 _CAN2RXDSR3.Bits.DB4 -#define CAN2RXDSR3_DB5 _CAN2RXDSR3.Bits.DB5 -#define CAN2RXDSR3_DB6 _CAN2RXDSR3.Bits.DB6 -#define CAN2RXDSR3_DB7 _CAN2RXDSR3.Bits.DB7 -#define CAN2RXDSR3_DB _CAN2RXDSR3.MergedBits.grpDB - - -/*** CAN2RXDSR4 - MSCAN 2 Receive Data Segment Register 4; 0x000001E8 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN2RXDSR4STR; -extern volatile CAN2RXDSR4STR _CAN2RXDSR4 @(REG_BASE + 0x000001E8); -#define CAN2RXDSR4 _CAN2RXDSR4.Byte -#define CAN2RXDSR4_DB0 _CAN2RXDSR4.Bits.DB0 -#define CAN2RXDSR4_DB1 _CAN2RXDSR4.Bits.DB1 -#define CAN2RXDSR4_DB2 _CAN2RXDSR4.Bits.DB2 -#define CAN2RXDSR4_DB3 _CAN2RXDSR4.Bits.DB3 -#define CAN2RXDSR4_DB4 _CAN2RXDSR4.Bits.DB4 -#define CAN2RXDSR4_DB5 _CAN2RXDSR4.Bits.DB5 -#define CAN2RXDSR4_DB6 _CAN2RXDSR4.Bits.DB6 -#define CAN2RXDSR4_DB7 _CAN2RXDSR4.Bits.DB7 -#define CAN2RXDSR4_DB _CAN2RXDSR4.MergedBits.grpDB - - -/*** CAN2RXDSR5 - MSCAN 2 Receive Data Segment Register 5; 0x000001E9 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN2RXDSR5STR; -extern volatile CAN2RXDSR5STR _CAN2RXDSR5 @(REG_BASE + 0x000001E9); -#define CAN2RXDSR5 _CAN2RXDSR5.Byte -#define CAN2RXDSR5_DB0 _CAN2RXDSR5.Bits.DB0 -#define CAN2RXDSR5_DB1 _CAN2RXDSR5.Bits.DB1 -#define CAN2RXDSR5_DB2 _CAN2RXDSR5.Bits.DB2 -#define CAN2RXDSR5_DB3 _CAN2RXDSR5.Bits.DB3 -#define CAN2RXDSR5_DB4 _CAN2RXDSR5.Bits.DB4 -#define CAN2RXDSR5_DB5 _CAN2RXDSR5.Bits.DB5 -#define CAN2RXDSR5_DB6 _CAN2RXDSR5.Bits.DB6 -#define CAN2RXDSR5_DB7 _CAN2RXDSR5.Bits.DB7 -#define CAN2RXDSR5_DB _CAN2RXDSR5.MergedBits.grpDB - - -/*** CAN2RXDSR6 - MSCAN 2 Receive Data Segment Register 6; 0x000001EA ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN2RXDSR6STR; -extern volatile CAN2RXDSR6STR _CAN2RXDSR6 @(REG_BASE + 0x000001EA); -#define CAN2RXDSR6 _CAN2RXDSR6.Byte -#define CAN2RXDSR6_DB0 _CAN2RXDSR6.Bits.DB0 -#define CAN2RXDSR6_DB1 _CAN2RXDSR6.Bits.DB1 -#define CAN2RXDSR6_DB2 _CAN2RXDSR6.Bits.DB2 -#define CAN2RXDSR6_DB3 _CAN2RXDSR6.Bits.DB3 -#define CAN2RXDSR6_DB4 _CAN2RXDSR6.Bits.DB4 -#define CAN2RXDSR6_DB5 _CAN2RXDSR6.Bits.DB5 -#define CAN2RXDSR6_DB6 _CAN2RXDSR6.Bits.DB6 -#define CAN2RXDSR6_DB7 _CAN2RXDSR6.Bits.DB7 -#define CAN2RXDSR6_DB _CAN2RXDSR6.MergedBits.grpDB - - -/*** CAN2RXDSR7 - MSCAN 2 Receive Data Segment Register 7; 0x000001EB ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN2RXDSR7STR; -extern volatile CAN2RXDSR7STR _CAN2RXDSR7 @(REG_BASE + 0x000001EB); -#define CAN2RXDSR7 _CAN2RXDSR7.Byte -#define CAN2RXDSR7_DB0 _CAN2RXDSR7.Bits.DB0 -#define CAN2RXDSR7_DB1 _CAN2RXDSR7.Bits.DB1 -#define CAN2RXDSR7_DB2 _CAN2RXDSR7.Bits.DB2 -#define CAN2RXDSR7_DB3 _CAN2RXDSR7.Bits.DB3 -#define CAN2RXDSR7_DB4 _CAN2RXDSR7.Bits.DB4 -#define CAN2RXDSR7_DB5 _CAN2RXDSR7.Bits.DB5 -#define CAN2RXDSR7_DB6 _CAN2RXDSR7.Bits.DB6 -#define CAN2RXDSR7_DB7 _CAN2RXDSR7.Bits.DB7 -#define CAN2RXDSR7_DB _CAN2RXDSR7.MergedBits.grpDB - - -/*** CAN2RXDLR - MSCAN 2 Receive Data Length Register; 0x000001EC ***/ -typedef union { - byte Byte; - struct { - byte DLC0 :1; /* Data Length Code Bit 0 */ - byte DLC1 :1; /* Data Length Code Bit 1 */ - byte DLC2 :1; /* Data Length Code Bit 2 */ - byte DLC3 :1; /* Data Length Code Bit 3 */ - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpDLC :4; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} CAN2RXDLRSTR; -extern volatile CAN2RXDLRSTR _CAN2RXDLR @(REG_BASE + 0x000001EC); -#define CAN2RXDLR _CAN2RXDLR.Byte -#define CAN2RXDLR_DLC0 _CAN2RXDLR.Bits.DLC0 -#define CAN2RXDLR_DLC1 _CAN2RXDLR.Bits.DLC1 -#define CAN2RXDLR_DLC2 _CAN2RXDLR.Bits.DLC2 -#define CAN2RXDLR_DLC3 _CAN2RXDLR.Bits.DLC3 -#define CAN2RXDLR_DLC _CAN2RXDLR.MergedBits.grpDLC - - -/*** CAN2TXIDR0 - MSCAN 2 Transmit Identifier Register 0; 0x000001F0 ***/ -typedef union { - byte Byte; - struct { - byte ID21 :1; /* Extended format identifier Bit 21 */ - byte ID22 :1; /* Extended format identifier Bit 22 */ - byte ID23 :1; /* Extended format identifier Bit 23 */ - byte ID24 :1; /* Extended format identifier Bit 24 */ - byte ID25 :1; /* Extended format identifier Bit 25 */ - byte ID26 :1; /* Extended format identifier Bit 26 */ - byte ID27 :1; /* Extended format identifier Bit 27 */ - byte ID28 :1; /* Extended format identifier Bit 28 */ - } Bits; - struct { - byte grpID_21 :8; - } MergedBits; -} CAN2TXIDR0STR; -extern volatile CAN2TXIDR0STR _CAN2TXIDR0 @(REG_BASE + 0x000001F0); -#define CAN2TXIDR0 _CAN2TXIDR0.Byte -#define CAN2TXIDR0_ID21 _CAN2TXIDR0.Bits.ID21 -#define CAN2TXIDR0_ID22 _CAN2TXIDR0.Bits.ID22 -#define CAN2TXIDR0_ID23 _CAN2TXIDR0.Bits.ID23 -#define CAN2TXIDR0_ID24 _CAN2TXIDR0.Bits.ID24 -#define CAN2TXIDR0_ID25 _CAN2TXIDR0.Bits.ID25 -#define CAN2TXIDR0_ID26 _CAN2TXIDR0.Bits.ID26 -#define CAN2TXIDR0_ID27 _CAN2TXIDR0.Bits.ID27 -#define CAN2TXIDR0_ID28 _CAN2TXIDR0.Bits.ID28 -#define CAN2TXIDR0_ID_21 _CAN2TXIDR0.MergedBits.grpID_21 -#define CAN2TXIDR0_ID CAN2TXIDR0_ID_21 - - -/*** CAN2TXIDR1 - MSCAN 2 Transmit Identifier Register 1; 0x000001F1 ***/ -typedef union { - byte Byte; - struct { - byte ID15 :1; /* Extended format identifier Bit 15 */ - byte ID16 :1; /* Extended format identifier Bit 16 */ - byte ID17 :1; /* Extended format identifier Bit 17 */ - byte IDE :1; /* ID Extended */ - byte SRR :1; /* Substitute Remote Request */ - byte ID18 :1; /* Extended format identifier Bit 18 */ - byte ID19 :1; /* Extended format identifier Bit 19 */ - byte ID20 :1; /* Extended format identifier Bit 20 */ - } Bits; - struct { - byte grpID_15 :3; - byte :1; - byte :1; - byte grpID_18 :3; - } MergedBits; -} CAN2TXIDR1STR; -extern volatile CAN2TXIDR1STR _CAN2TXIDR1 @(REG_BASE + 0x000001F1); -#define CAN2TXIDR1 _CAN2TXIDR1.Byte -#define CAN2TXIDR1_ID15 _CAN2TXIDR1.Bits.ID15 -#define CAN2TXIDR1_ID16 _CAN2TXIDR1.Bits.ID16 -#define CAN2TXIDR1_ID17 _CAN2TXIDR1.Bits.ID17 -#define CAN2TXIDR1_IDE _CAN2TXIDR1.Bits.IDE -#define CAN2TXIDR1_SRR _CAN2TXIDR1.Bits.SRR -#define CAN2TXIDR1_ID18 _CAN2TXIDR1.Bits.ID18 -#define CAN2TXIDR1_ID19 _CAN2TXIDR1.Bits.ID19 -#define CAN2TXIDR1_ID20 _CAN2TXIDR1.Bits.ID20 -#define CAN2TXIDR1_ID_15 _CAN2TXIDR1.MergedBits.grpID_15 -#define CAN2TXIDR1_ID_18 _CAN2TXIDR1.MergedBits.grpID_18 -#define CAN2TXIDR1_ID CAN2TXIDR1_ID_15 - - -/*** CAN2TXIDR2 - MSCAN 2 Transmit Identifier Register 2; 0x000001F2 ***/ -typedef union { - byte Byte; - struct { - byte ID7 :1; /* Extended format identifier Bit 7 */ - byte ID8 :1; /* Extended format identifier Bit 8 */ - byte ID9 :1; /* Extended format identifier Bit 9 */ - byte ID10 :1; /* Extended format identifier Bit 10 */ - byte ID11 :1; /* Extended format identifier Bit 11 */ - byte ID12 :1; /* Extended format identifier Bit 12 */ - byte ID13 :1; /* Extended format identifier Bit 13 */ - byte ID14 :1; /* Extended format identifier Bit 14 */ - } Bits; - struct { - byte grpID_7 :8; - } MergedBits; -} CAN2TXIDR2STR; -extern volatile CAN2TXIDR2STR _CAN2TXIDR2 @(REG_BASE + 0x000001F2); -#define CAN2TXIDR2 _CAN2TXIDR2.Byte -#define CAN2TXIDR2_ID7 _CAN2TXIDR2.Bits.ID7 -#define CAN2TXIDR2_ID8 _CAN2TXIDR2.Bits.ID8 -#define CAN2TXIDR2_ID9 _CAN2TXIDR2.Bits.ID9 -#define CAN2TXIDR2_ID10 _CAN2TXIDR2.Bits.ID10 -#define CAN2TXIDR2_ID11 _CAN2TXIDR2.Bits.ID11 -#define CAN2TXIDR2_ID12 _CAN2TXIDR2.Bits.ID12 -#define CAN2TXIDR2_ID13 _CAN2TXIDR2.Bits.ID13 -#define CAN2TXIDR2_ID14 _CAN2TXIDR2.Bits.ID14 -#define CAN2TXIDR2_ID_7 _CAN2TXIDR2.MergedBits.grpID_7 -#define CAN2TXIDR2_ID CAN2TXIDR2_ID_7 - - -/*** CAN2TXIDR3 - MSCAN 2 Transmit Identifier Register 3; 0x000001F3 ***/ -typedef union { - byte Byte; - struct { - byte RTR :1; /* Remote Transmission Request */ - byte ID0 :1; /* Extended format identifier Bit 0 */ - byte ID1 :1; /* Extended format identifier Bit 1 */ - byte ID2 :1; /* Extended format identifier Bit 2 */ - byte ID3 :1; /* Extended format identifier Bit 3 */ - byte ID4 :1; /* Extended format identifier Bit 4 */ - byte ID5 :1; /* Extended format identifier Bit 5 */ - byte ID6 :1; /* Extended format identifier Bit 6 */ - } Bits; - struct { - byte :1; - byte grpID :7; - } MergedBits; -} CAN2TXIDR3STR; -extern volatile CAN2TXIDR3STR _CAN2TXIDR3 @(REG_BASE + 0x000001F3); -#define CAN2TXIDR3 _CAN2TXIDR3.Byte -#define CAN2TXIDR3_RTR _CAN2TXIDR3.Bits.RTR -#define CAN2TXIDR3_ID0 _CAN2TXIDR3.Bits.ID0 -#define CAN2TXIDR3_ID1 _CAN2TXIDR3.Bits.ID1 -#define CAN2TXIDR3_ID2 _CAN2TXIDR3.Bits.ID2 -#define CAN2TXIDR3_ID3 _CAN2TXIDR3.Bits.ID3 -#define CAN2TXIDR3_ID4 _CAN2TXIDR3.Bits.ID4 -#define CAN2TXIDR3_ID5 _CAN2TXIDR3.Bits.ID5 -#define CAN2TXIDR3_ID6 _CAN2TXIDR3.Bits.ID6 -#define CAN2TXIDR3_ID _CAN2TXIDR3.MergedBits.grpID - - -/*** CAN2TXDSR0 - MSCAN 2 Transmit Data Segment Register 0; 0x000001F4 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN2TXDSR0STR; -extern volatile CAN2TXDSR0STR _CAN2TXDSR0 @(REG_BASE + 0x000001F4); -#define CAN2TXDSR0 _CAN2TXDSR0.Byte -#define CAN2TXDSR0_DB0 _CAN2TXDSR0.Bits.DB0 -#define CAN2TXDSR0_DB1 _CAN2TXDSR0.Bits.DB1 -#define CAN2TXDSR0_DB2 _CAN2TXDSR0.Bits.DB2 -#define CAN2TXDSR0_DB3 _CAN2TXDSR0.Bits.DB3 -#define CAN2TXDSR0_DB4 _CAN2TXDSR0.Bits.DB4 -#define CAN2TXDSR0_DB5 _CAN2TXDSR0.Bits.DB5 -#define CAN2TXDSR0_DB6 _CAN2TXDSR0.Bits.DB6 -#define CAN2TXDSR0_DB7 _CAN2TXDSR0.Bits.DB7 -#define CAN2TXDSR0_DB _CAN2TXDSR0.MergedBits.grpDB - - -/*** CAN2TXDSR1 - MSCAN 2 Transmit Data Segment Register 1; 0x000001F5 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN2TXDSR1STR; -extern volatile CAN2TXDSR1STR _CAN2TXDSR1 @(REG_BASE + 0x000001F5); -#define CAN2TXDSR1 _CAN2TXDSR1.Byte -#define CAN2TXDSR1_DB0 _CAN2TXDSR1.Bits.DB0 -#define CAN2TXDSR1_DB1 _CAN2TXDSR1.Bits.DB1 -#define CAN2TXDSR1_DB2 _CAN2TXDSR1.Bits.DB2 -#define CAN2TXDSR1_DB3 _CAN2TXDSR1.Bits.DB3 -#define CAN2TXDSR1_DB4 _CAN2TXDSR1.Bits.DB4 -#define CAN2TXDSR1_DB5 _CAN2TXDSR1.Bits.DB5 -#define CAN2TXDSR1_DB6 _CAN2TXDSR1.Bits.DB6 -#define CAN2TXDSR1_DB7 _CAN2TXDSR1.Bits.DB7 -#define CAN2TXDSR1_DB _CAN2TXDSR1.MergedBits.grpDB - - -/*** CAN2TXDSR2 - MSCAN 2 Transmit Data Segment Register 2; 0x000001F6 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN2TXDSR2STR; -extern volatile CAN2TXDSR2STR _CAN2TXDSR2 @(REG_BASE + 0x000001F6); -#define CAN2TXDSR2 _CAN2TXDSR2.Byte -#define CAN2TXDSR2_DB0 _CAN2TXDSR2.Bits.DB0 -#define CAN2TXDSR2_DB1 _CAN2TXDSR2.Bits.DB1 -#define CAN2TXDSR2_DB2 _CAN2TXDSR2.Bits.DB2 -#define CAN2TXDSR2_DB3 _CAN2TXDSR2.Bits.DB3 -#define CAN2TXDSR2_DB4 _CAN2TXDSR2.Bits.DB4 -#define CAN2TXDSR2_DB5 _CAN2TXDSR2.Bits.DB5 -#define CAN2TXDSR2_DB6 _CAN2TXDSR2.Bits.DB6 -#define CAN2TXDSR2_DB7 _CAN2TXDSR2.Bits.DB7 -#define CAN2TXDSR2_DB _CAN2TXDSR2.MergedBits.grpDB - - -/*** CAN2TXDSR3 - MSCAN 2 Transmit Data Segment Register 3; 0x000001F7 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN2TXDSR3STR; -extern volatile CAN2TXDSR3STR _CAN2TXDSR3 @(REG_BASE + 0x000001F7); -#define CAN2TXDSR3 _CAN2TXDSR3.Byte -#define CAN2TXDSR3_DB0 _CAN2TXDSR3.Bits.DB0 -#define CAN2TXDSR3_DB1 _CAN2TXDSR3.Bits.DB1 -#define CAN2TXDSR3_DB2 _CAN2TXDSR3.Bits.DB2 -#define CAN2TXDSR3_DB3 _CAN2TXDSR3.Bits.DB3 -#define CAN2TXDSR3_DB4 _CAN2TXDSR3.Bits.DB4 -#define CAN2TXDSR3_DB5 _CAN2TXDSR3.Bits.DB5 -#define CAN2TXDSR3_DB6 _CAN2TXDSR3.Bits.DB6 -#define CAN2TXDSR3_DB7 _CAN2TXDSR3.Bits.DB7 -#define CAN2TXDSR3_DB _CAN2TXDSR3.MergedBits.grpDB - - -/*** CAN2TXDSR4 - MSCAN 2 Transmit Data Segment Register 4; 0x000001F8 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN2TXDSR4STR; -extern volatile CAN2TXDSR4STR _CAN2TXDSR4 @(REG_BASE + 0x000001F8); -#define CAN2TXDSR4 _CAN2TXDSR4.Byte -#define CAN2TXDSR4_DB0 _CAN2TXDSR4.Bits.DB0 -#define CAN2TXDSR4_DB1 _CAN2TXDSR4.Bits.DB1 -#define CAN2TXDSR4_DB2 _CAN2TXDSR4.Bits.DB2 -#define CAN2TXDSR4_DB3 _CAN2TXDSR4.Bits.DB3 -#define CAN2TXDSR4_DB4 _CAN2TXDSR4.Bits.DB4 -#define CAN2TXDSR4_DB5 _CAN2TXDSR4.Bits.DB5 -#define CAN2TXDSR4_DB6 _CAN2TXDSR4.Bits.DB6 -#define CAN2TXDSR4_DB7 _CAN2TXDSR4.Bits.DB7 -#define CAN2TXDSR4_DB _CAN2TXDSR4.MergedBits.grpDB - - -/*** CAN2TXDSR5 - MSCAN 2 Transmit Data Segment Register 5; 0x000001F9 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN2TXDSR5STR; -extern volatile CAN2TXDSR5STR _CAN2TXDSR5 @(REG_BASE + 0x000001F9); -#define CAN2TXDSR5 _CAN2TXDSR5.Byte -#define CAN2TXDSR5_DB0 _CAN2TXDSR5.Bits.DB0 -#define CAN2TXDSR5_DB1 _CAN2TXDSR5.Bits.DB1 -#define CAN2TXDSR5_DB2 _CAN2TXDSR5.Bits.DB2 -#define CAN2TXDSR5_DB3 _CAN2TXDSR5.Bits.DB3 -#define CAN2TXDSR5_DB4 _CAN2TXDSR5.Bits.DB4 -#define CAN2TXDSR5_DB5 _CAN2TXDSR5.Bits.DB5 -#define CAN2TXDSR5_DB6 _CAN2TXDSR5.Bits.DB6 -#define CAN2TXDSR5_DB7 _CAN2TXDSR5.Bits.DB7 -#define CAN2TXDSR5_DB _CAN2TXDSR5.MergedBits.grpDB - - -/*** CAN2TXDSR6 - MSCAN 2 Transmit Data Segment Register 6; 0x000001FA ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN2TXDSR6STR; -extern volatile CAN2TXDSR6STR _CAN2TXDSR6 @(REG_BASE + 0x000001FA); -#define CAN2TXDSR6 _CAN2TXDSR6.Byte -#define CAN2TXDSR6_DB0 _CAN2TXDSR6.Bits.DB0 -#define CAN2TXDSR6_DB1 _CAN2TXDSR6.Bits.DB1 -#define CAN2TXDSR6_DB2 _CAN2TXDSR6.Bits.DB2 -#define CAN2TXDSR6_DB3 _CAN2TXDSR6.Bits.DB3 -#define CAN2TXDSR6_DB4 _CAN2TXDSR6.Bits.DB4 -#define CAN2TXDSR6_DB5 _CAN2TXDSR6.Bits.DB5 -#define CAN2TXDSR6_DB6 _CAN2TXDSR6.Bits.DB6 -#define CAN2TXDSR6_DB7 _CAN2TXDSR6.Bits.DB7 -#define CAN2TXDSR6_DB _CAN2TXDSR6.MergedBits.grpDB - - -/*** CAN2TXDSR7 - MSCAN 2 Transmit Data Segment Register 7; 0x000001FB ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN2TXDSR7STR; -extern volatile CAN2TXDSR7STR _CAN2TXDSR7 @(REG_BASE + 0x000001FB); -#define CAN2TXDSR7 _CAN2TXDSR7.Byte -#define CAN2TXDSR7_DB0 _CAN2TXDSR7.Bits.DB0 -#define CAN2TXDSR7_DB1 _CAN2TXDSR7.Bits.DB1 -#define CAN2TXDSR7_DB2 _CAN2TXDSR7.Bits.DB2 -#define CAN2TXDSR7_DB3 _CAN2TXDSR7.Bits.DB3 -#define CAN2TXDSR7_DB4 _CAN2TXDSR7.Bits.DB4 -#define CAN2TXDSR7_DB5 _CAN2TXDSR7.Bits.DB5 -#define CAN2TXDSR7_DB6 _CAN2TXDSR7.Bits.DB6 -#define CAN2TXDSR7_DB7 _CAN2TXDSR7.Bits.DB7 -#define CAN2TXDSR7_DB _CAN2TXDSR7.MergedBits.grpDB - - -/*** CAN2TXDLR - MSCAN 2 Transmit Data Length Register; 0x000001FC ***/ -typedef union { - byte Byte; - struct { - byte DLC0 :1; /* Data Length Code Bit 0 */ - byte DLC1 :1; /* Data Length Code Bit 1 */ - byte DLC2 :1; /* Data Length Code Bit 2 */ - byte DLC3 :1; /* Data Length Code Bit 3 */ - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpDLC :4; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} CAN2TXDLRSTR; -extern volatile CAN2TXDLRSTR _CAN2TXDLR @(REG_BASE + 0x000001FC); -#define CAN2TXDLR _CAN2TXDLR.Byte -#define CAN2TXDLR_DLC0 _CAN2TXDLR.Bits.DLC0 -#define CAN2TXDLR_DLC1 _CAN2TXDLR.Bits.DLC1 -#define CAN2TXDLR_DLC2 _CAN2TXDLR.Bits.DLC2 -#define CAN2TXDLR_DLC3 _CAN2TXDLR.Bits.DLC3 -#define CAN2TXDLR_DLC _CAN2TXDLR.MergedBits.grpDLC - - -/*** CAN2TXTBPR - MSCAN 2 Transmit Buffer Priority; 0x000001FF ***/ -typedef union { - byte Byte; - struct { - byte PRIO0 :1; /* Transmit Buffer Priority Bit 0 */ - byte PRIO1 :1; /* Transmit Buffer Priority Bit 1 */ - byte PRIO2 :1; /* Transmit Buffer Priority Bit 2 */ - byte PRIO3 :1; /* Transmit Buffer Priority Bit 3 */ - byte PRIO4 :1; /* Transmit Buffer Priority Bit 4 */ - byte PRIO5 :1; /* Transmit Buffer Priority Bit 5 */ - byte PRIO6 :1; /* Transmit Buffer Priority Bit 6 */ - byte PRIO7 :1; /* Transmit Buffer Priority Bit 7 */ - } Bits; - struct { - byte grpPRIO :8; - } MergedBits; -} CAN2TXTBPRSTR; -extern volatile CAN2TXTBPRSTR _CAN2TXTBPR @(REG_BASE + 0x000001FF); -#define CAN2TXTBPR _CAN2TXTBPR.Byte -#define CAN2TXTBPR_PRIO0 _CAN2TXTBPR.Bits.PRIO0 -#define CAN2TXTBPR_PRIO1 _CAN2TXTBPR.Bits.PRIO1 -#define CAN2TXTBPR_PRIO2 _CAN2TXTBPR.Bits.PRIO2 -#define CAN2TXTBPR_PRIO3 _CAN2TXTBPR.Bits.PRIO3 -#define CAN2TXTBPR_PRIO4 _CAN2TXTBPR.Bits.PRIO4 -#define CAN2TXTBPR_PRIO5 _CAN2TXTBPR.Bits.PRIO5 -#define CAN2TXTBPR_PRIO6 _CAN2TXTBPR.Bits.PRIO6 -#define CAN2TXTBPR_PRIO7 _CAN2TXTBPR.Bits.PRIO7 -#define CAN2TXTBPR_PRIO _CAN2TXTBPR.MergedBits.grpPRIO - - -/*** CAN3CTL0 - MSCAN 3 Control 0 Register; 0x00000200 ***/ -typedef union { - byte Byte; - struct { - byte INITRQ :1; /* Initialization Mode Request */ - byte SLPRQ :1; /* Sleep Mode Request */ - byte WUPE :1; /* Wake-Up Enable */ - byte TIME :1; /* Timer Enable */ - byte SYNCH :1; /* Synchronized Status */ - byte CSWAI :1; /* CAN Stops in Wait Mode */ - byte RXACT :1; /* Receiver Active Status */ - byte RXFRM :1; /* Received Frame Flag */ - } Bits; -} CAN3CTL0STR; -extern volatile CAN3CTL0STR _CAN3CTL0 @(REG_BASE + 0x00000200); -#define CAN3CTL0 _CAN3CTL0.Byte -#define CAN3CTL0_INITRQ _CAN3CTL0.Bits.INITRQ -#define CAN3CTL0_SLPRQ _CAN3CTL0.Bits.SLPRQ -#define CAN3CTL0_WUPE _CAN3CTL0.Bits.WUPE -#define CAN3CTL0_TIME _CAN3CTL0.Bits.TIME -#define CAN3CTL0_SYNCH _CAN3CTL0.Bits.SYNCH -#define CAN3CTL0_CSWAI _CAN3CTL0.Bits.CSWAI -#define CAN3CTL0_RXACT _CAN3CTL0.Bits.RXACT -#define CAN3CTL0_RXFRM _CAN3CTL0.Bits.RXFRM - - -/*** CAN3CTL1 - MSCAN 3 Control 1 Register; 0x00000201 ***/ -typedef union { - byte Byte; - struct { - byte INITAK :1; /* Initialization Mode Acknowledge */ - byte SLPAK :1; /* Sleep Mode Acknowledge */ - byte WUPM :1; /* Wake-Up Mode */ - byte :1; - byte LISTEN :1; /* Listen Only Mode */ - byte LOOPB :1; /* Loop Back Self Test Mode */ - byte CLKSRC :1; /* MSCAN 3 Clock Source */ - byte CANE :1; /* MSCAN 3 Enable */ - } Bits; -} CAN3CTL1STR; -extern volatile CAN3CTL1STR _CAN3CTL1 @(REG_BASE + 0x00000201); -#define CAN3CTL1 _CAN3CTL1.Byte -#define CAN3CTL1_INITAK _CAN3CTL1.Bits.INITAK -#define CAN3CTL1_SLPAK _CAN3CTL1.Bits.SLPAK -#define CAN3CTL1_WUPM _CAN3CTL1.Bits.WUPM -#define CAN3CTL1_LISTEN _CAN3CTL1.Bits.LISTEN -#define CAN3CTL1_LOOPB _CAN3CTL1.Bits.LOOPB -#define CAN3CTL1_CLKSRC _CAN3CTL1.Bits.CLKSRC -#define CAN3CTL1_CANE _CAN3CTL1.Bits.CANE - - -/*** CAN3BTR0 - MSCAN 3 Bus Timing Register 0; 0x00000202 ***/ -typedef union { - byte Byte; - struct { - byte BRP0 :1; /* Baud Rate Prescaler 0 */ - byte BRP1 :1; /* Baud Rate Prescaler 1 */ - byte BRP2 :1; /* Baud Rate Prescaler 2 */ - byte BRP3 :1; /* Baud Rate Prescaler 3 */ - byte BRP4 :1; /* Baud Rate Prescaler 4 */ - byte BRP5 :1; /* Baud Rate Prescaler 5 */ - byte SJW0 :1; /* Synchronization Jump Width 0 */ - byte SJW1 :1; /* Synchronization Jump Width 1 */ - } Bits; - struct { - byte grpBRP :6; - byte grpSJW :2; - } MergedBits; -} CAN3BTR0STR; -extern volatile CAN3BTR0STR _CAN3BTR0 @(REG_BASE + 0x00000202); -#define CAN3BTR0 _CAN3BTR0.Byte -#define CAN3BTR0_BRP0 _CAN3BTR0.Bits.BRP0 -#define CAN3BTR0_BRP1 _CAN3BTR0.Bits.BRP1 -#define CAN3BTR0_BRP2 _CAN3BTR0.Bits.BRP2 -#define CAN3BTR0_BRP3 _CAN3BTR0.Bits.BRP3 -#define CAN3BTR0_BRP4 _CAN3BTR0.Bits.BRP4 -#define CAN3BTR0_BRP5 _CAN3BTR0.Bits.BRP5 -#define CAN3BTR0_SJW0 _CAN3BTR0.Bits.SJW0 -#define CAN3BTR0_SJW1 _CAN3BTR0.Bits.SJW1 -#define CAN3BTR0_BRP _CAN3BTR0.MergedBits.grpBRP -#define CAN3BTR0_SJW _CAN3BTR0.MergedBits.grpSJW - - -/*** CAN3BTR1 - MSCAN 3 Bus Timing Register 1; 0x00000203 ***/ -typedef union { - byte Byte; - struct { - byte TSEG10 :1; /* Time Segment 1 */ - byte TSEG11 :1; /* Time Segment 1 */ - byte TSEG12 :1; /* Time Segment 1 */ - byte TSEG13 :1; /* Time Segment 1 */ - byte TSEG20 :1; /* Time Segment 2 */ - byte TSEG21 :1; /* Time Segment 2 */ - byte TSEG22 :1; /* Time Segment 2 */ - byte SAMP :1; /* Sampling */ - } Bits; - struct { - byte grpTSEG_10 :4; - byte grpTSEG_20 :3; - byte :1; - } MergedBits; -} CAN3BTR1STR; -extern volatile CAN3BTR1STR _CAN3BTR1 @(REG_BASE + 0x00000203); -#define CAN3BTR1 _CAN3BTR1.Byte -#define CAN3BTR1_TSEG10 _CAN3BTR1.Bits.TSEG10 -#define CAN3BTR1_TSEG11 _CAN3BTR1.Bits.TSEG11 -#define CAN3BTR1_TSEG12 _CAN3BTR1.Bits.TSEG12 -#define CAN3BTR1_TSEG13 _CAN3BTR1.Bits.TSEG13 -#define CAN3BTR1_TSEG20 _CAN3BTR1.Bits.TSEG20 -#define CAN3BTR1_TSEG21 _CAN3BTR1.Bits.TSEG21 -#define CAN3BTR1_TSEG22 _CAN3BTR1.Bits.TSEG22 -#define CAN3BTR1_SAMP _CAN3BTR1.Bits.SAMP -#define CAN3BTR1_TSEG_10 _CAN3BTR1.MergedBits.grpTSEG_10 -#define CAN3BTR1_TSEG_20 _CAN3BTR1.MergedBits.grpTSEG_20 -#define CAN3BTR1_TSEG CAN3BTR1_TSEG_10 - - -/*** CAN3RFLG - MSCAN 3 Receiver Flag Register; 0x00000204 ***/ -typedef union { - byte Byte; - struct { - byte RXF :1; /* Receive Buffer Full */ - byte OVRIF :1; /* Overrun Interrupt Flag */ - byte TSTAT0 :1; /* Transmitter Status Bit 0 */ - byte TSTAT1 :1; /* Transmitter Status Bit 1 */ - byte RSTAT0 :1; /* Receiver Status Bit 0 */ - byte RSTAT1 :1; /* Receiver Status Bit 1 */ - byte CSCIF :1; /* CAN Status Change Interrupt Flag */ - byte WUPIF :1; /* Wake-up Interrupt Flag */ - } Bits; - struct { - byte :1; - byte :1; - byte grpTSTAT :2; - byte grpRSTAT :2; - byte :1; - byte :1; - } MergedBits; -} CAN3RFLGSTR; -extern volatile CAN3RFLGSTR _CAN3RFLG @(REG_BASE + 0x00000204); -#define CAN3RFLG _CAN3RFLG.Byte -#define CAN3RFLG_RXF _CAN3RFLG.Bits.RXF -#define CAN3RFLG_OVRIF _CAN3RFLG.Bits.OVRIF -#define CAN3RFLG_TSTAT0 _CAN3RFLG.Bits.TSTAT0 -#define CAN3RFLG_TSTAT1 _CAN3RFLG.Bits.TSTAT1 -#define CAN3RFLG_RSTAT0 _CAN3RFLG.Bits.RSTAT0 -#define CAN3RFLG_RSTAT1 _CAN3RFLG.Bits.RSTAT1 -#define CAN3RFLG_CSCIF _CAN3RFLG.Bits.CSCIF -#define CAN3RFLG_WUPIF _CAN3RFLG.Bits.WUPIF -#define CAN3RFLG_TSTAT _CAN3RFLG.MergedBits.grpTSTAT -#define CAN3RFLG_RSTAT _CAN3RFLG.MergedBits.grpRSTAT - - -/*** CAN3RIER - MSCAN 3 Receiver Interrupt Enable Register; 0x00000205 ***/ -typedef union { - byte Byte; - struct { - byte RXFIE :1; /* Receiver Full Interrupt Enable */ - byte OVRIE :1; /* Overrun Interrupt Enable */ - byte TSTATE0 :1; /* Transmitter Status Change Enable 0 */ - byte TSTATE1 :1; /* Transmitter Status Change Enable 1 */ - byte RSTATE0 :1; /* Receiver Status Change Enable 0 */ - byte RSTATE1 :1; /* Receiver Status Change Enable 1 */ - byte CSCIE :1; /* CAN Status Change Interrupt Enable */ - byte WUPIE :1; /* Wake-up Interrupt Enable */ - } Bits; - struct { - byte :1; - byte :1; - byte grpTSTATE :2; - byte grpRSTATE :2; - byte :1; - byte :1; - } MergedBits; -} CAN3RIERSTR; -extern volatile CAN3RIERSTR _CAN3RIER @(REG_BASE + 0x00000205); -#define CAN3RIER _CAN3RIER.Byte -#define CAN3RIER_RXFIE _CAN3RIER.Bits.RXFIE -#define CAN3RIER_OVRIE _CAN3RIER.Bits.OVRIE -#define CAN3RIER_TSTATE0 _CAN3RIER.Bits.TSTATE0 -#define CAN3RIER_TSTATE1 _CAN3RIER.Bits.TSTATE1 -#define CAN3RIER_RSTATE0 _CAN3RIER.Bits.RSTATE0 -#define CAN3RIER_RSTATE1 _CAN3RIER.Bits.RSTATE1 -#define CAN3RIER_CSCIE _CAN3RIER.Bits.CSCIE -#define CAN3RIER_WUPIE _CAN3RIER.Bits.WUPIE -#define CAN3RIER_TSTATE _CAN3RIER.MergedBits.grpTSTATE -#define CAN3RIER_RSTATE _CAN3RIER.MergedBits.grpRSTATE - - -/*** CAN3TFLG - MSCAN 3 Transmitter Flag Register; 0x00000206 ***/ -typedef union { - byte Byte; - struct { - byte TXE0 :1; /* Transmitter Buffer Empty 0 */ - byte TXE1 :1; /* Transmitter Buffer Empty 1 */ - byte TXE2 :1; /* Transmitter Buffer Empty 2 */ - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpTXE :3; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} CAN3TFLGSTR; -extern volatile CAN3TFLGSTR _CAN3TFLG @(REG_BASE + 0x00000206); -#define CAN3TFLG _CAN3TFLG.Byte -#define CAN3TFLG_TXE0 _CAN3TFLG.Bits.TXE0 -#define CAN3TFLG_TXE1 _CAN3TFLG.Bits.TXE1 -#define CAN3TFLG_TXE2 _CAN3TFLG.Bits.TXE2 -#define CAN3TFLG_TXE _CAN3TFLG.MergedBits.grpTXE - - -/*** CAN3TIER - MSCAN 3 Transmitter Interrupt Enable Register; 0x00000207 ***/ -typedef union { - byte Byte; - struct { - byte TXEIE0 :1; /* Transmitter Empty Interrupt Enable 0 */ - byte TXEIE1 :1; /* Transmitter Empty Interrupt Enable 1 */ - byte TXEIE2 :1; /* Transmitter Empty Interrupt Enable 2 */ - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpTXEIE :3; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} CAN3TIERSTR; -extern volatile CAN3TIERSTR _CAN3TIER @(REG_BASE + 0x00000207); -#define CAN3TIER _CAN3TIER.Byte -#define CAN3TIER_TXEIE0 _CAN3TIER.Bits.TXEIE0 -#define CAN3TIER_TXEIE1 _CAN3TIER.Bits.TXEIE1 -#define CAN3TIER_TXEIE2 _CAN3TIER.Bits.TXEIE2 -#define CAN3TIER_TXEIE _CAN3TIER.MergedBits.grpTXEIE - - -/*** CAN3TARQ - MSCAN 3 Transmitter Message Abort Request; 0x00000208 ***/ -typedef union { - byte Byte; - struct { - byte ABTRQ0 :1; /* Abort Request 0 */ - byte ABTRQ1 :1; /* Abort Request 1 */ - byte ABTRQ2 :1; /* Abort Request 2 */ - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpABTRQ :3; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} CAN3TARQSTR; -extern volatile CAN3TARQSTR _CAN3TARQ @(REG_BASE + 0x00000208); -#define CAN3TARQ _CAN3TARQ.Byte -#define CAN3TARQ_ABTRQ0 _CAN3TARQ.Bits.ABTRQ0 -#define CAN3TARQ_ABTRQ1 _CAN3TARQ.Bits.ABTRQ1 -#define CAN3TARQ_ABTRQ2 _CAN3TARQ.Bits.ABTRQ2 -#define CAN3TARQ_ABTRQ _CAN3TARQ.MergedBits.grpABTRQ - - -/*** CAN3TAAK - MSCAN 3 Transmitter Message Abort Control; 0x00000209 ***/ -typedef union { - byte Byte; - struct { - byte ABTAK0 :1; /* Abort Acknowledge 0 */ - byte ABTAK1 :1; /* Abort Acknowledge 1 */ - byte ABTAK2 :1; /* Abort Acknowledge 2 */ - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpABTAK :3; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} CAN3TAAKSTR; -extern volatile CAN3TAAKSTR _CAN3TAAK @(REG_BASE + 0x00000209); -#define CAN3TAAK _CAN3TAAK.Byte -#define CAN3TAAK_ABTAK0 _CAN3TAAK.Bits.ABTAK0 -#define CAN3TAAK_ABTAK1 _CAN3TAAK.Bits.ABTAK1 -#define CAN3TAAK_ABTAK2 _CAN3TAAK.Bits.ABTAK2 -#define CAN3TAAK_ABTAK _CAN3TAAK.MergedBits.grpABTAK - - -/*** CAN3TBSEL - MSCAN 3 Transmit Buffer Selection; 0x0000020A ***/ -typedef union { - byte Byte; - struct { - byte TX0 :1; /* Transmit Buffer Select 0 */ - byte TX1 :1; /* Transmit Buffer Select 1 */ - byte TX2 :1; /* Transmit Buffer Select 2 */ - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpTX :3; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} CAN3TBSELSTR; -extern volatile CAN3TBSELSTR _CAN3TBSEL @(REG_BASE + 0x0000020A); -#define CAN3TBSEL _CAN3TBSEL.Byte -#define CAN3TBSEL_TX0 _CAN3TBSEL.Bits.TX0 -#define CAN3TBSEL_TX1 _CAN3TBSEL.Bits.TX1 -#define CAN3TBSEL_TX2 _CAN3TBSEL.Bits.TX2 -#define CAN3TBSEL_TX _CAN3TBSEL.MergedBits.grpTX - - -/*** CAN3IDAC - MSCAN 3 Identifier Acceptance Control Register; 0x0000020B ***/ -typedef union { - byte Byte; - struct { - byte IDHIT0 :1; /* Identifier Acceptance Hit Indicator 0 */ - byte IDHIT1 :1; /* Identifier Acceptance Hit Indicator 1 */ - byte IDHIT2 :1; /* Identifier Acceptance Hit Indicator 2 */ - byte :1; - byte IDAM0 :1; /* Identifier Acceptance Mode 0 */ - byte IDAM1 :1; /* Identifier Acceptance Mode 1 */ - byte :1; - byte :1; - } Bits; - struct { - byte grpIDHIT :3; - byte :1; - byte grpIDAM :2; - byte :1; - byte :1; - } MergedBits; -} CAN3IDACSTR; -extern volatile CAN3IDACSTR _CAN3IDAC @(REG_BASE + 0x0000020B); -#define CAN3IDAC _CAN3IDAC.Byte -#define CAN3IDAC_IDHIT0 _CAN3IDAC.Bits.IDHIT0 -#define CAN3IDAC_IDHIT1 _CAN3IDAC.Bits.IDHIT1 -#define CAN3IDAC_IDHIT2 _CAN3IDAC.Bits.IDHIT2 -#define CAN3IDAC_IDAM0 _CAN3IDAC.Bits.IDAM0 -#define CAN3IDAC_IDAM1 _CAN3IDAC.Bits.IDAM1 -#define CAN3IDAC_IDHIT _CAN3IDAC.MergedBits.grpIDHIT -#define CAN3IDAC_IDAM _CAN3IDAC.MergedBits.grpIDAM - - -/*** CAN3RXERR - MSCAN 3 Receive Error Counter Register; 0x0000020E ***/ -typedef union { - byte Byte; - struct { - byte RXERR0 :1; /* Bit 0 */ - byte RXERR1 :1; /* Bit 1 */ - byte RXERR2 :1; /* Bit 2 */ - byte RXERR3 :1; /* Bit 3 */ - byte RXERR4 :1; /* Bit 4 */ - byte RXERR5 :1; /* Bit 5 */ - byte RXERR6 :1; /* Bit 6 */ - byte RXERR7 :1; /* Bit 7 */ - } Bits; - struct { - byte grpRXERR :8; - } MergedBits; -} CAN3RXERRSTR; -extern volatile CAN3RXERRSTR _CAN3RXERR @(REG_BASE + 0x0000020E); -#define CAN3RXERR _CAN3RXERR.Byte -#define CAN3RXERR_RXERR0 _CAN3RXERR.Bits.RXERR0 -#define CAN3RXERR_RXERR1 _CAN3RXERR.Bits.RXERR1 -#define CAN3RXERR_RXERR2 _CAN3RXERR.Bits.RXERR2 -#define CAN3RXERR_RXERR3 _CAN3RXERR.Bits.RXERR3 -#define CAN3RXERR_RXERR4 _CAN3RXERR.Bits.RXERR4 -#define CAN3RXERR_RXERR5 _CAN3RXERR.Bits.RXERR5 -#define CAN3RXERR_RXERR6 _CAN3RXERR.Bits.RXERR6 -#define CAN3RXERR_RXERR7 _CAN3RXERR.Bits.RXERR7 -#define CAN3RXERR_RXERR _CAN3RXERR.MergedBits.grpRXERR - - -/*** CAN3TXERR - MSCAN 3 Transmit Error Counter Register; 0x0000020F ***/ -typedef union { - byte Byte; - struct { - byte TXERR0 :1; /* Bit 0 */ - byte TXERR1 :1; /* Bit 1 */ - byte TXERR2 :1; /* Bit 2 */ - byte TXERR3 :1; /* Bit 3 */ - byte TXERR4 :1; /* Bit 4 */ - byte TXERR5 :1; /* Bit 5 */ - byte TXERR6 :1; /* Bit 6 */ - byte TXERR7 :1; /* Bit 7 */ - } Bits; - struct { - byte grpTXERR :8; - } MergedBits; -} CAN3TXERRSTR; -extern volatile CAN3TXERRSTR _CAN3TXERR @(REG_BASE + 0x0000020F); -#define CAN3TXERR _CAN3TXERR.Byte -#define CAN3TXERR_TXERR0 _CAN3TXERR.Bits.TXERR0 -#define CAN3TXERR_TXERR1 _CAN3TXERR.Bits.TXERR1 -#define CAN3TXERR_TXERR2 _CAN3TXERR.Bits.TXERR2 -#define CAN3TXERR_TXERR3 _CAN3TXERR.Bits.TXERR3 -#define CAN3TXERR_TXERR4 _CAN3TXERR.Bits.TXERR4 -#define CAN3TXERR_TXERR5 _CAN3TXERR.Bits.TXERR5 -#define CAN3TXERR_TXERR6 _CAN3TXERR.Bits.TXERR6 -#define CAN3TXERR_TXERR7 _CAN3TXERR.Bits.TXERR7 -#define CAN3TXERR_TXERR _CAN3TXERR.MergedBits.grpTXERR - - -/*** CAN3IDAR0 - MSCAN 3 Identifier Acceptance Register 0; 0x00000210 ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CAN3IDAR0STR; -extern volatile CAN3IDAR0STR _CAN3IDAR0 @(REG_BASE + 0x00000210); -#define CAN3IDAR0 _CAN3IDAR0.Byte -#define CAN3IDAR0_AC0 _CAN3IDAR0.Bits.AC0 -#define CAN3IDAR0_AC1 _CAN3IDAR0.Bits.AC1 -#define CAN3IDAR0_AC2 _CAN3IDAR0.Bits.AC2 -#define CAN3IDAR0_AC3 _CAN3IDAR0.Bits.AC3 -#define CAN3IDAR0_AC4 _CAN3IDAR0.Bits.AC4 -#define CAN3IDAR0_AC5 _CAN3IDAR0.Bits.AC5 -#define CAN3IDAR0_AC6 _CAN3IDAR0.Bits.AC6 -#define CAN3IDAR0_AC7 _CAN3IDAR0.Bits.AC7 -#define CAN3IDAR0_AC _CAN3IDAR0.MergedBits.grpAC - - -/*** CAN3IDAR1 - MSCAN 3 Identifier Acceptance Register 1; 0x00000211 ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CAN3IDAR1STR; -extern volatile CAN3IDAR1STR _CAN3IDAR1 @(REG_BASE + 0x00000211); -#define CAN3IDAR1 _CAN3IDAR1.Byte -#define CAN3IDAR1_AC0 _CAN3IDAR1.Bits.AC0 -#define CAN3IDAR1_AC1 _CAN3IDAR1.Bits.AC1 -#define CAN3IDAR1_AC2 _CAN3IDAR1.Bits.AC2 -#define CAN3IDAR1_AC3 _CAN3IDAR1.Bits.AC3 -#define CAN3IDAR1_AC4 _CAN3IDAR1.Bits.AC4 -#define CAN3IDAR1_AC5 _CAN3IDAR1.Bits.AC5 -#define CAN3IDAR1_AC6 _CAN3IDAR1.Bits.AC6 -#define CAN3IDAR1_AC7 _CAN3IDAR1.Bits.AC7 -#define CAN3IDAR1_AC _CAN3IDAR1.MergedBits.grpAC - - -/*** CAN3IDAR2 - MSCAN 3 Identifier Acceptance Register 2; 0x00000212 ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CAN3IDAR2STR; -extern volatile CAN3IDAR2STR _CAN3IDAR2 @(REG_BASE + 0x00000212); -#define CAN3IDAR2 _CAN3IDAR2.Byte -#define CAN3IDAR2_AC0 _CAN3IDAR2.Bits.AC0 -#define CAN3IDAR2_AC1 _CAN3IDAR2.Bits.AC1 -#define CAN3IDAR2_AC2 _CAN3IDAR2.Bits.AC2 -#define CAN3IDAR2_AC3 _CAN3IDAR2.Bits.AC3 -#define CAN3IDAR2_AC4 _CAN3IDAR2.Bits.AC4 -#define CAN3IDAR2_AC5 _CAN3IDAR2.Bits.AC5 -#define CAN3IDAR2_AC6 _CAN3IDAR2.Bits.AC6 -#define CAN3IDAR2_AC7 _CAN3IDAR2.Bits.AC7 -#define CAN3IDAR2_AC _CAN3IDAR2.MergedBits.grpAC - - -/*** CAN3IDAR3 - MSCAN 3 Identifier Acceptance Register 3; 0x00000213 ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CAN3IDAR3STR; -extern volatile CAN3IDAR3STR _CAN3IDAR3 @(REG_BASE + 0x00000213); -#define CAN3IDAR3 _CAN3IDAR3.Byte -#define CAN3IDAR3_AC0 _CAN3IDAR3.Bits.AC0 -#define CAN3IDAR3_AC1 _CAN3IDAR3.Bits.AC1 -#define CAN3IDAR3_AC2 _CAN3IDAR3.Bits.AC2 -#define CAN3IDAR3_AC3 _CAN3IDAR3.Bits.AC3 -#define CAN3IDAR3_AC4 _CAN3IDAR3.Bits.AC4 -#define CAN3IDAR3_AC5 _CAN3IDAR3.Bits.AC5 -#define CAN3IDAR3_AC6 _CAN3IDAR3.Bits.AC6 -#define CAN3IDAR3_AC7 _CAN3IDAR3.Bits.AC7 -#define CAN3IDAR3_AC _CAN3IDAR3.MergedBits.grpAC - - -/*** CAN3IDMR0 - MSCAN 3 Identifier Mask Register 0; 0x00000214 ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CAN3IDMR0STR; -extern volatile CAN3IDMR0STR _CAN3IDMR0 @(REG_BASE + 0x00000214); -#define CAN3IDMR0 _CAN3IDMR0.Byte -#define CAN3IDMR0_AM0 _CAN3IDMR0.Bits.AM0 -#define CAN3IDMR0_AM1 _CAN3IDMR0.Bits.AM1 -#define CAN3IDMR0_AM2 _CAN3IDMR0.Bits.AM2 -#define CAN3IDMR0_AM3 _CAN3IDMR0.Bits.AM3 -#define CAN3IDMR0_AM4 _CAN3IDMR0.Bits.AM4 -#define CAN3IDMR0_AM5 _CAN3IDMR0.Bits.AM5 -#define CAN3IDMR0_AM6 _CAN3IDMR0.Bits.AM6 -#define CAN3IDMR0_AM7 _CAN3IDMR0.Bits.AM7 -#define CAN3IDMR0_AM _CAN3IDMR0.MergedBits.grpAM - - -/*** CAN3IDMR1 - MSCAN 3 Identifier Mask Register 1; 0x00000215 ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CAN3IDMR1STR; -extern volatile CAN3IDMR1STR _CAN3IDMR1 @(REG_BASE + 0x00000215); -#define CAN3IDMR1 _CAN3IDMR1.Byte -#define CAN3IDMR1_AM0 _CAN3IDMR1.Bits.AM0 -#define CAN3IDMR1_AM1 _CAN3IDMR1.Bits.AM1 -#define CAN3IDMR1_AM2 _CAN3IDMR1.Bits.AM2 -#define CAN3IDMR1_AM3 _CAN3IDMR1.Bits.AM3 -#define CAN3IDMR1_AM4 _CAN3IDMR1.Bits.AM4 -#define CAN3IDMR1_AM5 _CAN3IDMR1.Bits.AM5 -#define CAN3IDMR1_AM6 _CAN3IDMR1.Bits.AM6 -#define CAN3IDMR1_AM7 _CAN3IDMR1.Bits.AM7 -#define CAN3IDMR1_AM _CAN3IDMR1.MergedBits.grpAM - - -/*** CAN3IDMR2 - MSCAN 3 Identifier Mask Register 2; 0x00000216 ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CAN3IDMR2STR; -extern volatile CAN3IDMR2STR _CAN3IDMR2 @(REG_BASE + 0x00000216); -#define CAN3IDMR2 _CAN3IDMR2.Byte -#define CAN3IDMR2_AM0 _CAN3IDMR2.Bits.AM0 -#define CAN3IDMR2_AM1 _CAN3IDMR2.Bits.AM1 -#define CAN3IDMR2_AM2 _CAN3IDMR2.Bits.AM2 -#define CAN3IDMR2_AM3 _CAN3IDMR2.Bits.AM3 -#define CAN3IDMR2_AM4 _CAN3IDMR2.Bits.AM4 -#define CAN3IDMR2_AM5 _CAN3IDMR2.Bits.AM5 -#define CAN3IDMR2_AM6 _CAN3IDMR2.Bits.AM6 -#define CAN3IDMR2_AM7 _CAN3IDMR2.Bits.AM7 -#define CAN3IDMR2_AM _CAN3IDMR2.MergedBits.grpAM - - -/*** CAN3IDMR3 - MSCAN 3 Identifier Mask Register 3; 0x00000217 ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CAN3IDMR3STR; -extern volatile CAN3IDMR3STR _CAN3IDMR3 @(REG_BASE + 0x00000217); -#define CAN3IDMR3 _CAN3IDMR3.Byte -#define CAN3IDMR3_AM0 _CAN3IDMR3.Bits.AM0 -#define CAN3IDMR3_AM1 _CAN3IDMR3.Bits.AM1 -#define CAN3IDMR3_AM2 _CAN3IDMR3.Bits.AM2 -#define CAN3IDMR3_AM3 _CAN3IDMR3.Bits.AM3 -#define CAN3IDMR3_AM4 _CAN3IDMR3.Bits.AM4 -#define CAN3IDMR3_AM5 _CAN3IDMR3.Bits.AM5 -#define CAN3IDMR3_AM6 _CAN3IDMR3.Bits.AM6 -#define CAN3IDMR3_AM7 _CAN3IDMR3.Bits.AM7 -#define CAN3IDMR3_AM _CAN3IDMR3.MergedBits.grpAM - - -/*** CAN3IDAR4 - MSCAN 3 Identifier Acceptance Register 4; 0x00000218 ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CAN3IDAR4STR; -extern volatile CAN3IDAR4STR _CAN3IDAR4 @(REG_BASE + 0x00000218); -#define CAN3IDAR4 _CAN3IDAR4.Byte -#define CAN3IDAR4_AC0 _CAN3IDAR4.Bits.AC0 -#define CAN3IDAR4_AC1 _CAN3IDAR4.Bits.AC1 -#define CAN3IDAR4_AC2 _CAN3IDAR4.Bits.AC2 -#define CAN3IDAR4_AC3 _CAN3IDAR4.Bits.AC3 -#define CAN3IDAR4_AC4 _CAN3IDAR4.Bits.AC4 -#define CAN3IDAR4_AC5 _CAN3IDAR4.Bits.AC5 -#define CAN3IDAR4_AC6 _CAN3IDAR4.Bits.AC6 -#define CAN3IDAR4_AC7 _CAN3IDAR4.Bits.AC7 -#define CAN3IDAR4_AC _CAN3IDAR4.MergedBits.grpAC - - -/*** CAN3IDAR5 - MSCAN 3 Identifier Acceptance Register 5; 0x00000219 ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CAN3IDAR5STR; -extern volatile CAN3IDAR5STR _CAN3IDAR5 @(REG_BASE + 0x00000219); -#define CAN3IDAR5 _CAN3IDAR5.Byte -#define CAN3IDAR5_AC0 _CAN3IDAR5.Bits.AC0 -#define CAN3IDAR5_AC1 _CAN3IDAR5.Bits.AC1 -#define CAN3IDAR5_AC2 _CAN3IDAR5.Bits.AC2 -#define CAN3IDAR5_AC3 _CAN3IDAR5.Bits.AC3 -#define CAN3IDAR5_AC4 _CAN3IDAR5.Bits.AC4 -#define CAN3IDAR5_AC5 _CAN3IDAR5.Bits.AC5 -#define CAN3IDAR5_AC6 _CAN3IDAR5.Bits.AC6 -#define CAN3IDAR5_AC7 _CAN3IDAR5.Bits.AC7 -#define CAN3IDAR5_AC _CAN3IDAR5.MergedBits.grpAC - - -/*** CAN3IDAR6 - MSCAN 3 Identifier Acceptance Register 6; 0x0000021A ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CAN3IDAR6STR; -extern volatile CAN3IDAR6STR _CAN3IDAR6 @(REG_BASE + 0x0000021A); -#define CAN3IDAR6 _CAN3IDAR6.Byte -#define CAN3IDAR6_AC0 _CAN3IDAR6.Bits.AC0 -#define CAN3IDAR6_AC1 _CAN3IDAR6.Bits.AC1 -#define CAN3IDAR6_AC2 _CAN3IDAR6.Bits.AC2 -#define CAN3IDAR6_AC3 _CAN3IDAR6.Bits.AC3 -#define CAN3IDAR6_AC4 _CAN3IDAR6.Bits.AC4 -#define CAN3IDAR6_AC5 _CAN3IDAR6.Bits.AC5 -#define CAN3IDAR6_AC6 _CAN3IDAR6.Bits.AC6 -#define CAN3IDAR6_AC7 _CAN3IDAR6.Bits.AC7 -#define CAN3IDAR6_AC _CAN3IDAR6.MergedBits.grpAC - - -/*** CAN3IDAR7 - MSCAN 3 Identifier Acceptance Register 7; 0x0000021B ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CAN3IDAR7STR; -extern volatile CAN3IDAR7STR _CAN3IDAR7 @(REG_BASE + 0x0000021B); -#define CAN3IDAR7 _CAN3IDAR7.Byte -#define CAN3IDAR7_AC0 _CAN3IDAR7.Bits.AC0 -#define CAN3IDAR7_AC1 _CAN3IDAR7.Bits.AC1 -#define CAN3IDAR7_AC2 _CAN3IDAR7.Bits.AC2 -#define CAN3IDAR7_AC3 _CAN3IDAR7.Bits.AC3 -#define CAN3IDAR7_AC4 _CAN3IDAR7.Bits.AC4 -#define CAN3IDAR7_AC5 _CAN3IDAR7.Bits.AC5 -#define CAN3IDAR7_AC6 _CAN3IDAR7.Bits.AC6 -#define CAN3IDAR7_AC7 _CAN3IDAR7.Bits.AC7 -#define CAN3IDAR7_AC _CAN3IDAR7.MergedBits.grpAC - - -/*** CAN3IDMR4 - MSCAN 3 Identifier Mask Register 4; 0x0000021C ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CAN3IDMR4STR; -extern volatile CAN3IDMR4STR _CAN3IDMR4 @(REG_BASE + 0x0000021C); -#define CAN3IDMR4 _CAN3IDMR4.Byte -#define CAN3IDMR4_AM0 _CAN3IDMR4.Bits.AM0 -#define CAN3IDMR4_AM1 _CAN3IDMR4.Bits.AM1 -#define CAN3IDMR4_AM2 _CAN3IDMR4.Bits.AM2 -#define CAN3IDMR4_AM3 _CAN3IDMR4.Bits.AM3 -#define CAN3IDMR4_AM4 _CAN3IDMR4.Bits.AM4 -#define CAN3IDMR4_AM5 _CAN3IDMR4.Bits.AM5 -#define CAN3IDMR4_AM6 _CAN3IDMR4.Bits.AM6 -#define CAN3IDMR4_AM7 _CAN3IDMR4.Bits.AM7 -#define CAN3IDMR4_AM _CAN3IDMR4.MergedBits.grpAM - - -/*** CAN3IDMR5 - MSCAN 3 Identifier Mask Register 5; 0x0000021D ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CAN3IDMR5STR; -extern volatile CAN3IDMR5STR _CAN3IDMR5 @(REG_BASE + 0x0000021D); -#define CAN3IDMR5 _CAN3IDMR5.Byte -#define CAN3IDMR5_AM0 _CAN3IDMR5.Bits.AM0 -#define CAN3IDMR5_AM1 _CAN3IDMR5.Bits.AM1 -#define CAN3IDMR5_AM2 _CAN3IDMR5.Bits.AM2 -#define CAN3IDMR5_AM3 _CAN3IDMR5.Bits.AM3 -#define CAN3IDMR5_AM4 _CAN3IDMR5.Bits.AM4 -#define CAN3IDMR5_AM5 _CAN3IDMR5.Bits.AM5 -#define CAN3IDMR5_AM6 _CAN3IDMR5.Bits.AM6 -#define CAN3IDMR5_AM7 _CAN3IDMR5.Bits.AM7 -#define CAN3IDMR5_AM _CAN3IDMR5.MergedBits.grpAM - - -/*** CAN3IDMR6 - MSCAN 3 Identifier Mask Register 6; 0x0000021E ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CAN3IDMR6STR; -extern volatile CAN3IDMR6STR _CAN3IDMR6 @(REG_BASE + 0x0000021E); -#define CAN3IDMR6 _CAN3IDMR6.Byte -#define CAN3IDMR6_AM0 _CAN3IDMR6.Bits.AM0 -#define CAN3IDMR6_AM1 _CAN3IDMR6.Bits.AM1 -#define CAN3IDMR6_AM2 _CAN3IDMR6.Bits.AM2 -#define CAN3IDMR6_AM3 _CAN3IDMR6.Bits.AM3 -#define CAN3IDMR6_AM4 _CAN3IDMR6.Bits.AM4 -#define CAN3IDMR6_AM5 _CAN3IDMR6.Bits.AM5 -#define CAN3IDMR6_AM6 _CAN3IDMR6.Bits.AM6 -#define CAN3IDMR6_AM7 _CAN3IDMR6.Bits.AM7 -#define CAN3IDMR6_AM _CAN3IDMR6.MergedBits.grpAM - - -/*** CAN3IDMR7 - MSCAN 3 Identifier Mask Register 7; 0x0000021F ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CAN3IDMR7STR; -extern volatile CAN3IDMR7STR _CAN3IDMR7 @(REG_BASE + 0x0000021F); -#define CAN3IDMR7 _CAN3IDMR7.Byte -#define CAN3IDMR7_AM0 _CAN3IDMR7.Bits.AM0 -#define CAN3IDMR7_AM1 _CAN3IDMR7.Bits.AM1 -#define CAN3IDMR7_AM2 _CAN3IDMR7.Bits.AM2 -#define CAN3IDMR7_AM3 _CAN3IDMR7.Bits.AM3 -#define CAN3IDMR7_AM4 _CAN3IDMR7.Bits.AM4 -#define CAN3IDMR7_AM5 _CAN3IDMR7.Bits.AM5 -#define CAN3IDMR7_AM6 _CAN3IDMR7.Bits.AM6 -#define CAN3IDMR7_AM7 _CAN3IDMR7.Bits.AM7 -#define CAN3IDMR7_AM _CAN3IDMR7.MergedBits.grpAM - - -/*** CAN3RXIDR0 - MSCAN 3 Receive Identifier Register 0; 0x00000220 ***/ -typedef union { - byte Byte; - struct { - byte ID21 :1; /* Extended format identifier Bit 21 */ - byte ID22 :1; /* Extended format identifier Bit 22 */ - byte ID23 :1; /* Extended format identifier Bit 23 */ - byte ID24 :1; /* Extended format identifier Bit 24 */ - byte ID25 :1; /* Extended format identifier Bit 25 */ - byte ID26 :1; /* Extended format identifier Bit 26 */ - byte ID27 :1; /* Extended format identifier Bit 27 */ - byte ID28 :1; /* Extended format identifier Bit 28 */ - } Bits; - struct { - byte grpID_21 :8; - } MergedBits; -} CAN3RXIDR0STR; -extern volatile CAN3RXIDR0STR _CAN3RXIDR0 @(REG_BASE + 0x00000220); -#define CAN3RXIDR0 _CAN3RXIDR0.Byte -#define CAN3RXIDR0_ID21 _CAN3RXIDR0.Bits.ID21 -#define CAN3RXIDR0_ID22 _CAN3RXIDR0.Bits.ID22 -#define CAN3RXIDR0_ID23 _CAN3RXIDR0.Bits.ID23 -#define CAN3RXIDR0_ID24 _CAN3RXIDR0.Bits.ID24 -#define CAN3RXIDR0_ID25 _CAN3RXIDR0.Bits.ID25 -#define CAN3RXIDR0_ID26 _CAN3RXIDR0.Bits.ID26 -#define CAN3RXIDR0_ID27 _CAN3RXIDR0.Bits.ID27 -#define CAN3RXIDR0_ID28 _CAN3RXIDR0.Bits.ID28 -#define CAN3RXIDR0_ID_21 _CAN3RXIDR0.MergedBits.grpID_21 -#define CAN3RXIDR0_ID CAN3RXIDR0_ID_21 - - -/*** CAN3RXIDR1 - MSCAN 3 Receive Identifier Register 1; 0x00000221 ***/ -typedef union { - byte Byte; - struct { - byte ID15 :1; /* Extended format identifier Bit 15 */ - byte ID16 :1; /* Extended format identifier Bit 16 */ - byte ID17 :1; /* Extended format identifier Bit 17 */ - byte IDE :1; /* ID Extended */ - byte SRR :1; /* Substitute Remote Request */ - byte ID18 :1; /* Extended format identifier Bit 18 */ - byte ID19 :1; /* Extended format identifier Bit 19 */ - byte ID20 :1; /* Extended format identifier Bit 20 */ - } Bits; - struct { - byte grpID_15 :3; - byte :1; - byte :1; - byte grpID_18 :3; - } MergedBits; -} CAN3RXIDR1STR; -extern volatile CAN3RXIDR1STR _CAN3RXIDR1 @(REG_BASE + 0x00000221); -#define CAN3RXIDR1 _CAN3RXIDR1.Byte -#define CAN3RXIDR1_ID15 _CAN3RXIDR1.Bits.ID15 -#define CAN3RXIDR1_ID16 _CAN3RXIDR1.Bits.ID16 -#define CAN3RXIDR1_ID17 _CAN3RXIDR1.Bits.ID17 -#define CAN3RXIDR1_IDE _CAN3RXIDR1.Bits.IDE -#define CAN3RXIDR1_SRR _CAN3RXIDR1.Bits.SRR -#define CAN3RXIDR1_ID18 _CAN3RXIDR1.Bits.ID18 -#define CAN3RXIDR1_ID19 _CAN3RXIDR1.Bits.ID19 -#define CAN3RXIDR1_ID20 _CAN3RXIDR1.Bits.ID20 -#define CAN3RXIDR1_ID_15 _CAN3RXIDR1.MergedBits.grpID_15 -#define CAN3RXIDR1_ID_18 _CAN3RXIDR1.MergedBits.grpID_18 -#define CAN3RXIDR1_ID CAN3RXIDR1_ID_15 - - -/*** CAN3RXIDR2 - MSCAN 3 Receive Identifier Register 2; 0x00000222 ***/ -typedef union { - byte Byte; - struct { - byte ID7 :1; /* Extended format identifier Bit 7 */ - byte ID8 :1; /* Extended format identifier Bit 8 */ - byte ID9 :1; /* Extended format identifier Bit 9 */ - byte ID10 :1; /* Extended format identifier Bit 10 */ - byte ID11 :1; /* Extended format identifier Bit 11 */ - byte ID12 :1; /* Extended format identifier Bit 12 */ - byte ID13 :1; /* Extended format identifier Bit 13 */ - byte ID14 :1; /* Extended format identifier Bit 14 */ - } Bits; - struct { - byte grpID_7 :8; - } MergedBits; -} CAN3RXIDR2STR; -extern volatile CAN3RXIDR2STR _CAN3RXIDR2 @(REG_BASE + 0x00000222); -#define CAN3RXIDR2 _CAN3RXIDR2.Byte -#define CAN3RXIDR2_ID7 _CAN3RXIDR2.Bits.ID7 -#define CAN3RXIDR2_ID8 _CAN3RXIDR2.Bits.ID8 -#define CAN3RXIDR2_ID9 _CAN3RXIDR2.Bits.ID9 -#define CAN3RXIDR2_ID10 _CAN3RXIDR2.Bits.ID10 -#define CAN3RXIDR2_ID11 _CAN3RXIDR2.Bits.ID11 -#define CAN3RXIDR2_ID12 _CAN3RXIDR2.Bits.ID12 -#define CAN3RXIDR2_ID13 _CAN3RXIDR2.Bits.ID13 -#define CAN3RXIDR2_ID14 _CAN3RXIDR2.Bits.ID14 -#define CAN3RXIDR2_ID_7 _CAN3RXIDR2.MergedBits.grpID_7 -#define CAN3RXIDR2_ID CAN3RXIDR2_ID_7 - - -/*** CAN3RXIDR3 - MSCAN 3 Receive Identifier Register 3; 0x00000223 ***/ -typedef union { - byte Byte; - struct { - byte RTR :1; /* Remote Transmission Request */ - byte ID0 :1; /* Extended format identifier Bit 0 */ - byte ID1 :1; /* Extended format identifier Bit 1 */ - byte ID2 :1; /* Extended format identifier Bit 2 */ - byte ID3 :1; /* Extended format identifier Bit 3 */ - byte ID4 :1; /* Extended format identifier Bit 4 */ - byte ID5 :1; /* Extended format identifier Bit 5 */ - byte ID6 :1; /* Extended format identifier Bit 6 */ - } Bits; - struct { - byte :1; - byte grpID :7; - } MergedBits; -} CAN3RXIDR3STR; -extern volatile CAN3RXIDR3STR _CAN3RXIDR3 @(REG_BASE + 0x00000223); -#define CAN3RXIDR3 _CAN3RXIDR3.Byte -#define CAN3RXIDR3_RTR _CAN3RXIDR3.Bits.RTR -#define CAN3RXIDR3_ID0 _CAN3RXIDR3.Bits.ID0 -#define CAN3RXIDR3_ID1 _CAN3RXIDR3.Bits.ID1 -#define CAN3RXIDR3_ID2 _CAN3RXIDR3.Bits.ID2 -#define CAN3RXIDR3_ID3 _CAN3RXIDR3.Bits.ID3 -#define CAN3RXIDR3_ID4 _CAN3RXIDR3.Bits.ID4 -#define CAN3RXIDR3_ID5 _CAN3RXIDR3.Bits.ID5 -#define CAN3RXIDR3_ID6 _CAN3RXIDR3.Bits.ID6 -#define CAN3RXIDR3_ID _CAN3RXIDR3.MergedBits.grpID - - -/*** CAN3RXDSR0 - MSCAN 3 Receive Data Segment Register 0; 0x00000224 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN3RXDSR0STR; -extern volatile CAN3RXDSR0STR _CAN3RXDSR0 @(REG_BASE + 0x00000224); -#define CAN3RXDSR0 _CAN3RXDSR0.Byte -#define CAN3RXDSR0_DB0 _CAN3RXDSR0.Bits.DB0 -#define CAN3RXDSR0_DB1 _CAN3RXDSR0.Bits.DB1 -#define CAN3RXDSR0_DB2 _CAN3RXDSR0.Bits.DB2 -#define CAN3RXDSR0_DB3 _CAN3RXDSR0.Bits.DB3 -#define CAN3RXDSR0_DB4 _CAN3RXDSR0.Bits.DB4 -#define CAN3RXDSR0_DB5 _CAN3RXDSR0.Bits.DB5 -#define CAN3RXDSR0_DB6 _CAN3RXDSR0.Bits.DB6 -#define CAN3RXDSR0_DB7 _CAN3RXDSR0.Bits.DB7 -#define CAN3RXDSR0_DB _CAN3RXDSR0.MergedBits.grpDB - - -/*** CAN3RXDSR1 - MSCAN 3 Receive Data Segment Register 1; 0x00000225 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN3RXDSR1STR; -extern volatile CAN3RXDSR1STR _CAN3RXDSR1 @(REG_BASE + 0x00000225); -#define CAN3RXDSR1 _CAN3RXDSR1.Byte -#define CAN3RXDSR1_DB0 _CAN3RXDSR1.Bits.DB0 -#define CAN3RXDSR1_DB1 _CAN3RXDSR1.Bits.DB1 -#define CAN3RXDSR1_DB2 _CAN3RXDSR1.Bits.DB2 -#define CAN3RXDSR1_DB3 _CAN3RXDSR1.Bits.DB3 -#define CAN3RXDSR1_DB4 _CAN3RXDSR1.Bits.DB4 -#define CAN3RXDSR1_DB5 _CAN3RXDSR1.Bits.DB5 -#define CAN3RXDSR1_DB6 _CAN3RXDSR1.Bits.DB6 -#define CAN3RXDSR1_DB7 _CAN3RXDSR1.Bits.DB7 -#define CAN3RXDSR1_DB _CAN3RXDSR1.MergedBits.grpDB - - -/*** CAN3RXDSR2 - MSCAN 3 Receive Data Segment Register 2; 0x00000226 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN3RXDSR2STR; -extern volatile CAN3RXDSR2STR _CAN3RXDSR2 @(REG_BASE + 0x00000226); -#define CAN3RXDSR2 _CAN3RXDSR2.Byte -#define CAN3RXDSR2_DB0 _CAN3RXDSR2.Bits.DB0 -#define CAN3RXDSR2_DB1 _CAN3RXDSR2.Bits.DB1 -#define CAN3RXDSR2_DB2 _CAN3RXDSR2.Bits.DB2 -#define CAN3RXDSR2_DB3 _CAN3RXDSR2.Bits.DB3 -#define CAN3RXDSR2_DB4 _CAN3RXDSR2.Bits.DB4 -#define CAN3RXDSR2_DB5 _CAN3RXDSR2.Bits.DB5 -#define CAN3RXDSR2_DB6 _CAN3RXDSR2.Bits.DB6 -#define CAN3RXDSR2_DB7 _CAN3RXDSR2.Bits.DB7 -#define CAN3RXDSR2_DB _CAN3RXDSR2.MergedBits.grpDB - - -/*** CAN3RXDSR3 - MSCAN 3 Receive Data Segment Register 3; 0x00000227 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN3RXDSR3STR; -extern volatile CAN3RXDSR3STR _CAN3RXDSR3 @(REG_BASE + 0x00000227); -#define CAN3RXDSR3 _CAN3RXDSR3.Byte -#define CAN3RXDSR3_DB0 _CAN3RXDSR3.Bits.DB0 -#define CAN3RXDSR3_DB1 _CAN3RXDSR3.Bits.DB1 -#define CAN3RXDSR3_DB2 _CAN3RXDSR3.Bits.DB2 -#define CAN3RXDSR3_DB3 _CAN3RXDSR3.Bits.DB3 -#define CAN3RXDSR3_DB4 _CAN3RXDSR3.Bits.DB4 -#define CAN3RXDSR3_DB5 _CAN3RXDSR3.Bits.DB5 -#define CAN3RXDSR3_DB6 _CAN3RXDSR3.Bits.DB6 -#define CAN3RXDSR3_DB7 _CAN3RXDSR3.Bits.DB7 -#define CAN3RXDSR3_DB _CAN3RXDSR3.MergedBits.grpDB - - -/*** CAN3RXDSR4 - MSCAN 3 Receive Data Segment Register 4; 0x00000228 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN3RXDSR4STR; -extern volatile CAN3RXDSR4STR _CAN3RXDSR4 @(REG_BASE + 0x00000228); -#define CAN3RXDSR4 _CAN3RXDSR4.Byte -#define CAN3RXDSR4_DB0 _CAN3RXDSR4.Bits.DB0 -#define CAN3RXDSR4_DB1 _CAN3RXDSR4.Bits.DB1 -#define CAN3RXDSR4_DB2 _CAN3RXDSR4.Bits.DB2 -#define CAN3RXDSR4_DB3 _CAN3RXDSR4.Bits.DB3 -#define CAN3RXDSR4_DB4 _CAN3RXDSR4.Bits.DB4 -#define CAN3RXDSR4_DB5 _CAN3RXDSR4.Bits.DB5 -#define CAN3RXDSR4_DB6 _CAN3RXDSR4.Bits.DB6 -#define CAN3RXDSR4_DB7 _CAN3RXDSR4.Bits.DB7 -#define CAN3RXDSR4_DB _CAN3RXDSR4.MergedBits.grpDB - - -/*** CAN3RXDSR5 - MSCAN 3 Receive Data Segment Register 5; 0x00000229 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN3RXDSR5STR; -extern volatile CAN3RXDSR5STR _CAN3RXDSR5 @(REG_BASE + 0x00000229); -#define CAN3RXDSR5 _CAN3RXDSR5.Byte -#define CAN3RXDSR5_DB0 _CAN3RXDSR5.Bits.DB0 -#define CAN3RXDSR5_DB1 _CAN3RXDSR5.Bits.DB1 -#define CAN3RXDSR5_DB2 _CAN3RXDSR5.Bits.DB2 -#define CAN3RXDSR5_DB3 _CAN3RXDSR5.Bits.DB3 -#define CAN3RXDSR5_DB4 _CAN3RXDSR5.Bits.DB4 -#define CAN3RXDSR5_DB5 _CAN3RXDSR5.Bits.DB5 -#define CAN3RXDSR5_DB6 _CAN3RXDSR5.Bits.DB6 -#define CAN3RXDSR5_DB7 _CAN3RXDSR5.Bits.DB7 -#define CAN3RXDSR5_DB _CAN3RXDSR5.MergedBits.grpDB - - -/*** CAN3RXDSR6 - MSCAN 3 Receive Data Segment Register 6; 0x0000022A ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN3RXDSR6STR; -extern volatile CAN3RXDSR6STR _CAN3RXDSR6 @(REG_BASE + 0x0000022A); -#define CAN3RXDSR6 _CAN3RXDSR6.Byte -#define CAN3RXDSR6_DB0 _CAN3RXDSR6.Bits.DB0 -#define CAN3RXDSR6_DB1 _CAN3RXDSR6.Bits.DB1 -#define CAN3RXDSR6_DB2 _CAN3RXDSR6.Bits.DB2 -#define CAN3RXDSR6_DB3 _CAN3RXDSR6.Bits.DB3 -#define CAN3RXDSR6_DB4 _CAN3RXDSR6.Bits.DB4 -#define CAN3RXDSR6_DB5 _CAN3RXDSR6.Bits.DB5 -#define CAN3RXDSR6_DB6 _CAN3RXDSR6.Bits.DB6 -#define CAN3RXDSR6_DB7 _CAN3RXDSR6.Bits.DB7 -#define CAN3RXDSR6_DB _CAN3RXDSR6.MergedBits.grpDB - - -/*** CAN3RXDSR7 - MSCAN 3 Receive Data Segment Register 7; 0x0000022B ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN3RXDSR7STR; -extern volatile CAN3RXDSR7STR _CAN3RXDSR7 @(REG_BASE + 0x0000022B); -#define CAN3RXDSR7 _CAN3RXDSR7.Byte -#define CAN3RXDSR7_DB0 _CAN3RXDSR7.Bits.DB0 -#define CAN3RXDSR7_DB1 _CAN3RXDSR7.Bits.DB1 -#define CAN3RXDSR7_DB2 _CAN3RXDSR7.Bits.DB2 -#define CAN3RXDSR7_DB3 _CAN3RXDSR7.Bits.DB3 -#define CAN3RXDSR7_DB4 _CAN3RXDSR7.Bits.DB4 -#define CAN3RXDSR7_DB5 _CAN3RXDSR7.Bits.DB5 -#define CAN3RXDSR7_DB6 _CAN3RXDSR7.Bits.DB6 -#define CAN3RXDSR7_DB7 _CAN3RXDSR7.Bits.DB7 -#define CAN3RXDSR7_DB _CAN3RXDSR7.MergedBits.grpDB - - -/*** CAN3RXDLR - MSCAN 3 Receive Data Length Register; 0x0000022C ***/ -typedef union { - byte Byte; - struct { - byte DLC0 :1; /* Data Length Code Bit 0 */ - byte DLC1 :1; /* Data Length Code Bit 1 */ - byte DLC2 :1; /* Data Length Code Bit 2 */ - byte DLC3 :1; /* Data Length Code Bit 3 */ - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpDLC :4; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} CAN3RXDLRSTR; -extern volatile CAN3RXDLRSTR _CAN3RXDLR @(REG_BASE + 0x0000022C); -#define CAN3RXDLR _CAN3RXDLR.Byte -#define CAN3RXDLR_DLC0 _CAN3RXDLR.Bits.DLC0 -#define CAN3RXDLR_DLC1 _CAN3RXDLR.Bits.DLC1 -#define CAN3RXDLR_DLC2 _CAN3RXDLR.Bits.DLC2 -#define CAN3RXDLR_DLC3 _CAN3RXDLR.Bits.DLC3 -#define CAN3RXDLR_DLC _CAN3RXDLR.MergedBits.grpDLC - - -/*** CAN3TXIDR0 - MSCAN 3 Transmit Identifier Register 0; 0x00000230 ***/ -typedef union { - byte Byte; - struct { - byte ID21 :1; /* Extended format identifier Bit 21 */ - byte ID22 :1; /* Extended format identifier Bit 22 */ - byte ID23 :1; /* Extended format identifier Bit 23 */ - byte ID24 :1; /* Extended format identifier Bit 24 */ - byte ID25 :1; /* Extended format identifier Bit 25 */ - byte ID26 :1; /* Extended format identifier Bit 26 */ - byte ID27 :1; /* Extended format identifier Bit 27 */ - byte ID28 :1; /* Extended format identifier Bit 28 */ - } Bits; - struct { - byte grpID_21 :8; - } MergedBits; -} CAN3TXIDR0STR; -extern volatile CAN3TXIDR0STR _CAN3TXIDR0 @(REG_BASE + 0x00000230); -#define CAN3TXIDR0 _CAN3TXIDR0.Byte -#define CAN3TXIDR0_ID21 _CAN3TXIDR0.Bits.ID21 -#define CAN3TXIDR0_ID22 _CAN3TXIDR0.Bits.ID22 -#define CAN3TXIDR0_ID23 _CAN3TXIDR0.Bits.ID23 -#define CAN3TXIDR0_ID24 _CAN3TXIDR0.Bits.ID24 -#define CAN3TXIDR0_ID25 _CAN3TXIDR0.Bits.ID25 -#define CAN3TXIDR0_ID26 _CAN3TXIDR0.Bits.ID26 -#define CAN3TXIDR0_ID27 _CAN3TXIDR0.Bits.ID27 -#define CAN3TXIDR0_ID28 _CAN3TXIDR0.Bits.ID28 -#define CAN3TXIDR0_ID_21 _CAN3TXIDR0.MergedBits.grpID_21 -#define CAN3TXIDR0_ID CAN3TXIDR0_ID_21 - - -/*** CAN3TXIDR1 - MSCAN 3 Transmit Identifier Register 1; 0x00000231 ***/ -typedef union { - byte Byte; - struct { - byte ID15 :1; /* Extended format identifier Bit 15 */ - byte ID16 :1; /* Extended format identifier Bit 16 */ - byte ID17 :1; /* Extended format identifier Bit 17 */ - byte IDE :1; /* ID Extended */ - byte SRR :1; /* Substitute Remote Request */ - byte ID18 :1; /* Extended format identifier Bit 18 */ - byte ID19 :1; /* Extended format identifier Bit 19 */ - byte ID20 :1; /* Extended format identifier Bit 20 */ - } Bits; - struct { - byte grpID_15 :3; - byte :1; - byte :1; - byte grpID_18 :3; - } MergedBits; -} CAN3TXIDR1STR; -extern volatile CAN3TXIDR1STR _CAN3TXIDR1 @(REG_BASE + 0x00000231); -#define CAN3TXIDR1 _CAN3TXIDR1.Byte -#define CAN3TXIDR1_ID15 _CAN3TXIDR1.Bits.ID15 -#define CAN3TXIDR1_ID16 _CAN3TXIDR1.Bits.ID16 -#define CAN3TXIDR1_ID17 _CAN3TXIDR1.Bits.ID17 -#define CAN3TXIDR1_IDE _CAN3TXIDR1.Bits.IDE -#define CAN3TXIDR1_SRR _CAN3TXIDR1.Bits.SRR -#define CAN3TXIDR1_ID18 _CAN3TXIDR1.Bits.ID18 -#define CAN3TXIDR1_ID19 _CAN3TXIDR1.Bits.ID19 -#define CAN3TXIDR1_ID20 _CAN3TXIDR1.Bits.ID20 -#define CAN3TXIDR1_ID_15 _CAN3TXIDR1.MergedBits.grpID_15 -#define CAN3TXIDR1_ID_18 _CAN3TXIDR1.MergedBits.grpID_18 -#define CAN3TXIDR1_ID CAN3TXIDR1_ID_15 - - -/*** CAN3TXIDR2 - MSCAN 3 Transmit Identifier Register 2; 0x00000232 ***/ -typedef union { - byte Byte; - struct { - byte ID7 :1; /* Extended format identifier Bit 7 */ - byte ID8 :1; /* Extended format identifier Bit 8 */ - byte ID9 :1; /* Extended format identifier Bit 9 */ - byte ID10 :1; /* Extended format identifier Bit 10 */ - byte ID11 :1; /* Extended format identifier Bit 11 */ - byte ID12 :1; /* Extended format identifier Bit 12 */ - byte ID13 :1; /* Extended format identifier Bit 13 */ - byte ID14 :1; /* Extended format identifier Bit 14 */ - } Bits; - struct { - byte grpID_7 :8; - } MergedBits; -} CAN3TXIDR2STR; -extern volatile CAN3TXIDR2STR _CAN3TXIDR2 @(REG_BASE + 0x00000232); -#define CAN3TXIDR2 _CAN3TXIDR2.Byte -#define CAN3TXIDR2_ID7 _CAN3TXIDR2.Bits.ID7 -#define CAN3TXIDR2_ID8 _CAN3TXIDR2.Bits.ID8 -#define CAN3TXIDR2_ID9 _CAN3TXIDR2.Bits.ID9 -#define CAN3TXIDR2_ID10 _CAN3TXIDR2.Bits.ID10 -#define CAN3TXIDR2_ID11 _CAN3TXIDR2.Bits.ID11 -#define CAN3TXIDR2_ID12 _CAN3TXIDR2.Bits.ID12 -#define CAN3TXIDR2_ID13 _CAN3TXIDR2.Bits.ID13 -#define CAN3TXIDR2_ID14 _CAN3TXIDR2.Bits.ID14 -#define CAN3TXIDR2_ID_7 _CAN3TXIDR2.MergedBits.grpID_7 -#define CAN3TXIDR2_ID CAN3TXIDR2_ID_7 - - -/*** CAN3TXIDR3 - MSCAN 3 Transmit Identifier Register 3; 0x00000233 ***/ -typedef union { - byte Byte; - struct { - byte RTR :1; /* Remote Transmission Request */ - byte ID0 :1; /* Extended format identifier Bit 0 */ - byte ID1 :1; /* Extended format identifier Bit 1 */ - byte ID2 :1; /* Extended format identifier Bit 2 */ - byte ID3 :1; /* Extended format identifier Bit 3 */ - byte ID4 :1; /* Extended format identifier Bit 4 */ - byte ID5 :1; /* Extended format identifier Bit 5 */ - byte ID6 :1; /* Extended format identifier Bit 6 */ - } Bits; - struct { - byte :1; - byte grpID :7; - } MergedBits; -} CAN3TXIDR3STR; -extern volatile CAN3TXIDR3STR _CAN3TXIDR3 @(REG_BASE + 0x00000233); -#define CAN3TXIDR3 _CAN3TXIDR3.Byte -#define CAN3TXIDR3_RTR _CAN3TXIDR3.Bits.RTR -#define CAN3TXIDR3_ID0 _CAN3TXIDR3.Bits.ID0 -#define CAN3TXIDR3_ID1 _CAN3TXIDR3.Bits.ID1 -#define CAN3TXIDR3_ID2 _CAN3TXIDR3.Bits.ID2 -#define CAN3TXIDR3_ID3 _CAN3TXIDR3.Bits.ID3 -#define CAN3TXIDR3_ID4 _CAN3TXIDR3.Bits.ID4 -#define CAN3TXIDR3_ID5 _CAN3TXIDR3.Bits.ID5 -#define CAN3TXIDR3_ID6 _CAN3TXIDR3.Bits.ID6 -#define CAN3TXIDR3_ID _CAN3TXIDR3.MergedBits.grpID - - -/*** CAN3TXDSR0 - MSCAN 3 Transmit Data Segment Register 0; 0x00000234 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN3TXDSR0STR; -extern volatile CAN3TXDSR0STR _CAN3TXDSR0 @(REG_BASE + 0x00000234); -#define CAN3TXDSR0 _CAN3TXDSR0.Byte -#define CAN3TXDSR0_DB0 _CAN3TXDSR0.Bits.DB0 -#define CAN3TXDSR0_DB1 _CAN3TXDSR0.Bits.DB1 -#define CAN3TXDSR0_DB2 _CAN3TXDSR0.Bits.DB2 -#define CAN3TXDSR0_DB3 _CAN3TXDSR0.Bits.DB3 -#define CAN3TXDSR0_DB4 _CAN3TXDSR0.Bits.DB4 -#define CAN3TXDSR0_DB5 _CAN3TXDSR0.Bits.DB5 -#define CAN3TXDSR0_DB6 _CAN3TXDSR0.Bits.DB6 -#define CAN3TXDSR0_DB7 _CAN3TXDSR0.Bits.DB7 -#define CAN3TXDSR0_DB _CAN3TXDSR0.MergedBits.grpDB - - -/*** CAN3TXDSR1 - MSCAN 3 Transmit Data Segment Register 1; 0x00000235 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN3TXDSR1STR; -extern volatile CAN3TXDSR1STR _CAN3TXDSR1 @(REG_BASE + 0x00000235); -#define CAN3TXDSR1 _CAN3TXDSR1.Byte -#define CAN3TXDSR1_DB0 _CAN3TXDSR1.Bits.DB0 -#define CAN3TXDSR1_DB1 _CAN3TXDSR1.Bits.DB1 -#define CAN3TXDSR1_DB2 _CAN3TXDSR1.Bits.DB2 -#define CAN3TXDSR1_DB3 _CAN3TXDSR1.Bits.DB3 -#define CAN3TXDSR1_DB4 _CAN3TXDSR1.Bits.DB4 -#define CAN3TXDSR1_DB5 _CAN3TXDSR1.Bits.DB5 -#define CAN3TXDSR1_DB6 _CAN3TXDSR1.Bits.DB6 -#define CAN3TXDSR1_DB7 _CAN3TXDSR1.Bits.DB7 -#define CAN3TXDSR1_DB _CAN3TXDSR1.MergedBits.grpDB - - -/*** CAN3TXDSR2 - MSCAN 3 Transmit Data Segment Register 2; 0x00000236 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN3TXDSR2STR; -extern volatile CAN3TXDSR2STR _CAN3TXDSR2 @(REG_BASE + 0x00000236); -#define CAN3TXDSR2 _CAN3TXDSR2.Byte -#define CAN3TXDSR2_DB0 _CAN3TXDSR2.Bits.DB0 -#define CAN3TXDSR2_DB1 _CAN3TXDSR2.Bits.DB1 -#define CAN3TXDSR2_DB2 _CAN3TXDSR2.Bits.DB2 -#define CAN3TXDSR2_DB3 _CAN3TXDSR2.Bits.DB3 -#define CAN3TXDSR2_DB4 _CAN3TXDSR2.Bits.DB4 -#define CAN3TXDSR2_DB5 _CAN3TXDSR2.Bits.DB5 -#define CAN3TXDSR2_DB6 _CAN3TXDSR2.Bits.DB6 -#define CAN3TXDSR2_DB7 _CAN3TXDSR2.Bits.DB7 -#define CAN3TXDSR2_DB _CAN3TXDSR2.MergedBits.grpDB - - -/*** CAN3TXDSR3 - MSCAN 3 Transmit Data Segment Register 3; 0x00000237 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN3TXDSR3STR; -extern volatile CAN3TXDSR3STR _CAN3TXDSR3 @(REG_BASE + 0x00000237); -#define CAN3TXDSR3 _CAN3TXDSR3.Byte -#define CAN3TXDSR3_DB0 _CAN3TXDSR3.Bits.DB0 -#define CAN3TXDSR3_DB1 _CAN3TXDSR3.Bits.DB1 -#define CAN3TXDSR3_DB2 _CAN3TXDSR3.Bits.DB2 -#define CAN3TXDSR3_DB3 _CAN3TXDSR3.Bits.DB3 -#define CAN3TXDSR3_DB4 _CAN3TXDSR3.Bits.DB4 -#define CAN3TXDSR3_DB5 _CAN3TXDSR3.Bits.DB5 -#define CAN3TXDSR3_DB6 _CAN3TXDSR3.Bits.DB6 -#define CAN3TXDSR3_DB7 _CAN3TXDSR3.Bits.DB7 -#define CAN3TXDSR3_DB _CAN3TXDSR3.MergedBits.grpDB - - -/*** CAN3TXDSR4 - MSCAN 3 Transmit Data Segment Register 4; 0x00000238 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN3TXDSR4STR; -extern volatile CAN3TXDSR4STR _CAN3TXDSR4 @(REG_BASE + 0x00000238); -#define CAN3TXDSR4 _CAN3TXDSR4.Byte -#define CAN3TXDSR4_DB0 _CAN3TXDSR4.Bits.DB0 -#define CAN3TXDSR4_DB1 _CAN3TXDSR4.Bits.DB1 -#define CAN3TXDSR4_DB2 _CAN3TXDSR4.Bits.DB2 -#define CAN3TXDSR4_DB3 _CAN3TXDSR4.Bits.DB3 -#define CAN3TXDSR4_DB4 _CAN3TXDSR4.Bits.DB4 -#define CAN3TXDSR4_DB5 _CAN3TXDSR4.Bits.DB5 -#define CAN3TXDSR4_DB6 _CAN3TXDSR4.Bits.DB6 -#define CAN3TXDSR4_DB7 _CAN3TXDSR4.Bits.DB7 -#define CAN3TXDSR4_DB _CAN3TXDSR4.MergedBits.grpDB - - -/*** CAN3TXDSR5 - MSCAN 3 Transmit Data Segment Register 5; 0x00000239 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN3TXDSR5STR; -extern volatile CAN3TXDSR5STR _CAN3TXDSR5 @(REG_BASE + 0x00000239); -#define CAN3TXDSR5 _CAN3TXDSR5.Byte -#define CAN3TXDSR5_DB0 _CAN3TXDSR5.Bits.DB0 -#define CAN3TXDSR5_DB1 _CAN3TXDSR5.Bits.DB1 -#define CAN3TXDSR5_DB2 _CAN3TXDSR5.Bits.DB2 -#define CAN3TXDSR5_DB3 _CAN3TXDSR5.Bits.DB3 -#define CAN3TXDSR5_DB4 _CAN3TXDSR5.Bits.DB4 -#define CAN3TXDSR5_DB5 _CAN3TXDSR5.Bits.DB5 -#define CAN3TXDSR5_DB6 _CAN3TXDSR5.Bits.DB6 -#define CAN3TXDSR5_DB7 _CAN3TXDSR5.Bits.DB7 -#define CAN3TXDSR5_DB _CAN3TXDSR5.MergedBits.grpDB - - -/*** CAN3TXDSR6 - MSCAN 3 Transmit Data Segment Register 6; 0x0000023A ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN3TXDSR6STR; -extern volatile CAN3TXDSR6STR _CAN3TXDSR6 @(REG_BASE + 0x0000023A); -#define CAN3TXDSR6 _CAN3TXDSR6.Byte -#define CAN3TXDSR6_DB0 _CAN3TXDSR6.Bits.DB0 -#define CAN3TXDSR6_DB1 _CAN3TXDSR6.Bits.DB1 -#define CAN3TXDSR6_DB2 _CAN3TXDSR6.Bits.DB2 -#define CAN3TXDSR6_DB3 _CAN3TXDSR6.Bits.DB3 -#define CAN3TXDSR6_DB4 _CAN3TXDSR6.Bits.DB4 -#define CAN3TXDSR6_DB5 _CAN3TXDSR6.Bits.DB5 -#define CAN3TXDSR6_DB6 _CAN3TXDSR6.Bits.DB6 -#define CAN3TXDSR6_DB7 _CAN3TXDSR6.Bits.DB7 -#define CAN3TXDSR6_DB _CAN3TXDSR6.MergedBits.grpDB - - -/*** CAN3TXDSR7 - MSCAN 3 Transmit Data Segment Register 7; 0x0000023B ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN3TXDSR7STR; -extern volatile CAN3TXDSR7STR _CAN3TXDSR7 @(REG_BASE + 0x0000023B); -#define CAN3TXDSR7 _CAN3TXDSR7.Byte -#define CAN3TXDSR7_DB0 _CAN3TXDSR7.Bits.DB0 -#define CAN3TXDSR7_DB1 _CAN3TXDSR7.Bits.DB1 -#define CAN3TXDSR7_DB2 _CAN3TXDSR7.Bits.DB2 -#define CAN3TXDSR7_DB3 _CAN3TXDSR7.Bits.DB3 -#define CAN3TXDSR7_DB4 _CAN3TXDSR7.Bits.DB4 -#define CAN3TXDSR7_DB5 _CAN3TXDSR7.Bits.DB5 -#define CAN3TXDSR7_DB6 _CAN3TXDSR7.Bits.DB6 -#define CAN3TXDSR7_DB7 _CAN3TXDSR7.Bits.DB7 -#define CAN3TXDSR7_DB _CAN3TXDSR7.MergedBits.grpDB - - -/*** CAN3TXDLR - MSCAN 3 Transmit Data Length Register; 0x0000023C ***/ -typedef union { - byte Byte; - struct { - byte DLC0 :1; /* Data Length Code Bit 0 */ - byte DLC1 :1; /* Data Length Code Bit 1 */ - byte DLC2 :1; /* Data Length Code Bit 2 */ - byte DLC3 :1; /* Data Length Code Bit 3 */ - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpDLC :4; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} CAN3TXDLRSTR; -extern volatile CAN3TXDLRSTR _CAN3TXDLR @(REG_BASE + 0x0000023C); -#define CAN3TXDLR _CAN3TXDLR.Byte -#define CAN3TXDLR_DLC0 _CAN3TXDLR.Bits.DLC0 -#define CAN3TXDLR_DLC1 _CAN3TXDLR.Bits.DLC1 -#define CAN3TXDLR_DLC2 _CAN3TXDLR.Bits.DLC2 -#define CAN3TXDLR_DLC3 _CAN3TXDLR.Bits.DLC3 -#define CAN3TXDLR_DLC _CAN3TXDLR.MergedBits.grpDLC - - -/*** CAN3TXTBPR - MSCAN 3 Transmit Buffer Priority; 0x0000023F ***/ -typedef union { - byte Byte; - struct { - byte PRIO0 :1; /* Transmit Buffer Priority Bit 0 */ - byte PRIO1 :1; /* Transmit Buffer Priority Bit 1 */ - byte PRIO2 :1; /* Transmit Buffer Priority Bit 2 */ - byte PRIO3 :1; /* Transmit Buffer Priority Bit 3 */ - byte PRIO4 :1; /* Transmit Buffer Priority Bit 4 */ - byte PRIO5 :1; /* Transmit Buffer Priority Bit 5 */ - byte PRIO6 :1; /* Transmit Buffer Priority Bit 6 */ - byte PRIO7 :1; /* Transmit Buffer Priority Bit 7 */ - } Bits; - struct { - byte grpPRIO :8; - } MergedBits; -} CAN3TXTBPRSTR; -extern volatile CAN3TXTBPRSTR _CAN3TXTBPR @(REG_BASE + 0x0000023F); -#define CAN3TXTBPR _CAN3TXTBPR.Byte -#define CAN3TXTBPR_PRIO0 _CAN3TXTBPR.Bits.PRIO0 -#define CAN3TXTBPR_PRIO1 _CAN3TXTBPR.Bits.PRIO1 -#define CAN3TXTBPR_PRIO2 _CAN3TXTBPR.Bits.PRIO2 -#define CAN3TXTBPR_PRIO3 _CAN3TXTBPR.Bits.PRIO3 -#define CAN3TXTBPR_PRIO4 _CAN3TXTBPR.Bits.PRIO4 -#define CAN3TXTBPR_PRIO5 _CAN3TXTBPR.Bits.PRIO5 -#define CAN3TXTBPR_PRIO6 _CAN3TXTBPR.Bits.PRIO6 -#define CAN3TXTBPR_PRIO7 _CAN3TXTBPR.Bits.PRIO7 -#define CAN3TXTBPR_PRIO _CAN3TXTBPR.MergedBits.grpPRIO - - -/*** PTT - Port T I/O Register; 0x00000240 ***/ -typedef union { - byte Byte; - struct { - byte PTT0 :1; /* Port T Bit 0 */ - byte PTT1 :1; /* Port T Bit 1 */ - byte PTT2 :1; /* Port T Bit 2 */ - byte PTT3 :1; /* Port T Bit 3 */ - byte PTT4 :1; /* Port T Bit 4 */ - byte PTT5 :1; /* Port T Bit 5 */ - byte PTT6 :1; /* Port T Bit 6 */ - byte PTT7 :1; /* Port T Bit 7 */ - } Bits; - struct { - byte grpPTT :8; - } MergedBits; -} PTTSTR; -extern volatile PTTSTR _PTT @(REG_BASE + 0x00000240); -#define PTT _PTT.Byte -#define PTT_PTT0 _PTT.Bits.PTT0 -#define PTT_PTT1 _PTT.Bits.PTT1 -#define PTT_PTT2 _PTT.Bits.PTT2 -#define PTT_PTT3 _PTT.Bits.PTT3 -#define PTT_PTT4 _PTT.Bits.PTT4 -#define PTT_PTT5 _PTT.Bits.PTT5 -#define PTT_PTT6 _PTT.Bits.PTT6 -#define PTT_PTT7 _PTT.Bits.PTT7 -#define PTT_PTT _PTT.MergedBits.grpPTT - - -/*** PTIT - Port T Input; 0x00000241 ***/ -typedef union { - byte Byte; - struct { - byte PTIT0 :1; /* Port T Bit 0 */ - byte PTIT1 :1; /* Port T Bit 1 */ - byte PTIT2 :1; /* Port T Bit 2 */ - byte PTIT3 :1; /* Port T Bit 3 */ - byte PTIT4 :1; /* Port T Bit 4 */ - byte PTIT5 :1; /* Port T Bit 5 */ - byte PTIT6 :1; /* Port T Bit 6 */ - byte PTIT7 :1; /* Port T Bit 7 */ - } Bits; - struct { - byte grpPTIT :8; - } MergedBits; -} PTITSTR; -extern volatile PTITSTR _PTIT @(REG_BASE + 0x00000241); -#define PTIT _PTIT.Byte -#define PTIT_PTIT0 _PTIT.Bits.PTIT0 -#define PTIT_PTIT1 _PTIT.Bits.PTIT1 -#define PTIT_PTIT2 _PTIT.Bits.PTIT2 -#define PTIT_PTIT3 _PTIT.Bits.PTIT3 -#define PTIT_PTIT4 _PTIT.Bits.PTIT4 -#define PTIT_PTIT5 _PTIT.Bits.PTIT5 -#define PTIT_PTIT6 _PTIT.Bits.PTIT6 -#define PTIT_PTIT7 _PTIT.Bits.PTIT7 -#define PTIT_PTIT _PTIT.MergedBits.grpPTIT - - -/*** DDRT - Port T Data Direction Register; 0x00000242 ***/ -typedef union { - byte Byte; - struct { - byte DDRT0 :1; /* Data Direction Port T Bit 0 */ - byte DDRT1 :1; /* Data Direction Port T Bit 1 */ - byte DDRT2 :1; /* Data Direction Port T Bit 2 */ - byte DDRT3 :1; /* Data Direction Port T Bit 3 */ - byte DDRT4 :1; /* Data Direction Port T Bit 4 */ - byte DDRT5 :1; /* Data Direction Port T Bit 5 */ - byte DDRT6 :1; /* Data Direction Port T Bit 6 */ - byte DDRT7 :1; /* Data Direction Port T Bit 7 */ - } Bits; - struct { - byte grpDDRT :8; - } MergedBits; -} DDRTSTR; -extern volatile DDRTSTR _DDRT @(REG_BASE + 0x00000242); -#define DDRT _DDRT.Byte -#define DDRT_DDRT0 _DDRT.Bits.DDRT0 -#define DDRT_DDRT1 _DDRT.Bits.DDRT1 -#define DDRT_DDRT2 _DDRT.Bits.DDRT2 -#define DDRT_DDRT3 _DDRT.Bits.DDRT3 -#define DDRT_DDRT4 _DDRT.Bits.DDRT4 -#define DDRT_DDRT5 _DDRT.Bits.DDRT5 -#define DDRT_DDRT6 _DDRT.Bits.DDRT6 -#define DDRT_DDRT7 _DDRT.Bits.DDRT7 -#define DDRT_DDRT _DDRT.MergedBits.grpDDRT - - -/*** RDRT - Port T Reduced Drive Register; 0x00000243 ***/ -typedef union { - byte Byte; - struct { - byte RDRT0 :1; /* Reduced Drive Port T Bit 0 */ - byte RDRT1 :1; /* Reduced Drive Port T Bit 1 */ - byte RDRT2 :1; /* Reduced Drive Port T Bit 2 */ - byte RDRT3 :1; /* Reduced Drive Port T Bit 3 */ - byte RDRT4 :1; /* Reduced Drive Port T Bit 4 */ - byte RDRT5 :1; /* Reduced Drive Port T Bit 5 */ - byte RDRT6 :1; /* Reduced Drive Port T Bit 6 */ - byte RDRT7 :1; /* Reduced Drive Port T Bit 7 */ - } Bits; - struct { - byte grpRDRT :8; - } MergedBits; -} RDRTSTR; -extern volatile RDRTSTR _RDRT @(REG_BASE + 0x00000243); -#define RDRT _RDRT.Byte -#define RDRT_RDRT0 _RDRT.Bits.RDRT0 -#define RDRT_RDRT1 _RDRT.Bits.RDRT1 -#define RDRT_RDRT2 _RDRT.Bits.RDRT2 -#define RDRT_RDRT3 _RDRT.Bits.RDRT3 -#define RDRT_RDRT4 _RDRT.Bits.RDRT4 -#define RDRT_RDRT5 _RDRT.Bits.RDRT5 -#define RDRT_RDRT6 _RDRT.Bits.RDRT6 -#define RDRT_RDRT7 _RDRT.Bits.RDRT7 -#define RDRT_RDRT _RDRT.MergedBits.grpRDRT - - -/*** PERT - Port T Pull Device Enable Register; 0x00000244 ***/ -typedef union { - byte Byte; - struct { - byte PERT0 :1; /* Pull Device Enable Port T Bit 0 */ - byte PERT1 :1; /* Pull Device Enable Port T Bit 1 */ - byte PERT2 :1; /* Pull Device Enable Port T Bit 2 */ - byte PERT3 :1; /* Pull Device Enable Port T Bit 3 */ - byte PERT4 :1; /* Pull Device Enable Port T Bit 4 */ - byte PERT5 :1; /* Pull Device Enable Port T Bit 5 */ - byte PERT6 :1; /* Pull Device Enable Port T Bit 6 */ - byte PERT7 :1; /* Pull Device Enable Port T Bit 7 */ - } Bits; - struct { - byte grpPERT :8; - } MergedBits; -} PERTSTR; -extern volatile PERTSTR _PERT @(REG_BASE + 0x00000244); -#define PERT _PERT.Byte -#define PERT_PERT0 _PERT.Bits.PERT0 -#define PERT_PERT1 _PERT.Bits.PERT1 -#define PERT_PERT2 _PERT.Bits.PERT2 -#define PERT_PERT3 _PERT.Bits.PERT3 -#define PERT_PERT4 _PERT.Bits.PERT4 -#define PERT_PERT5 _PERT.Bits.PERT5 -#define PERT_PERT6 _PERT.Bits.PERT6 -#define PERT_PERT7 _PERT.Bits.PERT7 -#define PERT_PERT _PERT.MergedBits.grpPERT - - -/*** PPST - Port T Polarity Select Register; 0x00000245 ***/ -typedef union { - byte Byte; - struct { - byte PPST0 :1; /* Pull Select Port T Bit 0 */ - byte PPST1 :1; /* Pull Select Port T Bit 1 */ - byte PPST2 :1; /* Pull Select Port T Bit 2 */ - byte PPST3 :1; /* Pull Select Port T Bit 3 */ - byte PPST4 :1; /* Pull Select Port T Bit 4 */ - byte PPST5 :1; /* Pull Select Port T Bit 5 */ - byte PPST6 :1; /* Pull Select Port T Bit 6 */ - byte PPST7 :1; /* Pull Select Port T Bit 7 */ - } Bits; - struct { - byte grpPPST :8; - } MergedBits; -} PPSTSTR; -extern volatile PPSTSTR _PPST @(REG_BASE + 0x00000245); -#define PPST _PPST.Byte -#define PPST_PPST0 _PPST.Bits.PPST0 -#define PPST_PPST1 _PPST.Bits.PPST1 -#define PPST_PPST2 _PPST.Bits.PPST2 -#define PPST_PPST3 _PPST.Bits.PPST3 -#define PPST_PPST4 _PPST.Bits.PPST4 -#define PPST_PPST5 _PPST.Bits.PPST5 -#define PPST_PPST6 _PPST.Bits.PPST6 -#define PPST_PPST7 _PPST.Bits.PPST7 -#define PPST_PPST _PPST.MergedBits.grpPPST - - -/*** PTS - Port S I/O Register; 0x00000248 ***/ -typedef union { - byte Byte; - struct { - byte PTS0 :1; /* Port S Bit 0 */ - byte PTS1 :1; /* Port S Bit 1 */ - byte PTS2 :1; /* Port S Bit 2 */ - byte PTS3 :1; /* Port S Bit 3 */ - byte PTS4 :1; /* Port S Bit 4 */ - byte PTS5 :1; /* Port S Bit 5 */ - byte PTS6 :1; /* Port S Bit 6 */ - byte PTS7 :1; /* Port S Bit 7 */ - } Bits; - struct { - byte grpPTS :8; - } MergedBits; -} PTSSTR; -extern volatile PTSSTR _PTS @(REG_BASE + 0x00000248); -#define PTS _PTS.Byte -#define PTS_PTS0 _PTS.Bits.PTS0 -#define PTS_PTS1 _PTS.Bits.PTS1 -#define PTS_PTS2 _PTS.Bits.PTS2 -#define PTS_PTS3 _PTS.Bits.PTS3 -#define PTS_PTS4 _PTS.Bits.PTS4 -#define PTS_PTS5 _PTS.Bits.PTS5 -#define PTS_PTS6 _PTS.Bits.PTS6 -#define PTS_PTS7 _PTS.Bits.PTS7 -#define PTS_PTS _PTS.MergedBits.grpPTS - - -/*** PTIS - Port S Input; 0x00000249 ***/ -typedef union { - byte Byte; - struct { - byte PTIS0 :1; /* Port S Bit 0 */ - byte PTIS1 :1; /* Port S Bit 1 */ - byte PTIS2 :1; /* Port S Bit 2 */ - byte PTIS3 :1; /* Port S Bit 3 */ - byte PTIS4 :1; /* Port S Bit 4 */ - byte PTIS5 :1; /* Port S Bit 5 */ - byte PTIS6 :1; /* Port S Bit 6 */ - byte PTIS7 :1; /* Port S Bit 7 */ - } Bits; - struct { - byte grpPTIS :8; - } MergedBits; -} PTISSTR; -extern volatile PTISSTR _PTIS @(REG_BASE + 0x00000249); -#define PTIS _PTIS.Byte -#define PTIS_PTIS0 _PTIS.Bits.PTIS0 -#define PTIS_PTIS1 _PTIS.Bits.PTIS1 -#define PTIS_PTIS2 _PTIS.Bits.PTIS2 -#define PTIS_PTIS3 _PTIS.Bits.PTIS3 -#define PTIS_PTIS4 _PTIS.Bits.PTIS4 -#define PTIS_PTIS5 _PTIS.Bits.PTIS5 -#define PTIS_PTIS6 _PTIS.Bits.PTIS6 -#define PTIS_PTIS7 _PTIS.Bits.PTIS7 -#define PTIS_PTIS _PTIS.MergedBits.grpPTIS - - -/*** DDRS - Port S Data Direction Register; 0x0000024A ***/ -typedef union { - byte Byte; - struct { - byte DDRS0 :1; /* Data Direction Port S Bit 0 */ - byte DDRS1 :1; /* Data Direction Port S Bit 1 */ - byte DDRS2 :1; /* Data Direction Port S Bit 2 */ - byte DDRS3 :1; /* Data Direction Port S Bit 3 */ - byte DDRS4 :1; /* Data Direction Port S Bit 4 */ - byte DDRS5 :1; /* Data Direction Port S Bit 5 */ - byte DDRS6 :1; /* Data Direction Port S Bit 6 */ - byte DDRS7 :1; /* Data Direction Port S Bit 7 */ - } Bits; - struct { - byte grpDDRS :8; - } MergedBits; -} DDRSSTR; -extern volatile DDRSSTR _DDRS @(REG_BASE + 0x0000024A); -#define DDRS _DDRS.Byte -#define DDRS_DDRS0 _DDRS.Bits.DDRS0 -#define DDRS_DDRS1 _DDRS.Bits.DDRS1 -#define DDRS_DDRS2 _DDRS.Bits.DDRS2 -#define DDRS_DDRS3 _DDRS.Bits.DDRS3 -#define DDRS_DDRS4 _DDRS.Bits.DDRS4 -#define DDRS_DDRS5 _DDRS.Bits.DDRS5 -#define DDRS_DDRS6 _DDRS.Bits.DDRS6 -#define DDRS_DDRS7 _DDRS.Bits.DDRS7 -#define DDRS_DDRS _DDRS.MergedBits.grpDDRS - - -/*** RDRS - Port S Reduced Drive Register; 0x0000024B ***/ -typedef union { - byte Byte; - struct { - byte RDRS0 :1; /* Reduced Drive Port S Bit 0 */ - byte RDRS1 :1; /* Reduced Drive Port S Bit 1 */ - byte RDRS2 :1; /* Reduced Drive Port S Bit 2 */ - byte RDRS3 :1; /* Reduced Drive Port S Bit 3 */ - byte RDRS4 :1; /* Reduced Drive Port S Bit 4 */ - byte RDRS5 :1; /* Reduced Drive Port S Bit 5 */ - byte RDRS6 :1; /* Reduced Drive Port S Bit 6 */ - byte RDRS7 :1; /* Reduced Drive Port S Bit 7 */ - } Bits; - struct { - byte grpRDRS :8; - } MergedBits; -} RDRSSTR; -extern volatile RDRSSTR _RDRS @(REG_BASE + 0x0000024B); -#define RDRS _RDRS.Byte -#define RDRS_RDRS0 _RDRS.Bits.RDRS0 -#define RDRS_RDRS1 _RDRS.Bits.RDRS1 -#define RDRS_RDRS2 _RDRS.Bits.RDRS2 -#define RDRS_RDRS3 _RDRS.Bits.RDRS3 -#define RDRS_RDRS4 _RDRS.Bits.RDRS4 -#define RDRS_RDRS5 _RDRS.Bits.RDRS5 -#define RDRS_RDRS6 _RDRS.Bits.RDRS6 -#define RDRS_RDRS7 _RDRS.Bits.RDRS7 -#define RDRS_RDRS _RDRS.MergedBits.grpRDRS - - -/*** PERS - Port S Pull Device Enable Register; 0x0000024C ***/ -typedef union { - byte Byte; - struct { - byte PERS0 :1; /* Pull Device Enable Port S Bit 0 */ - byte PERS1 :1; /* Pull Device Enable Port S Bit 1 */ - byte PERS2 :1; /* Pull Device Enable Port S Bit 2 */ - byte PERS3 :1; /* Pull Device Enable Port S Bit 3 */ - byte PERS4 :1; /* Pull Device Enable Port S Bit 4 */ - byte PERS5 :1; /* Pull Device Enable Port S Bit 5 */ - byte PERS6 :1; /* Pull Device Enable Port S Bit 6 */ - byte PERS7 :1; /* Pull Device Enable Port S Bit 7 */ - } Bits; - struct { - byte grpPERS :8; - } MergedBits; -} PERSSTR; -extern volatile PERSSTR _PERS @(REG_BASE + 0x0000024C); -#define PERS _PERS.Byte -#define PERS_PERS0 _PERS.Bits.PERS0 -#define PERS_PERS1 _PERS.Bits.PERS1 -#define PERS_PERS2 _PERS.Bits.PERS2 -#define PERS_PERS3 _PERS.Bits.PERS3 -#define PERS_PERS4 _PERS.Bits.PERS4 -#define PERS_PERS5 _PERS.Bits.PERS5 -#define PERS_PERS6 _PERS.Bits.PERS6 -#define PERS_PERS7 _PERS.Bits.PERS7 -#define PERS_PERS _PERS.MergedBits.grpPERS - - -/*** PPSS - Port S Polarity Select Register; 0x0000024D ***/ -typedef union { - byte Byte; - struct { - byte PPSS0 :1; /* Pull Select Port S Bit 0 */ - byte PPSS1 :1; /* Pull Select Port S Bit 1 */ - byte PPSS2 :1; /* Pull Select Port S Bit 2 */ - byte PPSS3 :1; /* Pull Select Port S Bit 3 */ - byte PPSS4 :1; /* Pull Select Port S Bit 4 */ - byte PPSS5 :1; /* Pull Select Port S Bit 5 */ - byte PPSS6 :1; /* Pull Select Port S Bit 6 */ - byte PPSS7 :1; /* Pull Select Port S Bit 7 */ - } Bits; - struct { - byte grpPPSS :8; - } MergedBits; -} PPSSSTR; -extern volatile PPSSSTR _PPSS @(REG_BASE + 0x0000024D); -#define PPSS _PPSS.Byte -#define PPSS_PPSS0 _PPSS.Bits.PPSS0 -#define PPSS_PPSS1 _PPSS.Bits.PPSS1 -#define PPSS_PPSS2 _PPSS.Bits.PPSS2 -#define PPSS_PPSS3 _PPSS.Bits.PPSS3 -#define PPSS_PPSS4 _PPSS.Bits.PPSS4 -#define PPSS_PPSS5 _PPSS.Bits.PPSS5 -#define PPSS_PPSS6 _PPSS.Bits.PPSS6 -#define PPSS_PPSS7 _PPSS.Bits.PPSS7 -#define PPSS_PPSS _PPSS.MergedBits.grpPPSS - - -/*** WOMS - Port S Wired-Or Mode Register; 0x0000024E ***/ -typedef union { - byte Byte; - struct { - byte WOMS0 :1; /* Wired-Or Mode Port S Bit 0 */ - byte WOMS1 :1; /* Wired-Or Mode Port S Bit 1 */ - byte WOMS2 :1; /* Wired-Or Mode Port S Bit 2 */ - byte WOMS3 :1; /* Wired-Or Mode Port S Bit 3 */ - byte WOMS4 :1; /* Wired-Or Mode Port S Bit 4 */ - byte WOMS5 :1; /* Wired-Or Mode Port S Bit 5 */ - byte WOMS6 :1; /* Wired-Or Mode Port S Bit 6 */ - byte WOMS7 :1; /* Wired-Or Mode Port S Bit 7 */ - } Bits; - struct { - byte grpWOMS :8; - } MergedBits; -} WOMSSTR; -extern volatile WOMSSTR _WOMS @(REG_BASE + 0x0000024E); -#define WOMS _WOMS.Byte -#define WOMS_WOMS0 _WOMS.Bits.WOMS0 -#define WOMS_WOMS1 _WOMS.Bits.WOMS1 -#define WOMS_WOMS2 _WOMS.Bits.WOMS2 -#define WOMS_WOMS3 _WOMS.Bits.WOMS3 -#define WOMS_WOMS4 _WOMS.Bits.WOMS4 -#define WOMS_WOMS5 _WOMS.Bits.WOMS5 -#define WOMS_WOMS6 _WOMS.Bits.WOMS6 -#define WOMS_WOMS7 _WOMS.Bits.WOMS7 -#define WOMS_WOMS _WOMS.MergedBits.grpWOMS - - -/*** PTM - Port M I/O Register; 0x00000250 ***/ -typedef union { - byte Byte; - struct { - byte PTM0 :1; /* Port T Bit 0 */ - byte PTM1 :1; /* Port T Bit 1 */ - byte PTM2 :1; /* Port T Bit 2 */ - byte PTM3 :1; /* Port T Bit 3 */ - byte PTM4 :1; /* Port T Bit 4 */ - byte PTM5 :1; /* Port T Bit 5 */ - byte PTM6 :1; /* Port T Bit 6 */ - byte PTM7 :1; /* Port T Bit 7 */ - } Bits; - struct { - byte grpPTM :8; - } MergedBits; -} PTMSTR; -extern volatile PTMSTR _PTM @(REG_BASE + 0x00000250); -#define PTM _PTM.Byte -#define PTM_PTM0 _PTM.Bits.PTM0 -#define PTM_PTM1 _PTM.Bits.PTM1 -#define PTM_PTM2 _PTM.Bits.PTM2 -#define PTM_PTM3 _PTM.Bits.PTM3 -#define PTM_PTM4 _PTM.Bits.PTM4 -#define PTM_PTM5 _PTM.Bits.PTM5 -#define PTM_PTM6 _PTM.Bits.PTM6 -#define PTM_PTM7 _PTM.Bits.PTM7 -#define PTM_PTM _PTM.MergedBits.grpPTM - - -/*** PTIM - Port M Input; 0x00000251 ***/ -typedef union { - byte Byte; - struct { - byte PTIM0 :1; /* Port M Bit 0 */ - byte PTIM1 :1; /* Port M Bit 1 */ - byte PTIM2 :1; /* Port M Bit 2 */ - byte PTIM3 :1; /* Port M Bit 3 */ - byte PTIM4 :1; /* Port M Bit 4 */ - byte PTIM5 :1; /* Port M Bit 5 */ - byte PTIM6 :1; /* Port M Bit 6 */ - byte PTIM7 :1; /* Port M Bit 7 */ - } Bits; - struct { - byte grpPTIM :8; - } MergedBits; -} PTIMSTR; -extern volatile PTIMSTR _PTIM @(REG_BASE + 0x00000251); -#define PTIM _PTIM.Byte -#define PTIM_PTIM0 _PTIM.Bits.PTIM0 -#define PTIM_PTIM1 _PTIM.Bits.PTIM1 -#define PTIM_PTIM2 _PTIM.Bits.PTIM2 -#define PTIM_PTIM3 _PTIM.Bits.PTIM3 -#define PTIM_PTIM4 _PTIM.Bits.PTIM4 -#define PTIM_PTIM5 _PTIM.Bits.PTIM5 -#define PTIM_PTIM6 _PTIM.Bits.PTIM6 -#define PTIM_PTIM7 _PTIM.Bits.PTIM7 -#define PTIM_PTIM _PTIM.MergedBits.grpPTIM - - -/*** DDRM - Port M Data Direction Register; 0x00000252 ***/ -typedef union { - byte Byte; - struct { - byte DDRM0 :1; /* Data Direction Port M Bit 0 */ - byte DDRM1 :1; /* Data Direction Port M Bit 1 */ - byte DDRM2 :1; /* Data Direction Port M Bit 2 */ - byte DDRM3 :1; /* Data Direction Port M Bit 3 */ - byte DDRM4 :1; /* Data Direction Port M Bit 4 */ - byte DDRM5 :1; /* Data Direction Port M Bit 5 */ - byte DDRM6 :1; /* Data Direction Port M Bit 6 */ - byte DDRM7 :1; /* Data Direction Port M Bit 7 */ - } Bits; - struct { - byte grpDDRM :8; - } MergedBits; -} DDRMSTR; -extern volatile DDRMSTR _DDRM @(REG_BASE + 0x00000252); -#define DDRM _DDRM.Byte -#define DDRM_DDRM0 _DDRM.Bits.DDRM0 -#define DDRM_DDRM1 _DDRM.Bits.DDRM1 -#define DDRM_DDRM2 _DDRM.Bits.DDRM2 -#define DDRM_DDRM3 _DDRM.Bits.DDRM3 -#define DDRM_DDRM4 _DDRM.Bits.DDRM4 -#define DDRM_DDRM5 _DDRM.Bits.DDRM5 -#define DDRM_DDRM6 _DDRM.Bits.DDRM6 -#define DDRM_DDRM7 _DDRM.Bits.DDRM7 -#define DDRM_DDRM _DDRM.MergedBits.grpDDRM - - -/*** RDRM - Port M Reduced Drive Register; 0x00000253 ***/ -typedef union { - byte Byte; - struct { - byte RDRM0 :1; /* Reduced Drive Port M Bit 0 */ - byte RDRM1 :1; /* Reduced Drive Port M Bit 1 */ - byte RDRM2 :1; /* Reduced Drive Port M Bit 2 */ - byte RDRM3 :1; /* Reduced Drive Port M Bit 3 */ - byte RDRM4 :1; /* Reduced Drive Port M Bit 4 */ - byte RDRM5 :1; /* Reduced Drive Port M Bit 5 */ - byte RDRM6 :1; /* Reduced Drive Port M Bit 6 */ - byte RDRM7 :1; /* Reduced Drive Port M Bit 7 */ - } Bits; - struct { - byte grpRDRM :8; - } MergedBits; -} RDRMSTR; -extern volatile RDRMSTR _RDRM @(REG_BASE + 0x00000253); -#define RDRM _RDRM.Byte -#define RDRM_RDRM0 _RDRM.Bits.RDRM0 -#define RDRM_RDRM1 _RDRM.Bits.RDRM1 -#define RDRM_RDRM2 _RDRM.Bits.RDRM2 -#define RDRM_RDRM3 _RDRM.Bits.RDRM3 -#define RDRM_RDRM4 _RDRM.Bits.RDRM4 -#define RDRM_RDRM5 _RDRM.Bits.RDRM5 -#define RDRM_RDRM6 _RDRM.Bits.RDRM6 -#define RDRM_RDRM7 _RDRM.Bits.RDRM7 -#define RDRM_RDRM _RDRM.MergedBits.grpRDRM - - -/*** PERM - Port M Pull Device Enable Register; 0x00000254 ***/ -typedef union { - byte Byte; - struct { - byte PERM0 :1; /* Pull Device Enable Port M Bit 0 */ - byte PERM1 :1; /* Pull Device Enable Port M Bit 1 */ - byte PERM2 :1; /* Pull Device Enable Port M Bit 2 */ - byte PERM3 :1; /* Pull Device Enable Port M Bit 3 */ - byte PERM4 :1; /* Pull Device Enable Port M Bit 4 */ - byte PERM5 :1; /* Pull Device Enable Port M Bit 5 */ - byte PERM6 :1; /* Pull Device Enable Port M Bit 6 */ - byte PERM7 :1; /* Pull Device Enable Port M Bit 7 */ - } Bits; - struct { - byte grpPERM :8; - } MergedBits; -} PERMSTR; -extern volatile PERMSTR _PERM @(REG_BASE + 0x00000254); -#define PERM _PERM.Byte -#define PERM_PERM0 _PERM.Bits.PERM0 -#define PERM_PERM1 _PERM.Bits.PERM1 -#define PERM_PERM2 _PERM.Bits.PERM2 -#define PERM_PERM3 _PERM.Bits.PERM3 -#define PERM_PERM4 _PERM.Bits.PERM4 -#define PERM_PERM5 _PERM.Bits.PERM5 -#define PERM_PERM6 _PERM.Bits.PERM6 -#define PERM_PERM7 _PERM.Bits.PERM7 -#define PERM_PERM _PERM.MergedBits.grpPERM - - -/*** PPSM - Port M Polarity Select Register; 0x00000255 ***/ -typedef union { - byte Byte; - struct { - byte PPSM0 :1; /* Pull Select Port M Bit 0 */ - byte PPSM1 :1; /* Pull Select Port M Bit 1 */ - byte PPSM2 :1; /* Pull Select Port M Bit 2 */ - byte PPSM3 :1; /* Pull Select Port M Bit 3 */ - byte PPSM4 :1; /* Pull Select Port M Bit 4 */ - byte PPSM5 :1; /* Pull Select Port M Bit 5 */ - byte PPSM6 :1; /* Pull Select Port M Bit 6 */ - byte PPSM7 :1; /* Pull Select Port M Bit 7 */ - } Bits; - struct { - byte grpPPSM :8; - } MergedBits; -} PPSMSTR; -extern volatile PPSMSTR _PPSM @(REG_BASE + 0x00000255); -#define PPSM _PPSM.Byte -#define PPSM_PPSM0 _PPSM.Bits.PPSM0 -#define PPSM_PPSM1 _PPSM.Bits.PPSM1 -#define PPSM_PPSM2 _PPSM.Bits.PPSM2 -#define PPSM_PPSM3 _PPSM.Bits.PPSM3 -#define PPSM_PPSM4 _PPSM.Bits.PPSM4 -#define PPSM_PPSM5 _PPSM.Bits.PPSM5 -#define PPSM_PPSM6 _PPSM.Bits.PPSM6 -#define PPSM_PPSM7 _PPSM.Bits.PPSM7 -#define PPSM_PPSM _PPSM.MergedBits.grpPPSM - - -/*** WOMM - Port M Wired-Or Mode Register; 0x00000256 ***/ -typedef union { - byte Byte; - struct { - byte WOMM0 :1; /* Wired-Or Mode Port M Bit 0 */ - byte WOMM1 :1; /* Wired-Or Mode Port M Bit 1 */ - byte WOMM2 :1; /* Wired-Or Mode Port M Bit 2 */ - byte WOMM3 :1; /* Wired-Or Mode Port M Bit 3 */ - byte WOMM4 :1; /* Wired-Or Mode Port M Bit 4 */ - byte WOMM5 :1; /* Wired-Or Mode Port M Bit 5 */ - byte WOMM6 :1; /* Wired-Or Mode Port M Bit 6 */ - byte WOMM7 :1; /* Wired-Or Mode Port M Bit 7 */ - } Bits; - struct { - byte grpWOMM :8; - } MergedBits; -} WOMMSTR; -extern volatile WOMMSTR _WOMM @(REG_BASE + 0x00000256); -#define WOMM _WOMM.Byte -#define WOMM_WOMM0 _WOMM.Bits.WOMM0 -#define WOMM_WOMM1 _WOMM.Bits.WOMM1 -#define WOMM_WOMM2 _WOMM.Bits.WOMM2 -#define WOMM_WOMM3 _WOMM.Bits.WOMM3 -#define WOMM_WOMM4 _WOMM.Bits.WOMM4 -#define WOMM_WOMM5 _WOMM.Bits.WOMM5 -#define WOMM_WOMM6 _WOMM.Bits.WOMM6 -#define WOMM_WOMM7 _WOMM.Bits.WOMM7 -#define WOMM_WOMM _WOMM.MergedBits.grpWOMM - - -/*** MODRR - Module Routing Register; 0x00000257 ***/ -typedef union { - byte Byte; - struct { - byte MODRR0 :1; /* CAN0 Routing */ - byte MODRR1 :1; /* CAN0 Routing */ - byte MODRR2 :1; /* CAN4 Routing */ - byte MODRR3 :1; /* CAN4 Routing */ - byte MODRR4 :1; /* SPI0 Routing */ - byte MODRR5 :1; /* SPI1 Routing */ - byte MODRR6 :1; /* SPI2 Routing */ - byte :1; - } Bits; - struct { - byte grpMODRR :7; - byte :1; - } MergedBits; -} MODRRSTR; -extern volatile MODRRSTR _MODRR @(REG_BASE + 0x00000257); -#define MODRR _MODRR.Byte -#define MODRR_MODRR0 _MODRR.Bits.MODRR0 -#define MODRR_MODRR1 _MODRR.Bits.MODRR1 -#define MODRR_MODRR2 _MODRR.Bits.MODRR2 -#define MODRR_MODRR3 _MODRR.Bits.MODRR3 -#define MODRR_MODRR4 _MODRR.Bits.MODRR4 -#define MODRR_MODRR5 _MODRR.Bits.MODRR5 -#define MODRR_MODRR6 _MODRR.Bits.MODRR6 -#define MODRR_MODRR _MODRR.MergedBits.grpMODRR - - -/*** PTP - Port P I/O Register; 0x00000258 ***/ -typedef union { - byte Byte; - struct { - byte PTP0 :1; /* Port P Bit 0 */ - byte PTP1 :1; /* Port P Bit 1 */ - byte PTP2 :1; /* Port P Bit 2 */ - byte PTP3 :1; /* Port P Bit 3 */ - byte PTP4 :1; /* Port P Bit 4 */ - byte PTP5 :1; /* Port P Bit 5 */ - byte PTP6 :1; /* Port P Bit 6 */ - byte PTP7 :1; /* Port P Bit 7 */ - } Bits; - struct { - byte grpPTP :8; - } MergedBits; -} PTPSTR; -extern volatile PTPSTR _PTP @(REG_BASE + 0x00000258); -#define PTP _PTP.Byte -#define PTP_PTP0 _PTP.Bits.PTP0 -#define PTP_PTP1 _PTP.Bits.PTP1 -#define PTP_PTP2 _PTP.Bits.PTP2 -#define PTP_PTP3 _PTP.Bits.PTP3 -#define PTP_PTP4 _PTP.Bits.PTP4 -#define PTP_PTP5 _PTP.Bits.PTP5 -#define PTP_PTP6 _PTP.Bits.PTP6 -#define PTP_PTP7 _PTP.Bits.PTP7 -#define PTP_PTP _PTP.MergedBits.grpPTP - - -/*** PTIP - Port P Input; 0x00000259 ***/ -typedef union { - byte Byte; - struct { - byte PTIP0 :1; /* Port P Bit 0 */ - byte PTIP1 :1; /* Port P Bit 1 */ - byte PTIP2 :1; /* Port P Bit 2 */ - byte PTIP3 :1; /* Port P Bit 3 */ - byte PTIP4 :1; /* Port P Bit 4 */ - byte PTIP5 :1; /* Port P Bit 5 */ - byte PTIP6 :1; /* Port P Bit 6 */ - byte PTIP7 :1; /* Port P Bit 7 */ - } Bits; - struct { - byte grpPTIP :8; - } MergedBits; -} PTIPSTR; -extern volatile PTIPSTR _PTIP @(REG_BASE + 0x00000259); -#define PTIP _PTIP.Byte -#define PTIP_PTIP0 _PTIP.Bits.PTIP0 -#define PTIP_PTIP1 _PTIP.Bits.PTIP1 -#define PTIP_PTIP2 _PTIP.Bits.PTIP2 -#define PTIP_PTIP3 _PTIP.Bits.PTIP3 -#define PTIP_PTIP4 _PTIP.Bits.PTIP4 -#define PTIP_PTIP5 _PTIP.Bits.PTIP5 -#define PTIP_PTIP6 _PTIP.Bits.PTIP6 -#define PTIP_PTIP7 _PTIP.Bits.PTIP7 -#define PTIP_PTIP _PTIP.MergedBits.grpPTIP - - -/*** DDRP - Port P Data Direction Register; 0x0000025A ***/ -typedef union { - byte Byte; - struct { - byte DDRP0 :1; /* Data Direction Port P Bit 0 */ - byte DDRP1 :1; /* Data Direction Port P Bit 1 */ - byte DDRP2 :1; /* Data Direction Port P Bit 2 */ - byte DDRP3 :1; /* Data Direction Port P Bit 3 */ - byte DDRP4 :1; /* Data Direction Port P Bit 4 */ - byte DDRP5 :1; /* Data Direction Port P Bit 5 */ - byte DDRP6 :1; /* Data Direction Port P Bit 6 */ - byte DDRP7 :1; /* Data Direction Port P Bit 7 */ - } Bits; - struct { - byte grpDDRP :8; - } MergedBits; -} DDRPSTR; -extern volatile DDRPSTR _DDRP @(REG_BASE + 0x0000025A); -#define DDRP _DDRP.Byte -#define DDRP_DDRP0 _DDRP.Bits.DDRP0 -#define DDRP_DDRP1 _DDRP.Bits.DDRP1 -#define DDRP_DDRP2 _DDRP.Bits.DDRP2 -#define DDRP_DDRP3 _DDRP.Bits.DDRP3 -#define DDRP_DDRP4 _DDRP.Bits.DDRP4 -#define DDRP_DDRP5 _DDRP.Bits.DDRP5 -#define DDRP_DDRP6 _DDRP.Bits.DDRP6 -#define DDRP_DDRP7 _DDRP.Bits.DDRP7 -#define DDRP_DDRP _DDRP.MergedBits.grpDDRP - - -/*** RDRP - Port P Reduced Drive Register; 0x0000025B ***/ -typedef union { - byte Byte; - struct { - byte RDRP0 :1; /* Reduced Drive Port P Bit 0 */ - byte RDRP1 :1; /* Reduced Drive Port P Bit 1 */ - byte RDRP2 :1; /* Reduced Drive Port P Bit 2 */ - byte RDRP3 :1; /* Reduced Drive Port P Bit 3 */ - byte RDRP4 :1; /* Reduced Drive Port P Bit 4 */ - byte RDRP5 :1; /* Reduced Drive Port P Bit 5 */ - byte RDRP6 :1; /* Reduced Drive Port P Bit 6 */ - byte RDRP7 :1; /* Reduced Drive Port P Bit 7 */ - } Bits; - struct { - byte grpRDRP :8; - } MergedBits; -} RDRPSTR; -extern volatile RDRPSTR _RDRP @(REG_BASE + 0x0000025B); -#define RDRP _RDRP.Byte -#define RDRP_RDRP0 _RDRP.Bits.RDRP0 -#define RDRP_RDRP1 _RDRP.Bits.RDRP1 -#define RDRP_RDRP2 _RDRP.Bits.RDRP2 -#define RDRP_RDRP3 _RDRP.Bits.RDRP3 -#define RDRP_RDRP4 _RDRP.Bits.RDRP4 -#define RDRP_RDRP5 _RDRP.Bits.RDRP5 -#define RDRP_RDRP6 _RDRP.Bits.RDRP6 -#define RDRP_RDRP7 _RDRP.Bits.RDRP7 -#define RDRP_RDRP _RDRP.MergedBits.grpRDRP - - -/*** PERP - Port P Pull Device Enable Register; 0x0000025C ***/ -typedef union { - byte Byte; - struct { - byte PERP0 :1; /* Pull Device Enable Port P Bit 0 */ - byte PERP1 :1; /* Pull Device Enable Port P Bit 1 */ - byte PERP2 :1; /* Pull Device Enable Port P Bit 2 */ - byte PERP3 :1; /* Pull Device Enable Port P Bit 3 */ - byte PERP4 :1; /* Pull Device Enable Port P Bit 4 */ - byte PERP5 :1; /* Pull Device Enable Port P Bit 5 */ - byte PERP6 :1; /* Pull Device Enable Port P Bit 6 */ - byte PERP7 :1; /* Pull Device Enable Port P Bit 7 */ - } Bits; - struct { - byte grpPERP :8; - } MergedBits; -} PERPSTR; -extern volatile PERPSTR _PERP @(REG_BASE + 0x0000025C); -#define PERP _PERP.Byte -#define PERP_PERP0 _PERP.Bits.PERP0 -#define PERP_PERP1 _PERP.Bits.PERP1 -#define PERP_PERP2 _PERP.Bits.PERP2 -#define PERP_PERP3 _PERP.Bits.PERP3 -#define PERP_PERP4 _PERP.Bits.PERP4 -#define PERP_PERP5 _PERP.Bits.PERP5 -#define PERP_PERP6 _PERP.Bits.PERP6 -#define PERP_PERP7 _PERP.Bits.PERP7 -#define PERP_PERP _PERP.MergedBits.grpPERP - - -/*** PPSP - Port P Polarity Select Register; 0x0000025D ***/ -typedef union { - byte Byte; - struct { - byte PPSP0 :1; /* Pull Select Port P Bit 0 */ - byte PPSP1 :1; /* Pull Select Port P Bit 1 */ - byte PPSP2 :1; /* Pull Select Port P Bit 2 */ - byte PPSP3 :1; /* Pull Select Port P Bit 3 */ - byte PPSP4 :1; /* Pull Select Port P Bit 4 */ - byte PPSP5 :1; /* Pull Select Port P Bit 5 */ - byte PPSP6 :1; /* Pull Select Port P Bit 6 */ - byte PPSP7 :1; /* Pull Select Port P Bit 7 */ - } Bits; - struct { - byte grpPPSP :8; - } MergedBits; -} PPSPSTR; -extern volatile PPSPSTR _PPSP @(REG_BASE + 0x0000025D); -#define PPSP _PPSP.Byte -#define PPSP_PPSP0 _PPSP.Bits.PPSP0 -#define PPSP_PPSP1 _PPSP.Bits.PPSP1 -#define PPSP_PPSP2 _PPSP.Bits.PPSP2 -#define PPSP_PPSP3 _PPSP.Bits.PPSP3 -#define PPSP_PPSP4 _PPSP.Bits.PPSP4 -#define PPSP_PPSP5 _PPSP.Bits.PPSP5 -#define PPSP_PPSP6 _PPSP.Bits.PPSP6 -#define PPSP_PPSP7 _PPSP.Bits.PPSP7 -#define PPSP_PPSP _PPSP.MergedBits.grpPPSP - - -/*** PIEP - Port P Interrupt Enable Register; 0x0000025E ***/ -typedef union { - byte Byte; - struct { - byte PIEP0 :1; /* Interrupt Enable Port P Bit 0 */ - byte PIEP1 :1; /* Interrupt Enable Port P Bit 1 */ - byte PIEP2 :1; /* Interrupt Enable Port P Bit 2 */ - byte PIEP3 :1; /* Interrupt Enable Port P Bit 3 */ - byte PIEP4 :1; /* Interrupt Enable Port P Bit 4 */ - byte PIEP5 :1; /* Interrupt Enable Port P Bit 5 */ - byte PIEP6 :1; /* Interrupt Enable Port P Bit 6 */ - byte PIEP7 :1; /* Interrupt Enable Port P Bit 7 */ - } Bits; - struct { - byte grpPIEP :8; - } MergedBits; -} PIEPSTR; -extern volatile PIEPSTR _PIEP @(REG_BASE + 0x0000025E); -#define PIEP _PIEP.Byte -#define PIEP_PIEP0 _PIEP.Bits.PIEP0 -#define PIEP_PIEP1 _PIEP.Bits.PIEP1 -#define PIEP_PIEP2 _PIEP.Bits.PIEP2 -#define PIEP_PIEP3 _PIEP.Bits.PIEP3 -#define PIEP_PIEP4 _PIEP.Bits.PIEP4 -#define PIEP_PIEP5 _PIEP.Bits.PIEP5 -#define PIEP_PIEP6 _PIEP.Bits.PIEP6 -#define PIEP_PIEP7 _PIEP.Bits.PIEP7 -#define PIEP_PIEP _PIEP.MergedBits.grpPIEP - - -/*** PIFP - Port P Interrupt Flag Register; 0x0000025F ***/ -typedef union { - byte Byte; - struct { - byte PIFP0 :1; /* Interrupt Flags Port P Bit 0 */ - byte PIFP1 :1; /* Interrupt Flags Port P Bit 1 */ - byte PIFP2 :1; /* Interrupt Flags Port P Bit 2 */ - byte PIFP3 :1; /* Interrupt Flags Port P Bit 3 */ - byte PIFP4 :1; /* Interrupt Flags Port P Bit 4 */ - byte PIFP5 :1; /* Interrupt Flags Port P Bit 5 */ - byte PIFP6 :1; /* Interrupt Flags Port P Bit 6 */ - byte PIFP7 :1; /* Interrupt Flags Port P Bit 7 */ - } Bits; - struct { - byte grpPIFP :8; - } MergedBits; -} PIFPSTR; -extern volatile PIFPSTR _PIFP @(REG_BASE + 0x0000025F); -#define PIFP _PIFP.Byte -#define PIFP_PIFP0 _PIFP.Bits.PIFP0 -#define PIFP_PIFP1 _PIFP.Bits.PIFP1 -#define PIFP_PIFP2 _PIFP.Bits.PIFP2 -#define PIFP_PIFP3 _PIFP.Bits.PIFP3 -#define PIFP_PIFP4 _PIFP.Bits.PIFP4 -#define PIFP_PIFP5 _PIFP.Bits.PIFP5 -#define PIFP_PIFP6 _PIFP.Bits.PIFP6 -#define PIFP_PIFP7 _PIFP.Bits.PIFP7 -#define PIFP_PIFP _PIFP.MergedBits.grpPIFP - - -/*** PTH - Port H I/O Register; 0x00000260 ***/ -typedef union { - byte Byte; - struct { - byte PTH0 :1; /* Port H Bit 0 */ - byte PTH1 :1; /* Port H Bit 1 */ - byte PTH2 :1; /* Port H Bit 2 */ - byte PTH3 :1; /* Port H Bit 3 */ - byte PTH4 :1; /* Port H Bit 4 */ - byte PTH5 :1; /* Port H Bit 5 */ - byte PTH6 :1; /* Port H Bit 6 */ - byte PTH7 :1; /* Port H Bit 7 */ - } Bits; - struct { - byte grpPTH :8; - } MergedBits; -} PTHSTR; -extern volatile PTHSTR _PTH @(REG_BASE + 0x00000260); -#define PTH _PTH.Byte -#define PTH_PTH0 _PTH.Bits.PTH0 -#define PTH_PTH1 _PTH.Bits.PTH1 -#define PTH_PTH2 _PTH.Bits.PTH2 -#define PTH_PTH3 _PTH.Bits.PTH3 -#define PTH_PTH4 _PTH.Bits.PTH4 -#define PTH_PTH5 _PTH.Bits.PTH5 -#define PTH_PTH6 _PTH.Bits.PTH6 -#define PTH_PTH7 _PTH.Bits.PTH7 -#define PTH_PTH _PTH.MergedBits.grpPTH - - -/*** PTIH - Port H Input Register; 0x00000261 ***/ -typedef union { - byte Byte; - struct { - byte PTIH0 :1; /* Port H Bit 0 */ - byte PTIH1 :1; /* Port H Bit 1 */ - byte PTIH2 :1; /* Port H Bit 2 */ - byte PTIH3 :1; /* Port H Bit 3 */ - byte PTIH4 :1; /* Port H Bit 4 */ - byte PTIH5 :1; /* Port H Bit 5 */ - byte PTIH6 :1; /* Port H Bit 6 */ - byte PTIH7 :1; /* Port H Bit 7 */ - } Bits; - struct { - byte grpPTIH :8; - } MergedBits; -} PTIHSTR; -extern volatile PTIHSTR _PTIH @(REG_BASE + 0x00000261); -#define PTIH _PTIH.Byte -#define PTIH_PTIH0 _PTIH.Bits.PTIH0 -#define PTIH_PTIH1 _PTIH.Bits.PTIH1 -#define PTIH_PTIH2 _PTIH.Bits.PTIH2 -#define PTIH_PTIH3 _PTIH.Bits.PTIH3 -#define PTIH_PTIH4 _PTIH.Bits.PTIH4 -#define PTIH_PTIH5 _PTIH.Bits.PTIH5 -#define PTIH_PTIH6 _PTIH.Bits.PTIH6 -#define PTIH_PTIH7 _PTIH.Bits.PTIH7 -#define PTIH_PTIH _PTIH.MergedBits.grpPTIH - - -/*** DDRH - Port H Data Direction Register; 0x00000262 ***/ -typedef union { - byte Byte; - struct { - byte DDRH0 :1; /* Data Direction Port H Bit 0 */ - byte DDRH1 :1; /* Data Direction Port H Bit 1 */ - byte DDRH2 :1; /* Data Direction Port H Bit 2 */ - byte DDRH3 :1; /* Data Direction Port H Bit 3 */ - byte DDRH4 :1; /* Data Direction Port H Bit 4 */ - byte DDRH5 :1; /* Data Direction Port H Bit 5 */ - byte DDRH6 :1; /* Data Direction Port H Bit 6 */ - byte DDRH7 :1; /* Data Direction Port H Bit 7 */ - } Bits; - struct { - byte grpDDRH :8; - } MergedBits; -} DDRHSTR; -extern volatile DDRHSTR _DDRH @(REG_BASE + 0x00000262); -#define DDRH _DDRH.Byte -#define DDRH_DDRH0 _DDRH.Bits.DDRH0 -#define DDRH_DDRH1 _DDRH.Bits.DDRH1 -#define DDRH_DDRH2 _DDRH.Bits.DDRH2 -#define DDRH_DDRH3 _DDRH.Bits.DDRH3 -#define DDRH_DDRH4 _DDRH.Bits.DDRH4 -#define DDRH_DDRH5 _DDRH.Bits.DDRH5 -#define DDRH_DDRH6 _DDRH.Bits.DDRH6 -#define DDRH_DDRH7 _DDRH.Bits.DDRH7 -#define DDRH_DDRH _DDRH.MergedBits.grpDDRH - - -/*** RDRH - Port H Reduced Drive Register; 0x00000263 ***/ -typedef union { - byte Byte; - struct { - byte RDRH0 :1; /* Reduced Drive Port H Bit 0 */ - byte RDRH1 :1; /* Reduced Drive Port H Bit 1 */ - byte RDRH2 :1; /* Reduced Drive Port H Bit 2 */ - byte RDRH3 :1; /* Reduced Drive Port H Bit 3 */ - byte RDRH4 :1; /* Reduced Drive Port H Bit 4 */ - byte RDRH5 :1; /* Reduced Drive Port H Bit 5 */ - byte RDRH6 :1; /* Reduced Drive Port H Bit 6 */ - byte RDRH7 :1; /* Reduced Drive Port H Bit 7 */ - } Bits; - struct { - byte grpRDRH :8; - } MergedBits; -} RDRHSTR; -extern volatile RDRHSTR _RDRH @(REG_BASE + 0x00000263); -#define RDRH _RDRH.Byte -#define RDRH_RDRH0 _RDRH.Bits.RDRH0 -#define RDRH_RDRH1 _RDRH.Bits.RDRH1 -#define RDRH_RDRH2 _RDRH.Bits.RDRH2 -#define RDRH_RDRH3 _RDRH.Bits.RDRH3 -#define RDRH_RDRH4 _RDRH.Bits.RDRH4 -#define RDRH_RDRH5 _RDRH.Bits.RDRH5 -#define RDRH_RDRH6 _RDRH.Bits.RDRH6 -#define RDRH_RDRH7 _RDRH.Bits.RDRH7 -#define RDRH_RDRH _RDRH.MergedBits.grpRDRH - - -/*** PERH - Port H Pull Device Enable Register; 0x00000264 ***/ -typedef union { - byte Byte; - struct { - byte PERH0 :1; /* Pull Device Enable Port H Bit 0 */ - byte PERH1 :1; /* Pull Device Enable Port H Bit 1 */ - byte PERH2 :1; /* Pull Device Enable Port H Bit 2 */ - byte PERH3 :1; /* Pull Device Enable Port H Bit 3 */ - byte PERH4 :1; /* Pull Device Enable Port H Bit 4 */ - byte PERH5 :1; /* Pull Device Enable Port H Bit 5 */ - byte PERH6 :1; /* Pull Device Enable Port H Bit 6 */ - byte PERH7 :1; /* Pull Device Enable Port H Bit 7 */ - } Bits; - struct { - byte grpPERH :8; - } MergedBits; -} PERHSTR; -extern volatile PERHSTR _PERH @(REG_BASE + 0x00000264); -#define PERH _PERH.Byte -#define PERH_PERH0 _PERH.Bits.PERH0 -#define PERH_PERH1 _PERH.Bits.PERH1 -#define PERH_PERH2 _PERH.Bits.PERH2 -#define PERH_PERH3 _PERH.Bits.PERH3 -#define PERH_PERH4 _PERH.Bits.PERH4 -#define PERH_PERH5 _PERH.Bits.PERH5 -#define PERH_PERH6 _PERH.Bits.PERH6 -#define PERH_PERH7 _PERH.Bits.PERH7 -#define PERH_PERH _PERH.MergedBits.grpPERH - - -/*** PPSH - Port H Polarity Select Register; 0x00000265 ***/ -typedef union { - byte Byte; - struct { - byte PPSH0 :1; /* Pull Select Port H Bit 0 */ - byte PPSH1 :1; /* Pull Select Port H Bit 1 */ - byte PPSH2 :1; /* Pull Select Port H Bit 2 */ - byte PPSH3 :1; /* Pull Select Port H Bit 3 */ - byte PPSH4 :1; /* Pull Select Port H Bit 4 */ - byte PPSH5 :1; /* Pull Select Port H Bit 5 */ - byte PPSH6 :1; /* Pull Select Port H Bit 6 */ - byte PPSH7 :1; /* Pull Select Port H Bit 7 */ - } Bits; - struct { - byte grpPPSH :8; - } MergedBits; -} PPSHSTR; -extern volatile PPSHSTR _PPSH @(REG_BASE + 0x00000265); -#define PPSH _PPSH.Byte -#define PPSH_PPSH0 _PPSH.Bits.PPSH0 -#define PPSH_PPSH1 _PPSH.Bits.PPSH1 -#define PPSH_PPSH2 _PPSH.Bits.PPSH2 -#define PPSH_PPSH3 _PPSH.Bits.PPSH3 -#define PPSH_PPSH4 _PPSH.Bits.PPSH4 -#define PPSH_PPSH5 _PPSH.Bits.PPSH5 -#define PPSH_PPSH6 _PPSH.Bits.PPSH6 -#define PPSH_PPSH7 _PPSH.Bits.PPSH7 -#define PPSH_PPSH _PPSH.MergedBits.grpPPSH - - -/*** PIEH - Port H Interrupt Enable Register; 0x00000266 ***/ -typedef union { - byte Byte; - struct { - byte PIEH0 :1; /* Interrupt Enable Port H Bit 0 */ - byte PIEH1 :1; /* Interrupt Enable Port H Bit 1 */ - byte PIEH2 :1; /* Interrupt Enable Port H Bit 2 */ - byte PIEH3 :1; /* Interrupt Enable Port H Bit 3 */ - byte PIEH4 :1; /* Interrupt Enable Port H Bit 4 */ - byte PIEH5 :1; /* Interrupt Enable Port H Bit 5 */ - byte PIEH6 :1; /* Interrupt Enable Port H Bit 6 */ - byte PIEH7 :1; /* Interrupt Enable Port H Bit 7 */ - } Bits; - struct { - byte grpPIEH :8; - } MergedBits; -} PIEHSTR; -extern volatile PIEHSTR _PIEH @(REG_BASE + 0x00000266); -#define PIEH _PIEH.Byte -#define PIEH_PIEH0 _PIEH.Bits.PIEH0 -#define PIEH_PIEH1 _PIEH.Bits.PIEH1 -#define PIEH_PIEH2 _PIEH.Bits.PIEH2 -#define PIEH_PIEH3 _PIEH.Bits.PIEH3 -#define PIEH_PIEH4 _PIEH.Bits.PIEH4 -#define PIEH_PIEH5 _PIEH.Bits.PIEH5 -#define PIEH_PIEH6 _PIEH.Bits.PIEH6 -#define PIEH_PIEH7 _PIEH.Bits.PIEH7 -#define PIEH_PIEH _PIEH.MergedBits.grpPIEH - - -/*** PIFH - Port H Interrupt Flag Register; 0x00000267 ***/ -typedef union { - byte Byte; - struct { - byte PIFH0 :1; /* Interrupt Flags Port H Bit 0 */ - byte PIFH1 :1; /* Interrupt Flags Port H Bit 1 */ - byte PIFH2 :1; /* Interrupt Flags Port H Bit 2 */ - byte PIFH3 :1; /* Interrupt Flags Port H Bit 3 */ - byte PIFH4 :1; /* Interrupt Flags Port H Bit 4 */ - byte PIFH5 :1; /* Interrupt Flags Port H Bit 5 */ - byte PIFH6 :1; /* Interrupt Flags Port H Bit 6 */ - byte PIFH7 :1; /* Interrupt Flags Port H Bit 7 */ - } Bits; - struct { - byte grpPIFH :8; - } MergedBits; -} PIFHSTR; -extern volatile PIFHSTR _PIFH @(REG_BASE + 0x00000267); -#define PIFH _PIFH.Byte -#define PIFH_PIFH0 _PIFH.Bits.PIFH0 -#define PIFH_PIFH1 _PIFH.Bits.PIFH1 -#define PIFH_PIFH2 _PIFH.Bits.PIFH2 -#define PIFH_PIFH3 _PIFH.Bits.PIFH3 -#define PIFH_PIFH4 _PIFH.Bits.PIFH4 -#define PIFH_PIFH5 _PIFH.Bits.PIFH5 -#define PIFH_PIFH6 _PIFH.Bits.PIFH6 -#define PIFH_PIFH7 _PIFH.Bits.PIFH7 -#define PIFH_PIFH _PIFH.MergedBits.grpPIFH - - -/*** PTJ - Port J I/O Register; 0x00000268 ***/ -typedef union { - byte Byte; - struct { - byte PTJ0 :1; /* Port J Bit 0 */ - byte PTJ1 :1; /* Port J Bit 1 */ - byte :1; - byte :1; - byte :1; - byte :1; - byte PTJ6 :1; /* Port J Bit 6 */ - byte PTJ7 :1; /* Port J Bit 7 */ - } Bits; - struct { - byte grpPTJ :2; - byte :1; - byte :1; - byte :1; - byte :1; - byte grpPTJ_6 :2; - } MergedBits; -} PTJSTR; -extern volatile PTJSTR _PTJ @(REG_BASE + 0x00000268); -#define PTJ _PTJ.Byte -#define PTJ_PTJ0 _PTJ.Bits.PTJ0 -#define PTJ_PTJ1 _PTJ.Bits.PTJ1 -#define PTJ_PTJ6 _PTJ.Bits.PTJ6 -#define PTJ_PTJ7 _PTJ.Bits.PTJ7 -#define PTJ_PTJ _PTJ.MergedBits.grpPTJ -#define PTJ_PTJ_6 _PTJ.MergedBits.grpPTJ_6 - - -/*** PTIJ - Port J Input Register; 0x00000269 ***/ -typedef union { - byte Byte; - struct { - byte PTIJ0 :1; /* Port J Bit 0 */ - byte PTIJ1 :1; /* Port J Bit 1 */ - byte :1; - byte :1; - byte :1; - byte :1; - byte PTIJ6 :1; /* Port J Bit 6 */ - byte PTIJ7 :1; /* Port J Bit 7 */ - } Bits; - struct { - byte grpPTIJ :2; - byte :1; - byte :1; - byte :1; - byte :1; - byte grpPTIJ_6 :2; - } MergedBits; -} PTIJSTR; -extern volatile PTIJSTR _PTIJ @(REG_BASE + 0x00000269); -#define PTIJ _PTIJ.Byte -#define PTIJ_PTIJ0 _PTIJ.Bits.PTIJ0 -#define PTIJ_PTIJ1 _PTIJ.Bits.PTIJ1 -#define PTIJ_PTIJ6 _PTIJ.Bits.PTIJ6 -#define PTIJ_PTIJ7 _PTIJ.Bits.PTIJ7 -#define PTIJ_PTIJ _PTIJ.MergedBits.grpPTIJ -#define PTIJ_PTIJ_6 _PTIJ.MergedBits.grpPTIJ_6 - - -/*** DDRJ - Port J Data Direction Register; 0x0000026A ***/ -typedef union { - byte Byte; - struct { - byte DDRJ0 :1; /* Data Direction Port J Bit 0 */ - byte DDRJ1 :1; /* Data Direction Port J Bit 1 */ - byte :1; - byte :1; - byte :1; - byte :1; - byte DDRJ6 :1; /* Data Direction Port J Bit 6 */ - byte DDRJ7 :1; /* Data Direction Port J Bit 7 */ - } Bits; - struct { - byte grpDDRJ :2; - byte :1; - byte :1; - byte :1; - byte :1; - byte grpDDRJ_6 :2; - } MergedBits; -} DDRJSTR; -extern volatile DDRJSTR _DDRJ @(REG_BASE + 0x0000026A); -#define DDRJ _DDRJ.Byte -#define DDRJ_DDRJ0 _DDRJ.Bits.DDRJ0 -#define DDRJ_DDRJ1 _DDRJ.Bits.DDRJ1 -#define DDRJ_DDRJ6 _DDRJ.Bits.DDRJ6 -#define DDRJ_DDRJ7 _DDRJ.Bits.DDRJ7 -#define DDRJ_DDRJ _DDRJ.MergedBits.grpDDRJ -#define DDRJ_DDRJ_6 _DDRJ.MergedBits.grpDDRJ_6 - - -/*** RDRJ - Port J Reduced Drive Register; 0x0000026B ***/ -typedef union { - byte Byte; - struct { - byte RDRJ0 :1; /* Reduced Drive Port J Bit 0 */ - byte RDRJ1 :1; /* Reduced Drive Port J Bit 1 */ - byte :1; - byte :1; - byte :1; - byte :1; - byte RDRJ6 :1; /* Reduced Drive Port J Bit 6 */ - byte RDRJ7 :1; /* Reduced Drive Port J Bit 7 */ - } Bits; - struct { - byte grpRDRJ :2; - byte :1; - byte :1; - byte :1; - byte :1; - byte grpRDRJ_6 :2; - } MergedBits; -} RDRJSTR; -extern volatile RDRJSTR _RDRJ @(REG_BASE + 0x0000026B); -#define RDRJ _RDRJ.Byte -#define RDRJ_RDRJ0 _RDRJ.Bits.RDRJ0 -#define RDRJ_RDRJ1 _RDRJ.Bits.RDRJ1 -#define RDRJ_RDRJ6 _RDRJ.Bits.RDRJ6 -#define RDRJ_RDRJ7 _RDRJ.Bits.RDRJ7 -#define RDRJ_RDRJ _RDRJ.MergedBits.grpRDRJ -#define RDRJ_RDRJ_6 _RDRJ.MergedBits.grpRDRJ_6 - - -/*** PERJ - Port J Pull Device Enable Register; 0x0000026C ***/ -typedef union { - byte Byte; - struct { - byte PERJ0 :1; /* Pull Device Enable Port J Bit 0 */ - byte PERJ1 :1; /* Pull Device Enable Port J Bit 1 */ - byte :1; - byte :1; - byte :1; - byte :1; - byte PERJ6 :1; /* Pull Device Enable Port J Bit 6 */ - byte PERJ7 :1; /* Pull Device Enable Port J Bit 7 */ - } Bits; - struct { - byte grpPERJ :2; - byte :1; - byte :1; - byte :1; - byte :1; - byte grpPERJ_6 :2; - } MergedBits; -} PERJSTR; -extern volatile PERJSTR _PERJ @(REG_BASE + 0x0000026C); -#define PERJ _PERJ.Byte -#define PERJ_PERJ0 _PERJ.Bits.PERJ0 -#define PERJ_PERJ1 _PERJ.Bits.PERJ1 -#define PERJ_PERJ6 _PERJ.Bits.PERJ6 -#define PERJ_PERJ7 _PERJ.Bits.PERJ7 -#define PERJ_PERJ _PERJ.MergedBits.grpPERJ -#define PERJ_PERJ_6 _PERJ.MergedBits.grpPERJ_6 - - -/*** PPSJ - PortJP Polarity Select Register; 0x0000026D ***/ -typedef union { - byte Byte; - struct { - byte PPSJ0 :1; /* Pull Select Port J Bit 0 */ - byte PPSJ1 :1; /* Pull Select Port J Bit 1 */ - byte :1; - byte :1; - byte :1; - byte :1; - byte PPSJ6 :1; /* Pull Select Port J Bit 6 */ - byte PPSJ7 :1; /* Pull Select Port J Bit 7 */ - } Bits; - struct { - byte grpPPSJ :2; - byte :1; - byte :1; - byte :1; - byte :1; - byte grpPPSJ_6 :2; - } MergedBits; -} PPSJSTR; -extern volatile PPSJSTR _PPSJ @(REG_BASE + 0x0000026D); -#define PPSJ _PPSJ.Byte -#define PPSJ_PPSJ0 _PPSJ.Bits.PPSJ0 -#define PPSJ_PPSJ1 _PPSJ.Bits.PPSJ1 -#define PPSJ_PPSJ6 _PPSJ.Bits.PPSJ6 -#define PPSJ_PPSJ7 _PPSJ.Bits.PPSJ7 -#define PPSJ_PPSJ _PPSJ.MergedBits.grpPPSJ -#define PPSJ_PPSJ_6 _PPSJ.MergedBits.grpPPSJ_6 - - -/*** PIEJ - Port J Interrupt Enable Register; 0x0000026E ***/ -typedef union { - byte Byte; - struct { - byte PIEJ0 :1; /* Interrupt Enable Port J Bit 0 */ - byte PIEJ1 :1; /* Interrupt Enable Port J Bit 1 */ - byte :1; - byte :1; - byte :1; - byte :1; - byte PIEJ6 :1; /* Interrupt Enable Port J Bit 6 */ - byte PIEJ7 :1; /* Interrupt Enable Port J Bit 7 */ - } Bits; - struct { - byte grpPIEJ :2; - byte :1; - byte :1; - byte :1; - byte :1; - byte grpPIEJ_6 :2; - } MergedBits; -} PIEJSTR; -extern volatile PIEJSTR _PIEJ @(REG_BASE + 0x0000026E); -#define PIEJ _PIEJ.Byte -#define PIEJ_PIEJ0 _PIEJ.Bits.PIEJ0 -#define PIEJ_PIEJ1 _PIEJ.Bits.PIEJ1 -#define PIEJ_PIEJ6 _PIEJ.Bits.PIEJ6 -#define PIEJ_PIEJ7 _PIEJ.Bits.PIEJ7 -#define PIEJ_PIEJ _PIEJ.MergedBits.grpPIEJ -#define PIEJ_PIEJ_6 _PIEJ.MergedBits.grpPIEJ_6 - - -/*** PIFJ - Port J Interrupt Flag Register; 0x0000026F ***/ -typedef union { - byte Byte; - struct { - byte PIFJ0 :1; /* Interrupt Flags Port J Bit 0 */ - byte PIFJ1 :1; /* Interrupt Flags Port J Bit 1 */ - byte :1; - byte :1; - byte :1; - byte :1; - byte PIFJ6 :1; /* Interrupt Flags Port J Bit 6 */ - byte PIFJ7 :1; /* Interrupt Flags Port J Bit 7 */ - } Bits; - struct { - byte grpPIFJ :2; - byte :1; - byte :1; - byte :1; - byte :1; - byte grpPIFJ_6 :2; - } MergedBits; -} PIFJSTR; -extern volatile PIFJSTR _PIFJ @(REG_BASE + 0x0000026F); -#define PIFJ _PIFJ.Byte -#define PIFJ_PIFJ0 _PIFJ.Bits.PIFJ0 -#define PIFJ_PIFJ1 _PIFJ.Bits.PIFJ1 -#define PIFJ_PIFJ6 _PIFJ.Bits.PIFJ6 -#define PIFJ_PIFJ7 _PIFJ.Bits.PIFJ7 -#define PIFJ_PIFJ _PIFJ.MergedBits.grpPIFJ -#define PIFJ_PIFJ_6 _PIFJ.MergedBits.grpPIFJ_6 - - -/*** CAN4CTL0 - MSCAN4 Control 0 Register; 0x00000280 ***/ -typedef union { - byte Byte; - struct { - byte INITRQ :1; /* Initialization Mode Request */ - byte SLPRQ :1; /* Sleep Mode Request */ - byte WUPE :1; /* Wake-Up Enable */ - byte TIME :1; /* Timer Enable */ - byte SYNCH :1; /* Synchronized Status */ - byte CSWAI :1; /* CAN Stops in Wait Mode */ - byte RXACT :1; /* Receiver Active Status */ - byte RXFRM :1; /* Received Frame Flag */ - } Bits; -} CAN4CTL0STR; -extern volatile CAN4CTL0STR _CAN4CTL0 @(REG_BASE + 0x00000280); -#define CAN4CTL0 _CAN4CTL0.Byte -#define CAN4CTL0_INITRQ _CAN4CTL0.Bits.INITRQ -#define CAN4CTL0_SLPRQ _CAN4CTL0.Bits.SLPRQ -#define CAN4CTL0_WUPE _CAN4CTL0.Bits.WUPE -#define CAN4CTL0_TIME _CAN4CTL0.Bits.TIME -#define CAN4CTL0_SYNCH _CAN4CTL0.Bits.SYNCH -#define CAN4CTL0_CSWAI _CAN4CTL0.Bits.CSWAI -#define CAN4CTL0_RXACT _CAN4CTL0.Bits.RXACT -#define CAN4CTL0_RXFRM _CAN4CTL0.Bits.RXFRM - - -/*** CAN4CTL1 - MSCAN4 Control 1 Register; 0x00000281 ***/ -typedef union { - byte Byte; - struct { - byte INITAK :1; /* Initialization Mode Acknowledge */ - byte SLPAK :1; /* Sleep Mode Acknowledge */ - byte WUPM :1; /* Wake-Up Mode */ - byte :1; - byte LISTEN :1; /* Listen Only Mode */ - byte LOOPB :1; /* Loop Back Self Test Mode */ - byte CLKSRC :1; /* MSCAN4 Clock Source */ - byte CANE :1; /* MSCAN4 Enable */ - } Bits; -} CAN4CTL1STR; -extern volatile CAN4CTL1STR _CAN4CTL1 @(REG_BASE + 0x00000281); -#define CAN4CTL1 _CAN4CTL1.Byte -#define CAN4CTL1_INITAK _CAN4CTL1.Bits.INITAK -#define CAN4CTL1_SLPAK _CAN4CTL1.Bits.SLPAK -#define CAN4CTL1_WUPM _CAN4CTL1.Bits.WUPM -#define CAN4CTL1_LISTEN _CAN4CTL1.Bits.LISTEN -#define CAN4CTL1_LOOPB _CAN4CTL1.Bits.LOOPB -#define CAN4CTL1_CLKSRC _CAN4CTL1.Bits.CLKSRC -#define CAN4CTL1_CANE _CAN4CTL1.Bits.CANE - - -/*** CAN4BTR0 - MSCAN4 Bus Timing Register 0; 0x00000282 ***/ -typedef union { - byte Byte; - struct { - byte BRP0 :1; /* Baud Rate Prescaler 0 */ - byte BRP1 :1; /* Baud Rate Prescaler 1 */ - byte BRP2 :1; /* Baud Rate Prescaler 2 */ - byte BRP3 :1; /* Baud Rate Prescaler 3 */ - byte BRP4 :1; /* Baud Rate Prescaler 4 */ - byte BRP5 :1; /* Baud Rate Prescaler 5 */ - byte SJW0 :1; /* Synchronization Jump Width 0 */ - byte SJW1 :1; /* Synchronization Jump Width 1 */ - } Bits; - struct { - byte grpBRP :6; - byte grpSJW :2; - } MergedBits; -} CAN4BTR0STR; -extern volatile CAN4BTR0STR _CAN4BTR0 @(REG_BASE + 0x00000282); -#define CAN4BTR0 _CAN4BTR0.Byte -#define CAN4BTR0_BRP0 _CAN4BTR0.Bits.BRP0 -#define CAN4BTR0_BRP1 _CAN4BTR0.Bits.BRP1 -#define CAN4BTR0_BRP2 _CAN4BTR0.Bits.BRP2 -#define CAN4BTR0_BRP3 _CAN4BTR0.Bits.BRP3 -#define CAN4BTR0_BRP4 _CAN4BTR0.Bits.BRP4 -#define CAN4BTR0_BRP5 _CAN4BTR0.Bits.BRP5 -#define CAN4BTR0_SJW0 _CAN4BTR0.Bits.SJW0 -#define CAN4BTR0_SJW1 _CAN4BTR0.Bits.SJW1 -#define CAN4BTR0_BRP _CAN4BTR0.MergedBits.grpBRP -#define CAN4BTR0_SJW _CAN4BTR0.MergedBits.grpSJW - - -/*** CAN4BTR1 - MSCAN4 Bus Timing Register 1; 0x00000283 ***/ -typedef union { - byte Byte; - struct { - byte TSEG10 :1; /* Time Segment 1 */ - byte TSEG11 :1; /* Time Segment 1 */ - byte TSEG12 :1; /* Time Segment 1 */ - byte TSEG13 :1; /* Time Segment 1 */ - byte TSEG20 :1; /* Time Segment 2 */ - byte TSEG21 :1; /* Time Segment 2 */ - byte TSEG22 :1; /* Time Segment 2 */ - byte SAMP :1; /* Sampling */ - } Bits; - struct { - byte grpTSEG_10 :4; - byte grpTSEG_20 :3; - byte :1; - } MergedBits; -} CAN4BTR1STR; -extern volatile CAN4BTR1STR _CAN4BTR1 @(REG_BASE + 0x00000283); -#define CAN4BTR1 _CAN4BTR1.Byte -#define CAN4BTR1_TSEG10 _CAN4BTR1.Bits.TSEG10 -#define CAN4BTR1_TSEG11 _CAN4BTR1.Bits.TSEG11 -#define CAN4BTR1_TSEG12 _CAN4BTR1.Bits.TSEG12 -#define CAN4BTR1_TSEG13 _CAN4BTR1.Bits.TSEG13 -#define CAN4BTR1_TSEG20 _CAN4BTR1.Bits.TSEG20 -#define CAN4BTR1_TSEG21 _CAN4BTR1.Bits.TSEG21 -#define CAN4BTR1_TSEG22 _CAN4BTR1.Bits.TSEG22 -#define CAN4BTR1_SAMP _CAN4BTR1.Bits.SAMP -#define CAN4BTR1_TSEG_10 _CAN4BTR1.MergedBits.grpTSEG_10 -#define CAN4BTR1_TSEG_20 _CAN4BTR1.MergedBits.grpTSEG_20 -#define CAN4BTR1_TSEG CAN4BTR1_TSEG_10 - - -/*** CAN4RFLG - MSCAN4 Receiver Flag Register; 0x00000284 ***/ -typedef union { - byte Byte; - struct { - byte RXF :1; /* Receive Buffer Full */ - byte OVRIF :1; /* Overrun Interrupt Flag */ - byte TSTAT0 :1; /* Transmitter Status Bit 0 */ - byte TSTAT1 :1; /* Transmitter Status Bit 1 */ - byte RSTAT0 :1; /* Receiver Status Bit 0 */ - byte RSTAT1 :1; /* Receiver Status Bit 1 */ - byte CSCIF :1; /* CAN Status Change Interrupt Flag */ - byte WUPIF :1; /* Wake-up Interrupt Flag */ - } Bits; - struct { - byte :1; - byte :1; - byte grpTSTAT :2; - byte grpRSTAT :2; - byte :1; - byte :1; - } MergedBits; -} CAN4RFLGSTR; -extern volatile CAN4RFLGSTR _CAN4RFLG @(REG_BASE + 0x00000284); -#define CAN4RFLG _CAN4RFLG.Byte -#define CAN4RFLG_RXF _CAN4RFLG.Bits.RXF -#define CAN4RFLG_OVRIF _CAN4RFLG.Bits.OVRIF -#define CAN4RFLG_TSTAT0 _CAN4RFLG.Bits.TSTAT0 -#define CAN4RFLG_TSTAT1 _CAN4RFLG.Bits.TSTAT1 -#define CAN4RFLG_RSTAT0 _CAN4RFLG.Bits.RSTAT0 -#define CAN4RFLG_RSTAT1 _CAN4RFLG.Bits.RSTAT1 -#define CAN4RFLG_CSCIF _CAN4RFLG.Bits.CSCIF -#define CAN4RFLG_WUPIF _CAN4RFLG.Bits.WUPIF -#define CAN4RFLG_TSTAT _CAN4RFLG.MergedBits.grpTSTAT -#define CAN4RFLG_RSTAT _CAN4RFLG.MergedBits.grpRSTAT - - -/*** CAN4RIER - MSCAN4 Receiver Interrupt Enable Register; 0x00000285 ***/ -typedef union { - byte Byte; - struct { - byte RXFIE :1; /* Receiver Full Interrupt Enable */ - byte OVRIE :1; /* Overrun Interrupt Enable */ - byte TSTATE0 :1; /* Transmitter Status Change Enable 0 */ - byte TSTATE1 :1; /* Transmitter Status Change Enable 1 */ - byte RSTATE0 :1; /* Receiver Status Change Enable 0 */ - byte RSTATE1 :1; /* Receiver Status Change Enable 1 */ - byte CSCIE :1; /* CAN Status Change Interrupt Enable */ - byte WUPIE :1; /* Wake-up Interrupt Enable */ - } Bits; - struct { - byte :1; - byte :1; - byte grpTSTATE :2; - byte grpRSTATE :2; - byte :1; - byte :1; - } MergedBits; -} CAN4RIERSTR; -extern volatile CAN4RIERSTR _CAN4RIER @(REG_BASE + 0x00000285); -#define CAN4RIER _CAN4RIER.Byte -#define CAN4RIER_RXFIE _CAN4RIER.Bits.RXFIE -#define CAN4RIER_OVRIE _CAN4RIER.Bits.OVRIE -#define CAN4RIER_TSTATE0 _CAN4RIER.Bits.TSTATE0 -#define CAN4RIER_TSTATE1 _CAN4RIER.Bits.TSTATE1 -#define CAN4RIER_RSTATE0 _CAN4RIER.Bits.RSTATE0 -#define CAN4RIER_RSTATE1 _CAN4RIER.Bits.RSTATE1 -#define CAN4RIER_CSCIE _CAN4RIER.Bits.CSCIE -#define CAN4RIER_WUPIE _CAN4RIER.Bits.WUPIE -#define CAN4RIER_TSTATE _CAN4RIER.MergedBits.grpTSTATE -#define CAN4RIER_RSTATE _CAN4RIER.MergedBits.grpRSTATE - - -/*** CAN4TFLG - MSCAN4 Transmitter Flag Register; 0x00000286 ***/ -typedef union { - byte Byte; - struct { - byte TXE0 :1; /* Transmitter Buffer Empty 0 */ - byte TXE1 :1; /* Transmitter Buffer Empty 1 */ - byte TXE2 :1; /* Transmitter Buffer Empty 2 */ - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpTXE :3; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} CAN4TFLGSTR; -extern volatile CAN4TFLGSTR _CAN4TFLG @(REG_BASE + 0x00000286); -#define CAN4TFLG _CAN4TFLG.Byte -#define CAN4TFLG_TXE0 _CAN4TFLG.Bits.TXE0 -#define CAN4TFLG_TXE1 _CAN4TFLG.Bits.TXE1 -#define CAN4TFLG_TXE2 _CAN4TFLG.Bits.TXE2 -#define CAN4TFLG_TXE _CAN4TFLG.MergedBits.grpTXE - - -/*** CAN4TIER - MSCAN4 Transmitter Interrupt Enable Register; 0x00000287 ***/ -typedef union { - byte Byte; - struct { - byte TXEIE0 :1; /* Transmitter Empty Interrupt Enable 0 */ - byte TXEIE1 :1; /* Transmitter Empty Interrupt Enable 1 */ - byte TXEIE2 :1; /* Transmitter Empty Interrupt Enable 2 */ - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpTXEIE :3; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} CAN4TIERSTR; -extern volatile CAN4TIERSTR _CAN4TIER @(REG_BASE + 0x00000287); -#define CAN4TIER _CAN4TIER.Byte -#define CAN4TIER_TXEIE0 _CAN4TIER.Bits.TXEIE0 -#define CAN4TIER_TXEIE1 _CAN4TIER.Bits.TXEIE1 -#define CAN4TIER_TXEIE2 _CAN4TIER.Bits.TXEIE2 -#define CAN4TIER_TXEIE _CAN4TIER.MergedBits.grpTXEIE - - -/*** CAN4TARQ - MSCAN 4 Transmitter Message Abort Request; 0x00000288 ***/ -typedef union { - byte Byte; - struct { - byte ABTRQ0 :1; /* Abort Request 0 */ - byte ABTRQ1 :1; /* Abort Request 1 */ - byte ABTRQ2 :1; /* Abort Request 2 */ - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpABTRQ :3; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} CAN4TARQSTR; -extern volatile CAN4TARQSTR _CAN4TARQ @(REG_BASE + 0x00000288); -#define CAN4TARQ _CAN4TARQ.Byte -#define CAN4TARQ_ABTRQ0 _CAN4TARQ.Bits.ABTRQ0 -#define CAN4TARQ_ABTRQ1 _CAN4TARQ.Bits.ABTRQ1 -#define CAN4TARQ_ABTRQ2 _CAN4TARQ.Bits.ABTRQ2 -#define CAN4TARQ_ABTRQ _CAN4TARQ.MergedBits.grpABTRQ - - -/*** CAN4TAAK - MSCAN4 Transmitter Message Abort Control; 0x00000289 ***/ -typedef union { - byte Byte; - struct { - byte ABTAK0 :1; /* Abort Acknowledge 0 */ - byte ABTAK1 :1; /* Abort Acknowledge 1 */ - byte ABTAK2 :1; /* Abort Acknowledge 2 */ - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpABTAK :3; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} CAN4TAAKSTR; -extern volatile CAN4TAAKSTR _CAN4TAAK @(REG_BASE + 0x00000289); -#define CAN4TAAK _CAN4TAAK.Byte -#define CAN4TAAK_ABTAK0 _CAN4TAAK.Bits.ABTAK0 -#define CAN4TAAK_ABTAK1 _CAN4TAAK.Bits.ABTAK1 -#define CAN4TAAK_ABTAK2 _CAN4TAAK.Bits.ABTAK2 -#define CAN4TAAK_ABTAK _CAN4TAAK.MergedBits.grpABTAK - - -/*** CAN4TBSEL - MSCAN4 Transmit Buffer Selection; 0x0000028A ***/ -typedef union { - byte Byte; - struct { - byte TX0 :1; /* Transmit Buffer Select 0 */ - byte TX1 :1; /* Transmit Buffer Select 1 */ - byte TX2 :1; /* Transmit Buffer Select 2 */ - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpTX :3; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} CAN4TBSELSTR; -extern volatile CAN4TBSELSTR _CAN4TBSEL @(REG_BASE + 0x0000028A); -#define CAN4TBSEL _CAN4TBSEL.Byte -#define CAN4TBSEL_TX0 _CAN4TBSEL.Bits.TX0 -#define CAN4TBSEL_TX1 _CAN4TBSEL.Bits.TX1 -#define CAN4TBSEL_TX2 _CAN4TBSEL.Bits.TX2 -#define CAN4TBSEL_TX _CAN4TBSEL.MergedBits.grpTX - - -/*** CAN4IDAC - MSCAN4 Identifier Acceptance Control Register; 0x0000028B ***/ -typedef union { - byte Byte; - struct { - byte IDHIT0 :1; /* Identifier Acceptance Hit Indicator 0 */ - byte IDHIT1 :1; /* Identifier Acceptance Hit Indicator 1 */ - byte IDHIT2 :1; /* Identifier Acceptance Hit Indicator 2 */ - byte :1; - byte IDAM0 :1; /* Identifier Acceptance Mode 0 */ - byte IDAM1 :1; /* Identifier Acceptance Mode 1 */ - byte :1; - byte :1; - } Bits; - struct { - byte grpIDHIT :3; - byte :1; - byte grpIDAM :2; - byte :1; - byte :1; - } MergedBits; -} CAN4IDACSTR; -extern volatile CAN4IDACSTR _CAN4IDAC @(REG_BASE + 0x0000028B); -#define CAN4IDAC _CAN4IDAC.Byte -#define CAN4IDAC_IDHIT0 _CAN4IDAC.Bits.IDHIT0 -#define CAN4IDAC_IDHIT1 _CAN4IDAC.Bits.IDHIT1 -#define CAN4IDAC_IDHIT2 _CAN4IDAC.Bits.IDHIT2 -#define CAN4IDAC_IDAM0 _CAN4IDAC.Bits.IDAM0 -#define CAN4IDAC_IDAM1 _CAN4IDAC.Bits.IDAM1 -#define CAN4IDAC_IDHIT _CAN4IDAC.MergedBits.grpIDHIT -#define CAN4IDAC_IDAM _CAN4IDAC.MergedBits.grpIDAM - - -/*** CAN4RXERR - MSCAN4 Receive Error Counter Register; 0x0000028E ***/ -typedef union { - byte Byte; - struct { - byte RXERR0 :1; /* Bit 0 */ - byte RXERR1 :1; /* Bit 1 */ - byte RXERR2 :1; /* Bit 2 */ - byte RXERR3 :1; /* Bit 3 */ - byte RXERR4 :1; /* Bit 4 */ - byte RXERR5 :1; /* Bit 5 */ - byte RXERR6 :1; /* Bit 6 */ - byte RXERR7 :1; /* Bit 7 */ - } Bits; - struct { - byte grpRXERR :8; - } MergedBits; -} CAN4RXERRSTR; -extern volatile CAN4RXERRSTR _CAN4RXERR @(REG_BASE + 0x0000028E); -#define CAN4RXERR _CAN4RXERR.Byte -#define CAN4RXERR_RXERR0 _CAN4RXERR.Bits.RXERR0 -#define CAN4RXERR_RXERR1 _CAN4RXERR.Bits.RXERR1 -#define CAN4RXERR_RXERR2 _CAN4RXERR.Bits.RXERR2 -#define CAN4RXERR_RXERR3 _CAN4RXERR.Bits.RXERR3 -#define CAN4RXERR_RXERR4 _CAN4RXERR.Bits.RXERR4 -#define CAN4RXERR_RXERR5 _CAN4RXERR.Bits.RXERR5 -#define CAN4RXERR_RXERR6 _CAN4RXERR.Bits.RXERR6 -#define CAN4RXERR_RXERR7 _CAN4RXERR.Bits.RXERR7 -#define CAN4RXERR_RXERR _CAN4RXERR.MergedBits.grpRXERR - - -/*** CAN4TXERR - MSCAN4 Transmit Error Counter Register; 0x0000028F ***/ -typedef union { - byte Byte; - struct { - byte TXERR0 :1; /* Bit 0 */ - byte TXERR1 :1; /* Bit 1 */ - byte TXERR2 :1; /* Bit 2 */ - byte TXERR3 :1; /* Bit 3 */ - byte TXERR4 :1; /* Bit 4 */ - byte TXERR5 :1; /* Bit 5 */ - byte TXERR6 :1; /* Bit 6 */ - byte TXERR7 :1; /* Bit 7 */ - } Bits; - struct { - byte grpTXERR :8; - } MergedBits; -} CAN4TXERRSTR; -extern volatile CAN4TXERRSTR _CAN4TXERR @(REG_BASE + 0x0000028F); -#define CAN4TXERR _CAN4TXERR.Byte -#define CAN4TXERR_TXERR0 _CAN4TXERR.Bits.TXERR0 -#define CAN4TXERR_TXERR1 _CAN4TXERR.Bits.TXERR1 -#define CAN4TXERR_TXERR2 _CAN4TXERR.Bits.TXERR2 -#define CAN4TXERR_TXERR3 _CAN4TXERR.Bits.TXERR3 -#define CAN4TXERR_TXERR4 _CAN4TXERR.Bits.TXERR4 -#define CAN4TXERR_TXERR5 _CAN4TXERR.Bits.TXERR5 -#define CAN4TXERR_TXERR6 _CAN4TXERR.Bits.TXERR6 -#define CAN4TXERR_TXERR7 _CAN4TXERR.Bits.TXERR7 -#define CAN4TXERR_TXERR _CAN4TXERR.MergedBits.grpTXERR - - -/*** CAN4IDAR0 - MSCAN4 Identifier Acceptance Register 0; 0x00000290 ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CAN4IDAR0STR; -extern volatile CAN4IDAR0STR _CAN4IDAR0 @(REG_BASE + 0x00000290); -#define CAN4IDAR0 _CAN4IDAR0.Byte -#define CAN4IDAR0_AC0 _CAN4IDAR0.Bits.AC0 -#define CAN4IDAR0_AC1 _CAN4IDAR0.Bits.AC1 -#define CAN4IDAR0_AC2 _CAN4IDAR0.Bits.AC2 -#define CAN4IDAR0_AC3 _CAN4IDAR0.Bits.AC3 -#define CAN4IDAR0_AC4 _CAN4IDAR0.Bits.AC4 -#define CAN4IDAR0_AC5 _CAN4IDAR0.Bits.AC5 -#define CAN4IDAR0_AC6 _CAN4IDAR0.Bits.AC6 -#define CAN4IDAR0_AC7 _CAN4IDAR0.Bits.AC7 -#define CAN4IDAR0_AC _CAN4IDAR0.MergedBits.grpAC - - -/*** CAN4IDAR1 - MSCAN4 Identifier Acceptance Register 1; 0x00000291 ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CAN4IDAR1STR; -extern volatile CAN4IDAR1STR _CAN4IDAR1 @(REG_BASE + 0x00000291); -#define CAN4IDAR1 _CAN4IDAR1.Byte -#define CAN4IDAR1_AC0 _CAN4IDAR1.Bits.AC0 -#define CAN4IDAR1_AC1 _CAN4IDAR1.Bits.AC1 -#define CAN4IDAR1_AC2 _CAN4IDAR1.Bits.AC2 -#define CAN4IDAR1_AC3 _CAN4IDAR1.Bits.AC3 -#define CAN4IDAR1_AC4 _CAN4IDAR1.Bits.AC4 -#define CAN4IDAR1_AC5 _CAN4IDAR1.Bits.AC5 -#define CAN4IDAR1_AC6 _CAN4IDAR1.Bits.AC6 -#define CAN4IDAR1_AC7 _CAN4IDAR1.Bits.AC7 -#define CAN4IDAR1_AC _CAN4IDAR1.MergedBits.grpAC - - -/*** CAN4IDAR2 - MSCAN4 Identifier Acceptance Register 2; 0x00000292 ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CAN4IDAR2STR; -extern volatile CAN4IDAR2STR _CAN4IDAR2 @(REG_BASE + 0x00000292); -#define CAN4IDAR2 _CAN4IDAR2.Byte -#define CAN4IDAR2_AC0 _CAN4IDAR2.Bits.AC0 -#define CAN4IDAR2_AC1 _CAN4IDAR2.Bits.AC1 -#define CAN4IDAR2_AC2 _CAN4IDAR2.Bits.AC2 -#define CAN4IDAR2_AC3 _CAN4IDAR2.Bits.AC3 -#define CAN4IDAR2_AC4 _CAN4IDAR2.Bits.AC4 -#define CAN4IDAR2_AC5 _CAN4IDAR2.Bits.AC5 -#define CAN4IDAR2_AC6 _CAN4IDAR2.Bits.AC6 -#define CAN4IDAR2_AC7 _CAN4IDAR2.Bits.AC7 -#define CAN4IDAR2_AC _CAN4IDAR2.MergedBits.grpAC - - -/*** CAN4IDAR3 - MSCAN4 Identifier Acceptance Register 3; 0x00000293 ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CAN4IDAR3STR; -extern volatile CAN4IDAR3STR _CAN4IDAR3 @(REG_BASE + 0x00000293); -#define CAN4IDAR3 _CAN4IDAR3.Byte -#define CAN4IDAR3_AC0 _CAN4IDAR3.Bits.AC0 -#define CAN4IDAR3_AC1 _CAN4IDAR3.Bits.AC1 -#define CAN4IDAR3_AC2 _CAN4IDAR3.Bits.AC2 -#define CAN4IDAR3_AC3 _CAN4IDAR3.Bits.AC3 -#define CAN4IDAR3_AC4 _CAN4IDAR3.Bits.AC4 -#define CAN4IDAR3_AC5 _CAN4IDAR3.Bits.AC5 -#define CAN4IDAR3_AC6 _CAN4IDAR3.Bits.AC6 -#define CAN4IDAR3_AC7 _CAN4IDAR3.Bits.AC7 -#define CAN4IDAR3_AC _CAN4IDAR3.MergedBits.grpAC - - -/*** CAN4IDMR0 - MSCAN4 Identifier Mask Register 0; 0x00000294 ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CAN4IDMR0STR; -extern volatile CAN4IDMR0STR _CAN4IDMR0 @(REG_BASE + 0x00000294); -#define CAN4IDMR0 _CAN4IDMR0.Byte -#define CAN4IDMR0_AM0 _CAN4IDMR0.Bits.AM0 -#define CAN4IDMR0_AM1 _CAN4IDMR0.Bits.AM1 -#define CAN4IDMR0_AM2 _CAN4IDMR0.Bits.AM2 -#define CAN4IDMR0_AM3 _CAN4IDMR0.Bits.AM3 -#define CAN4IDMR0_AM4 _CAN4IDMR0.Bits.AM4 -#define CAN4IDMR0_AM5 _CAN4IDMR0.Bits.AM5 -#define CAN4IDMR0_AM6 _CAN4IDMR0.Bits.AM6 -#define CAN4IDMR0_AM7 _CAN4IDMR0.Bits.AM7 -#define CAN4IDMR0_AM _CAN4IDMR0.MergedBits.grpAM - - -/*** CAN4IDMR1 - MSCAN4 Identifier Mask Register 1; 0x00000295 ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CAN4IDMR1STR; -extern volatile CAN4IDMR1STR _CAN4IDMR1 @(REG_BASE + 0x00000295); -#define CAN4IDMR1 _CAN4IDMR1.Byte -#define CAN4IDMR1_AM0 _CAN4IDMR1.Bits.AM0 -#define CAN4IDMR1_AM1 _CAN4IDMR1.Bits.AM1 -#define CAN4IDMR1_AM2 _CAN4IDMR1.Bits.AM2 -#define CAN4IDMR1_AM3 _CAN4IDMR1.Bits.AM3 -#define CAN4IDMR1_AM4 _CAN4IDMR1.Bits.AM4 -#define CAN4IDMR1_AM5 _CAN4IDMR1.Bits.AM5 -#define CAN4IDMR1_AM6 _CAN4IDMR1.Bits.AM6 -#define CAN4IDMR1_AM7 _CAN4IDMR1.Bits.AM7 -#define CAN4IDMR1_AM _CAN4IDMR1.MergedBits.grpAM - - -/*** CAN4IDMR2 - MSCAN4 Identifier Mask Register 2; 0x00000296 ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CAN4IDMR2STR; -extern volatile CAN4IDMR2STR _CAN4IDMR2 @(REG_BASE + 0x00000296); -#define CAN4IDMR2 _CAN4IDMR2.Byte -#define CAN4IDMR2_AM0 _CAN4IDMR2.Bits.AM0 -#define CAN4IDMR2_AM1 _CAN4IDMR2.Bits.AM1 -#define CAN4IDMR2_AM2 _CAN4IDMR2.Bits.AM2 -#define CAN4IDMR2_AM3 _CAN4IDMR2.Bits.AM3 -#define CAN4IDMR2_AM4 _CAN4IDMR2.Bits.AM4 -#define CAN4IDMR2_AM5 _CAN4IDMR2.Bits.AM5 -#define CAN4IDMR2_AM6 _CAN4IDMR2.Bits.AM6 -#define CAN4IDMR2_AM7 _CAN4IDMR2.Bits.AM7 -#define CAN4IDMR2_AM _CAN4IDMR2.MergedBits.grpAM - - -/*** CAN4IDMR3 - MSCAN4 Identifier Mask Register 3; 0x00000297 ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CAN4IDMR3STR; -extern volatile CAN4IDMR3STR _CAN4IDMR3 @(REG_BASE + 0x00000297); -#define CAN4IDMR3 _CAN4IDMR3.Byte -#define CAN4IDMR3_AM0 _CAN4IDMR3.Bits.AM0 -#define CAN4IDMR3_AM1 _CAN4IDMR3.Bits.AM1 -#define CAN4IDMR3_AM2 _CAN4IDMR3.Bits.AM2 -#define CAN4IDMR3_AM3 _CAN4IDMR3.Bits.AM3 -#define CAN4IDMR3_AM4 _CAN4IDMR3.Bits.AM4 -#define CAN4IDMR3_AM5 _CAN4IDMR3.Bits.AM5 -#define CAN4IDMR3_AM6 _CAN4IDMR3.Bits.AM6 -#define CAN4IDMR3_AM7 _CAN4IDMR3.Bits.AM7 -#define CAN4IDMR3_AM _CAN4IDMR3.MergedBits.grpAM - - -/*** CAN4IDAR4 - MSCAN4 Identifier Acceptance Register 4; 0x00000298 ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CAN4IDAR4STR; -extern volatile CAN4IDAR4STR _CAN4IDAR4 @(REG_BASE + 0x00000298); -#define CAN4IDAR4 _CAN4IDAR4.Byte -#define CAN4IDAR4_AC0 _CAN4IDAR4.Bits.AC0 -#define CAN4IDAR4_AC1 _CAN4IDAR4.Bits.AC1 -#define CAN4IDAR4_AC2 _CAN4IDAR4.Bits.AC2 -#define CAN4IDAR4_AC3 _CAN4IDAR4.Bits.AC3 -#define CAN4IDAR4_AC4 _CAN4IDAR4.Bits.AC4 -#define CAN4IDAR4_AC5 _CAN4IDAR4.Bits.AC5 -#define CAN4IDAR4_AC6 _CAN4IDAR4.Bits.AC6 -#define CAN4IDAR4_AC7 _CAN4IDAR4.Bits.AC7 -#define CAN4IDAR4_AC _CAN4IDAR4.MergedBits.grpAC - - -/*** CAN4IDAR5 - MSCAN4 Identifier Acceptance Register 5; 0x00000299 ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CAN4IDAR5STR; -extern volatile CAN4IDAR5STR _CAN4IDAR5 @(REG_BASE + 0x00000299); -#define CAN4IDAR5 _CAN4IDAR5.Byte -#define CAN4IDAR5_AC0 _CAN4IDAR5.Bits.AC0 -#define CAN4IDAR5_AC1 _CAN4IDAR5.Bits.AC1 -#define CAN4IDAR5_AC2 _CAN4IDAR5.Bits.AC2 -#define CAN4IDAR5_AC3 _CAN4IDAR5.Bits.AC3 -#define CAN4IDAR5_AC4 _CAN4IDAR5.Bits.AC4 -#define CAN4IDAR5_AC5 _CAN4IDAR5.Bits.AC5 -#define CAN4IDAR5_AC6 _CAN4IDAR5.Bits.AC6 -#define CAN4IDAR5_AC7 _CAN4IDAR5.Bits.AC7 -#define CAN4IDAR5_AC _CAN4IDAR5.MergedBits.grpAC - - -/*** CAN4IDAR6 - MSCAN4 Identifier Acceptance Register 6; 0x0000029A ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CAN4IDAR6STR; -extern volatile CAN4IDAR6STR _CAN4IDAR6 @(REG_BASE + 0x0000029A); -#define CAN4IDAR6 _CAN4IDAR6.Byte -#define CAN4IDAR6_AC0 _CAN4IDAR6.Bits.AC0 -#define CAN4IDAR6_AC1 _CAN4IDAR6.Bits.AC1 -#define CAN4IDAR6_AC2 _CAN4IDAR6.Bits.AC2 -#define CAN4IDAR6_AC3 _CAN4IDAR6.Bits.AC3 -#define CAN4IDAR6_AC4 _CAN4IDAR6.Bits.AC4 -#define CAN4IDAR6_AC5 _CAN4IDAR6.Bits.AC5 -#define CAN4IDAR6_AC6 _CAN4IDAR6.Bits.AC6 -#define CAN4IDAR6_AC7 _CAN4IDAR6.Bits.AC7 -#define CAN4IDAR6_AC _CAN4IDAR6.MergedBits.grpAC - - -/*** CAN4IDAR7 - MSCAN4 Identifier Acceptance Register 7; 0x0000029B ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CAN4IDAR7STR; -extern volatile CAN4IDAR7STR _CAN4IDAR7 @(REG_BASE + 0x0000029B); -#define CAN4IDAR7 _CAN4IDAR7.Byte -#define CAN4IDAR7_AC0 _CAN4IDAR7.Bits.AC0 -#define CAN4IDAR7_AC1 _CAN4IDAR7.Bits.AC1 -#define CAN4IDAR7_AC2 _CAN4IDAR7.Bits.AC2 -#define CAN4IDAR7_AC3 _CAN4IDAR7.Bits.AC3 -#define CAN4IDAR7_AC4 _CAN4IDAR7.Bits.AC4 -#define CAN4IDAR7_AC5 _CAN4IDAR7.Bits.AC5 -#define CAN4IDAR7_AC6 _CAN4IDAR7.Bits.AC6 -#define CAN4IDAR7_AC7 _CAN4IDAR7.Bits.AC7 -#define CAN4IDAR7_AC _CAN4IDAR7.MergedBits.grpAC - - -/*** CAN4IDMR4 - MSCAN4 Identifier Mask Register 4; 0x0000029C ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CAN4IDMR4STR; -extern volatile CAN4IDMR4STR _CAN4IDMR4 @(REG_BASE + 0x0000029C); -#define CAN4IDMR4 _CAN4IDMR4.Byte -#define CAN4IDMR4_AM0 _CAN4IDMR4.Bits.AM0 -#define CAN4IDMR4_AM1 _CAN4IDMR4.Bits.AM1 -#define CAN4IDMR4_AM2 _CAN4IDMR4.Bits.AM2 -#define CAN4IDMR4_AM3 _CAN4IDMR4.Bits.AM3 -#define CAN4IDMR4_AM4 _CAN4IDMR4.Bits.AM4 -#define CAN4IDMR4_AM5 _CAN4IDMR4.Bits.AM5 -#define CAN4IDMR4_AM6 _CAN4IDMR4.Bits.AM6 -#define CAN4IDMR4_AM7 _CAN4IDMR4.Bits.AM7 -#define CAN4IDMR4_AM _CAN4IDMR4.MergedBits.grpAM - - -/*** CAN4IDMR5 - MSCAN4 Identifier Mask Register 5; 0x0000029D ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CAN4IDMR5STR; -extern volatile CAN4IDMR5STR _CAN4IDMR5 @(REG_BASE + 0x0000029D); -#define CAN4IDMR5 _CAN4IDMR5.Byte -#define CAN4IDMR5_AM0 _CAN4IDMR5.Bits.AM0 -#define CAN4IDMR5_AM1 _CAN4IDMR5.Bits.AM1 -#define CAN4IDMR5_AM2 _CAN4IDMR5.Bits.AM2 -#define CAN4IDMR5_AM3 _CAN4IDMR5.Bits.AM3 -#define CAN4IDMR5_AM4 _CAN4IDMR5.Bits.AM4 -#define CAN4IDMR5_AM5 _CAN4IDMR5.Bits.AM5 -#define CAN4IDMR5_AM6 _CAN4IDMR5.Bits.AM6 -#define CAN4IDMR5_AM7 _CAN4IDMR5.Bits.AM7 -#define CAN4IDMR5_AM _CAN4IDMR5.MergedBits.grpAM - - -/*** CAN4IDMR6 - MSCAN4 Identifier Mask Register 6; 0x0000029E ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CAN4IDMR6STR; -extern volatile CAN4IDMR6STR _CAN4IDMR6 @(REG_BASE + 0x0000029E); -#define CAN4IDMR6 _CAN4IDMR6.Byte -#define CAN4IDMR6_AM0 _CAN4IDMR6.Bits.AM0 -#define CAN4IDMR6_AM1 _CAN4IDMR6.Bits.AM1 -#define CAN4IDMR6_AM2 _CAN4IDMR6.Bits.AM2 -#define CAN4IDMR6_AM3 _CAN4IDMR6.Bits.AM3 -#define CAN4IDMR6_AM4 _CAN4IDMR6.Bits.AM4 -#define CAN4IDMR6_AM5 _CAN4IDMR6.Bits.AM5 -#define CAN4IDMR6_AM6 _CAN4IDMR6.Bits.AM6 -#define CAN4IDMR6_AM7 _CAN4IDMR6.Bits.AM7 -#define CAN4IDMR6_AM _CAN4IDMR6.MergedBits.grpAM - - -/*** CAN4IDMR7 - MSCAN4 Identifier Mask Register 7; 0x0000029F ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CAN4IDMR7STR; -extern volatile CAN4IDMR7STR _CAN4IDMR7 @(REG_BASE + 0x0000029F); -#define CAN4IDMR7 _CAN4IDMR7.Byte -#define CAN4IDMR7_AM0 _CAN4IDMR7.Bits.AM0 -#define CAN4IDMR7_AM1 _CAN4IDMR7.Bits.AM1 -#define CAN4IDMR7_AM2 _CAN4IDMR7.Bits.AM2 -#define CAN4IDMR7_AM3 _CAN4IDMR7.Bits.AM3 -#define CAN4IDMR7_AM4 _CAN4IDMR7.Bits.AM4 -#define CAN4IDMR7_AM5 _CAN4IDMR7.Bits.AM5 -#define CAN4IDMR7_AM6 _CAN4IDMR7.Bits.AM6 -#define CAN4IDMR7_AM7 _CAN4IDMR7.Bits.AM7 -#define CAN4IDMR7_AM _CAN4IDMR7.MergedBits.grpAM - - -/*** CAN4RXIDR0 - MSCAN4 Receive Identifier Register 0; 0x000002A0 ***/ -typedef union { - byte Byte; - struct { - byte ID21 :1; /* Extended format identifier Bit 21 */ - byte ID22 :1; /* Extended format identifier Bit 22 */ - byte ID23 :1; /* Extended format identifier Bit 23 */ - byte ID24 :1; /* Extended format identifier Bit 24 */ - byte ID25 :1; /* Extended format identifier Bit 25 */ - byte ID26 :1; /* Extended format identifier Bit 26 */ - byte ID27 :1; /* Extended format identifier Bit 27 */ - byte ID28 :1; /* Extended format identifier Bit 28 */ - } Bits; - struct { - byte grpID_21 :8; - } MergedBits; -} CAN4RXIDR0STR; -extern volatile CAN4RXIDR0STR _CAN4RXIDR0 @(REG_BASE + 0x000002A0); -#define CAN4RXIDR0 _CAN4RXIDR0.Byte -#define CAN4RXIDR0_ID21 _CAN4RXIDR0.Bits.ID21 -#define CAN4RXIDR0_ID22 _CAN4RXIDR0.Bits.ID22 -#define CAN4RXIDR0_ID23 _CAN4RXIDR0.Bits.ID23 -#define CAN4RXIDR0_ID24 _CAN4RXIDR0.Bits.ID24 -#define CAN4RXIDR0_ID25 _CAN4RXIDR0.Bits.ID25 -#define CAN4RXIDR0_ID26 _CAN4RXIDR0.Bits.ID26 -#define CAN4RXIDR0_ID27 _CAN4RXIDR0.Bits.ID27 -#define CAN4RXIDR0_ID28 _CAN4RXIDR0.Bits.ID28 -#define CAN4RXIDR0_ID_21 _CAN4RXIDR0.MergedBits.grpID_21 -#define CAN4RXIDR0_ID CAN4RXIDR0_ID_21 - - -/*** CAN4RXIDR1 - MSCAN4 Receive Identifier Register 1; 0x000002A1 ***/ -typedef union { - byte Byte; - struct { - byte ID15 :1; /* Extended format identifier Bit 15 */ - byte ID16 :1; /* Extended format identifier Bit 16 */ - byte ID17 :1; /* Extended format identifier Bit 17 */ - byte IDE :1; /* ID Extended */ - byte SRR :1; /* Substitute Remote Request */ - byte ID18 :1; /* Extended format identifier Bit 18 */ - byte ID19 :1; /* Extended format identifier Bit 19 */ - byte ID20 :1; /* Extended format identifier Bit 20 */ - } Bits; - struct { - byte grpID_15 :3; - byte :1; - byte :1; - byte grpID_18 :3; - } MergedBits; -} CAN4RXIDR1STR; -extern volatile CAN4RXIDR1STR _CAN4RXIDR1 @(REG_BASE + 0x000002A1); -#define CAN4RXIDR1 _CAN4RXIDR1.Byte -#define CAN4RXIDR1_ID15 _CAN4RXIDR1.Bits.ID15 -#define CAN4RXIDR1_ID16 _CAN4RXIDR1.Bits.ID16 -#define CAN4RXIDR1_ID17 _CAN4RXIDR1.Bits.ID17 -#define CAN4RXIDR1_IDE _CAN4RXIDR1.Bits.IDE -#define CAN4RXIDR1_SRR _CAN4RXIDR1.Bits.SRR -#define CAN4RXIDR1_ID18 _CAN4RXIDR1.Bits.ID18 -#define CAN4RXIDR1_ID19 _CAN4RXIDR1.Bits.ID19 -#define CAN4RXIDR1_ID20 _CAN4RXIDR1.Bits.ID20 -#define CAN4RXIDR1_ID_15 _CAN4RXIDR1.MergedBits.grpID_15 -#define CAN4RXIDR1_ID_18 _CAN4RXIDR1.MergedBits.grpID_18 -#define CAN4RXIDR1_ID CAN4RXIDR1_ID_15 - - -/*** CAN4RXIDR2 - MSCAN4 Receive Identifier Register 2; 0x000002A2 ***/ -typedef union { - byte Byte; - struct { - byte ID7 :1; /* Extended format identifier Bit 7 */ - byte ID8 :1; /* Extended format identifier Bit 8 */ - byte ID9 :1; /* Extended format identifier Bit 9 */ - byte ID10 :1; /* Extended format identifier Bit 10 */ - byte ID11 :1; /* Extended format identifier Bit 11 */ - byte ID12 :1; /* Extended format identifier Bit 12 */ - byte ID13 :1; /* Extended format identifier Bit 13 */ - byte ID14 :1; /* Extended format identifier Bit 14 */ - } Bits; - struct { - byte grpID_7 :8; - } MergedBits; -} CAN4RXIDR2STR; -extern volatile CAN4RXIDR2STR _CAN4RXIDR2 @(REG_BASE + 0x000002A2); -#define CAN4RXIDR2 _CAN4RXIDR2.Byte -#define CAN4RXIDR2_ID7 _CAN4RXIDR2.Bits.ID7 -#define CAN4RXIDR2_ID8 _CAN4RXIDR2.Bits.ID8 -#define CAN4RXIDR2_ID9 _CAN4RXIDR2.Bits.ID9 -#define CAN4RXIDR2_ID10 _CAN4RXIDR2.Bits.ID10 -#define CAN4RXIDR2_ID11 _CAN4RXIDR2.Bits.ID11 -#define CAN4RXIDR2_ID12 _CAN4RXIDR2.Bits.ID12 -#define CAN4RXIDR2_ID13 _CAN4RXIDR2.Bits.ID13 -#define CAN4RXIDR2_ID14 _CAN4RXIDR2.Bits.ID14 -#define CAN4RXIDR2_ID_7 _CAN4RXIDR2.MergedBits.grpID_7 -#define CAN4RXIDR2_ID CAN4RXIDR2_ID_7 - - -/*** CAN4RXIDR3 - MSCAN4 Receive Identifier Register 3; 0x000002A3 ***/ -typedef union { - byte Byte; - struct { - byte RTR :1; /* Remote Transmission Request */ - byte ID0 :1; /* Extended format identifier Bit 0 */ - byte ID1 :1; /* Extended format identifier Bit 1 */ - byte ID2 :1; /* Extended format identifier Bit 2 */ - byte ID3 :1; /* Extended format identifier Bit 3 */ - byte ID4 :1; /* Extended format identifier Bit 4 */ - byte ID5 :1; /* Extended format identifier Bit 5 */ - byte ID6 :1; /* Extended format identifier Bit 6 */ - } Bits; - struct { - byte :1; - byte grpID :7; - } MergedBits; -} CAN4RXIDR3STR; -extern volatile CAN4RXIDR3STR _CAN4RXIDR3 @(REG_BASE + 0x000002A3); -#define CAN4RXIDR3 _CAN4RXIDR3.Byte -#define CAN4RXIDR3_RTR _CAN4RXIDR3.Bits.RTR -#define CAN4RXIDR3_ID0 _CAN4RXIDR3.Bits.ID0 -#define CAN4RXIDR3_ID1 _CAN4RXIDR3.Bits.ID1 -#define CAN4RXIDR3_ID2 _CAN4RXIDR3.Bits.ID2 -#define CAN4RXIDR3_ID3 _CAN4RXIDR3.Bits.ID3 -#define CAN4RXIDR3_ID4 _CAN4RXIDR3.Bits.ID4 -#define CAN4RXIDR3_ID5 _CAN4RXIDR3.Bits.ID5 -#define CAN4RXIDR3_ID6 _CAN4RXIDR3.Bits.ID6 -#define CAN4RXIDR3_ID _CAN4RXIDR3.MergedBits.grpID - - -/*** CAN4RXDSR0 - MSCAN4 Receive Data Segment Register 0; 0x000002A4 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN4RXDSR0STR; -extern volatile CAN4RXDSR0STR _CAN4RXDSR0 @(REG_BASE + 0x000002A4); -#define CAN4RXDSR0 _CAN4RXDSR0.Byte -#define CAN4RXDSR0_DB0 _CAN4RXDSR0.Bits.DB0 -#define CAN4RXDSR0_DB1 _CAN4RXDSR0.Bits.DB1 -#define CAN4RXDSR0_DB2 _CAN4RXDSR0.Bits.DB2 -#define CAN4RXDSR0_DB3 _CAN4RXDSR0.Bits.DB3 -#define CAN4RXDSR0_DB4 _CAN4RXDSR0.Bits.DB4 -#define CAN4RXDSR0_DB5 _CAN4RXDSR0.Bits.DB5 -#define CAN4RXDSR0_DB6 _CAN4RXDSR0.Bits.DB6 -#define CAN4RXDSR0_DB7 _CAN4RXDSR0.Bits.DB7 -#define CAN4RXDSR0_DB _CAN4RXDSR0.MergedBits.grpDB - - -/*** CAN4RXDSR1 - MSCAN4 Receive Data Segment Register 1; 0x000002A5 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN4RXDSR1STR; -extern volatile CAN4RXDSR1STR _CAN4RXDSR1 @(REG_BASE + 0x000002A5); -#define CAN4RXDSR1 _CAN4RXDSR1.Byte -#define CAN4RXDSR1_DB0 _CAN4RXDSR1.Bits.DB0 -#define CAN4RXDSR1_DB1 _CAN4RXDSR1.Bits.DB1 -#define CAN4RXDSR1_DB2 _CAN4RXDSR1.Bits.DB2 -#define CAN4RXDSR1_DB3 _CAN4RXDSR1.Bits.DB3 -#define CAN4RXDSR1_DB4 _CAN4RXDSR1.Bits.DB4 -#define CAN4RXDSR1_DB5 _CAN4RXDSR1.Bits.DB5 -#define CAN4RXDSR1_DB6 _CAN4RXDSR1.Bits.DB6 -#define CAN4RXDSR1_DB7 _CAN4RXDSR1.Bits.DB7 -#define CAN4RXDSR1_DB _CAN4RXDSR1.MergedBits.grpDB - - -/*** CAN4RXDSR2 - MSCAN4 Receive Data Segment Register 2; 0x000002A6 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN4RXDSR2STR; -extern volatile CAN4RXDSR2STR _CAN4RXDSR2 @(REG_BASE + 0x000002A6); -#define CAN4RXDSR2 _CAN4RXDSR2.Byte -#define CAN4RXDSR2_DB0 _CAN4RXDSR2.Bits.DB0 -#define CAN4RXDSR2_DB1 _CAN4RXDSR2.Bits.DB1 -#define CAN4RXDSR2_DB2 _CAN4RXDSR2.Bits.DB2 -#define CAN4RXDSR2_DB3 _CAN4RXDSR2.Bits.DB3 -#define CAN4RXDSR2_DB4 _CAN4RXDSR2.Bits.DB4 -#define CAN4RXDSR2_DB5 _CAN4RXDSR2.Bits.DB5 -#define CAN4RXDSR2_DB6 _CAN4RXDSR2.Bits.DB6 -#define CAN4RXDSR2_DB7 _CAN4RXDSR2.Bits.DB7 -#define CAN4RXDSR2_DB _CAN4RXDSR2.MergedBits.grpDB - - -/*** CAN4RXDSR3 - MSCAN4 Receive Data Segment Register 3; 0x000002A7 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN4RXDSR3STR; -extern volatile CAN4RXDSR3STR _CAN4RXDSR3 @(REG_BASE + 0x000002A7); -#define CAN4RXDSR3 _CAN4RXDSR3.Byte -#define CAN4RXDSR3_DB0 _CAN4RXDSR3.Bits.DB0 -#define CAN4RXDSR3_DB1 _CAN4RXDSR3.Bits.DB1 -#define CAN4RXDSR3_DB2 _CAN4RXDSR3.Bits.DB2 -#define CAN4RXDSR3_DB3 _CAN4RXDSR3.Bits.DB3 -#define CAN4RXDSR3_DB4 _CAN4RXDSR3.Bits.DB4 -#define CAN4RXDSR3_DB5 _CAN4RXDSR3.Bits.DB5 -#define CAN4RXDSR3_DB6 _CAN4RXDSR3.Bits.DB6 -#define CAN4RXDSR3_DB7 _CAN4RXDSR3.Bits.DB7 -#define CAN4RXDSR3_DB _CAN4RXDSR3.MergedBits.grpDB - - -/*** CAN4RXDSR4 - MSCAN4 Receive Data Segment Register 4; 0x000002A8 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN4RXDSR4STR; -extern volatile CAN4RXDSR4STR _CAN4RXDSR4 @(REG_BASE + 0x000002A8); -#define CAN4RXDSR4 _CAN4RXDSR4.Byte -#define CAN4RXDSR4_DB0 _CAN4RXDSR4.Bits.DB0 -#define CAN4RXDSR4_DB1 _CAN4RXDSR4.Bits.DB1 -#define CAN4RXDSR4_DB2 _CAN4RXDSR4.Bits.DB2 -#define CAN4RXDSR4_DB3 _CAN4RXDSR4.Bits.DB3 -#define CAN4RXDSR4_DB4 _CAN4RXDSR4.Bits.DB4 -#define CAN4RXDSR4_DB5 _CAN4RXDSR4.Bits.DB5 -#define CAN4RXDSR4_DB6 _CAN4RXDSR4.Bits.DB6 -#define CAN4RXDSR4_DB7 _CAN4RXDSR4.Bits.DB7 -#define CAN4RXDSR4_DB _CAN4RXDSR4.MergedBits.grpDB - - -/*** CAN4RXDSR5 - MSCAN4 Receive Data Segment Register 5; 0x000002A9 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN4RXDSR5STR; -extern volatile CAN4RXDSR5STR _CAN4RXDSR5 @(REG_BASE + 0x000002A9); -#define CAN4RXDSR5 _CAN4RXDSR5.Byte -#define CAN4RXDSR5_DB0 _CAN4RXDSR5.Bits.DB0 -#define CAN4RXDSR5_DB1 _CAN4RXDSR5.Bits.DB1 -#define CAN4RXDSR5_DB2 _CAN4RXDSR5.Bits.DB2 -#define CAN4RXDSR5_DB3 _CAN4RXDSR5.Bits.DB3 -#define CAN4RXDSR5_DB4 _CAN4RXDSR5.Bits.DB4 -#define CAN4RXDSR5_DB5 _CAN4RXDSR5.Bits.DB5 -#define CAN4RXDSR5_DB6 _CAN4RXDSR5.Bits.DB6 -#define CAN4RXDSR5_DB7 _CAN4RXDSR5.Bits.DB7 -#define CAN4RXDSR5_DB _CAN4RXDSR5.MergedBits.grpDB - - -/*** CAN4RXDSR6 - MSCAN4 Receive Data Segment Register 6; 0x000002AA ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN4RXDSR6STR; -extern volatile CAN4RXDSR6STR _CAN4RXDSR6 @(REG_BASE + 0x000002AA); -#define CAN4RXDSR6 _CAN4RXDSR6.Byte -#define CAN4RXDSR6_DB0 _CAN4RXDSR6.Bits.DB0 -#define CAN4RXDSR6_DB1 _CAN4RXDSR6.Bits.DB1 -#define CAN4RXDSR6_DB2 _CAN4RXDSR6.Bits.DB2 -#define CAN4RXDSR6_DB3 _CAN4RXDSR6.Bits.DB3 -#define CAN4RXDSR6_DB4 _CAN4RXDSR6.Bits.DB4 -#define CAN4RXDSR6_DB5 _CAN4RXDSR6.Bits.DB5 -#define CAN4RXDSR6_DB6 _CAN4RXDSR6.Bits.DB6 -#define CAN4RXDSR6_DB7 _CAN4RXDSR6.Bits.DB7 -#define CAN4RXDSR6_DB _CAN4RXDSR6.MergedBits.grpDB - - -/*** CAN4RXDSR7 - MSCAN4 Receive Data Segment Register 7; 0x000002AB ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN4RXDSR7STR; -extern volatile CAN4RXDSR7STR _CAN4RXDSR7 @(REG_BASE + 0x000002AB); -#define CAN4RXDSR7 _CAN4RXDSR7.Byte -#define CAN4RXDSR7_DB0 _CAN4RXDSR7.Bits.DB0 -#define CAN4RXDSR7_DB1 _CAN4RXDSR7.Bits.DB1 -#define CAN4RXDSR7_DB2 _CAN4RXDSR7.Bits.DB2 -#define CAN4RXDSR7_DB3 _CAN4RXDSR7.Bits.DB3 -#define CAN4RXDSR7_DB4 _CAN4RXDSR7.Bits.DB4 -#define CAN4RXDSR7_DB5 _CAN4RXDSR7.Bits.DB5 -#define CAN4RXDSR7_DB6 _CAN4RXDSR7.Bits.DB6 -#define CAN4RXDSR7_DB7 _CAN4RXDSR7.Bits.DB7 -#define CAN4RXDSR7_DB _CAN4RXDSR7.MergedBits.grpDB - - -/*** CAN4RXDLR - MSCAN4 Receive Data Length Register; 0x000002AC ***/ -typedef union { - byte Byte; - struct { - byte DLC0 :1; /* Data Length Code Bit 0 */ - byte DLC1 :1; /* Data Length Code Bit 1 */ - byte DLC2 :1; /* Data Length Code Bit 2 */ - byte DLC3 :1; /* Data Length Code Bit 3 */ - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpDLC :4; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} CAN4RXDLRSTR; -extern volatile CAN4RXDLRSTR _CAN4RXDLR @(REG_BASE + 0x000002AC); -#define CAN4RXDLR _CAN4RXDLR.Byte -#define CAN4RXDLR_DLC0 _CAN4RXDLR.Bits.DLC0 -#define CAN4RXDLR_DLC1 _CAN4RXDLR.Bits.DLC1 -#define CAN4RXDLR_DLC2 _CAN4RXDLR.Bits.DLC2 -#define CAN4RXDLR_DLC3 _CAN4RXDLR.Bits.DLC3 -#define CAN4RXDLR_DLC _CAN4RXDLR.MergedBits.grpDLC - - -/*** CAN4TXIDR0 - MSCAN4 Transmit Identifier Register 0; 0x000002B0 ***/ -typedef union { - byte Byte; - struct { - byte ID21 :1; /* Extended format identifier Bit 21 */ - byte ID22 :1; /* Extended format identifier Bit 22 */ - byte ID23 :1; /* Extended format identifier Bit 23 */ - byte ID24 :1; /* Extended format identifier Bit 24 */ - byte ID25 :1; /* Extended format identifier Bit 25 */ - byte ID26 :1; /* Extended format identifier Bit 26 */ - byte ID27 :1; /* Extended format identifier Bit 27 */ - byte ID28 :1; /* Extended format identifier Bit 28 */ - } Bits; - struct { - byte grpID_21 :8; - } MergedBits; -} CAN4TXIDR0STR; -extern volatile CAN4TXIDR0STR _CAN4TXIDR0 @(REG_BASE + 0x000002B0); -#define CAN4TXIDR0 _CAN4TXIDR0.Byte -#define CAN4TXIDR0_ID21 _CAN4TXIDR0.Bits.ID21 -#define CAN4TXIDR0_ID22 _CAN4TXIDR0.Bits.ID22 -#define CAN4TXIDR0_ID23 _CAN4TXIDR0.Bits.ID23 -#define CAN4TXIDR0_ID24 _CAN4TXIDR0.Bits.ID24 -#define CAN4TXIDR0_ID25 _CAN4TXIDR0.Bits.ID25 -#define CAN4TXIDR0_ID26 _CAN4TXIDR0.Bits.ID26 -#define CAN4TXIDR0_ID27 _CAN4TXIDR0.Bits.ID27 -#define CAN4TXIDR0_ID28 _CAN4TXIDR0.Bits.ID28 -#define CAN4TXIDR0_ID_21 _CAN4TXIDR0.MergedBits.grpID_21 -#define CAN4TXIDR0_ID CAN4TXIDR0_ID_21 - - -/*** CAN4TXIDR1 - MSCAN4 Transmit Identifier Register 1; 0x000002B1 ***/ -typedef union { - byte Byte; - struct { - byte ID15 :1; /* Extended format identifier Bit 15 */ - byte ID16 :1; /* Extended format identifier Bit 16 */ - byte ID17 :1; /* Extended format identifier Bit 17 */ - byte IDE :1; /* ID Extended */ - byte SRR :1; /* Substitute Remote Request */ - byte ID18 :1; /* Extended format identifier Bit 18 */ - byte ID19 :1; /* Extended format identifier Bit 19 */ - byte ID20 :1; /* Extended format identifier Bit 20 */ - } Bits; - struct { - byte grpID_15 :3; - byte :1; - byte :1; - byte grpID_18 :3; - } MergedBits; -} CAN4TXIDR1STR; -extern volatile CAN4TXIDR1STR _CAN4TXIDR1 @(REG_BASE + 0x000002B1); -#define CAN4TXIDR1 _CAN4TXIDR1.Byte -#define CAN4TXIDR1_ID15 _CAN4TXIDR1.Bits.ID15 -#define CAN4TXIDR1_ID16 _CAN4TXIDR1.Bits.ID16 -#define CAN4TXIDR1_ID17 _CAN4TXIDR1.Bits.ID17 -#define CAN4TXIDR1_IDE _CAN4TXIDR1.Bits.IDE -#define CAN4TXIDR1_SRR _CAN4TXIDR1.Bits.SRR -#define CAN4TXIDR1_ID18 _CAN4TXIDR1.Bits.ID18 -#define CAN4TXIDR1_ID19 _CAN4TXIDR1.Bits.ID19 -#define CAN4TXIDR1_ID20 _CAN4TXIDR1.Bits.ID20 -#define CAN4TXIDR1_ID_15 _CAN4TXIDR1.MergedBits.grpID_15 -#define CAN4TXIDR1_ID_18 _CAN4TXIDR1.MergedBits.grpID_18 -#define CAN4TXIDR1_ID CAN4TXIDR1_ID_15 - - -/*** CAN4TXIDR2 - MSCAN4 Transmit Identifier Register 2; 0x000002B2 ***/ -typedef union { - byte Byte; - struct { - byte ID7 :1; /* Extended format identifier Bit 7 */ - byte ID8 :1; /* Extended format identifier Bit 8 */ - byte ID9 :1; /* Extended format identifier Bit 9 */ - byte ID10 :1; /* Extended format identifier Bit 10 */ - byte ID11 :1; /* Extended format identifier Bit 11 */ - byte ID12 :1; /* Extended format identifier Bit 12 */ - byte ID13 :1; /* Extended format identifier Bit 13 */ - byte ID14 :1; /* Extended format identifier Bit 14 */ - } Bits; - struct { - byte grpID_7 :8; - } MergedBits; -} CAN4TXIDR2STR; -extern volatile CAN4TXIDR2STR _CAN4TXIDR2 @(REG_BASE + 0x000002B2); -#define CAN4TXIDR2 _CAN4TXIDR2.Byte -#define CAN4TXIDR2_ID7 _CAN4TXIDR2.Bits.ID7 -#define CAN4TXIDR2_ID8 _CAN4TXIDR2.Bits.ID8 -#define CAN4TXIDR2_ID9 _CAN4TXIDR2.Bits.ID9 -#define CAN4TXIDR2_ID10 _CAN4TXIDR2.Bits.ID10 -#define CAN4TXIDR2_ID11 _CAN4TXIDR2.Bits.ID11 -#define CAN4TXIDR2_ID12 _CAN4TXIDR2.Bits.ID12 -#define CAN4TXIDR2_ID13 _CAN4TXIDR2.Bits.ID13 -#define CAN4TXIDR2_ID14 _CAN4TXIDR2.Bits.ID14 -#define CAN4TXIDR2_ID_7 _CAN4TXIDR2.MergedBits.grpID_7 -#define CAN4TXIDR2_ID CAN4TXIDR2_ID_7 - - -/*** CAN4TXIDR3 - MSCAN4 Transmit Identifier Register 3; 0x000002B3 ***/ -typedef union { - byte Byte; - struct { - byte RTR :1; /* Remote Transmission Request */ - byte ID0 :1; /* Extended format identifier Bit 0 */ - byte ID1 :1; /* Extended format identifier Bit 1 */ - byte ID2 :1; /* Extended format identifier Bit 2 */ - byte ID3 :1; /* Extended format identifier Bit 3 */ - byte ID4 :1; /* Extended format identifier Bit 4 */ - byte ID5 :1; /* Extended format identifier Bit 5 */ - byte ID6 :1; /* Extended format identifier Bit 6 */ - } Bits; - struct { - byte :1; - byte grpID :7; - } MergedBits; -} CAN4TXIDR3STR; -extern volatile CAN4TXIDR3STR _CAN4TXIDR3 @(REG_BASE + 0x000002B3); -#define CAN4TXIDR3 _CAN4TXIDR3.Byte -#define CAN4TXIDR3_RTR _CAN4TXIDR3.Bits.RTR -#define CAN4TXIDR3_ID0 _CAN4TXIDR3.Bits.ID0 -#define CAN4TXIDR3_ID1 _CAN4TXIDR3.Bits.ID1 -#define CAN4TXIDR3_ID2 _CAN4TXIDR3.Bits.ID2 -#define CAN4TXIDR3_ID3 _CAN4TXIDR3.Bits.ID3 -#define CAN4TXIDR3_ID4 _CAN4TXIDR3.Bits.ID4 -#define CAN4TXIDR3_ID5 _CAN4TXIDR3.Bits.ID5 -#define CAN4TXIDR3_ID6 _CAN4TXIDR3.Bits.ID6 -#define CAN4TXIDR3_ID _CAN4TXIDR3.MergedBits.grpID - - -/*** CAN4TXDSR0 - MSCAN4 Transmit Data Segment Register 0; 0x000002B4 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN4TXDSR0STR; -extern volatile CAN4TXDSR0STR _CAN4TXDSR0 @(REG_BASE + 0x000002B4); -#define CAN4TXDSR0 _CAN4TXDSR0.Byte -#define CAN4TXDSR0_DB0 _CAN4TXDSR0.Bits.DB0 -#define CAN4TXDSR0_DB1 _CAN4TXDSR0.Bits.DB1 -#define CAN4TXDSR0_DB2 _CAN4TXDSR0.Bits.DB2 -#define CAN4TXDSR0_DB3 _CAN4TXDSR0.Bits.DB3 -#define CAN4TXDSR0_DB4 _CAN4TXDSR0.Bits.DB4 -#define CAN4TXDSR0_DB5 _CAN4TXDSR0.Bits.DB5 -#define CAN4TXDSR0_DB6 _CAN4TXDSR0.Bits.DB6 -#define CAN4TXDSR0_DB7 _CAN4TXDSR0.Bits.DB7 -#define CAN4TXDSR0_DB _CAN4TXDSR0.MergedBits.grpDB - - -/*** CAN4TXDSR1 - MSCAN4 Transmit Data Segment Register 1; 0x000002B5 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN4TXDSR1STR; -extern volatile CAN4TXDSR1STR _CAN4TXDSR1 @(REG_BASE + 0x000002B5); -#define CAN4TXDSR1 _CAN4TXDSR1.Byte -#define CAN4TXDSR1_DB0 _CAN4TXDSR1.Bits.DB0 -#define CAN4TXDSR1_DB1 _CAN4TXDSR1.Bits.DB1 -#define CAN4TXDSR1_DB2 _CAN4TXDSR1.Bits.DB2 -#define CAN4TXDSR1_DB3 _CAN4TXDSR1.Bits.DB3 -#define CAN4TXDSR1_DB4 _CAN4TXDSR1.Bits.DB4 -#define CAN4TXDSR1_DB5 _CAN4TXDSR1.Bits.DB5 -#define CAN4TXDSR1_DB6 _CAN4TXDSR1.Bits.DB6 -#define CAN4TXDSR1_DB7 _CAN4TXDSR1.Bits.DB7 -#define CAN4TXDSR1_DB _CAN4TXDSR1.MergedBits.grpDB - - -/*** CAN4TXDSR2 - MSCAN4 Transmit Data Segment Register 2; 0x000002B6 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN4TXDSR2STR; -extern volatile CAN4TXDSR2STR _CAN4TXDSR2 @(REG_BASE + 0x000002B6); -#define CAN4TXDSR2 _CAN4TXDSR2.Byte -#define CAN4TXDSR2_DB0 _CAN4TXDSR2.Bits.DB0 -#define CAN4TXDSR2_DB1 _CAN4TXDSR2.Bits.DB1 -#define CAN4TXDSR2_DB2 _CAN4TXDSR2.Bits.DB2 -#define CAN4TXDSR2_DB3 _CAN4TXDSR2.Bits.DB3 -#define CAN4TXDSR2_DB4 _CAN4TXDSR2.Bits.DB4 -#define CAN4TXDSR2_DB5 _CAN4TXDSR2.Bits.DB5 -#define CAN4TXDSR2_DB6 _CAN4TXDSR2.Bits.DB6 -#define CAN4TXDSR2_DB7 _CAN4TXDSR2.Bits.DB7 -#define CAN4TXDSR2_DB _CAN4TXDSR2.MergedBits.grpDB - - -/*** CAN4TXDSR3 - MSCAN4 Transmit Data Segment Register 3; 0x000002B7 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN4TXDSR3STR; -extern volatile CAN4TXDSR3STR _CAN4TXDSR3 @(REG_BASE + 0x000002B7); -#define CAN4TXDSR3 _CAN4TXDSR3.Byte -#define CAN4TXDSR3_DB0 _CAN4TXDSR3.Bits.DB0 -#define CAN4TXDSR3_DB1 _CAN4TXDSR3.Bits.DB1 -#define CAN4TXDSR3_DB2 _CAN4TXDSR3.Bits.DB2 -#define CAN4TXDSR3_DB3 _CAN4TXDSR3.Bits.DB3 -#define CAN4TXDSR3_DB4 _CAN4TXDSR3.Bits.DB4 -#define CAN4TXDSR3_DB5 _CAN4TXDSR3.Bits.DB5 -#define CAN4TXDSR3_DB6 _CAN4TXDSR3.Bits.DB6 -#define CAN4TXDSR3_DB7 _CAN4TXDSR3.Bits.DB7 -#define CAN4TXDSR3_DB _CAN4TXDSR3.MergedBits.grpDB - - -/*** CAN4TXDSR4 - MSCAN4 Transmit Data Segment Register 4; 0x000002B8 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN4TXDSR4STR; -extern volatile CAN4TXDSR4STR _CAN4TXDSR4 @(REG_BASE + 0x000002B8); -#define CAN4TXDSR4 _CAN4TXDSR4.Byte -#define CAN4TXDSR4_DB0 _CAN4TXDSR4.Bits.DB0 -#define CAN4TXDSR4_DB1 _CAN4TXDSR4.Bits.DB1 -#define CAN4TXDSR4_DB2 _CAN4TXDSR4.Bits.DB2 -#define CAN4TXDSR4_DB3 _CAN4TXDSR4.Bits.DB3 -#define CAN4TXDSR4_DB4 _CAN4TXDSR4.Bits.DB4 -#define CAN4TXDSR4_DB5 _CAN4TXDSR4.Bits.DB5 -#define CAN4TXDSR4_DB6 _CAN4TXDSR4.Bits.DB6 -#define CAN4TXDSR4_DB7 _CAN4TXDSR4.Bits.DB7 -#define CAN4TXDSR4_DB _CAN4TXDSR4.MergedBits.grpDB - - -/*** CAN4TXDSR5 - MSCAN4 Transmit Data Segment Register 5; 0x000002B9 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN4TXDSR5STR; -extern volatile CAN4TXDSR5STR _CAN4TXDSR5 @(REG_BASE + 0x000002B9); -#define CAN4TXDSR5 _CAN4TXDSR5.Byte -#define CAN4TXDSR5_DB0 _CAN4TXDSR5.Bits.DB0 -#define CAN4TXDSR5_DB1 _CAN4TXDSR5.Bits.DB1 -#define CAN4TXDSR5_DB2 _CAN4TXDSR5.Bits.DB2 -#define CAN4TXDSR5_DB3 _CAN4TXDSR5.Bits.DB3 -#define CAN4TXDSR5_DB4 _CAN4TXDSR5.Bits.DB4 -#define CAN4TXDSR5_DB5 _CAN4TXDSR5.Bits.DB5 -#define CAN4TXDSR5_DB6 _CAN4TXDSR5.Bits.DB6 -#define CAN4TXDSR5_DB7 _CAN4TXDSR5.Bits.DB7 -#define CAN4TXDSR5_DB _CAN4TXDSR5.MergedBits.grpDB - - -/*** CAN4TXDSR6 - MSCAN4 Transmit Data Segment Register 6; 0x000002BA ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN4TXDSR6STR; -extern volatile CAN4TXDSR6STR _CAN4TXDSR6 @(REG_BASE + 0x000002BA); -#define CAN4TXDSR6 _CAN4TXDSR6.Byte -#define CAN4TXDSR6_DB0 _CAN4TXDSR6.Bits.DB0 -#define CAN4TXDSR6_DB1 _CAN4TXDSR6.Bits.DB1 -#define CAN4TXDSR6_DB2 _CAN4TXDSR6.Bits.DB2 -#define CAN4TXDSR6_DB3 _CAN4TXDSR6.Bits.DB3 -#define CAN4TXDSR6_DB4 _CAN4TXDSR6.Bits.DB4 -#define CAN4TXDSR6_DB5 _CAN4TXDSR6.Bits.DB5 -#define CAN4TXDSR6_DB6 _CAN4TXDSR6.Bits.DB6 -#define CAN4TXDSR6_DB7 _CAN4TXDSR6.Bits.DB7 -#define CAN4TXDSR6_DB _CAN4TXDSR6.MergedBits.grpDB - - -/*** CAN4TXDSR7 - MSCAN4 Transmit Data Segment Register 7; 0x000002BB ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CAN4TXDSR7STR; -extern volatile CAN4TXDSR7STR _CAN4TXDSR7 @(REG_BASE + 0x000002BB); -#define CAN4TXDSR7 _CAN4TXDSR7.Byte -#define CAN4TXDSR7_DB0 _CAN4TXDSR7.Bits.DB0 -#define CAN4TXDSR7_DB1 _CAN4TXDSR7.Bits.DB1 -#define CAN4TXDSR7_DB2 _CAN4TXDSR7.Bits.DB2 -#define CAN4TXDSR7_DB3 _CAN4TXDSR7.Bits.DB3 -#define CAN4TXDSR7_DB4 _CAN4TXDSR7.Bits.DB4 -#define CAN4TXDSR7_DB5 _CAN4TXDSR7.Bits.DB5 -#define CAN4TXDSR7_DB6 _CAN4TXDSR7.Bits.DB6 -#define CAN4TXDSR7_DB7 _CAN4TXDSR7.Bits.DB7 -#define CAN4TXDSR7_DB _CAN4TXDSR7.MergedBits.grpDB - - -/*** CAN4TXDLR - MSCAN4 Transmit Data Length Register; 0x000002BC ***/ -typedef union { - byte Byte; - struct { - byte DLC0 :1; /* Data Length Code Bit 0 */ - byte DLC1 :1; /* Data Length Code Bit 1 */ - byte DLC2 :1; /* Data Length Code Bit 2 */ - byte DLC3 :1; /* Data Length Code Bit 3 */ - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpDLC :4; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} CAN4TXDLRSTR; -extern volatile CAN4TXDLRSTR _CAN4TXDLR @(REG_BASE + 0x000002BC); -#define CAN4TXDLR _CAN4TXDLR.Byte -#define CAN4TXDLR_DLC0 _CAN4TXDLR.Bits.DLC0 -#define CAN4TXDLR_DLC1 _CAN4TXDLR.Bits.DLC1 -#define CAN4TXDLR_DLC2 _CAN4TXDLR.Bits.DLC2 -#define CAN4TXDLR_DLC3 _CAN4TXDLR.Bits.DLC3 -#define CAN4TXDLR_DLC _CAN4TXDLR.MergedBits.grpDLC - - -/*** CAN4TXTBPR - MSCAN4 Transmit Transmit Buffer Priority; 0x000002BF ***/ -typedef union { - byte Byte; - struct { - byte PRIO0 :1; /* Transmit Buffer Priority Bit 0 */ - byte PRIO1 :1; /* Transmit Buffer Priority Bit 1 */ - byte PRIO2 :1; /* Transmit Buffer Priority Bit 2 */ - byte PRIO3 :1; /* Transmit Buffer Priority Bit 3 */ - byte PRIO4 :1; /* Transmit Buffer Priority Bit 4 */ - byte PRIO5 :1; /* Transmit Buffer Priority Bit 5 */ - byte PRIO6 :1; /* Transmit Buffer Priority Bit 6 */ - byte PRIO7 :1; /* Transmit Buffer Priority Bit 7 */ - } Bits; - struct { - byte grpPRIO :8; - } MergedBits; -} CAN4TXTBPRSTR; -extern volatile CAN4TXTBPRSTR _CAN4TXTBPR @(REG_BASE + 0x000002BF); -#define CAN4TXTBPR _CAN4TXTBPR.Byte -#define CAN4TXTBPR_PRIO0 _CAN4TXTBPR.Bits.PRIO0 -#define CAN4TXTBPR_PRIO1 _CAN4TXTBPR.Bits.PRIO1 -#define CAN4TXTBPR_PRIO2 _CAN4TXTBPR.Bits.PRIO2 -#define CAN4TXTBPR_PRIO3 _CAN4TXTBPR.Bits.PRIO3 -#define CAN4TXTBPR_PRIO4 _CAN4TXTBPR.Bits.PRIO4 -#define CAN4TXTBPR_PRIO5 _CAN4TXTBPR.Bits.PRIO5 -#define CAN4TXTBPR_PRIO6 _CAN4TXTBPR.Bits.PRIO6 -#define CAN4TXTBPR_PRIO7 _CAN4TXTBPR.Bits.PRIO7 -#define CAN4TXTBPR_PRIO _CAN4TXTBPR.MergedBits.grpPRIO - - -/*** BDMSTS - BDM Status Register; 0x0000FF01 ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte UNSEC :1; /* Unsecure */ - byte CLKSW :1; /* Clock switch */ - byte TRACE :1; /* TRACE1 BDM firmware command is being executed */ - byte SDV :1; /* Shift data valid */ - byte ENTAG :1; /* Tagging enable */ - byte BDMACT :1; /* BDM active status */ - byte ENBDM :1; /* Enable BDM */ - } Bits; -} BDMSTSSTR; -extern volatile BDMSTSSTR _BDMSTS @(0x0000FF01); -#define BDMSTS _BDMSTS.Byte -#define BDMSTS_UNSEC _BDMSTS.Bits.UNSEC -#define BDMSTS_CLKSW _BDMSTS.Bits.CLKSW -#define BDMSTS_TRACE _BDMSTS.Bits.TRACE -#define BDMSTS_SDV _BDMSTS.Bits.SDV -#define BDMSTS_ENTAG _BDMSTS.Bits.ENTAG -#define BDMSTS_BDMACT _BDMSTS.Bits.BDMACT -#define BDMSTS_ENBDM _BDMSTS.Bits.ENBDM - - -/*** BDMCCR - BDM CCR Holding Register; 0x0000FF06 ***/ -typedef union { - byte Byte; - struct { - byte CCR0 :1; /* BDM CCR Holding Bit 0 */ - byte CCR1 :1; /* BDM CCR Holding Bit 1 */ - byte CCR2 :1; /* BDM CCR Holding Bit 2 */ - byte CCR3 :1; /* BDM CCR Holding Bit 3 */ - byte CCR4 :1; /* BDM CCR Holding Bit 4 */ - byte CCR5 :1; /* BDM CCR Holding Bit 5 */ - byte CCR6 :1; /* BDM CCR Holding Bit 6 */ - byte CCR7 :1; /* BDM CCR Holding Bit 7 */ - } Bits; - struct { - byte grpCCR :8; - } MergedBits; -} BDMCCRSTR; -extern volatile BDMCCRSTR _BDMCCR @(0x0000FF06); -#define BDMCCR _BDMCCR.Byte -#define BDMCCR_CCR0 _BDMCCR.Bits.CCR0 -#define BDMCCR_CCR1 _BDMCCR.Bits.CCR1 -#define BDMCCR_CCR2 _BDMCCR.Bits.CCR2 -#define BDMCCR_CCR3 _BDMCCR.Bits.CCR3 -#define BDMCCR_CCR4 _BDMCCR.Bits.CCR4 -#define BDMCCR_CCR5 _BDMCCR.Bits.CCR5 -#define BDMCCR_CCR6 _BDMCCR.Bits.CCR6 -#define BDMCCR_CCR7 _BDMCCR.Bits.CCR7 -#define BDMCCR_CCR _BDMCCR.MergedBits.grpCCR - - -/*** BDMINR - BDM Internal Register Position Register; 0x0000FF07 ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte REG11 :1; /* Internal register map position */ - byte REG12 :1; /* Internal register map position */ - byte REG13 :1; /* Internal register map position */ - byte REG14 :1; /* Internal register map position */ - byte REG15 :1; /* Internal register map position */ - } Bits; - struct { - byte :1; - byte :1; - byte :1; - byte grpREG_11 :5; - } MergedBits; -} BDMINRSTR; -extern volatile BDMINRSTR _BDMINR @(0x0000FF07); -#define BDMINR _BDMINR.Byte -#define BDMINR_REG11 _BDMINR.Bits.REG11 -#define BDMINR_REG12 _BDMINR.Bits.REG12 -#define BDMINR_REG13 _BDMINR.Bits.REG13 -#define BDMINR_REG14 _BDMINR.Bits.REG14 -#define BDMINR_REG15 _BDMINR.Bits.REG15 -#define BDMINR_REG_11 _BDMINR.MergedBits.grpREG_11 -#define BDMINR_REG BDMINR_REG_11 - - - /* Watchdog reset macro */ -#ifdef _lint - #define __RESET_WATCHDOG() /* empty */ -#else - #define __RESET_WATCHDOG() {asm sta COPCTL;} /* Just write a byte to feed the dog */ -#endif - -#endif - -/* -** ################################################################### -** -** This file was created by UNIS Processor Expert 03.33 for -** the Motorola HCS12 series of microcontrollers. -** -** ################################################################### -*/ - diff --git a/Demo/HCS12_CodeWarrior_banked/CODE/PESL.h b/Demo/HCS12_CodeWarrior_banked/CODE/PESL.h deleted file mode 100644 index a01bb9a21..000000000 --- a/Demo/HCS12_CodeWarrior_banked/CODE/PESL.h +++ /dev/null @@ -1,52 +0,0 @@ -/* ================================================================================================================================= ** -** ================================================================================================================================= ** -** CONFIGURATION FILE FOR PESL LIBRARY ** -** ================================================================================================================================= ** -** ================================================================================================================================= */ - -#define _MC9S12A128_112 1 -#define _MC9S12A128_80 2 -#define _MC9S12A256_112 3 -#define _MC9S12A256_80 4 -#define _MC9S12A64_112 5 -#define _MC9S12A64_80 6 -#define _MC9S12C32_48 7 -#define _MC9S12C32_52 8 -#define _MC9S12C32_80 9 -#define _MC9S12D64_112 10 -#define _MC9S12D64_80 11 -#define _MC9S12DB128_112 12 -#define _MC9S12DG128_112 13 -#define _MC9S12DG128_80 14 -#define _MC9S12DG256_112 15 -#define _MC9S12DJ128_112 16 -#define _MC9S12DJ128_80 17 -#define _MC9S12DJ256_112 18 -#define _MC9S12DJ256_80 19 -#define _MC9S12DJ64_112 20 -#define _MC9S12DJ64_80 21 -#define _MC9S12DP256_112 22 -#define _MC9S12DT128_112 23 -#define _MC9S12DT256_112 24 -#define _MC9S12A32_80 25 -#define _MC9S12D32_80 26 -#define _MC9S12DP512_112 27 -#define _MC9S12A512_112 28 -#define _MC9S12E128_112 29 -#define _MC9S12E128_80 30 -#define _MC9S12E64_112 31 - - -/* Selected target MCU */ - -#define CPUtype _MC9S12DP256_112 - - -/* PESL library */ - -#pragma MESSAGE DISABLE C4000 /* WARNING C4000: Condition is always TRUE */ -#pragma MESSAGE DISABLE C4001 /* WARNING C4001: Condition is always FALSE */ - -#include "PESLlib.h" - - diff --git a/Demo/HCS12_CodeWarrior_banked/CODE/PE_Const.H b/Demo/HCS12_CodeWarrior_banked/CODE/PE_Const.H deleted file mode 100644 index c278f4a88..000000000 --- a/Demo/HCS12_CodeWarrior_banked/CODE/PE_Const.H +++ /dev/null @@ -1,50 +0,0 @@ -/** ################################################################### -** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. -** Filename : PE_Const.H -** Project : RTOSDemo -** Processor : MC9S12DP256BCPV -** Beantype : PE_Const -** Version : Driver 01.00 -** Compiler : Metrowerks HC12 C Compiler -** Date/Time : 13/06/2005, 20:14 -** Abstract : -** This bean "PE_Const" contains internal definitions -** of the constants. -** Settings : -** Contents : -** No public methods -** -** (c) Copyright UNIS, spol. s r.o. 1997-2002 -** UNIS, spol. s r.o. -** Jundrovska 33 -** 624 00 Brno -** Czech Republic -** http : www.processorexpert.com -** mail : info@processorexpert.com -** ###################################################################*/ - -#ifndef __PE_Const_H -#define __PE_Const_H - -/* Constants for detecting running mode */ -#define HIGH_SPEED 0 /* High speed */ -#define LOW_SPEED 1 /* Low speed */ -#define SLOW_SPEED 2 /* Slow speed */ - -/* Reset cause constants */ -#define RSTSRC_POR 1 /* Power-on reset */ -#define RSTSRC_PIN 8 /* External reset bit */ -#define RSTSRC_COP 4 /* COP reset */ -#define RSTSRC_ILOP 2 /* Illegal opcode reset */ -#define RSTSRC_ILAD 16 /* Illegal address reset */ -#define RSTSRC_LVI 32 /* Low voltage inhibit reset */ - -#endif /* _PE_Const_H */ -/* -** ################################################################### -** -** This file was created by UNIS Processor Expert 03.33 for -** the Motorola HCS12 series of microcontrollers. -** -** ################################################################### -*/ diff --git a/Demo/HCS12_CodeWarrior_banked/CODE/PE_Error.H b/Demo/HCS12_CodeWarrior_banked/CODE/PE_Error.H deleted file mode 100644 index 813974ecc..000000000 --- a/Demo/HCS12_CodeWarrior_banked/CODE/PE_Error.H +++ /dev/null @@ -1,53 +0,0 @@ -/** ################################################################### -** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. -** Filename : PE_Error.H -** Project : RTOSDemo -** Processor : MC9S12DP256BCPV -** Beantype : PE_Error -** Version : Driver 01.00 -** Compiler : Metrowerks HC12 C Compiler -** Date/Time : 13/06/2005, 20:14 -** Abstract : -** This bean "PE_Error" contains internal definitions -** of the error constants. -** Settings : -** Contents : -** No public methods -** -** (c) Copyright UNIS, spol. s r.o. 1997-2002 -** UNIS, spol. s r.o. -** Jundrovska 33 -** 624 00 Brno -** Czech Republic -** http : www.processorexpert.com -** mail : info@processorexpert.com -** ###################################################################*/ - -#ifndef __PE_Error_H -#define __PE_Error_H - -#define ERR_OK 0 /* OK */ -#define ERR_SPEED 1 /* This device does not work in the active speed mode. */ -#define ERR_RANGE 2 /* Parameter out of range. */ -#define ERR_VALUE 3 /* Parameter of incorrect value. */ -#define ERR_OVERFLOW 4 /* Timer overflow. */ -#define ERR_MATH 5 /* Overflow during evaluation. */ -#define ERR_ENABLED 6 /* Device is enabled. */ -#define ERR_DISABLED 7 /* Device is disabled. */ -#define ERR_BUSY 8 /* Device is busy. */ -#define ERR_NOTAVAIL 9 /* Requested value or method not available. */ -#define ERR_RXEMPTY 10 /* No data in receiver. */ -#define ERR_TXFULL 11 /* Transmitter is full. */ -#define ERR_BUSOFF 12 /* Bus not available. */ -#define ERR_OVERRUN 13 /* Overrun error is detected. */ -#define ERR_FRAMING 14 /* Framing error is detected. */ -#define ERR_PARITY 15 /* Parity error is detected. */ -#define ERR_NOISE 16 /* Noise error is detected. */ -#define ERR_IDLE 17 /* Idle error is detectes. */ -#define ERR_FAULT 18 /* Fault error is detected. */ -#define ERR_BREAK 19 /* Break char is received during communication. */ -#define ERR_CRC 20 /* CRC error is detected. */ -#define ERR_ARBITR 21 /* A node losts arbitration. This error occurs if two nodes start transmission at the same time. */ -#define ERR_PROTECT 22 /* Protection error is detected. */ - -#endif __PE_Error_H diff --git a/Demo/HCS12_CodeWarrior_banked/CODE/PE_Timer.C b/Demo/HCS12_CodeWarrior_banked/CODE/PE_Timer.C deleted file mode 100644 index c94f087a6..000000000 --- a/Demo/HCS12_CodeWarrior_banked/CODE/PE_Timer.C +++ /dev/null @@ -1,205 +0,0 @@ -/** ################################################################### -** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. -** Filename : PE_Timer.C -** Project : RTOSDemo -** Processor : MC9S12DP256BCPV -** Beantype : PE_Timer -** Version : Driver 01.00 -** Compiler : Metrowerks HC12 C Compiler -** Date/Time : 14/06/2005, 16:34 -** Abstract : -** This bean "PE_Timer" implements internal methods and definitions -** used by beans working with timers. -** Settings : -** Contents : -** No public methods -** -** (c) Copyright UNIS, spol. s r.o. 1997-2002 -** UNIS, spol. s r.o. -** Jundrovska 33 -** 624 00 Brno -** Czech Republic -** http : www.processorexpert.com -** mail : info@processorexpert.com -** ###################################################################*/ - - -/* MODULE PE_Timer. */ - -#include "PE_Timer.h" - - - -typedef unsigned long UINT32; - -typedef union { - UINT32 val; - struct { - unsigned short hi16,lo16; - } s; -} OP_UINT32; - -typedef struct { - unsigned short dummy; - UINT32 mid; -} M_UINT32; - -typedef struct { - UINT32 hi32, lo32; -} UINT64; - -typedef union { - UINT64 val; - M_UINT32 m; -} OP_UINT64; - -/* -** =================================================================== -** Method : PE_Timer_LngMul (bean PE_Timer) -** -** Description : -** This method is internal. It is used by Processor Expert -** only. -** =================================================================== -*/ -void PE_Timer_LngMul(dword va1, dword va2, dlong *var) -{ - OP_UINT32 *va = (OP_UINT32*)&va1; - OP_UINT32 *vb = (OP_UINT32*)&va2; - OP_UINT64 *vr = (OP_UINT64*)var; - - vr->val.hi32 = 0UL; - vr->val.lo32 = ((UINT32)va->s.lo16)*((UINT32)vb->s.lo16); - { - OP_UINT32 tmp; - - tmp.val = ((UINT32)va->s.lo16)*((UINT32)vb->s.hi16); - vr->m.mid += (UINT32)tmp.s.lo16; - vr->val.hi32 += (UINT32)tmp.s.hi16; - } - { - OP_UINT32 tmp; - - tmp.val = ((UINT32)va->s.hi16)*((UINT32)vb->s.lo16); - vr->m.mid += (UINT32)tmp.s.lo16; - vr->val.hi32 += (UINT32)tmp.s.hi16; - } - vr->val.hi32 += ((UINT32)va->s.hi16)*((UINT32)vb->s.hi16); -} - -/* -** =================================================================== -** Method : PE_Timer_LngHi1 (bean PE_Timer) -** -** Description : -** This method is internal. It is used by Processor Expert -** only. -** =================================================================== -*/ -bool PE_Timer_LngHi1(dword High, dword Low, word *Out) -{ - if ((High == 0) && ((Low >> 24) == 0)) - if ((Low & 0x80) != 0) { - if ((Low >> 8) < 0xFFFF) { - *Out = ((unsigned int)(Low >> 8))+1; - return FALSE; - } - } - else { - *Out = (unsigned int)(Low >> 8); - return FALSE; - } - *Out = (unsigned int)(Low >> 8); - return TRUE; -} - -/* -** =================================================================== -** Method : PE_Timer_LngHi2 (bean PE_Timer) -** -** Description : -** This method is internal. It is used by Processor Expert -** only. -** =================================================================== -*/ -bool PE_Timer_LngHi2(dword High, dword Low, word *Out) -{ - if (High == 0) - if ((Low & 0x8000) != 0) { - if ((Low >> 16) < 0xFFFF) { - *Out = ((unsigned int)(Low >> 16))+1; - return FALSE; - } - } - else { - *Out = (unsigned int)(Low >> 16); - return FALSE; - } - *Out = (unsigned int)(Low >> 16); - return TRUE; -} - -/* -** =================================================================== -** Method : PE_Timer_LngHi3 (bean PE_Timer) -** -** Description : -** This method is internal. It is used by Processor Expert -** only. -** =================================================================== -*/ -bool PE_Timer_LngHi3(dword High, dword Low, word *Out) -{ - if ((High >> 8) == 0) - if ((Low & 0x800000) != 0) { - if (((Low >> 24) | (High << 8)) < 0xFFFF) { - *Out = ((unsigned int)((Low >> 24) | (High << 8)))+1; - return FALSE; - } - } - else { - *Out = (unsigned int)((Low >> 24) | (High << 8)); - return FALSE; - } - *Out = (unsigned int)((Low >> 24) | (High << 8)); - return TRUE; -} - -/* -** =================================================================== -** Method : PE_Timer_LngHi4 (bean PE_Timer) -** -** Description : -** This method is internal. It is used by Processor Expert -** only. -** =================================================================== -*/ -bool PE_Timer_LngHi4(dword High, dword Low, word *Out) -{ - if ((High >> 16) == 0) - if ((Low & 0x80000000) != 0) { - if (High < 0xFFFF) { - *Out = ((unsigned int)High)+1; - return FALSE; - } - } - else { - *Out = (unsigned int)High; - return FALSE; - } - *Out = (unsigned int)High; - return TRUE; -} - - - -/* END PE_Timer. */ - -/* -** ################################################################### -** -** This file was created by UNIS Processor Expert 03.33 for -** the Motorola HCS12 series of microcontrollers. -** -** ################################################################### -*/ diff --git a/Demo/HCS12_CodeWarrior_banked/CODE/PE_Timer.H b/Demo/HCS12_CodeWarrior_banked/CODE/PE_Timer.H deleted file mode 100644 index 6ba554b94..000000000 --- a/Demo/HCS12_CodeWarrior_banked/CODE/PE_Timer.H +++ /dev/null @@ -1,97 +0,0 @@ -/** ################################################################### -** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. -** Filename : PE_Timer.H -** Project : RTOSDemo -** Processor : MC9S12DP256BCPV -** Beantype : PE_Timer -** Version : Driver 01.00 -** Compiler : Metrowerks HC12 C Compiler -** Date/Time : 14/06/2005, 16:34 -** Abstract : -** This bean "PE_Timer" implements internal methods and definitions -** used by beans working with timers. -** Settings : -** Contents : -** No public methods -** -** (c) Copyright UNIS, spol. s r.o. 1997-2002 -** UNIS, spol. s r.o. -** Jundrovska 33 -** 624 00 Brno -** Czech Republic -** http : www.processorexpert.com -** mail : info@processorexpert.com -** ###################################################################*/ -#ifndef __PE_Timer -#define __PE_Timer -/*Include shared modules, which are used for whole project*/ -#include "PE_types.h" -#include "PE_const.h" - -/* MODULE PE_Timer. */ - -void PE_Timer_LngMul(dword va1, dword va2, dlong *var); -/* -** =================================================================== -** Method : PE_Timer_LngMul (bean PE_Timer) -** -** Description : -** This method is internal. It is used by Processor Expert -** only. -** =================================================================== -*/ - -bool PE_Timer_LngHi1(dword Low, dword High, word *Out); -/* -** =================================================================== -** Method : PE_Timer_LngHi1 (bean PE_Timer) -** -** Description : -** This method is internal. It is used by Processor Expert -** only. -** =================================================================== -*/ - -bool PE_Timer_LngHi2(dword Low, dword High, word *Out); -/* -** =================================================================== -** Method : PE_Timer_LngHi2 (bean PE_Timer) -** -** Description : -** This method is internal. It is used by Processor Expert -** only. -** =================================================================== -*/ - -bool PE_Timer_LngHi3(dword Low, dword High, word *Out); -/* -** =================================================================== -** Method : PE_Timer_LngHi3 (bean PE_Timer) -** -** Description : -** This method is internal. It is used by Processor Expert -** only. -** =================================================================== -*/ - -bool PE_Timer_LngHi4(dword Low, dword High, word *Out); -/* -** =================================================================== -** Method : PE_Timer_LngHi4 (bean PE_Timer) -** -** Description : -** This method is internal. It is used by Processor Expert -** only. -** =================================================================== -*/ - - -#endif /* END PE_Timer. */ -/* -** ################################################################### -** -** This file was created by UNIS Processor Expert 03.33 for -** the Motorola HCS12 series of microcontrollers. -** -** ################################################################### -*/ diff --git a/Demo/HCS12_CodeWarrior_banked/CODE/PE_Types.H b/Demo/HCS12_CodeWarrior_banked/CODE/PE_Types.H deleted file mode 100644 index 196279ded..000000000 --- a/Demo/HCS12_CodeWarrior_banked/CODE/PE_Types.H +++ /dev/null @@ -1,87 +0,0 @@ -/** ################################################################### -** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. -** Filename : PE_Types.H -** Project : RTOSDemo -** Processor : MC9S12DP256BCPV -** Beantype : PE_Types -** Version : Driver 01.04 -** Compiler : Metrowerks HC12 C Compiler -** Date/Time : 13/06/2005, 20:14 -** Abstract : -** This bean "PE_Types" contains internal definitions -** of the types. -** Settings : -** Contents : -** No public methods -** -** (c) Copyright UNIS, spol. s r.o. 1997-2002 -** UNIS, spol. s r.o. -** Jundrovska 33 -** 624 00 Brno -** Czech Republic -** http : www.processorexpert.com -** mail : info@processorexpert.com -** ###################################################################*/ - -#ifndef __PE_Types_H -#define __PE_Types_H - -#define FALSE 0 -#define TRUE 1 - -/*Types definition*/ -typedef unsigned char bool; -typedef unsigned char byte; -typedef unsigned int word; -typedef unsigned long dword; -typedef unsigned long dlong[2]; -typedef void (*tIntFunc)(void); - -/* Motorola types */ -typedef unsigned char VUINT8; -typedef signed char VINT8; -typedef unsigned short int VUINT16; -typedef signed short int VINT16; -typedef unsigned long int VUINT32; - -#define in16(var,l,h) var = ((word)(l)) | (((word)(h)) << 8) -#define out16(l,h,val) { l = (byte)val; h = (byte)(val >> 8); } - -#define output(P, V) P = (V) -#define input(P) (P) - -#define __DI() { asm sei; } /* Disable global interrupts */ -#define __EI() { asm cli; } /* Enable global interrupts */ -#define EnterCritical() { __asm pshc; __asm sei; __asm movb 1,SP+,CCR_reg; } /* This macro is used by Processor Expert. It saves CCR register and disable global interrupts. */ -#define ExitCritical() { __asm movb CCR_reg, 1,-SP; __asm pulc; } /* This macro is used by Processor Expert. It restores CCR register saved in SaveStatusReg(). */ -/* obsolete definition for backward compatibility */ -#define SaveStatusReg() EnterCritical() -#define RestoreStatusReg() ExitCritical() - - -typedef struct { /* Black&White Image */ - word width; /* Image width */ - word height; /* Image height */ - byte *pixmap; /* Image pixel bitmap */ - word size; /* Image size */ - char *name; /* Image name */ -} TIMAGE; -typedef TIMAGE* PIMAGE ; /* Pointer to image */ - -/* 16-bit register (Motorola format - big endian) */ -typedef union { - word w; - struct { - byte high,low; - } b; -} TWREG; - -#endif /* __PE_Types_H */ -/* -** ################################################################### -** -** This file was created by UNIS Processor Expert 03.33 for -** the Motorola HCS12 series of microcontrollers. -** -** ################################################################### -*/ diff --git a/Demo/HCS12_CodeWarrior_banked/CODE/RTOSDemo.C b/Demo/HCS12_CodeWarrior_banked/CODE/RTOSDemo.C deleted file mode 100644 index 9466aabd3..000000000 --- a/Demo/HCS12_CodeWarrior_banked/CODE/RTOSDemo.C +++ /dev/null @@ -1,67 +0,0 @@ -/** ################################################################### -** Filename : RTOSDemo.C -** Project : RTOSDemo -** Processor : MC9S12DP256BCPV -** Version : Driver 01.05 -** Compiler : Metrowerks HC12 C Compiler -** Date/Time : 13/06/2005, 20:14 -** Abstract : -** Main module. -** Here is to be placed user's code. -** Settings : -** Contents : -** No public methods -** -** (c) Copyright UNIS, spol. s r.o. 1997-2002 -** UNIS, spol. s r.o. -** Jundrovska 33 -** 624 00 Brno -** Czech Republic -** http : www.processorexpert.com -** mail : info@processorexpert.com -** ###################################################################*/ -/* MODULE RTOSDemo */ - -/* Including used modules for compilling procedure */ -#include "Cpu.h" -#include "Events.h" -#include "TickTimer.h" -#include "Byte1.h" -#include "COM0.h" -/* Include shared modules, which are used for whole project */ -#include "PE_Types.h" -#include "PE_Error.h" -#include "PE_Const.h" -#include "IO_Map.h" - -extern void vMain( void ); - -void main(void) -{ - /*** Processor Expert internal initialization. DON'T REMOVE THIS CODE!!! ***/ - PE_low_level_init(); - /*** End of Processor Expert internal initialization. ***/ - - /*Write your code here*/ - - /* Just jump to the real main(). */ - __asm - { - jmp vMain - } - - - /*** Processor Expert end of main routine. DON'T MODIFY THIS CODE!!! ***/ - for(;;); - /*** Processor Expert end of main routine. DON'T WRITE CODE BELOW!!! ***/ -} /*** End of main routine. DO NOT MODIFY THIS TEXT!!! ***/ - -/* END RTOSDemo */ -/* -** ################################################################### -** -** This file was created by UNIS Processor Expert 03.33 for -** the Motorola HCS12 series of microcontrollers. -** -** ################################################################### -*/ diff --git a/Demo/HCS12_CodeWarrior_banked/CODE/RTOSDemo.PRM b/Demo/HCS12_CodeWarrior_banked/CODE/RTOSDemo.PRM deleted file mode 100644 index 3cc861ac5..000000000 --- a/Demo/HCS12_CodeWarrior_banked/CODE/RTOSDemo.PRM +++ /dev/null @@ -1,64 +0,0 @@ -/* -** ################################################################### -** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. -** Filename : RTOSDemo.PRM -** Project : RTOSDemo -** Processor : MC9S12DP256BCPV -** Compiler : Metrowerks HC12 C Compiler -** Date/Time : 19/06/2005, 15:54 -** Abstract : -** This file is used by the linker. It describes files to be linked, -** memory ranges, stack size, etc. For detailed description of the PRM file -** see CodeWarrior documentation. This file is generated by default. -** You can switch off generation by setting the property -** "Generate PRM file = no" on the "Build options" tab in CPU bean and then modify -** this file if needed. -** -** (c) Copyright UNIS, spol. s r.o. 1997-2002 -** UNIS, spol. s r.o. -** Jundrovska 33 -** 624 00 Brno -** Czech Republic -** http : www.processorexpert.com -** mail : info@processorexpert.com -** ################################################################### -*/ - -NAMES - -END - -SECTIONS - /* List of all sections specified on the "Build options" tab */ - RAM = READ_WRITE 0x00001000 TO 0x00003FFF; - ROM_C000 = READ_ONLY 0x0000C000 TO 0x0000C511; - ROM_4000 = READ_ONLY 0x00004000 TO 0x00004255; - ROM_PAGE30 = READ_ONLY 0x00308000 TO 0x00308255; - ROM_PAGE31 = READ_ONLY 0x00318000 TO 0x00318255; - ROM_PAGE32 = READ_ONLY 0x00328000 TO 0x00328255; - ROM_PAGE33 = READ_ONLY 0x00338000 TO 0x00338255; - ROM_PAGE34 = READ_ONLY 0x00348000 TO 0x00348255; - ROM_PAGE35 = READ_ONLY 0x00358000 TO 0x00358255; - ROM_PAGE36 = READ_ONLY 0x00368000 TO 0x00368255; - ROM_PAGE37 = READ_ONLY 0x00378000 TO 0x00378255; - ROM_PAGE38 = READ_ONLY 0x00388000 TO 0x00388255; - ROM_PAGE39 = READ_ONLY 0x00398000 TO 0x00398255; - ROM_PAGE3A = READ_ONLY 0x003A8000 TO 0x003A8255; - ROM_PAGE3B = READ_ONLY 0x003B8000 TO 0x003B8255; - ROM_PAGE3C = READ_ONLY 0x003C8000 TO 0x003C8255; - ROM_PAGE3D = READ_ONLY 0x003D8000 TO 0x003D8255; -END - -PLACEMENT - DEFAULT_RAM INTO RAM; - DEFAULT_ROM INTO ROM_PAGE30, ROM_PAGE31, ROM_PAGE32, ROM_PAGE33, ROM_PAGE34, ROM_PAGE35, ROM_PAGE36, -ROM_PAGE37, ROM_PAGE38, ROM_PAGE39, ROM_PAGE3A, ROM_PAGE3B, ROM_PAGE3C, ROM_PAGE3D; - _PRESTART, STARTUP, - ROM_VAR, STRINGS, - NON_BANKED, COPY INTO ROM_C000, ROM_4000; -END - -INIT _EntryPoint /* The entry point of the application. This function is generated into the CPU module. */ - -STACKSIZE 0x0080 /* Size of the system stack. Value can be changed on the "Build options" tab */ - diff --git a/Demo/HCS12_CodeWarrior_banked/CODE/TickTimer.C b/Demo/HCS12_CodeWarrior_banked/CODE/TickTimer.C deleted file mode 100644 index 5e735073e..000000000 --- a/Demo/HCS12_CodeWarrior_banked/CODE/TickTimer.C +++ /dev/null @@ -1,393 +0,0 @@ -/** ################################################################### -** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. -** Filename : TickTimer.C -** Project : RTOSDemo -** Processor : MC9S12DP256BCPV -** Beantype : TimerInt -** Version : Bean 02.063, Driver 01.05, CPU db: 2.87.283 -** Compiler : Metrowerks HC12 C Compiler -** Date/Time : 18/06/2005, 16:21 -** Abstract : -** This bean "TimerInt" implements a periodic interrupt. -** When the bean and its events are enabled, the "OnInterrupt" -** event is called periodically with the period that you specify. -** TimerInt supports also changing the period in runtime. -** The source of periodic interrupt can be timer compare or reload -** register or timer-overflow interrupt (of free running counter). -** Settings : -** Timer name : ECT (16-bit) -** Compare name : TC0 -** Counter shared : No -** -** High-speed CPU mode -** Prescaler : divide-by-8 -** Clock : 3124000 Hz -** Initial period/frequency -** Xtal ticks : 16000 -** microseconds : 1000 -** milliseconds : 1 -** seconds (real) : 0.0010000 -** Hz : 1000 -** kHz : 1 -** -** Runtime setting : period/frequency interval (continual setting) -** ticks : 16000 to 320000 ticks -** microseconds : 1000 to 20000 microseconds -** milliseconds : 1 to 20 milliseconds -** seconds (real) : 0.0010000 to 0.0200000 seconds -** Hz : 50 to 1000 Hz -** -** Initialization: -** Timer : Enabled -** Events : Enabled -** -** Timer registers -** Counter : TCNT [68] -** Mode : TIOS [64] -** Run : TSCR1 [70] -** Prescaler : TSCR2 [77] -** -** Compare registers -** Compare : TC0 [80] -** -** Flip-flop registers -** Mode : TCTL2 [73] -** Contents : -** Enable - byte TickTimer_Enable(void); -** SetPeriodTicks16 - byte TickTimer_SetPeriodTicks16(word Ticks); -** SetPeriodTicks32 - byte TickTimer_SetPeriodTicks32(dword Ticks); -** SetPeriodUS - byte TickTimer_SetPeriodUS(word Time); -** SetPeriodMS - byte TickTimer_SetPeriodMS(word Time); -** SetFreqHz - byte TickTimer_SetFreqHz(word Freq); -** -** (c) Copyright UNIS, spol. s r.o. 1997-2002 -** UNIS, spol. s r.o. -** Jundrovska 33 -** 624 00 Brno -** Czech Republic -** http : www.processorexpert.com -** mail : info@processorexpert.com -** ###################################################################*/ - - -/* MODULE TickTimer. */ - -#include "Events.h" -#include "TickTimer.h" - -/* Definition of DATA and CODE segments for this bean. User can specify where - these segments will be located on "Build options" tab of the selected CPU bean. */ -#pragma DATA_SEG TickTimer_DATA /* Data section for this module. */ -#pragma CODE_SEG TickTimer_CODE /* Code section for this module. */ - -static word CmpHighVal; /* Compare register value for high speed CPU mode */ - - -/* -** =================================================================== -** Method : SetCV (bean TimerInt) -** -** Description : -** This method is internal. It is used by Processor Expert -** only. -** =================================================================== -*/ -static void SetCV(word Val) -{ - if (Val == 0) /* If the given value is zero */ - Val = 65535; /* then change it to the maximal one */ - TC0 = Val; /* Store given value to the compare register */ - TC7 = Val; /* Store given value to the modulo register */ -} - -/* -** =================================================================== -** Method : SetPV (bean TimerInt) -** -** Description : -** This method is internal. It is used by Processor Expert -** only. -** =================================================================== -*/ -static void SetPV(byte Val) -{ - TSCR2_PR = Val; /* Store given value to the prescaler */ -} - -/* -** =================================================================== -** Method : HWEnDi (bean TimerInt) -** -** Description : -** This method is internal. It is used by Processor Expert -** only. -** =================================================================== -*/ -static void HWEnDi(void) -{ - TFLG1 = 1; /* Reset interrupt request flag */ - TIE_C0I = 1; /* Enable interrupt */ -} - -/* -** =================================================================== -** Method : TickTimer_Enable (bean TimerInt) -** -** Description : -** Enable the bean - it starts the timer. Events may be -** generated ("DisableEvent"/"EnableEvent"). -** Parameters : None -** Returns : -** --- - Error code, possible codes: -** ERR_OK - OK -** ERR_SPEED - This device does not work in -** the active speed mode -** =================================================================== -*/ -byte TickTimer_Enable(void) -{ - HWEnDi(); /* Enable the device */ - return ERR_OK; /* OK */ -} - -/* -** =================================================================== -** Method : TickTimer_SetPeriodTicks16 (bean TimerInt) -** -** Description : -** This method sets the new period of the generated events. -** The period is expressed in Xtal ticks as a 16-bit unsigned -** integer number. -** This method is available only if runtime setting type -** 'from interval' is selected in the Timing dialog box in -** Runtime setting area. -** Parameters : -** NAME - DESCRIPTION -** Ticks - Period to set [in Xtal ticks] -** (16000 to 65535 ticks) -** Returns : -** --- - Error code, possible codes: -** ERR_OK - OK -** ERR_SPEED - This device does not work in -** the active speed mode -** ERR_MATH - Overflow during evaluation -** ERR_RANGE - Parameter out of range -** =================================================================== -*/ -byte TickTimer_SetPeriodTicks16(word Ticks) -{ - dlong rtval; /* Result of two 32-bit numbers multiplication */ - word rtword; /* Result of 64-bit number division */ - - if (Ticks < 16000) /* Is the given value out of range? */ - return ERR_RANGE; /* If yes then error */ - PE_Timer_LngMul((dword)Ticks,838592365,&rtval); /* Multiply given value and high speed CPU mode coefficient */ - if (PE_Timer_LngHi4(rtval[0],rtval[1],&rtword)) /* Is the result greater or equal than 65536 ? */ - rtword = 65535; /* If yes then use maximal possible value */ - CmpHighVal = rtword; /* Store result (compare register value for high speed CPU mode) to the variable CmpHighVal */ - SetCV(CmpHighVal); /* Store appropriate value to the compare register according to the selected high speed CPU mode */ - return ERR_OK; /* OK */ -} - -/* -** =================================================================== -** Method : TickTimer_SetPeriodTicks32 (bean TimerInt) -** -** Description : -** This method sets the new period of the generated events. -** The period is expressed in Xtal ticks as a 32-bit unsigned -** integer number. -** This method is available only if runtime setting type -** 'from interval' is selected in the Timing dialog box in -** Runtime setting area. -** Parameters : -** NAME - DESCRIPTION -** Ticks - Period to set [in Xtal ticks] -** (16000 to 320000 ticks) -** Returns : -** --- - Error code, possible codes: -** ERR_OK - OK -** ERR_SPEED - This device does not work in -** the active speed mode -** ERR_MATH - Overflow during evaluation -** ERR_RANGE - Parameter out of range -** =================================================================== -*/ -byte TickTimer_SetPeriodTicks32(dword Ticks) -{ - dlong rtval; /* Result of two 32-bit numbers multiplication */ - word rtword; /* Result of 64-bit number division */ - - if ((Ticks > 320000) || (Ticks < 16000)) /* Is the given value out of range? */ - return ERR_RANGE; /* Range error */ - PE_Timer_LngMul(Ticks,838592365,&rtval); /* Multiply given value and high speed CPU mode coefficient */ - if (PE_Timer_LngHi4(rtval[0],rtval[1],&rtword)) /* Is the result greater or equal than 65536 ? */ - rtword = 65535; /* If yes then use maximal possible value */ - CmpHighVal = rtword; /* Store result (compare register value for high speed CPU mode) to the variable CmpHighVal */ - SetCV(CmpHighVal); /* Store appropriate value to the compare register according to the selected high speed CPU mode */ - return ERR_OK; /* OK */ -} - -/* -** =================================================================== -** Method : TickTimer_SetPeriodUS (bean TimerInt) -** -** Description : -** This method sets the new period of the generated events. -** The period is expressed in microseconds as a 16-bit -** unsigned integer number. -** This method is available only if runtime setting type -** 'from interval' is selected in the Timing dialog box in -** Runtime setting area. -** Parameters : -** NAME - DESCRIPTION -** Time - Period to set [in microseconds] -** (1000 to 20000 microseconds) -** Returns : -** --- - Error code, possible codes: -** ERR_OK - OK -** ERR_SPEED - This device does not work in -** the active speed mode -** ERR_MATH - Overflow during evaluation -** ERR_RANGE - Parameter out of range -** =================================================================== -*/ -byte TickTimer_SetPeriodUS(word Time) -{ - dlong rtval; /* Result of two 32-bit numbers multiplication */ - word rtword; /* Result of 64-bit number division */ - - if ((Time > 20000) || (Time < 1000)) /* Is the given value out of range? */ - return ERR_RANGE; /* If yes then error */ - PE_Timer_LngMul((dword)Time,52412023,&rtval); /* Multiply given value and high speed CPU mode coefficient */ - if (PE_Timer_LngHi3(rtval[0],rtval[1],&rtword)) /* Is the result greater or equal than 65536 ? */ - rtword = 65535; /* If yes then use maximal possible value */ - CmpHighVal = rtword; /* Store result (compare register value for high speed CPU mode) to the variable CmpHighVal */ - SetCV(CmpHighVal); /* Store appropriate value to the compare register according to the selected high speed CPU mode */ - return ERR_OK; /* OK */ -} - -/* -** =================================================================== -** Method : TickTimer_SetPeriodMS (bean TimerInt) -** -** Description : -** This method sets the new period of the generated events. -** The period is expressed in miliseconds as a 16-bit -** unsigned integer number. -** This method is available only if runtime setting type -** 'from interval' is selected in the Timing dialog box in -** Runtime setting area. -** Parameters : -** NAME - DESCRIPTION -** Time - Period to set [in miliseconds] -** (1 to 20 milliseconds) -** Returns : -** --- - Error code, possible codes: -** ERR_OK - OK -** ERR_SPEED - This device does not work in -** the active speed mode -** ERR_MATH - Overflow during evaluation -** ERR_RANGE - Parameter out of range -** =================================================================== -*/ -byte TickTimer_SetPeriodMS(word Time) -{ - dlong rtval; /* Result of two 32-bit numbers multiplication */ - word rtword; /* Result of 64-bit number division */ - - if ((Time > 20) || (Time < 1)) /* Is the given value out of range? */ - return ERR_RANGE; /* If yes then error */ - PE_Timer_LngMul((dword)Time,204734464,&rtval); /* Multiply given value and high speed CPU mode coefficient */ - if (PE_Timer_LngHi2(rtval[0],rtval[1],&rtword)) /* Is the result greater or equal than 65536 ? */ - rtword = 65535; /* If yes then use maximal possible value */ - CmpHighVal = rtword; /* Store result (compare register value for high speed CPU mode) to the variable CmpHighVal */ - SetCV(CmpHighVal); /* Store appropriate value to the compare register according to the selected high speed CPU mode */ - return ERR_OK; /* OK */ -} - -/* -** =================================================================== -** Method : TickTimer_SetFreqHz (bean TimerInt) -** -** Description : -** This method sets the new frequency of the generated -** events. The frequency is expressed in Hz as a 16-bit -** unsigned integer number. -** This method is available only if runtime setting type -** 'from interval' is selected in the Timing dialog box in -** Runtime setting area. -** Parameters : -** NAME - DESCRIPTION -** Freq - Frequency to set [in Hz] -** (50 to 1000 Hz) -** Returns : -** --- - Error code, possible codes: -** ERR_OK - OK -** ERR_SPEED - This device does not work in -** the active speed mode -** ERR_MATH - Overflow during evaluation -** ERR_RANGE - Parameter out of range -** =================================================================== -*/ -byte TickTimer_SetFreqHz(word Freq) -{ - dlong rtval; /* Result of two 32-bit numbers division */ - word rtword; /* Result of 64-bit number division */ - - if ((Freq > 1000) || (Freq < 50)) /* Is the given value out of range? */ - return ERR_RANGE; /* If yes then error */ - rtval[1] = 799744000 / (dword)Freq; /* Divide high speed CPU mode coefficient by the given value */ - rtval[0] = 0; /* Convert result to the type dlong */ - if (PE_Timer_LngHi1(rtval[0],rtval[1],&rtword)) /* Is the result greater or equal than 65536 ? */ - rtword = 65535; /* If yes then use maximal possible value */ - CmpHighVal = rtword; /* Store result (compare register value for high speed CPU mode) to the variable CmpHighVal */ - SetCV(CmpHighVal); /* Store appropriate value to the compare register according to the selected high speed CPU mode */ - return ERR_OK; /* OK */ -} - -/* -** =================================================================== -** Method : TickTimer_Init (bean TimerInt) -** -** Description : -** This method is internal. It is used by Processor Expert -** only. -** =================================================================== -*/ -void TickTimer_Init(void) -{ - CmpHighVal = 3124; /* Compare register value for high speed CPU mode */ - SetCV(CmpHighVal); /* Store appropriate value to the compare register according to the selected high speed CPU mode */ - SetPV(3); /* Set prescaler register according to the selected high speed CPU mode */ - HWEnDi(); /* Enable/disable device according to status flags */ -} - -/* -** =================================================================== -** Method : TickTimer_Interrupt (bean TimerInt) -** -** Description : -** This method is internal. It is used by Processor Expert -** only. -** =================================================================== -*/ -#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */ -__interrupt void TickTimer_Interrupt(void) -{ - TFLG1 = 1; /* Reset interrupt request flag */ - TickTimer_OnInterrupt(); /* Invoke user event */ -} - -#pragma CODE_SEG TickTimer_CODE /* Code section for this module. */ - -/* END TickTimer. */ - -/* -** ################################################################### -** -** This file was created by UNIS Processor Expert 03.33 for -** the Motorola HCS12 series of microcontrollers. -** -** ################################################################### -*/ diff --git a/Demo/HCS12_CodeWarrior_banked/CODE/TickTimer.H b/Demo/HCS12_CodeWarrior_banked/CODE/TickTimer.H deleted file mode 100644 index 8ddab4b3b..000000000 --- a/Demo/HCS12_CodeWarrior_banked/CODE/TickTimer.H +++ /dev/null @@ -1,276 +0,0 @@ -/** ################################################################### -** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. -** Filename : TickTimer.H -** Project : RTOSDemo -** Processor : MC9S12DP256BCPV -** Beantype : TimerInt -** Version : Bean 02.063, Driver 01.05, CPU db: 2.87.283 -** Compiler : Metrowerks HC12 C Compiler -** Date/Time : 18/06/2005, 16:21 -** Abstract : -** This bean "TimerInt" implements a periodic interrupt. -** When the bean and its events are enabled, the "OnInterrupt" -** event is called periodically with the period that you specify. -** TimerInt supports also changing the period in runtime. -** The source of periodic interrupt can be timer compare or reload -** register or timer-overflow interrupt (of free running counter). -** Settings : -** Timer name : ECT (16-bit) -** Compare name : TC0 -** Counter shared : No -** -** High-speed CPU mode -** Prescaler : divide-by-8 -** Clock : 3124000 Hz -** Initial period/frequency -** Xtal ticks : 16000 -** microseconds : 1000 -** milliseconds : 1 -** seconds (real) : 0.0010000 -** Hz : 1000 -** kHz : 1 -** -** Runtime setting : period/frequency interval (continual setting) -** ticks : 16000 to 320000 ticks -** microseconds : 1000 to 20000 microseconds -** milliseconds : 1 to 20 milliseconds -** seconds (real) : 0.0010000 to 0.0200000 seconds -** Hz : 50 to 1000 Hz -** -** Initialization: -** Timer : Enabled -** Events : Enabled -** -** Timer registers -** Counter : TCNT [68] -** Mode : TIOS [64] -** Run : TSCR1 [70] -** Prescaler : TSCR2 [77] -** -** Compare registers -** Compare : TC0 [80] -** -** Flip-flop registers -** Mode : TCTL2 [73] -** Contents : -** Enable - byte TickTimer_Enable(void); -** SetPeriodTicks16 - byte TickTimer_SetPeriodTicks16(word Ticks); -** SetPeriodTicks32 - byte TickTimer_SetPeriodTicks32(dword Ticks); -** SetPeriodUS - byte TickTimer_SetPeriodUS(word Time); -** SetPeriodMS - byte TickTimer_SetPeriodMS(word Time); -** SetFreqHz - byte TickTimer_SetFreqHz(word Freq); -** -** (c) Copyright UNIS, spol. s r.o. 1997-2002 -** UNIS, spol. s r.o. -** Jundrovska 33 -** 624 00 Brno -** Czech Republic -** http : www.processorexpert.com -** mail : info@processorexpert.com -** ###################################################################*/ - -#ifndef __TickTimer -#define __TickTimer - -/* MODULE TickTimer. */ - -#include "Cpu.h" - -#pragma CODE_SEG TickTimer_CODE /* Code section for this module. */ - -#define TickTimer_SPT16Min 16000 /* Lower bound of interval for method SetPeriodTicks16 */ -#define TickTimer_SPT16Max 65535 /* Upper bound of interval for method SetPeriodTicks16 */ -#define TickTimer_SPT32Min 16000 /* Lower bound of interval for method SetPeriodTicks32 */ -#define TickTimer_SPT32Max 320000 /* Upper bound of interval for method SetPeriodTicks32 */ -#define TickTimer_SPUSMin 1000 /* Lower bound of interval for method SetPeriodUS */ -#define TickTimer_SPUSMax 20000 /* Upper bound of interval for method SetPeriodUS */ -#define TickTimer_SPMSMin 1 /* Lower bound of interval for method SetPeriodMS */ -#define TickTimer_SPMSMax 20 /* Upper bound of interval for method SetPeriodMS */ -#define TickTimer_SFHzMin 50 /* Lower bound of interval for method SetFreqHz */ -#define TickTimer_SFHzMax 1000 /* Upper bound of interval for method SetFreqHz */ - - -byte TickTimer_Enable(void); -/* -** =================================================================== -** Method : TickTimer_Enable (bean TimerInt) -** -** Description : -** Enable the bean - it starts the timer. Events may be -** generated ("DisableEvent"/"EnableEvent"). -** Parameters : None -** Returns : -** --- - Error code, possible codes: -** ERR_OK - OK -** ERR_SPEED - This device does not work in -** the active speed mode -** =================================================================== -*/ - -byte TickTimer_SetPeriodTicks16(word Ticks); -/* -** =================================================================== -** Method : TickTimer_SetPeriodTicks16 (bean TimerInt) -** -** Description : -** This method sets the new period of the generated events. -** The period is expressed in Xtal ticks as a 16-bit unsigned -** integer number. -** This method is available only if runtime setting type -** 'from interval' is selected in the Timing dialog box in -** Runtime setting area. -** Parameters : -** NAME - DESCRIPTION -** Ticks - Period to set [in Xtal ticks] -** (16000 to 65535 ticks) -** Returns : -** --- - Error code, possible codes: -** ERR_OK - OK -** ERR_SPEED - This device does not work in -** the active speed mode -** ERR_MATH - Overflow during evaluation -** ERR_RANGE - Parameter out of range -** =================================================================== -*/ - -byte TickTimer_SetPeriodTicks32(dword Ticks); -/* -** =================================================================== -** Method : TickTimer_SetPeriodTicks32 (bean TimerInt) -** -** Description : -** This method sets the new period of the generated events. -** The period is expressed in Xtal ticks as a 32-bit unsigned -** integer number. -** This method is available only if runtime setting type -** 'from interval' is selected in the Timing dialog box in -** Runtime setting area. -** Parameters : -** NAME - DESCRIPTION -** Ticks - Period to set [in Xtal ticks] -** (16000 to 320000 ticks) -** Returns : -** --- - Error code, possible codes: -** ERR_OK - OK -** ERR_SPEED - This device does not work in -** the active speed mode -** ERR_MATH - Overflow during evaluation -** ERR_RANGE - Parameter out of range -** =================================================================== -*/ - -byte TickTimer_SetPeriodUS(word Time); -/* -** =================================================================== -** Method : TickTimer_SetPeriodUS (bean TimerInt) -** -** Description : -** This method sets the new period of the generated events. -** The period is expressed in microseconds as a 16-bit -** unsigned integer number. -** This method is available only if runtime setting type -** 'from interval' is selected in the Timing dialog box in -** Runtime setting area. -** Parameters : -** NAME - DESCRIPTION -** Time - Period to set [in microseconds] -** (1000 to 20000 microseconds) -** Returns : -** --- - Error code, possible codes: -** ERR_OK - OK -** ERR_SPEED - This device does not work in -** the active speed mode -** ERR_MATH - Overflow during evaluation -** ERR_RANGE - Parameter out of range -** =================================================================== -*/ - -byte TickTimer_SetPeriodMS(word Time); -/* -** =================================================================== -** Method : TickTimer_SetPeriodMS (bean TimerInt) -** -** Description : -** This method sets the new period of the generated events. -** The period is expressed in miliseconds as a 16-bit -** unsigned integer number. -** This method is available only if runtime setting type -** 'from interval' is selected in the Timing dialog box in -** Runtime setting area. -** Parameters : -** NAME - DESCRIPTION -** Time - Period to set [in miliseconds] -** (1 to 20 milliseconds) -** Returns : -** --- - Error code, possible codes: -** ERR_OK - OK -** ERR_SPEED - This device does not work in -** the active speed mode -** ERR_MATH - Overflow during evaluation -** ERR_RANGE - Parameter out of range -** =================================================================== -*/ - -byte TickTimer_SetFreqHz(word Freq); -/* -** =================================================================== -** Method : TickTimer_SetFreqHz (bean TimerInt) -** -** Description : -** This method sets the new frequency of the generated -** events. The frequency is expressed in Hz as a 16-bit -** unsigned integer number. -** This method is available only if runtime setting type -** 'from interval' is selected in the Timing dialog box in -** Runtime setting area. -** Parameters : -** NAME - DESCRIPTION -** Freq - Frequency to set [in Hz] -** (50 to 1000 Hz) -** Returns : -** --- - Error code, possible codes: -** ERR_OK - OK -** ERR_SPEED - This device does not work in -** the active speed mode -** ERR_MATH - Overflow during evaluation -** ERR_RANGE - Parameter out of range -** =================================================================== -*/ - -#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */ -__interrupt void TickTimer_Interrupt(void); -#pragma CODE_SEG TickTimer_CODE /* Code section for this module. */ -/* -** =================================================================== -** Method : TickTimer_Interrupt (bean TimerInt) -** -** Description : -** This method is internal. It is used by Processor Expert -** only. -** =================================================================== -*/ - -void TickTimer_Init(void); -/* -** =================================================================== -** Method : TickTimer_Init (bean TimerInt) -** -** Description : -** This method is internal. It is used by Processor Expert -** only. -** =================================================================== -*/ - -#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */ - -/* END TickTimer. */ - -#endif /* ifndef __TickTimer */ -/* -** ################################################################### -** -** This file was created by UNIS Processor Expert 03.33 for -** the Motorola HCS12 series of microcontrollers. -** -** ################################################################### -*/ diff --git a/Demo/HCS12_CodeWarrior_banked/CODE/Vectors.c b/Demo/HCS12_CodeWarrior_banked/CODE/Vectors.c deleted file mode 100644 index 633348f90..000000000 --- a/Demo/HCS12_CodeWarrior_banked/CODE/Vectors.c +++ /dev/null @@ -1,112 +0,0 @@ -/** ################################################################### -** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. -** Filename : Cpu.C -** Project : RTOSDemo -** Processor : MC9S12DP256BCPV -** Beantype : MC9S12DP256_112 -** Version : Bean 01.148, Driver 01.09, CPU db: 2.87.283 -** Compiler : Metrowerks HC12 C Compiler -** Date/Time : 16/06/2005, 19:18 -** Abstract : -** This bean "MC9S12DP256_112" implements properties, methods, -** and events of the CPU. -** Settings : -** -** Contents : -** EnableInt - void Cpu_EnableInt(void); -** DisableInt - void Cpu_DisableInt(void); -** -** (c) Copyright UNIS, spol. s r.o. 1997-2002 -** UNIS, spol. s r.o. -** Jundrovska 33 -** 624 00 Brno -** Czech Republic -** http : www.processorexpert.com -** mail : info@processorexpert.com -** ###################################################################*/ - - -#include "Cpu.h" -#include "TickTimer.h" -#include "Byte1.h" - -extern void near _EntryPoint(void); /* Startup routine */ -extern void near vPortTickInterrupt( void ); -extern void near vPortYield( void ); -extern void near vCOM0_ISR( void ); - -typedef void (*near tIsrFunc)(void); -const tIsrFunc _vect[] @0xFF80 = { /* Interrupt table */ - Cpu_Interrupt, /* 0 Default (unused) interrupt */ - Cpu_Interrupt, /* 1 Default (unused) interrupt */ - Cpu_Interrupt, /* 2 Default (unused) interrupt */ - Cpu_Interrupt, /* 3 Default (unused) interrupt */ - Cpu_Interrupt, /* 4 Default (unused) interrupt */ - Cpu_Interrupt, /* 5 Default (unused) interrupt */ - Cpu_Interrupt, /* 6 Default (unused) interrupt */ - Cpu_Interrupt, /* 7 Default (unused) interrupt */ - Cpu_Interrupt, /* 8 Default (unused) interrupt */ - Cpu_Interrupt, /* 9 Default (unused) interrupt */ - Cpu_Interrupt, /* 10 Default (unused) interrupt */ - Cpu_Interrupt, /* 11 Default (unused) interrupt */ - Cpu_Interrupt, /* 12 Default (unused) interrupt */ - Cpu_Interrupt, /* 13 Default (unused) interrupt */ - Cpu_Interrupt, /* 14 Default (unused) interrupt */ - Cpu_Interrupt, /* 15 Default (unused) interrupt */ - Cpu_Interrupt, /* 16 Default (unused) interrupt */ - Cpu_Interrupt, /* 17 Default (unused) interrupt */ - Cpu_Interrupt, /* 18 Default (unused) interrupt */ - Cpu_Interrupt, /* 19 Default (unused) interrupt */ - Cpu_Interrupt, /* 20 Default (unused) interrupt */ - Cpu_Interrupt, /* 21 Default (unused) interrupt */ - Cpu_Interrupt, /* 22 Default (unused) interrupt */ - Cpu_Interrupt, /* 23 Default (unused) interrupt */ - Cpu_Interrupt, /* 24 Default (unused) interrupt */ - Cpu_Interrupt, /* 25 Default (unused) interrupt */ - Cpu_Interrupt, /* 26 Default (unused) interrupt */ - Cpu_Interrupt, /* 27 Default (unused) interrupt */ - Cpu_Interrupt, /* 28 Default (unused) interrupt */ - Cpu_Interrupt, /* 29 Default (unused) interrupt */ - Cpu_Interrupt, /* 30 Default (unused) interrupt */ - Cpu_Interrupt, /* 31 Default (unused) interrupt */ - Cpu_Interrupt, /* 32 Default (unused) interrupt */ - Cpu_Interrupt, /* 33 Default (unused) interrupt */ - Cpu_Interrupt, /* 34 Default (unused) interrupt */ - Cpu_Interrupt, /* 35 Default (unused) interrupt */ - Cpu_Interrupt, /* 36 Default (unused) interrupt */ - Cpu_Interrupt, /* 37 Default (unused) interrupt */ - Cpu_Interrupt, /* 38 Default (unused) interrupt */ - Cpu_Interrupt, /* 39 Default (unused) interrupt */ - Cpu_Interrupt, /* 40 Default (unused) interrupt */ - Cpu_Interrupt, /* 41 Default (unused) interrupt */ - Cpu_Interrupt, /* 42 Default (unused) interrupt */ - vCOM0_ISR, /* Defined in Demo/serial/serial.c */ - Cpu_Interrupt, /* 44 Default (unused) interrupt */ - Cpu_Interrupt, /* 45 Default (unused) interrupt */ - Cpu_Interrupt, /* 46 Default (unused) interrupt */ - Cpu_Interrupt, /* 47 Default (unused) interrupt */ - Cpu_Interrupt, /* 48 Default (unused) interrupt */ - Cpu_Interrupt, /* 49 Default (unused) interrupt */ - Cpu_Interrupt, /* 50 Default (unused) interrupt */ - Cpu_Interrupt, /* 51 Default (unused) interrupt */ - Cpu_Interrupt, /* 52 Default (unused) interrupt */ - Cpu_Interrupt, /* 53 Default (unused) interrupt */ - Cpu_Interrupt, /* 54 Default (unused) interrupt */ - vPortTickInterrupt, /* The RTOS tick. */ - Cpu_Interrupt, /* 56 Default (unused) interrupt */ - Cpu_Interrupt, /* 57 Default (unused) interrupt */ - Cpu_Interrupt, /* 58 Default (unused) interrupt */ - vPortYield, /* RTOS yield software interrupt. */ - Cpu_Interrupt, /* 60 Default (unused) interrupt */ - Cpu_Interrupt, /* 61 Default (unused) interrupt */ - Cpu_Interrupt, /* 62 Default (unused) interrupt */ - _EntryPoint /* Reset vector */ - }; -/* -** ################################################################### -** -** This file was created by UNIS Processor Expert 03.33 for -** the Motorola HCS12 series of microcontrollers. -** -** ################################################################### -*/ diff --git a/Demo/HCS12_CodeWarrior_banked/C_Layout.hwl b/Demo/HCS12_CodeWarrior_banked/C_Layout.hwl deleted file mode 100644 index 3b16d98a4..000000000 --- a/Demo/HCS12_CodeWarrior_banked/C_Layout.hwl +++ /dev/null @@ -1,20 +0,0 @@ -OPEN source 0 0 60 39 -Source < attributes MARKS off -OPEN assembly 60 0 40 31 -Assembly < attributes ADR on,CODE off,ABSADR on,SYMB off,TOPPC 0xF88C -OPEN procedure 0 39 60 17 -Procedure < attributes VALUES on,TYPES off -OPEN register 60 31 40 25 -Register < attributes FORMAT AUTO,COMPLEMENT None -OPEN memory 60 56 40 22 -Memory < attributes FORMAT hex,COMPLEMENT None,WORD 1,ASC on,ADR on,ADDRESS 0x80 -OPEN data 0 56 60 22 -Data:1 < attributes SCOPE global,COMPLEMENT None,FORMAT Symb,MODE automatic,UPDATERATE 10,NAMEWIDTH 16 -OPEN data 0 78 60 22 -Data:2 < attributes SCOPE local,COMPLEMENT None,FORMAT Symb,MODE automatic,UPDATERATE 10,NAMEWIDTH 16 -OPEN command 60 78 40 22 -Command < attributes CACHESIZE 1000 -bckcolor 50331647 -font 'Courier New' 9 BLACK -AUTOSIZE on -ACTIVATE Data:2 Command Procedure Data:1 Source Register Assembly Memory diff --git a/Demo/HCS12_CodeWarrior_banked/DOC/RTOSDemo.sig b/Demo/HCS12_CodeWarrior_banked/DOC/RTOSDemo.sig deleted file mode 100644 index 8aea029d4..000000000 --- a/Demo/HCS12_CodeWarrior_banked/DOC/RTOSDemo.sig +++ /dev/null @@ -1,23 +0,0 @@ -================================================================= -This file was generated from Processor Expert 03.33 - project "RTOSDemo", 19/06/2005, 15:54 ------------------------------------------------------------------ -There is no signal defined in this project. - Hint: Signals may be defined in the Bean Inspector (advanced or expert view) -================================================================= - -================================================================= - SIGNAL LIST ------------------------------------------------------------------ - SIGNAL NAME => PIN NAME ------------------------------------------------------------------ -================================================================= - - -================================================================= - PIN LIST ------------------------------------------------------------------ - PIN NAME => SIGNAL NAME ------------------------------------------------------------------ -================================================================= - diff --git a/Demo/HCS12_CodeWarrior_banked/DOC/RTOSDemo.txt b/Demo/HCS12_CodeWarrior_banked/DOC/RTOSDemo.txt deleted file mode 100644 index 479e92c6c..000000000 --- a/Demo/HCS12_CodeWarrior_banked/DOC/RTOSDemo.txt +++ /dev/null @@ -1,43 +0,0 @@ -============================================================================= -List of methods in project: RTOSDemo - -THIS TEXT DESCRIPTION IS GENERATED BY THE TOOL. DO NOT MODIFY IT. -============================================================================= - -Module "TickTimer" (bean TimerInt) - TickTimer_Enable -Enable the bean - it starts the timer. Events may be generated ("DisableEvent"/"EnableEvent"). - TickTimer_SetPeriodTicks16 -This method sets the new period of the generated events. The period is expressed in CPU [ticks] - as a 16-bit unsigned integer number. This method is available only if runtime setting type 'from interval' is - selected in the in Runtime setting area. - TickTimer_SetPeriodTicks32 -This method sets the new period of the generated events. The period is expressed in CPU [ticks] - as a 32-bit unsigned integer number. This method is available only if runtime setting type 'from interval' is - selected in the in Runtime setting area. - TickTimer_SetPeriodUS -This method sets the new period of the generated events. The period is expressed in [microseconds] as - a 16-bit unsigned integer number. This method is available only if runtime setting type 'from interval' is - selected in the in Runtime setting area. - TickTimer_SetPeriodMS -This method sets the new period of the generated events. The period is expressed in [miliseconds] as - a 16-bit unsigned integer number. This method is available only if runtime setting type 'from interval' is - selected in the in Runtime setting area. - TickTimer_SetFreqHz -This method sets the new frequency of the generated events. The frequency is expressed in [Hz] as a - 16-bit unsigned integer number. This method is available only if runtime setting type 'from interval' is - selected in the in Runtime setting area. - -Module "Byte1" (bean ByteIO) - Byte1_PutBit -Put the specified value to the specified bit/pin of the Input/Output bean. If direction is [input] saves the - value to a memory or a register, this value will be written to the pin after switching to the output mode - - using [SetDir(TRUE)]. If direction is [output] writes the value to the pin. - Byte1_NegBit -Negate (invert) the specified bit of the Input/Output bean. It is the same as [PutBit(Bit,!GetBit(Bit))]. - -Module "COM0" (bean AsynchroSerial) - COM0_SetBaudRateMode -This method changes the channel communication speed (baud rate). This method can be used only if you - specify a list of possible period settings at design time (see - Runtime setting - from a - list of values). Each of these settings constitutes a mode and Processor Expert^[TM] assigns them a mode - identifier. The prescaler and compare values corresponding to each mode are calculated at design time. You may - switch modes at runtime by referring only to a mode identifier. No run-time calculations are performed, all the - calculations are performed at design time. - -Module "Cpu" (bean MC9S12DP256_112) - Cpu_EnableInt -Enable maskable interrupts - Cpu_DisableInt -Disable maskable interrupts - -============================================================================= diff --git a/Demo/HCS12_CodeWarrior_banked/FreeRTOSConfig.h b/Demo/HCS12_CodeWarrior_banked/FreeRTOSConfig.h deleted file mode 100644 index 25e193ab0..000000000 --- a/Demo/HCS12_CodeWarrior_banked/FreeRTOSConfig.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -#include /* common defines and macros */ -#include "TickTimer.h" - -/* This port requires the compiler to generate code for the BANKED memory -model. */ -#define BANKED_MODEL - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 1 -#define configUSE_TICK_HOOK 0 -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 80 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 10240 ) ) -#define configMAX_TASK_NAME_LEN ( 1 ) -#define configUSE_TRACE_FACILITY 0 -#define configUSE_16_BIT_TICKS 1 -#define configIDLE_SHOULD_YIELD 1 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* This parameter is normally required in order to set the RTOS tick timer. -This port is a bit different in that hardware setup uses the code generated by -the Processor Expert, making this definition obsolete. - -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 25000000 ) -*/ - - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 - - - - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/HCS12_CodeWarrior_banked/P&E_ICD.ini b/Demo/HCS12_CodeWarrior_banked/P&E_ICD.ini deleted file mode 100644 index 628984302..000000000 --- a/Demo/HCS12_CodeWarrior_banked/P&E_ICD.ini +++ /dev/null @@ -1,71 +0,0 @@ -[Environment Variables] -GENPATH={Compiler}lib\HC12c\src;{Compiler}lib\HC12c\include;{Compiler}lib\HC12c\lib -LIBPATH={Compiler}lib\HC12c\include -OBJPATH={Project}bin -TEXTPATH={Project}bin -ABSPATH={Project}bin - -[HI-WAVE] -Target=icd12 -Layout=C_layout.hwl -LoadDialogOptions=AUTOERASEANDFLASH -CPU=HC12 -MainFrame=2,3,-1,-1,-1,-1,54,54,1254,908 -TOOLBAR=57600 57601 32795 0 57635 57634 57637 0 57671 57669 0 32777 32776 32782 32780 32781 32778 0 32806 -AEFWarningDialog=FALSE - -[ICD12] -CMDFILE0=CMDFILE STARTUP ON ".\cmd\p&e_icd_startup.cmd" -CMDFILE1=CMDFILE RESET ON ".\cmd\p&e_icd_reset.cmd" -CMDFILE2=CMDFILE PRELOAD ON ".\cmd\p&e_icd_preload.cmd" -CMDFILE3=CMDFILE POSTLOAD ON ".\cmd\p&e_icd_postload.cmd" -CMDFILE4=CMDFILE VPPON ON ".\cmd\p&e_icd_vppon.cmd" -CMDFILE5=CMDFILE VPPOFF ON ".\cmd\p&e_icd_vppoff.cmd" -CMDFILE6=CMDFILE UNSECURE ON ".\cmd\P&E_ICD_erase_unsecure_hcs12.cmd" -MCUID=0x3C6 -CHIPSECURE=CHIPSECURE SETUP 0xFF0F 0x3 0x2 -BDMClockSpeed=14 -BNKA_MCUID03C6_BANKWINDOW0=BANKWINDOW PPAGE ON 0x8000..0xBFFF 0x30 16 0x30 -BNKA_MCUID03C6_BANKWINDOW1=BANKWINDOW DPAGE OFF 0x7000..0x7FFF 0x34 256 0x0 -BNKA_MCUID03C6_BANKWINDOW2=BANKWINDOW EPAGE OFF 0x400..0x7FF 0x36 256 0x0 -HWBPD_MCUID03C6_HWBPM0=HWBPM MODE AUTOMATIC BPM22BITS 0x28 SKIP_OFF -HWBPD_MCUID03C6_BKPT_REMAP0=HWBPM REMAP_22BITS RANGE 0x4000 0x7FFF 0x3E -HWBPD_MCUID03C6_BKPT_REMAP1=HWBPM REMAP_22BITS RANGE 0xC000 0xFFFF 0x3F -HWBPD_MCUID03C6_HWBPM1=HWBPM SET16BITS 0x0 0x0 0x0 0x0 -HWBPD_MCUID03C6_HWBPM2=HWBPM SET22BITS 0x0 0x0 0x0 0x0 -BDMAutoSpeed=0 -COMDEVICE=SETCOMM COMPORT USB "USB-PE5014402" -SETCLKSW=1 -DETECTRUNNING=0 -ISRDISABLEDSTEP=0 -SHOWPROT=1 -NV_PARAMETER_FILE=C:\devtools\Metrowerks\CodeWarrior CW12_V3.1\prog\FPP\mcu03C6.fpp -NV_SAVE_WSP=0 -NV_AUTO_ID=1 -DMM_MCUID03C6_MODULE0=Registers 0x0 0x400 1 4 0 2 1 1 -DMM_MCUID03C6_MODULE1=Ram 0x1000 0x3000 2 5 0 3 1 1 -DMM_MCUID03C6_MODULE2=Eeprom 0x0 0x1000 3 5 1 4 1 1 -DMM_MCUID03C6_MODULE3=BankedŁmemory 0x8000 0x2f4000 100 6 0 6 1 0 -DMM_MCUID03C6_MODULE4=BankedŁflash 0x308000 0xf4000 101 6 1 5 1 0 -DMM_MCUID03C6_MODULE5=UnbankedŁflashŁ4000 0x4000 0x4000 102 5 1 5 1 1 -DMM_MCUID03C6_MODULE6=UnbankedŁflashŁC000 0xc000 0x4000 103 5 1 5 1 1 -HOTPLUGGING=0 -REALTIMEHWBP=0 -NOREADWHILERUNNING=0 -RESYNCONCOPRESET=0 - -[Recent Applications File List] -File1=E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_banked\bin\P&E_ICD.abs -File2=E:\Dev\FreeRTOS\Demo\MC9S12DP256_CodeWarrior\bin\P&E_ICD.abs -File3= -File4= -LoadFlags1=4099 -LoadFlags2=4099 -LoadFlags3=0 -LoadFlags4=0 - -[Recent Layout File List] -File1=C_layout.hwl -File2= -File3= -File4= diff --git a/Demo/HCS12_CodeWarrior_banked/ParTest/ParTest.c b/Demo/HCS12_CodeWarrior_banked/ParTest/ParTest.c deleted file mode 100644 index cd2286e2d..000000000 --- a/Demo/HCS12_CodeWarrior_banked/ParTest/ParTest.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "portable.h" - -/* Processor Expert created headers. */ -#include "byte1.h" - -/* Demo application include files. */ -#include "partest.h" - -/*----------------------------------------------------------- - * Simple parallel port IO routines. - *-----------------------------------------------------------*/ - -void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) -{ - /* This function is required as it is called from the standard demo - application files. All it does however is call the Processor Expert - created function. */ - portENTER_CRITICAL(); - Byte1_PutBit( uxLED, !xValue ); - portEXIT_CRITICAL(); -} -/*-----------------------------------------------------------*/ - -void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) -{ - /* This function is required as it is called from the standard demo - application files. All it does however is call the processor Expert - created function. */ - portENTER_CRITICAL(); - Byte1_NegBit( uxLED ); - portEXIT_CRITICAL(); -} - - - diff --git a/Demo/HCS12_CodeWarrior_banked/RTOSDemo.G_C b/Demo/HCS12_CodeWarrior_banked/RTOSDemo.G_C deleted file mode 100644 index 7840d35f7..000000000 --- a/Demo/HCS12_CodeWarrior_banked/RTOSDemo.G_C +++ /dev/null @@ -1,500 +0,0 @@ -;Please do not modify this file! -;The file contains internal information about the Processor Expert project generation -[Options] -ProjectName=RTOSDemo -ProjectDirectory=E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_banked\ -DestEventsDirectory=CODE\ -DestDriversSubDirectory= -DestDocumentationDirectory=DOC\ -DestCompiledFilesSubDirectory= -DestFpgaSubDirectory= -DestTemporaryDirectory= -[GenFiles] -LinkerFileGenerated=Yes -MakefileGenerated=No -GenSharedModules=5 -Line=PE_Types -Line=PE_Error -Line=PE_Const -Line=IO_Map -Line=PE_Timer -ShrdHeaderAge0=852337107 -ShrdCodeAge0=-1 -ShrdAsemblAge0=-1 -ShrdHeaderAge1=852337107 -ShrdCodeAge1=-1 -ShrdAsemblAge1=-1 -ShrdHeaderAge2=852337107 -ShrdCodeAge2=-1 -ShrdAsemblAge2=-1 -ShrdHeaderAge3=852337107 -ShrdCodeAge3=852337107 -ShrdAsemblAge3=-1 -ShrdHeaderAge4=852395090 -ShrdCodeAge4=852395090 -ShrdAsemblAge4=-1 -GenExtraFiles=2 -Line=E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_banked\CODE\Vectors.c -Line=E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_banked\CODE\PESL.h -XtraAge0=852534276 -XtraAge1=852337108 -GenExtraFileType1=4 -GenExtraFileType0=4 -GenEventModules=1 -Line=Events -GenMethodsInEvents=0 -GenAllModules=10 -Line=Byte1 -Line=COM0 -Line=Cpu -Line=Events -Line=IO_Map -Line=PE_Const -Line=PE_Error -Line=PE_Timer -Line=PE_Types -Line=TickTimer -GenExternModules=0 -GenBeanModules=3 -Line=COM0 -Line=Byte1 -Line=TickTimer -SignalListFile=E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_banked\DOC\RTOSDemo.sig -DestinationCompiler=MetrowerksHC12CC -ProjectModificationStamp=28 - -[4] -Generated=Yes -GenCompName=Cpu -GenEventModule=Events -HeaderAge=852395091 -CodeAge=852656823 -AsemblAge=-1 -GenNumMethods=10 -SetStopMode=No -SetWaitMode=No -DisableInt=Yes -EnableInt=Yes -GetIntVect=No -SetIntVect=No -GetSpeedMode=No -SetSlowSpeed=No -SetLowSpeed=No -SetHighSpeed=No -GenNumEvents=4 -OnClockMonitorFail_Selected=1 -OnClockMonitorFail_Name=Cpu_OnClockMonitorFail -OnClockMonitorFail_Priority=interrupts disabled -OnIllegalOpcode_Selected=1 -OnIllegalOpcode_Name=Cpu_OnIllegalOpcode -OnIllegalOpcode_Priority=interrupts disabled -OnReset_Selected=1 -OnReset_Name=Cpu_OnReset -OnReset_Priority=interrupts disabled -OnSwINT_Selected=1 -OnSwINT_Name=Cpu_OnSwINT -OnSwINT_Priority=interrupts disabled -GenSmartUserChangesDetected_Header=No -GenSmartUserChangesDetected_Code=No -GenSmartUserChangesDetected_Asembl=No - -[6] -Generated=Yes -GenCompName=TickTimer -GenEventModule=Events -HeaderAge=852656822 -CodeAge=852656822 -AsemblAge=-1 -GenNumMethods=14 -SetFreqMHz=No -SetFreqkHz=No -SetFreqHz=Yes -SetPeriodReal=No -SetPeriodSec=No -SetPeriodMS=Yes -SetPeriodUS=Yes -SetPeriodTicks32=Yes -SetPeriodTicks16=Yes -SetPeriodMode=No -DisableEvent=No -EnableEvent=No -Disable=No -Enable=Yes -GenNumEvents=3 -BeforeNewSpeed_Selected=1 -BeforeNewSpeed_Name=TickTimer_BeforeNewSpeed -BeforeNewSpeed_Priority=interrupts disabled -AfterNewSpeed_Selected=1 -AfterNewSpeed_Name=TickTimer_AfterNewSpeed -AfterNewSpeed_Priority=interrupts disabled -OnInterrupt_Selected=2 -OnInterrupt_Name=TickTimer_OnInterrupt -OnInterrupt_Priority=same as interrupt -GenSmartUserChangesDetected_Header=No -GenSmartUserChangesDetected_Code=No -GenSmartUserChangesDetected_Asembl=No -GenMethodPos=19 -MethodPos0=Enable -MethodType=method -ModuleType=Header -LineBeg=92 -LineEnd=108 -MethodPos1=SetPeriodTicks16 -MethodType=method -ModuleType=Header -LineBeg=109 -LineEnd=134 -MethodPos2=SetPeriodTicks32 -MethodType=method -ModuleType=Header -LineBeg=135 -LineEnd=160 -MethodPos3=SetPeriodUS -MethodType=method -ModuleType=Header -LineBeg=161 -LineEnd=186 -MethodPos4=SetPeriodMS -MethodType=method -ModuleType=Header -LineBeg=187 -LineEnd=212 -MethodPos5=SetFreqHz -MethodType=method -ModuleType=Header -LineBeg=213 -LineEnd=238 -MethodPos6=Interrupt -MethodType=internal_method -ModuleType=Header -LineBeg=239 -LineEnd=251 -MethodPos7=Init -MethodType=internal_method -ModuleType=Header -LineBeg=252 -LineEnd=262 -MethodPos8=SetCV -MethodType=internal_method -ModuleType=Code -LineBeg=85 -LineEnd=101 -MethodPos9=SetPV -MethodType=internal_method -ModuleType=Code -LineBeg=102 -LineEnd=115 -MethodPos10=HWEnDi -MethodType=internal_method -ModuleType=Code -LineBeg=116 -LineEnd=130 -MethodPos11=Enable -MethodType=method -ModuleType=Code -LineBeg=131 -LineEnd=151 -MethodPos12=SetPeriodTicks16 -MethodType=method -ModuleType=Code -LineBeg=152 -LineEnd=190 -MethodPos13=SetPeriodTicks32 -MethodType=method -ModuleType=Code -LineBeg=191 -LineEnd=229 -MethodPos14=SetPeriodUS -MethodType=method -ModuleType=Code -LineBeg=230 -LineEnd=268 -MethodPos15=SetPeriodMS -MethodType=method -ModuleType=Code -LineBeg=269 -LineEnd=307 -MethodPos16=SetFreqHz -MethodType=method -ModuleType=Code -LineBeg=308 -LineEnd=347 -MethodPos17=Init -MethodType=internal_method -ModuleType=Code -LineBeg=348 -LineEnd=364 -MethodPos18=Interrupt -MethodType=internal_method -ModuleType=Code -LineBeg=365 -LineEnd=381 - -[7] -Generated=Yes -GenCompName=Byte1 -GenEventModule=Events -HeaderAge=852535625 -CodeAge=852535625 -AsemblAge=-1 -GenNumMethods=9 -NegBit=Yes -ClrBit=No -SetBit=No -PutBit=Yes -GetBit=No -PutVal=No -GetVal=No -SetDir=No -GetDir=No -GenNumEvents=0 -GenSmartUserChangesDetected_Header=No -GenSmartUserChangesDetected_Code=No -GenSmartUserChangesDetected_Asembl=No -GenMethodPos=5 -MethodPos0=PutBit -MethodType=method -ModuleType=Header -LineBeg=66 -LineEnd=82 -MethodPos1=NegBit -MethodType=method -ModuleType=Header -LineBeg=83 -LineEnd=97 -MethodPos2=GetMsk -MethodType=internal_method -ModuleType=Code -LineBeg=68 -LineEnd=83 -MethodPos3=PutBit -MethodType=method -ModuleType=Code -LineBeg=84 -LineEnd=111 -MethodPos4=NegBit -MethodType=method -ModuleType=Code -LineBeg=112 -LineEnd=133 - -[8] -Generated=Yes -GenCompName=COM0 -GenEventModule=Events -HeaderAge=852719863 -CodeAge=852719863 -AsemblAge=-1 -GenNumMethods=29 -SetDirection=No -Standby=No -LoopMode=No -SetIdle=No -TurnRxOff=No -TurnRxOn=No -SetTxBaudGenerator=No -SetRxBaudGenerator=No -TurnTxOff=No -TurnTxOn=No -SetAttentionMode=No -SetBreak=No -GetBreak=No -GetError=No -SetBaudRateMode=Yes -GetCharsInTxBuf=No -CharsInTxBuf=No -GetCharsInRxBuf=No -CharsInRxBuf=No -ClearTxBuf=No -ClearRxBuf=No -SendBlock=No -RecvBlock=No -SendChar=No -RecvChar=No -DisableEvent=No -EnableEvent=No -Disable=No -Enable=No -GenNumEvents=9 -BeforeNewSpeed_Selected=1 -BeforeNewSpeed_Name=COM0_BeforeNewSpeed -BeforeNewSpeed_Priority=interrupts disabled -AfterNewSpeed_Selected=1 -AfterNewSpeed_Name=COM0_AfterNewSpeed -AfterNewSpeed_Priority=interrupts disabled -OnError_Selected=1 -OnError_Name=COM0_OnError -OnError_Priority=same as interrupt -OnRxChar_Selected=1 -OnRxChar_Name=COM0_OnRxChar -OnRxChar_Priority=same as interrupt -OnTxChar_Selected=1 -OnTxChar_Name=COM0_OnTxChar -OnTxChar_Priority=same as interrupt -OnFullRxBuf_Selected=0 -OnFullRxBuf_Name=COM0_OnFullRxBuf -OnFullRxBuf_Priority=same as interrupt -OnFreeTxBuf_Selected=0 -OnFreeTxBuf_Name=COM0_OnFreeTxBuf -OnFreeTxBuf_Priority=same as interrupt -OnBreak_Selected=0 -OnBreak_Name=COM0_OnBreak -OnBreak_Priority=same as interrupt -OnIdle_Selected=1 -OnIdle_Name=COM0_OnIdle -OnIdle_Priority=same as interrupt -GenSmartUserChangesDetected_Header=No -GenSmartUserChangesDetected_Code=No -GenSmartUserChangesDetected_Asembl=No -GenMethodPos=11 -MethodPos0=SetBaudRateMode -MethodType=method -ModuleType=Header -LineBeg=123 -LineEnd=150 -MethodPos1=Interrupt -MethodType=internal_method -ModuleType=Header -LineBeg=151 -LineEnd=163 -MethodPos2=InterruptCs -MethodType=internal_method -ModuleType=Header -LineBeg=164 -LineEnd=164 -MethodPos3=Init -MethodType=internal_method -ModuleType=Header -LineBeg=165 -LineEnd=175 -MethodPos4=HWEnDi -MethodType=internal_method -ModuleType=Code -LineBeg=115 -LineEnd=130 -MethodPos5=InterruptRx -MethodType=internal_method -ModuleType=Code -LineBeg=131 -LineEnd=157 -MethodPos6=InterruptTx -MethodType=internal_method -ModuleType=Code -LineBeg=158 -LineEnd=175 -MethodPos7=InterruptError -MethodType=internal_method -ModuleType=Code -LineBeg=176 -LineEnd=200 -MethodPos8=Interrupt -MethodType=internal_method -ModuleType=Code -LineBeg=201 -LineEnd=221 -MethodPos9=SetBaudRateMode -MethodType=method -ModuleType=Code -LineBeg=222 -LineEnd=259 -MethodPos10=Init -MethodType=internal_method -ModuleType=Code -LineBeg=260 -LineEnd=284 - -[UsedSrcFiles] -SrcFile=Drivers\TimerInt.src=779379233 -SrcFile=Drivers\HCS12\TimerInt.drv=790330280 -SrcFile=Drivers\Common\Header.h=788035759 -SrcFile=Drivers\Common\TimerIntAbstract.Inc=697533454 -SrcFile=Drivers\Common\TimerIntSettings.Inc=662077596 -SrcFile=Drivers\HCS12\CreateCodeSection.prg=759717537 -SrcFile=Drivers\Common\TimerIntEnable.Inc=724722488 -SrcFile=Drivers\Common\GeneralMethod.inc=711812818 -SrcFile=Drivers\Common\GeneralParametersNone.inc=711813294 -SrcFile=Drivers\Common\GeneralDamage.inc=711813453 -SrcFile=Drivers\Common\TimerIntSetPeriodTicks16.Inc=724921621 -SrcFile=Drivers\Common\GeneralParameters.inc=711813750 -SrcFile=Drivers\Common\TimerIntSetPeriodTicks32.Inc=724921601 -SrcFile=Drivers\Common\TimerIntSetPeriodUS.Inc=724921676 -SrcFile=Drivers\Common\TimerIntSetPeriodMS.Inc=724921329 -SrcFile=Drivers\Common\TimerIntSetFreqHz.Inc=724921137 -SrcFile=Drivers\HCS12\CreateIntSection.prg=760697835 -SrcFile=Drivers\Common\TimerIntInterrupt.Inc=662077583 -SrcFile=Drivers\Common\GeneralInternal.inc=724263004 -SrcFile=Drivers\Common\Header.End=710308512 -SrcFile=Drivers\Common\TimerIntOnInterrupt.Inc=724722488 -SrcFile=Drivers\Common\GeneralEvent.inc=711816218 -SrcFile=Drivers\Common\GeneralReturnNothing.inc=711816104 -SrcFile=Drivers\Common\Header.C=788035759 -SrcFile=Drivers\HCS12\CreateDataSection.prg=759780817 -SrcFile=Drivers\Common\GeneralInternalGlobal.Inc=724263104 -SrcFile=Drivers\Common\InitReg8.prg=727217490 -SrcFile=Drivers\Common\InitReg8Enable.prg=783766675 -SrcFile=Drivers\ByteIO.src=779379247 -SrcFile=Drivers\HCS12\ByteIO.drv=786325143 -SrcFile=Drivers\Common\ByteIOAbstract.Inc=697533609 -SrcFile=Drivers\Common\ByteIOSettings.Inc=662077581 -SrcFile=Drivers\Common\UsedPins.inc=662077580 -SrcFile=Drivers\Common\ByteIOPutBit.Inc=662077581 -SrcFile=Drivers\Common\GeneralPutBit.inc=724263173 -SrcFile=Drivers\Common\ByteIONegBit.Inc=662077581 -SrcFile=Drivers\Common\GeneralNegBit.inc=724263119 -SrcFile=Drivers\AsynchroSerial.src=779379258 -SrcFile=Drivers\HCS12\AsynchroSerial.drv=790261986 -SrcFile=Drivers\Common\AsynchroSerialAbstract.Inc=697534037 -SrcFile=Drivers\Common\AsynchroSerialSettings.Inc=696025229 -SrcFile=Drivers\Common\UsedAsynchroPins.inc=730763605 -SrcFile=Drivers\Common\UsedBaudModes.inc=662077584 -SrcFile=Drivers\Common\AsynchroSerialSetBaudRateMode.Inc=777215290 -SrcFile=Drivers\Common\DataHeader.Inc=662077594 -SrcFile=Drivers\Common\DataHeader.End=662077594 -SrcFile=Drivers\Common\GenReg8InitInfo.prg=754344225 -SrcFile=Drivers\Common\GenReg8BitsInitInfo.prg=777356856 -SrcFile=Drivers\HCS12\PE_Types.drv=790261986 -SrcFile=Drivers\Common\PE_TypesAbstract.Inc=662077595 -SrcFile=Drivers\Common\PE_TypesSettings.Inc=662077595 -SrcFile=Drivers\HCS12\PE_Error.drv=744839008 -SrcFile=Drivers\Common\PE_ErrorAbstract.Inc=662077580 -SrcFile=Drivers\Common\ErrorDefinitions.Inc=781282486 -SrcFile=Drivers\HCS12\PE_Const.drv=744839020 -SrcFile=Drivers\Common\PE_ConstAbstract.Inc=662077595 -SrcFile=Drivers\Common\PE_ConstSettings.Inc=662077595 -SrcFile=Drivers\HCS12\IO_Map.drv=790392555 -SrcFile=Drivers\Common\IO_MapAbstract.Inc=662077601 -SrcFile=Drivers\Common\IO_MapSettings.Inc=662077601 -SrcFile=Drivers\HCS12\MC9S12DP256_112h.prg=788297414 -SrcFile=Drivers\HCS12\MC9S12DP256_112c.prg=787841633 -SrcFile=Drivers\HCS12\PE_Timer.drv=764054261 -SrcFile=Drivers\Common\PE_TimerConstants.Inc=662077594 -SrcFile=Drivers\Common\PE_TimerMethods.Inc=662077585 -SrcFile=Drivers\Common\PE_TimerAbstract.Inc=662077594 -SrcFile=Drivers\Common\PE_TimerSettings.Inc=662077581 -SrcFile=Drivers\Common\PE_TimerLngMul.Inc=662077581 -SrcFile=Drivers\Common\PE_TimerLngHi1.Inc=662077594 -SrcFile=Drivers\Common\PE_TimerLngHi2.Inc=662077594 -SrcFile=Drivers\Common\PE_TimerLngHi3.Inc=662077594 -SrcFile=Drivers\Common\PE_TimerLngHi4.Inc=662077594 -SrcFile=Drivers\MC9S12DP256_112.src=746163715 -SrcFile=Drivers\HCS12\MC9S12.drv=788297552 -SrcFile=Drivers\Common\MC9S12Abstract.Inc=786070990 -SrcFile=Drivers\Common\MC9S12Settings.Inc=786070990 -SrcFile=Drivers\Common\MC9S12DisableInt.Inc=786070990 -SrcFile=Drivers\Common\MC9S12EnableInt.Inc=786070990 -SrcFile=Drivers\Common\CommonInitialization.prg=760832797 -SrcFile=Drivers\Common\CommonRegInitialization.prg=785882407 -SrcFile=Drivers\Common\SetRegBits8.prg=775453568 -SrcFile=Drivers\Common\SetReg8.prg=776374479 -SrcFile=Drivers\Common\CommonEnabling.prg=783766630 -SrcFile=Drivers\Common\CommonRegEnabling.prg=785882407 -SrcFile=Drivers\HCS12\PESL.prg=790397020 -SrcFile=Drivers\Event.src=779379228 -SrcFile=Drivers\HCS12\Evnt.drv=763978411 -SrcFile=Drivers\Common\EvntAbstract.Inc=662077596 -SrcFile=Drivers\Common\EvntSettings.inc=662077580 -SrcFile=Drivers\Common\Header.In1=710699431 -SrcFile=Drivers\_PE_ProjectInfo.src=713322570 -SrcFile=Drivers\SW\_PE_ProjectInfo.drv=726426382 - -[_end_] diff --git a/Demo/HCS12_CodeWarrior_banked/RTOSDemo.dsk b/Demo/HCS12_CodeWarrior_banked/RTOSDemo.dsk deleted file mode 100644 index 23b1cd45e..000000000 --- a/Demo/HCS12_CodeWarrior_banked/RTOSDemo.dsk +++ /dev/null @@ -1,166 +0,0 @@ -[Version] -PE_DesktopFileVersion=819 - -[Desktop] -StartupPrj=E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_banked\RTOSDemo.pe - -[PE_IDE_PlugIn] - -[CpuExpert] - -[AppPanel] -AllFocusedNode=Cpu:MC9S12DP256BCPV -ConfigurationsInAllExpanded=No -CPUsInAllExpanded=Yes -FPGAsInAllExpanded=No -OperatingSystemInAllExpanded=Yes -BeansInAllExpanded=Yes -TasksInAllExpanded=No -ProgramsInAllExpanded=No -DocumentationInAllExpanded=No -PESLInAllExpanded=No -PESL_moduleInAllExpanded=No -ViewEnabledItemsOnly=No - -[CpuPanel] -Status=hiden -WindowState=NORMAL -Rect=[0|90|593|532] -CpuPanViewMode=Default - -[ErrorPanel] -Status=Visible -WindowState=NORMAL -Rect=[593|976|593|178] - -[ResourceMeter] -Status=hiden -WindowState=NORMAL -Rect=[593|976|593|178] - -[BeanSelector] -Status=Visible -WindowState=NORMAL -Rect=[-4|62|1608|1130] -BF_ForTgtCpuOnly=Yes -BF_LicensedOnly=Yes - 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-[EndOfChilds] -Value=Auto selected prescaler -[ItemState] -ItemSymbol=_Tmg -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=1000 Hz -RuntimeSetting=1 -InitValue=1000 Hz -Precision=5 -PrecInProc=Yes -LowLimit=50 Hz -HighLimit=1000 Hz -List=0 -UnitText=Hz -[ItemState] -ItemSymbol=SameValuesInAllModes -ReadOnly=No -UserReadOnly=No -BasAdvHid=EXPERT -Index=0 -Value=Yes -[ItemState] -ItemSymbol=EntireTimer -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Index=1 -Value=No -[ItemState] -ItemSymbol=_InitGrp -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=InitEnable -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=0 -Value=Yes -[ItemState] -ItemSymbol=InitEnableEvent -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Index=0 -Value=Yes - -[EndOfChilds] -[ItemState] -ItemSymbol=_SpeedGrp -ReadOnly=No -UserReadOnly=No -BasAdvHid=EXPERT - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=HighSpeed -ReadOnly=No -UserReadOnly=No -BasAdvHid=EXPERT -Index=0 -Value=Yes -[ItemState] -ItemSymbol=LowSpeed -ReadOnly=No -UserReadOnly=No -BasAdvHid=EXPERT -Index=1 -Value=No -[ItemState] -ItemSymbol=SlowSpeed -ReadOnly=No -UserReadOnly=No -BasAdvHid=EXPERT -Index=1 -Value=No - -[EndOfChilds] -[ItemState] -ItemSymbol=MirrorECTmoduleGrp -ReadOnly=No -UserReadOnly=No -BasAdvHid=EXPERT - -[Childs] -List=GrupItem - -[EndOfChilds] - -[Methods] -List=Method -[ItemState] -ItemSymbol=Enable -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=0 -Value=Yes -LastSelection=No -LastUserSel=yes -UsrMethodName=Enable -[ItemState] -ItemSymbol=Disable -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=Disable -[ItemState] -ItemSymbol=EnableEvent -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=EnableEvent -[ItemState] -ItemSymbol=DisableEvent -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=DisableEvent -[ItemState] -ItemSymbol=SetPeriodMode -ReadOnly=Yes -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=Yes -LastUserSel=never -UsrMethodName=SetPeriodMode -[ItemState] -ItemSymbol=SetPeriodTicks16 -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=0 -Value=Yes -LastSelection=Yes -LastUserSel=yes -UsrMethodName=SetPeriodTicks16 -[ItemState] -ItemSymbol=SetPeriodTicks32 -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=0 -Value=Yes -LastSelection=Yes -LastUserSel=yes -UsrMethodName=SetPeriodTicks32 -[ItemState] -ItemSymbol=SetPeriodUS -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=0 -Value=Yes -LastSelection=Yes -LastUserSel=yes -UsrMethodName=SetPeriodUS -[ItemState] -ItemSymbol=SetPeriodMS -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=0 -Value=Yes -LastSelection=Yes -LastUserSel=yes -UsrMethodName=SetPeriodMS -[ItemState] -ItemSymbol=SetPeriodSec -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=SetPeriodSec -[ItemState] -ItemSymbol=SetPeriodReal -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=SetPeriodReal -[ItemState] -ItemSymbol=SetFreqHz -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=0 -Value=Yes -LastSelection=No -LastUserSel=yes -UsrMethodName=SetFreqHz -[ItemState] -ItemSymbol=SetFreqkHz -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=SetFreqkHz -[ItemState] -ItemSymbol=SetFreqMHz -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=SetFreqMHz - -[Events] -List=Event -[ItemState] -ItemSymbol=EventModule -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Value=Events -[ItemState] -ItemSymbol=BeforeNewSpeed -ReadOnly=No -UserReadOnly=No -BasAdvHid=EXPERT -Value=No - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=Name -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=TickTimer_BeforeNewSpeed - -[EndOfChilds] -LastSelection=No -LastUserSel=no -[ItemState] -ItemSymbol=AfterNewSpeed -ReadOnly=No -UserReadOnly=No -BasAdvHid=EXPERT -Value=No - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=Name -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=TickTimer_AfterNewSpeed - -[EndOfChilds] -LastSelection=No -LastUserSel=no -[ItemState] -ItemSymbol=OnInterrupt -ReadOnly=Yes -UserReadOnly=No -BasAdvHid=BASIC -Value=Yes - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=Name -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=TickTimer_OnInterrupt -[ItemState] -ItemSymbol=Priority -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Value=same as interrupt - -[EndOfChilds] -LastSelection=No -LastUserSel=always - -[ByteIO:Byte1] -CompNumb=7 -CompEnabled=Yes -GenCodeMode=CHECK_n_WRITE -IconName=BYTEIO -Comment=0 -Template= - -[Properties] -List=Property -[ItemState] -ItemSymbol=DeviceName -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Value=Byte1 -[ItemState] -ItemSymbol=_Port -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=B -SharedPrphMode=No -[ItemState] -ItemSymbol=PortSignal -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Value= -[ItemState] -ItemSymbol=PullMode -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -TypeSpecNameState=typePULL -Index=5 -[ItemState] -ItemSymbol=ODE -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=0 -[ItemState] -ItemSymbol=Dir -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -[ItemState] -ItemSymbol=_InitGrp -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=InitDir -ReadOnly=Yes -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -[ItemState] -ItemSymbol=InitValue -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=255 -Base=3 - -[EndOfChilds] -[ItemState] -ItemSymbol=SafeMode -ReadOnly=Yes -UserReadOnly=No -BasAdvHid=ADVANCED -Index=0 -Value=Yes -[ItemState] -ItemSymbol=Reduce -ReadOnly=No -UserReadOnly=No -BasAdvHid=EXPERT - -[Childs] -List=GrupItem - -[EndOfChilds] -[ItemState] -ItemSymbol=LEDdrive -ReadOnly=No -UserReadOnly=No -BasAdvHid=EXPERT - -[Childs] -List=GrupItem - -[EndOfChilds] - -[Methods] -List=Method -[ItemState] -ItemSymbol=GetDir -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=GetDir -[ItemState] -ItemSymbol=SetDir -ReadOnly=Yes -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=Yes -LastUserSel=never -UsrMethodName=SetDir -[ItemState] -ItemSymbol=GetVal -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=GetVal -[ItemState] -ItemSymbol=PutVal -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=PutVal -[ItemState] -ItemSymbol=GetBit -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=GetBit -[ItemState] -ItemSymbol=PutBit -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=0 -Value=Yes -LastSelection=No -LastUserSel=yes -UsrMethodName=PutBit -[ItemState] -ItemSymbol=SetBit -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=SetBit -[ItemState] -ItemSymbol=ClrBit -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=ClrBit -[ItemState] -ItemSymbol=NegBit -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=0 -Value=Yes -LastSelection=No -LastUserSel=yes -UsrMethodName=NegBit - -[Events] -List=Event -[ItemState] -ItemSymbol=EventModule -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Value=Events - -[AsynchroSerial:COM0] -CompNumb=8 -CompEnabled=Yes -GenCodeMode=CHECK_n_WRITE -IconName=PHONE -Comment=0 -Template= - -[Properties] -List=Property -[ItemState] -ItemSymbol=DeviceName -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Value=COM0 -[ItemState] -ItemSymbol=Ser -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=SCI0 -SharedPrphMode=No -[ItemState] -ItemSymbol=IntService -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=Yes - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=SpecInt -ReadOnly=Yes -UserReadOnly=No -BasAdvHid=ADVANCED -Value= -SharedPrphMode=No -[ItemState] -ItemSymbol=InpInt -ReadOnly=Yes -UserReadOnly=No -BasAdvHid=ADVANCED -Value=INT_SCI0 -SharedPrphMode=No -[ItemState] -ItemSymbol=InitPriority -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=medium priority -[ItemState] -ItemSymbol=OutInt -ReadOnly=Yes -UserReadOnly=No -BasAdvHid=ADVANCED -Value=INT_SCI0 -SharedPrphMode=No -[ItemState] -ItemSymbol=IntTxDPriority -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=low priority -[ItemState] -ItemSymbol=DSPgrp1 -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=ErrInt -ReadOnly=Yes -UserReadOnly=No -BasAdvHid=ADVANCED -Value= -SharedPrphMode=No -[ItemState] -ItemSymbol=IntErrorPriority -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=medium priority -[ItemState] -ItemSymbol=IdleInt -ReadOnly=Yes -UserReadOnly=No -BasAdvHid=ADVANCED -Value= -SharedPrphMode=No -[ItemState] -ItemSymbol=IntIdlePriority -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=medium priority - -[EndOfChilds] -[ItemState] -ItemSymbol=InpBufferSize -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=0 -Base=2 -[ItemState] -ItemSymbol=OutBufferSize -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=0 -Base=2 -[ItemState] -ItemSymbol=_HandshakeGrp -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=CTSsupport -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Value=No - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=CtsHardwareRequired -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -[ItemState] -ItemSymbol=Cts -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value= -SharedPrphMode=No -[ItemState] -ItemSymbol=CtsSignal -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Value= -[ItemState] -ItemSymbol=CtsInt -ReadOnly=Yes -UserReadOnly=No -BasAdvHid=BASIC -Value= -SharedPrphMode=No -[ItemState] -ItemSymbol=IntCtsPriority -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=medium priority - -[EndOfChilds] -[ItemState] -ItemSymbol=RTSsupport -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Value=No - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=RtsHardwareRequired -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -[ItemState] -ItemSymbol=Rts -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value= -SharedPrphMode=No -[ItemState] -ItemSymbol=RTSpinSignal -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Value= -[ItemState] -ItemSymbol=RtsBufferSize -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=1 -Base=2 - -[EndOfChilds] - -[EndOfChilds] - -[EndOfChilds] -[ItemState] -ItemSymbol=_SettingsGrp -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=SerParity -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=0 -[ItemState] -ItemSymbol=SerWidth -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=4 -[ItemState] -ItemSymbol=SerStopBit -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=0 -[ItemState] -ItemSymbol=DSPgrp10 -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=Mode -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=0 - -[EndOfChilds] -[ItemState] -ItemSymbol=Receiver -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=Yes - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=Inp -ReadOnly=Yes -UserReadOnly=No -BasAdvHid=BASIC -Value=PS0_RxD0 -SharedPrphMode=No -[ItemState] -ItemSymbol=RxDpinSignal -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Value= - -[EndOfChilds] -[ItemState] -ItemSymbol=Transmitter -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=Yes - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=Out -ReadOnly=Yes -UserReadOnly=No -BasAdvHid=BASIC -Value=PS1_TxD0 -SharedPrphMode=No -[ItemState] -ItemSymbol=TxDpinSignal -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Value= - -[EndOfChilds] -[ItemState] -ItemSymbol=_BdRate -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=38400 baud -RuntimeSetting=2 -InitValue=38400 baud -Precision=1.5 -PrecInProc=Yes -LowLimit= -HighLimit= -List=3 -Line=19200 baud -Line=9600 baud -Line=4800 baud -UnitText=baud -[ItemState] -ItemSymbol=SerBreak -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Index=1 -Value=No -[ItemState] -ItemSymbol=HC08grp -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=WakeupCond -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Index=1 - -[EndOfChilds] -[ItemState] -ItemSymbol=HC08grp0 -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=TxPolarity -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Index=1 - -[EndOfChilds] -[ItemState] -ItemSymbol=HCS12grp -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=WakeupCondHCS12 -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Index=1 -[ItemState] -ItemSymbol=StopInWait -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=0 -Value=Yes -[ItemState] -ItemSymbol=BreakLength -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Index=0 - -[EndOfChilds] -[ItemState] -ItemSymbol=DSPgrp -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=StopInWaitDSP -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No - -[EndOfChilds] -[ItemState] -ItemSymbol=HCS08grp -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=StopInWaitHCS08 -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=0 -Value=Yes - -[EndOfChilds] -[ItemState] -ItemSymbol=HCS08_HCS12grp -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=SCIOutMode -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=0 - -[Childs] -List=EnmGrpItm -[ItemState] -ItemSymbol=TxDPinDirection -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=0 - -[EndOfChilds] - -[EndOfChilds] -[ItemState] -ItemSymbol=HCS08grp0 -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=IdleMode -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=0 - -[EndOfChilds] -[ItemState] -ItemSymbol=ESCIGrp -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=LINsetting -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Index=0 -[ItemState] -ItemSymbol=ArbiterMode -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=0 -[ItemState] -ItemSymbol=ArbiterClock -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 - -[EndOfChilds] -[ItemState] -ItemSymbol=ESCILINGrp -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=BreakSetting -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Index=0 - -[EndOfChilds] -[ItemState] -ItemSymbol=IRSCIGrp -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=InfraredSCI -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=No - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=SCINarrowPulse -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=0 - -[EndOfChilds] - -[EndOfChilds] - -[EndOfChilds] -[ItemState] -ItemSymbol=COP8grp -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=Attention -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Index=1 -Value=No -[ItemState] -ItemSymbol=ClockPin -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=No - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=Clk -ReadOnly=Yes -UserReadOnly=No -BasAdvHid=BASIC -Value= -SharedPrphMode=No -[ItemState] -ItemSymbol=ClkPinSignal -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value= -[ItemState] -ItemSymbol=ClockPinDirection -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Index=0 -[ItemState] -ItemSymbol=BaudSource -ReadOnly=No -UserReadOnly=No -BasAdvHid=EXPERT - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=TxBaudSource -ReadOnly=No -UserReadOnly=No -BasAdvHid=EXPERT -Index=0 -[ItemState] -ItemSymbol=RxBaudSource -ReadOnly=No -UserReadOnly=No -BasAdvHid=EXPERT -Index=0 - -[EndOfChilds] - -[EndOfChilds] - -[EndOfChilds] -[ItemState] -ItemSymbol=_InitializationGrp -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=InitEnable -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=0 -Value=Yes -[ItemState] -ItemSymbol=InitEnableEvents -ReadOnly=Yes -UserReadOnly=No -BasAdvHid=ADVANCED -Index=0 -Value=Yes - -[EndOfChilds] -[ItemState] -ItemSymbol=_SpeedGrp -ReadOnly=No -UserReadOnly=No -BasAdvHid=EXPERT - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=HighSpeed -ReadOnly=No -UserReadOnly=No -BasAdvHid=EXPERT -Index=0 -Value=Yes -[ItemState] -ItemSymbol=LowSpeed -ReadOnly=No -UserReadOnly=No -BasAdvHid=EXPERT -Index=1 -Value=No -[ItemState] -ItemSymbol=SlowSpeed -ReadOnly=No -UserReadOnly=No -BasAdvHid=EXPERT -Index=1 -Value=No - -[EndOfChilds] - -[Methods] -List=Method -[ItemState] -ItemSymbol=Enable -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=Enable -[ItemState] -ItemSymbol=Disable -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=Disable -[ItemState] -ItemSymbol=EnableEvent -ReadOnly=Yes -UserReadOnly=No -BasAdvHid=ADVANCED -Index=1 -Value=No -LastSelection=No -LastUserSel=never -UsrMethodName=EnableEvent -[ItemState] -ItemSymbol=DisableEvent -ReadOnly=Yes -UserReadOnly=No -BasAdvHid=ADVANCED -Index=1 -Value=No -LastSelection=No -LastUserSel=never -UsrMethodName=DisableEvent -[ItemState] -ItemSymbol=RecvChar -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=RecvChar -[ItemState] -ItemSymbol=SendChar -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=SendChar -[ItemState] -ItemSymbol=RecvBlock -ReadOnly=Yes -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=No -LastUserSel=never -UsrMethodName=RecvBlock -[ItemState] -ItemSymbol=SendBlock -ReadOnly=Yes -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=No -LastUserSel=never -UsrMethodName=SendBlock -[ItemState] -ItemSymbol=ClearRxBuf -ReadOnly=Yes -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=No -LastUserSel=never -UsrMethodName=ClearRxBuf -[ItemState] -ItemSymbol=ClearTxBuf -ReadOnly=Yes -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=No -LastUserSel=never -UsrMethodName=ClearTxBuf -[ItemState] -ItemSymbol=CharsInRxBuf -ReadOnly=No -UserReadOnly=No -BasAdvHid=EXPERT -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=CharsInRxBuf -[ItemState] -ItemSymbol=GetCharsInRxBuf -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=GetCharsInRxBuf -[ItemState] -ItemSymbol=CharsInTxBuf -ReadOnly=No -UserReadOnly=No -BasAdvHid=EXPERT -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=CharsInTxBuf -[ItemState] -ItemSymbol=GetCharsInTxBuf -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=GetCharsInTxBuf -[ItemState] -ItemSymbol=SetBaudRateMode -ReadOnly=Yes -UserReadOnly=No -BasAdvHid=BASIC -Index=0 -Value=Yes -LastSelection=Yes -LastUserSel=always -UsrMethodName=SetBaudRateMode -[ItemState] -ItemSymbol=GetError -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=GetError -[ItemState] -ItemSymbol=GetBreak -ReadOnly=Yes -UserReadOnly=No -BasAdvHid=ADVANCED -Index=1 -Value=No -LastSelection=Yes -LastUserSel=never -UsrMethodName=GetBreak -[ItemState] -ItemSymbol=CPUCond2 -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=SetBreak0 -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Index=0 -Value=Yes -LastSelection=No -LastUserSel=yes -UsrMethodName=SetBreak - -[EndOfChilds] -[ItemState] -ItemSymbol=SetBreak -ReadOnly=Yes -UserReadOnly=No -BasAdvHid=ADVANCED -Index=1 -Value=No -LastSelection=Yes -LastUserSel=never -UsrMethodName=SetBreak -[ItemState] -ItemSymbol=SetAttentionMode -ReadOnly=No -UserReadOnly=No -BasAdvHid=@ HIDDEN @ -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=SetAttentionMode -[ItemState] -ItemSymbol=TurnTxOn -ReadOnly=No -UserReadOnly=No -BasAdvHid=EXPERT -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=TurnTxOn -[ItemState] -ItemSymbol=TurnTxOff -ReadOnly=No -UserReadOnly=No -BasAdvHid=EXPERT -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=TurnTxOff -[ItemState] -ItemSymbol=SetRxBaudGenerator -ReadOnly=No -UserReadOnly=No -BasAdvHid=@ HIDDEN @ -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=SetRxBaudGenerator -[ItemState] -ItemSymbol=SetTxBaudGenerator -ReadOnly=No -UserReadOnly=No -BasAdvHid=@ HIDDEN @ -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=SetTxBaudGenerator -[ItemState] -ItemSymbol=CPUCond -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=TurnRxOn -ReadOnly=No -UserReadOnly=No -BasAdvHid=EXPERT -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=TurnRxOn -[ItemState] -ItemSymbol=TurnRxOff -ReadOnly=No -UserReadOnly=No -BasAdvHid=EXPERT -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=TurnRxOff -[ItemState] -ItemSymbol=SetIdle -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=SetIdle -[ItemState] -ItemSymbol=LoopMode -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=LoopMode - -[EndOfChilds] -[ItemState] -ItemSymbol=CPUCond1 -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=Standby -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=Standby - -[EndOfChilds] -[ItemState] -ItemSymbol=ESCIMethodsGrp -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=GetArbiterStatus -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=GetArbiterStatus -[ItemState] -ItemSymbol=ResetArbiterCounter -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=ResetArbiterCounter -[ItemState] -ItemSymbol=GetArbiterCounter -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=GetArbiterCounter -[ItemState] -ItemSymbol=SetFallingEdgesMeasurement -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=SetFallingEdgesMeasurement -[ItemState] -ItemSymbol=SetLowLevelMeasurement -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=SetLowLevelMeasurement -[ItemState] -ItemSymbol=ClearArbiterFlags -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=ClearArbiterFlags -[ItemState] -ItemSymbol=SetArbitrationMode -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=SetArbitrationMode -[ItemState] -ItemSymbol=AdjustBaudRate -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=AdjustBaudRate - -[EndOfChilds] -[ItemState] -ItemSymbol=CPU_HCS08_HCS12 -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=SetDirection -ReadOnly=Yes -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=No -LastUserSel=never -UsrMethodName=SetDirection - -[EndOfChilds] -[ItemState] -ItemSymbol=56800grp -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=ConnectPin -ReadOnly=No -UserReadOnly=No -BasAdvHid=EXPERT -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=ConnectPin - -[EndOfChilds] - -[Events] -List=Event -[ItemState] -ItemSymbol=EventModule -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Value=Events -[ItemState] -ItemSymbol=BeforeNewSpeed -ReadOnly=No -UserReadOnly=No -BasAdvHid=EXPERT -Value=No - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=Name -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=COM0_BeforeNewSpeed - -[EndOfChilds] -LastSelection=No -LastUserSel=no -[ItemState] -ItemSymbol=AfterNewSpeed -ReadOnly=No -UserReadOnly=No -BasAdvHid=EXPERT -Value=No - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=Name -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=COM0_AfterNewSpeed - -[EndOfChilds] -LastSelection=No -LastUserSel=no -[ItemState] -ItemSymbol=OnError -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=No - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=Name -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=COM0_OnError -[ItemState] -ItemSymbol=Priority -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Value=same as interrupt - -[EndOfChilds] -LastSelection=Yes -LastUserSel=no -[ItemState] -ItemSymbol=OnRxChar -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=No - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=Name -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=COM0_OnRxChar -[ItemState] -ItemSymbol=Priority -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Value=same as interrupt - -[EndOfChilds] -LastSelection=Yes -LastUserSel=no -[ItemState] -ItemSymbol=OnTxChar -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=No - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=Name -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=COM0_OnTxChar -[ItemState] -ItemSymbol=Priority -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Value=same as interrupt - -[EndOfChilds] -LastSelection=Yes -LastUserSel=no -[ItemState] -ItemSymbol=OnFullRxBuf -ReadOnly=Yes -UserReadOnly=No -BasAdvHid=BASIC -Value=No - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=Name -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=COM0_OnFullRxBuf -[ItemState] -ItemSymbol=Priority -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Value=same as interrupt - -[EndOfChilds] -LastSelection=Yes -LastUserSel=never -[ItemState] -ItemSymbol=OnFreeTxBuf -ReadOnly=Yes -UserReadOnly=No -BasAdvHid=BASIC -Value=No - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=Name -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=COM0_OnFreeTxBuf -[ItemState] -ItemSymbol=Priority -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Value=same as interrupt - -[EndOfChilds] -LastSelection=Yes -LastUserSel=never -[ItemState] -ItemSymbol=OnBreak -ReadOnly=Yes -UserReadOnly=No -BasAdvHid=ADVANCED -Value=No - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=Name -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=COM0_OnBreak -[ItemState] -ItemSymbol=Priority -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Value=same as interrupt - -[EndOfChilds] -LastSelection=Yes -LastUserSel=never -[ItemState] -ItemSymbol=CPUCond0 -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=OnIdle -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Value=No - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=Name -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=COM0_OnIdle -[ItemState] -ItemSymbol=Priority -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Value=same as interrupt - -[EndOfChilds] -LastSelection=No -LastUserSel=no - -[EndOfChilds] - -[Program] -ProgType=event -ProgNumb=2 -List=Property -EventModule=Events - -[_end_] diff --git a/Demo/HCS12_CodeWarrior_banked/RTOSDemo_Data/CWSettingsWindows.stg b/Demo/HCS12_CodeWarrior_banked/RTOSDemo_Data/CWSettingsWindows.stg deleted file mode 100644 index f3d72ee0a..000000000 Binary files a/Demo/HCS12_CodeWarrior_banked/RTOSDemo_Data/CWSettingsWindows.stg and /dev/null differ diff --git a/Demo/HCS12_CodeWarrior_banked/RTOSDemo_Data/P&E_ICD/TargetDataWindows.tdt b/Demo/HCS12_CodeWarrior_banked/RTOSDemo_Data/P&E_ICD/TargetDataWindows.tdt deleted file mode 100644 index 8ab9f814d..000000000 Binary files a/Demo/HCS12_CodeWarrior_banked/RTOSDemo_Data/P&E_ICD/TargetDataWindows.tdt and /dev/null differ diff --git a/Demo/HCS12_CodeWarrior_banked/RTOSDemo_Data/Simulator/TargetDataWindows.tdt b/Demo/HCS12_CodeWarrior_banked/RTOSDemo_Data/Simulator/TargetDataWindows.tdt deleted file mode 100644 index 384e9541b..000000000 Binary files a/Demo/HCS12_CodeWarrior_banked/RTOSDemo_Data/Simulator/TargetDataWindows.tdt and /dev/null differ diff --git a/Demo/HCS12_CodeWarrior_banked/Simulator.ini b/Demo/HCS12_CodeWarrior_banked/Simulator.ini deleted file mode 100644 index 90a0c8e61..000000000 --- a/Demo/HCS12_CodeWarrior_banked/Simulator.ini +++ /dev/null @@ -1,25 +0,0 @@ -[Environment Variables] -GENPATH={Compiler}lib\HC12c\src;{Compiler}lib\HC12c\include;{Compiler}lib\HC12c\lib -LIBPATH={Compiler}lib\HC12c\include -OBJPATH={Project}bin -TEXTPATH={Project}bin -ABSPATH={Project}bin - -[HI-WAVE] -Target=sim -Layout=C_layout.hwl -LoadDialogOptions= AUTOERASEANDFLASH -CPU=HC12 -MainFrame=2,3,-1,-1,-1,-1,108,108,1308,962 -TOOLBAR=57600 57601 32795 0 57635 57634 57637 0 57671 57669 0 32777 32776 32782 32780 32781 32778 0 32806 - -[Simulator] -CMDFILE0=CMDFILE STARTUP ON ".\cmd\simulator_startup.cmd" - -[Simulator HC12] -CMDFILE0=CMDFILE RESET ON ".\cmd\simulator_reset.cmd" -CMDFILE1=CMDFILE PRELOAD ON ".\cmd\simulator_preload.cmd" -CMDFILE2=CMDFILE POSTLOAD ON ".\cmd\simulator_postload.cmd" -CMDFILE3=CMDFILE SETCPU ON ".\cmd\simulator_setcpu.cmd" -HCS12_SUPPORT=1 -FCS=MC9S12DP256B diff --git a/Demo/HCS12_CodeWarrior_banked/Sources/Start12.c b/Demo/HCS12_CodeWarrior_banked/Sources/Start12.c deleted file mode 100644 index df8b0e648..000000000 --- a/Demo/HCS12_CodeWarrior_banked/Sources/Start12.c +++ /dev/null @@ -1,342 +0,0 @@ -/***************************************************** - start12.c - standard startup code - The startup code may be optimized to special user requests - ---------------------------------------------------- - Copyright (c) Metrowerks, Basel, Switzerland - All rights reserved - Do not modify! - -Note: ROM libraries are not implemented in this startup code -Note: C++ destructors of global objects are NOT yet supported in the HIWARE Object File Format. - To use this feature, please build your application with the ELF object file format. - *****************************************************/ - -#include "hidef.h" -#include "start12.h" - -/* Macros to control how the startup code handles the COP: */ -/* #define _DO_FEED_COP_ : do feed the COP */ -/* #define _DO_ENABLE_COP_: do enable the COP */ -/* #define _DO_DISABLE_COP_: disable the COP */ -/* Without defining any of these, the startup code does NOT handle the COP */ - -#pragma DATA_SEG __NEAR_SEG STARTUP_DATA /* _startupData can be accessed using 16 bit accesses. This is needed because it contains the stack top, and without stack, far data cannot be accessed */ -struct _tagStartup _startupData; /* read-only: */ - /* _startupData is allocated in ROM and */ - /* initialized by the linker */ -#pragma DATA_SEG DEFAULT -#if defined(FAR_DATA) -#include "non_bank.sgm" -/* the init function must be in non banked memory if banked variables are used */ -/* because _SET_PAGE is called, which may change any page register. */ - -#ifdef __cplusplus - extern "C" -#endif -void _SET_PAGE(void); /* the inline assembler needs a prototype */ - /* this is a runtime routine with a special */ - /* calling convention, dont use it in c code! */ -static void Init(void); -static void Fini(void); -#else -#include "default.sgm" -#if defined( __BANKED__) || defined(__LARGE__) -static void __far Init(void); -static void __far Fini(void); -#endif /* defined( __BANKED__) || defined(__LARGE__) */ -#endif /* FAR_DATA */ - - -/* define value and bits for Windef Register */ -#ifdef HC812A4 -#define WINDEF (*(volatile unsigned char*) 0x37) -#if defined( __BANKED__) || defined(__LARGE__) || defined(__PPAGE__) -#define __ENABLE_PPAGE__ 0x40 -#else -#define __ENABLE_PPAGE__ 0x0 -#endif -#if defined(__DPAGE__) -#define __ENABLE_DPAGE__ 0x80 -#else -#define __ENABLE_DPAGE__ 0x0 -#endif -#if defined(__EPAGE__) -#define __ENABLE_EPAGE__ 0x20 -#else -#define __ENABLE_EPAGE__ 0x0 -#endif -#endif /* HC812A4 */ - -#ifdef _HCS12_SERIALMON - /* for Monitor based software remap the RAM & EEPROM to adhere - to EB386. Edit RAM and EEPROM sections in PRM file to match these. */ -#define ___INITRM (*(volatile unsigned char *) 0x0010) -#define ___INITRG (*(volatile unsigned char *) 0x0011) -#define ___INITEE (*(volatile unsigned char *) 0x0012) -#endif - -#if defined(_DO_FEED_COP_) -#define __FEED_COP_IN_HLI() } __asm movb #0x55, _COP_RST_ADR; __asm movb #0xAA, _COP_RST_ADR; __asm { -#else -#define __FEED_COP_IN_HLI() /* do nothing */ -#endif - -#if !defined(FAR_DATA) && (defined( __BANKED__) || defined(__LARGE__)) -static void __far Init(void) -#else -static void Init(void) -#endif - { -/* purpose: 1) zero out RAM-areas where data is allocated */ -/* 2) copy initialization data from ROM to RAM */ -/* 3) call global constructors in C++ */ -/* called from: _Startup, LibInits */ - __asm { -ZeroOut: -#if defined(__HIWARE_OBJECT_FILE_FORMAT__) && defined(__LARGE__) - LDX _startupData.pZeroOut:1 ; in the large memory model in the HIWARE format, pZeroOut is a 24 bit pointer -#else - LDX _startupData.pZeroOut ; *pZeroOut -#endif - LDY _startupData.nofZeroOuts ; nofZeroOuts - BEQ CopyDown ; if nothing to zero out - -NextZeroOut: PSHY ; save nofZeroOuts -#ifdef FAR_DATA - LDAB 1,X+ ; load page of destination address - LDY 2,X+ ; load offset of destination address - __PIC_JSR(_SET_PAGE) ; sets the page in the correct page register -#else /* FAR_DATA */ - LDY 2,X+ ; start address and advance *pZeroOut (X = X+4) -#endif /* FAR_DATA */ - LDD 2,X+ ; byte count -#ifdef __OPTIMIZE_FOR_SIZE__ /* -os, default */ -NextWord: CLR 1,Y+ ; clear memory byte - __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */ - DBNE D, NextWord ; dec byte count -#else - LSRD ; /2 and save bit 0 in the carry - PSHX - LDX #0 -LoopClrW: STX 2,Y+ ; Word-Clear - __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */ - DBNE D, LoopClrW - PULX - BCC LastClr ; handle last byte - CLR 1,Y+ -LastClr: -#endif - PULY ; restore nofZeroOuts - DEY ; dec nofZeroOuts - BNE NextZeroOut -CopyDown: -#ifdef __ELF_OBJECT_FILE_FORMAT__ - LDX _startupData.toCopyDownBeg ; load address of copy down desc. -#else - LDX _startupData.toCopyDownBeg:2 ; load address of copy down desc. -#endif -NextBlock: - LDD 2,X+ ; size of init-data -> D - BEQ funcInits ; end of copy down desc. -#ifdef FAR_DATA - PSHD ; save counter - LDAB 1,X+ ; load destination page - LDY 2,X+ ; destination address - __PIC_JSR(_SET_PAGE) ; sets the destinations page register - PULD ; restore counter -#else /* FAR_DATA */ - LDY 2,X+ ; load destination address -#endif /* FAR_DATA */ - -#ifdef __OPTIMIZE_FOR_SIZE__ /* -os, default */ -Copy: MOVB 1,X+,1,Y+ ; move a byte from ROM to the data area - __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */ - DBNE D,Copy ; copy-byte loop -#else - LSRD ; /2 and save bit 0 in the carry -Copy: MOVW 2,X+,2,Y+ ; move a word from ROM to the data area - __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */ - DBNE D,Copy ; copy-word loop - BCC NextBlock ; handle last byte? - MOVB 1,X+,1,Y+ ; copy the last byte -#endif - BRA NextBlock -funcInits: ; call of global construtors is only in c++ necessary -#if defined(__cplusplus) -#if defined(__ELF_OBJECT_FILE_FORMAT__) -#if defined( __BANKED__) || defined(__LARGE__) - LDY _startupData.nofInitBodies; load number of cpp. - BEQ done ; if cppcount == 0, goto done - LDX _startupData.initBodies ; load address of first module to initialize -nextInit: - LEAX 3,X ; increment to next init - PSHX ; save address of next function to initialize - PSHY ; save cpp counter - CALL [-3,X] ; use double indirect call to load the page register also - PULY ; restore cpp counter - PULX ; restore actual address - DEY ; decrement cpp counter - BNE nextInit -#else /* defined( __BANKED__) || defined(__LARGE__) */ - - LDD _startupData.nofInitBodies; load number of cpp. - BEQ done ; if cppcount == 0, goto done - LDX _startupData.initBodies ; load address of first module to initialize -nextInit: - LDY 2,X+ ; load address of first module to initialize - PSHD - PSHX ; save actual address - JSR 0,Y ; call initialization function - PULX ; restore actual address - PULD ; restore cpp counter - DBNE D, nextInit -#endif /* defined( __BANKED__) || defined(__LARGE__) */ -#else /* __ELF_OBJECT_FILE_FORMAT__ */ - LDX _startupData.mInits ; load address of first module to initialize -#if defined( __BANKED__) || defined(__LARGE__) -nextInit: LDY 3,X+ ; load address of initialization function - BEQ done ; stop when address == 0 - ; in common environments the offset of a function is never 0, so this test could be avoided -#ifdef __InitFunctionsMayHaveOffset0__ - BRCLR -1,X, done, 0xff ; stop when address == 0 -#endif /* __InitFunctionsMayHaveOffset0__ */ - PSHX ; save address of next function to initialize - CALL [-3,X] ; use double indirect call to load the page register also -#else /* defined( __BANKED__) || defined(__LARGE__) */ -nextInit: - LDY 2,X+ ; load address of first module to initialize - BEQ done ; stop when address of function == 0 - PSHX ; save actual address - JSR 0,Y ; call initialization function -#endif /* defined( __BANKED__) || defined(__LARGE__) */ - PULX ; restore actual address - BRA nextInit -#endif /* __ELF_OBJECT_FILE_FORMAT__ */ -done: -#endif /* __cplusplus */ - } -} - -#if defined( __ELF_OBJECT_FILE_FORMAT__) && defined(__cplusplus ) - -#if !defined(FAR_DATA) && (defined( __BANKED__) || defined(__LARGE__)) -static void __far Fini(void) -#else -static void Fini(void) -#endif -{ -/* purpose: 1) call global destructors in C++ */ - __asm { -#if defined( __BANKED__) || defined(__LARGE__) - - LDY _startupData.nofFiniBodies; load number of cpp. - BEQ done ; if cppcount == 0, goto done - LDX _startupData.finiBodies ; load address of first module to finalize -nextInit2: - LEAX 3,X ; increment to next init - PSHX ; save address of next function to finalize - PSHY ; save cpp counter - CALL [-3,X] ; use double indirect call to load the page register also - PULY ; restore cpp counter - PULX ; restore actual address - DEY ; decrement cpp counter - BNE nextInit2 -#else /* defined( __BANKED__) || defined(__LARGE__) */ - - LDD _startupData.nofFiniBodies; load number of cpp. - BEQ done ; if cppcount == 0, goto done - LDX _startupData.finiBodies ; load address of first module to finalize -nextInit2: - LDY 2,X+ ; load address of first module to finalize - PSHD - PSHX ; save actual address - JSR 0,Y ; call finalize function - PULX ; restore actual address - PULD ; restore cpp counter - DBNE D, nextInit2 -#endif /* defined( __BANKED__) || defined(__LARGE__) */ -done:; - } -} -#endif - - -#include "non_bank.sgm" - -#pragma MESSAGE DISABLE C12053 /* Stack-pointer change not in debugging-information */ -#pragma NO_FRAME -#pragma NO_ENTRY -#pragma NO_EXIT - -#ifdef __cplusplus - extern "C" -#endif - -/* The function _Startup must be called in order to initialize global variables and to call main */ -/* You can adapt this function or call it from your startup code to implement a different startup */ -/* functionality. */ - -/* You should also setup the needed IO registers as WINDEF (HC12A4 only) or the COP registers to run */ -/* on hardware */ - -/* to set the reset vector several ways are possible : */ -/* 1. define the function with "interrupt 0" as done below in the first case */ -/* 2. add the following line to your prm file : VECTOR ADDRESS 0xfffe _Startup */ -/* of course, even more posibilities exists */ -/* the reset vector must be set so that the application has a defined entry point */ - -#define STARTUP_FLAGS_NOT_INIT_SP (1<<1) - -#if defined(__SET_RESET_VECTOR__) -void __interrupt 0 _Startup(void) { -#else -void _Startup(void) { -#endif -/* purpose: 1) initialize the stack - 2) initialize the RAM, copy down init data etc (Init) - 3) call main; - parameters: NONE - called from: _PRESTART-code generated by the Linker - or directly referenced by the reset vector */ - for(;;) { /* forever: initialize the program; call the root-procedure */ - if (!(_startupData.flags&STARTUP_FLAGS_NOT_INIT_SP)) { - /* initialize the stack pointer */ - INIT_SP_FROM_STARTUP_DESC(); /*lint !e522 asm code */ /* HLI macro definition in hidef.h */ - } - -#ifdef _HCS12_SERIALMON - /* for Monitor based software remap the RAM & EEPROM to adhere - to EB386. Edit RAM and EEPROM sections in PRM file to match these. */ - ___INITRG = 0x00; /* lock registers block to 0x0000 */ - ___INITRM = 0x39; /* lock Ram to end at 0x3FFF */ - ___INITEE = 0x09; /* lock EEPROM block to end at 0x0fff */ -#endif - - /* Here user defined code could be inserted, the stack could be used */ -#if defined(_DO_DISABLE_COP_) - _DISABLE_COP(); -#endif - - /* Example : Set up WinDef Register to allow Paging */ -#ifdef HC812A4 /* HC12 A4 derivative needs WINDEF to configure which pages are available */ -#if (__ENABLE_EPAGE__ != 0 || __ENABLE_DPAGE__ != 0 || __ENABLE_PPAGE__ != 0) - WINDEF= __ENABLE_EPAGE__ | __ENABLE_DPAGE__ | __ENABLE_PPAGE__; -#endif -#endif - Init(); /* zero out, copy down, call constructors */ - /* Here user defined code could be inserted, all global variables are initilized */ -#if defined(_DO_ENABLE_COP_) - _ENABLE_COP(1); -#endif - - /* call main() */ - (*_startupData.main)(); - - /* call destructors. Only done when this file is compiled as C++ and for the ELF object file format */ - /* the HIWARE object file format does not support this */ -#if defined( __ELF_OBJECT_FILE_FORMAT__) && defined(__cplusplus ) - Fini(); -#endif - - } /* end loop forever */ -} diff --git a/Demo/HCS12_CodeWarrior_banked/Sources/datapage.c b/Demo/HCS12_CodeWarrior_banked/Sources/datapage.c deleted file mode 100644 index 80be5c566..000000000 --- a/Demo/HCS12_CodeWarrior_banked/Sources/datapage.c +++ /dev/null @@ -1,843 +0,0 @@ -/****************************************************************************** - FILE : datapage.c - PURPOSE : paged data access runtime routines - MACHINE : Motorola 68HC12 (Target) - LANGUAGE : ANSI-C - HISTORY : 21.7.96 first version created -******************************************************************************/ - -/* - According to the -Cp option of the compiler the - __DPAGE__, __PPAGE__ and __EPAGE__ macros are defined. - If none of them is given as argument, then no page accesses should occur and - this runtime routine should not be used ! - To be on the save side, the runtime routines are created anyway. - If some of the -Cp options are given an adapted versions which only covers the - needed cases is produced. -*/ - -/* if no compiler option -Cp is given, it is assumed that all possible are given : */ - -/* Compile with option -DHCS12 to activate this code */ -#if defined(HCS12) || defined(_HCS12) /* HCS12 family has PPAGE register only at 0x30 */ -#define PPAGE_ADDR (0x30+REGISTER_BASE) -#ifndef __PPAGE__ /* may be set already by option -CPPPAGE */ -#define __PPAGE__ -#endif -/* Compile with option -DDG128 to activate this code */ -#elif defined DG128 /* HC912DG128 derivative has PPAGE register only at 0xFF */ -#define PPAGE_ADDR (0xFF+REGISTER_BASE) -#ifndef __PPAGE__ /* may be set already by option -CPPPAGE */ -#define __PPAGE__ -#endif -#elif defined(HC812A4) -/* all setting default to A4 already */ -#endif - - -#if !defined(__EPAGE__) && !defined(__PPAGE__) && !defined(__DPAGE__) -/* as default use all page registers */ -#define __DPAGE__ -#define __EPAGE__ -#define __PPAGE__ -#endif - -/* modify the following defines to your memory configuration */ - -#define EPAGE_LOW_BOUND 0x400u -#define EPAGE_HIGH_BOUND 0x7ffu - -#define DPAGE_LOW_BOUND 0x7000u -#define DPAGE_HIGH_BOUND 0x7fffu - -#define PPAGE_LOW_BOUND (DPAGE_HIGH_BOUND+1) -#define PPAGE_HIGH_BOUND 0xBFFFu - -#define REGISTER_BASE 0x0u -#ifndef DPAGE_ADDR -#define DPAGE_ADDR (0x34u+REGISTER_BASE) -#endif -#ifndef EPAGE_ADDR -#define EPAGE_ADDR (0x36u+REGISTER_BASE) -#endif -#ifndef PPAGE_ADDR -#define PPAGE_ADDR (0x35u+REGISTER_BASE) -#endif - -/* - The following parts about the defines are assumed in the code of _GET_PAGE_REG : - - the memory region controlled by DPAGE is above the area controlled by the EPAGE and - below the area controlled by the PPAGE. - - the lower bound of the PPAGE area is equal to be the higher bound of the DPAGE area + 1 -*/ -#if EPAGE_LOW_BOUND >= EPAGE_HIGH_BOUND || EPAGE_HIGH_BOUND >= DPAGE_LOW_BOUND || DPAGE_LOW_BOUND >= DPAGE_HIGH_BOUND || DPAGE_HIGH_BOUND >= PPAGE_LOW_BOUND || PPAGE_LOW_BOUND >= PPAGE_HIGH_BOUND -#error /* please adapt _GET_PAGE_REG for this non default page configuration */ -#endif - -#if DPAGE_HIGH_BOUND+1 != PPAGE_LOW_BOUND -#error /* please adapt _GET_PAGE_REG for this non default page configuration */ -#endif - -#include "hidef.h" -#include "non_bank.sgm" -#include "runtime.sgm" - -/* this module does either control if any access is in the bounds of the specified page or */ -/* ,if only one page is specified, just use this page. */ -/* This behavior is controlled by the define USE_SEVERAL_PAGES. */ -/* If !USE_SEVERAL_PAGES does increase the performance significantly */ -/* NOTE : When !USE_SEVERAL_PAGES, the page is also set for accesses outside of the area controlled */ -/* by this single page. But this is usually no problem because the page is set again before any other access */ - -#if !defined(__DPAGE__) && !defined(__EPAGE__) && !defined(__PPAGE__) -/* no page at all is specified */ -/* only specifing the right pages will speed up these functions a lot */ -#define USE_SEVERAL_PAGES 1 -#elif defined(__DPAGE__) && defined(__EPAGE__) || defined(__DPAGE__) && defined(__PPAGE__) || defined(__EPAGE__) && defined(__PPAGE__) -/* more than one page register is used */ -#define USE_SEVERAL_PAGES 1 -#else - -#define USE_SEVERAL_PAGES 0 - -#if defined(__DPAGE__) /* check which pages are used */ -#define PAGE_ADDR PPAGE_ADDR -#elif defined(__EPAGE__) -#define PAGE_ADDR EPAGE_ADDR -#elif defined(__PPAGE__) -#define PAGE_ADDR PPAGE_ADDR -#else /* we dont know which page, decide it at runtime */ -#error /* must not happen */ -#endif - -#endif - - -#if USE_SEVERAL_PAGES /* only needed for several pages support */ -/*--------------------------- _GET_PAGE_REG -------------------------------- - Runtime routine to detect the right register depending on the 16 bit offset part - of an address. - This function is only used by the functions below. - - Depending on the compiler options -Cp different versions of _GET_PAGE_REG are produced. - - Arguments : - - Y : offset part of an address - - Result : - if address Y is controlled by a page register : - - X : address of page register if Y is controlled by an page register - - Zero flag cleared - - all other registers remain unchanged - - if address Y is not controlled by a page register : - - Zero flag is set - - all registers remain unchanged - - --------------------------- _GET_PAGE_REG ----------------------------------*/ - -#if defined(__DPAGE__) - -#ifdef __cplusplus -extern "C" -#endif -#pragma NO_ENTRY -#pragma NO_EXIT -#pragma NO_FRAME - -static void NEAR _GET_PAGE_REG(void) { /*lint -esym(528, _GET_PAGE_REG) used in asm code */ - asm { -L_DPAGE: - CPY #DPAGE_LOW_BOUND ; test of lower bound of DPAGE -#if defined(__EPAGE__) - BLO L_EPAGE ; EPAGE accesses are possible -#else - BLO L_NOPAGE ; no paged memory below accesses -#endif - CPY #DPAGE_HIGH_BOUND ; test of higher bound DPAGE/lower bound PPAGE -#if defined(__PPAGE__) - BHI L_PPAGE ; EPAGE accesses are possible -#else - BHI L_NOPAGE ; no paged memory above accesses -#endif -FOUND_DPAGE: - LDX #DPAGE_ADDR ; load page register address and clear zero flag - RTS - -#if defined(__PPAGE__) -L_PPAGE: - CPY #PPAGE_HIGH_BOUND ; test of higher bound of PPAGE - BHI L_NOPAGE -FOUND_PPAGE: - LDX #PPAGE_ADDR ; load page register address and clear zero flag - RTS -#endif - -#if defined(__EPAGE__) -L_EPAGE: - CPY #EPAGE_LOW_BOUND ; test of lower bound of EPAGE - BLO L_NOPAGE - CPY #EPAGE_HIGH_BOUND ; test of higher bound of EPAGE - BHI L_NOPAGE - -FOUND_EPAGE: - LDX #EPAGE_ADDR ; load page register address and clear zero flag - RTS -#endif - -L_NOPAGE: - ORCC #0x04 ; sets zero flag - RTS - } -} - -#else /* !defined(__DPAGE__) */ - -#if defined( __PPAGE__ ) - -#ifdef __cplusplus -extern "C" -#endif -#pragma NO_ENTRY -#pragma NO_EXIT -#pragma NO_FRAME - -static void NEAR _GET_PAGE_REG(void) { /*lint -esym(528, _GET_PAGE_REG) used in asm code */ - asm { -L_PPAGE: - CPY #PPAGE_LOW_BOUND ; test of lower bound of PPAGE -#if defined( __EPAGE__ ) - BLO L_EPAGE -#else - BLO L_NOPAGE ; no paged memory below -#endif - CPY #PPAGE_HIGH_BOUND ; test of higher bound PPAGE - BHI L_NOPAGE -FOUND_PPAGE: - LDX #PPAGE_ADDR ; load page register address and clear zero flag - RTS -#if defined( __EPAGE__ ) -L_EPAGE: - CPY #EPAGE_LOW_BOUND ; test of lower bound of EPAGE - BLO L_NOPAGE - CPY #EPAGE_HIGH_BOUND ; test of higher bound of EPAGE - BHI L_NOPAGE -FOUND_EPAGE: - LDX #EPAGE_ADDR ; load page register address and clear zero flag - RTS -#endif - -L_NOPAGE: ; not in any allowed page area - ; its a far access to a non paged variable - ORCC #0x04 ; sets zero flag - RTS - } -} - -#else /* !defined(__DPAGE__ ) && !defined( __PPAGE__) */ -#if defined(__EPAGE__) - -#ifdef __cplusplus -extern "C" -#endif -#pragma NO_ENTRY -#pragma NO_EXIT -#pragma NO_FRAME - -static void NEAR _GET_PAGE_REG(void) { /*lint -esym(528, _GET_PAGE_REG) used in asm code */ - asm { -L_EPAGE: - CPY #EPAGE_LOW_BOUND ; test of lower bound of EPAGE - BLO L_NOPAGE - CPY #EPAGE_HIGH_BOUND ; test of higher bound of EPAGE - BHI L_NOPAGE -FOUND_EPAGE: - LDX #EPAGE_ADDR ; load page register address and clear zero flag - RTS - -L_NOPAGE: ; not in any allowed page area - ; its a far access to a non paged variable - ORCC #0x04 ; sets zero flag - RTS - } -} - -#endif /* defined(__EPAGE__) */ -#endif /* defined(__PPAGE__) */ -#endif /* defined(__DPAGE__) */ - -#endif /* USE_SEVERAL_PAGES */ - -/*--------------------------- _SET_PAGE -------------------------------- - Runtime routine to set the right page register. This routine is used if the compiler - does not know the right page register, i.e. if the option -Cp is used for more than - one pageregister or if the runtime option is used for one of the -Cp options. - - Arguments : - - offset part of an address in the Y register - - page part of an address in the B register - - Result : - - page part written into the correct page register. - - the old page register content is destroyed - - all processor registers remains unchanged - --------------------------- _SET_PAGE ----------------------------------*/ - -#ifdef __cplusplus -extern "C" -#endif -#pragma NO_ENTRY -#pragma NO_EXIT -#pragma NO_FRAME - -void NEAR _SET_PAGE(void) { -#if USE_SEVERAL_PAGES - asm { - PSHX ; save X register - __PIC_JSR(_GET_PAGE_REG) - BEQ L_NOPAGE - STAB 0,X ; set page register -L_NOPAGE: - PULX ; restore X register - RTS - } -#else /* USE_SEVERAL_PAGES */ - asm { - STAB PAGE_ADDR ; set page register - RTS - } -#endif /* USE_SEVERAL_PAGES */ -} - -/*--------------------------- _LOAD_FAR_8 -------------------------------- - This runtime routine is used to access paged memory via a runtime function. - It may also be used if the compiler option -Cp is not used with the runtime argument. - - Arguments : - - offset part of an address in the Y register - - page part of an address in the B register - - Result : - - value to be read in the B register - - all other registers remains unchanged - - all page register still contain the same value - --------------------------- _LOAD_FAR_8 ----------------------------------*/ - -#ifdef __cplusplus -extern "C" -#endif -#pragma NO_ENTRY -#pragma NO_EXIT -#pragma NO_FRAME - -void NEAR _LOAD_FAR_8(void) { -#if USE_SEVERAL_PAGES - asm { - PSHX ; save X register - __PIC_JSR(_GET_PAGE_REG) - BEQ L_NOPAGE - PSHA ; save A register - LDAA 0,X ; save page register - STAB 0,X ; set page register - LDAB 0,Y ; actual load, overwrites page - STAA 0,X ; restore page register - PULA ; restore A register - PULX ; restore X register - RTS -L_NOPAGE: - LDAB 0,Y ; actual load, overwrites page - PULX ; restore X register - RTS - } -#else /* USE_SEVERAL_PAGES */ - asm { - PSHA ; save A register - LDAA PAGE_ADDR ; save page register - STAB PAGE_ADDR ; set page register - LDAB 0,Y ; actual load, overwrites page - STAA PAGE_ADDR ; restore page register - PULA ; restore A register - RTS - } -#endif /* USE_SEVERAL_PAGES */ -} - -/*--------------------------- _LOAD_FAR_16 -------------------------------- - This runtime routine is used to access paged memory via a runtime function. - It may also be used if the compiler option -Cp is not used with the runtime argument. - - Arguments : - - offset part of an address in the Y register - - page part of an address in the B register - - Result : - - value to be read in the Y register - - all other registers remains unchanged - - all page register still contain the same value - --------------------------- _LOAD_FAR_16 ----------------------------------*/ - -#ifdef __cplusplus -extern "C" -#endif -#pragma NO_ENTRY -#pragma NO_EXIT -#pragma NO_FRAME - -void NEAR _LOAD_FAR_16(void) { -#if USE_SEVERAL_PAGES - asm { - PSHX ; save X register - __PIC_JSR(_GET_PAGE_REG) - BEQ L_NOPAGE - PSHA ; save A register - LDAA 0,X ; save page register - STAB 0,X ; set page register - LDY 0,Y ; actual load, overwrites address - STAA 0,X ; restore page register - PULA ; restore A register - PULX ; restore X register - RTS -L_NOPAGE: - LDY 0,Y ; actual load, overwrites address - PULX ; restore X register - RTS - } -#else /* USE_SEVERAL_PAGES */ - asm { - PSHA ; save A register - LDAA PAGE_ADDR ; save page register - STAB PAGE_ADDR ; set page register - LDY 0,Y ; actual load, overwrites address - STAA PAGE_ADDR ; restore page register - PULA ; restore A register - RTS - } -#endif /* USE_SEVERAL_PAGES */ -} -/*--------------------------- _LOAD_FAR_24 -------------------------------- - This runtime routine is used to access paged memory via a runtime function. - It may also be used if the compiler option -Cp is not used with the runtime argument. - - Arguments : - - offset part of an address in the Y register - - page part of an address in the B register - - Result : - - value to be read in the Y:B registers - - all other registers remains unchanged - - all page register still contain the same value - --------------------------- _LOAD_FAR_24 ----------------------------------*/ - -#ifdef __cplusplus -extern "C" -#endif -#pragma NO_ENTRY -#pragma NO_EXIT -#pragma NO_FRAME - -void NEAR _LOAD_FAR_24(void) { -#if USE_SEVERAL_PAGES - asm { - PSHX ; save X register - __PIC_JSR(_GET_PAGE_REG) - BEQ L_NOPAGE - PSHA ; save A register - LDAA 0,X ; save page register - STAB 0,X ; set page register - LDAB 0,Y ; actual load, overwrites page of address - LDY 1,Y ; actual load, overwrites offset of address - STAA 0,X ; restore page register - PULA ; restore A register - PULX ; restore X register - RTS -L_NOPAGE: - LDAB 0,Y ; actual load, overwrites page of address - LDY 1,Y ; actual load, overwrites offset of address - PULX ; restore X register - RTS - } -#else /* USE_SEVERAL_PAGES */ - asm { - PSHA ; save A register - LDAA PAGE_ADDR ; save page register - STAB PAGE_ADDR ; set page register - LDAB 0,Y ; actual load, overwrites page of address - LDY 1,Y ; actual load, overwrites offset of address - STAA PAGE_ADDR ; restore page register - PULA ; restore A register - RTS - } -#endif /* USE_SEVERAL_PAGES */ - -} - -/*--------------------------- _LOAD_FAR_32 -------------------------------- - This runtime routine is used to access paged memory via a runtime function. - It may also be used if the compiler option -Cp is not used with the runtime argument. - - Arguments : - - offset part of an address in the Y register - - page part of an address in the B register - - Result : - - low 16 bit of value to be read in the D registers - - high 16 bit of value to be read in the Y registers - - all other registers remains unchanged - - all page register still contain the same value - --------------------------- _LOAD_FAR_32 ----------------------------------*/ - -#ifdef __cplusplus -extern "C" -#endif -#pragma NO_ENTRY -#pragma NO_EXIT -#pragma NO_FRAME - -void NEAR _LOAD_FAR_32(void) { -#if USE_SEVERAL_PAGES - asm { - PSHX ; save X register - __PIC_JSR(_GET_PAGE_REG) - BEQ L_NOPAGE - LDAA 0,X ; save page register - PSHA ; put it onto the stack - STAB 0,X ; set page register - LDD 2,Y ; actual load, low word - LDY 0,Y ; actual load, high word - MOVB 1,SP+,0,X ; restore page register - PULX ; restore X register - RTS -L_NOPAGE: - LDD 2,Y ; actual load, low word - LDY 0,Y ; actual load, high word - PULX ; restore X register - RTS - } -#else /* USE_SEVERAL_PAGES */ - asm { - LDAA PAGE_ADDR ; save page register - PSHA ; put it onto the stack - STAB PAGE_ADDR ; set page register - LDD 2,Y ; actual load, low word - LDY 0,Y ; actual load, high word - MOVB 1,SP+,PAGE_ADDR; restore page register - RTS - } -#endif /* USE_SEVERAL_PAGES */ -} - -/*--------------------------- _STORE_FAR_8 -------------------------------- - This runtime routine is used to access paged memory via a runtime function. - It may also be used if the compiler option -Cp is not used with the runtime argument. - - Arguments : - - offset part of an address in the Y register - - page part of an address in the B register - - value to be stored in the B register - - Result : - - value stored at the address - - all registers remains unchanged - - all page register still contain the same value - --------------------------- _STORE_FAR_8 ----------------------------------*/ - -#ifdef __cplusplus -extern "C" -#endif -#pragma NO_ENTRY -#pragma NO_EXIT -#pragma NO_FRAME - -void NEAR _STORE_FAR_8(void) { -#if USE_SEVERAL_PAGES - asm { - PSHX ; save X register - __PIC_JSR(_GET_PAGE_REG) - BEQ L_NOPAGE - PSHB ; save B register - LDAB 0,X ; save page register - MOVB 0,SP, 0,X ; set page register - STAA 0,Y ; store the value passed in A - STAB 0,X ; restore page register - PULB ; restore B register - PULX ; restore X register - RTS -L_NOPAGE: - STAA 0,Y ; store the value passed in A - PULX ; restore X register - RTS - } -#else /* USE_SEVERAL_PAGES */ - asm { - PSHB ; save A register - LDAB PAGE_ADDR ; save page register - MOVB 0,SP,PAGE_ADDR ; set page register - STAA 0,Y ; store the value passed in A - STAB PAGE_ADDR ; restore page register - PULB ; restore B register - RTS - } -#endif /* USE_SEVERAL_PAGES */ -} - -/*--------------------------- _STORE_FAR_16 -------------------------------- - This runtime routine is used to access paged memory via a runtime function. - It may also be used if the compiler option -Cp is not used with the runtime argument. - - Arguments : - - offset part of an address in the Y register - - page part of an address in the B register - - value to be stored in the X register - - Result : - - value stored at the address - - all registers remains unchanged - - all page register still contain the same value - --------------------------- _STORE_FAR_16 ----------------------------------*/ - -#ifdef __cplusplus -extern "C" -#endif -#pragma NO_ENTRY -#pragma NO_EXIT -#pragma NO_FRAME - -void NEAR _STORE_FAR_16(void) { -#if USE_SEVERAL_PAGES - asm { - PSHX ; save X register - __PIC_JSR(_GET_PAGE_REG) - BEQ L_NOPAGE - - PSHA - LDAA 0,X ; save page register - STAB 0,X ; set page register - MOVW 1,SP, 0,Y ; store the value passed in X - STAA 0,X ; restore page register - PULA ; restore A register - PULX ; restore X register - RTS - -L_NOPAGE: - STX 0,Y ; store the value passed in X - PULX ; restore X register - RTS - } -#else /* USE_SEVERAL_PAGES */ - asm { - PSHA ; save A register - LDAA PAGE_ADDR ; save page register - STAB PAGE_ADDR ; set page register - STX 0,Y ; store the value passed in X - STAA PAGE_ADDR ; restore page register - PULA ; restore A register - RTS - } -#endif /* USE_SEVERAL_PAGES */ -} -/*--------------------------- _STORE_FAR_24 -------------------------------- - This runtime routine is used to access paged memory via a runtime function. - It may also be used if the compiler option -Cp is not used with the runtime argument. - - Arguments : - - offset part of an address in the Y register - - page part of an address in the B register - - value to be stored in the X:A registers (X : low 16 bit, A : high 8 bit) - - Result : - - value stored at the address - - all registers remains unchanged - - all page register still contain the same value - --------------------------- _STORE_FAR_24 ----------------------------------*/ - -#ifdef __cplusplus -extern "C" -#endif -#pragma NO_ENTRY -#pragma NO_EXIT -#pragma NO_FRAME - -void NEAR _STORE_FAR_24(void) { -#if USE_SEVERAL_PAGES - asm { - PSHX ; save X register - __PIC_JSR(_GET_PAGE_REG) - BEQ L_NOPAGE - - PSHA - LDAA 0,X ; save page register - STAB 0,X ; set page register - MOVW 1,SP, 1,Y ; store the value passed in X - MOVB 0,SP, 0,Y ; store the value passed in A - STAA 0,X ; restore page register - PULA ; restore A register - PULX ; restore X register - RTS - -L_NOPAGE: - STX 1,Y ; store the value passed in X - STAA 0,Y ; store the value passed in X - PULX ; restore X register - RTS - } -#else /* USE_SEVERAL_PAGES */ - asm { - PSHA ; save A register - LDAA PAGE_ADDR ; save page register - STAB PAGE_ADDR ; set page register - MOVB 0,SP, 0,Y ; store the value passed in A - STX 1,Y ; store the value passed in X - STAA PAGE_ADDR ; restore page register - PULA ; restore A register - RTS - } -#endif /* USE_SEVERAL_PAGES */ -} -/*--------------------------- _STORE_FAR_32 -------------------------------- - This runtime routine is used to access paged memory via a runtime function. - It may also be used if the compiler option -Cp is not used with the runtime argument. - - Arguments : - - offset part of an address in the Y register - - page part of an address is on the stack at 3,SP (just below the return address) - - value to be stored in the X:D registers (D : low 16 bit, X : high 16 bit) - - Result : - - value stored at the address - - all registers remains unchanged - - the page part is removed from the stack - - all page register still contain the same value - --------------------------- _STORE_FAR_32 ----------------------------------*/ - -#ifdef __cplusplus -extern "C" -#endif -#pragma NO_ENTRY -#pragma NO_EXIT -#pragma NO_FRAME - -void NEAR _STORE_FAR_32(void) { -#if USE_SEVERAL_PAGES - asm { - PSHX ; save X register - __PIC_JSR(_GET_PAGE_REG) - BEQ L_NOPAGE - - PSHD - LDAA 0,X ; save page register - MOVB 6,SP, 0,X ; set page register - MOVW 2,SP, 0,Y ; store the value passed in X (high word) - MOVW 0,SP, 2,Y ; store the value passed in D (low word) - STAA 0,X ; restore page register - PULD ; restore A register - BRA done - -L_NOPAGE: - MOVW 0,SP, 0,Y ; store the value passed in X (high word) - STD 2,Y ; store the value passed in D (low word) -done: - PULX ; restore X register - MOVW 0,SP, 1,+SP ; move return address - RTS - } -#else /* USE_SEVERAL_PAGES */ - asm { - PSHD ; save D register - LDAA PAGE_ADDR ; save page register - LDAB 4,SP ; load page part of address - STAB PAGE_ADDR ; set page register - STX 0,Y ; store the value passed in X - MOVW 0,SP, 2,Y ; store the value passed in D (low word) - STAA PAGE_ADDR ; restore page register - PULD ; restore D register - MOVW 0,SP, 1,+SP ; move return address - RTS - } -#endif /* USE_SEVERAL_PAGES */ -} - -/*--------------------------- _FAR_COPY -------------------------------- - This runtime routine is used to access paged memory via a runtime function. - It may also be used if the compiler option -Cp is not used with the runtime argument. - - Arguments : - - offset part of the source int the X register - - page part of the source in the A register - - offset part of the dest int the Y register - - page part of the dest in the B register - - number of bytes to be copied at 2,SP. The number of bytes is always > 0 - - Result : - - memory area copied - - no registers are saved, i.e. all registers may be destroied - - all page register still contain the same value - - - stack-structure at the loop-label: - 0,SP : destination offset - 2,SP : source page - 3,SP : destination page - 4,SP : source offset - 6,SP : return address - 8,SP : counter, > 0 - --------------------------- _FAR_COPY ----------------------------------*/ - -#ifdef __cplusplus -extern "C" -#endif -#pragma NO_ENTRY -#pragma NO_EXIT -#pragma NO_FRAME - -void NEAR _FAR_COPY(void) { -#if USE_SEVERAL_PAGES - asm { - DEX ; source addr-=1, because loop counter ends at 1 - PSHX ; save source offset - PSHD ; save both pages - DEY ; destination addr-=1, because loop counter ends at 1 - PSHY ; save destination offset - LDX 8,SP ; load counter, assuming counter > 0 - -loop: - LDD 4,SP ; load source offset - LEAY D,X ; calcutate actual source address - LDAB 2,SP ; load source page - __PIC_JSR (_LOAD_FAR_8); load 1 source byte - PSHB ; save value - LDD 0+1,SP ; load destination offset - LEAY D,X ; calcutate acual destination address - PULA ; restore value - LDAB 3,SP ; load destination page - __PIC_JSR (_STORE_FAR_8); store one byte - DEX - BNE loop - LDX 6,SP ; load return address - LEAS 10,SP ; release stack - JMP 0,X ; return - } -#else - asm { - PSHD ; store page registers - TFR X,D - ADDD 4,SP ; calculate source end address - STD 4,SP - PULB ; reload source page - LDAA PAGE_ADDR ; save page register - PSHA -loop: - STAB PAGE_ADDR ; set source page - LDAA 1,X+ ; load value - MOVB 1,SP, PAGE_ADDR ; set destination page - STAA 1,Y+ - CPX 4,SP - BNE loop - - LDAA 2,SP+ ; restore old page value and release stack - STAA PAGE_ADDR ; store it into page register - LDX 4,SP+ ; release stack and load return address - JMP 0,X ; return - } -#endif -} - diff --git a/Demo/HCS12_CodeWarrior_banked/bin/P&E_ICD.map b/Demo/HCS12_CodeWarrior_banked/bin/P&E_ICD.map deleted file mode 100644 index ff7f0c498..000000000 --- a/Demo/HCS12_CodeWarrior_banked/bin/P&E_ICD.map +++ /dev/null @@ -1,3994 +0,0 @@ - -PROGRAM "E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_banked\bin\P&E_ICD.abs" - -********************************************************************************************* -TARGET SECTION ---------------------------------------------------------------------------------------------- -Processor : Motorola HC12 -Memory Model: BANKED -File Format : ELF\Dwarf 2.0 -Linker : SmartLinker V-5.0.22 Build 4047, Feb 17 2004 - -********************************************************************************************* -FILE SECTION ---------------------------------------------------------------------------------------------- -Start12.c.o Model: BANKED, Lang: ANSI-C -STRING.C.o (ansibi.lib) Model: BANKED, Lang: ANSI-C -rtshc12.c.o (ansibi.lib) Model: BANKED, Lang: ANSI-C -Cpu.C.o Model: BANKED, Lang: ANSI-C -IO_Map.C.o Model: BANKED, Lang: ANSI-C -Vectors.c.o Model: BANKED, Lang: ANSI-C -RTOSDemo.C.o Model: BANKED, Lang: ANSI-C -main.c.o Model: BANKED, Lang: ANSI-C -ParTest.c.o Model: BANKED, Lang: ANSI-C -serial.c.o Model: BANKED, Lang: ANSI-C -tasks.c.o Model: BANKED, Lang: ANSI-C -queue.c.o Model: BANKED, Lang: ANSI-C -list.c.o Model: BANKED, Lang: ANSI-C -heap_2.c.o Model: BANKED, Lang: ANSI-C -flash.c.o Model: BANKED, Lang: ANSI-C -dynamic.c.o Model: BANKED, Lang: ANSI-C -PollQ.c.o Model: BANKED, Lang: ANSI-C -TickTimer.C.o Model: BANKED, Lang: ANSI-C -Byte1.C.o Model: BANKED, Lang: ANSI-C -PE_Timer.C.o Model: BANKED, Lang: ANSI-C -comtest.c.o Model: BANKED, Lang: ANSI-C -COM0.C.o Model: BANKED, Lang: ANSI-C -port.c.o Model: BANKED, Lang: ANSI-C -integer.c.o Model: BANKED, Lang: ANSI-C -BlockQ.c.o Model: BANKED, Lang: ANSI-C -death.c.o Model: BANKED, Lang: ANSI-C - -********************************************************************************************* -STARTUP SECTION ---------------------------------------------------------------------------------------------- -Entry point: 0xC000 (_EntryPoint) -_startupData is allocated at 0xC07C and uses 24 Bytes -extern struct _tagStartup { - unsigned flags 0 - _PFunc main 0x30809A (main) - long stackOffset 0x3988 - unsigned nofZeroOut 1 - _Range pZeroOut 0x1000 10505 - _Copy *toCopyDownBeg 0xC3B5 - int nofLibInits 0 - _LibInit *libInits 0xC098 - int nofInitBodies 0 - _Cpp *initBodies 0xC09A - int nofFiniBodies 0 - _Cpp *finiBodies 0xC09A -} _startupData; - -********************************************************************************************* -SECTION-ALLOCATION SECTION -Section Name Size Type From To Segment ---------------------------------------------------------------------------------------------- -.data 1 R/W 0x1000 0x1000 RAM -.text 587 R 0x308000 0x30824A ROM_PAGE30 -.init 124 R 0xC000 0xC07B ROM_C000 -.startData 30 R 0xC07C 0xC099 ROM_C000 -.rodata1 183 R 0xC09A 0xC150 ROM_C000 -NON_BANKED 612 R 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0x398000 0x398196 ROM_PAGE39 -ROM_PAGE3A_533 588 R 0x3A8000 0x3A824B ROM_PAGE3A -ROM_PAGE3B_534 292 R 0x3B8000 0x3B8123 ROM_PAGE3B - -Summary of section sizes per section type: -READ_ONLY (R): 1DD4 (dec: 7636) -READ_WRITE (R/W): 2989 (dec: 10633) -NO_INIT (N/I): 241 (dec: 577) - -********************************************************************************************* -VECTOR-ALLOCATION SECTION - Address InitValue InitFunction ---------------------------------------------------------------------------------------------- - -********************************************************************************************* -OBJECT-ALLOCATION SECTION - Name Module Addr hSize dSize Ref Section RLIB ---------------------------------------------------------------------------------------------- -MODULE: -- Start12.c.o -- -- PROCEDURES: - Init 308000 29 41 2 .text - _Startup C151 12 18 1 NON_BANKED -- VARIABLES: - _startupData C07C 18 24 6 .startData -MODULE: -- STRING.C.o (ansibi.lib) -- -- PROCEDURES: - memcpy 308029 26 38 8 .text - memset 30804F 1E 30 2 .text - strncpy 30806D 2D 45 2 .text -- VARIABLES: -MODULE: -- rtshc12.c.o (ansibi.lib) -- -- PROCEDURES: - _LCMP C163 19 25 2 NON_BANKED - _LCMP_P C17C 15 21 3 NON_BANKED - _LNEG C191 D 13 2 NON_BANKED - _LINC C19E 5 5 4 NON_BANKED - _LMUL C1A3 27 39 1 NON_BANKED - _lDivMod C1CA E3 227 3 NON_BANKED - _LDIVU C2AD E 14 1 NON_BANKED - _NEG_P C2BB F 15 4 NON_BANKED - _LDIVS C2CA 35 53 2 NON_BANKED -- VARIABLES: -MODULE: -- Cpu.C.o -- -- PROCEDURES: - _EntryPoint C000 2E 46 1 .init - PE_low_level_init C02E 4E 78 2 .init - Cpu_Interrupt C2FF 1 1 60 NON_BANKED -- VARIABLES: -MODULE: -- IO_Map.C.o -- -- PROCEDURES: -- VARIABLES: - _ARMCOP 3F 1 1 0 .abs_section_3f - _ATD0DIEN 8D 1 1 0 .abs_section_8d - _ATD0STAT0 86 1 1 0 .abs_section_86 - _ATD0STAT1 8B 1 1 0 .abs_section_8b - _ATD1DIEN 12D 1 1 0 .abs_section_12d - _ATD1STAT0 126 1 1 0 .abs_section_126 - _ATD1STAT1 12B 1 1 0 .abs_section_12b - _BDMCCR FF06 1 1 0 .abs_section_ff06 - _BDMINR FF07 1 1 0 .abs_section_ff07 - _BDMSTS FF01 1 1 0 .abs_section_ff01 - _BKP0H 2B 1 1 0 .abs_section_2b - _BKP0L 2C 1 1 0 .abs_section_2c - _BKP0X 2A 1 1 0 .abs_section_2a - _BKP1H 2E 1 1 0 .abs_section_2e - _BKP1L 2F 1 1 0 .abs_section_2f - _BKP1X 2D 1 1 0 .abs_section_2d - _BKPCT0 28 1 1 0 .abs_section_28 - _BKPCT1 29 1 1 0 .abs_section_29 - _CAN0BTR0 142 1 1 0 .abs_section_142 - _CAN0BTR1 143 1 1 0 .abs_section_143 - _CAN0CTL0 140 1 1 0 .abs_section_140 - _CAN0CTL1 141 1 1 0 .abs_section_141 - _CAN0IDAC 14B 1 1 0 .abs_section_14b - _CAN0IDAR0 150 1 1 0 .abs_section_150 - _CAN0IDAR1 151 1 1 0 .abs_section_151 - _CAN0IDAR2 152 1 1 0 .abs_section_152 - _CAN0IDAR3 153 1 1 0 .abs_section_153 - _CAN0IDAR4 158 1 1 0 .abs_section_158 - _CAN0IDAR5 159 1 1 0 .abs_section_159 - _CAN0IDAR6 15A 1 1 0 .abs_section_15a - _CAN0IDAR7 15B 1 1 0 .abs_section_15b - _CAN0IDMR0 154 1 1 0 .abs_section_154 - _CAN0IDMR1 155 1 1 0 .abs_section_155 - _CAN0IDMR2 156 1 1 0 .abs_section_156 - _CAN0IDMR3 157 1 1 0 .abs_section_157 - _CAN0IDMR4 15C 1 1 0 .abs_section_15c - _CAN0IDMR5 15D 1 1 0 .abs_section_15d - _CAN0IDMR6 15E 1 1 0 .abs_section_15e - _CAN0IDMR7 15F 1 1 0 .abs_section_15f - _CAN0RFLG 144 1 1 0 .abs_section_144 - _CAN0RIER 145 1 1 0 .abs_section_145 - _CAN0RXDLR 16C 1 1 0 .abs_section_16c - _CAN0RXDSR0 164 1 1 0 .abs_section_164 - _CAN0RXDSR1 165 1 1 0 .abs_section_165 - _CAN0RXDSR2 166 1 1 0 .abs_section_166 - _CAN0RXDSR3 167 1 1 0 .abs_section_167 - _CAN0RXDSR4 168 1 1 0 .abs_section_168 - _CAN0RXDSR5 169 1 1 0 .abs_section_169 - _CAN0RXDSR6 16A 1 1 0 .abs_section_16a - _CAN0RXDSR7 16B 1 1 0 .abs_section_16b - _CAN0RXERR 14E 1 1 0 .abs_section_14e - _CAN0RXIDR0 160 1 1 0 .abs_section_160 - _CAN0RXIDR1 161 1 1 0 .abs_section_161 - _CAN0RXIDR2 162 1 1 0 .abs_section_162 - _CAN0RXIDR3 163 1 1 0 .abs_section_163 - _CAN0TAAK 149 1 1 0 .abs_section_149 - _CAN0TARQ 148 1 1 0 .abs_section_148 - _CAN0TBSEL 14A 1 1 0 .abs_section_14a - _CAN0TFLG 146 1 1 0 .abs_section_146 - _CAN0TIER 147 1 1 0 .abs_section_147 - _CAN0TXDLR 17C 1 1 0 .abs_section_17c - _CAN0TXDSR0 174 1 1 0 .abs_section_174 - _CAN0TXDSR1 175 1 1 0 .abs_section_175 - _CAN0TXDSR2 176 1 1 0 .abs_section_176 - _CAN0TXDSR3 177 1 1 0 .abs_section_177 - _CAN0TXDSR4 178 1 1 0 .abs_section_178 - _CAN0TXDSR5 179 1 1 0 .abs_section_179 - _CAN0TXDSR6 17A 1 1 0 .abs_section_17a - _CAN0TXDSR7 17B 1 1 0 .abs_section_17b - _CAN0TXERR 14F 1 1 0 .abs_section_14f - _CAN0TXIDR0 170 1 1 0 .abs_section_170 - _CAN0TXIDR1 171 1 1 0 .abs_section_171 - _CAN0TXIDR2 172 1 1 0 .abs_section_172 - _CAN0TXIDR3 173 1 1 0 .abs_section_173 - _CAN0TXTBPR 17F 1 1 0 .abs_section_17f - _CAN1BTR0 182 1 1 0 .abs_section_182 - _CAN1BTR1 183 1 1 0 .abs_section_183 - _CAN1CTL0 180 1 1 0 .abs_section_180 - _CAN1CTL1 181 1 1 0 .abs_section_181 - _CAN1IDAC 18B 1 1 0 .abs_section_18b - _CAN1IDAR0 190 1 1 0 .abs_section_190 - _CAN1IDAR1 191 1 1 0 .abs_section_191 - _CAN1IDAR2 192 1 1 0 .abs_section_192 - _CAN1IDAR3 193 1 1 0 .abs_section_193 - _CAN1IDAR4 198 1 1 0 .abs_section_198 - _CAN1IDAR5 199 1 1 0 .abs_section_199 - _CAN1IDAR6 19A 1 1 0 .abs_section_19a - _CAN1IDAR7 19B 1 1 0 .abs_section_19b - _CAN1IDMR0 194 1 1 0 .abs_section_194 - _CAN1IDMR1 195 1 1 0 .abs_section_195 - _CAN1IDMR2 196 1 1 0 .abs_section_196 - _CAN1IDMR3 197 1 1 0 .abs_section_197 - _CAN1IDMR4 19C 1 1 0 .abs_section_19c - _CAN1IDMR5 19D 1 1 0 .abs_section_19d - _CAN1IDMR6 19E 1 1 0 .abs_section_19e - _CAN1IDMR7 19F 1 1 0 .abs_section_19f - _CAN1RFLG 184 1 1 0 .abs_section_184 - _CAN1RIER 185 1 1 0 .abs_section_185 - _CAN1RXDLR 1AC 1 1 0 .abs_section_1ac - _CAN1RXDSR0 1A4 1 1 0 .abs_section_1a4 - _CAN1RXDSR1 1A5 1 1 0 .abs_section_1a5 - _CAN1RXDSR2 1A6 1 1 0 .abs_section_1a6 - _CAN1RXDSR3 1A7 1 1 0 .abs_section_1a7 - _CAN1RXDSR4 1A8 1 1 0 .abs_section_1a8 - _CAN1RXDSR5 1A9 1 1 0 .abs_section_1a9 - _CAN1RXDSR6 1AA 1 1 0 .abs_section_1aa - _CAN1RXDSR7 1AB 1 1 0 .abs_section_1ab - _CAN1RXERR 18E 1 1 0 .abs_section_18e - _CAN1RXIDR0 1A0 1 1 0 .abs_section_1a0 - _CAN1RXIDR1 1A1 1 1 0 .abs_section_1a1 - _CAN1RXIDR2 1A2 1 1 0 .abs_section_1a2 - _CAN1RXIDR3 1A3 1 1 0 .abs_section_1a3 - _CAN1TAAK 189 1 1 0 .abs_section_189 - _CAN1TARQ 188 1 1 0 .abs_section_188 - _CAN1TBSEL 18A 1 1 0 .abs_section_18a - _CAN1TFLG 186 1 1 0 .abs_section_186 - _CAN1TIER 187 1 1 0 .abs_section_187 - _CAN1TXDLR 1BC 1 1 0 .abs_section_1bc - _CAN1TXDSR0 1B4 1 1 0 .abs_section_1b4 - _CAN1TXDSR1 1B5 1 1 0 .abs_section_1b5 - _CAN1TXDSR2 1B6 1 1 0 .abs_section_1b6 - _CAN1TXDSR3 1B7 1 1 0 .abs_section_1b7 - _CAN1TXDSR4 1B8 1 1 0 .abs_section_1b8 - _CAN1TXDSR5 1B9 1 1 0 .abs_section_1b9 - _CAN1TXDSR6 1BA 1 1 0 .abs_section_1ba - _CAN1TXDSR7 1BB 1 1 0 .abs_section_1bb - _CAN1TXERR 18F 1 1 0 .abs_section_18f - _CAN1TXIDR0 1B0 1 1 0 .abs_section_1b0 - _CAN1TXIDR1 1B1 1 1 0 .abs_section_1b1 - _CAN1TXIDR2 1B2 1 1 0 .abs_section_1b2 - _CAN1TXIDR3 1B3 1 1 0 .abs_section_1b3 - _CAN1TXTBPR 1BF 1 1 0 .abs_section_1bf - _CAN2BTR0 1C2 1 1 0 .abs_section_1c2 - _CAN2BTR1 1C3 1 1 0 .abs_section_1c3 - _CAN2CTL0 1C0 1 1 0 .abs_section_1c0 - _CAN2CTL1 1C1 1 1 0 .abs_section_1c1 - _CAN2IDAC 1CB 1 1 0 .abs_section_1cb - _CAN2IDAR0 1D0 1 1 0 .abs_section_1d0 - _CAN2IDAR1 1D1 1 1 0 .abs_section_1d1 - _CAN2IDAR2 1D2 1 1 0 .abs_section_1d2 - _CAN2IDAR3 1D3 1 1 0 .abs_section_1d3 - _CAN2IDAR4 1D8 1 1 0 .abs_section_1d8 - _CAN2IDAR5 1D9 1 1 0 .abs_section_1d9 - _CAN2IDAR6 1DA 1 1 0 .abs_section_1da - _CAN2IDAR7 1DB 1 1 0 .abs_section_1db - _CAN2IDMR0 1D4 1 1 0 .abs_section_1d4 - _CAN2IDMR1 1D5 1 1 0 .abs_section_1d5 - _CAN2IDMR2 1D6 1 1 0 .abs_section_1d6 - _CAN2IDMR3 1D7 1 1 0 .abs_section_1d7 - _CAN2IDMR4 1DC 1 1 0 .abs_section_1dc - _CAN2IDMR5 1DD 1 1 0 .abs_section_1dd - _CAN2IDMR6 1DE 1 1 0 .abs_section_1de - _CAN2IDMR7 1DF 1 1 0 .abs_section_1df - _CAN2RFLG 1C4 1 1 0 .abs_section_1c4 - _CAN2RIER 1C5 1 1 0 .abs_section_1c5 - _CAN2RXDLR 1EC 1 1 0 .abs_section_1ec - _CAN2RXDSR0 1E4 1 1 0 .abs_section_1e4 - _CAN2RXDSR1 1E5 1 1 0 .abs_section_1e5 - _CAN2RXDSR2 1E6 1 1 0 .abs_section_1e6 - _CAN2RXDSR3 1E7 1 1 0 .abs_section_1e7 - _CAN2RXDSR4 1E8 1 1 0 .abs_section_1e8 - _CAN2RXDSR5 1E9 1 1 0 .abs_section_1e9 - _CAN2RXDSR6 1EA 1 1 0 .abs_section_1ea - _CAN2RXDSR7 1EB 1 1 0 .abs_section_1eb - _CAN2RXERR 1CE 1 1 0 .abs_section_1ce - _CAN2RXIDR0 1E0 1 1 0 .abs_section_1e0 - _CAN2RXIDR1 1E1 1 1 0 .abs_section_1e1 - _CAN2RXIDR2 1E2 1 1 0 .abs_section_1e2 - _CAN2RXIDR3 1E3 1 1 0 .abs_section_1e3 - _CAN2TAAK 1C9 1 1 0 .abs_section_1c9 - _CAN2TARQ 1C8 1 1 0 .abs_section_1c8 - _CAN2TBSEL 1CA 1 1 0 .abs_section_1ca - _CAN2TFLG 1C6 1 1 0 .abs_section_1c6 - _CAN2TIER 1C7 1 1 0 .abs_section_1c7 - _CAN2TXDLR 1FC 1 1 0 .abs_section_1fc - _CAN2TXDSR0 1F4 1 1 0 .abs_section_1f4 - _CAN2TXDSR1 1F5 1 1 0 .abs_section_1f5 - _CAN2TXDSR2 1F6 1 1 0 .abs_section_1f6 - _CAN2TXDSR3 1F7 1 1 0 .abs_section_1f7 - _CAN2TXDSR4 1F8 1 1 0 .abs_section_1f8 - _CAN2TXDSR5 1F9 1 1 0 .abs_section_1f9 - _CAN2TXDSR6 1FA 1 1 0 .abs_section_1fa - _CAN2TXDSR7 1FB 1 1 0 .abs_section_1fb - _CAN2TXERR 1CF 1 1 0 .abs_section_1cf - _CAN2TXIDR0 1F0 1 1 0 .abs_section_1f0 - _CAN2TXIDR1 1F1 1 1 0 .abs_section_1f1 - _CAN2TXIDR2 1F2 1 1 0 .abs_section_1f2 - _CAN2TXIDR3 1F3 1 1 0 .abs_section_1f3 - _CAN2TXTBPR 1FF 1 1 0 .abs_section_1ff - _CAN3BTR0 202 1 1 0 .abs_section_202 - _CAN3BTR1 203 1 1 0 .abs_section_203 - _CAN3CTL0 200 1 1 0 .abs_section_200 - _CAN3CTL1 201 1 1 0 .abs_section_201 - _CAN3IDAC 20B 1 1 0 .abs_section_20b - _CAN3IDAR0 210 1 1 0 .abs_section_210 - _CAN3IDAR1 211 1 1 0 .abs_section_211 - _CAN3IDAR2 212 1 1 0 .abs_section_212 - _CAN3IDAR3 213 1 1 0 .abs_section_213 - _CAN3IDAR4 218 1 1 0 .abs_section_218 - _CAN3IDAR5 219 1 1 0 .abs_section_219 - _CAN3IDAR6 21A 1 1 0 .abs_section_21a - _CAN3IDAR7 21B 1 1 0 .abs_section_21b - _CAN3IDMR0 214 1 1 0 .abs_section_214 - _CAN3IDMR1 215 1 1 0 .abs_section_215 - _CAN3IDMR2 216 1 1 0 .abs_section_216 - _CAN3IDMR3 217 1 1 0 .abs_section_217 - _CAN3IDMR4 21C 1 1 0 .abs_section_21c - _CAN3IDMR5 21D 1 1 0 .abs_section_21d - _CAN3IDMR6 21E 1 1 0 .abs_section_21e - _CAN3IDMR7 21F 1 1 0 .abs_section_21f - _CAN3RFLG 204 1 1 0 .abs_section_204 - _CAN3RIER 205 1 1 0 .abs_section_205 - _CAN3RXDLR 22C 1 1 0 .abs_section_22c - _CAN3RXDSR0 224 1 1 0 .abs_section_224 - _CAN3RXDSR1 225 1 1 0 .abs_section_225 - _CAN3RXDSR2 226 1 1 0 .abs_section_226 - _CAN3RXDSR3 227 1 1 0 .abs_section_227 - _CAN3RXDSR4 228 1 1 0 .abs_section_228 - _CAN3RXDSR5 229 1 1 0 .abs_section_229 - _CAN3RXDSR6 22A 1 1 0 .abs_section_22a - _CAN3RXDSR7 22B 1 1 0 .abs_section_22b - _CAN3RXERR 20E 1 1 0 .abs_section_20e - _CAN3RXIDR0 220 1 1 0 .abs_section_220 - _CAN3RXIDR1 221 1 1 0 .abs_section_221 - _CAN3RXIDR2 222 1 1 0 .abs_section_222 - _CAN3RXIDR3 223 1 1 0 .abs_section_223 - _CAN3TAAK 209 1 1 0 .abs_section_209 - _CAN3TARQ 208 1 1 0 .abs_section_208 - _CAN3TBSEL 20A 1 1 0 .abs_section_20a - _CAN3TFLG 206 1 1 0 .abs_section_206 - _CAN3TIER 207 1 1 0 .abs_section_207 - _CAN3TXDLR 23C 1 1 0 .abs_section_23c - _CAN3TXDSR0 234 1 1 0 .abs_section_234 - _CAN3TXDSR1 235 1 1 0 .abs_section_235 - _CAN3TXDSR2 236 1 1 0 .abs_section_236 - _CAN3TXDSR3 237 1 1 0 .abs_section_237 - _CAN3TXDSR4 238 1 1 0 .abs_section_238 - _CAN3TXDSR5 239 1 1 0 .abs_section_239 - _CAN3TXDSR6 23A 1 1 0 .abs_section_23a - _CAN3TXDSR7 23B 1 1 0 .abs_section_23b - _CAN3TXERR 20F 1 1 0 .abs_section_20f - _CAN3TXIDR0 230 1 1 0 .abs_section_230 - _CAN3TXIDR1 231 1 1 0 .abs_section_231 - _CAN3TXIDR2 232 1 1 0 .abs_section_232 - _CAN3TXIDR3 233 1 1 0 .abs_section_233 - _CAN3TXTBPR 23F 1 1 0 .abs_section_23f - _CAN4BTR0 282 1 1 0 .abs_section_282 - _CAN4BTR1 283 1 1 0 .abs_section_283 - _CAN4CTL0 280 1 1 0 .abs_section_280 - _CAN4CTL1 281 1 1 0 .abs_section_281 - _CAN4IDAC 28B 1 1 0 .abs_section_28b - _CAN4IDAR0 290 1 1 0 .abs_section_290 - _CAN4IDAR1 291 1 1 0 .abs_section_291 - _CAN4IDAR2 292 1 1 0 .abs_section_292 - _CAN4IDAR3 293 1 1 0 .abs_section_293 - _CAN4IDAR4 298 1 1 0 .abs_section_298 - _CAN4IDAR5 299 1 1 0 .abs_section_299 - _CAN4IDAR6 29A 1 1 0 .abs_section_29a - _CAN4IDAR7 29B 1 1 0 .abs_section_29b - _CAN4IDMR0 294 1 1 0 .abs_section_294 - _CAN4IDMR1 295 1 1 0 .abs_section_295 - _CAN4IDMR2 296 1 1 0 .abs_section_296 - _CAN4IDMR3 297 1 1 0 .abs_section_297 - _CAN4IDMR4 29C 1 1 0 .abs_section_29c - _CAN4IDMR5 29D 1 1 0 .abs_section_29d - _CAN4IDMR6 29E 1 1 0 .abs_section_29e - _CAN4IDMR7 29F 1 1 0 .abs_section_29f - _CAN4RFLG 284 1 1 0 .abs_section_284 - _CAN4RIER 285 1 1 0 .abs_section_285 - _CAN4RXDLR 2AC 1 1 0 .abs_section_2ac - _CAN4RXDSR0 2A4 1 1 0 .abs_section_2a4 - _CAN4RXDSR1 2A5 1 1 0 .abs_section_2a5 - _CAN4RXDSR2 2A6 1 1 0 .abs_section_2a6 - _CAN4RXDSR3 2A7 1 1 0 .abs_section_2a7 - _CAN4RXDSR4 2A8 1 1 0 .abs_section_2a8 - _CAN4RXDSR5 2A9 1 1 0 .abs_section_2a9 - _CAN4RXDSR6 2AA 1 1 0 .abs_section_2aa - _CAN4RXDSR7 2AB 1 1 0 .abs_section_2ab - _CAN4RXERR 28E 1 1 0 .abs_section_28e - _CAN4RXIDR0 2A0 1 1 0 .abs_section_2a0 - _CAN4RXIDR1 2A1 1 1 0 .abs_section_2a1 - _CAN4RXIDR2 2A2 1 1 0 .abs_section_2a2 - _CAN4RXIDR3 2A3 1 1 0 .abs_section_2a3 - _CAN4TAAK 289 1 1 0 .abs_section_289 - _CAN4TARQ 288 1 1 0 .abs_section_288 - _CAN4TBSEL 28A 1 1 0 .abs_section_28a - _CAN4TFLG 286 1 1 0 .abs_section_286 - _CAN4TIER 287 1 1 0 .abs_section_287 - _CAN4TXDLR 2BC 1 1 0 .abs_section_2bc - _CAN4TXDSR0 2B4 1 1 0 .abs_section_2b4 - _CAN4TXDSR1 2B5 1 1 0 .abs_section_2b5 - _CAN4TXDSR2 2B6 1 1 0 .abs_section_2b6 - _CAN4TXDSR3 2B7 1 1 0 .abs_section_2b7 - _CAN4TXDSR4 2B8 1 1 0 .abs_section_2b8 - _CAN4TXDSR5 2B9 1 1 0 .abs_section_2b9 - _CAN4TXDSR6 2BA 1 1 0 .abs_section_2ba - _CAN4TXDSR7 2BB 1 1 0 .abs_section_2bb - _CAN4TXERR 28F 1 1 0 .abs_section_28f - _CAN4TXIDR0 2B0 1 1 0 .abs_section_2b0 - _CAN4TXIDR1 2B1 1 1 0 .abs_section_2b1 - _CAN4TXIDR2 2B2 1 1 0 .abs_section_2b2 - _CAN4TXIDR3 2B3 1 1 0 .abs_section_2b3 - _CAN4TXTBPR 2BF 1 1 0 .abs_section_2bf - _CFORC 41 1 1 0 .abs_section_41 - _CLKSEL 39 1 1 3 .abs_section_39 - _COPCTL 3C 1 1 0 .abs_section_3c - _CRGFLG 37 1 1 1 .abs_section_37 - _CRGINT 38 1 1 0 .abs_section_38 - _CTCTL 3E 1 1 0 .abs_section_3e - _CTFLG 36 1 1 0 .abs_section_36 - _DDRE 9 1 1 0 .abs_section_9 - _DDRH 262 1 1 0 .abs_section_262 - _DDRJ 26A 1 1 0 .abs_section_26a - _DDRK 33 1 1 0 .abs_section_33 - _DDRM 252 1 1 0 .abs_section_252 - _DDRP 25A 1 1 0 .abs_section_25a - _DDRS 24A 1 1 2 .abs_section_24a - _DDRT 242 1 1 0 .abs_section_242 - _DLCBARD EC 1 1 0 .abs_section_ec - _DLCBCR1 E8 1 1 0 .abs_section_e8 - _DLCBCR2 EA 1 1 0 .abs_section_ea - _DLCBDR EB 1 1 0 .abs_section_eb - _DLCBRSR ED 1 1 0 .abs_section_ed - _DLCBSVR E9 1 1 0 .abs_section_e9 - _DLCSCR EE 1 1 0 .abs_section_ee - _DLYCT 69 1 1 0 .abs_section_69 - _EBICTL E 1 1 0 .abs_section_e - _ECLKDIV 110 1 1 0 .abs_section_110 - _ECMD 116 1 1 0 .abs_section_116 - _ECNFG 113 1 1 0 .abs_section_113 - _EPROT 114 1 1 0 .abs_section_114 - _ESTAT 115 1 1 0 .abs_section_115 - _FCLKDIV 100 1 1 0 .abs_section_100 - _FCMD 106 1 1 0 .abs_section_106 - _FCNFG 103 1 1 0 .abs_section_103 - _FORBYP 3D 1 1 0 .abs_section_3d - _FPROT 104 1 1 0 .abs_section_104 - _FSEC 101 1 1 0 .abs_section_101 - _FSTAT 105 1 1 0 .abs_section_105 - _HPRIO 1F 1 1 0 .abs_section_1f - _IBAD E0 1 1 0 .abs_section_e0 - _IBCR E2 1 1 0 .abs_section_e2 - _IBDR E4 1 1 0 .abs_section_e4 - _IBFD E1 1 1 0 .abs_section_e1 - _IBSR E3 1 1 0 .abs_section_e3 - _ICOVW 6A 1 1 0 .abs_section_6a - _ICPAR 68 1 1 0 .abs_section_68 - _ICSYS 6B 1 1 1 .abs_section_6b - _INITEE 12 1 1 1 .abs_section_12 - _INITRG 11 1 1 0 .abs_section_11 - _INITRM 10 1 1 1 .abs_section_10 - _INTCR 1E 1 1 1 .abs_section_1e - _ITCR 15 1 1 0 .abs_section_15 - _ITEST 16 1 1 0 .abs_section_16 - _MCCTL 66 1 1 1 .abs_section_66 - _MCFLG 67 1 1 0 .abs_section_67 - _MEMSIZ0 1C 1 1 0 .abs_section_1c - _MEMSIZ1 1D 1 1 0 .abs_section_1d - _MISC 13 1 1 1 .abs_section_13 - _MODE B 1 1 0 .abs_section_b - _MODRR 257 1 1 0 .abs_section_257 - _MTST0 14 1 1 0 .abs_section_14 - _MTST1 17 1 1 0 .abs_section_17 - _OC7D 43 1 1 0 .abs_section_43 - _OC7M 42 1 1 0 .abs_section_42 - _PACTL 60 1 1 0 .abs_section_60 - _PAFLG 61 1 1 0 .abs_section_61 - _PARTIDH 1A 1 1 0 .abs_section_1a - _PARTIDL 1B 1 1 0 .abs_section_1b - _PBCTL 70 1 1 0 .abs_section_70 - _PBFLG 71 1 1 0 .abs_section_71 - _PEAR A 1 1 0 .abs_section_a - _PERH 264 1 1 0 .abs_section_264 - _PERJ 26C 1 1 0 .abs_section_26c - _PERM 254 1 1 0 .abs_section_254 - _PERP 25C 1 1 0 .abs_section_25c - _PERS 24C 1 1 0 .abs_section_24c - _PERT 244 1 1 0 .abs_section_244 - _PIEH 266 1 1 0 .abs_section_266 - _PIEJ 26E 1 1 0 .abs_section_26e - _PIEP 25E 1 1 0 .abs_section_25e - _PIFH 267 1 1 0 .abs_section_267 - _PIFJ 26F 1 1 0 .abs_section_26f - _PIFP 25F 1 1 0 .abs_section_25f - _PLLCTL 3A 1 1 3 .abs_section_3a - _PORTAD0 8F 1 1 0 .abs_section_8f - _PORTAD1 12F 1 1 0 .abs_section_12f - _PORTE 8 1 1 0 .abs_section_8 - _PORTK 32 1 1 0 .abs_section_32 - _PPAGE 30 1 1 0 .abs_section_30 - _PPSH 265 1 1 0 .abs_section_265 - _PPSJ 26D 1 1 0 .abs_section_26d - _PPSM 255 1 1 0 .abs_section_255 - _PPSP 25D 1 1 0 .abs_section_25d - _PPSS 24D 1 1 0 .abs_section_24d - _PPST 245 1 1 0 .abs_section_245 - _PTH 260 1 1 0 .abs_section_260 - _PTIH 261 1 1 0 .abs_section_261 - _PTIJ 269 1 1 0 .abs_section_269 - _PTIM 251 1 1 0 .abs_section_251 - _PTIP 259 1 1 0 .abs_section_259 - _PTIS 249 1 1 0 .abs_section_249 - _PTIT 241 1 1 0 .abs_section_241 - _PTJ 268 1 1 0 .abs_section_268 - _PTM 250 1 1 0 .abs_section_250 - _PTP 258 1 1 0 .abs_section_258 - _PTS 248 1 1 1 .abs_section_248 - _PTT 240 1 1 0 .abs_section_240 - _PUCR C 1 1 0 .abs_section_c - _PWMCAE A4 1 1 0 .abs_section_a4 - _PWMCLK A2 1 1 0 .abs_section_a2 - _PWMCTL A5 1 1 1 .abs_section_a5 - _PWME A0 1 1 0 .abs_section_a0 - _PWMPOL A1 1 1 0 .abs_section_a1 - _PWMPRCLK A3 1 1 0 .abs_section_a3 - _PWMSCLA A8 1 1 0 .abs_section_a8 - _PWMSCLB A9 1 1 0 .abs_section_a9 - _PWMSDN C4 1 1 1 .abs_section_c4 - _RDRH 263 1 1 0 .abs_section_263 - _RDRIV D 1 1 0 .abs_section_d - _RDRJ 26B 1 1 0 .abs_section_26b - _RDRM 253 1 1 0 .abs_section_253 - _RDRP 25B 1 1 0 .abs_section_25b - _RDRS 24B 1 1 0 .abs_section_24b - _RDRT 243 1 1 0 .abs_section_243 - _REFDV 35 1 1 1 .abs_section_35 - _RTICTL 3B 1 1 0 .abs_section_3b - _SCI0CR1 CA 1 1 1 .abs_section_ca - _SCI0CR2 CB 1 1 7 .abs_section_cb - _SCI0DRH CE 1 1 0 .abs_section_ce - _SCI0DRL CF 1 1 3 .abs_section_cf - _SCI0SR1 CC 1 1 2 .abs_section_cc - _SCI0SR2 CD 1 1 1 .abs_section_cd - _SCI1CR1 D2 1 1 0 .abs_section_d2 - _SCI1CR2 D3 1 1 0 .abs_section_d3 - _SCI1DRH D6 1 1 0 .abs_section_d6 - _SCI1DRL D7 1 1 0 .abs_section_d7 - _SCI1SR1 D4 1 1 0 .abs_section_d4 - _SCI1SR2 D5 1 1 0 .abs_section_d5 - _SPI0BR DA 1 1 0 .abs_section_da - _SPI0CR1 D8 1 1 0 .abs_section_d8 - _SPI0CR2 D9 1 1 0 .abs_section_d9 - _SPI0DR DD 1 1 0 .abs_section_dd - _SPI0SR DB 1 1 0 .abs_section_db - _SPI1BR F2 1 1 0 .abs_section_f2 - _SPI1CR1 F0 1 1 0 .abs_section_f0 - _SPI1CR2 F1 1 1 0 .abs_section_f1 - _SPI1DR F5 1 1 0 .abs_section_f5 - _SPI1SR F3 1 1 0 .abs_section_f3 - _SPI2BR FA 1 1 0 .abs_section_fa - _SPI2CR1 F8 1 1 0 .abs_section_f8 - _SPI2CR2 F9 1 1 0 .abs_section_f9 - _SPI2DR FD 1 1 0 .abs_section_fd - _SPI2SR FB 1 1 0 .abs_section_fb - _SYNR 34 1 1 1 .abs_section_34 - _TCTL1 48 1 1 1 .abs_section_48 - _TCTL2 49 1 1 1 .abs_section_49 - _TCTL3 4A 1 1 0 .abs_section_4a - _TCTL4 4B 1 1 0 .abs_section_4b - _TFLG1 4E 1 1 3 .abs_section_4e - _TFLG2 4F 1 1 0 .abs_section_4f - _TIE 4C 1 1 3 .abs_section_4c - _TIMTST 6D 1 1 0 .abs_section_6d - _TIOS 40 1 1 1 .abs_section_40 - _TSCR1 46 1 1 3 .abs_section_46 - _TSCR2 4D 1 1 5 .abs_section_4d - _TTOV 47 1 1 1 .abs_section_47 - _WOMM 256 1 1 0 .abs_section_256 - _WOMS 24E 1 1 0 .abs_section_24e - _ATD0CTL23 82 2 2 0 .abs_section_82 - _ATD0CTL45 84 2 2 0 .abs_section_84 - _ATD0DR0 90 2 2 0 .abs_section_90 - _ATD0DR1 92 2 2 0 .abs_section_92 - _ATD0DR2 94 2 2 0 .abs_section_94 - _ATD0DR3 96 2 2 0 .abs_section_96 - _ATD0DR4 98 2 2 0 .abs_section_98 - _ATD0DR5 9A 2 2 0 .abs_section_9a - _ATD0DR6 9C 2 2 0 .abs_section_9c - _ATD0DR7 9E 2 2 0 .abs_section_9e - _ATD1CTL23 122 2 2 0 .abs_section_122 - _ATD1CTL45 124 2 2 0 .abs_section_124 - _ATD1DR0 130 2 2 0 .abs_section_130 - _ATD1DR1 132 2 2 0 .abs_section_132 - _ATD1DR2 134 2 2 0 .abs_section_134 - _ATD1DR3 136 2 2 0 .abs_section_136 - _ATD1DR4 138 2 2 0 .abs_section_138 - _ATD1DR5 13A 2 2 0 .abs_section_13a - _ATD1DR6 13C 2 2 0 .abs_section_13c - _ATD1DR7 13E 2 2 0 .abs_section_13e - _DDRAB 2 2 2 1 .abs_section_2 - _MCCNT 76 2 2 0 .abs_section_76 - _PA10H 74 2 2 0 .abs_section_74 - _PA32H 72 2 2 0 .abs_section_72 - _PACN10 64 2 2 0 .abs_section_64 - _PACN32 62 2 2 0 .abs_section_62 - _PORTAB 0 2 2 6 .abs_section_0 - _PWMCNT01 AC 2 2 0 .abs_section_ac - _PWMCNT23 AE 2 2 0 .abs_section_ae - _PWMCNT45 B0 2 2 0 .abs_section_b0 - _PWMCNT67 B2 2 2 0 .abs_section_b2 - _PWMDTY01 BC 2 2 0 .abs_section_bc - _PWMDTY23 BE 2 2 0 .abs_section_be - _PWMDTY45 C0 2 2 0 .abs_section_c0 - _PWMDTY67 C2 2 2 0 .abs_section_c2 - _PWMPER01 B4 2 2 0 .abs_section_b4 - _PWMPER23 B6 2 2 0 .abs_section_b6 - _PWMPER45 B8 2 2 0 .abs_section_b8 - _PWMPER67 BA 2 2 0 .abs_section_ba - _SCI0BD C8 2 2 2 .abs_section_c8 - _SCI1BD D0 2 2 0 .abs_section_d0 - _TC0 50 2 2 2 .abs_section_50 - _TC0H 78 2 2 0 .abs_section_78 - _TC1 52 2 2 0 .abs_section_52 - _TC1H 7A 2 2 0 .abs_section_7a - _TC2 54 2 2 0 .abs_section_54 - _TC2H 7C 2 2 0 .abs_section_7c - _TC3 56 2 2 0 .abs_section_56 - _TC3H 7E 2 2 0 .abs_section_7e - _TC4 58 2 2 0 .abs_section_58 - _TC5 5A 2 2 0 .abs_section_5a - _TC6 5C 2 2 0 .abs_section_5c - _TC7 5E 2 2 2 .abs_section_5e - _TCNT 44 2 2 0 .abs_section_44 -MODULE: -- Vectors.c.o -- -- PROCEDURES: -- VARIABLES: - _vect FF80 80 128 0 .abs_section_ff80 -MODULE: -- RTOSDemo.C.o -- -- PROCEDURES: - main 30809A 9 9 0 .text -- VARIABLES: -MODULE: -- main.c.o -- -- PROCEDURES: - vMain 3080A3 52 82 1 .text - vErrorChecks 3080F5 39 57 3 .text - prvCheckOtherTasksAreStillRunning 30812E 50 80 2 .text - vApplicationIdleHook 30817E 70 112 2 .text -- VARIABLES: - STRING.Check.1 C09A 6 6 1 .rodata1 - xLocalError 1001 1 1 2 .bss -MODULE: -- ParTest.c.o -- -- PROCEDURES: - vParTestSetLED 3081EE 23 35 4 .text - vParTestToggleLED 308211 14 20 10 .text -- VARIABLES: -MODULE: -- serial.c.o -- -- PROCEDURES: - xSerialPortInitMinimal 308225 26 38 2 .text - xSerialGetChar 318000 13 19 4 ROM_PAGE31_524 - xSerialPutChar 318013 18 24 2 ROM_PAGE31_524 - vCOM0_ISR C300 59 89 1 NON_BANKED -- VARIABLES: - xRxedChars 1002 2 2 3 .bss - xCharsForTx 1004 2 2 3 .bss -MODULE: -- tasks.c.o -- -- PROCEDURES: - xTaskCreate 31802B D5 213 48 ROM_PAGE31_524 - vTaskDelete 318100 4A 74 4 ROM_PAGE31_524 - vTaskDelayUntil 31814A 77 119 6 ROM_PAGE31_524 - vTaskDelay 3181C1 46 70 16 ROM_PAGE31_524 - uxTaskPriorityGet 318207 22 34 2 ROM_PAGE31_524 - vTaskPrioritySet 328000 69 105 4 ROM_PAGE32_525 - vTaskSuspend 328069 47 71 6 ROM_PAGE32_525 - vTaskResume 3280B0 5C 92 6 ROM_PAGE32_525 - vTaskStartScheduler 32810C 31 49 2 ROM_PAGE32_525 - vTaskSuspendAll 32813D 13 19 26 ROM_PAGE32_525 - xTaskResumeAll 328150 9F 159 30 ROM_PAGE32_525 - xTaskGetTickCount 3281EF 17 23 6 ROM_PAGE32_525 - uxTaskGetNumberOfTasks 328206 17 23 4 ROM_PAGE32_525 - vTaskIncrementTick 338000 84 132 4 ROM_PAGE33_526 - vTaskSwitchContext 338084 5B 91 4 ROM_PAGE33_526 - vTaskPlaceOnEventList 3380DF 41 65 4 ROM_PAGE33_526 - xTaskRemoveFromEventList 338120 69 105 8 ROM_PAGE33_526 - prvIdleTask 338189 12 18 3 ROM_PAGE33_526 - prvInitialiseTCBVariables 33819B 4D 77 2 ROM_PAGE33_526 - prvInitialiseTaskLists 3381E8 3C 60 2 ROM_PAGE33_526 - prvCheckTasksWaitingTermination 348000 53 83 2 ROM_PAGE34_527 - prvAllocateTCBAndStack 348053 3D 61 2 ROM_PAGE34_527 - prvDeleteTCB 348090 F 15 2 ROM_PAGE34_527 -- VARIABLES: - STRING.IDLE.2 C0A0 5 5 1 .rodata1 - pxCurrentTCB 1006 2 2 28 .bss - uxTasksDeleted 1008 1 1 3 .bss - uxCurrentNumberOfTasks 1009 1 1 5 .bss - xTickCount 100A 2 2 14 .bss - uxTopUsedPriority 100C 1 1 2 .bss - uxTopReadyPriority 100D 1 1 15 .bss - xSchedulerRunning 100E 1 1 3 .bss - uxSchedulerSuspended 100F 1 1 6 .bss - uxMissedTicks 1010 1 1 4 .bss - uxTaskNumber.1 1011 1 1 2 .bss - pxReadyTasksLists 1012 3C 60 11 .bss - xDelayedTaskList1 104E F 15 2 .bss - xDelayedTaskList2 105D F 15 2 .bss - pxDelayedTaskList 106C 2 2 8 .bss - pxOverflowDelayedTaskList 106E 2 2 6 .bss - xPendingReadyList 1070 F 15 4 .bss - xTasksWaitingTermination 107F F 15 5 .bss - xSuspendedTaskList 108E F 15 2 .bss -MODULE: -- queue.c.o -- -- PROCEDURES: - xQueueCreate 34809F 7B 123 14 ROM_PAGE34_527 - xQueueSend 34811A D4 212 9 ROM_PAGE34_527 - xQueueSendFromISR 3481EE 5D 93 2 ROM_PAGE34_527 - xQueueReceive 358000 CF 207 9 ROM_PAGE35_528 - xQueueReceiveFromISR 3580CF 61 97 2 ROM_PAGE35_528 - uxQueueMessagesWaiting 358130 1B 27 2 ROM_PAGE35_528 - prvUnlockQueue 35814B 71 113 8 ROM_PAGE35_528 - prvIsQueueEmpty 3581BC 22 34 2 ROM_PAGE35_528 - prvIsQueueFull 3581DE 25 37 2 ROM_PAGE35_528 -- VARIABLES: -MODULE: -- list.c.o -- -- PROCEDURES: - vListInitialise 358203 20 32 6 ROM_PAGE35_528 - vListInitialiseItem 358223 7 7 6 ROM_PAGE35_528 - vListInsertEnd 35822A 25 37 16 ROM_PAGE35_528 - vListInsert 368000 55 85 8 ROM_PAGE36_529 - vListRemove 368055 23 35 32 ROM_PAGE36_529 -- VARIABLES: -MODULE: -- heap_2.c.o -- -- PROCEDURES: - pvPortMalloc 368078 C1 193 14 ROM_PAGE36_529 - vPortFree 368139 3B 59 10 ROM_PAGE36_529 -- VARIABLES: - xHeapHasBeenInitialised.1 109D 1 1 2 .bss - xHeap 109E 2804 10244 2 .bss - xStart 38A2 4 4 6 .bss - xEnd 38A6 4 4 4 .bss -MODULE: -- flash.c.o -- -- PROCEDURES: - vStartLEDFlashTasks 368174 32 50 2 ROM_PAGE36_529 - vLEDFlashTask 3681A6 57 87 3 ROM_PAGE36_529 -- VARIABLES: - STRING.LEDx.1 C0A5 5 5 1 .rodata1 - uxFlashTaskNumber 38AA 1 1 2 .bss -MODULE: -- dynamic.c.o -- -- PROCEDURES: - vStartDynamicPriorityTasks 378000 9B 155 2 ROM_PAGE37_530 - vLimitedIncrementTask 37809B 27 39 3 ROM_PAGE37_530 - vContinuousIncrementTask 3780C2 38 56 3 ROM_PAGE37_530 - vCounterControlTask 3780FA A0 160 5 ROM_PAGE37_530 - vQueueSendWhenSuspendedTask 37819A 38 56 3 ROM_PAGE37_530 - vQueueReceiveWhenSuspendedTask 3781D2 54 84 3 ROM_PAGE37_530 - xAreDynamicPriorityTasksStillRunning 378226 2B 43 2 ROM_PAGE37_530 -- VARIABLES: - STRING.CNT_INC.1 C0AA 8 8 1 .rodata1 - STRING.LIM_INC.2 C0B2 8 8 1 .rodata1 - STRING.C_CTRL.3 C0BA 7 7 1 .rodata1 - STRING.SUSP_TX.4 C0C1 8 8 1 .rodata1 - STRING.SUSP_RX.5 C0C9 8 8 1 .rodata1 - usCheckVariable 38AB 2 2 3 .bss - xSuspendedQueueSendError 38AD 1 1 2 .bss - xSuspendedQueueReceiveError 38AE 1 1 3 .bss - ulValueToSend.6 38AF 4 4 5 .bss - ulExpectedValue.7 38B3 4 4 6 .bss - usLastTaskCheck.9 38B7 2 2 2 .bss - xContinousIncrementHandle 38B9 2 2 5 .bss - xLimitedIncrementHandle 38BB 2 2 2 .bss - ulCounter 38BD 4 4 10 .bss - ulReceivedValue.8 38C1 4 4 3 .bss - xSuspendedTestQueue 38EC 2 2 3 .common -MODULE: -- PollQ.c.o -- -- PROCEDURES: - vStartPolledQueueTasks 388000 4B 75 2 ROM_PAGE38_531 - vPolledQueueProducer 38804B 4F 79 3 ROM_PAGE38_531 - vPolledQueueConsumer 38809A 5C 92 3 ROM_PAGE38_531 - xArePollingQueuesStillRunning 3880F6 16 22 2 ROM_PAGE38_531 -- VARIABLES: - STRING.QConsNB.2 C0D1 8 8 1 .rodata1 - STRING.QProdNB.3 C0D9 8 8 1 .rodata1 - xPollingConsumerCount 38C5 1 1 3 .bss - xPollingProducerCount 38C6 1 1 3 .bss - xPolledQueue.1 38C7 2 2 3 .bss -MODULE: -- TickTimer.C.o -- -- PROCEDURES: - TickTimer_Enable 3B8124 9 9 2 TickTimer_CODE - TickTimer_SetFreqHz 3B812D 56 86 2 TickTimer_CODE - TickTimer_Init 3B8183 1C 28 2 TickTimer_CODE -- VARIABLES: - CmpHighVal 38F2 2 2 2 TickTimer_DATA -MODULE: -- Byte1.C.o -- -- PROCEDURES: - Byte1_PutBit 3B819F 21 33 2 Byte1_CODE - Byte1_NegBit 3B81C0 14 20 2 Byte1_CODE -- VARIABLES: - Byte1_Table 38F4 8 8 2 Byte1_DATA -MODULE: -- PE_Timer.C.o -- -- PROCEDURES: - PE_Timer_LngHi1 38810C 4A 74 2 ROM_PAGE38_531 -- VARIABLES: -MODULE: -- comtest.c.o -- -- PROCEDURES: - vAltStartComTestTasks 388156 4D 77 2 ROM_PAGE38_531 - vComTxTask 3881A3 4F 79 3 ROM_PAGE38_531 - vComRxTask 398000 7B 123 3 ROM_PAGE39_532 - xAreComTestTasksStillRunning 39807B D 13 2 ROM_PAGE39_532 -- VARIABLES: - STRING.COMTx.1 C0E1 6 6 1 .rodata1 - STRING.COMRx.2 C0E7 6 6 1 .rodata1 - xPort 38C9 2 2 3 .bss - uxBaseLED 38CB 1 1 5 .bss - uxRxLoops 38CC 1 1 3 .bss -MODULE: -- COM0.C.o -- -- PROCEDURES: - COM0_SetBaudRateMode 3B81D4 19 25 2 COM0_CODE - COM0_Init 3B81ED 25 37 2 COM0_CODE -- VARIABLES: - COM0_PrescHigh.1 38FC 8 8 1 COM0_DATA - SerFlag 3904 2 2 1 COM0_DATA - PrescHigh 3906 2 2 2 COM0_DATA - NumMode 3908 1 1 2 COM0_DATA -MODULE: -- port.c.o -- -- PROCEDURES: - pxPortInitialiseStack 398088 31 49 2 ROM_PAGE39_532 - xPortStartScheduler 3980B9 4 4 2 ROM_PAGE39_532 - xBankedStartScheduler C359 1A 26 1 NON_BANKED - vPortYield C373 1D 29 1 NON_BANKED - vPortTickInterrupt C390 25 37 1 NON_BANKED -- VARIABLES: - uxCriticalNesting 1000 1 1 101 .data -MODULE: -- integer.c.o -- -- PROCEDURES: - vStartIntegerMathTasks 3980BD 33 51 2 ROM_PAGE39_532 - vCompeteingIntMathTask 3980F0 87 135 3 ROM_PAGE39_532 - xAreIntegerMathsTaskStillRunning 398177 20 32 2 ROM_PAGE39_532 -- VARIABLES: - STRING.IntMath.1 C0ED 8 8 1 .rodata1 - xTaskCheck 38CD 1 1 3 .bss -MODULE: -- BlockQ.c.o -- -- PROCEDURES: - vStartBlockingQueueTasks 3A8000 143 323 7 ROM_PAGE3A_533 - vBlockingQueueProducer 3A8143 3F 63 9 ROM_PAGE3A_533 - vBlockingQueueConsumer 3A8182 47 71 9 ROM_PAGE3A_533 - xAreBlockingQueuesStillRunning 3A81C9 52 82 2 ROM_PAGE3A_533 -- VARIABLES: - STRING.QConsB1.1 C0F5 8 8 1 .rodata1 - STRING.QProdB2.2 C0FD 8 8 1 .rodata1 - STRING.QProdB3.3 C105 8 8 1 .rodata1 - STRING.QConsB4.4 C10D 8 8 1 .rodata1 - STRING.QProdB5.5 C115 8 8 1 .rodata1 - STRING.QConsB6.6 C11D 8 8 1 .rodata1 - sBlockingConsumerCount 38CE 6 6 4 .bss - sBlockingProducerCount 38D4 6 6 5 .bss - sLastBlockingConsumerCount.7 38DA 6 6 2 .bss - sLastBlockingProducerCount.8 38E0 6 6 2 .bss -MODULE: -- death.c.o -- -- PROCEDURES: - vCreateSuicidalTasks 3A821B 31 49 2 ROM_PAGE3A_533 - vSuicidalTask 3B8000 58 88 12 ROM_PAGE3B_534 - vCreateTasks 3B8058 92 146 4 ROM_PAGE3B_534 - xIsCreateTaskStillRunning 3B80EA 3A 58 2 ROM_PAGE3B_534 -- VARIABLES: - STRING.CREATOR.1 C125 8 8 1 .rodata1 - STRING.SUICIDE1.2 C12D 9 9 1 .rodata1 - STRING.SUICIDE2.3 C136 9 9 1 .rodata1 - STRING.SUICIDE1.4 C13F 9 9 1 .rodata1 - STRING.SUICIDE2.5 C148 9 9 1 .rodata1 - usCreationCount 38E6 2 2 4 .bss - uxTasksRunningAtStart 38E8 1 1 4 .bss - usLastCreationCount.6 38E9 2 2 2 .bss - uxTasksRunningNow.7 38EB 1 1 1 .bss - xCreatedTask1 38EE 2 2 2 .common - xCreatedTask2 38F0 2 2 2 .common - -********************************************************************************************* -MODULE STATISTIC - Name Data Code Const ---------------------------------------------------------------------------------------------- - Start12.c.o 0 59 0 - STRING.C.o (ansibi.lib) 0 113 0 - rtshc12.c.o (ansibi.lib) 0 412 0 - Cpu.C.o 0 125 0 - IO_Map.C.o 577 0 0 - Vectors.c.o 0 0 128 - RTOSDemo.C.o 0 9 0 - main.c.o 1 331 6 - ParTest.c.o 0 55 0 - serial.c.o 4 170 0 - tasks.c.o 151 1758 5 - queue.c.o 0 943 0 - list.c.o 0 196 0 - heap_2.c.o 10253 252 0 - flash.c.o 1 137 5 - dynamic.c.o 28 593 39 - PollQ.c.o 4 268 16 - TickTimer.C.o 2 123 0 - Byte1.C.o 8 53 0 - PE_Timer.C.o 0 74 0 - comtest.c.o 4 292 12 - COM0.C.o 13 62 0 - port.c.o 1 145 0 - integer.c.o 1 218 8 - BlockQ.c.o 24 539 48 - death.c.o 10 341 44 - other 128 30 27 - -********************************************************************************************* -SECTION USE IN OBJECT-ALLOCATION SECTION ---------------------------------------------------------------------------------------------- -SECTION: ".text" - Init memcpy memset strncpy main vMain vErrorChecks - prvCheckOtherTasksAreStillRunning vApplicationIdleHook vParTestSetLED - vParTestToggleLED xSerialPortInitMinimal -SECTION: ".data" - uxCriticalNesting -SECTION: ".bss" - xLocalError xRxedChars xCharsForTx pxCurrentTCB uxTasksDeleted - uxCurrentNumberOfTasks xTickCount uxTopUsedPriority uxTopReadyPriority - xSchedulerRunning uxSchedulerSuspended uxMissedTicks uxTaskNumber.1 - pxReadyTasksLists xDelayedTaskList1 xDelayedTaskList2 pxDelayedTaskList - pxOverflowDelayedTaskList xPendingReadyList xTasksWaitingTermination - xSuspendedTaskList xHeapHasBeenInitialised.1 xHeap xStart xEnd - uxFlashTaskNumber usCheckVariable xSuspendedQueueSendError - xSuspendedQueueReceiveError ulValueToSend.6 ulExpectedValue.7 - usLastTaskCheck.9 xContinousIncrementHandle xLimitedIncrementHandle ulCounter - ulReceivedValue.8 xPollingConsumerCount xPollingProducerCount xPolledQueue.1 - xPort uxBaseLED uxRxLoops xTaskCheck sBlockingConsumerCount - sBlockingProducerCount sLastBlockingConsumerCount.7 - sLastBlockingProducerCount.8 usCreationCount uxTasksRunningAtStart - usLastCreationCount.6 uxTasksRunningNow.7 -SECTION: ".init" - _EntryPoint PE_low_level_init -SECTION: ".rodata1" - STRING.Check.1 STRING.IDLE.2 STRING.LEDx.1 STRING.CNT_INC.1 STRING.LIM_INC.2 - STRING.C_CTRL.3 STRING.SUSP_TX.4 STRING.SUSP_RX.5 STRING.QConsNB.2 - STRING.QProdNB.3 STRING.COMTx.1 STRING.COMRx.2 STRING.IntMath.1 - STRING.QConsB1.1 STRING.QProdB2.2 STRING.QProdB3.3 STRING.QConsB4.4 - STRING.QProdB5.5 STRING.QConsB6.6 STRING.CREATOR.1 STRING.SUICIDE1.2 - STRING.SUICIDE2.3 STRING.SUICIDE1.4 STRING.SUICIDE2.5 -SECTION: "NON_BANKED" - _Startup _LCMP _LCMP_P _LNEG _LINC _LMUL _lDivMod _LDIVU _NEG_P _LDIVS - Cpu_Interrupt vCOM0_ISR xBankedStartScheduler vPortYield vPortTickInterrupt -SECTION: ".common" - xSuspendedTestQueue xCreatedTask1 xCreatedTask2 -SECTION: "TickTimer_CODE" - TickTimer_Enable TickTimer_SetFreqHz TickTimer_Init -SECTION: "Byte1_CODE" - Byte1_PutBit Byte1_NegBit -SECTION: "COM0_CODE" - COM0_SetBaudRateMode COM0_Init -SECTION: ".abs_section_3f" - _ARMCOP -SECTION: ".abs_section_8d" - _ATD0DIEN -SECTION: ".abs_section_86" - _ATD0STAT0 -SECTION: ".abs_section_8b" - _ATD0STAT1 -SECTION: ".abs_section_12d" - _ATD1DIEN -SECTION: ".abs_section_126" - _ATD1STAT0 -SECTION: ".abs_section_12b" - _ATD1STAT1 -SECTION: ".abs_section_ff06" - _BDMCCR -SECTION: ".abs_section_ff07" - _BDMINR -SECTION: ".abs_section_ff01" - _BDMSTS -SECTION: ".abs_section_2b" - _BKP0H -SECTION: ".abs_section_2c" - _BKP0L -SECTION: ".abs_section_2a" - _BKP0X -SECTION: ".abs_section_2e" - _BKP1H -SECTION: ".abs_section_2f" - _BKP1L -SECTION: ".abs_section_2d" - _BKP1X -SECTION: ".abs_section_28" - _BKPCT0 -SECTION: ".abs_section_29" - _BKPCT1 -SECTION: ".abs_section_142" - _CAN0BTR0 -SECTION: ".abs_section_143" - _CAN0BTR1 -SECTION: ".abs_section_140" - _CAN0CTL0 -SECTION: ".abs_section_141" - _CAN0CTL1 -SECTION: ".abs_section_14b" - _CAN0IDAC -SECTION: ".abs_section_150" - _CAN0IDAR0 -SECTION: ".abs_section_151" - _CAN0IDAR1 -SECTION: ".abs_section_152" - _CAN0IDAR2 -SECTION: ".abs_section_153" - _CAN0IDAR3 -SECTION: ".abs_section_158" - _CAN0IDAR4 -SECTION: ".abs_section_159" - _CAN0IDAR5 -SECTION: ".abs_section_15a" - _CAN0IDAR6 -SECTION: ".abs_section_15b" - _CAN0IDAR7 -SECTION: ".abs_section_154" - _CAN0IDMR0 -SECTION: ".abs_section_155" - _CAN0IDMR1 -SECTION: ".abs_section_156" - _CAN0IDMR2 -SECTION: ".abs_section_157" - _CAN0IDMR3 -SECTION: ".abs_section_15c" - _CAN0IDMR4 -SECTION: ".abs_section_15d" - _CAN0IDMR5 -SECTION: ".abs_section_15e" - _CAN0IDMR6 -SECTION: ".abs_section_15f" - _CAN0IDMR7 -SECTION: ".abs_section_144" - _CAN0RFLG -SECTION: ".abs_section_145" - _CAN0RIER -SECTION: ".abs_section_16c" - _CAN0RXDLR -SECTION: ".abs_section_164" - _CAN0RXDSR0 -SECTION: ".abs_section_165" - _CAN0RXDSR1 -SECTION: ".abs_section_166" - _CAN0RXDSR2 -SECTION: ".abs_section_167" - _CAN0RXDSR3 -SECTION: ".abs_section_168" - _CAN0RXDSR4 -SECTION: ".abs_section_169" - _CAN0RXDSR5 -SECTION: ".abs_section_16a" - _CAN0RXDSR6 -SECTION: ".abs_section_16b" - _CAN0RXDSR7 -SECTION: ".abs_section_14e" - _CAN0RXERR -SECTION: ".abs_section_160" - _CAN0RXIDR0 -SECTION: ".abs_section_161" - _CAN0RXIDR1 -SECTION: ".abs_section_162" - _CAN0RXIDR2 -SECTION: ".abs_section_163" - _CAN0RXIDR3 -SECTION: ".abs_section_149" - _CAN0TAAK -SECTION: ".abs_section_148" - _CAN0TARQ -SECTION: ".abs_section_14a" - _CAN0TBSEL -SECTION: ".abs_section_146" - _CAN0TFLG -SECTION: ".abs_section_147" - _CAN0TIER -SECTION: ".abs_section_17c" - _CAN0TXDLR -SECTION: ".abs_section_174" - _CAN0TXDSR0 -SECTION: ".abs_section_175" - _CAN0TXDSR1 -SECTION: ".abs_section_176" - _CAN0TXDSR2 -SECTION: ".abs_section_177" - _CAN0TXDSR3 -SECTION: ".abs_section_178" - _CAN0TXDSR4 -SECTION: ".abs_section_179" - _CAN0TXDSR5 -SECTION: ".abs_section_17a" - _CAN0TXDSR6 -SECTION: ".abs_section_17b" - _CAN0TXDSR7 -SECTION: ".abs_section_14f" - _CAN0TXERR -SECTION: ".abs_section_170" - _CAN0TXIDR0 -SECTION: ".abs_section_171" - _CAN0TXIDR1 -SECTION: ".abs_section_172" - _CAN0TXIDR2 -SECTION: ".abs_section_173" - _CAN0TXIDR3 -SECTION: ".abs_section_17f" - _CAN0TXTBPR -SECTION: ".abs_section_182" - _CAN1BTR0 -SECTION: ".abs_section_183" - _CAN1BTR1 -SECTION: ".abs_section_180" - _CAN1CTL0 -SECTION: ".abs_section_181" - _CAN1CTL1 -SECTION: ".abs_section_18b" - _CAN1IDAC -SECTION: ".abs_section_190" - _CAN1IDAR0 -SECTION: ".abs_section_191" - _CAN1IDAR1 -SECTION: ".abs_section_192" - _CAN1IDAR2 -SECTION: ".abs_section_193" - _CAN1IDAR3 -SECTION: ".abs_section_198" - _CAN1IDAR4 -SECTION: ".abs_section_199" - _CAN1IDAR5 -SECTION: ".abs_section_19a" - _CAN1IDAR6 -SECTION: ".abs_section_19b" - _CAN1IDAR7 -SECTION: ".abs_section_194" - _CAN1IDMR0 -SECTION: ".abs_section_195" - _CAN1IDMR1 -SECTION: ".abs_section_196" - _CAN1IDMR2 -SECTION: ".abs_section_197" - _CAN1IDMR3 -SECTION: ".abs_section_19c" - _CAN1IDMR4 -SECTION: ".abs_section_19d" - _CAN1IDMR5 -SECTION: ".abs_section_19e" - _CAN1IDMR6 -SECTION: ".abs_section_19f" - _CAN1IDMR7 -SECTION: ".abs_section_184" - _CAN1RFLG -SECTION: ".abs_section_185" - _CAN1RIER -SECTION: ".abs_section_1ac" - _CAN1RXDLR -SECTION: ".abs_section_1a4" - _CAN1RXDSR0 -SECTION: ".abs_section_1a5" - _CAN1RXDSR1 -SECTION: ".abs_section_1a6" - _CAN1RXDSR2 -SECTION: ".abs_section_1a7" - _CAN1RXDSR3 -SECTION: ".abs_section_1a8" - _CAN1RXDSR4 -SECTION: ".abs_section_1a9" - _CAN1RXDSR5 -SECTION: ".abs_section_1aa" - _CAN1RXDSR6 -SECTION: ".abs_section_1ab" - _CAN1RXDSR7 -SECTION: ".abs_section_18e" - _CAN1RXERR -SECTION: ".abs_section_1a0" - _CAN1RXIDR0 -SECTION: ".abs_section_1a1" - _CAN1RXIDR1 -SECTION: ".abs_section_1a2" - _CAN1RXIDR2 -SECTION: ".abs_section_1a3" - _CAN1RXIDR3 -SECTION: ".abs_section_189" - _CAN1TAAK -SECTION: ".abs_section_188" - _CAN1TARQ -SECTION: ".abs_section_18a" - _CAN1TBSEL -SECTION: ".abs_section_186" - _CAN1TFLG -SECTION: ".abs_section_187" - _CAN1TIER -SECTION: ".abs_section_1bc" - _CAN1TXDLR -SECTION: ".abs_section_1b4" - _CAN1TXDSR0 -SECTION: ".abs_section_1b5" - _CAN1TXDSR1 -SECTION: ".abs_section_1b6" - _CAN1TXDSR2 -SECTION: ".abs_section_1b7" - _CAN1TXDSR3 -SECTION: ".abs_section_1b8" - _CAN1TXDSR4 -SECTION: ".abs_section_1b9" - _CAN1TXDSR5 -SECTION: ".abs_section_1ba" - _CAN1TXDSR6 -SECTION: ".abs_section_1bb" - _CAN1TXDSR7 -SECTION: ".abs_section_18f" - _CAN1TXERR -SECTION: ".abs_section_1b0" - _CAN1TXIDR0 -SECTION: ".abs_section_1b1" - _CAN1TXIDR1 -SECTION: ".abs_section_1b2" - _CAN1TXIDR2 -SECTION: ".abs_section_1b3" - _CAN1TXIDR3 -SECTION: ".abs_section_1bf" - _CAN1TXTBPR -SECTION: ".abs_section_1c2" - _CAN2BTR0 -SECTION: ".abs_section_1c3" - _CAN2BTR1 -SECTION: ".abs_section_1c0" - _CAN2CTL0 -SECTION: ".abs_section_1c1" - _CAN2CTL1 -SECTION: ".abs_section_1cb" - _CAN2IDAC -SECTION: ".abs_section_1d0" - _CAN2IDAR0 -SECTION: ".abs_section_1d1" - _CAN2IDAR1 -SECTION: ".abs_section_1d2" - _CAN2IDAR2 -SECTION: ".abs_section_1d3" - _CAN2IDAR3 -SECTION: ".abs_section_1d8" - _CAN2IDAR4 -SECTION: ".abs_section_1d9" - _CAN2IDAR5 -SECTION: ".abs_section_1da" - _CAN2IDAR6 -SECTION: ".abs_section_1db" - _CAN2IDAR7 -SECTION: ".abs_section_1d4" - _CAN2IDMR0 -SECTION: ".abs_section_1d5" - _CAN2IDMR1 -SECTION: ".abs_section_1d6" - _CAN2IDMR2 -SECTION: ".abs_section_1d7" - _CAN2IDMR3 -SECTION: ".abs_section_1dc" - _CAN2IDMR4 -SECTION: ".abs_section_1dd" - _CAN2IDMR5 -SECTION: ".abs_section_1de" - _CAN2IDMR6 -SECTION: ".abs_section_1df" - _CAN2IDMR7 -SECTION: ".abs_section_1c4" - _CAN2RFLG -SECTION: ".abs_section_1c5" - _CAN2RIER -SECTION: ".abs_section_1ec" - _CAN2RXDLR -SECTION: ".abs_section_1e4" - _CAN2RXDSR0 -SECTION: ".abs_section_1e5" - _CAN2RXDSR1 -SECTION: ".abs_section_1e6" - _CAN2RXDSR2 -SECTION: ".abs_section_1e7" - _CAN2RXDSR3 -SECTION: ".abs_section_1e8" - _CAN2RXDSR4 -SECTION: ".abs_section_1e9" - _CAN2RXDSR5 -SECTION: ".abs_section_1ea" - _CAN2RXDSR6 -SECTION: ".abs_section_1eb" - _CAN2RXDSR7 -SECTION: ".abs_section_1ce" - _CAN2RXERR -SECTION: ".abs_section_1e0" - _CAN2RXIDR0 -SECTION: ".abs_section_1e1" - _CAN2RXIDR1 -SECTION: ".abs_section_1e2" - _CAN2RXIDR2 -SECTION: ".abs_section_1e3" - _CAN2RXIDR3 -SECTION: ".abs_section_1c9" - _CAN2TAAK -SECTION: ".abs_section_1c8" - _CAN2TARQ -SECTION: ".abs_section_1ca" - _CAN2TBSEL -SECTION: ".abs_section_1c6" - _CAN2TFLG -SECTION: ".abs_section_1c7" - _CAN2TIER -SECTION: ".abs_section_1fc" - _CAN2TXDLR -SECTION: ".abs_section_1f4" - _CAN2TXDSR0 -SECTION: ".abs_section_1f5" - _CAN2TXDSR1 -SECTION: ".abs_section_1f6" - _CAN2TXDSR2 -SECTION: ".abs_section_1f7" - _CAN2TXDSR3 -SECTION: ".abs_section_1f8" - _CAN2TXDSR4 -SECTION: ".abs_section_1f9" - _CAN2TXDSR5 -SECTION: ".abs_section_1fa" - _CAN2TXDSR6 -SECTION: ".abs_section_1fb" - _CAN2TXDSR7 -SECTION: ".abs_section_1cf" - _CAN2TXERR -SECTION: ".abs_section_1f0" - _CAN2TXIDR0 -SECTION: ".abs_section_1f1" - _CAN2TXIDR1 -SECTION: ".abs_section_1f2" - _CAN2TXIDR2 -SECTION: ".abs_section_1f3" - _CAN2TXIDR3 -SECTION: ".abs_section_1ff" - _CAN2TXTBPR -SECTION: ".abs_section_202" - _CAN3BTR0 -SECTION: ".abs_section_203" - _CAN3BTR1 -SECTION: ".abs_section_200" - _CAN3CTL0 -SECTION: ".abs_section_201" - _CAN3CTL1 -SECTION: ".abs_section_20b" - _CAN3IDAC -SECTION: ".abs_section_210" - _CAN3IDAR0 -SECTION: ".abs_section_211" - _CAN3IDAR1 -SECTION: ".abs_section_212" - _CAN3IDAR2 -SECTION: ".abs_section_213" - _CAN3IDAR3 -SECTION: ".abs_section_218" - _CAN3IDAR4 -SECTION: ".abs_section_219" - _CAN3IDAR5 -SECTION: ".abs_section_21a" - _CAN3IDAR6 -SECTION: ".abs_section_21b" - _CAN3IDAR7 -SECTION: ".abs_section_214" - _CAN3IDMR0 -SECTION: ".abs_section_215" - _CAN3IDMR1 -SECTION: ".abs_section_216" - _CAN3IDMR2 -SECTION: ".abs_section_217" - _CAN3IDMR3 -SECTION: ".abs_section_21c" - _CAN3IDMR4 -SECTION: ".abs_section_21d" - _CAN3IDMR5 -SECTION: ".abs_section_21e" - _CAN3IDMR6 -SECTION: ".abs_section_21f" - _CAN3IDMR7 -SECTION: ".abs_section_204" - _CAN3RFLG -SECTION: ".abs_section_205" - _CAN3RIER -SECTION: ".abs_section_22c" - _CAN3RXDLR -SECTION: ".abs_section_224" - _CAN3RXDSR0 -SECTION: ".abs_section_225" - _CAN3RXDSR1 -SECTION: ".abs_section_226" - _CAN3RXDSR2 -SECTION: ".abs_section_227" - _CAN3RXDSR3 -SECTION: ".abs_section_228" - _CAN3RXDSR4 -SECTION: ".abs_section_229" - _CAN3RXDSR5 -SECTION: ".abs_section_22a" - _CAN3RXDSR6 -SECTION: ".abs_section_22b" - _CAN3RXDSR7 -SECTION: ".abs_section_20e" - _CAN3RXERR -SECTION: ".abs_section_220" - _CAN3RXIDR0 -SECTION: ".abs_section_221" - _CAN3RXIDR1 -SECTION: ".abs_section_222" - _CAN3RXIDR2 -SECTION: ".abs_section_223" - _CAN3RXIDR3 -SECTION: ".abs_section_209" - _CAN3TAAK -SECTION: ".abs_section_208" - _CAN3TARQ -SECTION: ".abs_section_20a" - _CAN3TBSEL -SECTION: ".abs_section_206" - _CAN3TFLG -SECTION: ".abs_section_207" - _CAN3TIER -SECTION: ".abs_section_23c" - _CAN3TXDLR -SECTION: ".abs_section_234" - _CAN3TXDSR0 -SECTION: ".abs_section_235" - _CAN3TXDSR1 -SECTION: ".abs_section_236" - _CAN3TXDSR2 -SECTION: ".abs_section_237" - _CAN3TXDSR3 -SECTION: ".abs_section_238" - _CAN3TXDSR4 -SECTION: ".abs_section_239" - _CAN3TXDSR5 -SECTION: ".abs_section_23a" - _CAN3TXDSR6 -SECTION: ".abs_section_23b" - _CAN3TXDSR7 -SECTION: ".abs_section_20f" - _CAN3TXERR -SECTION: ".abs_section_230" - _CAN3TXIDR0 -SECTION: ".abs_section_231" - _CAN3TXIDR1 -SECTION: ".abs_section_232" - _CAN3TXIDR2 -SECTION: ".abs_section_233" - _CAN3TXIDR3 -SECTION: ".abs_section_23f" - _CAN3TXTBPR -SECTION: ".abs_section_282" - _CAN4BTR0 -SECTION: ".abs_section_283" - _CAN4BTR1 -SECTION: ".abs_section_280" - _CAN4CTL0 -SECTION: ".abs_section_281" - _CAN4CTL1 -SECTION: ".abs_section_28b" - _CAN4IDAC -SECTION: ".abs_section_290" - _CAN4IDAR0 -SECTION: ".abs_section_291" - _CAN4IDAR1 -SECTION: ".abs_section_292" - _CAN4IDAR2 -SECTION: ".abs_section_293" - _CAN4IDAR3 -SECTION: ".abs_section_298" - _CAN4IDAR4 -SECTION: ".abs_section_299" - _CAN4IDAR5 -SECTION: ".abs_section_29a" - _CAN4IDAR6 -SECTION: ".abs_section_29b" - _CAN4IDAR7 -SECTION: ".abs_section_294" - _CAN4IDMR0 -SECTION: ".abs_section_295" - _CAN4IDMR1 -SECTION: ".abs_section_296" - _CAN4IDMR2 -SECTION: ".abs_section_297" - _CAN4IDMR3 -SECTION: ".abs_section_29c" - _CAN4IDMR4 -SECTION: ".abs_section_29d" - _CAN4IDMR5 -SECTION: ".abs_section_29e" - _CAN4IDMR6 -SECTION: ".abs_section_29f" - _CAN4IDMR7 -SECTION: ".abs_section_284" - _CAN4RFLG -SECTION: ".abs_section_285" - _CAN4RIER -SECTION: ".abs_section_2ac" - _CAN4RXDLR -SECTION: ".abs_section_2a4" - _CAN4RXDSR0 -SECTION: ".abs_section_2a5" - _CAN4RXDSR1 -SECTION: ".abs_section_2a6" - _CAN4RXDSR2 -SECTION: ".abs_section_2a7" - _CAN4RXDSR3 -SECTION: ".abs_section_2a8" - _CAN4RXDSR4 -SECTION: ".abs_section_2a9" - _CAN4RXDSR5 -SECTION: ".abs_section_2aa" - _CAN4RXDSR6 -SECTION: ".abs_section_2ab" - _CAN4RXDSR7 -SECTION: ".abs_section_28e" - _CAN4RXERR -SECTION: ".abs_section_2a0" - _CAN4RXIDR0 -SECTION: ".abs_section_2a1" - _CAN4RXIDR1 -SECTION: ".abs_section_2a2" - _CAN4RXIDR2 -SECTION: ".abs_section_2a3" - _CAN4RXIDR3 -SECTION: ".abs_section_289" - _CAN4TAAK -SECTION: ".abs_section_288" - _CAN4TARQ -SECTION: ".abs_section_28a" - _CAN4TBSEL -SECTION: ".abs_section_286" - _CAN4TFLG -SECTION: ".abs_section_287" - _CAN4TIER -SECTION: ".abs_section_2bc" - _CAN4TXDLR -SECTION: ".abs_section_2b4" - _CAN4TXDSR0 -SECTION: ".abs_section_2b5" - _CAN4TXDSR1 -SECTION: ".abs_section_2b6" - _CAN4TXDSR2 -SECTION: ".abs_section_2b7" - _CAN4TXDSR3 -SECTION: ".abs_section_2b8" - _CAN4TXDSR4 -SECTION: ".abs_section_2b9" - _CAN4TXDSR5 -SECTION: ".abs_section_2ba" - _CAN4TXDSR6 -SECTION: ".abs_section_2bb" - _CAN4TXDSR7 -SECTION: ".abs_section_28f" - _CAN4TXERR -SECTION: ".abs_section_2b0" - _CAN4TXIDR0 -SECTION: ".abs_section_2b1" - _CAN4TXIDR1 -SECTION: ".abs_section_2b2" - _CAN4TXIDR2 -SECTION: ".abs_section_2b3" - _CAN4TXIDR3 -SECTION: ".abs_section_2bf" - _CAN4TXTBPR -SECTION: ".abs_section_41" - _CFORC -SECTION: ".abs_section_39" - _CLKSEL -SECTION: ".abs_section_3c" - _COPCTL -SECTION: ".abs_section_37" - _CRGFLG -SECTION: ".abs_section_38" - _CRGINT -SECTION: ".abs_section_3e" - _CTCTL -SECTION: ".abs_section_36" - _CTFLG -SECTION: ".abs_section_9" - _DDRE -SECTION: ".abs_section_262" - _DDRH -SECTION: ".abs_section_26a" - _DDRJ -SECTION: ".abs_section_33" - _DDRK -SECTION: ".abs_section_252" - _DDRM -SECTION: ".abs_section_25a" - _DDRP -SECTION: ".abs_section_24a" - _DDRS -SECTION: ".abs_section_242" - _DDRT -SECTION: ".abs_section_ec" - _DLCBARD -SECTION: ".abs_section_e8" - _DLCBCR1 -SECTION: ".abs_section_ea" - _DLCBCR2 -SECTION: ".abs_section_eb" - _DLCBDR -SECTION: ".abs_section_ed" - _DLCBRSR -SECTION: ".abs_section_e9" - _DLCBSVR -SECTION: ".abs_section_ee" - _DLCSCR -SECTION: ".abs_section_69" - _DLYCT -SECTION: ".abs_section_e" - _EBICTL -SECTION: ".abs_section_110" - _ECLKDIV -SECTION: ".abs_section_116" - _ECMD -SECTION: ".abs_section_113" - _ECNFG -SECTION: ".abs_section_114" - _EPROT -SECTION: ".abs_section_115" - _ESTAT -SECTION: ".abs_section_100" - _FCLKDIV -SECTION: ".abs_section_106" - _FCMD -SECTION: ".abs_section_103" - _FCNFG -SECTION: ".abs_section_3d" - _FORBYP -SECTION: ".abs_section_104" - _FPROT -SECTION: ".abs_section_101" - _FSEC -SECTION: ".abs_section_105" - _FSTAT -SECTION: ".abs_section_1f" - _HPRIO -SECTION: ".abs_section_e0" - _IBAD -SECTION: ".abs_section_e2" - _IBCR -SECTION: ".abs_section_e4" - _IBDR -SECTION: ".abs_section_e1" - _IBFD -SECTION: ".abs_section_e3" - _IBSR -SECTION: ".abs_section_6a" - _ICOVW -SECTION: ".abs_section_68" - _ICPAR -SECTION: ".abs_section_6b" - _ICSYS -SECTION: ".abs_section_12" - _INITEE -SECTION: ".abs_section_11" - _INITRG -SECTION: ".abs_section_10" - _INITRM -SECTION: ".abs_section_1e" - _INTCR -SECTION: ".abs_section_15" - _ITCR -SECTION: ".abs_section_16" - _ITEST -SECTION: ".abs_section_66" - _MCCTL -SECTION: ".abs_section_67" - _MCFLG -SECTION: ".abs_section_1c" - _MEMSIZ0 -SECTION: ".abs_section_1d" - _MEMSIZ1 -SECTION: ".abs_section_13" - _MISC -SECTION: ".abs_section_b" - _MODE -SECTION: ".abs_section_257" - _MODRR -SECTION: ".abs_section_14" - _MTST0 -SECTION: ".abs_section_17" - _MTST1 -SECTION: ".abs_section_43" - _OC7D -SECTION: ".abs_section_42" - _OC7M -SECTION: ".abs_section_60" - _PACTL -SECTION: ".abs_section_61" - _PAFLG -SECTION: ".abs_section_1a" - _PARTIDH -SECTION: ".abs_section_1b" - _PARTIDL -SECTION: ".abs_section_70" - _PBCTL -SECTION: ".abs_section_71" - _PBFLG -SECTION: ".abs_section_a" - _PEAR -SECTION: ".abs_section_264" - _PERH -SECTION: ".abs_section_26c" - _PERJ -SECTION: ".abs_section_254" - _PERM -SECTION: ".abs_section_25c" - _PERP -SECTION: ".abs_section_24c" - _PERS -SECTION: ".abs_section_244" - _PERT -SECTION: ".abs_section_266" - _PIEH -SECTION: ".abs_section_26e" - _PIEJ -SECTION: ".abs_section_25e" - _PIEP -SECTION: ".abs_section_267" - _PIFH -SECTION: ".abs_section_26f" - _PIFJ -SECTION: ".abs_section_25f" - _PIFP -SECTION: ".abs_section_3a" - _PLLCTL -SECTION: ".abs_section_8f" - _PORTAD0 -SECTION: ".abs_section_12f" - _PORTAD1 -SECTION: ".abs_section_8" - _PORTE -SECTION: ".abs_section_32" - _PORTK -SECTION: ".abs_section_30" - _PPAGE -SECTION: ".abs_section_265" - _PPSH -SECTION: ".abs_section_26d" - _PPSJ -SECTION: ".abs_section_255" - _PPSM -SECTION: ".abs_section_25d" - _PPSP -SECTION: ".abs_section_24d" - _PPSS -SECTION: ".abs_section_245" - _PPST -SECTION: ".abs_section_260" - _PTH -SECTION: ".abs_section_261" - _PTIH -SECTION: ".abs_section_269" - _PTIJ -SECTION: ".abs_section_251" - _PTIM -SECTION: ".abs_section_259" - _PTIP -SECTION: ".abs_section_249" - _PTIS -SECTION: ".abs_section_241" - _PTIT -SECTION: ".abs_section_268" - _PTJ -SECTION: ".abs_section_250" - _PTM -SECTION: ".abs_section_258" - _PTP -SECTION: ".abs_section_248" - _PTS -SECTION: ".abs_section_240" - _PTT -SECTION: ".abs_section_c" - _PUCR -SECTION: ".abs_section_a4" - _PWMCAE -SECTION: ".abs_section_a2" - _PWMCLK -SECTION: ".abs_section_a5" - _PWMCTL -SECTION: ".abs_section_a0" - _PWME -SECTION: ".abs_section_a1" - _PWMPOL -SECTION: ".abs_section_a3" - _PWMPRCLK -SECTION: ".abs_section_a8" - _PWMSCLA -SECTION: ".abs_section_a9" - _PWMSCLB -SECTION: ".abs_section_c4" - _PWMSDN -SECTION: ".abs_section_263" - _RDRH -SECTION: ".abs_section_d" - _RDRIV -SECTION: ".abs_section_26b" - _RDRJ -SECTION: ".abs_section_253" - _RDRM -SECTION: ".abs_section_25b" - _RDRP -SECTION: ".abs_section_24b" - _RDRS -SECTION: ".abs_section_243" - _RDRT -SECTION: ".abs_section_35" - _REFDV -SECTION: ".abs_section_3b" - _RTICTL -SECTION: ".abs_section_ca" - _SCI0CR1 -SECTION: ".abs_section_cb" - _SCI0CR2 -SECTION: ".abs_section_ce" - _SCI0DRH -SECTION: ".abs_section_cf" - _SCI0DRL -SECTION: ".abs_section_cc" - _SCI0SR1 -SECTION: ".abs_section_cd" - _SCI0SR2 -SECTION: ".abs_section_d2" - _SCI1CR1 -SECTION: ".abs_section_d3" - _SCI1CR2 -SECTION: ".abs_section_d6" - _SCI1DRH -SECTION: ".abs_section_d7" - _SCI1DRL -SECTION: ".abs_section_d4" - _SCI1SR1 -SECTION: ".abs_section_d5" - _SCI1SR2 -SECTION: ".abs_section_da" - _SPI0BR -SECTION: ".abs_section_d8" - _SPI0CR1 -SECTION: ".abs_section_d9" - _SPI0CR2 -SECTION: ".abs_section_dd" - _SPI0DR -SECTION: ".abs_section_db" - _SPI0SR -SECTION: ".abs_section_f2" - _SPI1BR -SECTION: ".abs_section_f0" - _SPI1CR1 -SECTION: ".abs_section_f1" - _SPI1CR2 -SECTION: ".abs_section_f5" - _SPI1DR -SECTION: ".abs_section_f3" - _SPI1SR -SECTION: ".abs_section_fa" - _SPI2BR -SECTION: ".abs_section_f8" - _SPI2CR1 -SECTION: ".abs_section_f9" - _SPI2CR2 -SECTION: ".abs_section_fd" - _SPI2DR -SECTION: ".abs_section_fb" - _SPI2SR -SECTION: ".abs_section_34" - _SYNR -SECTION: ".abs_section_48" - _TCTL1 -SECTION: ".abs_section_49" - _TCTL2 -SECTION: ".abs_section_4a" - _TCTL3 -SECTION: ".abs_section_4b" - _TCTL4 -SECTION: ".abs_section_4e" - _TFLG1 -SECTION: ".abs_section_4f" - _TFLG2 -SECTION: ".abs_section_4c" - _TIE -SECTION: ".abs_section_6d" - _TIMTST -SECTION: ".abs_section_40" - _TIOS -SECTION: ".abs_section_46" - _TSCR1 -SECTION: ".abs_section_4d" - _TSCR2 -SECTION: ".abs_section_47" - _TTOV -SECTION: ".abs_section_256" - _WOMM -SECTION: ".abs_section_24e" - _WOMS -SECTION: ".abs_section_82" - _ATD0CTL23 -SECTION: ".abs_section_84" - _ATD0CTL45 -SECTION: ".abs_section_90" - _ATD0DR0 -SECTION: ".abs_section_92" - _ATD0DR1 -SECTION: ".abs_section_94" - _ATD0DR2 -SECTION: ".abs_section_96" - _ATD0DR3 -SECTION: ".abs_section_98" - _ATD0DR4 -SECTION: ".abs_section_9a" - _ATD0DR5 -SECTION: ".abs_section_9c" - _ATD0DR6 -SECTION: ".abs_section_9e" - _ATD0DR7 -SECTION: ".abs_section_122" - _ATD1CTL23 -SECTION: ".abs_section_124" - _ATD1CTL45 -SECTION: ".abs_section_130" - _ATD1DR0 -SECTION: ".abs_section_132" - _ATD1DR1 -SECTION: ".abs_section_134" - _ATD1DR2 -SECTION: ".abs_section_136" - _ATD1DR3 -SECTION: ".abs_section_138" - _ATD1DR4 -SECTION: ".abs_section_13a" - _ATD1DR5 -SECTION: ".abs_section_13c" - _ATD1DR6 -SECTION: ".abs_section_13e" - _ATD1DR7 -SECTION: ".abs_section_2" - _DDRAB -SECTION: ".abs_section_76" - _MCCNT -SECTION: ".abs_section_74" - _PA10H -SECTION: ".abs_section_72" - _PA32H -SECTION: ".abs_section_64" - _PACN10 -SECTION: ".abs_section_62" - _PACN32 -SECTION: ".abs_section_0" - _PORTAB -SECTION: ".abs_section_ac" - _PWMCNT01 -SECTION: ".abs_section_ae" - _PWMCNT23 -SECTION: ".abs_section_b0" - _PWMCNT45 -SECTION: ".abs_section_b2" - _PWMCNT67 -SECTION: ".abs_section_bc" - _PWMDTY01 -SECTION: ".abs_section_be" - _PWMDTY23 -SECTION: ".abs_section_c0" - _PWMDTY45 -SECTION: ".abs_section_c2" - _PWMDTY67 -SECTION: ".abs_section_b4" - _PWMPER01 -SECTION: ".abs_section_b6" - _PWMPER23 -SECTION: ".abs_section_b8" - _PWMPER45 -SECTION: ".abs_section_ba" - _PWMPER67 -SECTION: ".abs_section_c8" - _SCI0BD -SECTION: ".abs_section_d0" - _SCI1BD -SECTION: ".abs_section_50" - _TC0 -SECTION: ".abs_section_78" - _TC0H -SECTION: ".abs_section_52" - _TC1 -SECTION: ".abs_section_7a" - _TC1H -SECTION: ".abs_section_54" - _TC2 -SECTION: ".abs_section_7c" - _TC2H -SECTION: ".abs_section_56" - _TC3 -SECTION: ".abs_section_7e" - _TC3H -SECTION: ".abs_section_58" - _TC4 -SECTION: ".abs_section_5a" - _TC5 -SECTION: ".abs_section_5c" - _TC6 -SECTION: ".abs_section_5e" - _TC7 -SECTION: ".abs_section_44" - _TCNT -SECTION: ".abs_section_ff80" - _vect -SECTION: "TickTimer_DATA" - CmpHighVal -SECTION: "Byte1_DATA" - Byte1_Table -SECTION: "COM0_DATA" - COM0_PrescHigh.1 SerFlag PrescHigh NumMode -SECTION: "ROM_PAGE31_524" - xSerialGetChar xSerialPutChar xTaskCreate vTaskDelete vTaskDelayUntil - vTaskDelay uxTaskPriorityGet -SECTION: "ROM_PAGE32_525" - vTaskPrioritySet vTaskSuspend vTaskResume vTaskStartScheduler - vTaskSuspendAll xTaskResumeAll xTaskGetTickCount uxTaskGetNumberOfTasks -SECTION: "ROM_PAGE33_526" - vTaskIncrementTick vTaskSwitchContext vTaskPlaceOnEventList - xTaskRemoveFromEventList prvIdleTask prvInitialiseTCBVariables - prvInitialiseTaskLists -SECTION: "ROM_PAGE34_527" - prvCheckTasksWaitingTermination prvAllocateTCBAndStack prvDeleteTCB - xQueueCreate xQueueSend xQueueSendFromISR -SECTION: "ROM_PAGE35_528" - xQueueReceive xQueueReceiveFromISR uxQueueMessagesWaiting prvUnlockQueue - prvIsQueueEmpty prvIsQueueFull vListInitialise vListInitialiseItem - vListInsertEnd -SECTION: "ROM_PAGE36_529" - vListInsert vListRemove pvPortMalloc vPortFree vStartLEDFlashTasks - vLEDFlashTask -SECTION: "ROM_PAGE37_530" - vStartDynamicPriorityTasks vLimitedIncrementTask vContinuousIncrementTask - vCounterControlTask vQueueSendWhenSuspendedTask - vQueueReceiveWhenSuspendedTask xAreDynamicPriorityTasksStillRunning -SECTION: "ROM_PAGE38_531" - vStartPolledQueueTasks vPolledQueueProducer vPolledQueueConsumer - xArePollingQueuesStillRunning PE_Timer_LngHi1 vAltStartComTestTasks - vComTxTask -SECTION: "ROM_PAGE39_532" - vComRxTask xAreComTestTasksStillRunning pxPortInitialiseStack - xPortStartScheduler vStartIntegerMathTasks vCompeteingIntMathTask - xAreIntegerMathsTaskStillRunning -SECTION: "ROM_PAGE3A_533" - vStartBlockingQueueTasks vBlockingQueueProducer vBlockingQueueConsumer - xAreBlockingQueuesStillRunning vCreateSuicidalTasks -SECTION: "ROM_PAGE3B_534" - vSuicidalTask vCreateTasks xIsCreateTaskStillRunning - -********************************************************************************************* -OBJECT LIST SORTED BY ADDRESS - Name Addr hSize dSize Ref Section RLIB ---------------------------------------------------------------------------------------------- - _PORTAB 0 2 2 6 .abs_section_0 - _DDRAB 2 2 2 1 .abs_section_2 - _PORTE 8 1 1 0 .abs_section_8 - _DDRE 9 1 1 0 .abs_section_9 - _PEAR A 1 1 0 .abs_section_a - _MODE B 1 1 0 .abs_section_b - _PUCR C 1 1 0 .abs_section_c - _RDRIV D 1 1 0 .abs_section_d - _EBICTL E 1 1 0 .abs_section_e - _INITRM 10 1 1 1 .abs_section_10 - _INITRG 11 1 1 0 .abs_section_11 - _INITEE 12 1 1 1 .abs_section_12 - _MISC 13 1 1 1 .abs_section_13 - _MTST0 14 1 1 0 .abs_section_14 - _ITCR 15 1 1 0 .abs_section_15 - _ITEST 16 1 1 0 .abs_section_16 - _MTST1 17 1 1 0 .abs_section_17 - _PARTIDH 1A 1 1 0 .abs_section_1a - _PARTIDL 1B 1 1 0 .abs_section_1b - _MEMSIZ0 1C 1 1 0 .abs_section_1c - _MEMSIZ1 1D 1 1 0 .abs_section_1d - _INTCR 1E 1 1 1 .abs_section_1e - _HPRIO 1F 1 1 0 .abs_section_1f - _BKPCT0 28 1 1 0 .abs_section_28 - _BKPCT1 29 1 1 0 .abs_section_29 - _BKP0X 2A 1 1 0 .abs_section_2a - _BKP0H 2B 1 1 0 .abs_section_2b - _BKP0L 2C 1 1 0 .abs_section_2c - _BKP1X 2D 1 1 0 .abs_section_2d - _BKP1H 2E 1 1 0 .abs_section_2e - _BKP1L 2F 1 1 0 .abs_section_2f - _PPAGE 30 1 1 0 .abs_section_30 - _PORTK 32 1 1 0 .abs_section_32 - _DDRK 33 1 1 0 .abs_section_33 - _SYNR 34 1 1 1 .abs_section_34 - _REFDV 35 1 1 1 .abs_section_35 - _CTFLG 36 1 1 0 .abs_section_36 - _CRGFLG 37 1 1 1 .abs_section_37 - _CRGINT 38 1 1 0 .abs_section_38 - _CLKSEL 39 1 1 3 .abs_section_39 - _PLLCTL 3A 1 1 3 .abs_section_3a - _RTICTL 3B 1 1 0 .abs_section_3b - _COPCTL 3C 1 1 0 .abs_section_3c - _FORBYP 3D 1 1 0 .abs_section_3d - _CTCTL 3E 1 1 0 .abs_section_3e - _ARMCOP 3F 1 1 0 .abs_section_3f - _TIOS 40 1 1 1 .abs_section_40 - _CFORC 41 1 1 0 .abs_section_41 - _OC7M 42 1 1 0 .abs_section_42 - _OC7D 43 1 1 0 .abs_section_43 - _TCNT 44 2 2 0 .abs_section_44 - _TSCR1 46 1 1 3 .abs_section_46 - _TTOV 47 1 1 1 .abs_section_47 - _TCTL1 48 1 1 1 .abs_section_48 - _TCTL2 49 1 1 1 .abs_section_49 - _TCTL3 4A 1 1 0 .abs_section_4a - _TCTL4 4B 1 1 0 .abs_section_4b - _TIE 4C 1 1 3 .abs_section_4c - _TSCR2 4D 1 1 5 .abs_section_4d - _TFLG1 4E 1 1 3 .abs_section_4e - _TFLG2 4F 1 1 0 .abs_section_4f - _TC0 50 2 2 2 .abs_section_50 - _TC1 52 2 2 0 .abs_section_52 - _TC2 54 2 2 0 .abs_section_54 - _TC3 56 2 2 0 .abs_section_56 - _TC4 58 2 2 0 .abs_section_58 - _TC5 5A 2 2 0 .abs_section_5a - _TC6 5C 2 2 0 .abs_section_5c - _TC7 5E 2 2 2 .abs_section_5e - _PACTL 60 1 1 0 .abs_section_60 - _PAFLG 61 1 1 0 .abs_section_61 - _PACN32 62 2 2 0 .abs_section_62 - _PACN10 64 2 2 0 .abs_section_64 - _MCCTL 66 1 1 1 .abs_section_66 - _MCFLG 67 1 1 0 .abs_section_67 - _ICPAR 68 1 1 0 .abs_section_68 - _DLYCT 69 1 1 0 .abs_section_69 - _ICOVW 6A 1 1 0 .abs_section_6a - _ICSYS 6B 1 1 1 .abs_section_6b - _TIMTST 6D 1 1 0 .abs_section_6d - _PBCTL 70 1 1 0 .abs_section_70 - _PBFLG 71 1 1 0 .abs_section_71 - _PA32H 72 2 2 0 .abs_section_72 - _PA10H 74 2 2 0 .abs_section_74 - _MCCNT 76 2 2 0 .abs_section_76 - _TC0H 78 2 2 0 .abs_section_78 - _TC1H 7A 2 2 0 .abs_section_7a - _TC2H 7C 2 2 0 .abs_section_7c - _TC3H 7E 2 2 0 .abs_section_7e - _ATD0CTL23 82 2 2 0 .abs_section_82 - _ATD0CTL45 84 2 2 0 .abs_section_84 - _ATD0STAT0 86 1 1 0 .abs_section_86 - _ATD0STAT1 8B 1 1 0 .abs_section_8b - _ATD0DIEN 8D 1 1 0 .abs_section_8d - _PORTAD0 8F 1 1 0 .abs_section_8f - _ATD0DR0 90 2 2 0 .abs_section_90 - _ATD0DR1 92 2 2 0 .abs_section_92 - _ATD0DR2 94 2 2 0 .abs_section_94 - _ATD0DR3 96 2 2 0 .abs_section_96 - _ATD0DR4 98 2 2 0 .abs_section_98 - _ATD0DR5 9A 2 2 0 .abs_section_9a - _ATD0DR6 9C 2 2 0 .abs_section_9c - _ATD0DR7 9E 2 2 0 .abs_section_9e - _PWME A0 1 1 0 .abs_section_a0 - _PWMPOL A1 1 1 0 .abs_section_a1 - _PWMCLK A2 1 1 0 .abs_section_a2 - _PWMPRCLK A3 1 1 0 .abs_section_a3 - _PWMCAE A4 1 1 0 .abs_section_a4 - _PWMCTL A5 1 1 1 .abs_section_a5 - _PWMSCLA A8 1 1 0 .abs_section_a8 - _PWMSCLB A9 1 1 0 .abs_section_a9 - _PWMCNT01 AC 2 2 0 .abs_section_ac - _PWMCNT23 AE 2 2 0 .abs_section_ae - _PWMCNT45 B0 2 2 0 .abs_section_b0 - _PWMCNT67 B2 2 2 0 .abs_section_b2 - _PWMPER01 B4 2 2 0 .abs_section_b4 - _PWMPER23 B6 2 2 0 .abs_section_b6 - _PWMPER45 B8 2 2 0 .abs_section_b8 - _PWMPER67 BA 2 2 0 .abs_section_ba - _PWMDTY01 BC 2 2 0 .abs_section_bc - _PWMDTY23 BE 2 2 0 .abs_section_be - _PWMDTY45 C0 2 2 0 .abs_section_c0 - _PWMDTY67 C2 2 2 0 .abs_section_c2 - _PWMSDN C4 1 1 1 .abs_section_c4 - _SCI0BD C8 2 2 2 .abs_section_c8 - _SCI0CR1 CA 1 1 1 .abs_section_ca - _SCI0CR2 CB 1 1 7 .abs_section_cb - _SCI0SR1 CC 1 1 2 .abs_section_cc - _SCI0SR2 CD 1 1 1 .abs_section_cd - _SCI0DRH CE 1 1 0 .abs_section_ce - _SCI0DRL CF 1 1 3 .abs_section_cf - _SCI1BD D0 2 2 0 .abs_section_d0 - _SCI1CR1 D2 1 1 0 .abs_section_d2 - _SCI1CR2 D3 1 1 0 .abs_section_d3 - _SCI1SR1 D4 1 1 0 .abs_section_d4 - _SCI1SR2 D5 1 1 0 .abs_section_d5 - _SCI1DRH D6 1 1 0 .abs_section_d6 - _SCI1DRL D7 1 1 0 .abs_section_d7 - _SPI0CR1 D8 1 1 0 .abs_section_d8 - _SPI0CR2 D9 1 1 0 .abs_section_d9 - _SPI0BR DA 1 1 0 .abs_section_da - _SPI0SR DB 1 1 0 .abs_section_db - _SPI0DR DD 1 1 0 .abs_section_dd - _IBAD E0 1 1 0 .abs_section_e0 - _IBFD E1 1 1 0 .abs_section_e1 - _IBCR E2 1 1 0 .abs_section_e2 - _IBSR E3 1 1 0 .abs_section_e3 - _IBDR E4 1 1 0 .abs_section_e4 - _DLCBCR1 E8 1 1 0 .abs_section_e8 - _DLCBSVR E9 1 1 0 .abs_section_e9 - _DLCBCR2 EA 1 1 0 .abs_section_ea - _DLCBDR EB 1 1 0 .abs_section_eb - _DLCBARD EC 1 1 0 .abs_section_ec - _DLCBRSR ED 1 1 0 .abs_section_ed - _DLCSCR EE 1 1 0 .abs_section_ee - _SPI1CR1 F0 1 1 0 .abs_section_f0 - _SPI1CR2 F1 1 1 0 .abs_section_f1 - _SPI1BR F2 1 1 0 .abs_section_f2 - _SPI1SR F3 1 1 0 .abs_section_f3 - _SPI1DR F5 1 1 0 .abs_section_f5 - _SPI2CR1 F8 1 1 0 .abs_section_f8 - _SPI2CR2 F9 1 1 0 .abs_section_f9 - _SPI2BR FA 1 1 0 .abs_section_fa - _SPI2SR FB 1 1 0 .abs_section_fb - _SPI2DR FD 1 1 0 .abs_section_fd - _FCLKDIV 100 1 1 0 .abs_section_100 - _FSEC 101 1 1 0 .abs_section_101 - _FCNFG 103 1 1 0 .abs_section_103 - _FPROT 104 1 1 0 .abs_section_104 - _FSTAT 105 1 1 0 .abs_section_105 - _FCMD 106 1 1 0 .abs_section_106 - _ECLKDIV 110 1 1 0 .abs_section_110 - _ECNFG 113 1 1 0 .abs_section_113 - _EPROT 114 1 1 0 .abs_section_114 - _ESTAT 115 1 1 0 .abs_section_115 - _ECMD 116 1 1 0 .abs_section_116 - _ATD1CTL23 122 2 2 0 .abs_section_122 - _ATD1CTL45 124 2 2 0 .abs_section_124 - _ATD1STAT0 126 1 1 0 .abs_section_126 - _ATD1STAT1 12B 1 1 0 .abs_section_12b - _ATD1DIEN 12D 1 1 0 .abs_section_12d - _PORTAD1 12F 1 1 0 .abs_section_12f - _ATD1DR0 130 2 2 0 .abs_section_130 - _ATD1DR1 132 2 2 0 .abs_section_132 - _ATD1DR2 134 2 2 0 .abs_section_134 - _ATD1DR3 136 2 2 0 .abs_section_136 - _ATD1DR4 138 2 2 0 .abs_section_138 - _ATD1DR5 13A 2 2 0 .abs_section_13a - _ATD1DR6 13C 2 2 0 .abs_section_13c - _ATD1DR7 13E 2 2 0 .abs_section_13e - _CAN0CTL0 140 1 1 0 .abs_section_140 - _CAN0CTL1 141 1 1 0 .abs_section_141 - _CAN0BTR0 142 1 1 0 .abs_section_142 - _CAN0BTR1 143 1 1 0 .abs_section_143 - _CAN0RFLG 144 1 1 0 .abs_section_144 - _CAN0RIER 145 1 1 0 .abs_section_145 - _CAN0TFLG 146 1 1 0 .abs_section_146 - _CAN0TIER 147 1 1 0 .abs_section_147 - _CAN0TARQ 148 1 1 0 .abs_section_148 - _CAN0TAAK 149 1 1 0 .abs_section_149 - _CAN0TBSEL 14A 1 1 0 .abs_section_14a - _CAN0IDAC 14B 1 1 0 .abs_section_14b - _CAN0RXERR 14E 1 1 0 .abs_section_14e - _CAN0TXERR 14F 1 1 0 .abs_section_14f - _CAN0IDAR0 150 1 1 0 .abs_section_150 - _CAN0IDAR1 151 1 1 0 .abs_section_151 - _CAN0IDAR2 152 1 1 0 .abs_section_152 - _CAN0IDAR3 153 1 1 0 .abs_section_153 - _CAN0IDMR0 154 1 1 0 .abs_section_154 - _CAN0IDMR1 155 1 1 0 .abs_section_155 - _CAN0IDMR2 156 1 1 0 .abs_section_156 - _CAN0IDMR3 157 1 1 0 .abs_section_157 - _CAN0IDAR4 158 1 1 0 .abs_section_158 - _CAN0IDAR5 159 1 1 0 .abs_section_159 - _CAN0IDAR6 15A 1 1 0 .abs_section_15a - _CAN0IDAR7 15B 1 1 0 .abs_section_15b - _CAN0IDMR4 15C 1 1 0 .abs_section_15c - _CAN0IDMR5 15D 1 1 0 .abs_section_15d - _CAN0IDMR6 15E 1 1 0 .abs_section_15e - _CAN0IDMR7 15F 1 1 0 .abs_section_15f - _CAN0RXIDR0 160 1 1 0 .abs_section_160 - _CAN0RXIDR1 161 1 1 0 .abs_section_161 - _CAN0RXIDR2 162 1 1 0 .abs_section_162 - _CAN0RXIDR3 163 1 1 0 .abs_section_163 - _CAN0RXDSR0 164 1 1 0 .abs_section_164 - _CAN0RXDSR1 165 1 1 0 .abs_section_165 - _CAN0RXDSR2 166 1 1 0 .abs_section_166 - _CAN0RXDSR3 167 1 1 0 .abs_section_167 - _CAN0RXDSR4 168 1 1 0 .abs_section_168 - _CAN0RXDSR5 169 1 1 0 .abs_section_169 - _CAN0RXDSR6 16A 1 1 0 .abs_section_16a - _CAN0RXDSR7 16B 1 1 0 .abs_section_16b - _CAN0RXDLR 16C 1 1 0 .abs_section_16c - _CAN0TXIDR0 170 1 1 0 .abs_section_170 - _CAN0TXIDR1 171 1 1 0 .abs_section_171 - _CAN0TXIDR2 172 1 1 0 .abs_section_172 - _CAN0TXIDR3 173 1 1 0 .abs_section_173 - _CAN0TXDSR0 174 1 1 0 .abs_section_174 - _CAN0TXDSR1 175 1 1 0 .abs_section_175 - _CAN0TXDSR2 176 1 1 0 .abs_section_176 - _CAN0TXDSR3 177 1 1 0 .abs_section_177 - _CAN0TXDSR4 178 1 1 0 .abs_section_178 - _CAN0TXDSR5 179 1 1 0 .abs_section_179 - _CAN0TXDSR6 17A 1 1 0 .abs_section_17a - _CAN0TXDSR7 17B 1 1 0 .abs_section_17b - _CAN0TXDLR 17C 1 1 0 .abs_section_17c - _CAN0TXTBPR 17F 1 1 0 .abs_section_17f - _CAN1CTL0 180 1 1 0 .abs_section_180 - _CAN1CTL1 181 1 1 0 .abs_section_181 - _CAN1BTR0 182 1 1 0 .abs_section_182 - _CAN1BTR1 183 1 1 0 .abs_section_183 - _CAN1RFLG 184 1 1 0 .abs_section_184 - _CAN1RIER 185 1 1 0 .abs_section_185 - _CAN1TFLG 186 1 1 0 .abs_section_186 - _CAN1TIER 187 1 1 0 .abs_section_187 - _CAN1TARQ 188 1 1 0 .abs_section_188 - _CAN1TAAK 189 1 1 0 .abs_section_189 - _CAN1TBSEL 18A 1 1 0 .abs_section_18a - _CAN1IDAC 18B 1 1 0 .abs_section_18b - _CAN1RXERR 18E 1 1 0 .abs_section_18e - _CAN1TXERR 18F 1 1 0 .abs_section_18f - _CAN1IDAR0 190 1 1 0 .abs_section_190 - _CAN1IDAR1 191 1 1 0 .abs_section_191 - _CAN1IDAR2 192 1 1 0 .abs_section_192 - _CAN1IDAR3 193 1 1 0 .abs_section_193 - _CAN1IDMR0 194 1 1 0 .abs_section_194 - _CAN1IDMR1 195 1 1 0 .abs_section_195 - _CAN1IDMR2 196 1 1 0 .abs_section_196 - _CAN1IDMR3 197 1 1 0 .abs_section_197 - _CAN1IDAR4 198 1 1 0 .abs_section_198 - _CAN1IDAR5 199 1 1 0 .abs_section_199 - _CAN1IDAR6 19A 1 1 0 .abs_section_19a - _CAN1IDAR7 19B 1 1 0 .abs_section_19b - _CAN1IDMR4 19C 1 1 0 .abs_section_19c - _CAN1IDMR5 19D 1 1 0 .abs_section_19d - _CAN1IDMR6 19E 1 1 0 .abs_section_19e - _CAN1IDMR7 19F 1 1 0 .abs_section_19f - _CAN1RXIDR0 1A0 1 1 0 .abs_section_1a0 - _CAN1RXIDR1 1A1 1 1 0 .abs_section_1a1 - _CAN1RXIDR2 1A2 1 1 0 .abs_section_1a2 - _CAN1RXIDR3 1A3 1 1 0 .abs_section_1a3 - _CAN1RXDSR0 1A4 1 1 0 .abs_section_1a4 - _CAN1RXDSR1 1A5 1 1 0 .abs_section_1a5 - _CAN1RXDSR2 1A6 1 1 0 .abs_section_1a6 - _CAN1RXDSR3 1A7 1 1 0 .abs_section_1a7 - _CAN1RXDSR4 1A8 1 1 0 .abs_section_1a8 - _CAN1RXDSR5 1A9 1 1 0 .abs_section_1a9 - _CAN1RXDSR6 1AA 1 1 0 .abs_section_1aa - _CAN1RXDSR7 1AB 1 1 0 .abs_section_1ab - _CAN1RXDLR 1AC 1 1 0 .abs_section_1ac - _CAN1TXIDR0 1B0 1 1 0 .abs_section_1b0 - _CAN1TXIDR1 1B1 1 1 0 .abs_section_1b1 - _CAN1TXIDR2 1B2 1 1 0 .abs_section_1b2 - _CAN1TXIDR3 1B3 1 1 0 .abs_section_1b3 - _CAN1TXDSR0 1B4 1 1 0 .abs_section_1b4 - _CAN1TXDSR1 1B5 1 1 0 .abs_section_1b5 - _CAN1TXDSR2 1B6 1 1 0 .abs_section_1b6 - _CAN1TXDSR3 1B7 1 1 0 .abs_section_1b7 - _CAN1TXDSR4 1B8 1 1 0 .abs_section_1b8 - _CAN1TXDSR5 1B9 1 1 0 .abs_section_1b9 - _CAN1TXDSR6 1BA 1 1 0 .abs_section_1ba - _CAN1TXDSR7 1BB 1 1 0 .abs_section_1bb - _CAN1TXDLR 1BC 1 1 0 .abs_section_1bc - _CAN1TXTBPR 1BF 1 1 0 .abs_section_1bf - _CAN2CTL0 1C0 1 1 0 .abs_section_1c0 - _CAN2CTL1 1C1 1 1 0 .abs_section_1c1 - _CAN2BTR0 1C2 1 1 0 .abs_section_1c2 - _CAN2BTR1 1C3 1 1 0 .abs_section_1c3 - _CAN2RFLG 1C4 1 1 0 .abs_section_1c4 - _CAN2RIER 1C5 1 1 0 .abs_section_1c5 - _CAN2TFLG 1C6 1 1 0 .abs_section_1c6 - _CAN2TIER 1C7 1 1 0 .abs_section_1c7 - _CAN2TARQ 1C8 1 1 0 .abs_section_1c8 - _CAN2TAAK 1C9 1 1 0 .abs_section_1c9 - _CAN2TBSEL 1CA 1 1 0 .abs_section_1ca - _CAN2IDAC 1CB 1 1 0 .abs_section_1cb - _CAN2RXERR 1CE 1 1 0 .abs_section_1ce - _CAN2TXERR 1CF 1 1 0 .abs_section_1cf - _CAN2IDAR0 1D0 1 1 0 .abs_section_1d0 - _CAN2IDAR1 1D1 1 1 0 .abs_section_1d1 - _CAN2IDAR2 1D2 1 1 0 .abs_section_1d2 - _CAN2IDAR3 1D3 1 1 0 .abs_section_1d3 - _CAN2IDMR0 1D4 1 1 0 .abs_section_1d4 - _CAN2IDMR1 1D5 1 1 0 .abs_section_1d5 - _CAN2IDMR2 1D6 1 1 0 .abs_section_1d6 - _CAN2IDMR3 1D7 1 1 0 .abs_section_1d7 - _CAN2IDAR4 1D8 1 1 0 .abs_section_1d8 - _CAN2IDAR5 1D9 1 1 0 .abs_section_1d9 - _CAN2IDAR6 1DA 1 1 0 .abs_section_1da - _CAN2IDAR7 1DB 1 1 0 .abs_section_1db - _CAN2IDMR4 1DC 1 1 0 .abs_section_1dc - _CAN2IDMR5 1DD 1 1 0 .abs_section_1dd - _CAN2IDMR6 1DE 1 1 0 .abs_section_1de - _CAN2IDMR7 1DF 1 1 0 .abs_section_1df - _CAN2RXIDR0 1E0 1 1 0 .abs_section_1e0 - _CAN2RXIDR1 1E1 1 1 0 .abs_section_1e1 - _CAN2RXIDR2 1E2 1 1 0 .abs_section_1e2 - _CAN2RXIDR3 1E3 1 1 0 .abs_section_1e3 - _CAN2RXDSR0 1E4 1 1 0 .abs_section_1e4 - _CAN2RXDSR1 1E5 1 1 0 .abs_section_1e5 - _CAN2RXDSR2 1E6 1 1 0 .abs_section_1e6 - _CAN2RXDSR3 1E7 1 1 0 .abs_section_1e7 - _CAN2RXDSR4 1E8 1 1 0 .abs_section_1e8 - _CAN2RXDSR5 1E9 1 1 0 .abs_section_1e9 - _CAN2RXDSR6 1EA 1 1 0 .abs_section_1ea - _CAN2RXDSR7 1EB 1 1 0 .abs_section_1eb - _CAN2RXDLR 1EC 1 1 0 .abs_section_1ec - _CAN2TXIDR0 1F0 1 1 0 .abs_section_1f0 - _CAN2TXIDR1 1F1 1 1 0 .abs_section_1f1 - _CAN2TXIDR2 1F2 1 1 0 .abs_section_1f2 - _CAN2TXIDR3 1F3 1 1 0 .abs_section_1f3 - _CAN2TXDSR0 1F4 1 1 0 .abs_section_1f4 - _CAN2TXDSR1 1F5 1 1 0 .abs_section_1f5 - _CAN2TXDSR2 1F6 1 1 0 .abs_section_1f6 - _CAN2TXDSR3 1F7 1 1 0 .abs_section_1f7 - _CAN2TXDSR4 1F8 1 1 0 .abs_section_1f8 - _CAN2TXDSR5 1F9 1 1 0 .abs_section_1f9 - _CAN2TXDSR6 1FA 1 1 0 .abs_section_1fa - _CAN2TXDSR7 1FB 1 1 0 .abs_section_1fb - _CAN2TXDLR 1FC 1 1 0 .abs_section_1fc - _CAN2TXTBPR 1FF 1 1 0 .abs_section_1ff - _CAN3CTL0 200 1 1 0 .abs_section_200 - _CAN3CTL1 201 1 1 0 .abs_section_201 - _CAN3BTR0 202 1 1 0 .abs_section_202 - _CAN3BTR1 203 1 1 0 .abs_section_203 - _CAN3RFLG 204 1 1 0 .abs_section_204 - _CAN3RIER 205 1 1 0 .abs_section_205 - _CAN3TFLG 206 1 1 0 .abs_section_206 - _CAN3TIER 207 1 1 0 .abs_section_207 - _CAN3TARQ 208 1 1 0 .abs_section_208 - _CAN3TAAK 209 1 1 0 .abs_section_209 - _CAN3TBSEL 20A 1 1 0 .abs_section_20a - _CAN3IDAC 20B 1 1 0 .abs_section_20b - _CAN3RXERR 20E 1 1 0 .abs_section_20e - _CAN3TXERR 20F 1 1 0 .abs_section_20f - _CAN3IDAR0 210 1 1 0 .abs_section_210 - _CAN3IDAR1 211 1 1 0 .abs_section_211 - _CAN3IDAR2 212 1 1 0 .abs_section_212 - _CAN3IDAR3 213 1 1 0 .abs_section_213 - _CAN3IDMR0 214 1 1 0 .abs_section_214 - _CAN3IDMR1 215 1 1 0 .abs_section_215 - _CAN3IDMR2 216 1 1 0 .abs_section_216 - _CAN3IDMR3 217 1 1 0 .abs_section_217 - _CAN3IDAR4 218 1 1 0 .abs_section_218 - _CAN3IDAR5 219 1 1 0 .abs_section_219 - _CAN3IDAR6 21A 1 1 0 .abs_section_21a - _CAN3IDAR7 21B 1 1 0 .abs_section_21b - _CAN3IDMR4 21C 1 1 0 .abs_section_21c - _CAN3IDMR5 21D 1 1 0 .abs_section_21d - _CAN3IDMR6 21E 1 1 0 .abs_section_21e - _CAN3IDMR7 21F 1 1 0 .abs_section_21f - _CAN3RXIDR0 220 1 1 0 .abs_section_220 - _CAN3RXIDR1 221 1 1 0 .abs_section_221 - _CAN3RXIDR2 222 1 1 0 .abs_section_222 - _CAN3RXIDR3 223 1 1 0 .abs_section_223 - _CAN3RXDSR0 224 1 1 0 .abs_section_224 - _CAN3RXDSR1 225 1 1 0 .abs_section_225 - _CAN3RXDSR2 226 1 1 0 .abs_section_226 - _CAN3RXDSR3 227 1 1 0 .abs_section_227 - _CAN3RXDSR4 228 1 1 0 .abs_section_228 - _CAN3RXDSR5 229 1 1 0 .abs_section_229 - _CAN3RXDSR6 22A 1 1 0 .abs_section_22a - _CAN3RXDSR7 22B 1 1 0 .abs_section_22b - _CAN3RXDLR 22C 1 1 0 .abs_section_22c - _CAN3TXIDR0 230 1 1 0 .abs_section_230 - _CAN3TXIDR1 231 1 1 0 .abs_section_231 - _CAN3TXIDR2 232 1 1 0 .abs_section_232 - _CAN3TXIDR3 233 1 1 0 .abs_section_233 - _CAN3TXDSR0 234 1 1 0 .abs_section_234 - _CAN3TXDSR1 235 1 1 0 .abs_section_235 - _CAN3TXDSR2 236 1 1 0 .abs_section_236 - _CAN3TXDSR3 237 1 1 0 .abs_section_237 - _CAN3TXDSR4 238 1 1 0 .abs_section_238 - _CAN3TXDSR5 239 1 1 0 .abs_section_239 - _CAN3TXDSR6 23A 1 1 0 .abs_section_23a - _CAN3TXDSR7 23B 1 1 0 .abs_section_23b - _CAN3TXDLR 23C 1 1 0 .abs_section_23c - _CAN3TXTBPR 23F 1 1 0 .abs_section_23f - _PTT 240 1 1 0 .abs_section_240 - _PTIT 241 1 1 0 .abs_section_241 - _DDRT 242 1 1 0 .abs_section_242 - _RDRT 243 1 1 0 .abs_section_243 - _PERT 244 1 1 0 .abs_section_244 - _PPST 245 1 1 0 .abs_section_245 - _PTS 248 1 1 1 .abs_section_248 - _PTIS 249 1 1 0 .abs_section_249 - _DDRS 24A 1 1 2 .abs_section_24a - _RDRS 24B 1 1 0 .abs_section_24b - _PERS 24C 1 1 0 .abs_section_24c - _PPSS 24D 1 1 0 .abs_section_24d - _WOMS 24E 1 1 0 .abs_section_24e - _PTM 250 1 1 0 .abs_section_250 - _PTIM 251 1 1 0 .abs_section_251 - _DDRM 252 1 1 0 .abs_section_252 - _RDRM 253 1 1 0 .abs_section_253 - _PERM 254 1 1 0 .abs_section_254 - _PPSM 255 1 1 0 .abs_section_255 - _WOMM 256 1 1 0 .abs_section_256 - _MODRR 257 1 1 0 .abs_section_257 - _PTP 258 1 1 0 .abs_section_258 - _PTIP 259 1 1 0 .abs_section_259 - _DDRP 25A 1 1 0 .abs_section_25a - _RDRP 25B 1 1 0 .abs_section_25b - _PERP 25C 1 1 0 .abs_section_25c - _PPSP 25D 1 1 0 .abs_section_25d - _PIEP 25E 1 1 0 .abs_section_25e - _PIFP 25F 1 1 0 .abs_section_25f - _PTH 260 1 1 0 .abs_section_260 - _PTIH 261 1 1 0 .abs_section_261 - _DDRH 262 1 1 0 .abs_section_262 - _RDRH 263 1 1 0 .abs_section_263 - _PERH 264 1 1 0 .abs_section_264 - _PPSH 265 1 1 0 .abs_section_265 - _PIEH 266 1 1 0 .abs_section_266 - _PIFH 267 1 1 0 .abs_section_267 - _PTJ 268 1 1 0 .abs_section_268 - _PTIJ 269 1 1 0 .abs_section_269 - _DDRJ 26A 1 1 0 .abs_section_26a - _RDRJ 26B 1 1 0 .abs_section_26b - _PERJ 26C 1 1 0 .abs_section_26c - _PPSJ 26D 1 1 0 .abs_section_26d - _PIEJ 26E 1 1 0 .abs_section_26e - _PIFJ 26F 1 1 0 .abs_section_26f - _CAN4CTL0 280 1 1 0 .abs_section_280 - _CAN4CTL1 281 1 1 0 .abs_section_281 - _CAN4BTR0 282 1 1 0 .abs_section_282 - _CAN4BTR1 283 1 1 0 .abs_section_283 - _CAN4RFLG 284 1 1 0 .abs_section_284 - _CAN4RIER 285 1 1 0 .abs_section_285 - _CAN4TFLG 286 1 1 0 .abs_section_286 - _CAN4TIER 287 1 1 0 .abs_section_287 - _CAN4TARQ 288 1 1 0 .abs_section_288 - _CAN4TAAK 289 1 1 0 .abs_section_289 - _CAN4TBSEL 28A 1 1 0 .abs_section_28a - _CAN4IDAC 28B 1 1 0 .abs_section_28b - _CAN4RXERR 28E 1 1 0 .abs_section_28e - _CAN4TXERR 28F 1 1 0 .abs_section_28f - _CAN4IDAR0 290 1 1 0 .abs_section_290 - _CAN4IDAR1 291 1 1 0 .abs_section_291 - _CAN4IDAR2 292 1 1 0 .abs_section_292 - _CAN4IDAR3 293 1 1 0 .abs_section_293 - _CAN4IDMR0 294 1 1 0 .abs_section_294 - _CAN4IDMR1 295 1 1 0 .abs_section_295 - _CAN4IDMR2 296 1 1 0 .abs_section_296 - _CAN4IDMR3 297 1 1 0 .abs_section_297 - _CAN4IDAR4 298 1 1 0 .abs_section_298 - _CAN4IDAR5 299 1 1 0 .abs_section_299 - _CAN4IDAR6 29A 1 1 0 .abs_section_29a - _CAN4IDAR7 29B 1 1 0 .abs_section_29b - _CAN4IDMR4 29C 1 1 0 .abs_section_29c - _CAN4IDMR5 29D 1 1 0 .abs_section_29d - _CAN4IDMR6 29E 1 1 0 .abs_section_29e - _CAN4IDMR7 29F 1 1 0 .abs_section_29f - _CAN4RXIDR0 2A0 1 1 0 .abs_section_2a0 - _CAN4RXIDR1 2A1 1 1 0 .abs_section_2a1 - _CAN4RXIDR2 2A2 1 1 0 .abs_section_2a2 - _CAN4RXIDR3 2A3 1 1 0 .abs_section_2a3 - _CAN4RXDSR0 2A4 1 1 0 .abs_section_2a4 - _CAN4RXDSR1 2A5 1 1 0 .abs_section_2a5 - _CAN4RXDSR2 2A6 1 1 0 .abs_section_2a6 - _CAN4RXDSR3 2A7 1 1 0 .abs_section_2a7 - _CAN4RXDSR4 2A8 1 1 0 .abs_section_2a8 - _CAN4RXDSR5 2A9 1 1 0 .abs_section_2a9 - _CAN4RXDSR6 2AA 1 1 0 .abs_section_2aa - _CAN4RXDSR7 2AB 1 1 0 .abs_section_2ab - _CAN4RXDLR 2AC 1 1 0 .abs_section_2ac - _CAN4TXIDR0 2B0 1 1 0 .abs_section_2b0 - _CAN4TXIDR1 2B1 1 1 0 .abs_section_2b1 - _CAN4TXIDR2 2B2 1 1 0 .abs_section_2b2 - _CAN4TXIDR3 2B3 1 1 0 .abs_section_2b3 - _CAN4TXDSR0 2B4 1 1 0 .abs_section_2b4 - _CAN4TXDSR1 2B5 1 1 0 .abs_section_2b5 - _CAN4TXDSR2 2B6 1 1 0 .abs_section_2b6 - _CAN4TXDSR3 2B7 1 1 0 .abs_section_2b7 - _CAN4TXDSR4 2B8 1 1 0 .abs_section_2b8 - _CAN4TXDSR5 2B9 1 1 0 .abs_section_2b9 - _CAN4TXDSR6 2BA 1 1 0 .abs_section_2ba - _CAN4TXDSR7 2BB 1 1 0 .abs_section_2bb - _CAN4TXDLR 2BC 1 1 0 .abs_section_2bc - _CAN4TXTBPR 2BF 1 1 0 .abs_section_2bf - uxCriticalNesting 1000 1 1 101 .data - xLocalError 1001 1 1 2 .bss - xRxedChars 1002 2 2 3 .bss - xCharsForTx 1004 2 2 3 .bss - pxCurrentTCB 1006 2 2 28 .bss - uxTasksDeleted 1008 1 1 3 .bss - uxCurrentNumberOfTasks 1009 1 1 5 .bss - xTickCount 100A 2 2 14 .bss - uxTopUsedPriority 100C 1 1 2 .bss - uxTopReadyPriority 100D 1 1 15 .bss - xSchedulerRunning 100E 1 1 3 .bss - uxSchedulerSuspended 100F 1 1 6 .bss - uxMissedTicks 1010 1 1 4 .bss - uxTaskNumber.1 1011 1 1 2 .bss - pxReadyTasksLists 1012 3C 60 11 .bss - xDelayedTaskList1 104E F 15 2 .bss - xDelayedTaskList2 105D F 15 2 .bss - pxDelayedTaskList 106C 2 2 8 .bss - pxOverflowDelayedTaskList 106E 2 2 6 .bss - xPendingReadyList 1070 F 15 4 .bss - xTasksWaitingTermination 107F F 15 5 .bss - xSuspendedTaskList 108E F 15 2 .bss - xHeapHasBeenInitialised.1 109D 1 1 2 .bss - xHeap 109E 2804 10244 2 .bss - xStart 38A2 4 4 6 .bss - xEnd 38A6 4 4 4 .bss - uxFlashTaskNumber 38AA 1 1 2 .bss - usCheckVariable 38AB 2 2 3 .bss - xSuspendedQueueSendError 38AD 1 1 2 .bss - xSuspendedQueueReceiveError 38AE 1 1 3 .bss - ulValueToSend.6 38AF 4 4 5 .bss - ulExpectedValue.7 38B3 4 4 6 .bss - usLastTaskCheck.9 38B7 2 2 2 .bss - xContinousIncrementHandle 38B9 2 2 5 .bss - xLimitedIncrementHandle 38BB 2 2 2 .bss - ulCounter 38BD 4 4 10 .bss - ulReceivedValue.8 38C1 4 4 3 .bss - xPollingConsumerCount 38C5 1 1 3 .bss - xPollingProducerCount 38C6 1 1 3 .bss - xPolledQueue.1 38C7 2 2 3 .bss - xPort 38C9 2 2 3 .bss - uxBaseLED 38CB 1 1 5 .bss - uxRxLoops 38CC 1 1 3 .bss - xTaskCheck 38CD 1 1 3 .bss - sBlockingConsumerCount 38CE 6 6 4 .bss - sBlockingProducerCount 38D4 6 6 5 .bss - sLastBlockingConsumerCount.7 38DA 6 6 2 .bss - sLastBlockingProducerCount.8 38E0 6 6 2 .bss - usCreationCount 38E6 2 2 4 .bss - uxTasksRunningAtStart 38E8 1 1 4 .bss - usLastCreationCount.6 38E9 2 2 2 .bss - uxTasksRunningNow.7 38EB 1 1 1 .bss - xSuspendedTestQueue 38EC 2 2 3 .common - xCreatedTask1 38EE 2 2 2 .common - xCreatedTask2 38F0 2 2 2 .common - CmpHighVal 38F2 2 2 2 TickTimer_DATA - Byte1_Table 38F4 8 8 2 Byte1_DATA - COM0_PrescHigh.1 38FC 8 8 1 COM0_DATA - SerFlag 3904 2 2 1 COM0_DATA - PrescHigh 3906 2 2 2 COM0_DATA - NumMode 3908 1 1 2 COM0_DATA - _EntryPoint C000 2E 46 1 .init - PE_low_level_init C02E 4E 78 2 .init - STRING.Check.1 C09A 6 6 1 .rodata1 - STRING.IDLE.2 C0A0 5 5 1 .rodata1 - STRING.LEDx.1 C0A5 5 5 1 .rodata1 - STRING.CNT_INC.1 C0AA 8 8 1 .rodata1 - STRING.LIM_INC.2 C0B2 8 8 1 .rodata1 - STRING.C_CTRL.3 C0BA 7 7 1 .rodata1 - STRING.SUSP_TX.4 C0C1 8 8 1 .rodata1 - STRING.SUSP_RX.5 C0C9 8 8 1 .rodata1 - STRING.QConsNB.2 C0D1 8 8 1 .rodata1 - STRING.QProdNB.3 C0D9 8 8 1 .rodata1 - STRING.COMTx.1 C0E1 6 6 1 .rodata1 - STRING.COMRx.2 C0E7 6 6 1 .rodata1 - STRING.IntMath.1 C0ED 8 8 1 .rodata1 - STRING.QConsB1.1 C0F5 8 8 1 .rodata1 - STRING.QProdB2.2 C0FD 8 8 1 .rodata1 - STRING.QProdB3.3 C105 8 8 1 .rodata1 - STRING.QConsB4.4 C10D 8 8 1 .rodata1 - STRING.QProdB5.5 C115 8 8 1 .rodata1 - STRING.QConsB6.6 C11D 8 8 1 .rodata1 - STRING.CREATOR.1 C125 8 8 1 .rodata1 - STRING.SUICIDE1.2 C12D 9 9 1 .rodata1 - STRING.SUICIDE2.3 C136 9 9 1 .rodata1 - STRING.SUICIDE1.4 C13F 9 9 1 .rodata1 - STRING.SUICIDE2.5 C148 9 9 1 .rodata1 - _Startup C151 12 18 1 NON_BANKED - _LCMP C163 19 25 2 NON_BANKED - _LCMP_P C17C 15 21 3 NON_BANKED - _LNEG C191 D 13 2 NON_BANKED - _LINC C19E 5 5 4 NON_BANKED - _LMUL C1A3 27 39 1 NON_BANKED - _lDivMod C1CA E3 227 3 NON_BANKED - _LDIVU C2AD E 14 1 NON_BANKED - _NEG_P C2BB F 15 4 NON_BANKED - _LDIVS C2CA 35 53 2 NON_BANKED - Cpu_Interrupt C2FF 1 1 60 NON_BANKED - vCOM0_ISR C300 59 89 1 NON_BANKED - xBankedStartScheduler C359 1A 26 1 NON_BANKED - vPortYield C373 1D 29 1 NON_BANKED - vPortTickInterrupt C390 25 37 1 NON_BANKED - _BDMSTS FF01 1 1 0 .abs_section_ff01 - _BDMCCR FF06 1 1 0 .abs_section_ff06 - _BDMINR FF07 1 1 0 .abs_section_ff07 - _vect FF80 80 128 0 .abs_section_ff80 - Init 308000 29 41 2 .text - memcpy 308029 26 38 8 .text - memset 30804F 1E 30 2 .text - strncpy 30806D 2D 45 2 .text - main 30809A 9 9 0 .text - vMain 3080A3 52 82 1 .text - vErrorChecks 3080F5 39 57 3 .text - prvCheckOtherTasksAreStillRunning 30812E 50 80 2 .text - vApplicationIdleHook 30817E 70 112 2 .text - vParTestSetLED 3081EE 23 35 4 .text - vParTestToggleLED 308211 14 20 10 .text - xSerialPortInitMinimal 308225 26 38 2 .text - xSerialGetChar 318000 13 19 4 ROM_PAGE31_524 - xSerialPutChar 318013 18 24 2 ROM_PAGE31_524 - xTaskCreate 31802B D5 213 48 ROM_PAGE31_524 - vTaskDelete 318100 4A 74 4 ROM_PAGE31_524 - vTaskDelayUntil 31814A 77 119 6 ROM_PAGE31_524 - vTaskDelay 3181C1 46 70 16 ROM_PAGE31_524 - uxTaskPriorityGet 318207 22 34 2 ROM_PAGE31_524 - vTaskPrioritySet 328000 69 105 4 ROM_PAGE32_525 - vTaskSuspend 328069 47 71 6 ROM_PAGE32_525 - vTaskResume 3280B0 5C 92 6 ROM_PAGE32_525 - vTaskStartScheduler 32810C 31 49 2 ROM_PAGE32_525 - vTaskSuspendAll 32813D 13 19 26 ROM_PAGE32_525 - xTaskResumeAll 328150 9F 159 30 ROM_PAGE32_525 - xTaskGetTickCount 3281EF 17 23 6 ROM_PAGE32_525 - uxTaskGetNumberOfTasks 328206 17 23 4 ROM_PAGE32_525 - vTaskIncrementTick 338000 84 132 4 ROM_PAGE33_526 - vTaskSwitchContext 338084 5B 91 4 ROM_PAGE33_526 - vTaskPlaceOnEventList 3380DF 41 65 4 ROM_PAGE33_526 - xTaskRemoveFromEventList 338120 69 105 8 ROM_PAGE33_526 - prvIdleTask 338189 12 18 3 ROM_PAGE33_526 - prvInitialiseTCBVariables 33819B 4D 77 2 ROM_PAGE33_526 - prvInitialiseTaskLists 3381E8 3C 60 2 ROM_PAGE33_526 - prvCheckTasksWaitingTermination 348000 53 83 2 ROM_PAGE34_527 - prvAllocateTCBAndStack 348053 3D 61 2 ROM_PAGE34_527 - prvDeleteTCB 348090 F 15 2 ROM_PAGE34_527 - xQueueCreate 34809F 7B 123 14 ROM_PAGE34_527 - xQueueSend 34811A D4 212 9 ROM_PAGE34_527 - xQueueSendFromISR 3481EE 5D 93 2 ROM_PAGE34_527 - xQueueReceive 358000 CF 207 9 ROM_PAGE35_528 - xQueueReceiveFromISR 3580CF 61 97 2 ROM_PAGE35_528 - uxQueueMessagesWaiting 358130 1B 27 2 ROM_PAGE35_528 - prvUnlockQueue 35814B 71 113 8 ROM_PAGE35_528 - prvIsQueueEmpty 3581BC 22 34 2 ROM_PAGE35_528 - prvIsQueueFull 3581DE 25 37 2 ROM_PAGE35_528 - vListInitialise 358203 20 32 6 ROM_PAGE35_528 - vListInitialiseItem 358223 7 7 6 ROM_PAGE35_528 - vListInsertEnd 35822A 25 37 16 ROM_PAGE35_528 - vListInsert 368000 55 85 8 ROM_PAGE36_529 - vListRemove 368055 23 35 32 ROM_PAGE36_529 - pvPortMalloc 368078 C1 193 14 ROM_PAGE36_529 - vPortFree 368139 3B 59 10 ROM_PAGE36_529 - vStartLEDFlashTasks 368174 32 50 2 ROM_PAGE36_529 - vLEDFlashTask 3681A6 57 87 3 ROM_PAGE36_529 - vStartDynamicPriorityTasks 378000 9B 155 2 ROM_PAGE37_530 - vLimitedIncrementTask 37809B 27 39 3 ROM_PAGE37_530 - vContinuousIncrementTask 3780C2 38 56 3 ROM_PAGE37_530 - vCounterControlTask 3780FA A0 160 5 ROM_PAGE37_530 - vQueueSendWhenSuspendedTask 37819A 38 56 3 ROM_PAGE37_530 - vQueueReceiveWhenSuspendedTask 3781D2 54 84 3 ROM_PAGE37_530 - xAreDynamicPriorityTasksStillRunning 378226 2B 43 2 ROM_PAGE37_530 - vStartPolledQueueTasks 388000 4B 75 2 ROM_PAGE38_531 - vPolledQueueProducer 38804B 4F 79 3 ROM_PAGE38_531 - vPolledQueueConsumer 38809A 5C 92 3 ROM_PAGE38_531 - xArePollingQueuesStillRunning 3880F6 16 22 2 ROM_PAGE38_531 - PE_Timer_LngHi1 38810C 4A 74 2 ROM_PAGE38_531 - vAltStartComTestTasks 388156 4D 77 2 ROM_PAGE38_531 - vComTxTask 3881A3 4F 79 3 ROM_PAGE38_531 - vComRxTask 398000 7B 123 3 ROM_PAGE39_532 - xAreComTestTasksStillRunning 39807B D 13 2 ROM_PAGE39_532 - pxPortInitialiseStack 398088 31 49 2 ROM_PAGE39_532 - xPortStartScheduler 3980B9 4 4 2 ROM_PAGE39_532 - vStartIntegerMathTasks 3980BD 33 51 2 ROM_PAGE39_532 - vCompeteingIntMathTask 3980F0 87 135 3 ROM_PAGE39_532 - xAreIntegerMathsTaskStillRunning 398177 20 32 2 ROM_PAGE39_532 - vStartBlockingQueueTasks 3A8000 143 323 7 ROM_PAGE3A_533 - vBlockingQueueProducer 3A8143 3F 63 9 ROM_PAGE3A_533 - vBlockingQueueConsumer 3A8182 47 71 9 ROM_PAGE3A_533 - xAreBlockingQueuesStillRunning 3A81C9 52 82 2 ROM_PAGE3A_533 - vCreateSuicidalTasks 3A821B 31 49 2 ROM_PAGE3A_533 - vSuicidalTask 3B8000 58 88 12 ROM_PAGE3B_534 - vCreateTasks 3B8058 92 146 4 ROM_PAGE3B_534 - xIsCreateTaskStillRunning 3B80EA 3A 58 2 ROM_PAGE3B_534 - TickTimer_Enable 3B8124 9 9 2 TickTimer_CODE - TickTimer_SetFreqHz 3B812D 56 86 2 TickTimer_CODE - TickTimer_Init 3B8183 1C 28 2 TickTimer_CODE - Byte1_PutBit 3B819F 21 33 2 Byte1_CODE - Byte1_NegBit 3B81C0 14 20 2 Byte1_CODE - COM0_SetBaudRateMode 3B81D4 19 25 2 COM0_CODE - COM0_Init 3B81ED 25 37 2 COM0_CODE - -********************************************************************************************* -UNUSED-OBJECTS SECTION ---------------------------------------------------------------------------------------------- -NOT USED PROCEDURES -STRING.C.o (ansibi.lib): - strerror memchr memcmp memcpy2 _memcpy_8bitCount memmove - _memset_clear_8bitCount strlen strset strcat strncat strcpy strcmp strncmp - strchr strrchr strspn strcspn strpbrk strstr strtok strcoll strxfrm -rtshc12.c.o (ansibi.lib): - _BSHL _BSHRS _BSHRU _BDIVMODU _BDIVMODS _ISHL _ISHRU _ISHRS _LSHL _LSHRU - _LSHRS _LADD _LSUB _LAND _LOR _LXOR _LCMP_PP _LABS _LCOM _LDEC _LMODU _LMODS - _ILSEXT _LTEST _COPY _CASE_DIRECT _CASE_DIRECT_BYTE _CASE_CHECKED - _CASE_CHECKED_BYTE _CASE_SEARCH _CASE_SEARCH_BYTE _CASE_SEARCH_8 - _CASE_SEARCH_8_BYTE _FCALL _FPCMP -serial.c.o: - vSerialClose -tasks.c.o: - vTaskEndScheduler -queue.c.o: - vQueueDelete -TickTimer.C.o: - TickTimer_Interrupt SetCV SetPV HWEnDi TickTimer_SetPeriodTicks16 - TickTimer_SetPeriodTicks32 TickTimer_SetPeriodUS TickTimer_SetPeriodMS -Byte1.C.o: - Byte1_GetMsk -PE_Timer.C.o: - PE_Timer_LngMul PE_Timer_LngHi2 PE_Timer_LngHi3 PE_Timer_LngHi4 -COM0.C.o: - HWEnDi -port.c.o: - vPortEndScheduler prvSetupTimerInterrupt -NOT USED VARIABLES -STRING.C.o (ansibi.lib): - STRING..1 next.2 -rtshc12.c.o (ansibi.lib): - _PowOfTwo_8 _PowOfTwo_16 _PowOfTwo_32 -Cpu.C.o: - CpuMode CCR_reg -heap_2.c.o: - heapSTRUCT_SIZE -death.c.o: - uxMaxNumberOfExtraTasksRunning - -********************************************************************************************* -COPYDOWN SECTION ---------------------------------------------------------------------------------------------- -------- ROM-ADDRESS: 0xC3B5 ---- SIZE 4 --- -Filling bytes inserted - 00011000 -------- ROM-ADDRESS: 0xC3B9 ---- RAM-ADDRESS: 0x1000 ---- SIZE 1 --- -Name of initialized Object : uxCriticalNesting - FF -------- ROM-ADDRESS: 0xC3BA ---- SIZE 4 --- -Filling bytes inserted - 001038F4 -------- ROM-ADDRESS: 0xC3BE ---- RAM-ADDRESS: 0x38F4 ---- SIZE 8 --- -Name of initialized Object : Byte1_Table - 0102040810 204080 -------- ROM-ADDRESS: 0xC3C6 ---- SIZE 1 --- -Filling bytes inserted - 00 -------- ROM-ADDRESS: 0xC3C7 ---- RAM-ADDRESS: 0x38FD ---- SIZE 7 --- -Name of initialized Object : COM0_PrescHigh.1:1 - 29005100A3 0146 -------- ROM-ADDRESS: 0xC3CE ---- SIZE 2 --- -Filling bytes inserted - 0000 - -********************************************************************************************* -OBJECT-DEPENDENCIES SECTION ---------------------------------------------------------------------------------------------- -_EntryPoint USES _INITRM _INITEE _MISC _CLKSEL _PLLCTL _SYNR - _REFDV _CRGFLG _Startup -PE_low_level_init USES _TSCR1 _TCTL2 _TCTL1 _TIE _TTOV _TSCR2 _TIOS - _PWMCTL _PWMSDN _ICSYS _MCCTL TickTimer_Init _PORTAB - _DDRAB _DDRS _PTS COM0_Init _INTCR -_Startup USES _startupData Init -_LDIVU USES _lDivMod -_LDIVS USES _NEG_P _lDivMod -vCOM0_ISR USES _SCI0SR1 _SCI0DRL xRxedChars xQueueSendFromISR - _SCI0CR2 xCharsForTx xQueueReceiveFromISR -xBankedStartScheduler USES TickTimer_SetFreqHz TickTimer_Enable - pxCurrentTCB uxCriticalNesting -vPortYield USES uxCriticalNesting pxCurrentTCB - vTaskSwitchContext -vPortTickInterrupt USES uxCriticalNesting pxCurrentTCB - vTaskIncrementTick vTaskSwitchContext _TFLG1 -_vect USES Cpu_Interrupt vCOM0_ISR vPortTickInterrupt - vPortYield _EntryPoint -Init USES _startupData -main USES PE_low_level_init vMain -vMain USES vStartLEDFlashTasks vStartPolledQueueTasks - vStartDynamicPriorityTasks vAltStartComTestTasks vStartBlockingQueueTasks - vStartIntegerMathTasks vCreateSuicidalTasks vErrorChecks - STRING.Check.1 xTaskCreate vTaskStartScheduler -vErrorChecks USES xTaskGetTickCount vTaskDelayUntil - prvCheckOtherTasksAreStillRunning _LCMP vParTestToggleLED -prvCheckOtherTasksAreStillRunning USES xArePollingQueuesStillRunning - xAreDynamicPriorityTasksStillRunning xAreComTestTasksStillRunning - xAreIntegerMathsTaskStillRunning xAreBlockingQueuesStillRunning - xIsCreateTaskStillRunning xLocalError -vApplicationIdleHook USES _LNEG _LDIVS _LCMP_P uxCriticalNesting - xLocalError -vParTestSetLED USES uxCriticalNesting Byte1_PutBit -vParTestToggleLED USES uxCriticalNesting Byte1_NegBit -xSerialPortInitMinimal USES xQueueCreate xRxedChars xCharsForTx - COM0_SetBaudRateMode -xSerialGetChar USES xRxedChars xQueueReceive -xSerialPutChar USES xCharsForTx xQueueSend _SCI0CR2 -xTaskCreate USES prvAllocateTCBAndStack - prvInitialiseTCBVariables pxPortInitialiseStack uxCriticalNesting - uxCurrentNumberOfTasks pxCurrentTCB prvInitialiseTaskLists - xSchedulerRunning uxTopUsedPriority uxTaskNumber.1 - uxTopReadyPriority pxReadyTasksLists vListInsertEnd -vTaskDelete USES uxCriticalNesting pxCurrentTCB vListRemove - xTasksWaitingTermination vListInsertEnd uxTasksDeleted -vTaskDelayUntil USES vTaskSuspendAll xTickCount pxCurrentTCB - vListRemove pxOverflowDelayedTaskList pxDelayedTaskList - vListInsert xTaskResumeAll -vTaskDelay USES vTaskSuspendAll xTickCount pxCurrentTCB - vListRemove pxOverflowDelayedTaskList pxDelayedTaskList - vListInsert xTaskResumeAll -uxTaskPriorityGet USES uxCriticalNesting pxCurrentTCB -vTaskPrioritySet USES uxCriticalNesting pxCurrentTCB - pxReadyTasksLists vListRemove uxTopReadyPriority vListInsertEnd -vTaskSuspend USES uxCriticalNesting pxCurrentTCB vListRemove - xSuspendedTaskList vListInsertEnd -vTaskResume USES uxCriticalNesting pxCurrentTCB vListRemove - uxTopReadyPriority pxReadyTasksLists vListInsertEnd -vTaskStartScheduler USES pxCurrentTCB prvIdleTask STRING.IDLE.2 - xTaskCreate xSchedulerRunning xTickCount - xPortStartScheduler -vTaskSuspendAll USES uxCriticalNesting uxSchedulerSuspended -xTaskResumeAll USES uxCriticalNesting uxSchedulerSuspended - uxCurrentNumberOfTasks vListRemove uxTopReadyPriority - pxReadyTasksLists vListInsertEnd pxCurrentTCB xPendingReadyList - uxMissedTicks vTaskIncrementTick -xTaskGetTickCount USES uxCriticalNesting xTickCount -uxTaskGetNumberOfTasks USES uxCriticalNesting uxCurrentNumberOfTasks -vTaskIncrementTick USES uxSchedulerSuspended xTickCount - pxDelayedTaskList pxOverflowDelayedTaskList vListRemove - uxTopReadyPriority pxReadyTasksLists vListInsertEnd uxMissedTicks -vTaskSwitchContext USES uxSchedulerSuspended uxTopReadyPriority - pxCurrentTCB pxReadyTasksLists -vTaskPlaceOnEventList USES pxCurrentTCB vListInsert xTickCount vListRemove - pxOverflowDelayedTaskList pxDelayedTaskList -xTaskRemoveFromEventList USES vListRemove uxSchedulerSuspended - uxTopReadyPriority pxReadyTasksLists xPendingReadyList - vListInsertEnd pxCurrentTCB -prvIdleTask USES prvCheckTasksWaitingTermination - pxReadyTasksLists vApplicationIdleHook -prvInitialiseTCBVariables USES strncpy vListInitialiseItem -prvInitialiseTaskLists USES pxReadyTasksLists xDelayedTaskList1 - xDelayedTaskList2 xPendingReadyList xTasksWaitingTermination - xSuspendedTaskList pxDelayedTaskList pxOverflowDelayedTaskList - vListInitialise -prvCheckTasksWaitingTermination USES uxTasksDeleted vTaskSuspendAll - xTasksWaitingTermination xTaskResumeAll uxCriticalNesting vListRemove - uxCurrentNumberOfTasks prvDeleteTCB -prvAllocateTCBAndStack USES pvPortMalloc vPortFree memset -prvDeleteTCB USES vPortFree -xQueueCreate USES pvPortMalloc vListInitialise vPortFree -xQueueSend USES vTaskSuspendAll uxCriticalNesting xQueueSend - prvIsQueueFull vTaskPlaceOnEventList prvUnlockQueue - xTaskResumeAll memcpy -xQueueSendFromISR USES memcpy xTaskRemoveFromEventList -xQueueReceive USES vTaskSuspendAll uxCriticalNesting xQueueReceive - prvIsQueueEmpty vTaskPlaceOnEventList prvUnlockQueue - xTaskResumeAll memcpy -xQueueReceiveFromISR USES memcpy xTaskRemoveFromEventList -uxQueueMessagesWaiting USES uxCriticalNesting -prvUnlockQueue USES uxCriticalNesting xTaskRemoveFromEventList -prvIsQueueEmpty USES uxCriticalNesting -prvIsQueueFull USES uxCriticalNesting -vListInitialise USES vListInitialiseItem -pvPortMalloc USES vTaskSuspendAll xHeapHasBeenInitialised.1 xHeap - xStart xEnd xTaskResumeAll -vPortFree USES vTaskSuspendAll xStart xTaskResumeAll -vStartLEDFlashTasks USES vLEDFlashTask STRING.LEDx.1 xTaskCreate -vLEDFlashTask USES uxCriticalNesting uxFlashTaskNumber - xTaskGetTickCount vTaskDelayUntil vParTestToggleLED -vStartDynamicPriorityTasks USES xQueueCreate xSuspendedTestQueue - vContinuousIncrementTask STRING.CNT_INC.1 ulCounter - xContinousIncrementHandle xTaskCreate vLimitedIncrementTask - STRING.LIM_INC.2 xLimitedIncrementHandle vCounterControlTask - STRING.C_CTRL.3 vQueueSendWhenSuspendedTask STRING.SUSP_TX.4 - vQueueReceiveWhenSuspendedTask STRING.SUSP_RX.5 -vLimitedIncrementTask USES _LINC _LCMP_P vTaskSuspend -vContinuousIncrementTask USES uxTaskPriorityGet vTaskPrioritySet _LINC -vCounterControlTask USES vCounterControlTask xContinousIncrementHandle - vTaskSuspend ulCounter vTaskResume vTaskDelay - vTaskSuspendAll xTaskResumeAll xLimitedIncrementHandle - uxCriticalNesting usCheckVariable -vQueueSendWhenSuspendedTask USES vTaskSuspendAll xSuspendedTestQueue - ulValueToSend.6 xQueueSend xSuspendedQueueSendError - xTaskResumeAll vTaskDelay _LINC -vQueueReceiveWhenSuspendedTask USES vTaskSuspendAll xSuspendedTestQueue - ulReceivedValue.8 xQueueReceive xTaskResumeAll - xSuspendedQueueReceiveError ulExpectedValue.7 _LINC -xAreDynamicPriorityTasksStillRunning USES usCheckVariable usLastTaskCheck.9 - xSuspendedQueueSendError xSuspendedQueueReceiveError -vStartPolledQueueTasks USES xQueueCreate xPolledQueue.1 - vPolledQueueConsumer STRING.QConsNB.2 xTaskCreate - vPolledQueueProducer STRING.QProdNB.3 -vPolledQueueProducer USES xQueueSend uxCriticalNesting - xPollingProducerCount vTaskDelay -vPolledQueueConsumer USES xQueueReceive uxCriticalNesting - xPollingConsumerCount uxQueueMessagesWaiting vTaskDelay -xArePollingQueuesStillRunning USES xPollingConsumerCount xPollingProducerCount -PE_Timer_LngHi1 USES _LCMP -vAltStartComTestTasks USES uxBaseLED xSerialPortInitMinimal vComTxTask - STRING.COMTx.1 xTaskCreate vComRxTask STRING.COMRx.2 -vComTxTask USES xPort xSerialPutChar uxBaseLED - vParTestToggleLED vParTestSetLED xTaskGetTickCount vTaskDelay -vComRxTask USES xPort xSerialGetChar uxBaseLED - vParTestToggleLED vParTestSetLED uxRxLoops -xAreComTestTasksStillRunning USES uxRxLoops -xPortStartScheduler USES xBankedStartScheduler -vStartIntegerMathTasks USES vCompeteingIntMathTask STRING.IntMath.1 - xTaskCheck xTaskCreate -vCompeteingIntMathTask USES _LNEG _LDIVS _LCMP_P uxCriticalNesting -xAreIntegerMathsTaskStillRunning USES xTaskCheck -vStartBlockingQueueTasks USES vStartBlockingQueueTasks xQueueCreate - sBlockingConsumerCount sBlockingProducerCount vBlockingQueueConsumer - STRING.QConsB1.1 xTaskCreate vBlockingQueueProducer - STRING.QProdB2.2 STRING.QProdB3.3 STRING.QConsB4.4 - STRING.QProdB5.5 STRING.QConsB6.6 pvPortMalloc -vBlockingQueueProducer USES xQueueSend -vBlockingQueueConsumer USES xQueueReceive -xAreBlockingQueuesStillRunning USES sLastBlockingConsumerCount.7 - sBlockingProducerCount sLastBlockingProducerCount.8 - sBlockingConsumerCount -vCreateSuicidalTasks USES pvPortMalloc vCreateTasks STRING.CREATOR.1 - xTaskCreate uxTaskGetNumberOfTasks uxTasksRunningAtStart -vSuicidalTask USES _LMUL vTaskDelay vTaskDelete -vCreateTasks USES vPortFree vTaskDelay vSuicidalTask - STRING.SUICIDE1.2 xCreatedTask1 xTaskCreate STRING.SUICIDE2.3 - STRING.SUICIDE1.4 xCreatedTask2 STRING.SUICIDE2.5 - usCreationCount vCreateTasks -xIsCreateTaskStillRunning USES usLastCreationCount.6 usCreationCount - uxTaskGetNumberOfTasks uxTasksRunningNow.7 uxTasksRunningAtStart -TickTimer_Enable USES _TFLG1 _TIE -TickTimer_SetFreqHz USES _LDIVU PE_Timer_LngHi1 CmpHighVal _TC0 _TC7 -TickTimer_Init USES CmpHighVal _TC0 _TC7 _TSCR2 _TFLG1 _TIE -Byte1_PutBit USES Byte1_Table _PORTAB -Byte1_NegBit USES Byte1_Table _PORTAB -COM0_SetBaudRateMode USES NumMode COM0_PrescHigh.1 PrescHigh _SCI0BD -COM0_Init USES PrescHigh SerFlag NumMode _SCI0CR1 _SCI0SR2 - _SCI0SR1 _SCI0CR2 _SCI0BD - -********************************************************************************************* -DEPENDENCY TREE -********************************************************************************************* - main and _Startup Group - | - +- main - | | - | +- PE_low_level_init - | | | - | | +- TickTimer_Init - | | | - | | +- COM0_Init - | | - | +- vMain - | | - | +- vStartLEDFlashTasks - | | | - | | +- vLEDFlashTask - | | | | - | | | +- xTaskGetTickCount - | | | | - | | | +- vTaskDelayUntil - | | | | | - | | | | +- vTaskSuspendAll - | | | | | - | | | | +- vListRemove - | | | | | - | | | | +- vListInsert - | | | | | - | | | | +- xTaskResumeAll - | | | | | - | | | | +- vListRemove (see above) - | | | | | - | | | | +- vListInsertEnd - | | | | | - | | | | +- vTaskIncrementTick - | | | | | - | | | | +- vListRemove (see above) - | | | | | - | | | | +- vListInsertEnd (see above) - | | | | - | | | +- vParTestToggleLED - | | | | - | | | +- Byte1_NegBit - | | | - | | +- xTaskCreate - | | | - | | +- prvAllocateTCBAndStack - | | | | - | | | +- pvPortMalloc - | | | | | - | | | | +- vTaskSuspendAll (see above) - | | | | | - | | | | +- xTaskResumeAll (see above) - | | | | - | | | +- vPortFree - | | | | | - | | | | +- vTaskSuspendAll (see above) - | | | | | - | | | | +- xTaskResumeAll (see above) - | | | | - | | | +- memset - | | | - | | +- prvInitialiseTCBVariables - | | | | - | | | +- strncpy - | | | | - | | | +- vListInitialiseItem - | | | - | | +- pxPortInitialiseStack - | | | - | | +- prvInitialiseTaskLists - | | | | - | | | +- vListInitialise - | | | | - | | | +- vListInitialiseItem (see above) - | | | - | | +- vListInsertEnd (see above) - | | - | +- vStartPolledQueueTasks - | | | - | | +- xQueueCreate - | | | | - | | | +- pvPortMalloc (see above) - | | | | - | | | +- vListInitialise (see above) - | | | | - | | | +- vPortFree (see above) - | | | - | | +- vPolledQueueConsumer - | | | | - | | | +- xQueueReceive - | | | | | - | | | | +- vTaskSuspendAll (see above) - | | | | | - | | | | +- prvIsQueueEmpty - | | | | | - | | | | +- vTaskPlaceOnEventList - | | | | | | - | | | | | +- vListInsert (see above) - | | | | | | - | | | | | +- vListRemove (see above) - | | | | | - | | | | +- prvUnlockQueue - | | | | | | - | | | | | +- xTaskRemoveFromEventList - | | | | | | - | | | | | +- vListRemove (see above) - | | | | | | - | | | | | +- vListInsertEnd (see above) - | | | | | - | | | | +- xTaskResumeAll (see above) - | | | | | - | | | | +- memcpy - | | | | - | | | +- uxQueueMessagesWaiting - | | | | - | | | +- vTaskDelay - | | | | - | | | +- vTaskSuspendAll (see above) - | | | | - | | | +- vListRemove (see above) - | | | | - | | | +- vListInsert (see above) - | | | | - | | | +- xTaskResumeAll (see above) - | | | - | | +- xTaskCreate (see above) - | | | - | | +- vPolledQueueProducer - | | | - | | +- xQueueSend - | | | | - | | | +- vTaskSuspendAll (see above) - | | | | - | | | +- prvIsQueueFull - | | | | - | | | +- vTaskPlaceOnEventList (see above) - | | | | - | | | +- prvUnlockQueue (see above) - | | | | - | | | +- xTaskResumeAll (see above) - | | | | - | | | +- memcpy (see above) - | | | - | | +- vTaskDelay (see above) - | | - | +- vStartDynamicPriorityTasks - | | | - | | +- xQueueCreate (see above) - | | | - | | +- vContinuousIncrementTask - | | | | - | | | +- uxTaskPriorityGet - | | | | - | | | +- vTaskPrioritySet - | | | | | - | | | | +- vListRemove (see above) - | | | | | - | | | | +- vListInsertEnd (see above) - | | | | - | | | +- _LINC - | | | - | | +- xTaskCreate (see above) - | | | - | | +- vLimitedIncrementTask - | | | | - | | | +- _LINC (see above) - | | | | - | | | +- _LCMP_P - | | | | - | | | +- vTaskSuspend - | | | | - | | | +- vListRemove (see above) - | | | | - | | | +- vListInsertEnd (see above) - | | | - | | +- vCounterControlTask - | | | | - | | | +- vTaskSuspend (see above) - | | | | - | | | +- vTaskResume - | | | | | - | | | | +- vListRemove (see above) - | | | | | - | | | | +- vListInsertEnd (see above) - | | | | - | | | +- vTaskDelay (see above) - | | | | - | | | +- vTaskSuspendAll (see above) - | | | | - | | | +- xTaskResumeAll (see above) - | | | - | | +- vQueueSendWhenSuspendedTask - | | | | - | | | +- vTaskSuspendAll (see above) - | | | | - | | | +- xQueueSend (see above) - | | | | - | | | +- xTaskResumeAll (see above) - | | | | - | | | +- vTaskDelay (see above) - | | | | - | | | +- _LINC (see above) - | | | - | | +- vQueueReceiveWhenSuspendedTask - | | | - | | +- vTaskSuspendAll (see above) - | | | - | | +- xQueueReceive (see above) - | | | - | | +- xTaskResumeAll (see above) - | | | - | | +- _LINC (see above) - | | - | +- vAltStartComTestTasks - | | | - | | +- xSerialPortInitMinimal - | | | | - | | | +- xQueueCreate (see above) - | | | | - | | | +- COM0_SetBaudRateMode - | | | - | | +- vComTxTask - | | | | - | | | +- xSerialPutChar - | | | | | - | | | | +- xQueueSend (see above) - | | | | - | | | +- vParTestToggleLED (see above) - | | | | - | | | +- vParTestSetLED - | | | | | - | | | | +- Byte1_PutBit - | | | | - | | | +- xTaskGetTickCount (see above) - | | | | - | | | +- vTaskDelay (see above) - | | | - | | +- xTaskCreate (see above) - | | | - | | +- vComRxTask - | | | - | | +- xSerialGetChar - | | | | - | | | +- xQueueReceive (see above) - | | | - | | +- vParTestToggleLED (see above) - | | | - | | +- vParTestSetLED (see above) - | | - | +- vStartBlockingQueueTasks - | | | - | | +- xQueueCreate (see above) - | | | - | | +- vBlockingQueueConsumer - | | | | - | | | +- xQueueReceive (see above) - | | | - | | +- xTaskCreate (see above) - | | | - | | +- vBlockingQueueProducer - | | | | - | | | +- xQueueSend (see above) - | | | - | | +- pvPortMalloc (see above) - | | - | +- vStartIntegerMathTasks - | | | - | | +- vCompeteingIntMathTask - | | | | - | | | +- _LNEG - | | | | - | | | +- _LDIVS - | | | | | - | | | | +- _NEG_P - | | | | | - | | | | +- _lDivMod - | | | | - | | | +- _LCMP_P (see above) - | | | - | | +- xTaskCreate (see above) - | | - | +- vCreateSuicidalTasks - | | | - | | +- pvPortMalloc (see above) - | | | - | | +- vCreateTasks - | | | | - | | | +- vPortFree (see above) - | | | | - | | | +- vTaskDelay (see above) - | | | | - | | | +- vSuicidalTask - | | | | | - | | | | +- _LMUL - | | | | | - | | | | +- vTaskDelay (see above) - | | | | | - | | | | +- vTaskDelete - | | | | | - | | | | +- vListRemove (see above) - | | | | | - | | | | +- vListInsertEnd (see above) - | | | | - | | | +- xTaskCreate (see above) - | | | - | | +- xTaskCreate (see above) - | | | - | | +- uxTaskGetNumberOfTasks - | | - | +- vErrorChecks - | | | - | | +- xTaskGetTickCount (see above) - | | | - | | +- vTaskDelayUntil (see above) - | | | - | | +- prvCheckOtherTasksAreStillRunning - | | | | - | | | +- xArePollingQueuesStillRunning - | | | | - | | | +- xAreDynamicPriorityTasksStillRunning - | | | | - | | | +- xAreComTestTasksStillRunning - | | | | - | | | +- xAreIntegerMathsTaskStillRunning - | | | | - | | | +- xAreBlockingQueuesStillRunning - | | | | - | | | +- xIsCreateTaskStillRunning - | | | | - | | | +- uxTaskGetNumberOfTasks (see above) - | | | - | | +- _LCMP - | | | - | | +- vParTestToggleLED (see above) - | | - | +- xTaskCreate (see above) - | | - | +- vTaskStartScheduler - | | - | +- prvIdleTask - | | | - | | +- prvCheckTasksWaitingTermination - | | | | - | | | +- vTaskSuspendAll (see above) - | | | | - | | | +- xTaskResumeAll (see above) - | | | | - | | | +- vListRemove (see above) - | | | | - | | | +- prvDeleteTCB - | | | | - | | | +- vPortFree (see above) - | | | - | | +- vApplicationIdleHook - | | | - | | +- _LNEG (see above) - | | | - | | +- _LDIVS (see above) - | | | - | | +- _LCMP_P (see above) - | | - | +- xTaskCreate (see above) - | | - | +- xPortStartScheduler - | | - | +- xBankedStartScheduler - | | - | +- TickTimer_SetFreqHz - | | | - | | +- _LDIVU - | | | | - | | | +- _lDivMod (see above) - | | | - | | +- PE_Timer_LngHi1 - | | | - | | +- _LCMP (see above) - | | - | +- TickTimer_Enable - | - +- _EntryPoint - | - +- _Startup - | - +- Init - - _vect - | - +- Cpu_Interrupt - | - +- vCOM0_ISR - | | - | +- xQueueSendFromISR - | | | - | | +- memcpy (see above) - | | | - | | +- xTaskRemoveFromEventList (see above) - | | - | +- xQueueReceiveFromISR - | | - | +- memcpy (see above) - | | - | +- xTaskRemoveFromEventList (see above) - | - +- vPortTickInterrupt - | | - | +- vTaskIncrementTick (see above) - | | - | +- vTaskSwitchContext - | - +- vPortYield - | | - | +- vTaskSwitchContext (see above) - | - +- _EntryPoint (see above) - -********************************************************************************************* -STATISTIC SECTION ---------------------------------------------------------------------------------------------- - -ExeFile: --------- -Number of blocks to be downloaded: 18 -Total size of all blocks to be downloaded: 7636 - diff --git a/Demo/HCS12_CodeWarrior_banked/bin/Simulator.map b/Demo/HCS12_CodeWarrior_banked/bin/Simulator.map deleted file mode 100644 index 6c7e3b7e4..000000000 --- a/Demo/HCS12_CodeWarrior_banked/bin/Simulator.map +++ /dev/null @@ -1,4026 +0,0 @@ - -PROGRAM "E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_banked\bin\Simulator.abs" - -********************************************************************************************* -TARGET SECTION ---------------------------------------------------------------------------------------------- -Processor : Motorola HC12 -Memory Model: BANKED -File Format : ELF\Dwarf 2.0 -Linker : SmartLinker V-5.0.22 Build 4047, Feb 17 2004 - -********************************************************************************************* -FILE SECTION ---------------------------------------------------------------------------------------------- -Start12.c.o Model: BANKED, Lang: ANSI-C -STRING.C.o (ansibi.lib) Model: BANKED, Lang: ANSI-C -rtshc12.c.o (ansibi.lib) Model: BANKED, Lang: ANSI-C -Cpu.C.o Model: BANKED, Lang: ANSI-C -IO_Map.C.o Model: BANKED, Lang: ANSI-C -Vectors.c.o Model: BANKED, Lang: ANSI-C -RTOSDemo.C.o Model: BANKED, Lang: ANSI-C -main.c.o Model: BANKED, Lang: ANSI-C -ParTest.c.o Model: BANKED, Lang: ANSI-C -serial.c.o Model: BANKED, Lang: ANSI-C -tasks.c.o Model: BANKED, Lang: ANSI-C -queue.c.o Model: BANKED, Lang: ANSI-C -list.c.o Model: BANKED, Lang: ANSI-C -heap_2.c.o Model: BANKED, Lang: ANSI-C -TickTimer.C.o Model: BANKED, Lang: ANSI-C -PE_Timer.C.o Model: BANKED, Lang: ANSI-C -Byte1.C.o Model: BANKED, Lang: ANSI-C -flash.c.o Model: BANKED, Lang: ANSI-C -dynamic.c.o Model: BANKED, Lang: ANSI-C -PollQ.c.o Model: BANKED, Lang: ANSI-C -comtest.c.o Model: BANKED, Lang: ANSI-C -COM0.C.o Model: BANKED, Lang: ANSI-C -port.c.o Model: BANKED, Lang: ANSI-C -integer.c.o Model: BANKED, Lang: ANSI-C -BlockQ.c.o Model: BANKED, Lang: ANSI-C -death.c.o Model: BANKED, Lang: ANSI-C - -********************************************************************************************* -STARTUP SECTION ---------------------------------------------------------------------------------------------- -Entry point: 0xC000 (_EntryPoint) -_startupData is allocated at 0xC07C and uses 24 Bytes -extern struct _tagStartup { - unsigned flags 0 - _PFunc main 0x30809A (main) - long stackOffset 0x3988 - unsigned nofZeroOut 1 - _Range pZeroOut 0x1000 10505 - _Copy *toCopyDownBeg 0xC3AE - int nofLibInits 0 - _LibInit *libInits 0xC098 - int nofInitBodies 0 - _Cpp *initBodies 0xC09A - int nofFiniBodies 0 - _Cpp *finiBodies 0xC09A -} _startupData; - -********************************************************************************************* -SECTION-ALLOCATION SECTION -Section Name Size Type From To Segment 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0x338000 0x338233 ROM_PAGE33 -ROM_PAGE34_527 579 R 0x348000 0x348242 ROM_PAGE34 -ROM_PAGE35_528 589 R 0x358000 0x35824C ROM_PAGE35 -ROM_PAGE36_529 555 R 0x368000 0x36822A ROM_PAGE36 -ROM_PAGE37_530 578 R 0x378000 0x378241 ROM_PAGE37 -ROM_PAGE38_531 558 R 0x388000 0x38822D ROM_PAGE38 -ROM_PAGE39_532 288 R 0x398000 0x39811F ROM_PAGE39 -ROM_PAGE3A_533 574 R 0x3A8000 0x3A823D ROM_PAGE3A -ROM_PAGE3B_534 284 R 0x3B8000 0x3B811B ROM_PAGE3B - -Summary of section sizes per section type: -READ_ONLY (R): 1DD3 (dec: 7635) -READ_WRITE (R/W): 2989 (dec: 10633) -NO_INIT (N/I): 241 (dec: 577) - -********************************************************************************************* -VECTOR-ALLOCATION SECTION - Address InitValue InitFunction ---------------------------------------------------------------------------------------------- - -********************************************************************************************* -OBJECT-ALLOCATION SECTION - Name Module Addr hSize dSize Ref Section RLIB ---------------------------------------------------------------------------------------------- -MODULE: -- Start12.c.o -- -- PROCEDURES: - Init 308000 29 41 2 .text - _Startup C151 12 18 1 NON_BANKED -- VARIABLES: - _startupData C07C 18 24 6 .startData -MODULE: -- STRING.C.o (ansibi.lib) -- -- PROCEDURES: - memcpy 308029 26 38 8 .text - memset 30804F 1E 30 2 .text - strncpy 30806D 2D 45 2 .text -- VARIABLES: -MODULE: -- rtshc12.c.o (ansibi.lib) -- -- PROCEDURES: - _LCMP C163 19 25 2 NON_BANKED - _LCMP_P C17C 15 21 3 NON_BANKED - _LNEG C191 D 13 2 NON_BANKED - _LINC C19E 5 5 4 NON_BANKED - _LMUL C1A3 27 39 1 NON_BANKED - _lDivMod C1CA E3 227 3 NON_BANKED - _LDIVU C2AD E 14 1 NON_BANKED - _NEG_P C2BB F 15 4 NON_BANKED - _LDIVS C2CA 35 53 2 NON_BANKED -- VARIABLES: -MODULE: -- Cpu.C.o -- -- PROCEDURES: - _EntryPoint C000 2E 46 1 .init - PE_low_level_init C02E 4E 78 2 .init - Cpu_Interrupt C2FF 1 1 60 NON_BANKED -- VARIABLES: -MODULE: -- IO_Map.C.o -- -- PROCEDURES: -- VARIABLES: - _ARMCOP 3F 1 1 0 .abs_section_3f - _ATD0DIEN 8D 1 1 0 .abs_section_8d - _ATD0STAT0 86 1 1 0 .abs_section_86 - _ATD0STAT1 8B 1 1 0 .abs_section_8b - _ATD1DIEN 12D 1 1 0 .abs_section_12d - _ATD1STAT0 126 1 1 0 .abs_section_126 - _ATD1STAT1 12B 1 1 0 .abs_section_12b - _BDMCCR FF06 1 1 0 .abs_section_ff06 - _BDMINR FF07 1 1 0 .abs_section_ff07 - _BDMSTS FF01 1 1 0 .abs_section_ff01 - _BKP0H 2B 1 1 0 .abs_section_2b - _BKP0L 2C 1 1 0 .abs_section_2c - _BKP0X 2A 1 1 0 .abs_section_2a - _BKP1H 2E 1 1 0 .abs_section_2e - _BKP1L 2F 1 1 0 .abs_section_2f - _BKP1X 2D 1 1 0 .abs_section_2d - _BKPCT0 28 1 1 0 .abs_section_28 - _BKPCT1 29 1 1 0 .abs_section_29 - _CAN0BTR0 142 1 1 0 .abs_section_142 - _CAN0BTR1 143 1 1 0 .abs_section_143 - _CAN0CTL0 140 1 1 0 .abs_section_140 - _CAN0CTL1 141 1 1 0 .abs_section_141 - _CAN0IDAC 14B 1 1 0 .abs_section_14b - _CAN0IDAR0 150 1 1 0 .abs_section_150 - _CAN0IDAR1 151 1 1 0 .abs_section_151 - _CAN0IDAR2 152 1 1 0 .abs_section_152 - _CAN0IDAR3 153 1 1 0 .abs_section_153 - _CAN0IDAR4 158 1 1 0 .abs_section_158 - _CAN0IDAR5 159 1 1 0 .abs_section_159 - _CAN0IDAR6 15A 1 1 0 .abs_section_15a - _CAN0IDAR7 15B 1 1 0 .abs_section_15b - _CAN0IDMR0 154 1 1 0 .abs_section_154 - _CAN0IDMR1 155 1 1 0 .abs_section_155 - _CAN0IDMR2 156 1 1 0 .abs_section_156 - _CAN0IDMR3 157 1 1 0 .abs_section_157 - _CAN0IDMR4 15C 1 1 0 .abs_section_15c - _CAN0IDMR5 15D 1 1 0 .abs_section_15d - _CAN0IDMR6 15E 1 1 0 .abs_section_15e - _CAN0IDMR7 15F 1 1 0 .abs_section_15f - _CAN0RFLG 144 1 1 0 .abs_section_144 - _CAN0RIER 145 1 1 0 .abs_section_145 - _CAN0RXDLR 16C 1 1 0 .abs_section_16c - _CAN0RXDSR0 164 1 1 0 .abs_section_164 - _CAN0RXDSR1 165 1 1 0 .abs_section_165 - _CAN0RXDSR2 166 1 1 0 .abs_section_166 - _CAN0RXDSR3 167 1 1 0 .abs_section_167 - _CAN0RXDSR4 168 1 1 0 .abs_section_168 - _CAN0RXDSR5 169 1 1 0 .abs_section_169 - _CAN0RXDSR6 16A 1 1 0 .abs_section_16a - _CAN0RXDSR7 16B 1 1 0 .abs_section_16b - _CAN0RXERR 14E 1 1 0 .abs_section_14e - _CAN0RXIDR0 160 1 1 0 .abs_section_160 - _CAN0RXIDR1 161 1 1 0 .abs_section_161 - _CAN0RXIDR2 162 1 1 0 .abs_section_162 - _CAN0RXIDR3 163 1 1 0 .abs_section_163 - _CAN0TAAK 149 1 1 0 .abs_section_149 - _CAN0TARQ 148 1 1 0 .abs_section_148 - _CAN0TBSEL 14A 1 1 0 .abs_section_14a - _CAN0TFLG 146 1 1 0 .abs_section_146 - _CAN0TIER 147 1 1 0 .abs_section_147 - _CAN0TXDLR 17C 1 1 0 .abs_section_17c - _CAN0TXDSR0 174 1 1 0 .abs_section_174 - _CAN0TXDSR1 175 1 1 0 .abs_section_175 - _CAN0TXDSR2 176 1 1 0 .abs_section_176 - _CAN0TXDSR3 177 1 1 0 .abs_section_177 - _CAN0TXDSR4 178 1 1 0 .abs_section_178 - _CAN0TXDSR5 179 1 1 0 .abs_section_179 - _CAN0TXDSR6 17A 1 1 0 .abs_section_17a - _CAN0TXDSR7 17B 1 1 0 .abs_section_17b - _CAN0TXERR 14F 1 1 0 .abs_section_14f - _CAN0TXIDR0 170 1 1 0 .abs_section_170 - _CAN0TXIDR1 171 1 1 0 .abs_section_171 - _CAN0TXIDR2 172 1 1 0 .abs_section_172 - _CAN0TXIDR3 173 1 1 0 .abs_section_173 - _CAN0TXTBPR 17F 1 1 0 .abs_section_17f - _CAN1BTR0 182 1 1 0 .abs_section_182 - _CAN1BTR1 183 1 1 0 .abs_section_183 - _CAN1CTL0 180 1 1 0 .abs_section_180 - _CAN1CTL1 181 1 1 0 .abs_section_181 - _CAN1IDAC 18B 1 1 0 .abs_section_18b - _CAN1IDAR0 190 1 1 0 .abs_section_190 - _CAN1IDAR1 191 1 1 0 .abs_section_191 - _CAN1IDAR2 192 1 1 0 .abs_section_192 - _CAN1IDAR3 193 1 1 0 .abs_section_193 - _CAN1IDAR4 198 1 1 0 .abs_section_198 - _CAN1IDAR5 199 1 1 0 .abs_section_199 - _CAN1IDAR6 19A 1 1 0 .abs_section_19a - _CAN1IDAR7 19B 1 1 0 .abs_section_19b - _CAN1IDMR0 194 1 1 0 .abs_section_194 - _CAN1IDMR1 195 1 1 0 .abs_section_195 - _CAN1IDMR2 196 1 1 0 .abs_section_196 - _CAN1IDMR3 197 1 1 0 .abs_section_197 - _CAN1IDMR4 19C 1 1 0 .abs_section_19c - _CAN1IDMR5 19D 1 1 0 .abs_section_19d - _CAN1IDMR6 19E 1 1 0 .abs_section_19e - _CAN1IDMR7 19F 1 1 0 .abs_section_19f - _CAN1RFLG 184 1 1 0 .abs_section_184 - _CAN1RIER 185 1 1 0 .abs_section_185 - _CAN1RXDLR 1AC 1 1 0 .abs_section_1ac - _CAN1RXDSR0 1A4 1 1 0 .abs_section_1a4 - _CAN1RXDSR1 1A5 1 1 0 .abs_section_1a5 - _CAN1RXDSR2 1A6 1 1 0 .abs_section_1a6 - _CAN1RXDSR3 1A7 1 1 0 .abs_section_1a7 - _CAN1RXDSR4 1A8 1 1 0 .abs_section_1a8 - _CAN1RXDSR5 1A9 1 1 0 .abs_section_1a9 - _CAN1RXDSR6 1AA 1 1 0 .abs_section_1aa - _CAN1RXDSR7 1AB 1 1 0 .abs_section_1ab - _CAN1RXERR 18E 1 1 0 .abs_section_18e - _CAN1RXIDR0 1A0 1 1 0 .abs_section_1a0 - _CAN1RXIDR1 1A1 1 1 0 .abs_section_1a1 - _CAN1RXIDR2 1A2 1 1 0 .abs_section_1a2 - _CAN1RXIDR3 1A3 1 1 0 .abs_section_1a3 - _CAN1TAAK 189 1 1 0 .abs_section_189 - _CAN1TARQ 188 1 1 0 .abs_section_188 - _CAN1TBSEL 18A 1 1 0 .abs_section_18a - _CAN1TFLG 186 1 1 0 .abs_section_186 - _CAN1TIER 187 1 1 0 .abs_section_187 - _CAN1TXDLR 1BC 1 1 0 .abs_section_1bc - _CAN1TXDSR0 1B4 1 1 0 .abs_section_1b4 - _CAN1TXDSR1 1B5 1 1 0 .abs_section_1b5 - _CAN1TXDSR2 1B6 1 1 0 .abs_section_1b6 - _CAN1TXDSR3 1B7 1 1 0 .abs_section_1b7 - _CAN1TXDSR4 1B8 1 1 0 .abs_section_1b8 - _CAN1TXDSR5 1B9 1 1 0 .abs_section_1b9 - _CAN1TXDSR6 1BA 1 1 0 .abs_section_1ba - _CAN1TXDSR7 1BB 1 1 0 .abs_section_1bb - _CAN1TXERR 18F 1 1 0 .abs_section_18f - _CAN1TXIDR0 1B0 1 1 0 .abs_section_1b0 - _CAN1TXIDR1 1B1 1 1 0 .abs_section_1b1 - _CAN1TXIDR2 1B2 1 1 0 .abs_section_1b2 - _CAN1TXIDR3 1B3 1 1 0 .abs_section_1b3 - _CAN1TXTBPR 1BF 1 1 0 .abs_section_1bf - _CAN2BTR0 1C2 1 1 0 .abs_section_1c2 - _CAN2BTR1 1C3 1 1 0 .abs_section_1c3 - _CAN2CTL0 1C0 1 1 0 .abs_section_1c0 - _CAN2CTL1 1C1 1 1 0 .abs_section_1c1 - _CAN2IDAC 1CB 1 1 0 .abs_section_1cb - _CAN2IDAR0 1D0 1 1 0 .abs_section_1d0 - _CAN2IDAR1 1D1 1 1 0 .abs_section_1d1 - _CAN2IDAR2 1D2 1 1 0 .abs_section_1d2 - _CAN2IDAR3 1D3 1 1 0 .abs_section_1d3 - _CAN2IDAR4 1D8 1 1 0 .abs_section_1d8 - _CAN2IDAR5 1D9 1 1 0 .abs_section_1d9 - _CAN2IDAR6 1DA 1 1 0 .abs_section_1da - _CAN2IDAR7 1DB 1 1 0 .abs_section_1db - _CAN2IDMR0 1D4 1 1 0 .abs_section_1d4 - _CAN2IDMR1 1D5 1 1 0 .abs_section_1d5 - _CAN2IDMR2 1D6 1 1 0 .abs_section_1d6 - _CAN2IDMR3 1D7 1 1 0 .abs_section_1d7 - _CAN2IDMR4 1DC 1 1 0 .abs_section_1dc - _CAN2IDMR5 1DD 1 1 0 .abs_section_1dd - _CAN2IDMR6 1DE 1 1 0 .abs_section_1de - _CAN2IDMR7 1DF 1 1 0 .abs_section_1df - _CAN2RFLG 1C4 1 1 0 .abs_section_1c4 - _CAN2RIER 1C5 1 1 0 .abs_section_1c5 - _CAN2RXDLR 1EC 1 1 0 .abs_section_1ec - _CAN2RXDSR0 1E4 1 1 0 .abs_section_1e4 - _CAN2RXDSR1 1E5 1 1 0 .abs_section_1e5 - _CAN2RXDSR2 1E6 1 1 0 .abs_section_1e6 - _CAN2RXDSR3 1E7 1 1 0 .abs_section_1e7 - _CAN2RXDSR4 1E8 1 1 0 .abs_section_1e8 - _CAN2RXDSR5 1E9 1 1 0 .abs_section_1e9 - _CAN2RXDSR6 1EA 1 1 0 .abs_section_1ea - _CAN2RXDSR7 1EB 1 1 0 .abs_section_1eb - _CAN2RXERR 1CE 1 1 0 .abs_section_1ce - _CAN2RXIDR0 1E0 1 1 0 .abs_section_1e0 - _CAN2RXIDR1 1E1 1 1 0 .abs_section_1e1 - _CAN2RXIDR2 1E2 1 1 0 .abs_section_1e2 - _CAN2RXIDR3 1E3 1 1 0 .abs_section_1e3 - _CAN2TAAK 1C9 1 1 0 .abs_section_1c9 - _CAN2TARQ 1C8 1 1 0 .abs_section_1c8 - _CAN2TBSEL 1CA 1 1 0 .abs_section_1ca - _CAN2TFLG 1C6 1 1 0 .abs_section_1c6 - _CAN2TIER 1C7 1 1 0 .abs_section_1c7 - _CAN2TXDLR 1FC 1 1 0 .abs_section_1fc - _CAN2TXDSR0 1F4 1 1 0 .abs_section_1f4 - _CAN2TXDSR1 1F5 1 1 0 .abs_section_1f5 - _CAN2TXDSR2 1F6 1 1 0 .abs_section_1f6 - _CAN2TXDSR3 1F7 1 1 0 .abs_section_1f7 - _CAN2TXDSR4 1F8 1 1 0 .abs_section_1f8 - _CAN2TXDSR5 1F9 1 1 0 .abs_section_1f9 - _CAN2TXDSR6 1FA 1 1 0 .abs_section_1fa - _CAN2TXDSR7 1FB 1 1 0 .abs_section_1fb - _CAN2TXERR 1CF 1 1 0 .abs_section_1cf - _CAN2TXIDR0 1F0 1 1 0 .abs_section_1f0 - _CAN2TXIDR1 1F1 1 1 0 .abs_section_1f1 - _CAN2TXIDR2 1F2 1 1 0 .abs_section_1f2 - _CAN2TXIDR3 1F3 1 1 0 .abs_section_1f3 - _CAN2TXTBPR 1FF 1 1 0 .abs_section_1ff - _CAN3BTR0 202 1 1 0 .abs_section_202 - _CAN3BTR1 203 1 1 0 .abs_section_203 - _CAN3CTL0 200 1 1 0 .abs_section_200 - _CAN3CTL1 201 1 1 0 .abs_section_201 - _CAN3IDAC 20B 1 1 0 .abs_section_20b - _CAN3IDAR0 210 1 1 0 .abs_section_210 - _CAN3IDAR1 211 1 1 0 .abs_section_211 - _CAN3IDAR2 212 1 1 0 .abs_section_212 - _CAN3IDAR3 213 1 1 0 .abs_section_213 - _CAN3IDAR4 218 1 1 0 .abs_section_218 - _CAN3IDAR5 219 1 1 0 .abs_section_219 - _CAN3IDAR6 21A 1 1 0 .abs_section_21a - _CAN3IDAR7 21B 1 1 0 .abs_section_21b - _CAN3IDMR0 214 1 1 0 .abs_section_214 - _CAN3IDMR1 215 1 1 0 .abs_section_215 - _CAN3IDMR2 216 1 1 0 .abs_section_216 - _CAN3IDMR3 217 1 1 0 .abs_section_217 - _CAN3IDMR4 21C 1 1 0 .abs_section_21c - _CAN3IDMR5 21D 1 1 0 .abs_section_21d - _CAN3IDMR6 21E 1 1 0 .abs_section_21e - _CAN3IDMR7 21F 1 1 0 .abs_section_21f - _CAN3RFLG 204 1 1 0 .abs_section_204 - _CAN3RIER 205 1 1 0 .abs_section_205 - _CAN3RXDLR 22C 1 1 0 .abs_section_22c - _CAN3RXDSR0 224 1 1 0 .abs_section_224 - _CAN3RXDSR1 225 1 1 0 .abs_section_225 - _CAN3RXDSR2 226 1 1 0 .abs_section_226 - _CAN3RXDSR3 227 1 1 0 .abs_section_227 - _CAN3RXDSR4 228 1 1 0 .abs_section_228 - _CAN3RXDSR5 229 1 1 0 .abs_section_229 - _CAN3RXDSR6 22A 1 1 0 .abs_section_22a - _CAN3RXDSR7 22B 1 1 0 .abs_section_22b - _CAN3RXERR 20E 1 1 0 .abs_section_20e - _CAN3RXIDR0 220 1 1 0 .abs_section_220 - _CAN3RXIDR1 221 1 1 0 .abs_section_221 - _CAN3RXIDR2 222 1 1 0 .abs_section_222 - _CAN3RXIDR3 223 1 1 0 .abs_section_223 - _CAN3TAAK 209 1 1 0 .abs_section_209 - _CAN3TARQ 208 1 1 0 .abs_section_208 - _CAN3TBSEL 20A 1 1 0 .abs_section_20a - _CAN3TFLG 206 1 1 0 .abs_section_206 - _CAN3TIER 207 1 1 0 .abs_section_207 - _CAN3TXDLR 23C 1 1 0 .abs_section_23c - _CAN3TXDSR0 234 1 1 0 .abs_section_234 - _CAN3TXDSR1 235 1 1 0 .abs_section_235 - _CAN3TXDSR2 236 1 1 0 .abs_section_236 - _CAN3TXDSR3 237 1 1 0 .abs_section_237 - _CAN3TXDSR4 238 1 1 0 .abs_section_238 - _CAN3TXDSR5 239 1 1 0 .abs_section_239 - _CAN3TXDSR6 23A 1 1 0 .abs_section_23a - _CAN3TXDSR7 23B 1 1 0 .abs_section_23b - _CAN3TXERR 20F 1 1 0 .abs_section_20f - _CAN3TXIDR0 230 1 1 0 .abs_section_230 - _CAN3TXIDR1 231 1 1 0 .abs_section_231 - _CAN3TXIDR2 232 1 1 0 .abs_section_232 - _CAN3TXIDR3 233 1 1 0 .abs_section_233 - _CAN3TXTBPR 23F 1 1 0 .abs_section_23f - _CAN4BTR0 282 1 1 0 .abs_section_282 - _CAN4BTR1 283 1 1 0 .abs_section_283 - _CAN4CTL0 280 1 1 0 .abs_section_280 - _CAN4CTL1 281 1 1 0 .abs_section_281 - _CAN4IDAC 28B 1 1 0 .abs_section_28b - _CAN4IDAR0 290 1 1 0 .abs_section_290 - _CAN4IDAR1 291 1 1 0 .abs_section_291 - _CAN4IDAR2 292 1 1 0 .abs_section_292 - _CAN4IDAR3 293 1 1 0 .abs_section_293 - _CAN4IDAR4 298 1 1 0 .abs_section_298 - _CAN4IDAR5 299 1 1 0 .abs_section_299 - _CAN4IDAR6 29A 1 1 0 .abs_section_29a - _CAN4IDAR7 29B 1 1 0 .abs_section_29b - _CAN4IDMR0 294 1 1 0 .abs_section_294 - _CAN4IDMR1 295 1 1 0 .abs_section_295 - _CAN4IDMR2 296 1 1 0 .abs_section_296 - _CAN4IDMR3 297 1 1 0 .abs_section_297 - _CAN4IDMR4 29C 1 1 0 .abs_section_29c - _CAN4IDMR5 29D 1 1 0 .abs_section_29d - _CAN4IDMR6 29E 1 1 0 .abs_section_29e - _CAN4IDMR7 29F 1 1 0 .abs_section_29f - _CAN4RFLG 284 1 1 0 .abs_section_284 - _CAN4RIER 285 1 1 0 .abs_section_285 - _CAN4RXDLR 2AC 1 1 0 .abs_section_2ac - _CAN4RXDSR0 2A4 1 1 0 .abs_section_2a4 - _CAN4RXDSR1 2A5 1 1 0 .abs_section_2a5 - _CAN4RXDSR2 2A6 1 1 0 .abs_section_2a6 - _CAN4RXDSR3 2A7 1 1 0 .abs_section_2a7 - _CAN4RXDSR4 2A8 1 1 0 .abs_section_2a8 - _CAN4RXDSR5 2A9 1 1 0 .abs_section_2a9 - _CAN4RXDSR6 2AA 1 1 0 .abs_section_2aa - _CAN4RXDSR7 2AB 1 1 0 .abs_section_2ab - _CAN4RXERR 28E 1 1 0 .abs_section_28e - _CAN4RXIDR0 2A0 1 1 0 .abs_section_2a0 - _CAN4RXIDR1 2A1 1 1 0 .abs_section_2a1 - _CAN4RXIDR2 2A2 1 1 0 .abs_section_2a2 - _CAN4RXIDR3 2A3 1 1 0 .abs_section_2a3 - _CAN4TAAK 289 1 1 0 .abs_section_289 - _CAN4TARQ 288 1 1 0 .abs_section_288 - _CAN4TBSEL 28A 1 1 0 .abs_section_28a - _CAN4TFLG 286 1 1 0 .abs_section_286 - _CAN4TIER 287 1 1 0 .abs_section_287 - _CAN4TXDLR 2BC 1 1 0 .abs_section_2bc - _CAN4TXDSR0 2B4 1 1 0 .abs_section_2b4 - _CAN4TXDSR1 2B5 1 1 0 .abs_section_2b5 - _CAN4TXDSR2 2B6 1 1 0 .abs_section_2b6 - _CAN4TXDSR3 2B7 1 1 0 .abs_section_2b7 - _CAN4TXDSR4 2B8 1 1 0 .abs_section_2b8 - _CAN4TXDSR5 2B9 1 1 0 .abs_section_2b9 - _CAN4TXDSR6 2BA 1 1 0 .abs_section_2ba - _CAN4TXDSR7 2BB 1 1 0 .abs_section_2bb - _CAN4TXERR 28F 1 1 0 .abs_section_28f - _CAN4TXIDR0 2B0 1 1 0 .abs_section_2b0 - _CAN4TXIDR1 2B1 1 1 0 .abs_section_2b1 - _CAN4TXIDR2 2B2 1 1 0 .abs_section_2b2 - _CAN4TXIDR3 2B3 1 1 0 .abs_section_2b3 - _CAN4TXTBPR 2BF 1 1 0 .abs_section_2bf - _CFORC 41 1 1 0 .abs_section_41 - _CLKSEL 39 1 1 3 .abs_section_39 - _COPCTL 3C 1 1 0 .abs_section_3c - _CRGFLG 37 1 1 1 .abs_section_37 - _CRGINT 38 1 1 0 .abs_section_38 - _CTCTL 3E 1 1 0 .abs_section_3e - _CTFLG 36 1 1 0 .abs_section_36 - _DDRE 9 1 1 0 .abs_section_9 - _DDRH 262 1 1 0 .abs_section_262 - _DDRJ 26A 1 1 0 .abs_section_26a - _DDRK 33 1 1 0 .abs_section_33 - _DDRM 252 1 1 0 .abs_section_252 - _DDRP 25A 1 1 0 .abs_section_25a - _DDRS 24A 1 1 2 .abs_section_24a - _DDRT 242 1 1 0 .abs_section_242 - _DLCBARD EC 1 1 0 .abs_section_ec - _DLCBCR1 E8 1 1 0 .abs_section_e8 - _DLCBCR2 EA 1 1 0 .abs_section_ea - _DLCBDR EB 1 1 0 .abs_section_eb - _DLCBRSR ED 1 1 0 .abs_section_ed - _DLCBSVR E9 1 1 0 .abs_section_e9 - _DLCSCR EE 1 1 0 .abs_section_ee - _DLYCT 69 1 1 0 .abs_section_69 - _EBICTL E 1 1 0 .abs_section_e - _ECLKDIV 110 1 1 0 .abs_section_110 - _ECMD 116 1 1 0 .abs_section_116 - _ECNFG 113 1 1 0 .abs_section_113 - _EPROT 114 1 1 0 .abs_section_114 - _ESTAT 115 1 1 0 .abs_section_115 - _FCLKDIV 100 1 1 0 .abs_section_100 - _FCMD 106 1 1 0 .abs_section_106 - _FCNFG 103 1 1 0 .abs_section_103 - _FORBYP 3D 1 1 0 .abs_section_3d - _FPROT 104 1 1 0 .abs_section_104 - _FSEC 101 1 1 0 .abs_section_101 - _FSTAT 105 1 1 0 .abs_section_105 - _HPRIO 1F 1 1 0 .abs_section_1f - _IBAD E0 1 1 0 .abs_section_e0 - _IBCR E2 1 1 0 .abs_section_e2 - _IBDR E4 1 1 0 .abs_section_e4 - _IBFD E1 1 1 0 .abs_section_e1 - _IBSR E3 1 1 0 .abs_section_e3 - _ICOVW 6A 1 1 0 .abs_section_6a - _ICPAR 68 1 1 0 .abs_section_68 - _ICSYS 6B 1 1 1 .abs_section_6b - _INITEE 12 1 1 1 .abs_section_12 - _INITRG 11 1 1 0 .abs_section_11 - _INITRM 10 1 1 1 .abs_section_10 - _INTCR 1E 1 1 1 .abs_section_1e - _ITCR 15 1 1 0 .abs_section_15 - _ITEST 16 1 1 0 .abs_section_16 - _MCCTL 66 1 1 1 .abs_section_66 - _MCFLG 67 1 1 0 .abs_section_67 - _MEMSIZ0 1C 1 1 0 .abs_section_1c - _MEMSIZ1 1D 1 1 0 .abs_section_1d - _MISC 13 1 1 1 .abs_section_13 - _MODE B 1 1 0 .abs_section_b - _MODRR 257 1 1 0 .abs_section_257 - _MTST0 14 1 1 0 .abs_section_14 - _MTST1 17 1 1 0 .abs_section_17 - _OC7D 43 1 1 0 .abs_section_43 - _OC7M 42 1 1 0 .abs_section_42 - _PACTL 60 1 1 0 .abs_section_60 - _PAFLG 61 1 1 0 .abs_section_61 - _PARTIDH 1A 1 1 0 .abs_section_1a - _PARTIDL 1B 1 1 0 .abs_section_1b - _PBCTL 70 1 1 0 .abs_section_70 - _PBFLG 71 1 1 0 .abs_section_71 - _PEAR A 1 1 0 .abs_section_a - _PERH 264 1 1 0 .abs_section_264 - _PERJ 26C 1 1 0 .abs_section_26c - _PERM 254 1 1 0 .abs_section_254 - _PERP 25C 1 1 0 .abs_section_25c - _PERS 24C 1 1 0 .abs_section_24c - _PERT 244 1 1 0 .abs_section_244 - _PIEH 266 1 1 0 .abs_section_266 - _PIEJ 26E 1 1 0 .abs_section_26e - _PIEP 25E 1 1 0 .abs_section_25e - _PIFH 267 1 1 0 .abs_section_267 - _PIFJ 26F 1 1 0 .abs_section_26f - _PIFP 25F 1 1 0 .abs_section_25f - _PLLCTL 3A 1 1 3 .abs_section_3a - _PORTAD0 8F 1 1 0 .abs_section_8f - _PORTAD1 12F 1 1 0 .abs_section_12f - _PORTE 8 1 1 0 .abs_section_8 - _PORTK 32 1 1 0 .abs_section_32 - _PPAGE 30 1 1 0 .abs_section_30 - _PPSH 265 1 1 0 .abs_section_265 - _PPSJ 26D 1 1 0 .abs_section_26d - _PPSM 255 1 1 0 .abs_section_255 - _PPSP 25D 1 1 0 .abs_section_25d - _PPSS 24D 1 1 0 .abs_section_24d - _PPST 245 1 1 0 .abs_section_245 - _PTH 260 1 1 0 .abs_section_260 - _PTIH 261 1 1 0 .abs_section_261 - _PTIJ 269 1 1 0 .abs_section_269 - _PTIM 251 1 1 0 .abs_section_251 - _PTIP 259 1 1 0 .abs_section_259 - _PTIS 249 1 1 0 .abs_section_249 - _PTIT 241 1 1 0 .abs_section_241 - _PTJ 268 1 1 0 .abs_section_268 - _PTM 250 1 1 0 .abs_section_250 - _PTP 258 1 1 0 .abs_section_258 - _PTS 248 1 1 1 .abs_section_248 - _PTT 240 1 1 0 .abs_section_240 - _PUCR C 1 1 0 .abs_section_c - _PWMCAE A4 1 1 0 .abs_section_a4 - _PWMCLK A2 1 1 0 .abs_section_a2 - _PWMCTL A5 1 1 1 .abs_section_a5 - _PWME A0 1 1 0 .abs_section_a0 - _PWMPOL A1 1 1 0 .abs_section_a1 - _PWMPRCLK A3 1 1 0 .abs_section_a3 - _PWMSCLA A8 1 1 0 .abs_section_a8 - _PWMSCLB A9 1 1 0 .abs_section_a9 - _PWMSDN C4 1 1 1 .abs_section_c4 - _RDRH 263 1 1 0 .abs_section_263 - _RDRIV D 1 1 0 .abs_section_d - _RDRJ 26B 1 1 0 .abs_section_26b - _RDRM 253 1 1 0 .abs_section_253 - _RDRP 25B 1 1 0 .abs_section_25b - _RDRS 24B 1 1 0 .abs_section_24b - _RDRT 243 1 1 0 .abs_section_243 - _REFDV 35 1 1 1 .abs_section_35 - _RTICTL 3B 1 1 0 .abs_section_3b - _SCI0CR1 CA 1 1 1 .abs_section_ca - _SCI0CR2 CB 1 1 7 .abs_section_cb - _SCI0DRH CE 1 1 0 .abs_section_ce - _SCI0DRL CF 1 1 3 .abs_section_cf - _SCI0SR1 CC 1 1 2 .abs_section_cc - _SCI0SR2 CD 1 1 1 .abs_section_cd - _SCI1CR1 D2 1 1 0 .abs_section_d2 - _SCI1CR2 D3 1 1 0 .abs_section_d3 - _SCI1DRH D6 1 1 0 .abs_section_d6 - _SCI1DRL D7 1 1 0 .abs_section_d7 - _SCI1SR1 D4 1 1 0 .abs_section_d4 - _SCI1SR2 D5 1 1 0 .abs_section_d5 - _SPI0BR DA 1 1 0 .abs_section_da - _SPI0CR1 D8 1 1 0 .abs_section_d8 - _SPI0CR2 D9 1 1 0 .abs_section_d9 - _SPI0DR DD 1 1 0 .abs_section_dd - _SPI0SR DB 1 1 0 .abs_section_db - _SPI1BR F2 1 1 0 .abs_section_f2 - _SPI1CR1 F0 1 1 0 .abs_section_f0 - _SPI1CR2 F1 1 1 0 .abs_section_f1 - _SPI1DR F5 1 1 0 .abs_section_f5 - _SPI1SR F3 1 1 0 .abs_section_f3 - _SPI2BR FA 1 1 0 .abs_section_fa - _SPI2CR1 F8 1 1 0 .abs_section_f8 - _SPI2CR2 F9 1 1 0 .abs_section_f9 - _SPI2DR FD 1 1 0 .abs_section_fd - _SPI2SR FB 1 1 0 .abs_section_fb - _SYNR 34 1 1 1 .abs_section_34 - _TCTL1 48 1 1 1 .abs_section_48 - _TCTL2 49 1 1 1 .abs_section_49 - _TCTL3 4A 1 1 0 .abs_section_4a - _TCTL4 4B 1 1 0 .abs_section_4b - _TFLG1 4E 1 1 2 .abs_section_4e - _TFLG2 4F 1 1 0 .abs_section_4f - _TIE 4C 1 1 2 .abs_section_4c - _TIMTST 6D 1 1 0 .abs_section_6d - _TIOS 40 1 1 1 .abs_section_40 - _TSCR1 46 1 1 3 .abs_section_46 - _TSCR2 4D 1 1 5 .abs_section_4d - _TTOV 47 1 1 1 .abs_section_47 - _WOMM 256 1 1 0 .abs_section_256 - _WOMS 24E 1 1 0 .abs_section_24e - _ATD0CTL23 82 2 2 0 .abs_section_82 - _ATD0CTL45 84 2 2 0 .abs_section_84 - _ATD0DR0 90 2 2 0 .abs_section_90 - _ATD0DR1 92 2 2 0 .abs_section_92 - _ATD0DR2 94 2 2 0 .abs_section_94 - _ATD0DR3 96 2 2 0 .abs_section_96 - _ATD0DR4 98 2 2 0 .abs_section_98 - _ATD0DR5 9A 2 2 0 .abs_section_9a - _ATD0DR6 9C 2 2 0 .abs_section_9c - _ATD0DR7 9E 2 2 0 .abs_section_9e - _ATD1CTL23 122 2 2 0 .abs_section_122 - _ATD1CTL45 124 2 2 0 .abs_section_124 - _ATD1DR0 130 2 2 0 .abs_section_130 - _ATD1DR1 132 2 2 0 .abs_section_132 - _ATD1DR2 134 2 2 0 .abs_section_134 - _ATD1DR3 136 2 2 0 .abs_section_136 - _ATD1DR4 138 2 2 0 .abs_section_138 - _ATD1DR5 13A 2 2 0 .abs_section_13a - _ATD1DR6 13C 2 2 0 .abs_section_13c - _ATD1DR7 13E 2 2 0 .abs_section_13e - _DDRAB 2 2 2 1 .abs_section_2 - _MCCNT 76 2 2 0 .abs_section_76 - _PA10H 74 2 2 0 .abs_section_74 - _PA32H 72 2 2 0 .abs_section_72 - _PACN10 64 2 2 0 .abs_section_64 - _PACN32 62 2 2 0 .abs_section_62 - _PORTAB 0 2 2 6 .abs_section_0 - _PWMCNT01 AC 2 2 0 .abs_section_ac - _PWMCNT23 AE 2 2 0 .abs_section_ae - _PWMCNT45 B0 2 2 0 .abs_section_b0 - _PWMCNT67 B2 2 2 0 .abs_section_b2 - _PWMDTY01 BC 2 2 0 .abs_section_bc - _PWMDTY23 BE 2 2 0 .abs_section_be - _PWMDTY45 C0 2 2 0 .abs_section_c0 - _PWMDTY67 C2 2 2 0 .abs_section_c2 - _PWMPER01 B4 2 2 0 .abs_section_b4 - _PWMPER23 B6 2 2 0 .abs_section_b6 - _PWMPER45 B8 2 2 0 .abs_section_b8 - _PWMPER67 BA 2 2 0 .abs_section_ba - _SCI0BD C8 2 2 2 .abs_section_c8 - _SCI1BD D0 2 2 0 .abs_section_d0 - _TC0 50 2 2 1 .abs_section_50 - _TC0H 78 2 2 0 .abs_section_78 - _TC1 52 2 2 0 .abs_section_52 - _TC1H 7A 2 2 0 .abs_section_7a - _TC2 54 2 2 0 .abs_section_54 - _TC2H 7C 2 2 0 .abs_section_7c - _TC3 56 2 2 0 .abs_section_56 - _TC3H 7E 2 2 0 .abs_section_7e - _TC4 58 2 2 0 .abs_section_58 - _TC5 5A 2 2 0 .abs_section_5a - _TC6 5C 2 2 0 .abs_section_5c - _TC7 5E 2 2 1 .abs_section_5e - _TCNT 44 2 2 0 .abs_section_44 -MODULE: -- Vectors.c.o -- -- PROCEDURES: -- VARIABLES: - _vect FF80 80 128 0 .abs_section_ff80 -MODULE: -- RTOSDemo.C.o -- -- PROCEDURES: - main 30809A 9 9 0 .text -- VARIABLES: -MODULE: -- main.c.o -- -- PROCEDURES: - vMain 3080A3 52 82 1 .text - vErrorChecks 3080F5 33 51 3 .text - prvCheckOtherTasksAreStillRunning 308128 49 73 2 .text - vApplicationIdleHook 308171 70 112 2 .text -- VARIABLES: - STRING.Check.1 C09A 6 6 1 .rodata1 - xLocalError 1001 1 1 2 .bss -MODULE: -- ParTest.c.o -- -- PROCEDURES: - vParTestSetLED 3081E1 22 34 4 .text - vParTestToggleLED 308203 14 20 10 .text -- VARIABLES: -MODULE: -- serial.c.o -- -- PROCEDURES: - xSerialPortInitMinimal 308217 24 36 2 .text - xSerialGetChar 30823B 17 23 2 .text - xSerialPutChar 318000 1D 29 2 ROM_PAGE31_524 - vCOM0_ISR C300 59 89 1 NON_BANKED -- VARIABLES: - xRxedChars 1002 2 2 3 .bss - xCharsForTx 1004 2 2 3 .bss -MODULE: -- tasks.c.o -- -- PROCEDURES: - xTaskCreate 31801D D9 217 48 ROM_PAGE31_524 - vTaskDelete 3180F6 4A 74 4 ROM_PAGE31_524 - vTaskDelayUntil 318140 78 120 6 ROM_PAGE31_524 - vTaskDelay 3181B8 4A 74 16 ROM_PAGE31_524 - uxTaskPriorityGet 318202 26 38 2 ROM_PAGE31_524 - vTaskPrioritySet 328000 6B 107 4 ROM_PAGE32_525 - vTaskSuspend 32806B 47 71 6 ROM_PAGE32_525 - vTaskResume 3280B2 5B 91 6 ROM_PAGE32_525 - vTaskStartScheduler 32810D 35 53 2 ROM_PAGE32_525 - vTaskSuspendAll 328142 13 19 26 ROM_PAGE32_525 - xTaskResumeAll 328155 A5 165 30 ROM_PAGE32_525 - xTaskGetTickCount 3281FA 17 23 6 ROM_PAGE32_525 - uxTaskGetNumberOfTasks 328211 17 23 4 ROM_PAGE32_525 - vTaskIncrementTick 338000 84 132 4 ROM_PAGE33_526 - vTaskSwitchContext 338084 5B 91 4 ROM_PAGE33_526 - vTaskPlaceOnEventList 3380DF 44 68 4 ROM_PAGE33_526 - xTaskRemoveFromEventList 338123 6F 111 8 ROM_PAGE33_526 - prvIdleTask 338192 12 18 3 ROM_PAGE33_526 - prvInitialiseTCBVariables 3381A4 4F 79 2 ROM_PAGE33_526 - prvInitialiseTaskLists 3381F3 41 65 2 ROM_PAGE33_526 - prvCheckTasksWaitingTermination 348000 55 85 2 ROM_PAGE34_527 - prvAllocateTCBAndStack 348055 37 55 2 ROM_PAGE34_527 - prvDeleteTCB 34808C 11 17 2 ROM_PAGE34_527 -- VARIABLES: - STRING.IDLE.2 C0A0 5 5 1 .rodata1 - pxCurrentTCB 1006 2 2 28 .bss - uxTasksDeleted 1008 1 1 3 .bss - uxCurrentNumberOfTasks 1009 1 1 5 .bss - xTickCount 100A 2 2 14 .bss - uxTopUsedPriority 100C 1 1 2 .bss - uxTopReadyPriority 100D 1 1 15 .bss - xSchedulerRunning 100E 1 1 3 .bss - uxSchedulerSuspended 100F 1 1 6 .bss - uxMissedTicks 1010 1 1 4 .bss - uxTaskNumber.1 1011 1 1 2 .bss - pxReadyTasksLists 1012 3C 60 11 .bss - xDelayedTaskList1 104E F 15 2 .bss - xDelayedTaskList2 105D F 15 2 .bss - pxDelayedTaskList 106C 2 2 8 .bss - pxOverflowDelayedTaskList 106E 2 2 6 .bss - xPendingReadyList 1070 F 15 4 .bss - xTasksWaitingTermination 107F F 15 5 .bss - xSuspendedTaskList 108E F 15 2 .bss -MODULE: -- queue.c.o -- -- PROCEDURES: - xQueueCreate 34809D 7C 124 14 ROM_PAGE34_527 - xQueueSend 348119 D4 212 9 ROM_PAGE34_527 - xQueueSendFromISR 3481ED 56 86 2 ROM_PAGE34_527 - xQueueReceive 358000 CE 206 9 ROM_PAGE35_528 - xQueueReceiveFromISR 3580CE 60 96 2 ROM_PAGE35_528 - uxQueueMessagesWaiting 35812E 1B 27 2 ROM_PAGE35_528 - prvUnlockQueue 358149 71 113 8 ROM_PAGE35_528 - prvIsQueueEmpty 3581BA 21 33 2 ROM_PAGE35_528 - prvIsQueueFull 3581DB 24 36 2 ROM_PAGE35_528 -- VARIABLES: -MODULE: -- list.c.o -- -- PROCEDURES: - vListInitialise 3581FF 20 32 6 ROM_PAGE35_528 - vListInitialiseItem 35821F 7 7 6 ROM_PAGE35_528 - vListInsertEnd 358226 27 39 16 ROM_PAGE35_528 - vListInsert 368000 5A 90 8 ROM_PAGE36_529 - vListRemove 36805A 23 35 32 ROM_PAGE36_529 -- VARIABLES: -MODULE: -- heap_2.c.o -- -- PROCEDURES: - pvPortMalloc 36807D B6 182 14 ROM_PAGE36_529 - vPortFree 368133 34 52 10 ROM_PAGE36_529 -- VARIABLES: - xHeapHasBeenInitialised.1 109D 1 1 2 .bss - xHeap 109E 2804 10244 2 .bss - xStart 38A2 4 4 6 .bss - xEnd 38A6 4 4 4 .bss -MODULE: -- TickTimer.C.o -- -- PROCEDURES: - SetCV 3B811C F 15 4 TickTimer_CODE - SetPV 3B812B C 12 2 TickTimer_CODE - HWEnDi 3B8137 8 8 4 TickTimer_CODE - TickTimer_Enable 3B813F 6 6 2 TickTimer_CODE - TickTimer_SetFreqHz 3B8145 51 81 2 TickTimer_CODE - TickTimer_Init 3B8196 15 21 2 TickTimer_CODE -- VARIABLES: - CmpHighVal 38F2 2 2 2 TickTimer_DATA -MODULE: -- PE_Timer.C.o -- -- PROCEDURES: - PE_Timer_LngHi1 368167 43 67 2 ROM_PAGE36_529 -- VARIABLES: -MODULE: -- Byte1.C.o -- -- PROCEDURES: - Byte1_GetMsk 3B81AB D 13 4 Byte1_CODE - Byte1_PutBit 3B81B8 1F 31 2 Byte1_CODE - Byte1_NegBit 3B81D7 11 17 2 Byte1_CODE -- VARIABLES: - Byte1_Table 38F4 8 8 1 Byte1_DATA -MODULE: -- flash.c.o -- -- PROCEDURES: - vStartLEDFlashTasks 3681AA 2A 42 2 ROM_PAGE36_529 - vLEDFlashTask 3681D4 57 87 3 ROM_PAGE36_529 -- VARIABLES: - STRING.LEDx.1 C0A5 5 5 1 .rodata1 - uxFlashTaskNumber 38AA 1 1 2 .bss -MODULE: -- dynamic.c.o -- -- PROCEDURES: - vStartDynamicPriorityTasks 378000 9B 155 2 ROM_PAGE37_530 - vLimitedIncrementTask 37809B 22 34 3 ROM_PAGE37_530 - vContinuousIncrementTask 3780BD 33 51 3 ROM_PAGE37_530 - vCounterControlTask 3780F0 A0 160 5 ROM_PAGE37_530 - vQueueSendWhenSuspendedTask 378190 38 56 3 ROM_PAGE37_530 - vQueueReceiveWhenSuspendedTask 3781C8 53 83 3 ROM_PAGE37_530 - xAreDynamicPriorityTasksStillRunning 37821B 27 39 2 ROM_PAGE37_530 -- VARIABLES: - STRING.CNT_INC.1 C0AA 8 8 1 .rodata1 - STRING.LIM_INC.2 C0B2 8 8 1 .rodata1 - STRING.C_CTRL.3 C0BA 7 7 1 .rodata1 - STRING.SUSP_TX.4 C0C1 8 8 1 .rodata1 - STRING.SUSP_RX.5 C0C9 8 8 1 .rodata1 - usCheckVariable 38AB 2 2 4 .bss - xSuspendedQueueSendError 38AD 1 1 2 .bss - xSuspendedQueueReceiveError 38AE 1 1 3 .bss - ulValueToSend.6 38AF 4 4 5 .bss - ulExpectedValue.7 38B3 4 4 6 .bss - usLastTaskCheck.9 38B7 2 2 2 .bss - xContinousIncrementHandle 38B9 2 2 5 .bss - xLimitedIncrementHandle 38BB 2 2 2 .bss - ulCounter 38BD 4 4 10 .bss - ulReceivedValue.8 38C1 4 4 3 .bss - xSuspendedTestQueue 38EC 2 2 3 .common -MODULE: -- PollQ.c.o -- -- PROCEDURES: - vStartPolledQueueTasks 388000 49 73 2 ROM_PAGE38_531 - vPolledQueueProducer 388049 4F 79 3 ROM_PAGE38_531 - vPolledQueueConsumer 388098 5C 92 3 ROM_PAGE38_531 - xArePollingQueuesStillRunning 3880F4 1D 29 2 ROM_PAGE38_531 -- VARIABLES: - STRING.QConsNB.2 C0D1 8 8 1 .rodata1 - STRING.QProdNB.3 C0D9 8 8 1 .rodata1 - xPollingConsumerCount 38C5 1 1 3 .bss - xPollingProducerCount 38C6 1 1 3 .bss - xPolledQueue.1 38C7 2 2 3 .bss -MODULE: -- comtest.c.o -- -- PROCEDURES: - vAltStartComTestTasks 388111 4D 77 2 ROM_PAGE38_531 - vComTxTask 38815E 51 81 3 ROM_PAGE38_531 - vComRxTask 3881AF 6A 106 3 ROM_PAGE38_531 - xAreComTestTasksStillRunning 388219 15 21 2 ROM_PAGE38_531 -- VARIABLES: - STRING.COMTx.1 C0E1 6 6 1 .rodata1 - STRING.COMRx.2 C0E7 6 6 1 .rodata1 - xPort 38C9 2 2 2 .bss - uxBaseLED 38CB 1 1 5 .bss - uxRxLoops 38CC 1 1 3 .bss -MODULE: -- COM0.C.o -- -- PROCEDURES: - HWEnDi 3B81E8 A 10 2 COM0_CODE - COM0_SetBaudRateMode 3B81F2 19 25 2 COM0_CODE - COM0_Init 3B820B 20 32 2 COM0_CODE -- VARIABLES: - COM0_PrescHigh.1 38FC 8 8 1 COM0_DATA - SerFlag 3904 2 2 1 COM0_DATA - PrescHigh 3906 2 2 2 COM0_DATA - NumMode 3908 1 1 2 COM0_DATA -MODULE: -- port.c.o -- -- PROCEDURES: - pxPortInitialiseStack 398000 31 49 2 ROM_PAGE39_532 - prvSetupTimerInterrupt 398031 C 12 2 ROM_PAGE39_532 - xPortStartScheduler 39803D 4 4 2 ROM_PAGE39_532 - xBankedStartScheduler C359 13 19 1 NON_BANKED - vPortYield C36C 1D 29 1 NON_BANKED - vPortTickInterrupt C389 25 37 1 NON_BANKED -- VARIABLES: - uxCriticalNesting 1000 1 1 101 .data -MODULE: -- integer.c.o -- -- PROCEDURES: - vStartIntegerMathTasks 398041 33 51 2 ROM_PAGE39_532 - vCompeteingIntMathTask 398074 87 135 3 ROM_PAGE39_532 - xAreIntegerMathsTaskStillRunning 3980FB 25 37 2 ROM_PAGE39_532 -- VARIABLES: - STRING.IntMath.1 C0ED 8 8 1 .rodata1 - xTaskCheck 38CD 1 1 3 .bss -MODULE: -- BlockQ.c.o -- -- PROCEDURES: - vStartBlockingQueueTasks 3A8000 143 323 7 ROM_PAGE3A_533 - vBlockingQueueProducer 3A8143 3A 58 9 ROM_PAGE3A_533 - vBlockingQueueConsumer 3A817D 45 69 9 ROM_PAGE3A_533 - xAreBlockingQueuesStillRunning 3A81C2 49 73 2 ROM_PAGE3A_533 -- VARIABLES: - STRING.QConsB1.1 C0F5 8 8 1 .rodata1 - STRING.QProdB2.2 C0FD 8 8 1 .rodata1 - STRING.QProdB3.3 C105 8 8 1 .rodata1 - STRING.QConsB4.4 C10D 8 8 1 .rodata1 - STRING.QProdB5.5 C115 8 8 1 .rodata1 - STRING.QConsB6.6 C11D 8 8 1 .rodata1 - sBlockingConsumerCount 38CE 6 6 5 .bss - sBlockingProducerCount 38D4 6 6 5 .bss - sLastBlockingConsumerCount.7 38DA 6 6 2 .bss - sLastBlockingProducerCount.8 38E0 6 6 2 .bss -MODULE: -- death.c.o -- -- PROCEDURES: - vCreateSuicidalTasks 3A820B 33 51 2 ROM_PAGE3A_533 - vSuicidalTask 3B8000 52 82 12 ROM_PAGE3B_534 - vCreateTasks 3B8052 94 148 4 ROM_PAGE3B_534 - xIsCreateTaskStillRunning 3B80E6 36 54 2 ROM_PAGE3B_534 -- VARIABLES: - STRING.CREATOR.1 C125 8 8 1 .rodata1 - STRING.SUICIDE1.2 C12D 9 9 1 .rodata1 - STRING.SUICIDE2.3 C136 9 9 1 .rodata1 - STRING.SUICIDE1.4 C13F 9 9 1 .rodata1 - STRING.SUICIDE2.5 C148 9 9 1 .rodata1 - usCreationCount 38E6 2 2 4 .bss - uxTasksRunningAtStart 38E8 1 1 4 .bss - usLastCreationCount.6 38E9 2 2 2 .bss - uxTasksRunningNow.7 38EB 1 1 1 .bss - xCreatedTask1 38EE 2 2 2 .common - xCreatedTask2 38F0 2 2 2 .common - -********************************************************************************************* -MODULE STATISTIC - Name Data Code Const ---------------------------------------------------------------------------------------------- - Start12.c.o 0 59 0 - STRING.C.o (ansibi.lib) 0 113 0 - rtshc12.c.o (ansibi.lib) 0 412 0 - Cpu.C.o 0 125 0 - IO_Map.C.o 577 0 0 - Vectors.c.o 0 0 128 - RTOSDemo.C.o 0 9 0 - main.c.o 1 318 6 - ParTest.c.o 0 54 0 - serial.c.o 4 177 0 - tasks.c.o 151 1796 5 - queue.c.o 0 933 0 - list.c.o 0 203 0 - heap_2.c.o 10253 234 0 - TickTimer.C.o 2 143 0 - PE_Timer.C.o 0 67 0 - Byte1.C.o 8 61 0 - flash.c.o 1 129 5 - dynamic.c.o 28 578 39 - PollQ.c.o 4 273 16 - comtest.c.o 4 285 12 - COM0.C.o 13 67 0 - port.c.o 1 150 0 - integer.c.o 1 223 8 - BlockQ.c.o 24 523 48 - death.c.o 10 335 44 - other 128 30 27 - -********************************************************************************************* -SECTION USE IN OBJECT-ALLOCATION SECTION ---------------------------------------------------------------------------------------------- -SECTION: ".text" - Init memcpy memset strncpy main vMain vErrorChecks - prvCheckOtherTasksAreStillRunning vApplicationIdleHook vParTestSetLED - vParTestToggleLED xSerialPortInitMinimal xSerialGetChar -SECTION: ".data" - uxCriticalNesting -SECTION: ".bss" - xLocalError xRxedChars xCharsForTx pxCurrentTCB uxTasksDeleted - uxCurrentNumberOfTasks xTickCount uxTopUsedPriority uxTopReadyPriority - xSchedulerRunning uxSchedulerSuspended uxMissedTicks uxTaskNumber.1 - pxReadyTasksLists xDelayedTaskList1 xDelayedTaskList2 pxDelayedTaskList - pxOverflowDelayedTaskList xPendingReadyList xTasksWaitingTermination - xSuspendedTaskList xHeapHasBeenInitialised.1 xHeap xStart xEnd - uxFlashTaskNumber usCheckVariable xSuspendedQueueSendError - xSuspendedQueueReceiveError ulValueToSend.6 ulExpectedValue.7 - usLastTaskCheck.9 xContinousIncrementHandle xLimitedIncrementHandle ulCounter - ulReceivedValue.8 xPollingConsumerCount xPollingProducerCount xPolledQueue.1 - xPort uxBaseLED uxRxLoops xTaskCheck sBlockingConsumerCount - sBlockingProducerCount sLastBlockingConsumerCount.7 - sLastBlockingProducerCount.8 usCreationCount uxTasksRunningAtStart - usLastCreationCount.6 uxTasksRunningNow.7 -SECTION: ".init" - _EntryPoint PE_low_level_init -SECTION: ".rodata1" - STRING.Check.1 STRING.IDLE.2 STRING.LEDx.1 STRING.CNT_INC.1 STRING.LIM_INC.2 - STRING.C_CTRL.3 STRING.SUSP_TX.4 STRING.SUSP_RX.5 STRING.QConsNB.2 - STRING.QProdNB.3 STRING.COMTx.1 STRING.COMRx.2 STRING.IntMath.1 - STRING.QConsB1.1 STRING.QProdB2.2 STRING.QProdB3.3 STRING.QConsB4.4 - STRING.QProdB5.5 STRING.QConsB6.6 STRING.CREATOR.1 STRING.SUICIDE1.2 - STRING.SUICIDE2.3 STRING.SUICIDE1.4 STRING.SUICIDE2.5 -SECTION: "NON_BANKED" - _Startup _LCMP _LCMP_P _LNEG _LINC _LMUL _lDivMod _LDIVU _NEG_P _LDIVS - Cpu_Interrupt vCOM0_ISR xBankedStartScheduler vPortYield vPortTickInterrupt -SECTION: ".common" - xSuspendedTestQueue xCreatedTask1 xCreatedTask2 -SECTION: "TickTimer_CODE" - SetCV SetPV HWEnDi TickTimer_Enable TickTimer_SetFreqHz TickTimer_Init -SECTION: "Byte1_CODE" - Byte1_GetMsk Byte1_PutBit Byte1_NegBit -SECTION: "COM0_CODE" - HWEnDi COM0_SetBaudRateMode COM0_Init -SECTION: ".abs_section_3f" - _ARMCOP -SECTION: ".abs_section_8d" - _ATD0DIEN -SECTION: ".abs_section_86" - _ATD0STAT0 -SECTION: ".abs_section_8b" - _ATD0STAT1 -SECTION: ".abs_section_12d" - _ATD1DIEN -SECTION: ".abs_section_126" - _ATD1STAT0 -SECTION: ".abs_section_12b" - _ATD1STAT1 -SECTION: ".abs_section_ff06" - _BDMCCR -SECTION: ".abs_section_ff07" - _BDMINR -SECTION: ".abs_section_ff01" - _BDMSTS -SECTION: ".abs_section_2b" - _BKP0H -SECTION: ".abs_section_2c" - _BKP0L -SECTION: ".abs_section_2a" - _BKP0X -SECTION: ".abs_section_2e" - _BKP1H -SECTION: ".abs_section_2f" - _BKP1L -SECTION: ".abs_section_2d" - _BKP1X -SECTION: ".abs_section_28" - _BKPCT0 -SECTION: ".abs_section_29" - _BKPCT1 -SECTION: ".abs_section_142" - _CAN0BTR0 -SECTION: ".abs_section_143" - _CAN0BTR1 -SECTION: ".abs_section_140" - _CAN0CTL0 -SECTION: ".abs_section_141" - _CAN0CTL1 -SECTION: ".abs_section_14b" - _CAN0IDAC -SECTION: ".abs_section_150" - _CAN0IDAR0 -SECTION: ".abs_section_151" - _CAN0IDAR1 -SECTION: ".abs_section_152" - _CAN0IDAR2 -SECTION: ".abs_section_153" - _CAN0IDAR3 -SECTION: ".abs_section_158" - _CAN0IDAR4 -SECTION: ".abs_section_159" - _CAN0IDAR5 -SECTION: ".abs_section_15a" - _CAN0IDAR6 -SECTION: ".abs_section_15b" - _CAN0IDAR7 -SECTION: ".abs_section_154" - _CAN0IDMR0 -SECTION: ".abs_section_155" - _CAN0IDMR1 -SECTION: ".abs_section_156" - _CAN0IDMR2 -SECTION: ".abs_section_157" - _CAN0IDMR3 -SECTION: ".abs_section_15c" - _CAN0IDMR4 -SECTION: ".abs_section_15d" - _CAN0IDMR5 -SECTION: ".abs_section_15e" - _CAN0IDMR6 -SECTION: ".abs_section_15f" - _CAN0IDMR7 -SECTION: ".abs_section_144" - _CAN0RFLG -SECTION: ".abs_section_145" - _CAN0RIER -SECTION: ".abs_section_16c" - _CAN0RXDLR -SECTION: ".abs_section_164" - _CAN0RXDSR0 -SECTION: ".abs_section_165" - _CAN0RXDSR1 -SECTION: ".abs_section_166" - _CAN0RXDSR2 -SECTION: ".abs_section_167" - _CAN0RXDSR3 -SECTION: ".abs_section_168" - _CAN0RXDSR4 -SECTION: ".abs_section_169" - _CAN0RXDSR5 -SECTION: ".abs_section_16a" - _CAN0RXDSR6 -SECTION: ".abs_section_16b" - _CAN0RXDSR7 -SECTION: ".abs_section_14e" - _CAN0RXERR -SECTION: ".abs_section_160" - _CAN0RXIDR0 -SECTION: ".abs_section_161" - _CAN0RXIDR1 -SECTION: ".abs_section_162" - _CAN0RXIDR2 -SECTION: ".abs_section_163" - _CAN0RXIDR3 -SECTION: ".abs_section_149" - _CAN0TAAK -SECTION: ".abs_section_148" - _CAN0TARQ -SECTION: ".abs_section_14a" - _CAN0TBSEL -SECTION: ".abs_section_146" - _CAN0TFLG -SECTION: ".abs_section_147" - _CAN0TIER -SECTION: ".abs_section_17c" - _CAN0TXDLR -SECTION: ".abs_section_174" - _CAN0TXDSR0 -SECTION: ".abs_section_175" - _CAN0TXDSR1 -SECTION: ".abs_section_176" - _CAN0TXDSR2 -SECTION: ".abs_section_177" - _CAN0TXDSR3 -SECTION: ".abs_section_178" - _CAN0TXDSR4 -SECTION: ".abs_section_179" - _CAN0TXDSR5 -SECTION: ".abs_section_17a" - _CAN0TXDSR6 -SECTION: ".abs_section_17b" - _CAN0TXDSR7 -SECTION: ".abs_section_14f" - _CAN0TXERR -SECTION: ".abs_section_170" - _CAN0TXIDR0 -SECTION: ".abs_section_171" - _CAN0TXIDR1 -SECTION: ".abs_section_172" - _CAN0TXIDR2 -SECTION: ".abs_section_173" - _CAN0TXIDR3 -SECTION: ".abs_section_17f" - _CAN0TXTBPR -SECTION: ".abs_section_182" - _CAN1BTR0 -SECTION: ".abs_section_183" - _CAN1BTR1 -SECTION: ".abs_section_180" - _CAN1CTL0 -SECTION: ".abs_section_181" - _CAN1CTL1 -SECTION: ".abs_section_18b" - _CAN1IDAC -SECTION: ".abs_section_190" - _CAN1IDAR0 -SECTION: ".abs_section_191" - _CAN1IDAR1 -SECTION: ".abs_section_192" - _CAN1IDAR2 -SECTION: ".abs_section_193" - _CAN1IDAR3 -SECTION: ".abs_section_198" - _CAN1IDAR4 -SECTION: ".abs_section_199" - _CAN1IDAR5 -SECTION: ".abs_section_19a" - _CAN1IDAR6 -SECTION: ".abs_section_19b" - _CAN1IDAR7 -SECTION: ".abs_section_194" - _CAN1IDMR0 -SECTION: ".abs_section_195" - _CAN1IDMR1 -SECTION: ".abs_section_196" - _CAN1IDMR2 -SECTION: ".abs_section_197" - _CAN1IDMR3 -SECTION: ".abs_section_19c" - _CAN1IDMR4 -SECTION: ".abs_section_19d" - _CAN1IDMR5 -SECTION: ".abs_section_19e" - _CAN1IDMR6 -SECTION: ".abs_section_19f" - _CAN1IDMR7 -SECTION: ".abs_section_184" - _CAN1RFLG -SECTION: ".abs_section_185" - _CAN1RIER -SECTION: ".abs_section_1ac" - _CAN1RXDLR -SECTION: ".abs_section_1a4" - _CAN1RXDSR0 -SECTION: ".abs_section_1a5" - _CAN1RXDSR1 -SECTION: ".abs_section_1a6" - _CAN1RXDSR2 -SECTION: ".abs_section_1a7" - _CAN1RXDSR3 -SECTION: ".abs_section_1a8" - _CAN1RXDSR4 -SECTION: ".abs_section_1a9" - _CAN1RXDSR5 -SECTION: ".abs_section_1aa" - _CAN1RXDSR6 -SECTION: ".abs_section_1ab" - _CAN1RXDSR7 -SECTION: ".abs_section_18e" - _CAN1RXERR -SECTION: ".abs_section_1a0" - _CAN1RXIDR0 -SECTION: ".abs_section_1a1" - _CAN1RXIDR1 -SECTION: ".abs_section_1a2" - _CAN1RXIDR2 -SECTION: ".abs_section_1a3" - _CAN1RXIDR3 -SECTION: ".abs_section_189" - _CAN1TAAK -SECTION: ".abs_section_188" - _CAN1TARQ -SECTION: ".abs_section_18a" - _CAN1TBSEL -SECTION: ".abs_section_186" - _CAN1TFLG -SECTION: ".abs_section_187" - _CAN1TIER -SECTION: ".abs_section_1bc" - _CAN1TXDLR -SECTION: ".abs_section_1b4" - _CAN1TXDSR0 -SECTION: ".abs_section_1b5" - _CAN1TXDSR1 -SECTION: ".abs_section_1b6" - _CAN1TXDSR2 -SECTION: ".abs_section_1b7" - _CAN1TXDSR3 -SECTION: ".abs_section_1b8" - _CAN1TXDSR4 -SECTION: ".abs_section_1b9" - _CAN1TXDSR5 -SECTION: ".abs_section_1ba" - _CAN1TXDSR6 -SECTION: ".abs_section_1bb" - _CAN1TXDSR7 -SECTION: ".abs_section_18f" - _CAN1TXERR -SECTION: ".abs_section_1b0" - _CAN1TXIDR0 -SECTION: ".abs_section_1b1" - _CAN1TXIDR1 -SECTION: ".abs_section_1b2" - _CAN1TXIDR2 -SECTION: ".abs_section_1b3" - _CAN1TXIDR3 -SECTION: ".abs_section_1bf" - _CAN1TXTBPR -SECTION: ".abs_section_1c2" - _CAN2BTR0 -SECTION: ".abs_section_1c3" - _CAN2BTR1 -SECTION: ".abs_section_1c0" - _CAN2CTL0 -SECTION: ".abs_section_1c1" - _CAN2CTL1 -SECTION: ".abs_section_1cb" - _CAN2IDAC -SECTION: ".abs_section_1d0" - _CAN2IDAR0 -SECTION: ".abs_section_1d1" - _CAN2IDAR1 -SECTION: ".abs_section_1d2" - _CAN2IDAR2 -SECTION: ".abs_section_1d3" - _CAN2IDAR3 -SECTION: ".abs_section_1d8" - _CAN2IDAR4 -SECTION: ".abs_section_1d9" - _CAN2IDAR5 -SECTION: ".abs_section_1da" - _CAN2IDAR6 -SECTION: ".abs_section_1db" - _CAN2IDAR7 -SECTION: ".abs_section_1d4" - _CAN2IDMR0 -SECTION: ".abs_section_1d5" - _CAN2IDMR1 -SECTION: ".abs_section_1d6" - _CAN2IDMR2 -SECTION: ".abs_section_1d7" - _CAN2IDMR3 -SECTION: ".abs_section_1dc" - _CAN2IDMR4 -SECTION: ".abs_section_1dd" - _CAN2IDMR5 -SECTION: ".abs_section_1de" - _CAN2IDMR6 -SECTION: ".abs_section_1df" - _CAN2IDMR7 -SECTION: ".abs_section_1c4" - _CAN2RFLG -SECTION: ".abs_section_1c5" - _CAN2RIER -SECTION: ".abs_section_1ec" - _CAN2RXDLR -SECTION: ".abs_section_1e4" - _CAN2RXDSR0 -SECTION: ".abs_section_1e5" - _CAN2RXDSR1 -SECTION: ".abs_section_1e6" - _CAN2RXDSR2 -SECTION: ".abs_section_1e7" - _CAN2RXDSR3 -SECTION: ".abs_section_1e8" - _CAN2RXDSR4 -SECTION: ".abs_section_1e9" - _CAN2RXDSR5 -SECTION: ".abs_section_1ea" - _CAN2RXDSR6 -SECTION: ".abs_section_1eb" - _CAN2RXDSR7 -SECTION: ".abs_section_1ce" - _CAN2RXERR -SECTION: ".abs_section_1e0" - _CAN2RXIDR0 -SECTION: ".abs_section_1e1" - _CAN2RXIDR1 -SECTION: ".abs_section_1e2" - _CAN2RXIDR2 -SECTION: ".abs_section_1e3" - _CAN2RXIDR3 -SECTION: ".abs_section_1c9" - _CAN2TAAK -SECTION: ".abs_section_1c8" - _CAN2TARQ -SECTION: ".abs_section_1ca" - _CAN2TBSEL -SECTION: ".abs_section_1c6" - _CAN2TFLG -SECTION: ".abs_section_1c7" - _CAN2TIER -SECTION: ".abs_section_1fc" - _CAN2TXDLR -SECTION: ".abs_section_1f4" - _CAN2TXDSR0 -SECTION: ".abs_section_1f5" - _CAN2TXDSR1 -SECTION: ".abs_section_1f6" - _CAN2TXDSR2 -SECTION: ".abs_section_1f7" - _CAN2TXDSR3 -SECTION: ".abs_section_1f8" - _CAN2TXDSR4 -SECTION: ".abs_section_1f9" - _CAN2TXDSR5 -SECTION: ".abs_section_1fa" - _CAN2TXDSR6 -SECTION: ".abs_section_1fb" - _CAN2TXDSR7 -SECTION: ".abs_section_1cf" - _CAN2TXERR -SECTION: ".abs_section_1f0" - _CAN2TXIDR0 -SECTION: ".abs_section_1f1" - _CAN2TXIDR1 -SECTION: ".abs_section_1f2" - _CAN2TXIDR2 -SECTION: ".abs_section_1f3" - _CAN2TXIDR3 -SECTION: ".abs_section_1ff" - _CAN2TXTBPR -SECTION: ".abs_section_202" - _CAN3BTR0 -SECTION: ".abs_section_203" - _CAN3BTR1 -SECTION: ".abs_section_200" - _CAN3CTL0 -SECTION: ".abs_section_201" - _CAN3CTL1 -SECTION: ".abs_section_20b" - _CAN3IDAC -SECTION: ".abs_section_210" - _CAN3IDAR0 -SECTION: ".abs_section_211" - _CAN3IDAR1 -SECTION: ".abs_section_212" - _CAN3IDAR2 -SECTION: ".abs_section_213" - _CAN3IDAR3 -SECTION: ".abs_section_218" - _CAN3IDAR4 -SECTION: ".abs_section_219" - _CAN3IDAR5 -SECTION: ".abs_section_21a" - _CAN3IDAR6 -SECTION: ".abs_section_21b" - _CAN3IDAR7 -SECTION: ".abs_section_214" - _CAN3IDMR0 -SECTION: ".abs_section_215" - _CAN3IDMR1 -SECTION: ".abs_section_216" - _CAN3IDMR2 -SECTION: ".abs_section_217" - _CAN3IDMR3 -SECTION: ".abs_section_21c" - _CAN3IDMR4 -SECTION: ".abs_section_21d" - _CAN3IDMR5 -SECTION: ".abs_section_21e" - _CAN3IDMR6 -SECTION: ".abs_section_21f" - _CAN3IDMR7 -SECTION: ".abs_section_204" - _CAN3RFLG -SECTION: ".abs_section_205" - _CAN3RIER -SECTION: ".abs_section_22c" - _CAN3RXDLR -SECTION: ".abs_section_224" - _CAN3RXDSR0 -SECTION: ".abs_section_225" - _CAN3RXDSR1 -SECTION: ".abs_section_226" - _CAN3RXDSR2 -SECTION: ".abs_section_227" - _CAN3RXDSR3 -SECTION: ".abs_section_228" - _CAN3RXDSR4 -SECTION: ".abs_section_229" - _CAN3RXDSR5 -SECTION: ".abs_section_22a" - _CAN3RXDSR6 -SECTION: ".abs_section_22b" - _CAN3RXDSR7 -SECTION: ".abs_section_20e" - _CAN3RXERR -SECTION: ".abs_section_220" - _CAN3RXIDR0 -SECTION: ".abs_section_221" - _CAN3RXIDR1 -SECTION: ".abs_section_222" - _CAN3RXIDR2 -SECTION: ".abs_section_223" - _CAN3RXIDR3 -SECTION: ".abs_section_209" - _CAN3TAAK -SECTION: ".abs_section_208" - _CAN3TARQ -SECTION: ".abs_section_20a" - _CAN3TBSEL -SECTION: ".abs_section_206" - _CAN3TFLG -SECTION: ".abs_section_207" - _CAN3TIER -SECTION: ".abs_section_23c" - _CAN3TXDLR -SECTION: ".abs_section_234" - _CAN3TXDSR0 -SECTION: ".abs_section_235" - _CAN3TXDSR1 -SECTION: ".abs_section_236" - _CAN3TXDSR2 -SECTION: ".abs_section_237" - _CAN3TXDSR3 -SECTION: ".abs_section_238" - _CAN3TXDSR4 -SECTION: ".abs_section_239" - _CAN3TXDSR5 -SECTION: ".abs_section_23a" - _CAN3TXDSR6 -SECTION: ".abs_section_23b" - _CAN3TXDSR7 -SECTION: ".abs_section_20f" - _CAN3TXERR -SECTION: ".abs_section_230" - _CAN3TXIDR0 -SECTION: ".abs_section_231" - _CAN3TXIDR1 -SECTION: ".abs_section_232" - _CAN3TXIDR2 -SECTION: ".abs_section_233" - _CAN3TXIDR3 -SECTION: ".abs_section_23f" - _CAN3TXTBPR -SECTION: ".abs_section_282" - _CAN4BTR0 -SECTION: ".abs_section_283" - _CAN4BTR1 -SECTION: ".abs_section_280" - _CAN4CTL0 -SECTION: ".abs_section_281" - _CAN4CTL1 -SECTION: ".abs_section_28b" - _CAN4IDAC -SECTION: ".abs_section_290" - _CAN4IDAR0 -SECTION: ".abs_section_291" - _CAN4IDAR1 -SECTION: ".abs_section_292" - _CAN4IDAR2 -SECTION: ".abs_section_293" - _CAN4IDAR3 -SECTION: ".abs_section_298" - _CAN4IDAR4 -SECTION: ".abs_section_299" - _CAN4IDAR5 -SECTION: ".abs_section_29a" - _CAN4IDAR6 -SECTION: ".abs_section_29b" - _CAN4IDAR7 -SECTION: ".abs_section_294" - _CAN4IDMR0 -SECTION: ".abs_section_295" - _CAN4IDMR1 -SECTION: ".abs_section_296" - _CAN4IDMR2 -SECTION: ".abs_section_297" - _CAN4IDMR3 -SECTION: ".abs_section_29c" - _CAN4IDMR4 -SECTION: ".abs_section_29d" - _CAN4IDMR5 -SECTION: ".abs_section_29e" - _CAN4IDMR6 -SECTION: ".abs_section_29f" - _CAN4IDMR7 -SECTION: ".abs_section_284" - _CAN4RFLG -SECTION: ".abs_section_285" - _CAN4RIER -SECTION: ".abs_section_2ac" - _CAN4RXDLR -SECTION: ".abs_section_2a4" - _CAN4RXDSR0 -SECTION: ".abs_section_2a5" - _CAN4RXDSR1 -SECTION: ".abs_section_2a6" - _CAN4RXDSR2 -SECTION: ".abs_section_2a7" - _CAN4RXDSR3 -SECTION: ".abs_section_2a8" - _CAN4RXDSR4 -SECTION: ".abs_section_2a9" - _CAN4RXDSR5 -SECTION: ".abs_section_2aa" - _CAN4RXDSR6 -SECTION: ".abs_section_2ab" - _CAN4RXDSR7 -SECTION: ".abs_section_28e" - _CAN4RXERR -SECTION: ".abs_section_2a0" - _CAN4RXIDR0 -SECTION: ".abs_section_2a1" - _CAN4RXIDR1 -SECTION: ".abs_section_2a2" - _CAN4RXIDR2 -SECTION: ".abs_section_2a3" - _CAN4RXIDR3 -SECTION: ".abs_section_289" - _CAN4TAAK -SECTION: ".abs_section_288" - _CAN4TARQ -SECTION: ".abs_section_28a" - _CAN4TBSEL -SECTION: ".abs_section_286" - _CAN4TFLG -SECTION: ".abs_section_287" - _CAN4TIER -SECTION: ".abs_section_2bc" - _CAN4TXDLR -SECTION: ".abs_section_2b4" - _CAN4TXDSR0 -SECTION: ".abs_section_2b5" - _CAN4TXDSR1 -SECTION: ".abs_section_2b6" - _CAN4TXDSR2 -SECTION: ".abs_section_2b7" - _CAN4TXDSR3 -SECTION: ".abs_section_2b8" - _CAN4TXDSR4 -SECTION: ".abs_section_2b9" - _CAN4TXDSR5 -SECTION: ".abs_section_2ba" - _CAN4TXDSR6 -SECTION: ".abs_section_2bb" - _CAN4TXDSR7 -SECTION: ".abs_section_28f" - _CAN4TXERR -SECTION: ".abs_section_2b0" - _CAN4TXIDR0 -SECTION: ".abs_section_2b1" - _CAN4TXIDR1 -SECTION: ".abs_section_2b2" - _CAN4TXIDR2 -SECTION: ".abs_section_2b3" - _CAN4TXIDR3 -SECTION: ".abs_section_2bf" - _CAN4TXTBPR -SECTION: ".abs_section_41" - _CFORC -SECTION: ".abs_section_39" - _CLKSEL -SECTION: ".abs_section_3c" - _COPCTL -SECTION: ".abs_section_37" - _CRGFLG -SECTION: ".abs_section_38" - _CRGINT -SECTION: ".abs_section_3e" - _CTCTL -SECTION: ".abs_section_36" - _CTFLG -SECTION: ".abs_section_9" - _DDRE -SECTION: ".abs_section_262" - _DDRH -SECTION: ".abs_section_26a" - _DDRJ -SECTION: ".abs_section_33" - _DDRK -SECTION: ".abs_section_252" - _DDRM -SECTION: ".abs_section_25a" - _DDRP -SECTION: ".abs_section_24a" - _DDRS -SECTION: ".abs_section_242" - _DDRT -SECTION: ".abs_section_ec" - _DLCBARD -SECTION: ".abs_section_e8" - _DLCBCR1 -SECTION: ".abs_section_ea" - _DLCBCR2 -SECTION: ".abs_section_eb" - _DLCBDR -SECTION: ".abs_section_ed" - _DLCBRSR -SECTION: ".abs_section_e9" - _DLCBSVR -SECTION: ".abs_section_ee" - _DLCSCR -SECTION: ".abs_section_69" - _DLYCT -SECTION: ".abs_section_e" - _EBICTL -SECTION: ".abs_section_110" - _ECLKDIV -SECTION: ".abs_section_116" - _ECMD -SECTION: ".abs_section_113" - _ECNFG -SECTION: ".abs_section_114" - _EPROT -SECTION: ".abs_section_115" - _ESTAT -SECTION: ".abs_section_100" - _FCLKDIV -SECTION: ".abs_section_106" - _FCMD -SECTION: ".abs_section_103" - _FCNFG -SECTION: ".abs_section_3d" - _FORBYP -SECTION: ".abs_section_104" - _FPROT -SECTION: ".abs_section_101" - _FSEC -SECTION: ".abs_section_105" - _FSTAT -SECTION: ".abs_section_1f" - _HPRIO -SECTION: ".abs_section_e0" - _IBAD -SECTION: ".abs_section_e2" - _IBCR -SECTION: ".abs_section_e4" - _IBDR -SECTION: ".abs_section_e1" - _IBFD -SECTION: ".abs_section_e3" - _IBSR -SECTION: ".abs_section_6a" - _ICOVW -SECTION: ".abs_section_68" - _ICPAR -SECTION: ".abs_section_6b" - _ICSYS -SECTION: ".abs_section_12" - _INITEE -SECTION: ".abs_section_11" - _INITRG -SECTION: ".abs_section_10" - _INITRM -SECTION: ".abs_section_1e" - _INTCR -SECTION: ".abs_section_15" - _ITCR -SECTION: ".abs_section_16" - _ITEST -SECTION: ".abs_section_66" - _MCCTL -SECTION: ".abs_section_67" - _MCFLG -SECTION: ".abs_section_1c" - _MEMSIZ0 -SECTION: ".abs_section_1d" - _MEMSIZ1 -SECTION: ".abs_section_13" - _MISC -SECTION: ".abs_section_b" - _MODE -SECTION: ".abs_section_257" - _MODRR -SECTION: ".abs_section_14" - _MTST0 -SECTION: ".abs_section_17" - _MTST1 -SECTION: ".abs_section_43" - _OC7D -SECTION: ".abs_section_42" - _OC7M -SECTION: ".abs_section_60" - _PACTL -SECTION: ".abs_section_61" - _PAFLG -SECTION: ".abs_section_1a" - _PARTIDH -SECTION: ".abs_section_1b" - _PARTIDL -SECTION: ".abs_section_70" - _PBCTL -SECTION: ".abs_section_71" - _PBFLG -SECTION: ".abs_section_a" - _PEAR -SECTION: ".abs_section_264" - _PERH -SECTION: ".abs_section_26c" - _PERJ -SECTION: ".abs_section_254" - _PERM -SECTION: ".abs_section_25c" - _PERP -SECTION: ".abs_section_24c" - _PERS -SECTION: ".abs_section_244" - _PERT -SECTION: ".abs_section_266" - _PIEH -SECTION: ".abs_section_26e" - _PIEJ -SECTION: ".abs_section_25e" - _PIEP -SECTION: ".abs_section_267" - _PIFH -SECTION: ".abs_section_26f" - _PIFJ -SECTION: ".abs_section_25f" - _PIFP -SECTION: ".abs_section_3a" - _PLLCTL -SECTION: ".abs_section_8f" - _PORTAD0 -SECTION: ".abs_section_12f" - _PORTAD1 -SECTION: ".abs_section_8" - _PORTE -SECTION: ".abs_section_32" - _PORTK -SECTION: ".abs_section_30" - _PPAGE -SECTION: ".abs_section_265" - _PPSH -SECTION: ".abs_section_26d" - _PPSJ -SECTION: ".abs_section_255" - _PPSM -SECTION: ".abs_section_25d" - _PPSP -SECTION: ".abs_section_24d" - _PPSS -SECTION: ".abs_section_245" - _PPST -SECTION: ".abs_section_260" - _PTH -SECTION: ".abs_section_261" - _PTIH -SECTION: ".abs_section_269" - _PTIJ -SECTION: ".abs_section_251" - _PTIM -SECTION: ".abs_section_259" - _PTIP -SECTION: ".abs_section_249" - _PTIS -SECTION: ".abs_section_241" - _PTIT -SECTION: ".abs_section_268" - _PTJ -SECTION: ".abs_section_250" - _PTM -SECTION: ".abs_section_258" - _PTP -SECTION: ".abs_section_248" - _PTS -SECTION: ".abs_section_240" - _PTT -SECTION: ".abs_section_c" - _PUCR -SECTION: ".abs_section_a4" - _PWMCAE -SECTION: ".abs_section_a2" - _PWMCLK -SECTION: ".abs_section_a5" - _PWMCTL -SECTION: ".abs_section_a0" - _PWME -SECTION: ".abs_section_a1" - _PWMPOL -SECTION: ".abs_section_a3" - _PWMPRCLK -SECTION: ".abs_section_a8" - _PWMSCLA -SECTION: ".abs_section_a9" - _PWMSCLB -SECTION: ".abs_section_c4" - _PWMSDN -SECTION: ".abs_section_263" - _RDRH -SECTION: ".abs_section_d" - _RDRIV -SECTION: ".abs_section_26b" - _RDRJ -SECTION: ".abs_section_253" - _RDRM -SECTION: ".abs_section_25b" - _RDRP -SECTION: ".abs_section_24b" - _RDRS -SECTION: ".abs_section_243" - _RDRT -SECTION: ".abs_section_35" - _REFDV -SECTION: ".abs_section_3b" - _RTICTL -SECTION: ".abs_section_ca" - _SCI0CR1 -SECTION: ".abs_section_cb" - _SCI0CR2 -SECTION: ".abs_section_ce" - _SCI0DRH -SECTION: ".abs_section_cf" - _SCI0DRL -SECTION: ".abs_section_cc" - _SCI0SR1 -SECTION: ".abs_section_cd" - _SCI0SR2 -SECTION: ".abs_section_d2" - _SCI1CR1 -SECTION: ".abs_section_d3" - _SCI1CR2 -SECTION: ".abs_section_d6" - _SCI1DRH -SECTION: ".abs_section_d7" - _SCI1DRL -SECTION: ".abs_section_d4" - _SCI1SR1 -SECTION: ".abs_section_d5" - _SCI1SR2 -SECTION: ".abs_section_da" - _SPI0BR -SECTION: ".abs_section_d8" - _SPI0CR1 -SECTION: ".abs_section_d9" - _SPI0CR2 -SECTION: ".abs_section_dd" - _SPI0DR -SECTION: ".abs_section_db" - _SPI0SR -SECTION: ".abs_section_f2" - _SPI1BR -SECTION: ".abs_section_f0" - _SPI1CR1 -SECTION: ".abs_section_f1" - _SPI1CR2 -SECTION: ".abs_section_f5" - _SPI1DR -SECTION: ".abs_section_f3" - _SPI1SR -SECTION: ".abs_section_fa" - _SPI2BR -SECTION: ".abs_section_f8" - _SPI2CR1 -SECTION: ".abs_section_f9" - _SPI2CR2 -SECTION: ".abs_section_fd" - _SPI2DR -SECTION: ".abs_section_fb" - _SPI2SR -SECTION: ".abs_section_34" - _SYNR -SECTION: ".abs_section_48" - _TCTL1 -SECTION: ".abs_section_49" - _TCTL2 -SECTION: ".abs_section_4a" - _TCTL3 -SECTION: ".abs_section_4b" - _TCTL4 -SECTION: ".abs_section_4e" - _TFLG1 -SECTION: ".abs_section_4f" - _TFLG2 -SECTION: ".abs_section_4c" - _TIE -SECTION: ".abs_section_6d" - _TIMTST -SECTION: ".abs_section_40" - _TIOS -SECTION: ".abs_section_46" - _TSCR1 -SECTION: ".abs_section_4d" - _TSCR2 -SECTION: ".abs_section_47" - _TTOV -SECTION: ".abs_section_256" - _WOMM -SECTION: ".abs_section_24e" - _WOMS -SECTION: ".abs_section_82" - _ATD0CTL23 -SECTION: ".abs_section_84" - _ATD0CTL45 -SECTION: ".abs_section_90" - _ATD0DR0 -SECTION: ".abs_section_92" - _ATD0DR1 -SECTION: ".abs_section_94" - _ATD0DR2 -SECTION: ".abs_section_96" - _ATD0DR3 -SECTION: ".abs_section_98" - _ATD0DR4 -SECTION: ".abs_section_9a" - _ATD0DR5 -SECTION: ".abs_section_9c" - _ATD0DR6 -SECTION: ".abs_section_9e" - _ATD0DR7 -SECTION: ".abs_section_122" - _ATD1CTL23 -SECTION: ".abs_section_124" - _ATD1CTL45 -SECTION: ".abs_section_130" - _ATD1DR0 -SECTION: ".abs_section_132" - _ATD1DR1 -SECTION: ".abs_section_134" - _ATD1DR2 -SECTION: ".abs_section_136" - _ATD1DR3 -SECTION: ".abs_section_138" - _ATD1DR4 -SECTION: ".abs_section_13a" - _ATD1DR5 -SECTION: ".abs_section_13c" - _ATD1DR6 -SECTION: ".abs_section_13e" - _ATD1DR7 -SECTION: ".abs_section_2" - _DDRAB -SECTION: ".abs_section_76" - _MCCNT -SECTION: ".abs_section_74" - _PA10H -SECTION: ".abs_section_72" - _PA32H -SECTION: ".abs_section_64" - _PACN10 -SECTION: ".abs_section_62" - _PACN32 -SECTION: ".abs_section_0" - _PORTAB -SECTION: ".abs_section_ac" - _PWMCNT01 -SECTION: ".abs_section_ae" - _PWMCNT23 -SECTION: ".abs_section_b0" - _PWMCNT45 -SECTION: ".abs_section_b2" - _PWMCNT67 -SECTION: ".abs_section_bc" - _PWMDTY01 -SECTION: ".abs_section_be" - _PWMDTY23 -SECTION: ".abs_section_c0" - _PWMDTY45 -SECTION: ".abs_section_c2" - _PWMDTY67 -SECTION: ".abs_section_b4" - _PWMPER01 -SECTION: ".abs_section_b6" - _PWMPER23 -SECTION: ".abs_section_b8" - _PWMPER45 -SECTION: ".abs_section_ba" - _PWMPER67 -SECTION: ".abs_section_c8" - _SCI0BD -SECTION: ".abs_section_d0" - _SCI1BD -SECTION: ".abs_section_50" - _TC0 -SECTION: ".abs_section_78" - _TC0H -SECTION: ".abs_section_52" - _TC1 -SECTION: ".abs_section_7a" - _TC1H -SECTION: ".abs_section_54" - _TC2 -SECTION: ".abs_section_7c" - _TC2H -SECTION: ".abs_section_56" - _TC3 -SECTION: ".abs_section_7e" - _TC3H -SECTION: ".abs_section_58" - _TC4 -SECTION: ".abs_section_5a" - _TC5 -SECTION: ".abs_section_5c" - _TC6 -SECTION: ".abs_section_5e" - _TC7 -SECTION: ".abs_section_44" - _TCNT -SECTION: ".abs_section_ff80" - _vect -SECTION: "TickTimer_DATA" - CmpHighVal -SECTION: "Byte1_DATA" - Byte1_Table -SECTION: "COM0_DATA" - COM0_PrescHigh.1 SerFlag PrescHigh NumMode -SECTION: "ROM_PAGE31_524" - xSerialPutChar xTaskCreate vTaskDelete vTaskDelayUntil vTaskDelay - uxTaskPriorityGet -SECTION: "ROM_PAGE32_525" - vTaskPrioritySet vTaskSuspend vTaskResume vTaskStartScheduler - vTaskSuspendAll xTaskResumeAll xTaskGetTickCount uxTaskGetNumberOfTasks -SECTION: "ROM_PAGE33_526" - vTaskIncrementTick vTaskSwitchContext vTaskPlaceOnEventList - xTaskRemoveFromEventList prvIdleTask prvInitialiseTCBVariables - prvInitialiseTaskLists -SECTION: "ROM_PAGE34_527" - prvCheckTasksWaitingTermination prvAllocateTCBAndStack prvDeleteTCB - xQueueCreate xQueueSend xQueueSendFromISR -SECTION: "ROM_PAGE35_528" - xQueueReceive xQueueReceiveFromISR uxQueueMessagesWaiting prvUnlockQueue - prvIsQueueEmpty prvIsQueueFull vListInitialise vListInitialiseItem - vListInsertEnd -SECTION: "ROM_PAGE36_529" - vListInsert vListRemove pvPortMalloc vPortFree PE_Timer_LngHi1 - vStartLEDFlashTasks vLEDFlashTask -SECTION: "ROM_PAGE37_530" - vStartDynamicPriorityTasks vLimitedIncrementTask vContinuousIncrementTask - vCounterControlTask vQueueSendWhenSuspendedTask - vQueueReceiveWhenSuspendedTask xAreDynamicPriorityTasksStillRunning -SECTION: "ROM_PAGE38_531" - vStartPolledQueueTasks vPolledQueueProducer vPolledQueueConsumer - xArePollingQueuesStillRunning vAltStartComTestTasks vComTxTask vComRxTask - xAreComTestTasksStillRunning -SECTION: "ROM_PAGE39_532" - pxPortInitialiseStack prvSetupTimerInterrupt xPortStartScheduler - vStartIntegerMathTasks vCompeteingIntMathTask - xAreIntegerMathsTaskStillRunning -SECTION: "ROM_PAGE3A_533" - vStartBlockingQueueTasks vBlockingQueueProducer vBlockingQueueConsumer - xAreBlockingQueuesStillRunning vCreateSuicidalTasks -SECTION: "ROM_PAGE3B_534" - vSuicidalTask vCreateTasks xIsCreateTaskStillRunning - -********************************************************************************************* -OBJECT LIST SORTED BY ADDRESS - Name Addr hSize dSize Ref Section RLIB ---------------------------------------------------------------------------------------------- - _PORTAB 0 2 2 6 .abs_section_0 - _DDRAB 2 2 2 1 .abs_section_2 - _PORTE 8 1 1 0 .abs_section_8 - _DDRE 9 1 1 0 .abs_section_9 - _PEAR A 1 1 0 .abs_section_a - _MODE B 1 1 0 .abs_section_b - _PUCR C 1 1 0 .abs_section_c - _RDRIV D 1 1 0 .abs_section_d - _EBICTL E 1 1 0 .abs_section_e - _INITRM 10 1 1 1 .abs_section_10 - _INITRG 11 1 1 0 .abs_section_11 - _INITEE 12 1 1 1 .abs_section_12 - _MISC 13 1 1 1 .abs_section_13 - _MTST0 14 1 1 0 .abs_section_14 - _ITCR 15 1 1 0 .abs_section_15 - _ITEST 16 1 1 0 .abs_section_16 - _MTST1 17 1 1 0 .abs_section_17 - _PARTIDH 1A 1 1 0 .abs_section_1a - _PARTIDL 1B 1 1 0 .abs_section_1b - _MEMSIZ0 1C 1 1 0 .abs_section_1c - _MEMSIZ1 1D 1 1 0 .abs_section_1d - _INTCR 1E 1 1 1 .abs_section_1e - _HPRIO 1F 1 1 0 .abs_section_1f - _BKPCT0 28 1 1 0 .abs_section_28 - _BKPCT1 29 1 1 0 .abs_section_29 - _BKP0X 2A 1 1 0 .abs_section_2a - _BKP0H 2B 1 1 0 .abs_section_2b - _BKP0L 2C 1 1 0 .abs_section_2c - _BKP1X 2D 1 1 0 .abs_section_2d - _BKP1H 2E 1 1 0 .abs_section_2e - _BKP1L 2F 1 1 0 .abs_section_2f - _PPAGE 30 1 1 0 .abs_section_30 - _PORTK 32 1 1 0 .abs_section_32 - _DDRK 33 1 1 0 .abs_section_33 - _SYNR 34 1 1 1 .abs_section_34 - _REFDV 35 1 1 1 .abs_section_35 - _CTFLG 36 1 1 0 .abs_section_36 - _CRGFLG 37 1 1 1 .abs_section_37 - _CRGINT 38 1 1 0 .abs_section_38 - _CLKSEL 39 1 1 3 .abs_section_39 - _PLLCTL 3A 1 1 3 .abs_section_3a - _RTICTL 3B 1 1 0 .abs_section_3b - _COPCTL 3C 1 1 0 .abs_section_3c - _FORBYP 3D 1 1 0 .abs_section_3d - _CTCTL 3E 1 1 0 .abs_section_3e - _ARMCOP 3F 1 1 0 .abs_section_3f - _TIOS 40 1 1 1 .abs_section_40 - _CFORC 41 1 1 0 .abs_section_41 - _OC7M 42 1 1 0 .abs_section_42 - _OC7D 43 1 1 0 .abs_section_43 - _TCNT 44 2 2 0 .abs_section_44 - _TSCR1 46 1 1 3 .abs_section_46 - _TTOV 47 1 1 1 .abs_section_47 - _TCTL1 48 1 1 1 .abs_section_48 - _TCTL2 49 1 1 1 .abs_section_49 - _TCTL3 4A 1 1 0 .abs_section_4a - _TCTL4 4B 1 1 0 .abs_section_4b - _TIE 4C 1 1 2 .abs_section_4c - _TSCR2 4D 1 1 5 .abs_section_4d - _TFLG1 4E 1 1 2 .abs_section_4e - _TFLG2 4F 1 1 0 .abs_section_4f - _TC0 50 2 2 1 .abs_section_50 - _TC1 52 2 2 0 .abs_section_52 - _TC2 54 2 2 0 .abs_section_54 - _TC3 56 2 2 0 .abs_section_56 - _TC4 58 2 2 0 .abs_section_58 - _TC5 5A 2 2 0 .abs_section_5a - _TC6 5C 2 2 0 .abs_section_5c - _TC7 5E 2 2 1 .abs_section_5e - _PACTL 60 1 1 0 .abs_section_60 - _PAFLG 61 1 1 0 .abs_section_61 - _PACN32 62 2 2 0 .abs_section_62 - _PACN10 64 2 2 0 .abs_section_64 - _MCCTL 66 1 1 1 .abs_section_66 - _MCFLG 67 1 1 0 .abs_section_67 - _ICPAR 68 1 1 0 .abs_section_68 - _DLYCT 69 1 1 0 .abs_section_69 - _ICOVW 6A 1 1 0 .abs_section_6a - _ICSYS 6B 1 1 1 .abs_section_6b - _TIMTST 6D 1 1 0 .abs_section_6d - _PBCTL 70 1 1 0 .abs_section_70 - _PBFLG 71 1 1 0 .abs_section_71 - _PA32H 72 2 2 0 .abs_section_72 - _PA10H 74 2 2 0 .abs_section_74 - _MCCNT 76 2 2 0 .abs_section_76 - _TC0H 78 2 2 0 .abs_section_78 - _TC1H 7A 2 2 0 .abs_section_7a - _TC2H 7C 2 2 0 .abs_section_7c - _TC3H 7E 2 2 0 .abs_section_7e - _ATD0CTL23 82 2 2 0 .abs_section_82 - _ATD0CTL45 84 2 2 0 .abs_section_84 - _ATD0STAT0 86 1 1 0 .abs_section_86 - _ATD0STAT1 8B 1 1 0 .abs_section_8b - _ATD0DIEN 8D 1 1 0 .abs_section_8d - _PORTAD0 8F 1 1 0 .abs_section_8f - _ATD0DR0 90 2 2 0 .abs_section_90 - _ATD0DR1 92 2 2 0 .abs_section_92 - _ATD0DR2 94 2 2 0 .abs_section_94 - _ATD0DR3 96 2 2 0 .abs_section_96 - _ATD0DR4 98 2 2 0 .abs_section_98 - _ATD0DR5 9A 2 2 0 .abs_section_9a - _ATD0DR6 9C 2 2 0 .abs_section_9c - _ATD0DR7 9E 2 2 0 .abs_section_9e - _PWME A0 1 1 0 .abs_section_a0 - _PWMPOL A1 1 1 0 .abs_section_a1 - _PWMCLK A2 1 1 0 .abs_section_a2 - _PWMPRCLK A3 1 1 0 .abs_section_a3 - _PWMCAE A4 1 1 0 .abs_section_a4 - _PWMCTL A5 1 1 1 .abs_section_a5 - _PWMSCLA A8 1 1 0 .abs_section_a8 - _PWMSCLB A9 1 1 0 .abs_section_a9 - _PWMCNT01 AC 2 2 0 .abs_section_ac - _PWMCNT23 AE 2 2 0 .abs_section_ae - _PWMCNT45 B0 2 2 0 .abs_section_b0 - _PWMCNT67 B2 2 2 0 .abs_section_b2 - _PWMPER01 B4 2 2 0 .abs_section_b4 - _PWMPER23 B6 2 2 0 .abs_section_b6 - _PWMPER45 B8 2 2 0 .abs_section_b8 - _PWMPER67 BA 2 2 0 .abs_section_ba - _PWMDTY01 BC 2 2 0 .abs_section_bc - _PWMDTY23 BE 2 2 0 .abs_section_be - _PWMDTY45 C0 2 2 0 .abs_section_c0 - _PWMDTY67 C2 2 2 0 .abs_section_c2 - _PWMSDN C4 1 1 1 .abs_section_c4 - _SCI0BD C8 2 2 2 .abs_section_c8 - _SCI0CR1 CA 1 1 1 .abs_section_ca - _SCI0CR2 CB 1 1 7 .abs_section_cb - _SCI0SR1 CC 1 1 2 .abs_section_cc - _SCI0SR2 CD 1 1 1 .abs_section_cd - _SCI0DRH CE 1 1 0 .abs_section_ce - _SCI0DRL CF 1 1 3 .abs_section_cf - _SCI1BD D0 2 2 0 .abs_section_d0 - _SCI1CR1 D2 1 1 0 .abs_section_d2 - _SCI1CR2 D3 1 1 0 .abs_section_d3 - _SCI1SR1 D4 1 1 0 .abs_section_d4 - _SCI1SR2 D5 1 1 0 .abs_section_d5 - _SCI1DRH D6 1 1 0 .abs_section_d6 - _SCI1DRL D7 1 1 0 .abs_section_d7 - _SPI0CR1 D8 1 1 0 .abs_section_d8 - _SPI0CR2 D9 1 1 0 .abs_section_d9 - _SPI0BR DA 1 1 0 .abs_section_da - _SPI0SR DB 1 1 0 .abs_section_db - _SPI0DR DD 1 1 0 .abs_section_dd - _IBAD E0 1 1 0 .abs_section_e0 - _IBFD E1 1 1 0 .abs_section_e1 - _IBCR E2 1 1 0 .abs_section_e2 - _IBSR E3 1 1 0 .abs_section_e3 - _IBDR E4 1 1 0 .abs_section_e4 - _DLCBCR1 E8 1 1 0 .abs_section_e8 - _DLCBSVR E9 1 1 0 .abs_section_e9 - _DLCBCR2 EA 1 1 0 .abs_section_ea - _DLCBDR EB 1 1 0 .abs_section_eb - _DLCBARD EC 1 1 0 .abs_section_ec - _DLCBRSR ED 1 1 0 .abs_section_ed - _DLCSCR EE 1 1 0 .abs_section_ee - _SPI1CR1 F0 1 1 0 .abs_section_f0 - _SPI1CR2 F1 1 1 0 .abs_section_f1 - _SPI1BR F2 1 1 0 .abs_section_f2 - _SPI1SR F3 1 1 0 .abs_section_f3 - _SPI1DR F5 1 1 0 .abs_section_f5 - _SPI2CR1 F8 1 1 0 .abs_section_f8 - _SPI2CR2 F9 1 1 0 .abs_section_f9 - _SPI2BR FA 1 1 0 .abs_section_fa - _SPI2SR FB 1 1 0 .abs_section_fb - _SPI2DR FD 1 1 0 .abs_section_fd - _FCLKDIV 100 1 1 0 .abs_section_100 - _FSEC 101 1 1 0 .abs_section_101 - _FCNFG 103 1 1 0 .abs_section_103 - _FPROT 104 1 1 0 .abs_section_104 - _FSTAT 105 1 1 0 .abs_section_105 - _FCMD 106 1 1 0 .abs_section_106 - _ECLKDIV 110 1 1 0 .abs_section_110 - _ECNFG 113 1 1 0 .abs_section_113 - _EPROT 114 1 1 0 .abs_section_114 - _ESTAT 115 1 1 0 .abs_section_115 - _ECMD 116 1 1 0 .abs_section_116 - _ATD1CTL23 122 2 2 0 .abs_section_122 - _ATD1CTL45 124 2 2 0 .abs_section_124 - _ATD1STAT0 126 1 1 0 .abs_section_126 - _ATD1STAT1 12B 1 1 0 .abs_section_12b - _ATD1DIEN 12D 1 1 0 .abs_section_12d - _PORTAD1 12F 1 1 0 .abs_section_12f - _ATD1DR0 130 2 2 0 .abs_section_130 - _ATD1DR1 132 2 2 0 .abs_section_132 - _ATD1DR2 134 2 2 0 .abs_section_134 - _ATD1DR3 136 2 2 0 .abs_section_136 - _ATD1DR4 138 2 2 0 .abs_section_138 - _ATD1DR5 13A 2 2 0 .abs_section_13a - _ATD1DR6 13C 2 2 0 .abs_section_13c - _ATD1DR7 13E 2 2 0 .abs_section_13e - _CAN0CTL0 140 1 1 0 .abs_section_140 - _CAN0CTL1 141 1 1 0 .abs_section_141 - _CAN0BTR0 142 1 1 0 .abs_section_142 - _CAN0BTR1 143 1 1 0 .abs_section_143 - _CAN0RFLG 144 1 1 0 .abs_section_144 - _CAN0RIER 145 1 1 0 .abs_section_145 - _CAN0TFLG 146 1 1 0 .abs_section_146 - _CAN0TIER 147 1 1 0 .abs_section_147 - _CAN0TARQ 148 1 1 0 .abs_section_148 - _CAN0TAAK 149 1 1 0 .abs_section_149 - _CAN0TBSEL 14A 1 1 0 .abs_section_14a - _CAN0IDAC 14B 1 1 0 .abs_section_14b - _CAN0RXERR 14E 1 1 0 .abs_section_14e - _CAN0TXERR 14F 1 1 0 .abs_section_14f - _CAN0IDAR0 150 1 1 0 .abs_section_150 - _CAN0IDAR1 151 1 1 0 .abs_section_151 - _CAN0IDAR2 152 1 1 0 .abs_section_152 - _CAN0IDAR3 153 1 1 0 .abs_section_153 - _CAN0IDMR0 154 1 1 0 .abs_section_154 - _CAN0IDMR1 155 1 1 0 .abs_section_155 - _CAN0IDMR2 156 1 1 0 .abs_section_156 - _CAN0IDMR3 157 1 1 0 .abs_section_157 - _CAN0IDAR4 158 1 1 0 .abs_section_158 - _CAN0IDAR5 159 1 1 0 .abs_section_159 - _CAN0IDAR6 15A 1 1 0 .abs_section_15a - _CAN0IDAR7 15B 1 1 0 .abs_section_15b - _CAN0IDMR4 15C 1 1 0 .abs_section_15c - _CAN0IDMR5 15D 1 1 0 .abs_section_15d - _CAN0IDMR6 15E 1 1 0 .abs_section_15e - _CAN0IDMR7 15F 1 1 0 .abs_section_15f - _CAN0RXIDR0 160 1 1 0 .abs_section_160 - _CAN0RXIDR1 161 1 1 0 .abs_section_161 - _CAN0RXIDR2 162 1 1 0 .abs_section_162 - _CAN0RXIDR3 163 1 1 0 .abs_section_163 - _CAN0RXDSR0 164 1 1 0 .abs_section_164 - _CAN0RXDSR1 165 1 1 0 .abs_section_165 - _CAN0RXDSR2 166 1 1 0 .abs_section_166 - _CAN0RXDSR3 167 1 1 0 .abs_section_167 - _CAN0RXDSR4 168 1 1 0 .abs_section_168 - _CAN0RXDSR5 169 1 1 0 .abs_section_169 - _CAN0RXDSR6 16A 1 1 0 .abs_section_16a - _CAN0RXDSR7 16B 1 1 0 .abs_section_16b - _CAN0RXDLR 16C 1 1 0 .abs_section_16c - _CAN0TXIDR0 170 1 1 0 .abs_section_170 - _CAN0TXIDR1 171 1 1 0 .abs_section_171 - _CAN0TXIDR2 172 1 1 0 .abs_section_172 - _CAN0TXIDR3 173 1 1 0 .abs_section_173 - _CAN0TXDSR0 174 1 1 0 .abs_section_174 - _CAN0TXDSR1 175 1 1 0 .abs_section_175 - _CAN0TXDSR2 176 1 1 0 .abs_section_176 - _CAN0TXDSR3 177 1 1 0 .abs_section_177 - _CAN0TXDSR4 178 1 1 0 .abs_section_178 - _CAN0TXDSR5 179 1 1 0 .abs_section_179 - _CAN0TXDSR6 17A 1 1 0 .abs_section_17a - _CAN0TXDSR7 17B 1 1 0 .abs_section_17b - _CAN0TXDLR 17C 1 1 0 .abs_section_17c - _CAN0TXTBPR 17F 1 1 0 .abs_section_17f - _CAN1CTL0 180 1 1 0 .abs_section_180 - _CAN1CTL1 181 1 1 0 .abs_section_181 - _CAN1BTR0 182 1 1 0 .abs_section_182 - _CAN1BTR1 183 1 1 0 .abs_section_183 - _CAN1RFLG 184 1 1 0 .abs_section_184 - _CAN1RIER 185 1 1 0 .abs_section_185 - _CAN1TFLG 186 1 1 0 .abs_section_186 - _CAN1TIER 187 1 1 0 .abs_section_187 - _CAN1TARQ 188 1 1 0 .abs_section_188 - _CAN1TAAK 189 1 1 0 .abs_section_189 - _CAN1TBSEL 18A 1 1 0 .abs_section_18a - _CAN1IDAC 18B 1 1 0 .abs_section_18b - _CAN1RXERR 18E 1 1 0 .abs_section_18e - _CAN1TXERR 18F 1 1 0 .abs_section_18f - _CAN1IDAR0 190 1 1 0 .abs_section_190 - _CAN1IDAR1 191 1 1 0 .abs_section_191 - _CAN1IDAR2 192 1 1 0 .abs_section_192 - _CAN1IDAR3 193 1 1 0 .abs_section_193 - _CAN1IDMR0 194 1 1 0 .abs_section_194 - _CAN1IDMR1 195 1 1 0 .abs_section_195 - _CAN1IDMR2 196 1 1 0 .abs_section_196 - _CAN1IDMR3 197 1 1 0 .abs_section_197 - _CAN1IDAR4 198 1 1 0 .abs_section_198 - _CAN1IDAR5 199 1 1 0 .abs_section_199 - _CAN1IDAR6 19A 1 1 0 .abs_section_19a - _CAN1IDAR7 19B 1 1 0 .abs_section_19b - _CAN1IDMR4 19C 1 1 0 .abs_section_19c - _CAN1IDMR5 19D 1 1 0 .abs_section_19d - _CAN1IDMR6 19E 1 1 0 .abs_section_19e - _CAN1IDMR7 19F 1 1 0 .abs_section_19f - _CAN1RXIDR0 1A0 1 1 0 .abs_section_1a0 - _CAN1RXIDR1 1A1 1 1 0 .abs_section_1a1 - _CAN1RXIDR2 1A2 1 1 0 .abs_section_1a2 - _CAN1RXIDR3 1A3 1 1 0 .abs_section_1a3 - _CAN1RXDSR0 1A4 1 1 0 .abs_section_1a4 - _CAN1RXDSR1 1A5 1 1 0 .abs_section_1a5 - _CAN1RXDSR2 1A6 1 1 0 .abs_section_1a6 - _CAN1RXDSR3 1A7 1 1 0 .abs_section_1a7 - _CAN1RXDSR4 1A8 1 1 0 .abs_section_1a8 - _CAN1RXDSR5 1A9 1 1 0 .abs_section_1a9 - _CAN1RXDSR6 1AA 1 1 0 .abs_section_1aa - _CAN1RXDSR7 1AB 1 1 0 .abs_section_1ab - _CAN1RXDLR 1AC 1 1 0 .abs_section_1ac - _CAN1TXIDR0 1B0 1 1 0 .abs_section_1b0 - _CAN1TXIDR1 1B1 1 1 0 .abs_section_1b1 - _CAN1TXIDR2 1B2 1 1 0 .abs_section_1b2 - _CAN1TXIDR3 1B3 1 1 0 .abs_section_1b3 - _CAN1TXDSR0 1B4 1 1 0 .abs_section_1b4 - _CAN1TXDSR1 1B5 1 1 0 .abs_section_1b5 - _CAN1TXDSR2 1B6 1 1 0 .abs_section_1b6 - _CAN1TXDSR3 1B7 1 1 0 .abs_section_1b7 - _CAN1TXDSR4 1B8 1 1 0 .abs_section_1b8 - _CAN1TXDSR5 1B9 1 1 0 .abs_section_1b9 - _CAN1TXDSR6 1BA 1 1 0 .abs_section_1ba - _CAN1TXDSR7 1BB 1 1 0 .abs_section_1bb - _CAN1TXDLR 1BC 1 1 0 .abs_section_1bc - _CAN1TXTBPR 1BF 1 1 0 .abs_section_1bf - _CAN2CTL0 1C0 1 1 0 .abs_section_1c0 - _CAN2CTL1 1C1 1 1 0 .abs_section_1c1 - _CAN2BTR0 1C2 1 1 0 .abs_section_1c2 - _CAN2BTR1 1C3 1 1 0 .abs_section_1c3 - _CAN2RFLG 1C4 1 1 0 .abs_section_1c4 - _CAN2RIER 1C5 1 1 0 .abs_section_1c5 - _CAN2TFLG 1C6 1 1 0 .abs_section_1c6 - _CAN2TIER 1C7 1 1 0 .abs_section_1c7 - _CAN2TARQ 1C8 1 1 0 .abs_section_1c8 - _CAN2TAAK 1C9 1 1 0 .abs_section_1c9 - _CAN2TBSEL 1CA 1 1 0 .abs_section_1ca - _CAN2IDAC 1CB 1 1 0 .abs_section_1cb - _CAN2RXERR 1CE 1 1 0 .abs_section_1ce - _CAN2TXERR 1CF 1 1 0 .abs_section_1cf - _CAN2IDAR0 1D0 1 1 0 .abs_section_1d0 - _CAN2IDAR1 1D1 1 1 0 .abs_section_1d1 - _CAN2IDAR2 1D2 1 1 0 .abs_section_1d2 - _CAN2IDAR3 1D3 1 1 0 .abs_section_1d3 - _CAN2IDMR0 1D4 1 1 0 .abs_section_1d4 - _CAN2IDMR1 1D5 1 1 0 .abs_section_1d5 - _CAN2IDMR2 1D6 1 1 0 .abs_section_1d6 - _CAN2IDMR3 1D7 1 1 0 .abs_section_1d7 - _CAN2IDAR4 1D8 1 1 0 .abs_section_1d8 - _CAN2IDAR5 1D9 1 1 0 .abs_section_1d9 - _CAN2IDAR6 1DA 1 1 0 .abs_section_1da - _CAN2IDAR7 1DB 1 1 0 .abs_section_1db - _CAN2IDMR4 1DC 1 1 0 .abs_section_1dc - _CAN2IDMR5 1DD 1 1 0 .abs_section_1dd - _CAN2IDMR6 1DE 1 1 0 .abs_section_1de - _CAN2IDMR7 1DF 1 1 0 .abs_section_1df - _CAN2RXIDR0 1E0 1 1 0 .abs_section_1e0 - _CAN2RXIDR1 1E1 1 1 0 .abs_section_1e1 - _CAN2RXIDR2 1E2 1 1 0 .abs_section_1e2 - _CAN2RXIDR3 1E3 1 1 0 .abs_section_1e3 - _CAN2RXDSR0 1E4 1 1 0 .abs_section_1e4 - _CAN2RXDSR1 1E5 1 1 0 .abs_section_1e5 - _CAN2RXDSR2 1E6 1 1 0 .abs_section_1e6 - _CAN2RXDSR3 1E7 1 1 0 .abs_section_1e7 - _CAN2RXDSR4 1E8 1 1 0 .abs_section_1e8 - _CAN2RXDSR5 1E9 1 1 0 .abs_section_1e9 - _CAN2RXDSR6 1EA 1 1 0 .abs_section_1ea - _CAN2RXDSR7 1EB 1 1 0 .abs_section_1eb - _CAN2RXDLR 1EC 1 1 0 .abs_section_1ec - _CAN2TXIDR0 1F0 1 1 0 .abs_section_1f0 - _CAN2TXIDR1 1F1 1 1 0 .abs_section_1f1 - _CAN2TXIDR2 1F2 1 1 0 .abs_section_1f2 - _CAN2TXIDR3 1F3 1 1 0 .abs_section_1f3 - _CAN2TXDSR0 1F4 1 1 0 .abs_section_1f4 - _CAN2TXDSR1 1F5 1 1 0 .abs_section_1f5 - _CAN2TXDSR2 1F6 1 1 0 .abs_section_1f6 - _CAN2TXDSR3 1F7 1 1 0 .abs_section_1f7 - _CAN2TXDSR4 1F8 1 1 0 .abs_section_1f8 - _CAN2TXDSR5 1F9 1 1 0 .abs_section_1f9 - _CAN2TXDSR6 1FA 1 1 0 .abs_section_1fa - _CAN2TXDSR7 1FB 1 1 0 .abs_section_1fb - _CAN2TXDLR 1FC 1 1 0 .abs_section_1fc - _CAN2TXTBPR 1FF 1 1 0 .abs_section_1ff - _CAN3CTL0 200 1 1 0 .abs_section_200 - _CAN3CTL1 201 1 1 0 .abs_section_201 - _CAN3BTR0 202 1 1 0 .abs_section_202 - _CAN3BTR1 203 1 1 0 .abs_section_203 - _CAN3RFLG 204 1 1 0 .abs_section_204 - _CAN3RIER 205 1 1 0 .abs_section_205 - _CAN3TFLG 206 1 1 0 .abs_section_206 - _CAN3TIER 207 1 1 0 .abs_section_207 - _CAN3TARQ 208 1 1 0 .abs_section_208 - _CAN3TAAK 209 1 1 0 .abs_section_209 - _CAN3TBSEL 20A 1 1 0 .abs_section_20a - _CAN3IDAC 20B 1 1 0 .abs_section_20b - _CAN3RXERR 20E 1 1 0 .abs_section_20e - _CAN3TXERR 20F 1 1 0 .abs_section_20f - _CAN3IDAR0 210 1 1 0 .abs_section_210 - _CAN3IDAR1 211 1 1 0 .abs_section_211 - _CAN3IDAR2 212 1 1 0 .abs_section_212 - _CAN3IDAR3 213 1 1 0 .abs_section_213 - _CAN3IDMR0 214 1 1 0 .abs_section_214 - _CAN3IDMR1 215 1 1 0 .abs_section_215 - _CAN3IDMR2 216 1 1 0 .abs_section_216 - _CAN3IDMR3 217 1 1 0 .abs_section_217 - _CAN3IDAR4 218 1 1 0 .abs_section_218 - _CAN3IDAR5 219 1 1 0 .abs_section_219 - _CAN3IDAR6 21A 1 1 0 .abs_section_21a - _CAN3IDAR7 21B 1 1 0 .abs_section_21b - _CAN3IDMR4 21C 1 1 0 .abs_section_21c - _CAN3IDMR5 21D 1 1 0 .abs_section_21d - _CAN3IDMR6 21E 1 1 0 .abs_section_21e - _CAN3IDMR7 21F 1 1 0 .abs_section_21f - _CAN3RXIDR0 220 1 1 0 .abs_section_220 - _CAN3RXIDR1 221 1 1 0 .abs_section_221 - _CAN3RXIDR2 222 1 1 0 .abs_section_222 - _CAN3RXIDR3 223 1 1 0 .abs_section_223 - _CAN3RXDSR0 224 1 1 0 .abs_section_224 - _CAN3RXDSR1 225 1 1 0 .abs_section_225 - _CAN3RXDSR2 226 1 1 0 .abs_section_226 - _CAN3RXDSR3 227 1 1 0 .abs_section_227 - _CAN3RXDSR4 228 1 1 0 .abs_section_228 - _CAN3RXDSR5 229 1 1 0 .abs_section_229 - _CAN3RXDSR6 22A 1 1 0 .abs_section_22a - _CAN3RXDSR7 22B 1 1 0 .abs_section_22b - _CAN3RXDLR 22C 1 1 0 .abs_section_22c - _CAN3TXIDR0 230 1 1 0 .abs_section_230 - _CAN3TXIDR1 231 1 1 0 .abs_section_231 - _CAN3TXIDR2 232 1 1 0 .abs_section_232 - _CAN3TXIDR3 233 1 1 0 .abs_section_233 - _CAN3TXDSR0 234 1 1 0 .abs_section_234 - _CAN3TXDSR1 235 1 1 0 .abs_section_235 - _CAN3TXDSR2 236 1 1 0 .abs_section_236 - _CAN3TXDSR3 237 1 1 0 .abs_section_237 - _CAN3TXDSR4 238 1 1 0 .abs_section_238 - _CAN3TXDSR5 239 1 1 0 .abs_section_239 - _CAN3TXDSR6 23A 1 1 0 .abs_section_23a - _CAN3TXDSR7 23B 1 1 0 .abs_section_23b - _CAN3TXDLR 23C 1 1 0 .abs_section_23c - _CAN3TXTBPR 23F 1 1 0 .abs_section_23f - _PTT 240 1 1 0 .abs_section_240 - _PTIT 241 1 1 0 .abs_section_241 - _DDRT 242 1 1 0 .abs_section_242 - _RDRT 243 1 1 0 .abs_section_243 - _PERT 244 1 1 0 .abs_section_244 - _PPST 245 1 1 0 .abs_section_245 - _PTS 248 1 1 1 .abs_section_248 - _PTIS 249 1 1 0 .abs_section_249 - _DDRS 24A 1 1 2 .abs_section_24a - _RDRS 24B 1 1 0 .abs_section_24b - _PERS 24C 1 1 0 .abs_section_24c - _PPSS 24D 1 1 0 .abs_section_24d - _WOMS 24E 1 1 0 .abs_section_24e - _PTM 250 1 1 0 .abs_section_250 - _PTIM 251 1 1 0 .abs_section_251 - _DDRM 252 1 1 0 .abs_section_252 - _RDRM 253 1 1 0 .abs_section_253 - _PERM 254 1 1 0 .abs_section_254 - _PPSM 255 1 1 0 .abs_section_255 - _WOMM 256 1 1 0 .abs_section_256 - _MODRR 257 1 1 0 .abs_section_257 - _PTP 258 1 1 0 .abs_section_258 - _PTIP 259 1 1 0 .abs_section_259 - _DDRP 25A 1 1 0 .abs_section_25a - _RDRP 25B 1 1 0 .abs_section_25b - _PERP 25C 1 1 0 .abs_section_25c - _PPSP 25D 1 1 0 .abs_section_25d - _PIEP 25E 1 1 0 .abs_section_25e - _PIFP 25F 1 1 0 .abs_section_25f - _PTH 260 1 1 0 .abs_section_260 - _PTIH 261 1 1 0 .abs_section_261 - _DDRH 262 1 1 0 .abs_section_262 - _RDRH 263 1 1 0 .abs_section_263 - _PERH 264 1 1 0 .abs_section_264 - _PPSH 265 1 1 0 .abs_section_265 - _PIEH 266 1 1 0 .abs_section_266 - _PIFH 267 1 1 0 .abs_section_267 - _PTJ 268 1 1 0 .abs_section_268 - _PTIJ 269 1 1 0 .abs_section_269 - _DDRJ 26A 1 1 0 .abs_section_26a - _RDRJ 26B 1 1 0 .abs_section_26b - _PERJ 26C 1 1 0 .abs_section_26c - _PPSJ 26D 1 1 0 .abs_section_26d - _PIEJ 26E 1 1 0 .abs_section_26e - _PIFJ 26F 1 1 0 .abs_section_26f - _CAN4CTL0 280 1 1 0 .abs_section_280 - _CAN4CTL1 281 1 1 0 .abs_section_281 - _CAN4BTR0 282 1 1 0 .abs_section_282 - _CAN4BTR1 283 1 1 0 .abs_section_283 - _CAN4RFLG 284 1 1 0 .abs_section_284 - _CAN4RIER 285 1 1 0 .abs_section_285 - _CAN4TFLG 286 1 1 0 .abs_section_286 - _CAN4TIER 287 1 1 0 .abs_section_287 - _CAN4TARQ 288 1 1 0 .abs_section_288 - _CAN4TAAK 289 1 1 0 .abs_section_289 - _CAN4TBSEL 28A 1 1 0 .abs_section_28a - _CAN4IDAC 28B 1 1 0 .abs_section_28b - _CAN4RXERR 28E 1 1 0 .abs_section_28e - _CAN4TXERR 28F 1 1 0 .abs_section_28f - _CAN4IDAR0 290 1 1 0 .abs_section_290 - _CAN4IDAR1 291 1 1 0 .abs_section_291 - _CAN4IDAR2 292 1 1 0 .abs_section_292 - _CAN4IDAR3 293 1 1 0 .abs_section_293 - _CAN4IDMR0 294 1 1 0 .abs_section_294 - _CAN4IDMR1 295 1 1 0 .abs_section_295 - _CAN4IDMR2 296 1 1 0 .abs_section_296 - _CAN4IDMR3 297 1 1 0 .abs_section_297 - _CAN4IDAR4 298 1 1 0 .abs_section_298 - _CAN4IDAR5 299 1 1 0 .abs_section_299 - _CAN4IDAR6 29A 1 1 0 .abs_section_29a - _CAN4IDAR7 29B 1 1 0 .abs_section_29b - _CAN4IDMR4 29C 1 1 0 .abs_section_29c - _CAN4IDMR5 29D 1 1 0 .abs_section_29d - _CAN4IDMR6 29E 1 1 0 .abs_section_29e - _CAN4IDMR7 29F 1 1 0 .abs_section_29f - _CAN4RXIDR0 2A0 1 1 0 .abs_section_2a0 - _CAN4RXIDR1 2A1 1 1 0 .abs_section_2a1 - _CAN4RXIDR2 2A2 1 1 0 .abs_section_2a2 - _CAN4RXIDR3 2A3 1 1 0 .abs_section_2a3 - _CAN4RXDSR0 2A4 1 1 0 .abs_section_2a4 - _CAN4RXDSR1 2A5 1 1 0 .abs_section_2a5 - _CAN4RXDSR2 2A6 1 1 0 .abs_section_2a6 - _CAN4RXDSR3 2A7 1 1 0 .abs_section_2a7 - _CAN4RXDSR4 2A8 1 1 0 .abs_section_2a8 - _CAN4RXDSR5 2A9 1 1 0 .abs_section_2a9 - _CAN4RXDSR6 2AA 1 1 0 .abs_section_2aa - _CAN4RXDSR7 2AB 1 1 0 .abs_section_2ab - _CAN4RXDLR 2AC 1 1 0 .abs_section_2ac - _CAN4TXIDR0 2B0 1 1 0 .abs_section_2b0 - _CAN4TXIDR1 2B1 1 1 0 .abs_section_2b1 - _CAN4TXIDR2 2B2 1 1 0 .abs_section_2b2 - _CAN4TXIDR3 2B3 1 1 0 .abs_section_2b3 - _CAN4TXDSR0 2B4 1 1 0 .abs_section_2b4 - _CAN4TXDSR1 2B5 1 1 0 .abs_section_2b5 - _CAN4TXDSR2 2B6 1 1 0 .abs_section_2b6 - _CAN4TXDSR3 2B7 1 1 0 .abs_section_2b7 - _CAN4TXDSR4 2B8 1 1 0 .abs_section_2b8 - _CAN4TXDSR5 2B9 1 1 0 .abs_section_2b9 - _CAN4TXDSR6 2BA 1 1 0 .abs_section_2ba - _CAN4TXDSR7 2BB 1 1 0 .abs_section_2bb - _CAN4TXDLR 2BC 1 1 0 .abs_section_2bc - _CAN4TXTBPR 2BF 1 1 0 .abs_section_2bf - uxCriticalNesting 1000 1 1 101 .data - xLocalError 1001 1 1 2 .bss - xRxedChars 1002 2 2 3 .bss - xCharsForTx 1004 2 2 3 .bss - pxCurrentTCB 1006 2 2 28 .bss - uxTasksDeleted 1008 1 1 3 .bss - uxCurrentNumberOfTasks 1009 1 1 5 .bss - xTickCount 100A 2 2 14 .bss - uxTopUsedPriority 100C 1 1 2 .bss - uxTopReadyPriority 100D 1 1 15 .bss - xSchedulerRunning 100E 1 1 3 .bss - uxSchedulerSuspended 100F 1 1 6 .bss - uxMissedTicks 1010 1 1 4 .bss - uxTaskNumber.1 1011 1 1 2 .bss - pxReadyTasksLists 1012 3C 60 11 .bss - xDelayedTaskList1 104E F 15 2 .bss - xDelayedTaskList2 105D F 15 2 .bss - pxDelayedTaskList 106C 2 2 8 .bss - pxOverflowDelayedTaskList 106E 2 2 6 .bss - xPendingReadyList 1070 F 15 4 .bss - xTasksWaitingTermination 107F F 15 5 .bss - xSuspendedTaskList 108E F 15 2 .bss - xHeapHasBeenInitialised.1 109D 1 1 2 .bss - xHeap 109E 2804 10244 2 .bss - xStart 38A2 4 4 6 .bss - xEnd 38A6 4 4 4 .bss - uxFlashTaskNumber 38AA 1 1 2 .bss - usCheckVariable 38AB 2 2 4 .bss - xSuspendedQueueSendError 38AD 1 1 2 .bss - xSuspendedQueueReceiveError 38AE 1 1 3 .bss - ulValueToSend.6 38AF 4 4 5 .bss - ulExpectedValue.7 38B3 4 4 6 .bss - usLastTaskCheck.9 38B7 2 2 2 .bss - xContinousIncrementHandle 38B9 2 2 5 .bss - xLimitedIncrementHandle 38BB 2 2 2 .bss - ulCounter 38BD 4 4 10 .bss - ulReceivedValue.8 38C1 4 4 3 .bss - xPollingConsumerCount 38C5 1 1 3 .bss - xPollingProducerCount 38C6 1 1 3 .bss - xPolledQueue.1 38C7 2 2 3 .bss - xPort 38C9 2 2 2 .bss - uxBaseLED 38CB 1 1 5 .bss - uxRxLoops 38CC 1 1 3 .bss - xTaskCheck 38CD 1 1 3 .bss - sBlockingConsumerCount 38CE 6 6 5 .bss - sBlockingProducerCount 38D4 6 6 5 .bss - sLastBlockingConsumerCount.7 38DA 6 6 2 .bss - sLastBlockingProducerCount.8 38E0 6 6 2 .bss - usCreationCount 38E6 2 2 4 .bss - uxTasksRunningAtStart 38E8 1 1 4 .bss - usLastCreationCount.6 38E9 2 2 2 .bss - uxTasksRunningNow.7 38EB 1 1 1 .bss - xSuspendedTestQueue 38EC 2 2 3 .common - xCreatedTask1 38EE 2 2 2 .common - xCreatedTask2 38F0 2 2 2 .common - CmpHighVal 38F2 2 2 2 TickTimer_DATA - Byte1_Table 38F4 8 8 1 Byte1_DATA - COM0_PrescHigh.1 38FC 8 8 1 COM0_DATA - SerFlag 3904 2 2 1 COM0_DATA - PrescHigh 3906 2 2 2 COM0_DATA - NumMode 3908 1 1 2 COM0_DATA - _EntryPoint C000 2E 46 1 .init - PE_low_level_init C02E 4E 78 2 .init - STRING.Check.1 C09A 6 6 1 .rodata1 - STRING.IDLE.2 C0A0 5 5 1 .rodata1 - STRING.LEDx.1 C0A5 5 5 1 .rodata1 - STRING.CNT_INC.1 C0AA 8 8 1 .rodata1 - STRING.LIM_INC.2 C0B2 8 8 1 .rodata1 - STRING.C_CTRL.3 C0BA 7 7 1 .rodata1 - STRING.SUSP_TX.4 C0C1 8 8 1 .rodata1 - STRING.SUSP_RX.5 C0C9 8 8 1 .rodata1 - STRING.QConsNB.2 C0D1 8 8 1 .rodata1 - STRING.QProdNB.3 C0D9 8 8 1 .rodata1 - STRING.COMTx.1 C0E1 6 6 1 .rodata1 - STRING.COMRx.2 C0E7 6 6 1 .rodata1 - STRING.IntMath.1 C0ED 8 8 1 .rodata1 - STRING.QConsB1.1 C0F5 8 8 1 .rodata1 - STRING.QProdB2.2 C0FD 8 8 1 .rodata1 - STRING.QProdB3.3 C105 8 8 1 .rodata1 - STRING.QConsB4.4 C10D 8 8 1 .rodata1 - STRING.QProdB5.5 C115 8 8 1 .rodata1 - STRING.QConsB6.6 C11D 8 8 1 .rodata1 - STRING.CREATOR.1 C125 8 8 1 .rodata1 - STRING.SUICIDE1.2 C12D 9 9 1 .rodata1 - STRING.SUICIDE2.3 C136 9 9 1 .rodata1 - STRING.SUICIDE1.4 C13F 9 9 1 .rodata1 - STRING.SUICIDE2.5 C148 9 9 1 .rodata1 - _Startup C151 12 18 1 NON_BANKED - _LCMP C163 19 25 2 NON_BANKED - _LCMP_P C17C 15 21 3 NON_BANKED - _LNEG C191 D 13 2 NON_BANKED - _LINC C19E 5 5 4 NON_BANKED - _LMUL C1A3 27 39 1 NON_BANKED - _lDivMod C1CA E3 227 3 NON_BANKED - _LDIVU C2AD E 14 1 NON_BANKED - _NEG_P C2BB F 15 4 NON_BANKED - _LDIVS C2CA 35 53 2 NON_BANKED - Cpu_Interrupt C2FF 1 1 60 NON_BANKED - vCOM0_ISR C300 59 89 1 NON_BANKED - xBankedStartScheduler C359 13 19 1 NON_BANKED - vPortYield C36C 1D 29 1 NON_BANKED - vPortTickInterrupt C389 25 37 1 NON_BANKED - _BDMSTS FF01 1 1 0 .abs_section_ff01 - _BDMCCR FF06 1 1 0 .abs_section_ff06 - _BDMINR FF07 1 1 0 .abs_section_ff07 - _vect FF80 80 128 0 .abs_section_ff80 - Init 308000 29 41 2 .text - memcpy 308029 26 38 8 .text - memset 30804F 1E 30 2 .text - strncpy 30806D 2D 45 2 .text - main 30809A 9 9 0 .text - vMain 3080A3 52 82 1 .text - vErrorChecks 3080F5 33 51 3 .text - prvCheckOtherTasksAreStillRunning 308128 49 73 2 .text - vApplicationIdleHook 308171 70 112 2 .text - vParTestSetLED 3081E1 22 34 4 .text - vParTestToggleLED 308203 14 20 10 .text - xSerialPortInitMinimal 308217 24 36 2 .text - xSerialGetChar 30823B 17 23 2 .text - xSerialPutChar 318000 1D 29 2 ROM_PAGE31_524 - xTaskCreate 31801D D9 217 48 ROM_PAGE31_524 - vTaskDelete 3180F6 4A 74 4 ROM_PAGE31_524 - vTaskDelayUntil 318140 78 120 6 ROM_PAGE31_524 - vTaskDelay 3181B8 4A 74 16 ROM_PAGE31_524 - uxTaskPriorityGet 318202 26 38 2 ROM_PAGE31_524 - vTaskPrioritySet 328000 6B 107 4 ROM_PAGE32_525 - vTaskSuspend 32806B 47 71 6 ROM_PAGE32_525 - vTaskResume 3280B2 5B 91 6 ROM_PAGE32_525 - vTaskStartScheduler 32810D 35 53 2 ROM_PAGE32_525 - vTaskSuspendAll 328142 13 19 26 ROM_PAGE32_525 - xTaskResumeAll 328155 A5 165 30 ROM_PAGE32_525 - xTaskGetTickCount 3281FA 17 23 6 ROM_PAGE32_525 - uxTaskGetNumberOfTasks 328211 17 23 4 ROM_PAGE32_525 - vTaskIncrementTick 338000 84 132 4 ROM_PAGE33_526 - vTaskSwitchContext 338084 5B 91 4 ROM_PAGE33_526 - vTaskPlaceOnEventList 3380DF 44 68 4 ROM_PAGE33_526 - xTaskRemoveFromEventList 338123 6F 111 8 ROM_PAGE33_526 - prvIdleTask 338192 12 18 3 ROM_PAGE33_526 - prvInitialiseTCBVariables 3381A4 4F 79 2 ROM_PAGE33_526 - prvInitialiseTaskLists 3381F3 41 65 2 ROM_PAGE33_526 - prvCheckTasksWaitingTermination 348000 55 85 2 ROM_PAGE34_527 - prvAllocateTCBAndStack 348055 37 55 2 ROM_PAGE34_527 - prvDeleteTCB 34808C 11 17 2 ROM_PAGE34_527 - xQueueCreate 34809D 7C 124 14 ROM_PAGE34_527 - xQueueSend 348119 D4 212 9 ROM_PAGE34_527 - xQueueSendFromISR 3481ED 56 86 2 ROM_PAGE34_527 - xQueueReceive 358000 CE 206 9 ROM_PAGE35_528 - xQueueReceiveFromISR 3580CE 60 96 2 ROM_PAGE35_528 - uxQueueMessagesWaiting 35812E 1B 27 2 ROM_PAGE35_528 - prvUnlockQueue 358149 71 113 8 ROM_PAGE35_528 - prvIsQueueEmpty 3581BA 21 33 2 ROM_PAGE35_528 - prvIsQueueFull 3581DB 24 36 2 ROM_PAGE35_528 - vListInitialise 3581FF 20 32 6 ROM_PAGE35_528 - vListInitialiseItem 35821F 7 7 6 ROM_PAGE35_528 - vListInsertEnd 358226 27 39 16 ROM_PAGE35_528 - vListInsert 368000 5A 90 8 ROM_PAGE36_529 - vListRemove 36805A 23 35 32 ROM_PAGE36_529 - pvPortMalloc 36807D B6 182 14 ROM_PAGE36_529 - vPortFree 368133 34 52 10 ROM_PAGE36_529 - PE_Timer_LngHi1 368167 43 67 2 ROM_PAGE36_529 - vStartLEDFlashTasks 3681AA 2A 42 2 ROM_PAGE36_529 - vLEDFlashTask 3681D4 57 87 3 ROM_PAGE36_529 - vStartDynamicPriorityTasks 378000 9B 155 2 ROM_PAGE37_530 - vLimitedIncrementTask 37809B 22 34 3 ROM_PAGE37_530 - vContinuousIncrementTask 3780BD 33 51 3 ROM_PAGE37_530 - vCounterControlTask 3780F0 A0 160 5 ROM_PAGE37_530 - vQueueSendWhenSuspendedTask 378190 38 56 3 ROM_PAGE37_530 - vQueueReceiveWhenSuspendedTask 3781C8 53 83 3 ROM_PAGE37_530 - xAreDynamicPriorityTasksStillRunning 37821B 27 39 2 ROM_PAGE37_530 - vStartPolledQueueTasks 388000 49 73 2 ROM_PAGE38_531 - vPolledQueueProducer 388049 4F 79 3 ROM_PAGE38_531 - vPolledQueueConsumer 388098 5C 92 3 ROM_PAGE38_531 - xArePollingQueuesStillRunning 3880F4 1D 29 2 ROM_PAGE38_531 - vAltStartComTestTasks 388111 4D 77 2 ROM_PAGE38_531 - vComTxTask 38815E 51 81 3 ROM_PAGE38_531 - vComRxTask 3881AF 6A 106 3 ROM_PAGE38_531 - xAreComTestTasksStillRunning 388219 15 21 2 ROM_PAGE38_531 - pxPortInitialiseStack 398000 31 49 2 ROM_PAGE39_532 - prvSetupTimerInterrupt 398031 C 12 2 ROM_PAGE39_532 - xPortStartScheduler 39803D 4 4 2 ROM_PAGE39_532 - vStartIntegerMathTasks 398041 33 51 2 ROM_PAGE39_532 - vCompeteingIntMathTask 398074 87 135 3 ROM_PAGE39_532 - xAreIntegerMathsTaskStillRunning 3980FB 25 37 2 ROM_PAGE39_532 - vStartBlockingQueueTasks 3A8000 143 323 7 ROM_PAGE3A_533 - vBlockingQueueProducer 3A8143 3A 58 9 ROM_PAGE3A_533 - vBlockingQueueConsumer 3A817D 45 69 9 ROM_PAGE3A_533 - xAreBlockingQueuesStillRunning 3A81C2 49 73 2 ROM_PAGE3A_533 - vCreateSuicidalTasks 3A820B 33 51 2 ROM_PAGE3A_533 - vSuicidalTask 3B8000 52 82 12 ROM_PAGE3B_534 - vCreateTasks 3B8052 94 148 4 ROM_PAGE3B_534 - xIsCreateTaskStillRunning 3B80E6 36 54 2 ROM_PAGE3B_534 - SetCV 3B811C F 15 4 TickTimer_CODE - SetPV 3B812B C 12 2 TickTimer_CODE - HWEnDi 3B8137 8 8 4 TickTimer_CODE - TickTimer_Enable 3B813F 6 6 2 TickTimer_CODE - TickTimer_SetFreqHz 3B8145 51 81 2 TickTimer_CODE - TickTimer_Init 3B8196 15 21 2 TickTimer_CODE - Byte1_GetMsk 3B81AB D 13 4 Byte1_CODE - Byte1_PutBit 3B81B8 1F 31 2 Byte1_CODE - Byte1_NegBit 3B81D7 11 17 2 Byte1_CODE - HWEnDi 3B81E8 A 10 2 COM0_CODE - COM0_SetBaudRateMode 3B81F2 19 25 2 COM0_CODE - COM0_Init 3B820B 20 32 2 COM0_CODE - -********************************************************************************************* -UNUSED-OBJECTS SECTION ---------------------------------------------------------------------------------------------- -NOT USED PROCEDURES -STRING.C.o (ansibi.lib): - strerror memchr memcmp memcpy2 _memcpy_8bitCount memmove - _memset_clear_8bitCount strlen strset strcat strncat strcpy strcmp strncmp - strchr strrchr strspn strcspn strpbrk strstr strtok strcoll strxfrm -rtshc12.c.o (ansibi.lib): - _BSHL _BSHRS _BSHRU _BDIVMODU _BDIVMODS _ISHL _ISHRU _ISHRS _LSHL _LSHRU - _LSHRS _LADD _LSUB _LAND _LOR _LXOR _LCMP_PP _LABS _LCOM _LDEC _LMODU _LMODS - _ILSEXT _LTEST _COPY _CASE_DIRECT _CASE_DIRECT_BYTE _CASE_CHECKED - _CASE_CHECKED_BYTE _CASE_SEARCH _CASE_SEARCH_BYTE _CASE_SEARCH_8 - _CASE_SEARCH_8_BYTE _FCALL _FPCMP -serial.c.o: - vSerialClose -tasks.c.o: - vTaskEndScheduler -queue.c.o: - vQueueDelete -TickTimer.C.o: - TickTimer_Interrupt TickTimer_SetPeriodTicks16 TickTimer_SetPeriodTicks32 - TickTimer_SetPeriodUS TickTimer_SetPeriodMS -PE_Timer.C.o: - PE_Timer_LngMul PE_Timer_LngHi2 PE_Timer_LngHi3 PE_Timer_LngHi4 -port.c.o: - vPortEndScheduler -NOT USED VARIABLES -STRING.C.o (ansibi.lib): - STRING..1 next.2 -rtshc12.c.o (ansibi.lib): - _PowOfTwo_8 _PowOfTwo_16 _PowOfTwo_32 -Cpu.C.o: - CpuMode CCR_reg -heap_2.c.o: - heapSTRUCT_SIZE -death.c.o: - uxMaxNumberOfExtraTasksRunning - -********************************************************************************************* -COPYDOWN SECTION ---------------------------------------------------------------------------------------------- -------- ROM-ADDRESS: 0xC3AE ---- SIZE 4 --- -Filling bytes inserted - 00011000 -------- ROM-ADDRESS: 0xC3B2 ---- RAM-ADDRESS: 0x1000 ---- SIZE 1 --- -Name of initialized Object : uxCriticalNesting - FF -------- ROM-ADDRESS: 0xC3B3 ---- SIZE 4 --- -Filling bytes inserted - 001038F4 -------- ROM-ADDRESS: 0xC3B7 ---- RAM-ADDRESS: 0x38F4 ---- SIZE 8 --- -Name of initialized Object : Byte1_Table - 0102040810 204080 -------- ROM-ADDRESS: 0xC3BF ---- SIZE 1 --- -Filling bytes inserted - 00 -------- ROM-ADDRESS: 0xC3C0 ---- RAM-ADDRESS: 0x38FD ---- SIZE 7 --- -Name of initialized Object : COM0_PrescHigh.1:1 - 29005100A3 0146 -------- ROM-ADDRESS: 0xC3C7 ---- SIZE 2 --- -Filling bytes inserted - 0000 - -********************************************************************************************* -OBJECT-DEPENDENCIES SECTION ---------------------------------------------------------------------------------------------- -_EntryPoint USES _INITRM _INITEE _MISC _CLKSEL _PLLCTL _SYNR - _REFDV _CRGFLG _Startup -PE_low_level_init USES _TSCR1 _TCTL2 _TCTL1 _TIE _TTOV _TSCR2 _TIOS - _PWMCTL _PWMSDN _ICSYS _MCCTL TickTimer_Init _PORTAB - _DDRAB _DDRS _PTS COM0_Init _INTCR -_Startup USES _startupData Init -_LDIVU USES _lDivMod -_LDIVS USES _NEG_P _lDivMod -vCOM0_ISR USES _SCI0SR1 _SCI0DRL xRxedChars xQueueSendFromISR - _SCI0CR2 xCharsForTx xQueueReceiveFromISR -xBankedStartScheduler USES prvSetupTimerInterrupt pxCurrentTCB - uxCriticalNesting -vPortYield USES uxCriticalNesting pxCurrentTCB - vTaskSwitchContext -vPortTickInterrupt USES uxCriticalNesting pxCurrentTCB - vTaskIncrementTick vTaskSwitchContext _TFLG1 -_vect USES Cpu_Interrupt vCOM0_ISR vPortTickInterrupt - vPortYield _EntryPoint -Init USES _startupData -main USES PE_low_level_init vMain -vMain USES vStartLEDFlashTasks vStartPolledQueueTasks - vStartDynamicPriorityTasks vAltStartComTestTasks vStartBlockingQueueTasks - vStartIntegerMathTasks vCreateSuicidalTasks vErrorChecks - STRING.Check.1 xTaskCreate vTaskStartScheduler -vErrorChecks USES xTaskGetTickCount vTaskDelayUntil - prvCheckOtherTasksAreStillRunning _LCMP vParTestToggleLED -prvCheckOtherTasksAreStillRunning USES xArePollingQueuesStillRunning - xAreDynamicPriorityTasksStillRunning xAreComTestTasksStillRunning - xAreIntegerMathsTaskStillRunning xAreBlockingQueuesStillRunning - xIsCreateTaskStillRunning xLocalError -vApplicationIdleHook USES _LNEG _LDIVS _LCMP_P uxCriticalNesting - xLocalError -vParTestSetLED USES uxCriticalNesting Byte1_PutBit -vParTestToggleLED USES uxCriticalNesting Byte1_NegBit -xSerialPortInitMinimal USES xQueueCreate xRxedChars xCharsForTx - COM0_SetBaudRateMode -xSerialGetChar USES xRxedChars xQueueReceive -xSerialPutChar USES xCharsForTx xQueueSend _SCI0CR2 -xTaskCreate USES prvAllocateTCBAndStack - prvInitialiseTCBVariables pxPortInitialiseStack uxCriticalNesting - uxCurrentNumberOfTasks pxCurrentTCB prvInitialiseTaskLists - xSchedulerRunning uxTopUsedPriority uxTaskNumber.1 - uxTopReadyPriority pxReadyTasksLists vListInsertEnd -vTaskDelete USES uxCriticalNesting pxCurrentTCB vListRemove - xTasksWaitingTermination vListInsertEnd uxTasksDeleted -vTaskDelayUntil USES vTaskSuspendAll xTickCount pxCurrentTCB - vListRemove pxOverflowDelayedTaskList pxDelayedTaskList - vListInsert xTaskResumeAll -vTaskDelay USES vTaskSuspendAll xTickCount pxCurrentTCB - vListRemove pxOverflowDelayedTaskList pxDelayedTaskList - vListInsert xTaskResumeAll -uxTaskPriorityGet USES uxCriticalNesting pxCurrentTCB -vTaskPrioritySet USES uxCriticalNesting pxCurrentTCB - pxReadyTasksLists vListRemove uxTopReadyPriority vListInsertEnd -vTaskSuspend USES uxCriticalNesting pxCurrentTCB vListRemove - xSuspendedTaskList vListInsertEnd -vTaskResume USES uxCriticalNesting pxCurrentTCB vListRemove - uxTopReadyPriority pxReadyTasksLists vListInsertEnd -vTaskStartScheduler USES pxCurrentTCB prvIdleTask STRING.IDLE.2 - xTaskCreate xSchedulerRunning xTickCount - xPortStartScheduler -vTaskSuspendAll USES uxCriticalNesting uxSchedulerSuspended -xTaskResumeAll USES uxCriticalNesting uxSchedulerSuspended - uxCurrentNumberOfTasks vListRemove uxTopReadyPriority - pxReadyTasksLists vListInsertEnd pxCurrentTCB xPendingReadyList - uxMissedTicks vTaskIncrementTick -xTaskGetTickCount USES uxCriticalNesting xTickCount -uxTaskGetNumberOfTasks USES uxCriticalNesting uxCurrentNumberOfTasks -vTaskIncrementTick USES uxSchedulerSuspended xTickCount - pxDelayedTaskList pxOverflowDelayedTaskList vListRemove - uxTopReadyPriority pxReadyTasksLists vListInsertEnd uxMissedTicks -vTaskSwitchContext USES uxSchedulerSuspended uxTopReadyPriority - pxCurrentTCB pxReadyTasksLists -vTaskPlaceOnEventList USES pxCurrentTCB vListInsert xTickCount vListRemove - pxOverflowDelayedTaskList pxDelayedTaskList -xTaskRemoveFromEventList USES vListRemove uxSchedulerSuspended - uxTopReadyPriority pxReadyTasksLists xPendingReadyList - vListInsertEnd pxCurrentTCB -prvIdleTask USES prvCheckTasksWaitingTermination - pxReadyTasksLists vApplicationIdleHook -prvInitialiseTCBVariables USES strncpy vListInitialiseItem -prvInitialiseTaskLists USES pxReadyTasksLists xDelayedTaskList1 - xDelayedTaskList2 xPendingReadyList xTasksWaitingTermination - xSuspendedTaskList pxDelayedTaskList pxOverflowDelayedTaskList - vListInitialise -prvCheckTasksWaitingTermination USES uxTasksDeleted vTaskSuspendAll - xTasksWaitingTermination xTaskResumeAll uxCriticalNesting vListRemove - uxCurrentNumberOfTasks prvDeleteTCB -prvAllocateTCBAndStack USES pvPortMalloc vPortFree memset -prvDeleteTCB USES vPortFree -xQueueCreate USES pvPortMalloc vListInitialise vPortFree -xQueueSend USES vTaskSuspendAll uxCriticalNesting xQueueSend - prvIsQueueFull vTaskPlaceOnEventList prvUnlockQueue - xTaskResumeAll memcpy -xQueueSendFromISR USES memcpy xTaskRemoveFromEventList -xQueueReceive USES vTaskSuspendAll uxCriticalNesting xQueueReceive - prvIsQueueEmpty vTaskPlaceOnEventList prvUnlockQueue - xTaskResumeAll memcpy -xQueueReceiveFromISR USES memcpy xTaskRemoveFromEventList -uxQueueMessagesWaiting USES uxCriticalNesting -prvUnlockQueue USES uxCriticalNesting xTaskRemoveFromEventList -prvIsQueueEmpty USES uxCriticalNesting -prvIsQueueFull USES uxCriticalNesting -vListInitialise USES vListInitialiseItem -pvPortMalloc USES vTaskSuspendAll xHeapHasBeenInitialised.1 xHeap - xStart xEnd xTaskResumeAll -vPortFree USES vTaskSuspendAll xStart xTaskResumeAll -PE_Timer_LngHi1 USES _LCMP -vStartLEDFlashTasks USES vLEDFlashTask STRING.LEDx.1 xTaskCreate -vLEDFlashTask USES uxCriticalNesting uxFlashTaskNumber - xTaskGetTickCount vTaskDelayUntil vParTestToggleLED -vStartDynamicPriorityTasks USES xQueueCreate xSuspendedTestQueue - vContinuousIncrementTask STRING.CNT_INC.1 ulCounter - xContinousIncrementHandle xTaskCreate vLimitedIncrementTask - STRING.LIM_INC.2 xLimitedIncrementHandle vCounterControlTask - STRING.C_CTRL.3 vQueueSendWhenSuspendedTask STRING.SUSP_TX.4 - vQueueReceiveWhenSuspendedTask STRING.SUSP_RX.5 -vLimitedIncrementTask USES _LINC _LCMP_P vTaskSuspend -vContinuousIncrementTask USES uxTaskPriorityGet vTaskPrioritySet _LINC -vCounterControlTask USES vCounterControlTask xContinousIncrementHandle - vTaskSuspend ulCounter vTaskResume vTaskDelay - vTaskSuspendAll xTaskResumeAll xLimitedIncrementHandle - uxCriticalNesting usCheckVariable -vQueueSendWhenSuspendedTask USES vTaskSuspendAll xSuspendedTestQueue - ulValueToSend.6 xQueueSend xSuspendedQueueSendError - xTaskResumeAll vTaskDelay _LINC -vQueueReceiveWhenSuspendedTask USES vTaskSuspendAll xSuspendedTestQueue - ulReceivedValue.8 xQueueReceive xTaskResumeAll - xSuspendedQueueReceiveError ulExpectedValue.7 _LINC -xAreDynamicPriorityTasksStillRunning USES usCheckVariable usLastTaskCheck.9 - xSuspendedQueueSendError xSuspendedQueueReceiveError -vStartPolledQueueTasks USES xQueueCreate xPolledQueue.1 - vPolledQueueConsumer STRING.QConsNB.2 xTaskCreate - vPolledQueueProducer STRING.QProdNB.3 -vPolledQueueProducer USES xQueueSend uxCriticalNesting - xPollingProducerCount vTaskDelay -vPolledQueueConsumer USES xQueueReceive uxCriticalNesting - xPollingConsumerCount uxQueueMessagesWaiting vTaskDelay -xArePollingQueuesStillRunning USES xPollingConsumerCount xPollingProducerCount -vAltStartComTestTasks USES uxBaseLED xSerialPortInitMinimal vComTxTask - STRING.COMTx.1 xTaskCreate vComRxTask STRING.COMRx.2 -vComTxTask USES xPort xSerialPutChar uxBaseLED - vParTestToggleLED vParTestSetLED xTaskGetTickCount vTaskDelay -vComRxTask USES uxBaseLED vParTestToggleLED vParTestSetLED - uxRxLoops xPort xSerialGetChar -xAreComTestTasksStillRunning USES uxRxLoops -prvSetupTimerInterrupt USES TickTimer_SetFreqHz TickTimer_Enable -xPortStartScheduler USES xBankedStartScheduler -vStartIntegerMathTasks USES vCompeteingIntMathTask STRING.IntMath.1 - xTaskCheck xTaskCreate -vCompeteingIntMathTask USES _LNEG _LDIVS _LCMP_P uxCriticalNesting -xAreIntegerMathsTaskStillRunning USES xTaskCheck -vStartBlockingQueueTasks USES vStartBlockingQueueTasks xQueueCreate - sBlockingConsumerCount sBlockingProducerCount vBlockingQueueConsumer - STRING.QConsB1.1 xTaskCreate vBlockingQueueProducer - STRING.QProdB2.2 STRING.QProdB3.3 STRING.QConsB4.4 - STRING.QProdB5.5 STRING.QConsB6.6 pvPortMalloc -vBlockingQueueProducer USES xQueueSend -vBlockingQueueConsumer USES xQueueReceive -xAreBlockingQueuesStillRunning USES sBlockingConsumerCount - sLastBlockingConsumerCount.7 sBlockingProducerCount - sLastBlockingProducerCount.8 -vCreateSuicidalTasks USES pvPortMalloc vCreateTasks STRING.CREATOR.1 - xTaskCreate uxTaskGetNumberOfTasks uxTasksRunningAtStart -vSuicidalTask USES _LMUL vTaskDelay vTaskDelete -vCreateTasks USES vPortFree vTaskDelay vSuicidalTask - STRING.SUICIDE1.2 xCreatedTask1 xTaskCreate STRING.SUICIDE2.3 - STRING.SUICIDE1.4 xCreatedTask2 STRING.SUICIDE2.5 - usCreationCount vCreateTasks -xIsCreateTaskStillRunning USES usLastCreationCount.6 usCreationCount - uxTaskGetNumberOfTasks uxTasksRunningNow.7 uxTasksRunningAtStart -SetCV USES _TC0 _TC7 -SetPV USES _TSCR2 -HWEnDi USES _TFLG1 _TIE -TickTimer_Enable USES HWEnDi -TickTimer_SetFreqHz USES _LDIVU PE_Timer_LngHi1 CmpHighVal SetCV -TickTimer_Init USES CmpHighVal SetCV SetPV HWEnDi -Byte1_GetMsk USES Byte1_Table -Byte1_PutBit USES Byte1_GetMsk _PORTAB -Byte1_NegBit USES Byte1_GetMsk _PORTAB -HWEnDi USES _SCI0CR2 -COM0_SetBaudRateMode USES NumMode COM0_PrescHigh.1 PrescHigh _SCI0BD -COM0_Init USES PrescHigh SerFlag NumMode _SCI0CR1 _SCI0SR2 - _SCI0SR1 _SCI0CR2 _SCI0BD HWEnDi - -********************************************************************************************* -DEPENDENCY TREE -********************************************************************************************* - main and _Startup Group - | - +- main - | | - | +- PE_low_level_init - | | | - | | +- TickTimer_Init - | | | | - | | | +- SetCV - | | | | - | | | +- SetPV - | | | | - | | | +- HWEnDi - | | | - | | +- COM0_Init - | | | - | | +- HWEnDi - | | - | +- vMain - | | - | +- vStartLEDFlashTasks - | | | - | | +- vLEDFlashTask - | | | | - | | | +- xTaskGetTickCount - | | | | - | | | +- vTaskDelayUntil - | | | | | - | | | | +- vTaskSuspendAll - | | | | | - | | | | +- vListRemove - | | | | | - | | | | +- vListInsert - | | | | | - | | | | +- xTaskResumeAll - | | | | | - | | | | +- vListRemove (see above) - | | | | | - | | | | +- vListInsertEnd - | | | | | - | | | | +- vTaskIncrementTick - | | | | | - | | | | +- vListRemove (see above) - | | | | | - | | | | +- vListInsertEnd (see above) - | | | | - | | | +- vParTestToggleLED - | | | | - | | | +- Byte1_NegBit - | | | | - | | | +- Byte1_GetMsk - | | | - | | +- xTaskCreate - | | | - | | +- prvAllocateTCBAndStack - | | | | - | | | +- pvPortMalloc - | | | | | - | | | | +- vTaskSuspendAll (see above) - | | | | | - | | | | +- xTaskResumeAll (see above) - | | | | - | | | +- vPortFree - | | | | | - | | | | +- vTaskSuspendAll (see above) - | | | | | - | | | | +- xTaskResumeAll (see above) - | | | | - | | | +- memset - | | | - | | +- prvInitialiseTCBVariables - | | | | - | | | +- strncpy - | | | | - | | | +- vListInitialiseItem - | | | - | | +- pxPortInitialiseStack - | | | - | | +- prvInitialiseTaskLists - | | | | - | | | +- vListInitialise - | | | | - | | | +- vListInitialiseItem (see above) - | | | - | | +- vListInsertEnd (see above) - | | - | +- vStartPolledQueueTasks - | | | - | | +- xQueueCreate - | | | | - | | | +- pvPortMalloc (see above) - | | | | - | | | +- vListInitialise (see above) - | | | | - | | | +- vPortFree (see above) - | | | - | | +- vPolledQueueConsumer - | | | | - | | | +- xQueueReceive - | | | | | - | | | | +- vTaskSuspendAll (see above) - | | | | | - | | | | +- prvIsQueueEmpty - | | | | | - | | | | +- vTaskPlaceOnEventList - | | | | | | - | | | | | +- vListInsert (see above) - | | | | | | - | | | | | +- vListRemove (see above) - | | | | | - | | | | +- prvUnlockQueue - | | | | | | - | | | | | +- xTaskRemoveFromEventList - | | | | | | - | | | | | +- vListRemove (see above) - | | | | | | - | | | | | +- vListInsertEnd (see above) - | | | | | - | | | | +- xTaskResumeAll (see above) - | | | | | - | | | | +- memcpy - | | | | - | | | +- uxQueueMessagesWaiting - | | | | - | | | +- vTaskDelay - | | | | - | | | +- vTaskSuspendAll (see above) - | | | | - | | | +- vListRemove (see above) - | | | | - | | | +- vListInsert (see above) - | | | | - | | | +- xTaskResumeAll (see above) - | | | - | | +- xTaskCreate (see above) - | | | - | | +- vPolledQueueProducer - | | | - | | +- xQueueSend - | | | | - | | | +- vTaskSuspendAll (see above) - | | | | - | | | +- prvIsQueueFull - | | | | - | | | +- vTaskPlaceOnEventList (see above) - | | | | - | | | +- prvUnlockQueue (see above) - | | | | - | | | +- xTaskResumeAll (see above) - | | | | - | | | +- memcpy (see above) - | | | - | | +- vTaskDelay (see above) - | | - | +- vStartDynamicPriorityTasks - | | | - | | +- xQueueCreate (see above) - | | | - | | +- vContinuousIncrementTask - | | | | - | | | +- uxTaskPriorityGet - | | | | - | | | +- vTaskPrioritySet - | | | | | - | | | | +- vListRemove (see above) - | | | | | - | | | | +- vListInsertEnd (see above) - | | | | - | | | +- _LINC - | | | - | | +- xTaskCreate (see above) - | | | - | | +- vLimitedIncrementTask - | | | | - | | | +- _LINC (see above) - | | | | - | | | +- _LCMP_P - | | | | - | | | +- vTaskSuspend - | | | | - | | | +- vListRemove (see above) - | | | | - | | | +- vListInsertEnd (see above) - | | | - | | +- vCounterControlTask - | | | | - | | | +- vTaskSuspend (see above) - | | | | - | | | +- vTaskResume - | | | | | - | | | | +- vListRemove (see above) - | | | | | - | | | | +- vListInsertEnd (see above) - | | | | - | | | +- vTaskDelay (see above) - | | | | - | | | +- vTaskSuspendAll (see above) - | | | | - | | | +- xTaskResumeAll (see above) - | | | - | | +- vQueueSendWhenSuspendedTask - | | | | - | | | +- vTaskSuspendAll (see above) - | | | | - | | | +- xQueueSend (see above) - | | | | - | | | +- xTaskResumeAll (see above) - | | | | - | | | +- vTaskDelay (see above) - | | | | - | | | +- _LINC (see above) - | | | - | | +- vQueueReceiveWhenSuspendedTask - | | | - | | +- vTaskSuspendAll (see above) - | | | - | | +- xQueueReceive (see above) - | | | - | | +- xTaskResumeAll (see above) - | | | - | | +- _LINC (see above) - | | - | +- vAltStartComTestTasks - | | | - | | +- xSerialPortInitMinimal - | | | | - | | | +- xQueueCreate (see above) - | | | | - | | | +- COM0_SetBaudRateMode - | | | - | | +- vComTxTask - | | | | - | | | +- xSerialPutChar - | | | | | - | | | | +- xQueueSend (see above) - | | | | - | | | +- vParTestToggleLED (see above) - | | | | - | | | +- vParTestSetLED - | | | | | - | | | | +- Byte1_PutBit - | | | | | - | | | | +- Byte1_GetMsk (see above) - | | | | - | | | +- xTaskGetTickCount (see above) - | | | | - | | | +- vTaskDelay (see above) - | | | - | | +- xTaskCreate (see above) - | | | - | | +- vComRxTask - | | | - | | +- vParTestToggleLED (see above) - | | | - | | +- vParTestSetLED (see above) - | | | - | | +- xSerialGetChar - | | | - | | +- xQueueReceive (see above) - | | - | +- vStartBlockingQueueTasks - | | | - | | +- xQueueCreate (see above) - | | | - | | +- vBlockingQueueConsumer - | | | | - | | | +- xQueueReceive (see above) - | | | - | | +- xTaskCreate (see above) - | | | - | | +- vBlockingQueueProducer - | | | | - | | | +- xQueueSend (see above) - | | | - | | +- pvPortMalloc (see above) - | | - | +- vStartIntegerMathTasks - | | | - | | +- vCompeteingIntMathTask - | | | | - | | | +- _LNEG - | | | | - | | | +- _LDIVS - | | | | | - | | | | +- _NEG_P - | | | | | - | | | | +- _lDivMod - | | | | - | | | +- _LCMP_P (see above) - | | | - | | +- xTaskCreate (see above) - | | - | +- vCreateSuicidalTasks - | | | - | | +- pvPortMalloc (see above) - | | | - | | +- vCreateTasks - | | | | - | | | +- vPortFree (see above) - | | | | - | | | +- vTaskDelay (see above) - | | | | - | | | +- vSuicidalTask - | | | | | - | | | | +- _LMUL - | | | | | - | | | | +- vTaskDelay (see above) - | | | | | - | | | | +- vTaskDelete - | | | | | - | | | | +- vListRemove (see above) - | | | | | - | | | | +- vListInsertEnd (see above) - | | | | - | | | +- xTaskCreate (see above) - | | | - | | +- xTaskCreate (see above) - | | | - | | +- uxTaskGetNumberOfTasks - | | - | +- vErrorChecks - | | | - | | +- xTaskGetTickCount (see above) - | | | - | | +- vTaskDelayUntil (see above) - | | | - | | +- prvCheckOtherTasksAreStillRunning - | | | | - | | | +- xArePollingQueuesStillRunning - | | | | - | | | +- xAreDynamicPriorityTasksStillRunning - | | | | - | | | +- xAreComTestTasksStillRunning - | | | | - | | | +- xAreIntegerMathsTaskStillRunning - | | | | - | | | +- xAreBlockingQueuesStillRunning - | | | | - | | | +- xIsCreateTaskStillRunning - | | | | - | | | +- uxTaskGetNumberOfTasks (see above) - | | | - | | +- _LCMP - | | | - | | +- vParTestToggleLED (see above) - | | - | +- xTaskCreate (see above) - | | - | +- vTaskStartScheduler - | | - | +- prvIdleTask - | | | - | | +- prvCheckTasksWaitingTermination - | | | | - | | | +- vTaskSuspendAll (see above) - | | | | - | | | +- xTaskResumeAll (see above) - | | | | - | | | +- vListRemove (see above) - | | | | - | | | +- prvDeleteTCB - | | | | - | | | +- vPortFree (see above) - | | | - | | +- vApplicationIdleHook - | | | - | | +- _LNEG (see above) - | | | - | | +- _LDIVS (see above) - | | | - | | +- _LCMP_P (see above) - | | - | +- xTaskCreate (see above) - | | - | +- xPortStartScheduler - | | - | +- xBankedStartScheduler - | | - | +- prvSetupTimerInterrupt - | | - | +- TickTimer_SetFreqHz - | | | - | | +- _LDIVU - | | | | - | | | +- _lDivMod (see above) - | | | - | | +- PE_Timer_LngHi1 - | | | | - | | | +- _LCMP (see above) - | | | - | | +- SetCV (see above) - | | - | +- TickTimer_Enable - | | - | +- HWEnDi (see above) - | - +- _EntryPoint - | - +- _Startup - | - +- Init - - _vect - | - +- Cpu_Interrupt - | - +- vCOM0_ISR - | | - | +- xQueueSendFromISR - | | | - | | +- memcpy (see above) - | | | - | | +- xTaskRemoveFromEventList (see above) - | | - | +- xQueueReceiveFromISR - | | - | +- memcpy (see above) - | | - | +- xTaskRemoveFromEventList (see above) - | - +- vPortTickInterrupt - | | - | +- vTaskIncrementTick (see above) - | | - | +- vTaskSwitchContext - | - +- vPortYield - | | - | +- vTaskSwitchContext (see above) - | - +- _EntryPoint (see above) - -********************************************************************************************* -STATISTIC SECTION ---------------------------------------------------------------------------------------------- - -ExeFile: --------- -Number of blocks to be downloaded: 19 -Total size of all blocks to be downloaded: 7635 - diff --git a/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Erase_unsecure_hcs12.cmd b/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Erase_unsecure_hcs12.cmd deleted file mode 100644 index eecca9d13..000000000 --- a/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Erase_unsecure_hcs12.cmd +++ /dev/null @@ -1,66 +0,0 @@ -// HCS12 Core erasing + unsecuring command file: -// These commands mass erase the chip then program the security byte to 0xFE (unsecured state). - -// Evaluate the clock divider to set in ECLKDIV/FCLKDIV registers: - -// An average programming clock of 175 kHz is chosen. - -// If the oscillator frequency is less than 10 MHz, the value to store -// in ECLKDIV/FCLKDIV is equal to " oscillator frequency (kHz) / 175 ". - -// If the oscillator frequency is higher than 10 MHz, the value to store -// in ECLKDIV/FCLKDIV is equal to " oscillator frequency (kHz) / 1400 + 0x40 (to set PRDIV8 flag)". - -// Datasheet proposed values: -// -// oscillator frequency ECLKDIV/FCLKDIV value (hexadecimal) -// -// 16 MHz $49 -// 8 MHz $27 -// 4 MHz $13 -// 2 MHz $9 -// 1 MHz $4 - -define CLKDIV 0x49 - -FLASH MEMUNMAP // do not interact with regular flash programming monitor - -//mass erase flash -wb 0x100 CLKDIV // set FCLKDIV clock divider -wb 0x103 0 // FCFNG select block 0 -wb 0x102 0x10 // set the WRALL bit in FTSTMOD to affect all blocks -wb 0x104 0xFF // FPROT all protection disabled -wb 0x105 0x30 // clear PVIOL and ACCERR in FSTAT register -ww 0x108 0xD000 // write to FADDR address register -ww 0x10A 0x0000 // write to FDATA data register -wb 0x106 0x41 // write MASS ERASE command in FCMD register -wb 0x105 0x80 // clear CBEIF in FSTAT register to execute the command -wait 20 // wait for command to complete - -//mass erase eeprom -wb 0x110 CLKDIV // set ECLKDV clock divider -wb 0x114 0xFF // EPROT all protection disabled -wb 0x115 0x30 // clear PVIOL and ACCERR in ESTAT register -ww 0x118 0x0400 // write to EADDR eeprom address register -ww 0x11A 0x0000 // write to EDATA eeprom data register -wb 0x116 0x41 // write MASS ERASE command in ECMD register -wb 0x115 0x80 // clear CBEIF in ESTAT register to execute the command -wait 20 // wait for command to complete - -reset - -//reprogram Security byte to Unsecure state -wb 0x100 CLKDIV // set FCLKDIV clock divider -wb 0x103 0 // FCFNG select block 0 -wb 0x104 0xFF // FPROT all protection disabled -wb 0x105 0x30 // clear PVIOL and ACCERR in FSTAT register -ww 0xFF0E 0xFFFE // write security byte to "Unsecured" state -wb 0x106 0x20 // write MEMORY PROGRAM command in FCMD register -wb 0x105 0x80 // clear CBEIF in FSTAT register to execute the command -wait 20 // wait for command to complete - -reset - -FLASH MEMMAP // restore regular flash programming monitor -undef CLKDIV // undefine variable - diff --git a/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Postload.cmd b/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Postload.cmd deleted file mode 100644 index 0a5372487..000000000 --- a/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Postload.cmd +++ /dev/null @@ -1,3 +0,0 @@ -// After load the commands written below will be executed -// Show main function at startup -FindProc main diff --git a/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Preload.cmd b/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Preload.cmd deleted file mode 100644 index 691c5eede..000000000 --- a/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Preload.cmd +++ /dev/null @@ -1 +0,0 @@ -// Before load the commands written below will be executed diff --git a/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Reset.cmd b/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Reset.cmd deleted file mode 100644 index f0fc87448..000000000 --- a/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Reset.cmd +++ /dev/null @@ -1 +0,0 @@ -// After reset the commands written below will be executed diff --git a/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Startup.cmd b/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Startup.cmd deleted file mode 100644 index 5f2b5a568..000000000 --- a/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Startup.cmd +++ /dev/null @@ -1 +0,0 @@ -// At startup the commands written below will be executed diff --git a/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Vppoff.cmd b/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Vppoff.cmd deleted file mode 100644 index 52e399a61..000000000 --- a/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Vppoff.cmd +++ /dev/null @@ -1 +0,0 @@ -// After programming the flash, the commands written below will be executed diff --git a/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Vppon.cmd b/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Vppon.cmd deleted file mode 100644 index 048a6d94d..000000000 --- a/Demo/HCS12_CodeWarrior_banked/cmd/P&E_ICD_Vppon.cmd +++ /dev/null @@ -1 +0,0 @@ -// Before programming the flash, the commands written below will be executed diff --git a/Demo/HCS12_CodeWarrior_banked/cmd/Simulator_Postload.cmd b/Demo/HCS12_CodeWarrior_banked/cmd/Simulator_Postload.cmd deleted file mode 100644 index 0a5372487..000000000 --- a/Demo/HCS12_CodeWarrior_banked/cmd/Simulator_Postload.cmd +++ /dev/null @@ -1,3 +0,0 @@ -// After load the commands written below will be executed -// Show main function at startup -FindProc main diff --git a/Demo/HCS12_CodeWarrior_banked/cmd/Simulator_Preload.cmd b/Demo/HCS12_CodeWarrior_banked/cmd/Simulator_Preload.cmd deleted file mode 100644 index 691c5eede..000000000 --- a/Demo/HCS12_CodeWarrior_banked/cmd/Simulator_Preload.cmd +++ /dev/null @@ -1 +0,0 @@ -// Before load the commands written below will be executed diff --git a/Demo/HCS12_CodeWarrior_banked/cmd/Simulator_Reset.cmd b/Demo/HCS12_CodeWarrior_banked/cmd/Simulator_Reset.cmd deleted file mode 100644 index f0fc87448..000000000 --- a/Demo/HCS12_CodeWarrior_banked/cmd/Simulator_Reset.cmd +++ /dev/null @@ -1 +0,0 @@ -// After reset the commands written below will be executed diff --git a/Demo/HCS12_CodeWarrior_banked/cmd/Simulator_SetCPU.cmd b/Demo/HCS12_CodeWarrior_banked/cmd/Simulator_SetCPU.cmd deleted file mode 100644 index 5f2b5a568..000000000 --- a/Demo/HCS12_CodeWarrior_banked/cmd/Simulator_SetCPU.cmd +++ /dev/null @@ -1 +0,0 @@ -// At startup the commands written below will be executed diff --git a/Demo/HCS12_CodeWarrior_banked/cmd/Simulator_Startup.cmd b/Demo/HCS12_CodeWarrior_banked/cmd/Simulator_Startup.cmd deleted file mode 100644 index 5f2b5a568..000000000 --- a/Demo/HCS12_CodeWarrior_banked/cmd/Simulator_Startup.cmd +++ /dev/null @@ -1 +0,0 @@ -// At startup the commands written below will be executed diff --git a/Demo/HCS12_CodeWarrior_banked/main.c b/Demo/HCS12_CodeWarrior_banked/main.c deleted file mode 100644 index c020a05a3..000000000 --- a/Demo/HCS12_CodeWarrior_banked/main.c +++ /dev/null @@ -1,291 +0,0 @@ - -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/* - * - * vMain() is effectively the demo application entry point. It is called by - * the main() function generated by the Processor Expert application. - * - * vMain() creates all the demo application tasks, then starts the scheduler. - * The WEB documentation provides more details of the demo application tasks. - * - * Main.c also creates a task called "Check". This only executes every three - * seconds but has the highest priority so is guaranteed to get processor time. - * Its main function is to check that all the other tasks are still operational. - * Each task (other than the "flash" tasks) maintains a unique count that is - * incremented each time the task successfully completes its function. Should - * any error occur within such a task the count is permanently halted. The - * check task inspects the count of each task to ensure it has changed since - * the last time the check task executed. If all the count variables have - * changed all the tasks are still executing error free, and the check task - * toggles the onboard LED. Should any task contain an error at any time - * the LED toggle rate will change from 3 seconds to 500ms. - * - * This file also includes the functionality implemented within the - * standard demo application file integer.c. This is done to demonstrate the - * use of an idle hook. See the documentation within integer.c for the - * rationale of the integer task functionality. - * */ - -/* Kernel includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" - -/* Demo application includes. */ -#include "flash.h" -#include "PollQ.h" -#include "dynamic.h" -#include "partest.h" -#include "comtest2.h" -#include "BlockQ.h" -#include "integer.h" -#include "death.h" - - -/*----------------------------------------------------------- - Definitions. ------------------------------------------------------------*/ - -/* Priorities assigned to demo application tasks. */ -#define mainFLASH_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainDEATH_PRIORITY ( tskIDLE_PRIORITY + 1 ) - -/* LED that is toggled by the check task. The check task periodically checks -that all the other tasks are operating without error. If no errors are found -the LED is toggled with mainCHECK_PERIOD frequency. If an error is found -then the toggle rate increases to mainERROR_CHECK_PERIOD. */ -#define mainCHECK_TASK_LED ( 7 ) -#define mainCHECK_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS ) -#define mainERROR_CHECK_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS ) - -/* The constants used in the idle task calculation. */ -#define intgCONST1 ( ( portLONG ) 123 ) -#define intgCONST2 ( ( portLONG ) 234567 ) -#define intgCONST3 ( ( portLONG ) -3 ) -#define intgCONST4 ( ( portLONG ) 7 ) -#define intgEXPECTED_ANSWER ( ( ( intgCONST1 + intgCONST2 ) * intgCONST3 ) / intgCONST4 ) - - -/* Baud rate used by the serial port tasks (ComTest tasks). -IMPORTANT: The function COM0_SetBaudRateValue() which is generated by the -Processor Expert is used to set the baud rate. As configured in the FreeRTOS -download this value must be one of the following: - -0 to configure for 38400 baud. -1 to configure for 19200 baud. -2 to configure for 9600 baud. -3 to configure for 4800 baud. */ -#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 2 ) - -/* LED used by the serial port tasks. This is toggled on each character Tx, -and mainCOM_TEST_LED + 1 is toggles on each character Rx. */ -#define mainCOM_TEST_LED ( 3 ) - -/*----------------------------------------------------------- - Local functions prototypes. ------------------------------------------------------------*/ - -/* - * The 'Check' task function. See the explanation at the top of the file. - */ -static void vErrorChecks( void* pvParameters ); - -/* - * The idle task hook - in which the integer task is implemented. See the - * explanation at the top of the file. - */ -void vApplicationIdleHook( void ); - -/* - * Checks the unique counts of other tasks to ensure they are still operational. - */ -static portLONG prvCheckOtherTasksAreStillRunning( void ); - - - -/*----------------------------------------------------------- - Local variables. ------------------------------------------------------------*/ - -/* A few tasks are defined within this file. This flag is used to indicate -their status. If an error is detected in one of the locally defined tasks then -this flag is set to pdTRUE. */ -portBASE_TYPE xLocalError = pdFALSE; - - -/*-----------------------------------------------------------*/ - -/* - * This is called from the main() function generated by the Processor Expert. - */ -void vMain( void ) -{ - /* Start some of the standard demo tasks. */ - vStartLEDFlashTasks( mainFLASH_PRIORITY ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartDynamicPriorityTasks(); - vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - - /* Start the locally defined tasks. There is also a task implemented as - the idle hook. */ - xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - - /* Must be the last demo created. */ - vCreateSuicidalTasks( mainDEATH_PRIORITY ); - - /* All the tasks have been created - start the scheduler. */ - vTaskStartScheduler(); - - /* Should not reach here! */ - for( ;; ); -} -/*-----------------------------------------------------------*/ - -static void vErrorChecks( void *pvParameters ) -{ -portTickType xDelayPeriod = mainCHECK_PERIOD; -portTickType xLastWakeTime; - - /* Initialise xLastWakeTime to ensure the first call to vTaskDelayUntil() - functions correctly. */ - xLastWakeTime = xTaskGetTickCount(); - - for( ;; ) - { - /* Delay until it is time to execute again. The delay period is - shorter following an error. */ - vTaskDelayUntil( &xLastWakeTime, xDelayPeriod ); - - /* Check all the demo application tasks are executing without - error. If an error is found the delay period is shortened - this - has the effect of increasing the flash rate of the 'check' task - LED. */ - if( prvCheckOtherTasksAreStillRunning() == pdFAIL ) - { - /* An error has been detected in one of the tasks - flash faster. */ - xDelayPeriod = mainERROR_CHECK_PERIOD; - } - - /* Toggle the LED each cycle round. */ - vParTestToggleLED( mainCHECK_TASK_LED ); - } -} -/*-----------------------------------------------------------*/ - -static portLONG prvCheckOtherTasksAreStillRunning( void ) -{ -portBASE_TYPE xAllTasksPassed = pdPASS; - - if( xArePollingQueuesStillRunning() != pdTRUE ) - { - xAllTasksPassed = pdFAIL; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - xAllTasksPassed = pdFAIL; - } - - if( xAreComTestTasksStillRunning() != pdTRUE ) - { - xAllTasksPassed = pdFALSE; - } - - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - xAllTasksPassed = pdFALSE; - } - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - xAllTasksPassed = pdFALSE; - } - - if( xIsCreateTaskStillRunning() != pdTRUE ) - { - xAllTasksPassed = pdFALSE; - } - - /* Also check the status flag for the tasks defined within this function. */ - if( xLocalError != pdFALSE ) - { - xAllTasksPassed = pdFAIL; - } - - return xAllTasksPassed; -} -/*-----------------------------------------------------------*/ - -void vApplicationIdleHook( void ) -{ -/* This variable is effectively set to a constant so it is made volatile to -ensure the compiler does not just get rid of it. */ -volatile portLONG lValue; - - /* Keep performing a calculation and checking the result against a constant. */ - - /* Perform the calculation. This will store partial value in - registers, resulting in a good test of the context switch mechanism. */ - lValue = intgCONST1; - lValue += intgCONST2; - lValue *= intgCONST3; - lValue /= intgCONST4; - - /* Did we perform the calculation correctly with no corruption? */ - if( lValue != intgEXPECTED_ANSWER ) - { - /* Error! */ - portENTER_CRITICAL(); - xLocalError = pdTRUE; - portEXIT_CRITICAL(); - } - - /* Yield in case cooperative scheduling is being used. */ - #if configUSE_PREEMPTION == 0 - { - taskYIELD(); - } - #endif -} -/*-----------------------------------------------------------*/ - - - diff --git a/Demo/HCS12_CodeWarrior_banked/prm/burner.bbl b/Demo/HCS12_CodeWarrior_banked/prm/burner.bbl deleted file mode 100644 index 639ffdef3..000000000 --- a/Demo/HCS12_CodeWarrior_banked/prm/burner.bbl +++ /dev/null @@ -1,223 +0,0 @@ -/* logical s-record file */ -OPENFILE "%ABS_FILE%.s19" -format=motorola -busWidth=1 -origin=0 -len=0x1000000 -destination=0 -SRECORD=Sx -SENDBYTE 1 "%ABS_FILE%" -CLOSE - -/* physical s-record file */ -OPENFILE "%ABS_FILE%.phy" -format = motorola -busWidth = 1 -len = 0x4000 - -origin = 0x008000 -destination = 0x000000 -SENDBYTE 1 "%ABS_FILE%" -origin = 0x018000 -destination = 0x004000 -SENDBYTE 1 "%ABS_FILE%" -origin = 0x028000 -destination = 0x008000 -SENDBYTE 1 "%ABS_FILE%" -origin = 0x038000 -destination = 0x00C000 -SENDBYTE 1 "%ABS_FILE%" -origin = 0x048000 -destination = 0x010000 -SENDBYTE 1 "%ABS_FILE%" -origin = 0x058000 -destination = 0x014000 -SENDBYTE 1 "%ABS_FILE%" -origin = 0x068000 -destination = 0x018000 -SENDBYTE 1 "%ABS_FILE%" -origin = 0x078000 -destination = 0x01C000 -SENDBYTE 1 "%ABS_FILE%" -origin = 0x088000 -destination = 0x020000 -SENDBYTE 1 "%ABS_FILE%" -origin = 0x098000 -destination = 0x024000 -SENDBYTE 1 "%ABS_FILE%" -origin = 0x0A8000 -destination = 0x028000 -SENDBYTE 1 "%ABS_FILE%" -origin = 0x0B8000 -destination = 0x02C000 -SENDBYTE 1 "%ABS_FILE%" -origin = 0x0C8000 -destination = 0x030000 -SENDBYTE 1 "%ABS_FILE%" -origin = 0x0D8000 -destination = 0x034000 -SENDBYTE 1 "%ABS_FILE%" -origin = 0x0E8000 -destination = 0x038000 -SENDBYTE 1 "%ABS_FILE%" -origin = 0x0F8000 -destination = 0x03C000 -SENDBYTE 1 "%ABS_FILE%" - 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This enables to debug with the P&E ICD12 target interface. - The P&E ICD12 target interface allows to debug using the - BDM connector with P&E BDM Multilink or Cable12 hardware. - The BDM Multilink and Cable12 connect to the host parallel port. - Please consult your hardware documentation for additional details. - - -Additional connections can be chosen in the simulator/debugger, -use the menu Component > Set Target. - -//------------------------------------------------------------------------ -// Processor Expert -//------------------------------------------------------------------------ -This project is prepared to be designed with Processor Expert. -The project has an additional 'tab' named 'Processor Expert' where you -can configure the CPU and its beans. -The CPU selected is inserted into the Processor Expert project panel, in -the Debug and Release configurations. -Change of the configuration is possible by the mouse double-click on it. -All the installed Embedded Beans are accessible in the Bean Selector -window, grouped into folders according to their function. The mouse -double-click on selected Embedded Bean in the Bean Selector window adds -the Bean to the project. The mouse double-click on the Bean icon in the -Project panel opens the Bean Inspector window, which is used to set the -Bean properties. Source code is generated after selecting the -(Code Design 'Project_name.mcp') menu command from the CodeWarrior main -window (Processor Expert > Code design 'Project_name.mcp'). -Use the bean methods and events to write your code in the main module -'Project_name'.c and the event module Events.c. - -For more help please read Processor Expert help: - (Processor Expert > Help > 'Topic'). - -The following folders are used in CodeWarrior project window for -ProcessorExpert: -- User modules: contains your sources. The main module 'Project_name'.c - and event module Events.c are located here after the Processor Expert - code generation. -- Prm: Linker parameter file used for linking. Note that the file used - for the linker is specified in the Linker Preference Panel. To open - the Preference Panel, please press or open the - (Edit > 'Current Build Target Name' Settings...) menu item in the - CodeWarrior main window menu, while the project window is opened). - After Processor Expert code generation 'Project_name'.prm file - will be placed here. You can switch off the .prm file generation in - Processor Expert if you want (in the CPU bean, Build Options) -- Generated code: this folder appears after the Processor Expert code - generation and contains generated code from Processor Expert. -- Doc: other files generated from the Processor Expert (documentation) - -//------------------------------------------------------------------------ -// Getting Started -//------------------------------------------------------------------------ -To build/debug your project, use the menu Project > Debug or press F5. -This will open the simulator/debugger. -Press again F5 in the debugger (or menu Run > Start/Continue) to start -the application. The menu Run > Halt or F6 stops the application. -In the debugger menu Component > Open you can load additional components. - -//------------------------------------------------------------------------ -// Project structure -//------------------------------------------------------------------------ -The project generated contains various files/folders: -- readme.txt: this file -- Sources: folder with the application source code -- Startup Code: C/C++ startup code -- Prm: - - burner.bbl file to generate S-Records -- Linker Map: the .map file generated by the linker -- Libraries: needed library files (ANSI, derivative header/implementation files) -- Debugger Project File: contains a .ini file for the debugger for each - connection -- Debugger Cmd Files: contains sub-folders for each connection with command - files - -//------------------------------------------------------------------------ -// Adding your own code -//------------------------------------------------------------------------ -Once everything is working as expected, you can begin adding your own code -to the project. Keep in mind that we provide this as an example of how to -get up and running quickly with CodeWarrior. There are certainly other -ways to handle interrupts and set up your linker command file. Feel free -to modify any of the source files provided. - -//------------------------------------------------------------------------ -// Simulator/Debugger: Additional components -//------------------------------------------------------------------------ -In the simulator/debugger, you can load additional components. Try the menu -Component > Open. - -//------------------------------------------------------------------------ -// Additional documentation -//------------------------------------------------------------------------ -Check out the online documentation provided. Use in CodeWarrior IDE the -menu Help > Online Manuals. - -//------------------------------------------------------------------------ -// Contacting Metrowerks -//------------------------------------------------------------------------ -For bug reports, technical questions, and suggestions, please use the -forms installed in the Release_Notes folder and send them to: -USA: support@metrowerks.com -EUROPE: support_europe@metrowerks.com -ASIA/PACIFIC: j-emb-sup@metrowerks.com \ No newline at end of file diff --git a/Demo/HCS12_CodeWarrior_banked/serial/serial.c b/Demo/HCS12_CodeWarrior_banked/serial/serial.c deleted file mode 100644 index bf2ce5b20..000000000 --- a/Demo/HCS12_CodeWarrior_banked/serial/serial.c +++ /dev/null @@ -1,177 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER for port 1. - -Note that this driver is written to test the RTOS port and is not intended -to represent an optimised solution. */ - -/* Processor Expert generated includes. */ -#include "com0.h" - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "queue.h" -#include "task.h" - -/* Demo application include files. */ -#include "serial.h" - -/* The queues used to communicate between the task code and the interrupt -service routines. */ -static xQueueHandle xRxedChars; -static xQueueHandle xCharsForTx; - -/* Interrupt identification bits. */ -#define serOVERRUN_INTERRUPT ( 0x08 ) -#define serRX_INTERRUPT ( 0x20 ) -#define serTX_INTERRUPT ( 0x80 ) - -/*-----------------------------------------------------------*/ - - -/* - * Initialise port for interrupt driven communications. - */ -xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) -{ - /* Hardware setup is performed by the Processor Expert generated code. - This function just creates the queues used to communicate between the - interrupt code and the task code - then sets the required baud rate. */ - - xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); - xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); - - COM0_SetBaudRateMode( ( portCHAR ) ulWantedBaud ); - - return NULL; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) -{ - /* Get the next character from the buffer queue. Return false if no characters - are available, or arrive before xBlockTime expires. */ - if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) - { - return pdTRUE; - } - else - { - return pdFALSE; - } -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) -{ - /* Place the character in the queue of characters to be transmitted. */ - if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) - { - return pdFAIL; - } - - /* Turn on the Tx interrupt so the ISR will remove the character from the - queue and send it. This does not need to be in a critical section as - if the interrupt has already removed the character the next interrupt - will simply turn off the Tx interrupt again. */ - SCI0CR2_SCTIE = 1;; - - return pdPASS; -} -/*-----------------------------------------------------------*/ - -void vSerialClose( xComPortHandle xPort ) -{ - /* Not supported. */ - ( void ) xPort; -} -/*-----------------------------------------------------------*/ - - -/* - * Interrupt service routine for the serial port. Must be in non-banked - * memory. - */ - -#pragma CODE_SEG __NEAR_SEG NON_BANKED - -__interrupt void vCOM0_ISR( void ) -{ -volatile unsigned portCHAR ucByte, ucStatus; -portBASE_TYPE xTaskWokenByPost = pdFALSE, xTaskWokenByTx = pdFALSE; - - /* What caused the interrupt? */ - ucStatus = SCI0SR1; - - if( ucStatus & serOVERRUN_INTERRUPT ) - { - /* The interrupt was caused by an overrun. Clear the error by reading - the data register. */ - ucByte = SCI0DRL; - } - - if( ucStatus & serRX_INTERRUPT ) - { - /* The interrupt was caused by a character being received. - Read the received byte. */ - ucByte = SCI0DRL; - - /* Post the character onto the queue of received characters - noting - whether or not this wakes a task. */ - xTaskWokenByPost = xQueueSendFromISR( xRxedChars, ( void * ) &ucByte, pdFALSE ); - } - - if( ( ucStatus & serTX_INTERRUPT ) && ( SCI0CR2_SCTIE ) ) - { - /* The interrupt was caused by a character being transmitted. */ - if( xQueueReceiveFromISR( xCharsForTx, ( void * ) &ucByte, &xTaskWokenByTx ) == pdTRUE ) - { - /* Clear the SCRF bit. */ - SCI0DRL = ucByte; - } - else - { - /* Disable transmit interrupt */ - SCI0CR2_SCTIE = 0; - } - } - - if( ( xTaskWokenByPost ) || ( xTaskWokenByTx ) ) - { - portYIELD(); - } -} - -#pragma CODE_SEG DEFAULT - diff --git a/Demo/HCS12_CodeWarrior_small/CODE/ButtonInterrupt.C b/Demo/HCS12_CodeWarrior_small/CODE/ButtonInterrupt.C deleted file mode 100644 index cb2e67ac5..000000000 --- a/Demo/HCS12_CodeWarrior_small/CODE/ButtonInterrupt.C +++ /dev/null @@ -1,117 +0,0 @@ -/** ################################################################### -** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. -** Filename : ButtonInterrupt.C -** Project : RTOSDemo -** Processor : MC9S12C32CFU -** Beantype : ExtInt -** Version : Bean 02.025, Driver 01.06, CPU db: 2.87.276 -** Compiler : Metrowerks HC12 C Compiler -** Date/Time : 19/05/2005, 19:02 -** Abstract : -** This bean "ExtInt" implements an external -** interrupt, its control methods and interrupt/event -** handling procedure. -** The bean uses one pin which generates interrupt on -** selected edge. -** Settings : -** Interrupt name : INT_PortP -** User handling procedure : ButtonInterrupt_OnInterrupt -** -** Used pin : -** ---------------------------------------------------- -** Number (on package) | Name -** ---------------------------------------------------- -** 4 | PP0_PWM0_KWP0 -** ---------------------------------------------------- -** -** Port name : P -** -** Bit number (in port) : 0 -** Bit mask of the port : 1 -** -** Signal edge/level : falling -** Priority : 1 -** Pull option : up -** Initial state : Disabled -** -** Edge register : PPSP [605] -** Priority register : HPRIO [31] -** Enable register : PIEP [606] -** Request register : PIFP [607] -** -** Port data register : PTP [600] -** Port control register : DDRP [602] -** Contents : -** Enable - void ButtonInterrupt_Enable(void); -** -** (c) Copyright UNIS, spol. s r.o. 1997-2002 -** UNIS, spol. s r.o. -** Jundrovska 33 -** 624 00 Brno -** Czech Republic -** http : www.processorexpert.com -** mail : info@processorexpert.com -** ###################################################################*/ - - -/* MODULE ButtonInterrupt. */ - -#include "ButtonInterrupt.h" -/*Including shared modules, which are used for all project*/ -#include "PE_Types.h" -#include "PE_Error.h" -#include "PE_Const.h" -#include "IO_Map.h" -#include "PE_Timer.h" -#include "Events.h" -#include "Cpu.h" - -/* Definition of DATA and CODE segments for this bean. User can specify where - these segments will be located on "Build options" tab of the selected CPU bean. */ -#pragma DATA_SEG ButtonInterrupt_DATA /* Data section for this module. */ -#pragma CODE_SEG ButtonInterrupt_CODE /* Code section for this module. */ - -/* -** =================================================================== -** Method : ButtonInterrupt_Enable (bean ExtInt) -** -** Description : -** Enable the bean - the external events are accepted. -** Parameters : None -** Returns : Nothing -** =================================================================== -*/ -void ButtonInterrupt_Enable(void) -{ - PIFP = 1; /* Clear flag */ - PIEP_PIEP0 = 1; /* Enable interrupt */ -} - -/* -** =================================================================== -** Method : ButtonInterrupt_Interrupt (bean ExtInt) -** -** Description : -** This method is internal. It is used by Processor Expert -** only. -** =================================================================== -*/ -#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */ -__interrupt void ButtonInterrupt_Interrupt(void) -{ - PIFP = 1; /* Clear flag */ - ButtonInterrupt_OnInterrupt(); -} - -#pragma CODE_SEG ButtonInterrupt_CODE /* Code section for this module. */ - -/* END ButtonInterrupt. */ - -/* -** ################################################################### -** -** This file was created by UNIS Processor Expert 03.33 for -** the Motorola HCS12 series of microcontrollers. -** -** ################################################################### -*/ diff --git a/Demo/HCS12_CodeWarrior_small/CODE/ButtonInterrupt.H b/Demo/HCS12_CodeWarrior_small/CODE/ButtonInterrupt.H deleted file mode 100644 index c23f5160b..000000000 --- a/Demo/HCS12_CodeWarrior_small/CODE/ButtonInterrupt.H +++ /dev/null @@ -1,109 +0,0 @@ -/** ################################################################### -** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. -** Filename : ButtonInterrupt.H -** Project : RTOSDemo -** Processor : MC9S12C32CFU -** Beantype : ExtInt -** Version : Bean 02.025, Driver 01.06, CPU db: 2.87.276 -** Compiler : Metrowerks HC12 C Compiler -** Date/Time : 19/05/2005, 19:02 -** Abstract : -** This bean "ExtInt" implements an external -** interrupt, its control methods and interrupt/event -** handling procedure. -** The bean uses one pin which generates interrupt on -** selected edge. -** Settings : -** Interrupt name : INT_PortP -** User handling procedure : ButtonInterrupt_OnInterrupt -** -** Used pin : -** ---------------------------------------------------- -** Number (on package) | Name -** ---------------------------------------------------- -** 4 | PP0_PWM0_KWP0 -** ---------------------------------------------------- -** -** Port name : P -** -** Bit number (in port) : 0 -** Bit mask of the port : 1 -** -** Signal edge/level : falling -** Priority : 1 -** Pull option : up -** Initial state : Disabled -** -** Edge register : PPSP [605] -** Priority register : HPRIO [31] -** Enable register : PIEP [606] -** Request register : PIFP [607] -** -** Port data register : PTP [600] -** Port control register : DDRP [602] -** Contents : -** Enable - void ButtonInterrupt_Enable(void); -** -** (c) Copyright UNIS, spol. s r.o. 1997-2002 -** UNIS, spol. s r.o. -** Jundrovska 33 -** 624 00 Brno -** Czech Republic -** http : www.processorexpert.com -** mail : info@processorexpert.com -** ###################################################################*/ - -#ifndef __ButtonInterrupt_H -#define __ButtonInterrupt_H - -/* MODULE ButtonInterrupt. */ - -/*Including shared modules, which are used in the whole project*/ -#include "PE_Types.h" -#include "PE_Error.h" -#include "PE_Const.h" -#include "IO_Map.h" -#include "PE_Timer.h" -#include "Events.h" -#include "Cpu.h" - -#pragma CODE_SEG ButtonInterrupt_CODE /* Code section for this module. */ - -void ButtonInterrupt_Enable(void); -/* -** =================================================================== -** Method : ButtonInterrupt_Enable (bean ExtInt) -** -** Description : -** Enable the bean - the external events are accepted. -** Parameters : None -** Returns : Nothing -** =================================================================== -*/ - -#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */ -__interrupt void ButtonInterrupt_Interrupt(void); -#pragma CODE_SEG ButtonInterrupt_CODE /* Code section for this module. */ -/* -** =================================================================== -** Method : ButtonInterrupt_Interrupt (bean ExtInt) -** -** Description : -** This method is internal. It is used by Processor Expert -** only. -** =================================================================== -*/ - -#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */ - -/* END ButtonInterrupt. */ - -#endif /* __ButtonInterrupt_H*/ -/* -** ################################################################### -** -** This file was created by UNIS Processor Expert 03.33 for -** the Motorola HCS12 series of microcontrollers. -** -** ################################################################### -*/ diff --git a/Demo/HCS12_CodeWarrior_small/CODE/Byte1.C b/Demo/HCS12_CodeWarrior_small/CODE/Byte1.C deleted file mode 100644 index 5a5dc9b50..000000000 --- a/Demo/HCS12_CodeWarrior_small/CODE/Byte1.C +++ /dev/null @@ -1,144 +0,0 @@ -/** ################################################################### -** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. -** Filename : Byte1.C -** Project : RTOSDemo -** Processor : MC9S12C32CFU -** Beantype : ByteIO -** Version : Bean 02.019, Driver 01.03, CPU db: 2.87.276 -** Compiler : Metrowerks HC12 C Compiler -** Date/Time : 10/05/2005, 11:49 -** Abstract : -** This bean "ByteIO" implements an one-byte input/output. -** It uses one 8-bit port. -** Note: This bean is set to work in Output direction only. -** Methods of this bean are mostly implemented as a macros -** (if supported by target langauage and compiler). -** Settings : -** Port name : B -** -** Initial direction : Output (direction cannot be changed) -** Initial output value : 0 = 000H -** Initial pull option : off -** -** 8-bit data register : PORTB [1] -** 8-bit control register : DDRB [3] -** -** ---------------------------------------------------- -** Bit | Pin | Name -** ---------------------------------------------------- -** 0 | 16 | PB0_ADDR0_DATA0 -** 1 | 17 | PB1_ADDR1_DATA1 -** 2 | 18 | PB2_ADDR2_DATA2 -** 3 | 19 | PB3_ADDR3_DATA3 -** 4 | 20 | PB4_ADDR4_DATA4 -** 5 | 21 | PB5_ADDR5_DATA5 -** 6 | 22 | PB6_ADDR6_DATA6 -** 7 | 23 | PB7_ADDR7_DATA7 -** ---------------------------------------------------- -** Contents : -** PutBit - void Byte1_PutBit(byte Bit,bool Val); -** NegBit - void Byte1_NegBit(byte Bit); -** -** (c) Copyright UNIS, spol. s r.o. 1997-2002 -** UNIS, spol. s r.o. -** Jundrovska 33 -** 624 00 Brno -** Czech Republic -** http : www.processorexpert.com -** mail : info@processorexpert.com -** ###################################################################*/ - - -/* MODULE Byte1. */ - -#include "Byte1.h" -/*Including shared modules, which are used for all project*/ -#include "PE_Types.h" -#include "PE_Error.h" -#include "PE_Const.h" -#include "IO_Map.h" - -#include "Cpu.h" - -/* Definition of DATA and CODE segments for this bean. User can specify where - these segments will be located on "Build options" tab of the selected CPU bean. */ -#pragma DATA_SEG Byte1_DATA /* Data section for this module. */ -#pragma CODE_SEG Byte1_CODE /* Code section for this module. */ - -/* -** =================================================================== -** Method : Byte1_GetMsk (bean ByteIO) -** -** Description : -** This method is internal. It is used by Processor Expert -** only. -** =================================================================== -*/ -byte Byte1_Table[8]={ 1, 2, 4, 8, 16, 32, 64, 128 }; /* Table of mask constants */ - -byte Byte1_GetMsk(byte Value) -{ - return((Value<8)?Byte1_Table[Value]:0); /* Return appropriate bit mask */ -} - -/* -** =================================================================== -** Method : Byte1_PutBit (bean ByteIO) -** -** Description : -** This method writes the new value to the specified bit -** of the output value. -** Parameters : -** NAME - DESCRIPTION -** Bitnum - Number of the bit (0 to 7) -** Val - New value of the bit (FALSE or TRUE) -** FALSE = "0" or "Low", TRUE = "1" or "High" -** Returns : Nothing -** =================================================================== -*/ -void Byte1_PutBit(byte BitNum, byte Value) -{ - byte Mask=Byte1_GetMsk(BitNum); /* Temporary variable - bit mask */ - - if (Mask) /* Is bit mask correct? */ - if (Value) { /* Is it one to be written? */ - PORTB |= Mask; /* Set appropriate bit on port */ - } - else { /* Is it zero to be written? */ - PORTB &= ~Mask; /* Clear appropriate bit on port */ - } -} - -/* -** =================================================================== -** Method : Byte1_NegBit (bean ByteIO) -** -** Description : -** This method negates (invertes) the specified bit of the -** output value. -** Parameters : -** NAME - DESCRIPTION -** Bit - Number of the bit to invert (0 to 7) -** Returns : Nothing -** =================================================================== -*/ -void Byte1_NegBit(byte BitNum) -{ - byte Mask=Byte1_GetMsk(BitNum); /* Temporary variable - bit mask */ - - if (Mask) { /* Is bit mask correct? */ - PORTB ^= Mask; /* Negate appropriate bit on port */ - } -} - - -/* END Byte1. */ - -/* -** ################################################################### -** -** This file was created by UNIS Processor Expert 03.33 for -** the Motorola HCS12 series of microcontrollers. -** -** ################################################################### -*/ diff --git a/Demo/HCS12_CodeWarrior_small/CODE/Byte1.H b/Demo/HCS12_CodeWarrior_small/CODE/Byte1.H deleted file mode 100644 index c33dd528f..000000000 --- a/Demo/HCS12_CodeWarrior_small/CODE/Byte1.H +++ /dev/null @@ -1,110 +0,0 @@ -/** ################################################################### -** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. -** Filename : Byte1.H -** Project : RTOSDemo -** Processor : MC9S12C32CFU -** Beantype : ByteIO -** Version : Bean 02.019, Driver 01.03, CPU db: 2.87.276 -** Compiler : Metrowerks HC12 C Compiler -** Date/Time : 10/05/2005, 11:49 -** Abstract : -** This bean "ByteIO" implements an one-byte input/output. -** It uses one 8-bit port. -** Note: This bean is set to work in Output direction only. -** Methods of this bean are mostly implemented as a macros -** (if supported by target langauage and compiler). -** Settings : -** Port name : B -** -** Initial direction : Output (direction cannot be changed) -** Initial output value : 0 = 000H -** Initial pull option : off -** -** 8-bit data register : PORTB [1] -** 8-bit control register : DDRB [3] -** -** ---------------------------------------------------- -** Bit | Pin | Name -** ---------------------------------------------------- -** 0 | 16 | PB0_ADDR0_DATA0 -** 1 | 17 | PB1_ADDR1_DATA1 -** 2 | 18 | PB2_ADDR2_DATA2 -** 3 | 19 | PB3_ADDR3_DATA3 -** 4 | 20 | PB4_ADDR4_DATA4 -** 5 | 21 | PB5_ADDR5_DATA5 -** 6 | 22 | PB6_ADDR6_DATA6 -** 7 | 23 | PB7_ADDR7_DATA7 -** ---------------------------------------------------- -** Contents : -** PutBit - void Byte1_PutBit(byte Bit,bool Val); -** NegBit - void Byte1_NegBit(byte Bit); -** -** (c) Copyright UNIS, spol. s r.o. 1997-2002 -** UNIS, spol. s r.o. -** Jundrovska 33 -** 624 00 Brno -** Czech Republic -** http : www.processorexpert.com -** mail : info@processorexpert.com -** ###################################################################*/ - -#ifndef __Byte1_H -#define __Byte1_H - -/* MODULE Byte1. */ - -/*Including shared modules, which are used in the whole project*/ -#include "PE_Types.h" -#include "PE_Error.h" -#include "PE_Const.h" -#include "IO_Map.h" - -#include "Cpu.h" - -#pragma CODE_SEG Byte1_CODE /* Code section for this module. */ - -/* -** =================================================================== -** Method : Byte1_PutBit (bean ByteIO) -** -** Description : -** This method writes the new value to the specified bit -** of the output value. -** Parameters : -** NAME - DESCRIPTION -** BitNum - Number of the bit (0 to 7) -** Val - New value of the bit (FALSE or TRUE) -** FALSE = "0" or "Low", TRUE = "1" or "High" -** Returns : Nothing -** =================================================================== -*/ -void Byte1_PutBit(byte BitNum, byte Value); - -/* -** =================================================================== -** Method : Byte1_NegBit (bean ByteIO) -** -** Description : -** This method negates (invertes) the specified bit of the -** output value. -** Parameters : -** NAME - DESCRIPTION -** BitNum - Number of the bit to invert (0 to 7) -** Returns : Nothing -** =================================================================== -*/ -void Byte1_NegBit(byte BitNum); - -#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */ - -/* END Byte1. */ - -#endif /* __Byte1_H*/ -/* -** ################################################################### -** -** This file was created by UNIS Processor Expert 03.33 for -** the Motorola HCS12 series of microcontrollers. -** -** ################################################################### -*/ diff --git a/Demo/HCS12_CodeWarrior_small/CODE/Copy of Vectors.c b/Demo/HCS12_CodeWarrior_small/CODE/Copy of Vectors.c deleted file mode 100644 index 38854b315..000000000 --- a/Demo/HCS12_CodeWarrior_small/CODE/Copy of Vectors.c +++ /dev/null @@ -1,115 +0,0 @@ -/** ################################################################### -** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. -** Filename : Cpu.C -** Project : RTOSDemo -** Processor : MC9S12C32CFU -** Beantype : MC9S12C32_80 -** Version : Bean 01.002, Driver 01.09, CPU db: 2.87.276 -** Compiler : Metrowerks HC12 C Compiler -** Date/Time : 17/05/2005, 18:22 -** Abstract : -** This bean "MC9S12C32_80" implements properties, methods, -** and events of the CPU. -** Settings : -** -** Contents : -** EnableInt - void Cpu_EnableInt(void); -** DisableInt - void Cpu_DisableInt(void); -** SetWaitMode - void Cpu_SetWaitMode(void); -** SetStopMode - void Cpu_SetStopMode(void); -** -** (c) Copyright UNIS, spol. s r.o. 1997-2002 -** UNIS, spol. s r.o. -** Jundrovska 33 -** 624 00 Brno -** Czech Republic -** http : www.processorexpert.com -** mail : info@processorexpert.com -** ###################################################################*/ - - -#include "Cpu.h" -#include "Byte1.h" -#include "TickTimer.h" -#include "ButtonInterrupt.h" - -extern void near _EntryPoint(void); /* Startup routine */ -extern void near vPortTickInterrupt( void ); -extern void near vPortYield( void ); -extern void near vButtonPush( void ); - -typedef void (*near tIsrFunc)(void); -const tIsrFunc _vect[] @0xFF80 = { /* Interrupt table */ - Cpu_Interrupt, /* 0 Default (unused) interrupt */ - Cpu_Interrupt, /* 1 Default (unused) interrupt */ - Cpu_Interrupt, /* 2 Default (unused) interrupt */ - Cpu_Interrupt, /* 3 Default (unused) interrupt */ - Cpu_Interrupt, /* 4 Default (unused) interrupt */ - Cpu_Interrupt, /* 5 Default (unused) interrupt */ - Cpu_Interrupt, /* 6 Default (unused) interrupt */ - vButtonPush, /* 7 Default (unused) interrupt */ - Cpu_Interrupt, /* 8 Default (unused) interrupt */ - Cpu_Interrupt, /* 9 Default (unused) interrupt */ - Cpu_Interrupt, /* 10 Default (unused) interrupt */ - Cpu_Interrupt, /* 11 Default (unused) interrupt */ - Cpu_Interrupt, /* 12 Default (unused) interrupt */ - Cpu_Interrupt, /* 13 Default (unused) interrupt */ - Cpu_Interrupt, /* 14 Default (unused) interrupt */ - Cpu_Interrupt, /* 15 Default (unused) interrupt */ - Cpu_Interrupt, /* 16 Default (unused) interrupt */ - Cpu_Interrupt, /* 17 Default (unused) interrupt */ - Cpu_Interrupt, /* 18 Default (unused) interrupt */ - Cpu_Interrupt, /* 19 Default (unused) interrupt */ - Cpu_Interrupt, /* 20 Default (unused) interrupt */ - Cpu_Interrupt, /* 21 Default (unused) interrupt */ - Cpu_Interrupt, /* 22 Default (unused) interrupt */ - Cpu_Interrupt, /* 23 Default (unused) interrupt */ - Cpu_Interrupt, /* 24 Default (unused) interrupt */ - Cpu_Interrupt, /* 25 Default (unused) interrupt */ - Cpu_Interrupt, /* 26 Default (unused) interrupt */ - Cpu_Interrupt, /* 27 Default (unused) interrupt */ - Cpu_Interrupt, /* 28 Default (unused) interrupt */ - Cpu_Interrupt, /* 29 Default (unused) interrupt */ - Cpu_Interrupt, /* 30 Default (unused) interrupt */ - Cpu_Interrupt, /* 31 Default (unused) interrupt */ - Cpu_Interrupt, /* 32 Default (unused) interrupt */ - Cpu_Interrupt, /* 33 Default (unused) interrupt */ - Cpu_Interrupt, /* 34 Default (unused) interrupt */ - Cpu_Interrupt, /* 35 Default (unused) interrupt */ - Cpu_Interrupt, /* 36 Default (unused) interrupt */ - Cpu_Interrupt, /* 37 Default (unused) interrupt */ - Cpu_Interrupt, /* 38 Default (unused) interrupt */ - Cpu_Interrupt, /* 39 Default (unused) interrupt */ - Cpu_Interrupt, /* 40 Default (unused) interrupt */ - Cpu_Interrupt, /* 41 Default (unused) interrupt */ - Cpu_Interrupt, /* 42 Default (unused) interrupt */ - Cpu_Interrupt, /* 43 Default (unused) interrupt */ - Cpu_Interrupt, /* 44 Default (unused) interrupt */ - Cpu_Interrupt, /* 45 Default (unused) interrupt */ - Cpu_Interrupt, /* 46 Default (unused) interrupt */ - Cpu_Interrupt, /* 47 Default (unused) interrupt */ - Cpu_Interrupt, /* 48 Default (unused) interrupt */ - Cpu_Interrupt, /* 49 Default (unused) interrupt */ - Cpu_Interrupt, /* 50 Default (unused) interrupt */ - Cpu_Interrupt, /* 51 Default (unused) interrupt */ - Cpu_Interrupt, /* 52 Default (unused) interrupt */ - Cpu_Interrupt, /* 53 Default (unused) interrupt */ - Cpu_Interrupt, /* 54 Default (unused) interrupt */ - vPortTickInterrupt, - Cpu_Interrupt, /* 56 Default (unused) interrupt */ - Cpu_Interrupt, /* 57 Default (unused) interrupt */ - Cpu_Interrupt, /* 58 Default (unused) interrupt */ - vPortYield, /* 59 Default (unused) interrupt */ - Cpu_Interrupt, /* 60 Default (unused) interrupt */ - Cpu_Interrupt, /* 61 Default (unused) interrupt */ - Cpu_Interrupt, /* 62 Default (unused) interrupt */ - _EntryPoint /* Reset vector */ - }; -/* -** ################################################################### -** -** This file was created by UNIS Processor Expert 03.33 for -** the Motorola HCS12 series of microcontrollers. -** -** ################################################################### -*/ \ No newline at end of file diff --git a/Demo/HCS12_CodeWarrior_small/CODE/Cpu.C b/Demo/HCS12_CodeWarrior_small/CODE/Cpu.C deleted file mode 100644 index 970d653b8..000000000 --- a/Demo/HCS12_CodeWarrior_small/CODE/Cpu.C +++ /dev/null @@ -1,233 +0,0 @@ -/** ################################################################### -** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. -** Filename : Cpu.C -** Project : RTOSDemo -** Processor : MC9S12C32CFU -** Beantype : MC9S12C32_80 -** Version : Bean 01.002, Driver 01.09, CPU db: 2.87.276 -** Compiler : Metrowerks HC12 C Compiler -** Date/Time : 18/06/2005, 18:00 -** Abstract : -** This bean "MC9S12C32_80" implements properties, methods, -** and events of the CPU. -** Settings : -** -** Contents : -** EnableInt - void Cpu_EnableInt(void); -** DisableInt - void Cpu_DisableInt(void); -** SetWaitMode - void Cpu_SetWaitMode(void); -** SetStopMode - void Cpu_SetStopMode(void); -** -** (c) Copyright UNIS, spol. s r.o. 1997-2002 -** UNIS, spol. s r.o. -** Jundrovska 33 -** 624 00 Brno -** Czech Republic -** http : www.processorexpert.com -** mail : info@processorexpert.com -** ###################################################################*/ - -/* MODULE Cpu. */ - -#include "Byte1.h" -#include "TickTimer.h" -#include "ButtonInterrupt.h" -#include "PE_Types.h" -#include "PE_Error.h" -#include "PE_Const.h" -#include "IO_Map.h" -#include "PE_Timer.h" -#include "Events.h" -#include "Cpu.h" - -#define CGM_DELAY 3071UL - - -/* Global variables */ -volatile byte CCR_reg; /* Current CCR reegister */ -byte CpuMode = HIGH_SPEED; /* Current speed mode */ - - -/* -** =================================================================== -** Method : Cpu_Interrupt (bean MC9S12C32_80) -** -** Description : -** This method is internal. It is used by Processor Expert -** only. -** =================================================================== -*/ -#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */ - -__interrupt void Cpu_Interrupt(void) -{ -} - -#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */ - -/* -** =================================================================== -** Method : Cpu_DisableInt (bean MC9S12C32_80) -** -** Description : -** Disable maskable interrupts -** Parameters : None -** Returns : Nothing -** =================================================================== -*/ -/* -void Cpu_DisableInt(void) - -** This method is implemented as macro in the header module. ** -*/ - -/* -** =================================================================== -** Method : Cpu_EnableInt (bean MC9S12C32_80) -** -** Description : -** Enable maskable interrupts -** Parameters : None -** Returns : Nothing -** =================================================================== -*/ -/* -void Cpu_EnableInt(void) - -** This method is implemented as macro in the header module. ** -*/ - -/* -** =================================================================== -** Method : Cpu_SetStopMode (bean MC9S12C32_80) -** -** Description : -** Set low power mode - Stop mode. For more information -** about the stop mode see documentation of this CPU. -** Parameters : None -** Returns : Nothing -** =================================================================== -*/ -/* -void Cpu_SetStopMode(void) - -** This method is implemented as macro in the header module. ** -*/ - -/* -** =================================================================== -** Method : Cpu_SetWaitMode (bean MC9S12C32_80) -** -** Description : -** Set low power mode - Wait mode. For more information -** about the wait mode see documentation of this CPU. -** Release from Watch mode: Reset or interrupt -** Parameters : None -** Returns : Nothing -** =================================================================== -*/ -/* -void Cpu_SetWaitMode(void) - -** This method is implemented as macro in the header module. ** -*/ - -/* -** =================================================================== -** Method : _EntryPoint (bean MC9S12C32_80) -** -** Description : -** This method is internal. It is used by Processor Expert -** only. -** =================================================================== -*/ -extern void _Startup(void); /* Forward declaration of external startup function declared in file Start12.c */ -#define INITRG_ADR 0x0011 /* Register map position register */ -#pragma NO_FRAME -#pragma NO_EXIT -void _EntryPoint(void) -{ - /*** ### MC9S12C32_80 "Cpu" init code ... ***/ - /*** PE initialization code after reset ***/ - /* Initialization of the registers INITRG, INITRM, INITEE is done to protect them to be written accidentally later by the application */ - *(byte*)INITRG_ADR = 0; /* Set the register map position */ - asm nop; /* nop instruction */ - INITRM=8; /* Set the RAM map position */ - /* MISC: ??=0,??=0,??=0,??=0,EXSTR1=0,EXSTR0=0,ROMHM=0,ROMON=1 */ - MISC=1; - /* System clock initialization */ - CLKSEL=0; - CLKSEL_PLLSEL = 0; /* Select clock source from XTAL */ - PLLCTL_PLLON = 0; /* Disable the PLL */ - SYNR = 23; /* Set the multiplier register */ - REFDV = 15; /* Set the divider register */ - PLLCTL = 192; - PLLCTL_PLLON = 1; /* Enable the PLL */ - while(!CRGFLG_LOCK); /* Wait */ - CLKSEL_PLLSEL = 1; /* Select clock source from PLL */ - /*** End of PE initialization code after reset ***/ - - __asm jmp _Startup; /* Jump to C startup code */ -} - -/* -** =================================================================== -** Method : PE_low_level_init (bean MC9S12C32_80) -** -** Description : -** This method is internal. It is used by Processor Expert -** only. -** =================================================================== -*/ -void PE_low_level_init(void) -{ - /* Common initialization of the CPU registers */ -/* TSCR1: TEN=0,TSWAI=0,TSFRZ=1 */ - output( TSCR1, input( TSCR1 ) & ~192 | 32 ); -/* TCTL2: OM0=0,OL0=0 */ - output( TCTL2, input( TCTL2 ) & ~3 ); -/* TCTL1: OM7=0,OL7=0 */ - output( TCTL1, input( TCTL1 ) & ~192 ); -/* TIE: C0I=0 */ - output( TIE, input( TIE ) & ~1 ); -/* TTOV: TOV0=0 */ - output( TTOV, input( TTOV ) & ~1 ); -/* TSCR2: TOI=0,TCRE=1 */ - output( TSCR2, input( TSCR2 ) & ~128 | 8 ); -/* TIOS: IOS7=1,IOS0=1 */ - output( TIOS, input( TIOS ) | 129 ); -/* PPSP: PPSP0=0 */ - output( PPSP, input( PPSP ) & ~1 ); -/* PERP: PERP0=1 */ - output( PERP, input( PERP ) | 1 ); -/* DDRP: DDRP0=0 */ - output( DDRP, input( DDRP ) & ~1 ); -/* PWMCTL: PSWAI=0,PFRZ=0 */ - output( PWMCTL, input( PWMCTL ) & ~12 ); -/* PWMSDN: PWMIF=0,PWMIE=0,PWMRSTRT=0,PWMLVL=0,??=0,PWM7IN=0,PWM7INL=0,PWM7ENA=0 */ - output( PWMSDN, 0 ); - /* ### MC9S12C32_80 "Cpu" init code ... */ - /* ### ByteIO "Byte1" init code ... */ - PORTB = 0; /* Prepare value for output */ - DDRB = 255; /* Set direction to output */ - /* ### TimerInt "TickTimer" init code ... */ - TickTimer_Init(); - /* ### External interrupt "ButtonInterrupt" init code ... */ - PIEP_PIEP0 = 0; /* Disable interrupt */ - /* Common peripheral initialization - ENABLE */ -/* TSCR1: TEN=1 */ - output( TSCR1, input( TSCR1 ) | 128 ); - INTCR_IRQEN = 0; /* Disable the IRQ interrupt. IRQ interrupt is enabled after CPU reset by default. */ - __DI(); /* Disable interrupts */ -} - -/* END Cpu. */ - -/* -** ################################################################### -** -** This file was created by UNIS Processor Expert 03.33 for -** the Motorola HCS12 series of microcontrollers. -** -** ################################################################### -*/ diff --git a/Demo/HCS12_CodeWarrior_small/CODE/Cpu.H b/Demo/HCS12_CodeWarrior_small/CODE/Cpu.H deleted file mode 100644 index a08230e92..000000000 --- a/Demo/HCS12_CodeWarrior_small/CODE/Cpu.H +++ /dev/null @@ -1,140 +0,0 @@ -/** ################################################################### -** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. -** Filename : Cpu.H -** Project : RTOSDemo -** Processor : MC9S12C32CFU -** Beantype : MC9S12C32_80 -** Version : Bean 01.002, Driver 01.09, CPU db: 2.87.276 -** Compiler : Metrowerks HC12 C Compiler -** Date/Time : 17/05/2005, 08:36 -** Abstract : -** This bean "MC9S12C32_80" implements properties, methods, -** and events of the CPU. -** Settings : -** -** Contents : -** EnableInt - void Cpu_EnableInt(void); -** DisableInt - void Cpu_DisableInt(void); -** SetWaitMode - void Cpu_SetWaitMode(void); -** SetStopMode - void Cpu_SetStopMode(void); -** -** (c) Copyright UNIS, spol. s r.o. 1997-2002 -** UNIS, spol. s r.o. -** Jundrovska 33 -** 624 00 Brno -** Czech Republic -** http : www.processorexpert.com -** mail : info@processorexpert.com -** ###################################################################*/ - -#ifndef __Cpu -#define __Cpu - -/* Active configuration define symbol */ -#define PEcfg_80pin 1 - -/*Include shared modules, which are used for whole project*/ -#include "PE_Types.h" -#include "PE_Error.h" -#include "PE_Const.h" -#include "IO_Map.h" -#include "PE_Timer.h" - -/* MODULE Cpu. */ - - -/* Global variables */ -extern volatile byte CCR_reg; /* Current CCR reegister */ -extern byte CpuMode; /* Current speed mode */ - - -#define Cpu_SetStopMode() __asm("STOP") /* Set STOP mode */ -/* -** =================================================================== -** Method : Cpu_SetStopMode (bean MC9S12C32_80) -** -** Description : -** Set low power mode - Stop mode. For more information -** about the stop mode see documentation of this CPU. -** Parameters : None -** Returns : Nothing -** =================================================================== -*/ - -#define Cpu_SetWaitMode() __asm("WAIT") /* Set WAIT mode */ -/* -** =================================================================== -** Method : Cpu_SetWaitMode (bean MC9S12C32_80) -** -** Description : -** Set low power mode - Wait mode. For more information -** about the wait mode see documentation of this CPU. -** Release from Watch mode: Reset or interrupt -** Parameters : None -** Returns : Nothing -** =================================================================== -*/ - - - -#define Cpu_DisableInt() __DI() /* Disable interrupts */ -/* -** =================================================================== -** Method : Cpu_DisableInt (bean MC9S12C32_80) -** -** Description : -** Disable maskable interrupts -** Parameters : None -** Returns : Nothing -** =================================================================== -*/ - -#define Cpu_EnableInt() __EI() /* Enable interrupts */ -/* -** =================================================================== -** Method : Cpu_EnableInt (bean MC9S12C32_80) -** -** Description : -** Enable maskable interrupts -** Parameters : None -** Returns : Nothing -** =================================================================== -*/ - -#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */ - -__interrupt void Cpu_Interrupt(void); -/* -** =================================================================== -** Method : Cpu_Interrupt (bean MC9S12C32_80) -** -** Description : -** This method is internal. It is used by Processor Expert -** only. -** =================================================================== -*/ - -#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */ - -void PE_low_level_init(void); -/* -** =================================================================== -** Method : PE_low_level_init (bean MC9S12C32_80) -** -** Description : -** This method is internal. It is used by Processor Expert -** only. -** =================================================================== -*/ - -/* END Cpu. */ - -#endif /* ifndef __Cpu */ -/* -** ################################################################### -** -** This file was created by UNIS Processor Expert 03.33 for -** the Motorola HCS12 series of microcontrollers. -** -** ################################################################### -*/ diff --git a/Demo/HCS12_CodeWarrior_small/CODE/Events.C b/Demo/HCS12_CodeWarrior_small/CODE/Events.C deleted file mode 100644 index 6a3f6079a..000000000 --- a/Demo/HCS12_CodeWarrior_small/CODE/Events.C +++ /dev/null @@ -1,87 +0,0 @@ -/** ################################################################### -** Filename : Events.C -** Project : RTOSDemo -** Processor : MC9S12C32CFU -** Beantype : Events -** Version : Driver 01.01 -** Compiler : Metrowerks HC12 C Compiler -** Date/Time : 17/05/2005, 08:36 -** Abstract : -** This is user's event module. -** Put your event handler code here. -** Settings : -** Contents : -** vTaskTickInterrupt - void vTaskTickInterrupt(void); -** -** (c) Copyright UNIS, spol. s r.o. 1997-2002 -** UNIS, spol. s r.o. -** Jundrovska 33 -** 624 00 Brno -** Czech Republic -** http : www.processorexpert.com -** mail : info@processorexpert.com -** ###################################################################*/ -/* MODULE Events */ - - -/*Including used modules for compilling procedure*/ -#include "Cpu.h" -#include "Events.h" -#include "Byte1.h" -#include "TickTimer.h" -#include "ButtonInterrupt.h" - -/*Include shared modules, which are used for whole project*/ -#include "PE_Types.h" -#include "PE_Error.h" -#include "PE_Const.h" -#include "IO_Map.h" -#include "PE_Timer.h" - -/* -** =================================================================== -** Event : vTaskTickInterrupt (module Events) -** -** From bean : TickTimer [TimerInt] -** Description : -** When a timer interrupt occurs this event is called (only -** when the bean is enabled - "Enable" and the events are -** enabled - "EnableEvent"). -** Parameters : None -** Returns : Nothing -** =================================================================== -*/ -void vTaskTickInterrupt(void) -{ - /* Write your code here ... */ -} - - -/* -** =================================================================== -** Event : ButtonInterrupt_OnInterrupt (module Events) -** -** From bean : ButtonInterrupt [ExtInt] -** Description : -** This event is called when the active signal edge/level -** occurs. -** Parameters : None -** Returns : Nothing -** =================================================================== -*/ -void ButtonInterrupt_OnInterrupt(void) -{ - /* place your ButtonInterrupt interrupt procedure body here */ -} - - -/* END Events */ - -/* -** ################################################################### -** -** This file was created by UNIS Processor Expert 03.33 for -** the Motorola HCS12 series of microcontrollers. -** -** ################################################################### -*/ diff --git a/Demo/HCS12_CodeWarrior_small/CODE/Events.H b/Demo/HCS12_CodeWarrior_small/CODE/Events.H deleted file mode 100644 index 23f2c45b4..000000000 --- a/Demo/HCS12_CodeWarrior_small/CODE/Events.H +++ /dev/null @@ -1,74 +0,0 @@ -/** ################################################################### -** Filename : Events.H -** Project : RTOSDemo -** Processor : MC9S12C32CFU -** Beantype : Events -** Version : Driver 01.01 -** Compiler : Metrowerks HC12 C Compiler -** Date/Time : 17/05/2005, 08:36 -** Abstract : -** This is user's event module. -** Put your event handler code here. -** Settings : -** Contents : -** vTaskTickInterrupt - void vTaskTickInterrupt(void); -** -** (c) Copyright UNIS, spol. s r.o. 1997-2002 -** UNIS, spol. s r.o. -** Jundrovska 33 -** 624 00 Brno -** Czech Republic -** http : www.processorexpert.com -** mail : info@processorexpert.com -** ###################################################################*/ - -#ifndef __Events_H -#define __Events_H -/* MODULE Events */ - -#include "PE_Types.h" -#include "PE_Error.h" -#include "PE_Const.h" -#include "IO_Map.h" -#include "PE_Timer.h" - -void vTaskTickInterrupt(void); -/* -** =================================================================== -** Event : vTaskTickInterrupt (module Events) -** -** From bean : TickTimer [TimerInt] -** Description : -** When a timer interrupt occurs this event is called (only -** when the bean is enabled - "Enable" and the events are -** enabled - "EnableEvent"). -** Parameters : None -** Returns : Nothing -** =================================================================== -*/ - - -void ButtonInterrupt_OnInterrupt(void); -/* -** =================================================================== -** Event : ButtonInterrupt_OnInterrupt (module Events) -** -** From bean : ButtonInterrupt [ExtInt] -** Description : -** This event is called when the active signal edge/level -** occurs. -** Parameters : None -** Returns : Nothing -** =================================================================== -*/ -/* END Events */ -#endif /* __Events_H*/ - -/* -** ################################################################### -** -** This file was created by UNIS Processor Expert 03.33 for -** the Motorola HCS12 series of microcontrollers. -** -** ################################################################### -*/ diff --git a/Demo/HCS12_CodeWarrior_small/CODE/IO_Map.C b/Demo/HCS12_CodeWarrior_small/CODE/IO_Map.C deleted file mode 100644 index ad23df3b1..000000000 --- a/Demo/HCS12_CodeWarrior_small/CODE/IO_Map.C +++ /dev/null @@ -1,260 +0,0 @@ -/** ################################################################### -** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. -** Filename : IO_Map.C -** Project : RTOSDemo -** Processor : MC9S12C32CFU -** Beantype : IO_Map -** Version : Driver 01.01 -** Compiler : Metrowerks HC12 C Compiler -** Date/Time : 10/05/2005, 11:11 -** Abstract : -** This bean "IO_Map" implements an IO devices mapping. -** Settings : -** -** Contents : -** No public methods -** -** (c) Copyright UNIS, spol. s r.o. 1997-2002 -** UNIS, spol. s r.o. -** Jundrovska 33 -** 624 00 Brno -** Czech Republic -** http : www.processorexpert.com -** mail : info@processorexpert.com -** ###################################################################*/ -/* Based on CPU DB MC9S12C32_80, version 2.87.264 */ -#include "PE_types.h" -#include "IO_Map.h" - -volatile ARMCOPSTR _ARMCOP; /* CRG COP Timer Arm/Reset Register */ -volatile ATDDIENSTR _ATDDIEN; /* ATD Input Enable Mask Register */ -volatile ATDSTAT0STR _ATDSTAT0; /* A/D Status Register 0 */ -volatile ATDSTAT1STR _ATDSTAT1; /* A/D Status Register 1 */ -volatile BDMCCRSTR _BDMCCR; /* BDM CCR Holding Register */ -volatile BDMINRSTR _BDMINR; /* BDM Internal Register Position Register */ -volatile BDMSTSSTR _BDMSTS; /* BDM Status Register */ -volatile BKP0HSTR _BKP0H; /* First Address High Byte Breakpoint Register */ -volatile BKP0LSTR _BKP0L; /* First Address Low Byte Breakpoint Register */ -volatile BKP0XSTR _BKP0X; /* First Address Memory Expansion Breakpoint Register */ -volatile BKP1HSTR _BKP1H; /* Data (Second Address) High Byte Breakpoint Register */ -volatile BKP1LSTR _BKP1L; /* Data (Second Address) Low Byte Breakpoint Register */ -volatile BKP1XSTR _BKP1X; /* Second Address Memory Expansion Breakpoint Register */ -volatile BKPCT0STR _BKPCT0; /* Breakpoint Control Register 0 */ -volatile BKPCT1STR _BKPCT1; /* Breakpoint Control Register 1 */ -volatile CANBTR0STR _CANBTR0; /* MSCAN Bus Timing Register 0 */ -volatile CANBTR1STR _CANBTR1; /* MSCAN Bus Timing Register 1 */ -volatile CANCTL0STR _CANCTL0; /* MSCAN Control 0 Register */ -volatile CANCTL1STR _CANCTL1; /* MSCAN Control 1 Register */ -volatile CANIDACSTR _CANIDAC; /* MSCAN Identifier Acceptance Control Register */ -volatile CANIDAR0STR _CANIDAR0; /* MSCAN Identifier Acceptance Register 0 */ -volatile CANIDAR1STR _CANIDAR1; /* MSCAN Identifier Acceptance Register 1 */ -volatile CANIDAR2STR _CANIDAR2; /* MSCAN Identifier Acceptance Register 2 */ -volatile CANIDAR3STR _CANIDAR3; /* MSCAN Identifier Acceptance Register 3 */ -volatile CANIDAR4STR _CANIDAR4; /* MSCAN Identifier Acceptance Register 4 */ -volatile CANIDAR5STR _CANIDAR5; /* MSCAN Identifier Acceptance Register 5 */ -volatile CANIDAR6STR _CANIDAR6; /* MSCAN Identifier Acceptance Register 6 */ -volatile CANIDAR7STR _CANIDAR7; /* MSCAN Identifier Acceptance Register 7 */ -volatile CANIDMR0STR _CANIDMR0; /* MSCAN Identifier Mask Register 0 */ -volatile CANIDMR1STR _CANIDMR1; /* MSCAN Identifier Mask Register 1 */ -volatile CANIDMR2STR _CANIDMR2; /* MSCAN Identifier Mask Register 2 */ -volatile CANIDMR3STR _CANIDMR3; /* MSCAN Identifier Mask Register 3 */ -volatile CANIDMR4STR _CANIDMR4; /* MSCAN Identifier Mask Register 4 */ -volatile CANIDMR5STR _CANIDMR5; /* MSCAN Identifier Mask Register 5 */ -volatile CANIDMR6STR _CANIDMR6; /* MSCAN Identifier Mask Register 6 */ -volatile CANIDMR7STR _CANIDMR7; /* MSCAN Identifier Mask Register 7 */ -volatile CANRFLGSTR _CANRFLG; /* MSCAN Receiver Flag Register */ -volatile CANRIERSTR _CANRIER; /* MSCAN Receiver Interrupt Enable Register */ -volatile CANRXDLRSTR _CANRXDLR; /* MSCAN Receive Data Length Register */ -volatile CANRXDSR0STR _CANRXDSR0; /* MSCAN Receive Data Segment Register 0 */ -volatile CANRXDSR1STR _CANRXDSR1; /* MSCAN Receive Data Segment Register 1 */ -volatile CANRXDSR2STR _CANRXDSR2; /* MSCAN Receive Data Segment Register 2 */ -volatile CANRXDSR3STR _CANRXDSR3; /* MSCAN Receive Data Segment Register 3 */ -volatile CANRXDSR4STR _CANRXDSR4; /* MSCAN Receive Data Segment Register 4 */ -volatile CANRXDSR5STR _CANRXDSR5; /* MSCAN Receive Data Segment Register 5 */ -volatile CANRXDSR6STR _CANRXDSR6; /* MSCAN Receive Data Segment Register 6 */ -volatile CANRXDSR7STR _CANRXDSR7; /* MSCAN Receive Data Segment Register 7 */ -volatile CANRXERRSTR _CANRXERR; /* MSCAN Receive Error Counter Register */ -volatile CANRXIDR0STR _CANRXIDR0; /* MSCAN Receive Identifier Register 0 */ -volatile CANRXIDR1STR _CANRXIDR1; /* MSCAN Receive Identifier Register 1 */ -volatile CANRXIDR2STR _CANRXIDR2; /* MSCAN Receive Identifier Register 2 */ -volatile CANRXIDR3STR _CANRXIDR3; /* MSCAN Receive Identifier Register 3 */ -volatile CANTAAKSTR _CANTAAK; /* MSCAN Transmitter Message Abort Control */ -volatile CANTARQSTR _CANTARQ; /* MSCAN Transmitter Message Abort Request */ -volatile CANTBSELSTR _CANTBSEL; /* MSCAN Transmit Buffer Selection */ -volatile CANTFLGSTR _CANTFLG; /* MSCAN Transmitter Flag Register */ -volatile CANTIERSTR _CANTIER; /* MSCAN Transmitter Interrupt Enable Register */ -volatile CANTXDLRSTR _CANTXDLR; /* MSCAN Transmit Data Length Register */ -volatile CANTXDSR0STR _CANTXDSR0; /* MSCAN Transmit Data Segment Register 0 */ -volatile CANTXDSR1STR _CANTXDSR1; /* MSCAN Transmit Data Segment Register 1 */ -volatile CANTXDSR2STR _CANTXDSR2; /* MSCAN Transmit Data Segment Register 2 */ -volatile CANTXDSR3STR _CANTXDSR3; /* MSCAN Transmit Data Segment Register 3 */ -volatile CANTXDSR4STR _CANTXDSR4; /* MSCAN Transmit Data Segment Register 4 */ -volatile CANTXDSR5STR _CANTXDSR5; /* MSCAN Transmit Data Segment Register 5 */ -volatile CANTXDSR6STR _CANTXDSR6; /* MSCAN Transmit Data Segment Register 6 */ -volatile CANTXDSR7STR _CANTXDSR7; /* MSCAN Transmit Data Segment Register 7 */ -volatile CANTXERRSTR _CANTXERR; /* MSCAN Transmit Error Counter Register */ -volatile CANTXIDR0STR _CANTXIDR0; /* MSCAN Transmit Identifier Register 0 */ -volatile CANTXIDR1STR _CANTXIDR1; /* MSCAN Transmit Identifier Register 1 */ -volatile CANTXIDR2STR _CANTXIDR2; /* MSCAN Transmit Identifier Register 2 */ -volatile CANTXIDR3STR _CANTXIDR3; /* MSCAN Transmit Identifier Register 3 */ -volatile CANTXTBPRSTR _CANTXTBPR; /* MSCAN Transmit Buffer Priority */ -volatile CFORCSTR _CFORC; /* Timer Compare Force Register */ -volatile CLKSELSTR _CLKSEL; /* CRG Clock Select Register */ -volatile COPCTLSTR _COPCTL; /* CRG COP Control Register */ -volatile CRGFLGSTR _CRGFLG; /* CRG Flags Register */ -volatile CRGINTSTR _CRGINT; /* CRG Interrupt Enable Register */ -volatile CTCTLSTR _CTCTL; /* CRG Test Control Register */ -volatile CTFLGSTR _CTFLG; /* CRG Test Flags Register */ -volatile DDRADSTR _DDRAD; /* Port AD Data Direction Register */ -volatile DDRESTR _DDRE; /* Port E Data Direction Register */ -volatile DDRJSTR _DDRJ; /* Port J Data Direction Register */ -volatile DDRKSTR _DDRK; /* Port K Data Direction Register */ -volatile DDRMSTR _DDRM; /* Port M Data Direction Register */ -volatile DDRPSTR _DDRP; /* Port P Data Direction Register */ -volatile DDRSSTR _DDRS; /* Port S Data Direction Register */ -volatile DDRTSTR _DDRT; /* Port T Data Direction Register */ -volatile EBICTLSTR _EBICTL; /* External Bus Interface Control */ -volatile FCLKDIVSTR _FCLKDIV; /* Flash Clock Divider Register */ -volatile FCMDSTR _FCMD; /* Flash Command Buffer and Register */ -volatile FCNFGSTR _FCNFG; /* Flash Configuration Register */ -volatile FPROTSTR _FPROT; /* Flash Protection Register */ -volatile FSECSTR _FSEC; /* Flash Security Register */ -volatile FSTATSTR _FSTAT; /* Flash Status Register */ -volatile HPRIOSTR _HPRIO; /* Highest Priority I Interrupt */ -volatile INITEESTR _INITEE; /* Initialization of Internal EEPROM Position Register */ -volatile INITRGSTR _INITRG; /* Initialization of Internal Register Position Register */ -volatile INITRMSTR _INITRM; /* Initialization of Internal RAM Position Register */ -volatile INTCRSTR _INTCR; /* Interrupt Control Register */ -volatile ITCRSTR _ITCR; /* Interrupt Test Control Register */ -volatile ITESTSTR _ITEST; /* Interrupt Test Register */ -volatile MEMSIZ0STR _MEMSIZ0; /* Memory Size Register Zero */ -volatile MEMSIZ1STR _MEMSIZ1; /* Memory Size Register One */ -volatile MISCSTR _MISC; /* Miscellaneous Mapping Control Register */ -volatile MODESTR _MODE; /* Mode Register */ -volatile MODRRSTR _MODRR; /* Module Routing Register */ -volatile MTST0STR _MTST0; /* MTST0 */ -volatile MTST1STR _MTST1; /* MTST1 */ -volatile OC7DSTR _OC7D; /* Output Compare 7 Data Register */ -volatile OC7MSTR _OC7M; /* Output Compare 7 Mask Register */ -volatile PACTLSTR _PACTL; /* 16-Bit Pulse Accumulator A Control Register */ -volatile PAFLGSTR _PAFLG; /* Pulse Accumulator A Flag Register */ -volatile PARTIDHSTR _PARTIDH; /* Part ID Register High */ -volatile PARTIDLSTR _PARTIDL; /* Part ID Register Low */ -volatile PEARSTR _PEAR; /* Port E Assignment Register */ -volatile PERADSTR _PERAD; /* Port AD Pull Device Enable Register */ -volatile PERJSTR _PERJ; /* Port J Pull Device Enable Register */ -volatile PERMSTR _PERM; /* Port M Pull Device Enable Register */ -volatile PERPSTR _PERP; /* Port P Pull Device Enable Register */ -volatile PERSSTR _PERS; /* Port S Pull Device Enable Register */ -volatile PERTSTR _PERT; /* Port T Pull Device Enable Register */ -volatile PIEJSTR _PIEJ; /* Port J Interrupt Enable Register */ -volatile PIEPSTR _PIEP; /* Port P Interrupt Enable Register */ -volatile PIFJSTR _PIFJ; /* Port J Interrupt Flag Register */ -volatile PIFPSTR _PIFP; /* Port P Interrupt Flag Register */ -volatile PLLCTLSTR _PLLCTL; /* CRG PLL Control Register */ -volatile PORTAD0STR _PORTAD0; /* Port AD0 Register */ -volatile PORTESTR _PORTE; /* Port E Register */ -volatile PORTKSTR _PORTK; /* Port K Data Register */ -volatile PPAGESTR _PPAGE; /* Page Index Register */ -volatile PPSADSTR _PPSAD; /* Port AD Polarity Select Register */ -volatile PPSJSTR _PPSJ; /* PortJP Polarity Select Register */ -volatile PPSMSTR _PPSM; /* Port M Polarity Select Register */ -volatile PPSPSTR _PPSP; /* Port P Polarity Select Register */ -volatile PPSSSTR _PPSS; /* Port S Polarity Select Register */ -volatile PPSTSTR _PPST; /* Port T Polarity Select Register */ -volatile PTADSTR _PTAD; /* Port AD I/O Register */ -volatile PTIADSTR _PTIAD; /* Port AD Input Register */ -volatile PTIJSTR _PTIJ; /* Port J Input Register */ -volatile PTIMSTR _PTIM; /* Port M Input */ -volatile PTIPSTR _PTIP; /* Port P Input */ -volatile PTISSTR _PTIS; /* Port S Input */ -volatile PTITSTR _PTIT; /* Port T Input */ -volatile PTJSTR _PTJ; /* Port J I/O Register */ -volatile PTMSTR _PTM; /* Port M I/O Register */ -volatile PTPSTR _PTP; /* Port P I/O Register */ -volatile PTSSTR _PTS; /* Port S I/O Register */ -volatile PTTSTR _PTT; /* Port T I/O Register */ -volatile PUCRSTR _PUCR; /* Pull-Up Control Register */ -volatile PWMCAESTR _PWMCAE; /* PWM Center Align Enable Register */ -volatile PWMCLKSTR _PWMCLK; /* PWM Clock Select Register */ -volatile PWMCTLSTR _PWMCTL; /* PWM Control Register */ -volatile PWMESTR _PWME; /* PWM Enable Register */ -volatile PWMPOLSTR _PWMPOL; /* PWM Polarity Register */ -volatile PWMPRCLKSTR _PWMPRCLK; /* PWM Prescale Clock Select Register */ -volatile PWMSCLASTR _PWMSCLA; /* PWM Scale A Register */ -volatile PWMSCLBSTR _PWMSCLB; /* PWM Scale B Register */ -volatile PWMSDNSTR _PWMSDN; /* PWM Shutdown Register */ -volatile RDRADSTR _RDRAD; /* Port AD Reduced Drive Register */ -volatile RDRIVSTR _RDRIV; /* Reduced Drive of I/O Lines */ -volatile RDRJSTR _RDRJ; /* Port J Reduced Drive Register */ -volatile RDRMSTR _RDRM; /* Port M Reduced Drive Register */ -volatile RDRPSTR _RDRP; /* Port P Reduced Drive Register */ -volatile RDRSSTR _RDRS; /* Port S Reduced Drive Register */ -volatile RDRTSTR _RDRT; /* Port T Reduced Drive Register */ -volatile REFDVSTR _REFDV; /* CRG Reference Divider Register */ -volatile RTICTLSTR _RTICTL; /* CRG RTI Control Register */ -volatile SCICR1STR _SCICR1; /* SCI Control Register 1 */ -volatile SCICR2STR _SCICR2; /* SCI Control Register 2 */ -volatile SCIDRHSTR _SCIDRH; /* SCI Data Register High */ -volatile SCIDRLSTR _SCIDRL; /* SCI Data Register Low */ -volatile SCISR1STR _SCISR1; /* SCI Status Register 1 */ -volatile SCISR2STR _SCISR2; /* SCI Status Register 2 */ -volatile SPIBRSTR _SPIBR; /* SPI Baud Rate Register */ -volatile SPICR1STR _SPICR1; /* SPI Control Register */ -volatile SPICR2STR _SPICR2; /* SPI Control Register 2 */ -volatile SPIDRSTR _SPIDR; /* SPI Data Register */ -volatile SPISRSTR _SPISR; /* SPI Status Register */ -volatile SYNRSTR _SYNR; /* CRG Synthesizer Register */ -volatile TCTL1STR _TCTL1; /* Timer Control Register 1 */ -volatile TCTL2STR _TCTL2; /* Timer Control Register 2 */ -volatile TCTL3STR _TCTL3; /* Timer Control Register 3 */ -volatile TCTL4STR _TCTL4; /* Timer Control Register 4 */ -volatile TFLG1STR _TFLG1; /* Main Timer Interrupt Flag 1 */ -volatile TFLG2STR _TFLG2; /* Main Timer Interrupt Flag 2 */ -volatile TIESTR _TIE; /* Timer Interrupt Enable Register */ -volatile TIOSSTR _TIOS; /* Timer Input Capture/Output Compare Select */ -volatile TSCR1STR _TSCR1; /* Timer System Control Register1 */ -volatile TSCR2STR _TSCR2; /* Timer System Control Register 2 */ -volatile TTOVSTR _TTOV; /* Timer Toggle On Overflow Register */ -volatile WOMMSTR _WOMM; /* Port M Wired-Or Mode Register */ -volatile WOMSSTR _WOMS; /* Port S Wired-Or Mode Register */ -volatile ATDCTL23STR _ATDCTL23; /* ATD Control Register 23 */ -volatile ATDCTL45STR _ATDCTL45; /* ATD Control Register 45 */ -volatile ATDDR0STR _ATDDR0; /* A/D Conversion Result Register 0 */ -volatile ATDDR1STR _ATDDR1; /* A/D Conversion Result Register 1 */ -volatile ATDDR2STR _ATDDR2; /* A/D Conversion Result Register 2 */ -volatile ATDDR3STR _ATDDR3; /* A/D Conversion Result Register 3 */ -volatile ATDDR4STR _ATDDR4; /* A/D Conversion Result Register 4 */ -volatile ATDDR5STR _ATDDR5; /* A/D Conversion Result Register 5 */ -volatile ATDDR6STR _ATDDR6; /* A/D Conversion Result Register 6 */ -volatile ATDDR7STR _ATDDR7; /* A/D Conversion Result Register 7 */ -volatile DDRABSTR _DDRAB; /* Port AB Data Direction Register */ -volatile PACNTSTR _PACNT; /* Pulse Accumulators Count Register */ -volatile PORTABSTR _PORTAB; /* Port AB Register */ -volatile PWMCNT01STR _PWMCNT01; /* PWM Channel Counter 01 Register */ -volatile PWMCNT23STR _PWMCNT23; /* PWM Channel Counter 23 Register */ -volatile PWMCNT45STR _PWMCNT45; /* PWM Channel Counter 45 Register */ -volatile PWMDTY01STR _PWMDTY01; /* PWM Channel Duty 01 Register */ -volatile PWMDTY23STR _PWMDTY23; /* PWM Channel Duty 23 Register */ -volatile PWMDTY45STR _PWMDTY45; /* PWM Channel Duty 45 Register */ -volatile PWMPER01STR _PWMPER01; /* PWM Channel Period 01 Register */ -volatile PWMPER23STR _PWMPER23; /* PWM Channel Period 23 Register */ -volatile PWMPER45STR _PWMPER45; /* PWM Channel Period 45 Register */ -volatile SCIBDSTR _SCIBD; /* SCI Baud Rate Register */ -volatile TC0STR _TC0; /* Timer Input Capture/Output Compare Register 0 */ -volatile TC1STR _TC1; /* Timer Input Capture/Output Compare Register 1 */ -volatile TC2STR _TC2; /* Timer Input Capture/Output Compare Register 2 */ -volatile TC3STR _TC3; /* Timer Input Capture/Output Compare Register 3 */ -volatile TC4STR _TC4; /* Timer Input Capture/Output Compare Register 4 */ -volatile TC5STR _TC5; /* Timer Input Capture/Output Compare Register 5 */ -volatile TC6STR _TC6; /* Timer Input Capture/Output Compare Register 6 */ -volatile TC7STR _TC7; /* Timer Input Capture/Output Compare Register 7 */ -volatile TCNTSTR _TCNT; /* Timer Count Register */ -/* -** ################################################################### -** -** This file was created by UNIS Processor Expert 03.33 for -** the Motorola HCS12 series of microcontrollers. -** -** ################################################################### -*/ diff --git a/Demo/HCS12_CodeWarrior_small/CODE/IO_Map.H b/Demo/HCS12_CodeWarrior_small/CODE/IO_Map.H deleted file mode 100644 index 2ff2281a1..000000000 --- a/Demo/HCS12_CodeWarrior_small/CODE/IO_Map.H +++ /dev/null @@ -1,8072 +0,0 @@ -/** ################################################################### -** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. -** Filename : IO_Map.H -** Project : RTOSDemo -** Processor : MC9S12C32CFU -** Beantype : IO_Map -** Version : Driver 01.01 -** Compiler : Metrowerks HC12 C Compiler -** Date/Time : 10/05/2005, 11:11 -** Abstract : -** This bean "IO_Map" implements an IO devices mapping. -** Settings : -** -** Contents : -** No public methods -** -** (c) Copyright UNIS, spol. s r.o. 1997-2002 -** UNIS, spol. s r.o. -** Jundrovska 33 -** 624 00 Brno -** Czech Republic -** http : www.processorexpert.com -** mail : info@processorexpert.com -** ###################################################################*/ - -/* Linker pragmas */ -#pragma LINK_INFO DERIVATIVE "MC9S12C32" -#pragma LINK_INFO OSCFREQUENCY "16000000" - - -#define REG_BASE 0x0000 /* Base address for the I/O register block */ - -/* Based on CPU DB MC9S12C32_80, version 2.87.264 (RegistersPrg V1.027) */ -#ifndef _MC9S12C32_80_H -#define _MC9S12C32_80_H - -#include "PE_Types.h" - -#pragma MESSAGE DISABLE C1106 /* WARNING C1106: Non-standard bitfield type */ - -/*********************************************/ -/* */ -/* PE I/O map format */ -/* */ -/*********************************************/ - -/*** PORTAB - Port AB Register; 0x00000000 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** PORTA - Port A Register; 0x00000000 ***/ - union { - byte Byte; - struct { - byte BIT0 :1; /* Port A Bit 0 */ - byte BIT1 :1; /* Port A Bit 1 */ - byte BIT2 :1; /* Port A Bit 2 */ - byte BIT3 :1; /* Port A Bit 3 */ - byte BIT4 :1; /* Port A Bit 4 */ - byte BIT5 :1; /* Port A Bit 5 */ - byte BIT6 :1; /* Port A Bit 6 */ - byte BIT7 :1; /* Port A Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; - } PORTASTR; - #define PORTA _PORTAB.Overlap_STR.PORTASTR.Byte - #define PORTA_BIT0 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT0 - #define PORTA_BIT1 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT1 - #define PORTA_BIT2 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT2 - #define PORTA_BIT3 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT3 - #define PORTA_BIT4 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT4 - #define PORTA_BIT5 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT5 - #define PORTA_BIT6 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT6 - #define PORTA_BIT7 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT7 - #define PORTA_BIT _PORTAB.Overlap_STR.PORTASTR.MergedBits.grpBIT - - /*** PORTB - Port B Register; 0x00000001 ***/ - union { - byte Byte; - struct { - byte BIT0 :1; /* Port B Bit 0 */ - byte BIT1 :1; /* Port B Bit 1 */ - byte BIT2 :1; /* Port B Bit 2 */ - byte BIT3 :1; /* Port B Bit 3 */ - byte BIT4 :1; /* Port B Bit 4 */ - byte BIT5 :1; /* Port B Bit 5 */ - byte BIT6 :1; /* Port B Bit 6 */ - byte BIT7 :1; /* Port B Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; - } PORTBSTR; - #define PORTB _PORTAB.Overlap_STR.PORTBSTR.Byte - #define PORTB_BIT0 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT0 - #define PORTB_BIT1 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT1 - #define PORTB_BIT2 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT2 - #define PORTB_BIT3 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT3 - #define PORTB_BIT4 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT4 - #define PORTB_BIT5 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT5 - #define PORTB_BIT6 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT6 - #define PORTB_BIT7 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT7 - #define PORTB_BIT _PORTAB.Overlap_STR.PORTBSTR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word BIT0 :1; /* Port AB Bit 0 */ - word BIT1 :1; /* Port AB Bit 1 */ - word BIT2 :1; /* Port AB Bit 2 */ - word BIT3 :1; /* Port AB Bit 3 */ - word BIT4 :1; /* Port AB Bit 4 */ - word BIT5 :1; /* Port AB Bit 5 */ - word BIT6 :1; /* Port AB Bit 6 */ - word BIT7 :1; /* Port AB Bit 7 */ - word BIT8 :1; /* Port AB Bit 8 */ - word BIT9 :1; /* Port AB Bit 9 */ - word BIT10 :1; /* Port AB Bit 10 */ - word BIT11 :1; /* Port AB Bit 11 */ - word BIT12 :1; /* Port AB Bit 12 */ - word BIT13 :1; /* Port AB Bit 13 */ - word BIT14 :1; /* Port AB Bit 14 */ - word BIT15 :1; /* Port AB Bit 15 */ - } Bits; - struct { - word grpBIT :16; - } MergedBits; -} PORTABSTR; -extern volatile PORTABSTR _PORTAB @(REG_BASE + 0x00000000); -#define PORTAB _PORTAB.Word -#define PORTAB_BIT0 _PORTAB.Bits.BIT0 -#define PORTAB_BIT1 _PORTAB.Bits.BIT1 -#define PORTAB_BIT2 _PORTAB.Bits.BIT2 -#define PORTAB_BIT3 _PORTAB.Bits.BIT3 -#define PORTAB_BIT4 _PORTAB.Bits.BIT4 -#define PORTAB_BIT5 _PORTAB.Bits.BIT5 -#define PORTAB_BIT6 _PORTAB.Bits.BIT6 -#define PORTAB_BIT7 _PORTAB.Bits.BIT7 -#define PORTAB_BIT8 _PORTAB.Bits.BIT8 -#define PORTAB_BIT9 _PORTAB.Bits.BIT9 -#define PORTAB_BIT10 _PORTAB.Bits.BIT10 -#define PORTAB_BIT11 _PORTAB.Bits.BIT11 -#define PORTAB_BIT12 _PORTAB.Bits.BIT12 -#define PORTAB_BIT13 _PORTAB.Bits.BIT13 -#define PORTAB_BIT14 _PORTAB.Bits.BIT14 -#define PORTAB_BIT15 _PORTAB.Bits.BIT15 -#define PORTAB_BIT _PORTAB.MergedBits.grpBIT - - -/*** DDRAB - Port AB Data Direction Register; 0x00000002 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** DDRA - Port A Data Direction Register; 0x00000002 ***/ - union { - byte Byte; - struct { - byte BIT0 :1; /* Data Direction Port A Bit 0 */ - byte BIT1 :1; /* Data Direction Port A Bit 1 */ - byte BIT2 :1; /* Data Direction Port A Bit 2 */ - byte BIT3 :1; /* Data Direction Port A Bit 3 */ - byte BIT4 :1; /* Data Direction Port A Bit 4 */ - byte BIT5 :1; /* Data Direction Port A Bit 5 */ - byte BIT6 :1; /* Data Direction Port A Bit 6 */ - byte BIT7 :1; /* Data Direction Port A Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; - } DDRASTR; - #define DDRA _DDRAB.Overlap_STR.DDRASTR.Byte - #define DDRA_BIT0 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT0 - #define DDRA_BIT1 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT1 - #define DDRA_BIT2 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT2 - #define DDRA_BIT3 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT3 - #define DDRA_BIT4 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT4 - #define DDRA_BIT5 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT5 - #define DDRA_BIT6 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT6 - #define DDRA_BIT7 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT7 - #define DDRA_BIT _DDRAB.Overlap_STR.DDRASTR.MergedBits.grpBIT - - /*** DDRB - Port B Data Direction Register; 0x00000003 ***/ - union { - byte Byte; - struct { - byte BIT0 :1; /* Data Direction Port B Bit 0 */ - byte BIT1 :1; /* Data Direction Port B Bit 1 */ - byte BIT2 :1; /* Data Direction Port B Bit 2 */ - byte BIT3 :1; /* Data Direction Port B Bit 3 */ - byte BIT4 :1; /* Data Direction Port B Bit 4 */ - byte BIT5 :1; /* Data Direction Port B Bit 5 */ - byte BIT6 :1; /* Data Direction Port B Bit 6 */ - byte BIT7 :1; /* Data Direction Port B Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; - } DDRBSTR; - #define DDRB _DDRAB.Overlap_STR.DDRBSTR.Byte - #define DDRB_BIT0 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT0 - #define DDRB_BIT1 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT1 - #define DDRB_BIT2 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT2 - #define DDRB_BIT3 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT3 - #define DDRB_BIT4 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT4 - #define DDRB_BIT5 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT5 - #define DDRB_BIT6 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT6 - #define DDRB_BIT7 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT7 - #define DDRB_BIT _DDRAB.Overlap_STR.DDRBSTR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word BIT0 :1; /* Data Direction Port B Bit 0 */ - word BIT1 :1; /* Data Direction Port B Bit 1 */ - word BIT2 :1; /* Data Direction Port B Bit 2 */ - word BIT3 :1; /* Data Direction Port B Bit 3 */ - word BIT4 :1; /* Data Direction Port B Bit 4 */ - word BIT5 :1; /* Data Direction Port B Bit 5 */ - word BIT6 :1; /* Data Direction Port B Bit 6 */ - word BIT7 :1; /* Data Direction Port B Bit 7 */ - word BIT8 :1; /* Data Direction Port A Bit 8 */ - word BIT9 :1; /* Data Direction Port A Bit 9 */ - word BIT10 :1; /* Data Direction Port A Bit 10 */ - word BIT11 :1; /* Data Direction Port A Bit 11 */ - word BIT12 :1; /* Data Direction Port A Bit 12 */ - word BIT13 :1; /* Data Direction Port A Bit 13 */ - word BIT14 :1; /* Data Direction Port A Bit 14 */ - word BIT15 :1; /* Data Direction Port A Bit 15 */ - } Bits; - struct { - word grpBIT :16; - } MergedBits; -} DDRABSTR; -extern volatile DDRABSTR _DDRAB @(REG_BASE + 0x00000002); -#define DDRAB _DDRAB.Word -#define DDRAB_BIT0 _DDRAB.Bits.BIT0 -#define DDRAB_BIT1 _DDRAB.Bits.BIT1 -#define DDRAB_BIT2 _DDRAB.Bits.BIT2 -#define DDRAB_BIT3 _DDRAB.Bits.BIT3 -#define DDRAB_BIT4 _DDRAB.Bits.BIT4 -#define DDRAB_BIT5 _DDRAB.Bits.BIT5 -#define DDRAB_BIT6 _DDRAB.Bits.BIT6 -#define DDRAB_BIT7 _DDRAB.Bits.BIT7 -#define DDRAB_BIT8 _DDRAB.Bits.BIT8 -#define DDRAB_BIT9 _DDRAB.Bits.BIT9 -#define DDRAB_BIT10 _DDRAB.Bits.BIT10 -#define DDRAB_BIT11 _DDRAB.Bits.BIT11 -#define DDRAB_BIT12 _DDRAB.Bits.BIT12 -#define DDRAB_BIT13 _DDRAB.Bits.BIT13 -#define DDRAB_BIT14 _DDRAB.Bits.BIT14 -#define DDRAB_BIT15 _DDRAB.Bits.BIT15 -#define DDRAB_BIT _DDRAB.MergedBits.grpBIT - - -/*** TCNT - Timer Count Register; 0x00000044 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** TCNTHi - Timer Count Register High; 0x00000044 ***/ - union { - byte Byte; - struct { - byte BIT15 :1; /* Timer Count Register Bit 15 */ - byte BIT14 :1; /* Timer Count Register Bit 14 */ - byte BIT13 :1; /* Timer Count Register Bit 13 */ - byte BIT12 :1; /* Timer Count Register Bit 12 */ - byte BIT11 :1; /* Timer Count Register Bit 11 */ - byte BIT10 :1; /* Timer Count Register Bit 10 */ - byte BIT9 :1; /* Timer Count Register Bit 9 */ - byte BIT8 :1; /* Timer Count Register Bit 8 */ - } Bits; - } TCNTHiSTR; - #define TCNTHi _TCNT.Overlap_STR.TCNTHiSTR.Byte - #define TCNTHi_BIT15 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT15 - #define TCNTHi_BIT14 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT14 - #define TCNTHi_BIT13 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT13 - #define TCNTHi_BIT12 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT12 - #define TCNTHi_BIT11 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT11 - #define TCNTHi_BIT10 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT10 - #define TCNTHi_BIT9 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT9 - #define TCNTHi_BIT8 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT8 - - /*** TCNTLo - Timer Count Register Low; 0x00000045 ***/ - union { - byte Byte; - struct { - byte BIT0 :1; /* Timer Count Register Bit 0 */ - byte BIT1 :1; /* Timer Count Register Bit 1 */ - byte BIT2 :1; /* Timer Count Register Bit 2 */ - byte BIT3 :1; /* Timer Count Register Bit 3 */ - byte BIT4 :1; /* Timer Count Bit Register 4 */ - byte BIT5 :1; /* Timer Count Bit Register 5 */ - byte BIT6 :1; /* Timer Count Bit Register 6 */ - byte BIT7 :1; /* Timer Count Bit Register 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; - } TCNTLoSTR; - #define TCNTLo _TCNT.Overlap_STR.TCNTLoSTR.Byte - #define TCNTLo_BIT0 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT0 - #define TCNTLo_BIT1 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT1 - #define TCNTLo_BIT2 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT2 - #define TCNTLo_BIT3 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT3 - #define TCNTLo_BIT4 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT4 - #define TCNTLo_BIT5 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT5 - #define TCNTLo_BIT6 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT6 - #define TCNTLo_BIT7 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT7 - #define TCNTLo_BIT _TCNT.Overlap_STR.TCNTLoSTR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word grpBIT :16; - } MergedBits; -} TCNTSTR; -extern volatile TCNTSTR _TCNT @(REG_BASE + 0x00000044); -#define TCNT _TCNT.Word -#define TCNT_BIT _TCNT.MergedBits.grpBIT - - -/*** TC0 - Timer Input Capture/Output Compare Register 0; 0x00000050 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** TC0Hi - Timer Input Capture/Output Compare Register 0 High; 0x00000050 ***/ - union { - byte Byte; - struct { - byte BIT8 :1; /* Timer Input Capture/Output Compare Register 0 Bit 8 */ - byte BIT9 :1; /* Timer Input Capture/Output Compare Register 0 Bit 9 */ - byte BIT10 :1; /* Timer Input Capture/Output Compare Register 0 Bit 10 */ - byte BIT11 :1; /* Timer Input Capture/Output Compare Register 0 Bit 11 */ - byte BIT12 :1; /* Timer Input Capture/Output Compare Register 0 Bit 12 */ - byte BIT13 :1; /* Timer Input Capture/Output Compare Register 0 Bit 13 */ - byte BIT14 :1; /* Timer Input Capture/Output Compare Register 0 Bit 14 */ - byte BIT15 :1; /* Timer Input Capture/Output Compare Register 0 Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; - } TC0HiSTR; - #define TC0Hi _TC0.Overlap_STR.TC0HiSTR.Byte - #define TC0Hi_BIT8 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT8 - #define TC0Hi_BIT9 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT9 - #define TC0Hi_BIT10 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT10 - #define TC0Hi_BIT11 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT11 - #define TC0Hi_BIT12 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT12 - #define TC0Hi_BIT13 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT13 - #define TC0Hi_BIT14 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT14 - #define TC0Hi_BIT15 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT15 - #define TC0Hi_BIT_8 _TC0.Overlap_STR.TC0HiSTR.MergedBits.grpBIT_8 - #define TC0Hi_BIT TC0Hi_BIT_8 - - /*** TC0Lo - Timer Input Capture/Output Compare Register 0 Low; 0x00000051 ***/ - union { - byte Byte; - struct { - byte BIT0 :1; /* Timer Input Capture/Output Compare Register 0 Bit 0 */ - byte BIT1 :1; /* Timer Input Capture/Output Compare Register 0 Bit 1 */ - byte BIT2 :1; /* Timer Input Capture/Output Compare Register 0 Bit 2 */ - byte BIT3 :1; /* Timer Input Capture/Output Compare Register 0 Bit 3 */ - byte BIT4 :1; /* Timer Input Capture/Output Compare Register 0 Bit 4 */ - byte BIT5 :1; /* Timer Input Capture/Output Compare Register 0 Bit 5 */ - byte BIT6 :1; /* Timer Input Capture/Output Compare Register 0 Bit 6 */ - byte BIT7 :1; /* Timer Input Capture/Output Compare Register 0 Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; - } TC0LoSTR; - #define TC0Lo _TC0.Overlap_STR.TC0LoSTR.Byte - #define TC0Lo_BIT0 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT0 - #define TC0Lo_BIT1 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT1 - #define TC0Lo_BIT2 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT2 - #define TC0Lo_BIT3 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT3 - #define TC0Lo_BIT4 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT4 - #define TC0Lo_BIT5 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT5 - #define TC0Lo_BIT6 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT6 - #define TC0Lo_BIT7 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT7 - #define TC0Lo_BIT _TC0.Overlap_STR.TC0LoSTR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word grpBIT :16; - } MergedBits; -} TC0STR; -extern volatile TC0STR _TC0 @(REG_BASE + 0x00000050); -#define TC0 _TC0.Word -#define TC0_BIT _TC0.MergedBits.grpBIT - - -/*** TC1 - Timer Input Capture/Output Compare Register 1; 0x00000052 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** TC1Hi - Timer Input Capture/Output Compare Register 1 High; 0x00000052 ***/ - union { - byte Byte; - struct { - byte BIT8 :1; /* Timer Input Capture/Output Compare Register 1 Bit 8 */ - byte BIT9 :1; /* Timer Input Capture/Output Compare Register 1 Bit 9 */ - byte BIT10 :1; /* Timer Input Capture/Output Compare Register 1 Bit 10 */ - byte BIT11 :1; /* Timer Input Capture/Output Compare Register 1 Bit 11 */ - byte BIT12 :1; /* Timer Input Capture/Output Compare Register 1 Bit 12 */ - byte BIT13 :1; /* Timer Input Capture/Output Compare Register 1 Bit 13 */ - byte BIT14 :1; /* Timer Input Capture/Output Compare Register 1 Bit 14 */ - byte BIT15 :1; /* Timer Input Capture/Output Compare Register 1 Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; - } TC1HiSTR; - #define TC1Hi _TC1.Overlap_STR.TC1HiSTR.Byte - #define TC1Hi_BIT8 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT8 - #define TC1Hi_BIT9 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT9 - #define TC1Hi_BIT10 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT10 - #define TC1Hi_BIT11 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT11 - #define TC1Hi_BIT12 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT12 - #define TC1Hi_BIT13 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT13 - #define TC1Hi_BIT14 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT14 - #define TC1Hi_BIT15 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT15 - #define TC1Hi_BIT_8 _TC1.Overlap_STR.TC1HiSTR.MergedBits.grpBIT_8 - #define TC1Hi_BIT TC1Hi_BIT_8 - - /*** TC1Lo - Timer Input Capture/Output Compare Register 1 Low; 0x00000053 ***/ - union { - byte Byte; - struct { - byte BIT0 :1; /* Timer Input Capture/Output Compare Register 1 Bit 0 */ - byte BIT1 :1; /* Timer Input Capture/Output Compare Register 1 Bit 1 */ - byte BIT2 :1; /* Timer Input Capture/Output Compare Register 1 Bit 2 */ - byte BIT3 :1; /* Timer Input Capture/Output Compare Register 1 Bit 3 */ - byte BIT4 :1; /* Timer Input Capture/Output Compare Register 1 Bit 4 */ - byte BIT5 :1; /* Timer Input Capture/Output Compare Register 1 Bit 5 */ - byte BIT6 :1; /* Timer Input Capture/Output Compare Register 1 Bit 6 */ - byte BIT7 :1; /* Timer Input Capture/Output Compare Register 1 Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; - } TC1LoSTR; - #define TC1Lo _TC1.Overlap_STR.TC1LoSTR.Byte - #define TC1Lo_BIT0 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT0 - #define TC1Lo_BIT1 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT1 - #define TC1Lo_BIT2 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT2 - #define TC1Lo_BIT3 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT3 - #define TC1Lo_BIT4 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT4 - #define TC1Lo_BIT5 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT5 - #define TC1Lo_BIT6 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT6 - #define TC1Lo_BIT7 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT7 - #define TC1Lo_BIT _TC1.Overlap_STR.TC1LoSTR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word grpBIT :16; - } MergedBits; -} TC1STR; -extern volatile TC1STR _TC1 @(REG_BASE + 0x00000052); -#define TC1 _TC1.Word -#define TC1_BIT _TC1.MergedBits.grpBIT - - -/*** TC2 - Timer Input Capture/Output Compare Register 2; 0x00000054 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** TC2Hi - Timer Input Capture/Output Compare Register 2 High; 0x00000054 ***/ - union { - byte Byte; - struct { - byte BIT8 :1; /* Timer Input Capture/Output Compare Register 2 Bit 8 */ - byte BIT9 :1; /* Timer Input Capture/Output Compare Register 2 Bit 9 */ - byte BIT10 :1; /* Timer Input Capture/Output Compare Register 2 Bit 10 */ - byte BIT11 :1; /* Timer Input Capture/Output Compare Register 2 Bit 11 */ - byte BIT12 :1; /* Timer Input Capture/Output Compare Register 2 Bit 12 */ - byte BIT13 :1; /* Timer Input Capture/Output Compare Register 2 Bit 13 */ - byte BIT14 :1; /* Timer Input Capture/Output Compare Register 2 Bit 14 */ - byte BIT15 :1; /* Timer Input Capture/Output Compare Register 2 Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; - } TC2HiSTR; - #define TC2Hi _TC2.Overlap_STR.TC2HiSTR.Byte - #define TC2Hi_BIT8 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT8 - #define TC2Hi_BIT9 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT9 - #define TC2Hi_BIT10 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT10 - #define TC2Hi_BIT11 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT11 - #define TC2Hi_BIT12 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT12 - #define TC2Hi_BIT13 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT13 - #define TC2Hi_BIT14 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT14 - #define TC2Hi_BIT15 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT15 - #define TC2Hi_BIT_8 _TC2.Overlap_STR.TC2HiSTR.MergedBits.grpBIT_8 - #define TC2Hi_BIT TC2Hi_BIT_8 - - /*** TC2Lo - Timer Input Capture/Output Compare Register 2 Low; 0x00000055 ***/ - union { - byte Byte; - struct { - byte BIT0 :1; /* Timer Input Capture/Output Compare Register 2 Bit 0 */ - byte BIT1 :1; /* Timer Input Capture/Output Compare Register 2 Bit 1 */ - byte BIT2 :1; /* Timer Input Capture/Output Compare Register 2 Bit 2 */ - byte BIT3 :1; /* Timer Input Capture/Output Compare Register 2 Bit 3 */ - byte BIT4 :1; /* Timer Input Capture/Output Compare Register 2 Bit 4 */ - byte BIT5 :1; /* Timer Input Capture/Output Compare Register 2 Bit 5 */ - byte BIT6 :1; /* Timer Input Capture/Output Compare Register 2 Bit 6 */ - byte BIT7 :1; /* Timer Input Capture/Output Compare Register 2 Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; - } TC2LoSTR; - #define TC2Lo _TC2.Overlap_STR.TC2LoSTR.Byte - #define TC2Lo_BIT0 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT0 - #define TC2Lo_BIT1 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT1 - #define TC2Lo_BIT2 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT2 - #define TC2Lo_BIT3 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT3 - #define TC2Lo_BIT4 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT4 - #define TC2Lo_BIT5 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT5 - #define TC2Lo_BIT6 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT6 - #define TC2Lo_BIT7 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT7 - #define TC2Lo_BIT _TC2.Overlap_STR.TC2LoSTR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word grpBIT :16; - } MergedBits; -} TC2STR; -extern volatile TC2STR _TC2 @(REG_BASE + 0x00000054); -#define TC2 _TC2.Word -#define TC2_BIT _TC2.MergedBits.grpBIT - - -/*** TC3 - Timer Input Capture/Output Compare Register 3; 0x00000056 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** TC3Hi - Timer Input Capture/Output Compare Register 3 High; 0x00000056 ***/ - union { - byte Byte; - struct { - byte BIT8 :1; /* Timer Input Capture/Output Compare Register 3 Bit 8 */ - byte BIT9 :1; /* Timer Input Capture/Output Compare Register 3 Bit 9 */ - byte BIT10 :1; /* Timer Input Capture/Output Compare Register 3 Bit 10 */ - byte BIT11 :1; /* Timer Input Capture/Output Compare Register 3 Bit 11 */ - byte BIT12 :1; /* Timer Input Capture/Output Compare Register 3 Bit 12 */ - byte BIT13 :1; /* Timer Input Capture/Output Compare Register 3 Bit 13 */ - byte BIT14 :1; /* Timer Input Capture/Output Compare Register 3 Bit 14 */ - byte BIT15 :1; /* Timer Input Capture/Output Compare Register 3 Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; - } TC3HiSTR; - #define TC3Hi _TC3.Overlap_STR.TC3HiSTR.Byte - #define TC3Hi_BIT8 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT8 - #define TC3Hi_BIT9 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT9 - #define TC3Hi_BIT10 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT10 - #define TC3Hi_BIT11 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT11 - #define TC3Hi_BIT12 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT12 - #define TC3Hi_BIT13 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT13 - #define TC3Hi_BIT14 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT14 - #define TC3Hi_BIT15 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT15 - #define TC3Hi_BIT_8 _TC3.Overlap_STR.TC3HiSTR.MergedBits.grpBIT_8 - #define TC3Hi_BIT TC3Hi_BIT_8 - - /*** TC3Lo - Timer Input Capture/Output Compare Register 3 Low; 0x00000057 ***/ - union { - byte Byte; - struct { - byte BIT0 :1; /* Timer Input Capture/Output Compare Register 3 Bit 0 */ - byte BIT1 :1; /* Timer Input Capture/Output Compare Register 3 Bit 1 */ - byte BIT2 :1; /* Timer Input Capture/Output Compare Register 3 Bit 2 */ - byte BIT3 :1; /* Timer Input Capture/Output Compare Register 3 Bit 3 */ - byte BIT4 :1; /* Timer Input Capture/Output Compare Register 3 Bit 4 */ - byte BIT5 :1; /* Timer Input Capture/Output Compare Register 3 Bit 5 */ - byte BIT6 :1; /* Timer Input Capture/Output Compare Register 3 Bit 6 */ - byte BIT7 :1; /* Timer Input Capture/Output Compare Register 3 Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; - } TC3LoSTR; - #define TC3Lo _TC3.Overlap_STR.TC3LoSTR.Byte - #define TC3Lo_BIT0 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT0 - #define TC3Lo_BIT1 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT1 - #define TC3Lo_BIT2 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT2 - #define TC3Lo_BIT3 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT3 - #define TC3Lo_BIT4 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT4 - #define TC3Lo_BIT5 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT5 - #define TC3Lo_BIT6 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT6 - #define TC3Lo_BIT7 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT7 - #define TC3Lo_BIT _TC3.Overlap_STR.TC3LoSTR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word grpBIT :16; - } MergedBits; -} TC3STR; -extern volatile TC3STR _TC3 @(REG_BASE + 0x00000056); -#define TC3 _TC3.Word -#define TC3_BIT _TC3.MergedBits.grpBIT - - -/*** TC4 - Timer Input Capture/Output Compare Register 4; 0x00000058 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** TC4Hi - Timer Input Capture/Output Compare Register 4 High; 0x00000058 ***/ - union { - byte Byte; - struct { - byte BIT8 :1; /* Timer Input Capture/Output Compare Register 4 Bit 8 */ - byte BIT9 :1; /* Timer Input Capture/Output Compare Register 4 Bit 9 */ - byte BIT10 :1; /* Timer Input Capture/Output Compare Register 4 Bit 10 */ - byte BIT11 :1; /* Timer Input Capture/Output Compare Register 4 Bit 11 */ - byte BIT12 :1; /* Timer Input Capture/Output Compare Register 4 Bit 12 */ - byte BIT13 :1; /* Timer Input Capture/Output Compare Register 4 Bit 13 */ - byte BIT14 :1; /* Timer Input Capture/Output Compare Register 4 Bit 14 */ - byte BIT15 :1; /* Timer Input Capture/Output Compare Register 4 Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; - } TC4HiSTR; - #define TC4Hi _TC4.Overlap_STR.TC4HiSTR.Byte - #define TC4Hi_BIT8 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT8 - #define TC4Hi_BIT9 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT9 - #define TC4Hi_BIT10 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT10 - #define TC4Hi_BIT11 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT11 - #define TC4Hi_BIT12 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT12 - #define TC4Hi_BIT13 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT13 - #define TC4Hi_BIT14 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT14 - #define TC4Hi_BIT15 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT15 - #define TC4Hi_BIT_8 _TC4.Overlap_STR.TC4HiSTR.MergedBits.grpBIT_8 - #define TC4Hi_BIT TC4Hi_BIT_8 - - /*** TC4Lo - Timer Input Capture/Output Compare Register 4 Low; 0x00000059 ***/ - union { - byte Byte; - struct { - byte BIT0 :1; /* Timer Input Capture/Output Compare Register 4 Bit 0 */ - byte BIT1 :1; /* Timer Input Capture/Output Compare Register 4 Bit 1 */ - byte BIT2 :1; /* Timer Input Capture/Output Compare Register 4 Bit 2 */ - byte BIT3 :1; /* Timer Input Capture/Output Compare Register 4 Bit 3 */ - byte BIT4 :1; /* Timer Input Capture/Output Compare Register 4 Bit 4 */ - byte BIT5 :1; /* Timer Input Capture/Output Compare Register 4 Bit 5 */ - byte BIT6 :1; /* Timer Input Capture/Output Compare Register 4 Bit 6 */ - byte BIT7 :1; /* Timer Input Capture/Output Compare Register 4 Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; - } TC4LoSTR; - #define TC4Lo _TC4.Overlap_STR.TC4LoSTR.Byte - #define TC4Lo_BIT0 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT0 - #define TC4Lo_BIT1 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT1 - #define TC4Lo_BIT2 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT2 - #define TC4Lo_BIT3 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT3 - #define TC4Lo_BIT4 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT4 - #define TC4Lo_BIT5 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT5 - #define TC4Lo_BIT6 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT6 - #define TC4Lo_BIT7 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT7 - #define TC4Lo_BIT _TC4.Overlap_STR.TC4LoSTR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word grpBIT :16; - } MergedBits; -} TC4STR; -extern volatile TC4STR _TC4 @(REG_BASE + 0x00000058); -#define TC4 _TC4.Word -#define TC4_BIT _TC4.MergedBits.grpBIT - - -/*** TC5 - Timer Input Capture/Output Compare Register 5; 0x0000005A ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** TC5Hi - Timer Input Capture/Output Compare Register 5 High; 0x0000005A ***/ - union { - byte Byte; - struct { - byte BIT8 :1; /* Timer Input Capture/Output Compare Register 5 Bit 8 */ - byte BIT9 :1; /* Timer Input Capture/Output Compare Register 5 Bit 9 */ - byte BIT10 :1; /* Timer Input Capture/Output Compare Register 5 Bit 10 */ - byte BIT11 :1; /* Timer Input Capture/Output Compare Register 5 Bit 11 */ - byte BIT12 :1; /* Timer Input Capture/Output Compare Register 5 Bit 12 */ - byte BIT13 :1; /* Timer Input Capture/Output Compare Register 5 Bit 13 */ - byte BIT14 :1; /* Timer Input Capture/Output Compare Register 5 Bit 14 */ - byte BIT15 :1; /* Timer Input Capture/Output Compare Register 5 Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; - } TC5HiSTR; - #define TC5Hi _TC5.Overlap_STR.TC5HiSTR.Byte - #define TC5Hi_BIT8 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT8 - #define TC5Hi_BIT9 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT9 - #define TC5Hi_BIT10 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT10 - #define TC5Hi_BIT11 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT11 - #define TC5Hi_BIT12 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT12 - #define TC5Hi_BIT13 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT13 - #define TC5Hi_BIT14 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT14 - #define TC5Hi_BIT15 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT15 - #define TC5Hi_BIT_8 _TC5.Overlap_STR.TC5HiSTR.MergedBits.grpBIT_8 - #define TC5Hi_BIT TC5Hi_BIT_8 - - /*** TC5Lo - Timer Input Capture/Output Compare Register 5 Low; 0x0000005B ***/ - union { - byte Byte; - struct { - byte BIT0 :1; /* Timer Input Capture/Output Compare Register 5 Bit 0 */ - byte BIT1 :1; /* Timer Input Capture/Output Compare Register 5 Bit 1 */ - byte BIT2 :1; /* Timer Input Capture/Output Compare Register 5 Bit 2 */ - byte BIT3 :1; /* Timer Input Capture/Output Compare Register 5 Bit 3 */ - byte BIT4 :1; /* Timer Input Capture/Output Compare Register 5 Bit 4 */ - byte BIT5 :1; /* Timer Input Capture/Output Compare Register 5 Bit 5 */ - byte BIT6 :1; /* Timer Input Capture/Output Compare Register 5 Bit 6 */ - byte BIT7 :1; /* Timer Input Capture/Output Compare Register 5 Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; - } TC5LoSTR; - #define TC5Lo _TC5.Overlap_STR.TC5LoSTR.Byte - #define TC5Lo_BIT0 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT0 - #define TC5Lo_BIT1 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT1 - #define TC5Lo_BIT2 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT2 - #define TC5Lo_BIT3 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT3 - #define TC5Lo_BIT4 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT4 - #define TC5Lo_BIT5 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT5 - #define TC5Lo_BIT6 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT6 - #define TC5Lo_BIT7 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT7 - #define TC5Lo_BIT _TC5.Overlap_STR.TC5LoSTR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word grpBIT :16; - } MergedBits; -} TC5STR; -extern volatile TC5STR _TC5 @(REG_BASE + 0x0000005A); -#define TC5 _TC5.Word -#define TC5_BIT _TC5.MergedBits.grpBIT - - -/*** TC6 - Timer Input Capture/Output Compare Register 6; 0x0000005C ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** TC6Hi - Timer Input Capture/Output Compare Register 6 High; 0x0000005C ***/ - union { - byte Byte; - struct { - byte BIT8 :1; /* Timer Input Capture/Output Compare Register 6 Bit 8 */ - byte BIT9 :1; /* Timer Input Capture/Output Compare Register 6 Bit 9 */ - byte BIT10 :1; /* Timer Input Capture/Output Compare Register 6 Bit 10 */ - byte BIT11 :1; /* Timer Input Capture/Output Compare Register 6 Bit 11 */ - byte BIT12 :1; /* Timer Input Capture/Output Compare Register 6 Bit 12 */ - byte BIT13 :1; /* Timer Input Capture/Output Compare Register 6 Bit 13 */ - byte BIT14 :1; /* Timer Input Capture/Output Compare Register 6 Bit 14 */ - byte BIT15 :1; /* Timer Input Capture/Output Compare Register 6 Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; - } TC6HiSTR; - #define TC6Hi _TC6.Overlap_STR.TC6HiSTR.Byte - #define TC6Hi_BIT8 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT8 - #define TC6Hi_BIT9 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT9 - #define TC6Hi_BIT10 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT10 - #define TC6Hi_BIT11 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT11 - #define TC6Hi_BIT12 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT12 - #define TC6Hi_BIT13 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT13 - #define TC6Hi_BIT14 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT14 - #define TC6Hi_BIT15 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT15 - #define TC6Hi_BIT_8 _TC6.Overlap_STR.TC6HiSTR.MergedBits.grpBIT_8 - #define TC6Hi_BIT TC6Hi_BIT_8 - - /*** TC6Lo - Timer Input Capture/Output Compare Register 6 Low; 0x0000005D ***/ - union { - byte Byte; - struct { - byte BIT0 :1; /* Timer Input Capture/Output Compare Register 6 Bit 0 */ - byte BIT1 :1; /* Timer Input Capture/Output Compare Register 6 Bit 1 */ - byte BIT2 :1; /* Timer Input Capture/Output Compare Register 6 Bit 2 */ - byte BIT3 :1; /* Timer Input Capture/Output Compare Register 6 Bit 3 */ - byte BIT4 :1; /* Timer Input Capture/Output Compare Register 6 Bit 4 */ - byte BIT5 :1; /* Timer Input Capture/Output Compare Register 6 Bit 5 */ - byte BIT6 :1; /* Timer Input Capture/Output Compare Register 6 Bit 6 */ - byte BIT7 :1; /* Timer Input Capture/Output Compare Register 6 Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; - } TC6LoSTR; - #define TC6Lo _TC6.Overlap_STR.TC6LoSTR.Byte - #define TC6Lo_BIT0 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT0 - #define TC6Lo_BIT1 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT1 - #define TC6Lo_BIT2 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT2 - #define TC6Lo_BIT3 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT3 - #define TC6Lo_BIT4 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT4 - #define TC6Lo_BIT5 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT5 - #define TC6Lo_BIT6 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT6 - #define TC6Lo_BIT7 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT7 - #define TC6Lo_BIT _TC6.Overlap_STR.TC6LoSTR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word grpBIT :16; - } MergedBits; -} TC6STR; -extern volatile TC6STR _TC6 @(REG_BASE + 0x0000005C); -#define TC6 _TC6.Word -#define TC6_BIT _TC6.MergedBits.grpBIT - - -/*** TC7 - Timer Input Capture/Output Compare Register 7; 0x0000005E ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** TC7Hi - Timer Input Capture/Output Compare Register 7 High; 0x0000005E ***/ - union { - byte Byte; - struct { - byte BIT8 :1; /* Timer Input Capture/Output Compare Register 7 Bit 8 */ - byte BIT9 :1; /* Timer Input Capture/Output Compare Register 7 Bit 9 */ - byte BIT10 :1; /* Timer Input Capture/Output Compare Register 7 Bit 10 */ - byte BIT11 :1; /* Timer Input Capture/Output Compare Register 7 Bit 11 */ - byte BIT12 :1; /* Timer Input Capture/Output Compare Register 7 Bit 12 */ - byte BIT13 :1; /* Timer Input Capture/Output Compare Register 7 Bit 13 */ - byte BIT14 :1; /* Timer Input Capture/Output Compare Register 7 Bit 14 */ - byte BIT15 :1; /* Timer Input Capture/Output Compare Register 7 Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; - } TC7HiSTR; - #define TC7Hi _TC7.Overlap_STR.TC7HiSTR.Byte - #define TC7Hi_BIT8 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT8 - #define TC7Hi_BIT9 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT9 - #define TC7Hi_BIT10 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT10 - #define TC7Hi_BIT11 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT11 - #define TC7Hi_BIT12 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT12 - #define TC7Hi_BIT13 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT13 - #define TC7Hi_BIT14 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT14 - #define TC7Hi_BIT15 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT15 - #define TC7Hi_BIT_8 _TC7.Overlap_STR.TC7HiSTR.MergedBits.grpBIT_8 - #define TC7Hi_BIT TC7Hi_BIT_8 - - /*** TC7Lo - Timer Input Capture/Output Compare Register 7 Low; 0x0000005F ***/ - union { - byte Byte; - struct { - byte BIT0 :1; /* Timer Input Capture/Output Compare Register 7 Bit 0 */ - byte BIT1 :1; /* Timer Input Capture/Output Compare Register 7 Bit 1 */ - byte BIT2 :1; /* Timer Input Capture/Output Compare Register 7 Bit 2 */ - byte BIT3 :1; /* Timer Input Capture/Output Compare Register 7 Bit 3 */ - byte BIT4 :1; /* Timer Input Capture/Output Compare Register 7 Bit 4 */ - byte BIT5 :1; /* Timer Input Capture/Output Compare Register 7 Bit 5 */ - byte BIT6 :1; /* Timer Input Capture/Output Compare Register 7 Bit 6 */ - byte BIT7 :1; /* Timer Input Capture/Output Compare Register 7 Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; - } TC7LoSTR; - #define TC7Lo _TC7.Overlap_STR.TC7LoSTR.Byte - #define TC7Lo_BIT0 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT0 - #define TC7Lo_BIT1 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT1 - #define TC7Lo_BIT2 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT2 - #define TC7Lo_BIT3 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT3 - #define TC7Lo_BIT4 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT4 - #define TC7Lo_BIT5 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT5 - #define TC7Lo_BIT6 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT6 - #define TC7Lo_BIT7 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT7 - #define TC7Lo_BIT _TC7.Overlap_STR.TC7LoSTR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word grpBIT :16; - } MergedBits; -} TC7STR; -extern volatile TC7STR _TC7 @(REG_BASE + 0x0000005E); -#define TC7 _TC7.Word -#define TC7_BIT _TC7.MergedBits.grpBIT - - -/*** PACNT - Pulse Accumulators Count Register; 0x00000062 ***/ -typedef union { - word Word; - struct { - word grpBIT :16; - } MergedBits; -} PACNTSTR; -extern volatile PACNTSTR _PACNT @(REG_BASE + 0x00000062); -#define PACNT _PACNT.Word -#define PACNT_BIT _PACNT.MergedBits.grpBIT - - -/*** ATDCTL23 - ATD Control Register 23; 0x00000082 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** ATDCTL2 - ATD Control Register 2; 0x00000082 ***/ - union { - byte Byte; - struct { - byte ASCIF :1; /* ATD Sequence Complete Interrupt Flag */ - byte ASCIE :1; /* ATD Sequence Complete Interrupt Enable */ - byte ETRIGE :1; /* External Trigger Mode enable */ - byte ETRIGP :1; /* External Trigger Polarity */ - byte ETRIGLE :1; /* External Trigger Level/Edge control */ - byte AWAI :1; /* ATD Wait Mode */ - byte AFFC :1; /* ATD Fast Conversion Complete Flag Clear */ - byte ADPU :1; /* ATD Disable / Power Down */ - } Bits; - } ATDCTL2STR; - #define ATDCTL2 _ATDCTL23.Overlap_STR.ATDCTL2STR.Byte - #define ATDCTL2_ASCIF _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.ASCIF - #define ATDCTL2_ASCIE _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.ASCIE - #define ATDCTL2_ETRIGE _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.ETRIGE - #define ATDCTL2_ETRIGP _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.ETRIGP - #define ATDCTL2_ETRIGLE _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.ETRIGLE - #define ATDCTL2_AWAI _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.AWAI - #define ATDCTL2_AFFC _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.AFFC - #define ATDCTL2_ADPU _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.ADPU - - /*** ATDCTL3 - ATD Control Register 3; 0x00000083 ***/ - union { - byte Byte; - struct { - byte FRZ0 :1; /* Background Debug Freeze Enable */ - byte FRZ1 :1; /* Background Debug Freeze Enable */ - byte FIFO :1; /* Result Register FIFO Mode */ - byte S1C :1; /* Conversion Sequence Length 1 */ - byte S2C :1; /* Conversion Sequence Length 2 */ - byte S4C :1; /* Conversion Sequence Length 4 */ - byte S8C :1; /* Conversion Sequence Length 8 */ - byte :1; - } Bits; - struct { - byte grpFRZ :2; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; - } ATDCTL3STR; - #define ATDCTL3 _ATDCTL23.Overlap_STR.ATDCTL3STR.Byte - #define ATDCTL3_FRZ0 _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.FRZ0 - #define ATDCTL3_FRZ1 _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.FRZ1 - #define ATDCTL3_FIFO _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.FIFO - #define ATDCTL3_S1C _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.S1C - #define ATDCTL3_S2C _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.S2C - #define ATDCTL3_S4C _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.S4C - #define ATDCTL3_S8C _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.S8C - #define ATDCTL3_FRZ _ATDCTL23.Overlap_STR.ATDCTL3STR.MergedBits.grpFRZ - - } Overlap_STR; - - struct { - word FRZ0 :1; /* Background Debug Freeze Enable */ - word FRZ1 :1; /* Background Debug Freeze Enable */ - word FIFO :1; /* Result Register FIFO Mode */ - word S1C :1; /* Conversion Sequence Length 1 */ - word S2C :1; /* Conversion Sequence Length 2 */ - word S4C :1; /* Conversion Sequence Length 4 */ - word S8C :1; /* Conversion Sequence Length 8 */ - word :1; - word ASCIF :1; /* ATD Sequence Complete Interrupt Flag */ - word ASCIE :1; /* ATD Sequence Complete Interrupt Enable */ - word ETRIGE :1; /* External Trigger Mode enable */ - word ETRIGP :1; /* External Trigger Polarity */ - word ETRIGLE :1; /* External Trigger Level/Edge control */ - word AWAI :1; /* ATD Wait Mode */ - word AFFC :1; /* ATD Fast Conversion Complete Flag Clear */ - word ADPU :1; /* ATD Disable / Power Down */ - } Bits; - struct { - word grpFRZ :2; - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - } MergedBits; -} ATDCTL23STR; -extern volatile ATDCTL23STR _ATDCTL23 @(REG_BASE + 0x00000082); -#define ATDCTL23 _ATDCTL23.Word -#define ATDCTL23_FRZ0 _ATDCTL23.Bits.FRZ0 -#define ATDCTL23_FRZ1 _ATDCTL23.Bits.FRZ1 -#define ATDCTL23_FIFO _ATDCTL23.Bits.FIFO -#define ATDCTL23_S1C _ATDCTL23.Bits.S1C -#define ATDCTL23_S2C _ATDCTL23.Bits.S2C -#define ATDCTL23_S4C _ATDCTL23.Bits.S4C -#define ATDCTL23_S8C _ATDCTL23.Bits.S8C -#define ATDCTL23_ASCIF _ATDCTL23.Bits.ASCIF -#define ATDCTL23_ASCIE _ATDCTL23.Bits.ASCIE -#define ATDCTL23_ETRIGE _ATDCTL23.Bits.ETRIGE -#define ATDCTL23_ETRIGP _ATDCTL23.Bits.ETRIGP -#define ATDCTL23_ETRIGLE _ATDCTL23.Bits.ETRIGLE -#define ATDCTL23_AWAI _ATDCTL23.Bits.AWAI -#define ATDCTL23_AFFC _ATDCTL23.Bits.AFFC -#define ATDCTL23_ADPU _ATDCTL23.Bits.ADPU -#define ATDCTL23_FRZ _ATDCTL23.MergedBits.grpFRZ - - -/*** ATDCTL45 - ATD Control Register 45; 0x00000084 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** ATDCTL4 - ATD Control Register 4; 0x00000084 ***/ - union { - byte Byte; - struct { - byte PRS0 :1; /* ATD Clock Prescaler 0 */ - byte PRS1 :1; /* ATD Clock Prescaler 1 */ - byte PRS2 :1; /* ATD Clock Prescaler 2 */ - byte PRS3 :1; /* ATD Clock Prescaler 3 */ - byte PRS4 :1; /* ATD Clock Prescaler 4 */ - byte SMP0 :1; /* Sample Time Select 0 */ - byte SMP1 :1; /* Sample Time Select 1 */ - byte SRES8 :1; /* A/D Resolution Select */ - } Bits; - struct { - byte grpPRS :5; - byte grpSMP :2; - byte grpSRES_8 :1; - } MergedBits; - } ATDCTL4STR; - #define ATDCTL4 _ATDCTL45.Overlap_STR.ATDCTL4STR.Byte - #define ATDCTL4_PRS0 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.PRS0 - #define ATDCTL4_PRS1 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.PRS1 - #define ATDCTL4_PRS2 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.PRS2 - #define ATDCTL4_PRS3 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.PRS3 - #define ATDCTL4_PRS4 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.PRS4 - #define ATDCTL4_SMP0 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.SMP0 - #define ATDCTL4_SMP1 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.SMP1 - #define ATDCTL4_SRES8 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.SRES8 - #define ATDCTL4_PRS _ATDCTL45.Overlap_STR.ATDCTL4STR.MergedBits.grpPRS - #define ATDCTL4_SMP _ATDCTL45.Overlap_STR.ATDCTL4STR.MergedBits.grpSMP - - /*** ATDCTL5 - ATD Control Register 5; 0x00000085 ***/ - union { - byte Byte; - struct { - byte CA :1; /* Analog Input Channel Select Code A */ - byte CB :1; /* Analog Input Channel Select Code B */ - byte CC :1; /* Analog Input Channel Select Code C */ - byte :1; - byte MULT :1; /* Multi-Channel Sample Mode */ - byte SCAN :1; /* Continuous Conversion Sequence Mode */ - byte DSGN :1; /* Signed/Unsigned Result Data Mode */ - byte DJM :1; /* Result Register Data Justification Mode */ - } Bits; - } ATDCTL5STR; - #define ATDCTL5 _ATDCTL45.Overlap_STR.ATDCTL5STR.Byte - #define ATDCTL5_CA _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.CA - #define ATDCTL5_CB _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.CB - #define ATDCTL5_CC _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.CC - #define ATDCTL5_MULT _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.MULT - #define ATDCTL5_SCAN _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.SCAN - #define ATDCTL5_DSGN _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.DSGN - #define ATDCTL5_DJM _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.DJM - - } Overlap_STR; - - struct { - word CA :1; /* Analog Input Channel Select Code A */ - word CB :1; /* Analog Input Channel Select Code B */ - word CC :1; /* Analog Input Channel Select Code C */ - word :1; - word MULT :1; /* Multi-Channel Sample Mode */ - word SCAN :1; /* Continuous Conversion Sequence Mode */ - word DSGN :1; /* Signed/Unsigned Result Data Mode */ - word DJM :1; /* Result Register Data Justification Mode */ - word PRS0 :1; /* ATD Clock Prescaler 0 */ - word PRS1 :1; /* ATD Clock Prescaler 1 */ - word PRS2 :1; /* ATD Clock Prescaler 2 */ - word PRS3 :1; /* ATD Clock Prescaler 3 */ - word PRS4 :1; /* ATD Clock Prescaler 4 */ - word SMP0 :1; /* Sample Time Select 0 */ - word SMP1 :1; /* Sample Time Select 1 */ - word SRES8 :1; /* A/D Resolution Select */ - } Bits; - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word grpPRS :5; - word grpSMP :2; - word grpSRES_8 :1; - } MergedBits; -} ATDCTL45STR; -extern volatile ATDCTL45STR _ATDCTL45 @(REG_BASE + 0x00000084); -#define ATDCTL45 _ATDCTL45.Word -#define ATDCTL45_CA _ATDCTL45.Bits.CA -#define ATDCTL45_CB _ATDCTL45.Bits.CB -#define ATDCTL45_CC _ATDCTL45.Bits.CC -#define ATDCTL45_MULT _ATDCTL45.Bits.MULT -#define ATDCTL45_SCAN _ATDCTL45.Bits.SCAN -#define ATDCTL45_DSGN _ATDCTL45.Bits.DSGN -#define ATDCTL45_DJM _ATDCTL45.Bits.DJM -#define ATDCTL45_PRS0 _ATDCTL45.Bits.PRS0 -#define ATDCTL45_PRS1 _ATDCTL45.Bits.PRS1 -#define ATDCTL45_PRS2 _ATDCTL45.Bits.PRS2 -#define ATDCTL45_PRS3 _ATDCTL45.Bits.PRS3 -#define ATDCTL45_PRS4 _ATDCTL45.Bits.PRS4 -#define ATDCTL45_SMP0 _ATDCTL45.Bits.SMP0 -#define ATDCTL45_SMP1 _ATDCTL45.Bits.SMP1 -#define ATDCTL45_SRES8 _ATDCTL45.Bits.SRES8 -#define ATDCTL45_PRS _ATDCTL45.MergedBits.grpPRS -#define ATDCTL45_SMP _ATDCTL45.MergedBits.grpSMP - - -/*** ATDDR0 - A/D Conversion Result Register 0; 0x00000090 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** ATDDR0H - A/D Conversion Result Register 0 High; 0x00000090 ***/ - union { - byte Byte; - struct { - byte BIT8 :1; /* Bit 8 */ - byte BIT9 :1; /* Bit 9 */ - byte BIT10 :1; /* Bit 10 */ - byte BIT11 :1; /* Bit 11 */ - byte BIT12 :1; /* Bit 12 */ - byte BIT13 :1; /* Bit 13 */ - byte BIT14 :1; /* Bit 14 */ - byte BIT15 :1; /* Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; - } ATDDR0HSTR; - #define ATDDR0H _ATDDR0.Overlap_STR.ATDDR0HSTR.Byte - #define ATDDR0H_BIT8 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT8 - #define ATDDR0H_BIT9 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT9 - #define ATDDR0H_BIT10 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT10 - #define ATDDR0H_BIT11 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT11 - #define ATDDR0H_BIT12 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT12 - #define ATDDR0H_BIT13 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT13 - #define ATDDR0H_BIT14 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT14 - #define ATDDR0H_BIT15 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT15 - #define ATDDR0H_BIT_8 _ATDDR0.Overlap_STR.ATDDR0HSTR.MergedBits.grpBIT_8 - #define ATDDR0H_BIT ATDDR0H_BIT_8 - - /*** ATDDR0L - A/D Conversion Result Register 0 Low; 0x00000091 ***/ - union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte BIT6 :1; /* Bit 6 */ - byte BIT7 :1; /* Bit 7 */ - } Bits; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte grpBIT_6 :2; - } MergedBits; - } ATDDR0LSTR; - #define ATDDR0L _ATDDR0.Overlap_STR.ATDDR0LSTR.Byte - #define ATDDR0L_BIT6 _ATDDR0.Overlap_STR.ATDDR0LSTR.Bits.BIT6 - #define ATDDR0L_BIT7 _ATDDR0.Overlap_STR.ATDDR0LSTR.Bits.BIT7 - #define ATDDR0L_BIT_6 _ATDDR0.Overlap_STR.ATDDR0LSTR.MergedBits.grpBIT_6 - #define ATDDR0L_BIT ATDDR0L_BIT_6 - - } Overlap_STR; - - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word BIT6 :1; /* Bit 6 */ - word BIT7 :1; /* Bit 7 */ - word BIT8 :1; /* Bit 8 */ - word BIT9 :1; /* Bit 9 */ - word BIT10 :1; /* Bit 10 */ - word BIT11 :1; /* Bit 11 */ - word BIT12 :1; /* Bit 12 */ - word BIT13 :1; /* Bit 13 */ - word BIT14 :1; /* Bit 14 */ - word BIT15 :1; /* Bit 15 */ - } Bits; - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word grpBIT_6 :10; - } MergedBits; -} ATDDR0STR; -extern volatile ATDDR0STR _ATDDR0 @(REG_BASE + 0x00000090); -#define ATDDR0 _ATDDR0.Word -#define ATDDR0_BIT6 _ATDDR0.Bits.BIT6 -#define ATDDR0_BIT7 _ATDDR0.Bits.BIT7 -#define ATDDR0_BIT8 _ATDDR0.Bits.BIT8 -#define ATDDR0_BIT9 _ATDDR0.Bits.BIT9 -#define ATDDR0_BIT10 _ATDDR0.Bits.BIT10 -#define ATDDR0_BIT11 _ATDDR0.Bits.BIT11 -#define ATDDR0_BIT12 _ATDDR0.Bits.BIT12 -#define ATDDR0_BIT13 _ATDDR0.Bits.BIT13 -#define ATDDR0_BIT14 _ATDDR0.Bits.BIT14 -#define ATDDR0_BIT15 _ATDDR0.Bits.BIT15 -#define ATDDR0_BIT_6 _ATDDR0.MergedBits.grpBIT_6 -#define ATDDR0_BIT ATDDR0_BIT_6 - - -/*** ATDDR1 - A/D Conversion Result Register 1; 0x00000092 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** ATDDR1H - A/D Conversion Result Register 1 High; 0x00000092 ***/ - union { - byte Byte; - struct { - byte BIT8 :1; /* Bit 8 */ - byte BIT9 :1; /* Bit 9 */ - byte BIT10 :1; /* Bit 10 */ - byte BIT11 :1; /* Bit 11 */ - byte BIT12 :1; /* Bit 12 */ - byte BIT13 :1; /* Bit 13 */ - byte BIT14 :1; /* Bit 14 */ - byte BIT15 :1; /* Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; - } ATDDR1HSTR; - #define ATDDR1H _ATDDR1.Overlap_STR.ATDDR1HSTR.Byte - #define ATDDR1H_BIT8 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT8 - #define ATDDR1H_BIT9 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT9 - #define ATDDR1H_BIT10 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT10 - #define ATDDR1H_BIT11 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT11 - #define ATDDR1H_BIT12 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT12 - #define ATDDR1H_BIT13 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT13 - #define ATDDR1H_BIT14 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT14 - #define ATDDR1H_BIT15 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT15 - #define ATDDR1H_BIT_8 _ATDDR1.Overlap_STR.ATDDR1HSTR.MergedBits.grpBIT_8 - #define ATDDR1H_BIT ATDDR1H_BIT_8 - - /*** ATDDR1L - A/D Conversion Result Register 1 Low; 0x00000093 ***/ - union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte BIT6 :1; /* Bit 6 */ - byte BIT7 :1; /* Bit 7 */ - } Bits; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte grpBIT_6 :2; - } MergedBits; - } ATDDR1LSTR; - #define ATDDR1L _ATDDR1.Overlap_STR.ATDDR1LSTR.Byte - #define ATDDR1L_BIT6 _ATDDR1.Overlap_STR.ATDDR1LSTR.Bits.BIT6 - #define ATDDR1L_BIT7 _ATDDR1.Overlap_STR.ATDDR1LSTR.Bits.BIT7 - #define ATDDR1L_BIT_6 _ATDDR1.Overlap_STR.ATDDR1LSTR.MergedBits.grpBIT_6 - #define ATDDR1L_BIT ATDDR1L_BIT_6 - - } Overlap_STR; - - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word BIT6 :1; /* Bit 6 */ - word BIT7 :1; /* Bit 7 */ - word BIT8 :1; /* Bit 8 */ - word BIT9 :1; /* Bit 9 */ - word BIT10 :1; /* Bit 10 */ - word BIT11 :1; /* Bit 11 */ - word BIT12 :1; /* Bit 12 */ - word BIT13 :1; /* Bit 13 */ - word BIT14 :1; /* Bit 14 */ - word BIT15 :1; /* Bit 15 */ - } Bits; - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word grpBIT_6 :10; - } MergedBits; -} ATDDR1STR; -extern volatile ATDDR1STR _ATDDR1 @(REG_BASE + 0x00000092); -#define ATDDR1 _ATDDR1.Word -#define ATDDR1_BIT6 _ATDDR1.Bits.BIT6 -#define ATDDR1_BIT7 _ATDDR1.Bits.BIT7 -#define ATDDR1_BIT8 _ATDDR1.Bits.BIT8 -#define ATDDR1_BIT9 _ATDDR1.Bits.BIT9 -#define ATDDR1_BIT10 _ATDDR1.Bits.BIT10 -#define ATDDR1_BIT11 _ATDDR1.Bits.BIT11 -#define ATDDR1_BIT12 _ATDDR1.Bits.BIT12 -#define ATDDR1_BIT13 _ATDDR1.Bits.BIT13 -#define ATDDR1_BIT14 _ATDDR1.Bits.BIT14 -#define ATDDR1_BIT15 _ATDDR1.Bits.BIT15 -#define ATDDR1_BIT_6 _ATDDR1.MergedBits.grpBIT_6 -#define ATDDR1_BIT ATDDR1_BIT_6 - - -/*** ATDDR2 - A/D Conversion Result Register 2; 0x00000094 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** ATDDR2H - A/D Conversion Result Register 2 High; 0x00000094 ***/ - union { - byte Byte; - struct { - byte BIT8 :1; /* Bit 8 */ - byte BIT9 :1; /* Bit 9 */ - byte BIT10 :1; /* Bit 10 */ - byte BIT11 :1; /* Bit 11 */ - byte BIT12 :1; /* Bit 12 */ - byte BIT13 :1; /* Bit 13 */ - byte BIT14 :1; /* Bit 14 */ - byte BIT15 :1; /* Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; - } ATDDR2HSTR; - #define ATDDR2H _ATDDR2.Overlap_STR.ATDDR2HSTR.Byte - #define ATDDR2H_BIT8 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT8 - #define ATDDR2H_BIT9 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT9 - #define ATDDR2H_BIT10 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT10 - #define ATDDR2H_BIT11 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT11 - #define ATDDR2H_BIT12 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT12 - #define ATDDR2H_BIT13 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT13 - #define ATDDR2H_BIT14 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT14 - #define ATDDR2H_BIT15 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT15 - #define ATDDR2H_BIT_8 _ATDDR2.Overlap_STR.ATDDR2HSTR.MergedBits.grpBIT_8 - #define ATDDR2H_BIT ATDDR2H_BIT_8 - - /*** ATDDR2L - A/D Conversion Result Register 2 Low; 0x00000095 ***/ - union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte BIT6 :1; /* Bit 6 */ - byte BIT7 :1; /* Bit 7 */ - } Bits; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte grpBIT_6 :2; - } MergedBits; - } ATDDR2LSTR; - #define ATDDR2L _ATDDR2.Overlap_STR.ATDDR2LSTR.Byte - #define ATDDR2L_BIT6 _ATDDR2.Overlap_STR.ATDDR2LSTR.Bits.BIT6 - #define ATDDR2L_BIT7 _ATDDR2.Overlap_STR.ATDDR2LSTR.Bits.BIT7 - #define ATDDR2L_BIT_6 _ATDDR2.Overlap_STR.ATDDR2LSTR.MergedBits.grpBIT_6 - #define ATDDR2L_BIT ATDDR2L_BIT_6 - - } Overlap_STR; - - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word BIT6 :1; /* Bit 6 */ - word BIT7 :1; /* Bit 7 */ - word BIT8 :1; /* Bit 8 */ - word BIT9 :1; /* Bit 9 */ - word BIT10 :1; /* Bit 10 */ - word BIT11 :1; /* Bit 11 */ - word BIT12 :1; /* Bit 12 */ - word BIT13 :1; /* Bit 13 */ - word BIT14 :1; /* Bit 14 */ - word BIT15 :1; /* Bit 15 */ - } Bits; - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word grpBIT_6 :10; - } MergedBits; -} ATDDR2STR; -extern volatile ATDDR2STR _ATDDR2 @(REG_BASE + 0x00000094); -#define ATDDR2 _ATDDR2.Word -#define ATDDR2_BIT6 _ATDDR2.Bits.BIT6 -#define ATDDR2_BIT7 _ATDDR2.Bits.BIT7 -#define ATDDR2_BIT8 _ATDDR2.Bits.BIT8 -#define ATDDR2_BIT9 _ATDDR2.Bits.BIT9 -#define ATDDR2_BIT10 _ATDDR2.Bits.BIT10 -#define ATDDR2_BIT11 _ATDDR2.Bits.BIT11 -#define ATDDR2_BIT12 _ATDDR2.Bits.BIT12 -#define ATDDR2_BIT13 _ATDDR2.Bits.BIT13 -#define ATDDR2_BIT14 _ATDDR2.Bits.BIT14 -#define ATDDR2_BIT15 _ATDDR2.Bits.BIT15 -#define ATDDR2_BIT_6 _ATDDR2.MergedBits.grpBIT_6 -#define ATDDR2_BIT ATDDR2_BIT_6 - - -/*** ATDDR3 - A/D Conversion Result Register 3; 0x00000096 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** ATDDR3H - A/D Conversion Result Register 3 High; 0x00000096 ***/ - union { - byte Byte; - struct { - byte BIT8 :1; /* Bit 8 */ - byte BIT9 :1; /* Bit 9 */ - byte BIT10 :1; /* Bit 10 */ - byte BIT11 :1; /* Bit 11 */ - byte BIT12 :1; /* Bit 12 */ - byte BIT13 :1; /* Bit 13 */ - byte BIT14 :1; /* Bit 14 */ - byte BIT15 :1; /* Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; - } ATDDR3HSTR; - #define ATDDR3H _ATDDR3.Overlap_STR.ATDDR3HSTR.Byte - #define ATDDR3H_BIT8 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT8 - #define ATDDR3H_BIT9 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT9 - #define ATDDR3H_BIT10 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT10 - #define ATDDR3H_BIT11 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT11 - #define ATDDR3H_BIT12 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT12 - #define ATDDR3H_BIT13 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT13 - #define ATDDR3H_BIT14 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT14 - #define ATDDR3H_BIT15 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT15 - #define ATDDR3H_BIT_8 _ATDDR3.Overlap_STR.ATDDR3HSTR.MergedBits.grpBIT_8 - #define ATDDR3H_BIT ATDDR3H_BIT_8 - - /*** ATDDR3L - A/D Conversion Result Register 3 Low; 0x00000097 ***/ - union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte BIT6 :1; /* Bit 6 */ - byte BIT7 :1; /* Bit 7 */ - } Bits; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte grpBIT_6 :2; - } MergedBits; - } ATDDR3LSTR; - #define ATDDR3L _ATDDR3.Overlap_STR.ATDDR3LSTR.Byte - #define ATDDR3L_BIT6 _ATDDR3.Overlap_STR.ATDDR3LSTR.Bits.BIT6 - #define ATDDR3L_BIT7 _ATDDR3.Overlap_STR.ATDDR3LSTR.Bits.BIT7 - #define ATDDR3L_BIT_6 _ATDDR3.Overlap_STR.ATDDR3LSTR.MergedBits.grpBIT_6 - #define ATDDR3L_BIT ATDDR3L_BIT_6 - - } Overlap_STR; - - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word BIT6 :1; /* Bit 6 */ - word BIT7 :1; /* Bit 7 */ - word BIT8 :1; /* Bit 8 */ - word BIT9 :1; /* Bit 9 */ - word BIT10 :1; /* Bit 10 */ - word BIT11 :1; /* Bit 11 */ - word BIT12 :1; /* Bit 12 */ - word BIT13 :1; /* Bit 13 */ - word BIT14 :1; /* Bit 14 */ - word BIT15 :1; /* Bit 15 */ - } Bits; - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word grpBIT_6 :10; - } MergedBits; -} ATDDR3STR; -extern volatile ATDDR3STR _ATDDR3 @(REG_BASE + 0x00000096); -#define ATDDR3 _ATDDR3.Word -#define ATDDR3_BIT6 _ATDDR3.Bits.BIT6 -#define ATDDR3_BIT7 _ATDDR3.Bits.BIT7 -#define ATDDR3_BIT8 _ATDDR3.Bits.BIT8 -#define ATDDR3_BIT9 _ATDDR3.Bits.BIT9 -#define ATDDR3_BIT10 _ATDDR3.Bits.BIT10 -#define ATDDR3_BIT11 _ATDDR3.Bits.BIT11 -#define ATDDR3_BIT12 _ATDDR3.Bits.BIT12 -#define ATDDR3_BIT13 _ATDDR3.Bits.BIT13 -#define ATDDR3_BIT14 _ATDDR3.Bits.BIT14 -#define ATDDR3_BIT15 _ATDDR3.Bits.BIT15 -#define ATDDR3_BIT_6 _ATDDR3.MergedBits.grpBIT_6 -#define ATDDR3_BIT ATDDR3_BIT_6 - - -/*** ATDDR4 - A/D Conversion Result Register 4; 0x00000098 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** ATDDR4H - A/D Conversion Result Register 4 High; 0x00000098 ***/ - union { - byte Byte; - struct { - byte BIT8 :1; /* Bit 8 */ - byte BIT9 :1; /* Bit 9 */ - byte BIT10 :1; /* Bit 10 */ - byte BIT11 :1; /* Bit 11 */ - byte BIT12 :1; /* Bit 12 */ - byte BIT13 :1; /* Bit 13 */ - byte BIT14 :1; /* Bit 14 */ - byte BIT15 :1; /* Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; - } ATDDR4HSTR; - #define ATDDR4H _ATDDR4.Overlap_STR.ATDDR4HSTR.Byte - #define ATDDR4H_BIT8 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT8 - #define ATDDR4H_BIT9 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT9 - #define ATDDR4H_BIT10 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT10 - #define ATDDR4H_BIT11 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT11 - #define ATDDR4H_BIT12 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT12 - #define ATDDR4H_BIT13 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT13 - #define ATDDR4H_BIT14 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT14 - #define ATDDR4H_BIT15 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT15 - #define ATDDR4H_BIT_8 _ATDDR4.Overlap_STR.ATDDR4HSTR.MergedBits.grpBIT_8 - #define ATDDR4H_BIT ATDDR4H_BIT_8 - - /*** ATDDR4L - A/D Conversion Result Register 4 Low; 0x00000099 ***/ - union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte BIT6 :1; /* Bit 6 */ - byte BIT7 :1; /* Bit 7 */ - } Bits; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte grpBIT_6 :2; - } MergedBits; - } ATDDR4LSTR; - #define ATDDR4L _ATDDR4.Overlap_STR.ATDDR4LSTR.Byte - #define ATDDR4L_BIT6 _ATDDR4.Overlap_STR.ATDDR4LSTR.Bits.BIT6 - #define ATDDR4L_BIT7 _ATDDR4.Overlap_STR.ATDDR4LSTR.Bits.BIT7 - #define ATDDR4L_BIT_6 _ATDDR4.Overlap_STR.ATDDR4LSTR.MergedBits.grpBIT_6 - #define ATDDR4L_BIT ATDDR4L_BIT_6 - - } Overlap_STR; - - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word BIT6 :1; /* Bit 6 */ - word BIT7 :1; /* Bit 7 */ - word BIT8 :1; /* Bit 8 */ - word BIT9 :1; /* Bit 9 */ - word BIT10 :1; /* Bit 10 */ - word BIT11 :1; /* Bit 11 */ - word BIT12 :1; /* Bit 12 */ - word BIT13 :1; /* Bit 13 */ - word BIT14 :1; /* Bit 14 */ - word BIT15 :1; /* Bit 15 */ - } Bits; - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word grpBIT_6 :10; - } MergedBits; -} ATDDR4STR; -extern volatile ATDDR4STR _ATDDR4 @(REG_BASE + 0x00000098); -#define ATDDR4 _ATDDR4.Word -#define ATDDR4_BIT6 _ATDDR4.Bits.BIT6 -#define ATDDR4_BIT7 _ATDDR4.Bits.BIT7 -#define ATDDR4_BIT8 _ATDDR4.Bits.BIT8 -#define ATDDR4_BIT9 _ATDDR4.Bits.BIT9 -#define ATDDR4_BIT10 _ATDDR4.Bits.BIT10 -#define ATDDR4_BIT11 _ATDDR4.Bits.BIT11 -#define ATDDR4_BIT12 _ATDDR4.Bits.BIT12 -#define ATDDR4_BIT13 _ATDDR4.Bits.BIT13 -#define ATDDR4_BIT14 _ATDDR4.Bits.BIT14 -#define ATDDR4_BIT15 _ATDDR4.Bits.BIT15 -#define ATDDR4_BIT_6 _ATDDR4.MergedBits.grpBIT_6 -#define ATDDR4_BIT ATDDR4_BIT_6 - - -/*** ATDDR5 - A/D Conversion Result Register 5; 0x0000009A ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** ATDDR5H - A/D Conversion Result Register 5 High; 0x0000009A ***/ - union { - byte Byte; - struct { - byte BIT8 :1; /* Bit 8 */ - byte BIT9 :1; /* Bit 9 */ - byte BIT10 :1; /* Bit 10 */ - byte BIT11 :1; /* Bit 11 */ - byte BIT12 :1; /* Bit 12 */ - byte BIT13 :1; /* Bit 13 */ - byte BIT14 :1; /* Bit 14 */ - byte BIT15 :1; /* Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; - } ATDDR5HSTR; - #define ATDDR5H _ATDDR5.Overlap_STR.ATDDR5HSTR.Byte - #define ATDDR5H_BIT8 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT8 - #define ATDDR5H_BIT9 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT9 - #define ATDDR5H_BIT10 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT10 - #define ATDDR5H_BIT11 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT11 - #define ATDDR5H_BIT12 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT12 - #define ATDDR5H_BIT13 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT13 - #define ATDDR5H_BIT14 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT14 - #define ATDDR5H_BIT15 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT15 - #define ATDDR5H_BIT_8 _ATDDR5.Overlap_STR.ATDDR5HSTR.MergedBits.grpBIT_8 - #define ATDDR5H_BIT ATDDR5H_BIT_8 - - /*** ATDDR5L - A/D Conversion Result Register 5 Low; 0x0000009B ***/ - union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte BIT6 :1; /* Bit 6 */ - byte BIT7 :1; /* Bit 7 */ - } Bits; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte grpBIT_6 :2; - } MergedBits; - } ATDDR5LSTR; - #define ATDDR5L _ATDDR5.Overlap_STR.ATDDR5LSTR.Byte - #define ATDDR5L_BIT6 _ATDDR5.Overlap_STR.ATDDR5LSTR.Bits.BIT6 - #define ATDDR5L_BIT7 _ATDDR5.Overlap_STR.ATDDR5LSTR.Bits.BIT7 - #define ATDDR5L_BIT_6 _ATDDR5.Overlap_STR.ATDDR5LSTR.MergedBits.grpBIT_6 - #define ATDDR5L_BIT ATDDR5L_BIT_6 - - } Overlap_STR; - - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word BIT6 :1; /* Bit 6 */ - word BIT7 :1; /* Bit 7 */ - word BIT8 :1; /* Bit 8 */ - word BIT9 :1; /* Bit 9 */ - word BIT10 :1; /* Bit 10 */ - word BIT11 :1; /* Bit 11 */ - word BIT12 :1; /* Bit 12 */ - word BIT13 :1; /* Bit 13 */ - word BIT14 :1; /* Bit 14 */ - word BIT15 :1; /* Bit 15 */ - } Bits; - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word grpBIT_6 :10; - } MergedBits; -} ATDDR5STR; -extern volatile ATDDR5STR _ATDDR5 @(REG_BASE + 0x0000009A); -#define ATDDR5 _ATDDR5.Word -#define ATDDR5_BIT6 _ATDDR5.Bits.BIT6 -#define ATDDR5_BIT7 _ATDDR5.Bits.BIT7 -#define ATDDR5_BIT8 _ATDDR5.Bits.BIT8 -#define ATDDR5_BIT9 _ATDDR5.Bits.BIT9 -#define ATDDR5_BIT10 _ATDDR5.Bits.BIT10 -#define ATDDR5_BIT11 _ATDDR5.Bits.BIT11 -#define ATDDR5_BIT12 _ATDDR5.Bits.BIT12 -#define ATDDR5_BIT13 _ATDDR5.Bits.BIT13 -#define ATDDR5_BIT14 _ATDDR5.Bits.BIT14 -#define ATDDR5_BIT15 _ATDDR5.Bits.BIT15 -#define ATDDR5_BIT_6 _ATDDR5.MergedBits.grpBIT_6 -#define ATDDR5_BIT ATDDR5_BIT_6 - - -/*** ATDDR6 - A/D Conversion Result Register 6; 0x0000009C ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** ATDDR6H - A/D Conversion Result Register 6 High; 0x0000009C ***/ - union { - byte Byte; - struct { - byte BIT8 :1; /* Bit 8 */ - byte BIT9 :1; /* Bit 9 */ - byte BIT10 :1; /* Bit 10 */ - byte BIT11 :1; /* Bit 11 */ - byte BIT12 :1; /* Bit 12 */ - byte BIT13 :1; /* Bit 13 */ - byte BIT14 :1; /* Bit 14 */ - byte BIT15 :1; /* Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; - } ATDDR6HSTR; - #define ATDDR6H _ATDDR6.Overlap_STR.ATDDR6HSTR.Byte - #define ATDDR6H_BIT8 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT8 - #define ATDDR6H_BIT9 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT9 - #define ATDDR6H_BIT10 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT10 - #define ATDDR6H_BIT11 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT11 - #define ATDDR6H_BIT12 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT12 - #define ATDDR6H_BIT13 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT13 - #define ATDDR6H_BIT14 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT14 - #define ATDDR6H_BIT15 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT15 - #define ATDDR6H_BIT_8 _ATDDR6.Overlap_STR.ATDDR6HSTR.MergedBits.grpBIT_8 - #define ATDDR6H_BIT ATDDR6H_BIT_8 - - /*** ATDDR6L - A/D Conversion Result Register 6 Low; 0x0000009D ***/ - union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte BIT6 :1; /* Bit 6 */ - byte BIT7 :1; /* Bit 7 */ - } Bits; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte grpBIT_6 :2; - } MergedBits; - } ATDDR6LSTR; - #define ATDDR6L _ATDDR6.Overlap_STR.ATDDR6LSTR.Byte - #define ATDDR6L_BIT6 _ATDDR6.Overlap_STR.ATDDR6LSTR.Bits.BIT6 - #define ATDDR6L_BIT7 _ATDDR6.Overlap_STR.ATDDR6LSTR.Bits.BIT7 - #define ATDDR6L_BIT_6 _ATDDR6.Overlap_STR.ATDDR6LSTR.MergedBits.grpBIT_6 - #define ATDDR6L_BIT ATDDR6L_BIT_6 - - } Overlap_STR; - - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word BIT6 :1; /* Bit 6 */ - word BIT7 :1; /* Bit 7 */ - word BIT8 :1; /* Bit 8 */ - word BIT9 :1; /* Bit 9 */ - word BIT10 :1; /* Bit 10 */ - word BIT11 :1; /* Bit 11 */ - word BIT12 :1; /* Bit 12 */ - word BIT13 :1; /* Bit 13 */ - word BIT14 :1; /* Bit 14 */ - word BIT15 :1; /* Bit 15 */ - } Bits; - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word grpBIT_6 :10; - } MergedBits; -} ATDDR6STR; -extern volatile ATDDR6STR _ATDDR6 @(REG_BASE + 0x0000009C); -#define ATDDR6 _ATDDR6.Word -#define ATDDR6_BIT6 _ATDDR6.Bits.BIT6 -#define ATDDR6_BIT7 _ATDDR6.Bits.BIT7 -#define ATDDR6_BIT8 _ATDDR6.Bits.BIT8 -#define ATDDR6_BIT9 _ATDDR6.Bits.BIT9 -#define ATDDR6_BIT10 _ATDDR6.Bits.BIT10 -#define ATDDR6_BIT11 _ATDDR6.Bits.BIT11 -#define ATDDR6_BIT12 _ATDDR6.Bits.BIT12 -#define ATDDR6_BIT13 _ATDDR6.Bits.BIT13 -#define ATDDR6_BIT14 _ATDDR6.Bits.BIT14 -#define ATDDR6_BIT15 _ATDDR6.Bits.BIT15 -#define ATDDR6_BIT_6 _ATDDR6.MergedBits.grpBIT_6 -#define ATDDR6_BIT ATDDR6_BIT_6 - - -/*** ATDDR7 - A/D Conversion Result Register 7; 0x0000009E ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** ATDDR7H - A/D Conversion Result Register 7 High; 0x0000009E ***/ - union { - byte Byte; - struct { - byte BIT8 :1; /* Bit 8 */ - byte BIT9 :1; /* Bit 9 */ - byte BIT10 :1; /* Bit 10 */ - byte BIT11 :1; /* Bit 11 */ - byte BIT12 :1; /* Bit 12 */ - byte BIT13 :1; /* Bit 13 */ - byte BIT14 :1; /* Bit 14 */ - byte BIT15 :1; /* Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; - } ATDDR7HSTR; - #define ATDDR7H _ATDDR7.Overlap_STR.ATDDR7HSTR.Byte - #define ATDDR7H_BIT8 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT8 - #define ATDDR7H_BIT9 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT9 - #define ATDDR7H_BIT10 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT10 - #define ATDDR7H_BIT11 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT11 - #define ATDDR7H_BIT12 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT12 - #define ATDDR7H_BIT13 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT13 - #define ATDDR7H_BIT14 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT14 - #define ATDDR7H_BIT15 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT15 - #define ATDDR7H_BIT_8 _ATDDR7.Overlap_STR.ATDDR7HSTR.MergedBits.grpBIT_8 - #define ATDDR7H_BIT ATDDR7H_BIT_8 - - /*** ATDDR7L - A/D Conversion Result Register 7 Low; 0x0000009F ***/ - union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte BIT6 :1; /* Bit 6 */ - byte BIT7 :1; /* Bit 7 */ - } Bits; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte grpBIT_6 :2; - } MergedBits; - } ATDDR7LSTR; - #define ATDDR7L _ATDDR7.Overlap_STR.ATDDR7LSTR.Byte - #define ATDDR7L_BIT6 _ATDDR7.Overlap_STR.ATDDR7LSTR.Bits.BIT6 - #define ATDDR7L_BIT7 _ATDDR7.Overlap_STR.ATDDR7LSTR.Bits.BIT7 - #define ATDDR7L_BIT_6 _ATDDR7.Overlap_STR.ATDDR7LSTR.MergedBits.grpBIT_6 - #define ATDDR7L_BIT ATDDR7L_BIT_6 - - } Overlap_STR; - - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word BIT6 :1; /* Bit 6 */ - word BIT7 :1; /* Bit 7 */ - word BIT8 :1; /* Bit 8 */ - word BIT9 :1; /* Bit 9 */ - word BIT10 :1; /* Bit 10 */ - word BIT11 :1; /* Bit 11 */ - word BIT12 :1; /* Bit 12 */ - word BIT13 :1; /* Bit 13 */ - word BIT14 :1; /* Bit 14 */ - word BIT15 :1; /* Bit 15 */ - } Bits; - struct { - word :1; - word :1; - word :1; - word :1; - word :1; - word :1; - word grpBIT_6 :10; - } MergedBits; -} ATDDR7STR; -extern volatile ATDDR7STR _ATDDR7 @(REG_BASE + 0x0000009E); -#define ATDDR7 _ATDDR7.Word -#define ATDDR7_BIT6 _ATDDR7.Bits.BIT6 -#define ATDDR7_BIT7 _ATDDR7.Bits.BIT7 -#define ATDDR7_BIT8 _ATDDR7.Bits.BIT8 -#define ATDDR7_BIT9 _ATDDR7.Bits.BIT9 -#define ATDDR7_BIT10 _ATDDR7.Bits.BIT10 -#define ATDDR7_BIT11 _ATDDR7.Bits.BIT11 -#define ATDDR7_BIT12 _ATDDR7.Bits.BIT12 -#define ATDDR7_BIT13 _ATDDR7.Bits.BIT13 -#define ATDDR7_BIT14 _ATDDR7.Bits.BIT14 -#define ATDDR7_BIT15 _ATDDR7.Bits.BIT15 -#define ATDDR7_BIT_6 _ATDDR7.MergedBits.grpBIT_6 -#define ATDDR7_BIT ATDDR7_BIT_6 - - -/*** SCIBD - SCI Baud Rate Register; 0x000000C8 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** SCIBDH - SCI Baud Rate Register High; 0x000000C8 ***/ - union { - byte Byte; - struct { - byte SBR8 :1; /* SCI baud rate Bit 8 */ - byte SBR9 :1; /* SCI baud rate Bit 9 */ - byte SBR10 :1; /* SCI baud rate Bit 10 */ - byte SBR11 :1; /* SCI baud rate Bit 11 */ - byte SBR12 :1; /* SCI baud rate Bit 12 */ - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpSBR_8 :5; - byte :1; - byte :1; - byte :1; - } MergedBits; - } SCIBDHSTR; - #define SCIBDH _SCIBD.Overlap_STR.SCIBDHSTR.Byte - #define SCIBDH_SBR8 _SCIBD.Overlap_STR.SCIBDHSTR.Bits.SBR8 - #define SCIBDH_SBR9 _SCIBD.Overlap_STR.SCIBDHSTR.Bits.SBR9 - #define SCIBDH_SBR10 _SCIBD.Overlap_STR.SCIBDHSTR.Bits.SBR10 - #define SCIBDH_SBR11 _SCIBD.Overlap_STR.SCIBDHSTR.Bits.SBR11 - #define SCIBDH_SBR12 _SCIBD.Overlap_STR.SCIBDHSTR.Bits.SBR12 - #define SCIBDH_SBR_8 _SCIBD.Overlap_STR.SCIBDHSTR.MergedBits.grpSBR_8 - #define SCIBDH_SBR SCIBDH_SBR_8 - - /*** SCIBDL - SCI Baud Rate Register Low; 0x000000C9 ***/ - union { - byte Byte; - struct { - byte SBR0 :1; /* SCI baud rate Bit 0 */ - byte SBR1 :1; /* SCI baud rate Bit 1 */ - byte SBR2 :1; /* SCI baud rate Bit 2 */ - byte SBR3 :1; /* SCI baud rate Bit 3 */ - byte SBR4 :1; /* SCI baud rate Bit 4 */ - byte SBR5 :1; /* SCI baud rate Bit 5 */ - byte SBR6 :1; /* SCI baud rate Bit 6 */ - byte SBR7 :1; /* SCI baud rate Bit 7 */ - } Bits; - struct { - byte grpSBR :8; - } MergedBits; - } SCIBDLSTR; - #define SCIBDL _SCIBD.Overlap_STR.SCIBDLSTR.Byte - #define SCIBDL_SBR0 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR0 - #define SCIBDL_SBR1 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR1 - #define SCIBDL_SBR2 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR2 - #define SCIBDL_SBR3 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR3 - #define SCIBDL_SBR4 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR4 - #define SCIBDL_SBR5 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR5 - #define SCIBDL_SBR6 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR6 - #define SCIBDL_SBR7 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR7 - #define SCIBDL_SBR _SCIBD.Overlap_STR.SCIBDLSTR.MergedBits.grpSBR - - } Overlap_STR; - - struct { - word SBR0 :1; /* SCI baud rate Bit 0 */ - word SBR1 :1; /* SCI baud rate Bit 1 */ - word SBR2 :1; /* SCI baud rate Bit 2 */ - word SBR3 :1; /* SCI baud rate Bit 3 */ - word SBR4 :1; /* SCI baud rate Bit 4 */ - word SBR5 :1; /* SCI baud rate Bit 5 */ - word SBR6 :1; /* SCI baud rate Bit 6 */ - word SBR7 :1; /* SCI baud rate Bit 7 */ - word SBR8 :1; /* SCI baud rate Bit 8 */ - word SBR9 :1; /* SCI baud rate Bit 9 */ - word SBR10 :1; /* SCI baud rate Bit 10 */ - word SBR11 :1; /* SCI baud rate Bit 11 */ - word SBR12 :1; /* SCI baud rate Bit 12 */ - word :1; - word :1; - word :1; - } Bits; - struct { - word grpSBR :13; - word :1; - word :1; - word :1; - } MergedBits; -} SCIBDSTR; -extern volatile SCIBDSTR _SCIBD @(REG_BASE + 0x000000C8); -#define SCIBD _SCIBD.Word -#define SCIBD_SBR0 _SCIBD.Bits.SBR0 -#define SCIBD_SBR1 _SCIBD.Bits.SBR1 -#define SCIBD_SBR2 _SCIBD.Bits.SBR2 -#define SCIBD_SBR3 _SCIBD.Bits.SBR3 -#define SCIBD_SBR4 _SCIBD.Bits.SBR4 -#define SCIBD_SBR5 _SCIBD.Bits.SBR5 -#define SCIBD_SBR6 _SCIBD.Bits.SBR6 -#define SCIBD_SBR7 _SCIBD.Bits.SBR7 -#define SCIBD_SBR8 _SCIBD.Bits.SBR8 -#define SCIBD_SBR9 _SCIBD.Bits.SBR9 -#define SCIBD_SBR10 _SCIBD.Bits.SBR10 -#define SCIBD_SBR11 _SCIBD.Bits.SBR11 -#define SCIBD_SBR12 _SCIBD.Bits.SBR12 -#define SCIBD_SBR _SCIBD.MergedBits.grpSBR - - -/*** PWMCNT01 - PWM Channel Counter 01 Register; 0x000000EC ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** PWMCNT0 - PWM Channel Counter 0 Register; 0x000000EC ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PWMCNT0STR; - #define PWMCNT0 _PWMCNT01.Overlap_STR.PWMCNT0STR.Byte - #define PWMCNT0_BIT _PWMCNT01.Overlap_STR.PWMCNT0STR.MergedBits.grpBIT - - /*** PWMCNT1 - PWM Channel Counter 1 Register; 0x000000ED ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PWMCNT1STR; - #define PWMCNT1 _PWMCNT01.Overlap_STR.PWMCNT1STR.Byte - #define PWMCNT1_BIT _PWMCNT01.Overlap_STR.PWMCNT1STR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word grpBIT :16; - } MergedBits; -} PWMCNT01STR; -extern volatile PWMCNT01STR _PWMCNT01 @(REG_BASE + 0x000000EC); -#define PWMCNT01 _PWMCNT01.Word -#define PWMCNT01_BIT _PWMCNT01.MergedBits.grpBIT - - -/*** PWMCNT23 - PWM Channel Counter 23 Register; 0x000000EE ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** PWMCNT2 - PWM Channel Counter 2 Register; 0x000000EE ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PWMCNT2STR; - #define PWMCNT2 _PWMCNT23.Overlap_STR.PWMCNT2STR.Byte - #define PWMCNT2_BIT _PWMCNT23.Overlap_STR.PWMCNT2STR.MergedBits.grpBIT - - /*** PWMCNT3 - PWM Channel Counter 3 Register; 0x000000EF ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PWMCNT3STR; - #define PWMCNT3 _PWMCNT23.Overlap_STR.PWMCNT3STR.Byte - #define PWMCNT3_BIT _PWMCNT23.Overlap_STR.PWMCNT3STR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word grpBIT :16; - } MergedBits; -} PWMCNT23STR; -extern volatile PWMCNT23STR _PWMCNT23 @(REG_BASE + 0x000000EE); -#define PWMCNT23 _PWMCNT23.Word -#define PWMCNT23_BIT _PWMCNT23.MergedBits.grpBIT - - -/*** PWMCNT45 - PWM Channel Counter 45 Register; 0x000000F0 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** PWMCNT4 - PWM Channel Counter 4 Register; 0x000000F0 ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PWMCNT4STR; - #define PWMCNT4 _PWMCNT45.Overlap_STR.PWMCNT4STR.Byte - #define PWMCNT4_BIT _PWMCNT45.Overlap_STR.PWMCNT4STR.MergedBits.grpBIT - - /*** PWMCNT5 - PWM Channel Counter 5 Register; 0x000000F1 ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PWMCNT5STR; - #define PWMCNT5 _PWMCNT45.Overlap_STR.PWMCNT5STR.Byte - #define PWMCNT5_BIT _PWMCNT45.Overlap_STR.PWMCNT5STR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word grpBIT :16; - } MergedBits; -} PWMCNT45STR; -extern volatile PWMCNT45STR _PWMCNT45 @(REG_BASE + 0x000000F0); -#define PWMCNT45 _PWMCNT45.Word -#define PWMCNT45_BIT _PWMCNT45.MergedBits.grpBIT - - -/*** PWMPER01 - PWM Channel Period 01 Register; 0x000000F2 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** PWMPER0 - PWM Channel Period 0 Register; 0x000000F2 ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PWMPER0STR; - #define PWMPER0 _PWMPER01.Overlap_STR.PWMPER0STR.Byte - #define PWMPER0_BIT _PWMPER01.Overlap_STR.PWMPER0STR.MergedBits.grpBIT - - /*** PWMPER1 - PWM Channel Period 1 Register; 0x000000F3 ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PWMPER1STR; - #define PWMPER1 _PWMPER01.Overlap_STR.PWMPER1STR.Byte - #define PWMPER1_BIT _PWMPER01.Overlap_STR.PWMPER1STR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word grpBIT :16; - } MergedBits; -} PWMPER01STR; -extern volatile PWMPER01STR _PWMPER01 @(REG_BASE + 0x000000F2); -#define PWMPER01 _PWMPER01.Word -#define PWMPER01_BIT _PWMPER01.MergedBits.grpBIT - - -/*** PWMPER23 - PWM Channel Period 23 Register; 0x000000F4 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** PWMPER2 - PWM Channel Period 2 Register; 0x000000F4 ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PWMPER2STR; - #define PWMPER2 _PWMPER23.Overlap_STR.PWMPER2STR.Byte - #define PWMPER2_BIT _PWMPER23.Overlap_STR.PWMPER2STR.MergedBits.grpBIT - - /*** PWMPER3 - PWM Channel Period 3 Register; 0x000000F5 ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PWMPER3STR; - #define PWMPER3 _PWMPER23.Overlap_STR.PWMPER3STR.Byte - #define PWMPER3_BIT _PWMPER23.Overlap_STR.PWMPER3STR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word grpBIT :16; - } MergedBits; -} PWMPER23STR; -extern volatile PWMPER23STR _PWMPER23 @(REG_BASE + 0x000000F4); -#define PWMPER23 _PWMPER23.Word -#define PWMPER23_BIT _PWMPER23.MergedBits.grpBIT - - -/*** PWMPER45 - PWM Channel Period 45 Register; 0x000000F6 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** PWMPER4 - PWM Channel Period 4 Register; 0x000000F6 ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PWMPER4STR; - #define PWMPER4 _PWMPER45.Overlap_STR.PWMPER4STR.Byte - #define PWMPER4_BIT _PWMPER45.Overlap_STR.PWMPER4STR.MergedBits.grpBIT - - /*** PWMPER5 - PWM Channel Period 5 Register; 0x000000F7 ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PWMPER5STR; - #define PWMPER5 _PWMPER45.Overlap_STR.PWMPER5STR.Byte - #define PWMPER5_BIT _PWMPER45.Overlap_STR.PWMPER5STR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word grpBIT :16; - } MergedBits; -} PWMPER45STR; -extern volatile PWMPER45STR _PWMPER45 @(REG_BASE + 0x000000F6); -#define PWMPER45 _PWMPER45.Word -#define PWMPER45_BIT _PWMPER45.MergedBits.grpBIT - - -/*** PWMDTY01 - PWM Channel Duty 01 Register; 0x000000F8 ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** PWMDTY0 - PWM Channel Duty 0 Register; 0x000000F8 ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PWMDTY0STR; - #define PWMDTY0 _PWMDTY01.Overlap_STR.PWMDTY0STR.Byte - #define PWMDTY0_BIT _PWMDTY01.Overlap_STR.PWMDTY0STR.MergedBits.grpBIT - - /*** PWMDTY1 - PWM Channel Duty 1 Register; 0x000000F9 ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PWMDTY1STR; - #define PWMDTY1 _PWMDTY01.Overlap_STR.PWMDTY1STR.Byte - #define PWMDTY1_BIT _PWMDTY01.Overlap_STR.PWMDTY1STR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word grpBIT :16; - } MergedBits; -} PWMDTY01STR; -extern volatile PWMDTY01STR _PWMDTY01 @(REG_BASE + 0x000000F8); -#define PWMDTY01 _PWMDTY01.Word -#define PWMDTY01_BIT _PWMDTY01.MergedBits.grpBIT - - -/*** PWMDTY23 - PWM Channel Duty 23 Register; 0x000000FA ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** PWMDTY2 - PWM Channel Duty 2 Register; 0x000000FA ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PWMDTY2STR; - #define PWMDTY2 _PWMDTY23.Overlap_STR.PWMDTY2STR.Byte - #define PWMDTY2_BIT _PWMDTY23.Overlap_STR.PWMDTY2STR.MergedBits.grpBIT - - /*** PWMDTY3 - PWM Channel Duty 3 Register; 0x000000FB ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PWMDTY3STR; - #define PWMDTY3 _PWMDTY23.Overlap_STR.PWMDTY3STR.Byte - #define PWMDTY3_BIT _PWMDTY23.Overlap_STR.PWMDTY3STR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word grpBIT :16; - } MergedBits; -} PWMDTY23STR; -extern volatile PWMDTY23STR _PWMDTY23 @(REG_BASE + 0x000000FA); -#define PWMDTY23 _PWMDTY23.Word -#define PWMDTY23_BIT _PWMDTY23.MergedBits.grpBIT - - -/*** PWMDTY45 - PWM Channel Duty 45 Register; 0x000000FC ***/ -typedef union { - word Word; - /* Overlapped registers: */ - struct { - /*** PWMDTY4 - PWM Channel Duty 4 Register; 0x000000FC ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PWMDTY4STR; - #define PWMDTY4 _PWMDTY45.Overlap_STR.PWMDTY4STR.Byte - #define PWMDTY4_BIT _PWMDTY45.Overlap_STR.PWMDTY4STR.MergedBits.grpBIT - - /*** PWMDTY5 - PWM Channel Duty 5 Register; 0x000000FD ***/ - union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; - } PWMDTY5STR; - #define PWMDTY5 _PWMDTY45.Overlap_STR.PWMDTY5STR.Byte - #define PWMDTY5_BIT _PWMDTY45.Overlap_STR.PWMDTY5STR.MergedBits.grpBIT - - } Overlap_STR; - - struct { - word grpBIT :16; - } MergedBits; -} PWMDTY45STR; -extern volatile PWMDTY45STR _PWMDTY45 @(REG_BASE + 0x000000FC); -#define PWMDTY45 _PWMDTY45.Word -#define PWMDTY45_BIT _PWMDTY45.MergedBits.grpBIT - - -/*** PORTE - Port E Register; 0x00000008 ***/ -typedef union { - byte Byte; - struct { - byte BIT0 :1; /* Port E Bit 0 */ - byte BIT1 :1; /* Port E Bit 1 */ - byte BIT2 :1; /* Port E Bit 2 */ - byte BIT3 :1; /* Port E Bit 3 */ - byte BIT4 :1; /* Port E Bit 4 */ - byte BIT5 :1; /* Port E Bit 5 */ - byte BIT6 :1; /* Port E Bit 6 */ - byte BIT7 :1; /* Port E Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; -} PORTESTR; -extern volatile PORTESTR _PORTE @(REG_BASE + 0x00000008); -#define PORTE _PORTE.Byte -#define PORTE_BIT0 _PORTE.Bits.BIT0 -#define PORTE_BIT1 _PORTE.Bits.BIT1 -#define PORTE_BIT2 _PORTE.Bits.BIT2 -#define PORTE_BIT3 _PORTE.Bits.BIT3 -#define PORTE_BIT4 _PORTE.Bits.BIT4 -#define PORTE_BIT5 _PORTE.Bits.BIT5 -#define PORTE_BIT6 _PORTE.Bits.BIT6 -#define PORTE_BIT7 _PORTE.Bits.BIT7 -#define PORTE_BIT _PORTE.MergedBits.grpBIT - - -/*** DDRE - Port E Data Direction Register; 0x00000009 ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte :1; - byte BIT2 :1; /* Data Direction Port A Bit 2 */ - byte BIT3 :1; /* Data Direction Port A Bit 3 */ - byte BIT4 :1; /* Data Direction Port A Bit 4 */ - byte BIT5 :1; /* Data Direction Port A Bit 5 */ - byte BIT6 :1; /* Data Direction Port A Bit 6 */ - byte BIT7 :1; /* Data Direction Port A Bit 7 */ - } Bits; - struct { - byte :1; - byte :1; - byte grpBIT_2 :6; - } MergedBits; -} DDRESTR; -extern volatile DDRESTR _DDRE @(REG_BASE + 0x00000009); -#define DDRE _DDRE.Byte -#define DDRE_BIT2 _DDRE.Bits.BIT2 -#define DDRE_BIT3 _DDRE.Bits.BIT3 -#define DDRE_BIT4 _DDRE.Bits.BIT4 -#define DDRE_BIT5 _DDRE.Bits.BIT5 -#define DDRE_BIT6 _DDRE.Bits.BIT6 -#define DDRE_BIT7 _DDRE.Bits.BIT7 -#define DDRE_BIT_2 _DDRE.MergedBits.grpBIT_2 -#define DDRE_BIT DDRE_BIT_2 - - -/*** PEAR - Port E Assignment Register; 0x0000000A ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte :1; - byte RDWE :1; /* Read / Write Enable */ - byte LSTRE :1; /* Low Strobe (LSTRB) Enable */ - byte NECLK :1; /* No External E Clock */ - byte PIPOE :1; /* Pipe Status Signal Output Enable */ - byte :1; - byte NOACCE :1; /* CPU No Access Output Enable */ - } Bits; -} PEARSTR; -extern volatile PEARSTR _PEAR @(REG_BASE + 0x0000000A); -#define PEAR _PEAR.Byte -#define PEAR_RDWE _PEAR.Bits.RDWE -#define PEAR_LSTRE _PEAR.Bits.LSTRE -#define PEAR_NECLK _PEAR.Bits.NECLK -#define PEAR_PIPOE _PEAR.Bits.PIPOE -#define PEAR_NOACCE _PEAR.Bits.NOACCE - - -/*** MODE - Mode Register; 0x0000000B ***/ -typedef union { - byte Byte; - struct { - byte EME :1; /* Emulate Port E */ - byte EMK :1; /* Emulate Port K */ - byte :1; - byte IVIS :1; /* Internal Visibility */ - byte :1; - byte MODA :1; /* Mode Select Bit A */ - byte MODB :1; /* Mode Select Bit B */ - byte MODC :1; /* Mode Select Bit C */ - } Bits; -} MODESTR; -extern volatile MODESTR _MODE @(REG_BASE + 0x0000000B); -#define MODE _MODE.Byte -#define MODE_EME _MODE.Bits.EME -#define MODE_EMK _MODE.Bits.EMK -#define MODE_IVIS _MODE.Bits.IVIS -#define MODE_MODA _MODE.Bits.MODA -#define MODE_MODB _MODE.Bits.MODB -#define MODE_MODC _MODE.Bits.MODC - - -/*** PUCR - Pull-Up Control Register; 0x0000000C ***/ -typedef union { - byte Byte; - struct { - byte PUPAE :1; /* Pull-Up Port A Enable */ - byte PUPBE :1; /* Pull-Up Port B Enable */ - byte :1; - byte :1; - byte PUPEE :1; /* Pull-Up Port E Enable */ - byte :1; - byte :1; - byte PUPKE :1; /* Pull-Up Port K Enable */ - } Bits; -} PUCRSTR; -extern volatile PUCRSTR _PUCR @(REG_BASE + 0x0000000C); -#define PUCR _PUCR.Byte -#define PUCR_PUPAE _PUCR.Bits.PUPAE -#define PUCR_PUPBE _PUCR.Bits.PUPBE -#define PUCR_PUPEE _PUCR.Bits.PUPEE -#define PUCR_PUPKE _PUCR.Bits.PUPKE - - -/*** RDRIV - Reduced Drive of I/O Lines; 0x0000000D ***/ -typedef union { - byte Byte; - struct { - byte RDPA :1; /* Reduced Drive of Port A */ - byte RDPB :1; /* Reduced Drive of Port B */ - byte :1; - byte :1; - byte RDPE :1; /* Reduced Drive of Port E */ - byte :1; - byte :1; - byte RDPK :1; /* Reduced Drive of Port K */ - } Bits; -} RDRIVSTR; -extern volatile RDRIVSTR _RDRIV @(REG_BASE + 0x0000000D); -#define RDRIV _RDRIV.Byte -#define RDRIV_RDPA _RDRIV.Bits.RDPA -#define RDRIV_RDPB _RDRIV.Bits.RDPB -#define RDRIV_RDPE _RDRIV.Bits.RDPE -#define RDRIV_RDPK _RDRIV.Bits.RDPK - - -/*** EBICTL - External Bus Interface Control; 0x0000000E ***/ -typedef union { - byte Byte; - struct { - byte ESTR :1; /* E Stretches */ - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; -} EBICTLSTR; -extern volatile EBICTLSTR _EBICTL @(REG_BASE + 0x0000000E); -#define EBICTL _EBICTL.Byte -#define EBICTL_ESTR _EBICTL.Bits.ESTR - - -/*** INITRM - Initialization of Internal RAM Position Register; 0x00000010 ***/ -typedef union { - byte Byte; - struct { - byte RAMHAL :1; /* Internal RAM map alignment */ - byte :1; - byte :1; - byte RAM11 :1; /* Internal RAM map position Bit 11 */ - byte RAM12 :1; /* Internal RAM map position Bit 12 */ - byte RAM13 :1; /* Internal RAM map position Bit 13 */ - byte RAM14 :1; /* Internal RAM map position Bit 14 */ - byte RAM15 :1; /* Internal RAM map position Bit 15 */ - } Bits; - struct { - byte :1; - byte :1; - byte :1; - byte grpRAM_11 :5; - } MergedBits; -} INITRMSTR; -extern volatile INITRMSTR _INITRM @(REG_BASE + 0x00000010); -#define INITRM _INITRM.Byte -#define INITRM_RAMHAL _INITRM.Bits.RAMHAL -#define INITRM_RAM11 _INITRM.Bits.RAM11 -#define INITRM_RAM12 _INITRM.Bits.RAM12 -#define INITRM_RAM13 _INITRM.Bits.RAM13 -#define INITRM_RAM14 _INITRM.Bits.RAM14 -#define INITRM_RAM15 _INITRM.Bits.RAM15 -#define INITRM_RAM_11 _INITRM.MergedBits.grpRAM_11 -#define INITRM_RAM INITRM_RAM_11 - - -/*** INITRG - Initialization of Internal Register Position Register; 0x00000011 ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte REG11 :1; /* Internal register map position REG11 */ - byte REG12 :1; /* Internal register map position REG12 */ - byte REG13 :1; /* Internal register map position REG13 */ - byte REG14 :1; /* Internal register map position REG14 */ - byte :1; - } Bits; - struct { - byte :1; - byte :1; - byte :1; - byte grpREG_11 :4; - byte :1; - } MergedBits; -} INITRGSTR; -extern volatile INITRGSTR _INITRG @(REG_BASE + 0x00000011); -#define INITRG _INITRG.Byte -#define INITRG_REG11 _INITRG.Bits.REG11 -#define INITRG_REG12 _INITRG.Bits.REG12 -#define INITRG_REG13 _INITRG.Bits.REG13 -#define INITRG_REG14 _INITRG.Bits.REG14 -#define INITRG_REG_11 _INITRG.MergedBits.grpREG_11 -#define INITRG_REG INITRG_REG_11 - - -/*** INITEE - Initialization of Internal EEPROM Position Register; 0x00000012 ***/ -typedef union { - byte Byte; - struct { - byte EEON :1; /* Internal EEPROM On */ - byte :1; - byte :1; - byte :1; - byte EE12 :1; /* Internal EEPROM map position Bit 12 */ - byte EE13 :1; /* Internal EEPROM map position Bit 13 */ - byte EE14 :1; /* Internal EEPROM map position Bit 14 */ - byte EE15 :1; /* Internal EEPROM map position Bit 15 */ - } Bits; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte grpEE_12 :4; - } MergedBits; -} INITEESTR; -extern volatile INITEESTR _INITEE @(REG_BASE + 0x00000012); -#define INITEE _INITEE.Byte -#define INITEE_EEON _INITEE.Bits.EEON -#define INITEE_EE12 _INITEE.Bits.EE12 -#define INITEE_EE13 _INITEE.Bits.EE13 -#define INITEE_EE14 _INITEE.Bits.EE14 -#define INITEE_EE15 _INITEE.Bits.EE15 -#define INITEE_EE_12 _INITEE.MergedBits.grpEE_12 -#define INITEE_EE INITEE_EE_12 - - -/*** MISC - Miscellaneous Mapping Control Register; 0x00000013 ***/ -typedef union { - byte Byte; - struct { - byte ROMON :1; /* Enable Flash EEPROM */ - byte ROMHM :1; /* Flash EEPROM only in second half of memory map */ - byte EXSTR0 :1; /* External Access Stretch Bit 0 */ - byte EXSTR1 :1; /* External Access Stretch Bit 1 */ - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte :1; - byte :1; - byte grpEXSTR :2; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} MISCSTR; -extern volatile MISCSTR _MISC @(REG_BASE + 0x00000013); -#define MISC _MISC.Byte -#define MISC_ROMON _MISC.Bits.ROMON -#define MISC_ROMHM _MISC.Bits.ROMHM -#define MISC_EXSTR0 _MISC.Bits.EXSTR0 -#define MISC_EXSTR1 _MISC.Bits.EXSTR1 -#define MISC_EXSTR _MISC.MergedBits.grpEXSTR - - -/*** MTST0 - MTST0; 0x00000014 ***/ -typedef union { - byte Byte; - struct { - byte BIT0 :1; /* MTST0 Bit 0 */ - byte BIT1 :1; /* MTST0 Bit 1 */ - byte BIT2 :1; /* MTST0 Bit 2 */ - byte BIT3 :1; /* MTST0 Bit 3 */ - byte BIT4 :1; /* MTST0 Bit 4 */ - byte BIT5 :1; /* MTST0 Bit 5 */ - byte BIT6 :1; /* MTST0 Bit 6 */ - byte BIT7 :1; /* MTST0 Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; -} MTST0STR; -extern volatile MTST0STR _MTST0 @(REG_BASE + 0x00000014); -#define MTST0 _MTST0.Byte -#define MTST0_BIT0 _MTST0.Bits.BIT0 -#define MTST0_BIT1 _MTST0.Bits.BIT1 -#define MTST0_BIT2 _MTST0.Bits.BIT2 -#define MTST0_BIT3 _MTST0.Bits.BIT3 -#define MTST0_BIT4 _MTST0.Bits.BIT4 -#define MTST0_BIT5 _MTST0.Bits.BIT5 -#define MTST0_BIT6 _MTST0.Bits.BIT6 -#define MTST0_BIT7 _MTST0.Bits.BIT7 -#define MTST0_BIT _MTST0.MergedBits.grpBIT - - -/*** ITCR - Interrupt Test Control Register; 0x00000015 ***/ -typedef union { - byte Byte; - struct { - byte ADR0 :1; /* Test register select Bit 0 */ - byte ADR1 :1; /* Test register select Bit 1 */ - byte ADR2 :1; /* Test register select Bit 2 */ - byte ADR3 :1; /* Test register select Bit 3 */ - byte WRTINT :1; /* Write to the Interrupt Test Registers */ - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpADR :4; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} ITCRSTR; -extern volatile ITCRSTR _ITCR @(REG_BASE + 0x00000015); -#define ITCR _ITCR.Byte -#define ITCR_ADR0 _ITCR.Bits.ADR0 -#define ITCR_ADR1 _ITCR.Bits.ADR1 -#define ITCR_ADR2 _ITCR.Bits.ADR2 -#define ITCR_ADR3 _ITCR.Bits.ADR3 -#define ITCR_WRTINT _ITCR.Bits.WRTINT -#define ITCR_ADR _ITCR.MergedBits.grpADR - - -/*** ITEST - Interrupt Test Register; 0x00000016 ***/ -typedef union { - byte Byte; - struct { - byte INT0 :1; /* Interrupt Test Register Bit 0 */ - byte INT2 :1; /* Interrupt Test Register Bit 1 */ - byte INT4 :1; /* Interrupt Test Register Bit 2 */ - byte INT6 :1; /* Interrupt Test Register Bit 3 */ - byte INT8 :1; /* Interrupt Test Register Bit 4 */ - byte INTA :1; /* Interrupt Test Register Bit 5 */ - byte INTC :1; /* Interrupt Test Register Bit 6 */ - byte INTE :1; /* Interrupt Test Register Bit 7 */ - } Bits; -} ITESTSTR; -extern volatile ITESTSTR _ITEST @(REG_BASE + 0x00000016); -#define ITEST _ITEST.Byte -#define ITEST_INT0 _ITEST.Bits.INT0 -#define ITEST_INT2 _ITEST.Bits.INT2 -#define ITEST_INT4 _ITEST.Bits.INT4 -#define ITEST_INT6 _ITEST.Bits.INT6 -#define ITEST_INT8 _ITEST.Bits.INT8 -#define ITEST_INTA _ITEST.Bits.INTA -#define ITEST_INTC _ITEST.Bits.INTC -#define ITEST_INTE _ITEST.Bits.INTE - - -/*** MTST1 - MTST1; 0x00000017 ***/ -typedef union { - byte Byte; - struct { - byte BIT0 :1; /* MTST1 Bit 0 */ - byte BIT1 :1; /* MTST1 Bit 1 */ - byte BIT2 :1; /* MTST1 Bit 2 */ - byte BIT3 :1; /* MTST1 Bit 3 */ - byte BIT4 :1; /* MTST1 Bit 4 */ - byte BIT5 :1; /* MTST1 Bit 5 */ - byte BIT6 :1; /* MTST1 Bit 6 */ - byte BIT7 :1; /* MTST1 Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; -} MTST1STR; -extern volatile MTST1STR _MTST1 @(REG_BASE + 0x00000017); -#define MTST1 _MTST1.Byte -#define MTST1_BIT0 _MTST1.Bits.BIT0 -#define MTST1_BIT1 _MTST1.Bits.BIT1 -#define MTST1_BIT2 _MTST1.Bits.BIT2 -#define MTST1_BIT3 _MTST1.Bits.BIT3 -#define MTST1_BIT4 _MTST1.Bits.BIT4 -#define MTST1_BIT5 _MTST1.Bits.BIT5 -#define MTST1_BIT6 _MTST1.Bits.BIT6 -#define MTST1_BIT7 _MTST1.Bits.BIT7 -#define MTST1_BIT _MTST1.MergedBits.grpBIT - - -/*** PARTIDH - Part ID Register High; 0x0000001A ***/ -typedef union { - byte Byte; - struct { - byte ID15 :1; /* Part ID Register Bit 15 */ - byte ID14 :1; /* Part ID Register Bit 14 */ - byte ID13 :1; /* Part ID Register Bit 13 */ - byte ID12 :1; /* Part ID Register Bit 12 */ - byte ID11 :1; /* Part ID Register Bit 11 */ - byte ID10 :1; /* Part ID Register Bit 10 */ - byte ID9 :1; /* Part ID Register Bit 9 */ - byte ID8 :1; /* Part ID Register Bit 8 */ - } Bits; -} PARTIDHSTR; -extern volatile PARTIDHSTR _PARTIDH @(REG_BASE + 0x0000001A); -#define PARTIDH _PARTIDH.Byte -#define PARTIDH_ID15 _PARTIDH.Bits.ID15 -#define PARTIDH_ID14 _PARTIDH.Bits.ID14 -#define PARTIDH_ID13 _PARTIDH.Bits.ID13 -#define PARTIDH_ID12 _PARTIDH.Bits.ID12 -#define PARTIDH_ID11 _PARTIDH.Bits.ID11 -#define PARTIDH_ID10 _PARTIDH.Bits.ID10 -#define PARTIDH_ID9 _PARTIDH.Bits.ID9 -#define PARTIDH_ID8 _PARTIDH.Bits.ID8 - - -/*** PARTIDL - Part ID Register Low; 0x0000001B ***/ -typedef union { - byte Byte; - struct { - byte ID0 :1; /* Part ID Register Bit 0 */ - byte ID1 :1; /* Part ID Register Bit 1 */ - byte ID2 :1; /* Part ID Register Bit 2 */ - byte ID3 :1; /* Part ID Register Bit 3 */ - byte ID4 :1; /* Part ID Register Bit 4 */ - byte ID5 :1; /* Part ID Register Bit 5 */ - byte ID6 :1; /* Part ID Register Bit 6 */ - byte ID7 :1; /* Part ID Register Bit 7 */ - } Bits; - struct { - byte grpID :8; - } MergedBits; -} PARTIDLSTR; -extern volatile PARTIDLSTR _PARTIDL @(REG_BASE + 0x0000001B); -#define PARTIDL _PARTIDL.Byte -#define PARTIDL_ID0 _PARTIDL.Bits.ID0 -#define PARTIDL_ID1 _PARTIDL.Bits.ID1 -#define PARTIDL_ID2 _PARTIDL.Bits.ID2 -#define PARTIDL_ID3 _PARTIDL.Bits.ID3 -#define PARTIDL_ID4 _PARTIDL.Bits.ID4 -#define PARTIDL_ID5 _PARTIDL.Bits.ID5 -#define PARTIDL_ID6 _PARTIDL.Bits.ID6 -#define PARTIDL_ID7 _PARTIDL.Bits.ID7 -#define PARTIDL_ID _PARTIDL.MergedBits.grpID - - -/*** MEMSIZ0 - Memory Size Register Zero; 0x0000001C ***/ -typedef union { - byte Byte; - struct { - byte ram_sw0 :1; /* Allocated RAM Memory Space Bit 0 */ - byte ram_sw1 :1; /* Allocated RAM Memory Space Bit 1 */ - byte ram_sw2 :1; /* Allocated RAM Memory Space Bit 2 */ - byte :1; - byte eep_sw0 :1; /* Allocated EEPROM Memory Space Bit 0 */ - byte eep_sw1 :1; /* Allocated EEPROM Memory Space Bit 1 */ - byte :1; - byte reg_sw0 :1; /* Allocated System Register Space */ - } Bits; - struct { - byte grpram_sw :3; - byte :1; - byte grpeep_sw :2; - byte :1; - byte grpreg_sw :1; - } MergedBits; -} MEMSIZ0STR; -extern volatile MEMSIZ0STR _MEMSIZ0 @(REG_BASE + 0x0000001C); -#define MEMSIZ0 _MEMSIZ0.Byte -#define MEMSIZ0_ram_sw0 _MEMSIZ0.Bits.ram_sw0 -#define MEMSIZ0_ram_sw1 _MEMSIZ0.Bits.ram_sw1 -#define MEMSIZ0_ram_sw2 _MEMSIZ0.Bits.ram_sw2 -#define MEMSIZ0_eep_sw0 _MEMSIZ0.Bits.eep_sw0 -#define MEMSIZ0_eep_sw1 _MEMSIZ0.Bits.eep_sw1 -#define MEMSIZ0_reg_sw0 _MEMSIZ0.Bits.reg_sw0 -#define MEMSIZ0_ram_sw _MEMSIZ0.MergedBits.grpram_sw -#define MEMSIZ0_eep_sw _MEMSIZ0.MergedBits.grpeep_sw - - -/*** MEMSIZ1 - Memory Size Register One; 0x0000001D ***/ -typedef union { - byte Byte; - struct { - byte pag_sw0 :1; /* Allocated Off-Chip Memory Options Bit 0 */ - byte pag_sw1 :1; /* Allocated Off-Chip Memory Options Bit 1 */ - byte :1; - byte :1; - byte :1; - byte :1; - byte rom_sw0 :1; /* Allocated Flash EEPROM/ROM Physical Memory Space Bit 0 */ - byte rom_sw1 :1; /* Allocated Flash EEPROM/ROM Physical Memory Space Bit 1 */ - } Bits; - struct { - byte grppag_sw :2; - byte :1; - byte :1; - byte :1; - byte :1; - byte grprom_sw :2; - } MergedBits; -} MEMSIZ1STR; -extern volatile MEMSIZ1STR _MEMSIZ1 @(REG_BASE + 0x0000001D); -#define MEMSIZ1 _MEMSIZ1.Byte -#define MEMSIZ1_pag_sw0 _MEMSIZ1.Bits.pag_sw0 -#define MEMSIZ1_pag_sw1 _MEMSIZ1.Bits.pag_sw1 -#define MEMSIZ1_rom_sw0 _MEMSIZ1.Bits.rom_sw0 -#define MEMSIZ1_rom_sw1 _MEMSIZ1.Bits.rom_sw1 -#define MEMSIZ1_pag_sw _MEMSIZ1.MergedBits.grppag_sw -#define MEMSIZ1_rom_sw _MEMSIZ1.MergedBits.grprom_sw - - -/*** INTCR - Interrupt Control Register; 0x0000001E ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte IRQEN :1; /* External IRQ Enable */ - byte IRQE :1; /* IRQ Select Edge Sensitive Only */ - } Bits; -} INTCRSTR; -extern volatile INTCRSTR _INTCR @(REG_BASE + 0x0000001E); -#define INTCR _INTCR.Byte -#define INTCR_IRQEN _INTCR.Bits.IRQEN -#define INTCR_IRQE _INTCR.Bits.IRQE - - -/*** HPRIO - Highest Priority I Interrupt; 0x0000001F ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte PSEL1 :1; /* Highest Priority I Interrupt Bit 1 */ - byte PSEL2 :1; /* Highest Priority I Interrupt Bit 2 */ - byte PSEL3 :1; /* Highest Priority I Interrupt Bit 3 */ - byte PSEL4 :1; /* Highest Priority I Interrupt Bit 4 */ - byte PSEL5 :1; /* Highest Priority I Interrupt Bit 5 */ - byte PSEL6 :1; /* Highest Priority I Interrupt Bit 6 */ - byte PSEL7 :1; /* Highest Priority I Interrupt Bit 7 */ - } Bits; - struct { - byte :1; - byte grpPSEL_1 :7; - } MergedBits; -} HPRIOSTR; -extern volatile HPRIOSTR _HPRIO @(REG_BASE + 0x0000001F); -#define HPRIO _HPRIO.Byte -#define HPRIO_PSEL1 _HPRIO.Bits.PSEL1 -#define HPRIO_PSEL2 _HPRIO.Bits.PSEL2 -#define HPRIO_PSEL3 _HPRIO.Bits.PSEL3 -#define HPRIO_PSEL4 _HPRIO.Bits.PSEL4 -#define HPRIO_PSEL5 _HPRIO.Bits.PSEL5 -#define HPRIO_PSEL6 _HPRIO.Bits.PSEL6 -#define HPRIO_PSEL7 _HPRIO.Bits.PSEL7 -#define HPRIO_PSEL_1 _HPRIO.MergedBits.grpPSEL_1 -#define HPRIO_PSEL HPRIO_PSEL_1 - - -/*** BKPCT0 - Breakpoint Control Register 0; 0x00000028 ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte BKTAG :1; /* Breakpoint on Tag */ - byte BKBDM :1; /* Breakpoint Background Debug Mode Enable */ - byte BKFULL :1; /* Full Breakpoint Mode Enable */ - byte BKEN :1; /* Breakpoint Enable */ - } Bits; -} BKPCT0STR; -extern volatile BKPCT0STR _BKPCT0 @(REG_BASE + 0x00000028); -#define BKPCT0 _BKPCT0.Byte -#define BKPCT0_BKTAG _BKPCT0.Bits.BKTAG -#define BKPCT0_BKBDM _BKPCT0.Bits.BKBDM -#define BKPCT0_BKFULL _BKPCT0.Bits.BKFULL -#define BKPCT0_BKEN _BKPCT0.Bits.BKEN - - -/*** BKPCT1 - Breakpoint Control Register 1; 0x00000029 ***/ -typedef union { - byte Byte; - struct { - byte BK1RW :1; /* R/W Compare Value 1 */ - byte BK1RWE :1; /* R/W Compare Enable 1 */ - byte BK0RW :1; /* R/W Compare Value 0 */ - byte BK0RWE :1; /* R/W Compare Enable 0 */ - byte BK1MBL :1; /* Breakpoint Mask Low Byte for Second Address */ - byte BK1MBH :1; /* Breakpoint Mask High Byte for Second Address */ - byte BK0MBL :1; /* Breakpoint Mask Low Byte for First Address */ - byte BK0MBH :1; /* Breakpoint Mask High Byte for First Address */ - } Bits; -} BKPCT1STR; -extern volatile BKPCT1STR _BKPCT1 @(REG_BASE + 0x00000029); -#define BKPCT1 _BKPCT1.Byte -#define BKPCT1_BK1RW _BKPCT1.Bits.BK1RW -#define BKPCT1_BK1RWE _BKPCT1.Bits.BK1RWE -#define BKPCT1_BK0RW _BKPCT1.Bits.BK0RW -#define BKPCT1_BK0RWE _BKPCT1.Bits.BK0RWE -#define BKPCT1_BK1MBL _BKPCT1.Bits.BK1MBL -#define BKPCT1_BK1MBH _BKPCT1.Bits.BK1MBH -#define BKPCT1_BK0MBL _BKPCT1.Bits.BK0MBL -#define BKPCT1_BK0MBH _BKPCT1.Bits.BK0MBH - - -/*** BKP0X - First Address Memory Expansion Breakpoint Register; 0x0000002A ***/ -typedef union { - byte Byte; - struct { - byte BK0V0 :1; /* First Address Breakpoint Expansion Address Value Bit 0 */ - byte BK0V1 :1; /* First Address Breakpoint Expansion Address Value Bit 1 */ - byte BK0V2 :1; /* First Address Breakpoint Expansion Address Value Bit 2 */ - byte BK0V3 :1; /* First Address Breakpoint Expansion Address Value Bit 3 */ - byte BK0V4 :1; /* First Address Breakpoint Expansion Address Value Bit 4 */ - byte BK0V5 :1; /* First Address Breakpoint Expansion Address Value Bit 5 */ - byte :1; - byte :1; - } Bits; - struct { - byte grpBK0V :6; - byte :1; - byte :1; - } MergedBits; -} BKP0XSTR; -extern volatile BKP0XSTR _BKP0X @(REG_BASE + 0x0000002A); -#define BKP0X _BKP0X.Byte -#define BKP0X_BK0V0 _BKP0X.Bits.BK0V0 -#define BKP0X_BK0V1 _BKP0X.Bits.BK0V1 -#define BKP0X_BK0V2 _BKP0X.Bits.BK0V2 -#define BKP0X_BK0V3 _BKP0X.Bits.BK0V3 -#define BKP0X_BK0V4 _BKP0X.Bits.BK0V4 -#define BKP0X_BK0V5 _BKP0X.Bits.BK0V5 -#define BKP0X_BK0V _BKP0X.MergedBits.grpBK0V - - -/*** BKP0H - First Address High Byte Breakpoint Register; 0x0000002B ***/ -typedef union { - byte Byte; - struct { - byte BIT8 :1; /* First Address Breakpoint Register Bit 8 */ - byte BIT9 :1; /* First Address Breakpoint Register Bit 9 */ - byte BIT10 :1; /* First Address Breakpoint Register Bit 10 */ - byte BIT11 :1; /* First Address Breakpoint Register Bit 11 */ - byte BIT12 :1; /* First Address Breakpoint Register Bit 12 */ - byte BIT13 :1; /* First Address Breakpoint Register Bit 13 */ - byte BIT14 :1; /* First Address Breakpoint Register Bit 14 */ - byte BIT15 :1; /* First Address Breakpoint Register Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; -} BKP0HSTR; -extern volatile BKP0HSTR _BKP0H @(REG_BASE + 0x0000002B); -#define BKP0H _BKP0H.Byte -#define BKP0H_BIT8 _BKP0H.Bits.BIT8 -#define BKP0H_BIT9 _BKP0H.Bits.BIT9 -#define BKP0H_BIT10 _BKP0H.Bits.BIT10 -#define BKP0H_BIT11 _BKP0H.Bits.BIT11 -#define BKP0H_BIT12 _BKP0H.Bits.BIT12 -#define BKP0H_BIT13 _BKP0H.Bits.BIT13 -#define BKP0H_BIT14 _BKP0H.Bits.BIT14 -#define BKP0H_BIT15 _BKP0H.Bits.BIT15 -#define BKP0H_BIT_8 _BKP0H.MergedBits.grpBIT_8 -#define BKP0H_BIT BKP0H_BIT_8 - - -/*** BKP0L - First Address Low Byte Breakpoint Register; 0x0000002C ***/ -typedef union { - byte Byte; - struct { - byte BIT0 :1; /* First Address Breakpoint Register Bit 0 */ - byte BIT1 :1; /* First Address Breakpoint Register Bit 1 */ - byte BIT2 :1; /* First Address Breakpoint Register Bit 2 */ - byte BIT3 :1; /* First Address Breakpoint Register Bit 3 */ - byte BIT4 :1; /* First Address Breakpoint Register Bit 4 */ - byte BIT5 :1; /* First Address Breakpoint Register Bit 5 */ - byte BIT6 :1; /* First Address Breakpoint Register Bit 6 */ - byte BIT7 :1; /* First Address Breakpoint Register Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; -} BKP0LSTR; -extern volatile BKP0LSTR _BKP0L @(REG_BASE + 0x0000002C); -#define BKP0L _BKP0L.Byte -#define BKP0L_BIT0 _BKP0L.Bits.BIT0 -#define BKP0L_BIT1 _BKP0L.Bits.BIT1 -#define BKP0L_BIT2 _BKP0L.Bits.BIT2 -#define BKP0L_BIT3 _BKP0L.Bits.BIT3 -#define BKP0L_BIT4 _BKP0L.Bits.BIT4 -#define BKP0L_BIT5 _BKP0L.Bits.BIT5 -#define BKP0L_BIT6 _BKP0L.Bits.BIT6 -#define BKP0L_BIT7 _BKP0L.Bits.BIT7 -#define BKP0L_BIT _BKP0L.MergedBits.grpBIT - - -/*** BKP1X - Second Address Memory Expansion Breakpoint Register; 0x0000002D ***/ -typedef union { - byte Byte; - struct { - byte BK1V0 :1; /* Second Address Breakpoint Expansion Address Value Bit 0 */ - byte BK1V1 :1; /* Second Address Breakpoint Expansion Address Value Bit 1 */ - byte BK1V2 :1; /* Second Address Breakpoint Expansion Address Value Bit 2 */ - byte BK1V3 :1; /* Second Address Breakpoint Expansion Address Value Bit 3 */ - byte BK1V4 :1; /* Second Address Breakpoint Expansion Address Value Bit 4 */ - byte BK1V5 :1; /* Second Address Breakpoint Expansion Address Value Bit 5 */ - byte :1; - byte :1; - } Bits; - struct { - byte grpBK1V :6; - byte :1; - byte :1; - } MergedBits; -} BKP1XSTR; -extern volatile BKP1XSTR _BKP1X @(REG_BASE + 0x0000002D); -#define BKP1X _BKP1X.Byte -#define BKP1X_BK1V0 _BKP1X.Bits.BK1V0 -#define BKP1X_BK1V1 _BKP1X.Bits.BK1V1 -#define BKP1X_BK1V2 _BKP1X.Bits.BK1V2 -#define BKP1X_BK1V3 _BKP1X.Bits.BK1V3 -#define BKP1X_BK1V4 _BKP1X.Bits.BK1V4 -#define BKP1X_BK1V5 _BKP1X.Bits.BK1V5 -#define BKP1X_BK1V _BKP1X.MergedBits.grpBK1V - - -/*** BKP1H - Data (Second Address) High Byte Breakpoint Register; 0x0000002E ***/ -typedef union { - byte Byte; - struct { - byte BIT8 :1; /* Data (Second Address) Breakpoint Register Bit 8 */ - byte BIT9 :1; /* Data (Second Address) Breakpoint Register Bit 9 */ - byte BIT10 :1; /* Data (Second Address) Breakpoint Register Bit 10 */ - byte BIT11 :1; /* Data (Second Address) Breakpoint Register Bit 11 */ - byte BIT12 :1; /* Data (Second Address) Breakpoint Register Bit 12 */ - byte BIT13 :1; /* Data (Second Address) Breakpoint Register Bit 13 */ - byte BIT14 :1; /* Data (Second Address) Breakpoint Register Bit 14 */ - byte BIT15 :1; /* Data (Second Address) Breakpoint Register Bit 15 */ - } Bits; - struct { - byte grpBIT_8 :8; - } MergedBits; -} BKP1HSTR; -extern volatile BKP1HSTR _BKP1H @(REG_BASE + 0x0000002E); -#define BKP1H _BKP1H.Byte -#define BKP1H_BIT8 _BKP1H.Bits.BIT8 -#define BKP1H_BIT9 _BKP1H.Bits.BIT9 -#define BKP1H_BIT10 _BKP1H.Bits.BIT10 -#define BKP1H_BIT11 _BKP1H.Bits.BIT11 -#define BKP1H_BIT12 _BKP1H.Bits.BIT12 -#define BKP1H_BIT13 _BKP1H.Bits.BIT13 -#define BKP1H_BIT14 _BKP1H.Bits.BIT14 -#define BKP1H_BIT15 _BKP1H.Bits.BIT15 -#define BKP1H_BIT_8 _BKP1H.MergedBits.grpBIT_8 -#define BKP1H_BIT BKP1H_BIT_8 - - -/*** BKP1L - Data (Second Address) Low Byte Breakpoint Register; 0x0000002F ***/ -typedef union { - byte Byte; - struct { - byte BIT0 :1; /* Data (Second Address) Breakpoint Register Bit 0 */ - byte BIT1 :1; /* Data (Second Address) Breakpoint Register Bit 1 */ - byte BIT2 :1; /* Data (Second Address) Breakpoint Register Bit 2 */ - byte BIT3 :1; /* Data (Second Address) Breakpoint Register Bit 3 */ - byte BIT4 :1; /* Data (Second Address) Breakpoint Register Bit 4 */ - byte BIT5 :1; /* Data (Second Address) Breakpoint Register Bit 5 */ - byte BIT6 :1; /* Data (Second Address) Breakpoint Register Bit 6 */ - byte BIT7 :1; /* Data (Second Address) Breakpoint Register Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; -} BKP1LSTR; -extern volatile BKP1LSTR _BKP1L @(REG_BASE + 0x0000002F); -#define BKP1L _BKP1L.Byte -#define BKP1L_BIT0 _BKP1L.Bits.BIT0 -#define BKP1L_BIT1 _BKP1L.Bits.BIT1 -#define BKP1L_BIT2 _BKP1L.Bits.BIT2 -#define BKP1L_BIT3 _BKP1L.Bits.BIT3 -#define BKP1L_BIT4 _BKP1L.Bits.BIT4 -#define BKP1L_BIT5 _BKP1L.Bits.BIT5 -#define BKP1L_BIT6 _BKP1L.Bits.BIT6 -#define BKP1L_BIT7 _BKP1L.Bits.BIT7 -#define BKP1L_BIT _BKP1L.MergedBits.grpBIT - - -/*** PPAGE - Page Index Register; 0x00000030 ***/ -typedef union { - byte Byte; - struct { - byte PIX0 :1; /* Page Index Register Bit 0 */ - byte PIX1 :1; /* Page Index Register Bit 1 */ - byte PIX2 :1; /* Page Index Register Bit 2 */ - byte PIX3 :1; /* Page Index Register Bit 3 */ - byte PIX4 :1; /* Page Index Register Bit 4 */ - byte PIX5 :1; /* Page Index Register Bit 5 */ - byte :1; - byte :1; - } Bits; - struct { - byte grpPIX :6; - byte :1; - byte :1; - } MergedBits; -} PPAGESTR; -extern volatile PPAGESTR _PPAGE @(REG_BASE + 0x00000030); -#define PPAGE _PPAGE.Byte -#define PPAGE_PIX0 _PPAGE.Bits.PIX0 -#define PPAGE_PIX1 _PPAGE.Bits.PIX1 -#define PPAGE_PIX2 _PPAGE.Bits.PIX2 -#define PPAGE_PIX3 _PPAGE.Bits.PIX3 -#define PPAGE_PIX4 _PPAGE.Bits.PIX4 -#define PPAGE_PIX5 _PPAGE.Bits.PIX5 -#define PPAGE_PIX _PPAGE.MergedBits.grpPIX - - -/*** PORTK - Port K Data Register; 0x00000032 ***/ -typedef union { - byte Byte; - struct { - byte BIT0 :1; /* Port K Bit 0, XAB14 */ - byte BIT1 :1; /* Port K Bit 1, XAB15 */ - byte BIT2 :1; /* Port K Bit 2, XAB16 */ - byte BIT3 :1; /* Port K Bit 3, XAB17 */ - byte BIT4 :1; /* Port K Bit 4, XAB18 */ - byte BIT5 :1; /* Port K Bit 5, XAB19 */ - byte BIT6 :1; /* Port K Bit 6 */ - byte BIT7 :1; /* Port K Bit 7, ECS/ROMONE */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; -} PORTKSTR; -extern volatile PORTKSTR _PORTK @(REG_BASE + 0x00000032); -#define PORTK _PORTK.Byte -#define PORTK_BIT0 _PORTK.Bits.BIT0 -#define PORTK_BIT1 _PORTK.Bits.BIT1 -#define PORTK_BIT2 _PORTK.Bits.BIT2 -#define PORTK_BIT3 _PORTK.Bits.BIT3 -#define PORTK_BIT4 _PORTK.Bits.BIT4 -#define PORTK_BIT5 _PORTK.Bits.BIT5 -#define PORTK_BIT6 _PORTK.Bits.BIT6 -#define PORTK_BIT7 _PORTK.Bits.BIT7 -#define PORTK_BIT _PORTK.MergedBits.grpBIT - - -/*** DDRK - Port K Data Direction Register; 0x00000033 ***/ -typedef union { - byte Byte; - struct { - byte DDK0 :1; /* Port K Data Direction Bit 0 */ - byte DDK1 :1; /* Port K Data Direction Bit 1 */ - byte DDK2 :1; /* Port K Data Direction Bit 2 */ - byte DDK3 :1; /* Port K Data Direction Bit 3 */ - byte DDK4 :1; /* Port K Data Direction Bit 4 */ - byte DDK5 :1; /* Port K Data Direction Bit 5 */ - byte :1; - byte DDK7 :1; /* Port K Data Direction Bit 7 */ - } Bits; - struct { - byte grpDDK :6; - byte :1; - byte grpDDK_7 :1; - } MergedBits; -} DDRKSTR; -extern volatile DDRKSTR _DDRK @(REG_BASE + 0x00000033); -#define DDRK _DDRK.Byte -#define DDRK_DDK0 _DDRK.Bits.DDK0 -#define DDRK_DDK1 _DDRK.Bits.DDK1 -#define DDRK_DDK2 _DDRK.Bits.DDK2 -#define DDRK_DDK3 _DDRK.Bits.DDK3 -#define DDRK_DDK4 _DDRK.Bits.DDK4 -#define DDRK_DDK5 _DDRK.Bits.DDK5 -#define DDRK_DDK7 _DDRK.Bits.DDK7 -#define DDRK_DDK _DDRK.MergedBits.grpDDK - - -/*** SYNR - CRG Synthesizer Register; 0x00000034 ***/ -typedef union { - byte Byte; - struct { - byte SYN0 :1; /* CRG Synthesizer Bit 0 */ - byte SYN1 :1; /* CRG Synthesizer Bit 1 */ - byte SYN2 :1; /* CRG Synthesizer Bit 2 */ - byte SYN3 :1; /* CRG Synthesizer Bit 3 */ - byte SYN4 :1; /* CRG Synthesizer Bit 4 */ - byte SYN5 :1; /* CRG Synthesizer Bit 5 */ - byte :1; - byte :1; - } Bits; - struct { - byte grpSYN :6; - byte :1; - byte :1; - } MergedBits; -} SYNRSTR; -extern volatile SYNRSTR _SYNR @(REG_BASE + 0x00000034); -#define SYNR _SYNR.Byte -#define SYNR_SYN0 _SYNR.Bits.SYN0 -#define SYNR_SYN1 _SYNR.Bits.SYN1 -#define SYNR_SYN2 _SYNR.Bits.SYN2 -#define SYNR_SYN3 _SYNR.Bits.SYN3 -#define SYNR_SYN4 _SYNR.Bits.SYN4 -#define SYNR_SYN5 _SYNR.Bits.SYN5 -#define SYNR_SYN _SYNR.MergedBits.grpSYN - - -/*** REFDV - CRG Reference Divider Register; 0x00000035 ***/ -typedef union { - byte Byte; - struct { - byte REFDV0 :1; /* CRG Reference Divider Bit 0 */ - byte REFDV1 :1; /* CRG Reference Divider Bit 1 */ - byte REFDV2 :1; /* CRG Reference Divider Bit 2 */ - byte REFDV3 :1; /* CRG Reference Divider Bit 3 */ - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpREFDV :4; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} REFDVSTR; -extern volatile REFDVSTR _REFDV @(REG_BASE + 0x00000035); -#define REFDV _REFDV.Byte -#define REFDV_REFDV0 _REFDV.Bits.REFDV0 -#define REFDV_REFDV1 _REFDV.Bits.REFDV1 -#define REFDV_REFDV2 _REFDV.Bits.REFDV2 -#define REFDV_REFDV3 _REFDV.Bits.REFDV3 -#define REFDV_REFDV _REFDV.MergedBits.grpREFDV - - -/*** CTFLG - CRG Test Flags Register; 0x00000036 ***/ -typedef union { - byte Byte; - struct { - byte TOUT0 :1; /* CRG Test Flags Bit 0 */ - byte TOUT1 :1; /* CRG Test Flags Bit 1 */ - byte TOUT2 :1; /* CRG Test Flags Bit 2 */ - byte TOUT3 :1; /* CRG Test Flags Bit 3 */ - byte TOUT4 :1; /* CRG Test Flags Bit 4 */ - byte TOUT5 :1; /* CRG Test Flags Bit 5 */ - byte TOUT6 :1; /* CRG Test Flags Bit 6 */ - byte TOUT7 :1; /* CRG Test Flags Bit 7 */ - } Bits; - struct { - byte grpTOUT :8; - } MergedBits; -} CTFLGSTR; -extern volatile CTFLGSTR _CTFLG @(REG_BASE + 0x00000036); -#define CTFLG _CTFLG.Byte -#define CTFLG_TOUT0 _CTFLG.Bits.TOUT0 -#define CTFLG_TOUT1 _CTFLG.Bits.TOUT1 -#define CTFLG_TOUT2 _CTFLG.Bits.TOUT2 -#define CTFLG_TOUT3 _CTFLG.Bits.TOUT3 -#define CTFLG_TOUT4 _CTFLG.Bits.TOUT4 -#define CTFLG_TOUT5 _CTFLG.Bits.TOUT5 -#define CTFLG_TOUT6 _CTFLG.Bits.TOUT6 -#define CTFLG_TOUT7 _CTFLG.Bits.TOUT7 -#define CTFLG_TOUT _CTFLG.MergedBits.grpTOUT - - -/*** CRGFLG - CRG Flags Register; 0x00000037 ***/ -typedef union { - byte Byte; - struct { - byte SCM :1; /* Self-clock mode Status */ - byte SCMIF :1; /* Self-clock mode Interrupt Flag */ - byte TRACK :1; /* Track Status */ - byte LOCK :1; /* Lock Status */ - byte LOCKIF :1; /* PLL Lock Interrupt Flag */ - byte :1; - byte PORF :1; /* Power on Reset Flag */ - byte RTIF :1; /* Real Time Interrupt Flag */ - } Bits; -} CRGFLGSTR; -extern volatile CRGFLGSTR _CRGFLG @(REG_BASE + 0x00000037); -#define CRGFLG _CRGFLG.Byte -#define CRGFLG_SCM _CRGFLG.Bits.SCM -#define CRGFLG_SCMIF _CRGFLG.Bits.SCMIF -#define CRGFLG_TRACK _CRGFLG.Bits.TRACK -#define CRGFLG_LOCK _CRGFLG.Bits.LOCK -#define CRGFLG_LOCKIF _CRGFLG.Bits.LOCKIF -#define CRGFLG_PORF _CRGFLG.Bits.PORF -#define CRGFLG_RTIF _CRGFLG.Bits.RTIF - - -/*** CRGINT - CRG Interrupt Enable Register; 0x00000038 ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte SCMIE :1; /* Self-clock mode Interrupt Enable */ - byte :1; - byte :1; - byte LOCKIE :1; /* Lock Interrupt Enable */ - byte :1; - byte :1; - byte RTIE :1; /* Real Time Interrupt Enable */ - } Bits; -} CRGINTSTR; -extern volatile CRGINTSTR _CRGINT @(REG_BASE + 0x00000038); -#define CRGINT _CRGINT.Byte -#define CRGINT_SCMIE _CRGINT.Bits.SCMIE -#define CRGINT_LOCKIE _CRGINT.Bits.LOCKIE -#define CRGINT_RTIE _CRGINT.Bits.RTIE - - -/*** CLKSEL - CRG Clock Select Register; 0x00000039 ***/ -typedef union { - byte Byte; - struct { - byte COPWAI :1; /* COP stops in WAIT mode */ - byte RTIWAI :1; /* RTI stops in WAIT mode */ - byte CWAI :1; /* CLK24 and CLK23 stop in WAIT mode */ - byte PLLWAI :1; /* PLL stops in WAIT mode */ - byte ROAWAI :1; /* Reduced Oscillator Amplitude in WAIT mode */ - byte SYSWAI :1; /* System clocks stop in WAIT mode */ - byte PSTP :1; /* Pseudo Stop */ - byte PLLSEL :1; /* PLL selected for system clock */ - } Bits; -} CLKSELSTR; -extern volatile CLKSELSTR _CLKSEL @(REG_BASE + 0x00000039); -#define CLKSEL _CLKSEL.Byte -#define CLKSEL_COPWAI _CLKSEL.Bits.COPWAI -#define CLKSEL_RTIWAI _CLKSEL.Bits.RTIWAI -#define CLKSEL_CWAI _CLKSEL.Bits.CWAI -#define CLKSEL_PLLWAI _CLKSEL.Bits.PLLWAI -#define CLKSEL_ROAWAI _CLKSEL.Bits.ROAWAI -#define CLKSEL_SYSWAI _CLKSEL.Bits.SYSWAI -#define CLKSEL_PSTP _CLKSEL.Bits.PSTP -#define CLKSEL_PLLSEL _CLKSEL.Bits.PLLSEL - - -/*** PLLCTL - CRG PLL Control Register; 0x0000003A ***/ -typedef union { - byte Byte; - struct { - byte SCME :1; /* Self-clock mode enable */ - byte :1; - byte :1; - byte :1; - byte ACQ :1; /* Acquisition */ - byte AUTO :1; /* Automatic Bandwidth Control */ - byte PLLON :1; /* Phase Lock Loop On */ - byte CME :1; /* Crystal Monitor Enable */ - } Bits; -} PLLCTLSTR; -extern volatile PLLCTLSTR _PLLCTL @(REG_BASE + 0x0000003A); -#define PLLCTL _PLLCTL.Byte -#define PLLCTL_SCME _PLLCTL.Bits.SCME -#define PLLCTL_ACQ _PLLCTL.Bits.ACQ -#define PLLCTL_AUTO _PLLCTL.Bits.AUTO -#define PLLCTL_PLLON _PLLCTL.Bits.PLLON -#define PLLCTL_CME _PLLCTL.Bits.CME - - -/*** RTICTL - CRG RTI Control Register; 0x0000003B ***/ -typedef union { - byte Byte; - struct { - byte RTR0 :1; /* Real Time Interrupt Modulus Counter Select */ - byte RTR1 :1; /* Real Time Interrupt Modulus Counter Select */ - byte RTR2 :1; /* Real Time Interrupt Modulus Counter Select */ - byte RTR3 :1; /* Real Time Interrupt Modulus Counter Select */ - byte RTR4 :1; /* Real Time Interrupt Prescale Rate Select */ - byte RTR5 :1; /* Real Time Interrupt Prescale Rate Select */ - byte RTR6 :1; /* Real Time Interrupt Prescale Rate Select */ - byte :1; - } Bits; - struct { - byte grpRTR :7; - byte :1; - } MergedBits; -} RTICTLSTR; -extern volatile RTICTLSTR _RTICTL @(REG_BASE + 0x0000003B); -#define RTICTL _RTICTL.Byte -#define RTICTL_RTR0 _RTICTL.Bits.RTR0 -#define RTICTL_RTR1 _RTICTL.Bits.RTR1 -#define RTICTL_RTR2 _RTICTL.Bits.RTR2 -#define RTICTL_RTR3 _RTICTL.Bits.RTR3 -#define RTICTL_RTR4 _RTICTL.Bits.RTR4 -#define RTICTL_RTR5 _RTICTL.Bits.RTR5 -#define RTICTL_RTR6 _RTICTL.Bits.RTR6 -#define RTICTL_RTR _RTICTL.MergedBits.grpRTR - - -/*** COPCTL - CRG COP Control Register; 0x0000003C ***/ -typedef union { - byte Byte; - struct { - byte CR0 :1; /* COP Watchdog Timer Rate select Bit 0 */ - byte CR1 :1; /* COP Watchdog Timer Rate select Bit 1 */ - byte CR2 :1; /* COP Watchdog Timer Rate select Bit 2 */ - byte :1; - byte :1; - byte :1; - byte RSBCK :1; /* COP and RTI stop in Active BDM mode Bit */ - byte WCOP :1; /* Window COP mode */ - } Bits; - struct { - byte grpCR :3; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} COPCTLSTR; -extern volatile COPCTLSTR _COPCTL @(REG_BASE + 0x0000003C); -#define COPCTL _COPCTL.Byte -#define COPCTL_CR0 _COPCTL.Bits.CR0 -#define COPCTL_CR1 _COPCTL.Bits.CR1 -#define COPCTL_CR2 _COPCTL.Bits.CR2 -#define COPCTL_RSBCK _COPCTL.Bits.RSBCK -#define COPCTL_WCOP _COPCTL.Bits.WCOP -#define COPCTL_CR _COPCTL.MergedBits.grpCR - - -/*** CTCTL - CRG Test Control Register; 0x0000003E ***/ -typedef union { - byte Byte; - struct { - byte TCTL0 :1; /* CRG Test Control Bit 0 */ - byte TCTL1 :1; /* CRG Test Control Bit 1 */ - byte TCTL2 :1; /* CRG Test Control Bit 2 */ - byte TCTL3 :1; /* CRG Test Control Bit 3 */ - byte TCTL4 :1; /* CRG Test Control Bit 4 */ - byte TCTL5 :1; /* CRG Test Control Bit 5 */ - byte TCTL6 :1; /* CRG Test Control Bit 6 */ - byte TCTL7 :1; /* CRG Test Control Bit 7 */ - } Bits; - struct { - byte grpTCTL :8; - } MergedBits; -} CTCTLSTR; -extern volatile CTCTLSTR _CTCTL @(REG_BASE + 0x0000003E); -#define CTCTL _CTCTL.Byte -#define CTCTL_TCTL0 _CTCTL.Bits.TCTL0 -#define CTCTL_TCTL1 _CTCTL.Bits.TCTL1 -#define CTCTL_TCTL2 _CTCTL.Bits.TCTL2 -#define CTCTL_TCTL3 _CTCTL.Bits.TCTL3 -#define CTCTL_TCTL4 _CTCTL.Bits.TCTL4 -#define CTCTL_TCTL5 _CTCTL.Bits.TCTL5 -#define CTCTL_TCTL6 _CTCTL.Bits.TCTL6 -#define CTCTL_TCTL7 _CTCTL.Bits.TCTL7 -#define CTCTL_TCTL _CTCTL.MergedBits.grpTCTL - - -/*** ARMCOP - CRG COP Timer Arm/Reset Register; 0x0000003F ***/ -typedef union { - byte Byte; - struct { - byte BIT0 :1; /* CRG COP Timer Arm/Reset Bit 0 */ - byte BIT1 :1; /* CRG COP Timer Arm/Reset Bit 1 */ - byte BIT2 :1; /* CRG COP Timer Arm/Reset Bit 2 */ - byte BIT3 :1; /* CRG COP Timer Arm/Reset Bit 3 */ - byte BIT4 :1; /* CRG COP Timer Arm/Reset Bit 4 */ - byte BIT5 :1; /* CRG COP Timer Arm/Reset Bit 5 */ - byte BIT6 :1; /* CRG COP Timer Arm/Reset Bit 6 */ - byte BIT7 :1; /* CRG COP Timer Arm/Reset Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; -} ARMCOPSTR; -extern volatile ARMCOPSTR _ARMCOP @(REG_BASE + 0x0000003F); -#define ARMCOP _ARMCOP.Byte -#define ARMCOP_BIT0 _ARMCOP.Bits.BIT0 -#define ARMCOP_BIT1 _ARMCOP.Bits.BIT1 -#define ARMCOP_BIT2 _ARMCOP.Bits.BIT2 -#define ARMCOP_BIT3 _ARMCOP.Bits.BIT3 -#define ARMCOP_BIT4 _ARMCOP.Bits.BIT4 -#define ARMCOP_BIT5 _ARMCOP.Bits.BIT5 -#define ARMCOP_BIT6 _ARMCOP.Bits.BIT6 -#define ARMCOP_BIT7 _ARMCOP.Bits.BIT7 -#define ARMCOP_BIT _ARMCOP.MergedBits.grpBIT - - -/*** TIOS - Timer Input Capture/Output Compare Select; 0x00000040 ***/ -typedef union { - byte Byte; - struct { - byte IOS0 :1; /* Input Capture or Output Compare Channel Configuration Bit 0 */ - byte IOS1 :1; /* Input Capture or Output Compare Channel Configuration Bit 1 */ - byte IOS2 :1; /* Input Capture or Output Compare Channel Configuration Bit 2 */ - byte IOS3 :1; /* Input Capture or Output Compare Channel Configuration Bit 3 */ - byte IOS4 :1; /* Input Capture or Output Compare Channel Configuration Bit 4 */ - byte IOS5 :1; /* Input Capture or Output Compare Channel Configuration Bit 5 */ - byte IOS6 :1; /* Input Capture or Output Compare Channel Configuration Bit 6 */ - byte IOS7 :1; /* Input Capture or Output Compare Channel Configuration Bit 7 */ - } Bits; - struct { - byte grpIOS :8; - } MergedBits; -} TIOSSTR; -extern volatile TIOSSTR _TIOS @(REG_BASE + 0x00000040); -#define TIOS _TIOS.Byte -#define TIOS_IOS0 _TIOS.Bits.IOS0 -#define TIOS_IOS1 _TIOS.Bits.IOS1 -#define TIOS_IOS2 _TIOS.Bits.IOS2 -#define TIOS_IOS3 _TIOS.Bits.IOS3 -#define TIOS_IOS4 _TIOS.Bits.IOS4 -#define TIOS_IOS5 _TIOS.Bits.IOS5 -#define TIOS_IOS6 _TIOS.Bits.IOS6 -#define TIOS_IOS7 _TIOS.Bits.IOS7 -#define TIOS_IOS _TIOS.MergedBits.grpIOS - - -/*** CFORC - Timer Compare Force Register; 0x00000041 ***/ -typedef union { - byte Byte; - struct { - byte FOC0 :1; /* Force Output Compare Action for Channel 0 */ - byte FOC1 :1; /* Force Output Compare Action for Channel 1 */ - byte FOC2 :1; /* Force Output Compare Action for Channel 2 */ - byte FOC3 :1; /* Force Output Compare Action for Channel 3 */ - byte FOC4 :1; /* Force Output Compare Action for Channel 4 */ - byte FOC5 :1; /* Force Output Compare Action for Channel 5 */ - byte FOC6 :1; /* Force Output Compare Action for Channel 6 */ - byte FOC7 :1; /* Force Output Compare Action for Channel 7 */ - } Bits; - struct { - byte grpFOC :8; - } MergedBits; -} CFORCSTR; -extern volatile CFORCSTR _CFORC @(REG_BASE + 0x00000041); -#define CFORC _CFORC.Byte -#define CFORC_FOC0 _CFORC.Bits.FOC0 -#define CFORC_FOC1 _CFORC.Bits.FOC1 -#define CFORC_FOC2 _CFORC.Bits.FOC2 -#define CFORC_FOC3 _CFORC.Bits.FOC3 -#define CFORC_FOC4 _CFORC.Bits.FOC4 -#define CFORC_FOC5 _CFORC.Bits.FOC5 -#define CFORC_FOC6 _CFORC.Bits.FOC6 -#define CFORC_FOC7 _CFORC.Bits.FOC7 -#define CFORC_FOC _CFORC.MergedBits.grpFOC - - -/*** OC7M - Output Compare 7 Mask Register; 0x00000042 ***/ -typedef union { - byte Byte; - struct { - byte OC7M0 :1; /* Output Compare 7 Mask Bit 0 */ - byte OC7M1 :1; /* Output Compare 7 Mask Bit 1 */ - byte OC7M2 :1; /* Output Compare 7 Mask Bit 2 */ - byte OC7M3 :1; /* Output Compare 7 Mask Bit 3 */ - byte OC7M4 :1; /* Output Compare 7 Mask Bit 4 */ - byte OC7M5 :1; /* Output Compare 7 Mask Bit 5 */ - byte OC7M6 :1; /* Output Compare 7 Mask Bit 6 */ - byte OC7M7 :1; /* Output Compare 7 Mask Bit 7 */ - } Bits; - struct { - byte grpOC7M :8; - } MergedBits; -} OC7MSTR; -extern volatile OC7MSTR _OC7M @(REG_BASE + 0x00000042); -#define OC7M _OC7M.Byte -#define OC7M_OC7M0 _OC7M.Bits.OC7M0 -#define OC7M_OC7M1 _OC7M.Bits.OC7M1 -#define OC7M_OC7M2 _OC7M.Bits.OC7M2 -#define OC7M_OC7M3 _OC7M.Bits.OC7M3 -#define OC7M_OC7M4 _OC7M.Bits.OC7M4 -#define OC7M_OC7M5 _OC7M.Bits.OC7M5 -#define OC7M_OC7M6 _OC7M.Bits.OC7M6 -#define OC7M_OC7M7 _OC7M.Bits.OC7M7 -#define OC7M_OC7M _OC7M.MergedBits.grpOC7M - - -/*** OC7D - Output Compare 7 Data Register; 0x00000043 ***/ -typedef union { - byte Byte; - struct { - byte OC7D0 :1; /* Output Compare 7 Bit 0 */ - byte OC7D1 :1; /* Output Compare 7 Bit 1 */ - byte OC7D2 :1; /* Output Compare 7 Bit 2 */ - byte OC7D3 :1; /* Output Compare 7 Bit 3 */ - byte OC7D4 :1; /* Output Compare 7 Bit 4 */ - byte OC7D5 :1; /* Output Compare 7 Bit 5 */ - byte OC7D6 :1; /* Output Compare 7 Bit 6 */ - byte OC7D7 :1; /* Output Compare 7 Bit 7 */ - } Bits; - struct { - byte grpOC7D :8; - } MergedBits; -} OC7DSTR; -extern volatile OC7DSTR _OC7D @(REG_BASE + 0x00000043); -#define OC7D _OC7D.Byte -#define OC7D_OC7D0 _OC7D.Bits.OC7D0 -#define OC7D_OC7D1 _OC7D.Bits.OC7D1 -#define OC7D_OC7D2 _OC7D.Bits.OC7D2 -#define OC7D_OC7D3 _OC7D.Bits.OC7D3 -#define OC7D_OC7D4 _OC7D.Bits.OC7D4 -#define OC7D_OC7D5 _OC7D.Bits.OC7D5 -#define OC7D_OC7D6 _OC7D.Bits.OC7D6 -#define OC7D_OC7D7 _OC7D.Bits.OC7D7 -#define OC7D_OC7D _OC7D.MergedBits.grpOC7D - - -/*** TSCR1 - Timer System Control Register1; 0x00000046 ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte TFFCA :1; /* Timer Fast Flag Clear All */ - byte TSFRZ :1; /* Timer and Modulus Counter Stop While in Freeze Mode */ - byte TSWAI :1; /* Timer Module Stops While in Wait */ - byte TEN :1; /* Timer Enable */ - } Bits; -} TSCR1STR; -extern volatile TSCR1STR _TSCR1 @(REG_BASE + 0x00000046); -#define TSCR1 _TSCR1.Byte -#define TSCR1_TFFCA _TSCR1.Bits.TFFCA -#define TSCR1_TSFRZ _TSCR1.Bits.TSFRZ -#define TSCR1_TSWAI _TSCR1.Bits.TSWAI -#define TSCR1_TEN _TSCR1.Bits.TEN - - -/*** TTOV - Timer Toggle On Overflow Register; 0x00000047 ***/ -typedef union { - byte Byte; - struct { - byte TOV0 :1; /* Toggle On Overflow Bit 0 */ - byte TOV1 :1; /* Toggle On Overflow Bit 1 */ - byte TOV2 :1; /* Toggle On Overflow Bit 2 */ - byte TOV3 :1; /* Toggle On Overflow Bit 3 */ - byte TOV4 :1; /* Toggle On Overflow Bit 4 */ - byte TOV5 :1; /* Toggle On Overflow Bit 5 */ - byte TOV6 :1; /* Toggle On Overflow Bit 6 */ - byte TOV7 :1; /* Toggle On Overflow Bit 7 */ - } Bits; - struct { - byte grpTOV :8; - } MergedBits; -} TTOVSTR; -extern volatile TTOVSTR _TTOV @(REG_BASE + 0x00000047); -#define TTOV _TTOV.Byte -#define TTOV_TOV0 _TTOV.Bits.TOV0 -#define TTOV_TOV1 _TTOV.Bits.TOV1 -#define TTOV_TOV2 _TTOV.Bits.TOV2 -#define TTOV_TOV3 _TTOV.Bits.TOV3 -#define TTOV_TOV4 _TTOV.Bits.TOV4 -#define TTOV_TOV5 _TTOV.Bits.TOV5 -#define TTOV_TOV6 _TTOV.Bits.TOV6 -#define TTOV_TOV7 _TTOV.Bits.TOV7 -#define TTOV_TOV _TTOV.MergedBits.grpTOV - - -/*** TCTL1 - Timer Control Register 1; 0x00000048 ***/ -typedef union { - byte Byte; - struct { - byte OL4 :1; /* Output Level Bit 4 */ - byte OM4 :1; /* Output Mode Bit 4 */ - byte OL5 :1; /* Output Level Bit 5 */ - byte OM5 :1; /* Output Mode Bit 5 */ - byte OL6 :1; /* Output Level Bit 6 */ - byte OM6 :1; /* Output Mode Bit 6 */ - byte OL7 :1; /* Output Level Bit 7 */ - byte OM7 :1; /* Output Mode Bit 7 */ - } Bits; -} TCTL1STR; -extern volatile TCTL1STR _TCTL1 @(REG_BASE + 0x00000048); -#define TCTL1 _TCTL1.Byte -#define TCTL1_OL4 _TCTL1.Bits.OL4 -#define TCTL1_OM4 _TCTL1.Bits.OM4 -#define TCTL1_OL5 _TCTL1.Bits.OL5 -#define TCTL1_OM5 _TCTL1.Bits.OM5 -#define TCTL1_OL6 _TCTL1.Bits.OL6 -#define TCTL1_OM6 _TCTL1.Bits.OM6 -#define TCTL1_OL7 _TCTL1.Bits.OL7 -#define TCTL1_OM7 _TCTL1.Bits.OM7 - - -/*** TCTL2 - Timer Control Register 2; 0x00000049 ***/ -typedef union { - byte Byte; - struct { - byte OL0 :1; /* Output Level Bit 0 */ - byte OM0 :1; /* Output Mode Bit 0 */ - byte OL1 :1; /* Output Level Bit 1 */ - byte OM1 :1; /* Output Mode Bit 1 */ - byte OL2 :1; /* Output Level Bit 2 */ - byte OM2 :1; /* Output Mode Bit 2 */ - byte OL3 :1; /* Output Level Bit 3 */ - byte OM3 :1; /* Output Mode Bit 3 */ - } Bits; -} TCTL2STR; -extern volatile TCTL2STR _TCTL2 @(REG_BASE + 0x00000049); -#define TCTL2 _TCTL2.Byte -#define TCTL2_OL0 _TCTL2.Bits.OL0 -#define TCTL2_OM0 _TCTL2.Bits.OM0 -#define TCTL2_OL1 _TCTL2.Bits.OL1 -#define TCTL2_OM1 _TCTL2.Bits.OM1 -#define TCTL2_OL2 _TCTL2.Bits.OL2 -#define TCTL2_OM2 _TCTL2.Bits.OM2 -#define TCTL2_OL3 _TCTL2.Bits.OL3 -#define TCTL2_OM3 _TCTL2.Bits.OM3 - - -/*** TCTL3 - Timer Control Register 3; 0x0000004A ***/ -typedef union { - byte Byte; - struct { - byte EDG4A :1; /* Input Capture Edge Control 4A */ - byte EDG4B :1; /* Input Capture Edge Control 4B */ - byte EDG5A :1; /* Input Capture Edge Control 5A */ - byte EDG5B :1; /* Input Capture Edge Control 5B */ - byte EDG6A :1; /* Input Capture Edge Control 6A */ - byte EDG6B :1; /* Input Capture Edge Control 6B */ - byte EDG7A :1; /* Input Capture Edge Control 7A */ - byte EDG7B :1; /* Input Capture Edge Control 7B */ - } Bits; -} TCTL3STR; -extern volatile TCTL3STR _TCTL3 @(REG_BASE + 0x0000004A); -#define TCTL3 _TCTL3.Byte -#define TCTL3_EDG4A _TCTL3.Bits.EDG4A -#define TCTL3_EDG4B _TCTL3.Bits.EDG4B -#define TCTL3_EDG5A _TCTL3.Bits.EDG5A -#define TCTL3_EDG5B _TCTL3.Bits.EDG5B -#define TCTL3_EDG6A _TCTL3.Bits.EDG6A -#define TCTL3_EDG6B _TCTL3.Bits.EDG6B -#define TCTL3_EDG7A _TCTL3.Bits.EDG7A -#define TCTL3_EDG7B _TCTL3.Bits.EDG7B - - -/*** TCTL4 - Timer Control Register 4; 0x0000004B ***/ -typedef union { - byte Byte; - struct { - byte EDG0A :1; /* Input Capture Edge Control 0A */ - byte EDG0B :1; /* Input Capture Edge Control 0B */ - byte EDG1A :1; /* Input Capture Edge Control 1A */ - byte EDG1B :1; /* Input Capture Edge Control 1B */ - byte EDG2A :1; /* Input Capture Edge Control 2A */ - byte EDG2B :1; /* Input Capture Edge Control 2B */ - byte EDG3A :1; /* Input Capture Edge Control 3A */ - byte EDG3B :1; /* Input Capture Edge Control 3B */ - } Bits; -} TCTL4STR; -extern volatile TCTL4STR _TCTL4 @(REG_BASE + 0x0000004B); -#define TCTL4 _TCTL4.Byte -#define TCTL4_EDG0A _TCTL4.Bits.EDG0A -#define TCTL4_EDG0B _TCTL4.Bits.EDG0B -#define TCTL4_EDG1A _TCTL4.Bits.EDG1A -#define TCTL4_EDG1B _TCTL4.Bits.EDG1B -#define TCTL4_EDG2A _TCTL4.Bits.EDG2A -#define TCTL4_EDG2B _TCTL4.Bits.EDG2B -#define TCTL4_EDG3A _TCTL4.Bits.EDG3A -#define TCTL4_EDG3B _TCTL4.Bits.EDG3B - - -/*** TIE - Timer Interrupt Enable Register; 0x0000004C ***/ -typedef union { - byte Byte; - struct { - byte C0I :1; /* Input Capture/Output Compare Interrupt Enable Bit 0 */ - byte C1I :1; /* Input Capture/Output Compare Interrupt Enable Bit 1 */ - byte C2I :1; /* Input Capture/Output Compare Interrupt Enable Bit 2 */ - byte C3I :1; /* Input Capture/Output Compare Interrupt Enable Bit 3 */ - byte C4I :1; /* Input Capture/Output Compare Interrupt Enable Bit 4 */ - byte C5I :1; /* Input Capture/Output Compare Interrupt Enable Bit 5 */ - byte C6I :1; /* Input Capture/Output Compare Interrupt Enable Bit 6 */ - byte C7I :1; /* Input Capture/Output Compare Interrupt Enable Bit 7 */ - } Bits; -} TIESTR; -extern volatile TIESTR _TIE @(REG_BASE + 0x0000004C); -#define TIE _TIE.Byte -#define TIE_C0I _TIE.Bits.C0I -#define TIE_C1I _TIE.Bits.C1I -#define TIE_C2I _TIE.Bits.C2I -#define TIE_C3I _TIE.Bits.C3I -#define TIE_C4I _TIE.Bits.C4I -#define TIE_C5I _TIE.Bits.C5I -#define TIE_C6I _TIE.Bits.C6I -#define TIE_C7I _TIE.Bits.C7I - - -/*** TSCR2 - Timer System Control Register 2; 0x0000004D ***/ -typedef union { - byte Byte; - struct { - byte PR0 :1; /* Timer Prescaler Select Bit 0 */ - byte PR1 :1; /* Timer Prescaler Select Bit 1 */ - byte PR2 :1; /* Timer Prescaler Select Bit 2 */ - byte TCRE :1; /* Timer Counter Reset Enable */ - byte :1; - byte :1; - byte :1; - byte TOI :1; /* Timer Overflow Interrupt Enable */ - } Bits; - struct { - byte grpPR :3; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} TSCR2STR; -extern volatile TSCR2STR _TSCR2 @(REG_BASE + 0x0000004D); -#define TSCR2 _TSCR2.Byte -#define TSCR2_PR0 _TSCR2.Bits.PR0 -#define TSCR2_PR1 _TSCR2.Bits.PR1 -#define TSCR2_PR2 _TSCR2.Bits.PR2 -#define TSCR2_TCRE _TSCR2.Bits.TCRE -#define TSCR2_TOI _TSCR2.Bits.TOI -#define TSCR2_PR _TSCR2.MergedBits.grpPR - - -/*** TFLG1 - Main Timer Interrupt Flag 1; 0x0000004E ***/ -typedef union { - byte Byte; - struct { - byte C0F :1; /* Input Capture/Output Compare Channel Flag 0 */ - byte C1F :1; /* Input Capture/Output Compare Channel Flag 1 */ - byte C2F :1; /* Input Capture/Output Compare Channel Flag 2 */ - byte C3F :1; /* Input Capture/Output Compare Channel Flag 3 */ - byte C4F :1; /* Input Capture/Output Compare Channel Flag 4 */ - byte C5F :1; /* Input Capture/Output Compare Channel Flag 5 */ - byte C6F :1; /* Input Capture/Output Compare Channel Flag 6 */ - byte C7F :1; /* Input Capture/Output Compare Channel Flag 7 */ - } Bits; -} TFLG1STR; -extern volatile TFLG1STR _TFLG1 @(REG_BASE + 0x0000004E); -#define TFLG1 _TFLG1.Byte -#define TFLG1_C0F _TFLG1.Bits.C0F -#define TFLG1_C1F _TFLG1.Bits.C1F -#define TFLG1_C2F _TFLG1.Bits.C2F -#define TFLG1_C3F _TFLG1.Bits.C3F -#define TFLG1_C4F _TFLG1.Bits.C4F -#define TFLG1_C5F _TFLG1.Bits.C5F -#define TFLG1_C6F _TFLG1.Bits.C6F -#define TFLG1_C7F _TFLG1.Bits.C7F - - -/*** TFLG2 - Main Timer Interrupt Flag 2; 0x0000004F ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte TOF :1; /* Timer Overflow Flag */ - } Bits; -} TFLG2STR; -extern volatile TFLG2STR _TFLG2 @(REG_BASE + 0x0000004F); -#define TFLG2 _TFLG2.Byte -#define TFLG2_TOF _TFLG2.Bits.TOF - - -/*** PACTL - 16-Bit Pulse Accumulator A Control Register; 0x00000060 ***/ -typedef union { - byte Byte; - struct { - byte PAI :1; /* Pulse Accumulator Input Interrupt enable */ - byte PAOVI :1; /* Pulse Accumulator A Overflow Interrupt enable */ - byte CLK0 :1; /* Clock Select Bit 0 */ - byte CLK1 :1; /* Clock Select Bit 1 */ - byte PEDGE :1; /* Pulse Accumulator Edge Control */ - byte PAMOD :1; /* Pulse Accumulator Mode */ - byte PAEN :1; /* Pulse Accumulator A System Enable */ - byte :1; - } Bits; - struct { - byte :1; - byte :1; - byte grpCLK :2; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} PACTLSTR; -extern volatile PACTLSTR _PACTL @(REG_BASE + 0x00000060); -#define PACTL _PACTL.Byte -#define PACTL_PAI _PACTL.Bits.PAI -#define PACTL_PAOVI _PACTL.Bits.PAOVI -#define PACTL_CLK0 _PACTL.Bits.CLK0 -#define PACTL_CLK1 _PACTL.Bits.CLK1 -#define PACTL_PEDGE _PACTL.Bits.PEDGE -#define PACTL_PAMOD _PACTL.Bits.PAMOD -#define PACTL_PAEN _PACTL.Bits.PAEN -#define PACTL_CLK _PACTL.MergedBits.grpCLK - - -/*** PAFLG - Pulse Accumulator A Flag Register; 0x00000061 ***/ -typedef union { - byte Byte; - struct { - byte PAIF :1; /* Pulse Accumulator Input edge Flag */ - byte PAOVF :1; /* Pulse Accumulator A Overflow Flag */ - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; -} PAFLGSTR; -extern volatile PAFLGSTR _PAFLG @(REG_BASE + 0x00000061); -#define PAFLG _PAFLG.Byte -#define PAFLG_PAIF _PAFLG.Bits.PAIF -#define PAFLG_PAOVF _PAFLG.Bits.PAOVF - - -/*** ATDSTAT0 - A/D Status Register 0; 0x00000086 ***/ -typedef union { - byte Byte; - struct { - byte CC0 :1; /* Conversion Counter 0 */ - byte CC1 :1; /* Conversion Counter 1 */ - byte CC2 :1; /* Conversion Counter 2 */ - byte :1; - byte FIFOR :1; /* FIFO Over Run Flag */ - byte ETORF :1; /* External Trigger Overrun Flag */ - byte :1; - byte SCF :1; /* Sequence Complete Flag */ - } Bits; - struct { - byte grpCC :3; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} ATDSTAT0STR; -extern volatile ATDSTAT0STR _ATDSTAT0 @(REG_BASE + 0x00000086); -#define ATDSTAT0 _ATDSTAT0.Byte -#define ATDSTAT0_CC0 _ATDSTAT0.Bits.CC0 -#define ATDSTAT0_CC1 _ATDSTAT0.Bits.CC1 -#define ATDSTAT0_CC2 _ATDSTAT0.Bits.CC2 -#define ATDSTAT0_FIFOR _ATDSTAT0.Bits.FIFOR -#define ATDSTAT0_ETORF _ATDSTAT0.Bits.ETORF -#define ATDSTAT0_SCF _ATDSTAT0.Bits.SCF -#define ATDSTAT0_CC _ATDSTAT0.MergedBits.grpCC - - -/*** ATDSTAT1 - A/D Status Register 1; 0x0000008B ***/ -typedef union { - byte Byte; - struct { - byte CCF0 :1; /* Conversion Complete Flag 0 */ - byte CCF1 :1; /* Conversion Complete Flag 1 */ - byte CCF2 :1; /* Conversion Complete Flag 2 */ - byte CCF3 :1; /* Conversion Complete Flag 3 */ - byte CCF4 :1; /* Conversion Complete Flag 4 */ - byte CCF5 :1; /* Conversion Complete Flag 5 */ - byte CCF6 :1; /* Conversion Complete Flag 6 */ - byte CCF7 :1; /* Conversion Complete Flag 7 */ - } Bits; - struct { - byte grpCCF :8; - } MergedBits; -} ATDSTAT1STR; -extern volatile ATDSTAT1STR _ATDSTAT1 @(REG_BASE + 0x0000008B); -#define ATDSTAT1 _ATDSTAT1.Byte -#define ATDSTAT1_CCF0 _ATDSTAT1.Bits.CCF0 -#define ATDSTAT1_CCF1 _ATDSTAT1.Bits.CCF1 -#define ATDSTAT1_CCF2 _ATDSTAT1.Bits.CCF2 -#define ATDSTAT1_CCF3 _ATDSTAT1.Bits.CCF3 -#define ATDSTAT1_CCF4 _ATDSTAT1.Bits.CCF4 -#define ATDSTAT1_CCF5 _ATDSTAT1.Bits.CCF5 -#define ATDSTAT1_CCF6 _ATDSTAT1.Bits.CCF6 -#define ATDSTAT1_CCF7 _ATDSTAT1.Bits.CCF7 -#define ATDSTAT1_CCF _ATDSTAT1.MergedBits.grpCCF - - -/*** ATDDIEN - ATD Input Enable Mask Register; 0x0000008D ***/ -typedef union { - byte Byte; - struct { - byte BIT0 :1; /* Disable/Enable digital input buffer */ - byte BIT1 :1; /* Disable/Enable digital input buffer */ - byte BIT2 :1; /* Disable/Enable digital input buffer */ - byte BIT3 :1; /* Disable/Enable digital input buffer */ - byte BIT4 :1; /* Disable/Enable digital input buffer */ - byte BIT5 :1; /* Disable/Enable digital input buffer */ - byte BIT6 :1; /* Disable/Enable digital input buffer */ - byte BIT7 :1; /* Disable/Enable digital input buffer */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; -} ATDDIENSTR; -extern volatile ATDDIENSTR _ATDDIEN @(REG_BASE + 0x0000008D); -#define ATDDIEN _ATDDIEN.Byte -#define ATDDIEN_BIT0 _ATDDIEN.Bits.BIT0 -#define ATDDIEN_BIT1 _ATDDIEN.Bits.BIT1 -#define ATDDIEN_BIT2 _ATDDIEN.Bits.BIT2 -#define ATDDIEN_BIT3 _ATDDIEN.Bits.BIT3 -#define ATDDIEN_BIT4 _ATDDIEN.Bits.BIT4 -#define ATDDIEN_BIT5 _ATDDIEN.Bits.BIT5 -#define ATDDIEN_BIT6 _ATDDIEN.Bits.BIT6 -#define ATDDIEN_BIT7 _ATDDIEN.Bits.BIT7 -#define ATDDIEN_BIT _ATDDIEN.MergedBits.grpBIT - - -/*** PORTAD0 - Port AD0 Register; 0x0000008F ***/ -typedef union { - byte Byte; - struct { - byte BIT0 :1; /* AN0 */ - byte BIT1 :1; /* AN1 */ - byte BIT2 :1; /* AN2 */ - byte BIT3 :1; /* AN3 */ - byte BIT4 :1; /* AN4 */ - byte BIT5 :1; /* AN5 */ - byte BIT6 :1; /* AN6 */ - byte BIT7 :1; /* AN7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; -} PORTAD0STR; -extern volatile PORTAD0STR _PORTAD0 @(REG_BASE + 0x0000008F); -#define PORTAD0 _PORTAD0.Byte -#define PORTAD0_BIT0 _PORTAD0.Bits.BIT0 -#define PORTAD0_BIT1 _PORTAD0.Bits.BIT1 -#define PORTAD0_BIT2 _PORTAD0.Bits.BIT2 -#define PORTAD0_BIT3 _PORTAD0.Bits.BIT3 -#define PORTAD0_BIT4 _PORTAD0.Bits.BIT4 -#define PORTAD0_BIT5 _PORTAD0.Bits.BIT5 -#define PORTAD0_BIT6 _PORTAD0.Bits.BIT6 -#define PORTAD0_BIT7 _PORTAD0.Bits.BIT7 -#define PORTAD0_BIT _PORTAD0.MergedBits.grpBIT - - -/*** SCICR1 - SCI Control Register 1; 0x000000CA ***/ -typedef union { - byte Byte; - struct { - byte PT :1; /* Parity Type Bit */ - byte PE :1; /* Parity Enable Bit */ - byte ILT :1; /* Idle Line Type Bit */ - byte WAKE :1; /* Wakeup Condition Bit */ - byte M :1; /* Data Format Mode Bit */ - byte RSRC :1; /* Receiver Source Bit */ - byte SCISWAI :1; /* SCI Stop in Wait Mode Bit */ - byte LOOPS :1; /* Loop Select Bit */ - } Bits; -} SCICR1STR; -extern volatile SCICR1STR _SCICR1 @(REG_BASE + 0x000000CA); -#define SCICR1 _SCICR1.Byte -#define SCICR1_PT _SCICR1.Bits.PT -#define SCICR1_PE _SCICR1.Bits.PE -#define SCICR1_ILT _SCICR1.Bits.ILT -#define SCICR1_WAKE _SCICR1.Bits.WAKE -#define SCICR1_M _SCICR1.Bits.M -#define SCICR1_RSRC _SCICR1.Bits.RSRC -#define SCICR1_SCISWAI _SCICR1.Bits.SCISWAI -#define SCICR1_LOOPS _SCICR1.Bits.LOOPS - - -/*** SCICR2 - SCI Control Register 2; 0x000000CB ***/ -typedef union { - byte Byte; - struct { - byte SBK :1; /* Send Break Bit */ - byte RWU :1; /* Receiver Wakeup Bit */ - byte RE :1; /* Receiver Enable Bit */ - byte TE :1; /* Transmitter Enable Bit */ - byte ILIE :1; /* Idle Line Interrupt Enable Bit */ - byte RIE :1; /* Receiver Full Interrupt Enable Bit */ - byte TCIE :1; /* Transmission Complete Interrupt Enable Bit */ - byte SCTIE :1; /* Transmitter Interrupt Enable Bit */ - } Bits; -} SCICR2STR; -extern volatile SCICR2STR _SCICR2 @(REG_BASE + 0x000000CB); -#define SCICR2 _SCICR2.Byte -#define SCICR2_SBK _SCICR2.Bits.SBK -#define SCICR2_RWU _SCICR2.Bits.RWU -#define SCICR2_RE _SCICR2.Bits.RE -#define SCICR2_TE _SCICR2.Bits.TE -#define SCICR2_ILIE _SCICR2.Bits.ILIE -#define SCICR2_RIE _SCICR2.Bits.RIE -#define SCICR2_TCIE _SCICR2.Bits.TCIE -#define SCICR2_SCTIE _SCICR2.Bits.SCTIE - - -/*** SCISR1 - SCI Status Register 1; 0x000000CC ***/ -typedef union { - byte Byte; - struct { - byte PF :1; /* Parity Error Flag */ - byte FE :1; /* Framing Error Flag */ - byte NF :1; /* Noise Flag */ - byte OR :1; /* Overrun Flag */ - byte IDLE :1; /* Idle Line Flag */ - byte RDRF :1; /* Receive Data Register Full Flag */ - byte TC :1; /* Transmit Complete Flag */ - byte TDRE :1; /* Transmit Data Register Empty Flag */ - } Bits; -} SCISR1STR; -extern volatile SCISR1STR _SCISR1 @(REG_BASE + 0x000000CC); -#define SCISR1 _SCISR1.Byte -#define SCISR1_PF _SCISR1.Bits.PF -#define SCISR1_FE _SCISR1.Bits.FE -#define SCISR1_NF _SCISR1.Bits.NF -#define SCISR1_OR _SCISR1.Bits.OR -#define SCISR1_IDLE _SCISR1.Bits.IDLE -#define SCISR1_RDRF _SCISR1.Bits.RDRF -#define SCISR1_TC _SCISR1.Bits.TC -#define SCISR1_TDRE _SCISR1.Bits.TDRE - - -/*** SCISR2 - SCI Status Register 2; 0x000000CD ***/ -typedef union { - byte Byte; - struct { - byte RAF :1; /* Receiver Active Flag */ - byte TXDIR :1; /* Transmitter pin data direction in Single-Wire mode */ - byte BRK13 :1; /* Break Transmit character length */ - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; -} SCISR2STR; -extern volatile SCISR2STR _SCISR2 @(REG_BASE + 0x000000CD); -#define SCISR2 _SCISR2.Byte -#define SCISR2_RAF _SCISR2.Bits.RAF -#define SCISR2_TXDIR _SCISR2.Bits.TXDIR -#define SCISR2_BRK13 _SCISR2.Bits.BRK13 - - -/*** SCIDRH - SCI Data Register High; 0x000000CE ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte T8 :1; /* Transmit Bit 8 */ - byte R8 :1; /* Received Bit 8 */ - } Bits; -} SCIDRHSTR; -extern volatile SCIDRHSTR _SCIDRH @(REG_BASE + 0x000000CE); -#define SCIDRH _SCIDRH.Byte -#define SCIDRH_T8 _SCIDRH.Bits.T8 -#define SCIDRH_R8 _SCIDRH.Bits.R8 - - -/*** SCIDRL - SCI Data Register Low; 0x000000CF ***/ -typedef union { - byte Byte; - struct { - byte R0_T0 :1; /* Received bit 0 or Transmit bit 0 */ - byte R1_T1 :1; /* Received bit 1 or Transmit bit 1 */ - byte R2_T2 :1; /* Received bit 2 or Transmit bit 2 */ - byte R3_T3 :1; /* Received bit 3 or Transmit bit 3 */ - byte R4_T4 :1; /* Received bit 4 or Transmit bit 4 */ - byte R5_T5 :1; /* Received bit 5 or Transmit bit 5 */ - byte R6_T6 :1; /* Received bit 6 or Transmit bit 6 */ - byte R7_T7 :1; /* Received bit 7 or Transmit bit 7 */ - } Bits; -} SCIDRLSTR; -extern volatile SCIDRLSTR _SCIDRL @(REG_BASE + 0x000000CF); -#define SCIDRL _SCIDRL.Byte -#define SCIDRL_R0_T0 _SCIDRL.Bits.R0_T0 -#define SCIDRL_R1_T1 _SCIDRL.Bits.R1_T1 -#define SCIDRL_R2_T2 _SCIDRL.Bits.R2_T2 -#define SCIDRL_R3_T3 _SCIDRL.Bits.R3_T3 -#define SCIDRL_R4_T4 _SCIDRL.Bits.R4_T4 -#define SCIDRL_R5_T5 _SCIDRL.Bits.R5_T5 -#define SCIDRL_R6_T6 _SCIDRL.Bits.R6_T6 -#define SCIDRL_R7_T7 _SCIDRL.Bits.R7_T7 - - -/*** SPICR1 - SPI Control Register; 0x000000D8 ***/ -typedef union { - byte Byte; - struct { - byte LSBFE :1; /* SPI LSB-First Enable */ - byte SSOE :1; /* Slave Select Output Enable */ - byte CPHA :1; /* SPI Clock Phase Bit */ - byte CPOL :1; /* SPI Clock Polarity Bit */ - byte MSTR :1; /* SPI Master/Slave Mode Select Bit */ - byte SPTIE :1; /* SPI Transmit Interrupt Enable */ - byte SPE :1; /* SPI System Enable Bit */ - byte SPIE :1; /* SPI Interrupt Enable Bit */ - } Bits; -} SPICR1STR; -extern volatile SPICR1STR _SPICR1 @(REG_BASE + 0x000000D8); -#define SPICR1 _SPICR1.Byte -#define SPICR1_LSBFE _SPICR1.Bits.LSBFE -#define SPICR1_SSOE _SPICR1.Bits.SSOE -#define SPICR1_CPHA _SPICR1.Bits.CPHA -#define SPICR1_CPOL _SPICR1.Bits.CPOL -#define SPICR1_MSTR _SPICR1.Bits.MSTR -#define SPICR1_SPTIE _SPICR1.Bits.SPTIE -#define SPICR1_SPE _SPICR1.Bits.SPE -#define SPICR1_SPIE _SPICR1.Bits.SPIE - - -/*** SPICR2 - SPI Control Register 2; 0x000000D9 ***/ -typedef union { - byte Byte; - struct { - byte SPC0 :1; /* Serial Pin Control Bit 0 */ - byte SPISWAI :1; /* SPI Stop in Wait Mode Bit */ - byte :1; - byte BIDIROE :1; /* Output enable in the Bidirectional mode of operation */ - byte MODFEN :1; /* Mode Fault Enable Bit */ - byte :1; - byte :1; - byte :1; - } Bits; -} SPICR2STR; -extern volatile SPICR2STR _SPICR2 @(REG_BASE + 0x000000D9); -#define SPICR2 _SPICR2.Byte -#define SPICR2_SPC0 _SPICR2.Bits.SPC0 -#define SPICR2_SPISWAI _SPICR2.Bits.SPISWAI -#define SPICR2_BIDIROE _SPICR2.Bits.BIDIROE -#define SPICR2_MODFEN _SPICR2.Bits.MODFEN - - -/*** SPIBR - SPI Baud Rate Register; 0x000000DA ***/ -typedef union { - byte Byte; - struct { - byte SPR0 :1; /* SPI Baud Rate Selection Bit 0 */ - byte SPR1 :1; /* SPI Baud Rate Selection Bit 1 */ - byte SPR2 :1; /* SPI Baud Rate Selection Bit 2 */ - byte :1; - byte SPPR0 :1; /* SPI Baud Rate Preselection Bits 0 */ - byte SPPR1 :1; /* SPI Baud Rate Preselection Bits 1 */ - byte SPPR2 :1; /* SPI Baud Rate Preselection Bits 2 */ - byte :1; - } Bits; - struct { - byte grpSPR :3; - byte :1; - byte grpSPPR :3; - byte :1; - } MergedBits; -} SPIBRSTR; -extern volatile SPIBRSTR _SPIBR @(REG_BASE + 0x000000DA); -#define SPIBR _SPIBR.Byte -#define SPIBR_SPR0 _SPIBR.Bits.SPR0 -#define SPIBR_SPR1 _SPIBR.Bits.SPR1 -#define SPIBR_SPR2 _SPIBR.Bits.SPR2 -#define SPIBR_SPPR0 _SPIBR.Bits.SPPR0 -#define SPIBR_SPPR1 _SPIBR.Bits.SPPR1 -#define SPIBR_SPPR2 _SPIBR.Bits.SPPR2 -#define SPIBR_SPR _SPIBR.MergedBits.grpSPR -#define SPIBR_SPPR _SPIBR.MergedBits.grpSPPR - - -/*** SPISR - SPI Status Register; 0x000000DB ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte MODF :1; /* Mode Fault Flag */ - byte SPTEF :1; /* SPI Transmit Empty Interrupt Flag */ - byte :1; - byte SPIF :1; /* SPIF Receive Interrupt Flag */ - } Bits; -} SPISRSTR; -extern volatile SPISRSTR _SPISR @(REG_BASE + 0x000000DB); -#define SPISR _SPISR.Byte -#define SPISR_MODF _SPISR.Bits.MODF -#define SPISR_SPTEF _SPISR.Bits.SPTEF -#define SPISR_SPIF _SPISR.Bits.SPIF - - -/*** SPIDR - SPI Data Register; 0x000000DD ***/ -typedef union { - byte Byte; - struct { - byte grpBIT :8; - } MergedBits; -} SPIDRSTR; -extern volatile SPIDRSTR _SPIDR @(REG_BASE + 0x000000DD); -#define SPIDR _SPIDR.Byte -#define SPIDR_BIT _SPIDR.MergedBits.grpBIT - - -/*** PWME - PWM Enable Register; 0x000000E0 ***/ -typedef union { - byte Byte; - struct { - byte PWME0 :1; /* Pulse Width Channel 0 Enable */ - byte PWME1 :1; /* Pulse Width Channel 1 Enable */ - byte PWME2 :1; /* Pulse Width Channel 2 Enable */ - byte PWME3 :1; /* Pulse Width Channel 3 Enable */ - byte PWME4 :1; /* Pulse Width Channel 4 Enable */ - byte PWME5 :1; /* Pulse Width Channel 5 Enable */ - byte PWME6 :1; /* Pulse Width Channel 6 Enable */ - byte PWME7 :1; /* Pulse Width Channel 7 Enable */ - } Bits; - struct { - byte grpPWME :8; - } MergedBits; -} PWMESTR; -extern volatile PWMESTR _PWME @(REG_BASE + 0x000000E0); -#define PWME _PWME.Byte -#define PWME_PWME0 _PWME.Bits.PWME0 -#define PWME_PWME1 _PWME.Bits.PWME1 -#define PWME_PWME2 _PWME.Bits.PWME2 -#define PWME_PWME3 _PWME.Bits.PWME3 -#define PWME_PWME4 _PWME.Bits.PWME4 -#define PWME_PWME5 _PWME.Bits.PWME5 -#define PWME_PWME6 _PWME.Bits.PWME6 -#define PWME_PWME7 _PWME.Bits.PWME7 -#define PWME_PWME _PWME.MergedBits.grpPWME - - -/*** PWMPOL - PWM Polarity Register; 0x000000E1 ***/ -typedef union { - byte Byte; - struct { - byte PPOL0 :1; /* Pulse Width Channel 0 Polarity */ - byte PPOL1 :1; /* Pulse Width Channel 1 Polarity */ - byte PPOL2 :1; /* Pulse Width Channel 2 Polarity */ - byte PPOL3 :1; /* Pulse Width Channel 3 Polarity */ - byte PPOL4 :1; /* Pulse Width Channel 4 Polarity */ - byte PPOL5 :1; /* Pulse Width Channel 5 Polarity */ - byte PPOL6 :1; /* Pulse Width Channel 6 Polarity */ - byte PPOL7 :1; /* Pulse Width Channel 7 Polarity */ - } Bits; - struct { - byte grpPPOL :8; - } MergedBits; -} PWMPOLSTR; -extern volatile PWMPOLSTR _PWMPOL @(REG_BASE + 0x000000E1); -#define PWMPOL _PWMPOL.Byte -#define PWMPOL_PPOL0 _PWMPOL.Bits.PPOL0 -#define PWMPOL_PPOL1 _PWMPOL.Bits.PPOL1 -#define PWMPOL_PPOL2 _PWMPOL.Bits.PPOL2 -#define PWMPOL_PPOL3 _PWMPOL.Bits.PPOL3 -#define PWMPOL_PPOL4 _PWMPOL.Bits.PPOL4 -#define PWMPOL_PPOL5 _PWMPOL.Bits.PPOL5 -#define PWMPOL_PPOL6 _PWMPOL.Bits.PPOL6 -#define PWMPOL_PPOL7 _PWMPOL.Bits.PPOL7 -#define PWMPOL_PPOL _PWMPOL.MergedBits.grpPPOL - - -/*** PWMCLK - PWM Clock Select Register; 0x000000E2 ***/ -typedef union { - byte Byte; - struct { - byte PCLK0 :1; /* Pulse Width Channel 0 Clock Select */ - byte PCLK1 :1; /* Pulse Width Channel 1 Clock Select */ - byte PCLK2 :1; /* Pulse Width Channel 2 Clock Select */ - byte PCLK3 :1; /* Pulse Width Channel 3 Clock Select */ - byte PCLK4 :1; /* Pulse Width Channel 4 Clock Select */ - byte PCLK5 :1; /* Pulse Width Channel 5 Clock Select */ - byte PCLK6 :1; /* Pulse Width Channel 6 Clock Select */ - byte PCLK7 :1; /* Pulse Width Channel 7 Clock Select */ - } Bits; - struct { - byte grpPCLK :8; - } MergedBits; -} PWMCLKSTR; -extern volatile PWMCLKSTR _PWMCLK @(REG_BASE + 0x000000E2); -#define PWMCLK _PWMCLK.Byte -#define PWMCLK_PCLK0 _PWMCLK.Bits.PCLK0 -#define PWMCLK_PCLK1 _PWMCLK.Bits.PCLK1 -#define PWMCLK_PCLK2 _PWMCLK.Bits.PCLK2 -#define PWMCLK_PCLK3 _PWMCLK.Bits.PCLK3 -#define PWMCLK_PCLK4 _PWMCLK.Bits.PCLK4 -#define PWMCLK_PCLK5 _PWMCLK.Bits.PCLK5 -#define PWMCLK_PCLK6 _PWMCLK.Bits.PCLK6 -#define PWMCLK_PCLK7 _PWMCLK.Bits.PCLK7 -#define PWMCLK_PCLK _PWMCLK.MergedBits.grpPCLK - - -/*** PWMPRCLK - PWM Prescale Clock Select Register; 0x000000E3 ***/ -typedef union { - byte Byte; - struct { - byte PCKA0 :1; /* Prescaler Select for Clock A 0 */ - byte PCKA1 :1; /* Prescaler Select for Clock A 1 */ - byte PCKA2 :1; /* Prescaler Select for Clock A 2 */ - byte :1; - byte PCKB0 :1; /* Prescaler Select for Clock B 0 */ - byte PCKB1 :1; /* Prescaler Select for Clock B 1 */ - byte PCKB2 :1; /* Prescaler Select for Clock B 2 */ - byte :1; - } Bits; - struct { - byte grpPCKA :3; - byte :1; - byte grpPCKB :3; - byte :1; - } MergedBits; -} PWMPRCLKSTR; -extern volatile PWMPRCLKSTR _PWMPRCLK @(REG_BASE + 0x000000E3); -#define PWMPRCLK _PWMPRCLK.Byte -#define PWMPRCLK_PCKA0 _PWMPRCLK.Bits.PCKA0 -#define PWMPRCLK_PCKA1 _PWMPRCLK.Bits.PCKA1 -#define PWMPRCLK_PCKA2 _PWMPRCLK.Bits.PCKA2 -#define PWMPRCLK_PCKB0 _PWMPRCLK.Bits.PCKB0 -#define PWMPRCLK_PCKB1 _PWMPRCLK.Bits.PCKB1 -#define PWMPRCLK_PCKB2 _PWMPRCLK.Bits.PCKB2 -#define PWMPRCLK_PCKA _PWMPRCLK.MergedBits.grpPCKA -#define PWMPRCLK_PCKB _PWMPRCLK.MergedBits.grpPCKB - - -/*** PWMCAE - PWM Center Align Enable Register; 0x000000E4 ***/ -typedef union { - byte Byte; - struct { - byte CAE0 :1; /* Center Aligned Output Mode on channel 0 */ - byte CAE1 :1; /* Center Aligned Output Mode on channel 1 */ - byte CAE2 :1; /* Center Aligned Output Mode on channel 2 */ - byte CAE3 :1; /* Center Aligned Output Mode on channel 3 */ - byte CAE4 :1; /* Center Aligned Output Mode on channel 4 */ - byte CAE5 :1; /* Center Aligned Output Mode on channel 5 */ - byte CAE6 :1; /* Center Aligned Output Mode on channel 6 */ - byte CAE7 :1; /* Center Aligned Output Mode on channel 7 */ - } Bits; - struct { - byte grpCAE :8; - } MergedBits; -} PWMCAESTR; -extern volatile PWMCAESTR _PWMCAE @(REG_BASE + 0x000000E4); -#define PWMCAE _PWMCAE.Byte -#define PWMCAE_CAE0 _PWMCAE.Bits.CAE0 -#define PWMCAE_CAE1 _PWMCAE.Bits.CAE1 -#define PWMCAE_CAE2 _PWMCAE.Bits.CAE2 -#define PWMCAE_CAE3 _PWMCAE.Bits.CAE3 -#define PWMCAE_CAE4 _PWMCAE.Bits.CAE4 -#define PWMCAE_CAE5 _PWMCAE.Bits.CAE5 -#define PWMCAE_CAE6 _PWMCAE.Bits.CAE6 -#define PWMCAE_CAE7 _PWMCAE.Bits.CAE7 -#define PWMCAE_CAE _PWMCAE.MergedBits.grpCAE - - -/*** PWMCTL - PWM Control Register; 0x000000E5 ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte :1; - byte PFRZ :1; /* PWM Counters Stop in Freeze Mode */ - byte PSWAI :1; /* PWM Stops in Wait Mode */ - byte CON01 :1; /* Concatenate channels 0 and 1 */ - byte CON23 :1; /* Concatenate channels 2 and 3 */ - byte CON45 :1; /* Concatenate channels 4 and 5 */ - byte CON67 :1; /* Concatenate channels 6 and 7 */ - } Bits; -} PWMCTLSTR; -extern volatile PWMCTLSTR _PWMCTL @(REG_BASE + 0x000000E5); -#define PWMCTL _PWMCTL.Byte -#define PWMCTL_PFRZ _PWMCTL.Bits.PFRZ -#define PWMCTL_PSWAI _PWMCTL.Bits.PSWAI -#define PWMCTL_CON01 _PWMCTL.Bits.CON01 -#define PWMCTL_CON23 _PWMCTL.Bits.CON23 -#define PWMCTL_CON45 _PWMCTL.Bits.CON45 -#define PWMCTL_CON67 _PWMCTL.Bits.CON67 - - -/*** PWMSCLA - PWM Scale A Register; 0x000000E8 ***/ -typedef union { - byte Byte; - struct { - byte BIT0 :1; /* PWM Scale A Bit 0 */ - byte BIT1 :1; /* PWM Scale A Bit 1 */ - byte BIT2 :1; /* PWM Scale A Bit 2 */ - byte BIT3 :1; /* PWM Scale A Bit 3 */ - byte BIT4 :1; /* PWM Scale A Bit 4 */ - byte BIT5 :1; /* PWM Scale A Bit 5 */ - byte BIT6 :1; /* PWM Scale A Bit 6 */ - byte BIT7 :1; /* PWM Scale A Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; -} PWMSCLASTR; -extern volatile PWMSCLASTR _PWMSCLA @(REG_BASE + 0x000000E8); -#define PWMSCLA _PWMSCLA.Byte -#define PWMSCLA_BIT0 _PWMSCLA.Bits.BIT0 -#define PWMSCLA_BIT1 _PWMSCLA.Bits.BIT1 -#define PWMSCLA_BIT2 _PWMSCLA.Bits.BIT2 -#define PWMSCLA_BIT3 _PWMSCLA.Bits.BIT3 -#define PWMSCLA_BIT4 _PWMSCLA.Bits.BIT4 -#define PWMSCLA_BIT5 _PWMSCLA.Bits.BIT5 -#define PWMSCLA_BIT6 _PWMSCLA.Bits.BIT6 -#define PWMSCLA_BIT7 _PWMSCLA.Bits.BIT7 -#define PWMSCLA_BIT _PWMSCLA.MergedBits.grpBIT - - -/*** PWMSCLB - PWM Scale B Register; 0x000000E9 ***/ -typedef union { - byte Byte; - struct { - byte BIT0 :1; /* PWM Scale B Bit 0 */ - byte BIT1 :1; /* PWM Scale B Bit 1 */ - byte BIT2 :1; /* PWM Scale B Bit 2 */ - byte BIT3 :1; /* PWM Scale B Bit 3 */ - byte BIT4 :1; /* PWM Scale B Bit 4 */ - byte BIT5 :1; /* PWM Scale B Bit 5 */ - byte BIT6 :1; /* PWM Scale B Bit 6 */ - byte BIT7 :1; /* PWM Scale B Bit 7 */ - } Bits; - struct { - byte grpBIT :8; - } MergedBits; -} PWMSCLBSTR; -extern volatile PWMSCLBSTR _PWMSCLB @(REG_BASE + 0x000000E9); -#define PWMSCLB _PWMSCLB.Byte -#define PWMSCLB_BIT0 _PWMSCLB.Bits.BIT0 -#define PWMSCLB_BIT1 _PWMSCLB.Bits.BIT1 -#define PWMSCLB_BIT2 _PWMSCLB.Bits.BIT2 -#define PWMSCLB_BIT3 _PWMSCLB.Bits.BIT3 -#define PWMSCLB_BIT4 _PWMSCLB.Bits.BIT4 -#define PWMSCLB_BIT5 _PWMSCLB.Bits.BIT5 -#define PWMSCLB_BIT6 _PWMSCLB.Bits.BIT6 -#define PWMSCLB_BIT7 _PWMSCLB.Bits.BIT7 -#define PWMSCLB_BIT _PWMSCLB.MergedBits.grpBIT - - -/*** PWMSDN - PWM Shutdown Register; 0x000000FE ***/ -typedef union { - byte Byte; - struct { - byte PWM7ENA :1; /* PWM emergency shutdown Enable */ - byte PWM7INL :1; /* PWM shutdown active input level for ch. 7 */ - byte PWM7IN :1; /* PWM channel 7 input status */ - byte :1; - byte PWMLVL :1; /* PWM shutdown output Level */ - byte PWMRSTRT :1; /* PWM Restart */ - byte PWMIE :1; /* PWM Interrupt Enable */ - byte PWMIF :1; /* PWM Interrupt Flag */ - } Bits; -} PWMSDNSTR; -extern volatile PWMSDNSTR _PWMSDN @(REG_BASE + 0x000000FE); -#define PWMSDN _PWMSDN.Byte -#define PWMSDN_PWM7ENA _PWMSDN.Bits.PWM7ENA -#define PWMSDN_PWM7INL _PWMSDN.Bits.PWM7INL -#define PWMSDN_PWM7IN _PWMSDN.Bits.PWM7IN -#define PWMSDN_PWMLVL _PWMSDN.Bits.PWMLVL -#define PWMSDN_PWMRSTRT _PWMSDN.Bits.PWMRSTRT -#define PWMSDN_PWMIE _PWMSDN.Bits.PWMIE -#define PWMSDN_PWMIF _PWMSDN.Bits.PWMIF - - -/*** FCLKDIV - Flash Clock Divider Register; 0x00000100 ***/ -typedef union { - byte Byte; - struct { - byte FDIV0 :1; /* Flash Clock Divider Bit 0 */ - byte FDIV1 :1; /* Flash Clock Divider Bit 1 */ - byte FDIV2 :1; /* Flash Clock Divider Bit 2 */ - byte FDIV3 :1; /* Flash Clock Divider Bit 3 */ - byte FDIV4 :1; /* Flash Clock Divider Bit 4 */ - byte FDIV5 :1; /* Flash Clock Divider Bit 5 */ - byte PRDIV8 :1; /* Enable Prescaler by 8 */ - byte FDIVLD :1; /* Flash Clock Divider Loaded */ - } Bits; - struct { - byte grpFDIV :6; - byte grpPRDIV_8 :1; - byte :1; - } MergedBits; -} FCLKDIVSTR; -extern volatile FCLKDIVSTR _FCLKDIV @(REG_BASE + 0x00000100); -#define FCLKDIV _FCLKDIV.Byte -#define FCLKDIV_FDIV0 _FCLKDIV.Bits.FDIV0 -#define FCLKDIV_FDIV1 _FCLKDIV.Bits.FDIV1 -#define FCLKDIV_FDIV2 _FCLKDIV.Bits.FDIV2 -#define FCLKDIV_FDIV3 _FCLKDIV.Bits.FDIV3 -#define FCLKDIV_FDIV4 _FCLKDIV.Bits.FDIV4 -#define FCLKDIV_FDIV5 _FCLKDIV.Bits.FDIV5 -#define FCLKDIV_PRDIV8 _FCLKDIV.Bits.PRDIV8 -#define FCLKDIV_FDIVLD _FCLKDIV.Bits.FDIVLD -#define FCLKDIV_FDIV _FCLKDIV.MergedBits.grpFDIV - - -/*** FSEC - Flash Security Register; 0x00000101 ***/ -typedef union { - byte Byte; - struct { - byte SEC0 :1; /* Memory security bit 0 */ - byte SEC1 :1; /* Memory security bit 1 */ - byte NV2 :1; /* Non Volatile flag bit 2 */ - byte NV3 :1; /* Non Volatile flag bit 3 */ - byte NV4 :1; /* Non Volatile flag bit 4 */ - byte NV5 :1; /* Non Volatile flag bit 5 */ - byte NV6 :1; /* Non Volatile flag bit 6 */ - byte KEYEN :1; /* Enable backdoor key to security */ - } Bits; - struct { - byte grpSEC :2; - byte grpNV_2 :5; - byte :1; - } MergedBits; -} FSECSTR; -extern volatile FSECSTR _FSEC @(REG_BASE + 0x00000101); -#define FSEC _FSEC.Byte -#define FSEC_SEC0 _FSEC.Bits.SEC0 -#define FSEC_SEC1 _FSEC.Bits.SEC1 -#define FSEC_NV2 _FSEC.Bits.NV2 -#define FSEC_NV3 _FSEC.Bits.NV3 -#define FSEC_NV4 _FSEC.Bits.NV4 -#define FSEC_NV5 _FSEC.Bits.NV5 -#define FSEC_NV6 _FSEC.Bits.NV6 -#define FSEC_KEYEN _FSEC.Bits.KEYEN -#define FSEC_SEC _FSEC.MergedBits.grpSEC -#define FSEC_NV_2 _FSEC.MergedBits.grpNV_2 -#define FSEC_NV FSEC_NV_2 - - -/*** FCNFG - Flash Configuration Register; 0x00000103 ***/ -typedef union { - byte Byte; - struct { - byte BKSEL0 :1; /* Register bank select 0 */ - byte BKSEL1 :1; /* Register bank select 1 */ - byte :1; - byte :1; - byte :1; - byte KEYACC :1; /* Enable Security Key Writing */ - byte CCIE :1; /* Command Complete Interrupt Enable */ - byte CBEIE :1; /* Command Buffers Empty Interrupt Enable */ - } Bits; - struct { - byte grpBKSEL :2; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} FCNFGSTR; -extern volatile FCNFGSTR _FCNFG @(REG_BASE + 0x00000103); -#define FCNFG _FCNFG.Byte -#define FCNFG_BKSEL0 _FCNFG.Bits.BKSEL0 -#define FCNFG_BKSEL1 _FCNFG.Bits.BKSEL1 -#define FCNFG_KEYACC _FCNFG.Bits.KEYACC -#define FCNFG_CCIE _FCNFG.Bits.CCIE -#define FCNFG_CBEIE _FCNFG.Bits.CBEIE -#define FCNFG_BKSEL _FCNFG.MergedBits.grpBKSEL - - -/*** FPROT - Flash Protection Register; 0x00000104 ***/ -typedef union { - byte Byte; - struct { - byte FPLS0 :1; /* Flash Protection Lower Address size 0 */ - byte FPLS1 :1; /* Flash Protection Lower Address size 1 */ - byte FPLDIS :1; /* Flash Protection Lower address range disable */ - byte FPHS0 :1; /* Flash Protection Higher address size 0 */ - byte FPHS1 :1; /* Flash Protection Higher address size 1 */ - byte FPHDIS :1; /* Flash Protection Higher address range disable */ - byte NV6 :1; /* Non Volatile Flag Bit */ - byte FPOPEN :1; /* Opens the flash block or subsections of it for program or erase */ - } Bits; - struct { - byte grpFPLS :2; - byte :1; - byte grpFPHS :2; - byte :1; - byte grpNV_6 :1; - byte :1; - } MergedBits; -} FPROTSTR; -extern volatile FPROTSTR _FPROT @(REG_BASE + 0x00000104); -#define FPROT _FPROT.Byte -#define FPROT_FPLS0 _FPROT.Bits.FPLS0 -#define FPROT_FPLS1 _FPROT.Bits.FPLS1 -#define FPROT_FPLDIS _FPROT.Bits.FPLDIS -#define FPROT_FPHS0 _FPROT.Bits.FPHS0 -#define FPROT_FPHS1 _FPROT.Bits.FPHS1 -#define FPROT_FPHDIS _FPROT.Bits.FPHDIS -#define FPROT_NV6 _FPROT.Bits.NV6 -#define FPROT_FPOPEN _FPROT.Bits.FPOPEN -#define FPROT_FPLS _FPROT.MergedBits.grpFPLS -#define FPROT_FPHS _FPROT.MergedBits.grpFPHS - - -/*** FSTAT - Flash Status Register; 0x00000105 ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte :1; - byte BLANK :1; /* Blank Verify Flag */ - byte :1; - byte ACCERR :1; /* Access error */ - byte PVIOL :1; /* Protection violation */ - byte CCIF :1; /* Command Complete Interrupt Flag */ - byte CBEIF :1; /* Command Buffers Empty Interrupt Flag */ - } Bits; -} FSTATSTR; -extern volatile FSTATSTR _FSTAT @(REG_BASE + 0x00000105); -#define FSTAT _FSTAT.Byte -#define FSTAT_BLANK _FSTAT.Bits.BLANK -#define FSTAT_ACCERR _FSTAT.Bits.ACCERR -#define FSTAT_PVIOL _FSTAT.Bits.PVIOL -#define FSTAT_CCIF _FSTAT.Bits.CCIF -#define FSTAT_CBEIF _FSTAT.Bits.CBEIF - - -/*** FCMD - Flash Command Buffer and Register; 0x00000106 ***/ -typedef union { - byte Byte; - struct { - byte CMDB0 :1; /* NVM User Mode Command Bit 0 */ - byte :1; - byte CMDB2 :1; /* NVM User Mode Command Bit 2 */ - byte :1; - byte :1; - byte CMDB5 :1; /* NVM User Mode Command Bit 5 */ - byte CMDB6 :1; /* NVM User Mode Command Bit 6 */ - byte :1; - } Bits; - struct { - byte grpCMDB :1; - byte :1; - byte grpCMDB_2 :1; - byte :1; - byte :1; - byte grpCMDB_5 :2; - byte :1; - } MergedBits; -} FCMDSTR; -extern volatile FCMDSTR _FCMD @(REG_BASE + 0x00000106); -#define FCMD _FCMD.Byte -#define FCMD_CMDB0 _FCMD.Bits.CMDB0 -#define FCMD_CMDB2 _FCMD.Bits.CMDB2 -#define FCMD_CMDB5 _FCMD.Bits.CMDB5 -#define FCMD_CMDB6 _FCMD.Bits.CMDB6 -#define FCMD_CMDB_5 _FCMD.MergedBits.grpCMDB_5 -#define FCMD_CMDB FCMD_CMDB_5 - - -/*** CANCTL0 - MSCAN Control 0 Register; 0x00000140 ***/ -typedef union { - byte Byte; - struct { - byte INITRQ :1; /* Initialization Mode Request */ - byte SLPRQ :1; /* Sleep Mode Request */ - byte WUPE :1; /* Wake-Up Enable */ - byte TIME :1; /* Timer Enable */ - byte SYNCH :1; /* Synchronized Status */ - byte CSWAI :1; /* CAN Stops in Wait Mode */ - byte RXACT :1; /* Receiver Active Status */ - byte RXFRM :1; /* Received Frame Flag */ - } Bits; -} CANCTL0STR; -extern volatile CANCTL0STR _CANCTL0 @(REG_BASE + 0x00000140); -#define CANCTL0 _CANCTL0.Byte -#define CANCTL0_INITRQ _CANCTL0.Bits.INITRQ -#define CANCTL0_SLPRQ _CANCTL0.Bits.SLPRQ -#define CANCTL0_WUPE _CANCTL0.Bits.WUPE -#define CANCTL0_TIME _CANCTL0.Bits.TIME -#define CANCTL0_SYNCH _CANCTL0.Bits.SYNCH -#define CANCTL0_CSWAI _CANCTL0.Bits.CSWAI -#define CANCTL0_RXACT _CANCTL0.Bits.RXACT -#define CANCTL0_RXFRM _CANCTL0.Bits.RXFRM - - -/*** CANCTL1 - MSCAN Control 1 Register; 0x00000141 ***/ -typedef union { - byte Byte; - struct { - byte INITAK :1; /* Initialization Mode Acknowledge */ - byte SLPAK :1; /* Sleep Mode Acknowledge */ - byte WUPM :1; /* Wake-Up Mode */ - byte :1; - byte LISTEN :1; /* Listen Only Mode */ - byte LOOPB :1; /* Loop Back Self Test Mode */ - byte CLKSRC :1; /* MSCAN Clock Source */ - byte CANE :1; /* MSCAN Enable */ - } Bits; -} CANCTL1STR; -extern volatile CANCTL1STR _CANCTL1 @(REG_BASE + 0x00000141); -#define CANCTL1 _CANCTL1.Byte -#define CANCTL1_INITAK _CANCTL1.Bits.INITAK -#define CANCTL1_SLPAK _CANCTL1.Bits.SLPAK -#define CANCTL1_WUPM _CANCTL1.Bits.WUPM -#define CANCTL1_LISTEN _CANCTL1.Bits.LISTEN -#define CANCTL1_LOOPB _CANCTL1.Bits.LOOPB -#define CANCTL1_CLKSRC _CANCTL1.Bits.CLKSRC -#define CANCTL1_CANE _CANCTL1.Bits.CANE - - -/*** CANBTR0 - MSCAN Bus Timing Register 0; 0x00000142 ***/ -typedef union { - byte Byte; - struct { - byte BRP0 :1; /* Baud Rate Prescaler 0 */ - byte BRP1 :1; /* Baud Rate Prescaler 1 */ - byte BRP2 :1; /* Baud Rate Prescaler 2 */ - byte BRP3 :1; /* Baud Rate Prescaler 3 */ - byte BRP4 :1; /* Baud Rate Prescaler 4 */ - byte BRP5 :1; /* Baud Rate Prescaler 5 */ - byte SJW0 :1; /* Synchronization Jump Width 0 */ - byte SJW1 :1; /* Synchronization Jump Width 1 */ - } Bits; - struct { - byte grpBRP :6; - byte grpSJW :2; - } MergedBits; -} CANBTR0STR; -extern volatile CANBTR0STR _CANBTR0 @(REG_BASE + 0x00000142); -#define CANBTR0 _CANBTR0.Byte -#define CANBTR0_BRP0 _CANBTR0.Bits.BRP0 -#define CANBTR0_BRP1 _CANBTR0.Bits.BRP1 -#define CANBTR0_BRP2 _CANBTR0.Bits.BRP2 -#define CANBTR0_BRP3 _CANBTR0.Bits.BRP3 -#define CANBTR0_BRP4 _CANBTR0.Bits.BRP4 -#define CANBTR0_BRP5 _CANBTR0.Bits.BRP5 -#define CANBTR0_SJW0 _CANBTR0.Bits.SJW0 -#define CANBTR0_SJW1 _CANBTR0.Bits.SJW1 -#define CANBTR0_BRP _CANBTR0.MergedBits.grpBRP -#define CANBTR0_SJW _CANBTR0.MergedBits.grpSJW - - -/*** CANBTR1 - MSCAN Bus Timing Register 1; 0x00000143 ***/ -typedef union { - byte Byte; - struct { - byte TSEG10 :1; /* Time Segment 1 */ - byte TSEG11 :1; /* Time Segment 1 */ - byte TSEG12 :1; /* Time Segment 1 */ - byte TSEG13 :1; /* Time Segment 1 */ - byte TSEG20 :1; /* Time Segment 2 */ - byte TSEG21 :1; /* Time Segment 2 */ - byte TSEG22 :1; /* Time Segment 2 */ - byte SAMP :1; /* Sampling */ - } Bits; - struct { - byte grpTSEG_10 :4; - byte grpTSEG_20 :3; - byte :1; - } MergedBits; -} CANBTR1STR; -extern volatile CANBTR1STR _CANBTR1 @(REG_BASE + 0x00000143); -#define CANBTR1 _CANBTR1.Byte -#define CANBTR1_TSEG10 _CANBTR1.Bits.TSEG10 -#define CANBTR1_TSEG11 _CANBTR1.Bits.TSEG11 -#define CANBTR1_TSEG12 _CANBTR1.Bits.TSEG12 -#define CANBTR1_TSEG13 _CANBTR1.Bits.TSEG13 -#define CANBTR1_TSEG20 _CANBTR1.Bits.TSEG20 -#define CANBTR1_TSEG21 _CANBTR1.Bits.TSEG21 -#define CANBTR1_TSEG22 _CANBTR1.Bits.TSEG22 -#define CANBTR1_SAMP _CANBTR1.Bits.SAMP -#define CANBTR1_TSEG_10 _CANBTR1.MergedBits.grpTSEG_10 -#define CANBTR1_TSEG_20 _CANBTR1.MergedBits.grpTSEG_20 -#define CANBTR1_TSEG CANBTR1_TSEG_10 - - -/*** CANRFLG - MSCAN Receiver Flag Register; 0x00000144 ***/ -typedef union { - byte Byte; - struct { - byte RXF :1; /* Receive Buffer Full */ - byte OVRIF :1; /* Overrun Interrupt Flag */ - byte TSTAT0 :1; /* Transmitter Status Bit 0 */ - byte TSTAT1 :1; /* Transmitter Status Bit 1 */ - byte RSTAT0 :1; /* Receiver Status Bit 0 */ - byte RSTAT1 :1; /* Receiver Status Bit 1 */ - byte CSCIF :1; /* CAN Status Change Interrupt Flag */ - byte WUPIF :1; /* Wake-up Interrupt Flag */ - } Bits; - struct { - byte :1; - byte :1; - byte grpTSTAT :2; - byte grpRSTAT :2; - byte :1; - byte :1; - } MergedBits; -} CANRFLGSTR; -extern volatile CANRFLGSTR _CANRFLG @(REG_BASE + 0x00000144); -#define CANRFLG _CANRFLG.Byte -#define CANRFLG_RXF _CANRFLG.Bits.RXF -#define CANRFLG_OVRIF _CANRFLG.Bits.OVRIF -#define CANRFLG_TSTAT0 _CANRFLG.Bits.TSTAT0 -#define CANRFLG_TSTAT1 _CANRFLG.Bits.TSTAT1 -#define CANRFLG_RSTAT0 _CANRFLG.Bits.RSTAT0 -#define CANRFLG_RSTAT1 _CANRFLG.Bits.RSTAT1 -#define CANRFLG_CSCIF _CANRFLG.Bits.CSCIF -#define CANRFLG_WUPIF _CANRFLG.Bits.WUPIF -#define CANRFLG_TSTAT _CANRFLG.MergedBits.grpTSTAT -#define CANRFLG_RSTAT _CANRFLG.MergedBits.grpRSTAT - - -/*** CANRIER - MSCAN Receiver Interrupt Enable Register; 0x00000145 ***/ -typedef union { - byte Byte; - struct { - byte RXFIE :1; /* Receiver Full Interrupt Enable */ - byte OVRIE :1; /* Overrun Interrupt Enable */ - byte TSTATE0 :1; /* Transmitter Status Change Enable 0 */ - byte TSTATE1 :1; /* Transmitter Status Change Enable 1 */ - byte RSTATE0 :1; /* Receiver Status Change Enable 0 */ - byte RSTATE1 :1; /* Receiver Status Change Enable 1 */ - byte CSCIE :1; /* CAN Status Change Interrupt Enable */ - byte WUPIE :1; /* Wake-up Interrupt Enable */ - } Bits; - struct { - byte :1; - byte :1; - byte grpTSTATE :2; - byte grpRSTATE :2; - byte :1; - byte :1; - } MergedBits; -} CANRIERSTR; -extern volatile CANRIERSTR _CANRIER @(REG_BASE + 0x00000145); -#define CANRIER _CANRIER.Byte -#define CANRIER_RXFIE _CANRIER.Bits.RXFIE -#define CANRIER_OVRIE _CANRIER.Bits.OVRIE -#define CANRIER_TSTATE0 _CANRIER.Bits.TSTATE0 -#define CANRIER_TSTATE1 _CANRIER.Bits.TSTATE1 -#define CANRIER_RSTATE0 _CANRIER.Bits.RSTATE0 -#define CANRIER_RSTATE1 _CANRIER.Bits.RSTATE1 -#define CANRIER_CSCIE _CANRIER.Bits.CSCIE -#define CANRIER_WUPIE _CANRIER.Bits.WUPIE -#define CANRIER_TSTATE _CANRIER.MergedBits.grpTSTATE -#define CANRIER_RSTATE _CANRIER.MergedBits.grpRSTATE - - -/*** CANTFLG - MSCAN Transmitter Flag Register; 0x00000146 ***/ -typedef union { - byte Byte; - struct { - byte TXE0 :1; /* Transmitter Buffer Empty 0 */ - byte TXE1 :1; /* Transmitter Buffer Empty 1 */ - byte TXE2 :1; /* Transmitter Buffer Empty 2 */ - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpTXE :3; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} CANTFLGSTR; -extern volatile CANTFLGSTR _CANTFLG @(REG_BASE + 0x00000146); -#define CANTFLG _CANTFLG.Byte -#define CANTFLG_TXE0 _CANTFLG.Bits.TXE0 -#define CANTFLG_TXE1 _CANTFLG.Bits.TXE1 -#define CANTFLG_TXE2 _CANTFLG.Bits.TXE2 -#define CANTFLG_TXE _CANTFLG.MergedBits.grpTXE - - -/*** CANTIER - MSCAN Transmitter Interrupt Enable Register; 0x00000147 ***/ -typedef union { - byte Byte; - struct { - byte TXEIE0 :1; /* Transmitter Empty Interrupt Enable 0 */ - byte TXEIE1 :1; /* Transmitter Empty Interrupt Enable 1 */ - byte TXEIE2 :1; /* Transmitter Empty Interrupt Enable 2 */ - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpTXEIE :3; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} CANTIERSTR; -extern volatile CANTIERSTR _CANTIER @(REG_BASE + 0x00000147); -#define CANTIER _CANTIER.Byte -#define CANTIER_TXEIE0 _CANTIER.Bits.TXEIE0 -#define CANTIER_TXEIE1 _CANTIER.Bits.TXEIE1 -#define CANTIER_TXEIE2 _CANTIER.Bits.TXEIE2 -#define CANTIER_TXEIE _CANTIER.MergedBits.grpTXEIE - - -/*** CANTARQ - MSCAN Transmitter Message Abort Request; 0x00000148 ***/ -typedef union { - byte Byte; - struct { - byte ABTRQ0 :1; /* Abort Request 0 */ - byte ABTRQ1 :1; /* Abort Request 1 */ - byte ABTRQ2 :1; /* Abort Request 2 */ - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpABTRQ :3; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} CANTARQSTR; -extern volatile CANTARQSTR _CANTARQ @(REG_BASE + 0x00000148); -#define CANTARQ _CANTARQ.Byte -#define CANTARQ_ABTRQ0 _CANTARQ.Bits.ABTRQ0 -#define CANTARQ_ABTRQ1 _CANTARQ.Bits.ABTRQ1 -#define CANTARQ_ABTRQ2 _CANTARQ.Bits.ABTRQ2 -#define CANTARQ_ABTRQ _CANTARQ.MergedBits.grpABTRQ - - -/*** CANTAAK - MSCAN Transmitter Message Abort Control; 0x00000149 ***/ -typedef union { - byte Byte; - struct { - byte ABTAK0 :1; /* Abort Acknowledge 0 */ - byte ABTAK1 :1; /* Abort Acknowledge 1 */ - byte ABTAK2 :1; /* Abort Acknowledge 2 */ - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpABTAK :3; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} CANTAAKSTR; -extern volatile CANTAAKSTR _CANTAAK @(REG_BASE + 0x00000149); -#define CANTAAK _CANTAAK.Byte -#define CANTAAK_ABTAK0 _CANTAAK.Bits.ABTAK0 -#define CANTAAK_ABTAK1 _CANTAAK.Bits.ABTAK1 -#define CANTAAK_ABTAK2 _CANTAAK.Bits.ABTAK2 -#define CANTAAK_ABTAK _CANTAAK.MergedBits.grpABTAK - - -/*** CANTBSEL - MSCAN Transmit Buffer Selection; 0x0000014A ***/ -typedef union { - byte Byte; - struct { - byte TX0 :1; /* Transmit Buffer Select 0 */ - byte TX1 :1; /* Transmit Buffer Select 1 */ - byte TX2 :1; /* Transmit Buffer Select 2 */ - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpTX :3; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} CANTBSELSTR; -extern volatile CANTBSELSTR _CANTBSEL @(REG_BASE + 0x0000014A); -#define CANTBSEL _CANTBSEL.Byte -#define CANTBSEL_TX0 _CANTBSEL.Bits.TX0 -#define CANTBSEL_TX1 _CANTBSEL.Bits.TX1 -#define CANTBSEL_TX2 _CANTBSEL.Bits.TX2 -#define CANTBSEL_TX _CANTBSEL.MergedBits.grpTX - - -/*** CANIDAC - MSCAN Identifier Acceptance Control Register; 0x0000014B ***/ -typedef union { - byte Byte; - struct { - byte IDHIT0 :1; /* Identifier Acceptance Hit Indicator 0 */ - byte IDHIT1 :1; /* Identifier Acceptance Hit Indicator 1 */ - byte IDHIT2 :1; /* Identifier Acceptance Hit Indicator 2 */ - byte :1; - byte IDAM0 :1; /* Identifier Acceptance Mode 0 */ - byte IDAM1 :1; /* Identifier Acceptance Mode 1 */ - byte :1; - byte :1; - } Bits; - struct { - byte grpIDHIT :3; - byte :1; - byte grpIDAM :2; - byte :1; - byte :1; - } MergedBits; -} CANIDACSTR; -extern volatile CANIDACSTR _CANIDAC @(REG_BASE + 0x0000014B); -#define CANIDAC _CANIDAC.Byte -#define CANIDAC_IDHIT0 _CANIDAC.Bits.IDHIT0 -#define CANIDAC_IDHIT1 _CANIDAC.Bits.IDHIT1 -#define CANIDAC_IDHIT2 _CANIDAC.Bits.IDHIT2 -#define CANIDAC_IDAM0 _CANIDAC.Bits.IDAM0 -#define CANIDAC_IDAM1 _CANIDAC.Bits.IDAM1 -#define CANIDAC_IDHIT _CANIDAC.MergedBits.grpIDHIT -#define CANIDAC_IDAM _CANIDAC.MergedBits.grpIDAM - - -/*** CANRXERR - MSCAN Receive Error Counter Register; 0x0000014E ***/ -typedef union { - byte Byte; - struct { - byte RXERR0 :1; /* Bit 0 */ - byte RXERR1 :1; /* Bit 1 */ - byte RXERR2 :1; /* Bit 2 */ - byte RXERR3 :1; /* Bit 3 */ - byte RXERR4 :1; /* Bit 4 */ - byte RXERR5 :1; /* Bit 5 */ - byte RXERR6 :1; /* Bit 6 */ - byte RXERR7 :1; /* Bit 7 */ - } Bits; - struct { - byte grpRXERR :8; - } MergedBits; -} CANRXERRSTR; -extern volatile CANRXERRSTR _CANRXERR @(REG_BASE + 0x0000014E); -#define CANRXERR _CANRXERR.Byte -#define CANRXERR_RXERR0 _CANRXERR.Bits.RXERR0 -#define CANRXERR_RXERR1 _CANRXERR.Bits.RXERR1 -#define CANRXERR_RXERR2 _CANRXERR.Bits.RXERR2 -#define CANRXERR_RXERR3 _CANRXERR.Bits.RXERR3 -#define CANRXERR_RXERR4 _CANRXERR.Bits.RXERR4 -#define CANRXERR_RXERR5 _CANRXERR.Bits.RXERR5 -#define CANRXERR_RXERR6 _CANRXERR.Bits.RXERR6 -#define CANRXERR_RXERR7 _CANRXERR.Bits.RXERR7 -#define CANRXERR_RXERR _CANRXERR.MergedBits.grpRXERR - - -/*** CANTXERR - MSCAN Transmit Error Counter Register; 0x0000014F ***/ -typedef union { - byte Byte; - struct { - byte TXERR0 :1; /* Bit 0 */ - byte TXERR1 :1; /* Bit 1 */ - byte TXERR2 :1; /* Bit 2 */ - byte TXERR3 :1; /* Bit 3 */ - byte TXERR4 :1; /* Bit 4 */ - byte TXERR5 :1; /* Bit 5 */ - byte TXERR6 :1; /* Bit 6 */ - byte TXERR7 :1; /* Bit 7 */ - } Bits; - struct { - byte grpTXERR :8; - } MergedBits; -} CANTXERRSTR; -extern volatile CANTXERRSTR _CANTXERR @(REG_BASE + 0x0000014F); -#define CANTXERR _CANTXERR.Byte -#define CANTXERR_TXERR0 _CANTXERR.Bits.TXERR0 -#define CANTXERR_TXERR1 _CANTXERR.Bits.TXERR1 -#define CANTXERR_TXERR2 _CANTXERR.Bits.TXERR2 -#define CANTXERR_TXERR3 _CANTXERR.Bits.TXERR3 -#define CANTXERR_TXERR4 _CANTXERR.Bits.TXERR4 -#define CANTXERR_TXERR5 _CANTXERR.Bits.TXERR5 -#define CANTXERR_TXERR6 _CANTXERR.Bits.TXERR6 -#define CANTXERR_TXERR7 _CANTXERR.Bits.TXERR7 -#define CANTXERR_TXERR _CANTXERR.MergedBits.grpTXERR - - -/*** CANIDAR0 - MSCAN Identifier Acceptance Register 0; 0x00000150 ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CANIDAR0STR; -extern volatile CANIDAR0STR _CANIDAR0 @(REG_BASE + 0x00000150); -#define CANIDAR0 _CANIDAR0.Byte -#define CANIDAR0_AC0 _CANIDAR0.Bits.AC0 -#define CANIDAR0_AC1 _CANIDAR0.Bits.AC1 -#define CANIDAR0_AC2 _CANIDAR0.Bits.AC2 -#define CANIDAR0_AC3 _CANIDAR0.Bits.AC3 -#define CANIDAR0_AC4 _CANIDAR0.Bits.AC4 -#define CANIDAR0_AC5 _CANIDAR0.Bits.AC5 -#define CANIDAR0_AC6 _CANIDAR0.Bits.AC6 -#define CANIDAR0_AC7 _CANIDAR0.Bits.AC7 -#define CANIDAR0_AC _CANIDAR0.MergedBits.grpAC - - -/*** CANIDAR1 - MSCAN Identifier Acceptance Register 1; 0x00000151 ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CANIDAR1STR; -extern volatile CANIDAR1STR _CANIDAR1 @(REG_BASE + 0x00000151); -#define CANIDAR1 _CANIDAR1.Byte -#define CANIDAR1_AC0 _CANIDAR1.Bits.AC0 -#define CANIDAR1_AC1 _CANIDAR1.Bits.AC1 -#define CANIDAR1_AC2 _CANIDAR1.Bits.AC2 -#define CANIDAR1_AC3 _CANIDAR1.Bits.AC3 -#define CANIDAR1_AC4 _CANIDAR1.Bits.AC4 -#define CANIDAR1_AC5 _CANIDAR1.Bits.AC5 -#define CANIDAR1_AC6 _CANIDAR1.Bits.AC6 -#define CANIDAR1_AC7 _CANIDAR1.Bits.AC7 -#define CANIDAR1_AC _CANIDAR1.MergedBits.grpAC - - -/*** CANIDAR2 - MSCAN Identifier Acceptance Register 2; 0x00000152 ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CANIDAR2STR; -extern volatile CANIDAR2STR _CANIDAR2 @(REG_BASE + 0x00000152); -#define CANIDAR2 _CANIDAR2.Byte -#define CANIDAR2_AC0 _CANIDAR2.Bits.AC0 -#define CANIDAR2_AC1 _CANIDAR2.Bits.AC1 -#define CANIDAR2_AC2 _CANIDAR2.Bits.AC2 -#define CANIDAR2_AC3 _CANIDAR2.Bits.AC3 -#define CANIDAR2_AC4 _CANIDAR2.Bits.AC4 -#define CANIDAR2_AC5 _CANIDAR2.Bits.AC5 -#define CANIDAR2_AC6 _CANIDAR2.Bits.AC6 -#define CANIDAR2_AC7 _CANIDAR2.Bits.AC7 -#define CANIDAR2_AC _CANIDAR2.MergedBits.grpAC - - -/*** CANIDAR3 - MSCAN Identifier Acceptance Register 3; 0x00000153 ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CANIDAR3STR; -extern volatile CANIDAR3STR _CANIDAR3 @(REG_BASE + 0x00000153); -#define CANIDAR3 _CANIDAR3.Byte -#define CANIDAR3_AC0 _CANIDAR3.Bits.AC0 -#define CANIDAR3_AC1 _CANIDAR3.Bits.AC1 -#define CANIDAR3_AC2 _CANIDAR3.Bits.AC2 -#define CANIDAR3_AC3 _CANIDAR3.Bits.AC3 -#define CANIDAR3_AC4 _CANIDAR3.Bits.AC4 -#define CANIDAR3_AC5 _CANIDAR3.Bits.AC5 -#define CANIDAR3_AC6 _CANIDAR3.Bits.AC6 -#define CANIDAR3_AC7 _CANIDAR3.Bits.AC7 -#define CANIDAR3_AC _CANIDAR3.MergedBits.grpAC - - -/*** CANIDMR0 - MSCAN Identifier Mask Register 0; 0x00000154 ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CANIDMR0STR; -extern volatile CANIDMR0STR _CANIDMR0 @(REG_BASE + 0x00000154); -#define CANIDMR0 _CANIDMR0.Byte -#define CANIDMR0_AM0 _CANIDMR0.Bits.AM0 -#define CANIDMR0_AM1 _CANIDMR0.Bits.AM1 -#define CANIDMR0_AM2 _CANIDMR0.Bits.AM2 -#define CANIDMR0_AM3 _CANIDMR0.Bits.AM3 -#define CANIDMR0_AM4 _CANIDMR0.Bits.AM4 -#define CANIDMR0_AM5 _CANIDMR0.Bits.AM5 -#define CANIDMR0_AM6 _CANIDMR0.Bits.AM6 -#define CANIDMR0_AM7 _CANIDMR0.Bits.AM7 -#define CANIDMR0_AM _CANIDMR0.MergedBits.grpAM - - -/*** CANIDMR1 - MSCAN Identifier Mask Register 1; 0x00000155 ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CANIDMR1STR; -extern volatile CANIDMR1STR _CANIDMR1 @(REG_BASE + 0x00000155); -#define CANIDMR1 _CANIDMR1.Byte -#define CANIDMR1_AM0 _CANIDMR1.Bits.AM0 -#define CANIDMR1_AM1 _CANIDMR1.Bits.AM1 -#define CANIDMR1_AM2 _CANIDMR1.Bits.AM2 -#define CANIDMR1_AM3 _CANIDMR1.Bits.AM3 -#define CANIDMR1_AM4 _CANIDMR1.Bits.AM4 -#define CANIDMR1_AM5 _CANIDMR1.Bits.AM5 -#define CANIDMR1_AM6 _CANIDMR1.Bits.AM6 -#define CANIDMR1_AM7 _CANIDMR1.Bits.AM7 -#define CANIDMR1_AM _CANIDMR1.MergedBits.grpAM - - -/*** CANIDMR2 - MSCAN Identifier Mask Register 2; 0x00000156 ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CANIDMR2STR; -extern volatile CANIDMR2STR _CANIDMR2 @(REG_BASE + 0x00000156); -#define CANIDMR2 _CANIDMR2.Byte -#define CANIDMR2_AM0 _CANIDMR2.Bits.AM0 -#define CANIDMR2_AM1 _CANIDMR2.Bits.AM1 -#define CANIDMR2_AM2 _CANIDMR2.Bits.AM2 -#define CANIDMR2_AM3 _CANIDMR2.Bits.AM3 -#define CANIDMR2_AM4 _CANIDMR2.Bits.AM4 -#define CANIDMR2_AM5 _CANIDMR2.Bits.AM5 -#define CANIDMR2_AM6 _CANIDMR2.Bits.AM6 -#define CANIDMR2_AM7 _CANIDMR2.Bits.AM7 -#define CANIDMR2_AM _CANIDMR2.MergedBits.grpAM - - -/*** CANIDMR3 - MSCAN Identifier Mask Register 3; 0x00000157 ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CANIDMR3STR; -extern volatile CANIDMR3STR _CANIDMR3 @(REG_BASE + 0x00000157); -#define CANIDMR3 _CANIDMR3.Byte -#define CANIDMR3_AM0 _CANIDMR3.Bits.AM0 -#define CANIDMR3_AM1 _CANIDMR3.Bits.AM1 -#define CANIDMR3_AM2 _CANIDMR3.Bits.AM2 -#define CANIDMR3_AM3 _CANIDMR3.Bits.AM3 -#define CANIDMR3_AM4 _CANIDMR3.Bits.AM4 -#define CANIDMR3_AM5 _CANIDMR3.Bits.AM5 -#define CANIDMR3_AM6 _CANIDMR3.Bits.AM6 -#define CANIDMR3_AM7 _CANIDMR3.Bits.AM7 -#define CANIDMR3_AM _CANIDMR3.MergedBits.grpAM - - -/*** CANIDAR4 - MSCAN Identifier Acceptance Register 4; 0x00000158 ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CANIDAR4STR; -extern volatile CANIDAR4STR _CANIDAR4 @(REG_BASE + 0x00000158); -#define CANIDAR4 _CANIDAR4.Byte -#define CANIDAR4_AC0 _CANIDAR4.Bits.AC0 -#define CANIDAR4_AC1 _CANIDAR4.Bits.AC1 -#define CANIDAR4_AC2 _CANIDAR4.Bits.AC2 -#define CANIDAR4_AC3 _CANIDAR4.Bits.AC3 -#define CANIDAR4_AC4 _CANIDAR4.Bits.AC4 -#define CANIDAR4_AC5 _CANIDAR4.Bits.AC5 -#define CANIDAR4_AC6 _CANIDAR4.Bits.AC6 -#define CANIDAR4_AC7 _CANIDAR4.Bits.AC7 -#define CANIDAR4_AC _CANIDAR4.MergedBits.grpAC - - -/*** CANIDAR5 - MSCAN Identifier Acceptance Register 5; 0x00000159 ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CANIDAR5STR; -extern volatile CANIDAR5STR _CANIDAR5 @(REG_BASE + 0x00000159); -#define CANIDAR5 _CANIDAR5.Byte -#define CANIDAR5_AC0 _CANIDAR5.Bits.AC0 -#define CANIDAR5_AC1 _CANIDAR5.Bits.AC1 -#define CANIDAR5_AC2 _CANIDAR5.Bits.AC2 -#define CANIDAR5_AC3 _CANIDAR5.Bits.AC3 -#define CANIDAR5_AC4 _CANIDAR5.Bits.AC4 -#define CANIDAR5_AC5 _CANIDAR5.Bits.AC5 -#define CANIDAR5_AC6 _CANIDAR5.Bits.AC6 -#define CANIDAR5_AC7 _CANIDAR5.Bits.AC7 -#define CANIDAR5_AC _CANIDAR5.MergedBits.grpAC - - -/*** CANIDAR6 - MSCAN Identifier Acceptance Register 6; 0x0000015A ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CANIDAR6STR; -extern volatile CANIDAR6STR _CANIDAR6 @(REG_BASE + 0x0000015A); -#define CANIDAR6 _CANIDAR6.Byte -#define CANIDAR6_AC0 _CANIDAR6.Bits.AC0 -#define CANIDAR6_AC1 _CANIDAR6.Bits.AC1 -#define CANIDAR6_AC2 _CANIDAR6.Bits.AC2 -#define CANIDAR6_AC3 _CANIDAR6.Bits.AC3 -#define CANIDAR6_AC4 _CANIDAR6.Bits.AC4 -#define CANIDAR6_AC5 _CANIDAR6.Bits.AC5 -#define CANIDAR6_AC6 _CANIDAR6.Bits.AC6 -#define CANIDAR6_AC7 _CANIDAR6.Bits.AC7 -#define CANIDAR6_AC _CANIDAR6.MergedBits.grpAC - - -/*** CANIDAR7 - MSCAN Identifier Acceptance Register 7; 0x0000015B ***/ -typedef union { - byte Byte; - struct { - byte AC0 :1; /* Acceptance Code Bit 0 */ - byte AC1 :1; /* Acceptance Code Bit 1 */ - byte AC2 :1; /* Acceptance Code Bit 2 */ - byte AC3 :1; /* Acceptance Code Bit 3 */ - byte AC4 :1; /* Acceptance Code Bit 4 */ - byte AC5 :1; /* Acceptance Code Bit 5 */ - byte AC6 :1; /* Acceptance Code Bit 6 */ - byte AC7 :1; /* Acceptance Code Bit 7 */ - } Bits; - struct { - byte grpAC :8; - } MergedBits; -} CANIDAR7STR; -extern volatile CANIDAR7STR _CANIDAR7 @(REG_BASE + 0x0000015B); -#define CANIDAR7 _CANIDAR7.Byte -#define CANIDAR7_AC0 _CANIDAR7.Bits.AC0 -#define CANIDAR7_AC1 _CANIDAR7.Bits.AC1 -#define CANIDAR7_AC2 _CANIDAR7.Bits.AC2 -#define CANIDAR7_AC3 _CANIDAR7.Bits.AC3 -#define CANIDAR7_AC4 _CANIDAR7.Bits.AC4 -#define CANIDAR7_AC5 _CANIDAR7.Bits.AC5 -#define CANIDAR7_AC6 _CANIDAR7.Bits.AC6 -#define CANIDAR7_AC7 _CANIDAR7.Bits.AC7 -#define CANIDAR7_AC _CANIDAR7.MergedBits.grpAC - - -/*** CANIDMR4 - MSCAN Identifier Mask Register 4; 0x0000015C ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CANIDMR4STR; -extern volatile CANIDMR4STR _CANIDMR4 @(REG_BASE + 0x0000015C); -#define CANIDMR4 _CANIDMR4.Byte -#define CANIDMR4_AM0 _CANIDMR4.Bits.AM0 -#define CANIDMR4_AM1 _CANIDMR4.Bits.AM1 -#define CANIDMR4_AM2 _CANIDMR4.Bits.AM2 -#define CANIDMR4_AM3 _CANIDMR4.Bits.AM3 -#define CANIDMR4_AM4 _CANIDMR4.Bits.AM4 -#define CANIDMR4_AM5 _CANIDMR4.Bits.AM5 -#define CANIDMR4_AM6 _CANIDMR4.Bits.AM6 -#define CANIDMR4_AM7 _CANIDMR4.Bits.AM7 -#define CANIDMR4_AM _CANIDMR4.MergedBits.grpAM - - -/*** CANIDMR5 - MSCAN Identifier Mask Register 5; 0x0000015D ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CANIDMR5STR; -extern volatile CANIDMR5STR _CANIDMR5 @(REG_BASE + 0x0000015D); -#define CANIDMR5 _CANIDMR5.Byte -#define CANIDMR5_AM0 _CANIDMR5.Bits.AM0 -#define CANIDMR5_AM1 _CANIDMR5.Bits.AM1 -#define CANIDMR5_AM2 _CANIDMR5.Bits.AM2 -#define CANIDMR5_AM3 _CANIDMR5.Bits.AM3 -#define CANIDMR5_AM4 _CANIDMR5.Bits.AM4 -#define CANIDMR5_AM5 _CANIDMR5.Bits.AM5 -#define CANIDMR5_AM6 _CANIDMR5.Bits.AM6 -#define CANIDMR5_AM7 _CANIDMR5.Bits.AM7 -#define CANIDMR5_AM _CANIDMR5.MergedBits.grpAM - - -/*** CANIDMR6 - MSCAN Identifier Mask Register 6; 0x0000015E ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CANIDMR6STR; -extern volatile CANIDMR6STR _CANIDMR6 @(REG_BASE + 0x0000015E); -#define CANIDMR6 _CANIDMR6.Byte -#define CANIDMR6_AM0 _CANIDMR6.Bits.AM0 -#define CANIDMR6_AM1 _CANIDMR6.Bits.AM1 -#define CANIDMR6_AM2 _CANIDMR6.Bits.AM2 -#define CANIDMR6_AM3 _CANIDMR6.Bits.AM3 -#define CANIDMR6_AM4 _CANIDMR6.Bits.AM4 -#define CANIDMR6_AM5 _CANIDMR6.Bits.AM5 -#define CANIDMR6_AM6 _CANIDMR6.Bits.AM6 -#define CANIDMR6_AM7 _CANIDMR6.Bits.AM7 -#define CANIDMR6_AM _CANIDMR6.MergedBits.grpAM - - -/*** CANIDMR7 - MSCAN Identifier Mask Register 7; 0x0000015F ***/ -typedef union { - byte Byte; - struct { - byte AM0 :1; /* Acceptance Mask Bit 0 */ - byte AM1 :1; /* Acceptance Mask Bit 1 */ - byte AM2 :1; /* Acceptance Mask Bit 2 */ - byte AM3 :1; /* Acceptance Mask Bit 3 */ - byte AM4 :1; /* Acceptance Mask Bit 4 */ - byte AM5 :1; /* Acceptance Mask Bit 5 */ - byte AM6 :1; /* Acceptance Mask Bit 6 */ - byte AM7 :1; /* Acceptance Mask Bit 7 */ - } Bits; - struct { - byte grpAM :8; - } MergedBits; -} CANIDMR7STR; -extern volatile CANIDMR7STR _CANIDMR7 @(REG_BASE + 0x0000015F); -#define CANIDMR7 _CANIDMR7.Byte -#define CANIDMR7_AM0 _CANIDMR7.Bits.AM0 -#define CANIDMR7_AM1 _CANIDMR7.Bits.AM1 -#define CANIDMR7_AM2 _CANIDMR7.Bits.AM2 -#define CANIDMR7_AM3 _CANIDMR7.Bits.AM3 -#define CANIDMR7_AM4 _CANIDMR7.Bits.AM4 -#define CANIDMR7_AM5 _CANIDMR7.Bits.AM5 -#define CANIDMR7_AM6 _CANIDMR7.Bits.AM6 -#define CANIDMR7_AM7 _CANIDMR7.Bits.AM7 -#define CANIDMR7_AM _CANIDMR7.MergedBits.grpAM - - -/*** CANRXIDR0 - MSCAN Receive Identifier Register 0; 0x00000160 ***/ -typedef union { - byte Byte; - struct { - byte ID21 :1; /* Extended format identifier Bit 21 */ - byte ID22 :1; /* Extended format identifier Bit 22 */ - byte ID23 :1; /* Extended format identifier Bit 23 */ - byte ID24 :1; /* Extended format identifier Bit 24 */ - byte ID25 :1; /* Extended format identifier Bit 25 */ - byte ID26 :1; /* Extended format identifier Bit 26 */ - byte ID27 :1; /* Extended format identifier Bit 27 */ - byte ID28 :1; /* Extended format identifier Bit 28 */ - } Bits; - struct { - byte grpID_21 :8; - } MergedBits; -} CANRXIDR0STR; -extern volatile CANRXIDR0STR _CANRXIDR0 @(REG_BASE + 0x00000160); -#define CANRXIDR0 _CANRXIDR0.Byte -#define CANRXIDR0_ID21 _CANRXIDR0.Bits.ID21 -#define CANRXIDR0_ID22 _CANRXIDR0.Bits.ID22 -#define CANRXIDR0_ID23 _CANRXIDR0.Bits.ID23 -#define CANRXIDR0_ID24 _CANRXIDR0.Bits.ID24 -#define CANRXIDR0_ID25 _CANRXIDR0.Bits.ID25 -#define CANRXIDR0_ID26 _CANRXIDR0.Bits.ID26 -#define CANRXIDR0_ID27 _CANRXIDR0.Bits.ID27 -#define CANRXIDR0_ID28 _CANRXIDR0.Bits.ID28 -#define CANRXIDR0_ID_21 _CANRXIDR0.MergedBits.grpID_21 -#define CANRXIDR0_ID CANRXIDR0_ID_21 - - -/*** CANRXIDR1 - MSCAN Receive Identifier Register 1; 0x00000161 ***/ -typedef union { - byte Byte; - struct { - byte ID15 :1; /* Extended format identifier Bit 15 */ - byte ID16 :1; /* Extended format identifier Bit 16 */ - byte ID17 :1; /* Extended format identifier Bit 17 */ - byte IDE :1; /* ID Extended */ - byte SRR :1; /* Substitute Remote Request */ - byte ID18 :1; /* Extended format identifier Bit 18 */ - byte ID19 :1; /* Extended format identifier Bit 19 */ - byte ID20 :1; /* Extended format identifier Bit 20 */ - } Bits; - struct { - byte grpID_15 :3; - byte :1; - byte :1; - byte grpID_18 :3; - } MergedBits; -} CANRXIDR1STR; -extern volatile CANRXIDR1STR _CANRXIDR1 @(REG_BASE + 0x00000161); -#define CANRXIDR1 _CANRXIDR1.Byte -#define CANRXIDR1_ID15 _CANRXIDR1.Bits.ID15 -#define CANRXIDR1_ID16 _CANRXIDR1.Bits.ID16 -#define CANRXIDR1_ID17 _CANRXIDR1.Bits.ID17 -#define CANRXIDR1_IDE _CANRXIDR1.Bits.IDE -#define CANRXIDR1_SRR _CANRXIDR1.Bits.SRR -#define CANRXIDR1_ID18 _CANRXIDR1.Bits.ID18 -#define CANRXIDR1_ID19 _CANRXIDR1.Bits.ID19 -#define CANRXIDR1_ID20 _CANRXIDR1.Bits.ID20 -#define CANRXIDR1_ID_15 _CANRXIDR1.MergedBits.grpID_15 -#define CANRXIDR1_ID_18 _CANRXIDR1.MergedBits.grpID_18 -#define CANRXIDR1_ID CANRXIDR1_ID_15 - - -/*** CANRXIDR2 - MSCAN Receive Identifier Register 2; 0x00000162 ***/ -typedef union { - byte Byte; - struct { - byte ID7 :1; /* Extended format identifier Bit 7 */ - byte ID8 :1; /* Extended format identifier Bit 8 */ - byte ID9 :1; /* Extended format identifier Bit 9 */ - byte ID10 :1; /* Extended format identifier Bit 10 */ - byte ID11 :1; /* Extended format identifier Bit 11 */ - byte ID12 :1; /* Extended format identifier Bit 12 */ - byte ID13 :1; /* Extended format identifier Bit 13 */ - byte ID14 :1; /* Extended format identifier Bit 14 */ - } Bits; - struct { - byte grpID_7 :8; - } MergedBits; -} CANRXIDR2STR; -extern volatile CANRXIDR2STR _CANRXIDR2 @(REG_BASE + 0x00000162); -#define CANRXIDR2 _CANRXIDR2.Byte -#define CANRXIDR2_ID7 _CANRXIDR2.Bits.ID7 -#define CANRXIDR2_ID8 _CANRXIDR2.Bits.ID8 -#define CANRXIDR2_ID9 _CANRXIDR2.Bits.ID9 -#define CANRXIDR2_ID10 _CANRXIDR2.Bits.ID10 -#define CANRXIDR2_ID11 _CANRXIDR2.Bits.ID11 -#define CANRXIDR2_ID12 _CANRXIDR2.Bits.ID12 -#define CANRXIDR2_ID13 _CANRXIDR2.Bits.ID13 -#define CANRXIDR2_ID14 _CANRXIDR2.Bits.ID14 -#define CANRXIDR2_ID_7 _CANRXIDR2.MergedBits.grpID_7 -#define CANRXIDR2_ID CANRXIDR2_ID_7 - - -/*** CANRXIDR3 - MSCAN Receive Identifier Register 3; 0x00000163 ***/ -typedef union { - byte Byte; - struct { - byte RTR :1; /* Remote Transmission Request */ - byte ID0 :1; /* Extended format identifier Bit 0 */ - byte ID1 :1; /* Extended format identifier Bit 1 */ - byte ID2 :1; /* Extended format identifier Bit 2 */ - byte ID3 :1; /* Extended format identifier Bit 3 */ - byte ID4 :1; /* Extended format identifier Bit 4 */ - byte ID5 :1; /* Extended format identifier Bit 5 */ - byte ID6 :1; /* Extended format identifier Bit 6 */ - } Bits; - struct { - byte :1; - byte grpID :7; - } MergedBits; -} CANRXIDR3STR; -extern volatile CANRXIDR3STR _CANRXIDR3 @(REG_BASE + 0x00000163); -#define CANRXIDR3 _CANRXIDR3.Byte -#define CANRXIDR3_RTR _CANRXIDR3.Bits.RTR -#define CANRXIDR3_ID0 _CANRXIDR3.Bits.ID0 -#define CANRXIDR3_ID1 _CANRXIDR3.Bits.ID1 -#define CANRXIDR3_ID2 _CANRXIDR3.Bits.ID2 -#define CANRXIDR3_ID3 _CANRXIDR3.Bits.ID3 -#define CANRXIDR3_ID4 _CANRXIDR3.Bits.ID4 -#define CANRXIDR3_ID5 _CANRXIDR3.Bits.ID5 -#define CANRXIDR3_ID6 _CANRXIDR3.Bits.ID6 -#define CANRXIDR3_ID _CANRXIDR3.MergedBits.grpID - - -/*** CANRXDSR0 - MSCAN Receive Data Segment Register 0; 0x00000164 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CANRXDSR0STR; -extern volatile CANRXDSR0STR _CANRXDSR0 @(REG_BASE + 0x00000164); -#define CANRXDSR0 _CANRXDSR0.Byte -#define CANRXDSR0_DB0 _CANRXDSR0.Bits.DB0 -#define CANRXDSR0_DB1 _CANRXDSR0.Bits.DB1 -#define CANRXDSR0_DB2 _CANRXDSR0.Bits.DB2 -#define CANRXDSR0_DB3 _CANRXDSR0.Bits.DB3 -#define CANRXDSR0_DB4 _CANRXDSR0.Bits.DB4 -#define CANRXDSR0_DB5 _CANRXDSR0.Bits.DB5 -#define CANRXDSR0_DB6 _CANRXDSR0.Bits.DB6 -#define CANRXDSR0_DB7 _CANRXDSR0.Bits.DB7 -#define CANRXDSR0_DB _CANRXDSR0.MergedBits.grpDB - - -/*** CANRXDSR1 - MSCAN Receive Data Segment Register 1; 0x00000165 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CANRXDSR1STR; -extern volatile CANRXDSR1STR _CANRXDSR1 @(REG_BASE + 0x00000165); -#define CANRXDSR1 _CANRXDSR1.Byte -#define CANRXDSR1_DB0 _CANRXDSR1.Bits.DB0 -#define CANRXDSR1_DB1 _CANRXDSR1.Bits.DB1 -#define CANRXDSR1_DB2 _CANRXDSR1.Bits.DB2 -#define CANRXDSR1_DB3 _CANRXDSR1.Bits.DB3 -#define CANRXDSR1_DB4 _CANRXDSR1.Bits.DB4 -#define CANRXDSR1_DB5 _CANRXDSR1.Bits.DB5 -#define CANRXDSR1_DB6 _CANRXDSR1.Bits.DB6 -#define CANRXDSR1_DB7 _CANRXDSR1.Bits.DB7 -#define CANRXDSR1_DB _CANRXDSR1.MergedBits.grpDB - - -/*** CANRXDSR2 - MSCAN Receive Data Segment Register 2; 0x00000166 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CANRXDSR2STR; -extern volatile CANRXDSR2STR _CANRXDSR2 @(REG_BASE + 0x00000166); -#define CANRXDSR2 _CANRXDSR2.Byte -#define CANRXDSR2_DB0 _CANRXDSR2.Bits.DB0 -#define CANRXDSR2_DB1 _CANRXDSR2.Bits.DB1 -#define CANRXDSR2_DB2 _CANRXDSR2.Bits.DB2 -#define CANRXDSR2_DB3 _CANRXDSR2.Bits.DB3 -#define CANRXDSR2_DB4 _CANRXDSR2.Bits.DB4 -#define CANRXDSR2_DB5 _CANRXDSR2.Bits.DB5 -#define CANRXDSR2_DB6 _CANRXDSR2.Bits.DB6 -#define CANRXDSR2_DB7 _CANRXDSR2.Bits.DB7 -#define CANRXDSR2_DB _CANRXDSR2.MergedBits.grpDB - - -/*** CANRXDSR3 - MSCAN Receive Data Segment Register 3; 0x00000167 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CANRXDSR3STR; -extern volatile CANRXDSR3STR _CANRXDSR3 @(REG_BASE + 0x00000167); -#define CANRXDSR3 _CANRXDSR3.Byte -#define CANRXDSR3_DB0 _CANRXDSR3.Bits.DB0 -#define CANRXDSR3_DB1 _CANRXDSR3.Bits.DB1 -#define CANRXDSR3_DB2 _CANRXDSR3.Bits.DB2 -#define CANRXDSR3_DB3 _CANRXDSR3.Bits.DB3 -#define CANRXDSR3_DB4 _CANRXDSR3.Bits.DB4 -#define CANRXDSR3_DB5 _CANRXDSR3.Bits.DB5 -#define CANRXDSR3_DB6 _CANRXDSR3.Bits.DB6 -#define CANRXDSR3_DB7 _CANRXDSR3.Bits.DB7 -#define CANRXDSR3_DB _CANRXDSR3.MergedBits.grpDB - - -/*** CANRXDSR4 - MSCAN Receive Data Segment Register 4; 0x00000168 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CANRXDSR4STR; -extern volatile CANRXDSR4STR _CANRXDSR4 @(REG_BASE + 0x00000168); -#define CANRXDSR4 _CANRXDSR4.Byte -#define CANRXDSR4_DB0 _CANRXDSR4.Bits.DB0 -#define CANRXDSR4_DB1 _CANRXDSR4.Bits.DB1 -#define CANRXDSR4_DB2 _CANRXDSR4.Bits.DB2 -#define CANRXDSR4_DB3 _CANRXDSR4.Bits.DB3 -#define CANRXDSR4_DB4 _CANRXDSR4.Bits.DB4 -#define CANRXDSR4_DB5 _CANRXDSR4.Bits.DB5 -#define CANRXDSR4_DB6 _CANRXDSR4.Bits.DB6 -#define CANRXDSR4_DB7 _CANRXDSR4.Bits.DB7 -#define CANRXDSR4_DB _CANRXDSR4.MergedBits.grpDB - - -/*** CANRXDSR5 - MSCAN Receive Data Segment Register 5; 0x00000169 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CANRXDSR5STR; -extern volatile CANRXDSR5STR _CANRXDSR5 @(REG_BASE + 0x00000169); -#define CANRXDSR5 _CANRXDSR5.Byte -#define CANRXDSR5_DB0 _CANRXDSR5.Bits.DB0 -#define CANRXDSR5_DB1 _CANRXDSR5.Bits.DB1 -#define CANRXDSR5_DB2 _CANRXDSR5.Bits.DB2 -#define CANRXDSR5_DB3 _CANRXDSR5.Bits.DB3 -#define CANRXDSR5_DB4 _CANRXDSR5.Bits.DB4 -#define CANRXDSR5_DB5 _CANRXDSR5.Bits.DB5 -#define CANRXDSR5_DB6 _CANRXDSR5.Bits.DB6 -#define CANRXDSR5_DB7 _CANRXDSR5.Bits.DB7 -#define CANRXDSR5_DB _CANRXDSR5.MergedBits.grpDB - - -/*** CANRXDSR6 - MSCAN Receive Data Segment Register 6; 0x0000016A ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CANRXDSR6STR; -extern volatile CANRXDSR6STR _CANRXDSR6 @(REG_BASE + 0x0000016A); -#define CANRXDSR6 _CANRXDSR6.Byte -#define CANRXDSR6_DB0 _CANRXDSR6.Bits.DB0 -#define CANRXDSR6_DB1 _CANRXDSR6.Bits.DB1 -#define CANRXDSR6_DB2 _CANRXDSR6.Bits.DB2 -#define CANRXDSR6_DB3 _CANRXDSR6.Bits.DB3 -#define CANRXDSR6_DB4 _CANRXDSR6.Bits.DB4 -#define CANRXDSR6_DB5 _CANRXDSR6.Bits.DB5 -#define CANRXDSR6_DB6 _CANRXDSR6.Bits.DB6 -#define CANRXDSR6_DB7 _CANRXDSR6.Bits.DB7 -#define CANRXDSR6_DB _CANRXDSR6.MergedBits.grpDB - - -/*** CANRXDSR7 - MSCAN Receive Data Segment Register 7; 0x0000016B ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CANRXDSR7STR; -extern volatile CANRXDSR7STR _CANRXDSR7 @(REG_BASE + 0x0000016B); -#define CANRXDSR7 _CANRXDSR7.Byte -#define CANRXDSR7_DB0 _CANRXDSR7.Bits.DB0 -#define CANRXDSR7_DB1 _CANRXDSR7.Bits.DB1 -#define CANRXDSR7_DB2 _CANRXDSR7.Bits.DB2 -#define CANRXDSR7_DB3 _CANRXDSR7.Bits.DB3 -#define CANRXDSR7_DB4 _CANRXDSR7.Bits.DB4 -#define CANRXDSR7_DB5 _CANRXDSR7.Bits.DB5 -#define CANRXDSR7_DB6 _CANRXDSR7.Bits.DB6 -#define CANRXDSR7_DB7 _CANRXDSR7.Bits.DB7 -#define CANRXDSR7_DB _CANRXDSR7.MergedBits.grpDB - - -/*** CANRXDLR - MSCAN Receive Data Length Register; 0x0000016C ***/ -typedef union { - byte Byte; - struct { - byte DLC0 :1; /* Data Length Code Bit 0 */ - byte DLC1 :1; /* Data Length Code Bit 1 */ - byte DLC2 :1; /* Data Length Code Bit 2 */ - byte DLC3 :1; /* Data Length Code Bit 3 */ - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpDLC :4; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} CANRXDLRSTR; -extern volatile CANRXDLRSTR _CANRXDLR @(REG_BASE + 0x0000016C); -#define CANRXDLR _CANRXDLR.Byte -#define CANRXDLR_DLC0 _CANRXDLR.Bits.DLC0 -#define CANRXDLR_DLC1 _CANRXDLR.Bits.DLC1 -#define CANRXDLR_DLC2 _CANRXDLR.Bits.DLC2 -#define CANRXDLR_DLC3 _CANRXDLR.Bits.DLC3 -#define CANRXDLR_DLC _CANRXDLR.MergedBits.grpDLC - - -/*** CANTXIDR0 - MSCAN Transmit Identifier Register 0; 0x00000170 ***/ -typedef union { - byte Byte; - struct { - byte ID21 :1; /* Extended format identifier Bit 21 */ - byte ID22 :1; /* Extended format identifier Bit 22 */ - byte ID23 :1; /* Extended format identifier Bit 23 */ - byte ID24 :1; /* Extended format identifier Bit 24 */ - byte ID25 :1; /* Extended format identifier Bit 25 */ - byte ID26 :1; /* Extended format identifier Bit 26 */ - byte ID27 :1; /* Extended format identifier Bit 27 */ - byte ID28 :1; /* Extended format identifier Bit 28 */ - } Bits; - struct { - byte grpID_21 :8; - } MergedBits; -} CANTXIDR0STR; -extern volatile CANTXIDR0STR _CANTXIDR0 @(REG_BASE + 0x00000170); -#define CANTXIDR0 _CANTXIDR0.Byte -#define CANTXIDR0_ID21 _CANTXIDR0.Bits.ID21 -#define CANTXIDR0_ID22 _CANTXIDR0.Bits.ID22 -#define CANTXIDR0_ID23 _CANTXIDR0.Bits.ID23 -#define CANTXIDR0_ID24 _CANTXIDR0.Bits.ID24 -#define CANTXIDR0_ID25 _CANTXIDR0.Bits.ID25 -#define CANTXIDR0_ID26 _CANTXIDR0.Bits.ID26 -#define CANTXIDR0_ID27 _CANTXIDR0.Bits.ID27 -#define CANTXIDR0_ID28 _CANTXIDR0.Bits.ID28 -#define CANTXIDR0_ID_21 _CANTXIDR0.MergedBits.grpID_21 -#define CANTXIDR0_ID CANTXIDR0_ID_21 - - -/*** CANTXIDR1 - MSCAN Transmit Identifier Register 1; 0x00000171 ***/ -typedef union { - byte Byte; - struct { - byte ID15 :1; /* Extended format identifier Bit 15 */ - byte ID16 :1; /* Extended format identifier Bit 16 */ - byte ID17 :1; /* Extended format identifier Bit 17 */ - byte IDE :1; /* ID Extended */ - byte SRR :1; /* Substitute Remote Request */ - byte ID18 :1; /* Extended format identifier Bit 18 */ - byte ID19 :1; /* Extended format identifier Bit 19 */ - byte ID20 :1; /* Extended format identifier Bit 20 */ - } Bits; - struct { - byte grpID_15 :3; - byte :1; - byte :1; - byte grpID_18 :3; - } MergedBits; -} CANTXIDR1STR; -extern volatile CANTXIDR1STR _CANTXIDR1 @(REG_BASE + 0x00000171); -#define CANTXIDR1 _CANTXIDR1.Byte -#define CANTXIDR1_ID15 _CANTXIDR1.Bits.ID15 -#define CANTXIDR1_ID16 _CANTXIDR1.Bits.ID16 -#define CANTXIDR1_ID17 _CANTXIDR1.Bits.ID17 -#define CANTXIDR1_IDE _CANTXIDR1.Bits.IDE -#define CANTXIDR1_SRR _CANTXIDR1.Bits.SRR -#define CANTXIDR1_ID18 _CANTXIDR1.Bits.ID18 -#define CANTXIDR1_ID19 _CANTXIDR1.Bits.ID19 -#define CANTXIDR1_ID20 _CANTXIDR1.Bits.ID20 -#define CANTXIDR1_ID_15 _CANTXIDR1.MergedBits.grpID_15 -#define CANTXIDR1_ID_18 _CANTXIDR1.MergedBits.grpID_18 -#define CANTXIDR1_ID CANTXIDR1_ID_15 - - -/*** CANTXIDR2 - MSCAN Transmit Identifier Register 2; 0x00000172 ***/ -typedef union { - byte Byte; - struct { - byte ID7 :1; /* Extended format identifier Bit 7 */ - byte ID8 :1; /* Extended format identifier Bit 8 */ - byte ID9 :1; /* Extended format identifier Bit 9 */ - byte ID10 :1; /* Extended format identifier Bit 10 */ - byte ID11 :1; /* Extended format identifier Bit 11 */ - byte ID12 :1; /* Extended format identifier Bit 12 */ - byte ID13 :1; /* Extended format identifier Bit 13 */ - byte ID14 :1; /* Extended format identifier Bit 14 */ - } Bits; - struct { - byte grpID_7 :8; - } MergedBits; -} CANTXIDR2STR; -extern volatile CANTXIDR2STR _CANTXIDR2 @(REG_BASE + 0x00000172); -#define CANTXIDR2 _CANTXIDR2.Byte -#define CANTXIDR2_ID7 _CANTXIDR2.Bits.ID7 -#define CANTXIDR2_ID8 _CANTXIDR2.Bits.ID8 -#define CANTXIDR2_ID9 _CANTXIDR2.Bits.ID9 -#define CANTXIDR2_ID10 _CANTXIDR2.Bits.ID10 -#define CANTXIDR2_ID11 _CANTXIDR2.Bits.ID11 -#define CANTXIDR2_ID12 _CANTXIDR2.Bits.ID12 -#define CANTXIDR2_ID13 _CANTXIDR2.Bits.ID13 -#define CANTXIDR2_ID14 _CANTXIDR2.Bits.ID14 -#define CANTXIDR2_ID_7 _CANTXIDR2.MergedBits.grpID_7 -#define CANTXIDR2_ID CANTXIDR2_ID_7 - - -/*** CANTXIDR3 - MSCAN Transmit Identifier Register 3; 0x00000173 ***/ -typedef union { - byte Byte; - struct { - byte RTR :1; /* Remote Transmission Request */ - byte ID0 :1; /* Extended format identifier Bit 0 */ - byte ID1 :1; /* Extended format identifier Bit 1 */ - byte ID2 :1; /* Extended format identifier Bit 2 */ - byte ID3 :1; /* Extended format identifier Bit 3 */ - byte ID4 :1; /* Extended format identifier Bit 4 */ - byte ID5 :1; /* Extended format identifier Bit 5 */ - byte ID6 :1; /* Extended format identifier Bit 6 */ - } Bits; - struct { - byte :1; - byte grpID :7; - } MergedBits; -} CANTXIDR3STR; -extern volatile CANTXIDR3STR _CANTXIDR3 @(REG_BASE + 0x00000173); -#define CANTXIDR3 _CANTXIDR3.Byte -#define CANTXIDR3_RTR _CANTXIDR3.Bits.RTR -#define CANTXIDR3_ID0 _CANTXIDR3.Bits.ID0 -#define CANTXIDR3_ID1 _CANTXIDR3.Bits.ID1 -#define CANTXIDR3_ID2 _CANTXIDR3.Bits.ID2 -#define CANTXIDR3_ID3 _CANTXIDR3.Bits.ID3 -#define CANTXIDR3_ID4 _CANTXIDR3.Bits.ID4 -#define CANTXIDR3_ID5 _CANTXIDR3.Bits.ID5 -#define CANTXIDR3_ID6 _CANTXIDR3.Bits.ID6 -#define CANTXIDR3_ID _CANTXIDR3.MergedBits.grpID - - -/*** CANTXDSR0 - MSCAN Transmit Data Segment Register 0; 0x00000174 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CANTXDSR0STR; -extern volatile CANTXDSR0STR _CANTXDSR0 @(REG_BASE + 0x00000174); -#define CANTXDSR0 _CANTXDSR0.Byte -#define CANTXDSR0_DB0 _CANTXDSR0.Bits.DB0 -#define CANTXDSR0_DB1 _CANTXDSR0.Bits.DB1 -#define CANTXDSR0_DB2 _CANTXDSR0.Bits.DB2 -#define CANTXDSR0_DB3 _CANTXDSR0.Bits.DB3 -#define CANTXDSR0_DB4 _CANTXDSR0.Bits.DB4 -#define CANTXDSR0_DB5 _CANTXDSR0.Bits.DB5 -#define CANTXDSR0_DB6 _CANTXDSR0.Bits.DB6 -#define CANTXDSR0_DB7 _CANTXDSR0.Bits.DB7 -#define CANTXDSR0_DB _CANTXDSR0.MergedBits.grpDB - - -/*** CANTXDSR1 - MSCAN Transmit Data Segment Register 1; 0x00000175 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CANTXDSR1STR; -extern volatile CANTXDSR1STR _CANTXDSR1 @(REG_BASE + 0x00000175); -#define CANTXDSR1 _CANTXDSR1.Byte -#define CANTXDSR1_DB0 _CANTXDSR1.Bits.DB0 -#define CANTXDSR1_DB1 _CANTXDSR1.Bits.DB1 -#define CANTXDSR1_DB2 _CANTXDSR1.Bits.DB2 -#define CANTXDSR1_DB3 _CANTXDSR1.Bits.DB3 -#define CANTXDSR1_DB4 _CANTXDSR1.Bits.DB4 -#define CANTXDSR1_DB5 _CANTXDSR1.Bits.DB5 -#define CANTXDSR1_DB6 _CANTXDSR1.Bits.DB6 -#define CANTXDSR1_DB7 _CANTXDSR1.Bits.DB7 -#define CANTXDSR1_DB _CANTXDSR1.MergedBits.grpDB - - -/*** CANTXDSR2 - MSCAN Transmit Data Segment Register 2; 0x00000176 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CANTXDSR2STR; -extern volatile CANTXDSR2STR _CANTXDSR2 @(REG_BASE + 0x00000176); -#define CANTXDSR2 _CANTXDSR2.Byte -#define CANTXDSR2_DB0 _CANTXDSR2.Bits.DB0 -#define CANTXDSR2_DB1 _CANTXDSR2.Bits.DB1 -#define CANTXDSR2_DB2 _CANTXDSR2.Bits.DB2 -#define CANTXDSR2_DB3 _CANTXDSR2.Bits.DB3 -#define CANTXDSR2_DB4 _CANTXDSR2.Bits.DB4 -#define CANTXDSR2_DB5 _CANTXDSR2.Bits.DB5 -#define CANTXDSR2_DB6 _CANTXDSR2.Bits.DB6 -#define CANTXDSR2_DB7 _CANTXDSR2.Bits.DB7 -#define CANTXDSR2_DB _CANTXDSR2.MergedBits.grpDB - - -/*** CANTXDSR3 - MSCAN Transmit Data Segment Register 3; 0x00000177 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CANTXDSR3STR; -extern volatile CANTXDSR3STR _CANTXDSR3 @(REG_BASE + 0x00000177); -#define CANTXDSR3 _CANTXDSR3.Byte -#define CANTXDSR3_DB0 _CANTXDSR3.Bits.DB0 -#define CANTXDSR3_DB1 _CANTXDSR3.Bits.DB1 -#define CANTXDSR3_DB2 _CANTXDSR3.Bits.DB2 -#define CANTXDSR3_DB3 _CANTXDSR3.Bits.DB3 -#define CANTXDSR3_DB4 _CANTXDSR3.Bits.DB4 -#define CANTXDSR3_DB5 _CANTXDSR3.Bits.DB5 -#define CANTXDSR3_DB6 _CANTXDSR3.Bits.DB6 -#define CANTXDSR3_DB7 _CANTXDSR3.Bits.DB7 -#define CANTXDSR3_DB _CANTXDSR3.MergedBits.grpDB - - -/*** CANTXDSR4 - MSCAN Transmit Data Segment Register 4; 0x00000178 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CANTXDSR4STR; -extern volatile CANTXDSR4STR _CANTXDSR4 @(REG_BASE + 0x00000178); -#define CANTXDSR4 _CANTXDSR4.Byte -#define CANTXDSR4_DB0 _CANTXDSR4.Bits.DB0 -#define CANTXDSR4_DB1 _CANTXDSR4.Bits.DB1 -#define CANTXDSR4_DB2 _CANTXDSR4.Bits.DB2 -#define CANTXDSR4_DB3 _CANTXDSR4.Bits.DB3 -#define CANTXDSR4_DB4 _CANTXDSR4.Bits.DB4 -#define CANTXDSR4_DB5 _CANTXDSR4.Bits.DB5 -#define CANTXDSR4_DB6 _CANTXDSR4.Bits.DB6 -#define CANTXDSR4_DB7 _CANTXDSR4.Bits.DB7 -#define CANTXDSR4_DB _CANTXDSR4.MergedBits.grpDB - - -/*** CANTXDSR5 - MSCAN Transmit Data Segment Register 5; 0x00000179 ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CANTXDSR5STR; -extern volatile CANTXDSR5STR _CANTXDSR5 @(REG_BASE + 0x00000179); -#define CANTXDSR5 _CANTXDSR5.Byte -#define CANTXDSR5_DB0 _CANTXDSR5.Bits.DB0 -#define CANTXDSR5_DB1 _CANTXDSR5.Bits.DB1 -#define CANTXDSR5_DB2 _CANTXDSR5.Bits.DB2 -#define CANTXDSR5_DB3 _CANTXDSR5.Bits.DB3 -#define CANTXDSR5_DB4 _CANTXDSR5.Bits.DB4 -#define CANTXDSR5_DB5 _CANTXDSR5.Bits.DB5 -#define CANTXDSR5_DB6 _CANTXDSR5.Bits.DB6 -#define CANTXDSR5_DB7 _CANTXDSR5.Bits.DB7 -#define CANTXDSR5_DB _CANTXDSR5.MergedBits.grpDB - - -/*** CANTXDSR6 - MSCAN Transmit Data Segment Register 6; 0x0000017A ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CANTXDSR6STR; -extern volatile CANTXDSR6STR _CANTXDSR6 @(REG_BASE + 0x0000017A); -#define CANTXDSR6 _CANTXDSR6.Byte -#define CANTXDSR6_DB0 _CANTXDSR6.Bits.DB0 -#define CANTXDSR6_DB1 _CANTXDSR6.Bits.DB1 -#define CANTXDSR6_DB2 _CANTXDSR6.Bits.DB2 -#define CANTXDSR6_DB3 _CANTXDSR6.Bits.DB3 -#define CANTXDSR6_DB4 _CANTXDSR6.Bits.DB4 -#define CANTXDSR6_DB5 _CANTXDSR6.Bits.DB5 -#define CANTXDSR6_DB6 _CANTXDSR6.Bits.DB6 -#define CANTXDSR6_DB7 _CANTXDSR6.Bits.DB7 -#define CANTXDSR6_DB _CANTXDSR6.MergedBits.grpDB - - -/*** CANTXDSR7 - MSCAN Transmit Data Segment Register 7; 0x0000017B ***/ -typedef union { - byte Byte; - struct { - byte DB0 :1; /* Data Bit 0 */ - byte DB1 :1; /* Data Bit 1 */ - byte DB2 :1; /* Data Bit 2 */ - byte DB3 :1; /* Data Bit 3 */ - byte DB4 :1; /* Data Bit 4 */ - byte DB5 :1; /* Data Bit 5 */ - byte DB6 :1; /* Data Bit 6 */ - byte DB7 :1; /* Data Bit 7 */ - } Bits; - struct { - byte grpDB :8; - } MergedBits; -} CANTXDSR7STR; -extern volatile CANTXDSR7STR _CANTXDSR7 @(REG_BASE + 0x0000017B); -#define CANTXDSR7 _CANTXDSR7.Byte -#define CANTXDSR7_DB0 _CANTXDSR7.Bits.DB0 -#define CANTXDSR7_DB1 _CANTXDSR7.Bits.DB1 -#define CANTXDSR7_DB2 _CANTXDSR7.Bits.DB2 -#define CANTXDSR7_DB3 _CANTXDSR7.Bits.DB3 -#define CANTXDSR7_DB4 _CANTXDSR7.Bits.DB4 -#define CANTXDSR7_DB5 _CANTXDSR7.Bits.DB5 -#define CANTXDSR7_DB6 _CANTXDSR7.Bits.DB6 -#define CANTXDSR7_DB7 _CANTXDSR7.Bits.DB7 -#define CANTXDSR7_DB _CANTXDSR7.MergedBits.grpDB - - -/*** CANTXDLR - MSCAN Transmit Data Length Register; 0x0000017C ***/ -typedef union { - byte Byte; - struct { - byte DLC0 :1; /* Data Length Code Bit 0 */ - byte DLC1 :1; /* Data Length Code Bit 1 */ - byte DLC2 :1; /* Data Length Code Bit 2 */ - byte DLC3 :1; /* Data Length Code Bit 3 */ - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpDLC :4; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} CANTXDLRSTR; -extern volatile CANTXDLRSTR _CANTXDLR @(REG_BASE + 0x0000017C); -#define CANTXDLR _CANTXDLR.Byte -#define CANTXDLR_DLC0 _CANTXDLR.Bits.DLC0 -#define CANTXDLR_DLC1 _CANTXDLR.Bits.DLC1 -#define CANTXDLR_DLC2 _CANTXDLR.Bits.DLC2 -#define CANTXDLR_DLC3 _CANTXDLR.Bits.DLC3 -#define CANTXDLR_DLC _CANTXDLR.MergedBits.grpDLC - - -/*** CANTXTBPR - MSCAN Transmit Buffer Priority; 0x0000017F ***/ -typedef union { - byte Byte; - struct { - byte PRIO0 :1; /* Transmit Buffer Priority Bit 0 */ - byte PRIO1 :1; /* Transmit Buffer Priority Bit 1 */ - byte PRIO2 :1; /* Transmit Buffer Priority Bit 2 */ - byte PRIO3 :1; /* Transmit Buffer Priority Bit 3 */ - byte PRIO4 :1; /* Transmit Buffer Priority Bit 4 */ - byte PRIO5 :1; /* Transmit Buffer Priority Bit 5 */ - byte PRIO6 :1; /* Transmit Buffer Priority Bit 6 */ - byte PRIO7 :1; /* Transmit Buffer Priority Bit 7 */ - } Bits; - struct { - byte grpPRIO :8; - } MergedBits; -} CANTXTBPRSTR; -extern volatile CANTXTBPRSTR _CANTXTBPR @(REG_BASE + 0x0000017F); -#define CANTXTBPR _CANTXTBPR.Byte -#define CANTXTBPR_PRIO0 _CANTXTBPR.Bits.PRIO0 -#define CANTXTBPR_PRIO1 _CANTXTBPR.Bits.PRIO1 -#define CANTXTBPR_PRIO2 _CANTXTBPR.Bits.PRIO2 -#define CANTXTBPR_PRIO3 _CANTXTBPR.Bits.PRIO3 -#define CANTXTBPR_PRIO4 _CANTXTBPR.Bits.PRIO4 -#define CANTXTBPR_PRIO5 _CANTXTBPR.Bits.PRIO5 -#define CANTXTBPR_PRIO6 _CANTXTBPR.Bits.PRIO6 -#define CANTXTBPR_PRIO7 _CANTXTBPR.Bits.PRIO7 -#define CANTXTBPR_PRIO _CANTXTBPR.MergedBits.grpPRIO - - -/*** PTT - Port T I/O Register; 0x00000240 ***/ -typedef union { - byte Byte; - struct { - byte PTT0 :1; /* Port T Bit 0 */ - byte PTT1 :1; /* Port T Bit 1 */ - byte PTT2 :1; /* Port T Bit 2 */ - byte PTT3 :1; /* Port T Bit 3 */ - byte PTT4 :1; /* Port T Bit 4 */ - byte PTT5 :1; /* Port T Bit 5 */ - byte PTT6 :1; /* Port T Bit 6 */ - byte PTT7 :1; /* Port T Bit 7 */ - } Bits; - struct { - byte grpPTT :8; - } MergedBits; -} PTTSTR; -extern volatile PTTSTR _PTT @(REG_BASE + 0x00000240); -#define PTT _PTT.Byte -#define PTT_PTT0 _PTT.Bits.PTT0 -#define PTT_PTT1 _PTT.Bits.PTT1 -#define PTT_PTT2 _PTT.Bits.PTT2 -#define PTT_PTT3 _PTT.Bits.PTT3 -#define PTT_PTT4 _PTT.Bits.PTT4 -#define PTT_PTT5 _PTT.Bits.PTT5 -#define PTT_PTT6 _PTT.Bits.PTT6 -#define PTT_PTT7 _PTT.Bits.PTT7 -#define PTT_PTT _PTT.MergedBits.grpPTT - - -/*** PTIT - Port T Input; 0x00000241 ***/ -typedef union { - byte Byte; - struct { - byte PTIT0 :1; /* Port T Bit 0 */ - byte PTIT1 :1; /* Port T Bit 1 */ - byte PTIT2 :1; /* Port T Bit 2 */ - byte PTIT3 :1; /* Port T Bit 3 */ - byte PTIT4 :1; /* Port T Bit 4 */ - byte PTIT5 :1; /* Port T Bit 5 */ - byte PTIT6 :1; /* Port T Bit 6 */ - byte PTIT7 :1; /* Port T Bit 7 */ - } Bits; - struct { - byte grpPTIT :8; - } MergedBits; -} PTITSTR; -extern volatile PTITSTR _PTIT @(REG_BASE + 0x00000241); -#define PTIT _PTIT.Byte -#define PTIT_PTIT0 _PTIT.Bits.PTIT0 -#define PTIT_PTIT1 _PTIT.Bits.PTIT1 -#define PTIT_PTIT2 _PTIT.Bits.PTIT2 -#define PTIT_PTIT3 _PTIT.Bits.PTIT3 -#define PTIT_PTIT4 _PTIT.Bits.PTIT4 -#define PTIT_PTIT5 _PTIT.Bits.PTIT5 -#define PTIT_PTIT6 _PTIT.Bits.PTIT6 -#define PTIT_PTIT7 _PTIT.Bits.PTIT7 -#define PTIT_PTIT _PTIT.MergedBits.grpPTIT - - -/*** DDRT - Port T Data Direction Register; 0x00000242 ***/ -typedef union { - byte Byte; - struct { - byte DDRT0 :1; /* Data Direction Port T Bit 0 */ - byte DDRT1 :1; /* Data Direction Port T Bit 1 */ - byte DDRT2 :1; /* Data Direction Port T Bit 2 */ - byte DDRT3 :1; /* Data Direction Port T Bit 3 */ - byte DDRT4 :1; /* Data Direction Port T Bit 4 */ - byte DDRT5 :1; /* Data Direction Port T Bit 5 */ - byte DDRT6 :1; /* Data Direction Port T Bit 6 */ - byte DDRT7 :1; /* Data Direction Port T Bit 7 */ - } Bits; - struct { - byte grpDDRT :8; - } MergedBits; -} DDRTSTR; -extern volatile DDRTSTR _DDRT @(REG_BASE + 0x00000242); -#define DDRT _DDRT.Byte -#define DDRT_DDRT0 _DDRT.Bits.DDRT0 -#define DDRT_DDRT1 _DDRT.Bits.DDRT1 -#define DDRT_DDRT2 _DDRT.Bits.DDRT2 -#define DDRT_DDRT3 _DDRT.Bits.DDRT3 -#define DDRT_DDRT4 _DDRT.Bits.DDRT4 -#define DDRT_DDRT5 _DDRT.Bits.DDRT5 -#define DDRT_DDRT6 _DDRT.Bits.DDRT6 -#define DDRT_DDRT7 _DDRT.Bits.DDRT7 -#define DDRT_DDRT _DDRT.MergedBits.grpDDRT - - -/*** RDRT - Port T Reduced Drive Register; 0x00000243 ***/ -typedef union { - byte Byte; - struct { - byte RDRT0 :1; /* Reduced Drive Port T Bit 0 */ - byte RDRT1 :1; /* Reduced Drive Port T Bit 1 */ - byte RDRT2 :1; /* Reduced Drive Port T Bit 2 */ - byte RDRT3 :1; /* Reduced Drive Port T Bit 3 */ - byte RDRT4 :1; /* Reduced Drive Port T Bit 4 */ - byte RDRT5 :1; /* Reduced Drive Port T Bit 5 */ - byte RDRT6 :1; /* Reduced Drive Port T Bit 6 */ - byte RDRT7 :1; /* Reduced Drive Port T Bit 7 */ - } Bits; - struct { - byte grpRDRT :8; - } MergedBits; -} RDRTSTR; -extern volatile RDRTSTR _RDRT @(REG_BASE + 0x00000243); -#define RDRT _RDRT.Byte -#define RDRT_RDRT0 _RDRT.Bits.RDRT0 -#define RDRT_RDRT1 _RDRT.Bits.RDRT1 -#define RDRT_RDRT2 _RDRT.Bits.RDRT2 -#define RDRT_RDRT3 _RDRT.Bits.RDRT3 -#define RDRT_RDRT4 _RDRT.Bits.RDRT4 -#define RDRT_RDRT5 _RDRT.Bits.RDRT5 -#define RDRT_RDRT6 _RDRT.Bits.RDRT6 -#define RDRT_RDRT7 _RDRT.Bits.RDRT7 -#define RDRT_RDRT _RDRT.MergedBits.grpRDRT - - -/*** PERT - Port T Pull Device Enable Register; 0x00000244 ***/ -typedef union { - byte Byte; - struct { - byte PERT0 :1; /* Pull Device Enable Port T Bit 0 */ - byte PERT1 :1; /* Pull Device Enable Port T Bit 1 */ - byte PERT2 :1; /* Pull Device Enable Port T Bit 2 */ - byte PERT3 :1; /* Pull Device Enable Port T Bit 3 */ - byte PERT4 :1; /* Pull Device Enable Port T Bit 4 */ - byte PERT5 :1; /* Pull Device Enable Port T Bit 5 */ - byte PERT6 :1; /* Pull Device Enable Port T Bit 6 */ - byte PERT7 :1; /* Pull Device Enable Port T Bit 7 */ - } Bits; - struct { - byte grpPERT :8; - } MergedBits; -} PERTSTR; -extern volatile PERTSTR _PERT @(REG_BASE + 0x00000244); -#define PERT _PERT.Byte -#define PERT_PERT0 _PERT.Bits.PERT0 -#define PERT_PERT1 _PERT.Bits.PERT1 -#define PERT_PERT2 _PERT.Bits.PERT2 -#define PERT_PERT3 _PERT.Bits.PERT3 -#define PERT_PERT4 _PERT.Bits.PERT4 -#define PERT_PERT5 _PERT.Bits.PERT5 -#define PERT_PERT6 _PERT.Bits.PERT6 -#define PERT_PERT7 _PERT.Bits.PERT7 -#define PERT_PERT _PERT.MergedBits.grpPERT - - -/*** PPST - Port T Polarity Select Register; 0x00000245 ***/ -typedef union { - byte Byte; - struct { - byte PPST0 :1; /* Pull Select Port T Bit 0 */ - byte PPST1 :1; /* Pull Select Port T Bit 1 */ - byte PPST2 :1; /* Pull Select Port T Bit 2 */ - byte PPST3 :1; /* Pull Select Port T Bit 3 */ - byte PPST4 :1; /* Pull Select Port T Bit 4 */ - byte PPST5 :1; /* Pull Select Port T Bit 5 */ - byte PPST6 :1; /* Pull Select Port T Bit 6 */ - byte PPST7 :1; /* Pull Select Port T Bit 7 */ - } Bits; - struct { - byte grpPPST :8; - } MergedBits; -} PPSTSTR; -extern volatile PPSTSTR _PPST @(REG_BASE + 0x00000245); -#define PPST _PPST.Byte -#define PPST_PPST0 _PPST.Bits.PPST0 -#define PPST_PPST1 _PPST.Bits.PPST1 -#define PPST_PPST2 _PPST.Bits.PPST2 -#define PPST_PPST3 _PPST.Bits.PPST3 -#define PPST_PPST4 _PPST.Bits.PPST4 -#define PPST_PPST5 _PPST.Bits.PPST5 -#define PPST_PPST6 _PPST.Bits.PPST6 -#define PPST_PPST7 _PPST.Bits.PPST7 -#define PPST_PPST _PPST.MergedBits.grpPPST - - -/*** MODRR - Module Routing Register; 0x00000247 ***/ -typedef union { - byte Byte; - struct { - byte MODRR0 :1; /* Module Routing Bit 0 */ - byte MODRR1 :1; /* Module Routing Bit 1 */ - byte MODRR2 :1; /* Module Routing Bit 2 */ - byte MODRR3 :1; /* Module Routing Bit 3 */ - byte MODRR4 :1; /* Module Routing Bit 4 */ - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpMODRR :5; - byte :1; - byte :1; - byte :1; - } MergedBits; -} MODRRSTR; -extern volatile MODRRSTR _MODRR @(REG_BASE + 0x00000247); -#define MODRR _MODRR.Byte -#define MODRR_MODRR0 _MODRR.Bits.MODRR0 -#define MODRR_MODRR1 _MODRR.Bits.MODRR1 -#define MODRR_MODRR2 _MODRR.Bits.MODRR2 -#define MODRR_MODRR3 _MODRR.Bits.MODRR3 -#define MODRR_MODRR4 _MODRR.Bits.MODRR4 -#define MODRR_MODRR _MODRR.MergedBits.grpMODRR - - -/*** PTS - Port S I/O Register; 0x00000248 ***/ -typedef union { - byte Byte; - struct { - byte PTS0 :1; /* Port S Bit 0 */ - byte PTS1 :1; /* Port S Bit 1 */ - byte PTS2 :1; /* Port S Bit 2 */ - byte PTS3 :1; /* Port S Bit 3 */ - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpPTS :4; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} PTSSTR; -extern volatile PTSSTR _PTS @(REG_BASE + 0x00000248); -#define PTS _PTS.Byte -#define PTS_PTS0 _PTS.Bits.PTS0 -#define PTS_PTS1 _PTS.Bits.PTS1 -#define PTS_PTS2 _PTS.Bits.PTS2 -#define PTS_PTS3 _PTS.Bits.PTS3 -#define PTS_PTS _PTS.MergedBits.grpPTS - - -/*** PTIS - Port S Input; 0x00000249 ***/ -typedef union { - byte Byte; - struct { - byte PTIS0 :1; /* Port S Bit 0 */ - byte PTIS1 :1; /* Port S Bit 1 */ - byte PTIS2 :1; /* Port S Bit 2 */ - byte PTIS3 :1; /* Port S Bit 3 */ - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpPTIS :4; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} PTISSTR; -extern volatile PTISSTR _PTIS @(REG_BASE + 0x00000249); -#define PTIS _PTIS.Byte -#define PTIS_PTIS0 _PTIS.Bits.PTIS0 -#define PTIS_PTIS1 _PTIS.Bits.PTIS1 -#define PTIS_PTIS2 _PTIS.Bits.PTIS2 -#define PTIS_PTIS3 _PTIS.Bits.PTIS3 -#define PTIS_PTIS _PTIS.MergedBits.grpPTIS - - -/*** DDRS - Port S Data Direction Register; 0x0000024A ***/ -typedef union { - byte Byte; - struct { - byte DDRS0 :1; /* Data Direction Port S Bit 0 */ - byte DDRS1 :1; /* Data Direction Port S Bit 1 */ - byte DDRS2 :1; /* Data Direction Port S Bit 2 */ - byte DDRS3 :1; /* Data Direction Port S Bit 3 */ - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpDDRS :4; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} DDRSSTR; -extern volatile DDRSSTR _DDRS @(REG_BASE + 0x0000024A); -#define DDRS _DDRS.Byte -#define DDRS_DDRS0 _DDRS.Bits.DDRS0 -#define DDRS_DDRS1 _DDRS.Bits.DDRS1 -#define DDRS_DDRS2 _DDRS.Bits.DDRS2 -#define DDRS_DDRS3 _DDRS.Bits.DDRS3 -#define DDRS_DDRS _DDRS.MergedBits.grpDDRS - - -/*** RDRS - Port S Reduced Drive Register; 0x0000024B ***/ -typedef union { - byte Byte; - struct { - byte RDRS0 :1; /* Reduced Drive Port S Bit 0 */ - byte RDRS1 :1; /* Reduced Drive Port S Bit 1 */ - byte RDRS2 :1; /* Reduced Drive Port S Bit 2 */ - byte RDRS3 :1; /* Reduced Drive Port S Bit 3 */ - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpRDRS :4; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} RDRSSTR; -extern volatile RDRSSTR _RDRS @(REG_BASE + 0x0000024B); -#define RDRS _RDRS.Byte -#define RDRS_RDRS0 _RDRS.Bits.RDRS0 -#define RDRS_RDRS1 _RDRS.Bits.RDRS1 -#define RDRS_RDRS2 _RDRS.Bits.RDRS2 -#define RDRS_RDRS3 _RDRS.Bits.RDRS3 -#define RDRS_RDRS _RDRS.MergedBits.grpRDRS - - -/*** PERS - Port S Pull Device Enable Register; 0x0000024C ***/ -typedef union { - byte Byte; - struct { - byte PERS0 :1; /* Pull Device Enable Port S Bit 0 */ - byte PERS1 :1; /* Pull Device Enable Port S Bit 1 */ - byte PERS2 :1; /* Pull Device Enable Port S Bit 2 */ - byte PERS3 :1; /* Pull Device Enable Port S Bit 3 */ - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpPERS :4; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} PERSSTR; -extern volatile PERSSTR _PERS @(REG_BASE + 0x0000024C); -#define PERS _PERS.Byte -#define PERS_PERS0 _PERS.Bits.PERS0 -#define PERS_PERS1 _PERS.Bits.PERS1 -#define PERS_PERS2 _PERS.Bits.PERS2 -#define PERS_PERS3 _PERS.Bits.PERS3 -#define PERS_PERS _PERS.MergedBits.grpPERS - - -/*** PPSS - Port S Polarity Select Register; 0x0000024D ***/ -typedef union { - byte Byte; - struct { - byte PPSS0 :1; /* Pull Select Port S Bit 0 */ - byte PPSS1 :1; /* Pull Select Port S Bit 1 */ - byte PPSS2 :1; /* Pull Select Port S Bit 2 */ - byte PPSS3 :1; /* Pull Select Port S Bit 3 */ - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpPPSS :4; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} PPSSSTR; -extern volatile PPSSSTR _PPSS @(REG_BASE + 0x0000024D); -#define PPSS _PPSS.Byte -#define PPSS_PPSS0 _PPSS.Bits.PPSS0 -#define PPSS_PPSS1 _PPSS.Bits.PPSS1 -#define PPSS_PPSS2 _PPSS.Bits.PPSS2 -#define PPSS_PPSS3 _PPSS.Bits.PPSS3 -#define PPSS_PPSS _PPSS.MergedBits.grpPPSS - - -/*** WOMS - Port S Wired-Or Mode Register; 0x0000024E ***/ -typedef union { - byte Byte; - struct { - byte WOMS0 :1; /* Wired-Or Mode Port S Bit 0 */ - byte WOMS1 :1; /* Wired-Or Mode Port S Bit 1 */ - byte WOMS2 :1; /* Wired-Or Mode Port S Bit 2 */ - byte WOMS3 :1; /* Wired-Or Mode Port S Bit 3 */ - byte :1; - byte :1; - byte :1; - byte :1; - } Bits; - struct { - byte grpWOMS :4; - byte :1; - byte :1; - byte :1; - byte :1; - } MergedBits; -} WOMSSTR; -extern volatile WOMSSTR _WOMS @(REG_BASE + 0x0000024E); -#define WOMS _WOMS.Byte -#define WOMS_WOMS0 _WOMS.Bits.WOMS0 -#define WOMS_WOMS1 _WOMS.Bits.WOMS1 -#define WOMS_WOMS2 _WOMS.Bits.WOMS2 -#define WOMS_WOMS3 _WOMS.Bits.WOMS3 -#define WOMS_WOMS _WOMS.MergedBits.grpWOMS - - -/*** PTM - Port M I/O Register; 0x00000250 ***/ -typedef union { - byte Byte; - struct { - byte PTM0 :1; /* Port T Bit 0 */ - byte PTM1 :1; /* Port T Bit 1 */ - byte PTM2 :1; /* Port T Bit 2 */ - byte PTM3 :1; /* Port T Bit 3 */ - byte PTM4 :1; /* Port T Bit 4 */ - byte PTM5 :1; /* Port T Bit 5 */ - byte :1; - byte :1; - } Bits; - struct { - byte grpPTM :6; - byte :1; - byte :1; - } MergedBits; -} PTMSTR; -extern volatile PTMSTR _PTM @(REG_BASE + 0x00000250); -#define PTM _PTM.Byte -#define PTM_PTM0 _PTM.Bits.PTM0 -#define PTM_PTM1 _PTM.Bits.PTM1 -#define PTM_PTM2 _PTM.Bits.PTM2 -#define PTM_PTM3 _PTM.Bits.PTM3 -#define PTM_PTM4 _PTM.Bits.PTM4 -#define PTM_PTM5 _PTM.Bits.PTM5 -#define PTM_PTM _PTM.MergedBits.grpPTM - - -/*** PTIM - Port M Input; 0x00000251 ***/ -typedef union { - byte Byte; - struct { - byte PTIM0 :1; /* Port M Bit 0 */ - byte PTIM1 :1; /* Port M Bit 1 */ - byte PTIM2 :1; /* Port M Bit 2 */ - byte PTIM3 :1; /* Port M Bit 3 */ - byte PTIM4 :1; /* Port M Bit 4 */ - byte PTIM5 :1; /* Port M Bit 5 */ - byte :1; - byte :1; - } Bits; - struct { - byte grpPTIM :6; - byte :1; - byte :1; - } MergedBits; -} PTIMSTR; -extern volatile PTIMSTR _PTIM @(REG_BASE + 0x00000251); -#define PTIM _PTIM.Byte -#define PTIM_PTIM0 _PTIM.Bits.PTIM0 -#define PTIM_PTIM1 _PTIM.Bits.PTIM1 -#define PTIM_PTIM2 _PTIM.Bits.PTIM2 -#define PTIM_PTIM3 _PTIM.Bits.PTIM3 -#define PTIM_PTIM4 _PTIM.Bits.PTIM4 -#define PTIM_PTIM5 _PTIM.Bits.PTIM5 -#define PTIM_PTIM _PTIM.MergedBits.grpPTIM - - -/*** DDRM - Port M Data Direction Register; 0x00000252 ***/ -typedef union { - byte Byte; - struct { - byte DDRM0 :1; /* Data Direction Port M Bit 0 */ - byte DDRM1 :1; /* Data Direction Port M Bit 1 */ - byte DDRM2 :1; /* Data Direction Port M Bit 2 */ - byte DDRM3 :1; /* Data Direction Port M Bit 3 */ - byte DDRM4 :1; /* Data Direction Port M Bit 4 */ - byte DDRM5 :1; /* Data Direction Port M Bit 5 */ - byte :1; - byte :1; - } Bits; - struct { - byte grpDDRM :6; - byte :1; - byte :1; - } MergedBits; -} DDRMSTR; -extern volatile DDRMSTR _DDRM @(REG_BASE + 0x00000252); -#define DDRM _DDRM.Byte -#define DDRM_DDRM0 _DDRM.Bits.DDRM0 -#define DDRM_DDRM1 _DDRM.Bits.DDRM1 -#define DDRM_DDRM2 _DDRM.Bits.DDRM2 -#define DDRM_DDRM3 _DDRM.Bits.DDRM3 -#define DDRM_DDRM4 _DDRM.Bits.DDRM4 -#define DDRM_DDRM5 _DDRM.Bits.DDRM5 -#define DDRM_DDRM _DDRM.MergedBits.grpDDRM - - -/*** RDRM - Port M Reduced Drive Register; 0x00000253 ***/ -typedef union { - byte Byte; - struct { - byte RDRM0 :1; /* Reduced Drive Port M Bit 0 */ - byte RDRM1 :1; /* Reduced Drive Port M Bit 1 */ - byte RDRM2 :1; /* Reduced Drive Port M Bit 2 */ - byte RDRM3 :1; /* Reduced Drive Port M Bit 3 */ - byte RDRM4 :1; /* Reduced Drive Port M Bit 4 */ - byte RDRM5 :1; /* Reduced Drive Port M Bit 5 */ - byte :1; - byte :1; - } Bits; - struct { - byte grpRDRM :6; - byte :1; - byte :1; - } MergedBits; -} RDRMSTR; -extern volatile RDRMSTR _RDRM @(REG_BASE + 0x00000253); -#define RDRM _RDRM.Byte -#define RDRM_RDRM0 _RDRM.Bits.RDRM0 -#define RDRM_RDRM1 _RDRM.Bits.RDRM1 -#define RDRM_RDRM2 _RDRM.Bits.RDRM2 -#define RDRM_RDRM3 _RDRM.Bits.RDRM3 -#define RDRM_RDRM4 _RDRM.Bits.RDRM4 -#define RDRM_RDRM5 _RDRM.Bits.RDRM5 -#define RDRM_RDRM _RDRM.MergedBits.grpRDRM - - -/*** PERM - Port M Pull Device Enable Register; 0x00000254 ***/ -typedef union { - byte Byte; - struct { - byte PERM0 :1; /* Pull Device Enable Port M Bit 0 */ - byte PERM1 :1; /* Pull Device Enable Port M Bit 1 */ - byte PERM2 :1; /* Pull Device Enable Port M Bit 2 */ - byte PERM3 :1; /* Pull Device Enable Port M Bit 3 */ - byte PERM4 :1; /* Pull Device Enable Port M Bit 4 */ - byte PERM5 :1; /* Pull Device Enable Port M Bit 5 */ - byte :1; - byte :1; - } Bits; - struct { - byte grpPERM :6; - byte :1; - byte :1; - } MergedBits; -} PERMSTR; -extern volatile PERMSTR _PERM @(REG_BASE + 0x00000254); -#define PERM _PERM.Byte -#define PERM_PERM0 _PERM.Bits.PERM0 -#define PERM_PERM1 _PERM.Bits.PERM1 -#define PERM_PERM2 _PERM.Bits.PERM2 -#define PERM_PERM3 _PERM.Bits.PERM3 -#define PERM_PERM4 _PERM.Bits.PERM4 -#define PERM_PERM5 _PERM.Bits.PERM5 -#define PERM_PERM _PERM.MergedBits.grpPERM - - -/*** PPSM - Port M Polarity Select Register; 0x00000255 ***/ -typedef union { - byte Byte; - struct { - byte PPSM0 :1; /* Pull Select Port M Bit 0 */ - byte PPSM1 :1; /* Pull Select Port M Bit 1 */ - byte PPSM2 :1; /* Pull Select Port M Bit 2 */ - byte PPSM3 :1; /* Pull Select Port M Bit 3 */ - byte PPSM4 :1; /* Pull Select Port M Bit 4 */ - byte PPSM5 :1; /* Pull Select Port M Bit 5 */ - byte :1; - byte :1; - } Bits; - struct { - byte grpPPSM :6; - byte :1; - byte :1; - } MergedBits; -} PPSMSTR; -extern volatile PPSMSTR _PPSM @(REG_BASE + 0x00000255); -#define PPSM _PPSM.Byte -#define PPSM_PPSM0 _PPSM.Bits.PPSM0 -#define PPSM_PPSM1 _PPSM.Bits.PPSM1 -#define PPSM_PPSM2 _PPSM.Bits.PPSM2 -#define PPSM_PPSM3 _PPSM.Bits.PPSM3 -#define PPSM_PPSM4 _PPSM.Bits.PPSM4 -#define PPSM_PPSM5 _PPSM.Bits.PPSM5 -#define PPSM_PPSM _PPSM.MergedBits.grpPPSM - - -/*** WOMM - Port M Wired-Or Mode Register; 0x00000256 ***/ -typedef union { - byte Byte; - struct { - byte WOMM0 :1; /* Wired-Or Mode Port M Bit 0 */ - byte WOMM1 :1; /* Wired-Or Mode Port M Bit 1 */ - byte WOMM2 :1; /* Wired-Or Mode Port M Bit 2 */ - byte WOMM3 :1; /* Wired-Or Mode Port M Bit 3 */ - byte WOMM4 :1; /* Wired-Or Mode Port M Bit 4 */ - byte WOMM5 :1; /* Wired-Or Mode Port M Bit 5 */ - byte :1; - byte :1; - } Bits; - struct { - byte grpWOMM :6; - byte :1; - byte :1; - } MergedBits; -} WOMMSTR; -extern volatile WOMMSTR _WOMM @(REG_BASE + 0x00000256); -#define WOMM _WOMM.Byte -#define WOMM_WOMM0 _WOMM.Bits.WOMM0 -#define WOMM_WOMM1 _WOMM.Bits.WOMM1 -#define WOMM_WOMM2 _WOMM.Bits.WOMM2 -#define WOMM_WOMM3 _WOMM.Bits.WOMM3 -#define WOMM_WOMM4 _WOMM.Bits.WOMM4 -#define WOMM_WOMM5 _WOMM.Bits.WOMM5 -#define WOMM_WOMM _WOMM.MergedBits.grpWOMM - - -/*** PTP - Port P I/O Register; 0x00000258 ***/ -typedef union { - byte Byte; - struct { - byte PTP0 :1; /* Port P Bit 0 */ - byte PTP1 :1; /* Port P Bit 1 */ - byte PTP2 :1; /* Port P Bit 2 */ - byte PTP3 :1; /* Port P Bit 3 */ - byte PTP4 :1; /* Port P Bit 4 */ - byte PTP5 :1; /* Port P Bit 5 */ - byte PTP6 :1; /* Port P Bit 6 */ - byte PTP7 :1; /* Port P Bit 7 */ - } Bits; - struct { - byte grpPTP :8; - } MergedBits; -} PTPSTR; -extern volatile PTPSTR _PTP @(REG_BASE + 0x00000258); -#define PTP _PTP.Byte -#define PTP_PTP0 _PTP.Bits.PTP0 -#define PTP_PTP1 _PTP.Bits.PTP1 -#define PTP_PTP2 _PTP.Bits.PTP2 -#define PTP_PTP3 _PTP.Bits.PTP3 -#define PTP_PTP4 _PTP.Bits.PTP4 -#define PTP_PTP5 _PTP.Bits.PTP5 -#define PTP_PTP6 _PTP.Bits.PTP6 -#define PTP_PTP7 _PTP.Bits.PTP7 -#define PTP_PTP _PTP.MergedBits.grpPTP - - -/*** PTIP - Port P Input; 0x00000259 ***/ -typedef union { - byte Byte; - struct { - byte PTIP0 :1; /* Port P Bit 0 */ - byte PTIP1 :1; /* Port P Bit 1 */ - byte PTIP2 :1; /* Port P Bit 2 */ - byte PTIP3 :1; /* Port P Bit 3 */ - byte PTIP4 :1; /* Port P Bit 4 */ - byte PTIP5 :1; /* Port P Bit 5 */ - byte PTIP6 :1; /* Port P Bit 6 */ - byte PTIP7 :1; /* Port P Bit 7 */ - } Bits; - struct { - byte grpPTIP :8; - } MergedBits; -} PTIPSTR; -extern volatile PTIPSTR _PTIP @(REG_BASE + 0x00000259); -#define PTIP _PTIP.Byte -#define PTIP_PTIP0 _PTIP.Bits.PTIP0 -#define PTIP_PTIP1 _PTIP.Bits.PTIP1 -#define PTIP_PTIP2 _PTIP.Bits.PTIP2 -#define PTIP_PTIP3 _PTIP.Bits.PTIP3 -#define PTIP_PTIP4 _PTIP.Bits.PTIP4 -#define PTIP_PTIP5 _PTIP.Bits.PTIP5 -#define PTIP_PTIP6 _PTIP.Bits.PTIP6 -#define PTIP_PTIP7 _PTIP.Bits.PTIP7 -#define PTIP_PTIP _PTIP.MergedBits.grpPTIP - - -/*** DDRP - Port P Data Direction Register; 0x0000025A ***/ -typedef union { - byte Byte; - struct { - byte DDRP0 :1; /* Data Direction Port P Bit 0 */ - byte DDRP1 :1; /* Data Direction Port P Bit 1 */ - byte DDRP2 :1; /* Data Direction Port P Bit 2 */ - byte DDRP3 :1; /* Data Direction Port P Bit 3 */ - byte DDRP4 :1; /* Data Direction Port P Bit 4 */ - byte DDRP5 :1; /* Data Direction Port P Bit 5 */ - byte DDRP6 :1; /* Data Direction Port P Bit 6 */ - byte DDRP7 :1; /* Data Direction Port P Bit 7 */ - } Bits; - struct { - byte grpDDRP :8; - } MergedBits; -} DDRPSTR; -extern volatile DDRPSTR _DDRP @(REG_BASE + 0x0000025A); -#define DDRP _DDRP.Byte -#define DDRP_DDRP0 _DDRP.Bits.DDRP0 -#define DDRP_DDRP1 _DDRP.Bits.DDRP1 -#define DDRP_DDRP2 _DDRP.Bits.DDRP2 -#define DDRP_DDRP3 _DDRP.Bits.DDRP3 -#define DDRP_DDRP4 _DDRP.Bits.DDRP4 -#define DDRP_DDRP5 _DDRP.Bits.DDRP5 -#define DDRP_DDRP6 _DDRP.Bits.DDRP6 -#define DDRP_DDRP7 _DDRP.Bits.DDRP7 -#define DDRP_DDRP _DDRP.MergedBits.grpDDRP - - -/*** RDRP - Port P Reduced Drive Register; 0x0000025B ***/ -typedef union { - byte Byte; - struct { - byte RDRP0 :1; /* Reduced Drive Port P Bit 0 */ - byte RDRP1 :1; /* Reduced Drive Port P Bit 1 */ - byte RDRP2 :1; /* Reduced Drive Port P Bit 2 */ - byte RDRP3 :1; /* Reduced Drive Port P Bit 3 */ - byte RDRP4 :1; /* Reduced Drive Port P Bit 4 */ - byte RDRP5 :1; /* Reduced Drive Port P Bit 5 */ - byte RDRP6 :1; /* Reduced Drive Port P Bit 6 */ - byte RDRP7 :1; /* Reduced Drive Port P Bit 7 */ - } Bits; - struct { - byte grpRDRP :8; - } MergedBits; -} RDRPSTR; -extern volatile RDRPSTR _RDRP @(REG_BASE + 0x0000025B); -#define RDRP _RDRP.Byte -#define RDRP_RDRP0 _RDRP.Bits.RDRP0 -#define RDRP_RDRP1 _RDRP.Bits.RDRP1 -#define RDRP_RDRP2 _RDRP.Bits.RDRP2 -#define RDRP_RDRP3 _RDRP.Bits.RDRP3 -#define RDRP_RDRP4 _RDRP.Bits.RDRP4 -#define RDRP_RDRP5 _RDRP.Bits.RDRP5 -#define RDRP_RDRP6 _RDRP.Bits.RDRP6 -#define RDRP_RDRP7 _RDRP.Bits.RDRP7 -#define RDRP_RDRP _RDRP.MergedBits.grpRDRP - - -/*** PERP - Port P Pull Device Enable Register; 0x0000025C ***/ -typedef union { - byte Byte; - struct { - byte PERP0 :1; /* Pull Device Enable Port P Bit 0 */ - byte PERP1 :1; /* Pull Device Enable Port P Bit 1 */ - byte PERP2 :1; /* Pull Device Enable Port P Bit 2 */ - byte PERP3 :1; /* Pull Device Enable Port P Bit 3 */ - byte PERP4 :1; /* Pull Device Enable Port P Bit 4 */ - byte PERP5 :1; /* Pull Device Enable Port P Bit 5 */ - byte PERP6 :1; /* Pull Device Enable Port P Bit 6 */ - byte PERP7 :1; /* Pull Device Enable Port P Bit 7 */ - } Bits; - struct { - byte grpPERP :8; - } MergedBits; -} PERPSTR; -extern volatile PERPSTR _PERP @(REG_BASE + 0x0000025C); -#define PERP _PERP.Byte -#define PERP_PERP0 _PERP.Bits.PERP0 -#define PERP_PERP1 _PERP.Bits.PERP1 -#define PERP_PERP2 _PERP.Bits.PERP2 -#define PERP_PERP3 _PERP.Bits.PERP3 -#define PERP_PERP4 _PERP.Bits.PERP4 -#define PERP_PERP5 _PERP.Bits.PERP5 -#define PERP_PERP6 _PERP.Bits.PERP6 -#define PERP_PERP7 _PERP.Bits.PERP7 -#define PERP_PERP _PERP.MergedBits.grpPERP - - -/*** PPSP - Port P Polarity Select Register; 0x0000025D ***/ -typedef union { - byte Byte; - struct { - byte PPSP0 :1; /* Pull Select Port P Bit 0 */ - byte PPSP1 :1; /* Pull Select Port P Bit 1 */ - byte PPSP2 :1; /* Pull Select Port P Bit 2 */ - byte PPSP3 :1; /* Pull Select Port P Bit 3 */ - byte PPSP4 :1; /* Pull Select Port P Bit 4 */ - byte PPSP5 :1; /* Pull Select Port P Bit 5 */ - byte PPSP6 :1; /* Pull Select Port P Bit 6 */ - byte PPSP7 :1; /* Pull Select Port P Bit 7 */ - } Bits; - struct { - byte grpPPSP :8; - } MergedBits; -} PPSPSTR; -extern volatile PPSPSTR _PPSP @(REG_BASE + 0x0000025D); -#define PPSP _PPSP.Byte -#define PPSP_PPSP0 _PPSP.Bits.PPSP0 -#define PPSP_PPSP1 _PPSP.Bits.PPSP1 -#define PPSP_PPSP2 _PPSP.Bits.PPSP2 -#define PPSP_PPSP3 _PPSP.Bits.PPSP3 -#define PPSP_PPSP4 _PPSP.Bits.PPSP4 -#define PPSP_PPSP5 _PPSP.Bits.PPSP5 -#define PPSP_PPSP6 _PPSP.Bits.PPSP6 -#define PPSP_PPSP7 _PPSP.Bits.PPSP7 -#define PPSP_PPSP _PPSP.MergedBits.grpPPSP - - -/*** PIEP - Port P Interrupt Enable Register; 0x0000025E ***/ -typedef union { - byte Byte; - struct { - byte PIEP0 :1; /* Interrupt Enable Port P Bit 0 */ - byte PIEP1 :1; /* Interrupt Enable Port P Bit 1 */ - byte PIEP2 :1; /* Interrupt Enable Port P Bit 2 */ - byte PIEP3 :1; /* Interrupt Enable Port P Bit 3 */ - byte PIEP4 :1; /* Interrupt Enable Port P Bit 4 */ - byte PIEP5 :1; /* Interrupt Enable Port P Bit 5 */ - byte PIEP6 :1; /* Interrupt Enable Port P Bit 6 */ - byte PIEP7 :1; /* Interrupt Enable Port P Bit 7 */ - } Bits; - struct { - byte grpPIEP :8; - } MergedBits; -} PIEPSTR; -extern volatile PIEPSTR _PIEP @(REG_BASE + 0x0000025E); -#define PIEP _PIEP.Byte -#define PIEP_PIEP0 _PIEP.Bits.PIEP0 -#define PIEP_PIEP1 _PIEP.Bits.PIEP1 -#define PIEP_PIEP2 _PIEP.Bits.PIEP2 -#define PIEP_PIEP3 _PIEP.Bits.PIEP3 -#define PIEP_PIEP4 _PIEP.Bits.PIEP4 -#define PIEP_PIEP5 _PIEP.Bits.PIEP5 -#define PIEP_PIEP6 _PIEP.Bits.PIEP6 -#define PIEP_PIEP7 _PIEP.Bits.PIEP7 -#define PIEP_PIEP _PIEP.MergedBits.grpPIEP - - -/*** PIFP - Port P Interrupt Flag Register; 0x0000025F ***/ -typedef union { - byte Byte; - struct { - byte PIFP0 :1; /* Interrupt Flags Port P Bit 0 */ - byte PIFP1 :1; /* Interrupt Flags Port P Bit 1 */ - byte PIFP2 :1; /* Interrupt Flags Port P Bit 2 */ - byte PIFP3 :1; /* Interrupt Flags Port P Bit 3 */ - byte PIFP4 :1; /* Interrupt Flags Port P Bit 4 */ - byte PIFP5 :1; /* Interrupt Flags Port P Bit 5 */ - byte PIFP6 :1; /* Interrupt Flags Port P Bit 6 */ - byte PIFP7 :1; /* Interrupt Flags Port P Bit 7 */ - } Bits; - struct { - byte grpPIFP :8; - } MergedBits; -} PIFPSTR; -extern volatile PIFPSTR _PIFP @(REG_BASE + 0x0000025F); -#define PIFP _PIFP.Byte -#define PIFP_PIFP0 _PIFP.Bits.PIFP0 -#define PIFP_PIFP1 _PIFP.Bits.PIFP1 -#define PIFP_PIFP2 _PIFP.Bits.PIFP2 -#define PIFP_PIFP3 _PIFP.Bits.PIFP3 -#define PIFP_PIFP4 _PIFP.Bits.PIFP4 -#define PIFP_PIFP5 _PIFP.Bits.PIFP5 -#define PIFP_PIFP6 _PIFP.Bits.PIFP6 -#define PIFP_PIFP7 _PIFP.Bits.PIFP7 -#define PIFP_PIFP _PIFP.MergedBits.grpPIFP - - -/*** PTJ - Port J I/O Register; 0x00000268 ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte PTJ6 :1; /* Port J Bit 6 */ - byte PTJ7 :1; /* Port J Bit 7 */ - } Bits; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte grpPTJ_6 :2; - } MergedBits; -} PTJSTR; -extern volatile PTJSTR _PTJ @(REG_BASE + 0x00000268); -#define PTJ _PTJ.Byte -#define PTJ_PTJ6 _PTJ.Bits.PTJ6 -#define PTJ_PTJ7 _PTJ.Bits.PTJ7 -#define PTJ_PTJ_6 _PTJ.MergedBits.grpPTJ_6 - - -/*** PTIJ - Port J Input Register; 0x00000269 ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte PTIJ6 :1; /* Port J Bit 6 */ - byte PTIJ7 :1; /* Port J Bit 7 */ - } Bits; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte grpPTIJ_6 :2; - } MergedBits; -} PTIJSTR; -extern volatile PTIJSTR _PTIJ @(REG_BASE + 0x00000269); -#define PTIJ _PTIJ.Byte -#define PTIJ_PTIJ6 _PTIJ.Bits.PTIJ6 -#define PTIJ_PTIJ7 _PTIJ.Bits.PTIJ7 -#define PTIJ_PTIJ_6 _PTIJ.MergedBits.grpPTIJ_6 - - -/*** DDRJ - Port J Data Direction Register; 0x0000026A ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte DDRJ6 :1; /* Data Direction Port J Bit 6 */ - byte DDRJ7 :1; /* Data Direction Port J Bit 7 */ - } Bits; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte grpDDRJ_6 :2; - } MergedBits; -} DDRJSTR; -extern volatile DDRJSTR _DDRJ @(REG_BASE + 0x0000026A); -#define DDRJ _DDRJ.Byte -#define DDRJ_DDRJ6 _DDRJ.Bits.DDRJ6 -#define DDRJ_DDRJ7 _DDRJ.Bits.DDRJ7 -#define DDRJ_DDRJ_6 _DDRJ.MergedBits.grpDDRJ_6 - - -/*** RDRJ - Port J Reduced Drive Register; 0x0000026B ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte RDRJ6 :1; /* Reduced Drive Port J Bit 6 */ - byte RDRJ7 :1; /* Reduced Drive Port J Bit 7 */ - } Bits; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte grpRDRJ_6 :2; - } MergedBits; -} RDRJSTR; -extern volatile RDRJSTR _RDRJ @(REG_BASE + 0x0000026B); -#define RDRJ _RDRJ.Byte -#define RDRJ_RDRJ6 _RDRJ.Bits.RDRJ6 -#define RDRJ_RDRJ7 _RDRJ.Bits.RDRJ7 -#define RDRJ_RDRJ_6 _RDRJ.MergedBits.grpRDRJ_6 - - -/*** PERJ - Port J Pull Device Enable Register; 0x0000026C ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte PERJ6 :1; /* Pull Device Enable Port J Bit 6 */ - byte PERJ7 :1; /* Pull Device Enable Port J Bit 7 */ - } Bits; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte grpPERJ_6 :2; - } MergedBits; -} PERJSTR; -extern volatile PERJSTR _PERJ @(REG_BASE + 0x0000026C); -#define PERJ _PERJ.Byte -#define PERJ_PERJ6 _PERJ.Bits.PERJ6 -#define PERJ_PERJ7 _PERJ.Bits.PERJ7 -#define PERJ_PERJ_6 _PERJ.MergedBits.grpPERJ_6 - - -/*** PPSJ - PortJP Polarity Select Register; 0x0000026D ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte PPSJ6 :1; /* Pull Select Port J Bit 6 */ - byte PPSJ7 :1; /* Pull Select Port J Bit 7 */ - } Bits; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte grpPPSJ_6 :2; - } MergedBits; -} PPSJSTR; -extern volatile PPSJSTR _PPSJ @(REG_BASE + 0x0000026D); -#define PPSJ _PPSJ.Byte -#define PPSJ_PPSJ6 _PPSJ.Bits.PPSJ6 -#define PPSJ_PPSJ7 _PPSJ.Bits.PPSJ7 -#define PPSJ_PPSJ_6 _PPSJ.MergedBits.grpPPSJ_6 - - -/*** PIEJ - Port J Interrupt Enable Register; 0x0000026E ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte PIEJ6 :1; /* Interrupt Enable Port J Bit 6 */ - byte PIEJ7 :1; /* Interrupt Enable Port J Bit 7 */ - } Bits; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte grpPIEJ_6 :2; - } MergedBits; -} PIEJSTR; -extern volatile PIEJSTR _PIEJ @(REG_BASE + 0x0000026E); -#define PIEJ _PIEJ.Byte -#define PIEJ_PIEJ6 _PIEJ.Bits.PIEJ6 -#define PIEJ_PIEJ7 _PIEJ.Bits.PIEJ7 -#define PIEJ_PIEJ_6 _PIEJ.MergedBits.grpPIEJ_6 - - -/*** PIFJ - Port J Interrupt Flag Register; 0x0000026F ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte PIFJ6 :1; /* Interrupt Flags Port J Bit 6 */ - byte PIFJ7 :1; /* Interrupt Flags Port J Bit 7 */ - } Bits; - struct { - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte :1; - byte grpPIFJ_6 :2; - } MergedBits; -} PIFJSTR; -extern volatile PIFJSTR _PIFJ @(REG_BASE + 0x0000026F); -#define PIFJ _PIFJ.Byte -#define PIFJ_PIFJ6 _PIFJ.Bits.PIFJ6 -#define PIFJ_PIFJ7 _PIFJ.Bits.PIFJ7 -#define PIFJ_PIFJ_6 _PIFJ.MergedBits.grpPIFJ_6 - - -/*** PTAD - Port AD I/O Register; 0x00000270 ***/ -typedef union { - byte Byte; - struct { - byte PTAD0 :1; /* Port AD Bit 0 */ - byte PTAD1 :1; /* Port AD Bit 1 */ - byte PTAD2 :1; /* Port AD Bit 2 */ - byte PTAD3 :1; /* Port AD Bit 3 */ - byte PTAD4 :1; /* Port AD Bit 4 */ - byte PTAD5 :1; /* Port AD Bit 5 */ - byte PTAD6 :1; /* Port AD Bit 6 */ - byte PTAD7 :1; /* Port AD Bit 7 */ - } Bits; - struct { - byte grpPTAD :8; - } MergedBits; -} PTADSTR; -extern volatile PTADSTR _PTAD @(REG_BASE + 0x00000270); -#define PTAD _PTAD.Byte -#define PTAD_PTAD0 _PTAD.Bits.PTAD0 -#define PTAD_PTAD1 _PTAD.Bits.PTAD1 -#define PTAD_PTAD2 _PTAD.Bits.PTAD2 -#define PTAD_PTAD3 _PTAD.Bits.PTAD3 -#define PTAD_PTAD4 _PTAD.Bits.PTAD4 -#define PTAD_PTAD5 _PTAD.Bits.PTAD5 -#define PTAD_PTAD6 _PTAD.Bits.PTAD6 -#define PTAD_PTAD7 _PTAD.Bits.PTAD7 -#define PTAD_PTAD _PTAD.MergedBits.grpPTAD - - -/*** PTIAD - Port AD Input Register; 0x00000271 ***/ -typedef union { - byte Byte; - struct { - byte PTIAD0 :1; /* Port AD Bit 0 */ - byte PTIAD1 :1; /* Port AD Bit 1 */ - byte PTIAD2 :1; /* Port AD Bit 2 */ - byte PTIAD3 :1; /* Port AD Bit 3 */ - byte PTIAD4 :1; /* Port AD Bit 4 */ - byte PTIAD5 :1; /* Port AD Bit 5 */ - byte PTIAD6 :1; /* Port AD Bit 6 */ - byte PTIAD7 :1; /* Port AD Bit 7 */ - } Bits; - struct { - byte grpPTIAD :8; - } MergedBits; -} PTIADSTR; -extern volatile PTIADSTR _PTIAD @(REG_BASE + 0x00000271); -#define PTIAD _PTIAD.Byte -#define PTIAD_PTIAD0 _PTIAD.Bits.PTIAD0 -#define PTIAD_PTIAD1 _PTIAD.Bits.PTIAD1 -#define PTIAD_PTIAD2 _PTIAD.Bits.PTIAD2 -#define PTIAD_PTIAD3 _PTIAD.Bits.PTIAD3 -#define PTIAD_PTIAD4 _PTIAD.Bits.PTIAD4 -#define PTIAD_PTIAD5 _PTIAD.Bits.PTIAD5 -#define PTIAD_PTIAD6 _PTIAD.Bits.PTIAD6 -#define PTIAD_PTIAD7 _PTIAD.Bits.PTIAD7 -#define PTIAD_PTIAD _PTIAD.MergedBits.grpPTIAD - - -/*** DDRAD - Port AD Data Direction Register; 0x00000272 ***/ -typedef union { - byte Byte; - struct { - byte DDRAD0 :1; /* Port AD Data Direction Bit 0 */ - byte DDRAD1 :1; /* Port AD Data Direction Bit 1 */ - byte DDRAD2 :1; /* Port AD Data Direction Bit 2 */ - byte DDRAD3 :1; /* Port AD Data Direction Bit 3 */ - byte DDRAD4 :1; /* Port AD Data Direction Bit 4 */ - byte DDRAD5 :1; /* Port AD Data Direction Bit 5 */ - byte DDRAD6 :1; /* Port AD Data Direction Bit 6 */ - byte DDRAD7 :1; /* Port AD Data Direction Bit 7 */ - } Bits; - struct { - byte grpDDRAD :8; - } MergedBits; -} DDRADSTR; -extern volatile DDRADSTR _DDRAD @(REG_BASE + 0x00000272); -#define DDRAD _DDRAD.Byte -#define DDRAD_DDRAD0 _DDRAD.Bits.DDRAD0 -#define DDRAD_DDRAD1 _DDRAD.Bits.DDRAD1 -#define DDRAD_DDRAD2 _DDRAD.Bits.DDRAD2 -#define DDRAD_DDRAD3 _DDRAD.Bits.DDRAD3 -#define DDRAD_DDRAD4 _DDRAD.Bits.DDRAD4 -#define DDRAD_DDRAD5 _DDRAD.Bits.DDRAD5 -#define DDRAD_DDRAD6 _DDRAD.Bits.DDRAD6 -#define DDRAD_DDRAD7 _DDRAD.Bits.DDRAD7 -#define DDRAD_DDRAD _DDRAD.MergedBits.grpDDRAD - - -/*** RDRAD - Port AD Reduced Drive Register; 0x00000273 ***/ -typedef union { - byte Byte; - struct { - byte RDRAD0 :1; /* Port AD Reduced Drive Bit 0 */ - byte RDRAD1 :1; /* Port AD Reduced Drive Bit 1 */ - byte RDRAD2 :1; /* Port AD Reduced Drive Bit 2 */ - byte RDRAD3 :1; /* Port AD Reduced Drive Bit 3 */ - byte RDRAD4 :1; /* Port AD Reduced Drive Bit 4 */ - byte RDRAD5 :1; /* Port AD Reduced Drive Bit 5 */ - byte RDRAD6 :1; /* Port AD Reduced Drive Bit 6 */ - byte RDRAD7 :1; /* Port AD Reduced Drive Bit 7 */ - } Bits; - struct { - byte grpRDRAD :8; - } MergedBits; -} RDRADSTR; -extern volatile RDRADSTR _RDRAD @(REG_BASE + 0x00000273); -#define RDRAD _RDRAD.Byte -#define RDRAD_RDRAD0 _RDRAD.Bits.RDRAD0 -#define RDRAD_RDRAD1 _RDRAD.Bits.RDRAD1 -#define RDRAD_RDRAD2 _RDRAD.Bits.RDRAD2 -#define RDRAD_RDRAD3 _RDRAD.Bits.RDRAD3 -#define RDRAD_RDRAD4 _RDRAD.Bits.RDRAD4 -#define RDRAD_RDRAD5 _RDRAD.Bits.RDRAD5 -#define RDRAD_RDRAD6 _RDRAD.Bits.RDRAD6 -#define RDRAD_RDRAD7 _RDRAD.Bits.RDRAD7 -#define RDRAD_RDRAD _RDRAD.MergedBits.grpRDRAD - - -/*** PERAD - Port AD Pull Device Enable Register; 0x00000274 ***/ -typedef union { - byte Byte; - struct { - byte PERAD0 :1; /* Port AD Pull Device Enable Bit 0 */ - byte PERAD1 :1; /* Port AD Pull Device Enable Bit 1 */ - byte PERAD2 :1; /* Port AD Pull Device Enable Bit 2 */ - byte PERAD3 :1; /* Port AD Pull Device Enable Bit 3 */ - byte PERAD4 :1; /* Port AD Pull Device Enable Bit 4 */ - byte PERAD5 :1; /* Port AD Pull Device Enable Bit 5 */ - byte PERAD6 :1; /* Port AD Pull Device Enable Bit 6 */ - byte PERAD7 :1; /* Port AD Pull Device Enable Bit 7 */ - } Bits; - struct { - byte grpPERAD :8; - } MergedBits; -} PERADSTR; -extern volatile PERADSTR _PERAD @(REG_BASE + 0x00000274); -#define PERAD _PERAD.Byte -#define PERAD_PERAD0 _PERAD.Bits.PERAD0 -#define PERAD_PERAD1 _PERAD.Bits.PERAD1 -#define PERAD_PERAD2 _PERAD.Bits.PERAD2 -#define PERAD_PERAD3 _PERAD.Bits.PERAD3 -#define PERAD_PERAD4 _PERAD.Bits.PERAD4 -#define PERAD_PERAD5 _PERAD.Bits.PERAD5 -#define PERAD_PERAD6 _PERAD.Bits.PERAD6 -#define PERAD_PERAD7 _PERAD.Bits.PERAD7 -#define PERAD_PERAD _PERAD.MergedBits.grpPERAD - - -/*** PPSAD - Port AD Polarity Select Register; 0x00000275 ***/ -typedef union { - byte Byte; - struct { - byte PPSAD0 :1; /* Port AD Polarity Select Bit 0 */ - byte PPSAD1 :1; /* Port AD Polarity Select Bit 1 */ - byte PPSAD2 :1; /* Port AD Polarity Select Bit 2 */ - byte PPSAD3 :1; /* Port AD Polarity Select Bit 3 */ - byte PPSAD4 :1; /* Port AD Polarity Select Bit 4 */ - byte PPSAD5 :1; /* Port AD Polarity Select Bit 5 */ - byte PPSAD6 :1; /* Port AD Polarity Select Bit 6 */ - byte PPSAD7 :1; /* Port AD Polarity Select Bit 7 */ - } Bits; - struct { - byte grpPPSAD :8; - } MergedBits; -} PPSADSTR; -extern volatile PPSADSTR _PPSAD @(REG_BASE + 0x00000275); -#define PPSAD _PPSAD.Byte -#define PPSAD_PPSAD0 _PPSAD.Bits.PPSAD0 -#define PPSAD_PPSAD1 _PPSAD.Bits.PPSAD1 -#define PPSAD_PPSAD2 _PPSAD.Bits.PPSAD2 -#define PPSAD_PPSAD3 _PPSAD.Bits.PPSAD3 -#define PPSAD_PPSAD4 _PPSAD.Bits.PPSAD4 -#define PPSAD_PPSAD5 _PPSAD.Bits.PPSAD5 -#define PPSAD_PPSAD6 _PPSAD.Bits.PPSAD6 -#define PPSAD_PPSAD7 _PPSAD.Bits.PPSAD7 -#define PPSAD_PPSAD _PPSAD.MergedBits.grpPPSAD - - -/*** BDMSTS - BDM Status Register; 0x0000FF01 ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte UNSEC :1; /* Unsecure */ - byte CLKSW :1; /* Clock switch */ - byte TRACE :1; /* TRACE1 BDM firmware command is being executed */ - byte SDV :1; /* Shift data valid */ - byte ENTAG :1; /* Tagging enable */ - byte BDMACT :1; /* BDM active status */ - byte ENBDM :1; /* Enable BDM */ - } Bits; -} BDMSTSSTR; -extern volatile BDMSTSSTR _BDMSTS @(0x0000FF01); -#define BDMSTS _BDMSTS.Byte -#define BDMSTS_UNSEC _BDMSTS.Bits.UNSEC -#define BDMSTS_CLKSW _BDMSTS.Bits.CLKSW -#define BDMSTS_TRACE _BDMSTS.Bits.TRACE -#define BDMSTS_SDV _BDMSTS.Bits.SDV -#define BDMSTS_ENTAG _BDMSTS.Bits.ENTAG -#define BDMSTS_BDMACT _BDMSTS.Bits.BDMACT -#define BDMSTS_ENBDM _BDMSTS.Bits.ENBDM - - -/*** BDMCCR - BDM CCR Holding Register; 0x0000FF06 ***/ -typedef union { - byte Byte; - struct { - byte CCR0 :1; /* BDM CCR Holding Bit 0 */ - byte CCR1 :1; /* BDM CCR Holding Bit 1 */ - byte CCR2 :1; /* BDM CCR Holding Bit 2 */ - byte CCR3 :1; /* BDM CCR Holding Bit 3 */ - byte CCR4 :1; /* BDM CCR Holding Bit 4 */ - byte CCR5 :1; /* BDM CCR Holding Bit 5 */ - byte CCR6 :1; /* BDM CCR Holding Bit 6 */ - byte CCR7 :1; /* BDM CCR Holding Bit 7 */ - } Bits; - struct { - byte grpCCR :8; - } MergedBits; -} BDMCCRSTR; -extern volatile BDMCCRSTR _BDMCCR @(0x0000FF06); -#define BDMCCR _BDMCCR.Byte -#define BDMCCR_CCR0 _BDMCCR.Bits.CCR0 -#define BDMCCR_CCR1 _BDMCCR.Bits.CCR1 -#define BDMCCR_CCR2 _BDMCCR.Bits.CCR2 -#define BDMCCR_CCR3 _BDMCCR.Bits.CCR3 -#define BDMCCR_CCR4 _BDMCCR.Bits.CCR4 -#define BDMCCR_CCR5 _BDMCCR.Bits.CCR5 -#define BDMCCR_CCR6 _BDMCCR.Bits.CCR6 -#define BDMCCR_CCR7 _BDMCCR.Bits.CCR7 -#define BDMCCR_CCR _BDMCCR.MergedBits.grpCCR - - -/*** BDMINR - BDM Internal Register Position Register; 0x0000FF07 ***/ -typedef union { - byte Byte; - struct { - byte :1; - byte :1; - byte :1; - byte REG11 :1; /* Internal register map position */ - byte REG12 :1; /* Internal register map position */ - byte REG13 :1; /* Internal register map position */ - byte REG14 :1; /* Internal register map position */ - byte REG15 :1; /* Internal register map position */ - } Bits; - struct { - byte :1; - byte :1; - byte :1; - byte grpREG_11 :5; - } MergedBits; -} BDMINRSTR; -extern volatile BDMINRSTR _BDMINR @(0x0000FF07); -#define BDMINR _BDMINR.Byte -#define BDMINR_REG11 _BDMINR.Bits.REG11 -#define BDMINR_REG12 _BDMINR.Bits.REG12 -#define BDMINR_REG13 _BDMINR.Bits.REG13 -#define BDMINR_REG14 _BDMINR.Bits.REG14 -#define BDMINR_REG15 _BDMINR.Bits.REG15 -#define BDMINR_REG_11 _BDMINR.MergedBits.grpREG_11 -#define BDMINR_REG BDMINR_REG_11 - - - /* Watchdog reset macro */ -#ifdef _lint - #define __RESET_WATCHDOG() /* empty */ -#else - #define __RESET_WATCHDOG() {asm sta COPCTL;} /* Just write a byte to feed the dog */ -#endif - -#endif - -/* -** ################################################################### -** -** This file was created by UNIS Processor Expert 03.33 for -** the Motorola HCS12 series of microcontrollers. -** -** ################################################################### -*/ - diff --git a/Demo/HCS12_CodeWarrior_small/CODE/PESL.h b/Demo/HCS12_CodeWarrior_small/CODE/PESL.h deleted file mode 100644 index 9f79f6868..000000000 --- a/Demo/HCS12_CodeWarrior_small/CODE/PESL.h +++ /dev/null @@ -1,52 +0,0 @@ -/* ================================================================================================================================= ** -** ================================================================================================================================= ** -** CONFIGURATION FILE FOR PESL LIBRARY ** -** ================================================================================================================================= ** -** ================================================================================================================================= */ - -#define _MC9S12A128_112 1 -#define _MC9S12A128_80 2 -#define _MC9S12A256_112 3 -#define _MC9S12A256_80 4 -#define _MC9S12A64_112 5 -#define _MC9S12A64_80 6 -#define _MC9S12C32_48 7 -#define _MC9S12C32_52 8 -#define _MC9S12C32_80 9 -#define _MC9S12D64_112 10 -#define _MC9S12D64_80 11 -#define _MC9S12DB128_112 12 -#define _MC9S12DG128_112 13 -#define _MC9S12DG128_80 14 -#define _MC9S12DG256_112 15 -#define _MC9S12DJ128_112 16 -#define _MC9S12DJ128_80 17 -#define _MC9S12DJ256_112 18 -#define _MC9S12DJ256_80 19 -#define _MC9S12DJ64_112 20 -#define _MC9S12DJ64_80 21 -#define _MC9S12DP256_112 22 -#define _MC9S12DT128_112 23 -#define _MC9S12DT256_112 24 -#define _MC9S12A32_80 25 -#define _MC9S12D32_80 26 -#define _MC9S12DP512_112 27 -#define _MC9S12A512_112 28 -#define _MC9S12E128_112 29 -#define _MC9S12E128_80 30 -#define _MC9S12E64_112 31 - - -/* Selected target MCU */ - -#define CPUtype _MC9S12C32_80 - - -/* PESL library */ - -#pragma MESSAGE DISABLE C4000 /* WARNING C4000: Condition is always TRUE */ -#pragma MESSAGE DISABLE C4001 /* WARNING C4001: Condition is always FALSE */ - -#include "PESLlib.h" - - diff --git a/Demo/HCS12_CodeWarrior_small/CODE/PE_Const.H b/Demo/HCS12_CodeWarrior_small/CODE/PE_Const.H deleted file mode 100644 index 2f0b2f1ca..000000000 --- a/Demo/HCS12_CodeWarrior_small/CODE/PE_Const.H +++ /dev/null @@ -1,50 +0,0 @@ -/** ################################################################### -** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. -** Filename : PE_Const.H -** Project : RTOSDemo -** Processor : MC9S12C32CFU -** Beantype : PE_Const -** Version : Driver 01.00 -** Compiler : Metrowerks HC12 C Compiler -** Date/Time : 10/05/2005, 11:11 -** Abstract : -** This bean "PE_Const" contains internal definitions -** of the constants. -** Settings : -** Contents : -** No public methods -** -** (c) Copyright UNIS, spol. s r.o. 1997-2002 -** UNIS, spol. s r.o. -** Jundrovska 33 -** 624 00 Brno -** Czech Republic -** http : www.processorexpert.com -** mail : info@processorexpert.com -** ###################################################################*/ - -#ifndef __PE_Const_H -#define __PE_Const_H - -/* Constants for detecting running mode */ -#define HIGH_SPEED 0 /* High speed */ -#define LOW_SPEED 1 /* Low speed */ -#define SLOW_SPEED 2 /* Slow speed */ - -/* Reset cause constants */ -#define RSTSRC_POR 1 /* Power-on reset */ -#define RSTSRC_PIN 8 /* External reset bit */ -#define RSTSRC_COP 4 /* COP reset */ -#define RSTSRC_ILOP 2 /* Illegal opcode reset */ -#define RSTSRC_ILAD 16 /* Illegal address reset */ -#define RSTSRC_LVI 32 /* Low voltage inhibit reset */ - -#endif /* _PE_Const_H */ -/* -** ################################################################### -** -** This file was created by UNIS Processor Expert 03.33 for -** the Motorola HCS12 series of microcontrollers. -** -** ################################################################### -*/ diff --git a/Demo/HCS12_CodeWarrior_small/CODE/PE_Error.H b/Demo/HCS12_CodeWarrior_small/CODE/PE_Error.H deleted file mode 100644 index 2025f4e0a..000000000 --- a/Demo/HCS12_CodeWarrior_small/CODE/PE_Error.H +++ /dev/null @@ -1,53 +0,0 @@ -/** ################################################################### -** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. -** Filename : PE_Error.H -** Project : RTOSDemo -** Processor : MC9S12C32CFU -** Beantype : PE_Error -** Version : Driver 01.00 -** Compiler : Metrowerks HC12 C Compiler -** Date/Time : 10/05/2005, 11:11 -** Abstract : -** This bean "PE_Error" contains internal definitions -** of the error constants. -** Settings : -** Contents : -** No public methods -** -** (c) Copyright UNIS, spol. s r.o. 1997-2002 -** UNIS, spol. s r.o. -** Jundrovska 33 -** 624 00 Brno -** Czech Republic -** http : www.processorexpert.com -** mail : info@processorexpert.com -** ###################################################################*/ - -#ifndef __PE_Error_H -#define __PE_Error_H - -#define ERR_OK 0 /* OK */ -#define ERR_SPEED 1 /* This device does not work in the active speed mode. */ -#define ERR_RANGE 2 /* Parameter out of range. */ -#define ERR_VALUE 3 /* Parameter of incorrect value. */ -#define ERR_OVERFLOW 4 /* Timer overflow. */ -#define ERR_MATH 5 /* Overflow during evaluation. */ -#define ERR_ENABLED 6 /* Device is enabled. */ -#define ERR_DISABLED 7 /* Device is disabled. */ -#define ERR_BUSY 8 /* Device is busy. */ -#define ERR_NOTAVAIL 9 /* Requested value or method not available. */ -#define ERR_RXEMPTY 10 /* No data in receiver. */ -#define ERR_TXFULL 11 /* Transmitter is full. */ -#define ERR_BUSOFF 12 /* Bus not available. */ -#define ERR_OVERRUN 13 /* Overrun error is detected. */ -#define ERR_FRAMING 14 /* Framing error is detected. */ -#define ERR_PARITY 15 /* Parity error is detected. */ -#define ERR_NOISE 16 /* Noise error is detected. */ -#define ERR_IDLE 17 /* Idle error is detectes. */ -#define ERR_FAULT 18 /* Fault error is detected. */ -#define ERR_BREAK 19 /* Break char is received during communication. */ -#define ERR_CRC 20 /* CRC error is detected. */ -#define ERR_ARBITR 21 /* A node losts arbitration. This error occurs if two nodes start transmission at the same time. */ -#define ERR_PROTECT 22 /* Protection error is detected. */ - -#endif __PE_Error_H diff --git a/Demo/HCS12_CodeWarrior_small/CODE/PE_Timer.C b/Demo/HCS12_CodeWarrior_small/CODE/PE_Timer.C deleted file mode 100644 index 3618734f6..000000000 --- a/Demo/HCS12_CodeWarrior_small/CODE/PE_Timer.C +++ /dev/null @@ -1,69 +0,0 @@ -/** ################################################################### -** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. -** Filename : PE_Timer.C -** Project : RTOSDemo -** Processor : MC9S12C32CFU -** Beantype : PE_Timer -** Version : Driver 01.00 -** Compiler : Metrowerks HC12 C Compiler -** Date/Time : 17/05/2005, 08:44 -** Abstract : -** This bean "PE_Timer" implements internal methods and definitions -** used by beans working with timers. -** Settings : -** Contents : -** No public methods -** -** (c) Copyright UNIS, spol. s r.o. 1997-2002 -** UNIS, spol. s r.o. -** Jundrovska 33 -** 624 00 Brno -** Czech Republic -** http : www.processorexpert.com -** mail : info@processorexpert.com -** ###################################################################*/ - - -/* MODULE PE_Timer. */ - -#include "PE_Timer.h" - - -/* -** =================================================================== -** Method : PE_Timer_LngHi1 (bean PE_Timer) -** -** Description : -** This method is internal. It is used by Processor Expert -** only. -** =================================================================== -*/ -bool PE_Timer_LngHi1(dword High, dword Low, word *Out) -{ - if ((High == 0) && ((Low >> 24) == 0)) - if ((Low & 0x80) != 0) { - if ((Low >> 8) < 0xFFFF) { - *Out = ((unsigned int)(Low >> 8))+1; - return FALSE; - } - } - else { - *Out = (unsigned int)(Low >> 8); - return FALSE; - } - *Out = (unsigned int)(Low >> 8); - return TRUE; -} - - - -/* END PE_Timer. */ - -/* -** ################################################################### -** -** This file was created by UNIS Processor Expert 03.33 for -** the Motorola HCS12 series of microcontrollers. -** -** ################################################################### -*/ diff --git a/Demo/HCS12_CodeWarrior_small/CODE/PE_Timer.H b/Demo/HCS12_CodeWarrior_small/CODE/PE_Timer.H deleted file mode 100644 index 1ec107559..000000000 --- a/Demo/HCS12_CodeWarrior_small/CODE/PE_Timer.H +++ /dev/null @@ -1,53 +0,0 @@ -/** ################################################################### -** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. -** Filename : PE_Timer.H -** Project : RTOSDemo -** Processor : MC9S12C32CFU -** Beantype : PE_Timer -** Version : Driver 01.00 -** Compiler : Metrowerks HC12 C Compiler -** Date/Time : 17/05/2005, 08:44 -** Abstract : -** This bean "PE_Timer" implements internal methods and definitions -** used by beans working with timers. -** Settings : -** Contents : -** No public methods -** -** (c) Copyright UNIS, spol. s r.o. 1997-2002 -** UNIS, spol. s r.o. -** Jundrovska 33 -** 624 00 Brno -** Czech Republic -** http : www.processorexpert.com -** mail : info@processorexpert.com -** ###################################################################*/ -#ifndef __PE_Timer -#define __PE_Timer -/*Include shared modules, which are used for whole project*/ -#include "PE_types.h" -#include "PE_const.h" - -/* MODULE PE_Timer. */ - -bool PE_Timer_LngHi1(dword Low, dword High, word *Out); -/* -** =================================================================== -** Method : PE_Timer_LngHi1 (bean PE_Timer) -** -** Description : -** This method is internal. It is used by Processor Expert -** only. -** =================================================================== -*/ - - -#endif /* END PE_Timer. */ -/* -** ################################################################### -** -** This file was created by UNIS Processor Expert 03.33 for -** the Motorola HCS12 series of microcontrollers. -** -** ################################################################### -*/ diff --git a/Demo/HCS12_CodeWarrior_small/CODE/PE_Types.H b/Demo/HCS12_CodeWarrior_small/CODE/PE_Types.H deleted file mode 100644 index 42c849ebd..000000000 --- a/Demo/HCS12_CodeWarrior_small/CODE/PE_Types.H +++ /dev/null @@ -1,87 +0,0 @@ -/** ################################################################### -** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. -** Filename : PE_Types.H -** Project : RTOSDemo -** Processor : MC9S12C32CFU -** Beantype : PE_Types -** Version : Driver 01.04 -** Compiler : Metrowerks HC12 C Compiler -** Date/Time : 10/05/2005, 11:11 -** Abstract : -** This bean "PE_Types" contains internal definitions -** of the types. -** Settings : -** Contents : -** No public methods -** -** (c) Copyright UNIS, spol. s r.o. 1997-2002 -** UNIS, spol. s r.o. -** Jundrovska 33 -** 624 00 Brno -** Czech Republic -** http : www.processorexpert.com -** mail : info@processorexpert.com -** ###################################################################*/ - -#ifndef __PE_Types_H -#define __PE_Types_H - -#define FALSE 0 -#define TRUE 1 - -/*Types definition*/ -typedef unsigned char bool; -typedef unsigned char byte; -typedef unsigned int word; -typedef unsigned long dword; -typedef unsigned long dlong[2]; -typedef void (*tIntFunc)(void); - -/* Motorola types */ -typedef unsigned char VUINT8; -typedef signed char VINT8; -typedef unsigned short int VUINT16; -typedef signed short int VINT16; -typedef unsigned long int VUINT32; - -#define in16(var,l,h) var = ((word)(l)) | (((word)(h)) << 8) -#define out16(l,h,val) { l = (byte)val; h = (byte)(val >> 8); } - -#define output(P, V) P = (V) -#define input(P) (P) - -#define __DI() { asm sei; } /* Disable global interrupts */ -#define __EI() { asm cli; } /* Enable global interrupts */ -#define EnterCritical() { __asm pshc; __asm sei; __asm movb 1,SP+,CCR_reg; } /* This macro is used by Processor Expert. It saves CCR register and disable global interrupts. */ -#define ExitCritical() { __asm movb CCR_reg, 1,-SP; __asm pulc; } /* This macro is used by Processor Expert. It restores CCR register saved in SaveStatusReg(). */ -/* obsolete definition for backward compatibility */ -#define SaveStatusReg() EnterCritical() -#define RestoreStatusReg() ExitCritical() - - -typedef struct { /* Black&White Image */ - word width; /* Image width */ - word height; /* Image height */ - byte *pixmap; /* Image pixel bitmap */ - word size; /* Image size */ - char *name; /* Image name */ -} TIMAGE; -typedef TIMAGE* PIMAGE ; /* Pointer to image */ - -/* 16-bit register (Motorola format - big endian) */ -typedef union { - word w; - struct { - byte high,low; - } b; -} TWREG; - -#endif /* __PE_Types_H */ -/* -** ################################################################### -** -** This file was created by UNIS Processor Expert 03.33 for -** the Motorola HCS12 series of microcontrollers. -** -** ################################################################### -*/ diff --git a/Demo/HCS12_CodeWarrior_small/CODE/RTOSDemo.C b/Demo/HCS12_CodeWarrior_small/CODE/RTOSDemo.C deleted file mode 100644 index 95899d4ea..000000000 --- a/Demo/HCS12_CodeWarrior_small/CODE/RTOSDemo.C +++ /dev/null @@ -1,66 +0,0 @@ -/** ################################################################### -** Filename : RTOSDemo.C -** Project : RTOSDemo -** Processor : MC9S12C32CFU -** Version : Driver 01.05 -** Compiler : Metrowerks HC12 C Compiler -** Date/Time : 10/05/2005, 11:11 -** Abstract : -** Main module. -** Here is to be placed user's code. -** Settings : -** Contents : -** No public methods -** -** (c) Copyright UNIS, spol. s r.o. 1997-2002 -** UNIS, spol. s r.o. -** Jundrovska 33 -** 624 00 Brno -** Czech Republic -** http : www.processorexpert.com -** mail : info@processorexpert.com -** ###################################################################*/ -/* MODULE RTOSDemo */ - -/* Including used modules for compilling procedure */ -#include "Cpu.h" -#include "Events.h" -#include "Byte1.h" -#include "TickTimer.h" -#include "ButtonInterrupt.h" -/* Include shared modules, which are used for whole project */ -#include "PE_Types.h" -#include "PE_Error.h" -#include "PE_Const.h" -#include "IO_Map.h" - -extern void vMain( void ); - -void main(void) -{ - /*** Processor Expert internal initialization. DON'T REMOVE THIS CODE!!! ***/ - PE_low_level_init(); - /*** End of Processor Expert internal initialization. ***/ - - /*Write your code here*/ - - /* Just jump to the real main(). */ - __asm - { - jmp vMain - } - - /*** Processor Expert end of main routine. DON'T MODIFY THIS CODE!!! ***/ - for(;;); - /*** Processor Expert end of main routine. DON'T WRITE CODE BELOW!!! ***/ -} /*** End of main routine. DO NOT MODIFY THIS TEXT!!! ***/ - -/* END RTOSDemo */ -/* -** ################################################################### -** -** This file was created by UNIS Processor Expert 03.33 for -** the Motorola HCS12 series of microcontrollers. -** -** ################################################################### -*/ diff --git a/Demo/HCS12_CodeWarrior_small/CODE/RTOSDemo.PRM b/Demo/HCS12_CodeWarrior_small/CODE/RTOSDemo.PRM deleted file mode 100644 index cfa3147fd..000000000 --- a/Demo/HCS12_CodeWarrior_small/CODE/RTOSDemo.PRM +++ /dev/null @@ -1,48 +0,0 @@ -/* -** ################################################################### -** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. -** Filename : RTOSDemo.PRM -** Project : RTOSDemo -** Processor : MC9S12C32CFU -** Compiler : Metrowerks HC12 C Compiler -** Date/Time : 18/06/2005, 18:00 -** Abstract : -** This file is used by the linker. It describes files to be linked, -** memory ranges, stack size, etc. For detailed description of the PRM file -** see CodeWarrior documentation. This file is generated by default. -** You can switch off generation by setting the property -** "Generate PRM file = no" on the "Build options" tab in CPU bean and then modify -** this file if needed. -** -** (c) Copyright UNIS, spol. s r.o. 1997-2002 -** UNIS, spol. s r.o. -** Jundrovska 33 -** 624 00 Brno -** Czech Republic -** http : www.processorexpert.com -** mail : info@processorexpert.com -** ################################################################### -*/ - -NAMES - -END - -SECTIONS - /* List of all sections specified on the "Build options" tab */ - RAM = READ_WRITE 0x00000800 TO 0x00000FFF; - ROM_C000 = READ_ONLY 0x0000C000 TO 0x0000FF7F; - ROM_4000 = READ_ONLY 0x00004000 TO 0x00007FFF; -END - -PLACEMENT - DEFAULT_RAM INTO RAM; - _PRESTART, STARTUP, - ROM_VAR, STRINGS, - NON_BANKED, DEFAULT_ROM, COPY INTO ROM_C000, ROM_4000; -END - -INIT _EntryPoint /* The entry point of the application. This function is generated into the CPU module. */ - -STACKSIZE 0x0030 /* Size of the system stack. Value can be changed on the "Build options" tab */ - diff --git a/Demo/HCS12_CodeWarrior_small/CODE/TickTimer.C b/Demo/HCS12_CodeWarrior_small/CODE/TickTimer.C deleted file mode 100644 index d00bb65cc..000000000 --- a/Demo/HCS12_CodeWarrior_small/CODE/TickTimer.C +++ /dev/null @@ -1,243 +0,0 @@ -/** ################################################################### -** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. -** Filename : TickTimer.C -** Project : RTOSDemo -** Processor : MC9S12C32CFU -** Beantype : TimerInt -** Version : Bean 02.063, Driver 01.05, CPU db: 2.87.276 -** Compiler : Metrowerks HC12 C Compiler -** Date/Time : 18/06/2005, 17:53 -** Abstract : -** This bean "TimerInt" implements a periodic interrupt. -** When the bean and its events are enabled, the "OnInterrupt" -** event is called periodically with the period that you specify. -** TimerInt supports also changing the period in runtime. -** The source of periodic interrupt can be timer compare or reload -** register or timer-overflow interrupt (of free running counter). -** Settings : -** Timer name : TIM (16-bit) -** Compare name : TC0 -** Counter shared : No -** -** High-speed CPU mode -** Prescaler : divide-by-4 -** Clock : 5999000 Hz -** Initial period/frequency -** Xtal ticks : 16000 -** microseconds : 1000 -** milliseconds : 1 -** seconds (real) : 0.0010000 -** Hz : 1000 -** kHz : 1 -** -** Runtime setting : period/frequency interval (continual setting) -** ticks : 16000 to 160000 ticks -** microseconds : 1000 to 10000 microseconds -** milliseconds : 1 to 10 milliseconds -** seconds (real) : 0.0010000 to 0.0100000 seconds -** Hz : 100 to 1000 Hz -** -** Initialization: -** Timer : Disabled -** Events : Enabled -** -** Timer registers -** Counter : TCNT [68] -** Mode : TIOS [64] -** Run : TSCR1 [70] -** Prescaler : TSCR2 [77] -** -** Compare registers -** Compare : TC0 [80] -** -** Flip-flop registers -** Mode : TCTL2 [73] -** Contents : -** Enable - byte TickTimer_Enable(void); -** SetFreqHz - byte TickTimer_SetFreqHz(word Freq); -** -** (c) Copyright UNIS, spol. s r.o. 1997-2002 -** UNIS, spol. s r.o. -** Jundrovska 33 -** 624 00 Brno -** Czech Republic -** http : www.processorexpert.com -** mail : info@processorexpert.com -** ###################################################################*/ - - -/* MODULE TickTimer. */ - -#include "Events.h" -#include "TickTimer.h" - -/* Definition of DATA and CODE segments for this bean. User can specify where - these segments will be located on "Build options" tab of the selected CPU bean. */ -#pragma DATA_SEG TickTimer_DATA /* Data section for this module. */ -#pragma CODE_SEG TickTimer_CODE /* Code section for this module. */ - -static bool EnUser; /* Enable/Disable device by user */ -static word CmpHighVal; /* Compare register value for high speed CPU mode */ - - -/* -** =================================================================== -** Method : SetCV (bean TimerInt) -** -** Description : -** This method is internal. It is used by Processor Expert -** only. -** =================================================================== -*/ -static void SetCV(word Val) -{ - if (Val == 0) /* If the given value is zero */ - Val = 65535; /* then change it to the maximal one */ - TC0 = Val; /* Store given value to the compare register */ - TC7 = Val; /* Store given value to the modulo register */ -} - -/* -** =================================================================== -** Method : SetPV (bean TimerInt) -** -** Description : -** This method is internal. It is used by Processor Expert -** only. -** =================================================================== -*/ -static void SetPV(byte Val) -{ - TSCR2_PR = Val; /* Store given value to the prescaler */ -} - -/* -** =================================================================== -** Method : HWEnDi (bean TimerInt) -** -** Description : -** This method is internal. It is used by Processor Expert -** only. -** =================================================================== -*/ -static void HWEnDi(void) -{ - if (EnUser) { /* Enable device? */ - TFLG1 = 1; /* Reset interrupt request flag */ - TIE_C0I = 1; /* Enable interrupt */ - } - else { /* Disable device? */ - TIE_C0I = 0; /* Disable interrupt */ - } -} - -/* -** =================================================================== -** Method : TickTimer_Enable (bean TimerInt) -** -** Description : -** Enable the bean - it starts the timer. Events may be -** generated ("DisableEvent"/"EnableEvent"). -** Parameters : None -** Returns : -** --- - Error code, possible codes: -** ERR_OK - OK -** ERR_SPEED - This device does not work in -** the active speed mode -** =================================================================== -*/ -byte TickTimer_Enable(void) -{ - if (!EnUser) { /* Is the device disabled by user? */ - EnUser = TRUE; /* If yes then set the flag "device enabled" */ - HWEnDi(); /* Enable the device */ - } - return ERR_OK; /* OK */ -} - -/* -** =================================================================== -** Method : TickTimer_SetFreqHz (bean TimerInt) -** -** Description : -** This method sets the new frequency of the generated -** events. The frequency is expressed in Hz as a 16-bit -** unsigned integer number. -** This method is available only if runtime setting type -** 'from interval' is selected in the Timing dialog box in -** Runtime setting area. -** Parameters : -** NAME - DESCRIPTION -** Freq - Frequency to set [in Hz] -** (100 to 1000 Hz) -** Returns : -** --- - Error code, possible codes: -** ERR_OK - OK -** ERR_SPEED - This device does not work in -** the active speed mode -** ERR_MATH - Overflow during evaluation -** ERR_RANGE - Parameter out of range -** =================================================================== -*/ -byte TickTimer_SetFreqHz(word Freq) -{ - dlong rtval; /* Result of two 32-bit numbers division */ - word rtword; /* Result of 64-bit number division */ - - if ((Freq > 1000) || (Freq < 100)) /* Is the given value out of range? */ - return ERR_RANGE; /* If yes then error */ - rtval[1] = 1535744000 / (dword)Freq; /* Divide high speed CPU mode coefficient by the given value */ - rtval[0] = 0; /* Convert result to the type dlong */ - if (PE_Timer_LngHi1(rtval[0],rtval[1],&rtword)) /* Is the result greater or equal than 65536 ? */ - rtword = 65535; /* If yes then use maximal possible value */ - CmpHighVal = rtword; /* Store result (compare register value for high speed CPU mode) to the variable CmpHighVal */ - SetCV(CmpHighVal); /* Store appropriate value to the compare register according to the selected high speed CPU mode */ - return ERR_OK; /* OK */ -} - -/* -** =================================================================== -** Method : TickTimer_Init (bean TimerInt) -** -** Description : -** This method is internal. It is used by Processor Expert -** only. -** =================================================================== -*/ -void TickTimer_Init(void) -{ - CmpHighVal = 5999; /* Compare register value for high speed CPU mode */ - EnUser = FALSE; /* Disable device */ - SetCV(CmpHighVal); /* Store appropriate value to the compare register according to the selected high speed CPU mode */ - SetPV(2); /* Set prescaler register according to the selected high speed CPU mode */ - HWEnDi(); /* Enable/disable device according to status flags */ -} - -/* -** =================================================================== -** Method : TickTimer_Interrupt (bean TimerInt) -** -** Description : -** This method is internal. It is used by Processor Expert -** only. -** =================================================================== -*/ -#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */ -__interrupt void TickTimer_Interrupt(void) -{ - TFLG1 = 1; /* Reset interrupt request flag */ - vTaskTickInterrupt(); /* Invoke user event */ -} - -#pragma CODE_SEG TickTimer_CODE /* Code section for this module. */ - -/* END TickTimer. */ - -/* -** ################################################################### -** -** This file was created by UNIS Processor Expert 03.33 for -** the Motorola HCS12 series of microcontrollers. -** -** ################################################################### -*/ diff --git a/Demo/HCS12_CodeWarrior_small/CODE/TickTimer.H b/Demo/HCS12_CodeWarrior_small/CODE/TickTimer.H deleted file mode 100644 index f0818fd9e..000000000 --- a/Demo/HCS12_CodeWarrior_small/CODE/TickTimer.H +++ /dev/null @@ -1,160 +0,0 @@ -/** ################################################################### -** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. -** Filename : TickTimer.H -** Project : RTOSDemo -** Processor : MC9S12C32CFU -** Beantype : TimerInt -** Version : Bean 02.063, Driver 01.05, CPU db: 2.87.276 -** Compiler : Metrowerks HC12 C Compiler -** Date/Time : 18/06/2005, 17:53 -** Abstract : -** This bean "TimerInt" implements a periodic interrupt. -** When the bean and its events are enabled, the "OnInterrupt" -** event is called periodically with the period that you specify. -** TimerInt supports also changing the period in runtime. -** The source of periodic interrupt can be timer compare or reload -** register or timer-overflow interrupt (of free running counter). -** Settings : -** Timer name : TIM (16-bit) -** Compare name : TC0 -** Counter shared : No -** -** High-speed CPU mode -** Prescaler : divide-by-4 -** Clock : 5999000 Hz -** Initial period/frequency -** Xtal ticks : 16000 -** microseconds : 1000 -** milliseconds : 1 -** seconds (real) : 0.0010000 -** Hz : 1000 -** kHz : 1 -** -** Runtime setting : period/frequency interval (continual setting) -** ticks : 16000 to 160000 ticks -** microseconds : 1000 to 10000 microseconds -** milliseconds : 1 to 10 milliseconds -** seconds (real) : 0.0010000 to 0.0100000 seconds -** Hz : 100 to 1000 Hz -** -** Initialization: -** Timer : Disabled -** Events : Enabled -** -** Timer registers -** Counter : TCNT [68] -** Mode : TIOS [64] -** Run : TSCR1 [70] -** Prescaler : TSCR2 [77] -** -** Compare registers -** Compare : TC0 [80] -** -** Flip-flop registers -** Mode : TCTL2 [73] -** Contents : -** Enable - byte TickTimer_Enable(void); -** SetFreqHz - byte TickTimer_SetFreqHz(word Freq); -** -** (c) Copyright UNIS, spol. s r.o. 1997-2002 -** UNIS, spol. s r.o. -** Jundrovska 33 -** 624 00 Brno -** Czech Republic -** http : www.processorexpert.com -** mail : info@processorexpert.com -** ###################################################################*/ - -#ifndef __TickTimer -#define __TickTimer - -/* MODULE TickTimer. */ - -#include "Cpu.h" - -#pragma CODE_SEG TickTimer_CODE /* Code section for this module. */ - -#define TickTimer_SFHzMin 100 /* Lower bound of interval for method SetFreqHz */ -#define TickTimer_SFHzMax 1000 /* Upper bound of interval for method SetFreqHz */ - - -byte TickTimer_Enable(void); -/* -** =================================================================== -** Method : TickTimer_Enable (bean TimerInt) -** -** Description : -** Enable the bean - it starts the timer. Events may be -** generated ("DisableEvent"/"EnableEvent"). -** Parameters : None -** Returns : -** --- - Error code, possible codes: -** ERR_OK - OK -** ERR_SPEED - This device does not work in -** the active speed mode -** =================================================================== -*/ - -byte TickTimer_SetFreqHz(word Freq); -/* -** =================================================================== -** Method : TickTimer_SetFreqHz (bean TimerInt) -** -** Description : -** This method sets the new frequency of the generated -** events. The frequency is expressed in Hz as a 16-bit -** unsigned integer number. -** This method is available only if runtime setting type -** 'from interval' is selected in the Timing dialog box in -** Runtime setting area. -** Parameters : -** NAME - DESCRIPTION -** Freq - Frequency to set [in Hz] -** (100 to 1000 Hz) -** Returns : -** --- - Error code, possible codes: -** ERR_OK - OK -** ERR_SPEED - This device does not work in -** the active speed mode -** ERR_MATH - Overflow during evaluation -** ERR_RANGE - Parameter out of range -** =================================================================== -*/ - -#pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */ -__interrupt void TickTimer_Interrupt(void); -#pragma CODE_SEG TickTimer_CODE /* Code section for this module. */ -/* -** =================================================================== -** Method : TickTimer_Interrupt (bean TimerInt) -** -** Description : -** This method is internal. It is used by Processor Expert -** only. -** =================================================================== -*/ - -void TickTimer_Init(void); -/* -** =================================================================== -** Method : TickTimer_Init (bean TimerInt) -** -** Description : -** This method is internal. It is used by Processor Expert -** only. -** =================================================================== -*/ - -#pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */ - -/* END TickTimer. */ - -#endif /* ifndef __TickTimer */ -/* -** ################################################################### -** -** This file was created by UNIS Processor Expert 03.33 for -** the Motorola HCS12 series of microcontrollers. -** -** ################################################################### -*/ diff --git a/Demo/HCS12_CodeWarrior_small/CODE/Vectors.c b/Demo/HCS12_CodeWarrior_small/CODE/Vectors.c deleted file mode 100644 index 38854b315..000000000 --- a/Demo/HCS12_CodeWarrior_small/CODE/Vectors.c +++ /dev/null @@ -1,115 +0,0 @@ -/** ################################################################### -** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. -** Filename : Cpu.C -** Project : RTOSDemo -** Processor : MC9S12C32CFU -** Beantype : MC9S12C32_80 -** Version : Bean 01.002, Driver 01.09, CPU db: 2.87.276 -** Compiler : Metrowerks HC12 C Compiler -** Date/Time : 17/05/2005, 18:22 -** Abstract : -** This bean "MC9S12C32_80" implements properties, methods, -** and events of the CPU. -** Settings : -** -** Contents : -** EnableInt - void Cpu_EnableInt(void); -** DisableInt - void Cpu_DisableInt(void); -** SetWaitMode - void Cpu_SetWaitMode(void); -** SetStopMode - void Cpu_SetStopMode(void); -** -** (c) Copyright UNIS, spol. s r.o. 1997-2002 -** UNIS, spol. s r.o. -** Jundrovska 33 -** 624 00 Brno -** Czech Republic -** http : www.processorexpert.com -** mail : info@processorexpert.com -** ###################################################################*/ - - -#include "Cpu.h" -#include "Byte1.h" -#include "TickTimer.h" -#include "ButtonInterrupt.h" - -extern void near _EntryPoint(void); /* Startup routine */ -extern void near vPortTickInterrupt( void ); -extern void near vPortYield( void ); -extern void near vButtonPush( void ); - -typedef void (*near tIsrFunc)(void); -const tIsrFunc _vect[] @0xFF80 = { /* Interrupt table */ - Cpu_Interrupt, /* 0 Default (unused) interrupt */ - Cpu_Interrupt, /* 1 Default (unused) interrupt */ - Cpu_Interrupt, /* 2 Default (unused) interrupt */ - Cpu_Interrupt, /* 3 Default (unused) interrupt */ - Cpu_Interrupt, /* 4 Default (unused) interrupt */ - Cpu_Interrupt, /* 5 Default (unused) interrupt */ - Cpu_Interrupt, /* 6 Default (unused) interrupt */ - vButtonPush, /* 7 Default (unused) interrupt */ - Cpu_Interrupt, /* 8 Default (unused) interrupt */ - Cpu_Interrupt, /* 9 Default (unused) interrupt */ - Cpu_Interrupt, /* 10 Default (unused) interrupt */ - Cpu_Interrupt, /* 11 Default (unused) interrupt */ - Cpu_Interrupt, /* 12 Default (unused) interrupt */ - Cpu_Interrupt, /* 13 Default (unused) interrupt */ - Cpu_Interrupt, /* 14 Default (unused) interrupt */ - Cpu_Interrupt, /* 15 Default (unused) interrupt */ - Cpu_Interrupt, /* 16 Default (unused) interrupt */ - Cpu_Interrupt, /* 17 Default (unused) interrupt */ - Cpu_Interrupt, /* 18 Default (unused) interrupt */ - Cpu_Interrupt, /* 19 Default (unused) interrupt */ - Cpu_Interrupt, /* 20 Default (unused) interrupt */ - Cpu_Interrupt, /* 21 Default (unused) interrupt */ - Cpu_Interrupt, /* 22 Default (unused) interrupt */ - Cpu_Interrupt, /* 23 Default (unused) interrupt */ - Cpu_Interrupt, /* 24 Default (unused) interrupt */ - Cpu_Interrupt, /* 25 Default (unused) interrupt */ - Cpu_Interrupt, /* 26 Default (unused) interrupt */ - Cpu_Interrupt, /* 27 Default (unused) interrupt */ - Cpu_Interrupt, /* 28 Default (unused) interrupt */ - Cpu_Interrupt, /* 29 Default (unused) interrupt */ - Cpu_Interrupt, /* 30 Default (unused) interrupt */ - Cpu_Interrupt, /* 31 Default (unused) interrupt */ - Cpu_Interrupt, /* 32 Default (unused) interrupt */ - Cpu_Interrupt, /* 33 Default (unused) interrupt */ - Cpu_Interrupt, /* 34 Default (unused) interrupt */ - Cpu_Interrupt, /* 35 Default (unused) interrupt */ - Cpu_Interrupt, /* 36 Default (unused) interrupt */ - Cpu_Interrupt, /* 37 Default (unused) interrupt */ - Cpu_Interrupt, /* 38 Default (unused) interrupt */ - Cpu_Interrupt, /* 39 Default (unused) interrupt */ - Cpu_Interrupt, /* 40 Default (unused) interrupt */ - Cpu_Interrupt, /* 41 Default (unused) interrupt */ - Cpu_Interrupt, /* 42 Default (unused) interrupt */ - Cpu_Interrupt, /* 43 Default (unused) interrupt */ - Cpu_Interrupt, /* 44 Default (unused) interrupt */ - Cpu_Interrupt, /* 45 Default (unused) interrupt */ - Cpu_Interrupt, /* 46 Default (unused) interrupt */ - Cpu_Interrupt, /* 47 Default (unused) interrupt */ - Cpu_Interrupt, /* 48 Default (unused) interrupt */ - Cpu_Interrupt, /* 49 Default (unused) interrupt */ - Cpu_Interrupt, /* 50 Default (unused) interrupt */ - Cpu_Interrupt, /* 51 Default (unused) interrupt */ - Cpu_Interrupt, /* 52 Default (unused) interrupt */ - Cpu_Interrupt, /* 53 Default (unused) interrupt */ - Cpu_Interrupt, /* 54 Default (unused) interrupt */ - vPortTickInterrupt, - Cpu_Interrupt, /* 56 Default (unused) interrupt */ - Cpu_Interrupt, /* 57 Default (unused) interrupt */ - Cpu_Interrupt, /* 58 Default (unused) interrupt */ - vPortYield, /* 59 Default (unused) interrupt */ - Cpu_Interrupt, /* 60 Default (unused) interrupt */ - Cpu_Interrupt, /* 61 Default (unused) interrupt */ - Cpu_Interrupt, /* 62 Default (unused) interrupt */ - _EntryPoint /* Reset vector */ - }; -/* -** ################################################################### -** -** This file was created by UNIS Processor Expert 03.33 for -** the Motorola HCS12 series of microcontrollers. -** -** ################################################################### -*/ \ No newline at end of file diff --git a/Demo/HCS12_CodeWarrior_small/C_Layout.hwl b/Demo/HCS12_CodeWarrior_small/C_Layout.hwl deleted file mode 100644 index 3b16d98a4..000000000 --- a/Demo/HCS12_CodeWarrior_small/C_Layout.hwl +++ /dev/null @@ -1,20 +0,0 @@ -OPEN source 0 0 60 39 -Source < attributes MARKS off -OPEN assembly 60 0 40 31 -Assembly < attributes ADR on,CODE off,ABSADR on,SYMB off,TOPPC 0xF88C -OPEN procedure 0 39 60 17 -Procedure < attributes VALUES on,TYPES off -OPEN register 60 31 40 25 -Register < attributes FORMAT AUTO,COMPLEMENT None -OPEN memory 60 56 40 22 -Memory < attributes FORMAT hex,COMPLEMENT None,WORD 1,ASC on,ADR on,ADDRESS 0x80 -OPEN data 0 56 60 22 -Data:1 < attributes SCOPE global,COMPLEMENT None,FORMAT Symb,MODE automatic,UPDATERATE 10,NAMEWIDTH 16 -OPEN data 0 78 60 22 -Data:2 < attributes SCOPE local,COMPLEMENT None,FORMAT Symb,MODE automatic,UPDATERATE 10,NAMEWIDTH 16 -OPEN command 60 78 40 22 -Command < attributes CACHESIZE 1000 -bckcolor 50331647 -font 'Courier New' 9 BLACK -AUTOSIZE on -ACTIVATE Data:2 Command Procedure Data:1 Source Register Assembly Memory diff --git a/Demo/HCS12_CodeWarrior_small/DOC/RTOSDemo.sig b/Demo/HCS12_CodeWarrior_small/DOC/RTOSDemo.sig deleted file mode 100644 index 7931aed92..000000000 --- a/Demo/HCS12_CodeWarrior_small/DOC/RTOSDemo.sig +++ /dev/null @@ -1,23 +0,0 @@ -================================================================= -This file was generated from Processor Expert 03.33 - project "RTOSDemo", 18/06/2005, 18:00 ------------------------------------------------------------------ -There is no signal defined in this project. - Hint: Signals may be defined in the Bean Inspector (advanced or expert view) -================================================================= - -================================================================= - SIGNAL LIST ------------------------------------------------------------------ - SIGNAL NAME => PIN NAME ------------------------------------------------------------------ -================================================================= - - -================================================================= - PIN LIST ------------------------------------------------------------------ - PIN NAME => SIGNAL NAME ------------------------------------------------------------------ -================================================================= - diff --git a/Demo/HCS12_CodeWarrior_small/DOC/RTOSDemo.txt b/Demo/HCS12_CodeWarrior_small/DOC/RTOSDemo.txt deleted file mode 100644 index 7bfe268c6..000000000 --- a/Demo/HCS12_CodeWarrior_small/DOC/RTOSDemo.txt +++ /dev/null @@ -1,32 +0,0 @@ -============================================================================= -List of methods in project: RTOSDemo - -THIS TEXT DESCRIPTION IS GENERATED BY THE TOOL. DO NOT MODIFY IT. -============================================================================= - -Module "Byte1" (bean ByteIO) - Byte1_PutBit -Put the specified value to the specified bit/pin of the Input/Output bean. If direction is [input] saves the - value to a memory or a register, this value will be written to the pin after switching to the output mode - - using [SetDir(TRUE)]. If direction is [output] writes the value to the pin. - Byte1_NegBit -Negate (invert) the specified bit of the Input/Output bean. It is the same as [PutBit(Bit,!GetBit(Bit))]. - -Module "TickTimer" (bean TimerInt) - TickTimer_Enable -Enable the bean - it starts the timer. Events may be generated ("DisableEvent"/"EnableEvent"). - TickTimer_SetFreqHz -This method sets the new frequency of the generated events. The frequency is expressed in [Hz] as a - 16-bit unsigned integer number. This method is available only if runtime setting type 'from interval' is - selected in the in Runtime setting area. - -Module "ButtonInterrupt" (bean ExtInt) - ButtonInterrupt_Enable -Enable the bean - the external events are accepted. - -Module "Cpu" (bean MC9S12C32_80) - Cpu_EnableInt -Enable maskable interrupts - Cpu_DisableInt -Disable maskable interrupts - Cpu_SetWaitMode -Set low power mode - Wait mode. -For more information about the wait mode see documentation of this CPU. - -Release from Wait mode: Reset or interrupt - Cpu_SetStopMode -Set low power mode - Stop mode. -For more information about the stop mode see documentation of this CPU. - -============================================================================= diff --git a/Demo/HCS12_CodeWarrior_small/FreeRTOSConfig.h b/Demo/HCS12_CodeWarrior_small/FreeRTOSConfig.h deleted file mode 100644 index d7dc6f5e8..000000000 --- a/Demo/HCS12_CodeWarrior_small/FreeRTOSConfig.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -#include /* common defines and macros */ -#include "TickTimer.h" - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 1 -#define configUSE_TICK_HOOK 0 -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 70 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 2048 - 256 ) ) -#define configMAX_TASK_NAME_LEN ( 1 ) -#define configUSE_TRACE_FACILITY 0 -#define configUSE_16_BIT_TICKS 1 -#define configIDLE_SHOULD_YIELD 1 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* This parameter is normally required in order to set the RTOS tick timer. -This port is a bit different in that hardware setup uses the code generated by -the Processor Expert, making this definition obsolete. - -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 24000000 ) -*/ - - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 0 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 - - - - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/HCS12_CodeWarrior_small/ParTest/ParTest.c b/Demo/HCS12_CodeWarrior_small/ParTest/ParTest.c deleted file mode 100644 index cd2286e2d..000000000 --- a/Demo/HCS12_CodeWarrior_small/ParTest/ParTest.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "portable.h" - -/* Processor Expert created headers. */ -#include "byte1.h" - -/* Demo application include files. */ -#include "partest.h" - -/*----------------------------------------------------------- - * Simple parallel port IO routines. - *-----------------------------------------------------------*/ - -void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) -{ - /* This function is required as it is called from the standard demo - application files. All it does however is call the Processor Expert - created function. */ - portENTER_CRITICAL(); - Byte1_PutBit( uxLED, !xValue ); - portEXIT_CRITICAL(); -} -/*-----------------------------------------------------------*/ - -void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) -{ - /* This function is required as it is called from the standard demo - application files. All it does however is call the processor Expert - created function. */ - portENTER_CRITICAL(); - Byte1_NegBit( uxLED ); - portEXIT_CRITICAL(); -} - - - diff --git a/Demo/HCS12_CodeWarrior_small/RTOSDemo.G_C b/Demo/HCS12_CodeWarrior_small/RTOSDemo.G_C deleted file mode 100644 index f25c6b4af..000000000 --- a/Demo/HCS12_CodeWarrior_small/RTOSDemo.G_C +++ /dev/null @@ -1,368 +0,0 @@ -;Please do not modify this file! -;The file contains internal information about the Processor Expert project generation -[Options] -ProjectName=RTOSDemo -ProjectDirectory=E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_small\ -DestEventsDirectory=CODE\ -DestDriversSubDirectory= -DestDocumentationDirectory=DOC\ -DestCompiledFilesSubDirectory= -DestFpgaSubDirectory= -DestTemporaryDirectory= -[GenFiles] -LinkerFileGenerated=Yes -MakefileGenerated=No -GenSharedModules=5 -Line=PE_Types -Line=PE_Error -Line=PE_Const -Line=IO_Map -Line=PE_Timer -ShrdHeaderAge0=850024804 -ShrdCodeAge0=-1 -ShrdAsemblAge0=-1 -ShrdHeaderAge1=850024804 -ShrdCodeAge1=-1 -ShrdAsemblAge1=-1 -ShrdHeaderAge2=850024804 -ShrdCodeAge2=-1 -ShrdAsemblAge2=-1 -ShrdHeaderAge3=850024804 -ShrdCodeAge3=850024804 -ShrdAsemblAge3=-1 -ShrdHeaderAge4=850478475 -ShrdCodeAge4=850478475 -ShrdAsemblAge4=-1 -GenExtraFiles=2 -Line=E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_small\CODE\Vectors.c -Line=E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_small\CODE\PESL.h -XtraAge0=852660312 -XtraAge1=850024804 -GenExtraFileType1=4 -GenExtraFileType0=4 -GenEventModules=1 -Line=Events -GenMethodsInEvents=0 -GenAllModules=10 -Line=ButtonInterrupt -Line=Byte1 -Line=Cpu -Line=Events -Line=IO_Map -Line=PE_Const -Line=PE_Error -Line=PE_Timer -Line=PE_Types -Line=TickTimer -GenExternModules=0 -GenBeanModules=3 -Line=ButtonInterrupt -Line=TickTimer -Line=Byte1 -SignalListFile=E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_small\DOC\RTOSDemo.sig -DestinationCompiler=MetrowerksHC12CC -ProjectModificationStamp=23 - -[18] -Generated=Yes -GenCompName=Cpu -GenEventModule=Events -HeaderAge=850478231 -CodeAge=852660246 -AsemblAge=-1 -GenNumMethods=10 -SetStopMode=Yes -SetWaitMode=Yes -DisableInt=Yes -EnableInt=Yes -GetIntVect=No -SetIntVect=No -GetSpeedMode=No -SetSlowSpeed=No -SetLowSpeed=No -SetHighSpeed=No -GenNumEvents=4 -OnClockMonitorFail_Selected=1 -OnClockMonitorFail_Name=Cpu_OnClockMonitorFail -OnClockMonitorFail_Priority=interrupts disabled -OnIllegalOpcode_Selected=1 -OnIllegalOpcode_Name=Cpu_OnIllegalOpcode -OnIllegalOpcode_Priority=interrupts disabled -OnReset_Selected=1 -OnReset_Name=Cpu_OnReset -OnReset_Priority=interrupts disabled -OnSwINT_Selected=1 -OnSwINT_Name=Cpu_OnSwINT -OnSwINT_Priority=interrupts disabled -GenSmartUserChangesDetected_Header=No -GenSmartUserChangesDetected_Code=No -GenSmartUserChangesDetected_Asembl=No - -[22] -Generated=Yes -GenCompName=Byte1 -GenEventModule=Events -HeaderAge=850026034 -CodeAge=850026034 -AsemblAge=-1 -GenNumMethods=9 -NegBit=Yes -ClrBit=No -SetBit=No -PutBit=Yes -GetBit=No -PutVal=No -GetVal=No -SetDir=No -GetDir=No -GenNumEvents=0 -GenSmartUserChangesDetected_Header=No -GenSmartUserChangesDetected_Code=No -GenSmartUserChangesDetected_Asembl=No -GenMethodPos=5 -MethodPos0=PutBit -MethodType=method -ModuleType=Header -LineBeg=65 -LineEnd=81 -MethodPos1=NegBit -MethodType=method -ModuleType=Header -LineBeg=82 -LineEnd=96 -MethodPos2=GetMsk -MethodType=internal_method -ModuleType=Code -LineBeg=67 -LineEnd=82 -MethodPos3=PutBit -MethodType=method -ModuleType=Code -LineBeg=83 -LineEnd=110 -MethodPos4=NegBit -MethodType=method -ModuleType=Code -LineBeg=111 -LineEnd=132 - -[25] -Generated=Yes -GenCompName=TickTimer -GenEventModule=Events -HeaderAge=852659892 -CodeAge=852659892 -AsemblAge=-1 -GenNumMethods=14 -SetFreqMHz=No -SetFreqkHz=No -SetFreqHz=Yes -SetPeriodReal=No -SetPeriodSec=No -SetPeriodMS=No -SetPeriodUS=No -SetPeriodTicks32=No -SetPeriodTicks16=No -SetPeriodMode=No -DisableEvent=No -EnableEvent=No -Disable=No -Enable=Yes -GenNumEvents=3 -BeforeNewSpeed_Selected=1 -BeforeNewSpeed_Name=TickTimer_BeforeNewSpeed -BeforeNewSpeed_Priority=interrupts disabled -AfterNewSpeed_Selected=1 -AfterNewSpeed_Name=TickTimer_AfterNewSpeed -AfterNewSpeed_Priority=interrupts disabled -OnInterrupt_Selected=2 -OnInterrupt_Name=vTaskTickInterrupt -OnInterrupt_Priority=same as interrupt -GenSmartUserChangesDetected_Header=No -GenSmartUserChangesDetected_Code=No -GenSmartUserChangesDetected_Asembl=No -GenMethodPos=11 -MethodPos0=Enable -MethodType=method -ModuleType=Header -LineBeg=80 -LineEnd=96 -MethodPos1=SetFreqHz -MethodType=method -ModuleType=Header -LineBeg=97 -LineEnd=122 -MethodPos2=Interrupt -MethodType=internal_method -ModuleType=Header -LineBeg=123 -LineEnd=135 -MethodPos3=Init -MethodType=internal_method -ModuleType=Header -LineBeg=136 -LineEnd=146 -MethodPos4=SetCV -MethodType=internal_method -ModuleType=Code -LineBeg=82 -LineEnd=98 -MethodPos5=SetPV -MethodType=internal_method -ModuleType=Code -LineBeg=99 -LineEnd=112 -MethodPos6=HWEnDi -MethodType=internal_method -ModuleType=Code -LineBeg=113 -LineEnd=132 -MethodPos7=Enable -MethodType=method -ModuleType=Code -LineBeg=133 -LineEnd=156 -MethodPos8=SetFreqHz -MethodType=method -ModuleType=Code -LineBeg=157 -LineEnd=196 -MethodPos9=Init -MethodType=internal_method -ModuleType=Code -LineBeg=197 -LineEnd=214 -MethodPos10=Interrupt -MethodType=internal_method -ModuleType=Code -LineBeg=215 -LineEnd=231 - -[26] -Generated=Yes -GenCompName=ButtonInterrupt -GenEventModule=Events -HeaderAge=850630744 -CodeAge=850630744 -AsemblAge=-1 -GenNumMethods=4 -SetEdge=No -GetVal=No -Disable=No -Enable=Yes -GenNumEvents=1 -OnInterrupt_Selected=2 -OnInterrupt_Name=ButtonInterrupt_OnInterrupt -OnInterrupt_Priority=same as interrupt -GenSmartUserChangesDetected_Header=No -GenSmartUserChangesDetected_Code=No -GenSmartUserChangesDetected_Asembl=No -GenMethodPos=4 -MethodPos0=Enable -MethodType=method -ModuleType=Header -LineBeg=71 -LineEnd=82 -MethodPos1=Interrupt -MethodType=internal_method -ModuleType=Header -LineBeg=83 -LineEnd=95 -MethodPos2=Enable -MethodType=method -ModuleType=Code -LineBeg=73 -LineEnd=88 -MethodPos3=Interrupt -MethodType=internal_method -ModuleType=Code -LineBeg=89 -LineEnd=105 - -[UsedSrcFiles] -SrcFile=Drivers\ByteIO.src=779379247 -SrcFile=Drivers\HCS12\ByteIO.drv=786325143 -SrcFile=Drivers\Common\Header.h=788035759 -SrcFile=Drivers\Common\ByteIOAbstract.Inc=697533609 -SrcFile=Drivers\Common\ByteIOSettings.Inc=662077581 -SrcFile=Drivers\Common\UsedPins.inc=662077580 -SrcFile=Drivers\HCS12\CreateCodeSection.prg=759717537 -SrcFile=Drivers\Common\ByteIOPutBit.Inc=662077581 -SrcFile=Drivers\Common\GeneralPutBit.inc=724263173 -SrcFile=Drivers\Common\GeneralMethod.inc=711812818 -SrcFile=Drivers\Common\GeneralParameters.inc=711813750 -SrcFile=Drivers\Common\GeneralReturnNothing.inc=711816104 -SrcFile=Drivers\Common\GeneralDamage.inc=711813453 -SrcFile=Drivers\Common\ByteIONegBit.Inc=662077581 -SrcFile=Drivers\Common\GeneralNegBit.inc=724263119 -SrcFile=Drivers\Common\Header.End=710308512 -SrcFile=Drivers\Common\Header.c=788035759 -SrcFile=Drivers\HCS12\CreateDataSection.prg=759780817 -SrcFile=Drivers\Common\GeneralInternal.Inc=724263004 -SrcFile=Drivers\TimerInt.src=779379233 -SrcFile=Drivers\HCS12\TimerInt.drv=790330280 -SrcFile=Drivers\Common\TimerIntAbstract.Inc=697533454 -SrcFile=Drivers\Common\TimerIntSettings.Inc=662077596 -SrcFile=Drivers\Common\TimerIntEnable.Inc=724722488 -SrcFile=Drivers\Common\GeneralParametersNone.inc=711813294 -SrcFile=Drivers\Common\TimerIntSetFreqHz.Inc=724921137 -SrcFile=Drivers\HCS12\CreateIntSection.prg=760697835 -SrcFile=Drivers\Common\TimerIntInterrupt.Inc=662077583 -SrcFile=Drivers\Common\TimerIntOnInterrupt.Inc=724722488 -SrcFile=Drivers\Common\GeneralEvent.inc=711816218 -SrcFile=Drivers\Common\GeneralInternalGlobal.Inc=724263104 -SrcFile=Drivers\Common\InitReg8.prg=727217490 -SrcFile=Drivers\Common\InitReg8Enable.prg=783766675 -SrcFile=Drivers\ExtInt.src=779379242 -SrcFile=Drivers\HCS12\ExternalInterrupt.drv=786325143 -SrcFile=Drivers\Common\ExternalInterruptAbstract.Inc=697533660 -SrcFile=Drivers\Common\ExternalInterruptSettings.Inc=662077582 -SrcFile=Drivers\Common\UsedPin.inc=662077580 -SrcFile=Drivers\Common\ExternalInterruptEnable.Inc=724459205 -SrcFile=Drivers\Common\ExternalInterruptOnInterrupt.inc=724459205 -SrcFile=Drivers\HCS12\PE_Types.drv=790261986 -SrcFile=Drivers\Common\PE_TypesAbstract.Inc=662077595 -SrcFile=Drivers\Common\PE_TypesSettings.Inc=662077595 -SrcFile=Drivers\HCS12\PE_Error.drv=744839008 -SrcFile=Drivers\Common\PE_ErrorAbstract.Inc=662077580 -SrcFile=Drivers\Common\ErrorDefinitions.Inc=781282486 -SrcFile=Drivers\HCS12\PE_Const.drv=744839020 -SrcFile=Drivers\Common\PE_ConstAbstract.Inc=662077595 -SrcFile=Drivers\Common\PE_ConstSettings.Inc=662077595 -SrcFile=Drivers\HCS12\IO_Map.drv=790392555 -SrcFile=Drivers\Common\IO_MapAbstract.Inc=662077601 -SrcFile=Drivers\Common\IO_MapSettings.Inc=662077601 -SrcFile=Drivers\HCS12\MC9S12C32_80h.prg=788297413 -SrcFile=Drivers\HCS12\MC9S12C32_80c.prg=787968924 -SrcFile=Drivers\HCS12\PE_Timer.drv=764054261 -SrcFile=Drivers\Common\PE_TimerConstants.Inc=662077594 -SrcFile=Drivers\Common\PE_TimerMethods.Inc=662077585 -SrcFile=Drivers\Common\PE_TimerAbstract.Inc=662077594 -SrcFile=Drivers\Common\PE_TimerSettings.Inc=662077581 -SrcFile=Drivers\Common\PE_TimerLngHi1.Inc=662077594 -SrcFile=Drivers\MC9S12C32_80.src=783110234 -SrcFile=Drivers\HCS12\MC9S12.drv=788297552 -SrcFile=Drivers\Common\MC9S12Abstract.Inc=786070990 -SrcFile=Drivers\Common\MC9S12Settings.Inc=786070990 -SrcFile=Drivers\Common\MC9S12SetStopMode.Inc=786070990 -SrcFile=Drivers\Common\MC9S12SetWaitMode.Inc=786070990 -SrcFile=Drivers\Common\MC9S12DisableInt.Inc=786070990 -SrcFile=Drivers\Common\MC9S12EnableInt.Inc=786070990 -SrcFile=Drivers\Common\GenReg8InitInfo.prg=754344225 -SrcFile=Drivers\Common\GenReg8BitsInitInfo.prg=777356856 -SrcFile=Drivers\Common\CommonInitialization.prg=760832797 -SrcFile=Drivers\Common\CommonRegInitialization.prg=785882407 -SrcFile=Drivers\Common\SetRegBits8.prg=775453568 -SrcFile=Drivers\Common\SetReg8.prg=776374479 -SrcFile=Drivers\Common\CommonEnabling.prg=783766630 -SrcFile=Drivers\Common\CommonRegEnabling.prg=785882407 -SrcFile=Drivers\HCS12\PESL.prg=790397020 -SrcFile=Drivers\Event.src=779379228 -SrcFile=Drivers\HCS12\Evnt.drv=763978411 -SrcFile=Drivers\Common\EvntAbstract.Inc=662077596 -SrcFile=Drivers\Common\EvntSettings.inc=662077580 -SrcFile=Drivers\Common\Header.In1=710699431 -SrcFile=Drivers\_PE_ProjectInfo.src=713322570 -SrcFile=Drivers\SW\_PE_ProjectInfo.drv=726426382 - -[_end_] diff --git a/Demo/HCS12_CodeWarrior_small/RTOSDemo.dsk b/Demo/HCS12_CodeWarrior_small/RTOSDemo.dsk deleted file mode 100644 index 14b46d97a..000000000 --- a/Demo/HCS12_CodeWarrior_small/RTOSDemo.dsk +++ /dev/null @@ -1,166 +0,0 @@ -[Version] -PE_DesktopFileVersion=819 - -[Desktop] -StartupPrj=E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_small\RTOSDemo.pe - -[PE_IDE_PlugIn] - -[CpuExpert] - -[AppPanel] -AllFocusedNode=Cpu:MC9S12C32CFU -ConfigurationsInAllExpanded=Yes -CPUsInAllExpanded=Yes -FPGAsInAllExpanded=No -OperatingSystemInAllExpanded=Yes -BeansInAllExpanded=Yes -TasksInAllExpanded=No -ProgramsInAllExpanded=No -DocumentationInAllExpanded=No -PESLInAllExpanded=No -PESL_moduleInAllExpanded=No -ViewEnabledItemsOnly=No - -[CpuPanel] -Status=hiden -WindowState=NORMAL -Rect=[-568|282|617|532] -CpuPanViewMode=Default - -[ErrorPanel] -Status=hiden -WindowState=NORMAL -Rect=[4|94|1608|1130] - -[ResourceMeter] -Status=hiden -WindowState=NORMAL -Rect=[49|1168|617|178] - -[BeanSelector] -Status=Visible -WindowState=NORMAL -Rect=[-4|62|1608|1130] -BF_ForTgtCpuOnly=Yes -BF_LicensedOnly=Yes - -[ObjInspector] -Status=Visible -WindowState=MAXIMAL -Rect=[-4|62|1199|1100] -ColWidth01=263 -ColWidth02=479 -ColWidth11=188 -ColWidth12=317 -ColWidth21=180 -ColWidth22=352 -ColWidth31=255 -ColWidth32=479 -ColWidth41=133 -ColWidth42=266 -ViewItemLevel=2 - -[PrphInspector] -Status=hiden -WindowState=NORMAL -Rect=[-466|400|516|411] -ViewMode=PrphUsageReport -SortRegsByAddr=Yes -GroupRegisters=No -Peripheral= - -[Editor] -Rect=[-4|0|1199|1100] -FontName=Courier New -FontSize=10 -FontBold=No -FontItalic=No -FontScript=1 -ToolBar=Yes -ToolBarPosition=top -SyntaxHighlighting=Yes -NoHorizScrollBar=Yes -ShowLineNumbers=No -PreserveCurPosDuringPaste=No -UseTabChar=No -ModulesInOneWindow=Yes -TabSize=8 -HintDelay=2 -OpenFilesCount=0 -SelFile= -SelLine=-1 -FileHistory=0 - -[CpuStructure] -Rect=[0|0|0|0] - -[StrListEditor] -WindowWidth=450 -WindowHeight=333 - -[Breakpoints] -WindowVisible=No -Rect=[0|0|0|0] -BreakLine1=0 -BreakModule1= - -[Watches] -Rect=[0|0|0|0] -WindowVisible=No -WatchCount=0 -WatchHistoryCount=0 - -[Registers] -Rect=[0|0|100|500] -WindowVisible=No - -[Dump] -WindowVisible=No -Rect=[0|0|0|0] -Address=0 -DataSize=1 -DataType=num -HistoryAddrCount=0 - -[InterruptVectors] -WindowVisible=No -Rect=[0|0|0|0] - -[MemoryMap] -Rect=[422|156|355|480] -DisplayOnlyMemories=No -WindowVisible=No - -[Browser] -Rect=[0|0|0|0] -WindowVisible=No - -[BeanManager] -Rect=[0|0|0|0] -BeanInfoFilter= -DriverFilter= -DriverInfoFilter= -BeanSettingsProjectFilter= - -[Options] -AutosaveWithProject=No -AutosaveBeforeTool=No -NumberOfBackupCopies=0 -AutoSaveDesktop=Yes -AutoOpenPropEdit=Yes -AutoConnectDevice=Yes -SelectTemplate=No -ShowGenProgress=Yes -AutoShowGeneratedSrc=No -AutoShowEventModules=No -ShowMethodCode=No -GenerateUndo=No -CpuBitmapFileName=Config\PE\CPUbckgr.bmp -CpuBitmapTilled=No -ShowProducerLogo=No -AutoStartApplicationCode=No -ShowSourceLinAfterDbgInit=No -RestoreFilesAfterDebug=No - -[_end_] diff --git a/Demo/HCS12_CodeWarrior_small/RTOSDemo.mcp b/Demo/HCS12_CodeWarrior_small/RTOSDemo.mcp deleted file mode 100644 index 14c456857..000000000 Binary files a/Demo/HCS12_CodeWarrior_small/RTOSDemo.mcp and /dev/null differ diff --git a/Demo/HCS12_CodeWarrior_small/RTOSDemo.pe b/Demo/HCS12_CodeWarrior_small/RTOSDemo.pe deleted file mode 100644 index 54386559d..000000000 --- a/Demo/HCS12_CodeWarrior_small/RTOSDemo.pe +++ /dev/null @@ -1,2387 +0,0 @@ -Processor Expert Version 0333 -ProjectModificationStamp=23 - -[Options] -EventsDirectory=CODE\ -DestinationSubDir= -DocumentationDir=DOC\ -CompiledFilesSubDir= -FPGAsubdirectory= -TemporaryDir=%TEMP% -OverwriteEvents=3 -OverwriteBeanDrv=0 -UseExistingModules=Yes -RenamePeripheries=Yes -Autodependency=Yes -ProjectCompNumb=27 -DelUnusedPreviouslyGenFiles=Yes - -[MC9S12C32_80:Cpu] -CompNumb=18 -CompEnabled=Yes -GenCodeMode=CHECK_n_WRITE -IconName=CPU_CHIP2 -Comment=0 -Template= - -[Properties] -List=Property -[ItemState] -ItemSymbol=DeviceName -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=Cpu -[ItemState] -ItemSymbol=CPU -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=MC9S12C32CFU -[ItemState] -ItemSymbol=Xtal -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=16 -[ItemState] -ItemSymbol=InitPriority -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=interrupts disabled -[ItemState] -ItemSymbol=PLLStopsInWait -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -[ItemState] -ItemSymbol=HC12_ChipSelects -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=MemMode -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=0 -[ItemState] -ItemSymbol=HC12_INTFLASHON -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Value=Yes - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=HalfFlashEn -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No - -[EndOfChilds] -[ItemState] -ItemSymbol=ExtBusGrp -ReadOnly=Yes -UserReadOnly=No -BasAdvHid=ADVANCED -Value=No - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=ExtBusStretch -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=3 - -[EndOfChilds] - -[EndOfChilds] -[ItemState] -ItemSymbol=HC12_InternalMapping -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=HC12_INITRG -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=0 -[ItemState] -ItemSymbol=HC12_INITRM -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -TypeSpecNameState=typeHCS12_RAMMapping2kRAM -Index=1 - -[EndOfChilds] -[ItemState] -ItemSymbol=Intperiphgrp -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=PWMmoduleGrp -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=PWMStopsInWait -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -[ItemState] -ItemSymbol=PWMStopsInFreeze -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -[ItemState] -ItemSymbol=PWMEmergency -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=No - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=PWMEmergencyInputLevel -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=0 -[ItemState] -ItemSymbol=PWMEmergencyShutLevel -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=0 - -[EndOfChilds] - -[EndOfChilds] -[ItemState] -ItemSymbol=ECTmoduleGrp -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=ECTStopsInWait -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -[ItemState] -ItemSymbol=ECTStopsInFreeze -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=0 -Value=Yes - -[EndOfChilds] -[ItemState] -ItemSymbol=IOmoduleGrp0 -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=PortAGrp0 -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=PAreduceddrive -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No - -[EndOfChilds] -[ItemState] -ItemSymbol=PortBGrp0 -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=PBreduceddrive -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No - -[EndOfChilds] -[ItemState] -ItemSymbol=PortEGrp0 -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=PEreduceddrive -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No - -[EndOfChilds] -[ItemState] -ItemSymbol=PortTGrp0 -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=PTreduceddriveBit0 -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -[ItemState] -ItemSymbol=PTreduceddriveBit1 -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -[ItemState] -ItemSymbol=PTreduceddriveBit2 -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -[ItemState] -ItemSymbol=PTreduceddriveBit3 -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -[ItemState] -ItemSymbol=PTreduceddriveBit4 -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -[ItemState] -ItemSymbol=PTreduceddriveBit5 -ReadOnly=No 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-UsrMethodName=GetVal -[ItemState] -ItemSymbol=PutVal -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=PutVal -[ItemState] -ItemSymbol=GetBit -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=GetBit -[ItemState] -ItemSymbol=PutBit -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=0 -Value=Yes -LastSelection=No -LastUserSel=yes -UsrMethodName=PutBit -[ItemState] -ItemSymbol=SetBit -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=SetBit -[ItemState] -ItemSymbol=ClrBit -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=ClrBit -[ItemState] -ItemSymbol=NegBit -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=0 -Value=Yes -LastSelection=No -LastUserSel=yes -UsrMethodName=NegBit - -[Events] -List=Event -[ItemState] -ItemSymbol=EventModule -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Value=Events - -[TimerInt:TickTimer] -CompNumb=25 -CompEnabled=Yes -GenCodeMode=CHECK_n_WRITE -IconName=TMRCNTR -Comment=0 -Template= - -[Properties] -List=Property -[ItemState] -ItemSymbol=DeviceName -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Value=TickTimer -[ItemState] -ItemSymbol=_Cmp -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=TC0 -SharedPrphMode=No -[ItemState] -ItemSymbol=Tmr -ReadOnly=Yes -UserReadOnly=No -BasAdvHid=ADVANCED -Value=TIM -SharedPrphMode=No -[ItemState] -ItemSymbol=IntService -ReadOnly=Yes -UserReadOnly=No -BasAdvHid=BASIC -Value=Yes - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=CmpInt -ReadOnly=Yes -UserReadOnly=No -BasAdvHid=ADVANCED -Value=INT_TC0 -SharedPrphMode=No -[ItemState] -ItemSymbol=CmpInitPriority -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=medium priority -[ItemState] -ItemSymbol=COP8_grp -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=ScndReloadGrp -ReadOnly=Yes -UserReadOnly=No -BasAdvHid=ADVANCED -Value=Yes - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=ScndTmr -ReadOnly=Yes -UserReadOnly=No -BasAdvHid=EXPERT -Value= -SharedPrphMode=No -[ItemState] -ItemSymbol=ScndIntr -ReadOnly=Yes -UserReadOnly=No -BasAdvHid=ADVANCED -Value= -SharedPrphMode=No - -[EndOfChilds] - -[EndOfChilds] - -[EndOfChilds] -[ItemState] -ItemSymbol=COP8grp -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=COP8TimerSpeedBase -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -TypeSpecNameState=typeCOP8_TimerPrescalerDefault -Index=0 - -[EndOfChilds] -[ItemState] -ItemSymbol=InitPrescaler -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=InternPrescaler -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC - -[Childs] -List=GrupItem - -[EndOfChilds] -Value=Auto selected prescaler -[ItemState] -ItemSymbol=InternCompare -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC - -[Childs] -List=GrupItem - -[EndOfChilds] -Value=Auto selected prescaler - -[EndOfChilds] -Value=Auto selected prescaler -[ItemState] -ItemSymbol=_Tmg -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=1000 Hz -RuntimeSetting=1 -InitValue=1000 Hz -Precision=5 -PrecInProc=Yes -LowLimit=100 Hz -HighLimit=1000 Hz -List=0 -UnitText=Hz -[ItemState] -ItemSymbol=SameValuesInAllModes -ReadOnly=No -UserReadOnly=No -BasAdvHid=EXPERT -Index=0 -Value=Yes -[ItemState] -ItemSymbol=EntireTimer -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Index=1 -Value=No -[ItemState] -ItemSymbol=_InitGrp -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=InitEnable -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -[ItemState] -ItemSymbol=InitEnableEvent -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Index=0 -Value=Yes - -[EndOfChilds] -[ItemState] -ItemSymbol=_SpeedGrp -ReadOnly=No -UserReadOnly=No -BasAdvHid=EXPERT - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=HighSpeed -ReadOnly=No -UserReadOnly=No -BasAdvHid=EXPERT -Index=0 -Value=Yes -[ItemState] -ItemSymbol=LowSpeed -ReadOnly=No -UserReadOnly=No -BasAdvHid=EXPERT -Index=0 -Value=Yes -[ItemState] -ItemSymbol=SlowSpeed -ReadOnly=No -UserReadOnly=No -BasAdvHid=EXPERT -Index=0 -Value=Yes - -[EndOfChilds] -[ItemState] -ItemSymbol=MirrorECTmoduleGrp -ReadOnly=No -UserReadOnly=No -BasAdvHid=EXPERT - -[Childs] -List=GrupItem - -[EndOfChilds] - -[Methods] -List=Method -[ItemState] -ItemSymbol=Enable -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=0 -Value=Yes -LastSelection=No -LastUserSel=yes -UsrMethodName=Enable -[ItemState] -ItemSymbol=Disable -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=Disable -[ItemState] -ItemSymbol=EnableEvent -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=EnableEvent -[ItemState] -ItemSymbol=DisableEvent -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=DisableEvent -[ItemState] -ItemSymbol=SetPeriodMode -ReadOnly=Yes -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=Yes -LastUserSel=never -UsrMethodName=SetPeriodMode -[ItemState] -ItemSymbol=SetPeriodTicks16 -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=Yes -LastUserSel=no -UsrMethodName=SetPeriodTicks16 -[ItemState] -ItemSymbol=SetPeriodTicks32 -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=Yes -LastUserSel=no -UsrMethodName=SetPeriodTicks32 -[ItemState] -ItemSymbol=SetPeriodUS -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=Yes -LastUserSel=no -UsrMethodName=SetPeriodUS -[ItemState] -ItemSymbol=SetPeriodMS -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=Yes -LastUserSel=no -UsrMethodName=SetPeriodMS -[ItemState] -ItemSymbol=SetPeriodSec -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=SetPeriodSec -[ItemState] -ItemSymbol=SetPeriodReal -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=SetPeriodReal -[ItemState] -ItemSymbol=SetFreqHz -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=0 -Value=Yes -LastSelection=No -LastUserSel=yes -UsrMethodName=SetFreqHz -[ItemState] -ItemSymbol=SetFreqkHz -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=SetFreqkHz -[ItemState] -ItemSymbol=SetFreqMHz -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=SetFreqMHz - -[Events] -List=Event -[ItemState] -ItemSymbol=EventModule -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Value=Events -[ItemState] -ItemSymbol=BeforeNewSpeed -ReadOnly=No -UserReadOnly=No -BasAdvHid=EXPERT -Value=No - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=Name -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=TickTimer_BeforeNewSpeed - -[EndOfChilds] -LastSelection=No -LastUserSel=no -[ItemState] -ItemSymbol=AfterNewSpeed -ReadOnly=No -UserReadOnly=No -BasAdvHid=EXPERT -Value=No - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=Name -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=TickTimer_AfterNewSpeed - -[EndOfChilds] -LastSelection=No -LastUserSel=no -[ItemState] -ItemSymbol=OnInterrupt -ReadOnly=Yes -UserReadOnly=No -BasAdvHid=BASIC -Value=Yes - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=Name -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=vTaskTickInterrupt -[ItemState] -ItemSymbol=Priority -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Value=same as interrupt - -[EndOfChilds] -LastSelection=No -LastUserSel=always - -[ExtInt:ButtonInterrupt] -CompNumb=26 -CompEnabled=Yes -GenCodeMode=CHECK_n_WRITE -IconName=EXTINT -Comment=0 -Template= - -[Properties] -List=Property -[ItemState] -ItemSymbol=DeviceName -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Value=ButtonInterrupt -[ItemState] -ItemSymbol=_Pin -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=PP0_PWM0_KWP0 -SharedPrphMode=No -[ItemState] -ItemSymbol=PinSignal -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Value= -[ItemState] -ItemSymbol=PullMode -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -TypeSpecNameState=typePULL -Index=1 -[ItemState] -ItemSymbol=InitEdge -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=2 -[ItemState] -ItemSymbol=HCS08grp -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=Invert -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No - -[EndOfChilds] -[ItemState] -ItemSymbol=Int -ReadOnly=Yes -UserReadOnly=No -BasAdvHid=ADVANCED -Value=INT_PortP -SharedPrphMode=No -[ItemState] -ItemSymbol=InitPriority -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=medium priority -[ItemState] -ItemSymbol=JBJGcond -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=PTE4Int -ReadOnly=Yes -UserReadOnly=No -BasAdvHid=BASIC -Value=No - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=SHpin -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value= -SharedPrphMode=No -[ItemState] -ItemSymbol=SHPinSignal -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Value= -[ItemState] -ItemSymbol=SHPullMode -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -TypeSpecNameState=typePULL -Index=5 - -[EndOfChilds] - -[EndOfChilds] -[ItemState] -ItemSymbol=_InitGrp -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=InitEnable -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No - -[EndOfChilds] - -[Methods] -List=Method -[ItemState] -ItemSymbol=Enable -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=0 -Value=Yes -LastSelection=No -LastUserSel=yes -UsrMethodName=Enable -[ItemState] -ItemSymbol=Disable -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=Disable -[ItemState] -ItemSymbol=GetVal -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=GetVal -[ItemState] -ItemSymbol=SetEdge -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=SetEdge -[ItemState] -ItemSymbol=56800grp -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=ConnectPin -ReadOnly=No -UserReadOnly=No -BasAdvHid=EXPERT -Index=1 -Value=No -LastSelection=No -LastUserSel=no -UsrMethodName=ConnectPin - -[EndOfChilds] - -[Events] -List=Event -[ItemState] -ItemSymbol=EventModule -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Value=Events -[ItemState] -ItemSymbol=OnInterrupt -ReadOnly=Yes -UserReadOnly=No -BasAdvHid=BASIC -Value=Yes - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=Name -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=ButtonInterrupt_OnInterrupt -[ItemState] -ItemSymbol=Priority -ReadOnly=No -UserReadOnly=No -BasAdvHid=ADVANCED -Value=same as interrupt - -[EndOfChilds] -LastSelection=No -LastUserSel=always -[ItemState] -ItemSymbol=CPUCondJBJG -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=OnTriggerInterrupt -ReadOnly=Yes -UserReadOnly=No -BasAdvHid=BASIC -Value=No - -[Childs] -List=GrupItem -[ItemState] -ItemSymbol=Name -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=ButtonInterrupt_OnTriggerInterrupt -[ItemState] -ItemSymbol=Priority -ReadOnly=No -UserReadOnly=No -BasAdvHid=BASIC -Value=interrupts disabled - -[EndOfChilds] -LastSelection=No -LastUserSel=never - -[EndOfChilds] - -[Program] -ProgType=event -ProgNumb=2 -List=Property -EventModule=Events - -[_end_] diff --git a/Demo/HCS12_CodeWarrior_small/RTOSDemo_Data/CWSettingsWindows.stg b/Demo/HCS12_CodeWarrior_small/RTOSDemo_Data/CWSettingsWindows.stg deleted file mode 100644 index 34ba6fcbe..000000000 Binary files a/Demo/HCS12_CodeWarrior_small/RTOSDemo_Data/CWSettingsWindows.stg and /dev/null differ diff --git a/Demo/HCS12_CodeWarrior_small/RTOSDemo_Data/Simulator/TargetDataWindows.tdt b/Demo/HCS12_CodeWarrior_small/RTOSDemo_Data/Simulator/TargetDataWindows.tdt deleted file mode 100644 index 908534209..000000000 Binary files a/Demo/HCS12_CodeWarrior_small/RTOSDemo_Data/Simulator/TargetDataWindows.tdt and /dev/null differ diff --git a/Demo/HCS12_CodeWarrior_small/RTOSDemo_Data/SofTec/TargetDataWindows.tdt b/Demo/HCS12_CodeWarrior_small/RTOSDemo_Data/SofTec/TargetDataWindows.tdt deleted file mode 100644 index f3e53147f..000000000 Binary files a/Demo/HCS12_CodeWarrior_small/RTOSDemo_Data/SofTec/TargetDataWindows.tdt and /dev/null differ diff --git a/Demo/HCS12_CodeWarrior_small/Simulator.ini b/Demo/HCS12_CodeWarrior_small/Simulator.ini deleted file mode 100644 index bf14c5590..000000000 --- a/Demo/HCS12_CodeWarrior_small/Simulator.ini +++ /dev/null @@ -1,41 +0,0 @@ -[Environment Variables] -GENPATH={Compiler}lib\HC12c\src;{Compiler}lib\HC12c\include;{Compiler}lib\HC12c\lib -LIBPATH={Compiler}lib\HC12c\include -OBJPATH={Project}bin -TEXTPATH={Project}bin -ABSPATH={Project}bin - -[HI-WAVE] -Target=sim -Layout=C_layout.hwl -LoadDialogOptions= -CPU=HC12 -MainFrame=2,3,-1,-1,-1,-1,243,243,1443,1097 -TOOLBAR=57600 57601 32795 0 57635 57634 57637 0 57671 57669 0 32777 32776 32782 32780 32781 32778 0 32806 - -[Simulator] -CMDFILE0=CMDFILE STARTUP ON ".\cmd\simulator_startup.cmd" - -[Simulator HC12] -CMDFILE0=CMDFILE RESET ON ".\cmd\simulator_reset.cmd" -CMDFILE1=CMDFILE PRELOAD ON ".\cmd\simulator_preload.cmd" -CMDFILE2=CMDFILE POSTLOAD ON ".\cmd\simulator_postload.cmd" -CMDFILE3=CMDFILE SETCPU ON ".\cmd\simulator_setcpu.cmd" -HCS12_SUPPORT=1 -FCS=MC9S12C32 - -[Recent Applications File List] -File1=E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior\bin\Simulator.abs -File2= -File3= -File4= -LoadFlags1=4099 -LoadFlags2=0 -LoadFlags3=0 -LoadFlags4=0 - -[Recent Layout File List] -File1=C_layout.hwl -File2= -File3= -File4= diff --git a/Demo/HCS12_CodeWarrior_small/SofTec.ini b/Demo/HCS12_CodeWarrior_small/SofTec.ini deleted file mode 100644 index 88e349622..000000000 --- a/Demo/HCS12_CodeWarrior_small/SofTec.ini +++ /dev/null @@ -1,50 +0,0 @@ -[Environment Variables] -GENPATH={Compiler}lib\HC12c\src;{Compiler}lib\HC12c\include;{Compiler}lib\HC12c\lib -LIBPATH={Compiler}lib\HC12c\include -OBJPATH={Project}bin -TEXTPATH={Project}bin -ABSPATH={Project}bin - -[HI-WAVE] -Target=gdi -Layout=C_layout.hwl -LoadDialogOptions=AUTOERASEANDFLASH -CPU=HC12 -MainFrame=2,3,-1,-1,-1,-1,216,216,1416,1070 -TOOLBAR=57600 57601 32795 0 57635 57634 57637 0 57671 57669 0 32777 32776 32782 32780 32781 32778 0 32806 - -[GDI] -COMSETTINGS=SETCOMM DRIVER NOPROTOCOL NOPERIODICAL "SofTec_BDM12.dll" - -[SofTec_Microsystems_GdiHCS12] -Hardware=PK-HCS12C32 -DeviceName=MC9S12C32 -Settings=- - -[inDART-HCS12_GDI_SETTINGS] -CMDFILE0=CMDFILE STARTUP ON ".\cmd\SofTec_startup.cmd" -CMDFILE1=CMDFILE RESET ON ".\cmd\SofTec_reset.cmd" -CMDFILE2=CMDFILE PRELOAD ON ".\cmd\SofTec_preload.cmd" -CMDFILE3=CMDFILE POSTLOAD ON ".\cmd\SofTec_postload.cmd" -BNKA_MCUID03E1_BANKWINDOW0=BANKWINDOW PPAGE ON 0x8000..0xBFFF 0x30 2 0x3E -BNKA_MCUID03E1_BANKWINDOW1=BANKWINDOW DPAGE OFF 0x7000..0x7FFF 0x34 256 0x0 -BNKA_MCUID03E1_BANKWINDOW2=BANKWINDOW EPAGE OFF 0x400..0x7FF 0x36 256 0x0 -DBG_S12_0=DBG GENERAL DISARM_ON PROTECT_OFF ANALYZE_ON STEPATRUN_ON -DBG_S12_1=DBG USER12 0x0 0x0 0x0 0x0 -DBG_S12_2=DBG PREDEFINED SELECT 0 END STOP 0x0 DATAMATCH_HIGH NORMAL - -[Recent Applications File List] -File1=E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior\bin\SofTec.abs -File2= -File3= -File4= -LoadFlags1=4099 -LoadFlags2=0 -LoadFlags3=0 -LoadFlags4=0 - -[Recent Layout File List] -File1=C_layout.hwl -File2= -File3= -File4= diff --git a/Demo/HCS12_CodeWarrior_small/Sources/Start12.c b/Demo/HCS12_CodeWarrior_small/Sources/Start12.c deleted file mode 100644 index df8b0e648..000000000 --- a/Demo/HCS12_CodeWarrior_small/Sources/Start12.c +++ /dev/null @@ -1,342 +0,0 @@ -/***************************************************** - start12.c - standard startup code - The startup code may be optimized to special user requests - ---------------------------------------------------- - Copyright (c) Metrowerks, Basel, Switzerland - All rights reserved - Do not modify! - -Note: ROM libraries are not implemented in this startup code -Note: C++ destructors of global objects are NOT yet supported in the HIWARE Object File Format. - To use this feature, please build your application with the ELF object file format. - *****************************************************/ - -#include "hidef.h" -#include "start12.h" - -/* Macros to control how the startup code handles the COP: */ -/* #define _DO_FEED_COP_ : do feed the COP */ -/* #define _DO_ENABLE_COP_: do enable the COP */ -/* #define _DO_DISABLE_COP_: disable the COP */ -/* Without defining any of these, the startup code does NOT handle the COP */ - -#pragma DATA_SEG __NEAR_SEG STARTUP_DATA /* _startupData can be accessed using 16 bit accesses. This is needed because it contains the stack top, and without stack, far data cannot be accessed */ -struct _tagStartup _startupData; /* read-only: */ - /* _startupData is allocated in ROM and */ - /* initialized by the linker */ -#pragma DATA_SEG DEFAULT -#if defined(FAR_DATA) -#include "non_bank.sgm" -/* the init function must be in non banked memory if banked variables are used */ -/* because _SET_PAGE is called, which may change any page register. */ - -#ifdef __cplusplus - extern "C" -#endif -void _SET_PAGE(void); /* the inline assembler needs a prototype */ - /* this is a runtime routine with a special */ - /* calling convention, dont use it in c code! */ -static void Init(void); -static void Fini(void); -#else -#include "default.sgm" -#if defined( __BANKED__) || defined(__LARGE__) -static void __far Init(void); -static void __far Fini(void); -#endif /* defined( __BANKED__) || defined(__LARGE__) */ -#endif /* FAR_DATA */ - - -/* define value and bits for Windef Register */ -#ifdef HC812A4 -#define WINDEF (*(volatile unsigned char*) 0x37) -#if defined( __BANKED__) || defined(__LARGE__) || defined(__PPAGE__) -#define __ENABLE_PPAGE__ 0x40 -#else -#define __ENABLE_PPAGE__ 0x0 -#endif -#if defined(__DPAGE__) -#define __ENABLE_DPAGE__ 0x80 -#else -#define __ENABLE_DPAGE__ 0x0 -#endif -#if defined(__EPAGE__) -#define __ENABLE_EPAGE__ 0x20 -#else -#define __ENABLE_EPAGE__ 0x0 -#endif -#endif /* HC812A4 */ - -#ifdef _HCS12_SERIALMON - /* for Monitor based software remap the RAM & EEPROM to adhere - to EB386. Edit RAM and EEPROM sections in PRM file to match these. */ -#define ___INITRM (*(volatile unsigned char *) 0x0010) -#define ___INITRG (*(volatile unsigned char *) 0x0011) -#define ___INITEE (*(volatile unsigned char *) 0x0012) -#endif - -#if defined(_DO_FEED_COP_) -#define __FEED_COP_IN_HLI() } __asm movb #0x55, _COP_RST_ADR; __asm movb #0xAA, _COP_RST_ADR; __asm { -#else -#define __FEED_COP_IN_HLI() /* do nothing */ -#endif - -#if !defined(FAR_DATA) && (defined( __BANKED__) || defined(__LARGE__)) -static void __far Init(void) -#else -static void Init(void) -#endif - { -/* purpose: 1) zero out RAM-areas where data is allocated */ -/* 2) copy initialization data from ROM to RAM */ -/* 3) call global constructors in C++ */ -/* called from: _Startup, LibInits */ - __asm { -ZeroOut: -#if defined(__HIWARE_OBJECT_FILE_FORMAT__) && defined(__LARGE__) - LDX _startupData.pZeroOut:1 ; in the large memory model in the HIWARE format, pZeroOut is a 24 bit pointer -#else - LDX _startupData.pZeroOut ; *pZeroOut -#endif - LDY _startupData.nofZeroOuts ; nofZeroOuts - BEQ CopyDown ; if nothing to zero out - -NextZeroOut: PSHY ; save nofZeroOuts -#ifdef FAR_DATA - LDAB 1,X+ ; load page of destination address - LDY 2,X+ ; load offset of destination address - __PIC_JSR(_SET_PAGE) ; sets the page in the correct page register -#else /* FAR_DATA */ - LDY 2,X+ ; start address and advance *pZeroOut (X = X+4) -#endif /* FAR_DATA */ - LDD 2,X+ ; byte count -#ifdef __OPTIMIZE_FOR_SIZE__ /* -os, default */ -NextWord: CLR 1,Y+ ; clear memory byte - __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */ - DBNE D, NextWord ; dec byte count -#else - LSRD ; /2 and save bit 0 in the carry - PSHX - LDX #0 -LoopClrW: STX 2,Y+ ; Word-Clear - __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */ - DBNE D, LoopClrW - PULX - BCC LastClr ; handle last byte - CLR 1,Y+ -LastClr: -#endif - PULY ; restore nofZeroOuts - DEY ; dec nofZeroOuts - BNE NextZeroOut -CopyDown: -#ifdef __ELF_OBJECT_FILE_FORMAT__ - LDX _startupData.toCopyDownBeg ; load address of copy down desc. -#else - LDX _startupData.toCopyDownBeg:2 ; load address of copy down desc. -#endif -NextBlock: - LDD 2,X+ ; size of init-data -> D - BEQ funcInits ; end of copy down desc. -#ifdef FAR_DATA - PSHD ; save counter - LDAB 1,X+ ; load destination page - LDY 2,X+ ; destination address - __PIC_JSR(_SET_PAGE) ; sets the destinations page register - PULD ; restore counter -#else /* FAR_DATA */ - LDY 2,X+ ; load destination address -#endif /* FAR_DATA */ - -#ifdef __OPTIMIZE_FOR_SIZE__ /* -os, default */ -Copy: MOVB 1,X+,1,Y+ ; move a byte from ROM to the data area - __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */ - DBNE D,Copy ; copy-byte loop -#else - LSRD ; /2 and save bit 0 in the carry -Copy: MOVW 2,X+,2,Y+ ; move a word from ROM to the data area - __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */ - DBNE D,Copy ; copy-word loop - BCC NextBlock ; handle last byte? - MOVB 1,X+,1,Y+ ; copy the last byte -#endif - BRA NextBlock -funcInits: ; call of global construtors is only in c++ necessary -#if defined(__cplusplus) -#if defined(__ELF_OBJECT_FILE_FORMAT__) -#if defined( __BANKED__) || defined(__LARGE__) - LDY _startupData.nofInitBodies; load number of cpp. - BEQ done ; if cppcount == 0, goto done - LDX _startupData.initBodies ; load address of first module to initialize -nextInit: - LEAX 3,X ; increment to next init - PSHX ; save address of next function to initialize - PSHY ; save cpp counter - CALL [-3,X] ; use double indirect call to load the page register also - PULY ; restore cpp counter - PULX ; restore actual address - DEY ; decrement cpp counter - BNE nextInit -#else /* defined( __BANKED__) || defined(__LARGE__) */ - - LDD _startupData.nofInitBodies; load number of cpp. - BEQ done ; if cppcount == 0, goto done - LDX _startupData.initBodies ; load address of first module to initialize -nextInit: - LDY 2,X+ ; load address of first module to initialize - PSHD - PSHX ; save actual address - JSR 0,Y ; call initialization function - PULX ; restore actual address - PULD ; restore cpp counter - DBNE D, nextInit -#endif /* defined( __BANKED__) || defined(__LARGE__) */ -#else /* __ELF_OBJECT_FILE_FORMAT__ */ - LDX _startupData.mInits ; load address of first module to initialize -#if defined( __BANKED__) || defined(__LARGE__) -nextInit: LDY 3,X+ ; load address of initialization function - BEQ done ; stop when address == 0 - ; in common environments the offset of a function is never 0, so this test could be avoided -#ifdef __InitFunctionsMayHaveOffset0__ - BRCLR -1,X, done, 0xff ; stop when address == 0 -#endif /* __InitFunctionsMayHaveOffset0__ */ - PSHX ; save address of next function to initialize - CALL [-3,X] ; use double indirect call to load the page register also -#else /* defined( __BANKED__) || defined(__LARGE__) */ -nextInit: - LDY 2,X+ ; load address of first module to initialize - BEQ done ; stop when address of function == 0 - PSHX ; save actual address - JSR 0,Y ; call initialization function -#endif /* defined( __BANKED__) || defined(__LARGE__) */ - PULX ; restore actual address - BRA nextInit -#endif /* __ELF_OBJECT_FILE_FORMAT__ */ -done: -#endif /* __cplusplus */ - } -} - -#if defined( __ELF_OBJECT_FILE_FORMAT__) && defined(__cplusplus ) - -#if !defined(FAR_DATA) && (defined( __BANKED__) || defined(__LARGE__)) -static void __far Fini(void) -#else -static void Fini(void) -#endif -{ -/* purpose: 1) call global destructors in C++ */ - __asm { -#if defined( __BANKED__) || defined(__LARGE__) - - LDY _startupData.nofFiniBodies; load number of cpp. - BEQ done ; if cppcount == 0, goto done - LDX _startupData.finiBodies ; load address of first module to finalize -nextInit2: - LEAX 3,X ; increment to next init - PSHX ; save address of next function to finalize - PSHY ; save cpp counter - CALL [-3,X] ; use double indirect call to load the page register also - PULY ; restore cpp counter - PULX ; restore actual address - DEY ; decrement cpp counter - BNE nextInit2 -#else /* defined( __BANKED__) || defined(__LARGE__) */ - - LDD _startupData.nofFiniBodies; load number of cpp. - BEQ done ; if cppcount == 0, goto done - LDX _startupData.finiBodies ; load address of first module to finalize -nextInit2: - LDY 2,X+ ; load address of first module to finalize - PSHD - PSHX ; save actual address - JSR 0,Y ; call finalize function - PULX ; restore actual address - PULD ; restore cpp counter - DBNE D, nextInit2 -#endif /* defined( __BANKED__) || defined(__LARGE__) */ -done:; - } -} -#endif - - -#include "non_bank.sgm" - -#pragma MESSAGE DISABLE C12053 /* Stack-pointer change not in debugging-information */ -#pragma NO_FRAME -#pragma NO_ENTRY -#pragma NO_EXIT - -#ifdef __cplusplus - extern "C" -#endif - -/* The function _Startup must be called in order to initialize global variables and to call main */ -/* You can adapt this function or call it from your startup code to implement a different startup */ -/* functionality. */ - -/* You should also setup the needed IO registers as WINDEF (HC12A4 only) or the COP registers to run */ -/* on hardware */ - -/* to set the reset vector several ways are possible : */ -/* 1. define the function with "interrupt 0" as done below in the first case */ -/* 2. add the following line to your prm file : VECTOR ADDRESS 0xfffe _Startup */ -/* of course, even more posibilities exists */ -/* the reset vector must be set so that the application has a defined entry point */ - -#define STARTUP_FLAGS_NOT_INIT_SP (1<<1) - -#if defined(__SET_RESET_VECTOR__) -void __interrupt 0 _Startup(void) { -#else -void _Startup(void) { -#endif -/* purpose: 1) initialize the stack - 2) initialize the RAM, copy down init data etc (Init) - 3) call main; - parameters: NONE - called from: _PRESTART-code generated by the Linker - or directly referenced by the reset vector */ - for(;;) { /* forever: initialize the program; call the root-procedure */ - if (!(_startupData.flags&STARTUP_FLAGS_NOT_INIT_SP)) { - /* initialize the stack pointer */ - INIT_SP_FROM_STARTUP_DESC(); /*lint !e522 asm code */ /* HLI macro definition in hidef.h */ - } - -#ifdef _HCS12_SERIALMON - /* for Monitor based software remap the RAM & EEPROM to adhere - to EB386. Edit RAM and EEPROM sections in PRM file to match these. */ - ___INITRG = 0x00; /* lock registers block to 0x0000 */ - ___INITRM = 0x39; /* lock Ram to end at 0x3FFF */ - ___INITEE = 0x09; /* lock EEPROM block to end at 0x0fff */ -#endif - - /* Here user defined code could be inserted, the stack could be used */ -#if defined(_DO_DISABLE_COP_) - _DISABLE_COP(); -#endif - - /* Example : Set up WinDef Register to allow Paging */ -#ifdef HC812A4 /* HC12 A4 derivative needs WINDEF to configure which pages are available */ -#if (__ENABLE_EPAGE__ != 0 || __ENABLE_DPAGE__ != 0 || __ENABLE_PPAGE__ != 0) - WINDEF= __ENABLE_EPAGE__ | __ENABLE_DPAGE__ | __ENABLE_PPAGE__; -#endif -#endif - Init(); /* zero out, copy down, call constructors */ - /* Here user defined code could be inserted, all global variables are initilized */ -#if defined(_DO_ENABLE_COP_) - _ENABLE_COP(1); -#endif - - /* call main() */ - (*_startupData.main)(); - - /* call destructors. Only done when this file is compiled as C++ and for the ELF object file format */ - /* the HIWARE object file format does not support this */ -#if defined( __ELF_OBJECT_FILE_FORMAT__) && defined(__cplusplus ) - Fini(); -#endif - - } /* end loop forever */ -} diff --git a/Demo/HCS12_CodeWarrior_small/Sources/datapage.c b/Demo/HCS12_CodeWarrior_small/Sources/datapage.c deleted file mode 100644 index 80be5c566..000000000 --- a/Demo/HCS12_CodeWarrior_small/Sources/datapage.c +++ /dev/null @@ -1,843 +0,0 @@ -/****************************************************************************** - FILE : datapage.c - PURPOSE : paged data access runtime routines - MACHINE : Motorola 68HC12 (Target) - LANGUAGE : ANSI-C - HISTORY : 21.7.96 first version created -******************************************************************************/ - -/* - According to the -Cp option of the compiler the - __DPAGE__, __PPAGE__ and __EPAGE__ macros are defined. - If none of them is given as argument, then no page accesses should occur and - this runtime routine should not be used ! - To be on the save side, the runtime routines are created anyway. - If some of the -Cp options are given an adapted versions which only covers the - needed cases is produced. -*/ - -/* if no compiler option -Cp is given, it is assumed that all possible are given : */ - -/* Compile with option -DHCS12 to activate this code */ -#if defined(HCS12) || defined(_HCS12) /* HCS12 family has PPAGE register only at 0x30 */ -#define PPAGE_ADDR (0x30+REGISTER_BASE) -#ifndef __PPAGE__ /* may be set already by option -CPPPAGE */ -#define __PPAGE__ -#endif -/* Compile with option -DDG128 to activate this code */ -#elif defined DG128 /* HC912DG128 derivative has PPAGE register only at 0xFF */ -#define PPAGE_ADDR (0xFF+REGISTER_BASE) -#ifndef __PPAGE__ /* may be set already by option -CPPPAGE */ -#define __PPAGE__ -#endif -#elif defined(HC812A4) -/* all setting default to A4 already */ -#endif - - -#if !defined(__EPAGE__) && !defined(__PPAGE__) && !defined(__DPAGE__) -/* as default use all page registers */ -#define __DPAGE__ -#define __EPAGE__ -#define __PPAGE__ -#endif - -/* modify the following defines to your memory configuration */ - -#define EPAGE_LOW_BOUND 0x400u -#define EPAGE_HIGH_BOUND 0x7ffu - -#define DPAGE_LOW_BOUND 0x7000u -#define DPAGE_HIGH_BOUND 0x7fffu - -#define PPAGE_LOW_BOUND (DPAGE_HIGH_BOUND+1) -#define PPAGE_HIGH_BOUND 0xBFFFu - -#define REGISTER_BASE 0x0u -#ifndef DPAGE_ADDR -#define DPAGE_ADDR (0x34u+REGISTER_BASE) -#endif -#ifndef EPAGE_ADDR -#define EPAGE_ADDR (0x36u+REGISTER_BASE) -#endif -#ifndef PPAGE_ADDR -#define PPAGE_ADDR (0x35u+REGISTER_BASE) -#endif - -/* - The following parts about the defines are assumed in the code of _GET_PAGE_REG : - - the memory region controlled by DPAGE is above the area controlled by the EPAGE and - below the area controlled by the PPAGE. - - the lower bound of the PPAGE area is equal to be the higher bound of the DPAGE area + 1 -*/ -#if EPAGE_LOW_BOUND >= EPAGE_HIGH_BOUND || EPAGE_HIGH_BOUND >= DPAGE_LOW_BOUND || DPAGE_LOW_BOUND >= DPAGE_HIGH_BOUND || DPAGE_HIGH_BOUND >= PPAGE_LOW_BOUND || PPAGE_LOW_BOUND >= PPAGE_HIGH_BOUND -#error /* please adapt _GET_PAGE_REG for this non default page configuration */ -#endif - -#if DPAGE_HIGH_BOUND+1 != PPAGE_LOW_BOUND -#error /* please adapt _GET_PAGE_REG for this non default page configuration */ -#endif - -#include "hidef.h" -#include "non_bank.sgm" -#include "runtime.sgm" - -/* this module does either control if any access is in the bounds of the specified page or */ -/* ,if only one page is specified, just use this page. */ -/* This behavior is controlled by the define USE_SEVERAL_PAGES. */ -/* If !USE_SEVERAL_PAGES does increase the performance significantly */ -/* NOTE : When !USE_SEVERAL_PAGES, the page is also set for accesses outside of the area controlled */ -/* by this single page. But this is usually no problem because the page is set again before any other access */ - -#if !defined(__DPAGE__) && !defined(__EPAGE__) && !defined(__PPAGE__) -/* no page at all is specified */ -/* only specifing the right pages will speed up these functions a lot */ -#define USE_SEVERAL_PAGES 1 -#elif defined(__DPAGE__) && defined(__EPAGE__) || defined(__DPAGE__) && defined(__PPAGE__) || defined(__EPAGE__) && defined(__PPAGE__) -/* more than one page register is used */ -#define USE_SEVERAL_PAGES 1 -#else - -#define USE_SEVERAL_PAGES 0 - -#if defined(__DPAGE__) /* check which pages are used */ -#define PAGE_ADDR PPAGE_ADDR -#elif defined(__EPAGE__) -#define PAGE_ADDR EPAGE_ADDR -#elif defined(__PPAGE__) -#define PAGE_ADDR PPAGE_ADDR -#else /* we dont know which page, decide it at runtime */ -#error /* must not happen */ -#endif - -#endif - - -#if USE_SEVERAL_PAGES /* only needed for several pages support */ -/*--------------------------- _GET_PAGE_REG -------------------------------- - Runtime routine to detect the right register depending on the 16 bit offset part - of an address. - This function is only used by the functions below. - - Depending on the compiler options -Cp different versions of _GET_PAGE_REG are produced. - - Arguments : - - Y : offset part of an address - - Result : - if address Y is controlled by a page register : - - X : address of page register if Y is controlled by an page register - - Zero flag cleared - - all other registers remain unchanged - - if address Y is not controlled by a page register : - - Zero flag is set - - all registers remain unchanged - - --------------------------- _GET_PAGE_REG ----------------------------------*/ - -#if defined(__DPAGE__) - -#ifdef __cplusplus -extern "C" -#endif -#pragma NO_ENTRY -#pragma NO_EXIT -#pragma NO_FRAME - -static void NEAR _GET_PAGE_REG(void) { /*lint -esym(528, _GET_PAGE_REG) used in asm code */ - asm { -L_DPAGE: - CPY #DPAGE_LOW_BOUND ; test of lower bound of DPAGE -#if defined(__EPAGE__) - BLO L_EPAGE ; EPAGE accesses are possible -#else - BLO L_NOPAGE ; no paged memory below accesses -#endif - CPY #DPAGE_HIGH_BOUND ; test of higher bound DPAGE/lower bound PPAGE -#if defined(__PPAGE__) - BHI L_PPAGE ; EPAGE accesses are possible -#else - BHI L_NOPAGE ; no paged memory above accesses -#endif -FOUND_DPAGE: - LDX #DPAGE_ADDR ; load page register address and clear zero flag - RTS - -#if defined(__PPAGE__) -L_PPAGE: - CPY #PPAGE_HIGH_BOUND ; test of higher bound of PPAGE - BHI L_NOPAGE -FOUND_PPAGE: - LDX #PPAGE_ADDR ; load page register address and clear zero flag - RTS -#endif - -#if defined(__EPAGE__) -L_EPAGE: - CPY #EPAGE_LOW_BOUND ; test of lower bound of EPAGE - BLO L_NOPAGE - CPY #EPAGE_HIGH_BOUND ; test of higher bound of EPAGE - BHI L_NOPAGE - -FOUND_EPAGE: - LDX #EPAGE_ADDR ; load page register address and clear zero flag - RTS -#endif - -L_NOPAGE: - ORCC #0x04 ; sets zero flag - RTS - } -} - -#else /* !defined(__DPAGE__) */ - -#if defined( __PPAGE__ ) - -#ifdef __cplusplus -extern "C" -#endif -#pragma NO_ENTRY -#pragma NO_EXIT -#pragma NO_FRAME - -static void NEAR _GET_PAGE_REG(void) { /*lint -esym(528, _GET_PAGE_REG) used in asm code */ - asm { -L_PPAGE: - CPY #PPAGE_LOW_BOUND ; test of lower bound of PPAGE -#if defined( __EPAGE__ ) - BLO L_EPAGE -#else - BLO L_NOPAGE ; no paged memory below -#endif - CPY #PPAGE_HIGH_BOUND ; test of higher bound PPAGE - BHI L_NOPAGE -FOUND_PPAGE: - LDX #PPAGE_ADDR ; load page register address and clear zero flag - RTS -#if defined( __EPAGE__ ) -L_EPAGE: - CPY #EPAGE_LOW_BOUND ; test of lower bound of EPAGE - BLO L_NOPAGE - CPY #EPAGE_HIGH_BOUND ; test of higher bound of EPAGE - BHI L_NOPAGE -FOUND_EPAGE: - LDX #EPAGE_ADDR ; load page register address and clear zero flag - RTS -#endif - -L_NOPAGE: ; not in any allowed page area - ; its a far access to a non paged variable - ORCC #0x04 ; sets zero flag - RTS - } -} - -#else /* !defined(__DPAGE__ ) && !defined( __PPAGE__) */ -#if defined(__EPAGE__) - -#ifdef __cplusplus -extern "C" -#endif -#pragma NO_ENTRY -#pragma NO_EXIT -#pragma NO_FRAME - -static void NEAR _GET_PAGE_REG(void) { /*lint -esym(528, _GET_PAGE_REG) used in asm code */ - asm { -L_EPAGE: - CPY #EPAGE_LOW_BOUND ; test of lower bound of EPAGE - BLO L_NOPAGE - CPY #EPAGE_HIGH_BOUND ; test of higher bound of EPAGE - BHI L_NOPAGE -FOUND_EPAGE: - LDX #EPAGE_ADDR ; load page register address and clear zero flag - RTS - -L_NOPAGE: ; not in any allowed page area - ; its a far access to a non paged variable - ORCC #0x04 ; sets zero flag - RTS - } -} - -#endif /* defined(__EPAGE__) */ -#endif /* defined(__PPAGE__) */ -#endif /* defined(__DPAGE__) */ - -#endif /* USE_SEVERAL_PAGES */ - -/*--------------------------- _SET_PAGE -------------------------------- - Runtime routine to set the right page register. This routine is used if the compiler - does not know the right page register, i.e. if the option -Cp is used for more than - one pageregister or if the runtime option is used for one of the -Cp options. - - Arguments : - - offset part of an address in the Y register - - page part of an address in the B register - - Result : - - page part written into the correct page register. - - the old page register content is destroyed - - all processor registers remains unchanged - --------------------------- _SET_PAGE ----------------------------------*/ - -#ifdef __cplusplus -extern "C" -#endif -#pragma NO_ENTRY -#pragma NO_EXIT -#pragma NO_FRAME - -void NEAR _SET_PAGE(void) { -#if USE_SEVERAL_PAGES - asm { - PSHX ; save X register - __PIC_JSR(_GET_PAGE_REG) - BEQ L_NOPAGE - STAB 0,X ; set page register -L_NOPAGE: - PULX ; restore X register - RTS - } -#else /* USE_SEVERAL_PAGES */ - asm { - STAB PAGE_ADDR ; set page register - RTS - } -#endif /* USE_SEVERAL_PAGES */ -} - -/*--------------------------- _LOAD_FAR_8 -------------------------------- - This runtime routine is used to access paged memory via a runtime function. - It may also be used if the compiler option -Cp is not used with the runtime argument. - - Arguments : - - offset part of an address in the Y register - - page part of an address in the B register - - Result : - - value to be read in the B register - - all other registers remains unchanged - - all page register still contain the same value - --------------------------- _LOAD_FAR_8 ----------------------------------*/ - -#ifdef __cplusplus -extern "C" -#endif -#pragma NO_ENTRY -#pragma NO_EXIT -#pragma NO_FRAME - -void NEAR _LOAD_FAR_8(void) { -#if USE_SEVERAL_PAGES - asm { - PSHX ; save X register - __PIC_JSR(_GET_PAGE_REG) - BEQ L_NOPAGE - PSHA ; save A register - LDAA 0,X ; save page register - STAB 0,X ; set page register - LDAB 0,Y ; actual load, overwrites page - STAA 0,X ; restore page register - PULA ; restore A register - PULX ; restore X register - RTS -L_NOPAGE: - LDAB 0,Y ; actual load, overwrites page - PULX ; restore X register - RTS - } -#else /* USE_SEVERAL_PAGES */ - asm { - PSHA ; save A register - LDAA PAGE_ADDR ; save page register - STAB PAGE_ADDR ; set page register - LDAB 0,Y ; actual load, overwrites page - STAA PAGE_ADDR ; restore page register - PULA ; restore A register - RTS - } -#endif /* USE_SEVERAL_PAGES */ -} - -/*--------------------------- _LOAD_FAR_16 -------------------------------- - This runtime routine is used to access paged memory via a runtime function. - It may also be used if the compiler option -Cp is not used with the runtime argument. - - Arguments : - - offset part of an address in the Y register - - page part of an address in the B register - - Result : - - value to be read in the Y register - - all other registers remains unchanged - - all page register still contain the same value - --------------------------- _LOAD_FAR_16 ----------------------------------*/ - -#ifdef __cplusplus -extern "C" -#endif -#pragma NO_ENTRY -#pragma NO_EXIT -#pragma NO_FRAME - -void NEAR _LOAD_FAR_16(void) { -#if USE_SEVERAL_PAGES - asm { - PSHX ; save X register - __PIC_JSR(_GET_PAGE_REG) - BEQ L_NOPAGE - PSHA ; save A register - LDAA 0,X ; save page register - STAB 0,X ; set page register - LDY 0,Y ; actual load, overwrites address - STAA 0,X ; restore page register - PULA ; restore A register - PULX ; restore X register - RTS -L_NOPAGE: - LDY 0,Y ; actual load, overwrites address - PULX ; restore X register - RTS - } -#else /* USE_SEVERAL_PAGES */ - asm { - PSHA ; save A register - LDAA PAGE_ADDR ; save page register - STAB PAGE_ADDR ; set page register - LDY 0,Y ; actual load, overwrites address - STAA PAGE_ADDR ; restore page register - PULA ; restore A register - RTS - } -#endif /* USE_SEVERAL_PAGES */ -} -/*--------------------------- _LOAD_FAR_24 -------------------------------- - This runtime routine is used to access paged memory via a runtime function. - It may also be used if the compiler option -Cp is not used with the runtime argument. - - Arguments : - - offset part of an address in the Y register - - page part of an address in the B register - - Result : - - value to be read in the Y:B registers - - all other registers remains unchanged - - all page register still contain the same value - --------------------------- _LOAD_FAR_24 ----------------------------------*/ - -#ifdef __cplusplus -extern "C" -#endif -#pragma NO_ENTRY -#pragma NO_EXIT -#pragma NO_FRAME - -void NEAR _LOAD_FAR_24(void) { -#if USE_SEVERAL_PAGES - asm { - PSHX ; save X register - __PIC_JSR(_GET_PAGE_REG) - BEQ L_NOPAGE - PSHA ; save A register - LDAA 0,X ; save page register - STAB 0,X ; set page register - LDAB 0,Y ; actual load, overwrites page of address - LDY 1,Y ; actual load, overwrites offset of address - STAA 0,X ; restore page register - PULA ; restore A register - PULX ; restore X register - RTS -L_NOPAGE: - LDAB 0,Y ; actual load, overwrites page of address - LDY 1,Y ; actual load, overwrites offset of address - PULX ; restore X register - RTS - } -#else /* USE_SEVERAL_PAGES */ - asm { - PSHA ; save A register - LDAA PAGE_ADDR ; save page register - STAB PAGE_ADDR ; set page register - LDAB 0,Y ; actual load, overwrites page of address - LDY 1,Y ; actual load, overwrites offset of address - STAA PAGE_ADDR ; restore page register - PULA ; restore A register - RTS - } -#endif /* USE_SEVERAL_PAGES */ - -} - -/*--------------------------- _LOAD_FAR_32 -------------------------------- - This runtime routine is used to access paged memory via a runtime function. - It may also be used if the compiler option -Cp is not used with the runtime argument. - - Arguments : - - offset part of an address in the Y register - - page part of an address in the B register - - Result : - - low 16 bit of value to be read in the D registers - - high 16 bit of value to be read in the Y registers - - all other registers remains unchanged - - all page register still contain the same value - --------------------------- _LOAD_FAR_32 ----------------------------------*/ - -#ifdef __cplusplus -extern "C" -#endif -#pragma NO_ENTRY -#pragma NO_EXIT -#pragma NO_FRAME - -void NEAR _LOAD_FAR_32(void) { -#if USE_SEVERAL_PAGES - asm { - PSHX ; save X register - __PIC_JSR(_GET_PAGE_REG) - BEQ L_NOPAGE - LDAA 0,X ; save page register - PSHA ; put it onto the stack - STAB 0,X ; set page register - LDD 2,Y ; actual load, low word - LDY 0,Y ; actual load, high word - MOVB 1,SP+,0,X ; restore page register - PULX ; restore X register - RTS -L_NOPAGE: - LDD 2,Y ; actual load, low word - LDY 0,Y ; actual load, high word - PULX ; restore X register - RTS - } -#else /* USE_SEVERAL_PAGES */ - asm { - LDAA PAGE_ADDR ; save page register - PSHA ; put it onto the stack - STAB PAGE_ADDR ; set page register - LDD 2,Y ; actual load, low word - LDY 0,Y ; actual load, high word - MOVB 1,SP+,PAGE_ADDR; restore page register - RTS - } -#endif /* USE_SEVERAL_PAGES */ -} - -/*--------------------------- _STORE_FAR_8 -------------------------------- - This runtime routine is used to access paged memory via a runtime function. - It may also be used if the compiler option -Cp is not used with the runtime argument. - - Arguments : - - offset part of an address in the Y register - - page part of an address in the B register - - value to be stored in the B register - - Result : - - value stored at the address - - all registers remains unchanged - - all page register still contain the same value - --------------------------- _STORE_FAR_8 ----------------------------------*/ - -#ifdef __cplusplus -extern "C" -#endif -#pragma NO_ENTRY -#pragma NO_EXIT -#pragma NO_FRAME - -void NEAR _STORE_FAR_8(void) { -#if USE_SEVERAL_PAGES - asm { - PSHX ; save X register - __PIC_JSR(_GET_PAGE_REG) - BEQ L_NOPAGE - PSHB ; save B register - LDAB 0,X ; save page register - MOVB 0,SP, 0,X ; set page register - STAA 0,Y ; store the value passed in A - STAB 0,X ; restore page register - PULB ; restore B register - PULX ; restore X register - RTS -L_NOPAGE: - STAA 0,Y ; store the value passed in A - PULX ; restore X register - RTS - } -#else /* USE_SEVERAL_PAGES */ - asm { - PSHB ; save A register - LDAB PAGE_ADDR ; save page register - MOVB 0,SP,PAGE_ADDR ; set page register - STAA 0,Y ; store the value passed in A - STAB PAGE_ADDR ; restore page register - PULB ; restore B register - RTS - } -#endif /* USE_SEVERAL_PAGES */ -} - -/*--------------------------- _STORE_FAR_16 -------------------------------- - This runtime routine is used to access paged memory via a runtime function. - It may also be used if the compiler option -Cp is not used with the runtime argument. - - Arguments : - - offset part of an address in the Y register - - page part of an address in the B register - - value to be stored in the X register - - Result : - - value stored at the address - - all registers remains unchanged - - all page register still contain the same value - --------------------------- _STORE_FAR_16 ----------------------------------*/ - -#ifdef __cplusplus -extern "C" -#endif -#pragma NO_ENTRY -#pragma NO_EXIT -#pragma NO_FRAME - -void NEAR _STORE_FAR_16(void) { -#if USE_SEVERAL_PAGES - asm { - PSHX ; save X register - __PIC_JSR(_GET_PAGE_REG) - BEQ L_NOPAGE - - PSHA - LDAA 0,X ; save page register - STAB 0,X ; set page register - MOVW 1,SP, 0,Y ; store the value passed in X - STAA 0,X ; restore page register - PULA ; restore A register - PULX ; restore X register - RTS - -L_NOPAGE: - STX 0,Y ; store the value passed in X - PULX ; restore X register - RTS - } -#else /* USE_SEVERAL_PAGES */ - asm { - PSHA ; save A register - LDAA PAGE_ADDR ; save page register - STAB PAGE_ADDR ; set page register - STX 0,Y ; store the value passed in X - STAA PAGE_ADDR ; restore page register - PULA ; restore A register - RTS - } -#endif /* USE_SEVERAL_PAGES */ -} -/*--------------------------- _STORE_FAR_24 -------------------------------- - This runtime routine is used to access paged memory via a runtime function. - It may also be used if the compiler option -Cp is not used with the runtime argument. - - Arguments : - - offset part of an address in the Y register - - page part of an address in the B register - - value to be stored in the X:A registers (X : low 16 bit, A : high 8 bit) - - Result : - - value stored at the address - - all registers remains unchanged - - all page register still contain the same value - --------------------------- _STORE_FAR_24 ----------------------------------*/ - -#ifdef __cplusplus -extern "C" -#endif -#pragma NO_ENTRY -#pragma NO_EXIT -#pragma NO_FRAME - -void NEAR _STORE_FAR_24(void) { -#if USE_SEVERAL_PAGES - asm { - PSHX ; save X register - __PIC_JSR(_GET_PAGE_REG) - BEQ L_NOPAGE - - PSHA - LDAA 0,X ; save page register - STAB 0,X ; set page register - MOVW 1,SP, 1,Y ; store the value passed in X - MOVB 0,SP, 0,Y ; store the value passed in A - STAA 0,X ; restore page register - PULA ; restore A register - PULX ; restore X register - RTS - -L_NOPAGE: - STX 1,Y ; store the value passed in X - STAA 0,Y ; store the value passed in X - PULX ; restore X register - RTS - } -#else /* USE_SEVERAL_PAGES */ - asm { - PSHA ; save A register - LDAA PAGE_ADDR ; save page register - STAB PAGE_ADDR ; set page register - MOVB 0,SP, 0,Y ; store the value passed in A - STX 1,Y ; store the value passed in X - STAA PAGE_ADDR ; restore page register - PULA ; restore A register - RTS - } -#endif /* USE_SEVERAL_PAGES */ -} -/*--------------------------- _STORE_FAR_32 -------------------------------- - This runtime routine is used to access paged memory via a runtime function. - It may also be used if the compiler option -Cp is not used with the runtime argument. - - Arguments : - - offset part of an address in the Y register - - page part of an address is on the stack at 3,SP (just below the return address) - - value to be stored in the X:D registers (D : low 16 bit, X : high 16 bit) - - Result : - - value stored at the address - - all registers remains unchanged - - the page part is removed from the stack - - all page register still contain the same value - --------------------------- _STORE_FAR_32 ----------------------------------*/ - -#ifdef __cplusplus -extern "C" -#endif -#pragma NO_ENTRY -#pragma NO_EXIT -#pragma NO_FRAME - -void NEAR _STORE_FAR_32(void) { -#if USE_SEVERAL_PAGES - asm { - PSHX ; save X register - __PIC_JSR(_GET_PAGE_REG) - BEQ L_NOPAGE - - PSHD - LDAA 0,X ; save page register - MOVB 6,SP, 0,X ; set page register - MOVW 2,SP, 0,Y ; store the value passed in X (high word) - MOVW 0,SP, 2,Y ; store the value passed in D (low word) - STAA 0,X ; restore page register - PULD ; restore A register - BRA done - -L_NOPAGE: - MOVW 0,SP, 0,Y ; store the value passed in X (high word) - STD 2,Y ; store the value passed in D (low word) -done: - PULX ; restore X register - MOVW 0,SP, 1,+SP ; move return address - RTS - } -#else /* USE_SEVERAL_PAGES */ - asm { - PSHD ; save D register - LDAA PAGE_ADDR ; save page register - LDAB 4,SP ; load page part of address - STAB PAGE_ADDR ; set page register - STX 0,Y ; store the value passed in X - MOVW 0,SP, 2,Y ; store the value passed in D (low word) - STAA PAGE_ADDR ; restore page register - PULD ; restore D register - MOVW 0,SP, 1,+SP ; move return address - RTS - } -#endif /* USE_SEVERAL_PAGES */ -} - -/*--------------------------- _FAR_COPY -------------------------------- - This runtime routine is used to access paged memory via a runtime function. - It may also be used if the compiler option -Cp is not used with the runtime argument. - - Arguments : - - offset part of the source int the X register - - page part of the source in the A register - - offset part of the dest int the Y register - - page part of the dest in the B register - - number of bytes to be copied at 2,SP. The number of bytes is always > 0 - - Result : - - memory area copied - - no registers are saved, i.e. all registers may be destroied - - all page register still contain the same value - - - stack-structure at the loop-label: - 0,SP : destination offset - 2,SP : source page - 3,SP : destination page - 4,SP : source offset - 6,SP : return address - 8,SP : counter, > 0 - --------------------------- _FAR_COPY ----------------------------------*/ - -#ifdef __cplusplus -extern "C" -#endif -#pragma NO_ENTRY -#pragma NO_EXIT -#pragma NO_FRAME - -void NEAR _FAR_COPY(void) { -#if USE_SEVERAL_PAGES - asm { - DEX ; source addr-=1, because loop counter ends at 1 - PSHX ; save source offset - PSHD ; save both pages - DEY ; destination addr-=1, because loop counter ends at 1 - PSHY ; save destination offset - LDX 8,SP ; load counter, assuming counter > 0 - -loop: - LDD 4,SP ; load source offset - LEAY D,X ; calcutate actual source address - LDAB 2,SP ; load source page - __PIC_JSR (_LOAD_FAR_8); load 1 source byte - PSHB ; save value - LDD 0+1,SP ; load destination offset - LEAY D,X ; calcutate acual destination address - PULA ; restore value - LDAB 3,SP ; load destination page - __PIC_JSR (_STORE_FAR_8); store one byte - DEX - BNE loop - LDX 6,SP ; load return address - LEAS 10,SP ; release stack - JMP 0,X ; return - } -#else - asm { - PSHD ; store page registers - TFR X,D - ADDD 4,SP ; calculate source end address - STD 4,SP - PULB ; reload source page - LDAA PAGE_ADDR ; save page register - PSHA -loop: - STAB PAGE_ADDR ; set source page - LDAA 1,X+ ; load value - MOVB 1,SP, PAGE_ADDR ; set destination page - STAA 1,Y+ - CPX 4,SP - BNE loop - - LDAA 2,SP+ ; restore old page value and release stack - STAA PAGE_ADDR ; store it into page register - LDX 4,SP+ ; release stack and load return address - JMP 0,X ; return - } -#endif -} - diff --git a/Demo/HCS12_CodeWarrior_small/bin/Simulator.map b/Demo/HCS12_CodeWarrior_small/bin/Simulator.map deleted file mode 100644 index 64c54c7eb..000000000 --- a/Demo/HCS12_CodeWarrior_small/bin/Simulator.map +++ /dev/null @@ -1,2175 +0,0 @@ - -PROGRAM "E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_small\bin\Simulator.abs" - -********************************************************************************************* -TARGET SECTION ---------------------------------------------------------------------------------------------- -Processor : Motorola HC12 -Memory Model: SMALL -File Format : ELF\Dwarf 2.0 -Linker : SmartLinker V-5.0.22 Build 4047, Feb 17 2004 - -********************************************************************************************* -FILE SECTION ---------------------------------------------------------------------------------------------- -Start12.c.o Model: SMALL, Lang: ANSI-C -STRING.C.o (ansisi.lib) Model: SMALL, Lang: ANSI-C -rtshc12.c.o (ansisi.lib) Model: SMALL, Lang: ANSI-C -Cpu.C.o Model: SMALL, Lang: ANSI-C -Byte1.C.o Model: SMALL, Lang: ANSI-C -IO_Map.C.o Model: SMALL, Lang: ANSI-C -Vectors.c.o Model: SMALL, Lang: ANSI-C -RTOSDemo.C.o Model: SMALL, Lang: ANSI-C -tasks.c.o Model: SMALL, Lang: ANSI-C -queue.c.o Model: SMALL, Lang: ANSI-C -list.c.o Model: SMALL, Lang: ANSI-C -port.c.o Model: SMALL, Lang: ANSI-C -flash.c.o Model: SMALL, Lang: ANSI-C -main.c.o Model: SMALL, Lang: ANSI-C -heap_1.c.o Model: SMALL, Lang: ANSI-C -TickTimer.C.o Model: SMALL, Lang: ANSI-C -PE_Timer.C.o Model: SMALL, Lang: ANSI-C -ParTest.c.o Model: SMALL, Lang: ANSI-C -PollQ.c.o Model: SMALL, Lang: ANSI-C -dynamic.c.o Model: SMALL, Lang: ANSI-C -ButtonInterrupt.C.o Model: SMALL, Lang: ANSI-C - -********************************************************************************************* -STARTUP SECTION ---------------------------------------------------------------------------------------------- -Entry point: 0xC000 (_EntryPoint) -_startupData is allocated at 0xC076 and uses 23 Bytes -extern struct _tagStartup { - unsigned flags 0 - _PFunc main 0xC1FD (main) - long stackOffset 0xFED - unsigned nofZeroOut 1 - _Range pZeroOut 0x800 1982 - _Copy *toCopyDownBeg 0xD3CF - int nofLibInits 0 - _LibInit *libInits 0xC091 - int nofInitBodies 0 - _Cpp *initBodies 0xC093 - int nofFiniBodies 0 - _Cpp *finiBodies 0xC093 -} _startupData; - -********************************************************************************************* -SECTION-ALLOCATION SECTION -Section Name Size Type From To Segment ---------------------------------------------------------------------------------------------- -.data 1 R/W 0x800 0x800 RAM -.init 118 R 0xC000 0xC075 ROM_C000 -.startData 29 R 0xC076 0xC092 ROM_C000 -.rodata1 78 R 0xC093 0xC0E0 ROM_C000 -NON_BANKED 114 R 0xC0E1 0xC152 ROM_C000 -.text 4164 R 0xC153 0xD196 ROM_C000 -.copy 19 R 0xD3CF 0xD3E1 ROM_C000 -.abs_section_3f 1 N/I 0x3F 0x3F .absSeg0 -.abs_section_8d 1 N/I 0x8D 0x8D .absSeg1 -.abs_section_86 1 N/I 0x86 0x86 .absSeg2 -.abs_section_8b 1 N/I 0x8B 0x8B .absSeg3 -.abs_section_ff06 1 N/I 0xFF06 0xFF06 .absSeg4 -.abs_section_ff07 1 N/I 0xFF07 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-Byte1_CODE 28 R 0xD30C 0xD327 ROM_C000 -TickTimer_CODE 157 R 0xD328 0xD3C4 ROM_C000 -ButtonInterrupt_CODE 10 R 0xD3C5 0xD3CE ROM_C000 -Byte1_DATA 8 R/W 0xFB3 0xFBA RAM -TickTimer_DATA 3 R/W 0xFBB 0xFBD RAM -.stack 48 R/W 0xFBE 0xFED RAM - -Summary of section sizes per section type: -READ_ONLY (R): 1462 (dec: 5218) -READ_WRITE (R/W): 7EE (dec: 2030) -NO_INIT (N/I): 100 (dec: 256) - -********************************************************************************************* -VECTOR-ALLOCATION SECTION - Address InitValue InitFunction ---------------------------------------------------------------------------------------------- - -********************************************************************************************* -OBJECT-ALLOCATION SECTION - Name Module Addr hSize dSize Ref Section RLIB ---------------------------------------------------------------------------------------------- -MODULE: -- Start12.c.o -- -- PROCEDURES: - Init C153 29 41 1 .text - _Startup C17C 10 16 1 .text -- VARIABLES: - _startupData C076 17 23 6 .startData -MODULE: -- STRING.C.o (ansisi.lib) -- -- PROCEDURES: - memcpy C18C 26 38 3 .text - memset C1B2 1E 30 1 .text - strncpy C1D0 2D 45 1 .text -- VARIABLES: -MODULE: -- rtshc12.c.o (ansisi.lib) -- -- PROCEDURES: - _LCMP D197 19 25 2 RUNTIME - _LCMP_P D1B0 15 21 2 RUNTIME - _LNEG D1C5 D 13 1 RUNTIME - _LINC D1D2 5 5 4 RUNTIME - _lDivMod D1D7 E3 227 3 RUNTIME - _LDIVU D2BA E 14 1 RUNTIME - _NEG_P D2C8 F 15 4 RUNTIME - _LDIVS D2D7 35 53 1 RUNTIME -- VARIABLES: -MODULE: -- Cpu.C.o -- -- PROCEDURES: - _EntryPoint C000 2E 46 1 .init - PE_low_level_init C02E 48 72 1 .init - Cpu_Interrupt C0E1 1 1 60 NON_BANKED -- VARIABLES: -MODULE: -- Byte1.C.o -- -- PROCEDURES: - Byte1_GetMsk D30C D 13 1 Byte1_CODE - Byte1_NegBit D319 F 15 1 Byte1_CODE -- VARIABLES: - Byte1_Table FB3 8 8 1 Byte1_DATA -MODULE: -- IO_Map.C.o -- -- PROCEDURES: -- VARIABLES: - _ARMCOP 3F 1 1 0 .abs_section_3f - _ATDDIEN 8D 1 1 0 .abs_section_8d - _ATDSTAT0 86 1 1 0 .abs_section_86 - _ATDSTAT1 8B 1 1 0 .abs_section_8b - _BDMCCR FF06 1 1 0 .abs_section_ff06 - _BDMINR FF07 1 1 0 .abs_section_ff07 - _BDMSTS FF01 1 1 0 .abs_section_ff01 - _BKP0H 2B 1 1 0 .abs_section_2b - _BKP0L 2C 1 1 0 .abs_section_2c - _BKP0X 2A 1 1 0 .abs_section_2a - _BKP1H 2E 1 1 0 .abs_section_2e - _BKP1L 2F 1 1 0 .abs_section_2f - _BKP1X 2D 1 1 0 .abs_section_2d - _BKPCT0 28 1 1 0 .abs_section_28 - _BKPCT1 29 1 1 0 .abs_section_29 - _CANBTR0 142 1 1 0 .abs_section_142 - _CANBTR1 143 1 1 0 .abs_section_143 - _CANCTL0 140 1 1 0 .abs_section_140 - _CANCTL1 141 1 1 0 .abs_section_141 - _CANIDAC 14B 1 1 0 .abs_section_14b - _CANIDAR0 150 1 1 0 .abs_section_150 - _CANIDAR1 151 1 1 0 .abs_section_151 - _CANIDAR2 152 1 1 0 .abs_section_152 - _CANIDAR3 153 1 1 0 .abs_section_153 - _CANIDAR4 158 1 1 0 .abs_section_158 - _CANIDAR5 159 1 1 0 .abs_section_159 - _CANIDAR6 15A 1 1 0 .abs_section_15a - _CANIDAR7 15B 1 1 0 .abs_section_15b - _CANIDMR0 154 1 1 0 .abs_section_154 - _CANIDMR1 155 1 1 0 .abs_section_155 - _CANIDMR2 156 1 1 0 .abs_section_156 - _CANIDMR3 157 1 1 0 .abs_section_157 - _CANIDMR4 15C 1 1 0 .abs_section_15c - _CANIDMR5 15D 1 1 0 .abs_section_15d - _CANIDMR6 15E 1 1 0 .abs_section_15e - _CANIDMR7 15F 1 1 0 .abs_section_15f - _CANRFLG 144 1 1 0 .abs_section_144 - _CANRIER 145 1 1 0 .abs_section_145 - _CANRXDLR 16C 1 1 0 .abs_section_16c - _CANRXDSR0 164 1 1 0 .abs_section_164 - _CANRXDSR1 165 1 1 0 .abs_section_165 - _CANRXDSR2 166 1 1 0 .abs_section_166 - _CANRXDSR3 167 1 1 0 .abs_section_167 - _CANRXDSR4 168 1 1 0 .abs_section_168 - _CANRXDSR5 169 1 1 0 .abs_section_169 - _CANRXDSR6 16A 1 1 0 .abs_section_16a - _CANRXDSR7 16B 1 1 0 .abs_section_16b - _CANRXERR 14E 1 1 0 .abs_section_14e - _CANRXIDR0 160 1 1 0 .abs_section_160 - _CANRXIDR1 161 1 1 0 .abs_section_161 - _CANRXIDR2 162 1 1 0 .abs_section_162 - _CANRXIDR3 163 1 1 0 .abs_section_163 - _CANTAAK 149 1 1 0 .abs_section_149 - _CANTARQ 148 1 1 0 .abs_section_148 - _CANTBSEL 14A 1 1 0 .abs_section_14a - _CANTFLG 146 1 1 0 .abs_section_146 - _CANTIER 147 1 1 0 .abs_section_147 - _CANTXDLR 17C 1 1 0 .abs_section_17c - _CANTXDSR0 174 1 1 0 .abs_section_174 - _CANTXDSR1 175 1 1 0 .abs_section_175 - _CANTXDSR2 176 1 1 0 .abs_section_176 - _CANTXDSR3 177 1 1 0 .abs_section_177 - _CANTXDSR4 178 1 1 0 .abs_section_178 - _CANTXDSR5 179 1 1 0 .abs_section_179 - _CANTXDSR6 17A 1 1 0 .abs_section_17a - _CANTXDSR7 17B 1 1 0 .abs_section_17b - _CANTXERR 14F 1 1 0 .abs_section_14f - _CANTXIDR0 170 1 1 0 .abs_section_170 - _CANTXIDR1 171 1 1 0 .abs_section_171 - _CANTXIDR2 172 1 1 0 .abs_section_172 - _CANTXIDR3 173 1 1 0 .abs_section_173 - _CANTXTBPR 17F 1 1 0 .abs_section_17f - _CFORC 41 1 1 0 .abs_section_41 - _CLKSEL 39 1 1 3 .abs_section_39 - _COPCTL 3C 1 1 0 .abs_section_3c - _CRGFLG 37 1 1 1 .abs_section_37 - _CRGINT 38 1 1 0 .abs_section_38 - _CTCTL 3E 1 1 0 .abs_section_3e - _CTFLG 36 1 1 0 .abs_section_36 - _DDRAD 272 1 1 0 .abs_section_272 - _DDRE 9 1 1 0 .abs_section_9 - _DDRJ 26A 1 1 0 .abs_section_26a - _DDRK 33 1 1 0 .abs_section_33 - _DDRM 252 1 1 0 .abs_section_252 - _DDRP 25A 1 1 1 .abs_section_25a - _DDRS 24A 1 1 0 .abs_section_24a - _DDRT 242 1 1 0 .abs_section_242 - _EBICTL E 1 1 0 .abs_section_e - _FCLKDIV 100 1 1 0 .abs_section_100 - _FCMD 106 1 1 0 .abs_section_106 - _FCNFG 103 1 1 0 .abs_section_103 - _FPROT 104 1 1 0 .abs_section_104 - _FSEC 101 1 1 0 .abs_section_101 - _FSTAT 105 1 1 0 .abs_section_105 - _HPRIO 1F 1 1 0 .abs_section_1f - _INITEE 12 1 1 0 .abs_section_12 - _INITRG 11 1 1 0 .abs_section_11 - _INITRM 10 1 1 1 .abs_section_10 - _INTCR 1E 1 1 1 .abs_section_1e - _ITCR 15 1 1 0 .abs_section_15 - _ITEST 16 1 1 0 .abs_section_16 - _MEMSIZ0 1C 1 1 0 .abs_section_1c - _MEMSIZ1 1D 1 1 0 .abs_section_1d - _MISC 13 1 1 1 .abs_section_13 - _MODE B 1 1 0 .abs_section_b - _MODRR 247 1 1 0 .abs_section_247 - _MTST0 14 1 1 0 .abs_section_14 - _MTST1 17 1 1 0 .abs_section_17 - _OC7D 43 1 1 0 .abs_section_43 - _OC7M 42 1 1 0 .abs_section_42 - _PACTL 60 1 1 0 .abs_section_60 - _PAFLG 61 1 1 0 .abs_section_61 - _PARTIDH 1A 1 1 0 .abs_section_1a - _PARTIDL 1B 1 1 0 .abs_section_1b - _PEAR A 1 1 0 .abs_section_a - _PERAD 274 1 1 0 .abs_section_274 - _PERJ 26C 1 1 0 .abs_section_26c - _PERM 254 1 1 0 .abs_section_254 - _PERP 25C 1 1 1 .abs_section_25c - _PERS 24C 1 1 0 .abs_section_24c - _PERT 244 1 1 0 .abs_section_244 - _PIEJ 26E 1 1 0 .abs_section_26e - _PIEP 25E 1 1 2 .abs_section_25e - _PIFJ 26F 1 1 0 .abs_section_26f - _PIFP 25F 1 1 2 .abs_section_25f - _PLLCTL 3A 1 1 3 .abs_section_3a - _PORTAD0 8F 1 1 0 .abs_section_8f - _PORTE 8 1 1 0 .abs_section_8 - _PORTK 32 1 1 0 .abs_section_32 - _PPAGE 30 1 1 0 .abs_section_30 - _PPSAD 275 1 1 0 .abs_section_275 - _PPSJ 26D 1 1 0 .abs_section_26d - _PPSM 255 1 1 0 .abs_section_255 - _PPSP 25D 1 1 1 .abs_section_25d - _PPSS 24D 1 1 0 .abs_section_24d - _PPST 245 1 1 0 .abs_section_245 - _PTAD 270 1 1 0 .abs_section_270 - _PTIAD 271 1 1 0 .abs_section_271 - _PTIJ 269 1 1 0 .abs_section_269 - _PTIM 251 1 1 0 .abs_section_251 - _PTIP 259 1 1 0 .abs_section_259 - _PTIS 249 1 1 0 .abs_section_249 - _PTIT 241 1 1 0 .abs_section_241 - _PTJ 268 1 1 0 .abs_section_268 - _PTM 250 1 1 0 .abs_section_250 - _PTP 258 1 1 0 .abs_section_258 - _PTS 248 1 1 0 .abs_section_248 - _PTT 240 1 1 0 .abs_section_240 - _PUCR C 1 1 0 .abs_section_c - _PWMCAE E4 1 1 0 .abs_section_e4 - _PWMCLK E2 1 1 0 .abs_section_e2 - _PWMCTL E5 1 1 1 .abs_section_e5 - _PWME E0 1 1 0 .abs_section_e0 - _PWMPOL E1 1 1 0 .abs_section_e1 - _PWMPRCLK E3 1 1 0 .abs_section_e3 - _PWMSCLA E8 1 1 0 .abs_section_e8 - _PWMSCLB E9 1 1 0 .abs_section_e9 - _PWMSDN FE 1 1 1 .abs_section_fe - _RDRAD 273 1 1 0 .abs_section_273 - _RDRIV D 1 1 0 .abs_section_d - _RDRJ 26B 1 1 0 .abs_section_26b - _RDRM 253 1 1 0 .abs_section_253 - _RDRP 25B 1 1 0 .abs_section_25b - _RDRS 24B 1 1 0 .abs_section_24b - _RDRT 243 1 1 0 .abs_section_243 - _REFDV 35 1 1 1 .abs_section_35 - _RTICTL 3B 1 1 0 .abs_section_3b - _SCICR1 CA 1 1 0 .abs_section_ca - _SCICR2 CB 1 1 0 .abs_section_cb - _SCIDRH CE 1 1 0 .abs_section_ce - _SCIDRL CF 1 1 0 .abs_section_cf - _SCISR1 CC 1 1 0 .abs_section_cc - _SCISR2 CD 1 1 0 .abs_section_cd - _SPIBR DA 1 1 0 .abs_section_da - _SPICR1 D8 1 1 0 .abs_section_d8 - _SPICR2 D9 1 1 0 .abs_section_d9 - _SPIDR DD 1 1 0 .abs_section_dd - _SPISR DB 1 1 0 .abs_section_db - _SYNR 34 1 1 1 .abs_section_34 - _TCTL1 48 1 1 1 .abs_section_48 - _TCTL2 49 1 1 1 .abs_section_49 - _TCTL3 4A 1 1 0 .abs_section_4a - _TCTL4 4B 1 1 0 .abs_section_4b - _TFLG1 4E 1 1 2 .abs_section_4e - _TFLG2 4F 1 1 0 .abs_section_4f - _TIE 4C 1 1 3 .abs_section_4c - _TIOS 40 1 1 1 .abs_section_40 - _TSCR1 46 1 1 3 .abs_section_46 - _TSCR2 4D 1 1 5 .abs_section_4d - _TTOV 47 1 1 1 .abs_section_47 - _WOMM 256 1 1 0 .abs_section_256 - _WOMS 24E 1 1 0 .abs_section_24e - _ATDCTL23 82 2 2 0 .abs_section_82 - _ATDCTL45 84 2 2 0 .abs_section_84 - _ATDDR0 90 2 2 0 .abs_section_90 - _ATDDR1 92 2 2 0 .abs_section_92 - _ATDDR2 94 2 2 0 .abs_section_94 - _ATDDR3 96 2 2 0 .abs_section_96 - _ATDDR4 98 2 2 0 .abs_section_98 - _ATDDR5 9A 2 2 0 .abs_section_9a - _ATDDR6 9C 2 2 0 .abs_section_9c - _ATDDR7 9E 2 2 0 .abs_section_9e - _DDRAB 2 2 2 1 .abs_section_2 - _PACNT 62 2 2 0 .abs_section_62 - _PORTAB 0 2 2 3 .abs_section_0 - _PWMCNT01 EC 2 2 0 .abs_section_ec - _PWMCNT23 EE 2 2 0 .abs_section_ee - _PWMCNT45 F0 2 2 0 .abs_section_f0 - _PWMDTY01 F8 2 2 0 .abs_section_f8 - _PWMDTY23 FA 2 2 0 .abs_section_fa - _PWMDTY45 FC 2 2 0 .abs_section_fc - _PWMPER01 F2 2 2 0 .abs_section_f2 - _PWMPER23 F4 2 2 0 .abs_section_f4 - _PWMPER45 F6 2 2 0 .abs_section_f6 - _SCIBD C8 2 2 0 .abs_section_c8 - _TC0 50 2 2 1 .abs_section_50 - _TC1 52 2 2 0 .abs_section_52 - _TC2 54 2 2 0 .abs_section_54 - _TC3 56 2 2 0 .abs_section_56 - _TC4 58 2 2 0 .abs_section_58 - _TC5 5A 2 2 0 .abs_section_5a - _TC6 5C 2 2 0 .abs_section_5c - _TC7 5E 2 2 1 .abs_section_5e - _TCNT 44 2 2 0 .abs_section_44 -MODULE: -- Vectors.c.o -- -- PROCEDURES: -- VARIABLES: - _vect FF80 80 128 0 .abs_section_ff80 -MODULE: -- RTOSDemo.C.o -- -- PROCEDURES: - main C1FD 8 8 0 .text -- VARIABLES: -MODULE: -- tasks.c.o -- -- PROCEDURES: - xTaskCreate C205 CE 206 11 .text - vTaskDelayUntil C2D3 74 116 3 .text - vTaskDelay C347 46 70 4 .text - uxTaskPriorityGet C38D 26 38 1 .text - vTaskPrioritySet C3B3 69 105 2 .text - vTaskSuspend C41C 44 68 3 .text - vTaskResume C460 59 89 3 .text - vTaskStartScheduler C4B9 30 48 1 .text - vTaskSuspendAll C4E9 13 19 11 .text - xTaskResumeAll C4FC 9F 159 13 .text - xTaskGetTickCount C59B 17 23 2 .text - vTaskIncrementTick C5B2 81 129 2 .text - vTaskSwitchContext C633 5B 91 3 .text - vTaskPlaceOnEventList C68E 41 65 2 .text - xTaskRemoveFromEventList C6CF 6C 108 3 .text - prvIdleTask C73B 10 16 1 .text - prvInitialiseTCBVariables C74B 4C 76 1 .text - prvInitialiseTaskLists C797 3C 60 1 .text - prvCheckTasksWaitingTermination C7D3 1 1 1 .text - prvAllocateTCBAndStack C7D4 33 51 1 .text -- VARIABLES: - STRING.IDLE.2 C093 5 5 1 .rodata1 - pxCurrentTCB 801 2 2 29 .bss - uxCurrentNumberOfTasks 803 1 1 3 .bss - xTickCount 804 2 2 14 .bss - uxTopUsedPriority 806 1 1 2 .bss - uxTopReadyPriority 807 1 1 15 .bss - xSchedulerRunning 808 1 1 3 .bss - uxSchedulerSuspended 809 1 1 6 .bss - uxMissedTicks 80A 1 1 4 .bss - uxTaskNumber.1 80B 1 1 2 .bss - pxReadyTasksLists 80C 3C 60 11 .bss - xDelayedTaskList1 848 F 15 2 .bss - xDelayedTaskList2 857 F 15 2 .bss - pxDelayedTaskList 866 2 2 8 .bss - pxOverflowDelayedTaskList 868 2 2 6 .bss - xPendingReadyList 86A F 15 4 .bss - xSuspendedTaskList 879 F 15 2 .bss -MODULE: -- queue.c.o -- -- PROCEDURES: - xQueueCreate C807 77 119 3 .text - xQueueSend C87E CA 202 3 .text - xQueueSendFromISR C948 54 84 1 .text - xQueueReceive C99C C4 196 4 .text - uxQueueMessagesWaiting CA60 1B 27 1 .text - prvUnlockQueue CA7B 6F 111 4 .text - prvIsQueueEmpty CAEA 21 33 1 .text - prvIsQueueFull CB0B 24 36 1 .text -- VARIABLES: -MODULE: -- list.c.o -- -- PROCEDURES: - vListInitialise CB2F 1F 31 7 .text - vListInitialiseItem CB4E 7 7 3 .text - vListInsertEnd CB55 27 39 7 .text - vListInsert CB7C 5A 90 4 .text - vListRemove CBD6 23 35 13 .text -- VARIABLES: -MODULE: -- port.c.o -- -- PROCEDURES: - pxPortInitialiseStack CBF9 2B 43 1 .text - prvSetupTimerInterrupt CC24 9 9 1 .text - xPortStartScheduler CC2D 4 4 1 .text - xBankedStartScheduler C0E2 F 15 1 NON_BANKED - vPortYield C0F1 16 22 1 NON_BANKED - vPortTickInterrupt C107 1D 29 1 NON_BANKED -- VARIABLES: - uxCriticalNesting 800 1 1 91 .data -MODULE: -- flash.c.o -- -- PROCEDURES: - vStartLEDFlashTasks CC31 26 38 1 .text - vLEDFlashTask CC57 52 82 1 .text -- VARIABLES: - STRING.LEDx.1 C098 5 5 1 .rodata1 - uxFlashTaskNumber 888 1 1 2 .bss -MODULE: -- main.c.o -- -- PROCEDURES: - vMain CCA9 42 66 1 .text - vErrorChecks CCEB 2F 47 1 .text - prvCheckOtherTasksAreStillRunning CD1A 23 35 1 .text - vApplicationIdleHook CD3D 73 115 1 .text - vButtonTask CDB0 4F 79 1 .text - vButtonPush C124 2F 47 1 NON_BANKED -- VARIABLES: - STRING.Check.1 C09D 6 6 1 .rodata1 - STRING.Button.2 C0A3 7 7 1 .rodata1 - xLocalError 889 1 1 3 .bss - uxValToSend.3 88A 1 1 2 .bss - xButtonQueue 88B 2 2 3 .bss -MODULE: -- heap_1.c.o -- -- PROCEDURES: - pvPortMalloc CDFF 30 48 4 .text - vPortFree CE2F 1 1 2 .text -- VARIABLES: - xNextFreeByte 88D 2 2 5 .bss - xHeap 88F 704 1796 1 .bss -MODULE: -- TickTimer.C.o -- -- PROCEDURES: - SetCV D328 F 15 2 TickTimer_CODE - SetPV D337 C 12 1 TickTimer_CODE - HWEnDi D343 11 17 2 TickTimer_CODE - TickTimer_Enable D354 E 14 1 TickTimer_CODE - TickTimer_SetFreqHz D362 4F 79 1 TickTimer_CODE - TickTimer_Init D3B1 14 20 1 TickTimer_CODE -- VARIABLES: - EnUser FBB 1 1 4 TickTimer_DATA - CmpHighVal FBC 2 2 2 TickTimer_DATA -MODULE: -- PE_Timer.C.o -- -- PROCEDURES: - PE_Timer_LngHi1 CE30 43 67 1 .text -- VARIABLES: -MODULE: -- ParTest.c.o -- -- PROCEDURES: - vParTestToggleLED CE73 13 19 4 .text -- VARIABLES: -MODULE: -- PollQ.c.o -- -- PROCEDURES: - vStartPolledQueueTasks CE86 40 64 1 .text - vPolledQueueProducer CEC6 4D 77 1 .text - vPolledQueueConsumer CF13 59 89 1 .text - xArePollingQueuesStillRunning CF6C 1D 29 1 .text -- VARIABLES: - STRING.QConsNB.2 C0AA 8 8 1 .rodata1 - STRING.QProdNB.3 C0B2 8 8 1 .rodata1 - xPollingConsumerCount F93 1 1 3 .bss - xPollingProducerCount F94 1 1 3 .bss - xPolledQueue.1 F95 2 2 3 .bss -MODULE: -- dynamic.c.o -- -- PROCEDURES: - vStartDynamicPriorityTasks CF89 7C 124 1 .text - vLimitedIncrementTask D005 21 33 1 .text - vContinuousIncrementTask D026 30 48 1 .text - vCounterControlTask D056 98 152 3 .text - vQueueSendWhenSuspendedTask D0EE 34 52 1 .text - vQueueReceiveWhenSuspendedTask D122 4E 78 1 .text - xAreDynamicPriorityTasksStillRunning D170 27 39 1 .text -- VARIABLES: - STRING.CNT_INC.1 C0BA 8 8 1 .rodata1 - STRING.LIM_INC.2 C0C2 8 8 1 .rodata1 - STRING.C_CTRL.3 C0CA 7 7 1 .rodata1 - STRING.SUSP_TX.4 C0D1 8 8 1 .rodata1 - STRING.SUSP_RX.5 C0D9 8 8 1 .rodata1 - usCheckVariable F97 2 2 4 .bss - xSuspendedQueueSendError F99 1 1 2 .bss - xSuspendedQueueReceiveError F9A 1 1 3 .bss - ulValueToSend.6 F9B 4 4 5 .bss - ulExpectedValue.7 F9F 4 4 6 .bss - usLastTaskCheck.9 FA3 2 2 2 .bss - xContinousIncrementHandle FA5 2 2 5 .bss - xLimitedIncrementHandle FA7 2 2 2 .bss - ulCounter FA9 4 4 10 .bss - ulReceivedValue.8 FAD 4 4 3 .bss - xSuspendedTestQueue FB1 2 2 3 .common -MODULE: -- ButtonInterrupt.C.o -- -- PROCEDURES: - ButtonInterrupt_Enable D3C5 A 10 1 ButtonInterrupt_CODE -- VARIABLES: - -********************************************************************************************* -MODULE STATISTIC - Name Data Code Const ---------------------------------------------------------------------------------------------- - Start12.c.o 0 57 0 - STRING.C.o (ansisi.lib) 0 113 0 - rtshc12.c.o (ansisi.lib) 0 373 0 - Cpu.C.o 0 119 0 - Byte1.C.o 8 28 0 - IO_Map.C.o 256 0 0 - Vectors.c.o 0 0 128 - RTOSDemo.C.o 0 8 0 - tasks.c.o 135 1538 5 - queue.c.o 0 808 0 - list.c.o 0 202 0 - port.c.o 1 122 0 - flash.c.o 1 120 5 - main.c.o 4 389 13 - heap_1.c.o 1798 49 0 - TickTimer.C.o 3 157 0 - PE_Timer.C.o 0 67 0 - ParTest.c.o 0 19 0 - PollQ.c.o 4 259 16 - dynamic.c.o 28 526 39 - ButtonInterrupt.C.o 0 10 0 - other 48 29 19 - -********************************************************************************************* -SECTION USE IN OBJECT-ALLOCATION SECTION ---------------------------------------------------------------------------------------------- -SECTION: ".text" - Init _Startup memcpy memset strncpy main xTaskCreate vTaskDelayUntil - vTaskDelay uxTaskPriorityGet vTaskPrioritySet vTaskSuspend vTaskResume - vTaskStartScheduler vTaskSuspendAll xTaskResumeAll xTaskGetTickCount - vTaskIncrementTick vTaskSwitchContext vTaskPlaceOnEventList - xTaskRemoveFromEventList prvIdleTask prvInitialiseTCBVariables - prvInitialiseTaskLists prvCheckTasksWaitingTermination prvAllocateTCBAndStack - xQueueCreate xQueueSend xQueueSendFromISR xQueueReceive - uxQueueMessagesWaiting prvUnlockQueue prvIsQueueEmpty prvIsQueueFull - vListInitialise vListInitialiseItem vListInsertEnd vListInsert vListRemove - pxPortInitialiseStack prvSetupTimerInterrupt xPortStartScheduler - vStartLEDFlashTasks vLEDFlashTask vMain vErrorChecks - prvCheckOtherTasksAreStillRunning vApplicationIdleHook vButtonTask - pvPortMalloc vPortFree PE_Timer_LngHi1 vParTestToggleLED - vStartPolledQueueTasks vPolledQueueProducer vPolledQueueConsumer - xArePollingQueuesStillRunning vStartDynamicPriorityTasks - vLimitedIncrementTask vContinuousIncrementTask vCounterControlTask - vQueueSendWhenSuspendedTask vQueueReceiveWhenSuspendedTask - xAreDynamicPriorityTasksStillRunning -SECTION: ".data" - uxCriticalNesting -SECTION: ".bss" - pxCurrentTCB uxCurrentNumberOfTasks xTickCount uxTopUsedPriority - uxTopReadyPriority xSchedulerRunning uxSchedulerSuspended uxMissedTicks - uxTaskNumber.1 pxReadyTasksLists xDelayedTaskList1 xDelayedTaskList2 - pxDelayedTaskList pxOverflowDelayedTaskList xPendingReadyList - xSuspendedTaskList uxFlashTaskNumber xLocalError uxValToSend.3 xButtonQueue - xNextFreeByte xHeap xPollingConsumerCount xPollingProducerCount - xPolledQueue.1 usCheckVariable xSuspendedQueueSendError - xSuspendedQueueReceiveError ulValueToSend.6 ulExpectedValue.7 - usLastTaskCheck.9 xContinousIncrementHandle xLimitedIncrementHandle ulCounter - ulReceivedValue.8 -SECTION: ".init" - _EntryPoint PE_low_level_init -SECTION: ".rodata1" - STRING.IDLE.2 STRING.LEDx.1 STRING.Check.1 STRING.Button.2 STRING.QConsNB.2 - STRING.QProdNB.3 STRING.CNT_INC.1 STRING.LIM_INC.2 STRING.C_CTRL.3 - STRING.SUSP_TX.4 STRING.SUSP_RX.5 -SECTION: "NON_BANKED" - Cpu_Interrupt xBankedStartScheduler vPortYield vPortTickInterrupt - vButtonPush -SECTION: "RUNTIME" - _LCMP _LCMP_P _LNEG _LINC _lDivMod _LDIVU _NEG_P _LDIVS -SECTION: ".common" - xSuspendedTestQueue -SECTION: "Byte1_CODE" - Byte1_GetMsk Byte1_NegBit -SECTION: "TickTimer_CODE" - SetCV SetPV HWEnDi TickTimer_Enable TickTimer_SetFreqHz TickTimer_Init -SECTION: "ButtonInterrupt_CODE" - ButtonInterrupt_Enable -SECTION: "Byte1_DATA" - Byte1_Table -SECTION: ".abs_section_3f" - _ARMCOP -SECTION: ".abs_section_8d" - _ATDDIEN -SECTION: ".abs_section_86" - _ATDSTAT0 -SECTION: ".abs_section_8b" - _ATDSTAT1 -SECTION: ".abs_section_ff06" - _BDMCCR -SECTION: ".abs_section_ff07" - _BDMINR -SECTION: ".abs_section_ff01" - _BDMSTS -SECTION: ".abs_section_2b" - _BKP0H -SECTION: ".abs_section_2c" - _BKP0L -SECTION: ".abs_section_2a" - _BKP0X -SECTION: ".abs_section_2e" - _BKP1H -SECTION: ".abs_section_2f" - _BKP1L -SECTION: ".abs_section_2d" - _BKP1X -SECTION: ".abs_section_28" - _BKPCT0 -SECTION: ".abs_section_29" - _BKPCT1 -SECTION: ".abs_section_142" - _CANBTR0 -SECTION: ".abs_section_143" - _CANBTR1 -SECTION: ".abs_section_140" - _CANCTL0 -SECTION: ".abs_section_141" - _CANCTL1 -SECTION: ".abs_section_14b" - _CANIDAC -SECTION: ".abs_section_150" - _CANIDAR0 -SECTION: ".abs_section_151" - _CANIDAR1 -SECTION: ".abs_section_152" - _CANIDAR2 -SECTION: ".abs_section_153" - _CANIDAR3 -SECTION: ".abs_section_158" - _CANIDAR4 -SECTION: ".abs_section_159" - _CANIDAR5 -SECTION: ".abs_section_15a" - _CANIDAR6 -SECTION: ".abs_section_15b" - _CANIDAR7 -SECTION: ".abs_section_154" - _CANIDMR0 -SECTION: ".abs_section_155" - _CANIDMR1 -SECTION: ".abs_section_156" - _CANIDMR2 -SECTION: ".abs_section_157" - _CANIDMR3 -SECTION: ".abs_section_15c" - _CANIDMR4 -SECTION: ".abs_section_15d" - _CANIDMR5 -SECTION: ".abs_section_15e" - _CANIDMR6 -SECTION: ".abs_section_15f" - _CANIDMR7 -SECTION: ".abs_section_144" - _CANRFLG -SECTION: ".abs_section_145" - _CANRIER -SECTION: ".abs_section_16c" - _CANRXDLR -SECTION: ".abs_section_164" - _CANRXDSR0 -SECTION: ".abs_section_165" - _CANRXDSR1 -SECTION: ".abs_section_166" - _CANRXDSR2 -SECTION: ".abs_section_167" - _CANRXDSR3 -SECTION: ".abs_section_168" - _CANRXDSR4 -SECTION: ".abs_section_169" - _CANRXDSR5 -SECTION: ".abs_section_16a" - _CANRXDSR6 -SECTION: ".abs_section_16b" - _CANRXDSR7 -SECTION: ".abs_section_14e" - _CANRXERR -SECTION: ".abs_section_160" - _CANRXIDR0 -SECTION: ".abs_section_161" - _CANRXIDR1 -SECTION: ".abs_section_162" - _CANRXIDR2 -SECTION: ".abs_section_163" - _CANRXIDR3 -SECTION: ".abs_section_149" - _CANTAAK -SECTION: ".abs_section_148" - _CANTARQ -SECTION: ".abs_section_14a" - _CANTBSEL -SECTION: ".abs_section_146" - _CANTFLG -SECTION: ".abs_section_147" - _CANTIER -SECTION: ".abs_section_17c" - _CANTXDLR -SECTION: ".abs_section_174" - _CANTXDSR0 -SECTION: ".abs_section_175" - _CANTXDSR1 -SECTION: ".abs_section_176" - _CANTXDSR2 -SECTION: ".abs_section_177" - _CANTXDSR3 -SECTION: ".abs_section_178" - _CANTXDSR4 -SECTION: ".abs_section_179" - _CANTXDSR5 -SECTION: ".abs_section_17a" - _CANTXDSR6 -SECTION: ".abs_section_17b" - _CANTXDSR7 -SECTION: ".abs_section_14f" - _CANTXERR -SECTION: ".abs_section_170" - _CANTXIDR0 -SECTION: ".abs_section_171" - _CANTXIDR1 -SECTION: ".abs_section_172" - _CANTXIDR2 -SECTION: ".abs_section_173" - _CANTXIDR3 -SECTION: ".abs_section_17f" - _CANTXTBPR -SECTION: ".abs_section_41" - _CFORC -SECTION: ".abs_section_39" - _CLKSEL -SECTION: ".abs_section_3c" - _COPCTL -SECTION: ".abs_section_37" - _CRGFLG -SECTION: ".abs_section_38" - _CRGINT -SECTION: ".abs_section_3e" - _CTCTL -SECTION: ".abs_section_36" - _CTFLG -SECTION: ".abs_section_272" - _DDRAD -SECTION: ".abs_section_9" - _DDRE -SECTION: ".abs_section_26a" - _DDRJ -SECTION: ".abs_section_33" - _DDRK -SECTION: ".abs_section_252" - _DDRM -SECTION: ".abs_section_25a" - _DDRP -SECTION: ".abs_section_24a" - _DDRS -SECTION: ".abs_section_242" - _DDRT -SECTION: ".abs_section_e" - _EBICTL -SECTION: ".abs_section_100" - _FCLKDIV -SECTION: ".abs_section_106" - _FCMD -SECTION: ".abs_section_103" - _FCNFG -SECTION: ".abs_section_104" - _FPROT -SECTION: ".abs_section_101" - _FSEC -SECTION: ".abs_section_105" - _FSTAT -SECTION: ".abs_section_1f" - _HPRIO -SECTION: ".abs_section_12" - _INITEE -SECTION: ".abs_section_11" - _INITRG -SECTION: ".abs_section_10" - _INITRM -SECTION: ".abs_section_1e" - _INTCR -SECTION: ".abs_section_15" - _ITCR -SECTION: ".abs_section_16" - _ITEST -SECTION: ".abs_section_1c" - _MEMSIZ0 -SECTION: ".abs_section_1d" - _MEMSIZ1 -SECTION: ".abs_section_13" - _MISC -SECTION: ".abs_section_b" - _MODE -SECTION: ".abs_section_247" - _MODRR -SECTION: ".abs_section_14" - _MTST0 -SECTION: ".abs_section_17" - _MTST1 -SECTION: ".abs_section_43" - _OC7D -SECTION: ".abs_section_42" - _OC7M -SECTION: ".abs_section_60" - _PACTL -SECTION: ".abs_section_61" - _PAFLG -SECTION: ".abs_section_1a" - _PARTIDH -SECTION: ".abs_section_1b" - _PARTIDL -SECTION: ".abs_section_a" - _PEAR -SECTION: ".abs_section_274" - _PERAD -SECTION: ".abs_section_26c" - _PERJ -SECTION: ".abs_section_254" - _PERM -SECTION: ".abs_section_25c" - _PERP -SECTION: ".abs_section_24c" - _PERS -SECTION: ".abs_section_244" - _PERT -SECTION: ".abs_section_26e" - _PIEJ -SECTION: ".abs_section_25e" - _PIEP -SECTION: ".abs_section_26f" - _PIFJ -SECTION: ".abs_section_25f" - _PIFP -SECTION: ".abs_section_3a" - _PLLCTL -SECTION: ".abs_section_8f" - _PORTAD0 -SECTION: ".abs_section_8" - _PORTE -SECTION: ".abs_section_32" - _PORTK -SECTION: ".abs_section_30" - _PPAGE -SECTION: ".abs_section_275" - _PPSAD -SECTION: ".abs_section_26d" - _PPSJ -SECTION: ".abs_section_255" - _PPSM -SECTION: ".abs_section_25d" - _PPSP -SECTION: ".abs_section_24d" - _PPSS -SECTION: ".abs_section_245" - _PPST -SECTION: ".abs_section_270" - _PTAD -SECTION: ".abs_section_271" - _PTIAD -SECTION: ".abs_section_269" - _PTIJ -SECTION: ".abs_section_251" - _PTIM -SECTION: ".abs_section_259" - _PTIP -SECTION: ".abs_section_249" - _PTIS -SECTION: ".abs_section_241" - _PTIT -SECTION: ".abs_section_268" - _PTJ -SECTION: ".abs_section_250" - _PTM -SECTION: ".abs_section_258" - _PTP -SECTION: ".abs_section_248" - _PTS -SECTION: ".abs_section_240" - _PTT -SECTION: ".abs_section_c" - _PUCR -SECTION: ".abs_section_e4" - _PWMCAE -SECTION: ".abs_section_e2" - _PWMCLK -SECTION: ".abs_section_e5" - _PWMCTL -SECTION: ".abs_section_e0" - _PWME -SECTION: ".abs_section_e1" - _PWMPOL -SECTION: ".abs_section_e3" - _PWMPRCLK -SECTION: ".abs_section_e8" - _PWMSCLA -SECTION: ".abs_section_e9" - _PWMSCLB -SECTION: ".abs_section_fe" - _PWMSDN -SECTION: ".abs_section_273" - _RDRAD -SECTION: ".abs_section_d" - _RDRIV -SECTION: ".abs_section_26b" - _RDRJ -SECTION: ".abs_section_253" - _RDRM -SECTION: ".abs_section_25b" - _RDRP -SECTION: ".abs_section_24b" - _RDRS -SECTION: ".abs_section_243" - _RDRT -SECTION: ".abs_section_35" - _REFDV -SECTION: ".abs_section_3b" - _RTICTL -SECTION: ".abs_section_ca" - _SCICR1 -SECTION: ".abs_section_cb" - _SCICR2 -SECTION: ".abs_section_ce" - _SCIDRH -SECTION: ".abs_section_cf" - _SCIDRL -SECTION: ".abs_section_cc" - _SCISR1 -SECTION: ".abs_section_cd" - _SCISR2 -SECTION: ".abs_section_da" - _SPIBR -SECTION: ".abs_section_d8" - _SPICR1 -SECTION: ".abs_section_d9" - _SPICR2 -SECTION: ".abs_section_dd" - _SPIDR -SECTION: ".abs_section_db" - _SPISR -SECTION: ".abs_section_34" - _SYNR -SECTION: ".abs_section_48" - _TCTL1 -SECTION: ".abs_section_49" - _TCTL2 -SECTION: ".abs_section_4a" - _TCTL3 -SECTION: ".abs_section_4b" - _TCTL4 -SECTION: ".abs_section_4e" - _TFLG1 -SECTION: ".abs_section_4f" - _TFLG2 -SECTION: ".abs_section_4c" - _TIE -SECTION: ".abs_section_40" - _TIOS -SECTION: ".abs_section_46" - _TSCR1 -SECTION: ".abs_section_4d" - _TSCR2 -SECTION: ".abs_section_47" - _TTOV -SECTION: ".abs_section_256" - _WOMM -SECTION: ".abs_section_24e" - _WOMS -SECTION: ".abs_section_82" - _ATDCTL23 -SECTION: ".abs_section_84" - _ATDCTL45 -SECTION: ".abs_section_90" - _ATDDR0 -SECTION: ".abs_section_92" - _ATDDR1 -SECTION: ".abs_section_94" - _ATDDR2 -SECTION: ".abs_section_96" - _ATDDR3 -SECTION: ".abs_section_98" - _ATDDR4 -SECTION: ".abs_section_9a" - _ATDDR5 -SECTION: ".abs_section_9c" - _ATDDR6 -SECTION: ".abs_section_9e" - _ATDDR7 -SECTION: ".abs_section_2" - _DDRAB -SECTION: ".abs_section_62" - _PACNT -SECTION: ".abs_section_0" - _PORTAB -SECTION: ".abs_section_ec" - _PWMCNT01 -SECTION: ".abs_section_ee" - _PWMCNT23 -SECTION: ".abs_section_f0" - _PWMCNT45 -SECTION: ".abs_section_f8" - _PWMDTY01 -SECTION: ".abs_section_fa" - _PWMDTY23 -SECTION: ".abs_section_fc" - _PWMDTY45 -SECTION: ".abs_section_f2" - _PWMPER01 -SECTION: ".abs_section_f4" - _PWMPER23 -SECTION: ".abs_section_f6" - _PWMPER45 -SECTION: ".abs_section_c8" - _SCIBD -SECTION: ".abs_section_50" - _TC0 -SECTION: ".abs_section_52" - _TC1 -SECTION: ".abs_section_54" - _TC2 -SECTION: ".abs_section_56" - _TC3 -SECTION: ".abs_section_58" - _TC4 -SECTION: ".abs_section_5a" - _TC5 -SECTION: ".abs_section_5c" - _TC6 -SECTION: ".abs_section_5e" - _TC7 -SECTION: ".abs_section_44" - _TCNT -SECTION: ".abs_section_ff80" - _vect -SECTION: "TickTimer_DATA" - EnUser CmpHighVal - -********************************************************************************************* -OBJECT LIST SORTED BY ADDRESS - Name Addr hSize dSize Ref Section RLIB ---------------------------------------------------------------------------------------------- - _PORTAB 0 2 2 3 .abs_section_0 - _DDRAB 2 2 2 1 .abs_section_2 - _PORTE 8 1 1 0 .abs_section_8 - _DDRE 9 1 1 0 .abs_section_9 - _PEAR A 1 1 0 .abs_section_a - _MODE B 1 1 0 .abs_section_b - _PUCR C 1 1 0 .abs_section_c - _RDRIV D 1 1 0 .abs_section_d - _EBICTL E 1 1 0 .abs_section_e - _INITRM 10 1 1 1 .abs_section_10 - _INITRG 11 1 1 0 .abs_section_11 - _INITEE 12 1 1 0 .abs_section_12 - _MISC 13 1 1 1 .abs_section_13 - _MTST0 14 1 1 0 .abs_section_14 - _ITCR 15 1 1 0 .abs_section_15 - _ITEST 16 1 1 0 .abs_section_16 - _MTST1 17 1 1 0 .abs_section_17 - _PARTIDH 1A 1 1 0 .abs_section_1a - _PARTIDL 1B 1 1 0 .abs_section_1b - _MEMSIZ0 1C 1 1 0 .abs_section_1c - _MEMSIZ1 1D 1 1 0 .abs_section_1d - _INTCR 1E 1 1 1 .abs_section_1e - _HPRIO 1F 1 1 0 .abs_section_1f - _BKPCT0 28 1 1 0 .abs_section_28 - _BKPCT1 29 1 1 0 .abs_section_29 - _BKP0X 2A 1 1 0 .abs_section_2a - _BKP0H 2B 1 1 0 .abs_section_2b - _BKP0L 2C 1 1 0 .abs_section_2c - _BKP1X 2D 1 1 0 .abs_section_2d - _BKP1H 2E 1 1 0 .abs_section_2e - _BKP1L 2F 1 1 0 .abs_section_2f - _PPAGE 30 1 1 0 .abs_section_30 - _PORTK 32 1 1 0 .abs_section_32 - _DDRK 33 1 1 0 .abs_section_33 - _SYNR 34 1 1 1 .abs_section_34 - _REFDV 35 1 1 1 .abs_section_35 - _CTFLG 36 1 1 0 .abs_section_36 - _CRGFLG 37 1 1 1 .abs_section_37 - _CRGINT 38 1 1 0 .abs_section_38 - _CLKSEL 39 1 1 3 .abs_section_39 - _PLLCTL 3A 1 1 3 .abs_section_3a - _RTICTL 3B 1 1 0 .abs_section_3b - _COPCTL 3C 1 1 0 .abs_section_3c - _CTCTL 3E 1 1 0 .abs_section_3e - _ARMCOP 3F 1 1 0 .abs_section_3f - _TIOS 40 1 1 1 .abs_section_40 - _CFORC 41 1 1 0 .abs_section_41 - _OC7M 42 1 1 0 .abs_section_42 - _OC7D 43 1 1 0 .abs_section_43 - _TCNT 44 2 2 0 .abs_section_44 - _TSCR1 46 1 1 3 .abs_section_46 - _TTOV 47 1 1 1 .abs_section_47 - _TCTL1 48 1 1 1 .abs_section_48 - _TCTL2 49 1 1 1 .abs_section_49 - _TCTL3 4A 1 1 0 .abs_section_4a - _TCTL4 4B 1 1 0 .abs_section_4b - _TIE 4C 1 1 3 .abs_section_4c - _TSCR2 4D 1 1 5 .abs_section_4d - _TFLG1 4E 1 1 2 .abs_section_4e - _TFLG2 4F 1 1 0 .abs_section_4f - _TC0 50 2 2 1 .abs_section_50 - _TC1 52 2 2 0 .abs_section_52 - _TC2 54 2 2 0 .abs_section_54 - _TC3 56 2 2 0 .abs_section_56 - _TC4 58 2 2 0 .abs_section_58 - _TC5 5A 2 2 0 .abs_section_5a - _TC6 5C 2 2 0 .abs_section_5c - _TC7 5E 2 2 1 .abs_section_5e - _PACTL 60 1 1 0 .abs_section_60 - _PAFLG 61 1 1 0 .abs_section_61 - _PACNT 62 2 2 0 .abs_section_62 - _ATDCTL23 82 2 2 0 .abs_section_82 - _ATDCTL45 84 2 2 0 .abs_section_84 - _ATDSTAT0 86 1 1 0 .abs_section_86 - _ATDSTAT1 8B 1 1 0 .abs_section_8b - _ATDDIEN 8D 1 1 0 .abs_section_8d - _PORTAD0 8F 1 1 0 .abs_section_8f - _ATDDR0 90 2 2 0 .abs_section_90 - _ATDDR1 92 2 2 0 .abs_section_92 - _ATDDR2 94 2 2 0 .abs_section_94 - _ATDDR3 96 2 2 0 .abs_section_96 - _ATDDR4 98 2 2 0 .abs_section_98 - _ATDDR5 9A 2 2 0 .abs_section_9a - _ATDDR6 9C 2 2 0 .abs_section_9c - _ATDDR7 9E 2 2 0 .abs_section_9e - _SCIBD C8 2 2 0 .abs_section_c8 - _SCICR1 CA 1 1 0 .abs_section_ca - _SCICR2 CB 1 1 0 .abs_section_cb - _SCISR1 CC 1 1 0 .abs_section_cc - _SCISR2 CD 1 1 0 .abs_section_cd - _SCIDRH CE 1 1 0 .abs_section_ce - _SCIDRL CF 1 1 0 .abs_section_cf - _SPICR1 D8 1 1 0 .abs_section_d8 - _SPICR2 D9 1 1 0 .abs_section_d9 - _SPIBR DA 1 1 0 .abs_section_da - _SPISR DB 1 1 0 .abs_section_db - _SPIDR DD 1 1 0 .abs_section_dd - _PWME E0 1 1 0 .abs_section_e0 - _PWMPOL E1 1 1 0 .abs_section_e1 - _PWMCLK E2 1 1 0 .abs_section_e2 - _PWMPRCLK E3 1 1 0 .abs_section_e3 - _PWMCAE E4 1 1 0 .abs_section_e4 - _PWMCTL E5 1 1 1 .abs_section_e5 - _PWMSCLA E8 1 1 0 .abs_section_e8 - _PWMSCLB E9 1 1 0 .abs_section_e9 - _PWMCNT01 EC 2 2 0 .abs_section_ec - _PWMCNT23 EE 2 2 0 .abs_section_ee - _PWMCNT45 F0 2 2 0 .abs_section_f0 - _PWMPER01 F2 2 2 0 .abs_section_f2 - _PWMPER23 F4 2 2 0 .abs_section_f4 - _PWMPER45 F6 2 2 0 .abs_section_f6 - _PWMDTY01 F8 2 2 0 .abs_section_f8 - _PWMDTY23 FA 2 2 0 .abs_section_fa - _PWMDTY45 FC 2 2 0 .abs_section_fc - _PWMSDN FE 1 1 1 .abs_section_fe - _FCLKDIV 100 1 1 0 .abs_section_100 - _FSEC 101 1 1 0 .abs_section_101 - _FCNFG 103 1 1 0 .abs_section_103 - _FPROT 104 1 1 0 .abs_section_104 - _FSTAT 105 1 1 0 .abs_section_105 - _FCMD 106 1 1 0 .abs_section_106 - _CANCTL0 140 1 1 0 .abs_section_140 - _CANCTL1 141 1 1 0 .abs_section_141 - _CANBTR0 142 1 1 0 .abs_section_142 - _CANBTR1 143 1 1 0 .abs_section_143 - _CANRFLG 144 1 1 0 .abs_section_144 - _CANRIER 145 1 1 0 .abs_section_145 - _CANTFLG 146 1 1 0 .abs_section_146 - _CANTIER 147 1 1 0 .abs_section_147 - _CANTARQ 148 1 1 0 .abs_section_148 - _CANTAAK 149 1 1 0 .abs_section_149 - _CANTBSEL 14A 1 1 0 .abs_section_14a - _CANIDAC 14B 1 1 0 .abs_section_14b - _CANRXERR 14E 1 1 0 .abs_section_14e - _CANTXERR 14F 1 1 0 .abs_section_14f - _CANIDAR0 150 1 1 0 .abs_section_150 - _CANIDAR1 151 1 1 0 .abs_section_151 - _CANIDAR2 152 1 1 0 .abs_section_152 - _CANIDAR3 153 1 1 0 .abs_section_153 - _CANIDMR0 154 1 1 0 .abs_section_154 - _CANIDMR1 155 1 1 0 .abs_section_155 - _CANIDMR2 156 1 1 0 .abs_section_156 - _CANIDMR3 157 1 1 0 .abs_section_157 - _CANIDAR4 158 1 1 0 .abs_section_158 - _CANIDAR5 159 1 1 0 .abs_section_159 - _CANIDAR6 15A 1 1 0 .abs_section_15a - _CANIDAR7 15B 1 1 0 .abs_section_15b - _CANIDMR4 15C 1 1 0 .abs_section_15c - _CANIDMR5 15D 1 1 0 .abs_section_15d - _CANIDMR6 15E 1 1 0 .abs_section_15e - _CANIDMR7 15F 1 1 0 .abs_section_15f - _CANRXIDR0 160 1 1 0 .abs_section_160 - _CANRXIDR1 161 1 1 0 .abs_section_161 - _CANRXIDR2 162 1 1 0 .abs_section_162 - _CANRXIDR3 163 1 1 0 .abs_section_163 - _CANRXDSR0 164 1 1 0 .abs_section_164 - _CANRXDSR1 165 1 1 0 .abs_section_165 - _CANRXDSR2 166 1 1 0 .abs_section_166 - _CANRXDSR3 167 1 1 0 .abs_section_167 - _CANRXDSR4 168 1 1 0 .abs_section_168 - _CANRXDSR5 169 1 1 0 .abs_section_169 - _CANRXDSR6 16A 1 1 0 .abs_section_16a - _CANRXDSR7 16B 1 1 0 .abs_section_16b - _CANRXDLR 16C 1 1 0 .abs_section_16c - _CANTXIDR0 170 1 1 0 .abs_section_170 - _CANTXIDR1 171 1 1 0 .abs_section_171 - _CANTXIDR2 172 1 1 0 .abs_section_172 - _CANTXIDR3 173 1 1 0 .abs_section_173 - _CANTXDSR0 174 1 1 0 .abs_section_174 - _CANTXDSR1 175 1 1 0 .abs_section_175 - _CANTXDSR2 176 1 1 0 .abs_section_176 - _CANTXDSR3 177 1 1 0 .abs_section_177 - _CANTXDSR4 178 1 1 0 .abs_section_178 - _CANTXDSR5 179 1 1 0 .abs_section_179 - _CANTXDSR6 17A 1 1 0 .abs_section_17a - _CANTXDSR7 17B 1 1 0 .abs_section_17b - _CANTXDLR 17C 1 1 0 .abs_section_17c - _CANTXTBPR 17F 1 1 0 .abs_section_17f - _PTT 240 1 1 0 .abs_section_240 - _PTIT 241 1 1 0 .abs_section_241 - _DDRT 242 1 1 0 .abs_section_242 - _RDRT 243 1 1 0 .abs_section_243 - _PERT 244 1 1 0 .abs_section_244 - _PPST 245 1 1 0 .abs_section_245 - _MODRR 247 1 1 0 .abs_section_247 - _PTS 248 1 1 0 .abs_section_248 - _PTIS 249 1 1 0 .abs_section_249 - _DDRS 24A 1 1 0 .abs_section_24a - _RDRS 24B 1 1 0 .abs_section_24b - _PERS 24C 1 1 0 .abs_section_24c - _PPSS 24D 1 1 0 .abs_section_24d - _WOMS 24E 1 1 0 .abs_section_24e - _PTM 250 1 1 0 .abs_section_250 - _PTIM 251 1 1 0 .abs_section_251 - _DDRM 252 1 1 0 .abs_section_252 - _RDRM 253 1 1 0 .abs_section_253 - _PERM 254 1 1 0 .abs_section_254 - _PPSM 255 1 1 0 .abs_section_255 - _WOMM 256 1 1 0 .abs_section_256 - _PTP 258 1 1 0 .abs_section_258 - _PTIP 259 1 1 0 .abs_section_259 - _DDRP 25A 1 1 1 .abs_section_25a - _RDRP 25B 1 1 0 .abs_section_25b - _PERP 25C 1 1 1 .abs_section_25c - _PPSP 25D 1 1 1 .abs_section_25d - _PIEP 25E 1 1 2 .abs_section_25e - _PIFP 25F 1 1 2 .abs_section_25f - _PTJ 268 1 1 0 .abs_section_268 - _PTIJ 269 1 1 0 .abs_section_269 - _DDRJ 26A 1 1 0 .abs_section_26a - _RDRJ 26B 1 1 0 .abs_section_26b - _PERJ 26C 1 1 0 .abs_section_26c - _PPSJ 26D 1 1 0 .abs_section_26d - _PIEJ 26E 1 1 0 .abs_section_26e - _PIFJ 26F 1 1 0 .abs_section_26f - _PTAD 270 1 1 0 .abs_section_270 - _PTIAD 271 1 1 0 .abs_section_271 - _DDRAD 272 1 1 0 .abs_section_272 - _RDRAD 273 1 1 0 .abs_section_273 - _PERAD 274 1 1 0 .abs_section_274 - _PPSAD 275 1 1 0 .abs_section_275 - uxCriticalNesting 800 1 1 91 .data - pxCurrentTCB 801 2 2 29 .bss - uxCurrentNumberOfTasks 803 1 1 3 .bss - xTickCount 804 2 2 14 .bss - uxTopUsedPriority 806 1 1 2 .bss - uxTopReadyPriority 807 1 1 15 .bss - xSchedulerRunning 808 1 1 3 .bss - uxSchedulerSuspended 809 1 1 6 .bss - uxMissedTicks 80A 1 1 4 .bss - uxTaskNumber.1 80B 1 1 2 .bss - pxReadyTasksLists 80C 3C 60 11 .bss - xDelayedTaskList1 848 F 15 2 .bss - xDelayedTaskList2 857 F 15 2 .bss - pxDelayedTaskList 866 2 2 8 .bss - pxOverflowDelayedTaskList 868 2 2 6 .bss - xPendingReadyList 86A F 15 4 .bss - xSuspendedTaskList 879 F 15 2 .bss - uxFlashTaskNumber 888 1 1 2 .bss - xLocalError 889 1 1 3 .bss - uxValToSend.3 88A 1 1 2 .bss - xButtonQueue 88B 2 2 3 .bss - xNextFreeByte 88D 2 2 5 .bss - xHeap 88F 704 1796 1 .bss - xPollingConsumerCount F93 1 1 3 .bss - xPollingProducerCount F94 1 1 3 .bss - xPolledQueue.1 F95 2 2 3 .bss - usCheckVariable F97 2 2 4 .bss - xSuspendedQueueSendError F99 1 1 2 .bss - xSuspendedQueueReceiveError F9A 1 1 3 .bss - ulValueToSend.6 F9B 4 4 5 .bss - ulExpectedValue.7 F9F 4 4 6 .bss - usLastTaskCheck.9 FA3 2 2 2 .bss - xContinousIncrementHandle FA5 2 2 5 .bss - xLimitedIncrementHandle FA7 2 2 2 .bss - ulCounter FA9 4 4 10 .bss - ulReceivedValue.8 FAD 4 4 3 .bss - xSuspendedTestQueue FB1 2 2 3 .common - Byte1_Table FB3 8 8 1 Byte1_DATA - EnUser FBB 1 1 4 TickTimer_DATA - CmpHighVal FBC 2 2 2 TickTimer_DATA - _EntryPoint C000 2E 46 1 .init - PE_low_level_init C02E 48 72 1 .init - STRING.IDLE.2 C093 5 5 1 .rodata1 - STRING.LEDx.1 C098 5 5 1 .rodata1 - STRING.Check.1 C09D 6 6 1 .rodata1 - STRING.Button.2 C0A3 7 7 1 .rodata1 - STRING.QConsNB.2 C0AA 8 8 1 .rodata1 - STRING.QProdNB.3 C0B2 8 8 1 .rodata1 - STRING.CNT_INC.1 C0BA 8 8 1 .rodata1 - STRING.LIM_INC.2 C0C2 8 8 1 .rodata1 - STRING.C_CTRL.3 C0CA 7 7 1 .rodata1 - STRING.SUSP_TX.4 C0D1 8 8 1 .rodata1 - STRING.SUSP_RX.5 C0D9 8 8 1 .rodata1 - Cpu_Interrupt C0E1 1 1 60 NON_BANKED - xBankedStartScheduler C0E2 F 15 1 NON_BANKED - vPortYield C0F1 16 22 1 NON_BANKED - vPortTickInterrupt C107 1D 29 1 NON_BANKED - vButtonPush C124 2F 47 1 NON_BANKED - Init C153 29 41 1 .text - _Startup C17C 10 16 1 .text - memcpy C18C 26 38 3 .text - memset C1B2 1E 30 1 .text - strncpy C1D0 2D 45 1 .text - main C1FD 8 8 0 .text - xTaskCreate C205 CE 206 11 .text - vTaskDelayUntil C2D3 74 116 3 .text - vTaskDelay C347 46 70 4 .text - uxTaskPriorityGet C38D 26 38 1 .text - vTaskPrioritySet C3B3 69 105 2 .text - vTaskSuspend C41C 44 68 3 .text - vTaskResume C460 59 89 3 .text - vTaskStartScheduler C4B9 30 48 1 .text - vTaskSuspendAll C4E9 13 19 11 .text - xTaskResumeAll C4FC 9F 159 13 .text - xTaskGetTickCount C59B 17 23 2 .text - vTaskIncrementTick C5B2 81 129 2 .text - vTaskSwitchContext C633 5B 91 3 .text - vTaskPlaceOnEventList C68E 41 65 2 .text - xTaskRemoveFromEventList C6CF 6C 108 3 .text - prvIdleTask C73B 10 16 1 .text - prvInitialiseTCBVariables C74B 4C 76 1 .text - prvInitialiseTaskLists C797 3C 60 1 .text - prvCheckTasksWaitingTermination C7D3 1 1 1 .text - prvAllocateTCBAndStack C7D4 33 51 1 .text - xQueueCreate C807 77 119 3 .text - xQueueSend C87E CA 202 3 .text - xQueueSendFromISR C948 54 84 1 .text - xQueueReceive C99C C4 196 4 .text - uxQueueMessagesWaiting CA60 1B 27 1 .text - prvUnlockQueue CA7B 6F 111 4 .text - prvIsQueueEmpty CAEA 21 33 1 .text - prvIsQueueFull CB0B 24 36 1 .text - vListInitialise CB2F 1F 31 7 .text - vListInitialiseItem CB4E 7 7 3 .text - vListInsertEnd CB55 27 39 7 .text - vListInsert CB7C 5A 90 4 .text - vListRemove CBD6 23 35 13 .text - pxPortInitialiseStack CBF9 2B 43 1 .text - prvSetupTimerInterrupt CC24 9 9 1 .text - xPortStartScheduler CC2D 4 4 1 .text - vStartLEDFlashTasks CC31 26 38 1 .text - vLEDFlashTask CC57 52 82 1 .text - vMain CCA9 42 66 1 .text - vErrorChecks CCEB 2F 47 1 .text - prvCheckOtherTasksAreStillRunning CD1A 23 35 1 .text - vApplicationIdleHook CD3D 73 115 1 .text - vButtonTask CDB0 4F 79 1 .text - pvPortMalloc CDFF 30 48 4 .text - vPortFree CE2F 1 1 2 .text - PE_Timer_LngHi1 CE30 43 67 1 .text - vParTestToggleLED CE73 13 19 4 .text - vStartPolledQueueTasks CE86 40 64 1 .text - vPolledQueueProducer CEC6 4D 77 1 .text - vPolledQueueConsumer CF13 59 89 1 .text - xArePollingQueuesStillRunning CF6C 1D 29 1 .text - vStartDynamicPriorityTasks CF89 7C 124 1 .text - vLimitedIncrementTask D005 21 33 1 .text - vContinuousIncrementTask D026 30 48 1 .text - vCounterControlTask D056 98 152 3 .text - vQueueSendWhenSuspendedTask D0EE 34 52 1 .text - vQueueReceiveWhenSuspendedTask D122 4E 78 1 .text - xAreDynamicPriorityTasksStillRunning D170 27 39 1 .text - _LCMP D197 19 25 2 RUNTIME - _LCMP_P D1B0 15 21 2 RUNTIME - _LNEG D1C5 D 13 1 RUNTIME - _LINC D1D2 5 5 4 RUNTIME - _lDivMod D1D7 E3 227 3 RUNTIME - _LDIVU D2BA E 14 1 RUNTIME - _NEG_P D2C8 F 15 4 RUNTIME - _LDIVS D2D7 35 53 1 RUNTIME - Byte1_GetMsk D30C D 13 1 Byte1_CODE - Byte1_NegBit D319 F 15 1 Byte1_CODE - SetCV D328 F 15 2 TickTimer_CODE - SetPV D337 C 12 1 TickTimer_CODE - HWEnDi D343 11 17 2 TickTimer_CODE - TickTimer_Enable D354 E 14 1 TickTimer_CODE - TickTimer_SetFreqHz D362 4F 79 1 TickTimer_CODE - TickTimer_Init D3B1 14 20 1 TickTimer_CODE - ButtonInterrupt_Enable D3C5 A 10 1 ButtonInterrupt_CODE - _BDMSTS FF01 1 1 0 .abs_section_ff01 - _BDMCCR FF06 1 1 0 .abs_section_ff06 - _BDMINR FF07 1 1 0 .abs_section_ff07 - _vect FF80 80 128 0 .abs_section_ff80 - -********************************************************************************************* -UNUSED-OBJECTS SECTION ---------------------------------------------------------------------------------------------- -NOT USED PROCEDURES -STRING.C.o (ansisi.lib): - strerror memchr memcmp memcpy2 _memcpy_8bitCount memmove - _memset_clear_8bitCount strlen strset strcat strncat strcpy strcmp strncmp - strchr strrchr strspn strcspn strpbrk strstr strtok strcoll strxfrm -rtshc12.c.o (ansisi.lib): - _BSHL _BSHRS _BSHRU _BDIVMODU _BDIVMODS _ISHL _ISHRU _ISHRS _LSHL _LSHRU - _LSHRS _LADD _LSUB _LAND _LOR _LXOR _LCMP_PP _LABS _LCOM _LDEC _LMUL _LMODU - _LMODS _ILSEXT _LTEST _COPY _CASE_DIRECT _CASE_DIRECT_BYTE _CASE_CHECKED - _CASE_CHECKED_BYTE _CASE_SEARCH _CASE_SEARCH_BYTE _CASE_SEARCH_8 - _CASE_SEARCH_8_BYTE _FCALL _FPCMP -Byte1.C.o: - Byte1_PutBit -tasks.c.o: - vTaskEndScheduler uxTaskGetNumberOfTasks -queue.c.o: - xQueueReceiveFromISR vQueueDelete -port.c.o: - vPortEndScheduler -heap_1.c.o: - vPortInitialiseBlocks -TickTimer.C.o: - TickTimer_Interrupt -ParTest.c.o: - vParTestSetLED -ButtonInterrupt.C.o: - ButtonInterrupt_Interrupt -NOT USED VARIABLES -STRING.C.o (ansisi.lib): - STRING..1 next.2 -rtshc12.c.o (ansisi.lib): - _PowOfTwo_8 _PowOfTwo_16 _PowOfTwo_32 -Cpu.C.o: - CpuMode CCR_reg - -********************************************************************************************* -COPYDOWN SECTION ---------------------------------------------------------------------------------------------- -------- ROM-ADDRESS: 0xD3CF ---- SIZE 4 --- -Filling bytes inserted - 00010800 -------- ROM-ADDRESS: 0xD3D3 ---- RAM-ADDRESS: 0x800 ---- SIZE 1 --- -Name of initialized Object : uxCriticalNesting - FF -------- ROM-ADDRESS: 0xD3D4 ---- SIZE 4 --- -Filling bytes inserted - 00080FB3 -------- ROM-ADDRESS: 0xD3D8 ---- RAM-ADDRESS: 0xFB3 ---- SIZE 8 --- -Name of initialized Object : Byte1_Table - 0102040810 204080 -------- ROM-ADDRESS: 0xD3E0 ---- SIZE 2 --- -Filling bytes inserted - 0000 - -********************************************************************************************* -OBJECT-DEPENDENCIES SECTION ---------------------------------------------------------------------------------------------- -_EntryPoint USES _INITRM _MISC _CLKSEL _PLLCTL _SYNR _REFDV - _CRGFLG _Startup -PE_low_level_init USES _TSCR1 _TCTL2 _TCTL1 _TIE _TTOV _TSCR2 _TIOS - _PPSP _PERP _DDRP _PWMCTL _PWMSDN _PORTAB _DDRAB - TickTimer_Init _PIEP _INTCR -xBankedStartScheduler USES prvSetupTimerInterrupt pxCurrentTCB - uxCriticalNesting -vPortYield USES uxCriticalNesting pxCurrentTCB - vTaskSwitchContext -vPortTickInterrupt USES uxCriticalNesting pxCurrentTCB - vTaskIncrementTick vTaskSwitchContext _TFLG1 -vButtonPush USES uxValToSend.3 _PIFP xButtonQueue - xQueueSendFromISR uxCriticalNesting pxCurrentTCB - vTaskSwitchContext -Init USES _startupData -_Startup USES _startupData Init -main USES PE_low_level_init vMain -xTaskCreate USES prvAllocateTCBAndStack - prvInitialiseTCBVariables pxPortInitialiseStack uxCriticalNesting - uxCurrentNumberOfTasks pxCurrentTCB prvInitialiseTaskLists - xSchedulerRunning uxTopUsedPriority uxTaskNumber.1 - uxTopReadyPriority pxReadyTasksLists vListInsertEnd -vTaskDelayUntil USES vTaskSuspendAll xTickCount pxCurrentTCB - vListRemove pxOverflowDelayedTaskList pxDelayedTaskList - vListInsert xTaskResumeAll -vTaskDelay USES vTaskSuspendAll xTickCount pxCurrentTCB - vListRemove pxOverflowDelayedTaskList pxDelayedTaskList - vListInsert xTaskResumeAll -uxTaskPriorityGet USES uxCriticalNesting pxCurrentTCB -vTaskPrioritySet USES uxCriticalNesting pxCurrentTCB - pxReadyTasksLists vListRemove uxTopReadyPriority vListInsertEnd -vTaskSuspend USES uxCriticalNesting pxCurrentTCB vListRemove - xSuspendedTaskList vListInsertEnd -vTaskResume USES uxCriticalNesting pxCurrentTCB vListRemove - uxTopReadyPriority pxReadyTasksLists vListInsertEnd -vTaskStartScheduler USES pxCurrentTCB prvIdleTask STRING.IDLE.2 - xTaskCreate xSchedulerRunning xTickCount - xPortStartScheduler -vTaskSuspendAll USES uxCriticalNesting uxSchedulerSuspended -xTaskResumeAll USES uxCriticalNesting uxSchedulerSuspended - uxCurrentNumberOfTasks vListRemove uxTopReadyPriority - pxReadyTasksLists vListInsertEnd pxCurrentTCB xPendingReadyList - uxMissedTicks vTaskIncrementTick -xTaskGetTickCount USES uxCriticalNesting xTickCount -vTaskIncrementTick USES uxSchedulerSuspended xTickCount - pxDelayedTaskList pxOverflowDelayedTaskList vListRemove - uxTopReadyPriority pxReadyTasksLists vListInsertEnd uxMissedTicks -vTaskSwitchContext USES uxSchedulerSuspended uxTopReadyPriority - pxCurrentTCB pxReadyTasksLists -vTaskPlaceOnEventList USES pxCurrentTCB vListInsert xTickCount vListRemove - pxOverflowDelayedTaskList pxDelayedTaskList -xTaskRemoveFromEventList USES vListRemove uxSchedulerSuspended - uxTopReadyPriority pxReadyTasksLists xPendingReadyList - vListInsertEnd pxCurrentTCB -prvIdleTask USES prvCheckTasksWaitingTermination - pxReadyTasksLists vApplicationIdleHook -prvInitialiseTCBVariables USES strncpy vListInitialiseItem -prvInitialiseTaskLists USES pxReadyTasksLists vListInitialise - xDelayedTaskList1 xDelayedTaskList2 xPendingReadyList - xSuspendedTaskList pxDelayedTaskList pxOverflowDelayedTaskList -prvAllocateTCBAndStack USES pvPortMalloc vPortFree memset -xQueueCreate USES pvPortMalloc vListInitialise vPortFree -xQueueSend USES vTaskSuspendAll uxCriticalNesting xQueueSend - prvIsQueueFull vTaskPlaceOnEventList prvUnlockQueue - xTaskResumeAll memcpy -xQueueSendFromISR USES memcpy xTaskRemoveFromEventList -xQueueReceive USES vTaskSuspendAll uxCriticalNesting xQueueReceive - prvIsQueueEmpty vTaskPlaceOnEventList prvUnlockQueue - xTaskResumeAll memcpy -uxQueueMessagesWaiting USES uxCriticalNesting -prvUnlockQueue USES uxCriticalNesting xTaskRemoveFromEventList -prvIsQueueEmpty USES uxCriticalNesting -prvIsQueueFull USES uxCriticalNesting -vListInitialise USES vListInitialiseItem -prvSetupTimerInterrupt USES TickTimer_SetFreqHz TickTimer_Enable -xPortStartScheduler USES xBankedStartScheduler -vStartLEDFlashTasks USES vLEDFlashTask STRING.LEDx.1 xTaskCreate -vLEDFlashTask USES uxCriticalNesting uxFlashTaskNumber - xTaskGetTickCount vTaskDelayUntil vParTestToggleLED -vMain USES vStartLEDFlashTasks vStartPolledQueueTasks - vStartDynamicPriorityTasks vErrorChecks STRING.Check.1 xTaskCreate - vButtonTask STRING.Button.2 vTaskStartScheduler -vErrorChecks USES xTaskGetTickCount vTaskDelayUntil - prvCheckOtherTasksAreStillRunning _LCMP vParTestToggleLED -prvCheckOtherTasksAreStillRunning USES xArePollingQueuesStillRunning - xAreDynamicPriorityTasksStillRunning xLocalError -vApplicationIdleHook USES _LNEG _LDIVS _LCMP_P uxCriticalNesting - xLocalError -vButtonTask USES xQueueCreate xButtonQueue - ButtonInterrupt_Enable xQueueReceive uxCriticalNesting xLocalError - vParTestToggleLED -pvPortMalloc USES vTaskSuspendAll xNextFreeByte xHeap - xTaskResumeAll -PE_Timer_LngHi1 USES _LCMP -vParTestToggleLED USES uxCriticalNesting Byte1_NegBit -vStartPolledQueueTasks USES xQueueCreate xPolledQueue.1 - vPolledQueueConsumer STRING.QConsNB.2 xTaskCreate - vPolledQueueProducer STRING.QProdNB.3 -vPolledQueueProducer USES xQueueSend uxCriticalNesting - xPollingProducerCount vTaskDelay -vPolledQueueConsumer USES xQueueReceive uxCriticalNesting - xPollingConsumerCount uxQueueMessagesWaiting vTaskDelay -xArePollingQueuesStillRunning USES xPollingConsumerCount xPollingProducerCount -vStartDynamicPriorityTasks USES xQueueCreate xSuspendedTestQueue - vContinuousIncrementTask STRING.CNT_INC.1 ulCounter - xContinousIncrementHandle xTaskCreate vLimitedIncrementTask - STRING.LIM_INC.2 xLimitedIncrementHandle vCounterControlTask - STRING.C_CTRL.3 vQueueSendWhenSuspendedTask STRING.SUSP_TX.4 - vQueueReceiveWhenSuspendedTask STRING.SUSP_RX.5 -vLimitedIncrementTask USES _LINC _LCMP_P vTaskSuspend -vContinuousIncrementTask USES uxTaskPriorityGet vTaskPrioritySet _LINC -vCounterControlTask USES vCounterControlTask xContinousIncrementHandle - vTaskSuspend ulCounter vTaskResume vTaskDelay - vTaskSuspendAll xTaskResumeAll xLimitedIncrementHandle - uxCriticalNesting usCheckVariable -vQueueSendWhenSuspendedTask USES vTaskSuspendAll xSuspendedTestQueue - ulValueToSend.6 xQueueSend xSuspendedQueueSendError - xTaskResumeAll vTaskDelay _LINC -vQueueReceiveWhenSuspendedTask USES vTaskSuspendAll xSuspendedTestQueue - ulReceivedValue.8 xQueueReceive xTaskResumeAll - xSuspendedQueueReceiveError ulExpectedValue.7 _LINC -xAreDynamicPriorityTasksStillRunning USES usCheckVariable usLastTaskCheck.9 - xSuspendedQueueSendError xSuspendedQueueReceiveError -_LDIVU USES _lDivMod -_LDIVS USES _NEG_P _lDivMod -Byte1_GetMsk USES Byte1_Table -Byte1_NegBit USES Byte1_GetMsk _PORTAB -SetCV USES _TC0 _TC7 -SetPV USES _TSCR2 -HWEnDi USES EnUser _TFLG1 _TIE -TickTimer_Enable USES EnUser HWEnDi -TickTimer_SetFreqHz USES _LDIVU PE_Timer_LngHi1 CmpHighVal SetCV -TickTimer_Init USES CmpHighVal EnUser SetCV SetPV HWEnDi -ButtonInterrupt_Enable USES _PIFP _PIEP -_vect USES Cpu_Interrupt vButtonPush vPortTickInterrupt - vPortYield _EntryPoint - -********************************************************************************************* -DEPENDENCY TREE -********************************************************************************************* - main and _Startup Group - | - +- main - | | - | +- PE_low_level_init - | | | - | | +- TickTimer_Init - | | | - | | +- SetCV - | | | - | | +- SetPV - | | | - | | +- HWEnDi - | | - | +- vMain - | | - | +- vStartLEDFlashTasks - | | | - | | +- vLEDFlashTask - | | | | - | | | +- xTaskGetTickCount - | | | | - | | | +- vTaskDelayUntil - | | | | | - | | | | +- vTaskSuspendAll - | | | | | - | | | | +- vListRemove - | | | | | - | | | | +- vListInsert - | | | | | - | | | | +- xTaskResumeAll - | | | | | - | | | | +- vListRemove (see above) - | | | | | - | | | | +- vListInsertEnd - | | | | | - | | | | +- vTaskIncrementTick - | | | | | - | | | | +- vListRemove (see above) - | | | | | - | | | | +- vListInsertEnd (see above) - | | | | - | | | +- vParTestToggleLED - | | | | - | | | +- Byte1_NegBit - | | | | - | | | +- Byte1_GetMsk - | | | - | | +- xTaskCreate - | | | - | | +- prvAllocateTCBAndStack - | | | | - | | | +- pvPortMalloc - | | | | | - | | | | +- vTaskSuspendAll (see above) - | | | | | - | | | | +- xTaskResumeAll (see above) - | | | | - | | | +- vPortFree - | | | | - | | | +- memset - | | | - | | +- prvInitialiseTCBVariables - | | | | - | | | +- strncpy - | | | | - | | | +- vListInitialiseItem - | | | - | | +- pxPortInitialiseStack - | | | - | | +- prvInitialiseTaskLists - | | | | - | | | +- vListInitialise - | | | | - | | | +- vListInitialiseItem (see above) - | | | - | | +- vListInsertEnd (see above) - | | - | +- vStartPolledQueueTasks - | | | - | | +- xQueueCreate - | | | | - | | | +- pvPortMalloc (see above) - | | | | - | | | +- vListInitialise (see above) - | | | | - | | | +- vPortFree (see above) - | | | - | | +- vPolledQueueConsumer - | | | | - | | | +- xQueueReceive - | | | | | - | | | | +- vTaskSuspendAll (see above) - | | | | | - | | | | +- prvIsQueueEmpty - | | | | | - | | | | +- vTaskPlaceOnEventList - | | | | | | - | | | | | +- vListInsert (see above) - | | | | | | - | | | | | +- vListRemove (see above) - | | | | | - | | | | +- prvUnlockQueue - | | | | | | - | | | | | +- xTaskRemoveFromEventList - | | | | | | - | | | | | +- vListRemove (see above) - | | | | | | - | | | | | +- vListInsertEnd (see above) - | | | | | - | | | | +- xTaskResumeAll (see above) - | | | | | - | | | | +- memcpy - | | | | - | | | +- uxQueueMessagesWaiting - | | | | - | | | +- vTaskDelay - | | | | - | | | +- vTaskSuspendAll (see above) - | | | | - | | | +- vListRemove (see above) - | | | | - | | | +- vListInsert (see above) - | | | | - | | | +- xTaskResumeAll (see above) - | | | - | | +- xTaskCreate (see above) - | | | - | | +- vPolledQueueProducer - | | | - | | +- xQueueSend - | | | | - | | | +- vTaskSuspendAll (see above) - | | | | - | | | +- prvIsQueueFull - | | | | - | | | +- vTaskPlaceOnEventList (see above) - | | | | - | | | +- prvUnlockQueue (see above) - | | | | - | | | +- xTaskResumeAll (see above) - | | | | - | | | +- memcpy (see above) - | | | - | | +- vTaskDelay (see above) - | | - | +- vStartDynamicPriorityTasks - | | | - | | +- xQueueCreate (see above) - | | | - | | +- vContinuousIncrementTask - | | | | - | | | +- uxTaskPriorityGet - | | | | - | | | +- vTaskPrioritySet - | | | | | - | | | | +- vListRemove (see above) - | | | | | - | | | | +- vListInsertEnd (see above) - | | | | - | | | +- _LINC - | | | - | | +- xTaskCreate (see above) - | | | - | | +- vLimitedIncrementTask - | | | | - | | | +- _LINC (see above) - | | | | - | | | +- _LCMP_P - | | | | - | | | +- vTaskSuspend - | | | | - | | | +- vListRemove (see above) - | | | | - | | | +- vListInsertEnd (see above) - | | | - | | +- vCounterControlTask - | | | | - | | | +- vTaskSuspend (see above) - | | | | - | | | +- vTaskResume - | | | | | - | | | | +- vListRemove (see above) - | | | | | - | | | | +- vListInsertEnd (see above) - | | | | - | | | +- vTaskDelay (see above) - | | | | - | | | +- vTaskSuspendAll (see above) - | | | | - | | | +- xTaskResumeAll (see above) - | | | - | | +- vQueueSendWhenSuspendedTask - | | | | - | | | +- vTaskSuspendAll (see above) - | | | | - | | | +- xQueueSend (see above) - | | | | - | | | +- xTaskResumeAll (see above) - | | | | - | | | +- vTaskDelay (see above) - | | | | - | | | +- _LINC (see above) - | | | - | | +- vQueueReceiveWhenSuspendedTask - | | | - | | +- vTaskSuspendAll (see above) - | | | - | | +- xQueueReceive (see above) - | | | - | | +- xTaskResumeAll (see above) - | | | - | | +- _LINC (see above) - | | - | +- vErrorChecks - | | | - | | +- xTaskGetTickCount (see above) - | | | - | | +- vTaskDelayUntil (see above) - | | | - | | +- prvCheckOtherTasksAreStillRunning - | | | | - | | | +- xArePollingQueuesStillRunning - | | | | - | | | +- xAreDynamicPriorityTasksStillRunning - | | | - | | +- _LCMP - | | | - | | +- vParTestToggleLED (see above) - | | - | +- xTaskCreate (see above) - | | - | +- vButtonTask - | | | - | | +- xQueueCreate (see above) - | | | - | | +- ButtonInterrupt_Enable - | | | - | | +- xQueueReceive (see above) - | | | - | | +- vParTestToggleLED (see above) - | | - | +- vTaskStartScheduler - | | - | +- prvIdleTask - | | | - | | +- prvCheckTasksWaitingTermination - | | | - | | +- vApplicationIdleHook - | | | - | | +- _LNEG - | | | - | | +- _LDIVS - | | | | - | | | +- _NEG_P - | | | | - | | | +- _lDivMod - | | | - | | +- _LCMP_P (see above) - | | - | +- xTaskCreate (see above) - | | - | +- xPortStartScheduler - | | - | +- xBankedStartScheduler - | | - | +- prvSetupTimerInterrupt - | | - | +- TickTimer_SetFreqHz - | | | - | | +- _LDIVU - | | | | - | | | +- _lDivMod (see above) - | | | - | | +- PE_Timer_LngHi1 - | | | | - | | | +- _LCMP (see above) - | | | - | | +- SetCV (see above) - | | - | +- TickTimer_Enable - | | - | +- HWEnDi (see above) - | - +- _EntryPoint - | - +- _Startup - | - +- Init - - _vect - | - +- Cpu_Interrupt - | - +- vButtonPush - | | - | +- xQueueSendFromISR - | | | - | | +- memcpy (see above) - | | | - | | +- xTaskRemoveFromEventList (see above) - | | - | +- vTaskSwitchContext - | - +- vPortTickInterrupt - | | - | +- vTaskIncrementTick (see above) - | | - | +- vTaskSwitchContext (see above) - | - +- vPortYield - | | - | +- vTaskSwitchContext (see above) - | - +- _EntryPoint (see above) - -********************************************************************************************* -STATISTIC SECTION ---------------------------------------------------------------------------------------------- - -ExeFile: --------- -Number of blocks to be downloaded: 9 -Total size of all blocks to be downloaded: 5218 - diff --git a/Demo/HCS12_CodeWarrior_small/bin/SofTec.map b/Demo/HCS12_CodeWarrior_small/bin/SofTec.map deleted file mode 100644 index d221a8792..000000000 --- a/Demo/HCS12_CodeWarrior_small/bin/SofTec.map +++ /dev/null @@ -1,2175 +0,0 @@ - -PROGRAM "E:\Dev\FreeRTOS\Demo\HCS12_CodeWarrior_small\bin\SofTec.abs" - -********************************************************************************************* -TARGET SECTION ---------------------------------------------------------------------------------------------- -Processor : Motorola HC12 -Memory Model: SMALL -File Format : ELF\Dwarf 2.0 -Linker : SmartLinker V-5.0.22 Build 4047, Feb 17 2004 - -********************************************************************************************* -FILE SECTION ---------------------------------------------------------------------------------------------- -Start12.c.o Model: SMALL, Lang: ANSI-C -STRING.C.o (ansisi.lib) Model: SMALL, Lang: ANSI-C -rtshc12.c.o (ansisi.lib) Model: SMALL, Lang: ANSI-C -tasks.c.o Model: SMALL, Lang: ANSI-C -queue.c.o Model: SMALL, Lang: ANSI-C -list.c.o Model: SMALL, Lang: ANSI-C -port.c.o Model: SMALL, Lang: ANSI-C -flash.c.o Model: SMALL, Lang: ANSI-C -main.c.o Model: SMALL, Lang: ANSI-C -heap_1.c.o Model: SMALL, Lang: ANSI-C -ParTest.c.o Model: SMALL, Lang: ANSI-C -Cpu.C.o Model: SMALL, Lang: ANSI-C -Byte1.C.o Model: SMALL, Lang: ANSI-C -TickTimer.C.o Model: SMALL, Lang: ANSI-C -IO_Map.C.o Model: SMALL, Lang: ANSI-C -PE_Timer.C.o Model: SMALL, Lang: ANSI-C -Vectors.c.o Model: SMALL, Lang: ANSI-C -RTOSDemo.C.o Model: SMALL, Lang: ANSI-C -PollQ.c.o Model: SMALL, Lang: ANSI-C -dynamic.c.o Model: SMALL, Lang: ANSI-C -ButtonInterrupt.C.o Model: SMALL, Lang: ANSI-C - -********************************************************************************************* -STARTUP SECTION ---------------------------------------------------------------------------------------------- -Entry point: 0xC000 (_EntryPoint) -_startupData is allocated at 0xC076 and uses 23 Bytes -extern struct _tagStartup { - unsigned flags 0 - _PFunc main 0xCE77 (main) - long stackOffset 0xFED - unsigned nofZeroOut 1 - _Range pZeroOut 0x800 1982 - _Copy *toCopyDownBeg 0xD3C4 - int nofLibInits 0 - _LibInit *libInits 0xC091 - int nofInitBodies 0 - _Cpp *initBodies 0xC093 - int nofFiniBodies 0 - _Cpp *finiBodies 0xC093 -} _startupData; - -********************************************************************************************* -SECTION-ALLOCATION SECTION -Section Name Size Type From To Segment ---------------------------------------------------------------------------------------------- -.data 1 R/W 0x800 0x800 RAM -.init 118 R 0xC000 0xC075 ROM_C000 -.startData 29 R 0xC076 0xC092 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.absSeg218 -.abs_section_58 2 N/I 0x58 0x59 .absSeg219 -.abs_section_5a 2 N/I 0x5A 0x5B .absSeg220 -.abs_section_5c 2 N/I 0x5C 0x5D .absSeg221 -.abs_section_5e 2 N/I 0x5E 0x5F .absSeg222 -.abs_section_44 2 N/I 0x44 0x45 .absSeg223 -.abs_section_ff80 128 R 0xFF80 0xFFFF .absSeg224 -.bss 1968 R/W 0x801 0xFB0 RAM -RUNTIME 373 R 0xD199 0xD30D ROM_C000 -.common 2 R/W 0xFB1 0xFB2 RAM -TickTimer_CODE 149 R 0xD30E 0xD3A2 ROM_C000 -ButtonInterrupt_CODE 10 R 0xD3A3 0xD3AC ROM_C000 -Byte1_CODE 23 R 0xD3AD 0xD3C3 ROM_C000 -Byte1_DATA 8 R/W 0xFB3 0xFBA RAM -TickTimer_DATA 3 R/W 0xFBB 0xFBD RAM -.stack 48 R/W 0xFBE 0xFED RAM - -Summary of section sizes per section type: -READ_ONLY (R): 1457 (dec: 5207) -READ_WRITE (R/W): 7EE (dec: 2030) -NO_INIT (N/I): 100 (dec: 256) - -********************************************************************************************* -VECTOR-ALLOCATION SECTION - Address InitValue InitFunction ---------------------------------------------------------------------------------------------- - -********************************************************************************************* -OBJECT-ALLOCATION SECTION - Name Module Addr hSize dSize Ref Section RLIB ---------------------------------------------------------------------------------------------- -MODULE: -- Start12.c.o -- -- PROCEDURES: - Init C153 29 41 1 .text - _Startup C17C 10 16 1 .text -- VARIABLES: - _startupData C076 17 23 6 .startData -MODULE: -- STRING.C.o (ansisi.lib) -- -- PROCEDURES: - _memcpy_8bitCount C18C 1C 28 3 .text - memset C1A8 1E 30 1 .text - strncpy C1C6 2D 45 1 .text -- VARIABLES: -MODULE: -- rtshc12.c.o (ansisi.lib) -- -- PROCEDURES: - _LCMP D199 19 25 2 RUNTIME - _LCMP_P D1B2 15 21 2 RUNTIME - _LNEG D1C7 D 13 1 RUNTIME - _LINC D1D4 5 5 4 RUNTIME - _lDivMod D1D9 E3 227 3 RUNTIME - _LDIVU D2BC E 14 1 RUNTIME - _NEG_P D2CA F 15 4 RUNTIME - _LDIVS D2D9 35 53 1 RUNTIME -- VARIABLES: -MODULE: -- tasks.c.o -- -- PROCEDURES: - xTaskCreate C1F3 CE 206 11 .text - vTaskDelayUntil C2C1 74 116 3 .text - vTaskDelay C335 46 70 4 .text - uxTaskPriorityGet C37B 26 38 1 .text - vTaskPrioritySet C3A1 69 105 2 .text - vTaskSuspend C40A 44 68 3 .text - vTaskResume C44E 59 89 3 .text - vTaskStartScheduler C4A7 30 48 1 .text - vTaskSuspendAll C4D7 13 19 11 .text - xTaskResumeAll C4EA 9F 159 13 .text - xTaskGetTickCount C589 17 23 2 .text - vTaskIncrementTick C5A0 81 129 2 .text - vTaskSwitchContext C621 5B 91 3 .text - vTaskPlaceOnEventList C67C 3E 62 2 .text - xTaskRemoveFromEventList C6BA 65 101 3 .text - prvIdleTask C71F 10 16 1 .text - prvInitialiseTCBVariables C72F 4A 74 1 .text - prvInitialiseTaskLists C779 37 55 1 .text - prvCheckTasksWaitingTermination C7B0 1 1 1 .text - prvAllocateTCBAndStack C7B1 39 57 1 .text -- VARIABLES: - STRING.IDLE.2 C093 5 5 1 .rodata1 - pxCurrentTCB 801 2 2 29 .bss - uxCurrentNumberOfTasks 803 1 1 3 .bss - xTickCount 804 2 2 14 .bss - uxTopUsedPriority 806 1 1 2 .bss - uxTopReadyPriority 807 1 1 15 .bss - xSchedulerRunning 808 1 1 3 .bss - uxSchedulerSuspended 809 1 1 6 .bss - uxMissedTicks 80A 1 1 4 .bss - uxTaskNumber.1 80B 1 1 2 .bss - pxReadyTasksLists 80C 3C 60 11 .bss - xDelayedTaskList1 848 F 15 2 .bss - xDelayedTaskList2 857 F 15 2 .bss - pxDelayedTaskList 866 2 2 8 .bss - pxOverflowDelayedTaskList 868 2 2 6 .bss - xPendingReadyList 86A F 15 4 .bss - xSuspendedTaskList 879 F 15 2 .bss -MODULE: -- queue.c.o -- -- PROCEDURES: - xQueueCreate C7EA 76 118 3 .text - xQueueSend C860 C9 201 3 .text - xQueueSendFromISR C929 58 88 1 .text - xQueueReceive C981 C3 195 4 .text - uxQueueMessagesWaiting CA44 1B 27 1 .text - prvUnlockQueue CA5F 6F 111 4 .text - prvIsQueueEmpty CACE 21 33 1 .text - prvIsQueueFull CAEF 24 36 1 .text -- VARIABLES: -MODULE: -- list.c.o -- -- PROCEDURES: - vListInitialise CB13 1F 31 7 .text - vListInitialiseItem CB32 7 7 3 .text - vListInsertEnd CB39 25 37 7 .text - vListInsert CB5E 54 84 4 .text - vListRemove CBB2 23 35 13 .text -- VARIABLES: -MODULE: -- port.c.o -- -- PROCEDURES: - pxPortInitialiseStack CBD5 2B 43 1 .text - prvSetupTimerInterrupt CC00 9 9 1 .text - xPortStartScheduler CC09 4 4 1 .text - xBankedStartScheduler C0E1 F 15 1 NON_BANKED - vPortYield C0F0 16 22 1 NON_BANKED - vPortTickInterrupt C106 1D 29 1 NON_BANKED -- VARIABLES: - uxCriticalNesting 800 1 1 91 .data -MODULE: -- flash.c.o -- -- PROCEDURES: - vStartLEDFlashTasks CC0D 2E 46 1 .text - vLEDFlashTask CC3B 52 82 1 .text -- VARIABLES: - STRING.LEDx.1 C098 5 5 1 .rodata1 - uxFlashTaskNumber 888 1 1 2 .bss -MODULE: -- main.c.o -- -- PROCEDURES: - vMain CC8D 42 66 1 .text - vErrorChecks CCCF 35 53 1 .text - prvCheckOtherTasksAreStillRunning CD04 26 38 1 .text - vApplicationIdleHook CD2A 73 115 1 .text - vButtonTask CD9D 4F 79 1 .text - vButtonPush C123 2F 47 1 NON_BANKED -- VARIABLES: - STRING.Check.1 C09D 6 6 1 .rodata1 - STRING.Button.2 C0A3 7 7 1 .rodata1 - xLocalError 889 1 1 3 .bss - uxValToSend.3 88A 1 1 2 .bss - xButtonQueue 88B 2 2 3 .bss -MODULE: -- heap_1.c.o -- -- PROCEDURES: - pvPortMalloc CDEC 2D 45 4 .text - vPortFree CE19 1 1 2 .text -- VARIABLES: - xNextFreeByte 88D 2 2 4 .bss - xHeap 88F 704 1796 1 .bss -MODULE: -- ParTest.c.o -- -- PROCEDURES: - vParTestToggleLED CE1A 13 19 4 .text -- VARIABLES: -MODULE: -- Cpu.C.o -- -- PROCEDURES: - _EntryPoint C000 2E 46 1 .init - PE_low_level_init C02E 48 72 1 .init - Cpu_Interrupt C152 1 1 60 NON_BANKED -- VARIABLES: -MODULE: -- Byte1.C.o -- -- PROCEDURES: - Byte1_GetMsk D3AD D 13 1 Byte1_CODE - Byte1_NegBit D3BA A 10 1 Byte1_CODE -- VARIABLES: - Byte1_Table FB3 8 8 1 Byte1_DATA -MODULE: -- TickTimer.C.o -- -- PROCEDURES: - SetCV D30E B 11 2 TickTimer_CODE - SetPV D319 9 9 1 TickTimer_CODE - HWEnDi D322 11 17 2 TickTimer_CODE - TickTimer_Enable D333 E 14 1 TickTimer_CODE - TickTimer_SetFreqHz D341 4E 78 1 TickTimer_CODE - TickTimer_Init D38F 14 20 1 TickTimer_CODE -- VARIABLES: - EnUser FBB 1 1 4 TickTimer_DATA - CmpHighVal FBC 2 2 2 TickTimer_DATA -MODULE: -- IO_Map.C.o -- -- PROCEDURES: -- VARIABLES: - _ARMCOP 3F 1 1 0 .abs_section_3f - _ATDDIEN 8D 1 1 0 .abs_section_8d - _ATDSTAT0 86 1 1 0 .abs_section_86 - _ATDSTAT1 8B 1 1 0 .abs_section_8b - _BDMCCR FF06 1 1 0 .abs_section_ff06 - _BDMINR FF07 1 1 0 .abs_section_ff07 - _BDMSTS FF01 1 1 0 .abs_section_ff01 - _BKP0H 2B 1 1 0 .abs_section_2b - _BKP0L 2C 1 1 0 .abs_section_2c - _BKP0X 2A 1 1 0 .abs_section_2a - _BKP1H 2E 1 1 0 .abs_section_2e - _BKP1L 2F 1 1 0 .abs_section_2f - _BKP1X 2D 1 1 0 .abs_section_2d - _BKPCT0 28 1 1 0 .abs_section_28 - _BKPCT1 29 1 1 0 .abs_section_29 - _CANBTR0 142 1 1 0 .abs_section_142 - _CANBTR1 143 1 1 0 .abs_section_143 - _CANCTL0 140 1 1 0 .abs_section_140 - _CANCTL1 141 1 1 0 .abs_section_141 - _CANIDAC 14B 1 1 0 .abs_section_14b - _CANIDAR0 150 1 1 0 .abs_section_150 - _CANIDAR1 151 1 1 0 .abs_section_151 - _CANIDAR2 152 1 1 0 .abs_section_152 - _CANIDAR3 153 1 1 0 .abs_section_153 - _CANIDAR4 158 1 1 0 .abs_section_158 - _CANIDAR5 159 1 1 0 .abs_section_159 - _CANIDAR6 15A 1 1 0 .abs_section_15a - _CANIDAR7 15B 1 1 0 .abs_section_15b - _CANIDMR0 154 1 1 0 .abs_section_154 - _CANIDMR1 155 1 1 0 .abs_section_155 - _CANIDMR2 156 1 1 0 .abs_section_156 - _CANIDMR3 157 1 1 0 .abs_section_157 - _CANIDMR4 15C 1 1 0 .abs_section_15c - _CANIDMR5 15D 1 1 0 .abs_section_15d - _CANIDMR6 15E 1 1 0 .abs_section_15e - _CANIDMR7 15F 1 1 0 .abs_section_15f - _CANRFLG 144 1 1 0 .abs_section_144 - _CANRIER 145 1 1 0 .abs_section_145 - _CANRXDLR 16C 1 1 0 .abs_section_16c - _CANRXDSR0 164 1 1 0 .abs_section_164 - _CANRXDSR1 165 1 1 0 .abs_section_165 - _CANRXDSR2 166 1 1 0 .abs_section_166 - _CANRXDSR3 167 1 1 0 .abs_section_167 - _CANRXDSR4 168 1 1 0 .abs_section_168 - _CANRXDSR5 169 1 1 0 .abs_section_169 - _CANRXDSR6 16A 1 1 0 .abs_section_16a - _CANRXDSR7 16B 1 1 0 .abs_section_16b - _CANRXERR 14E 1 1 0 .abs_section_14e - _CANRXIDR0 160 1 1 0 .abs_section_160 - _CANRXIDR1 161 1 1 0 .abs_section_161 - _CANRXIDR2 162 1 1 0 .abs_section_162 - _CANRXIDR3 163 1 1 0 .abs_section_163 - _CANTAAK 149 1 1 0 .abs_section_149 - _CANTARQ 148 1 1 0 .abs_section_148 - _CANTBSEL 14A 1 1 0 .abs_section_14a - _CANTFLG 146 1 1 0 .abs_section_146 - _CANTIER 147 1 1 0 .abs_section_147 - _CANTXDLR 17C 1 1 0 .abs_section_17c - _CANTXDSR0 174 1 1 0 .abs_section_174 - _CANTXDSR1 175 1 1 0 .abs_section_175 - _CANTXDSR2 176 1 1 0 .abs_section_176 - _CANTXDSR3 177 1 1 0 .abs_section_177 - _CANTXDSR4 178 1 1 0 .abs_section_178 - _CANTXDSR5 179 1 1 0 .abs_section_179 - _CANTXDSR6 17A 1 1 0 .abs_section_17a - _CANTXDSR7 17B 1 1 0 .abs_section_17b - _CANTXERR 14F 1 1 0 .abs_section_14f - _CANTXIDR0 170 1 1 0 .abs_section_170 - _CANTXIDR1 171 1 1 0 .abs_section_171 - _CANTXIDR2 172 1 1 0 .abs_section_172 - _CANTXIDR3 173 1 1 0 .abs_section_173 - _CANTXTBPR 17F 1 1 0 .abs_section_17f - _CFORC 41 1 1 0 .abs_section_41 - _CLKSEL 39 1 1 3 .abs_section_39 - _COPCTL 3C 1 1 0 .abs_section_3c - _CRGFLG 37 1 1 1 .abs_section_37 - _CRGINT 38 1 1 0 .abs_section_38 - _CTCTL 3E 1 1 0 .abs_section_3e - _CTFLG 36 1 1 0 .abs_section_36 - _DDRAD 272 1 1 0 .abs_section_272 - _DDRE 9 1 1 0 .abs_section_9 - _DDRJ 26A 1 1 0 .abs_section_26a - _DDRK 33 1 1 0 .abs_section_33 - _DDRM 252 1 1 0 .abs_section_252 - _DDRP 25A 1 1 1 .abs_section_25a - _DDRS 24A 1 1 0 .abs_section_24a - _DDRT 242 1 1 0 .abs_section_242 - _EBICTL E 1 1 0 .abs_section_e - _FCLKDIV 100 1 1 0 .abs_section_100 - _FCMD 106 1 1 0 .abs_section_106 - _FCNFG 103 1 1 0 .abs_section_103 - _FPROT 104 1 1 0 .abs_section_104 - _FSEC 101 1 1 0 .abs_section_101 - _FSTAT 105 1 1 0 .abs_section_105 - _HPRIO 1F 1 1 0 .abs_section_1f - _INITEE 12 1 1 0 .abs_section_12 - _INITRG 11 1 1 0 .abs_section_11 - _INITRM 10 1 1 1 .abs_section_10 - _INTCR 1E 1 1 1 .abs_section_1e - _ITCR 15 1 1 0 .abs_section_15 - _ITEST 16 1 1 0 .abs_section_16 - _MEMSIZ0 1C 1 1 0 .abs_section_1c - _MEMSIZ1 1D 1 1 0 .abs_section_1d - _MISC 13 1 1 1 .abs_section_13 - _MODE B 1 1 0 .abs_section_b - _MODRR 247 1 1 0 .abs_section_247 - _MTST0 14 1 1 0 .abs_section_14 - _MTST1 17 1 1 0 .abs_section_17 - _OC7D 43 1 1 0 .abs_section_43 - _OC7M 42 1 1 0 .abs_section_42 - _PACTL 60 1 1 0 .abs_section_60 - _PAFLG 61 1 1 0 .abs_section_61 - _PARTIDH 1A 1 1 0 .abs_section_1a - _PARTIDL 1B 1 1 0 .abs_section_1b - _PEAR A 1 1 0 .abs_section_a - _PERAD 274 1 1 0 .abs_section_274 - _PERJ 26C 1 1 0 .abs_section_26c - _PERM 254 1 1 0 .abs_section_254 - _PERP 25C 1 1 1 .abs_section_25c - _PERS 24C 1 1 0 .abs_section_24c - _PERT 244 1 1 0 .abs_section_244 - _PIEJ 26E 1 1 0 .abs_section_26e - _PIEP 25E 1 1 2 .abs_section_25e - _PIFJ 26F 1 1 0 .abs_section_26f - _PIFP 25F 1 1 2 .abs_section_25f - _PLLCTL 3A 1 1 3 .abs_section_3a - _PORTAD0 8F 1 1 0 .abs_section_8f - _PORTE 8 1 1 0 .abs_section_8 - _PORTK 32 1 1 0 .abs_section_32 - _PPAGE 30 1 1 0 .abs_section_30 - _PPSAD 275 1 1 0 .abs_section_275 - _PPSJ 26D 1 1 0 .abs_section_26d - _PPSM 255 1 1 0 .abs_section_255 - _PPSP 25D 1 1 1 .abs_section_25d - _PPSS 24D 1 1 0 .abs_section_24d - _PPST 245 1 1 0 .abs_section_245 - _PTAD 270 1 1 0 .abs_section_270 - _PTIAD 271 1 1 0 .abs_section_271 - _PTIJ 269 1 1 0 .abs_section_269 - _PTIM 251 1 1 0 .abs_section_251 - _PTIP 259 1 1 0 .abs_section_259 - _PTIS 249 1 1 0 .abs_section_249 - _PTIT 241 1 1 0 .abs_section_241 - _PTJ 268 1 1 0 .abs_section_268 - _PTM 250 1 1 0 .abs_section_250 - _PTP 258 1 1 0 .abs_section_258 - _PTS 248 1 1 0 .abs_section_248 - _PTT 240 1 1 0 .abs_section_240 - _PUCR C 1 1 0 .abs_section_c - _PWMCAE E4 1 1 0 .abs_section_e4 - _PWMCLK E2 1 1 0 .abs_section_e2 - _PWMCTL E5 1 1 1 .abs_section_e5 - _PWME E0 1 1 0 .abs_section_e0 - _PWMPOL E1 1 1 0 .abs_section_e1 - _PWMPRCLK E3 1 1 0 .abs_section_e3 - _PWMSCLA E8 1 1 0 .abs_section_e8 - _PWMSCLB E9 1 1 0 .abs_section_e9 - _PWMSDN FE 1 1 1 .abs_section_fe - _RDRAD 273 1 1 0 .abs_section_273 - _RDRIV D 1 1 0 .abs_section_d - _RDRJ 26B 1 1 0 .abs_section_26b - _RDRM 253 1 1 0 .abs_section_253 - _RDRP 25B 1 1 0 .abs_section_25b - _RDRS 24B 1 1 0 .abs_section_24b - _RDRT 243 1 1 0 .abs_section_243 - _REFDV 35 1 1 1 .abs_section_35 - _RTICTL 3B 1 1 0 .abs_section_3b - _SCICR1 CA 1 1 0 .abs_section_ca - _SCICR2 CB 1 1 0 .abs_section_cb - _SCIDRH CE 1 1 0 .abs_section_ce - _SCIDRL CF 1 1 0 .abs_section_cf - _SCISR1 CC 1 1 0 .abs_section_cc - _SCISR2 CD 1 1 0 .abs_section_cd - _SPIBR DA 1 1 0 .abs_section_da - _SPICR1 D8 1 1 0 .abs_section_d8 - _SPICR2 D9 1 1 0 .abs_section_d9 - _SPIDR DD 1 1 0 .abs_section_dd - _SPISR DB 1 1 0 .abs_section_db - _SYNR 34 1 1 1 .abs_section_34 - _TCTL1 48 1 1 1 .abs_section_48 - _TCTL2 49 1 1 1 .abs_section_49 - _TCTL3 4A 1 1 0 .abs_section_4a - _TCTL4 4B 1 1 0 .abs_section_4b - _TFLG1 4E 1 1 2 .abs_section_4e - _TFLG2 4F 1 1 0 .abs_section_4f - _TIE 4C 1 1 3 .abs_section_4c - _TIOS 40 1 1 1 .abs_section_40 - _TSCR1 46 1 1 3 .abs_section_46 - _TSCR2 4D 1 1 5 .abs_section_4d - _TTOV 47 1 1 1 .abs_section_47 - _WOMM 256 1 1 0 .abs_section_256 - _WOMS 24E 1 1 0 .abs_section_24e - _ATDCTL23 82 2 2 0 .abs_section_82 - _ATDCTL45 84 2 2 0 .abs_section_84 - _ATDDR0 90 2 2 0 .abs_section_90 - _ATDDR1 92 2 2 0 .abs_section_92 - _ATDDR2 94 2 2 0 .abs_section_94 - _ATDDR3 96 2 2 0 .abs_section_96 - _ATDDR4 98 2 2 0 .abs_section_98 - _ATDDR5 9A 2 2 0 .abs_section_9a - _ATDDR6 9C 2 2 0 .abs_section_9c - _ATDDR7 9E 2 2 0 .abs_section_9e - _DDRAB 2 2 2 1 .abs_section_2 - _PACNT 62 2 2 0 .abs_section_62 - _PORTAB 0 2 2 3 .abs_section_0 - _PWMCNT01 EC 2 2 0 .abs_section_ec - _PWMCNT23 EE 2 2 0 .abs_section_ee - _PWMCNT45 F0 2 2 0 .abs_section_f0 - _PWMDTY01 F8 2 2 0 .abs_section_f8 - _PWMDTY23 FA 2 2 0 .abs_section_fa - _PWMDTY45 FC 2 2 0 .abs_section_fc - _PWMPER01 F2 2 2 0 .abs_section_f2 - _PWMPER23 F4 2 2 0 .abs_section_f4 - _PWMPER45 F6 2 2 0 .abs_section_f6 - _SCIBD C8 2 2 0 .abs_section_c8 - _TC0 50 2 2 1 .abs_section_50 - _TC1 52 2 2 0 .abs_section_52 - _TC2 54 2 2 0 .abs_section_54 - _TC3 56 2 2 0 .abs_section_56 - _TC4 58 2 2 0 .abs_section_58 - _TC5 5A 2 2 0 .abs_section_5a - _TC6 5C 2 2 0 .abs_section_5c - _TC7 5E 2 2 1 .abs_section_5e - _TCNT 44 2 2 0 .abs_section_44 -MODULE: -- PE_Timer.C.o -- -- PROCEDURES: - PE_Timer_LngHi1 CE2D 4A 74 1 .text -- VARIABLES: -MODULE: -- Vectors.c.o -- -- PROCEDURES: -- VARIABLES: - _vect FF80 80 128 0 .abs_section_ff80 -MODULE: -- RTOSDemo.C.o -- -- PROCEDURES: - main CE77 8 8 0 .text -- VARIABLES: -MODULE: -- PollQ.c.o -- -- PROCEDURES: - vStartPolledQueueTasks CE7F 42 66 1 .text - vPolledQueueProducer CEC1 4D 77 1 .text - vPolledQueueConsumer CF0E 59 89 1 .text - xArePollingQueuesStillRunning CF67 15 21 1 .text -- VARIABLES: - STRING.QConsNB.2 C0AA 8 8 1 .rodata1 - STRING.QProdNB.3 C0B2 8 8 1 .rodata1 - xPollingConsumerCount F93 1 1 3 .bss - xPollingProducerCount F94 1 1 3 .bss - xPolledQueue.1 F95 2 2 3 .bss -MODULE: -- dynamic.c.o -- -- PROCEDURES: - vStartDynamicPriorityTasks CF7C 7C 124 1 .text - vLimitedIncrementTask CFF8 26 38 1 .text - vContinuousIncrementTask D01E 35 53 1 .text - vCounterControlTask D053 98 152 3 .text - vQueueSendWhenSuspendedTask D0EB 34 52 1 .text - vQueueReceiveWhenSuspendedTask D11F 4F 79 1 .text - xAreDynamicPriorityTasksStillRunning D16E 2B 43 1 .text -- VARIABLES: - STRING.CNT_INC.1 C0BA 8 8 1 .rodata1 - STRING.LIM_INC.2 C0C2 8 8 1 .rodata1 - STRING.C_CTRL.3 C0CA 7 7 1 .rodata1 - STRING.SUSP_TX.4 C0D1 8 8 1 .rodata1 - STRING.SUSP_RX.5 C0D9 8 8 1 .rodata1 - usCheckVariable F97 2 2 3 .bss - xSuspendedQueueSendError F99 1 1 2 .bss - xSuspendedQueueReceiveError F9A 1 1 3 .bss - ulValueToSend.6 F9B 4 4 5 .bss - ulExpectedValue.7 F9F 4 4 6 .bss - usLastTaskCheck.9 FA3 2 2 2 .bss - xContinousIncrementHandle FA5 2 2 5 .bss - xLimitedIncrementHandle FA7 2 2 2 .bss - ulCounter FA9 4 4 10 .bss - ulReceivedValue.8 FAD 4 4 3 .bss - xSuspendedTestQueue FB1 2 2 3 .common -MODULE: -- ButtonInterrupt.C.o -- -- PROCEDURES: - ButtonInterrupt_Enable D3A3 A 10 1 ButtonInterrupt_CODE -- VARIABLES: - -********************************************************************************************* -MODULE STATISTIC - Name Data Code Const ---------------------------------------------------------------------------------------------- - Start12.c.o 0 57 0 - STRING.C.o (ansisi.lib) 0 103 0 - rtshc12.c.o (ansisi.lib) 0 373 0 - tasks.c.o 135 1527 5 - queue.c.o 0 809 0 - list.c.o 0 194 0 - port.c.o 1 122 0 - flash.c.o 1 128 5 - main.c.o 4 398 13 - heap_1.c.o 1798 46 0 - ParTest.c.o 0 19 0 - Cpu.C.o 0 119 0 - Byte1.C.o 8 23 0 - TickTimer.C.o 3 149 0 - IO_Map.C.o 256 0 0 - PE_Timer.C.o 0 74 0 - Vectors.c.o 0 0 128 - RTOSDemo.C.o 0 8 0 - PollQ.c.o 4 253 16 - dynamic.c.o 28 541 39 - ButtonInterrupt.C.o 0 10 0 - other 48 29 19 - -********************************************************************************************* -SECTION USE IN OBJECT-ALLOCATION SECTION ---------------------------------------------------------------------------------------------- -SECTION: ".text" - Init _Startup _memcpy_8bitCount memset strncpy xTaskCreate vTaskDelayUntil - vTaskDelay uxTaskPriorityGet vTaskPrioritySet vTaskSuspend vTaskResume - vTaskStartScheduler vTaskSuspendAll xTaskResumeAll xTaskGetTickCount - vTaskIncrementTick vTaskSwitchContext vTaskPlaceOnEventList - xTaskRemoveFromEventList prvIdleTask prvInitialiseTCBVariables - prvInitialiseTaskLists prvCheckTasksWaitingTermination prvAllocateTCBAndStack - xQueueCreate xQueueSend xQueueSendFromISR xQueueReceive - uxQueueMessagesWaiting prvUnlockQueue prvIsQueueEmpty prvIsQueueFull - vListInitialise vListInitialiseItem vListInsertEnd vListInsert vListRemove - pxPortInitialiseStack prvSetupTimerInterrupt xPortStartScheduler - vStartLEDFlashTasks vLEDFlashTask vMain vErrorChecks - prvCheckOtherTasksAreStillRunning vApplicationIdleHook vButtonTask - pvPortMalloc vPortFree vParTestToggleLED PE_Timer_LngHi1 main - vStartPolledQueueTasks vPolledQueueProducer vPolledQueueConsumer - xArePollingQueuesStillRunning vStartDynamicPriorityTasks - vLimitedIncrementTask vContinuousIncrementTask vCounterControlTask - vQueueSendWhenSuspendedTask vQueueReceiveWhenSuspendedTask - xAreDynamicPriorityTasksStillRunning -SECTION: ".data" - uxCriticalNesting -SECTION: ".bss" - pxCurrentTCB uxCurrentNumberOfTasks xTickCount uxTopUsedPriority - uxTopReadyPriority xSchedulerRunning uxSchedulerSuspended uxMissedTicks - uxTaskNumber.1 pxReadyTasksLists xDelayedTaskList1 xDelayedTaskList2 - pxDelayedTaskList pxOverflowDelayedTaskList xPendingReadyList - xSuspendedTaskList uxFlashTaskNumber xLocalError uxValToSend.3 xButtonQueue - xNextFreeByte xHeap xPollingConsumerCount xPollingProducerCount - xPolledQueue.1 usCheckVariable xSuspendedQueueSendError - xSuspendedQueueReceiveError ulValueToSend.6 ulExpectedValue.7 - usLastTaskCheck.9 xContinousIncrementHandle xLimitedIncrementHandle ulCounter - ulReceivedValue.8 -SECTION: ".init" - _EntryPoint PE_low_level_init -SECTION: ".rodata1" - STRING.IDLE.2 STRING.LEDx.1 STRING.Check.1 STRING.Button.2 STRING.QConsNB.2 - STRING.QProdNB.3 STRING.CNT_INC.1 STRING.LIM_INC.2 STRING.C_CTRL.3 - STRING.SUSP_TX.4 STRING.SUSP_RX.5 -SECTION: "NON_BANKED" - xBankedStartScheduler vPortYield vPortTickInterrupt vButtonPush - Cpu_Interrupt -SECTION: "RUNTIME" - _LCMP _LCMP_P _LNEG _LINC _lDivMod _LDIVU _NEG_P _LDIVS -SECTION: ".common" - xSuspendedTestQueue -SECTION: "TickTimer_CODE" - SetCV SetPV HWEnDi TickTimer_Enable TickTimer_SetFreqHz TickTimer_Init -SECTION: "ButtonInterrupt_CODE" - ButtonInterrupt_Enable -SECTION: "Byte1_CODE" - Byte1_GetMsk Byte1_NegBit -SECTION: "Byte1_DATA" - Byte1_Table -SECTION: "TickTimer_DATA" - EnUser CmpHighVal -SECTION: ".abs_section_3f" - _ARMCOP -SECTION: ".abs_section_8d" - _ATDDIEN -SECTION: ".abs_section_86" - _ATDSTAT0 -SECTION: ".abs_section_8b" - _ATDSTAT1 -SECTION: ".abs_section_ff06" - _BDMCCR -SECTION: ".abs_section_ff07" - _BDMINR -SECTION: ".abs_section_ff01" - _BDMSTS -SECTION: ".abs_section_2b" - _BKP0H -SECTION: ".abs_section_2c" - _BKP0L -SECTION: ".abs_section_2a" - _BKP0X -SECTION: ".abs_section_2e" - _BKP1H -SECTION: ".abs_section_2f" - _BKP1L -SECTION: ".abs_section_2d" - _BKP1X -SECTION: ".abs_section_28" - _BKPCT0 -SECTION: ".abs_section_29" - _BKPCT1 -SECTION: ".abs_section_142" - _CANBTR0 -SECTION: ".abs_section_143" - _CANBTR1 -SECTION: ".abs_section_140" - _CANCTL0 -SECTION: ".abs_section_141" - _CANCTL1 -SECTION: ".abs_section_14b" - _CANIDAC -SECTION: ".abs_section_150" - _CANIDAR0 -SECTION: ".abs_section_151" - _CANIDAR1 -SECTION: ".abs_section_152" - _CANIDAR2 -SECTION: ".abs_section_153" - _CANIDAR3 -SECTION: ".abs_section_158" - _CANIDAR4 -SECTION: ".abs_section_159" - _CANIDAR5 -SECTION: ".abs_section_15a" - _CANIDAR6 -SECTION: ".abs_section_15b" - _CANIDAR7 -SECTION: ".abs_section_154" - _CANIDMR0 -SECTION: ".abs_section_155" - _CANIDMR1 -SECTION: ".abs_section_156" - _CANIDMR2 -SECTION: ".abs_section_157" - _CANIDMR3 -SECTION: ".abs_section_15c" - _CANIDMR4 -SECTION: ".abs_section_15d" - _CANIDMR5 -SECTION: ".abs_section_15e" - _CANIDMR6 -SECTION: ".abs_section_15f" - _CANIDMR7 -SECTION: ".abs_section_144" - _CANRFLG -SECTION: ".abs_section_145" - _CANRIER -SECTION: ".abs_section_16c" - _CANRXDLR -SECTION: ".abs_section_164" - _CANRXDSR0 -SECTION: ".abs_section_165" - _CANRXDSR1 -SECTION: ".abs_section_166" - _CANRXDSR2 -SECTION: ".abs_section_167" - _CANRXDSR3 -SECTION: ".abs_section_168" - _CANRXDSR4 -SECTION: ".abs_section_169" - _CANRXDSR5 -SECTION: ".abs_section_16a" - _CANRXDSR6 -SECTION: ".abs_section_16b" - _CANRXDSR7 -SECTION: ".abs_section_14e" - _CANRXERR -SECTION: ".abs_section_160" - _CANRXIDR0 -SECTION: ".abs_section_161" - _CANRXIDR1 -SECTION: ".abs_section_162" - _CANRXIDR2 -SECTION: ".abs_section_163" - _CANRXIDR3 -SECTION: ".abs_section_149" - _CANTAAK -SECTION: ".abs_section_148" - _CANTARQ -SECTION: ".abs_section_14a" - _CANTBSEL -SECTION: ".abs_section_146" - _CANTFLG -SECTION: ".abs_section_147" - _CANTIER -SECTION: ".abs_section_17c" - _CANTXDLR -SECTION: ".abs_section_174" - _CANTXDSR0 -SECTION: ".abs_section_175" - _CANTXDSR1 -SECTION: ".abs_section_176" - _CANTXDSR2 -SECTION: ".abs_section_177" - _CANTXDSR3 -SECTION: ".abs_section_178" - _CANTXDSR4 -SECTION: ".abs_section_179" - _CANTXDSR5 -SECTION: ".abs_section_17a" - _CANTXDSR6 -SECTION: ".abs_section_17b" - _CANTXDSR7 -SECTION: ".abs_section_14f" - _CANTXERR -SECTION: ".abs_section_170" - _CANTXIDR0 -SECTION: ".abs_section_171" - _CANTXIDR1 -SECTION: ".abs_section_172" - _CANTXIDR2 -SECTION: ".abs_section_173" - _CANTXIDR3 -SECTION: ".abs_section_17f" - _CANTXTBPR -SECTION: ".abs_section_41" - _CFORC -SECTION: ".abs_section_39" - _CLKSEL -SECTION: ".abs_section_3c" - _COPCTL -SECTION: ".abs_section_37" - _CRGFLG -SECTION: ".abs_section_38" - _CRGINT -SECTION: ".abs_section_3e" - _CTCTL -SECTION: ".abs_section_36" - _CTFLG -SECTION: ".abs_section_272" - _DDRAD -SECTION: ".abs_section_9" - _DDRE -SECTION: ".abs_section_26a" - _DDRJ -SECTION: ".abs_section_33" - _DDRK -SECTION: ".abs_section_252" - _DDRM -SECTION: ".abs_section_25a" - _DDRP -SECTION: ".abs_section_24a" - _DDRS -SECTION: ".abs_section_242" - _DDRT -SECTION: ".abs_section_e" - _EBICTL -SECTION: ".abs_section_100" - _FCLKDIV -SECTION: ".abs_section_106" - _FCMD -SECTION: ".abs_section_103" - _FCNFG -SECTION: ".abs_section_104" - _FPROT -SECTION: ".abs_section_101" - _FSEC -SECTION: ".abs_section_105" - _FSTAT -SECTION: ".abs_section_1f" - _HPRIO -SECTION: ".abs_section_12" - _INITEE -SECTION: ".abs_section_11" - _INITRG -SECTION: ".abs_section_10" - _INITRM -SECTION: ".abs_section_1e" - _INTCR -SECTION: ".abs_section_15" - _ITCR -SECTION: ".abs_section_16" - _ITEST -SECTION: ".abs_section_1c" - _MEMSIZ0 -SECTION: ".abs_section_1d" - _MEMSIZ1 -SECTION: ".abs_section_13" - _MISC -SECTION: ".abs_section_b" - _MODE -SECTION: ".abs_section_247" - _MODRR -SECTION: ".abs_section_14" - _MTST0 -SECTION: ".abs_section_17" - _MTST1 -SECTION: ".abs_section_43" - _OC7D -SECTION: ".abs_section_42" - _OC7M -SECTION: ".abs_section_60" - _PACTL -SECTION: ".abs_section_61" - _PAFLG -SECTION: ".abs_section_1a" - _PARTIDH -SECTION: ".abs_section_1b" - _PARTIDL -SECTION: ".abs_section_a" - _PEAR -SECTION: ".abs_section_274" - _PERAD -SECTION: ".abs_section_26c" - _PERJ -SECTION: ".abs_section_254" - _PERM -SECTION: ".abs_section_25c" - _PERP -SECTION: ".abs_section_24c" - _PERS -SECTION: ".abs_section_244" - _PERT -SECTION: ".abs_section_26e" - _PIEJ -SECTION: ".abs_section_25e" - _PIEP -SECTION: ".abs_section_26f" - _PIFJ -SECTION: ".abs_section_25f" - _PIFP -SECTION: ".abs_section_3a" - _PLLCTL -SECTION: ".abs_section_8f" - _PORTAD0 -SECTION: ".abs_section_8" - _PORTE -SECTION: ".abs_section_32" - _PORTK -SECTION: ".abs_section_30" - _PPAGE -SECTION: ".abs_section_275" - _PPSAD -SECTION: ".abs_section_26d" - _PPSJ -SECTION: ".abs_section_255" - _PPSM -SECTION: ".abs_section_25d" - _PPSP -SECTION: ".abs_section_24d" - _PPSS -SECTION: ".abs_section_245" - _PPST -SECTION: ".abs_section_270" - _PTAD -SECTION: ".abs_section_271" - _PTIAD -SECTION: ".abs_section_269" - _PTIJ -SECTION: ".abs_section_251" - _PTIM -SECTION: ".abs_section_259" - _PTIP -SECTION: ".abs_section_249" - _PTIS -SECTION: ".abs_section_241" - _PTIT -SECTION: ".abs_section_268" - _PTJ -SECTION: ".abs_section_250" - _PTM -SECTION: ".abs_section_258" - _PTP -SECTION: ".abs_section_248" - _PTS -SECTION: ".abs_section_240" - _PTT -SECTION: ".abs_section_c" - _PUCR -SECTION: ".abs_section_e4" - _PWMCAE -SECTION: ".abs_section_e2" - _PWMCLK -SECTION: ".abs_section_e5" - _PWMCTL -SECTION: ".abs_section_e0" - _PWME -SECTION: ".abs_section_e1" - _PWMPOL -SECTION: ".abs_section_e3" - _PWMPRCLK -SECTION: ".abs_section_e8" - _PWMSCLA -SECTION: ".abs_section_e9" - _PWMSCLB -SECTION: ".abs_section_fe" - _PWMSDN -SECTION: ".abs_section_273" - _RDRAD -SECTION: ".abs_section_d" - _RDRIV -SECTION: ".abs_section_26b" - _RDRJ -SECTION: ".abs_section_253" - _RDRM -SECTION: ".abs_section_25b" - _RDRP -SECTION: ".abs_section_24b" - _RDRS -SECTION: ".abs_section_243" - _RDRT -SECTION: ".abs_section_35" - _REFDV -SECTION: ".abs_section_3b" - _RTICTL -SECTION: ".abs_section_ca" - _SCICR1 -SECTION: ".abs_section_cb" - _SCICR2 -SECTION: ".abs_section_ce" - _SCIDRH -SECTION: ".abs_section_cf" - _SCIDRL -SECTION: ".abs_section_cc" - _SCISR1 -SECTION: ".abs_section_cd" - _SCISR2 -SECTION: ".abs_section_da" - _SPIBR -SECTION: ".abs_section_d8" - _SPICR1 -SECTION: ".abs_section_d9" - _SPICR2 -SECTION: ".abs_section_dd" - _SPIDR -SECTION: ".abs_section_db" - _SPISR -SECTION: ".abs_section_34" - _SYNR -SECTION: ".abs_section_48" - _TCTL1 -SECTION: ".abs_section_49" - _TCTL2 -SECTION: ".abs_section_4a" - _TCTL3 -SECTION: ".abs_section_4b" - _TCTL4 -SECTION: ".abs_section_4e" - _TFLG1 -SECTION: ".abs_section_4f" - _TFLG2 -SECTION: ".abs_section_4c" - _TIE -SECTION: ".abs_section_40" - _TIOS -SECTION: ".abs_section_46" - _TSCR1 -SECTION: ".abs_section_4d" - _TSCR2 -SECTION: ".abs_section_47" - _TTOV -SECTION: ".abs_section_256" - _WOMM -SECTION: ".abs_section_24e" - _WOMS -SECTION: ".abs_section_82" - _ATDCTL23 -SECTION: ".abs_section_84" - _ATDCTL45 -SECTION: ".abs_section_90" - _ATDDR0 -SECTION: ".abs_section_92" - _ATDDR1 -SECTION: ".abs_section_94" - _ATDDR2 -SECTION: ".abs_section_96" - _ATDDR3 -SECTION: ".abs_section_98" - _ATDDR4 -SECTION: ".abs_section_9a" - _ATDDR5 -SECTION: ".abs_section_9c" - _ATDDR6 -SECTION: ".abs_section_9e" - _ATDDR7 -SECTION: ".abs_section_2" - _DDRAB -SECTION: ".abs_section_62" - _PACNT -SECTION: ".abs_section_0" - _PORTAB -SECTION: ".abs_section_ec" - _PWMCNT01 -SECTION: ".abs_section_ee" - _PWMCNT23 -SECTION: ".abs_section_f0" - _PWMCNT45 -SECTION: ".abs_section_f8" - _PWMDTY01 -SECTION: ".abs_section_fa" - _PWMDTY23 -SECTION: ".abs_section_fc" - _PWMDTY45 -SECTION: ".abs_section_f2" - _PWMPER01 -SECTION: ".abs_section_f4" - _PWMPER23 -SECTION: ".abs_section_f6" - _PWMPER45 -SECTION: ".abs_section_c8" - _SCIBD -SECTION: ".abs_section_50" - _TC0 -SECTION: ".abs_section_52" - _TC1 -SECTION: ".abs_section_54" - _TC2 -SECTION: ".abs_section_56" - _TC3 -SECTION: ".abs_section_58" - _TC4 -SECTION: ".abs_section_5a" - _TC5 -SECTION: ".abs_section_5c" - _TC6 -SECTION: ".abs_section_5e" - _TC7 -SECTION: ".abs_section_44" - _TCNT -SECTION: ".abs_section_ff80" - _vect - -********************************************************************************************* -OBJECT LIST SORTED BY ADDRESS - Name Addr hSize dSize Ref Section RLIB ---------------------------------------------------------------------------------------------- - _PORTAB 0 2 2 3 .abs_section_0 - _DDRAB 2 2 2 1 .abs_section_2 - _PORTE 8 1 1 0 .abs_section_8 - _DDRE 9 1 1 0 .abs_section_9 - _PEAR A 1 1 0 .abs_section_a - _MODE B 1 1 0 .abs_section_b - _PUCR C 1 1 0 .abs_section_c - _RDRIV D 1 1 0 .abs_section_d - _EBICTL E 1 1 0 .abs_section_e - _INITRM 10 1 1 1 .abs_section_10 - _INITRG 11 1 1 0 .abs_section_11 - _INITEE 12 1 1 0 .abs_section_12 - _MISC 13 1 1 1 .abs_section_13 - _MTST0 14 1 1 0 .abs_section_14 - _ITCR 15 1 1 0 .abs_section_15 - _ITEST 16 1 1 0 .abs_section_16 - _MTST1 17 1 1 0 .abs_section_17 - _PARTIDH 1A 1 1 0 .abs_section_1a - _PARTIDL 1B 1 1 0 .abs_section_1b - _MEMSIZ0 1C 1 1 0 .abs_section_1c - _MEMSIZ1 1D 1 1 0 .abs_section_1d - _INTCR 1E 1 1 1 .abs_section_1e - _HPRIO 1F 1 1 0 .abs_section_1f - _BKPCT0 28 1 1 0 .abs_section_28 - _BKPCT1 29 1 1 0 .abs_section_29 - _BKP0X 2A 1 1 0 .abs_section_2a - _BKP0H 2B 1 1 0 .abs_section_2b - _BKP0L 2C 1 1 0 .abs_section_2c - _BKP1X 2D 1 1 0 .abs_section_2d - _BKP1H 2E 1 1 0 .abs_section_2e - _BKP1L 2F 1 1 0 .abs_section_2f - _PPAGE 30 1 1 0 .abs_section_30 - _PORTK 32 1 1 0 .abs_section_32 - _DDRK 33 1 1 0 .abs_section_33 - _SYNR 34 1 1 1 .abs_section_34 - _REFDV 35 1 1 1 .abs_section_35 - _CTFLG 36 1 1 0 .abs_section_36 - _CRGFLG 37 1 1 1 .abs_section_37 - _CRGINT 38 1 1 0 .abs_section_38 - _CLKSEL 39 1 1 3 .abs_section_39 - _PLLCTL 3A 1 1 3 .abs_section_3a - _RTICTL 3B 1 1 0 .abs_section_3b - _COPCTL 3C 1 1 0 .abs_section_3c - _CTCTL 3E 1 1 0 .abs_section_3e - _ARMCOP 3F 1 1 0 .abs_section_3f - _TIOS 40 1 1 1 .abs_section_40 - _CFORC 41 1 1 0 .abs_section_41 - _OC7M 42 1 1 0 .abs_section_42 - _OC7D 43 1 1 0 .abs_section_43 - _TCNT 44 2 2 0 .abs_section_44 - _TSCR1 46 1 1 3 .abs_section_46 - _TTOV 47 1 1 1 .abs_section_47 - _TCTL1 48 1 1 1 .abs_section_48 - _TCTL2 49 1 1 1 .abs_section_49 - _TCTL3 4A 1 1 0 .abs_section_4a - _TCTL4 4B 1 1 0 .abs_section_4b - _TIE 4C 1 1 3 .abs_section_4c - _TSCR2 4D 1 1 5 .abs_section_4d - _TFLG1 4E 1 1 2 .abs_section_4e - _TFLG2 4F 1 1 0 .abs_section_4f - _TC0 50 2 2 1 .abs_section_50 - _TC1 52 2 2 0 .abs_section_52 - _TC2 54 2 2 0 .abs_section_54 - _TC3 56 2 2 0 .abs_section_56 - _TC4 58 2 2 0 .abs_section_58 - _TC5 5A 2 2 0 .abs_section_5a - _TC6 5C 2 2 0 .abs_section_5c - _TC7 5E 2 2 1 .abs_section_5e - _PACTL 60 1 1 0 .abs_section_60 - _PAFLG 61 1 1 0 .abs_section_61 - _PACNT 62 2 2 0 .abs_section_62 - _ATDCTL23 82 2 2 0 .abs_section_82 - _ATDCTL45 84 2 2 0 .abs_section_84 - _ATDSTAT0 86 1 1 0 .abs_section_86 - _ATDSTAT1 8B 1 1 0 .abs_section_8b - _ATDDIEN 8D 1 1 0 .abs_section_8d - _PORTAD0 8F 1 1 0 .abs_section_8f - _ATDDR0 90 2 2 0 .abs_section_90 - _ATDDR1 92 2 2 0 .abs_section_92 - _ATDDR2 94 2 2 0 .abs_section_94 - _ATDDR3 96 2 2 0 .abs_section_96 - _ATDDR4 98 2 2 0 .abs_section_98 - _ATDDR5 9A 2 2 0 .abs_section_9a - _ATDDR6 9C 2 2 0 .abs_section_9c - _ATDDR7 9E 2 2 0 .abs_section_9e - _SCIBD C8 2 2 0 .abs_section_c8 - _SCICR1 CA 1 1 0 .abs_section_ca - _SCICR2 CB 1 1 0 .abs_section_cb - _SCISR1 CC 1 1 0 .abs_section_cc - _SCISR2 CD 1 1 0 .abs_section_cd - _SCIDRH CE 1 1 0 .abs_section_ce - _SCIDRL CF 1 1 0 .abs_section_cf - _SPICR1 D8 1 1 0 .abs_section_d8 - _SPICR2 D9 1 1 0 .abs_section_d9 - _SPIBR DA 1 1 0 .abs_section_da - _SPISR DB 1 1 0 .abs_section_db - _SPIDR DD 1 1 0 .abs_section_dd - _PWME E0 1 1 0 .abs_section_e0 - _PWMPOL E1 1 1 0 .abs_section_e1 - _PWMCLK E2 1 1 0 .abs_section_e2 - _PWMPRCLK E3 1 1 0 .abs_section_e3 - _PWMCAE E4 1 1 0 .abs_section_e4 - _PWMCTL E5 1 1 1 .abs_section_e5 - _PWMSCLA E8 1 1 0 .abs_section_e8 - _PWMSCLB E9 1 1 0 .abs_section_e9 - _PWMCNT01 EC 2 2 0 .abs_section_ec - _PWMCNT23 EE 2 2 0 .abs_section_ee - _PWMCNT45 F0 2 2 0 .abs_section_f0 - _PWMPER01 F2 2 2 0 .abs_section_f2 - _PWMPER23 F4 2 2 0 .abs_section_f4 - _PWMPER45 F6 2 2 0 .abs_section_f6 - _PWMDTY01 F8 2 2 0 .abs_section_f8 - _PWMDTY23 FA 2 2 0 .abs_section_fa - _PWMDTY45 FC 2 2 0 .abs_section_fc - _PWMSDN FE 1 1 1 .abs_section_fe - _FCLKDIV 100 1 1 0 .abs_section_100 - _FSEC 101 1 1 0 .abs_section_101 - _FCNFG 103 1 1 0 .abs_section_103 - _FPROT 104 1 1 0 .abs_section_104 - _FSTAT 105 1 1 0 .abs_section_105 - _FCMD 106 1 1 0 .abs_section_106 - _CANCTL0 140 1 1 0 .abs_section_140 - _CANCTL1 141 1 1 0 .abs_section_141 - _CANBTR0 142 1 1 0 .abs_section_142 - _CANBTR1 143 1 1 0 .abs_section_143 - _CANRFLG 144 1 1 0 .abs_section_144 - _CANRIER 145 1 1 0 .abs_section_145 - _CANTFLG 146 1 1 0 .abs_section_146 - _CANTIER 147 1 1 0 .abs_section_147 - _CANTARQ 148 1 1 0 .abs_section_148 - _CANTAAK 149 1 1 0 .abs_section_149 - _CANTBSEL 14A 1 1 0 .abs_section_14a - _CANIDAC 14B 1 1 0 .abs_section_14b - _CANRXERR 14E 1 1 0 .abs_section_14e - _CANTXERR 14F 1 1 0 .abs_section_14f - _CANIDAR0 150 1 1 0 .abs_section_150 - _CANIDAR1 151 1 1 0 .abs_section_151 - _CANIDAR2 152 1 1 0 .abs_section_152 - _CANIDAR3 153 1 1 0 .abs_section_153 - _CANIDMR0 154 1 1 0 .abs_section_154 - _CANIDMR1 155 1 1 0 .abs_section_155 - _CANIDMR2 156 1 1 0 .abs_section_156 - _CANIDMR3 157 1 1 0 .abs_section_157 - _CANIDAR4 158 1 1 0 .abs_section_158 - _CANIDAR5 159 1 1 0 .abs_section_159 - _CANIDAR6 15A 1 1 0 .abs_section_15a - _CANIDAR7 15B 1 1 0 .abs_section_15b - _CANIDMR4 15C 1 1 0 .abs_section_15c - _CANIDMR5 15D 1 1 0 .abs_section_15d - _CANIDMR6 15E 1 1 0 .abs_section_15e - _CANIDMR7 15F 1 1 0 .abs_section_15f - _CANRXIDR0 160 1 1 0 .abs_section_160 - _CANRXIDR1 161 1 1 0 .abs_section_161 - _CANRXIDR2 162 1 1 0 .abs_section_162 - _CANRXIDR3 163 1 1 0 .abs_section_163 - _CANRXDSR0 164 1 1 0 .abs_section_164 - _CANRXDSR1 165 1 1 0 .abs_section_165 - _CANRXDSR2 166 1 1 0 .abs_section_166 - _CANRXDSR3 167 1 1 0 .abs_section_167 - _CANRXDSR4 168 1 1 0 .abs_section_168 - _CANRXDSR5 169 1 1 0 .abs_section_169 - _CANRXDSR6 16A 1 1 0 .abs_section_16a - _CANRXDSR7 16B 1 1 0 .abs_section_16b - _CANRXDLR 16C 1 1 0 .abs_section_16c - _CANTXIDR0 170 1 1 0 .abs_section_170 - _CANTXIDR1 171 1 1 0 .abs_section_171 - _CANTXIDR2 172 1 1 0 .abs_section_172 - _CANTXIDR3 173 1 1 0 .abs_section_173 - _CANTXDSR0 174 1 1 0 .abs_section_174 - _CANTXDSR1 175 1 1 0 .abs_section_175 - _CANTXDSR2 176 1 1 0 .abs_section_176 - _CANTXDSR3 177 1 1 0 .abs_section_177 - _CANTXDSR4 178 1 1 0 .abs_section_178 - _CANTXDSR5 179 1 1 0 .abs_section_179 - _CANTXDSR6 17A 1 1 0 .abs_section_17a - _CANTXDSR7 17B 1 1 0 .abs_section_17b - _CANTXDLR 17C 1 1 0 .abs_section_17c - _CANTXTBPR 17F 1 1 0 .abs_section_17f - _PTT 240 1 1 0 .abs_section_240 - _PTIT 241 1 1 0 .abs_section_241 - _DDRT 242 1 1 0 .abs_section_242 - _RDRT 243 1 1 0 .abs_section_243 - _PERT 244 1 1 0 .abs_section_244 - _PPST 245 1 1 0 .abs_section_245 - _MODRR 247 1 1 0 .abs_section_247 - _PTS 248 1 1 0 .abs_section_248 - _PTIS 249 1 1 0 .abs_section_249 - _DDRS 24A 1 1 0 .abs_section_24a - _RDRS 24B 1 1 0 .abs_section_24b - _PERS 24C 1 1 0 .abs_section_24c - _PPSS 24D 1 1 0 .abs_section_24d - _WOMS 24E 1 1 0 .abs_section_24e - _PTM 250 1 1 0 .abs_section_250 - _PTIM 251 1 1 0 .abs_section_251 - _DDRM 252 1 1 0 .abs_section_252 - _RDRM 253 1 1 0 .abs_section_253 - _PERM 254 1 1 0 .abs_section_254 - _PPSM 255 1 1 0 .abs_section_255 - _WOMM 256 1 1 0 .abs_section_256 - _PTP 258 1 1 0 .abs_section_258 - _PTIP 259 1 1 0 .abs_section_259 - _DDRP 25A 1 1 1 .abs_section_25a - _RDRP 25B 1 1 0 .abs_section_25b - _PERP 25C 1 1 1 .abs_section_25c - _PPSP 25D 1 1 1 .abs_section_25d - _PIEP 25E 1 1 2 .abs_section_25e - _PIFP 25F 1 1 2 .abs_section_25f - _PTJ 268 1 1 0 .abs_section_268 - _PTIJ 269 1 1 0 .abs_section_269 - _DDRJ 26A 1 1 0 .abs_section_26a - _RDRJ 26B 1 1 0 .abs_section_26b - _PERJ 26C 1 1 0 .abs_section_26c - _PPSJ 26D 1 1 0 .abs_section_26d - _PIEJ 26E 1 1 0 .abs_section_26e - _PIFJ 26F 1 1 0 .abs_section_26f - _PTAD 270 1 1 0 .abs_section_270 - _PTIAD 271 1 1 0 .abs_section_271 - _DDRAD 272 1 1 0 .abs_section_272 - _RDRAD 273 1 1 0 .abs_section_273 - _PERAD 274 1 1 0 .abs_section_274 - _PPSAD 275 1 1 0 .abs_section_275 - uxCriticalNesting 800 1 1 91 .data - pxCurrentTCB 801 2 2 29 .bss - uxCurrentNumberOfTasks 803 1 1 3 .bss - xTickCount 804 2 2 14 .bss - uxTopUsedPriority 806 1 1 2 .bss - uxTopReadyPriority 807 1 1 15 .bss - xSchedulerRunning 808 1 1 3 .bss - uxSchedulerSuspended 809 1 1 6 .bss - uxMissedTicks 80A 1 1 4 .bss - uxTaskNumber.1 80B 1 1 2 .bss - pxReadyTasksLists 80C 3C 60 11 .bss - xDelayedTaskList1 848 F 15 2 .bss - xDelayedTaskList2 857 F 15 2 .bss - pxDelayedTaskList 866 2 2 8 .bss - pxOverflowDelayedTaskList 868 2 2 6 .bss - xPendingReadyList 86A F 15 4 .bss - xSuspendedTaskList 879 F 15 2 .bss - uxFlashTaskNumber 888 1 1 2 .bss - xLocalError 889 1 1 3 .bss - uxValToSend.3 88A 1 1 2 .bss - xButtonQueue 88B 2 2 3 .bss - xNextFreeByte 88D 2 2 4 .bss - xHeap 88F 704 1796 1 .bss - xPollingConsumerCount F93 1 1 3 .bss - xPollingProducerCount F94 1 1 3 .bss - xPolledQueue.1 F95 2 2 3 .bss - usCheckVariable F97 2 2 3 .bss - xSuspendedQueueSendError F99 1 1 2 .bss - xSuspendedQueueReceiveError F9A 1 1 3 .bss - ulValueToSend.6 F9B 4 4 5 .bss - ulExpectedValue.7 F9F 4 4 6 .bss - usLastTaskCheck.9 FA3 2 2 2 .bss - xContinousIncrementHandle FA5 2 2 5 .bss - xLimitedIncrementHandle FA7 2 2 2 .bss - ulCounter FA9 4 4 10 .bss - ulReceivedValue.8 FAD 4 4 3 .bss - xSuspendedTestQueue FB1 2 2 3 .common - Byte1_Table FB3 8 8 1 Byte1_DATA - EnUser FBB 1 1 4 TickTimer_DATA - CmpHighVal FBC 2 2 2 TickTimer_DATA - _EntryPoint C000 2E 46 1 .init - PE_low_level_init C02E 48 72 1 .init - STRING.IDLE.2 C093 5 5 1 .rodata1 - STRING.LEDx.1 C098 5 5 1 .rodata1 - STRING.Check.1 C09D 6 6 1 .rodata1 - STRING.Button.2 C0A3 7 7 1 .rodata1 - STRING.QConsNB.2 C0AA 8 8 1 .rodata1 - STRING.QProdNB.3 C0B2 8 8 1 .rodata1 - STRING.CNT_INC.1 C0BA 8 8 1 .rodata1 - STRING.LIM_INC.2 C0C2 8 8 1 .rodata1 - STRING.C_CTRL.3 C0CA 7 7 1 .rodata1 - STRING.SUSP_TX.4 C0D1 8 8 1 .rodata1 - STRING.SUSP_RX.5 C0D9 8 8 1 .rodata1 - xBankedStartScheduler C0E1 F 15 1 NON_BANKED - vPortYield C0F0 16 22 1 NON_BANKED - vPortTickInterrupt C106 1D 29 1 NON_BANKED - vButtonPush C123 2F 47 1 NON_BANKED - Cpu_Interrupt C152 1 1 60 NON_BANKED - Init C153 29 41 1 .text - _Startup C17C 10 16 1 .text - _memcpy_8bitCount C18C 1C 28 3 .text - memset C1A8 1E 30 1 .text - strncpy C1C6 2D 45 1 .text - xTaskCreate C1F3 CE 206 11 .text - vTaskDelayUntil C2C1 74 116 3 .text - vTaskDelay C335 46 70 4 .text - uxTaskPriorityGet C37B 26 38 1 .text - vTaskPrioritySet C3A1 69 105 2 .text - vTaskSuspend C40A 44 68 3 .text - vTaskResume C44E 59 89 3 .text - vTaskStartScheduler C4A7 30 48 1 .text - vTaskSuspendAll C4D7 13 19 11 .text - xTaskResumeAll C4EA 9F 159 13 .text - xTaskGetTickCount C589 17 23 2 .text - vTaskIncrementTick C5A0 81 129 2 .text - vTaskSwitchContext C621 5B 91 3 .text - vTaskPlaceOnEventList C67C 3E 62 2 .text - xTaskRemoveFromEventList C6BA 65 101 3 .text - prvIdleTask C71F 10 16 1 .text - prvInitialiseTCBVariables C72F 4A 74 1 .text - prvInitialiseTaskLists C779 37 55 1 .text - prvCheckTasksWaitingTermination C7B0 1 1 1 .text - prvAllocateTCBAndStack C7B1 39 57 1 .text - xQueueCreate C7EA 76 118 3 .text - xQueueSend C860 C9 201 3 .text - xQueueSendFromISR C929 58 88 1 .text - xQueueReceive C981 C3 195 4 .text - uxQueueMessagesWaiting CA44 1B 27 1 .text - prvUnlockQueue CA5F 6F 111 4 .text - prvIsQueueEmpty CACE 21 33 1 .text - prvIsQueueFull CAEF 24 36 1 .text - vListInitialise CB13 1F 31 7 .text - vListInitialiseItem CB32 7 7 3 .text - vListInsertEnd CB39 25 37 7 .text - vListInsert CB5E 54 84 4 .text - vListRemove CBB2 23 35 13 .text - pxPortInitialiseStack CBD5 2B 43 1 .text - prvSetupTimerInterrupt CC00 9 9 1 .text - xPortStartScheduler CC09 4 4 1 .text - vStartLEDFlashTasks CC0D 2E 46 1 .text - vLEDFlashTask CC3B 52 82 1 .text - vMain CC8D 42 66 1 .text - vErrorChecks CCCF 35 53 1 .text - prvCheckOtherTasksAreStillRunning CD04 26 38 1 .text - vApplicationIdleHook CD2A 73 115 1 .text - vButtonTask CD9D 4F 79 1 .text - pvPortMalloc CDEC 2D 45 4 .text - vPortFree CE19 1 1 2 .text - vParTestToggleLED CE1A 13 19 4 .text - PE_Timer_LngHi1 CE2D 4A 74 1 .text - main CE77 8 8 0 .text - vStartPolledQueueTasks CE7F 42 66 1 .text - vPolledQueueProducer CEC1 4D 77 1 .text - vPolledQueueConsumer CF0E 59 89 1 .text - xArePollingQueuesStillRunning CF67 15 21 1 .text - vStartDynamicPriorityTasks CF7C 7C 124 1 .text - vLimitedIncrementTask CFF8 26 38 1 .text - vContinuousIncrementTask D01E 35 53 1 .text - vCounterControlTask D053 98 152 3 .text - vQueueSendWhenSuspendedTask D0EB 34 52 1 .text - vQueueReceiveWhenSuspendedTask D11F 4F 79 1 .text - xAreDynamicPriorityTasksStillRunning D16E 2B 43 1 .text - _LCMP D199 19 25 2 RUNTIME - _LCMP_P D1B2 15 21 2 RUNTIME - _LNEG D1C7 D 13 1 RUNTIME - _LINC D1D4 5 5 4 RUNTIME - _lDivMod D1D9 E3 227 3 RUNTIME - _LDIVU D2BC E 14 1 RUNTIME - _NEG_P D2CA F 15 4 RUNTIME - _LDIVS D2D9 35 53 1 RUNTIME - SetCV D30E B 11 2 TickTimer_CODE - SetPV D319 9 9 1 TickTimer_CODE - HWEnDi D322 11 17 2 TickTimer_CODE - TickTimer_Enable D333 E 14 1 TickTimer_CODE - TickTimer_SetFreqHz D341 4E 78 1 TickTimer_CODE - TickTimer_Init D38F 14 20 1 TickTimer_CODE - ButtonInterrupt_Enable D3A3 A 10 1 ButtonInterrupt_CODE - Byte1_GetMsk D3AD D 13 1 Byte1_CODE - Byte1_NegBit D3BA A 10 1 Byte1_CODE - _BDMSTS FF01 1 1 0 .abs_section_ff01 - _BDMCCR FF06 1 1 0 .abs_section_ff06 - _BDMINR FF07 1 1 0 .abs_section_ff07 - _vect FF80 80 128 0 .abs_section_ff80 - -********************************************************************************************* -UNUSED-OBJECTS SECTION ---------------------------------------------------------------------------------------------- -NOT USED PROCEDURES -STRING.C.o (ansisi.lib): - strerror memchr memcmp memcpy2 memcpy memmove _memset_clear_8bitCount strlen - strset strcat strncat strcpy strcmp strncmp strchr strrchr strspn strcspn - strpbrk strstr strtok strcoll strxfrm -rtshc12.c.o (ansisi.lib): - _BSHL _BSHRS _BSHRU _BDIVMODU _BDIVMODS _ISHL _ISHRU _ISHRS _LSHL _LSHRU - _LSHRS _LADD _LSUB _LAND _LOR _LXOR _LCMP_PP _LABS _LCOM _LDEC _LMUL _LMODU - _LMODS _ILSEXT _LTEST _COPY _CASE_DIRECT _CASE_DIRECT_BYTE _CASE_CHECKED - _CASE_CHECKED_BYTE _CASE_SEARCH _CASE_SEARCH_BYTE _CASE_SEARCH_8 - _CASE_SEARCH_8_BYTE _FCALL _FPCMP -tasks.c.o: - vTaskEndScheduler uxTaskGetNumberOfTasks -queue.c.o: - xQueueReceiveFromISR vQueueDelete -port.c.o: - vPortEndScheduler -heap_1.c.o: - vPortInitialiseBlocks -ParTest.c.o: - vParTestSetLED -Byte1.C.o: - Byte1_PutBit -TickTimer.C.o: - TickTimer_Interrupt -ButtonInterrupt.C.o: - ButtonInterrupt_Interrupt -NOT USED VARIABLES -STRING.C.o (ansisi.lib): - STRING..1 next.2 -rtshc12.c.o (ansisi.lib): - _PowOfTwo_8 _PowOfTwo_16 _PowOfTwo_32 -Cpu.C.o: - CpuMode CCR_reg - -********************************************************************************************* -COPYDOWN SECTION ---------------------------------------------------------------------------------------------- -------- ROM-ADDRESS: 0xD3C4 ---- SIZE 4 --- -Filling bytes inserted - 00010800 -------- ROM-ADDRESS: 0xD3C8 ---- RAM-ADDRESS: 0x800 ---- SIZE 1 --- -Name of initialized Object : uxCriticalNesting - FF -------- ROM-ADDRESS: 0xD3C9 ---- SIZE 4 --- -Filling bytes inserted - 00080FB3 -------- ROM-ADDRESS: 0xD3CD ---- RAM-ADDRESS: 0xFB3 ---- SIZE 8 --- -Name of initialized Object : Byte1_Table - 0102040810 204080 -------- ROM-ADDRESS: 0xD3D5 ---- SIZE 2 --- -Filling bytes inserted - 0000 - -********************************************************************************************* -OBJECT-DEPENDENCIES SECTION ---------------------------------------------------------------------------------------------- -_EntryPoint USES _INITRM _MISC _CLKSEL _PLLCTL _SYNR _REFDV - _CRGFLG _Startup -PE_low_level_init USES _TSCR1 _TCTL2 _TCTL1 _TIE _TTOV _TSCR2 _TIOS - _PPSP _PERP _DDRP _PWMCTL _PWMSDN _PORTAB _DDRAB - TickTimer_Init _PIEP _INTCR -xBankedStartScheduler USES prvSetupTimerInterrupt pxCurrentTCB - uxCriticalNesting -vPortYield USES uxCriticalNesting pxCurrentTCB - vTaskSwitchContext -vPortTickInterrupt USES uxCriticalNesting pxCurrentTCB - vTaskIncrementTick vTaskSwitchContext _TFLG1 -vButtonPush USES uxValToSend.3 _PIFP xButtonQueue - xQueueSendFromISR uxCriticalNesting pxCurrentTCB - vTaskSwitchContext -Init USES _startupData -_Startup USES _startupData Init -xTaskCreate USES prvAllocateTCBAndStack - prvInitialiseTCBVariables pxPortInitialiseStack uxCriticalNesting - uxCurrentNumberOfTasks pxCurrentTCB prvInitialiseTaskLists - xSchedulerRunning uxTopUsedPriority uxTaskNumber.1 - uxTopReadyPriority pxReadyTasksLists vListInsertEnd -vTaskDelayUntil USES vTaskSuspendAll xTickCount pxCurrentTCB - vListRemove pxOverflowDelayedTaskList pxDelayedTaskList - vListInsert xTaskResumeAll -vTaskDelay USES vTaskSuspendAll xTickCount pxCurrentTCB - vListRemove pxOverflowDelayedTaskList pxDelayedTaskList - vListInsert xTaskResumeAll -uxTaskPriorityGet USES uxCriticalNesting pxCurrentTCB -vTaskPrioritySet USES uxCriticalNesting pxCurrentTCB - pxReadyTasksLists vListRemove uxTopReadyPriority vListInsertEnd -vTaskSuspend USES uxCriticalNesting pxCurrentTCB vListRemove - xSuspendedTaskList vListInsertEnd -vTaskResume USES uxCriticalNesting pxCurrentTCB vListRemove - uxTopReadyPriority pxReadyTasksLists vListInsertEnd -vTaskStartScheduler USES pxCurrentTCB prvIdleTask STRING.IDLE.2 - xTaskCreate xSchedulerRunning xTickCount - xPortStartScheduler -vTaskSuspendAll USES uxCriticalNesting uxSchedulerSuspended -xTaskResumeAll USES uxCriticalNesting uxSchedulerSuspended - uxCurrentNumberOfTasks vListRemove uxTopReadyPriority - pxReadyTasksLists vListInsertEnd pxCurrentTCB xPendingReadyList - uxMissedTicks vTaskIncrementTick -xTaskGetTickCount USES uxCriticalNesting xTickCount -vTaskIncrementTick USES uxSchedulerSuspended xTickCount - pxDelayedTaskList pxOverflowDelayedTaskList vListRemove - uxTopReadyPriority pxReadyTasksLists vListInsertEnd uxMissedTicks -vTaskSwitchContext USES uxSchedulerSuspended uxTopReadyPriority - pxCurrentTCB pxReadyTasksLists -vTaskPlaceOnEventList USES pxCurrentTCB vListInsert xTickCount vListRemove - pxOverflowDelayedTaskList pxDelayedTaskList -xTaskRemoveFromEventList USES vListRemove uxSchedulerSuspended - uxTopReadyPriority pxReadyTasksLists xPendingReadyList - vListInsertEnd pxCurrentTCB -prvIdleTask USES prvCheckTasksWaitingTermination - pxReadyTasksLists vApplicationIdleHook -prvInitialiseTCBVariables USES strncpy vListInitialiseItem -prvInitialiseTaskLists USES pxReadyTasksLists vListInitialise - xDelayedTaskList1 xDelayedTaskList2 xPendingReadyList - xSuspendedTaskList pxDelayedTaskList pxOverflowDelayedTaskList -prvAllocateTCBAndStack USES pvPortMalloc vPortFree memset -xQueueCreate USES pvPortMalloc vListInitialise vPortFree -xQueueSend USES vTaskSuspendAll uxCriticalNesting xQueueSend - prvIsQueueFull vTaskPlaceOnEventList prvUnlockQueue - xTaskResumeAll _memcpy_8bitCount -xQueueSendFromISR USES _memcpy_8bitCount xTaskRemoveFromEventList -xQueueReceive USES vTaskSuspendAll uxCriticalNesting xQueueReceive - prvIsQueueEmpty vTaskPlaceOnEventList prvUnlockQueue - xTaskResumeAll _memcpy_8bitCount -uxQueueMessagesWaiting USES uxCriticalNesting -prvUnlockQueue USES uxCriticalNesting xTaskRemoveFromEventList -prvIsQueueEmpty USES uxCriticalNesting -prvIsQueueFull USES uxCriticalNesting -vListInitialise USES vListInitialiseItem -prvSetupTimerInterrupt USES TickTimer_SetFreqHz TickTimer_Enable -xPortStartScheduler USES xBankedStartScheduler -vStartLEDFlashTasks USES vLEDFlashTask STRING.LEDx.1 xTaskCreate -vLEDFlashTask USES uxCriticalNesting uxFlashTaskNumber - xTaskGetTickCount vTaskDelayUntil vParTestToggleLED -vMain USES vStartLEDFlashTasks vStartPolledQueueTasks - vStartDynamicPriorityTasks vErrorChecks STRING.Check.1 xTaskCreate - vButtonTask STRING.Button.2 vTaskStartScheduler -vErrorChecks USES xTaskGetTickCount vTaskDelayUntil - prvCheckOtherTasksAreStillRunning _LCMP vParTestToggleLED -prvCheckOtherTasksAreStillRunning USES xArePollingQueuesStillRunning - xAreDynamicPriorityTasksStillRunning xLocalError -vApplicationIdleHook USES _LNEG _LDIVS _LCMP_P uxCriticalNesting - xLocalError -vButtonTask USES xQueueCreate xButtonQueue - ButtonInterrupt_Enable xQueueReceive uxCriticalNesting xLocalError - vParTestToggleLED -pvPortMalloc USES vTaskSuspendAll xNextFreeByte xHeap - xTaskResumeAll -vParTestToggleLED USES uxCriticalNesting Byte1_NegBit -PE_Timer_LngHi1 USES _LCMP -main USES PE_low_level_init vMain -vStartPolledQueueTasks USES xQueueCreate xPolledQueue.1 - vPolledQueueConsumer STRING.QConsNB.2 xTaskCreate - vPolledQueueProducer STRING.QProdNB.3 -vPolledQueueProducer USES xQueueSend uxCriticalNesting - xPollingProducerCount vTaskDelay -vPolledQueueConsumer USES xQueueReceive uxCriticalNesting - xPollingConsumerCount uxQueueMessagesWaiting vTaskDelay -xArePollingQueuesStillRunning USES xPollingConsumerCount xPollingProducerCount -vStartDynamicPriorityTasks USES xQueueCreate xSuspendedTestQueue - vContinuousIncrementTask STRING.CNT_INC.1 ulCounter - xContinousIncrementHandle xTaskCreate vLimitedIncrementTask - STRING.LIM_INC.2 xLimitedIncrementHandle vCounterControlTask - STRING.C_CTRL.3 vQueueSendWhenSuspendedTask STRING.SUSP_TX.4 - vQueueReceiveWhenSuspendedTask STRING.SUSP_RX.5 -vLimitedIncrementTask USES _LINC _LCMP_P vTaskSuspend -vContinuousIncrementTask USES uxTaskPriorityGet vTaskPrioritySet _LINC -vCounterControlTask USES vCounterControlTask xContinousIncrementHandle - vTaskSuspend ulCounter vTaskResume vTaskDelay - vTaskSuspendAll xTaskResumeAll xLimitedIncrementHandle - uxCriticalNesting usCheckVariable -vQueueSendWhenSuspendedTask USES vTaskSuspendAll xSuspendedTestQueue - ulValueToSend.6 xQueueSend xSuspendedQueueSendError - xTaskResumeAll vTaskDelay _LINC -vQueueReceiveWhenSuspendedTask USES vTaskSuspendAll xSuspendedTestQueue - ulReceivedValue.8 xQueueReceive xTaskResumeAll - xSuspendedQueueReceiveError ulExpectedValue.7 _LINC -xAreDynamicPriorityTasksStillRunning USES usCheckVariable usLastTaskCheck.9 - xSuspendedQueueSendError xSuspendedQueueReceiveError -_LDIVU USES _lDivMod -_LDIVS USES _NEG_P _lDivMod -SetCV USES _TC0 _TC7 -SetPV USES _TSCR2 -HWEnDi USES EnUser _TFLG1 _TIE -TickTimer_Enable USES EnUser HWEnDi -TickTimer_SetFreqHz USES _LDIVU PE_Timer_LngHi1 CmpHighVal SetCV -TickTimer_Init USES CmpHighVal EnUser SetCV SetPV HWEnDi -ButtonInterrupt_Enable USES _PIFP _PIEP -Byte1_GetMsk USES Byte1_Table -Byte1_NegBit USES Byte1_GetMsk _PORTAB -_vect USES Cpu_Interrupt vButtonPush vPortTickInterrupt - vPortYield _EntryPoint - -********************************************************************************************* -DEPENDENCY TREE -********************************************************************************************* - main and _Startup Group - | - +- main - | | - | +- PE_low_level_init - | | | - | | +- TickTimer_Init - | | | - | | +- SetCV - | | | - | | +- SetPV - | | | - | | +- HWEnDi - | | - | +- vMain - | | - | +- vStartLEDFlashTasks - | | | - | | +- vLEDFlashTask - | | | | - | | | +- xTaskGetTickCount - | | | | - | | | +- vTaskDelayUntil - | | | | | - | | | | +- vTaskSuspendAll - | | | | | - | | | | +- vListRemove - | | | | | - | | | | +- vListInsert - | | | | | - | | | | +- xTaskResumeAll - | | | | | - | | | | +- vListRemove (see above) - | | | | | - | | | | +- vListInsertEnd - | | | | | - | | | | +- vTaskIncrementTick - | | | | | - | | | | +- vListRemove (see above) - | | | | | - | | | | +- vListInsertEnd (see above) - | | | | - | | | +- vParTestToggleLED - | | | | - | | | +- Byte1_NegBit - | | | | - | | | +- Byte1_GetMsk - | | | - | | +- xTaskCreate - | | | - | | +- prvAllocateTCBAndStack - | | | | - | | | +- pvPortMalloc - | | | | | - | | | | +- vTaskSuspendAll (see above) - | | | | | - | | | | +- xTaskResumeAll (see above) - | | | | - | | | +- vPortFree - | | | | - | | | +- memset - | | | - | | +- prvInitialiseTCBVariables - | | | | - | | | +- strncpy - | | | | - | | | +- vListInitialiseItem - | | | - | | +- pxPortInitialiseStack - | | | - | | +- prvInitialiseTaskLists - | | | | - | | | +- vListInitialise - | | | | - | | | +- vListInitialiseItem (see above) - | | | - | | +- vListInsertEnd (see above) - | | - | +- vStartPolledQueueTasks - | | | - | | +- xQueueCreate - | | | | - | | | +- pvPortMalloc (see above) - | | | | - | | | +- vListInitialise (see above) - | | | | - | | | +- vPortFree (see above) - | | | - | | +- vPolledQueueConsumer - | | | | - | | | +- xQueueReceive - | | | | | - | | | | +- vTaskSuspendAll (see above) - | | | | | - | | | | +- prvIsQueueEmpty - | | | | | - | | | | +- vTaskPlaceOnEventList - | | | | | | - | | | | | +- vListInsert (see above) - | | | | | | - | | | | | +- vListRemove (see above) - | | | | | - | | | | +- prvUnlockQueue - | | | | | | - | | | | | +- xTaskRemoveFromEventList - | | | | | | - | | | | | +- vListRemove (see above) - | | | | | | - | | | | | +- vListInsertEnd (see above) - | | | | | - | | | | +- xTaskResumeAll (see above) - | | | | | - | | | | +- _memcpy_8bitCount - | | | | - | | | +- uxQueueMessagesWaiting - | | | | - | | | +- vTaskDelay - | | | | - | | | +- vTaskSuspendAll (see above) - | | | | - | | | +- vListRemove (see above) - | | | | - | | | +- vListInsert (see above) - | | | | - | | | +- xTaskResumeAll (see above) - | | | - | | +- xTaskCreate (see above) - | | | - | | +- vPolledQueueProducer - | | | - | | +- xQueueSend - | | | | - | | | +- vTaskSuspendAll (see above) - | | | | - | | | +- prvIsQueueFull - | | | | - | | | +- vTaskPlaceOnEventList (see above) - | | | | - | | | +- prvUnlockQueue (see above) - | | | | - | | | +- xTaskResumeAll (see above) - | | | | - | | | +- _memcpy_8bitCount (see above) - | | | - | | +- vTaskDelay (see above) - | | - | +- vStartDynamicPriorityTasks - | | | - | | +- xQueueCreate (see above) - | | | - | | +- vContinuousIncrementTask - | | | | - | | | +- uxTaskPriorityGet - | | | | - | | | +- vTaskPrioritySet - | | | | | - | | | | +- vListRemove (see above) - | | | | | - | | | | +- vListInsertEnd (see above) - | | | | - | | | +- _LINC - | | | - | | +- xTaskCreate (see above) - | | | - | | +- vLimitedIncrementTask - | | | | - | | | +- _LINC (see above) - | | | | - | | | +- _LCMP_P - | | | | - | | | +- vTaskSuspend - | | | | - | | | +- vListRemove (see above) - | | | | - | | | +- vListInsertEnd (see above) - | | | - | | +- vCounterControlTask - | | | | - | | | +- vTaskSuspend (see above) - | | | | - | | | +- vTaskResume - | | | | | - | | | | +- vListRemove (see above) - | | | | | - | | | | +- vListInsertEnd (see above) - | | | | - | | | +- vTaskDelay (see above) - | | | | - | | | +- vTaskSuspendAll (see above) - | | | | - | | | +- xTaskResumeAll (see above) - | | | - | | +- vQueueSendWhenSuspendedTask - | | | | - | | | +- vTaskSuspendAll (see above) - | | | | - | | | +- xQueueSend (see above) - | | | | - | | | +- xTaskResumeAll (see above) - | | | | - | | | +- vTaskDelay (see above) - | | | | - | | | +- _LINC (see above) - | | | - | | +- vQueueReceiveWhenSuspendedTask - | | | - | | +- vTaskSuspendAll (see above) - | | | - | | +- xQueueReceive (see above) - | | | - | | +- xTaskResumeAll (see above) - | | | - | | +- _LINC (see above) - | | - | +- vErrorChecks - | | | - | | +- xTaskGetTickCount (see above) - | | | - | | +- vTaskDelayUntil (see above) - | | | - | | +- prvCheckOtherTasksAreStillRunning - | | | | - | | | +- xArePollingQueuesStillRunning - | | | | - | | | +- xAreDynamicPriorityTasksStillRunning - | | | - | | +- _LCMP - | | | - | | +- vParTestToggleLED (see above) - | | - | +- xTaskCreate (see above) - | | - | +- vButtonTask - | | | - | | +- xQueueCreate (see above) - | | | - | | +- ButtonInterrupt_Enable - | | | - | | +- xQueueReceive (see above) - | | | - | | +- vParTestToggleLED (see above) - | | - | +- vTaskStartScheduler - | | - | +- prvIdleTask - | | | - | | +- prvCheckTasksWaitingTermination - | | | - | | +- vApplicationIdleHook - | | | - | | +- _LNEG - | | | - | | +- _LDIVS - | | | | - | | | +- _NEG_P - | | | | - | | | +- _lDivMod - | | | - | | +- _LCMP_P (see above) - | | - | +- xTaskCreate (see above) - | | - | +- xPortStartScheduler - | | - | +- xBankedStartScheduler - | | - | +- prvSetupTimerInterrupt - | | - | +- TickTimer_SetFreqHz - | | | - | | +- _LDIVU - | | | | - | | | +- _lDivMod (see above) - | | | - | | +- PE_Timer_LngHi1 - | | | | - | | | +- _LCMP (see above) - | | | - | | +- SetCV (see above) - | | - | +- TickTimer_Enable - | | - | +- HWEnDi (see above) - | - +- _EntryPoint - | - +- _Startup - | - +- Init - - _vect - | - +- Cpu_Interrupt - | - +- vButtonPush - | | - | +- xQueueSendFromISR - | | | - | | +- _memcpy_8bitCount (see above) - | | | - | | +- xTaskRemoveFromEventList (see above) - | | - | +- vTaskSwitchContext - | - +- vPortTickInterrupt - | | - | +- vTaskIncrementTick (see above) - | | - | +- vTaskSwitchContext (see above) - | - +- vPortYield - | | - | +- vTaskSwitchContext (see above) - | - +- _EntryPoint (see above) - -********************************************************************************************* -STATISTIC SECTION ---------------------------------------------------------------------------------------------- - -ExeFile: --------- -Number of blocks to be downloaded: 11 -Total size of all blocks to be downloaded: 5207 - diff --git a/Demo/HCS12_CodeWarrior_small/cmd/Simulator_Postload.cmd b/Demo/HCS12_CodeWarrior_small/cmd/Simulator_Postload.cmd deleted file mode 100644 index 0a5372487..000000000 --- a/Demo/HCS12_CodeWarrior_small/cmd/Simulator_Postload.cmd +++ /dev/null @@ -1,3 +0,0 @@ -// After load the commands written below will be executed -// Show main function at startup -FindProc main diff --git a/Demo/HCS12_CodeWarrior_small/cmd/Simulator_Preload.cmd b/Demo/HCS12_CodeWarrior_small/cmd/Simulator_Preload.cmd deleted file mode 100644 index 691c5eede..000000000 --- a/Demo/HCS12_CodeWarrior_small/cmd/Simulator_Preload.cmd +++ /dev/null @@ -1 +0,0 @@ -// Before load the commands written below will be executed diff --git a/Demo/HCS12_CodeWarrior_small/cmd/Simulator_Reset.cmd b/Demo/HCS12_CodeWarrior_small/cmd/Simulator_Reset.cmd deleted file mode 100644 index f0fc87448..000000000 --- a/Demo/HCS12_CodeWarrior_small/cmd/Simulator_Reset.cmd +++ /dev/null @@ -1 +0,0 @@ -// After reset the commands written below will be executed diff --git a/Demo/HCS12_CodeWarrior_small/cmd/Simulator_SetCPU.cmd b/Demo/HCS12_CodeWarrior_small/cmd/Simulator_SetCPU.cmd deleted file mode 100644 index 5f2b5a568..000000000 --- a/Demo/HCS12_CodeWarrior_small/cmd/Simulator_SetCPU.cmd +++ /dev/null @@ -1 +0,0 @@ -// At startup the commands written below will be executed diff --git a/Demo/HCS12_CodeWarrior_small/cmd/Simulator_Startup.cmd b/Demo/HCS12_CodeWarrior_small/cmd/Simulator_Startup.cmd deleted file mode 100644 index 5f2b5a568..000000000 --- a/Demo/HCS12_CodeWarrior_small/cmd/Simulator_Startup.cmd +++ /dev/null @@ -1 +0,0 @@ -// At startup the commands written below will be executed diff --git a/Demo/HCS12_CodeWarrior_small/cmd/SofTec_Postload.cmd b/Demo/HCS12_CodeWarrior_small/cmd/SofTec_Postload.cmd deleted file mode 100644 index 0a5372487..000000000 --- a/Demo/HCS12_CodeWarrior_small/cmd/SofTec_Postload.cmd +++ /dev/null @@ -1,3 +0,0 @@ -// After load the commands written below will be executed -// Show main function at startup -FindProc main diff --git a/Demo/HCS12_CodeWarrior_small/cmd/SofTec_Preload.cmd b/Demo/HCS12_CodeWarrior_small/cmd/SofTec_Preload.cmd deleted file mode 100644 index 691c5eede..000000000 --- a/Demo/HCS12_CodeWarrior_small/cmd/SofTec_Preload.cmd +++ /dev/null @@ -1 +0,0 @@ -// Before load the commands written below will be executed diff --git a/Demo/HCS12_CodeWarrior_small/cmd/SofTec_Reset.cmd b/Demo/HCS12_CodeWarrior_small/cmd/SofTec_Reset.cmd deleted file mode 100644 index f0fc87448..000000000 --- a/Demo/HCS12_CodeWarrior_small/cmd/SofTec_Reset.cmd +++ /dev/null @@ -1 +0,0 @@ -// After reset the commands written below will be executed diff --git a/Demo/HCS12_CodeWarrior_small/cmd/SofTec_Startup.cmd b/Demo/HCS12_CodeWarrior_small/cmd/SofTec_Startup.cmd deleted file mode 100644 index 5f2b5a568..000000000 --- a/Demo/HCS12_CodeWarrior_small/cmd/SofTec_Startup.cmd +++ /dev/null @@ -1 +0,0 @@ -// At startup the commands written below will be executed diff --git a/Demo/HCS12_CodeWarrior_small/main.c b/Demo/HCS12_CodeWarrior_small/main.c deleted file mode 100644 index 1400fe3f0..000000000 --- a/Demo/HCS12_CodeWarrior_small/main.c +++ /dev/null @@ -1,364 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/* - * - * vMain() is effectively the demo application entry point. It is called by - * the main() function generated by the Processor Expert application. - * - * vMain() creates all the demo application tasks, then starts the scheduler. - * The WEB documentation provides more details of the demo application tasks. - * - * Main.c also creates a task called "Check". This only executes every three - * seconds but has the highest priority so is guaranteed to get processor time. - * Its main function is to check that all the other tasks are still operational. - * Each task (other than the "flash" tasks) maintains a unique count that is - * incremented each time the task successfully completes its function. Should - * any error occur within such a task the count is permanently halted. The - * check task inspects the count of each task to ensure it has changed since - * the last time the check task executed. If all the count variables have - * changed all the tasks are still executing error free, and the check task - * toggles the onboard LED. Should any task contain an error at any time - * the LED toggle rate will change from 3 seconds to 500ms. - * - * This file also includes the functionality normally implemented within the - * standard demo application file integer.c. Due to the limited memory - * available on the microcontroller the functionality has been included within - * the idle task hook [vApplicationIdleHook()] - instead of within the usual - * separate task. See the documentation within integer.c for the rationale - * of the integer task functionality. - * - * - * - * The demo applications included with other FreeRTOS ports make use of the - * standard ComTest tasks. These use a loopback connector to transmit and - * receive RS232 characters between two tasks. The test is important for two - * reasons: - * - * 1) It tests the mechanism of context switching from within an application - * ISR. - * - * 2) It generates some randomised timing. - * - * The demo board used to develop this port does not include an RS232 interface - * so the ComTest tasks could not easily be included. Instead these two tests - * are created using a 'Button Push' task. - * - * The 'Button Push' task blocks on a queue, waiting for data to arrive. A - * simple interrupt routine connected to the PP0 input on the demo board places - * data in the queue each time the PP0 button is pushed (this button is built - * onto the demo board). As the 'Button Push' task is created with a - * relatively high priority it will unblock and want to execute as soon as data - * arrives in the queue - resulting in a context switch within the PP0 input - * ISR. If the data retrieved from the queue is that expected the 'Button Push' - * task toggles LED 5. Therefore correct operation is indicated by the LED - * toggling each time the PP0 button is pressed. - * - * This test is not as satisfactory as the ComTest method - but the simple - * nature of the port makes is just about adequate. - * - */ - -/* Kernel includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" - -/* Demo application includes. */ -#include "flash.h" -#include "PollQ.h" -#include "dynamic.h" -#include "partest.h" - -/* Processor expert includes. */ -#include "ButtonInterrupt.h" - -/*----------------------------------------------------------- - Definitions. ------------------------------------------------------------*/ - -/* Priorities assigned to demo application tasks. */ -#define mainFLASH_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainBUTTON_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) - -/* LED that is toggled by the check task. The check task periodically checks -that all the other tasks are operating without error. If no errors are found -the LED is toggled with mainCHECK_PERIOD frequency. If an error is found -then the toggle rate increases to mainERROR_CHECK_PERIOD. */ -#define mainCHECK_TASK_LED ( 7 ) -#define mainCHECK_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS ) -#define mainERROR_CHECK_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS ) - -/* LED that is toggled by the button push interrupt. */ -#define mainBUTTON_PUSH_LED ( 5 ) - -/* The constants used in the idle task calculation. */ -#define intgCONST1 ( ( portLONG ) 123 ) -#define intgCONST2 ( ( portLONG ) 234567 ) -#define intgCONST3 ( ( portLONG ) -3 ) -#define intgCONST4 ( ( portLONG ) 7 ) -#define intgEXPECTED_ANSWER ( ( ( intgCONST1 + intgCONST2 ) * intgCONST3 ) / intgCONST4 ) - -/* The length of the queue between is button push ISR and the Button Push task -is greater than 1 to account for switch bounces generating multiple inputs. */ -#define mainBUTTON_QUEUE_SIZE 6 - -/*----------------------------------------------------------- - Local functions prototypes. ------------------------------------------------------------*/ - -/* - * The 'Check' task function. See the explanation at the top of the file. - */ -static void vErrorChecks( void* pvParameters ); - -/* - * The 'Button Push' task. See the explanation at the top of the file. - */ -static void vButtonTask( void *pvParameters ); - -/* - * The idle task hook - in which the integer task is implemented. See the - * explanation at the top of the file. - */ -void vApplicationIdleHook( void ); - -/* - * Checks the unique counts of other tasks to ensure they are still operational. - */ -static portLONG prvCheckOtherTasksAreStillRunning( void ); - - - -/*----------------------------------------------------------- - Local variables. ------------------------------------------------------------*/ - -/* A few tasks are defined within this file. This flag is used to indicate -their status. If an error is detected in one of the locally defined tasks then -this flag is set to pdTRUE. */ -portBASE_TYPE xLocalError = pdFALSE; - -/* The queue used to send data from the button push ISR to the Button Push -task. */ -static xQueueHandle xButtonQueue; - - -/*-----------------------------------------------------------*/ - -/* - * This is called from the main() function generated by the Processor Expert. - */ -void vMain( void ) -{ - /* Start some of the standard demo tasks. */ - vStartLEDFlashTasks( mainFLASH_PRIORITY ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartDynamicPriorityTasks(); - - /* Start the locally defined tasks. There is also a task implemented as - the idle hook. */ - xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - xTaskCreate( vButtonTask, "Button", configMINIMAL_STACK_SIZE, NULL, mainBUTTON_TASK_PRIORITY, NULL ); - - /* All the tasks have been created - start the scheduler. */ - vTaskStartScheduler(); - - /* Should not reach here! */ - for( ;; ); -} -/*-----------------------------------------------------------*/ - -static void vErrorChecks( void *pvParameters ) -{ -portTickType xDelayPeriod = mainCHECK_PERIOD; -portTickType xLastWakeTime; - - /* Initialise xLastWakeTime to ensure the first call to vTaskDelayUntil() - functions correctly. */ - xLastWakeTime = xTaskGetTickCount(); - - for( ;; ) - { - /* Delay until it is time to execute again. The delay period is - shorter following an error. */ - vTaskDelayUntil( &xLastWakeTime, xDelayPeriod ); - - /* Check all the demo application tasks are executing without - error. If an error is found the delay period is shortened - this - has the effect of increasing the flash rate of the 'check' task - LED. */ - if( prvCheckOtherTasksAreStillRunning() == pdFAIL ) - { - /* An error has been detected in one of the tasks - flash faster. */ - xDelayPeriod = mainERROR_CHECK_PERIOD; - } - - /* Toggle the LED each cycle round. */ - vParTestToggleLED( mainCHECK_TASK_LED ); - } -} -/*-----------------------------------------------------------*/ - -static portLONG prvCheckOtherTasksAreStillRunning( void ) -{ -portBASE_TYPE xAllTasksPassed = pdPASS; - - if( xArePollingQueuesStillRunning() != pdTRUE ) - { - xAllTasksPassed = pdFAIL; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - xAllTasksPassed = pdFAIL; - } - - /* Also check the status flag for the tasks defined within this function. */ - if( xLocalError != pdFALSE ) - { - xAllTasksPassed = pdFAIL; - } - - return xAllTasksPassed; -} -/*-----------------------------------------------------------*/ - -void vApplicationIdleHook( void ) -{ -/* This variable is effectively set to a constant so it is made volatile to -ensure the compiler does not just get rid of it. */ -volatile portLONG lValue; - - /* Keep performing a calculation and checking the result against a constant. */ - for( ;; ) - { - /* Perform the calculation. This will store partial value in - registers, resulting in a good test of the context switch mechanism. */ - lValue = intgCONST1; - lValue += intgCONST2; - lValue *= intgCONST3; - lValue /= intgCONST4; - - /* Did we perform the calculation correctly with no corruption? */ - if( lValue != intgEXPECTED_ANSWER ) - { - /* Error! */ - portENTER_CRITICAL(); - xLocalError = pdTRUE; - portEXIT_CRITICAL(); - } - - /* Yield in case cooperative scheduling is being used. */ - #if configUSE_PREEMPTION == 0 - { - taskYIELD(); - } - #endif - } -} -/*-----------------------------------------------------------*/ - -static void vButtonTask( void *pvParameters ) -{ -unsigned portBASE_TYPE uxExpected = 1, uxReceived; - - /* Create the queue used by the producer and consumer. */ - xButtonQueue = xQueueCreate( mainBUTTON_QUEUE_SIZE, ( unsigned portBASE_TYPE ) sizeof( unsigned portBASE_TYPE ) ); - - if( xButtonQueue ) - { - /* Now the queue is created it is safe to enable the button interrupt. */ - ButtonInterrupt_Enable(); - - for( ;; ) - { - /* Simply wait for data to arrive from the button push interrupt. */ - if( xQueueReceive( xButtonQueue, &uxReceived, portMAX_DELAY ) == pdPASS ) - { - /* Was the data we received that expected? */ - if( uxReceived != uxExpected ) - { - /* Error! */ - portENTER_CRITICAL(); - xLocalError = pdTRUE; - portEXIT_CRITICAL(); - } - else - { - /* Toggle the LED for every successful push. */ - vParTestToggleLED( mainBUTTON_PUSH_LED ); - } - - uxExpected++; - } - } - } - - /* Will only get here if the queue could not be created. */ - for( ;; ); -} -/*-----------------------------------------------------------*/ - -#pragma CODE_SEG __NEAR_SEG NON_BANKED - - /* Button push ISR. */ - void interrupt vButtonPush( void ) - { - static unsigned portBASE_TYPE uxValToSend = 0; - - /* Send an incrementing value to the button push task each run. */ - uxValToSend++; - - /* Clear the interrupt flag. */ - PIFP = 1; - - /* Send the incremented value down the queue. The button push task is - blocked waiting for the data. As the button push task is high priority - it will wake and a context switch should be performed before leaving - the ISR. */ - if( xQueueSendFromISR( xButtonQueue, &uxValToSend, pdFALSE ) ) - { - /* NOTE: This macro can only be used if there are no local - variables defined. This function uses a static variable so it's - use is permitted. If the variable were not static portYIELD() - would have to be used in it's place. */ - portTASK_SWITCH_FROM_ISR(); - } - } - -#pragma CODE_SEG DEFAULT - - diff --git a/Demo/HCS12_CodeWarrior_small/prm/burner.bbl b/Demo/HCS12_CodeWarrior_small/prm/burner.bbl deleted file mode 100644 index 639ffdef3..000000000 --- a/Demo/HCS12_CodeWarrior_small/prm/burner.bbl +++ /dev/null @@ -1,223 +0,0 @@ -/* logical s-record file */ -OPENFILE "%ABS_FILE%.s19" -format=motorola -busWidth=1 -origin=0 -len=0x1000000 -destination=0 -SRECORD=Sx -SENDBYTE 1 "%ABS_FILE%" -CLOSE - -/* physical s-record file */ -OPENFILE "%ABS_FILE%.phy" -format = motorola -busWidth = 1 -len = 0x4000 - -origin = 0x008000 -destination = 0x000000 -SENDBYTE 1 "%ABS_FILE%" -origin = 0x018000 -destination = 0x004000 -SENDBYTE 1 "%ABS_FILE%" -origin = 0x028000 -destination = 0x008000 -SENDBYTE 1 "%ABS_FILE%" -origin = 0x038000 -destination = 0x00C000 -SENDBYTE 1 "%ABS_FILE%" -origin = 0x048000 -destination = 0x010000 -SENDBYTE 1 "%ABS_FILE%" -origin = 0x058000 -destination = 0x014000 -SENDBYTE 1 "%ABS_FILE%" -origin = 0x068000 -destination = 0x018000 -SENDBYTE 1 "%ABS_FILE%" -origin = 0x078000 -destination = 0x01C000 -SENDBYTE 1 "%ABS_FILE%" -origin = 0x088000 -destination = 0x020000 -SENDBYTE 1 "%ABS_FILE%" -origin = 0x098000 -destination = 0x024000 -SENDBYTE 1 "%ABS_FILE%" -origin = 0x0A8000 -destination = 0x028000 -SENDBYTE 1 "%ABS_FILE%" -origin = 0x0B8000 -destination = 0x02C000 -SENDBYTE 1 "%ABS_FILE%" -origin = 0x0C8000 -destination = 0x030000 -SENDBYTE 1 "%ABS_FILE%" -origin = 0x0D8000 -destination = 0x034000 -SENDBYTE 1 "%ABS_FILE%" -origin = 0x0E8000 -destination = 0x038000 -SENDBYTE 1 "%ABS_FILE%" -origin = 0x0F8000 -destination = 0x03C000 -SENDBYTE 1 "%ABS_FILE%" - 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-origin = 0x3F8000 -destination = 0x0FC000 -SENDBYTE 1 "%ABS_FILE%" -origin = 0x00C000 -destination = 0x0FC000 -SENDBYTE 1 "%ABS_FILE%" - -CLOSE - diff --git a/Demo/HCS12_CodeWarrior_small/readme.txt b/Demo/HCS12_CodeWarrior_small/readme.txt deleted file mode 100644 index 417a9af56..000000000 --- a/Demo/HCS12_CodeWarrior_small/readme.txt +++ /dev/null @@ -1,117 +0,0 @@ -//------------------------------------------------------------------------ -// Readme.txt -//------------------------------------------------------------------------ -This project stationery is designed to get you up and running -quickly with CodeWarrior for MC9S12C32. -It is set up for the selected CPU and target connection, -but can be easily modified. - -Sample code for the following language(s) is at your disposal: -- C - -The wizard has prepared CodeWarrior target(s) with the connection methods of -your choice: -- Simulator: - This interface/target is prepared to use the FCS (Full Chip Simulation). - -- SofTec: - This target interface connects to any of the USB-based SofTec Microsystems tools for HC(S)12. - - -Additional connections can be chosen in the simulator/debugger, -use the menu Component > Set Target. - -//------------------------------------------------------------------------ -// Processor Expert -//------------------------------------------------------------------------ -This project is prepared to be designed with Processor Expert. -The project has an additional 'tab' named 'Processor Expert' where you -can configure the CPU and its beans. -The CPU selected is inserted into the Processor Expert project panel, in -the Debug and Release configurations. -Change of the configuration is possible by the mouse double-click on it. -All the installed Embedded Beans are accessible in the Bean Selector -window, grouped into folders according to their function. The mouse -double-click on selected Embedded Bean in the Bean Selector window adds -the Bean to the project. The mouse double-click on the Bean icon in the -Project panel opens the Bean Inspector window, which is used to set the -Bean properties. Source code is generated after selecting the -(Code Design 'Project_name.mcp') menu command from the CodeWarrior main -window (Processor Expert > Code design 'Project_name.mcp'). -Use the bean methods and events to write your code in the main module -'Project_name'.c and the event module Events.c. - -For more help please read Processor Expert help: - (Processor Expert > Help > 'Topic'). - -The following folders are used in CodeWarrior project window for -ProcessorExpert: -- User modules: contains your sources. The main module 'Project_name'.c - and event module Events.c are located here after the Processor Expert - code generation. -- Prm: Linker parameter file used for linking. Note that the file used - for the linker is specified in the Linker Preference Panel. To open - the Preference Panel, please press or open the - (Edit > 'Current Build Target Name' Settings...) menu item in the - CodeWarrior main window menu, while the project window is opened). - After Processor Expert code generation 'Project_name'.prm file - will be placed here. You can switch off the .prm file generation in - Processor Expert if you want (in the CPU bean, Build Options) -- Generated code: this folder appears after the Processor Expert code - generation and contains generated code from Processor Expert. -- Doc: other files generated from the Processor Expert (documentation) - -//------------------------------------------------------------------------ -// Getting Started -//------------------------------------------------------------------------ -To build/debug your project, use the menu Project > Debug or press F5. -This will open the simulator/debugger. -Press again F5 in the debugger (or menu Run > Start/Continue) to start -the application. The menu Run > Halt or F6 stops the application. -In the debugger menu Component > Open you can load additional components. - -//------------------------------------------------------------------------ -// Project structure -//------------------------------------------------------------------------ -The project generated contains various files/folders: -- readme.txt: this file -- Sources: folder with the application source code -- Startup Code: C/C++ startup code -- Prm: - - burner.bbl file to generate S-Records -- Linker Map: the .map file generated by the linker -- Libraries: needed library files (ANSI, derivative header/implementation files) -- Debugger Project File: contains a .ini file for the debugger for each - connection -- Debugger Cmd Files: contains sub-folders for each connection with command - files - -//------------------------------------------------------------------------ -// Adding your own code -//------------------------------------------------------------------------ -Once everything is working as expected, you can begin adding your own code -to the project. Keep in mind that we provide this as an example of how to -get up and running quickly with CodeWarrior. There are certainly other -ways to handle interrupts and set up your linker command file. Feel free -to modify any of the source files provided. - -//------------------------------------------------------------------------ -// Simulator/Debugger: Additional components -//------------------------------------------------------------------------ -In the simulator/debugger, you can load additional components. Try the menu -Component > Open. - -//------------------------------------------------------------------------ -// Additional documentation -//------------------------------------------------------------------------ -Check out the online documentation provided. Use in CodeWarrior IDE the -menu Help > Online Manuals. - -//------------------------------------------------------------------------ -// Contacting Metrowerks -//------------------------------------------------------------------------ -For bug reports, technical questions, and suggestions, please use the -forms installed in the Release_Notes folder and send them to: -USA: support@metrowerks.com -EUROPE: support_europe@metrowerks.com -ASIA/PACIFIC: j-emb-sup@metrowerks.com \ No newline at end of file diff --git a/Demo/HCS12_CodeWarrior_small/serial/serial.c b/Demo/HCS12_CodeWarrior_small/serial/serial.c deleted file mode 100644 index 1743d20b0..000000000 --- a/Demo/HCS12_CodeWarrior_small/serial/serial.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER for port 1. - -Note that this driver is written to test the RTOS port and is not intended -to represent an optimised solution. */ - -/* Standard include files. */ -#include - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "queue.h" -#include "task.h" - -/* Demo application include files. */ -#include "serial.h" - - -/* - * Initialise port 1 for interrupt driven communications. - */ -xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) -{ - return NULL; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) -{ - return pdFALSE; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) -{ -signed portBASE_TYPE xReturn = pdPASS; - - return xReturn; -} -/*-----------------------------------------------------------*/ - -void vSerialClose( xComPortHandle xPort ) -{ - /* Not supported. */ - ( void ) xPort; -} -/*-----------------------------------------------------------*/ - diff --git a/Demo/HCS12_GCC_banked/FreeRTOSConfig.h b/Demo/HCS12_GCC_banked/FreeRTOSConfig.h deleted file mode 100644 index 36d36dddb..000000000 --- a/Demo/HCS12_GCC_banked/FreeRTOSConfig.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/** - * FreeRTOSConfig.h configures FreeRTOS for GCC/HCS12 version of FreeRTOS Demo - * - * Modified by Jefferson L Smith, Robotronics Inc. - */ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/* This port requires the compiler to generate code for the BANKED memory -model. */ -#define BANKED_MODEL - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 1 -#define configUSE_TICK_HOOK 0 -#define configTICK_RATE_HZ ( ( portTickType ) 977 ) -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 300/*128*/ ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 10752 ) ) -#define configMAX_TASK_NAME_LEN ( 3 ) -#define configUSE_TRACE_FACILITY 0 -#define configUSE_16_BIT_TICKS 1 -#define configIDLE_SHOULD_YIELD 1 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* This parameter is normally affects the clock frequency. In this port, at the moment -it might just be used for reference. */ - -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 24000000 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 - - - - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/HCS12_GCC_banked/Makefile b/Demo/HCS12_GCC_banked/Makefile deleted file mode 100644 index 4d19f27c7..000000000 --- a/Demo/HCS12_GCC_banked/Makefile +++ /dev/null @@ -1,64 +0,0 @@ -# Demo for GCC/HCS12 port of FreeRTOS -# Author Jefferson Smith -# -SRCDIR=../.. -RTOS_BASEDIR=$(SRCDIR)/Source - -# what board to compile for -TARGET_BOARD ?= dragon12-rom -CPU=m68hcs12 - -DEVC_PREFIX=m6811-elf- -CC=$(DEVC_PREFIX)gcc -AS=$(DEVC_PREFIX)as -AR=$(DEVC_PREFIX)ar -OBJCOPY=$(DEVC_PREFIX)objcopy -OBJDUMP=$(DEVC_PREFIX)objdump - -CPPFLAGS+=-I. -I./asm-$(CPU)/arch-dragon12 -I../Common/include \ - -I$(RTOS_BASEDIR)/include -DGCC_HCS12 -DM6812_DEF_SCI=1 -DPORT_LED=M6811_PORTB - -CFLAGS+=-$(CPU) -mshort -mlong-calls -g -Os -Wall -Wmissing-prototypes \ - -Wno-char-subscripts -fomit-frame-pointer -msoft-reg-count=0 -mauto-incdec -#-Os -fomit-frame-pointer - -LDFLAGS+=-$(CPU) -mshort -mlong-calls -Wl,-T,ldscript-rtos.x - -OBJCOPY_FLAGS=--srec-len=0x20 --change-addresses 0xffff0000 - -CSRCS=main.c startup.c vectors.c serial.c sci.c ParTest.c gelfunc.c \ - ../Common/Minimal/flash.c \ - ../Common/Minimal/dynamic.c \ - ../Common/Minimal/BlockQ.c \ - ../Common/Minimal/PollQ.c \ - ../Common/Minimal/comtest.c \ - ../Common/Minimal/integer.c \ - ../Common/Minimal/death.c \ - -RTOS_OBJS = $(RTOS_BASEDIR)/portable/GCC/HCS12/port.c \ - $(RTOS_BASEDIR)/portable/MemMang/heap_2.c \ - $(RTOS_BASEDIR)/list.c \ - $(RTOS_BASEDIR)/tasks.c \ - $(RTOS_BASEDIR)/queue.c - -OBJS=$(CSRCS:.c=.o) $(RTOS_OBJS:.c=.o) - -# -# *.elf for the simulator and gdb -# *.s19 is original S Records from ld -# *.s2 is S2 Records (from SRecCvt.exe) -# -all:: main.elf main.lst main.s19 - -main.elf: $(OBJS) - $(CC) $(LDFLAGS) -o $@ $^ -lc -lbcc -lc - -%.lst: %.elf - $(OBJDUMP) -htS $< >$@ - -%.s19: %.elf - $(OBJCOPY) --output-target=srec $(OBJCOPY_FLAGS) $< $*.s19 - -clean:: - $(RM) $(OBJS) *.elf *.s19 - diff --git a/Demo/HCS12_GCC_banked/PE_Error.h b/Demo/HCS12_GCC_banked/PE_Error.h deleted file mode 100644 index bc1ca1a57..000000000 --- a/Demo/HCS12_GCC_banked/PE_Error.h +++ /dev/null @@ -1,53 +0,0 @@ -/** ################################################################### -** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. -** Filename : PE_Error.H -** Project : RTOSDemo -** Processor : MC9S12DP256BCPV -** Beantype : PE_Error -** Version : Driver 01.00 -** Compiler : Metrowerks HC12 C Compiler -** Date/Time : 13/06/2005, 20:14 -** Abstract : -** This bean "PE_Error" contains internal definitions -** of the error constants. -** Settings : -** Contents : -** No public methods -** -** (c) Copyright UNIS, spol. s r.o. 1997-2002 -** UNIS, spol. s r.o. -** Jundrovska 33 -** 624 00 Brno -** Czech Republic -** http : www.processorexpert.com -** mail : info@processorexpert.com -** ###################################################################*/ - -#ifndef __PE_Error_H -#define __PE_Error_H - -#define ERR_OK 0 /* OK */ -#define ERR_SPEED 1 /* This device does not work in the active speed mode. */ -#define ERR_RANGE 2 /* Parameter out of range. */ -#define ERR_VALUE 3 /* Parameter of incorrect value. */ -#define ERR_OVERFLOW 4 /* Timer overflow. */ -#define ERR_MATH 5 /* Overflow during evaluation. */ -#define ERR_ENABLED 6 /* Device is enabled. */ -#define ERR_DISABLED 7 /* Device is disabled. */ -#define ERR_BUSY 8 /* Device is busy. */ -#define ERR_NOTAVAIL 9 /* Requested value or method not available. */ -#define ERR_RXEMPTY 10 /* No data in receiver. */ -#define ERR_TXFULL 11 /* Transmitter is full. */ -#define ERR_BUSOFF 12 /* Bus not available. */ -#define ERR_OVERRUN 13 /* Overrun error is detected. */ -#define ERR_FRAMING 14 /* Framing error is detected. */ -#define ERR_PARITY 15 /* Parity error is detected. */ -#define ERR_NOISE 16 /* Noise error is detected. */ -#define ERR_IDLE 17 /* Idle error is detectes. */ -#define ERR_FAULT 18 /* Fault error is detected. */ -#define ERR_BREAK 19 /* Break char is received during communication. */ -#define ERR_CRC 20 /* CRC error is detected. */ -#define ERR_ARBITR 21 /* A node losts arbitration. This error occurs if two nodes start transmission at the same time. */ -#define ERR_PROTECT 22 /* Protection error is detected. */ - -#endif //__PE_Error_H diff --git a/Demo/HCS12_GCC_banked/ParTest.c b/Demo/HCS12_GCC_banked/ParTest.c deleted file mode 100644 index a593d0c47..000000000 --- a/Demo/HCS12_GCC_banked/ParTest.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/** - * ParTest.c controls bits (LEDs) for GCC/HCS12 version of FreeRTOS Demo - * - * Modified from CodeWarrior/HCS12 by Jefferson L Smith, Robotronics Inc. - */ - -#include - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "portable.h" - -/* Demo application include files. */ -#include "partest.h" - -#define LEDIO PORTIO_8(PORT_LED) - -/*----------------------------------------------------------- - * Simple parallel port IO routines. - *-----------------------------------------------------------*/ - -void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) -{ - /* This function is required as it is called from the standard demo - application files. It manipulates a bit to control one LED. */ - portENTER_CRITICAL(); - - if (xValue) { /* Is it one to be written? */ - LEDIO |= (1< -#include - -/* Initialize SCI serial port to default baudrate and enable. */ -extern inline void -serial_init (void) -{ - SCIBD = M6811_DEF_BAUD; - SCICR1 = 0x00; //typical 8 bit - SCICR2 = 0x0c; //Enable sci for polling -} - -/* Return != 0 if there is something to read on the serial line. */ -extern inline unsigned char -serial_receive_pending (void) -{ - return SCISR1 & RDRF; -} - -/* Wait until the SIO has finished to send the character. */ -extern inline void -serial_flush (void) -{ - while (!(SCISR1 & TDRE)) - cop_optional_reset (); -} - -/* Return != 0 if serial port is ready to send another char. */ -extern inline unsigned char -serial_send_ready (void) -{ - return SCISR1 & TDRE; -} - -/* Send the character on the serial line. */ -extern inline void -serial_send (char c) -{ - serial_flush (); - SCIDRL = c; - SCICR2 |= (1<<3); -} - -/* Wait for a character on the serial line and return it. */ -extern inline unsigned char -serial_recv (void) -{ - while (!(SCISR1 & RDRF)) - cop_optional_reset (); - - return SCIDRL; -} - -extern void serial_print (const char *msg); -extern void serial_getline (char *buf); - -#endif /* _M68HC11_SIO_H */ - diff --git a/Demo/HCS12_GCC_banked/cpu.h b/Demo/HCS12_GCC_banked/cpu.h deleted file mode 100644 index dfbfbe767..000000000 --- a/Demo/HCS12_GCC_banked/cpu.h +++ /dev/null @@ -1,39 +0,0 @@ -/** - * sci.c controls SCI for GCC/HCS12 version of FreeRTOS Demo - * To replace CodeWarrior Cpu.h - * - * Author Jefferson L Smith, Robotronics Inc. - */ - -#ifndef __Cpu -#define __Cpu - -/*Types definition*/ -typedef unsigned char bool; -typedef unsigned char byte; -typedef unsigned int word; -typedef unsigned long dword; - -#define ATTR_INT __attribute__((interrupt)) -#define ATTR_FAR __attribute__((far)) -#define ATTR_NEAR __attribute__((near)) -#define ATTR_BANK0 __attribute__((far,section (".bank0"))) -#define ATTR_BANK1 __attribute__((far,section (".bank1"))) -#define ATTR_BANK2 __attribute__((far,section (".bank2"))) -#define ATTR_BANK3 __attribute__((far,section (".bank3"))) -#define ATTR_BANK4 __attribute__((far,section (".bank4"))) -#define ATTR_BANK5 __attribute__((far,section (".bank5"))) -#define ATTR_BANK6 __attribute__((far,section (".bank6"))) -#define ATTR_BANK7 __attribute__((far,section (".bank7"))) -#define ATTR_BANK8 __attribute__((far,section (".bank8"))) -#define ATTR_BANK9 __attribute__((far,section (".bank9"))) -#define ATTR_BANK10 __attribute__((far,section (".bank10"))) -#define ATTR_BANK11 __attribute__((far,section (".bank11"))) -#define ATTR_BANK12 __attribute__((far,section (".bank12"))) -#define ATTR_BANK13 __attribute__((far,section (".bank13"))) - -#include "PE_Error.h" -#include -#include - -#endif /* ifndef __Cpu */ diff --git a/Demo/HCS12_GCC_banked/gelfunc.c b/Demo/HCS12_GCC_banked/gelfunc.c deleted file mode 100644 index dcecfb4da..000000000 --- a/Demo/HCS12_GCC_banked/gelfunc.c +++ /dev/null @@ -1,25 +0,0 @@ -/* gelfunc.c -- functions from GEL 1.6 - Author Jefferson Smith, Robotronics Inc. - -*/ - -#include "asm-m68hcs12/ports_def.h" -void cop_reset (void); -void cop_optional_reset (void); - -/* Reset the COP. */ -void -cop_reset (void) -{ - ARMCOP = 0x55; - ARMCOP = 0xAA; -} - -void -cop_optional_reset (void) -{ -#if defined(M6811_USE_COP) && M6811_USE_COP == 1 - cop_reset (); -#endif -} - diff --git a/Demo/HCS12_GCC_banked/ldscript-rtos.x b/Demo/HCS12_GCC_banked/ldscript-rtos.x deleted file mode 100644 index c495844ea..000000000 --- a/Demo/HCS12_GCC_banked/ldscript-rtos.x +++ /dev/null @@ -1,266 +0,0 @@ -/* Linker script for MC689S12DP256 Flash - rom banks. - - Author Jefferson L Smith; Robotronics, Inc. 2006 - */ -OUTPUT_FORMAT("elf32-m68hc12", "elf32-m68hc12", - "elf32-m68hc12") -OUTPUT_ARCH(m68hc12) -ENTRY(_start) - -/* Get memory banks definition from some user configuration file. - This file must be located in some linker directory (search path - with -L). See fixed memory banks emulation script. */ -INCLUDE memory.x; - -SECTIONS -{ - /* Concatenate .page0 sections. Put them in the page0 memory bank - unless we are creating a relocatable file. */ - .page0 : - { - *(.page0) - } > page0 - - /* PPAGE memory banks */ - - .bank0 : - { - *(.bank0) - . = ALIGN(2); - } > bank0 =0xff - .bank1 : - { - *(.bank1) - . = ALIGN(2); - } > bank1 =0xff - .bank2 : - { - *(.bank2) - . = ALIGN(2); - } > bank2 =0xff - .bank3 : - { - *(.bank3) - . = ALIGN(2); - } > bank3 =0xff - .bank4 : - { - *(.bank4) - . = ALIGN(2); - } > bank4 =0xff - .bank5 : - { - *(.bank5) - . = ALIGN(2); - } > bank5 =0xff - .bank6 : - { - *(.bank6) - . = ALIGN(2); - } > bank6 =0xff - .bank7 : - { - *(.bank7) - . = ALIGN(2); - } > bank7 =0xff - .bank8 : - { - *(.bank8) - . = ALIGN(2); - } > bank8 =0xff - .bank9 : - { - *(.bank9) - . = ALIGN(2); - } > bank9 =0xff - .bank10 : - { - *(.bank10) - . = ALIGN(2); - } > bank10 =0xff - .bank11 : - { - *(.bank11) - . = ALIGN(2); - } > bank11 =0xff - .bank12 : - { - *(.bank12) - . = ALIGN(2); - } > bank12 =0xff - .bank13 : - { - *(.bank13) - . = ALIGN(2); - } > bank13 =0xff - - /* Start of text section. */ - .text : - { - /* Put startup code at beginning so that _start keeps same address. */ - /* Startup code. */ - KEEP (*(.install0)) /* Section should setup the stack pointer. */ - KEEP (*(.install1)) /* Place holder for applications. */ - KEEP (*(.install2)) /* Optional installation of data sections in RAM. */ - KEEP (*(.install3)) /* Place holder for applications. */ - KEEP (*(.install4)) /* Section that calls the main. */ - *(.init) - *(.text) - *(.text.*) - *(.text_c) - /* .gnu.warning sections are handled specially by elf32.em. */ - *(.gnu.warning) - *(.gnu.linkonce.t.*) - *(.tramp) - *(.tramp.*) - /* Finish code. */ - KEEP (*(.fini0)) /* Beginning of finish code (_exit symbol). */ - KEEP (*(.fini1)) /* Place holder for applications. */ - KEEP (*(.fini2)) /* C++ destructors. */ - KEEP (*(.fini3)) /* Place holder for applications. */ - KEEP (*(.fini4)) /* Runtime exit. */ - _etext = .; - PROVIDE (etext = .); - . = ALIGN(2); - } > text AT>bank14 =0xff - - .text_h : - { - *(.text_h) /* Bootloader; high Flash area unbanked */ - . = ALIGN(2); - } > text_h AT>bank15 =0xff - .rodata : - { - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r*) - . = ALIGN(2); - } > text_h AT>bank15 =0xff - .eh_frame : - { - KEEP (*(.eh_frame)) - . = ALIGN(2); - } > text_h AT>bank15 =0xff - - /* Constructor and destructor tables are in ROM. */ - .ctors : - { - PROVIDE (__CTOR_LIST__ = .); - KEEP (*(.ctors)) - PROVIDE(__CTOR_END__ = .); - . = ALIGN(2); - } > text_h AT>bank15 =0xff - .dtors : - { - PROVIDE(__DTOR_LIST__ = .); - KEEP (*(.dtors)) - PROVIDE(__DTOR_END__ = .); - . = ALIGN(2); - } > text_h AT>bank15 =0xff - - /* Start of the data section image in ROM. */ - __data_image = .; - PROVIDE (__data_image = .); - - /* All read-only sections that normally go in PROM must be above. - We construct the DATA image section in PROM at end of all these - read-only sections. The data image must be copied at init time. - Refer to GNU ld, Section 3.6.8.2 Output Section LMA. */ - .data : - { - __data_section_start = .; - PROVIDE (__data_section_start = .); - *(.sdata) - *(.data) - *(.data.*) - *(.data1) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - _edata = .; - PROVIDE (edata = .); - . = ALIGN(2); - } > data AT>bank15 =0xff - __data_section_size = SIZEOF(.data); - __data_image_end = __data_image + __data_section_size; - PROVIDE (__data_section_size = SIZEOF(.data)); - /* .install : - { - . = _data_image_end; - } > text */ - /* Relocation for some bss and data sections. */ - .softregs : - { - __softregs_section_start = .; - *(.softregs) - __softregs_section_end = .; - } > data - __softregs_section_size = SIZEOF(.softregs); - .bss : - { - __bss_start = .; - *(.sbss) - *(.scommon) - *(.dynbss) - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - PROVIDE (_end = .); - } > data - __bss_size = SIZEOF(.bss); - PROVIDE (__bss_size = SIZEOF(.bss)); - .eeprom : - { - *(.eeprom) - *(.eeprom.*) - . = ALIGN(2); - } > eeprom =0xff - - /* If the 'vectors_addr' symbol is defined, it indicates the start address - of interrupt vectors. This depends on the 9S12 operating mode: - Addr - Hardware location LMA 0x10ff80, mirror 0xff80 - Called by dbug12 LMA 0x10ef80, mirror 0xef80 - Ram called by dbug12 0x3e00 - The default vectors address is (LMA) 0x10ff80. This can be overriden - with the '-defsym vectors_addr=0x...' ld option. - */ - PROVIDE (_vectors_addr = DEFINED (vectors_addr) ? vectors_addr : 0x10ff80); - .vectors DEFINED (vectors_addr) ? vectors_addr : 0x10ff80 : - { - KEEP (*(.vectors)) - } - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - Symbols in the DWARF debugging sections are relative to the beginning - of the section so we begin them at 0. - Treatment of DWARF debug section must be at end of the linker - script to avoid problems when there are undefined symbols. It's necessary - to avoid that the DWARF section is relocated before such undefined - symbols are found. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info) *(.gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } -} diff --git a/Demo/HCS12_GCC_banked/main.c b/Demo/HCS12_GCC_banked/main.c deleted file mode 100644 index bcf973584..000000000 --- a/Demo/HCS12_GCC_banked/main.c +++ /dev/null @@ -1,291 +0,0 @@ - -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/* - * - * main() creates all the demo application tasks, then starts the scheduler. - * The WEB documentation provides more details of the demo application tasks. - * - * main.c also creates a task called "Check". This only executes every three - * seconds but has the highest priority so is guaranteed to get processor time. - * Its main function is to check that all the other tasks are still operational. - * Each task (other than the "flash" tasks) maintains a unique count that is - * incremented each time the task successfully completes its function. Should - * any error occur within such a task the count is permanently halted. The - * check task inspects the count of each task to ensure it has changed since - * the last time the check task executed. If all the count variables have - * changed all the tasks are still executing error free, and the check task - * toggles the onboard LED. Should any task contain an error at any time - * the LED toggle rate will change from 3 seconds to 500ms. - * - * This file also includes the functionality implemented within the - * standard demo application file integer.c. This is done to demonstrate the - * use of an idle hook. See the documentation within integer.c for the - * rationale of the integer task functionality. - * */ - -/* Kernel includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" - -#include "cpu.h" - -/* special prototypes for memory-banked functions */ -void vStartPolledQueueTasks( unsigned portBASE_TYPE uxPriority ); -portBASE_TYPE xArePollingQueuesStillRunning( void ); - -/* Demo application includes. */ -#include "flash.h" -#include "PollQ.h" -#include "dynamic.h" -#include "partest.h" -#include "comtest2.h" -#include "BlockQ.h" -#include "integer.h" -#include "death.h" - - -/*----------------------------------------------------------- - Definitions. ------------------------------------------------------------*/ - -/* Priorities assigned to demo application tasks. */ -#define mainFLASH_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainDEATH_PRIORITY ( tskIDLE_PRIORITY + 1 ) - -/* LED that is toggled by the check task. The check task periodically checks -that all the other tasks are operating without error. If no errors are found -the LED is toggled with mainCHECK_PERIOD frequency. If an error is found -then the toggle rate increases to mainERROR_CHECK_PERIOD. */ -#define mainCHECK_TASK_LED ( 7 ) -#define mainCHECK_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS ) -#define mainERROR_CHECK_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS ) - -/* The constants used in the idle task calculation. */ -#define intgCONST1 ( ( portLONG ) 123 ) -#define intgCONST2 ( ( portLONG ) 234567 ) -#define intgCONST3 ( ( portLONG ) -3 ) -#define intgCONST4 ( ( portLONG ) 7 ) -#define intgEXPECTED_ANSWER ( ( ( intgCONST1 + intgCONST2 ) * intgCONST3 ) / intgCONST4 ) - - -/* Baud rate used by the serial port tasks (ComTest tasks). -IMPORTANT: The function COM0_SetBaudRateValue() which is generated by the -Processor Expert is used to set the baud rate. As configured in the FreeRTOS -download this value must be one of the following: - -0 to configure for 38400 baud. -1 to configure for 19200 baud. -2 to configure for 9600 baud. -3 to configure for 4800 baud. */ -#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 2 ) - -/* LED used by the serial port tasks. This is toggled on each character Tx, -and mainCOM_TEST_LED + 1 is toggles on each character Rx. */ -#define mainCOM_TEST_LED ( 3 ) - -/*----------------------------------------------------------- - Local functions prototypes. ------------------------------------------------------------*/ - -/* - * The 'Check' task function. See the explanation at the top of the file. - */ -static void ATTR_BANK1 vErrorChecks( void* pvParameters ); - -/* - * The idle task hook - in which the integer task is implemented. See the - * explanation at the top of the file. - */ -void ATTR_BANK0 vApplicationIdleHook( void ); - -/* - * Checks the unique counts of other tasks to ensure they are still operational. - */ -static portLONG ATTR_BANK0 prvCheckOtherTasksAreStillRunning( void ); - - - -/*----------------------------------------------------------- - Local variables. ------------------------------------------------------------*/ - -/* A few tasks are defined within this file. This flag is used to indicate -their status. If an error is detected in one of the locally defined tasks then -this flag is set to pdTRUE. */ -portBASE_TYPE xLocalError = pdFALSE; - - -/*-----------------------------------------------------------*/ - -/* This is called from startup. */ -int ATTR_BANK0 main ( void ) -{ - /* Start some of the standard demo tasks. */ - vStartLEDFlashTasks( mainFLASH_PRIORITY ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartDynamicPriorityTasks(); - vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - - /* Start the locally defined tasks. There is also a task implemented as - the idle hook. */ - xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - - /* Must be the last demo created. */ - vCreateSuicidalTasks( mainDEATH_PRIORITY ); - - /* All the tasks have been created - start the scheduler. */ - vTaskStartScheduler(); - - /* Should not reach here! */ - for( ;; ); - return 0; -} -/*-----------------------------------------------------------*/ - -static void vErrorChecks( void *pvParameters ) -{ -portTickType xDelayPeriod = mainCHECK_PERIOD; -portTickType xLastWakeTime; - - /* Initialise xLastWakeTime to ensure the first call to vTaskDelayUntil() - functions correctly. */ - xLastWakeTime = xTaskGetTickCount(); - - for( ;; ) - { - /* Delay until it is time to execute again. The delay period is - shorter following an error. */ - vTaskDelayUntil( &xLastWakeTime, xDelayPeriod ); - - /* Check all the demo application tasks are executing without - error. If an error is found the delay period is shortened - this - has the effect of increasing the flash rate of the 'check' task - LED. */ - if( prvCheckOtherTasksAreStillRunning() == pdFAIL ) - { - /* An error has been detected in one of the tasks - flash faster. */ - xDelayPeriod = mainERROR_CHECK_PERIOD; - } - - /* Toggle the LED each cycle round. */ - vParTestToggleLED( mainCHECK_TASK_LED ); - } -} -/*-----------------------------------------------------------*/ - -static portLONG prvCheckOtherTasksAreStillRunning( void ) -{ -portBASE_TYPE xAllTasksPassed = pdPASS; - - if( xArePollingQueuesStillRunning() != pdTRUE ) - { - xAllTasksPassed = pdFAIL; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - xAllTasksPassed = pdFAIL; - } - - if( xAreComTestTasksStillRunning() != pdTRUE ) - { - xAllTasksPassed = pdFALSE; - } - - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - xAllTasksPassed = pdFALSE; - } - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - xAllTasksPassed = pdFALSE; - } - - if( xIsCreateTaskStillRunning() != pdTRUE ) - { - xAllTasksPassed = pdFALSE; - } - - /* Also check the status flag for the tasks defined within this function. */ - if( xLocalError != pdFALSE ) - { - xAllTasksPassed = pdFAIL; - } - - return xAllTasksPassed; -} -/*-----------------------------------------------------------*/ - -void vApplicationIdleHook( void ) -{ -/* This variable is effectively set to a constant so it is made volatile to -ensure the compiler does not just get rid of it. */ -volatile portLONG lValue; - - /* Keep performing a calculation and checking the result against a constant. */ - - /* Perform the calculation. This will store partial value in - registers, resulting in a good test of the context switch mechanism. */ - lValue = intgCONST1; - lValue += intgCONST2; - lValue *= intgCONST3; - lValue /= intgCONST4; - - /* Did we perform the calculation correctly with no corruption? */ - if( lValue != intgEXPECTED_ANSWER ) - { - /* Error! */ - portENTER_CRITICAL(); - xLocalError = pdTRUE; - portEXIT_CRITICAL(); - } - - /* Yield in case cooperative scheduling is being used. */ - #if configUSE_PREEMPTION == 0 - { - taskYIELD(); - } - #endif -} -/*-----------------------------------------------------------*/ - diff --git a/Demo/HCS12_GCC_banked/memory.x b/Demo/HCS12_GCC_banked/memory.x deleted file mode 100644 index 97ff4b6dc..000000000 --- a/Demo/HCS12_GCC_banked/memory.x +++ /dev/null @@ -1,63 +0,0 @@ -/* Flash Memory Banks - For Wytec Dragon12, Technological Arts Adapt9S12DP256 - with DBug12 v4 bootloader - - Author Jefferson L Smith; Robotronics, Inc. - */ - -MEMORY -{ - page0 (rwx) : ORIGIN = 0x0, LENGTH = 256 - - /* RAM */ - data (rwx) : ORIGIN = 0x1000, LENGTH = 12k - - eeprom (rx): ORIGIN = 0x0400, LENGTH = 3k - text (rx) : ORIGIN = 0x4000, LENGTH = 16k - - /* high fixed bank, reserve 0x100 vectors and security. */ - text_h (rx) : ORIGIN = 0xc000, LENGTH = 16k-0x100 - - /* Flash memory banks */ - bank0 (rx) : ORIGIN = 0x0d0000, LENGTH = 16k - bank1 (rx) : ORIGIN = 0x0d4000, LENGTH = 16k - bank2 (rx) : ORIGIN = 0x0d8000, LENGTH = 16k - bank3 (rx) : ORIGIN = 0x0dc000, LENGTH = 16k - bank4 (rx) : ORIGIN = 0x0e0000, LENGTH = 16k - bank5 (rx) : ORIGIN = 0x0e4000, LENGTH = 16k - bank6 (rx) : ORIGIN = 0x0e8000, LENGTH = 16k - bank7 (rx) : ORIGIN = 0x0ec000, LENGTH = 16k - bank8 (rx) : ORIGIN = 0x0f0000, LENGTH = 16k - bank9 (rx) : ORIGIN = 0x0f4000, LENGTH = 16k - bank10 (rx) : ORIGIN = 0x0f8000, LENGTH = 16k - bank11 (rx) : ORIGIN = 0x0fc000, LENGTH = 16k - bank12 (rx) : ORIGIN = 0x100000, LENGTH = 16k - bank13 (rx) : ORIGIN = 0x104000, LENGTH = 16k - - bank14 (rx) : ORIGIN = 0x108000, LENGTH = 16k - bank15 (rx) : ORIGIN = 0x10c000, LENGTH = 16k-0x100 -} -/* Setup the stack on the top of the data memory bank. */ -PROVIDE (_stack = 0x1000+12k); - -/* interrupt/reset vectors*/ -vectors_addr = 0x10ff80; - -SECTIONS -{ - /* PPAGE memory banks */ - - .bank2 : - { - ../Common/Minimal/flash.o(.text .rodata) - *(.bank2) - } > bank2 - - .bank3 : - { - ParTest.o(.text .rodata) - *(.bank3) - } > bank3 - -} - diff --git a/Demo/HCS12_GCC_banked/sci.c b/Demo/HCS12_GCC_banked/sci.c deleted file mode 100644 index d32f7cde4..000000000 --- a/Demo/HCS12_GCC_banked/sci.c +++ /dev/null @@ -1,75 +0,0 @@ -/** - * sci.c controls SCI for GCC/HCS12 version of FreeRTOS Demo - * Parts taken from the CodeWarrior Demo in order to work similar. - * - * Author Jefferson L Smith, Robotronics Inc. - */ - -#include "sci.h" -#include - -//static word SerFlag; /* Flags for serial communication */ - /* Bits: 0 - OverRun error */ - /* 1 - Framing error */ - /* 2 - Parity error */ - /* 3 - Char in RX buffer */ - /* 4 - Full TX buffer */ - /* 5 - Running int from TX */ - /* 6 - Full RX buffer */ - /* 7 - Noise error */ - /* 8 - Idle character */ - /* 9 - Break detected */ - /* 10 - Unused */ -static word PrescaleValue; -//static byte NumMode; /* Number of selected baud mode */ - - -/** - * SCI_SetBaudRateMode - * - * Changes the speed (baud rate). - */ -byte SCI_SetBaudRateMode(byte Mod) -{ - // wired for 24 MHz bus --jeffs - static const word SCI_Presc[4] = {39,78,156,313}; - - if(Mod >= 4) /* Is mode in baud mode list */ - return ERR_VALUE; /* If no then error */ - //NumMode = Mod; /* New baud mode */ - PrescaleValue = SCI_Presc[Mod]; /* Prescaler in high speed mode */ - - /* SCI0CR1: LOOPS=0,SCISWAI=0,RSRC=0,M=0,WAKE=0,ILT=0,PE=0,PT=0 */ - SCICR1 = 0x00; /* Set the SCI configuration */ - /* SCI0SR2: ??=0,??=0,??=0,??=0,??=0,BRK13=0,TXDIR=0,RAF=0 */ - SCISR2 = 0x00; /* Set the Break Character Length and Transmitter pin data direction in Single-wire mode */ - SCISR1; /* Reset interrupt request flags */ - SCIBD = PrescaleValue; /* Set prescaler bits */ - /* SCI0CR2: SCTIE=0,TCIE=0,RIE=1,ILIE=0,TE=1,RE=1,RWU=0,SBK=0 */ - SCICR2 = 0x2c; /* Disable error interrupts */ - - return ERR_OK; /* OK */ -} - -#if 0 //(not used) - -/** - * SCI_Init (bean AsynchroSerial) - * - * This enables SCI. - */ -void SCI_Init(void) -{ - PrescaleValue = 39; /* Precaler in high speed mode */ - - /* SCI0CR1: LOOPS=0,SCISWAI=0,RSRC=0,M=0,WAKE=0,ILT=0,PE=0,PT=0 */ - SCICR1 = 0x00; /* Set the SCI configuration */ - /* SCI0SR2: ??=0,??=0,??=0,??=0,??=0,BRK13=0,TXDIR=0,RAF=0 */ - SCISR2 = 0x00; /* Set the Break Character Length and Transmitter pin data direction in Single-wire mode */ - SCISR1; /* Reset interrupt request flags */ - SCIBD = PrescaleValue; /* Set prescaler bits */ - /* SCI0CR2: SCTIE=0,TCIE=0,RIE=1,ILIE=0,TE=1,RE=1,RWU=0,SBK=0 */ - SCICR2 = 0x2c; /* Disable error interrupts */ -} -#endif - diff --git a/Demo/HCS12_GCC_banked/sci.h b/Demo/HCS12_GCC_banked/sci.h deleted file mode 100644 index 8a039f490..000000000 --- a/Demo/HCS12_GCC_banked/sci.h +++ /dev/null @@ -1,34 +0,0 @@ -/** - * sci.h controls SCI for GCC/HCS12 version of FreeRTOS Demo - * Parts taken from the CodeWarrior Demo in order to work similar. - * - * Author Jefferson L Smith, Robotronics Inc. - */ - -#ifndef __SCI -#define __SCI - -#include "cpu.h" - -#define COM0_Bm_38400baud 0 /* Constant for switch to mode 0 */ -#define COM0_Bm_19200baud 1 /* Constant for switch to mode 1 */ -#define COM0_Bm_9600baud 2 /* Constant for switch to mode 2 */ -#define COM0_Bm_4800baud 3 /* Constant for switch to mode 3 */ - - -/** - * SCI_SetBaudRateMode - * - * Changes the speed (baud rate). - */ -byte SCI_SetBaudRateMode(byte Mod); - - -/** - * SCI_Init (bean AsynchroSerial) - * - * This enables SCI. - */ -void SCI_Init(void); - -#endif /* ifndef __SCI */ diff --git a/Demo/HCS12_GCC_banked/serial.c b/Demo/HCS12_GCC_banked/serial.c deleted file mode 100644 index 93bc3b5d2..000000000 --- a/Demo/HCS12_GCC_banked/serial.c +++ /dev/null @@ -1,150 +0,0 @@ -/* - serial.c for using FreeRTOS - Copyright (C) 2005 Robotronics Inc. -*/ - - -/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER for port 1. - - GCC demo modifications by Jeff Smith, Robotronics Inc. 2005 -*/ - -#include "cpu.h" -#include - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "queue.h" -#include "task.h" - -/* Demo application include files. */ -#include "sci.h" -#include "serial.h" - -/* The queues used to communicate between the task code and the interrupt -service routines. */ -static xQueueHandle xRxedChars; -static xQueueHandle xCharsForTx; - -/* Interrupt identification bits. */ -#define serOVERRUN_INTERRUPT ( '\x08' ) -#define serRX_INTERRUPT ( 0x20 ) -#define serTX_INTERRUPT ( 0x80 ) - -/*-----------------------------------------------------------*/ - - -/* - * Initialise port for interrupt driven communications. - */ -xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) -{ - /* Hardware setup is performed by the Processor Expert generated code. - This function just creates the queues used to communicate between the - interrupt code and the task code - then sets the required baud rate. */ - - xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); - xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); - - SCI_SetBaudRateMode( ( portCHAR ) ulWantedBaud ); - - return NULL; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) -{ - /* Get the next character from the buffer queue. Return false if no characters - are available, or arrive before xBlockTime expires. */ - if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) - { - return pdTRUE; - } - else - { - return pdFALSE; - } -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) -{ - /* Place the character in the queue of characters to be transmitted. */ - if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) - { - return pdFAIL; - } - - /* Turn on the Tx interrupt so the ISR will remove the character from the - queue and send it. This does not need to be in a critical section as - if the interrupt has already removed the character the next interrupt - will simply turn off the Tx interrupt again. */ - SCICR2 |= 0x80; // TIE - - return pdPASS; -} -/*-----------------------------------------------------------*/ - -void vSerialClose( xComPortHandle xPort ) -{ - /* Not supported. */ - //( void ) xPort; -} -/*-----------------------------------------------------------*/ - - -/* - * Interrupt service routine for the serial port. Must be in non-banked - * memory. - */ - -void ATTR_INT ATTR_NEAR vCOM_ISR( void ); - -void vCOM_ISR( void ) -{ -volatile unsigned portCHAR ucByte, ucStatus; -portBASE_TYPE xTaskWokenByPost = pdFALSE, xTaskWokenByTx = pdFALSE; - - /* What caused the interrupt? */ - ucStatus = SCISR1; - - if( ucStatus & serOVERRUN_INTERRUPT ) - { - /* The interrupt was caused by an overrun. Clear the error by reading - the data register. */ - ucByte = SCIDRL; - } - else - if( ucStatus & serRX_INTERRUPT ) - { - /* The interrupt was caused by a character being received. - Read the received byte. */ - ucByte = SCIDRL; - - /* Post the character onto the queue of received characters - noting - whether or not this wakes a task. */ - xTaskWokenByPost = xQueueSendFromISR( xRxedChars, ( void * ) &ucByte, pdFALSE ); - } - - if( ( ucStatus & serTX_INTERRUPT ) && ( SCICR2 & 0x80 ) ) - { - /* The interrupt was caused by a character being transmitted. */ - if( xQueueReceiveFromISR( xCharsForTx, ( void * ) &ucByte, &xTaskWokenByTx ) == pdTRUE ) - { - /* Clear the SCRF bit. */ - SCIDRL = ucByte; - } - else - { - /* Disable transmit interrupt */ - SCICR2 &= ~0x80; // TIE - } - } - - if( ( xTaskWokenByPost ) || ( xTaskWokenByTx ) ) - { - portYIELD(); - } - -} - diff --git a/Demo/HCS12_GCC_banked/startup.c b/Demo/HCS12_GCC_banked/startup.c deleted file mode 100644 index 4ab8acf35..000000000 --- a/Demo/HCS12_GCC_banked/startup.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/* - * startup.c - * Author Jefferson L Smith, Robotronics Inc. - * - * __premain() is the startup code to init hardware and ram to execute the - * C application. - * - */ - -#include -#include "cpu.h" - -void ATTR_NEAR __premain (void); - -void -__premain (void) -{ - // in case special mode enabled, avoid conflict on PORTE - PEAR |= NECLK; - // bgnd mode stops COP and RTI clocks - COPCTL = RSBCK; - // stops TCNT counter when debugging stops - TSCR1 |= (1<<5); // TFRZ - - // PLL - CLKSEL = 0; // disable PLL to configure - // xtal 16MHz, bus 24MHz - SYNR = 3 - 1; - REFDV = 2 - 1; - while (!(CRGFLG & 0x08)) // wait for PLL LOCK - cop_optional_reset(); - CLKSEL |= 0x80; // use PLL - - // init switch inputs - PERH = 0xff; // pullups - - // outputs -#if PORT_LED==M6811_PORTB //PORTB - DDRB = 0xff; // init LED -#elif PORT_LED==M6811_PORTA //PORTA - DDRA = 0xff; -#elif PORT_LED==M6811_PTT //PTT - DDRT = 0xff; -#elif PORT_LED==M6811_PTM //PTM - DDRM = 0xff; -#elif PORT_LED==M6811_PTP //PTP - DDRP = 0xff; -#elif PORT_LED==M6811_PTH //PTH - DDRH = 0xff; -#endif - -} - diff --git a/Demo/HCS12_GCC_banked/sys/interrupts.h b/Demo/HCS12_GCC_banked/sys/interrupts.h deleted file mode 100644 index b783e4b95..000000000 --- a/Demo/HCS12_GCC_banked/sys/interrupts.h +++ /dev/null @@ -1,73 +0,0 @@ -/* Interrupt Vectors - Copyright (C) 2000, 2002, 2003 Free Software Foundation, Inc. - Written by Stephane Carrez (stcarrez@nerim.fr) - -This file is free software; you can redistribute it and/or modify it -under the terms of the GNU General Public License as published by the -Free Software Foundation; either version 2, or (at your option) any -later version. - -In addition to the permissions in the GNU General Public License, the -Free Software Foundation gives you unlimited permission to link the -compiled version of this file with other programs, and to distribute -those programs without any restriction coming from the use of this -file. (The General Public License restrictions do apply in other -respects; for example, they cover modification of the file, and -distribution when not linked into another program.) - -This file is distributed in the hope that it will be useful, but -WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -#ifndef _SYS_INTERRUPTS_H -#define _SYS_INTERRUPTS_H - -#include - -#ifdef mc6811 -//# include -#endif - -#ifdef mc68hcs12 -# include -#elif defined(mc6812) -//# include -#endif - -/*! Install an interrupt handler. - - Install the interrupt handler for an exception. The handler - is installed for \b bootstrap mode and also for \b normal operating - mode. - - @param id the interrupt number to be installed - @param handler the interrupt handler entry point -*/ -extern void -set_interrupt_handler (interrupt_vector_id id, interrupt_t handler); - -/*! Default and fatal interrupt handler. - - This function is an interrupt handler intended to be used to - handle all interrupt not used by a program. Since it is an - error to have an interrupt when it is not handled, the default - behavior is to print a message and stop. */ -extern void __attribute__((interrupt, noreturn)) -fatal_interrupt (void); - -#include - -/*! Entry point of any program. - - This function should never be called by itself. It represents the - entry point of any program. It is intended to be used in an - interrupt table to specify the function to jump to after reset. */ -extern void _start (void); - -#endif diff --git a/Demo/HCS12_GCC_banked/sys/param.h b/Demo/HCS12_GCC_banked/sys/param.h deleted file mode 100644 index 8dbf1a3a2..000000000 --- a/Demo/HCS12_GCC_banked/sys/param.h +++ /dev/null @@ -1,56 +0,0 @@ -/* param.h - Board specific parameters - Copyright (C) 2000, 2002, 2003 Free Software Foundation, Inc. - Written by Stephane Carrez (stcarrez@nerim.fr) - -This file is free software; you can redistribute it and/or modify it -under the terms of the GNU General Public License as published by the -Free Software Foundation; either version 2, or (at your option) any -later version. - -In addition to the permissions in the GNU General Public License, the -Free Software Foundation gives you unlimited permission to link the -compiled version of this file with other programs, and to distribute -those programs without any restriction coming from the use of this -file. (The General Public License restrictions do apply in other -respects; for example, they cover modification of the file, and -distribution when not linked into another program.) - -This file is distributed in the hope that it will be useful, but -WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -#ifndef _SYS_PARAM_H -#define _SYS_PARAM_H - -/*! Attribute unused. - Use this attribute to indicate that a parameter, a variable or a - static function is not used. The compiler will not warn about the - unused variable. */ -#define ATTRIBUTE_UNUSED __attribute__((unused)) - -/*! Attribute page0. - Use this attribute to put a global or static variable in page0. */ -#define PAGE0_ATTRIBUTE __attribute__((section(".page0"))) - -#ifdef mc6811 -//# include -#endif - -#ifdef mc68hcs12 -# include -#elif defined(mc6812) -//# include -#endif - -#include - -#define GNU_LINKER_WARNING(SYMBOL, MSG) \ - asm (".section .gnu.warning." SYMBOL "\n\t.string \"" MSG "\"\n\t.previous"); - -#endif diff --git a/Demo/HCS12_GCC_banked/sys/ports.h b/Demo/HCS12_GCC_banked/sys/ports.h deleted file mode 100644 index 934c2f399..000000000 --- a/Demo/HCS12_GCC_banked/sys/ports.h +++ /dev/null @@ -1,69 +0,0 @@ -/* sys/ports.h -- Definition of system ports - Copyright 2000, 2001, 2002 Free Software Foundation, Inc. - Written by Stephane Carrez (stcarrez@worldnet.fr) - -This file is part of GEL. - -GEL is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GEL is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GEL; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -#ifndef _SYS_PORTS_H -#define _SYS_PORTS_H - -#ifdef __cplusplus -extern "C" { -#endif - - extern unsigned short get_timer_counter (void); - extern void set_timer_counter (unsigned short); - extern unsigned short get_input_capture_1 (void); - extern void set_input_capture_1 (unsigned short); - extern unsigned short get_input_capture_2 (void); - extern void set_input_capture_2 (unsigned short); - extern unsigned short get_input_capture_3 (void); - extern void set_input_capture_3 (unsigned short); - extern unsigned short get_output_compare_1 (void); - extern void set_output_compare_1 (unsigned short); - extern unsigned short get_output_compare_2 (void); - extern void set_output_compare_2 (unsigned short); - extern unsigned short get_output_compare_3 (void); - extern void set_output_compare_3 (unsigned short); - extern unsigned short get_output_compare_4 (void); - extern void set_output_compare_4 (unsigned short); - extern unsigned short get_output_compare_5 (void); - extern void set_output_compare_5 (unsigned short); - extern void set_bus_expanded (void); - extern void set_bus_single_chip (void); - extern void cop_reset (void); - extern void cop_optional_reset (void); - extern void timer_acknowledge (void); - extern void timer_initialize_rate (unsigned char); - -#ifdef mc6811 -//# include -#endif - -#ifdef mc68hcs12 -# include -#elif defined(mc6812) -//# include -#endif - -#ifdef __cplusplus -}; -#endif - -#endif /* _SYS_PORTS_H */ - diff --git a/Demo/HCS12_GCC_banked/sys/ports_def.h b/Demo/HCS12_GCC_banked/sys/ports_def.h deleted file mode 100644 index 8d2c74930..000000000 --- a/Demo/HCS12_GCC_banked/sys/ports_def.h +++ /dev/null @@ -1,36 +0,0 @@ -/* sys/ports_def.h -- Definition of system ports - Copyright 2000 Free Software Foundation, Inc. - Written by Stephane Carrez (stcarrez@worldnet.fr) - -This file is part of GEL. - -GEL is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GEL is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GEL; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -#ifndef _SYS_PORTS_DEF_H -#define _SYS_PORTS_DEF_H - -#ifdef mc6811 -//# include -#endif - -#ifdef mc68hcs12 -# include -#elif defined(mc6812) -//# include -#endif - -#endif /* _SYS_PORTS_DEF_H */ - diff --git a/Demo/HCS12_GCC_banked/sys/sio.h b/Demo/HCS12_GCC_banked/sys/sio.h deleted file mode 100644 index a28fe94fe..000000000 --- a/Demo/HCS12_GCC_banked/sys/sio.h +++ /dev/null @@ -1,80 +0,0 @@ -/* sys/sio.h -- Utility methods to read/write the SIO - Copyright 2000 Free Software Foundation, Inc. - Written by Stephane Carrez (stcarrez@worldnet.fr) - -This file is part of GEL. - -GEL is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GEL is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GEL; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -#ifndef _SYS_SIO_H -#define _SYS_SIO_H - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -extern void serial_init (void); - -/* Return != 0 if there is something to read on the serial line. */ -extern unsigned char serial_receive_pending (void); - -/* Wait until the SIO has finished to send the character. */ -extern void serial_flush (void); - -/* Return != 0 if serial port is ready to send another char. */ -extern unsigned char serial_send_ready (void); - -/* Send the character on the serial line. */ -extern void serial_send (char c); - -/* Wait for a character on the serial line and return it. */ -extern unsigned char serial_recv (void); - -/** Write the string on the serial line. - - @param msg null terminated string to write. - - @see serial_init, serial_send -*/ -extern void serial_print (const char *msg); - -/** Wait for a string from serial line. - - @param msg buffer that will hold the string. - - @see serial_init, serial_recv -*/ -extern void serial_getline (char *buf); - -#ifdef mc6811 -//# include -#endif - -#ifdef mc68hcs12 -# include -#elif defined(mc6812) -//# include -#endif - - -#ifdef __cplusplus -}; -#endif -#endif /* _SYS_SIO_H */ - diff --git a/Demo/HCS12_GCC_banked/vectors.c b/Demo/HCS12_GCC_banked/vectors.c deleted file mode 100644 index 2375a73b6..000000000 --- a/Demo/HCS12_GCC_banked/vectors.c +++ /dev/null @@ -1,115 +0,0 @@ -/* modrx.c -- wireless controller receiver for robots - Copyright 2004 Robotronics, Inc. - Author Jefferson Smith - - This file is part of the Modular Robot Design. -*/ - -#include "cpu.h" -#include -#include - -void fatal_interrupt () -{ - /* Infinite loop for debugging - Returning would not help as it's necessary to clear the interrupt flag. - */ - for (;;) cop_optional_reset(); -} - -#ifdef USE_INTERRUPT_TABLE - -/* NOTE: these ISR must be in non-banked memory (near) */ - -/* Manual context switch function. This is the SWI ISR. */ -void ATTR_INT ATTR_NEAR vPortYield( void ); - -/* Tick context switch function. This is the timer ISR. */ -void ATTR_INT ATTR_NEAR vPortTickInterrupt( void ); - -void ATTR_INT ATTR_NEAR vCOM_ISR( void ); - -/* Interrupt vectors table. - - Note: the `XXX_handler: foo' notation is a GNU extension which is - used here to ensure correct association of the handler in the struct. - This is why the order of handlers declared below does not follow - the MCU order. */ -const struct interrupt_vectors __attribute__((section(".vectors"))) vectors = -{ - pwm_shutdown_handler: fatal_interrupt, - ptpif_handler: fatal_interrupt, - can4_tx_handler: fatal_interrupt, - can4_rx_handler: fatal_interrupt, - can4_err_handler: fatal_interrupt, - can4_wake_handler: fatal_interrupt, - can3_tx_handler: fatal_interrupt, - can3_rx_handler: fatal_interrupt, - can3_err_handler: fatal_interrupt, - can3_wake_handler: fatal_interrupt, - can2_tx_handler: fatal_interrupt, - can2_rx_handler: fatal_interrupt, - can2_err_handler: fatal_interrupt, - can2_wake_handler: fatal_interrupt, - can1_tx_handler: fatal_interrupt, - can1_rx_handler: fatal_interrupt, - can1_err_handler: fatal_interrupt, - can1_wake_handler: fatal_interrupt, - can0_tx_handler: fatal_interrupt, - can0_rx_handler: fatal_interrupt, - can0_err_handler: fatal_interrupt, - can0_wake_handler: fatal_interrupt, - flash_handler: fatal_interrupt, - eeprom_handler: fatal_interrupt, - spi2_handler: fatal_interrupt, - spi1_handler: fatal_interrupt, - iic_handler: fatal_interrupt, - bdlc_handler: fatal_interrupt, - selfclk_mode_handler: fatal_interrupt, - pll_lock_handler: fatal_interrupt, - accb_overflow_handler: fatal_interrupt, - mccnt_underflow_handler: fatal_interrupt, - pthif_handler: fatal_interrupt, - ptjif_handler: fatal_interrupt, - atd1_handler: fatal_interrupt, - atd0_handler: fatal_interrupt, - sci1_handler: fatal_interrupt, - sci0_handler: fatal_interrupt, - spi0_handler: fatal_interrupt, - - /** Timer and Accumulator */ - acca_input_handler: fatal_interrupt, - acca_overflow_handler: fatal_interrupt, - timer_overflow_handler: fatal_interrupt, - - /** Input capture / Output compare Timers */ - tc7_handler: fatal_interrupt, - tc6_handler: fatal_interrupt, - tc5_handler: fatal_interrupt, - tc4_handler: fatal_interrupt, - tc3_handler: fatal_interrupt, - tc2_handler: fatal_interrupt, - tc1_handler: fatal_interrupt, - tc0_handler: fatal_interrupt, - - /** External Interrupts */ - rtii_handler: fatal_interrupt, - irq_handler: fatal_interrupt, - xirq_handler: fatal_interrupt, - - illegal_handler: fatal_interrupt, - cop_fail_handler: fatal_interrupt, - cop_clock_handler: fatal_interrupt, - - /** Vectors in use */ - swi_handler: vPortYield, - rtii_handler: vPortTickInterrupt, -#if M6812_DEF_SCI==1 - sci1_handler: vCOM_ISR, -#else - sci0_handler: vCOM_ISR, -#endif - reset_handler: _start -}; -#endif - diff --git a/Demo/MCF5235_GCC/Changelog.txt b/Demo/MCF5235_GCC/Changelog.txt deleted file mode 100644 index 0290fbae0..000000000 --- a/Demo/MCF5235_GCC/Changelog.txt +++ /dev/null @@ -1,4 +0,0 @@ - -2006-08-31 (REL_1_2) Christian Walter : - Notes: Recreated from lwIP port. - diff --git a/Demo/MCF5235_GCC/FreeRTOSConfig.h b/Demo/MCF5235_GCC/FreeRTOSConfig.h deleted file mode 100644 index f88e9f19f..000000000 --- a/Demo/MCF5235_GCC/FreeRTOSConfig.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - FreeRTOS V4.1.0 - Copyright (C) 2003-2006 Richard Barry. - MCF5235 Port - Copyright (C) 2006 Christian Walter. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 25000000 ) -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 7 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 256 ) -#define configMAX_TASK_NAME_LEN ( 16 ) -#define configUSE_TRACE_FACILITY 1 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 1 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 -#define INCLUDE_xTaskGetCurrentTaskHandle 1 - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/MCF5235_GCC/LICENSE_FREESCALE.TXT b/Demo/MCF5235_GCC/LICENSE_FREESCALE.TXT deleted file mode 100644 index 7e58b1174..000000000 --- a/Demo/MCF5235_GCC/LICENSE_FREESCALE.TXT +++ /dev/null @@ -1,35 +0,0 @@ -MCF523x example code - -IMPORTANT. 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This Agreement may only be amended in written form, executed by you and Freescale. - -SEVERABILITY. If any provision of this Agreement is held for any reason to be invalid or unenforceable, then the remaining provisions of this Agreement will be unimpaired and, unless a modification or replacement of the invalid or unenforceable provision is further held to deprive you or Freescale of a material benefit, in which case the Agreement will immediately terminate, the invalid or unenforceable provision will be replaced with a provision that is valid and enforceable and that comes closest to the intention underlying the invalid or unenforceable provision. - -NO WAIVER. The waiver by Freescale of any breach of any provision of this Agreement will not operate or be construed as a waiver of any other or a subsequent breach of the same or a different provision. diff --git a/Demo/MCF5235_GCC/Makefile b/Demo/MCF5235_GCC/Makefile deleted file mode 100644 index 7a2da52f6..000000000 --- a/Demo/MCF5235_GCC/Makefile +++ /dev/null @@ -1,87 +0,0 @@ -# -# FreeRTOS 4.1.0 - MCF5235 Coldfire Port -# -# Copyright (c) 2006 Christian Walter, Vienna 2006. -# -# $Id: Makefile,v 1.1 2006/08/31 22:45:48 wolti Exp $ -# -# --------------------------------------------------------------------------- -BASE = /opt/gcc-m68k/bin -CC = $(BASE)/m68k-elf-gcc -CXX = $(BASE)/m68k-elf-g++ -OBJCOPY = $(BASE)/m68k-elf-objcopy -SIZE = $(BASE)/m68k-elf-size -INSIGHT = $(BASE)/m68k-bdm-elf-insight -BDMFLASH = $(BASE)/bdmflash - -#CFLAGS = -MD -O2 -m528x -Wall -CFLAGS = -MD -gdwarf-2 -g3 -m528x -Wall \ - -D'GCC_MCF5235=1' -D'_GCC_USES_FP=1' \ - -D'__IPSBAR=((vuint8 *) 0x40000000)' -D'FSYS_2=25000000UL' \ - -I. -Iinclude -Iinclude/arch -Ifec \ - -I../../Source/include -I../Common/include - -ASFLAGS = -MD -gdwarf-2 -g3 -m528x -Wa,--register-prefix-optional \ - -Wa,--bitwise-or -Wa,--defsym,IPSBAR=0x40000000 -LDSCRIPT = m5235-ram.ld -LDFLAGS = -nostartfiles -m528x -Wl,--script=$(LDSCRIPT) - -TGT = demo -OTHER_CSRC = -OTHER_ASRC = $(addprefix system/, crt0.S vector.S) -CSRC = demo.c \ - $(addprefix system/, init.c newlib.c serial.c) \ - $(addprefix ../Common/Minimal/, PollQ.c integer.c flop.c BlockQ.c semtest.c dynamic.c ) \ - $(addprefix ../../Source/, tasks.c queue.c list.c) \ - $(addprefix ../../Source/portable/MemMang/, heap_3.c) \ - $(addprefix ../../Source/portable/GCC/MCF5235/, port.c) - -ASRC = $(addprefix system/, mcf5xxx.S ) -OBJS = $(CSRC:.c=.o) $(ASRC:.S=.o) -NOLINK_OBJS = $(OTHER_CSRC:.c=.o) $(OTHER_ASRC:.S=.o) -DEPS = $(OBJS:.o=.d) $(NOLINK_OBJS:.o=.d) -BIN = $(TGT).elf - -.PHONY: clean all - -all: $(BIN) - -flash-programm: $(TGT).elf - $(OBJCOPY) -O binary $(TGT).elf $(TGT).bin - @BIN_SIZE=`du -b $(TGT).bin | awk '//{ print $$1; }'`; \ - echo "programming $(TGT).bin with size $$BIN_SIZE to flash..."; \ - $(BDMFLASH) /dev/bdmcf20 0x00000000 1 2 write $(TGT).bin 0 - -flash-verify: - @BIN_SIZE=`du -b $(TGT).bin | awk '//{ print $$1; }'`; \ - echo "loading $$BIN_SIZE bytes from target into $(TGT).vrf..."; \ - $(BDMFLASH) /dev/bdmcf20 0x00000000 1 2 read $(TGT).vrf 0 $$BIN_SIZE - -flash-erase: - $(BDMFLASH) /dev/bdmcf20 0x00000000 1 2 erase - -debug: - $(INSIGHT) --command=m5235.gdb --se=$(TGT).elf - -$(BIN): $(OBJS) $(NOLINK_OBJS) - $(CC) $(LDFLAGS) -Wl,-Map=$(TGT).map $(OBJS) $(LDLIBS) -o $@ - -clean: - rm -f $(DEPS) - rm -f $(OBJS) $(NOLINK_OBJS) - rm -f $(BIN) $(TGT).map - -# --------------------------------------------------------------------------- -# rules for code generation -# --------------------------------------------------------------------------- -%.o: %.c - $(CC) $(CFLAGS) -o $@ -c $< - -%.o: %.S - $(CC) $(ASFLAGS) -o $@ -c $< - -# --------------------------------------------------------------------------- -# # compiler generated dependencies -# --------------------------------------------------------------------------- --include $(DEPS) - diff --git a/Demo/MCF5235_GCC/demo.c b/Demo/MCF5235_GCC/demo.c deleted file mode 100644 index 220964d1f..000000000 --- a/Demo/MCF5235_GCC/demo.c +++ /dev/null @@ -1,298 +0,0 @@ -/* - FreeRTOS V4.1.0 - Copyright (C) 2003-2006 Richard Barry. - MCF5235 Port - Copyright (C) 2006 Christian Walter. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* ------------------------ System includes ------------------------------- */ -#include -#include - -/* ------------------------ FreeRTOS includes ----------------------------- */ -#include "FreeRTOS.h" -#include "task.h" - -/* ------------------------ Demo application includes --------------------- */ -#include "partest.h" -#include "flash.h" -#include "integer.h" -#include "PollQ.h" -#include "comtest2.h" -#include "semtest.h" -#include "flop.h" -#include "dynamic.h" -#include "BlockQ.h" -#include "serial.h" - -/* ------------------------ Defines --------------------------------------- */ -/* Constants for the ComTest tasks. */ -#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 38400 ) -#define mainCOM_TEST_LED ( -1 ) - -/* Priorities for the demo application tasks. */ -#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) - -/* Interval in which tasks are checked. */ -#define mainCHECK_PERIOD ( ( portTickType ) 2000 / portTICK_RATE_MS ) - -/* Constants used by the vMemCheckTask() task. */ -#define mainCOUNT_INITIAL_VALUE ( ( unsigned portLONG ) 0 ) -#define mainNO_TASK ( 0 ) - -/* The size of the memory blocks allocated by the vMemCheckTask() task. */ -#define mainMEM_CHECK_SIZE_1 ( ( size_t ) 51 ) -#define mainMEM_CHECK_SIZE_2 ( ( size_t ) 52 ) -#define mainMEM_CHECK_SIZE_3 ( ( size_t ) 151 ) - -/* ------------------------ Static variables ------------------------------ */ -xComPortHandle xSTDComPort = NULL; - -/* ------------------------ Static functions ------------------------------ */ -static portTASK_FUNCTION( vErrorChecks, pvParameters ); -static portLONG prvCheckOtherTasksAreStillRunning( unsigned portLONG - ulMemCheckTaskCount ); -static portTASK_FUNCTION( vMemCheckTask, pvParameters ); - -/* ------------------------ Implementation -------------------------------- */ -int -main( int argc, char *argv[] ) -{ - asm volatile ( "move.w #0x2000, %sr\n\t" ); - - xSTDComPort = xSerialPortInitMinimal( 38400, 8 ); - - /* Start the demo/test application tasks. */ - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartMathTasks( tskIDLE_PRIORITY ); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartDynamicPriorityTasks( ); - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - - /* Start the check task - which is defined in this file. */ - xTaskCreate( vErrorChecks, ( signed portCHAR * )"Check", 512, NULL, - mainCHECK_TASK_PRIORITY, NULL ); - - /* Now all the tasks have been started - start the scheduler. */ - vTaskStartScheduler( ); - - /* Should never get here! */ - return 0; -} - - - -static -portTASK_FUNCTION( vErrorChecks, pvParameters ) -{ - unsigned portLONG ulMemCheckTaskRunningCount; - xTaskHandle xCreatedTask; - - /* The parameters are not used in this function. */ - ( void )pvParameters; - - xSerialPortInitMinimal( mainCOM_TEST_BAUD_RATE, 8 ); - - for( ;; ) - { - ulMemCheckTaskRunningCount = mainCOUNT_INITIAL_VALUE; - xCreatedTask = mainNO_TASK; - - if( xTaskCreate - ( vMemCheckTask, ( signed portCHAR * )"MEM_CHECK", - configMINIMAL_STACK_SIZE, ( void * )&ulMemCheckTaskRunningCount, - tskIDLE_PRIORITY, &xCreatedTask ) != pdPASS ) - { - xSerialPutChar( xSTDComPort, 'E', portMAX_DELAY ); - } - - /* Delay until it is time to execute again. */ - vTaskDelay( mainCHECK_PERIOD ); - - /* Delete the dynamically created task. */ - if( xCreatedTask != mainNO_TASK ) - { - vTaskDelete( xCreatedTask ); - } - - if( prvCheckOtherTasksAreStillRunning( ulMemCheckTaskRunningCount ) != - pdPASS ) - { - xSerialPutChar( xSTDComPort, 'E', portMAX_DELAY ); - } - else - { - xSerialPutChar( xSTDComPort, '.', portMAX_DELAY ); - } - } -} - -static portLONG -prvCheckOtherTasksAreStillRunning( unsigned portLONG ulMemCheckTaskCount ) -{ - portLONG lReturn = ( portLONG ) pdPASS; - - /* Check all the demo tasks (other than the flash tasks) to ensure - * that they are all still running, and that none of them have detected - * an error. - */ - - if( xAreIntegerMathsTaskStillRunning( ) != pdTRUE ) - { - lReturn = ( portLONG ) pdFAIL; - } - - if( xArePollingQueuesStillRunning( ) != pdTRUE ) - { - lReturn = ( portLONG ) pdFAIL; - } - - if( xAreMathsTaskStillRunning( ) != pdTRUE ) - { - lReturn = ( portLONG ) pdFAIL; - } - - if( xAreSemaphoreTasksStillRunning( ) != pdTRUE ) - { - lReturn = ( portLONG ) pdFAIL; - } - - if( xAreDynamicPriorityTasksStillRunning( ) != pdTRUE ) - { - lReturn = ( portLONG ) pdFAIL; - } - - if( xAreBlockingQueuesStillRunning( ) != pdTRUE ) - { - lReturn = ( portLONG ) pdFAIL; - } - if( ulMemCheckTaskCount == mainCOUNT_INITIAL_VALUE ) - { - // The vMemCheckTask did not increment the counter - it must - // have failed. - lReturn = ( portLONG ) pdFAIL; - } - return lReturn; -} - -static void -vMemCheckTask( void *pvParameters ) -{ - unsigned portLONG *pulMemCheckTaskRunningCounter; - void *pvMem1, *pvMem2, *pvMem3; - static portLONG lErrorOccurred = pdFALSE; - - /* This task is dynamically created then deleted during each cycle of the - vErrorChecks task to check the operation of the memory allocator. Each time - the task is created memory is allocated for the stack and TCB. Each time - the task is deleted this memory is returned to the heap. This task itself - exercises the allocator by allocating and freeing blocks. - - The task executes at the idle priority so does not require a delay. - - pulMemCheckTaskRunningCounter is incremented each cycle to indicate to the - vErrorChecks() task that this task is still executing without error. */ - - pulMemCheckTaskRunningCounter = ( unsigned portLONG * )pvParameters; - - for( ;; ) - { - if( lErrorOccurred == pdFALSE ) - { - /* We have never seen an error so increment the counter. */ - ( *pulMemCheckTaskRunningCounter )++; - } - - /* Allocate some memory - just to give the allocator some extra - exercise. This has to be in a critical section to ensure the - task does not get deleted while it has memory allocated. */ - vTaskSuspendAll( ); - { - pvMem1 = pvPortMalloc( mainMEM_CHECK_SIZE_1 ); - if( pvMem1 == NULL ) - { - lErrorOccurred = pdTRUE; - } - else - { - memset( pvMem1, 0xaa, mainMEM_CHECK_SIZE_1 ); - vPortFree( pvMem1 ); - } - } - xTaskResumeAll( ); - - /* Again - with a different size block. */ - vTaskSuspendAll( ); - { - pvMem2 = pvPortMalloc( mainMEM_CHECK_SIZE_2 ); - if( pvMem2 == NULL ) - { - lErrorOccurred = pdTRUE; - } - else - { - memset( pvMem2, 0xaa, mainMEM_CHECK_SIZE_2 ); - vPortFree( pvMem2 ); - } - } - xTaskResumeAll( ); - - /* Again - with a different size block. */ - vTaskSuspendAll( ); - { - pvMem3 = pvPortMalloc( mainMEM_CHECK_SIZE_3 ); - if( pvMem3 == NULL ) - { - lErrorOccurred = pdTRUE; - } - else - { - memset( pvMem3, 0xaa, mainMEM_CHECK_SIZE_3 ); - vPortFree( pvMem3 ); - } - } - xTaskResumeAll( ); - } -} - -void -vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) -{ -} - -void -vParTestToggleLED( unsigned portBASE_TYPE uxLED ) -{ -} diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x.h b/Demo/MCF5235_GCC/include/arch/mcf523x.h deleted file mode 100644 index 4b7761fd5..000000000 --- a/Demo/MCF5235_GCC/include/arch/mcf523x.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * These files are taken from the MCF523X source code example package - * which is available on the Freescale website. Freescale explicitly - * grants the redistribution and modification of these source files. - * The complete licensing information is available in the file - * LICENSE_FREESCALE.TXT. - * - * File: mcf523x.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_H__ -#define __MCF523X_H__ - -/*********************************************************************/ - -#include "mcf523x/mcf523x_fec.h" -#include "mcf523x/mcf523x_rng.h" -#include "mcf523x/mcf523x_fmpll.h" -#include "mcf523x/mcf523x_cs.h" -#include "mcf523x/mcf523x_intc0.h" -#include "mcf523x/mcf523x_intc1.h" -#include "mcf523x/mcf523x_sdramc.h" -#include "mcf523x/mcf523x_sram.h" -#include "mcf523x/mcf523x_uart.h" -#include "mcf523x/mcf523x_timer.h" -#include "mcf523x/mcf523x_qspi.h" -#include "mcf523x/mcf523x_eport.h" -#include "mcf523x/mcf523x_i2c.h" -#include "mcf523x/mcf523x_scm.h" -#include "mcf523x/mcf523x_pit.h" -#include "mcf523x/mcf523x_can.h" -#include "mcf523x/mcf523x_wtm.h" -#include "mcf523x/mcf523x_gpio.h" -#include "mcf523x/mcf523x_mdha.h" -#include "mcf523x/mcf523x_ccm.h" -#include "mcf523x/mcf523x_rcm.h" -#include "mcf523x/mcf523x_etpu.h" - - -/********************************************************************/ - -#endif /* __MCF523X_H__ */ diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_can.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_can.h deleted file mode 100644 index 7aaa34496..000000000 --- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_can.h +++ /dev/null @@ -1,325 +0,0 @@ -/* - * These files are taken from the MCF523X source code example package - * which is available on the Freescale website. Freescale explicitly - * grants the redistribution and modification of these source files. - * The complete licensing information is available in the file - * LICENSE_FREESCALE.TXT. - * - * File: mcf523x_can.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_CAN_H__ -#define __MCF523X_CAN_H__ - -/********************************************************************* -* -* FlexCAN Module (CAN) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_CAN_CANMCR0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0000])) -#define MCF_CAN_CANCTRL0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0004])) -#define MCF_CAN_TIMER0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0008])) -#define MCF_CAN_RXGMASK0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0010])) -#define MCF_CAN_RX14MASK0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0014])) -#define MCF_CAN_RX15MASK0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0018])) -#define MCF_CAN_ERRCNT0 (*(vuint32*)(void*)(&__IPSBAR[0x1C001C])) -#define MCF_CAN_ERRSTAT0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0020])) -#define MCF_CAN_IMASK0 (*(vuint16*)(void*)(&__IPSBAR[0x1C002A])) -#define MCF_CAN_IFLAG0 (*(vuint16*)(void*)(&__IPSBAR[0x1C0032])) -#define MCF_CAN_CANMCR1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0000])) -#define MCF_CAN_CANCTRL1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0004])) -#define MCF_CAN_TIMER1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0008])) -#define MCF_CAN_RXGMASK1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0010])) -#define MCF_CAN_RX14MASK1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0014])) -#define MCF_CAN_RX15MASK1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0018])) -#define MCF_CAN_ERRCNT1 (*(vuint32*)(void*)(&__IPSBAR[0x1F001C])) -#define MCF_CAN_ERRSTAT1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0020])) -#define MCF_CAN_IMASK1 (*(vuint16*)(void*)(&__IPSBAR[0x1F002A])) -#define MCF_CAN_IFLAG1 (*(vuint16*)(void*)(&__IPSBAR[0x1F0032])) -#define MCF_CAN_CANMCR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0000+((x)*0x30000)])) -#define MCF_CAN_CANCTRL(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0004+((x)*0x30000)])) -#define MCF_CAN_TIMER(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0008+((x)*0x30000)])) -#define MCF_CAN_RXGMASK(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0010+((x)*0x30000)])) -#define MCF_CAN_RX14MASK(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0014+((x)*0x30000)])) -#define MCF_CAN_RX15MASK(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0018+((x)*0x30000)])) -#define MCF_CAN_ERRCNT(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C001C+((x)*0x30000)])) -#define MCF_CAN_ERRSTAT(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0020+((x)*0x30000)])) -#define MCF_CAN_IMASK(x) (*(vuint16*)(void*)(&__IPSBAR[0x1C002A+((x)*0x30000)])) -#define MCF_CAN_IFLAG(x) (*(vuint16*)(void*)(&__IPSBAR[0x1C0032+((x)*0x30000)])) - -#define MCF_CAN_MBUF0_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0080+((x)*0x30000)])) -#define MCF_CAN_MBUF0_TMSTP(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0082+((x)*0x30000)])) -#define MCF_CAN_MBUF0_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0084+((x)*0x30000)])) -#define MCF_CAN_MBUF0_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0088+((x)*0x30000)])) -#define MCF_CAN_MBUF0_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0089+((x)*0x30000)])) -#define MCF_CAN_MBUF0_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008A+((x)*0x30000)])) -#define MCF_CAN_MBUF0_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008B+((x)*0x30000)])) -#define MCF_CAN_MBUF0_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008C+((x)*0x30000)])) -#define MCF_CAN_MBUF0_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008D+((x)*0x30000)])) -#define MCF_CAN_MBUF0_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008E+((x)*0x30000)])) -#define MCF_CAN_MBUF0_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008F+((x)*0x30000)])) -#define MCF_CAN_MBUF1_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0090+((x)*0x30000)])) -#define MCF_CAN_MBUF1_TMSTP(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0092+((x)*0x30000)])) -#define MCF_CAN_MBUF1_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0094+((x)*0x30000)])) -#define MCF_CAN_MBUF1_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0098+((x)*0x30000)])) -#define MCF_CAN_MBUF1_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0099+((x)*0x30000)])) -#define MCF_CAN_MBUF1_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009A+((x)*0x30000)])) -#define MCF_CAN_MBUF1_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009B+((x)*0x30000)])) -#define MCF_CAN_MBUF1_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009C+((x)*0x30000)])) -#define MCF_CAN_MBUF1_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009D+((x)*0x30000)])) -#define MCF_CAN_MBUF1_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009E+((x)*0x30000)])) -#define MCF_CAN_MBUF1_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009F+((x)*0x30000)])) -#define MCF_CAN_MBUF2_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00A0+((x)*0x30000)])) -#define MCF_CAN_MBUF2_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00A4+((x)*0x30000)])) -#define MCF_CAN_MBUF2_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00A8+((x)*0x30000)])) -#define MCF_CAN_MBUF2_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00A9+((x)*0x30000)])) -#define MCF_CAN_MBUF2_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AA+((x)*0x30000)])) -#define MCF_CAN_MBUF2_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AB+((x)*0x30000)])) -#define MCF_CAN_MBUF2_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AC+((x)*0x30000)])) -#define MCF_CAN_MBUF2_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AD+((x)*0x30000)])) -#define MCF_CAN_MBUF2_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AE+((x)*0x30000)])) -#define MCF_CAN_MBUF2_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AF+((x)*0x30000)])) -#define MCF_CAN_MBUF3_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00B0+((x)*0x30000)])) -#define MCF_CAN_MBUF3_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00B4+((x)*0x30000)])) -#define MCF_CAN_MBUF3_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00B8+((x)*0x30000)])) -#define MCF_CAN_MBUF3_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00B9+((x)*0x30000)])) -#define MCF_CAN_MBUF3_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BA+((x)*0x30000)])) -#define MCF_CAN_MBUF3_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BB+((x)*0x30000)])) -#define MCF_CAN_MBUF3_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BC+((x)*0x30000)])) -#define MCF_CAN_MBUF3_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BD+((x)*0x30000)])) -#define MCF_CAN_MBUF3_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BE+((x)*0x30000)])) -#define MCF_CAN_MBUF3_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BF+((x)*0x30000)])) -#define MCF_CAN_MBUF4_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00C0+((x)*0x30000)])) -#define MCF_CAN_MBUF4_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00C4+((x)*0x30000)])) -#define MCF_CAN_MBUF4_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00C8+((x)*0x30000)])) -#define MCF_CAN_MBUF4_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00C9+((x)*0x30000)])) -#define MCF_CAN_MBUF4_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CA+((x)*0x30000)])) -#define MCF_CAN_MBUF4_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CB+((x)*0x30000)])) -#define MCF_CAN_MBUF4_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CC+((x)*0x30000)])) -#define MCF_CAN_MBUF4_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CD+((x)*0x30000)])) -#define MCF_CAN_MBUF4_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CE+((x)*0x30000)])) -#define MCF_CAN_MBUF4_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CF+((x)*0x30000)])) -#define MCF_CAN_MBUF5_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00D0+((x)*0x30000)])) -#define MCF_CAN_MBUF5_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00D4+((x)*0x30000)])) -#define MCF_CAN_MBUF5_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00D8+((x)*0x30000)])) -#define MCF_CAN_MBUF5_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00D9+((x)*0x30000)])) -#define MCF_CAN_MBUF5_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DA+((x)*0x30000)])) -#define MCF_CAN_MBUF5_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DB+((x)*0x30000)])) -#define MCF_CAN_MBUF5_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DC+((x)*0x30000)])) -#define MCF_CAN_MBUF5_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DD+((x)*0x30000)])) -#define MCF_CAN_MBUF5_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DE+((x)*0x30000)])) -#define MCF_CAN_MBUF5_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DF+((x)*0x30000)])) -#define MCF_CAN_MBUF6_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00E0+((x)*0x30000)])) -#define MCF_CAN_MBUF6_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00E4+((x)*0x30000)])) -#define MCF_CAN_MBUF6_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00E8+((x)*0x30000)])) -#define MCF_CAN_MBUF6_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00E9+((x)*0x30000)])) -#define MCF_CAN_MBUF6_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EA+((x)*0x30000)])) -#define MCF_CAN_MBUF6_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EB+((x)*0x30000)])) -#define MCF_CAN_MBUF6_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EC+((x)*0x30000)])) -#define MCF_CAN_MBUF6_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00ED+((x)*0x30000)])) -#define MCF_CAN_MBUF6_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EE+((x)*0x30000)])) -#define MCF_CAN_MBUF6_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EF+((x)*0x30000)])) -#define MCF_CAN_MBUF7_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00F0+((x)*0x30000)])) -#define MCF_CAN_MBUF7_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00F4+((x)*0x30000)])) -#define MCF_CAN_MBUF7_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00F8+((x)*0x30000)])) -#define MCF_CAN_MBUF7_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00F9+((x)*0x30000)])) -#define MCF_CAN_MBUF7_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FA+((x)*0x30000)])) -#define MCF_CAN_MBUF7_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FB+((x)*0x30000)])) -#define MCF_CAN_MBUF7_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FC+((x)*0x30000)])) -#define MCF_CAN_MBUF7_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FD+((x)*0x30000)])) -#define MCF_CAN_MBUF7_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FE+((x)*0x30000)])) -#define MCF_CAN_MBUF7_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FF+((x)*0x30000)])) -#define MCF_CAN_MBUF8_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0100+((x)*0x30000)])) -#define MCF_CAN_MBUF8_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0104+((x)*0x30000)])) -#define MCF_CAN_MBUF8_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0108+((x)*0x30000)])) -#define MCF_CAN_MBUF8_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0109+((x)*0x30000)])) -#define MCF_CAN_MBUF8_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010A+((x)*0x30000)])) -#define MCF_CAN_MBUF8_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010B+((x)*0x30000)])) -#define MCF_CAN_MBUF8_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010C+((x)*0x30000)])) -#define MCF_CAN_MBUF8_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010D+((x)*0x30000)])) -#define MCF_CAN_MBUF8_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010E+((x)*0x30000)])) -#define MCF_CAN_MBUF8_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010F+((x)*0x30000)])) -#define MCF_CAN_MBUF9_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0100+((x)*0x30000)])) -#define MCF_CAN_MBUF9_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0114+((x)*0x30000)])) -#define MCF_CAN_MBUF9_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0118+((x)*0x30000)])) -#define MCF_CAN_MBUF9_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0119+((x)*0x30000)])) -#define MCF_CAN_MBUF9_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011A+((x)*0x30000)])) -#define MCF_CAN_MBUF9_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011B+((x)*0x30000)])) -#define MCF_CAN_MBUF9_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011C+((x)*0x30000)])) -#define MCF_CAN_MBUF9_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011D+((x)*0x30000)])) -#define MCF_CAN_MBUF9_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011E+((x)*0x30000)])) -#define MCF_CAN_MBUF9_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011F+((x)*0x30000)])) -#define MCF_CAN_MBUF10_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0120+((x)*0x30000)])) -#define MCF_CAN_MBUF10_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0124+((x)*0x30000)])) -#define MCF_CAN_MBUF10_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0128+((x)*0x30000)])) -#define MCF_CAN_MBUF10_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0129+((x)*0x30000)])) -#define MCF_CAN_MBUF10_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012A+((x)*0x30000)])) -#define MCF_CAN_MBUF10_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012B+((x)*0x30000)])) -#define MCF_CAN_MBUF10_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012C+((x)*0x30000)])) -#define MCF_CAN_MBUF10_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012D+((x)*0x30000)])) -#define MCF_CAN_MBUF10_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012E+((x)*0x30000)])) -#define MCF_CAN_MBUF10_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012F+((x)*0x30000)])) -#define MCF_CAN_MBUF11_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0130+((x)*0x30000)])) -#define MCF_CAN_MBUF11_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0134+((x)*0x30000)])) -#define MCF_CAN_MBUF11_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0138+((x)*0x30000)])) -#define MCF_CAN_MBUF11_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0139+((x)*0x30000)])) -#define MCF_CAN_MBUF11_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013A+((x)*0x30000)])) -#define MCF_CAN_MBUF11_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013B+((x)*0x30000)])) -#define MCF_CAN_MBUF11_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013C+((x)*0x30000)])) -#define MCF_CAN_MBUF11_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013D+((x)*0x30000)])) -#define MCF_CAN_MBUF11_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013E+((x)*0x30000)])) -#define MCF_CAN_MBUF11_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013F+((x)*0x30000)])) -#define MCF_CAN_MBUF12_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0140+((x)*0x30000)])) -#define MCF_CAN_MBUF12_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0144+((x)*0x30000)])) -#define MCF_CAN_MBUF12_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0148+((x)*0x30000)])) -#define MCF_CAN_MBUF12_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0149+((x)*0x30000)])) -#define MCF_CAN_MBUF12_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014A+((x)*0x30000)])) -#define MCF_CAN_MBUF12_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014B+((x)*0x30000)])) -#define MCF_CAN_MBUF12_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014C+((x)*0x30000)])) -#define MCF_CAN_MBUF12_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014D+((x)*0x30000)])) -#define MCF_CAN_MBUF12_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014E+((x)*0x30000)])) -#define MCF_CAN_MBUF12_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014F+((x)*0x30000)])) -#define MCF_CAN_MBUF13_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0150+((x)*0x30000)])) -#define MCF_CAN_MBUF13_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0154+((x)*0x30000)])) -#define MCF_CAN_MBUF13_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0158+((x)*0x30000)])) -#define MCF_CAN_MBUF13_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0159+((x)*0x30000)])) -#define MCF_CAN_MBUF13_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015A+((x)*0x30000)])) -#define MCF_CAN_MBUF13_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015B+((x)*0x30000)])) -#define MCF_CAN_MBUF13_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015C+((x)*0x30000)])) -#define MCF_CAN_MBUF13_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015D+((x)*0x30000)])) -#define MCF_CAN_MBUF13_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015E+((x)*0x30000)])) -#define MCF_CAN_MBUF13_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015F+((x)*0x30000)])) -#define MCF_CAN_MBUF14_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0160+((x)*0x30000)])) -#define MCF_CAN_MBUF14_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0164+((x)*0x30000)])) -#define MCF_CAN_MBUF14_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0168+((x)*0x30000)])) -#define MCF_CAN_MBUF14_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0169+((x)*0x30000)])) -#define MCF_CAN_MBUF14_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016A+((x)*0x30000)])) -#define MCF_CAN_MBUF14_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016B+((x)*0x30000)])) -#define MCF_CAN_MBUF14_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016C+((x)*0x30000)])) -#define MCF_CAN_MBUF14_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016D+((x)*0x30000)])) -#define MCF_CAN_MBUF14_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016E+((x)*0x30000)])) -#define MCF_CAN_MBUF14_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016F+((x)*0x30000)])) -#define MCF_CAN_MBUF15_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0170+((x)*0x30000)])) -#define MCF_CAN_MBUF15_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0174+((x)*0x30000)])) -#define MCF_CAN_MBUF15_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0178+((x)*0x30000)])) -#define MCF_CAN_MBUF15_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0179+((x)*0x30000)])) -#define MCF_CAN_MBUF15_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017A+((x)*0x30000)])) -#define MCF_CAN_MBUF15_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017B+((x)*0x30000)])) -#define MCF_CAN_MBUF15_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017C+((x)*0x30000)])) -#define MCF_CAN_MBUF15_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017D+((x)*0x30000)])) -#define MCF_CAN_MBUF15_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017E+((x)*0x30000)])) -#define MCF_CAN_MBUF15_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017F+((x)*0x30000)])) - - -#define MCF_CAN_MBUF0_DATAL(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0088+((x)*0x30000)])) -#define MCF_CAN_MBUF0_DATAH(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C008C+((x)*0x30000)])) -#define MCF_CAN_MBUF1_DATAL(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0098+((x)*0x30000)])) -#define MCF_CAN_MBUF1_DATAH(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C009C+((x)*0x30000)])) -#define MCF_CAN_MBUF2_DATAL(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00A8+((x)*0x30000)])) -#define MCF_CAN_MBUF2_DATAH(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00AC+((x)*0x30000)])) - - -/* Bit definitions and macros for MCF_CAN_CANMCR */ -#define MCF_CAN_CANMCR_MAXMB(x) (((x)&0x0000000F)<<0) -#define MCF_CAN_CANMCR_SUPV (0x00800000) -#define MCF_CAN_CANMCR_FRZACK (0x01000000) -#define MCF_CAN_CANMCR_SOFTRST (0x02000000) -#define MCF_CAN_CANMCR_HALT (0x10000000) -#define MCF_CAN_CANMCR_FRZ (0x40000000) -#define MCF_CAN_CANMCR_MDIS (0x80000000) - -/* Bit definitions and macros for MCF_CAN_CANCTRL */ -#define MCF_CAN_CANCTRL_PROPSEG(x) (((x)&0x00000007)<<0) -#define MCF_CAN_CANCTRL_LOM (0x00000008) -#define MCF_CAN_CANCTRL_LBUF (0x00000010) -#define MCF_CAN_CANCTRL_TSYNC (0x00000020) -#define MCF_CAN_CANCTRL_BOFFREC (0x00000040) -#define MCF_CAN_CANCTRL_SAMP (0x00000080) -#define MCF_CAN_CANCTRL_LPB (0x00001000) -#define MCF_CAN_CANCTRL_CLKSRC (0x00002000) -#define MCF_CAN_CANCTRL_ERRMSK (0x00004000) -#define MCF_CAN_CANCTRL_BOFFMSK (0x00008000) -#define MCF_CAN_CANCTRL_PSEG2(x) (((x)&0x00000007)<<16) -#define MCF_CAN_CANCTRL_PSEG1(x) (((x)&0x00000007)<<19) -#define MCF_CAN_CANCTRL_RJW(x) (((x)&0x00000003)<<22) -#define MCF_CAN_CANCTRL_PRESDIV(x) (((x)&0x000000FF)<<24) - -/* Bit definitions and macros for MCF_CAN_TIMER */ -#define MCF_CAN_TIMER_TIMER(x) (((x)&0x0000FFFF)<<0) - -/* Bit definitions and macros for MCF_CAN_RXGMASK */ -#define MCF_CAN_RXGMASK_MI(x) (((x)&0x1FFFFFFF)<<0) - -/* Bit definitions and macros for MCF_CAN_RX14MASK */ -#define MCF_CAN_RX14MASK_MI(x) (((x)&0x1FFFFFFF)<<0) - -/* Bit definitions and macros for MCF_CAN_RX15MASK */ -#define MCF_CAN_RX15MASK_MI(x) (((x)&0x1FFFFFFF)<<0) - -/* Bit definitions and macros for MCF_CAN_ERRCNT */ -#define MCF_CAN_ERRCNT_TXECTR(x) (((x)&0x000000FF)<<0) -#define MCF_CAN_ERRCNT_RXECTR(x) (((x)&0x000000FF)<<8) - -/* Bit definitions and macros for MCF_CAN_ERRSTAT */ -#define MCF_CAN_ERRSTAT_WAKINT (0x00000001) -#define MCF_CAN_ERRSTAT_ERRINT (0x00000002) -#define MCF_CAN_ERRSTAT_BOFFINT (0x00000004) -#define MCF_CAN_ERRSTAT_FLTCONF(x) (((x)&0x00000003)<<4) -#define MCF_CAN_ERRSTAT_TXRX (0x00000040) -#define MCF_CAN_ERRSTAT_IDLE (0x00000080) -#define MCF_CAN_ERRSTAT_RXWRN (0x00000100) -#define MCF_CAN_ERRSTAT_TXWRN (0x00000200) -#define MCF_CAN_ERRSTAT_STFERR (0x00000400) -#define MCF_CAN_ERRSTAT_FRMERR (0x00000800) -#define MCF_CAN_ERRSTAT_CRCERR (0x00001000) -#define MCF_CAN_ERRSTAT_ACKERR (0x00002000) -#define MCF_CAN_ERRSTAT_BITERR(x) (((x)&0x00000003)<<14) -#define MCF_CAN_ERRSTAT_FLTCONF_ACTIVE (0x00000000) -#define MCF_CAN_ERRSTAT_FLTCONF_PASSIVE (0x00000010) -#define MCF_CAN_ERRSTAT_FLTCONF_BUSOFF (0x00000020) - -/* Bit definitions and macros for MCF_CAN_IMASK */ -#define MCF_CAN_IMASK_BUF0M (0x0001) -#define MCF_CAN_IMASK_BUF1M (0x0002) -#define MCF_CAN_IMASK_BUF2M (0x0004) -#define MCF_CAN_IMASK_BUF3M (0x0008) -#define MCF_CAN_IMASK_BUF4M (0x0010) -#define MCF_CAN_IMASK_BUF5M (0x0020) -#define MCF_CAN_IMASK_BUF6M (0x0040) -#define MCF_CAN_IMASK_BUF7M (0x0080) -#define MCF_CAN_IMASK_BUF8M (0x0100) -#define MCF_CAN_IMASK_BUF9M (0x0200) -#define MCF_CAN_IMASK_BUF10M (0x0400) -#define MCF_CAN_IMASK_BUF11M (0x0800) -#define MCF_CAN_IMASK_BUF12M (0x1000) -#define MCF_CAN_IMASK_BUF13M (0x2000) -#define MCF_CAN_IMASK_BUF14M (0x4000) -#define MCF_CAN_IMASK_BUF15M (0x8000) - -/* Bit definitions and macros for MCF_CAN_IFLAG */ -#define MCF_CAN_IFLAG_BUF0I (0x0001) -#define MCF_CAN_IFLAG_BUF1I (0x0002) -#define MCF_CAN_IFLAG_BUF2I (0x0004) -#define MCF_CAN_IFLAG_BUF3I (0x0008) -#define MCF_CAN_IFLAG_BUF4I (0x0010) -#define MCF_CAN_IFLAG_BUF5I (0x0020) -#define MCF_CAN_IFLAG_BUF6I (0x0040) -#define MCF_CAN_IFLAG_BUF7I (0x0080) -#define MCF_CAN_IFLAG_BUF8I (0x0100) -#define MCF_CAN_IFLAG_BUF9I (0x0200) -#define MCF_CAN_IFLAG_BUF10I (0x0400) -#define MCF_CAN_IFLAG_BUF11I (0x0800) -#define MCF_CAN_IFLAG_BUF12I (0x1000) -#define MCF_CAN_IFLAG_BUF13I (0x2000) -#define MCF_CAN_IFLAG_BUF14I (0x4000) -#define MCF_CAN_IFLAG_BUF15I (0x8000) - -/********************************************************************/ - -#endif /* __MCF523X_CAN_H__ */ diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_ccm.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_ccm.h deleted file mode 100644 index da9bdb79e..000000000 --- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_ccm.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * These files are taken from the MCF523X source code example package - * which is available on the Freescale website. Freescale explicitly - * grants the redistribution and modification of these source files. - * The complete licensing information is available in the file - * LICENSE_FREESCALE.TXT. - * - * File: mcf523x_ccm.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_CCM_H__ -#define __MCF523X_CCM_H__ - -/********************************************************************* -* -* Chip Configuration Module (CCM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_CCM_CCR (*(vuint16*)(void*)(&__IPSBAR[0x110004])) -#define MCF_CCM_LPCR (*(vuint8 *)(void*)(&__IPSBAR[0x110007])) -#define MCF_CCM_CIR (*(vuint16*)(void*)(&__IPSBAR[0x11000A])) -#define MCF_CCM_RCON (*(vuint16*)(void*)(&__IPSBAR[0x110008])) - -/* Bit definitions and macros for MCF_CCM_CCR */ -#define MCF_CCM_CCR_BMT(x) (((x)&0x0007)<<0) -#define MCF_CCM_CCR_BME (0x0008) -#define MCF_CCM_CCR_SZEN (0x0040) -#define MCF_CCM_CCR_MODE(x) (((x)&0x0007)<<8) - -/* Bit definitions and macros for MCF_CCM_LPCR */ -#define MCF_CCM_LPCR_STPMD(x) (((x)&0x03)<<3) -#define MCF_CCM_LPCR_LPMD(x) (((x)&0x03)<<6) -#define MCF_CCM_LPCR_LPMD_STOP (0xC0) -#define MCF_CCM_LPCR_LPMD_WAIT (0x80) -#define MCF_CCM_LPCR_LPMD_DOZE (0x40) -#define MCF_CCM_LPCR_LPMD_RUN (0x00) - -/* Bit definitions and macros for MCF_CCM_CIR */ -#define MCF_CCM_CIR_PRN(x) (((x)&0x003F)<<0) -#define MCF_CCM_CIR_PIN(x) (((x)&0x03FF)<<6) - -/* Bit definitions and macros for MCF_CCM_RCON */ -#define MCF_CCM_RCON_MODE (0x0001) -#define MCF_CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3) -#define MCF_CCM_RCON_RLOAD (0x0020) -#define MCF_CCM_RCON_RCSC(x) (((x)&0x0003)<<8) - -/********************************************************************/ - -#endif /* __MCF523X_CCM_H__ */ diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_cs.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_cs.h deleted file mode 100644 index 27251c80a..000000000 --- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_cs.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * These files are taken from the MCF523X source code example package - * which is available on the Freescale website. Freescale explicitly - * grants the redistribution and modification of these source files. - * The complete licensing information is available in the file - * LICENSE_FREESCALE.TXT. - * - * File: mcf523x_cs.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_CS_H__ -#define __MCF523X_CS_H__ - -/********************************************************************* -* -* Chip Selects (CS) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_CS_CSAR0 (*(vuint16*)(void*)(&__IPSBAR[0x000080])) -#define MCF_CS_CSMR0 (*(vuint32*)(void*)(&__IPSBAR[0x000084])) -#define MCF_CS_CSCR0 (*(vuint16*)(void*)(&__IPSBAR[0x00008A])) -#define MCF_CS_CSAR1 (*(vuint16*)(void*)(&__IPSBAR[0x00008C])) -#define MCF_CS_CSMR1 (*(vuint32*)(void*)(&__IPSBAR[0x000090])) -#define MCF_CS_CSCR1 (*(vuint16*)(void*)(&__IPSBAR[0x000096])) -#define MCF_CS_CSAR2 (*(vuint16*)(void*)(&__IPSBAR[0x000098])) -#define MCF_CS_CSMR2 (*(vuint32*)(void*)(&__IPSBAR[0x00009C])) -#define MCF_CS_CSCR2 (*(vuint16*)(void*)(&__IPSBAR[0x0000A2])) -#define MCF_CS_CSAR3 (*(vuint16*)(void*)(&__IPSBAR[0x0000A4])) -#define MCF_CS_CSMR3 (*(vuint32*)(void*)(&__IPSBAR[0x0000A8])) -#define MCF_CS_CSCR3 (*(vuint16*)(void*)(&__IPSBAR[0x0000AE])) -#define MCF_CS_CSAR4 (*(vuint16*)(void*)(&__IPSBAR[0x0000B0])) -#define MCF_CS_CSMR4 (*(vuint32*)(void*)(&__IPSBAR[0x0000B4])) -#define MCF_CS_CSCR4 (*(vuint16*)(void*)(&__IPSBAR[0x0000BA])) -#define MCF_CS_CSAR5 (*(vuint16*)(void*)(&__IPSBAR[0x0000BC])) -#define MCF_CS_CSMR5 (*(vuint32*)(void*)(&__IPSBAR[0x0000C0])) -#define MCF_CS_CSCR5 (*(vuint16*)(void*)(&__IPSBAR[0x0000C6])) -#define MCF_CS_CSAR6 (*(vuint16*)(void*)(&__IPSBAR[0x0000C8])) -#define MCF_CS_CSMR6 (*(vuint32*)(void*)(&__IPSBAR[0x0000CC])) -#define MCF_CS_CSCR6 (*(vuint16*)(void*)(&__IPSBAR[0x0000D2])) -#define MCF_CS_CSAR7 (*(vuint16*)(void*)(&__IPSBAR[0x0000D4])) -#define MCF_CS_CSMR7 (*(vuint32*)(void*)(&__IPSBAR[0x0000D8])) -#define MCF_CS_CSCR7 (*(vuint16*)(void*)(&__IPSBAR[0x0000DE])) -#define MCF_CS_CSAR(x) (*(vuint16*)(void*)(&__IPSBAR[0x000080+((x)*0x00C)])) -#define MCF_CS_CSMR(x) (*(vuint32*)(void*)(&__IPSBAR[0x000084+((x)*0x00C)])) -#define MCF_CS_CSCR(x) (*(vuint16*)(void*)(&__IPSBAR[0x00008A+((x)*0x00C)])) - -/* Bit definitions and macros for MCF_CS_CSAR */ -#define MCF_CS_CSAR_BA(x) ((uint16)(((x)&0xFFFF0000)>>16)) - -/* Bit definitions and macros for MCF_CS_CSMR */ -#define MCF_CS_CSMR_V (0x00000001) -#define MCF_CS_CSMR_UD (0x00000002) -#define MCF_CS_CSMR_UC (0x00000004) -#define MCF_CS_CSMR_SD (0x00000008) -#define MCF_CS_CSMR_SC (0x00000010) -#define MCF_CS_CSMR_CI (0x00000020) -#define MCF_CS_CSMR_AM (0x00000040) -#define MCF_CS_CSMR_WP (0x00000100) -#define MCF_CS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) -#define MCF_CS_CSMR_BAM_4G (0xFFFF0000) -#define MCF_CS_CSMR_BAM_2G (0x7FFF0000) -#define MCF_CS_CSMR_BAM_1G (0x3FFF0000) -#define MCF_CS_CSMR_BAM_1024M (0x3FFF0000) -#define MCF_CS_CSMR_BAM_512M (0x1FFF0000) -#define MCF_CS_CSMR_BAM_256M (0x0FFF0000) -#define MCF_CS_CSMR_BAM_128M (0x07FF0000) -#define MCF_CS_CSMR_BAM_64M (0x03FF0000) -#define MCF_CS_CSMR_BAM_32M (0x01FF0000) -#define MCF_CS_CSMR_BAM_16M (0x00FF0000) -#define MCF_CS_CSMR_BAM_8M (0x007F0000) -#define MCF_CS_CSMR_BAM_4M (0x003F0000) -#define MCF_CS_CSMR_BAM_2M (0x001F0000) -#define MCF_CS_CSMR_BAM_1M (0x000F0000) -#define MCF_CS_CSMR_BAM_1024K (0x000F0000) -#define MCF_CS_CSMR_BAM_512K (0x00070000) -#define MCF_CS_CSMR_BAM_256K (0x00030000) -#define MCF_CS_CSMR_BAM_128K (0x00010000) -#define MCF_CS_CSMR_BAM_64K (0x00000000) - -/* Bit definitions and macros for MCF_CS_CSCR */ -#define MCF_CS_CSCR_SWWS(x) (((x)&0x0007)<<0) -#define MCF_CS_CSCR_BSTW (0x0008) -#define MCF_CS_CSCR_BSTR (0x0010) -#define MCF_CS_CSCR_BEM (0x0020) -#define MCF_CS_CSCR_PS(x) (((x)&0x0003)<<6) -#define MCF_CS_CSCR_AA (0x0100) -#define MCF_CS_CSCR_IWS(x) (((x)&0x000F)<<10) -#define MCF_CS_CSCR_SRWS(x) (((x)&0x0003)<<14) -#define MCF_CS_CSCR_PS_8 (0x0040) -#define MCF_CS_CSCR_PS_16 (0x0080) -#define MCF_CS_CSCR_PS_32 (0x0000) - -/********************************************************************/ - -#endif /* __MCF523X_CS_H__ */ diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_eport.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_eport.h deleted file mode 100644 index 5629ebfa4..000000000 --- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_eport.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - * These files are taken from the MCF523X source code example package - * which is available on the Freescale website. Freescale explicitly - * grants the redistribution and modification of these source files. - * The complete licensing information is available in the file - * LICENSE_FREESCALE.TXT. - * - * File: mcf523x_eport.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_EPORT_H__ -#define __MCF523X_EPORT_H__ - -/********************************************************************* -* -* Edge Port Module (EPORT) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_EPORT_EPPAR (*(vuint16*)(void*)(&__IPSBAR[0x130000])) -#define MCF_EPORT_EPDDR (*(vuint8 *)(void*)(&__IPSBAR[0x130002])) -#define MCF_EPORT_EPIER (*(vuint8 *)(void*)(&__IPSBAR[0x130003])) -#define MCF_EPORT_EPDR (*(vuint8 *)(void*)(&__IPSBAR[0x130004])) -#define MCF_EPORT_EPPDR (*(vuint8 *)(void*)(&__IPSBAR[0x130005])) -#define MCF_EPORT_EPFR (*(vuint8 *)(void*)(&__IPSBAR[0x130006])) - -/* Bit definitions and macros for MCF_EPORT_EPPAR */ -#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2) -#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4) -#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6) -#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8) -#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10) -#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12) -#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14) -#define MCF_EPORT_EPPAR_EPPAx_LEVEL (0) -#define MCF_EPORT_EPPAR_EPPAx_RISING (1) -#define MCF_EPORT_EPPAR_EPPAx_FALLING (2) -#define MCF_EPORT_EPPAR_EPPAx_BOTH (3) - -/* Bit definitions and macros for MCF_EPORT_EPDDR */ -#define MCF_EPORT_EPDDR_EPDD1 (0x02) -#define MCF_EPORT_EPDDR_EPDD2 (0x04) -#define MCF_EPORT_EPDDR_EPDD3 (0x08) -#define MCF_EPORT_EPDDR_EPDD4 (0x10) -#define MCF_EPORT_EPDDR_EPDD5 (0x20) -#define MCF_EPORT_EPDDR_EPDD6 (0x40) -#define MCF_EPORT_EPDDR_EPDD7 (0x80) - -/* Bit definitions and macros for MCF_EPORT_EPIER */ -#define MCF_EPORT_EPIER_EPIE1 (0x02) -#define MCF_EPORT_EPIER_EPIE2 (0x04) -#define MCF_EPORT_EPIER_EPIE3 (0x08) -#define MCF_EPORT_EPIER_EPIE4 (0x10) -#define MCF_EPORT_EPIER_EPIE5 (0x20) -#define MCF_EPORT_EPIER_EPIE6 (0x40) -#define MCF_EPORT_EPIER_EPIE7 (0x80) - -/* Bit definitions and macros for MCF_EPORT_EPDR */ -#define MCF_EPORT_EPDR_EPD1 (0x02) -#define MCF_EPORT_EPDR_EPD2 (0x04) -#define MCF_EPORT_EPDR_EPD3 (0x08) -#define MCF_EPORT_EPDR_EPD4 (0x10) -#define MCF_EPORT_EPDR_EPD5 (0x20) -#define MCF_EPORT_EPDR_EPD6 (0x40) -#define MCF_EPORT_EPDR_EPD7 (0x80) - -/* Bit definitions and macros for MCF_EPORT_EPPDR */ -#define MCF_EPORT_EPPDR_EPPD1 (0x02) -#define MCF_EPORT_EPPDR_EPPD2 (0x04) -#define MCF_EPORT_EPPDR_EPPD3 (0x08) -#define MCF_EPORT_EPPDR_EPPD4 (0x10) -#define MCF_EPORT_EPPDR_EPPD5 (0x20) -#define MCF_EPORT_EPPDR_EPPD6 (0x40) -#define MCF_EPORT_EPPDR_EPPD7 (0x80) - -/* Bit definitions and macros for MCF_EPORT_EPFR */ -#define MCF_EPORT_EPFR_EPF1 (0x02) -#define MCF_EPORT_EPFR_EPF2 (0x04) -#define MCF_EPORT_EPFR_EPF3 (0x08) -#define MCF_EPORT_EPFR_EPF4 (0x10) -#define MCF_EPORT_EPFR_EPF5 (0x20) -#define MCF_EPORT_EPFR_EPF6 (0x40) -#define MCF_EPORT_EPFR_EPF7 (0x80) - -/********************************************************************/ - -#endif /* __MCF523X_EPORT_H__ */ diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_etpu.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_etpu.h deleted file mode 100644 index 91075acf8..000000000 --- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_etpu.h +++ /dev/null @@ -1,493 +0,0 @@ -/* - * These files are taken from the MCF523X source code example package - * which is available on the Freescale website. Freescale explicitly - * grants the redistribution and modification of these source files. - * The complete licensing information is available in the file - * LICENSE_FREESCALE.TXT. - * - * File: mcf523x_etpu.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_ETPU_H__ -#define __MCF523X_ETPU_H__ - -/********************************************************************* -* -* enhanced Time Processor Unit (ETPU) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_ETPU_EMCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0000])) -#define MCF_ETPU_ECDCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0004])) -#define MCF_ETPU_EMISCCR (*(vuint32*)(void*)(&__IPSBAR[0x1D000C])) -#define MCF_ETPU_ESCMODR (*(vuint32*)(void*)(&__IPSBAR[0x1D0010])) -#define MCF_ETPU_EECR (*(vuint32*)(void*)(&__IPSBAR[0x1D0014])) -#define MCF_ETPU_ETBCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0020])) -#define MCF_ETPU_ETB1R (*(vuint32*)(void*)(&__IPSBAR[0x1D0024])) -#define MCF_ETPU_ETB2R (*(vuint32*)(void*)(&__IPSBAR[0x1D0028])) -#define MCF_ETPU_EREDCR (*(vuint32*)(void*)(&__IPSBAR[0x1D002C])) -#define MCF_ETPU_ECISR (*(vuint32*)(void*)(&__IPSBAR[0x1D0200])) -#define MCF_ETPU_ECDTRSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0210])) -#define MCF_ETPU_ECIOSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0220])) -#define MCF_ETPU_ECDTROSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0230])) -#define MCF_ETPU_ECIER (*(vuint32*)(void*)(&__IPSBAR[0x1D0240])) -#define MCF_ETPU_ECDTRER (*(vuint32*)(void*)(&__IPSBAR[0x1D0250])) -#define MCF_ETPU_ECPSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0280])) -#define MCF_ETPU_ECSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0290])) -#define MCF_ETPU_EC0SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0404])) -#define MCF_ETPU_EC1SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0414])) -#define MCF_ETPU_EC2SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0424])) -#define MCF_ETPU_EC3SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0434])) -#define MCF_ETPU_EC4SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0444])) -#define MCF_ETPU_EC5SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0454])) -#define MCF_ETPU_EC6SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0464])) -#define MCF_ETPU_EC7SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0474])) -#define MCF_ETPU_EC8SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0484])) -#define MCF_ETPU_EC9SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0494])) -#define MCF_ETPU_EC10SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04A4])) -#define MCF_ETPU_EC11SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04B4])) -#define MCF_ETPU_EC12SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04C4])) -#define MCF_ETPU_EC13SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04D4])) -#define MCF_ETPU_EC14SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04E4])) -#define MCF_ETPU_EC15SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04F4])) -#define MCF_ETPU_EC16SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0504])) -#define MCF_ETPU_EC17SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0514])) -#define MCF_ETPU_EC18SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0524])) -#define MCF_ETPU_EC19SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0534])) -#define MCF_ETPU_EC20SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0544])) -#define MCF_ETPU_EC21SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0554])) -#define MCF_ETPU_EC22SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0564])) -#define MCF_ETPU_EC23SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0574])) -#define MCF_ETPU_EC24SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0584])) -#define MCF_ETPU_EC25SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0594])) -#define MCF_ETPU_EC26SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05A4])) -#define MCF_ETPU_EC27SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05B4])) -#define MCF_ETPU_EC28SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05C4])) -#define MCF_ETPU_EC29SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05D4])) -#define MCF_ETPU_EC30SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05E4])) -#define MCF_ETPU_EC31SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05F4])) -#define MCF_ETPU_ECnSCR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1D0404+((x)*0x010)])) -#define MCF_ETPU_EC0CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0400])) -#define MCF_ETPU_EC1CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0410])) -#define MCF_ETPU_EC2CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0420])) -#define MCF_ETPU_EC3CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0430])) -#define MCF_ETPU_EC4CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0440])) -#define MCF_ETPU_EC5CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0450])) -#define MCF_ETPU_EC6CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0460])) -#define MCF_ETPU_EC7CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0470])) -#define MCF_ETPU_EC8CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0480])) -#define MCF_ETPU_EC9CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0490])) -#define MCF_ETPU_EC10CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04A0])) -#define MCF_ETPU_EC11CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04B0])) -#define MCF_ETPU_EC12CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04C0])) -#define MCF_ETPU_EC13CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04D0])) -#define MCF_ETPU_EC14CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04E0])) -#define MCF_ETPU_EC15CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04F0])) -#define MCF_ETPU_EC16CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0500])) -#define MCF_ETPU_EC17CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0510])) -#define MCF_ETPU_EC18CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0520])) -#define MCF_ETPU_EC19CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0530])) -#define MCF_ETPU_EC20CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0540])) -#define MCF_ETPU_EC21CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0550])) -#define MCF_ETPU_EC22CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0560])) -#define MCF_ETPU_EC23CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0570])) -#define MCF_ETPU_EC24CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0580])) -#define MCF_ETPU_EC25CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0590])) -#define MCF_ETPU_EC26CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05A0])) -#define MCF_ETPU_EC27CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05B0])) -#define MCF_ETPU_EC28CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05C0])) -#define MCF_ETPU_EC29CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05D0])) -#define MCF_ETPU_EC30CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05E0])) -#define MCF_ETPU_EC31CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05F0])) -#define MCF_ETPU_ECnCR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1D0400+((x)*0x010)])) -#define MCF_ETPU_EC0HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0408])) -#define MCF_ETPU_EC1HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0418])) -#define MCF_ETPU_EC2HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0428])) -#define MCF_ETPU_EC3HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0438])) -#define MCF_ETPU_EC4HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0448])) -#define MCF_ETPU_EC5HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0458])) -#define MCF_ETPU_EC6HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0468])) -#define MCF_ETPU_EC7HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0478])) -#define MCF_ETPU_EC8HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0488])) -#define MCF_ETPU_EC9HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0498])) -#define MCF_ETPU_EC10HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04A8])) -#define MCF_ETPU_EC11HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04B8])) -#define MCF_ETPU_EC12HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04C8])) -#define MCF_ETPU_EC13HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04D8])) -#define MCF_ETPU_EC14HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04E8])) -#define MCF_ETPU_EC15HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04F8])) -#define MCF_ETPU_EC16HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0508])) -#define MCF_ETPU_EC17HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0518])) -#define MCF_ETPU_EC18HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0528])) -#define MCF_ETPU_EC19HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0538])) -#define MCF_ETPU_EC20HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0548])) -#define MCF_ETPU_EC21HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0558])) -#define MCF_ETPU_EC22HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0568])) -#define MCF_ETPU_EC23HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0578])) -#define MCF_ETPU_EC24HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0588])) -#define MCF_ETPU_EC25HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0598])) -#define MCF_ETPU_EC26HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05A8])) -#define MCF_ETPU_EC27HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05B8])) -#define MCF_ETPU_EC28HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05C8])) -#define MCF_ETPU_EC29HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05D8])) -#define MCF_ETPU_EC30HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05E8])) -#define MCF_ETPU_EC31HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05F8])) -#define MCF_ETPU_ECnHSSR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1D0408+((x)*0x010)])) - -/* Bit definitions and macros for MCF_ETPU_EMCR */ -#define MCF_ETPU_EMCR_GTBE (0x00000001) -#define MCF_ETPU_EMCR_VIS (0x00000040) -#define MCF_ETPU_EMCR_SCMMISEN (0x00000200) -#define MCF_ETPU_EMCR_SCMMISF (0x00000400) -#define MCF_ETPU_EMCR_SCMSIZE(x) (((x)&0x0000001F)<<16) -#define MCF_ETPU_EMCR_ILF2 (0x01000000) -#define MCF_ETPU_EMCR_ILF1 (0x02000000) -#define MCF_ETPU_EMCR_MGE2 (0x04000000) -#define MCF_ETPU_EMCR_MGE1 (0x08000000) -#define MCF_ETPU_EMCR_GEC (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECDCR */ -#define MCF_ETPU_ECDCR_PARM1(x) (((x)&0x0000007F)<<0) -#define MCF_ETPU_ECDCR_WR (0x00000080) -#define MCF_ETPU_ECDCR_PARM0(x) (((x)&0x0000007F)<<8) -#define MCF_ETPU_ECDCR_PWIDTH (0x00008000) -#define MCF_ETPU_ECDCR_PBASE(x) (((x)&0x000003FF)<<16) -#define MCF_ETPU_ECDCR_CTBASE(x) (((x)&0x0000001F)<<26) -#define MCF_ETPU_ECDCR_STS (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_EECR */ -#define MCF_ETPU_EECR_ETB(x) (((x)&0x0000001F)<<0) -#define MCF_ETPU_EECR_CDFC(x) (((x)&0x00000003)<<14) -#define MCF_ETPU_EECR_FPSK(x) (((x)&0x00000007)<<16) -#define MCF_ETPU_EECR_HLTF (0x00800000) -#define MCF_ETPU_EECR_STF (0x10000000) -#define MCF_ETPU_EECR_MDIS (0x40000000) -#define MCF_ETPU_EECR_FEND (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ETBCR */ -#define MCF_ETPU_ETBCR_TCR1P(x) (((x)&0x000000FF)<<0) -#define MCF_ETPU_ETBCR_TCR1CTL(x) (((x)&0x00000003)<<14) -#define MCF_ETPU_ETBCR_TCR2P(x) (((x)&0x0000003F)<<16) -#define MCF_ETPU_ETBCR_AM (0x02000000) -#define MCF_ETPU_ETBCR_TCRCF(x) (((x)&0x00000003)<<27) -#define MCF_ETPU_ETBCR_TCR2CTL(x) (((x)&0x00000007)<<29) - -/* Bit definitions and macros for MCF_ETPU_ETB1R */ -#define MCF_ETPU_ETB1R_TCR1(x) (((x)&0x00FFFFFF)<<0) - -/* Bit definitions and macros for MCF_ETPU_ETB2R */ -#define MCF_ETPU_ETB2R_TCR2(x) (((x)&0x00FFFFFF)<<0) - -/* Bit definitions and macros for MCF_ETPU_EREDCR */ -#define MCF_ETPU_EREDCR_SRV2(x) (((x)&0x0000000F)<<0) -#define MCF_ETPU_EREDCR_SERVER_ID2(x) (((x)&0x0000000F)<<8) -#define MCF_ETPU_EREDCR_RSC2 (0x00004000) -#define MCF_ETPU_EREDCR_REN2 (0x00008000) -#define MCF_ETPU_EREDCR_SRV1(x) (((x)&0x0000000F)<<16) -#define MCF_ETPU_EREDCR_SERVER_ID1(x) (((x)&0x0000000F)<<24) -#define MCF_ETPU_EREDCR_RSC1 (0x40000000) -#define MCF_ETPU_EREDCR_REN1 (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECISR */ -#define MCF_ETPU_ECISR_CIS0 (0x00000001) -#define MCF_ETPU_ECISR_CIS1 (0x00000002) -#define MCF_ETPU_ECISR_CIS2 (0x00000004) -#define MCF_ETPU_ECISR_CIS3 (0x00000008) -#define MCF_ETPU_ECISR_CIS4 (0x00000010) -#define MCF_ETPU_ECISR_CIS5 (0x00000020) -#define MCF_ETPU_ECISR_CIS6 (0x00000040) -#define MCF_ETPU_ECISR_CIS7 (0x00000080) -#define MCF_ETPU_ECISR_CIS8 (0x00000100) -#define MCF_ETPU_ECISR_CIS9 (0x00000200) -#define MCF_ETPU_ECISR_CIS10 (0x00000400) -#define MCF_ETPU_ECISR_CIS11 (0x00000800) -#define MCF_ETPU_ECISR_CIS12 (0x00001000) -#define MCF_ETPU_ECISR_CIS13 (0x00002000) -#define MCF_ETPU_ECISR_CIS14 (0x00004000) -#define MCF_ETPU_ECISR_CIS15 (0x00008000) -#define MCF_ETPU_ECISR_CIS16 (0x00010000) -#define MCF_ETPU_ECISR_CIS17 (0x00020000) -#define MCF_ETPU_ECISR_CIS18 (0x00040000) -#define MCF_ETPU_ECISR_CIS19 (0x00080000) -#define MCF_ETPU_ECISR_CIS20 (0x00100000) -#define MCF_ETPU_ECISR_CIS21 (0x00200000) -#define MCF_ETPU_ECISR_CIS22 (0x00400000) -#define MCF_ETPU_ECISR_CIS23 (0x00800000) -#define MCF_ETPU_ECISR_CIS24 (0x01000000) -#define MCF_ETPU_ECISR_CIS25 (0x02000000) -#define MCF_ETPU_ECISR_CIS26 (0x04000000) -#define MCF_ETPU_ECISR_CIS27 (0x08000000) -#define MCF_ETPU_ECISR_CIS28 (0x10000000) -#define MCF_ETPU_ECISR_CIS29 (0x20000000) -#define MCF_ETPU_ECISR_CIS30 (0x40000000) -#define MCF_ETPU_ECISR_CIS31 (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECDTRSR */ -#define MCF_ETPU_ECDTRSR_DTRS0 (0x00000001) -#define MCF_ETPU_ECDTRSR_DTRS1 (0x00000002) -#define MCF_ETPU_ECDTRSR_DTRS2 (0x00000004) -#define MCF_ETPU_ECDTRSR_DTRS3 (0x00000008) -#define MCF_ETPU_ECDTRSR_DTRS4 (0x00000010) -#define MCF_ETPU_ECDTRSR_DTRS5 (0x00000020) -#define MCF_ETPU_ECDTRSR_DTRS6 (0x00000040) -#define MCF_ETPU_ECDTRSR_DTRS7 (0x00000080) -#define MCF_ETPU_ECDTRSR_DTRS8 (0x00000100) -#define MCF_ETPU_ECDTRSR_DTRS9 (0x00000200) -#define MCF_ETPU_ECDTRSR_DTRS10 (0x00000400) -#define MCF_ETPU_ECDTRSR_DTRS11 (0x00000800) -#define MCF_ETPU_ECDTRSR_DTRS12 (0x00001000) -#define MCF_ETPU_ECDTRSR_DTRS13 (0x00002000) -#define MCF_ETPU_ECDTRSR_DTRS14 (0x00004000) -#define MCF_ETPU_ECDTRSR_DTRS15 (0x00008000) -#define MCF_ETPU_ECDTRSR_DTRS16 (0x00010000) -#define MCF_ETPU_ECDTRSR_DTRS17 (0x00020000) -#define MCF_ETPU_ECDTRSR_DTRS18 (0x00040000) -#define MCF_ETPU_ECDTRSR_DTRS19 (0x00080000) -#define MCF_ETPU_ECDTRSR_DTRS20 (0x00100000) -#define MCF_ETPU_ECDTRSR_DTRS21 (0x00200000) -#define MCF_ETPU_ECDTRSR_DTRS22 (0x00400000) -#define MCF_ETPU_ECDTRSR_DTRS23 (0x00800000) -#define MCF_ETPU_ECDTRSR_DTRS24 (0x01000000) -#define MCF_ETPU_ECDTRSR_DTRS25 (0x02000000) -#define MCF_ETPU_ECDTRSR_DTRS26 (0x04000000) -#define MCF_ETPU_ECDTRSR_DTRS27 (0x08000000) -#define MCF_ETPU_ECDTRSR_DTRS28 (0x10000000) -#define MCF_ETPU_ECDTRSR_DTRS29 (0x20000000) -#define MCF_ETPU_ECDTRSR_DTRS30 (0x40000000) -#define MCF_ETPU_ECDTRSR_DTRS31 (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECIOSR */ -#define MCF_ETPU_ECIOSR_CIOS0 (0x00000001) -#define MCF_ETPU_ECIOSR_CIOS1 (0x00000002) -#define MCF_ETPU_ECIOSR_CIOS2 (0x00000004) -#define MCF_ETPU_ECIOSR_CIOS3 (0x00000008) -#define MCF_ETPU_ECIOSR_CIOS4 (0x00000010) -#define MCF_ETPU_ECIOSR_CIOS5 (0x00000020) -#define MCF_ETPU_ECIOSR_CIOS6 (0x00000040) -#define MCF_ETPU_ECIOSR_CIOS7 (0x00000080) -#define MCF_ETPU_ECIOSR_CIOS8 (0x00000100) -#define MCF_ETPU_ECIOSR_CIOS9 (0x00000200) -#define MCF_ETPU_ECIOSR_CIOS10 (0x00000400) -#define MCF_ETPU_ECIOSR_CIOS11 (0x00000800) -#define MCF_ETPU_ECIOSR_CIOS12 (0x00001000) -#define MCF_ETPU_ECIOSR_CIOS13 (0x00002000) -#define MCF_ETPU_ECIOSR_CIOS14 (0x00004000) -#define MCF_ETPU_ECIOSR_CIOS15 (0x00008000) -#define MCF_ETPU_ECIOSR_CIOS16 (0x00010000) -#define MCF_ETPU_ECIOSR_CIOS17 (0x00020000) -#define MCF_ETPU_ECIOSR_CIOS18 (0x00040000) -#define MCF_ETPU_ECIOSR_CIOS19 (0x00080000) -#define MCF_ETPU_ECIOSR_CIOS20 (0x00100000) -#define MCF_ETPU_ECIOSR_CIOS21 (0x00200000) -#define MCF_ETPU_ECIOSR_CIOS22 (0x00400000) -#define MCF_ETPU_ECIOSR_CIOS23 (0x00800000) -#define MCF_ETPU_ECIOSR_CIOS24 (0x01000000) -#define MCF_ETPU_ECIOSR_CIOS25 (0x02000000) -#define MCF_ETPU_ECIOSR_CIOS26 (0x04000000) -#define MCF_ETPU_ECIOSR_CIOS27 (0x08000000) -#define MCF_ETPU_ECIOSR_CIOS28 (0x10000000) -#define MCF_ETPU_ECIOSR_CIOS29 (0x20000000) -#define MCF_ETPU_ECIOSR_CIOS30 (0x40000000) -#define MCF_ETPU_ECIOSR_CIOS31 (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECDTROSR */ -#define MCF_ETPU_ECDTROSR_DTROS0 (0x00000001) -#define MCF_ETPU_ECDTROSR_DTROS1 (0x00000002) -#define MCF_ETPU_ECDTROSR_DTROS2 (0x00000004) -#define MCF_ETPU_ECDTROSR_DTROS3 (0x00000008) -#define MCF_ETPU_ECDTROSR_DTROS4 (0x00000010) -#define MCF_ETPU_ECDTROSR_DTROS5 (0x00000020) -#define MCF_ETPU_ECDTROSR_DTROS6 (0x00000040) -#define MCF_ETPU_ECDTROSR_DTROS7 (0x00000080) -#define MCF_ETPU_ECDTROSR_DTROS8 (0x00000100) -#define MCF_ETPU_ECDTROSR_DTROS9 (0x00000200) -#define MCF_ETPU_ECDTROSR_DTROS10 (0x00000400) -#define MCF_ETPU_ECDTROSR_DTROS11 (0x00000800) -#define MCF_ETPU_ECDTROSR_DTROS12 (0x00001000) -#define MCF_ETPU_ECDTROSR_DTROS13 (0x00002000) -#define MCF_ETPU_ECDTROSR_DTROS14 (0x00004000) -#define MCF_ETPU_ECDTROSR_DTROS15 (0x00008000) -#define MCF_ETPU_ECDTROSR_DTROS16 (0x00010000) -#define MCF_ETPU_ECDTROSR_DTROS17 (0x00020000) -#define MCF_ETPU_ECDTROSR_DTROS18 (0x00040000) -#define MCF_ETPU_ECDTROSR_DTROS19 (0x00080000) -#define MCF_ETPU_ECDTROSR_DTROS20 (0x00100000) -#define MCF_ETPU_ECDTROSR_DTROS21 (0x00200000) -#define MCF_ETPU_ECDTROSR_DTROS22 (0x00400000) -#define MCF_ETPU_ECDTROSR_DTROS23 (0x00800000) -#define MCF_ETPU_ECDTROSR_DTROS24 (0x01000000) -#define MCF_ETPU_ECDTROSR_DTROS25 (0x02000000) -#define MCF_ETPU_ECDTROSR_DTROS26 (0x04000000) -#define MCF_ETPU_ECDTROSR_DTROS27 (0x08000000) -#define MCF_ETPU_ECDTROSR_DTROS28 (0x10000000) -#define MCF_ETPU_ECDTROSR_DTROS29 (0x20000000) -#define MCF_ETPU_ECDTROSR_DTROS30 (0x40000000) -#define MCF_ETPU_ECDTROSR_DTROS31 (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECIER */ -#define MCF_ETPU_ECIER_CIE0 (0x00000001) -#define MCF_ETPU_ECIER_CIE1 (0x00000002) -#define MCF_ETPU_ECIER_CIE2 (0x00000004) -#define MCF_ETPU_ECIER_CIE3 (0x00000008) -#define MCF_ETPU_ECIER_CIE4 (0x00000010) -#define MCF_ETPU_ECIER_CIE5 (0x00000020) -#define MCF_ETPU_ECIER_CIE6 (0x00000040) -#define MCF_ETPU_ECIER_CIE7 (0x00000080) -#define MCF_ETPU_ECIER_CIE8 (0x00000100) -#define MCF_ETPU_ECIER_CIE9 (0x00000200) -#define MCF_ETPU_ECIER_CIE10 (0x00000400) -#define MCF_ETPU_ECIER_CIE11 (0x00000800) -#define MCF_ETPU_ECIER_CIE12 (0x00001000) -#define MCF_ETPU_ECIER_CIE13 (0x00002000) -#define MCF_ETPU_ECIER_CIE14 (0x00004000) -#define MCF_ETPU_ECIER_CIE15 (0x00008000) -#define MCF_ETPU_ECIER_CIE16 (0x00010000) -#define MCF_ETPU_ECIER_CIE17 (0x00020000) -#define MCF_ETPU_ECIER_CIE18 (0x00040000) -#define MCF_ETPU_ECIER_CIE19 (0x00080000) -#define MCF_ETPU_ECIER_CIE20 (0x00100000) -#define MCF_ETPU_ECIER_CIE21 (0x00200000) -#define MCF_ETPU_ECIER_CIE22 (0x00400000) -#define MCF_ETPU_ECIER_CIE23 (0x00800000) -#define MCF_ETPU_ECIER_CIE24 (0x01000000) -#define MCF_ETPU_ECIER_CIE25 (0x02000000) -#define MCF_ETPU_ECIER_CIE26 (0x04000000) -#define MCF_ETPU_ECIER_CIE27 (0x08000000) -#define MCF_ETPU_ECIER_CIE28 (0x10000000) -#define MCF_ETPU_ECIER_CIE29 (0x20000000) -#define MCF_ETPU_ECIER_CIE30 (0x40000000) -#define MCF_ETPU_ECIER_CIE31 (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECDTRER */ -#define MCF_ETPU_ECDTRER_DTRE0 (0x00000001) -#define MCF_ETPU_ECDTRER_DTRE1 (0x00000002) -#define MCF_ETPU_ECDTRER_DTRE2 (0x00000004) -#define MCF_ETPU_ECDTRER_DTRE3 (0x00000008) -#define MCF_ETPU_ECDTRER_DTRE4 (0x00000010) -#define MCF_ETPU_ECDTRER_DTRE5 (0x00000020) -#define MCF_ETPU_ECDTRER_DTRE6 (0x00000040) -#define MCF_ETPU_ECDTRER_DTRE7 (0x00000080) -#define MCF_ETPU_ECDTRER_DTRE8 (0x00000100) -#define MCF_ETPU_ECDTRER_DTRE9 (0x00000200) -#define MCF_ETPU_ECDTRER_DTRE10 (0x00000400) -#define MCF_ETPU_ECDTRER_DTRE11 (0x00000800) -#define MCF_ETPU_ECDTRER_DTRE12 (0x00001000) -#define MCF_ETPU_ECDTRER_DTRE13 (0x00002000) -#define MCF_ETPU_ECDTRER_DTRE14 (0x00004000) -#define MCF_ETPU_ECDTRER_DTRE15 (0x00008000) -#define MCF_ETPU_ECDTRER_DTRE16 (0x00010000) -#define MCF_ETPU_ECDTRER_DTRE17 (0x00020000) -#define MCF_ETPU_ECDTRER_DTRE18 (0x00040000) -#define MCF_ETPU_ECDTRER_DTRE19 (0x00080000) -#define MCF_ETPU_ECDTRER_DTRE20 (0x00100000) -#define MCF_ETPU_ECDTRER_DTRE21 (0x00200000) -#define MCF_ETPU_ECDTRER_DTRE22 (0x00400000) -#define MCF_ETPU_ECDTRER_DTRE23 (0x00800000) -#define MCF_ETPU_ECDTRER_DTRE24 (0x01000000) -#define MCF_ETPU_ECDTRER_DTRE25 (0x02000000) -#define MCF_ETPU_ECDTRER_DTRE26 (0x04000000) -#define MCF_ETPU_ECDTRER_DTRE27 (0x08000000) -#define MCF_ETPU_ECDTRER_DTRE28 (0x10000000) -#define MCF_ETPU_ECDTRER_DTRE29 (0x20000000) -#define MCF_ETPU_ECDTRER_DTRE30 (0x40000000) -#define MCF_ETPU_ECDTRER_DTRE31 (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECPSSR */ -#define MCF_ETPU_ECPSSR_SR0 (0x00000001) -#define MCF_ETPU_ECPSSR_SR1 (0x00000002) -#define MCF_ETPU_ECPSSR_SR2 (0x00000004) -#define MCF_ETPU_ECPSSR_SR3 (0x00000008) -#define MCF_ETPU_ECPSSR_SR4 (0x00000010) -#define MCF_ETPU_ECPSSR_SR5 (0x00000020) -#define MCF_ETPU_ECPSSR_SR6 (0x00000040) -#define MCF_ETPU_ECPSSR_SR7 (0x00000080) -#define MCF_ETPU_ECPSSR_SR8 (0x00000100) -#define MCF_ETPU_ECPSSR_SR9 (0x00000200) -#define MCF_ETPU_ECPSSR_SR10 (0x00000400) -#define MCF_ETPU_ECPSSR_SR11 (0x00000800) -#define MCF_ETPU_ECPSSR_SR12 (0x00001000) -#define MCF_ETPU_ECPSSR_SR13 (0x00002000) -#define MCF_ETPU_ECPSSR_SR14 (0x00004000) -#define MCF_ETPU_ECPSSR_SR15 (0x00008000) -#define MCF_ETPU_ECPSSR_SR16 (0x00010000) -#define MCF_ETPU_ECPSSR_SR17 (0x00020000) -#define MCF_ETPU_ECPSSR_SR18 (0x00040000) -#define MCF_ETPU_ECPSSR_SR19 (0x00080000) -#define MCF_ETPU_ECPSSR_SR20 (0x00100000) -#define MCF_ETPU_ECPSSR_SR21 (0x00200000) -#define MCF_ETPU_ECPSSR_SR22 (0x00400000) -#define MCF_ETPU_ECPSSR_SR23 (0x00800000) -#define MCF_ETPU_ECPSSR_SR24 (0x01000000) -#define MCF_ETPU_ECPSSR_SR25 (0x02000000) -#define MCF_ETPU_ECPSSR_SR26 (0x04000000) -#define MCF_ETPU_ECPSSR_SR27 (0x08000000) -#define MCF_ETPU_ECPSSR_SR28 (0x10000000) -#define MCF_ETPU_ECPSSR_SR29 (0x20000000) -#define MCF_ETPU_ECPSSR_SR30 (0x40000000) -#define MCF_ETPU_ECPSSR_SR31 (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECSSR */ -#define MCF_ETPU_ECSSR_SS0 (0x00000001) -#define MCF_ETPU_ECSSR_SS1 (0x00000002) -#define MCF_ETPU_ECSSR_SS2 (0x00000004) -#define MCF_ETPU_ECSSR_SS3 (0x00000008) -#define MCF_ETPU_ECSSR_SS4 (0x00000010) -#define MCF_ETPU_ECSSR_SS5 (0x00000020) -#define MCF_ETPU_ECSSR_SS6 (0x00000040) -#define MCF_ETPU_ECSSR_SS7 (0x00000080) -#define MCF_ETPU_ECSSR_SS8 (0x00000100) -#define MCF_ETPU_ECSSR_SS9 (0x00000200) -#define MCF_ETPU_ECSSR_SS10 (0x00000400) -#define MCF_ETPU_ECSSR_SS11 (0x00000800) -#define MCF_ETPU_ECSSR_SS12 (0x00001000) -#define MCF_ETPU_ECSSR_SS13 (0x00002000) -#define MCF_ETPU_ECSSR_SS14 (0x00004000) -#define MCF_ETPU_ECSSR_SS15 (0x00008000) -#define MCF_ETPU_ECSSR_SS16 (0x00010000) -#define MCF_ETPU_ECSSR_SS17 (0x00020000) -#define MCF_ETPU_ECSSR_SS18 (0x00040000) -#define MCF_ETPU_ECSSR_SS19 (0x00080000) -#define MCF_ETPU_ECSSR_SS20 (0x00100000) -#define MCF_ETPU_ECSSR_SS21 (0x00200000) -#define MCF_ETPU_ECSSR_SS22 (0x00400000) -#define MCF_ETPU_ECSSR_SS23 (0x00800000) -#define MCF_ETPU_ECSSR_SS24 (0x01000000) -#define MCF_ETPU_ECSSR_SS25 (0x02000000) -#define MCF_ETPU_ECSSR_SS26 (0x04000000) -#define MCF_ETPU_ECSSR_SS27 (0x08000000) -#define MCF_ETPU_ECSSR_SS28 (0x10000000) -#define MCF_ETPU_ECSSR_SS29 (0x20000000) -#define MCF_ETPU_ECSSR_SS30 (0x40000000) -#define MCF_ETPU_ECSSR_SS31 (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECnSCR */ -#define MCF_ETPU_ECnSCR_FM(x) (((x)&0x00000003)<<0) -#define MCF_ETPU_ECnSCR_OBE (0x00002000) -#define MCF_ETPU_ECnSCR_OPS (0x00004000) -#define MCF_ETPU_ECnSCR_IPS (0x00008000) -#define MCF_ETPU_ECnSCR_DTROS (0x00400000) -#define MCF_ETPU_ECnSCR_DTRS (0x00800000) -#define MCF_ETPU_ECnSCR_CIOS (0x40000000) -#define MCF_ETPU_ECnSCR_CIS (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECnCR */ -#define MCF_ETPU_ECnCR_CPBA(x) (((x)&0x000007FF)<<0) -#define MCF_ETPU_ECnCR_OPOL (0x00004000) -#define MCF_ETPU_ECnCR_ODIS (0x00008000) -#define MCF_ETPU_ECnCR_CFS(x) (((x)&0x0000001F)<<16) -#define MCF_ETPU_ECnCR_ETCS (0x01000000) -#define MCF_ETPU_ECnCR_CPR(x) (((x)&0x00000003)<<28) -#define MCF_ETPU_ECnCR_DTRE (0x40000000) -#define MCF_ETPU_ECnCR_CIE (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECnHSSR */ -#define MCF_ETPU_ECnHSSR_HSR(x) (((x)&0x00000007)<<0) - -/********************************************************************/ - -#endif /* __MCF523X_ETPU_H__ */ diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_fec.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_fec.h deleted file mode 100644 index 2b20a153f..000000000 --- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_fec.h +++ /dev/null @@ -1,208 +0,0 @@ -/* - * These files are taken from the MCF523X source code example package - * which is available on the Freescale website. Freescale explicitly - * grants the redistribution and modification of these source files. - * The complete licensing information is available in the file - * LICENSE_FREESCALE.TXT. - * - * File: mcf523x_fec.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_FEC_H__ -#define __MCF523X_FEC_H__ - -/********************************************************************* -* -* Fast Ethernet Controller (FEC) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_FEC_EIR (*(vuint32*)(void*)(&__IPSBAR[0x001004])) -#define MCF_FEC_EIMR (*(vuint32*)(void*)(&__IPSBAR[0x001008])) -#define MCF_FEC_RDAR (*(vuint32*)(void*)(&__IPSBAR[0x001010])) -#define MCF_FEC_TDAR (*(vuint32*)(void*)(&__IPSBAR[0x001014])) -#define MCF_FEC_ECR (*(vuint32*)(void*)(&__IPSBAR[0x001024])) -#define MCF_FEC_MMFR (*(vuint32*)(void*)(&__IPSBAR[0x001040])) -#define MCF_FEC_MSCR (*(vuint32*)(void*)(&__IPSBAR[0x001044])) -#define MCF_FEC_MIBC (*(vuint32*)(void*)(&__IPSBAR[0x001064])) -#define MCF_FEC_RCR (*(vuint32*)(void*)(&__IPSBAR[0x001084])) -#define MCF_FEC_TCR (*(vuint32*)(void*)(&__IPSBAR[0x0010C4])) -#define MCF_FEC_PALR (*(vuint32*)(void*)(&__IPSBAR[0x0010E4])) -#define MCF_FEC_PAUR (*(vuint32*)(void*)(&__IPSBAR[0x0010E8])) -#define MCF_FEC_OPD (*(vuint32*)(void*)(&__IPSBAR[0x0010EC])) -#define MCF_FEC_IAUR (*(vuint32*)(void*)(&__IPSBAR[0x001118])) -#define MCF_FEC_IALR (*(vuint32*)(void*)(&__IPSBAR[0x00111C])) -#define MCF_FEC_GAUR (*(vuint32*)(void*)(&__IPSBAR[0x001120])) -#define MCF_FEC_GALR (*(vuint32*)(void*)(&__IPSBAR[0x001124])) -#define MCF_FEC_TFWR (*(vuint32*)(void*)(&__IPSBAR[0x001144])) -#define MCF_FEC_FRBR (*(vuint32*)(void*)(&__IPSBAR[0x00114C])) -#define MCF_FEC_FRSR (*(vuint32*)(void*)(&__IPSBAR[0x001150])) -#define MCF_FEC_ERDSR (*(vuint32*)(void*)(&__IPSBAR[0x001180])) -#define MCF_FEC_ETDSR (*(vuint32*)(void*)(&__IPSBAR[0x001184])) -#define MCF_FEC_EMRBR (*(vuint32*)(void*)(&__IPSBAR[0x001188])) -#define MCF_FEC_RMON_T_DROP (*(vuint32*)(void*)(&__IPSBAR[0x001200])) -#define MCF_FEC_RMON_T_PACKETS (*(vuint32*)(void*)(&__IPSBAR[0x001204])) -#define MCF_FEC_RMON_T_BC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x001208])) -#define MCF_FEC_RMON_T_MC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x00120C])) -#define MCF_FEC_RMON_T_CRC_ALIGN (*(vuint32*)(void*)(&__IPSBAR[0x001210])) -#define MCF_FEC_RMON_T_UNDERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001214])) -#define MCF_FEC_RMON_T_OVERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001218])) -#define MCF_FEC_RMON_T_FRAG (*(vuint32*)(void*)(&__IPSBAR[0x00121C])) -#define MCF_FEC_RMON_T_JAB (*(vuint32*)(void*)(&__IPSBAR[0x001220])) -#define MCF_FEC_RMON_T_COL (*(vuint32*)(void*)(&__IPSBAR[0x001224])) -#define MCF_FEC_RMON_T_P64 (*(vuint32*)(void*)(&__IPSBAR[0x001228])) -#define MCF_FEC_RMON_T_P65TO127 (*(vuint32*)(void*)(&__IPSBAR[0x00122C])) -#define MCF_FEC_RMON_T_P128TO255 (*(vuint32*)(void*)(&__IPSBAR[0x001230])) -#define MCF_FEC_RMON_T_P256TO511 (*(vuint32*)(void*)(&__IPSBAR[0x001234])) -#define MCF_FEC_RMON_T_P512TO1023 (*(vuint32*)(void*)(&__IPSBAR[0x001238])) -#define MCF_FEC_RMON_T_P1024TO2047 (*(vuint32*)(void*)(&__IPSBAR[0x00123C])) -#define MCF_FEC_RMON_T_P_GTE2048 (*(vuint32*)(void*)(&__IPSBAR[0x001240])) -#define MCF_FEC_RMON_T_OCTETS (*(vuint32*)(void*)(&__IPSBAR[0x001244])) -#define MCF_FEC_IEEE_T_DROP (*(vuint32*)(void*)(&__IPSBAR[0x001248])) -#define MCF_FEC_IEEE_T_FRAME_OK (*(vuint32*)(void*)(&__IPSBAR[0x00124C])) -#define MCF_FEC_IEEE_T_1COL (*(vuint32*)(void*)(&__IPSBAR[0x001250])) -#define MCF_FEC_IEEE_T_MCOL (*(vuint32*)(void*)(&__IPSBAR[0x001254])) -#define MCF_FEC_IEEE_T_DEF (*(vuint32*)(void*)(&__IPSBAR[0x001258])) -#define MCF_FEC_IEEE_T_LCOL (*(vuint32*)(void*)(&__IPSBAR[0x00125C])) -#define MCF_FEC_IEEE_T_EXCOL (*(vuint32*)(void*)(&__IPSBAR[0x001260])) -#define MCF_FEC_IEEE_T_MACERR (*(vuint32*)(void*)(&__IPSBAR[0x001264])) -#define MCF_FEC_IEEE_T_CSERR (*(vuint32*)(void*)(&__IPSBAR[0x001268])) -#define MCF_FEC_IEEE_T_SQE (*(vuint32*)(void*)(&__IPSBAR[0x00126C])) -#define MCF_FEC_IEEE_T_FDXFC (*(vuint32*)(void*)(&__IPSBAR[0x001270])) -#define MCF_FEC_IEEE_T_OCTETS_OK (*(vuint32*)(void*)(&__IPSBAR[0x001274])) -#define MCF_FEC_RMON_R_PACKETS (*(vuint32*)(void*)(&__IPSBAR[0x001284])) -#define MCF_FEC_RMON_R_BC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x001288])) -#define MCF_FEC_RMON_R_MC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x00128C])) -#define MCF_FEC_RMON_R_CRC_ALIGN (*(vuint32*)(void*)(&__IPSBAR[0x001290])) -#define MCF_FEC_RMON_R_UNDERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001294])) -#define MCF_FEC_RMON_R_OVERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001298])) -#define MCF_FEC_RMON_R_FRAG (*(vuint32*)(void*)(&__IPSBAR[0x00129C])) -#define MCF_FEC_RMON_R_JAB (*(vuint32*)(void*)(&__IPSBAR[0x0012A0])) -#define MCF_FEC_RMON_R_RESVD_0 (*(vuint32*)(void*)(&__IPSBAR[0x0012A4])) -#define MCF_FEC_RMON_R_P64 (*(vuint32*)(void*)(&__IPSBAR[0x0012A8])) -#define MCF_FEC_RMON_R_P65TO127 (*(vuint32*)(void*)(&__IPSBAR[0x0012AC])) -#define MCF_FEC_RMON_R_P128TO255 (*(vuint32*)(void*)(&__IPSBAR[0x0012B0])) -#define MCF_FEC_RMON_R_P256TO511 (*(vuint32*)(void*)(&__IPSBAR[0x0012B4])) -#define MCF_FEC_RMON_R_512TO1023 (*(vuint32*)(void*)(&__IPSBAR[0x0012B8])) -#define MCF_FEC_RMON_R_P_GTE2048 (*(vuint32*)(void*)(&__IPSBAR[0x0012C0])) -#define MCF_FEC_RMON_R_1024TO2047 (*(vuint32*)(void*)(&__IPSBAR[0x0012BC])) -#define MCF_FEC_RMON_R_OCTETS (*(vuint32*)(void*)(&__IPSBAR[0x0012C4])) -#define MCF_FEC_IEEE_R_DROP (*(vuint32*)(void*)(&__IPSBAR[0x0012C8])) -#define MCF_FEC_IEEE_R_FRAME_OK (*(vuint32*)(void*)(&__IPSBAR[0x0012CC])) -#define MCF_FEC_IEEE_R_CRC (*(vuint32*)(void*)(&__IPSBAR[0x0012D0])) -#define MCF_FEC_IEEE_R_ALIGN (*(vuint32*)(void*)(&__IPSBAR[0x0012D4])) -#define MCF_FEC_IEEE_R_MACERR (*(vuint32*)(void*)(&__IPSBAR[0x0012D8])) -#define MCF_FEC_IEEE_R_FDXFC (*(vuint32*)(void*)(&__IPSBAR[0x0012DC])) -#define MCF_FEC_IEEE_R_OCTETS_OK (*(vuint32*)(void*)(&__IPSBAR[0x0012E0])) - -/* Bit definitions and macros for MCF_FEC_EIR */ -#define MCF_FEC_EIR_UN (0x00080000) -#define MCF_FEC_EIR_RL (0x00100000) -#define MCF_FEC_EIR_LC (0x00200000) -#define MCF_FEC_EIR_EBERR (0x00400000) -#define MCF_FEC_EIR_MII (0x00800000) -#define MCF_FEC_EIR_RXB (0x01000000) -#define MCF_FEC_EIR_RXF (0x02000000) -#define MCF_FEC_EIR_TXB (0x04000000) -#define MCF_FEC_EIR_TXF (0x08000000) -#define MCF_FEC_EIR_GRA (0x10000000) -#define MCF_FEC_EIR_BABT (0x20000000) -#define MCF_FEC_EIR_BABR (0x40000000) -#define MCF_FEC_EIR_HBERR (0x80000000) - -/* Bit definitions and macros for MCF_FEC_EIMR */ -#define MCF_FEC_EIMR_UN (0x00080000) -#define MCF_FEC_EIMR_RL (0x00100000) -#define MCF_FEC_EIMR_LC (0x00200000) -#define MCF_FEC_EIMR_EBERR (0x00400000) -#define MCF_FEC_EIMR_MII (0x00800000) -#define MCF_FEC_EIMR_RXB (0x01000000) -#define MCF_FEC_EIMR_RXF (0x02000000) -#define MCF_FEC_EIMR_TXB (0x04000000) -#define MCF_FEC_EIMR_TXF (0x08000000) -#define MCF_FEC_EIMR_GRA (0x10000000) -#define MCF_FEC_EIMR_BABT (0x20000000) -#define MCF_FEC_EIMR_BABR (0x40000000) -#define MCF_FEC_EIMR_HBERR (0x80000000) - -/* Bit definitions and macros for MCF_FEC_RDAR */ -#define MCF_FEC_RDAR_R_DES_ACTIVE (0x01000000) - -/* Bit definitions and macros for MCF_FEC_TDAR */ -#define MCF_FEC_TDAR_X_DES_ACTIVE (0x01000000) - -/* Bit definitions and macros for MCF_FEC_ECR */ -#define MCF_FEC_ECR_RESET (0x00000001) -#define MCF_FEC_ECR_ETHER_EN (0x00000002) - -/* Bit definitions and macros for MCF_FEC_MMFR */ -#define MCF_FEC_MMFR_DATA(x) (((x)&0x0000FFFF)<<0) -#define MCF_FEC_MMFR_TA(x) (((x)&0x00000003)<<16) -#define MCF_FEC_MMFR_RA(x) (((x)&0x0000001F)<<18) -#define MCF_FEC_MMFR_PA(x) (((x)&0x0000001F)<<23) -#define MCF_FEC_MMFR_OP(x) (((x)&0x00000003)<<28) -#define MCF_FEC_MMFR_ST(x) (((x)&0x00000003)<<30) -#define MCF_FEC_MMFR_ST_01 (0x40000000) -#define MCF_FEC_MMFR_OP_READ (0x20000000) -#define MCF_FEC_MMFR_OP_WRITE (0x10000000) -#define MCF_FEC_MMFR_TA_10 (0x00020000) - - -/* Bit definitions and macros for MCF_FEC_MSCR */ -#define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x0000003F)<<1) -#define MCF_FEC_MSCR_DIS_PREAMBLE (0x00000080) - -/* Bit definitions and macros for MCF_FEC_MIBC */ -#define MCF_FEC_MIBC_MIB_IDLE (0x40000000) -#define MCF_FEC_MIBC_MIB_DISABLE (0x80000000) - -/* Bit definitions and macros for MCF_FEC_RCR */ -#define MCF_FEC_RCR_LOOP (0x00000001) -#define MCF_FEC_RCR_DRT (0x00000002) -#define MCF_FEC_RCR_MII_MODE (0x00000004) -#define MCF_FEC_RCR_PROM (0x00000008) -#define MCF_FEC_RCR_BC_REJ (0x00000010) -#define MCF_FEC_RCR_FCE (0x00000020) -#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x000007FF)<<16) - -/* Bit definitions and macros for MCF_FEC_TCR */ -#define MCF_FEC_TCR_GTS (0x00000001) -#define MCF_FEC_TCR_HBC (0x00000002) -#define MCF_FEC_TCR_FDEN (0x00000004) -#define MCF_FEC_TCR_TFC_PAUSE (0x00000008) -#define MCF_FEC_TCR_RFC_PAUSE (0x00000010) - -/* Bit definitions and macros for MCF_FEC_PAUR */ -#define MCF_FEC_PAUR_TYPE(x) (((x)&0x0000FFFF)<<0) -#define MCF_FEC_PAUR_PADDR2(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_FEC_OPD */ -#define MCF_FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0) -#define MCF_FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_FEC_TFWR */ -#define MCF_FEC_TFWR_X_WMRK(x) (((x)&0x00000003)<<0) - -/* Bit definitions and macros for MCF_FEC_FRBR */ -#define MCF_FEC_FRBR_R_BOUND(x) (((x)&0x000000FF)<<2) - -/* Bit definitions and macros for MCF_FEC_FRSR */ -#define MCF_FEC_FRSR_R_FSTART(x) (((x)&0x000000FF)<<2) - -/* Bit definitions and macros for MCF_FEC_ERDSR */ -#define MCF_FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2) - -/* Bit definitions and macros for MCF_FEC_ETDSR */ -#define MCF_FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2) - -/* Bit definitions and macros for MCF_FEC_EMRBR */ -#define MCF_FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x0000007F)<<4) - -/********************************************************************/ - -#endif /* __MCF523X_FEC_H__ */ diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_fmpll.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_fmpll.h deleted file mode 100644 index d9dc941d4..000000000 --- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_fmpll.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * These files are taken from the MCF523X source code example package - * which is available on the Freescale website. Freescale explicitly - * grants the redistribution and modification of these source files. - * The complete licensing information is available in the file - * LICENSE_FREESCALE.TXT. - * - * File: mcf523x_fmpll.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_FMPLL_H__ -#define __MCF523X_FMPLL_H__ - -/********************************************************************* -* -* Frequency Modulated Phase Locked Loop (FMPLL) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_FMPLL_SYNCR (*(vuint32*)(void*)(&__IPSBAR[0x120000])) -#define MCF_FMPLL_SYNSR (*(vuint32*)(void*)(&__IPSBAR[0x120004])) - -/* Bit definitions and macros for MCF_FMPLL_SYNCR */ -#define MCF_FMPLL_SYNCR_EXP(x) (((x)&0x000003FF)<<0) -#define MCF_FMPLL_SYNCR_DEPTH(x) (((x)&0x00000003)<<10) -#define MCF_FMPLL_SYNCR_RATE (0x00001000) -#define MCF_FMPLL_SYNCR_LOCIRQ (0x00002000) -#define MCF_FMPLL_SYNCR_LOLIRQ (0x00004000) -#define MCF_FMPLL_SYNCR_DISCLK (0x00008000) -#define MCF_FMPLL_SYNCR_LOCRE (0x00010000) -#define MCF_FMPLL_SYNCR_LOLRE (0x00020000) -#define MCF_FMPLL_SYNCR_LOCEN (0x00040000) -#define MCF_FMPLL_SYNCR_RFD(x) (((x)&0x00000007)<<19) -#define MCF_FMPLL_SYNCR_MFD(x) (((x)&0x00000007)<<24) - -/* Bit definitions and macros for MCF_FMPLL_SYNSR */ -#define MCF_FMPLL_SYNSR_CALPASS (0x00000001) -#define MCF_FMPLL_SYNSR_CALDONE (0x00000002) -#define MCF_FMPLL_SYNSR_LOCF (0x00000004) -#define MCF_FMPLL_SYNSR_LOCK (0x00000008) -#define MCF_FMPLL_SYNSR_LOCKS (0x00000010) -#define MCF_FMPLL_SYNSR_PLLREF (0x00000020) -#define MCF_FMPLL_SYNSR_PLLSEL (0x00000040) -#define MCF_FMPLL_SYNSR_MODE (0x00000080) -#define MCF_FMPLL_SYNSR_LOC (0x00000100) -#define MCF_FMPLL_SYNSR_LOLF (0x00000200) - -/********************************************************************/ - -#endif /* __MCF523X_FMPLL_H__ */ diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_gpio.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_gpio.h deleted file mode 100644 index 455ac850d..000000000 --- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_gpio.h +++ /dev/null @@ -1,676 +0,0 @@ -/* - * These files are taken from the MCF523X source code example package - * which is available on the Freescale website. Freescale explicitly - * grants the redistribution and modification of these source files. - * The complete licensing information is available in the file - * LICENSE_FREESCALE.TXT. - * - * File: mcf523x_gpio.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_GPIO_H__ -#define __MCF523X_GPIO_H__ - -/********************************************************************* -* -* General Purpose I/O (GPIO) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_GPIO_PODR_ADDR (*(vuint8 *)(void*)(&__IPSBAR[0x100000])) -#define MCF_GPIO_PODR_DATAH (*(vuint8 *)(void*)(&__IPSBAR[0x100001])) -#define MCF_GPIO_PODR_DATAL (*(vuint8 *)(void*)(&__IPSBAR[0x100002])) -#define MCF_GPIO_PODR_BUSCTL (*(vuint8 *)(void*)(&__IPSBAR[0x100003])) -#define MCF_GPIO_PODR_BS (*(vuint8 *)(void*)(&__IPSBAR[0x100004])) -#define MCF_GPIO_PODR_CS (*(vuint8 *)(void*)(&__IPSBAR[0x100005])) -#define MCF_GPIO_PODR_SDRAM (*(vuint8 *)(void*)(&__IPSBAR[0x100006])) -#define MCF_GPIO_PODR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100007])) -#define MCF_GPIO_PODR_UARTH (*(vuint8 *)(void*)(&__IPSBAR[0x100008])) -#define MCF_GPIO_PODR_UARTL (*(vuint8 *)(void*)(&__IPSBAR[0x100009])) -#define MCF_GPIO_PODR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x10000A])) -#define MCF_GPIO_PODR_TIMER (*(vuint8 *)(void*)(&__IPSBAR[0x10000B])) -#define MCF_GPIO_PODR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x10000C])) -#define MCF_GPIO_PDDR_APDDR (*(vuint8 *)(void*)(&__IPSBAR[0x100010])) -#define MCF_GPIO_PDDR_DATAH (*(vuint8 *)(void*)(&__IPSBAR[0x100011])) -#define MCF_GPIO_PDDR_DATAL (*(vuint8 *)(void*)(&__IPSBAR[0x100012])) -#define MCF_GPIO_PDDR_BUSCTL (*(vuint8 *)(void*)(&__IPSBAR[0x100013])) -#define MCF_GPIO_PDDR_BS (*(vuint8 *)(void*)(&__IPSBAR[0x100014])) -#define MCF_GPIO_PDDR_CS (*(vuint8 *)(void*)(&__IPSBAR[0x100015])) -#define MCF_GPIO_PDDR_SDRAM (*(vuint8 *)(void*)(&__IPSBAR[0x100016])) -#define MCF_GPIO_PDDR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100017])) -#define MCF_GPIO_PDDR_UARTH (*(vuint8 *)(void*)(&__IPSBAR[0x100018])) -#define MCF_GPIO_PDDR_UARTL (*(vuint8 *)(void*)(&__IPSBAR[0x100019])) -#define MCF_GPIO_PDDR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x10001A])) -#define MCF_GPIO_PDDR_TIMER (*(vuint8 *)(void*)(&__IPSBAR[0x10001B])) -#define MCF_GPIO_PDDR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x10001C])) -#define MCF_GPIO_PPDSDR_ADDR (*(vuint8 *)(void*)(&__IPSBAR[0x100020])) -#define MCF_GPIO_PPDSDR_DATAH (*(vuint8 *)(void*)(&__IPSBAR[0x100021])) -#define MCF_GPIO_PPDSDR_DATAL (*(vuint8 *)(void*)(&__IPSBAR[0x100022])) -#define MCF_GPIO_PPDSDR_BUSCTL (*(vuint8 *)(void*)(&__IPSBAR[0x100023])) -#define MCF_GPIO_PPDSDR_BS (*(vuint8 *)(void*)(&__IPSBAR[0x100024])) -#define MCF_GPIO_PPDSDR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100027])) -#define MCF_GPIO_PPDSDR_CS (*(vuint8 *)(void*)(&__IPSBAR[0x100025])) -#define MCF_GPIO_PPDSDR_SDRAM (*(vuint8 *)(void*)(&__IPSBAR[0x100026])) -#define MCF_GPIO_PPDSDR_UARTH (*(vuint8 *)(void*)(&__IPSBAR[0x100028])) -#define MCF_GPIO_PPDSDR_UARTL (*(vuint8 *)(void*)(&__IPSBAR[0x100029])) -#define MCF_GPIO_PPDSDR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x10002A])) -#define MCF_GPIO_PPDSDR_TIMER (*(vuint8 *)(void*)(&__IPSBAR[0x10002B])) -#define MCF_GPIO_PPDSDR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x10002C])) -#define MCF_GPIO_PCLRR_ADDR (*(vuint8 *)(void*)(&__IPSBAR[0x100030])) -#define MCF_GPIO_PCLRR_DATAH (*(vuint8 *)(void*)(&__IPSBAR[0x100031])) -#define MCF_GPIO_PCLRR_DATAL (*(vuint8 *)(void*)(&__IPSBAR[0x100032])) -#define MCF_GPIO_PCLRR_BUSCTL (*(vuint8 *)(void*)(&__IPSBAR[0x100033])) -#define MCF_GPIO_PCLRR_BS (*(vuint8 *)(void*)(&__IPSBAR[0x100034])) -#define MCF_GPIO_PCLRR_CS (*(vuint8 *)(void*)(&__IPSBAR[0x100035])) -#define MCF_GPIO_PCLRR_SDRAM (*(vuint8 *)(void*)(&__IPSBAR[0x100036])) -#define MCF_GPIO_PCLRR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100037])) -#define MCF_GPIO_PCLRR_UARTH (*(vuint8 *)(void*)(&__IPSBAR[0x100038])) -#define MCF_GPIO_PCLRR_UARTL (*(vuint8 *)(void*)(&__IPSBAR[0x100039])) -#define MCF_GPIO_PCLRR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x10003A])) -#define MCF_GPIO_PCLRR_TIMER (*(vuint8 *)(void*)(&__IPSBAR[0x10003B])) -#define MCF_GPIO_PCLRR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x10003C])) -#define MCF_GPIO_PAR_AD (*(vuint8 *)(void*)(&__IPSBAR[0x100040])) -#define MCF_GPIO_PAR_BUSCTL (*(vuint16*)(void*)(&__IPSBAR[0x100042])) -#define MCF_GPIO_PAR_BS (*(vuint8 *)(void*)(&__IPSBAR[0x100044])) -#define MCF_GPIO_PAR_CS (*(vuint8 *)(void*)(&__IPSBAR[0x100045])) -#define MCF_GPIO_PAR_SDRAM (*(vuint8 *)(void*)(&__IPSBAR[0x100046])) -#define MCF_GPIO_PAR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100047])) -#define MCF_GPIO_PAR_UART (*(vuint16*)(void*)(&__IPSBAR[0x100048])) -#define MCF_GPIO_PAR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x10004A])) -#define MCF_GPIO_PAR_TIMER (*(vuint16*)(void*)(&__IPSBAR[0x10004C])) -#define MCF_GPIO_PAR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x10004E])) -#define MCF_GPIO_DSCR_EIM (*(vuint8 *)(void*)(&__IPSBAR[0x100050])) -#define MCF_GPIO_DSCR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x100051])) -#define MCF_GPIO_DSCR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100052])) -#define MCF_GPIO_DSCR_UART (*(vuint8 *)(void*)(&__IPSBAR[0x100053])) -#define MCF_GPIO_DSCR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x100054])) -#define MCF_GPIO_DSCR_TIMER (*(vuint8 *)(void*)(&__IPSBAR[0x100055])) - -/* Bit definitions and macros for MCF_GPIO_PODR_ADDR */ -#define MCF_GPIO_PODR_ADDR_PODR_ADDR5 (0x20) -#define MCF_GPIO_PODR_ADDR_PODR_ADDR6 (0x40) -#define MCF_GPIO_PODR_ADDR_PODR_ADDR7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_DATAH */ -#define MCF_GPIO_PODR_DATAH_PODR_DATAH0 (0x01) -#define MCF_GPIO_PODR_DATAH_PODR_DATAH1 (0x02) -#define MCF_GPIO_PODR_DATAH_PODR_DATAH2 (0x04) -#define MCF_GPIO_PODR_DATAH_PODR_DATAH3 (0x08) -#define MCF_GPIO_PODR_DATAH_PODR_DATAH4 (0x10) -#define MCF_GPIO_PODR_DATAH_PODR_DATAH5 (0x20) -#define MCF_GPIO_PODR_DATAH_PODR_DATAH6 (0x40) -#define MCF_GPIO_PODR_DATAH_PODR_DATAH7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_DATAL */ -#define MCF_GPIO_PODR_DATAL_PODR_DATAL0 (0x01) -#define MCF_GPIO_PODR_DATAL_PODR_DATAL1 (0x02) -#define MCF_GPIO_PODR_DATAL_PODR_DATAL2 (0x04) -#define MCF_GPIO_PODR_DATAL_PODR_DATAL3 (0x08) -#define MCF_GPIO_PODR_DATAL_PODR_DATAL4 (0x10) -#define MCF_GPIO_PODR_DATAL_PODR_DATAL5 (0x20) -#define MCF_GPIO_PODR_DATAL_PODR_DATAL6 (0x40) -#define MCF_GPIO_PODR_DATAL_PODR_DATAL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_BUSCTL */ -#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL0 (0x01) -#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL1 (0x02) -#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL2 (0x04) -#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL3 (0x08) -#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL4 (0x10) -#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL5 (0x20) -#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL6 (0x40) -#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_BS */ -#define MCF_GPIO_PODR_BS_PODR_BS0 (0x01) -#define MCF_GPIO_PODR_BS_PODR_BS1 (0x02) -#define MCF_GPIO_PODR_BS_PODR_BS2 (0x04) -#define MCF_GPIO_PODR_BS_PODR_BS3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PODR_CS */ -#define MCF_GPIO_PODR_CS_PODR_CS1 (0x02) -#define MCF_GPIO_PODR_CS_PODR_CS2 (0x04) -#define MCF_GPIO_PODR_CS_PODR_CS3 (0x08) -#define MCF_GPIO_PODR_CS_PODR_CS4 (0x10) -#define MCF_GPIO_PODR_CS_PODR_CS5 (0x20) -#define MCF_GPIO_PODR_CS_PODR_CS6 (0x40) -#define MCF_GPIO_PODR_CS_PODR_CS7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_SDRAM */ -#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM0 (0x01) -#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM1 (0x02) -#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM2 (0x04) -#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM3 (0x08) -#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM4 (0x10) -#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */ -#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x01) -#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x02) -#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x04) -#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PODR_UARTH */ -#define MCF_GPIO_PODR_UARTH_PODR_UARTH0 (0x01) -#define MCF_GPIO_PODR_UARTH_PODR_UARTH1 (0x02) - -/* Bit definitions and macros for MCF_GPIO_PODR_UARTL */ -#define MCF_GPIO_PODR_UARTL_PODR_UARTL0 (0x01) -#define MCF_GPIO_PODR_UARTL_PODR_UARTL1 (0x02) -#define MCF_GPIO_PODR_UARTL_PODR_UARTL2 (0x04) -#define MCF_GPIO_PODR_UARTL_PODR_UARTL3 (0x08) -#define MCF_GPIO_PODR_UARTL_PODR_UARTL4 (0x10) -#define MCF_GPIO_PODR_UARTL_PODR_UARTL5 (0x20) -#define MCF_GPIO_PODR_UARTL_PODR_UARTL6 (0x40) -#define MCF_GPIO_PODR_UARTL_PODR_UARTL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_QSPI */ -#define MCF_GPIO_PODR_QSPI_PODR_QSPI0 (0x01) -#define MCF_GPIO_PODR_QSPI_PODR_QSPI1 (0x02) -#define MCF_GPIO_PODR_QSPI_PODR_QSPI2 (0x04) -#define MCF_GPIO_PODR_QSPI_PODR_QSPI3 (0x08) -#define MCF_GPIO_PODR_QSPI_PODR_QSPI4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PODR_TIMER */ -#define MCF_GPIO_PODR_TIMER_PODR_TIMER0 (0x01) -#define MCF_GPIO_PODR_TIMER_PODR_TIMER1 (0x02) -#define MCF_GPIO_PODR_TIMER_PODR_TIMER2 (0x04) -#define MCF_GPIO_PODR_TIMER_PODR_TIMER3 (0x08) -#define MCF_GPIO_PODR_TIMER_PODR_TIMER4 (0x10) -#define MCF_GPIO_PODR_TIMER_PODR_TIMER5 (0x20) -#define MCF_GPIO_PODR_TIMER_PODR_TIMER6 (0x40) -#define MCF_GPIO_PODR_TIMER_PODR_TIMER7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_ETPU */ -#define MCF_GPIO_PODR_ETPU_PODR_ETPU0 (0x01) -#define MCF_GPIO_PODR_ETPU_PODR_ETPU1 (0x02) -#define MCF_GPIO_PODR_ETPU_PODR_ETPU2 (0x04) - -/* Bit definitions and macros for MCF_GPIO_PDDR_APDDR */ -#define MCF_GPIO_PDDR_APDDR_PDDR_APDDR5 (0x20) -#define MCF_GPIO_PDDR_APDDR_PDDR_APDDR6 (0x40) -#define MCF_GPIO_PDDR_APDDR_PDDR_APDDR7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_DATAH */ -#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH0 (0x01) -#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH1 (0x02) -#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH2 (0x04) -#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH3 (0x08) -#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH4 (0x10) -#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH5 (0x20) -#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH6 (0x40) -#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_DATAL */ -#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL0 (0x01) -#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL1 (0x02) -#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL2 (0x04) -#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL3 (0x08) -#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL4 (0x10) -#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL5 (0x20) -#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL6 (0x40) -#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_BUSCTL */ -#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL0 (0x01) -#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL1 (0x02) -#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL2 (0x04) -#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL3 (0x08) -#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL4 (0x10) -#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL5 (0x20) -#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL6 (0x40) -#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_BS */ -#define MCF_GPIO_PDDR_BS_PDDR_BS0 (0x01) -#define MCF_GPIO_PDDR_BS_PDDR_BS3(x) (((x)&0x07)<<1) - -/* Bit definitions and macros for MCF_GPIO_PDDR_CS */ -#define MCF_GPIO_PDDR_CS_PDDR_CS1 (0x02) -#define MCF_GPIO_PDDR_CS_PDDR_CS2 (0x04) -#define MCF_GPIO_PDDR_CS_PDDR_CS3 (0x08) -#define MCF_GPIO_PDDR_CS_PDDR_CS4 (0x10) -#define MCF_GPIO_PDDR_CS_PDDR_CS5 (0x20) -#define MCF_GPIO_PDDR_CS_PDDR_CS6 (0x40) -#define MCF_GPIO_PDDR_CS_PDDR_CS7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_SDRAM */ -#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM0 (0x01) -#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM1 (0x02) -#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM2 (0x04) -#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM3 (0x08) -#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM4 (0x10) -#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */ -#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x01) -#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x02) -#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x04) -#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PDDR_UARTH */ -#define MCF_GPIO_PDDR_UARTH_PDDR_UARTH0 (0x01) -#define MCF_GPIO_PDDR_UARTH_PDDR_UARTH1 (0x02) - -/* Bit definitions and macros for MCF_GPIO_PDDR_UARTL */ -#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL0 (0x01) -#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL1 (0x02) -#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL2 (0x04) -#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL3 (0x08) -#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL4 (0x10) -#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL5 (0x20) -#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL6 (0x40) -#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_QSPI */ -#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI0 (0x01) -#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI1 (0x02) -#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI2 (0x04) -#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI3 (0x08) -#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PDDR_TIMER */ -#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER0 (0x01) -#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER1 (0x02) -#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER2 (0x04) -#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER3 (0x08) -#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER4 (0x10) -#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER5 (0x20) -#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER6 (0x40) -#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_ETPU */ -#define MCF_GPIO_PDDR_ETPU_PDDR_ETPU0 (0x01) -#define MCF_GPIO_PDDR_ETPU_PDDR_ETPU1 (0x02) -#define MCF_GPIO_PDDR_ETPU_PDDR_ETPU2 (0x04) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_ADDR */ -#define MCF_GPIO_PPDSDR_ADDR_PPDSDR_ADDR5 (0x20) -#define MCF_GPIO_PPDSDR_ADDR_PPDSDR_ADDR6 (0x40) -#define MCF_GPIO_PPDSDR_ADDR_PPDSDR_ADDR7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_DATAH */ -#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH0 (0x01) -#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH1 (0x02) -#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH2 (0x04) -#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH3 (0x08) -#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH4 (0x10) -#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH5 (0x20) -#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH6 (0x40) -#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_DATAL */ -#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL0 (0x01) -#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL1 (0x02) -#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL2 (0x04) -#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL3 (0x08) -#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL4 (0x10) -#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL5 (0x20) -#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL6 (0x40) -#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_BUSCTL */ -#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL0 (0x01) -#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL1 (0x02) -#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL2 (0x04) -#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL3 (0x08) -#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL4 (0x10) -#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL5 (0x20) -#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL6 (0x40) -#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_BS */ -#define MCF_GPIO_PPDSDR_BS_PPDSDR_BS0 (0x01) -#define MCF_GPIO_PPDSDR_BS_PPDSDR_BS1 (0x02) -#define MCF_GPIO_PPDSDR_BS_PPDSDR_BS2 (0x04) -#define MCF_GPIO_PPDSDR_BS_PPDSDR_BS3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */ -#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x01) -#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x02) -#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x04) -#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_CS */ -#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS1 (0x02) -#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS2 (0x04) -#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS3 (0x08) -#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS4 (0x10) -#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS5 (0x20) -#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS6 (0x40) -#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_SDRAM */ -#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM0 (0x01) -#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM1 (0x02) -#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM2 (0x04) -#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM3 (0x08) -#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM4 (0x10) -#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM5 (0x20) -#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM6 (0x40) -#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_UARTH */ -#define MCF_GPIO_PPDSDR_UARTH_PPDSDR_UARTH0 (0x01) -#define MCF_GPIO_PPDSDR_UARTH_PPDSDR_UARTH1 (0x02) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_UARTL */ -#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL0 (0x01) -#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL1 (0x02) -#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL2 (0x04) -#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL3 (0x08) -#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL4 (0x10) -#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL5 (0x20) -#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL6 (0x40) -#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_QSPI */ -#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI0 (0x01) -#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI1 (0x02) -#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI2 (0x04) -#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI3 (0x08) -#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_TIMER */ -#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER0 (0x01) -#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER1 (0x02) -#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER2 (0x04) -#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER3 (0x08) -#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER4 (0x10) -#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER5 (0x20) -#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER6 (0x40) -#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_ETPU */ -#define MCF_GPIO_PPDSDR_ETPU_PPDSDR_ETPU0 (0x01) -#define MCF_GPIO_PPDSDR_ETPU_PPDSDR_ETPU1 (0x02) -#define MCF_GPIO_PPDSDR_ETPU_PPDSDR_ETPU2 (0x04) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_ADDR */ -#define MCF_GPIO_PCLRR_ADDR_PCLRR_ADDR5 (0x20) -#define MCF_GPIO_PCLRR_ADDR_PCLRR_ADDR6 (0x40) -#define MCF_GPIO_PCLRR_ADDR_PCLRR_ADDR7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_DATAH */ -#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH0 (0x01) -#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH1 (0x02) -#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH2 (0x04) -#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH3 (0x08) -#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH4 (0x10) -#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH5 (0x20) -#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH6 (0x40) -#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_DATAL */ -#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL0 (0x01) -#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL1 (0x02) -#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL2 (0x04) -#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL3 (0x08) -#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL4 (0x10) -#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL5 (0x20) -#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL6 (0x40) -#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_BUSCTL */ -#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL0 (0x01) -#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL1 (0x02) -#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL2 (0x04) -#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL3 (0x08) -#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL4 (0x10) -#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL5 (0x20) -#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL6 (0x40) -#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_BS */ -#define MCF_GPIO_PCLRR_BS_PCLRR_BS0 (0x01) -#define MCF_GPIO_PCLRR_BS_PCLRR_BS1 (0x02) -#define MCF_GPIO_PCLRR_BS_PCLRR_BS2 (0x04) -#define MCF_GPIO_PCLRR_BS_PCLRR_BS3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_CS */ -#define MCF_GPIO_PCLRR_CS_PCLRR_CS1 (0x02) -#define MCF_GPIO_PCLRR_CS_PCLRR_CS2 (0x04) -#define MCF_GPIO_PCLRR_CS_PCLRR_CS3 (0x08) -#define MCF_GPIO_PCLRR_CS_PCLRR_CS4 (0x10) -#define MCF_GPIO_PCLRR_CS_PCLRR_CS5 (0x20) -#define MCF_GPIO_PCLRR_CS_PCLRR_CS6 (0x40) -#define MCF_GPIO_PCLRR_CS_PCLRR_CS7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_SDRAM */ -#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM0 (0x01) -#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM1 (0x02) -#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM2 (0x04) -#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM3 (0x08) -#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM4 (0x10) -#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */ -#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x01) -#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x02) -#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2 (0x04) -#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_UARTH */ -#define MCF_GPIO_PCLRR_UARTH_PCLRR_UARTH0 (0x01) -#define MCF_GPIO_PCLRR_UARTH_PCLRR_UARTH1 (0x02) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_UARTL */ -#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL0 (0x01) -#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL1 (0x02) -#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL2 (0x04) -#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL3 (0x08) -#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL4 (0x10) -#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL5 (0x20) -#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL6 (0x40) -#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_QSPI */ -#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI0 (0x01) -#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI1 (0x02) -#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI2 (0x04) -#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI3 (0x08) -#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_TIMER */ -#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER0 (0x01) -#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER1 (0x02) -#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER2 (0x04) -#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER3 (0x08) -#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER4 (0x10) -#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER5 (0x20) -#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER6 (0x40) -#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_ETPU */ -#define MCF_GPIO_PCLRR_ETPU_PCLRR_ETPU0 (0x01) -#define MCF_GPIO_PCLRR_ETPU_PCLRR_ETPU1 (0x02) -#define MCF_GPIO_PCLRR_ETPU_PCLRR_ETPU2 (0x04) - -/* Bit definitions and macros for MCF_GPIO_PAR_AD */ -#define MCF_GPIO_PAR_AD_PAR_DATAL (0x01) -#define MCF_GPIO_PAR_AD_PAR_ADDR21 (0x20) -#define MCF_GPIO_PAR_AD_PAR_ADDR22 (0x40) -#define MCF_GPIO_PAR_AD_PAR_ADDR23 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PAR_BUSCTL */ -#define MCF_GPIO_PAR_BUSCTL_PAR_TIP(x) (((x)&0x0003)<<0) -#define MCF_GPIO_PAR_BUSCTL_PAR_TS(x) (((x)&0x0003)<<2) -#define MCF_GPIO_PAR_BUSCTL_PAR_TSIZ0 (0x0010) -#define MCF_GPIO_PAR_BUSCTL_PAR_TSIZ1 (0x0040) -#define MCF_GPIO_PAR_BUSCTL_PAR_RWB (0x0100) -#define MCF_GPIO_PAR_BUSCTL_PAR_TEA(x) (((x)&0x0003)<<10) -#define MCF_GPIO_PAR_BUSCTL_PAR_TA (0x1000) -#define MCF_GPIO_PAR_BUSCTL_PAR_OE (0x4000) -#define MCF_GPIO_PAR_BUSCTL_PAR_TEA_GPIO (0x0000) -#define MCF_GPIO_PAR_BUSCTL_PAR_TEA_DMA (0x0800) -#define MCF_GPIO_PAR_BUSCTL_PAR_TEA_TEA (0x0C00) -#define MCF_GPIO_PAR_BUSCTL_PAR_TS_GPIO (0x0000) -#define MCF_GPIO_PAR_BUSCTL_PAR_TS_DMA (0x0080) -#define MCF_GPIO_PAR_BUSCTL_PAR_TS_TS (0x00C0) -#define MCF_GPIO_PAR_BUSCTL_PAR_TIP_GPIO (0x0000) -#define MCF_GPIO_PAR_BUSCTL_PAR_TIP_DMA (0x0002) -#define MCF_GPIO_PAR_BUSCTL_PAR_TIP_TEA (0x0003) - -/* Bit definitions and macros for MCF_GPIO_PAR_BS */ -#define MCF_GPIO_PAR_BS_PAR_BS0 (0x01) -#define MCF_GPIO_PAR_BS_PAR_BS1 (0x02) -#define MCF_GPIO_PAR_BS_PAR_BS2 (0x04) -#define MCF_GPIO_PAR_BS_PAR_BS3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PAR_CS */ -#define MCF_GPIO_PAR_CS_PAR_CS1 (0x02) -#define MCF_GPIO_PAR_CS_PAR_CS2 (0x04) -#define MCF_GPIO_PAR_CS_PAR_CS3 (0x08) -#define MCF_GPIO_PAR_CS_PAR_CS4 (0x10) -#define MCF_GPIO_PAR_CS_PAR_CS5 (0x20) -#define MCF_GPIO_PAR_CS_PAR_CS6 (0x40) -#define MCF_GPIO_PAR_CS_PAR_CS7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PAR_SDRAM */ -#define MCF_GPIO_PAR_SDRAM_PAR_SDCS0 (0x01) -#define MCF_GPIO_PAR_SDRAM_PAR_SDCS1 (0x02) -#define MCF_GPIO_PAR_SDRAM_PAR_SCKE (0x04) -#define MCF_GPIO_PAR_SDRAM_PAR_SRAS (0x08) -#define MCF_GPIO_PAR_SDRAM_PAR_SCAS (0x10) -#define MCF_GPIO_PAR_SDRAM_PAR_SDWE (0x20) -#define MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(x) (((x)&0x03)<<6) - -/* Bit definitions and macros for MCF_GPIO_PAR_FECI2C */ -#define MCF_GPIO_PAR_FECI2C_PAR_SDA(x) (((x)&0x03)<<0) -#define MCF_GPIO_PAR_FECI2C_PAR_SCL(x) (((x)&0x03)<<2) -#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO(x) (((x)&0x03)<<4) -#define MCF_GPIO_PAR_FECI2C_PAR_EMDC(x) (((x)&0x03)<<6) -#define MCF_GPIO_PAR_FECI2C_PAR_EMDC_GPIO (0x00) -#define MCF_GPIO_PAR_FECI2C_PAR_EMDC_UART2 (0x40) -#define MCF_GPIO_PAR_FECI2C_PAR_EMDC_I2C (0x80) -#define MCF_GPIO_PAR_FECI2C_PAR_EMDC_FEC (0xC0) -#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO_GPIO (0x00) -#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO_UART2 (0x10) -#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO_I2C (0x20) -#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO_FEC (0x30) -#define MCF_GPIO_PAR_FECI2C_PAR_SCL_GPIO (0x00) -#define MCF_GPIO_PAR_FECI2C_PAR_SCL_FLEX (0x08) -#define MCF_GPIO_PAR_FECI2C_PAR_SCL_I2C (0x0C) -#define MCF_GPIO_PAR_FECI2C_PAR_SDA_GPIO (0x00) -#define MCF_GPIO_PAR_FECI2C_PAR_SDA_FLEX (0x02) -#define MCF_GPIO_PAR_FECI2C_PAR_SDA_I2C (0x03) - -/* Bit definitions and macros for MCF_GPIO_PAR_UART */ -#define MCF_GPIO_PAR_UART_PAR_U0RTS (0x0001) -#define MCF_GPIO_PAR_UART_PAR_U0CTS (0x0002) -#define MCF_GPIO_PAR_UART_PAR_U0TXD (0x0004) -#define MCF_GPIO_PAR_UART_PAR_U0RXD (0x0008) -#define MCF_GPIO_PAR_UART_PAR_U1RTS(x) (((x)&0x0003)<<4) -#define MCF_GPIO_PAR_UART_PAR_U1CTS(x) (((x)&0x0003)<<6) -#define MCF_GPIO_PAR_UART_PAR_U1TXD(x) (((x)&0x0003)<<8) -#define MCF_GPIO_PAR_UART_PAR_U1RXD(x) (((x)&0x0003)<<10) -#define MCF_GPIO_PAR_UART_PAR_U2TXD (0x1000) -#define MCF_GPIO_PAR_UART_PAR_U2RXD (0x2000) -#define MCF_GPIO_PAR_UART_PAR_CAN1EN (0x4000) -#define MCF_GPIO_PAR_UART_PAR_DREQ2 (0x8000) -#define MCF_GPIO_PAR_UART_PAR_U1RXD_GPIO (0x0000) -#define MCF_GPIO_PAR_UART_PAR_U1RXD_FLEX (0x0800) -#define MCF_GPIO_PAR_UART_PAR_U1RXD_UART1 (0x0C00) -#define MCF_GPIO_PAR_UART_PAR_U1TXD_GPIO (0x0000) -#define MCF_GPIO_PAR_UART_PAR_U1TXD_FLEX (0x0200) -#define MCF_GPIO_PAR_UART_PAR_U1TXD_UART1 (0x0300) -#define MCF_GPIO_PAR_UART_PAR_U1CTS_GPIO (0x0000) -#define MCF_GPIO_PAR_UART_PAR_U1CTS_UART2 (0x0080) -#define MCF_GPIO_PAR_UART_PAR_U1CTS_UART1 (0x00C0) -#define MCF_GPIO_PAR_UART_PAR_U1RTS_GPIO (0x0000) -#define MCF_GPIO_PAR_UART_PAR_U1RTS_UART2 (0x0020) -#define MCF_GPIO_PAR_UART_PAR_U1RTS_UART1 (0x0030) - -/* Bit definitions and macros for MCF_GPIO_PAR_QSPI */ -#define MCF_GPIO_PAR_QSPI_PAR_SCK(x) (((x)&0x03)<<0) -#define MCF_GPIO_PAR_QSPI_PAR_DOUT (0x04) -#define MCF_GPIO_PAR_QSPI_PAR_DIN(x) (((x)&0x03)<<3) -#define MCF_GPIO_PAR_QSPI_PAR_PCS0 (0x20) -#define MCF_GPIO_PAR_QSPI_PAR_PCS1(x) (((x)&0x03)<<6) -#define MCF_GPIO_PAR_QSPI_PAR_PCS1_GPIO (0x00) -#define MCF_GPIO_PAR_QSPI_PAR_PCS1_SDRAMC (0x80) -#define MCF_GPIO_PAR_QSPI_PAR_PCS1_QSPI (0xC0) -#define MCF_GPIO_PAR_QSPI_PAR_DIN_GPIO (0x00) -#define MCF_GPIO_PAR_QSPI_PAR_DIN_I2C (0x10) -#define MCF_GPIO_PAR_QSPI_PAR_DIN_QSPI (0x1C) -#define MCF_GPIO_PAR_QSPI_PAR_SCK_GPIO (0x00) -#define MCF_GPIO_PAR_QSPI_PAR_SCK_I2C (0x02) -#define MCF_GPIO_PAR_QSPI_PAR_SCK_QSPI (0x03) - -/* Bit definitions and macros for MCF_GPIO_PAR_TIMER */ -#define MCF_GPIO_PAR_TIMER_PAR_T0OUT(x) (((x)&0x0003)<<0) -#define MCF_GPIO_PAR_TIMER_PAR_T1OUT(x) (((x)&0x0003)<<2) -#define MCF_GPIO_PAR_TIMER_PAR_T2OUT(x) (((x)&0x0003)<<4) -#define MCF_GPIO_PAR_TIMER_PAR_T3OUT(x) (((x)&0x0003)<<6) -#define MCF_GPIO_PAR_TIMER_PAR_T0IN(x) (((x)&0x0003)<<8) -#define MCF_GPIO_PAR_TIMER_PAR_T1IN(x) (((x)&0x0003)<<10) -#define MCF_GPIO_PAR_TIMER_PAR_T2IN(x) (((x)&0x0003)<<12) -#define MCF_GPIO_PAR_TIMER_PAR_T3IN(x) (((x)&0x0003)<<14) -#define MCF_GPIO_PAR_TIMER_PAR_T3IN_GPIO (0x0000) -#define MCF_GPIO_PAR_TIMER_PAR_T3IN_QSPI (0x4000) -#define MCF_GPIO_PAR_TIMER_PAR_T3IN_UART2 (0x8000) -#define MCF_GPIO_PAR_TIMER_PAR_T3IN_T3IN (0xC000) -#define MCF_GPIO_PAR_TIMER_PAR_T2IN_GPIO (0x0000) -#define MCF_GPIO_PAR_TIMER_PAR_T2IN_T2OUT (0x1000) -#define MCF_GPIO_PAR_TIMER_PAR_T2IN_DMA (0x2000) -#define MCF_GPIO_PAR_TIMER_PAR_T2IN_T2IN (0x3000) -#define MCF_GPIO_PAR_TIMER_PAR_T1IN_GPIO (0x0000) -#define MCF_GPIO_PAR_TIMER_PAR_T1IN_T1OUT (0x0400) -#define MCF_GPIO_PAR_TIMER_PAR_T1IN_DMA (0x0800) -#define MCF_GPIO_PAR_TIMER_PAR_T1IN_T1IN (0x0C00) -#define MCF_GPIO_PAR_TIMER_PAR_T0IN_GPIO (0x0000) -#define MCF_GPIO_PAR_TIMER_PAR_T0IN_DMA (0x0200) -#define MCF_GPIO_PAR_TIMER_PAR_T0IN_T0IN (0x0300) -#define MCF_GPIO_PAR_TIMER_PAR_T3OUT_GPIO (0x0000) -#define MCF_GPIO_PAR_TIMER_PAR_T3OUT_QSPI (0x0040) -#define MCF_GPIO_PAR_TIMER_PAR_T3OUT_UART2 (0x0080) -#define MCF_GPIO_PAR_TIMER_PAR_T3OUT_T3OUT (0x00C0) -#define MCF_GPIO_PAR_TIMER_PAR_T2OUT_GPIO (0x0000) -#define MCF_GPIO_PAR_TIMER_PAR_T2OUT_DMA (0x0020) -#define MCF_GPIO_PAR_TIMER_PAR_T2OUT_T2OUT (0x0030) -#define MCF_GPIO_PAR_TIMER_PAR_T1OUT_GPIO (0x0000) -#define MCF_GPIO_PAR_TIMER_PAR_T1OUT_DMA (0x0008) -#define MCF_GPIO_PAR_TIMER_PAR_T1OUT_T1OUT (0x000C) -#define MCF_GPIO_PAR_TIMER_PAR_T0OUT_GPIO (0x0000) -#define MCF_GPIO_PAR_TIMER_PAR_T0OUT_DMA (0x0002) -#define MCF_GPIO_PAR_TIMER_PAR_T0OUT_T0OUT (0x0003) - -/* Bit definitions and macros for MCF_GPIO_PAR_ETPU */ -#define MCF_GPIO_PAR_ETPU_PAR_LTPU_ODIS (0x01) -#define MCF_GPIO_PAR_ETPU_PAR_UTPU_ODIS (0x02) -#define MCF_GPIO_PAR_ETPU_PAR_TCRCLK (0x04) - -/* Bit definitions and macros for MCF_GPIO_DSCR_EIM */ -#define MCF_GPIO_DSCR_EIM_DSCR_EIM0 (0x01) -#define MCF_GPIO_DSCR_EIM_DSCR_EIM1 (0x10) - -/* Bit definitions and macros for MCF_GPIO_DSCR_ETPU */ -#define MCF_GPIO_DSCR_ETPU_DSCR_ETPU_7_0 (0x01) -#define MCF_GPIO_DSCR_ETPU_DSCR_ETPU_15_8 (0x04) -#define MCF_GPIO_DSCR_ETPU_DSCR_ETPU_23_16 (0x10) -#define MCF_GPIO_DSCR_ETPU_DSCR_ETPU_31_24 (0x40) - -/* Bit definitions and macros for MCF_GPIO_DSCR_FECI2C */ -#define MCF_GPIO_DSCR_FECI2C_DSCR_I2C (0x01) -#define MCF_GPIO_DSCR_FECI2C_DSCR_FEC (0x10) - -/* Bit definitions and macros for MCF_GPIO_DSCR_UART */ -#define MCF_GPIO_DSCR_UART_DSCR_UART0 (0x01) -#define MCF_GPIO_DSCR_UART_DSCR_UART1 (0x04) -#define MCF_GPIO_DSCR_UART_DSCR_UART2 (0x10) -#define MCF_GPIO_DSCR_UART_DSCR_IRQ (0x40) - -/* Bit definitions and macros for MCF_GPIO_DSCR_QSPI */ -#define MCF_GPIO_DSCR_QSPI_DSCR_QSPI (0x01) - -/* Bit definitions and macros for MCF_GPIO_DSCR_TIMER */ -#define MCF_GPIO_DSCR_TIMER_DSCR_TIMER (0x01) - -/********************************************************************/ - -#endif /* __MCF523X_GPIO_H__ */ diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_i2c.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_i2c.h deleted file mode 100644 index ee4665507..000000000 --- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_i2c.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * These files are taken from the MCF523X source code example package - * which is available on the Freescale website. Freescale explicitly - * grants the redistribution and modification of these source files. - * The complete licensing information is available in the file - * LICENSE_FREESCALE.TXT. - * - * File: mcf523x_i2c.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_I2C_H__ -#define __MCF523X_I2C_H__ - -/********************************************************************* -* -* I2C Module (I2C) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_I2C_I2AR (*(vuint8 *)(void*)(&__IPSBAR[0x000300])) -#define MCF_I2C_I2FDR (*(vuint8 *)(void*)(&__IPSBAR[0x000304])) -#define MCF_I2C_I2CR (*(vuint8 *)(void*)(&__IPSBAR[0x000308])) -#define MCF_I2C_I2SR (*(vuint8 *)(void*)(&__IPSBAR[0x00030C])) -#define MCF_I2C_I2DR (*(vuint8 *)(void*)(&__IPSBAR[0x000310])) -#define MCF_I2C_I2ICR (*(vuint8 *)(void*)(&__IPSBAR[0x000320])) - -/* Bit definitions and macros for MCF_I2C_I2AR */ -#define MCF_I2C_I2AR_ADR(x) (((x)&0x7F)<<1) - -/* Bit definitions and macros for MCF_I2C_I2FDR */ -#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0) - -/* Bit definitions and macros for MCF_I2C_I2CR */ -#define MCF_I2C_I2CR_RSTA (0x04) -#define MCF_I2C_I2CR_TXAK (0x08) -#define MCF_I2C_I2CR_MTX (0x10) -#define MCF_I2C_I2CR_MSTA (0x20) -#define MCF_I2C_I2CR_IIEN (0x40) -#define MCF_I2C_I2CR_IEN (0x80) - -/* Bit definitions and macros for MCF_I2C_I2SR */ -#define MCF_I2C_I2SR_RXAK (0x01) -#define MCF_I2C_I2SR_IIF (0x02) -#define MCF_I2C_I2SR_SRW (0x04) -#define MCF_I2C_I2SR_IAL (0x10) -#define MCF_I2C_I2SR_IBB (0x20) -#define MCF_I2C_I2SR_IAAS (0x40) -#define MCF_I2C_I2SR_ICF (0x80) - -/* Bit definitions and macros for MCF_I2C_I2ICR */ -#define MCF_I2C_I2ICR_IE (0x01) -#define MCF_I2C_I2ICR_RE (0x02) -#define MCF_I2C_I2ICR_TE (0x04) -#define MCF_I2C_I2ICR_BNBE (0x08) - -/********************************************************************/ - -#endif /* __MCF523X_I2C_H__ */ diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_intc0.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_intc0.h deleted file mode 100644 index 7d19e9863..000000000 --- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_intc0.h +++ /dev/null @@ -1,323 +0,0 @@ -/* - * These files are taken from the MCF523X source code example package - * which is available on the Freescale website. Freescale explicitly - * grants the redistribution and modification of these source files. - * The complete licensing information is available in the file - * LICENSE_FREESCALE.TXT. - * - * File: mcf523x_intc0.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_INTC0_H__ -#define __MCF523X_INTC0_H__ - -/********************************************************************* -* -* Interrupt Controller 0 (INTC0) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_INTC0_IPRH (*(vuint32*)(void*)(&__IPSBAR[0x000C00])) -#define MCF_INTC0_IPRL (*(vuint32*)(void*)(&__IPSBAR[0x000C04])) -#define MCF_INTC0_IMRH (*(vuint32*)(void*)(&__IPSBAR[0x000C08])) -#define MCF_INTC0_IMRL (*(vuint32*)(void*)(&__IPSBAR[0x000C0C])) -#define MCF_INTC0_INTFRCH (*(vuint32*)(void*)(&__IPSBAR[0x000C10])) -#define MCF_INTC0_INTFRCL (*(vuint32*)(void*)(&__IPSBAR[0x000C14])) -#define MCF_INTC0_IRLR (*(vuint8 *)(void*)(&__IPSBAR[0x000C18])) -#define MCF_INTC0_IACKLPR (*(vuint8 *)(void*)(&__IPSBAR[0x000C19])) -#define MCF_INTC0_ICR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000C40])) -#define MCF_INTC0_ICR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000C41])) -#define MCF_INTC0_ICR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000C42])) -#define MCF_INTC0_ICR3 (*(vuint8 *)(void*)(&__IPSBAR[0x000C43])) -#define MCF_INTC0_ICR4 (*(vuint8 *)(void*)(&__IPSBAR[0x000C44])) -#define MCF_INTC0_ICR5 (*(vuint8 *)(void*)(&__IPSBAR[0x000C45])) -#define MCF_INTC0_ICR6 (*(vuint8 *)(void*)(&__IPSBAR[0x000C46])) -#define MCF_INTC0_ICR7 (*(vuint8 *)(void*)(&__IPSBAR[0x000C47])) -#define MCF_INTC0_ICR8 (*(vuint8 *)(void*)(&__IPSBAR[0x000C48])) -#define MCF_INTC0_ICR9 (*(vuint8 *)(void*)(&__IPSBAR[0x000C49])) -#define MCF_INTC0_ICR10 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4A])) -#define MCF_INTC0_ICR11 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4B])) -#define MCF_INTC0_ICR12 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4C])) -#define MCF_INTC0_ICR13 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4D])) -#define MCF_INTC0_ICR14 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4E])) -#define MCF_INTC0_ICR15 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4F])) -#define MCF_INTC0_ICR16 (*(vuint8 *)(void*)(&__IPSBAR[0x000C50])) -#define MCF_INTC0_ICR17 (*(vuint8 *)(void*)(&__IPSBAR[0x000C51])) -#define MCF_INTC0_ICR18 (*(vuint8 *)(void*)(&__IPSBAR[0x000C52])) -#define MCF_INTC0_ICR19 (*(vuint8 *)(void*)(&__IPSBAR[0x000C53])) -#define MCF_INTC0_ICR20 (*(vuint8 *)(void*)(&__IPSBAR[0x000C54])) -#define MCF_INTC0_ICR21 (*(vuint8 *)(void*)(&__IPSBAR[0x000C55])) -#define MCF_INTC0_ICR22 (*(vuint8 *)(void*)(&__IPSBAR[0x000C56])) -#define MCF_INTC0_ICR23 (*(vuint8 *)(void*)(&__IPSBAR[0x000C57])) -#define MCF_INTC0_ICR24 (*(vuint8 *)(void*)(&__IPSBAR[0x000C58])) -#define MCF_INTC0_ICR25 (*(vuint8 *)(void*)(&__IPSBAR[0x000C59])) -#define MCF_INTC0_ICR26 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5A])) -#define MCF_INTC0_ICR27 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5B])) -#define MCF_INTC0_ICR28 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5C])) -#define MCF_INTC0_ICR29 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5D])) -#define MCF_INTC0_ICR30 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5E])) -#define MCF_INTC0_ICR31 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5F])) -#define MCF_INTC0_ICR32 (*(vuint8 *)(void*)(&__IPSBAR[0x000C60])) -#define MCF_INTC0_ICR33 (*(vuint8 *)(void*)(&__IPSBAR[0x000C61])) -#define MCF_INTC0_ICR34 (*(vuint8 *)(void*)(&__IPSBAR[0x000C62])) -#define MCF_INTC0_ICR35 (*(vuint8 *)(void*)(&__IPSBAR[0x000C63])) -#define MCF_INTC0_ICR36 (*(vuint8 *)(void*)(&__IPSBAR[0x000C64])) -#define MCF_INTC0_ICR37 (*(vuint8 *)(void*)(&__IPSBAR[0x000C65])) -#define MCF_INTC0_ICR38 (*(vuint8 *)(void*)(&__IPSBAR[0x000C66])) -#define MCF_INTC0_ICR39 (*(vuint8 *)(void*)(&__IPSBAR[0x000C67])) -#define MCF_INTC0_ICR40 (*(vuint8 *)(void*)(&__IPSBAR[0x000C68])) -#define MCF_INTC0_ICR41 (*(vuint8 *)(void*)(&__IPSBAR[0x000C69])) -#define MCF_INTC0_ICR42 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6A])) -#define MCF_INTC0_ICR43 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6B])) -#define MCF_INTC0_ICR44 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6C])) -#define MCF_INTC0_ICR45 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6D])) -#define MCF_INTC0_ICR46 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6E])) -#define MCF_INTC0_ICR47 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6F])) -#define MCF_INTC0_ICR48 (*(vuint8 *)(void*)(&__IPSBAR[0x000C70])) -#define MCF_INTC0_ICR49 (*(vuint8 *)(void*)(&__IPSBAR[0x000C71])) -#define MCF_INTC0_ICR50 (*(vuint8 *)(void*)(&__IPSBAR[0x000C72])) -#define MCF_INTC0_ICR51 (*(vuint8 *)(void*)(&__IPSBAR[0x000C73])) -#define MCF_INTC0_ICR52 (*(vuint8 *)(void*)(&__IPSBAR[0x000C74])) -#define MCF_INTC0_ICR53 (*(vuint8 *)(void*)(&__IPSBAR[0x000C75])) -#define MCF_INTC0_ICR54 (*(vuint8 *)(void*)(&__IPSBAR[0x000C76])) -#define MCF_INTC0_ICR55 (*(vuint8 *)(void*)(&__IPSBAR[0x000C77])) -#define MCF_INTC0_ICR56 (*(vuint8 *)(void*)(&__IPSBAR[0x000C78])) -#define MCF_INTC0_ICR57 (*(vuint8 *)(void*)(&__IPSBAR[0x000C79])) -#define MCF_INTC0_ICR58 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7A])) -#define MCF_INTC0_ICR59 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7B])) -#define MCF_INTC0_ICR60 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7C])) -#define MCF_INTC0_ICR61 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7D])) -#define MCF_INTC0_ICR62 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7E])) -#define MCF_INTC0_ICR63 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7F])) -#define MCF_INTC0_ICRn(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000C40+((x)*0x001)])) -#define MCF_INTC0_SWIACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CE0])) -#define MCF_INTC0_L1IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CE4])) -#define MCF_INTC0_L2IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CE8])) -#define MCF_INTC0_L3IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CEC])) -#define MCF_INTC0_L4IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CF0])) -#define MCF_INTC0_L5IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CF4])) -#define MCF_INTC0_L6IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CF8])) -#define MCF_INTC0_L7IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CFC])) -#define MCF_INTC0_LnIACK(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000CE4+((x)*0x004)])) - -/* Bit definitions and macros for MCF_INTC0_IPRH */ -#define MCF_INTC0_IPRH_INT32 (0x00000001) -#define MCF_INTC0_IPRH_INT33 (0x00000002) -#define MCF_INTC0_IPRH_INT34 (0x00000004) -#define MCF_INTC0_IPRH_INT35 (0x00000008) -#define MCF_INTC0_IPRH_INT36 (0x00000010) -#define MCF_INTC0_IPRH_INT37 (0x00000020) -#define MCF_INTC0_IPRH_INT38 (0x00000040) -#define MCF_INTC0_IPRH_INT39 (0x00000080) -#define MCF_INTC0_IPRH_INT40 (0x00000100) -#define MCF_INTC0_IPRH_INT41 (0x00000200) -#define MCF_INTC0_IPRH_INT42 (0x00000400) -#define MCF_INTC0_IPRH_INT43 (0x00000800) -#define MCF_INTC0_IPRH_INT44 (0x00001000) -#define MCF_INTC0_IPRH_INT45 (0x00002000) -#define MCF_INTC0_IPRH_INT46 (0x00004000) -#define MCF_INTC0_IPRH_INT47 (0x00008000) -#define MCF_INTC0_IPRH_INT48 (0x00010000) -#define MCF_INTC0_IPRH_INT49 (0x00020000) -#define MCF_INTC0_IPRH_INT50 (0x00040000) -#define MCF_INTC0_IPRH_INT51 (0x00080000) -#define MCF_INTC0_IPRH_INT52 (0x00100000) -#define MCF_INTC0_IPRH_INT53 (0x00200000) -#define MCF_INTC0_IPRH_INT54 (0x00400000) -#define MCF_INTC0_IPRH_INT55 (0x00800000) -#define MCF_INTC0_IPRH_INT56 (0x01000000) -#define MCF_INTC0_IPRH_INT57 (0x02000000) -#define MCF_INTC0_IPRH_INT58 (0x04000000) -#define MCF_INTC0_IPRH_INT59 (0x08000000) -#define MCF_INTC0_IPRH_INT60 (0x10000000) -#define MCF_INTC0_IPRH_INT61 (0x20000000) -#define MCF_INTC0_IPRH_INT62 (0x40000000) -#define MCF_INTC0_IPRH_INT63 (0x80000000) - -/* Bit definitions and macros for MCF_INTC0_IPRL */ -#define MCF_INTC0_IPRL_INT1 (0x00000002) -#define MCF_INTC0_IPRL_INT2 (0x00000004) -#define MCF_INTC0_IPRL_INT3 (0x00000008) -#define MCF_INTC0_IPRL_INT4 (0x00000010) -#define MCF_INTC0_IPRL_INT5 (0x00000020) -#define MCF_INTC0_IPRL_INT6 (0x00000040) -#define MCF_INTC0_IPRL_INT7 (0x00000080) -#define MCF_INTC0_IPRL_INT8 (0x00000100) -#define MCF_INTC0_IPRL_INT9 (0x00000200) -#define MCF_INTC0_IPRL_INT10 (0x00000400) -#define MCF_INTC0_IPRL_INT11 (0x00000800) -#define MCF_INTC0_IPRL_INT12 (0x00001000) -#define MCF_INTC0_IPRL_INT13 (0x00002000) -#define MCF_INTC0_IPRL_INT14 (0x00004000) -#define MCF_INTC0_IPRL_INT15 (0x00008000) -#define MCF_INTC0_IPRL_INT16 (0x00010000) -#define MCF_INTC0_IPRL_INT17 (0x00020000) -#define MCF_INTC0_IPRL_INT18 (0x00040000) -#define MCF_INTC0_IPRL_INT19 (0x00080000) -#define MCF_INTC0_IPRL_INT20 (0x00100000) -#define MCF_INTC0_IPRL_INT21 (0x00200000) -#define MCF_INTC0_IPRL_INT22 (0x00400000) -#define MCF_INTC0_IPRL_INT23 (0x00800000) -#define MCF_INTC0_IPRL_INT24 (0x01000000) -#define MCF_INTC0_IPRL_INT25 (0x02000000) -#define MCF_INTC0_IPRL_INT26 (0x04000000) -#define MCF_INTC0_IPRL_INT27 (0x08000000) -#define MCF_INTC0_IPRL_INT28 (0x10000000) -#define MCF_INTC0_IPRL_INT29 (0x20000000) -#define MCF_INTC0_IPRL_INT30 (0x40000000) -#define MCF_INTC0_IPRL_INT31 (0x80000000) - -/* Bit definitions and macros for MCF_INTC0_IMRH */ -#define MCF_INTC0_IMRH_INT_MASK32 (0x00000001) -#define MCF_INTC0_IMRH_INT_MASK33 (0x00000002) -#define MCF_INTC0_IMRH_INT_MASK34 (0x00000004) -#define MCF_INTC0_IMRH_INT_MASK35 (0x00000008) -#define MCF_INTC0_IMRH_INT_MASK36 (0x00000010) -#define MCF_INTC0_IMRH_INT_MASK37 (0x00000020) -#define MCF_INTC0_IMRH_INT_MASK38 (0x00000040) -#define MCF_INTC0_IMRH_INT_MASK39 (0x00000080) -#define MCF_INTC0_IMRH_INT_MASK40 (0x00000100) -#define MCF_INTC0_IMRH_INT_MASK41 (0x00000200) -#define MCF_INTC0_IMRH_INT_MASK42 (0x00000400) -#define MCF_INTC0_IMRH_INT_MASK43 (0x00000800) -#define MCF_INTC0_IMRH_INT_MASK44 (0x00001000) -#define MCF_INTC0_IMRH_INT_MASK45 (0x00002000) -#define MCF_INTC0_IMRH_INT_MASK46 (0x00004000) -#define MCF_INTC0_IMRH_INT_MASK47 (0x00008000) -#define MCF_INTC0_IMRH_INT_MASK48 (0x00010000) -#define MCF_INTC0_IMRH_INT_MASK49 (0x00020000) -#define MCF_INTC0_IMRH_INT_MASK50 (0x00040000) -#define MCF_INTC0_IMRH_INT_MASK51 (0x00080000) -#define MCF_INTC0_IMRH_INT_MASK52 (0x00100000) -#define MCF_INTC0_IMRH_INT_MASK53 (0x00200000) -#define MCF_INTC0_IMRH_INT_MASK54 (0x00400000) -#define MCF_INTC0_IMRH_INT_MASK55 (0x00800000) -#define MCF_INTC0_IMRH_INT_MASK56 (0x01000000) -#define MCF_INTC0_IMRH_INT_MASK57 (0x02000000) -#define MCF_INTC0_IMRH_INT_MASK58 (0x04000000) -#define MCF_INTC0_IMRH_INT_MASK59 (0x08000000) -#define MCF_INTC0_IMRH_INT_MASK60 (0x10000000) -#define MCF_INTC0_IMRH_INT_MASK61 (0x20000000) -#define MCF_INTC0_IMRH_INT_MASK62 (0x40000000) -#define MCF_INTC0_IMRH_INT_MASK63 (0x80000000) - -/* Bit definitions and macros for MCF_INTC0_IMRL */ -#define MCF_INTC0_IMRL_MASKALL (0x00000001) -#define MCF_INTC0_IMRL_INT_MASK1 (0x00000002) -#define MCF_INTC0_IMRL_INT_MASK2 (0x00000004) -#define MCF_INTC0_IMRL_INT_MASK3 (0x00000008) -#define MCF_INTC0_IMRL_INT_MASK4 (0x00000010) -#define MCF_INTC0_IMRL_INT_MASK5 (0x00000020) -#define MCF_INTC0_IMRL_INT_MASK6 (0x00000040) -#define MCF_INTC0_IMRL_INT_MASK7 (0x00000080) -#define MCF_INTC0_IMRL_INT_MASK8 (0x00000100) -#define MCF_INTC0_IMRL_INT_MASK9 (0x00000200) -#define MCF_INTC0_IMRL_INT_MASK10 (0x00000400) -#define MCF_INTC0_IMRL_INT_MASK11 (0x00000800) -#define MCF_INTC0_IMRL_INT_MASK12 (0x00001000) -#define MCF_INTC0_IMRL_INT_MASK13 (0x00002000) -#define MCF_INTC0_IMRL_INT_MASK14 (0x00004000) -#define MCF_INTC0_IMRL_INT_MASK15 (0x00008000) -#define MCF_INTC0_IMRL_INT_MASK16 (0x00010000) -#define MCF_INTC0_IMRL_INT_MASK17 (0x00020000) -#define MCF_INTC0_IMRL_INT_MASK18 (0x00040000) -#define MCF_INTC0_IMRL_INT_MASK19 (0x00080000) -#define MCF_INTC0_IMRL_INT_MASK20 (0x00100000) -#define MCF_INTC0_IMRL_INT_MASK21 (0x00200000) -#define MCF_INTC0_IMRL_INT_MASK22 (0x00400000) -#define MCF_INTC0_IMRL_INT_MASK23 (0x00800000) -#define MCF_INTC0_IMRL_INT_MASK24 (0x01000000) -#define MCF_INTC0_IMRL_INT_MASK25 (0x02000000) -#define MCF_INTC0_IMRL_INT_MASK26 (0x04000000) -#define MCF_INTC0_IMRL_INT_MASK27 (0x08000000) -#define MCF_INTC0_IMRL_INT_MASK28 (0x10000000) -#define MCF_INTC0_IMRL_INT_MASK29 (0x20000000) -#define MCF_INTC0_IMRL_INT_MASK30 (0x40000000) -#define MCF_INTC0_IMRL_INT_MASK31 (0x80000000) - -/* Bit definitions and macros for MCF_INTC0_INTFRCH */ -#define MCF_INTC0_INTFRCH_INTFRC32 (0x00000001) -#define MCF_INTC0_INTFRCH_INTFRC33 (0x00000002) -#define MCF_INTC0_INTFRCH_INTFRC34 (0x00000004) -#define MCF_INTC0_INTFRCH_INTFRC35 (0x00000008) -#define MCF_INTC0_INTFRCH_INTFRC36 (0x00000010) -#define MCF_INTC0_INTFRCH_INTFRC37 (0x00000020) -#define MCF_INTC0_INTFRCH_INTFRC38 (0x00000040) -#define MCF_INTC0_INTFRCH_INTFRC39 (0x00000080) -#define MCF_INTC0_INTFRCH_INTFRC40 (0x00000100) -#define MCF_INTC0_INTFRCH_INTFRC41 (0x00000200) -#define MCF_INTC0_INTFRCH_INTFRC42 (0x00000400) -#define MCF_INTC0_INTFRCH_INTFRC43 (0x00000800) -#define MCF_INTC0_INTFRCH_INTFRC44 (0x00001000) -#define MCF_INTC0_INTFRCH_INTFRC45 (0x00002000) -#define MCF_INTC0_INTFRCH_INTFRC46 (0x00004000) -#define MCF_INTC0_INTFRCH_INTFRC47 (0x00008000) -#define MCF_INTC0_INTFRCH_INTFRC48 (0x00010000) -#define MCF_INTC0_INTFRCH_INTFRC49 (0x00020000) -#define MCF_INTC0_INTFRCH_INTFRC50 (0x00040000) -#define MCF_INTC0_INTFRCH_INTFRC51 (0x00080000) -#define MCF_INTC0_INTFRCH_INTFRC52 (0x00100000) -#define MCF_INTC0_INTFRCH_INTFRC53 (0x00200000) -#define MCF_INTC0_INTFRCH_INTFRC54 (0x00400000) -#define MCF_INTC0_INTFRCH_INTFRC55 (0x00800000) -#define MCF_INTC0_INTFRCH_INTFRC56 (0x01000000) -#define MCF_INTC0_INTFRCH_INTFRC57 (0x02000000) -#define MCF_INTC0_INTFRCH_INTFRC58 (0x04000000) -#define MCF_INTC0_INTFRCH_INTFRC59 (0x08000000) -#define MCF_INTC0_INTFRCH_INTFRC60 (0x10000000) -#define MCF_INTC0_INTFRCH_INTFRC61 (0x20000000) -#define MCF_INTC0_INTFRCH_INTFRC62 (0x40000000) -#define MCF_INTC0_INTFRCH_INTFRC63 (0x80000000) - -/* Bit definitions and macros for MCF_INTC0_INTFRCL */ -#define MCF_INTC0_INTFRCL_INTFRC1 (0x00000002) -#define MCF_INTC0_INTFRCL_INTFRC2 (0x00000004) -#define MCF_INTC0_INTFRCL_INTFRC3 (0x00000008) -#define MCF_INTC0_INTFRCL_INTFRC4 (0x00000010) -#define MCF_INTC0_INTFRCL_INTFRC5 (0x00000020) -#define MCF_INTC0_INTFRCL_INT6 (0x00000040) -#define MCF_INTC0_INTFRCL_INT7 (0x00000080) -#define MCF_INTC0_INTFRCL_INT8 (0x00000100) -#define MCF_INTC0_INTFRCL_INT9 (0x00000200) -#define MCF_INTC0_INTFRCL_INT10 (0x00000400) -#define MCF_INTC0_INTFRCL_INTFRC11 (0x00000800) -#define MCF_INTC0_INTFRCL_INTFRC12 (0x00001000) -#define MCF_INTC0_INTFRCL_INTFRC13 (0x00002000) -#define MCF_INTC0_INTFRCL_INTFRC14 (0x00004000) -#define MCF_INTC0_INTFRCL_INT15 (0x00008000) -#define MCF_INTC0_INTFRCL_INTFRC16 (0x00010000) -#define MCF_INTC0_INTFRCL_INTFRC17 (0x00020000) -#define MCF_INTC0_INTFRCL_INTFRC18 (0x00040000) -#define MCF_INTC0_INTFRCL_INTFRC19 (0x00080000) -#define MCF_INTC0_INTFRCL_INTFRC20 (0x00100000) -#define MCF_INTC0_INTFRCL_INTFRC21 (0x00200000) -#define MCF_INTC0_INTFRCL_INTFRC22 (0x00400000) -#define MCF_INTC0_INTFRCL_INTFRC23 (0x00800000) -#define MCF_INTC0_INTFRCL_INTFRC24 (0x01000000) -#define MCF_INTC0_INTFRCL_INTFRC25 (0x02000000) -#define MCF_INTC0_INTFRCL_INTFRC26 (0x04000000) -#define MCF_INTC0_INTFRCL_INTFRC27 (0x08000000) -#define MCF_INTC0_INTFRCL_INTFRC28 (0x10000000) -#define MCF_INTC0_INTFRCL_INTFRC29 (0x20000000) -#define MCF_INTC0_INTFRCL_INTFRC30 (0x40000000) -#define MCF_INTC0_INTFRCL_INTFRC31 (0x80000000) - -/* Bit definitions and macros for MCF_INTC0_IRLR */ -#define MCF_INTC0_IRLR_IRQ(x) (((x)&0x7F)<<1) - -/* Bit definitions and macros for MCF_INTC0_IACKLPR */ -#define MCF_INTC0_IACKLPR_PRI(x) (((x)&0x0F)<<0) -#define MCF_INTC0_IACKLPR_LEVEL(x) (((x)&0x07)<<4) - -/* Bit definitions and macros for MCF_INTC0_ICRn */ -#define MCF_INTC0_ICRn_IP(x) (((x)&0x07)<<0) -#define MCF_INTC0_ICRn_IL(x) (((x)&0x07)<<3) - -/********************************************************************/ - -#endif /* __MCF523X_INTC0_H__ */ diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_intc1.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_intc1.h deleted file mode 100644 index 45613eaaf..000000000 --- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_intc1.h +++ /dev/null @@ -1,323 +0,0 @@ -/* - * These files are taken from the MCF523X source code example package - * which is available on the Freescale website. Freescale explicitly - * grants the redistribution and modification of these source files. - * The complete licensing information is available in the file - * LICENSE_FREESCALE.TXT. - * - * File: mcf523x_intc1.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_INTC1_H__ -#define __MCF523X_INTC1_H__ - -/********************************************************************* -* -* Interrupt Controller 1 (INTC1) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_INTC1_IPRH (*(vuint32*)(void*)(&__IPSBAR[0x000D00])) -#define MCF_INTC1_IPRL (*(vuint32*)(void*)(&__IPSBAR[0x000D04])) -#define MCF_INTC1_IMRH (*(vuint32*)(void*)(&__IPSBAR[0x000D08])) -#define MCF_INTC1_IMRL (*(vuint32*)(void*)(&__IPSBAR[0x000D0C])) -#define MCF_INTC1_INTFRCH (*(vuint32*)(void*)(&__IPSBAR[0x000D10])) -#define MCF_INTC1_INTFRCL (*(vuint32*)(void*)(&__IPSBAR[0x000D14])) -#define MCF_INTC1_IRLR (*(vuint8 *)(void*)(&__IPSBAR[0x000D18])) -#define MCF_INTC1_IACKLPR (*(vuint8 *)(void*)(&__IPSBAR[0x000D19])) -#define MCF_INTC1_ICR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000D40])) -#define MCF_INTC1_ICR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000D41])) -#define MCF_INTC1_ICR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000D42])) -#define MCF_INTC1_ICR3 (*(vuint8 *)(void*)(&__IPSBAR[0x000D43])) -#define MCF_INTC1_ICR4 (*(vuint8 *)(void*)(&__IPSBAR[0x000D44])) -#define MCF_INTC1_ICR5 (*(vuint8 *)(void*)(&__IPSBAR[0x000D45])) -#define MCF_INTC1_ICR6 (*(vuint8 *)(void*)(&__IPSBAR[0x000D46])) -#define MCF_INTC1_ICR7 (*(vuint8 *)(void*)(&__IPSBAR[0x000D47])) -#define MCF_INTC1_ICR8 (*(vuint8 *)(void*)(&__IPSBAR[0x000D48])) -#define MCF_INTC1_ICR9 (*(vuint8 *)(void*)(&__IPSBAR[0x000D49])) -#define MCF_INTC1_ICR10 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4A])) -#define MCF_INTC1_ICR11 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4B])) -#define MCF_INTC1_ICR12 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4C])) -#define MCF_INTC1_ICR13 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4D])) -#define MCF_INTC1_ICR14 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4E])) -#define MCF_INTC1_ICR15 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4F])) -#define MCF_INTC1_ICR16 (*(vuint8 *)(void*)(&__IPSBAR[0x000D50])) -#define MCF_INTC1_ICR17 (*(vuint8 *)(void*)(&__IPSBAR[0x000D51])) -#define MCF_INTC1_ICR18 (*(vuint8 *)(void*)(&__IPSBAR[0x000D52])) -#define MCF_INTC1_ICR19 (*(vuint8 *)(void*)(&__IPSBAR[0x000D53])) -#define MCF_INTC1_ICR20 (*(vuint8 *)(void*)(&__IPSBAR[0x000D54])) -#define MCF_INTC1_ICR21 (*(vuint8 *)(void*)(&__IPSBAR[0x000D55])) -#define MCF_INTC1_ICR22 (*(vuint8 *)(void*)(&__IPSBAR[0x000D56])) -#define MCF_INTC1_ICR23 (*(vuint8 *)(void*)(&__IPSBAR[0x000D57])) -#define MCF_INTC1_ICR24 (*(vuint8 *)(void*)(&__IPSBAR[0x000D58])) -#define MCF_INTC1_ICR25 (*(vuint8 *)(void*)(&__IPSBAR[0x000D59])) -#define MCF_INTC1_ICR26 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5A])) -#define MCF_INTC1_ICR27 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5B])) -#define MCF_INTC1_ICR28 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5C])) -#define MCF_INTC1_ICR29 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5D])) -#define MCF_INTC1_ICR30 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5E])) -#define MCF_INTC1_ICR31 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5F])) -#define MCF_INTC1_ICR32 (*(vuint8 *)(void*)(&__IPSBAR[0x000D60])) -#define MCF_INTC1_ICR33 (*(vuint8 *)(void*)(&__IPSBAR[0x000D61])) -#define MCF_INTC1_ICR34 (*(vuint8 *)(void*)(&__IPSBAR[0x000D62])) -#define MCF_INTC1_ICR35 (*(vuint8 *)(void*)(&__IPSBAR[0x000D63])) -#define MCF_INTC1_ICR36 (*(vuint8 *)(void*)(&__IPSBAR[0x000D64])) -#define MCF_INTC1_ICR37 (*(vuint8 *)(void*)(&__IPSBAR[0x000D65])) -#define MCF_INTC1_ICR38 (*(vuint8 *)(void*)(&__IPSBAR[0x000D66])) -#define MCF_INTC1_ICR39 (*(vuint8 *)(void*)(&__IPSBAR[0x000D67])) -#define MCF_INTC1_ICR40 (*(vuint8 *)(void*)(&__IPSBAR[0x000D68])) -#define MCF_INTC1_ICR41 (*(vuint8 *)(void*)(&__IPSBAR[0x000D69])) -#define MCF_INTC1_ICR42 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6A])) -#define MCF_INTC1_ICR43 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6B])) -#define MCF_INTC1_ICR44 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6C])) -#define MCF_INTC1_ICR45 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6D])) -#define MCF_INTC1_ICR46 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6E])) -#define MCF_INTC1_ICR47 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6F])) -#define MCF_INTC1_ICR48 (*(vuint8 *)(void*)(&__IPSBAR[0x000D70])) -#define MCF_INTC1_ICR49 (*(vuint8 *)(void*)(&__IPSBAR[0x000D71])) -#define MCF_INTC1_ICR50 (*(vuint8 *)(void*)(&__IPSBAR[0x000D72])) -#define MCF_INTC1_ICR51 (*(vuint8 *)(void*)(&__IPSBAR[0x000D73])) -#define MCF_INTC1_ICR52 (*(vuint8 *)(void*)(&__IPSBAR[0x000D74])) -#define MCF_INTC1_ICR53 (*(vuint8 *)(void*)(&__IPSBAR[0x000D75])) -#define MCF_INTC1_ICR54 (*(vuint8 *)(void*)(&__IPSBAR[0x000D76])) -#define MCF_INTC1_ICR55 (*(vuint8 *)(void*)(&__IPSBAR[0x000D77])) -#define MCF_INTC1_ICR56 (*(vuint8 *)(void*)(&__IPSBAR[0x000D78])) -#define MCF_INTC1_ICR57 (*(vuint8 *)(void*)(&__IPSBAR[0x000D79])) -#define MCF_INTC1_ICR58 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7A])) -#define MCF_INTC1_ICR59 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7B])) -#define MCF_INTC1_ICR60 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7C])) -#define MCF_INTC1_ICR61 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7D])) -#define MCF_INTC1_ICR62 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7E])) -#define MCF_INTC1_ICR63 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7F])) -#define MCF_INTC1_ICRn(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000D40+((x)*0x001)])) -#define MCF_INTC1_SWIACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DE0])) -#define MCF_INTC1_L1IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DE4])) -#define MCF_INTC1_L2IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DE8])) -#define MCF_INTC1_L3IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DEC])) -#define MCF_INTC1_L4IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DF0])) -#define MCF_INTC1_L5IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DF4])) -#define MCF_INTC1_L6IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DF8])) -#define MCF_INTC1_L7IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DFC])) -#define MCF_INTC1_LnIACK(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000DE4+((x)*0x004)])) - -/* Bit definitions and macros for MCF_INTC1_IPRH */ -#define MCF_INTC1_IPRH_INT32 (0x00000001) -#define MCF_INTC1_IPRH_INT33 (0x00000002) -#define MCF_INTC1_IPRH_INT34 (0x00000004) -#define MCF_INTC1_IPRH_INT35 (0x00000008) -#define MCF_INTC1_IPRH_INT36 (0x00000010) -#define MCF_INTC1_IPRH_INT37 (0x00000020) -#define MCF_INTC1_IPRH_INT38 (0x00000040) -#define MCF_INTC1_IPRH_INT39 (0x00000080) -#define MCF_INTC1_IPRH_INT40 (0x00000100) -#define MCF_INTC1_IPRH_INT41 (0x00000200) -#define MCF_INTC1_IPRH_INT42 (0x00000400) -#define MCF_INTC1_IPRH_INT43 (0x00000800) -#define MCF_INTC1_IPRH_INT44 (0x00001000) -#define MCF_INTC1_IPRH_INT45 (0x00002000) -#define MCF_INTC1_IPRH_INT46 (0x00004000) -#define MCF_INTC1_IPRH_INT47 (0x00008000) -#define MCF_INTC1_IPRH_INT48 (0x00010000) -#define MCF_INTC1_IPRH_INT49 (0x00020000) -#define MCF_INTC1_IPRH_INT50 (0x00040000) -#define MCF_INTC1_IPRH_INT51 (0x00080000) -#define MCF_INTC1_IPRH_INT52 (0x00100000) -#define MCF_INTC1_IPRH_INT53 (0x00200000) -#define MCF_INTC1_IPRH_INT54 (0x00400000) -#define MCF_INTC1_IPRH_INT55 (0x00800000) -#define MCF_INTC1_IPRH_INT56 (0x01000000) -#define MCF_INTC1_IPRH_INT57 (0x02000000) -#define MCF_INTC1_IPRH_INT58 (0x04000000) -#define MCF_INTC1_IPRH_INT59 (0x08000000) -#define MCF_INTC1_IPRH_INT60 (0x10000000) -#define MCF_INTC1_IPRH_INT61 (0x20000000) -#define MCF_INTC1_IPRH_INT62 (0x40000000) -#define MCF_INTC1_IPRH_INT63 (0x80000000) - -/* Bit definitions and macros for MCF_INTC1_IPRL */ -#define MCF_INTC1_IPRL_INT1 (0x00000002) -#define MCF_INTC1_IPRL_INT2 (0x00000004) -#define MCF_INTC1_IPRL_INT3 (0x00000008) -#define MCF_INTC1_IPRL_INT4 (0x00000010) -#define MCF_INTC1_IPRL_INT5 (0x00000020) -#define MCF_INTC1_IPRL_INT6 (0x00000040) -#define MCF_INTC1_IPRL_INT7 (0x00000080) -#define MCF_INTC1_IPRL_INT8 (0x00000100) -#define MCF_INTC1_IPRL_INT9 (0x00000200) -#define MCF_INTC1_IPRL_INT10 (0x00000400) -#define MCF_INTC1_IPRL_INT11 (0x00000800) -#define MCF_INTC1_IPRL_INT12 (0x00001000) -#define MCF_INTC1_IPRL_INT13 (0x00002000) -#define MCF_INTC1_IPRL_INT14 (0x00004000) -#define MCF_INTC1_IPRL_INT15 (0x00008000) -#define MCF_INTC1_IPRL_INT16 (0x00010000) -#define MCF_INTC1_IPRL_INT17 (0x00020000) -#define MCF_INTC1_IPRL_INT18 (0x00040000) -#define MCF_INTC1_IPRL_INT19 (0x00080000) -#define MCF_INTC1_IPRL_INT20 (0x00100000) -#define MCF_INTC1_IPRL_INT21 (0x00200000) -#define MCF_INTC1_IPRL_INT22 (0x00400000) -#define MCF_INTC1_IPRL_INT23 (0x00800000) -#define MCF_INTC1_IPRL_INT24 (0x01000000) -#define MCF_INTC1_IPRL_INT25 (0x02000000) -#define MCF_INTC1_IPRL_INT26 (0x04000000) -#define MCF_INTC1_IPRL_INT27 (0x08000000) -#define MCF_INTC1_IPRL_INT28 (0x10000000) -#define MCF_INTC1_IPRL_INT29 (0x20000000) -#define MCF_INTC1_IPRL_INT30 (0x40000000) -#define MCF_INTC1_IPRL_INT31 (0x80000000) - -/* Bit definitions and macros for MCF_INTC1_IMRH */ -#define MCF_INTC1_IMRH_INT_MASK32 (0x00000001) -#define MCF_INTC1_IMRH_INT_MASK33 (0x00000002) -#define MCF_INTC1_IMRH_INT_MASK34 (0x00000004) -#define MCF_INTC1_IMRH_INT_MASK35 (0x00000008) -#define MCF_INTC1_IMRH_INT_MASK36 (0x00000010) -#define MCF_INTC1_IMRH_INT_MASK37 (0x00000020) -#define MCF_INTC1_IMRH_INT_MASK38 (0x00000040) -#define MCF_INTC1_IMRH_INT_MASK39 (0x00000080) -#define MCF_INTC1_IMRH_INT_MASK40 (0x00000100) -#define MCF_INTC1_IMRH_INT_MASK41 (0x00000200) -#define MCF_INTC1_IMRH_INT_MASK42 (0x00000400) -#define MCF_INTC1_IMRH_INT_MASK43 (0x00000800) -#define MCF_INTC1_IMRH_INT_MASK44 (0x00001000) -#define MCF_INTC1_IMRH_INT_MASK45 (0x00002000) -#define MCF_INTC1_IMRH_INT_MASK46 (0x00004000) -#define MCF_INTC1_IMRH_INT_MASK47 (0x00008000) -#define MCF_INTC1_IMRH_INT_MASK48 (0x00010000) -#define MCF_INTC1_IMRH_INT_MASK49 (0x00020000) -#define MCF_INTC1_IMRH_INT_MASK50 (0x00040000) -#define MCF_INTC1_IMRH_INT_MASK51 (0x00080000) -#define MCF_INTC1_IMRH_INT_MASK52 (0x00100000) -#define MCF_INTC1_IMRH_INT_MASK53 (0x00200000) -#define MCF_INTC1_IMRH_INT_MASK54 (0x00400000) -#define MCF_INTC1_IMRH_INT_MASK55 (0x00800000) -#define MCF_INTC1_IMRH_INT_MASK56 (0x01000000) -#define MCF_INTC1_IMRH_INT_MASK57 (0x02000000) -#define MCF_INTC1_IMRH_INT_MASK58 (0x04000000) -#define MCF_INTC1_IMRH_INT_MASK59 (0x08000000) -#define MCF_INTC1_IMRH_INT_MASK60 (0x10000000) -#define MCF_INTC1_IMRH_INT_MASK61 (0x20000000) -#define MCF_INTC1_IMRH_INT_MASK62 (0x40000000) -#define MCF_INTC1_IMRH_INT_MASK63 (0x80000000) - -/* Bit definitions and macros for MCF_INTC1_IMRL */ -#define MCF_INTC1_IMRL_MASKALL (0x00000001) -#define MCF_INTC1_IMRL_INT_MASK1 (0x00000002) -#define MCF_INTC1_IMRL_INT_MASK2 (0x00000004) -#define MCF_INTC1_IMRL_INT_MASK3 (0x00000008) -#define MCF_INTC1_IMRL_INT_MASK4 (0x00000010) -#define MCF_INTC1_IMRL_INT_MASK5 (0x00000020) -#define MCF_INTC1_IMRL_INT_MASK6 (0x00000040) -#define MCF_INTC1_IMRL_INT_MASK7 (0x00000080) -#define MCF_INTC1_IMRL_INT_MASK8 (0x00000100) -#define MCF_INTC1_IMRL_INT_MASK9 (0x00000200) -#define MCF_INTC1_IMRL_INT_MASK10 (0x00000400) -#define MCF_INTC1_IMRL_INT_MASK11 (0x00000800) -#define MCF_INTC1_IMRL_INT_MASK12 (0x00001000) -#define MCF_INTC1_IMRL_INT_MASK13 (0x00002000) -#define MCF_INTC1_IMRL_INT_MASK14 (0x00004000) -#define MCF_INTC1_IMRL_INT_MASK15 (0x00008000) -#define MCF_INTC1_IMRL_INT_MASK16 (0x00010000) -#define MCF_INTC1_IMRL_INT_MASK17 (0x00020000) -#define MCF_INTC1_IMRL_INT_MASK18 (0x00040000) -#define MCF_INTC1_IMRL_INT_MASK19 (0x00080000) -#define MCF_INTC1_IMRL_INT_MASK20 (0x00100000) -#define MCF_INTC1_IMRL_INT_MASK21 (0x00200000) -#define MCF_INTC1_IMRL_INT_MASK22 (0x00400000) -#define MCF_INTC1_IMRL_INT_MASK23 (0x00800000) -#define MCF_INTC1_IMRL_INT_MASK24 (0x01000000) -#define MCF_INTC1_IMRL_INT_MASK25 (0x02000000) -#define MCF_INTC1_IMRL_INT_MASK26 (0x04000000) -#define MCF_INTC1_IMRL_INT_MASK27 (0x08000000) -#define MCF_INTC1_IMRL_INT_MASK28 (0x10000000) -#define MCF_INTC1_IMRL_INT_MASK29 (0x20000000) -#define MCF_INTC1_IMRL_INT_MASK30 (0x40000000) -#define MCF_INTC1_IMRL_INT_MASK31 (0x80000000) - -/* Bit definitions and macros for MCF_INTC1_INTFRCH */ -#define MCF_INTC1_INTFRCH_INTFRC32 (0x00000001) -#define MCF_INTC1_INTFRCH_INTFRC33 (0x00000002) -#define MCF_INTC1_INTFRCH_INTFRC34 (0x00000004) -#define MCF_INTC1_INTFRCH_INTFRC35 (0x00000008) -#define MCF_INTC1_INTFRCH_INTFRC36 (0x00000010) -#define MCF_INTC1_INTFRCH_INTFRC37 (0x00000020) -#define MCF_INTC1_INTFRCH_INTFRC38 (0x00000040) -#define MCF_INTC1_INTFRCH_INTFRC39 (0x00000080) -#define MCF_INTC1_INTFRCH_INTFRC40 (0x00000100) -#define MCF_INTC1_INTFRCH_INTFRC41 (0x00000200) -#define MCF_INTC1_INTFRCH_INTFRC42 (0x00000400) -#define MCF_INTC1_INTFRCH_INTFRC43 (0x00000800) -#define MCF_INTC1_INTFRCH_INTFRC44 (0x00001000) -#define MCF_INTC1_INTFRCH_INTFRC45 (0x00002000) -#define MCF_INTC1_INTFRCH_INTFRC46 (0x00004000) -#define MCF_INTC1_INTFRCH_INTFRC47 (0x00008000) -#define MCF_INTC1_INTFRCH_INTFRC48 (0x00010000) -#define MCF_INTC1_INTFRCH_INTFRC49 (0x00020000) -#define MCF_INTC1_INTFRCH_INTFRC50 (0x00040000) -#define MCF_INTC1_INTFRCH_INTFRC51 (0x00080000) -#define MCF_INTC1_INTFRCH_INTFRC52 (0x00100000) -#define MCF_INTC1_INTFRCH_INTFRC53 (0x00200000) -#define MCF_INTC1_INTFRCH_INTFRC54 (0x00400000) -#define MCF_INTC1_INTFRCH_INTFRC55 (0x00800000) -#define MCF_INTC1_INTFRCH_INTFRC56 (0x01000000) -#define MCF_INTC1_INTFRCH_INTFRC57 (0x02000000) -#define MCF_INTC1_INTFRCH_INTFRC58 (0x04000000) -#define MCF_INTC1_INTFRCH_INTFRC59 (0x08000000) -#define MCF_INTC1_INTFRCH_INTFRC60 (0x10000000) -#define MCF_INTC1_INTFRCH_INTFRC61 (0x20000000) -#define MCF_INTC1_INTFRCH_INTFRC62 (0x40000000) -#define MCF_INTC1_INTFRCH_INTFRC63 (0x80000000) - -/* Bit definitions and macros for MCF_INTC1_INTFRCL */ -#define MCF_INTC1_INTFRCL_INTFRC1 (0x00000002) -#define MCF_INTC1_INTFRCL_INTFRC2 (0x00000004) -#define MCF_INTC1_INTFRCL_INTFRC3 (0x00000008) -#define MCF_INTC1_INTFRCL_INTFRC4 (0x00000010) -#define MCF_INTC1_INTFRCL_INTFRC5 (0x00000020) -#define MCF_INTC1_INTFRCL_INT6 (0x00000040) -#define MCF_INTC1_INTFRCL_INT7 (0x00000080) -#define MCF_INTC1_INTFRCL_INT8 (0x00000100) -#define MCF_INTC1_INTFRCL_INT9 (0x00000200) -#define MCF_INTC1_INTFRCL_INT10 (0x00000400) -#define MCF_INTC1_INTFRCL_INTFRC11 (0x00000800) -#define MCF_INTC1_INTFRCL_INTFRC12 (0x00001000) -#define MCF_INTC1_INTFRCL_INTFRC13 (0x00002000) -#define MCF_INTC1_INTFRCL_INTFRC14 (0x00004000) -#define MCF_INTC1_INTFRCL_INT15 (0x00008000) -#define MCF_INTC1_INTFRCL_INTFRC16 (0x00010000) -#define MCF_INTC1_INTFRCL_INTFRC17 (0x00020000) -#define MCF_INTC1_INTFRCL_INTFRC18 (0x00040000) -#define MCF_INTC1_INTFRCL_INTFRC19 (0x00080000) -#define MCF_INTC1_INTFRCL_INTFRC20 (0x00100000) -#define MCF_INTC1_INTFRCL_INTFRC21 (0x00200000) -#define MCF_INTC1_INTFRCL_INTFRC22 (0x00400000) -#define MCF_INTC1_INTFRCL_INTFRC23 (0x00800000) -#define MCF_INTC1_INTFRCL_INTFRC24 (0x01000000) -#define MCF_INTC1_INTFRCL_INTFRC25 (0x02000000) -#define MCF_INTC1_INTFRCL_INTFRC26 (0x04000000) -#define MCF_INTC1_INTFRCL_INTFRC27 (0x08000000) -#define MCF_INTC1_INTFRCL_INTFRC28 (0x10000000) -#define MCF_INTC1_INTFRCL_INTFRC29 (0x20000000) -#define MCF_INTC1_INTFRCL_INTFRC30 (0x40000000) -#define MCF_INTC1_INTFRCL_INTFRC31 (0x80000000) - -/* Bit definitions and macros for MCF_INTC1_IRLR */ -#define MCF_INTC1_IRLR_IRQ(x) (((x)&0x7F)<<1) - -/* Bit definitions and macros for MCF_INTC1_IACKLPR */ -#define MCF_INTC1_IACKLPR_PRI(x) (((x)&0x0F)<<0) -#define MCF_INTC1_IACKLPR_LEVEL(x) (((x)&0x07)<<4) - -/* Bit definitions and macros for MCF_INTC1_ICRn */ -#define MCF_INTC1_ICRn_IP(x) (((x)&0x07)<<0) -#define MCF_INTC1_ICRn_IL(x) (((x)&0x07)<<3) - -/********************************************************************/ - -#endif /* __MCF523X_INTC1_H__ */ diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_mdha.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_mdha.h deleted file mode 100644 index adc714f6d..000000000 --- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_mdha.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * These files are taken from the MCF523X source code example package - * which is available on the Freescale website. Freescale explicitly - * grants the redistribution and modification of these source files. - * The complete licensing information is available in the file - * LICENSE_FREESCALE.TXT. - * - * File: mcf523x_mdha.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_MDHA_H__ -#define __MCF523X_MDHA_H__ - -/********************************************************************* -* -* Message Digest Hardware Accelerator (MDHA) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_MDHA_MDMR (*(vuint32*)(void*)(&__IPSBAR[0x190000])) -#define MCF_MDHA_MDCR (*(vuint32*)(void*)(&__IPSBAR[0x190004])) -#define MCF_MDHA_MDCMR (*(vuint32*)(void*)(&__IPSBAR[0x190008])) -#define MCF_MDHA_MDSR (*(vuint32*)(void*)(&__IPSBAR[0x19000C])) -#define MCF_MDHA_MDISR (*(vuint32*)(void*)(&__IPSBAR[0x190010])) -#define MCF_MDHA_MDIMR (*(vuint32*)(void*)(&__IPSBAR[0x190014])) -#define MCF_MDHA_MDDSR (*(vuint32*)(void*)(&__IPSBAR[0x19001C])) -#define MCF_MDHA_MDIN (*(vuint32*)(void*)(&__IPSBAR[0x190020])) -#define MCF_MDHA_MDA0 (*(vuint32*)(void*)(&__IPSBAR[0x190030])) -#define MCF_MDHA_MDB0 (*(vuint32*)(void*)(&__IPSBAR[0x190034])) -#define MCF_MDHA_MDC0 (*(vuint32*)(void*)(&__IPSBAR[0x190038])) -#define MCF_MDHA_MDD0 (*(vuint32*)(void*)(&__IPSBAR[0x19003C])) -#define MCF_MDHA_MDE0 (*(vuint32*)(void*)(&__IPSBAR[0x190040])) -#define MCF_MDHA_MDMDS (*(vuint32*)(void*)(&__IPSBAR[0x190044])) -#define MCF_MDHA_MDA1 (*(vuint32*)(void*)(&__IPSBAR[0x190070])) -#define MCF_MDHA_MDB1 (*(vuint32*)(void*)(&__IPSBAR[0x190074])) -#define MCF_MDHA_MDC1 (*(vuint32*)(void*)(&__IPSBAR[0x190078])) -#define MCF_MDHA_MDD1 (*(vuint32*)(void*)(&__IPSBAR[0x19007C])) -#define MCF_MDHA_MDE1 (*(vuint32*)(void*)(&__IPSBAR[0x190080])) - -/* Bit definitions and macros for MCF_MDHA_MDMR */ -#define MCF_MDHA_MDMR_ALG (0x00000001) -#define MCF_MDHA_MDMR_PDATA (0x00000004) -#define MCF_MDHA_MDMR_MAC(x) (((x)&0x00000003)<<3) -#define MCF_MDHA_MDMR_INIT (0x00000020) -#define MCF_MDHA_MDMR_IPAD (0x00000040) -#define MCF_MDHA_MDMR_OPAD (0x00000080) -#define MCF_MDHA_MDMR_SWAP (0x00000100) -#define MCF_MDHA_MDMR_MACFULL (0x00000200) -#define MCF_MDHA_MDMR_SSL (0x00000400) - -/* Bit definitions and macros for MCF_MDHA_MDCR */ -#define MCF_MDHA_MDCR_IE (0x00000001) - -/* Bit definitions and macros for MCF_MDHA_MDCMR */ -#define MCF_MDHA_MDCMR_SWR (0x00000001) -#define MCF_MDHA_MDCMR_RI (0x00000002) -#define MCF_MDHA_MDCMR_CI (0x00000004) -#define MCF_MDHA_MDCMR_GO (0x00000008) - -/* Bit definitions and macros for MCF_MDHA_MDSR */ -#define MCF_MDHA_MDSR_INT (0x00000001) -#define MCF_MDHA_MDSR_DONE (0x00000002) -#define MCF_MDHA_MDSR_ERR (0x00000004) -#define MCF_MDHA_MDSR_RD (0x00000008) -#define MCF_MDHA_MDSR_BUSY (0x00000010) -#define MCF_MDHA_MDSR_END (0x00000020) -#define MCF_MDHA_MDSR_HSH (0x00000040) -#define MCF_MDHA_MDSR_GNW (0x00000080) -#define MCF_MDHA_MDSR_FS(x) (((x)&0x00000007)<<8) -#define MCF_MDHA_MDSR_APD(x) (((x)&0x00000007)<<13) -#define MCF_MDHA_MDSR_IFL(x) (((x)&0x000000FF)<<16) - -/* Bit definitions and macros for MCF_MDHA_MDIR */ -#define MCF_MDHA_MDIR_IFO (0x00000001) -#define MCF_MDHA_MDIR_NON (0x00000004) -#define MCF_MDHA_MDIR_IME (0x00000010) -#define MCF_MDHA_MDIR_IDS (0x00000020) -#define MCF_MDHA_MDIR_RMDP (0x00000080) -#define MCF_MDHA_MDIR_ERE (0x00000100) -#define MCF_MDHA_MDIR_GTDS (0x00000200) - -/* Bit definitions and macros for MCF_MDHA_MDIMR */ -#define MCF_MDHA_MDIMR_IFO (0x00000001) -#define MCF_MDHA_MDIMR_NON (0x00000004) -#define MCF_MDHA_MDIMR_IME (0x00000010) -#define MCF_MDHA_MDIMR_IDS (0x00000020) -#define MCF_MDHA_MDIMR_RMDP (0x00000080) -#define MCF_MDHA_MDIMR_ERE (0x00000100) -#define MCF_MDHA_MDIMR_GTDS (0x00000200) - -/* Bit definitions and macros for MCF_MDHA_MDDSR */ -#define MCF_MDHA_MDDSR_DATASIZE(x) (((x)&0x1FFFFFFF)<<0) - -/********************************************************************/ - -#endif /* __MCF523X_MDHA_H__ */ diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_pit.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_pit.h deleted file mode 100644 index 0763d20f2..000000000 --- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_pit.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * These files are taken from the MCF523X source code example package - * which is available on the Freescale website. Freescale explicitly - * grants the redistribution and modification of these source files. - * The complete licensing information is available in the file - * LICENSE_FREESCALE.TXT. - * - * File: mcf523x_pit.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_PIT_H__ -#define __MCF523X_PIT_H__ - -/********************************************************************* -* -* Programmable Interrupt Timer Modules (PIT) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_PIT_PCSR0 (*(vuint16*)(void*)(&__IPSBAR[0x150000])) -#define MCF_PIT_PMR0 (*(vuint16*)(void*)(&__IPSBAR[0x150002])) -#define MCF_PIT_PCNTR0 (*(vuint16*)(void*)(&__IPSBAR[0x150004])) -#define MCF_PIT_PCSR1 (*(vuint16*)(void*)(&__IPSBAR[0x160000])) -#define MCF_PIT_PMR1 (*(vuint16*)(void*)(&__IPSBAR[0x160002])) -#define MCF_PIT_PCNTR1 (*(vuint16*)(void*)(&__IPSBAR[0x160004])) -#define MCF_PIT_PCSR2 (*(vuint16*)(void*)(&__IPSBAR[0x170000])) -#define MCF_PIT_PMR2 (*(vuint16*)(void*)(&__IPSBAR[0x170002])) -#define MCF_PIT_PCNTR2 (*(vuint16*)(void*)(&__IPSBAR[0x170004])) -#define MCF_PIT_PCSR3 (*(vuint16*)(void*)(&__IPSBAR[0x180000])) -#define MCF_PIT_PMR3 (*(vuint16*)(void*)(&__IPSBAR[0x180002])) -#define MCF_PIT_PCNTR3 (*(vuint16*)(void*)(&__IPSBAR[0x180004])) -#define MCF_PIT_PCSR(x) (*(vuint16*)(void*)(&__IPSBAR[0x150000+((x)*0x10000)])) -#define MCF_PIT_PMR(x) (*(vuint16*)(void*)(&__IPSBAR[0x150002+((x)*0x10000)])) -#define MCF_PIT_PCNTR(x) (*(vuint16*)(void*)(&__IPSBAR[0x150004+((x)*0x10000)])) - -/* Bit definitions and macros for MCF_PIT_PCSR */ -#define MCF_PIT_PCSR_EN (0x0001) -#define MCF_PIT_PCSR_RLD (0x0002) -#define MCF_PIT_PCSR_PIF (0x0004) -#define MCF_PIT_PCSR_PIE (0x0008) -#define MCF_PIT_PCSR_OVW (0x0010) -#define MCF_PIT_PCSR_HALTED (0x0020) -#define MCF_PIT_PCSR_DOZE (0x0040) -#define MCF_PIT_PCSR_PRE(x) (((x)&0x000F)<<8) - -/* Bit definitions and macros for MCF_PIT_PMR */ -#define MCF_PIT_PMR_PM0 (0x0001) -#define MCF_PIT_PMR_PM1 (0x0002) -#define MCF_PIT_PMR_PM2 (0x0004) -#define MCF_PIT_PMR_PM3 (0x0008) -#define MCF_PIT_PMR_PM4 (0x0010) -#define MCF_PIT_PMR_PM5 (0x0020) -#define MCF_PIT_PMR_PM6 (0x0040) -#define MCF_PIT_PMR_PM7 (0x0080) -#define MCF_PIT_PMR_PM8 (0x0100) -#define MCF_PIT_PMR_PM9 (0x0200) -#define MCF_PIT_PMR_PM10 (0x0400) -#define MCF_PIT_PMR_PM11 (0x0800) -#define MCF_PIT_PMR_PM12 (0x1000) -#define MCF_PIT_PMR_PM13 (0x2000) -#define MCF_PIT_PMR_PM14 (0x4000) -#define MCF_PIT_PMR_PM15 (0x8000) - -/* Bit definitions and macros for MCF_PIT_PCNTR */ -#define MCF_PIT_PCNTR_PC0 (0x0001) -#define MCF_PIT_PCNTR_PC1 (0x0002) -#define MCF_PIT_PCNTR_PC2 (0x0004) -#define MCF_PIT_PCNTR_PC3 (0x0008) -#define MCF_PIT_PCNTR_PC4 (0x0010) -#define MCF_PIT_PCNTR_PC5 (0x0020) -#define MCF_PIT_PCNTR_PC6 (0x0040) -#define MCF_PIT_PCNTR_PC7 (0x0080) -#define MCF_PIT_PCNTR_PC8 (0x0100) -#define MCF_PIT_PCNTR_PC9 (0x0200) -#define MCF_PIT_PCNTR_PC10 (0x0400) -#define MCF_PIT_PCNTR_PC11 (0x0800) -#define MCF_PIT_PCNTR_PC12 (0x1000) -#define MCF_PIT_PCNTR_PC13 (0x2000) -#define MCF_PIT_PCNTR_PC14 (0x4000) -#define MCF_PIT_PCNTR_PC15 (0x8000) - -/********************************************************************/ - -#endif /* __MCF523X_PIT_H__ */ diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_qspi.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_qspi.h deleted file mode 100644 index ed32d6d40..000000000 --- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_qspi.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * These files are taken from the MCF523X source code example package - * which is available on the Freescale website. Freescale explicitly - * grants the redistribution and modification of these source files. - * The complete licensing information is available in the file - * LICENSE_FREESCALE.TXT. - * - * File: mcf523x_qspi.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_QSPI_H__ -#define __MCF523X_QSPI_H__ - -/********************************************************************* -* -* Queued Serial Peripheral Interface (QSPI) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_QSPI_QMR (*(vuint16*)(void*)(&__IPSBAR[0x000340])) -#define MCF_QSPI_QDLYR (*(vuint16*)(void*)(&__IPSBAR[0x000344])) -#define MCF_QSPI_QWR (*(vuint16*)(void*)(&__IPSBAR[0x000348])) -#define MCF_QSPI_QIR (*(vuint16*)(void*)(&__IPSBAR[0x00034C])) -#define MCF_QSPI_QAR (*(vuint16*)(void*)(&__IPSBAR[0x000350])) -#define MCF_QSPI_QDR (*(vuint16*)(void*)(&__IPSBAR[0x000354])) - -/* Bit definitions and macros for MCF_QSPI_QMR */ -#define MCF_QSPI_QMR_BAUD(x) (((x)&0x00FF)<<0) -#define MCF_QSPI_QMR_CPHA (0x0100) -#define MCF_QSPI_QMR_CPOL (0x0200) -#define MCF_QSPI_QMR_BITS(x) (((x)&0x000F)<<10) -#define MCF_QSPI_QMR_DOHIE (0x4000) -#define MCF_QSPI_QMR_MSTR (0x8000) - -/* Bit definitions and macros for MCF_QSPI_QDLYR */ -#define MCF_QSPI_QDLYR_DTL(x) (((x)&0x00FF)<<0) -#define MCF_QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8) -#define MCF_QSPI_QDLYR_SPE (0x8000) - -/* Bit definitions and macros for MCF_QSPI_QWR */ -#define MCF_QSPI_QWR_NEWQP(x) (((x)&0x000F)<<0) -#define MCF_QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8) -#define MCF_QSPI_QWR_CSIV (0x1000) -#define MCF_QSPI_QWR_WRTO (0x2000) -#define MCF_QSPI_QWR_WREN (0x4000) -#define MCF_QSPI_QWR_HALT (0x8000) - -/* Bit definitions and macros for MCF_QSPI_QIR */ -#define MCF_QSPI_QIR_SPIF (0x0001) -#define MCF_QSPI_QIR_ABRT (0x0004) -#define MCF_QSPI_QIR_WCEF (0x0008) -#define MCF_QSPI_QIR_SPIFE (0x0100) -#define MCF_QSPI_QIR_ABRTE (0x0400) -#define MCF_QSPI_QIR_WCEFE (0x0800) -#define MCF_QSPI_QIR_ABRTL (0x1000) -#define MCF_QSPI_QIR_ABRTB (0x4000) -#define MCF_QSPI_QIR_WCEFB (0x8000) - -/* Bit definitions and macros for MCF_QSPI_QAR */ -#define MCF_QSPI_QAR_ADDR(x) (((x)&0x003F)<<0) - -/********************************************************************/ - -#endif /* __MCF523X_QSPI_H__ */ diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_rcm.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_rcm.h deleted file mode 100644 index 784d0fab0..000000000 --- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_rcm.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * These files are taken from the MCF523X source code example package - * which is available on the Freescale website. Freescale explicitly - * grants the redistribution and modification of these source files. - * The complete licensing information is available in the file - * LICENSE_FREESCALE.TXT. - * - * File: mcf523x_rcm.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_RCM_H__ -#define __MCF523X_RCM_H__ - -/********************************************************************* -* -* Reset Configuration Module (RCM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_RCM_RCR (*(vuint8 *)(void*)(&__IPSBAR[0x110000])) -#define MCF_RCM_RSR (*(vuint8 *)(void*)(&__IPSBAR[0x110001])) - -/* Bit definitions and macros for MCF_RCM_RCR */ -#define MCF_RCM_RCR_FRCRSTOUT (0x40) -#define MCF_RCM_RCR_SOFTRST (0x80) - -/* Bit definitions and macros for MCF_RCM_RSR */ -#define MCF_RCM_RSR_LOL (0x01) -#define MCF_RCM_RSR_LOC (0x02) -#define MCF_RCM_RSR_EXT (0x04) -#define MCF_RCM_RSR_POR (0x08) -#define MCF_RCM_RSR_WDR (0x10) -#define MCF_RCM_RSR_SOFT (0x20) - -/********************************************************************/ - -#endif /* __MCF523X_RCM_H__ */ diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_rng.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_rng.h deleted file mode 100644 index 744bd0ae3..000000000 --- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_rng.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * These files are taken from the MCF523X source code example package - * which is available on the Freescale website. Freescale explicitly - * grants the redistribution and modification of these source files. - * The complete licensing information is available in the file - * LICENSE_FREESCALE.TXT. - * - * File: mcf523x_rng.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_RNG_H__ -#define __MCF523X_RNG_H__ - -/********************************************************************* -* -* Random Number Generator (RNG) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_RNG_RNGCR (*(vuint32*)(void*)(&__IPSBAR[0x1A0000])) -#define MCF_RNG_RNGSR (*(vuint32*)(void*)(&__IPSBAR[0x1A0004])) -#define MCF_RNG_RNGER (*(vuint32*)(void*)(&__IPSBAR[0x1A0008])) -#define MCF_RNG_RNGOUT (*(vuint32*)(void*)(&__IPSBAR[0x1A000C])) - -/* Bit definitions and macros for MCF_RNG_RNGCR */ -#define MCF_RNG_RNGCR_GO (0x00000001) -#define MCF_RNG_RNGCR_HA (0x00000002) -#define MCF_RNG_RNGCR_IM (0x00000004) -#define MCF_RNG_RNGCR_CI (0x00000008) - -/* Bit definitions and macros for MCF_RNG_RNGSR */ -#define MCF_RNG_RNGSR_SV (0x00000001) -#define MCF_RNG_RNGSR_LRS (0x00000002) -#define MCF_RNG_RNGSR_FUF (0x00000004) -#define MCF_RNG_RNGSR_EI (0x00000008) -#define MCF_RNG_RNGSR_OFL(x) (((x)&0x000000FF)<<8) -#define MCF_RNG_RNGSR_OFS(x) (((x)&0x000000FF)<<16) - -/********************************************************************/ - -#endif /* __MCF523X_RNG_H__ */ diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_scm.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_scm.h deleted file mode 100644 index d9ef0f0eb..000000000 --- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_scm.h +++ /dev/null @@ -1,150 +0,0 @@ -/* - * These files are taken from the MCF523X source code example package - * which is available on the Freescale website. Freescale explicitly - * grants the redistribution and modification of these source files. - * The complete licensing information is available in the file - * LICENSE_FREESCALE.TXT. - * - * File: mcf523x_scm.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_SCM_H__ -#define __MCF523X_SCM_H__ - -/********************************************************************* -* -* System Control Module (SCM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_SCM_IPSBAR (*(vuint32*)(void*)(&__IPSBAR[0x000000])) -#define MCF_SCM_RAMBAR (*(vuint32*)(void*)(&__IPSBAR[0x000008])) -#define MCF_SCM_CRSR (*(vuint8 *)(void*)(&__IPSBAR[0x000010])) -#define MCF_SCM_CWCR (*(vuint8 *)(void*)(&__IPSBAR[0x000011])) -#define MCF_SCM_LPICR (*(vuint8 *)(void*)(&__IPSBAR[0x000012])) -#define MCF_SCM_CWSR (*(vuint8 *)(void*)(&__IPSBAR[0x000013])) -#define MCF_SCM_DMAREQC (*(vuint32*)(void*)(&__IPSBAR[0x000014])) -#define MCF_SCM_MPARK (*(vuint32*)(void*)(&__IPSBAR[0x00001C])) -#define MCF_SCM_MPR (*(vuint8 *)(void*)(&__IPSBAR[0x000020])) -#define MCF_SCM_PACR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000024])) -#define MCF_SCM_PACR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000025])) -#define MCF_SCM_PACR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000026])) -#define MCF_SCM_PACR3 (*(vuint8 *)(void*)(&__IPSBAR[0x000027])) -#define MCF_SCM_PACR4 (*(vuint8 *)(void*)(&__IPSBAR[0x000028])) -#define MCF_SCM_PACR5 (*(vuint8 *)(void*)(&__IPSBAR[0x00002A])) -#define MCF_SCM_PACR6 (*(vuint8 *)(void*)(&__IPSBAR[0x00002B])) -#define MCF_SCM_PACR7 (*(vuint8 *)(void*)(&__IPSBAR[0x00002C])) -#define MCF_SCM_PACR8 (*(vuint8 *)(void*)(&__IPSBAR[0x00002E])) -#define MCF_SCM_GPACR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000030])) - -/* Bit definitions and macros for MCF_SCM_IPSBAR */ -#define MCF_SCM_IPSBAR_V (0x00000001) -#define MCF_SCM_IPSBAR_BA(x) (((x)&0x00000003)<<30) - -/* Bit definitions and macros for MCF_SCM_RAMBAR */ -#define MCF_SCM_RAMBAR_BDE (0x00000200) -#define MCF_SCM_RAMBAR_BA(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_SCM_CRSR */ -#define MCF_SCM_CRSR_CWDR (0x20) -#define MCF_SCM_CRSR_EXT (0x80) - -/* Bit definitions and macros for MCF_SCM_CWCR */ -#define MCF_SCM_CWCR_CWTIC (0x01) -#define MCF_SCM_CWCR_CWTAVAL (0x02) -#define MCF_SCM_CWCR_CWTA (0x04) -#define MCF_SCM_CWCR_CWT(x) (((x)&0x07)<<3) -#define MCF_SCM_CWCR_CWRI (0x40) -#define MCF_SCM_CWCR_CWE (0x80) - -/* Bit definitions and macros for MCF_SCM_LPICR */ -#define MCF_SCM_LPICR_XLPM_IPL(x) (((x)&0x07)<<4) -#define MCF_SCM_LPICR_ENBSTOP (0x80) - -/* Bit definitions and macros for MCF_SCM_DMAREQC */ -#define MCF_SCM_DMAREQC_DMAC0(x) (((x)&0x0000000F)<<0) -#define MCF_SCM_DMAREQC_DMAC1(x) (((x)&0x0000000F)<<4) -#define MCF_SCM_DMAREQC_DMAC2(x) (((x)&0x0000000F)<<8) -#define MCF_SCM_DMAREQC_DMAC3(x) (((x)&0x0000000F)<<12) - -/* Bit definitions and macros for MCF_SCM_MPARK */ -#define MCF_SCM_MPARK_LCKOUT_TIME(x) (((x)&0x0000000F)<<8) -#define MCF_SCM_MPARK_PRKLAST (0x00001000) -#define MCF_SCM_MPARK_TIMEOUT (0x00002000) -#define MCF_SCM_MPARK_FIXED (0x00004000) -#define MCF_SCM_MPARK_M1_PRTY(x) (((x)&0x00000003)<<16) -#define MCF_SCM_MPARK_M0_PRTY(x) (((x)&0x00000003)<<18) -#define MCF_SCM_MPARK_M2_PRTY(x) (((x)&0x00000003)<<20) -#define MCF_SCM_MPARK_M3_PRTY(x) (((x)&0x00000003)<<22) -#define MCF_SCM_MPARK_BCR24BIT (0x01000000) -#define MCF_SCM_MPARK_M2_P_EN (0x02000000) - -/* Bit definitions and macros for MCF_SCM_MPR */ -#define MCF_SCM_MPR_MPR(x) (((x)&0x0F)<<0) - -/* Bit definitions and macros for MCF_SCM_PACR0 */ -#define MCF_SCM_PACR0_ACCESS_CTRL0(x) (((x)&0x07)<<0) -#define MCF_SCM_PACR0_LOCK0 (0x08) -#define MCF_SCM_PACR0_ACCESS_CTRL1(x) (((x)&0x07)<<4) -#define MCF_SCM_PACR0_LOCK1 (0x80) - -/* Bit definitions and macros for MCF_SCM_PACR1 */ -#define MCF_SCM_PACR1_ACCESS_CTRL0(x) (((x)&0x07)<<0) -#define MCF_SCM_PACR1_LOCK0 (0x08) -#define MCF_SCM_PACR1_ACCESS_CTRL1(x) (((x)&0x07)<<4) -#define MCF_SCM_PACR1_LOCK1 (0x80) - -/* Bit definitions and macros for MCF_SCM_PACR2 */ -#define MCF_SCM_PACR2_ACCESS_CTRL0(x) (((x)&0x07)<<0) -#define MCF_SCM_PACR2_LOCK0 (0x08) -#define MCF_SCM_PACR2_ACCESS_CTRL1(x) (((x)&0x07)<<4) -#define MCF_SCM_PACR2_LOCK1 (0x80) - -/* Bit definitions and macros for MCF_SCM_PACR3 */ -#define MCF_SCM_PACR3_ACCESS_CTRL0(x) (((x)&0x07)<<0) -#define MCF_SCM_PACR3_LOCK0 (0x08) -#define MCF_SCM_PACR3_ACCESS_CTRL1(x) (((x)&0x07)<<4) -#define MCF_SCM_PACR3_LOCK1 (0x80) - -/* Bit definitions and macros for MCF_SCM_PACR4 */ -#define MCF_SCM_PACR4_ACCESS_CTRL0(x) (((x)&0x07)<<0) -#define MCF_SCM_PACR4_LOCK0 (0x08) -#define MCF_SCM_PACR4_ACCESS_CTRL1(x) (((x)&0x07)<<4) -#define MCF_SCM_PACR4_LOCK1 (0x80) - -/* Bit definitions and macros for MCF_SCM_PACR5 */ -#define MCF_SCM_PACR5_ACCESS_CTRL0(x) (((x)&0x07)<<0) -#define MCF_SCM_PACR5_LOCK0 (0x08) -#define MCF_SCM_PACR5_ACCESS_CTRL1(x) (((x)&0x07)<<4) -#define MCF_SCM_PACR5_LOCK1 (0x80) - -/* Bit definitions and macros for MCF_SCM_PACR6 */ -#define MCF_SCM_PACR6_ACCESS_CTRL0(x) (((x)&0x07)<<0) -#define MCF_SCM_PACR6_LOCK0 (0x08) -#define MCF_SCM_PACR6_ACCESS_CTRL1(x) (((x)&0x07)<<4) -#define MCF_SCM_PACR6_LOCK1 (0x80) - -/* Bit definitions and macros for MCF_SCM_PACR7 */ -#define MCF_SCM_PACR7_ACCESS_CTRL0(x) (((x)&0x07)<<0) -#define MCF_SCM_PACR7_LOCK0 (0x08) -#define MCF_SCM_PACR7_ACCESS_CTRL1(x) (((x)&0x07)<<4) -#define MCF_SCM_PACR7_LOCK1 (0x80) - -/* Bit definitions and macros for MCF_SCM_PACR8 */ -#define MCF_SCM_PACR8_ACCESS_CTRL0(x) (((x)&0x07)<<0) -#define MCF_SCM_PACR8_LOCK0 (0x08) -#define MCF_SCM_PACR8_ACCESS_CTRL1(x) (((x)&0x07)<<4) -#define MCF_SCM_PACR8_LOCK1 (0x80) - -/* Bit definitions and macros for MCF_SCM_GPACR0 */ -#define MCF_SCM_GPACR0_ACCESS_CTRL(x) (((x)&0x0F)<<0) -#define MCF_SCM_GPACR0_LOCK (0x80) - -/********************************************************************/ - -#endif /* __MCF523X_SCM_H__ */ diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_sdramc.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_sdramc.h deleted file mode 100644 index dbf38f8b6..000000000 --- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_sdramc.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * These files are taken from the MCF523X source code example package - * which is available on the Freescale website. Freescale explicitly - * grants the redistribution and modification of these source files. - * The complete licensing information is available in the file - * LICENSE_FREESCALE.TXT. - * - * File: mcf523x_sdramc.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_SDRAMC_H__ -#define __MCF523X_SDRAMC_H__ - -/********************************************************************* -* -* SDRAM Controller (SDRAMC) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_SDRAMC_DCR (*(vuint16*)(void*)(&__IPSBAR[0x000040])) -#define MCF_SDRAMC_DACR0 (*(vuint32*)(void*)(&__IPSBAR[0x000048])) -#define MCF_SDRAMC_DMR0 (*(vuint32*)(void*)(&__IPSBAR[0x00004C])) -#define MCF_SDRAMC_DACR1 (*(vuint32*)(void*)(&__IPSBAR[0x000050])) -#define MCF_SDRAMC_DMR1 (*(vuint32*)(void*)(&__IPSBAR[0x000054])) - -/* Bit definitions and macros for MCF_SDRAMC_DCR */ -#define MCF_SDRAMC_DCR_RC(x) (((x)&0x01FF)<<0) -#define MCF_SDRAMC_DCR_RTIM(x) (((x)&0x0003)<<9) -#define MCF_SDRAMC_DCR_IS (0x0800) -#define MCF_SDRAMC_DCR_COC (0x1000) -#define MCF_SDRAMC_DCR_NAM (0x2000) - -/* Bit definitions and macros for MCF_SDRAMC_DACR0 */ -#define MCF_SDRAMC_DACR0_IP (0x00000008) -#define MCF_SDRAMC_DACR0_PS(x) (((x)&0x00000003)<<4) -#define MCF_SDRAMC_DACR0_MRS (0x00000040) -#define MCF_SDRAMC_DACR0_CBM(x) (((x)&0x00000007)<<8) -#define MCF_SDRAMC_DACR0_CASL(x) (((x)&0x00000003)<<12) -#define MCF_SDRAMC_DACR0_RE (0x00008000) -#define MCF_SDRAMC_DACR0_BA(x) (((x)&0x00003FFF)<<18) - -/* Bit definitions and macros for MCF_SDRAMC_DMR0 */ -#define MCF_SDRAMC_DMR0_V (0x00000001) -#define MCF_SDRAMC_DMR0_WP (0x00000100) -#define MCF_SDRAMC_DMR0_BAM(x) (((x)&0x00003FFF)<<18) - -/* Bit definitions and macros for MCF_SDRAMC_DACR1 */ -#define MCF_SDRAMC_DACR1_IP (0x00000008) -#define MCF_SDRAMC_DACR1_PS(x) (((x)&0x00000003)<<4) -#define MCF_SDRAMC_DACR1_MRS (0x00000040) -#define MCF_SDRAMC_DACR1_CBM(x) (((x)&0x00000007)<<8) -#define MCF_SDRAMC_DACR1_CASL(x) (((x)&0x00000003)<<12) -#define MCF_SDRAMC_DACR1_RE (0x00008000) -#define MCF_SDRAMC_DACR1_BA(x) (((x)&0x00003FFF)<<18) - -/* Bit definitions and macros for MCF_SDRAMC_DMR1 */ -#define MCF_SDRAMC_DMR1_V (0x00000001) -#define MCF_SDRAMC_DMR1_WP (0x00000100) -#define MCF_SDRAMC_DMR1_BAM(x) (((x)&0x00003FFF)<<18) - -/********************************************************************/ - -#define MCF_SDRAMC_DMR_BAM_4G (0xFFFC0000) -#define MCF_SDRAMC_DMR_BAM_2G (0x7FFC0000) -#define MCF_SDRAMC_DMR_BAM_1G (0x3FFC0000) -#define MCF_SDRAMC_DMR_BAM_1024M (0x3FFC0000) -#define MCF_SDRAMC_DMR_BAM_512M (0x1FFC0000) -#define MCF_SDRAMC_DMR_BAM_256M (0x0FFC0000) -#define MCF_SDRAMC_DMR_BAM_128M (0x07FC0000) -#define MCF_SDRAMC_DMR_BAM_64M (0x03FC0000) -#define MCF_SDRAMC_DMR_BAM_32M (0x01FC0000) -#define MCF_SDRAMC_DMR_BAM_16M (0x00FC0000) -#define MCF_SDRAMC_DMR_BAM_8M (0x007C0000) -#define MCF_SDRAMC_DMR_BAM_4M (0x003C0000) -#define MCF_SDRAMC_DMR_BAM_2M (0x001C0000) -#define MCF_SDRAMC_DMR_BAM_1M (0x000C0000) -#define MCF_SDRAMC_DMR_BAM_1024K (0x000C0000) -#define MCF_SDRAMC_DMR_BAM_512K (0x00040000) -#define MCF_SDRAMC_DMR_BAM_256K (0x00000000) -#define MCF_SDRAMC_DMR_WP (0x00000100) -#define MCF_SDRAMC_DMR_CI (0x00000040) -#define MCF_SDRAMC_DMR_AM (0x00000020) -#define MCF_SDRAMC_DMR_SC (0x00000010) -#define MCF_SDRAMC_DMR_SD (0x00000008) -#define MCF_SDRAMC_DMR_UC (0x00000004) -#define MCF_SDRAMC_DMR_UD (0x00000002) -#define MCF_SDRAMC_DMR_V (0x00000001) - -#endif /* __MCF523X_SDRAMC_H__ */ diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_skha.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_skha.h deleted file mode 100644 index e03d2e05c..000000000 --- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_skha.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - * These files are taken from the MCF523X source code example package - * which is available on the Freescale website. Freescale explicitly - * grants the redistribution and modification of these source files. - * The complete licensing information is available in the file - * LICENSE_FREESCALE.TXT. - * - * File: mcf523x_skha.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_SKHA_H__ -#define __MCF523X_SKHA_H__ - -/********************************************************************* -* -* Symmetric Key Hardware Accelerator (SKHA) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_SKHA_SKMR (*(vuint32*)(void*)(&__IPSBAR[0x1B0000])) -#define MCF_SKHA_SKCR (*(vuint32*)(void*)(&__IPSBAR[0x1B0004])) -#define MCF_SKHA_SKCMR (*(vuint32*)(void*)(&__IPSBAR[0x1B0008])) -#define MCF_SKHA_SKSR (*(vuint32*)(void*)(&__IPSBAR[0x1B000C])) -#define MCF_SKHA_SKIR (*(vuint32*)(void*)(&__IPSBAR[0x1B0010])) -#define MCF_SKHA_SKIMR (*(vuint32*)(void*)(&__IPSBAR[0x1B0014])) -#define MCF_SKHA_SKKSR (*(vuint32*)(void*)(&__IPSBAR[0x1B0018])) -#define MCF_SKHA_SKDSR (*(vuint32*)(void*)(&__IPSBAR[0x1B001C])) -#define MCF_SKHA_SKIN (*(vuint32*)(void*)(&__IPSBAR[0x1B0020])) -#define MCF_SKHA_SKOUT (*(vuint32*)(void*)(&__IPSBAR[0x1B0024])) -#define MCF_SKHA_SKKDR0 (*(vuint32*)(void*)(&__IPSBAR[0x1B0030])) -#define MCF_SKHA_SKKDR1 (*(vuint32*)(void*)(&__IPSBAR[0x1B0034])) -#define MCF_SKHA_SKKDR2 (*(vuint32*)(void*)(&__IPSBAR[0x1B0038])) -#define MCF_SKHA_SKKDR3 (*(vuint32*)(void*)(&__IPSBAR[0x1B003C])) -#define MCF_SKHA_SKKDR4 (*(vuint32*)(void*)(&__IPSBAR[0x1B0040])) -#define MCF_SKHA_SKKDR5 (*(vuint32*)(void*)(&__IPSBAR[0x1B0044])) -#define MCF_SKHA_SKKDRn(x) (*(vuint32*)(void*)(&__IPSBAR[0x1B0030+((x)*0x004)])) -#define MCF_SKHA_SKCR0 (*(vuint32*)(void*)(&__IPSBAR[0x1B0070])) -#define MCF_SKHA_SKCR1 (*(vuint32*)(void*)(&__IPSBAR[0x1B0074])) -#define MCF_SKHA_SKCR2 (*(vuint32*)(void*)(&__IPSBAR[0x1B0078])) -#define MCF_SKHA_SKCR3 (*(vuint32*)(void*)(&__IPSBAR[0x1B007C])) -#define MCF_SKHA_SKCR4 (*(vuint32*)(void*)(&__IPSBAR[0x1B0080])) -#define MCF_SKHA_SKCR5 (*(vuint32*)(void*)(&__IPSBAR[0x1B0084])) -#define MCF_SKHA_SKCR6 (*(vuint32*)(void*)(&__IPSBAR[0x1B0088])) -#define MCF_SKHA_SKCR7 (*(vuint32*)(void*)(&__IPSBAR[0x1B008C])) -#define MCF_SKHA_SKCR8 (*(vuint32*)(void*)(&__IPSBAR[0x1B0090])) -#define MCF_SKHA_SKCR9 (*(vuint32*)(void*)(&__IPSBAR[0x1B0094])) -#define MCF_SKHA_SKCR10 (*(vuint32*)(void*)(&__IPSBAR[0x1B0098])) -#define MCF_SKHA_SKCR11 (*(vuint32*)(void*)(&__IPSBAR[0x1B009C])) -#define MCF_SKHA_SKCRn(x) (*(vuint32*)(void*)(&__IPSBAR[0x1B0070+((x)*0x004)])) - -/* Bit definitions and macros for MCF_SKHA_SKMR */ -#define MCF_SKHA_SKMR_ALG(x) (((x)&0x00000003)<<0) -#define MCF_SKHA_SKMR_DIR (0x00000004) -#define MCF_SKHA_SKMR_CM(x) (((x)&0x00000003)<<3) -#define MCF_SKHA_SKMR_DKP (0x00000100) -#define MCF_SKHA_SKMR_CTRM(x) (((x)&0x0000000F)<<9) -#define MCF_SKHA_SKMR_CM_ECB (0x00000000) -#define MCF_SKHA_SKMR_CM_CBC (0x00000008) -#define MCF_SKHA_SKMR_CM_CTR (0x00000018) -#define MCF_SKHA_SKMR_DIR_DEC (0x00000000) -#define MCF_SKHA_SKMR_DIR_ENC (0x00000004) -#define MCF_SKHA_SKMR_ALG_AES (0x00000000) -#define MCF_SKHA_SKMR_ALG_DES (0x00000001) -#define MCF_SKHA_SKMR_ALG_TDES (0x00000002) - -/* Bit definitions and macros for MCF_SKHA_SKCR */ -#define MCF_SKHA_SKCR_IE (0x00000001) - -/* Bit definitions and macros for MCF_SKHA_SKCMR */ -#define MCF_SKHA_SKCMR_SWR (0x00000001) -#define MCF_SKHA_SKCMR_RI (0x00000002) -#define MCF_SKHA_SKCMR_CI (0x00000004) -#define MCF_SKHA_SKCMR_GO (0x00000008) - -/* Bit definitions and macros for MCF_SKHA_SKSR */ -#define MCF_SKHA_SKSR_INT (0x00000001) -#define MCF_SKHA_SKSR_DONE (0x00000002) -#define MCF_SKHA_SKSR_ERR (0x00000004) -#define MCF_SKHA_SKSR_RD (0x00000008) -#define MCF_SKHA_SKSR_BUSY (0x00000010) -#define MCF_SKHA_SKSR_IFL(x) (((x)&0x000000FF)<<16) -#define MCF_SKHA_SKSR_OFL(x) (((x)&0x000000FF)<<24) - -/* Bit definitions and macros for MCF_SKHA_SKIR */ -#define MCF_SKHA_SKIR_IFO (0x00000001) -#define MCF_SKHA_SKIR_OFU (0x00000002) -#define MCF_SKHA_SKIR_NEIF (0x00000004) -#define MCF_SKHA_SKIR_NEOF (0x00000008) -#define MCF_SKHA_SKIR_IME (0x00000010) -#define MCF_SKHA_SKIR_DSE (0x00000020) -#define MCF_SKHA_SKIR_KSE (0x00000040) -#define MCF_SKHA_SKIR_RMDP (0x00000080) -#define MCF_SKHA_SKIR_ERE (0x00000100) -#define MCF_SKHA_SKIR_KPE (0x00000200) -#define MCF_SKHA_SKIR_KRE (0x00000400) - -/* Bit definitions and macros for MCF_SKHA_SKIMR */ -#define MCF_SKHA_SKIMR_IFO (0x00000001) -#define MCF_SKHA_SKIMR_OFU (0x00000002) -#define MCF_SKHA_SKIMR_NEIF (0x00000004) -#define MCF_SKHA_SKIMR_NEOF (0x00000008) -#define MCF_SKHA_SKIMR_IME (0x00000010) -#define MCF_SKHA_SKIMR_DSE (0x00000020) -#define MCF_SKHA_SKIMR_KSE (0x00000040) -#define MCF_SKHA_SKIMR_RMDP (0x00000080) -#define MCF_SKHA_SKIMR_ERE (0x00000100) -#define MCF_SKHA_SKIMR_KPE (0x00000200) -#define MCF_SKHA_SKIMR_KRE (0x00000400) - -/* Bit definitions and macros for MCF_SKHA_SKKSR */ -#define MCF_SKHA_SKKSR_KEYSIZE(x) (((x)&0x0000003F)<<0) - -/********************************************************************/ - -#endif /* __MCF523X_SKHA_H__ */ diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_sram.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_sram.h deleted file mode 100644 index b40dda0e6..000000000 --- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_sram.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * These files are taken from the MCF523X source code example package - * which is available on the Freescale website. Freescale explicitly - * grants the redistribution and modification of these source files. - * The complete licensing information is available in the file - * LICENSE_FREESCALE.TXT. - * - * File: mcf523x_sram.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_SRAM_H__ -#define __MCF523X_SRAM_H__ - -/********************************************************************* -* -* 64KByte System SRAM (SRAM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_SRAM_RAMBAR (*(vuint32*)(void*)(&__IPSBAR[0x20000000])) - -/* Bit definitions and macros for MCF_SRAM_RAMBAR */ -#define MCF_SRAM_RAMBAR_V (0x00000001) -#define MCF_SRAM_RAMBAR_UD (0x00000002) -#define MCF_SRAM_RAMBAR_UC (0x00000004) -#define MCF_SRAM_RAMBAR_SD (0x00000008) -#define MCF_SRAM_RAMBAR_SC (0x00000010) -#define MCF_SRAM_RAMBAR_CI (0x00000020) -#define MCF_SRAM_RAMBAR_WP (0x00000100) -#define MCF_SRAM_RAMBAR_SPV (0x00000200) -#define MCF_SRAM_RAMBAR_PRI2 (0x00000400) -#define MCF_SRAM_RAMBAR_PRI1 (0x00000800) -#define MCF_SRAM_RAMBAR_BA(x) (((x)&0x0000FFFF)<<16) - -/********************************************************************/ - -#endif /* __MCF523X_SRAM_H__ */ diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_timer.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_timer.h deleted file mode 100644 index e9db74c27..000000000 --- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_timer.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - * These files are taken from the MCF523X source code example package - * which is available on the Freescale website. Freescale explicitly - * grants the redistribution and modification of these source files. - * The complete licensing information is available in the file - * LICENSE_FREESCALE.TXT. - * - * File: mcf523x_timer.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_TIMER_H__ -#define __MCF523X_TIMER_H__ - -/********************************************************************* -* -* DMA Timers (TIMER) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_TIMER_DTMR0 (*(vuint16*)(void*)(&__IPSBAR[0x000400])) -#define MCF_TIMER_DTXMR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000402])) -#define MCF_TIMER_DTER0 (*(vuint8 *)(void*)(&__IPSBAR[0x000403])) -#define MCF_TIMER_DTRR0 (*(vuint32*)(void*)(&__IPSBAR[0x000404])) -#define MCF_TIMER_DTCR0 (*(vuint32*)(void*)(&__IPSBAR[0x000408])) -#define MCF_TIMER_DTCN0 (*(vuint32*)(void*)(&__IPSBAR[0x00040C])) -#define MCF_TIMER_DTMR1 (*(vuint16*)(void*)(&__IPSBAR[0x000440])) -#define MCF_TIMER_DTXMR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000442])) -#define MCF_TIMER_DTER1 (*(vuint8 *)(void*)(&__IPSBAR[0x000443])) -#define MCF_TIMER_DTRR1 (*(vuint32*)(void*)(&__IPSBAR[0x000444])) -#define MCF_TIMER_DTCR1 (*(vuint32*)(void*)(&__IPSBAR[0x000448])) -#define MCF_TIMER_DTCN1 (*(vuint32*)(void*)(&__IPSBAR[0x00044C])) -#define MCF_TIMER_DTMR2 (*(vuint16*)(void*)(&__IPSBAR[0x000480])) -#define MCF_TIMER_DTXMR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000482])) -#define MCF_TIMER_DTER2 (*(vuint8 *)(void*)(&__IPSBAR[0x000483])) -#define MCF_TIMER_DTRR2 (*(vuint32*)(void*)(&__IPSBAR[0x000484])) -#define MCF_TIMER_DTCR2 (*(vuint32*)(void*)(&__IPSBAR[0x000488])) -#define MCF_TIMER_DTCN2 (*(vuint32*)(void*)(&__IPSBAR[0x00048C])) -#define MCF_TIMER_DTMR3 (*(vuint16*)(void*)(&__IPSBAR[0x0004C0])) -#define MCF_TIMER_DTXMR3 (*(vuint8 *)(void*)(&__IPSBAR[0x0004C2])) -#define MCF_TIMER_DTER3 (*(vuint8 *)(void*)(&__IPSBAR[0x0004C3])) -#define MCF_TIMER_DTRR3 (*(vuint32*)(void*)(&__IPSBAR[0x0004C4])) -#define MCF_TIMER_DTCR3 (*(vuint32*)(void*)(&__IPSBAR[0x0004C8])) -#define MCF_TIMER_DTCN3 (*(vuint32*)(void*)(&__IPSBAR[0x0004CC])) -#define MCF_TIMER_DTMR(x) (*(vuint16*)(void*)(&__IPSBAR[0x000400+((x)*0x040)])) -#define MCF_TIMER_DTXMR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000402+((x)*0x040)])) -#define MCF_TIMER_DTER(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000403+((x)*0x040)])) -#define MCF_TIMER_DTRR(x) (*(vuint32*)(void*)(&__IPSBAR[0x000404+((x)*0x040)])) -#define MCF_TIMER_DTCR(x) (*(vuint32*)(void*)(&__IPSBAR[0x000408+((x)*0x040)])) -#define MCF_TIMER_DTCN(x) (*(vuint32*)(void*)(&__IPSBAR[0x00040C+((x)*0x040)])) - -/* Bit definitions and macros for MCF_TIMER_DTMR */ -#define MCF_TIMER_DTMR_RST (0x0001) -#define MCF_TIMER_DTMR_CLK(x) (((x)&0x0003)<<1) -#define MCF_TIMER_DTMR_FRR (0x0008) -#define MCF_TIMER_DTMR_ORRI (0x0010) -#define MCF_TIMER_DTMR_OM (0x0020) -#define MCF_TIMER_DTMR_CE(x) (((x)&0x0003)<<6) -#define MCF_TIMER_DTMR_PS(x) (((x)&0x00FF)<<8) -#define MCF_TIMER_DTMR_CE_ANY (0x00C0) -#define MCF_TIMER_DTMR_CE_FALL (0x0080) -#define MCF_TIMER_DTMR_CE_RISE (0x0040) -#define MCF_TIMER_DTMR_CE_NONE (0x0000) -#define MCF_TIMER_DTMR_CLK_DTIN (0x0006) -#define MCF_TIMER_DTMR_CLK_DIV16 (0x0004) -#define MCF_TIMER_DTMR_CLK_DIV1 (0x0002) -#define MCF_TIMER_DTMR_CLK_STOP (0x0000) - -/* Bit definitions and macros for MCF_TIMER_DTXMR */ -#define MCF_TIMER_DTXMR_MODE16 (0x01) -#define MCF_TIMER_DTXMR_DMAEN (0x80) - -/* Bit definitions and macros for MCF_TIMER_DTER */ -#define MCF_TIMER_DTER_CAP (0x01) -#define MCF_TIMER_DTER_REF (0x02) - -/********************************************************************/ - -#endif /* __MCF523X_TIMER_H__ */ diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_uart.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_uart.h deleted file mode 100644 index 43a44a67f..000000000 --- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_uart.h +++ /dev/null @@ -1,186 +0,0 @@ -/* - * These files are taken from the MCF523X source code example package - * which is available on the Freescale website. Freescale explicitly - * grants the redistribution and modification of these source files. - * The complete licensing information is available in the file - * LICENSE_FREESCALE.TXT. - * - * File: mcf523x_uart.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_UART_H__ -#define __MCF523X_UART_H__ - -/********************************************************************* -* -* Universal Asynchronous Receiver Transmitter (UART) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_UART_UMR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000200])) -#define MCF_UART_USR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000204])) -#define MCF_UART_UCSR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000204])) -#define MCF_UART_UCR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000208])) -#define MCF_UART_URB0 (*(vuint8 *)(void*)(&__IPSBAR[0x00020C])) -#define MCF_UART_UTB0 (*(vuint8 *)(void*)(&__IPSBAR[0x00020C])) -#define MCF_UART_UIPCR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000210])) -#define MCF_UART_UACR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000210])) -#define MCF_UART_UISR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000214])) -#define MCF_UART_UIMR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000214])) -#define MCF_UART_UBG10 (*(vuint8 *)(void*)(&__IPSBAR[0x000218])) -#define MCF_UART_UBG20 (*(vuint8 *)(void*)(&__IPSBAR[0x00021C])) -#define MCF_UART_UIP0 (*(vuint8 *)(void*)(&__IPSBAR[0x000234])) -#define MCF_UART_UOP10 (*(vuint8 *)(void*)(&__IPSBAR[0x000238])) -#define MCF_UART_UOP00 (*(vuint8 *)(void*)(&__IPSBAR[0x00023C])) -#define MCF_UART_UMR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000240])) -#define MCF_UART_USR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000244])) -#define MCF_UART_UCSR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000244])) -#define MCF_UART_UCR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000248])) -#define MCF_UART_URB1 (*(vuint8 *)(void*)(&__IPSBAR[0x00024C])) -#define MCF_UART_UTB1 (*(vuint8 *)(void*)(&__IPSBAR[0x00024C])) -#define MCF_UART_UIPCR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000250])) -#define MCF_UART_UACR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000250])) -#define MCF_UART_UISR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000254])) -#define MCF_UART_UIMR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000254])) -#define MCF_UART_UBG11 (*(vuint8 *)(void*)(&__IPSBAR[0x000258])) -#define MCF_UART_UBG21 (*(vuint8 *)(void*)(&__IPSBAR[0x00025C])) -#define MCF_UART_UIP1 (*(vuint8 *)(void*)(&__IPSBAR[0x000274])) -#define MCF_UART_UOP11 (*(vuint8 *)(void*)(&__IPSBAR[0x000278])) -#define MCF_UART_UOP01 (*(vuint8 *)(void*)(&__IPSBAR[0x00027C])) -#define MCF_UART_UMR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000280])) -#define MCF_UART_USR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000284])) -#define MCF_UART_UCSR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000284])) -#define MCF_UART_UCR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000288])) -#define MCF_UART_URB2 (*(vuint8 *)(void*)(&__IPSBAR[0x00028C])) -#define MCF_UART_UTB2 (*(vuint8 *)(void*)(&__IPSBAR[0x00028C])) -#define MCF_UART_UIPCR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000290])) -#define MCF_UART_UACR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000290])) -#define MCF_UART_UISR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000294])) -#define MCF_UART_UIMR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000294])) -#define MCF_UART_UBG12 (*(vuint8 *)(void*)(&__IPSBAR[0x000298])) -#define MCF_UART_UBG22 (*(vuint8 *)(void*)(&__IPSBAR[0x00029C])) -#define MCF_UART_UIP2 (*(vuint8 *)(void*)(&__IPSBAR[0x0002B4])) -#define MCF_UART_UOP12 (*(vuint8 *)(void*)(&__IPSBAR[0x0002B8])) -#define MCF_UART_UOP02 (*(vuint8 *)(void*)(&__IPSBAR[0x0002BC])) -#define MCF_UART_UMR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000200+((x)*0x040)])) -#define MCF_UART_USR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000204+((x)*0x040)])) -#define MCF_UART_UCSR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000204+((x)*0x040)])) -#define MCF_UART_UCR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000208+((x)*0x040)])) -#define MCF_UART_URB(x) (*(vuint8 *)(void*)(&__IPSBAR[0x00020C+((x)*0x040)])) -#define MCF_UART_UTB(x) (*(vuint8 *)(void*)(&__IPSBAR[0x00020C+((x)*0x040)])) -#define MCF_UART_UIPCR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000210+((x)*0x040)])) -#define MCF_UART_UACR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000210+((x)*0x040)])) -#define MCF_UART_UISR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000214+((x)*0x040)])) -#define MCF_UART_UIMR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000214+((x)*0x040)])) -#define MCF_UART_UBG1(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000218+((x)*0x040)])) -#define MCF_UART_UBG2(x) (*(vuint8 *)(void*)(&__IPSBAR[0x00021C+((x)*0x040)])) -#define MCF_UART_UIP(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000234+((x)*0x040)])) -#define MCF_UART_UOP1(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000238+((x)*0x040)])) -#define MCF_UART_UOP0(x) (*(vuint8 *)(void*)(&__IPSBAR[0x00023C+((x)*0x040)])) - -/* Bit definitions and macros for MCF_UART_UMR */ -#define MCF_UART_UMR_BC(x) (((x)&0x03)<<0) -#define MCF_UART_UMR_PT (0x04) -#define MCF_UART_UMR_PM(x) (((x)&0x03)<<3) -#define MCF_UART_UMR_ERR (0x20) -#define MCF_UART_UMR_RXIRQ (0x40) -#define MCF_UART_UMR_RXRTS (0x80) -#define MCF_UART_UMR_SB(x) (((x)&0x0F)<<0) -#define MCF_UART_UMR_TXCTS (0x10) -#define MCF_UART_UMR_TXRTS (0x20) -#define MCF_UART_UMR_CM(x) (((x)&0x03)<<6) -#define MCF_UART_UMR_PM_MULTI_ADDR (0x1C) -#define MCF_UART_UMR_PM_MULTI_DATA (0x18) -#define MCF_UART_UMR_PM_NONE (0x10) -#define MCF_UART_UMR_PM_FORCE_HI (0x0C) -#define MCF_UART_UMR_PM_FORCE_LO (0x08) -#define MCF_UART_UMR_PM_ODD (0x04) -#define MCF_UART_UMR_PM_EVEN (0x00) -#define MCF_UART_UMR_BC_5 (0x00) -#define MCF_UART_UMR_BC_6 (0x01) -#define MCF_UART_UMR_BC_7 (0x02) -#define MCF_UART_UMR_BC_8 (0x03) -#define MCF_UART_UMR_CM_NORMAL (0x00) -#define MCF_UART_UMR_CM_ECHO (0x40) -#define MCF_UART_UMR_CM_LOCAL_LOOP (0x80) -#define MCF_UART_UMR_CM_REMOTE_LOOP (0xC0) -#define MCF_UART_UMR_SB_STOP_BITS_1 (0x07) -#define MCF_UART_UMR_SB_STOP_BITS_15 (0x08) -#define MCF_UART_UMR_SB_STOP_BITS_2 (0x0F) - -/* Bit definitions and macros for MCF_UART_USR */ -#define MCF_UART_USR_RXRDY (0x01) -#define MCF_UART_USR_FFULL (0x02) -#define MCF_UART_USR_TXRDY (0x04) -#define MCF_UART_USR_TXEMP (0x08) -#define MCF_UART_USR_OE (0x10) -#define MCF_UART_USR_PE (0x20) -#define MCF_UART_USR_FE (0x40) -#define MCF_UART_USR_RB (0x80) - -/* Bit definitions and macros for MCF_UART_UCSR */ -#define MCF_UART_UCSR_TCS(x) (((x)&0x0F)<<0) -#define MCF_UART_UCSR_RCS(x) (((x)&0x0F)<<4) -#define MCF_UART_UCSR_RCS_SYS_CLK (0xD0) -#define MCF_UART_UCSR_RCS_CTM16 (0xE0) -#define MCF_UART_UCSR_RCS_CTM (0xF0) -#define MCF_UART_UCSR_TCS_SYS_CLK (0x0D) -#define MCF_UART_UCSR_TCS_CTM16 (0x0E) -#define MCF_UART_UCSR_TCS_CTM (0x0F) - -/* Bit definitions and macros for MCF_UART_UCR */ -#define MCF_UART_UCR_RXC(x) (((x)&0x03)<<0) -#define MCF_UART_UCR_TXC(x) (((x)&0x03)<<2) -#define MCF_UART_UCR_MISC(x) (((x)&0x07)<<4) -#define MCF_UART_UCR_NONE (0x00) -#define MCF_UART_UCR_STOP_BREAK (0x70) -#define MCF_UART_UCR_START_BREAK (0x60) -#define MCF_UART_UCR_BKCHGINT (0x50) -#define MCF_UART_UCR_RESET_ERROR (0x40) -#define MCF_UART_UCR_RESET_TX (0x30) -#define MCF_UART_UCR_RESET_RX (0x20) -#define MCF_UART_UCR_RESET_MR (0x10) -#define MCF_UART_UCR_TX_DISABLED (0x08) -#define MCF_UART_UCR_TX_ENABLED (0x04) -#define MCF_UART_UCR_RX_DISABLED (0x02) -#define MCF_UART_UCR_RX_ENABLED (0x01) - -/* Bit definitions and macros for MCF_UART_UIPCR */ -#define MCF_UART_UIPCR_CTS (0x01) -#define MCF_UART_UIPCR_COS (0x10) - -/* Bit definitions and macros for MCF_UART_UACR */ -#define MCF_UART_UACR_IEC (0x01) - -/* Bit definitions and macros for MCF_UART_UISR */ -#define MCF_UART_UISR_TXRDY (0x01) -#define MCF_UART_UISR_RXRDY_FU (0x02) -#define MCF_UART_UISR_DB (0x04) -#define MCF_UART_UISR_RXFTO (0x08) -#define MCF_UART_UISR_TXFIFO (0x10) -#define MCF_UART_UISR_RXFIFO (0x20) -#define MCF_UART_UISR_COS (0x80) - -/* Bit definitions and macros for MCF_UART_UIMR */ -#define MCF_UART_UIMR_TXRDY (0x01) -#define MCF_UART_UIMR_RXRDY_FU (0x02) -#define MCF_UART_UIMR_DB (0x04) -#define MCF_UART_UIMR_COS (0x80) - -/* Bit definitions and macros for MCF_UART_UIP */ -#define MCF_UART_UIP_CTS (0x01) - -/* Bit definitions and macros for MCF_UART_UOP1 */ -#define MCF_UART_UOP1_RTS (0x01) - -/* Bit definitions and macros for MCF_UART_UOP0 */ -#define MCF_UART_UOP0_RTS (0x01) - -/********************************************************************/ - -#endif /* __MCF523X_UART_H__ */ diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_wtm.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_wtm.h deleted file mode 100644 index 489486791..000000000 --- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_wtm.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - * These files are taken from the MCF523X source code example package - * which is available on the Freescale website. Freescale explicitly - * grants the redistribution and modification of these source files. - * The complete licensing information is available in the file - * LICENSE_FREESCALE.TXT. - * - * File: mcf523x_wtm.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_WTM_H__ -#define __MCF523X_WTM_H__ - -/********************************************************************* -* -* Watchdog Timer Modules (WTM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_WTM_WCR (*(vuint16*)(void*)(&__IPSBAR[0x140000])) -#define MCF_WTM_WMR (*(vuint16*)(void*)(&__IPSBAR[0x140002])) -#define MCF_WTM_WCNTR (*(vuint16*)(void*)(&__IPSBAR[0x140004])) -#define MCF_WTM_WSR (*(vuint16*)(void*)(&__IPSBAR[0x140006])) - -/* Bit definitions and macros for MCF_WTM_WCR */ -#define MCF_WTM_WCR_EN (0x0001) -#define MCF_WTM_WCR_HALTED (0x0002) -#define MCF_WTM_WCR_DOZE (0x0004) -#define MCF_WTM_WCR_WAIT (0x0008) - -/* Bit definitions and macros for MCF_WTM_WMR */ -#define MCF_WTM_WMR_WM0 (0x0001) -#define MCF_WTM_WMR_WM1 (0x0002) -#define MCF_WTM_WMR_WM2 (0x0004) -#define MCF_WTM_WMR_WM3 (0x0008) -#define MCF_WTM_WMR_WM4 (0x0010) -#define MCF_WTM_WMR_WM5 (0x0020) -#define MCF_WTM_WMR_WM6 (0x0040) -#define MCF_WTM_WMR_WM7 (0x0080) -#define MCF_WTM_WMR_WM8 (0x0100) -#define MCF_WTM_WMR_WM9 (0x0200) -#define MCF_WTM_WMR_WM10 (0x0400) -#define MCF_WTM_WMR_WM11 (0x0800) -#define MCF_WTM_WMR_WM12 (0x1000) -#define MCF_WTM_WMR_WM13 (0x2000) -#define MCF_WTM_WMR_WM14 (0x4000) -#define MCF_WTM_WMR_WM15 (0x8000) - -/* Bit definitions and macros for MCF_WTM_WCNTR */ -#define MCF_WTM_WCNTR_WC0 (0x0001) -#define MCF_WTM_WCNTR_WC1 (0x0002) -#define MCF_WTM_WCNTR_WC2 (0x0004) -#define MCF_WTM_WCNTR_WC3 (0x0008) -#define MCF_WTM_WCNTR_WC4 (0x0010) -#define MCF_WTM_WCNTR_WC5 (0x0020) -#define MCF_WTM_WCNTR_WC6 (0x0040) -#define MCF_WTM_WCNTR_WC7 (0x0080) -#define MCF_WTM_WCNTR_WC8 (0x0100) -#define MCF_WTM_WCNTR_WC9 (0x0200) -#define MCF_WTM_WCNTR_WC10 (0x0400) -#define MCF_WTM_WCNTR_WC11 (0x0800) -#define MCF_WTM_WCNTR_WC12 (0x1000) -#define MCF_WTM_WCNTR_WC13 (0x2000) -#define MCF_WTM_WCNTR_WC14 (0x4000) -#define MCF_WTM_WCNTR_WC15 (0x8000) - -/* Bit definitions and macros for MCF_WTM_WSR */ -#define MCF_WTM_WSR_WS0 (0x0001) -#define MCF_WTM_WSR_WS1 (0x0002) -#define MCF_WTM_WSR_WS2 (0x0004) -#define MCF_WTM_WSR_WS3 (0x0008) -#define MCF_WTM_WSR_WS4 (0x0010) -#define MCF_WTM_WSR_WS5 (0x0020) -#define MCF_WTM_WSR_WS6 (0x0040) -#define MCF_WTM_WSR_WS7 (0x0080) -#define MCF_WTM_WSR_WS8 (0x0100) -#define MCF_WTM_WSR_WS9 (0x0200) -#define MCF_WTM_WSR_WS10 (0x0400) -#define MCF_WTM_WSR_WS11 (0x0800) -#define MCF_WTM_WSR_WS12 (0x1000) -#define MCF_WTM_WSR_WS13 (0x2000) -#define MCF_WTM_WSR_WS14 (0x4000) -#define MCF_WTM_WSR_WS15 (0x8000) - -/********************************************************************/ - -#endif /* __MCF523X_WTM_H__ */ diff --git a/Demo/MCF5235_GCC/include/arch/mcf5xxx.h b/Demo/MCF5235_GCC/include/arch/mcf5xxx.h deleted file mode 100644 index 692d690e1..000000000 --- a/Demo/MCF5235_GCC/include/arch/mcf5xxx.h +++ /dev/null @@ -1,196 +0,0 @@ -/* - * These files are taken from the MCF523X source code example package - * which is available on the Freescale website. Freescale explicitly - * grants the redistribution and modification of these source files. - * The complete licensing information is available in the file - * LICENSE_FREESCALE.TXT. - * - * File: mcf5xxx.h - * Purpose: Definitions common to all ColdFire processors - * - * Notes: - */ - -#ifndef _CPU_MCF5XXX_H -#define _CPU_MCF5XXX_H - -/***********************************************************************/ -/* - * Misc. Defines - */ - -#ifdef FALSE -#undef FALSE -#endif -#define FALSE (0) - -#ifdef TRUE -#undef TRUE -#endif -#define TRUE (1) - -#ifdef NULL -#undef NULL -#endif -#define NULL (0) - -/***********************************************************************/ -/* - * The basic data types - */ - -typedef unsigned char uint8; /* 8 bits */ -typedef unsigned short int uint16; /* 16 bits */ -typedef unsigned long int uint32; /* 32 bits */ - -typedef signed char int8; /* 8 bits */ -typedef signed short int int16; /* 16 bits */ -typedef signed long int int32; /* 32 bits */ - -typedef volatile uint8 vuint8; /* 8 bits */ -typedef volatile uint16 vuint16; /* 16 bits */ -typedef volatile uint32 vuint32; /* 32 bits */ - -/***********************************************************************/ -/* - * Common M68K & ColdFire definitions - */ - -#define ADDRESS uint32 -#define INSTRUCTION uint16 -#define ILLEGAL 0x4AFC -#define CPU_WORD_SIZE 16 - -#define MCF5XXX_SR_T (0x8000) -#define MCF5XXX_SR_S (0x2000) -#define MCF5XXX_SR_M (0x1000) -#define MCF5XXX_SR_IPL (0x0700) -#define MCF5XXX_SR_IPL_0 (0x0000) -#define MCF5XXX_SR_IPL_1 (0x0100) -#define MCF5XXX_SR_IPL_2 (0x0200) -#define MCF5XXX_SR_IPL_3 (0x0300) -#define MCF5XXX_SR_IPL_4 (0x0400) -#define MCF5XXX_SR_IPL_5 (0x0500) -#define MCF5XXX_SR_IPL_6 (0x0600) -#define MCF5XXX_SR_IPL_7 (0x0700) -#define MCF5XXX_SR_X (0x0010) -#define MCF5XXX_SR_N (0x0008) -#define MCF5XXX_SR_Z (0x0004) -#define MCF5XXX_SR_V (0x0002) -#define MCF5XXX_SR_C (0x0001) - -#define MCF5XXX_CACR_CENB (0x80000000) -#define MCF5XXX_CACR_CPDI (0x10000000) -#define MCF5XXX_CACR_CPD (0x10000000) -#define MCF5XXX_CACR_CFRZ (0x08000000) -#define MCF5XXX_CACR_CINV (0x01000000) -#define MCF5XXX_CACR_DIDI (0x00800000) -#define MCF5XXX_CACR_DISD (0x00400000) -#define MCF5XXX_CACR_INVI (0x00200000) -#define MCF5XXX_CACR_INVD (0x00100000) -#define MCF5XXX_CACR_CEIB (0x00000400) -#define MCF5XXX_CACR_DCM_WR (0x00000000) -#define MCF5XXX_CACR_DCM_CB (0x00000100) -#define MCF5XXX_CACR_DCM_IP (0x00000200) -#define MCF5XXX_CACR_DCM (0x00000200) -#define MCF5XXX_CACR_DCM_II (0x00000300) -#define MCF5XXX_CACR_DBWE (0x00000100) -#define MCF5XXX_CACR_DWP (0x00000020) -#define MCF5XXX_CACR_EUST (0x00000010) -#define MCF5XXX_CACR_CLNF_00 (0x00000000) -#define MCF5XXX_CACR_CLNF_01 (0x00000002) -#define MCF5XXX_CACR_CLNF_10 (0x00000004) -#define MCF5XXX_CACR_CLNF_11 (0x00000006) - -#define MCF5XXX_ACR_AB(a) ((a)&0xFF000000) -#define MCF5XXX_ACR_AM(a) (((a)&0xFF000000) >> 8) -#define MCF5XXX_ACR_EN (0x00008000) -#define MCF5XXX_ACR_SM_USER (0x00000000) -#define MCF5XXX_ACR_SM_SUPER (0x00002000) -#define MCF5XXX_ACR_SM_IGNORE (0x00006000) -#define MCF5XXX_ACR_ENIB (0x00000080) -#define MCF5XXX_ACR_CM (0x00000040) -#define MCF5XXX_ACR_DCM_WR (0x00000000) -#define MCF5XXX_ACR_DCM_CB (0x00000020) -#define MCF5XXX_ACR_DCM_IP (0x00000040) -#define MCF5XXX_ACR_DCM_II (0x00000060) -#define MCF5XXX_ACR_CM (0x00000040) -#define MCF5XXX_ACR_BWE (0x00000020) -#define MCF5XXX_ACR_WP (0x00000004) - -#define MCF5XXX_RAMBAR_BA(a) ((a)&0xFFFFC000) -#define MCF5XXX_RAMBAR_PRI_00 (0x00000000) -#define MCF5XXX_RAMBAR_PRI_01 (0x00004000) -#define MCF5XXX_RAMBAR_PRI_10 (0x00008000) -#define MCF5XXX_RAMBAR_PRI_11 (0x0000C000) -#define MCF5XXX_RAMBAR_WP (0x00000100) -#define MCF5XXX_RAMBAR_CI (0x00000020) -#define MCF5XXX_RAMBAR_SC (0x00000010) -#define MCF5XXX_RAMBAR_SD (0x00000008) -#define MCF5XXX_RAMBAR_UC (0x00000004) -#define MCF5XXX_RAMBAR_UD (0x00000002) -#define MCF5XXX_RAMBAR_V (0x00000001) - -/***********************************************************************/ -/* - * The ColdFire family of processors has a simplified exception stack - * frame that looks like the following: - * - * 3322222222221111 111111 - * 1098765432109876 5432109876543210 - * 8 +----------------+----------------+ - * | Program Counter | - * 4 +----------------+----------------+ - * |FS/Fmt/Vector/FS| SR | - * SP --> 0 +----------------+----------------+ - * - * The stack self-aligns to a 4-byte boundary at an exception, with - * the FS/Fmt/Vector/FS field indicating the size of the adjustment - * (SP += 0,1,2,3 bytes). - */ - -#define MCF5XXX_RD_SF_FORMAT(PTR) \ - ((*((uint16 *)(PTR)) >> 12) & 0x00FF) - -#define MCF5XXX_RD_SF_VECTOR(PTR) \ - ((*((uint16 *)(PTR)) >> 2) & 0x00FF) - -#define MCF5XXX_RD_SF_FS(PTR) \ - ( ((*((uint16 *)(PTR)) & 0x0C00) >> 8) | (*((uint16 *)(PTR)) & 0x0003) ) - -#define MCF5XXX_SF_SR(PTR) *((uint16 *)(PTR)+1) -#define MCF5XXX_SF_PC(PTR) *((uint32 *)(PTR)+1) - -/********************************************************************/ -/* - * Functions provided by mcf5xxx.s - */ - -int asm_set_ipl (uint32); -void mcf5xxx_wr_cacr (uint32); -void mcf5xxx_wr_acr0 (uint32); -void mcf5xxx_wr_acr1 (uint32); -void mcf5xxx_wr_acr2 (uint32); -void mcf5xxx_wr_acr3 (uint32); -void mcf5xxx_wr_other_a7 (uint32); -void mcf5xxx_wr_other_sp (uint32); -void mcf5xxx_wr_vbr (uint32); -void mcf5xxx_wr_macsr (uint32); -void mcf5xxx_wr_mask (uint32); -void mcf5xxx_wr_acc0 (uint32); -void mcf5xxx_wr_accext01 (uint32); -void mcf5xxx_wr_accext23 (uint32); -void mcf5xxx_wr_acc1 (uint32); -void mcf5xxx_wr_acc2 (uint32); -void mcf5xxx_wr_acc3 (uint32); -void mcf5xxx_wr_sr (uint32); -void mcf5xxx_wr_rambar0 (uint32); -void mcf5xxx_wr_rambar1 (uint32); -void mcf5xxx_wr_mbar (uint32); -void mcf5xxx_wr_mbar0 (uint32); -void mcf5xxx_wr_mbar1 (uint32); - -/********************************************************************/ - -#endif /* _CPU_MCF5XXX_H */ - diff --git a/Demo/MCF5235_GCC/m5235-ram.ld b/Demo/MCF5235_GCC/m5235-ram.ld deleted file mode 100644 index 7119d3f51..000000000 --- a/Demo/MCF5235_GCC/m5235-ram.ld +++ /dev/null @@ -1,119 +0,0 @@ -STARTUP(system/crt0.o) -INPUT(system/vector.o) -OUTPUT_ARCH(m68k) -SEARCH_DIR(.) -GROUP(-lc -lgcc) - -__DYNAMIC = 0; - -MEMORY -{ - sdram (rwx) : ORIGIN = 0x00000000, LENGTH = 0x01000000 - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 - ipsbar (rwx) : ORIGIN = 0x40000000, LENGTH = 0x40000000 - flash (rwx) : ORIGIN = 0x80000000, LENGTH = 0x00080000 -} - -PROVIDE (__stack = 0x2000FFFC); - -SECTIONS -{ - .sdram : {} > sdram - .ipsbar : {} > ipsbar - .sram (NOLOAD) : { *(.vector_ram); *(.nbuf) } > sram - .flash : {} > flash - - .text : - { - __text_start = . ; - *(.vector_rom) - . = ALIGN (0x100); - *(.text) - . = ALIGN (16); - - *(.eh_frame) - . = ALIGN (16); - - *(.gnu.linkonce.t.*) - - . = ALIGN(0x4); - __CTOR_LIST__ = .; - ___CTOR_LIST__ = .; - LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2) - *(.ctors) - LONG(0) - __CTOR_END__ = .; - __DTOR_LIST__ = .; - ___DTOR_LIST__ = .; - LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2) - *(.dtors) - LONG(0) - __DTOR_END__ = .; - *(.rodata) - *(.rodata.*) - *(.gcc_except_table) - - . = ALIGN(0x2); - __INIT_SECTION__ = . ; - LONG (0x4e560000) /* linkw %fp,#0 */ - *(.init) - SHORT (0x4e5e) /* unlk %fp */ - SHORT (0x4e75) /* rts */ - - __FINI_SECTION__ = . ; - LONG (0x4e560000) /* linkw %fp,#0 */ - *(.fini) - SHORT (0x4e5e) /* unlk %fp */ - SHORT (0x4e75) /* rts */ - - *(.lit) - . = ALIGN(16); - _etext = .; - etext = .; - } > sdram - - .data : - { - copy_start = .; - *(.shdata) - *(.data) - *(.gnu.linkonce.d.*) - . = ALIGN (16); - _edata = .; - copy_end = .; - } > sdram - __data_load_start = LOADADDR(.data); - __data_load_end = __data_load_start + SIZEOF(.data); - - .bss : - { - . = ALIGN(0x4); - __bss_start = . ; - *(.shbss) - *(.bss) - *(COMMON) - _end = ALIGN (0x8); - __end = _end; - } > sdram - - .stab 0 (NOLOAD) : - { - *(.stab) - } - - .stabstr 0 (NOLOAD) : - { - *(.stabstr) - } -} - -__IPSBAR = ADDR(.ipsbar); - -__SDRAM = ADDR(.sdram); -__SDRAM_SIZE = SIZEOF(.sdram); - -__SRAM = ADDR(.sram); -__SRAM_SIZE = SIZEOF(.sram); - -__FLASH = ADDR(.flash); -__FLASH_SIZE = SIZEOF(.flash); diff --git a/Demo/MCF5235_GCC/m5235-rom.ld b/Demo/MCF5235_GCC/m5235-rom.ld deleted file mode 100644 index 7119d3f51..000000000 --- a/Demo/MCF5235_GCC/m5235-rom.ld +++ /dev/null @@ -1,119 +0,0 @@ -STARTUP(system/crt0.o) -INPUT(system/vector.o) -OUTPUT_ARCH(m68k) -SEARCH_DIR(.) -GROUP(-lc -lgcc) - -__DYNAMIC = 0; - -MEMORY -{ - sdram (rwx) : ORIGIN = 0x00000000, LENGTH = 0x01000000 - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 - ipsbar (rwx) : ORIGIN = 0x40000000, LENGTH = 0x40000000 - flash (rwx) : ORIGIN = 0x80000000, LENGTH = 0x00080000 -} - -PROVIDE (__stack = 0x2000FFFC); - -SECTIONS -{ - .sdram : {} > sdram - .ipsbar : {} > ipsbar - .sram (NOLOAD) : { *(.vector_ram); *(.nbuf) } > sram - .flash : {} > flash - - .text : - { - __text_start = . ; - *(.vector_rom) - . = ALIGN (0x100); - *(.text) - . = ALIGN (16); - - *(.eh_frame) - . = ALIGN (16); - - *(.gnu.linkonce.t.*) - - . = ALIGN(0x4); - __CTOR_LIST__ = .; - ___CTOR_LIST__ = .; - LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2) - *(.ctors) - LONG(0) - __CTOR_END__ = .; - __DTOR_LIST__ = .; - ___DTOR_LIST__ = .; - LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2) - *(.dtors) - LONG(0) - __DTOR_END__ = .; - *(.rodata) - *(.rodata.*) - *(.gcc_except_table) - - . = ALIGN(0x2); - __INIT_SECTION__ = . ; - LONG (0x4e560000) /* linkw %fp,#0 */ - *(.init) - SHORT (0x4e5e) /* unlk %fp */ - SHORT (0x4e75) /* rts */ - - __FINI_SECTION__ = . ; - LONG (0x4e560000) /* linkw %fp,#0 */ - *(.fini) - SHORT (0x4e5e) /* unlk %fp */ - SHORT (0x4e75) /* rts */ - - *(.lit) - . = ALIGN(16); - _etext = .; - etext = .; - } > sdram - - .data : - { - copy_start = .; - *(.shdata) - *(.data) - *(.gnu.linkonce.d.*) - . = ALIGN (16); - _edata = .; - copy_end = .; - } > sdram - __data_load_start = LOADADDR(.data); - __data_load_end = __data_load_start + SIZEOF(.data); - - .bss : - { - . = ALIGN(0x4); - __bss_start = . ; - *(.shbss) - *(.bss) - *(COMMON) - _end = ALIGN (0x8); - __end = _end; - } > sdram - - .stab 0 (NOLOAD) : - { - *(.stab) - } - - .stabstr 0 (NOLOAD) : - { - *(.stabstr) - } -} - -__IPSBAR = ADDR(.ipsbar); - -__SDRAM = ADDR(.sdram); -__SDRAM_SIZE = SIZEOF(.sdram); - -__SRAM = ADDR(.sram); -__SRAM_SIZE = SIZEOF(.sram); - -__FLASH = ADDR(.flash); -__FLASH_SIZE = SIZEOF(.flash); diff --git a/Demo/MCF5235_GCC/m5235.gdb b/Demo/MCF5235_GCC/m5235.gdb deleted file mode 100644 index 545fbea31..000000000 --- a/Demo/MCF5235_GCC/m5235.gdb +++ /dev/null @@ -1,134 +0,0 @@ -set $IPSBAR = 0x40000000 - -set $DCR = $IPSBAR + 0x000040 -set $DACR0 = $IPSBAR + 0x000048 -set $DMR0 = $IPSBAR + 0x00004C - -set $CSAR0 = $IPSBAR + 0x000080 -set $CSMR0 = $IPSBAR + 0x000084 -set $CSCR0 = $IPSBAR + 0x00008A - -set $PAR_SDRAM = $IPSBAR + 0x100046 -set $PAR_AD = $IPSBAR + 0x100040 - -set $WCR = $IPSBAR + 0x140000 - -define delay - set $delay = 0 - while ($delay < 20000) - set $delay += 1 - end -end - -define delay_memsync - set $delay = 0 - while ($delay < 10000) - set $delay += 1 - end -end - -define setup-cs - # 2MB FLASH on CS0 at 0x80000000 - set *(unsigned short *)$CSAR0 = 0x00008000 - set *(unsigned long *)$CSMR0 = 0x001F0101 - set *(unsigned short *)$CSCR0 = 0x00001980 -end - -define setup-sdram - # Set PAR_SDRAM to allow SDRAM signals to be enable - set *(unsigned char *)$PAR_SDRAM = 0x3F - # Set PAR_AD to allow 32-bit SDRAM if the external boot device is 16-bit - set *(unsigned char *)$PAR_AD = 0xE1 - - # SDRAM - set *(unsigned short *)$DCR = 0x0446 - set *(unsigned long *)$DACR0 = 0x00001300 - set *(unsigned long *)$DMR0 = 0x00FC0001 - - # Set IP in DACR and init precharge. - set *(unsigned long *)$DACR0 |= 0x00000008 - set *(0x00000000) = 0xAA55AA55 - delay - - # Set RE in DACR - set *(unsigned long *)$DACR0 |= 0x00008000 - # Issue IMRS - set *(unsigned long *)$DACR0 |= 0x00000040 - set *(0x00000400) = 0xAA55AA55 - delay -end - -define setup-other - # Turn Off WCR - set *(unsigned char *)$WCR = 0x00 -end - -define setup-and-load - bdm-reset - - # Set VBR to the vector table. - set $vbr = 0x00000000 - # Set internal SRAM to start at 0x20000000 - set $rambar = 0x20000001 - - setup-other - setup-cs - setup-sdram -end - -define debug-sramtest - set $srambase = 0x20000000 - set $sramsize = 0x00010000 - set $j = 0 - printf "Testing SRAM : 0x%08X - 0x%08X\n", $srambase, ($srambase + $sramsize) - set $i = $srambase - while $i < ($srambase + $sramsize) - set *(unsigned long *)($i) = 0xAA55AA55 - delay_memsync - if 0xAA55AA55 != *(unsigned long *)$i - printf " 0x%08X = FAIL\n", $i - else - printf " 0x%08X = OK", $i - if $j % 4 == 3 - printf "\n" - end - set $j = $j + 1 - end - set $i = $i + 0x400 - end -en - -define debug-ramtest - set $sdrambase = 0x00000000 - set $sdramsize = 0x01000000 - set $j = 0 - printf "Testing SDRAM : 0x%08X - 0x%08X\n", $sdrambase, ($sdrambase + $sdramsize) - set $i = $sdrambase - while $i < ($sdrambase + $sdramsize) - set *(unsigned long *)($i) = 0xAA55AA55 - delay_memsync - if 0xAA55AA55 != *(unsigned long *)$i - printf " 0x%08X = FAIL\n", $i - else - printf " 0x%08X = OK", $i - if $j % 4 == 3 - printf "\n" - end - set $j = $j + 1 - end - set $i = $i + 0x10000 - end - printf "\n" -end - -define execute - set $pc = *(long *)0x00000004 - tbreak main - tk gdbtk_update -end - -define debug-printexception - printf "vector: %d", *(unsigned short *)$sp >> 2 &0x1F - printf "old pc: 0x%08x", *(unsigned long *)($sp + 4) - printf "old sr: 0x%02x", *(unsigned short *)($sp + 2) -end diff --git a/Demo/MCF5235_GCC/system/crt0.S b/Demo/MCF5235_GCC/system/crt0.S deleted file mode 100644 index 21954bcb1..000000000 --- a/Demo/MCF5235_GCC/system/crt0.S +++ /dev/null @@ -1,115 +0,0 @@ -/* - FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - .title "crt0.S" - - .extern main - .extern __stack - .extern __bss_start - .extern __text_start - .extern init_main - - .equ MCF5XXX_RAMBAR_SPV, 0x00000200 - .equ MCF5XXX_RAMBAR_V, 0x00000001 - .global start - - .align 4 -debug: - .word 0x2C80 /* write to CSR */ - .word 0x0010 - .word 0x0400 - .word 0x0000 - -start: - /* disable all interrupts on startup. */ - move.w #0x2700, sr - - /* prepare internal SRAM. */ - move.l #__SRAM, d0 - ori.l #( MCF5XXX_RAMBAR_SPV | MCF5XXX_RAMBAR_V ), d0 - movec d0, rambar - - /* prepare stack and frame pointer. */ - move.l #__stack, sp - link a6, #-8 - - /* initialize hardware. */ - jsr init_main - - /* zero out the bss section. */ - move.l #__bss_start, d1 - move.l #_end, d0 - cmp.l d0, d1 - jbeq 3f - move.l d1, a0 - sub.l d1, d0 - subq.l #1, d0 -2: - clr.b (a0)+ - subq.l #1, d0 - jbpl 2b -3: - - /* Relocate the data section. */ - move.l #__data_load_start, %a0 /* .data in ROM */ - move.l #copy_start, %a1 /* .data in RAM */ - - /* Test if the two sections overlap. This is the case when we are working - * with the debugger and the debugger loads the .data section. - */ - cmpa.l %a0, %a1 - beq 2f -1: - /* Have we already copied everything. */ - cmpa.l #__data_load_end, %a0 - beq 2f - move.b (%a0)+, (%a1)+ - bra 1b - -2: - - /* C library */ - move.l #__FINI_SECTION__, -(%sp) - jsr atexit - jsr __INIT_SECTION__ - - /* call main(int argc, char *argv[] */ - move.l #0, -(sp) - move.l #0, -(sp) - move.l #0, -(sp) - jsr main - lea (sp, 12), %sp - - /* stop on exit from main. */ -1: - halt - diff --git a/Demo/MCF5235_GCC/system/init.c b/Demo/MCF5235_GCC/system/init.c deleted file mode 100644 index 74957f35e..000000000 --- a/Demo/MCF5235_GCC/system/init.c +++ /dev/null @@ -1,743 +0,0 @@ -/* - FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#include "mcf5xxx.h" -#include "mcf523x.h" - -/* Function prototypes */ -void init_main( void ); -static void disable_interrupts( void ); -static void disable_watchdog_timer( void ); -static void disable_cache( void ); -static void init_ipsbar( void ); -static void init_basics( void ); -static void init_clock_config( void ); -static void init_chip_selects( void ); -static void init_bus_config( void ); -static void init_cache( void ); -static void init_eport( void ); -static void init_flexcan( void ); -static void init_power_management( void ); -static void init_dma_timers( void ); -static void init_interrupt_timers( void ); -static void init_watchdog_timers( void ); -static void init_pin_assignments( void ); -static void init_sdram_controller( void ); -static void init_interrupt_controller( void ); - - -/********************************************************************* -* init_main - Main entry point for initialisation code * -**********************************************************************/ -void -init_main( void ) -{ - - /* Initialise base address of peripherals, VBR, etc */ - init_ipsbar( ); - init_basics( ); - init_clock_config( ); - - /* Disable interrupts, watchdog timer, cache */ - disable_interrupts( ); - disable_watchdog_timer( ); - disable_cache( ); - - /* Initialise individual modules */ - init_chip_selects( ); - init_bus_config( ); - init_cache( ); - init_eport( ); - init_flexcan( ); - init_power_management( ); - init_dma_timers( ); - init_interrupt_timers( ); - init_watchdog_timers( ); - init_pin_assignments( ); - init_sdram_controller( ); - - /* Initialise interrupt controller */ - init_interrupt_controller( ); -} - -/********************************************************************* -* disable_interrupts - Disable all interrupt sources * -**********************************************************************/ -static void -disable_interrupts( void ) -{ - vuint8 *p; - int i; - - - /* Set ICR008-ICR063 to 0x0 */ - p = ( vuint8 * ) & MCF_INTC0_ICR8; - for( i = 8; i <= 63; i++ ) - *p++ = 0x0; - - /* Set ICR108-ICR163 to 0x0 */ - p = ( vuint8 * ) & MCF_INTC1_ICR8; - for( i = 108; i <= 163; i++ ) - *p++ = 0x0; -} - - -/********************************************************************* -* disable_watchdog_timer - Disable system watchdog timer * -**********************************************************************/ -static void -disable_watchdog_timer( void ) -{ - - /* Disable Core Watchdog Timer */ - MCF_SCM_CWCR = 0; -} - -/********************************************************************* -* disable_cache - Disable and invalidate cache * -**********************************************************************/ -static void -disable_cache( void ) -{ - asm ( "move.l #0x01000000, %d0" ); - asm ( "movec %d0, %CACR" ); -} - -/********************************************************************* -* init_basics - Configuration Information & VBR * -**********************************************************************/ -static void -init_basics( void ) -{ - int i; - extern uint32 __RAMVEC[]; - extern uint32 __ROMVEC[]; - - /* Transfer size not driven on SIZ[1:0] pins during external cycles - Processor Status (PST) and Debug Data (DDATA) functions disabled - Bus monitor disabled - Output pads configured for full strength - */ - MCF_CCM_CCR = ( 0x1 << 15 ) | MCF_CCM_CCR_BME; - - /* Set up RAM vectors */ - for( i = 0; i < 256; i++ ) - - { - __RAMVEC[i] = __ROMVEC[i]; - } - asm( "move.l %0,%%d0": :"i"( __RAMVEC ) ); - asm( "movec %d0,%vbr" ); -} - - -/********************************************************************* -* init_clock_config - Clock Module * -**********************************************************************/ -static void -init_clock_config( void ) -{ - /* Clock module uses normal PLL mode with 25.0000 MHz external reference (Fref) - MFD = 0, RFD = 1 - Bus clock frequency = 25.00 MHz - Processor clock frequency = 2 x bus clock = 50.00 MHz - Frequency Modulation disabled - Loss of clock detection disabled - Reset/Interrupt on loss of lock disabled - */ - MCF_FMPLL_SYNCR = 0x00100000; /* Set RFD=RFD+1 to avoid frequency overshoot */ - while( ( MCF_FMPLL_SYNSR & 0x08 ) == 0 ) /* Wait for PLL to lock */ - ; - MCF_FMPLL_SYNCR = 0x00080000; /* Set desired RFD */ - while( ( MCF_FMPLL_SYNSR & 0x08 ) == 0 ) /* Wait for PLL to lock */ - ; -} - - -/********************************************************************* -* init_ipsbar - Internal Peripheral System Base Address (IPSBAR) * -**********************************************************************/ -static void -init_ipsbar( void ) -{ - extern int __SRAM; - - /* Base address of internal peripherals (IPSBAR) = 0x40000000 - - Note: Processor powers up with IPS base address = 0x40000000 - Write to IPS base + 0x00000000 to set new value - */ - *( vuint32 * ) 0x40000000 = ( vuint32 ) __IPSBAR + 1; - - /* Configure RAMBAR in SCM module and allow dual-ported access. */ - MCF_SCM_RAMBAR = ( uint32 ) &__SRAM | MCF_SCM_RAMBAR_BDE; -} - -/********************************************************************* -* init_chip_selects - Chip Select Module * -**********************************************************************/ -static void -init_chip_selects( void ) -{ - extern void __FLASH; - uint32 FLASH_ADDR = (uint32)&__FLASH; - - /* Chip Select 0 - External Flash */ - MCF_CS_CSAR0 = MCF_CS_CSAR_BA( FLASH_ADDR ); - MCF_CS_CSCR0 = ( 0 - | MCF_CS_CSCR_IWS( 6 ) - | MCF_CS_CSCR_AA | MCF_CS_CSCR_PS_16 ); - MCF_CS_CSMR0 = MCF_CS_CSMR_BAM_2M | MCF_CS_CSMR_V; - - /* Chip Select 1 disabled (CSMR1[V] = 0) */ - MCF_CS_CSAR1 = 0; - MCF_CS_CSMR1 = 0; - MCF_CS_CSCR1 = 0; - - /* Chip Select 2 disabled (CSMR2[V] = 0) */ - MCF_CS_CSAR2 = 0; - MCF_CS_CSMR2 = 0; - MCF_CS_CSCR2 = 0; - - /* Chip Select 3 disabled (CSMR3[V] = 0) */ - MCF_CS_CSAR3 = 0; - MCF_CS_CSMR3 = 0; - MCF_CS_CSCR3 = 0; - - /* Chip Select 4 disabled (CSMR4[V] = 0) */ - MCF_CS_CSAR4 = 0; - MCF_CS_CSMR4 = 0; - MCF_CS_CSCR4 = 0; - - /* Chip Select 5 disabled (CSMR5[V] = 0) */ - MCF_CS_CSAR5 = 0; - MCF_CS_CSMR5 = 0; - MCF_CS_CSCR5 = 0; - - /* Chip Select 6 disabled (CSMR6[V] = 0) */ - MCF_CS_CSAR6 = 0; - MCF_CS_CSMR6 = 0; - MCF_CS_CSCR6 = 0; - - /* Chip Select 7 disabled (CSMR7[V] = 0) */ - MCF_CS_CSAR7 = 0; - MCF_CS_CSMR7 = 0; - MCF_CS_CSCR7 = 0; -} - -/********************************************************************* -* init_bus_config - Internal Bus Arbitration * -**********************************************************************/ -static void -init_bus_config( void ) -{ - - /* Use round robin arbitration scheme - Assigned priorities (highest first): - Ethernet - DMA Controller - ColdFire Core - DMA bandwidth control disabled - Park on last active bus master - */ - MCF_SCM_MPARK = - MCF_SCM_MPARK_M3_PRTY( 0x3 ) | MCF_SCM_MPARK_M2_PRTY( 0x2 ) | - MCF_SCM_MPARK_M1_PRTY( 0x1 ); -} - -/********************************************************************* -* init_cache - Instruction/Data Cache * -**********************************************************************/ -static void -init_cache( void ) -{ - /* Configured as split cache: 4 KByte instruction cache and 4 Kbyte data cache - ACR0: Don't cache accesses to 16 MB memory region at address $20000000 - ACR1: Don't cache accesses to 1 GB memory region at address $40000000 - CACR: Cache accesses to the rest of memory - */ - asm("move.l #0x80000000,%d0"); - asm("movec %d0,%CACR"); - asm("move.l #0x2000c040,%d0"); - asm("movec %d0,%ACR0"); - asm("move.l #0x403fc040,%d0"); - asm("movec %d0,%ACR1"); - - /* Instruction/Data cache disabled. */ - //asm( "move.l #0x00000000, %d0" ); - //asm( "movec %d0,%cacr" ); -} - -/********************************************************************* -* init_eport - Edge Port Module (EPORT) * -**********************************************************************/ -static void -init_eport( void ) -{ - - /* Pins 1-7 configured as GPIO inputs */ - MCF_EPORT_EPPAR = 0; - MCF_EPORT_EPDDR = 0; - MCF_EPORT_EPIER = 0; -} - -/********************************************************************* -* init_flexcan - FlexCAN Module * -**********************************************************************/ -static void -init_flexcan( void ) -{ - - /* FlexCAN controller 0 disabled (CANMCR0[MDIS]=1) */ - MCF_CAN_IMASK0 = 0; - MCF_CAN_RXGMASK0 = MCF_CAN_RXGMASK_MI( 0x1fffffff ); - MCF_CAN_RX14MASK0 = MCF_CAN_RX14MASK_MI( 0x1fffffff ); - MCF_CAN_RX15MASK0 = MCF_CAN_RX15MASK_MI( 0x1fffffff ); - MCF_CAN_CANCTRL0 = 0; - MCF_CAN_CANMCR0 = - MCF_CAN_CANMCR_MDIS | MCF_CAN_CANMCR_FRZ | MCF_CAN_CANMCR_HALT | - MCF_CAN_CANMCR_SUPV | MCF_CAN_CANMCR_MAXMB( 0xf ); - - /* FlexCAN controller 1 disabled (CANMCR1[MDIS]=1) */ - MCF_CAN_IMASK1 = 0; - MCF_CAN_RXGMASK1 = MCF_CAN_RXGMASK_MI( 0x1fffffff ); - MCF_CAN_RX14MASK1 = MCF_CAN_RX14MASK_MI( 0x1fffffff ); - MCF_CAN_RX15MASK1 = MCF_CAN_RX15MASK_MI( 0x1fffffff ); - MCF_CAN_CANCTRL1 = 0; - MCF_CAN_CANMCR1 = - MCF_CAN_CANMCR_MDIS | MCF_CAN_CANMCR_FRZ | MCF_CAN_CANMCR_HALT | - MCF_CAN_CANMCR_SUPV | MCF_CAN_CANMCR_MAXMB( 0xf ); -} - -/********************************************************************* -* init_power_management - Power Management * -**********************************************************************/ -static void -init_power_management( void ) -{ - - /* On executing STOP instruction, processor enters RUN mode - Mode is exited when an interrupt of level 1 or higher is received - */ - MCF_SCM_LPICR = MCF_SCM_LPICR_ENBSTOP; - MCF_CCM_LPCR = 0; -} - -/********************************************************************* -* init_sdram_controller - SDRAM Controller * -**********************************************************************/ -static void -init_sdram_controller( void ) -{ - extern void __SDRAM; - uint32 SDRAM_ADDR = (uint32)&__SDRAM; - int i; - - - /* - * Check to see if the SDRAM has already been initialized - * by a run control tool - */ - if( !( MCF_SDRAMC_DACR0 & MCF_SDRAMC_DACR0_RE ) ) - { - /* Initialize DRAM Control Register: DCR */ - MCF_SDRAMC_DCR = ( MCF_SDRAMC_DCR_RTIM( 1 ) | - MCF_SDRAMC_DCR_RC( ( 15 * FSYS_2 ) >> 4 ) ); - - /* Initialize DACR0 */ - MCF_SDRAMC_DACR0 = ( MCF_SDRAMC_DACR0_BA( SDRAM_ADDR >> 18UL ) | - MCF_SDRAMC_DACR0_CASL( 1 ) | - MCF_SDRAMC_DACR0_CBM( 3 ) | - MCF_SDRAMC_DACR0_PS( 0 ) ); - - /* Initialize DMR0 */ - MCF_SDRAMC_DMR0 = ( MCF_SDRAMC_DMR_BAM_16M | MCF_SDRAMC_DMR0_V ); - - /* Set IP (bit 3) in DACR */ - MCF_SDRAMC_DACR0 |= MCF_SDRAMC_DACR0_IP; - - /* Wait 30ns to allow banks to precharge */ - for( i = 0; i < 5; i++ ) - { - asm volatile ( " nop" ); - } - /* Write to this block to initiate precharge */ - *( uint32 * ) ( SDRAM_ADDR ) = 0xA5A59696; - - /* Set RE (bit 15) in DACR */ - MCF_SDRAMC_DACR0 |= MCF_SDRAMC_DACR0_RE; - - /* Wait for at least 8 auto refresh cycles to occur */ - for( i = 0; i < 2000; i++ ) - { - asm volatile ( "nop" ); - } - /* Finish the configuration by issuing the IMRS. */ - MCF_SDRAMC_DACR0 |= MCF_SDRAMC_DACR0_MRS; - - /* Write to the SDRAM Mode Register */ - *( uint32 * ) ( SDRAM_ADDR + 0x400 ) = 0xA5A59696; - } -} - -/********************************************************************* -* init_dma_timers - DMA Timer Modules * -**********************************************************************/ -static void -init_dma_timers( void ) -{ - - /* DMA Timer 0 disabled (DTMR0[RST] = 0) */ - MCF_TIMER_DTMR0 = 0; - MCF_TIMER_DTXMR0 = 0; - MCF_TIMER_DTRR0 = 0xffffffff; - - /* DMA Timer 1 disabled (DTMR1[RST] = 0) */ - MCF_TIMER_DTMR1 = 0; - MCF_TIMER_DTXMR1 = 0; - MCF_TIMER_DTRR1 = 0xffffffff; - - /* DMA Timer 2 disabled (DTMR2[RST] = 0) */ - MCF_TIMER_DTMR2 = 0; - MCF_TIMER_DTXMR2 = 0; - MCF_TIMER_DTRR2 = 0xffffffff; - - /* DMA Timer 3 disabled (DTMR3[RST] = 0) */ - MCF_TIMER_DTMR3 = 0; - MCF_TIMER_DTXMR3 = 0; - MCF_TIMER_DTRR3 = 0xffffffff; -} - -/********************************************************************** -* init_interrupt_timers - Programmable Interrupt Timer (PIT) Modules * -***********************************************************************/ -static void -init_interrupt_timers( void ) -{ - - /* PIT0 disabled (PCSR0[EN]=0) */ - MCF_PIT_PCSR0 = 0; - - /* PIT1 disabled (PCSR1[EN]=0) */ - MCF_PIT_PCSR1 = 0; - - /* PIT2 disabled (PCSR2[EN]=0) */ - MCF_PIT_PCSR2 = 0; - - /* PIT3 disabled (PCSR3[EN]=0) */ - MCF_PIT_PCSR3 = 0; -} - -/********************************************************************* -* init_watchdog_timers - Watchdog Timer Modules * -**********************************************************************/ -static void -init_watchdog_timers( void ) -{ - - /* Watchdog Timer disabled (WCR[EN]=0) - NOTE: WCR and WMR cannot be written again until after the - processor is reset. - */ - MCF_WTM_WCR = MCF_WTM_WCR_WAIT | MCF_WTM_WCR_DOZE | MCF_WTM_WCR_HALTED; - MCF_WTM_WMR = 0xffff; - - /* Core Watchdog Timer disabled (CWCR[CWE]=0) */ - MCF_SCM_CWCR = 0; -} - -/********************************************************************* -* init_interrupt_controller - Interrupt Controller * -**********************************************************************/ -static void -init_interrupt_controller( void ) -{ - - /* Configured interrupt sources in order of priority... - Level 7: External interrupt /IRQ7, (initially masked) - Level 6: External interrupt /IRQ6, (initially masked) - Level 5: External interrupt /IRQ5, (initially masked) - Level 4: External interrupt /IRQ4, (initially masked) - Level 3: External interrupt /IRQ3, (initially masked) - Level 2: External interrupt /IRQ2, (initially masked) - Level 1: External interrupt /IRQ1, (initially masked) - */ - MCF_INTC0_ICR1 = 0; - MCF_INTC0_ICR2 = 0; - MCF_INTC0_ICR3 = 0; - MCF_INTC0_ICR4 = 0; - MCF_INTC0_ICR5 = 0; - MCF_INTC0_ICR6 = 0; - MCF_INTC0_ICR7 = 0; - MCF_INTC0_ICR8 = 0; - MCF_INTC0_ICR9 = 0; - MCF_INTC0_ICR10 = 0; - MCF_INTC0_ICR11 = 0; - MCF_INTC0_ICR12 = 0; - MCF_INTC0_ICR13 = 0; - MCF_INTC0_ICR14 = 0; - MCF_INTC0_ICR15 = 0; - MCF_INTC0_ICR17 = 0; - MCF_INTC0_ICR18 = 0; - MCF_INTC0_ICR19 = 0; - MCF_INTC0_ICR20 = 0; - MCF_INTC0_ICR21 = 0; - MCF_INTC0_ICR22 = 0; - MCF_INTC0_ICR23 = 0; - MCF_INTC0_ICR24 = 0; - MCF_INTC0_ICR25 = 0; - MCF_INTC0_ICR26 = 0; - MCF_INTC0_ICR27 = 0; - MCF_INTC0_ICR28 = 0; - MCF_INTC0_ICR29 = 0; - MCF_INTC0_ICR30 = 0; - MCF_INTC0_ICR31 = 0; - MCF_INTC0_ICR32 = 0; - MCF_INTC0_ICR33 = 0; - MCF_INTC0_ICR34 = 0; - MCF_INTC0_ICR35 = 0; - MCF_INTC0_ICR36 = 0; - MCF_INTC0_ICR37 = 0; - MCF_INTC0_ICR38 = 0; - MCF_INTC0_ICR39 = 0; - MCF_INTC0_ICR40 = 0; - MCF_INTC0_ICR41 = 0; - MCF_INTC0_ICR42 = 0; - MCF_INTC0_ICR43 = 0; - MCF_INTC0_ICR44 = 0; - MCF_INTC0_ICR45 = 0; - MCF_INTC0_ICR46 = 0; - MCF_INTC0_ICR47 = 0; - MCF_INTC0_ICR48 = 0; - MCF_INTC0_ICR49 = 0; - MCF_INTC0_ICR50 = 0; - MCF_INTC0_ICR51 = 0; - MCF_INTC0_ICR52 = 0; - MCF_INTC0_ICR53 = 0; - MCF_INTC0_ICR54 = 0; - MCF_INTC0_ICR55 = 0; - MCF_INTC0_ICR56 = 0; - MCF_INTC0_ICR57 = 0; - MCF_INTC0_ICR58 = 0; - MCF_INTC0_ICR59 = 0; - MCF_INTC0_ICR60 = 0; - MCF_INTC1_ICR8 = 0; - MCF_INTC1_ICR9 = 0; - MCF_INTC1_ICR10 = 0; - MCF_INTC1_ICR11 = 0; - MCF_INTC1_ICR12 = 0; - MCF_INTC1_ICR13 = 0; - MCF_INTC1_ICR14 = 0; - MCF_INTC1_ICR15 = 0; - MCF_INTC1_ICR16 = 0; - MCF_INTC1_ICR17 = 0; - MCF_INTC1_ICR18 = 0; - MCF_INTC1_ICR19 = 0; - MCF_INTC1_ICR20 = 0; - MCF_INTC1_ICR21 = 0; - MCF_INTC1_ICR22 = 0; - MCF_INTC1_ICR23 = 0; - MCF_INTC1_ICR24 = 0; - MCF_INTC1_ICR25 = 0; - MCF_INTC1_ICR27 = 0; - MCF_INTC1_ICR28 = 0; - MCF_INTC1_ICR29 = 0; - MCF_INTC1_ICR30 = 0; - MCF_INTC1_ICR31 = 0; - MCF_INTC1_ICR32 = 0; - MCF_INTC1_ICR33 = 0; - MCF_INTC1_ICR34 = 0; - MCF_INTC1_ICR35 = 0; - MCF_INTC1_ICR36 = 0; - MCF_INTC1_ICR37 = 0; - MCF_INTC1_ICR38 = 0; - MCF_INTC1_ICR39 = 0; - MCF_INTC1_ICR40 = 0; - MCF_INTC1_ICR41 = 0; - MCF_INTC1_ICR42 = 0; - MCF_INTC1_ICR59 = 0; - MCF_INTC0_IMRH = 0xffffffff; - MCF_INTC0_IMRL = - MCF_INTC0_IMRL_INT_MASK31 | MCF_INTC0_IMRL_INT_MASK30 | - MCF_INTC0_IMRL_INT_MASK29 | MCF_INTC0_IMRL_INT_MASK28 | - MCF_INTC0_IMRL_INT_MASK27 | MCF_INTC0_IMRL_INT_MASK26 | - MCF_INTC0_IMRL_INT_MASK25 | MCF_INTC0_IMRL_INT_MASK24 | - MCF_INTC0_IMRL_INT_MASK23 | MCF_INTC0_IMRL_INT_MASK22 | - MCF_INTC0_IMRL_INT_MASK21 | MCF_INTC0_IMRL_INT_MASK20 | - MCF_INTC0_IMRL_INT_MASK19 | MCF_INTC0_IMRL_INT_MASK18 | - MCF_INTC0_IMRL_INT_MASK17 | MCF_INTC0_IMRL_INT_MASK16 | - MCF_INTC0_IMRL_INT_MASK15 | MCF_INTC0_IMRL_INT_MASK14 | - MCF_INTC0_IMRL_INT_MASK13 | MCF_INTC0_IMRL_INT_MASK12 | - MCF_INTC0_IMRL_INT_MASK11 | MCF_INTC0_IMRL_INT_MASK10 | - MCF_INTC0_IMRL_INT_MASK9 | MCF_INTC0_IMRL_INT_MASK8 | - MCF_INTC0_IMRL_INT_MASK7 | MCF_INTC0_IMRL_INT_MASK6 | - MCF_INTC0_IMRL_INT_MASK5 | MCF_INTC0_IMRL_INT_MASK4 | - MCF_INTC0_IMRL_INT_MASK3 | MCF_INTC0_IMRL_INT_MASK2 | - MCF_INTC0_IMRL_INT_MASK1; - MCF_INTC1_IMRH = 0xffffffff; - MCF_INTC1_IMRL = - MCF_INTC1_IMRL_INT_MASK31 | MCF_INTC1_IMRL_INT_MASK30 | - MCF_INTC1_IMRL_INT_MASK29 | MCF_INTC1_IMRL_INT_MASK28 | - MCF_INTC1_IMRL_INT_MASK27 | MCF_INTC1_IMRL_INT_MASK26 | - MCF_INTC1_IMRL_INT_MASK25 | MCF_INTC1_IMRL_INT_MASK24 | - MCF_INTC1_IMRL_INT_MASK23 | MCF_INTC1_IMRL_INT_MASK22 | - MCF_INTC1_IMRL_INT_MASK21 | MCF_INTC1_IMRL_INT_MASK20 | - MCF_INTC1_IMRL_INT_MASK19 | MCF_INTC1_IMRL_INT_MASK18 | - MCF_INTC1_IMRL_INT_MASK17 | MCF_INTC1_IMRL_INT_MASK16 | - MCF_INTC1_IMRL_INT_MASK15 | MCF_INTC1_IMRL_INT_MASK14 | - MCF_INTC1_IMRL_INT_MASK13 | MCF_INTC1_IMRL_INT_MASK12 | - MCF_INTC1_IMRL_INT_MASK11 | MCF_INTC1_IMRL_INT_MASK10 | - MCF_INTC1_IMRL_INT_MASK9 | MCF_INTC1_IMRL_INT_MASK8 | - MCF_INTC1_IMRL_INT_MASK7 | MCF_INTC1_IMRL_INT_MASK6 | - MCF_INTC1_IMRL_INT_MASK5 | MCF_INTC1_IMRL_INT_MASK4 | - MCF_INTC1_IMRL_INT_MASK3 | MCF_INTC1_IMRL_INT_MASK2 | - MCF_INTC1_IMRL_INT_MASK1; -} - -/********************************************************************* -* init_pin_assignments - Pin Assignment and General Purpose I/O * -**********************************************************************/ -static void -init_pin_assignments( void ) -{ - - /* Pin assignments for port ADDR - Pins are all GPIO inputs - */ - MCF_GPIO_PDDR_APDDR = 0; - MCF_GPIO_PAR_AD = MCF_GPIO_PAR_AD_PAR_ADDR23 - | MCF_GPIO_PAR_AD_PAR_ADDR22 - | MCF_GPIO_PAR_AD_PAR_ADDR21 | MCF_GPIO_PAR_AD_PAR_DATAL; - - /* Pin assignments for ports DATAH and DATAL - Pins are all GPIO inputs - */ - MCF_GPIO_PDDR_DATAH = 0; - MCF_GPIO_PDDR_DATAL = 0; - - /* Pin assignments for port BUSCTL - Pin /OE : External bus output enable, /OE - Pin /TA : External bus transfer acknowledge, /TA - Pin /TEA : External bus transfer error acknowledge, /TEA - Pin R/W : External bus read/write indication, R/W - Pin TSIZ1 : External bus transfer size TSIZ1 or DMA acknowledge /DACK1 - Pin TSIZ0 : External bus transfer size TSIZ0 or DMA acknowledge /DACK0 - Pin /TS : External bus transfer start, /TS - Pin /TIP : External bus transfer in progess, /TIP - */ - MCF_GPIO_PDDR_BUSCTL = 0; - MCF_GPIO_PAR_BUSCTL = - MCF_GPIO_PAR_BUSCTL_PAR_OE | MCF_GPIO_PAR_BUSCTL_PAR_TA | - MCF_GPIO_PAR_BUSCTL_PAR_TEA( 0x3 ) | MCF_GPIO_PAR_BUSCTL_PAR_RWB | - MCF_GPIO_PAR_BUSCTL_PAR_TSIZ1 | MCF_GPIO_PAR_BUSCTL_PAR_TSIZ0 | - MCF_GPIO_PAR_BUSCTL_PAR_TS( 0x3 ) | - MCF_GPIO_PAR_BUSCTL_PAR_TIP( 0x3 ); - - /* Pin assignments for port BS - Pin /BS3 : External byte strobe /BS3 - Pin /BS2 : External byte strobe /BS2 - Pin /BS1 : External byte strobe /BS1 - Pin /BS0 : External byte strobe /BS0 - */ - MCF_GPIO_PDDR_BS = 0; - MCF_GPIO_PAR_BS = - MCF_GPIO_PAR_BS_PAR_BS3 | MCF_GPIO_PAR_BS_PAR_BS2 | - MCF_GPIO_PAR_BS_PAR_BS1 | MCF_GPIO_PAR_BS_PAR_BS0; - - /* Pin assignments for port CS - Pin /CS7 : Chip select /CS7 - Pin /CS6 : Chip select /CS6 - Pin /CS5 : Chip select /CS5 - Pin /CS4 : Chip select /CS4 - Pin /CS3 : Chip select /CS3 - Pin /CS2 : Chip select /CS2 - Pin /CS1 : Chip select /CS1 - */ - MCF_GPIO_PDDR_CS = 0; - MCF_GPIO_PAR_CS = - MCF_GPIO_PAR_CS_PAR_CS7 | MCF_GPIO_PAR_CS_PAR_CS6 | - MCF_GPIO_PAR_CS_PAR_CS5 | MCF_GPIO_PAR_CS_PAR_CS4 | - MCF_GPIO_PAR_CS_PAR_CS3 | MCF_GPIO_PAR_CS_PAR_CS2 | - MCF_GPIO_PAR_CS_PAR_CS1; - - /* Pin assignments for port SDRAM - Pin /SD_WE : SDRAM controller /SD_WE - Pin /SD_SCAS : SDRAM controller /SD_SCAS - Pin /SD_SRAS : SDRAM controller /SD_SRAS - Pin /SD_SCKE : SDRAM controller /SD_SCKE - Pin /SD_CS1 : SDRAM controller /SD_CS1 - Pin /SD_CS0 : SDRAM controller /SD_CS0 - */ - MCF_GPIO_PDDR_SDRAM = 0; - MCF_GPIO_PAR_SDRAM = - MCF_GPIO_PAR_SDRAM_PAR_SDWE | MCF_GPIO_PAR_SDRAM_PAR_SCAS | - MCF_GPIO_PAR_SDRAM_PAR_SRAS | MCF_GPIO_PAR_SDRAM_PAR_SCKE | - MCF_GPIO_PAR_SDRAM_PAR_SDCS1 | MCF_GPIO_PAR_SDRAM_PAR_SDCS0; - - /* Pin assignments for port FECI2C - Pins are all GPIO inputs - */ - MCF_GPIO_PDDR_FECI2C = 0; - MCF_GPIO_PAR_FECI2C = - MCF_GPIO_PAR_FECI2C_PAR_EMDC_FEC | MCF_GPIO_PAR_FECI2C_PAR_EMDIO_FEC; - - /* Pin assignments for port UARTL - Pins are all GPIO inputs - */ - MCF_GPIO_PDDR_UARTL = 0; - MCF_GPIO_PAR_UART = 0; - - /* Pin assignments for port UARTH - Pin U2TXD : GPIO input - Pin U2RXD : GPIO input - Pin /IRQ2 : Interrupt request /IRQ2 or GPIO - */ - MCF_GPIO_PDDR_UARTH = 0; - - /* Pin assignments for port QSPI - Pins are all GPIO inputs - */ - MCF_GPIO_PDDR_QSPI = 0; - MCF_GPIO_PAR_QSPI = 0; - - /* Pin assignments for port TIMER - Pins are all GPIO inputs - */ - MCF_GPIO_PDDR_TIMER = 0; - MCF_GPIO_PAR_TIMER = 0; - - /* Pin assignments for port ETPU - Pins are all GPIO inputs - */ - MCF_GPIO_PDDR_ETPU = 0; - MCF_GPIO_PAR_ETPU = 0; -} diff --git a/Demo/MCF5235_GCC/system/mcf5xxx.S b/Demo/MCF5235_GCC/system/mcf5xxx.S deleted file mode 100644 index b68c689c4..000000000 --- a/Demo/MCF5235_GCC/system/mcf5xxx.S +++ /dev/null @@ -1,249 +0,0 @@ -/* - * Lowest level routines for all ColdFire processors. Based on the - * MCF523x examples from Freescale. - * - * Freescale explicitly grants the redistribution and modification - * of these source files. The complete licensing information is - * available in the file LICENSE_FREESCALE.TXT. - * - * Modifications Copyright (c) 2006 Christian Walter - * - * File: $Id: mcf5xxx.S,v 1.2 2006/09/24 22:50:22 wolti Exp $ - */ - - .global asm_set_ipl - .global _asm_set_ipl - .global mcf5xxx_wr_cacr - .global _mcf5xxx_wr_cacr - .global mcf5xxx_wr_acr0 - .global _mcf5xxx_wr_acr0 - .global mcf5xxx_wr_acr1 - .global _mcf5xxx_wr_acr1 - .global mcf5xxx_wr_acr2 - .global _mcf5xxx_wr_acr2 - .global mcf5xxx_wr_acr3 - .global _mcf5xxx_wr_acr3 - .global mcf5xxx_wr_other_sp - .global _mcf5xxx_wr_other_sp - .global mcf5xxx_wr_other_a7 - .global _mcf5xxx_wr_other_a7 - .global mcf5xxx_wr_vbr - .global _mcf5xxx_wr_vbr - .global mcf5xxx_wr_macsr - .global _mcf5xxx_wr_macsr - .global mcf5xxx_wr_mask - .global _mcf5xxx_wr_mask - .global mcf5xxx_wr_acc0 - .global _mcf5xxx_wr_acc0 - .global mcf5xxx_wr_accext01 - .global _mcf5xxx_wr_accext01 - .global mcf5xxx_wr_accext23 - .global _mcf5xxx_wr_accext23 - .global mcf5xxx_wr_acc1 - .global _mcf5xxx_wr_acc1 - .global mcf5xxx_wr_acc2 - .global _mcf5xxx_wr_acc2 - .global mcf5xxx_wr_acc3 - .global _mcf5xxx_wr_acc3 - .global mcf5xxx_wr_sr - .global _mcf5xxx_wr_sr - .global mcf5xxx_wr_rambar0 - .global _mcf5xxx_wr_rambar0 - .global mcf5xxx_wr_rambar1 - .global _mcf5xxx_wr_rambar1 - .global mcf5xxx_wr_mbar - .global _mcf5xxx_wr_mbar - .global mcf5xxx_wr_mbar0 - .global _mcf5xxx_wr_mbar0 - .global mcf5xxx_wr_mbar1 - .global _mcf5xxx_wr_mbar1 - - .text - -/********************************************************************/ -/* - * This routines changes the IPL to the value passed into the routine. - * It also returns the old IPL value back. - * Calling convention from C: - * old_ipl = asm_set_ipl(new_ipl); - * For the Diab Data C compiler, it passes return value thru D0. - * Note that only the least significant three bits of the passed - * value are used. - */ - -asm_set_ipl: -_asm_set_ipl: - link a6,#-8 - movem.l d6-d7,(sp) - - move.w sr,d7 /* current sr */ - - move.l d7,d0 /* prepare return value */ - andi.l #0x0700,d0 /* mask out IPL */ - lsr.l #8,d0 /* IPL */ - - move.l 8(a6),d6 /* get argument */ - andi.l #0x07,d6 /* least significant three bits */ - lsl.l #8,d6 /* move over to make mask */ - - andi.l #0x0000F8FF,d7 /* zero out current IPL */ - or.l d6,d7 /* place new IPL in sr */ - move.w d7,sr - - movem.l (sp),d6-d7 - lea 8(sp),sp - unlk a6 - rts - -/********************************************************************/ -/* - * These routines write to the special purpose registers in the ColdFire - * core. Since these registers are write-only in the supervisor model, - * no corresponding read routines exist. - */ - -mcf5xxx_wr_cacr: -_mcf5xxx_wr_cacr: - move.l 4(sp),d0 - .long 0x4e7b0002 /* movec d0,cacr */ - nop - rts - -mcf5xxx_wr_acr0: -_mcf5xxx_wr_acr0: - move.l 4(sp),d0 - .long 0x4e7b0004 /* movec d0,ACR0 */ - nop - rts - -mcf5xxx_wr_acr1: -_mcf5xxx_wr_acr1: - move.l 4(sp),d0 - .long 0x4e7b0005 /* movec d0,ACR1 */ - nop - rts - -mcf5xxx_wr_acr2: -_mcf5xxx_wr_acr2: - move.l 4(sp),d0 - .long 0x4e7b0006 /* movec d0,ACR2 */ - nop - rts - -mcf5xxx_wr_acr3: -_mcf5xxx_wr_acr3: - move.l 4(sp),d0 - .long 0x4e7b0007 /* movec d0,ACR3 */ - nop - rts - -mcf5xxx_wr_other_sp: -_mcf5xxx_wr_other_sp: -mcf5xxx_wr_other_a7: -_mcf5xxx_wr_other_a7: - move.l 4(sp),d0 - .long 0x4e7b0800 /* movec d0,OTHER_A7 */ - nop - rts - -mcf5xxx_wr_vbr: -_mcf5xxx_wr_vbr: - move.l 4(sp),d0 - .long 0x4e7b0801 /* movec d0,VBR */ - nop - rts - -mcf5xxx_wr_macsr: -_mcf5xxx_wr_macsr: - move.l 4(sp),d0 - .long 0x4e7b0804 /* movec d0,MACSR */ - nop - rts - -mcf5xxx_wr_mask: -_mcf5xxx_wr_mask: - move.l 4(sp),d0 - .long 0x4e7b0805 /* movec d0,MASK */ - nop - rts - -mcf5xxx_wr_acc0: -_mcf5xxx_wr_acc0: - move.l 4(sp),d0 - .long 0x4e7b0806 /* movec d0,ACC0 */ - nop - rts - -mcf5xxx_wr_accext01: -_mcf5xxx_wr_accext01: - move.l 4(sp),d0 - .long 0x4e7b0807 /* movec d0,ACCEXT01 */ - nop - rts - -mcf5xxx_wr_accext23: -_mcf5xxx_wr_accext23: - move.l 4(sp),d0 - .long 0x4e7b0808 /* movec d0,ACCEXT23 */ - nop - rts - -mcf5xxx_wr_acc1: -_mcf5xxx_wr_acc1: - move.l 4(sp),d0 - .long 0x4e7b0809 /* movec d0,ACC1 */ - nop - rts - -mcf5xxx_wr_acc2: -_mcf5xxx_wr_acc2: - move.l 4(sp),d0 - .long 0x4e7b080A /* movec d0,ACC2 */ - nop - rts - -mcf5xxx_wr_acc3: -_mcf5xxx_wr_acc3: - move.l 4(sp),d0 - .long 0x4e7b080B /* movec d0,ACC3 */ - nop - rts - -mcf5xxx_wr_sr: -_mcf5xxx_wr_sr: - move.l 4(sp),d0 - move.w d0,SR - rts - -mcf5xxx_wr_rambar0: -_mcf5xxx_wr_rambar0: - move.l 4(sp),d0 - .long 0x4e7b0C04 /* movec d0,RAMBAR0 */ - nop - rts - -mcf5xxx_wr_rambar1: -_mcf5xxx_wr_rambar1: - move.l 4(sp),d0 - .long 0x4e7b0C05 /* movec d0,RAMBAR1 */ - nop - rts - -mcf5xxx_wr_mbar: -_mcf5xxx_wr_mbar: -mcf5xxx_wr_mbar0: -_mcf5xxx_wr_mbar0: - move.l 4(sp),d0 - .long 0x4e7b0C0F /* movec d0,MBAR0 */ - nop - rts - -mcf5xxx_wr_mbar1: -_mcf5xxx_wr_mbar1: - move.l 4(sp),d0 - .long 0x4e7b0C0E /* movec d0,MBAR1 */ - nop - rts - - .end -/********************************************************************/ diff --git a/Demo/MCF5235_GCC/system/newlib.c b/Demo/MCF5235_GCC/system/newlib.c deleted file mode 100644 index 82ffbb0aa..000000000 --- a/Demo/MCF5235_GCC/system/newlib.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* ------------------------ System includes ------------------------------- */ -#include -#include -#include -#include - -/* ------------------------ FreeRTOS includes ----------------------------- */ -#include -#include - -/* ------------------------ Prototypes ------------------------------------ */ -void vSerialPutStringNOISR( xComPortHandle pxPort, - const signed portCHAR * const pcString, - unsigned portSHORT usStringLength ); - -/* ------------------------ Start implementation -------------------------- */ -void -_exit( int status ) -{ - asm volatile ( "halt" ); - - for( ;; ); -} - -pid_t -getpid( void ) -{ - return 0; -} - -int -kill( pid_t pid, int sig ) -{ - _exit( 0 ); -} - -int -close( int fd ) -{ - return 0; -} - -int -fstat( int fd, struct stat *buf ) -{ - buf->st_mode = S_IFCHR; - buf->st_blksize = 0; - return 0; -} - -ssize_t -write( int fd, const void *buf, size_t nbytes ) -{ - ssize_t res = nbytes; - extern xComPortHandle xSTDComPort; - switch ( fd ) - { - case STDERR_FILENO: - vSerialPutStringNOISR( xSTDComPort, - ( const signed portCHAR * const )buf, - ( unsigned portSHORT )nbytes ); - break; - case STDOUT_FILENO: - vSerialPutString( xSTDComPort, - ( const signed portCHAR * const)buf, - ( unsigned portSHORT )nbytes ); - break; - default: - errno = EIO; - res = -1; - break; - } - return res; -} - -int -read( int fd, void *buf, size_t nbytes ) -{ - switch ( fd ) - { - default: - errno = EIO; - return -1; - } -} - -int -isatty( int fd ) -{ - return 0; -} - -off_t -lseek( int fd, off_t offset, int whence ) -{ - errno = EIO; - return ( off_t ) - 1; -} - -extern char _end[]; -char *heap_ptr; - -void * -sbrk( ptrdiff_t nbytes ) -{ - char *base; - - if( !heap_ptr ) - heap_ptr = ( char * )&_end; - base = heap_ptr; - heap_ptr += nbytes; - - return base; -} diff --git a/Demo/MCF5235_GCC/system/serial.c b/Demo/MCF5235_GCC/system/serial.c deleted file mode 100644 index f1fb6a368..000000000 --- a/Demo/MCF5235_GCC/system/serial.c +++ /dev/null @@ -1,298 +0,0 @@ -/* - FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* ------------------------ MCF523x includes ------------------------------ */ -#include "mcf5xxx.h" -#include "mcf523x.h" - -/* ------------------------ FreeRTOS includes ----------------------------- */ -#include "FreeRTOS.h" -#include "queue.h" -#include "task.h" - -#include "serial.h" - -/* ----------------------- Defines ----------------------------------------- */ -#define BAUDRATE_VALUE(fsys, baud) ( ( fsys )/(32UL * baud) ) -#define MCF_UART_VECTOR ( 64 + 13 ) -#define COM_NIFACE 1 -#define COM_BLOCK_RETRYTIME 10 - -/* ------------------------ Static functions ------------------------------ */ -static void prvSerialISR( void ); - -/* ------------------------ Static variables ------------------------------ */ -typedef struct -{ - portBASE_TYPE xInitialized; - xQueueHandle xRXChars; - xQueueHandle xTXChars; -} xComPortIF_t; - -static xComPortIF_t xComPortIF[ COM_NIFACE ]; - -/* ------------------------ Begin implementation -------------------------- */ -xComPortHandle -xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, - unsigned portBASE_TYPE uxQueueLength ) -{ - extern void ( *__RAMVEC[] ) ( ); - xComPortHandle xReturn; - portBASE_TYPE xOldIPL; - - /* Create the queues used to hold Rx and Tx characters. */ - xComPortIF[ 0 ].xRXChars = - xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE )sizeof( signed portCHAR ) ); - xComPortIF[ 0 ].xTXChars = - xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE )sizeof( signed portCHAR ) ); - - /* If the queues were created correctly then setup the serial port hardware. */ - if( ( xComPortIF[ 0 ].xRXChars != 0 ) && ( xComPortIF[ 0 ].xTXChars != 0 ) ) - { - xOldIPL = portSET_IPL( portIPL_MAX ); - - /* UART 0: Reset transmitter, receiver and mode register pointer */ - MCF_UART_UCR0 = MCF_UART_UCR_MISC( 0x3 ); - MCF_UART_UCR0 = MCF_UART_UCR_MISC( 0x2 ); - MCF_UART_UCR0 = MCF_UART_UCR_MISC( 0x1 ); - - /* Enable receive interrupts. */ - MCF_UART_UIMR0 = MCF_UART_UIMR_RXRDY_FU; - - /* 8 Databits, 1 Stopbit and no parity */ - MCF_UART_UMR0 = MCF_UART_UMR_PM( 0x3 ) | MCF_UART_UMR_SB( 0x7 ) | MCF_UART_UMR_BC( 0x3 ); - - /* UART 0 Clocking */ - MCF_UART_UCSR0 = MCF_UART_UCSR_RCS( 0xd ) | MCF_UART_UCSR_TCS( 0xd ); - MCF_UART_UBG10 = BAUDRATE_VALUE( FSYS_2, ulWantedBaud ) >> 8U; - MCF_UART_UBG20 = BAUDRATE_VALUE( FSYS_2, ulWantedBaud ) & 0xFFU; - - /* UART 0: Enable interrupts */ - __RAMVEC[MCF_UART_VECTOR] = prvSerialISR; - MCF_INTC0_ICR13 = MCF_INTC0_ICRn_IL( 0x2 ) | MCF_INTC0_ICRn_IP( 0x1 ); - MCF_INTC0_IMRL &= ~MCF_INTC0_IMRL_INT_MASK13; - - /* UART 0 Miscellaneous */ - MCF_UART_UACR0 = 0; - - /* UART 0: Enable pins */ - MCF_GPIO_PAR_UART = MCF_GPIO_PAR_UART_PAR_U0RXD | MCF_GPIO_PAR_UART_PAR_U0TXD; - - /* Enable the UART. */ - MCF_UART_UCR0 = MCF_UART_UCR_RXC( 0x1 ) | MCF_UART_UCR_TXC( 0x1 ); - - xComPortIF[ 0 ].xInitialized = TRUE; - xReturn = ( xComPortHandle ) &xComPortIF[ 0 ]; - - ( void )portSET_IPL( xOldIPL ); - } - else - { - xReturn = ( xComPortHandle ) 0; - } - - return xReturn; -} - -signed portBASE_TYPE -xSerialGetChar( xComPortHandle pxPort, signed portCHAR * pcRxedChar, - portTickType xBlockTime ) -{ - int i; - portBASE_TYPE xResult = pdFALSE; - /* Lookup the correct interface. */ - for( i = 0; i < COM_NIFACE; i++ ) - { - if( pxPort == ( xComPortHandle ) &xComPortIF[ i ] ) - { - break; - } - } - /* This COM port is available. */ - if( ( i != COM_NIFACE ) && xComPortIF[ i ].xInitialized ) - { - /* Get the next character from the buffer. Return false if no characters - * are available, or arrive before xBlockTime expires. - */ - if( xQueueReceive( xComPortIF[ i ].xRXChars, pcRxedChar, xBlockTime ) ) - { - xResult = pdTRUE; - } - } - return xResult; -} - -void -vSerialPutString( xComPortHandle pxPort, const signed portCHAR * - const pcString, unsigned portSHORT usStringLength ) -{ - int i; - signed portCHAR *pChNext; - - /* Send each character in the string, one at a time. */ - pChNext = ( signed portCHAR * )pcString; - for( i = 0; i < usStringLength; i++ ) - { - /* Block until character has been transmitted. */ - while( xSerialPutChar( pxPort, *pChNext, COM_BLOCK_RETRYTIME ) != pdTRUE ); pChNext++; - } -} - -signed portBASE_TYPE -xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, - portTickType xBlockTime ) -{ - int i; - portBASE_TYPE xResult = pdFALSE; - portBASE_TYPE xOldIPL; - /* Lookup the correct interface. */ - for( i = 0; i < COM_NIFACE; i++ ) - { - if( pxPort == ( xComPortHandle ) &xComPortIF[ i ] ) - { - break; - } - } - /* This COM port is available. */ - if( ( i != COM_NIFACE ) && xComPortIF[ i ].xInitialized ) - { - /* Place the character in the queue of characters to be transmitted. */ - if( xQueueSend( xComPortIF[ i ].xTXChars, &cOutChar, xBlockTime ) == pdPASS ) - { - /* Turn on the Tx interrupt so the ISR will remove the character from the - * queue and send it. */ - MCF_UART_UIMR0 = MCF_UART_UIMR_TXRDY | MCF_UART_UIMR_RXRDY_FU; - xResult = pdTRUE; - } - } - return xResult; -} - -signed portBASE_TYPE -xSerialPutCharNOISR( xComPortHandle pxPort, signed portCHAR cOutChar ) -{ - int i; - portBASE_TYPE xResult = pdFALSE; - portBASE_TYPE xOldIPL = portSET_IPL( portIPL_MAX ); - /* Lookup the correct interface. */ - for( i = 0; i < COM_NIFACE; i++ ) - { - if( pxPort == ( xComPortHandle ) &xComPortIF[ i ] ) - { - break; - } - } - /* This COM port is available. Support for this only available for COM1 right now. */ - if( ( i != COM_NIFACE ) && ( i == 0 ) ) - { - /* Wait until the transmit buffer is ready. */ - while( !( MCF_UART_USR0 & MCF_UART_USR_TXRDY ) ); - /* Place the character in the transmit buffer. */ - MCF_UART_UTB0 = cOutChar; - xResult = pdTRUE; - } - ( void )portSET_IPL( xOldIPL ); - return xResult; -} - -void -vSerialPutStringNOISR( xComPortHandle pxPort, const signed portCHAR * - const pcString, unsigned portSHORT usStringLength ) -{ - int i; - signed portCHAR *pChNext; - portBASE_TYPE xOldIPL = portSET_IPL( portIPL_MAX ); - - /* Send each character in the string, one at a time. */ - pChNext = ( signed portCHAR * )pcString; - for( i = 0; i < usStringLength; i++ ) - { - /* Block until character has been transmitted. */ - while( xSerialPutCharNOISR( pxPort, *pChNext ) != pdTRUE ); - pChNext++; - } - ( void )portSET_IPL( xOldIPL ); -} - -void -vSerialClose( xComPortHandle xPort ) -{ - /* Not supported as not required by the demo application. */ -} - -void -prvSerialISR( void ) -{ - static signed portCHAR cChar; - static portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByRx = pdFALSE; - - /* We have to remvoe the effect of the GCC. Please note that the - * __attribute__ ((interrupt_handler)) does not work here because we - * have to do the storing of the registers ourself. Another problem - * is the usage of a frame pointer which is unlinked on entry. - */ -#if _GCC_USES_FP == 1 - asm volatile ( "unlk %fp\n\t" ); -#endif - /* This ISR can cause a context switch, so the first statement must be - * a call to the portENTER_SWITCHING_ISR() macro. This must be BEFORE any - * variable declarations. - */ - portENTER_SWITCHING_ISR(); - - /* Ready to send a character from the buffer. */ - if( MCF_UART_USR0 & MCF_UART_USR_TXRDY ) - { - /* Transmit buffer is ready. Test if there are characters available. */ - if( xQueueReceiveFromISR( xComPortIF[ 0 ].xTXChars, &cChar, &xTaskWokenByTx ) == - pdTRUE ) - { - /* A character was retrieved from the queue so can be sent. */ - MCF_UART_UTB0 = cChar; - } - else - { - /* Leave only receiver enabled. */ - MCF_UART_UIMR0 = MCF_UART_UIMR_RXRDY_FU; - } - } - if( MCF_UART_USR0 & MCF_UART_USR_RXRDY ) - { - cChar = MCF_UART_URB0; - xTaskWokenByRx = - xQueueSendFromISR( xComPortIF[ 0].xRXChars, &cChar, xTaskWokenByRx ); - } - /* Exit the ISR. If a task was woken by either a character being - * or transmitted then a context switch will occur. - */ - portEXIT_SWITCHING_ISR( ( xTaskWokenByTx || xTaskWokenByRx ) ); -} diff --git a/Demo/MCF5235_GCC/system/vector.S b/Demo/MCF5235_GCC/system/vector.S deleted file mode 100644 index 4c278a64c..000000000 --- a/Demo/MCF5235_GCC/system/vector.S +++ /dev/null @@ -1,302 +0,0 @@ -/* - FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - .extern __stack - .extern start - .extern fec_handler - .extern fec_if - .extern decrement_timers - .global __RAMVEC - .global __ROMVEC - - .equ MCF_PIT_PCSR0, IPSBAR + 0x150000 - .equ MCF_PIT_PCSR_PIF, 0x0004 - - .section .vector_rom, "x" -__ROMVEC: - .long __stack /* Reset: Initial Stack Pointer */ - .long start /* Reset: Initial Program Counter */ - .long VecDefault /* Bus Error */ - .long VecDefault /* Address Error */ - .long VecDefault /* Illegal Instruction */ - .long VecDefault /* Zero Divison */ - .space 4 /* reserved */ - .space 4 /* reserved */ - .long VecDefault /* Privilege Violation */ - .long VecDefault /* Trace */ - .long VecDefault /* Unimplemented line-a opcode */ - .long VecDefault /* Unimplemented line-b opcode */ - .long VecDefault /* Non-PC breakpoint debug interrupt */ - .long VecDefault /* PC breakpoint debug interrupt */ - .long VecDefault /* Format Error */ - .long VecDefault /* Uninitialized Interrupt */ - .org 0x60 - .long IRQSpurious /* Spurious Interrupt */ - .long IRQDefault /* Level 1 Interrupt */ - .long IRQDefault /* Level 2 Interrupt */ - .long IRQDefault /* Level 3 Interrupt */ - .long IRQDefault /* Level 4 Interrupt */ - .long IRQDefault /* Level 5 Interrupt */ - .long IRQDefault /* Level 6 Interrupt */ - .long IRQDefault /* Level 7 Interrupt */ - .org 0x80 - .long TrapDefault /* TRAP 0 */ - .long TrapDefault /* TRAP 1 */ - .long TrapDefault /* TRAP 2 */ - .long TrapDefault /* TRAP 3 */ - .long TrapDefault /* TRAP 4 */ - .long TrapDefault /* TRAP 5 */ - .long TrapDefault /* TRAP 6 */ - .long TrapDefault /* TRAP 7 */ - .long TrapDefault /* TRAP 8 */ - .long TrapDefault /* TRAP 9 */ - .long TrapDefault /* TRAP 10 */ - .long TrapDefault /* TRAP 11 */ - .long TrapDefault /* TRAP 12 */ - .long TrapDefault /* TRAP 13 */ - .long TrapDefault /* TRAP 14 */ - .long TrapDefault /* TRAP 15 */ - .org 0x100 - .long IRQDefault /* User-Defined Interrupt 0 */ - .long IRQDefault /* User-Defined Interrupt 1 */ - .long IRQDefault /* User-Defined Interrupt 2 */ - .long IRQDefault /* User-Defined Interrupt 3 */ - .long IRQDefault /* User-Defined Interrupt 4 */ - .long IRQDefault /* User-Defined Interrupt 5 */ - .long IRQDefault /* User-Defined Interrupt 6 */ - .long IRQDefault /* User-Defined Interrupt 7 */ - .long IRQDefault /* User-Defined Interrupt 8 */ - .long IRQDefault /* User-Defined Interrupt 9 */ - .long IRQDefault /* User-Defined Interrupt 10 */ - .long IRQDefault /* User-Defined Interrupt 11 */ - .long IRQDefault /* User-Defined Interrupt 12 */ - .long IRQDefault /* User-Defined Interrupt 13 */ - .long IRQDefault /* User-Defined Interrupt 14 */ - .long IRQDefault /* User-Defined Interrupt 15 */ - .long IRQDefault /* User-Defined Interrupt 16 */ - .long IRQDefault /* User-Defined Interrupt 17 */ - .long IRQDefault /* User-Defined Interrupt 18 */ - .long IRQDefault /* User-Defined Interrupt 19 */ - .long IRQDefault /* User-Defined Interrupt 20 */ - .long IRQDefault /* User-Defined Interrupt 21 */ - .long IRQDefault /* User-Defined Interrupt 22 */ - .long IRQDefault /* Transmit frame interrupt */ - .long IRQDefault /* Transmit buffer interrupt */ - .long IRQDefault /* Transmit FIFO underrun */ - .long IRQDefault /* Collision retry limit */ - .long IRQDefault /* Receive frame interrupt */ - .long IRQDefault /* Receive buffer interrupt */ - .long IRQDefault /* MII interrupt */ - .long IRQDefault /* Late collision */ - .long IRQDefault /* Heartbeat error */ - .long IRQDefault /* Graceful stop complete */ - .long IRQDefault /* Ethernet bus error */ - .long IRQDefault /* Babbling transmit error */ - .long IRQDefault /* Babbling receive error */ - .long IRQDefault /* Timer interrupt */ - .long IRQDefault /* User-Defined Interrupt 37 */ - .long IRQDefault /* User-Defined Interrupt 38 */ - .long IRQDefault /* User-Defined Interrupt 39 */ - .long IRQDefault /* User-Defined Interrupt 40 */ - .long IRQDefault /* User-Defined Interrupt 41 */ - .long IRQDefault /* User-Defined Interrupt 42 */ - .long IRQDefault /* User-Defined Interrupt 43 */ - .long IRQDefault /* User-Defined Interrupt 44 */ - .long IRQDefault /* User-Defined Interrupt 45 */ - .long IRQDefault /* User-Defined Interrupt 46 */ - .long IRQDefault /* User-Defined Interrupt 47 */ - .long IRQDefault /* User-Defined Interrupt 48 */ - .long IRQDefault /* User-Defined Interrupt 49 */ - .long IRQDefault /* User-Defined Interrupt 50 */ - .long IRQDefault /* User-Defined Interrupt 51 */ - .long IRQDefault /* User-Defined Interrupt 52 */ - .long IRQDefault /* User-Defined Interrupt 53 */ - .long IRQDefault /* User-Defined Interrupt 54 */ - .long IRQDefault /* User-Defined Interrupt 55 */ - .long IRQDefault /* User-Defined Interrupt 56 */ - .long IRQDefault /* User-Defined Interrupt 57 */ - .long IRQDefault /* User-Defined Interrupt 58 */ - .long IRQDefault /* User-Defined Interrupt 59 */ - .long IRQDefault /* User-Defined Interrupt 60 */ - .long IRQDefault /* User-Defined Interrupt 61 */ - .long IRQDefault /* User-Defined Interrupt 62 */ - .long IRQDefault /* User-Defined Interrupt 63 */ - .long IRQDefault /* User-Defined Interrupt 64 */ - .long IRQDefault /* User-Defined Interrupt 65 */ - .long IRQDefault /* User-Defined Interrupt 66 */ - .long IRQDefault /* User-Defined Interrupt 67 */ - .long IRQDefault /* User-Defined Interrupt 68 */ - .long IRQDefault /* User-Defined Interrupt 69 */ - .long IRQDefault /* User-Defined Interrupt 70 */ - .long IRQDefault /* User-Defined Interrupt 71 */ - .long IRQDefault /* User-Defined Interrupt 72 */ - .long IRQDefault /* User-Defined Interrupt 73 */ - .long IRQDefault /* User-Defined Interrupt 74 */ - .long IRQDefault /* User-Defined Interrupt 75 */ - .long IRQDefault /* User-Defined Interrupt 76 */ - .long IRQDefault /* User-Defined Interrupt 77 */ - .long IRQDefault /* User-Defined Interrupt 78 */ - .long IRQDefault /* User-Defined Interrupt 79 */ - .long IRQDefault /* User-Defined Interrupt 80 */ - .long IRQDefault /* User-Defined Interrupt 81 */ - .long IRQDefault /* User-Defined Interrupt 82 */ - .long IRQDefault /* User-Defined Interrupt 83 */ - .long IRQDefault /* User-Defined Interrupt 84 */ - .long IRQDefault /* User-Defined Interrupt 85 */ - .long IRQDefault /* User-Defined Interrupt 86 */ - .long IRQDefault /* User-Defined Interrupt 87 */ - .long IRQDefault /* User-Defined Interrupt 88 */ - .long IRQDefault /* User-Defined Interrupt 89 */ - .long IRQDefault /* User-Defined Interrupt 90 */ - .long IRQDefault /* User-Defined Interrupt 91 */ - .long IRQDefault /* User-Defined Interrupt 92 */ - .long IRQDefault /* User-Defined Interrupt 93 */ - .long IRQDefault /* User-Defined Interrupt 94 */ - .long IRQDefault /* User-Defined Interrupt 95 */ - .long IRQDefault /* User-Defined Interrupt 96 */ - .long IRQDefault /* User-Defined Interrupt 97 */ - .long IRQDefault /* User-Defined Interrupt 98 */ - .long IRQDefault /* User-Defined Interrupt 99 */ - .long IRQDefault /* User-Defined Interrupt 100 */ - .long IRQDefault /* User-Defined Interrupt 101 */ - .long IRQDefault /* User-Defined Interrupt 102 */ - .long IRQDefault /* User-Defined Interrupt 103 */ - .long IRQDefault /* User-Defined Interrupt 104 */ - .long IRQDefault /* User-Defined Interrupt 105 */ - .long IRQDefault /* User-Defined Interrupt 106 */ - .long IRQDefault /* User-Defined Interrupt 107 */ - .long IRQDefault /* User-Defined Interrupt 108 */ - .long IRQDefault /* User-Defined Interrupt 109 */ - .long IRQDefault /* User-Defined Interrupt 110 */ - .long IRQDefault /* User-Defined Interrupt 111 */ - .long IRQDefault /* User-Defined Interrupt 112 */ - .long IRQDefault /* User-Defined Interrupt 113 */ - .long IRQDefault /* User-Defined Interrupt 114 */ - .long IRQDefault /* User-Defined Interrupt 115 */ - .long IRQDefault /* User-Defined Interrupt 116 */ - .long IRQDefault /* User-Defined Interrupt 117 */ - .long IRQDefault /* User-Defined Interrupt 118 */ - .long IRQDefault /* User-Defined Interrupt 119 */ - .long IRQDefault /* User-Defined Interrupt 120 */ - .long IRQDefault /* User-Defined Interrupt 121 */ - .long IRQDefault /* User-Defined Interrupt 122 */ - .long IRQDefault /* User-Defined Interrupt 123 */ - .long IRQDefault /* User-Defined Interrupt 124 */ - .long IRQDefault /* User-Defined Interrupt 125 */ - .long IRQDefault /* User-Defined Interrupt 126 */ - .long IRQDefault /* User-Defined Interrupt 127 */ - .long IRQDefault /* User-Defined Interrupt 128 */ - .long IRQDefault /* User-Defined Interrupt 129 */ - .long IRQDefault /* User-Defined Interrupt 130 */ - .long IRQDefault /* User-Defined Interrupt 131 */ - .long IRQDefault /* User-Defined Interrupt 132 */ - .long IRQDefault /* User-Defined Interrupt 133 */ - .long IRQDefault /* User-Defined Interrupt 134 */ - .long IRQDefault /* User-Defined Interrupt 135 */ - .long IRQDefault /* User-Defined Interrupt 136 */ - .long IRQDefault /* User-Defined Interrupt 137 */ - .long IRQDefault /* User-Defined Interrupt 138 */ - .long IRQDefault /* User-Defined Interrupt 139 */ - .long IRQDefault /* User-Defined Interrupt 140 */ - .long IRQDefault /* User-Defined Interrupt 141 */ - .long IRQDefault /* User-Defined Interrupt 142 */ - .long IRQDefault /* User-Defined Interrupt 143 */ - .long IRQDefault /* User-Defined Interrupt 144 */ - .long IRQDefault /* User-Defined Interrupt 145 */ - .long IRQDefault /* User-Defined Interrupt 146 */ - .long IRQDefault /* User-Defined Interrupt 147 */ - .long IRQDefault /* User-Defined Interrupt 148 */ - .long IRQDefault /* User-Defined Interrupt 149 */ - .long IRQDefault /* User-Defined Interrupt 150 */ - .long IRQDefault /* User-Defined Interrupt 151 */ - .long IRQDefault /* User-Defined Interrupt 152 */ - .long IRQDefault /* User-Defined Interrupt 153 */ - .long IRQDefault /* User-Defined Interrupt 154 */ - .long IRQDefault /* User-Defined Interrupt 155 */ - .long IRQDefault /* User-Defined Interrupt 156 */ - .long IRQDefault /* User-Defined Interrupt 157 */ - .long IRQDefault /* User-Defined Interrupt 158 */ - .long IRQDefault /* User-Defined Interrupt 159 */ - .long IRQDefault /* User-Defined Interrupt 160 */ - .long IRQDefault /* User-Defined Interrupt 161 */ - .long IRQDefault /* User-Defined Interrupt 162 */ - .long IRQDefault /* User-Defined Interrupt 163 */ - .long IRQDefault /* User-Defined Interrupt 164 */ - .long IRQDefault /* User-Defined Interrupt 165 */ - .long IRQDefault /* User-Defined Interrupt 166 */ - .long IRQDefault /* User-Defined Interrupt 167 */ - .long IRQDefault /* User-Defined Interrupt 168 */ - .long IRQDefault /* User-Defined Interrupt 169 */ - .long IRQDefault /* User-Defined Interrupt 170 */ - .long IRQDefault /* User-Defined Interrupt 171 */ - .long IRQDefault /* User-Defined Interrupt 172 */ - .long IRQDefault /* User-Defined Interrupt 173 */ - .long IRQDefault /* User-Defined Interrupt 174 */ - .long IRQDefault /* User-Defined Interrupt 175 */ - .long IRQDefault /* User-Defined Interrupt 176 */ - .long IRQDefault /* User-Defined Interrupt 177 */ - .long IRQDefault /* User-Defined Interrupt 178 */ - .long IRQDefault /* User-Defined Interrupt 179 */ - .long IRQDefault /* User-Defined Interrupt 180 */ - .long IRQDefault /* User-Defined Interrupt 181 */ - .long IRQDefault /* User-Defined Interrupt 182 */ - .long IRQDefault /* User-Defined Interrupt 183 */ - .long IRQDefault /* User-Defined Interrupt 184 */ - .long IRQDefault /* User-Defined Interrupt 185 */ - .long IRQDefault /* User-Defined Interrupt 186 */ - .long IRQDefault /* User-Defined Interrupt 187 */ - .long IRQDefault /* User-Defined Interrupt 188 */ - .long IRQDefault /* User-Defined Interrupt 189 */ - .long IRQDefault /* User-Defined Interrupt 190 */ - .long IRQDefault /* User-Defined Interrupt 191 */ - .org 0x00000400 - - .section .vector_ram -__RAMVEC: - .space 0x400 - - .section .text -VecDefault: - halt - bra VecDefault - -IRQDefault: - halt - bra IRQDefault - -IRQSpurious: - halt - bra IRQSpurious - -TrapDefault: - halt - bra TrapDefault diff --git a/Demo/MicroBlaze/FreeRTOSConfig.h b/Demo/MicroBlaze/FreeRTOSConfig.h deleted file mode 100644 index bac7f73d3..000000000 --- a/Demo/MicroBlaze/FreeRTOSConfig.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -#include "xparameters.h" - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 100000000 ) -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 120 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 18 * 1024 ) ) -#define configMAX_TASK_NAME_LEN ( 5 ) -#define configUSE_TRACE_FACILITY 0 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 0 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 0 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/MicroBlaze/ParTest/ParTest.c b/Demo/MicroBlaze/ParTest/ParTest.c deleted file mode 100644 index b4db827d6..000000000 --- a/Demo/MicroBlaze/ParTest/ParTest.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/*----------------------------------------------------------- - * Simple parallel port IO routines. - *-----------------------------------------------------------*/ - -/* Kernel includes. */ -#include "FreeRTOS.h" - -/* Demo application includes. */ -#include "partest.h" - -/* Library includes. */ -#include "xgpio_l.h" - -/* Misc hardware specific definitions. */ -#define partstALL_AS_OUTPUT 0x00 -#define partstCHANNEL_1 0x01 -#define partstMAX_4BIT_LED 0x03 - -/* The outputs are split into two IO sections, these variables maintain the -current value of either section. */ -static unsigned portBASE_TYPE uxCurrentOutput4Bit, uxCurrentOutput5Bit; - -/*-----------------------------------------------------------*/ -/* - * Setup the IO for the LED outputs. - */ -void vParTestInitialise( void ) -{ - /* Set both sets of LED's on the demo board to outputs. */ - XGpio_mSetDataDirection( XPAR_LEDS_4BIT_BASEADDR, partstCHANNEL_1, partstALL_AS_OUTPUT ); - XGpio_mSetDataDirection( XPAR_LEDS_POSITIONS_BASEADDR, partstCHANNEL_1, partstALL_AS_OUTPUT ); - - /* Start with all outputs off. */ - uxCurrentOutput4Bit = 0; - XGpio_mSetDataReg( XPAR_LEDS_4BIT_BASEADDR, partstCHANNEL_1, 0x00 ); - uxCurrentOutput5Bit = 0; - XGpio_mSetDataReg( XPAR_LEDS_POSITIONS_BASEADDR, partstCHANNEL_1, 0x00 ); -} -/*-----------------------------------------------------------*/ - -void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) -{ -unsigned portBASE_TYPE uxBaseAddress, *puxCurrentValue; - - portENTER_CRITICAL(); - { - /* Which IO section does the LED being set/cleared belong to? The - 4 bit or 5 bit outputs? */ - if( uxLED <= partstMAX_4BIT_LED ) - { - uxBaseAddress = XPAR_LEDS_4BIT_BASEADDR; - puxCurrentValue = &uxCurrentOutput4Bit; - } - else - { - uxBaseAddress = XPAR_LEDS_POSITIONS_BASEADDR; - puxCurrentValue = &uxCurrentOutput5Bit; - uxLED -= partstMAX_4BIT_LED; - } - - /* Setup the bit mask accordingly. */ - uxLED = 0x01 << uxLED; - - /* Maintain the current output value. */ - if( xValue ) - { - *puxCurrentValue |= uxLED; - } - else - { - *puxCurrentValue &= ~uxLED; - } - - /* Write the value to the port. */ - XGpio_mSetDataReg( uxBaseAddress, partstCHANNEL_1, *puxCurrentValue ); - } - portEXIT_CRITICAL(); -} -/*-----------------------------------------------------------*/ - -void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) -{ -unsigned portBASE_TYPE uxBaseAddress, *puxCurrentValue; - - portENTER_CRITICAL(); - { - /* Which IO section does the LED being toggled belong to? The - 4 bit or 5 bit outputs? */ - if( uxLED <= partstMAX_4BIT_LED ) - { - uxBaseAddress = XPAR_LEDS_4BIT_BASEADDR; - puxCurrentValue = &uxCurrentOutput4Bit; - } - else - { - uxBaseAddress = XPAR_LEDS_POSITIONS_BASEADDR; - puxCurrentValue = &uxCurrentOutput5Bit; - uxLED -= partstMAX_4BIT_LED; - } - - /* Setup the bit mask accordingly. */ - uxLED = 0x01 << uxLED; - - /* Maintain the current output value. */ - if( *puxCurrentValue & uxLED ) - { - *puxCurrentValue &= ~uxLED; - } - else - { - *puxCurrentValue |= uxLED; - } - - /* Write the value to the port. */ - XGpio_mSetDataReg(uxBaseAddress, partstCHANNEL_1, *puxCurrentValue ); - } - portEXIT_CRITICAL(); -} - - diff --git a/Demo/MicroBlaze/__xps/bitinit.opt b/Demo/MicroBlaze/__xps/bitinit.opt deleted file mode 100644 index 2496fab76..000000000 --- a/Demo/MicroBlaze/__xps/bitinit.opt +++ /dev/null @@ -1 +0,0 @@ - -pe microblaze_0 RTOSDemo/executable.elf diff --git a/Demo/MicroBlaze/__xps/libgen.opt b/Demo/MicroBlaze/__xps/libgen.opt deleted file mode 100644 index 77b154845..000000000 --- a/Demo/MicroBlaze/__xps/libgen.opt +++ /dev/null @@ -1 +0,0 @@ - -p virtex4 diff --git a/Demo/MicroBlaze/__xps/platgen.opt b/Demo/MicroBlaze/__xps/platgen.opt deleted file mode 100644 index f56ee64ea..000000000 --- a/Demo/MicroBlaze/__xps/platgen.opt +++ /dev/null @@ -1 +0,0 @@ - -p virtex4 -lang vhdl -st xst diff --git a/Demo/MicroBlaze/__xps/rtosdemo_compiler.opt b/Demo/MicroBlaze/__xps/rtosdemo_compiler.opt deleted file mode 100644 index c108c4082..000000000 --- a/Demo/MicroBlaze/__xps/rtosdemo_compiler.opt +++ /dev/null @@ -1,23 +0,0 @@ -microblaze_0 -RTOSDEMO_SOURCES = main.c ParTest/ParTest.c ../../Source/tasks.c ../../Source/queue.c ../../Source/list.c ../../Source/portable/MemMang/heap_1.c ../../Source/portable/GCC/MicroBlaze/port.c ../../Source/portable/GCC/MicroBlaze/portasm.s ../Common/Minimal/flash.c serial/serial.c ../Common/Minimal/comtest.c ../Common/Minimal/integer.c ../Common/Minimal/semtest.c ../Common/Minimal/dynamic.c ../Common/Minimal/PollQ.c ../Common/Minimal/BlockQ.c -RTOSDEMO_HEADERS = FreeRTOSConfig.h -RTOSDEMO_CC = mb-gcc -RTOSDEMO_CC_SIZE = mb-size -RTOSDEMO_CC_OPT = -Os -RTOSDEMO_CFLAGS = -D MICROBLAZE_GCC -Wall -RTOSDEMO_CC_SEARCH = # -B -RTOSDEMO_LIBPATH = -L./microblaze_0/lib/ # -L -RTOSDEMO_INCLUDES = -I./microblaze_0/include/ -IDev/FreeRTOS/Demo/MicroBlaze/ -I. -I../Common/include -I../../Source/include -I../../Source/portable/GCC/MicroBlaze -RTOSDEMO_LFLAGS = # -l -RTOSDEMO_CC_PREPROC_FLAG = # -Wp, -RTOSDEMO_CC_ASM_FLAG = # -Wa, -RTOSDEMO_CC_LINKER_FLAG = -Wl,-Map=rtosdemo.map -RTOSDEMO_LINKER_SCRIPT = -RTOSDEMO_CC_DEBUG_FLAG = -g -RTOSDEMO_CC_GLOBPTR_FLAG= # -mxl-gp-opt -RTOSDEMO_MODE = executable -RTOSDEMO_LIBG_OPT = -$(RTOSDEMO_MODE) microblaze_0 -RTOSDEMO_CC_SOFTMUL_FLAG= -mno-xl-soft-mul -RTOSDEMO_CC_START_ADDR_FLAG= # -Wl,-defsym -Wl,_TEXT_START_ADDR= -RTOSDEMO_CC_STACK_SIZE_FLAG= # -Wl,-defsym -Wl,_STACK_SIZE= - $(RTOSDEMO_CC_SOFTMUL_FLAG) \ diff --git a/Demo/MicroBlaze/__xps/simgen.opt b/Demo/MicroBlaze/__xps/simgen.opt deleted file mode 100644 index 236453ae0..000000000 --- a/Demo/MicroBlaze/__xps/simgen.opt +++ /dev/null @@ -1 +0,0 @@ - -p virtex4 -lang vhdl -pe microblaze_0 RTOSDemo/executable.elf -s mti diff --git a/Demo/MicroBlaze/__xps/testapp_peripheral_compiler.opt b/Demo/MicroBlaze/__xps/testapp_peripheral_compiler.opt deleted file mode 100644 index 67e70306a..000000000 --- a/Demo/MicroBlaze/__xps/testapp_peripheral_compiler.opt +++ /dev/null @@ -1,23 +0,0 @@ -microblaze_0 -TESTAPP_PERIPHERAL_SOURCES = TestApp_Peripheral/src/TestApp_Peripheral.c TestApp_Peripheral/src/xuartlite_selftest_example.c -TESTAPP_PERIPHERAL_HEADERS = -TESTAPP_PERIPHERAL_CC = mb-gcc -TESTAPP_PERIPHERAL_CC_SIZE = mb-size -TESTAPP_PERIPHERAL_CC_OPT = -O2 -TESTAPP_PERIPHERAL_CFLAGS = -TESTAPP_PERIPHERAL_CC_SEARCH = # -B -TESTAPP_PERIPHERAL_LIBPATH = -L./microblaze_0/lib/ # -L -TESTAPP_PERIPHERAL_INCLUDES = -I./microblaze_0/include/ # -I -TESTAPP_PERIPHERAL_LFLAGS = # -l -TESTAPP_PERIPHERAL_CC_PREPROC_FLAG = # -Wp, -TESTAPP_PERIPHERAL_CC_ASM_FLAG = # -Wa, -TESTAPP_PERIPHERAL_CC_LINKER_FLAG = # -Wl, -TESTAPP_PERIPHERAL_LINKER_SCRIPT = TestApp_Peripheral/src/TestApp_Peripheral_LinkScr -TESTAPP_PERIPHERAL_CC_DEBUG_FLAG = -g -TESTAPP_PERIPHERAL_CC_GLOBPTR_FLAG= # -mxl-gp-opt -TESTAPP_PERIPHERAL_MODE = executable -TESTAPP_PERIPHERAL_LIBG_OPT = -$(TESTAPP_PERIPHERAL_MODE) microblaze_0 -TESTAPP_PERIPHERAL_CC_SOFTMUL_FLAG= -mno-xl-soft-mul -TESTAPP_PERIPHERAL_CC_START_ADDR_FLAG= # -Wl,-defsym -Wl,_TEXT_START_ADDR= -TESTAPP_PERIPHERAL_CC_STACK_SIZE_FLAG= # -Wl,-defsym -Wl,_STACK_SIZE= - $(TESTAPP_PERIPHERAL_CC_SOFTMUL_FLAG) \ diff --git a/Demo/MicroBlaze/__xps/vpgen.opt b/Demo/MicroBlaze/__xps/vpgen.opt deleted file mode 100644 index 8ea8f6640..000000000 --- a/Demo/MicroBlaze/__xps/vpgen.opt +++ /dev/null @@ -1 +0,0 @@ - -p xc4vfx12ff668-10 diff --git a/Demo/MicroBlaze/__xps/xpsxflow.opt b/Demo/MicroBlaze/__xps/xpsxflow.opt deleted file mode 100644 index bf6b9048d..000000000 --- a/Demo/MicroBlaze/__xps/xpsxflow.opt +++ /dev/null @@ -1 +0,0 @@ --device xc4vfx12ff668-10 diff --git a/Demo/MicroBlaze/_impact.cmd b/Demo/MicroBlaze/_impact.cmd deleted file mode 100644 index a712a7180..000000000 --- a/Demo/MicroBlaze/_impact.cmd +++ /dev/null @@ -1,7 +0,0 @@ -setMode -bs -setCable -port auto -identify -identifyMPM -setAttribute -position 3 -attr configFileName -value "implementation/download.bit" -program -p 3 -quit diff --git a/Demo/MicroBlaze/crt0.s b/Demo/MicroBlaze/crt0.s deleted file mode 100644 index 8198096e8..000000000 --- a/Demo/MicroBlaze/crt0.s +++ /dev/null @@ -1,126 +0,0 @@ -###################################-*-asm*- -# -# Copyright (c) 2001 Xilinx, Inc. All rights reserved. -# -# Xilinx, Inc. CONFIDENTIAL -# -# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR -# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION -# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE -# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO -# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE -# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY -# AND FITNESS FOR A PARTICULAR PURPOSE. -# -# crt0.s -# -# C RunTime: -# Used for initialization of small data -# anchors and stack for programs compiled using -# Xilinx Gnu Tools. This routine also intializes the -# exception and interrupt handlers -# -# $Id: crt0.s,v 1.1.4.2 2005/05/26 21:50:39 vasanth Exp $ -# -####################################### - -/* Vector map (Interrupts, Exceptions, Breakpoints) */ -# # 0x00 # Jump to Start -# # 0x04 # nop -# # 0x08 # Imm instr for soft exception address [Hi halfword] -# # 0x0c # Jump to sof Exception handler [Lo halfword] -# # 0x10 # Imm instr for interrupt address [Hi halfword] -# # 0x14 # Jump to interrupt handler [Lo halfword] -# # 0x18 # nop - Reserved for breakpoint vector -# # 0x1C # nop - Reserved for breakpoint vector -# # 0x20 # Imm instr for hw exception address [Hi halfword] -# # 0x24 # Jump instr to hw exception handler [Lo halfword] - - .globl _start - -/* Set the exception and interrupt address vectors */ -/* to jump to the appropriate handlers */ - - .align 2 - .ent _start - _start: - bri _start1 # 0x00 - nop # 0x04 - nop # 0x08 # Reserve space for software exception vector - nop # 0x0c - nop # 0x10 # Reserve space for interrupt vector - nop # 0x14 - nop # 0x18 # Reserve space for breakpoint vector - nop # 0x1c - nop # 0x18 # Reserve space for hw exception vector - nop # 0x1c - - _start1: -/* Set the Small Data Anchors and the Stack pointer */ - la r13, r0, _SDA_BASE_ - la r2, r0, _SDA2_BASE_ - la r1, r0, _stack-16 # 16 bytes (4 words are needed by - # crt for args and link reg ) - -/* Set the opcodes brai and imm for handlers */ - la r6,r0,0xb8080000 # [opcode for brai ] - swi r6,r0,0x4 # [brai opcode for reset] - swi r6,r0,0xc # [brai opcode for exception] - swi r6,r0,0x14 # [brai opcode for interrupt] - swi r6,r0,0x24 # [brai opcode for hw exceptions] - - la r6,r0,0xb0000000 # [opcode for imm ] - swi r6,r0,0x0 # [imm opcode for reset] - swi r6,r0,0x8 # [imm opcode for exception] - swi r6,r0,0x10 # [imm opocde for interrupt] - swi r6,r0,0x20 # [imm opocde for hw exceptions] - -/* Set Reset vector */ - la r6,r0,_start1 - sw r6,r1,r0 - lhu r7,r1,r0 - shi r7,r0, 0x2 # [imm for reset] - shi r6,r0, 0x6 # [lower half for reset] - -/* Set Software Exception Handler */ - la r6,r0,_exception_handler - sw r6,r1,r0 - lhu r7,r1,r0 - shi r7,r0, 0xa # [imm for exception] - shi r6,r0, 0xe # [lower half for exception ] - -/* Set Interrupt Handler */ - la r6,r0,_interrupt_handler - sw r6,r1,r0 - lhu r7,r1,r0 - shi r7,r0, 0x12 # [imm for exception] - shi r6,r0, 0x16 # [lower half for intterupt ] - -/* Set HW Exception Handler */ - la r6,r0,_hw_exception_handler - sw r6,r1,r0 - lhu r7,r1,r0 - shi r7,r0, 0x22 # [imm for exception] - shi r6,r0, 0x26 # [lower half for hw exception] - -/* initialize bss sections */ - brlid r15,_crtinit - nop - -/* Adjust the stack pointer */ - addi r1,r1,16 - -/* Fall through to exit */ - .end _start - -/* Use this exit function */ - .globl exit # exit library call - .ent exit -exit: - bri exit - .end exit - diff --git a/Demo/MicroBlaze/data/system.ucf b/Demo/MicroBlaze/data/system.ucf deleted file mode 100644 index 81a63a2f8..000000000 --- a/Demo/MicroBlaze/data/system.ucf +++ /dev/null @@ -1,74 +0,0 @@ -############################################################################ -## This system.ucf file is generated by Base System Builder based on the -## settings in the selected Xilinx Board Definition file. Please add other -## user constraints to this file based on customer design specifications. -############################################################################ - -Net sys_clk_pin LOC=AE14; -Net sys_clk_pin IOSTANDARD = LVCMOS33; -Net sys_rst_pin LOC=D6; -Net sys_rst_pin PULLUP; -## System level constraints -Net sys_clk_pin TNM_NET = sys_clk_pin; -TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10000 ps; -Net sys_rst_pin TIG; - -## FPGA pin constraints -Net fpga_0_RS232_Uart_RX_pin LOC=W2; -Net fpga_0_RS232_Uart_RX_pin IOSTANDARD = LVCMOS33; -Net fpga_0_RS232_Uart_TX_pin LOC=W1; -Net fpga_0_RS232_Uart_TX_pin IOSTANDARD = LVCMOS33; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> LOC=G5; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> PULLUP; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> SLEW = SLOW; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> DRIVE = 2; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> TIG; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> LOC=G6; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> PULLUP; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> SLEW = SLOW; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> DRIVE = 2; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> TIG; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> LOC=A11; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> PULLUP; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> SLEW = SLOW; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> DRIVE = 2; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> TIG; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> LOC=A12; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> PULLUP; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> SLEW = SLOW; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> DRIVE = 2; -Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> TIG; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> LOC=C6; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> PULLUP; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> SLEW = SLOW; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> DRIVE = 2; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> TIG; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> LOC=F9; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> PULLUP; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> SLEW = SLOW; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> DRIVE = 2; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> TIG; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> LOC=A5; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> PULLUP; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> SLEW = SLOW; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> DRIVE = 2; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> TIG; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> LOC=E10; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> PULLUP; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> SLEW = SLOW; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> DRIVE = 2; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> TIG; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> LOC=E2; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> IOSTANDARD = LVCMOS25; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> PULLUP; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> SLEW = SLOW; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> DRIVE = 2; -Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> TIG; diff --git a/Demo/MicroBlaze/etc/bitgen.ut b/Demo/MicroBlaze/etc/bitgen.ut deleted file mode 100644 index 442444880..000000000 --- a/Demo/MicroBlaze/etc/bitgen.ut +++ /dev/null @@ -1,21 +0,0 @@ --g ConfigRate:4 --g CclkPin:PULLUP --g TdoPin:PULLNONE --g M1Pin:PULLDOWN --g DonePin:PULLUP --g DriveDone:No --g StartUpClk:JTAGCLK --g DONE_cycle:4 --g GTS_cycle:5 --g M0Pin:PULLUP --g M2Pin:PULLUP --g ProgPin:PULLUP --g TckPin:PULLUP --g TdiPin:PULLUP --g TmsPin:PULLUP --g DonePipe:No --g GWE_cycle:6 --g LCK_cycle:NoWait --g Security:NONE --m --g Persist:No diff --git a/Demo/MicroBlaze/etc/bitgen_spartan3.ut b/Demo/MicroBlaze/etc/bitgen_spartan3.ut deleted file mode 100644 index 65522563b..000000000 --- a/Demo/MicroBlaze/etc/bitgen_spartan3.ut +++ /dev/null @@ -1,15 +0,0 @@ --g CclkPin:PULLUP --g TdoPin:PULLNONE --g M1Pin:PULLDOWN --g DonePin:PULLUP --g StartUpClk:JTAGCLK --g M0Pin:PULLUP --g M2Pin:PULLUP --g ProgPin:PULLUP --g TckPin:PULLUP --g TdiPin:PULLUP --g TmsPin:PULLUP --g LCK_cycle:NoWait --g Security:NONE --m --g Persist:No diff --git a/Demo/MicroBlaze/etc/download.cmd b/Demo/MicroBlaze/etc/download.cmd deleted file mode 100644 index 15728dcff..000000000 --- a/Demo/MicroBlaze/etc/download.cmd +++ /dev/null @@ -1,6 +0,0 @@ -setMode -bscan -setCable -p auto -identify -assignfile -p 3 -file implementation/download.bit -program -p 3 -quit diff --git a/Demo/MicroBlaze/etc/fast_runtime.opt b/Demo/MicroBlaze/etc/fast_runtime.opt deleted file mode 100644 index 7335e7a21..000000000 --- a/Demo/MicroBlaze/etc/fast_runtime.opt +++ /dev/null @@ -1,80 +0,0 @@ -FLOWTYPE = FPGA; -############################################################### -## Filename: fast_runtime.opt -## -## Option File For Xilinx FPGA Implementation Flow for Fast -## Runtime. -## -## Version: 4.1.1 -############################################################### -# -# Options for Translator -# -# Type "ngdbuild -h" for a detailed list of ngdbuild command line options -# -Program ngdbuild --p ; # Partname to use - picked from xflow commandline --nt timestamp; # NGO File generation. Regenerate only when - # source netlist is newer than existing - # NGO file (default) --bm .bmm # Block RAM memory map file -; # User design - pick from xflow command line --uc .ucf; # ucf constraints -.ngd; # Name of NGD file. Filebase same as design filebase -End Program ngdbuild - -# -# Options for Mapper -# -# Type "map -h " for a detailed list of map command line options -# -Program map --o _map.ncd; # Output Mapped ncd file --pr b; # Pack internal FF/latches into IOBs -#-fp .mfp; # Floorplan file -.ngd; # Input NGD file -.pcf; # Physical constraints file -END Program map - -# -# Options for Post Map Trace -# -# Type "trce -h" for a detailed list of trce command line options -# -Program post_map_trce --e 3; # Produce error report limited to 3 items per constraint -#-o _map.twr; # Output trace report file --xml _map.twx; # Output XML version of the timing report -#-tsi _map.tsi; # Produce Timing Specification Interaction report -_map.ncd; # Input mapped ncd -.pcf; # Physical constraints file -END Program post_map_trce - -# -# Options for Place and Route -# -# Type "par -h" for a detailed list of par command line options -# -Program par --w; # Overwrite existing placed and routed ncd --ol high; # Overall effort level -_map.ncd; # Input mapped NCD file -.ncd; # Output placed and routed NCD -.pcf; # Input physical constraints file -END Program par - -# -# Options for Post Par Trace -# -# Type "trce -h" for a detailed list of trce command line options -# -Program post_par_trce --e 3; # Produce error report limited to 3 items per constraint -#-o .twr; # Output trace report file --xml .twx; # Output XML version of the timing report -#-tsi .tsi; # Produce Timing Specification Interaction report -.ncd; # Input placed and routed ncd -.pcf; # Physical constraints file -END Program post_par_trce - - diff --git a/Demo/MicroBlaze/etc/xmd_microblaze_0.opt b/Demo/MicroBlaze/etc/xmd_microblaze_0.opt deleted file mode 100644 index 43994b0af..000000000 --- a/Demo/MicroBlaze/etc/xmd_microblaze_0.opt +++ /dev/null @@ -1 +0,0 @@ -connect mb mdm -cable type xilinx_parallel port LPT1 frequency 5000000 -debugdevice cpunr 1 diff --git a/Demo/MicroBlaze/main.c b/Demo/MicroBlaze/main.c deleted file mode 100644 index b6f31570c..000000000 --- a/Demo/MicroBlaze/main.c +++ /dev/null @@ -1,436 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * Creates all the demo application tasks, then starts the scheduler. The WEB - * documentation provides more details of the standard demo application tasks. - * - * In addition to the standard tasks, main() creates two "Register Check" - * tasks. These tasks write known values into every general purpose register, - * then check each register to ensure it still contains the expected (written) - * value. The register check tasks operate at the idle priority so will get - * repeatedly preempted. A register being found to contain an incorrect value - * following such a preemption would be indicative of an error in the context - * switch mechanism. - * - * Main.c also creates a task called "Check". This only executes every three - * seconds but has the highest priority so is guaranteed to get processor time. - * Its main function is to check that all the other tasks are still operational. - * Each task (other than the "flash" tasks) maintains a unique count that is - * incremented each time the task successfully completes its function. Should - * any error occur within such a task the count is permanently halted. The - * check task inspects the count of each task to ensure it has changed since - * the last time the check task executed. If all the count variables have - * changed all the tasks are still executing error free, and the check task - * toggles the onboard LED. Should any task contain an error at any time - * the LED toggle rate will change from 3 seconds to 500ms. - * - */ - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Demo application includes. */ -#include "ParTest.h" -#include "flash.h" -#include "comtest2.h" -#include "integer.h" -#include "semtest.h" -#include "BlockQ.h" -#include "dynamic.h" -#include "PollQ.h" - -/* Hardware library includes. */ -#include - -/* The rate at which the 'check' LED will flash when no errors have been -detected. */ -#define mainNO_ERROR_CHECK_PERIOD 3000 - -/* The rate at which the 'check' LED will flash when an error has been -detected in one of the demo tasks. */ -#define mainERROR_CHECK_PERIOD 500 - -/* Demo application task priorities. */ -#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) - -/* Software cannot influence the BAUD rate used by the simple UART -implementation. */ -#define mainBAUD_RATE 0 - -/* The LED flashed by the 'check' task to indicate the system status. */ -#define mainCHECK_TASK_LED 3 - -/* The first LED flashed by the COM port test tasks. LED mainCOM_TEST_LED + 1 -will also be used. */ -#define mainCOM_TEST_LED 4 - -/* The register test task does not make any function calls so does not require -much stack at all. */ -#define mainTINY_STACK 70 - -/* - * The task that executes at the highest priority and calls - * prvCheckOtherTasksAreStillRunning(). See the description at the top - * of the file. - */ -static void vErrorChecks( void *pvParameters ); - -/* - * Checks that all the demo application tasks are still executing without error - * - as described at the top of the file. - */ -static portBASE_TYPE prvCheckOtherTasksAreStillRunning( void ); - -/* - * The register test task as described at the top of this file. - */ -static void vRegisterTest( void *pvParameters ); - -/* - * Perform any necessary hardware configuration. - */ -static void prvSetupHardware( void ); - -/* Set to pdFAIL should an error be discovered in the register test tasks. */ -static unsigned portLONG ulRegisterTestStatus = pdPASS; -const unsigned portLONG *pulStatusAddr = &ulRegisterTestStatus; - -/*-----------------------------------------------------------*/ - -/* - * Create all the demo tasks - then start the scheduler. - */ -int main (void) -{ - /* When re-starting a debug session (rather than cold booting) we want - to ensure the installed interrupt handlers do not execute until after the - scheduler has been started. */ - portDISABLE_INTERRUPTS(); - - prvSetupHardware(); - - /* Start the standard demo application tasks. */ - vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); - vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainBAUD_RATE, mainCOM_TEST_LED ); - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - vStartDynamicPriorityTasks(); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - - /* Create two register check tasks - using a different parameter for each. - The parameter is used to generate the known values written to the registers. */ - #if configUSE_PREEMPTION == 1 - xTaskCreate( vRegisterTest, "Reg1", mainTINY_STACK, ( void * ) 10, tskIDLE_PRIORITY, NULL ); - xTaskCreate( vRegisterTest, "Reg2", mainTINY_STACK, ( void * ) 20, tskIDLE_PRIORITY, NULL ); - #endif - - /* Create the 'check' task that is defined in this file. */ - xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - - /* Finally start the scheduler. */ - vTaskStartScheduler(); - - /* Should not get here as the processor is now under control of the - scheduler! */ - - return 0; -} -/*-----------------------------------------------------------*/ - -static void vErrorChecks( void *pvParameters ) -{ -portTickType xDelayPeriod = mainNO_ERROR_CHECK_PERIOD; - - /* The parameters are not used. */ - ( void ) pvParameters; - - /* Cycle for ever, delaying then checking all the other tasks are still - operating without error. The delay period used will depend on whether - or not an error has been discovered in one of the demo tasks. */ - for( ;; ) - { - vTaskDelay( xDelayPeriod ); - if( !prvCheckOtherTasksAreStillRunning() ) - { - /* An error has been found. Shorten the delay period to make - the LED flash faster. */ - xDelayPeriod = mainERROR_CHECK_PERIOD; - } - - vParTestToggleLED( mainCHECK_TASK_LED ); - } -} -/*-----------------------------------------------------------*/ - -static portBASE_TYPE prvCheckOtherTasksAreStillRunning( void ) -{ -static portBASE_TYPE xAllTestsPass = pdTRUE; - - /* Return pdFALSE if any demo application task set has encountered - an error. */ - - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - xAllTestsPass = pdFALSE; - } - - if( xAreComTestTasksStillRunning() != pdTRUE ) - { - xAllTestsPass = pdFALSE; - } - - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - xAllTestsPass = pdFALSE; - } - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - xAllTestsPass = pdFAIL; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - xAllTestsPass = ( portLONG ) pdFAIL; - } - - if( xArePollingQueuesStillRunning() != pdTRUE ) - { - xAllTestsPass = ( portLONG ) pdFAIL; - } - - /* Mutual exclusion on this variable is not necessary as we only read it. */ - if( ulRegisterTestStatus != pdPASS ) - { - xAllTestsPass = pdFALSE; - } - - return xAllTestsPass; -} -/*-----------------------------------------------------------*/ - -static void prvSetupHardware( void ) -{ - /* Ensure the interrupt controller is enabled in order that subsequent - code can successfully configure the peripherals. */ - XIntc_mMasterEnable( XPAR_OPB_INTC_0_BASEADDR ); - - /* Initialise the GPIO used for the LED's. */ - vParTestInitialise(); -} -/*-----------------------------------------------------------*/ - -static void vRegisterTest( void *pvParameters ) -{ - for( ;; ) - { - /* Fill the registers with their register number plus the offset - (added) value. The added value is passed in as a parameter so - is contained in r5. */ - asm volatile ( "addi r3, r5, 3 \n\t" \ - "addi r4, r5, 4 \n\t" \ - "addi r6, r5, 6 \n\t" \ - "addi r7, r5, 7 \n\t" \ - "addi r8, r5, 8 \n\t" \ - "addi r9, r5, 9 \n\t" \ - "addi r10, r5, 10 \n\t" \ - "addi r11, r5, 11 \n\t" \ - "addi r12, r5, 12 \n\t" \ - "addi r16, r5, 16 \n\t" \ - "addi r17, r5, 17 \n\t" \ - "addi r18, r5, 18 \n\t" \ - "addi r19, r5, 19 \n\t" \ - "addi r20, r5, 20 \n\t" \ - "addi r21, r5, 21 \n\t" \ - "addi r22, r5, 22 \n\t" \ - "addi r23, r5, 23 \n\t" \ - "addi r24, r5, 24 \n\t" \ - "addi r25, r5, 25 \n\t" \ - "addi r26, r5, 26 \n\t" \ - "addi r27, r5, 27 \n\t" \ - "addi r28, r5, 28 \n\t" \ - "addi r29, r5, 29 \n\t" \ - "addi r30, r5, 30 \n\t" \ - "addi r31, r5, 31 \n\t" - ); - - /* Now read back the register values to ensure they are as we expect. - This task will get preempted frequently so other tasks are likely to - have executed since the register values were written. */ - - /* r3 should contain r5 + 3. Subtract 3 to leave r3 equal to r5. */ - asm volatile ( "addi r3, r3, -3 " ); - - /* Compare r3 and r5. If they are not equal then either r3 or r5 - contains the wrong value and *pulStatusAddr is to pdFAIL. */ - asm volatile ( "cmp r3, r3, r5 \n\t" \ - "beqi r3, 12 \n\t" \ - "lwi r3, r0, pulStatusAddr \n\t" \ - "sw r0, r0, r3 \n\t" - ); - - /* Repeat for all the other registers. */ - asm volatile ( "addi r4, r4, -4 \n\t" \ - "cmp r4, r4, r5 \n\t" \ - "beqi r4, 12 \n\t" \ - "lwi r3, r0, pulStatusAddr \n\t" \ - "sw r0, r0, r3 \n\t" \ - "addi r6, r6, -6 \n\t" \ - "cmp r6, r6, r5 \n\t" \ - "beqi r6, 12 \n\t" \ - "lwi r3, r0, pulStatusAddr \n\t" \ - "sw r0, r0, r3 \n\t" \ - "addi r7, r7, -7 \n\t" \ - "cmp r7, r7, r5 \n\t" \ - "beqi r7, 12 \n\t" \ - "lwi r3, r0, pulStatusAddr \n\t" \ - "sw r0, r0, r3 \n\t" \ - "addi r8, r8, -8 \n\t" \ - "cmp r8, r8, r5 \n\t" \ - "beqi r8, 12 \n\t" \ - "lwi r3, r0, pulStatusAddr \n\t" \ - "sw r0, r0, r3 \n\t" \ - "addi r9, r9, -9 \n\t" \ - "cmp r9, r9, r5 \n\t" \ - "beqi r9, 12 \n\t" \ - "lwi r3, r0, pulStatusAddr \n\t" \ - "sw r0, r0, r3 \n\t" \ - "addi r10, r10, -10 \n\t" \ - "cmp r10, r10, r5 \n\t" \ - "beqi r10, 12 \n\t" \ - "lwi r3, r0, pulStatusAddr \n\t" \ - "sw r0, r0, r3 \n\t" \ - "addi r11, r11, -11 \n\t" \ - "cmp r11, r11, r5 \n\t" \ - "beqi r11, 12 \n\t" \ - "lwi r3, r0, pulStatusAddr \n\t" \ - "sw r0, r0, r3 \n\t" \ - "addi r12, r12, -12 \n\t" \ - "cmp r12, r12, r5 \n\t" \ - "beqi r12, 12 \n\t" \ - "lwi r3, r0, pulStatusAddr \n\t" \ - "sw r0, r0, r3 \n\t" \ - "sw r0, r0, r3 \n\t" \ - "addi r16, r16, -16 \n\t" \ - "cmp r16, r16, r5 \n\t" \ - "beqi r16, 12 \n\t" \ - "lwi r3, r0, pulStatusAddr \n\t" \ - "sw r0, r0, r3 \n\t" \ - "addi r17, r17, -17 \n\t" \ - "cmp r17, r17, r5 \n\t" \ - "beqi r17, 12 \n\t" \ - "lwi r3, r0, pulStatusAddr \n\t" \ - "sw r0, r0, r3 \n\t" \ - "addi r18, r18, -18 \n\t" \ - "cmp r18, r18, r5 \n\t" \ - "beqi r18, 12 \n\t" \ - "lwi r3, r0, pulStatusAddr \n\t" \ - "sw r0, r0, r3 \n\t" \ - "addi r19, r19, -19 \n\t" \ - "cmp r19, r19, r5 \n\t" \ - "beqi r19, 12 \n\t" \ - "lwi r3, r0, pulStatusAddr \n\t" \ - "sw r0, r0, r3 \n\t" \ - "addi r20, r20, -20 \n\t" \ - "cmp r20, r20, r5 \n\t" \ - "beqi r20, 12 \n\t" \ - "lwi r3, r0, pulStatusAddr \n\t" \ - "sw r0, r0, r3 \n\t" \ - "addi r21, r21, -21 \n\t" \ - "cmp r21, r21, r5 \n\t" \ - "beqi r21, 12 \n\t" \ - "lwi r3, r0, pulStatusAddr \n\t" \ - "sw r0, r0, r3 \n\t" \ - "addi r22, r22, -22 \n\t" \ - "cmp r22, r22, r5 \n\t" \ - "beqi r22, 12 \n\t" \ - "lwi r3, r0, pulStatusAddr \n\t" \ - "sw r0, r0, r3 \n\t" \ - "addi r23, r23, -23 \n\t" \ - "cmp r23, r23, r5 \n\t" \ - "beqi r23, 12 \n\t" \ - "lwi r3, r0, pulStatusAddr \n\t" \ - "sw r0, r0, r3 \n\t" \ - "addi r24, r24, -24 \n\t" \ - "cmp r24, r24, r5 \n\t" \ - "beqi r24, 12 \n\t" \ - "lwi r3, r0, pulStatusAddr \n\t" \ - "sw r0, r0, r3 \n\t" \ - "addi r25, r25, -25 \n\t" \ - "cmp r25, r25, r5 \n\t" \ - "beqi r25, 12 \n\t" \ - "lwi r3, r0, pulStatusAddr \n\t" \ - "sw r0, r0, r3 \n\t" \ - "addi r26, r26, -26 \n\t" \ - "cmp r26, r26, r5 \n\t" \ - "beqi r26, 12 \n\t" \ - "lwi r3, r0, pulStatusAddr \n\t" \ - "sw r0, r0, r3 \n\t" \ - "addi r27, r27, -27 \n\t" \ - "cmp r27, r27, r5 \n\t" \ - "beqi r27, 12 \n\t" \ - "lwi r3, r0, pulStatusAddr \n\t" \ - "sw r0, r0, r3 \n\t" \ - "addi r28, r28, -28 \n\t" \ - "cmp r28, r28, r5 \n\t" \ - "beqi r28, 12 \n\t" \ - "lwi r3, r0, pulStatusAddr \n\t" \ - "sw r0, r0, r3 \n\t" \ - "addi r29, r29, -29 \n\t" \ - "cmp r29, r29, r5 \n\t" \ - "beqi r29, 12 \n\t" \ - "lwi r3, r0, pulStatusAddr \n\t" \ - "sw r0, r0, r3 \n\t" \ - "addi r30, r30, -30 \n\t" \ - "cmp r30, r30, r5 \n\t" \ - "beqi r30, 12 \n\t" \ - "lwi r3, r0, pulStatusAddr \n\t" \ - "sw r0, r0, r3 \n\t" \ - "addi r31, r31, -31 \n\t" \ - "cmp r31, r31, r5 \n\t" \ - "beqi r31, 12 \n\t" \ - "lwi r3, r0, pulStatusAddr \n\t" \ - "sw r0, r0, r3 \n\t" - ); - } -} - - - diff --git a/Demo/MicroBlaze/platgen.opt b/Demo/MicroBlaze/platgen.opt deleted file mode 100644 index 1a984fdb6..000000000 --- a/Demo/MicroBlaze/platgen.opt +++ /dev/null @@ -1,7 +0,0 @@ --p -xc4vfx12ff668-10 --lang -vhdl --st -xst -system.mhs diff --git a/Demo/MicroBlaze/serial/serial.c b/Demo/MicroBlaze/serial/serial.c deleted file mode 100644 index 30abdfa16..000000000 --- a/Demo/MicroBlaze/serial/serial.c +++ /dev/null @@ -1,195 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/* - BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART -*/ - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "queue.h" -#include "task.h" - -/* Demo application includes. */ -#include "serial.h" - -/* Microblaze driver includes. */ -#include "xuartlite_l.h" -#include "xintc_l.h" - -/*-----------------------------------------------------------*/ - -/* Queues used to hold received characters, and characters waiting to be -transmitted. */ -static xQueueHandle xRxedChars; -static xQueueHandle xCharsForTx; - -/*-----------------------------------------------------------*/ - -xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) -{ -unsigned portLONG ulControlReg, ulMask; - - /* NOTE: The baud rate used by this driver is determined by the hardware - parameterization of the UART Lite peripheral, and the baud value passed to - this function has no effect. */ - - /* Create the queues used to hold Rx and Tx characters. */ - xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); - xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); - - if( ( xRxedChars ) && ( xCharsForTx ) ) - { - /* Disable the interrupt. */ - XUartLite_mDisableIntr( XPAR_RS232_UART_BASEADDR ); - - /* Flush the fifos. */ - ulControlReg = XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_STATUS_REG_OFFSET ); - XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_CONTROL_REG_OFFSET, ulControlReg | XUL_CR_FIFO_TX_RESET | XUL_CR_FIFO_RX_RESET ); - - /* Enable the interrupt again. The interrupt controller has not yet been - initialised so there is no chance of receiving an interrupt until the - scheduler has been started. */ - XUartLite_mEnableIntr( XPAR_RS232_UART_BASEADDR ); - - /* Enable the interrupt in the interrupt controller while maintaining - all the other bit settings. */ - ulMask = XIntc_In32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ) ); - ulMask |= XPAR_RS232_UART_INTERRUPT_MASK; - XIntc_Out32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ), ( ulMask ) ); - XIntc_mAckIntr( XPAR_INTC_SINGLE_BASEADDR, 2 ); - } - - return ( xComPortHandle ) 0; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) -{ - /* The port handle is not required as this driver only supports one UART. */ - ( void ) pxPort; - - /* Get the next character from the buffer. Return false if no characters - are available, or arrive before xBlockTime expires. */ - if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) - { - return pdTRUE; - } - else - { - return pdFALSE; - } -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) -{ -portBASE_TYPE xReturn = pdTRUE; - - portENTER_CRITICAL(); - { - /* If the UART FIFO is full we can block posting the new data on the - Tx queue. */ - if( XUartLite_mIsTransmitFull( XPAR_RS232_UART_BASEADDR ) ) - { - if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) - { - xReturn = pdFAIL; - } - } - /* Otherwise, if there is data already in the queue we should add the - new data to the back of the queue to ensure the sequencing is - maintained. */ - else if( uxQueueMessagesWaiting( xCharsForTx ) ) - { - if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) - { - xReturn = pdFAIL; - } - } - /* If the UART FIFO is not full and there is no data already in the - queue we can write directly to the FIFO without disrupting the - sequence. */ - else - { - XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_TX_FIFO_OFFSET, cOutChar ); - } - } - portEXIT_CRITICAL(); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -void vSerialClose( xComPortHandle xPort ) -{ - /* Not supported as not required by the demo application. */ - ( void ) xPort; -} -/*-----------------------------------------------------------*/ - -void vSerialISR( void *pvBaseAddress ) -{ -unsigned portLONG ulISRStatus; -portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByRx = pdFALSE; -portCHAR cChar; - - /* Determine the cause of the interrupt. */ - ulISRStatus = XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_STATUS_REG_OFFSET ); - - if( ( ulISRStatus & ( XUL_SR_RX_FIFO_FULL | XUL_SR_RX_FIFO_VALID_DATA ) ) != 0 ) - { - /* A character is available - place it in the queue of received - characters. This might wake a task that was blocked waiting for - data. */ - cChar = ( portCHAR )XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_RX_FIFO_OFFSET ); - xTaskWokenByRx = xQueueSendFromISR( xRxedChars, &cChar, xTaskWokenByRx ); - } - - if( ( ulISRStatus & XUL_SR_TX_FIFO_EMPTY ) != 0 ) - { - /* There is space in the FIFO - if there are any characters queue for - transmission they can be send to the UART now. This might unblock a - task that was waiting for space to become available on the Tx queue. */ - if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE ) - { - XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_TX_FIFO_OFFSET, cChar ); - } - } - - /* If we woke any tasks we may require a context switch. */ - if( xTaskWokenByTx || xTaskWokenByRx ) - { - portYIELD_FROM_ISR(); - } -} diff --git a/Demo/MicroBlaze/system.bsb b/Demo/MicroBlaze/system.bsb deleted file mode 100644 index cc6c27827..000000000 --- a/Demo/MicroBlaze/system.bsb +++ /dev/null @@ -1 +0,0 @@ -„ćÄ®Ňôtt¦Ęč¬ĘäćŇŢÜ@Dn\b\dDvC„ćÄ®Ňôtt¦Ęč„ŢÂäČ@D°ŇŘŇÜđD@D¬ŇäčĘđ@h@šh`f@ŠěÂŘęÂčŇŢÜ@ ŘÂčĚŢäÚD@DbDv,„ćÄ®ŇôttŞŕČÂčĘŚ Ž‚@D‚¤†’¨Š†¨Ş¤ŠD@DěŇäčĘđhDv,„ćÄ®ŇôttŞŕČÂčĘŚ Ž‚@DŠ¬’†Šľ¦’´ŠD@DđĆhěĚđbdDv%„ćÄ®ŇôttŞŕČÂčĘŚ Ž‚@D ‚†–‚ŽŠD@DĚĚllpDv&„ćÄ®ŇôttŞŕČÂčĘŚ Ž‚@D¦ ŠŠŽ¤‚ŠD@DZb`Dv"„ćÄ®Ňôtt‚ČČ äŢĆĘććŢä@DÚŇĆäŢÄŘÂôĘDv=„ćÄ®ŇôttŞŕČÂčʆŢÚŕŢÜĘÜč@DÚŇĆäŢÄŘÂôĘD@D„ަľŚ¤Š˘D@Db``\``````Dv8„ćÄ®ŇôttŞŕČÂčʆŢÚŕŢÜĘÜč@DÚŇĆäŢÄŘÂôĘD@D†‚†ŠD@Dśž@†‚†ŠDvN„ćÄ®ŇôttŞŕČÂčʆŢÚŕŢÜĘÜč@DÚŇĆäŢÄŘÂôĘD@D†‚†Š’ś–@†žš žśŠś¨D@D¤ľ¦¤‚šľlhšđfdDv=„ćÄ®ŇôttŞŕČÂčʆŢÚŕŢÜĘÜč@DÚŇĆäŢÄŘÂôĘD@D†–ľŚ¤Š˘D@Db``\``````DvJ„ćÄ®ŇôttŞŕČÂčʆŢÚŕŢÜĘÜč@DÚŇĆäŢÄŘÂôĘD@DŠ„ŞŽľ’ŚD@DžÜZ†ĐŇŕ@®@ĘÄęÎ@šŢČęŘĘDv<„ćÄ®ŇôttŞŕČÂčʆŢÚŕŢÜĘÜč@DÚŇĆäŢÄŘÂôĘD@Dš„„¤‚š@¦’´ŠD@DljjflDv>„ćÄ®ŇôttŞŕČÂčʆŢÚŕŢÜĘÜč@DÚŇĆäŢÄŘÂôĘD@D ¤ž†ľŚ¤Š˘D@Db``\``````Dv8„ćÄ®ŇôttŞŕČÂčʆŢÚŕŢÜĘÜč@DÚŇĆäŢÄŘÂôĘD@D¤¦¨ľ ž‚¤’¨˛D@D`Dv2„ćÄ®Ňôtt‚ČČ ĘäŇŕĐĘäÂŘ@D¤¦dfdľŞÂäčD@DŢŕÄľęÂäčŘŇčĘDv9„ćÄ®ŇôttŞŕČÂčʆŢÚŕŢÜĘÜč@D¤¦dfdľŞÂäčD@D†ľ„‚ޤ‚¨ŠD@Drl``Dv7„ćÄ®ŇôttŞŕČÂčʆŢÚŕŢÜĘÜč@D¤¦dfdľŞÂäčD@D†ľ‚¨‚ľ„’¨¦D@DpDv8„ćÄ®ŇôttŞŕČÂčʆŢÚŕŢÜĘÜč@D¤¦dfdľŞÂäčD@D†ľžľ ‚¤’¨˛D@D`Dv8„ćÄ®ŇôttŞŕČÂčʆŢÚŕŢÜĘÜč@D¤¦dfdľŞÂäčD@D†ľŞ¦Šľ ‚¤’¨˛D@D`Dv<„ćÄ®ŇôttŞŕČÂčʆŢÚŕŢÜĘÜč@D¤¦dfdľŞÂäčD@D’ž¨˛ ŠD@D°’ľŞ‚¤¨ľ¬bDv<„ćÄ®ŇôttŞŕČÂčʆŢÚŕŢÜĘÜč@D¤¦dfdľŞÂäčD@DަŠľ’ś¨Š¤¤Ş ¨D@D¨¤ŞŠDv-„ćÄ®Ňôtt‚ČČ ĘäŇŕĐĘäÂŘ@DŠćľh„ŇčD@DŢŕÄľÎŕŇŢDv;„ćÄ®ŇôttŞŕČÂčʆŢÚŕŢÜĘÜč@DŠćľh„ŇčD@D’ž¨˛ ŠD@D°’ľŽ ’žľ¬bDv2„ćÄ®Ňôtt‚ČČ ĘäŇŕĐĘäÂŘ@DŠćľ ŢćŇčŇŢÜćD@DŢŕÄľÎŕŇŢDv@„ćÄ®ŇôttŞŕČÂčʆŢÚŕŢÜĘÜč@DŠćľ ŢćŇčŇŢÜćD@D’ž¨˛ ŠD@D°’ľŽ ’žľ¬bDv0„ćÄ®Ňôtt‚ČČ ĘäŇŕĐĘäÂŘ@DŢŕÄľčŇÚĘäľbD@DŢŕÄľčŇÚĘäDv;„ćÄ®ŇôttŞŕČÂčʆŢÚŕŢÜĘÜč@DŢŕÄľčŇÚĘäľbD@D†ľ†žŞś¨ľ®’¨D@DfdDv=„ćÄ®ŇôttŞŕČÂčʆŢÚŕŢÜĘÜč@DŢŕÄľčŇÚĘäľbD@D†ľžśŠľ¨’šŠ¤ľžś˛D@DbDv=„ćÄ®ŇôttŞŕČÂčʆŢÚŕŢÜĘÜč@DŢŕÄľčŇÚĘäľbD@DަŠľ’ś¨Š¤¤Ş ¨D@D¨¤ŞŠDv/„ćÄ®ŇôttŞŕČÂčʦ®@D¦®ľŽŠśŠ¤‚¨ŠľšŠš¨Š¦¨D@DŚ‚¦ŠDv1„ćÄ®ŇôttŞŕČÂčʦ®@D¦®ľŽŠśŠ¤‚¨Šľ Š¤’ ¨Š¦¨D@D¨¤ŞŠDv#„ćÄ®ŇôttŞŕČÂčʦ®@D¦®ľ¦¨’śD@DśŢÜĘDv$„ćÄ®ŇôttŞŕČÂčʦ®@D¦®ľ¦¨žŞ¨D@DśŢÜĘDvA„ćÄ®ŇôttŞŕČÂčʦ®@D¦®ľ‚¨‚ľ’ś¦D@DČŘÚÄľĆÜčŘäD@D¨Ęćč‚ŕŕľ ĘäŇŕĐĘäÂŘDvA„ćÄ®ŇôttŞŕČÂčʦ®@D¦®ľ‚¨‚ľ ‚¤D@D†ľ„‚¦Š‚¤D@D¨Ęćč‚ŕŕľ ĘäŇŕĐĘäÂŘDvD„ćÄ®ŇôttŞŕČÂčʦ®@D¦®ľ ¤žŽ¤‚šľ’ś¦D@DŇŘÚÄľĆÜčŘäD@D¨Ęćč‚ŕŕľ ĘäŇŕĐĘäÂŘDvD„ćÄ®ŇôttŞŕČÂčʦ®@D¦®ľ ¤žŽ¤‚šľ ‚¤D@D†ľ„‚¦Š‚¤D@D¨Ęćč‚ŕŕľ ĘäŇŕĐĘäÂŘDvB„ćÄ®ŇôttŞŕČÂčʦ®@D¦®ľ¦¨‚†–ľ’ś¦D@DČŘÚÄľĆÜčŘäD@D¨Ęćč‚ŕŕľ ĘäŇŕĐĘäÂŘDvB„ćÄ®ŇôttŞŕČÂčʦ®@D¦®ľ¦¨‚†–ľ ‚¤D@D†ľ„‚¦Š‚¤D@D¨Ęćč‚ŕŕľ ĘäŇŕĐĘäÂŘDv \ No newline at end of file diff --git a/Demo/MicroBlaze/system.make b/Demo/MicroBlaze/system.make deleted file mode 100644 index 143cd8096..000000000 --- a/Demo/MicroBlaze/system.make +++ /dev/null @@ -1,258 +0,0 @@ -################################################################# -# Makefile generated by Xilinx Platform Studio -# Project:E:\Dev\FreeRTOS\Demo\MicroBlaze\system.xmp -################################################################# - -# Name of the Microprocessor system -# The hardware specification of the system is in file : -# E:\Dev\FreeRTOS\Demo\MicroBlaze\system.mhs -# The software specification of the system is in file : -# E:\Dev\FreeRTOS\Demo\MicroBlaze\system.mss - -include system_incl.make - - -################################################################# -# EXTERNAL TARGETS -################################################################# -all: - @echo "Makefile to build a Microprocessor system :" - @echo "Run make with any of the following targets" - @echo " " - @echo " netlist : Generates the netlist for the given MHS " - @echo " bits : Runs Implementation tools to generate the bitstream" - @echo " exporttopn:Export to ProjNav" - @echo " " - @echo " libs : Configures the sw libraries for this system" - @echo " program : Compiles the program sources for all the processor instances" - @echo " " - @echo " init_bram: Initializes bitstream with BRAM data" - @echo " ace : Generate ace file from bitstream and elf" - @echo " download : Downloads the bitstream onto the board" - @echo " " - @echo " sim : Generates HDL simulation models and runs simulator for chosen simulation mode" - @echo " simmodel : Generates HDL simulation models for chosen simulation mode" - @echo " behavioral_model:Generates behavioral HDL models with BRAM initialization" - @echo " structural_model:Generates structural simulation HDL models with BRAM initialization" - @echo " timing_model : Generates timing simulation HDL models with BRAM initialization" - @echo " vp : Generates virtual platform model" - @echo " " - @echo " netlistclean: Deletes netlist" - @echo " bitsclean: Deletes bit, ncd, bmm files" - @echo " hwclean : Deletes implementation dir" - @echo " libsclean: Deletes sw libraries" - @echo " programclean: Deletes compiled ELF files" - @echo " swclean : Deletes sw libraries and ELF files" - @echo " simclean : Deletes simulation dir" - @echo " vpclean : Deletes virtualplatform dir" - @echo " clean : Deletes all generated files/directories" - @echo " " - @echo " make : (Default)" - @echo " Creates a Microprocessor system using default initializations" - @echo " specified for each processor in MSS file" - - -bits: $(SYSTEM_BIT) - -ace: $(SYSTEM_ACE) - -netlist: $(POSTSYN_NETLIST) - -libs: $(LIBRARIES) - -program: $(ALL_USER_ELF_FILES) - -download: $(DOWNLOAD_BIT) dummy - @echo "*********************************************" - @echo "Downloading Bitstream onto the target board" - @echo "*********************************************" - impact -batch etc/download.cmd - -init_bram: $(DOWNLOAD_BIT) - -sim: $(DEFAULT_SIM_SCRIPT) - cd simulation/behavioral; \ - $(SIM_CMD) & - -simmodel: $(DEFAULT_SIM_SCRIPT) - -behavioral_model: $(BEHAVIORAL_SIM_SCRIPT) - -structural_model: $(STRUCTURAL_SIM_SCRIPT) - -timing_model: $(TIMING_SIM_SCRIPT) - -vp: $(VPEXEC) - -clean: hwclean libsclean programclean simclean vpclean - rm -f _impact.cmd - -hwclean: netlistclean bitsclean - rm -rf implementation synthesis xst hdl - rm -rf xst.srp $(SYSTEM).srp - -netlistclean: - rm -f $(POSTSYN_NETLIST) - rm -f $(BMM_FILE) - -bitsclean: - rm -f $(SYSTEM_BIT) - rm -f implementation/$(SYSTEM).ncd - rm -f implementation/$(SYSTEM)_bd.bmm - -bitsclean: - -simclean: - rm -rf simulation/behavioral - -swclean: libsclean programclean - @echo "" - -libsclean: $(LIBSCLEAN_TARGETS) - -programclean: $(PROGRAMCLEAN_TARGETS) - -vpclean: - rm -rf virtualplatform - -################################################################# -# SOFTWARE PLATFORM FLOW -################################################################# - - -$(LIBRARIES): $(MHSFILE) $(MSSFILE) __xps/libgen.opt - @echo "*********************************************" - @echo "Creating software libraries..." - @echo "*********************************************" - libgen $(LIBGEN_OPTIONS) $(MSSFILE) - - -microblaze_0_libsclean: - rm -rf microblaze_0/lib/ - -$(MICROBLAZE_0_XMDSTUB): $(LIBRARIES) - -################################################################# -# SOFTWARE APPLICATION RTOSDEMO -################################################################# - -RTOSDemo_program: $(RTOSDEMO_OUTPUT) - -$(RTOSDEMO_OUTPUT) : $(RTOSDEMO_SOURCES) $(RTOSDEMO_HEADERS) $(RTOSDEMO_LINKER_SCRIPT) \ - $(LIBRARIES) __xps/rtosdemo_compiler.opt - @mkdir -p $(RTOSDEMO_OUTPUT_DIR) - $(RTOSDEMO_CC) $(RTOSDEMO_CC_OPT) $(RTOSDEMO_SOURCES) -o $(RTOSDEMO_OUTPUT) \ - $(RTOSDEMO_OTHER_CC_FLAGS) $(RTOSDEMO_INCLUDES) $(RTOSDEMO_LIBPATH) \ - -xl-mode-$(RTOSDEMO_MODE) \ - $(RTOSDEMO_CFLAGS) $(RTOSDEMO_LFLAGS) - $(RTOSDEMO_CC_SIZE) $(RTOSDEMO_OUTPUT) - -RTOSDemo_programclean: - rm -f $(RTOSDEMO_OUTPUT) - -################################################################# -# BOOTLOOP ELF FILES -################################################################# - - - -$(MICROBLAZE_0_BOOTLOOP): $(MICROBLAZE_BOOTLOOP) - @mkdir -p $(BOOTLOOP_DIR) - cp -f $(MICROBLAZE_BOOTLOOP) $(MICROBLAZE_0_BOOTLOOP) - -################################################################# -# HARDWARE IMPLEMENTATION FLOW -################################################################# - - -$(BMM_FILE) \ -$(WRAPPER_NGC_FILES): $(MHSFILE) __xps/platgen.opt \ - $(CORE_STATE_DEVELOPMENT_FILES) - @echo "****************************************************" - @echo "Creating system netlist for hardware specification.." - @echo "****************************************************" - platgen $(PLATGEN_OPTIONS) -st xst $(MHSFILE) - -$(POSTSYN_NETLIST): $(WRAPPER_NGC_FILES) - @echo "Running synthesis..." - bash -c "cd synthesis; ./synthesis.sh; cd .." - -$(SYSTEM_BIT): $(BMM_FILE) $(POSTSYN_NETLIST) __xps/xpsxflow.opt \ - $(UCF_FILE) $(BITGEN_UT_FILE) $(FASTRUNTIME_OPT_FILE) - @echo "Copying Xilinx Implementation tool scripts.." - @cp -f $(BITGEN_UT_FILE) implementation/bitgen.ut - @cp -f $(FASTRUNTIME_OPT_FILE) implementation/fast_runtime.opt - @cp -f $(UCF_FILE) implementation/$(SYSTEM).ucf - @echo "*********************************************" - @echo "Running Xilinx Implementation tools.." - @echo "*********************************************" - xflow -wd implementation -p $(DEVICE) -implement fast_runtime.opt $(SYSTEM).ngc - cd implementation; bitgen -w -f bitgen.ut $(SYSTEM) - -exporttopn: - @echo "You have chosen XPS for implementation tool flow." - @echo "Please select ProjNav as your implementation flow in Project Options." - @echo "In batch mode, use commad xset pnproj ." - -$(DOWNLOAD_BIT): $(SYSTEM_BIT) $(BRAMINIT_ELF_FILES) __xps/bitinit.opt - @cp -f implementation/$(SYSTEM)_bd.bmm . - @echo "*********************************************" - @echo "Initializing BRAM contents of the bitstream" - @echo "*********************************************" - bitinit $(MHSFILE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_FILE_ARGS) \ - -bt $(SYSTEM_BIT) -o $(DOWNLOAD_BIT) - @rm -f $(SYSTEM)_bd.bmm - -$(SYSTEM_ACE): $(DOWNLOAD_BIT) $(RTOSDEMO_OUTPUT) - @echo "*********************************************" - @echo "Creating system ace file" - @echo "*********************************************" - xmd -tcl genace.tcl -jprog -hw $(DOWNLOAD_BIT) -elf $(RTOSDEMO_OUTPUT) -ace $(SYSTEM_ACE) - -################################################################# -# SIMULATION FLOW -################################################################# - - -################## BEHAVIORAL SIMULATION ################## - -$(BEHAVIORAL_SIM_SCRIPT): $(MHSFILE) __xps/simgen.opt \ - $(BRAMINIT_ELF_FILES) - @echo "*********************************************" - @echo "Creating behavioral simulation models..." - @echo "*********************************************" - simgen $(SIMGEN_OPTIONS) -m behavioral $(MHSFILE) - -################## STRUCTURAL SIMULATION ################## - -$(STRUCTURAL_SIM_SCRIPT): $(WRAPPER_NGC_FILES) __xps/simgen.opt \ - $(BRAMINIT_ELF_FILES) - @echo "*********************************************" - @echo "Creating structural simulation models..." - @echo "*********************************************" - simgen $(SIMGEN_OPTIONS) -sd implementation -m structural $(MHSFILE) - - -################## TIMING SIMULATION ################## - -$(TIMING_SIM_SCRIPT): $(SYSTEM_BIT) __xps/simgen.opt \ - $(BRAMINIT_ELF_FILES) - @echo "*********************************************" - @echo "Creating timing simulation models..." - @echo "*********************************************" - simgen $(SIMGEN_OPTIONS) -sd implementation -m timing $(MHSFILE) - -################################################################# -# VIRTUAL PLATFORM FLOW -################################################################# - - -$(VPEXEC): $(MHSFILE) __xps/vpgen.opt - @echo "****************************************************" - @echo "Creating virtual platform for hardware specification.." - @echo "****************************************************" - vpgen $(VPGEN_OPTIONS) $(MHSFILE) - -dummy: - @echo "" - diff --git a/Demo/MicroBlaze/system.mhs b/Demo/MicroBlaze/system.mhs deleted file mode 100644 index 2999abcea..000000000 --- a/Demo/MicroBlaze/system.mhs +++ /dev/null @@ -1,196 +0,0 @@ -# ############################################################################## -# Created by Base System Builder Wizard for Xilinx EDK 7.1.2 Build EDK_H.12.5.1 -# Sun Nov 13 16:46:19 2005 -# Target Board: Xilinx Virtex 4 ML403 Evaluation Platform Rev 1 -# Family: virtex4 -# Device: xc4vfx12 -# Package: ff668 -# Speed Grade: -10 -# Processor: Microblaze -# System clock frequency: 100.000000 MHz -# Debug interface: On-Chip HW Debug Module -# On Chip Memory : 64 KB -# ############################################################################## - - - PARAMETER VERSION = 2.1.0 - - - PORT fpga_0_RS232_Uart_RX_pin = fpga_0_RS232_Uart_RX, DIR = INPUT - PORT fpga_0_RS232_Uart_TX_pin = fpga_0_RS232_Uart_TX, DIR = OUTPUT - PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO, DIR = INOUT, VEC = [0:3] - PORT fpga_0_LEDs_Positions_GPIO_IO_pin = fpga_0_LEDs_Positions_GPIO_IO, DIR = INOUT, VEC = [0:4] - PORT sys_clk_pin = dcm_clk_s, DIR = INPUT, SIGIS = DCMCLK - PORT sys_rst_pin = sys_rst_s, DIR = INPUT - - -BEGIN microblaze - PARAMETER INSTANCE = microblaze_0 - PARAMETER HW_VER = 4.00.a - PARAMETER C_DEBUG_ENABLED = 1 - PARAMETER C_NUMBER_OF_PC_BRK = 2 - PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1 - PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1 - BUS_INTERFACE DLMB = dlmb - BUS_INTERFACE ILMB = ilmb - BUS_INTERFACE DOPB = mb_opb - BUS_INTERFACE IOPB = mb_opb - PORT CLK = sys_clk_s - PORT DBG_CAPTURE = DBG_CAPTURE_s - PORT DBG_CLK = DBG_CLK_s - PORT DBG_REG_EN = DBG_REG_EN_s - PORT DBG_TDI = DBG_TDI_s - PORT DBG_TDO = DBG_TDO_s - PORT DBG_UPDATE = DBG_UPDATE_s - PORT Interrupt = Interrupt -END - -BEGIN opb_v20 - PARAMETER INSTANCE = mb_opb - PARAMETER HW_VER = 1.10.c - PARAMETER C_EXT_RESET_HIGH = 0 - PORT SYS_Rst = sys_rst_s - PORT OPB_Clk = sys_clk_s -END - -BEGIN opb_mdm - PARAMETER INSTANCE = debug_module - PARAMETER HW_VER = 2.00.a - PARAMETER C_MB_DBG_PORTS = 1 - PARAMETER C_USE_UART = 1 - PARAMETER C_UART_WIDTH = 8 - PARAMETER C_BASEADDR = 0x41400000 - PARAMETER C_HIGHADDR = 0x4140ffff - BUS_INTERFACE SOPB = mb_opb - PORT OPB_Clk = sys_clk_s - PORT DBG_CAPTURE_0 = DBG_CAPTURE_s - PORT DBG_CLK_0 = DBG_CLK_s - PORT DBG_REG_EN_0 = DBG_REG_EN_s - PORT DBG_TDI_0 = DBG_TDI_s - PORT DBG_TDO_0 = DBG_TDO_s - PORT DBG_UPDATE_0 = DBG_UPDATE_s -END - -BEGIN lmb_v10 - PARAMETER INSTANCE = ilmb - PARAMETER HW_VER = 1.00.a - PARAMETER C_EXT_RESET_HIGH = 0 - PORT SYS_Rst = sys_rst_s - PORT LMB_Clk = sys_clk_s -END - -BEGIN lmb_v10 - PARAMETER INSTANCE = dlmb - PARAMETER HW_VER = 1.00.a - PARAMETER C_EXT_RESET_HIGH = 0 - PORT SYS_Rst = sys_rst_s - PORT LMB_Clk = sys_clk_s -END - -BEGIN lmb_bram_if_cntlr - PARAMETER INSTANCE = dlmb_cntlr - PARAMETER HW_VER = 1.00.b - PARAMETER C_BASEADDR = 0x00000000 - PARAMETER C_HIGHADDR = 0x0000ffff - BUS_INTERFACE SLMB = dlmb - BUS_INTERFACE BRAM_PORT = dlmb_port -END - -BEGIN lmb_bram_if_cntlr - PARAMETER INSTANCE = ilmb_cntlr - PARAMETER HW_VER = 1.00.b - PARAMETER C_BASEADDR = 0x00000000 - PARAMETER C_HIGHADDR = 0x0000ffff - BUS_INTERFACE SLMB = ilmb - BUS_INTERFACE BRAM_PORT = ilmb_port -END - -BEGIN bram_block - PARAMETER INSTANCE = lmb_bram - PARAMETER HW_VER = 1.00.a - BUS_INTERFACE PORTA = ilmb_port - BUS_INTERFACE PORTB = dlmb_port -END - -BEGIN opb_uartlite - PARAMETER INSTANCE = RS232_Uart - PARAMETER HW_VER = 1.00.b - PARAMETER C_BAUDRATE = 9600 - PARAMETER C_DATA_BITS = 8 - PARAMETER C_ODD_PARITY = 0 - PARAMETER C_USE_PARITY = 0 - PARAMETER C_CLK_FREQ = 100000000 - PARAMETER C_BASEADDR = 0x40600000 - PARAMETER C_HIGHADDR = 0x4060ffff - BUS_INTERFACE SOPB = mb_opb - PORT OPB_Clk = sys_clk_s - PORT Interrupt = RS232_Uart_Interrupt - PORT RX = fpga_0_RS232_Uart_RX - PORT TX = fpga_0_RS232_Uart_TX -END - -BEGIN opb_gpio - PARAMETER INSTANCE = LEDs_4Bit - PARAMETER HW_VER = 3.01.b - PARAMETER C_GPIO_WIDTH = 4 - PARAMETER C_IS_DUAL = 0 - PARAMETER C_IS_BIDIR = 1 - PARAMETER C_ALL_INPUTS = 0 - PARAMETER C_BASEADDR = 0x40020000 - PARAMETER C_HIGHADDR = 0x4002ffff - BUS_INTERFACE SOPB = mb_opb - PORT OPB_Clk = sys_clk_s - PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO -END - -BEGIN opb_gpio - PARAMETER INSTANCE = LEDs_Positions - PARAMETER HW_VER = 3.01.b - PARAMETER C_GPIO_WIDTH = 5 - PARAMETER C_IS_DUAL = 0 - PARAMETER C_IS_BIDIR = 1 - PARAMETER C_ALL_INPUTS = 0 - PARAMETER C_BASEADDR = 0x40000000 - PARAMETER C_HIGHADDR = 0x4000ffff - BUS_INTERFACE SOPB = mb_opb - PORT OPB_Clk = sys_clk_s - PORT GPIO_IO = fpga_0_LEDs_Positions_GPIO_IO -END - -BEGIN opb_timer - PARAMETER INSTANCE = opb_timer_1 - PARAMETER HW_VER = 1.00.b - PARAMETER C_COUNT_WIDTH = 32 - PARAMETER C_ONE_TIMER_ONLY = 1 - PARAMETER C_BASEADDR = 0x41c00000 - PARAMETER C_HIGHADDR = 0x41c0ffff - BUS_INTERFACE SOPB = mb_opb - PORT OPB_Clk = sys_clk_s - PORT Interrupt = opb_timer_1_Interrupt -END - -BEGIN opb_intc - PARAMETER INSTANCE = opb_intc_0 - PARAMETER HW_VER = 1.00.c - PARAMETER C_BASEADDR = 0x41200000 - PARAMETER C_HIGHADDR = 0x4120ffff - PARAMETER C_HAS_IPR = 0 - BUS_INTERFACE SOPB = mb_opb - PORT Irq = Interrupt - PORT Intr = RS232_Uart_Interrupt & opb_timer_1_Interrupt -END - -BEGIN dcm_module - PARAMETER INSTANCE = dcm_0 - PARAMETER HW_VER = 1.00.a - PARAMETER C_CLK0_BUF = TRUE - PARAMETER C_CLKIN_PERIOD = 10.000000 - PARAMETER C_CLK_FEEDBACK = 1X - PARAMETER C_EXT_RESET_HIGH = 1 - PORT CLKIN = dcm_clk_s - PORT CLK0 = sys_clk_s - PORT CLKFB = sys_clk_s - PORT RST = net_gnd - PORT LOCKED = dcm_0_lock -END - diff --git a/Demo/MicroBlaze/system.mss b/Demo/MicroBlaze/system.mss deleted file mode 100644 index 6c13869ca..000000000 --- a/Demo/MicroBlaze/system.mss +++ /dev/null @@ -1,84 +0,0 @@ - - PARAMETER VERSION = 2.2.0 - - -BEGIN OS - PARAMETER OS_NAME = standalone - PARAMETER OS_VER = 1.00.a - PARAMETER PROC_INSTANCE = microblaze_0 -END - - -BEGIN PROCESSOR - PARAMETER DRIVER_NAME = cpu - PARAMETER DRIVER_VER = 1.00.a - PARAMETER HW_INSTANCE = microblaze_0 - PARAMETER COMPILER = mb-gcc - PARAMETER ARCHIVER = mb-ar - PARAMETER XMDSTUB_PERIPHERAL = debug_module -END - - -BEGIN DRIVER - PARAMETER DRIVER_NAME = opbarb - PARAMETER DRIVER_VER = 1.02.a - PARAMETER HW_INSTANCE = mb_opb -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = uartlite - PARAMETER DRIVER_VER = 1.00.b - PARAMETER HW_INSTANCE = debug_module -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = bram - PARAMETER DRIVER_VER = 1.00.a - PARAMETER HW_INSTANCE = dlmb_cntlr -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = bram - PARAMETER DRIVER_VER = 1.00.a - PARAMETER HW_INSTANCE = ilmb_cntlr -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = uartlite - PARAMETER DRIVER_VER = 1.00.b - PARAMETER HW_INSTANCE = RS232_Uart - PARAMETER int_handler = vSerialISR, int_port = Interrupt -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = gpio - PARAMETER DRIVER_VER = 2.00.a - PARAMETER HW_INSTANCE = LEDs_4Bit -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = gpio - PARAMETER DRIVER_VER = 2.00.a - PARAMETER HW_INSTANCE = LEDs_Positions -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = tmrctr - PARAMETER DRIVER_VER = 1.00.b - PARAMETER HW_INSTANCE = opb_timer_1 - PARAMETER int_handler = vTickISR, int_port = Interrupt -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = intc - PARAMETER DRIVER_VER = 1.00.c - PARAMETER HW_INSTANCE = opb_intc_0 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 1.00.a - PARAMETER HW_INSTANCE = dcm_0 -END - - diff --git a/Demo/MicroBlaze/system.xmp b/Demo/MicroBlaze/system.xmp deleted file mode 100644 index c899fd9b5..000000000 --- a/Demo/MicroBlaze/system.xmp +++ /dev/null @@ -1,66 +0,0 @@ -#Please do not modify this file by hand -XmpVersion: 7.1 -IntStyle: default -MHS File: system.mhs -MSS File: system.mss -NPL File: projnav/system.ise -Architecture: virtex4 -Device: xc4vfx12 -Package: ff668 -SpeedGrade: -10 -UseProjNav: 0 -AddToNPL: 0 -PNImportBitFile: -PNImportBmmFile: -UserCmd1: -UserCmd1Type: 0 -UserCmd2: -UserCmd2Type: 0 -SynProj: xst -ReloadPbde: 0 -MainMhsEditor: 0 -InsertNoPads: 0 -HdlLang: VHDL -Simulator: mti -SimModel: BEHAVIORAL -SimXLib: -SimEdkLib: -MixLangSim: 1 -UcfFile: data/system.ucf -Processor: microblaze_0 -BootLoop: 0 -XmdStub: 0 -SwProj: RTOSDemo -Processor: microblaze_0 -Executable: RTOSDemo/executable.elf -Source: main.c -Source: ParTest/ParTest.c -Source: ../../Source/tasks.c -Source: ../../Source/queue.c -Source: ../../Source/list.c -Source: ../../Source/portable/MemMang/heap_1.c -Source: ../../Source/portable/GCC/MicroBlaze/port.c -Source: ../../Source/portable/GCC/MicroBlaze/portasm.s -Source: ../Common/Minimal/flash.c -Source: serial/serial.c -Source: ../Common/Minimal/comtest.c -Source: ../Common/Minimal/integer.c -Source: ../Common/Minimal/semtest.c -Source: ../Common/Minimal/dynamic.c -Source: ../Common/Minimal/PollQ.c -Source: ../Common/Minimal/BlockQ.c -Header: FreeRTOSConfig.h -DefaultInit: EXECUTABLE -InitBram: 1 -Active: 1 -CompilerOptLevel: 4 -GlobPtrOpt: 0 -DebugSym: 1 -SearchIncl: . ../Common/include ../../Source/include ../../Source/portable/GCC/MicroBlaze -AsmOpt: -LinkOpt: -Map=rtosdemo.map -ProgStart: -StackSize: -HeapSize: -LinkerScript: -ProgCCFlags: -D MICROBLAZE_GCC -Wall diff --git a/Demo/MicroBlaze/system_incl.make b/Demo/MicroBlaze/system_incl.make deleted file mode 100644 index 9973ee322..000000000 --- a/Demo/MicroBlaze/system_incl.make +++ /dev/null @@ -1,134 +0,0 @@ -################################################################# -# Makefile generated by Xilinx Platform Studio -# Project:E:\Dev\FreeRTOS\Demo\MicroBlaze\system.xmp -################################################################# - -XILINX_EDK_DIR = C:/devtools/xilinx/EDK - -SYSTEM = system - -MHSFILE = system.mhs - -MSSFILE = system.mss - -FPGA_ARCH = virtex4 - -DEVICE = xc4vfx12ff668-10 - -LANGUAGE = vhdl - -SEARCHPATHOPT = - -SUBMODULE_OPT = - -PLATGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(SUBMODULE_OPT) - -LIBGEN_OPTIONS = -mhs $(MHSFILE) -p $(DEVICE) $(SEARCHPATHOPT) \ - $(MICROBLAZE_0_LIBG_OPT) - -VPGEN_OPTIONS = -p $(DEVICE) $(SEARCHPATHOPT) - -RTOSDEMO_OUTPUT_DIR = RTOSDemo -RTOSDEMO_OUTPUT = $(RTOSDEMO_OUTPUT_DIR)/executable.elf - -MICROBLAZE_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/microblaze/mb_bootloop.elf -PPC405_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc405/ppc_bootloop.elf -BOOTLOOP_DIR = bootloops - -MICROBLAZE_0_BOOTLOOP = $(BOOTLOOP_DIR)/microblaze_0.elf -MICROBLAZE_0_XMDSTUB = microblaze_0/code/xmdstub.elf - -BRAMINIT_ELF_FILES = $(RTOSDEMO_OUTPUT) -BRAMINIT_ELF_FILE_ARGS = -pe microblaze_0 $(RTOSDEMO_OUTPUT) - -ALL_USER_ELF_FILES = $(RTOSDEMO_OUTPUT) - -SIM_CMD = vsim - -BEHAVIORAL_SIM_SCRIPT = simulation/behavioral/$(SYSTEM).do - -STRUCTURAL_SIM_SCRIPT = simulation/structural/$(SYSTEM).do - -TIMING_SIM_SCRIPT = simulation/timing/$(SYSTEM).do - -DEFAULT_SIM_SCRIPT = $(BEHAVIORAL_SIM_SCRIPT) - -MIX_LANG_SIM_OPT = -mixed yes - -SIMGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(SUBMODULE_OPT) $(BRAMINIT_ELF_FILE_ARGS) $(MIX_LANG_SIM_OPT) -s mti - -MICROBLAZE_0_XMDSTUB = microblaze_0/code/xmdstub.elf - -LIBRARIES = \ - microblaze_0/lib/libxil.a -VPEXEC = virtualplatform/vpexec.exe - -LIBSCLEAN_TARGETS = microblaze_0_libsclean - -PROGRAMCLEAN_TARGETS = RTOSDemo_programclean - -CORE_STATE_DEVELOPMENT_FILES = - -WRAPPER_NGC_FILES = implementation/microblaze_0_wrapper.ngc \ -implementation/mb_opb_wrapper.ngc \ -implementation/debug_module_wrapper.ngc \ -implementation/ilmb_wrapper.ngc \ -implementation/dlmb_wrapper.ngc \ -implementation/dlmb_cntlr_wrapper.ngc \ -implementation/ilmb_cntlr_wrapper.ngc \ -implementation/lmb_bram_wrapper.ngc \ -implementation/rs232_uart_wrapper.ngc \ -implementation/leds_4bit_wrapper.ngc \ -implementation/leds_positions_wrapper.ngc \ -implementation/opb_timer_1_wrapper.ngc \ -implementation/opb_intc_0_wrapper.ngc \ -implementation/dcm_0_wrapper.ngc - -POSTSYN_NETLIST = implementation/$(SYSTEM).ngc - -SYSTEM_BIT = implementation/$(SYSTEM).bit - -DOWNLOAD_BIT = implementation/download.bit - -SYSTEM_ACE = implementation/$(SYSTEM).ace - -UCF_FILE = data/system.ucf - -BMM_FILE = implementation/$(SYSTEM).bmm - -FASTRUNTIME_OPT_FILE = etc/fast_runtime.opt -BITGEN_UT_FILE = etc/bitgen.ut - -################################################################# -# SOFTWARE APPLICATION RTOSDEMO -################################################################# - -RTOSDEMO_SOURCES = main.c ParTest/ParTest.c ../../Source/tasks.c ../../Source/queue.c ../../Source/list.c ../../Source/portable/MemMang/heap_1.c ../../Source/portable/GCC/MicroBlaze/port.c ../../Source/portable/GCC/MicroBlaze/portasm.s ../Common/Minimal/flash.c serial/serial.c ../Common/Minimal/comtest.c ../Common/Minimal/integer.c ../Common/Minimal/semtest.c ../Common/Minimal/dynamic.c ../Common/Minimal/PollQ.c ../Common/Minimal/BlockQ.c - -RTOSDEMO_HEADERS = FreeRTOSConfig.h - -RTOSDEMO_CC = mb-gcc -RTOSDEMO_CC_SIZE = mb-size -RTOSDEMO_CC_OPT = -Os -RTOSDEMO_CFLAGS = -D MICROBLAZE_GCC -Wall -RTOSDEMO_CC_SEARCH = # -B -RTOSDEMO_LIBPATH = -L./microblaze_0/lib/ # -L -RTOSDEMO_INCLUDES = -I./microblaze_0/include/ -IDev/FreeRTOS/Demo/MicroBlaze/ -I. -I../Common/include -I../../Source/include -I../../Source/portable/GCC/MicroBlaze -RTOSDEMO_LFLAGS = # -l -RTOSDEMO_CC_PREPROC_FLAG = # -Wp, -RTOSDEMO_CC_ASM_FLAG = # -Wa, -RTOSDEMO_CC_LINKER_FLAG = -Wl,-Map=rtosdemo.map -RTOSDEMO_LINKER_SCRIPT = -RTOSDEMO_LINKER_SCRIPT_FLAG = #-Wl,-T -Wl,$(RTOSDEMO_LINKER_SCRIPT) -RTOSDEMO_CC_DEBUG_FLAG = -g -RTOSDEMO_CC_GLOBPTR_FLAG= # -mxl-gp-opt -RTOSDEMO_MODE = executable -RTOSDEMO_LIBG_OPT = -$(RTOSDEMO_MODE) microblaze_0 -RTOSDEMO_CC_SOFTMUL_FLAG= -mno-xl-soft-mul -RTOSDEMO_CC_START_ADDR_FLAG= # -Wl,-defsym -Wl,_TEXT_START_ADDR= -RTOSDEMO_CC_STACK_SIZE_FLAG= # -Wl,-defsym -Wl,_STACK_SIZE= -RTOSDEMO_OTHER_CC_FLAGS= $(RTOSDEMO_CC_GLOBPTR_FLAG) \ - $(RTOSDEMO_CC_START_ADDR_FLAG) $(RTOSDEMO_CC_STACK_SIZE_FLAG) \ - $(RTOSDEMO_CC_SOFTMUL_FLAG) \ - $(RTOSDEMO_CC_PREPROC_FLAG) $(RTOSDEMO_CC_ASM_FLAG) $(RTOSDEMO_CC_LINKER_FLAG) \ - $(RTOSDEMO_LINKER_SCRIPT_FLAG) $(RTOSDEMO_CC_DEBUG_FLAG) diff --git a/Demo/PC/FRConfig.h b/Demo/PC/FRConfig.h deleted file mode 100644 index c7930b3a3..000000000 --- a/Demo/PC/FRConfig.h +++ /dev/null @@ -1,84 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -#include - -/*----------------------------------------------------------- - * Application specific definitions for the x86 port. - *----------------------------------------------------------*/ - -/* These are the only definitions that can be modified!. */ -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 1 -#define configUSE_TICK_HOOK 1 -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 ) /* This can be made smaller if required. */ -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 32 * 1024 ) ) -#define configMAX_TASK_NAME_LEN ( 16 ) -#define configUSE_TRACE_FACILITY 0 -#define configUSE_16_BIT_TICKS 1 -#define configIDLE_SHOULD_YIELD 1 -#define configUSE_CO_ROUTINES 1 - -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 10 ) -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - - -/* The maximum number of characters a task name can take, -including the null terminator. */ -#define configMAX_TASK_NAME_LEN ( 16 ) - -/* Set the following definitions to 1 to include the component, or zero -to exclude the component. */ - -/* Include/exclude the stated API function. */ -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 1 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 - - -/* - * The tick count (and times defined in tick count units) can be either a 16bit - * or a 32 bit value. See documentation on http://www.FreeRTOS.org to decide - * which to use. - */ -#define configUSE_16_BIT_TICKS 1 - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/PC/FileIO/fileIO.c b/Demo/PC/FileIO/fileIO.c deleted file mode 100644 index 69e1af33e..000000000 --- a/Demo/PC/FileIO/fileIO.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#include -#include - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Demo program include files. */ -#include "fileio.h" - -void vDisplayMessage( const portCHAR * const pcMessageToPrint ) -{ - taskENTER_CRITICAL(); - printf( "%s", pcMessageToPrint ); - fflush( stdout ); - taskEXIT_CRITICAL(); -} -/*-----------------------------------------------------------*/ - -void vWriteMessageToDisk( const portCHAR * const pcMessage ) -{ -const portCHAR * const pcFileName = "a:\\RTOSlog.txt"; -const portCHAR * const pcSeparator = "\r\n-----------------------\r\n"; -FILE *pf; - - taskENTER_CRITICAL(); - { - pf = fopen( pcFileName, "a" ); - if( pf != NULL ) - { - fwrite( pcMessage, strlen( pcMessage ), ( unsigned portSHORT ) 1, pf ); - fwrite( pcSeparator, strlen( pcSeparator ), ( unsigned portSHORT ) 1, pf ); - fclose( pf ); - } - } - taskEXIT_CRITICAL(); -} -/*-----------------------------------------------------------*/ - -void vWriteBufferToDisk( const portCHAR * const pcBuffer, unsigned portLONG ulBufferLength ) -{ -const portCHAR * const pcFileName = "a:\\trace.bin"; -FILE *pf; - - taskENTER_CRITICAL(); - { - pf = fopen( pcFileName, "wb" ); - if( pf ) - { - fwrite( pcBuffer, ( size_t ) ulBufferLength, ( unsigned portSHORT ) 1, pf ); - fclose( pf ); - } - } - taskEXIT_CRITICAL(); -} - diff --git a/Demo/PC/FreeRTOSConfig.h b/Demo/PC/FreeRTOSConfig.h deleted file mode 100644 index e36fe68f2..000000000 --- a/Demo/PC/FreeRTOSConfig.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -#include -#include - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 1 -#define configUSE_TICK_HOOK 1 -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 ) /* This can be made smaller if required. */ -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 32 * 1024 ) ) -#define configMAX_TASK_NAME_LEN ( 16 ) -#define configUSE_TRACE_FACILITY 1 -#define configUSE_16_BIT_TICKS 1 -#define configIDLE_SHOULD_YIELD 1 -#define configUSE_CO_ROUTINES 1 - -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 10 ) -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 1 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 - - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/PC/ParTest/ParTest.c b/Demo/PC/ParTest/ParTest.c deleted file mode 100644 index 5dfec2ff0..000000000 --- a/Demo/PC/ParTest/ParTest.c +++ /dev/null @@ -1,121 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V1.01: - - + Types used updated. - + Add vParTestToggleLED(); - - -Changes from V2.0.0 - - + Use scheduler suspends in place of critical sections. -*/ - -#include "FreeRTOS.h" -#include "partest.h" -#include "task.h" - -#define partstALL_OUTPUTS_OFF ( ( unsigned portCHAR ) 0x00 ) -#define partstMAX_OUTPUT_LED ( ( unsigned portCHAR ) 7 ) - -/*lint -e956 File scope parameters okay here. */ -static unsigned portSHORT usPortAddress = partstDEFAULT_PORT_ADDRESS; -static volatile unsigned portCHAR ucCurrentOutputValue = partstALL_OUTPUTS_OFF; -/*lint +e956 */ - - -/*----------------------------------------------------------- - * Simple parallel port IO routines - *-----------------------------------------------------------*/ - -void vParTestInitialise( void ) -{ - ucCurrentOutputValue = partstALL_OUTPUTS_OFF; - - portOUTPUT_BYTE( usPortAddress, ( unsigned ) partstALL_OUTPUTS_OFF ); -} -/*-----------------------------------------------------------*/ - -void vParTestSetLED( unsigned portBASE_TYPE uxLED, portBASE_TYPE xValue ) -{ -unsigned portCHAR ucBit = ( unsigned portCHAR ) 1; - - if( uxLED <= partstMAX_OUTPUT_LED ) - { - ucBit <<= uxLED; - } - - vTaskSuspendAll(); - { - if( xValue == pdTRUE ) - { - ucBit ^= ( unsigned portCHAR ) 0xff; - ucCurrentOutputValue &= ucBit; - } - else - { - ucCurrentOutputValue |= ucBit; - } - - portOUTPUT_BYTE( usPortAddress, ( unsigned ) ucCurrentOutputValue ); - } - xTaskResumeAll(); -} -/*-----------------------------------------------------------*/ - -void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) -{ -unsigned portCHAR ucBit; - - if( uxLED <= partstMAX_OUTPUT_LED ) - { - ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED; - - vTaskSuspendAll(); - { - if( ucCurrentOutputValue & ucBit ) - { - ucCurrentOutputValue &= ~ucBit; - } - else - { - ucCurrentOutputValue |= ucBit; - } - - portOUTPUT_BYTE( usPortAddress, ( unsigned ) ucCurrentOutputValue ); - } - xTaskResumeAll(); - } -} - diff --git a/Demo/PC/RTOSDEMO.IDE b/Demo/PC/RTOSDEMO.IDE deleted file mode 100644 index 18c17b616..000000000 Binary files a/Demo/PC/RTOSDEMO.IDE and /dev/null differ diff --git a/Demo/PC/main.c b/Demo/PC/main.c deleted file mode 100644 index 73dc4086e..000000000 --- a/Demo/PC/main.c +++ /dev/null @@ -1,427 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/** - * Creates all the demo application tasks and co-routines, then starts the - * scheduler. - * - * Main. c also creates a task called "Print". This only executes every - * five seconds but has the highest priority so is guaranteed to get - * processor time. Its main function is to check that all the other tasks - * are still operational. Nearly all the tasks in the demo application - * maintain a unique count that is incremented each time the task successfully - * completes its function. Should any error occur within the task the count is - * permanently halted. The print task checks the count of each task to ensure - * it has changed since the last time the print task executed. If any count is - * found not to have changed the print task displays an appropriate message. - * If all the tasks are still incrementing their unique counts the print task - * displays an "OK" message. - * - * The LED flash tasks do not maintain a count as they already provide visual - * feedback of their status. - * - * The print task blocks on the queue into which messages that require - * displaying are posted. It will therefore only block for the full 5 seconds - * if no messages are posted onto the queue. - * - * Main. c also provides a demonstration of how the trace visualisation utility - * can be used, and how the scheduler can be stopped. - * - * \page MainC main.c - * \ingroup DemoFiles - *
- */ - -/* -Changes from V1.00: - - + Prevent the call to kbhit() for debug builds as the debugger seems to - have problems stepping over the call. - -Changes from V1.2.3 - - + The integer and comtest tasks are now used when the cooperative scheduler - is being used. Previously they were only used with the preemptive - scheduler. - -Changes from V1.2.6 - - + Create new tasks as defined by the new demo application file dynamic.c. - -Changes from V2.0.0 - - + Delay periods are now specified using variables and constants of - portTickType rather than unsigned portLONG. - -Changes from V3.1.1 - - + The tasks defined in the new file "events.c" are now created and - monitored for errors. - -Changes from V3.2.4 - - + Now includes the flash co-routine demo rather than the flash task demo. - This is to demonstrate the co-routine functionality. -*/ - -#include -#include -#include "FreeRTOS.h" -#include "task.h" -#include "croutine.h" -#include "partest.h" -#include "serial.h" - -/* Demo file headers. */ -#include "BlockQ.h" -#include "PollQ.h" -#include "death.h" -#include "crflash.h" -#include "flop.h" -#include "print.h" -#include "comtest.h" -#include "fileio.h" -#include "semtest.h" -#include "integer.h" -#include "dynamic.h" -#include "mevents.h" -#include "crhook.h" -#include "blocktim.h" - -/* Priority definitions for the tasks in the demo application. */ -#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainPRINT_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_BLOCK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainSEMAPHORE_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) - -#define mainPRINT_STACK_SIZE ( ( unsigned portSHORT ) 512 ) -#define mainDEBUG_LOG_BUFFER_SIZE ( ( unsigned portSHORT ) 20480 ) - -/* The number of flash co-routines to create. */ -#define mainNUM_FLASH_CO_ROUTINES ( 8 ) - -/* Task function for the "Print" task as described at the top of the file. */ -static void vErrorChecks( void *pvParameters ); - -/* Function that checks the unique count of all the other tasks as described at -the top of the file. */ -static void prvCheckOtherTasksAreStillRunning( void ); - -/* Key presses can be used to start/stop the trace visualisation utility or stop -the scheduler. */ -static void prvCheckForKeyPresses( void ); - -/* Buffer used by the trace visualisation utility so only needed if the trace -being used. */ -#if configUSE_TRACE_FACILITY == 1 - static portCHAR pcWriteBuffer[ mainDEBUG_LOG_BUFFER_SIZE ]; -#endif - -/* Constant definition used to turn on/off the pre-emptive scheduler. */ -static const portSHORT sUsingPreemption = configUSE_PREEMPTION; - -/* Start the math tasks appropriate to the build. The Borland port does -not yet support floating point so uses the integer equivalent. */ -static void prvStartMathTasks( void ); - -/* Check which ever tasks are relevant to this build. */ -static portBASE_TYPE prvCheckMathTasksAreStillRunning( void ); - -/*-----------------------------------------------------------*/ - -portSHORT main( void ) -{ - /* Initialise hardware and utilities. */ - vParTestInitialise(); - vPrintInitialise(); - - /* CREATE ALL THE DEMO APPLICATION TASKS. */ - prvStartMathTasks(); - vStartComTestTasks( mainCOM_TEST_PRIORITY, serCOM1, ser115200 ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartBlockingQueueTasks( mainQUEUE_BLOCK_PRIORITY ); - vCreateBlockTimeTasks(); - - vStartSemaphoreTasks( mainSEMAPHORE_TASK_PRIORITY ); - vStartDynamicPriorityTasks(); - vStartMultiEventTasks(); - - /* Create the "Print" task as described at the top of the file. */ - xTaskCreate( vErrorChecks, "Print", mainPRINT_STACK_SIZE, NULL, mainPRINT_TASK_PRIORITY, NULL ); - - /* This task has to be created last as it keeps account of the number of tasks - it expects to see running. */ - vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); - - /* Create the co-routines that flash the LED's. */ - vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES ); - - /* Create the co-routines that communicate with the tick hook. */ - vStartHookCoRoutines(); - - /* Set the scheduler running. This function will not return unless a task - calls vTaskEndScheduler(). */ - vTaskStartScheduler(); - - return 1; -} -/*-----------------------------------------------------------*/ - -static void vErrorChecks( void *pvParameters ) -{ -portTickType xExpectedWakeTime; -const portTickType xPrintRate = ( portTickType ) 5000 / portTICK_RATE_MS; -const portLONG lMaxAllowableTimeDifference = ( portLONG ) 0; -portTickType xWakeTime; -portLONG lTimeDifference; -const portCHAR *pcReceivedMessage; -const portCHAR * const pcTaskBlockedTooLongMsg = "Print task blocked too long!\r\n"; - - ( void ) pvParameters; - - /* Loop continuously, blocking, then checking all the other tasks are still - running, before blocking once again. This task blocks on the queue of - messages that require displaying so will wake either by its time out expiring, - or a message becoming available. */ - for( ;; ) - { - /* Calculate the time we will unblock if no messages are received - on the queue. This is used to check that we have not blocked for too long. */ - xExpectedWakeTime = xTaskGetTickCount(); - xExpectedWakeTime += xPrintRate; - - /* Block waiting for either a time out or a message to be posted that - required displaying. */ - pcReceivedMessage = pcPrintGetNextMessage( xPrintRate ); - - /* Was a message received? */ - if( pcReceivedMessage == NULL ) - { - /* A message was not received so we timed out, did we unblock at the - expected time? */ - xWakeTime = xTaskGetTickCount(); - - /* Calculate the difference between the time we unblocked and the - time we should have unblocked. */ - if( xWakeTime > xExpectedWakeTime ) - { - lTimeDifference = ( portLONG ) ( xWakeTime - xExpectedWakeTime ); - } - else - { - lTimeDifference = ( portLONG ) ( xExpectedWakeTime - xWakeTime ); - } - - if( lTimeDifference > lMaxAllowableTimeDifference ) - { - /* We blocked too long - create a message that will get - printed out the next time around. If we are not using - preemption then we won't expect the timing to be so - accurate. */ - if( sUsingPreemption == pdTRUE ) - { - vPrintDisplayMessage( &pcTaskBlockedTooLongMsg ); - } - } - - /* Check the other tasks are still running, just in case. */ - prvCheckOtherTasksAreStillRunning(); - } - else - { - /* We unblocked due to a message becoming available. Send the message - for printing. */ - vDisplayMessage( pcReceivedMessage ); - } - - /* Key presses are used to invoke the trace visualisation utility, or end - the program. */ - prvCheckForKeyPresses(); - } -} -/*-----------------------------------------------------------*/ - -static void prvCheckForKeyPresses( void ) -{ -portSHORT sIn; - - taskENTER_CRITICAL(); - #ifdef DEBUG_BUILD - /* kbhit can be used in .exe's that are executed from the command - line, but not if executed through the debugger. */ - sIn = 0; - #else - sIn = kbhit(); - #endif - taskEXIT_CRITICAL(); - - if( sIn ) - { - /* Key presses can be used to start/stop the trace utility, or end the - program. */ - sIn = getch(); - switch( sIn ) - { - /* Only define keys for turning on and off the trace if the trace - is being used. */ - #if configUSE_TRACE_FACILITY == 1 - case 't' : vTaskList( pcWriteBuffer ); - vWriteMessageToDisk( pcWriteBuffer ); - break; - case 's' : vTaskStartTrace( pcWriteBuffer, mainDEBUG_LOG_BUFFER_SIZE ); - break; - - case 'e' : { - unsigned portLONG ulBufferLength; - ulBufferLength = ulTaskEndTrace(); - vWriteBufferToDisk( pcWriteBuffer, ulBufferLength ); - } - break; - #endif - - default : vTaskEndScheduler(); - break; - } - } -} -/*-----------------------------------------------------------*/ - -static void prvCheckOtherTasksAreStillRunning( void ) -{ -static portSHORT sErrorHasOccurred = pdFALSE; - - if( prvCheckMathTasksAreStillRunning() != pdTRUE ) - { - vDisplayMessage( "Maths task count unchanged!\r\n" ); - sErrorHasOccurred = pdTRUE; - } - - if( xAreComTestTasksStillRunning() != pdTRUE ) - { - vDisplayMessage( "Com test count unchanged!\r\n" ); - sErrorHasOccurred = pdTRUE; - } - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - vDisplayMessage( "Blocking queues count unchanged!\r\n" ); - sErrorHasOccurred = pdTRUE; - } - - if( xArePollingQueuesStillRunning() != pdTRUE ) - { - vDisplayMessage( "Polling queue count unchanged!\r\n" ); - sErrorHasOccurred = pdTRUE; - } - - if( xIsCreateTaskStillRunning() != pdTRUE ) - { - vDisplayMessage( "Incorrect number of tasks running!\r\n" ); - sErrorHasOccurred = pdTRUE; - } - - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - vDisplayMessage( "Semaphore take count unchanged!\r\n" ); - sErrorHasOccurred = pdTRUE; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - vDisplayMessage( "Dynamic priority count unchanged!\r\n" ); - sErrorHasOccurred = pdTRUE; - } - - if( xAreMultiEventTasksStillRunning() != pdTRUE ) - { - vDisplayMessage( "Error in multi events tasks!\r\n" ); - sErrorHasOccurred = pdTRUE; - } - - if( xAreFlashCoRoutinesStillRunning() != pdTRUE ) - { - vDisplayMessage( "Error in co-routine flash tasks!\r\n" ); - sErrorHasOccurred = pdTRUE; - } - - if( xAreHookCoRoutinesStillRunning() != pdTRUE ) - { - vDisplayMessage( "Error in tick hook to co-routine communications!\r\n" ); - sErrorHasOccurred = pdTRUE; - } - - if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) - { - vDisplayMessage( "Error in block time test tasks!\r\n" ); - sErrorHasOccurred = pdTRUE; - } - - if( sErrorHasOccurred == pdFALSE ) - { - vDisplayMessage( "OK " ); - } -} -/*-----------------------------------------------------------*/ - -static void prvStartMathTasks( void ) -{ - #ifdef BCC_INDUSTRIAL_PC_PORT - /* The Borland project does not yet support floating point. */ - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - #else - vStartMathTasks( tskIDLE_PRIORITY ); - #endif -} -/*-----------------------------------------------------------*/ - -static portBASE_TYPE prvCheckMathTasksAreStillRunning( void ) -{ - #ifdef BCC_INDUSTRIAL_PC_PORT - /* The Borland project does not yet support floating point. */ - return xAreIntegerMathsTaskStillRunning(); - #else - return xAreMathsTaskStillRunning(); - #endif -} -/*-----------------------------------------------------------*/ - -void vApplicationIdleHook( void ) -{ - /* The co-routines are executed in the idle task using the idle task - hook. */ - vCoRoutineSchedule(); -} -/*-----------------------------------------------------------*/ - diff --git a/Demo/PC/rtosdemo.DSW b/Demo/PC/rtosdemo.DSW deleted file mode 100644 index 3b8e4254c..000000000 Binary files a/Demo/PC/rtosdemo.DSW and /dev/null differ diff --git a/Demo/PC/rtosdemo.tgt b/Demo/PC/rtosdemo.tgt deleted file mode 100644 index 7b5f2d66d..000000000 --- a/Demo/PC/rtosdemo.tgt +++ /dev/null @@ -1,1282 +0,0 @@ -40 -targetIdent -0 -MProject -1 -MComponent -0 -2 -WString -3 -EXE -3 -WString -5 -de6en -1 -0 -0 -4 -MCommand -0 -5 -MCommand -0 -6 -MItem -12 -rtosdemo.exe -7 -WString -3 -EXE -8 -WVList -2 -9 -MRState -10 -WString -5 -WLINK -11 -WString -14 -?????Debug All -1 -0 -12 -MRState -13 -WString -5 -WLINK -14 -WString -16 -?????Debug Dwarf -1 -1 -15 -WVList -1 -16 -ActionStates -17 -WString -5 -&Make -18 -WVList -0 --1 -1 -1 -0 -19 -WPickList -50 -20 -MItem -3 -*.c -21 -WString -4 -COBJ -22 -WVList -24 -23 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file mode 100644 index 1b02cfb2f..000000000 --- a/Demo/PC/rtosdemo.wpj +++ /dev/null @@ -1,43 +0,0 @@ -40 -projectIdent -0 -VpeMain -1 -WRect -0 -0 -7680 -9216 -2 -MProject -3 -MCommand -0 -4 -MCommand -0 -1 -5 -WFileName -12 -rtosdemo.tgt -6 -WVList -1 -7 -VComponent -8 -WRect -0 -0 -7168 -7168 -0 -0 -9 -WFileName -12 -rtosdemo.tgt -0 -25 -7 diff --git a/Demo/PC/serial/serial.c b/Demo/PC/serial/serial.c deleted file mode 100644 index d3beb8d2e..000000000 --- a/Demo/PC/serial/serial.c +++ /dev/null @@ -1,674 +0,0 @@ -/* - This serial port driver is borrowed heavily from DZComm. I have - simplified it by removing a lot of the functionality (hardware - flow control, etc.). For more details and the full version see - http://dzcomm.sourceforge.net - - - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V1.00: - - + Call to the more efficient portSWITCH_CONTEXT() replaces the call to - taskYIELD() in the ISR. - -Changes from V1.2.0: - - + Added vSerialPutString(). - -Changes from V1.2.3 - - + The function xPortInitMinimal() has been renamed to - xSerialPortInitMinimal() and the function xPortInit() has been renamed - to xSerialPortInit(). - -Changes From V2.0.0 - - + Use portTickType in place of unsigned pdLONG for delay periods. - + cQueueReieveFromISR() used in place of xQueueReceive() in ISR. -*/ - - -#include -#include -#include "FreeRTOS.h" -#include "queue.h" -#include "task.h" -#include "semphr.h" -#include "portasm.h" - -#define serMAX_IRQs ( 16 ) -#define serTRANSMIT_HOLD_EMPTY_INT ( 0x02 ) -#define serCOM1_STANDARD_IRQ ( ( unsigned portCHAR ) 4 ) -#define serCOM2_STANDARD_IRQ ( ( unsigned portCHAR ) 3 ) - - -#define serIMR_8259_0 ( ( unsigned portCHAR ) 0x21 ) -#define serIMR_8259_1 ( ( unsigned portCHAR ) 0xa1 ) -#define serISR_8259_0 ( ( unsigned portCHAR ) 0x20 ) -#define serISR_8259_1 ( ( unsigned portCHAR ) 0xa0 ) -#define serALL_COMS_INTERRUPTS ( ( unsigned portCHAR ) 0x0f ) -#define serALL_MODEM_CTRL_INTERRUPTS ( ( unsigned portCHAR ) 0x0f ) - -#define serTRANSMIT_HOLD_OFFSET ( 0 ) -#define serRECEIVE_DATA_OFFSET ( 0 ) -#define serBAUD_RATE_DIVISOR_LOW_OFFSET ( 0 ) -#define serBAUD_RATE_DIVISOR_HIGH_OFFSET ( 1 ) -#define serINTERRUPT_ENABLE_OFFSET ( 1 ) -#define serINTERRUPT_ID_OFFSET ( 2 ) -#define serFIFO_CTRL_OFFSET ( 2 ) -#define serLINE_CTRL_OFFSET ( 3 ) -#define serMODEM_CTRL_OFFSET ( 4 ) -#define serLINE_STATUS_OFFSET ( 5 ) -#define serMODEM_STATUS_OFFSET ( 6 ) -#define serSCR_OFFSET ( 7 ) - -#define serMAX_BAUD ( ( unsigned portLONG ) 115200UL ) - -#define serNO_INTERRUPTS ( 0x00 ) - -#define vInterruptOn( pxPort, ucInterrupt ) \ -{ \ - unsigned portCHAR ucIn = portINPUT_BYTE( pxPort->usInterruptEnableReg ); \ - if( !( ucIn & ucInterrupt ) ) \ - { \ - portOUTPUT_BYTE( pxPort->usInterruptEnableReg, ucIn | ucInterrupt ); \ - } \ -} -/*-----------------------------------------------------------*/ - -#define vInterruptOff( pxPort, ucInterrupt ) \ -{ \ - unsigned portCHAR ucIn = portINPUT_BYTE( pxPort->usInterruptEnableReg ); \ - if( ucIn & ucInterrupt ) \ - { \ - portOUTPUT_BYTE( pxPort->usInterruptEnableReg, ucIn & ~ucInterrupt); \ - } \ -} -/*-----------------------------------------------------------*/ - -typedef enum -{ - serCOM1, - serCOM2, - serCOM3, - serCOM4, - serCOM5, - serCOM6, - serCOM7, - serCOM8 -} eCOMPort; - -typedef enum -{ - serNO_PARITY, - serODD_PARITY, - serEVEN_PARITY, - serMARK_PARITY, - serSPACE_PARITY -} eParity; - -typedef enum -{ - serSTOP_1, - serSTOP_2 -} eStopBits; - -typedef enum -{ - serBITS_5, - serBITS_6, - serBITS_7, - serBITS_8 -} eDataBits; - -typedef enum -{ - ser50, - ser75, - ser110, - ser134, - ser150, - ser200, - ser300, - ser600, - ser1200, - ser1800, - ser2400, - ser4800, - ser9600, - ser19200, - ser38400, - ser57600, - ser115200 -} eBaud; - -/* This *MUST* match the order in the eBaud definition. */ -unsigned portLONG ulBaudFromEnum[] = -{ - ( unsigned portLONG ) 50, - ( unsigned portLONG ) 75, - ( unsigned portLONG ) 110, - ( unsigned portLONG ) 134, - ( unsigned portLONG ) 150, - ( unsigned portLONG ) 200, - ( unsigned portLONG ) 300, - ( unsigned portLONG ) 600, - ( unsigned portLONG ) 1200, - ( unsigned portLONG ) 1800, - ( unsigned portLONG ) 2400, - ( unsigned portLONG ) 4800, - ( unsigned portLONG ) 9600, - ( unsigned portLONG ) 19200, - ( unsigned portLONG ) 38400UL, - ( unsigned portLONG ) 57600UL, - ( unsigned portLONG ) 115200UL -}; - -typedef struct xCOM_PORT -{ - unsigned portSHORT sPort; /* comm port address eg. 0x3f8 */ - unsigned portCHAR ucIRQ; /* comm IRQ eg. 3 */ - - /* Next two fields used for setting up the IRQ routine and - * (un)masking the interrupt in certain circumstances. - */ - unsigned portSHORT usIRQVector; - unsigned portCHAR ucInterruptEnableMast; - - /* Read/Write buffers. */ - xQueueHandle xRxedChars; - xQueueHandle xCharsForTx; - - /* This lot are set up to minimise CPU time where accessing the comm - * port's registers. - */ - unsigned portSHORT usTransmitHoldReg; - unsigned portSHORT usReceiveDataRegister; - unsigned portSHORT usBaudRateDivisorLow; - unsigned portSHORT usBaudRateDivisorHigh; - unsigned portSHORT usInterruptEnableReg; - unsigned portSHORT usInterruptIDReg; - unsigned portSHORT usFIFOCtrlReg; - unsigned portSHORT usLineCtrlReg; - unsigned portSHORT usModemCtrlReg; - unsigned portSHORT usLineStatusReg; - unsigned portSHORT usModemStatusReg; - unsigned portSHORT usSCRReg; - unsigned portSHORT us8259InterruptServiceReg; - unsigned portSHORT us8259InterruptMaskReg; - - /* This semaphore does nothing useful except test a feature of the - scheduler. */ - xSemaphoreHandle xTestSem; - -} xComPort; - -typedef xComPort *xComPortHandle; - -/* A xComPort structure can be associated with each IRQ. Initially none -are create/installed. */ -xComPort *xPortStatus[ serMAX_IRQs ] = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL }; - -/*-----------------------------------------------------------*/ - -/* These prototypes are repeated here so we don't have to include the serial header. This allows -the xComPortHandle structure details to be private to this file. */ -xComPortHandle xSerialPortInit( eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits, unsigned portBASE_TYPE uxBufferLength ); -portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, portCHAR *pcRxedChar, portTickType xBlockTime ); -portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, portCHAR cOutChar, portTickType xBlockTime ); -portBASE_TYPE xSerialWaitForSemaphore( xComPortHandle xPort ); - -static void prvSetupPortHardware( xComPort *pxPort, eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits ); -static portSHORT sComPortISR( const xComPort * const pxPort ); - -/*-----------------------------------------------------------*/ - -/* Define an interrupt handler for each slot in the xPortStatus array. */ - -#define COM_IRQ_WRAPPER(N) \ - static void __interrupt COM_IRQ##N##_WRAPPER( void ) \ - { \ - portDISABLE_INTERRUPTS(); \ - if( sComPortISR( xPortStatus[##N##] ) ) \ - { \ - portSWITCH_CONTEXT(); \ - } \ - } - -COM_IRQ_WRAPPER( 0 ) -COM_IRQ_WRAPPER( 1 ) -COM_IRQ_WRAPPER( 2 ) -COM_IRQ_WRAPPER( 3 ) -COM_IRQ_WRAPPER( 4 ) -COM_IRQ_WRAPPER( 5 ) -COM_IRQ_WRAPPER( 6 ) -COM_IRQ_WRAPPER( 7 ) -COM_IRQ_WRAPPER( 8 ) -COM_IRQ_WRAPPER( 9 ) -COM_IRQ_WRAPPER( 10 ) -COM_IRQ_WRAPPER( 11 ) -COM_IRQ_WRAPPER( 12 ) -COM_IRQ_WRAPPER( 13 ) -COM_IRQ_WRAPPER( 14 ) -COM_IRQ_WRAPPER( 15 ) - -static pxISR xISRs[ serMAX_IRQs ] = -{ - COM_IRQ0_WRAPPER, - COM_IRQ1_WRAPPER, - COM_IRQ2_WRAPPER, - COM_IRQ3_WRAPPER, - COM_IRQ4_WRAPPER, - COM_IRQ5_WRAPPER, - COM_IRQ6_WRAPPER, - COM_IRQ7_WRAPPER, - COM_IRQ8_WRAPPER, - COM_IRQ9_WRAPPER, - COM_IRQ10_WRAPPER, - COM_IRQ11_WRAPPER, - COM_IRQ12_WRAPPER, - COM_IRQ13_WRAPPER, - COM_IRQ14_WRAPPER, - COM_IRQ15_WRAPPER -}; - -static pxISR xOldISRs[ serMAX_IRQs ] = { NULL }; - -/*-----------------------------------------------------------*/ - - -xComPortHandle xSerialPortInit( eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits, unsigned portBASE_TYPE uxBufferLength ) -{ -xComPort *pxPort; - - /* Create a structure to handle this port. */ - pxPort = ( xComPort * ) pvPortMalloc( sizeof( xComPort ) ); - - if( pxPort != NULL ) - { - /* Create the queues used by the comtest task. */ - pxPort->xRxedChars = xQueueCreate( uxBufferLength, ( unsigned portBASE_TYPE ) sizeof( portCHAR ) ); - pxPort->xCharsForTx = xQueueCreate( uxBufferLength, ( unsigned portBASE_TYPE ) sizeof( portCHAR ) ); - - /* Create the test semaphore. This does nothing useful except test a feature of the scheduler. */ - vSemaphoreCreateBinary( pxPort->xTestSem ); - - prvSetupPortHardware( pxPort, ePort, eWantedBaud, eWantedParity, eWantedDataBits, eWantedStopBits ); - - return pxPort; - } - - return NULL; -} -/*-----------------------------------------------------------*/ - -static void prvSetupPortHardware( xComPort *pxPort, eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits ) -{ -portSHORT sIn; -unsigned portLONG ulDivisor; -unsigned portCHAR ucDivisorLow; -unsigned portCHAR ucDivisorHigh; -unsigned portCHAR ucCommParam; - - /* IRQ numbers - standard */ - if( ( ePort == serCOM1 ) || ( ePort == serCOM3 ) || ( ePort == serCOM5 ) || ( ePort == serCOM7 ) ) - { - pxPort->ucIRQ = serCOM1_STANDARD_IRQ; - pxPort->sPort = 0x3f8; - } - else - { - pxPort->ucIRQ = serCOM2_STANDARD_IRQ; - pxPort->sPort = 0x2f8; - } - - /* Set up variables in port making it easy to see which sIn/o address is which */ - pxPort->usTransmitHoldReg = pxPort->sPort + serTRANSMIT_HOLD_OFFSET; - pxPort->usReceiveDataRegister = pxPort->sPort + serRECEIVE_DATA_OFFSET; - pxPort->usBaudRateDivisorLow = pxPort->sPort + serBAUD_RATE_DIVISOR_LOW_OFFSET; - pxPort->usBaudRateDivisorHigh = pxPort->sPort + serBAUD_RATE_DIVISOR_HIGH_OFFSET; - pxPort->usInterruptEnableReg = pxPort->sPort + serINTERRUPT_ENABLE_OFFSET; - pxPort->usInterruptIDReg = pxPort->sPort + serINTERRUPT_ID_OFFSET; - pxPort->usFIFOCtrlReg = pxPort->sPort + serFIFO_CTRL_OFFSET; - pxPort->usLineCtrlReg = pxPort->sPort + serLINE_CTRL_OFFSET; - pxPort->usModemCtrlReg = pxPort->sPort + serMODEM_CTRL_OFFSET; - pxPort->usLineStatusReg = pxPort->sPort + serLINE_STATUS_OFFSET; - pxPort->usModemStatusReg = pxPort->sPort + serMODEM_STATUS_OFFSET; - pxPort->usSCRReg = pxPort->sPort + serSCR_OFFSET; - - /* Set communication parameters. */ - ulDivisor = serMAX_BAUD / ulBaudFromEnum[ eWantedBaud ]; - ucDivisorLow = ( unsigned portCHAR ) ulDivisor & ( unsigned portCHAR ) 0xff; - ucDivisorHigh = ( unsigned portCHAR ) ( ( ( unsigned portSHORT ) ulDivisor >> 8 ) & 0xff ); - - switch( eWantedParity ) - { - case serNO_PARITY: ucCommParam = 0x00; - break; - case serODD_PARITY: ucCommParam = 0x08; - break; - case serEVEN_PARITY: ucCommParam = 0x18; - break; - case serMARK_PARITY: ucCommParam = 0x28; - break; - case serSPACE_PARITY: ucCommParam = 0x38; - break; - default: ucCommParam = 0x00; - break; - } - - switch ( eWantedDataBits ) - { - case serBITS_5: ucCommParam |= 0x00; - break; - case serBITS_6: ucCommParam |= 0x01; - break; - case serBITS_7: ucCommParam |= 0x02; - break; - case serBITS_8: ucCommParam |= 0x03; - break; - default: ucCommParam |= 0x03; - break; - } - - if( eWantedStopBits == serSTOP_2 ) - { - ucCommParam |= 0x04; - } - - /* Reset UART into known state - Thanks to Bradley Town */ - portOUTPUT_BYTE( pxPort->usLineCtrlReg, 0x00 ); /* Access usTransmitHoldReg/RBR/usInterruptEnableReg */ - portOUTPUT_BYTE( pxPort->usInterruptEnableReg, 0x00 ); /* Disable interrupts from UART */ - portOUTPUT_BYTE( pxPort->usModemCtrlReg, 0x04 ); /* Enable some multi-port cards */ - - /* Code based on stuff from SVAsync lib. Clear UART Status and data registers - setting up FIFO if possible */ - sIn = portINPUT_BYTE( pxPort->usSCRReg ); - portOUTPUT_BYTE( pxPort->usSCRReg, 0x55 ); - - if( portINPUT_BYTE( pxPort->usSCRReg ) == 0x55 ) - { - /* The chip is better than an 8250 */ - portOUTPUT_BYTE( pxPort->usSCRReg, sIn ); /* Set usSCRReg back to what it was before */ - portINPUT_BYTE( pxPort->usSCRReg); /* Give slow motherboards a chance */ - - /* Try and start the FIFO. It appears that some chips need a two call - protocol, but those that don't seem to work even if you do start it twice. - The first call is simply to start it, the second starts it and sets an 8 - byte FIFO trigger level. */ - portOUTPUT_BYTE( pxPort->usFIFOCtrlReg, 0x01 ); - portINPUT_BYTE( pxPort->usFIFOCtrlReg ); /* Give slow motherboards a chance to catch up */ - portOUTPUT_BYTE( pxPort->usFIFOCtrlReg, 0x87 ); - - /* Check that the FIFO initialised */ - if( ( portINPUT_BYTE( pxPort->usInterruptIDReg ) & 0xc0 ) != 0xc0 ) - { - /* It didn't so we assume it isn't there but disable it to be on the - safe side. */ - portOUTPUT_BYTE( pxPort->usInterruptIDReg, 0xfe ); - } - } - - /* End of (modified) SVAsync code. - Set interrupt parameters calculating mask for 8259 controller's - IMR and number of interrupt handler for given irq level */ - if (pxPort->ucIRQ <= 7) - { - /* if 0<=irq<=7 first IMR address used */ - pxPort->ucInterruptEnableMast = ~(0x01 << pxPort->ucIRQ); - pxPort->usIRQVector = pxPort->ucIRQ + 8; - pxPort->us8259InterruptMaskReg = serIMR_8259_0; - pxPort->us8259InterruptServiceReg = serISR_8259_0; - } - else - { - pxPort->ucInterruptEnableMast = ~( 0x01 << ( pxPort->ucIRQ % 8 ) ); - pxPort->usIRQVector = 0x70 + ( pxPort->ucIRQ - 8) ; - pxPort->us8259InterruptMaskReg = serIMR_8259_1; - pxPort->us8259InterruptServiceReg = serISR_8259_1; - } - - /* Set Port Toggle to usBaudRateDivisorLow/usBaudRateDivisorHigh registers - to set baud rate */ - portOUTPUT_BYTE( pxPort->usLineCtrlReg, ucCommParam | 0x80 ); - portOUTPUT_BYTE( pxPort->usBaudRateDivisorLow, ucDivisorLow ); - portOUTPUT_BYTE( pxPort->usBaudRateDivisorHigh, ucDivisorHigh ); - - /* reset usLineCtrlReg and Port Toggleout */ - portOUTPUT_BYTE( pxPort->usLineCtrlReg, ucCommParam & 0x7F ); - - portENTER_CRITICAL(); - - if( xPortStatus[ pxPort->ucIRQ ] == NULL ) - { - xPortStatus[ pxPort->ucIRQ ] = pxPort; - } - - xOldISRs[ pxPort->ucIRQ ] = _dos_getvect( pxPort->usIRQVector ); - _dos_setvect( pxPort->usIRQVector, xISRs[ pxPort->ucIRQ ] ); - - /* enable interrupt pxPort->ucIRQ level */ - portOUTPUT_BYTE( pxPort->us8259InterruptMaskReg, portINPUT_BYTE( pxPort->us8259InterruptMaskReg ) & pxPort->ucInterruptEnableMast ); - - /* And allow interrupts again now the hairy bit's done */ - portEXIT_CRITICAL(); - - /* This version does not allow flow control. */ - portOUTPUT_BYTE( pxPort->usModemCtrlReg, serALL_MODEM_CTRL_INTERRUPTS ); - - /* enable all communication's interrupts */ - portOUTPUT_BYTE( pxPort->usInterruptEnableReg, serALL_COMS_INTERRUPTS ); -} -/*-----------------------------------------------------------*/ - -static portSHORT sComPortISR( const xComPort * const pxPort ) -{ -portSHORT sInterruptID; -portCHAR cIn, cOut; -portBASE_TYPE xTaskWokenByPost = pdFALSE, xAnotherTaskWokenByPost = pdFALSE, xTaskWokenByTx = pdFALSE; - - portOUTPUT_BYTE( pxPort->us8259InterruptMaskReg, ( portINPUT_BYTE( pxPort->us8259InterruptMaskReg) | ~pxPort->ucInterruptEnableMast ) ); - - /* Decide which UART has issued the interrupt */ - sInterruptID = portINPUT_BYTE( pxPort->usInterruptIDReg ); - - /* service whatever requests the calling UART may have. The top 4 bits are - either unused or indicate the presence of a functioning FIFO, which we don't - need to know. So trim them off to simplify the switch statement below. */ - sInterruptID &= 0x0f; - do - { - switch( sInterruptID ) - { - case 0x0c: /* Timeout - Called when FIFO not up to trigger level but no activity for - a while. Handled exactly as RDAINT, see below for - description. */ - do - { - cIn = ( portCHAR ) portINPUT_BYTE( pxPort->usReceiveDataRegister ); - xTaskWokenByPost = xQueueSendFromISR( pxPort->xRxedChars, &cIn, xTaskWokenByPost ); - - /* Also release the semaphore - this does nothing interesting and is just a test. */ - xAnotherTaskWokenByPost = xSemaphoreGiveFromISR( pxPort->xTestSem, xAnotherTaskWokenByPost ); - - } while( portINPUT_BYTE( pxPort->usLineStatusReg ) & 0x01 ); - break; - - case 0x06: /* LSINT */ - portINPUT_BYTE( pxPort->usLineStatusReg ); - break; - - case 0x04: /* RDAINT */ - /* The usInterruptIDReg flag tested above stops when the - FIFO is below the trigger level rather than empty, whereas - this flag allows one to empty it: (do loop because there - must be at least one to read by virtue of having got here.) */ - do - { - cIn = ( portCHAR ) portINPUT_BYTE( pxPort->usReceiveDataRegister ); - xTaskWokenByPost = xQueueSendFromISR( pxPort->xRxedChars, &cIn, xTaskWokenByPost ); - - /* Also release the semaphore - this does nothing interesting and is just a test. */ - xAnotherTaskWokenByPost = xSemaphoreGiveFromISR( pxPort->xTestSem, xAnotherTaskWokenByPost ); - - } while( portINPUT_BYTE( pxPort->usLineStatusReg ) & 0x01 ); - break; - - case 0x02: /* serTRANSMIT_HOLD_EMPTY_INT */ - if( xQueueReceiveFromISR( pxPort->xCharsForTx, &cOut, &xTaskWokenByTx ) != pdTRUE ) - { - /* Queue empty, nothing to send */ - vInterruptOff( pxPort, serTRANSMIT_HOLD_EMPTY_INT); - } - else - { - portOUTPUT_BYTE( pxPort->usTransmitHoldReg, ( portSHORT ) cOut ); - } - break; - - case 0x00: /* MSINT */ - portINPUT_BYTE( pxPort->usModemStatusReg ); - break; - } - - /* Get the next instruction, trimming as above */ - sInterruptID = portINPUT_BYTE( pxPort->usInterruptIDReg ) & 0x0f; - - } while( !( sInterruptID & 0x01 ) ); - - if( pxPort->ucIRQ > 7 ) - { - portOUTPUT_BYTE( 0xA0, 0x60 + ( pxPort->ucIRQ & 0x07 ) ); - portOUTPUT_BYTE( 0x20, 0x62); - } - else - { - portOUTPUT_BYTE( 0x20, 0x60 + pxPort->ucIRQ ); - } - - portOUTPUT_BYTE( pxPort->us8259InterruptMaskReg, portINPUT_BYTE( pxPort->us8259InterruptMaskReg ) & pxPort->ucInterruptEnableMast ); - - /* If posting any of the characters to a queue woke a task that was blocked on - the queue we may want to return to the task just woken (depending on its - priority relative to the task this ISR interrupted. */ - if( xTaskWokenByPost || xAnotherTaskWokenByPost || xTaskWokenByTx ) - { - return pdTRUE; - } - else - { - return pdFALSE; - } -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, portCHAR *pcRxedChar, portTickType xBlockTime ) -{ - /* Get the next character from the buffer, note that this routine is only - called having checked that the is (at least) one to get */ - if( xQueueReceive( pxPort->xRxedChars, pcRxedChar, xBlockTime ) ) - { - return pdTRUE; - } - else - { - return pdFALSE; - } -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, portCHAR cOutChar, portTickType xBlockTime ) -{ - if( xQueueSend( pxPort->xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) - { - return pdFAIL; - } - - vInterruptOn( pxPort, serTRANSMIT_HOLD_EMPTY_INT ); - - return pdPASS; -} -/*-----------------------------------------------------------*/ - -void vSerialPutString( xComPortHandle pxPort, const portCHAR * const pcString, unsigned portSHORT usStringLength ) -{ -portCHAR * pcNextChar; -const portTickType xNoBlock = ( portTickType ) 0; - - /* Stop warnings. */ - ( void ) usStringLength; - - pcNextChar = ( portCHAR * ) pcString; - while( *pcNextChar ) - { - xSerialPutChar( pxPort, *pcNextChar, xNoBlock ); - pcNextChar++; - } -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xSerialWaitForSemaphore( xComPortHandle xPort ) -{ -const portTickType xBlockTime = ( portTickType ) 0xffff; - - /* This function does nothing interesting, but test the - semaphore from ISR mechanism. */ - return xSemaphoreTake( xPort->xTestSem, xBlockTime ); -} -/*-----------------------------------------------------------*/ - -void vSerialClose( xComPortHandle xPort ) -{ - portENTER_CRITICAL(); - - /* Turn off the interrupts. */ - portOUTPUT_BYTE( xPort->usModemCtrlReg, serNO_INTERRUPTS ); - portOUTPUT_BYTE( xPort->usInterruptEnableReg, serNO_INTERRUPTS ); - - /* Put back the original ISR. */ - _dos_setvect( xPort->usIRQVector, xOldISRs[ xPort->ucIRQ ] ); - - /* Remove the reference in the array of xComPort structures. */ - xPortStatus[ xPort->ucIRQ ] = NULL; - - /* Delete the queues. */ - vQueueDelete( xPort->xRxedChars ); - vQueueDelete( xPort->xCharsForTx ); - - vPortFree( ( void * ) xPort ); - - portEXIT_CRITICAL(); -} - diff --git a/Demo/PIC18_MPLAB/18f452.lkr b/Demo/PIC18_MPLAB/18f452.lkr deleted file mode 100644 index 3e844289c..000000000 --- a/Demo/PIC18_MPLAB/18f452.lkr +++ /dev/null @@ -1,24 +0,0 @@ -// $Id: 18f452.lkr,v 1.4 2003/03/13 05:02:23 sealep Exp $ -// File: 18f452.lkr -// Sample linker script for the PIC18F452 processor - -LIBPATH . - -FILES c018i.o -FILES clib.lib -FILES p18f452.lib - -CODEPAGE NAME=vectors START=0x0 END=0x39 PROTECTED -CODEPAGE NAME=page START=0x3A END=0x7FFF -CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED -CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED -CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED -CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED - -ACCESSBANK NAME=accessram START=0x0 END=0x7F -DATABANK NAME=BIG_BLOCK START=0x80 END=0x5FF -ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED - -SECTION NAME=CONFIG ROM=config - -STACK SIZE=0x60 RAM=BIG_BLOCK diff --git a/Demo/PIC18_MPLAB/FreeRTOSConfig.h b/Demo/PIC18_MPLAB/FreeRTOSConfig.h deleted file mode 100644 index 058c2eb4e..000000000 --- a/Demo/PIC18_MPLAB/FreeRTOSConfig.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -#include - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 ) -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 ) -#define configMINIMAL_STACK_SIZE ( 105 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) 1024 ) -#define configMAX_TASK_NAME_LEN ( 4 ) -#define configUSE_TRACE_FACILITY 0 -#define configUSE_16_BIT_TICKS 1 -#define configIDLE_SHOULD_YIELD 1 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 0 -#define INCLUDE_uxTaskPriorityGet 0 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 0 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/PIC18_MPLAB/ParTest/ParTest.c b/Demo/PIC18_MPLAB/ParTest/ParTest.c deleted file mode 100644 index 9ad3613a5..000000000 --- a/Demo/PIC18_MPLAB/ParTest/ParTest.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V2.0.0 - - + Use scheduler suspends in place of critical sections. -*/ - -#include "FreeRTOS.h" -#include "task.h" -#include "partest.h" - -/*----------------------------------------------------------- - * Simple parallel port IO routines for the FED 40pin demo board. - * The four LED's are connected to D4 to D7. - *-----------------------------------------------------------*/ - -#define partstBIT_AS_OUTPUT ( ( unsigned portSHORT ) 0 ) -#define partstSET_OUTPUT ( ( unsigned portSHORT ) 1 ) -#define partstCLEAR_OUTPUT ( ( unsigned portSHORT ) 0 ) - -#define partstENABLE_GENERAL_IO ( ( unsigned portCHAR ) 7 ) - -/*-----------------------------------------------------------*/ - -void vParTestInitialise( void ) -{ - /* Set the top four bits of port D to output. */ - TRISDbits.TRISD7 = partstBIT_AS_OUTPUT; - TRISDbits.TRISD6 = partstBIT_AS_OUTPUT; - TRISDbits.TRISD5 = partstBIT_AS_OUTPUT; - TRISDbits.TRISD4 = partstBIT_AS_OUTPUT; - - /* Start with all bits off. */ - PORTDbits.RD7 = partstCLEAR_OUTPUT; - PORTDbits.RD6 = partstCLEAR_OUTPUT; - PORTDbits.RD5 = partstCLEAR_OUTPUT; - PORTDbits.RD4 = partstCLEAR_OUTPUT; - - /* Enable the driver. */ - ADCON1 = partstENABLE_GENERAL_IO; - TRISEbits.TRISE2 = partstBIT_AS_OUTPUT; - PORTEbits.RE2 = partstSET_OUTPUT; -} -/*-----------------------------------------------------------*/ - -void vParTestSetLED( unsigned portBASE_TYPE uxLED, portBASE_TYPE xValue ) -{ - /* We are only using the top nibble, so LED 0 corresponds to bit 4. */ - vTaskSuspendAll(); - { - switch( uxLED ) - { - case 3 : PORTDbits.RD7 = ( portSHORT ) xValue; - break; - case 2 : PORTDbits.RD6 = ( portSHORT ) xValue; - break; - case 1 : PORTDbits.RD5 = ( portSHORT ) xValue; - break; - case 0 : PORTDbits.RD4 = ( portSHORT ) xValue; - break; - default : /* There are only 4 LED's. */ - break; - } - } - xTaskResumeAll(); -} -/*-----------------------------------------------------------*/ - -void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) -{ - /* We are only using the top nibble, so LED 0 corresponds to bit 4. */ - vTaskSuspendAll(); - { - switch( uxLED ) - { - case 3 : PORTDbits.RD7 = !( PORTDbits.RD7 ); - break; - case 2 : PORTDbits.RD6 = !( PORTDbits.RD6 ); - break; - case 1 : PORTDbits.RD5 = !( PORTDbits.RD5 ); - break; - case 0 : PORTDbits.RD4 = !( PORTDbits.RD4 ); - break; - default : /* There are only 4 LED's. */ - break; - } - } - xTaskResumeAll(); -} - - - diff --git a/Demo/PIC18_MPLAB/main1.c b/Demo/PIC18_MPLAB/main1.c deleted file mode 100644 index f45137763..000000000 --- a/Demo/PIC18_MPLAB/main1.c +++ /dev/null @@ -1,186 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * Instead of the normal single demo application, the PIC18F demo is split - * into several smaller programs of which this is the first. This enables the - * demo's to be executed on the RAM limited 40 pin devices. The 64 and 80 pin - * devices require a more costly development platform and are not so readily - * available. - * - * The RTOSDemo1 project is configured for a PIC18F452 device. Main1.c starts 5 - * tasks (including the idle task). - * - * The first task runs at the idle priority. It repeatedly performs a 32bit - * calculation and checks it's result against the expected value. This checks - * that the temporary storage utilised by the compiler to hold intermediate - * results does not get corrupted when the task gets switched in and out. See - * demo/common/minimal/integer.c for more information. - * - * The second and third tasks pass an incrementing value between each other on - * a message queue. See demo/common/minimal/PollQ.c for more information. - * - * Main1.c also creates a check task. This periodically checks that all the - * other tasks are still running and have not experienced any unexpected - * results. If all the other tasks are executing correctly an LED is flashed - * once every mainCHECK_PERIOD milliseconds. If any of the tasks have not - * executed, or report and error, the frequency of the LED flash will increase - * to mainERROR_FLASH_RATE. - * - * On entry to main an 'X' is transmitted. Monitoring the serial port using a - * dumb terminal allows for verification that the device is not continuously - * being reset (no more than one 'X' should be transmitted). - * - * http://www.FreeRTOS.org contains important information on the use of the - * PIC18F port. - */ - -/* -Changes from V2.0.0 - - + Delay periods are now specified using variables and constants of - portTickType rather than unsigned portLONG. -*/ - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Demo app include files. */ -#include "pollq.h" -#include "integer.h" -#include "partest.h" -#include "serial.h" - -/* The period between executions of the check task before and after an error -has been discovered. If an error has been discovered the check task runs -more frequently - increasing the LED flash rate. */ -#define mainNO_ERROR_CHECK_PERIOD ( ( portTickType ) 1000 / portTICK_RATE_MS ) -#define mainERROR_CHECK_PERIOD ( ( portTickType ) 100 / portTICK_RATE_MS ) - -/* Priority definitions for some of the tasks. Other tasks just use the idle -priority. */ -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) - -/* The LED that is flashed by the check task. */ -#define mainCHECK_TASK_LED ( 0 ) - -/* Constants required for the communications. Only one character is ever -transmitted. */ -#define mainCOMMS_QUEUE_LENGTH ( 5 ) -#define mainNO_BLOCK ( ( portTickType ) 0 ) -#define mainBAUD_RATE ( ( unsigned portLONG ) 9600 ) - -/* - * The task function for the "Check" task. - */ -static void vErrorChecks( void *pvParameters ); - -/* - * Checks the unique counts of other tasks to ensure they are still operational. - * Returns pdTRUE if an error is detected, otherwise pdFALSE. - */ -static portBASE_TYPE prvCheckOtherTasksAreStillRunning( void ); - -/*-----------------------------------------------------------*/ - -/* Creates the tasks, then starts the scheduler. */ -void main( void ) -{ - /* Initialise the required hardware. */ - vParTestInitialise(); - vPortInitialiseBlocks(); - - /* Send a character so we have some visible feedback of a reset. */ - xSerialPortInitMinimal( mainBAUD_RATE, mainCOMMS_QUEUE_LENGTH ); - xSerialPutChar( NULL, 'X', mainNO_BLOCK ); - - /* Start the standard demo tasks found in the demo\common directory. */ - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - - /* Start the check task defined in this file. */ - xTaskCreate( vErrorChecks, ( const portCHAR * const ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - - /* Start the scheduler. Will never return here. */ - vTaskStartScheduler(); -} -/*-----------------------------------------------------------*/ - -static void vErrorChecks( void *pvParameters ) -{ -portTickType xDelayTime = mainNO_ERROR_CHECK_PERIOD; -portBASE_TYPE xErrorOccurred; - - /* Cycle for ever, delaying then checking all the other tasks are still - operating without error. */ - for( ;; ) - { - /* Wait until it is time to check the other tasks. */ - vTaskDelay( xDelayTime ); - - /* Check all the other tasks are running, and running without ever - having an error. */ - xErrorOccurred = prvCheckOtherTasksAreStillRunning(); - - /* If an error was detected increase the frequency of the LED flash. */ - if( xErrorOccurred == pdTRUE ) - { - xDelayTime = mainERROR_CHECK_PERIOD; - } - - /* Flash the LED for visual feedback. */ - vParTestToggleLED( mainCHECK_TASK_LED ); - } -} -/*-----------------------------------------------------------*/ - -static portBASE_TYPE prvCheckOtherTasksAreStillRunning( void ) -{ -portBASE_TYPE xErrorHasOccurred = pdFALSE; - - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - xErrorHasOccurred = pdTRUE; - } - - if( xArePollingQueuesStillRunning() != pdTRUE ) - { - xErrorHasOccurred = pdTRUE; - } - - return xErrorHasOccurred; -} -/*-----------------------------------------------------------*/ - - diff --git a/Demo/PIC18_MPLAB/main2.c b/Demo/PIC18_MPLAB/main2.c deleted file mode 100644 index 67658893b..000000000 --- a/Demo/PIC18_MPLAB/main2.c +++ /dev/null @@ -1,161 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * Instead of the normal single demo application, the PIC18F demo is split - * into several smaller programs of which this is the second. This enables the - * demo's to be executed on the RAM limited 40 pin devices. The 64 and 80 pin - * devices require a more costly development platform and are not so readily - * available. - * - * The RTOSDemo2 project is configured for a PIC18F452 device. Main2.c starts - * 5 tasks (including the idle task). - * - * The first, second and third tasks do nothing but flash an LED. This gives - * visual feedback that everything is executing as expected. One task flashes - * an LED every 333ms (i.e. on and off every 333/2 ms), then next every 666ms - * and the last every 999ms. - * - * The last task runs at the idle priority. It repeatedly performs a 32bit - * calculation and checks it's result against the expected value. This checks - * that the temporary storage utilised by the compiler to hold intermediate - * results does not get corrupted when the task gets switched in and out. - * should the calculation ever provide an incorrect result the final LED is - * turned on. - * - * On entry to main() an 'X' is transmitted. Monitoring the serial port using a - * dumb terminal allows for verification that the device is not continuously - * being reset (no more than one 'X' should be transmitted). - * - * http://www.FreeRTOS.org contains important information on the use of the - * PIC18F port. - */ - -/* -Changes from V2.0.0 - - + Delay periods are now specified using variables and constants of - portTickType rather than unsigned portLONG. -*/ - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Demo app include files. */ -#include "flash.h" -#include "partest.h" -#include "serial.h" - -/* Priority definitions for the LED tasks. Other tasks just use the idle -priority. */ -#define mainLED_FLASH_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portBASE_TYPE ) 1 ) - -/* The LED that is lit when should the calculation fail. */ -#define mainCHECK_TASK_LED ( ( unsigned portBASE_TYPE ) 3 ) - -/* Constants required for the communications. Only one character is ever -transmitted. */ -#define mainCOMMS_QUEUE_LENGTH ( ( unsigned portBASE_TYPE ) 5 ) -#define mainNO_BLOCK ( ( portTickType ) 0 ) -#define mainBAUD_RATE ( ( unsigned portLONG ) 9600 ) - -/* - * The task that performs the 32 bit calculation at the idle priority. - */ -static void vCalculationTask( void *pvParameters ); - -/*-----------------------------------------------------------*/ - -/* Creates the tasks, then starts the scheduler. */ -void main( void ) -{ - /* Initialise the required hardware. */ - vParTestInitialise(); - vPortInitialiseBlocks(); - - /* Send a character so we have some visible feedback of a reset. */ - xSerialPortInitMinimal( mainBAUD_RATE, mainCOMMS_QUEUE_LENGTH ); - xSerialPutChar( NULL, 'X', mainNO_BLOCK ); - - /* Start the standard LED flash tasks as defined in demo/common/minimal. */ - vStartLEDFlashTasks( mainLED_FLASH_PRIORITY ); - - /* Start the check task defined in this file. */ - xTaskCreate( vCalculationTask, ( const portCHAR * const ) "Check", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); - - /* Start the scheduler. */ - vTaskStartScheduler(); -} -/*-----------------------------------------------------------*/ - -static void vCalculationTask( void *pvParameters ) -{ -volatile unsigned long ulCalculatedValue; /* Volatile to ensure optimisation is minimal. */ - - /* Continuously perform a calculation. If the calculation result is ever - incorrect turn the LED on. */ - for( ;; ) - { - /* A good optimising compiler would just remove all this! */ - ulCalculatedValue = 1234UL; - ulCalculatedValue *= 99UL; - - if( ulCalculatedValue != 122166UL ) - { - vParTestSetLED( mainCHECK_TASK_LED, pdTRUE ); - } - - ulCalculatedValue *= 9876UL; - - if( ulCalculatedValue != 1206511416UL ) - { - vParTestSetLED( mainCHECK_TASK_LED, pdTRUE ); - } - - ulCalculatedValue /= 15UL; - - if( ulCalculatedValue != 80434094UL ) - { - vParTestSetLED( mainCHECK_TASK_LED, pdTRUE ); - } - - ulCalculatedValue += 918273UL; - - if( ulCalculatedValue != 81352367UL ) - { - vParTestSetLED( mainCHECK_TASK_LED, pdTRUE ); - } - } -} -/*-----------------------------------------------------------*/ - diff --git a/Demo/PIC18_MPLAB/main3.c b/Demo/PIC18_MPLAB/main3.c deleted file mode 100644 index cb958a1f1..000000000 --- a/Demo/PIC18_MPLAB/main3.c +++ /dev/null @@ -1,190 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * THIS DEMO APPLICATION REQUIRES A LOOPBACK CONNECTOR TO BE FITTED TO THE PIC - * USART PORT - connect pin 2 to pin 3 on J2. - * - * Instead of the normal single demo application, the PIC18F demo is split - * into several smaller programs of which this is the third. This enables the - * demo's to be executed on the RAM limited 40 pin devices. The 64 and 80 pin - * devices require a more costly development platform and are not so readily - * available. - * - * The RTOSDemo3 project is configured for a PIC18F452 device. Main3.c starts - * 5 tasks (including the idle task). - * - * The first task repeatedly transmits a string of characters on the PIC USART - * port. The second task receives the characters, checking that the correct - * sequence is maintained (i.e. what is transmitted is identical to that - * received). Each transmitted and each received character causes an LED to - * flash. See demo/common/minimal/comtest. c for more information. - * - * The third task continuously performs a 32 bit calculation. This is a good - * test of the context switch mechanism as the 8 bit architecture requires - * the use of several file registers to perform the 32 bit operations. See - * demo/common/minimal/integer. c for more information. - * - * The third task is the check task. This periodically checks that the other - * tasks are still running and have not experienced any errors. If no errors - * have been reported by either the comms or integer tasks an LED is flashed - * with a frequency mainNO_ERROR_CHECK_PERIOD. If an error is discovered the - * frequency is increased to mainERROR_FLASH_RATE. - * - * The check task also provides a visual indication of a system reset by - * flashing the one remaining LED (mainRESET_LED) when it starts. After - * this initial flash mainRESET_LED should remain off. - * - * http://www.FreeRTOS.org contains important information on the use of the - * PIC18F port. - */ - -/* -Changes from V2.0.0 - - + Delay periods are now specified using variables and constants of - portTickType rather than unsigned portLONG. -*/ - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Demo app include files. */ -#include "partest.h" -#include "serial.h" -#include "comtest.h" -#include "integer.h" - -/* Priority definitions for the LED tasks. Other tasks just use the idle -priority. */ -#define mainCOMM_TEST_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portBASE_TYPE ) 2 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portBASE_TYPE ) 3 ) - -/* The period between executions of the check task before and after an error -has been discovered. If an error has been discovered the check task runs -more frequently - increasing the LED flash rate. */ -#define mainNO_ERROR_CHECK_PERIOD ( ( portTickType ) 1000 / portTICK_RATE_MS ) -#define mainERROR_CHECK_PERIOD ( ( portTickType ) 100 / portTICK_RATE_MS ) - -/* The period for which mainRESET_LED remain on every reset. */ -#define mainRESET_LED_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS ) - -/* The LED that is toggled whenever a character is transmitted. -mainCOMM_TX_RX_LED + 1 will be toggled every time a character is received. */ -#define mainCOMM_TX_RX_LED ( ( unsigned portBASE_TYPE ) 2 ) - -/* The LED that is flashed by the check task at a rate that indicates the -error status. */ -#define mainCHECK_TASK_LED ( ( unsigned portBASE_TYPE ) 1 ) - -/* The LED that is flashed once upon every reset. */ -#define mainRESET_LED ( ( unsigned portBASE_TYPE ) 0 ) - -/* Constants required for the communications. */ -#define mainCOMMS_QUEUE_LENGTH ( ( unsigned portBASE_TYPE ) 5 ) -#define mainBAUD_RATE ( ( unsigned portLONG ) 57600 ) -/*-----------------------------------------------------------*/ - -/* - * Task function which periodically checks the other tasks for errors. Flashes - * an LED at a rate that indicates whether an error has ever been detected. - */ -static void vErrorChecks( void *pvParameters ); - -/*-----------------------------------------------------------*/ - -/* Creates the tasks, then starts the scheduler. */ -void main( void ) -{ - /* Initialise the required hardware. */ - vParTestInitialise(); - - /* Initialise the block memory allocator. */ - vPortInitialiseBlocks(); - - /* Start the standard comtest tasks as defined in demo/common/minimal. */ - vAltStartComTestTasks( mainCOMM_TEST_PRIORITY, mainBAUD_RATE, mainCOMM_TX_RX_LED ); - - /* Start the standard 32bit calculation task as defined in - demo/common/minimal. */ - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - - /* Start the check task defined in this file. */ - xTaskCreate( vErrorChecks, ( const portCHAR * const ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - - /* Start the scheduler. This will never return. */ - vTaskStartScheduler(); -} -/*-----------------------------------------------------------*/ - -static void vErrorChecks( void *pvParameters ) -{ -portTickType xDelayTime = mainNO_ERROR_CHECK_PERIOD; -volatile unsigned portLONG ulDummy = 3UL; - - /* Toggle the LED so we can see when a reset occurs. */ - vParTestSetLED( mainRESET_LED, pdTRUE ); - vTaskDelay( mainRESET_LED_PERIOD ); - vParTestSetLED( mainRESET_LED, pdFALSE ); - - /* Cycle for ever, delaying then checking all the other tasks are still - operating without error. */ - for( ;; ) - { - /* Wait until it is time to check the other tasks. */ - vTaskDelay( xDelayTime ); - - /* Perform an integer calculation - just to ensure the registers - get used. The result is not important. */ - ulDummy *= 3UL; - - /* Check all the other tasks are running, and running without ever - having an error. The delay period is lowered if an error is reported, - causing the LED to flash at a higher rate. */ - if( xAreIntegerMathsTaskStillRunning() == pdFALSE ) - { - xDelayTime = mainERROR_CHECK_PERIOD; - } - - if( xAreComTestTasksStillRunning() == pdFALSE ) - { - xDelayTime = mainERROR_CHECK_PERIOD; - } - - /* Flash the LED for visual feedback. The rate of the flash will - indicate the health of the system. */ - vParTestToggleLED( mainCHECK_TASK_LED ); - } -} -/*-----------------------------------------------------------*/ - diff --git a/Demo/PIC18_MPLAB/makebin1.bat b/Demo/PIC18_MPLAB/makebin1.bat deleted file mode 100644 index 2e9132f61..000000000 --- a/Demo/PIC18_MPLAB/makebin1.bat +++ /dev/null @@ -1,3 +0,0 @@ -del rtosdemo.hex -copy rtosdemo1.hex rtosdemo.hex -hex2bin rtosdemo.hex diff --git a/Demo/PIC18_MPLAB/makebin2.bat b/Demo/PIC18_MPLAB/makebin2.bat deleted file mode 100644 index 9c4a7e56e..000000000 --- a/Demo/PIC18_MPLAB/makebin2.bat +++ /dev/null @@ -1,3 +0,0 @@ -del rtosdemo.hex -copy rtosdemo2.hex rtosdemo.hex -hex2bin rtosdemo.hex diff --git a/Demo/PIC18_MPLAB/makebin3.bat b/Demo/PIC18_MPLAB/makebin3.bat deleted file mode 100644 index 57db0de0e..000000000 --- a/Demo/PIC18_MPLAB/makebin3.bat +++ /dev/null @@ -1,3 +0,0 @@ -del rtosdemo.hex -copy rtosdemo3.hex rtosdemo.hex -hex2bin rtosdemo.hex diff --git a/Demo/PIC18_MPLAB/readme.txt b/Demo/PIC18_MPLAB/readme.txt deleted file mode 100644 index a46af4d5d..000000000 --- a/Demo/PIC18_MPLAB/readme.txt +++ /dev/null @@ -1,12 +0,0 @@ -Unfortunately the project files: - -RTOSDemo1.mcp -RTOSDemo2.mcp -and RTOSDemo3.mcp - -contain absolute paths. I don't know how to get around this, so if somebody knows, let me know! - -Edit the paths in a text editor before use. - -See the PIC port section of www.FreeRTOS.org for more information. - diff --git a/Demo/PIC18_MPLAB/rtosdemo.mcw b/Demo/PIC18_MPLAB/rtosdemo.mcw deleted file mode 100644 index 1b81b6c19..000000000 Binary files a/Demo/PIC18_MPLAB/rtosdemo.mcw and /dev/null differ diff --git a/Demo/PIC18_MPLAB/rtosdemo1.mcp b/Demo/PIC18_MPLAB/rtosdemo1.mcp deleted file mode 100644 index 3d84a0562..000000000 --- a/Demo/PIC18_MPLAB/rtosdemo1.mcp +++ /dev/null @@ -1,72 +0,0 @@ -[HEADER] -magic_cookie={66E99B07-E706-4689-9E80-9B2582898A13} -file_version=1.0 -[PATH_INFO] -dir_src= -dir_bin= -dir_tmp= -dir_sin= -dir_inc=D:\DevTools\mcc18\h;e:\dev\freertos\demo\common\include;e:\dev\freertos\source\include;e:\dev\freertos\source\portable\mplab\PIC18F;e:\dev\freertos\demo\PIC18_MPLAB -dir_lib=D:\DevTools\mcc18\lib -dir_lkr= -[CAT_FILTERS] -filter_src=*.asm;*.c -filter_inc=*.h;*.inc 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+0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V1.2.5 - - + Clear overrun errors in the Rx ISR. Overrun errors prevent any further - characters being received. - -Changes from V2.0.0 - - + Use portTickType in place of unsigned pdLONG for delay periods. - + cQueueReieveFromISR() used in place of xQueueReceive() in ISR. -*/ - -/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER. */ - -/* Scheduler header files. */ -#include "FreeRTOS.h" -#include "task.h" -#include "serial.h" -#include "queue.h" - -/* - * Prototypes for ISR's. The PIC architecture means that these functions - * have to be called from port.c. The prototypes are not however included - * in the header as the header is common to all ports. - */ -void vSerialTxISR( void ); -void vSerialRxISR( void ); - -/* Hardware pin definitions. */ -#define serTX_PIN TRISCbits.TRISC6 -#define serRX_PIN TRISCbits.TRISC7 - -/* Bit/register definitions. */ -#define serINPUT ( 1 ) -#define serOUTPUT ( 0 ) -#define serTX_ENABLE ( ( unsigned portSHORT ) 1 ) -#define serRX_ENABLE ( ( unsigned portSHORT ) 1 ) -#define serHIGH_SPEED ( ( unsigned portSHORT ) 1 ) -#define serCONTINUOUS_RX ( ( unsigned portSHORT ) 1 ) -#define serCLEAR_OVERRUN ( ( unsigned portSHORT ) 0 ) -#define serINTERRUPT_ENABLED ( ( unsigned portSHORT ) 1 ) -#define serINTERRUPT_DISABLED ( ( unsigned portSHORT ) 0 ) - -/* All ISR's use the PIC18 low priority interrupt. */ -#define serLOW_PRIORITY ( 0 ) - -/*-----------------------------------------------------------*/ - -/* Queues to interface between comms API and interrupt routines. */ -static xQueueHandle xRxedChars; -static xQueueHandle xCharsForTx; - -/*-----------------------------------------------------------*/ - -xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) -{ -unsigned portLONG ulBaud; - - /* Calculate the baud rate generator constant. - SPBRG = ( (FOSC / Desired Baud Rate) / 16 ) - 1 */ - ulBaud = configCPU_CLOCK_HZ / ulWantedBaud; - ulBaud /= ( unsigned portLONG ) 16; - ulBaud -= ( unsigned portLONG ) 1; - - /* Create the queues used by the ISR's to interface to tasks. */ - xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( portCHAR ) ); - xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( portCHAR ) ); - - portENTER_CRITICAL(); - { - /* Start with config registers cleared, so we can just set the wanted - bits. */ - TXSTA = ( unsigned portSHORT ) 0; - RCSTA = ( unsigned portSHORT ) 0; - - /* Set the baud rate generator using the above calculated constant. */ - SPBRG = ( unsigned portCHAR ) ulBaud; - - /* Setup the IO pins to enable the USART IO. */ - serTX_PIN = serOUTPUT; - serRX_PIN = serINPUT; - - /* Set the serial interrupts to use the same priority as the tick. */ - IPR1bits.TXIP = serLOW_PRIORITY; - IPR1bits.RCIP = serLOW_PRIORITY; - - /* Setup Tx configuration. */ - TXSTAbits.BRGH = serHIGH_SPEED; - TXSTAbits.TXEN = serTX_ENABLE; - - /* Setup Rx configuration. */ - RCSTAbits.SPEN = serRX_ENABLE; - RCSTAbits.CREN = serCONTINUOUS_RX; - - /* Enable the Rx interrupt now, the Tx interrupt will get enabled when - we have data to send. */ - PIE1bits.RCIE = serINTERRUPT_ENABLED; - } - portEXIT_CRITICAL(); - - /* Unlike other ports, this serial code does not allow for more than one - com port. We therefore don't return a pointer to a port structure and - can instead just return NULL. */ - return NULL; -} -/*-----------------------------------------------------------*/ - -xComPortHandle xSerialPortInit( eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits, unsigned portBASE_TYPE uxBufferLength ) -{ - /* This is not implemented in this port. - Use xSerialPortInitMinimal() instead. */ -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) -{ - /* Get the next character from the buffer. Return false if no characters - are available, or arrive before xBlockTime expires. */ - if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) - { - return pdTRUE; - } - else - { - return pdFALSE; - } -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) -{ - /* Return false if after the block time there is no room on the Tx queue. */ - if( xQueueSend( xCharsForTx, ( const void * ) &cOutChar, xBlockTime ) != pdPASS ) - { - return pdFAIL; - } - - /* Turn interrupt on - ensure the compiler only generates a single - instruction for this. */ - PIE1bits.TXIE = serINTERRUPT_ENABLED; - - return pdPASS; -} -/*-----------------------------------------------------------*/ - -void vSerialClose( xComPortHandle xPort ) -{ - /* Not implemented for this port. - To implement, turn off the interrupts and delete the memory - allocated to the queues. */ -} -/*-----------------------------------------------------------*/ - -#pragma interruptlow vSerialRxISR save=PRODH, PRODL, TABLAT, section(".tmpdata") -void vSerialRxISR( void ) -{ -portCHAR cChar; - - /* Get the character and post it on the queue of Rxed characters. - If the post causes a task to wake force a context switch as the woken task - may have a higher priority than the task we have interrupted. */ - cChar = RCREG; - - /* Clear any overrun errors. */ - if( RCSTAbits.OERR ) - { - RCSTAbits.CREN = serCLEAR_OVERRUN; - RCSTAbits.CREN = serCONTINUOUS_RX; - } - - if( xQueueSendFromISR( xRxedChars, ( const void * ) &cChar, pdFALSE ) ) - { - taskYIELD(); - } -} -/*-----------------------------------------------------------*/ - -#pragma interruptlow vSerialTxISR save=PRODH, PRODL, TABLAT, section(".tmpdata") -void vSerialTxISR( void ) -{ -portCHAR cChar, cTaskWoken; - - if( xQueueReceiveFromISR( xCharsForTx, &cChar, &cTaskWoken ) == pdTRUE ) - { - /* Send the next character queued for Tx. */ - TXREG = cChar; - } - else - { - /* Queue empty, nothing to send. */ - PIE1bits.TXIE = serINTERRUPT_DISABLED; - } -} - - - diff --git a/Demo/PIC18_WizC/Demo1/Demo1.PC b/Demo/PIC18_WizC/Demo1/Demo1.PC deleted file mode 100644 index 7dc2e20ac..000000000 --- a/Demo/PIC18_WizC/Demo1/Demo1.PC +++ /dev/null @@ -1,557 +0,0 @@ -[F29746990] -x=0 -y=122 -[F10478061] -x=0 -y=48 -[F15207742] -x=0 -y=48 -[F20376480] -x=0 -y=1332 -[F29843090] -x=5 -y=23 -[F20121086] -x=0 -y=84 -[F29765107] -x=31 -y=45 -[F29843242] -x=13 -y=8 -[F20539803] -x=0 -y=266 -[F15568046] -x=1 -y=293 -[F20441499] -x=0 -y=105 -[F20558577] -x=0 -y=4714 -[F20528681] -x=0 -y=44 -[ProjectGroup] -nFiles=1 -FileName0=Demo1.PC -[Project] -nFiles=3 -UseAD=0 -CompatOpts=0 -AutoHead= -IdentifierPrint=0 -TreePrint=0 -StatementResultPrint=0 -SourcePrint=0 -spoPrint=0 -AsmPrint=0 -CaseSens=1 -Optimise=45 -AProcFreq=40000000 -LOptBytes=16 -LOptBytesReg=6 -TopROM=32767 -StackPointer=3839 -HeapPointer=3584 -HasDoneOptionDialog=1 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of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V3.0.0 - + TickRate reduced to 250Hz. - - + configIDLE_SHOULD_YIELD added. - -Changes from V3.0.1 -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION ( 1 ) -#define configUSE_IDLE_HOOK ( 0 ) -#define configUSE_TICK_HOOK ( 0 ) -#define configTICK_RATE_HZ ( 250 ) -#define configMAX_PRIORITIES ( 1 ) -#define configMINIMAL_STACK_SIZE portMINIMAL_STACK_SIZE -#define configMAX_TASK_NAME_LEN ( 3 ) -#define configUSE_TRACE_FACILITY ( 0 ) -#define configUSE_16_BIT_TICKS ( 1 ) -#define configIDLE_SHOULD_YIELD ( 1 ) - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the component, or zero -to exclude the component. */ - -/* Include/exclude the stated API function. */ -#define INCLUDE_vTaskPrioritySet ( 0 ) -#define INCLUDE_uxTaskPriorityGet ( 0 ) -#define INCLUDE_vTaskDelete ( 0 ) -#define INCLUDE_vTaskCleanUpResources ( 0 ) -#define INCLUDE_vTaskSuspend ( 0 ) -#define INCLUDE_vTaskDelayUntil ( 1 ) -#define INCLUDE_vTaskDelay ( 0 ) - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/PIC18_WizC/Demo1/MallocConfig.h b/Demo/PIC18_WizC/Demo1/MallocConfig.h deleted file mode 100644 index 195258b51..000000000 --- a/Demo/PIC18_WizC/Demo1/MallocConfig.h +++ /dev/null @@ -1,41 +0,0 @@ -#ifndef _MALLOC_SETTINGS_H -#define _MALLOC_SETTINGS_H -/********************************************************************* -** Title: Dynamic memory (de-)allocation library for wizC. -** -** Author: Marcel van Lieshout -** -** Copyright: (c) 2005, HMCS, Marcel van Lieshout -** -** License: This software is released to the public domain and comes -** without warranty and/or guarantees of any kind. You have -** the right to use, copy, modify and/or (re-)distribute the -** software as long as the reference to the author is -** maintained in the software and a reference to the author -** is included in any documentation of each product in which -** this library (in it's original or in a modified form) -** is used. -*********************************************************************/ - -/********************************************************************* -** The model to use -*********************************************************************/ -//#define MALLOC_SMALL -#define MALLOC_LARGE - -/********************************************************************* -** The size of the heap -*********************************************************************/ -#define MALLOC_HEAP_SIZE (3200) - -/********************************************************************* -** Should released memory be scribbled with 0x55 before releasing it? -*********************************************************************/ -//#define MALLOC_SCRIBBLE - -/******************************************************************** -** Enable Debug-mode? -*********************************************************************/ -//#define MALLOC_DEBUG - -#endif /* _MALLOC_SETTINGS_H */ diff --git a/Demo/PIC18_WizC/Demo1/WIZCmake.h b/Demo/PIC18_WizC/Demo1/WIZCmake.h deleted file mode 100644 index e7c94797c..000000000 --- a/Demo/PIC18_WizC/Demo1/WIZCmake.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V3.0.0 - + Several modules predefined to avoid linker problems - -Changes from V3.0.1 -*/ - -#ifndef _memcpy - #define _memcpy 1 -#endif - -#ifndef _memset - #define _memset 1 -#endif - -#ifndef _strncpy - #define _strncpy 1 -#endif diff --git a/Demo/PIC18_WizC/Demo1/fuses.c b/Demo/PIC18_WizC/Demo1/fuses.c deleted file mode 100644 index a352d48f5..000000000 --- a/Demo/PIC18_WizC/Demo1/fuses.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V3.0.0 - -Changes from V3.0.1 -*/ - -/* -** Here are the configuration words set. See the PIC datasheet -** and the wizC manual for an explanation -*/ -#include - -/* -** These fuses are for PIC18F4620 -*/ -#pragma __config _CONFIG1H,_IESO_OFF_1H & _FCMEN_OFF_1H & _OSC_HSPLL_1H -#pragma __config _CONFIG2L,_BORV_21_2L & _BOREN_SBORDIS_2L & _PWRT_ON_2L -#pragma __config _CONFIG2H,_WDTPS_32768_2H & _WDT_OFF_2H -#pragma __config _CONFIG3H,_MCLRE_ON_3H & _LPT1OSC_OFF_3H & _PBADEN_OFF_3H & _CCP2MX_PORTC_3H -#pragma __config _CONFIG4L,_DEBUG_OFF_4L & _XINST_OFF_4L & _LVP_OFF_4L & _STVREN_OFF_4L -#pragma __config _CONFIG5L,_CP3_OFF_5L & _CP2_OFF_5L & _CP1_OFF_5L & _CP0_OFF_5L -#pragma __config _CONFIG5H,_CPD_OFF_5H & _CPB_OFF_5H -#pragma __config _CONFIG6L,_WRT3_OFF_6L & _WRT2_OFF_6L & _WRT1_OFF_6L & _WRT0_OFF_6L -#pragma __config _CONFIG6H,_WRTD_OFF_6H & _WRTB_OFF_6H & _WRTC_OFF_6H -#pragma __config _CONFIG7L,_EBTR3_OFF_7L & _EBTR2_OFF_7L & _EBTR1_OFF_7L & _EBTR0_OFF_7L -#pragma __config _CONFIG7H,_EBTRB_OFF_7H diff --git a/Demo/PIC18_WizC/Demo1/interrupt.c b/Demo/PIC18_WizC/Demo1/interrupt.c deleted file mode 100644 index 6a4293302..000000000 --- a/Demo/PIC18_WizC/Demo1/interrupt.c +++ /dev/null @@ -1,109 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V3.0.0 - + Added functionality to only call vTaskSwitchContext() once - when handling multiple interruptsources in a single interruptcall. - - + Included Filenames changed to a .c extension to allow stepping through - code using F7. - -Changes from V3.0.1 -*/ - -#include - -/* Scheduler include files. */ -#include -#include -#include - -static bit uxSwitchRequested; - -/* - * Vector for the ISR. - */ -void pointed Interrupt() -{ - /* - * Save the context of the current task. - */ - portSAVE_CONTEXT( portINTERRUPTS_FORCED ); - - /* - * No contextswitch requested yet - */ - uxSwitchRequested = pdFALSE; - - /* - * Was the interrupt the FreeRTOS SystemTick? - */ - #include - -/******************************************************************************* -** DO NOT MODIFY ANYTHING ABOVE THIS LINE -******************************************************************************** -** Enter the includes for the ISR-code of the FreeRTOS drivers below. -** -** You cannot use local variables. Alternatives are: -** - Use static variables (Global RAM usage increases) -** - Call a function (Additional cycles are needed) -** - Use unused SFR's (preferred, no additional overhead) -** See "../Serial/isrSerialTx.c" for an example of this last option -*******************************************************************************/ - - - - - - - -/******************************************************************************* -** DO NOT MODIFY ANYTHING BELOW THIS LINE -*******************************************************************************/ - /* - * Was a contextswitch requested by one of the - * interrupthandlers? - */ - if ( uxSwitchRequested ) - { - vTaskSwitchContext(); - } - - /* - * Restore the context of the (possibly other) task. - */ - portRESTORE_CONTEXT(); - - #pragma asmline retfie 0 -} diff --git a/Demo/PIC18_WizC/Demo1/main.c b/Demo/PIC18_WizC/Demo1/main.c deleted file mode 100644 index badb0a6af..000000000 --- a/Demo/PIC18_WizC/Demo1/main.c +++ /dev/null @@ -1,202 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V3.0.0 - -Changes from V3.0.1 -*/ - -/* - * Instead of the normal single demo application, the PIC18F demo is split - * into several smaller programs of which this is the first. This enables the - * demo's to be executed on the RAM limited PIC-devices. - * - * The Demo1 project is configured for a PIC18F4620 device. Main.c starts 9 - * tasks (including the idle task). - - * This first demo is included to do a quick check on the FreeRTOS - * installation. It is also included to demonstrate a minimal project-setup - * to use FreeRTOS in a wizC environment. - * - * Eight independant tasks are created. All tasks share the same taskcode. - * Each task blinks a different led on portB. The blinkrate for each task - * is different, but chosen in such a way that portB will show a binary - * counter pattern. All blinkrates are derived from a single master-rate. - * By default, this masterrate is set to 100 milliseconds. Although such - * a low value will make it almost impossible to see some of the leds - * actually blink, it is a good value when using the wizC-simulator. - * When testing on a real chip, changing the value to eg. 500 milliseconds - * would be appropiate. - */ - -/* Scheduler include files. */ -#include -#include - -#define mainBLINK_LED_INTERVAL ( ( portTickType ) 100 / ( portTICK_RATE_MS ) ) - -/* The LED that is flashed by the B0 task. */ -#define mainBLINK_LED0_PORT LATD -#define mainBLINK_LED0_TRIS TRISD -#define mainBLINK_LED0_PIN 0 -#define mainBLINK_LED0_INTERVAL ((mainBLINK_LED_INTERVAL) << (mainBLINK_LED0_PIN)) - -/* The LED that is flashed by the B1 task. */ -#define mainBLINK_LED1_PORT LATD -#define mainBLINK_LED1_TRIS TRISD -#define mainBLINK_LED1_PIN 1 -#define mainBLINK_LED1_INTERVAL ((mainBLINK_LED_INTERVAL) << (mainBLINK_LED1_PIN)) - -/* The LED that is flashed by the B2 task. */ -#define mainBLINK_LED2_PORT LATD -#define mainBLINK_LED2_TRIS TRISD -#define mainBLINK_LED2_PIN 2 -#define mainBLINK_LED2_INTERVAL ((mainBLINK_LED_INTERVAL) << (mainBLINK_LED2_PIN)) - -/* The LED that is flashed by the B3 task. */ -#define mainBLINK_LED3_PORT LATD -#define mainBLINK_LED3_TRIS TRISD -#define mainBLINK_LED3_PIN 3 -#define mainBLINK_LED3_INTERVAL ((mainBLINK_LED_INTERVAL) << (mainBLINK_LED3_PIN)) - -/* The LED that is flashed by the B4 task. */ -#define mainBLINK_LED4_PORT LATD -#define mainBLINK_LED4_TRIS TRISD -#define mainBLINK_LED4_PIN 4 -#define mainBLINK_LED4_INTERVAL ((mainBLINK_LED_INTERVAL) << (mainBLINK_LED4_PIN)) - -/* The LED that is flashed by the B5 task. */ -#define mainBLINK_LED5_PORT LATD -#define mainBLINK_LED5_TRIS TRISD -#define mainBLINK_LED5_PIN 5 -#define mainBLINK_LED5_INTERVAL ((mainBLINK_LED_INTERVAL) << (mainBLINK_LED5_PIN)) - -/* The LED that is flashed by the B6 task. */ -#define mainBLINK_LED6_PORT LATD -#define mainBLINK_LED6_TRIS TRISD -#define mainBLINK_LED6_PIN 6 -#define mainBLINK_LED6_INTERVAL ((mainBLINK_LED_INTERVAL) << (mainBLINK_LED6_PIN)) - -/* The LED that is flashed by the B7 task. */ -#define mainBLINK_LED7_PORT LATD -#define mainBLINK_LED7_TRIS TRISD -#define mainBLINK_LED7_PIN 7 -#define mainBLINK_LED7_INTERVAL ((mainBLINK_LED_INTERVAL) << (mainBLINK_LED7_PIN)) - -typedef struct { - unsigned char *port; - unsigned char *tris; - unsigned char pin; - portTickType interval; -} SBLINK; - -const SBLINK sled0 = {&mainBLINK_LED0_PORT, &mainBLINK_LED0_TRIS, mainBLINK_LED0_PIN, mainBLINK_LED0_INTERVAL}; -const SBLINK sled1 = {&mainBLINK_LED1_PORT, &mainBLINK_LED1_TRIS, mainBLINK_LED1_PIN, mainBLINK_LED1_INTERVAL}; -const SBLINK sled2 = {&mainBLINK_LED2_PORT, &mainBLINK_LED2_TRIS, mainBLINK_LED2_PIN, mainBLINK_LED2_INTERVAL}; -const SBLINK sled3 = {&mainBLINK_LED3_PORT, &mainBLINK_LED3_TRIS, mainBLINK_LED3_PIN, mainBLINK_LED3_INTERVAL}; -const SBLINK sled4 = {&mainBLINK_LED4_PORT, &mainBLINK_LED4_TRIS, mainBLINK_LED4_PIN, mainBLINK_LED4_INTERVAL}; -const SBLINK sled5 = {&mainBLINK_LED5_PORT, &mainBLINK_LED5_TRIS, mainBLINK_LED5_PIN, mainBLINK_LED5_INTERVAL}; -const SBLINK sled6 = {&mainBLINK_LED6_PORT, &mainBLINK_LED6_TRIS, mainBLINK_LED6_PIN, mainBLINK_LED6_INTERVAL}; -const SBLINK sled7 = {&mainBLINK_LED7_PORT, &mainBLINK_LED7_TRIS, mainBLINK_LED7_PIN, mainBLINK_LED7_INTERVAL}; - -/* - * The task code for the "vBlink" task. - */ -static portTASK_FUNCTION_PROTO(vBlink, pvParameters); - -/*-----------------------------------------------------------*/ - -/* - * Creates the tasks, then starts the scheduler. - */ -void main( void ) -{ - /* - * Start the blink tasks defined in this file. - */ - xTaskCreate( vBlink, "B0", configMINIMAL_STACK_SIZE, &sled0, tskIDLE_PRIORITY, NULL ); - xTaskCreate( vBlink, "B1", configMINIMAL_STACK_SIZE, &sled1, tskIDLE_PRIORITY, NULL ); - xTaskCreate( vBlink, "B2", configMINIMAL_STACK_SIZE, &sled2, tskIDLE_PRIORITY, NULL ); - xTaskCreate( vBlink, "B3", configMINIMAL_STACK_SIZE, &sled3, tskIDLE_PRIORITY, NULL ); - xTaskCreate( vBlink, "B4", configMINIMAL_STACK_SIZE, &sled4, tskIDLE_PRIORITY, NULL ); - xTaskCreate( vBlink, "B5", configMINIMAL_STACK_SIZE, &sled5, tskIDLE_PRIORITY, NULL ); - xTaskCreate( vBlink, "B6", configMINIMAL_STACK_SIZE, &sled6, tskIDLE_PRIORITY, NULL ); - xTaskCreate( vBlink, "B7", configMINIMAL_STACK_SIZE, &sled7, tskIDLE_PRIORITY, NULL ); - - /* - * Start the scheduler. - */ - vTaskStartScheduler( ); - - while(1) /* This point should never be reached. */ - { - } -} -/*-----------------------------------------------------------*/ - -static portTASK_FUNCTION(vBlink, pvParameters) -{ - unsigned char *Port = ((SBLINK *)pvParameters)->port; - unsigned char *Tris = ((SBLINK *)pvParameters)->tris; - unsigned char Pin = ((SBLINK *)pvParameters)->pin; - portTickType Interval = ((SBLINK *)pvParameters)->interval; - - portTickType xLastWakeTime; - - /* - * Initialize the hardware - */ - *Tris &= ~(1< diff --git a/Demo/PIC18_WizC/Demo2/fuses.c b/Demo/PIC18_WizC/Demo2/fuses.c deleted file mode 100644 index a352d48f5..000000000 --- a/Demo/PIC18_WizC/Demo2/fuses.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V3.0.0 - -Changes from V3.0.1 -*/ - -/* -** Here are the configuration words set. See the PIC datasheet -** and the wizC manual for an explanation -*/ -#include - -/* -** These fuses are for PIC18F4620 -*/ -#pragma __config _CONFIG1H,_IESO_OFF_1H & _FCMEN_OFF_1H & _OSC_HSPLL_1H -#pragma __config _CONFIG2L,_BORV_21_2L & _BOREN_SBORDIS_2L & _PWRT_ON_2L -#pragma __config _CONFIG2H,_WDTPS_32768_2H & _WDT_OFF_2H -#pragma __config _CONFIG3H,_MCLRE_ON_3H & _LPT1OSC_OFF_3H & _PBADEN_OFF_3H & _CCP2MX_PORTC_3H -#pragma __config _CONFIG4L,_DEBUG_OFF_4L & _XINST_OFF_4L & _LVP_OFF_4L & _STVREN_OFF_4L -#pragma __config _CONFIG5L,_CP3_OFF_5L & _CP2_OFF_5L & _CP1_OFF_5L & _CP0_OFF_5L -#pragma __config _CONFIG5H,_CPD_OFF_5H & _CPB_OFF_5H -#pragma __config _CONFIG6L,_WRT3_OFF_6L & _WRT2_OFF_6L & _WRT1_OFF_6L & _WRT0_OFF_6L -#pragma __config _CONFIG6H,_WRTD_OFF_6H & _WRTB_OFF_6H & _WRTC_OFF_6H -#pragma __config _CONFIG7L,_EBTR3_OFF_7L & _EBTR2_OFF_7L & _EBTR1_OFF_7L & _EBTR0_OFF_7L -#pragma __config _CONFIG7H,_EBTRB_OFF_7H diff --git a/Demo/PIC18_WizC/Demo2/interrupt.c b/Demo/PIC18_WizC/Demo2/interrupt.c deleted file mode 100644 index 1d41c8c28..000000000 --- a/Demo/PIC18_WizC/Demo2/interrupt.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V3.0.0 - + Added functionality to only call vTaskSwitchContext() once - when handling multiple interruptsources in a single interruptcall. - - + Included Filenames changed to a .c extension to allow stepping through - code using F7. - -Changes from V3.0.1 -*/ - -#include - -/* Scheduler include files. */ -#include -#include -#include - -static bit uxSwitchRequested; - -/* - * Vector for the ISR. - */ -void pointed Interrupt() -{ - /* - * Save the context of the current task. - */ - portSAVE_CONTEXT( portINTERRUPTS_FORCED ); - - /* - * No contextswitch requested yet - */ - uxSwitchRequested = pdFALSE; - - /* - * Was the interrupt the FreeRTOS SystemTick? - */ - #include - -/******************************************************************************* -** DO NOT MODIFY ANYTHING ABOVE THIS LINE -******************************************************************************** -** Enter the includes for the ISR-code of the FreeRTOS drivers below. -** -** You cannot use local variables. Alternatives are: -** - Use static variables (Global RAM usage increases) -** - Call a function (Additional cycles are needed) -** - Use unused SFR's (preferred, no additional overhead) -** See "../Serial/isrSerialTx.c" for an example of this last option -*******************************************************************************/ - - - - /* - * Was the interrupt a byte being received? - */ - #include "../Serial/isrSerialRx.c" - - - /* - * Was the interrupt the Tx register becoming empty? - */ - #include "../Serial/isrSerialTx.c" - - - -/******************************************************************************* -** DO NOT MODIFY ANYTHING BELOW THIS LINE -*******************************************************************************/ - /* - * Was a contextswitch requested by one of the - * interrupthandlers? - */ - if ( uxSwitchRequested ) - { - vTaskSwitchContext(); - } - - /* - * Restore the context of the (possibly other) task. - */ - portRESTORE_CONTEXT(); - - #pragma asmline retfie 0 -} diff --git a/Demo/PIC18_WizC/Demo2/main.c b/Demo/PIC18_WizC/Demo2/main.c deleted file mode 100644 index 68cf8c974..000000000 --- a/Demo/PIC18_WizC/Demo2/main.c +++ /dev/null @@ -1,198 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V3.0.0 - -Changes from V3.0.1 -*/ - -/* - * Instead of the normal single demo application, the PIC18F demo is split - * into several smaller programs of which this is the second. This enables the - * demo's to be executed on the RAM limited PIC-devices. - * - * The Demo2 project is configured for a PIC18F4620 device. Main.c starts 12 - * tasks (including the idle task). See the indicated files in the demo/common - * directory for more information. - * - * demo/common/minimal/integer.c: Creates 1 task - * demo/common/minimal/PollQ.c: Creates 2 tasks - * demo/common/minimal/semtest.c: Creates 4 tasks - * demo/common/minimal/flash.c: Creates 3 tasks - * - * Main.c also creates a check task. This periodically checks that all the - * other tasks are still running and have not experienced any unexpected - * results. If all the other tasks are executing correctly an LED is flashed - * once every mainCHECK_PERIOD milliseconds. If any of the tasks have not - * executed, or report an error, the frequency of the LED flash will increase - * to mainERROR_FLASH_RATE. - * - * On entry to main an 'X' is transmitted. Monitoring the serial port using a - * dumb terminal allows for verification that the device is not continuously - * being reset (no more than one 'X' should be transmitted). - * - * http://www.FreeRTOS.org contains important information on the use of the - * wizC PIC18F port. - */ - -/* Scheduler include files. */ -#include -#include - -/* Demo app include files. */ -#include "integer.h" -#include "pollq.h" -#include "semtest.h" -#include "flash.h" -#include "partest.h" -#include "serial.h" - -/* The period between executions of the check task before and after an error -has been discovered. If an error has been discovered the check task runs -more frequently - increasing the LED flash rate. */ -#define mainNO_ERROR_CHECK_PERIOD ( ( portTickType ) 10000 / portTICK_RATE_MS ) -#define mainERROR_CHECK_PERIOD ( ( portTickType ) 1000 / portTICK_RATE_MS ) -#define mainCHECK_TASK_LED ( ( unsigned portCHAR ) 3 ) - -/* Priority definitions for some of the tasks. Other tasks just use the idle -priority. */ -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 3 ) -#define mainLED_FLASH_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 2 ) -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 1 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 1 ) -#define mainINTEGER_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 0 ) - -/* Constants required for the communications. Only one character is ever -transmitted. */ -#define mainCOMMS_QUEUE_LENGTH ( ( unsigned portCHAR ) 5 ) -#define mainNO_BLOCK ( ( portTickType ) 0 ) -#define mainBAUD_RATE ( ( unsigned portLONG ) 57600 ) - -/* - * The task function for the "Check" task. - */ -static portTASK_FUNCTION_PROTO( vErrorChecks, pvParameters ); - -/* - * Checks the unique counts of other tasks to ensure they are still operational. - * Returns pdTRUE if an error is detected, otherwise pdFALSE. - */ -static portCHAR prvCheckOtherTasksAreStillRunning( void ); - -/*-----------------------------------------------------------*/ - -/* Creates the tasks, then starts the scheduler. */ -void main( void ) -{ - /* Initialise the required hardware. */ - vParTestInitialise(); - - /* Send a character so we have some visible feedback of a reset. */ - xSerialPortInitMinimal( mainBAUD_RATE, mainCOMMS_QUEUE_LENGTH ); - xSerialPutChar( NULL, 'X', mainNO_BLOCK ); - - /* Start a few of the standard demo tasks found in the demo\common directory. */ - vStartIntegerMathTasks( mainINTEGER_PRIORITY); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartLEDFlashTasks( mainLED_FLASH_PRIORITY ); - - /* Start the check task defined in this file. */ - xTaskCreate( vErrorChecks, ( const portCHAR * const ) "Check", portMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - - /* Start the scheduler. Will never return here. */ - vTaskStartScheduler(); - - while(1) /* This point should never be reached. */ - { - } -} -/*-----------------------------------------------------------*/ - -static portTASK_FUNCTION( vErrorChecks, pvParameters ) -{ -portTickType xLastCheckTime; -portTickType xDelayTime = mainNO_ERROR_CHECK_PERIOD; -portCHAR cErrorOccurred; - - /* We need to initialise xLastCheckTime prior to the first call to - vTaskDelayUntil(). */ - xLastCheckTime = xTaskGetTickCount(); - - /* Cycle for ever, delaying then checking all the other tasks are still - operating without error. */ - for( ;; ) - { - /* Wait until it is time to check the other tasks again. */ - vTaskDelayUntil( &xLastCheckTime, xDelayTime ); - - /* Check all the other tasks are running, and running without ever - having an error. */ - cErrorOccurred = prvCheckOtherTasksAreStillRunning(); - - /* If an error was detected increase the frequency of the LED flash. */ - if( cErrorOccurred == pdTRUE ) - { - xDelayTime = mainERROR_CHECK_PERIOD; - } - - /* Flash the LED for visual feedback. */ - vParTestToggleLED( mainCHECK_TASK_LED ); - } -} -/*-----------------------------------------------------------*/ - -static portCHAR prvCheckOtherTasksAreStillRunning( void ) -{ - portCHAR cErrorHasOccurred = ( portCHAR ) pdFALSE; - - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - cErrorHasOccurred = ( portCHAR ) pdTRUE; - } - - if( xArePollingQueuesStillRunning() != pdTRUE ) - { - cErrorHasOccurred = ( portCHAR ) pdTRUE; - } - - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - cErrorHasOccurred = ( portCHAR ) pdTRUE; - } - - return cErrorHasOccurred; -} -/*-----------------------------------------------------------*/ - - diff --git a/Demo/PIC18_WizC/Demo3/Demo3.PC b/Demo/PIC18_WizC/Demo3/Demo3.PC deleted file mode 100644 index 1fed171da..000000000 --- a/Demo/PIC18_WizC/Demo3/Demo3.PC +++ /dev/null @@ -1,503 +0,0 @@ -[F29011781] -x=0 -y=118 -[F29216334] -x=0 -y=189 -[F15207742] -x=0 -y=48 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option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V3.0.0 - + TickRate reduced to 250Hz. - - + configIDLE_SHOULD_YIELD added. - -Changes from V3.0.1 -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION ( 1 ) -#define configUSE_IDLE_HOOK ( 0 ) -#define configUSE_TICK_HOOK ( 0 ) -#define configTICK_RATE_HZ ( 250 ) -#define configMAX_PRIORITIES ( 4 ) -#define configMINIMAL_STACK_SIZE portMINIMAL_STACK_SIZE -#define configMAX_TASK_NAME_LEN ( 3 ) -#define configUSE_TRACE_FACILITY ( 0 ) -#define configUSE_16_BIT_TICKS ( 1 ) -#define configIDLE_SHOULD_YIELD ( 1 ) - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the component, or zero -to exclude the component. */ - -/* Include/exclude the stated API function. */ -#define INCLUDE_vTaskPrioritySet ( 0 ) -#define INCLUDE_uxTaskPriorityGet ( 0 ) -#define INCLUDE_vTaskDelete ( 0 ) -#define INCLUDE_vTaskCleanUpResources ( 0 ) -#define INCLUDE_vTaskSuspend ( 0 ) -#define INCLUDE_vTaskDelayUntil ( 1 ) -#define INCLUDE_vTaskDelay ( 0 ) - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/PIC18_WizC/Demo3/MallocConfig.h b/Demo/PIC18_WizC/Demo3/MallocConfig.h deleted file mode 100644 index 195258b51..000000000 --- a/Demo/PIC18_WizC/Demo3/MallocConfig.h +++ /dev/null @@ -1,41 +0,0 @@ -#ifndef _MALLOC_SETTINGS_H -#define _MALLOC_SETTINGS_H -/********************************************************************* -** Title: Dynamic memory (de-)allocation library for wizC. -** -** Author: Marcel van Lieshout -** -** Copyright: (c) 2005, HMCS, Marcel van Lieshout -** -** License: This software is released to the public domain and comes -** without warranty and/or guarantees of any kind. You have -** the right to use, copy, modify and/or (re-)distribute the -** software as long as the reference to the author is -** maintained in the software and a reference to the author -** is included in any documentation of each product in which -** this library (in it's original or in a modified form) -** is used. -*********************************************************************/ - -/********************************************************************* -** The model to use -*********************************************************************/ -//#define MALLOC_SMALL -#define MALLOC_LARGE - -/********************************************************************* -** The size of the heap -*********************************************************************/ -#define MALLOC_HEAP_SIZE (3200) - -/********************************************************************* -** Should released memory be scribbled with 0x55 before releasing it? -*********************************************************************/ -//#define MALLOC_SCRIBBLE - -/******************************************************************** -** Enable Debug-mode? -*********************************************************************/ -//#define MALLOC_DEBUG - -#endif /* _MALLOC_SETTINGS_H */ diff --git a/Demo/PIC18_WizC/Demo3/WIZCmake.h b/Demo/PIC18_WizC/Demo3/WIZCmake.h deleted file mode 100644 index f1225c62e..000000000 --- a/Demo/PIC18_WizC/Demo3/WIZCmake.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V3.0.0 - + Several modules predefined to avoid linker problems - -Changes from V3.0.1 -*/ - -#ifndef _memcpy - #define _memcpy 1 -#endif - -#ifndef _memset - #define _memset 1 -#endif - -#ifndef _strncpy - #define _strncpy 1 -#endif - - -#pragma wizcpp searchpath <../../Common/Include/> diff --git a/Demo/PIC18_WizC/Demo3/fuses.c b/Demo/PIC18_WizC/Demo3/fuses.c deleted file mode 100644 index a352d48f5..000000000 --- a/Demo/PIC18_WizC/Demo3/fuses.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V3.0.0 - -Changes from V3.0.1 -*/ - -/* -** Here are the configuration words set. See the PIC datasheet -** and the wizC manual for an explanation -*/ -#include - -/* -** These fuses are for PIC18F4620 -*/ -#pragma __config _CONFIG1H,_IESO_OFF_1H & _FCMEN_OFF_1H & _OSC_HSPLL_1H -#pragma __config _CONFIG2L,_BORV_21_2L & _BOREN_SBORDIS_2L & _PWRT_ON_2L -#pragma __config _CONFIG2H,_WDTPS_32768_2H & _WDT_OFF_2H -#pragma __config _CONFIG3H,_MCLRE_ON_3H & _LPT1OSC_OFF_3H & _PBADEN_OFF_3H & _CCP2MX_PORTC_3H -#pragma __config _CONFIG4L,_DEBUG_OFF_4L & _XINST_OFF_4L & _LVP_OFF_4L & _STVREN_OFF_4L -#pragma __config _CONFIG5L,_CP3_OFF_5L & _CP2_OFF_5L & _CP1_OFF_5L & _CP0_OFF_5L -#pragma __config _CONFIG5H,_CPD_OFF_5H & _CPB_OFF_5H -#pragma __config _CONFIG6L,_WRT3_OFF_6L & _WRT2_OFF_6L & _WRT1_OFF_6L & _WRT0_OFF_6L -#pragma __config _CONFIG6H,_WRTD_OFF_6H & _WRTB_OFF_6H & _WRTC_OFF_6H -#pragma __config _CONFIG7L,_EBTR3_OFF_7L & _EBTR2_OFF_7L & _EBTR1_OFF_7L & _EBTR0_OFF_7L -#pragma __config _CONFIG7H,_EBTRB_OFF_7H diff --git a/Demo/PIC18_WizC/Demo3/interrupt.c b/Demo/PIC18_WizC/Demo3/interrupt.c deleted file mode 100644 index 1d41c8c28..000000000 --- a/Demo/PIC18_WizC/Demo3/interrupt.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V3.0.0 - + Added functionality to only call vTaskSwitchContext() once - when handling multiple interruptsources in a single interruptcall. - - + Included Filenames changed to a .c extension to allow stepping through - code using F7. - -Changes from V3.0.1 -*/ - -#include - -/* Scheduler include files. */ -#include -#include -#include - -static bit uxSwitchRequested; - -/* - * Vector for the ISR. - */ -void pointed Interrupt() -{ - /* - * Save the context of the current task. - */ - portSAVE_CONTEXT( portINTERRUPTS_FORCED ); - - /* - * No contextswitch requested yet - */ - uxSwitchRequested = pdFALSE; - - /* - * Was the interrupt the FreeRTOS SystemTick? - */ - #include - -/******************************************************************************* -** DO NOT MODIFY ANYTHING ABOVE THIS LINE -******************************************************************************** -** Enter the includes for the ISR-code of the FreeRTOS drivers below. -** -** You cannot use local variables. Alternatives are: -** - Use static variables (Global RAM usage increases) -** - Call a function (Additional cycles are needed) -** - Use unused SFR's (preferred, no additional overhead) -** See "../Serial/isrSerialTx.c" for an example of this last option -*******************************************************************************/ - - - - /* - * Was the interrupt a byte being received? - */ - #include "../Serial/isrSerialRx.c" - - - /* - * Was the interrupt the Tx register becoming empty? - */ - #include "../Serial/isrSerialTx.c" - - - -/******************************************************************************* -** DO NOT MODIFY ANYTHING BELOW THIS LINE -*******************************************************************************/ - /* - * Was a contextswitch requested by one of the - * interrupthandlers? - */ - if ( uxSwitchRequested ) - { - vTaskSwitchContext(); - } - - /* - * Restore the context of the (possibly other) task. - */ - portRESTORE_CONTEXT(); - - #pragma asmline retfie 0 -} diff --git a/Demo/PIC18_WizC/Demo3/main.c b/Demo/PIC18_WizC/Demo3/main.c deleted file mode 100644 index 7450f5db4..000000000 --- a/Demo/PIC18_WizC/Demo3/main.c +++ /dev/null @@ -1,190 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V3.0.0 - -Changes from V3.0.1 -*/ - -/* - * Instead of the normal single demo application, the PIC18F demo is split - * into several smaller programs of which this is the third. This enables the - * demo's to be executed on the RAM limited PIC-devices. - * - * The Demo3 project is configured for a PIC18F4620 device. Main.c starts 12 - * tasks (including the idle task). See the indicated files in the demo/common - * directory for more information. - * - * demo/common/minimal/integer.c: Creates 1 task - * demo/common/minimal/BlockQ.c: Creates 6 tasks - * demo/common/minimal/flash.c: Creates 3 tasks - * - * Main.c also creates a check task. This periodically checks that all the - * other tasks are still running and have not experienced any unexpected - * results. If all the other tasks are executing correctly an LED is flashed - * once every mainCHECK_PERIOD milliseconds. If any of the tasks have not - * executed, or report an error, the frequency of the LED flash will increase - * to mainERROR_FLASH_RATE. - * - * On entry to main an 'X' is transmitted. Monitoring the serial port using a - * dumb terminal allows for verification that the device is not continuously - * being reset (no more than one 'X' should be transmitted). - * - * http://www.FreeRTOS.org contains important information on the use of the - * wizC PIC18F port. - */ - -/* Scheduler include files. */ -#include -#include - -/* Demo app include files. */ -#include "integer.h" -#include "BlockQ.h" -#include "flash.h" -#include "partest.h" -#include "serial.h" - -/* The period between executions of the check task before and after an error -has been discovered. If an error has been discovered the check task runs -more frequently - increasing the LED flash rate. */ -#define mainNO_ERROR_CHECK_PERIOD ( ( portTickType ) 10000 / portTICK_RATE_MS ) -#define mainERROR_CHECK_PERIOD ( ( portTickType ) 1000 / portTICK_RATE_MS ) -#define mainCHECK_TASK_LED ( ( unsigned portCHAR ) 3 ) - -/* Priority definitions for some of the tasks. Other tasks just use the idle -priority. */ -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 3 ) -#define mainLED_FLASH_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 2 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 1 ) -#define mainINTEGER_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 0 ) - -/* Constants required for the communications. Only one character is ever -transmitted. */ -#define mainCOMMS_QUEUE_LENGTH ( ( unsigned portCHAR ) 5 ) -#define mainNO_BLOCK ( ( portTickType ) 0 ) -#define mainBAUD_RATE ( ( unsigned portLONG ) 57600 ) - -/* - * The task function for the "Check" task. - */ -static portTASK_FUNCTION_PROTO( vErrorChecks, pvParameters ); - -/* - * Checks the unique counts of other tasks to ensure they are still operational. - * Returns pdTRUE if an error is detected, otherwise pdFALSE. - */ -static portCHAR prvCheckOtherTasksAreStillRunning( void ); - -/*-----------------------------------------------------------*/ - -/* Creates the tasks, then starts the scheduler. */ -void main( void ) -{ - /* Initialise the required hardware. */ - vParTestInitialise(); - - /* Send a character so we have some visible feedback of a reset. */ - xSerialPortInitMinimal( mainBAUD_RATE, mainCOMMS_QUEUE_LENGTH ); - xSerialPutChar( NULL, 'X', mainNO_BLOCK ); - - /* Start the standard demo tasks found in the demo\common directory. */ - vStartIntegerMathTasks( mainINTEGER_PRIORITY); - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - vStartLEDFlashTasks( mainLED_FLASH_PRIORITY ); - - /* Start the check task defined in this file. */ - xTaskCreate( vErrorChecks, ( const portCHAR * const ) "Check", portMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - - /* Start the scheduler. Will never return here. */ - vTaskStartScheduler( ); - - while(1) /* This point should never be reached. */ - { - } -} -/*-----------------------------------------------------------*/ - -static portTASK_FUNCTION( vErrorChecks, pvParameters ) -{ - portTickType xLastCheckTime; - portTickType xDelayTime = mainNO_ERROR_CHECK_PERIOD; - portCHAR cErrorOccurred; - - /* We need to initialise xLastCheckTime prior to the first call to - vTaskDelayUntil(). */ - xLastCheckTime = xTaskGetTickCount(); - - /* Cycle for ever, delaying then checking all the other tasks are still - operating without error. */ - for( ;; ) - { - /* Wait until it is time to check the other tasks again. */ - vTaskDelayUntil( &xLastCheckTime, xDelayTime ); - - /* Check all the other tasks are running, and running without ever - having an error. */ - cErrorOccurred = prvCheckOtherTasksAreStillRunning(); - - /* If an error was detected increase the frequency of the LED flash. */ - if( cErrorOccurred == pdTRUE ) - { - xDelayTime = mainERROR_CHECK_PERIOD; - } - - /* Flash the LED for visual feedback. */ - vParTestToggleLED( mainCHECK_TASK_LED ); - } -} - -/*-----------------------------------------------------------*/ - -static portCHAR prvCheckOtherTasksAreStillRunning( void ) -{ - portCHAR cErrorHasOccurred = ( portCHAR ) pdFALSE; - - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - cErrorHasOccurred = ( portCHAR ) pdTRUE; - } - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - cErrorHasOccurred = ( portCHAR ) pdTRUE; - } - - return cErrorHasOccurred; -} -/*-----------------------------------------------------------*/ - - diff --git a/Demo/PIC18_WizC/Demo4/Demo4.PC b/Demo/PIC18_WizC/Demo4/Demo4.PC deleted file mode 100644 index f4ee06de5..000000000 --- a/Demo/PIC18_WizC/Demo4/Demo4.PC +++ /dev/null @@ -1,475 +0,0 @@ -[F29012037] -x=0 -y=115 -[F15207742] -x=0 -y=48 -[F10478061] -x=0 -y=48 -[F28429921] -x=0 -y=0 -[ProjectGroup] -nFiles=1 -FileName0=Demo4.PC -[Project] -nFiles=8 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b/Demo/PIC18_WizC/Demo4/FreeRTOSConfig.h deleted file mode 100644 index c4595f5eb..000000000 --- a/Demo/PIC18_WizC/Demo4/FreeRTOSConfig.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V3.0.0 - + TickRate reduced to 250Hz. - - + configIDLE_SHOULD_YIELD added. - -Changes from V3.0.1 -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION ( 1 ) -#define configUSE_IDLE_HOOK ( 0 ) -#define configUSE_TICK_HOOK ( 0 ) -#define configTICK_RATE_HZ ( 250 ) -#define configMAX_PRIORITIES ( 4 ) -#define configMINIMAL_STACK_SIZE portMINIMAL_STACK_SIZE -#define configMAX_TASK_NAME_LEN ( 3 ) -#define configUSE_TRACE_FACILITY ( 0 ) -#define configUSE_16_BIT_TICKS ( 1 ) -#define configIDLE_SHOULD_YIELD ( 1 ) - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the component, or zero -to exclude the component. */ - -/* Include/exclude the stated API function. */ -#define INCLUDE_vTaskPrioritySet ( 1 ) -#define INCLUDE_uxTaskPriorityGet ( 1 ) -#define INCLUDE_vTaskDelete ( 0 ) -#define INCLUDE_vTaskCleanUpResources ( 0 ) -#define INCLUDE_vTaskSuspend ( 1 ) -#define INCLUDE_vTaskDelayUntil ( 1 ) -#define INCLUDE_vTaskDelay ( 1 ) - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/PIC18_WizC/Demo4/MallocConfig.h b/Demo/PIC18_WizC/Demo4/MallocConfig.h deleted file mode 100644 index 195258b51..000000000 --- a/Demo/PIC18_WizC/Demo4/MallocConfig.h +++ /dev/null @@ -1,41 +0,0 @@ -#ifndef _MALLOC_SETTINGS_H -#define _MALLOC_SETTINGS_H -/********************************************************************* -** Title: Dynamic memory (de-)allocation library for wizC. -** -** Author: Marcel van Lieshout -** -** Copyright: (c) 2005, HMCS, Marcel van Lieshout -** -** License: This software is released to the public domain and comes -** without warranty and/or guarantees of any kind. You have -** the right to use, copy, modify and/or (re-)distribute the -** software as long as the reference to the author is -** maintained in the software and a reference to the author -** is included in any documentation of each product in which -** this library (in it's original or in a modified form) -** is used. -*********************************************************************/ - -/********************************************************************* -** The model to use -*********************************************************************/ -//#define MALLOC_SMALL -#define MALLOC_LARGE - -/********************************************************************* -** The size of the heap -*********************************************************************/ -#define MALLOC_HEAP_SIZE (3200) - -/********************************************************************* -** Should released memory be scribbled with 0x55 before releasing it? -*********************************************************************/ -//#define MALLOC_SCRIBBLE - -/******************************************************************** -** Enable Debug-mode? -*********************************************************************/ -//#define MALLOC_DEBUG - -#endif /* _MALLOC_SETTINGS_H */ diff --git a/Demo/PIC18_WizC/Demo4/WIZCmake.h b/Demo/PIC18_WizC/Demo4/WIZCmake.h deleted file mode 100644 index f1225c62e..000000000 --- a/Demo/PIC18_WizC/Demo4/WIZCmake.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V3.0.0 - + Several modules predefined to avoid linker problems - -Changes from V3.0.1 -*/ - -#ifndef _memcpy - #define _memcpy 1 -#endif - -#ifndef _memset - #define _memset 1 -#endif - -#ifndef _strncpy - #define _strncpy 1 -#endif - - -#pragma wizcpp searchpath <../../Common/Include/> diff --git a/Demo/PIC18_WizC/Demo4/fuses.c b/Demo/PIC18_WizC/Demo4/fuses.c deleted file mode 100644 index a352d48f5..000000000 --- a/Demo/PIC18_WizC/Demo4/fuses.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V3.0.0 - -Changes from V3.0.1 -*/ - -/* -** Here are the configuration words set. See the PIC datasheet -** and the wizC manual for an explanation -*/ -#include - -/* -** These fuses are for PIC18F4620 -*/ -#pragma __config _CONFIG1H,_IESO_OFF_1H & _FCMEN_OFF_1H & _OSC_HSPLL_1H -#pragma __config _CONFIG2L,_BORV_21_2L & _BOREN_SBORDIS_2L & _PWRT_ON_2L -#pragma __config _CONFIG2H,_WDTPS_32768_2H & _WDT_OFF_2H -#pragma __config _CONFIG3H,_MCLRE_ON_3H & _LPT1OSC_OFF_3H & _PBADEN_OFF_3H & _CCP2MX_PORTC_3H -#pragma __config _CONFIG4L,_DEBUG_OFF_4L & _XINST_OFF_4L & _LVP_OFF_4L & _STVREN_OFF_4L -#pragma __config _CONFIG5L,_CP3_OFF_5L & _CP2_OFF_5L & _CP1_OFF_5L & _CP0_OFF_5L -#pragma __config _CONFIG5H,_CPD_OFF_5H & _CPB_OFF_5H -#pragma __config _CONFIG6L,_WRT3_OFF_6L & _WRT2_OFF_6L & _WRT1_OFF_6L & _WRT0_OFF_6L -#pragma __config _CONFIG6H,_WRTD_OFF_6H & _WRTB_OFF_6H & _WRTC_OFF_6H -#pragma __config _CONFIG7L,_EBTR3_OFF_7L & _EBTR2_OFF_7L & _EBTR1_OFF_7L & _EBTR0_OFF_7L -#pragma __config _CONFIG7H,_EBTRB_OFF_7H diff --git a/Demo/PIC18_WizC/Demo4/interrupt.c b/Demo/PIC18_WizC/Demo4/interrupt.c deleted file mode 100644 index 1d41c8c28..000000000 --- a/Demo/PIC18_WizC/Demo4/interrupt.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V3.0.0 - + Added functionality to only call vTaskSwitchContext() once - when handling multiple interruptsources in a single interruptcall. - - + Included Filenames changed to a .c extension to allow stepping through - code using F7. - -Changes from V3.0.1 -*/ - -#include - -/* Scheduler include files. */ -#include -#include -#include - -static bit uxSwitchRequested; - -/* - * Vector for the ISR. - */ -void pointed Interrupt() -{ - /* - * Save the context of the current task. - */ - portSAVE_CONTEXT( portINTERRUPTS_FORCED ); - - /* - * No contextswitch requested yet - */ - uxSwitchRequested = pdFALSE; - - /* - * Was the interrupt the FreeRTOS SystemTick? - */ - #include - -/******************************************************************************* -** DO NOT MODIFY ANYTHING ABOVE THIS LINE -******************************************************************************** -** Enter the includes for the ISR-code of the FreeRTOS drivers below. -** -** You cannot use local variables. Alternatives are: -** - Use static variables (Global RAM usage increases) -** - Call a function (Additional cycles are needed) -** - Use unused SFR's (preferred, no additional overhead) -** See "../Serial/isrSerialTx.c" for an example of this last option -*******************************************************************************/ - - - - /* - * Was the interrupt a byte being received? - */ - #include "../Serial/isrSerialRx.c" - - - /* - * Was the interrupt the Tx register becoming empty? - */ - #include "../Serial/isrSerialTx.c" - - - -/******************************************************************************* -** DO NOT MODIFY ANYTHING BELOW THIS LINE -*******************************************************************************/ - /* - * Was a contextswitch requested by one of the - * interrupthandlers? - */ - if ( uxSwitchRequested ) - { - vTaskSwitchContext(); - } - - /* - * Restore the context of the (possibly other) task. - */ - portRESTORE_CONTEXT(); - - #pragma asmline retfie 0 -} diff --git a/Demo/PIC18_WizC/Demo4/main.c b/Demo/PIC18_WizC/Demo4/main.c deleted file mode 100644 index 0bd51ce7a..000000000 --- a/Demo/PIC18_WizC/Demo4/main.c +++ /dev/null @@ -1,189 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V3.0.0 - -Changes from V3.0.1 -*/ - -/* - * Instead of the normal single demo application, the PIC18F demo is split - * into several smaller programs of which this is the fourth. This enables the - * demo's to be executed on the RAM limited PIC-devices. - * - * The Demo4 project is configured for a PIC18F4620 device. Main.c starts 11 - * tasks (including the idle task). See the indicated files in the demo/common - * directory for more information. - * - * demo/common/minimal/integer.c: Creates 1 task - * demo/common/minimal/dynamic.c: Creates 5 tasks - * demo/common/minimal/flash.c: Creates 3 tasks - * - * Main.c also creates a check task. This periodically checks that all the - * other tasks are still running and have not experienced any unexpected - * results. If all the other tasks are executing correctly an LED is flashed - * once every mainCHECK_PERIOD milliseconds. If any of the tasks have not - * executed, or report an error, the frequency of the LED flash will increase - * to mainERROR_FLASH_RATE. - * - * On entry to main an 'X' is transmitted. Monitoring the serial port using a - * dumb terminal allows for verification that the device is not continuously - * being reset (no more than one 'X' should be transmitted). - * - * http://www.FreeRTOS.org contains important information on the use of the - * wizC PIC18F port. - */ - -/* Scheduler include files. */ -#include -#include - -/* Demo app include files. */ -#include "integer.h" -#include "dynamic.h" -#include "flash.h" -#include "partest.h" -#include "serial.h" - -/* The period between executions of the check task before and after an error -has been discovered. If an error has been discovered the check task runs -more frequently - increasing the LED flash rate. */ -#define mainNO_ERROR_CHECK_PERIOD ( ( portTickType ) 10000 / portTICK_RATE_MS ) -#define mainERROR_CHECK_PERIOD ( ( portTickType ) 1000 / portTICK_RATE_MS ) -#define mainCHECK_TASK_LED ( ( unsigned portCHAR ) 3 ) - -/* Priority definitions for some of the tasks. Other tasks just use the idle -priority. */ -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 3 ) -#define mainLED_FLASH_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 2 ) -#define mainINTEGER_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 0 ) - -/* Constants required for the communications. Only one character is ever -transmitted. */ -#define mainCOMMS_QUEUE_LENGTH ( ( unsigned portCHAR ) 5 ) -#define mainNO_BLOCK ( ( portTickType ) 0 ) -#define mainBAUD_RATE ( ( unsigned portLONG ) 57600 ) - -/* - * The task function for the "Check" task. - */ -static portTASK_FUNCTION_PROTO( vErrorChecks, pvParameters ); - -/* - * Checks the unique counts of other tasks to ensure they are still operational. - * Returns pdTRUE if an error is detected, otherwise pdFALSE. - */ -static portCHAR prvCheckOtherTasksAreStillRunning( void ); - -/*-----------------------------------------------------------*/ - -/* Creates the tasks, then starts the scheduler. */ -void main( void ) -{ - /* Initialise the required hardware. */ - vParTestInitialise(); - - /* Send a character so we have some visible feedback of a reset. */ - xSerialPortInitMinimal( mainBAUD_RATE, mainCOMMS_QUEUE_LENGTH ); - xSerialPutChar( NULL, 'X', mainNO_BLOCK ); - - /* Start the standard demo tasks found in the demo\common directory. */ - vStartIntegerMathTasks( mainINTEGER_PRIORITY); - vStartDynamicPriorityTasks(); - vStartLEDFlashTasks( mainLED_FLASH_PRIORITY ); - - /* Start the check task defined in this file. */ - xTaskCreate( vErrorChecks, ( const portCHAR * const ) "Check", portMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - - /* Start the scheduler. Will never return here. */ - vTaskStartScheduler( ); - - while(1) /* This point should never be reached. */ - { - } -} -/*-----------------------------------------------------------*/ - -static portTASK_FUNCTION( vErrorChecks, pvParameters ) -{ - portTickType xLastCheckTime; - portTickType xDelayTime = mainNO_ERROR_CHECK_PERIOD; - portCHAR cErrorOccurred; - - /* We need to initialise xLastCheckTime prior to the first call to - vTaskDelayUntil(). */ - xLastCheckTime = xTaskGetTickCount(); - - /* Cycle for ever, delaying then checking all the other tasks are still - operating without error. */ - for( ;; ) - { - /* Wait until it is time to check the other tasks again. */ - vTaskDelayUntil( &xLastCheckTime, xDelayTime ); - - /* Check all the other tasks are running, and running without ever - having an error. */ - cErrorOccurred = prvCheckOtherTasksAreStillRunning(); - - /* If an error was detected increase the frequency of the LED flash. */ - if( cErrorOccurred == pdTRUE ) - { - xDelayTime = mainERROR_CHECK_PERIOD; - } - - /* Flash the LED for visual feedback. */ - vParTestToggleLED( mainCHECK_TASK_LED ); - } -} - -/*-----------------------------------------------------------*/ - -static portCHAR prvCheckOtherTasksAreStillRunning( void ) -{ - portCHAR cErrorHasOccurred = ( portCHAR ) pdFALSE; - - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - cErrorHasOccurred = ( portCHAR ) pdTRUE; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - cErrorHasOccurred = ( portCHAR ) pdTRUE; - } - - return cErrorHasOccurred; -} -/*-----------------------------------------------------------*/ - - diff --git a/Demo/PIC18_WizC/Demo5/Demo5.PC b/Demo/PIC18_WizC/Demo5/Demo5.PC deleted file mode 100644 index 479208633..000000000 --- a/Demo/PIC18_WizC/Demo5/Demo5.PC +++ /dev/null @@ -1,536 +0,0 @@ -[F29012293] -x=0 -y=114 -[F10478061] -x=0 -y=48 -[F15207742] -x=0 -y=48 -[F28446561] -x=0 -y=0 -[F30163742] -x=38 -y=56 -[F29565566] -x=0 -y=0 -[ProjectGroup] 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the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V3.0.0 - + TickRate reduced to 250Hz. - - + configIDLE_SHOULD_YIELD added. - -Changes from V3.0.1 -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION ( 1 ) -#define configUSE_IDLE_HOOK ( 0 ) -#define configUSE_TICK_HOOK ( 0 ) -#define configTICK_RATE_HZ ( 250 ) -#define configMAX_PRIORITIES ( 3 ) -#define configMINIMAL_STACK_SIZE portMINIMAL_STACK_SIZE -#define configMAX_TASK_NAME_LEN ( 3 ) -#define configUSE_TRACE_FACILITY ( 0 ) -#define configUSE_16_BIT_TICKS ( 1 ) -#define configIDLE_SHOULD_YIELD ( 1 ) - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the component, or zero -to exclude the component. */ - -/* Include/exclude the stated API function. */ -#define INCLUDE_vTaskPrioritySet ( 0 ) -#define INCLUDE_uxTaskPriorityGet ( 0 ) -#define INCLUDE_vTaskDelete ( 0 ) -#define INCLUDE_vTaskCleanUpResources ( 0 ) -#define INCLUDE_vTaskSuspend ( 0 ) -#define INCLUDE_vTaskDelayUntil ( 1 ) -#define INCLUDE_vTaskDelay ( 0 ) - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/PIC18_WizC/Demo5/MallocConfig.h b/Demo/PIC18_WizC/Demo5/MallocConfig.h deleted file mode 100644 index 195258b51..000000000 --- a/Demo/PIC18_WizC/Demo5/MallocConfig.h +++ /dev/null @@ -1,41 +0,0 @@ -#ifndef _MALLOC_SETTINGS_H -#define _MALLOC_SETTINGS_H -/********************************************************************* -** Title: Dynamic memory (de-)allocation library for wizC. -** -** Author: Marcel van Lieshout -** -** Copyright: (c) 2005, HMCS, Marcel van Lieshout -** -** License: This software is released to the public domain and comes -** without warranty and/or guarantees of any kind. You have -** the right to use, copy, modify and/or (re-)distribute the -** software as long as the reference to the author is -** maintained in the software and a reference to the author -** is included in any documentation of each product in which -** this library (in it's original or in a modified form) -** is used. -*********************************************************************/ - -/********************************************************************* -** The model to use -*********************************************************************/ -//#define MALLOC_SMALL -#define MALLOC_LARGE - -/********************************************************************* -** The size of the heap -*********************************************************************/ -#define MALLOC_HEAP_SIZE (3200) - -/********************************************************************* -** Should released memory be scribbled with 0x55 before releasing it? -*********************************************************************/ -//#define MALLOC_SCRIBBLE - -/******************************************************************** -** Enable Debug-mode? -*********************************************************************/ -//#define MALLOC_DEBUG - -#endif /* _MALLOC_SETTINGS_H */ diff --git a/Demo/PIC18_WizC/Demo5/WIZCmake.h b/Demo/PIC18_WizC/Demo5/WIZCmake.h deleted file mode 100644 index f1225c62e..000000000 --- a/Demo/PIC18_WizC/Demo5/WIZCmake.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V3.0.0 - + Several modules predefined to avoid linker problems - -Changes from V3.0.1 -*/ - -#ifndef _memcpy - #define _memcpy 1 -#endif - -#ifndef _memset - #define _memset 1 -#endif - -#ifndef _strncpy - #define _strncpy 1 -#endif - - -#pragma wizcpp searchpath <../../Common/Include/> diff --git a/Demo/PIC18_WizC/Demo5/fuses.c b/Demo/PIC18_WizC/Demo5/fuses.c deleted file mode 100644 index a352d48f5..000000000 --- a/Demo/PIC18_WizC/Demo5/fuses.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V3.0.0 - -Changes from V3.0.1 -*/ - -/* -** Here are the configuration words set. See the PIC datasheet -** and the wizC manual for an explanation -*/ -#include - -/* -** These fuses are for PIC18F4620 -*/ -#pragma __config _CONFIG1H,_IESO_OFF_1H & _FCMEN_OFF_1H & _OSC_HSPLL_1H -#pragma __config _CONFIG2L,_BORV_21_2L & _BOREN_SBORDIS_2L & _PWRT_ON_2L -#pragma __config _CONFIG2H,_WDTPS_32768_2H & _WDT_OFF_2H -#pragma __config _CONFIG3H,_MCLRE_ON_3H & _LPT1OSC_OFF_3H & _PBADEN_OFF_3H & _CCP2MX_PORTC_3H -#pragma __config _CONFIG4L,_DEBUG_OFF_4L & _XINST_OFF_4L & _LVP_OFF_4L & _STVREN_OFF_4L -#pragma __config _CONFIG5L,_CP3_OFF_5L & _CP2_OFF_5L & _CP1_OFF_5L & _CP0_OFF_5L -#pragma __config _CONFIG5H,_CPD_OFF_5H & _CPB_OFF_5H -#pragma __config _CONFIG6L,_WRT3_OFF_6L & _WRT2_OFF_6L & _WRT1_OFF_6L & _WRT0_OFF_6L -#pragma __config _CONFIG6H,_WRTD_OFF_6H & _WRTB_OFF_6H & _WRTC_OFF_6H -#pragma __config _CONFIG7L,_EBTR3_OFF_7L & _EBTR2_OFF_7L & _EBTR1_OFF_7L & _EBTR0_OFF_7L -#pragma __config _CONFIG7H,_EBTRB_OFF_7H diff --git a/Demo/PIC18_WizC/Demo5/interrupt.c b/Demo/PIC18_WizC/Demo5/interrupt.c deleted file mode 100644 index 1d41c8c28..000000000 --- a/Demo/PIC18_WizC/Demo5/interrupt.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V3.0.0 - + Added functionality to only call vTaskSwitchContext() once - when handling multiple interruptsources in a single interruptcall. - - + Included Filenames changed to a .c extension to allow stepping through - code using F7. - -Changes from V3.0.1 -*/ - -#include - -/* Scheduler include files. */ -#include -#include -#include - -static bit uxSwitchRequested; - -/* - * Vector for the ISR. - */ -void pointed Interrupt() -{ - /* - * Save the context of the current task. - */ - portSAVE_CONTEXT( portINTERRUPTS_FORCED ); - - /* - * No contextswitch requested yet - */ - uxSwitchRequested = pdFALSE; - - /* - * Was the interrupt the FreeRTOS SystemTick? - */ - #include - -/******************************************************************************* -** DO NOT MODIFY ANYTHING ABOVE THIS LINE -******************************************************************************** -** Enter the includes for the ISR-code of the FreeRTOS drivers below. -** -** You cannot use local variables. Alternatives are: -** - Use static variables (Global RAM usage increases) -** - Call a function (Additional cycles are needed) -** - Use unused SFR's (preferred, no additional overhead) -** See "../Serial/isrSerialTx.c" for an example of this last option -*******************************************************************************/ - - - - /* - * Was the interrupt a byte being received? - */ - #include "../Serial/isrSerialRx.c" - - - /* - * Was the interrupt the Tx register becoming empty? - */ - #include "../Serial/isrSerialTx.c" - - - -/******************************************************************************* -** DO NOT MODIFY ANYTHING BELOW THIS LINE -*******************************************************************************/ - /* - * Was a contextswitch requested by one of the - * interrupthandlers? - */ - if ( uxSwitchRequested ) - { - vTaskSwitchContext(); - } - - /* - * Restore the context of the (possibly other) task. - */ - portRESTORE_CONTEXT(); - - #pragma asmline retfie 0 -} diff --git a/Demo/PIC18_WizC/Demo5/main.c b/Demo/PIC18_WizC/Demo5/main.c deleted file mode 100644 index dcc413086..000000000 --- a/Demo/PIC18_WizC/Demo5/main.c +++ /dev/null @@ -1,178 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V3.0.0 - -Changes from V3.0.1 -*/ - -/* - * Instead of the normal single demo application, the PIC18F demo is split - * into several smaller programs of which this is the fifth. This enables the - * demo's to be executed on the RAM limited PIC-devices. - * - * The Demo5 project is configured for a PIC18F4620 device. Main.c starts 13 - * tasks (including the idle task). See the indicated files in the demo/common - * directory for more information. - * - * demo/common/minimal/flop.c: Creates 8 tasks - * demo/common/minimal/flash.c: Creates 3 tasks - * - * Main.c also creates a check task. This periodically checks that all the - * other tasks are still running and have not experienced any unexpected - * results. If all the other tasks are executing correctly an LED is flashed - * once every mainCHECK_PERIOD milliseconds. If any of the tasks have not - * executed, or report an error, the frequency of the LED flash will increase - * to mainERROR_FLASH_RATE. - * - * On entry to main an 'X' is transmitted. Monitoring the serial port using a - * dumb terminal allows for verification that the device is not continuously - * being reset (no more than one 'X' should be transmitted). - * - * http://www.FreeRTOS.org contains important information on the use of the - * wizC PIC18F port. - */ - -/* Scheduler include files. */ -#include -#include - -/* Demo app include files. */ -#include "flop.h" -#include "flash.h" -#include "partest.h" -#include "serial.h" - -/* The period between executions of the check task before and after an error -has been discovered. If an error has been discovered the check task runs -more frequently - increasing the LED flash rate. */ -#define mainNO_ERROR_CHECK_PERIOD ( ( portTickType ) 10000 / portTICK_RATE_MS ) -#define mainERROR_CHECK_PERIOD ( ( portTickType ) 1000 / portTICK_RATE_MS ) -#define mainCHECK_TASK_LED ( ( unsigned portCHAR ) 3 ) - -/* Priority definitions for some of the tasks. Other tasks just use the idle -priority. */ -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 2 ) -#define mainLED_FLASH_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 1 ) - -/* Constants required for the communications. Only one character is ever -transmitted. */ -#define mainCOMMS_QUEUE_LENGTH ( ( unsigned portCHAR ) 5 ) -#define mainNO_BLOCK ( ( portTickType ) 0 ) -#define mainBAUD_RATE ( ( unsigned portLONG ) 57600 ) - -/* - * The task function for the "Check" task. - */ -static portTASK_FUNCTION_PROTO( vErrorChecks, pvParameters ); - -/* - * Checks the unique counts of other tasks to ensure they are still operational. - * Returns pdTRUE if an error is detected, otherwise pdFALSE. - */ -static portCHAR prvCheckOtherTasksAreStillRunning( void ); - -/*-----------------------------------------------------------*/ - -/* Creates the tasks, then starts the scheduler. */ -void main( void ) -{ - /* Initialise the required hardware. */ - vParTestInitialise(); - - /* Send a character so we have some visible feedback of a reset. */ - xSerialPortInitMinimal( mainBAUD_RATE, mainCOMMS_QUEUE_LENGTH ); - xSerialPutChar( NULL, 'X', mainNO_BLOCK ); - - /* Start a few of the standard demo tasks found in the demo\common directory. */ - vStartMathTasks( tskIDLE_PRIORITY ); - vStartLEDFlashTasks( mainLED_FLASH_PRIORITY ); - - /* Start the check task defined in this file. */ - xTaskCreate( vErrorChecks, ( const portCHAR * const ) "Check", portMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - - /* Start the scheduler. Will never return here. */ - vTaskStartScheduler(); - - while(1) /* This point should never be reached. */ - { - } -} -/*-----------------------------------------------------------*/ - -static portTASK_FUNCTION( vErrorChecks, pvParameters ) -{ -portTickType xLastCheckTime; -portTickType xDelayTime = mainNO_ERROR_CHECK_PERIOD; -portCHAR cErrorOccurred; - - /* We need to initialise xLastCheckTime prior to the first call to - vTaskDelayUntil(). */ - xLastCheckTime = xTaskGetTickCount(); - - /* Cycle for ever, delaying then checking all the other tasks are still - operating without error. */ - for( ;; ) - { - /* Wait until it is time to check the other tasks again. */ - vTaskDelayUntil( &xLastCheckTime, xDelayTime ); - - /* Check all the other tasks are running, and running without ever - having an error. */ - cErrorOccurred = prvCheckOtherTasksAreStillRunning(); - - /* If an error was detected increase the frequency of the LED flash. */ - if( cErrorOccurred == pdTRUE ) - { - xDelayTime = mainERROR_CHECK_PERIOD; - } - - /* Flash the LED for visual feedback. */ - vParTestToggleLED( mainCHECK_TASK_LED ); - } -} -/*-----------------------------------------------------------*/ - -static portCHAR prvCheckOtherTasksAreStillRunning( void ) -{ - portCHAR cErrorHasOccurred = ( portCHAR ) pdFALSE; - - if( xAreMathsTaskStillRunning() != pdTRUE ) - { - cErrorHasOccurred = ( portCHAR ) pdTRUE; - } - return cErrorHasOccurred; -} -/*-----------------------------------------------------------*/ - - diff --git a/Demo/PIC18_WizC/Demo6/Demo6.PC b/Demo/PIC18_WizC/Demo6/Demo6.PC deleted file mode 100644 index 5f5f39862..000000000 --- a/Demo/PIC18_WizC/Demo6/Demo6.PC +++ /dev/null @@ -1,632 +0,0 @@ -[F29012549] -x=0 -y=111 -[F15207742] -x=0 -y=48 -[F28463201] -x=0 -y=0 -[F30163998] -x=60 -y=44 -[F29565822] -x=2 -y=23 -[F26101515] -x=0 -y=269 -[ProjectGroup] -nFiles=1 -FileName0=Demo6.PC -[Project] -nFiles=6 -UseAD=0 -CompatOpts=0 -AutoHead= -IdentifierPrint=0 -TreePrint=0 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will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V3.0.0 - + TickRate reduced to 250Hz. - - + configIDLE_SHOULD_YIELD added. - -Changes from V3.0.1 -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION ( 1 ) -#define configUSE_IDLE_HOOK ( 0 ) -#define configUSE_TICK_HOOK ( 0 ) -#define configTICK_RATE_HZ ( 250 ) -#define configMAX_PRIORITIES ( 3 ) -#define configMINIMAL_STACK_SIZE portMINIMAL_STACK_SIZE -#define configMAX_TASK_NAME_LEN ( 3 ) -#define configUSE_TRACE_FACILITY ( 0 ) -#define configUSE_16_BIT_TICKS ( 1 ) -#define configIDLE_SHOULD_YIELD ( 1 ) - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the component, or zero -to exclude the component. */ - -/* Include/exclude the stated API function. */ -#define INCLUDE_vTaskPrioritySet ( 0 ) -#define INCLUDE_uxTaskPriorityGet ( 0 ) -#define INCLUDE_vTaskDelete ( 0 ) -#define INCLUDE_vTaskCleanUpResources ( 0 ) -#define INCLUDE_vTaskSuspend ( 0 ) -#define INCLUDE_vTaskDelayUntil ( 1 ) -#define INCLUDE_vTaskDelay ( 1 ) - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/PIC18_WizC/Demo6/MallocConfig.h b/Demo/PIC18_WizC/Demo6/MallocConfig.h deleted file mode 100644 index 195258b51..000000000 --- a/Demo/PIC18_WizC/Demo6/MallocConfig.h +++ /dev/null @@ -1,41 +0,0 @@ -#ifndef _MALLOC_SETTINGS_H -#define _MALLOC_SETTINGS_H -/********************************************************************* -** Title: Dynamic memory (de-)allocation library for wizC. -** -** Author: Marcel van Lieshout -** -** Copyright: (c) 2005, HMCS, Marcel van Lieshout -** -** License: This software is released to the public domain and comes -** without warranty and/or guarantees of any kind. You have -** the right to use, copy, modify and/or (re-)distribute the -** software as long as the reference to the author is -** maintained in the software and a reference to the author -** is included in any documentation of each product in which -** this library (in it's original or in a modified form) -** is used. -*********************************************************************/ - -/********************************************************************* -** The model to use -*********************************************************************/ -//#define MALLOC_SMALL -#define MALLOC_LARGE - -/********************************************************************* -** The size of the heap -*********************************************************************/ -#define MALLOC_HEAP_SIZE (3200) - -/********************************************************************* -** Should released memory be scribbled with 0x55 before releasing it? -*********************************************************************/ -//#define MALLOC_SCRIBBLE - -/******************************************************************** -** Enable Debug-mode? -*********************************************************************/ -//#define MALLOC_DEBUG - -#endif /* _MALLOC_SETTINGS_H */ diff --git a/Demo/PIC18_WizC/Demo6/WIZCmake.h b/Demo/PIC18_WizC/Demo6/WIZCmake.h deleted file mode 100644 index f1225c62e..000000000 --- a/Demo/PIC18_WizC/Demo6/WIZCmake.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V3.0.0 - + Several modules predefined to avoid linker problems - -Changes from V3.0.1 -*/ - -#ifndef _memcpy - #define _memcpy 1 -#endif - -#ifndef _memset - #define _memset 1 -#endif - -#ifndef _strncpy - #define _strncpy 1 -#endif - - -#pragma wizcpp searchpath <../../Common/Include/> diff --git a/Demo/PIC18_WizC/Demo6/fuses.c b/Demo/PIC18_WizC/Demo6/fuses.c deleted file mode 100644 index a352d48f5..000000000 --- a/Demo/PIC18_WizC/Demo6/fuses.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V3.0.0 - -Changes from V3.0.1 -*/ - -/* -** Here are the configuration words set. See the PIC datasheet -** and the wizC manual for an explanation -*/ -#include - -/* -** These fuses are for PIC18F4620 -*/ -#pragma __config _CONFIG1H,_IESO_OFF_1H & _FCMEN_OFF_1H & _OSC_HSPLL_1H -#pragma __config _CONFIG2L,_BORV_21_2L & _BOREN_SBORDIS_2L & _PWRT_ON_2L -#pragma __config _CONFIG2H,_WDTPS_32768_2H & _WDT_OFF_2H -#pragma __config _CONFIG3H,_MCLRE_ON_3H & _LPT1OSC_OFF_3H & _PBADEN_OFF_3H & _CCP2MX_PORTC_3H -#pragma __config _CONFIG4L,_DEBUG_OFF_4L & _XINST_OFF_4L & _LVP_OFF_4L & _STVREN_OFF_4L -#pragma __config _CONFIG5L,_CP3_OFF_5L & _CP2_OFF_5L & _CP1_OFF_5L & _CP0_OFF_5L -#pragma __config _CONFIG5H,_CPD_OFF_5H & _CPB_OFF_5H -#pragma __config _CONFIG6L,_WRT3_OFF_6L & _WRT2_OFF_6L & _WRT1_OFF_6L & _WRT0_OFF_6L -#pragma __config _CONFIG6H,_WRTD_OFF_6H & _WRTB_OFF_6H & _WRTC_OFF_6H -#pragma __config _CONFIG7L,_EBTR3_OFF_7L & _EBTR2_OFF_7L & _EBTR1_OFF_7L & _EBTR0_OFF_7L -#pragma __config _CONFIG7H,_EBTRB_OFF_7H diff --git a/Demo/PIC18_WizC/Demo6/interrupt.c b/Demo/PIC18_WizC/Demo6/interrupt.c deleted file mode 100644 index 1d41c8c28..000000000 --- a/Demo/PIC18_WizC/Demo6/interrupt.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V3.0.0 - + Added functionality to only call vTaskSwitchContext() once - when handling multiple interruptsources in a single interruptcall. - - + Included Filenames changed to a .c extension to allow stepping through - code using F7. - -Changes from V3.0.1 -*/ - -#include - -/* Scheduler include files. */ -#include -#include -#include - -static bit uxSwitchRequested; - -/* - * Vector for the ISR. - */ -void pointed Interrupt() -{ - /* - * Save the context of the current task. - */ - portSAVE_CONTEXT( portINTERRUPTS_FORCED ); - - /* - * No contextswitch requested yet - */ - uxSwitchRequested = pdFALSE; - - /* - * Was the interrupt the FreeRTOS SystemTick? - */ - #include - -/******************************************************************************* -** DO NOT MODIFY ANYTHING ABOVE THIS LINE -******************************************************************************** -** Enter the includes for the ISR-code of the FreeRTOS drivers below. -** -** You cannot use local variables. Alternatives are: -** - Use static variables (Global RAM usage increases) -** - Call a function (Additional cycles are needed) -** - Use unused SFR's (preferred, no additional overhead) -** See "../Serial/isrSerialTx.c" for an example of this last option -*******************************************************************************/ - - - - /* - * Was the interrupt a byte being received? - */ - #include "../Serial/isrSerialRx.c" - - - /* - * Was the interrupt the Tx register becoming empty? - */ - #include "../Serial/isrSerialTx.c" - - - -/******************************************************************************* -** DO NOT MODIFY ANYTHING BELOW THIS LINE -*******************************************************************************/ - /* - * Was a contextswitch requested by one of the - * interrupthandlers? - */ - if ( uxSwitchRequested ) - { - vTaskSwitchContext(); - } - - /* - * Restore the context of the (possibly other) task. - */ - portRESTORE_CONTEXT(); - - #pragma asmline retfie 0 -} diff --git a/Demo/PIC18_WizC/Demo6/main.c b/Demo/PIC18_WizC/Demo6/main.c deleted file mode 100644 index 0f2e23812..000000000 --- a/Demo/PIC18_WizC/Demo6/main.c +++ /dev/null @@ -1,170 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V3.0.0 - -Changes from V3.0.1 -*/ - -/* - * Instead of the normal single demo application, the PIC18F demo is split - * into several smaller programs of which this is the sixth. This enables the - * demo's to be executed on the RAM limited PIC-devices. - * - * The Demo6 project is configured for a PIC18F4620 device. Main.c starts 4 - * tasks (including the idle task). See the indicated files in the demo/common - * directory for more information. - * - * demo/common/minimal/comtest.c: Creates 2 tasks - * ATTENTION: Comtest needs a loopback-connector on the serial port. - * - * Main.c also creates a check task. This periodically checks that all the - * other tasks are still running and have not experienced any unexpected - * results. If all the other tasks are executing correctly an LED is flashed - * once every mainCHECK_PERIOD milliseconds. If any of the tasks have not - * executed, or report an error, the frequency of the LED flash will increase - * to mainERROR_FLASH_RATE. - * - * http://www.FreeRTOS.org contains important information on the use of the - * wizC PIC18F port. - */ - -/* Scheduler include files. */ -#include -#include - -/* Demo app include files. */ -#include "partest.h" -#include "serial.h" -#include "comtest.h" - -/* The period between executions of the check task before and after an error -has been discovered. If an error has been discovered the check task runs -more frequently - increasing the LED flash rate. */ -#define mainNO_ERROR_CHECK_PERIOD ( ( portTickType ) 10000 / portTICK_RATE_MS ) -#define mainERROR_CHECK_PERIOD ( ( portTickType ) 1000 / portTICK_RATE_MS ) -#define mainCHECK_TASK_LED ( ( unsigned portCHAR ) 3 ) - -/* Priority definitions for some of the tasks. Other tasks just use the idle -priority. */ -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 2 ) -#define mainCOMM_TEST_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 1 ) - -/* The LED that is toggled whenever a character is transmitted. -mainCOMM_TX_RX_LED + 1 will be toggled every time a character is received. */ -#define mainCOMM_TX_RX_LED ( ( unsigned portCHAR ) 0 ) - -/* Constants required for the communications. */ -#define mainBAUD_RATE ( ( unsigned portLONG ) 57600 ) - -/* - * The task function for the "Check" task. - */ -static portTASK_FUNCTION_PROTO( vErrorChecks, pvParameters ); - -/* - * Checks the unique counts of other tasks to ensure they are still operational. - * Returns pdTRUE if an error is detected, otherwise pdFALSE. - */ -static portCHAR prvCheckOtherTasksAreStillRunning( void ); - -/*-----------------------------------------------------------*/ - -/* Creates the tasks, then starts the scheduler. */ -void main( void ) -{ - /* Initialise the required hardware. */ - vParTestInitialise(); - - /* Start a few of the standard demo tasks found in the demo\common directory. */ - vAltStartComTestTasks( mainCOMM_TEST_PRIORITY, mainBAUD_RATE, mainCOMM_TX_RX_LED ); - - /* Start the check task defined in this file. */ - xTaskCreate( vErrorChecks, ( const portCHAR * const ) "Check", portMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - - /* Start the scheduler. Will never return here. */ - vTaskStartScheduler(); - - while(1) /* This point should never be reached. */ - { - } -} -/*-----------------------------------------------------------*/ - -static portTASK_FUNCTION( vErrorChecks, pvParameters ) -{ -portTickType xLastCheckTime; -portTickType xDelayTime = mainNO_ERROR_CHECK_PERIOD; -portCHAR cErrorOccurred; - - /* We need to initialise xLastCheckTime prior to the first call to - vTaskDelayUntil(). */ - xLastCheckTime = xTaskGetTickCount(); - - /* Cycle for ever, delaying then checking all the other tasks are still - operating without error. */ - for( ;; ) - { - /* Wait until it is time to check the other tasks again. */ - vTaskDelayUntil( &xLastCheckTime, xDelayTime ); - - /* Check all the other tasks are running, and running without ever - having an error. */ - cErrorOccurred = prvCheckOtherTasksAreStillRunning(); - - /* If an error was detected increase the frequency of the LED flash. */ - if( cErrorOccurred == pdTRUE ) - { - xDelayTime = mainERROR_CHECK_PERIOD; - } - - /* Flash the LED for visual feedback. */ - vParTestToggleLED( mainCHECK_TASK_LED ); - } -} -/*-----------------------------------------------------------*/ - -static portCHAR prvCheckOtherTasksAreStillRunning( void ) -{ - portCHAR cErrorHasOccurred = ( portCHAR ) pdFALSE; - - if( xAreComTestTasksStillRunning() != pdTRUE ) - { - cErrorHasOccurred = ( portCHAR ) pdTRUE; - } - - return cErrorHasOccurred; -} -/*-----------------------------------------------------------*/ - - diff --git a/Demo/PIC18_WizC/Demo7/Demo7.PC b/Demo/PIC18_WizC/Demo7/Demo7.PC deleted file mode 100644 index a89bd1912..000000000 --- a/Demo/PIC18_WizC/Demo7/Demo7.PC +++ /dev/null @@ -1,546 +0,0 @@ -[F29012549] -x=0 -y=111 -[F15207742] -x=0 -y=48 -[F26101515] -x=0 -y=269 -[F28463201] -x=0 -y=0 -[F20539803] -x=0 -y=233 -[ProjectGroup] -nFiles=1 -FileName0=Demo7.PC -[Project] -nFiles=7 -UseAD=0 -CompatOpts=0 -AutoHead= -IdentifierPrint=0 -TreePrint=0 -StatementResultPrint=0 -SourcePrint=0 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cce2ef9f4..000000000 --- a/Demo/PIC18_WizC/Demo7/FreeRTOSConfig.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V3.0.0 - + TickRate reduced to 250Hz. - - + configIDLE_SHOULD_YIELD added. - -Changes from V3.0.1 -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION ( 1 ) -#define configUSE_IDLE_HOOK ( 0 ) -#define configUSE_TICK_HOOK ( 0 ) -#define configTICK_RATE_HZ ( 250 ) -#define configMAX_PRIORITIES ( 4 ) -#define configMINIMAL_STACK_SIZE portMINIMAL_STACK_SIZE -#define configMAX_TASK_NAME_LEN ( 3 ) -#define configUSE_TRACE_FACILITY ( 0 ) -#define configUSE_16_BIT_TICKS ( 1 ) -#define configIDLE_SHOULD_YIELD ( 1 ) - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the component, or zero -to exclude the component. */ - -/* Include/exclude the stated API function. */ -#define INCLUDE_vTaskPrioritySet ( 0 ) -#define INCLUDE_uxTaskPriorityGet ( 0 ) -#define INCLUDE_vTaskDelete ( 1 ) -#define INCLUDE_vTaskCleanUpResources ( 0 ) -#define INCLUDE_vTaskSuspend ( 0 ) -#define INCLUDE_vTaskDelayUntil ( 1 ) -#define INCLUDE_vTaskDelay ( 1 ) - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/PIC18_WizC/Demo7/MallocConfig.h b/Demo/PIC18_WizC/Demo7/MallocConfig.h deleted file mode 100644 index 195258b51..000000000 --- a/Demo/PIC18_WizC/Demo7/MallocConfig.h +++ /dev/null @@ -1,41 +0,0 @@ -#ifndef _MALLOC_SETTINGS_H -#define _MALLOC_SETTINGS_H -/********************************************************************* -** Title: Dynamic memory (de-)allocation library for wizC. -** -** Author: Marcel van Lieshout -** -** Copyright: (c) 2005, HMCS, Marcel van Lieshout -** -** License: This software is released to the public domain and comes -** without warranty and/or guarantees of any kind. You have -** the right to use, copy, modify and/or (re-)distribute the -** software as long as the reference to the author is -** maintained in the software and a reference to the author -** is included in any documentation of each product in which -** this library (in it's original or in a modified form) -** is used. -*********************************************************************/ - -/********************************************************************* -** The model to use -*********************************************************************/ -//#define MALLOC_SMALL -#define MALLOC_LARGE - -/********************************************************************* -** The size of the heap -*********************************************************************/ -#define MALLOC_HEAP_SIZE (3200) - -/********************************************************************* -** Should released memory be scribbled with 0x55 before releasing it? -*********************************************************************/ -//#define MALLOC_SCRIBBLE - -/******************************************************************** -** Enable Debug-mode? -*********************************************************************/ -//#define MALLOC_DEBUG - -#endif /* _MALLOC_SETTINGS_H */ diff --git a/Demo/PIC18_WizC/Demo7/WIZCmake.h b/Demo/PIC18_WizC/Demo7/WIZCmake.h deleted file mode 100644 index f1225c62e..000000000 --- a/Demo/PIC18_WizC/Demo7/WIZCmake.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V3.0.0 - + Several modules predefined to avoid linker problems - -Changes from V3.0.1 -*/ - -#ifndef _memcpy - #define _memcpy 1 -#endif - -#ifndef _memset - #define _memset 1 -#endif - -#ifndef _strncpy - #define _strncpy 1 -#endif - - -#pragma wizcpp searchpath <../../Common/Include/> diff --git a/Demo/PIC18_WizC/Demo7/fuses.c b/Demo/PIC18_WizC/Demo7/fuses.c deleted file mode 100644 index a352d48f5..000000000 --- a/Demo/PIC18_WizC/Demo7/fuses.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V3.0.0 - -Changes from V3.0.1 -*/ - -/* -** Here are the configuration words set. See the PIC datasheet -** and the wizC manual for an explanation -*/ -#include - -/* -** These fuses are for PIC18F4620 -*/ -#pragma __config _CONFIG1H,_IESO_OFF_1H & _FCMEN_OFF_1H & _OSC_HSPLL_1H -#pragma __config _CONFIG2L,_BORV_21_2L & _BOREN_SBORDIS_2L & _PWRT_ON_2L -#pragma __config _CONFIG2H,_WDTPS_32768_2H & _WDT_OFF_2H -#pragma __config _CONFIG3H,_MCLRE_ON_3H & _LPT1OSC_OFF_3H & _PBADEN_OFF_3H & _CCP2MX_PORTC_3H -#pragma __config _CONFIG4L,_DEBUG_OFF_4L & _XINST_OFF_4L & _LVP_OFF_4L & _STVREN_OFF_4L -#pragma __config _CONFIG5L,_CP3_OFF_5L & _CP2_OFF_5L & _CP1_OFF_5L & _CP0_OFF_5L -#pragma __config _CONFIG5H,_CPD_OFF_5H & _CPB_OFF_5H -#pragma __config _CONFIG6L,_WRT3_OFF_6L & _WRT2_OFF_6L & _WRT1_OFF_6L & _WRT0_OFF_6L -#pragma __config _CONFIG6H,_WRTD_OFF_6H & _WRTB_OFF_6H & _WRTC_OFF_6H -#pragma __config _CONFIG7L,_EBTR3_OFF_7L & _EBTR2_OFF_7L & _EBTR1_OFF_7L & _EBTR0_OFF_7L -#pragma __config _CONFIG7H,_EBTRB_OFF_7H diff --git a/Demo/PIC18_WizC/Demo7/interrupt.c b/Demo/PIC18_WizC/Demo7/interrupt.c deleted file mode 100644 index 1d41c8c28..000000000 --- a/Demo/PIC18_WizC/Demo7/interrupt.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V3.0.0 - + Added functionality to only call vTaskSwitchContext() once - when handling multiple interruptsources in a single interruptcall. - - + Included Filenames changed to a .c extension to allow stepping through - code using F7. - -Changes from V3.0.1 -*/ - -#include - -/* Scheduler include files. */ -#include -#include -#include - -static bit uxSwitchRequested; - -/* - * Vector for the ISR. - */ -void pointed Interrupt() -{ - /* - * Save the context of the current task. - */ - portSAVE_CONTEXT( portINTERRUPTS_FORCED ); - - /* - * No contextswitch requested yet - */ - uxSwitchRequested = pdFALSE; - - /* - * Was the interrupt the FreeRTOS SystemTick? - */ - #include - -/******************************************************************************* -** DO NOT MODIFY ANYTHING ABOVE THIS LINE -******************************************************************************** -** Enter the includes for the ISR-code of the FreeRTOS drivers below. -** -** You cannot use local variables. Alternatives are: -** - Use static variables (Global RAM usage increases) -** - Call a function (Additional cycles are needed) -** - Use unused SFR's (preferred, no additional overhead) -** See "../Serial/isrSerialTx.c" for an example of this last option -*******************************************************************************/ - - - - /* - * Was the interrupt a byte being received? - */ - #include "../Serial/isrSerialRx.c" - - - /* - * Was the interrupt the Tx register becoming empty? - */ - #include "../Serial/isrSerialTx.c" - - - -/******************************************************************************* -** DO NOT MODIFY ANYTHING BELOW THIS LINE -*******************************************************************************/ - /* - * Was a contextswitch requested by one of the - * interrupthandlers? - */ - if ( uxSwitchRequested ) - { - vTaskSwitchContext(); - } - - /* - * Restore the context of the (possibly other) task. - */ - portRESTORE_CONTEXT(); - - #pragma asmline retfie 0 -} diff --git a/Demo/PIC18_WizC/Demo7/main.c b/Demo/PIC18_WizC/Demo7/main.c deleted file mode 100644 index 7f534d35d..000000000 --- a/Demo/PIC18_WizC/Demo7/main.c +++ /dev/null @@ -1,184 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V3.0.0 - -Changes from V3.0.1 -*/ - -/* - * Instead of the normal single demo application, the PIC18F demo is split - * into several smaller programs of which this is the seventh. This enables the - * demo's to be executed on the RAM limited PIC-devices. - * - * The Demo7 project is configured for a PIC18F4620 device. Main.c starts 10 - * tasks (including the idle task). See the indicated files in the demo/common - * directory for more information. - * - * demo/common/minimal/flash.c: Creates 3 tasks - * demo/common/minimal/death.c: Creates 1 controltask and - * creates/deletes 4 suicidaltasks - * - * Main.c also creates a check task. This periodically checks that all the - * other tasks are still running and have not experienced any unexpected - * results. If all the other tasks are executing correctly an LED is flashed - * once every mainCHECK_PERIOD milliseconds. If any of the tasks have not - * executed, or report an error, the frequency of the LED flash will increase - * to mainERROR_FLASH_RATE. - * - * On entry to main an 'X' is transmitted. Monitoring the serial port using a - * dumb terminal allows for verification that the device is not continuously - * being reset (no more than one 'X' should be transmitted). - * - * http://www.FreeRTOS.org contains important information on the use of the - * wizC PIC18F port. - */ - -/* Scheduler include files. */ -#include -#include - -/* Demo app include files. */ -#include "death.h" -#include "flash.h" -#include "partest.h" -#include "serial.h" - -/* The period between executions of the check task before and after an error -has been discovered. If an error has been discovered the check task runs -more frequently - increasing the LED flash rate. */ -#define mainNO_ERROR_CHECK_PERIOD ( ( portTickType ) 10000 / portTICK_RATE_MS ) -#define mainERROR_CHECK_PERIOD ( ( portTickType ) 1000 / portTICK_RATE_MS ) -#define mainCHECK_TASK_LED ( ( unsigned portCHAR ) 3 ) - -/* Priority definitions for some of the tasks. Other tasks just use the idle -priority. */ -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 2 ) -#define mainLED_FLASH_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 2 ) -#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + ( unsigned portCHAR ) 1 ) - -/* Constants required for the communications. Only one character is ever -transmitted. */ -#define mainCOMMS_QUEUE_LENGTH ( ( unsigned portCHAR ) 5 ) -#define mainNO_BLOCK ( ( portTickType ) 0 ) -#define mainBAUD_RATE ( ( unsigned portLONG ) 57600 ) - -/* - * The task function for the "Check" task. - */ -static portTASK_FUNCTION_PROTO( vErrorChecks, pvParameters ); - -/* - * Checks the unique counts of other tasks to ensure they are still operational. - * Returns pdTRUE if an error is detected, otherwise pdFALSE. - */ -static portCHAR prvCheckOtherTasksAreStillRunning( void ); - -/*-----------------------------------------------------------*/ - -/* Creates the tasks, then starts the scheduler. */ -void main( void ) -{ - /* Initialise the required hardware. */ - vParTestInitialise(); - - /* Send a character so we have some visible feedback of a reset. */ - xSerialPortInitMinimal( mainBAUD_RATE, mainCOMMS_QUEUE_LENGTH ); - xSerialPutChar( NULL, 'X', mainNO_BLOCK ); - - /* Start a few of the standard demo tasks found in the demo\common directory. */ - vStartLEDFlashTasks( mainLED_FLASH_PRIORITY ); - - /* Start the check task defined in this file. */ - xTaskCreate( vErrorChecks, ( const portCHAR * const ) "Check", portMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - - /* This task has to be created last as it keeps account of the number of tasks - it expects to see running. */ - vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); - - /* Start the scheduler. Will never return here. */ - vTaskStartScheduler(); - - while(1) /* This point should never be reached. */ - { - } -} -/*-----------------------------------------------------------*/ - -static portTASK_FUNCTION( vErrorChecks, pvParameters ) -{ -portTickType xLastCheckTime; -portTickType xDelayTime = mainNO_ERROR_CHECK_PERIOD; -portCHAR cErrorOccurred; - - /* We need to initialise xLastCheckTime prior to the first call to - vTaskDelayUntil(). */ - xLastCheckTime = xTaskGetTickCount(); - - /* Cycle for ever, delaying then checking all the other tasks are still - operating without error. */ - for( ;; ) - { - /* Wait until it is time to check the other tasks again. */ - vTaskDelayUntil( &xLastCheckTime, xDelayTime ); - - /* Check all the other tasks are running, and running without ever - having an error. */ - cErrorOccurred = prvCheckOtherTasksAreStillRunning(); - - /* If an error was detected increase the frequency of the LED flash. */ - if( cErrorOccurred == pdTRUE ) - { - xDelayTime = mainERROR_CHECK_PERIOD; - } - - /* Flash the LED for visual feedback. */ - vParTestToggleLED( mainCHECK_TASK_LED ); - } -} -/*-----------------------------------------------------------*/ - -static portCHAR prvCheckOtherTasksAreStillRunning( void ) -{ - portCHAR cErrorHasOccurred = ( portCHAR ) pdFALSE; - - if( xIsCreateTaskStillRunning() != pdTRUE ) - { - cErrorHasOccurred = ( portCHAR ) pdTRUE; - } - - return cErrorHasOccurred; -} -/*-----------------------------------------------------------*/ - - diff --git a/Demo/PIC18_WizC/ParTest/ParTest.c b/Demo/PIC18_WizC/ParTest/ParTest.c deleted file mode 100644 index b245c92f0..000000000 --- a/Demo/PIC18_WizC/ParTest/ParTest.c +++ /dev/null @@ -1,125 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V3.0.0 - -Changes from V3.0.1 -*/ - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include - -#include "partest.h" - -/*----------------------------------------------------------- - * Simple parallel port IO routines for the FED 40pin demo board. - * The four LED's are connected to D4 to D7. - *-----------------------------------------------------------*/ - -#define partstBIT_AS_OUTPUT ( ( unsigned portSHORT ) 0 ) -#define partstSET_OUTPUT ( ( unsigned portSHORT ) 1 ) -#define partstCLEAR_OUTPUT ( ( unsigned portSHORT ) 0 ) - -#define partstENABLE_GENERAL_IO ( ( unsigned portCHAR ) 7 ) - -/*-----------------------------------------------------------*/ - -void vParTestInitialise( void ) -{ - /* Set the top four bits of port D to output. */ - bTRD7 = partstBIT_AS_OUTPUT; - bTRD6 = partstBIT_AS_OUTPUT; - bTRD5 = partstBIT_AS_OUTPUT; - bTRD4 = partstBIT_AS_OUTPUT; - - /* Start with all bits off. */ - bRD7 = partstCLEAR_OUTPUT; - bRD6 = partstCLEAR_OUTPUT; - bRD5 = partstCLEAR_OUTPUT; - bRD4 = partstCLEAR_OUTPUT; - - /* Enable the driver. */ - ADCON1 = partstENABLE_GENERAL_IO; - bTRE2 = partstBIT_AS_OUTPUT; - bRE2 = partstSET_OUTPUT; -} -/*-----------------------------------------------------------*/ - -void vParTestSetLED( unsigned portCHAR ucLED, portCHAR cValue ) -{ - /* We are only using the top nibble, so LED 0 corresponds to bit 4. */ - vTaskSuspendAll(); - { - switch( ucLED ) - { - case 3 : bRD7 = ( portSHORT ) cValue; - break; - case 2 : bRD6 = ( portSHORT ) cValue; - break; - case 1 : bRD5 = ( portSHORT ) cValue; - break; - case 0 : bRD4 = ( portSHORT ) cValue; - break; - default : /* There are only 4 LED's. */ - break; - } - } - xTaskResumeAll(); -} -/*-----------------------------------------------------------*/ - -void vParTestToggleLED( unsigned portCHAR ucLED ) -{ - /* We are only using the top nibble, so LED 0 corresponds to bit 4. */ - vTaskSuspendAll(); - { - switch( ucLED ) - { - case 3 : bRD7 = !bRD7; - break; - case 2 : bRD6 = !bRD6; - break; - case 1 : bRD5 = !bRD5; - break; - case 0 : bRD4 = !bRD4 ); - break; - default : /* There are only 4 LED's. */ - break; - } - } - xTaskResumeAll(); -} - - - diff --git a/Demo/PIC18_WizC/serial/isrSerialRx.c b/Demo/PIC18_WizC/serial/isrSerialRx.c deleted file mode 100644 index ddcd831ae..000000000 --- a/Demo/PIC18_WizC/serial/isrSerialRx.c +++ /dev/null @@ -1,106 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V3.0.0 - + ISRcode pulled inline to reduce stack-usage. - - + Added functionality to only call vTaskSwitchContext() once - when handling multiple interruptsources in a single interruptcall. - - + Filename changed to a .c extension to allow stepping through code - using F7. - -Changes from V3.0.1 -*/ - -#ifndef _FREERTOS_SERIAL_ISRSERIALRX_C -#define _FREERTOS_SERIAL_ISRSERIALRX_C - -#define serCONTINUOUS_RX ( 1 ) -#define serCLEAR_OVERRUN ( 0 ) - -{ - /* - * Was the interrupt a byte being received? - */ - if( bRCIF && bRCIE) - { - /* - * Queue to interface between comms API and interrupt routine. - */ - extern xQueueHandle xRxedChars; - - /* - * Because we are not allowed to use local variables here, - * PRODL is (ab)used as temporary storage. This is allowed - * because this SFR will be restored before exiting the ISR. - */ - extern portCHAR cChar; - #pragma locate cChar &PRODL - - /* - * If there was a framing error, just get and ignore - * the character - */ - if( bFERR ) - { - cChar = RCREG; - } - else - { - /* - * Get the character and post it on the queue of Rxed - * characters. If the post causes a task to wake ask - * for a context switch as the woken task may have a - * higher priority than the task we have interrupted. - */ - cChar = RCREG; - - /* - * Clear any overrun errors. - */ - if( bOERR ) - { - bCREN = serCLEAR_OVERRUN; - bCREN = serCONTINUOUS_RX; - } - - if( xQueueSendFromISR( xRxedChars, ( const void * ) &cChar, pdFALSE ) ) - { - uxSwitchRequested = pdTRUE; - } - } - } -} - -#endif /* _FREERTOS_SERIAL_ISRSERIALRX_C */ diff --git a/Demo/PIC18_WizC/serial/isrSerialTx.c b/Demo/PIC18_WizC/serial/isrSerialTx.c deleted file mode 100644 index 9cd59496b..000000000 --- a/Demo/PIC18_WizC/serial/isrSerialTx.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V3.0.0 - + ISRcode pulled inline to reduce stack-usage. - - + Added functionality to only call vTaskSwitchContext() once - when handling multiple interruptsources in a single interruptcall. - - + Filename changed to a .c extension to allow stepping through code - using F7. - -Changes from V3.0.1 -*/ - -#ifndef _FREERTOS_SERIAL_ISRSERIALTX_C -#define _FREERTOS_SERIAL_ISRSERIALTX_C - -#define serINTERRUPT_DISABLED ( 0 ) - - -{ - /* - * Was the interrupt the Tx register becoming empty? - */ - if( bTXIF && bTXIE) - { - /* - * Queue to interface between comms API and interrupt routine. - */ - extern xQueueHandle xCharsForTx; - - /* - * Because we are not allowed to use local variables here, - * PRODL and PRODH are (ab)used as temporary storage. This - * is allowed because these SFR's will be restored before - * exiting the ISR. - */ - extern portCHAR cChar; - #pragma locate cChar &PRODL - extern portBASE_TYPE pxTaskWoken; - #pragma locate pxTaskWoken &PRODH - - if( xQueueReceiveFromISR( xCharsForTx, &cChar, &pxTaskWoken ) == pdTRUE ) - { - /* - * Send the next character queued for Tx. - */ - TXREG = cChar; - } - else - { - /* - * Queue empty, nothing to send. - */ - bTXIE = serINTERRUPT_DISABLED; - } - - /* - * If we woke another task, ask for a contextswitch - */ - if( pxTaskWoken == pdTRUE ) - { - uxSwitchRequested = pdTRUE; - } - } -} - -#endif /* _FREERTOS_SERIAL_ISRSERIALTX_C */ diff --git a/Demo/PIC18_WizC/serial/serial.c b/Demo/PIC18_WizC/serial/serial.c deleted file mode 100644 index 166f4c875..000000000 --- a/Demo/PIC18_WizC/serial/serial.c +++ /dev/null @@ -1,177 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V3.0.0 - + ISRcode removed. Is now pulled inline to reduce stack-usage. - -Changes from V3.0.1 -*/ - -/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER. */ - -/* Scheduler header files. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" - -#include "serial.h" - -/* Hardware pin definitions. */ -#define serTX_PIN bTRC6 -#define serRX_PIN bTRC7 - -/* Bit/register definitions. */ -#define serINPUT ( 1 ) -#define serOUTPUT ( 0 ) -#define serINTERRUPT_ENABLED ( 1 ) - -/* All ISR's use the PIC18 low priority interrupt. */ -#define serLOW_PRIORITY ( 0 ) - -/*-----------------------------------------------------------*/ - -/* Queues to interface between comms API and interrupt routines. */ -xQueueHandle xRxedChars; -xQueueHandle xCharsForTx; - -/*-----------------------------------------------------------*/ - -xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portCHAR ucQueueLength ) -{ - unsigned portSHORT usSPBRG; - - /* Create the queues used by the ISR's to interface to tasks. */ - xRxedChars = xQueueCreate( ucQueueLength, ( unsigned portBASE_TYPE ) sizeof( portCHAR ) ); - xCharsForTx = xQueueCreate( ucQueueLength, ( unsigned portBASE_TYPE ) sizeof( portCHAR ) ); - - portENTER_CRITICAL(); - - /* Setup the IO pins to enable the USART IO. */ - serTX_PIN = serINPUT; // YES really! See datasheet - serRX_PIN = serINPUT; - - /* Set the TX config register. */ - TXSTA = 0b00100000; - // ||||||||--bit0: TX9D = n/a - // |||||||---bit1: TRMT = ReadOnly - // ||||||----bit2: BRGH = High speed - // |||||-----bit3: SENDB = n/a - // ||||------bit4: SYNC = Asynchronous mode - // |||-------bit5: TXEN = Transmit enable - // ||--------bit6: TX9 = 8-bit transmission - // |---------bit7: CSRC = n/a - - /* Set the Receive config register. */ - RCSTA = 0b10010000; - // ||||||||--bit0: RX9D = ReadOnly - // |||||||---bit1: OERR = ReadOnly - // ||||||----bit2: FERR = ReadOnly - // |||||-----bit3: ADDEN = n/a - // ||||------bit4: CREN = Enable receiver - // |||-------bit5: SREN = n/a - // ||--------bit6: RX9 = 8-bit reception - // |---------bit7: SPEN = Serial port enabled - - /* Calculate the baud rate generator value. - We use low-speed (BRGH=0), the formula is - SPBRG = ( ( FOSC / Desired Baud Rate ) / 64 ) - 1 */ - usSPBRG = ( ( APROCFREQ / ulWantedBaud ) / 64 ) - 1; - if( usSPBRG > 255 ) - { - SPBRG = 255; - } - else - { - SPBRG = usSPBRG; - } - - /* Set the serial interrupts to use the same priority as the tick. */ - bTXIP = serLOW_PRIORITY; - bRCIP = serLOW_PRIORITY; - - /* Enable the Rx interrupt now, the Tx interrupt will get enabled when - we have data to send. */ - bRCIE = serINTERRUPT_ENABLED; - - portEXIT_CRITICAL(); - - /* Unlike other ports, this serial code does not allow for more than one - com port. We therefore don't return a pointer to a port structure and - can instead just return NULL. */ - return NULL; -} -/*-----------------------------------------------------------*/ - -xComPortHandle xSerialPortInit( eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits, unsigned portCHAR ucBufferLength ) -{ - /* This is not implemented in this port. - Use xSerialPortInitMinimal() instead. */ - return NULL; -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, portCHAR *pcRxedChar, portTickType xBlockTime ) -{ - /* Get the next character from the buffer. Return false if no characters - are available, or arrive before xBlockTime expires. */ - if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) - { - return ( portCHAR ) pdTRUE; - } - - return ( portCHAR ) pdFALSE; -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, portCHAR cOutChar, portTickType xBlockTime ) -{ - /* Return false if after the block time there is no room on the Tx queue. */ - if( xQueueSend( xCharsForTx, ( const void * ) &cOutChar, xBlockTime ) != ( portCHAR ) pdPASS ) - { - return pdFAIL; - } - - /* Turn interrupt on - ensure the compiler only generates a single - instruction for this. */ - bTXIE = serINTERRUPT_ENABLED; - - return pdPASS; -} -/*-----------------------------------------------------------*/ - -void vSerialClose( xComPortHandle xPort ) -{ - /* Not implemented for this port. - To implement, turn off the interrupts and delete the memory - allocated to the queues. */ -} diff --git a/Demo/PIC24_MPLAB/FreeRTOSConfig.h b/Demo/PIC24_MPLAB/FreeRTOSConfig.h deleted file mode 100644 index a1d5eab4f..000000000 --- a/Demo/PIC24_MPLAB/FreeRTOSConfig.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -#include - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 1 -#define configUSE_TICK_HOOK 0 -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 16000000 ) /* Fosc / 2 */ -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 ) -#define configMINIMAL_STACK_SIZE ( 105 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) 5120 ) -#define configMAX_TASK_NAME_LEN ( 4 ) -#define configUSE_TRACE_FACILITY 0 -#define configUSE_16_BIT_TICKS 1 -#define configIDLE_SHOULD_YIELD 1 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 1 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 0 -#define INCLUDE_vTaskDelete 0 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/PIC24_MPLAB/ParTest/ParTest.c b/Demo/PIC24_MPLAB/ParTest/ParTest.c deleted file mode 100644 index 760b1991f..000000000 --- a/Demo/PIC24_MPLAB/ParTest/ParTest.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* Scheduler includes. */ -#include "FreeRTOS.h" - -/* Demo app includes. */ -#include "partest.h" - -#define ptOUTPUT 0 -#define ptALL_OFF 0 - -/*----------------------------------------------------------- - * Simple parallel port IO routines. - *-----------------------------------------------------------*/ - -void vParTestInitialise( void ) -{ - /* The explorer 16 board has LED's on port A. All bits are set as output - so PORTA is read-modified-written directly. */ - TRISA = ptOUTPUT; - PORTA = ptALL_OFF; -} -/*-----------------------------------------------------------*/ - -void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) -{ -unsigned portBASE_TYPE uxLEDBit; - - /* Which port A bit is being modified? */ - uxLEDBit = 1 << uxLED; - - if( xValue ) - { - /* Turn the LED on. */ - portENTER_CRITICAL(); - { - PORTA |= uxLEDBit; - } - portEXIT_CRITICAL(); - } - else - { - /* Turn the LED off. */ - portENTER_CRITICAL(); - { - PORTA &= ~uxLEDBit; - } - portEXIT_CRITICAL(); - } -} -/*-----------------------------------------------------------*/ - -void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) -{ -unsigned portBASE_TYPE uxLEDBit; - - uxLEDBit = 1 << uxLED; - portENTER_CRITICAL(); - { - /* If the LED is already on - turn it off. If the LED is already - off, turn it on. */ - if( PORTA & uxLEDBit ) - { - PORTA &= ~uxLEDBit; - } - else - { - PORTA |= uxLEDBit; - } - } - portEXIT_CRITICAL(); -} - diff --git a/Demo/PIC24_MPLAB/RTOSDemo.mcs b/Demo/PIC24_MPLAB/RTOSDemo.mcs deleted file mode 100644 index ad85eb9d5..000000000 --- a/Demo/PIC24_MPLAB/RTOSDemo.mcs +++ /dev/null @@ -1,3 +0,0 @@ -[Header] -MagicCookie={0b13fe8c-dfe0-40eb-8900-6712719559a7} -Version=1.0 diff --git a/Demo/PIC24_MPLAB/RTOSDemo.mcw b/Demo/PIC24_MPLAB/RTOSDemo.mcw deleted file mode 100644 index acf1e014d..000000000 Binary files a/Demo/PIC24_MPLAB/RTOSDemo.mcw and /dev/null differ diff --git a/Demo/PIC24_MPLAB/RTOSDemo_PIC24.mcp b/Demo/PIC24_MPLAB/RTOSDemo_PIC24.mcp deleted file mode 100644 index e42a7e8d8..000000000 --- a/Demo/PIC24_MPLAB/RTOSDemo_PIC24.mcp +++ /dev/null @@ -1,67 +0,0 @@ -[HEADER] -magic_cookie={66E99B07-E706-4689-9E80-9B2582898A13} -file_version=1.0 -[PATH_INFO] -dir_src= -dir_bin= -dir_tmp= -dir_sin= -dir_inc=.;C:\E\Dev\FreeRTOS\Demo\Common\include;C:\E\Dev\FreeRTOS\Demo\PIC24_MPLAB;C:\E\Dev\FreeRTOS\source\include -dir_lib= -dir_lkr= -[CAT_FILTERS] -filter_src=*.s;*.c -filter_inc=*.h;*.inc -filter_obj=*.o -filter_lib=*.a -filter_lkr=*.gld -[OTHER_FILES] -file_000=no -file_001=no -file_002=no -file_003=no -file_004=no -file_005=no -file_006=no -file_007=no -file_008=no -file_009=no -file_010=no -file_011=no -file_012=no -file_013=no -file_014=no -file_015=no -file_016=no -file_017=no -file_018=no -file_019=no -[FILE_INFO] -file_000=main.c -file_001=..\..\source\list.c -file_002=..\..\source\queue.c -file_003=..\..\source\tasks.c -file_004=..\..\source\portable\MPLAB\PIC24_dsPIC\port.c -file_005=..\..\source\portable\MemMang\heap_1.c -file_006=..\Common\Minimal\BlockQ.c -file_007=..\..\source\croutine.c -file_008=..\Common\Minimal\crflash.c -file_009=ParTest\ParTest.c -file_010=..\Common\Minimal\blocktim.c -file_011=..\Common\Minimal\integer.c -file_012=..\Common\Minimal\comtest.c -file_013=serial\serial.c -file_014=..\..\source\include\semphr.h -file_015=..\..\source\include\task.h -file_016=..\..\source\include\croutine.h -file_017=..\..\source\include\queue.h -file_018=FreeRTOSConfig.h -file_019=p24FJ128GA010.gld -[SUITE_INFO] -suite_guid={479DDE59-4D56-455E-855E-FFF59A3DB57E} -suite_state= -[TOOL_SETTINGS] -TS{7D9C6ECE-785D-44CB-BA22-17BF2E119622}=-g -TS{25AC22BD-2378-4FDB-BFB6-7345A15512D3}=-g -Wall -DMPLAB_PIC24_PORT -mlarge-code -fomit-frame-pointer -fno-schedule-insns -fno-schedule-insns2 -TS{7DAC9A1D-4C45-45D6-B25A-D117C74E8F5A}=--defsym=__ICD2RAM=1 -Map="$(TARGETBASE).map" -o"$(TARGETBASE).$(TARGETSUFFIX)" -TS{509E5861-1E2A-483B-8B6B-CA8DB7F2DD78}= diff --git a/Demo/PIC24_MPLAB/RTOSDemo_PIC24.mcs b/Demo/PIC24_MPLAB/RTOSDemo_PIC24.mcs deleted file mode 100644 index ad85eb9d5..000000000 --- a/Demo/PIC24_MPLAB/RTOSDemo_PIC24.mcs +++ /dev/null @@ -1,3 +0,0 @@ -[Header] -MagicCookie={0b13fe8c-dfe0-40eb-8900-6712719559a7} -Version=1.0 diff --git a/Demo/PIC24_MPLAB/main.c b/Demo/PIC24_MPLAB/main.c deleted file mode 100644 index fb48840f2..000000000 --- a/Demo/PIC24_MPLAB/main.c +++ /dev/null @@ -1,421 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * Creates all the demo application tasks, then starts the scheduler. The WEB - * documentation provides more details of the standard demo application tasks. - * In addition to the standard demo tasks, the following tasks are defined - * within this file: - * - * "Register test" tasks - These tasks first set all the general purpose - * registers to a known value (with each register containing a different value) - * then test each general purpose register to ensure it still contains the - * set value. There are two register test tasks, with different values being - * used by each. The register test tasks will be preempted frequently due to - * their low priority. Setting then testing the value of each register in this - * manner ensures the context of the tasks is being correctly saved and then - * restored as the preemptive context switches occur. An error is flagged - * should any register be found to contain an unexpected value. In addition - * the register test tasks maintain a count of the number of times they cycle, - * so an error can also be flagged should the cycle count not increment as - * expected (indicating the the tasks are not executing at all). - * - * "Check" task - This only executes every three seconds but has the highest - * priority so is guaranteed to get processor time. Its main function is to - * check that all the other tasks are still operational. Each task maintains a - * unique count that is incremented each time the task successfully completes - * its function. Should any error occur within such a task the count is - * permanently halted. The check task inspects the count of each task to - * ensure it has changed since the last time the check task executed. If all - * the count variables have changed all the tasks are still executing error - * free, and the check task toggles the onboard LED. Should any task contain - * an error at any time check task cycle frequency is increased to 500ms, - * causing the LED toggle rate to increase from 3 seconds to 500ms and in so - * doing providing visual feedback that an error has occurred. - * - */ - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "croutine.h" - -/* Demo application includes. */ -#include "BlockQ.h" -#include "crflash.h" -#include "blocktim.h" -#include "integer.h" -#include "comtest2.h" -#include "partest.h" - -/* Demo task priorities. */ -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainCOM_TEST_PRIORITY ( 2 ) - -/* Delay between check task cycles when an error has/has not been detected. */ -#define mainNO_ERROR_DELAY ( ( portTickType ) 3000 / portTICK_RATE_MS ) -#define mainERROR_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS ) - -/* The number of flash co-routines to create. */ -#define mainNUM_FLASH_COROUTINES ( 3 ) - -/* Baud rate used by the comtest tasks. */ -#define mainCOM_TEST_BAUD_RATE ( 19200 ) - -/* The LED used by the comtest tasks. mainCOM_TEST_LED + 1 is also used. -See the comtest.c file for more information. */ -#define mainCOM_TEST_LED ( 4 ) - -/* The LED used by the check task. */ -#define mainCHECK_LED ( 7 ) - -/*-----------------------------------------------------------*/ - -/* - * The register test tasks as described at the top of this file. - */ -void xRegisterTest1( void *pvParameters ); -void xRegisterTest2( void *pvParameters ); - -/* - * The check task as described at the top of this file. - */ -static void vCheckTask( void *pvParameters ); - -/* - * Setup the processor ready for the demo. - */ -static void prvSetupHardware( void ); - -/*-----------------------------------------------------------*/ - -/* Variables used to detect errors within the register test tasks. */ -static volatile unsigned portSHORT usTest1CycleCounter = 0, usTest2CycleCounter = 0; -static unsigned portSHORT usPreviousTest1Count = 0, usPreviousTest2Count = 0; - -/* Set to pdTRUE should an error be detected in any of the standard demo tasks -or tasks defined within this file. */ -static unsigned portSHORT usErrorDetected = pdFALSE; - -/*-----------------------------------------------------------*/ - -/* - * Create the demo tasks then start the scheduler. - */ -int main( void ) -{ - /* Configure any hardware required for this demo. */ - prvSetupHardware(); - - /* Create the standard demo tasks. */ - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - vStartFlashCoRoutines( mainNUM_FLASH_COROUTINES ); - vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); - vCreateBlockTimeTasks(); - - /* Create the test tasks defined within this file. */ - xTaskCreate( xRegisterTest1, "Reg1", configMINIMAL_STACK_SIZE, ( void * ) &usTest1CycleCounter, tskIDLE_PRIORITY, NULL ); - xTaskCreate( xRegisterTest2, "Reg2", configMINIMAL_STACK_SIZE, ( void * ) &usTest2CycleCounter, tskIDLE_PRIORITY, NULL ); - xTaskCreate( vCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - - /* Finally start the scheduler. */ - vTaskStartScheduler(); - - /* Will only reach here if there is insufficient heap available to start - the scheduler. */ - return 0; -} -/*-----------------------------------------------------------*/ - -static void prvSetupHardware( void ) -{ - vParTestInitialise(); -} -/*-----------------------------------------------------------*/ - -static void vCheckTask( void *pvParameters ) -{ -portTickType xLastExecutionTime; - -/* Start with the no error delay. The long delay will cause the LED to flash -slowly. */ -portTickType xDelay = mainNO_ERROR_DELAY; - - /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() - works correctly. */ - xLastExecutionTime = xTaskGetTickCount(); - - for( ;; ) - { - /* Wait until it is time for the next cycle. */ - vTaskDelayUntil( &xLastExecutionTime, xDelay ); - - /* Has an error been found in any of the standard demo tasks? */ - - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - usErrorDetected = pdTRUE; - } - - if( xAreComTestTasksStillRunning() != pdTRUE ) - { - usErrorDetected = pdTRUE; - } - - if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) - { - usErrorDetected = pdTRUE; - } - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - usErrorDetected = pdTRUE; - } - - - /* Are the register test tasks still cycling? */ - - if( usTest1CycleCounter == usPreviousTest1Count ) - { - usErrorDetected = pdTRUE; - } - - if( usTest2CycleCounter == usPreviousTest2Count ) - { - usErrorDetected = pdTRUE; - } - - usPreviousTest2Count = usTest2CycleCounter; - usPreviousTest1Count = usTest1CycleCounter; - - - /* If an error has been detected in any task then the delay will be - reduced to increase the cycle rate of this task. This has the effect - of causing the LED to flash much faster giving a visual indication of - the error condition. */ - if( usErrorDetected != pdFALSE ) - { - xDelay = mainERROR_DELAY; - } - - /* Finally, toggle the LED before returning to delay to wait for the - next cycle. */ - vParTestToggleLED( mainCHECK_LED ); - } -} -/*-----------------------------------------------------------*/ - -void xRegisterTest1( void *pvParameters ) -{ -/* This static so as not to use the frame pointer. They are volatile -also to avoid it being stored in a register that we clobber during the test. */ -static unsigned portSHORT * volatile pusParameter; - - /* The variable incremented by this task is passed in as the parameter - even though it is defined within this file. This is just to test the - parameter passing mechanism. */ - pusParameter = pvParameters; - - for( ;; ) - { - /* Increment the variable to show this task is still cycling. */ - ( *pusParameter )++; - - /* Set the w registers to known values, then check that each register - contains the expected value. See the explanation at the top of this - file for more information. */ - asm volatile( "mov.w #0x0101, W0 \n" \ - "mov.w #0x0102, W1 \n" \ - "mov.w #0x0103, W2 \n" \ - "mov.w #0x0104, W3 \n" \ - "mov.w #0x0105, W4 \n" \ - "mov.w #0x0106, W5 \n" \ - "mov.w #0x0107, W6 \n" \ - "mov.w #0x0108, W7 \n" \ - "mov.w #0x0109, W8 \n" \ - "mov.w #0x010a, W9 \n" \ - "mov.w #0x010b, W10 \n" \ - "mov.w #0x010c, W11 \n" \ - "mov.w #0x010d, W12 \n" \ - "mov.w #0x010e, W13 \n" \ - "mov.w #0x010f, W14 \n" \ - "sub #0x0101, W0 \n" \ - "cp0.w W0 \n" \ - "bra NZ, ERROR_TEST1 \n" \ - "sub #0x0102, W1 \n" \ - "cp0.w W1 \n" \ - "bra NZ, ERROR_TEST1 \n" \ - "sub #0x0103, W2 \n" \ - "cp0.w W2 \n" \ - "bra NZ, ERROR_TEST1 \n" \ - "sub #0x0104, W3 \n" \ - "cp0.w W3 \n" \ - "bra NZ, ERROR_TEST1 \n" \ - "sub #0x0105, W4 \n" \ - "cp0.w W4 \n" \ - "bra NZ, ERROR_TEST1 \n" \ - "sub #0x0106, W5 \n" \ - "cp0.w W5 \n" \ - "bra NZ, ERROR_TEST1 \n" \ - "sub #0x0107, W6 \n" \ - "cp0.w W6 \n" \ - "bra NZ, ERROR_TEST1 \n" \ - "sub #0x0108, W7 \n" \ - "cp0.w W7 \n" \ - "bra NZ, ERROR_TEST1 \n" \ - "sub #0x0109, W8 \n" \ - "cp0.w W8 \n" \ - "bra NZ, ERROR_TEST1 \n" \ - "sub #0x010a, W9 \n" \ - "cp0.w W9 \n" \ - "bra NZ, ERROR_TEST1 \n" \ - "sub #0x010b, W10 \n" \ - "cp0.w W10 \n" \ - "bra NZ, ERROR_TEST1 \n" \ - "sub #0x010c, W11 \n" \ - "cp0.w W11 \n" \ - "bra NZ, ERROR_TEST1 \n" \ - "sub #0x010d, W12 \n" \ - "cp0.w W12 \n" \ - "bra NZ, ERROR_TEST1 \n" \ - "sub #0x010e, W13 \n" \ - "cp0.w W13 \n" \ - "bra NZ, ERROR_TEST1 \n" \ - "sub #0x010f, W14 \n" \ - "cp0.w W14 \n" \ - "bra NZ, ERROR_TEST1 \n" \ - "bra NO_ERROR1 \n" \ - "ERROR_TEST1: \n" \ - "mov.w #1, W0 \n" \ - "mov.w W0, _usErrorDetected\n" \ - "NO_ERROR1: \n" ); - } -} -/*-----------------------------------------------------------*/ - -void xRegisterTest2( void *pvParameters ) -{ -/* This static so as not to use the frame pointer. They are volatile -also to avoid it being stored in a register that we clobber during the test. */ -static unsigned portSHORT * volatile pusParameter; - - /* The variable incremented by this task is passed in as the parameter - even though it is defined within this file. This is just to test the - parameter passing mechanism. */ - pusParameter = pvParameters; - - for( ;; ) - { - /* Increment the variable to show this task is still cycling. */ - ( *pusParameter )++; - - /* Set the w registers to known values, then check that each register - contains the expected value. See the explanation at the top of this - file for more information. */ - asm volatile( "mov.w #0x0100, W0 \n" \ - "mov.w #0x0101, W1 \n" \ - "mov.w #0x0102, W2 \n" \ - "mov.w #0x0103, W3 \n" \ - "mov.w #0x0104, W4 \n" \ - "mov.w #0x0105, W5 \n" \ - "mov.w #0x0106, W6 \n" \ - "mov.w #0x0107, W7 \n" \ - "mov.w #0x0108, W8 \n" \ - "mov.w #0x0109, W9 \n" \ - "mov.w #0x010a, W10 \n" \ - "mov.w #0x010b, W11 \n" \ - "mov.w #0x010c, W12 \n" \ - "mov.w #0x010d, W13 \n" \ - "mov.w #0x010e, W14 \n" \ - "sub #0x0100, W0 \n" \ - "cp0.w W0 \n" \ - "bra NZ, ERROR_TEST2 \n" \ - "sub #0x0101, W1 \n" \ - "cp0.w W1 \n" \ - "bra NZ, ERROR_TEST2 \n" \ - "sub #0x0102, W2 \n" \ - "cp0.w W2 \n" \ - "bra NZ, ERROR_TEST2 \n" \ - "sub #0x0103, W3 \n" \ - "cp0.w W3 \n" \ - "bra NZ, ERROR_TEST2 \n" \ - "sub #0x0104, W4 \n" \ - "cp0.w W4 \n" \ - "bra NZ, ERROR_TEST2 \n" \ - "sub #0x0105, W5 \n" \ - "cp0.w W5 \n" \ - "bra NZ, ERROR_TEST2 \n" \ - "sub #0x0106, W6 \n" \ - "cp0.w W6 \n" \ - "bra NZ, ERROR_TEST2 \n" \ - "sub #0x0107, W7 \n" \ - "cp0.w W7 \n" \ - "bra NZ, ERROR_TEST2 \n" \ - "sub #0x0108, W8 \n" \ - "cp0.w W8 \n" \ - "bra NZ, ERROR_TEST2 \n" \ - "sub #0x0109, W9 \n" \ - "cp0.w W9 \n" \ - "bra NZ, ERROR_TEST2 \n" \ - "sub #0x010a, W10 \n" \ - "cp0.w W10 \n" \ - "bra NZ, ERROR_TEST2 \n" \ - "sub #0x010b, W11 \n" \ - "cp0.w W11 \n" \ - "bra NZ, ERROR_TEST2 \n" \ - "sub #0x010c, W12 \n" \ - "cp0.w W12 \n" \ - "bra NZ, ERROR_TEST2 \n" \ - "sub #0x010d, W13 \n" \ - "cp0.w W13 \n" \ - "bra NZ, ERROR_TEST2 \n" \ - "sub #0x010e, W14 \n" \ - "cp0.w W14 \n" \ - "bra NZ, ERROR_TEST2 \n" \ - "bra NO_ERROR2 \n" \ - "ERROR_TEST2: \n" \ - "mov.w #1, W0 \n" \ - "mov.w W0, _usErrorDetected\n" \ - "NO_ERROR2: \n" ); - } -} -/*-----------------------------------------------------------*/ - -void vApplicationIdleHook( void ) -{ - /* Schedule the co-routines from within the idle task hook. */ - vCoRoutineSchedule(); -} -/*-----------------------------------------------------------*/ - diff --git a/Demo/PIC24_MPLAB/p24FJ128GA010.gld b/Demo/PIC24_MPLAB/p24FJ128GA010.gld deleted file mode 100644 index 630a066c9..000000000 --- a/Demo/PIC24_MPLAB/p24FJ128GA010.gld +++ /dev/null @@ -1,1333 +0,0 @@ -/* -** Linker script for PIC24FJ128GA010 -*/ - -OUTPUT_ARCH("24FJ128GA010") -EXTERN(__resetPRI) -EXTERN(__resetALT) - - -/* -** Memory Regions -*/ -MEMORY -{ - data (a!xr) : ORIGIN = 0x800, LENGTH = 0x2000 - reset : ORIGIN = 0x0, LENGTH = 0x4 - ivt : ORIGIN = 0x4, LENGTH = 0xFC - aivt : ORIGIN = 0x104, LENGTH = 0xFC - program (xr) : ORIGIN = 0x200, LENGTH = 0x155FC - config2 : ORIGIN = 0x157FC, LENGTH = 0x2 - config1 : ORIGIN = 0x157FE, LENGTH = 0x2 -} -__IVT_BASE = 0x4; -__AIVT_BASE = 0x104; -__DATA_BASE = 0x800; -__CODE_BASE = 0x200; - - -/* -** ==================== Section Map ====================== -*/ -SECTIONS -{ - /* - ** ========== Program Memory ========== - */ - - - /* - ** Reset Instruction - */ - .reset : - { - SHORT(ABSOLUTE(__reset)); - SHORT(0x04); - SHORT((ABSOLUTE(__reset) >> 16) & 0x7F); - SHORT(0); - } >reset - - - /* - ** Interrupt Vector Tables - ** - ** The primary and alternate tables are loaded - ** here, between sections .reset and .text. - ** Vector table source code appears below. - */ - - - /* - ** User Code and Library Code - */ - .text __CODE_BASE : - { - *(.handle); - *(.libc) *(.libm) *(.libdsp); /* keep together in this order */ - *(.lib*); - *(.text); - } >program - - - /* - ** Configuration Words - */ - __CONFIG2 : - { *(__CONFIG2.sec) } >config2 - __CONFIG1 : - { *(__CONFIG1.sec) } >config1 - - - /* - ** =========== Data Memory =========== - */ - - - /* - ** ICD Debug Exec - ** - ** This section provides optional storage for - ** the ICD2 debugger. Define a global symbol - ** named __ICD2RAM to enable ICD2. This section - ** must be loaded at data address 0x800. - */ - .icd __DATA_BASE (NOLOAD): - { - . += (DEFINED (__ICD2RAM) ? 0x50 : 0 ); - } > data - - - /* - ** Other sections in data memory are not explicitly mapped. - ** Instead they are allocated according to their section - ** attributes, which is most efficient. - ** - ** If a specific arrangement of sections is required - ** (other than what can be achieved using attributes) - ** additional sections may be defined here. See chapter - ** 10.5 in the MPLAB ASM30/LINK30 User's Guide (DS51317) - ** for more information. - */ - - - /* - ** ========== Debug Info ============== - */ - - .comment 0 : { *(.comment) } - - /* - ** DWARF-2 - */ - .debug_info 0 : { *(.debug_info) *(.gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_ranges 0 : { *(.debug_ranges) } - .debug_aranges 0 : { *(.debug_aranges) } - -} /* SECTIONS */ - -/* -** ================= End of Section Map ================ -*/ - -/* -** Section Map for Interrupt Vector Tables -*/ -SECTIONS -{ - -/* -** Interrupt Vector Table -*/ -.ivt __IVT_BASE : - { - LONG( DEFINED(__ReservedTrap0) ? ABSOLUTE(__ReservedTrap0) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__OscillatorFail) ? ABSOLUTE(__OscillatorFail) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__AddressError) ? ABSOLUTE(__AddressError) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__StackError) ? ABSOLUTE(__StackError) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__MathError) ? ABSOLUTE(__MathError) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__ReservedTrap5) ? ABSOLUTE(__ReservedTrap5) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__ReservedTrap6) ? ABSOLUTE(__ReservedTrap6) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__ReservedTrap7) ? ABSOLUTE(__ReservedTrap7) : - ABSOLUTE(__DefaultInterrupt)); - - LONG( DEFINED(__INT0Interrupt) ? ABSOLUTE(__INT0Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__IC1Interrupt) ? ABSOLUTE(__IC1Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__OC1Interrupt) ? ABSOLUTE(__OC1Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__T1Interrupt) ? ABSOLUTE(__T1Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt4) ? ABSOLUTE(__Interrupt4) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__IC2Interrupt) ? ABSOLUTE(__IC2Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__OC2Interrupt) ? ABSOLUTE(__OC2Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__T2Interrupt) ? ABSOLUTE(__T2Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__T3Interrupt) ? ABSOLUTE(__T3Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__SPI1ErrInterrupt) ? ABSOLUTE(__SPI1ErrInterrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__SPI1TInterrupt) ? ABSOLUTE(__SPI1TInterrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__U1RXInterrupt) ? ABSOLUTE(__U1RXInterrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__U1TXInterrupt) ? ABSOLUTE(__U1TXInterrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__ADC1Interrupt) ? ABSOLUTE(__ADC1Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt14) ? ABSOLUTE(__Interrupt14) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt15) ? ABSOLUTE(__Interrupt15) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__SI2C1Interrupt) ? ABSOLUTE(__SI2C1Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__MI2C1Interrupt) ? ABSOLUTE(__MI2C1Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__CompInterrupt) ? ABSOLUTE(__CompInterrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__CNInterrupt) ? ABSOLUTE(__CNInterrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__INT1Interrupt) ? ABSOLUTE(__INT1Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt21) ? ABSOLUTE(__Interrupt21) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt22) ? ABSOLUTE(__Interrupt22) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt23) ? ABSOLUTE(__Interrupt23) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt24) ? ABSOLUTE(__Interrupt24) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__OC3Interrupt) ? ABSOLUTE(__OC3Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__OC4Interrupt) ? ABSOLUTE(__OC4Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__T4Interrupt) ? ABSOLUTE(__T4Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__T5Interrupt) ? ABSOLUTE(__T5Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__INT2Interrupt) ? ABSOLUTE(__INT2Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__U2RXInterrupt) ? ABSOLUTE(__U2RXInterrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__U2TXInterrupt) ? ABSOLUTE(__U2TXInterrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__SPI2ErrInterrupt) ? ABSOLUTE(__SPI2ErrInterrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__SPI2Interrupt) ? ABSOLUTE(__SPI2Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt34) ? ABSOLUTE(__Interrupt34) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt35) ? ABSOLUTE(__Interrupt35) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt36) ? ABSOLUTE(__Interrupt36) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__IC3Interrupt) ? ABSOLUTE(__IC3Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__IC4Interrupt) ? ABSOLUTE(__IC4Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__IC5Interrupt) ? ABSOLUTE(__IC5Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt40) ? ABSOLUTE(__Interrupt40) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__OC5Interrupt) ? ABSOLUTE(__OC5Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt42) ? ABSOLUTE(__Interrupt42) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt43) ? ABSOLUTE(__Interrupt43) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt44) ? ABSOLUTE(__Interrupt44) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__PMPInterrupt) ? ABSOLUTE(__PMPInterrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt46) ? ABSOLUTE(__Interrupt46) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt47) ? ABSOLUTE(__Interrupt47) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt48) ? ABSOLUTE(__Interrupt48) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__SI2C2Interrupt) ? ABSOLUTE(__SI2C2Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__MI2C2Interrupt) ? ABSOLUTE(__MI2C2Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt51) ? ABSOLUTE(__Interrupt51) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt52) ? ABSOLUTE(__Interrupt52) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__INT3Interrupt) ? ABSOLUTE(__INT3Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__INT4Interrupt) ? ABSOLUTE(__INT4Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt55) ? ABSOLUTE(__Interrupt55) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt56) ? ABSOLUTE(__Interrupt56) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt57) ? ABSOLUTE(__Interrupt57) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt58) ? ABSOLUTE(__Interrupt58) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt59) ? ABSOLUTE(__Interrupt59) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt60) ? ABSOLUTE(__Interrupt60) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt61) ? ABSOLUTE(__Interrupt61) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__RTCCInterrupt) ? ABSOLUTE(__RTCCInterrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt63) ? ABSOLUTE(__Interrupt63) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt64) ? ABSOLUTE(__Interrupt64) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__U1ErrInterrupt) ? ABSOLUTE(__U1ErrInterrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__U2ErrInterrupt) ? ABSOLUTE(__U2ErrInterrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__CRCInterrupt) ? ABSOLUTE(__CRCInterrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt68) ? ABSOLUTE(__Interrupt68) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt69) ? ABSOLUTE(__Interrupt69) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt70) ? ABSOLUTE(__Interrupt70) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt71) ? ABSOLUTE(__Interrupt71) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt72) ? ABSOLUTE(__Interrupt72) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt73) ? ABSOLUTE(__Interrupt73) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt74) ? ABSOLUTE(__Interrupt74) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt75) ? ABSOLUTE(__Interrupt75) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt76) ? ABSOLUTE(__Interrupt76) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt77) ? ABSOLUTE(__Interrupt77) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt78) ? ABSOLUTE(__Interrupt78) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt79) ? ABSOLUTE(__Interrupt79) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt80) ? ABSOLUTE(__Interrupt80) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt81) ? ABSOLUTE(__Interrupt81) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt82) ? ABSOLUTE(__Interrupt82) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt83) ? ABSOLUTE(__Interrupt83) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt84) ? ABSOLUTE(__Interrupt84) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt85) ? ABSOLUTE(__Interrupt85) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt86) ? ABSOLUTE(__Interrupt86) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt87) ? ABSOLUTE(__Interrupt87) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt88) ? ABSOLUTE(__Interrupt88) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt89) ? ABSOLUTE(__Interrupt89) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt90) ? ABSOLUTE(__Interrupt90) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt91) ? ABSOLUTE(__Interrupt91) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt92) ? ABSOLUTE(__Interrupt92) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt93) ? ABSOLUTE(__Interrupt93) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt94) ? ABSOLUTE(__Interrupt94) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt95) ? ABSOLUTE(__Interrupt95) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt96) ? ABSOLUTE(__Interrupt96) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt97) ? ABSOLUTE(__Interrupt97) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt98) ? ABSOLUTE(__Interrupt98) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt99) ? ABSOLUTE(__Interrupt99) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt100) ? ABSOLUTE(__Interrupt100) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt101) ? ABSOLUTE(__Interrupt101) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt102) ? ABSOLUTE(__Interrupt102) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt103) ? ABSOLUTE(__Interrupt103) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt104) ? ABSOLUTE(__Interrupt104) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt105) ? ABSOLUTE(__Interrupt105) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt106) ? ABSOLUTE(__Interrupt106) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt107) ? ABSOLUTE(__Interrupt107) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt108) ? ABSOLUTE(__Interrupt108) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt109) ? ABSOLUTE(__Interrupt109) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt110) ? ABSOLUTE(__Interrupt110) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt111) ? ABSOLUTE(__Interrupt111) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt112) ? ABSOLUTE(__Interrupt112) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt113) ? ABSOLUTE(__Interrupt113) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt114) ? ABSOLUTE(__Interrupt114) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt115) ? ABSOLUTE(__Interrupt115) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt116) ? ABSOLUTE(__Interrupt116) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt117) ? ABSOLUTE(__Interrupt117) : - ABSOLUTE(__DefaultInterrupt)); - } >ivt - - -/* -** Alternate Interrupt Vector Table -*/ -.aivt __AIVT_BASE : - { - LONG( DEFINED(__AltReservedTrap0) ? ABSOLUTE(__AltReservedTrap0) : - (DEFINED(__ReservedTrap0) ? ABSOLUTE(__ReservedTrap0) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltOscillatorFail) ? ABSOLUTE(__AltOscillatorFail) : - (DEFINED(__OscillatorFail) ? ABSOLUTE(__OscillatorFail) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltAddressError) ? ABSOLUTE(__AltAddressError) : - (DEFINED(__AddressError) ? ABSOLUTE(__AddressError) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltStackError) ? ABSOLUTE(__AltStackError) : - (DEFINED(__StackError) ? ABSOLUTE(__StackError) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltMathError) ? ABSOLUTE(__AltMathError) : - (DEFINED(__MathError) ? ABSOLUTE(__MathError) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltReservedTrap5) ? ABSOLUTE(__AltReservedTrap5) : - (DEFINED(__ReservedTrap5) ? ABSOLUTE(__ReservedTrap5) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltReservedTrap6) ? ABSOLUTE(__AltReservedTrap6) : - (DEFINED(__ReservedTrap6) ? ABSOLUTE(__ReservedTrap6) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltReservedTrap7) ? ABSOLUTE(__AltReservedTrap7) : - (DEFINED(__ReservedTrap7) ? ABSOLUTE(__ReservedTrap7) : - ABSOLUTE(__DefaultInterrupt))); - - LONG( DEFINED(__AltINT0Interrupt) ? ABSOLUTE(__AltINT0Interrupt) : - (DEFINED(__INT0Interrupt) ? ABSOLUTE(__INT0Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltIC1Interrupt) ? ABSOLUTE(__AltIC1Interrupt) : - (DEFINED(__IC1Interrupt) ? ABSOLUTE(__IC1Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltOC1Interrupt) ? ABSOLUTE(__AltOC1Interrupt) : - (DEFINED(__OC1Interrupt) ? ABSOLUTE(__OC1Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltT1Interrupt) ? ABSOLUTE(__AltT1Interrupt) : - (DEFINED(__T1Interrupt) ? ABSOLUTE(__T1Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt4) ? ABSOLUTE(__AltInterrupt4) : - (DEFINED(__Interrupt4) ? ABSOLUTE(__Interrupt4) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltIC2Interrupt) ? ABSOLUTE(__AltIC2Interrupt) : - (DEFINED(__IC2Interrupt) ? ABSOLUTE(__IC2Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltOC2Interrupt) ? ABSOLUTE(__AltOC2Interrupt) : - (DEFINED(__OC2Interrupt) ? ABSOLUTE(__OC2Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltT2Interrupt) ? ABSOLUTE(__AltT2Interrupt) : - (DEFINED(__T2Interrupt) ? ABSOLUTE(__T2Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltT3Interrupt) ? ABSOLUTE(__AltT3Interrupt) : - (DEFINED(__T3Interrupt) ? ABSOLUTE(__T3Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltSPI1ErrInterrupt) ? ABSOLUTE(__AltSPI1ErrInterrupt) : - (DEFINED(__SPI1ErrInterrupt) ? ABSOLUTE(__SPI1ErrInterrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltSPI1TInterrupt) ? ABSOLUTE(__AltSPI1TInterrupt) : - (DEFINED(__SPI1TInterrupt) ? ABSOLUTE(__SPI1TInterrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltU1RXInterrupt) ? ABSOLUTE(__AltU1RXInterrupt) : - (DEFINED(__U1RXInterrupt) ? ABSOLUTE(__U1RXInterrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltU1TXInterrupt) ? ABSOLUTE(__AltU1TXInterrupt) : - (DEFINED(__U1TXInterrupt) ? ABSOLUTE(__U1TXInterrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltADC1Interrupt) ? ABSOLUTE(__AltADC1Interrupt) : - (DEFINED(__ADC1Interrupt) ? ABSOLUTE(__ADC1Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt14) ? ABSOLUTE(__AltInterrupt14) : - (DEFINED(__Interrupt14) ? ABSOLUTE(__Interrupt14) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt15) ? ABSOLUTE(__AltInterrupt15) : - (DEFINED(__Interrupt15) ? ABSOLUTE(__Interrupt15) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltSI2C1Interrupt) ? ABSOLUTE(__AltSI2C1Interrupt) : - (DEFINED(__SI2C1Interrupt) ? ABSOLUTE(__SI2C1Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltMI2C1Interrupt) ? ABSOLUTE(__AltMI2C1Interrupt) : - (DEFINED(__MI2C1Interrupt) ? ABSOLUTE(__MI2C1Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltCompInterrupt) ? ABSOLUTE(__AltCompInterrupt) : - (DEFINED(__CompInterrupt) ? ABSOLUTE(__CompInterrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltCNInterrupt) ? ABSOLUTE(__AltCNInterrupt) : - (DEFINED(__CNInterrupt) ? ABSOLUTE(__CNInterrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltINT1Interrupt) ? ABSOLUTE(__AltINT1Interrupt) : - (DEFINED(__INT1Interrupt) ? ABSOLUTE(__INT1Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt21) ? ABSOLUTE(__AltInterrupt21) : - (DEFINED(__Interrupt21) ? ABSOLUTE(__Interrupt21) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt22) ? ABSOLUTE(__AltInterrupt22) : - (DEFINED(__Interrupt22) ? ABSOLUTE(__Interrupt22) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt23) ? ABSOLUTE(__AltInterrupt23) : - (DEFINED(__Interrupt23) ? ABSOLUTE(__Interrupt23) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt24) ? ABSOLUTE(__AltInterrupt24) : - (DEFINED(__Interrupt24) ? ABSOLUTE(__Interrupt24) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltOC3Interrupt) ? ABSOLUTE(__AltOC3Interrupt) : - (DEFINED(__OC3Interrupt) ? ABSOLUTE(__OC3Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltOC4Interrupt) ? ABSOLUTE(__AltOC4Interrupt) : - (DEFINED(__OC4Interrupt) ? ABSOLUTE(__OC4Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltT4Interrupt) ? ABSOLUTE(__AltT4Interrupt) : - (DEFINED(__T4Interrupt) ? ABSOLUTE(__T4Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltT5Interrupt) ? ABSOLUTE(__AltT5Interrupt) : - (DEFINED(__T5Interrupt) ? ABSOLUTE(__T5Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltINT2Interrupt) ? ABSOLUTE(__AltINT2Interrupt) : - (DEFINED(__INT2Interrupt) ? ABSOLUTE(__INT2Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltU2RXInterrupt) ? ABSOLUTE(__AltU2RXInterrupt) : - (DEFINED(__U2RXInterrupt) ? ABSOLUTE(__U2RXInterrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltU2TXInterrupt) ? ABSOLUTE(__AltU2TXInterrupt) : - (DEFINED(__U2TXInterrupt) ? ABSOLUTE(__U2TXInterrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltSPI2ErrInterrupt) ? ABSOLUTE(__AltSPI2ErrInterrupt) : - (DEFINED(__SPI2ErrInterrupt) ? ABSOLUTE(__SPI2ErrInterrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltSPI2Interrupt) ? ABSOLUTE(__AltSPI2Interrupt) : - (DEFINED(__SPI2Interrupt) ? ABSOLUTE(__SPI2Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt34) ? ABSOLUTE(__AltInterrupt34) : - (DEFINED(__Interrupt34) ? ABSOLUTE(__Interrupt34) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt35) ? ABSOLUTE(__AltInterrupt35) : - (DEFINED(__Interrupt35) ? ABSOLUTE(__Interrupt35) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt36) ? ABSOLUTE(__AltInterrupt36) : - (DEFINED(__Interrupt36) ? ABSOLUTE(__Interrupt36) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltIC3Interrupt) ? ABSOLUTE(__AltIC3Interrupt) : - (DEFINED(__IC3Interrupt) ? ABSOLUTE(__IC3Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltIC4Interrupt) ? ABSOLUTE(__AltIC4Interrupt) : - (DEFINED(__IC4Interrupt) ? ABSOLUTE(__IC4Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltIC5Interrupt) ? ABSOLUTE(__AltIC5Interrupt) : - (DEFINED(__IC5Interrupt) ? ABSOLUTE(__IC5Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt40) ? ABSOLUTE(__AltInterrupt40) : - (DEFINED(__Interrupt40) ? ABSOLUTE(__Interrupt40) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltOC5Interrupt) ? ABSOLUTE(__AltOC5Interrupt) : - (DEFINED(__OC5Interrupt) ? ABSOLUTE(__OC5Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt42) ? ABSOLUTE(__AltInterrupt42) : - (DEFINED(__Interrupt42) ? ABSOLUTE(__Interrupt42) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt43) ? ABSOLUTE(__AltInterrupt43) : - (DEFINED(__Interrupt43) ? ABSOLUTE(__Interrupt43) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt44) ? ABSOLUTE(__AltInterrupt44) : - (DEFINED(__Interrupt44) ? ABSOLUTE(__Interrupt44) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltPMPInterrupt) ? ABSOLUTE(__AltPMPInterrupt) : - (DEFINED(__PMPInterrupt) ? ABSOLUTE(__PMPInterrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt46) ? ABSOLUTE(__AltInterrupt46) : - (DEFINED(__Interrupt46) ? ABSOLUTE(__Interrupt46) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt47) ? ABSOLUTE(__AltInterrupt47) : - (DEFINED(__Interrupt47) ? ABSOLUTE(__Interrupt47) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt48) ? ABSOLUTE(__AltInterrupt48) : - (DEFINED(__Interrupt48) ? ABSOLUTE(__Interrupt48) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltSI2C2Interrupt) ? ABSOLUTE(__AltSI2C2Interrupt) : - (DEFINED(__SI2C2Interrupt) ? ABSOLUTE(__SI2C2Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltMI2C2Interrupt) ? ABSOLUTE(__AltMI2C2Interrupt) : - (DEFINED(__MI2C2Interrupt) ? ABSOLUTE(__MI2C2Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt51) ? ABSOLUTE(__AltInterrupt51) : - (DEFINED(__Interrupt51) ? ABSOLUTE(__Interrupt51) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt52) ? ABSOLUTE(__AltInterrupt52) : - (DEFINED(__Interrupt52) ? ABSOLUTE(__Interrupt52) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltINT3Interrupt) ? ABSOLUTE(__AltINT3Interrupt) : - (DEFINED(__INT3Interrupt) ? ABSOLUTE(__INT3Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltINT4Interrupt) ? ABSOLUTE(__AltINT4Interrupt) : - (DEFINED(__INT4Interrupt) ? ABSOLUTE(__INT4Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt55) ? ABSOLUTE(__AltInterrupt55) : - (DEFINED(__Interrupt55) ? ABSOLUTE(__Interrupt55) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt56) ? ABSOLUTE(__AltInterrupt56) : - (DEFINED(__Interrupt56) ? ABSOLUTE(__Interrupt56) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt57) ? ABSOLUTE(__AltInterrupt57) : - (DEFINED(__Interrupt57) ? ABSOLUTE(__Interrupt57) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt58) ? ABSOLUTE(__AltInterrupt58) : - (DEFINED(__Interrupt58) ? ABSOLUTE(__Interrupt58) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt59) ? ABSOLUTE(__AltInterrupt59) : - (DEFINED(__Interrupt59) ? ABSOLUTE(__Interrupt59) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt60) ? ABSOLUTE(__AltInterrupt60) : - (DEFINED(__Interrupt60) ? ABSOLUTE(__Interrupt60) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt61) ? ABSOLUTE(__AltInterrupt61) : - (DEFINED(__Interrupt61) ? ABSOLUTE(__Interrupt61) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltRTCCInterrupt) ? ABSOLUTE(__AltRTCCInterrupt) : - (DEFINED(__RTCCInterrupt) ? ABSOLUTE(__RTCCInterrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt63) ? ABSOLUTE(__AltInterrupt63) : - (DEFINED(__Interrupt63) ? ABSOLUTE(__Interrupt63) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt64) ? ABSOLUTE(__AltInterrupt64) : - (DEFINED(__Interrupt64) ? ABSOLUTE(__Interrupt64) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltU1ErrInterrupt) ? ABSOLUTE(__AltU1ErrInterrupt) : - (DEFINED(__U1ErrInterrupt) ? ABSOLUTE(__U1ErrInterrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltU2ErrInterrupt) ? ABSOLUTE(__AltU2ErrInterrupt) : - (DEFINED(__U2ErrInterrupt) ? ABSOLUTE(__U2ErrInterrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltCRCInterrupt) ? ABSOLUTE(__AltCRCInterrupt) : - (DEFINED(__CRCInterrupt) ? ABSOLUTE(__CRCInterrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt68) ? ABSOLUTE(__AltInterrupt68) : - (DEFINED(__Interrupt68) ? ABSOLUTE(__Interrupt68) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt69) ? ABSOLUTE(__AltInterrupt69) : - (DEFINED(__Interrupt69) ? ABSOLUTE(__Interrupt69) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt70) ? ABSOLUTE(__AltInterrupt70) : - (DEFINED(__Interrupt70) ? ABSOLUTE(__Interrupt70) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt71) ? ABSOLUTE(__AltInterrupt71) : - (DEFINED(__Interrupt71) ? ABSOLUTE(__Interrupt71) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt72) ? ABSOLUTE(__AltInterrupt72) : - (DEFINED(__Interrupt72) ? ABSOLUTE(__Interrupt72) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt73) ? ABSOLUTE(__AltInterrupt73) : - (DEFINED(__Interrupt73) ? ABSOLUTE(__Interrupt73) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt74) ? ABSOLUTE(__AltInterrupt74) : - (DEFINED(__Interrupt74) ? ABSOLUTE(__Interrupt74) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt75) ? ABSOLUTE(__AltInterrupt75) : - (DEFINED(__Interrupt75) ? ABSOLUTE(__Interrupt75) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt76) ? ABSOLUTE(__AltInterrupt76) : - (DEFINED(__Interrupt76) ? ABSOLUTE(__Interrupt76) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt77) ? ABSOLUTE(__AltInterrupt77) : - (DEFINED(__Interrupt77) ? ABSOLUTE(__Interrupt77) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt78) ? ABSOLUTE(__AltInterrupt78) : - (DEFINED(__Interrupt78) ? ABSOLUTE(__Interrupt78) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt79) ? ABSOLUTE(__AltInterrupt79) : - (DEFINED(__Interrupt79) ? ABSOLUTE(__Interrupt79) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt80) ? ABSOLUTE(__AltInterrupt80) : - (DEFINED(__Interrupt80) ? ABSOLUTE(__Interrupt80) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt81) ? ABSOLUTE(__AltInterrupt81) : - (DEFINED(__Interrupt81) ? ABSOLUTE(__Interrupt81) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt82) ? ABSOLUTE(__AltInterrupt82) : - (DEFINED(__Interrupt82) ? ABSOLUTE(__Interrupt82) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt83) ? ABSOLUTE(__AltInterrupt83) : - (DEFINED(__Interrupt83) ? ABSOLUTE(__Interrupt83) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt84) ? ABSOLUTE(__AltInterrupt84) : - (DEFINED(__Interrupt84) ? ABSOLUTE(__Interrupt84) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt85) ? ABSOLUTE(__AltInterrupt85) : - (DEFINED(__Interrupt85) ? ABSOLUTE(__Interrupt85) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt86) ? ABSOLUTE(__AltInterrupt86) : - (DEFINED(__Interrupt86) ? ABSOLUTE(__Interrupt86) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt87) ? ABSOLUTE(__AltInterrupt87) : - (DEFINED(__Interrupt87) ? ABSOLUTE(__Interrupt87) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt88) ? ABSOLUTE(__AltInterrupt88) : - (DEFINED(__Interrupt88) ? ABSOLUTE(__Interrupt88) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt89) ? ABSOLUTE(__AltInterrupt89) : - (DEFINED(__Interrupt89) ? ABSOLUTE(__Interrupt89) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt90) ? ABSOLUTE(__AltInterrupt90) : - (DEFINED(__Interrupt90) ? ABSOLUTE(__Interrupt90) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt91) ? ABSOLUTE(__AltInterrupt91) : - (DEFINED(__Interrupt91) ? ABSOLUTE(__Interrupt91) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt92) ? ABSOLUTE(__AltInterrupt92) : - (DEFINED(__Interrupt92) ? ABSOLUTE(__Interrupt92) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt93) ? ABSOLUTE(__AltInterrupt93) : - (DEFINED(__Interrupt93) ? ABSOLUTE(__Interrupt93) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt94) ? ABSOLUTE(__AltInterrupt94) : - (DEFINED(__Interrupt94) ? ABSOLUTE(__Interrupt94) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt95) ? ABSOLUTE(__AltInterrupt95) : - (DEFINED(__Interrupt95) ? ABSOLUTE(__Interrupt95) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt96) ? ABSOLUTE(__AltInterrupt96) : - (DEFINED(__Interrupt96) ? ABSOLUTE(__Interrupt96) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt97) ? ABSOLUTE(__AltInterrupt97) : - (DEFINED(__Interrupt97) ? ABSOLUTE(__Interrupt97) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt98) ? ABSOLUTE(__AltInterrupt98) : - (DEFINED(__Interrupt98) ? ABSOLUTE(__Interrupt98) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt99) ? ABSOLUTE(__AltInterrupt99) : - (DEFINED(__Interrupt99) ? ABSOLUTE(__Interrupt99) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt100) ? ABSOLUTE(__AltInterrupt100) : - (DEFINED(__Interrupt100) ? ABSOLUTE(__Interrupt100) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt101) ? ABSOLUTE(__AltInterrupt101) : - (DEFINED(__Interrupt101) ? ABSOLUTE(__Interrupt101) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt102) ? ABSOLUTE(__AltInterrupt102) : - (DEFINED(__Interrupt102) ? ABSOLUTE(__Interrupt102) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt103) ? ABSOLUTE(__AltInterrupt103) : - (DEFINED(__Interrupt103) ? ABSOLUTE(__Interrupt103) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt104) ? ABSOLUTE(__AltInterrupt104) : - (DEFINED(__Interrupt104) ? ABSOLUTE(__Interrupt104) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt105) ? ABSOLUTE(__AltInterrupt105) : - (DEFINED(__Interrupt105) ? ABSOLUTE(__Interrupt105) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt106) ? ABSOLUTE(__AltInterrupt106) : - (DEFINED(__Interrupt106) ? ABSOLUTE(__Interrupt106) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt107) ? ABSOLUTE(__AltInterrupt107) : - (DEFINED(__Interrupt107) ? ABSOLUTE(__Interrupt107) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt108) ? ABSOLUTE(__AltInterrupt108) : - (DEFINED(__Interrupt108) ? ABSOLUTE(__Interrupt108) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt109) ? ABSOLUTE(__AltInterrupt109) : - (DEFINED(__Interrupt109) ? ABSOLUTE(__Interrupt109) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt110) ? ABSOLUTE(__AltInterrupt110) : - (DEFINED(__Interrupt110) ? ABSOLUTE(__Interrupt110) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt111) ? ABSOLUTE(__AltInterrupt111) : - (DEFINED(__Interrupt111) ? ABSOLUTE(__Interrupt111) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt112) ? ABSOLUTE(__AltInterrupt112) : - (DEFINED(__Interrupt112) ? ABSOLUTE(__Interrupt112) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt113) ? ABSOLUTE(__AltInterrupt113) : - (DEFINED(__Interrupt113) ? ABSOLUTE(__Interrupt113) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt114) ? ABSOLUTE(__AltInterrupt114) : - (DEFINED(__Interrupt114) ? ABSOLUTE(__Interrupt114) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt115) ? ABSOLUTE(__AltInterrupt115) : - (DEFINED(__Interrupt115) ? ABSOLUTE(__Interrupt115) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt116) ? ABSOLUTE(__AltInterrupt116) : - (DEFINED(__Interrupt116) ? ABSOLUTE(__Interrupt116) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt117) ? ABSOLUTE(__AltInterrupt117) : - (DEFINED(__Interrupt117) ? ABSOLUTE(__Interrupt117) : - ABSOLUTE(__DefaultInterrupt))); - } >aivt -} /* SECTIONS */ - - -/* -** ============== Equates for SFR Addresses ============= -*/ - - WREG0 = 0x0; -_WREG0 = 0x0; - WREG1 = 0x2; -_WREG1 = 0x2; - WREG2 = 0x4; -_WREG2 = 0x4; - WREG3 = 0x6; -_WREG3 = 0x6; - WREG4 = 0x8; -_WREG4 = 0x8; - WREG5 = 0xA; -_WREG5 = 0xA; - WREG6 = 0xC; -_WREG6 = 0xC; - WREG7 = 0xE; -_WREG7 = 0xE; - WREG8 = 0x10; -_WREG8 = 0x10; - WREG9 = 0x12; -_WREG9 = 0x12; - WREG10 = 0x14; -_WREG10 = 0x14; - WREG11 = 0x16; -_WREG11 = 0x16; - WREG12 = 0x18; -_WREG12 = 0x18; - WREG13 = 0x1A; -_WREG13 = 0x1A; - WREG14 = 0x1C; -_WREG14 = 0x1C; - WREG15 = 0x1E; -_WREG15 = 0x1E; - SPLIM = 0x20; -_SPLIM = 0x20; - PCL = 0x2E; -_PCL = 0x2E; - PCH = 0x30; -_PCH = 0x30; - TBLPAG = 0x32; -_TBLPAG = 0x32; - PSVPAG = 0x34; -_PSVPAG = 0x34; - RCOUNT = 0x36; -_RCOUNT = 0x36; - SR = 0x42; -_SR = 0x42; -_SRbits = 0x42; - CORCON = 0x44; -_CORCON = 0x44; -_CORCONbits = 0x44; - DISICNT = 0x52; -_DISICNT = 0x52; - CNEN1 = 0x60; -_CNEN1 = 0x60; -_CNEN1bits = 0x60; - CNEN2 = 0x62; -_CNEN2 = 0x62; -_CNEN2bits = 0x62; - CNPU1 = 0x68; -_CNPU1 = 0x68; -_CNPU1bits = 0x68; - CNPU2 = 0x6A; -_CNPU2 = 0x6A; -_CNPU2bits = 0x6A; - INTCON1 = 0x80; -_INTCON1 = 0x80; -_INTCON1bits = 0x80; - INTCON2 = 0x82; -_INTCON2 = 0x82; -_INTCON2bits = 0x82; - IFS0 = 0x84; -_IFS0 = 0x84; -_IFS0bits = 0x84; - IFS1 = 0x86; -_IFS1 = 0x86; -_IFS1bits = 0x86; - IFS2 = 0x88; -_IFS2 = 0x88; -_IFS2bits = 0x88; - IFS3 = 0x8A; -_IFS3 = 0x8A; -_IFS3bits = 0x8A; - IFS4 = 0x8C; -_IFS4 = 0x8C; -_IFS4bits = 0x8C; - IEC0 = 0x94; -_IEC0 = 0x94; -_IEC0bits = 0x94; - IEC1 = 0x96; -_IEC1 = 0x96; -_IEC1bits = 0x96; - IEC2 = 0x98; -_IEC2 = 0x98; -_IEC2bits = 0x98; - IEC3 = 0x9A; -_IEC3 = 0x9A; -_IEC3bits = 0x9A; - IEC4 = 0x9C; -_IEC4 = 0x9C; -_IEC4bits = 0x9C; - IPC0 = 0xA4; -_IPC0 = 0xA4; -_IPC0bits = 0xA4; - IPC1 = 0xA6; -_IPC1 = 0xA6; -_IPC1bits = 0xA6; - IPC2 = 0xA8; -_IPC2 = 0xA8; -_IPC2bits = 0xA8; - IPC3 = 0xAA; -_IPC3 = 0xAA; -_IPC3bits = 0xAA; - IPC4 = 0xAC; -_IPC4 = 0xAC; -_IPC4bits = 0xAC; - IPC5 = 0xAE; -_IPC5 = 0xAE; -_IPC5bits = 0xAE; - IPC6 = 0xB0; -_IPC6 = 0xB0; -_IPC6bits = 0xB0; - IPC7 = 0xB2; -_IPC7 = 0xB2; -_IPC7bits = 0xB2; - IPC8 = 0xB4; -_IPC8 = 0xB4; -_IPC8bits = 0xB4; - IPC9 = 0xB6; -_IPC9 = 0xB6; -_IPC9bits = 0xB6; - IPC10 = 0xB8; -_IPC10 = 0xB8; -_IPC10bits = 0xB8; - IPC11 = 0xBA; -_IPC11 = 0xBA; -_IPC11bits = 0xBA; - IPC12 = 0xBC; -_IPC12 = 0xBC; -_IPC12bits = 0xBC; - IPC13 = 0xBE; -_IPC13 = 0xBE; -_IPC13bits = 0xBE; - IPC15 = 0xC2; -_IPC15 = 0xC2; -_IPC15bits = 0xC2; - IPC16 = 0xC4; -_IPC16 = 0xC4; -_IPC16bits = 0xC4; - TMR1 = 0x100; -_TMR1 = 0x100; - PR1 = 0x102; -_PR1 = 0x102; - T1CON = 0x104; -_T1CON = 0x104; -_T1CONbits = 0x104; - TMR2 = 0x106; -_TMR2 = 0x106; - TMR3HLD = 0x108; -_TMR3HLD = 0x108; - TMR3 = 0x10A; -_TMR3 = 0x10A; - PR2 = 0x10C; -_PR2 = 0x10C; - PR3 = 0x10E; -_PR3 = 0x10E; - T2CON = 0x110; -_T2CON = 0x110; -_T2CONbits = 0x110; - T3CON = 0x112; -_T3CON = 0x112; -_T3CONbits = 0x112; - TMR4 = 0x114; -_TMR4 = 0x114; - TMR5HLD = 0x116; -_TMR5HLD = 0x116; - TMR5 = 0x118; -_TMR5 = 0x118; - PR4 = 0x11A; -_PR4 = 0x11A; - PR5 = 0x11C; -_PR5 = 0x11C; - T4CON = 0x11E; -_T4CON = 0x11E; -_T4CONbits = 0x11E; - T5CON = 0x120; -_T5CON = 0x120; -_T5CONbits = 0x120; - IC1BUF = 0x140; -_IC1BUF = 0x140; - IC1CON = 0x142; -_IC1CON = 0x142; -_IC1CONbits = 0x142; - IC2BUF = 0x144; -_IC2BUF = 0x144; - IC2CON = 0x146; -_IC2CON = 0x146; -_IC2CONbits = 0x146; - IC3BUF = 0x148; -_IC3BUF = 0x148; - IC3CON = 0x14A; -_IC3CON = 0x14A; -_IC3CONbits = 0x14A; - IC4BUF = 0x14C; -_IC4BUF = 0x14C; - IC4CON = 0x14E; -_IC4CON = 0x14E; -_IC4CONbits = 0x14E; - IC5BUF = 0x150; -_IC5BUF = 0x150; - IC5CON = 0x152; -_IC5CON = 0x152; -_IC5CONbits = 0x152; - OC1RS = 0x180; -_OC1RS = 0x180; - OC1R = 0x182; -_OC1R = 0x182; - OC1CON = 0x184; -_OC1CON = 0x184; -_OC1CONbits = 0x184; - OC2RS = 0x186; -_OC2RS = 0x186; - OC2R = 0x188; -_OC2R = 0x188; - OC2CON = 0x18A; -_OC2CON = 0x18A; -_OC2CONbits = 0x18A; - OC3RS = 0x18C; -_OC3RS = 0x18C; - OC3R = 0x18E; -_OC3R = 0x18E; - OC3CON = 0x190; -_OC3CON = 0x190; -_OC3CONbits = 0x190; - OC4RS = 0x192; -_OC4RS = 0x192; - OC4R = 0x194; -_OC4R = 0x194; - OC4CON = 0x196; -_OC4CON = 0x196; -_OC4CONbits = 0x196; - OC5RS = 0x198; -_OC5RS = 0x198; - OC5R = 0x19A; -_OC5R = 0x19A; - OC5CON = 0x19C; -_OC5CON = 0x19C; -_OC5CONbits = 0x19C; - I2C1RCV = 0x200; -_I2C1RCV = 0x200; - I2C1TRN = 0x202; -_I2C1TRN = 0x202; - I2C1BRG = 0x204; -_I2C1BRG = 0x204; - I2C1CON = 0x206; -_I2C1CON = 0x206; -_I2C1CONbits = 0x206; - I2C1STAT = 0x208; -_I2C1STAT = 0x208; -_I2C1STATbits = 0x208; - I2C1ADD = 0x20A; -_I2C1ADD = 0x20A; - I2C1MSK = 0x20C; -_I2C1MSK = 0x20C; - I2C2RCV = 0x210; -_I2C2RCV = 0x210; - I2C2TRN = 0x212; -_I2C2TRN = 0x212; - I2C2BRG = 0x214; -_I2C2BRG = 0x214; - I2C2CON = 0x216; -_I2C2CON = 0x216; -_I2C2CONbits = 0x216; - I2C2STAT = 0x218; -_I2C2STAT = 0x218; -_I2C2STATbits = 0x218; - I2C2ADD = 0x21A; -_I2C2ADD = 0x21A; - I2C2MSK = 0x21C; -_I2C2MSK = 0x21C; - U1MODE = 0x220; -_U1MODE = 0x220; -_U1MODEbits = 0x220; - U1STA = 0x222; -_U1STA = 0x222; -_U1STAbits = 0x222; - U1TXREG = 0x224; -_U1TXREG = 0x224; - U1RXREG = 0x226; -_U1RXREG = 0x226; - U1BRG = 0x228; -_U1BRG = 0x228; - U2MODE = 0x230; -_U2MODE = 0x230; -_U2MODEbits = 0x230; - U2STA = 0x232; -_U2STA = 0x232; -_U2STAbits = 0x232; - U2TXREG = 0x234; -_U2TXREG = 0x234; - U2RXREG = 0x236; -_U2RXREG = 0x236; - U2BRG = 0x238; -_U2BRG = 0x238; - SPI1STAT = 0x240; -_SPI1STAT = 0x240; -_SPI1STATbits = 0x240; - SPI1CON1 = 0x242; -_SPI1CON1 = 0x242; -_SPI1CON1bits = 0x242; - SPI1CON2 = 0x244; -_SPI1CON2 = 0x244; -_SPI1CON2bits = 0x244; - SPI1BUF = 0x248; -_SPI1BUF = 0x248; - SPI2STAT = 0x260; -_SPI2STAT = 0x260; -_SPI2STATbits = 0x260; - SPI2CON1 = 0x262; -_SPI2CON1 = 0x262; -_SPI2CON1bits = 0x262; - SPI2CON2 = 0x264; -_SPI2CON2 = 0x264; -_SPI2CON2bits = 0x264; - SPI2BUF = 0x268; -_SPI2BUF = 0x268; - TRISA = 0x2C0; -_TRISA = 0x2C0; -_TRISAbits = 0x2C0; - PORTA = 0x2C2; -_PORTA = 0x2C2; -_PORTAbits = 0x2C2; - LATA = 0x2C4; -_LATA = 0x2C4; -_LATAbits = 0x2C4; - TRISB = 0x2C6; -_TRISB = 0x2C6; -_TRISBbits = 0x2C6; - PORTB = 0x2C8; -_PORTB = 0x2C8; -_PORTBbits = 0x2C8; - LATB = 0x2CA; -_LATB = 0x2CA; -_LATBbits = 0x2CA; - TRISC = 0x2CC; -_TRISC = 0x2CC; -_TRISCbits = 0x2CC; - PORTC = 0x2CE; -_PORTC = 0x2CE; -_PORTCbits = 0x2CE; - LATC = 0x2D0; -_LATC = 0x2D0; -_LATCbits = 0x2D0; - TRISD = 0x2D2; -_TRISD = 0x2D2; -_TRISDbits = 0x2D2; - PORTD = 0x2D4; -_PORTD = 0x2D4; -_PORTDbits = 0x2D4; - LATD = 0x2D6; -_LATD = 0x2D6; -_LATDbits = 0x2D6; - TRISE = 0x2D8; -_TRISE = 0x2D8; -_TRISEbits = 0x2D8; - PORTE = 0x2DA; -_PORTE = 0x2DA; -_PORTEbits = 0x2DA; - LATE = 0x2DC; -_LATE = 0x2DC; -_LATEbits = 0x2DC; - TRISF = 0x2DE; -_TRISF = 0x2DE; -_TRISFbits = 0x2DE; - PORTF = 0x2E0; -_PORTF = 0x2E0; -_PORTFbits = 0x2E0; - LATF = 0x2E2; -_LATF = 0x2E2; -_LATFbits = 0x2E2; - TRISG = 0x2E4; -_TRISG = 0x2E4; -_TRISGbits = 0x2E4; - PORTG = 0x2E6; -_PORTG = 0x2E6; -_PORTGbits = 0x2E6; - LATG = 0x2E8; -_LATG = 0x2E8; -_LATGbits = 0x2E8; - PADCFG1 = 0x2FC; -_PADCFG1 = 0x2FC; -_PADCFG1bits = 0x2FC; - ADC1BUF0 = 0x300; -_ADC1BUF0 = 0x300; - ADC1BUF1 = 0x302; -_ADC1BUF1 = 0x302; - ADC1BUF2 = 0x304; -_ADC1BUF2 = 0x304; - ADC1BUF3 = 0x306; -_ADC1BUF3 = 0x306; - ADC1BUF4 = 0x308; -_ADC1BUF4 = 0x308; - ADC1BUF5 = 0x30A; -_ADC1BUF5 = 0x30A; - ADC1BUF6 = 0x30C; -_ADC1BUF6 = 0x30C; - ADC1BUF7 = 0x30E; -_ADC1BUF7 = 0x30E; - ADC1BUF8 = 0x310; -_ADC1BUF8 = 0x310; - ADC1BUF9 = 0x312; -_ADC1BUF9 = 0x312; - ADC1BUFA = 0x314; -_ADC1BUFA = 0x314; - ADC1BUFB = 0x316; -_ADC1BUFB = 0x316; - ADC1BUFC = 0x318; -_ADC1BUFC = 0x318; - ADC1BUFD = 0x31A; -_ADC1BUFD = 0x31A; - ADC1BUFE = 0x31C; -_ADC1BUFE = 0x31C; - ADC1BUFF = 0x31E; -_ADC1BUFF = 0x31E; - AD1CON1 = 0x320; -_AD1CON1 = 0x320; -_AD1CON1bits = 0x320; - AD1CON2 = 0x322; -_AD1CON2 = 0x322; -_AD1CON2bits = 0x322; - AD1CON3 = 0x324; -_AD1CON3 = 0x324; -_AD1CON3bits = 0x324; - AD1CHS = 0x328; -_AD1CHS = 0x328; -_AD1CHSbits = 0x328; - AD1PCFG = 0x32C; -_AD1PCFG = 0x32C; -_AD1PCFGbits = 0x32C; - AD1CSSL = 0x330; -_AD1CSSL = 0x330; -_AD1CSSLbits = 0x330; - PMCON = 0x600; -_PMCON = 0x600; -_PMCONbits = 0x600; - PMMODE = 0x602; -_PMMODE = 0x602; -_PMMODEbits = 0x602; - PMADDR = 0x604; -_PMADDR = 0x604; -_PMADDRbits = 0x604; - PMDOUT1 = 0x604; -_PMDOUT1 = 0x604; - PMDOUT2 = 0x606; -_PMDOUT2 = 0x606; - PMDIN1 = 0x608; -_PMDIN1 = 0x608; - PMDIN2 = 0x60A; -_PMDIN2 = 0x60A; - PMPEN = 0x60C; -_PMPEN = 0x60C; -_PMPENbits = 0x60C; - PMSTAT = 0x60E; -_PMSTAT = 0x60E; -_PMSTATbits = 0x60E; - ALRMVAL = 0x620; -_ALRMVAL = 0x620; - ALCFGRPT = 0x622; -_ALCFGRPT = 0x622; -_ALCFGRPTbits = 0x622; - RTCVAL = 0x624; -_RTCVAL = 0x624; - RCFGCAL = 0x626; -_RCFGCAL = 0x626; -_RCFGCALbits = 0x626; - CMCON = 0x630; -_CMCON = 0x630; -_CMCONbits = 0x630; - CVRCON = 0x632; -_CVRCON = 0x632; -_CVRCONbits = 0x632; - CRCCON = 0x640; -_CRCCON = 0x640; -_CRCCONbits = 0x640; - CRCXOR = 0x642; -_CRCXOR = 0x642; - CRCDAT = 0x644; -_CRCDAT = 0x644; - CRCWDAT = 0x646; -_CRCWDAT = 0x646; - ODCA = 0x6C0; -_ODCA = 0x6C0; -_ODCAbits = 0x6C0; - ODCB = 0x6C6; -_ODCB = 0x6C6; -_ODCBbits = 0x6C6; - ODCC = 0x6CC; -_ODCC = 0x6CC; -_ODCCbits = 0x6CC; - ODCD = 0x6D2; -_ODCD = 0x6D2; -_ODCDbits = 0x6D2; - ODCE = 0x6D8; -_ODCE = 0x6D8; -_ODCEbits = 0x6D8; - ODCF = 0x6DE; -_ODCF = 0x6DE; -_ODCFbits = 0x6DE; - ODCG = 0x6E4; -_ODCG = 0x6E4; -_ODCGbits = 0x6E4; - RCON = 0x740; -_RCON = 0x740; -_RCONbits = 0x740; - OSCCON = 0x742; -_OSCCON = 0x742; -_OSCCONbits = 0x742; - CLKDIV = 0x744; -_CLKDIV = 0x744; -_CLKDIVbits = 0x744; - OSCTUN = 0x748; -_OSCTUN = 0x748; -_OSCTUNbits = 0x748; - NVMCON = 0x760; -_NVMCON = 0x760; -_NVMCONbits = 0x760; - NVMKEY = 0x766; -_NVMKEY = 0x766; - PMD1 = 0x770; -_PMD1 = 0x770; -_PMD1bits = 0x770; - PMD2 = 0x772; -_PMD2 = 0x772; -_PMD2bits = 0x772; - PMD3 = 0x774; -_PMD3 = 0x774; -_PMD3bits = 0x774; diff --git a/Demo/PIC24_MPLAB/serial/serial.c b/Demo/PIC24_MPLAB/serial/serial.c deleted file mode 100644 index 32a11def5..000000000 --- a/Demo/PIC24_MPLAB/serial/serial.c +++ /dev/null @@ -1,235 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER. - -NOTE: This driver is primarily to test the scheduler functionality. It does -not effectively use the buffers or DMA and is therefore not intended to be -an example of an efficient driver. */ - -/* Standard include file. */ -#include - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "queue.h" -#include "task.h" - -/* Demo app include files. */ -#include "serial.h" - -/* Hardware setup. */ -#define serOUTPUT 0 -#define serINPUT 1 -#define serLOW_SPEED 0 -#define serONE_STOP_BIT 0 -#define serEIGHT_DATA_BITS_NO_PARITY 0 -#define serNORMAL_IDLE_STATE 0 -#define serAUTO_BAUD_OFF 0 -#define serLOOPBACK_OFF 0 -#define serWAKE_UP_DISABLE 0 -#define serNO_HARDWARE_FLOW_CONTROL 0 -#define serSTANDARD_IO 0 -#define serNO_IRDA 0 -#define serCONTINUE_IN_IDLE_MODE 0 -#define serUART_ENABLED 1 -#define serINTERRUPT_ON_SINGLE_CHAR 0 -#define serTX_ENABLE 1 -#define serINTERRUPT_ENABLE 1 -#define serINTERRUPT_DISABLE 0 -#define serCLEAR_FLAG 0 -#define serSET_FLAG 1 - - -/* The queues used to communicate between tasks and ISR's. */ -static xQueueHandle xRxedChars; -static xQueueHandle xCharsForTx; - -static portBASE_TYPE xTxHasEnded; -/*-----------------------------------------------------------*/ - -xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) -{ -portCHAR cChar; - - /* Create the queues used by the com test task. */ - xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); - xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); - - /* Setup the UART. */ - U2MODEbits.BRGH = serLOW_SPEED; - U2MODEbits.STSEL = serONE_STOP_BIT; - U2MODEbits.PDSEL = serEIGHT_DATA_BITS_NO_PARITY; - U2MODEbits.RXINV = serNORMAL_IDLE_STATE; - U2MODEbits.ABAUD = serAUTO_BAUD_OFF; - U2MODEbits.LPBACK = serLOOPBACK_OFF; - U2MODEbits.WAKE = serWAKE_UP_DISABLE; - U2MODEbits.UEN = serNO_HARDWARE_FLOW_CONTROL; - U2MODEbits.IREN = serNO_IRDA; - U2MODEbits.USIDL = serCONTINUE_IN_IDLE_MODE; - U2MODEbits.UARTEN = serUART_ENABLED; - - U2BRG = (unsigned portSHORT)(( (float)configCPU_CLOCK_HZ / ( (float)16 * (float)ulWantedBaud ) ) - (float)0.5); - - U2STAbits.URXISEL = serINTERRUPT_ON_SINGLE_CHAR; - U2STAbits.UTXEN = serTX_ENABLE; - U2STAbits.UTXINV = serNORMAL_IDLE_STATE; - U2STAbits.UTXISEL0 = serINTERRUPT_ON_SINGLE_CHAR; - U2STAbits.UTXISEL1 = serINTERRUPT_ON_SINGLE_CHAR; - - /* It is assumed that this function is called prior to the scheduler being - started. Therefore interrupts must not be allowed to occur yet as they - may attempt to perform a context switch. */ - portDISABLE_INTERRUPTS(); - - IFS1bits.U2RXIF = serCLEAR_FLAG; - IFS1bits.U2TXIF = serCLEAR_FLAG; - IPC7bits.U2RXIP = portKERNEL_INTERRUPT_PRIORITY; - IPC7bits.U2TXIP = portKERNEL_INTERRUPT_PRIORITY; - IEC1bits.U2TXIE = serINTERRUPT_ENABLE; - IEC1bits.U2RXIE = serINTERRUPT_ENABLE; - - /* Clear the Rx buffer. */ - while( U2STAbits.URXDA == serSET_FLAG ) - { - cChar = U2RXREG; - } - - xTxHasEnded = pdTRUE; - - return NULL; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) -{ - /* Only one port is supported. */ - ( void ) pxPort; - - /* Get the next character from the buffer. Return false if no characters - are available or arrive before xBlockTime expires. */ - if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) - { - return pdTRUE; - } - else - { - return pdFALSE; - } -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) -{ - /* Only one port is supported. */ - ( void ) pxPort; - - /* Return false if after the block time there is no room on the Tx queue. */ - if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) - { - return pdFAIL; - } - - /* A critical section should not be required as xTxHasEnded will not be - written to by the ISR if it is already 0 (is this correct?). */ - if( xTxHasEnded ) - { - xTxHasEnded = pdFALSE; - IFS1bits.U2TXIF = serSET_FLAG; - } - - return pdPASS; -} -/*-----------------------------------------------------------*/ - -void vSerialClose( xComPortHandle xPort ) -{ -} -/*-----------------------------------------------------------*/ - -volatile short s = 0; -char c[80] = {0}; - -void __attribute__((__interrupt__)) _U2RXInterrupt( void ) -{ -portCHAR cChar; -portBASE_TYPE xYieldRequired = pdFALSE; - - /* Get the character and post it on the queue of Rxed characters. - If the post causes a task to wake force a context switch as the woken task - may have a higher priority than the task we have interrupted. */ - IFS1bits.U2RXIF = serCLEAR_FLAG; - while( U2STAbits.URXDA ) - { - cChar = U2RXREG; - xYieldRequired = xQueueSendFromISR( xRxedChars, &cChar, xYieldRequired ); - } - - if( xYieldRequired != pdFALSE ) - { - taskYIELD(); - } -} -/*-----------------------------------------------------------*/ - -void __attribute__((__interrupt__)) _U2TXInterrupt( void ) -{ -signed portCHAR cChar; -portBASE_TYPE xTaskWoken = pdFALSE; - - /* If the transmit buffer is full we cannot get the next character. - Another interrupt will occur the next time there is space so this does - not matter. */ - IFS1bits.U2TXIF = serCLEAR_FLAG; - while( !( U2STAbits.UTXBF ) ) - { - if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWoken ) == pdTRUE ) - { - /* Send the next character queued for Tx. */ - U2TXREG = cChar; - } - else - { - /* Queue empty, nothing to send. */ - xTxHasEnded = pdTRUE; - break; - } - } - - if( xTaskWoken != pdFALSE ) - { - taskYIELD(); - } -} - - diff --git a/Demo/WizNET_DEMO_GCC_ARM7/FreeRTOSConfig.h b/Demo/WizNET_DEMO_GCC_ARM7/FreeRTOSConfig.h deleted file mode 100644 index 26b3064d6..000000000 --- a/Demo/WizNET_DEMO_GCC_ARM7/FreeRTOSConfig.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -#include - - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 58982400 ) /* =14.7456MHz xtal multiplied by 4 using the PLL. */ -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 23 * 1024 ) ) -#define configMAX_TASK_NAME_LEN ( 16 ) -#define configUSE_TRACE_FACILITY 0 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 1 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 - - - - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/WizNET_DEMO_GCC_ARM7/HTTP_Serv.c b/Demo/WizNET_DEMO_GCC_ARM7/HTTP_Serv.c deleted file mode 100644 index f0d12997c..000000000 --- a/Demo/WizNET_DEMO_GCC_ARM7/HTTP_Serv.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/* Standard includes. */ -#include - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Application includes. */ -#include "tcp.h" - -/* Misc constants. */ -#define tcpPOLL_DELAY ( ( portTickType ) 12 / portTICK_RATE_MS ) -#define tcpCONNECTION_DELAY ( ( portTickType ) 8 / portTICK_RATE_MS ) -/*-----------------------------------------------------------*/ - -/* - * This task initialises the hardware then processes one TCP connection at a - * time. When an HTTP client connects we just simply send a single page then - * disconnect - reset the socket data and wait for the next connection. - */ -void vHTTPServerTask( void *pvParameters ) -{ - /* Reset the network hardware. */ - vTCPHardReset(); - - /* Loop, processing connections are they arrive. */ - for( ;; ) - { - /* Initialise the TCP interface. - - The current minimal implementation does not check for buffer overflows - in the WIZnet hardware, so simply resets all the buffers for each - connection - and only processes one connection at a time. */ - if( lTCPSoftReset() ) - { - /* Create the socket that is going to accept incoming connections. */ - if( lTCPCreateSocket() ) - { - /* Wait for a connection. */ - vTCPListen(); - - /* Process connections as they arrive. This function will only - return once the connection has been closed. */ - lProcessConnection(); - } - } - - /* If we get here then the connection completed or failed. Wait a - while then try or start again. */ - vTaskDelay( tcpCONNECTION_DELAY ); - } -} - diff --git a/Demo/WizNET_DEMO_GCC_ARM7/HTTP_Serv.h b/Demo/WizNET_DEMO_GCC_ARM7/HTTP_Serv.h deleted file mode 100644 index e62011a99..000000000 --- a/Demo/WizNET_DEMO_GCC_ARM7/HTTP_Serv.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef HTTP_H -#define HTTP_H - -void vHTTPServerTask( void *pvParameters ); - -#endif diff --git a/Demo/WizNET_DEMO_GCC_ARM7/Makefile b/Demo/WizNET_DEMO_GCC_ARM7/Makefile deleted file mode 100644 index 385b36f10..000000000 --- a/Demo/WizNET_DEMO_GCC_ARM7/Makefile +++ /dev/null @@ -1,116 +0,0 @@ -# FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. -# -# This file is part of the FreeRTOS.org distribution. -# -# FreeRTOS.org is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# FreeRTOS.org is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with FreeRTOS.org; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -# -# A special exception to the GPL can be applied should you wish to distribute -# a combined work that includes FreeRTOS.org, without being obliged to provide -# the source code for any proprietary components. See the licensing section -# of http://www.FreeRTOS.org for full details of how and when the exception -# can be applied. -# -# *************************************************************************** -# See http://www.FreeRTOS.org for documentation, latest information, license -# and contact details. Please ensure to read the configuration and relevant -# port sections of the online documentation. -# *************************************************************************** - - -CC=arm-elf-gcc -OBJCOPY=arm-elf-objcopy -ARCH=arm-elf-ar -CRT0=boot.s -USE_THUMB_MODE=YES -DEBUG=-g -OPTIM=-Os -RUN_MODE=RUN_FROM_ROM -LDSCRIPT=lpc2106-rom.ld - - -# -# CFLAGS common to both the THUMB and ARM mode builds -# -CFLAGS=-Wall -D $(RUN_MODE) -D GCC_ARM7 -I. -I../../Source/include \ - -I../Common/include $(DEBUG) -mcpu=arm7tdmi -T$(LDSCRIPT) \ - -Wcast-align $(OPTIM) -fomit-frame-pointer - -ifeq ($(USE_THUMB_MODE),YES) - CFLAGS += -mthumb-interwork -D THUMB_INTERWORK - THUMB_FLAGS=-mthumb -endif - - -LINKER_FLAGS=-Xlinker -oWebServeDemo.elf -Xlinker -M -Xlinker -Map=WebServeDemo.map - -# -# Source files that can be built to THUMB mode. -# -THUMB_SRC = \ -../../Source/tasks.c \ -../../Source/queue.c \ -../../Source/list.c \ -../../Source/portable/MemMang/heap_2.c \ -../../Source/portable/GCC/ARM7_LPC2000/port.c \ -../Common/Minimal/flash.c \ -../Common/Minimal/dynamic.c \ -../Common/Minimal/semtest.c \ -../Common/Minimal/PollQ.c \ -../Common/Minimal/BlockQ.c \ -../Common/Minimal/integer.c \ -../ARM7_LPC2106_GCC/ParTest/ParTest.c \ -main.c \ -TCP.c \ -HTTP_Serv.c \ -i2c.c - -# -# Source files that must be built to ARM mode. -# -ARM_SRC = \ -../../Source/portable/GCC/ARM7_LPC2000/portISR.c \ -i2cISR.c \ -TCPISR.c - -# -# Define all object files. -# -ARM_OBJ = $(ARM_SRC:.c=.o) -THUMB_OBJ = $(THUMB_SRC:.c=.o) - -WebServeDemo.hex : WebServeDemo.elf - $(OBJCOPY) WebServeDemo.elf -O ihex WebServeDemo.hex - -WebServeDemo.elf : $(ARM_OBJ) $(THUMB_OBJ) $(CRT0) Makefile - $(CC) $(CFLAGS) $(ARM_OBJ) $(THUMB_OBJ) -nostartfiles $(CRT0) $(LINKER_FLAGS) - -$(THUMB_OBJ) : %.o : %.c $(LDSCRIPT) Makefile - $(CC) -c $(THUMB_FLAGS) $(CFLAGS) $< -o $@ - -$(ARM_OBJ) : %.o : %.c $(LDSCRIPT) Makefile - $(CC) -c $(CFLAGS) $< -o $@ - -clean : - touch makefile - - - - - - - - - - diff --git a/Demo/WizNET_DEMO_GCC_ARM7/TCP.c b/Demo/WizNET_DEMO_GCC_ARM7/TCP.c deleted file mode 100644 index 2c1de726f..000000000 --- a/Demo/WizNET_DEMO_GCC_ARM7/TCP.c +++ /dev/null @@ -1,740 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - Changes from V3.2.3 - - + Modified char* types to compile without warning when using GCC V4.0.1. - + Corrected the address to which the MAC address is written. Thanks to - Bill Knight for this correction. - - Changes from V3.2.4 - - + Changed the default MAC address to something more realistic. - -*/ - -/* Standard includes. */ -#include -#include - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" -#include "semphr.h" -#include "tcp.h" -#include "serial.h" - -/* Application includes. */ -#include "i2c.h" -#include "html_pages.h" - -/*-----------------------------------------------------------*/ - -/* Hardwired i2c address of the WIZNet device. */ -#define tcpDEVICE_ADDRESS ( ( unsigned portCHAR ) 0x00 ) - -/* Constants used to configure the Tx and Rx buffer sizes within the WIZnet -device. */ -#define tcp8K_RX ( ( unsigned portCHAR ) 0x03 ) -#define tcp8K_TX ( ( unsigned portCHAR ) 0x03 ) - -/* Constants used to generate the WIZnet internal buffer addresses. */ -#define tcpSINGLE_SOCKET_ADDR_MASK ( ( unsigned portLONG ) 0x1fff ) -#define tcpSINGLE_SOCKET_ADDR_OFFSET ( ( unsigned portLONG ) 0x4000 ) - -/* Bit definitions of the commands that can be sent to the command register. */ -#define tcpRESET_CMD ( ( unsigned portCHAR ) 0x80 ) -#define tcpSYS_INIT_CMD ( ( unsigned portCHAR ) 0x01 ) -#define tcpSOCK_STREAM ( ( unsigned portCHAR ) 0x01 ) -#define tcpSOCK_INIT ( ( unsigned portCHAR ) 0x02 ) -#define tcpLISTEN_CMD ( ( unsigned portCHAR ) 0x08 ) -#define tcpRECEIVE_CMD ( ( unsigned portCHAR ) 0x40 ) -#define tcpDISCONNECT_CMD ( ( unsigned portCHAR ) 0x10 ) -#define tcpSEND_CMD ( ( unsigned portCHAR ) 0x20 ) - -/* Constants required to handle the interrupts. */ -#define tcpCLEAR_EINT0 ( 1 ) -#define i2cCLEAR_ALL_INTERRUPTS ( ( unsigned portCHAR ) 0xff ) -#define i2cCHANNEL_0_ISR_ENABLE ( ( unsigned portCHAR ) 0x01 ) -#define i2cCHANNEL_0_ISR_DISABLE ( ( unsigned portCHAR ) 0x00 ) -#define tcpWAKE_ON_EINT0 ( 1 ) -#define tcpENABLE_EINT0_FUNCTION ( ( unsigned portLONG ) 0x01 ) -#define tcpEINT0_VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x4000 ) -#define tcpEINT0_VIC_CHANNEL ( ( unsigned portLONG ) 14 ) -#define tcpEINT0_VIC_ENABLE ( ( unsigned portLONG ) 0x0020 ) - -/* Various delays used in the driver. */ -#define tcpRESET_DELAY ( ( portTickType ) 16 / portTICK_RATE_MS ) -#define tcpINIT_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS ) -#define tcpLONG_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS ) -#define tcpSHORT_DELAY ( ( portTickType ) 5 / portTICK_RATE_MS ) -#define tcpCONNECTION_WAIT_DELAY ( ( portTickType ) 100 / portTICK_RATE_MS ) -#define tcpNO_DELAY ( ( portTickType ) 0 ) - -/* Length of the data to read for various register reads. */ -#define tcpSTATUS_READ_LEN ( ( unsigned portLONG ) 1 ) -#define tcpSHADOW_READ_LEN ( ( unsigned portLONG ) 1 ) - -/* Register addresses within the WIZnet device. */ -#define tcpCOMMAND_REG ( ( unsigned portSHORT ) 0x0000 ) -#define tcpGATEWAY_ADDR_REG ( ( unsigned portSHORT ) 0x0080 ) -#define tcpSUBNET_MASK_REG ( ( unsigned portSHORT ) 0x0084 ) -#define tcpSOURCE_HA_REG ( ( unsigned portSHORT ) 0x0088 ) -#define tpcSOURCE_IP_REG ( ( unsigned portSHORT ) 0x008E ) -#define tpcSOCKET_OPT_REG ( ( unsigned portSHORT ) 0x00A1 ) -#define tcpSOURCE_PORT_REG ( ( unsigned portSHORT ) 0x00AE ) -#define tcpTX_WRITE_POINTER_REG ( ( unsigned portSHORT ) 0x0040 ) -#define tcpTX_READ_POINTER_REG ( ( unsigned portSHORT ) 0x0044 ) -#define tcpTX_ACK_POINTER_REG ( ( unsigned portSHORT ) 0x0018 ) -#define tcpTX_MEM_SIZE_REG ( ( unsigned portSHORT ) 0x0096 ) -#define tcpRX_MEM_SIZE_REG ( ( unsigned portSHORT ) 0x0095 ) -#define tcpINTERRUPT_STATUS_REG ( ( unsigned portSHORT ) 0x0004 ) -#define tcpTX_WRITE_SHADOW_REG ( ( unsigned portSHORT ) 0x01F0 ) -#define tcpTX_ACK_SHADOW_REG ( ( unsigned portSHORT ) 0x01E2 ) -#define tcpISR_MASK_REG ( ( unsigned portSHORT ) 0x0009 ) -#define tcpINTERRUPT_REG ( ( unsigned portSHORT ) 0x0008 ) -#define tcpSOCKET_STATE_REG ( ( unsigned portSHORT ) 0x00a0 ) - -/* Constants required for hardware setup. */ -#define tcpRESET_ACTIVE_LOW ( ( unsigned portLONG ) 0x20 ) -#define tcpRESET_ACTIVE_HIGH ( ( unsigned portLONG ) 0x10 ) - -/* Constants defining the source of the WIZnet ISR. */ -#define tcpISR_SYS_INIT ( ( unsigned portCHAR ) 0x01 ) -#define tcpISR_SOCKET_INIT ( ( unsigned portCHAR ) 0x02 ) -#define tcpISR_ESTABLISHED ( ( unsigned portCHAR ) 0x04 ) -#define tcpISR_CLOSED ( ( unsigned portCHAR ) 0x08 ) -#define tcpISR_TIMEOUT ( ( unsigned portCHAR ) 0x10 ) -#define tcpISR_TX_COMPLETE ( ( unsigned portCHAR ) 0x20 ) -#define tcpISR_RX_COMPLETE ( ( unsigned portCHAR ) 0x40 ) - -/* Constants defining the socket status bits. */ -#define tcpSTATUS_ESTABLISHED ( ( unsigned portCHAR ) 0x06 ) -#define tcpSTATUS_LISTEN ( ( unsigned portCHAR ) 0x02 ) - -/* Misc constants. */ -#define tcpNO_STATUS_BITS ( ( unsigned portCHAR ) 0x00 ) -#define i2cNO_ADDR_REQUIRED ( ( unsigned portSHORT ) 0x0000 ) -#define i2cNO_DATA_REQUIRED ( 0x0000 ) -#define tcpISR_QUEUE_LENGTH ( ( unsigned portBASE_TYPE ) 10 ) -#define tcpISR_QUEUE_ITEM_SIZE ( ( unsigned portBASE_TYPE ) 0 ) -#define tcpBUFFER_LEN ( 4 * 1024 ) -#define tcpMAX_REGISTER_LEN ( 4 ) -#define tcpMAX_ATTEMPTS_TO_CHECK_BUFFER ( 6 ) -#define tcpMAX_NON_LISTEN_STAUS_READS ( 5 ) - -/* Message definitions. The IP address, MAC address, gateway address, etc. -is set here! */ -const unsigned portCHAR const ucDataGAR[] = { 172, 25, 218, 3 }; /* Gateway address. */ -const unsigned portCHAR const ucDataMSR[] = { 255, 255, 255, 0 }; /* Subnet mask. */ -const unsigned portCHAR const ucDataSIPR[] = { 172, 25, 218, 201 };/* IP address. */ -const unsigned portCHAR const ucDataSHAR[] = { 00, 23, 30, 41, 15, 26 }; /* MAC address - DO NOT USE THIS ON A PUBLIC NETWORK! */ - -/* Other fixed messages. */ -const unsigned portCHAR const ucDataReset[] = { tcpRESET_CMD }; -const unsigned portCHAR const ucDataInit[] = { tcpSYS_INIT_CMD }; -const unsigned portCHAR const ucDataProtocol[] = { tcpSOCK_STREAM }; -const unsigned portCHAR const ucDataPort[] = { 0xBA, 0xCC }; -const unsigned portCHAR const ucDataSockInit[] = { tcpSOCK_INIT }; -const unsigned portCHAR const ucDataTxWritePointer[] = { 0x11, 0x22, 0x00, 0x00 }; -const unsigned portCHAR const ucDataTxAckPointer[] = { 0x11, 0x22, 0x00, 0x00 }; -const unsigned portCHAR const ucDataTxReadPointer[] = { 0x11, 0x22, 0x00, 0x00 }; -const unsigned portCHAR const ucDataListen[] = { tcpLISTEN_CMD }; -const unsigned portCHAR const ucDataReceiveCmd[] = { tcpRECEIVE_CMD }; -const unsigned portCHAR const ucDataSetTxBufSize[] = { tcp8K_TX }; -const unsigned portCHAR const ucDataSetRxBufSize[] = { tcp8K_RX }; -const unsigned portCHAR const ucDataSend[] = { tcpSEND_CMD }; -const unsigned portCHAR const ucDataDisconnect[] = { tcpDISCONNECT_CMD }; -const unsigned portCHAR const ucDataEnableISR[] = { i2cCHANNEL_0_ISR_ENABLE }; -const unsigned portCHAR const ucDataDisableISR[] = { i2cCHANNEL_0_ISR_DISABLE }; -const unsigned portCHAR const ucDataClearInterrupt[] = { i2cCLEAR_ALL_INTERRUPTS }; - -static xSemaphoreHandle xMessageComplete = NULL; -xQueueHandle xTCPISRQueue = NULL; - -/* Dynamically generate and send an html page. */ -static void prvSendSamplePage( void ); - -/* Read a register from the WIZnet device via the i2c interface. */ -static void prvReadRegister( unsigned portCHAR *pucDestination, unsigned portSHORT usAddress, unsigned portLONG ulLength ); - -/* Send the entire Tx buffer (the Tx buffer within the WIZnet device). */ -static void prvFlushBuffer( unsigned portLONG ulTxAddress ); - -/* Write a string to the WIZnet Tx buffer. */ -static void prvWriteString( const portCHAR * const pucTxBuffer, portLONG lTxLen, unsigned portLONG *pulTxAddress ); - -/* Convert a number to a string. */ -void ultoa( unsigned portLONG ulVal, portCHAR *pcBuffer, portLONG lIgnore ); - -/*-----------------------------------------------------------*/ - -void ultoa( unsigned portLONG ulVal, portCHAR *pcBuffer, portLONG lIgnore ) -{ -unsigned portLONG lNibble; -portLONG lIndex; - - /* Simple routine to convert an unsigned long value into a string in hex - format. */ - - /* For each nibble in the number we are converting. */ - for( lIndex = 0; lIndex < ( sizeof( ulVal ) * 2 ); lIndex++ ) - { - /* Take the top four bits of the number. */ - lNibble = ( ulVal >> 28 ); - - /* We are converting it to a hex string, so is the number in the range - 0-10 or A-F? */ - if( lNibble < 10 ) - { - pcBuffer[ lIndex ] = '0' + lNibble; - } - else - { - lNibble -= 10; - pcBuffer[ lIndex ] = 'A' + lNibble; - } - - /* Shift off the top nibble so we use the next nibble next time around. */ - ulVal <<= 4; - } - - /* Mark the end of the string with a null terminator. */ - pcBuffer[ lIndex ] = 0x00; -} -/*-----------------------------------------------------------*/ - -static void prvReadRegister( unsigned portCHAR *pucDestination, unsigned portSHORT usAddress, unsigned portLONG ulLength ) -{ -unsigned portCHAR ucRxBuffer[ tcpMAX_REGISTER_LEN ]; - - /* Read a register value from the WIZnet device. */ - - /* First write out the address of the register we want to read. */ - i2cMessage( ucRxBuffer, i2cNO_DATA_REQUIRED, tcpDEVICE_ADDRESS, usAddress, i2cWRITE, NULL, portMAX_DELAY ); - - /* Then read back from that address. */ - i2cMessage( ( unsigned portCHAR * ) pucDestination, ulLength, tcpDEVICE_ADDRESS, i2cNO_ADDR_REQUIRED, i2cREAD, xMessageComplete, portMAX_DELAY ); - - /* I2C messages are queued so use the semaphore to wait for the read to - complete - otherwise we will leave this function before the I2C - transactions have completed. */ - xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ); -} -/*-----------------------------------------------------------*/ - -void vTCPHardReset( void ) -{ - /* Physical reset of the WIZnet device by using the GPIO lines to hold the - WIZnet reset lines active for a few milliseconds. */ - - /* Make sure the interrupt from the WIZnet is disabled. */ - VICIntEnClear |= tcpEINT0_VIC_CHANNEL_BIT; - - /* If xMessageComplete is NULL then this is the first time that this - function has been called and the queue and semaphore used in this file - have not yet been created. */ - if( xMessageComplete == NULL ) - { - /* Create and obtain the semaphore used when we want to wait for an i2c - message to be completed. */ - vSemaphoreCreateBinary( xMessageComplete ); - xSemaphoreTake( xMessageComplete, tcpNO_DELAY ); - - /* Create the queue used to communicate between the WIZnet and TCP tasks. */ - xTCPISRQueue = xQueueCreate( tcpISR_QUEUE_LENGTH, tcpISR_QUEUE_ITEM_SIZE ); - } - - /* Use the GPIO to reset the network hardware. */ - GPIO_IOCLR = tcpRESET_ACTIVE_LOW; - GPIO_IOSET = tcpRESET_ACTIVE_HIGH; - - /* Delay with the network hardware in reset for a short while. */ - vTaskDelay( tcpRESET_DELAY ); - - GPIO_IOCLR = tcpRESET_ACTIVE_HIGH; - GPIO_IOSET = tcpRESET_ACTIVE_LOW; - - vTaskDelay( tcpINIT_DELAY ); - - /* Setup the EINT0 to interrupt on required events from the WIZnet device. - First enable the EINT0 function of the pin. */ - PCB_PINSEL1 |= tcpENABLE_EINT0_FUNCTION; - - /* We want the TCP comms to wake us from power save. */ - SCB_EXTWAKE = tcpWAKE_ON_EINT0; - - /* Install the ISR into the VIC - but don't enable it yet! */ - portENTER_CRITICAL(); - { - extern void ( vEINT0_ISR )( void ); - - VICIntSelect &= ~( tcpEINT0_VIC_CHANNEL_BIT ); - VICVectAddr3 = ( portLONG ) vEINT0_ISR; - - VICVectCntl3 = tcpEINT0_VIC_CHANNEL | tcpEINT0_VIC_ENABLE; - } - portEXIT_CRITICAL(); - - /* Enable interrupts in the WIZnet itself. */ - i2cMessage( ucDataEnableISR, sizeof( ucDataEnableISR ), tcpDEVICE_ADDRESS, tcpISR_MASK_REG, i2cWRITE, NULL, portMAX_DELAY ); - - vTaskDelay( tcpLONG_DELAY ); -} -/*-----------------------------------------------------------*/ - -portLONG lTCPSoftReset( void ) -{ -unsigned portCHAR ucStatus; -extern volatile portLONG lTransactionCompleted; - - /* Send a message to the WIZnet device to tell it set all it's registers - back to their default states. Then setup the WIZnet device as required. */ - - /* Reset the internal WIZnet registers. */ - i2cMessage( ucDataReset, sizeof( ucDataReset ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY ); - - /* Now we can configure the protocol. Here the MAC address, gateway - address, subnet mask and IP address are configured. */ - i2cMessage( ucDataSHAR, sizeof( ucDataSHAR ), tcpDEVICE_ADDRESS, tcpSOURCE_HA_REG, i2cWRITE, NULL, portMAX_DELAY ); - i2cMessage( ucDataGAR, sizeof( ucDataGAR ), tcpDEVICE_ADDRESS, tcpGATEWAY_ADDR_REG, i2cWRITE, NULL, portMAX_DELAY ); - i2cMessage( ucDataMSR, sizeof( ucDataMSR ), tcpDEVICE_ADDRESS, tcpSUBNET_MASK_REG, i2cWRITE, NULL, portMAX_DELAY ); - i2cMessage( ucDataSIPR, sizeof( ucDataSIPR ), tcpDEVICE_ADDRESS, tpcSOURCE_IP_REG, i2cWRITE, NULL, portMAX_DELAY ); - - /* Next the memory buffers are configured to give all the WIZnet internal - memory over to a single socket. This gives the socket the maximum internal - Tx and Rx buffer space. */ - i2cMessage( ucDataSetTxBufSize, sizeof( ucDataSetTxBufSize ), tcpDEVICE_ADDRESS, tcpTX_MEM_SIZE_REG, i2cWRITE, NULL, portMAX_DELAY ); - i2cMessage( ucDataSetRxBufSize, sizeof( ucDataSetRxBufSize ), tcpDEVICE_ADDRESS, tcpRX_MEM_SIZE_REG, i2cWRITE, NULL, portMAX_DELAY ); - - /* Send the sys init command so the above parameters take effect. */ - i2cMessage( ucDataInit, sizeof( ucDataInit ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY ); - - /* Seems to like a little wait here. */ - vTaskDelay( tcpINIT_DELAY ); - - /* Read back the status to ensure the system initialised ok. */ - prvReadRegister( &ucStatus, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN ); - - /* We should find that the sys init was successful. */ - if( ucStatus != tcpISR_SYS_INIT ) - { - return ( portLONG ) pdFAIL; - } - - /* No i2c errors yet. */ - portENTER_CRITICAL(); - lTransactionCompleted = pdTRUE; - portEXIT_CRITICAL(); - - return ( portLONG ) pdPASS; -} -/*-----------------------------------------------------------*/ - -portLONG lTCPCreateSocket( void ) -{ -unsigned portCHAR ucStatus; - - /* Create and configure a socket. */ - - /* Setup and init the socket. Here the port number is set and the socket - is initialised. */ - i2cMessage( ucDataProtocol, sizeof( ucDataProtocol),tcpDEVICE_ADDRESS, tpcSOCKET_OPT_REG, i2cWRITE, NULL, portMAX_DELAY ); - i2cMessage( ucDataPort, sizeof( ucDataPort), tcpDEVICE_ADDRESS, tcpSOURCE_PORT_REG, i2cWRITE, NULL, portMAX_DELAY ); - i2cMessage( ucDataSockInit, sizeof( ucDataSockInit),tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, xMessageComplete, portMAX_DELAY ); - - /* Wait for the Init command to be sent. */ - if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) ) - { - /* For some reason the message was not transmitted within our block - period. */ - return ( portLONG ) pdFAIL; - } - - /* Allow the socket to initialise. */ - vTaskDelay( tcpINIT_DELAY ); - - /* Read back the status to ensure the socket initialised ok. */ - prvReadRegister( &ucStatus, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN ); - - /* We should find that the socket init was successful. */ - if( ucStatus != tcpISR_SOCKET_INIT ) - { - return ( portLONG ) pdFAIL; - } - - - /* Setup the Tx pointer registers to indicate that the Tx buffer is empty. */ - i2cMessage( ucDataTxReadPointer, sizeof( ucDataTxReadPointer ), tcpDEVICE_ADDRESS, tcpTX_READ_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY ); - vTaskDelay( tcpSHORT_DELAY ); - i2cMessage( ucDataTxWritePointer, sizeof( ucDataTxWritePointer ), tcpDEVICE_ADDRESS, tcpTX_WRITE_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY ); - vTaskDelay( tcpSHORT_DELAY ); - i2cMessage( ucDataTxAckPointer, sizeof( ucDataTxAckPointer ), tcpDEVICE_ADDRESS, tcpTX_ACK_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY ); - vTaskDelay( tcpSHORT_DELAY ); - - return ( portLONG ) pdPASS; -} -/*-----------------------------------------------------------*/ - -void vTCPListen( void ) -{ -unsigned portCHAR ucISR; - - /* Start a passive listen on the socket. */ - - /* Enable interrupts in the WizNet device after ensuring none are - currently pending. */ - while( SCB_EXTINT & tcpCLEAR_EINT0 ) - { - /* The WIZnet device is still asserting and interrupt so tell it to - clear. */ - i2cMessage( ucDataClearInterrupt, sizeof( ucDataClearInterrupt ), tcpDEVICE_ADDRESS, tcpINTERRUPT_REG, i2cWRITE, xMessageComplete, portMAX_DELAY ); - xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ); - - vTaskDelay( 1 ); - SCB_EXTINT = tcpCLEAR_EINT0; - } - - while( xQueueReceive( xTCPISRQueue, &ucISR, tcpNO_DELAY ) ) - { - /* Just clearing the queue used by the ISR routine to tell this task - that the WIZnet device needs attention. */ - } - - /* Now all the pending interrupts have been cleared we can enable the - processor interrupts. */ - VICIntEnable |= tcpEINT0_VIC_CHANNEL_BIT; - - /* Then start listening for incoming connections. */ - i2cMessage( ucDataListen, sizeof( ucDataListen ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY ); -} -/*-----------------------------------------------------------*/ - -portLONG lProcessConnection( void ) -{ -unsigned portCHAR ucISR, ucState, ucLastState = 2, ucShadow; -extern volatile portLONG lTransactionCompleted; -portLONG lSameStateCount = 0, lDataSent = pdFALSE; -unsigned portLONG ulWritePointer, ulAckPointer; - - /* No I2C errors can yet have occurred. */ - portENTER_CRITICAL(); - lTransactionCompleted = pdTRUE; - portEXIT_CRITICAL(); - - /* Keep looping - processing interrupts, until we have completed a - transaction. This uses the WIZnet in it's simplest form. The socket - accepts a connection - we process the connection - then close the socket. - We then go back to reinitialise everything and start again. */ - while( lTransactionCompleted == pdTRUE ) - { - /* Wait for a message on the queue from the WIZnet ISR. When the - WIZnet device asserts an interrupt the ISR simply posts a message - onto this queue to wake this task. */ - if( xQueueReceive( xTCPISRQueue, &ucISR, tcpCONNECTION_WAIT_DELAY ) ) - { - /* The ISR posted a message on this queue to tell us that the - WIZnet device asserted an interrupt. The ISR cannot process - an I2C message so cannot tell us what caused the interrupt so - we have to query the device here. This task is the highest - priority in the system so will run immediately following the ISR. */ - prvReadRegister( &ucISR, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN ); - - /* Once we have read what caused the ISR we can clear the interrupt - in the WIZnet. */ - i2cMessage( ucDataClearInterrupt, sizeof( ucDataClearInterrupt ), tcpDEVICE_ADDRESS, tcpINTERRUPT_REG, i2cWRITE, NULL, portMAX_DELAY ); - - /* Now we can clear the processor interrupt and re-enable ready for - the next. */ - SCB_EXTINT = tcpCLEAR_EINT0; - VICIntEnable |= tcpEINT0_VIC_CHANNEL_BIT; - - /* Process the interrupt ... */ - - if( ucISR & tcpISR_ESTABLISHED ) - { - /* A connection has been established - respond by sending - a receive command. */ - i2cMessage( ucDataReceiveCmd, sizeof( ucDataReceiveCmd ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY ); - } - - if( ucISR & tcpISR_RX_COMPLETE ) - { - /* We message has been received. This will be an HTTP get - command. We only have one page to send so just send it without - regard to what the actual requested page was. */ - prvSendSamplePage(); - } - - if( ucISR & tcpISR_TX_COMPLETE ) - { - /* We have a TX complete interrupt - which oddly does not - indicate that the message being sent is complete so we cannot - yet close the socket. Instead we read the position of the Tx - pointer within the WIZnet device so we know how much data it - has to send. Later we will read the ack pointer and compare - this to the Tx pointer to ascertain whether the transmission - has completed. */ - - /* First read the shadow register. */ - prvReadRegister( &ucShadow, tcpTX_WRITE_SHADOW_REG, tcpSHADOW_READ_LEN ); - - /* Now a short delay is required. */ - vTaskDelay( tcpSHORT_DELAY ); - - /* Then we can read the real register. */ - prvReadRegister( ( unsigned portCHAR * ) &ulWritePointer, tcpTX_WRITE_POINTER_REG, sizeof( ulWritePointer ) ); - - /* We cannot do anything more here but need to remember that - this interrupt has occurred. */ - lDataSent = pdTRUE; - } - - if( ucISR & tcpISR_CLOSED ) - { - /* The socket has been closed so we can leave this function. */ - lTransactionCompleted = pdFALSE; - } - } - else - { - /* We have not received an interrupt from the WIZnet device for a - while. Read the socket status and check that everything is as - expected. */ - prvReadRegister( &ucState, tcpSOCKET_STATE_REG, tcpSTATUS_READ_LEN ); - - if( ( ucState == tcpSTATUS_ESTABLISHED ) && ( lDataSent > 0 ) ) - { - /* The socket is established and we have already received a Tx - end interrupt. We must therefore be waiting for the Tx buffer - inside the WIZnet device to be empty before we can close the - socket. - - Read the Ack pointer register to see if it has caught up with - the Tx pointer register. First we have to read the shadow - register. */ - prvReadRegister( &ucShadow, tcpTX_ACK_SHADOW_REG, tcpSHADOW_READ_LEN ); - vTaskDelay( tcpSHORT_DELAY ); - prvReadRegister( ( unsigned portCHAR * ) &ulAckPointer, tcpTX_ACK_POINTER_REG, sizeof( ulWritePointer ) ); - - if( ulAckPointer == ulWritePointer ) - { - /* The Ack and write pointer are now equal and we can - safely close the socket. */ - i2cMessage( ucDataDisconnect, sizeof( ucDataDisconnect ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY ); - } - else - { - /* Keep a count of how many times we encounter the Tx - buffer still containing data. */ - lDataSent++; - if( lDataSent > tcpMAX_ATTEMPTS_TO_CHECK_BUFFER ) - { - /* Assume we cannot complete sending the data and - therefore cannot safely close the socket. Start over. */ - vTCPHardReset(); - lTransactionCompleted = pdFALSE; - } - } - } - else if( ucState != tcpSTATUS_LISTEN ) - { - /* If we have not yet received a Tx end interrupt we would only - ever expect to find the socket still listening for any - sustained period. */ - if( ucState == ucLastState ) - { - lSameStateCount++; - if( lSameStateCount > tcpMAX_NON_LISTEN_STAUS_READS ) - { - /* We are persistently in an unexpected state. Assume - we cannot safely close the socket and start over. */ - vTCPHardReset(); - lTransactionCompleted = pdFALSE; - } - } - } - else - { - /* We are in the listen state so are happy that everything - is as expected. */ - lSameStateCount = 0; - } - - /* Remember what state we are in this time around so we can check - for a persistence on an unexpected state. */ - ucLastState = ucState; - } - } - - /* We are going to reinitialise the WIZnet device so do not want our - interrupts from the WIZnet to be processed. */ - VICIntEnClear |= tcpEINT0_VIC_CHANNEL_BIT; - return lTransactionCompleted; -} -/*-----------------------------------------------------------*/ - -static void prvWriteString( const portCHAR * const pucTxBuffer, portLONG lTxLen, unsigned portLONG *pulTxAddress ) -{ -unsigned portLONG ulSendAddress; - - /* Send a string to the Tx buffer internal to the WIZnet device. */ - - /* Calculate the address to which we are going to write in the buffer. */ - ulSendAddress = ( *pulTxAddress & tcpSINGLE_SOCKET_ADDR_MASK ) + tcpSINGLE_SOCKET_ADDR_OFFSET; - - /* Send the buffer to the calculated address. Use the semaphore so we - can wait until the entire message has been transferred. */ - i2cMessage( ( unsigned portCHAR * ) pucTxBuffer, lTxLen, tcpDEVICE_ADDRESS, ( unsigned portSHORT ) ulSendAddress, i2cWRITE, xMessageComplete, portMAX_DELAY ); - - /* Wait until the semaphore indicates that the message has been transferred. */ - if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) ) - { - return; - } - - /* Return the new address of the end of the buffer (within the WIZnet - device). */ - *pulTxAddress += ( unsigned portLONG ) lTxLen; -} -/*-----------------------------------------------------------*/ - -static void prvFlushBuffer( unsigned portLONG ulTxAddress ) -{ -unsigned portCHAR ucTxBuffer[ tcpMAX_REGISTER_LEN ]; - - /* We have written some data to the Tx buffer internal to the WIZnet - device. Now we update the Tx pointer inside the WIZnet then send a - Send command - which causes the data up to the new Tx pointer to be - transmitted. */ - - /* Make sure endieness is correct for transmission. */ - ulTxAddress = htonl( ulTxAddress ); - - /* Place the new Tx pointer in the string to be transmitted. */ - ucTxBuffer[ 0 ] = ( unsigned portCHAR ) ( ulTxAddress & 0xff ); - ulTxAddress >>= 8; - ucTxBuffer[ 1 ] = ( unsigned portCHAR ) ( ulTxAddress & 0xff ); - ulTxAddress >>= 8; - ucTxBuffer[ 2 ] = ( unsigned portCHAR ) ( ulTxAddress & 0xff ); - ulTxAddress >>= 8; - ucTxBuffer[ 3 ] = ( unsigned portCHAR ) ( ulTxAddress & 0xff ); - ulTxAddress >>= 8; - - /* And send it to the WIZnet device. */ - i2cMessage( ucTxBuffer, sizeof( ulTxAddress ), tcpDEVICE_ADDRESS, tcpTX_WRITE_POINTER_REG, i2cWRITE, xMessageComplete, portMAX_DELAY ); - - if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) ) - { - return; - } - - vTaskDelay( tcpSHORT_DELAY ); - - /* Transmit! */ - i2cMessage( ucDataSend, sizeof( ucDataSend ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, xMessageComplete, portMAX_DELAY ); - - if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) ) - { - return; - } -} -/*-----------------------------------------------------------*/ - -static void prvSendSamplePage( void ) -{ -extern portLONG lErrorInTask; -unsigned portLONG ulTxAddress; -unsigned portCHAR ucShadow; -portLONG lIndex; -static unsigned portLONG ulRefreshCount = 0x00; -static portCHAR cPageBuffer[ tcpBUFFER_LEN ]; - - - /* This function just generates a sample page of HTML which gets - sent each time a client attaches to the socket. The page is created - from two fixed strings (cSamplePageFirstPart and cSamplePageSecondPart) - with a bit of dynamically generated data in the middle. */ - - /* We need to know the address to which the html string should be sent - in the WIZnet Tx buffer. First read the shadow register. */ - prvReadRegister( &ucShadow, tcpTX_WRITE_SHADOW_REG, tcpSHADOW_READ_LEN ); - - /* Now a short delay is required. */ - vTaskDelay( tcpSHORT_DELAY ); - - /* Now we can read the real pointer value. */ - prvReadRegister( ( unsigned portCHAR * ) &ulTxAddress, tcpTX_WRITE_POINTER_REG, sizeof( ulTxAddress ) ); - - /* Make sure endieness is correct. */ - ulTxAddress = htonl( ulTxAddress ); - - /* Send the start of the page. */ - prvWriteString( cSamplePageFirstPart, strlen( cSamplePageFirstPart ), &ulTxAddress ); - - /* Generate a bit of dynamic data and place it in the buffer ready to be - transmitted. */ - strcpy( cPageBuffer, "
Number of ticks since boot = 0x" ); - lIndex = strlen( cPageBuffer ); - ultoa( xTaskGetTickCount(), &( cPageBuffer[ lIndex ] ), 0 ); - strcat( cPageBuffer, "
Number of tasks executing = "); - lIndex = strlen( cPageBuffer ); - ultoa( ( unsigned portLONG ) uxTaskGetNumberOfTasks(), &( cPageBuffer[ lIndex ] ), 0 ); - strcat( cPageBuffer, "
IO port 0 state (used by flash tasks) = 0x" ); - lIndex = strlen( cPageBuffer ); - ultoa( ( unsigned portLONG ) GPIO0_IOPIN, &( cPageBuffer[ lIndex ] ), 0 ); - strcat( cPageBuffer, "
Refresh = 0x" ); - lIndex = strlen( cPageBuffer ); - ultoa( ( unsigned portLONG ) ulRefreshCount, &( cPageBuffer[ lIndex ] ), 0 ); - - if( lErrorInTask ) - { - strcat( cPageBuffer, "

An error has occurred in at least one task." ); - } - else - { - strcat( cPageBuffer, "

All tasks executing without error." ); - } - - ulRefreshCount++; - - /* Send the dynamically generated string. */ - prvWriteString( cPageBuffer, strlen( cPageBuffer ), &ulTxAddress ); - - /* Finish the page. */ - prvWriteString( cSamplePageSecondPart, strlen( cSamplePageSecondPart ), &ulTxAddress ); - - /* Tell the WIZnet to send the data we have just written to its Tx buffer. */ - prvFlushBuffer( ulTxAddress ); -} - diff --git a/Demo/WizNET_DEMO_GCC_ARM7/TCP.h b/Demo/WizNET_DEMO_GCC_ARM7/TCP.h deleted file mode 100644 index ca5551edf..000000000 --- a/Demo/WizNET_DEMO_GCC_ARM7/TCP.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef TCP_H -#define TCP_H - -#define htonl(A) ((((A) & 0xff000000) >> 24) | (((A) & 0x00ff0000) >> 8) | (((A) & 0x0000ff00) << 8) | (((A) & 0x000000ff) << 24)) - -void vTCPHardReset( void ); -portLONG lTCPSoftReset( void ); -portLONG lTCPCreateSocket( void ); -portLONG lTCPListen( void ); -portLONG lProcessConnection( void ); -void vTCPListen( void ); - -#endif diff --git a/Demo/WizNET_DEMO_GCC_ARM7/TCPISR.c b/Demo/WizNET_DEMO_GCC_ARM7/TCPISR.c deleted file mode 100644 index 66d6ebdbb..000000000 --- a/Demo/WizNET_DEMO_GCC_ARM7/TCPISR.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" - -/* Constants required for interrupt management. */ -#define tcpCLEAR_VIC_INTERRUPT ( 0 ) -#define tcpEINT0_VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x4000 ) - -/* EINT0 interrupt handler. This processes interrupts from the WIZnet device. */ -void vEINT0_ISR( void ) __attribute__((naked)); - -/* Variable is required for its address, but does not otherwise get used. */ -static portLONG lDummyVariable; - -/* - * When the WIZnet device asserts an interrupt we send an (empty) message to - * the TCP task. This wakes the task so the interrupt can be processed. The - * source of the interrupt has to be ascertained by the TCP task as this - * requires an I2C transaction which cannot be performed from this ISR. - */ -void vEINT0_ISR( void ) -{ - portENTER_SWITCHING_ISR(); - - extern xQueueHandle xTCPISRQueue; - portBASE_TYPE xTaskWoken = pdFALSE; - - /* Just wake the TCP task so it knows an ISR has occurred. */ - xQueueSendFromISR( xTCPISRQueue, ( void * ) &lDummyVariable, xTaskWoken ); - - /* We cannot carry on processing interrupts until the TCP task has - processed this one - so for now interrupts are disabled. The TCP task will - re-enable it. */ - VICIntEnClear |= tcpEINT0_VIC_CHANNEL_BIT; - - /* Clear the interrupt bit. */ - VICVectAddr = tcpCLEAR_VIC_INTERRUPT; - - /* Switch to the TCP task immediately so the cause of the interrupt can - be ascertained. It is the responsibility of the TCP task to clear the - interrupts. */ - portEXIT_SWITCHING_ISR( ( xTaskWoken ) ); -} - - diff --git a/Demo/WizNET_DEMO_GCC_ARM7/boot.s b/Demo/WizNET_DEMO_GCC_ARM7/boot.s deleted file mode 100644 index 33e5226eb..000000000 --- a/Demo/WizNET_DEMO_GCC_ARM7/boot.s +++ /dev/null @@ -1,157 +0,0 @@ - /* Sample initialization file */ - - .extern main - .extern exit - - .text - .code 32 - - - .align 0 - - .extern __bss_beg__ - .extern __bss_end__ - .extern __stack_end__ - .extern __data_beg__ - .extern __data_end__ - .extern __data+beg_src__ - - .global start - .global endless_loop - - /* Stack Sizes */ - .set UND_STACK_SIZE, 0x00000004 - .set ABT_STACK_SIZE, 0x00000004 - .set FIQ_STACK_SIZE, 0x00000004 - .set IRQ_STACK_SIZE, 0X00000400 - .set SVC_STACK_SIZE, 0x00000400 - - /* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */ - .set MODE_USR, 0x10 /* User Mode */ - .set MODE_FIQ, 0x11 /* FIQ Mode */ - .set MODE_IRQ, 0x12 /* IRQ Mode */ - .set MODE_SVC, 0x13 /* Supervisor Mode */ - .set MODE_ABT, 0x17 /* Abort Mode */ - .set MODE_UND, 0x1B /* Undefined Mode */ - .set MODE_SYS, 0x1F /* System Mode */ - - .equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */ - .equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */ - - -start: -_start: -_mainCRTStartup: - - /* Setup a stack for each mode - note that this only sets up a usable stack - for system/user, SWI and IRQ modes. Also each mode is setup with - interrupts initially disabled. */ - ldr r0, .LC6 - msr CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode - mov sp, r0 - sub r0, r0, #UND_STACK_SIZE - msr CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */ - mov sp, r0 - sub r0, r0, #ABT_STACK_SIZE - msr CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */ - mov sp, r0 - sub r0, r0, #FIQ_STACK_SIZE - msr CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */ - mov sp, r0 - sub r0, r0, #IRQ_STACK_SIZE - msr CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */ - mov sp, r0 - sub r0, r0, #SVC_STACK_SIZE - msr CPSR_c, #MODE_SYS|I_BIT|F_BIT /* System Mode */ - mov sp, r0 - - /* We want to start in supervisor mode. Operation will switch to system - mode when the first task starts. */ - msr CPSR_c, #MODE_SVC|I_BIT|F_BIT - - /* Clear BSS. */ - - mov a2, #0 /* Fill value */ - mov fp, a2 /* Null frame pointer */ - mov r7, a2 /* Null frame pointer for Thumb */ - - ldr r1, .LC1 /* Start of memory block */ - ldr r3, .LC2 /* End of memory block */ - subs r3, r3, r1 /* Length of block */ - beq .end_clear_loop - mov r2, #0 - -.clear_loop: - strb r2, [r1], #1 - subs r3, r3, #1 - bgt .clear_loop - -.end_clear_loop: - - /* Initialise data. */ - - ldr r1, .LC3 /* Start of memory block */ - ldr r2, .LC4 /* End of memory block */ - ldr r3, .LC5 - subs r3, r3, r1 /* Length of block */ - beq .end_set_loop - -.set_loop: - ldrb r4, [r2], #1 - strb r4, [r1], #1 - subs r3, r3, #1 - bgt .set_loop - -.end_set_loop: - - mov r0, #0 /* no arguments */ - mov r1, #0 /* no argv either */ - - bl main - -endless_loop: - b endless_loop - - - .align 0 - - .LC1: - .word __bss_beg__ - .LC2: - .word __bss_end__ - .LC3: - .word __data_beg__ - .LC4: - .word __data_beg_src__ - .LC5: - .word __data_end__ - .LC6: - .word __stack_end__ - - - /* Setup vector table. Note that undf, pabt, dabt, fiq just execute - a null loop. */ - -.section .startup,"ax" - .code 32 - .align 0 - - b _start /* reset - _start */ - ldr pc, _undf /* undefined - _undf */ - ldr pc, _swi /* SWI - _swi */ - ldr pc, _pabt /* program abort - _pabt */ - ldr pc, _dabt /* data abort - _dabt */ - nop /* reserved */ - ldr pc, [pc,#-0xFF0] /* IRQ - read the VIC */ - ldr pc, _fiq /* FIQ - _fiq */ - -_undf: .word __undf /* undefined */ -_swi: .word vPortYieldProcessor /* SWI */ -_pabt: .word __pabt /* program abort */ -_dabt: .word __dabt /* data abort */ -_fiq: .word __fiq /* FIQ */ - -__undf: b . /* undefined */ -__pabt: b . /* program abort */ -__dabt: b . /* data abort */ -__fiq: b . /* FIQ */ diff --git a/Demo/WizNET_DEMO_GCC_ARM7/html_pages.h b/Demo/WizNET_DEMO_GCC_ARM7/html_pages.h deleted file mode 100644 index 1a3aad898..000000000 --- a/Demo/WizNET_DEMO_GCC_ARM7/html_pages.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef HTML_PAGES_H -#define HTML_PAGES_H - -/* Simply defines some strings that get sent as HTML pages. */ - -const portCHAR * const cSamplePageFirstPart = -"HTTP/1.0 200 OK\r\n" -"Content-type: text/html\r\n" -"\r\n" -"\r\n" -"\r\n" -"\r\n" -"FreeRTOS - Live embedded WEB server demo\r\n" -"\r\n" -"\r\n" -"\r\n" -"FreeRTOS Homepage

" -"

Embedded WEB Server
On the FreeRTOS real time kernel

\r\n" -"

\r\n" -"This demo is now using FreeRTOS.org V4.x.x!

" -"This page is being served by the FreeRTOS embedded WEB server running on an ARM7 microcontroller.\r\n

";
-
-const portCHAR * const cSamplePageSecondPart =
-"
" -"If all is well you should see that 18 tasks are executing - 15 standard demo tasks, the embedded WEB server" -" task, the error check task and the idle task.

" -"\r\n" -"\r\n" -"\r\n"; - - - -#endif - diff --git a/Demo/WizNET_DEMO_GCC_ARM7/i2c.c b/Demo/WizNET_DEMO_GCC_ARM7/i2c.c deleted file mode 100644 index 1ad5d4fbc..000000000 --- a/Demo/WizNET_DEMO_GCC_ARM7/i2c.c +++ /dev/null @@ -1,209 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/* Standard includes. */ -#include - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "queue.h" -#include "semphr.h" - -/* Application includes. */ -#include "i2c.h" - -/*-----------------------------------------------------------*/ - -/* Constants to setup the microcontroller IO. */ -#define mainSDA_ENABLE ( ( unsigned portLONG ) 0x0040 ) -#define mainSCL_ENABLE ( ( unsigned portLONG ) 0x0010 ) - -/* Bit definitions within the I2CONCLR register. */ -#define i2cSTA_BIT ( ( unsigned portCHAR ) 0x20 ) -#define i2cSI_BIT ( ( unsigned portCHAR ) 0x08 ) -#define i2cSTO_BIT ( ( unsigned portCHAR ) 0x10 ) - -/* Constants required to setup the VIC. */ -#define i2cI2C_VIC_CHANNEL ( ( unsigned portLONG ) 0x0009 ) -#define i2cI2C_VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x0200 ) -#define i2cI2C_VIC_ENABLE ( ( unsigned portLONG ) 0x0020 ) - -/* Misc constants. */ -#define i2cNO_BLOCK ( ( portTickType ) 0 ) -#define i2cQUEUE_LENGTH ( ( unsigned portCHAR ) 5 ) -#define i2cEXTRA_MESSAGES ( ( unsigned portCHAR ) 2 ) -#define i2cREAD_TX_LEN ( ( unsigned portLONG ) 2 ) -#define i2cACTIVE_MASTER_MODE ( ( unsigned portCHAR ) 0x40 ) -#define i2cTIMERL ( 200 ) -#define i2cTIMERH ( 200 ) - -/* Array of message definitions. See the header file for more information -on the structure members. There are two more places in the queue than as -defined by i2cQUEUE_LENGTH. This is to ensure that there is always a free -message available - one can be in the process of being transmitted and one -can be left free. */ -static xI2CMessage xTxMessages[ i2cQUEUE_LENGTH + i2cEXTRA_MESSAGES ]; - -/* Function in the ARM part of the code used to create the queues. */ -extern void vI2CISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxTxMessages, unsigned portLONG **ppulBusFree ); - -/* Index to the next free message in the xTxMessages array. */ -unsigned portLONG ulNextFreeMessage = ( unsigned portLONG ) 0; - -/* Queue of messages that are waiting transmission. */ -static xQueueHandle xMessagesForTx; - -/* Flag to indicate the state of the I2C ISR state machine. */ -static unsigned portLONG *pulBusFree; - -/*-----------------------------------------------------------*/ -void i2cMessage( const unsigned portCHAR * const pucMessage, portLONG lMessageLength, unsigned portCHAR ucSlaveAddress, unsigned portSHORT usBufferAddress, unsigned portLONG ulDirection, xSemaphoreHandle xMessageCompleteSemaphore, portTickType xBlockTime ) -{ -extern volatile xI2CMessage *pxCurrentMessage; -xI2CMessage *pxNextFreeMessage; -signed portBASE_TYPE xReturn; - - portENTER_CRITICAL(); - { - /* This message is guaranteed to be free as there are two more messages - than spaces in the queue allowing for one message to be in process of - being transmitted and one to be left free. */ - pxNextFreeMessage = &( xTxMessages[ ulNextFreeMessage ] ); - - /* Fill the message with the data to be sent. */ - - /* Pointer to the actual data. Only a pointer is stored (i.e. the - actual data is not copied, so the data being pointed to must still - be valid when the message eventually gets sent (it may be queued for - a while. */ - pxNextFreeMessage->pucBuffer = ( unsigned portCHAR * ) pucMessage; - - /* This is the address of the I2C device we are going to transmit this - message to. */ - pxNextFreeMessage->ucSlaveAddress = ucSlaveAddress | ( unsigned portCHAR ) ulDirection; - - /* A semaphore can be used to allow the I2C ISR to indicate that the - message has been sent. This can be NULL if you don't want to wait for - the message transmission to complete. */ - pxNextFreeMessage->xMessageCompleteSemaphore = xMessageCompleteSemaphore; - - /* How many bytes are to be sent? */ - pxNextFreeMessage->lMessageLength = lMessageLength; - - /* The address within the WIZnet device to which the data will be - written. This could be the address of a register, or alternatively - a location within the WIZnet Tx buffer. */ - pxNextFreeMessage->ucBufferAddressLowByte = ( unsigned portCHAR ) ( usBufferAddress & 0xff ); - - /* Second byte of the address. */ - usBufferAddress >>= 8; - pxNextFreeMessage->ucBufferAddressHighByte = ( unsigned portCHAR ) ( usBufferAddress & 0xff ); - - /* Increment to the next message in the array - with a wrap around check. */ - ulNextFreeMessage++; - if( ulNextFreeMessage >= ( i2cQUEUE_LENGTH + i2cEXTRA_MESSAGES ) ) - { - ulNextFreeMessage = ( unsigned portLONG ) 0; - } - - /* Is the I2C interrupt in the middle of transmitting a message? */ - if( *pulBusFree == ( unsigned portLONG ) pdTRUE ) - { - /* No message is currently being sent or queued to be sent. We - can start the ISR sending this message immediately. */ - pxCurrentMessage = pxNextFreeMessage; - - I2C_I2CONCLR = i2cSI_BIT; - I2C_I2CONSET = i2cSTA_BIT; - - *pulBusFree = ( unsigned portLONG ) pdFALSE; - } - else - { - /* The I2C interrupt routine is mid sending a message. Queue - this message ready to be sent. */ - xReturn = xQueueSend( xMessagesForTx, &pxNextFreeMessage, xBlockTime ); - - /* We may have blocked while trying to queue the message. If this - was the case then the interrupt would have been enabled and we may - now find that the I2C interrupt routine is no longer sending a - message. */ - if( ( *pulBusFree == ( unsigned portLONG ) pdTRUE ) && ( xReturn == pdPASS ) ) - { - /* Get the next message in the queue (this should be the - message we just posted) and start off the transmission - again. */ - xQueueReceive( xMessagesForTx, &pxNextFreeMessage, i2cNO_BLOCK ); - pxCurrentMessage = pxNextFreeMessage; - - I2C_I2CONCLR = i2cSI_BIT; - I2C_I2CONSET = i2cSTA_BIT; - - *pulBusFree = ( unsigned portLONG ) pdFALSE; - } - } - } - portEXIT_CRITICAL(); -} -/*-----------------------------------------------------------*/ - -void i2cInit( void ) -{ -extern void ( vI2C_ISR )( void ); - - /* Create the queue used to send messages to the ISR. */ - vI2CISRCreateQueues( i2cQUEUE_LENGTH, &xMessagesForTx, &pulBusFree ); - - /* Configure the I2C hardware. */ - - I2C_I2CONCLR = 0xff; - - PCB_PINSEL0 |= mainSDA_ENABLE; - PCB_PINSEL0 |= mainSCL_ENABLE; - - I2C_I2SCLL = i2cTIMERL; - I2C_I2SCLH = i2cTIMERH; - I2C_I2CONSET = i2cACTIVE_MASTER_MODE; - - portENTER_CRITICAL(); - { - /* Setup the VIC for the i2c interrupt. */ - VICIntSelect &= ~( i2cI2C_VIC_CHANNEL_BIT ); - VICIntEnable |= i2cI2C_VIC_CHANNEL_BIT; - VICVectAddr2 = ( portLONG ) vI2C_ISR; - - VICVectCntl2 = i2cI2C_VIC_CHANNEL | i2cI2C_VIC_ENABLE; - } - portEXIT_CRITICAL(); -} - diff --git a/Demo/WizNET_DEMO_GCC_ARM7/i2c.h b/Demo/WizNET_DEMO_GCC_ARM7/i2c.h deleted file mode 100644 index 9810b5958..000000000 --- a/Demo/WizNET_DEMO_GCC_ARM7/i2c.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef I2C_H -#define I2C_H - -/* Structure used to capture the I2C message details. The structure is then - * queued for processing by the I2C ISR. - */ -typedef struct AN_I2C_MESSAGE -{ - portLONG lMessageLength; /*< How many bytes of data to send or received - excluding the buffer address. */ - unsigned portCHAR ucSlaveAddress; /*< The slave address of the WIZnet on the I2C bus. */ - unsigned portCHAR ucBufferAddressLowByte; /*< The address within the WIZnet device to which data should be read from / written to. */ - unsigned portCHAR ucBufferAddressHighByte; /*< As above, high byte. */ - xSemaphoreHandle xMessageCompleteSemaphore; /*< Contains a reference to a semaphore if the application tasks wants notifying when the message has been transacted. */ - unsigned portCHAR *pucBuffer; /*< Pointer to the buffer from where data will be read for transmission, or into which received data will be placed. */ -} xI2CMessage; - -/* Constants to use as the ulDirection parameter of i2cMessage(). */ -#define i2cWRITE ( ( unsigned portLONG ) 0 ) -#define i2cREAD ( ( unsigned portLONG ) 1 ) - -/** - * Must be called once before any calls to i2cMessage. - */ -void i2cInit( void ); - -/** - * Send or receive a message over the I2C bus. - * - * @param pucMessage The data to be transmitted or the buffer into which - * received data will be placed. - * - * @param lMessageLength The number of bytes to either transmit or receive. - * - * @param ucSlaveAddress The slave address of the WIZNet device on the I2C bus. - * - * @param usBufferAddress The address within the WIZNet device to which data is - * either written to or read from. The WIZnet has it's - * own Rx and Tx buffers. - * - * @param ulDirection Must be either i2cWRITE or i2cREAD as #defined above. - * - * @param xMessageCompleteSemaphore - * Can be used to pass a semaphore reference if the - * calling task want notification of when the message has - * completed. Otherwise NULL can be passed. - * - * @param xBlockTime The time to wait for a space in the message queue to - * become available should one not be available - * immediately. - */ -void i2cMessage( const unsigned portCHAR * const pucMessage, portLONG lMessageLength, unsigned portCHAR ucSlaveAddress, unsigned portSHORT usBufferAddress, unsigned portLONG ulDirection, xSemaphoreHandle xMessageCompleteSemaphore, portTickType xBlockTime ); - -#endif - diff --git a/Demo/WizNET_DEMO_GCC_ARM7/i2cISR.c b/Demo/WizNET_DEMO_GCC_ARM7/i2cISR.c deleted file mode 100644 index 202333402..000000000 --- a/Demo/WizNET_DEMO_GCC_ARM7/i2cISR.c +++ /dev/null @@ -1,340 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/* Standard includes. */ -#include - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" -#include "semphr.h" - -/* Application includes. */ -#include "i2c.h" - -/*-----------------------------------------------------------*/ - -/* Bit definitions within the I2CONCLR register. */ -#define i2cSTA_BIT ( ( unsigned portCHAR ) 0x20 ) -#define i2cSI_BIT ( ( unsigned portCHAR ) 0x08 ) -#define i2cSTO_BIT ( ( unsigned portCHAR ) 0x10 ) -#define i2cAA_BIT ( ( unsigned portCHAR ) 0x04 ) - -/* Status codes for the I2STAT register. */ -#define i2cSTATUS_START_TXED ( 0x08 ) -#define i2cSTATUS_REP_START_TXED ( 0x10 ) -#define i2cSTATUS_TX_ADDR_ACKED ( 0x18 ) -#define i2cSTATUS_DATA_TXED ( 0x28 ) -#define i2cSTATUS_RX_ADDR_ACKED ( 0x40 ) -#define i2cSTATUS_DATA_RXED ( 0x50 ) -#define i2cSTATUS_LAST_BYTE_RXED ( 0x58 ) - -/* Constants for operation of the VIC. */ -#define i2cCLEAR_VIC_INTERRUPT ( 0 ) - -/* Misc constants. */ -#define i2cJUST_ONE_BYTE_TO_RX ( 1 ) -#define i2cBUFFER_ADDRESS_BYTES ( 2 ) - -/* End the current transmission and free the bus. */ -#define i2cEND_TRANSMISSION( lStatus ) \ -{ \ - I2C_I2CONCLR = i2cAA_BIT; \ - I2C_I2CONSET = i2cSTO_BIT; \ - eCurrentState = eSentStart; \ - lTransactionCompleted = lStatus; \ -} -/*-----------------------------------------------------------*/ - -/* Valid i2c communication states. */ -typedef enum -{ - eSentStart, /*<< Last action was the transmission of a start bit. */ - eSentAddressForWrite, /*<< Last action was the transmission of the slave address we are to write to. */ - eSentAddressForRead, /*<< Last action was the transmission of the slave address we are to read from. */ - eSentData, /*<< Last action was the transmission of a data byte. */ - eReceiveData /*<< We expected data to be received. */ -} I2C_STATE; -/*-----------------------------------------------------------*/ - -/* Points to the message currently being sent. */ -volatile xI2CMessage *pxCurrentMessage = NULL; - -/* The queue of messages waiting to be transmitted. */ -static xQueueHandle xMessagesForTx; - -/* Flag used to indicate whether or not the ISR is amid sending a message. */ -unsigned portLONG ulBusFree = ( unsigned portLONG ) pdTRUE; - -/* Setting this to true will cause the TCP task to think a message is -complete and thus restart. It can therefore be used under error states -to force a restart. */ -volatile portLONG lTransactionCompleted = pdTRUE; - -/*-----------------------------------------------------------*/ - -void vI2CISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxTxMessages, unsigned portLONG **ppulBusFree ) -{ - /* Create the queues used to hold Rx and Tx characters. */ - xMessagesForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( xI2CMessage * ) ); - - /* Pass back a reference to the queue and bus free flag so the I2C API file - can post messages. */ - *pxTxMessages = xMessagesForTx; - *ppulBusFree = &ulBusFree; -} -/*-----------------------------------------------------------*/ - -void vI2C_ISR( void ) __attribute__ (( naked )); -void vI2C_ISR( void ) -{ - portENTER_SWITCHING_ISR(); - - /* Holds the current transmission state. */ - static I2C_STATE eCurrentState = eSentStart; - static portLONG lMessageIndex = -i2cBUFFER_ADDRESS_BYTES; /* There are two address bytes to send prior to the data. */ - portBASE_TYPE xTaskWokenByTx = pdFALSE; - portLONG lBytesLeft; - - /* The action taken for this interrupt depends on our current state. */ - switch( eCurrentState ) - { - case eSentStart : - - /* We sent a start bit, if it was successful we can - go on to send the slave address. */ - if( ( I2C_I2STAT == i2cSTATUS_START_TXED ) || ( I2C_I2STAT == i2cSTATUS_REP_START_TXED ) ) - { - /* Send the slave address. */ - I2C_I2DAT = pxCurrentMessage->ucSlaveAddress; - - if( pxCurrentMessage->ucSlaveAddress & i2cREAD ) - { - /* We are then going to read bytes back from the - slave. */ - eCurrentState = eSentAddressForRead; - - /* Initialise the buffer index so the first byte goes - into the first buffer position. */ - lMessageIndex = 0; - } - else - { - /* We are then going to write some data to the slave. */ - eCurrentState = eSentAddressForWrite; - - /* When writing bytes we first have to send the two - byte buffer address so lMessageIndex is set negative, - when it reaches 0 it is time to send the actual data. */ - lMessageIndex = -i2cBUFFER_ADDRESS_BYTES; - } - } - else - { - /* Could not send the start bit so give up. */ - i2cEND_TRANSMISSION( pdFAIL ); - } - - I2C_I2CONCLR = i2cSTA_BIT; - - break; - - case eSentAddressForWrite : - - /* We sent the address of the slave we are going to write to. - If this was acknowledged we can go on to send the data. */ - if( I2C_I2STAT == i2cSTATUS_TX_ADDR_ACKED ) - { - /* Start the first byte transmitting which is the - first byte of the buffer address to which the data will - be sent. */ - I2C_I2DAT = pxCurrentMessage->ucBufferAddressHighByte; - eCurrentState = eSentData; - } - else - { - /* Address was not acknowledged so give up. */ - i2cEND_TRANSMISSION( pdFAIL ); - } - break; - - case eSentAddressForRead : - - /* We sent the address of the slave we are going to read from. - If this was acknowledged we can go on to read the data. */ - if( I2C_I2STAT == i2cSTATUS_RX_ADDR_ACKED ) - { - eCurrentState = eReceiveData; - if( pxCurrentMessage->lMessageLength > i2cJUST_ONE_BYTE_TO_RX ) - { - /* Don't ack the last byte of the message. */ - I2C_I2CONSET = i2cAA_BIT; - } - } - else - { - /* Something unexpected happened - give up. */ - i2cEND_TRANSMISSION( pdFAIL ); - } - break; - - case eReceiveData : - - /* We have just received a byte from the slave. */ - if( ( I2C_I2STAT == i2cSTATUS_DATA_RXED ) || ( I2C_I2STAT == i2cSTATUS_LAST_BYTE_RXED ) ) - { - /* Buffer the byte just received then increment the index - so it points to the next free space. */ - pxCurrentMessage->pucBuffer[ lMessageIndex ] = I2C_I2DAT; - lMessageIndex++; - - /* How many more bytes are we expecting to receive? */ - lBytesLeft = pxCurrentMessage->lMessageLength - lMessageIndex; - if( lBytesLeft == ( unsigned portLONG ) 0 ) - { - /* This was the last byte in the message. */ - i2cEND_TRANSMISSION( pdPASS ); - - /* If xMessageCompleteSemaphore is not null then there - is a task waiting for this message to complete and we - must 'give' the semaphore so the task is woken.*/ - if( pxCurrentMessage->xMessageCompleteSemaphore ) - { - xTaskWokenByTx = xSemaphoreGiveFromISR( pxCurrentMessage->xMessageCompleteSemaphore, xTaskWokenByTx ); - } - - /* Are there any other messages to transact? */ - if( xQueueReceiveFromISR( xMessagesForTx, &pxCurrentMessage, &xTaskWokenByTx ) == pdTRUE ) - { - /* Start the next message - which was - retrieved from the queue. */ - I2C_I2CONSET = i2cSTA_BIT; - } - else - { - /* No more messages were found to be waiting for - transaction so the bus is free. */ - ulBusFree = ( unsigned portLONG ) pdTRUE; - } - } - else - { - /* There are more bytes to receive but don't ack the - last byte. */ - if( lBytesLeft <= i2cJUST_ONE_BYTE_TO_RX ) - { - I2C_I2CONCLR = i2cAA_BIT; - } - } - } - else - { - /* Something unexpected happened - give up. */ - i2cEND_TRANSMISSION( pdFAIL ); - } - - break; - - case eSentData : - - /* We sent a data byte, if successful send the next byte in - the message. */ - if( I2C_I2STAT == i2cSTATUS_DATA_TXED ) - { - /* Index to the next byte to send. */ - lMessageIndex++; - if( lMessageIndex < 0 ) - { - /* lMessage index is still negative so we have so far - only sent the first byte of the buffer address. Send - the second byte now, then initialise the buffer index - to zero so the next byte sent comes from the actual - data buffer. */ - I2C_I2DAT = pxCurrentMessage->ucBufferAddressLowByte; - } - else if( lMessageIndex < pxCurrentMessage->lMessageLength ) - { - /* Simply send the next byte in the tx buffer. */ - I2C_I2DAT = pxCurrentMessage->pucBuffer[ lMessageIndex ]; - } - else - { - /* No more bytes in this message to be send. Finished - sending message - send a stop bit. */ - i2cEND_TRANSMISSION( pdPASS ); - - /* If xMessageCompleteSemaphore is not null then there - is a task waiting for this message to be sent and the - semaphore must be 'given' to wake the task. */ - if( pxCurrentMessage->xMessageCompleteSemaphore ) - { - xTaskWokenByTx = xSemaphoreGiveFromISR( pxCurrentMessage->xMessageCompleteSemaphore, xTaskWokenByTx ); - } - - /* Are there any other messages to transact? */ - if( xQueueReceiveFromISR( xMessagesForTx, &pxCurrentMessage, &xTaskWokenByTx ) == pdTRUE ) - { - /* Start the next message from the Tx queue. */ - I2C_I2CONSET = i2cSTA_BIT; - } - else - { - /* No more message were queues for transaction so - the bus is free. */ - ulBusFree = ( unsigned portLONG ) pdTRUE; - } - } - } - else - { - /* Something unexpected happened, give up. */ - i2cEND_TRANSMISSION( pdFAIL ); - } - break; - - default : - - /* Should never get here. */ - eCurrentState = eSentStart; - break; - } - - /* Clear the interrupt. */ - I2C_I2CONCLR = i2cSI_BIT; - VICVectAddr = i2cCLEAR_VIC_INTERRUPT; - - portEXIT_SWITCHING_ISR( ( xTaskWokenByTx ) ); -} -/*-----------------------------------------------------------*/ - diff --git a/Demo/WizNET_DEMO_GCC_ARM7/lpc2106-rom.ld b/Demo/WizNET_DEMO_GCC_ARM7/lpc2106-rom.ld deleted file mode 100644 index e7cf25a22..000000000 --- a/Demo/WizNET_DEMO_GCC_ARM7/lpc2106-rom.ld +++ /dev/null @@ -1,49 +0,0 @@ -MEMORY -{ - flash : ORIGIN = 0, LENGTH = 120K - ram : ORIGIN = 0x40000000, LENGTH = 64K -} - -__stack_end__ = 0x40000000 + 64K - 4; - -SECTIONS -{ - . = 0; - startup : { *(.startup)} >flash - - prog : - { - *(.text) - *(.rodata) - *(.rodata*) - *(.glue_7) - *(.glue_7t) - } >flash - - __end_of_text__ = .; - - .data : - { - __data_beg__ = .; - __data_beg_src__ = __end_of_text__; - *(.data) - __data_end__ = .; - } >ram AT>flash - - .bss : - { - __bss_beg__ = .; - *(.bss) - } >ram - - /* Align here to ensure that the .bss section occupies space up to - _end. Align after .bss to ensure correct alignment even if the - .bss section disappears because there are no input sections. */ - . = ALIGN(32 / 8); -} - . = ALIGN(32 / 8); - _end = .; - _bss_end__ = . ; __bss_end__ = . ; __end__ = . ; - PROVIDE (end = .); - - diff --git a/Demo/WizNET_DEMO_GCC_ARM7/lpc210x.h b/Demo/WizNET_DEMO_GCC_ARM7/lpc210x.h deleted file mode 100644 index 3f1e3042d..000000000 --- a/Demo/WizNET_DEMO_GCC_ARM7/lpc210x.h +++ /dev/null @@ -1,321 +0,0 @@ -#ifndef lpc210x_h -#define lpc210x_h -/******************************************************************************* -lpc210x.h - Register defs for Philips LPC210X: LPC2104, LPC2105 and LPC2106 - - -THE SOFTWARE IS DELIVERED "AS IS" WITHOUT WARRANTY OR CONDITION OF ANY KIND, -EITHER EXPRESS, IMPLIED OR STATUTORY. THIS INCLUDES WITHOUT LIMITATION ANY -WARRANTY OR CONDITION WITH RESPECT TO MERCHANTABILITY OR FITNESS FOR ANY -PARTICULAR PURPOSE, OR AGAINST THE INFRINGEMENTS OF INTELLECTUAL PROPERTY RIGHTS -OF OTHERS. - -This file may be freely used for commercial and non-commercial applications, -including being redistributed with any tools. - -If you find a problem with the file, please report it so that it can be fixed. - -Created by Sten Larsson (sten_larsson at yahoo com) - -Edited by Richard Barry. -*******************************************************************************/ - -#define REG8 (volatile unsigned char*) -#define REG16 (volatile unsigned short*) -#define REG32 (volatile unsigned int*) - - -/*############################################################################## -## MISC -##############################################################################*/ - - /* Constants for data to put in IRQ/FIQ Exception Vectors */ -#define VECTDATA_IRQ 0xE51FFFF0 /* LDR PC,[PC,#-0xFF0] */ -#define VECTDATA_FIQ /* __TODO */ - - -/*############################################################################## -## VECTORED INTERRUPT CONTROLLER -##############################################################################*/ - -#define VICIRQStatus (*(REG32 (0xFFFFF000))) -#define VICFIQStatus (*(REG32 (0xFFFFF004))) -#define VICRawIntr (*(REG32 (0xFFFFF008))) -#define VICIntSelect (*(REG32 (0xFFFFF00C))) -#define VICIntEnable (*(REG32 (0xFFFFF010))) -#define VICIntEnClear (*(REG32 (0xFFFFF014))) -#define VICSoftInt (*(REG32 (0xFFFFF018))) -#define VICSoftIntClear (*(REG32 (0xFFFFF01C))) -#define VICProtection (*(REG32 (0xFFFFF020))) -#define VICVectAddr (*(REG32 (0xFFFFF030))) -#define VICDefVectAddr (*(REG32 (0xFFFFF034))) - -#define VICVectAddr0 (*(REG32 (0xFFFFF100))) -#define VICVectAddr1 (*(REG32 (0xFFFFF104))) -#define VICVectAddr2 (*(REG32 (0xFFFFF108))) -#define VICVectAddr3 (*(REG32 (0xFFFFF10C))) -#define VICVectAddr4 (*(REG32 (0xFFFFF110))) -#define VICVectAddr5 (*(REG32 (0xFFFFF114))) -#define VICVectAddr6 (*(REG32 (0xFFFFF118))) -#define VICVectAddr7 (*(REG32 (0xFFFFF11C))) -#define VICVectAddr8 (*(REG32 (0xFFFFF120))) -#define VICVectAddr9 (*(REG32 (0xFFFFF124))) -#define VICVectAddr10 (*(REG32 (0xFFFFF128))) -#define VICVectAddr11 (*(REG32 (0xFFFFF12C))) -#define VICVectAddr12 (*(REG32 (0xFFFFF130))) -#define VICVectAddr13 (*(REG32 (0xFFFFF134))) -#define VICVectAddr14 (*(REG32 (0xFFFFF138))) -#define VICVectAddr15 (*(REG32 (0xFFFFF13C))) - -#define VICVectCntl0 (*(REG32 (0xFFFFF200))) -#define VICVectCntl1 (*(REG32 (0xFFFFF204))) -#define VICVectCntl2 (*(REG32 (0xFFFFF208))) -#define VICVectCntl3 (*(REG32 (0xFFFFF20C))) -#define VICVectCntl4 (*(REG32 (0xFFFFF210))) -#define VICVectCntl5 (*(REG32 (0xFFFFF214))) -#define VICVectCntl6 (*(REG32 (0xFFFFF218))) -#define VICVectCntl7 (*(REG32 (0xFFFFF21C))) -#define VICVectCntl8 (*(REG32 (0xFFFFF220))) -#define VICVectCntl9 (*(REG32 (0xFFFFF224))) -#define VICVectCntl10 (*(REG32 (0xFFFFF228))) -#define VICVectCntl11 (*(REG32 (0xFFFFF22C))) -#define VICVectCntl12 (*(REG32 (0xFFFFF230))) -#define VICVectCntl13 (*(REG32 (0xFFFFF234))) -#define VICVectCntl14 (*(REG32 (0xFFFFF238))) -#define VICVectCntl15 (*(REG32 (0xFFFFF23C))) - -#define VICITCR (*(REG32 (0xFFFFF300))) -#define VICITIP1 (*(REG32 (0xFFFFF304))) -#define VICITIP2 (*(REG32 (0xFFFFF308))) -#define VICITOP1 (*(REG32 (0xFFFFF30C))) -#define VICITOP2 (*(REG32 (0xFFFFF310))) -#define VICPeriphID0 (*(REG32 (0xFFFFFFE0))) -#define VICPeriphID1 (*(REG32 (0xFFFFFFE4))) -#define VICPeriphID2 (*(REG32 (0xFFFFFFE8))) -#define VICPeriphID3 (*(REG32 (0xFFFFFFEC))) - -#define VICIntEnClr VICIntEnClear -#define VICSoftIntClr VICSoftIntClear - - -/*############################################################################## -## PCB - Pin Connect Block -##############################################################################*/ - -#define PCB_PINSEL0 (*(REG32 (0xE002C000))) -#define PCB_PINSEL1 (*(REG32 (0xE002C004))) - - -/*############################################################################## -## GPIO - General Purpose I/O -##############################################################################*/ - -#define GPIO_IOPIN (*(REG32 (0xE0028000))) /* ALTERNATE NAME GPIO = GPIO0 */ -#define GPIO_IOSET (*(REG32 (0xE0028004))) -#define GPIO_IODIR (*(REG32 (0xE0028008))) -#define GPIO_IOCLR (*(REG32 (0xE002800C))) - -#define GPIO0_IOPIN (*(REG32 (0xE0028000))) /* ALTERNATE NAME GPIO = GPIO0 */ -#define GPIO0_IOSET (*(REG32 (0xE0028004))) -#define GPIO0_IODIR (*(REG32 (0xE0028008))) -#define GPIO0_IOCLR (*(REG32 (0xE002800C))) - - -/*############################################################################## -## UART0 / UART1 -##############################################################################*/ - -/* ---- UART 0 --------------------------------------------- */ -#define UART0_RBR (*(REG32 (0xE000C000))) -#define UART0_THR (*(REG32 (0xE000C000))) -#define UART0_IER (*(REG32 (0xE000C004))) -#define UART0_IIR (*(REG32 (0xE000C008))) -#define UART0_FCR (*(REG32 (0xE000C008))) -#define UART0_LCR (*(REG32 (0xE000C00C))) -#define UART0_LSR (*(REG32 (0xE000C014))) -#define UART0_SCR (*(REG32 (0xE000C01C))) -#define UART0_DLL (*(REG32 (0xE000C000))) -#define UART0_DLM (*(REG32 (0xE000C004))) - -/* ---- UART 1 --------------------------------------------- */ -#define UART1_RBR (*(REG32 (0xE0010000))) -#define UART1_THR (*(REG32 (0xE0010000))) -#define UART1_IER (*(REG32 (0xE0010004))) -#define UART1_IIR (*(REG32 (0xE0010008))) -#define UART1_FCR (*(REG32 (0xE0010008))) -#define UART1_LCR (*(REG32 (0xE001000C))) -#define UART1_LSR (*(REG32 (0xE0010014))) -#define UART1_SCR (*(REG32 (0xE001001C))) -#define UART1_DLL (*(REG32 (0xE0010000))) -#define UART1_DLM (*(REG32 (0xE0010004))) -#define UART1_MCR (*(REG32 (0xE0010010))) -#define UART1_MSR (*(REG32 (0xE0010018))) - - -/*############################################################################## -## I2C -##############################################################################*/ - -#define I2C_I2CONSET (*(REG32 (0xE001C000))) -#define I2C_I2STAT (*(REG32 (0xE001C004))) -#define I2C_I2DAT (*(REG32 (0xE001C008))) -#define I2C_I2ADR (*(REG32 (0xE001C00C))) -#define I2C_I2SCLH (*(REG32 (0xE001C010))) -#define I2C_I2SCLL (*(REG32 (0xE001C014))) -#define I2C_I2CONCLR (*(REG32 (0xE001C018))) - - -/*############################################################################## -## SPI - Serial Peripheral Interface -##############################################################################*/ - -#define SPI_SPCR (*(REG32 (0xE0020000))) -#define SPI_SPSR (*(REG32 (0xE0020004))) -#define SPI_SPDR (*(REG32 (0xE0020008))) -#define SPI_SPCCR (*(REG32 (0xE002000C))) -#define SPI_SPTCR (*(REG32 (0xE0020010))) -#define SPI_SPTSR (*(REG32 (0xE0020014))) -#define SPI_SPTOR (*(REG32 (0xE0020018))) -#define SPI_SPINT (*(REG32 (0xE002001C))) - - -/*############################################################################## -## Timer 0 and Timer 1 -##############################################################################*/ - -/* ---- Timer 0 -------------------------------------------- */ -#define T0_IR (*(REG32 (0xE0004000))) -#define T0_TCR (*(REG32 (0xE0004004))) -#define T0_TC (*(REG32 (0xE0004008))) -#define T0_PR (*(REG32 (0xE000400C))) -#define T0_PC (*(REG32 (0xE0004010))) -#define T0_MCR (*(REG32 (0xE0004014))) -#define T0_MR0 (*(REG32 (0xE0004018))) -#define T0_MR1 (*(REG32 (0xE000401C))) -#define T0_MR2 (*(REG32 (0xE0004020))) -#define T0_MR3 (*(REG32 (0xE0004024))) -#define T0_CCR (*(REG32 (0xE0004028))) -#define T0_CR0 (*(REG32 (0xE000402C))) -#define T0_CR1 (*(REG32 (0xE0004030))) -#define T0_CR2 (*(REG32 (0xE0004034))) -#define T0_CR3 (*(REG32 (0xE0004038))) -#define T0_EMR (*(REG32 (0xE000403C))) - -/* ---- Timer 1 -------------------------------------------- */ -#define T1_IR (*(REG32 (0xE0008000))) -#define T1_TCR (*(REG32 (0xE0008004))) -#define T1_TC (*(REG32 (0xE0008008))) -#define T1_PR (*(REG32 (0xE000800C))) -#define T1_PC (*(REG32 (0xE0008010))) -#define T1_MCR (*(REG32 (0xE0008014))) -#define T1_MR0 (*(REG32 (0xE0008018))) -#define T1_MR1 (*(REG32 (0xE000801C))) -#define T1_MR2 (*(REG32 (0xE0008020))) -#define T1_MR3 (*(REG32 (0xE0008024))) -#define T1_CCR (*(REG32 (0xE0008028))) -#define T1_CR0 (*(REG32 (0xE000802C))) -#define T1_CR1 (*(REG32 (0xE0008030))) -#define T1_CR2 (*(REG32 (0xE0008034))) -#define T1_CR3 (*(REG32 (0xE0008038))) -#define T1_EMR (*(REG32 (0xE000803C))) - - -/*############################################################################## -## PWM -##############################################################################*/ - -#define PWM_IR (*(REG32 (0xE0014000))) -#define PWM_TCR (*(REG32 (0xE0014004))) -#define PWM_TC (*(REG32 (0xE0014008))) -#define PWM_PR (*(REG32 (0xE001400C))) -#define PWM_PC (*(REG32 (0xE0014010))) -#define PWM_MCR (*(REG32 (0xE0014014))) -#define PWM_MR0 (*(REG32 (0xE0014018))) -#define PWM_MR1 (*(REG32 (0xE001401C))) -#define PWM_MR2 (*(REG32 (0xE0014020))) -#define PWM_MR3 (*(REG32 (0xE0014024))) -#define PWM_MR4 (*(REG32 (0xE0014040))) -#define PWM_MR5 (*(REG32 (0xE0014044))) -#define PWM_MR6 (*(REG32 (0xE0014048))) -#define PWM_EMR (*(REG32 (0xE001403C))) -#define PWM_PCR (*(REG32 (0xE001404C))) -#define PWM_LER (*(REG32 (0xE0014050))) -#define PWM_CCR (*(REG32 (0xE0014028))) -#define PWM_CR0 (*(REG32 (0xE001402C))) -#define PWM_CR1 (*(REG32 (0xE0014030))) -#define PWM_CR2 (*(REG32 (0xE0014034))) -#define PWM_CR3 (*(REG32 (0xE0014038))) - -/*############################################################################## -## RTC -##############################################################################*/ - -/* ---- RTC: Miscellaneous Register Group ------------------ */ -#define RTC_ILR (*(REG32 (0xE0024000))) -#define RTC_CTC (*(REG32 (0xE0024004))) -#define RTC_CCR (*(REG32 (0xE0024008))) -#define RTC_CIIR (*(REG32 (0xE002400C))) -#define RTC_AMR (*(REG32 (0xE0024010))) -#define RTC_CTIME0 (*(REG32 (0xE0024014))) -#define RTC_CTIME1 (*(REG32 (0xE0024018))) -#define RTC_CTIME2 (*(REG32 (0xE002401C))) - -/* ---- RTC: Timer Control Group --------------------------- */ -#define RTC_SEC (*(REG32 (0xE0024020))) -#define RTC_MIN (*(REG32 (0xE0024024))) -#define RTC_HOUR (*(REG32 (0xE0024028))) -#define RTC_DOM (*(REG32 (0xE002402C))) -#define RTC_DOW (*(REG32 (0xE0024030))) -#define RTC_DOY (*(REG32 (0xE0024034))) -#define RTC_MONTH (*(REG32 (0xE0024038))) -#define RTC_YEAR (*(REG32 (0xE002403C))) - -/* ---- RTC: Alarm Control Group --------------------------- */ -#define RTC_ALSEC (*(REG32 (0xE0024060))) -#define RTC_ALMIN (*(REG32 (0xE0024064))) -#define RTC_ALHOUR (*(REG32 (0xE0024068))) -#define RTC_ALDOM (*(REG32 (0xE002406C))) -#define RTC_ALDOW (*(REG32 (0xE0024070))) -#define RTC_ALDOY (*(REG32 (0xE0024074))) -#define RTC_ALMON (*(REG32 (0xE0024078))) -#define RTC_ALYEAR (*(REG32 (0xE002407C))) - -/* ---- RTC: Reference Clock Divider Group ----------------- */ -#define RTC_PREINT (*(REG32 (0xE0024080))) -#define RTC_PREFRAC (*(REG32 (0xE0024084))) - - -/*############################################################################## -## WD - Watchdog -##############################################################################*/ - -#define WD_WDMOD (*(REG32 (0xE0000000))) -#define WD_WDTC (*(REG32 (0xE0000004))) -#define WD_WDFEED (*(REG32 (0xE0000008))) -#define WD_WDTV (*(REG32 (0xE000000C))) - - -/*############################################################################## -## System Control Block -##############################################################################*/ - -#define SCB_EXTINT (*(REG32 (0xE01FC140))) -#define SCB_EXTWAKE (*(REG32 (0xE01FC144))) -#define SCB_MEMMAP (*(REG32 (0xE01FC040))) -#define SCB_PLLCON (*(REG32 (0xE01FC080))) -#define SCB_PLLCFG (*(REG32 (0xE01FC084))) -#define SCB_PLLSTAT (*(REG32 (0xE01FC088))) -#define SCB_PLLFEED (*(REG32 (0xE01FC08C))) -#define SCB_PCON (*(REG32 (0xE01FC0C0))) -#define SCB_PCONP (*(REG32 (0xE01FC0C4))) -#define SCB_VPBDIV (*(REG32 (0xE01FC100))) - -/*############################################################################## -## Memory Accelerator Module (MAM) -##############################################################################*/ - -#define MAM_TIM (*(REG32 (0xE01FC004))) -#define MAM_CR (*(REG32 (0xE01FC000))) - -#endif /* lpc210x_h */ - diff --git a/Demo/WizNET_DEMO_GCC_ARM7/main.c b/Demo/WizNET_DEMO_GCC_ARM7/main.c deleted file mode 100644 index 8054ba8f0..000000000 --- a/Demo/WizNET_DEMO_GCC_ARM7/main.c +++ /dev/null @@ -1,298 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. - The processor MUST be in supervisor mode when vTaskStartScheduler is - called. The demo applications included in the FreeRTOS.org download switch - to supervisor mode prior to main being called. If you are not using one of - these demo application projects then ensure Supervisor mode is used. -*/ - - -/* - * Program entry point. - * - * main() is responsible for setting up the microcontroller peripherals, then - * starting the demo application tasks. Once the tasks have been created the - * scheduler is started and main() should never complete. - * - * The demo creates the three standard 'flash' tasks to provide some visual - * feedback that the system and scheduler are still operating correctly. - * - * The HTTP server task operates at the highest priority so will always preempt - * the flash or idle task on TCP/IP events. - */ - -/* Standard includes. */ -#include - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "semphr.h" -#include "task.h" - -/* Application includes. */ -#include "i2c.h" -#include "HTTP_Serv.h" -#include "flash.h" -#include "partest.h" -#include "dynamic.h" -#include "semtest.h" -#include "PollQ.h" -#include "BlockQ.h" -#include "integer.h" - -/*-----------------------------------------------------------*/ - -/* Constants to setup the PLL. */ -#define mainPLL_MUL_4 ( ( unsigned portCHAR ) 0x0003 ) -#define mainPLL_DIV_1 ( ( unsigned portCHAR ) 0x0000 ) -#define mainPLL_ENABLE ( ( unsigned portCHAR ) 0x0001 ) -#define mainPLL_CONNECT ( ( unsigned portCHAR ) 0x0003 ) -#define mainPLL_FEED_BYTE1 ( ( unsigned portCHAR ) 0xaa ) -#define mainPLL_FEED_BYTE2 ( ( unsigned portCHAR ) 0x55 ) -#define mainPLL_LOCK ( ( unsigned portLONG ) 0x0400 ) - -/* Constants to setup the MAM. */ -#define mainMAM_TIM_3 ( ( unsigned portCHAR ) 0x03 ) -#define mainMAM_MODE_FULL ( ( unsigned portCHAR ) 0x02 ) - -/* Constants to setup the peripheral bus. */ -#define mainBUS_CLK_FULL ( ( unsigned portCHAR ) 0x01 ) - -/* Constants to setup I/O and processor. */ -#define mainBUS_CLK_FULL ( ( unsigned portCHAR ) 0x01 ) -#define mainLED_TO_OUTPUT ( ( unsigned portLONG ) 0xff0000 ) -#define mainJTAG_PORT ( ( unsigned portLONG ) 0x3E0000UL ) - -/* Priorities for the demo application tasks. */ -#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainHTTP_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainERROR_CHECK_PRIORITY ( tskIDLE_PRIORITY + 1 ) - -/* Flash rates of the on board LED to indicate the health of the system. */ -#define mainNO_ERROR_DELAY ( 3000 ) -#define mainERROR_DELAY ( 500 ) -#define mainON_BOARD_LED_BIT ( ( unsigned portLONG ) 0x80 ) - -/*-----------------------------------------------------------*/ - -/* - * The Olimex demo board has a single built in LED. This function simply - * toggles its state. - */ -void prvToggleOnBoardLED( void ); - -/* - * Configure the processor for use with the Olimex demo board. - */ -static void prvSetupHardware( void ); - -/* - * Simply check for errors and toggle the onboard LED. - */ -static void prvErrorChecks( void *pvParameters ); - -/* - * Return true if the demo tasks are executing without error - otherwise - * return false. - */ -static void prvMainCheckOtherTasksAreStillRunning( void ); -/*-----------------------------------------------------------*/ - -/* Flag set by prvMainCheckOtherTasksAreStillExecuting(). */ -portLONG lErrorInTask = pdFALSE; - -/* - * Application entry point: - * Starts all the other tasks, then starts the scheduler. - */ -int main( void ) -{ - /* Setup the hardware for use with the Olimex demo board. */ - prvSetupHardware(); - - /* Start the standard flash tasks so the WEB server is not the only thing - running. */ - vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); - vStartSemaphoreTasks( tskIDLE_PRIORITY ); - vStartDynamicPriorityTasks(); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - - /* Start the WEB server task and the error check task. */ - xTaskCreate( vHTTPServerTask, ( signed portCHAR * ) "HTTP", configMINIMAL_STACK_SIZE, NULL, mainHTTP_TASK_PRIORITY, NULL ); - xTaskCreate( prvErrorChecks, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainERROR_CHECK_PRIORITY, NULL ); - - /* Now all the tasks have been started - start the scheduler. - - NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. - The processor MUST be in supervisor mode when vTaskStartScheduler is - called. The demo applications included in the FreeRTOS.org download switch - to supervisor mode prior to main being called. If you are not using one of - these demo application projects then ensure Supervisor mode is used. */ - vTaskStartScheduler(); - - /* Should never reach here! */ - return 0; -} -/*-----------------------------------------------------------*/ - -static void prvSetupHardware( void ) -{ - #ifdef RUN_FROM_RAM - /* Remap the interrupt vectors to RAM if we are are running from RAM. */ - SCB_MEMMAP = 2; - #endif - - /* Set all GPIO to output other than the P0.14 (BSL), and the JTAG pins. - The JTAG pins are left as input as I'm not sure what will happen if the - Wiggler is connected after powerup - not that it would be a good idea to - do that anyway. */ - GPIO_IODIR = ~( mainJTAG_PORT ); - - /* Setup the PLL to multiply the XTAL input by 4. */ - SCB_PLLCFG = ( mainPLL_MUL_4 | mainPLL_DIV_1 ); - - /* Activate the PLL by turning it on then feeding the correct sequence of - bytes. */ - SCB_PLLCON = mainPLL_ENABLE; - SCB_PLLFEED = mainPLL_FEED_BYTE1; - SCB_PLLFEED = mainPLL_FEED_BYTE2; - - /* Wait for the PLL to lock... */ - while( !( SCB_PLLSTAT & mainPLL_LOCK ) ); - - /* ...before connecting it using the feed sequence again. */ - SCB_PLLCON = mainPLL_CONNECT; - SCB_PLLFEED = mainPLL_FEED_BYTE1; - SCB_PLLFEED = mainPLL_FEED_BYTE2; - - /* Setup and turn on the MAM. Three cycle access is used due to the fast - PLL used. It is possible faster overall performance could be obtained by - tuning the MAM and PLL settings. */ - MAM_TIM = mainMAM_TIM_3; - MAM_CR = mainMAM_MODE_FULL; - - /* Setup the peripheral bus to be the same as the PLL output. */ - SCB_VPBDIV = mainBUS_CLK_FULL; - - /* Initialise the i2c peripheral. */ - i2cInit(); - - /* Initialise the LED's used by the flash tasks. */ - vParTestInitialise(); -} -/*-----------------------------------------------------------*/ - -static void prvMainCheckOtherTasksAreStillRunning( void ) -{ - /* Check all the demo tasks (other than the flash tasks) to ensure - that they are all still running, and that none of them have detected - an error. */ - - /* This function is called from more than one task. */ - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - lErrorInTask = pdTRUE; - } - - if( xArePollingQueuesStillRunning() != pdTRUE ) - { - lErrorInTask = pdTRUE; - } - - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - lErrorInTask = pdTRUE; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - lErrorInTask = pdTRUE; - } - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - lErrorInTask = pdTRUE; - } -} -/*-----------------------------------------------------------*/ - -void prvToggleOnBoardLED( void ) -{ -unsigned portLONG ulState; - - ulState = GPIO0_IOPIN; - if( ulState & mainON_BOARD_LED_BIT ) - { - GPIO_IOCLR = mainON_BOARD_LED_BIT; - } - else - { - GPIO_IOSET = mainON_BOARD_LED_BIT; - } -} -/*-----------------------------------------------------------*/ - -static void prvErrorChecks( void *pvParameters ) -{ -portTickType xDelay = mainNO_ERROR_DELAY; - - /* The parameters are not used. */ - ( void ) pvParameters; - - for( ;; ) - { - /* How long we delay depends on whether an error has been detected - or not. Therefore the flash rate of the on board LED indicates - whether or not an error has occurred. */ - vTaskDelay( xDelay ); - - /* Update the lErrorInTask flag. */ - prvMainCheckOtherTasksAreStillRunning(); - - if( lErrorInTask ) - { - /* An error has been found so reduce the delay period and in so - doing speed up the flash rate of the on board LED. */ - xDelay = mainERROR_DELAY; - } - - prvToggleOnBoardLED(); - } -} - diff --git a/Demo/WizNET_DEMO_TERN_186/186.cfg b/Demo/WizNET_DEMO_TERN_186/186.cfg deleted file mode 100644 index f7e61706c..000000000 --- a/Demo/WizNET_DEMO_TERN_186/186.cfg +++ /dev/null @@ -1,145 +0,0 @@ -// 186.cfg -// You must select RAM, ROM for your controller 04-26-2000 -// Your TERN controller is installed with SRAM and ROM with different sizes. -// For debug, 128K or 512K SRAM can be selected -// For build a ROM, you need to select the ROM size. -// How to select ? -// 1) commend out the unwanted #define RAM size line with "//" -// 2) delete the "//" preceding the wanted #define RAM size line -// - -// #define RAM 32 // 32KB SRAM installed -#define RAM 128 // 128KB SRAM installed -// #define RAM 512 // 512KB SRAM installed - -// #define ROM 32 // Use 32KB ROM chip 27C256-70 -#define ROM 64 // Use 64KB ROM chip 27C512-70 -// #define ROM 128 // Use 128KB ROM chip 27C010-70 -// #define ROM 256 // Use 256KB ROM chip 27C020-70 -// #define ROM 512 // Use 512KB ROM chip 27C040-70, Change Jumper on board - - -cputype Am186ES // AMD188/6 based controllers - -#if defined(__PDREMOTE__) - -#if RAM == 32 -map 0x00000 to 0x00fff as reserved // interrupt vector table -map 0x01000 to 0x03fff as rdwr // System RAM area (60KB RAM) -map 0x04000 to 0x07fff as rdonly // Simulated EPROM area (64KB RAM) -map 0x08000 to 0xfffff as reserved // No access allowed -#define CODE_START 0x0400 // Start of application code, STEP2 ! - -#elif RAM == 128 -map 0x00000 to 0x00fff as reserved // interrupt vector table -map 0x01000 to 0x07fff as rdwr // System RAM area (60KB RAM) -map 0x08000 to 0x1ffff as rdonly // Simulated EPROM area (64KB RAM) -map 0x20000 to 0xfffff as reserved // No access allowed -#define CODE_START 0x0800 // Start of application code - -#elif RAM == 512 -map 0x00000 to 0x00fff as reserved // interrupt vector table -map 0x01000 to 0x07fff as rdwr // System RAM area (60KB RAM) -map 0x08000 to 0x7ffff as rdonly // Simulated EPROM area(480KB RAM) -map 0x80000 to 0xfffff as reserved // No access allowed -#define CODE_START 0x0800 // Start of application code -#endif - -#define DATA_START 0x0100 // Start of application data -#define BOOT_START 0x1fc0 // Start of initialization code - -#else -#if ROM == 32 -map 0x00000 to 0x1ffff as rdwr // 128KB RAM address space -map 0x20000 to 0xf7fff as reserved // No access -map 0xF8000 to 0xfffff as rdonly // 32KB EPROM address space -#define CODE_START 0xF800 // Start of application code -#elif ROM == 64 -map 0x00000 to 0x1ffff as rdwr // 128KB RAM address space -map 0x20000 to 0xEffff as reserved // No access -map 0xF0000 to 0xfffff as rdonly // 64KB EPROM address space -#define CODE_START 0xF000 // Start of application code -#elif ROM == 128 -map 0x00000 to 0x1ffff as rdwr // 128KB RAM address space -map 0x20000 to 0xDffff as reserved // No access -map 0xE0000 to 0xfffff as rdonly // 128KB EPROM address space -#define CODE_START 0xE000 // Start of application code -#elif ROM == 256 -map 0x00000 to 0x1ffff as rdwr // 128KB RAM address space -map 0x20000 to 0xBffff as reserved // No access -map 0xC0000 to 0xfffff as rdonly // 256KB EPROM address space -#define CODE_START 0xC000 // Start of application code -#elif ROM == 512 -map 0x00000 to 0x1ffff as rdwr // 128KB RAM address space -map 0x20000 to 0x7ffff as reserved // No access -map 0x80000 to 0xfffff as rdonly // 512KB EPROM address space -#define CODE_START 0x8000 // Start of application code -#endif - -#define DATA_START 0x0040 // Start of application data -#define BOOT_START 0xffc0 // Start of initialization code - -initcode reset \ // Reset vector to program entry point - umcs = 0x80bf \ // 512K ROM, 3 wait states - lmcs = 0x7fbf \ // 512K RAM, 3 wait states - mpcs = 0xa0bf \ - mmcs = 0x81ff \ - pacs = 0x007f - -class ??LOCATE = BOOT_START // Chip select initialization -output ??LOCATE - -#if ROM == 32 // 27C256-90 EPROM or FLASH -hexfile binary offset=0xf8000 size=32 // for 27C256, bin file -#elif ROM == 64 // 27C512-90 EPROM or FLASH -hexfile binary offset=0xF0000 size=64 // for 27C512 -#elif ROM == 128 // 27C010-90 EPROM or FLASH -hexfile binary offset=0xE0000 size=128 // for 27C010 -#elif ROM == 256 // 27C020-90 EPROM or FLASH -hexfile binary offset=0xC0000 size=256 // for 27C020 -#elif ROM == 512 // 27C040-90 EPROM or FLASH -hexfile Intel86 offset=0x80000 size=512 // for 27C040, output .HEX file -#endif - -#endif - - -// -// Start of common configuration file settings. -// - -absfile axe86 // Paradigm C++ debugging output -listfile segments // Absolute segment map - -dup DATA ROMDATA // Make a copy of initialized data -dup FAR_DATA ROMFARDATA // Make a copy of far initialized data - -#if defined(__COMPFARDATA__) // Compress and display results -compress ROMFARDATA -display compression -#endif - -class CODE = CODE_START // Application code -class DATA = DATA_START // Application data - -order DATA \ // RAM class organization - BSS \ - NVRAM \ - EDATA \ - STACK \ - FAR_DATA ENDFAR_DATA \ - FAR_BSS ENDFAR_BSS \ - FAR_HEAP ENDFAR_HEAP - -order CODE \ // EPROM class organization - INITDATA EXITDATA \ - FAR_CONST ENDFAR_CONST \ - ROMDATA ENDROMDATA \ - ROMFARDATA ENDROMFARDATA - -output CODE \ // Classes in the output file(s) - INITDATA EXITDATA \ - FAR_CONST ENDFAR_CONST \ - ROMDATA ENDROMDATA \ - ROMFARDATA ENDROMFARDATA - \ No newline at end of file diff --git a/Demo/WizNET_DEMO_TERN_186/AE.LIB b/Demo/WizNET_DEMO_TERN_186/AE.LIB deleted file mode 100644 index dcfffa152..000000000 Binary files a/Demo/WizNET_DEMO_TERN_186/AE.LIB and /dev/null differ diff --git a/Demo/WizNET_DEMO_TERN_186/FreeRTOSConfig.h b/Demo/WizNET_DEMO_TERN_186/FreeRTOSConfig.h deleted file mode 100644 index 8931404c3..000000000 --- a/Demo/WizNET_DEMO_TERN_186/FreeRTOSConfig.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 1 -#define configUSE_TICK_HOOK 0 -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 80000000 ) -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 256 ) /* This can be made smaller if required. */ -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 20 * 1024 ) ) -#define configMAX_TASK_NAME_LEN ( 16 ) -#define configUSE_TRACE_FACILITY 1 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 1 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 1 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 - - - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/WizNET_DEMO_TERN_186/HTTPTask.c b/Demo/WizNET_DEMO_TERN_186/HTTPTask.c deleted file mode 100644 index 3af0e3dd9..000000000 --- a/Demo/WizNET_DEMO_TERN_186/HTTPTask.c +++ /dev/null @@ -1,289 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * Very simple task that responds with a single WEB page to http requests. - * - * The WEB page displays task and system status. A semaphore is used to - * wake the task when there is processing to perform as determined by the - * interrupts generated by the Ethernet interface. - */ - -/* Standard includes. */ -#include -#include - -/* Tern includes. */ -#include "utils\system_common.h" -#include "i2chip_hw.h" -#include "socket.h" - -/* FreeRTOS.org includes. */ -#include -#include -#include - -/* The standard http port on which we are going to listen. */ -#define httpPORT 80 - -#define httpTX_WAIT 2 - -/* Network address configuration. */ -const unsigned portCHAR ucMacAddress[] = { 12, 128, 12, 34, 56, 78 }; -const unsigned portCHAR ucGatewayAddress[] = { 192, 168, 2, 1 }; -const unsigned portCHAR ucIPAddress[] = { 172, 25, 218, 210 }; -const unsigned portCHAR ucSubnetMask[] = { 255, 255, 255, 0 }; - -/* The number of sockets this task is going to handle. */ -#define httpSOCKET_NUM 3 -unsigned portCHAR ucConnection[ httpSOCKET_NUM ]; - -/* The maximum data buffer size we can handle. */ -#define httpSOCKET_BUFFER_SIZE 2048 - -/* Standard HTTP response. */ -#define httpOUTPUT_OK "HTTP/1.0 200 OK\r\nContent-Type: text/html\r\n\r\n" - -/* Hard coded HTML components. Other data is generated dynamically. */ -#define HTML_OUTPUT_BEGIN "\ -\ -

FreeRTOS.orgtm + Tern E-Enginetm

\ -FreeRTOS.org Homepage

\ -

Task status table:\r\n\ -

Task          State  Priority  Stack	#
\
-************************************************
"
-
-#define HTML_OUTPUT_END   "\
-"
-
-/*-----------------------------------------------------------*/
-
-/*
- * Initialise the data structures used to hold the socket status.
- */
-static void prvHTTPInit( void );
-
-/*
- * Setup the Ethernet interface with the network addressing information.
- */
-static void prvNetifInit( void );
-
-/*
- * Generate the dynamic components of the served WEB page and transmit the 
- * entire page through the socket.
- */
-static void prvTransmitHTTP( unsigned portCHAR socket );
-/*-----------------------------------------------------------*/
-
-/* This variable is simply incremented by the idle task hook so the number of
-iterations the idle task has performed can be displayed as part of the served
-page. */
-unsigned portLONG ulIdleLoops = 0UL;
-
-/* Data buffer shared by sockets. */
-unsigned portCHAR ucSocketBuffer[ httpSOCKET_BUFFER_SIZE ];
-
-/* The semaphore used by the Ethernet ISR to signal that the task should wake
-and process whatever caused the interrupt. */
-xSemaphoreHandle xTCPSemaphore = NULL;
-
-/*-----------------------------------------------------------*/
-void vHTTPTask( void * pvParameters )
-{
-portSHORT i, sLen;
-unsigned portCHAR ucState;
-
-	( void ) pvParameters;
-
-    /* Create the semaphore used to communicate between this task and the
-    WIZnet ISR. */
-    vSemaphoreCreateBinary( xTCPSemaphore );
-
-	/* Make sure everything is setup before we start. */
-	prvNetifInit();
-	prvHTTPInit();
-
-	for( ;; )
-	{
-		/* Wait until the ISR tells us there is something to do. */
-    	xSemaphoreTake( xTCPSemaphore, portMAX_DELAY );
-
-		/* Check each socket. */
-		for( i = 0; i < httpSOCKET_NUM; i++ )
-		{
-			ucState = select( i, SEL_CONTROL );
-
-			switch (ucState)
-			{
-				case SOCK_ESTABLISHED :  /* new connection established. */
-
-					if( ( sLen = select( i, SEL_RECV ) ) > 0 )
-					{
-						if( sLen > httpSOCKET_BUFFER_SIZE ) 
-						{
-							sLen = httpSOCKET_BUFFER_SIZE;
-						}
-
-						disable();
-						
-						sLen = recv( i, ucSocketBuffer, sLen );    
-
-						if( ucConnection[ i ] == 1 )
-						{	
-							/* This is our first time processing a HTTP
-							 request on this connection. */
-							prvTransmitHTTP( i );
-							ucConnection[i] = 0;
-						}
-						enable();
-					}
-					break;
-
-				case SOCK_CLOSE_WAIT :
-
-					close(i);
-					break;
-
-				case SOCK_CLOSED :
-
-					ucConnection[i] = 1;
-					socket( i, SOCK_STREAM, 80, 0x00 );
-					NBlisten( i ); /* reinitialize socket. */
-					break;
-			}
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-static void prvHTTPInit( void )
-{
-unsigned portCHAR ucIndex;
-
-	/* There are 4 total sockets available; we will claim 3 for HTTP. */
-	for(ucIndex = 0; ucIndex < httpSOCKET_NUM; ucIndex++)
-	{
-		socket( ucIndex, SOCK_STREAM, httpPORT, 0x00 );
-		NBlisten( ucIndex );
-		ucConnection[ ucIndex ] = 1;
-	}
-}
-/*-----------------------------------------------------------*/
-
-static void prvNetifInit( void )
-{
-	i2chip_init();
-	initW3100A();
-
-	setMACAddr( ( unsigned portCHAR * ) ucMacAddress );
-	setgateway( ( unsigned portCHAR * ) ucGatewayAddress );
-	setsubmask( ( unsigned portCHAR * ) ucSubnetMask );
-	setIP( ( unsigned portCHAR * ) ucIPAddress );
-
-	/* See definition of 'sysinit' in socket.c
-	 - 8 KB transmit buffer, and 8 KB receive buffer available.  These buffers
-	   are shared by all 4 channels.
-	 - (0x55, 0x55) configures the send and receive buffers at 
-		httpSOCKET_BUFFER_SIZE bytes for each of the 4 channels. */
-	sysinit( 0x55, 0x55 );
-}
-/*-----------------------------------------------------------*/
-
-static void prvTransmitHTTP(unsigned portCHAR socket)
-{
-extern portSHORT usCheckStatus;
-
-	/* Send the http and html headers. */
-	send( socket, ( unsigned portCHAR * ) httpOUTPUT_OK, strlen( httpOUTPUT_OK ) );
-	send( socket, ( unsigned portCHAR * ) HTML_OUTPUT_BEGIN, strlen( HTML_OUTPUT_BEGIN ) );
-
-	/* Generate then send the table showing the status of each task. */
-	vTaskList( ucSocketBuffer );
- 	send( socket, ( unsigned portCHAR * ) ucSocketBuffer, strlen( ucSocketBuffer ) );
-
-	/* Send the number of times the idle task has looped. */
-    sprintf( ucSocketBuffer, "


The idle task has looped 0x%08lx times
", ulIdleLoops ); - send( socket, ( unsigned portCHAR * ) ucSocketBuffer, strlen( ucSocketBuffer ) ); - - /* Send the tick count. */ - sprintf( ucSocketBuffer, "The tick count is 0x%08lx
", xTaskGetTickCount() ); - send( socket, ( unsigned portCHAR * ) ucSocketBuffer, strlen( ucSocketBuffer ) ); - - /* Show a message indicating whether or not the check task has discovered - an error in any of the standard demo tasks. */ - if( usCheckStatus == 0 ) - { - sprintf( ucSocketBuffer, "No errors detected." ); - send( socket, ( unsigned portCHAR * ) ucSocketBuffer, strlen( ucSocketBuffer ) ); - } - else - { - sprintf( ucSocketBuffer, "An error has been detected in at least one task %x.

", usCheckStatus ); - send( socket, ( unsigned portCHAR * ) ucSocketBuffer, strlen( ucSocketBuffer ) ); - } - - /* Finish the page off. */ - send( socket, (unsigned portCHAR*)HTML_OUTPUT_END, strlen(HTML_OUTPUT_END)); - - /* Must make sure the data is gone before closing the socket. */ - while( !tx_empty( socket ) ) - { - vTaskDelay( httpTX_WAIT ); - } - close(socket); -} -/*-----------------------------------------------------------*/ - -void vApplicationIdleHook( void ) -{ - ulIdleLoops++; -} - - - - - - - - - - - - - - - - - - - - diff --git a/Demo/WizNET_DEMO_TERN_186/HTTPTask.h b/Demo/WizNET_DEMO_TERN_186/HTTPTask.h deleted file mode 100644 index 342d03561..000000000 --- a/Demo/WizNET_DEMO_TERN_186/HTTPTask.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef HTTP_TASK_H -#define HTTP_TASK_H - -void vHTTPTask( void *pvParameters ); - -#endif - diff --git a/Demo/WizNET_DEMO_TERN_186/RTOSDemo.DSW b/Demo/WizNET_DEMO_TERN_186/RTOSDemo.DSW deleted file mode 100644 index 0d41cd60a..000000000 Binary files a/Demo/WizNET_DEMO_TERN_186/RTOSDemo.DSW and /dev/null differ diff --git a/Demo/WizNET_DEMO_TERN_186/RTOSDemo.ide b/Demo/WizNET_DEMO_TERN_186/RTOSDemo.ide deleted file mode 100644 index 144e9695f..000000000 Binary files a/Demo/WizNET_DEMO_TERN_186/RTOSDemo.ide and /dev/null differ diff --git a/Demo/WizNET_DEMO_TERN_186/RTOSDemo.mbt b/Demo/WizNET_DEMO_TERN_186/RTOSDemo.mbt deleted file mode 100644 index 9af2d521a..000000000 Binary files a/Demo/WizNET_DEMO_TERN_186/RTOSDemo.mbt and /dev/null differ diff --git a/Demo/WizNET_DEMO_TERN_186/RTOSDemo.mrt b/Demo/WizNET_DEMO_TERN_186/RTOSDemo.mrt deleted file mode 100644 index 6fe70dd57..000000000 Binary files a/Demo/WizNET_DEMO_TERN_186/RTOSDemo.mrt and /dev/null differ diff --git a/Demo/WizNET_DEMO_TERN_186/RTOSDemo.rom b/Demo/WizNET_DEMO_TERN_186/RTOSDemo.rom deleted file mode 100644 index 74ecd1f94..000000000 Binary files a/Demo/WizNET_DEMO_TERN_186/RTOSDemo.rom and /dev/null differ diff --git a/Demo/WizNET_DEMO_TERN_186/include/SOCKET.H b/Demo/WizNET_DEMO_TERN_186/include/SOCKET.H deleted file mode 100644 index b3f7b6cf2..000000000 --- a/Demo/WizNET_DEMO_TERN_186/include/SOCKET.H +++ /dev/null @@ -1,247 +0,0 @@ -/* -******************************************************************************** -* TERN, Inc. -* (c) Copyright 2005, http://www.tern.com -* -* - Derived based on development version provided by Wiznet. -* -* Filename : socket.h -* Programmer(s): -* Created : 2002/06/20 -* Modified : -* 2002/09/27 : - Renaming -* INT_STATUS --> INT_REG -* STATUS(i) --> INT_STATUS(i) -* C_STATUS(i) --> SOCK_STATUS(i) -* 2003/11/06 : Ported for use with TERN controller. Note all byte access is at even addresses -* 2005/10/8 : Modified constants for easier initialization. -* -* Description : Header file of W3100A for TERN embedded controller -******************************************************************************** -*/ -#ifndef __SOCKET_H__ -#define __SOCKET_H__ - -#include "types.h" -#include "i2chip_hw.h" -#include - -/*******************************************************************/ -#define MAX_SOCK_NUM 4 // Concurrent maxmium number of socket - -#define I2CHIP_C0_CR 0x00 -#define I2CHIP_C1_CR 0x01 -#define I2CHIP_C2_CR 0x02 -#define I2CHIP_C3_CR 0x03 -#define I2CHIP_C0_ISR 0x04 -#define I2CHIP_C1_ISR 0x05 -#define I2CHIP_C2_ISR 0x06 -#define I2CHIP_C3_ISR 0x07 -#define I2CHIP_IR 0x08 -#define I2CHIP_IMR 0x09 - -#define I2CHIP_IDM_OR 0x0C -#define I2CHIP_IDM_AR0 0x0D -#define I2CHIP_IDM_AR1 0x0E -#define I2CHIP_IDM_DR 0x0F -#define I2CHIP_C0_RW_PR 0x10 -#define I2CHIP_C0_RR_PR 0x14 -#define I2CHIP_C0_TA_PR 0x18 -#define I2CHIP_C1_RW_PR 0x1C -#define I2CHIP_C1_RR_PR 0x20 -#define I2CHIP_C1_TA_PR 0x24 -#define I2CHIP_C2_RW_PR 0x28 -#define I2CHIP_C2_RR_PR 0x2C -#define I2CHIP_C2_TA_PR 0x30 -#define I2CHIP_C3_RW_PR 0x34 -#define I2CHIP_C3_RR_PR 0x38 -#define I2CHIP_C3_TA_PR 0x3C -#define I2CHIP_C0_TW_PR 0x40 -#define I2CHIP_C0_TR_PR 0x44 -#define I2CHIP_C1_TW_PR 0x4C -#define I2CHIP_C1_TR_PR 0x50 -#define I2CHIP_C2_TW_PR 0x58 -#define I2CHIP_C2_TR_PR 0x5C -#define I2CHIP_C3_TW_PR 0x64 -#define I2CHIP_C3_TR_PR 0x68 -#define I2CHIP_GAR 0x80 -#define I2CHIP_SMR 0x84 -#define I2CHIP_SHAR 0x88 -#define I2CHIP_SIPR 0x8E -#define I2CHIP_IRTR 0x92 -#define I2CHIP_RCR 0x94 -#define I2CHIP_RMSR 0x95 -#define I2CHIP_TMSR 0x96 -#define I2CHIP_C0_SSR 0xA0 -#define I2CHIP_C0_SOPR 0xA1 -#define I2CHIP_C0_DIR 0xA8 -#define I2CHIP_CO_DPR 0xAC -#define I2CHIP_C0_SPR 0xAE -#define I2CHIP_C0_IPR 0xB0 -#define I2CHIP_C0_TOSR 0xB1 -#define I2CHIP_C0_MSSR 0xB2 - -#define I2CHIP_C1_SSR 0xB8 -#define I2CHIP_C1_SOPR 0xB9 -#define I2CHIP_C1_DIR 0xC0 -#define I2CHIP_C1_DPR 0xC4 -#define I2CHIP_C1_SPR 0xC6 -#define I2CHIP_C1_IPR 0xC8 -#define I2CHIP_C1_TOSR 0xC9 -#define I2CHIP_C1_MSSR 0xCA - -#define I2CHIP_C2_SSR 0xD0 -#define I2CHIP_C2_SOPR 0xD1 -#define I2CHIP_C2_DIR 0xD8 -#define I2CHIP_C2_DPR 0xDC -#define I2CHIP_C2_SPR 0xDE -#define I2CHIP_C2_IPR 0xE0 -#define I2CHIP_C2_TOSR 0xE1 -#define I2CHIP_C2_MSSR 0xE2 - -#define I2CHIP_C3_SSR 0xE8 -#define I2CHIP_C3_SOPR 0xE9 -#define I2CHIP_C3_DIR 0xF0 -#define I2CHIP_C3_DPR 0xF4 -#define I2CHIP_C3_SPR 0xF6 -#define I2CHIP_C3_IPR 0xF8 -#define I2CHIP_C3_TOSR 0xF9 -#define I2CHIP_C3_MSSR 0xFA - -#define MAX_SEGMENT_SIZE 1460 // Maximum TCP transmission packet size -#define MAX_BUF_SIZE1 0 - - -/* SOCKET OPTION(Settting OPT_PROTOCOL REG.) */ -#define SOCKOPT_BROADCAST 0x80 // Transmission, Reception of broadcasting data -#define SOCKOPT_NDTIMEOUT 0x40 // Setting timeout -#define SOCKOPT_NDACK 0x20 // Setting No Delayed Ack(TCP) -#define SOCKOPT_SWS 0x10 // Setting Silly Window Syndrome(TCP) - -/* OPTION(Setting OPT_PROTOCOL REG.) for MAC LAYER RAW MODE */ -#define MACLOPT_RXERR 0x80 // Setting reception of error packet -#define MACLOPT_BROADCAST 0x40 // Setting reception of broadcast packet -#define MACLOPT_PROMISC 0x20 // Setting reception of promiscuous packet - -/* Distinguish TCP / UDP / IP RAW / MAC RAW (Setting OPT_PROTOCOL REG.) */ -#define SOCK_CLOSEDM 0x00 // unused socket -#define SOCK_STREAM 0x01 // TCP -#define SOCK_DGRAM 0x02 // UDP -#define SOCK_IPL_RAW 0x03 // IP LAYER RAW SOCK -#define SOCK_MACL_RAW 0x04 // MAC LAYER RAW SOCK - -/* Setting IP PROTOCOL */ -#define IPPROTO_IP 0 // dummy for IP -#define IPPROTO_ICMP 1 // control message protocol -#define IPPROTO_IGMP 2 // internet group management protocol -#define IPPROTO_GGP 3 // gateway^2 (deprecated) -#define IPPROTO_TCP 6 // tcp -#define IPPROTO_PUP 12 // pup -#define IPPROTO_UDP 17 // user datagram protocol -#define IPPROTO_IDP 22 // xns idp -#define IPPROTO_ND 77 // UNOFFICIAL net disk proto -#define IPPROTO_RAW 255 // raw IP packet - -/* Select parameter to use */ -#define SEL_CONTROL 0 //Confirm socket status -#define SEL_SEND 1 // Confirm Tx free buffer size -#define SEL_RECV 2 // Confirm Rx data size - -/* Command variables */ -#define CSYS_INIT 0x01 // To set up network information(mac address, gateway address, - // subnet mask, source ip) -#define CSOCK_INIT 0x02 // To initialize socket -#define CCONNECT 0x04 // To establish connection as tcp client mode -#define CLISTEN 0x08 // To wait for connection request as tcp server mode -#define CCLOSE 0x10 // To terminate connection -#define CSEND 0x20 // To send data -#define CRECV 0x40 // To receive data -#define CSW_RESET 0x80 // To do software reset - -#define CSET_MEMORY_TEST 0x80 // To set the memory test bit -#define CRESET_MEMORY_TEST 0x00 // To clear the memory test bit - -/* Status Variables */ -#define SSYS_INIT_OK 0x01 // Completion of CSYS_INIT command -#define SSOCK_INIT_OK 0x02 // Completion of CSOCK_INIT command -#define SESTABLISHED 0x04 // Completion of connection setup -#define SCLOSED 0x08 // Completion of CCLOSED command -#define SSEND_OK 0x20 // Completion of sending data -#define SRECV_OK 0x40 // Completion of receiving data - -/* Socket Status Vabiables */ -#define SOCK_CLOSED 0x00 // Status of connection closed -#define SOCK_ARP 0x01 // Status of ARP -#define SOCK_LISTEN 0x02 // Status of waiting for TCP connection setup -#define SOCK_SYNSENT 0x03 // Status of setting up TCP connection -#define SOCK_SYNSENT_ACK 0x04 // Status of setting up TCP connection -#define SOCK_SYNRECV 0x05 // Status of setting up TCP connection -#define SOCK_ESTABLISHED 0x06 // Status of TCP connection established -#define SOCK_CLOSE_WAIT 0x07 // Status of closing TCP connection -#define SOCK_LAST_ACK 0x08 // Status of closing TCP connection -#define SOCK_FIN_WAIT1 0x09 // Status of closing TCP connection -#define SOCK_FIN_WAIT2 0x0A // Status of closing TCP connection -#define SOCK_CLOSING 0x0B // Status of closing TCP connection -#define SOCK_TIME_WAIT 0x0C // Status of closing TCP connection -#define SOCK_RESET 0x0D // Status of closing TCP connection -#define SOCK_INIT 0x0E // Status of socket initialization -#define SOCK_UDP 0x0F // Status of UDP -#define SOCK_RAW 0x10 // Status of IP RAW - -/* TERN Behavior Parameters */ -#define TERN_TDMA_THRES 10000 // Use DMA for transmits if data > thres bytes. -#define TERN_RDMA_THRES 10000 // Use DMA for receives if data > thres bytes. - // High thres value effectively disables DMA - -void far interrupt in4_isr_i2chip(void); - -//void ISR_ESTABLISHED(SOCKET s); -//void ISR_CLOSED(SOCKET s); -//void ISR_RX(SOCKET s); - -void initW3100A(void); -void sysinit(u_char sbufsize, u_char rbufsize); -void setsubmask(u_char * addr); -void setgateway(u_char * addr); -void setMACAddr(u_char * addr); -void setIP(u_char * addr); - -char socket(SOCKET s, u_char protocol, u_int port, u_char flag); - -void setIPprotocol(SOCKET s, u_char ipprotocol); - -void setINTMask(u_char mask); -void settimeout(u_char * val); -void setTOS(SOCKET s, u_char tos); - -void GetDestAddr(SOCKET s, u_char* addr); - -//void setbroadcast(SOCKET s); - -char connect(SOCKET s, u_char far * addr, u_int port); -char NBconnect(SOCKET s, u_char far * addr, u_int port); - -//char listen(SOCKET s, u_char far * addr, u_int far * port); -char NBlisten(SOCKET s); - -void initseqnum(SOCKET s); - -int send(SOCKET s, u_char far * buf, u_int len); -int send_in(SOCKET s, u_char far * buf, u_int len); -int recv(SOCKET s, u_char far * buf, u_int len); - -u_int sendto(SOCKET , u_char far * buf, u_int, u_char * addr, u_int); -u_int sendto_in(SOCKET , u_char far *, u_int); -u_int recvfrom(SOCKET , u_char far * buf, u_int, u_char * addr, u_int *); - -u_int read_data(SOCKET s, u_int src_offset, u_char far * dst, u_int len); -u_int write_data(SOCKET s, u_char far * src, u_int dst_offset, u_int len); - -void close(SOCKET s); -char reset_sock(SOCKET s); - -u_int select(SOCKET s, u_char func); -void recv_clear(SOCKET s); -u_char tx_empty(SOCKET s); - -#endif // __SOCKET_H__ diff --git a/Demo/WizNET_DEMO_TERN_186/include/TYPES.H b/Demo/WizNET_DEMO_TERN_186/include/TYPES.H deleted file mode 100644 index eb4551e94..000000000 --- a/Demo/WizNET_DEMO_TERN_186/include/TYPES.H +++ /dev/null @@ -1,64 +0,0 @@ -/* -******************************************************************************** -* Wiznet. -* 5F Simmtech Bldg., 228-3, Nonhyun-dong, Kangnam-gu, -* Seoul, Korea -* -* (c) Copyright 2002, Wiznet, Seoul, Korea -* -* Filename : types.h -* Programmer(s): -* Created : 2002/01/ -* Modified : -* Description : Define of data type. -******************************************************************************** -*/ - -#ifndef _TYPES_H_ -#define _TYPES_H_ - -#ifndef NULL -# define NULL ((void *) 0) -#endif - -typedef enum { false, true } bool; - -#ifndef _SIZE_T -#define _SIZE_T -typedef unsigned int size_t; -#endif - -typedef unsigned char BYTE; // 8-bit value -typedef unsigned char UCHAR; // 8-bit value -typedef int INT; // 16-bit value -typedef unsigned int UINT; // 16-bit value -typedef unsigned short USHORT; // 16-bit value -typedef unsigned short WORD; // 16-bit value -typedef unsigned long ULONG; // 32-bit value -typedef unsigned long DWORD; // 32-bit value - -// bsd -typedef unsigned char u_char; // 8-bit value -typedef unsigned short u_short; // 16-bit value -typedef unsigned int u_int; // 16-bit value -typedef unsigned long u_long; // 32-bit value - -typedef UCHAR SOCKET; - - -/* Type for treating 4 byte variables with byte by byte */ -typedef union un_l2cval - { - u_long lVal; - u_char cVal[4]; - }; - -/* Type for treating 2 byte variables with byte by byte */ -typedef union un_i2cval - { - u_int iVal; - u_char cVal[2]; - }; - -#endif // _TYPES_H_ - diff --git a/Demo/WizNET_DEMO_TERN_186/include/ae.H b/Demo/WizNET_DEMO_TERN_186/include/ae.H deleted file mode 100644 index 060c7efb0..000000000 --- a/Demo/WizNET_DEMO_TERN_186/include/ae.H +++ /dev/null @@ -1,264 +0,0 @@ -#ifndef _AE_H_ -#define _AE_H_ - -/********************************************************************* - ae.h headers for AM188ES 6-20-99 7-16-98 -*********************************************************************/ -/* Data structure for Serial operation */ - -typedef struct { - unsigned char ready; /* TRUE when ready */ - unsigned char baud; - unsigned int mode; - unsigned char iflag; /* interrupt status */ - unsigned char* in_buf; /* Input buffer */ - unsigned int in_tail; /* Input buffer TAIL ptr */ - unsigned int in_head; /* Input buffer HEAD ptr */ - unsigned int in_size; /* Input buffer size */ - unsigned int in_crcnt; /* Input count */ - unsigned char in_mt; /* Input buffer FLAG */ - unsigned char in_full; /* input buffer full */ - unsigned char* out_buf; /* Output buffer */ - unsigned int out_tail; /* Output buffer TAIL ptr */ - unsigned int out_head; /* Output buffer HEAD ptr */ - unsigned int out_size; /* Output buffer size */ - unsigned char out_full; /* Output buffer FLAG */ - unsigned char out_mt; /* Output buffer MT */ - unsigned char tmso; // transmit macro service operation - unsigned char rts; - unsigned char dtr; - unsigned char en485; - unsigned char err; - unsigned char node; - unsigned char cr; /* scc CR register */ - unsigned char slave; - unsigned int in_segm; /* input buffer segment */ - unsigned int in_offs; /* input buffer offset */ - unsigned int out_segm; /* output buffer segment */ - unsigned int out_offs; /* output buffer offset */ - unsigned char byte_delay; /* V25 macro service byte delay */ -} COM; - - -typedef struct{ - unsigned char sec1; - unsigned char sec10; - unsigned char min1; - unsigned char min10; - unsigned char hour1; - unsigned char hour10; - unsigned char day1; - unsigned char day10; - unsigned char mon1; - unsigned char mon10; - unsigned char year1; - unsigned char year10; - unsigned char wk; -} TIM; - -void ae_init(void); -void ae_reset(void); -void led(int i); //P12 used for led -void delay_ms(int m); -void delay0(unsigned int t); -void HLPRsetvect( - unsigned int wVec, /* Interrupt vector number */ - void far *ih /* Interrupt handler to install */ - ); - -void clka_en(int i); -void clkb_en(int i); -void pwr_save_en(int i); -void hitwd(void); - -// -// reset ee to remain enabled for reads -// where s = segment register value pointing to ee starting addr. -// for example = 0x8000 -// -void amd_ee_read_reset(unsigned int s); - -// -// sec=0x00-0x07 for AM29F010, 16K/sector -// sec=0 0x00000-0x03fff -// sec=1 0x04000-0x07fff -// sec=2 0x08000-0x0bfff -// sec=3 0x0c000-0x0ffff -// sec=4 0x10000-0x13fff -// sec=5 0x14000-0x17fff -// sec=6 0x18000-0x1bfff -// sec=7 0x1c000-0x1ffff -// -// sec=0x10-0x17 for AM29F040 -// sec=10 0x00000-0x0ffff -// sec=11 0x10000-0x1ffff -// sec=12 0x20000-0x2ffff -// sec=13 0x30000-0x3ffff -// sec=14 0x40000-0x4ffff -// sec=15 0x50000-0x5ffff -// sec=16 0x60000-0x6ffff -// sec=17 0x70000-0x7ffff -// segm=segment register value pointing to ee address 0 -// returns: if pass, return(0); -// if fail, return(1); -// -int amd_ee_sec_erase(unsigned int segm, unsigned char sec ); - -// -// write one byte dat to AM29F040, at address of s:o -// Approximately 70 us for 0 wait, 80us for 1 wait. -// where s=segment register, it is fixed to 0x8000 -// o=offset register -// returns: if pass, return(0); -// if fail, return(1); -// -// Be aware of that a data bit "0" can not be programmed back to a "1" !!! -// Attempting to do so will hang up the system !!! -// you can program the "1"s to "0"s. -// Only erase operation can convert "0"s to "1"s -// -// - -int amd_ee_byte_pro_512(unsigned int s, unsigned int o, unsigned char dat); - -// -// write one byte dat to AM29F010, at address of s:o, 80us per byte approx. -// where s=segment register, you may use s=0x8000-0xe000 -// o=offset register -// returns: if pass, return(0); -// if fail, return(1); -// -// Be aware of that a data bit "0" can not be programmed back to a "1" !!! -// Attempting to do so will hang up the system !!! -// you can program the "1"s to "0"s. -// Only erase operation can convert "0"s to "1"s -// - -int amd_ee_byte_pro_128(unsigned int s, unsigned int o, unsigned char dat); - -// -// unsigned char rtc_rds(char* time_string); -// put a time string into time_string, based on the reading of RTC. -// At least 15 bytes of buffer must be available for the time_string -// returns 0, if RTC OK, or returns 1, if problem -// -unsigned char rtc_rds(char* time_string); -int rtc_rd(TIM *r); -void rtc_init(unsigned char*); -unsigned char r_rd(void); -int r_out(unsigned char v); - - -void t2_init(unsigned int tm,unsigned int ta,void interrupt far(*t2_isr)()); -void t1_init(unsigned int tm,unsigned int ta,unsigned int tb,void interrupt far(*t1_isr)()); -void t0_init(unsigned int tm,unsigned int ta,unsigned int tb,void interrupt far(*t0_isr)()); -unsigned int t2_rd(void); -unsigned int t1_rd(void); -unsigned int t0_rd(void); - -// Analog to Digital conversion using TLC2543 on the A-Engine-88/86 -// Input: -// unsigned char c = input channel -// c = 0, input ch = AD0 -// c = 1, input ch = AD1 -// c = 2, input ch = AD2 -// c = 3, input ch = AD3 -// c = 4, input ch = AD4 -// c = 5, input ch = AD5 -// c = 6, input ch = AD6 -// c = 7, input ch = AD7 -// c = 8, input ch = AD8 -// c = 9, input ch = AD9 -// c = a, input ch = AD10 -// In order to operate ADC, P11 must be input. -// P11 is shared by RTC, EE. It must be high while power on/reset -// For AE88, using PPI for ADC, I20,I21,I22 must be output -// For AE86, using PAL for ADC, T0=CLK, T1=DIN, T2=ADCS -// Enter the ae_ad12(unsigned char c); EE is stopped first. -// Enter the ae86_ad12(unsigned char c); EE is stopped first. -// -// Output: 12 bit AD data of the previous channel ! -// Unipolar: -// (Vref+ - Vref-)=0x7ff -// Vref- = 0x000 -// Vref+ = 0xfff -// -// -int ae_ad12(unsigned char c); - -// outportb(0x120,1); // T0=0, CLK -// outportb(0x128,1); // T1=0, DIN -// outportb(0x130,1); // T2=0, ADCS -int ae86_ad12(unsigned char c); - -void nmi_init(void interrupt far (* nmi_isr)()); -void int0_init(unsigned char i, void interrupt far (*int0_isr)()); -void int1_init(unsigned char i, void interrupt far (*int1_isr)()); -void int2_init(unsigned char i, void interrupt far (*int2_isr)()); -void int3_init(unsigned char i, void interrupt far (*int3_isr)()); -void int4_init(unsigned char i, void interrupt far (*int4_isr)()); -void int5_init(unsigned char i, void interrupt far (*int5_isr)()); -void int6_init(unsigned char i, void interrupt far (*int6_isr)()); - - -// -// void pio_init(char bit, char mode) -// where bit=0-31 -// mode=0, Normal operation -// mode=1, Input with pullup/down -// mode=2, Output -// mode=3, input without pull -// -void pio_init(char bit, char mode); - - -// -// void pio_wr(char bit, char dat) -// where bit=0-31 -// dat=0/1 -// -void pio_wr(char bit, char dat); - -// -// unsigned int pio_rd(char port) -// return P15-P0, if port=0 -// return P31-P16, if port=1 -// -unsigned int pio_rd(char port); - -// setup I/O wait states for I/O instructions -// where wait = 0-7 -// wait=0, wait states = 0, I/O enable for 100 ns -// wait=1, wait states = 1, I/O enable for 100+25 ns -// wait=2, wait states = 2, I/O enable for 100+50 ns -// wait=3, wait states = 3, I/O enable for 100+75 ns -// wait=4, wait states = 5, I/O enable for 100+125 ns -// wait=5, wait states = 7, I/O enable for 100+175 ns -// wait=6, wait states = 9, I/O enable for 100+225 ns -// wait=7, wait states = 15, I/O enable for 100+375 ns -void io_wait(char wait); - -unsigned int crc16(unsigned char *wptr, unsigned int count); - -/****************************************************** - void ae_da(int dat1, int dat2) - output dat to U11 DAC of AE88 - Requires P12=CLK, P26=DI, P29=LD/CS as output pins ! - where dat1 for channel A, dat2 for channel B; dat1/2 = 0-4095 -*******************************************************/ -void ae_da(int dat1, int dat2); - -/****************************************************** - void ae86_da(int dat1, int dat2) - output dat to U15 DAC of AE86 - Requires T0=CLK=0x120, T1=DI=0x128, T3=LD/CS=0x138 - where dat1 for channel A, dat2 for channel B; dat1/2 = 0-4095 - Output 0-2.5V at VA=J4.16, VB=J4.18 -*******************************************************/ -void ae86_da(int dat1, int dat2); -void interrupt reset_io_trap(); - -#endif - - - \ No newline at end of file diff --git a/Demo/WizNET_DEMO_TERN_186/include/i2chip_hw.h b/Demo/WizNET_DEMO_TERN_186/include/i2chip_hw.h deleted file mode 100644 index 2ea32c139..000000000 --- a/Demo/WizNET_DEMO_TERN_186/include/i2chip_hw.h +++ /dev/null @@ -1,309 +0,0 @@ -/* -******************************************************************************** -* TERN, Inc. -* (c) Copyright 2005, http://www.tern.com -* -* - Created to support i2chip module on a variety of TERN hardware platforms. -******************************************************************************** -*/ - -#ifndef _I2CHIP_HW_H_ -#define _I2CHIP_HW_H_ - -#include "types.h" - -#ifdef TERN_SC // SensorCore controller, has mapping identical to the RL -#define TERN_RL -#endif - -#ifdef TERN_RL // R-Engine-L controller, with mapping at MCS0. -#define I2CHIP_MCS_DIRECT -#define I2CHIP_INT4 -#define TERN_RE -#endif // TERN_RL - -#ifdef TERN_5E -#define TERN_586 -#endif - -#ifdef TERN_RD -#define TERN_RE -#endif // TERN_RD - -#ifdef TERN_RE -#define TERN_186 -#endif - -#ifdef TERN_P51 -void p51_window(unsigned int page); -#define I2CHIP_WINDOW -#define I2CHIP_P51 -#ifdef TERN_186 -#define I2CHIP_INT4 -#define TERN_16_BIT -#endif // TERN_186 -#ifdef TERN_586 -#define I2CHIP_INT0 -#define I2CHIP_WINDOW_IO -#endif // TERN_586 -#endif // TERN_P51 - -#ifdef TERN_CEYE -#define TERN_EE // C-Eye configured with onboard i2chip, same as EE -#endif - -#ifdef TERN_EE -#define TERN_186 -#define I2CHIP_MCS_DIRECT -#define I2CHIP_INT4 -#define TERN_16_BIT -#endif // TERN_EE - -#ifdef TERN_MMC -#define I2CHIP_WINDOW -#define I2CHIP_MMC -#ifdef TERN_RD -#define I2CHIP_INT3 -#else -#ifdef TERN_186 -#define I2CHIP_INT4 -#endif // TERN_186 -#endif // TERN_RD -#ifdef TERN_586 -#define I2CHIP_INT0 -#define I2CHIP_WINDOW_IO -#endif // TERN_586 -#endif // TERN_MMC - -#ifdef TERN_586 -#include "586.h" -void interrupt far int0_isr(void); -void interrupt far spu_m_isr(void); -void interrupt far spu_1_isr(void); -void interrupt far spu_2_isr(void); -#define MMCR 0xdf00 -#endif // TERN_586 - -#ifdef TERN_186 -#ifndef TERN_RE -#include "ae.h" -#else -#include "re.h" -#define I2CHIP_SHIFTED_ADDRESS -#endif -#endif - - -#ifndef I2CHIP_MCS_DIRECT -#ifndef I2CHIP_WINDOW -#ifndef I2CHIP_WINDOW_IO -#error You must define the TERN address mapping used to drive the I2CHIP module! -#endif // I2CHIP_WINDOW_IO -#endif // I2CHIP_MMC_WINDOW -#endif // I2CHIP_MCS_DIRECT - -#ifndef I2CHIP_INT0 -#ifndef I2CHIP_INT3 -#ifndef I2CHIP_INT4 -#ifndef I2CHIP_POLL -#error You must specify an interrupt/polling mechanism for the I2CHIP module! -#endif // I2CHIP_POLL -#endif // I2CHIP_INT3 -#endif // I2CHIP_INT4 -#endif // I2CHIP_INT0 - -#ifdef I2CHIP_POLL -#define I2CHIP_POLL_ISR(a) { delay_ms(20); disable(); a(); enable(); } -#define INT_INIT(isr) -#define INT_EOI -#endif // I2CHIP_POLL - -#ifdef I2CHIP_INT4 -#define INT_INIT(isr) int4_init(1, isr) -#define INT_EOI outport(0xff22,0x0010) -#define I2CHIP_POLL_ISR(a) -#endif - -#ifdef I2CHIP_INT3 -#define INT_INIT(isr) int3_init(1, isr) -#define INT_EOI outport(0xff22,0x000f) -#define I2CHIP_POLL_ISR(a) -#endif - -#ifdef I2CHIP_INT0 -#define INT_INIT(isr) int0_init(1, isr) -#define INT_EOI outportb(_MPICOCW2_IO,0x61); // 586 only EOI -#define I2CHIP_POLL_ISR(a) -#endif - - -#ifdef I2CHIP_SHIFTED_ADDRESS -#define SA_OFFSET(a) ((a) << 1) -#else -#define SA_OFFSET(a) a -#endif // I2CHIP_SHIFTED_ADDRESS ... *if* - - -// -------------------- WINDOW-RELATED DEFINES ---------------------- -#ifdef I2CHIP_WINDOW -void i2chip_set_page(u_int addr); -#define I2CHIP_SET_PAGE(p) i2chip_set_page(p) - -u_char far* i2chip_mkptr(u_int addr); -void i2chip_push_window(u_int addr); -void i2chip_pop_window(void); -u_int i2chip_get_window(void); -void i2chip_set_window(u_int window_addr); - -// Set to command window. -// Note that if you're using other MMC chips within your application, you will -// need to call this function regularly, if you've changed the MMC chip/page -// selection via mmc_window(). The driver code otherwise assume that you never -// change away from chip 7, page 0. -#define WINDOW_RESTORE_BASE i2chip_mkptr(0) - -// ----------------------- I2CHIP_WINDOW_IO ---------------------------- -#ifdef I2CHIP_WINDOW_IO - -#ifdef TERN_5E -#define I2CHIP_BASE_SEG 0x2000 // Address offset for W3100A -#else -#define I2CHIP_BASE_SEG 0x1800 // Address offset for W3100A -#endif - -#define COMMAND_BASE_SEG 0x0000 -#define SEND_DATA_BUF 0x4000 // Internal Tx buffer address of W3100A -#define RECV_DATA_BUF 0x6000 // Internal Rx buffer address of W3100A -#define WINDOW_BASE_SEGM COMMAND_BASE_SEG - -#define MK_FP_WINDOW(a, b) i2chip_mkptr(a+SA_OFFSET(b)) -#define MK_FP_SA MK_FP_WINDOW - -u_char io_read_value(u_char far* addr); -void io_write_value(u_char far* addr, u_char value); -#define READ_VALUE(a) io_read_value(a) -#define WRITE_VALUE(a, v) io_write_value(a, v) - -#define WINDOW_PTR_INC(a) \ - if ((FP_OFF(a) & 0xff) == 0xff) \ - a = MK_FP_WINDOW(i2chip_get_window() + 0x100, 0); \ - else \ - a++; - -#endif // I2CHIP_WINDOW_IO - -// -------------------- !NOT! I2CHIP_WINDOW_IO ---------------------------- -#ifndef I2CHIP_WINDOW_IO - -#define READ_VALUE(a) *(a) -#define WRITE_VALUE(a, v) *(a) = v - -#define WINDOW_BASE_SEGM 0x8000 -#define MK_FP_WINDOW(a, b) i2chip_mkptr(a+SA_OFFSET(b)) -#define MK_FP_SA MK_FP_WINDOW - -#ifdef I2CHIP_SHIFTED_ADDRESS -#define COMMAND_BASE_SEG 0x0000 -#define SEND_DATA_BUF 0x8000 -#define RECV_DATA_BUF 0xC000 -#define WINDOW_PTR_INC(a) \ - if ((FP_OFF(a) & 0xff) == 0xfe) \ - a = MK_FP_WINDOW(i2chip_get_window() + 0x100, 0); \ - else \ - a+=2; -#else -#define COMMAND_BASE_SEG 0x0000 -#define SEND_DATA_BUF 0x4000 -#define RECV_DATA_BUF 0x6000 -#define WINDOW_PTR_INC(a) \ - if ((FP_OFF(a) & 0xff) == 0xff) \ - a = MK_FP_WINDOW(i2chip_get_window() + 0x100, 0); \ - else \ - a++; -#endif // I2CHIP_SHIFTED_ADDRESS -#endif // NOT I2CHIP_WINDOW_IO - -#endif // I2CHIP_WINDOW - -// -------------------- I2CHIP_DIRECT ---------------------------- -#ifdef I2CHIP_MCS_DIRECT - -#define READ_VALUE(a) *(a) -#define WRITE_VALUE(a, v) *(a) = v - -#define I2CHIP_BASE_SEG 0x8000 -#define MK_FP_SA(a, b) MK_FP(a, SA_OFFSET(b)) -#define WINDOW_PTR_INC(a) a+=SA_OFFSET(1); -#define WINDOW_RESTORE_BASE -#define MK_FP_WINDOW MK_FP_SA -#define WINDOW_BASE_SEG I2CHIP_BASE_SEG -#define COMMAND_BASE_SEG I2CHIP_BASE_SEG - -#ifdef I2CHIP_SHIFTED_ADDRESS -#define SEND_DATA_BUF 0x8800 // Internal Tx buffer address of W3100A -#define RECV_DATA_BUF 0x8C00 // Internal Rx buffer address of W3100A -#else -#define SEND_DATA_BUF 0x8400 // Internal Tx buffer address of W3100A -#define RECV_DATA_BUF 0x8600 // Internal Rx buffer address of W3100A -#endif // I2CHIP_SHIFTED_ADDRESS - -#endif // I2CHIP_MCS_DIRECT - -/* Internal register set of W3100A */ -#define COMMAND(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, i))) -#define INT_STATUS(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, I2CHIP_C0_ISR + i))) -#define INT_REG ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, I2CHIP_IR))) -#define INTMASK ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, I2CHIP_IMR))) -#define RESETSOCK ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, 0x0A))) - -#define RX_PTR_BASE I2CHIP_C0_RW_PR -#define RX_PTR_SIZE (I2CHIP_C1_RW_PR - I2CHIP_C0_RW_PR) - -#define RX_WR_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, RX_PTR_BASE + RX_PTR_SIZE * i))) -#define RX_RD_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, RX_PTR_BASE + RX_PTR_SIZE * i + 0x04))) -#define RX_ACK_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, TX_PTR_BASE + TX_PTR_SIZE * i + 0x08))) - -#define TX_PTR_BASE I2CHIP_C0_TW_PR -#define TX_PTR_SIZE (I2CHIP_C1_TW_PR - I2CHIP_C0_TW_PR) - -#define TX_WR_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, TX_PTR_BASE + TX_PTR_SIZE * i))) -#define TX_RD_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, TX_PTR_BASE + TX_PTR_SIZE * i + 0x04))) -#define TX_ACK_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, RX_PTR_BASE + RX_PTR_SIZE * i + 0x08))) - -/* Shadow Register Pointer Define */ -/* For windowing purposes, these are definitely outside the first 256-byte Window... -therefore, use the MK_FP_WINDOW macros instead. */ -#define SHADOW_RXWR_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, 0x1E0 + 3*i))) -#define SHADOW_RXRD_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, 0x1E1 + 3*i))) -#define SHADOW_TXACK_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, 0x1E2 + 3*i))) -#define SHADOW_TXWR_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, 0x1F0 + 3*i))) -#define SHADOW_TXRD_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, 0x1F1 + 3*i))) - -#define SOCK_BASE I2CHIP_C0_SSR -#define SOCK_SIZE (I2CHIP_C1_SSR - I2CHIP_C0_SSR) - -#define SOCK_STATUS(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, SOCK_BASE + SOCK_SIZE * i))) -#define OPT_PROTOCOL(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, SOCK_BASE + SOCK_SIZE * i + 0x01))) -#define DST_HA_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, SOCK_BASE + SOCK_SIZE * i + 0x02))) -#define DST_IP_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, SOCK_BASE + SOCK_SIZE * i + 0x08))) -#define DST_PORT_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, SOCK_BASE + SOCK_SIZE * i + 0x0C))) -#define SRC_PORT_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, SOCK_BASE + SOCK_SIZE * i + 0x0E))) -#define IP_PROTOCOL(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, SOCK_BASE + SOCK_SIZE * i + 0x10))) -#define TOS(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG,SOCK_BASE + SOCK_SIZE * i + 0x11))) -#define MSS(i) ((u_int far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, SOCK_BASE + SOCK_SIZE * i + 0x12))) -#define P_WINDOW(i) ((u_int far *)(MK_FP_WINDOW(COMMAND_BASE_SEG,SOCK_BASE + SOCK_SIZE * i + 0x14))) -#define WINDOW(i) ((u_int far*)(MK_FP_WINDOW(COMMAND_BASE_SEG, SOCK_BASE + SOCK_SIZE * i + 0x16))) - -#define GATEWAY_PTR ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG,I2CHIP_GAR))) -#define SUBNET_MASK_PTR ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG,I2CHIP_SMR))) - -#define SRC_HA_PTR ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG,I2CHIP_SHAR))) -#define SRC_IP_PTR ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG,I2CHIP_SIPR))) -#define TIMEOUT_PTR ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG,I2CHIP_IRTR))) - -#define RX_DMEM_SIZE ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG,I2CHIP_RMSR))) -#define TX_DMEM_SIZE ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG,I2CHIP_TMSR))) - -void i2chip_init(void); - -#endif // _irchip_hw_h diff --git a/Demo/WizNET_DEMO_TERN_186/include/utils/system_common.h b/Demo/WizNET_DEMO_TERN_186/include/utils/system_common.h deleted file mode 100644 index 1a40cf80d..000000000 --- a/Demo/WizNET_DEMO_TERN_186/include/utils/system_common.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef _SYSTEM_COMMON_H_ -#define _SYSTEM_COMMON_H_ - -typedef unsigned char UCHAR8; -typedef unsigned int UINT16; - -#define RETURN_OK 0 // Non-zero return values are always - // error values. -#define RETURN_ILLEGAL 1 // Some sort of illegal argument. -#define RETURN_MEM 2 // Out of memory space. - -#endif // _SYSTEM_COMMON_H_ \ No newline at end of file diff --git a/Demo/WizNET_DEMO_TERN_186/main.c b/Demo/WizNET_DEMO_TERN_186/main.c deleted file mode 100644 index 022302232..000000000 --- a/Demo/WizNET_DEMO_TERN_186/main.c +++ /dev/null @@ -1,196 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * Creates all the demo application tasks then starts the scheduler. In - * addition to the standard demo application tasks main() creates the - * HTTPServer task, and a "Check" task. The Check task periodically inspects - * all the other tasks in the system to see if any errors have been reported. - * The error status is then displayed on the served WEB page. - */ - -/* Tern includes. */ -#include -#include - -/* FreeRTOS.org includes. */ -#include -#include - -/* Demo application includes. */ -#include "HTTPTask.h" -#include "integer.h" -#include "PollQ.h" -#include "semtest.h" -#include "dynamic.h" -#include "BlockQ.h" -#include "Death.h" -#include "serial.h" -#include "comtest.h" - -/* How often should the "check" task execute? */ -#define mainCHECK_DELAY ( 3000 / portTICK_RATE_MS ) - -/* Priorities allocated to the various tasks. */ -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainHTTP_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainSUICIDE_TASKS_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) - -/* Used to indicate the error status. A value of 0 means that an error has not -been detected in any task. A non zero value indicates which group of demo -tasks has reported an error. See prvCheckTask() for bit definitions. */ -unsigned portSHORT usCheckStatus = 0; - -/*-----------------------------------------------------------*/ - -/* - * Setup any hardware required by the demo - other than the RTOS tick which - * is configured when the scheduler is started. - */ -static void prvSetupHardware( void ); - -/* - * Periodically inspect all the other tasks, updating usCheckStatus should an - * error be discovered in any task. - */ -static void prvCheckTask( void *pvParameters ); -/*-----------------------------------------------------------*/ - -void main(void) -{ - prvSetupHardware(); - - /* Start the HTTP server task. */ - xTaskCreate( vHTTPTask, "WizNet", configMINIMAL_STACK_SIZE, NULL, mainHTTP_TASK_PRIORITY, NULL ); - - /* Start the demo/test application tasks. See the demo application - section of the FreeRTOS.org WEB site for more information. */ - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartDynamicPriorityTasks(); - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - vStartComTestTasks( mainCOM_TEST_PRIORITY, serCOM2, ser57600 ); - - /* Start the task that checks the other demo tasks for errors. */ - xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - - /* The suicide tasks must be created last as they monitor the number of - tasks in the system to ensure there are no more or fewer than expected - compared to the number that were executing when the task started. */ - vCreateSuicidalTasks( mainSUICIDE_TASKS_PRIORITY ); - - /* Finally start the scheduler. */ - vTaskStartScheduler(); - - /* Should not get here! */ - for( ;; ); -} -/*-----------------------------------------------------------*/ - -static void prvSetupHardware( void ) -{ - ae_init(); -} -/*-----------------------------------------------------------*/ - -static void prvCheckTask( void *pvParameters ) -{ - ( void ) pvParameters; - - /* Check all the demo tasks to ensure that they are all still running, and - that none of them have detected an error. */ - for( ;; ) - { - /* Block until it is time to check again. */ - vTaskDelay( mainCHECK_DELAY ); - - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - usCheckStatus |= 0x01; - } - - if( xArePollingQueuesStillRunning() != pdTRUE ) - { - usCheckStatus |= 0x02; - } - - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - usCheckStatus |= 0x04; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - usCheckStatus |= 0x08; - } - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - usCheckStatus |= 0x10; - } - - if( xIsCreateTaskStillRunning() != pdTRUE ) - { - usCheckStatus |= 0x20; - } - - if( xAreComTestTasksStillRunning() != pdTRUE ) - { - usCheckStatus |= 0x40; - } - } -} -/*-----------------------------------------------------------*/ - -/* This is included to prevent link errors - allowing the 'full' version of -the comtest tasks to be used. It can be ignored. */ -void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend ) -{ - ( void ) ppcMessageToSend; -} - - - - - - - - - - - - diff --git a/Demo/WizNET_DEMO_TERN_186/serial/serial.c b/Demo/WizNET_DEMO_TERN_186/serial/serial.c deleted file mode 100644 index e87bcf5b4..000000000 --- a/Demo/WizNET_DEMO_TERN_186/serial/serial.c +++ /dev/null @@ -1,442 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -#include -#include -#include "FreeRTOS.h" -#include "portasm.h" -#include "queue.h" -#include "task.h" -#include "semphr.h" - -#define serMAX_PORTS ( ( unsigned portSHORT ) 2 ) - -#define serPORT_0_INT_REG ( 0xff44 ) -#define serPORT_0_BAUD_REG ( 0xff88 ) -#define serPORT_0_RX_REG ( 0xff86 ) -#define serPORT_0_TX_REG ( 0xff84 ) -#define serPORT_0_STATUS_REG ( 0xff82 ) -#define serPORT_0_CTRL_REG ( 0xff80 ) -#define serPORT_0_IRQ ( 0x14 ) - -#define serPORT_1_INT_REG ( 0xff42 ) -#define serPORT_1_BAUD_REG ( 0xff18 ) -#define serPORT_1_RX_REG ( 0xff16 ) -#define serPORT_1_TX_REG ( 0xff14 ) -#define serPORT_1_STATUS_REG ( 0xff12 ) -#define serPORT_1_CTRL_REG ( 0xff10 ) -#define serPORT_1_IRQ ( 0x11 ) - -#define serTX_EMPTY ( ( unsigned portSHORT ) 0x40 ) -#define serRX_READY ( ( unsigned portSHORT ) 0x80 ) - -#define serRESET_PIC( usEOI_TYPE ) portOUTPUT_WORD( ( unsigned portSHORT ) 0xff22, usEOI_TYPE ) -#define serTX_HOLD_EMPTY_INT ( ( unsigned portSHORT ) 0x100 ) - -#define serENABLE_INTERRUPTS ( ( unsigned portSHORT ) 0x80 ) -#define serMODE ( ( unsigned portSHORT ) 0x01 ) -#define serENABLE_TX_MACHINES ( ( unsigned portSHORT ) 0x40 ) -#define serENABLE_RX_MACHINES ( ( unsigned portSHORT ) 0x20 ) -#define serINTERRUPT_MASK ( ( unsigned portSHORT ) 0x08 ) -#define serCLEAR_ALL_STATUS_BITS ( ( unsigned portSHORT ) 0x00 ) -#define serINTERRUPT_PRIORITY ( ( unsigned portSHORT ) 0x01 ) /*< Just below the scheduler priority. */ - -#define serDONT_BLOCK ( ( portTickType ) 0 ) - -typedef enum -{ - serCOM1 = 0, - serCOM2, - serCOM3, - serCOM4, - serCOM5, - serCOM6, - serCOM7, - serCOM8 -} eCOMPort; - -typedef enum -{ - serNO_PARITY, - serODD_PARITY, - serEVEN_PARITY, - serMARK_PARITY, - serSPACE_PARITY -} eParity; - -typedef enum -{ - serSTOP_1, - serSTOP_2 -} eStopBits; - -typedef enum -{ - serBITS_5, - serBITS_6, - serBITS_7, - serBITS_8 -} eDataBits; - -typedef enum -{ - ser50 = 0, - ser75, - ser110, - ser134, - ser150, - ser200, - ser300, - ser600, - ser1200, - ser1800, - ser2400, - ser4800, - ser9600, - ser19200, - ser38400, - ser57600, - ser115200 -} eBaud; - -typedef struct xCOM_PORT -{ - /* Hardware parameters for this port. */ - portSHORT sTxInterruptOn; - unsigned portSHORT usIntReg; - unsigned portSHORT usBaudReg; - unsigned portSHORT usRxReg; - unsigned portSHORT usTxReg; - unsigned portSHORT usStatusReg; - unsigned portSHORT usCtrlReg; - - unsigned portSHORT usIRQVector; - - /* Queues used for communications with com test task. */ - xQueueHandle xRxedChars; - xQueueHandle xCharsForTx; - - /* This semaphore does nothing useful except test a feature of the - scheduler. */ - xSemaphoreHandle xTestSem; - -} xComPort; - -static xComPort xPorts[ serMAX_PORTS ] = -{ - { pdFALSE, serPORT_0_INT_REG, serPORT_0_BAUD_REG, serPORT_0_RX_REG, serPORT_0_TX_REG, serPORT_0_STATUS_REG, serPORT_0_CTRL_REG, serPORT_0_IRQ, NULL, NULL, NULL }, - { pdFALSE, serPORT_1_INT_REG, serPORT_1_BAUD_REG, serPORT_1_RX_REG, serPORT_1_TX_REG, serPORT_1_STATUS_REG, serPORT_1_CTRL_REG, serPORT_1_IRQ, NULL, NULL, NULL } -}; - -typedef xComPort * xComPortHandle; - -/** - * Lookup the baud rate from the enum. - */ -static unsigned portLONG prvBaud( eBaud eWantedBaud ); - -/* These prototypes are repeated here so we don't have to include the serial header. This allows -the xComPortHandle structure details to be private to this file. */ -xComPortHandle xSerialPortInit( eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits, unsigned portBASE_TYPE uxBufferLength ); -portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, portCHAR *pcRxedChar, portTickType xBlockTime ); -portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, portCHAR cOutChar, portTickType xBlockTime ); -void vSerialClose( xComPortHandle xPort ); -portSHORT sSerialWaitForSemaphore( xComPortHandle xPort ); -/*-----------------------------------------------------------*/ - -static portSHORT xComPortISR( xComPort * const pxPort ); - -#define vInterruptOn( pxPort, usInterrupt ) \ -{ \ -unsigned portSHORT usIn; \ - \ - portENTER_CRITICAL(); \ - { \ - if( pxPort->sTxInterruptOn == pdFALSE ) \ - { \ - usIn = portINPUT_WORD( pxPort->usCtrlReg ); \ - portOUTPUT_WORD( pxPort->usCtrlReg, usIn | usInterrupt ); \ - \ - pxPort->sTxInterruptOn = pdTRUE; \ - } \ - } \ - portEXIT_CRITICAL(); \ -} -/*-----------------------------------------------------------*/ - -#define vInterruptOff( pxPort, usInterrupt ) \ -{ \ - unsigned portSHORT usIn = portINPUT_WORD( pxPort->usCtrlReg ); \ - if( usIn & usInterrupt ) \ - { \ - portOUTPUT_WORD( pxPort->usCtrlReg, usIn & ~usInterrupt); \ - pxPort->sTxInterruptOn = pdFALSE; \ - } \ -} -/*-----------------------------------------------------------*/ - - -/* Define an interrupt handler for each port */ -#define COM_IRQ_WRAPPER(N) \ - static void __interrupt COM_IRQ##N##_WRAPPER( void ) \ - { \ - if( xComPortISR( &( xPorts[##N##] ) ) ) \ - { \ - portEND_SWITCHING_ISR(); \ - } \ - } - - - -COM_IRQ_WRAPPER( 0 ) -COM_IRQ_WRAPPER( 1 ) - -static pxISR xISRs[ serMAX_PORTS ] = -{ - COM_IRQ0_WRAPPER, - COM_IRQ1_WRAPPER -}; - -/*-----------------------------------------------------------*/ - -static unsigned portLONG prvBaud( eBaud eWantedBaud ) -{ - switch( eWantedBaud ) - { - case ser50 : return 50UL; - case ser75 : return 75UL; - case ser110 : return 110UL; - case ser134 : return 134UL; - case ser150 : return 150UL; - case ser200 : return 200UL; - case ser300 : return 300UL; - case ser600 : return 600UL; - case ser1200 : return 1200UL; - case ser1800 : return 1800UL; - case ser2400 : return 2400UL; - case ser4800 : return 4800UL; - case ser19200 : return 19200UL; - case ser38400 : return 38400UL; - case ser57600 : return 57600UL; - case ser115200 : return 115200UL; - default : return 9600UL; - } -} - -/*-----------------------------------------------------------*/ - -xComPortHandle xSerialPortInit( eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits, unsigned portBASE_TYPE uxBufferLength ) -{ -unsigned portSHORT usPort; -xComPortHandle pxPort = NULL; -unsigned portLONG ulBaudDiv; - - /* BAUDDIV = ( Microprocessor Clock / Baud Rate ) / 16 */ - ulBaudDiv = ( configCPU_CLOCK_HZ / prvBaud( eWantedBaud ) ) / 16UL; - - /* Only n, 8, 1 is supported so these parameters are not required for this - port. */ - ( void ) eWantedParity; - ( void ) eWantedDataBits; - ( void ) eWantedStopBits; - - /* Currently only n,8,1 is supported. */ - - usPort = ( unsigned portSHORT ) ePort; - - if( usPort < serMAX_PORTS ) - { - pxPort = &( xPorts[ usPort ] ); - - portENTER_CRITICAL(); - { - unsigned portSHORT usInWord; - - /* Create the queues used by the com test task. */ - pxPort->xRxedChars = xQueueCreate( uxBufferLength, ( unsigned portBASE_TYPE ) sizeof( portCHAR ) ); - pxPort->xCharsForTx = xQueueCreate( uxBufferLength, ( unsigned portBASE_TYPE ) sizeof( portCHAR ) ); - - /* Create the test semaphore. This does nothing useful except test a feature of the scheduler. */ - vSemaphoreCreateBinary( pxPort->xTestSem ); - - /* There is no ISR here already to restore later. */ - setvect( ( portSHORT ) pxPort->usIRQVector, xISRs[ usPort ] ); - - usInWord = portINPUT_WORD( pxPort->usIntReg ); - usInWord &= ~serINTERRUPT_MASK; - usInWord |= serINTERRUPT_PRIORITY; - portOUTPUT_WORD( pxPort->usIntReg, usInWord ); - - portOUTPUT_WORD( pxPort->usBaudReg, ( unsigned portSHORT ) ulBaudDiv ); - portOUTPUT_WORD( pxPort->usCtrlReg, serENABLE_INTERRUPTS | serMODE | serENABLE_TX_MACHINES | serENABLE_RX_MACHINES ); - - portOUTPUT_WORD( pxPort->usStatusReg, serCLEAR_ALL_STATUS_BITS ); - } - portEXIT_CRITICAL(); - } - - return pxPort; -} /*lint !e715 Some parameters are not used as only a subset of the serial port functionality is currently implemented. */ -/*-----------------------------------------------------------*/ - -void vSerialPutString( xComPortHandle pxPort, const portCHAR * const pcString, unsigned portSHORT usStringLength ) -{ -unsigned portSHORT usByte; -portCHAR *pcNextChar; - - pcNextChar = ( portCHAR * ) pcString; - - for( usByte = 0; usByte < usStringLength; usByte++ ) - { - xQueueSend( pxPort->xCharsForTx, pcNextChar, serDONT_BLOCK ); - pcNextChar++; - } - - vInterruptOn( pxPort, serTX_HOLD_EMPTY_INT ); -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, portCHAR *pcRxedChar, portTickType xBlockTime ) -{ - /* Get the next character from the buffer, note that this routine is only - called having checked that the is (at least) one to get */ - if( xQueueReceive( pxPort->xRxedChars, pcRxedChar, xBlockTime ) ) - { - return pdTRUE; - } - else - { - return pdFALSE; - } -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, portCHAR cOutChar, portTickType xBlockTime ) -{ - if( xQueueSend( pxPort->xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) - { - return pdFAIL; - } - - vInterruptOn( pxPort, serTX_HOLD_EMPTY_INT ); - - return pdPASS; -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xSerialWaitForSemaphore( xComPortHandle xPort ) -{ -const portTickType xBlockTime = ( portTickType ) 0xffff; - - /* This function does nothing interesting, but test the - semaphore from ISR mechanism. */ - return xSemaphoreTake( xPort->xTestSem, xBlockTime ); -} -/*-----------------------------------------------------------*/ - -void vSerialClose( xComPortHandle xPort ) -{ -unsigned portSHORT usOutput; - - /* Turn off the interrupts. We may also want to delete the queues and/or - re-install the original ISR. */ - - portENTER_CRITICAL(); - { - usOutput = portINPUT_WORD( xPort->usCtrlReg ); - - usOutput &= ~serENABLE_INTERRUPTS; - usOutput &= ~serENABLE_TX_MACHINES; - usOutput &= ~serENABLE_RX_MACHINES; - portOUTPUT_WORD( xPort->usCtrlReg, usOutput ); - - usOutput = portINPUT_WORD( xPort->usIntReg ); - usOutput |= serINTERRUPT_MASK; - portOUTPUT_WORD( xPort->usIntReg, usOutput ); - } - portEXIT_CRITICAL(); -} -/*-----------------------------------------------------------*/ -unsigned short usStatus; -static portBASE_TYPE xComPortISR( xComPort * const pxPort ) -{ -unsigned portSHORT usStatusRegister; -portCHAR cChar; -portBASE_TYPE xTaskWokenByPost = pdFALSE, xAnotherTaskWokenByPost = pdFALSE, xTaskWokenByTx = pdFALSE; - - /* NOTE: THIS IS NOT AN EFFICIENT ISR AS IT IS DESIGNED SOLELY TO TEST - THE SCHEDULER FUNCTIONALITY. REAL APPLICATIONS SHOULD NOT USE THIS - FUNCTION. */ - - usStatusRegister = portINPUT_WORD( pxPort->usStatusReg ); - - if( usStatusRegister & serRX_READY ) - { - cChar = ( portCHAR ) portINPUT_WORD( pxPort->usRxReg ); - xTaskWokenByPost = xQueueSendFromISR( pxPort->xRxedChars, &cChar, xTaskWokenByPost ); - - /* Also release the semaphore - this does nothing interesting and is just a test. */ - xAnotherTaskWokenByPost = xSemaphoreGiveFromISR( pxPort->xTestSem, xAnotherTaskWokenByPost ); - } - else if( pxPort->sTxInterruptOn && ( usStatusRegister & serTX_EMPTY ) ) - { - if( xQueueReceiveFromISR( pxPort->xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE ) - { - portOUTPUT_WORD( pxPort->usTxReg, ( unsigned portSHORT ) cChar ); - } - else - { - /* Queue empty, nothing to send */ - vInterruptOff( pxPort, serTX_HOLD_EMPTY_INT ); - } - } - - serRESET_PIC( pxPort->usIRQVector ); - - /* If posting to the queue woke a task that was blocked on the queue we may - want to switch to the woken task - depending on its priority relative to - the task interrupted by this ISR. */ - if( xTaskWokenByPost || xAnotherTaskWokenByPost || xTaskWokenByTx) - { - return pdTRUE; - } - else - { - return pdFALSE; - } -} - - - - - diff --git a/Demo/WizNET_DEMO_TERN_186/tern_code/i2chip_hw.c b/Demo/WizNET_DEMO_TERN_186/tern_code/i2chip_hw.c deleted file mode 100644 index eb513ef1b..000000000 --- a/Demo/WizNET_DEMO_TERN_186/tern_code/i2chip_hw.c +++ /dev/null @@ -1,239 +0,0 @@ -/* -******************************************************************************** -* TERN, Inc. -* (c) Copyright 2005, http://www.tern.com -* -* - Created to support i2chip module on a variety of TERN hardware platforms. -******************************************************************************** -*/ - -#include -#include "i2chip_hw.h" - -#ifdef I2CHIP_MMC -#include "mmc.h" -#endif - -void i2chip_init(void) -{ - -#ifdef TERN_586 -/* - poke(MMCR,_BOOTCSCTL_,peek(MMCR,_BOOTCSCTL_)&0xffc9); // ROM 1 wait - poke(MMCR,_ROMCS2CTL_,peek(MMCR,_ROMCS2CTL_)&0xffc8); // SRAM 0 wait - - pokeb(MMCR, _GPCSRT_, 24); // set the GP CS recovery time, 12 works - pokeb(MMCR, _GPCSPW_, 128); // set the GP CS width, 64 works - pokeb(MMCR, _GPCSOFF_, 16); // set the GP CS offset, 8 works - pokeb(MMCR, _GPRDW_, 80); // set the GP RD pulse width, 50 works - pokeb(MMCR, _GPRDOFF_, 30); // set the GP RD offset, 15 works - pokeb(MMCR, _GPWRW_, 80); // set the GP WR pulse width, 50 - pokeb(MMCR, _GPWROFF_, 30); // set the GP WR offset, 15 -*/ - -#ifdef TERN_5E - pokeb(MMCR, _GPCSDW_, peekb(MMCR, _GPCSDW_)&0xf7); // set /CS3-/CSM Data Width=8 - pokeb(MMCR, _CSPFS_, peekb(MMCR, _CSPFS_)|0x08); // set the GP CS3 PIN Function - poke(MMCR, _PAR15_, 0x2000); // set CS3 I/O region - poke(MMCR, _PAR15_+2, 0x2dff); // set CS3 I/O region, 512 bytes - - pokeb(MMCR, _GPCSDW_, peekb(MMCR, _GPCSDW_)&0x7f); // CS7=J4.3 Data Width=8, /CSI -// pokeb(MMCR, _GPCSDW_, peekb(MMCR, _GPCSDW_)|0x80); // CS7=J4.3 Data Width=16 - pokeb(MMCR, _CSPFS_, peekb(MMCR, _CSPFS_)|0x80); // set the GP CS7 PIN Function - poke(MMCR, _PAR7_, 0x4000); // set CS7 I/O region - poke(MMCR, _PAR7_+2, 0x3dff); // set CS7 I/O region, 512 bytes -#else - // If it's not 5E, then it must be 5P... in which case, we use PCS0 and - // PCS1 as the chip-selects. - pokeb(MMCR, _GPCSDW_, peekb(MMCR, _GPCSDW_)&0xfe); // CS0 Data Width=8 - poke(MMCR, _PIOPFS31_16_, peek(MMCR,_PIOPFS31_16_)|0x0800); // P27=/CS0 - poke(MMCR, _PAR13_, 0x1800); // CS0 I/O region - poke(MMCR, _PAR13_+2, 0x21ff); // CS0 I/O RW, 512 bytes, start 0x1800 -#endif - -a HLPRsetvect(0x47, (void far *) spu_m_isr); - HLPRsetvect(0x4f, (void far *) spu_1_isr); - HLPRsetvect(0x57, (void far *) spu_2_isr); -#endif // 186, or RE - -#ifdef TERN_186 - pio_init(18, 0); // P18=CTS1 for /PCS2 - -#ifdef TERN_16_BIT - outport(0xfff2, 2); // AUXCON, MCS, Bus 16-bit -#endif - -#ifdef I2CHIP_MCS_DIRECT - outport(0xffa0,0xc0bf); // UMCS, 256K ROM, disable AD15-0 - outport(0xfff0,inport(0xfff0)|0x4000 ); // SYSCON, MCS0 0x80000-0xbffff - outport(0xffa8,0xa0bf ); // MPCS, MCS0=P14, 64KB, PCS I/O, - outport(0xffa6,0x81ff); // MMCS, base 0x80000, - outport(0xffa2,0x7fbf); // 512K RAM, - outport(0xffa4,0x007d); // PACS, base 0, - -#else - - outport( 0xffa0,0xc0bf); // UMCS, 256K ROM, 3 wait, disable AD15-0 - outport( 0xfff0,inport(0xfff0)|0x4000 ); // SYSCON, MCS0 0x80000-0xbffff -// outport( 0xffa8,0xa0bc ); // MPCS, MCS0=P14, 64KB, PCS I/O 0 wait -// outport( 0xffa8,0xa0bd ); // MPCS, MCS0=P14, 64KB, PCS I/O 1 wait - outport( 0xffa8,0xa0bf ); // MPCS, MCS0=P14, 64KB, PCS I/O 1 wait -#endif // I2CHIP_MCS_DIRECT - -#ifndef TERN_RE // 80 MHz R- boards can't tolerate zero wait state. - outport( 0xffa6,0x81ff ); // MMCS, base 0x80000 - outport(0xffa2,0x7fbe); // 512K RAM, 0 wait states - outport(0xffa4,0x007d); // PACS, base 0, 0 wait -#endif - pio_init(14,0); // Enable /MCS0 - -#endif // TERN_186 - - -#ifdef I2CHIP_WINDOW -#ifdef I2CHIP_SHIFTED_ADDRESS - pio_init(12, 2); // Configure P12 as A7, an output we'll be using. - pio_wr(12, 0); // Set A7 low, initially. -#endif - WINDOW_RESTORE_BASE; // Equivalent to calling mmc_window(7, 0); -#endif -} - -#ifdef I2CHIP_WINDOW - -void i2chip_set_page(u_int page) -{ - u_int new_page = page; - -#ifdef I2CHIP_SHIFTED_ADDRESS - if (page & 0x01) // ... we're checking the right-most bit in the page. - outport(0xff74, inport(0xff74) | 0x1000 ); // Using P12 as A7... - else - outport(0xff74, inport(0xff74) & 0xefff ); - - new_page = page >> 1; -#endif - -#ifdef I2CHIP_MMC - mmc_window(7, new_page); // See mmc.c -#endif -#ifdef I2CHIP_P51 - p51_window(new_page); -#endif -} - -static u_int s_addr = 0xffff; -u_char far* i2chip_mkptr(u_int addr) -{ - if ((s_addr & 0xff00) == (addr & 0xff00)) // No point... no point... - return MK_FP(WINDOW_BASE_SEGM, addr & 0xff); - - s_addr = addr ; - - // So the argument to this function is... what again? - // I think it should be the highest 16-bits... or, in other words, - // FP_SEG of a huge ptr. - // Ok, and the *return* value should be a UINT value for the new - // segment address to be used, if it's at all needed. TODO - I2CHIP_SET_PAGE(s_addr >> 8); // Portable version -// outportb(0x00, addr>>8); // quicker version - - return MK_FP(WINDOW_BASE_SEGM, addr & 0xff); -} - -void i2chip_set_window(u_int window_addr) -{ - s_addr = window_addr; - I2CHIP_SET_PAGE(s_addr >> 8); -} - -// Still inside #define I2CHIP_WINDOW ... - -u_int i2chip_get_window(void) -{ - return s_addr & 0xff00; -} - -void i2chip_push_window(u_int addr) -{ - I2CHIP_SET_PAGE(addr>>8); -} - -void i2chip_pop_window(void) -{ - I2CHIP_SET_PAGE(s_addr >> 8); -} - -#ifdef I2CHIP_WINDOW_IO -u_char io_read_value(u_char far* addr) -{ - // return value ... we assume the page is already set. So, instead, - // we just go ahead and output valeu. - return inportb(I2CHIP_BASE_SEG + (FP_OFF(addr) & 0xff)); -} - -void io_write_value(u_char far* addr, u_char value) -{ - // Get the last whatever bytes... and write value. - outportb(I2CHIP_BASE_SEG + (FP_OFF(addr) & 0xff), value); -} - -#endif // I2CHIP_WINDOW_IO - - -#ifdef I2CHIP_P51 -void p51_window(unsigned int page) -{ -asm xor ax, ax -asm mov ax, page -#ifdef I2CHIP_WINDOW_IO -asm mov dx, 1040h -asm out dx, al -#else -asm out 040h, al -#endif -// use J1.19=/CS6 -} -#endif // I2CHIP_P51 - -#endif // I2CHIP_WINDOW - -#ifdef TERN_586 -/* -// Function: spu_m_isr -// P22=Master PIC IR7, interrupt vector=0x47, /INTA -*/ -void interrupt far spu_m_isr(void) -{ -disable(); -// Issue the EOI to interrupt controller -outportb(_MPICOCW2_IO,0x67); // Specific EQI for master IR7 -enable(); -} - -/* -// Function: spu_1_isr -// P10=slave1 PIC IR7, Master IR2, interrupt vector=0x4f, /INTC -*/ -void interrupt far spu_1_isr(void) -{ -disable(); -// Issue the EOI to interrupt controller - outportb(_S1PICOCW2_IO,0x67); // Specific EOI for slave 1 IR7 - outportb(_MPICOCW2_IO,0x62); // Specific EQI for master IR2 -enable(); -} - -/* -// Function: spu_2_isr -// P20=Slave2 PIC IR7, Master IR5, interrupt vector=0x57, GPIRQ7=PIO16 GP timer1 -*/ -void interrupt far spu_2_isr(void) -{ -disable(); -// Issue the EOI to interrupt controller - outportb(_S2PICOCW2_IO,0x67); // Specific EOI for slave 1 IR7 - outportb(_MPICOCW2_IO,0x65); // Specific EQI for master IR5 -enable(); -} -#endif diff --git a/Demo/WizNET_DEMO_TERN_186/tern_code/socket.c b/Demo/WizNET_DEMO_TERN_186/tern_code/socket.c deleted file mode 100644 index 4749e16d8..000000000 --- a/Demo/WizNET_DEMO_TERN_186/tern_code/socket.c +++ /dev/null @@ -1,1869 +0,0 @@ -/* -******************************************************************************** -* TERN, Inc. -* (c) Copyright 2005, http://www.tern.com -* -* MODIFIED BY RICHARD BARRY TO ADD SEMAPHORE FOR COMMUNICATION BETWEEN THE -* WIZnet ISR AND THE HTTP TASK. -* -* - Derived based on development version provided by Wiznet. -* -* Filename : socket.h -* Programmer(s): -* Created : 2002/06/20 -* Modified : -* 2002/09/27 : - Renaming -* INT_STATUS --> INT_REG -* STATUS(i) --> INT_STATUS(i) -* C_STATUS(i) --> SOCK_STATUS(i) -* 2003/11/06 : Ported for use with TERN controller. Note all byte access is at even addresses -* 2005/10/8 : Modified constants for easier initialization. -* -* Description : Header file of W3100A for TERN embedded controller -******************************************************************************** -*/ -/* -############################################################################### -File Include Section -############################################################################### -*/ -#include "i2chip_hw.h" -#include "socket.h" -#include "types.h" -#include -#include - -#include -#include -#include - - -/* -############################################################################### -Local Variable Declaration Section -############################################################################### -*/ -u_char I_STATUS[4]; // Store Interrupt Status according to channels -u_int Local_Port; // Designate Local Port -union un_l2cval SEQ_NUM; // Set initial sequence number - -u_long SMASK[MAX_SOCK_NUM]; // Variable to store MASK of Tx in each channel, - // on setting dynamic memory size. -u_long RMASK[MAX_SOCK_NUM]; // Variable to store MASK of Rx in each channel, - // on setting dynamic memory size. -int SSIZE[MAX_SOCK_NUM]; // Maximun Tx memory size by each channel -int RSIZE[MAX_SOCK_NUM]; // Maximun Rx memory size by each channel - -u_int SBUFBASEADDRESS[MAX_SOCK_NUM]; // Maximun Tx memory base address by each channel -u_int RBUFBASEADDRESS[MAX_SOCK_NUM]; // Maximun Rx memory base address by each channel - -/* -############################################################################### -Function Implementation Section -############################################################################### -*/ - -/* -******************************************************************************** -* Interrupt handling function of the W3100A -* -* Description : -* Stores the status information that each function waits for in the global variable I_STATUS -* for transfer. I_STATUS stores the interrupt status value for each channel. -* Arguments : None -* Returns : None -* Note : Internal Function -******************************************************************************** -*/ - -portBASE_TYPE prvProcessISR( void ) -{ -unsigned char status; -extern xSemaphoreHandle xTCPSemaphore; -portBASE_TYPE xSwitchRequired = pdFALSE; - -#ifdef I2CHIP_WINDOW -u_int current_window = i2chip_get_window(); -#endif - -status = READ_VALUE(INT_REG); - - -if (status) - { - xSwitchRequired = pdTRUE; - // channel 0 interrupt(sysinit, sockinit, established, closed, timeout, send_ok, recv_ok) - if (status & 0x01) - { - I_STATUS[0] = READ_VALUE(INT_STATUS(0)); - -// if (I_STATUS[0] & SESTABLISHED) -// ISR_ESTABLISHED(0); -// if (I_STATUS[0] & SCLOSED) -// ISR_CLOSED(0); - - WRITE_VALUE(INT_REG, 0x01); - } - - // channel 1 interrupt(sysinit, sockinit, established, closed, timeout, send_ok, recv_ok) - if (status & 0x02) - { - I_STATUS[1] = READ_VALUE(INT_STATUS(1)); - -// if (I_STATUS[1] & SESTABLISHED) -// ISR_ESTABLISHED(1); -// if (I_STATUS[1] & SCLOSED) -// ISR_CLOSED(1); - - WRITE_VALUE(INT_REG, 0x02); - } - - // channel 2 interrupt(sysinit, sockinit, established, closed, timeout, send_ok, recv_ok) - if (status & 0x04) - { - I_STATUS[2] = READ_VALUE(INT_STATUS(2)); - -// if (I_STATUS[2] & SESTABLISHED) -// ISR_ESTABLISHED(2); -// if (I_STATUS[2] & SCLOSED) -// ISR_CLOSED(2); - - WRITE_VALUE(INT_REG, 0x04); - } - - // channel 3 interrupt(sysinit, sockinit, established, closed, timeout, send_ok, recv_ok) - if (status & 0x08) - { - I_STATUS[3] = READ_VALUE(INT_STATUS(3)); - -// if (I_STATUS[3] & SESTABLISHED) ISR_ESTABLISHED(3); -// if (I_STATUS[3] & SCLOSED) ISR_CLOSED(3); - - WRITE_VALUE(INT_REG, 0x08); - } - - // channel 0 receive interrupt - if (status & 0x10) - { -// ISR_RX(0); - WRITE_VALUE(INT_REG, 0x10); - } - - // channel 1 receive interrupt - if (status & 0x20) - { -// ISR_RX(1); - WRITE_VALUE(INT_REG, 0x20); - } - - // channel 2 receive interrupt - if (status & 0x40) - { -// ISR_RX(2); - WRITE_VALUE(INT_REG, 0x40); - } - - // channel 3 receive interrupt - if (status & 0x80) - { -// ISR_RX(3); - WRITE_VALUE(INT_REG, 0x80); - } - status = READ_VALUE(INT_REG); - } - -WRITE_VALUE(INT_REG, 0xFF); - -#ifdef I2CHIP_WINDOW -i2chip_set_window(current_window); -#endif - - if( xSwitchRequired == pdTRUE ) - { - xSwitchRequired = xSemaphoreGiveFromISR( xTCPSemaphore, pdFALSE ); - } - - return xSwitchRequired; -} - -void far interrupt in4_isr_i2chip(void) -{ - if( prvProcessISR() == pdTRUE ) - { - portEND_SWITCHING_ISR(); - } - - INT_EOI; -} - -/* -**************************************************************************************************** -* Established connection interrupt handling function. -* -* Description : -* Called upon connection establishment, and may be inserted in user code if needed by -* the programmer. -* Arguments : None -* Returns : None -* Note : Internal Function -**************************************************************************************************** -*/ -/* -void ISR_ESTABLISHED(SOCKET s) -{ -// TO ADD YOUR CODE -} -*/ - -/* -**************************************************************************************************** -* Closed connection interrupt handling function -* -* Description : -* Called upon connection closure, and may be inserted in user code if needed by the programmer. -* Arguments : None -* Returns : None -* Note : Internal Function -**************************************************************************************************** -*/ -/* -void ISR_CLOSED(SOCKET s) -{ -// TO ADD YOUR CODE -} -*/ - -/* -**************************************************************************************************** -* Received data interrupt handling function -* -* Description : -* Called upon receiving data, and may be inserted in user code if needed by the programmer. -* Arguments : None -* Returns : None -* Note : Internal Function -**************************************************************************************************** -*/ -/* -void ISR_RX(SOCKET s) -{ -// TO ADD YOUR CODE -} -*/ - -/* -**************************************************************************************************** -* W3100A Initialization Function -* -* Description: Reset of W3100A S/W and Registeration of i386 interrupt -* Arguments : None. -* Returns : None. -* Note : -**************************************************************************************************** -*/ -void initW3100A(void) -{ - -// Install interrupt handler for i2Chip -INT_INIT(in4_isr_i2chip); - - -Local_Port = 1000; // This default value will be set if you didn't designate it when you - // create a socket. If you don't designate port number and create a - // socket continuously, the port number will be assigned with - // incremented by one to Local_Port -SEQ_NUM.lVal = 4294967293ul; // Sets the initial SEQ# to be used for TCP communication. - // (It should be ramdom value) -WRITE_VALUE(COMMAND(0), CSW_RESET); // Software RESET -} - -/* -**************************************************************************************************** -* W3100A initialization function -* -* Description : -* Sets the Tx, Rx memory size by each channel, source MAC, source IP, gateway, and subnet mask -* to be used by the W3100A to the designated values. -* May be called when reflecting modified network information or Tx, Rx memory size on the W3100A -* Include Ping Request for ARP update (In case that a device embedding W3100A is directly -* connected to Router) -* Arguments : sbufsize - Tx memory size (00 - 1KByte, 01- 2KBtye, 10 - 4KByte, 11 - 8KByte) -* bit 1-0 : Tx memory size of channel #0 -* bit 3-2 : Tx memory size of channel #1 -* bit 5-4 : Tx memory size of channel #2 -* bit 7-6 : Tx memory size of channel #3 -* rbufsize - Rx memory size (00 - 1KByte, 01- 2KBtye, 10 - 4KByte, 11 - 8KByte) -* bit 1-0 : Rx memory size of channel #0 -* bit 3-2 : Rx memory size of channel #1 -* bit 5-4 : Rx memory size of channel #2 -* bit 7-6 : Rx memory size of channel #3 -* Returns : None -* Note : API Function -* Maximum memory size for Tx, Rx in W3100A is 8KBytes, -* In the range of 8KBytes, the memory size could be allocated dynamically by -* each channel -* Be attentive to sum of memory size shouldn't exceed 8Kbytes -* and to data transmission and receiption from non-allocated channel may cause -* some problems. -* If 8KBytes memory already is assigned to centain channel, other 3 channels -* couldn't be used, for there's no available memory. -* If two 4KBytes memory are assigned to two each channels, other 2 channels couldn't -* be used, for there's no available memory. -* (Example of memory assignment) -* sbufsize => 00000011, rbufsize => 00000011 : -* Assign 8KBytes for Tx and Rx to channel #0, Cannot use channel #1,#2,#3 -* sbufsize => 00001010, rbufsize => 00001010 : -* Assign 4KBytes for Tx and Rx to each channel #0,#1 respectively. Cannot use -* channel #2,#3 -* sbufsize => 01010101, rbufsize => 01010101 : -* Assign 2KBytes for Tx and Rx to each all channels respectively. -* sbufsize => 00010110, rbufsize => 01010101 : -* Assign 4KBytes for Tx, 2KBytes for Rx to channel #0 -* s 2KBytes for Tx, 2KBytes for Rx to channel #1 -* 2KBytes for Tx, 2KBytes for Rx to channel #2 -* 2KBytes is available exclusively for Rx in channel #3. There's no memory for Tx. -**************************************************************************************************** -*/ -void sysinit(u_char sbufsize, u_char rbufsize) -{ -char i; -int ssum,rsum; - -ssum = 0; -rsum = 0; - -// Set Tx memory size for each channel -WRITE_VALUE(TX_DMEM_SIZE, sbufsize); - -// Set Rx memory size for each channel -WRITE_VALUE(RX_DMEM_SIZE, rbufsize); - -// Set Base Address of Tx memory for channel #0 -SBUFBASEADDRESS[0] = 0; - -// Set Base Address of Rx memory for channel #0 -RBUFBASEADDRESS[0] = 0; - -// Set maximum memory size for Tx and Rx, mask, base address of memory by each channel -for(i = 0 ; i < MAX_SOCK_NUM; i++) - { - SSIZE[i] = 0; - RSIZE[i] = 0; - if(ssum < 8192) - { - switch((sbufsize >> i*2) & 0x03) // Set maximum Tx memory size - { - case 0: - SSIZE[i] = 1024; - SMASK[i] = 0x000003FF; - break; - - case 1: - SSIZE[i] = 2048; - SMASK[i] = 0x000007FF; - break; - - case 2: - SSIZE[i] = 4096; - SMASK[i] = 0x00000FFF; - break; - - case 3: - SSIZE[i] = 8192; - SMASK[i] = 0x00001FFF; - break; - } - } - if(rsum < 8192) - { - switch((rbufsize >> i*2) & 0x03) // Set maximum Rx memory size - { - case 0: - RSIZE[i] = 1024; - RMASK[i] = 0x000003FF; - break; - - case 1: - RSIZE[i] = 2048; - RMASK[i] = 0x000007FF; - break; - - case 2: - RSIZE[i] = 4096; - RMASK[i] = 0x00000FFF; - break; - - case 3: - RSIZE[i] = 8192; - RMASK[i] = 0x00001FFF; - break; - } - } - ssum += SSIZE[i]; - rsum += RSIZE[i]; - - // Set base address of Tx and Rx memory for channel #1,#2,#3 - if(i != 0) - { - SBUFBASEADDRESS[i] = ssum - SSIZE[i]; - RBUFBASEADDRESS[i] = rsum - RSIZE[i]; - } - } - - WRITE_VALUE(COMMAND(0), CSYS_INIT); - -while(!(I_STATUS[0] & SSYS_INIT_OK)) - I2CHIP_POLL_ISR(in4_isr_i2chip); - -#ifdef __PING__ - { - u_char xdata pingbuf[8]; - setIPprotocol(0, IPPROTO_ICMP); - socket(0, SOCK_IPL_RAW, 3000,0); // Create a socket for ARP update - - pingbuf[0] = 8; // ICMP TYPE - pingbuf[1] = 0; // ICMP CODE - pingbuf[2] = 0xf7; // CHECKSUM (already calculated) - pingbuf[3] = 0xfd; - pingbuf[4] = 0; // ID - pingbuf[5] = 1; - pingbuf[6] = 0; // SEQ # - pingbuf[7] = 1; - pingbuf[8] = 0; // Data 1 Byte - - sendto(0, pingbuf, 9, GATEWAY_PTR,3000); // Ping Request - close(0); - printf("Route MAC Update Success"); - } -#endif -} - -/* -**************************************************************************************************** -* Function to set subnet mask -* -* Description: -* Arguments : addr--> Pointer that has the value to be set -* Returns : None. -* Note : -**************************************************************************************************** -*/ -void setsubmask(u_char * addr) -{ -u_char i; -u_char far* sm_ptr = SUBNET_MASK_PTR; // We can only convert to 'regular' - // pointer if we're confident arithmetic - // won't take us out of current window. - -for (i = 0; i < 4; i++) - { - WRITE_VALUE(sm_ptr + SA_OFFSET(i), addr[i]); - } -} - -/* -**************************************************************************************************** -* Function to set gateway IP -* -* Description: -* Arguments : addr--> Pointer that has Gateway IP to be set -* Returns : None. -* Note : -**************************************************************************************************** -*/ -void setgateway(u_char * addr) -{ -u_char i; -u_char far* gw_ptr = GATEWAY_PTR; // We can only convert to 'regular' - // pointer if we're confident arithmetic - // won't take us out of current window. -for (i = 0; i < 4; i++) - { - WRITE_VALUE(gw_ptr + SA_OFFSET(i), addr[i]); - } -} - -/* -**************************************************************************************************** -* Function to set W3100A IP -* -* Description: -* Arguments : addr--> Pointer that has Source IP to be set -* Returns : None. -* Note : -**************************************************************************************************** -*/ -void setIP(u_char * addr) -{ -u_char i; -u_char far* src_ptr = SRC_IP_PTR; // We can only convert to 'regular' - // pointer if we're confident arithmetic - // won't take us out of current window. - -for (i = 0; i < 4; i++) - { - WRITE_VALUE(src_ptr + SA_OFFSET(i), addr[i]); - } -} - -// DEBUG -void getIP(u_char* addr) -{ -u_char i; -u_char far* src_ptr = SRC_IP_PTR; // We can only convert to 'regular' - // pointer if we're confident arithmetic - // won't take us out of current window. - -for (i = 0; i < 4; i++) - addr[i] = READ_VALUE(src_ptr + SA_OFFSET(i)); -} - - -/* -**************************************************************************************************** -* Function to set MAC -* -* Description: -* Arguments : addr--> Pointer that has MAC to be set -* Returns : None. -* Note : -**************************************************************************************************** -*/ -void setMACAddr(u_char * addr) -{ -u_char i; -u_char far* ha_ptr = SRC_HA_PTR; // We can only convert to 'regular' - // pointer if we're confident arithmetic - // won't take us out of current window. - -for (i = 0; i < 6; i++) - { - WRITE_VALUE(ha_ptr + SA_OFFSET(i), addr[i]); - } -} - -/* -**************************************************************************************************** -* Function to set TCP timeout -* -* Description: The function that used to adjust time to resend TCP -* Arguments : val --> Pointer that has the value to be set -* Upper 2 byte:Initial timeout value -* Last 1 byte:The count to retry till timeout -* Returns : None. -* Note : -**************************************************************************************************** -*/ -void settimeout(u_char * val) -{ -u_char i; -u_char far* tout_ptr = TIMEOUT_PTR; // We can only convert to 'regular' - // pointer if we're confident arithmetic - // won't take us out of current window. - -for (i = 0; i < 3; i++) - { - WRITE_VALUE(tout_ptr + SA_OFFSET(i), val[i]); - } -} - -/* -**************************************************************************************************** -* Function to set interrupt mask. -* -* Description: -* Arguments : mask--> Mask value to be set ('1'-> interrupt ) -* Returns : None. -* Note : -**************************************************************************************************** -*/ -void setINTMask(u_char mask) -{ -WRITE_VALUE(INTMASK, mask); -} - -/* -**************************************************************************************************** -* Function to set enable in sending and receiving of broadcast data -* -* Description: Enable to process of broadcating data in UDP or IP RAW mode. -* Arguments : s --> Channel No. to be set -* Returns : None. -* Note : -**************************************************************************************************** -*/ -void setbroadcast(SOCKET s) -{ -u_char val = READ_VALUE(OPT_PROTOCOL(s)); -WRITE_VALUE(OPT_PROTOCOL(s), val | SOCKOPT_BROADCAST); -} - -/* -**************************************************************************************************** -* Function to set process protocol in IP RAW mode. -* -* Description: -* Arguments : s--> Channel No. to be set -* tos-->Protocol Value to be set -* Returns : None. -* Note : -**************************************************************************************************** -*/ -void setTOS(SOCKET s, u_char tos) -{ -WRITE_VALUE(TOS(s), tos); -} - -/* -**************************************************************************************************** -* Upper layer protocol setup function in IP RAW Mode -* -* Description : Upper layer protocol setup function in protocol field of IP header when -* developing upper layer protocol like ICMP, IGMP, EGP etc. by using IP Protocol -* Arguments : s - Channel number -* ipprotocol - Upper layer protocol setting value of IP Protocol -* (Possible to use designated IPPROTO_ in header file) -* Returns : None -* Note : API Function -* This function should be called before calling socket() that is, before -* socket initialization. -**************************************************************************************************** -*/ -void setIPprotocol(SOCKET s, u_char ipprotocol) -{ -WRITE_VALUE(IP_PROTOCOL(s), ipprotocol); -} - -/* -**************************************************************************************************** -* Initialization function to appropriate channel -* -* Description : Initialize designated channel and wait until W3100 has done. -* Arguments : s - channel number -* protocol - designate protocol for channel -* SOCK_STREAM(0x01) -> TCP. -* SOCK_DGRAM(0x02) -> UDP. -* SOCK_IPL_RAW(0x03) -> IP LAYER RAW. -* SOCK_MACL_RAW(0x04) -> MAC LAYER RAW. -* port - designate source port for appropriate channel -* flag - designate option to be used in appropriate. -* SOCKOPT_BROADCAST(0x80) -> Send/receive broadcast message in UDP -* SOCKOPT_NDTIMEOUT(0x40) -> Use register value which designated TIMEOUT -* value -* SOCKOPT_NDACK(0x20) -> When not using no delayed ack -* SOCKOPT_SWS(0x10) -> When not using silly window syndrome -* Returns : When succeeded : Channel number, failed :-1 -* Note : API Function -**************************************************************************************************** -*/ -char socket(SOCKET s, u_char protocol, u_int port, u_char flag) -{ -u_char k; - -//Designate socket protocol and option -WRITE_VALUE(OPT_PROTOCOL(s), protocol | flag); - -// setup designated port number -if (port != 0) - { - k = (u_char)((port & 0xff00) >> 8); - WRITE_VALUE(SRC_PORT_PTR(s), k); - k = (u_char)(port & 0x00ff); - WRITE_VALUE(SRC_PORT_PTR(s) + SA_OFFSET(1), k); - } -else - { - // Designate random port number which is managed by local when you didn't designate source port - Local_Port++; - - WRITE_VALUE(SRC_PORT_PTR(s), (u_char)((Local_Port & 0xff00) >> 8)); - WRITE_VALUE(SRC_PORT_PTR(s) + SA_OFFSET(1), (u_char)(Local_Port & 0x00ff)); - } - -// SOCK_INIT -I_STATUS[s] = 0; -WRITE_VALUE(COMMAND(s), CSOCK_INIT); - -// Waiting Interrupt to CSOCK_INIT -while (I_STATUS[s] == 0) - I2CHIP_POLL_ISR(in4_isr_i2chip); - -if (!(I_STATUS[s] & SSOCK_INIT_OK)) - return(-1); - -initseqnum(s); // Use initial seq# with random number - -return(s); -} - -/* -**************************************************************************************************** -* Connection establishing function to designated peer. -* -* Description : This function establish a connection to the peer by designated channel, -* and wait until the connection is established successfully. (TCP client mode) -* Arguments : s - channel number -* addr - destination IP Address -* port - destination Port Number -* Returns : when succeeded : 1, failed : -1 -* Note : API Function -**************************************************************************************************** -*/ -char connect(SOCKET s, u_char far * addr, u_int port) -{ - -if (port != 0) - { //designate destination port - WRITE_VALUE(DST_PORT_PTR(s), (u_char)((port & 0xff00) >> 8)); - WRITE_VALUE(DST_PORT_PTR(s) + SA_OFFSET(1), (u_char)(port & 0x00ff)); - } -else - return(-1); - - WRITE_VALUE(DST_IP_PTR(s), addr[0]); //designate destination IP address - WRITE_VALUE(DST_IP_PTR(s) + SA_OFFSET(1), addr[1]); - WRITE_VALUE(DST_IP_PTR(s) + SA_OFFSET(2), addr[2]); - WRITE_VALUE(DST_IP_PTR(s) + SA_OFFSET(3), addr[3]); - -I_STATUS[s] = 0; - - WRITE_VALUE(COMMAND(s), CCONNECT); // CONNECT - I2CHIP_POLL_ISR(in4_isr_i2chip); - -// Wait until connection is established successfully -while (I_STATUS[s] == 0) - { - // When failed, appropriate channel will be closed and return an error - if (select(s, SEL_CONTROL) == SOCK_CLOSED) - return -1; - } - -if (!(I_STATUS[s] & SESTABLISHED)) - return(-1); - -return(1); -} - -/* -**************************************************************************************************** -* Connection establishing function to designated peer. (Non-blocking Mode) -* -* Description : This function establish a connection to the peer by designated channel. -* -* Arguments : s - channel number -* addr - destination IP Address -* port - destination Port Number -* Returns : when succeeded : 1, failed : -1 -* Note : API Function -**************************************************************************************************** -*/ -char NBconnect(SOCKET s, u_char far * addr, u_int port) -{ - -if (port != 0) - { //designate destination port - WRITE_VALUE(DST_PORT_PTR(s), (u_char) ((port & 0xff00) >> 8) ); - WRITE_VALUE(DST_PORT_PTR(s) + SA_OFFSET(1), (u_char)(port & 0x00ff)); - } -else - return(-1); - - WRITE_VALUE(DST_IP_PTR(s), addr[0]); //designate destination IP address - WRITE_VALUE(DST_IP_PTR(s) + SA_OFFSET(1), addr[1]); - WRITE_VALUE(DST_IP_PTR(s) + SA_OFFSET(2), addr[2]); - WRITE_VALUE(DST_IP_PTR(s) + SA_OFFSET(3), addr[3]); - -I_STATUS[s] = 0; - -WRITE_VALUE(COMMAND(s), CCONNECT); // CONNECT -return(1); -} - -/* -**************************************************************************************************** -* Waits for connection request from a peer (Blocking Mode) -* -* Description : Wait for connection request from a peer through designated channel (TCP Server mode) -* Arguments : s - channel number -* addr - IP Address of the peer when a connection is established -* port - Port number of the peer when a connection is established -* Returns : When succeeded : 1, failed : -1 -* Note : API Function -**************************************************************************************************** -*/ -/* -char listen(SOCKET s, u_char far * addr, u_int far * port) -{ -u_int i; - -I_STATUS[s] = 0; - -// LISTEN -COMMAND(s) = CLISTEN; - -// Wait until connection is established -while (I_STATUS[s] == 0) - { - // When failed to connect, the designated channel will be closed and return an error. - if (select(s, SEL_CONTROL) == SOCK_CLOSED) - return -1; - } - -// Receive IP address and port number of the peer connected -if (I_STATUS[s] & SESTABLISHED) - { - i = *DST_PORT_PTR(s); - *port = (u_int)((i & 0xff00) >> 8); - i = *(DST_PORT_PTR(s) + 2); - i = (u_int)(i & 0x00ff); - *port += (i << 8); - - addr[0] = *DST_IP_PTR(s); - addr[1] = *(DST_IP_PTR(s) + 2); - addr[2] = *(DST_IP_PTR(s) + 4); - addr[3] = *(DST_IP_PTR(s) + 6); - } -else - return(-1); - -return(1); -} -*/ - -/* -**************************************************************************************************** -* Waits for connection request from a peer (Non-blocking Mode) -* -* Description : Wait for connection request from a peer through designated channel (TCP Server mode) -* Arguments : s - channel number -* Returns : None -* Note : API Function -**************************************************************************************************** -*/ -char NBlisten(SOCKET s) -{ -I_STATUS[s] = 0; - -// LISTEN -WRITE_VALUE(COMMAND(s), CLISTEN); - -return(1); -} - -/* -**************************************************************************************************** -* Create random value for initial Seq# when establishing TCP connection -* -* Description : In this function, you can add some source codes to create random number for -* initial Seq#. In real, TCP initial SEQ# should be random value. -* (Currently, we're using static value in EVB/DK.) -* Arguments : s - channel number -* Returns : None -* Note : API Function -**************************************************************************************************** -*/ -void initseqnum(SOCKET s) -{ -// Designate initial seq# -// If you have random number generation function, assign random number instead of SEQ_NUM.lVal++. -SEQ_NUM.lVal++; - -//randomize(); -//SEQ_NUM.lVal = rand(); - -WRITE_VALUE(TX_WR_PTR(s), SEQ_NUM.cVal[0]); -WRITE_VALUE(TX_WR_PTR(s) + SA_OFFSET(1), SEQ_NUM.cVal[1]); -WRITE_VALUE(TX_WR_PTR(s) + SA_OFFSET(2), SEQ_NUM.cVal[2]); -WRITE_VALUE(TX_WR_PTR(s) + SA_OFFSET(3), SEQ_NUM.cVal[3]); -delay0(2); - -WRITE_VALUE(TX_RD_PTR(s), SEQ_NUM.cVal[0]); -WRITE_VALUE(TX_RD_PTR(s) + SA_OFFSET(1), SEQ_NUM.cVal[1]); -WRITE_VALUE(TX_RD_PTR(s) + SA_OFFSET(2), SEQ_NUM.cVal[2]); -WRITE_VALUE(TX_RD_PTR(s) + SA_OFFSET(3), SEQ_NUM.cVal[3]); -delay0(2); - -WRITE_VALUE(TX_ACK_PTR(s), SEQ_NUM.cVal[0]); -WRITE_VALUE(TX_ACK_PTR(s) + SA_OFFSET(1), SEQ_NUM.cVal[1]); -WRITE_VALUE(TX_ACK_PTR(s) + SA_OFFSET(2), SEQ_NUM.cVal[2]); -WRITE_VALUE(TX_ACK_PTR(s) + SA_OFFSET(3), SEQ_NUM.cVal[3]); -delay0(2); -} - -/* -**************************************************************************************************** -* Function for sending TCP data. -* -* Description : Function for sending TCP data and Composed of the send() and send_in() functions. -* The send() function is an application I/F function. -* It continues to call the send_in() function to complete the sending of the data up to the -* size of the data to be sent when the application is called. -* The send_in() function receives the return value (the size of the data sent), calculates -* the size of the data to be sent, and calls the send_in() function again if there is any -* data left to be sent. -* Arguments : s - channel number -* buf - Pointer pointing data to send -* len - data size to send -* Returns : Succeed: sent data size, Failed: -1; -* Note : API Function -**************************************************************************************************** -*/ -int send(SOCKET s, u_char far * buf, u_int len) -{ -int ptr, size; -u_char huge* huge_buf = (u_char huge*)buf; -u_char far* local_buf = (u_char far*)huge_buf; - -if (len <= 0) - return (0); -else - { - ptr = 0; - do - { - size = send_in(s, local_buf + ptr, len); - if (size == -1) - return -1; - len = len - size; - ptr += size; - } while ( len > 0); - } -return ptr; -} - -/* -**************************************************************************************************** -* Internal function for sending TCP data. -* -* Description : Called by the send() function for TCP transmission. -* It first calculates the free transmit buffer size -* and compares it with the size of the data to be transmitted to determine the transmission size. -* After calculating the data size, it copies data from TX_WR_PTR. -* It waits if there is a previous send command in process. -* When the send command is cleared, it updates the TX_WR_PTR up to the size to be transmitted - and performs the send command. -* Arguments : s - channel number -* buf - Pointer pointing data to send -* len - data size to send -* Returns : Succeeded: sent data size, Failed: -1 -* Note : Internal Function -**************************************************************************************************** -*/ -int send_in(SOCKET s, u_char far * buf, u_int len) -{ -u_char k; -u_int size; -union un_l2cval wr_ptr, ack_ptr; -unsigned int offset; - -S_START: -disable(); // CT: Shadow register access should not conflict with ISR. -k = READ_VALUE(SHADOW_TXWR_PTR(s)); -WINDOW_RESTORE_BASE; // Needed whenever we touch a shadow ptr; different window. -delay0(2); -wr_ptr.cVal[3] = READ_VALUE(TX_WR_PTR(s)); -wr_ptr.cVal[2] = READ_VALUE(TX_WR_PTR(s) + SA_OFFSET(1)); -wr_ptr.cVal[1] = READ_VALUE(TX_WR_PTR(s) + SA_OFFSET(2)); -wr_ptr.cVal[0] = READ_VALUE(TX_WR_PTR(s) + SA_OFFSET(3)); - -k = READ_VALUE(SHADOW_TXACK_PTR(s)); -WINDOW_RESTORE_BASE; // Needed whenever we touch a shadow ptr; different window. -delay0(2); -ack_ptr.cVal[3] = READ_VALUE(TX_ACK_PTR(s)); -ack_ptr.cVal[2] = READ_VALUE(TX_ACK_PTR(s) + SA_OFFSET(1)); -ack_ptr.cVal[1] = READ_VALUE(TX_ACK_PTR(s) + SA_OFFSET(2)); -ack_ptr.cVal[0] = READ_VALUE(TX_ACK_PTR(s) + SA_OFFSET(3)); -enable(); - -// Suppress compiler errors that k is not used -k = k; - -// Calculate send free buffer size -if (wr_ptr.lVal >= ack_ptr.lVal) - size = (u_int)(SSIZE[s] - (wr_ptr.lVal - ack_ptr.lVal)); -else - size = (u_int)(SSIZE[s] - (0 - ack_ptr.lVal + wr_ptr.lVal)); - -// Recalulate after some delay because of error in pointer calculation -if (size > SSIZE[s]) - { - if (select(s, SEL_CONTROL) != SOCK_ESTABLISHED) - return -1; - delay_ms(1); - goto S_START; - } - -// Wait when previous sending has not finished yet and there's no free buffer -if (size == 0) - { - if (select(s, SEL_CONTROL) != SOCK_ESTABLISHED) - return -1; - - delay_ms(1); - goto S_START; - } -else if (size < len) - { - len = size; - } - -// Calculate pointer to data copy -offset = (UINT)(wr_ptr.lVal & SMASK[s]); - -// copy data -write_data(s, buf, offset, len); - -while (READ_VALUE(COMMAND(s)) & CSEND) - { - // Confirm previous send command - if (select(s, SEL_CONTROL) != SOCK_ESTABLISHED) - return -1; - } - -// update tx_wr_ptr -wr_ptr.lVal = wr_ptr.lVal + len; -WRITE_VALUE(TX_WR_PTR(s), wr_ptr.cVal[3]); -WRITE_VALUE(TX_WR_PTR(s) + SA_OFFSET(1), wr_ptr.cVal[2]); -WRITE_VALUE(TX_WR_PTR(s) + SA_OFFSET(2), wr_ptr.cVal[1]); -WRITE_VALUE(TX_WR_PTR(s) + SA_OFFSET(3), wr_ptr.cVal[0]); - -delay0(1); - -// SEND -WRITE_VALUE(COMMAND(s), CSEND); - -return(len); -} - -/* -**************************************************************************************************** -* TCP data receiving function. -* -* Description : This function is to clear out any received TCP data. -* Arguments : s - channel number -* Returns : None -* Note : API Fcuntion -**************************************************************************************************** -*/ -void recv_clear(SOCKET s) -{ -u_char k; -u_int size; -union un_l2cval wr_ptr, rd_ptr; - -disable(); -k = READ_VALUE(SHADOW_RXWR_PTR(s)); -WINDOW_RESTORE_BASE; // Needed whenever we touch a shadow ptr; different window. -delay0(2); -wr_ptr.cVal[3] = READ_VALUE(RX_WR_PTR(s)); -wr_ptr.cVal[2] = READ_VALUE(RX_WR_PTR(s) + SA_OFFSET(1)); -wr_ptr.cVal[1] = READ_VALUE(RX_WR_PTR(s) + SA_OFFSET(2)); -wr_ptr.cVal[0] = READ_VALUE(RX_WR_PTR(s) + SA_OFFSET(3)); - -k = READ_VALUE(SHADOW_RXRD_PTR(s)); -WINDOW_RESTORE_BASE; // Needed whenever we touch a shadow ptr; different window. -delay0(2); -rd_ptr.cVal[3] = READ_VALUE(RX_RD_PTR(s)); -rd_ptr.cVal[2] = READ_VALUE(RX_RD_PTR(s) + SA_OFFSET(1)); -rd_ptr.cVal[1] = READ_VALUE(RX_RD_PTR(s) + SA_OFFSET(2)); -rd_ptr.cVal[0] = READ_VALUE(RX_RD_PTR(s) + SA_OFFSET(3)); -enable(); - -// Suppress compiler errors that k is not used -k = k; - -// calculate received data size -if (wr_ptr.lVal >= rd_ptr.lVal) - size = (u_int)(wr_ptr.lVal - rd_ptr.lVal); -else - size = (u_int)(0 - rd_ptr.lVal + wr_ptr.lVal); - -// Update rx_rd_ptr -rd_ptr.lVal += size; -WRITE_VALUE(RX_RD_PTR(s), rd_ptr.cVal[3]); -WRITE_VALUE(RX_RD_PTR(s) + SA_OFFSET(1), rd_ptr.cVal[2]); -WRITE_VALUE(RX_RD_PTR(s) + SA_OFFSET(2), rd_ptr.cVal[1]); -WRITE_VALUE(RX_RD_PTR(s) + SA_OFFSET(3), rd_ptr.cVal[0]); - -// RECV - WRITE_VALUE(COMMAND(s), CRECV); -} - -/* -**************************************************************************************************** -* TCP data receiving function. -* -* Description : This function is for receiving TCP data. -* The recv() function is an application I/F function. It will read up to len chars if there are - enough characters in the buffer, otherwise will onl read the number of characters availiable -* Arguments : s - channel number -* buf - Pointer where the data to be received is copied -* len - Size of the data to be received -* Returns : Succeeded: received data size, Failed: -1 -* Note : API Fcuntion -**************************************************************************************************** -*/ -int recv(SOCKET s, u_char far * buf, u_int len) -{ -u_char k; -u_int size; -union un_l2cval wr_ptr, rd_ptr; -unsigned int offset; - -// If out length is 0, then we do not need to do anything -if (len <= 0) - return (0); - -disable(); -k = READ_VALUE(SHADOW_RXWR_PTR(s)); -WINDOW_RESTORE_BASE; // Needed whenever we touch a shadow ptr; different window. -delay0(2); -wr_ptr.cVal[3] = READ_VALUE(RX_WR_PTR(s)); -wr_ptr.cVal[2] = READ_VALUE(RX_WR_PTR(s) + SA_OFFSET(1)); -wr_ptr.cVal[1] = READ_VALUE(RX_WR_PTR(s) + SA_OFFSET(2)); -wr_ptr.cVal[0] = READ_VALUE(RX_WR_PTR(s) + SA_OFFSET(3)); - -k = READ_VALUE(SHADOW_RXRD_PTR(s)); -WINDOW_RESTORE_BASE; // Needed whenever we touch a shadow ptr; different window. -delay0(2); -rd_ptr.cVal[3] = READ_VALUE(RX_RD_PTR(s)); -rd_ptr.cVal[2] = READ_VALUE(RX_RD_PTR(s) + SA_OFFSET(1)); -rd_ptr.cVal[1] = READ_VALUE(RX_RD_PTR(s) + SA_OFFSET(2)); -rd_ptr.cVal[0] = READ_VALUE(RX_RD_PTR(s) + SA_OFFSET(3)); -enable(); - -// Suppress compiler errors that k is not used -k = k; - -// calculate IIM7010A received data size -if (wr_ptr.lVal == rd_ptr.lVal) - return(0); -else if (wr_ptr.lVal >= rd_ptr.lVal) - size = (u_int)(wr_ptr.lVal - rd_ptr.lVal); -else - size = (u_int)(0 - rd_ptr.lVal + wr_ptr.lVal); - -// Make sure we do not try to read more characters than what is availiable in the IIM7010 buffer -if (size < len) - len = size; - -// Calculate pointer to be copied received data -offset = ((UINT)(rd_ptr.lVal & RMASK[s])); - -// Copy received data -size = read_data(s, offset, buf, len); - -// Update rx_rd_ptr -rd_ptr.lVal += size; -WRITE_VALUE(RX_RD_PTR(s), rd_ptr.cVal[3]); -WRITE_VALUE(RX_RD_PTR(s) + SA_OFFSET(1), rd_ptr.cVal[2]); -WRITE_VALUE(RX_RD_PTR(s) + SA_OFFSET(2), rd_ptr.cVal[1]); -WRITE_VALUE(RX_RD_PTR(s) + SA_OFFSET(3), rd_ptr.cVal[0]); - -// RECV - WRITE_VALUE(COMMAND(s), CRECV); -return(size); -} - - -/* -**************************************************************************************************** -* UDP data sending function. -* -* Description : Composed of the sendto()and sendto_in() functions. -* The send() function is an application I/F function. -* It continues to call the send_in() function to complete the sending of the data up to the -* size of the data to be sent -* when the application is called.Unlike TCP transmission, it designates the destination address -* and the port. -* Arguments : s - channel port -* buf - Pointer pointing data to send -* len - data size to send -* addr - destination IP address to send data -* port - destination port number to send data -* Returns : Sent data size -* Note : API Function -**************************************************************************************************** -*/ -u_int sendto(SOCKET s, u_char far * buf, u_int len, u_char * addr, u_int port) -{ -//char val; -u_int ptr, size; - -// Wait until previous send commnad has completed. -while(READ_VALUE(COMMAND(s)) & CSEND) - { - if(select(s, SEL_CONTROL) == SOCK_CLOSED) - return -1; // Error. - } - -// Designate destination port number. -if (port != 0) - { - WRITE_VALUE(DST_PORT_PTR(s), (u_char)((port & 0xff00) >> 8)); - WRITE_VALUE(DST_PORT_PTR(s) + SA_OFFSET(1), (u_char)(port & 0x00ff)); - } - -// Designate destination IP address -WRITE_VALUE(DST_IP_PTR(s), addr[0]); -WRITE_VALUE(DST_IP_PTR(s) + SA_OFFSET(1), addr[1]); -WRITE_VALUE(DST_IP_PTR(s) + SA_OFFSET(2), addr[2]); -WRITE_VALUE(DST_IP_PTR(s) + SA_OFFSET(3), addr[3]); - -if (len <= 0) - return (0); -else - { - ptr = 0; - do - { - size = sendto_in(s, buf + ptr, len); - len = len - size; - ptr += size; - } while ( len > 0); - } -return ptr; -} - -/* -**************************************************************************************************** -* UDP data sending function. -* -* Description : An internal function that is the same as the send_in() function of the TCP. -* Arguments : s - Channel number -* buf - Pointer indicating the data to send -* len - data size to send -* Returns : Sent data size -* Note : Internal Function -**************************************************************************************************** -*/ -u_int sendto_in(SOCKET s, u_char far * buf, u_int len) -{ -u_char k; -u_int size; -union un_l2cval wr_ptr, rd_ptr; -unsigned int offset; - -S2_START: -disable(); -k = READ_VALUE(SHADOW_TXWR_PTR(s)); -WINDOW_RESTORE_BASE; // Needed whenever we touch a shadow ptr; different window. -delay0(2); -wr_ptr.cVal[3] = READ_VALUE(TX_WR_PTR(s)); -wr_ptr.cVal[2] = READ_VALUE(TX_WR_PTR(s) + SA_OFFSET(1)); -wr_ptr.cVal[1] = READ_VALUE(TX_WR_PTR(s) + SA_OFFSET(2)); -wr_ptr.cVal[0] = READ_VALUE(TX_WR_PTR(s) + SA_OFFSET(3)); - -k = READ_VALUE(SHADOW_TXRD_PTR(s)); -WINDOW_RESTORE_BASE; // Needed whenever we touch a shadow ptr; different window. -delay0(2); -rd_ptr.cVal[3] = READ_VALUE(TX_RD_PTR(s)); -rd_ptr.cVal[2] = READ_VALUE(TX_RD_PTR(s) + SA_OFFSET(1)); -rd_ptr.cVal[1] = READ_VALUE(TX_RD_PTR(s) + SA_OFFSET(2)); -rd_ptr.cVal[0] = READ_VALUE(TX_RD_PTR(s) + SA_OFFSET(3)); -enable(); - -// Suppress compiler errors that k is not used -k = k; - -// Calculate free buffer size to send -if (wr_ptr.lVal >= rd_ptr.lVal) - size = (u_int)(SSIZE[s] - (wr_ptr.lVal - rd_ptr.lVal)); -else - size = (u_int)(SSIZE[s] - (0 - rd_ptr.lVal + wr_ptr.lVal)); - -// Recalulate after some delay because of error in pointer caluation -if (size > SSIZE[s]) - { - delay_ms(1); - goto S2_START; - } - -// Wait when previous sending has not finished yet and there's no free buffer -if (size == 0) - { - delay_ms(1); - goto S2_START; - - } -else if (size < len) - { - len = size; - } - -// Calculate pointer to copy data pointer -offset =(UINT)(wr_ptr.lVal & SMASK[s]); - -// copy data -write_data(s, buf, offset, len); - -// Confirm previous send command -while (READ_VALUE(COMMAND(s)) & CSEND) - { - if(select(s, SEL_CONTROL)==SOCK_CLOSED) - return -1; // Error - } - -// update tx_wr_ptr -wr_ptr.lVal = wr_ptr.lVal + len; -WRITE_VALUE(TX_WR_PTR(s), wr_ptr.cVal[3]); -WRITE_VALUE(TX_WR_PTR(s) + SA_OFFSET(1), wr_ptr.cVal[2]); -WRITE_VALUE(TX_WR_PTR(s) + SA_OFFSET(2), wr_ptr.cVal[1]); -WRITE_VALUE(TX_WR_PTR(s) + SA_OFFSET(3), wr_ptr.cVal[0]); - -delay0(1); - -// SEND -WRITE_VALUE(COMMAND(s), CSEND); - -return(len); -} - -/* -**************************************************************************************************** -* UDP data receiving function. -* -* Description : Function for receiving UDP and IP layer RAW mode data, and handling the data header. -* Arguments : s - channel number -* buf - Pointer where the data to be received is copied -* len - Size of the data to be received -* addr - Peer IP address for receiving -* port - Peer port number for receiving -* Returns : Received data size -* Note : API Function -**************************************************************************************************** -*/ -u_int recvfrom(SOCKET s, u_char far *buf, u_int len, u_char *addr, u_int *port) -{ -struct _UDPHeader // When receiving UDP data, header added by W3100A - { - union - { - struct - { - u_int size; - u_char addr[4]; - u_int port; - } header; - u_char stream[8]; - } u; - } UDPHeader; - -u_int ret; -union un_l2cval wr_ptr, rd_ptr; -u_long size; -u_char k; -unsigned int offset; - -if(select(s,SEL_CONTROL)==SOCK_CLOSED) - return -1; - -disable(); -k = READ_VALUE(SHADOW_RXWR_PTR(s)); -WINDOW_RESTORE_BASE; // Needed whenever we touch a shadow ptr; different window. -delay0(2); -wr_ptr.cVal[3] = READ_VALUE(RX_WR_PTR(s)); -wr_ptr.cVal[2] = READ_VALUE(RX_WR_PTR(s) + SA_OFFSET(1)); -wr_ptr.cVal[1] = READ_VALUE(RX_WR_PTR(s) + SA_OFFSET(2)); -wr_ptr.cVal[0] = READ_VALUE(RX_WR_PTR(s) + SA_OFFSET(3)); - -k = READ_VALUE(SHADOW_RXRD_PTR(s)); -WINDOW_RESTORE_BASE; // Needed whenever we touch a shadow ptr; different window. -delay0(2); -rd_ptr.cVal[3] = READ_VALUE(RX_RD_PTR(s)); -rd_ptr.cVal[2] = READ_VALUE(RX_RD_PTR(s) + SA_OFFSET(1)); -rd_ptr.cVal[1] = READ_VALUE(RX_RD_PTR(s) + SA_OFFSET(2)); -rd_ptr.cVal[0] = READ_VALUE(RX_RD_PTR(s) + SA_OFFSET(3)); -enable(); - -// Suppress compiler errors that k is not used -k = k; - -// Calculate received data size -if (len <= 0) - return (0); -else if (wr_ptr.lVal >= rd_ptr.lVal) - size = wr_ptr.lVal - rd_ptr.lVal; -else - size = 0 - rd_ptr.lVal + wr_ptr.lVal; - -if (size == 0) - return 0; - - // Calulate received data pointer -offset = ((UINT)(rd_ptr.lVal & RMASK[s])); - -// When UDP data -if (( READ_VALUE(OPT_PROTOCOL(s)) & 0x07) == SOCK_DGRAM) - { - // Copy W3100A UDP header - read_data(s, offset, UDPHeader.u.stream, 8); - - // Read UDP Packet size - size = UDPHeader.u.stream[0]; - size = (size << 8) + UDPHeader.u.stream[1]; - - // Read IP address of the peer - addr[0] = UDPHeader.u.header.addr[0]; - addr[1] = UDPHeader.u.header.addr[1]; - addr[2] = UDPHeader.u.header.addr[2]; - addr[3] = UDPHeader.u.header.addr[3]; - - // Read Port number of the peer - *port = UDPHeader.u.stream[6]; - *port = (*port << 8) + UDPHeader.u.stream[7]; - - // Increase read pointer by 8, because already read as UDP header size - rd_ptr.lVal += 8; - - // Calculate UDP data copy pointer - offset = ((UINT)(rd_ptr.lVal & RMASK[s])); - - // Calculate data size of current UDP Packet from UDP header - size = size - 8; - - // Copy one UDP data packet to user-specific buffer - ret = read_data(s, offset, buf, (u_int)size); - - // Increase read pointer by UDP packet data size - rd_ptr.lVal += ret; - } -else if ((READ_VALUE(OPT_PROTOCOL(s)) & 0x07) == SOCK_IPL_RAW) // When IP layer RAW mode data - { - // Copy W3100A IP Raw header - read_data(s, offset, UDPHeader.u.stream, 6); - - // Read IP layer RAW Packet size - size = UDPHeader.u.stream[0]; - size = (size << 8) + UDPHeader.u.stream[1]; - - // Read IP address of the peer - addr[0] = UDPHeader.u.header.addr[0]; - addr[1] = UDPHeader.u.header.addr[1]; - addr[2] = UDPHeader.u.header.addr[2]; - addr[3] = UDPHeader.u.header.addr[3]; - - // Increase read pointer by 6, because already read as IP RAW header size - rd_ptr.lVal += 6; - - // Calculate IP layer raw mode data pointer - offset = ((UINT)(rd_ptr.lVal & RMASK[s])); - - // Copy one IP Raw data packet to user-specific buffer - ret = read_data(s, offset, buf, (u_int)size); - rd_ptr.lVal = rd_ptr.lVal + (ret - 4); - } - - // Update rx_rd_ptr - WRITE_VALUE(RX_RD_PTR(s), rd_ptr.cVal[3]); - WRITE_VALUE(RX_RD_PTR(s) + SA_OFFSET(1), rd_ptr.cVal[2]); - WRITE_VALUE(RX_RD_PTR(s) + SA_OFFSET(2), rd_ptr.cVal[1]); - WRITE_VALUE(RX_RD_PTR(s) + SA_OFFSET(3), rd_ptr.cVal[0]); - - // RECV - WRITE_VALUE(COMMAND(s), CRECV); - -// Real received size return -return(ret); -} - -/* -**************************************************************************************************** -* Channel closing function. -* -* Description : Function for closing the connection of the designated channel. -* Arguments : s - channel number -* Returns : None -* Note : API Function -**************************************************************************************************** -*/ -void close(SOCKET s) -{ -u_int len; -short sAttempts = 0; - -I_STATUS[s] = 0; - -if (select(s, SEL_CONTROL) == SOCK_CLOSED) - return; // Already closed - -// When closing, if there's data which have not processed, Insert some source codes to handle this -// Or before application call close(), handle those data first and call close() later. - -len = select(s, SEL_SEND); -if (len == SSIZE[s]) - { - // CLOSE - WRITE_VALUE(COMMAND(s), CCLOSE); - // TODO: The 'SCLOSED' status value is only set briefly as part of the close, - // and will otherwise quickly return to normal. That means your code might - // become 'stuck' at this point even if the packet has closed normally. - // Rather than a while() call, it might be preferred to time out on this - // close check and return to the application after some time. - while(!(I_STATUS[s] & SCLOSED)) - { - sAttempts++; - if( sAttempts > 10 ) - { - break; - } - I2CHIP_POLL_ISR(in4_isr_i2chip); - } - } -} - -u_char tx_empty(SOCKET s) -{ - return (select(s, SEL_SEND) == SSIZE[s]); -} - -/* -**************************************************************************************************** -* Channel closing function. -* -* Description : Function for closing the connection of the designated channel. -* Arguments : s - channel number -* Returns : None -* Note : API Function -**************************************************************************************************** -*/ -char reset_sock(SOCKET s) -{ -u_char c; - -c = 1 << s; - -// RESET -WRITE_VALUE(RESETSOCK, c); -return (1); -} - -/* -**************************************************************************************************** -* Function handling the channel socket information. -* -* Description : Return socket information of designated channel -* Arguments : s - channel number -* func - SEL_CONTROL(0x00) -> return socket status -* SEL_SEND(0x01) -> return free transmit buffer size -* SEL_RECV(0x02) -> return received data size -* Returns : socket status or free transmit buffer size or received data size -* Note : API Function -**************************************************************************************************** -*/ -u_int select(SOCKET s, u_char func) -{ -u_int val; -union un_l2cval rd_ptr, wr_ptr, ack_ptr; -u_char k; - -switch (func) - { - // socket status information - case SEL_CONTROL : - val = READ_VALUE(SOCK_STATUS(s)); - break; - - // Calculate send free buffer size - case SEL_SEND : - disable(); - k = READ_VALUE(SHADOW_TXWR_PTR(s)); - WINDOW_RESTORE_BASE; // Needed whenever we touch a shadow ptr; different window. - delay0(2); - wr_ptr.cVal[3] = READ_VALUE(TX_WR_PTR(s)); - wr_ptr.cVal[2] = READ_VALUE(TX_WR_PTR(s) + SA_OFFSET(1)); - wr_ptr.cVal[1] = READ_VALUE(TX_WR_PTR(s) + SA_OFFSET(2)); - wr_ptr.cVal[0] = READ_VALUE(TX_WR_PTR(s) + SA_OFFSET(3)); - - if (( READ_VALUE(OPT_PROTOCOL(s)) & 0x07) == SOCK_STREAM) // TCP - { - k = READ_VALUE(SHADOW_TXACK_PTR(s)); - WINDOW_RESTORE_BASE; // Needed whenever we touch a shadow ptr; different window. - delay0(2); - ack_ptr.cVal[3] = READ_VALUE(TX_ACK_PTR(s)); - ack_ptr.cVal[2] = READ_VALUE(TX_ACK_PTR(s) + SA_OFFSET(1)); - ack_ptr.cVal[1] = READ_VALUE(TX_ACK_PTR(s) + SA_OFFSET(2)); - ack_ptr.cVal[0] = READ_VALUE(TX_ACK_PTR(s) + SA_OFFSET(3)); - enable(); - - if (wr_ptr.lVal >= ack_ptr.lVal) - val = (u_int)(SSIZE[s] - (wr_ptr.lVal - ack_ptr.lVal)); - else - val = (u_int)(SSIZE[s] - (0 - ack_ptr.lVal + wr_ptr.lVal)); - } - else // UDP, IP RAW ... (except TCP) - { - k = READ_VALUE(SHADOW_TXRD_PTR(s)); - WINDOW_RESTORE_BASE; // Needed whenever we touch a shadow ptr; different window. - delay0(2); - rd_ptr.cVal[3] = READ_VALUE(TX_RD_PTR(s)); - rd_ptr.cVal[2] = READ_VALUE(TX_RD_PTR(s) + SA_OFFSET(1)); - rd_ptr.cVal[1] = READ_VALUE(TX_RD_PTR(s) + SA_OFFSET(2)); - rd_ptr.cVal[0] = READ_VALUE(TX_RD_PTR(s) + SA_OFFSET(3)); - enable(); - - if (wr_ptr.lVal >= rd_ptr.lVal) - val = (u_int)(SSIZE[s] - (wr_ptr.lVal - rd_ptr.lVal)); - else - val = (u_int)(SSIZE[s] - (0 - rd_ptr.lVal + wr_ptr.lVal)); - } - break; - - // Calculate received data size - case SEL_RECV : - disable(); - k = READ_VALUE(SHADOW_RXWR_PTR(s)); - WINDOW_RESTORE_BASE; // Needed whenever we touch a shadow ptr; different window. - delay0(2); - wr_ptr.cVal[3] = READ_VALUE(RX_WR_PTR(s)); - wr_ptr.cVal[2] = READ_VALUE(RX_WR_PTR(s) + SA_OFFSET(1)); - wr_ptr.cVal[1] = READ_VALUE(RX_WR_PTR(s) + SA_OFFSET(2)); - wr_ptr.cVal[0] = READ_VALUE(RX_WR_PTR(s) + SA_OFFSET(3)); - - k = READ_VALUE(SHADOW_RXRD_PTR(s)); - WINDOW_RESTORE_BASE; // Needed whenever we touch a shadow ptr; different window. - delay0(2); - rd_ptr.cVal[3] = READ_VALUE(RX_RD_PTR(s)); - rd_ptr.cVal[2] = READ_VALUE(RX_RD_PTR(s) + SA_OFFSET(1)); - rd_ptr.cVal[1] = READ_VALUE(RX_RD_PTR(s) + SA_OFFSET(2)); - rd_ptr.cVal[0] = READ_VALUE(RX_RD_PTR(s) + SA_OFFSET(3)); - enable(); - - if (wr_ptr.lVal == rd_ptr.lVal) - val = 0; - else if (wr_ptr.lVal > rd_ptr.lVal) - val = (u_int)(wr_ptr.lVal - rd_ptr.lVal); - else - val = (u_int)(0 - rd_ptr.lVal + wr_ptr.lVal); - break; - - default : - val = -1; - break; - } -// Suppress compiler errors that k is not used -k = k; -return(val); -} - -// -// unsigned char dma_read_i2chip (unsigned int i2_segm, unsigned int i2_offs, -// unsigned int cnt, unsigned int des_segm, unsigned int des_offs); -// Using DMA0 to read data from i2chip buffer into destination SRAM. -// where: -// unsigned int cnt = number of sectors, 512-byte per sector -// unsigned int des_segm = segment of destination SRAM data memory -// unsigned int des_offs = offset of destination SRAM data memory -// unsigned int i2_segm = segment of i2chip buffer mapped in memory -// unsigned int i2_offs = offset of i2chip buffer mapped in memory -// return DMA counter value -// -unsigned int dma_read_i2chip(u_char far* i2_src, u_char far* des, u_int cnt) -{ - u_int des_segm, des_offs; - u_int i2_segm, i2_offs; - u_long temp; - - temp = ((long)FP_SEG(des) << 4) + ((long)FP_OFF(des)); - des_segm = (u_int)(temp >> 16); - des_offs = (u_int)(temp & 0xffff); - - temp = ((long)FP_SEG(i2_src) << 4) + ((long)FP_OFF(i2_src)); - i2_segm = (u_int)(temp >> 16); - i2_offs = (u_int)(temp & 0xffff); - - outport(0xffc6, des_segm); /* D0DSTH destination SRAM segment */ - outport(0xffc4, des_offs); /* D0DSTL destination SRAM offset */ - outport(0xffc2, i2_segm); /* D0SRCH=SP0RD */ - outport(0xffc0, i2_offs); /* D0SRCL=SP0RD */ - outport(0xffc8, cnt); // D0TC counter - outport(0xfff8,0x0504); // PLLCON, 0203=10M,050f=40M, 051f=80MHz -// DMA0 mem-mem, 16-bit, unsync, Start moving data line below - outport(0xffca, 0xb60e); /* D0CON 1011 0110 0000 1111 */ -// outport(0xffca, 0xb42e); // 1011 0100 0010 1110 - while( inport(0xffc8) ); /* D0TC counter=0, DMA complete */ - outport(0xfff8,0x051f); // PLLCON, 0203=10M,050f=40M, 051f=80MHz -return( inport(0xffc8) ); // counter -} - -// -// unsigned int dma_write_i2chip (unsigned int src_segm, unsigned int src_offs, -// unsigned int cnt, unsigned int i2_segm, unsigned int i2_offs); -// Using DMA0 to write data from memory into i2chip. -// where: -// unsigned int cnt = number of 16-bit DMA transfers -// unsigned int src_segm = segment of the source SRAM data memory -// unsigned int src_offs = offset of the source SRAM data memory -// unsigned int i2_segm = segment of i2chip buffer mapped in memory -// unsigned int i2_offs = offset of i2chip buffer mapped in memory -// return DMA counter value -// -unsigned int dma_write_i2chip(u_char far* src, u_char far* i2_dest, u_int cnt) -{ - u_int src_segm, src_offs; - u_int i2_segm, i2_offs; - u_long temp; - - temp = (FP_SEG(src) << 4) + (FP_OFF(src)); - src_segm = (u_int)(temp >> 4); - src_offs = (u_int)(temp & 0xffff); - - temp = (FP_SEG(i2_dest) << 4) + (FP_OFF(i2_dest)); - i2_segm = (u_int)(temp >> 4); - i2_offs = (u_int)(temp & 0xffff); - - outport(0xffc8, cnt); // D0TC counter - outport(0xffc6, i2_segm); // D0DSTH=i2chip buffer segment - outport(0xffc4, i2_offs); // D0DSTL=i2chip buffer offset - outport(0xffc2, src_segm); /* D0SRCH=SP0RD */ - outport(0xffc0, src_offs); /* D0SRCL=SP0RD */ -// outport(0xfff8,0x050f); // PLLCON, 0203=10M,050f=40M, 051f=80MHz -// DMA0 mem-mem, 16-bit, unsync, Start moving data line below - outport(0xffca, 0xb60f); /* D0CON 1011 0110 0000 1111 */ - while( inport(0xffc8) ); /* D0TC counter=0, DMA complete */ -// outport(0xfff8,0x051f); // PLLCON, 0203=10M,050f=40M, 051f=80MHz - -return( inport(0xffc8) ); // counter -} - -/* -**************************************************************************************************** -* Copies the receive buffer data of the W3100A to the system buffer. -* -* Description : Copies the receive buffer data of the W3100A to the system buffer. -* It is called from the recv()or recvfrom() function. -* Arguments : s - channel number -* src - receive buffer pointer of W3100A -* dst - system buffer pointer -* len - data size to copy -* Returns : copied data size -* Note : Internal Function -**************************************************************************************************** -*/ -u_int read_data(SOCKET s, u_int offset, u_char far * dst, u_int len) -{ - u_int i, size, size1; - u_char far* src = (u_char far*)(MK_FP_WINDOW(RECV_DATA_BUF, - RBUFBASEADDRESS[s] + offset)); -// src = (u_char far*)(MK_FP_WINDOW(RECV_DATA_BUF, -// 0)); - - if (len == 0) - { - WINDOW_RESTORE_BASE; // Needed whenever we do a call to MK_FP_WINDOW. - return 0; - } - - if ((offset + len) > RSIZE[s]) - { - size = (u_int)(RSIZE[s] - offset); - - if (size > TERN_RDMA_THRES) - { - dma_read_i2chip(src, dst, size); - } - else - { - for (i = 0; i < size; i++) - { - *dst++ = READ_VALUE(src); - WINDOW_PTR_INC(src); - - } - } - - size1 = len - size; - src = (u_char far *)(MK_FP_WINDOW(RECV_DATA_BUF, (RBUFBASEADDRESS[s]))); - - if (size1 > TERN_RDMA_THRES) - { - dma_read_i2chip(src, dst, size); - } - else - { - for (i = 0; i < size1; i++) - { - *dst++ = READ_VALUE(src); - WINDOW_PTR_INC(src); - } - } - } - else - { - if (len > TERN_RDMA_THRES) - { - dma_read_i2chip(src, dst, size); - } - else - { - for (i = 0; i < len; i++) - { - *dst++ = READ_VALUE(src); - WINDOW_PTR_INC(src); - } - } - } - WINDOW_RESTORE_BASE; // Needed whenever we do a call to MK_FP_WINDOW. - return len; -} - - -/* -**************************************************************************************************** -* Copies the system buffer data to the transmit buffer of the W3100A. -* -* Description : Copies the system buffer data to the transmit buffer of the W3100A. -* It is called from the send_in()or sendto_in() function. -* Arguments : s - channel number -* src - system buffer pointer -* dst - send buffer pointer of W3100A -* len - data size to copy -* Returns : copied data size -* Note : Internal Function -**************************************************************************************************** -*/ -u_int write_data(SOCKET s, u_char far * src, u_int offset, u_int len) -{ - u_int i, size, size1; - u_char far* dst = (u_char far*)MK_FP_WINDOW(SEND_DATA_BUF, - SBUFBASEADDRESS[s] + offset); - - if (len == 0) - { - WINDOW_RESTORE_BASE; // Needed whenever we do a call to MK_FP_WINDOW. - return 0; - } - - if ((offset + len) > SSIZE[s]) - { - size = (u_int)(SSIZE[s] - offset); - - for (i = 0; i < size; i++) - { - WRITE_VALUE(dst, *src++); - WINDOW_PTR_INC(dst); - } - - size1 = len - size; - dst = (u_char far *)(MK_FP_WINDOW(SEND_DATA_BUF, (SBUFBASEADDRESS[s]))); - - for (i = 0; i < size1; i++) - { - WRITE_VALUE(dst, *src++); - WINDOW_PTR_INC(dst); - } - } - else - { - for (i = 0; i < len; i++) - { - WRITE_VALUE(dst, *src++); - WINDOW_PTR_INC(dst); - } - } - WINDOW_RESTORE_BASE; // Needed whenever we do a call to MK_FP_WINDOW. - return len; -} - - - diff --git a/Demo/dsPIC_MPLAB/FreeRTOSConfig.h b/Demo/dsPIC_MPLAB/FreeRTOSConfig.h deleted file mode 100644 index 8df3ea807..000000000 --- a/Demo/dsPIC_MPLAB/FreeRTOSConfig.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -#include - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 1 -#define configUSE_TICK_HOOK 0 -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 25000000 ) /* Fosc / 2 */ -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 ) -#define configMINIMAL_STACK_SIZE ( 105 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) 5120 ) -#define configMAX_TASK_NAME_LEN ( 4 ) -#define configUSE_TRACE_FACILITY 0 -#define configUSE_16_BIT_TICKS 1 -#define configIDLE_SHOULD_YIELD 1 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 1 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 0 -#define INCLUDE_vTaskDelete 0 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/dsPIC_MPLAB/ParTest/ParTest.c b/Demo/dsPIC_MPLAB/ParTest/ParTest.c deleted file mode 100644 index 9f25cf820..000000000 --- a/Demo/dsPIC_MPLAB/ParTest/ParTest.c +++ /dev/null @@ -1,113 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* Scheduler includes. */ -#include "FreeRTOS.h" - -/* Demo app includes. */ -#include "partest.h" - -#define ptOUTPUT 0 -#define ptALL_OFF 0 - -unsigned portBASE_TYPE uxOutput; - -/*----------------------------------------------------------- - * Simple parallel port IO routines. - *-----------------------------------------------------------*/ - -void vParTestInitialise( void ) -{ - /* The explorer 16 board has LED's on port A. All bits are set as output - so PORTA is read-modified-written directly. Two pins have change - notification pullups that need disabling. */ - CNPU2bits.CN22PUE = 0; - CNPU2bits.CN23PUE = 0; - TRISA = ptOUTPUT; - PORTA = ptALL_OFF; - uxOutput = ptALL_OFF; -} -/*-----------------------------------------------------------*/ - -void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) -{ -unsigned portBASE_TYPE uxLEDBit; - - /* Which port A bit is being modified? */ - uxLEDBit = 1 << uxLED; - - if( xValue ) - { - /* Turn the LED on. */ - portENTER_CRITICAL(); - { - uxOutput |= uxLEDBit; - PORTA = uxOutput; - } - portEXIT_CRITICAL(); - } - else - { - /* Turn the LED off. */ - portENTER_CRITICAL(); - { - uxOutput &= ~uxLEDBit; - PORTA = uxOutput; - } - portEXIT_CRITICAL(); - } -} -/*-----------------------------------------------------------*/ - -void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) -{ -unsigned portBASE_TYPE uxLEDBit; - - uxLEDBit = 1 << uxLED; - portENTER_CRITICAL(); - { - /* If the LED is already on - turn it off. If the LED is already - off, turn it on. */ - if( uxOutput & uxLEDBit ) - { - uxOutput &= ~uxLEDBit; - PORTA = uxOutput; - } - else - { - uxOutput |= uxLEDBit; - PORTA = uxOutput; - } - } - portEXIT_CRITICAL(); -} - diff --git a/Demo/dsPIC_MPLAB/RTOSDemo.mcs b/Demo/dsPIC_MPLAB/RTOSDemo.mcs deleted file mode 100644 index ad85eb9d5..000000000 --- a/Demo/dsPIC_MPLAB/RTOSDemo.mcs +++ /dev/null @@ -1,3 +0,0 @@ -[Header] -MagicCookie={0b13fe8c-dfe0-40eb-8900-6712719559a7} -Version=1.0 diff --git a/Demo/dsPIC_MPLAB/RTOSDemo.mcw b/Demo/dsPIC_MPLAB/RTOSDemo.mcw deleted file mode 100644 index a85e0aebd..000000000 Binary files a/Demo/dsPIC_MPLAB/RTOSDemo.mcw and /dev/null differ diff --git a/Demo/dsPIC_MPLAB/RTOSDemo_dsPIC.mcp b/Demo/dsPIC_MPLAB/RTOSDemo_dsPIC.mcp deleted file mode 100644 index 62952f51b..000000000 --- a/Demo/dsPIC_MPLAB/RTOSDemo_dsPIC.mcp +++ /dev/null @@ -1,67 +0,0 @@ -[HEADER] -magic_cookie={66E99B07-E706-4689-9E80-9B2582898A13} -file_version=1.0 -[PATH_INFO] -dir_src= -dir_bin= -dir_tmp= -dir_sin= -dir_inc=.;C:\E\Dev\FreeRTOS\Demo\Common\include;C:\E\Dev\FreeRTOS\Demo\dsPIC_MPLAB;C:\E\Dev\FreeRTOS\source\include -dir_lib= -dir_lkr= -[CAT_FILTERS] -filter_src=*.s;*.c -filter_inc=*.h;*.inc -filter_obj=*.o -filter_lib=*.a -filter_lkr=*.gld -[OTHER_FILES] -file_000=no -file_001=no -file_002=no -file_003=no -file_004=no -file_005=no -file_006=no -file_007=no -file_008=no -file_009=no -file_010=no -file_011=no -file_012=no -file_013=no -file_014=no -file_015=no -file_016=no -file_017=no -file_018=no -file_019=no -[FILE_INFO] -file_000=main.c -file_001=..\..\source\list.c -file_002=..\..\source\queue.c -file_003=..\..\source\tasks.c -file_004=..\..\source\portable\MPLAB\PIC24_dsPIC\port.c -file_005=..\..\source\portable\MemMang\heap_1.c -file_006=..\Common\Minimal\BlockQ.c -file_007=..\..\source\croutine.c -file_008=..\Common\Minimal\crflash.c -file_009=ParTest\ParTest.c -file_010=..\Common\Minimal\blocktim.c -file_011=..\Common\Minimal\integer.c -file_012=..\Common\Minimal\comtest.c -file_013=serial\serial.c -file_014=..\..\source\include\semphr.h -file_015=..\..\source\include\task.h -file_016=..\..\source\include\croutine.h -file_017=..\..\source\include\queue.h -file_018=FreeRTOSConfig.h -file_019=p33FJ256GP710.gld -[SUITE_INFO] -suite_guid={479DDE59-4D56-455E-855E-FFF59A3DB57E} -suite_state= -[TOOL_SETTINGS] -TS{7D9C6ECE-785D-44CB-BA22-17BF2E119622}=-g -TS{25AC22BD-2378-4FDB-BFB6-7345A15512D3}=-g -Wall -DMPLAB_DSPIC_PORT -O2 -fomit-frame-pointer -fno-schedule-insns -fno-schedule-insns2 -TS{7DAC9A1D-4C45-45D6-B25A-D117C74E8F5A}=--defsym=__ICD2RAM=1 -Map="$(TARGETBASE).map" -o"$(TARGETBASE).$(TARGETSUFFIX)" -TS{509E5861-1E2A-483B-8B6B-CA8DB7F2DD78}= diff --git a/Demo/dsPIC_MPLAB/RTOSDemo_dsPIC.mcs b/Demo/dsPIC_MPLAB/RTOSDemo_dsPIC.mcs deleted file mode 100644 index ad85eb9d5..000000000 --- a/Demo/dsPIC_MPLAB/RTOSDemo_dsPIC.mcs +++ /dev/null @@ -1,3 +0,0 @@ -[Header] -MagicCookie={0b13fe8c-dfe0-40eb-8900-6712719559a7} -Version=1.0 diff --git a/Demo/dsPIC_MPLAB/main.c b/Demo/dsPIC_MPLAB/main.c deleted file mode 100644 index 6a5b8f493..000000000 --- a/Demo/dsPIC_MPLAB/main.c +++ /dev/null @@ -1,420 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * Creates all the demo application tasks, then starts the scheduler. The WEB - * documentation provides more details of the standard demo application tasks. - * In addition to the standard demo tasks, the following tasks are defined - * within this file: - * - * "Register test" tasks - These tasks first set all the general purpose - * registers to a known value (with each register containing a different value) - * then test each general purpose register to ensure it still contains the - * set value. There are two register test tasks, with different values being - * used by each. The register test tasks will be preempted frequently due to - * their low priority. Setting then testing the value of each register in this - * manner ensures the context of the tasks is being correctly saved and then - * restored as the preemptive context switches occur. An error is flagged - * should any register be found to contain an unexpected value. In addition - * the register test tasks maintain a count of the number of times they cycle, - * so an error can also be flagged should the cycle count not increment as - * expected (indicating the the tasks are not executing at all). - * - * "Check" task - This only executes every three seconds but has the highest - * priority so is guaranteed to get processor time. Its main function is to - * check that all the other tasks are still operational. Each task maintains a - * unique count that is incremented each time the task successfully completes - * its function. Should any error occur within such a task the count is - * permanently halted. The check task inspects the count of each task to - * ensure it has changed since the last time the check task executed. If all - * the count variables have changed all the tasks are still executing error - * free, and the check task toggles the onboard LED. Should any task contain - * an error at any time check task cycle frequency is increased to 500ms, - * causing the LED toggle rate to increase from 3 seconds to 500ms and in so - * doing providing visual feedback that an error has occurred. - * - */ - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "croutine.h" - -/* Demo application includes. */ -#include "BlockQ.h" -#include "crflash.h" -#include "blocktim.h" -#include "integer.h" -#include "comtest2.h" -#include "partest.h" - -/* Demo task priorities. */ -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainCOM_TEST_PRIORITY ( 2 ) - -/* Delay between check task cycles when an error has/has not been detected. */ -#define mainNO_ERROR_DELAY ( ( portTickType ) 3000 / portTICK_RATE_MS ) -#define mainERROR_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS ) - -/* The number of flash co-routines to create. */ -#define mainNUM_FLASH_COROUTINES ( 3 ) - -/* Baud rate used by the comtest tasks. */ -#define mainCOM_TEST_BAUD_RATE ( 19200 ) - -/* The LED used by the comtest tasks. mainCOM_TEST_LED + 1 is also used. -See the comtest.c file for more information. */ -#define mainCOM_TEST_LED ( 4 ) - -/* The LED used by the check task. */ -#define mainCHECK_LED ( 7 ) - -/*-----------------------------------------------------------*/ - -/* - * The register test tasks as described at the top of this file. - */ -void xRegisterTest1( void *pvParameters ); -void xRegisterTest2( void *pvParameters ); - -/* - * The check task as described at the top of this file. - */ -static void vCheckTask( void *pvParameters ); - -/* - * Setup the processor ready for the demo. - */ -static void prvSetupHardware( void ); - -/*-----------------------------------------------------------*/ - -/* Variables used to detect errors within the register test tasks. */ -static volatile unsigned portSHORT usTest1CycleCounter = 0, usTest2CycleCounter = 0; -static unsigned portSHORT usPreviousTest1Count = 0, usPreviousTest2Count = 0; - -/* Set to pdTRUE should an error be detected in any of the standard demo tasks -or tasks defined within this file. */ -static unsigned portSHORT usErrorDetected = pdFALSE; - -/*-----------------------------------------------------------*/ - -/* - * Create the demo tasks then start the scheduler. - */ -int main( void ) -{ - /* Configure any hardware required for this demo. */ - prvSetupHardware(); - - /* Create the standard demo tasks. */ - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - vStartIntegerMathTasks( tskIDLE_PRIORITY ); - vStartFlashCoRoutines( mainNUM_FLASH_COROUTINES ); - vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); - vCreateBlockTimeTasks(); - - /* Create the test tasks defined within this file. */ - xTaskCreate( xRegisterTest1, "Reg1", configMINIMAL_STACK_SIZE, ( void * ) &usTest1CycleCounter, tskIDLE_PRIORITY, NULL ); - xTaskCreate( xRegisterTest2, "Reg2", configMINIMAL_STACK_SIZE, ( void * ) &usTest2CycleCounter, tskIDLE_PRIORITY, NULL ); - xTaskCreate( vCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - - /* Finally start the scheduler. */ - vTaskStartScheduler(); - - /* Will only reach here if there is insufficient heap available to start - the scheduler. */ - return 0; -} -/*-----------------------------------------------------------*/ - -static void prvSetupHardware( void ) -{ - vParTestInitialise(); -} -/*-----------------------------------------------------------*/ - -static void vCheckTask( void *pvParameters ) -{ -portTickType xLastExecutionTime; - -/* Start with the no error delay. The long delay will cause the LED to flash -slowly. */ -portTickType xDelay = mainNO_ERROR_DELAY; - - /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() - works correctly. */ - xLastExecutionTime = xTaskGetTickCount(); - - for( ;; ) - { - /* Wait until it is time for the next cycle. */ - vTaskDelayUntil( &xLastExecutionTime, xDelay ); - - /* Has an error been found in any of the standard demo tasks? */ - - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - usErrorDetected = pdTRUE; - } - - if( xAreComTestTasksStillRunning() != pdTRUE ) - { - usErrorDetected = pdTRUE; - } - - if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) - { - usErrorDetected = pdTRUE; - } - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - usErrorDetected = pdTRUE; - } - - - /* Are the register test tasks still cycling? */ - - if( usTest1CycleCounter == usPreviousTest1Count ) - { - usErrorDetected = pdTRUE; - } - - if( usTest2CycleCounter == usPreviousTest2Count ) - { - usErrorDetected = pdTRUE; - } - - usPreviousTest2Count = usTest2CycleCounter; - usPreviousTest1Count = usTest1CycleCounter; - - - /* If an error has been detected in any task then the delay will be - reduced to increase the cycle rate of this task. This has the effect - of causing the LED to flash much faster giving a visual indication of - the error condition. */ - if( usErrorDetected != pdFALSE ) - { - xDelay = mainERROR_DELAY; - } - - /* Finally, toggle the LED before returning to delay to wait for the - next cycle. */ - vParTestToggleLED( mainCHECK_LED ); - } -} -/*-----------------------------------------------------------*/ - -void xRegisterTest1( void *pvParameters ) -{ -/* This static so as not to use the frame pointer. They are volatile -also to avoid it being stored in a register that we clobber during the test. */ -static unsigned portSHORT * volatile pusParameter; - - /* The variable incremented by this task is passed in as the parameter - even though it is defined within this file. This is just to test the - parameter passing mechanism. */ - pusParameter = pvParameters; - - for( ;; ) - { - /* Increment the variable to show this task is still cycling. */ - ( *pusParameter )++; - - /* Set the w registers to known values, then check that each register - contains the expected value. See the explanation at the top of this - file for more information. */ - asm volatile( "mov.w #0x0101, W0 \n" \ - "mov.w #0x0102, W1 \n" \ - "mov.w #0x0103, W2 \n" \ - "mov.w #0x0104, W3 \n" \ - "mov.w #0x0105, W4 \n" \ - "mov.w #0x0106, W5 \n" \ - "mov.w #0x0107, W6 \n" \ - "mov.w #0x0108, W7 \n" \ - "mov.w #0x0109, W8 \n" \ - "mov.w #0x010a, W9 \n" \ - "mov.w #0x010b, W10 \n" \ - "mov.w #0x010c, W11 \n" \ - "mov.w #0x010d, W12 \n" \ - "mov.w #0x010e, W13 \n" \ - "mov.w #0x010f, W14 \n" \ - "sub #0x0101, W0 \n" \ - "cp0.w W0 \n" \ - "bra NZ, ERROR_TEST1 \n" \ - "sub #0x0102, W1 \n" \ - "cp0.w W1 \n" \ - "bra NZ, ERROR_TEST1 \n" \ - "sub #0x0103, W2 \n" \ - "cp0.w W2 \n" \ - "bra NZ, ERROR_TEST1 \n" \ - "sub #0x0104, W3 \n" \ - "cp0.w W3 \n" \ - "bra NZ, ERROR_TEST1 \n" \ - "sub #0x0105, W4 \n" \ - "cp0.w W4 \n" \ - "bra NZ, ERROR_TEST1 \n" \ - "sub #0x0106, W5 \n" \ - "cp0.w W5 \n" \ - "bra NZ, ERROR_TEST1 \n" \ - "sub #0x0107, W6 \n" \ - "cp0.w W6 \n" \ - "bra NZ, ERROR_TEST1 \n" \ - "sub #0x0108, W7 \n" \ - "cp0.w W7 \n" \ - "bra NZ, ERROR_TEST1 \n" \ - "sub #0x0109, W8 \n" \ - "cp0.w W8 \n" \ - "bra NZ, ERROR_TEST1 \n" \ - "sub #0x010a, W9 \n" \ - "cp0.w W9 \n" \ - "bra NZ, ERROR_TEST1 \n" \ - "sub #0x010b, W10 \n" \ - "cp0.w W10 \n" \ - "bra NZ, ERROR_TEST1 \n" \ - "sub #0x010c, W11 \n" \ - "cp0.w W11 \n" \ - "bra NZ, ERROR_TEST1 \n" \ - "sub #0x010d, W12 \n" \ - "cp0.w W12 \n" \ - "bra NZ, ERROR_TEST1 \n" \ - "sub #0x010e, W13 \n" \ - "cp0.w W13 \n" \ - "bra NZ, ERROR_TEST1 \n" \ - "sub #0x010f, W14 \n" \ - "cp0.w W14 \n" \ - "bra NZ, ERROR_TEST1 \n" \ - "bra NO_ERROR1 \n" \ - "ERROR_TEST1: \n" \ - "mov.w #1, W0 \n" \ - "mov.w W0, _usErrorDetected\n" \ - "NO_ERROR1: \n" ); - } -} -/*-----------------------------------------------------------*/ - -void xRegisterTest2( void *pvParameters ) -{ -/* This static so as not to use the frame pointer. They are volatile -also to avoid it being stored in a register that we clobber during the test. */ -static unsigned portSHORT * volatile pusParameter; - - /* The variable incremented by this task is passed in as the parameter - even though it is defined within this file. This is just to test the - parameter passing mechanism. */ - pusParameter = pvParameters; - - for( ;; ) - { - /* Increment the variable to show this task is still cycling. */ - ( *pusParameter )++; - - /* Set the w registers to known values, then check that each register - contains the expected value. See the explanation at the top of this - file for more information. */ - asm volatile( "mov.w #0x0100, W0 \n" \ - "mov.w #0x0101, W1 \n" \ - "mov.w #0x0102, W2 \n" \ - "mov.w #0x0103, W3 \n" \ - "mov.w #0x0104, W4 \n" \ - "mov.w #0x0105, W5 \n" \ - "mov.w #0x0106, W6 \n" \ - "mov.w #0x0107, W7 \n" \ - "mov.w #0x0108, W8 \n" \ - "mov.w #0x0109, W9 \n" \ - "mov.w #0x010a, W10 \n" \ - "mov.w #0x010b, W11 \n" \ - "mov.w #0x010c, W12 \n" \ - "mov.w #0x010d, W13 \n" \ - "mov.w #0x010e, W14 \n" \ - "sub #0x0100, W0 \n" \ - "cp0.w W0 \n" \ - "bra NZ, ERROR_TEST2 \n" \ - "sub #0x0101, W1 \n" \ - "cp0.w W1 \n" \ - "bra NZ, ERROR_TEST2 \n" \ - "sub #0x0102, W2 \n" \ - "cp0.w W2 \n" \ - "bra NZ, ERROR_TEST2 \n" \ - "sub #0x0103, W3 \n" \ - "cp0.w W3 \n" \ - "bra NZ, ERROR_TEST2 \n" \ - "sub #0x0104, W4 \n" \ - "cp0.w W4 \n" \ - "bra NZ, ERROR_TEST2 \n" \ - "sub #0x0105, W5 \n" \ - "cp0.w W5 \n" \ - "bra NZ, ERROR_TEST2 \n" \ - "sub #0x0106, W6 \n" \ - "cp0.w W6 \n" \ - "bra NZ, ERROR_TEST2 \n" \ - "sub #0x0107, W7 \n" \ - "cp0.w W7 \n" \ - "bra NZ, ERROR_TEST2 \n" \ - "sub #0x0108, W8 \n" \ - "cp0.w W8 \n" \ - "bra NZ, ERROR_TEST2 \n" \ - "sub #0x0109, W9 \n" \ - "cp0.w W9 \n" \ - "bra NZ, ERROR_TEST2 \n" \ - "sub #0x010a, W10 \n" \ - "cp0.w W10 \n" \ - "bra NZ, ERROR_TEST2 \n" \ - "sub #0x010b, W11 \n" \ - "cp0.w W11 \n" \ - "bra NZ, ERROR_TEST2 \n" \ - "sub #0x010c, W12 \n" \ - "cp0.w W12 \n" \ - "bra NZ, ERROR_TEST2 \n" \ - "sub #0x010d, W13 \n" \ - "cp0.w W13 \n" \ - "bra NZ, ERROR_TEST2 \n" \ - "sub #0x010e, W14 \n" \ - "cp0.w W14 \n" \ - "bra NZ, ERROR_TEST2 \n" \ - "bra NO_ERROR2 \n" \ - "ERROR_TEST2: \n" \ - "mov.w #1, W0 \n" \ - "mov.w W0, _usErrorDetected\n" \ - "NO_ERROR2: \n" ); - } -} -/*-----------------------------------------------------------*/ - -void vApplicationIdleHook( void ) -{ - /* Schedule the co-routines from within the idle task hook. */ - vCoRoutineSchedule(); -} -/*-----------------------------------------------------------*/ diff --git a/Demo/dsPIC_MPLAB/p33FJ256GP710.gld b/Demo/dsPIC_MPLAB/p33FJ256GP710.gld deleted file mode 100644 index c5e6cffae..000000000 --- a/Demo/dsPIC_MPLAB/p33FJ256GP710.gld +++ /dev/null @@ -1,1986 +0,0 @@ -/* -** Linker script for PIC33FJ256GP710 -*/ - -OUTPUT_ARCH("33FJ256GP710") -EXTERN(__resetPRI) -EXTERN(__resetALT) - - -/* -** Memory Regions -*/ -MEMORY -{ - data (a!xr) : ORIGIN = 0x800, LENGTH = 0x7800 - reset : ORIGIN = 0x0, LENGTH = 0x4 - ivt : ORIGIN = 0x4, LENGTH = 0xFC - aivt : ORIGIN = 0x104, LENGTH = 0xFC - program (xr) : ORIGIN = 0x200, LENGTH = 0x2AA00 - FBS : ORIGIN = 0xF80000, LENGTH = 0x2 - FSS : ORIGIN = 0xF80002, LENGTH = 0x2 - FGS : ORIGIN = 0xF80004, LENGTH = 0x2 - FOSCSEL : ORIGIN = 0xF80006, LENGTH = 0x2 - FOSC : ORIGIN = 0xF80008, LENGTH = 0x2 - FWDT : ORIGIN = 0xF8000A, LENGTH = 0x2 - FPOR : ORIGIN = 0xF8000C, LENGTH = 0x2 - CONFIG3 : ORIGIN = 0xF8000E, LENGTH = 0x2 - FUID0 : ORIGIN = 0xF80010, LENGTH = 0x2 - FUID1 : ORIGIN = 0xF80012, LENGTH = 0x2 - FUID2 : ORIGIN = 0xF80014, LENGTH = 0x2 - FUID3 : ORIGIN = 0xF80016, LENGTH = 0x2 -} -__IVT_BASE = 0x4; -__AIVT_BASE = 0x104; -__DATA_BASE = 0x800; -__YDATA_BASE = 0x4800; -__DMA_BASE = 0x7800; -__DMA_END = 0x7FFF; -__CODE_BASE = 0x200; - - -/* -** ==================== Section Map ====================== -*/ -SECTIONS -{ - /* - ** ========== Program Memory ========== - */ - - - /* - ** Reset Instruction - */ - .reset : - { - SHORT(ABSOLUTE(__reset)); - SHORT(0x04); - SHORT((ABSOLUTE(__reset) >> 16) & 0x7F); - SHORT(0); - } >reset - - - /* - ** Interrupt Vector Tables - ** - ** The primary and alternate tables are loaded - ** here, between sections .reset and .text. - ** Vector table source code appears below. - */ - - - /* - ** User Code and Library Code - */ - .text __CODE_BASE : - { - *(.handle); - *(.libc) *(.libm) *(.libdsp); /* keep together in this order */ - *(.lib*); - *(.text); - } >program - - - /* - ** Configuration Words - */ - __FBS : - { *(__FBS.sec) } >FBS - __FSS : - { *(__FSS.sec) } >FSS - __FGS : - { *(__FGS.sec) } >FGS - __FOSCSEL : - { *(__FOSCSEL.sec) } >FOSCSEL - __FOSC : - { *(__FOSC.sec) } >FOSC - __FWDT : - { *(__FWDT.sec) } >FWDT - __FPOR : - { *(__FPOR.sec) } >FPOR - __FUID0 : - { *(__FUID0.sec) } >FUID0 - __FUID1 : - { *(__FUID1.sec) } >FUID1 - __FUID2 : - { *(__FUID2.sec) } >FUID2 - __FUID3 : - { *(__FUID3.sec) } >FUID3 - - - /* - ** =========== Data Memory =========== - */ - - - /* - ** ICD Debug Exec - ** - ** This section provides optional storage for - ** the ICD2 debugger. Define a global symbol - ** named __ICD2RAM to enable ICD2. This section - ** must be loaded at data address 0x800. - */ - .icd __DATA_BASE (NOLOAD): - { - . += (DEFINED (__ICD2RAM) ? 0x50 : 0 ); - } > data - - - /* - ** Other sections in data memory are not explicitly mapped. - ** Instead they are allocated according to their section - ** attributes, which is most efficient. - ** - ** If a specific arrangement of sections is required - ** (other than what can be achieved using attributes) - ** additional sections may be defined here. See chapter - ** 10.5 in the MPLAB ASM30/LINK30 User's Guide (DS51317) - ** for more information. - */ - - - /* - ** ========== Debug Info ============== - */ - - .comment 0 : { *(.comment) } - - /* - ** DWARF-2 - */ - .debug_info 0 : { *(.debug_info) *(.gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_ranges 0 : { *(.debug_ranges) } - .debug_aranges 0 : { *(.debug_aranges) } - -} /* SECTIONS */ - -/* -** ================= End of Section Map ================ -*/ - -/* -** Section Map for Interrupt Vector Tables -*/ -SECTIONS -{ - -/* -** Interrupt Vector Table -*/ -.ivt __IVT_BASE : - { - LONG( DEFINED(__ReservedTrap0) ? ABSOLUTE(__ReservedTrap0) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__OscillatorFail) ? ABSOLUTE(__OscillatorFail) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__AddressError) ? ABSOLUTE(__AddressError) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__StackError) ? ABSOLUTE(__StackError) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__MathError) ? ABSOLUTE(__MathError) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__DMACError) ? ABSOLUTE(__DMACError) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__ReservedTrap6) ? ABSOLUTE(__ReservedTrap6) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__ReservedTrap7) ? ABSOLUTE(__ReservedTrap7) : - ABSOLUTE(__DefaultInterrupt)); - - LONG( DEFINED(__INT0Interrupt) ? ABSOLUTE(__INT0Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__IC1Interrupt) ? ABSOLUTE(__IC1Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__OC1Interrupt) ? ABSOLUTE(__OC1Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__T1Interrupt) ? ABSOLUTE(__T1Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__DMA0Interrupt) ? ABSOLUTE(__DMA0Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__IC2Interrupt) ? ABSOLUTE(__IC2Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__OC2Interrupt) ? ABSOLUTE(__OC2Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__T2Interrupt) ? ABSOLUTE(__T2Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__T3Interrupt) ? ABSOLUTE(__T3Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__SPI1ErrInterrupt) ? ABSOLUTE(__SPI1ErrInterrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__SPI1Interrupt) ? ABSOLUTE(__SPI1Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__U1RXInterrupt) ? ABSOLUTE(__U1RXInterrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__U1TXInterrupt) ? ABSOLUTE(__U1TXInterrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__ADC1Interrupt) ? ABSOLUTE(__ADC1Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__DMA1Interrupt) ? ABSOLUTE(__DMA1Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt15) ? ABSOLUTE(__Interrupt15) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__SI2C1Interrupt) ? ABSOLUTE(__SI2C1Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__MI2C1Interrupt) ? ABSOLUTE(__MI2C1Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt18) ? ABSOLUTE(__Interrupt18) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__CNInterrupt) ? ABSOLUTE(__CNInterrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__INT1Interrupt) ? ABSOLUTE(__INT1Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__ADC2Interrupt) ? ABSOLUTE(__ADC2Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__IC7Interrupt) ? ABSOLUTE(__IC7Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__IC8Interrupt) ? ABSOLUTE(__IC8Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__DMA2Interrupt) ? ABSOLUTE(__DMA2Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__OC3Interrupt) ? ABSOLUTE(__OC3Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__OC4Interrupt) ? ABSOLUTE(__OC4Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__T4Interrupt) ? ABSOLUTE(__T4Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__T5Interrupt) ? ABSOLUTE(__T5Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__INT2Interrupt) ? ABSOLUTE(__INT2Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__U2RXInterrupt) ? ABSOLUTE(__U2RXInterrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__U2TXInterrupt) ? ABSOLUTE(__U2TXInterrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__SPI2ErrInterrupt) ? ABSOLUTE(__SPI2ErrInterrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__SPI2Interrupt) ? ABSOLUTE(__SPI2Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__C1RxRdyInterrupt) ? ABSOLUTE(__C1RxRdyInterrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__C1Interrupt) ? ABSOLUTE(__C1Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__DMA3Interrupt) ? ABSOLUTE(__DMA3Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__IC3Interrupt) ? ABSOLUTE(__IC3Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__IC4Interrupt) ? ABSOLUTE(__IC4Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__IC5Interrupt) ? ABSOLUTE(__IC5Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__IC6Interrupt) ? ABSOLUTE(__IC6Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__OC5Interrupt) ? ABSOLUTE(__OC5Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__OC6Interrupt) ? ABSOLUTE(__OC6Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__OC7Interrupt) ? ABSOLUTE(__OC7Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__OC8Interrupt) ? ABSOLUTE(__OC8Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt45) ? ABSOLUTE(__Interrupt45) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__DMA4Interrupt) ? ABSOLUTE(__DMA4Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__T6Interrupt) ? ABSOLUTE(__T6Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__T7Interrupt) ? ABSOLUTE(__T7Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__SI2C2Interrupt) ? ABSOLUTE(__SI2C2Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__MI2C2Interrupt) ? ABSOLUTE(__MI2C2Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__T8Interrupt) ? ABSOLUTE(__T8Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__T9Interrupt) ? ABSOLUTE(__T9Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__INT3Interrupt) ? ABSOLUTE(__INT3Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__INT4Interrupt) ? ABSOLUTE(__INT4Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__C2RxRdyInterrupt) ? ABSOLUTE(__C2RxRdyInterrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__C2Interrupt) ? ABSOLUTE(__C2Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt57) ? ABSOLUTE(__Interrupt57) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt58) ? ABSOLUTE(__Interrupt58) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__DCIErrInterrupt) ? ABSOLUTE(__DCIErrInterrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__DCIInterrupt) ? ABSOLUTE(__DCIInterrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__DMA5Interrupt) ? ABSOLUTE(__DMA5Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt62) ? ABSOLUTE(__Interrupt62) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt63) ? ABSOLUTE(__Interrupt63) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt64) ? ABSOLUTE(__Interrupt64) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__U1ErrInterrupt) ? ABSOLUTE(__U1ErrInterrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__U2ErrInterrupt) ? ABSOLUTE(__U2ErrInterrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt68) ? ABSOLUTE(__Interrupt68) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__DMA6Interrupt) ? ABSOLUTE(__DMA6Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__DMA7Interrupt) ? ABSOLUTE(__DMA7Interrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__C1TxReqInterrupt) ? ABSOLUTE(__C1TxReqInterrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__C2TxReqInterrupt) ? ABSOLUTE(__C2TxReqInterrupt) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt72) ? ABSOLUTE(__Interrupt72) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt73) ? ABSOLUTE(__Interrupt73) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt74) ? ABSOLUTE(__Interrupt74) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt75) ? ABSOLUTE(__Interrupt75) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt76) ? ABSOLUTE(__Interrupt76) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt77) ? ABSOLUTE(__Interrupt77) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt78) ? ABSOLUTE(__Interrupt78) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt79) ? ABSOLUTE(__Interrupt79) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt80) ? ABSOLUTE(__Interrupt80) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt81) ? ABSOLUTE(__Interrupt81) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt82) ? ABSOLUTE(__Interrupt82) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt83) ? ABSOLUTE(__Interrupt83) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt84) ? ABSOLUTE(__Interrupt84) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt85) ? ABSOLUTE(__Interrupt85) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt86) ? ABSOLUTE(__Interrupt86) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt87) ? ABSOLUTE(__Interrupt87) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt88) ? ABSOLUTE(__Interrupt88) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt89) ? ABSOLUTE(__Interrupt89) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt90) ? ABSOLUTE(__Interrupt90) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt91) ? ABSOLUTE(__Interrupt91) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt92) ? ABSOLUTE(__Interrupt92) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt93) ? ABSOLUTE(__Interrupt93) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt94) ? ABSOLUTE(__Interrupt94) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt95) ? ABSOLUTE(__Interrupt95) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt96) ? ABSOLUTE(__Interrupt96) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt97) ? ABSOLUTE(__Interrupt97) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt98) ? ABSOLUTE(__Interrupt98) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt99) ? ABSOLUTE(__Interrupt99) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt100) ? ABSOLUTE(__Interrupt100) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt101) ? ABSOLUTE(__Interrupt101) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt102) ? ABSOLUTE(__Interrupt102) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt103) ? ABSOLUTE(__Interrupt103) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt104) ? ABSOLUTE(__Interrupt104) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt105) ? ABSOLUTE(__Interrupt105) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt106) ? ABSOLUTE(__Interrupt106) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt107) ? ABSOLUTE(__Interrupt107) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt108) ? ABSOLUTE(__Interrupt108) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt109) ? ABSOLUTE(__Interrupt109) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt110) ? ABSOLUTE(__Interrupt110) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt111) ? ABSOLUTE(__Interrupt111) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt112) ? ABSOLUTE(__Interrupt112) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt113) ? ABSOLUTE(__Interrupt113) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt114) ? ABSOLUTE(__Interrupt114) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt115) ? ABSOLUTE(__Interrupt115) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt116) ? ABSOLUTE(__Interrupt116) : - ABSOLUTE(__DefaultInterrupt)); - LONG( DEFINED(__Interrupt117) ? ABSOLUTE(__Interrupt117) : - ABSOLUTE(__DefaultInterrupt)); - } >ivt - - -/* -** Alternate Interrupt Vector Table -*/ -.aivt __AIVT_BASE : - { - LONG( DEFINED(__AltReservedTrap0) ? ABSOLUTE(__AltReservedTrap0) : - (DEFINED(__ReservedTrap0) ? ABSOLUTE(__ReservedTrap0) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltOscillatorFail) ? ABSOLUTE(__AltOscillatorFail) : - (DEFINED(__OscillatorFail) ? ABSOLUTE(__OscillatorFail) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltAddressError) ? ABSOLUTE(__AltAddressError) : - (DEFINED(__AddressError) ? ABSOLUTE(__AddressError) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltStackError) ? ABSOLUTE(__AltStackError) : - (DEFINED(__StackError) ? ABSOLUTE(__StackError) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltMathError) ? ABSOLUTE(__AltMathError) : - (DEFINED(__MathError) ? ABSOLUTE(__MathError) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltDMACError) ? ABSOLUTE(__AltDMACError) : - (DEFINED(__DMACError) ? ABSOLUTE(__DMACError) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltReservedTrap6) ? ABSOLUTE(__AltReservedTrap6) : - (DEFINED(__ReservedTrap6) ? ABSOLUTE(__ReservedTrap6) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltReservedTrap7) ? ABSOLUTE(__AltReservedTrap7) : - (DEFINED(__ReservedTrap7) ? ABSOLUTE(__ReservedTrap7) : - ABSOLUTE(__DefaultInterrupt))); - - LONG( DEFINED(__AltINT0Interrupt) ? ABSOLUTE(__AltINT0Interrupt) : - (DEFINED(__INT0Interrupt) ? ABSOLUTE(__INT0Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltIC1Interrupt) ? ABSOLUTE(__AltIC1Interrupt) : - (DEFINED(__IC1Interrupt) ? ABSOLUTE(__IC1Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltOC1Interrupt) ? ABSOLUTE(__AltOC1Interrupt) : - (DEFINED(__OC1Interrupt) ? ABSOLUTE(__OC1Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltT1Interrupt) ? ABSOLUTE(__AltT1Interrupt) : - (DEFINED(__T1Interrupt) ? ABSOLUTE(__T1Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltDMA0Interrupt) ? ABSOLUTE(__AltDMA0Interrupt) : - (DEFINED(__DMA0Interrupt) ? ABSOLUTE(__DMA0Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltIC2Interrupt) ? ABSOLUTE(__AltIC2Interrupt) : - (DEFINED(__IC2Interrupt) ? ABSOLUTE(__IC2Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltOC2Interrupt) ? ABSOLUTE(__AltOC2Interrupt) : - (DEFINED(__OC2Interrupt) ? ABSOLUTE(__OC2Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltT2Interrupt) ? ABSOLUTE(__AltT2Interrupt) : - (DEFINED(__T2Interrupt) ? ABSOLUTE(__T2Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltT3Interrupt) ? ABSOLUTE(__AltT3Interrupt) : - (DEFINED(__T3Interrupt) ? ABSOLUTE(__T3Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltSPI1ErrInterrupt) ? ABSOLUTE(__AltSPI1ErrInterrupt) : - (DEFINED(__SPI1ErrInterrupt) ? ABSOLUTE(__SPI1ErrInterrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltSPI1Interrupt) ? ABSOLUTE(__AltSPI1Interrupt) : - (DEFINED(__SPI1Interrupt) ? ABSOLUTE(__SPI1Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltU1RXInterrupt) ? ABSOLUTE(__AltU1RXInterrupt) : - (DEFINED(__U1RXInterrupt) ? ABSOLUTE(__U1RXInterrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltU1TXInterrupt) ? ABSOLUTE(__AltU1TXInterrupt) : - (DEFINED(__U1TXInterrupt) ? ABSOLUTE(__U1TXInterrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltADC1Interrupt) ? ABSOLUTE(__AltADC1Interrupt) : - (DEFINED(__ADC1Interrupt) ? ABSOLUTE(__ADC1Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltDMA1Interrupt) ? ABSOLUTE(__AltDMA1Interrupt) : - (DEFINED(__DMA1Interrupt) ? ABSOLUTE(__DMA1Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt15) ? ABSOLUTE(__AltInterrupt15) : - (DEFINED(__Interrupt15) ? ABSOLUTE(__Interrupt15) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltSI2C1Interrupt) ? ABSOLUTE(__AltSI2C1Interrupt) : - (DEFINED(__SI2C1Interrupt) ? ABSOLUTE(__SI2C1Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltMI2C1Interrupt) ? ABSOLUTE(__AltMI2C1Interrupt) : - (DEFINED(__MI2C1Interrupt) ? ABSOLUTE(__MI2C1Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt18) ? ABSOLUTE(__AltInterrupt18) : - (DEFINED(__Interrupt18) ? ABSOLUTE(__Interrupt18) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltCNInterrupt) ? ABSOLUTE(__AltCNInterrupt) : - (DEFINED(__CNInterrupt) ? ABSOLUTE(__CNInterrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltINT1Interrupt) ? ABSOLUTE(__AltINT1Interrupt) : - (DEFINED(__INT1Interrupt) ? ABSOLUTE(__INT1Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltADC2Interrupt) ? ABSOLUTE(__AltADC2Interrupt) : - (DEFINED(__ADC2Interrupt) ? ABSOLUTE(__ADC2Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltIC7Interrupt) ? ABSOLUTE(__AltIC7Interrupt) : - (DEFINED(__IC7Interrupt) ? ABSOLUTE(__IC7Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltIC8Interrupt) ? ABSOLUTE(__AltIC8Interrupt) : - (DEFINED(__IC8Interrupt) ? ABSOLUTE(__IC8Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltDMA2Interrupt) ? ABSOLUTE(__AltDMA2Interrupt) : - (DEFINED(__DMA2Interrupt) ? ABSOLUTE(__DMA2Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltOC3Interrupt) ? ABSOLUTE(__AltOC3Interrupt) : - (DEFINED(__OC3Interrupt) ? ABSOLUTE(__OC3Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltOC4Interrupt) ? ABSOLUTE(__AltOC4Interrupt) : - (DEFINED(__OC4Interrupt) ? ABSOLUTE(__OC4Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltT4Interrupt) ? ABSOLUTE(__AltT4Interrupt) : - (DEFINED(__T4Interrupt) ? ABSOLUTE(__T4Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltT5Interrupt) ? ABSOLUTE(__AltT5Interrupt) : - (DEFINED(__T5Interrupt) ? ABSOLUTE(__T5Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltINT2Interrupt) ? ABSOLUTE(__AltINT2Interrupt) : - (DEFINED(__INT2Interrupt) ? ABSOLUTE(__INT2Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltU2RXInterrupt) ? ABSOLUTE(__AltU2RXInterrupt) : - (DEFINED(__U2RXInterrupt) ? ABSOLUTE(__U2RXInterrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltU2TXInterrupt) ? ABSOLUTE(__AltU2TXInterrupt) : - (DEFINED(__U2TXInterrupt) ? ABSOLUTE(__U2TXInterrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltSPI2ErrInterrupt) ? ABSOLUTE(__AltSPI2ErrInterrupt) : - (DEFINED(__SPI2ErrInterrupt) ? ABSOLUTE(__SPI2ErrInterrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltSPI2Interrupt) ? ABSOLUTE(__AltSPI2Interrupt) : - (DEFINED(__SPI2Interrupt) ? ABSOLUTE(__SPI2Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltC1RxRdyInterrupt) ? ABSOLUTE(__AltC1RxRdyInterrupt) : - (DEFINED(__C1RxRdyInterrupt) ? ABSOLUTE(__C1RxRdyInterrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltC1Interrupt) ? ABSOLUTE(__AltC1Interrupt) : - (DEFINED(__C1Interrupt) ? ABSOLUTE(__C1Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltDMA3Interrupt) ? ABSOLUTE(__AltDMA3Interrupt) : - (DEFINED(__DMA3Interrupt) ? ABSOLUTE(__DMA3Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltIC3Interrupt) ? ABSOLUTE(__AltIC3Interrupt) : - (DEFINED(__IC3Interrupt) ? ABSOLUTE(__IC3Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltIC4Interrupt) ? ABSOLUTE(__AltIC4Interrupt) : - (DEFINED(__IC4Interrupt) ? ABSOLUTE(__IC4Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltIC5Interrupt) ? ABSOLUTE(__AltIC5Interrupt) : - (DEFINED(__IC5Interrupt) ? ABSOLUTE(__IC5Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltIC6Interrupt) ? ABSOLUTE(__AltIC6Interrupt) : - (DEFINED(__IC6Interrupt) ? ABSOLUTE(__IC6Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltOC5Interrupt) ? ABSOLUTE(__AltOC5Interrupt) : - (DEFINED(__OC5Interrupt) ? ABSOLUTE(__OC5Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltOC6Interrupt) ? ABSOLUTE(__AltOC6Interrupt) : - (DEFINED(__OC6Interrupt) ? ABSOLUTE(__OC6Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltOC7Interrupt) ? ABSOLUTE(__AltOC7Interrupt) : - (DEFINED(__OC7Interrupt) ? ABSOLUTE(__OC7Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltOC8Interrupt) ? ABSOLUTE(__AltOC8Interrupt) : - (DEFINED(__OC8Interrupt) ? ABSOLUTE(__OC8Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt45) ? ABSOLUTE(__AltInterrupt45) : - (DEFINED(__Interrupt45) ? ABSOLUTE(__Interrupt45) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltDMA4Interrupt) ? ABSOLUTE(__AltDMA4Interrupt) : - (DEFINED(__DMA4Interrupt) ? ABSOLUTE(__DMA4Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltT6Interrupt) ? ABSOLUTE(__AltT6Interrupt) : - (DEFINED(__T6Interrupt) ? ABSOLUTE(__T6Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltT7Interrupt) ? ABSOLUTE(__AltT7Interrupt) : - (DEFINED(__T7Interrupt) ? ABSOLUTE(__T7Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltSI2C2Interrupt) ? ABSOLUTE(__AltSI2C2Interrupt) : - (DEFINED(__SI2C2Interrupt) ? ABSOLUTE(__SI2C2Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltMI2C2Interrupt) ? ABSOLUTE(__AltMI2C2Interrupt) : - (DEFINED(__MI2C2Interrupt) ? ABSOLUTE(__MI2C2Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltT8Interrupt) ? ABSOLUTE(__AltT8Interrupt) : - (DEFINED(__T8Interrupt) ? ABSOLUTE(__T8Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltT9Interrupt) ? ABSOLUTE(__AltT9Interrupt) : - (DEFINED(__T9Interrupt) ? ABSOLUTE(__T9Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltINT3Interrupt) ? ABSOLUTE(__AltINT3Interrupt) : - (DEFINED(__INT3Interrupt) ? ABSOLUTE(__INT3Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltINT4Interrupt) ? ABSOLUTE(__AltINT4Interrupt) : - (DEFINED(__INT4Interrupt) ? ABSOLUTE(__INT4Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltC2RxRdyInterrupt) ? ABSOLUTE(__AltC2RxRdyInterrupt) : - (DEFINED(__C2RxRdyInterrupt) ? ABSOLUTE(__C2RxRdyInterrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltC2Interrupt) ? ABSOLUTE(__AltC2Interrupt) : - (DEFINED(__C2Interrupt) ? ABSOLUTE(__C2Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt57) ? ABSOLUTE(__AltInterrupt57) : - (DEFINED(__Interrupt57) ? ABSOLUTE(__Interrupt57) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt58) ? ABSOLUTE(__AltInterrupt58) : - (DEFINED(__Interrupt58) ? ABSOLUTE(__Interrupt58) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltDCIErrInterrupt) ? ABSOLUTE(__AltDCIErrInterrupt) : - (DEFINED(__DCIErrInterrupt) ? ABSOLUTE(__DCIErrInterrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltDCIInterrupt) ? ABSOLUTE(__AltDCIInterrupt) : - (DEFINED(__DCIInterrupt) ? ABSOLUTE(__DCIInterrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltDMA5Interrupt) ? ABSOLUTE(__AltDMA5Interrupt) : - (DEFINED(__DMA5Interrupt) ? ABSOLUTE(__DMA5Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt62) ? ABSOLUTE(__AltInterrupt62) : - (DEFINED(__Interrupt62) ? ABSOLUTE(__Interrupt62) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt63) ? ABSOLUTE(__AltInterrupt63) : - (DEFINED(__Interrupt63) ? ABSOLUTE(__Interrupt63) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt64) ? ABSOLUTE(__AltInterrupt64) : - (DEFINED(__Interrupt64) ? ABSOLUTE(__Interrupt64) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltU1ErrInterrupt) ? ABSOLUTE(__AltU1ErrInterrupt) : - (DEFINED(__U1ErrInterrupt) ? ABSOLUTE(__U1ErrInterrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltU2ErrInterrupt) ? ABSOLUTE(__AltU2ErrInterrupt) : - (DEFINED(__U2ErrInterrupt) ? ABSOLUTE(__U2ErrInterrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt68) ? ABSOLUTE(__AltInterrupt68) : - (DEFINED(__Interrupt68) ? ABSOLUTE(__Interrupt68) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltDMA6Interrupt) ? ABSOLUTE(__AltDMA6Interrupt) : - (DEFINED(__DMA6Interrupt) ? ABSOLUTE(__DMA6Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltDMA7Interrupt) ? ABSOLUTE(__AltDMA7Interrupt) : - (DEFINED(__DMA7Interrupt) ? ABSOLUTE(__DMA7Interrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltC1TxReqInterrupt) ? ABSOLUTE(__AltC1TxReqInterrupt) : - (DEFINED(__C1TxReqInterrupt) ? ABSOLUTE(__C1TxReqInterrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltC2TxReqInterrupt) ? ABSOLUTE(__AltC2TxReqInterrupt) : - (DEFINED(__C2TxReqInterrupt) ? ABSOLUTE(__C2TxReqInterrupt) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt72) ? ABSOLUTE(__AltInterrupt72) : - (DEFINED(__Interrupt72) ? ABSOLUTE(__Interrupt72) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt73) ? ABSOLUTE(__AltInterrupt73) : - (DEFINED(__Interrupt73) ? ABSOLUTE(__Interrupt73) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt74) ? ABSOLUTE(__AltInterrupt74) : - (DEFINED(__Interrupt74) ? ABSOLUTE(__Interrupt74) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt75) ? ABSOLUTE(__AltInterrupt75) : - (DEFINED(__Interrupt75) ? ABSOLUTE(__Interrupt75) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt76) ? ABSOLUTE(__AltInterrupt76) : - (DEFINED(__Interrupt76) ? ABSOLUTE(__Interrupt76) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt77) ? ABSOLUTE(__AltInterrupt77) : - (DEFINED(__Interrupt77) ? ABSOLUTE(__Interrupt77) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt78) ? ABSOLUTE(__AltInterrupt78) : - (DEFINED(__Interrupt78) ? ABSOLUTE(__Interrupt78) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt79) ? ABSOLUTE(__AltInterrupt79) : - (DEFINED(__Interrupt79) ? ABSOLUTE(__Interrupt79) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt80) ? ABSOLUTE(__AltInterrupt80) : - (DEFINED(__Interrupt80) ? ABSOLUTE(__Interrupt80) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt81) ? ABSOLUTE(__AltInterrupt81) : - (DEFINED(__Interrupt81) ? ABSOLUTE(__Interrupt81) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt82) ? ABSOLUTE(__AltInterrupt82) : - (DEFINED(__Interrupt82) ? ABSOLUTE(__Interrupt82) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt83) ? ABSOLUTE(__AltInterrupt83) : - (DEFINED(__Interrupt83) ? ABSOLUTE(__Interrupt83) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt84) ? ABSOLUTE(__AltInterrupt84) : - (DEFINED(__Interrupt84) ? ABSOLUTE(__Interrupt84) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt85) ? ABSOLUTE(__AltInterrupt85) : - (DEFINED(__Interrupt85) ? ABSOLUTE(__Interrupt85) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt86) ? ABSOLUTE(__AltInterrupt86) : - (DEFINED(__Interrupt86) ? ABSOLUTE(__Interrupt86) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt87) ? ABSOLUTE(__AltInterrupt87) : - (DEFINED(__Interrupt87) ? ABSOLUTE(__Interrupt87) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt88) ? ABSOLUTE(__AltInterrupt88) : - (DEFINED(__Interrupt88) ? ABSOLUTE(__Interrupt88) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt89) ? ABSOLUTE(__AltInterrupt89) : - (DEFINED(__Interrupt89) ? ABSOLUTE(__Interrupt89) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt90) ? ABSOLUTE(__AltInterrupt90) : - (DEFINED(__Interrupt90) ? ABSOLUTE(__Interrupt90) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt91) ? ABSOLUTE(__AltInterrupt91) : - (DEFINED(__Interrupt91) ? ABSOLUTE(__Interrupt91) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt92) ? ABSOLUTE(__AltInterrupt92) : - (DEFINED(__Interrupt92) ? ABSOLUTE(__Interrupt92) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt93) ? ABSOLUTE(__AltInterrupt93) : - (DEFINED(__Interrupt93) ? ABSOLUTE(__Interrupt93) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt94) ? ABSOLUTE(__AltInterrupt94) : - (DEFINED(__Interrupt94) ? ABSOLUTE(__Interrupt94) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt95) ? ABSOLUTE(__AltInterrupt95) : - (DEFINED(__Interrupt95) ? ABSOLUTE(__Interrupt95) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt96) ? ABSOLUTE(__AltInterrupt96) : - (DEFINED(__Interrupt96) ? ABSOLUTE(__Interrupt96) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt97) ? ABSOLUTE(__AltInterrupt97) : - (DEFINED(__Interrupt97) ? ABSOLUTE(__Interrupt97) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt98) ? ABSOLUTE(__AltInterrupt98) : - (DEFINED(__Interrupt98) ? ABSOLUTE(__Interrupt98) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt99) ? ABSOLUTE(__AltInterrupt99) : - (DEFINED(__Interrupt99) ? ABSOLUTE(__Interrupt99) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt100) ? ABSOLUTE(__AltInterrupt100) : - (DEFINED(__Interrupt100) ? ABSOLUTE(__Interrupt100) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt101) ? ABSOLUTE(__AltInterrupt101) : - (DEFINED(__Interrupt101) ? ABSOLUTE(__Interrupt101) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt102) ? ABSOLUTE(__AltInterrupt102) : - (DEFINED(__Interrupt102) ? ABSOLUTE(__Interrupt102) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt103) ? ABSOLUTE(__AltInterrupt103) : - (DEFINED(__Interrupt103) ? ABSOLUTE(__Interrupt103) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt104) ? ABSOLUTE(__AltInterrupt104) : - (DEFINED(__Interrupt104) ? ABSOLUTE(__Interrupt104) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt105) ? ABSOLUTE(__AltInterrupt105) : - (DEFINED(__Interrupt105) ? ABSOLUTE(__Interrupt105) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt106) ? ABSOLUTE(__AltInterrupt106) : - (DEFINED(__Interrupt106) ? ABSOLUTE(__Interrupt106) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt107) ? ABSOLUTE(__AltInterrupt107) : - (DEFINED(__Interrupt107) ? ABSOLUTE(__Interrupt107) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt108) ? ABSOLUTE(__AltInterrupt108) : - (DEFINED(__Interrupt108) ? ABSOLUTE(__Interrupt108) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt109) ? ABSOLUTE(__AltInterrupt109) : - (DEFINED(__Interrupt109) ? ABSOLUTE(__Interrupt109) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt110) ? ABSOLUTE(__AltInterrupt110) : - (DEFINED(__Interrupt110) ? ABSOLUTE(__Interrupt110) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt111) ? ABSOLUTE(__AltInterrupt111) : - (DEFINED(__Interrupt111) ? ABSOLUTE(__Interrupt111) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt112) ? ABSOLUTE(__AltInterrupt112) : - (DEFINED(__Interrupt112) ? ABSOLUTE(__Interrupt112) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt113) ? ABSOLUTE(__AltInterrupt113) : - (DEFINED(__Interrupt113) ? ABSOLUTE(__Interrupt113) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt114) ? ABSOLUTE(__AltInterrupt114) : - (DEFINED(__Interrupt114) ? ABSOLUTE(__Interrupt114) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt115) ? ABSOLUTE(__AltInterrupt115) : - (DEFINED(__Interrupt115) ? ABSOLUTE(__Interrupt115) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt116) ? ABSOLUTE(__AltInterrupt116) : - (DEFINED(__Interrupt116) ? ABSOLUTE(__Interrupt116) : - ABSOLUTE(__DefaultInterrupt))); - LONG( DEFINED(__AltInterrupt117) ? ABSOLUTE(__AltInterrupt117) : - (DEFINED(__Interrupt117) ? ABSOLUTE(__Interrupt117) : - ABSOLUTE(__DefaultInterrupt))); - } >aivt -} /* SECTIONS */ - - -/* -** ============== Equates for SFR Addresses ============= -*/ - - WREG0 = 0x0; -_WREG0 = 0x0; - WREG1 = 0x2; -_WREG1 = 0x2; - WREG2 = 0x4; -_WREG2 = 0x4; - WREG3 = 0x6; -_WREG3 = 0x6; - WREG4 = 0x8; -_WREG4 = 0x8; - WREG5 = 0xA; -_WREG5 = 0xA; - WREG6 = 0xC; -_WREG6 = 0xC; - WREG7 = 0xE; -_WREG7 = 0xE; - WREG8 = 0x10; -_WREG8 = 0x10; - WREG9 = 0x12; -_WREG9 = 0x12; - WREG10 = 0x14; -_WREG10 = 0x14; - WREG11 = 0x16; -_WREG11 = 0x16; - WREG12 = 0x18; -_WREG12 = 0x18; - WREG13 = 0x1A; -_WREG13 = 0x1A; - WREG14 = 0x1C; -_WREG14 = 0x1C; - WREG15 = 0x1E; -_WREG15 = 0x1E; - SPLIM = 0x20; -_SPLIM = 0x20; - ACCAL = 0x22; -_ACCAL = 0x22; - ACCAH = 0x24; -_ACCAH = 0x24; - ACCAU = 0x26; -_ACCAU = 0x26; - ACCBL = 0x28; -_ACCBL = 0x28; - ACCBH = 0x2A; -_ACCBH = 0x2A; - ACCBU = 0x2C; -_ACCBU = 0x2C; - PCL = 0x2E; -_PCL = 0x2E; - PCH = 0x30; -_PCH = 0x30; - TBLPAG = 0x32; -_TBLPAG = 0x32; - PSVPAG = 0x34; -_PSVPAG = 0x34; - RCOUNT = 0x36; -_RCOUNT = 0x36; - DCOUNT = 0x38; -_DCOUNT = 0x38; - DOSTARTL = 0x3A; -_DOSTARTL = 0x3A; - DOSTARTH = 0x3C; -_DOSTARTH = 0x3C; - DOENDL = 0x3E; -_DOENDL = 0x3E; - DOENDH = 0x40; -_DOENDH = 0x40; - SR = 0x42; -_SR = 0x42; -_SRbits = 0x42; - CORCON = 0x44; -_CORCON = 0x44; -_CORCONbits = 0x44; - MODCON = 0x46; -_MODCON = 0x46; -_MODCONbits = 0x46; - XMODSRT = 0x48; -_XMODSRT = 0x48; - XMODEND = 0x4A; -_XMODEND = 0x4A; - YMODSRT = 0x4C; -_YMODSRT = 0x4C; - YMODEND = 0x4E; -_YMODEND = 0x4E; - XBREV = 0x50; -_XBREV = 0x50; -_XBREVbits = 0x50; - DISICNT = 0x52; -_DISICNT = 0x52; - CNEN1 = 0x60; -_CNEN1 = 0x60; -_CNEN1bits = 0x60; - CNEN2 = 0x62; -_CNEN2 = 0x62; -_CNEN2bits = 0x62; - CNPU1 = 0x68; -_CNPU1 = 0x68; -_CNPU1bits = 0x68; - CNPU2 = 0x6A; -_CNPU2 = 0x6A; -_CNPU2bits = 0x6A; - INTCON1 = 0x80; -_INTCON1 = 0x80; -_INTCON1bits = 0x80; - INTCON2 = 0x82; -_INTCON2 = 0x82; -_INTCON2bits = 0x82; - IFS0 = 0x84; -_IFS0 = 0x84; -_IFS0bits = 0x84; - IFS1 = 0x86; -_IFS1 = 0x86; -_IFS1bits = 0x86; - IFS2 = 0x88; -_IFS2 = 0x88; -_IFS2bits = 0x88; - IFS3 = 0x8A; -_IFS3 = 0x8A; -_IFS3bits = 0x8A; - IFS4 = 0x8C; -_IFS4 = 0x8C; -_IFS4bits = 0x8C; - IEC0 = 0x94; -_IEC0 = 0x94; -_IEC0bits = 0x94; - IEC1 = 0x96; -_IEC1 = 0x96; -_IEC1bits = 0x96; - IEC2 = 0x98; -_IEC2 = 0x98; -_IEC2bits = 0x98; - IEC3 = 0x9A; -_IEC3 = 0x9A; -_IEC3bits = 0x9A; - IEC4 = 0x9C; -_IEC4 = 0x9C; -_IEC4bits = 0x9C; - IPC0 = 0xA4; -_IPC0 = 0xA4; -_IPC0bits = 0xA4; - IPC1 = 0xA6; -_IPC1 = 0xA6; -_IPC1bits = 0xA6; - IPC2 = 0xA8; -_IPC2 = 0xA8; -_IPC2bits = 0xA8; - IPC3 = 0xAA; -_IPC3 = 0xAA; -_IPC3bits = 0xAA; - IPC4 = 0xAC; -_IPC4 = 0xAC; -_IPC4bits = 0xAC; - IPC5 = 0xAE; -_IPC5 = 0xAE; -_IPC5bits = 0xAE; - IPC6 = 0xB0; -_IPC6 = 0xB0; -_IPC6bits = 0xB0; - IPC7 = 0xB2; -_IPC7 = 0xB2; -_IPC7bits = 0xB2; - IPC8 = 0xB4; -_IPC8 = 0xB4; -_IPC8bits = 0xB4; - IPC9 = 0xB6; -_IPC9 = 0xB6; -_IPC9bits = 0xB6; - IPC10 = 0xB8; -_IPC10 = 0xB8; -_IPC10bits = 0xB8; - IPC11 = 0xBA; -_IPC11 = 0xBA; -_IPC11bits = 0xBA; - IPC12 = 0xBC; -_IPC12 = 0xBC; -_IPC12bits = 0xBC; - IPC13 = 0xBE; -_IPC13 = 0xBE; -_IPC13bits = 0xBE; - IPC14 = 0xC0; -_IPC14 = 0xC0; -_IPC14bits = 0xC0; - IPC15 = 0xC2; -_IPC15 = 0xC2; -_IPC15bits = 0xC2; - IPC16 = 0xC4; -_IPC16 = 0xC4; -_IPC16bits = 0xC4; - IPC17 = 0xC6; -_IPC17 = 0xC6; -_IPC17bits = 0xC6; - INTTREG = 0xE0; -_INTTREG = 0xE0; -_INTTREGbits = 0xE0; - TMR1 = 0x100; -_TMR1 = 0x100; - PR1 = 0x102; -_PR1 = 0x102; - T1CON = 0x104; -_T1CON = 0x104; -_T1CONbits = 0x104; - TMR2 = 0x106; -_TMR2 = 0x106; - TMR3HLD = 0x108; -_TMR3HLD = 0x108; - TMR3 = 0x10A; -_TMR3 = 0x10A; - PR2 = 0x10C; -_PR2 = 0x10C; - PR3 = 0x10E; -_PR3 = 0x10E; - T2CON = 0x110; -_T2CON = 0x110; -_T2CONbits = 0x110; - T3CON = 0x112; -_T3CON = 0x112; -_T3CONbits = 0x112; - TMR4 = 0x114; -_TMR4 = 0x114; - TMR5HLD = 0x116; -_TMR5HLD = 0x116; - TMR5 = 0x118; -_TMR5 = 0x118; - PR4 = 0x11A; -_PR4 = 0x11A; - PR5 = 0x11C; -_PR5 = 0x11C; - T4CON = 0x11E; -_T4CON = 0x11E; -_T4CONbits = 0x11E; - T5CON = 0x120; -_T5CON = 0x120; -_T5CONbits = 0x120; - TMR6 = 0x122; -_TMR6 = 0x122; - TMR7HLD = 0x124; -_TMR7HLD = 0x124; - TMR7 = 0x126; -_TMR7 = 0x126; - PR6 = 0x128; -_PR6 = 0x128; - PR7 = 0x12A; -_PR7 = 0x12A; - T6CON = 0x12C; -_T6CON = 0x12C; -_T6CONbits = 0x12C; - T7CON = 0x12E; -_T7CON = 0x12E; -_T7CONbits = 0x12E; - TMR8 = 0x130; -_TMR8 = 0x130; - TMR9HLD = 0x132; -_TMR9HLD = 0x132; - TMR9 = 0x134; -_TMR9 = 0x134; - PR8 = 0x136; -_PR8 = 0x136; - PR9 = 0x138; -_PR9 = 0x138; - T8CON = 0x13A; -_T8CON = 0x13A; -_T8CONbits = 0x13A; - T9CON = 0x13C; -_T9CON = 0x13C; -_T9CONbits = 0x13C; - IC1BUF = 0x140; -_IC1BUF = 0x140; - IC1CON = 0x142; -_IC1CON = 0x142; -_IC1CONbits = 0x142; - IC2BUF = 0x144; -_IC2BUF = 0x144; - IC2CON = 0x146; -_IC2CON = 0x146; -_IC2CONbits = 0x146; - IC3BUF = 0x148; -_IC3BUF = 0x148; - IC3CON = 0x14A; -_IC3CON = 0x14A; -_IC3CONbits = 0x14A; - IC4BUF = 0x14C; -_IC4BUF = 0x14C; - IC4CON = 0x14E; -_IC4CON = 0x14E; -_IC4CONbits = 0x14E; - IC5BUF = 0x150; -_IC5BUF = 0x150; - IC5CON = 0x152; -_IC5CON = 0x152; -_IC5CONbits = 0x152; - IC6BUF = 0x154; -_IC6BUF = 0x154; - IC6CON = 0x156; -_IC6CON = 0x156; -_IC6CONbits = 0x156; - IC7BUF = 0x158; -_IC7BUF = 0x158; - IC7CON = 0x15A; -_IC7CON = 0x15A; -_IC7CONbits = 0x15A; - IC8BUF = 0x15C; -_IC8BUF = 0x15C; - IC8CON = 0x15E; -_IC8CON = 0x15E; -_IC8CONbits = 0x15E; - OC1RS = 0x180; -_OC1RS = 0x180; - OC1R = 0x182; -_OC1R = 0x182; - OC1CON = 0x184; -_OC1CON = 0x184; -_OC1CONbits = 0x184; - OC2RS = 0x186; -_OC2RS = 0x186; - OC2R = 0x188; -_OC2R = 0x188; - OC2CON = 0x18A; -_OC2CON = 0x18A; -_OC2CONbits = 0x18A; - OC3RS = 0x18C; -_OC3RS = 0x18C; - OC3R = 0x18E; -_OC3R = 0x18E; - OC3CON = 0x190; -_OC3CON = 0x190; -_OC3CONbits = 0x190; - OC4RS = 0x192; -_OC4RS = 0x192; - OC4R = 0x194; -_OC4R = 0x194; - OC4CON = 0x196; -_OC4CON = 0x196; -_OC4CONbits = 0x196; - OC5RS = 0x198; -_OC5RS = 0x198; - OC5R = 0x19A; -_OC5R = 0x19A; - OC5CON = 0x19C; -_OC5CON = 0x19C; -_OC5CONbits = 0x19C; - OC6RS = 0x19E; -_OC6RS = 0x19E; - OC6R = 0x1A0; -_OC6R = 0x1A0; - OC6CON = 0x1A2; -_OC6CON = 0x1A2; -_OC6CONbits = 0x1A2; - OC7RS = 0x1A4; -_OC7RS = 0x1A4; - OC7R = 0x1A6; -_OC7R = 0x1A6; - OC7CON = 0x1A8; -_OC7CON = 0x1A8; -_OC7CONbits = 0x1A8; - OC8RS = 0x1AA; -_OC8RS = 0x1AA; - OC8R = 0x1AC; -_OC8R = 0x1AC; - OC8CON = 0x1AE; -_OC8CON = 0x1AE; -_OC8CONbits = 0x1AE; - I2C1RCV = 0x200; -_I2C1RCV = 0x200; - I2C1TRN = 0x202; -_I2C1TRN = 0x202; - I2C1BRG = 0x204; -_I2C1BRG = 0x204; - I2C1CON = 0x206; -_I2C1CON = 0x206; -_I2C1CONbits = 0x206; - I2C1STAT = 0x208; -_I2C1STAT = 0x208; -_I2C1STATbits = 0x208; - I2C1ADD = 0x20A; -_I2C1ADD = 0x20A; - I2C1MSK = 0x20C; -_I2C1MSK = 0x20C; - I2C2RCV = 0x210; -_I2C2RCV = 0x210; - I2C2TRN = 0x212; -_I2C2TRN = 0x212; - I2C2BRG = 0x214; -_I2C2BRG = 0x214; - I2C2CON = 0x216; -_I2C2CON = 0x216; -_I2C2CONbits = 0x216; - I2C2STAT = 0x218; -_I2C2STAT = 0x218; -_I2C2STATbits = 0x218; - I2C2ADD = 0x21A; -_I2C2ADD = 0x21A; - I2C2MSK = 0x21C; -_I2C2MSK = 0x21C; - U1MODE = 0x220; -_U1MODE = 0x220; -_U1MODEbits = 0x220; - U1STA = 0x222; -_U1STA = 0x222; -_U1STAbits = 0x222; - U1TXREG = 0x224; -_U1TXREG = 0x224; -_U1TXREGbits = 0x224; - U1RXREG = 0x226; -_U1RXREG = 0x226; -_U1RXREGbits = 0x226; - U1BRG = 0x228; -_U1BRG = 0x228; - U2MODE = 0x230; -_U2MODE = 0x230; -_U2MODEbits = 0x230; - U2STA = 0x232; -_U2STA = 0x232; -_U2STAbits = 0x232; - U2TXREG = 0x234; -_U2TXREG = 0x234; -_U2TXREGbits = 0x234; - U2RXREG = 0x236; -_U2RXREG = 0x236; -_U2RXREGbits = 0x236; - U2BRG = 0x238; -_U2BRG = 0x238; - SPI1STAT = 0x240; -_SPI1STAT = 0x240; -_SPI1STATbits = 0x240; - SPI1CON1 = 0x242; -_SPI1CON1 = 0x242; -_SPI1CON1bits = 0x242; - SPI1CON2 = 0x244; -_SPI1CON2 = 0x244; -_SPI1CON2bits = 0x244; - SPI1BUF = 0x248; -_SPI1BUF = 0x248; - SPI2STAT = 0x260; -_SPI2STAT = 0x260; -_SPI2STATbits = 0x260; - SPI2CON1 = 0x262; -_SPI2CON1 = 0x262; -_SPI2CON1bits = 0x262; - SPI2CON2 = 0x264; -_SPI2CON2 = 0x264; -_SPI2CON2bits = 0x264; - SPI2BUF = 0x268; -_SPI2BUF = 0x268; - DCICON1 = 0x280; -_DCICON1 = 0x280; -_DCICON1bits = 0x280; - DCICON2 = 0x282; -_DCICON2 = 0x282; -_DCICON2bits = 0x282; - DCICON3 = 0x284; -_DCICON3 = 0x284; -_DCICON3bits = 0x284; - DCISTAT = 0x286; -_DCISTAT = 0x286; -_DCISTATbits = 0x286; - TSCON = 0x288; -_TSCON = 0x288; -_TSCONbits = 0x288; - RSCON = 0x28C; -_RSCON = 0x28C; -_RSCONbits = 0x28C; - RXBUF0 = 0x290; -_RXBUF0 = 0x290; - RXBUF1 = 0x292; -_RXBUF1 = 0x292; - RXBUF2 = 0x294; -_RXBUF2 = 0x294; - RXBUF3 = 0x296; -_RXBUF3 = 0x296; - TXBUF0 = 0x298; -_TXBUF0 = 0x298; - TXBUF1 = 0x29A; -_TXBUF1 = 0x29A; - TXBUF2 = 0x29C; -_TXBUF2 = 0x29C; - TXBUF3 = 0x29E; -_TXBUF3 = 0x29E; - TRISA = 0x2C0; -_TRISA = 0x2C0; -_TRISAbits = 0x2C0; - PORTA = 0x2C2; -_PORTA = 0x2C2; -_PORTAbits = 0x2C2; - LATA = 0x2C4; -_LATA = 0x2C4; -_LATAbits = 0x2C4; - TRISB = 0x2C6; -_TRISB = 0x2C6; -_TRISBbits = 0x2C6; - PORTB = 0x2C8; -_PORTB = 0x2C8; -_PORTBbits = 0x2C8; - LATB = 0x2CA; -_LATB = 0x2CA; -_LATBbits = 0x2CA; - TRISC = 0x2CC; -_TRISC = 0x2CC; -_TRISCbits = 0x2CC; - PORTC = 0x2CE; -_PORTC = 0x2CE; -_PORTCbits = 0x2CE; - LATC = 0x2D0; -_LATC = 0x2D0; -_LATCbits = 0x2D0; - TRISD = 0x2D2; -_TRISD = 0x2D2; -_TRISDbits = 0x2D2; - PORTD = 0x2D4; -_PORTD = 0x2D4; -_PORTDbits = 0x2D4; - LATD = 0x2D6; -_LATD = 0x2D6; -_LATDbits = 0x2D6; - TRISE = 0x2D8; -_TRISE = 0x2D8; -_TRISEbits = 0x2D8; - PORTE = 0x2DA; -_PORTE = 0x2DA; -_PORTEbits = 0x2DA; - LATE = 0x2DC; -_LATE = 0x2DC; -_LATEbits = 0x2DC; - TRISF = 0x2DE; -_TRISF = 0x2DE; -_TRISFbits = 0x2DE; - PORTF = 0x2E0; -_PORTF = 0x2E0; -_PORTFbits = 0x2E0; - LATF = 0x2E2; -_LATF = 0x2E2; -_LATFbits = 0x2E2; - TRISG = 0x2E4; -_TRISG = 0x2E4; -_TRISGbits = 0x2E4; - PORTG = 0x2E6; -_PORTG = 0x2E6; -_PORTGbits = 0x2E6; - LATG = 0x2E8; -_LATG = 0x2E8; -_LATGbits = 0x2E8; - ADC1BUF0 = 0x300; -_ADC1BUF0 = 0x300; - AD1CON1 = 0x320; -_AD1CON1 = 0x320; -_AD1CON1bits = 0x320; - AD1CON2 = 0x322; -_AD1CON2 = 0x322; -_AD1CON2bits = 0x322; - AD1CON3 = 0x324; -_AD1CON3 = 0x324; -_AD1CON3bits = 0x324; - AD1CHS123 = 0x326; -_AD1CHS123 = 0x326; -_AD1CHS123bits = 0x326; - AD1CHS0 = 0x328; -_AD1CHS0 = 0x328; -_AD1CHS0bits = 0x328; - AD1PCFGH = 0x32A; -_AD1PCFGH = 0x32A; -_AD1PCFGHbits = 0x32A; - AD1PCFGL = 0x32C; -_AD1PCFGL = 0x32C; -_AD1PCFGLbits = 0x32C; - AD1CSSH = 0x32E; -_AD1CSSH = 0x32E; -_AD1CSSHbits = 0x32E; - AD1CSSL = 0x330; -_AD1CSSL = 0x330; -_AD1CSSLbits = 0x330; - AD1CON4 = 0x332; -_AD1CON4 = 0x332; -_AD1CON4bits = 0x332; - ADC2BUF0 = 0x340; -_ADC2BUF0 = 0x340; - AD2CON1 = 0x360; -_AD2CON1 = 0x360; -_AD2CON1bits = 0x360; - AD2CON2 = 0x362; -_AD2CON2 = 0x362; -_AD2CON2bits = 0x362; - AD2CON3 = 0x364; -_AD2CON3 = 0x364; -_AD2CON3bits = 0x364; - AD2CHS123 = 0x366; -_AD2CHS123 = 0x366; -_AD2CHS123bits = 0x366; - AD2CHS0 = 0x368; -_AD2CHS0 = 0x368; -_AD2CHS0bits = 0x368; - AD2PCFGL = 0x36C; -_AD2PCFGL = 0x36C; -_AD2PCFGLbits = 0x36C; - AD2CSSL = 0x370; -_AD2CSSL = 0x370; -_AD2CSSLbits = 0x370; - AD2CON4 = 0x372; -_AD2CON4 = 0x372; -_AD2CON4bits = 0x372; - DMA0CON = 0x380; -_DMA0CON = 0x380; -_DMA0CONbits = 0x380; - DMA0REQ = 0x382; -_DMA0REQ = 0x382; -_DMA0REQbits = 0x382; - DMA0STA = 0x384; -_DMA0STA = 0x384; - DMA0STB = 0x386; -_DMA0STB = 0x386; - DMA0PAD = 0x388; -_DMA0PAD = 0x388; - DMA0CNT = 0x38A; -_DMA0CNT = 0x38A; - DMA1CON = 0x38C; -_DMA1CON = 0x38C; -_DMA1CONbits = 0x38C; - DMA1REQ = 0x38E; -_DMA1REQ = 0x38E; -_DMA1REQbits = 0x38E; - DMA1STA = 0x390; -_DMA1STA = 0x390; - DMA1STB = 0x392; -_DMA1STB = 0x392; - DMA1PAD = 0x394; -_DMA1PAD = 0x394; - DMA1CNT = 0x396; -_DMA1CNT = 0x396; - DMA2CON = 0x398; -_DMA2CON = 0x398; -_DMA2CONbits = 0x398; - DMA2REQ = 0x39A; -_DMA2REQ = 0x39A; -_DMA2REQbits = 0x39A; - DMA2STA = 0x39C; -_DMA2STA = 0x39C; - DMA2STB = 0x39E; -_DMA2STB = 0x39E; - DMA2PAD = 0x3A0; -_DMA2PAD = 0x3A0; - DMA2CNT = 0x3A2; -_DMA2CNT = 0x3A2; - DMA3CON = 0x3A4; -_DMA3CON = 0x3A4; -_DMA3CONbits = 0x3A4; - DMA3REQ = 0x3A6; -_DMA3REQ = 0x3A6; -_DMA3REQbits = 0x3A6; - DMA3STA = 0x3A8; -_DMA3STA = 0x3A8; - DMA3STB = 0x3AA; -_DMA3STB = 0x3AA; - DMA3PAD = 0x3AC; -_DMA3PAD = 0x3AC; - DMA3CNT = 0x3AE; -_DMA3CNT = 0x3AE; - DMA4CON = 0x3B0; -_DMA4CON = 0x3B0; -_DMA4CONbits = 0x3B0; - DMA4REQ = 0x3B2; -_DMA4REQ = 0x3B2; -_DMA4REQbits = 0x3B2; - DMA4STA = 0x3B4; -_DMA4STA = 0x3B4; - DMA4STB = 0x3B6; -_DMA4STB = 0x3B6; - DMA4PAD = 0x3B8; -_DMA4PAD = 0x3B8; - DMA4CNT = 0x3BA; -_DMA4CNT = 0x3BA; - DMA5CON = 0x3BC; -_DMA5CON = 0x3BC; -_DMA5CONbits = 0x3BC; - DMA5REQ = 0x3BE; -_DMA5REQ = 0x3BE; -_DMA5REQbits = 0x3BE; - DMA5STA = 0x3C0; -_DMA5STA = 0x3C0; - DMA5STB = 0x3C2; -_DMA5STB = 0x3C2; - DMA5PAD = 0x3C4; -_DMA5PAD = 0x3C4; - DMA5CNT = 0x3C6; -_DMA5CNT = 0x3C6; - DMA6CON = 0x3C8; -_DMA6CON = 0x3C8; -_DMA6CONbits = 0x3C8; - DMA6REQ = 0x3CA; -_DMA6REQ = 0x3CA; -_DMA6REQbits = 0x3CA; - DMA6STA = 0x3CC; -_DMA6STA = 0x3CC; - DMA6STB = 0x3CE; -_DMA6STB = 0x3CE; - DMA6PAD = 0x3D0; -_DMA6PAD = 0x3D0; - DMA6CNT = 0x3D2; -_DMA6CNT = 0x3D2; - DMA7CON = 0x3D4; -_DMA7CON = 0x3D4; -_DMA7CONbits = 0x3D4; - DMA7REQ = 0x3D6; -_DMA7REQ = 0x3D6; -_DMA7REQbits = 0x3D6; - DMA7STA = 0x3D8; -_DMA7STA = 0x3D8; - DMA7STB = 0x3DA; -_DMA7STB = 0x3DA; - DMA7PAD = 0x3DC; -_DMA7PAD = 0x3DC; - DMA7CNT = 0x3DE; -_DMA7CNT = 0x3DE; - DMACS0 = 0x3E0; -_DMACS0 = 0x3E0; -_DMACS0bits = 0x3E0; - DMACS1 = 0x3E2; -_DMACS1 = 0x3E2; -_DMACS1bits = 0x3E2; - DSADR = 0x3E4; -_DSADR = 0x3E4; - C1CTRL1 = 0x400; -_C1CTRL1 = 0x400; -_C1CTRL1bits = 0x400; - C1CTRL2 = 0x402; -_C1CTRL2 = 0x402; -_C1CTRL2bits = 0x402; - C1VEC = 0x404; -_C1VEC = 0x404; -_C1VECbits = 0x404; - C1FCTRL = 0x406; -_C1FCTRL = 0x406; -_C1FCTRLbits = 0x406; - C1FIFO = 0x408; -_C1FIFO = 0x408; -_C1FIFObits = 0x408; - C1INTF = 0x40A; -_C1INTF = 0x40A; -_C1INTFbits = 0x40A; - C1INTE = 0x40C; -_C1INTE = 0x40C; -_C1INTEbits = 0x40C; - C1EC = 0x40E; -_C1EC = 0x40E; -_C1ECbits = 0x40E; - C1RERRCNT = 0x40E; -_C1RERRCNT = 0x40E; - C1TERRCNT = 0x40F; -_C1TERRCNT = 0x40F; - C1CFG1 = 0x410; -_C1CFG1 = 0x410; -_C1CFG1bits = 0x410; - C1CFG2 = 0x412; -_C1CFG2 = 0x412; -_C1CFG2bits = 0x412; - C1FEN1 = 0x414; -_C1FEN1 = 0x414; -_C1FEN1bits = 0x414; - C1FMSKSEL1 = 0x418; -_C1FMSKSEL1 = 0x418; -_C1FMSKSEL1bits = 0x418; - C1FMSKSEL2 = 0x41A; -_C1FMSKSEL2 = 0x41A; -_C1FMSKSEL2bits = 0x41A; - C1BUFPNT1 = 0x420; -_C1BUFPNT1 = 0x420; -_C1BUFPNT1bits = 0x420; - C1RXFUL1 = 0x420; -_C1RXFUL1 = 0x420; -_C1RXFUL1bits = 0x420; - C1BUFPNT2 = 0x422; -_C1BUFPNT2 = 0x422; -_C1BUFPNT2bits = 0x422; - C1RXFUL2 = 0x422; -_C1RXFUL2 = 0x422; -_C1RXFUL2bits = 0x422; - C1BUFPNT3 = 0x424; -_C1BUFPNT3 = 0x424; -_C1BUFPNT3bits = 0x424; - C1BUFPNT4 = 0x426; -_C1BUFPNT4 = 0x426; -_C1BUFPNT4bits = 0x426; - C1RXOVF1 = 0x428; -_C1RXOVF1 = 0x428; -_C1RXOVF1bits = 0x428; - C1RXOVF2 = 0x42A; -_C1RXOVF2 = 0x42A; -_C1RXOVF2bits = 0x42A; - C1RXM0SID = 0x430; -_C1RXM0SID = 0x430; -_C1RXM0SIDbits = 0x430; - C1TR01CON = 0x430; -_C1TR01CON = 0x430; -_C1TR01CONbits = 0x430; - C1RXM0EID = 0x432; -_C1RXM0EID = 0x432; -_C1RXM0EIDbits = 0x432; - C1TR23CON = 0x432; -_C1TR23CON = 0x432; -_C1TR23CONbits = 0x432; - C1RXM1SID = 0x434; -_C1RXM1SID = 0x434; -_C1RXM1SIDbits = 0x434; - C1TR45CON = 0x434; -_C1TR45CON = 0x434; -_C1TR45CONbits = 0x434; - C1RXM1EID = 0x436; -_C1RXM1EID = 0x436; -_C1RXM1EIDbits = 0x436; - C1TR67CON = 0x436; -_C1TR67CON = 0x436; -_C1TR67CONbits = 0x436; - C1RXM2SID = 0x438; -_C1RXM2SID = 0x438; -_C1RXM2SIDbits = 0x438; - C1RXM2EID = 0x43A; -_C1RXM2EID = 0x43A; -_C1RXM2EIDbits = 0x43A; - C1RXD = 0x440; -_C1RXD = 0x440; - C1RXF0SID = 0x440; -_C1RXF0SID = 0x440; -_C1RXF0SIDbits = 0x440; - C1RXF0EID = 0x442; -_C1RXF0EID = 0x442; -_C1RXF0EIDbits = 0x442; - C1TXD = 0x442; -_C1TXD = 0x442; - C1RXF1SID = 0x444; -_C1RXF1SID = 0x444; -_C1RXF1SIDbits = 0x444; - C1RXF1EID = 0x446; -_C1RXF1EID = 0x446; -_C1RXF1EIDbits = 0x446; - C1RXF2SID = 0x448; -_C1RXF2SID = 0x448; -_C1RXF2SIDbits = 0x448; - C1RXF2EID = 0x44A; -_C1RXF2EID = 0x44A; -_C1RXF2EIDbits = 0x44A; - C1RXF3SID = 0x44C; -_C1RXF3SID = 0x44C; -_C1RXF3SIDbits = 0x44C; - C1RXF3EID = 0x44E; -_C1RXF3EID = 0x44E; -_C1RXF3EIDbits = 0x44E; - C1RXF4SID = 0x450; -_C1RXF4SID = 0x450; -_C1RXF4SIDbits = 0x450; - C1RXF4EID = 0x452; -_C1RXF4EID = 0x452; -_C1RXF4EIDbits = 0x452; - C1RXF5SID = 0x454; -_C1RXF5SID = 0x454; -_C1RXF5SIDbits = 0x454; - C1RXF5EID = 0x456; -_C1RXF5EID = 0x456; -_C1RXF5EIDbits = 0x456; - C1RXF6SID = 0x458; -_C1RXF6SID = 0x458; -_C1RXF6SIDbits = 0x458; - C1RXF6EID = 0x45A; -_C1RXF6EID = 0x45A; -_C1RXF6EIDbits = 0x45A; - C1RXF7SID = 0x45C; -_C1RXF7SID = 0x45C; -_C1RXF7SIDbits = 0x45C; - C1RXF7EID = 0x45E; -_C1RXF7EID = 0x45E; -_C1RXF7EIDbits = 0x45E; - C1RXF8SID = 0x460; -_C1RXF8SID = 0x460; -_C1RXF8SIDbits = 0x460; - C1RXF8EID = 0x462; -_C1RXF8EID = 0x462; -_C1RXF8EIDbits = 0x462; - C1RXF9SID = 0x464; -_C1RXF9SID = 0x464; -_C1RXF9SIDbits = 0x464; - C1RXF9EID = 0x466; -_C1RXF9EID = 0x466; -_C1RXF9EIDbits = 0x466; - C1RXF10SID = 0x468; -_C1RXF10SID = 0x468; -_C1RXF10SIDbits = 0x468; - C1RXF10EID = 0x46A; -_C1RXF10EID = 0x46A; -_C1RXF10EIDbits = 0x46A; - C1RXF11SID = 0x46C; -_C1RXF11SID = 0x46C; -_C1RXF11SIDbits = 0x46C; - C1RXF11EID = 0x46E; -_C1RXF11EID = 0x46E; -_C1RXF11EIDbits = 0x46E; - C1RXF12SID = 0x470; -_C1RXF12SID = 0x470; -_C1RXF12SIDbits = 0x470; - C1RXF12EID = 0x472; -_C1RXF12EID = 0x472; -_C1RXF12EIDbits = 0x472; - C1RXF13SID = 0x474; -_C1RXF13SID = 0x474; -_C1RXF13SIDbits = 0x474; - C1RXF13EID = 0x476; -_C1RXF13EID = 0x476; -_C1RXF13EIDbits = 0x476; - C1RXF14SID = 0x478; -_C1RXF14SID = 0x478; -_C1RXF14SIDbits = 0x478; - C1RXF14EID = 0x47A; -_C1RXF14EID = 0x47A; -_C1RXF14EIDbits = 0x47A; - C1RXF15SID = 0x47C; -_C1RXF15SID = 0x47C; -_C1RXF15SIDbits = 0x47C; - C1RXF15EID = 0x47E; -_C1RXF15EID = 0x47E; -_C1RXF15EIDbits = 0x47E; - C2CTRL1 = 0x500; -_C2CTRL1 = 0x500; -_C2CTRL1bits = 0x500; - C2CTRL2 = 0x502; -_C2CTRL2 = 0x502; -_C2CTRL2bits = 0x502; - C2VEC = 0x504; -_C2VEC = 0x504; -_C2VECbits = 0x504; - C2FCTRL = 0x506; -_C2FCTRL = 0x506; -_C2FCTRLbits = 0x506; - C2FIFO = 0x508; -_C2FIFO = 0x508; -_C2FIFObits = 0x508; - C2INTF = 0x50A; -_C2INTF = 0x50A; -_C2INTFbits = 0x50A; - C2INTE = 0x50C; -_C2INTE = 0x50C; -_C2INTEbits = 0x50C; - C2EC = 0x50E; -_C2EC = 0x50E; -_C2ECbits = 0x50E; - C2RERRCNT = 0x50E; -_C2RERRCNT = 0x50E; - C2TERRCNT = 0x50F; -_C2TERRCNT = 0x50F; - C2CFG1 = 0x510; -_C2CFG1 = 0x510; -_C2CFG1bits = 0x510; - C2CFG2 = 0x512; -_C2CFG2 = 0x512; -_C2CFG2bits = 0x512; - C2FEN1 = 0x514; -_C2FEN1 = 0x514; -_C2FEN1bits = 0x514; - C2FMSKSEL1 = 0x518; -_C2FMSKSEL1 = 0x518; -_C2FMSKSEL1bits = 0x518; - C2FMSKSEL2 = 0x51A; -_C2FMSKSEL2 = 0x51A; -_C2FMSKSEL2bits = 0x51A; - C2BUFPNT1 = 0x520; -_C2BUFPNT1 = 0x520; -_C2BUFPNT1bits = 0x520; - C2RXFUL1 = 0x520; -_C2RXFUL1 = 0x520; -_C2RXFUL1bits = 0x520; - C2BUFPNT2 = 0x522; -_C2BUFPNT2 = 0x522; -_C2BUFPNT2bits = 0x522; - C2RXFUL2 = 0x522; -_C2RXFUL2 = 0x522; -_C2RXFUL2bits = 0x522; - C2BUFPNT3 = 0x524; -_C2BUFPNT3 = 0x524; -_C2BUFPNT3bits = 0x524; - C2BUFPNT4 = 0x526; -_C2BUFPNT4 = 0x526; -_C2BUFPNT4bits = 0x526; - C2RXOVF1 = 0x528; -_C2RXOVF1 = 0x528; -_C2RXOVF1bits = 0x528; - C2RXOVF2 = 0x52A; -_C2RXOVF2 = 0x52A; -_C2RXOVF2bits = 0x52A; - C2RXM0SID = 0x530; -_C2RXM0SID = 0x530; -_C2RXM0SIDbits = 0x530; - C2TR01CON = 0x530; -_C2TR01CON = 0x530; -_C2TR01CONbits = 0x530; - C2RXM0EID = 0x532; -_C2RXM0EID = 0x532; -_C2RXM0EIDbits = 0x532; - C2TR23CON = 0x532; -_C2TR23CON = 0x532; -_C2TR23CONbits = 0x532; - C2RXM1SID = 0x534; -_C2RXM1SID = 0x534; -_C2RXM1SIDbits = 0x534; - C2TR45CON = 0x534; -_C2TR45CON = 0x534; -_C2TR45CONbits = 0x534; - C2RXM1EID = 0x536; -_C2RXM1EID = 0x536; -_C2RXM1EIDbits = 0x536; - C2TR67CON = 0x536; -_C2TR67CON = 0x536; -_C2TR67CONbits = 0x536; - C2RXM2SID = 0x538; -_C2RXM2SID = 0x538; -_C2RXM2SIDbits = 0x538; - C2RXM2EID = 0x53A; -_C2RXM2EID = 0x53A; -_C2RXM2EIDbits = 0x53A; - C2RXD = 0x540; -_C2RXD = 0x540; - C2RXF0SID = 0x540; -_C2RXF0SID = 0x540; -_C2RXF0SIDbits = 0x540; - C2RXF0EID = 0x542; -_C2RXF0EID = 0x542; -_C2RXF0EIDbits = 0x542; - C2TXD = 0x542; -_C2TXD = 0x542; - C2RXF1SID = 0x544; -_C2RXF1SID = 0x544; -_C2RXF1SIDbits = 0x544; - C2RXF1EID = 0x546; -_C2RXF1EID = 0x546; -_C2RXF1EIDbits = 0x546; - C2RXF2SID = 0x548; -_C2RXF2SID = 0x548; -_C2RXF2SIDbits = 0x548; - C2RXF2EID = 0x54A; -_C2RXF2EID = 0x54A; -_C2RXF2EIDbits = 0x54A; - C2RXF3SID = 0x54C; -_C2RXF3SID = 0x54C; -_C2RXF3SIDbits = 0x54C; - C2RXF3EID = 0x54E; -_C2RXF3EID = 0x54E; -_C2RXF3EIDbits = 0x54E; - C2RXF4SID = 0x550; -_C2RXF4SID = 0x550; -_C2RXF4SIDbits = 0x550; - C2RXF4EID = 0x552; -_C2RXF4EID = 0x552; -_C2RXF4EIDbits = 0x552; - C2RXF5SID = 0x554; -_C2RXF5SID = 0x554; -_C2RXF5SIDbits = 0x554; - C2RXF5EID = 0x556; -_C2RXF5EID = 0x556; -_C2RXF5EIDbits = 0x556; - C2RXF6SID = 0x558; -_C2RXF6SID = 0x558; -_C2RXF6SIDbits = 0x558; - C2RXF6EID = 0x55A; -_C2RXF6EID = 0x55A; -_C2RXF6EIDbits = 0x55A; - C2RXF7SID = 0x55C; -_C2RXF7SID = 0x55C; -_C2RXF7SIDbits = 0x55C; - C2RXF7EID = 0x55E; -_C2RXF7EID = 0x55E; -_C2RXF7EIDbits = 0x55E; - C2RXF8SID = 0x560; -_C2RXF8SID = 0x560; -_C2RXF8SIDbits = 0x560; - C2RXF8EID = 0x562; -_C2RXF8EID = 0x562; -_C2RXF8EIDbits = 0x562; - C2RXF9SID = 0x564; -_C2RXF9SID = 0x564; -_C2RXF9SIDbits = 0x564; - C2RXF9EID = 0x566; -_C2RXF9EID = 0x566; -_C2RXF9EIDbits = 0x566; - C2RXF10SID = 0x568; -_C2RXF10SID = 0x568; -_C2RXF10SIDbits = 0x568; - C2RXF10EID = 0x56A; -_C2RXF10EID = 0x56A; -_C2RXF10EIDbits = 0x56A; - C2RXF11SID = 0x56C; -_C2RXF11SID = 0x56C; -_C2RXF11SIDbits = 0x56C; - C2RXF11EID = 0x56E; -_C2RXF11EID = 0x56E; -_C2RXF11EIDbits = 0x56E; - C2RXF12SID = 0x570; -_C2RXF12SID = 0x570; -_C2RXF12SIDbits = 0x570; - C2RXF12EID = 0x572; -_C2RXF12EID = 0x572; -_C2RXF12EIDbits = 0x572; - C2RXF13SID = 0x574; -_C2RXF13SID = 0x574; -_C2RXF13SIDbits = 0x574; - C2RXF13EID = 0x576; -_C2RXF13EID = 0x576; -_C2RXF13EIDbits = 0x576; - C2RXF14SID = 0x578; -_C2RXF14SID = 0x578; -_C2RXF14SIDbits = 0x578; - C2RXF14EID = 0x57A; -_C2RXF14EID = 0x57A; -_C2RXF14EIDbits = 0x57A; - C2RXF15SID = 0x57C; -_C2RXF15SID = 0x57C; -_C2RXF15SIDbits = 0x57C; - C2RXF15EID = 0x57E; -_C2RXF15EID = 0x57E; -_C2RXF15EIDbits = 0x57E; - ODCA = 0x6C0; -_ODCA = 0x6C0; -_ODCAbits = 0x6C0; - ODCD = 0x6D2; -_ODCD = 0x6D2; -_ODCDbits = 0x6D2; - ODCF = 0x6DE; -_ODCF = 0x6DE; -_ODCFbits = 0x6DE; - ODCG = 0x6E4; -_ODCG = 0x6E4; -_ODCGbits = 0x6E4; - RCON = 0x740; -_RCON = 0x740; -_RCONbits = 0x740; - OSCCON = 0x742; -_OSCCON = 0x742; -_OSCCONbits = 0x742; - CLKDIV = 0x744; -_CLKDIV = 0x744; -_CLKDIVbits = 0x744; - PLLFBD = 0x746; -_PLLFBD = 0x746; -_PLLFBDbits = 0x746; - OSCTUN = 0x748; -_OSCTUN = 0x748; -_OSCTUNbits = 0x748; - BSRAM = 0x750; -_BSRAM = 0x750; -_BSRAMbits = 0x750; - SSRAM = 0x752; -_SSRAM = 0x752; -_SSRAMbits = 0x752; - NVMCON = 0x760; -_NVMCON = 0x760; -_NVMCONbits = 0x760; - NVMKEY = 0x766; -_NVMKEY = 0x766; - PMD1 = 0x770; -_PMD1 = 0x770; -_PMD1bits = 0x770; - PMD2 = 0x772; -_PMD2 = 0x772; -_PMD2bits = 0x772; - PMD3 = 0x774; -_PMD3 = 0x774; -_PMD3bits = 0x774; diff --git a/Demo/dsPIC_MPLAB/serial/serial.c b/Demo/dsPIC_MPLAB/serial/serial.c deleted file mode 100644 index 78771ff5d..000000000 --- a/Demo/dsPIC_MPLAB/serial/serial.c +++ /dev/null @@ -1,234 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER. - -NOTE: This driver is primarily to test the scheduler functionality. It does -not effectively use the buffers or DMA and is therefore not intended to be -an example of an efficient driver. */ - -/* Standard include file. */ -#include - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "queue.h" -#include "task.h" - -/* Demo app include files. */ -#include "serial.h" - -/* Hardware setup. */ -#define serOUTPUT 0 -#define serINPUT 1 -#define serLOW_SPEED 0 -#define serONE_STOP_BIT 0 -#define serEIGHT_DATA_BITS_NO_PARITY 0 -#define serNORMAL_IDLE_STATE 0 -#define serAUTO_BAUD_OFF 0 -#define serLOOPBACK_OFF 0 -#define serWAKE_UP_DISABLE 0 -#define serNO_HARDWARE_FLOW_CONTROL 0 -#define serSTANDARD_IO 0 -#define serNO_IRDA 0 -#define serCONTINUE_IN_IDLE_MODE 0 -#define serUART_ENABLED 1 -#define serINTERRUPT_ON_SINGLE_CHAR 0 -#define serTX_ENABLE 1 -#define serINTERRUPT_ENABLE 1 -#define serINTERRUPT_DISABLE 0 -#define serCLEAR_FLAG 0 -#define serSET_FLAG 1 - - -/* The queues used to communicate between tasks and ISR's. */ -static xQueueHandle xRxedChars; -static xQueueHandle xCharsForTx; - -static portBASE_TYPE xTxHasEnded; -/*-----------------------------------------------------------*/ - -xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) -{ -portCHAR cChar; - - /* Create the queues used by the com test task. */ - xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); - xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); - - /* Setup the UART. */ - U2MODEbits.BRGH = serLOW_SPEED; - U2MODEbits.STSEL = serONE_STOP_BIT; - U2MODEbits.PDSEL = serEIGHT_DATA_BITS_NO_PARITY; - U2MODEbits.ABAUD = serAUTO_BAUD_OFF; - U2MODEbits.LPBACK = serLOOPBACK_OFF; - U2MODEbits.WAKE = serWAKE_UP_DISABLE; - U2MODEbits.UEN = serNO_HARDWARE_FLOW_CONTROL; - U2MODEbits.IREN = serNO_IRDA; - U2MODEbits.USIDL = serCONTINUE_IN_IDLE_MODE; - U2MODEbits.UARTEN = serUART_ENABLED; - - U2BRG = (unsigned portSHORT)(( (float)configCPU_CLOCK_HZ / ( (float)16 * (float)ulWantedBaud ) ) - (float)0.5); - - U2STAbits.URXISEL = serINTERRUPT_ON_SINGLE_CHAR; - U2STAbits.UTXEN = serTX_ENABLE; - U2STAbits.UTXINV = serNORMAL_IDLE_STATE; - U2STAbits.UTXISEL0 = serINTERRUPT_ON_SINGLE_CHAR; - U2STAbits.UTXISEL1 = serINTERRUPT_ON_SINGLE_CHAR; - - /* It is assumed that this function is called prior to the scheduler being - started. Therefore interrupts must not be allowed to occur yet as they - may attempt to perform a context switch. */ - portDISABLE_INTERRUPTS(); - - IFS1bits.U2RXIF = serCLEAR_FLAG; - IFS1bits.U2TXIF = serCLEAR_FLAG; - IPC7bits.U2RXIP = portKERNEL_INTERRUPT_PRIORITY; - IPC7bits.U2TXIP = portKERNEL_INTERRUPT_PRIORITY; - IEC1bits.U2TXIE = serINTERRUPT_ENABLE; - IEC1bits.U2RXIE = serINTERRUPT_ENABLE; - - /* Clear the Rx buffer. */ - while( U2STAbits.URXDA == serSET_FLAG ) - { - cChar = U2RXREG; - } - - xTxHasEnded = pdTRUE; - - return NULL; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) -{ - /* Only one port is supported. */ - ( void ) pxPort; - - /* Get the next character from the buffer. Return false if no characters - are available or arrive before xBlockTime expires. */ - if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) - { - return pdTRUE; - } - else - { - return pdFALSE; - } -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) -{ - /* Only one port is supported. */ - ( void ) pxPort; - - /* Return false if after the block time there is no room on the Tx queue. */ - if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) - { - return pdFAIL; - } - - /* A critical section should not be required as xTxHasEnded will not be - written to by the ISR if it is already 0 (is this correct?). */ - if( xTxHasEnded ) - { - xTxHasEnded = pdFALSE; - IFS1bits.U2TXIF = serSET_FLAG; - } - - return pdPASS; -} -/*-----------------------------------------------------------*/ - -void vSerialClose( xComPortHandle xPort ) -{ -} -/*-----------------------------------------------------------*/ - -volatile short s = 0; -char c[80] = {0}; - -void __attribute__((__interrupt__)) _U2RXInterrupt( void ) -{ -portCHAR cChar; -portBASE_TYPE xYieldRequired = pdFALSE; - - /* Get the character and post it on the queue of Rxed characters. - If the post causes a task to wake force a context switch as the woken task - may have a higher priority than the task we have interrupted. */ - IFS1bits.U2RXIF = serCLEAR_FLAG; - while( U2STAbits.URXDA ) - { - cChar = U2RXREG; - xYieldRequired = xQueueSendFromISR( xRxedChars, &cChar, xYieldRequired ); - } - - if( xYieldRequired != pdFALSE ) - { - taskYIELD(); - } -} -/*-----------------------------------------------------------*/ - -void __attribute__((__interrupt__)) _U2TXInterrupt( void ) -{ -signed portCHAR cChar; -portBASE_TYPE xTaskWoken = pdFALSE; - - /* If the transmit buffer is full we cannot get the next character. - Another interrupt will occur the next time there is space so this does - not matter. */ - IFS1bits.U2TXIF = serCLEAR_FLAG; - while( !( U2STAbits.UTXBF ) ) - { - if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWoken ) == pdTRUE ) - { - /* Send the next character queued for Tx. */ - U2TXREG = cChar; - } - else - { - /* Queue empty, nothing to send. */ - xTxHasEnded = pdTRUE; - break; - } - } - - if( xTaskWoken != pdFALSE ) - { - taskYIELD(); - } -} - - diff --git a/Demo/lwIP_Demo_Rowley_ARM7/AT91SAM7S256_MemoryMap.xml b/Demo/lwIP_Demo_Rowley_ARM7/AT91SAM7S256_MemoryMap.xml deleted file mode 100644 index a8d8820fb..000000000 --- a/Demo/lwIP_Demo_Rowley_ARM7/AT91SAM7S256_MemoryMap.xml +++ /dev/null @@ -1,3038 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Demo/lwIP_Demo_Rowley_ARM7/AT91SAM7_Startup.s b/Demo/lwIP_Demo_Rowley_ARM7/AT91SAM7_Startup.s deleted file mode 100644 index ba5c46218..000000000 --- a/Demo/lwIP_Demo_Rowley_ARM7/AT91SAM7_Startup.s +++ /dev/null @@ -1,173 +0,0 @@ -/***************************************************************************** - Exception handlers and startup code for ATMEL AT91SAM7. - - Copyright (c) 2004 Rowley Associates Limited. - - This file may be distributed under the terms of the License Agreement - provided with this software. - - THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE - WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. - *****************************************************************************/ - -#define REG_BASE 0xFFFFF000 -#define CKGR_MOR_OFFSET 0xC20 -#define CKGR_PLLR_OFFSET 0xC2C -#define PMC_MCKR_OFFSET 0xC30 -#define PMC_SR_OFFSET 0xC68 -#define WDT_MR_OFFSET 0xD44 -#define MC_RCR_OFFSET 0xF00 -#define MC_FMR_OFFSET 0xF60 - -#define CKGR_MOR_MOSCEN (1 << 0) -#define CKGR_MOR_OSCBYPASS (1 << 1) -#define CKGR_MOR_OSCOUNT_BIT_OFFSET (8) - -#define CKGR_PLLR_DIV_BIT_OFFSET (0) -#define CKGR_PLLR_PLLCOUNT_BIT_OFFSET (8) -#define CKGR_PLLR_OUT_BIT_OFFSET (14) -#define CKGR_PLLR_MUL_BIT_OFFSET (16) -#define CKGR_PLLR_USBDIV_BIT_OFFSET (28) - -#define PMC_MCKR_CSS_MAIN_CLOCK (0x1) -#define PMC_MCKR_CSS_PLL_CLOCK (0x3) -#define PMC_MCKR_PRES_CLK (0) -#define PMC_MCKR_PRES_CLK_2 (1 << 2) -#define PMC_MCKR_PRES_CLK_4 (2 << 2) -#define PMC_MCKR_PRES_CLK_8 (3 << 2) -#define PMC_MCKR_PRES_CLK_16 (4 << 2) -#define PMC_MCKR_PRES_CLK_32 (5 << 2) -#define PMC_MCKR_PRES_CLK_64 (6 << 2) - -#define PMC_SR_MOSCS (1 << 0) -#define PMC_SR_LOCK (1 << 2) -#define PMC_SR_MCKRDY (1 << 3) -#define PMC_SR_PCKRDY0 (1 << 8) -#define PMC_SR_PCKRDY1 (1 << 9) -#define PMC_SR_PCKRDY2 (1 << 10) - -#define MC_RCR_RCB (1 << 0) - -#define MC_FMR_FWS_0FWS (0) -#define MC_FMR_FWS_1FWS (1 << 8) -#define MC_FMR_FWS_2FWS (2 << 8) -#define MC_FMR_FWS_3FWS (3 << 8) -#define MC_FMR_FMCN_BIT_OFFSET 16 - -#define WDT_MR_WDDIS (1 << 15) - - .section .vectors, "ax" - .code 32 - .align 0 - -/***************************************************************************** - Exception Vectors - *****************************************************************************/ -_vectors: - ldr pc, [pc, #reset_handler_address - . - 8] /* reset */ - ldr pc, [pc, #undef_handler_address - . - 8] /* undefined instruction */ - ldr pc, [pc, #swi_handler_address - . - 8] /* swi handler */ - ldr pc, [pc, #pabort_handler_address - . - 8] /* abort prefetch */ - ldr pc, [pc, #dabort_handler_address - . - 8] /* abort data */ - nop - ldr pc, [PC, #-0xF20] /* irq */ - ldr pc, [pc, #fiq_handler_address - . - 8] /* fiq */ - -reset_handler_address: - .word reset_handler -undef_handler_address: - .word undef_handler -swi_handler_address: - .word swi_handler -pabort_handler_address: - .word pabort_handler -dabort_handler_address: - .word dabort_handler -irq_handler_address: - .word irq_handler -fiq_handler_address: - .word fiq_handler - - .section .init, "ax" - .code 32 - .align 0 - -/****************************************************************************** - Reset handler - ******************************************************************************/ -reset_handler: - - - ldr r10, =REG_BASE - - /* Set up FLASH wait state */ - ldr r0, =(50 << MC_FMR_FMCN_BIT_OFFSET) | MC_FMR_FWS_1FWS - str r0, [r10, #MC_FMR_OFFSET] - - /* Disable Watchdog */ - ldr r0, =WDT_MR_WDDIS - str r0, [r10, #WDT_MR_OFFSET] - - /* Enable the main oscillator */ - ldr r0, =(6 << CKGR_MOR_OSCOUNT_BIT_OFFSET) | CKGR_MOR_MOSCEN - str r0, [r10, #CKGR_MOR_OFFSET] - -1:/* Wait for main oscillator to stabilize */ - ldr r0, [r10, #PMC_SR_OFFSET] - tst r0, #PMC_SR_MOSCS - beq 1b - - /* Set up the PLL */ - ldr r0, =(5 << CKGR_PLLR_DIV_BIT_OFFSET) | (28 << CKGR_PLLR_PLLCOUNT_BIT_OFFSET) | (25 << CKGR_PLLR_MUL_BIT_OFFSET) - str r0, [r10, #CKGR_PLLR_OFFSET] - -1:/* Wait for PLL to lock */ - ldr r0, [r10, #PMC_SR_OFFSET] - tst r0, #PMC_SR_LOCK - beq 1b - - /* Select PLL as clock source */ - ldr r0, =(PMC_MCKR_CSS_PLL_CLOCK | PMC_MCKR_PRES_CLK_2) - str r0, [r10, #PMC_MCKR_OFFSET] - -#ifdef __FLASH_BUILD - /* Copy exception vectors into Internal SRAM */ - mov r8, #0x00200000 - ldr r9, =_vectors - ldmia r9!, {r0-r7} - stmia r8!, {r0-r7} - ldmia r9!, {r0-r6} - stmia r8!, {r0-r6} - - /* Remap Internal SRAM to 0x00000000 */ - ldr r0, =MC_RCR_RCB - strb r0, [r10, #MC_RCR_OFFSET] -#endif - - - /* Jump to the default C runtime startup code. */ - b _start - -/****************************************************************************** - Default exception handlers - (These are declared weak symbols so they can be redefined in user code) - ******************************************************************************/ -undef_handler: - b undef_handler - -swi_handler: - b swi_handler - -pabort_handler: - b pabort_handler - -dabort_handler: - b dabort_handler - -irq_handler: - b irq_handler - -fiq_handler: - b fiq_handler - - .weak undef_handler, swi_handler, pabort_handler, dabort_handler, irq_handler, fiq_handler diff --git a/Demo/lwIP_Demo_Rowley_ARM7/AT91SAM7_Target.js b/Demo/lwIP_Demo_Rowley_ARM7/AT91SAM7_Target.js deleted file mode 100644 index d7cbc435d..000000000 --- a/Demo/lwIP_Demo_Rowley_ARM7/AT91SAM7_Target.js +++ /dev/null @@ -1,61 +0,0 @@ -/****************************************************************************** - Target Script for ATMEL AT91SAM7. - - Copyright (c) 2004 Rowley Associates Limited. - - This file may be distributed under the terms of the License Agreement - provided with this software. - - THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE - WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. - ******************************************************************************/ - -function Reset() -{ - /* Reset and stop target */ - TargetInterface.pokeWord(0xFFFFFD00, 0xA500000D); // RSTC_CR - TargetInterface.waitForDebugState(1000); - /* Configure Clock */ - TargetInterface.pokeWord(0xFFFFFC20, 0x00000601); // CKGR_MOR - TargetInterface.delay(10); - TargetInterface.pokeWord(0xFFFFFC2C, 0x00191C05); // CKGR_PLLR - TargetInterface.delay(10); - TargetInterface.pokeWord(0xFFFFFC30, 0x00000007); // CKGR_MCKR - TargetInterface.delay(10); -} - -function RAMReset() -{ - Reset(); - /* Remap SRAM to 0x00000000 */ - TargetInterface.pokeWord(0xFFFFFF00, 1); // MC_RCR -} - -function FLASHReset() -{ - Reset(); - -// Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF; - - TargetInterface.pokeWord(0xffffffff,0xFFFFF124); - TargetInterface.pokeWord(0xffffffff,0xFFFFF128); -// disable peripheral clock Peripheral Clock Disable Register - TargetInterface.pokeWord(0xffffffff,0xFFFFFC14); - -// #define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register -// #define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register -// #define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register - TargetInterface.peekWord(0xFFFA0020); - TargetInterface.peekWord(0xFFFA0060); - TargetInterface.peekWord(0xFFFA00A0); - -// for (__mac_i=0;__mac_i < 8; __mac_i++) -// { - // AT91C_BASE_AIC->AIC_EOICR -// __mac_pt = TargetInterface.peekWord(0xFFFFF130); - -// } -// __message "------------------------------- AIC 2 INIT ---------------------------------------------"; - -} - diff --git a/Demo/lwIP_Demo_Rowley_ARM7/BasicWEB.c b/Demo/lwIP_Demo_Rowley_ARM7/BasicWEB.c deleted file mode 100644 index 1ff813228..000000000 --- a/Demo/lwIP_Demo_Rowley_ARM7/BasicWEB.c +++ /dev/null @@ -1,220 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - Implements a simplistic WEB server. Every time a connection is made and - data is received a dynamic page that shows the current TCP/IP statistics - is generated and returned. The connection is then closed. - - This file was adapted from a FreeRTOS lwIP slip demo supplied by a third - party. -*/ - -/* - Changes from V3.2.2 - - + Changed the page returned by the lwIP WEB server demo to display the - task status table rather than the TCP/IP statistics. -*/ - - -/* Standard includes. */ -#include -#include - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "semphr.h" - -/* Demo includes. */ -#include "BasicWEB.h" -#include "SAM7_EMAC.h" - -/* lwIP includes. */ -#include "lwip/api.h" -#include "lwip/tcpip.h" -#include "lwip/memp.h" -#include "lwip/stats.h" -#include "netif/loopif.h" - -/* The size of the buffer in which the dynamic WEB page is created. */ -#define webMAX_PAGE_SIZE 2048 - -/* Standard GET response. */ -#define webHTTP_OK "HTTP/1.0 200 OK\r\nContent-type: text/html\r\n\r\n" - -/* The port on which we listen. */ -#define webHTTP_PORT ( 80 ) - -/* Delay on close error. */ -#define webSHORT_DELAY ( 10 ) - -/* Format of the dynamic page that is returned on each connection. */ -#define webHTML_START \ -"\ -\ -\ -\ -\r\nPage Hits = " - -#define webHTML_END \ -"\r\n\ -\r\n\ -" - -/*------------------------------------------------------------*/ - -/* - * Process an incoming connection on port 80. - * - * This simply checks to see if the incoming data contains a GET request, and - * if so sends back a single dynamically created page. The connection is then - * closed. A more complete implementation could create a task for each - * connection. - */ -static void vProcessConnection( struct netconn *pxNetCon ); - -/*------------------------------------------------------------*/ - -static void vProcessConnection( struct netconn *pxNetCon ) -{ -static portCHAR cDynamicPage[ webMAX_PAGE_SIZE ], cPageHits[ 11 ]; -struct netbuf *pxRxBuffer; -portCHAR *pcRxString; -unsigned portSHORT usLength; -static unsigned portLONG ulPageHits = 0; - - /* We expect to immediately get data. */ - pxRxBuffer = netconn_recv( pxNetCon ); - - if( pxRxBuffer != NULL ) - { - /* Where is the data? */ - netbuf_data( pxRxBuffer, ( void * ) &pcRxString, &usLength ); - - /* Is this a GET? We don't handle anything else. */ - if( !strncmp( pcRxString, "GET", 3 ) ) - { - pcRxString = cDynamicPage; - - /* Update the hit count. */ - ulPageHits++; - sprintf( cPageHits, "%lu", ulPageHits ); - - /* Write out the HTTP OK header. */ - netconn_write(pxNetCon, webHTTP_OK, (u16_t)strlen( webHTTP_OK ), NETCONN_COPY ); - - /* Generate the dynamic page... - - ... First the page header. */ - strcpy( cDynamicPage, webHTML_START ); - /* ... Then the hit count... */ - strcat( cDynamicPage, cPageHits ); - strcat( cDynamicPage, "

Task          State  Priority  Stack	#
************************************************
" );
-			/* ... Then the list of tasks and their status... */
-			vTaskList( ( signed portCHAR * ) cDynamicPage + strlen( cDynamicPage ) );	
-			/* ... Finally the page footer. */
-			strcat( cDynamicPage, webHTML_END );
-
-			/* Write out the dynamically generated page. */
-			netconn_write(pxNetCon, cDynamicPage, (u16_t)strlen( cDynamicPage ), NETCONN_COPY );
-		}
- 
-		netbuf_delete( pxRxBuffer );
-	}
-
-	netconn_close( pxNetCon );
-}
-/*------------------------------------------------------------*/
-
-void vlwIPInit( void )
-{
-    /* Initialize lwIP and its interface layer. */
-	sys_init();
-	mem_init();								
-	memp_init();
-	pbuf_init(); 
-	netif_init();
-	ip_init();
-	tcpip_init( NULL, NULL );
-}
-/*------------------------------------------------------------*/
-
-void vBasicWEBServer( void *pvParameters )
-{
-struct netconn *pxHTTPListener, *pxNewConnection;
-struct ip_addr xIpAddr, xNetMast, xGateway;
-extern err_t ethernetif_init( struct netif *netif );
-static struct netif EMAC_if;
-
-	/* Parameters are not used - suppress compiler error. */
-	( void ) pvParameters;
-
-
-	/* Create and configure the EMAC interface. */
-	IP4_ADDR(&xIpAddr,emacIPADDR0,emacIPADDR1,emacIPADDR2,emacIPADDR3);
-	IP4_ADDR(&xNetMast,emacNET_MASK0,emacNET_MASK1,emacNET_MASK2,emacNET_MASK3);
-	IP4_ADDR(&xGateway,emacGATEWAY_ADDR0,emacGATEWAY_ADDR1,emacGATEWAY_ADDR2,emacGATEWAY_ADDR3);
-	netif_add(&EMAC_if, &xIpAddr, &xNetMast, &xGateway, NULL, ethernetif_init, tcpip_input);
-
-	/* make it the default interface */
-    netif_set_default(&EMAC_if);
-
-	/* bring it up */
-    netif_set_up(&EMAC_if);
-	
-	/* Create a new tcp connection handle */
-
- 	pxHTTPListener = netconn_new( NETCONN_TCP );
-	netconn_bind(pxHTTPListener, NULL, webHTTP_PORT );
-	netconn_listen( pxHTTPListener );
-
-	/* Loop forever */
-	for( ;; )
-	{
-		/* Wait for connection. */
-		pxNewConnection = netconn_accept(pxHTTPListener);
-
-		if(pxNewConnection != NULL)
-		{
-			/* Service connection. */
-			vProcessConnection( pxNewConnection );
-			while( netconn_delete( pxNewConnection ) != ERR_OK )
-			{
-				vTaskDelay( webSHORT_DELAY );
-			}
-		}
-	}
-}
-
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/BasicWEB.h b/Demo/lwIP_Demo_Rowley_ARM7/BasicWEB.h
deleted file mode 100644
index 6213c9bfa..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/BasicWEB.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
-	FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
-
-	This file is part of the FreeRTOS.org distribution.
-
-	FreeRTOS.org is free software; you can redistribute it and/or modify
-	it under the terms of the GNU General Public License as published by
-	the Free Software Foundation; either version 2 of the License, or
-	(at your option) any later version.
-
-	FreeRTOS.org is distributed in the hope that it will be useful,
-	but WITHOUT ANY WARRANTY; without even the implied warranty of
-	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-	GNU General Public License for more details.
-
-	You should have received a copy of the GNU General Public License
-	along with FreeRTOS.org; if not, write to the Free Software
-	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-
-	A special exception to the GPL can be applied should you wish to distribute
-	a combined work that includes FreeRTOS.org, without being obliged to provide
-	the source code for any proprietary components.  See the licensing section
-	of http://www.FreeRTOS.org for full details of how and when the exception
-	can be applied.
-
-	***************************************************************************
-	See http://www.FreeRTOS.org for documentation, latest information, license
-	and contact details.  Please ensure to read the configuration and relevant
-	port sections of the online documentation.
-	***************************************************************************
-*/
-
-#ifndef BASIC_WEB_SERVER_H
-#define BASIC_WEB_SERVER_H
-
-/* The function that implements the WEB server task. */
-void vBasicWEBServer( void *pvParameters );
-
-/* Initialisation required by lwIP. */
-void vlwIPInit( void );
-
-#endif
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/Board.h b/Demo/lwIP_Demo_Rowley_ARM7/Board.h
deleted file mode 100644
index f3ae3c11d..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/Board.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/*----------------------------------------------------------------------------
-*         ATMEL Microcontroller Software Support  -  ROUSSET  -
-*----------------------------------------------------------------------------
-* The software is delivered "AS IS" without warranty or condition of any
-* kind, either express, implied or statutory. This includes without
-* limitation any warranty or condition with respect to merchantability or
-* fitness for any particular purpose, or against the infringements of
-* intellectual property rights of others.
-*----------------------------------------------------------------------------
-* File Name           : Board.h
-* Object              : AT91SAM7X Evaluation Board Features Definition File.
-*
-* Creation            : JG   20/Jun/2005
-*----------------------------------------------------------------------------
-*/
-#ifndef Board_h
-#define Board_h
-
-#include "AT91SAM7X256.h"
-#include "ioat91sam7x256.h"
-
-#define true	-1
-#define false	0
-
-/*-------------------------------*/
-/* SAM7Board Memories Definition */
-/*-------------------------------*/
-// The AT91SAM7X128 embeds a 32-Kbyte SRAM bank, and 128K-Byte Flash
-
-#define  FLASH_PAGE_NB		256
-#define  FLASH_PAGE_SIZE	128
-
-/*-----------------*/
-/* Leds Definition */
-/*-----------------*/
-#define LED1            (1<<19)	// PB19
-#define LED2            (1<<20)	// PB20
-#define LED3            (1<<21)	// PB21
-#define LED4            (1<<22)	// PB22
-#define NB_LED			4
-
-#define LED_MASK        (LED1|LED2|LED3|LED4)
-
-/*-------------------------*/
-/* Push Buttons Definition */
-/*-------------------------*/
-
-#define SW1_MASK        (1<<21)	// PA21
-#define SW2_MASK        (1<<22)	// PA22
-#define SW3_MASK        (1<<23)	// PA23
-#define SW4_MASK        (1<<24)	// PA24
-#define SW_MASK         (SW1_MASK|SW2_MASK|SW3_MASK|SW4_MASK)
-
-
-#define SW1 	(1<<21)	// PA21
-#define SW2 	(1<<22)	// PA22
-#define SW3 	(1<<23)	// PA23
-#define SW4 	(1<<24)	// PA24
-
-/*--------------*/
-/* Master Clock */
-/*--------------*/
-
-#define EXT_OC          18432000   // Exetrnal ocilator MAINCK
-#define MCK             47923200   // MCK (PLLRC div by 2)
-#define MCKKHz          (MCK/1000) //
-
-#endif /* Board_h */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/Cstartup_SAM7.c b/Demo/lwIP_Demo_Rowley_ARM7/Cstartup_SAM7.c
deleted file mode 100644
index d9716c0ef..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/Cstartup_SAM7.c
+++ /dev/null
@@ -1,69 +0,0 @@
-//*----------------------------------------------------------------------------
-//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
-//*----------------------------------------------------------------------------
-//* The software is delivered "AS IS" without warranty or condition of any
-//* kind, either express, implied or statutory. This includes without
-//* limitation any warranty or condition with respect to merchantability or
-//* fitness for any particular purpose, or against the infringements of
-//* intellectual property rights of others.
-//*----------------------------------------------------------------------------
-//* File Name           : Cstartup_SAM7.c
-//* Object              : Low level initializations written in C for IAR
-//*                       tools
-//* 1.0   08/Sep/04 JPP	: Creation
-//* 1.10  10/Sep/04 JPP : Update AT91C_CKGR_PLLCOUNT filed
-//*----------------------------------------------------------------------------
-
-
-// Include the board file description
-#include "Board.h"
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_LowLevelInit
-//* \brief This function performs very low level HW initialization
-//*        this function can be use a Stack, depending the compilation
-//*        optimization mode
-//*----------------------------------------------------------------------------
-void AT91F_LowLevelInit( void);
-void AT91F_LowLevelInit( void )
-{
- AT91PS_PMC     pPMC = AT91C_BASE_PMC;
-
-    //* Set Flash Waite sate
-	//  Single Cycle Access at Up to 30 MHz, or 40
-	//  if MCK = 47923200 I have 50 Cycle for 1 useconde ( flied MC_FMR->FMCN
-	    AT91C_BASE_MC->MC_FMR = ((AT91C_MC_FMCN)&(75 <<16)) | AT91C_MC_FWS_1FWS ;
-
-    //* Watchdog Disable
-        AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS;
-
-	//* Set MCK at 47 923 200
-    // 1 Enabling the Main Oscillator:
-        // SCK = 1/32768 = 30.51 uSeconde
-    	// Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms
-       pPMC->PMC_MOR = ((( AT91C_CKGR_OSCOUNT & (0x06 <<8)) | AT91C_CKGR_MOSCEN ));
-        // Wait the startup time
-        while(!(pPMC->PMC_SR & AT91C_PMC_MOSCS));
-	// 2 Checking the Main Oscillator Frequency (Optional)
-	// 3 Setting PLL and divider:
-		// - div by 5 Fin = 3,6864 =(18,432 / 5)
-		// - Mul 25+1: Fout =	95,8464 =(3,6864 *26)
-		// for 96 MHz the erroe is 0.16%
-		//eld out NOT USED = 0 Fi
-       pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 5) |
-                         (AT91C_CKGR_PLLCOUNT & (28<<8)) |
-                         (AT91C_CKGR_MUL & (25<<16)));
-
-        // Wait the startup time
-        while(!(pPMC->PMC_SR & AT91C_PMC_LOCK));
-	// 4. Selection of Master Clock and Processor Clock
-        // select the PLL clock divided by 2
-       pPMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2 ;
-        while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
-
-        pPMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK ;
-        while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
-}
-
-
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/EMAC/Emac.h b/Demo/lwIP_Demo_Rowley_ARM7/EMAC/Emac.h
deleted file mode 100644
index 6523e6868..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/EMAC/Emac.h
+++ /dev/null
@@ -1,117 +0,0 @@
-//*----------------------------------------------------------------------------
-//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
-//*----------------------------------------------------------------------------
-//* The software is delivered "AS IS" without warranty or condition of any
-//* kind, either express, implied or statutory. This includes without
-//* limitation any warranty or condition with respect to merchantability or
-//* fitness for any particular purpose, or against the infringements of
-//* intellectual property rights of others.
-//*----------------------------------------------------------------------------
-//* File Name           : Emac.h
-//* Object              : Emac header file
-//* Creation            : Hi   11/18/2002
-//*
-//*----------------------------------------------------------------------------
-#ifndef AT91C_EMAC_H
-#define AT91C_EMAC_H
-
-#include "lwipopts.h"
-
-
-/* Number of receive buffers */
-#define NB_RX_BUFFERS			20
-
-/* Size of each receive buffer - DO NOT CHANGE. */
-#define ETH_RX_BUFFER_SIZE		128         
-
-/* Number of Transmit buffers */
-#define NB_TX_BUFFERS			( MEMP_NUM_PBUF / 2 )	
-
-/* Size of each Transmit buffer. */
-#define ETH_TX_BUFFER_SIZE		( PBUF_POOL_BUFSIZE  )   
-
-/* Receive Transfer descriptor structure */
-typedef struct  _AT91S_RxTdDescriptor {
-	unsigned int addr;
-	union
-	{
-		unsigned int status;
-		struct {
-			unsigned int Length:11;
-			unsigned int Res0:1;
-			unsigned int Rxbuf_off:2;
-			unsigned int StartOfFrame:1;
-			unsigned int EndOfFrame:1;
-			unsigned int Cfi:1;
-			unsigned int VlanPriority:3;
-			unsigned int PriorityTag:1;
-			unsigned int VlanTag:1;
-			unsigned int TypeID:1;
-			unsigned int Sa4Match:1;
-			unsigned int Sa3Match:1;
-			unsigned int Sa2Match:1;
-			unsigned int Sa1Match:1;
-			unsigned int Res1:1;
-			unsigned int ExternalAdd:1;
-			unsigned int UniCast:1;
-			unsigned int MultiCast:1;
-			unsigned int BroadCast:1;
-		}S_Status;		
-	}U_Status;
-}AT91S_RxTdDescriptor, *AT91PS_RxTdDescriptor;
-
-
-/* Transmit Transfer descriptor structure */
-typedef struct _AT91S_TxTdDescriptor {
-	unsigned int addr;
-	union
-	{
-		unsigned int status;
-		struct {
-			unsigned int Length:11;
-			unsigned int Res0:4;
-			unsigned int LastBuff:1;
-			unsigned int NoCrc:1;
-			unsigned int Res1:10;
-			unsigned int BufExhausted:1;
-			unsigned int TransmitUnderrun:1;
-			unsigned int TransmitError:1;
-			unsigned int Wrap:1;
-			unsigned int BuffUsed:1;
-		}S_Status;		
-	}U_Status;
-}AT91S_TxTdDescriptor, *AT91PS_TxTdDescriptor;
-
-#define AT91C_OWNERSHIP_BIT		0x00000001
-
-/* Receive status defintion */
-#define AT91C_BROADCAST_ADDR	((unsigned int) (1 << 31))	//* Broadcat address detected
-#define AT91C_MULTICAST_HASH 	((unsigned int) (1 << 30))	//* MultiCast hash match
-#define AT91C_UNICAST_HASH 	    ((unsigned int) (1 << 29))	//* UniCast hash match
-#define AT91C_EXTERNAL_ADDR	    ((unsigned int) (1 << 28))	//* External Address match
-#define AT91C_SA1_ADDR	    	((unsigned int) (1 << 26))	//* Specific address 1 match
-#define AT91C_SA2_ADDR	    	((unsigned int) (1 << 25))	//* Specific address 2 match
-#define AT91C_SA3_ADDR	    	((unsigned int) (1 << 24))	//* Specific address 3 match
-#define AT91C_SA4_ADDR	    	((unsigned int) (1 << 23))	//* Specific address 4 match
-#define AT91C_TYPE_ID	    	((unsigned int) (1 << 22))	//* Type ID match
-#define AT91C_VLAN_TAG	    	((unsigned int) (1 << 21))	//* VLAN tag detected
-#define AT91C_PRIORITY_TAG    	((unsigned int) (1 << 20))	//* PRIORITY tag detected
-#define AT91C_VLAN_PRIORITY    	((unsigned int) (7 << 17))  //* PRIORITY Mask
-#define AT91C_CFI_IND        	((unsigned int) (1 << 16))  //* CFI indicator
-#define AT91C_EOF           	((unsigned int) (1 << 15))  //* EOF
-#define AT91C_SOF           	((unsigned int) (1 << 14))  //* SOF
-#define AT91C_RBF_OFFSET     	((unsigned int) (3 << 12))  //* Receive Buffer Offset Mask
-#define AT91C_LENGTH_FRAME     	((unsigned int) 0x07FF)     //* Length of frame
-
-/* Transmit Status definition */
-#define AT91C_TRANSMIT_OK		((unsigned int) (1 << 31))	//*
-#define AT91C_TRANSMIT_WRAP		((unsigned int) (1 << 30))	//* Wrap bit: mark the last descriptor
-#define AT91C_TRANSMIT_ERR		((unsigned int) (1 << 29))	//* RLE:transmit error
-#define AT91C_TRANSMIT_UND		((unsigned int) (1 << 28))	//* Transmit Underrun
-#define AT91C_BUF_EX     		((unsigned int) (1 << 27))	//* Buffers exhausted in mid frame
-#define AT91C_TRANSMIT_NO_CRC	((unsigned int) (1 << 16))	//* No CRC will be appended to the current frame
-#define AT91C_LAST_BUFFER    	((unsigned int) (1 << 15))	//*
-
-#define AT91C_EMAC_CLKEN 0x2
-
-#endif //* AT91C_EMAC_H
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/EMAC/SAM7_EMAC.c b/Demo/lwIP_Demo_Rowley_ARM7/EMAC/SAM7_EMAC.c
deleted file mode 100644
index c2d530b7c..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/EMAC/SAM7_EMAC.c
+++ /dev/null
@@ -1,861 +0,0 @@
-/*
-	FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
-
-	This file is part of the FreeRTOS.org distribution.
-
-	FreeRTOS.org is free software; you can redistribute it and/or modify
-	it under the terms of the GNU General Public License as published by
-	the Free Software Foundation; either version 2 of the License, or
-	(at your option) any later version.
-
-	FreeRTOS.org is distributed in the hope that it will be useful,
-	but WITHOUT ANY WARRANTY; without even the implied warranty of
-	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-	GNU General Public License for more details.
-
-	You should have received a copy of the GNU General Public License
-	along with FreeRTOS.org; if not, write to the Free Software
-	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-
-	A special exception to the GPL can be applied should you wish to distribute
-	a combined work that includes FreeRTOS.org, without being obliged to provide
-	the source code for any proprietary components.  See the licensing section
-	of http://www.FreeRTOS.org for full details of how and when the exception
-	can be applied.
-
-	***************************************************************************
-	See http://www.FreeRTOS.org for documentation, latest information, license
-	and contact details.  Please ensure to read the configuration and relevant
-	port sections of the online documentation.
-	***************************************************************************
-*/
-
-/*
- * Interrupt driven driver for the EMAC peripheral.  This driver is not
- * reentrant, re-entrancy is handled by a semaphore at the network interface
- * level. 
- */
-
-
-/*
-Changes from V3.2.2
-
-	+ Corrected the byte order when writing the MAC address to the MAC.
-	+ Support added for MII interfaces.  Previously only RMII was supported.
-
-Changes from V3.2.3
-
-	+ The MII interface is now the default.
-	+ Modified the initialisation sequence slightly to allow auto init more
-	  time to complete.
-
-Changes from V4.0.1
-
-	+ Made the function vClearEMACTxBuffer() more robust by moving the index
-	  manipulation into the if() statement.  This allows the tx interrupt to
-	  execute even when there is no data to handle.
-
-Changes from V4.0.4
-
-	+ Corrected the Rx frame length mask when obtaining the length from the
-	  rx descriptor.
-*/
-
-
-/* Standard includes. */
-#include 
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "semphr.h"
-#include "task.h"
-
-/* Demo app includes. */
-#include "SAM7_EMAC.h"
-
-/* Hardware specific includes. */
-#include "Emac.h"
-#include "mii.h"
-#include "AT91SAM7X256.h"
-
-
-/* USE_RMII_INTERFACE must be defined as 1 to use an RMII interface, or 0
-to use an MII interface. */
-#define USE_RMII_INTERFACE 0
-
-
-/* The buffer addresses written into the descriptors must be aligned so the
-last few bits are zero.  These bits have special meaning for the EMAC
-peripheral and cannot be used as part of the address. */
-#define emacADDRESS_MASK			( ( unsigned portLONG ) 0xFFFFFFFC )
-
-/* Bit used within the address stored in the descriptor to mark the last
-descriptor in the array. */
-#define emacRX_WRAP_BIT				( ( unsigned portLONG ) 0x02 )
-
-/* Bit used within the Tx descriptor status to indicate whether the
-descriptor is under the control of the EMAC or the software. */
-#define emacTX_BUF_USED				( ( unsigned portLONG ) 0x80000000 )
-
-/* A short delay is used to wait for a buffer to become available, should
-one not be immediately available when trying to transmit a frame. */
-#define emacBUFFER_WAIT_DELAY		( 2 )
-#define emacMAX_WAIT_CYCLES			( ( portBASE_TYPE ) ( configTICK_RATE_HZ / 40 ) )
-
-/* The time to block waiting for input. */
-#define emacBLOCK_TIME_WAITING_FOR_INPUT	( ( portTickType ) 100 )
-
-/* Peripheral setup for the EMAC. */
-#define emacPERIPHERAL_A_SETUP 		( ( unsigned portLONG ) AT91C_PB2_ETX0			) | \
-									( ( unsigned portLONG ) AT91C_PB12_ETXER		) | \
-									( ( unsigned portLONG ) AT91C_PB16_ECOL			) | \
-									( ( unsigned portLONG ) AT91C_PB11_ETX3			) | \
-									( ( unsigned portLONG ) AT91C_PB6_ERX1			) | \
-									( ( unsigned portLONG ) AT91C_PB15_ERXDV		) | \
-									( ( unsigned portLONG ) AT91C_PB13_ERX2			) | \
-									( ( unsigned portLONG ) AT91C_PB3_ETX1			) | \
-									( ( unsigned portLONG ) AT91C_PB8_EMDC			) | \
-									( ( unsigned portLONG ) AT91C_PB5_ERX0			) | \
-									( ( unsigned portLONG ) AT91C_PB14_ERX3			) | \
-									( ( unsigned portLONG ) AT91C_PB4_ECRS_ECRSDV	) | \
-									( ( unsigned portLONG ) AT91C_PB1_ETXEN			) | \
-									( ( unsigned portLONG ) AT91C_PB10_ETX2			) | \
-									( ( unsigned portLONG ) AT91C_PB0_ETXCK_EREFCK	) | \
-									( ( unsigned portLONG ) AT91C_PB9_EMDIO			) | \
-									( ( unsigned portLONG ) AT91C_PB7_ERXER			) | \
-									( ( unsigned portLONG ) AT91C_PB17_ERXCK		);
-
-/* Misc defines. */
-#define emacINTERRUPT_LEVEL			( 5 )
-#define emacNO_DELAY				( 0 )
-#define emacTOTAL_FRAME_HEADER_SIZE	( 54 )
-#define emacPHY_INIT_DELAY			( 5000 / portTICK_RATE_MS )
-#define emacRESET_KEY				( ( unsigned portLONG ) 0xA5000000 )
-#define emacRESET_LENGTH			( ( unsigned portLONG ) ( 0x01 << 8 ) )
-
-/* The Atmel header file only defines the TX frame length mask. */
-#define emacRX_LENGTH_FRAME			( 0xfff )
-
-/*-----------------------------------------------------------*/
-
-/* Buffer written to by the EMAC DMA.  Must be aligned as described by the
-comment above the emacADDRESS_MASK definition. */
-static volatile portCHAR pcRxBuffer[ NB_RX_BUFFERS * ETH_RX_BUFFER_SIZE ] __attribute__ ((aligned (8)));
-
-/* Buffer read by the EMAC DMA.  Must be aligned as described by the comment
-above the emacADDRESS_MASK definition. */
-static portCHAR pcTxBuffer[ NB_TX_BUFFERS * ETH_TX_BUFFER_SIZE ] __attribute__ ((aligned (8)));
-
-/* Descriptors used to communicate between the program and the EMAC peripheral.
-These descriptors hold the locations and state of the Rx and Tx buffers. */
-static volatile AT91S_TxTdDescriptor xTxDescriptors[ NB_TX_BUFFERS ];
-static volatile AT91S_RxTdDescriptor xRxDescriptors[ NB_RX_BUFFERS ];
-
-/* The IP and Ethernet addresses are read from the header files. */
-const portCHAR cMACAddress[ 6 ] = { emacETHADDR0, emacETHADDR1, emacETHADDR2, emacETHADDR3, emacETHADDR4, emacETHADDR5 };
-const unsigned char ucIPAddress[ 4 ]  = { emacIPADDR0, emacIPADDR1, emacIPADDR2, emacIPADDR3 };
-
-/*-----------------------------------------------------------*/
-
-/* See the header file for descriptions of public functions. */
-
-/*
- * Prototype for the EMAC interrupt function - called by the asm wrapper.
- */
-void vEMACISR( void ) __attribute__ ((naked));
-
-/*
- * Initialise both the Tx and Rx descriptors used by the EMAC.
- */
-static void prvSetupDescriptors(void);
-
-/*
- * Write our MAC address into the EMAC.  
- */
-static void prvSetupMACAddress( void );
-
-/*
- * Configure the EMAC and AIC for EMAC interrupts.
- */
-static void prvSetupEMACInterrupt( void );
-
-/*
- * Some initialisation functions taken from the Atmel EMAC sample code.
- */
-static void vReadPHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG *pulValue );
-static portBASE_TYPE xGetLinkSpeed( void );
-static portBASE_TYPE prvProbePHY( void );
-#if USE_RMII_INTERFACE != 1
-	static void vWritePHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG ulValue);
-#endif
-
-
-/* The semaphore used by the EMAC ISR to wake the EMAC task. */
-static xSemaphoreHandle xSemaphore = NULL;
-
-/* Holds the index to the next buffer from which data will be read. */
-static volatile unsigned portLONG ulNextRxBuffer = 0;
-
-/*-----------------------------------------------------------*/
-
-/* See the header file for descriptions of public functions. */
-portLONG lEMACSend( portCHAR *pcFrom, unsigned portLONG ulLength, portLONG lEndOfFrame )
-{
-static unsigned portBASE_TYPE uxTxBufferIndex = 0;
-portBASE_TYPE xWaitCycles = 0;
-portLONG lReturn = pdPASS;
-portCHAR *pcBuffer;
-unsigned portLONG ulLastBuffer, ulDataBuffered = 0, ulDataRemainingToSend, ulLengthToSend;
-
-	/* If the length of data to be transmitted is greater than each individual
-	transmit buffer then the data will be split into more than one buffer.
-	Loop until the entire length has been buffered. */
-	while( ulDataBuffered < ulLength )
-	{
-		/* Is a buffer available? */
-		while( !( xTxDescriptors[ uxTxBufferIndex ].U_Status.status & AT91C_TRANSMIT_OK ) )
-		{
-			/* There is no room to write the Tx data to the Tx buffer.  Wait a
-			short while, then try again. */
-			xWaitCycles++;
-			if( xWaitCycles > emacMAX_WAIT_CYCLES )
-			{
-				/* Give up. */
-				lReturn = pdFAIL;
-				break;
-			}
-			else
-			{
-				vTaskDelay( emacBUFFER_WAIT_DELAY );
-			}
-		}
-	
-		/* lReturn will only be pdPASS if a buffer is available. */
-		if( lReturn == pdPASS )
-		{
-			portENTER_CRITICAL();
-			{
-				/* Get the address of the buffer from the descriptor, then copy 
-				the data into the buffer. */
-				pcBuffer = ( portCHAR * ) xTxDescriptors[ uxTxBufferIndex ].addr;
-
-				/* How much can we write to the buffer? */
-				ulDataRemainingToSend = ulLength - ulDataBuffered;
-				if( ulDataRemainingToSend <= ETH_TX_BUFFER_SIZE )
-				{
-					/* We can write all the remaining bytes. */
-					ulLengthToSend = ulDataRemainingToSend;
-				}
-				else
-				{
-					/* We can not write more than ETH_TX_BUFFER_SIZE in one go. */
-					ulLengthToSend = ETH_TX_BUFFER_SIZE;
-				}
-
-				/* Copy the data into the buffer. */
-				memcpy( ( void * ) pcBuffer, ( void * ) &( pcFrom[ ulDataBuffered ] ), ulLengthToSend );
-				ulDataBuffered += ulLengthToSend;
-
-				/* Is this the last data for the frame? */
-				if( lEndOfFrame && ( ulDataBuffered >= ulLength ) )
-				{
-					/* No more data remains for this frame so we can start the 
-					transmission. */
-					ulLastBuffer = AT91C_LAST_BUFFER;
-				}
-				else
-				{
-					/* More data to come for this frame. */
-					ulLastBuffer = 0;
-				}
-	
-				/* Fill out the necessary in the descriptor to get the data sent, 
-				then move to the next descriptor, wrapping if necessary. */
-				if( uxTxBufferIndex >= ( NB_TX_BUFFERS - 1 ) )
-				{				
-					xTxDescriptors[ uxTxBufferIndex ].U_Status.status = 	( ulLengthToSend & ( unsigned portLONG ) AT91C_LENGTH_FRAME )
-																			| ulLastBuffer
-																			| AT91C_TRANSMIT_WRAP;
-					uxTxBufferIndex = 0;
-				}
-				else
-				{
-					xTxDescriptors[ uxTxBufferIndex ].U_Status.status = 	( ulLengthToSend & ( unsigned portLONG ) AT91C_LENGTH_FRAME )
-																			| ulLastBuffer;
-					uxTxBufferIndex++;
-				}
-	
-				/* If this is the last buffer to be sent for this frame we can
-				start the transmission. */
-				if( ulLastBuffer )
-				{
-					AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART;
-				}
-			}
-			portEXIT_CRITICAL();
-		}
-		else
-		{
-			break;
-		}
-	}
-
-	return lReturn;
-}
-/*-----------------------------------------------------------*/
-
-/* See the header file for descriptions of public functions. */
-unsigned portLONG ulEMACInputLength( void )
-{
-register unsigned portLONG ulIndex, ulLength = 0;
-
-	/* Skip any fragments.  We are looking for the first buffer that contains
-	data and has the SOF (start of frame) bit set. */
-	while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !( xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_SOF ) )
-	{
-		/* Ignoring this buffer.  Mark it as free again. */
-		xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );		
-		ulNextRxBuffer++;
-		if( ulNextRxBuffer >= NB_RX_BUFFERS )
-		{
-			ulNextRxBuffer = 0;
-		}
-	}
-
-	/* We are going to walk through the descriptors that make up this frame, 
-	but don't want to alter ulNextRxBuffer as this would prevent vEMACRead()
-	from finding the data.  Therefore use a copy of ulNextRxBuffer instead. */
-	ulIndex = ulNextRxBuffer;
-
-	/* Walk through the descriptors until we find the last buffer for this 
-	frame.  The last buffer will give us the length of the entire frame. */
-	while( ( xRxDescriptors[ ulIndex ].addr & AT91C_OWNERSHIP_BIT ) && !ulLength )
-	{
-		ulLength = xRxDescriptors[ ulIndex ].U_Status.status & emacRX_LENGTH_FRAME;
-
-		/* Increment to the next buffer, wrapping if necessary. */
-		ulIndex++;
-		if( ulIndex >= NB_RX_BUFFERS )
-		{
-			ulIndex = 0;
-		}
-	}
-
-	return ulLength;
-}
-/*-----------------------------------------------------------*/
-
-/* See the header file for descriptions of public functions. */
-void vEMACRead( portCHAR *pcTo, unsigned portLONG ulSectionLength, unsigned portLONG ulTotalFrameLength )
-{
-static unsigned portLONG ulSectionBytesReadSoFar = 0, ulBufferPosition = 0, ulFameBytesReadSoFar = 0;
-static portCHAR *pcSource;
-register unsigned portLONG ulBytesRemainingInBuffer, ulRemainingSectionBytes;
-
-	/* Read ulSectionLength bytes from the Rx buffers.  This is not necessarily any
-	correspondence between the length of our Rx buffers, and the length of the
-	data we are returning or the length of the data being requested.  Therefore, 
-	between calls  we have to remember not only which buffer we are currently 
-	processing, but our position within that buffer.  This would be greatly
-	simplified if PBUF_POOL_BUFSIZE could be guaranteed to be greater than
-	the size of each Rx buffer, and that memory fragmentation did not occur.
-	
-	This function should only be called after a call to ulEMACInputLength().
-	This will ensure ulNextRxBuffer is set to the correct buffer. */
-
-
-
-	/* vEMACRead is called with pcTo set to NULL to indicate that we are about
-	to read a new frame.  Any fragments remaining in the frame we were 
-	processing during the last call should be dropped. */
-	if( pcTo == NULL )
-	{
-		/* How many bytes are indicated as being in this buffer?  If none then
-		the buffer is completely full and the frame is contained within more
-		than one buffer. */
-
-		/* Reset our state variables ready for the next read from this buffer. */
-        pcSource = ( portCHAR * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );
-        ulFameBytesReadSoFar = ( unsigned portLONG ) 0;
-		ulBufferPosition = ( unsigned portLONG ) 0;
-	}
-	else
-	{
-		/* Loop until we have obtained the required amount of data. */
-        ulSectionBytesReadSoFar = 0;
-		while( ulSectionBytesReadSoFar < ulSectionLength )
-		{
-			/* We may have already read some data from this buffer.  How much
-			data remains in the buffer? */
-			ulBytesRemainingInBuffer = ( ETH_RX_BUFFER_SIZE - ulBufferPosition );
-
-			/* How many more bytes do we need to read before we have the 
-			required amount of data? */
-            ulRemainingSectionBytes = ulSectionLength - ulSectionBytesReadSoFar;
-
-			/* Do we want more data than remains in the buffer? */
-			if( ulRemainingSectionBytes > ulBytesRemainingInBuffer )
-			{
-				/* We want more data than remains in the buffer so we can 
-				write the remains of the buffer to the destination, then move
-				onto the next buffer to get the rest. */
-				memcpy( &( pcTo[ ulSectionBytesReadSoFar ] ), &( pcSource[ ulBufferPosition ] ), ulBytesRemainingInBuffer );
-				ulSectionBytesReadSoFar += ulBytesRemainingInBuffer;
-                ulFameBytesReadSoFar += ulBytesRemainingInBuffer;
-
-				/* Mark the buffer as free again. */
-				xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
-
-				/* Move onto the next buffer. */
-				ulNextRxBuffer++;
-				if( ulNextRxBuffer >= NB_RX_BUFFERS )
-				{
-					ulNextRxBuffer = ( unsigned portLONG ) 0;
-				}
-
-				/* Reset the variables for the new buffer. */
-				pcSource = ( portCHAR * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );
-				ulBufferPosition = ( unsigned portLONG ) 0;
-			}
-			else
-			{
-				/* We have enough data in this buffer to send back.  Read out
-				enough data and remember how far we read up to. */
-				memcpy( &( pcTo[ ulSectionBytesReadSoFar ] ), &( pcSource[ ulBufferPosition ] ), ulRemainingSectionBytes );
-
-				/* There may be more data in this buffer yet.  Increment our 
-				position in this buffer past the data we have just read. */
-				ulBufferPosition += ulRemainingSectionBytes;
-				ulSectionBytesReadSoFar += ulRemainingSectionBytes;
-                ulFameBytesReadSoFar += ulRemainingSectionBytes;
-
-				/* Have we now finished with this buffer? */
-				if( ( ulBufferPosition >= ETH_RX_BUFFER_SIZE ) || ( ulFameBytesReadSoFar >= ulTotalFrameLength ) )
-				{
-					/* Mark the buffer as free again. */
-					xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
-
-					/* Move onto the next buffer. */
-					ulNextRxBuffer++;
-					if( ulNextRxBuffer >= NB_RX_BUFFERS )
-					{
-						ulNextRxBuffer = 0;
-					}
-	
-					pcSource = ( portCHAR * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );
-					ulBufferPosition = 0;
-				}
-			}
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-/* See the header file for descriptions of public functions. */
-xSemaphoreHandle xEMACInit( void )
-{
-	/* Code supplied by Atmel -------------------------------*/
-
-	/* Disable pull up on RXDV => PHY normal mode (not in test mode),
-	PHY has internal pull down. */
-	AT91C_BASE_PIOB->PIO_PPUDR = 1 << 15;
-
-	#if USE_RMII_INTERFACE != 1
-	  	/* PHY has internal pull down : set MII mode. */
-	  	AT91C_BASE_PIOB->PIO_PPUDR = 1 << 16;
-	#endif
-
-	/* Clear PB18 <=> PHY powerdown. */
-   	AT91C_BASE_PIOB->PIO_PER = 1 << 18;
-	AT91C_BASE_PIOB->PIO_OER = 1 << 18;
-	AT91C_BASE_PIOB->PIO_CODR = 1 << 18;
-
-	/* After PHY power up, hardware reset. */
-	AT91C_BASE_RSTC->RSTC_RMR = emacRESET_KEY | emacRESET_LENGTH;
-	AT91C_BASE_RSTC->RSTC_RCR = emacRESET_KEY | AT91C_RSTC_EXTRST;
-
-	/* Wait for hardware reset end. */
-	while( !( AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL ) )
-	{
-		__asm volatile ( "NOP" );
-	}
-    __asm volatile ( "NOP" );
-
-	/* Setup the pins. */
-	AT91C_BASE_PIOB->PIO_ASR = emacPERIPHERAL_A_SETUP;
-	AT91C_BASE_PIOB->PIO_PDR = emacPERIPHERAL_A_SETUP;
-
-	/* Enable com between EMAC PHY.
-
-	Enable management port. */
-	AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;	
-
-	/* MDC = MCK/32. */
-	AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;	
-
-	/* Wait for PHY auto init end (rather crude delay!). */
-	vTaskDelay( emacPHY_INIT_DELAY );
-
-	/* PHY configuration. */
-	#if USE_RMII_INTERFACE != 1
-	{
-		unsigned portLONG ulControl;
-
-		/* PHY has internal pull down : disable MII isolate. */
-		vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
-		vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
-		ulControl &= ~BMCR_ISOLATE;
-		vWritePHY( AT91C_PHY_ADDR, MII_BMCR, ulControl );
-	}
-	#endif
-
-	/* Disable management port again. */
-	AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
-
-	#if USE_RMII_INTERFACE != 1
-		/* Enable EMAC in MII mode, enable clock ERXCK and ETXCK. */
-		AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN ;
-	#else
-		/* Enable EMAC in RMII mode, enable RMII clock (50MHz from oscillator
-		on ERFCK). */
-		AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_RMII | AT91C_EMAC_CLKEN ;
-	#endif
-
-	/* End of code supplied by Atmel ------------------------*/
-
-	/* Setup the buffers and descriptors. */
-	prvSetupDescriptors();
-	
-	/* Load our MAC address into the EMAC. */
-	prvSetupMACAddress();
-
-	/* Are we connected? */
-	if( prvProbePHY() )
-	{
-		/* Enable the interrupt! */
-		portENTER_CRITICAL();
-		{
-			prvSetupEMACInterrupt();
-			vPassEMACSemaphore( xSemaphore );
-		}
-		portEXIT_CRITICAL();
-	}
-
-	return xSemaphore;
-}
-/*-----------------------------------------------------------*/
-
-/* See the header file for descriptions of public functions. */
-void vClearEMACTxBuffer( void )
-{
-static unsigned portBASE_TYPE uxNextBufferToClear = 0;
-
-	/* Called on Tx interrupt events to reset the AT91C_TRANSMIT_OK bit in each 
-	Tx buffer within the frame just transmitted.  This marks all the buffers
-	as available again.
-
-	The first buffer in the frame should have the bit set automatically. */
-	if( xTxDescriptors[ uxNextBufferToClear ].U_Status.status & AT91C_TRANSMIT_OK )
-	{
-		/* Loop through the other buffers in the frame. */
-		while( !( xTxDescriptors[ uxNextBufferToClear ].U_Status.status & AT91C_LAST_BUFFER ) )
-		{
-			uxNextBufferToClear++;
-
-			if( uxNextBufferToClear >= NB_TX_BUFFERS )
-			{
-				uxNextBufferToClear = 0;
-			}
-
-			xTxDescriptors[ uxNextBufferToClear ].U_Status.status |= AT91C_TRANSMIT_OK;
-		}
-
-		/* Start with the next buffer the next time a Tx interrupt is called. */
-		uxNextBufferToClear++;
-
-		/* Do we need to wrap back to the first buffer? */
-		if( uxNextBufferToClear >= NB_TX_BUFFERS )
-		{
-			uxNextBufferToClear = 0;
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetupDescriptors(void)
-{
-unsigned portBASE_TYPE xIndex;
-unsigned portLONG ulAddress;
-
-	/* Initialise xRxDescriptors descriptor. */
-	for( xIndex = 0; xIndex < NB_RX_BUFFERS; ++xIndex )
-	{
-		/* Calculate the address of the nth buffer within the array. */
-		ulAddress = ( unsigned portLONG )( pcRxBuffer + ( xIndex * ETH_RX_BUFFER_SIZE ) );
-
-		/* Write the buffer address into the descriptor.  The DMA will place
-		the data at this address when this descriptor is being used.  Mask off
-		the bottom bits of the address as these have special meaning. */
-		xRxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
-	}	
-
-	/* The last buffer has the wrap bit set so the EMAC knows to wrap back
-	to the first buffer. */
-	xRxDescriptors[ NB_RX_BUFFERS - 1 ].addr |= emacRX_WRAP_BIT;
-
-	/* Initialise xTxDescriptors. */
-	for( xIndex = 0; xIndex < NB_TX_BUFFERS; ++xIndex )
-	{
-		/* Calculate the address of the nth buffer within the array. */
-		ulAddress = ( unsigned portLONG )( pcTxBuffer + ( xIndex * ETH_TX_BUFFER_SIZE ) );
-
-		/* Write the buffer address into the descriptor.  The DMA will read
-		data from here when the descriptor is being used. */
-		xTxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
-		xTxDescriptors[ xIndex ].U_Status.status = AT91C_TRANSMIT_OK;
-	}	
-
-	/* The last buffer has the wrap bit set so the EMAC knows to wrap back
-	to the first buffer. */
-	xTxDescriptors[ NB_TX_BUFFERS - 1 ].U_Status.status = AT91C_TRANSMIT_WRAP | AT91C_TRANSMIT_OK;
-
-	/* Tell the EMAC where to find the descriptors. */
-	AT91C_BASE_EMAC->EMAC_RBQP = ( unsigned portLONG ) xRxDescriptors;
-	AT91C_BASE_EMAC->EMAC_TBQP = ( unsigned portLONG ) xTxDescriptors;
-	
-	/* Clear all the bits in the receive status register. */
-	AT91C_BASE_EMAC->EMAC_RSR = ( AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA );
-
-	/* Enable the copy of data into the buffers, ignore broadcasts, 
-	and don't copy FCS. */
-	AT91C_BASE_EMAC->EMAC_NCFGR |= ( AT91C_EMAC_CAF | AT91C_EMAC_NBC | AT91C_EMAC_DRFCS);
-
-	/* Enable Rx and Tx, plus the stats register. */
-	AT91C_BASE_EMAC->EMAC_NCR |= ( AT91C_EMAC_TE | AT91C_EMAC_RE | AT91C_EMAC_WESTAT );
-}	
-/*-----------------------------------------------------------*/
-
-static void prvSetupMACAddress( void )
-{
-	/* Must be written SA1L then SA1H. */
-	AT91C_BASE_EMAC->EMAC_SA1L =	( ( unsigned portLONG ) cMACAddress[ 3 ] << 24 ) |
-									( ( unsigned portLONG ) cMACAddress[ 2 ] << 16 ) |
-									( ( unsigned portLONG ) cMACAddress[ 1 ] << 8  ) |
-									cMACAddress[ 0 ];
-
-	AT91C_BASE_EMAC->EMAC_SA1H =	( ( unsigned portLONG ) cMACAddress[ 5 ] << 8 ) |
-									cMACAddress[ 4 ];
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetupEMACInterrupt( void )
-{
-	/* Create the semaphore used to trigger the EMAC task. */
-	vSemaphoreCreateBinary( xSemaphore );
-	if( xSemaphore )
-	{
-		/* We start by 'taking' the semaphore so the ISR can 'give' it when the
-		first interrupt occurs. */
-		xSemaphoreTake( xSemaphore, emacNO_DELAY );
-		portENTER_CRITICAL();
-		{
-			/* We want to interrupt on Rx and Tx events. */
-			AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP | AT91C_EMAC_TCOMP;
-
-			/* Enable the interrupts in the AIC. */
-			AT91F_AIC_ConfigureIt( AT91C_ID_EMAC, emacINTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, ( void (*)( void ) ) vEMACISR );
-            AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_EMAC;
-		}
-		portEXIT_CRITICAL();
-	}
-}
-
-
-
-
-
-/*
- * The following functions are initialisation functions taken from the Atmel
- * EMAC sample code.
- */
-
-
-static portBASE_TYPE prvProbePHY( void )
-{
-unsigned portLONG ulPHYId1, ulPHYId2, ulStatus;
-portBASE_TYPE xReturn = pdPASS;
-	
-	/* Code supplied by Atmel (reformatted) -----------------*/
-
-	/* Enable management port */
-	AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;	
-   	AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;
-
-	/* Read the PHY ID. */
-	vReadPHY( AT91C_PHY_ADDR, MII_PHYSID1, &ulPHYId1 );
-	vReadPHY(AT91C_PHY_ADDR, MII_PHYSID2, &ulPHYId2 );
-
-	/* AMD AM79C875:
-			PHY_ID1 = 0x0022
-			PHY_ID2 = 0x5541
-			Bits 3:0 Revision Number Four bit manufacturer?s revision number.
-				0001 stands for Rev. A, etc.
-	*/
-	if( ( ( ulPHYId1 << 16 ) | ( ulPHYId2 & 0xfff0 ) ) != MII_DM9161_ID )
-	{
-		/* Did not expect this ID. */
-		xReturn = pdFAIL;
-	}
-	else
-	{
-		ulStatus = xGetLinkSpeed();
-
-		if( ulStatus != pdPASS )
-		{
-			xReturn = pdFAIL;
-		}
-	}
-
-	/* Disable management port */
-	AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;	
-
-	/* End of code supplied by Atmel ------------------------*/
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-static void vReadPHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG *pulValue )
-{
-	/* Code supplied by Atmel (reformatted) ----------------------*/
-
-	AT91C_BASE_EMAC->EMAC_MAN = 	(AT91C_EMAC_SOF & (0x01<<30))
-									| (2 << 16) | (2 << 28)
-									| ((ucPHYAddress & 0x1f) << 23)
-									| (ucAddress << 18);
-
-	/* Wait until IDLE bit in Network Status register is cleared. */
-	while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
-	{
-		__asm( "NOP" );
-	}
-
-	*pulValue = ( AT91C_BASE_EMAC->EMAC_MAN & 0x0000ffff );	
-
-	/* End of code supplied by Atmel ------------------------*/
-}
-/*-----------------------------------------------------------*/
-
-#if USE_RMII_INTERFACE != 1
-static void vWritePHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG ulValue )
-{
-	/* Code supplied by Atmel (reformatted) ----------------------*/
-
-	AT91C_BASE_EMAC->EMAC_MAN = (( AT91C_EMAC_SOF & (0x01<<30))
-								| (2 << 16) | (1 << 28)
-								| ((ucPHYAddress & 0x1f) << 23)
-								| (ucAddress << 18))
-								| (ulValue & 0xffff);
-
-	/* Wait until IDLE bit in Network Status register is cleared */
-	while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
-	{
-		__asm( "NOP" );
-	};
-
-	/* End of code supplied by Atmel ------------------------*/
-}
-#endif
-/*-----------------------------------------------------------*/
-
-static portBASE_TYPE xGetLinkSpeed( void )
-{
-	unsigned portLONG ulBMSR, ulBMCR, ulLPA, ulMACCfg, ulSpeed, ulDuplex;
-
-	/* Code supplied by Atmel (reformatted) -----------------*/
-
-	/* Link status is latched, so read twice to get current value */
-	vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
-	vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
-
-	if( !( ulBMSR & BMSR_LSTATUS ) )
-	{	
-		/* No Link. */
-		return pdFAIL;
-	}
-
-	vReadPHY(AT91C_PHY_ADDR, MII_BMCR, &ulBMCR);
-	if (ulBMCR & BMCR_ANENABLE)
-	{				
-		/* AutoNegotiation is enabled. */
-		if (!(ulBMSR & BMSR_ANEGCOMPLETE))
-		{
-			/* Auto-negotitation in progress. */
-			return pdFAIL;				
-		}		
-
-		vReadPHY(AT91C_PHY_ADDR, MII_LPA, &ulLPA);
-		if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_100HALF ) )
-		{
-			ulSpeed = SPEED_100;
-		}
-		else
-		{
-			ulSpeed = SPEED_10;
-		}
-
-		if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_10FULL ) )
-		{
-			ulDuplex = DUPLEX_FULL;
-		}
-		else
-		{
-			ulDuplex = DUPLEX_HALF;
-		}
-	}
-	else
-	{
-		ulSpeed = ( ulBMCR & BMCR_SPEED100 ) ? SPEED_100 : SPEED_10;
-		ulDuplex = ( ulBMCR & BMCR_FULLDPLX ) ? DUPLEX_FULL : DUPLEX_HALF;
-	}
-
-	/* Update the MAC */
-	ulMACCfg = AT91C_BASE_EMAC->EMAC_NCFGR & ~( AT91C_EMAC_SPD | AT91C_EMAC_FD );
-	if( ulSpeed == SPEED_100 )
-	{
-		if( ulDuplex == DUPLEX_FULL )
-		{
-			/* 100 Full Duplex */
-			AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD | AT91C_EMAC_FD;
-		}
-		else
-		{					
-			/* 100 Half Duplex */
-			AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD;
-		}
-	}
-	else
-	{
-		if (ulDuplex == DUPLEX_FULL)
-		{
-			/* 10 Full Duplex */
-			AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_FD;
-		}
-		else
-		{			/* 10 Half Duplex */
-			AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg;
-		}
-	}
-
-	/* End of code supplied by Atmel ------------------------*/
-
-	return pdPASS;
-}
-/*-----------------------------------------------------------*/
-
-void vEMACWaitForInput( void )
-{
-	/* Just wait until we are signled from an ISR that data is available, or
-	we simply time out. */
-	xSemaphoreTake( xSemaphore, emacBLOCK_TIME_WAITING_FOR_INPUT );
-}
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/EMAC/SAM7_EMAC.h b/Demo/lwIP_Demo_Rowley_ARM7/EMAC/SAM7_EMAC.h
deleted file mode 100644
index c9537dcfb..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/EMAC/SAM7_EMAC.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
-	FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
-
-	This file is part of the FreeRTOS.org distribution.
-
-	FreeRTOS.org is free software; you can redistribute it and/or modify
-	it under the terms of the GNU General Public License as published by
-	the Free Software Foundation; either version 2 of the License, or
-	(at your option) any later version.
-
-	FreeRTOS.org is distributed in the hope that it will be useful,
-	but WITHOUT ANY WARRANTY; without even the implied warranty of
-	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-	GNU General Public License for more details.
-
-	You should have received a copy of the GNU General Public License
-	along with FreeRTOS.org; if not, write to the Free Software
-	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-
-	A special exception to the GPL can be applied should you wish to distribute
-	a combined work that includes FreeRTOS.org, without being obliged to provide
-	the source code for any proprietary components.  See the licensing section
-	of http://www.FreeRTOS.org for full details of how and when the exception
-	can be applied.
-
-	***************************************************************************
-	See http://www.FreeRTOS.org for documentation, latest information, license
-	and contact details.  Please ensure to read the configuration and relevant
-	port sections of the online documentation.
-	***************************************************************************
-*/
-
-/*
-Changes from V3.2.4
-
-	+ Modified the default MAC address as the one used previously was not liked
-	  by some routers.
-
-*/
-
-#ifndef SAM_7_EMAC_H
-#define SAM_7_EMAC_H
-
-/* MAC address definition.  The MAC address must be unique on the network. */
-#define emacETHADDR0 0
-#define emacETHADDR1 0xbd
-#define emacETHADDR2 0x33
-#define emacETHADDR3 0x06
-#define emacETHADDR4 0x68
-#define emacETHADDR5 0x22
-
-/* The IP address being used. */
-#define emacIPADDR0 172
-#define emacIPADDR1 25
-#define emacIPADDR2 218
-#define emacIPADDR3 205
-
-/* The gateway address being used. */
-#define emacGATEWAY_ADDR0 172
-#define emacGATEWAY_ADDR1 25
-#define emacGATEWAY_ADDR2 218
-#define emacGATEWAY_ADDR3 3
-
-/* The network mask being used. */
-#define emacNET_MASK0 255
-#define emacNET_MASK1 255
-#define emacNET_MASK2 0
-#define emacNET_MASK3 0
-
-/*
- * Initialise the EMAC driver.  If successful a semaphore is returned that
- * is used by the EMAC ISR to indicate that Rx packets have been received.
- * If the initialisation fails then NULL is returned.
- */
-xSemaphoreHandle xEMACInit( void );
-
-/*
- * Send ulLength bytes from pcFrom.  This copies the buffer to one of the
- * EMAC Tx buffers, then indicates to the EMAC that the buffer is ready.
- * If lEndOfFrame is true then the data being copied is the end of the frame
- * and the frame can be transmitted. 
- */
-portLONG lEMACSend( portCHAR *pcFrom, unsigned portLONG ulLength, portLONG lEndOfFrame );
-
-/*
- * Frames can be read from the EMAC in multiple sections.
- * Read ulSectionLength bytes from the EMAC receive buffers to pcTo.  
- * ulTotalFrameLength is the size of the entire frame.  Generally vEMACRead
- * will be repetedly called until the sum of all the ulSectionLenths totals
- * the value of ulTotalFrameLength.
- */
-void vEMACRead( portCHAR *pcTo, unsigned portLONG ulSectionLength, unsigned portLONG ulTotalFrameLength );
-
-/*
- * The EMAC driver and interrupt service routines are defined in different 
- * files as the driver is compiled to THUMB, and the ISR to ARM.  This function
- * simply passes the semaphore used to communicate between the two.
- */
-void vPassEMACSemaphore( xSemaphoreHandle xCreatedSemaphore );
-
-/* 
- * Called by the Tx interrupt, this function traverses the buffers used to
- * hold the frame that has just completed transmission and marks each as
- * free again.
- */
-void vClearEMACTxBuffer( void );
-
-/*
- * Suspend on a semaphore waiting either for the semaphore to be obtained 
- * or a timeout.  The semaphore is used by the EMAC ISR to indicate that
- * data has been received and is ready for processing.
- */
-void vEMACWaitForInput( void );
-
-/*
- * Return the length of the next frame in the receive buffers.
- */
-unsigned portLONG ulEMACInputLength( void );
-
-#endif
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/EMAC/SAM7_EMAC_ISR.c b/Demo/lwIP_Demo_Rowley_ARM7/EMAC/SAM7_EMAC_ISR.c
deleted file mode 100644
index 0359b4d6a..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/EMAC/SAM7_EMAC_ISR.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
-	FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
-
-	This file is part of the FreeRTOS.org distribution.
-
-	FreeRTOS.org is free software; you can redistribute it and/or modify
-	it under the terms of the GNU General Public License as published by
-	the Free Software Foundation; either version 2 of the License, or
-	(at your option) any later version.
-
-	FreeRTOS.org is distributed in the hope that it will be useful,
-	but WITHOUT ANY WARRANTY; without even the implied warranty of
-	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-	GNU General Public License for more details.
-
-	You should have received a copy of the GNU General Public License
-	along with FreeRTOS.org; if not, write to the Free Software
-	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-
-	A special exception to the GPL can be applied should you wish to distribute
-	a combined work that includes FreeRTOS.org, without being obliged to provide
-	the source code for any proprietary components.  See the licensing section
-	of http://www.FreeRTOS.org for full details of how and when the exception
-	can be applied.
-
-	***************************************************************************
-	See http://www.FreeRTOS.org for documentation, latest information, license
-	and contact details.  Please ensure to read the configuration and relevant
-	port sections of the online documentation.
-	***************************************************************************
-*/
-
-/* 
-Changes from V3.2.4
-
-	+ Also read the EMAC_RSR register in the EMAC ISR as a work around the 
-	  the EMAC bug that can reset the RX bit in EMAC_ISR register before the
-	  bit has been read.
-
-Changes from V4.0.1
-
-	+ Only check the interrupt status register to see if an EMAC Tx interrupt
-	  has occurred.  Previously the TSR register was also inspected.
-*/
-
-#include "FreeRTOS.h"
-#include "task.h"
-#include "semphr.h"
-#include "SAM7_EMAC.h"
-#include "AT91SAM7X256.h"
-
-/*-----------------------------------------------------------*/
-
-/* The semaphore used to signal the arrival of new data to the interface
-task. */
-static xSemaphoreHandle xSemaphore = NULL;
-
-void vEMACISR( void ) __attribute__((naked));
-
-/*-----------------------------------------------------------*/
-/*
- * The EMAC ISR.  Handles both Tx and Rx complete interrupts.
- */
-void vEMACISR( void )
-{
-	/* This ISR can cause a context switch, so the first statement must be a
-	call to the portENTER_SWITCHING_ISR() macro.  This must be BEFORE any
-	variable declarations. */
-	portENTER_SWITCHING_ISR();
-
-	/* Variable definitions can be made now. */
-	volatile unsigned portLONG ulIntStatus, ulEventStatus;
-	portBASE_TYPE xSwitchRequired = pdFALSE;
-    extern void vClearEMACTxBuffer( void );
-
-	/* Find the cause of the interrupt. */
-	ulIntStatus = AT91C_BASE_EMAC->EMAC_ISR;
-	ulEventStatus = AT91C_BASE_EMAC->EMAC_RSR;
-
-	if( ( ulIntStatus & AT91C_EMAC_RCOMP ) || ( ulEventStatus & AT91C_EMAC_REC ) )
-	{
-		/* A frame has been received, signal the lwIP task so it can process
-		the Rx descriptors. */
-		xSwitchRequired = xSemaphoreGiveFromISR( xSemaphore, pdFALSE );
-		AT91C_BASE_EMAC->EMAC_RSR = AT91C_EMAC_REC;
-	}
-
-	if( ulIntStatus & AT91C_EMAC_TCOMP )
-	{
-		/* A frame has been transmitted.  Mark all the buffers used by the
-		frame just transmitted as free again. */
-		vClearEMACTxBuffer();
-		AT91C_BASE_EMAC->EMAC_TSR = AT91C_EMAC_COMP;
-	}
-
-	/* Clear the interrupt. */
-	AT91C_BASE_AIC->AIC_EOICR = 0;
-
-	/* If a task was woken by either a frame being received then we may need to 
-	switch to another task. */
-	portEXIT_SWITCHING_ISR( xSwitchRequired );
-}
-/*-----------------------------------------------------------*/
-
-void vPassEMACSemaphore( xSemaphoreHandle xCreatedSemaphore )
-{
-	/* Simply store the semaphore that should be used by the ISR. */
-	xSemaphore = xCreatedSemaphore;
-}
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/EMAC/mii.h b/Demo/lwIP_Demo_Rowley_ARM7/EMAC/mii.h
deleted file mode 100644
index 29b2f53d5..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/EMAC/mii.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/* Generic MII registers. */
-
-#define MII_BMCR            0x00        /* Basic mode control register */
-#define MII_BMSR            0x01        /* Basic mode status register  */
-#define MII_PHYSID1         0x02        /* PHYS ID 1                   */
-#define MII_PHYSID2         0x03        /* PHYS ID 2                   */
-#define MII_ADVERTISE       0x04        /* Advertisement control reg   */
-#define MII_LPA             0x05        /* Link partner ability reg    */
-#define MII_EXPANSION       0x06        /* Expansion register          */
-#define MII_DCOUNTER        0x12        /* Disconnect counter          */
-#define MII_FCSCOUNTER      0x13        /* False carrier counter       */
-#define MII_NWAYTEST        0x14        /* N-way auto-neg test reg     */
-#define MII_RERRCOUNTER     0x15        /* Receive error counter       */
-#define MII_SREVISION       0x16        /* Silicon revision            */
-#define MII_RESV1           0x17        /* Reserved...                 */
-#define MII_LBRERROR        0x18        /* Lpback, rx, bypass error    */
-#define MII_PHYADDR         0x19        /* PHY address                 */
-#define MII_RESV2           0x1a        /* Reserved...                 */
-#define MII_TPISTATUS       0x1b        /* TPI status for 10mbps       */
-#define MII_NCONFIG         0x1c        /* Network interface config    */
-
-/* Basic mode control register. */
-#define BMCR_RESV               0x007f  /* Unused...                   */
-#define BMCR_CTST               0x0080  /* Collision test              */
-#define BMCR_FULLDPLX           0x0100  /* Full duplex                 */
-#define BMCR_ANRESTART          0x0200  /* Auto negotiation restart    */
-#define BMCR_ISOLATE            0x0400  /* Disconnect DP83840 from MII */
-#define BMCR_PDOWN              0x0800  /* Powerdown the DP83840       */
-#define BMCR_ANENABLE           0x1000  /* Enable auto negotiation     */
-#define BMCR_SPEED100           0x2000  /* Select 100Mbps              */
-#define BMCR_LOOPBACK           0x4000  /* TXD loopback bits           */
-#define BMCR_RESET              0x8000  /* Reset the DP83840           */
-
-/* Basic mode status register. */
-#define BMSR_ERCAP              0x0001  /* Ext-reg capability          */
-#define BMSR_JCD                0x0002  /* Jabber detected             */
-#define BMSR_LSTATUS            0x0004  /* Link status                 */
-#define BMSR_ANEGCAPABLE        0x0008  /* Able to do auto-negotiation */
-#define BMSR_RFAULT             0x0010  /* Remote fault detected       */
-#define BMSR_ANEGCOMPLETE       0x0020  /* Auto-negotiation complete   */
-#define BMSR_RESV               0x07c0  /* Unused...                   */
-#define BMSR_10HALF             0x0800  /* Can do 10mbps, half-duplex  */
-#define BMSR_10FULL             0x1000  /* Can do 10mbps, full-duplex  */
-#define BMSR_100HALF            0x2000  /* Can do 100mbps, half-duplex */
-#define BMSR_100FULL            0x4000  /* Can do 100mbps, full-duplex */
-#define BMSR_100BASE4           0x8000  /* Can do 100mbps, 4k packets  */
-
-/* Advertisement control register. */
-#define ADVERTISE_SLCT          0x001f  /* Selector bits               */
-#define ADVERTISE_CSMA          0x0001  /* Only selector supported     */
-#define ADVERTISE_10HALF        0x0020  /* Try for 10mbps half-duplex  */
-#define ADVERTISE_10FULL        0x0040  /* Try for 10mbps full-duplex  */
-#define ADVERTISE_100HALF       0x0080  /* Try for 100mbps half-duplex */
-#define ADVERTISE_100FULL       0x0100  /* Try for 100mbps full-duplex */
-#define ADVERTISE_100BASE4      0x0200  /* Try for 100mbps 4k packets  */
-#define ADVERTISE_RESV          0x1c00  /* Unused...                   */
-#define ADVERTISE_RFAULT        0x2000  /* Say we can detect faults    */
-#define ADVERTISE_LPACK         0x4000  /* Ack link partners response  */
-#define ADVERTISE_NPAGE         0x8000  /* Next page bit               */
-
-#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
-			ADVERTISE_CSMA)
-#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
-                       ADVERTISE_100HALF | ADVERTISE_100FULL)
-
-/* Link partner ability register. */
-#define LPA_SLCT                0x001f  /* Same as advertise selector  */
-#define LPA_10HALF              0x0020  /* Can do 10mbps half-duplex   */
-#define LPA_10FULL              0x0040  /* Can do 10mbps full-duplex   */
-#define LPA_100HALF             0x0080  /* Can do 100mbps half-duplex  */
-#define LPA_100FULL             0x0100  /* Can do 100mbps full-duplex  */
-#define LPA_100BASE4            0x0200  /* Can do 100mbps 4k packets   */
-#define LPA_RESV                0x1c00  /* Unused...                   */
-#define LPA_RFAULT              0x2000  /* Link partner faulted        */
-#define LPA_LPACK               0x4000  /* Link partner acked us       */
-#define LPA_NPAGE               0x8000  /* Next page bit               */
-
-#define LPA_DUPLEX		(LPA_10FULL | LPA_100FULL)
-#define LPA_100			(LPA_100FULL | LPA_100HALF | LPA_100BASE4)
-
-/* Expansion register for auto-negotiation. */
-#define EXPANSION_NWAY          0x0001  /* Can do N-way auto-nego      */
-#define EXPANSION_LCWP          0x0002  /* Got new RX page code word   */
-#define EXPANSION_ENABLENPAGE   0x0004  /* This enables npage words    */
-#define EXPANSION_NPCAPABLE     0x0008  /* Link partner supports npage */
-#define EXPANSION_MFAULTS       0x0010  /* Multiple faults detected    */
-#define EXPANSION_RESV          0xffe0  /* Unused...                   */
-
-/* N-way test register. */
-#define NWAYTEST_RESV1          0x00ff  /* Unused...                   */
-#define NWAYTEST_LOOPBACK       0x0100  /* Enable loopback for N-way   */
-#define NWAYTEST_RESV2          0xfe00  /* Unused...                   */
-
-#define SPEED_10				10
-#define SPEED_100				100
-
-/* Duplex, half or full. */
-#define DUPLEX_HALF				0x00
-#define DUPLEX_FULL				0x01
-
-/* PHY ID */
-#define MII_DM9161_ID     0x0181b8a0
-#define MII_AM79C875_ID   0x00225540	/* 0x00225541 */
-
-#define AT91C_PHY_ADDR	31
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/FreeRTOSConfig.h b/Demo/lwIP_Demo_Rowley_ARM7/FreeRTOSConfig.h
deleted file mode 100644
index fc385982a..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/FreeRTOSConfig.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
-	FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
-
-	This file is part of the FreeRTOS.org distribution.
-
-	FreeRTOS.org is free software; you can redistribute it and/or modify
-	it under the terms of the GNU General Public License as published by
-	the Free Software Foundation; either version 2 of the License, or
-	(at your option) any later version.
-
-	FreeRTOS.org is distributed in the hope that it will be useful,
-	but WITHOUT ANY WARRANTY; without even the implied warranty of
-	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-	GNU General Public License for more details.
-
-	You should have received a copy of the GNU General Public License
-	along with FreeRTOS.org; if not, write to the Free Software
-	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-
-	A special exception to the GPL can be applied should you wish to distribute
-	a combined work that includes FreeRTOS.org, without being obliged to provide
-	the source code for any proprietary components.  See the licensing section
-	of http://www.FreeRTOS.org for full details of how and when the exception
-	can be applied.
-
-	***************************************************************************
-	See http://www.FreeRTOS.org for documentation, latest information, license
-	and contact details.  Please ensure to read the configuration and relevant
-	port sections of the online documentation.
-	***************************************************************************
-*/
-
-#ifndef FREERTOS_CONFIG_H
-#define FREERTOS_CONFIG_H
-
-/*-----------------------------------------------------------
- * Application specific definitions.
- *
- * These definitions should be adjusted for your particular hardware and
- * application requirements.
- *
- * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
- * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
- *----------------------------------------------------------*/
-
-/* The SWI is used by the scheduler. */
-#define vPortYieldProcessor swi_handler
-
-
-#define configUSE_PREEMPTION		1
-#define configUSE_IDLE_HOOK			1
-#define configUSE_TICK_HOOK			0
-#define configCPU_CLOCK_HZ			( ( unsigned portLONG ) 47923200 )
-#define configTICK_RATE_HZ			( ( portTickType ) 1000 )
-#define configMAX_PRIORITIES		( ( unsigned portBASE_TYPE ) 5 )
-#define configMINIMAL_STACK_SIZE	( ( unsigned portSHORT ) 110 )
-#define configTOTAL_HEAP_SIZE		( ( size_t ) 22000 )
-#define configMAX_TASK_NAME_LEN		( 16 )
-#define configUSE_TRACE_FACILITY	1
-#define configUSE_16_BIT_TICKS		0
-#define configIDLE_SHOULD_YIELD		1
-
-/* Co-routine definitions. */
-#define configUSE_CO_ROUTINES 		0
-#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
-
-/* Set the following definitions to 1 to include the API function, or zero
-to exclude the API function. */
-
-#define INCLUDE_vTaskPrioritySet			1
-#define INCLUDE_uxTaskPriorityGet			1
-#define INCLUDE_vTaskDelete					1
-#define INCLUDE_vTaskCleanUpResources		0
-#define INCLUDE_vTaskSuspend				1
-#define INCLUDE_vTaskDelayUntil				1
-#define INCLUDE_vTaskDelay					1
-#define INCLUDE_xTaskGetCurrentTaskHandle	1
-
-#endif /* FREERTOS_CONFIG_H */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/ParTest/ParTest.c b/Demo/lwIP_Demo_Rowley_ARM7/ParTest/ParTest.c
deleted file mode 100644
index 80e111363..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/ParTest/ParTest.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
-	FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
-
-	This file is part of the FreeRTOS.org distribution.
-
-	FreeRTOS.org is free software; you can redistribute it and/or modify
-	it under the terms of the GNU General Public License as published by
-	the Free Software Foundation; either version 2 of the License, or
-	(at your option) any later version.
-
-	FreeRTOS.org is distributed in the hope that it will be useful,
-	but WITHOUT ANY WARRANTY; without even the implied warranty of
-	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-	GNU General Public License for more details.
-
-	You should have received a copy of the GNU General Public License
-	along with FreeRTOS.org; if not, write to the Free Software
-	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-
-	A special exception to the GPL can be applied should you wish to distribute
-	a combined work that includes FreeRTOS.org, without being obliged to provide
-	the source code for any proprietary components.  See the licensing section
-	of http://www.FreeRTOS.org for full details of how and when the exception
-	can be applied.
-
-	***************************************************************************
-	See http://www.FreeRTOS.org for documentation, latest information, license
-	and contact details.  Please ensure to read the configuration and relevant
-	port sections of the online documentation.
-	***************************************************************************
-*/
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-
-/* Demo application includes. */
-#include "partest.h"
-
-/* Hardware specific includes. */
-#include "Board.h"
-
-
-/*-----------------------------------------------------------
- * Simple parallel port IO routines for the LED's.  LED's can be set, cleared
- * or toggled.
- *-----------------------------------------------------------*/
-const unsigned portLONG ulLED_MASK[ NB_LED ]= { LED1, LED2, LED3, LED4 };
-
-void vParTestInitialise( void )
-{	
-	/* Start with all LED's off. */
-    AT91C_BASE_PIOB->PIO_SODR = LED_MASK;
-}
-/*-----------------------------------------------------------*/
-
-void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
-{
-	if( uxLED < ( portBASE_TYPE ) NB_LED )
-	{
-		if( xValue )
-		{
-			AT91C_BASE_PIOB->PIO_SODR = ulLED_MASK[ uxLED ];
-		}
-		else
-		{
-			AT91C_BASE_PIOB->PIO_CODR = ulLED_MASK[ uxLED ];
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
-{
-	if( uxLED < ( portBASE_TYPE ) NB_LED )
-	{
-		if( AT91C_BASE_PIOB->PIO_PDSR & ulLED_MASK[ uxLED ] )
-		{
-			AT91C_BASE_PIOB->PIO_CODR = ulLED_MASK[ uxLED ];
-		}
-		else
-		{
-			AT91C_BASE_PIOB->PIO_SODR = ulLED_MASK[ uxLED ];
-		}
-	}
-}
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/USB/FreeRTOSCDC.inf b/Demo/lwIP_Demo_Rowley_ARM7/USB/FreeRTOSCDC.inf
deleted file mode 100644
index eb3cb61c1..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/USB/FreeRTOSCDC.inf
+++ /dev/null
@@ -1,48 +0,0 @@
-[Version]
-Signature="$Windows NT$"
-Class=Ports
-ClassGuid={4D36E978-E325-11CE-BFC1-08002BE10318}
-Provider=%ATMEL%
-LayoutFile=layout.inf
-DriverVer=10/15/1999,5.0.2153.1
-
-[MANUFACTURER]
-%FreeRTOS%=FreeRTOS
-
-[FreeRTOS]
-%FreeRTOS_CDC%=Reader,USB\VID_EB03&PID_0920
-
-[Reader_Install.NTx86]
-;Windows2000
-
-[DestinationDirs]
-DefaultDestDir=12
-Reader.NT.Copy=12
-
-[Reader.NT]
-CopyFiles=Reader.NT.Copy
-AddReg=Reader.NT.AddReg
-
-[Reader.NT.Copy]
-usbser.sys
-
-[Reader.NT.AddReg]
-HKR,,NTMPDriver,,*ntkern
-HKR,,NTMPDriver,,usbser.sys
-HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider"
-[Reader.NT.Services]
-AddService = usbser, 0x00000002,Service_Inst
-
-[Service_Inst]
-DisplayName = %Serial.SvcDesc%
-ServiceType = 1 ; SERVICE_KERNEL_DRIVER
-StartType = 3 ; SERVICE_DEMAND_START
-ErrorControl = 1 ;SERVICE_ERROR_NORMAL
-ServiceBinary = %12%\usbser.sys
-LoadOrderGroup = Base
-
-[Strings]
-FreeRTOS = "FreeRTOS"
-FreeRTOS_CDC = "FreeRTOS CDC Demo"
-Serial.SvcDesc = "USB Serial emulation driver"
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/USB/USB-CDC.c b/Demo/lwIP_Demo_Rowley_ARM7/USB/USB-CDC.c
deleted file mode 100644
index 2cbbc7b64..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/USB/USB-CDC.c
+++ /dev/null
@@ -1,863 +0,0 @@
-/*
-	FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
-
-	This file is part of the FreeRTOS.org distribution.
-
-	FreeRTOS.org is free software; you can redistribute it and/or modify
-	it under the terms of the GNU General Public License as published by
-	the Free Software Foundation; either version 2 of the License, or
-	(at your option) any later version.
-
-	FreeRTOS.org is distributed in the hope that it will be useful,
-	but WITHOUT ANY WARRANTY; without even the implied warranty of
-	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-	GNU General Public License for more details.
-
-	You should have received a copy of the GNU General Public License
-	along with FreeRTOS.org; if not, write to the Free Software
-	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-
-	A special exception to the GPL can be applied should you wish to distribute
-	a combined work that includes FreeRTOS.org, without being obliged to provide
-	the source code for any proprietary components.  See the licensing section
-	of http://www.FreeRTOS.org for full details of how and when the exception
-	can be applied.
-
-	***************************************************************************
-	See http://www.FreeRTOS.org for documentation, latest information, license
-	and contact details.  Please ensure to read the configuration and relevant
-	port sections of the online documentation.
-	***************************************************************************
-*/
-
-/*
-	USB Communications Device Class driver.
-	Implements task vUSBCDCTask and provides an Abstract Control Model serial 
-	interface.  Control is through endpoint 0, device-to-host notification is 
-	provided by interrupt-in endpoint 3, and raw data is transferred through 
-	bulk endpoints 1 and 2.
-
-	- developed from original FreeRTOS HID example by Scott Miller
-	- modified to support 3.2 GCC by najay
-*/
-
-/* Standard includes. */
-#include 
-#include 
-
-/* Demo board includes. */
-#include "Board.h"
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-#include "queue.h"
-
-/* Demo app includes. */
-#include "USB-CDC.h"
-#include "descriptors.h"
-
-#define usbNO_BLOCK ( ( portTickType ) 0 )
-
-/* Reset all endpoints */
-static void prvResetEndPoints( void );
-
-/* Clear pull up resistor to detach device from host */
-static void vDetachUSBInterface( void );
-
-/* Set up interface and initialize variables */
-static void vInitUSBInterface( void );
-
-/* Handle control endpoint events. */
-static void prvProcessEndPoint0Interrupt( xISRStatus *pxMessage );
-
-/* Handle standard device requests. */
-static void prvHandleStandardDeviceRequest( xUSB_REQUEST *pxRequest );
-
-/* Handle standard interface requests. */
-static void prvHandleStandardInterfaceRequest( xUSB_REQUEST *pxRequest );
-
-/* Handle endpoint requests. */
-static void prvHandleStandardEndPointRequest( xUSB_REQUEST *pxRequest );
-
-/* Handle class interface requests. */
-static void prvHandleClassInterfaceRequest( xUSB_REQUEST *pxRequest );
-
-/* Prepare control data transfer.  prvSendNextSegment starts transfer. */
-static void prvSendControlData( unsigned portCHAR *pucData, unsigned portSHORT usRequestedLength, unsigned portLONG ulLengthLeftToSend, portLONG lSendingDescriptor );
-
-/* Send next segment of data for the control transfer */
-static void prvSendNextSegment( void );
-
-/* Send stall - used to respond to unsupported requests */
-static void prvSendStall( void );
-
-/* Send a zero-length (null) packet */
-static void prvSendZLP( void );
-
-/* Handle requests for standard interface descriptors */
-static void prvGetStandardInterfaceDescriptor( xUSB_REQUEST *pxRequest );
-
-/*------------------------------------------------------------*/
-
-/* File scope static variables */
-static unsigned portCHAR ucUSBConfig = ( unsigned portCHAR ) 0;
-static unsigned portLONG ulReceivedAddress = ( unsigned portLONG ) 0;
-static eDRIVER_STATE eDriverState = eNOTHING;
-
-/* Incoming and outgoing control data structures */
-static xCONTROL_MESSAGE pxControlTx;
-static xCONTROL_MESSAGE pxControlRx;
-
-/* Queue holding pointers to pending messages */
-xQueueHandle xUSBInterruptQueue; 
-
-/* Queues used to hold received characters, and characters waiting to be
-transmitted.  Rx queue must be larger than FIFO size. */
-static xQueueHandle xRxCDC; 
-static xQueueHandle xTxCDC; 
-
-/* Line coding - 115,200 baud, N-8-1 */
-static const unsigned portCHAR pxLineCoding[] = { 0x00, 0xC2, 0x01, 0x00, 0x00, 0x00, 0x08 };
-
-/* Status variables. */
-static unsigned portCHAR ucControlState;
-static unsigned int uiCurrentBank;
-
-
-/*------------------------------------------------------------*/
-
-
-void vUSBCDCTask( void *pvParameters )
-{
-xISRStatus *pxMessage;
-unsigned portLONG ulStatus;
-unsigned portLONG ulRxBytes;
-unsigned portCHAR ucByte;
-portBASE_TYPE xByte;
-
-	( void ) pvParameters;
-
-	/* Disconnect USB device from hub.  For debugging - causes host to register reset */
-	portENTER_CRITICAL();
-		 vDetachUSBInterface();
-	portEXIT_CRITICAL();
-	
-	vTaskDelay( portTICK_RATE_MS * 60 );
-
-	/* Init USB interface */
-	portENTER_CRITICAL();
-		vInitUSBInterface();
-	portEXIT_CRITICAL();
-	
-	/* Main task loop.  Process incoming endpoint 0 interrupts, handle data transfers. */
-	 
-	for( ;; )
-	{
-		/* Look for data coming from the ISR. */
-		if( xQueueReceive( xUSBInterruptQueue, &pxMessage, usbSHORTEST_DELAY ) )
-		{
-			if( pxMessage->ulISR & AT91C_UDP_EPINT0 )
-			{
-				/* All endpoint 0 interrupts are handled here. */
-				prvProcessEndPoint0Interrupt( pxMessage );
-			}
-
-			if( pxMessage->ulISR & AT91C_UDP_ENDBUSRES )
-			{
-				/* End of bus reset - reset the endpoints and de-configure. */
-				prvResetEndPoints();		
-			}
-		}
-		
-		/* See if we're ready to send and receive data. */
-		if( eDriverState == eREADY_TO_SEND && ucControlState ) 
-		{
-			if( ( !(AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_2 ] & AT91C_UDP_TXPKTRDY) ) && uxQueueMessagesWaiting( xTxCDC ) )
-			{
-				for( xByte = 0; xByte < 64; xByte++ )
-				{				   
-					if( !xQueueReceive( xTxCDC, &ucByte, 0 ) ) 
-					{
-						/* No data buffered to transmit. */
-						break;
-					}
-
-					/* Got a byte to transmit. */
-					AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_2 ] = ucByte;
-				} 
-				AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_2 ] |= AT91C_UDP_TXPKTRDY;
-			}
-
-			/* Check for incoming data (host-to-device) on endpoint 1. */
-			while( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] & (AT91C_UDP_RX_DATA_BK0 | AT91C_UDP_RX_DATA_BK1) )
-			{
-				ulRxBytes = (AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] >> 16) & usbRX_COUNT_MASK;
-
-				/* Only process FIFO if there's room to store it in the queue */
-				if( ulRxBytes < ( USB_CDC_QUEUE_SIZE - uxQueueMessagesWaiting( xRxCDC ) ) )
-				{
-					while( ulRxBytes-- )
-					{
-						ucByte = AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_1 ];
-						xQueueSend( xRxCDC, &ucByte, 0 );
-					}
-
-					/* Release the FIFO */
-					portENTER_CRITICAL();
-					{
-						ulStatus = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ];
-						usbCSR_CLEAR_BIT( &ulStatus, uiCurrentBank );
-						AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] = ulStatus;
-					}
-					portEXIT_CRITICAL();
-
-					/* Re-enable endpoint 1's interrupts */
-					AT91C_BASE_UDP->UDP_IER = AT91C_UDP_EPINT1;
-				
-					/* Update the current bank in use */
-					if( uiCurrentBank == AT91C_UDP_RX_DATA_BK0 ) 
-					{
-						uiCurrentBank = AT91C_UDP_RX_DATA_BK1;
-					}
-					else 
-					{
-						uiCurrentBank = AT91C_UDP_RX_DATA_BK0;
-					}
-
-				}
-				else 
-				{
-					break;
-				}
-			}
-		}
-	}
-}
-/*------------------------------------------------------------*/
-
-void vUSBSendByte( portCHAR cByte )
-{
-	/* Queue the byte to be sent.  The USB task will send it. */
-	xQueueSend( xTxCDC, &cByte, usbNO_BLOCK );
-}
-/*------------------------------------------------------------*/
-
-static void prvSendZLP( void )
-{
-unsigned portLONG ulStatus;
-
-	/* Wait until the FIFO is free - even though we are not going to use it.
-	THERE IS NO TIMEOUT HERE! */
-	while( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] & AT91C_UDP_TXPKTRDY )
-	{
-		vTaskDelay( usbSHORTEST_DELAY );
-	}
-
-	portENTER_CRITICAL();
-	{
-		/* Cancel any further pending data */
-		pxControlTx.ulTotalDataLength = pxControlTx.ulNextCharIndex;
-
-		/* Set the TXPKTRDY bit to cause a transmission with no data. */
-		ulStatus = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ];
-		usbCSR_SET_BIT( &ulStatus, AT91C_UDP_TXPKTRDY );
-		AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulStatus;
-	}
-	portEXIT_CRITICAL();
-}
-/*------------------------------------------------------------*/
-
-static void prvSendStall( void )
-{
-	unsigned portLONG ulStatus;
-
-	portENTER_CRITICAL();
-	{
-		/* Force a stall by simply setting the FORCESTALL bit in the CSR. */
-		ulStatus = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ];
-		usbCSR_SET_BIT( &ulStatus, AT91C_UDP_FORCESTALL );
-		AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulStatus;
-	}
-	portEXIT_CRITICAL();
-}
-/*------------------------------------------------------------*/
-
-static void prvResetEndPoints( void )
-{
-unsigned portLONG ulTemp;
-
-	eDriverState = eJUST_RESET;
-	ucControlState = 0;
-
-	/* Reset all the end points. */
-	AT91C_BASE_UDP->UDP_RSTEP  = usbEND_POINT_RESET_MASK;
-	AT91C_BASE_UDP->UDP_RSTEP  = ( unsigned portLONG ) 0x00;
-
-	/* Enable data to be sent and received. */
-	AT91C_BASE_UDP->UDP_FADDR = AT91C_UDP_FEN;
-
-	/* Repair the configuration end point. */
-	portENTER_CRITICAL();
-	{
-		ulTemp = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ];
-		usbCSR_SET_BIT( &ulTemp, ( ( unsigned portLONG ) ( AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_CTRL ) ) );
-		AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulTemp;
-		AT91C_BASE_UDP->UDP_IER = AT91C_UDP_EPINT0;
-	}
-	portEXIT_CRITICAL();
-	uiCurrentBank = AT91C_UDP_RX_DATA_BK0;
-}
-/*------------------------------------------------------------*/
-
-static void prvProcessEndPoint0Interrupt( xISRStatus *pxMessage )
-{
-static xUSB_REQUEST xRequest;
-unsigned portLONG ulRxBytes;
-
-	/* Get number of bytes received, if any */
-	ulRxBytes = pxMessage->ulCSR0 >> 16;
-	ulRxBytes &= usbRX_COUNT_MASK;
-
-	if( pxMessage->ulCSR0 & AT91C_UDP_TXCOMP )
-	{
-		/* We received a TX complete interrupt.  What we do depends on
-		what we sent to get this interrupt. */
-
-		if( eDriverState == eJUST_GOT_CONFIG )
-		{
-			/* We sent an acknowledgement of a SET_CONFIG request.  We
-			are now at the end of the enumeration.
-			
-			TODO: Config 0 sets unconfigured state, should enter Address state.
-			Request for unsupported config should stall. */
-			AT91C_BASE_UDP->UDP_GLBSTATE = AT91C_UDP_CONFG;
-			
-			/* Set up endpoints */
-			portENTER_CRITICAL();
-			{
-				unsigned portLONG ulTemp;
-
-				/* Set endpoint 1 to bulk-out */
-				ulTemp = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ];					
-				usbCSR_SET_BIT( &ulTemp, AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_BULK_OUT );
-				AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] = ulTemp;		
-				AT91C_BASE_UDP->UDP_IER = AT91C_UDP_EPINT1;
-				/* Set endpoint 2 to bulk-in */
-				ulTemp = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_2 ];					
-				usbCSR_SET_BIT( &ulTemp, AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_BULK_IN );
-				AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_2 ] = ulTemp;		
-				AT91C_BASE_UDP->UDP_IER = AT91C_UDP_EPINT2;
-					/* Set endpoint 3 to interrupt-in, enable it, and enable interrupts */
-				ulTemp = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_3 ];					
-				usbCSR_SET_BIT( &ulTemp, AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_INT_IN );
-				AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_3 ] = ulTemp;		
-				/*AT91F_UDP_EnableIt( AT91C_BASE_UDP, AT91C_UDP_EPINT3 );				 */
-			}
-			portEXIT_CRITICAL();
-
-			eDriverState = eREADY_TO_SEND;
-		}		
-		else if( eDriverState == eJUST_GOT_ADDRESS )
-		{
-			/* We sent an acknowledgement of a SET_ADDRESS request.  Move
-			to the addressed state. */
-			if( ulReceivedAddress != ( unsigned portLONG ) 0 )
-			{			
-				AT91C_BASE_UDP->UDP_GLBSTATE = AT91C_UDP_FADDEN;
-			}
-			else
-			{
-				AT91C_BASE_UDP->UDP_GLBSTATE = 0;
-			}			
-
-			AT91C_BASE_UDP->UDP_FADDR = ( AT91C_UDP_FEN | ulReceivedAddress );		
-			eDriverState = eNOTHING;
-		}
-		else
-		{		
-			/* The TXCOMP was not for any special type of transmission.  See
-			if there is any more data to send. */
-			prvSendNextSegment();
-		}
-	}
-
-	if( pxMessage->ulCSR0 & AT91C_UDP_RX_DATA_BK0 )
-	{
-		/* Received a control data packet.  May be a 0-length ACK or a data stage. */
-		unsigned portCHAR ucBytesToGet;
-	 
-		/* Got data.  Cancel any outgoing data. */
-		pxControlTx.ulNextCharIndex = pxControlTx.ulTotalDataLength;
-		
-		 /* Determine how many bytes we need to receive. */
-		ucBytesToGet = pxControlRx.ulTotalDataLength - pxControlRx.ulNextCharIndex;
-		if( ucBytesToGet > ulRxBytes ) 
-		{	
-			ucBytesToGet = ulRxBytes;
-		}
-
-		/* If we're not expecting any data, it's an ack - just quit now. */
-		if( !ucBytesToGet )
-		{
-			 return;
-		}
-
-		/* Get the required data and update the index. */
-		memcpy( pxControlRx.ucBuffer, pxMessage->ucFifoData, ucBytesToGet );
-		pxControlRx.ulNextCharIndex += ucBytesToGet;	
-	}
-
-	if( pxMessage->ulCSR0 & AT91C_UDP_RXSETUP )
-	{
-		/* Received a SETUP packet.  May be followed by data packets. */
-
-		if( ulRxBytes >= usbEXPECTED_NUMBER_OF_BYTES )
-		{		 		
-			/* Create an xUSB_REQUEST variable from the raw bytes array. */
-
-			xRequest.ucReqType = pxMessage->ucFifoData[ usbREQUEST_TYPE_INDEX ];
-			xRequest.ucRequest = pxMessage->ucFifoData[ usbREQUEST_INDEX ];
-
-			xRequest.usValue = pxMessage->ucFifoData[ usbVALUE_HIGH_BYTE ];
-			xRequest.usValue <<= 8;
-			xRequest.usValue |= pxMessage->ucFifoData[ usbVALUE_LOW_BYTE ];
-						
-			xRequest.usIndex = pxMessage->ucFifoData[ usbINDEX_HIGH_BYTE ];
-			xRequest.usIndex <<= 8;
-			xRequest.usIndex |= pxMessage->ucFifoData[ usbINDEX_LOW_BYTE ];
-			
-			xRequest.usLength = pxMessage->ucFifoData[ usbLENGTH_HIGH_BYTE ];
-			xRequest.usLength <<= 8;
-			xRequest.usLength |= pxMessage->ucFifoData[ usbLENGTH_LOW_BYTE ];
-
-			pxControlRx.ulNextCharIndex = 0;
-			if( ! (xRequest.ucReqType & 0x80) ) /* Host-to-Device transfer, may need to get data first */
-			{
-				if( xRequest.usLength > usbMAX_CONTROL_MESSAGE_SIZE )
-				{	
-					/* Too big!  No space for control data, stall and abort. */
-					prvSendStall();
-					return;
-				}
-
-				pxControlRx.ulTotalDataLength = xRequest.usLength;
-			}
-			else
-			{
-				/* We're sending the data, don't wait for any. */
-				pxControlRx.ulTotalDataLength = 0; 
-			}
-		}
-	}
-
-	/* See if we've got a pending request and all its associated data ready */
-	if( ( pxMessage->ulCSR0 & ( AT91C_UDP_RX_DATA_BK0 | AT91C_UDP_RXSETUP ) ) 
-		&& ( pxControlRx.ulNextCharIndex >= pxControlRx.ulTotalDataLength ) )
-	{
-		unsigned portCHAR ucRequest;
-
-		/* Manipulate the ucRequestType and the ucRequest parameters to 
-		generate a zero based request selection.  This is just done to 
-		break up the requests into subsections for clarity.  The 
-		alternative would be to have more huge switch statement that would
-		be difficult to optimise. */
-		ucRequest = ( ( xRequest.ucReqType & 0x60 ) >> 3 );
-		ucRequest |= ( xRequest.ucReqType & 0x03 );
-			
-		switch( ucRequest )
-		{
-			case usbSTANDARD_DEVICE_REQUEST:	
-				/* Standard Device request */
-				prvHandleStandardDeviceRequest( &xRequest );
-				break;
-
-			case usbSTANDARD_INTERFACE_REQUEST:	
-				/* Standard Interface request */
-				prvHandleStandardInterfaceRequest( &xRequest );
-				break;
-
-			case usbSTANDARD_END_POINT_REQUEST:	
-				/* Standard Endpoint request */
-				prvHandleStandardEndPointRequest( &xRequest );
-				break;
-
-			case usbCLASS_INTERFACE_REQUEST:	
-				/* Class Interface request */
-				prvHandleClassInterfaceRequest( &xRequest );
-				break;
-
-			default:	/* This is not something we want to respond to. */
-				prvSendStall();	
-		}
-	}
-}
-/*------------------------------------------------------------*/
-
-static void prvGetStandardDeviceDescriptor( xUSB_REQUEST *pxRequest )
-{
-	/* The type is in the high byte.  Return whatever has been requested. */
-	switch( ( pxRequest->usValue & 0xff00 ) >> 8 )
-	{
-		case usbDESCRIPTOR_TYPE_DEVICE:
-			prvSendControlData( ( unsigned portCHAR * ) &pxDeviceDescriptor, pxRequest->usLength, sizeof( pxDeviceDescriptor ), pdTRUE );
-			break;
-
-		case usbDESCRIPTOR_TYPE_CONFIGURATION:
-			prvSendControlData( ( unsigned portCHAR * ) &( pxConfigDescriptor ), pxRequest->usLength, sizeof( pxConfigDescriptor ), pdTRUE );
-			break;
-
-		case usbDESCRIPTOR_TYPE_STRING:
-
-			/* The index to the string descriptor is the lower byte. */
-			switch( pxRequest->usValue & 0xff )
-			{			
-				case usbLANGUAGE_STRING:
-					prvSendControlData( ( unsigned portCHAR * ) &pxLanguageStringDescriptor, pxRequest->usLength, sizeof(pxLanguageStringDescriptor), pdTRUE );
-					break;
-
-				case usbMANUFACTURER_STRING:
-					prvSendControlData( ( unsigned portCHAR * ) &pxManufacturerStringDescriptor, pxRequest->usLength, sizeof( pxManufacturerStringDescriptor ), pdTRUE );
-					break;
-
-				case usbPRODUCT_STRING:
-					prvSendControlData( ( unsigned portCHAR * ) &pxProductStringDescriptor, pxRequest->usLength, sizeof( pxProductStringDescriptor ), pdTRUE );
-					break;
-
-				case usbCONFIGURATION_STRING:
-					prvSendControlData( ( unsigned portCHAR * ) &pxConfigurationStringDescriptor, pxRequest->usLength, sizeof( pxConfigurationStringDescriptor ), pdTRUE );
-					break;
-
-				case usbINTERFACE_STRING:
-					prvSendControlData( ( unsigned portCHAR * ) &pxInterfaceStringDescriptor, pxRequest->usLength, sizeof( pxInterfaceStringDescriptor ), pdTRUE );
-					break;
-
-				default:
-					prvSendStall();
-					break;
-			}
-			break;
-
-		default:
-			prvSendStall();
-			break;
-	}
-}
-/*------------------------------------------------------------*/
-
-static void prvHandleStandardDeviceRequest( xUSB_REQUEST *pxRequest )
-{
-unsigned portSHORT usStatus = 0;
-
-	switch( pxRequest->ucRequest )
-	{
-		case usbGET_STATUS_REQUEST:
-			/* Just send two byte dummy status. */
-			prvSendControlData( ( unsigned portCHAR * ) &usStatus, sizeof( usStatus ), sizeof( usStatus ), pdFALSE );
-			break;
-
-		case usbGET_DESCRIPTOR_REQUEST:
-			/* Send device descriptor */
-			prvGetStandardDeviceDescriptor( pxRequest );
-			break;
-
-		case usbGET_CONFIGURATION_REQUEST:
-			/* Send selected device configuration */
-			prvSendControlData( ( unsigned portCHAR * ) &ucUSBConfig, sizeof( ucUSBConfig ), sizeof( ucUSBConfig ), pdFALSE );
-			break;
-
-		case usbSET_FEATURE_REQUEST:
-			prvSendZLP();
-			break;
-
-		case usbSET_ADDRESS_REQUEST:			
-			/* Get assigned address and send ack, but don't implement new address until we get a TXCOMP */
-			prvSendZLP();			
-			eDriverState = eJUST_GOT_ADDRESS;			
-			ulReceivedAddress = ( unsigned portLONG ) pxRequest->usValue;
-			break;
-
-		case usbSET_CONFIGURATION_REQUEST:
-			/* Ack SET_CONFIGURATION request, but don't implement until TXCOMP */
-			ucUSBConfig = ( unsigned portCHAR ) ( pxRequest->usValue & 0xff );
-			eDriverState = eJUST_GOT_CONFIG;
-			prvSendZLP();
-			break;
-
-		default:
-			/* Any unsupported request results in a STALL response. */
-			prvSendStall();
-			break;
-	}
-}
-/*------------------------------------------------------------*/
-
-static void prvHandleClassInterfaceRequest( xUSB_REQUEST *pxRequest )
-{
-	switch( pxRequest->ucRequest )
-	{
-		case usbSEND_ENCAPSULATED_COMMAND:
-			prvSendStall();
-			break;
-
-		case usbGET_ENCAPSULATED_RESPONSE:
-			prvSendStall();
-			break;
-
-		case usbSET_LINE_CODING:
-			/* Set line coding - baud rate, data bits, parity, stop bits */
-			prvSendZLP();
-			memcpy( ( void * ) pxLineCoding, pxControlRx.ucBuffer, sizeof( pxLineCoding ) );
-			break;
-
-		case usbGET_LINE_CODING:
-			/* Get line coding */
-			prvSendControlData( (unsigned portCHAR *) &pxLineCoding, pxRequest->usLength, sizeof( pxLineCoding ), pdFALSE );
-			break;
-
-		case usbSET_CONTROL_LINE_STATE:
-			/* D0: 1=DTR, 0=No DTR,  D1: 1=Activate Carrier, 0=Deactivate carrier (RTS, half-duplex) */
-			prvSendZLP();
-			ucControlState = pxRequest->usValue;
-			break;
-
-		default:
-			prvSendStall();
-			break;
-	}
-}
-/*------------------------------------------------------------*/
-
-static void prvGetStandardInterfaceDescriptor( xUSB_REQUEST *pxRequest )
-{
-	switch( ( pxRequest->usValue & ( unsigned portSHORT ) 0xff00 ) >> 8 )
-	{
-		default:
-			prvSendStall();
-			break;
-	}
-}
-/*-----------------------------------------------------------*/
-
-static void prvHandleStandardInterfaceRequest( xUSB_REQUEST *pxRequest )
-{
-unsigned portSHORT usStatus = 0;
-
-	switch( pxRequest->ucRequest )
-	{
-		case usbGET_STATUS_REQUEST:
-			/* Send dummy 2 bytes. */
-			prvSendControlData( ( unsigned portCHAR * ) &usStatus, sizeof( usStatus ), sizeof( usStatus ), pdFALSE );
-			break;
-
-		case usbGET_DESCRIPTOR_REQUEST:
-			prvGetStandardInterfaceDescriptor( pxRequest ); 
-			break;
-
-		/* This minimal implementation does not respond to these. */
-		case usbGET_INTERFACE_REQUEST:
-		case usbSET_FEATURE_REQUEST:
-		case usbSET_INTERFACE_REQUEST:	
-
-		default:
-			prvSendStall();
-			break;
-	}
-}
-/*-----------------------------------------------------------*/
-
-static void prvHandleStandardEndPointRequest( xUSB_REQUEST *pxRequest )
-{
-	switch( pxRequest->ucRequest )
-	{
-		/* This minimal implementation does not expect to respond to these. */
-		case usbGET_STATUS_REQUEST:
-		case usbCLEAR_FEATURE_REQUEST: 
-		case usbSET_FEATURE_REQUEST:
-
-		default:			
-			prvSendStall();
-			break;
-	}
-}
-/*-----------------------------------------------------------*/
-
-static void vDetachUSBInterface( void)
-{
-	/* Setup the PIO for the USB pull up resistor. */
-	AT91C_BASE_PIOA->PIO_PER = AT91C_PIO_PA16;
-	AT91C_BASE_PIOA->PIO_OER = AT91C_PIO_PA16;
-
-
-	/* Disable pull up */
-	AT91C_BASE_PIOA->PIO_SODR = AT91C_PIO_PA16;
-} 
-/*-----------------------------------------------------------*/
-
-static void vInitUSBInterface( void )
-{
-extern void ( vUSB_ISR )( void );
-
-	/* Create the queue used to communicate between the USB ISR and task. */
-	xUSBInterruptQueue = xQueueCreate( usbQUEUE_LENGTH + 1, sizeof( xISRStatus * ) );
-	
-	/* Create the queues used to hold Rx and Tx characters. */
-	xRxCDC = xQueueCreate( USB_CDC_QUEUE_SIZE, ( unsigned portCHAR ) sizeof( signed portCHAR ) );
-	xTxCDC = xQueueCreate( USB_CDC_QUEUE_SIZE + 1, ( unsigned portCHAR ) sizeof( signed portCHAR ) );
-
-	if( (!xUSBInterruptQueue) || (!xRxCDC) || (!xTxCDC) )
-	{	
-		/* Not enough RAM to create queues!. */
-		return;
-	}
-	
-	/* Initialise a few state variables. */
-	pxControlTx.ulNextCharIndex = ( unsigned portLONG ) 0;
-	pxControlRx.ulNextCharIndex = ( unsigned portLONG ) 0;
-	ucUSBConfig = ( unsigned portCHAR ) 0;
-	eDriverState = eNOTHING;
-	ucControlState = 0;
-	uiCurrentBank = AT91C_UDP_RX_DATA_BK0;
-
-
-	/* HARDWARE SETUP */
-
-	/* Set the PLL USB Divider */
-	AT91C_BASE_CKGR->CKGR_PLLR |= AT91C_CKGR_USBDIV_1;
-
-	/* Enables the 48MHz USB clock UDPCK and System Peripheral USB Clock. */
-	AT91C_BASE_PMC->PMC_SCER = AT91C_PMC_UDP;
-	AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_UDP);
-
-	/* Setup the PIO for the USB pull up resistor. */
-	AT91C_BASE_PIOA->PIO_PER = AT91C_PIO_PA16;
-	AT91C_BASE_PIOA->PIO_OER = AT91C_PIO_PA16;
-
-
-	/* Start without the pullup - this will get set at the end of this 
-	function. */
-   	AT91C_BASE_PIOA->PIO_SODR = AT91C_PIO_PA16;
-
-
-	/* When using the USB debugger the peripheral registers do not always get
-	set to the correct default values.  To make sure set the relevant registers
-	manually here. */
-	AT91C_BASE_UDP->UDP_IDR = ( unsigned portLONG ) 0xffffffff;
-	AT91C_BASE_UDP->UDP_ICR = ( unsigned portLONG ) 0xffffffff;
-	AT91C_BASE_UDP->UDP_CSR[ 0 ] = ( unsigned portLONG ) 0x00;
-	AT91C_BASE_UDP->UDP_CSR[ 1 ] = ( unsigned portLONG ) 0x00;
-	AT91C_BASE_UDP->UDP_CSR[ 2 ] = ( unsigned portLONG ) 0x00;
-	AT91C_BASE_UDP->UDP_CSR[ 3 ] = ( unsigned portLONG ) 0x00;
-	AT91C_BASE_UDP->UDP_GLBSTATE = 0;
-	AT91C_BASE_UDP->UDP_FADDR = 0;
-
-	/* Enable the transceiver. */
-	AT91C_UDP_TRANSCEIVER_ENABLE = 0;
-
-	/* Enable the USB interrupts - other interrupts get enabled as the 
-	enumeration process progresses. */
-	AT91F_AIC_ConfigureIt( AT91C_ID_UDP, usbINTERRUPT_PRIORITY, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, ( void (*)( void ) ) vUSB_ISR );
-	AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_UDP;
-
-
-	/* Wait a short while before making our presence known. */
-	vTaskDelay( usbINIT_DELAY );
-	AT91C_BASE_PIOA->PIO_CODR = AT91C_PIO_PA16;
-}
-/*-----------------------------------------------------------*/
-
-static void prvSendControlData( unsigned portCHAR *pucData, unsigned portSHORT usRequestedLength, unsigned portLONG ulLengthToSend, portLONG lSendingDescriptor )
-{
-	if( ( ( unsigned portLONG ) usRequestedLength < ulLengthToSend ) )
-	{
-		/* Cap the data length to that requested. */
-		ulLengthToSend = ( unsigned portSHORT ) usRequestedLength;
-	}
-	else if( ( ulLengthToSend < ( unsigned portLONG ) usRequestedLength ) && lSendingDescriptor )
-	{
-		/* We are sending a descriptor.  If the descriptor is an exact 
-		multiple of the FIFO length then it will have to be terminated
-		with a NULL packet.  Set the state to indicate this if
-		necessary. */
-		if( ( ulLengthToSend % usbFIFO_LENGTH ) == 0 )
-		{
-			eDriverState = eSENDING_EVEN_DESCRIPTOR;
-		}
-	}
-
-	/* Here we assume that the previous message has been sent.  THERE IS NO
-	BUFFER OVERFLOW PROTECTION HERE.
-
-	Copy the data to send into the buffer as we cannot send it all at once
-	(if it is greater than 8 bytes in length). */
-	memcpy( pxControlTx.ucBuffer, pucData, ulLengthToSend );
-
-	/* Reinitialise the buffer index so we start sending from the start of 
-	the data. */
-	pxControlTx.ulTotalDataLength = ulLengthToSend;
-	pxControlTx.ulNextCharIndex = ( unsigned portLONG ) 0;
-
-	/* Send the first 8 bytes now.  The rest will get sent in response to 
-	TXCOMP interrupts. */
-	prvSendNextSegment();
-}
-/*-----------------------------------------------------------*/
-
-static void prvSendNextSegment( void )
-{
-volatile unsigned portLONG ulNextLength, ulStatus, ulLengthLeftToSend;
-
-	/* Is there any data to send? */
-	if( pxControlTx.ulTotalDataLength > pxControlTx.ulNextCharIndex )
-	{
-		ulLengthLeftToSend = pxControlTx.ulTotalDataLength - pxControlTx.ulNextCharIndex;
-	
-		/* We can only send 8 bytes to the fifo at a time. */
-		if( ulLengthLeftToSend > usbFIFO_LENGTH )
-		{
-			ulNextLength = usbFIFO_LENGTH;
-		}
-		else
-		{
-			ulNextLength = ulLengthLeftToSend;
-		}
-
-		/* Wait until we can place data in the fifo.  THERE IS NO TIMEOUT
-		HERE! */
-		while( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] & AT91C_UDP_TXPKTRDY )
-		{
-			vTaskDelay( usbSHORTEST_DELAY );
-		}
-
-		/* Write the data to the FIFO. */
-		while( ulNextLength > ( unsigned portLONG ) 0 )
-		{
-			AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_0 ] = pxControlTx.ucBuffer[ pxControlTx.ulNextCharIndex ];
-	
-			ulNextLength--;
-			pxControlTx.ulNextCharIndex++;
-		}
-	
-		/* Start the transmission. */
-		portENTER_CRITICAL();
-		{
-			ulStatus = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ];
-			usbCSR_SET_BIT( &ulStatus, ( ( unsigned portLONG ) 0x10 ) );
-			AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulStatus;
-		}
-		portEXIT_CRITICAL();
-	}
-	else
-	{
-		/* There is no data to send.  If we were sending a descriptor and the 
-		descriptor was an exact multiple of the max packet size then we need
-		to send a null to terminate the transmission. */
-		if( eDriverState == eSENDING_EVEN_DESCRIPTOR )
-		{
-			prvSendZLP();
-			eDriverState = eNOTHING;
-		}
-	}
-}
-
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/USB/USB-CDC.h b/Demo/lwIP_Demo_Rowley_ARM7/USB/USB-CDC.h
deleted file mode 100644
index 8adb15e44..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/USB/USB-CDC.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
-	FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
-
-	This file is part of the FreeRTOS.org distribution.
-
-	FreeRTOS.org is free software; you can redistribute it and/or modify
-	it under the terms of the GNU General Public License as published by
-	the Free Software Foundation; either version 2 of the License, or
-	(at your option) any later version.
-
-	FreeRTOS.org is distributed in the hope that it will be useful,
-	but WITHOUT ANY WARRANTY; without even the implied warranty of
-	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-	GNU General Public License for more details.
-
-	You should have received a copy of the GNU General Public License
-	along with FreeRTOS.org; if not, write to the Free Software
-	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-
-	A special exception to the GPL can be applied should you wish to distribute
-	a combined work that includes FreeRTOS.org, without being obliged to provide
-	the source code for any proprietary components.  See the licensing section
-	of http://www.FreeRTOS.org for full details of how and when the exception
-	can be applied.
-
-	***************************************************************************
-	See http://www.FreeRTOS.org for documentation, latest information, license
-	and contact details.  Please ensure to read the configuration and relevant
-	port sections of the online documentation.
-	***************************************************************************
-*/
-
-#ifndef USB_CDC_H
-#define USB_CDC_H
-
-#include "usb.h"
-
-#define USB_CDC_QUEUE_SIZE    200
-
-/* Structure used to take a snapshot of the USB status from within the ISR. */
-typedef struct X_ISR_STATUS
-{
-	unsigned portLONG ulISR;
-	unsigned portLONG ulCSR0;
-	unsigned portCHAR ucFifoData[ 8 ];
-} xISRStatus;
-
-/* Structure used to hold the received requests. */
-typedef struct 
-{
-	unsigned portCHAR ucReqType;
-	unsigned portCHAR ucRequest;
-	unsigned portSHORT usValue;
-	unsigned portSHORT usIndex;
-	unsigned portSHORT usLength;
-} xUSB_REQUEST;
-
-typedef enum
-{
-	eNOTHING,
-	eJUST_RESET,
-	eJUST_GOT_CONFIG,
-	eJUST_GOT_ADDRESS,
-	eSENDING_EVEN_DESCRIPTOR,
-	eREADY_TO_SEND
-} eDRIVER_STATE;
-
-/* Structure used to control the data being sent to the host. */
-typedef struct
-{
-	unsigned portCHAR ucBuffer[ usbMAX_CONTROL_MESSAGE_SIZE ];
-	unsigned portLONG ulNextCharIndex;
-	unsigned portLONG ulTotalDataLength;
-} xCONTROL_MESSAGE;
-
-/*-----------------------------------------------------------*/
-void vUSBCDCTask( void *pvParameters );
-
-/* Send cByte down the USB port.  Characters are simply buffered and not
-sent unless the port is connected. */
-void vUSBSendByte( portCHAR cByte );
-
-
-#endif
-
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/USB/USBIsr.c b/Demo/lwIP_Demo_Rowley_ARM7/USB/USBIsr.c
deleted file mode 100644
index e8c0b06f7..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/USB/USBIsr.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
-  FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
-
-  This file is part of the FreeRTOS.org distribution.
-
-  FreeRTOS.org is free software; you can redistribute it and/or modify
-  it under the terms of the GNU General Public License as published by
-  the Free Software Foundation; either version 2 of the License, or
-  (at your option) any later version.
-
-  FreeRTOS.org is distributed in the hope that it will be useful,
-  but WITHOUT ANY WARRANTY; without even the implied warranty of
-  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-  GNU General Public License for more details.
-
-  You should have received a copy of the GNU General Public License
-  along with FreeRTOS.org; if not, write to the Free Software
-  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-
-  A special exception to the GPL can be applied should you wish to distribute
-  a combined work that includes FreeRTOS.org, without being obliged to provide
-  the source code for any proprietary components.  See the licensing section 
-  of http://www.FreeRTOS.org for full details of how and when the exception
-  can be applied.
-
-  ***************************************************************************
-  See http://www.FreeRTOS.org for documentation, latest information, license 
-  and contact details.  Please ensure to read the configuration and relevant 
-  port sections of the online documentation.
-  ***************************************************************************
-*/
-
-
-/* 
-  BASIC INTERRUPT DRIVEN DRIVER FOR USB. 
-
-  This file contains all the usb components that must be compiled
-  to ARM mode.  The components that can be compiled to either ARM or THUMB
-  mode are contained in USB-CDC.c.
-
-*/
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-#include "queue.h"
-
-/* Demo application includes. */
-#include "Board.h"
-#include "usb.h"
-#include "USB-CDC.h"
-
-#define usbINT_CLEAR_MASK	(AT91C_UDP_TXCOMP | AT91C_UDP_STALLSENT | AT91C_UDP_RXSETUP | AT91C_UDP_RX_DATA_BK0 | AT91C_UDP_RX_DATA_BK1 )
-/*-----------------------------------------------------------*/
-
-/* Messages and queue used to communicate between the ISR and the USB task. */
-static xISRStatus xISRMessages[ usbQUEUE_LENGTH + 1 ];
-extern xQueueHandle xUSBInterruptQueue;
-/*-----------------------------------------------------------*/
-
-/* The ISR can cause a context switch so is declared naked. */
-void vUSB_ISR( void ) __attribute__ ((naked));
-
-/*-----------------------------------------------------------*/
-
-
-void vUSB_ISR( void )
-{
-	/* This ISR can cause a context switch.  Therefore a call to the 
-	portENTER_SWITCHING_ISR() macro is made.  This must come BEFORE any 
-	stack variable declarations. */
-	portENTER_SWITCHING_ISR();
-
-	/* Now variables can be declared. */
-	portCHAR cTaskWokenByPost = pdFALSE; 
-	static volatile unsigned portLONG ulNextMessage = 0;
-	xISRStatus *pxMessage;
-	unsigned portLONG ulRxBytes;
-	unsigned portCHAR ucFifoIndex;
-
-    /* Use the next message from the array. */
-	pxMessage = &( xISRMessages[ ( ulNextMessage & usbQUEUE_LENGTH ) ] );
-	ulNextMessage++;
-
-    /* Save UDP ISR state for task-level processing. */
-	pxMessage->ulISR = AT91C_BASE_UDP->UDP_ISR;
-	pxMessage->ulCSR0 = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ];
-
-    /* Clear interrupts from ICR. */
-	AT91C_BASE_UDP->UDP_ICR = AT91C_BASE_UDP->UDP_IMR | AT91C_UDP_ENDBUSRES;
-	
-    
-	/* Process incoming FIFO data.  Must set DIR (if needed) and clear RXSETUP 
-	before exit. */
-
-    /* Read CSR and get incoming byte count. */
-	ulRxBytes = ( pxMessage->ulCSR0 >> 16 ) & usbRX_COUNT_MASK;
-	
-	/* Receive control transfers on endpoint 0. */
-	if( pxMessage->ulCSR0 & ( AT91C_UDP_RXSETUP | AT91C_UDP_RX_DATA_BK0 ) )
-	{
-		/* Save FIFO data buffer for either a SETUP or DATA stage */
-		for( ucFifoIndex = 0; ucFifoIndex < ulRxBytes; ucFifoIndex++ )
-		{
-			pxMessage->ucFifoData[ ucFifoIndex ] = AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_0 ];
-		}
-
-		/* Set direction for data stage.  Must be done before RXSETUP is 
-		cleared. */
-		if( ( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] & AT91C_UDP_RXSETUP ) )
-		{
-			if( ulRxBytes && ( pxMessage->ucFifoData[ usbREQUEST_TYPE_INDEX ] & 0x80 ) )
-			{
-				AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] |= AT91C_UDP_DIR;
-
-				/* Might not be wise in an ISR! */
-				while( !(AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] & AT91C_UDP_DIR) );
-			}
-
-			/* Clear RXSETUP */
-			AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] &= ~AT91C_UDP_RXSETUP;
-
-			/* Might not be wise in an ISR! */
-			while ( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] & AT91C_UDP_RXSETUP );
-		}
-		else
-		{
-		   /* Clear RX_DATA_BK0 */
-		   AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] &= ~AT91C_UDP_RX_DATA_BK0;
-
-		   /* Might not be wise in an ISR! */
-		   while ( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] & AT91C_UDP_RX_DATA_BK0 );
-		}
-	}
-	
-	/* If we received data on endpoint 1, disable its interrupts until it is 
-	processed in the main loop */
-	if( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] & ( AT91C_UDP_RX_DATA_BK0 | AT91C_UDP_RX_DATA_BK1 ) )
-	{
-		AT91C_BASE_UDP->UDP_IDR = AT91C_UDP_EPINT1;
-	}
-	
-	AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] &= ~( AT91C_UDP_TXCOMP | AT91C_UDP_STALLSENT );
-     
-	/* Clear interrupts for the other endpoints, retain data flags for endpoint 
-	1. */
-	AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] &= ~( AT91C_UDP_TXCOMP | AT91C_UDP_STALLSENT | AT91C_UDP_RXSETUP );
-	AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_2 ] &= ~usbINT_CLEAR_MASK;
-	AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_3 ] &= ~usbINT_CLEAR_MASK;
-
-	/* Post ISR data to queue for task-level processing */
-	cTaskWokenByPost = xQueueSendFromISR( xUSBInterruptQueue, &pxMessage, cTaskWokenByPost );
-
-	/* Clear AIC to complete ISR processing */
-	AT91C_BASE_AIC->AIC_EOICR = 0;
-
-	/* Do a task switch if needed */
-	portEXIT_SWITCHING_ISR( cTaskWokenByPost )
-}
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/USB/descriptors.h b/Demo/lwIP_Demo_Rowley_ARM7/USB/descriptors.h
deleted file mode 100644
index bd353db0e..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/USB/descriptors.h
+++ /dev/null
@@ -1,203 +0,0 @@
-/*
-	FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
-
-	This file is part of the FreeRTOS.org distribution.
-
-	FreeRTOS.org is free software; you can redistribute it and/or modify
-	it under the terms of the GNU General Public License as published by
-	the Free Software Foundation; either version 2 of the License, or
-	(at your option) any later version.
-
-	FreeRTOS.org is distributed in the hope that it will be useful,
-	but WITHOUT ANY WARRANTY; without even the implied warranty of
-	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-	GNU General Public License for more details.
-
-	You should have received a copy of the GNU General Public License
-	along with FreeRTOS.org; if not, write to the Free Software
-	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-
-	A special exception to the GPL can be applied should you wish to distribute
-	a combined work that includes FreeRTOS.org, without being obliged to provide
-	the source code for any proprietary components.  See the licensing section
-	of http://www.FreeRTOS.org for full details of how and when the exception
-	can be applied.
-
-	***************************************************************************
-	See http://www.FreeRTOS.org for documentation, latest information, license
-	and contact details.  Please ensure to read the configuration and relevant
-	port sections of the online documentation.
-	***************************************************************************
-*/
-
-/*
-	- DESCRIPTOR DEFINITIONS -
-*/
-
-/* String descriptors used during the enumeration process.
-These take the form:
-
-{
-	Length of descriptor,
-	Descriptor type,
-	Data
-}
-*/
-
-const portCHAR pxLanguageStringDescriptor[] =
-{
-	4,
-	usbDESCRIPTOR_TYPE_STRING,
-	0x09, 0x04
-};
-
-const portCHAR pxManufacturerStringDescriptor[] = 
-{
-	18,
-	usbDESCRIPTOR_TYPE_STRING,
-
-	'F', 0x00, 'r', 0x00, 'e', 0x00, 'e', 0x00, 'R', 0x00, 'T', 0x00, 'O', 0x00, 'S', 0x00
-};
-
-const portCHAR pxProductStringDescriptor[] = 
-{
-	36,
-	usbDESCRIPTOR_TYPE_STRING,
-
-	'F', 0x00, 'r', 0x00, 'e', 0x00, 'e', 0x00, 'R', 0x00, 'T', 0x00, 'O', 0x00, 'S', 0x00, ' ', 0x00, 'C', 0x00, 'D', 0x00,
-	'C', 0x00, ' ', 0x00, 'D', 0x00, 'E', 0x00, 'M', 0x00, 'O', 0x00
-};
-
-const portCHAR pxConfigurationStringDescriptor[] = 
-{
-	38,
-	usbDESCRIPTOR_TYPE_STRING,
-
-	'C', 0x00, 'o', 0x00, 'n', 0x00, 'f', 0x00, 'i', 0x00, 'g', 0x00, 'u', 0x00, 'r', 0x00, 'a', 0x00, 't', 0x00, 'i', 0x00,
-	'o', 0x00, 'n', 0x00, ' ', 0x00, 'N', 0x00, 'a', 0x00, 'm', 0x00, 'e', 0x00
-};
-
-const portCHAR pxInterfaceStringDescriptor[] = 
-{
-	30,
-	usbDESCRIPTOR_TYPE_STRING,
-
-	'I', 0x00, 'n', 0x00, 't', 0x00, 'e', 0x00, 'r', 0x00, 'f', 0x00, 'a', 0x00, 'c', 0x00, 'e', 0x00, ' ', 0x00, 'N', 0x00,
-	'a', 0x00, 'm', 0x00, 'e', 0x00
-};
-
-/* Device should properly be 0x134A:0x9001, using 0x05F9:0xFFFF for Linux testing */
-const char pxDeviceDescriptor[] = 
-{
-	/* Device descriptor */
-	0x12,								/* bLength				*/
-	0x01,								/* bDescriptorType		*/
-	0x10, 0x01,							/* bcdUSBL				*/
-	0x02,								/* bDeviceClass:		*/
-	0x00,								/* bDeviceSubclass:		*/
-	0x00,								/* bDeviceProtocol:		*/
-	0x08,								/* bMaxPacketSize0		*/
-	0x03, 0xEB,							/* idVendorL			*/
-	0x20, 0x09,							/* idProductL			*/
-	0x10, 0x01,							/* bcdDeviceL			*/
-	usbMANUFACTURER_STRING,  			/* iManufacturer		*/
-	usbPRODUCT_STRING,					/* iProduct				*/
-	0x00,								/* SerialNumber			*/
-	0x01								/* bNumConfigs			*/
-};
-
-const char pxConfigDescriptor[] = {
-
-	/* Configuration 1 descriptor
-	Here we define two interfaces (0 and 1) and a total of 3 endpoints.
-	Interface 0 is a CDC Abstract Control Model interface with one interrupt-in endpoint.
-	Interface 1 is a CDC Data Interface class, with a bulk-in and bulk-out endpoint.
-	Endpoint 0 gets used as the CDC management element.
-	*/
-	0x09,				/* CbLength								*/
-	0x02,				/* CbDescriptorType					  	*/
-	0x43, 0x00,			/* CwTotalLength 2 EP + Control		?	*/
-	0x02,				/* CbNumInterfaces			  			*/
-	0x01,				/* CbConfigurationValue					*/
-	usbCONFIGURATION_STRING,/* CiConfiguration					*/
-	usbBUS_POWERED,		/* CbmAttributes Bus powered + Remote Wakeup*/
-	0x32,				/* CMaxPower: 100mA						*/
-
-	/* Communication Class Interface Descriptor Requirement		*/
-	0x09,				/* bLength								*/
-	0x04,				/* bDescriptorType						*/
-	0x00,				/* bInterfaceNumber						*/
-	0x00,				/* bAlternateSetting					*/
-	0x01,				/* bNumEndpoints						*/
-	0x02,				/* bInterfaceClass: Comm Interface Class */
-	0x02,				/* bInterfaceSubclass: Abstract Control Model*/
-	0x00,				/* bInterfaceProtocol					*/
-	usbINTERFACE_STRING,/* iInterface							*/
-
-	/* Header Functional Descriptor								*/
-	0x05,				/* bLength								*/
-	0x24,				/* bDescriptor type: CS_INTERFACE		*/
-	0x00,				/* bDescriptor subtype: Header Func Desc*/
-	0x10, 0x01,			/* bcdCDC:1.1  							*/
-
-	/* ACM Functional Descriptor								*/
-	0x04,				/* bFunctionLength						*/
-	0x24,				/* bDescriptor type: CS_INTERFACE		*/
-	0x02,				/* bDescriptor subtype: ACM Func Desc	*/
-	0x00,				/* bmCapabilities: We don't support squat*/
-
-	/* Union Functional Descriptor								*/
-	0x05,				/* bFunctionLength						*/
-	0x24,				/* bDescriptor type: CS_INTERFACE		*/
-	0x06,				/* bDescriptor subtype: Union Func Desc	*/
-	0x00,				/* bMasterInterface: CDC Interface		*/
-	0x01,				/* bSlaveInterface0: Data Class Interface*/
-
-	/* Call Management Functional Descriptor
-	0 in D1 and D0 indicates that device does not handle call management*/
-	0x05,				/* bFunctionLength						*/
-	0x24,				/* bDescriptor type: CS_INTERFACE		*/
-	0x01,				/* bDescriptor subtype: Call Management Func*/
-	0x00,				/* bmCapabilities: D1 + D0				*/
-	0x01,				/* bDataInterface: Data Class Interface 1*/
-
-	/* CDC Control - Endpoint 3 descriptor
-	This endpoint serves as a notification element.				*/
-
-	0x07,				/* bLength								*/
-	0x05,				/* bDescriptorType						*/
-	0x83,				/* bEndpointAddress, Endpoint 03 - IN	*/
-	0x03,				/* bmAttributes	  INT					*/
-	0x08, 0x00,			/* wMaxPacketSize: 8 bytes		   		*/
-	0xFF,				/* bInterval							*/
-
-	/* Data Class Interface Descriptor Requirement				*/
-	0x09,				/* bLength								*/
-	0x04,				/* bDescriptorType						*/
-	0x01,				/* bInterfaceNumber						*/
-	0x00,				/* bAlternateSetting					*/
-	0x02,				/* bNumEndPoints						*/
-	0x0A,				/* bInterfaceClass						*/
-	0x00,				/* bInterfaceSubclass					*/
-	0x00,				/* bInterfaceProtocol					*/
-	0x00,				/* iInterface							*/
-
-	/* CDC Data - Endpoint 1 descriptor */
-	0x07,				/* bLenght								*/
-	0x05,				/* bDescriptorType						*/
-	0x01,				/* bEndPointAddress, Endpoint 01 - OUT	*/
-	0x02,				/* bmAttributes BULK					*/
-	64,					/* wMaxPacketSize						*/
-	0x00,
-	0x00,				/* bInterval							*/
-
-	/* CDC Data - Endpoint 2 descriptor */
-	0x07,				/* bLength								*/
-	0x05,				/* bDescriptorType						*/
-	0x82,				/* bEndPointAddress, Endpoint 02 - IN	*/
-	0x02,				/* bmAttributes BULK					*/
-	64,					/* wMaxPacketSize						*/
-	0x00,
-	0x00				/* bInterval							*/
-};
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/USB/usb.h b/Demo/lwIP_Demo_Rowley_ARM7/USB/usb.h
deleted file mode 100644
index 0dc1f5abe..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/USB/usb.h
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
-	FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
-
-	This file is part of the FreeRTOS.org distribution.
-
-	FreeRTOS.org is free software; you can redistribute it and/or modify
-	it under the terms of the GNU General Public License as published by
-	the Free Software Foundation; either version 2 of the License, or
-	(at your option) any later version.
-
-	FreeRTOS.org is distributed in the hope that it will be useful,
-	but WITHOUT ANY WARRANTY; without even the implied warranty of
-	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-	GNU General Public License for more details.
-
-	You should have received a copy of the GNU General Public License
-	along with FreeRTOS.org; if not, write to the Free Software
-	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-
-	A special exception to the GPL can be applied should you wish to distribute
-	a combined work that includes FreeRTOS.org, without being obliged to provide
-	the source code for any proprietary components.  See the licensing section
-	of http://www.FreeRTOS.org for full details of how and when the exception
-	can be applied.
-
-	***************************************************************************
-	See http://www.FreeRTOS.org for documentation, latest information, license
-	and contact details.  Please ensure to read the configuration and relevant
-	port sections of the online documentation.
-	***************************************************************************
-*/
-
-/* Descriptor type definitions. */
-#define usbDESCRIPTOR_TYPE_DEVICE			( 0x01 )
-#define usbDESCRIPTOR_TYPE_CONFIGURATION	( 0x02 )
-#define usbDESCRIPTOR_TYPE_STRING			( 0x03 )
-
-/* USB request type definitions. */
-#define usbGET_REPORT_REQUEST				( 0x01 )
-#define usbGET_IDLE_REQUEST					( 0x02 )
-#define usbGET_PROTOCOL_REQUEST				( 0x03 )
-#define usbSET_REPORT_REQUEST				( 0x09 )
-#define usbSET_IDLE_REQUEST					( 0x0A )
-#define usbSET_PROTOCOL_REQUEST				( 0x0B )
-#define usbGET_CONFIGURATION_REQUEST		( 0x08 )
-#define usbGET_STATUS_REQUEST				( 0x00 )
-#define usbCLEAR_FEATURE_REQUEST			( 0x01 )
-#define usbSET_FEATURE_REQUEST				( 0x03 )
-#define usbSET_ADDRESS_REQUEST				( 0x05 )
-#define usbGET_DESCRIPTOR_REQUEST			( 0x06 )
-#define usbSET_CONFIGURATION_REQUEST		( 0x09 )
-#define usbGET_INTERFACE_REQUEST			( 0x0A )
-#define usbSET_INTERFACE_REQUEST			( 0x0B )
-
-/* ACM Requests */
-#define usbSEND_ENCAPSULATED_COMMAND		( 0x00 )
-#define usbGET_ENCAPSULATED_RESPONSE		( 0x01 )
-#define usbSET_LINE_CODING					( 0x20 )
-#define usbGET_LINE_CODING					( 0x21 )
-#define usbSET_CONTROL_LINE_STATE			( 0x22 )
-
-/* Misc USB definitions. */
-#define usbDEVICE_CLASS_VENDOR_SPECIFIC		( 0xFF )
-#define usbBUS_POWERED						( 0x80 )
-#define usbHID_REPORT_DESCRIPTOR			( 0x22 )
-#define AT91C_UDP_TRANSCEIVER_ENABLE		( *( ( unsigned long * ) 0xfffb0074 ) )
-
-/* Index to the various string. */
-#define usbLANGUAGE_STRING					( 0 )
-#define usbMANUFACTURER_STRING				( 1 )
-#define usbPRODUCT_STRING					( 2 )
-#define usbCONFIGURATION_STRING				( 3 )
-#define usbINTERFACE_STRING					( 4 )
-
-/* Defines fields of standard SETUP request.  Now in normal order. */
-#define usbREQUEST_TYPE_INDEX				( 0 )
-#define usbREQUEST_INDEX					( 1 )
-#define usbVALUE_HIGH_BYTE					( 3 )
-#define usbVALUE_LOW_BYTE					( 2 )
-#define usbINDEX_HIGH_BYTE					( 5 )
-#define usbINDEX_LOW_BYTE					( 4 )
-#define usbLENGTH_HIGH_BYTE					( 7 )
-#define usbLENGTH_LOW_BYTE					( 6 )
-
-/* Misc application definitions. */
-#define usbINTERRUPT_PRIORITY				( 3 )
-#define usbQUEUE_LENGTH						( 0x3 )	/* Must have all bits set! */
-#define usbFIFO_LENGTH						( ( unsigned portLONG ) 8 )
-#define usbEND_POINT_0						( 0 )
-#define usbEND_POINT_1						( 1 )
-#define usbEND_POINT_2						( 2 )
-#define usbEND_POINT_3						( 3 )
-#define usbMAX_CONTROL_MESSAGE_SIZE			( 128 )
-#define usbRX_COUNT_MASK					( ( unsigned portLONG ) 0x7ff )
-#define AT91C_UDP_STALLSENT					AT91C_UDP_ISOERROR
-#define usbSHORTEST_DELAY					( ( portTickType ) 1 )
-#define usbINIT_DELAY						( ( portTickType ) 1000 / portTICK_RATE_MS )
-#define usbSHORT_DELAY						( ( portTickType ) 50 / portTICK_RATE_MS )
-#define usbEND_POINT_RESET_MASK				( ( unsigned portLONG ) 0x0f )
-#define usbDATA_INC							( ( portCHAR ) 5 )
-#define usbEXPECTED_NUMBER_OF_BYTES			( ( unsigned portLONG ) 8 )
-
-/* Control request types. */
-#define usbSTANDARD_DEVICE_REQUEST			( 0 )
-#define usbSTANDARD_INTERFACE_REQUEST		( 1 )
-#define usbSTANDARD_END_POINT_REQUEST		( 2 )
-#define usbCLASS_INTERFACE_REQUEST			( 5 )
-
-
-/* Macros to manipulate the control and status registers.  These registers 
-cannot be accessed using a direct read modify write operation outside of the 
-ISR as some bits are left unchanged by writing with a 0, and some are left 
-unchanged by writing with a 1. */
-
-
-#define usbCSR_SET_BIT( pulValueNow, ulBit )											\
-{																						\
-	/* Set TXCOMP, RX_DATA_BK0, RXSETUP, */												\
-	/* STALLSENT and RX_DATA_BK1 to 1 so the */											\
-	/* write has no effect. */															\
-	( * ( ( unsigned portLONG * ) pulValueNow ) ) |= ( unsigned portLONG ) 0x4f;		\
-																						\
-	/* Clear the FORCE_STALL and TXPKTRDY bits */										\
-	/* so the write has no effect. */													\
-	( * ( ( unsigned portLONG * ) pulValueNow ) ) &= ( unsigned portLONG ) 0xffffffcf;	\
-																						\
-	/* Set whichever bit we want set. */												\
-	( * ( ( unsigned portLONG * ) pulValueNow ) ) |= ( ulBit );							\
-}
-
-#define usbCSR_CLEAR_BIT( pulValueNow, ulBit )											\
-{																						\
-	/* Set TXCOMP, RX_DATA_BK0, RXSETUP, */												\
-	/* STALLSENT and RX_DATA_BK1 to 1 so the */											\
-	/* write has no effect. */															\
-	( * ( ( unsigned portLONG * ) pulValueNow ) ) |= ( unsigned portLONG ) 0x4f;		\
-																						\
-	/* Clear the FORCE_STALL and TXPKTRDY bits */										\
-	/* so the write has no effect. */													\
-	( * ( ( unsigned portLONG * ) pulValueNow ) ) &= ( unsigned portLONG ) 0xffffffcf;	\
-																						\
-	/* Clear whichever bit we want clear. */											\
-	( * ( ( unsigned portLONG * ) pulValueNow ) ) &= ( ~ulBit );						\
-}
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/atmel-rom.ld b/Demo/lwIP_Demo_Rowley_ARM7/atmel-rom.ld
deleted file mode 100644
index db22b4acd..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/atmel-rom.ld
+++ /dev/null
@@ -1,49 +0,0 @@
-MEMORY 
-{
-	flash	: ORIGIN = 0x00100000, LENGTH = 256K
-	ram		: ORIGIN = 0x00200000, LENGTH = 64K
-}
-
-__stack_end__ = 0x00200000 + 64K - 4;
-
-SECTIONS 
-{
-	. = 0;
-	startup : { *(.startup)} >flash
-
-	prog : 
-	{
-		*(.text)
-		*(.rodata)
-		*(.rodata*)
-		*(.glue_7)
-		*(.glue_7t)
-	} >flash
-
-	__end_of_text__ = .;
-
-	.data : 
-	{
-		__data_beg__ = .;
-		__data_beg_src__ = __end_of_text__;
-		*(.data)
-		__data_end__ = .;
-	} >ram AT>flash
-
-	.bss : 
-	{
-		__bss_beg__ = .;
-		*(.bss)
-	} >ram
-
-	/* Align here to ensure that the .bss section occupies space up to
-	_end.  Align after .bss to ensure correct alignment even if the
-	.bss section disappears because there are no input sections.  */
-	. = ALIGN(32 / 8);
-}
-	. = ALIGN(32 / 8);
-	_end = .;
-	_bss_end__ = . ; __bss_end__ = . ; __end__ = . ;
-	PROVIDE (end = .);
-
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/boot.s b/Demo/lwIP_Demo_Rowley_ARM7/boot.s
deleted file mode 100644
index 88fac35db..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/boot.s
+++ /dev/null
@@ -1,161 +0,0 @@
-	/* Sample initialization file */
-
-	.extern main
-	.extern exit
-	.extern AT91F_LowLevelInit
-
-	.text
-	.code 32
-
-
-	.align  0
-
-	.extern __stack_end__
-	.extern __bss_beg__
-	.extern __bss_end__
-	.extern __data_beg__
-	.extern __data_end__
-	.extern __data+beg_src__
-
-	.global start
-	.global endless_loop
-
-	/* Stack Sizes */
-    .set  UND_STACK_SIZE, 0x00000004
-    .set  ABT_STACK_SIZE, 0x00000004
-    .set  FIQ_STACK_SIZE, 0x00000004
-    .set  IRQ_STACK_SIZE, 0X00000400
-    .set  SVC_STACK_SIZE, 0x00000400
-
-	/* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */
-    .set  MODE_USR, 0x10            /* User Mode */
-    .set  MODE_FIQ, 0x11            /* FIQ Mode */
-    .set  MODE_IRQ, 0x12            /* IRQ Mode */
-    .set  MODE_SVC, 0x13            /* Supervisor Mode */
-    .set  MODE_ABT, 0x17            /* Abort Mode */
-    .set  MODE_UND, 0x1B            /* Undefined Mode */
-    .set  MODE_SYS, 0x1F            /* System Mode */
-
-    .equ  I_BIT, 0x80               /* when I bit is set, IRQ is disabled */
-    .equ  F_BIT, 0x40               /* when F bit is set, FIQ is disabled */
-
-
-start:
-_start:
-_mainCRTStartup:
-
-	/* Setup a stack for each mode - note that this only sets up a usable stack
-	for system/user, SWI and IRQ modes.   Also each mode is setup with
-	interrupts initially disabled. */
-    ldr   r0, .LC6
-    msr   CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode */
-    mov   sp, r0
-    sub   r0, r0, #UND_STACK_SIZE
-    msr   CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */
-    mov   sp, r0
-    sub   r0, r0, #ABT_STACK_SIZE
-    msr   CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */
-    mov   sp, r0
-    sub   r0, r0, #FIQ_STACK_SIZE
-    msr   CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */
-    mov   sp, r0
-    sub   r0, r0, #IRQ_STACK_SIZE
-    msr   CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */
-    mov   sp, r0
-    sub   r0, r0, #SVC_STACK_SIZE
-    msr   CPSR_c, #MODE_SYS|I_BIT|F_BIT /* System Mode */
-    mov   sp, r0
-
-	/* We want to start in supervisor mode.  Operation will switch to system
-	mode when the first task starts. */
-	msr   CPSR_c, #MODE_SVC|I_BIT|F_BIT
-
-    bl		AT91F_LowLevelInit
-
-	/* Clear BSS. */
-
-	mov     a2, #0			/* Fill value */
-	mov		fp, a2			/* Null frame pointer */
-	mov		r7, a2			/* Null frame pointer for Thumb */
-
-	ldr		r1, .LC1		/* Start of memory block */
-	ldr		r3, .LC2		/* End of memory block */
-	subs	r3, r3, r1      /* Length of block */
-	beq		.end_clear_loop
-	mov		r2, #0
-
-.clear_loop:
-	strb	r2, [r1], #1
-	subs	r3, r3, #1
-	bgt		.clear_loop
-
-.end_clear_loop:
-
-	/* Initialise data. */
-
-	ldr		r1, .LC3		/* Start of memory block */
-	ldr		r2, .LC4		/* End of memory block */
-	ldr		r3, .LC5
-	subs	r3, r3, r1		/* Length of block */
-	beq		.end_set_loop
-
-.set_loop:
-	ldrb	r4, [r2], #1
-	strb	r4, [r1], #1
-	subs	r3, r3, #1
-	bgt		.set_loop
-
-.end_set_loop:
-
-	mov		r0, #0          /* no arguments  */
-	mov		r1, #0          /* no argv either */
-
-    ldr lr, =main	
-	bx	lr
-
-endless_loop:
-	b               endless_loop
-
-
-	.align 0
-
-	.LC1:
-	.word   __bss_beg__
-	.LC2:
-	.word   __bss_end__
-	.LC3:
-	.word   __data_beg__
-	.LC4:
-	.word   __data_beg_src__
-	.LC5:
-	.word   __data_end__
-	.LC6:
-	.word	__stack_end__
-
-
-	/* Setup vector table.  Note that undf, pabt, dabt, fiq just execute
-	a null loop. */
-
-.section .startup,"ax"
-         .code 32
-         .align 0
-
-	b     _start						/* reset - _start			*/
-	ldr   pc, _undf						/* undefined - _undf		*/
-	ldr   pc, _swi						/* SWI - _swi				*/
-	ldr   pc, _pabt						/* program abort - _pabt	*/
-	ldr   pc, _dabt						/* data abort - _dabt		*/
-	nop									/* reserved					*/
-	ldr   pc, [pc,#-0xF20]				/* IRQ - read the AIC		*/
-	ldr   pc, _fiq						/* FIQ - _fiq				*/
-
-_undf:  .word __undf                    /* undefined				*/
-_swi:   .word swi_handler				/* SWI						*/
-_pabt:  .word __pabt                    /* program abort			*/
-_dabt:  .word __dabt                    /* data abort				*/
-_fiq:   .word __fiq                     /* FIQ						*/
-
-__undf: b     .                         /* undefined				*/
-__pabt: b     .                         /* program abort			*/
-__dabt: b     .                         /* data abort				*/
-__fiq:  b     .                         /* FIQ						*/
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/crt0.s b/Demo/lwIP_Demo_Rowley_ARM7/crt0.s
deleted file mode 100644
index a16c22012..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/crt0.s
+++ /dev/null
@@ -1,265 +0,0 @@
-/*****************************************************************************
- * Copyright (c) 2001, 2002 Rowley Associates Limited.                       *
- *                                                                           *
- * This file may be distributed under the terms of the License Agreement     *
- * provided with this software.                                              *
- *                                                                           *
- * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE   *
- * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
- *****************************************************************************/
-  .section .init, "ax"
-  .code 32
-  .align 0
-                
-  .weak _start
-  .global __start
-  .global __gccmain
-  .extern main
-  .extern exit
-
-/*****************************************************************************
- * Function    : _start                                                      *
- * Description : Main entry point and startup code for C system.             *
- *****************************************************************************/
-_start:
-__start:                        
-  mrs r0, cpsr
-  bic r0, r0, #0x1F
-
-  /* Setup stacks */ 
-  orr r1, r0, #0x1B /* Undefined mode */
-  msr cpsr_cxsf, r1
-  ldr sp, =__stack_und_end__
-  
-  orr r1, r0, #0x17 /* Abort mode */
-  msr cpsr_cxsf, r1
-  ldr sp, =__stack_abt_end__
-
-  orr r1, r0, #0x12 /* IRQ mode */
-  msr cpsr_cxsf, r1
-  ldr sp, =__stack_irq_end__
-
-  orr r1, r0, #0x11 /* FIQ mode */
-  msr cpsr_cxsf, r1
-  ldr sp, =__stack_fiq_end__
-
-  orr r1, r0, #0x13 /* Supervisor mode */
-  msr cpsr_cxsf, r1
-  ldr sp, =__stack_svc_end__
-#ifdef SUPERVISOR_START
-  /* Start application in supervisor mode */
-  ldr r1, =__stack_end__ /* Setup user/system mode stack */ 
-  mov r2, sp
-  stmfd r2!, {r1}
-  ldmfd r2, {sp}^
-#else
-  /* Start application in system mode */
-  orr r1, r0, #0x1F /* System mode */
-  msr cpsr_cxsf, r1
-  ldr sp, =__stack_end__
-#endif
-  
-  /* Copy from initialised data section to data section (if necessary). */
-  ldr r0, =__data_load_start__
-  ldr r1, =__data_start__
-  cmp r0, r1
-  beq copy_data_end
-  
-  ldr r2, =__data_end__
-  subs r2, r2, r1
-  beq copy_data_end
-  
-copy_data_loop:
-  ldrb r3, [r0], #+1
-  strb r3, [r1], #+1
-  subs r2, r2, #1
-  bne copy_data_loop
-copy_data_end:  
-
-  /* Copy from initialised text section to text section (if necessary). */
-  ldr r0, =__text_load_start__
-  ldr r1, =__text_start__
-  cmp r0, r1
-  beq copy_text_end
-  
-  ldr r2, =__text_end__
-  subs r2, r2, r1
-  beq copy_text_end
-  
-copy_text_loop:
-  ldrb r3, [r0], #+1
-  strb r3, [r1], #+1
-  subs r2, r2, #1
-  bne copy_text_loop
-copy_text_end:  
-
-  /* Copy from initialised fast_text section to fast_text section (if necessary). */
-  ldr r0, =__fast_load_start__
-  ldr r1, =__fast_start__
-  cmp r0, r1
-  beq copy_fast_end
-  
-  ldr r2, =__fast_end__
-  subs r2, r2, r1
-  beq copy_fast_end
-  
-copy_fast_loop:
-  ldrb r3, [r0], #+1
-  strb r3, [r1], #+1
-  subs r2, r2, #1
-  bne copy_fast_loop
-copy_fast_end:  
-
-  /* Zero the bss. */
-  ldr r0, =__bss_start__
-  ldr r1, =__bss_end__
-  mov r2, #0
-zero_bss_loop:
-  cmp r0, r1
-  beq zero_bss_end
-  strb r2, [r0], #+1
-  b zero_bss_loop
-zero_bss_end:    
-
-#ifdef CHECK  
-  /* Check data */
-  ldr r0, =__data_load_start__
-  ldr r1, =__data_start__
-  cmp r0, r1
-  beq check_data_end
-  ldr r2, =__data_end__
-  subs r2, r2, r1
-  beq check_data_end
-  
-check_data_loop:
-  ldrb r3, [r0], #+1
-  ldrb r4, [r1], #+1
-  cmp r3, r4
-  bne data_error_loop
-  subs r2, r2, #1
-  bne check_data_loop
-check_data_end:  
-
-  /* Check text */
-  ldr r0, =__text_load_start__
-  ldr r1, =__text_start__
-  cmp r0, r1
-  beq check_text_end
-  ldr r2, =__text_end__
-  subs r2, r2, r1
-  beq check_text_end
-  
-check_text_loop:
-  ldrb r3, [r0], #+1
-  ldrb r4, [r1], #+1
-  cmp r3, r4
-  bne text_error_loop
-  subs r2, r2, #1
-  bne check_text_loop
-check_text_end:  
-
-  /* Check fast */
-  ldr r0, =__fast_load_start__
-  ldr r1, =__fast_start__
-  cmp r0, r1
-  beq check_fast_end
-  ldr r2, =__fast_end__
-  subs r2, r2, r1
-  beq check_fast_end
-  
-check_fast_loop:
-  ldrb r3, [r0], #+1
-  ldrb r4, [r1], #+1
-  cmp r3, r4
-  bne fast_error_loop
-  subs r2, r2, #1
-  bne check_fast_loop
-check_fast_end:  
-
-  /* Check bss */
-  ldr r0, =__bss_start__
-  ldr r1, =__bss_end__
-  mov r2, #0
-check_bss_loop:
-  cmp r0, r1
-  beq check_bss_end
-  ldrb r2, [r0], #+1
-  cmp r2, #0
-  bne bss_error_loop  
-  b check_bss_loop
-check_bss_end:    
-#endif
-
-  /* Initialise the heap */
-  ldr r0, = __heap_start__
-  ldr r1, = __heap_end__
-  sub r1, r1, r0     /* r1 = r1-r0 */ 
-  mov r2, #0
-  str r2, [r0], #+4 /* *r0++ = 0 */
-  str r1, [r0]      /* *r0 = __heap_end__ - __heap_start__ */
-
-  /* Call constructors */
-  ldr r0, =__ctors_start__
-  ldr r1, =__ctors_end__
-ctor_loop:
-  cmp r0, r1
-  beq ctor_end
-  ldr r2, [r0], #+4
-  stmfd sp!, {r0-r1}
-  mov lr, pc
-  mov pc, r2
-  ldmfd sp!, {r0-r1}
-  b ctor_loop
-ctor_end:
-
-  /* Setup initial call frame */
-  mov lr, #4
-  mov r12, sp
-  stmfd sp!, {r11-r12, lr-pc}
-  sub r11, r12, #0x00000004
-
-start:
-  /* Jump to main entry point */
-  mov r0, #0
-  mov r1, #0
-  ldr r2, =main
-  mov lr, pc
-#ifdef __ARM_ARCH_3__
-  mov pc, r2
-#else    
-  bx r2
-#endif
-
-  /* Call destructors */
-  ldr r0, =__dtors_start__
-  ldr r1, =__dtors_end__
-dtor_loop:
-  cmp r0, r1
-  beq dtor_end
-  ldr r2, [r0], #+4
-  stmfd sp!, {r0-r1}
-  mov lr, pc
-  mov pc, r2
-  ldmfd sp!, {r0-r1}
-  b dtor_loop
-dtor_end:
-
-  /* Return from main, loop forever. */
-exit_loop:
-  b exit_loop
-
-#ifdef CHECK
-data_error_loop:
-  b data_error_loop
-
-text_error_loop:
-  b text_error_loop
-  
-fast_error_loop:
-  b fast_error_loop
-  
-bss_error_loop:
-  b bss_error_loop  
-#endif
-  
-                  
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/flash_placement.xml b/Demo/lwIP_Demo_Rowley_ARM7/flash_placement.xml
deleted file mode 100644
index 0df08fd26..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/flash_placement.xml
+++ /dev/null
@@ -1,29 +0,0 @@
-
-
-  
-    
-    
-    
-    
-    
-    
-    
-    
-    
-  
-  
-    
-    
-    
-    
-    
-    
-    
-    
-    
-  
-  
-    
-    
-  
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/CHANGELOG b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/CHANGELOG
deleted file mode 100644
index 67a56cd62..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/CHANGELOG
+++ /dev/null
@@ -1,536 +0,0 @@
-FUTURE
-
-  * TODO: The lwIP source code makes some invalid assumptions on processor
-    word-length, storage sizes and alignment. See the mailing lists for
-    problems with exoteric (/DSP) architectures showing these problems.
-    We still have to fix some of these issues neatly.
-
-  * TODO: the ARP layer is not protected against concurrent access. If
-    you run from a multitasking OS, serialize access to ARP (called from
-    your network device driver and from a timeout thread.)
-
-HISTORY
-
-(HEAD)
-
-  2004-12-28 Leon Woestenberg 
-  * etharp.*: Disabled multiple packets on the ARP queue.
-    This clashes with TCP queueing.
-
-  2004-11-28 Leon Woestenberg 
-  * etharp.*: Fixed race condition from ARP request to ARP timeout.
-    Halved the ARP period, doubled the period counts.
-    ETHARP_MAX_PENDING now should be at least 2. This prevents
-    the counter from reaching 0 right away (which would allow
-    too little time for ARP responses to be received).
-    
-  2004-11-25 Leon Woestenberg 
-  * dhcp.c: Decline messages were not multicast but unicast.
-  * etharp.c: ETHARP_CREATE is renamed to ETHARP_TRY_HARD.
-    Do not try hard to insert arbitrary packet's source address,
-    etharp_ip_input() now calls etharp_update() without ETHARP_TRY_HARD. 
-    etharp_query() now always DOES call ETHARP_TRY_HARD so that users
-    querying an address will see it appear in the cache (DHCP could
-    suffer from this when a server invalidly gave an in-use address.)
-  * ipv4/ip_addr.h: Renamed ip_addr_maskcmp() to _netcmp() as we are
-    comparing network addresses (identifiers), not the network masks
-    themselves.
-  * ipv4/ip_addr.c: ip_addr_isbroadcast() now checks that the given
-    IP address actually belongs to the network of the given interface.
-
-  2004-11-24 Kieran Mansley 
-  * tcp.c: Increment pcb->snd_buf when ACK is received in SYN_SENT state.
-
-(STABLE-1_1_0-RC1)
-
-  2004-10-16 Kieran Mansley 
-  * tcp.c: Add code to tcp_recved() to send an ACK (window update) immediately,
-	even if one is already pending, if the rcv_wnd is above a threshold
-	(currently TCP_WND/2). This avoids waiting for a timer to expire to send a
-	delayed ACK in order to open the window if the stack is only receiving data.
-
-  2004-09-12 Kieran Mansley 
-  * tcp*.*: Retransmit time-out handling improvement by Sam Jansen.
-
-  2004-08-20 Tony Mountifield 
-  * etharp.c: Make sure the first pbuf queued on an ARP entry
-    is properly ref counted.
-
-  2004-07-27 Tony Mountifield 
-  * debug.h: Added (int) cast in LWIP_DEBUGF() to avoid compiler
-    warnings about comparison.
-  * pbuf.c: Stopped compiler complaining of empty if statement
-    when LWIP_DEBUGF() empty.  Closed an unclosed comment.
-  * tcp.c: Stopped compiler complaining of empty if statement
-    when LWIP_DEBUGF() empty.
-  * ip.h Corrected IPH_TOS() macro: returns a byte, so doesn't need htons().
-  * inet.c: Added a couple of casts to quiet the compiler.
-    No need to test isascii(c) before isdigit(c) or isxdigit(c).
-
-  2004-07-22 Tony Mountifield 
-  * inet.c: Made data types consistent in inet_ntoa().
-    Added casts for return values of checksum routines, to pacify compiler.
-  * ip_frag.c, tcp_out.c, sockets.c, pbuf.c
-    Small corrections to some debugging statements, to pacify compiler.
-
-  2004-07-21 Tony Mountifield 
-  * etharp.c: Removed spurious semicolon and added missing end-of-comment.
-  * ethernetif.c Updated low_level_output() to match prototype for
-    netif->linkoutput and changed low_level_input() similarly for consistency.
-  * api_msg.c: Changed recv_raw() from int to u8_t, to match prototype
-    of raw_recv() in raw.h and so avoid compiler error.
-  * sockets.c: Added trivial (int) cast to keep compiler happier.
-  * ip.c, netif.c Changed debug statements to use the tidier ip4_addrN() macros.
-  
-(STABLE-1_0_0)
-
-  ++ Changes:
-
-  2004-07-05 Leon Woestenberg 
-  * sockets.*: Restructured LWIP_PRIVATE_TIMEVAL. Make sure
-    your cc.h file defines this either 1 or 0. If non-defined,
-    defaults to 1.
-  * .c: Added  and  includes where used.
-  * etharp.c: Made some array indices unsigned.
-
-  2004-06-27 Leon Woestenberg 
-  * netif.*: Added netif_set_up()/down().
-  * dhcp.c: Changes to restart program flow.
-
-  2004-05-07 Leon Woestenberg 
-  * etharp.c: In find_entry(), instead of a list traversal per candidate, do a
-    single-pass lookup for different candidates. Should exploit locality.
-
-  2004-04-29 Leon Woestenberg 
-  * tcp*.c: Cleaned up source comment documentation for Doxygen processing.
-  * opt.h: ETHARP_ALWAYS_INSERT option removed to comply with ARP RFC.
-  * etharp.c: update_arp_entry() only adds new ARP entries when adviced to by
-    the caller. This deprecates the ETHARP_ALWAYS_INSERT overrule option.
-
-  ++ Bug fixes:
-
-  2004-04-27 Leon Woestenberg 
-  * etharp.c: Applied patch of bug #8708 by Toni Mountifield with a solution
-    suggested by Timmy Brolin. Fix for 32-bit processors that cannot access
-    non-aligned 32-bit words, such as soms 32-bit TCP/IP header fields. Fix
-    is to prefix the 14-bit Ethernet headers with two padding bytes.
-
-  2004-04-23 Leon Woestenberg 
-  * ip_addr.c: Fix in the ip_addr_isbroadcast() check.
-  * etharp.c: Fixed the case where the packet that initiates the ARP request
-    is not queued, and gets lost. Fixed the case where the packets destination
-    address is already known; we now always queue the packet and perform an ARP
-    request.
-  
-(STABLE-0_7_0)
-
-  ++ Bug fixes:
-
-  * Fixed TCP bug for SYN_SENT to ESTABLISHED state transition.
-  * Fixed TCP bug in dequeueing of FIN from out of order segment queue.
-  * Fixed two possible NULL references in rare cases.
-
-(STABLE-0_6_6)
-
-  ++ Bug fixes:
-
-  * Fixed DHCP which did not include the IP address in DECLINE messages.
-
-  ++ Changes:
-
-  * etharp.c has been hauled over a bit.
-
-(STABLE-0_6_5)
-
-  ++ Bug fixes:
-
-  * Fixed TCP bug induced by bad window resizing with unidirectional TCP traffic.
-  * Packets sent from ARP queue had invalid source hardware address.
-
-  ++ Changes:
-
-  * Pass-by ARP requests do now update the cache.
-
-  ++ New features:
-
-  * No longer dependent on ctype.h.
-  * New socket options.
-  * Raw IP pcb support.
-
-(STABLE-0_6_4)
-
-  ++ Bug fixes:
-
-  * Some debug formatters and casts fixed.
-  * Numereous fixes in PPP.
-
-  ++ Changes:
-
-  * DEBUGF now is LWIP_DEBUGF
-  * pbuf_dechain() has been re-enabled.
-  * Mentioned the changed use of CVS branches in README.
-
-(STABLE-0_6_3)
-
-  ++ Bug fixes:
-
-  * Fixed pool pbuf memory leak in pbuf_alloc().
-    Occured if not enough PBUF_POOL pbufs for a packet pbuf chain.
-    Reported by Savin Zlobec.
-
-  * PBUF_POOL chains had their tot_len field not set for non-first
-    pbufs. Fixed in pbuf_alloc().
-
-  ++ New features:
-
-  * Added PPP stack contributed by Marc Boucher
-
-  ++ Changes:
-
-  * Now drops short packets for ICMP/UDP/TCP protocols. More robust.
-
-  * ARP queueuing now queues the latest packet instead of the first.
-    This is the RFC recommended behaviour, but can be overridden in
-    lwipopts.h.
-
-(0.6.2)
-
-  ++ Bugfixes:
-
-  * TCP has been fixed to deal with the new use of the pbuf->ref
-    counter.
-
-  * DHCP dhcp_inform() crash bug fixed.
-
-  ++ Changes:
-
-  * Removed pbuf_pool_free_cache and pbuf_pool_alloc_cache. Also removed
-    pbuf_refresh(). This has sped up pbuf pool operations considerably.
-    Implemented by David Haas.
-
-(0.6.1)
-
-  ++ New features:
-
-  * The packet buffer implementation has been enhanced to support
-    zero-copy and copy-on-demand for packet buffers which have their
-    payloads in application-managed memory.
-    Implemented by David Haas.
-
-    Use PBUF_REF to make a pbuf refer to RAM. lwIP will use zero-copy
-    if an outgoing packet can be directly sent on the link, or perform
-    a copy-on-demand when necessary.
-
-    The application can safely assume the packet is sent, and the RAM
-    is available to the application directly after calling udp_send()
-    or similar function.
-
-  ++ Bugfixes:
-
-  * ARP_QUEUEING should now correctly work for all cases, including
-    PBUF_REF.
-    Implemented by Leon Woestenberg.
-
-  ++ Changes:
-
-  * IP_ADDR_ANY is no longer a NULL pointer. Instead, it is a pointer
-    to a '0.0.0.0' IP address.
-
-  * The packet buffer implementation is changed. The pbuf->ref counter
-    meaning has changed, and several pbuf functions have been
-    adapted accordingly.
-
-  * netif drivers have to be changed to set the hardware address length field
-    that must be initialized correctly by the driver (hint: 6 for Ethernet MAC).
-    See the contrib/ports/c16x cs8900 driver as a driver example.
-
-  * netif's have a dhcp field that must be initialized to NULL by the driver.
-    See the contrib/ports/c16x cs8900 driver as a driver example.
-
-(0.5.x) This file has been unmaintained up to 0.6.1. All changes are
-  logged in CVS but have not been explained here.
-
-(0.5.3) Changes since version 0.5.2
-
-  ++ Bugfixes:
-
-  * memp_malloc(MEMP_API_MSG) could fail with multiple application
-    threads because it wasn't protected by semaphores.
-
-  ++ Other changes:
-
-  * struct ip_addr now packed.
-
-  * The name of the time variable in arp.c has been changed to ctime
-    to avoid conflicts with the time() function.
-
-(0.5.2) Changes since version 0.5.1
-
-  ++ New features:
-
-  * A new TCP function, tcp_tmr(), now handles both TCP timers.
-
-  ++ Bugfixes:
-
-  * A bug in tcp_parseopt() could cause the stack to hang because of a
-    malformed TCP option.
-
-  * The address of new connections in the accept() function in the BSD
-    socket library was not handled correctly.
-
-  * pbuf_dechain() did not update the ->tot_len field of the tail.
-
-  * Aborted TCP connections were not handled correctly in all
-    situations.
-
-  ++ Other changes:
-
-  * All protocol header structs are now packed.
-
-  * The ->len field in the tcp_seg structure now counts the actual
-    amount of data, and does not add one for SYN and FIN segments.
-
-(0.5.1) Changes since version 0.5.0
-
-  ++ New features:
-
-  * Possible to run as a user process under Linux.
-
-  * Preliminary support for cross platform packed structs.
-
-  * ARP timer now implemented.
-
-  ++ Bugfixes:
-
-  * TCP output queue length was badly initialized when opening
-    connections.
-
-  * TCP delayed ACKs were not sent correctly.
-
-  * Explicit initialization of BSS segment variables.
-
-  * read() in BSD socket library could drop data.
-
-  * Problems with memory alignment.
-
-  * Situations when all TCP buffers were used could lead to
-    starvation.
-
-  * TCP MSS option wasn't parsed correctly.
-
-  * Problems with UDP checksum calculation.
-
-  * IP multicast address tests had endianess problems.
-
-  * ARP requests had wrong destination hardware address.
-
-  ++ Other changes:
-
-  * struct eth_addr changed from u16_t[3] array to u8_t[6].
-
-  * A ->linkoutput() member was added to struct netif.
-
-  * TCP and UDP ->dest_* struct members where changed to ->remote_*.
-
-  * ntoh* macros are now null definitions for big endian CPUs.
-
-(0.5.0) Changes since version 0.4.2
-
-  ++ New features:
-
-  * Redesigned operating system emulation layer to make porting easier.
-
-  * Better control over TCP output buffers.
-
-  * Documenation added.
-
-  ++ Bugfixes:
-
-  * Locking issues in buffer management.
-
-  * Bugfixes in the sequential API.
-
-  * IP forwarding could cause memory leakage. This has been fixed.
-
-  ++ Other changes:
-
-  * Directory structure somewhat changed; the core/ tree has been
-    collapsed.
-
-(0.4.2) Changes since version 0.4.1
-
-  ++ New features:
-
-  * Experimental ARP implementation added.
-
-  * Skeleton Ethernet driver added.
-
-  * Experimental BSD socket API library added.
-
-  ++ Bugfixes:
-
-  * In very intense situations, memory leakage could occur. This has
-    been fixed.
-
-  ++ Other changes:
-
-  * Variables named "data" and "code" have been renamed in order to
-    avoid name conflicts in certain compilers.
-
-  * Variable++ have in appliciable cases been translated to ++variable
-    since some compilers generate better code in the latter case.
-
-(0.4.1) Changes since version 0.4
-
-  ++ New features:
-
-  * TCP: Connection attempts time out earlier than data
-    transmissions. Nagle algorithm implemented. Push flag set on the
-    last segment in a burst.
-
-  * UDP: experimental support for UDP-Lite extensions.
-
-  ++ Bugfixes:
-
-  * TCP: out of order segments were in some cases handled incorrectly,
-    and this has now been fixed. Delayed acknowledgements was broken
-    in 0.4, has now been fixed. Binding to an address that is in use
-    now results in an error. Reset connections sometimes hung an
-    application; this has been fixed.
-
-  * Checksum calculation sometimes failed for chained pbufs with odd
-    lengths. This has been fixed.
-
-  * API: a lot of bug fixes in the API. The UDP API has been improved
-    and tested. Error reporting and handling has been
-    improved. Logical flaws and race conditions for incoming TCP
-    connections has been found and removed.
-
-  * Memory manager: alignment issues. Reallocating memory sometimes
-    failed, this has been fixed.
-
-  * Generic library: bcopy was flawed and has been fixed.
-
-  ++ Other changes:
-
-  * API: all datatypes has been changed from generic ones such as
-    ints, to specified ones such as u16_t. Functions that return
-    errors now have the correct type (err_t).
-
-  * General: A lot of code cleaned up and debugging code removed. Many
-    portability issues have been fixed.
-
-  * The license was changed; the advertising clause was removed.
-
-  * C64 port added.
-
-  * Thanks: Huge thanks go to Dagan Galarneau, Horst Garnetzke, Petri
-    Kosunen, Mikael Caleres, and Frits Wilmink for reporting and
-    fixing bugs!
-
-(0.4) Changes since version 0.3.1
-
-  * Memory management has been radically changed; instead of
-    allocating memory from a shared heap, memory for objects that are
-    rapidly allocated and deallocated is now kept in pools. Allocation
-    and deallocation from those memory pools is very fast. The shared
-    heap is still present but is used less frequently.
-
-  * The memory, memory pool, and packet buffer subsystems now support
-    4-, 2-, or 1-byte alignment.
-
-  * "Out of memory" situations are handled in a more robust way.
-
-  * Stack usage has been reduced.
-
-  * Easier configuration of lwIP parameters such as memory usage,
-    TTLs, statistics gathering, etc. All configuration parameters are
-    now kept in a single header file "lwipopts.h".
-
-  * The directory structure has been changed slightly so that all
-    architecture specific files are kept under the src/arch
-    hierarchy.
-
-  * Error propagation has been improved, both in the protocol modules
-    and in the API.
-
-  * The code for the RTXC architecture has been implemented, tested
-    and put to use.
-
-  * Bugs have been found and corrected in the TCP, UDP, IP, API, and
-    the Internet checksum modules.
-
-  * Bugs related to porting between a 32-bit and a 16-bit architecture
-    have been found and corrected.
-
-  * The license has been changed slightly to conform more with the
-    original BSD license, including the advertisement clause.
-
-(0.3.1) Changes since version 0.3
-
-  * Fix of a fatal bug in the buffer management. Pbufs with allocated
-    RAM never returned the RAM when the pbuf was deallocated.
-
-  * TCP congestion control, window updates and retransmissions did not
-    work correctly. This has now been fixed.
-
-  * Bugfixes in the API.
-
-(0.3) Changes since version 0.2
-
-  * New and improved directory structure. All include files are now
-    kept in a dedicated include/ directory.
-
-  * The API now has proper error handling. A new function,
-    netconn_err(), now returns an error code for the connection in
-    case of errors.
-
-  * Improvements in the memory management subsystem. The system now
-    keeps a pointer to the lowest free memory block. A new function,
-    mem_malloc2() tries to allocate memory once, and if it fails tries
-    to free some memory and retry the allocation.
-
-  * Much testing has been done with limited memory
-    configurations. lwIP now does a better job when overloaded.
-
-  * Some bugfixes and improvements to the buffer (pbuf) subsystem.
-
-  * Many bugfixes in the TCP code:
-
-    - Fixed a bug in tcp_close().
-
-    - The TCP receive window was incorrectly closed when out of
-      sequence segments was received. This has been fixed.
-
-    - Connections are now timed-out of the FIN-WAIT-2 state.
-
-    - The initial congestion window could in some cases be too
-      large. This has been fixed.
-
-    - The retransmission queue could in some cases be screwed up. This
-      has been fixed.
-
-    - TCP RST flag now handled correctly.
-
-    - Out of sequence data was in some cases never delivered to the
-      application. This has been fixed.
-
-    - Retransmitted segments now contain the correct acknowledgment
-      number and advertised window.
-
-    - TCP retransmission timeout backoffs are not correctly computed
-      (ala BSD). After a number of retransmissions, TCP now gives up
-      the connection.
-
-  * TCP connections now are kept on three lists, one for active
-    connections, one for listening connections, and one for
-    connections that are in TIME-WAIT. This greatly speeds up the fast
-    timeout processing for sending delayed ACKs.
-
-  * TCP now provides proper feedback to the application when a
-    connection has been successfully set up.
-
-  * More comments have been added to the code. The code has also been
-    somewhat cleaned up.
-
-(0.2) Initial public release.
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/COPYING b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/COPYING
deleted file mode 100644
index e23898b5e..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/COPYING
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright (c) 2001, 2002 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/FILES b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/FILES
deleted file mode 100644
index 66253196f..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/FILES
+++ /dev/null
@@ -1,4 +0,0 @@
-src/      - The source code for the lwIP TCP/IP stack.
-doc/      - The documentation for lwIP.
-
-See also the FILES file in each subdirectory.
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/README b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/README
deleted file mode 100644
index 4795d3afe..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/README
+++ /dev/null
@@ -1,92 +0,0 @@
-INTRODUCTION
-
-lwIP is a small independent implementation of the TCP/IP protocol
-suite that has been developed by Adam Dunkels at the Computer and
-Networks Architectures (CNA) lab at the Swedish Institute of Computer
-Science (SICS).
-
-The focus of the lwIP TCP/IP implementation is to reduce the RAM usage
-while still having a full scale TCP. This making lwIP suitable for use
-in embedded systems with tenths of kilobytes of free RAM and room for
-around 40 kilobytes of code ROM.
-
-FEATURES
-
- * IP (Internet Protocol) including packet forwarding over multiple
-   network interfaces
- * ICMP (Internet Control Message Protocol) for network maintenance
-   and debugging
- * UDP (User Datagram Protocol) including experimental UDP-lite
-   extensions
- * TCP (Transmission Control Protocol) with congestion control, RTT
-   estimation and fast recovery/fast retransmit
- * Specialized API for enhanced performance
- * Optional Berkeley socket API
-
-LICENSE
-
-lwIP is freely available under a BSD license.
-
-DEVELOPMENT
-
-lwIP has grown into an excellent TCP/IP stack for embedded devices,
-and developers using the stack often submit bug fixes, improvements,
-and additions to the stack to further increase its usefulness.
-
-Development of lwIP is hosted on Savannah, a central point for
-software development, maintenance and distribution. Everyone can
-help improve lwIP by use of Savannah's interface, CVS and the
-mailing list. A core team of developers will commit changes to the
-CVS source tree.
-
-The lwIP TCP/IP stack is maintained in the 'lwip' CVS module and
-contributions (such as platform ports) are in the 'contrib' module.
-
-The CVS main trunk is the stable branch, which contains bug fixes and
-tested features. The latest stable branch can be checked out by doing:
-  cvs -d:pserver:anoncvs@subversions.gnu.org:/cvsroot/lwip login
-  cvs -z3 -d:pserver:anoncvs@subversions.gnu.org:/cvsroot/lwip co lwip
-
-The 'STABLE' tag in the stable branch will represent the most stable
-revision (which may be somewhat older to protect us from errors
-introduced by merges). This 'STABLE' tagged version can be checked out
-by doing:
-  cvs -d:pserver:anoncvs@subversions.gnu.org:/cvsroot/lwip login
-  cvs -z3 -d:pserver:anoncvs@subversions.gnu.org:/cvsroot/lwip co -r STABLE lwip
-
-The 'DEVEL' branch is the active development branch, which contains
-bleeding edge changes, and may be instable. It can be checkout by doing:
-  cvs -d:pserver:anoncvs@subversions.gnu.org:/cvsroot/lwip login
-  cvs -z3 -d:pserver:anoncvs@subversions.gnu.org:/cvsroot/lwip co -r DEVEL lwip
-
-The current contrib CVS tree can be checked out by doing:
-  cvs -d:pserver:anoncvs@subversions.gnu.org:/cvsroot/lwip login
-  cvs -z3 -d:pserver:anoncvs@subversions.gnu.org:/cvsroot/lwip co contrib
-
-Last night's CVS tar ball can be downloaded from:
-  http://savannah.gnu.org/cvs.backups/lwip.tar.gz
-
-The current CVS trees are web-browsable:
-  http://savannah.nongnu.org/cgi-bin/viewcvs/lwip/lwip/
-  http://savannah.nongnu.org/cgi-bin/viewcvs/lwip/contrib/
-
-Submit patches and bugs via the lwIP project page:
-  http://savannah.nongnu.org/projects/lwip/
-
-
-DOCUMENTATION
-
-The original out-dated homepage of lwIP and Adam Dunkels' papers on
-lwIP are at the official lwIP home page:
-  http://www.sics.se/~adam/lwip/
-
-Self documentation of the source code is regularly extracted from the
-current CVS sources and is available from this web page:
-  http://www.nongnu.org/lwip/
-
-Reading Adam's papers, the files in docs/, browsing the source code
-documentation and browsing the mailing list archives is a good way to
-become familiar with the design of lwIP.
-
-Adam Dunkels 
-Leon Woestenberg 		    
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/cc.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/cc.h
deleted file mode 100644
index cbb300a12..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/cc.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __CC_H__
-#define __CC_H__
-
-#include "cpu.h"
-
-typedef unsigned   char    u8_t;
-typedef signed     char    s8_t;
-typedef unsigned   short   u16_t;
-typedef signed     short   s16_t;
-typedef unsigned   long    u32_t;
-typedef signed     long    s32_t;
-typedef u32_t mem_ptr_t;
-typedef int sys_prot_t;
-
-
-#define PACK_STRUCT_BEGIN
-#define PACK_STRUCT_STRUCT __attribute__ ((__packed__))
-#define PACK_STRUCT_END
-#define PACK_STRUCT_FIELD(x) x
-
-#endif /* __CC_H__ */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/cpu.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/cpu.h
deleted file mode 100644
index 2af31a864..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/cpu.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __CPU_H__
-#define __CPU_H__
-
-#define BYTE_ORDER LITTLE_ENDIAN
-
-#endif /* __CPU_H__ */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/init.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/init.h
deleted file mode 100644
index 14b95158b..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/init.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __ARCH_INIT_H__
-#define __ARCH_INIT_H__
-
-#define TCPIP_INIT_DONE(arg)  tcpip_init_done(arg)
-
-void tcpip_init_done(void *);
-int wait_for_tcpip_init(void);
-
-#endif /* __ARCH_INIT_H__ */
-
-
-
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/lib.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/lib.h
deleted file mode 100644
index 9726dee12..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/lib.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LIB_H__
-#define __LIB_H__
-
-#include 
-
-
-#endif /* __LIB_H__ */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/perf.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/perf.h
deleted file mode 100644
index 68afdb56f..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/perf.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __PERF_H__
-#define __PERF_H__
-
-#define PERF_START    /* null definition */
-#define PERF_STOP(x)  /* null definition */
-
-#endif /* __PERF_H__ */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/sys_arch.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/sys_arch.h
deleted file mode 100644
index 406f1f641..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/arch/sys_arch.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __SYS_RTXC_H__
-#define __SYS_RTXC_H__
-
-#include "FreeRTOS.h"
-#include "task.h"
-#include "queue.h"
-#include "semphr.h"
-
-#define SYS_MBOX_NULL (xQueueHandle)0
-#define SYS_SEM_NULL  (xSemaphoreHandle)0
-
-typedef xSemaphoreHandle sys_sem_t;
-typedef xQueueHandle sys_mbox_t;
-typedef xTaskHandle sys_thread_t;
-
-#endif /* __SYS_RTXC_H__ */
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/sys_arch.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/sys_arch.c
deleted file mode 100644
index a48fa78f9..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/sys_arch.c
+++ /dev/null
@@ -1,385 +0,0 @@
-/*
- * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-
-/* lwIP includes. */
-#include "lwip/debug.h"
-#include "lwip/def.h"
-#include "lwip/sys.h"
-#include "lwip/mem.h"
-
-/* Message queue constants. */
-#define archMESG_QUEUE_LENGTH	( 6 )
-#define archPOST_BLOCK_TIME_MS	( ( unsigned portLONG ) 10000 )
-
-struct timeoutlist 
-{
-	struct sys_timeouts timeouts;
-	xTaskHandle pid;
-};
-
-/* This is the number of threads that can be started with sys_thread_new() */
-#define SYS_THREAD_MAX 4
-
-#define lwipTCP_STACK_SIZE			600
-#define lwipBASIC_SERVER_STACK_SIZE	250
-
-static struct timeoutlist timeoutlist[SYS_THREAD_MAX];
-static u16_t nextthread = 0;
-int intlevel = 0;
-
-
-/*-----------------------------------------------------------------------------------*/
-//  Creates an empty mailbox.
-sys_mbox_t
-sys_mbox_new(void)
-{
-	xQueueHandle mbox;
-
-	mbox = xQueueCreate( archMESG_QUEUE_LENGTH, sizeof( void * ) );
-
-	return mbox;
-}
-
-/*-----------------------------------------------------------------------------------*/
-/*
-  Deallocates a mailbox. If there are messages still present in the
-  mailbox when the mailbox is deallocated, it is an indication of a
-  programming error in lwIP and the developer should be notified.
-*/
-void
-sys_mbox_free(sys_mbox_t mbox)
-{
-	if( uxQueueMessagesWaiting( mbox ) )
-	{
-		/* Line for breakpoint.  Should never break here! */
-		__asm volatile ( "NOP" );
-	}
-
-	vQueueDelete( mbox ); 
-}
-
-/*-----------------------------------------------------------------------------------*/
-//   Posts the "msg" to the mailbox.
-void
-sys_mbox_post(sys_mbox_t mbox, void *data)
-{   
-	xQueueSend( mbox, &data, ( portTickType ) ( archPOST_BLOCK_TIME_MS / portTICK_RATE_MS ) );
-}
-
-
-/*-----------------------------------------------------------------------------------*/
-/*
-  Blocks the thread until a message arrives in the mailbox, but does
-  not block the thread longer than "timeout" milliseconds (similar to
-  the sys_arch_sem_wait() function). The "msg" argument is a result
-  parameter that is set by the function (i.e., by doing "*msg =
-  ptr"). The "msg" parameter maybe NULL to indicate that the message
-  should be dropped.
-
-  The return values are the same as for the sys_arch_sem_wait() function:
-  Number of milliseconds spent waiting or SYS_ARCH_TIMEOUT if there was a
-  timeout.
-
-  Note that a function with a similar name, sys_mbox_fetch(), is
-  implemented by lwIP. 
-*/
-u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout)
-{
-void *dummyptr;
-portTickType StartTime, EndTime, Elapsed;
-
-	StartTime = xTaskGetTickCount();
-
-	if( msg == NULL )
-	{
-		msg = &dummyptr;
-	}
-		
-	if(	timeout != 0 )
-	{
-		if(pdTRUE == xQueueReceive( mbox, &(*msg), timeout ) )
-		{
-			EndTime = xTaskGetTickCount();
-			Elapsed = EndTime - StartTime;
-			if( Elapsed == 0 )
-			{
-				Elapsed = 1;
-			}
-			return ( Elapsed );
-		}
-		else // timed out blocking for message
-		{
-			*msg = NULL;
-			return SYS_ARCH_TIMEOUT;
-		}
-	}
-	else // block forever for a message.
-	{
-		while( pdTRUE != xQueueReceive( mbox, &(*msg), 10000 ) ) // time is arbitrary
-		{
-			;
-		}
-		EndTime = xTaskGetTickCount();
-		Elapsed = EndTime - StartTime;
-		if( Elapsed == 0 )
-		{
-			Elapsed = 1;
-		}
-		return ( Elapsed ); // return time blocked TBD test	
-	}
-}
-
-/*-----------------------------------------------------------------------------------*/
-//  Creates and returns a new semaphore. The "count" argument specifies
-//  the initial state of the semaphore. TBD finish and test
-sys_sem_t
-sys_sem_new(u8_t count)
-{
-	xSemaphoreHandle  xSemaphore;
-
-	portENTER_CRITICAL();
-	vSemaphoreCreateBinary( xSemaphore );
-	if(count == 0)	// Means it can't be taken
-	{
-		xSemaphoreTake(xSemaphore,1);
-	}
-	portEXIT_CRITICAL();
-
-	if( xSemaphore == NULL )
-	{
-		return NULL;	// TBD need assert
-	}
-	else
-	{
-		return xSemaphore;
-	}
-}
-
-/*-----------------------------------------------------------------------------------*/
-/*
-  Blocks the thread while waiting for the semaphore to be
-  signaled. If the "timeout" argument is non-zero, the thread should
-  only be blocked for the specified time (measured in
-  milliseconds).
-
-  If the timeout argument is non-zero, the return value is the number of
-  milliseconds spent waiting for the semaphore to be signaled. If the
-  semaphore wasn't signaled within the specified time, the return value is
-  SYS_ARCH_TIMEOUT. If the thread didn't have to wait for the semaphore
-  (i.e., it was already signaled), the function may return zero.
-
-  Notice that lwIP implements a function with a similar name,
-  sys_sem_wait(), that uses the sys_arch_sem_wait() function.
-*/
-u32_t
-sys_arch_sem_wait(sys_sem_t sem, u32_t timeout)
-{
-portTickType StartTime, EndTime, Elapsed;
-
-	StartTime = xTaskGetTickCount();
-
-	if(	timeout != 0)
-	{
-		if( xSemaphoreTake( sem, timeout ) == pdTRUE )
-		{
-			EndTime = xTaskGetTickCount();
-			Elapsed = EndTime - StartTime;
-			if( Elapsed == 0 )
-			{
-				Elapsed = 1;
-			}
-			return (Elapsed); // return time blocked TBD test	
-		}
-		else
-		{
-			return SYS_ARCH_TIMEOUT;
-		}
-	}
-	else // must block without a timeout
-	{
-		while( xSemaphoreTake( sem, 10000 ) != pdTRUE )
-		{
-			;
-		}
-		EndTime = xTaskGetTickCount();
-		Elapsed = EndTime - StartTime;
-		if( Elapsed == 0 )
-		{
-			Elapsed = 1;
-		}
-
-		return ( Elapsed ); // return time blocked	
-		 
-	}
-}
-
-/*-----------------------------------------------------------------------------------*/
-// Signals a semaphore
-void
-sys_sem_signal(sys_sem_t sem)
-{
-	xSemaphoreGive( sem );
-}
-
-/*-----------------------------------------------------------------------------------*/
-// Deallocates a semaphore
-void
-sys_sem_free(sys_sem_t sem)
-{
-	vQueueDelete( sem ); 
-}
-
-/*-----------------------------------------------------------------------------------*/
-// Initialize sys arch
-void
-sys_init(void)
-{
-
-	int i;
-
-	// Initialize the the per-thread sys_timeouts structures
-	// make sure there are no valid pids in the list
-	for(i = 0; i < SYS_THREAD_MAX; i++)
-	{
-		timeoutlist[i].pid = 0;
-	}
-
-	// keep track of how many threads have been created
-	nextthread = 0;
-}
-
-/*-----------------------------------------------------------------------------------*/
-/*
-  Returns a pointer to the per-thread sys_timeouts structure. In lwIP,
-  each thread has a list of timeouts which is represented as a linked
-  list of sys_timeout structures. The sys_timeouts structure holds a
-  pointer to a linked list of timeouts. This function is called by
-  the lwIP timeout scheduler and must not return a NULL value. 
-
-  In a single threaded sys_arch implementation, this function will
-  simply return a pointer to a global sys_timeouts variable stored in
-  the sys_arch module.
-*/
-struct sys_timeouts *
-sys_arch_timeouts(void)
-{
-int i;
-xTaskHandle pid;
-struct timeoutlist *tl;  
-
-	pid = xTaskGetCurrentTaskHandle( ); 
-
-	for(i = 0; i < nextthread; i++) 
-	{
-		tl = &timeoutlist[i];
-		if(tl->pid == pid) 
-		{
-			return &(tl->timeouts);
-		}
-	}
-
-	// Error
-	return NULL;
-}
-
-/*-----------------------------------------------------------------------------------*/
-/*-----------------------------------------------------------------------------------*/
-// TBD 
-/*-----------------------------------------------------------------------------------*/
-/*
-  Starts a new thread with priority "prio" that will begin its execution in the
-  function "thread()". The "arg" argument will be passed as an argument to the
-  thread() function. The id of the new thread is returned. Both the id and
-  the priority are system dependent.
-*/
-sys_thread_t sys_thread_new(void (* thread)(void *arg), void *arg, int prio)
-{
-xTaskHandle CreatedTask;
-int result;
-static int iCall = 0;
-
-	if( iCall == 0 )
-	{
-		/* The first time this is called we are creating the lwIP handler. */
-		result = xTaskCreate( thread, ( signed portCHAR * ) "lwIP", lwipTCP_STACK_SIZE, arg, prio, &CreatedTask );
-		iCall++;
-	}
-	else
-	{
-		result = xTaskCreate( thread, ( signed portCHAR * ) "WEBSvr", lwipBASIC_SERVER_STACK_SIZE, arg, prio, &CreatedTask );
-	}
-
-	// For each task created, store the task handle (pid) in the timers array.
-	// This scheme doesn't allow for threads to be deleted
-	timeoutlist[nextthread++].pid = CreatedTask;
-
-	if(result == pdPASS)
-	{
-		return CreatedTask;
-	}
-	else
-	{
-		return NULL;
-	}
-}
-
-/*
-  This optional function does a "fast" critical region protection and returns
-  the previous protection level. This function is only called during very short
-  critical regions. An embedded system which supports ISR-based drivers might
-  want to implement this function by disabling interrupts. Task-based systems
-  might want to implement this by using a mutex or disabling tasking. This
-  function should support recursive calls from the same task or interrupt. In
-  other words, sys_arch_protect() could be called while already protected. In
-  that case the return value indicates that it is already protected.
-
-  sys_arch_protect() is only required if your port is supporting an operating
-  system.
-*/
-sys_prot_t sys_arch_protect(void)
-{
-	vPortEnterCritical();
-	return 1;
-}
-
-/*
-  This optional function does a "fast" set of critical region protection to the
-  value specified by pval. See the documentation for sys_arch_protect() for
-  more information. This function is only required if your port is supporting
-  an operating system.
-*/
-void sys_arch_unprotect(sys_prot_t pval)
-{ 
-	( void ) pval;
-	vPortExitCritical();
-}
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/doc/contrib.txt b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/doc/contrib.txt
deleted file mode 100644
index 7c99b9be2..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/doc/contrib.txt
+++ /dev/null
@@ -1,62 +0,0 @@
-1 Introduction
-
-This document describes some guidelines for people participating
-in lwIP development.
-
-2 How to contribute to lwIP
-
-Here is a short list of suggestions to anybody working with lwIP and 
-trying to contribute bug reports, fixes, enhancements, platform ports etc.
-First of all as you may already know lwIP is a volunteer project so feedback
-to fixes or questions might often come late. Hopefully the bug and patch tracking 
-features of Savannah help us not lose users' input.
-
-2.1 Source code style:
-
-1. do not use tabs.
-2. indentation is two spaces per level (i.e. per tab).
-3. end debug messages with a trailing newline (\n).
-4. one space between keyword and opening bracket.
-5. no space between function and opening bracket.
-6. one space and no newline before opening curly braces of a block.
-7. closing curly brace on a single line.
-8. spaces surrounding assignment and comparisons.
-9. use current source code style as further reference.
-
-2.2 Source code documentation style:
-
-1. JavaDoc compliant and Doxygen compatible.
-2. Function documentation above functions in .c files, not .h files.
-   (This forces you to synchronize documentation and implementation.)
-3. Use current documentation style as further reference.
- 
-2.3 Bug reports and patches:
-
-1. Make sure you are reporting bugs or send patches against the latest
-   sources. (From the latest release and/or the current CVS sources.)
-2. If you think you found a bug make sure it's not already filed in the
-   bugtracker at Savannah.
-3. If you have a fix put the patch on Savannah. If it is a patch that affects
-   both core and arch specific stuff please separate them so that the core can
-   be applied separately while leaving the other patch 'open'. The prefered way
-   is to NOT touch archs you can't test and let maintainers take care of them.
-   This is a good way to see if they are used at all - the same goes for unix
-   netifs except tapif.
-4. Do not file a bug and post a fix to it to the patch area. Either a bug report
-   or a patch will be enough.
-   If you correct an existing bug then attach the patch to the bug rather than creating a new entry in the patch area.
-5. Trivial patches (compiler warning, indentation and spelling fixes or anything obvious which takes a line or two)
-   can go to the lwip-users list. This is still the fastest way of interaction and the list is not so crowded
-   as to allow for loss of fixes. Putting bugs on Savannah and subsequently closing them is too much an overhead
-   for reporting a compiler warning fix.
-6. Patches should be specific to a single change or to related changes.Do not mix bugfixes with spelling and other
-   trivial fixes unless the bugfix is trivial too.Do not reorganize code and rename identifiers in the same patch you
-   change behaviour if not necessary.A patch is easier to read and understand if it's to the point and short than
-   if it's not to the point and long :) so the chances for it to be applied are greater. 
-
-2.4 Platform porters:
-
-1. If you have ported lwIP to a platform (an OS, a uC/processor or a combination of these) and
-   you think it could benefit others[1] you might want discuss this on the mailing list. You
-   can also ask for CVS access to submit and maintain your port in the contrib CVS module.
-   
\ No newline at end of file
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/doc/rawapi.txt b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/doc/rawapi.txt
deleted file mode 100644
index 6d1c93cab..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/doc/rawapi.txt
+++ /dev/null
@@ -1,292 +0,0 @@
-Raw TCP/IP interface for lwIP
-
-Authors: Adam Dunkels, Leon Woestenberg
-
-lwIP provides two Application Program's Interfaces (APIs) for programs
-to use for communication with the TCP/IP code:
-* low-level "core" / "callback" or "raw" API.
-* higher-level "sequential" API.
-
-The sequential API provides a way for ordinary, sequential, programs
-to use the lwIP stack. It is quite similar to the BSD socket API. The
-model of execution is based on the blocking open-read-write-close
-paradigm. Since the TCP/IP stack is event based by nature, the TCP/IP
-code and the application program must reside in different execution
-contexts (threads).
-
-** The remainder of this document discusses the "raw" API. **
-
-The raw TCP/IP interface allows the application program to integrate
-better with the TCP/IP code. Program execution is event based by
-having callback functions being called from within the TCP/IP
-code. The TCP/IP code and the application program both run in the same
-thread. The sequential API has a much higher overhead and is not very
-well suited for small systems since it forces a multithreaded paradigm
-on the application.
-
-The raw TCP/IP interface is not only faster in terms of code execution
-time but is also less memory intensive. The drawback is that program
-development is somewhat harder and application programs written for
-the raw TCP/IP interface are more difficult to understand. Still, this
-is the preferred way of writing applications that should be small in
-code size and memory usage.
-
-Both APIs can be used simultaneously by different application
-programs. In fact, the sequential API is implemented as an application
-program using the raw TCP/IP interface.
-
---- Callbacks
-
-Program execution is driven by callbacks. Each callback is an ordinary
-C function that is called from within the TCP/IP code. Every callback
-function is passed the current TCP or UDP connection state as an
-argument. Also, in order to be able to keep program specific state,
-the callback functions are called with a program specified argument
-that is independent of the TCP/IP state.
-
-The function for setting the application connection state is:
-
-- void tcp_arg(struct tcp_pcb *pcb, void *arg)
-
-  Specifies the program specific state that should be passed to all
-  other callback functions. The "pcb" argument is the current TCP
-  connection control block, and the "arg" argument is the argument
-  that will be passed to the callbacks.
-
-  
---- TCP connection setup
-
-The functions used for setting up connections is similar to that of
-the sequential API and of the BSD socket API. A new TCP connection
-identifier (i.e., a protocol control block - PCB) is created with the
-tcp_new() function. This PCB can then be either set to listen for new
-incoming connections or be explicitly connected to another host.
-
-- struct tcp_pcb *tcp_new(void)
-
-  Creates a new connection identifier (PCB). If memory is not
-  available for creating the new pcb, NULL is returned.
-
-- err_t tcp_bind(struct tcp_pcb *pcb, struct ip_addr *ipaddr,
-                 u16_t port)
-
-  Binds the pcb to a local IP address and port number. The IP address
-  can be specified as IP_ADDR_ANY in order to bind the connection to
-  all local IP addresses.
-
-  If another connection is bound to the same port, the function will
-  return ERR_USE, otherwise ERR_OK is returned.
-
-- struct tcp_pcb *tcp_listen(struct tcp_pcb *pcb)
-
-  Commands a pcb to start listening for incoming connections. When an
-  incoming connection is accepted, the function specified with the
-  tcp_accept() function will be called. The pcb will have to be bound
-  to a local port with the tcp_bind() function.
-
-  The tcp_listen() function returns a new connection identifier, and
-  the one passed as an argument to the function will be
-  deallocated. The reason for this behavior is that less memory is
-  needed for a connection that is listening, so tcp_listen() will
-  reclaim the memory needed for the original connection and allocate a
-  new smaller memory block for the listening connection.
-
-  tcp_listen() may return NULL if no memory was available for the
-  listening connection. If so, the memory associated with the pcb
-  passed as an argument to tcp_listen() will not be deallocated.
-
-- void tcp_accept(struct tcp_pcb *pcb,
-                  err_t (* accept)(void *arg, struct tcp_pcb *newpcb,
-                                   err_t err))
-
-  Specified the callback function that should be called when a new
-  connection arrives on a listening connection.
-      
-- err_t tcp_connect(struct tcp_pcb *pcb, struct ip_addr *ipaddr,
-                    u16_t port, err_t (* connected)(void *arg,
-                                                    struct tcp_pcb *tpcb,
-                                                    err_t err));
-
-  Sets up the pcb to connect to the remote host and sends the
-  initial SYN segment which opens the connection. 
-
-  The tcp_connect() function returns immediately; it does not wait for
-  the connection to be properly setup. Instead, it will call the
-  function specified as the fourth argument (the "connected" argument)
-  when the connection is established. If the connection could not be
-  properly established, either because the other host refused the
-  connection or because the other host didn't answer, the "connected"
-  function will be called with an the "err" argument set accordingly.
-
-  The tcp_connect() function can return ERR_MEM if no memory is
-  available for enqueueing the SYN segment. If the SYN indeed was
-  enqueued successfully, the tcp_connect() function returns ERR_OK.
-
-  
---- Sending TCP data
-
-TCP data is sent by enqueueing the data with a call to
-tcp_write(). When the data is successfully transmitted to the remote
-host, the application will be notified with a call to a specified
-callback function.
-
-- err_t tcp_write(struct tcp_pcb *pcb, void *dataptr, u16_t len,
-                  u8_t copy)
-
-  Enqueues the data pointed to by the argument dataptr. The length of
-  the data is passed as the len parameter. The copy argument is either
-  0 or 1 and indicates whether the new memory should be allocated for
-  the data to be copied into. If the argument is 0, no new memory
-  should be allocated and the data should only be referenced by
-  pointer.
-
-  The tcp_write() function will fail and return ERR_MEM if the length
-  of the data exceeds the current send buffer size or if the length of
-  the queue of outgoing segment is larger than the upper limit defined
-  in lwipopts.h. The number of bytes available in the output queue can
-  be retrieved with the tcp_sndbuf() function.
-
-  The proper way to use this function is to call the function with at
-  most tcp_sndbuf() bytes of data. If the function returns ERR_MEM,
-  the application should wait until some of the currently enqueued
-  data has been successfully received by the other host and try again.
-
-- void tcp_sent(struct tcp_pcb *pcb,
-                err_t (* sent)(void *arg, struct tcp_pcb *tpcb,
-		               u16_t len))
-
-  Specifies the callback function that should be called when data has
-  successfully been received (i.e., acknowledged) by the remote
-  host. The len argument passed to the callback function gives the
-  amount bytes that was acknowledged by the last acknowledgment.
-
-  
---- Receiving TCP data
-
-TCP data reception is callback based - an application specified
-callback function is called when new data arrives. When the
-application has taken the data, it has to call the tcp_recved()
-function to indicate that TCP can advertise increase the receive
-window.
-
-- void tcp_recv(struct tcp_pcb *pcb,
-                err_t (* recv)(void *arg, struct tcp_pcb *tpcb,
-                               struct pbuf *p, err_t err))
-
-  Sets the callback function that will be called when new data
-  arrives. The callback function will be passed a NULL pbuf to
-  indicate that the remote host has closed the connection.
-
-- void tcp_recved(struct tcp_pcb *pcb, u16_t len)
-
-  Must be called when the application has received the data. The len
-  argument indicates the length of the received data.
-    
-
---- Application polling
-
-When a connection is idle (i.e., no data is either transmitted or
-received), lwIP will repeatedly poll the application by calling a
-specified callback function. This can be used either as a watchdog
-timer for killing connections that have stayed idle for too long, or
-as a method of waiting for memory to become available. For instance,
-if a call to tcp_write() has failed because memory wasn't available,
-the application may use the polling functionality to call tcp_write()
-again when the connection has been idle for a while.
-
-- void tcp_poll(struct tcp_pcb *pcb, u8_t interval,
-                err_t (* poll)(void *arg, struct tcp_pcb *tpcb))
-
-  Specifies the polling interval and the callback function that should
-  be called to poll the application. The interval is specified in
-  number of TCP coarse grained timer shots, which typically occurs
-  twice a second. An interval of 10 means that the application would
-  be polled every 5 seconds.
-
-
---- Closing and aborting connections
-
-- err_t tcp_close(struct tcp_pcb *pcb)
-
-  Closes the connection. The function may return ERR_MEM if no memory
-  was available for closing the connection. If so, the application
-  should wait and try again either by using the acknowledgment
-  callback or the polling functionality. If the close succeeds, the
-  function returns ERR_OK.
-
-  The pcb is deallocated by the TCP code after a call to tcp_close(). 
-
-- void tcp_abort(struct tcp_pcb *pcb)
-
-  Aborts the connection by sending a RST (reset) segment to the remote
-  host. The pcb is deallocated. This function never fails.
-
-If a connection is aborted because of an error, the application is
-alerted of this event by the err callback. Errors that might abort a
-connection are when there is a shortage of memory. The callback
-function to be called is set using the tcp_err() function.
-
-- void tcp_err(struct tcp_pcb *pcb, void (* err)(void *arg,
-	       err_t err))
-
-  The error callback function does not get the pcb passed to it as a
-  parameter since the pcb may already have been deallocated.
-
-
---- Lower layer TCP interface
-
-TCP provides a simple interface to the lower layers of the
-system. During system initialization, the function tcp_init() has
-to be called before any other TCP function is called. When the system
-is running, the two timer functions tcp_fasttmr() and tcp_slowtmr()
-must be called with regular intervals. The tcp_fasttmr() should be
-called every TCP_FAST_INTERVAL milliseconds (defined in tcp.h) and
-tcp_slowtmr() should be called every TCP_SLOW_INTERVAL milliseconds. 
-
-
---- UDP interface
-
-The UDP interface is similar to that of TCP, but due to the lower
-level of complexity of UDP, the interface is significantly simpler.
-
-- struct udp_pcb *udp_new(void)
-
-  Creates a new UDP pcb which can be used for UDP communication. The
-  pcb is not active until it has either been bound to a local address
-  or connected to a remote address.
-
-- void udp_remove(struct udp_pcb *pcb)
-
-  Removes and deallocates the pcb.  
-  
-- err_t udp_bind(struct udp_pcb *pcb, struct ip_addr *ipaddr,
-                 u16_t port)
-
-  Binds the pcb to a local address. The IP-address argument "ipaddr"
-  can be IP_ADDR_ANY to indicate that it should listen to any local IP
-  address. The function currently always return ERR_OK.
-
-- err_t udp_connect(struct udp_pcb *pcb, struct ip_addr *ipaddr,
-                    u16_t port)
-
-  Sets the remote end of the pcb. This function does not generate any
-  network traffic, but only set the remote address of the pcb.
-
-- err_t udp_disconnect(struct udp_pcb *pcb)
-
-  Remove the remote end of the pcb. This function does not generate
-  any network traffic, but only removes the remote address of the pcb.
-
-- err_t udp_send(struct udp_pcb *pcb, struct pbuf *p)
-
-  Sends the pbuf p. The pbuf is not deallocated.
-
-- void udp_recv(struct udp_pcb *pcb,
-                void (* recv)(void *arg, struct udp_pcb *upcb,
-                                         struct pbuf *p,
-                                         struct ip_addr *addr,
-                                         u16_t port),
-                              void *recv_arg)
-
-  Specifies a callback function that should be called when a UDP
-  datagram is received.
\ No newline at end of file
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/doc/savannah.txt b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/doc/savannah.txt
deleted file mode 100644
index 56cc1f190..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/doc/savannah.txt
+++ /dev/null
@@ -1,135 +0,0 @@
-Daily Use Guide for using Savannah for lwIP
-
-Table of Contents:
-
-1 - Obtaining lwIP from the CVS repository
-2 - Committers/developers CVS access using SSH (to be written)
-3 - Merging from DEVEL branch to main trunk (stable branch)
-4 - How to release lwIP
-
-
-
-1 Obtaining lwIP from the CVS repository
-----------------------------------------
-
-To perform an anonymous CVS checkout of the main trunk (this is where
-bug fixes and incremental enhancements occur), do this:
-
-export CVS_RSH=ssh
-cvs -d:ext:anoncvs@subversions.gnu.org:/cvsroot/lwip checkout lwip
-
-(If SSH asks about authenticity of the host, you can check the key
- fingerprint against http://savannah.nongnu.org/cvs/?group=lwip)
-
-Or, obtain a stable branch (updated with bug fixes only) as follows:
-cvs -d:ext:anoncvs@subversions.gnu.org:/cvsroot/lwip checkout -r STABLE-0_7 -d lwip-0.7 lwip
-
-Or, obtain a specific (fixed) release as follows:
-cvs -d:ext:anoncvs@subversions.gnu.org:/cvsroot/lwip checkout -r STABLE-0_7_0 -d lwip-0.7.0 lwip
-
-Or, obtain a development branch (considered unstable!) as follows:
-cvs -d:ext:anoncvs@subversions.gnu.org:/cvsroot/lwip checkout -r DEVEL -d lwip-DEVEL lwip
-
-3 Committers/developers CVS access using SSH
---------------------------------------------
-
-The Savannah server uses SSH (Secure Shell) protocol 2 authentication and encryption.
-As such, CVS commits to the server occur through a SSH tunnel for project members.
-To create a SSH2 key pair in UNIX-like environments, do this:
-
-ssh-keygen -t dsa
-
-Under Windows, a recommended SSH client is "PuTTY", freely available with good
-documentation and a graphic user interface. Use its key generator.
-
-Now paste the id_dsa.pub contents into your Savannah account public key list. Wait
-a while so that Savannah can update its configuration (This can take minutes).
-
-Try to login using SSH:
-
-ssh -v your_login@subversions.gnu.org
-
-If it tells you:
-
-Authenticating with public key "your_key_name"...
-Server refused to allocate pty
-
-then you could login; Savannah refuses to give you a shell - which is OK, as we
-are allowed to use SSH for CVS only. Now, you should be able to do this:
-
-export CVS_RSH=ssh
-cvs -d:ext:your_login@subversions.gnu.org:/cvsroot/lwip checkout lwip
-
-after which you can edit your local files with bug fixes or new features and
-commit them. Make sure you know what you are doing when using CVS to make
-changes on the repository. If in doubt, ask on the lwip-members mailing list.
-
-3 Merging from DEVEL branch to main trunk (stable)
---------------------------------------------------
-
-Merging is a delicate process in CVS and requires the
-following disciplined steps in order to prevent conflicts
-in the future. Conflicts can be hard to solve!
-
-Merging from branch A to branch B requires that the A branch
-has a tag indicating the previous merger. This tag is called
-'merged_from_A_to_B'. After merging, the tag is moved in the
-A branch to remember this merger for future merge actions.
-
-IMPORTANT: AFTER COMMITTING A SUCCESFUL MERGE IN THE
-REPOSITORY, THE TAG MUST BE SET ON THE SOURCE BRANCH OF THE
-MERGE ACTION (REPLACING EXISTING TAGS WITH THE SAME NAME).
-
-Merge all changes in DEVEL since our last merge to main:
-
-In the working copy of the main trunk:
-cvs update -P -jmerged_from_DEVEL_to_main -jDEVEL 
-
-(This will apply the changes between 'merged_from_DEVEL_to_main'
-and 'DEVEL' to your work set of files)
-
-We can now commit the merge result.
-cvs commit -R -m "Merged from DEVEL to main." 
-
-If this worked out OK, we now move the tag in the DEVEL branch
-to this merge point, so we can use this point for future merges:
-
-cvs rtag -F -r DEVEL merged_from_DEVEL_to_main lwip 
-
-4 How to release lwIP
----------------------
-
-First, checkout a clean copy of the branch to be released. Tag this set with
-tag name "STABLE-0_6_3". (I use release number 0.6.3 throughout this example).
-
-Login CVS using pserver authentication, then export a clean copy of the
-tagged tree. Export is similar to a checkout, except that the CVS metadata
-is not created locally. 
-
-export CVS_RSH=ssh
-cvs -d:ext:anoncvs@subversions.gnu.org:/cvsroot/lwip export -r STABLE-0_6_3 -d lwip-0.6.3 lwip
-
-Archive this directory using tar, gzip'd, bzip2'd and zip'd.
-
-tar czvf lwip-0.6.3.tar.gz lwip-0.6.3
-tar cjvf lwip-0.6.3.tar.bz2 lwip-0.6.3
-zip -r lwip-0.6.3.zip lwip-0.6.3
-
-Now, sign the archives with a detached GPG binary signature as follows:
-
-gpg -b lwip-0.6.3.tar.gz
-gpg -b lwip-0.6.3.tar.bz2
-gpg -b lwip-0.6.3.zip
-
-Upload these files using anonymous FTP:
-ncftp ftp://savannah.gnu.org/incoming/savannah/lwip
-
-ncftp>mput *0.6.3.*
-
-Additionally, you may post a news item on Savannah, like this:
-
-A new 0.6.3 release is now available here:
-http://savannah.nongnu.org/files/?group=lwip&highlight=0.6.3
-
-You will have to submit this via the user News interface, then approve
-this via the Administrator News interface.
\ No newline at end of file
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/doc/sys_arch.txt b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/doc/sys_arch.txt
deleted file mode 100644
index 95d0add73..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/doc/sys_arch.txt
+++ /dev/null
@@ -1,194 +0,0 @@
-sys_arch interface for lwIP 0.6++
-
-Author: Adam Dunkels
-
-The operating system emulation layer provides a common interface
-between the lwIP code and the underlying operating system kernel. The
-general idea is that porting lwIP to new architectures requires only
-small changes to a few header files and a new sys_arch
-implementation. It is also possible to do a sys_arch implementation
-that does not rely on any underlying operating system.
-
-The sys_arch provides semaphores and mailboxes to lwIP. For the full
-lwIP functionality, multiple threads support can be implemented in the
-sys_arch, but this is not required for the basic lwIP
-functionality. Previous versions of lwIP required the sys_arch to
-implement timer scheduling as well but as of lwIP 0.5 this is
-implemented in a higher layer.
-
-In addition to the source file providing the functionality of sys_arch,
-the OS emulation layer must provide several header files defining
-macros used throughout lwip.  The files required and the macros they
-must define are listed below the sys_arch description.
-
-Semaphores can be either counting or binary - lwIP works with both
-kinds. Mailboxes are used for message passing and can be implemented
-either as a queue which allows multiple messages to be posted to a
-mailbox, or as a rendez-vous point where only one message can be
-posted at a time. lwIP works with both kinds, but the former type will
-be more efficient. A message in a mailbox is just a pointer, nothing
-more. 
-
-Semaphores are represented by the type "sys_sem_t" which is typedef'd
-in the sys_arch.h file. Mailboxes are equivalently represented by the
-type "sys_mbox_t". lwIP does not place any restrictions on how
-sys_sem_t or sys_mbox_t are represented internally.
-
-The following functions must be implemented by the sys_arch:
-
-- void sys_init(void)
-
-  Is called to initialize the sys_arch layer.
-
-- sys_sem_t sys_sem_new(u8_t count)
-
-  Creates and returns a new semaphore. The "count" argument specifies
-  the initial state of the semaphore.
-
-- void sys_sem_free(sys_sem_t sem)
-
-  Deallocates a semaphore.
-
-- void sys_sem_signal(sys_sem_t sem)
-
-  Signals a semaphore.
-
-- u32_t sys_arch_sem_wait(sys_sem_t sem, u32_t timeout)
-
-  Blocks the thread while waiting for the semaphore to be
-  signaled. If the "timeout" argument is non-zero, the thread should
-  only be blocked for the specified time (measured in
-  milliseconds).
-
-  If the timeout argument is non-zero, the return value is the number of
-  milliseconds spent waiting for the semaphore to be signaled. If the
-  semaphore wasn't signaled within the specified time, the return value is
-  SYS_ARCH_TIMEOUT. If the thread didn't have to wait for the semaphore
-  (i.e., it was already signaled), the function may return zero.
-
-  Notice that lwIP implements a function with a similar name,
-  sys_sem_wait(), that uses the sys_arch_sem_wait() function.
-
-- sys_mbox_t sys_mbox_new(void)
-
-  Creates an empty mailbox.
-
-- void sys_mbox_free(sys_mbox_t mbox)
-
-  Deallocates a mailbox. If there are messages still present in the
-  mailbox when the mailbox is deallocated, it is an indication of a
-  programming error in lwIP and the developer should be notified.
-
-- void sys_mbox_post(sys_mbox_t mbox, void *msg)
-
-  Posts the "msg" to the mailbox.
-
-- u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout)
-
-  Blocks the thread until a message arrives in the mailbox, but does
-  not block the thread longer than "timeout" milliseconds (similar to
-  the sys_arch_sem_wait() function). The "msg" argument is a result
-  parameter that is set by the function (i.e., by doing "*msg =
-  ptr"). The "msg" parameter maybe NULL to indicate that the message
-  should be dropped.
-
-  The return values are the same as for the sys_arch_sem_wait() function:
-  Number of milliseconds spent waiting or SYS_ARCH_TIMEOUT if there was a
-  timeout.
-
-  Note that a function with a similar name, sys_mbox_fetch(), is
-  implemented by lwIP. 
-  
-- struct sys_timeouts *sys_arch_timeouts(void)
-
-  Returns a pointer to the per-thread sys_timeouts structure. In lwIP,
-  each thread has a list of timeouts which is repressented as a linked
-  list of sys_timeout structures. The sys_timeouts structure holds a
-  pointer to a linked list of timeouts. This function is called by
-  the lwIP timeout scheduler and must not return a NULL value. 
-
-  In a single threadd sys_arch implementation, this function will
-  simply return a pointer to a global sys_timeouts variable stored in
-  the sys_arch module.
-  
-If threads are supported by the underlying operating system and if
-such functionality is needed in lwIP, the following function will have
-to be implemented as well:
-
-- sys_thread_t sys_thread_new(void (* thread)(void *arg), void *arg, int prio)
-
-  Starts a new thread with priority "prio" that will begin its execution in the
-  function "thread()". The "arg" argument will be passed as an argument to the
-  thread() function. The id of the new thread is returned. Both the id and
-  the priority are system dependent.
-
-- sys_prot_t sys_arch_protect(void)
-
-  This optional function does a "fast" critical region protection and returns
-  the previous protection level. This function is only called during very short
-  critical regions. An embedded system which supports ISR-based drivers might
-  want to implement this function by disabling interrupts. Task-based systems
-  might want to implement this by using a mutex or disabling tasking. This
-  function should support recursive calls from the same task or interrupt. In
-  other words, sys_arch_protect() could be called while already protected. In
-  that case the return value indicates that it is already protected.
-
-  sys_arch_protect() is only required if your port is supporting an operating
-  system.
-
-- void sys_arch_unprotect(sys_prot_t pval)
-
-  This optional function does a "fast" set of critical region protection to the
-  value specified by pval. See the documentation for sys_arch_protect() for
-  more information. This function is only required if your port is supporting
-  an operating system.
-
--------------------------------------------------------------------------------
-Additional files required for the "OS support" emulation layer:
--------------------------------------------------------------------------------
-
-cc.h       - Architecture environment, some compiler specific, some
-             environment specific (probably should move env stuff 
-             to sys_arch.h.)
-
-  Typedefs for the types used by lwip -
-    u8_t, s8_t, u16_t, s16_t, u32_t, s32_t, mem_ptr_t
-
-  Compiler hints for packing lwip's structures -
-    PACK_STRUCT_FIELD(x)
-    PACK_STRUCT_STRUCT
-    PACK_STRUCT_BEGIN
-    PACK_STRUCT_END
-
-  Platform specific diagnostic output -
-    LWIP_PLATFORM_DIAG(x)    - non-fatal, print a message.
-    LWIP_PLATFORM_ASSERT(x)  - fatal, print message and abandon execution.
-
-  "lightweight" synchronization mechanisms -
-    SYS_ARCH_DECL_PROTECT(x) - declare a protection state variable.
-    SYS_ARCH_PROTECT(x)      - enter protection mode.
-    SYS_ARCH_UNPROTECT(x)    - leave protection mode.
-
-  If the compiler does not provide memset() this file must include a
-  definition of it, or include a file which defines it.
-
-  This file must either include a system-local  which defines
-  the standard *nix error codes, or it should #define LWIP_PROVIDE_ERRNO
-  to make lwip/arch.h define the codes which are used throughout.
-
-
-perf.h     - Architecture specific performance measurement.
-  Measurement calls made throughout lwip, these can be defined to nothing.
-    PERF_START               - start measuring something.
-    PERF_STOP(x)             - stop measuring something, and record the result.
-
-sys_arch.h - Tied to sys_arch.c
-
-  Arch dependent types for the following objects:
-    sys_sem_t, sys_mbox_t, sys_thread_t,
-  And, optionally:
-    sys_prot_t
-
-  Defines to set vars of sys_mbox_t and sys_sem_t to NULL.
-    SYS_MBOX_NULL NULL
-    SYS_SEM_NULL NULL
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/FILES b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/FILES
deleted file mode 100644
index 2b6573185..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/FILES
+++ /dev/null
@@ -1,13 +0,0 @@
-api/      - The code for the high-level wrapper API. Not needed if
-            you use the lowel-level call-back/raw API.
-
-core/     - The core of the TPC/IP stack; protocol implementations,
-            memory and buffer management, and the low-level raw API.
-	    
-include/  - lwIP include files.
-
-netif/    - Generic network interface device drivers are kept here,
-            as well as the ARP module.
-
-For more information on the various subdirectories, check the FILES
-file in each directory.
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/api/api_lib.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/api/api_lib.c
deleted file mode 100644
index 48d0a384b..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/api/api_lib.c
+++ /dev/null
@@ -1,729 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-
-/* This is the part of the API that is linked with
-   the application */
-
-#include "lwip/opt.h"
-#include "lwip/api.h"
-#include "lwip/api_msg.h"
-#include "lwip/memp.h"
-
-
-struct
-netbuf *netbuf_new(void)
-{
-  struct netbuf *buf;
-
-  buf = memp_malloc(MEMP_NETBUF);
-  if (buf != NULL) {
-    buf->p = NULL;
-    buf->ptr = NULL;
-    return buf;
-  } else {
-    return NULL;
-  }
-}
-
-void
-netbuf_delete(struct netbuf *buf)
-{
-  if (buf != NULL) {
-    if (buf->p != NULL) {
-      pbuf_free(buf->p);
-      buf->p = buf->ptr = NULL;
-    }
-    memp_free(MEMP_NETBUF, buf);
-  }
-}
-
-void *
-netbuf_alloc(struct netbuf *buf, u16_t size)
-{
-  /* Deallocate any previously allocated memory. */
-  if (buf->p != NULL) {
-    pbuf_free(buf->p);
-  }
-  buf->p = pbuf_alloc(PBUF_TRANSPORT, size, PBUF_RAM);
-  if (buf->p == NULL) {
-     return NULL;
-  }
-  buf->ptr = buf->p;
-  return buf->p->payload;
-}
-
-void
-netbuf_free(struct netbuf *buf)
-{
-  if (buf->p != NULL) {
-    pbuf_free(buf->p);
-  }
-  buf->p = buf->ptr = NULL;
-}
-
-void
-netbuf_ref(struct netbuf *buf, void *dataptr, u16_t size)
-{
-  if (buf->p != NULL) {
-    pbuf_free(buf->p);
-  }
-  buf->p = pbuf_alloc(PBUF_TRANSPORT, 0, PBUF_REF);
-  buf->p->payload = dataptr;
-  buf->p->len = buf->p->tot_len = size;
-  buf->ptr = buf->p;
-}
-
-void
-netbuf_chain(struct netbuf *head, struct netbuf *tail)
-{
-  pbuf_chain(head->p, tail->p);
-  head->ptr = head->p;
-  memp_free(MEMP_NETBUF, tail);
-}
-
-u16_t
-netbuf_len(struct netbuf *buf)
-{
-  return buf->p->tot_len;
-}
-
-err_t
-netbuf_data(struct netbuf *buf, void **dataptr, u16_t *len)
-{
-  if (buf->ptr == NULL) {
-    return ERR_BUF;
-  }
-  *dataptr = buf->ptr->payload;
-  *len = buf->ptr->len;
-  return ERR_OK;
-}
-
-s8_t
-netbuf_next(struct netbuf *buf)
-{
-  if (buf->ptr->next == NULL) {
-    return -1;
-  }
-  buf->ptr = buf->ptr->next;
-  if (buf->ptr->next == NULL) {
-    return 1;
-  }
-  return 0;
-}
-
-void
-netbuf_first(struct netbuf *buf)
-{
-  buf->ptr = buf->p;
-}
-
-void
-netbuf_copy_partial(struct netbuf *buf, void *dataptr, u16_t len, u16_t offset)
-{
-  struct pbuf *p;
-  u16_t i, left;
-
-  left = 0;
-
-  if(buf == NULL || dataptr == NULL) {
-    return;
-  }
-  
-  /* This implementation is bad. It should use bcopy
-     instead. */
-  for(p = buf->p; left < len && p != NULL; p = p->next) {
-    if (offset != 0 && offset >= p->len) {
-      offset -= p->len;
-    } else {    
-      for(i = offset; i < p->len; ++i) {
-  ((char *)dataptr)[left] = ((char *)p->payload)[i];
-  if (++left >= len) {
-    return;
-  }
-      }
-      offset = 0;
-    }
-  }
-}
-
-void
-netbuf_copy(struct netbuf *buf, void *dataptr, u16_t len)
-{
-  netbuf_copy_partial(buf, dataptr, len, 0);
-}
-
-struct ip_addr *
-netbuf_fromaddr(struct netbuf *buf)
-{
-  return buf->fromaddr;
-}
-
-u16_t
-netbuf_fromport(struct netbuf *buf)
-{
-  return buf->fromport;
-}
-
-struct
-netconn *netconn_new_with_proto_and_callback(enum netconn_type t, u16_t proto,
-                                   void (*callback)(struct netconn *, enum netconn_evt, u16_t len))
-{
-  struct netconn *conn;
-  struct api_msg *msg;
-
-  conn = memp_malloc(MEMP_NETCONN);
-  if (conn == NULL) {
-    return NULL;
-  }
-  
-  conn->err = ERR_OK;
-  conn->type = t;
-  conn->pcb.tcp = NULL;
-
-  if ((conn->mbox = sys_mbox_new()) == SYS_MBOX_NULL) {
-    memp_free(MEMP_NETCONN, conn);
-    return NULL;
-  }
-  conn->recvmbox = SYS_MBOX_NULL;
-  conn->acceptmbox = SYS_MBOX_NULL;
-  conn->sem = SYS_SEM_NULL;
-  conn->state = NETCONN_NONE;
-  conn->socket = 0;
-  conn->callback = callback;
-  conn->recv_avail = 0;
-
-  if((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
-    memp_free(MEMP_NETCONN, conn);
-    return NULL;
-  }
-  
-  msg->type = API_MSG_NEWCONN;
-  msg->msg.msg.bc.port = proto; /* misusing the port field */
-  msg->msg.conn = conn;
-  api_msg_post(msg);  
-  sys_mbox_fetch(conn->mbox, NULL);
-  memp_free(MEMP_API_MSG, msg);
-
-  if ( conn->err != ERR_OK ) {
-    memp_free(MEMP_NETCONN, conn);
-    return NULL;
-  }
-
-  return conn;
-}
-
-
-struct
-netconn *netconn_new(enum netconn_type t)
-{
-  return netconn_new_with_proto_and_callback(t,0,NULL);
-}
-
-struct
-netconn *netconn_new_with_callback(enum netconn_type t,
-                                   void (*callback)(struct netconn *, enum netconn_evt, u16_t len))
-{
-  return netconn_new_with_proto_and_callback(t,0,callback);
-}
-
-
-err_t
-netconn_delete(struct netconn *conn)
-{
-  struct api_msg *msg;
-  void *mem;
-  
-  if (conn == NULL) {
-    return ERR_OK;
-  }
-  
-  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
-    return ERR_MEM;
-  }
-  
-  msg->type = API_MSG_DELCONN;
-  msg->msg.conn = conn;
-  api_msg_post(msg);  
-  sys_mbox_fetch(conn->mbox, NULL);
-  memp_free(MEMP_API_MSG, msg);
-
-  /* Drain the recvmbox. */
-  if (conn->recvmbox != SYS_MBOX_NULL) {
-    while (sys_arch_mbox_fetch(conn->recvmbox, &mem, 1) != SYS_ARCH_TIMEOUT) {
-      if (conn->type == NETCONN_TCP) {
-        if(mem != NULL)
-          pbuf_free((struct pbuf *)mem);
-      } else {
-        netbuf_delete((struct netbuf *)mem);
-      }
-    }
-    sys_mbox_free(conn->recvmbox);
-    conn->recvmbox = SYS_MBOX_NULL;
-  }
- 
-
-  /* Drain the acceptmbox. */
-  if (conn->acceptmbox != SYS_MBOX_NULL) {
-    while (sys_arch_mbox_fetch(conn->acceptmbox, &mem, 1) != SYS_ARCH_TIMEOUT) {
-      netconn_delete((struct netconn *)mem);
-    }
-    
-    sys_mbox_free(conn->acceptmbox);
-    conn->acceptmbox = SYS_MBOX_NULL;
-  }
-
-  sys_mbox_free(conn->mbox);
-  conn->mbox = SYS_MBOX_NULL;
-  if (conn->sem != SYS_SEM_NULL) {
-    sys_sem_free(conn->sem);
-  }
-  /*  conn->sem = SYS_SEM_NULL;*/
-  memp_free(MEMP_NETCONN, conn);
-  return ERR_OK;
-}
-
-enum netconn_type
-netconn_type(struct netconn *conn)
-{
-  return conn->type;
-}
-
-err_t
-netconn_peer(struct netconn *conn, struct ip_addr *addr,
-       u16_t *port)
-{
-  switch (conn->type) {
-  case NETCONN_RAW:
-    /* return an error as connecting is only a helper for upper layers */
-    return ERR_CONN;
-  case NETCONN_UDPLITE:
-  case NETCONN_UDPNOCHKSUM:
-  case NETCONN_UDP:
-    if (conn->pcb.udp == NULL ||
-  ((conn->pcb.udp->flags & UDP_FLAGS_CONNECTED) == 0))
-     return ERR_CONN;
-    *addr = (conn->pcb.udp->remote_ip);
-    *port = conn->pcb.udp->remote_port;
-    break;
-  case NETCONN_TCP:
-    if (conn->pcb.tcp == NULL)
-      return ERR_CONN;
-    *addr = (conn->pcb.tcp->remote_ip);
-    *port = conn->pcb.tcp->remote_port;
-    break;
-  }
-  return (conn->err = ERR_OK);
-}
-
-err_t
-netconn_addr(struct netconn *conn, struct ip_addr **addr,
-       u16_t *port)
-{
-  switch (conn->type) {
-  case NETCONN_RAW:
-    *addr = &(conn->pcb.raw->local_ip);
-    *port = conn->pcb.raw->protocol;
-    break;
-  case NETCONN_UDPLITE:
-  case NETCONN_UDPNOCHKSUM:
-  case NETCONN_UDP:
-    *addr = &(conn->pcb.udp->local_ip);
-    *port = conn->pcb.udp->local_port;
-    break;
-  case NETCONN_TCP:
-    *addr = &(conn->pcb.tcp->local_ip);
-    *port = conn->pcb.tcp->local_port;
-    break;
-  }
-  return (conn->err = ERR_OK);
-}
-
-err_t
-netconn_bind(struct netconn *conn, struct ip_addr *addr,
-      u16_t port)
-{
-  struct api_msg *msg;
-
-  if (conn == NULL) {
-    return ERR_VAL;
-  }
-
-  if (conn->type != NETCONN_TCP &&
-     conn->recvmbox == SYS_MBOX_NULL) {
-    if ((conn->recvmbox = sys_mbox_new()) == SYS_MBOX_NULL) {
-      return ERR_MEM;
-    }
-  }
-  
-  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
-    return (conn->err = ERR_MEM);
-  }
-  msg->type = API_MSG_BIND;
-  msg->msg.conn = conn;
-  msg->msg.msg.bc.ipaddr = addr;
-  msg->msg.msg.bc.port = port;
-  api_msg_post(msg);
-  sys_mbox_fetch(conn->mbox, NULL);
-  memp_free(MEMP_API_MSG, msg);
-  return conn->err;
-}
-
-
-err_t
-netconn_connect(struct netconn *conn, struct ip_addr *addr,
-       u16_t port)
-{
-  struct api_msg *msg;
-  
-  if (conn == NULL) {
-    return ERR_VAL;
-  }
-
-
-  if (conn->recvmbox == SYS_MBOX_NULL) {
-    if ((conn->recvmbox = sys_mbox_new()) == SYS_MBOX_NULL) {
-      return ERR_MEM;
-    }
-  }
-  
-  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
-    return ERR_MEM;
-  }
-  msg->type = API_MSG_CONNECT;
-  msg->msg.conn = conn;  
-  msg->msg.msg.bc.ipaddr = addr;
-  msg->msg.msg.bc.port = port;
-  api_msg_post(msg);
-  sys_mbox_fetch(conn->mbox, NULL);
-  memp_free(MEMP_API_MSG, msg);
-  return conn->err;
-}
-
-err_t
-netconn_disconnect(struct netconn *conn)
-{
-  struct api_msg *msg;
-  
-  if (conn == NULL) {
-    return ERR_VAL;
-  }
-
-  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
-    return ERR_MEM;
-  }
-  msg->type = API_MSG_DISCONNECT;
-  msg->msg.conn = conn;  
-  api_msg_post(msg);
-  sys_mbox_fetch(conn->mbox, NULL);
-  memp_free(MEMP_API_MSG, msg);
-  return conn->err;
-
-}
-
-err_t
-netconn_listen(struct netconn *conn)
-{
-  struct api_msg *msg;
-
-  if (conn == NULL) {
-    return ERR_VAL;
-  }
-
-  if (conn->acceptmbox == SYS_MBOX_NULL) {
-    conn->acceptmbox = sys_mbox_new();
-    if (conn->acceptmbox == SYS_MBOX_NULL) {
-      return ERR_MEM;
-    }
-  }
-  
-  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
-    return (conn->err = ERR_MEM);
-  }
-  msg->type = API_MSG_LISTEN;
-  msg->msg.conn = conn;
-  api_msg_post(msg);
-  sys_mbox_fetch(conn->mbox, NULL);
-  memp_free(MEMP_API_MSG, msg);
-  return conn->err;
-}
-
-struct netconn *
-netconn_accept(struct netconn *conn)
-{
-  struct netconn *newconn;
-  
-  if (conn == NULL) {
-    return NULL;
-  }
-  
-  sys_mbox_fetch(conn->acceptmbox, (void **)&newconn);
-  /* Register event with callback */
-  if (conn->callback)
-      (*conn->callback)(conn, NETCONN_EVT_RCVMINUS, 0);
-  
-  return newconn;
-}
-
-struct netbuf *
-netconn_recv(struct netconn *conn)
-{
-  struct api_msg *msg;
-  struct netbuf *buf;
-  struct pbuf *p;
-  u16_t len;
-    
-  if (conn == NULL) {
-    return NULL;
-  }
-  
-  if (conn->recvmbox == SYS_MBOX_NULL) {
-    conn->err = ERR_CONN;
-    return NULL;
-  }
-
-  if (conn->err != ERR_OK) {
-    return NULL;
-  }
-
-  if (conn->type == NETCONN_TCP) {
-    if (conn->pcb.tcp->state == LISTEN) {
-      conn->err = ERR_CONN;
-      return NULL;
-    }
-
-
-    buf = memp_malloc(MEMP_NETBUF);
-
-    if (buf == NULL) {
-      conn->err = ERR_MEM;
-      return NULL;
-    }
-    
-    sys_mbox_fetch(conn->recvmbox, (void **)&p);
-
-    if (p != NULL)
-    {
-        len = p->tot_len;
-        conn->recv_avail -= len;
-    }
-    else
-        len = 0;
-    
-    /* Register event with callback */
-      if (conn->callback)
-        (*conn->callback)(conn, NETCONN_EVT_RCVMINUS, len);
-
-    /* If we are closed, we indicate that we no longer wish to receive
-       data by setting conn->recvmbox to SYS_MBOX_NULL. */
-    if (p == NULL) {
-      memp_free(MEMP_NETBUF, buf);
-      sys_mbox_free(conn->recvmbox);
-      conn->recvmbox = SYS_MBOX_NULL;
-      return NULL;
-    }
-
-    buf->p = p;
-    buf->ptr = p;
-    buf->fromport = 0;
-    buf->fromaddr = NULL;
-
-    /* Let the stack know that we have taken the data. */
-    if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
-      conn->err = ERR_MEM;
-      return buf;
-    }
-    msg->type = API_MSG_RECV;
-    msg->msg.conn = conn;
-    if (buf != NULL) {
-      msg->msg.msg.len = buf->p->tot_len;
-    } else {
-      msg->msg.msg.len = 1;
-    }
-    api_msg_post(msg);
-
-    sys_mbox_fetch(conn->mbox, NULL);
-    memp_free(MEMP_API_MSG, msg);
-  } else {
-    sys_mbox_fetch(conn->recvmbox, (void **)&buf);
-  conn->recv_avail -= buf->p->tot_len;
-    /* Register event with callback */
-    if (conn->callback)
-        (*conn->callback)(conn, NETCONN_EVT_RCVMINUS, buf->p->tot_len);
-  }
-
-  
-
-    
-  LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_recv: received %p (err %d)\n", (void *)buf, conn->err));
-
-
-  return buf;
-}
-
-err_t
-netconn_send(struct netconn *conn, struct netbuf *buf)
-{
-  struct api_msg *msg;
-
-  if (conn == NULL) {
-    return ERR_VAL;
-  }
-
-  if (conn->err != ERR_OK) {
-    return conn->err;
-  }
-
-  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
-    return (conn->err = ERR_MEM);
-  }
-
-  LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_send: sending %d bytes\n", buf->p->tot_len));
-  msg->type = API_MSG_SEND;
-  msg->msg.conn = conn;
-  msg->msg.msg.p = buf->p;
-  api_msg_post(msg);
-
-  sys_mbox_fetch(conn->mbox, NULL);
-  memp_free(MEMP_API_MSG, msg);
-  return conn->err;
-}
-
-err_t
-netconn_write(struct netconn *conn, void *dataptr, u16_t size, u8_t copy)
-{
-  struct api_msg *msg;
-  u16_t len;
-  
-  if (conn == NULL) {
-    return ERR_VAL;
-  }
-
-  if (conn->err != ERR_OK) {
-    return conn->err;
-  }
-  
-  if (conn->sem == SYS_SEM_NULL) {
-    conn->sem = sys_sem_new(0);
-    if (conn->sem == SYS_SEM_NULL) {
-      return ERR_MEM;
-    }
-  }
-
-  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
-    return (conn->err = ERR_MEM);
-  }
-  msg->type = API_MSG_WRITE;
-  msg->msg.conn = conn;
-        
-
-  conn->state = NETCONN_WRITE;
-  while (conn->err == ERR_OK && size > 0) {
-    msg->msg.msg.w.dataptr = dataptr;
-    msg->msg.msg.w.copy = copy;
-    
-    if (conn->type == NETCONN_TCP) {
-      if (tcp_sndbuf(conn->pcb.tcp) == 0) {
-  sys_sem_wait(conn->sem);
-  if (conn->err != ERR_OK) {
-    goto ret;
-  }
-      }
-      if (size > tcp_sndbuf(conn->pcb.tcp)) {
-  /* We cannot send more than one send buffer's worth of data at a
-     time. */
-  len = tcp_sndbuf(conn->pcb.tcp);
-      } else {
-  len = size;
-      }
-    } else {
-      len = size;
-    }
-    
-    LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_write: writing %d bytes (%d)\n", len, copy));
-    msg->msg.msg.w.len = len;
-    api_msg_post(msg);
-    sys_mbox_fetch(conn->mbox, NULL);    
-    if (conn->err == ERR_OK) {
-      dataptr = (void *)((char *)dataptr + len);
-      size -= len;
-    } else if (conn->err == ERR_MEM) {
-      conn->err = ERR_OK;
-      sys_sem_wait(conn->sem);
-    } else {
-      goto ret;
-    }
-  }
- ret:
-  memp_free(MEMP_API_MSG, msg);
-  conn->state = NETCONN_NONE;
-  if (conn->sem != SYS_SEM_NULL) {
-    sys_sem_free(conn->sem);
-    conn->sem = SYS_SEM_NULL;
-  }
-  
-  return conn->err;
-}
-
-err_t
-netconn_close(struct netconn *conn)
-{
-  struct api_msg *msg;
-
-  if (conn == NULL) {
-    return ERR_VAL;
-  }
-  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
-    return (conn->err = ERR_MEM);
-  }
-
-  conn->state = NETCONN_CLOSE;
- again:
-  msg->type = API_MSG_CLOSE;
-  msg->msg.conn = conn;
-  api_msg_post(msg);
-  sys_mbox_fetch(conn->mbox, NULL);
-  if (conn->err == ERR_MEM &&
-     conn->sem != SYS_SEM_NULL) {
-    sys_sem_wait(conn->sem);
-    goto again;
-  }
-  conn->state = NETCONN_NONE;
-  memp_free(MEMP_API_MSG, msg);
-  return conn->err;
-}
-
-err_t
-netconn_err(struct netconn *conn)
-{
-  return conn->err;
-}
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/api/api_msg.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/api/api_msg.c
deleted file mode 100644
index 8247aaaab..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/api/api_msg.c
+++ /dev/null
@@ -1,810 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-
-#include "lwip/opt.h"
-#include "lwip/arch.h"
-#include "lwip/api_msg.h"
-#include "lwip/memp.h"
-#include "lwip/sys.h"
-#include "lwip/tcpip.h"
-
-#if LWIP_RAW
-static u8_t
-recv_raw(void *arg, struct raw_pcb *pcb, struct pbuf *p,
-    struct ip_addr *addr)
-{
-  struct netbuf *buf;
-  struct netconn *conn;
-
-  conn = arg;
-  if (!conn) return 0;
-
-  if (conn->recvmbox != SYS_MBOX_NULL) {
-    if (!(buf = memp_malloc(MEMP_NETBUF))) {
-      return 0;
-    }
-    pbuf_ref(p);
-    buf->p = p;
-    buf->ptr = p;
-    buf->fromaddr = addr;
-    buf->fromport = pcb->protocol;
-
-    conn->recv_avail += p->tot_len;
-    /* Register event with callback */
-    if (conn->callback)
-        (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, p->tot_len);
-    sys_mbox_post(conn->recvmbox, buf);
-  }
-
-  return 0; /* do not eat the packet */
-}
-#endif
-#if LWIP_UDP
-static void
-recv_udp(void *arg, struct udp_pcb *pcb, struct pbuf *p,
-   struct ip_addr *addr, u16_t port)
-{
-  struct netbuf *buf;
-  struct netconn *conn;
-
-  (void)pcb;
-
-  conn = arg;
-  
-  if (conn == NULL) {
-    pbuf_free(p);
-    return;
-  }
-  if (conn->recvmbox != SYS_MBOX_NULL) {
-    buf = memp_malloc(MEMP_NETBUF);
-    if (buf == NULL) {
-      pbuf_free(p);
-      return;
-    } else {
-      buf->p = p;
-      buf->ptr = p;
-      buf->fromaddr = addr;
-      buf->fromport = port;
-    }
-
-  conn->recv_avail += p->tot_len;
-    /* Register event with callback */
-    if (conn->callback)
-        (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, p->tot_len);
-    sys_mbox_post(conn->recvmbox, buf);
-  }
-}
-#endif /* LWIP_UDP */
-#if LWIP_TCP
-
-static err_t
-recv_tcp(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err)
-{
-  struct netconn *conn;
-  u16_t len;
-
-  (void)pcb;
-
-  conn = arg;
-
-  if (conn == NULL) {
-    pbuf_free(p);
-    return ERR_VAL;
-  }
-
-  if (conn->recvmbox != SYS_MBOX_NULL) {
-        
-    conn->err = err;
-    if (p != NULL) {
-        len = p->tot_len;
-        conn->recv_avail += len;
-    }
-    else
-        len = 0;
-    /* Register event with callback */
-    if (conn->callback)
-        (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, len);
-    sys_mbox_post(conn->recvmbox, p);
-  }  
-  return ERR_OK;
-}
-
-
-static err_t
-poll_tcp(void *arg, struct tcp_pcb *pcb)
-{
-  struct netconn *conn;
-
-  (void)pcb;
-
-  conn = arg;
-  if (conn != NULL &&
-     (conn->state == NETCONN_WRITE || conn->state == NETCONN_CLOSE) &&
-     conn->sem != SYS_SEM_NULL) {
-    sys_sem_signal(conn->sem);
-  }
-  return ERR_OK;
-}
-
-static err_t
-sent_tcp(void *arg, struct tcp_pcb *pcb, u16_t len)
-{
-  struct netconn *conn;
-
-  (void)pcb;
-
-  conn = arg;
-  if (conn != NULL && conn->sem != SYS_SEM_NULL) {
-    sys_sem_signal(conn->sem);
-  }
-
-  if (conn && conn->callback)
-      if (tcp_sndbuf(conn->pcb.tcp) > TCP_SNDLOWAT)
-          (*conn->callback)(conn, NETCONN_EVT_SENDPLUS, len);
-  
-  return ERR_OK;
-}
-
-static void
-err_tcp(void *arg, err_t err)
-{
-  struct netconn *conn;
-
-  conn = arg;
-
-  conn->pcb.tcp = NULL;
-
-  
-  conn->err = err;
-  if (conn->recvmbox != SYS_MBOX_NULL) {
-    /* Register event with callback */
-    if (conn->callback)
-      (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, 0);
-    sys_mbox_post(conn->recvmbox, NULL);
-  }
-  if (conn->mbox != SYS_MBOX_NULL) {
-    sys_mbox_post(conn->mbox, NULL);
-  }
-  if (conn->acceptmbox != SYS_MBOX_NULL) {
-     /* Register event with callback */
-    if (conn->callback)
-      (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, 0);
-    sys_mbox_post(conn->acceptmbox, NULL);
-  }
-  if (conn->sem != SYS_SEM_NULL) {
-    sys_sem_signal(conn->sem);
-  }
-}
-
-static void
-setup_tcp(struct netconn *conn)
-{
-  struct tcp_pcb *pcb;
-  
-  pcb = conn->pcb.tcp;
-  tcp_arg(pcb, conn);
-  tcp_recv(pcb, recv_tcp);
-  tcp_sent(pcb, sent_tcp);
-  tcp_poll(pcb, poll_tcp, 4);
-  tcp_err(pcb, err_tcp);
-}
-
-static err_t
-accept_function(void *arg, struct tcp_pcb *newpcb, err_t err)
-{
-  sys_mbox_t mbox;
-  struct netconn *newconn;
-  struct netconn *conn;
-  
-#if API_MSG_DEBUG
-#if TCP_DEBUG
-  tcp_debug_print_state(newpcb->state);
-#endif /* TCP_DEBUG */
-#endif /* API_MSG_DEBUG */
-  conn = (struct netconn *)arg;
-  mbox = conn->acceptmbox;
-  newconn = memp_malloc(MEMP_NETCONN);
-  if (newconn == NULL) {
-    return ERR_MEM;
-  }
-  newconn->type = NETCONN_TCP;
-  newconn->pcb.tcp = newpcb;
-  setup_tcp(newconn);
-  newconn->recvmbox = sys_mbox_new();
-  if (newconn->recvmbox == SYS_MBOX_NULL) {
-    memp_free(MEMP_NETCONN, newconn);
-    return ERR_MEM;
-  }
-  newconn->mbox = sys_mbox_new();
-  if (newconn->mbox == SYS_MBOX_NULL) {
-    sys_mbox_free(newconn->recvmbox);
-    memp_free(MEMP_NETCONN, newconn);
-    return ERR_MEM;
-  }
-  newconn->sem = sys_sem_new(0);
-  if (newconn->sem == SYS_SEM_NULL) {
-    sys_mbox_free(newconn->recvmbox);
-    sys_mbox_free(newconn->mbox);
-    memp_free(MEMP_NETCONN, newconn);
-    return ERR_MEM;
-  }
-  newconn->acceptmbox = SYS_MBOX_NULL;
-  newconn->err = err;
-  /* Register event with callback */
-  if (conn->callback)
-  {
-    (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, 0);
-    /* We have to set the callback here even though
-     * the new socket is unknown. Mark the socket as -1. */
-    newconn->callback = conn->callback;
-    newconn->socket = -1;
-  }
-  
-  sys_mbox_post(mbox, newconn);
-  return ERR_OK;
-}
-#endif /* LWIP_TCP */
-
-static void
-do_newconn(struct api_msg_msg *msg)
-{
-   if(msg->conn->pcb.tcp != NULL) {
-   /* This "new" connection already has a PCB allocated. */
-   /* Is this an error condition? Should it be deleted? 
-      We currently just are happy and return. */
-     sys_mbox_post(msg->conn->mbox, NULL);
-     return;
-   }
-
-   msg->conn->err = ERR_OK;
-
-   /* Allocate a PCB for this connection */
-   switch(msg->conn->type) {
-#if LWIP_RAW
-   case NETCONN_RAW:
-      msg->conn->pcb.raw = raw_new(msg->msg.bc.port); /* misusing the port field */
-      raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn);
-     break;
-#endif
-#if LWIP_UDP
-   case NETCONN_UDPLITE:
-      msg->conn->pcb.udp = udp_new();
-      if(msg->conn->pcb.udp == NULL) {
-         msg->conn->err = ERR_MEM;
-         break;
-      }
-      udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE);
-      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
-      break;
-   case NETCONN_UDPNOCHKSUM:
-      msg->conn->pcb.udp = udp_new();
-      if(msg->conn->pcb.udp == NULL) {
-         msg->conn->err = ERR_MEM;
-         break;
-      }
-      udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM);
-      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
-      break;
-   case NETCONN_UDP:
-      msg->conn->pcb.udp = udp_new();
-      if(msg->conn->pcb.udp == NULL) {
-         msg->conn->err = ERR_MEM;
-         break;
-      }
-      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
-      break;
-#endif /* LWIP_UDP */
-#if LWIP_TCP
-   case NETCONN_TCP:
-      msg->conn->pcb.tcp = tcp_new();
-      if(msg->conn->pcb.tcp == NULL) {
-         msg->conn->err = ERR_MEM;
-         break;
-      }
-      setup_tcp(msg->conn);
-      break;
-#endif
-   }
-   
-  
-  sys_mbox_post(msg->conn->mbox, NULL);
-}
-
-
-static void
-do_delconn(struct api_msg_msg *msg)
-{
-  if (msg->conn->pcb.tcp != NULL) {
-    switch (msg->conn->type) {
-#if LWIP_RAW
-    case NETCONN_RAW:
-      raw_remove(msg->conn->pcb.raw);
-      break;
-#endif
-#if LWIP_UDP
-    case NETCONN_UDPLITE:
-      /* FALLTHROUGH */
-    case NETCONN_UDPNOCHKSUM:
-      /* FALLTHROUGH */
-    case NETCONN_UDP:
-      msg->conn->pcb.udp->recv_arg = NULL;
-      udp_remove(msg->conn->pcb.udp);
-      break;
-#endif /* LWIP_UDP */
-#if LWIP_TCP      
-    case NETCONN_TCP:
-      if (msg->conn->pcb.tcp->state == LISTEN) {
-  tcp_arg(msg->conn->pcb.tcp, NULL);
-  tcp_accept(msg->conn->pcb.tcp, NULL);  
-  tcp_close(msg->conn->pcb.tcp);
-      } else {
-  tcp_arg(msg->conn->pcb.tcp, NULL);
-  tcp_sent(msg->conn->pcb.tcp, NULL);
-  tcp_recv(msg->conn->pcb.tcp, NULL);  
-  tcp_poll(msg->conn->pcb.tcp, NULL, 0);
-  tcp_err(msg->conn->pcb.tcp, NULL);
-  if (tcp_close(msg->conn->pcb.tcp) != ERR_OK) {
-    tcp_abort(msg->conn->pcb.tcp);
-  }
-      }
-#endif
-    default:  
-    break;
-    }
-  }
-  /* Trigger select() in socket layer */
-  if (msg->conn->callback)
-  {
-      (*msg->conn->callback)(msg->conn, NETCONN_EVT_RCVPLUS, 0);
-      (*msg->conn->callback)(msg->conn, NETCONN_EVT_SENDPLUS, 0);
-  }
-  
-  if (msg->conn->mbox != SYS_MBOX_NULL) {
-    sys_mbox_post(msg->conn->mbox, NULL);
-  }
-}
-
-static void
-do_bind(struct api_msg_msg *msg)
-{
-  if (msg->conn->pcb.tcp == NULL) {
-    switch (msg->conn->type) {
-#if LWIP_RAW
-    case NETCONN_RAW:
-      msg->conn->pcb.raw = raw_new(msg->msg.bc.port); /* misusing the port field as protocol */
-      raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn);
-      break;
-#endif
-#if LWIP_UDP
-    case NETCONN_UDPLITE:
-      msg->conn->pcb.udp = udp_new();
-      udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE);
-      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
-      break;
-    case NETCONN_UDPNOCHKSUM:
-      msg->conn->pcb.udp = udp_new();
-      udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM);
-      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
-      break;
-    case NETCONN_UDP:
-      msg->conn->pcb.udp = udp_new();
-      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
-      break;
-#endif /* LWIP_UDP */
-#if LWIP_TCP      
-    case NETCONN_TCP:
-      msg->conn->pcb.tcp = tcp_new();
-      setup_tcp(msg->conn);
-#endif /* LWIP_TCP */
-    default:  
-    break;
-    }
-  }
-  switch (msg->conn->type) {
-#if LWIP_RAW
-  case NETCONN_RAW:
-    msg->conn->err = raw_bind(msg->conn->pcb.raw,msg->msg.bc.ipaddr);
-    break;
-#endif
-#if LWIP_UDP
-  case NETCONN_UDPLITE:
-    /* FALLTHROUGH */
-  case NETCONN_UDPNOCHKSUM:
-    /* FALLTHROUGH */
-  case NETCONN_UDP:
-    msg->conn->err = udp_bind(msg->conn->pcb.udp, msg->msg.bc.ipaddr, msg->msg.bc.port);
-    break;
-#endif /* LWIP_UDP */
-#if LWIP_TCP
-  case NETCONN_TCP:
-    msg->conn->err = tcp_bind(msg->conn->pcb.tcp,
-            msg->msg.bc.ipaddr, msg->msg.bc.port);
-#endif /* LWIP_TCP */
-  default:
-    break;
-  }
-  sys_mbox_post(msg->conn->mbox, NULL);
-}
-#if LWIP_TCP
-
-static err_t
-do_connected(void *arg, struct tcp_pcb *pcb, err_t err)
-{
-  struct netconn *conn;
-
-  (void)pcb;
-
-  conn = arg;
-
-  if (conn == NULL) {
-    return ERR_VAL;
-  }
-  
-  conn->err = err;
-  if (conn->type == NETCONN_TCP && err == ERR_OK) {
-    setup_tcp(conn);
-  }    
-  sys_mbox_post(conn->mbox, NULL);
-  return ERR_OK;
-}
-#endif  
-
-static void
-do_connect(struct api_msg_msg *msg)
-{
-  if (msg->conn->pcb.tcp == NULL) {
-    switch (msg->conn->type) {
-#if LWIP_RAW
-    case NETCONN_RAW:
-      msg->conn->pcb.raw = raw_new(msg->msg.bc.port); /* misusing the port field as protocol */
-      raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn);
-      break;
-#endif
-#if LWIP_UDP
-    case NETCONN_UDPLITE:
-      msg->conn->pcb.udp = udp_new();
-      if (msg->conn->pcb.udp == NULL) {
-  msg->conn->err = ERR_MEM;
-  sys_mbox_post(msg->conn->mbox, NULL);
-  return;
-      }
-      udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE);
-      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
-      break;
-    case NETCONN_UDPNOCHKSUM:
-      msg->conn->pcb.udp = udp_new();
-      if (msg->conn->pcb.udp == NULL) {
-  msg->conn->err = ERR_MEM;
-  sys_mbox_post(msg->conn->mbox, NULL);
-  return;
-      }
-      udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM);
-      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
-      break;
-    case NETCONN_UDP:
-      msg->conn->pcb.udp = udp_new();
-      if (msg->conn->pcb.udp == NULL) {
-  msg->conn->err = ERR_MEM;
-  sys_mbox_post(msg->conn->mbox, NULL);
-  return;
-      }
-      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
-      break;
-#endif /* LWIP_UDP */
-#if LWIP_TCP      
-    case NETCONN_TCP:
-      msg->conn->pcb.tcp = tcp_new();      
-      if (msg->conn->pcb.tcp == NULL) {
-  msg->conn->err = ERR_MEM;
-  sys_mbox_post(msg->conn->mbox, NULL);
-  return;
-      }
-#endif
-    default:
-      break;
-    }
-  }
-  switch (msg->conn->type) {
-#if LWIP_RAW
-  case NETCONN_RAW:
-    raw_connect(msg->conn->pcb.raw, msg->msg.bc.ipaddr);
-    sys_mbox_post(msg->conn->mbox, NULL);
-    break;
-#endif
-#if LWIP_UDP
-  case NETCONN_UDPLITE:
-    /* FALLTHROUGH */
-  case NETCONN_UDPNOCHKSUM:
-    /* FALLTHROUGH */
-  case NETCONN_UDP:
-    udp_connect(msg->conn->pcb.udp, msg->msg.bc.ipaddr, msg->msg.bc.port);
-    sys_mbox_post(msg->conn->mbox, NULL);
-    break;
-#endif 
-#if LWIP_TCP      
-  case NETCONN_TCP:
-    /*    tcp_arg(msg->conn->pcb.tcp, msg->conn);*/
-    setup_tcp(msg->conn);
-    tcp_connect(msg->conn->pcb.tcp, msg->msg.bc.ipaddr, msg->msg.bc.port,
-    do_connected);
-    /*tcp_output(msg->conn->pcb.tcp);*/
-#endif
-
-  default:
-    break;
-  }
-}
-
-static void
-do_disconnect(struct api_msg_msg *msg)
-{
-
-  switch (msg->conn->type) {
-#if LWIP_RAW
-  case NETCONN_RAW:
-    /* Do nothing as connecting is only a helper for upper lwip layers */
-    break;
-#endif
-#if LWIP_UDP
-  case NETCONN_UDPLITE:
-    /* FALLTHROUGH */
-  case NETCONN_UDPNOCHKSUM:
-    /* FALLTHROUGH */
-  case NETCONN_UDP:
-    udp_disconnect(msg->conn->pcb.udp);
-    break;
-#endif 
-  case NETCONN_TCP:
-    break;
-  }
-  sys_mbox_post(msg->conn->mbox, NULL);
-}
-
-
-static void
-do_listen(struct api_msg_msg *msg)
-{
-  if (msg->conn->pcb.tcp != NULL) {
-    switch (msg->conn->type) {
-#if LWIP_RAW
-    case NETCONN_RAW:
-      LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: listen RAW: cannot listen for RAW.\n"));
-      break;
-#endif
-#if LWIP_UDP
-    case NETCONN_UDPLITE:
-      /* FALLTHROUGH */
-    case NETCONN_UDPNOCHKSUM:
-      /* FALLTHROUGH */
-    case NETCONN_UDP:
-      LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: listen UDP: cannot listen for UDP.\n"));
-      break;
-#endif /* LWIP_UDP */
-#if LWIP_TCP      
-    case NETCONN_TCP:
-      msg->conn->pcb.tcp = tcp_listen(msg->conn->pcb.tcp);
-      if (msg->conn->pcb.tcp == NULL) {
-  msg->conn->err = ERR_MEM;
-      } else {
-  if (msg->conn->acceptmbox == SYS_MBOX_NULL) {
-    msg->conn->acceptmbox = sys_mbox_new();
-    if (msg->conn->acceptmbox == SYS_MBOX_NULL) {
-      msg->conn->err = ERR_MEM;
-      break;
-    }
-  }
-  tcp_arg(msg->conn->pcb.tcp, msg->conn);
-  tcp_accept(msg->conn->pcb.tcp, accept_function);
-      }
-#endif
-    default:
-      break;
-    }
-  }
-  sys_mbox_post(msg->conn->mbox, NULL);
-}
-
-static void
-do_accept(struct api_msg_msg *msg)
-{
-  if (msg->conn->pcb.tcp != NULL) {
-    switch (msg->conn->type) {
-#if LWIP_RAW
-    case NETCONN_RAW:
-      LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: accept RAW: cannot accept for RAW.\n"));
-      break;
-#endif
-#if LWIP_UDP
-    case NETCONN_UDPLITE:
-      /* FALLTHROUGH */
-    case NETCONN_UDPNOCHKSUM:
-      /* FALLTHROUGH */
-    case NETCONN_UDP:    
-      LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: accept UDP: cannot accept for UDP.\n"));
-      break;
-#endif /* LWIP_UDP */
-    case NETCONN_TCP:
-      break;
-    }
-  }
-}
-
-static void
-do_send(struct api_msg_msg *msg)
-{
-  if (msg->conn->pcb.tcp != NULL) {
-    switch (msg->conn->type) {
-#if LWIP_RAW
-    case NETCONN_RAW:
-      raw_send(msg->conn->pcb.raw, msg->msg.p);
-      break;
-#endif
-#if LWIP_UDP
-    case NETCONN_UDPLITE:
-      /* FALLTHROUGH */
-    case NETCONN_UDPNOCHKSUM:
-      /* FALLTHROUGH */
-    case NETCONN_UDP:
-      udp_send(msg->conn->pcb.udp, msg->msg.p);
-      break;
-#endif /* LWIP_UDP */
-    case NETCONN_TCP:
-      break;
-    }
-  }
-  sys_mbox_post(msg->conn->mbox, NULL);
-}
-
-static void
-do_recv(struct api_msg_msg *msg)
-{
-#if LWIP_TCP
-  if (msg->conn->pcb.tcp != NULL) {
-    if (msg->conn->type == NETCONN_TCP) {
-      tcp_recved(msg->conn->pcb.tcp, msg->msg.len);
-    }
-  }
-#endif  
-  sys_mbox_post(msg->conn->mbox, NULL);
-}
-
-static void
-do_write(struct api_msg_msg *msg)
-{
-#if LWIP_TCP  
-  err_t err;
-#endif  
-  if (msg->conn->pcb.tcp != NULL) {
-    switch (msg->conn->type) {
-#if LWIP_RAW
-    case NETCONN_RAW:
-      msg->conn->err = ERR_VAL;
-      break;
-#endif
-#if LWIP_UDP 
-    case NETCONN_UDPLITE:
-      /* FALLTHROUGH */
-    case NETCONN_UDPNOCHKSUM:
-      /* FALLTHROUGH */
-    case NETCONN_UDP:
-      msg->conn->err = ERR_VAL;
-      break;
-#endif /* LWIP_UDP */
-#if LWIP_TCP 
-    case NETCONN_TCP:      
-      err = tcp_write(msg->conn->pcb.tcp, msg->msg.w.dataptr,
-                      msg->msg.w.len, msg->msg.w.copy);
-      /* This is the Nagle algorithm: inhibit the sending of new TCP
-   segments when new outgoing data arrives from the user if any
-   previously transmitted data on the connection remains
-   unacknowledged. */
-      if(err == ERR_OK && (msg->conn->pcb.tcp->unacked == NULL || (msg->conn->pcb.tcp->flags & TF_NODELAY)) ) {
-  tcp_output(msg->conn->pcb.tcp);
-      }
-      msg->conn->err = err;
-      if (msg->conn->callback)
-          if (err == ERR_OK)
-          {
-              if (tcp_sndbuf(msg->conn->pcb.tcp) <= TCP_SNDLOWAT)
-                  (*msg->conn->callback)(msg->conn, NETCONN_EVT_SENDMINUS, msg->msg.w.len);
-          }
-#endif
-    default:
-      break;
-    }
-  }
-  sys_mbox_post(msg->conn->mbox, NULL);
-}
-
-static void
-do_close(struct api_msg_msg *msg)
-{
-  err_t err;
-
-  err = ERR_OK;
-
-  if (msg->conn->pcb.tcp != NULL) {
-    switch (msg->conn->type) {
-#if LWIP_RAW
-    case NETCONN_RAW:
-      break;
-#endif
-#if LWIP_UDP
-    case NETCONN_UDPLITE:
-      /* FALLTHROUGH */
-    case NETCONN_UDPNOCHKSUM:
-      /* FALLTHROUGH */
-    case NETCONN_UDP:
-      break;
-#endif /* LWIP_UDP */
-#if LWIP_TCP
-    case NETCONN_TCP:
-      if (msg->conn->pcb.tcp->state == LISTEN) {
-  err = tcp_close(msg->conn->pcb.tcp);
-      }
-      msg->conn->err = err;      
-#endif
-    default:      
-      break;
-    }
-  }
-  sys_mbox_post(msg->conn->mbox, NULL);
-}
-
-typedef void (* api_msg_decode)(struct api_msg_msg *msg);
-static api_msg_decode decode[API_MSG_MAX] = {
-  do_newconn,
-  do_delconn,
-  do_bind,
-  do_connect,
-  do_disconnect,
-  do_listen,
-  do_accept,
-  do_send,
-  do_recv,
-  do_write,
-  do_close
-  };
-void
-api_msg_input(struct api_msg *msg)
-{  
-  decode[msg->type](&(msg->msg));
-}
-
-void
-api_msg_post(struct api_msg *msg)
-{
-  tcpip_apimsg(msg);
-}
-
-
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/api/err.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/api/err.c
deleted file mode 100644
index b582d88a2..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/api/err.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-
-#include "lwip/err.h"
-
-#ifdef LWIP_DEBUG
-
-static char *err_strerr[] = {"Ok.",
-           "Out of memory error.",
-           "Buffer error.",
-           "Connection aborted.",
-           "Connection reset.",
-           "Connection closed.",
-           "Not connected.",
-           "Illegal value.",
-           "Illegal argument.",
-           "Routing problem.",
-           "Address in use."
-};
-
-
-char *
-lwip_strerr(err_t err)
-{
-  return err_strerr[-err];
-
-}
-
-
-#endif /* LWIP_DEBUG */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/api/sockets.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/api/sockets.c
deleted file mode 100644
index 0528ac44f..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/api/sockets.c
+++ /dev/null
@@ -1,1359 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels 
- *
- * Improved by Marc Boucher  and David Haas 
- *
- */
-
-#include 
-#include 
-
-#include "lwip/opt.h"
-#include "lwip/api.h"
-#include "lwip/arch.h"
-#include "lwip/sys.h"
-
-#include "lwip/sockets.h"
-
-#define NUM_SOCKETS MEMP_NUM_NETCONN
-
-struct lwip_socket {
-  struct netconn *conn;
-  struct netbuf *lastdata;
-  u16_t lastoffset;
-  u16_t rcvevent;
-  u16_t sendevent;
-  u16_t  flags;
-  int err;
-};
-
-struct lwip_select_cb
-{
-    struct lwip_select_cb *next;
-    fd_set *readset;
-    fd_set *writeset;
-    fd_set *exceptset;
-    int sem_signalled;
-    sys_sem_t sem;
-};
-
-static struct lwip_socket sockets[NUM_SOCKETS];
-static struct lwip_select_cb *select_cb_list = 0;
-
-static sys_sem_t socksem = 0;
-static sys_sem_t selectsem = 0;
-
-static void
-event_callback(struct netconn *conn, enum netconn_evt evt, u16_t len);
-
-static int err_to_errno_table[11] = {
-    0,      /* ERR_OK    0      No error, everything OK. */
-    ENOMEM,    /* ERR_MEM  -1      Out of memory error.     */
-    ENOBUFS,    /* ERR_BUF  -2      Buffer error.            */
-    ECONNABORTED,  /* ERR_ABRT -3      Connection aborted.      */
-    ECONNRESET,    /* ERR_RST  -4      Connection reset.        */
-    ESHUTDOWN,    /* ERR_CLSD -5      Connection closed.       */
-    ENOTCONN,    /* ERR_CONN -6      Not connected.           */
-    EINVAL,    /* ERR_VAL  -7      Illegal value.           */
-    EIO,    /* ERR_ARG  -8      Illegal argument.        */
-    EHOSTUNREACH,  /* ERR_RTE  -9      Routing problem.         */
-    EADDRINUSE    /* ERR_USE  -10     Address in use.          */
-};
-
-#define err_to_errno(err) \
-  ((err) < (sizeof(err_to_errno_table)/sizeof(int))) ? \
-    err_to_errno_table[-(err)] : EIO
-
-#ifdef ERRNO
-#define set_errno(err) errno = (err)
-#else
-#define set_errno(err)
-#endif
-
-#define sock_set_errno(sk, e) do { \
-      sk->err = (e); \
-      set_errno(sk->err); \
-} while (0)
-
-
-static struct lwip_socket *
-get_socket(int s)
-{
-  struct lwip_socket *sock;
-
-  if ((s < 0) || (s > NUM_SOCKETS)) {
-    LWIP_DEBUGF(SOCKETS_DEBUG, ("get_socket(%d): invalid\n", s));
-    set_errno(EBADF);
-    return NULL;
-  }
-
-  sock = &sockets[s];
-
-  if (!sock->conn) {
-    LWIP_DEBUGF(SOCKETS_DEBUG, ("get_socket(%d): not active\n", s));
-    set_errno(EBADF);
-    return NULL;
-  }
-
-  return sock;
-}
-
-static int
-alloc_socket(struct netconn *newconn)
-{
-  int i;
-
-  if (!socksem)
-      socksem = sys_sem_new(1);
-
-  /* Protect socket array */
-  sys_sem_wait(socksem);
-
-  /* allocate a new socket identifier */
-  for(i = 0; i < NUM_SOCKETS; ++i) {
-    if (!sockets[i].conn) {
-      sockets[i].conn = newconn;
-      sockets[i].lastdata = NULL;
-      sockets[i].lastoffset = 0;
-      sockets[i].rcvevent = 0;
-      sockets[i].sendevent = 1; /* TCP send buf is empty */
-      sockets[i].flags = 0;
-      sockets[i].err = 0;
-      sys_sem_signal(socksem);
-      return i;
-    }
-  }
-  sys_sem_signal(socksem);
-  return -1;
-}
-
-int
-lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen)
-{
-  struct lwip_socket *sock;
-  struct netconn *newconn;
-  struct ip_addr naddr;
-  u16_t port;
-  int newsock;
-  struct sockaddr_in sin;
-
-  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d)...\n", s));
-  sock = get_socket(s);
-  if (!sock) {
-    set_errno(EBADF);
-    return -1;
-  }
-
-  newconn = netconn_accept(sock->conn);
-
-  /* get the IP address and port of the remote host */
-  netconn_peer(newconn, &naddr, &port);
-
-  memset(&sin, 0, sizeof(sin));
-  sin.sin_len = sizeof(sin);
-  sin.sin_family = AF_INET;
-  sin.sin_port = htons(port);
-  sin.sin_addr.s_addr = naddr.addr;
-
-  if (*addrlen > sizeof(sin))
-      *addrlen = sizeof(sin);
-
-  memcpy(addr, &sin, *addrlen);
-
-  newsock = alloc_socket(newconn);
-  if (newsock == -1) {
-    netconn_delete(newconn);
-  sock_set_errno(sock, ENOBUFS);
-  return -1;
-  }
-  newconn->callback = event_callback;
-  sock = get_socket(newsock);
-
-  sys_sem_wait(socksem);
-  sock->rcvevent += -1 - newconn->socket;
-  newconn->socket = newsock;
-  sys_sem_signal(socksem);
-
-  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d) returning new sock=%d addr=", s, newsock));
-  ip_addr_debug_print(SOCKETS_DEBUG, &naddr);
-  LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u\n", port));
-
-  sock_set_errno(sock, 0);
-  return newsock;
-}
-
-int
-lwip_bind(int s, struct sockaddr *name, socklen_t namelen)
-{
-  struct lwip_socket *sock;
-  struct ip_addr local_addr;
-  u16_t local_port;
-  err_t err;
-
-  sock = get_socket(s);
-  if (!sock) {
-    set_errno(EBADF);
-    return -1;
-  }
-
-  local_addr.addr = ((struct sockaddr_in *)name)->sin_addr.s_addr;
-  local_port = ((struct sockaddr_in *)name)->sin_port;
-
-  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d, addr=", s));
-  ip_addr_debug_print(SOCKETS_DEBUG, &local_addr);
-  LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u)\n", ntohs(local_port)));
-
-  err = netconn_bind(sock->conn, &local_addr, ntohs(local_port));
-
-  if (err != ERR_OK) {
-    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d) failed, err=%d\n", s, err));
-    sock_set_errno(sock, err_to_errno(err));
-    return -1;
-  }
-
-  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d) succeeded\n", s));
-  sock_set_errno(sock, 0);
-  return 0;
-}
-
-int
-lwip_close(int s)
-{
-  struct lwip_socket *sock;
-
-  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_close(%d)\n", s));
-  if (!socksem)
-      socksem = sys_sem_new(1);
-
-  /* We cannot allow multiple closes of the same socket. */
-  sys_sem_wait(socksem);
-
-  sock = get_socket(s);
-  if (!sock) {
-      sys_sem_signal(socksem);
-      set_errno(EBADF);
-      return -1;
-  }
-
-  netconn_delete(sock->conn);
-  if (sock->lastdata) {
-    netbuf_delete(sock->lastdata);
-  }
-  sock->lastdata = NULL;
-  sock->lastoffset = 0;
-  sock->conn = NULL;
-  sys_sem_signal(socksem);
-  sock_set_errno(sock, 0);
-  return 0;
-}
-
-int
-lwip_connect(int s, struct sockaddr *name, socklen_t namelen)
-{
-  struct lwip_socket *sock;
-  err_t err;
-
-  sock = get_socket(s);
-  if (!sock) {
-    set_errno(EBADF);
-    return -1;
-  }
-
-  if (((struct sockaddr_in *)name)->sin_family == AF_UNSPEC) {
-    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d, AF_UNSPEC)\n", s));
-    err = netconn_disconnect(sock->conn);
-  } else {
-    struct ip_addr remote_addr;
-    u16_t remote_port;
-
-    remote_addr.addr = ((struct sockaddr_in *)name)->sin_addr.s_addr;
-    remote_port = ((struct sockaddr_in *)name)->sin_port;
-
-    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d, addr=", s));
-    ip_addr_debug_print(SOCKETS_DEBUG, &remote_addr);
-    LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u)\n", ntohs(remote_port)));
-
-    err = netconn_connect(sock->conn, &remote_addr, ntohs(remote_port));
-   }
-
-  if (err != ERR_OK) {
-    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d) failed, err=%d\n", s, err));
-    sock_set_errno(sock, err_to_errno(err));
-    return -1;
-  }
-
-  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d) succeeded\n", s));
-  sock_set_errno(sock, 0);
-  return 0;
-}
-
-int
-lwip_listen(int s, int backlog)
-{
-  struct lwip_socket *sock;
-  err_t err;
-
-  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_listen(%d, backlog=%d)\n", s, backlog));
-  sock = get_socket(s);
-  if (!sock) {
-    set_errno(EBADF);
-    return -1;
-  }
-
-  err = netconn_listen(sock->conn);
-
-  if (err != ERR_OK) {
-    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_listen(%d) failed, err=%d\n", s, err));
-    sock_set_errno(sock, err_to_errno(err));
-    return -1;
-  }
-
-  sock_set_errno(sock, 0);
-  return 0;
-}
-
-int
-lwip_recvfrom(int s, void *mem, int len, unsigned int flags,
-        struct sockaddr *from, socklen_t *fromlen)
-{
-  struct lwip_socket *sock;
-  struct netbuf *buf;
-  u16_t buflen, copylen;
-  struct ip_addr *addr;
-  u16_t port;
-
-
-  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d, %p, %d, 0x%x, ..)\n", s, mem, len, flags));
-  sock = get_socket(s);
-  if (!sock) {
-    set_errno(EBADF);
-    return -1;
-  }
-
-  /* Check if there is data left from the last recv operation. */
-  if (sock->lastdata) {
-    buf = sock->lastdata;
-  } else {
-    /* If this is non-blocking call, then check first */
-    if (((flags & MSG_DONTWAIT) || (sock->flags & O_NONBLOCK))
-  && !sock->rcvevent)
-    {
-      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): returning EWOULDBLOCK\n", s));
-      sock_set_errno(sock, EWOULDBLOCK);
-      return -1;
-    }
-
-    /* No data was left from the previous operation, so we try to get
-       some from the network. */
-    buf = netconn_recv(sock->conn);
-
-    if (!buf) {
-      /* We should really do some error checking here. */
-      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): buf == NULL!\n", s));
-      sock_set_errno(sock, 0);
-      return 0;
-    }
-  }
-
-  buflen = netbuf_len(buf);
-
-  buflen -= sock->lastoffset;
-
-  if (len > buflen) {
-    copylen = buflen;
-  } else {
-    copylen = len;
-  }
-
-  /* copy the contents of the received buffer into
-     the supplied memory pointer mem */
-  netbuf_copy_partial(buf, mem, copylen, sock->lastoffset);
-
-  /* Check to see from where the data was. */
-  if (from && fromlen) {
-    struct sockaddr_in sin;
-
-    addr = netbuf_fromaddr(buf);
-    port = netbuf_fromport(buf);
-
-    memset(&sin, 0, sizeof(sin));
-    sin.sin_len = sizeof(sin);
-    sin.sin_family = AF_INET;
-    sin.sin_port = htons(port);
-    sin.sin_addr.s_addr = addr->addr;
-
-    if (*fromlen > sizeof(sin))
-      *fromlen = sizeof(sin);
-
-    memcpy(from, &sin, *fromlen);
-
-    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): addr=", s));
-    ip_addr_debug_print(SOCKETS_DEBUG, addr);
-    LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u len=%u\n", port, copylen));
-  } else {
-#if SOCKETS_DEBUG
-    addr = netbuf_fromaddr(buf);
-    port = netbuf_fromport(buf);
-
-    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): addr=", s));
-    ip_addr_debug_print(SOCKETS_DEBUG, addr);
-    LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u len=%u\n", port, copylen));
-#endif
-
-  }
-
-  /* If this is a TCP socket, check if there is data left in the
-     buffer. If so, it should be saved in the sock structure for next
-     time around. */
-  if (netconn_type(sock->conn) == NETCONN_TCP && buflen - copylen > 0) {
-    sock->lastdata = buf;
-    sock->lastoffset += copylen;
-  } else {
-    sock->lastdata = NULL;
-    sock->lastoffset = 0;
-    netbuf_delete(buf);
-  }
-
-
-  sock_set_errno(sock, 0);
-  return copylen;
-}
-
-int
-lwip_read(int s, void *mem, int len)
-{
-  return lwip_recvfrom(s, mem, len, 0, NULL, NULL);
-}
-
-int
-lwip_recv(int s, void *mem, int len, unsigned int flags)
-{
-  return lwip_recvfrom(s, mem, len, flags, NULL, NULL);
-}
-
-int
-lwip_send(int s, void *data, int size, unsigned int flags)
-{
-  struct lwip_socket *sock;
-  struct netbuf *buf;
-  err_t err;
-
-  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d, data=%p, size=%d, flags=0x%x)\n", s, data, size, flags));
-
-  sock = get_socket(s);
-  if (!sock) {
-    set_errno(EBADF);
-    return -1;
-  }
-
-  switch (netconn_type(sock->conn)) {
-  case NETCONN_RAW:
-  case NETCONN_UDP:
-  case NETCONN_UDPLITE:
-  case NETCONN_UDPNOCHKSUM:
-    /* create a buffer */
-    buf = netbuf_new();
-
-    if (!buf) {
-      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d) ENOBUFS\n", s));
-      sock_set_errno(sock, ENOBUFS);
-      return -1;
-    }
-
-    /* make the buffer point to the data that should
-       be sent */
-    netbuf_ref(buf, data, size);
-
-    /* send the data */
-    err = netconn_send(sock->conn, buf);
-
-    /* deallocated the buffer */
-    netbuf_delete(buf);
-    break;
-  case NETCONN_TCP:
-    err = netconn_write(sock->conn, data, size, NETCONN_COPY);
-    break;
-  default:
-    err = ERR_ARG;
-    break;
-  }
-  if (err != ERR_OK) {
-    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d) err=%d\n", s, err));
-    sock_set_errno(sock, err_to_errno(err));
-    return -1;
-  }
-
-  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d) ok size=%d\n", s, size));
-  sock_set_errno(sock, 0);
-  return size;
-}
-
-int
-lwip_sendto(int s, void *data, int size, unsigned int flags,
-       struct sockaddr *to, socklen_t tolen)
-{
-  struct lwip_socket *sock;
-  struct ip_addr remote_addr, addr;
-  u16_t remote_port, port;
-  int ret,connected;
-
-  sock = get_socket(s);
-  if (!sock) {
-    set_errno(EBADF);
-    return -1;
-  }
-
-  /* get the peer if currently connected */
-  connected = (netconn_peer(sock->conn, &addr, &port) == ERR_OK);
-
-  remote_addr.addr = ((struct sockaddr_in *)to)->sin_addr.s_addr;
-  remote_port = ((struct sockaddr_in *)to)->sin_port;
-
-  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_sendto(%d, data=%p, size=%d, flags=0x%x to=", s, data, size, flags));
-  ip_addr_debug_print(SOCKETS_DEBUG, &remote_addr);
-  LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u\n", ntohs(remote_port)));
-
-  netconn_connect(sock->conn, &remote_addr, ntohs(remote_port));
-
-  ret = lwip_send(s, data, size, flags);
-
-  /* reset the remote address and port number
-     of the connection */
-  if (connected)
-    netconn_connect(sock->conn, &addr, port);
-  else
-  netconn_disconnect(sock->conn);
-  return ret;
-}
-
-int
-lwip_socket(int domain, int type, int protocol)
-{
-  struct netconn *conn;
-  int i;
-
-  /* create a netconn */
-  switch (type) {
-  case SOCK_RAW:
-    conn = netconn_new_with_proto_and_callback(NETCONN_RAW, protocol, event_callback);
-    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_RAW, %d) = ", domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol));
-    break;
-  case SOCK_DGRAM:
-    conn = netconn_new_with_callback(NETCONN_UDP, event_callback);
-    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_DGRAM, %d) = ", domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol));
-    break;
-  case SOCK_STREAM:
-    conn = netconn_new_with_callback(NETCONN_TCP, event_callback);
-    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_STREAM, %d) = ", domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol));
-    break;
-  default:
-    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%d, %d/UNKNOWN, %d) = -1\n", domain, type, protocol));
-    set_errno(EINVAL);
-    return -1;
-  }
-
-  if (!conn) {
-    LWIP_DEBUGF(SOCKETS_DEBUG, ("-1 / ENOBUFS (could not create netconn)\n"));
-    set_errno(ENOBUFS);
-    return -1;
-  }
-
-  i = alloc_socket(conn);
-
-  if (i == -1) {
-    netconn_delete(conn);
-  set_errno(ENOBUFS);
-  return -1;
-  }
-  conn->socket = i;
-  LWIP_DEBUGF(SOCKETS_DEBUG, ("%d\n", i));
-  set_errno(0);
-  return i;
-}
-
-int
-lwip_write(int s, void *data, int size)
-{
-   return lwip_send(s, data, size, 0);
-}
-
-
-static int
-lwip_selscan(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset)
-{
-    int i, nready = 0;
-    fd_set lreadset, lwriteset, lexceptset;
-    struct lwip_socket *p_sock;
-
-    FD_ZERO(&lreadset);
-    FD_ZERO(&lwriteset);
-    FD_ZERO(&lexceptset);
-
-    /* Go through each socket in each list to count number of sockets which
-       currently match */
-    for(i = 0; i < maxfdp1; i++)
-    {
-        if (FD_ISSET(i, readset))
-        {
-            /* See if netconn of this socket is ready for read */
-            p_sock = get_socket(i);
-            if (p_sock && (p_sock->lastdata || p_sock->rcvevent))
-            {
-                FD_SET(i, &lreadset);
-		LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for reading\n", i));
-                nready++;
-            }
-        }
-        if (FD_ISSET(i, writeset))
-        {
-            /* See if netconn of this socket is ready for write */
-            p_sock = get_socket(i);
-            if (p_sock && p_sock->sendevent)
-            {
-                FD_SET(i, &lwriteset);
-		LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for writing\n", i));
-                nready++;
-            }
-        }
-    }
-    *readset = lreadset;
-    *writeset = lwriteset;
-    FD_ZERO(exceptset);
-
-    return nready;
-}
-
-
-
-int
-lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset,
-               struct timeval *timeout)
-{
-    int i;
-    int nready;
-    fd_set lreadset, lwriteset, lexceptset;
-    u32_t msectimeout;
-    struct lwip_select_cb select_cb;
-    struct lwip_select_cb *p_selcb;
-
-    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select(%d, %p, %p, %p, tvsec=%ld tvusec=%ld)\n", maxfdp1, (void *)readset, (void *) writeset, (void *) exceptset, timeout ? timeout->tv_sec : -1L, timeout ? timeout->tv_usec : -1L));
-
-    select_cb.next = 0;
-    select_cb.readset = readset;
-    select_cb.writeset = writeset;
-    select_cb.exceptset = exceptset;
-    select_cb.sem_signalled = 0;
-
-    /* Protect ourselves searching through the list */
-    if (!selectsem)
-        selectsem = sys_sem_new(1);
-    sys_sem_wait(selectsem);
-
-    if (readset)
-        lreadset = *readset;
-    else
-        FD_ZERO(&lreadset);
-    if (writeset)
-        lwriteset = *writeset;
-    else
-        FD_ZERO(&lwriteset);
-    if (exceptset)
-        lexceptset = *exceptset;
-    else
-        FD_ZERO(&lexceptset);
-
-    /* Go through each socket in each list to count number of sockets which
-       currently match */
-    nready = lwip_selscan(maxfdp1, &lreadset, &lwriteset, &lexceptset);
-
-    /* If we don't have any current events, then suspend if we are supposed to */
-    if (!nready)
-    {
-        if (timeout && timeout->tv_sec == 0 && timeout->tv_usec == 0)
-        {
-            sys_sem_signal(selectsem);
-            if (readset)
-                FD_ZERO(readset);
-            if (writeset)
-                FD_ZERO(writeset);
-            if (exceptset)
-                FD_ZERO(exceptset);
-
-	    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: no timeout, returning 0\n"));
-	    set_errno(0);
-
-            return 0;
-        }
-
-        /* add our semaphore to list */
-        /* We don't actually need any dynamic memory. Our entry on the
-         * list is only valid while we are in this function, so it's ok
-         * to use local variables */
-
-        select_cb.sem = sys_sem_new(0);
-        /* Note that we are still protected */
-        /* Put this select_cb on top of list */
-        select_cb.next = select_cb_list;
-        select_cb_list = &select_cb;
-
-        /* Now we can safely unprotect */
-        sys_sem_signal(selectsem);
-
-        /* Now just wait to be woken */
-        if (timeout == 0)
-            /* Wait forever */
-            msectimeout = 0;
-        else
-            msectimeout =  ((timeout->tv_sec * 1000) + ((timeout->tv_usec + 500)/1000));
-
-        i = sys_sem_wait_timeout(select_cb.sem, msectimeout);
-
-        /* Take us off the list */
-        sys_sem_wait(selectsem);
-        if (select_cb_list == &select_cb)
-            select_cb_list = select_cb.next;
-        else
-            for (p_selcb = select_cb_list; p_selcb; p_selcb = p_selcb->next)
-                if (p_selcb->next == &select_cb)
-                {
-                    p_selcb->next = select_cb.next;
-                    break;
-                }
-
-        sys_sem_signal(selectsem);
-
-        sys_sem_free(select_cb.sem);
-        if (i == 0)             /* Timeout */
-        {
-            if (readset)
-                FD_ZERO(readset);
-            if (writeset)
-                FD_ZERO(writeset);
-            if (exceptset)
-                FD_ZERO(exceptset);
-
-	    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: timeout expired\n"));
-	    set_errno(0);
-
-            return 0;
-        }
-
-        if (readset)
-            lreadset = *readset;
-        else
-            FD_ZERO(&lreadset);
-        if (writeset)
-            lwriteset = *writeset;
-        else
-            FD_ZERO(&lwriteset);
-        if (exceptset)
-            lexceptset = *exceptset;
-        else
-            FD_ZERO(&lexceptset);
-
-        /* See what's set */
-        nready = lwip_selscan(maxfdp1, &lreadset, &lwriteset, &lexceptset);
-    }
-    else
-        sys_sem_signal(selectsem);
-
-    if (readset)
-        *readset = lreadset;
-    if (writeset)
-        *writeset = lwriteset;
-    if (exceptset)
-        *exceptset = lexceptset;
-
-    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: nready=%d\n", nready));
-    set_errno(0);
-
-    return nready;
-}
-
-
-static void
-event_callback(struct netconn *conn, enum netconn_evt evt, u16_t len)
-{
-    int s;
-    struct lwip_socket *sock;
-    struct lwip_select_cb *scb;
-
-    /* Get socket */
-    if (conn)
-    {
-        s = conn->socket;
-        if (s < 0)
-        {
-            /* Data comes in right away after an accept, even though
-             * the server task might not have created a new socket yet.
-             * Just count down (or up) if that's the case and we
-             * will use the data later. Note that only receive events
-             * can happen before the new socket is set up. */
-            if (evt == NETCONN_EVT_RCVPLUS)
-                conn->socket--;
-            return;
-        }
-
-        sock = get_socket(s);
-        if (!sock)
-            return;
-    }
-    else
-        return;
-
-    if (!selectsem)
-        selectsem = sys_sem_new(1);
-
-    sys_sem_wait(selectsem);
-    /* Set event as required */
-    switch (evt)
-    {
-      case NETCONN_EVT_RCVPLUS:
-        sock->rcvevent++;
-        break;
-      case NETCONN_EVT_RCVMINUS:
-        sock->rcvevent--;
-        break;
-      case NETCONN_EVT_SENDPLUS:
-        sock->sendevent = 1;
-        break;
-      case NETCONN_EVT_SENDMINUS:
-        sock->sendevent = 0;
-        break;
-    }
-    sys_sem_signal(selectsem);
-
-    /* Now decide if anyone is waiting for this socket */
-    /* NOTE: This code is written this way to protect the select link list
-       but to avoid a deadlock situation by releasing socksem before
-       signalling for the select. This means we need to go through the list
-       multiple times ONLY IF a select was actually waiting. We go through
-       the list the number of waiting select calls + 1. This list is
-       expected to be small. */
-    while (1)
-    {
-        sys_sem_wait(selectsem);
-        for (scb = select_cb_list; scb; scb = scb->next)
-        {
-            if (scb->sem_signalled == 0)
-            {
-                /* Test this select call for our socket */
-                if (scb->readset && FD_ISSET(s, scb->readset))
-                    if (sock->rcvevent)
-                        break;
-                if (scb->writeset && FD_ISSET(s, scb->writeset))
-                    if (sock->sendevent)
-                        break;
-            }
-        }
-        if (scb)
-        {
-            scb->sem_signalled = 1;
-            sys_sem_signal(selectsem);
-            sys_sem_signal(scb->sem);
-        } else {
-            sys_sem_signal(selectsem);
-            break;
-        }
-    }
-
-}
-
-
-
-
-int lwip_shutdown(int s, int how)
-{
-  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_shutdown(%d, how=%d)\n", s, how));
-  return lwip_close(s); /* XXX temporary hack until proper implementation */
-}
-
-int lwip_getpeername (int s, struct sockaddr *name, socklen_t *namelen)
-{
-  struct lwip_socket *sock;
-  struct sockaddr_in sin;
-  struct ip_addr naddr;
-
-  sock = get_socket(s);
-  if (!sock) {
-    set_errno(EBADF);
-    return -1;
-  }
-
-  memset(&sin, 0, sizeof(sin));
-  sin.sin_len = sizeof(sin);
-  sin.sin_family = AF_INET;
-
-  /* get the IP address and port of the remote host */
-  netconn_peer(sock->conn, &naddr, &sin.sin_port);
-
-  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getpeername(%d, addr=", s));
-  ip_addr_debug_print(SOCKETS_DEBUG, &naddr);
-  LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%d)\n", sin.sin_port));
-
-  sin.sin_port = htons(sin.sin_port);
-  sin.sin_addr.s_addr = naddr.addr;
-
-  if (*namelen > sizeof(sin))
-      *namelen = sizeof(sin);
-
-  memcpy(name, &sin, *namelen);
-  sock_set_errno(sock, 0);
-  return 0;
-}
-
-int lwip_getsockname (int s, struct sockaddr *name, socklen_t *namelen)
-{
-  struct lwip_socket *sock;
-  struct sockaddr_in sin;
-  struct ip_addr *naddr;
-
-  sock = get_socket(s);
-  if (!sock) {
-    set_errno(EBADF);
-    return -1;
-  }
-
-  memset(&sin, 0, sizeof(sin));
-  sin.sin_len = sizeof(sin);
-  sin.sin_family = AF_INET;
-
-  /* get the IP address and port of the remote host */
-  netconn_addr(sock->conn, &naddr, &sin.sin_port);
-
-  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockname(%d, addr=", s));
-  ip_addr_debug_print(SOCKETS_DEBUG, naddr);
-  LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%d)\n", sin.sin_port));
-
-  sin.sin_port = htons(sin.sin_port);
-  sin.sin_addr.s_addr = naddr->addr;
-
-  if (*namelen > sizeof(sin))
-      *namelen = sizeof(sin);
-
-  memcpy(name, &sin, *namelen);
-  sock_set_errno(sock, 0);
-  return 0;
-}
-
-int lwip_getsockopt (int s, int level, int optname, void *optval, socklen_t *optlen)
-{
-  int err = 0;
-  struct lwip_socket *sock = get_socket(s);
-
-  if(!sock) {
-   	set_errno(EBADF);
-    return -1;
-  }
-
-  if( NULL == optval || NULL == optlen ) {
-    sock_set_errno( sock, EFAULT );
-    return -1;
-  }
-
-  /* Do length and type checks for the various options first, to keep it readable. */
-  switch( level ) {
-   
-/* Level: SOL_SOCKET */
-  case SOL_SOCKET:
-      switch(optname) {
-         
-      case SO_ACCEPTCONN:
-      case SO_BROADCAST:
-      /* UNIMPL case SO_DEBUG: */
-      /* UNIMPL case SO_DONTROUTE: */
-      case SO_ERROR:
-      case SO_KEEPALIVE:
-      /* UNIMPL case SO_OOBINLINE: */
-      /* UNIMPL case SO_RCVBUF: */
-      /* UNIMPL case SO_SNDBUF: */
-      /* UNIMPL case SO_RCVLOWAT: */
-      /* UNIMPL case SO_SNDLOWAT: */
-#if SO_REUSE
-      case SO_REUSEADDR:
-      case SO_REUSEPORT:
-#endif /* SO_REUSE */
-      case SO_TYPE:
-      /* UNIMPL case SO_USELOOPBACK: */
-        if( *optlen < sizeof(int) ) {
-          err = EINVAL;
-        }
-          break;
-
-      default:
-        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, UNIMPL: optname=0x%x, ..)\n", s, optname));
-        err = ENOPROTOOPT;
-      }  /* switch */
-      break;
-                     
-/* Level: IPPROTO_IP */
-  case IPPROTO_IP:
-      switch(optname) {
-      /* UNIMPL case IP_HDRINCL: */
-      /* UNIMPL case IP_RCVDSTADDR: */
-      /* UNIMPL case IP_RCVIF: */
-      case IP_TTL:
-      case IP_TOS:
-        if( *optlen < sizeof(int) ) {
-          err = EINVAL;
-        }
-        break;
-
-      default:
-        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, UNIMPL: optname=0x%x, ..)\n", s, optname));
-        err = ENOPROTOOPT;
-      }  /* switch */
-      break;
-         
-/* Level: IPPROTO_TCP */
-  case IPPROTO_TCP:
-      if( *optlen < sizeof(int) ) {
-        err = EINVAL;
-        break;
-    }
-      
-      /* If this is no TCP socket, ignore any options. */
-      if ( sock->conn->type != NETCONN_TCP ) return 0;
-
-      switch( optname ) {
-      case TCP_NODELAY:
-      case TCP_KEEPALIVE:
-        break;
-         
-      default:
-        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, UNIMPL: optname=0x%x, ..)\n", s, optname));
-        err = ENOPROTOOPT;
-      }  /* switch */
-      break;
-
-/* UNDEFINED LEVEL */
-  default:
-      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, level=0x%x, UNIMPL: optname=0x%x, ..)\n", s, level, optname));
-      err = ENOPROTOOPT;
-  }  /* switch */
-
-   
-  if( 0 != err ) {
-    sock_set_errno(sock, err);
-    return -1;
-  }
-   
-
-
-  /* Now do the actual option processing */
-
-  switch(level) {
-   
-/* Level: SOL_SOCKET */
-  case SOL_SOCKET:
-    switch( optname ) {
-
-    /* The option flags */
-    case SO_ACCEPTCONN:
-    case SO_BROADCAST:
-    /* UNIMPL case SO_DEBUG: */
-    /* UNIMPL case SO_DONTROUTE: */
-    case SO_KEEPALIVE:
-    /* UNIMPL case SO_OOBINCLUDE: */
-#if SO_REUSE
-    case SO_REUSEADDR:
-    case SO_REUSEPORT:
-#endif /* SO_REUSE */
-    /*case SO_USELOOPBACK: UNIMPL */
-      *(int*)optval = sock->conn->pcb.tcp->so_options & optname;
-      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, optname=0x%x, ..) = %s\n", s, optname, (*(int*)optval?"on":"off")));
-      break;
-
-    case SO_TYPE:
-      switch (sock->conn->type) {
-      case NETCONN_RAW:
-        *(int*)optval = SOCK_RAW;
-        break;
-      case NETCONN_TCP:
-        *(int*)optval = SOCK_STREAM;
-        break;
-      case NETCONN_UDP:
-      case NETCONN_UDPLITE:
-      case NETCONN_UDPNOCHKSUM:
-        *(int*)optval = SOCK_DGRAM;
-        break;
-      default: /* unrecognized socket type */
-        *(int*)optval = sock->conn->type;
-        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_TYPE): unrecognized socket type %d\n", s, *(int *)optval));
-      }  /* switch */
-      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_TYPE) = %d\n", s, *(int *)optval));
-      break;
-
-    case SO_ERROR:
-      *(int *)optval = sock->err;
-      sock->err = 0;
-      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_ERROR) = %d\n", s, *(int *)optval));
-      break;
-    }  /* switch */
-    break;
-
-/* Level: IPPROTO_IP */
-  case IPPROTO_IP:
-    switch( optname ) {
-    case IP_TTL:
-      *(int*)optval = sock->conn->pcb.tcp->ttl;
-      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_TTL) = %d\n", s, *(int *)optval));
-      break;
-    case IP_TOS:
-      *(int*)optval = sock->conn->pcb.tcp->tos;
-      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_TOS) = %d\n", s, *(int *)optval));
-      break;
-    }  /* switch */
-    break;
-
-/* Level: IPPROTO_TCP */
-  case IPPROTO_TCP:
-    switch( optname ) {
-    case TCP_NODELAY:
-      *(int*)optval = (sock->conn->pcb.tcp->flags & TF_NODELAY);
-      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, TCP_NODELAY) = %s\n", s, (*(int*)optval)?"on":"off") );
-      break;
-    case TCP_KEEPALIVE:
-      *(int*)optval = (int)sock->conn->pcb.tcp->keepalive;
-      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, TCP_KEEPALIVE) = %d\n", s, *(int *)optval));
-      break;
-    }  /* switch */
-    break;
-  }
-
-
-  sock_set_errno(sock, err);
-  return err ? -1 : 0;
-}
-
-int lwip_setsockopt (int s, int level, int optname, const void *optval, socklen_t optlen)
-{
-  struct lwip_socket *sock = get_socket(s);
-  int err = 0;
-
-  if(!sock) {
-   	set_errno(EBADF);
-    return -1;
-  }
-
-  if( NULL == optval ) {
-    sock_set_errno( sock, EFAULT );
-    return -1;
-  }
-
-
-  /* Do length and type checks for the various options first, to keep it readable. */
-  switch( level ) {
-
-/* Level: SOL_SOCKET */
-  case SOL_SOCKET:
-    switch(optname) {
-
-    case SO_BROADCAST:
-    /* UNIMPL case SO_DEBUG: */
-    /* UNIMPL case SO_DONTROUTE: */
-    case SO_KEEPALIVE:
-    /* UNIMPL case SO_OOBINLINE: */
-    /* UNIMPL case SO_RCVBUF: */
-    /* UNIMPL case SO_SNDBUF: */
-    /* UNIMPL case SO_RCVLOWAT: */
-    /* UNIMPL case SO_SNDLOWAT: */
-#if SO_REUSE
-    case SO_REUSEADDR:
-    case SO_REUSEPORT:
-#endif /* SO_REUSE */
-    /* UNIMPL case SO_USELOOPBACK: */
-      if( optlen < sizeof(int) ) {
-        err = EINVAL;
-      }
-      break;
-    default:
-      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, SOL_SOCKET, UNIMPL: optname=0x%x, ..)\n", s, optname));
-      err = ENOPROTOOPT;
-    }  /* switch */
-    break;
-
-/* Level: IPPROTO_IP */
-  case IPPROTO_IP:
-    switch(optname) {
-    /* UNIMPL case IP_HDRINCL: */
-    /* UNIMPL case IP_RCVDSTADDR: */
-    /* UNIMPL case IP_RCVIF: */
-    case IP_TTL:
-    case IP_TOS:
-      if( optlen < sizeof(int) ) {
-        err = EINVAL;
-      }
-        break;
-      default:
-      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, UNIMPL: optname=0x%x, ..)\n", s, optname));
-      err = ENOPROTOOPT;
-    }  /* switch */
-    break;
-
-/* Level: IPPROTO_TCP */
-  case IPPROTO_TCP:
-    if( optlen < sizeof(int) ) {
-      err = EINVAL;
-        break;
-    }
-
-    /* If this is no TCP socket, ignore any options. */
-    if ( sock->conn->type != NETCONN_TCP ) return 0;
-
-    switch( optname ) {
-    case TCP_NODELAY:
-    case TCP_KEEPALIVE:
-      break;
-
-    default:
-      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, UNIMPL: optname=0x%x, ..)\n", s, optname));
-      err = ENOPROTOOPT;
-    }  /* switch */
-    break;
-
-/* UNDEFINED LEVEL */      
-  default:
-    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, level=0x%x, UNIMPL: optname=0x%x, ..)\n", s, level, optname));
-    err = ENOPROTOOPT;
-  }  /* switch */
-
-
-  if( 0 != err ) {
-    sock_set_errno(sock, err);
-    return -1;
-  }
-
-
-
-  /* Now do the actual option processing */
-
-  switch(level) {
-
-/* Level: SOL_SOCKET */
-  case SOL_SOCKET:
-    switch(optname) {
-
-    /* The option flags */
-    case SO_BROADCAST:
-    /* UNIMPL case SO_DEBUG: */
-    /* UNIMPL case SO_DONTROUTE: */
-    case SO_KEEPALIVE:
-    /* UNIMPL case SO_OOBINCLUDE: */
-#if SO_REUSE
-    case SO_REUSEADDR:
-    case SO_REUSEPORT:
-#endif /* SO_REUSE */
-    /* UNIMPL case SO_USELOOPBACK: */
-      if ( *(int*)optval ) {
-        sock->conn->pcb.tcp->so_options |= optname;
-      } else {
-        sock->conn->pcb.tcp->so_options &= ~optname;
-      }
-      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, SOL_SOCKET, optname=0x%x, ..) -> %s\n", s, optname, (*(int*)optval?"on":"off")));
-      break;
-    }  /* switch */
-    break;
-
-/* Level: IPPROTO_IP */
-  case IPPROTO_IP:
-    switch( optname ) {
-    case IP_TTL:
-      sock->conn->pcb.tcp->ttl = (u8_t)(*(int*)optval);
-      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, IP_TTL, ..) -> %u\n", s, sock->conn->pcb.tcp->ttl));
-      break;
-    case IP_TOS:
-      sock->conn->pcb.tcp->tos = (u8_t)(*(int*)optval);
-      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, IP_TOS, ..)-> %u\n", s, sock->conn->pcb.tcp->tos));
-      break;
-    }  /* switch */
-    break;
-
-/* Level: IPPROTO_TCP */
-  case IPPROTO_TCP:
-    switch( optname ) {
-    case TCP_NODELAY:
-      if ( *(int*)optval ) {
-        sock->conn->pcb.tcp->flags |= TF_NODELAY;
-      } else {
-        sock->conn->pcb.tcp->flags &= ~TF_NODELAY;
-      }
-      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_NODELAY) -> %s\n", s, (*(int *)optval)?"on":"off") );
-      break;
-    case TCP_KEEPALIVE:
-      sock->conn->pcb.tcp->keepalive = (u32_t)(*(int*)optval);
-      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPALIVE) -> %lu\n", s, sock->conn->pcb.tcp->keepalive));
-      break;
-    }  /* switch */
-    break;
-  }  /* switch */
-
-  sock_set_errno(sock, err);
-  return err ? -1 : 0;
-}
-
-int lwip_ioctl(int s, long cmd, void *argp)
-{
-  struct lwip_socket *sock = get_socket(s);
-
-  if(!sock) {
-   	set_errno(EBADF);
-    return -1;
-  }
-
-  switch (cmd) {
-  case FIONREAD:
-    if (!argp) {
-      sock_set_errno(sock, EINVAL);
-      return -1;
-    }
-
-    *((u16_t*)argp) = sock->conn->recv_avail;
-
-    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, FIONREAD, %p) = %u\n", s, argp, *((u16_t*)argp)));
-    sock_set_errno(sock, 0);
-    return 0;
-
-  case FIONBIO:
-    if (argp && *(u32_t*)argp)
-      sock->flags |= O_NONBLOCK;
-    else
-      sock->flags &= ~O_NONBLOCK;
-    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, FIONBIO, %d)\n", s, !!(sock->flags & O_NONBLOCK)));
-    sock_set_errno(sock, 0);
-    return 0;
-
-  default:
-    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, UNIMPL: 0x%lx, %p)\n", s, cmd, argp));
-    sock_set_errno(sock, ENOSYS); /* not yet implemented */
-    return -1;
-  }
-}
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/api/tcpip.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/api/tcpip.c
deleted file mode 100644
index b9e11f8e7..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/api/tcpip.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-
-#include "lwip/opt.h"
-
-#include "lwip/sys.h"
-
-#include "lwip/memp.h"
-#include "lwip/pbuf.h"
-
-#include "lwip/ip.h"
-#include "lwip/udp.h"
-#include "lwip/tcp.h"
-
-#include "lwip/tcpip.h"
-
-static void (* tcpip_init_done)(void *arg) = NULL;
-static void *tcpip_init_done_arg;
-static sys_mbox_t mbox;
-
-#if LWIP_TCP
-static int tcpip_tcp_timer_active = 0;
-
-static void
-tcpip_tcp_timer(void *arg)
-{
-  (void)arg;
-
-  /* call TCP timer handler */
-  tcp_tmr();
-  /* timer still needed? */
-  if (tcp_active_pcbs || tcp_tw_pcbs) {
-    /* restart timer */
-    sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL);
-  } else {
-    /* disable timer */
-    tcpip_tcp_timer_active = 0;
-  }
-}
-
-#if !NO_SYS
-void
-tcp_timer_needed(void)
-{
-  /* timer is off but needed again? */
-  if (!tcpip_tcp_timer_active && (tcp_active_pcbs || tcp_tw_pcbs)) {
-    /* enable and start timer */
-    tcpip_tcp_timer_active = 1;
-    sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL);
-  }
-}
-#endif /* !NO_SYS */
-#endif /* LWIP_TCP */
-
-static void
-tcpip_thread(void *arg)
-{
-  struct tcpip_msg *msg;
-
-  (void)arg;
-
-  ip_init();
-#if LWIP_UDP  
-  udp_init();
-#endif
-#if LWIP_TCP
-  tcp_init();
-#endif
-  if (tcpip_init_done != NULL) {
-    tcpip_init_done(tcpip_init_done_arg);
-  }
-
-  while (1) {                          /* MAIN Loop */
-    sys_mbox_fetch(mbox, (void *)&msg);
-    switch (msg->type) {
-    case TCPIP_MSG_API:
-      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: API message %p\n", (void *)msg));
-      api_msg_input(msg->msg.apimsg);
-      break;
-    case TCPIP_MSG_INPUT:
-      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: IP packet %p\n", (void *)msg));
-      ip_input(msg->msg.inp.p, msg->msg.inp.netif);
-      break;
-    case TCPIP_MSG_CALLBACK:
-      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: CALLBACK %p\n", (void *)msg));
-      msg->msg.cb.f(msg->msg.cb.ctx);
-      break;
-    default:
-      break;
-    }
-    memp_free(MEMP_TCPIP_MSG, msg);
-  }
-}
-
-err_t
-tcpip_input(struct pbuf *p, struct netif *inp)
-{
-  struct tcpip_msg *msg;
-  
-  msg = memp_malloc(MEMP_TCPIP_MSG);
-  if (msg == NULL) {
-    pbuf_free(p);    
-    return ERR_MEM;  
-  }
-  
-  msg->type = TCPIP_MSG_INPUT;
-  msg->msg.inp.p = p;
-  msg->msg.inp.netif = inp;
-  sys_mbox_post(mbox, msg);
-  return ERR_OK;
-}
-
-err_t
-tcpip_callback(void (*f)(void *ctx), void *ctx)
-{
-  struct tcpip_msg *msg;
-  
-  msg = memp_malloc(MEMP_TCPIP_MSG);
-  if (msg == NULL) {
-    return ERR_MEM;  
-  }
-  
-  msg->type = TCPIP_MSG_CALLBACK;
-  msg->msg.cb.f = f;
-  msg->msg.cb.ctx = ctx;
-  sys_mbox_post(mbox, msg);
-  return ERR_OK;
-}
-
-void
-tcpip_apimsg(struct api_msg *apimsg)
-{
-  struct tcpip_msg *msg;
-  msg = memp_malloc(MEMP_TCPIP_MSG);
-  if (msg == NULL) {
-    memp_free(MEMP_API_MSG, apimsg);
-    return;
-  }
-  msg->type = TCPIP_MSG_API;
-  msg->msg.apimsg = apimsg;
-  sys_mbox_post(mbox, msg);
-}
-
-void
-tcpip_init(void (* initfunc)(void *), void *arg)
-{
-  tcpip_init_done = initfunc;
-  tcpip_init_done_arg = arg;
-  mbox = sys_mbox_new();
-  sys_thread_new(tcpip_thread, NULL, TCPIP_THREAD_PRIO);
-}
-
-
-
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/dhcp.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/dhcp.c
deleted file mode 100644
index 2a9c1887d..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/dhcp.c
+++ /dev/null
@@ -1,1454 +0,0 @@
-/**
- * @file
- *
- * Dynamic Host Configuration Protocol client
- */
-
-/*
- *
- * Copyright (c) 2001-2004 Leon Woestenberg 
- * Copyright (c) 2001-2004 Axon Digital Design B.V., The Netherlands.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is a contribution to the lwIP TCP/IP stack.
- * The Swedish Institute of Computer Science and Adam Dunkels
- * are specifically granted permission to redistribute this
- * source code.
- *
- * Author: Leon Woestenberg 
- *
- * This is a DHCP client for the lwIP TCP/IP stack. It aims to conform
- * with RFC 2131 and RFC 2132.
- *
- * TODO:
- * - Proper parsing of DHCP messages exploiting file/sname field overloading.
- * - Add JavaDoc style documentation (API, internals).
- * - Support for interfaces other than Ethernet (SLIP, PPP, ...)
- *
- * Please coordinate changes and requests with Leon Woestenberg
- * 
- *
- * Integration with your code:
- *
- * In lwip/dhcp.h
- * #define DHCP_COARSE_TIMER_SECS (recommended 60 which is a minute)
- * #define DHCP_FINE_TIMER_MSECS (recommended 500 which equals TCP coarse timer)
- *
- * Then have your application call dhcp_coarse_tmr() and
- * dhcp_fine_tmr() on the defined intervals.
- *
- * dhcp_start(struct netif *netif);
- * starts a DHCP client instance which configures the interface by
- * obtaining an IP address lease and maintaining it.
- *
- * Use dhcp_release(netif) to end the lease and use dhcp_stop(netif)
- * to remove the DHCP client.
- *
- */
- 
-#include 
- 
-#include "lwip/stats.h"
-#include "lwip/mem.h"
-#include "lwip/udp.h"
-#include "lwip/ip_addr.h"
-#include "lwip/netif.h"
-#include "lwip/inet.h"
-#include "netif/etharp.h"
-
-#include "lwip/sys.h"
-#include "lwip/opt.h"
-#include "lwip/dhcp.h"
-
-#if LWIP_DHCP /* don't build if not configured for use in lwipopt.h */
-
-/** global transaction identifier, must be
- *  unique for each DHCP request. We simply increment, starting
- *  with this value (easy to match with a packet analyzer) */
-static u32_t xid = 0xABCD0000;
-
-/** DHCP client state machine functions */
-static void dhcp_handle_ack(struct netif *netif);
-static void dhcp_handle_nak(struct netif *netif);
-static void dhcp_handle_offer(struct netif *netif);
-
-static err_t dhcp_discover(struct netif *netif);
-static err_t dhcp_select(struct netif *netif);
-static void dhcp_check(struct netif *netif);
-static void dhcp_bind(struct netif *netif);
-static err_t dhcp_decline(struct netif *netif);
-static err_t dhcp_rebind(struct netif *netif);
-static void dhcp_set_state(struct dhcp *dhcp, unsigned char new_state);
-
-/** receive, unfold, parse and free incoming messages */
-static void dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port);
-static err_t dhcp_unfold_reply(struct dhcp *dhcp);
-static u8_t *dhcp_get_option_ptr(struct dhcp *dhcp, u8_t option_type);
-static u8_t dhcp_get_option_byte(u8_t *ptr);
-static u16_t dhcp_get_option_short(u8_t *ptr);
-static u32_t dhcp_get_option_long(u8_t *ptr);
-static void dhcp_free_reply(struct dhcp *dhcp);
-
-/** set the DHCP timers */
-static void dhcp_timeout(struct netif *netif);
-static void dhcp_t1_timeout(struct netif *netif);
-static void dhcp_t2_timeout(struct netif *netif);
-
-/** build outgoing messages */
-/** create a DHCP request, fill in common headers */
-static err_t dhcp_create_request(struct netif *netif);
-/** free a DHCP request */
-static void dhcp_delete_request(struct netif *netif);
-/** add a DHCP option (type, then length in bytes) */
-static void dhcp_option(struct dhcp *dhcp, u8_t option_type, u8_t option_len);
-/** add option values */
-static void dhcp_option_byte(struct dhcp *dhcp, u8_t value);
-static void dhcp_option_short(struct dhcp *dhcp, u16_t value);
-static void dhcp_option_long(struct dhcp *dhcp, u32_t value);
-/** always add the DHCP options trailer to end and pad */
-static void dhcp_option_trailer(struct dhcp *dhcp);
-
-/**
- * Back-off the DHCP client (because of a received NAK response).
- *
- * Back-off the DHCP client because of a received NAK. Receiving a
- * NAK means the client asked for something non-sensible, for
- * example when it tries to renew a lease obtained on another network.
- *
- * We back-off and will end up restarting a fresh DHCP negotiation later.
- *
- * @param state pointer to DHCP state structure
- */
-static void dhcp_handle_nak(struct netif *netif) {
-  struct dhcp *dhcp = netif->dhcp;
-  u16_t msecs = 10 * 1000;
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_handle_nak(netif=%p) %c%c%u\n", netif,
-    netif->name[0], netif->name[1], (unsigned int)netif->num));
-  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_handle_nak(): set request timeout %u msecs\n", msecs));
-  dhcp_set_state(dhcp, DHCP_BACKING_OFF);
-}
-
-/**
- * Checks if the offered IP address is already in use.
- *
- * It does so by sending an ARP request for the offered address and
- * entering CHECKING state. If no ARP reply is received within a small
- * interval, the address is assumed to be free for use by us.
- */
-static void dhcp_check(struct netif *netif)
-{
-  struct dhcp *dhcp = netif->dhcp;
-  err_t result;
-  u16_t msecs;
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_check(netif=%p) %c%c\n", (void *)netif, (unsigned int)netif->name[0],
-    (unsigned int)netif->name[1]));
-  /* create an ARP query for the offered IP address, expecting that no host
-     responds, as the IP address should not be in use. */
-  result = etharp_query(netif, &dhcp->offered_ip_addr, NULL);
-  if (result != ERR_OK) {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_check: could not perform ARP query\n"));
-  }
-  dhcp->tries++;
-  msecs = 500;
-  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_check(): set request timeout %u msecs\n", msecs));
-  dhcp_set_state(dhcp, DHCP_CHECKING);
-}
-
-/**
- * Remember the configuration offered by a DHCP server.
- *
- * @param state pointer to DHCP state structure
- */
-static void dhcp_handle_offer(struct netif *netif)
-{
-  struct dhcp *dhcp = netif->dhcp;
-  /* obtain the server address */
-  u8_t *option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_SERVER_ID);
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_handle_offer(netif=%p) %c%c%u\n", netif,
-    netif->name[0], netif->name[1], netif->num));
-  if (option_ptr != NULL)
-  {
-    dhcp->server_ip_addr.addr = htonl(dhcp_get_option_long(&option_ptr[2]));
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_handle_offer(): server 0x%08lx\n", dhcp->server_ip_addr.addr));
-    /* remember offered address */
-    ip_addr_set(&dhcp->offered_ip_addr, (struct ip_addr *)&dhcp->msg_in->yiaddr);
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_handle_offer(): offer for 0x%08lx\n", dhcp->offered_ip_addr.addr));
-
-    dhcp_select(netif);
-  }
-}
-
-/**
- * Select a DHCP server offer out of all offers.
- *
- * Simply select the first offer received.
- *
- * @param netif the netif under DHCP control
- * @return lwIP specific error (see error.h)
- */
-static err_t dhcp_select(struct netif *netif)
-{
-  struct dhcp *dhcp = netif->dhcp;
-  err_t result;
-  u32_t msecs;
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_select(netif=%p) %c%c%u\n", netif, netif->name[0], netif->name[1], netif->num));
-
-  /* create and initialize the DHCP message header */
-  result = dhcp_create_request(netif);
-  if (result == ERR_OK)
-  {
-    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
-    dhcp_option_byte(dhcp, DHCP_REQUEST);
-
-    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
-    dhcp_option_short(dhcp, 576);
-
-    /* MUST request the offered IP address */
-    dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4);
-    dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr));
-
-    dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4);
-    dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr));
-
-    dhcp_option(dhcp, DHCP_OPTION_PARAMETER_REQUEST_LIST, 4/*num options*/);
-    dhcp_option_byte(dhcp, DHCP_OPTION_SUBNET_MASK);
-    dhcp_option_byte(dhcp, DHCP_OPTION_ROUTER);
-    dhcp_option_byte(dhcp, DHCP_OPTION_BROADCAST);
-    dhcp_option_byte(dhcp, DHCP_OPTION_DNS_SERVER);
-
-    dhcp_option_trailer(dhcp);
-    /* shrink the pbuf to the actual content length */
-    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
-
-    /* TODO: we really should bind to a specific local interface here
-       but we cannot specify an unconfigured netif as it is addressless */
-    udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
-    /* send broadcast to any DHCP server */
-    udp_connect(dhcp->pcb, IP_ADDR_BROADCAST, DHCP_SERVER_PORT);
-    udp_send(dhcp->pcb, dhcp->p_out);
-    /* reconnect to any (or to server here?!) */
-    udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
-    dhcp_delete_request(netif);
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_select: REQUESTING\n"));
-    dhcp_set_state(dhcp, DHCP_REQUESTING);
-  } else {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_select: could not allocate DHCP request\n"));
-  }
-  dhcp->tries++;
-  msecs = dhcp->tries < 4 ? dhcp->tries * 1000 : 4 * 1000;
-  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_select(): set request timeout %u msecs\n", msecs));
-  return result;
-}
-
-/**
- * The DHCP timer that checks for lease renewal/rebind timeouts.
- *
- */
-void dhcp_coarse_tmr()
-{
-  struct netif *netif = netif_list;
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_coarse_tmr()\n"));
-  /* iterate through all network interfaces */
-  while (netif != NULL) {
-    /* only act on DHCP configured interfaces */
-    if (netif->dhcp != NULL) {
-      /* timer is active (non zero), and triggers (zeroes) now? */
-      if (netif->dhcp->t2_timeout-- == 1) {
-        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_coarse_tmr(): t2 timeout\n"));
-        /* this clients' rebind timeout triggered */
-        dhcp_t2_timeout(netif);
-      /* timer is active (non zero), and triggers (zeroes) now */
-      } else if (netif->dhcp->t1_timeout-- == 1) {
-        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_coarse_tmr(): t1 timeout\n"));
-        /* this clients' renewal timeout triggered */
-        dhcp_t1_timeout(netif);
-      }
-    }
-    /* proceed to next netif */
-    netif = netif->next;
-  }
-}
-
-/**
- * DHCP transaction timeout handling
- *
- * A DHCP server is expected to respond within a short period of time.
- * This timer checks whether an outstanding DHCP request is timed out.
- * 
- */
-void dhcp_fine_tmr()
-{
-  struct netif *netif = netif_list;
-  /* loop through netif's */
-  while (netif != NULL) {
-    /* only act on DHCP configured interfaces */
-    if (netif->dhcp != NULL) {
-      /* timer is active (non zero), and is about to trigger now */
-      if (netif->dhcp->request_timeout-- == 1) {
-        /* { netif->dhcp->request_timeout == 0 } */
-        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_fine_tmr(): request timeout\n"));
-        /* this clients' request timeout triggered */
-        dhcp_timeout(netif);
-      }
-    }
-    /* proceed to next network interface */
-    netif = netif->next;
-  }
-}
-
-/**
- * A DHCP negotiation transaction, or ARP request, has timed out.
- *
- * The timer that was started with the DHCP or ARP request has
- * timed out, indicating no response was received in time.
- *
- * @param netif the netif under DHCP control
- *
- */
-static void dhcp_timeout(struct netif *netif)
-{
-  struct dhcp *dhcp = netif->dhcp;
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_timeout()\n"));
-  /* back-off period has passed, or server selection timed out */
-  if ((dhcp->state == DHCP_BACKING_OFF) || (dhcp->state == DHCP_SELECTING)) {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_timeout(): restarting discovery\n"));
-    dhcp_discover(netif);
-  /* receiving the requested lease timed out */
-  } else if (dhcp->state == DHCP_REQUESTING) {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): REQUESTING, DHCP request timed out\n"));
-    if (dhcp->tries <= 5) {
-      dhcp_select(netif);
-    } else {
-      LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): REQUESTING, releasing, restarting\n"));
-      dhcp_release(netif);
-      dhcp_discover(netif);
-    }
-  /* received no ARP reply for the offered address (which is good) */
-  } else if (dhcp->state == DHCP_CHECKING) {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): CHECKING, ARP request timed out\n"));
-    if (dhcp->tries <= 1) {
-      dhcp_check(netif);
-    /* no ARP replies on the offered address,
-       looks like the IP address is indeed free */
-    } else {
-      /* bind the interface to the offered address */
-      dhcp_bind(netif);
-    }
-  }
-  /* did not get response to renew request? */
-  else if (dhcp->state == DHCP_RENEWING) {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): RENEWING, DHCP request timed out\n"));
-    /* just retry renewal */
-    /* note that the rebind timer will eventually time-out if renew does not work */
-    dhcp_renew(netif);
-  /* did not get response to rebind request? */
-  } else if (dhcp->state == DHCP_REBINDING) {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): REBINDING, DHCP request timed out\n"));
-    if (dhcp->tries <= 8) {
-      dhcp_rebind(netif);
-    } else {
-      LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): RELEASING, DISCOVERING\n"));
-      dhcp_release(netif);
-      dhcp_discover(netif);
-    }
-  }
-}
-
-/**
- * The renewal period has timed out.
- *
- * @param netif the netif under DHCP control
- */
-static void dhcp_t1_timeout(struct netif *netif)
-{
-  struct dhcp *dhcp = netif->dhcp;
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_t1_timeout()\n"));
-  if ((dhcp->state == DHCP_REQUESTING) || (dhcp->state == DHCP_BOUND) || (dhcp->state == DHCP_RENEWING)) {
-    /* just retry to renew - note that the rebind timer (t2) will
-     * eventually time-out if renew tries fail. */
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_t1_timeout(): must renew\n"));
-    dhcp_renew(netif);
-  }
-}
-
-/**
- * The rebind period has timed out.
- *
- */
-static void dhcp_t2_timeout(struct netif *netif)
-{
-  struct dhcp *dhcp = netif->dhcp;
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_t2_timeout()\n"));
-  if ((dhcp->state == DHCP_REQUESTING) || (dhcp->state == DHCP_BOUND) || (dhcp->state == DHCP_RENEWING)) {
-    /* just retry to rebind */
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_t2_timeout(): must rebind\n"));
-    dhcp_rebind(netif);
-  }
-}
-
-/**
- *
- * @param netif the netif under DHCP control
- */
-static void dhcp_handle_ack(struct netif *netif)
-{
-  struct dhcp *dhcp = netif->dhcp;
-  u8_t *option_ptr;
-  /* clear options we might not get from the ACK */
-  dhcp->offered_sn_mask.addr = 0;
-  dhcp->offered_gw_addr.addr = 0;
-  dhcp->offered_bc_addr.addr = 0;
-
-  /* lease time given? */
-  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_LEASE_TIME);
-  if (option_ptr != NULL) {
-    /* remember offered lease time */
-    dhcp->offered_t0_lease = dhcp_get_option_long(option_ptr + 2);
-  }
-  /* renewal period given? */
-  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_T1);
-  if (option_ptr != NULL) {
-    /* remember given renewal period */
-    dhcp->offered_t1_renew = dhcp_get_option_long(option_ptr + 2);
-  } else {
-    /* calculate safe periods for renewal */
-    dhcp->offered_t1_renew = dhcp->offered_t0_lease / 2;
-  }
-
-  /* renewal period given? */
-  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_T2);
-  if (option_ptr != NULL) {
-    /* remember given rebind period */
-    dhcp->offered_t2_rebind = dhcp_get_option_long(option_ptr + 2);
-  } else {
-    /* calculate safe periods for rebinding */
-    dhcp->offered_t2_rebind = dhcp->offered_t0_lease;
-  }
-
-  /* (y)our internet address */
-  ip_addr_set(&dhcp->offered_ip_addr, &dhcp->msg_in->yiaddr);
-
-/**
- * Patch #1308
- * TODO: we must check if the file field is not overloaded by DHCP options!
- */
-#if 0
-  /* boot server address */
-  ip_addr_set(&dhcp->offered_si_addr, &dhcp->msg_in->siaddr);
-  /* boot file name */
-  if (dhcp->msg_in->file[0]) {
-    dhcp->boot_file_name = mem_malloc(strlen(dhcp->msg_in->file) + 1);
-    strcpy(dhcp->boot_file_name, dhcp->msg_in->file);
-  }
-#endif
-
-  /* subnet mask */
-  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_SUBNET_MASK);
-  /* subnet mask given? */
-  if (option_ptr != NULL) {
-    dhcp->offered_sn_mask.addr = htonl(dhcp_get_option_long(&option_ptr[2]));
-  }
-
-  /* gateway router */
-  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_ROUTER);
-  if (option_ptr != NULL) {
-    dhcp->offered_gw_addr.addr = htonl(dhcp_get_option_long(&option_ptr[2]));
-  }
-
-  /* broadcast address */
-  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_BROADCAST);
-  if (option_ptr != NULL) {
-    dhcp->offered_bc_addr.addr = htonl(dhcp_get_option_long(&option_ptr[2]));
-  }
-  
-  /* DNS servers */
-  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_DNS_SERVER);
-  if (option_ptr != NULL) {
-    u8_t n;
-    dhcp->dns_count = dhcp_get_option_byte(&option_ptr[1]);
-    /* limit to at most DHCP_MAX_DNS DNS servers */
-    if (dhcp->dns_count > DHCP_MAX_DNS) dhcp->dns_count = DHCP_MAX_DNS;
-    for (n = 0; n < dhcp->dns_count; n++)
-    {
-      dhcp->offered_dns_addr[n].addr = htonl(dhcp_get_option_long(&option_ptr[2+(n<<2)]));
-    }
-  }
-}
-
-/**
- * Start DHCP negotiation for a network interface.
- *
- * If no DHCP client instance was attached to this interface,
- * a new client is created first. If a DHCP client instance
- * was already present, it restarts negotiation.
- *
- * @param netif The lwIP network interface
- * @return lwIP error code
- * - ERR_OK - No error
- * - ERR_MEM - Out of memory
- *
- */
-err_t dhcp_start(struct netif *netif)
-{
-  struct dhcp *dhcp = netif->dhcp;
-  err_t result = ERR_OK;
-
-  LWIP_ASSERT("netif != NULL", netif != NULL);
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_start(netif=%p) %c%c%u\n", netif, netif->name[0], netif->name[1], netif->num));
-  netif->flags &= ~NETIF_FLAG_DHCP;
-
-  /* no DHCP client attached yet? */
-  if (dhcp == NULL) {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): starting new DHCP client\n"));
-    dhcp = mem_malloc(sizeof(struct dhcp));
-    if (dhcp == NULL) {
-      LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): could not allocate dhcp\n"));
-      return ERR_MEM;
-    }
-    /* store this dhcp client in the netif */
-    netif->dhcp = dhcp;
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): allocated dhcp"));
-  /* already has DHCP client attached */
-  } else {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE | 3, ("dhcp_start(): restarting DHCP configuration\n"));
-  }
-  	
-	/* clear data structure */
-	memset(dhcp, 0, sizeof(struct dhcp));
-  /* allocate UDP PCB */
-	dhcp->pcb = udp_new();
-	if (dhcp->pcb == NULL) {
-	  LWIP_DEBUGF(DHCP_DEBUG  | DBG_TRACE, ("dhcp_start(): could not obtain pcb\n"));
-	  mem_free((void *)dhcp);
-	  netif->dhcp = dhcp = NULL;
-	  return ERR_MEM;
-	}
-	LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): starting DHCP configuration\n"));
-  /* (re)start the DHCP negotiation */
-  result = dhcp_discover(netif);
-  if (result != ERR_OK) {
-    /* free resources allocated above */
-    dhcp_stop(netif);
-    return ERR_MEM;
-  }
-  netif->flags |= NETIF_FLAG_DHCP;
-  return result;
-}
-
-/**
- * Inform a DHCP server of our manual configuration.
- *
- * This informs DHCP servers of our fixed IP address configuration
- * by sending an INFORM message. It does not involve DHCP address
- * configuration, it is just here to be nice to the network.
- *
- * @param netif The lwIP network interface
- *
- */
-void dhcp_inform(struct netif *netif)
-{
-  struct dhcp *dhcp;
-  err_t result = ERR_OK;
-  dhcp = mem_malloc(sizeof(struct dhcp));
-  if (dhcp == NULL) {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_inform(): could not allocate dhcp\n"));
-    return;
-  }
-  netif->dhcp = dhcp;
-  memset(dhcp, 0, sizeof(struct dhcp));
-
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_inform(): allocated dhcp\n"));
-  dhcp->pcb = udp_new();
-  if (dhcp->pcb == NULL) {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_inform(): could not obtain pcb"));
-    mem_free((void *)dhcp);
-    return;
-  }
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_inform(): created new udp pcb\n"));
-  /* create and initialize the DHCP message header */
-  result = dhcp_create_request(netif);
-  if (result == ERR_OK) {
-
-    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
-    dhcp_option_byte(dhcp, DHCP_INFORM);
-
-    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
-    /* TODO: use netif->mtu ?! */
-    dhcp_option_short(dhcp, 576);
-
-    dhcp_option_trailer(dhcp);
-
-    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
-
-    udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
-    udp_connect(dhcp->pcb, IP_ADDR_BROADCAST, DHCP_SERVER_PORT);
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_inform: INFORMING\n"));
-    udp_send(dhcp->pcb, dhcp->p_out);
-    udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
-    dhcp_delete_request(netif);
-  } else {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_inform: could not allocate DHCP request\n"));
-  }
-
-  if (dhcp != NULL)
-  {
-    if (dhcp->pcb != NULL) udp_remove(dhcp->pcb);
-    dhcp->pcb = NULL;
-    mem_free((void *)dhcp);
-    netif->dhcp = NULL;
-  }
-}
-
-#if DHCP_DOES_ARP_CHECK
-/**
- * Match an ARP reply with the offered IP address.
- *
- * @param addr The IP address we received a reply from
- *
- */
-void dhcp_arp_reply(struct netif *netif, struct ip_addr *addr)
-{
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_arp_reply()\n"));
-  /* is this DHCP client doing an ARP check? */
-  if ((netif->dhcp != NULL) && (netif->dhcp->state == DHCP_CHECKING)) {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_arp_reply(): CHECKING, arp reply for 0x%08lx\n", addr->addr));
-    /* did a host respond with the address we
-       were offered by the DHCP server? */
-    if (ip_addr_cmp(addr, &netif->dhcp->offered_ip_addr)) {
-      /* we will not accept the offered address */
-      LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE | 1, ("dhcp_arp_reply(): arp reply matched with offered address, declining\n"));
-      dhcp_decline(netif);
-    }
-  }
-}
-
-/**
- * Decline an offered lease.
- *
- * Tell the DHCP server we do not accept the offered address.
- * One reason to decline the lease is when we find out the address
- * is already in use by another host (through ARP).
- */
-static err_t dhcp_decline(struct netif *netif)
-{
-  struct dhcp *dhcp = netif->dhcp;
-  err_t result = ERR_OK;
-  u16_t msecs;
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_decline()\n"));
-  dhcp_set_state(dhcp, DHCP_BACKING_OFF);
-  /* create and initialize the DHCP message header */
-  result = dhcp_create_request(netif);
-  if (result == ERR_OK)
-  {
-    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
-    dhcp_option_byte(dhcp, DHCP_DECLINE);
-
-    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
-    dhcp_option_short(dhcp, 576);
-
-    dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4);
-    dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr));
-
-    dhcp_option_trailer(dhcp);
-    /* resize pbuf to reflect true size of options */
-    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
-
-    udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
-    /* @todo: should we really connect here? we are performing sendto() */
-    udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
-    /* per section 4.4.4, broadcast DECLINE messages */
-    udp_sendto(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT);
-    dhcp_delete_request(netif);
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_decline: BACKING OFF\n"));
-  } else {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_decline: could not allocate DHCP request\n"));
-  }
-  dhcp->tries++;
-  msecs = 10*1000;
-  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
-   LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_decline(): set request timeout %u msecs\n", msecs));
-  return result;
-}
-#endif
-
-
-/**
- * Start the DHCP process, discover a DHCP server.
- *
- */
-static err_t dhcp_discover(struct netif *netif)
-{
-  struct dhcp *dhcp = netif->dhcp;
-  err_t result = ERR_OK;
-  u16_t msecs;
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_discover()\n"));
-  ip_addr_set(&dhcp->offered_ip_addr, IP_ADDR_ANY);
-  /* create and initialize the DHCP message header */
-  result = dhcp_create_request(netif);
-  if (result == ERR_OK)
-  {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_discover: making request\n"));
-    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
-    dhcp_option_byte(dhcp, DHCP_DISCOVER);
-
-    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
-    dhcp_option_short(dhcp, 576);
-
-    dhcp_option(dhcp, DHCP_OPTION_PARAMETER_REQUEST_LIST, 4/*num options*/);
-    dhcp_option_byte(dhcp, DHCP_OPTION_SUBNET_MASK);
-    dhcp_option_byte(dhcp, DHCP_OPTION_ROUTER);
-    dhcp_option_byte(dhcp, DHCP_OPTION_BROADCAST);
-    dhcp_option_byte(dhcp, DHCP_OPTION_DNS_SERVER);
-
-    dhcp_option_trailer(dhcp);
-
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_discover: realloc()ing\n"));
-    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
-
-    /* set receive callback function with netif as user data */
-    udp_recv(dhcp->pcb, dhcp_recv, netif);
-    udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
-    udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_discover: sendto(DISCOVER, IP_ADDR_BROADCAST, DHCP_SERVER_PORT)\n"));
-    udp_sendto(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT);
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_discover: deleting()ing\n"));
-    dhcp_delete_request(netif);
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_discover: SELECTING\n"));
-    dhcp_set_state(dhcp, DHCP_SELECTING);
-  } else {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_discover: could not allocate DHCP request\n"));
-  }
-  dhcp->tries++;
-  msecs = dhcp->tries < 4 ? (dhcp->tries + 1) * 1000 : 10 * 1000;
-  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_discover(): set request timeout %u msecs\n", msecs));
-  return result;
-}
-
-
-/**
- * Bind the interface to the offered IP address.
- *
- * @param netif network interface to bind to the offered address
- */
-static void dhcp_bind(struct netif *netif)
-{
-  struct dhcp *dhcp = netif->dhcp;
-  struct ip_addr sn_mask, gw_addr;
-  LWIP_ASSERT("dhcp_bind: netif != NULL", netif != NULL);
-  LWIP_ASSERT("dhcp_bind: dhcp != NULL", dhcp != NULL);
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_bind(netif=%p) %c%c%u\n", netif, netif->name[0], netif->name[1], netif->num));
-
-  /* temporary DHCP lease? */
-  if (dhcp->offered_t1_renew != 0xffffffffUL) {
-    /* set renewal period timer */
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_bind(): t1 renewal timer %lu secs\n", dhcp->offered_t1_renew));
-    dhcp->t1_timeout = (dhcp->offered_t1_renew + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS;
-    if (dhcp->t1_timeout == 0) dhcp->t1_timeout = 1;
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_bind(): set request timeout %u msecs\n", dhcp->offered_t1_renew*1000));
-  }
-  /* set renewal period timer */
-  if (dhcp->offered_t2_rebind != 0xffffffffUL) {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_bind(): t2 rebind timer %lu secs\n", dhcp->offered_t2_rebind));
-    dhcp->t2_timeout = (dhcp->offered_t2_rebind + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS;
-    if (dhcp->t2_timeout == 0) dhcp->t2_timeout = 1;
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_bind(): set request timeout %u msecs\n", dhcp->offered_t2_rebind*1000));
-  }
-  /* copy offered network mask */
-  ip_addr_set(&sn_mask, &dhcp->offered_sn_mask);
-
-  /* subnet mask not given? */
-  /* TODO: this is not a valid check. what if the network mask is 0? */
-  if (sn_mask.addr == 0) {
-    /* choose a safe subnet mask given the network class */
-    u8_t first_octet = ip4_addr1(&sn_mask);
-    if (first_octet <= 127) sn_mask.addr = htonl(0xff000000);
-    else if (first_octet >= 192) sn_mask.addr = htonl(0xffffff00);
-    else sn_mask.addr = htonl(0xffff0000);
-  }
-
-  ip_addr_set(&gw_addr, &dhcp->offered_gw_addr);
-  /* gateway address not given? */
-  if (gw_addr.addr == 0) {
-    /* copy network address */
-    gw_addr.addr = (dhcp->offered_ip_addr.addr & sn_mask.addr);
-    /* use first host address on network as gateway */
-    gw_addr.addr |= htonl(0x00000001);
-  }
-
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_bind(): IP: 0x%08lx\n", dhcp->offered_ip_addr.addr));
-  netif_set_ipaddr(netif, &dhcp->offered_ip_addr);
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_bind(): SN: 0x%08lx\n", sn_mask.addr));
-  netif_set_netmask(netif, &sn_mask);
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_bind(): GW: 0x%08lx\n", gw_addr.addr));
-  netif_set_gw(netif, &gw_addr);
-  /* bring the interface up */
-  netif_set_up(netif);
-  /* netif is now bound to DHCP leased address */
-  dhcp_set_state(dhcp, DHCP_BOUND);
-}
-
-/**
- * Renew an existing DHCP lease at the involved DHCP server.
- *
- * @param netif network interface which must renew its lease
- */
-err_t dhcp_renew(struct netif *netif)
-{
-  struct dhcp *dhcp = netif->dhcp;
-  err_t result;
-  u16_t msecs;
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_renew()\n"));
-  dhcp_set_state(dhcp, DHCP_RENEWING);
-
-  /* create and initialize the DHCP message header */
-  result = dhcp_create_request(netif);
-  if (result == ERR_OK) {
-
-    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
-    dhcp_option_byte(dhcp, DHCP_REQUEST);
-
-    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
-    /* TODO: use netif->mtu in some way */
-    dhcp_option_short(dhcp, 576);
-
-#if 0
-    dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4);
-    dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr));
-#endif
-
-#if 0
-    dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4);
-    dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr));
-#endif
-    /* append DHCP message trailer */
-    dhcp_option_trailer(dhcp);
-
-    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
-
-    udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
-    udp_connect(dhcp->pcb, &dhcp->server_ip_addr, DHCP_SERVER_PORT);
-    udp_send(dhcp->pcb, dhcp->p_out);
-    dhcp_delete_request(netif);
-
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_renew: RENEWING\n"));
-  } else {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_renew: could not allocate DHCP request\n"));
-  }
-  dhcp->tries++;
-  /* back-off on retries, but to a maximum of 20 seconds */
-  msecs = dhcp->tries < 10 ? dhcp->tries * 2000 : 20 * 1000;
-  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
-   LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_renew(): set request timeout %u msecs\n", msecs));
-  return result;
-}
-
-/**
- * Rebind with a DHCP server for an existing DHCP lease.
- *
- * @param netif network interface which must rebind with a DHCP server
- */
-static err_t dhcp_rebind(struct netif *netif)
-{
-  struct dhcp *dhcp = netif->dhcp;
-  err_t result;
-  u16_t msecs;
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_rebind()\n"));
-  dhcp_set_state(dhcp, DHCP_REBINDING);
-
-  /* create and initialize the DHCP message header */
-  result = dhcp_create_request(netif);
-  if (result == ERR_OK)
-  {
-
-    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
-    dhcp_option_byte(dhcp, DHCP_REQUEST);
-
-    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
-    dhcp_option_short(dhcp, 576);
-
-#if 0
-    dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4);
-    dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr));
-
-    dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4);
-    dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr));
-#endif
-
-    dhcp_option_trailer(dhcp);
-
-    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
-
-    /* set remote IP association to any DHCP server */
-    udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
-    udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
-    /* broadcast to server */
-    udp_sendto(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT);
-    dhcp_delete_request(netif);
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_rebind: REBINDING\n"));
-  } else {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_rebind: could not allocate DHCP request\n"));
-  }
-  dhcp->tries++;
-  msecs = dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000;
-  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
-   LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_rebind(): set request timeout %u msecs\n", msecs));
-  return result;
-}
-
-/**
- * Release a DHCP lease.
- *
- * @param netif network interface which must release its lease
- */
-err_t dhcp_release(struct netif *netif)
-{
-  struct dhcp *dhcp = netif->dhcp;
-  err_t result;
-  u16_t msecs;
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_release()\n"));
-
-  /* idle DHCP client */
-  dhcp_set_state(dhcp, DHCP_OFF);
-  /* clean old DHCP offer */
-  dhcp->server_ip_addr.addr = 0;
-  dhcp->offered_ip_addr.addr = dhcp->offered_sn_mask.addr = 0;
-  dhcp->offered_gw_addr.addr = dhcp->offered_bc_addr.addr = 0;
-  dhcp->offered_t0_lease = dhcp->offered_t1_renew = dhcp->offered_t2_rebind = 0;
-  dhcp->dns_count = 0;
-  
-  /* create and initialize the DHCP message header */
-  result = dhcp_create_request(netif);
-  if (result == ERR_OK) {
-    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
-    dhcp_option_byte(dhcp, DHCP_RELEASE);
-
-    dhcp_option_trailer(dhcp);
-
-    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
-
-    udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
-    udp_connect(dhcp->pcb, &dhcp->server_ip_addr, DHCP_SERVER_PORT);
-    udp_send(dhcp->pcb, dhcp->p_out);
-    dhcp_delete_request(netif);
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_release: RELEASED, DHCP_OFF\n"));
-  } else {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_release: could not allocate DHCP request\n"));
-  }
-  dhcp->tries++;
-  msecs = dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000;
-  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_release(): set request timeout %u msecs\n", msecs));
-  /* bring the interface down */
-  netif_set_down(netif);
-  /* remove IP address from interface */
-  netif_set_ipaddr(netif, IP_ADDR_ANY);
-  netif_set_gw(netif, IP_ADDR_ANY);
-  netif_set_netmask(netif, IP_ADDR_ANY);
-  
-  /* TODO: netif_down(netif); */
-  return result;
-}
-/**
- * Remove the DHCP client from the interface.
- *
- * @param netif The network interface to stop DHCP on
- */
-void dhcp_stop(struct netif *netif)
-{
-  struct dhcp *dhcp = netif->dhcp;
-  LWIP_ASSERT("dhcp_stop: netif != NULL", netif != NULL);
-
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_stop()\n"));
-  /* netif is DHCP configured? */
-  if (dhcp != NULL)
-  {
-    if (dhcp->pcb != NULL)
-    {
-      udp_remove(dhcp->pcb);
-      dhcp->pcb = NULL;
-    }
-    if (dhcp->p != NULL)
-    {
-      pbuf_free(dhcp->p);
-      dhcp->p = NULL;
-    }
-    /* free unfolded reply */
-    dhcp_free_reply(dhcp);
-    mem_free((void *)dhcp);
-    netif->dhcp = NULL;
-  }
-}
-
-/*
- * Set the DHCP state of a DHCP client.
- *
- * If the state changed, reset the number of tries.
- *
- * TODO: we might also want to reset the timeout here?
- */
-static void dhcp_set_state(struct dhcp *dhcp, unsigned char new_state)
-{
-  if (new_state != dhcp->state)
-  {
-    dhcp->state = new_state;
-    dhcp->tries = 0;
-  }
-}
-
-/*
- * Concatenate an option type and length field to the outgoing
- * DHCP message.
- *
- */
-static void dhcp_option(struct dhcp *dhcp, u8_t option_type, u8_t option_len)
-{
-  LWIP_ASSERT("dhcp_option_short: dhcp->options_out_len + 2 + option_len <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 2 + option_len <= DHCP_OPTIONS_LEN);
-  dhcp->msg_out->options[dhcp->options_out_len++] = option_type;
-  dhcp->msg_out->options[dhcp->options_out_len++] = option_len;
-}
-/*
- * Concatenate a single byte to the outgoing DHCP message.
- *
- */
-static void dhcp_option_byte(struct dhcp *dhcp, u8_t value)
-{
-  LWIP_ASSERT("dhcp_option_short: dhcp->options_out_len < DHCP_OPTIONS_LEN", dhcp->options_out_len < DHCP_OPTIONS_LEN);
-  dhcp->msg_out->options[dhcp->options_out_len++] = value;
-}
-static void dhcp_option_short(struct dhcp *dhcp, u16_t value)
-{
-  LWIP_ASSERT("dhcp_option_short: dhcp->options_out_len + 2 <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 2 <= DHCP_OPTIONS_LEN);
-  dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0xff00U) >> 8;
-  dhcp->msg_out->options[dhcp->options_out_len++] =  value & 0x00ffU;
-}
-static void dhcp_option_long(struct dhcp *dhcp, u32_t value)
-{
-  LWIP_ASSERT("dhcp_option_long: dhcp->options_out_len + 4 <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 4 <= DHCP_OPTIONS_LEN);
-  dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0xff000000UL) >> 24;
-  dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0x00ff0000UL) >> 16;
-  dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0x0000ff00UL) >> 8;
-  dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0x000000ffUL);
-}
-
-/**
- * Extract the DHCP message and the DHCP options.
- *
- * Extract the DHCP message and the DHCP options, each into a contiguous
- * piece of memory. As a DHCP message is variable sized by its options,
- * and also allows overriding some fields for options, the easy approach
- * is to first unfold the options into a conitguous piece of memory, and
- * use that further on.
- *
- */
-static err_t dhcp_unfold_reply(struct dhcp *dhcp)
-{
-  struct pbuf *p = dhcp->p;
-  u8_t *ptr;
-  u16_t i;
-  u16_t j = 0;
-  LWIP_ASSERT("dhcp->p != NULL", dhcp->p != NULL);
-  /* free any left-overs from previous unfolds */
-  dhcp_free_reply(dhcp);
-  /* options present? */
-  if (dhcp->p->tot_len > (sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN))
-  {
-    dhcp->options_in_len = dhcp->p->tot_len - (sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN);
-    dhcp->options_in = mem_malloc(dhcp->options_in_len);
-    if (dhcp->options_in == NULL)
-    {
-      LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_unfold_reply(): could not allocate dhcp->options\n"));
-      return ERR_MEM;
-    }
-  }
-  dhcp->msg_in = mem_malloc(sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN);
-  if (dhcp->msg_in == NULL)
-  {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_unfold_reply(): could not allocate dhcp->msg_in\n"));
-    mem_free((void *)dhcp->options_in);
-    dhcp->options_in = NULL;
-    return ERR_MEM;
-  }
-
-  ptr = (u8_t *)dhcp->msg_in;
-  /* proceed through struct dhcp_msg */
-  for (i = 0; i < sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN; i++)
-  {
-    *ptr++ = ((u8_t *)p->payload)[j++];
-    /* reached end of pbuf? */
-    if (j == p->len)
-    {
-      /* proceed to next pbuf in chain */
-      p = p->next;
-      j = 0;
-    }
-  }
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_unfold_reply(): copied %u bytes into dhcp->msg_in[]\n", i));
-  if (dhcp->options_in != NULL) {
-    ptr = (u8_t *)dhcp->options_in;
-    /* proceed through options */
-    for (i = 0; i < dhcp->options_in_len; i++) {
-      *ptr++ = ((u8_t *)p->payload)[j++];
-      /* reached end of pbuf? */
-      if (j == p->len) {
-        /* proceed to next pbuf in chain */
-        p = p->next;
-        j = 0;
-      }
-    }
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_unfold_reply(): copied %u bytes to dhcp->options_in[]\n", i));
-  }
-  return ERR_OK;
-}
-
-/**
- * Free the incoming DHCP message including contiguous copy of
- * its DHCP options.
- *
- */
-static void dhcp_free_reply(struct dhcp *dhcp)
-{
-  if (dhcp->msg_in != NULL) {
-    mem_free((void *)dhcp->msg_in);
-    dhcp->msg_in = NULL;
-  }
-  if (dhcp->options_in) {
-    mem_free((void *)dhcp->options_in);
-    dhcp->options_in = NULL;
-    dhcp->options_in_len = 0;
-  }
-  LWIP_DEBUGF(DHCP_DEBUG, ("dhcp_free_reply(): free'd\n"));
-}
-
-
-/**
- * If an incoming DHCP message is in response to us, then trigger the state machine
- */
-static void dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port)
-{
-  struct netif *netif = (struct netif *)arg;
-  struct dhcp *dhcp = netif->dhcp;
-  struct dhcp_msg *reply_msg = (struct dhcp_msg *)p->payload;
-  u8_t *options_ptr;
-  u8_t msg_type;
-  u8_t i;
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_recv(pbuf = %p) from DHCP server %u.%u.%u.%u port %u\n", p,
-    (unsigned int)(ntohl(addr->addr) >> 24 & 0xff), (unsigned int)(ntohl(addr->addr) >> 16 & 0xff),
-    (unsigned int)(ntohl(addr->addr) >>  8 & 0xff), (unsigned int)(ntohl(addr->addr) & 0xff), port));
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("pbuf->len = %u\n", p->len));
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("pbuf->tot_len = %u\n", p->tot_len));
-  /* prevent warnings about unused arguments */
-  (void)pcb; (void)addr; (void)port;
-  dhcp->p = p;
-  /* TODO: check packet length before reading them */
-  if (reply_msg->op != DHCP_BOOTREPLY) {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("not a DHCP reply message, but type %u\n", reply_msg->op));
-    pbuf_free(p);
-    dhcp->p = NULL;
-    return;
-  }
-  /* iterate through hardware address and match against DHCP message */
-  for (i = 0; i < netif->hwaddr_len; i++) {
-    if (netif->hwaddr[i] != reply_msg->chaddr[i]) {
-      LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("netif->hwaddr[%u]==%02x != reply_msg->chaddr[%u]==%02x\n",
-        i, netif->hwaddr[i], i, reply_msg->chaddr[i]));
-      pbuf_free(p);
-      dhcp->p = NULL;
-      return;
-    }
-  }
-  /* match transaction ID against what we expected */
-  if (ntohl(reply_msg->xid) != dhcp->xid) {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("transaction id mismatch\n"));
-    pbuf_free(p);
-    dhcp->p = NULL;
-    return;
-  }
-  /* option fields could be unfold? */
-  if (dhcp_unfold_reply(dhcp) != ERR_OK) {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("problem unfolding DHCP message - too short on memory?\n"));
-    pbuf_free(p);
-    dhcp->p = NULL;
-    return;
-  }
-
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("searching DHCP_OPTION_MESSAGE_TYPE\n"));
-  /* obtain pointer to DHCP message type */
-  options_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_MESSAGE_TYPE);
-  if (options_ptr == NULL) {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("DHCP_OPTION_MESSAGE_TYPE option not found\n"));
-    pbuf_free(p);
-    dhcp->p = NULL;
-    return;
-  }
-
-  /* read DHCP message type */
-  msg_type = dhcp_get_option_byte(options_ptr + 2);
-  /* message type is DHCP ACK? */
-  if (msg_type == DHCP_ACK) {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("DHCP_ACK received\n"));
-    /* in requesting state? */
-    if (dhcp->state == DHCP_REQUESTING) {
-      dhcp_handle_ack(netif);
-      dhcp->request_timeout = 0;
-#if DHCP_DOES_ARP_CHECK
-      /* check if the acknowledged lease address is already in use */
-      dhcp_check(netif);
-#else
-      /* bind interface to the acknowledged lease address */
-      dhcp_bind(netif);
-#endif
-    }
-    /* already bound to the given lease address? */
-    else if ((dhcp->state == DHCP_REBOOTING) || (dhcp->state == DHCP_REBINDING) || (dhcp->state == DHCP_RENEWING)) {
-      dhcp->request_timeout = 0;
-      dhcp_bind(netif);
-    }
-  }
-  /* received a DHCP_NAK in appropriate state? */
-  else if ((msg_type == DHCP_NAK) &&
-    ((dhcp->state == DHCP_REBOOTING) || (dhcp->state == DHCP_REQUESTING) ||
-     (dhcp->state == DHCP_REBINDING) || (dhcp->state == DHCP_RENEWING  ))) {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("DHCP_NAK received\n"));
-    dhcp->request_timeout = 0;
-    dhcp_handle_nak(netif);
-  }
-  /* received a DHCP_OFFER in DHCP_SELECTING state? */
-  else if ((msg_type == DHCP_OFFER) && (dhcp->state == DHCP_SELECTING)) {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("DHCP_OFFER received in DHCP_SELECTING state\n"));
-    dhcp->request_timeout = 0;
-    /* remember offered lease */
-    dhcp_handle_offer(netif);
-  }
-  pbuf_free(p);
-  dhcp->p = NULL;
-}
-
-
-static err_t dhcp_create_request(struct netif *netif)
-{
-  struct dhcp *dhcp = netif->dhcp;
-  u16_t i;
-  LWIP_ASSERT("dhcp_create_request: dhcp->p_out == NULL", dhcp->p_out == NULL);
-  LWIP_ASSERT("dhcp_create_request: dhcp->msg_out == NULL", dhcp->msg_out == NULL);
-  dhcp->p_out = pbuf_alloc(PBUF_TRANSPORT, sizeof(struct dhcp_msg), PBUF_RAM);
-  if (dhcp->p_out == NULL) {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_create_request(): could not allocate pbuf\n"));
-    return ERR_MEM;
-  }
-  /* give unique transaction identifier to this request */
-  dhcp->xid = xid++;
-
-  dhcp->msg_out = (struct dhcp_msg *)dhcp->p_out->payload;
-
-  dhcp->msg_out->op = DHCP_BOOTREQUEST;
-  /* TODO: make link layer independent */
-  dhcp->msg_out->htype = DHCP_HTYPE_ETH;
-  /* TODO: make link layer independent */
-  dhcp->msg_out->hlen = DHCP_HLEN_ETH;
-  dhcp->msg_out->hops = 0;
-  dhcp->msg_out->xid = htonl(dhcp->xid);
-  dhcp->msg_out->secs = 0;
-  dhcp->msg_out->flags = 0;
-  dhcp->msg_out->ciaddr.addr = netif->ip_addr.addr;
-  dhcp->msg_out->yiaddr.addr = 0;
-  dhcp->msg_out->siaddr.addr = 0;
-  dhcp->msg_out->giaddr.addr = 0;
-  for (i = 0; i < DHCP_CHADDR_LEN; i++) {
-    /* copy netif hardware address, pad with zeroes */
-    dhcp->msg_out->chaddr[i] = (i < netif->hwaddr_len) ? netif->hwaddr[i] : 0/* pad byte*/;
-  }
-  for (i = 0; i < DHCP_SNAME_LEN; i++) dhcp->msg_out->sname[i] = 0;
-  for (i = 0; i < DHCP_FILE_LEN; i++) dhcp->msg_out->file[i] = 0;
-  dhcp->msg_out->cookie = htonl(0x63825363UL);
-  dhcp->options_out_len = 0;
-  /* fill options field with an incrementing array (for debugging purposes) */
-  for (i = 0; i < DHCP_OPTIONS_LEN; i++) dhcp->msg_out->options[i] = i;
-  return ERR_OK;
-}
-
-static void dhcp_delete_request(struct netif *netif)
-{
-  struct dhcp *dhcp = netif->dhcp;
-  LWIP_ASSERT("dhcp_free_msg: dhcp->p_out != NULL", dhcp->p_out != NULL);
-  LWIP_ASSERT("dhcp_free_msg: dhcp->msg_out != NULL", dhcp->msg_out != NULL);
-  pbuf_free(dhcp->p_out);
-  dhcp->p_out = NULL;
-  dhcp->msg_out = NULL;
-}
-
-/**
- * Add a DHCP message trailer
- *
- * Adds the END option to the DHCP message, and if
- * necessary, up to three padding bytes.
- */
-
-static void dhcp_option_trailer(struct dhcp *dhcp)
-{
-  LWIP_ASSERT("dhcp_option_trailer: dhcp->msg_out != NULL\n", dhcp->msg_out != NULL);
-  LWIP_ASSERT("dhcp_option_trailer: dhcp->options_out_len < DHCP_OPTIONS_LEN\n", dhcp->options_out_len < DHCP_OPTIONS_LEN);
-  dhcp->msg_out->options[dhcp->options_out_len++] = DHCP_OPTION_END;
-  /* packet is too small, or not 4 byte aligned? */
-  while ((dhcp->options_out_len < DHCP_MIN_OPTIONS_LEN) || (dhcp->options_out_len & 3)) {
-    /* LWIP_DEBUGF(DHCP_DEBUG, ("dhcp_option_trailer: dhcp->options_out_len=%u, DHCP_OPTIONS_LEN=%u", dhcp->options_out_len, DHCP_OPTIONS_LEN)); */
-    LWIP_ASSERT("dhcp_option_trailer: dhcp->options_out_len < DHCP_OPTIONS_LEN\n", dhcp->options_out_len < DHCP_OPTIONS_LEN);
-    /* add a fill/padding byte */
-    dhcp->msg_out->options[dhcp->options_out_len++] = 0;
-  }
-}
-
-/**
- * Find the offset of a DHCP option inside the DHCP message.
- *
- * @param client DHCP client
- * @param option_type
- *
- * @return a byte offset into the UDP message where the option was found, or
- * zero if the given option was not found.
- */
-static u8_t *dhcp_get_option_ptr(struct dhcp *dhcp, u8_t option_type)
-{
-  u8_t overload = DHCP_OVERLOAD_NONE;
-
-  /* options available? */
-  if ((dhcp->options_in != NULL) && (dhcp->options_in_len > 0)) {
-    /* start with options field */
-    u8_t *options = (u8_t *)dhcp->options_in;
-    u16_t offset = 0;
-    /* at least 1 byte to read and no end marker, then at least 3 bytes to read? */
-    while ((offset < dhcp->options_in_len) && (options[offset] != DHCP_OPTION_END)) {
-      /* LWIP_DEBUGF(DHCP_DEBUG, ("msg_offset=%u, q->len=%u", msg_offset, q->len)); */
-      /* are the sname and/or file field overloaded with options? */
-      if (options[offset] == DHCP_OPTION_OVERLOAD) {
-        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("overloaded message detected\n"));
-        /* skip option type and length */
-        offset += 2;
-        overload = options[offset++];
-      }
-      /* requested option found */
-      else if (options[offset] == option_type) {
-        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("option found at offset %u in options\n", offset));
-        return &options[offset];
-      /* skip option */
-      } else {
-         LWIP_DEBUGF(DHCP_DEBUG, ("skipping option %u in options\n", options[offset]));
-        /* skip option type */
-        offset++;
-        /* skip option length, and then length bytes */
-        offset += 1 + options[offset];
-      }
-    }
-    /* is this an overloaded message? */
-    if (overload != DHCP_OVERLOAD_NONE) {
-      u16_t field_len;
-      if (overload == DHCP_OVERLOAD_FILE) {
-        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("overloaded file field\n"));
-        options = (u8_t *)&dhcp->msg_in->file;
-        field_len = DHCP_FILE_LEN;
-      } else if (overload == DHCP_OVERLOAD_SNAME) {
-        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("overloaded sname field\n"));
-        options = (u8_t *)&dhcp->msg_in->sname;
-        field_len = DHCP_SNAME_LEN;
-      /* TODO: check if else if () is necessary */
-      } else {
-        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("overloaded sname and file field\n"));
-        options = (u8_t *)&dhcp->msg_in->sname;
-        field_len = DHCP_FILE_LEN + DHCP_SNAME_LEN;
-      }
-      offset = 0;
-
-      /* at least 1 byte to read and no end marker */
-      while ((offset < field_len) && (options[offset] != DHCP_OPTION_END)) {
-        if (options[offset] == option_type) {
-           LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("option found at offset=%u\n", offset));
-          return &options[offset];
-        /* skip option */
-        } else {
-          LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("skipping option %u\n", options[offset]));
-          /* skip option type */
-          offset++;
-          offset += 1 + options[offset];
-        }
-      }
-    }
-  }
-  return 0;
-}
-
-/**
- * Return the byte of DHCP option data.
- *
- * @param client DHCP client.
- * @param ptr pointer obtained by dhcp_get_option_ptr().
- *
- * @return byte value at the given address.
- */
-static u8_t dhcp_get_option_byte(u8_t *ptr)
-{
-  LWIP_DEBUGF(DHCP_DEBUG, ("option byte value=%u\n", *ptr));
-  return *ptr;
-}
-
-/**
- * Return the 16-bit value of DHCP option data.
- *
- * @param client DHCP client.
- * @param ptr pointer obtained by dhcp_get_option_ptr().
- *
- * @return byte value at the given address.
- */
-static u16_t dhcp_get_option_short(u8_t *ptr)
-{
-  u16_t value;
-  value = *ptr++ << 8;
-  value |= *ptr;
-  LWIP_DEBUGF(DHCP_DEBUG, ("option short value=%u\n", value));
-  return value;
-}
-
-/**
- * Return the 32-bit value of DHCP option data.
- *
- * @param client DHCP client.
- * @param ptr pointer obtained by dhcp_get_option_ptr().
- *
- * @return byte value at the given address.
- */
-static u32_t dhcp_get_option_long(u8_t *ptr)
-{
-  u32_t value;
-  value = (u32_t)(*ptr++) << 24;
-  value |= (u32_t)(*ptr++) << 16;
-  value |= (u32_t)(*ptr++) << 8;
-  value |= (u32_t)(*ptr++);
-  LWIP_DEBUGF(DHCP_DEBUG, ("option long value=%lu\n", value));
-  return value;
-}
-
-#endif /* LWIP_DHCP */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/inet.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/inet.c
deleted file mode 100644
index 59c80ea48..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/inet.c
+++ /dev/null
@@ -1,377 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels 
- *
- */
-
-
-/* inet.c
- *
- * Functions common to all TCP/IP modules, such as the Internet checksum and the
- * byte order functions.
- *
- */
-
-
-#include "lwip/opt.h"
-
-#include "lwip/arch.h"
-
-#include "lwip/def.h"
-#include "lwip/inet.h"
-
-#include "lwip/sys.h"
-
-/* This is a reference implementation of the checksum algorithm
-
- - it may not work on all architectures, and all processors, particularly
-   if they have issues with alignment and 16 bit access.
-
- - in this case you will need to port it to your architecture and 
-   #define LWIP_CHKSUM  
-   in your sys_arch.h
-*/
-#ifndef LWIP_CHKSUM
-#define LWIP_CHKSUM lwip_standard_chksum
-static u16_t
-lwip_standard_chksum(void *dataptr, int len)
-{
-  u32_t acc;
-
-  LWIP_DEBUGF(INET_DEBUG, ("lwip_chksum(%p, %d)\n", (void *)dataptr, len));
-  for(acc = 0; len > 1; len -= 2) {
-      /*    acc = acc + *((u16_t *)dataptr)++;*/
-    acc += *(u16_t *)dataptr;
-    dataptr = (void *)((u16_t *)dataptr + 1);
-  }
-
-  /* add up any odd byte */
-  if (len == 1) {
-    acc += htons((u16_t)((*(u8_t *)dataptr) & 0xff) << 8);
-    LWIP_DEBUGF(INET_DEBUG, ("inet: chksum: odd byte %d\n", (unsigned int)(*(u8_t *)dataptr)));
-  } else {
-    LWIP_DEBUGF(INET_DEBUG, ("inet: chksum: no odd byte\n"));
-  }
-  acc = (acc >> 16) + (acc & 0xffffUL);
-
-  if ((acc & 0xffff0000) != 0) {
-    acc = (acc >> 16) + (acc & 0xffffUL);
-  }
-
-  return (u16_t)acc;
-}
-#endif
-
-/* inet_chksum_pseudo:
- *
- * Calculates the pseudo Internet checksum used by TCP and UDP for a pbuf chain.
- */
-
-u16_t
-inet_chksum_pseudo(struct pbuf *p,
-       struct ip_addr *src, struct ip_addr *dest,
-       u8_t proto, u16_t proto_len)
-{
-  u32_t acc;
-  struct pbuf *q;
-  u8_t swapped;
-
-  acc = 0;
-  swapped = 0;
-  /* iterate through all pbuf in chain */
-  for(q = p; q != NULL; q = q->next) {
-    LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): checksumming pbuf %p (has next %p) \n",
-      (void *)q, (void *)q->next));
-    acc += LWIP_CHKSUM(q->payload, q->len);
-    /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): unwrapped lwip_chksum()=%lx \n", acc));*/
-    while (acc >> 16) {
-      acc = (acc & 0xffffUL) + (acc >> 16);
-    }
-    if (q->len % 2 != 0) {
-      swapped = 1 - swapped;
-      acc = ((acc & 0xff) << 8) | ((acc & 0xff00UL) >> 8);
-    }
-    /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): wrapped lwip_chksum()=%lx \n", acc));*/
-  }
-
-  if (swapped) {
-    acc = ((acc & 0xff) << 8) | ((acc & 0xff00UL) >> 8);
-  }
-  acc += (src->addr & 0xffffUL);
-  acc += ((src->addr >> 16) & 0xffffUL);
-  acc += (dest->addr & 0xffffUL);
-  acc += ((dest->addr >> 16) & 0xffffUL);
-  acc += (u32_t)htons((u16_t)proto);
-  acc += (u32_t)htons(proto_len);
-
-  while (acc >> 16) {
-    acc = (acc & 0xffffUL) + (acc >> 16);
-  }
-  LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): pbuf chain lwip_chksum()=%lx\n", acc));
-  return (u16_t)~(acc & 0xffffUL);
-}
-
-/* inet_chksum:
- *
- * Calculates the Internet checksum over a portion of memory. Used primarely for IP
- * and ICMP.
- */
-
-u16_t
-inet_chksum(void *dataptr, u16_t len)
-{
-  u32_t acc;
-
-  acc = LWIP_CHKSUM(dataptr, len);
-  while (acc >> 16) {
-    acc = (acc & 0xffff) + (acc >> 16);
-  }
-  return (u16_t)~(acc & 0xffff);
-}
-
-u16_t
-inet_chksum_pbuf(struct pbuf *p)
-{
-  u32_t acc;
-  struct pbuf *q;
-  u8_t swapped;
-
-  acc = 0;
-  swapped = 0;
-  for(q = p; q != NULL; q = q->next) {
-    acc += LWIP_CHKSUM(q->payload, q->len);
-    while (acc >> 16) {
-      acc = (acc & 0xffffUL) + (acc >> 16);
-    }
-    if (q->len % 2 != 0) {
-      swapped = 1 - swapped;
-      acc = (acc & 0x00ffUL << 8) | (acc & 0xff00UL >> 8);
-    }
-  }
-
-  if (swapped) {
-    acc = ((acc & 0x00ffUL) << 8) | ((acc & 0xff00UL) >> 8);
-  }
-  return (u16_t)~(acc & 0xffffUL);
-}
-
-/* Here for now until needed in other places in lwIP */
-#ifndef isascii
-#define in_range(c, lo, up)  ((u8_t)c >= lo && (u8_t)c <= up)
-#define isascii(c)           in_range(c, 0x20, 0x7f)
-#define isdigit(c)           in_range(c, '0', '9')
-#define isxdigit(c)          (isdigit(c) || in_range(c, 'a', 'f') || in_range(c, 'A', 'F'))
-#define islower(c)           in_range(c, 'a', 'z')
-#define isspace(c)           (c == ' ' || c == '\f' || c == '\n' || c == '\r' || c == '\t' || c == '\v')
-#endif		
-		
-
- /*
-  * Ascii internet address interpretation routine.
-  * The value returned is in network order.
-  */
-
- /*  */
- /* inet_addr */
- u32_t inet_addr(const char *cp)
- {
-     struct in_addr val;
-
-     if (inet_aton(cp, &val)) {
-         return (val.s_addr);
-     }
-     return (INADDR_NONE);
- }
-
- /*
-  * Check whether "cp" is a valid ascii representation
-  * of an Internet address and convert to a binary address.
-  * Returns 1 if the address is valid, 0 if not.
-  * This replaces inet_addr, the return value from which
-  * cannot distinguish between failure and a local broadcast address.
-  */
- /*  */
- /* inet_aton */
- int inet_aton(const char *cp, struct in_addr *addr)
- {
-     u32_t val;
-     int base, n;
-     char c;
-     u32_t parts[4];
-     u32_t* pp = parts;
-
-     c = *cp;
-     for (;;) {
-         /*
-          * Collect number up to ``.''.
-          * Values are specified as for C:
-          * 0x=hex, 0=octal, isdigit=decimal.
-          */
-         if (!isdigit(c))
-             return (0);
-         val = 0; base = 10;
-         if (c == '0') {
-             c = *++cp;
-             if (c == 'x' || c == 'X')
-                 base = 16, c = *++cp;
-             else
-                 base = 8;
-         }
-         for (;;) {
-             if (isdigit(c)) {
-                 val = (val * base) + (int)(c - '0');
-                 c = *++cp;
-             } else if (base == 16 && isxdigit(c)) {
-                 val = (val << 4) |
-                     (int)(c + 10 - (islower(c) ? 'a' : 'A'));
-                 c = *++cp;
-             } else
-             break;
-         }
-         if (c == '.') {
-             /*
-              * Internet format:
-              *  a.b.c.d
-              *  a.b.c   (with c treated as 16 bits)
-              *  a.b (with b treated as 24 bits)
-              */
-             if (pp >= parts + 3)
-                 return (0);
-             *pp++ = val;
-             c = *++cp;
-         } else
-             break;
-     }
-     /*
-      * Check for trailing characters.
-      */
-     if (c != '\0' && (!isascii(c) || !isspace(c)))
-         return (0);
-     /*
-      * Concoct the address according to
-      * the number of parts specified.
-      */
-     n = pp - parts + 1;
-     switch (n) {
-
-     case 0:
-         return (0);     /* initial nondigit */
-
-     case 1:             /* a -- 32 bits */
-         break;
-
-     case 2:             /* a.b -- 8.24 bits */
-         if (val > 0xffffff)
-             return (0);
-         val |= parts[0] << 24;
-         break;
-
-     case 3:             /* a.b.c -- 8.8.16 bits */
-         if (val > 0xffff)
-             return (0);
-         val |= (parts[0] << 24) | (parts[1] << 16);
-         break;
-
-     case 4:             /* a.b.c.d -- 8.8.8.8 bits */
-         if (val > 0xff)
-             return (0);
-         val |= (parts[0] << 24) | (parts[1] << 16) | (parts[2] << 8);
-         break;
-     }
-     if (addr)
-         addr->s_addr = htonl(val);
-     return (1);
- }
-
-/* Convert numeric IP address into decimal dotted ASCII representation.
- * returns ptr to static buffer; not reentrant!
- */
-char *inet_ntoa(struct in_addr addr)
-{
-  static char str[16];
-  u32_t s_addr = addr.s_addr;
-  char inv[3];
-  char *rp;
-  u8_t *ap;
-  u8_t rem;
-  u8_t n;
-  u8_t i;
-
-  rp = str;
-  ap = (u8_t *)&s_addr;
-  for(n = 0; n < 4; n++) {
-    i = 0;
-    do {
-      rem = *ap % (u8_t)10;
-      *ap /= (u8_t)10;
-      inv[i++] = '0' + rem;
-    } while(*ap);
-    while(i--)
-      *rp++ = inv[i];
-    *rp++ = '.';
-    ap++;
-  }
-  *--rp = 0;
-  return str;
-}
-
-
-#ifndef BYTE_ORDER
-#error BYTE_ORDER is not defined
-#endif
-#if BYTE_ORDER == LITTLE_ENDIAN
-
-u16_t
-htons(u16_t n)
-{
-  return ((n & 0xff) << 8) | ((n & 0xff00) >> 8);
-}
-
-u16_t
-ntohs(u16_t n)
-{
-  return htons(n);
-}
-
-u32_t
-htonl(u32_t n)
-{
-  return ((n & 0xff) << 24) |
-    ((n & 0xff00) << 8) |
-    ((n & 0xff0000) >> 8) |
-    ((n & 0xff000000) >> 24);
-}
-
-u32_t
-ntohl(u32_t n)
-{
-  return htonl(n);
-}
-
-#endif /* BYTE_ORDER == LITTLE_ENDIAN */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/inet6.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/inet6.c
deleted file mode 100644
index c04915b73..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/inet6.c
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-
-
-/* inet6.c
- *
- * Functions common to all TCP/IP modules, such as the Internet checksum and the
- * byte order functions.
- *
- */
-
-
-#include "lwip/opt.h"
-
-#include "lwip/def.h"
-#include "lwip/inet.h"
-
-
-
-/* chksum:
- *
- * Sums up all 16 bit words in a memory portion. Also includes any odd byte.
- * This function is used by the other checksum functions.
- *
- * For now, this is not optimized. Must be optimized for the particular processor
- * arcitecture on which it is to run. Preferebly coded in assembler.
- */
-
-static u32_t
-chksum(void *dataptr, u16_t len)
-{
-  u16_t *sdataptr = dataptr;
-  u32_t acc;
-  
-  
-  for(acc = 0; len > 1; len -= 2) {
-    acc += *sdataptr++;
-  }
-
-  /* add up any odd byte */
-  if (len == 1) {
-    acc += htons((u16_t)(*(u8_t *)dataptr) << 8);
-  }
-
-  return acc;
-
-}
-
-/* inet_chksum_pseudo:
- *
- * Calculates the pseudo Internet checksum used by TCP and UDP for a pbuf chain.
- */
-
-u16_t
-inet_chksum_pseudo(struct pbuf *p,
-       struct ip_addr *src, struct ip_addr *dest,
-       u8_t proto, u32_t proto_len)
-{
-  u32_t acc;
-  struct pbuf *q;
-  u8_t swapped, i;
-
-  acc = 0;
-  swapped = 0;
-  for(q = p; q != NULL; q = q->next) {    
-    acc += chksum(q->payload, q->len);
-    while (acc >> 16) {
-      acc = (acc & 0xffff) + (acc >> 16);
-    }
-    if (q->len % 2 != 0) {
-      swapped = 1 - swapped;
-      acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8);
-    }
-  }
-
-  if (swapped) {
-    acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8);
-  }
-  
-  for(i = 0; i < 8; i++) {
-    acc += ((u16_t *)src->addr)[i] & 0xffff;
-    acc += ((u16_t *)dest->addr)[i] & 0xffff;
-    while (acc >> 16) {
-      acc = (acc & 0xffff) + (acc >> 16);
-    }
-  }
-  acc += (u16_t)htons((u16_t)proto);
-  acc += ((u16_t *)&proto_len)[0] & 0xffff;
-  acc += ((u16_t *)&proto_len)[1] & 0xffff;
-
-  while (acc >> 16) {
-    acc = (acc & 0xffff) + (acc >> 16);
-  }
-  return ~(acc & 0xffff);
-}
-
-/* inet_chksum:
- *
- * Calculates the Internet checksum over a portion of memory. Used primarely for IP
- * and ICMP.
- */
-
-u16_t
-inet_chksum(void *dataptr, u16_t len)
-{
-  u32_t acc, sum;
-
-  acc = chksum(dataptr, len);
-  sum = (acc & 0xffff) + (acc >> 16);
-  sum += (sum >> 16);
-  return ~(sum & 0xffff);
-}
-
-u16_t
-inet_chksum_pbuf(struct pbuf *p)
-{
-  u32_t acc;
-  struct pbuf *q;
-  u8_t swapped;
-  
-  acc = 0;
-  swapped = 0;
-  for(q = p; q != NULL; q = q->next) {
-    acc += chksum(q->payload, q->len);
-    while (acc >> 16) {
-      acc = (acc & 0xffff) + (acc >> 16);
-    }    
-    if (q->len % 2 != 0) {
-      swapped = 1 - swapped;
-      acc = (acc & 0xff << 8) | (acc & 0xff00 >> 8);
-    }
-  }
- 
-  if (swapped) {
-    acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8);
-  }
-  return ~(acc & 0xffff);
-}
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv4/icmp.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv4/icmp.c
deleted file mode 100644
index 45525e44c..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv4/icmp.c
+++ /dev/null
@@ -1,205 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels 
- *
- */
-
-/* Some ICMP messages should be passed to the transport protocols. This
-   is not implemented. */
-
-#include "lwip/opt.h"
-
-#include "lwip/icmp.h"
-#include "lwip/inet.h"
-#include "lwip/ip.h"
-#include "lwip/def.h"
-
-#include "lwip/stats.h"
-
-#include "lwip/snmp.h"
-
-#include 
-
-void
-icmp_input(struct pbuf *p, struct netif *inp)
-{
-  unsigned char type;
-  unsigned char code;
-  struct icmp_echo_hdr *iecho;
-  struct ip_hdr *iphdr;
-  struct ip_addr tmpaddr;
-  u16_t hlen;
-
-  ICMP_STATS_INC(icmp.recv);
-  snmp_inc_icmpinmsgs();
-
-
-  iphdr = p->payload;
-  hlen = IPH_HL(iphdr) * 4;
-  if (pbuf_header(p, -((s16_t)hlen)) || (p->tot_len < sizeof(u16_t)*2)) {
-    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: short ICMP (%u bytes) received\n", p->tot_len));
-    pbuf_free(p);
-    ICMP_STATS_INC(icmp.lenerr);
-    snmp_inc_icmpinerrors();
-    return;
-  }
-
-  type = *((u8_t *)p->payload);
-  code = *(((u8_t *)p->payload)+1);
-  switch (type) {
-  case ICMP_ECHO:
-    /* broadcast or multicast destination address? */
-    if (ip_addr_isbroadcast(&iphdr->dest, inp) || ip_addr_ismulticast(&iphdr->dest)) {
-      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: Not echoing to multicast or broadcast pings\n"));
-      ICMP_STATS_INC(icmp.err);
-      pbuf_free(p);
-      return;
-    }
-    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ping\n"));
-    if (p->tot_len < sizeof(struct icmp_echo_hdr)) {
-      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: bad ICMP echo received\n"));
-      pbuf_free(p);
-      ICMP_STATS_INC(icmp.lenerr);
-      snmp_inc_icmpinerrors();
-
-      return;
-    }
-    iecho = p->payload;
-    if (inet_chksum_pbuf(p) != 0) {
-      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo\n"));
-      pbuf_free(p);
-      ICMP_STATS_INC(icmp.chkerr);
-      snmp_inc_icmpinerrors();
-      return;
-    }
-    tmpaddr.addr = iphdr->src.addr;
-    iphdr->src.addr = iphdr->dest.addr;
-    iphdr->dest.addr = tmpaddr.addr;
-    ICMPH_TYPE_SET(iecho, ICMP_ER);
-    /* adjust the checksum */
-    if (iecho->chksum >= htons(0xffff - (ICMP_ECHO << 8))) {
-      iecho->chksum += htons(ICMP_ECHO << 8) + 1;
-    } else {
-      iecho->chksum += htons(ICMP_ECHO << 8);
-    }
-    ICMP_STATS_INC(icmp.xmit);
-    /* increase number of messages attempted to send */
-    snmp_inc_icmpoutmsgs();
-    /* increase number of echo replies attempted to send */
-    snmp_inc_icmpoutechoreps();
-
-    pbuf_header(p, hlen);
-    ip_output_if(p, &(iphdr->src), IP_HDRINCL,
-		 IPH_TTL(iphdr), 0, IP_PROTO_ICMP, inp);
-    break;
-  default:
-  LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ICMP type %d code %d not supported.\n", (int)type, (int)code));
-    ICMP_STATS_INC(icmp.proterr);
-    ICMP_STATS_INC(icmp.drop);
-  }
-  pbuf_free(p);
-}
-
-void
-icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t)
-{
-  struct pbuf *q;
-  struct ip_hdr *iphdr;
-  struct icmp_dur_hdr *idur;
-
-  q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM);
-  /* ICMP header + IP header + 8 bytes of data */
-
-  iphdr = p->payload;
-
-  idur = q->payload;
-  ICMPH_TYPE_SET(idur, ICMP_DUR);
-  ICMPH_CODE_SET(idur, t);
-
-  memcpy((char *)q->payload + 8, p->payload, IP_HLEN + 8);
-
-  /* calculate checksum */
-  idur->chksum = 0;
-  idur->chksum = inet_chksum(idur, q->len);
-  ICMP_STATS_INC(icmp.xmit);
-  /* increase number of messages attempted to send */
-  snmp_inc_icmpoutmsgs();
-  /* increase number of destination unreachable messages attempted to send */
-  snmp_inc_icmpoutdestunreachs();
-
-  ip_output(q, NULL, &(iphdr->src),
-	    ICMP_TTL, 0, IP_PROTO_ICMP);
-  pbuf_free(q);
-}
-
-#if IP_FORWARD
-void
-icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t)
-{
-  struct pbuf *q;
-  struct ip_hdr *iphdr;
-  struct icmp_te_hdr *tehdr;
-
-  q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM);
-
-  iphdr = p->payload;
-  LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded from "));
-  ip_addr_debug_print(ICMP_DEBUG, &(iphdr->src));
-  LWIP_DEBUGF(ICMP_DEBUG, (" to "));
-  ip_addr_debug_print(ICMP_DEBUG, &(iphdr->dest));
-  LWIP_DEBUGF(ICMP_DEBUG, ("\n"));
-
-  tehdr = q->payload;
-  ICMPH_TYPE_SET(tehdr, ICMP_TE);
-  ICMPH_CODE_SET(tehdr, t);
-
-  /* copy fields from original packet */
-  memcpy((char *)q->payload + 8, (char *)p->payload, IP_HLEN + 8);
-
-  /* calculate checksum */
-  tehdr->chksum = 0;
-  tehdr->chksum = inet_chksum(tehdr, q->len);
-  ICMP_STATS_INC(icmp.xmit);
-  /* increase number of messages attempted to send */
-  snmp_inc_icmpoutmsgs();
-  /* increase number of destination unreachable messages attempted to send */
-  snmp_inc_icmpouttimeexcds();
-  ip_output(q, NULL, &(iphdr->src),
-	    ICMP_TTL, 0, IP_PROTO_ICMP);
-  pbuf_free(q);
-}
-
-#endif /* IP_FORWARD */
-
-
-
-
-
-
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv4/ip.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv4/ip.c
deleted file mode 100644
index 368d97763..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv4/ip.c
+++ /dev/null
@@ -1,508 +0,0 @@
-/* @file
- *
- * This is the IP layer implementation for incoming and outgoing IP traffic.
- * 
- * @see ip_frag.c
- *
- */
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels 
- *
- */
-
-#include "lwip/opt.h"
-
-#include "lwip/def.h"
-#include "lwip/mem.h"
-#include "lwip/ip.h"
-#include "lwip/ip_frag.h"
-#include "lwip/inet.h"
-#include "lwip/netif.h"
-#include "lwip/icmp.h"
-#include "lwip/raw.h"
-#include "lwip/udp.h"
-#include "lwip/tcp.h"
-
-#include "lwip/stats.h"
-
-#include "arch/perf.h"
-
-#include "lwip/snmp.h"
-#if LWIP_DHCP
-#  include "lwip/dhcp.h"
-#endif /* LWIP_DHCP */
-
-
-/**
- * Initializes the IP layer.
- */
-
-void
-ip_init(void)
-{
-  /* no initializations as of yet */
-}
-
-/**
- * Finds the appropriate network interface for a given IP address. It
- * searches the list of network interfaces linearly. A match is found
- * if the masked IP address of the network interface equals the masked
- * IP address given to the function.
- */
-
-struct netif *
-ip_route(struct ip_addr *dest)
-{
-  struct netif *netif;
-
-  /* iterate through netifs */
-  for(netif = netif_list; netif != NULL; netif = netif->next) {
-    /* network mask matches? */
-    if (ip_addr_netcmp(dest, &(netif->ip_addr), &(netif->netmask))) {
-      /* return netif on which to forward IP packet */
-      return netif;
-    }
-  }
-  /* no matching netif found, use default netif */
-  return netif_default;
-}
-#if IP_FORWARD
-
-/**
- * Forwards an IP packet. It finds an appropriate route for the
- * packet, decrements the TTL value of the packet, adjusts the
- * checksum and outputs the packet on the appropriate interface.
- */
-
-static struct netif *
-ip_forward(struct pbuf *p, struct ip_hdr *iphdr, struct netif *inp)
-{
-  struct netif *netif;
-
-  PERF_START;
-  /* Find network interface where to forward this IP packet to. */
-  netif = ip_route((struct ip_addr *)&(iphdr->dest));
-  if (netif == NULL) {
-    LWIP_DEBUGF(IP_DEBUG, ("ip_forward: no forwarding route for 0x%lx found\n",
-                      iphdr->dest.addr));
-    snmp_inc_ipnoroutes();
-    return (struct netif *)NULL;
-  }
-  /* Do not forward packets onto the same network interface on which
-   * they arrived. */
-  if (netif == inp) {
-    LWIP_DEBUGF(IP_DEBUG, ("ip_forward: not bouncing packets back on incoming interface.\n"));
-    snmp_inc_ipnoroutes();
-    return (struct netif *)NULL;
-  }
-
-  /* decrement TTL */
-  IPH_TTL_SET(iphdr, IPH_TTL(iphdr) - 1);
-  /* send ICMP if TTL == 0 */
-  if (IPH_TTL(iphdr) == 0) {
-    /* Don't send ICMP messages in response to ICMP messages */
-    if (IPH_PROTO(iphdr) != IP_PROTO_ICMP) {
-      icmp_time_exceeded(p, ICMP_TE_TTL);
-      snmp_inc_icmpouttimeexcds();
-    }
-    return (struct netif *)NULL;
-  }
-
-  /* Incrementally update the IP checksum. */
-  if (IPH_CHKSUM(iphdr) >= htons(0xffff - 0x100)) {
-    IPH_CHKSUM_SET(iphdr, IPH_CHKSUM(iphdr) + htons(0x100) + 1);
-  } else {
-    IPH_CHKSUM_SET(iphdr, IPH_CHKSUM(iphdr) + htons(0x100));
-  }
-
-  LWIP_DEBUGF(IP_DEBUG, ("ip_forward: forwarding packet to 0x%lx\n",
-                    iphdr->dest.addr));
-
-  IP_STATS_INC(ip.fw);
-  IP_STATS_INC(ip.xmit);
-    snmp_inc_ipforwdatagrams();
-
-  PERF_STOP("ip_forward");
-  /* transmit pbuf on chosen interface */
-  netif->output(netif, p, (struct ip_addr *)&(iphdr->dest));
-  return netif;
-}
-#endif /* IP_FORWARD */
-
-/**
- * This function is called by the network interface device driver when
- * an IP packet is received. The function does the basic checks of the
- * IP header such as packet size being at least larger than the header
- * size etc. If the packet was not destined for us, the packet is
- * forwarded (using ip_forward). The IP checksum is always checked.
- *
- * Finally, the packet is sent to the upper layer protocol input function.
- * 
- * 
- * 
- */
-
-err_t
-ip_input(struct pbuf *p, struct netif *inp) {
-  struct ip_hdr *iphdr;
-  struct netif *netif;
-  u16_t iphdrlen;
-
-  IP_STATS_INC(ip.recv);
-  snmp_inc_ipinreceives();
-
-  /* identify the IP header */
-  iphdr = p->payload;
-  if (IPH_V(iphdr) != 4) {
-    LWIP_DEBUGF(IP_DEBUG | 1, ("IP packet dropped due to bad version number %u\n", IPH_V(iphdr)));
-    ip_debug_print(p);
-    pbuf_free(p);
-    IP_STATS_INC(ip.err);
-    IP_STATS_INC(ip.drop);
-    snmp_inc_ipunknownprotos();
-    return ERR_OK;
-  }
-  /* obtain IP header length in number of 32-bit words */
-  iphdrlen = IPH_HL(iphdr);
-  /* calculate IP header length in bytes */
-  iphdrlen *= 4;
-
-  /* header length exceeds first pbuf length? */
-  if (iphdrlen > p->len) {
-    LWIP_DEBUGF(IP_DEBUG | 2, ("IP header (len %u) does not fit in first pbuf (len %u), IP packet droppped.\n",
-      iphdrlen, p->len));
-    /* free (drop) packet pbufs */
-    pbuf_free(p);
-    IP_STATS_INC(ip.lenerr);
-    IP_STATS_INC(ip.drop);
-    snmp_inc_ipindiscards();
-    return ERR_OK;
-  }
-
-  /* verify checksum */
-#if CHECKSUM_CHECK_IP
-  if (inet_chksum(iphdr, iphdrlen) != 0) {
-
-    LWIP_DEBUGF(IP_DEBUG | 2, ("Checksum (0x%x) failed, IP packet dropped.\n", inet_chksum(iphdr, iphdrlen)));
-    ip_debug_print(p);
-    pbuf_free(p);
-    IP_STATS_INC(ip.chkerr);
-    IP_STATS_INC(ip.drop);
-    snmp_inc_ipindiscards();
-    return ERR_OK;
-  }
-#endif
-
-  /* Trim pbuf. This should have been done at the netif layer,
-   * but we'll do it anyway just to be sure that its done. */
-  pbuf_realloc(p, ntohs(IPH_LEN(iphdr)));
-
-  /* match packet against an interface, i.e. is this packet for us? */
-  for (netif = netif_list; netif != NULL; netif = netif->next) {
-
-    LWIP_DEBUGF(IP_DEBUG, ("ip_input: iphdr->dest 0x%lx netif->ip_addr 0x%lx (0x%lx, 0x%lx, 0x%lx)\n",
-      iphdr->dest.addr, netif->ip_addr.addr,
-      iphdr->dest.addr & netif->netmask.addr,
-      netif->ip_addr.addr & netif->netmask.addr,
-      iphdr->dest.addr & ~(netif->netmask.addr)));
-
-    /* interface is up and configured? */
-    if ((netif_is_up(netif)) && (!ip_addr_isany(&(netif->ip_addr))))
-    {
-      /* unicast to this interface address? */
-      if (ip_addr_cmp(&(iphdr->dest), &(netif->ip_addr)) ||
-         /* or broadcast on this interface network address? */
-         ip_addr_isbroadcast(&(iphdr->dest), netif)) {
-        LWIP_DEBUGF(IP_DEBUG, ("ip_input: packet accepted on interface %c%c\n",
-          netif->name[0], netif->name[1]));
-        /* break out of for loop */
-        break;
-      }
-    }
-  }
-#if LWIP_DHCP
-  /* Pass DHCP messages regardless of destination address. DHCP traffic is addressed
-   * using link layer addressing (such as Ethernet MAC) so we must not filter on IP.
-   * According to RFC 1542 section 3.1.1, referred by RFC 2131).
-   */
-  if (netif == NULL) {
-    /* remote port is DHCP server? */
-    if (IPH_PROTO(iphdr) == IP_PROTO_UDP) {
-      LWIP_DEBUGF(IP_DEBUG | DBG_TRACE | 1, ("ip_input: UDP packet to DHCP client port %u\n",
-        ntohs(((struct udp_hdr *)((u8_t *)iphdr + iphdrlen))->dest)));
-      if (ntohs(((struct udp_hdr *)((u8_t *)iphdr + iphdrlen))->dest) == DHCP_CLIENT_PORT) {
-        LWIP_DEBUGF(IP_DEBUG | DBG_TRACE | 1, ("ip_input: DHCP packet accepted.\n"));
-        netif = inp;
-      }
-    }
-  }
-#endif /* LWIP_DHCP */
-  /* packet not for us? */
-  if (netif == NULL) {
-    /* packet not for us, route or discard */
-    LWIP_DEBUGF(IP_DEBUG | DBG_TRACE | 1, ("ip_input: packet not for us.\n"));
-#if IP_FORWARD
-    /* non-broadcast packet? */
-    if (!ip_addr_isbroadcast(&(iphdr->dest), inp)) {
-      /* try to forward IP packet on (other) interfaces */
-      ip_forward(p, iphdr, inp);
-    }
-    else
-#endif /* IP_FORWARD */
-    {
-      snmp_inc_ipindiscards();
-    }
-    pbuf_free(p);
-    return ERR_OK;
-  }
-  /* packet consists of multiple fragments? */
-  if ((IPH_OFFSET(iphdr) & htons(IP_OFFMASK | IP_MF)) != 0) {
-#if IP_REASSEMBLY /* packet fragment reassembly code present? */
-    LWIP_DEBUGF(IP_DEBUG, ("IP packet is a fragment (id=0x%04x tot_len=%u len=%u MF=%u offset=%u), calling ip_reass()\n",
-      ntohs(IPH_ID(iphdr)), p->tot_len, ntohs(IPH_LEN(iphdr)), !!(IPH_OFFSET(iphdr) & htons(IP_MF)), (ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK)*8));
-    /* reassemble the packet*/
-    p = ip_reass(p);
-    /* packet not fully reassembled yet? */
-    if (p == NULL) {
-      return ERR_OK;
-    }
-    iphdr = p->payload;
-#else /* IP_REASSEMBLY == 0, no packet fragment reassembly code present */
-    pbuf_free(p);
-    LWIP_DEBUGF(IP_DEBUG | 2, ("IP packet dropped since it was fragmented (0x%x) (while IP_REASSEMBLY == 0).\n",
-      ntohs(IPH_OFFSET(iphdr))));
-    IP_STATS_INC(ip.opterr);
-    IP_STATS_INC(ip.drop);
-    snmp_inc_ipunknownprotos();
-    return ERR_OK;
-#endif /* IP_REASSEMBLY */
-  }
-
-#if IP_OPTIONS == 0 /* no support for IP options in the IP header? */
-  if (iphdrlen > IP_HLEN) {
-    LWIP_DEBUGF(IP_DEBUG | 2, ("IP packet dropped since there were IP options (while IP_OPTIONS == 0).\n"));
-    pbuf_free(p);
-    IP_STATS_INC(ip.opterr);
-    IP_STATS_INC(ip.drop);
-    snmp_inc_ipunknownprotos();
-    return ERR_OK;
-  }
-#endif /* IP_OPTIONS == 0 */
-
-  /* send to upper layers */
-  LWIP_DEBUGF(IP_DEBUG, ("ip_input: \n"));
-  ip_debug_print(p);
-  LWIP_DEBUGF(IP_DEBUG, ("ip_input: p->len %d p->tot_len %d\n", p->len, p->tot_len));
-
-#if LWIP_RAW
-  /* raw input did not eat the packet? */
-  if (raw_input(p, inp) == 0) {
-#endif /* LWIP_RAW */
-
-  switch (IPH_PROTO(iphdr)) {
-#if LWIP_UDP
-  case IP_PROTO_UDP:
-  case IP_PROTO_UDPLITE:
-    snmp_inc_ipindelivers();
-    udp_input(p, inp);
-    break;
-#endif /* LWIP_UDP */
-#if LWIP_TCP
-  case IP_PROTO_TCP:
-    snmp_inc_ipindelivers();
-    tcp_input(p, inp);
-    break;
-#endif /* LWIP_TCP */
-  case IP_PROTO_ICMP:
-    snmp_inc_ipindelivers();
-    icmp_input(p, inp);
-    break;
-  default:
-    /* send ICMP destination protocol unreachable unless is was a broadcast */
-    if (!ip_addr_isbroadcast(&(iphdr->dest), inp) &&
-        !ip_addr_ismulticast(&(iphdr->dest))) {
-      p->payload = iphdr;
-      icmp_dest_unreach(p, ICMP_DUR_PROTO);
-    }
-    pbuf_free(p);
-
-    LWIP_DEBUGF(IP_DEBUG | 2, ("Unsupported transport protocol %d\n", IPH_PROTO(iphdr)));
-
-    IP_STATS_INC(ip.proterr);
-    IP_STATS_INC(ip.drop);
-    snmp_inc_ipunknownprotos();
-  }
-#if LWIP_RAW
-  } /* LWIP_RAW */
-#endif
-  return ERR_OK;
-}
-
-/**
- * Sends an IP packet on a network interface. This function constructs
- * the IP header and calculates the IP header checksum. If the source
- * IP address is NULL, the IP address of the outgoing network
- * interface is filled in as source address.
- */
-
-err_t
-ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
-             u8_t ttl, u8_t tos,
-             u8_t proto, struct netif *netif)
-{
-  struct ip_hdr *iphdr;
-  u16_t ip_id = 0;
-
-  snmp_inc_ipoutrequests();
-
-  if (dest != IP_HDRINCL) {
-    if (pbuf_header(p, IP_HLEN)) {
-      LWIP_DEBUGF(IP_DEBUG | 2, ("ip_output: not enough room for IP header in pbuf\n"));
-
-      IP_STATS_INC(ip.err);
-      snmp_inc_ipoutdiscards();
-      return ERR_BUF;
-    }
-
-    iphdr = p->payload;
-
-    IPH_TTL_SET(iphdr, ttl);
-    IPH_PROTO_SET(iphdr, proto);
-
-    ip_addr_set(&(iphdr->dest), dest);
-
-    IPH_VHLTOS_SET(iphdr, 4, IP_HLEN / 4, tos);
-    IPH_LEN_SET(iphdr, htons(p->tot_len));
-    IPH_OFFSET_SET(iphdr, htons(IP_DF));
-    IPH_ID_SET(iphdr, htons(ip_id));
-    ++ip_id;
-
-    if (ip_addr_isany(src)) {
-      ip_addr_set(&(iphdr->src), &(netif->ip_addr));
-    } else {
-      ip_addr_set(&(iphdr->src), src);
-    }
-
-    IPH_CHKSUM_SET(iphdr, 0);
-#if CHECKSUM_GEN_IP
-    IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN));
-#endif
-  } else {
-    iphdr = p->payload;
-    dest = &(iphdr->dest);
-  }
-
-#if IP_FRAG
-  /* don't fragment if interface has mtu set to 0 [loopif] */
-  if (netif->mtu && (p->tot_len > netif->mtu))
-    return ip_frag(p,netif,dest);
-#endif
-
-  IP_STATS_INC(ip.xmit);
-
-  LWIP_DEBUGF(IP_DEBUG, ("ip_output_if: %c%c%u\n", netif->name[0], netif->name[1], netif->num));
-  ip_debug_print(p);
-
-  LWIP_DEBUGF(IP_DEBUG, ("netif->output()"));
-
-  return netif->output(netif, p, dest);
-}
-
-/**
- * Simple interface to ip_output_if. It finds the outgoing network
- * interface and calls upon ip_output_if to do the actual work.
- */
-
-err_t
-ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
-          u8_t ttl, u8_t tos, u8_t proto)
-{
-  struct netif *netif;
-
-  if ((netif = ip_route(dest)) == NULL) {
-    LWIP_DEBUGF(IP_DEBUG | 2, ("ip_output: No route to 0x%lx\n", dest->addr));
-
-    IP_STATS_INC(ip.rterr);
-    snmp_inc_ipoutdiscards();
-    return ERR_RTE;
-  }
-
-  return ip_output_if(p, src, dest, ttl, tos, proto, netif);
-}
-
-#if IP_DEBUG
-void
-ip_debug_print(struct pbuf *p)
-{
-  struct ip_hdr *iphdr = p->payload;
-  u8_t *payload;
-
-  payload = (u8_t *)iphdr + IP_HLEN;
-
-  LWIP_DEBUGF(IP_DEBUG, ("IP header:\n"));
-  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
-  LWIP_DEBUGF(IP_DEBUG, ("|%2d |%2d |  0x%02x |     %5u     | (v, hl, tos, len)\n",
-                    IPH_V(iphdr),
-                    IPH_HL(iphdr),
-                    IPH_TOS(iphdr),
-                    ntohs(IPH_LEN(iphdr))));
-  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
-  LWIP_DEBUGF(IP_DEBUG, ("|    %5u      |%u%u%u|    %4u   | (id, flags, offset)\n",
-                    ntohs(IPH_ID(iphdr)),
-                    ntohs(IPH_OFFSET(iphdr)) >> 15 & 1,
-                    ntohs(IPH_OFFSET(iphdr)) >> 14 & 1,
-                    ntohs(IPH_OFFSET(iphdr)) >> 13 & 1,
-                    ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK));
-  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
-  LWIP_DEBUGF(IP_DEBUG, ("|  %3u  |  %3u  |    0x%04x     | (ttl, proto, chksum)\n",
-                    IPH_TTL(iphdr),
-                    IPH_PROTO(iphdr),
-                    ntohs(IPH_CHKSUM(iphdr))));
-  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
-  LWIP_DEBUGF(IP_DEBUG, ("|  %3u  |  %3u  |  %3u  |  %3u  | (src)\n",
-                    ip4_addr1(&iphdr->src),
-                    ip4_addr2(&iphdr->src),
-                    ip4_addr3(&iphdr->src),
-                    ip4_addr4(&iphdr->src)));
-  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
-  LWIP_DEBUGF(IP_DEBUG, ("|  %3u  |  %3u  |  %3u  |  %3u  | (dest)\n",
-                    ip4_addr1(&iphdr->dest),
-                    ip4_addr2(&iphdr->dest),
-                    ip4_addr3(&iphdr->dest),
-                    ip4_addr4(&iphdr->dest)));
-  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
-}
-#endif /* IP_DEBUG */
-
-
-
-
-
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv4/ip_addr.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv4/ip_addr.c
deleted file mode 100644
index 2af526e9f..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv4/ip_addr.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-
-#include "lwip/ip_addr.h"
-#include "lwip/inet.h"
-#include "lwip/netif.h"
-
-/* used by IP_ADDR_ANY and IP_ADDR_BROADCAST in ip_addr.h */
-const struct ip_addr ip_addr_any = { 0x00000000UL };
-const struct ip_addr ip_addr_broadcast = { 0xffffffffUL };
-
-/* Determine if an address is a broadcast address on a network interface 
- * 
- * @param addr address to be checked
- * @param netif the network interface against which the address is checked
- * @return returns non-zero if the address is a broadcast address
- *
- */
-
-u8_t ip_addr_isbroadcast(struct ip_addr *addr, struct netif *netif)
-{
-  /* all ones (broadcast) or all zeroes (old skool broadcast) */
-  if ((addr->addr == ip_addr_broadcast.addr) ||
-      (addr->addr == ip_addr_any.addr))
-    return 1;
-  /* no broadcast support on this network interface? */
-  else if ((netif->flags & NETIF_FLAG_BROADCAST) == 0)
-    /* the given address cannot be a broadcast address
-     * nor can we check against any broadcast addresses */
-    return 0;
-  /* address matches network interface address exactly? => no broadcast */
-  else if (addr->addr == netif->ip_addr.addr)
-    return 0;
-  /*  on the same (sub) network... */
-  else if (ip_addr_netcmp(addr, &(netif->ip_addr), &(netif->netmask))
-         /* ...and host identifier bits are all ones? =>... */
-          && ((addr->addr & ~netif->netmask.addr) ==
-           (ip_addr_broadcast.addr & ~netif->netmask.addr)))
-    /* => network broadcast address */
-    return 1;
-  else
-    return 0;
-}
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv4/ip_frag.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv4/ip_frag.c
deleted file mode 100644
index 380929317..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv4/ip_frag.c
+++ /dev/null
@@ -1,345 +0,0 @@
-/* @file
- * 
- * This is the IP packet segmentation and reassembly implementation.
- *
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Jani Monoses  
- * original reassembly code by Adam Dunkels 
- * 
- */
-
-#include "lwip/opt.h"
-#include "lwip/sys.h"
-#include "lwip/ip.h"
-#include "lwip/ip_frag.h"
-#include "lwip/netif.h"
-
-#include "lwip/stats.h"
-
-#include 
-
-/*
- * Copy len bytes from offset in pbuf to buffer 
- *
- * helper used by both ip_reass and ip_frag
- */
-static struct pbuf *
-copy_from_pbuf(struct pbuf *p, u16_t * offset,
-           u8_t * buffer, u16_t len)
-{
-  u16_t l;
-
-  p->payload = (u8_t *)p->payload + *offset;
-  p->len -= *offset;
-  while (len) {
-    l = len < p->len ? len : p->len;
-    memcpy(buffer, p->payload, l);
-    buffer += l;
-    len -= l;
-    if (len)
-      p = p->next;
-    else
-      *offset = l;
-  }
-  return p;
-}
-
-#define IP_REASS_BUFSIZE 5760
-#define IP_REASS_MAXAGE 30
-#define IP_REASS_TMO 1000
-
-static u8_t ip_reassbuf[IP_HLEN + IP_REASS_BUFSIZE];
-static u8_t ip_reassbitmap[IP_REASS_BUFSIZE / (8 * 8)];
-static const u8_t bitmap_bits[8] = { 0xff, 0x7f, 0x3f, 0x1f,
-  0x0f, 0x07, 0x03, 0x01
-};
-static u16_t ip_reasslen;
-static u8_t ip_reassflags;
-#define IP_REASS_FLAG_LASTFRAG 0x01
-
-static u8_t ip_reasstmr;
-
-/* Reassembly timer */ 
-static void 
-ip_reass_timer(void *arg)
-{
-  (void)arg;
-  if (ip_reasstmr > 1) {
-    ip_reasstmr--;
-    sys_timeout(IP_REASS_TMO, ip_reass_timer, NULL);
-  } else if (ip_reasstmr == 1)
-  ip_reasstmr = 0;
-}
-
-struct pbuf *
-ip_reass(struct pbuf *p)
-{
-  struct pbuf *q;
-  struct ip_hdr *fraghdr, *iphdr;
-  u16_t offset, len;
-  u16_t i;
-
-  IPFRAG_STATS_INC(ip_frag.recv);
-
-  iphdr = (struct ip_hdr *) ip_reassbuf;
-  fraghdr = (struct ip_hdr *) p->payload;
-  /* If ip_reasstmr is zero, no packet is present in the buffer, so we
-     write the IP header of the fragment into the reassembly
-     buffer. The timer is updated with the maximum age. */
-  if (ip_reasstmr == 0) {
-    LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass: new packet\n"));
-    memcpy(iphdr, fraghdr, IP_HLEN);
-    ip_reasstmr = IP_REASS_MAXAGE;
-    sys_timeout(IP_REASS_TMO, ip_reass_timer, NULL);
-    ip_reassflags = 0;
-    /* Clear the bitmap. */
-    memset(ip_reassbitmap, 0, sizeof(ip_reassbitmap));
-  }
-
-  /* Check if the incoming fragment matches the one currently present
-     in the reasembly buffer. If so, we proceed with copying the
-     fragment into the buffer. */
-  if (ip_addr_cmp(&iphdr->src, &fraghdr->src) &&
-      ip_addr_cmp(&iphdr->dest, &fraghdr->dest) &&
-      IPH_ID(iphdr) == IPH_ID(fraghdr)) {
-    LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass: matching old packet\n"));
-    IPFRAG_STATS_INC(ip_frag.cachehit);
-    /* Find out the offset in the reassembly buffer where we should
-       copy the fragment. */
-    len = ntohs(IPH_LEN(fraghdr)) - IPH_HL(fraghdr) * 4;
-    offset = (ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) * 8;
-
-    /* If the offset or the offset + fragment length overflows the
-       reassembly buffer, we discard the entire packet. */
-    if (offset > IP_REASS_BUFSIZE || offset + len > IP_REASS_BUFSIZE) {
-      LWIP_DEBUGF(IP_REASS_DEBUG,
-       ("ip_reass: fragment outside of buffer (%d:%d/%d).\n", offset,
-        offset + len, IP_REASS_BUFSIZE));
-      sys_untimeout(ip_reass_timer, NULL);
-      ip_reasstmr = 0;
-      goto nullreturn;
-    }
-
-    /* Copy the fragment into the reassembly buffer, at the right
-       offset. */
-    LWIP_DEBUGF(IP_REASS_DEBUG,
-     ("ip_reass: copying with offset %d into %d:%d\n", offset,
-      IP_HLEN + offset, IP_HLEN + offset + len));
-    i = IPH_HL(fraghdr) * 4;
-    copy_from_pbuf(p, &i, &ip_reassbuf[IP_HLEN + offset], len);
-
-    /* Update the bitmap. */
-    if (offset / (8 * 8) == (offset + len) / (8 * 8)) {
-      LWIP_DEBUGF(IP_REASS_DEBUG,
-       ("ip_reass: updating single byte in bitmap.\n"));
-      /* If the two endpoints are in the same byte, we only update
-         that byte. */
-      ip_reassbitmap[offset / (8 * 8)] |=
-    bitmap_bits[(offset / 8) & 7] &
-    ~bitmap_bits[((offset + len) / 8) & 7];
-    } else {
-      /* If the two endpoints are in different bytes, we update the
-         bytes in the endpoints and fill the stuff inbetween with
-         0xff. */
-      ip_reassbitmap[offset / (8 * 8)] |= bitmap_bits[(offset / 8) & 7];
-      LWIP_DEBUGF(IP_REASS_DEBUG,
-       ("ip_reass: updating many bytes in bitmap (%d:%d).\n",
-        1 + offset / (8 * 8), (offset + len) / (8 * 8)));
-      for (i = 1 + offset / (8 * 8); i < (offset + len) / (8 * 8); ++i) {
-  ip_reassbitmap[i] = 0xff;
-      }
-      ip_reassbitmap[(offset + len) / (8 * 8)] |=
-    ~bitmap_bits[((offset + len) / 8) & 7];
-    }
-
-    /* If this fragment has the More Fragments flag set to zero, we
-       know that this is the last fragment, so we can calculate the
-       size of the entire packet. We also set the
-       IP_REASS_FLAG_LASTFRAG flag to indicate that we have received
-       the final fragment. */
-
-    if ((ntohs(IPH_OFFSET(fraghdr)) & IP_MF) == 0) {
-      ip_reassflags |= IP_REASS_FLAG_LASTFRAG;
-      ip_reasslen = offset + len;
-      LWIP_DEBUGF(IP_REASS_DEBUG,
-       ("ip_reass: last fragment seen, total len %d\n",
-        ip_reasslen));
-    }
-
-    /* Finally, we check if we have a full packet in the buffer. We do
-       this by checking if we have the last fragment and if all bits
-       in the bitmap are set. */
-    if (ip_reassflags & IP_REASS_FLAG_LASTFRAG) {
-      /* Check all bytes up to and including all but the last byte in
-         the bitmap. */
-      for (i = 0; i < ip_reasslen / (8 * 8) - 1; ++i) {
-  if (ip_reassbitmap[i] != 0xff) {
-    LWIP_DEBUGF(IP_REASS_DEBUG,
-     ("ip_reass: last fragment seen, bitmap %d/%d failed (%x)\n",
-      i, ip_reasslen / (8 * 8) - 1, ip_reassbitmap[i]));
-    goto nullreturn;
-  }
-      }
-      /* Check the last byte in the bitmap. It should contain just the
-         right amount of bits. */
-      if (ip_reassbitmap[ip_reasslen / (8 * 8)] !=
-    (u8_t) ~ bitmap_bits[ip_reasslen / 8 & 7]) {
-  LWIP_DEBUGF(IP_REASS_DEBUG,
-         ("ip_reass: last fragment seen, bitmap %d didn't contain %x (%x)\n",
-    ip_reasslen / (8 * 8), ~bitmap_bits[ip_reasslen / 8 & 7],
-    ip_reassbitmap[ip_reasslen / (8 * 8)]));
-  goto nullreturn;
-      }
-
-      /* Pretend to be a "normal" (i.e., not fragmented) IP packet
-         from now on. */
-      ip_reasslen += IP_HLEN;
-
-      IPH_LEN_SET(iphdr, htons(ip_reasslen));
-      IPH_OFFSET_SET(iphdr, 0);
-      IPH_CHKSUM_SET(iphdr, 0);
-      IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN));
-
-      /* If we have come this far, we have a full packet in the
-         buffer, so we allocate a pbuf and copy the packet into it. We
-         also reset the timer. */
-      sys_untimeout(ip_reass_timer, NULL);
-      ip_reasstmr = 0;
-      pbuf_free(p);
-      p = pbuf_alloc(PBUF_LINK, ip_reasslen, PBUF_POOL);
-      if (p != NULL) {
-  i = 0;
-  for (q = p; q != NULL; q = q->next) {
-    /* Copy enough bytes to fill this pbuf in the chain. The
-       available data in the pbuf is given by the q->len
-       variable. */
-    LWIP_DEBUGF(IP_REASS_DEBUG,
-     ("ip_reass: memcpy from %p (%d) to %p, %d bytes\n",
-      (void *)&ip_reassbuf[i], i, q->payload,
-      q->len > ip_reasslen - i ? ip_reasslen - i : q->len));
-    memcpy(q->payload, &ip_reassbuf[i],
-    q->len > ip_reasslen - i ? ip_reasslen - i : q->len);
-    i += q->len;
-  }
-  IPFRAG_STATS_INC(ip_frag.fw);
-      } else {
-  IPFRAG_STATS_INC(ip_frag.memerr);
-      }
-      LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass: p %p\n", (void*)p));
-      return p;
-    }
-  }
-
-nullreturn:
-  IPFRAG_STATS_INC(ip_frag.drop);
-  pbuf_free(p);
-  return NULL;
-}
-
-#define MAX_MTU 1500
-static u8_t buf[MEM_ALIGN_SIZE(MAX_MTU)];
-
-/**
- * Fragment an IP packet if too large
- *
- * Chop the packet in mtu sized chunks and send them in order
- * by using a fixed size static memory buffer (PBUF_ROM)
- */
-err_t 
-ip_frag(struct pbuf *p, struct netif *netif, struct ip_addr *dest)
-{
-  struct pbuf *rambuf;
-  struct pbuf *header;
-  struct ip_hdr *iphdr;
-  u16_t nfb = 0;
-  u16_t left, cop;
-  u16_t mtu = netif->mtu;
-  u16_t ofo, omf;
-  u16_t last;
-  u16_t poff = IP_HLEN;
-  u16_t tmp;
-
-  /* Get a RAM based MTU sized pbuf */
-  rambuf = pbuf_alloc(PBUF_LINK, 0, PBUF_REF);
-  rambuf->tot_len = rambuf->len = mtu;
-  rambuf->payload = MEM_ALIGN((void *)buf);
-
-  /* Copy the IP header in it */
-  iphdr = rambuf->payload;
-  memcpy(iphdr, p->payload, IP_HLEN);
-
-  /* Save original offset */
-  tmp = ntohs(IPH_OFFSET(iphdr));
-  ofo = tmp & IP_OFFMASK;
-  omf = tmp & IP_MF;
-
-  left = p->tot_len - IP_HLEN;
-
-  while (left) {
-    last = (left <= mtu - IP_HLEN);
-
-    /* Set new offset and MF flag */
-    ofo += nfb;
-    tmp = omf | (IP_OFFMASK & (ofo));
-    if (!last)
-      tmp = tmp | IP_MF;
-    IPH_OFFSET_SET(iphdr, htons(tmp));
-
-    /* Fill this fragment */
-    nfb = (mtu - IP_HLEN) / 8;
-    cop = last ? left : nfb * 8;
-
-    p = copy_from_pbuf(p, &poff, (u8_t *) iphdr + IP_HLEN, cop);
-
-    /* Correct header */
-    IPH_LEN_SET(iphdr, htons(cop + IP_HLEN));
-    IPH_CHKSUM_SET(iphdr, 0);
-    IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN));
-
-    if (last)
-      pbuf_realloc(rambuf, left + IP_HLEN);
-    /* This part is ugly: we alloc a RAM based pbuf for 
-     * the link level header for each chunk and then 
-     * free it.A PBUF_ROM style pbuf for which pbuf_header
-     * worked would make things simpler.
-     */
-    header = pbuf_alloc(PBUF_LINK, 0, PBUF_RAM);
-    pbuf_chain(header, rambuf);
-    netif->output(netif, header, dest);
-    IPFRAG_STATS_INC(ip_frag.xmit);
-    pbuf_free(header);
-
-    left -= cop;
-  }
-  pbuf_free(rambuf);
-  return ERR_OK;
-}
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv6/README b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv6/README
deleted file mode 100644
index 362000486..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv6/README
+++ /dev/null
@@ -1 +0,0 @@
-IPv6 support in lwIP is very experimental.
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv6/icmp6.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv6/icmp6.c
deleted file mode 100644
index a162758aa..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv6/icmp6.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels 
- *
- */
-
-/* Some ICMP messages should be passed to the transport protocols. This
-   is not implemented. */
-
-#include "lwip/opt.h"
-
-#include "lwip/icmp.h"
-#include "lwip/inet.h"
-#include "lwip/ip.h"
-#include "lwip/def.h"
-
-#include "lwip/stats.h"
-
-
-void
-icmp_input(struct pbuf *p, struct netif *inp)
-{
-  unsigned char type;
-  struct icmp_echo_hdr *iecho;
-  struct ip_hdr *iphdr;
-  struct ip_addr tmpaddr;
-
-#ifdef ICMP_STATS
-  ++lwip_stats.icmp.recv;
-#endif /* ICMP_STATS */
-
-  /* TODO: check length before accessing payload! */
-
-  type = ((char *)p->payload)[0];
-
-  switch (type) {
-  case ICMP6_ECHO:
-    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ping\n"));
-
-    if (p->tot_len < sizeof(struct icmp_echo_hdr)) {
-      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: bad ICMP echo received\n"));
-
-      pbuf_free(p);
-#ifdef ICMP_STATS
-      ++lwip_stats.icmp.lenerr;
-#endif /* ICMP_STATS */
-
-      return;
-    }
-    iecho = p->payload;
-    iphdr = (struct ip_hdr *)((char *)p->payload - IP_HLEN);
-    if (inet_chksum_pbuf(p) != 0) {
-      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo (%x)\n", inet_chksum_pseudo(p, &(iphdr->src), &(iphdr->dest), IP_PROTO_ICMP, p->tot_len)));
-
-#ifdef ICMP_STATS
-      ++lwip_stats.icmp.chkerr;
-#endif /* ICMP_STATS */
-    /*      return;*/
-    }
-    LWIP_DEBUGF(ICMP_DEBUG, ("icmp: p->len %d p->tot_len %d\n", p->len, p->tot_len));
-    ip_addr_set(&tmpaddr, &(iphdr->src));
-    ip_addr_set(&(iphdr->src), &(iphdr->dest));
-    ip_addr_set(&(iphdr->dest), &tmpaddr);
-    iecho->type = ICMP6_ER;
-    /* adjust the checksum */
-    if (iecho->chksum >= htons(0xffff - (ICMP6_ECHO << 8))) {
-      iecho->chksum += htons(ICMP6_ECHO << 8) + 1;
-    } else {
-      iecho->chksum += htons(ICMP6_ECHO << 8);
-    }
-    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo (%x)\n", inet_chksum_pseudo(p, &(iphdr->src), &(iphdr->dest), IP_PROTO_ICMP, p->tot_len)));
-#ifdef ICMP_STATS
-    ++lwip_stats.icmp.xmit;
-#endif /* ICMP_STATS */
-
-    /*    LWIP_DEBUGF("icmp: p->len %u p->tot_len %u\n", p->len, p->tot_len);*/
-    ip_output_if (p, &(iphdr->src), IP_HDRINCL,
-     iphdr->hoplim, IP_PROTO_ICMP, inp);
-    break;
-  default:
-    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ICMP type %d not supported.\n", (int)type));
-#ifdef ICMP_STATS
-    ++lwip_stats.icmp.proterr;
-    ++lwip_stats.icmp.drop;
-#endif /* ICMP_STATS */
-  }
-
-  pbuf_free(p);
-}
-
-void
-icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t)
-{
-  struct pbuf *q;
-  struct ip_hdr *iphdr;
-  struct icmp_dur_hdr *idur;
-
-  q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM);
-  /* ICMP header + IP header + 8 bytes of data */
-
-  iphdr = p->payload;
-
-  idur = q->payload;
-  idur->type = (char)ICMP6_DUR;
-  idur->icode = (char)t;
-
-  memcpy((char *)q->payload + 8, p->payload, IP_HLEN + 8);
-
-  /* calculate checksum */
-  idur->chksum = 0;
-  idur->chksum = inet_chksum(idur, q->len);
-#ifdef ICMP_STATS
-  ++lwip_stats.icmp.xmit;
-#endif /* ICMP_STATS */
-
-  ip_output(q, NULL,
-      (struct ip_addr *)&(iphdr->src), ICMP_TTL, IP_PROTO_ICMP);
-  pbuf_free(q);
-}
-
-void
-icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t)
-{
-  struct pbuf *q;
-  struct ip_hdr *iphdr;
-  struct icmp_te_hdr *tehdr;
-
-  LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded\n"));
-
-  q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM);
-
-  iphdr = p->payload;
-
-  tehdr = q->payload;
-  tehdr->type = (char)ICMP6_TE;
-  tehdr->icode = (char)t;
-
-  /* copy fields from original packet */
-  memcpy((char *)q->payload + 8, (char *)p->payload, IP_HLEN + 8);
-
-  /* calculate checksum */
-  tehdr->chksum = 0;
-  tehdr->chksum = inet_chksum(tehdr, q->len);
-#ifdef ICMP_STATS
-  ++lwip_stats.icmp.xmit;
-#endif /* ICMP_STATS */
-  ip_output(q, NULL,
-      (struct ip_addr *)&(iphdr->src), ICMP_TTL, IP_PROTO_ICMP);
-  pbuf_free(q);
-}
-
-
-
-
-
-
-
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv6/ip6.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv6/ip6.c
deleted file mode 100644
index abce830cf..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv6/ip6.c
+++ /dev/null
@@ -1,386 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels 
- *
- */
-
-
-
-/* ip.c
- *
- * This is the code for the IP layer for IPv6.
- *
- */
-
-
-#include "lwip/opt.h"
-
-#include "lwip/def.h"
-#include "lwip/mem.h"
-#include "lwip/ip.h"
-#include "lwip/inet.h"
-#include "lwip/netif.h"
-#include "lwip/icmp.h"
-#include "lwip/udp.h"
-#include "lwip/tcp.h"
-
-#include "lwip/stats.h"
-
-#include "arch/perf.h"
-
-/* ip_init:
- *
- * Initializes the IP layer.
- */
-
-void
-ip_init(void)
-{
-}
-
-/* ip_route:
- *
- * Finds the appropriate network interface for a given IP address. It searches the
- * list of network interfaces linearly. A match is found if the masked IP address of
- * the network interface equals the masked IP address given to the function.
- */
-
-struct netif *
-ip_route(struct ip_addr *dest)
-{
-  struct netif *netif;
-
-  for(netif = netif_list; netif != NULL; netif = netif->next) {
-    if (ip_addr_netcmp(dest, &(netif->ip_addr), &(netif->netmask))) {
-      return netif;
-    }
-  }
-
-  return netif_default;
-}
-
-/* ip_forward:
- *
- * Forwards an IP packet. It finds an appropriate route for the packet, decrements
- * the TTL value of the packet, adjusts the checksum and outputs the packet on the
- * appropriate interface.
- */
-
-static void
-ip_forward(struct pbuf *p, struct ip_hdr *iphdr)
-{
-  struct netif *netif;
-
-  PERF_START;
-
-  if ((netif = ip_route((struct ip_addr *)&(iphdr->dest))) == NULL) {
-
-    LWIP_DEBUGF(IP_DEBUG, ("ip_input: no forwarding route found for "));
-#if IP_DEBUG
-    ip_addr_debug_print(IP_DEBUG, &(iphdr->dest));
-#endif /* IP_DEBUG */
-    LWIP_DEBUGF(IP_DEBUG, ("\n"));
-    pbuf_free(p);
-    return;
-  }
-  /* Decrement TTL and send ICMP if ttl == 0. */
-  if (--iphdr->hoplim == 0) {
-    /* Don't send ICMP messages in response to ICMP messages */
-    if (iphdr->nexthdr != IP_PROTO_ICMP) {
-      icmp_time_exceeded(p, ICMP_TE_TTL);
-    }
-    pbuf_free(p);
-    return;
-  }
-
-  /* Incremental update of the IP checksum. */
-  /*  if (iphdr->chksum >= htons(0xffff - 0x100)) {
-    iphdr->chksum += htons(0x100) + 1;
-  } else {
-    iphdr->chksum += htons(0x100);
-    }*/
-
-
-  LWIP_DEBUGF(IP_DEBUG, ("ip_forward: forwarding packet to "));
-#if IP_DEBUG
-  ip_addr_debug_print(IP_DEBUG, &(iphdr->dest));
-#endif /* IP_DEBUG */
-  LWIP_DEBUGF(IP_DEBUG, ("\n"));
-
-#ifdef IP_STATS
-  ++lwip_stats.ip.fw;
-  ++lwip_stats.ip.xmit;
-#endif /* IP_STATS */
-
-  PERF_STOP("ip_forward");
-
-  netif->output(netif, p, (struct ip_addr *)&(iphdr->dest));
-}
-
-/* ip_input:
- *
- * This function is called by the network interface device driver when an IP packet is
- * received. The function does the basic checks of the IP header such as packet size
- * being at least larger than the header size etc. If the packet was not destined for
- * us, the packet is forwarded (using ip_forward). The IP checksum is always checked.
- *
- * Finally, the packet is sent to the upper layer protocol input function.
- */
-
-void
-ip_input(struct pbuf *p, struct netif *inp) {
-  struct ip_hdr *iphdr;
-  struct netif *netif;
-
-
-  PERF_START;
-
-#if IP_DEBUG
-  ip_debug_print(p);
-#endif /* IP_DEBUG */
-
-
-#ifdef IP_STATS
-  ++lwip_stats.ip.recv;
-#endif /* IP_STATS */
-
-  /* identify the IP header */
-  iphdr = p->payload;
-
-
-  if (iphdr->v != 6) {
-    LWIP_DEBUGF(IP_DEBUG, ("IP packet dropped due to bad version number\n"));
-#if IP_DEBUG
-    ip_debug_print(p);
-#endif /* IP_DEBUG */
-    pbuf_free(p);
-#ifdef IP_STATS
-    ++lwip_stats.ip.err;
-    ++lwip_stats.ip.drop;
-#endif /* IP_STATS */
-    return;
-  }
-
-  /* is this packet for us? */
-  for(netif = netif_list; netif != NULL; netif = netif->next) {
-#if IP_DEBUG
-    LWIP_DEBUGF(IP_DEBUG, ("ip_input: iphdr->dest "));
-    ip_addr_debug_print(IP_DEBUG, &(iphdr->dest));
-    LWIP_DEBUGF(IP_DEBUG, ("netif->ip_addr "));
-    ip_addr_debug_print(IP_DEBUG, &(netif->ip_addr));
-    LWIP_DEBUGF(IP_DEBUG, ("\n"));
-#endif /* IP_DEBUG */
-    if (ip_addr_cmp(&(iphdr->dest), &(netif->ip_addr))) {
-      break;
-    }
-  }
-
-
-  if (netif == NULL) {
-    /* packet not for us, route or discard */
-#ifdef IP_FORWARD
-    ip_forward(p, iphdr);
-#endif
-    pbuf_free(p);
-    return;
-  }
-
-  pbuf_realloc(p, IP_HLEN + ntohs(iphdr->len));
-
-  /* send to upper layers */
-#if IP_DEBUG
-  /*  LWIP_DEBUGF("ip_input: \n");
-  ip_debug_print(p);
-  LWIP_DEBUGF("ip_input: p->len %u p->tot_len %u\n", p->len, p->tot_len);*/
-#endif /* IP_DEBUG */
-
-
-  pbuf_header(p, -IP_HLEN);
-
-  switch (iphdr->nexthdr) {
-  case IP_PROTO_UDP:
-    udp_input(p);
-    break;
-  case IP_PROTO_TCP:
-    tcp_input(p);
-    break;
-  case IP_PROTO_ICMP:
-    icmp_input(p, inp);
-    break;
-  default:
-    /* send ICMP destination protocol unreachable */
-    icmp_dest_unreach(p, ICMP_DUR_PROTO);
-    pbuf_free(p);
-    LWIP_DEBUGF(IP_DEBUG, ("Unsupported transport protocol %u\n",
-          iphdr->nexthdr));
-
-#ifdef IP_STATS
-    ++lwip_stats.ip.proterr;
-    ++lwip_stats.ip.drop;
-#endif /* IP_STATS */
-
-  }
-  PERF_STOP("ip_input");
-}
-
-
-/* ip_output_if:
- *
- * Sends an IP packet on a network interface. This function constructs the IP header
- * and calculates the IP header checksum. If the source IP address is NULL,
- * the IP address of the outgoing network interface is filled in as source address.
- */
-
-err_t
-ip_output_if (struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
-       u8_t ttl,
-       u8_t proto, struct netif *netif)
-{
-  struct ip_hdr *iphdr;
-
-  PERF_START;
-
-  printf("len %u tot_len %u\n", p->len, p->tot_len);
-  if (pbuf_header(p, IP_HLEN)) {
-    LWIP_DEBUGF(IP_DEBUG, ("ip_output: not enough room for IP header in pbuf\n"));
-#ifdef IP_STATS
-    ++lwip_stats.ip.err;
-#endif /* IP_STATS */
-
-    return ERR_BUF;
-  }
-  printf("len %u tot_len %u\n", p->len, p->tot_len);
-
-  iphdr = p->payload;
-
-
-  if (dest != IP_HDRINCL) {
-    printf("!IP_HDRLINCL\n");
-    iphdr->hoplim = ttl;
-    iphdr->nexthdr = proto;
-    iphdr->len = htons(p->tot_len - IP_HLEN);
-    ip_addr_set(&(iphdr->dest), dest);
-
-    iphdr->v = 6;
-
-    if (ip_addr_isany(src)) {
-      ip_addr_set(&(iphdr->src), &(netif->ip_addr));
-    } else {
-      ip_addr_set(&(iphdr->src), src);
-    }
-
-  } else {
-    dest = &(iphdr->dest);
-  }
-
-#ifdef IP_STATS
-  ++lwip_stats.ip.xmit;
-#endif /* IP_STATS */
-
-  LWIP_DEBUGF(IP_DEBUG, ("ip_output_if: %c%c (len %u)\n", netif->name[0], netif->name[1], p->tot_len));
-#if IP_DEBUG
-  ip_debug_print(p);
-#endif /* IP_DEBUG */
-
-  PERF_STOP("ip_output_if");
-  return netif->output(netif, p, dest);
-}
-
-/* ip_output:
- *
- * Simple interface to ip_output_if. It finds the outgoing network interface and
- * calls upon ip_output_if to do the actual work.
- */
-
-err_t
-ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
-    u8_t ttl, u8_t proto)
-{
-  struct netif *netif;
-  if ((netif = ip_route(dest)) == NULL) {
-    LWIP_DEBUGF(IP_DEBUG, ("ip_output: No route to 0x%lx\n", dest->addr));
-#ifdef IP_STATS
-    ++lwip_stats.ip.rterr;
-#endif /* IP_STATS */
-    return ERR_RTE;
-  }
-
-  return ip_output_if (p, src, dest, ttl, proto, netif);
-}
-
-#if IP_DEBUG
-void
-ip_debug_print(struct pbuf *p)
-{
-  struct ip_hdr *iphdr = p->payload;
-  char *payload;
-
-  payload = (char *)iphdr + IP_HLEN;
-
-  LWIP_DEBUGF(IP_DEBUG, ("IP header:\n"));
-  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
-  LWIP_DEBUGF(IP_DEBUG, ("|%2d |  %x%x  |      %x%x           | (v, traffic class, flow label)\n",
-        iphdr->v,
-        iphdr->tclass1, iphdr->tclass2,
-        iphdr->flow1, iphdr->flow2));
-  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
-  LWIP_DEBUGF(IP_DEBUG, ("|    %5u      | %2u  |  %2u   | (len, nexthdr, hoplim)\n",
-        ntohs(iphdr->len),
-        iphdr->nexthdr,
-        iphdr->hoplim));
-  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
-  LWIP_DEBUGF(IP_DEBUG, ("|       %4lx      |       %4lx     | (src)\n",
-        ntohl(iphdr->src.addr[0]) >> 16 & 0xffff,
-        ntohl(iphdr->src.addr[0]) & 0xffff));
-  LWIP_DEBUGF(IP_DEBUG, ("|       %4lx      |       %4lx     | (src)\n",
-        ntohl(iphdr->src.addr[1]) >> 16 & 0xffff,
-        ntohl(iphdr->src.addr[1]) & 0xffff));
-  LWIP_DEBUGF(IP_DEBUG, ("|       %4lx      |       %4lx     | (src)\n",
-        ntohl(iphdr->src.addr[2]) >> 16 & 0xffff,
-        ntohl(iphdr->src.addr[2]) & 0xffff));
-  LWIP_DEBUGF(IP_DEBUG, ("|       %4lx      |       %4lx     | (src)\n",
-        ntohl(iphdr->src.addr[3]) >> 16 & 0xffff,
-        ntohl(iphdr->src.addr[3]) & 0xffff));
-  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
-  LWIP_DEBUGF(IP_DEBUG, ("|       %4lx      |       %4lx     | (dest)\n",
-        ntohl(iphdr->dest.addr[0]) >> 16 & 0xffff,
-        ntohl(iphdr->dest.addr[0]) & 0xffff));
-  LWIP_DEBUGF(IP_DEBUG, ("|       %4lx      |       %4lx     | (dest)\n",
-        ntohl(iphdr->dest.addr[1]) >> 16 & 0xffff,
-        ntohl(iphdr->dest.addr[1]) & 0xffff));
-  LWIP_DEBUGF(IP_DEBUG, ("|       %4lx      |       %4lx     | (dest)\n",
-        ntohl(iphdr->dest.addr[2]) >> 16 & 0xffff,
-        ntohl(iphdr->dest.addr[2]) & 0xffff));
-  LWIP_DEBUGF(IP_DEBUG, ("|       %4lx      |       %4lx     | (dest)\n",
-        ntohl(iphdr->dest.addr[3]) >> 16 & 0xffff,
-        ntohl(iphdr->dest.addr[3]) & 0xffff));
-  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
-}
-#endif /* IP_DEBUG */
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv6/ip6_addr.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv6/ip6_addr.c
deleted file mode 100644
index d1bc358a6..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/ipv6/ip6_addr.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-
-#include "lwip/ip_addr.h"
-#include "lwip/inet.h"
-
-
-int
-ip_addr_netcmp(struct ip_addr *addr1, struct ip_addr *addr2,
-                struct ip_addr *mask)
-{
-  return((addr1->addr[0] & mask->addr[0]) == (addr2->addr[0] & mask->addr[0]) &&
-         (addr1->addr[1] & mask->addr[1]) == (addr2->addr[1] & mask->addr[1]) &&
-         (addr1->addr[2] & mask->addr[2]) == (addr2->addr[2] & mask->addr[2]) &&
-         (addr1->addr[3] & mask->addr[3]) == (addr2->addr[3] & mask->addr[3]));
-        
-}
-
-int
-ip_addr_cmp(struct ip_addr *addr1, struct ip_addr *addr2)
-{
-  return(addr1->addr[0] == addr2->addr[0] &&
-         addr1->addr[1] == addr2->addr[1] &&
-         addr1->addr[2] == addr2->addr[2] &&
-         addr1->addr[3] == addr2->addr[3]);
-}
-
-void
-ip_addr_set(struct ip_addr *dest, struct ip_addr *src)
-{
-  memcpy(dest, src, sizeof(struct ip_addr));
-  /*  dest->addr[0] = src->addr[0];
-  dest->addr[1] = src->addr[1];
-  dest->addr[2] = src->addr[2];
-  dest->addr[3] = src->addr[3];*/
-}
-
-int
-ip_addr_isany(struct ip_addr *addr)
-{
-  if (addr == NULL) return 1;
-  return((addr->addr[0] | addr->addr[1] | addr->addr[2] | addr->addr[3]) == 0);
-}
-
-
-/*#if IP_DEBUG*/
-void
-ip_addr_debug_print(struct ip_addr *addr)
-{
-  printf("%lx:%lx:%lx:%lx:%lx:%lx:%lx:%lx",
-         ntohl(addr->addr[0]) >> 16 & 0xffff,
-         ntohl(addr->addr[0]) & 0xffff,
-         ntohl(addr->addr[1]) >> 16 & 0xffff,
-         ntohl(addr->addr[1]) & 0xffff,
-         ntohl(addr->addr[2]) >> 16 & 0xffff,
-         ntohl(addr->addr[2]) & 0xffff,
-         ntohl(addr->addr[3]) >> 16 & 0xffff,
-         ntohl(addr->addr[3]) & 0xffff);
-}
-/*#endif*/ /* IP_DEBUG */
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/mem.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/mem.c
deleted file mode 100644
index aea62963b..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/mem.c
+++ /dev/null
@@ -1,310 +0,0 @@
-/** @file
- *
- * Dynamic memory manager
- *
- */
-
-/* 
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-
-#include 
-
-#include "lwip/arch.h"
-#include "lwip/opt.h"
-#include "lwip/def.h"
-#include "lwip/mem.h"
-
-#include "lwip/sys.h"
-
-#include "lwip/stats.h"
-
-struct mem {
-  mem_size_t next, prev;
-#if MEM_ALIGNMENT == 1
-  u8_t used;
-#elif MEM_ALIGNMENT == 2
-  u16_t used;
-#elif MEM_ALIGNMENT == 4
-  u32_t used;
-#elif MEM_ALIGNMENT == 8
-  u64_t used;
-#else
-#error "unhandled MEM_ALIGNMENT size"
-#endif /* MEM_ALIGNMENT */
-}; 
-
-static struct mem *ram_end;
-static u8_t ram[MEM_SIZE + sizeof(struct mem) + MEM_ALIGNMENT];
-
-#define MIN_SIZE 12
-#if 0 /* this one does not align correctly for some, resulting in crashes */
-#define SIZEOF_STRUCT_MEM (unsigned int)MEM_ALIGN_SIZE(sizeof(struct mem))
-#else
-#define SIZEOF_STRUCT_MEM (sizeof(struct mem) + \
-                          (((sizeof(struct mem) % MEM_ALIGNMENT) == 0)? 0 : \
-                          (4 - (sizeof(struct mem) % MEM_ALIGNMENT))))
-#endif
-
-static struct mem *lfree;   /* pointer to the lowest free block */
-
-static sys_sem_t mem_sem;
-
-static void
-plug_holes(struct mem *mem)
-{
-  struct mem *nmem;
-  struct mem *pmem;
-
-  LWIP_ASSERT("plug_holes: mem >= ram", (u8_t *)mem >= ram);
-  LWIP_ASSERT("plug_holes: mem < ram_end", (u8_t *)mem < (u8_t *)ram_end);
-  LWIP_ASSERT("plug_holes: mem->used == 0", mem->used == 0);
-  
-  /* plug hole forward */
-  LWIP_ASSERT("plug_holes: mem->next <= MEM_SIZE", mem->next <= MEM_SIZE);
-  
-  nmem = (struct mem *)&ram[mem->next];
-  if (mem != nmem && nmem->used == 0 && (u8_t *)nmem != (u8_t *)ram_end) {
-    if (lfree == nmem) {
-      lfree = mem;
-    }
-    mem->next = nmem->next;
-    ((struct mem *)&ram[nmem->next])->prev = (u8_t *)mem - ram;
-  }
-
-  /* plug hole backward */
-  pmem = (struct mem *)&ram[mem->prev];
-  if (pmem != mem && pmem->used == 0) {
-    if (lfree == mem) {
-      lfree = pmem;
-    }
-    pmem->next = mem->next;
-    ((struct mem *)&ram[mem->next])->prev = (u8_t *)pmem - ram;
-  }
-
-}
-void
-mem_init(void)
-{
-  struct mem *mem;
-
-  memset(ram, 0, MEM_SIZE);
-  mem = (struct mem *)ram;
-  mem->next = MEM_SIZE;
-  mem->prev = 0;
-  mem->used = 0;
-  ram_end = (struct mem *)&ram[MEM_SIZE];
-  ram_end->used = 1;
-  ram_end->next = MEM_SIZE;
-  ram_end->prev = MEM_SIZE;
-
-  mem_sem = sys_sem_new(1);
-
-  lfree = (struct mem *)ram;
-
-#if MEM_STATS
-  lwip_stats.mem.avail = MEM_SIZE;
-#endif /* MEM_STATS */
-}
-void
-mem_free(void *rmem)
-{
-  struct mem *mem;
-
-  if (rmem == NULL) {
-    LWIP_DEBUGF(MEM_DEBUG | DBG_TRACE | 2, ("mem_free(p == NULL) was called.\n"));
-    return;
-  }
-  
-  sys_sem_wait(mem_sem);
-
-  LWIP_ASSERT("mem_free: legal memory", (u8_t *)rmem >= (u8_t *)ram &&
-    (u8_t *)rmem < (u8_t *)ram_end);
-  
-  if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) {
-    LWIP_DEBUGF(MEM_DEBUG | 3, ("mem_free: illegal memory\n"));
-#if MEM_STATS
-    ++lwip_stats.mem.err;
-#endif /* MEM_STATS */
-    sys_sem_signal(mem_sem);
-    return;
-  }
-  mem = (struct mem *)((u8_t *)rmem - SIZEOF_STRUCT_MEM);
-
-  LWIP_ASSERT("mem_free: mem->used", mem->used);
-  
-  mem->used = 0;
-
-  if (mem < lfree) {
-    lfree = mem;
-  }
-  
-#if MEM_STATS
-  lwip_stats.mem.used -= mem->next - ((u8_t *)mem - ram);
-  
-#endif /* MEM_STATS */
-  plug_holes(mem);
-  sys_sem_signal(mem_sem);
-}
-void *
-mem_reallocm(void *rmem, mem_size_t newsize)
-{
-  void *nmem;
-  nmem = mem_malloc(newsize);
-  if (nmem == NULL) {
-    return mem_realloc(rmem, newsize);
-  }
-  memcpy(nmem, rmem, newsize);
-  mem_free(rmem);
-  return nmem;
-}
-
-void *
-mem_realloc(void *rmem, mem_size_t newsize)
-{
-  mem_size_t size;
-  mem_size_t ptr, ptr2;
-  struct mem *mem, *mem2;
-
-  /* Expand the size of the allocated memory region so that we can
-     adjust for alignment. */
-  if ((newsize % MEM_ALIGNMENT) != 0) {
-   newsize += MEM_ALIGNMENT - ((newsize + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT);
-  }
-  
-  if (newsize > MEM_SIZE) {
-    return NULL;
-  }
-  
-  sys_sem_wait(mem_sem);
-  
-  LWIP_ASSERT("mem_realloc: legal memory", (u8_t *)rmem >= (u8_t *)ram &&
-   (u8_t *)rmem < (u8_t *)ram_end);
-  
-  if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) {
-    LWIP_DEBUGF(MEM_DEBUG | 3, ("mem_realloc: illegal memory\n"));
-    return rmem;
-  }
-  mem = (struct mem *)((u8_t *)rmem - SIZEOF_STRUCT_MEM);
-
-  ptr = (u8_t *)mem - ram;
-
-  size = mem->next - ptr - SIZEOF_STRUCT_MEM;
-#if MEM_STATS
-  lwip_stats.mem.used -= (size - newsize);
-#endif /* MEM_STATS */
-  
-  if (newsize + SIZEOF_STRUCT_MEM + MIN_SIZE < size) {
-    ptr2 = ptr + SIZEOF_STRUCT_MEM + newsize;
-    mem2 = (struct mem *)&ram[ptr2];
-    mem2->used = 0;
-    mem2->next = mem->next;
-    mem2->prev = ptr;
-    mem->next = ptr2;
-    if (mem2->next != MEM_SIZE) {
-      ((struct mem *)&ram[mem2->next])->prev = ptr2;
-    }
-
-    plug_holes(mem2);
-  }
-  sys_sem_signal(mem_sem);  
-  return rmem;
-}
-void *
-mem_malloc(mem_size_t size)
-{
-  mem_size_t ptr, ptr2;
-  struct mem *mem, *mem2;
-
-  if (size == 0) {
-    return NULL;
-  }
-
-  /* Expand the size of the allocated memory region so that we can
-     adjust for alignment. */
-  if ((size % MEM_ALIGNMENT) != 0) {
-    size += MEM_ALIGNMENT - ((size + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT);
-  }
-  
-  if (size > MEM_SIZE) {
-    return NULL;
-  }
-  
-  sys_sem_wait(mem_sem);
-
-  for (ptr = (u8_t *)lfree - ram; ptr < MEM_SIZE; ptr = ((struct mem *)&ram[ptr])->next) {
-    mem = (struct mem *)&ram[ptr];
-    if (!mem->used &&
-       mem->next - (ptr + SIZEOF_STRUCT_MEM) >= size + SIZEOF_STRUCT_MEM) {
-      ptr2 = ptr + SIZEOF_STRUCT_MEM + size;
-      mem2 = (struct mem *)&ram[ptr2];
-
-      mem2->prev = ptr;      
-      mem2->next = mem->next;
-      mem->next = ptr2;      
-      if (mem2->next != MEM_SIZE) {
-        ((struct mem *)&ram[mem2->next])->prev = ptr2;
-      }
-      
-      mem2->used = 0;      
-      mem->used = 1;
-#if MEM_STATS
-      lwip_stats.mem.used += (size + SIZEOF_STRUCT_MEM);
-      /*      if (lwip_stats.mem.max < lwip_stats.mem.used) {
-        lwip_stats.mem.max = lwip_stats.mem.used;
-  } */
-      if (lwip_stats.mem.max < ptr2) {
-        lwip_stats.mem.max = ptr2;
-      }      
-#endif /* MEM_STATS */
-
-      if (mem == lfree) {
-  /* Find next free block after mem */
-        while (lfree->used && lfree != ram_end) {
-    lfree = (struct mem *)&ram[lfree->next];
-        }
-        LWIP_ASSERT("mem_malloc: !lfree->used", !lfree->used);
-      }
-      sys_sem_signal(mem_sem);
-      LWIP_ASSERT("mem_malloc: allocated memory not above ram_end.",
-       (mem_ptr_t)mem + SIZEOF_STRUCT_MEM + size <= (mem_ptr_t)ram_end);
-      LWIP_ASSERT("mem_malloc: allocated memory properly aligned.",
-       (unsigned long)((u8_t *)mem + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT == 0);
-      return (u8_t *)mem + SIZEOF_STRUCT_MEM;
-    }    
-  }
-  LWIP_DEBUGF(MEM_DEBUG | 2, ("mem_malloc: could not allocate %d bytes\n", (int)size));
-#if MEM_STATS
-  ++lwip_stats.mem.err;
-#endif /* MEM_STATS */  
-  sys_sem_signal(mem_sem);
-  return NULL;
-}
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/memp.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/memp.c
deleted file mode 100644
index c570b7e10..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/memp.c
+++ /dev/null
@@ -1,274 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-
-#include "lwip/opt.h"
-
-#include "lwip/memp.h"
-
-#include "lwip/pbuf.h"
-#include "lwip/udp.h"
-#include "lwip/raw.h"
-#include "lwip/tcp.h"
-#include "lwip/api.h"
-#include "lwip/api_msg.h"
-#include "lwip/tcpip.h"
-
-#include "lwip/sys.h"
-#include "lwip/stats.h"
-
-struct memp {
-  struct memp *next;
-};
-
-
-
-static struct memp *memp_tab[MEMP_MAX];
-
-static const u16_t memp_sizes[MEMP_MAX] = {
-  sizeof(struct pbuf),
-  sizeof(struct raw_pcb),
-  sizeof(struct udp_pcb),
-  sizeof(struct tcp_pcb),
-  sizeof(struct tcp_pcb_listen),
-  sizeof(struct tcp_seg),
-  sizeof(struct netbuf),
-  sizeof(struct netconn),
-  sizeof(struct api_msg),
-  sizeof(struct tcpip_msg),
-  sizeof(struct sys_timeout)
-};
-
-static const u16_t memp_num[MEMP_MAX] = {
-  MEMP_NUM_PBUF,
-  MEMP_NUM_RAW_PCB,
-  MEMP_NUM_UDP_PCB,
-  MEMP_NUM_TCP_PCB,
-  MEMP_NUM_TCP_PCB_LISTEN,
-  MEMP_NUM_TCP_SEG,
-  MEMP_NUM_NETBUF,
-  MEMP_NUM_NETCONN,
-  MEMP_NUM_API_MSG,
-  MEMP_NUM_TCPIP_MSG,
-  MEMP_NUM_SYS_TIMEOUT
-};
-
-static u8_t memp_memory[(MEMP_NUM_PBUF *
-       MEM_ALIGN_SIZE(sizeof(struct pbuf) +
-          sizeof(struct memp)) +
-      MEMP_NUM_RAW_PCB *
-       MEM_ALIGN_SIZE(sizeof(struct raw_pcb) +
-          sizeof(struct memp)) +
-      MEMP_NUM_UDP_PCB *
-       MEM_ALIGN_SIZE(sizeof(struct udp_pcb) +
-          sizeof(struct memp)) +
-      MEMP_NUM_TCP_PCB *
-       MEM_ALIGN_SIZE(sizeof(struct tcp_pcb) +
-          sizeof(struct memp)) +
-      MEMP_NUM_TCP_PCB_LISTEN *
-       MEM_ALIGN_SIZE(sizeof(struct tcp_pcb_listen) +
-          sizeof(struct memp)) +
-      MEMP_NUM_TCP_SEG *
-       MEM_ALIGN_SIZE(sizeof(struct tcp_seg) +
-          sizeof(struct memp)) +
-      MEMP_NUM_NETBUF *
-       MEM_ALIGN_SIZE(sizeof(struct netbuf) +
-          sizeof(struct memp)) +
-      MEMP_NUM_NETCONN *
-       MEM_ALIGN_SIZE(sizeof(struct netconn) +
-          sizeof(struct memp)) +
-      MEMP_NUM_API_MSG *
-       MEM_ALIGN_SIZE(sizeof(struct api_msg) +
-          sizeof(struct memp)) +
-      MEMP_NUM_TCPIP_MSG *
-       MEM_ALIGN_SIZE(sizeof(struct tcpip_msg) +
-          sizeof(struct memp)) +
-      MEMP_NUM_SYS_TIMEOUT *
-       MEM_ALIGN_SIZE(sizeof(struct sys_timeout) +
-          sizeof(struct memp)))];
-
-
-#if !SYS_LIGHTWEIGHT_PROT
-static sys_sem_t mutex;
-#endif
-
-#if MEMP_SANITY_CHECK
-static int
-memp_sanity(void)
-{
-  int i, c;
-  struct memp *m, *n;
-
-  for(i = 0; i < MEMP_MAX; i++) {
-    for(m = memp_tab[i]; m != NULL; m = m->next) {
-      c = 1;
-      for(n = memp_tab[i]; n != NULL; n = n->next) {
-         if (n == m) {
-          --c;
-        }
-        if (c < 0) return 0; /* LW was: abort(); */
-      }
-    }
-  }
-  return 1;
-}
-#endif /* MEMP_SANITY_CHECK*/
-
-void
-memp_init(void)
-{
-  struct memp *m, *memp;
-  u16_t i, j;
-  u16_t size;
-      
-#if MEMP_STATS
-  for(i = 0; i < MEMP_MAX; ++i) {
-    lwip_stats.memp[i].used = lwip_stats.memp[i].max =
-      lwip_stats.memp[i].err = 0;
-    lwip_stats.memp[i].avail = memp_num[i];
-  }
-#endif /* MEMP_STATS */
-
-  memp = (struct memp *)&memp_memory[0];
-  for(i = 0; i < MEMP_MAX; ++i) {
-    size = MEM_ALIGN_SIZE(memp_sizes[i] + sizeof(struct memp));
-    if (memp_num[i] > 0) {
-      memp_tab[i] = memp;
-      m = memp;
-      
-      for(j = 0; j < memp_num[i]; ++j) {
-  m->next = (struct memp *)MEM_ALIGN((u8_t *)m + size);
-  memp = m;
-  m = m->next;
-      }
-      memp->next = NULL;
-      memp = m;
-    } else {
-      memp_tab[i] = NULL;
-    }
-  }
-
-#if !SYS_LIGHTWEIGHT_PROT
-  mutex = sys_sem_new(1);
-#endif
-
-  
-}
-
-void *
-memp_malloc(memp_t type)
-{
-  struct memp *memp;
-  void *mem;
-#if SYS_LIGHTWEIGHT_PROT
-  SYS_ARCH_DECL_PROTECT(old_level);
-#endif
- 
-  LWIP_ASSERT("memp_malloc: type < MEMP_MAX", type < MEMP_MAX);
-
-#if SYS_LIGHTWEIGHT_PROT
-  SYS_ARCH_PROTECT(old_level);
-#else /* SYS_LIGHTWEIGHT_PROT */  
-  sys_sem_wait(mutex);
-#endif /* SYS_LIGHTWEIGHT_PROT */  
-
-  memp = memp_tab[type];
-  
-  if (memp != NULL) {    
-    memp_tab[type] = memp->next;    
-    memp->next = NULL;
-#if MEMP_STATS
-    ++lwip_stats.memp[type].used;
-    if (lwip_stats.memp[type].used > lwip_stats.memp[type].max) {
-      lwip_stats.memp[type].max = lwip_stats.memp[type].used;
-    }
-#endif /* MEMP_STATS */
-#if SYS_LIGHTWEIGHT_PROT
-    SYS_ARCH_UNPROTECT(old_level);
-#else /* SYS_LIGHTWEIGHT_PROT */
-    sys_sem_signal(mutex);
-#endif /* SYS_LIGHTWEIGHT_PROT */  
-    LWIP_ASSERT("memp_malloc: memp properly aligned",
-     ((mem_ptr_t)MEM_ALIGN((u8_t *)memp + sizeof(struct memp)) % MEM_ALIGNMENT) == 0);
-
-    mem = MEM_ALIGN((u8_t *)memp + sizeof(struct memp));
-    return mem;
-  } else {
-    LWIP_DEBUGF(MEMP_DEBUG | 2, ("memp_malloc: out of memory in pool %d\n", type));
-#if MEMP_STATS
-    ++lwip_stats.memp[type].err;
-#endif /* MEMP_STATS */
-#if SYS_LIGHTWEIGHT_PROT
-  SYS_ARCH_UNPROTECT(old_level);
-#else /* SYS_LIGHTWEIGHT_PROT */
-  sys_sem_signal(mutex);
-#endif /* SYS_LIGHTWEIGHT_PROT */  
-    return NULL;
-  }
-}
-
-void
-memp_free(memp_t type, void *mem)
-{
-  struct memp *memp;
-#if SYS_LIGHTWEIGHT_PROT
-  SYS_ARCH_DECL_PROTECT(old_level);
-#endif /* SYS_LIGHTWEIGHT_PROT */  
-
-  if (mem == NULL) {
-    return;
-  }
-  memp = (struct memp *)((u8_t *)mem - sizeof(struct memp));
-
-#if SYS_LIGHTWEIGHT_PROT
-    SYS_ARCH_PROTECT(old_level);
-#else /* SYS_LIGHTWEIGHT_PROT */  
-  sys_sem_wait(mutex);
-#endif /* SYS_LIGHTWEIGHT_PROT */  
-
-#if MEMP_STATS
-  lwip_stats.memp[type].used--; 
-#endif /* MEMP_STATS */
-  
-  memp->next = memp_tab[type]; 
-  memp_tab[type] = memp;
-
-#if MEMP_SANITY_CHECK
-  LWIP_ASSERT("memp sanity", memp_sanity());
-#endif  
-
-#if SYS_LIGHTWEIGHT_PROT
-  SYS_ARCH_UNPROTECT(old_level);
-#else /* SYS_LIGHTWEIGHT_PROT */
-  sys_sem_signal(mutex);
-#endif /* SYS_LIGHTWEIGHT_PROT */  
-}
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/netif.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/netif.c
deleted file mode 100644
index 32deb8d9d..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/netif.c
+++ /dev/null
@@ -1,288 +0,0 @@
-/**
- * @file
- *
- * lwIP network interface abstraction
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels 
- *
- */
-
-#include "lwip/opt.h"
-
-#include "lwip/def.h"
-#include "lwip/ip_addr.h"
-#include "lwip/netif.h"
-#include "lwip/tcp.h"
-
-struct netif *netif_list = NULL;
-struct netif *netif_default = NULL;
-
-/**
- * Add a network interface to the list of lwIP netifs.
- *
- * @param netif a pre-allocated netif structure
- * @param ipaddr IP address for the new netif
- * @param netmask network mask for the new netif
- * @param gw default gateway IP address for the new netif
- * @param state opaque data passed to the new netif
- * @param init callback function that initializes the interface
- * @param input callback function that is called to pass
- * ingress packets up in the protocol layer stack.
- *
- * @return netif, or NULL if failed.
- */
-struct netif *
-netif_add(struct netif *netif, struct ip_addr *ipaddr, struct ip_addr *netmask,
-  struct ip_addr *gw,
-  void *state,
-  err_t (* init)(struct netif *netif),
-  err_t (* input)(struct pbuf *p, struct netif *netif))
-{
-  static int netifnum = 0;
-  
-#if LWIP_DHCP
-  /* netif not under DHCP control by default */
-  netif->dhcp = NULL;
-#endif
-  /* remember netif specific state information data */
-  netif->state = state;
-  netif->num = netifnum++;
-  netif->input = input;
-
-  netif_set_addr(netif, ipaddr, netmask, gw);
-
-  /* call user specified initialization function for netif */
-  if (init(netif) != ERR_OK) {
-    return NULL;
-  }
-
-  /* add this netif to the list */
-  netif->next = netif_list;
-  netif_list = netif;
-  LWIP_DEBUGF(NETIF_DEBUG, ("netif: added interface %c%c IP addr ",
-    netif->name[0], netif->name[1]));
-  ip_addr_debug_print(NETIF_DEBUG, ipaddr);
-  LWIP_DEBUGF(NETIF_DEBUG, (" netmask "));
-  ip_addr_debug_print(NETIF_DEBUG, netmask);
-  LWIP_DEBUGF(NETIF_DEBUG, (" gw "));
-  ip_addr_debug_print(NETIF_DEBUG, gw);
-  LWIP_DEBUGF(NETIF_DEBUG, ("\n"));
-  return netif;
-}
-
-void
-netif_set_addr(struct netif *netif,struct ip_addr *ipaddr, struct ip_addr *netmask,
-    struct ip_addr *gw)
-{
-  netif_set_ipaddr(netif, ipaddr);
-  netif_set_netmask(netif, netmask);
-  netif_set_gw(netif, gw);
-}
-
-void netif_remove(struct netif * netif)
-{
-  if ( netif == NULL ) return;
-
-  /*  is it the first netif? */
-  if (netif_list == netif) {
-    netif_list = netif->next;
-  }
-  else {
-    /*  look for netif further down the list */
-    struct netif * tmpNetif;
-    for (tmpNetif = netif_list; tmpNetif != NULL; tmpNetif = tmpNetif->next) {
-      if (tmpNetif->next == netif) {
-        tmpNetif->next = netif->next;
-        break;
-        }
-    }
-    if (tmpNetif == NULL)
-      return; /*  we didn't find any netif today */
-  }
-  /* this netif is default? */
-  if (netif_default == netif)
-    /* reset default netif */
-    netif_default = NULL;
-  LWIP_DEBUGF( NETIF_DEBUG, ("netif_remove: removed netif\n") );
-}
-
-struct netif *
-netif_find(char *name)
-{
-  struct netif *netif;
-  u8_t num;
-
-  if (name == NULL) {
-    return NULL;
-  }
-
-  num = name[2] - '0';
-
-  for(netif = netif_list; netif != NULL; netif = netif->next) {
-    if (num == netif->num &&
-       name[0] == netif->name[0] &&
-       name[1] == netif->name[1]) {
-      LWIP_DEBUGF(NETIF_DEBUG, ("netif_find: found %c%c\n", name[0], name[1]));
-      return netif;
-    }
-  }
-  LWIP_DEBUGF(NETIF_DEBUG, ("netif_find: didn't find %c%c\n", name[0], name[1]));
-  return NULL;
-}
-
-void
-netif_set_ipaddr(struct netif *netif, struct ip_addr *ipaddr)
-{
-  /* TODO: Handling of obsolete pcbs */
-  /* See:  http://mail.gnu.org/archive/html/lwip-users/2003-03/msg00118.html */
-#if LWIP_TCP
-  struct tcp_pcb *pcb;
-  struct tcp_pcb_listen *lpcb;
-
-  /* address is actually being changed? */
-  if ((ip_addr_cmp(ipaddr, &(netif->ip_addr))) == 0)
-  {
-    /* extern struct tcp_pcb *tcp_active_pcbs; defined by tcp.h */
-    LWIP_DEBUGF(NETIF_DEBUG | 1, ("netif_set_ipaddr: netif address being changed\n"));
-    pcb = tcp_active_pcbs;
-    while (pcb != NULL) {
-      /* PCB bound to current local interface address? */
-      if (ip_addr_cmp(&(pcb->local_ip), &(netif->ip_addr))) {
-        /* this connection must be aborted */
-        struct tcp_pcb *next = pcb->next;
-        LWIP_DEBUGF(NETIF_DEBUG | 1, ("netif_set_ipaddr: aborting TCP pcb %p\n", (void *)pcb));
-        tcp_abort(pcb);
-        pcb = next;
-      } else {
-        pcb = pcb->next;
-      }
-    }
-    for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
-      /* PCB bound to current local interface address? */
-      if (ip_addr_cmp(&(lpcb->local_ip), &(netif->ip_addr))) {
-        /* The PCB is listening to the old ipaddr and
-         * is set to listen to the new one instead */
-        ip_addr_set(&(lpcb->local_ip), ipaddr);
-      }
-    }
-  }
-#endif
-  ip_addr_set(&(netif->ip_addr), ipaddr);
-#if 0 /* only allowed for Ethernet interfaces TODO: how can we check? */
-  /** For Ethernet network interfaces, we would like to send a
-   *  "gratuitous ARP"; this is an ARP packet sent by a node in order
-   *  to spontaneously cause other nodes to update an entry in their
-   *  ARP cache. From RFC 3220 "IP Mobility Support for IPv4" section 4.6.
-   */ 
-  etharp_query(netif, ipaddr, NULL);
-#endif
-  LWIP_DEBUGF(NETIF_DEBUG | DBG_TRACE | DBG_STATE | 3, ("netif: IP address of interface %c%c set to %u.%u.%u.%u\n",
-    netif->name[0], netif->name[1],
-    ip4_addr1(&netif->ip_addr),
-    ip4_addr2(&netif->ip_addr),
-    ip4_addr3(&netif->ip_addr),
-    ip4_addr4(&netif->ip_addr)));
-}
-
-void
-netif_set_gw(struct netif *netif, struct ip_addr *gw)
-{
-  ip_addr_set(&(netif->gw), gw);
-  LWIP_DEBUGF(NETIF_DEBUG | DBG_TRACE | DBG_STATE | 3, ("netif: GW address of interface %c%c set to %u.%u.%u.%u\n",
-    netif->name[0], netif->name[1],
-    ip4_addr1(&netif->gw),
-    ip4_addr2(&netif->gw),
-    ip4_addr3(&netif->gw),
-    ip4_addr4(&netif->gw)));
-}
-
-void
-netif_set_netmask(struct netif *netif, struct ip_addr *netmask)
-{
-  ip_addr_set(&(netif->netmask), netmask);
-  LWIP_DEBUGF(NETIF_DEBUG | DBG_TRACE | DBG_STATE | 3, ("netif: netmask of interface %c%c set to %u.%u.%u.%u\n",
-    netif->name[0], netif->name[1],
-    ip4_addr1(&netif->netmask),
-    ip4_addr2(&netif->netmask),
-    ip4_addr3(&netif->netmask),
-    ip4_addr4(&netif->netmask)));
-}
-
-void
-netif_set_default(struct netif *netif)
-{
-  netif_default = netif;
-  LWIP_DEBUGF(NETIF_DEBUG, ("netif: setting default interface %c%c\n",
-           netif ? netif->name[0] : '\'', netif ? netif->name[1] : '\''));
-}
-
-/**
- * Bring an interface up, available for processing
- * traffic.
- * 
- * @note: Enabling DHCP on a down interface will make it come
- * up once configured.
- * 
- * @see dhcp_start()
- */ 
-void netif_set_up(struct netif *netif)
-{
-  netif->flags |= NETIF_FLAG_UP;
-}
-
-/**
- * Ask if an interface is up
- */ 
-u8_t netif_is_up(struct netif *netif)
-{
-  return (netif->flags & NETIF_FLAG_UP)?1:0;
-}
-
-/**
- * Bring an interface down, disabling any traffic processing.
- *
- * @note: Enabling DHCP on a down interface will make it come
- * up once configured.
- * 
- * @see dhcp_start()
- */ 
-void netif_set_down(struct netif *netif)
-{
-  netif->flags &= ~NETIF_FLAG_UP;
-}
-
-void
-netif_init(void)
-{
-  netif_list = netif_default = NULL;
-}
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/pbuf.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/pbuf.c
deleted file mode 100644
index ad929c6b5..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/pbuf.c
+++ /dev/null
@@ -1,962 +0,0 @@
-/**
- * @file
- * Packet buffer management
- *
- * Packets are built from the pbuf data structure. It supports dynamic
- * memory allocation for packet contents or can reference externally
- * managed packet contents both in RAM and ROM. Quick allocation for
- * incoming packets is provided through pools with fixed sized pbufs.
- *
- * A packet may span over multiple pbufs, chained as a singly linked
- * list. This is called a "pbuf chain".
- *
- * Multiple packets may be queued, also using this singly linked list.
- * This is called a "packet queue".
- * 
- * So, a packet queue consists of one or more pbuf chains, each of
- * which consist of one or more pbufs. Currently, queues are only
- * supported in a limited section of lwIP, this is the etharp queueing
- * code. Outside of this section no packet queues are supported yet.
- * 
- * The differences between a pbuf chain and a packet queue are very
- * precise but subtle. 
- *
- * The last pbuf of a packet has a ->tot_len field that equals the
- * ->len field. It can be found by traversing the list. If the last
- * pbuf of a packet has a ->next field other than NULL, more packets
- * are on the queue.
- *
- * Therefore, looping through a pbuf of a single packet, has an
- * loop end condition (tot_len == p->len), NOT (next == NULL).
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels 
- *
- */
-
-#include "lwip/opt.h"
-
-#include "lwip/stats.h"
-
-#include "lwip/def.h"
-#include "lwip/mem.h"
-#include "lwip/memp.h"
-#include "lwip/pbuf.h"
-
-#include "lwip/sys.h"
-
-#include "arch/perf.h"
-
-#include 
-
-static u8_t pbuf_pool_memory[(PBUF_POOL_SIZE * MEM_ALIGN_SIZE(PBUF_POOL_BUFSIZE + sizeof(struct pbuf)))];
-
-#if !SYS_LIGHTWEIGHT_PROT
-static volatile u8_t pbuf_pool_free_lock, pbuf_pool_alloc_lock;
-static sys_sem_t pbuf_pool_free_sem;
-#endif
-
-static struct pbuf *pbuf_pool = NULL;
-
-/**
- * Initializes the pbuf module.
- *
- * A large part of memory is allocated for holding the pool of pbufs.
- * The size of the individual pbufs in the pool is given by the size
- * parameter, and the number of pbufs in the pool by the num parameter.
- *
- * After the memory has been allocated, the pbufs are set up. The
- * ->next pointer in each pbuf is set up to point to the next pbuf in
- * the pool.
- *
- */
-void
-pbuf_init(void)
-{
-  struct pbuf *p, *q = NULL;
-  u16_t i;
-
-  pbuf_pool = (struct pbuf *)&pbuf_pool_memory[0];
-  LWIP_ASSERT("pbuf_init: pool aligned", (mem_ptr_t)pbuf_pool % MEM_ALIGNMENT == 0);
-
-#if PBUF_STATS
-  lwip_stats.pbuf.avail = PBUF_POOL_SIZE;
-#endif /* PBUF_STATS */
-
-  /* Set up ->next pointers to link the pbufs of the pool together */
-  p = pbuf_pool;
-
-  for(i = 0; i < PBUF_POOL_SIZE; ++i) {
-    p->next = (struct pbuf *)((u8_t *)p + PBUF_POOL_BUFSIZE + sizeof(struct pbuf));
-    p->len = p->tot_len = PBUF_POOL_BUFSIZE;
-    p->payload = MEM_ALIGN((void *)((u8_t *)p + sizeof(struct pbuf)));
-    p->flags = PBUF_FLAG_POOL;
-    q = p;
-    p = p->next;
-  }
-
-  /* The ->next pointer of last pbuf is NULL to indicate that there
-     are no more pbufs in the pool */
-  q->next = NULL;
-
-#if !SYS_LIGHTWEIGHT_PROT
-  pbuf_pool_alloc_lock = 0;
-  pbuf_pool_free_lock = 0;
-  pbuf_pool_free_sem = sys_sem_new(1);
-#endif
-}
-
-/**
- * @internal only called from pbuf_alloc()
- */
-static struct pbuf *
-pbuf_pool_alloc(void)
-{
-  struct pbuf *p = NULL;
-
-  SYS_ARCH_DECL_PROTECT(old_level);
-  SYS_ARCH_PROTECT(old_level);
-
-#if !SYS_LIGHTWEIGHT_PROT
-  /* Next, check the actual pbuf pool, but if the pool is locked, we
-     pretend to be out of buffers and return NULL. */
-  if (pbuf_pool_free_lock) {
-#if PBUF_STATS
-    ++lwip_stats.pbuf.alloc_locked;
-#endif /* PBUF_STATS */
-    return NULL;
-  }
-  pbuf_pool_alloc_lock = 1;
-  if (!pbuf_pool_free_lock) {
-#endif /* SYS_LIGHTWEIGHT_PROT */
-    p = pbuf_pool;
-    if (p) {
-      pbuf_pool = p->next;
-    }
-#if !SYS_LIGHTWEIGHT_PROT
-#if PBUF_STATS
-  } else {
-    ++lwip_stats.pbuf.alloc_locked;
-#endif /* PBUF_STATS */
-  }
-  pbuf_pool_alloc_lock = 0;
-#endif /* SYS_LIGHTWEIGHT_PROT */
-
-#if PBUF_STATS
-  if (p != NULL) {
-    ++lwip_stats.pbuf.used;
-    if (lwip_stats.pbuf.used > lwip_stats.pbuf.max) {
-      lwip_stats.pbuf.max = lwip_stats.pbuf.used;
-    }
-  }
-#endif /* PBUF_STATS */
-
-  SYS_ARCH_UNPROTECT(old_level);
-  return p;
-}
-
-
-/**
- * Allocates a pbuf of the given type (possibly a chain for PBUF_POOL type).
- *
- * The actual memory allocated for the pbuf is determined by the
- * layer at which the pbuf is allocated and the requested size
- * (from the size parameter).
- *
- * @param flag this parameter decides how and where the pbuf
- * should be allocated as follows:
- *
- * - PBUF_RAM: buffer memory for pbuf is allocated as one large
- *             chunk. This includes protocol headers as well.
- * - PBUF_ROM: no buffer memory is allocated for the pbuf, even for
- *             protocol headers. Additional headers must be prepended
- *             by allocating another pbuf and chain in to the front of
- *             the ROM pbuf. It is assumed that the memory used is really
- *             similar to ROM in that it is immutable and will not be
- *             changed. Memory which is dynamic should generally not
- *             be attached to PBUF_ROM pbufs. Use PBUF_REF instead.
- * - PBUF_REF: no buffer memory is allocated for the pbuf, even for
- *             protocol headers. It is assumed that the pbuf is only
- *             being used in a single thread. If the pbuf gets queued,
- *             then pbuf_take should be called to copy the buffer.
- * - PBUF_POOL: the pbuf is allocated as a pbuf chain, with pbufs from
- *              the pbuf pool that is allocated during pbuf_init().
- *
- * @return the allocated pbuf. If multiple pbufs where allocated, this
- * is the first pbuf of a pbuf chain.
- */
-struct pbuf *
-pbuf_alloc(pbuf_layer l, u16_t length, pbuf_flag flag)
-{
-  struct pbuf *p, *q, *r;
-  u16_t offset;
-  s32_t rem_len; /* remaining length */
-  LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_alloc(length=%u)\n", length));
-
-  /* determine header offset */
-  offset = 0;
-  switch (l) {
-  case PBUF_TRANSPORT:
-    /* add room for transport (often TCP) layer header */
-    offset += PBUF_TRANSPORT_HLEN;
-    /* FALLTHROUGH */
-  case PBUF_IP:
-    /* add room for IP layer header */
-    offset += PBUF_IP_HLEN;
-    /* FALLTHROUGH */
-  case PBUF_LINK:
-    /* add room for link layer header */
-    offset += PBUF_LINK_HLEN;
-    break;
-  case PBUF_RAW:
-    break;
-  default:
-    LWIP_ASSERT("pbuf_alloc: bad pbuf layer", 0);
-    return NULL;
-  }
-
-  switch (flag) {
-  case PBUF_POOL:
-    /* allocate head of pbuf chain into p */
-    p = pbuf_pool_alloc();
-    LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_alloc: allocated pbuf %p\n", (void *)p));
-    if (p == NULL) {
-#if PBUF_STATS
-      ++lwip_stats.pbuf.err;
-#endif /* PBUF_STATS */
-      return NULL;
-    }
-    p->next = NULL;
-
-    /* make the payload pointer point 'offset' bytes into pbuf data memory */
-    p->payload = MEM_ALIGN((void *)((u8_t *)p + (sizeof(struct pbuf) + offset)));
-    LWIP_ASSERT("pbuf_alloc: pbuf p->payload properly aligned",
-            ((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0);
-    /* the total length of the pbuf chain is the requested size */
-    p->tot_len = length;
-    /* set the length of the first pbuf in the chain */
-    p->len = length > PBUF_POOL_BUFSIZE - offset? PBUF_POOL_BUFSIZE - offset: length;
-    /* set reference count (needed here in case we fail) */
-    p->ref = 1;
-
-    /* now allocate the tail of the pbuf chain */
-
-    /* remember first pbuf for linkage in next iteration */
-    r = p;
-    /* remaining length to be allocated */
-    rem_len = length - p->len;
-    /* any remaining pbufs to be allocated? */
-    while (rem_len > 0) {
-      q = pbuf_pool_alloc();
-      if (q == NULL) {
-       LWIP_DEBUGF(PBUF_DEBUG | 2, ("pbuf_alloc: Out of pbufs in pool.\n"));
-#if PBUF_STATS
-        ++lwip_stats.pbuf.err;
-#endif /* PBUF_STATS */
-        /* free chain so far allocated */
-        pbuf_free(p);
-        /* bail out unsuccesfully */
-        return NULL;
-      }
-      q->next = NULL;
-      /* make previous pbuf point to this pbuf */
-      r->next = q;
-      /* set total length of this pbuf and next in chain */
-      q->tot_len = rem_len;
-      /* this pbuf length is pool size, unless smaller sized tail */
-      q->len = rem_len > PBUF_POOL_BUFSIZE? PBUF_POOL_BUFSIZE: rem_len;
-      q->payload = (void *)((u8_t *)q + sizeof(struct pbuf));
-      LWIP_ASSERT("pbuf_alloc: pbuf q->payload properly aligned",
-              ((mem_ptr_t)q->payload % MEM_ALIGNMENT) == 0);
-      q->ref = 1;
-      /* calculate remaining length to be allocated */
-      rem_len -= q->len;
-      /* remember this pbuf for linkage in next iteration */
-      r = q;
-    }
-    /* end of chain */
-    /*r->next = NULL;*/
-
-    break;
-  case PBUF_RAM:
-    /* If pbuf is to be allocated in RAM, allocate memory for it. */
-    p = mem_malloc(MEM_ALIGN_SIZE(sizeof(struct pbuf) + offset) + MEM_ALIGN_SIZE(length));
-    if (p == NULL) {
-      return NULL;
-    }
-    /* Set up internal structure of the pbuf. */
-    p->payload = MEM_ALIGN((void *)((u8_t *)p + sizeof(struct pbuf) + offset));
-    p->len = p->tot_len = length;
-    p->next = NULL;
-    p->flags = PBUF_FLAG_RAM;
-
-    LWIP_ASSERT("pbuf_alloc: pbuf->payload properly aligned",
-           ((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0);
-    break;
-  /* pbuf references existing (non-volatile static constant) ROM payload? */
-  case PBUF_ROM:
-  /* pbuf references existing (externally allocated) RAM payload? */
-  case PBUF_REF:
-    /* only allocate memory for the pbuf structure */
-    p = memp_malloc(MEMP_PBUF);
-    if (p == NULL) {
-      LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_alloc: Could not allocate MEMP_PBUF for PBUF_%s.\n", flag == PBUF_ROM?"ROM":"REF"));
-      return NULL;
-    }
-    /* caller must set this field properly, afterwards */
-    p->payload = NULL;
-    p->len = p->tot_len = length;
-    p->next = NULL;
-    p->flags = (flag == PBUF_ROM? PBUF_FLAG_ROM: PBUF_FLAG_REF);
-    break;
-  default:
-    LWIP_ASSERT("pbuf_alloc: erroneous flag", 0);
-    return NULL;
-  }
-  /* set reference count */
-  p->ref = 1;
-  LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_alloc(length=%u) == %p\n", length, (void *)p));
-  return p;
-}
-
-
-#if PBUF_STATS
-#define DEC_PBUF_STATS do { --lwip_stats.pbuf.used; } while (0)
-#else /* PBUF_STATS */
-#define DEC_PBUF_STATS
-#endif /* PBUF_STATS */
-
-#define PBUF_POOL_FAST_FREE(p)  do {                                    \
-                                  p->next = pbuf_pool;                  \
-                                  pbuf_pool = p;                        \
-                                  DEC_PBUF_STATS;                       \
-                                } while (0)
-
-#if SYS_LIGHTWEIGHT_PROT
-#define PBUF_POOL_FREE(p)  do {                                         \
-                                SYS_ARCH_DECL_PROTECT(old_level);       \
-                                SYS_ARCH_PROTECT(old_level);            \
-                                PBUF_POOL_FAST_FREE(p);                 \
-                                SYS_ARCH_UNPROTECT(old_level);          \
-                               } while (0)
-#else /* SYS_LIGHTWEIGHT_PROT */
-#define PBUF_POOL_FREE(p)  do {                                         \
-                             sys_sem_wait(pbuf_pool_free_sem);          \
-                             PBUF_POOL_FAST_FREE(p);                    \
-                             sys_sem_signal(pbuf_pool_free_sem);        \
-                           } while (0)
-#endif /* SYS_LIGHTWEIGHT_PROT */
-
-/**
- * Shrink a pbuf chain to a desired length.
- *
- * @param p pbuf to shrink.
- * @param new_len desired new length of pbuf chain
- *
- * Depending on the desired length, the first few pbufs in a chain might
- * be skipped and left unchanged. The new last pbuf in the chain will be
- * resized, and any remaining pbufs will be freed.
- *
- * @note If the pbuf is ROM/REF, only the ->tot_len and ->len fields are adjusted.
- * @note May not be called on a packet queue.
- *
- * @bug Cannot grow the size of a pbuf (chain) (yet).
- */
-void
-pbuf_realloc(struct pbuf *p, u16_t new_len)
-{
-  struct pbuf *q;
-  u16_t rem_len; /* remaining length */
-  s16_t grow;
-
-  LWIP_ASSERT("pbuf_realloc: sane p->flags", p->flags == PBUF_FLAG_POOL ||
-              p->flags == PBUF_FLAG_ROM ||
-              p->flags == PBUF_FLAG_RAM ||
-              p->flags == PBUF_FLAG_REF);
-
-  /* desired length larger than current length? */
-  if (new_len >= p->tot_len) {
-    /* enlarging not yet supported */
-    return;
-  }
-
-  /* the pbuf chain grows by (new_len - p->tot_len) bytes
-   * (which may be negative in case of shrinking) */
-  grow = new_len - p->tot_len;
-
-  /* first, step over any pbufs that should remain in the chain */
-  rem_len = new_len;
-  q = p;
-  /* should this pbuf be kept? */
-  while (rem_len > q->len) {
-    /* decrease remaining length by pbuf length */
-    rem_len -= q->len;
-    /* decrease total length indicator */
-    q->tot_len += grow;
-    /* proceed to next pbuf in chain */
-    q = q->next;
-  }
-  /* we have now reached the new last pbuf (in q) */
-  /* rem_len == desired length for pbuf q */
-
-  /* shrink allocated memory for PBUF_RAM */
-  /* (other types merely adjust their length fields */
-  if ((q->flags == PBUF_FLAG_RAM) && (rem_len != q->len)) {
-    /* reallocate and adjust the length of the pbuf that will be split */
-    mem_realloc(q, (u8_t *)q->payload - (u8_t *)q + rem_len);
-  }
-  /* adjust length fields for new last pbuf */
-  q->len = rem_len;
-  q->tot_len = q->len;
-
-  /* any remaining pbufs in chain? */
-  if (q->next != NULL) {
-    /* free remaining pbufs in chain */
-    pbuf_free(q->next);
-  }
-  /* q is last packet in chain */
-  q->next = NULL;
-
-}
-
-/**
- * Adjusts the payload pointer to hide or reveal headers in the payload.
- *
- * Adjusts the ->payload pointer so that space for a header
- * (dis)appears in the pbuf payload.
- *
- * The ->payload, ->tot_len and ->len fields are adjusted.
- *
- * @param hdr_size_inc Number of bytes to increment header size which
- * increases the size of the pbuf. New space is on the front.
- * (Using a negative value decreases the header size.)
- * If hdr_size_inc is 0, this function does nothing and returns succesful.
- *
- * PBUF_ROM and PBUF_REF type buffers cannot have their sizes increased, so
- * the call will fail. A check is made that the increase in header size does
- * not move the payload pointer in front of the start of the buffer.
- * @return non-zero on failure, zero on success.
- *
- */
-u8_t
-pbuf_header(struct pbuf *p, s16_t header_size_increment)
-{
-  void *payload;
-
-  LWIP_ASSERT("p != NULL", p != NULL);
-  if ((header_size_increment == 0) || (p == NULL)) return 0;
- 
-  /* remember current payload pointer */
-  payload = p->payload;
-
-  /* pbuf types containing payloads? */
-  if (p->flags == PBUF_FLAG_RAM || p->flags == PBUF_FLAG_POOL) {
-    /* set new payload pointer */
-    p->payload = (u8_t *)p->payload - header_size_increment;
-    /* boundary check fails? */
-    if ((u8_t *)p->payload < (u8_t *)p + sizeof(struct pbuf)) {
-      LWIP_DEBUGF( PBUF_DEBUG | 2, ("pbuf_header: failed as %p < %p (not enough space for new header size)\n",
-        (void *)p->payload,
-        (void *)(p + 1)));\
-      /* restore old payload pointer */
-      p->payload = payload;
-      /* bail out unsuccesfully */
-      return 1;
-    }
-  /* pbuf types refering to external payloads? */
-  } else if (p->flags == PBUF_FLAG_REF || p->flags == PBUF_FLAG_ROM) {
-    /* hide a header in the payload? */
-    if ((header_size_increment < 0) && (header_size_increment - p->len <= 0)) {
-      /* increase payload pointer */
-      p->payload = (u8_t *)p->payload - header_size_increment;
-    } else {
-      /* cannot expand payload to front (yet!)
-       * bail out unsuccesfully */
-      return 1;
-    }
-  }
-  /* modify pbuf length fields */
-  p->len += header_size_increment;
-  p->tot_len += header_size_increment;
-
-  LWIP_DEBUGF( PBUF_DEBUG, ("pbuf_header: old %p new %p (%d)\n",
-    (void *)payload, (void *)p->payload, header_size_increment));
-
-  return 0;
-}
-
-/**
- * Dereference a pbuf chain or queue and deallocate any no-longer-used
- * pbufs at the head of this chain or queue.
- *
- * Decrements the pbuf reference count. If it reaches zero, the pbuf is
- * deallocated.
- *
- * For a pbuf chain, this is repeated for each pbuf in the chain,
- * up to the first pbuf which has a non-zero reference count after
- * decrementing. So, when all reference counts are one, the whole
- * chain is free'd.
- *
- * @param pbuf The pbuf (chain) to be dereferenced.
- *
- * @return the number of pbufs that were de-allocated
- * from the head of the chain.
- *
- * @note MUST NOT be called on a packet queue (Not verified to work yet).
- * @note the reference counter of a pbuf equals the number of pointers
- * that refer to the pbuf (or into the pbuf).
- *
- * @internal examples:
- *
- * Assuming existing chains a->b->c with the following reference
- * counts, calling pbuf_free(a) results in:
- * 
- * 1->2->3 becomes ...1->3
- * 3->3->3 becomes 2->3->3
- * 1->1->2 becomes ......1
- * 2->1->1 becomes 1->1->1
- * 1->1->1 becomes .......
- *
- */
-u8_t
-pbuf_free(struct pbuf *p)
-{
-  struct pbuf *q;
-  u8_t count;
-  SYS_ARCH_DECL_PROTECT(old_level);
-
-  LWIP_ASSERT("p != NULL", p != NULL);
-  /* if assertions are disabled, proceed with debug output */
-  if (p == NULL) {
-    LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_free(p == NULL) was called.\n"));
-    return 0;
-  }
-  LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_free(%p)\n", (void *)p));
-
-  PERF_START;
-
-  LWIP_ASSERT("pbuf_free: sane flags",
-    p->flags == PBUF_FLAG_RAM || p->flags == PBUF_FLAG_ROM ||
-    p->flags == PBUF_FLAG_REF || p->flags == PBUF_FLAG_POOL);
-
-  count = 0;
-  /* Since decrementing ref cannot be guaranteed to be a single machine operation
-   * we must protect it. Also, the later test of ref must be protected.
-   */
-  SYS_ARCH_PROTECT(old_level);
-  /* de-allocate all consecutive pbufs from the head of the chain that
-   * obtain a zero reference count after decrementing*/
-  while (p != NULL) {
-    /* all pbufs in a chain are referenced at least once */
-    LWIP_ASSERT("pbuf_free: p->ref > 0", p->ref > 0);
-    /* decrease reference count (number of pointers to pbuf) */
-    p->ref--;
-    /* this pbuf is no longer referenced to? */
-    if (p->ref == 0) {
-      /* remember next pbuf in chain for next iteration */
-      q = p->next;
-      LWIP_DEBUGF( PBUF_DEBUG | 2, ("pbuf_free: deallocating %p\n", (void *)p));
-      /* is this a pbuf from the pool? */
-      if (p->flags == PBUF_FLAG_POOL) {
-        p->len = p->tot_len = PBUF_POOL_BUFSIZE;
-        p->payload = (void *)((u8_t *)p + sizeof(struct pbuf));
-        PBUF_POOL_FREE(p);
-      /* is this a ROM or RAM referencing pbuf? */
-      } else if (p->flags == PBUF_FLAG_ROM || p->flags == PBUF_FLAG_REF) {
-        memp_free(MEMP_PBUF, p);
-      /* p->flags == PBUF_FLAG_RAM */
-      } else {
-        mem_free(p);
-      }
-      count++;
-      /* proceed to next pbuf */
-      p = q;
-    /* p->ref > 0, this pbuf is still referenced to */
-    /* (and so the remaining pbufs in chain as well) */
-    } else {
-      LWIP_DEBUGF( PBUF_DEBUG | 2, ("pbuf_free: %p has ref %u, ending here.\n", (void *)p, (unsigned int)p->ref));
-      /* stop walking through the chain */
-      p = NULL;
-    }
-  }
-  SYS_ARCH_UNPROTECT(old_level);
-  PERF_STOP("pbuf_free");
-  /* return number of de-allocated pbufs */
-  return count;
-}
-
-/**
- * Count number of pbufs in a chain
- *
- * @param p first pbuf of chain
- * @return the number of pbufs in a chain
- */
-
-u8_t
-pbuf_clen(struct pbuf *p)
-{
-  u8_t len;
-
-  len = 0;
-  while (p != NULL) {
-    ++len;
-    p = p->next;
-  }
-  return len;
-}
-
-/**
- * Increment the reference count of the pbuf.
- *
- * @param p pbuf to increase reference counter of
- *
- */
-void
-pbuf_ref(struct pbuf *p)
-{
-  SYS_ARCH_DECL_PROTECT(old_level);
-  /* pbuf given? */
-  if (p != NULL) {
-    SYS_ARCH_PROTECT(old_level);
-    ++(p->ref);
-    SYS_ARCH_UNPROTECT(old_level);
-  }
-}
-
-/**
- * Concatenate two pbufs (each may be a pbuf chain) and take over
- * the caller's reference of the tail pbuf.
- * 
- * @note The caller MAY NOT reference the tail pbuf afterwards.
- * Use pbuf_chain() for that purpose.
- * 
- * @see pbuf_chain()
- */
-
-void
-pbuf_cat(struct pbuf *h, struct pbuf *t)
-{
-  struct pbuf *p;
-
-  LWIP_ASSERT("h != NULL (programmer violates API)", h != NULL);
-  LWIP_ASSERT("t != NULL (programmer violates API)", t != NULL);
-  if ((h == NULL) || (t == NULL)) return;
-
-  /* proceed to last pbuf of chain */
-  for (p = h; p->next != NULL; p = p->next) {
-    /* add total length of second chain to all totals of first chain */
-    p->tot_len += t->tot_len;
-  }
-  /* { p is last pbuf of first h chain, p->next == NULL } */
-  LWIP_ASSERT("p->tot_len == p->len (of last pbuf in chain)", p->tot_len == p->len);
-  LWIP_ASSERT("p->next == NULL", p->next == NULL);
-  /* add total length of second chain to last pbuf total of first chain */
-  p->tot_len += t->tot_len;
-  /* chain last pbuf of head (p) with first of tail (t) */
-  p->next = t;
-  /* p->next now references t, but the caller will drop its reference to t,
-   * so netto there is no change to the reference count of t.
-   */
-}
-
-/**
- * Chain two pbufs (or pbuf chains) together.
- * 
- * The caller MUST call pbuf_free(t) once it has stopped
- * using it. Use pbuf_cat() instead if you no longer use t.
- * 
- * @param h head pbuf (chain)
- * @param t tail pbuf (chain)
- * @note The pbufs MUST belong to the same packet.
- * @note MAY NOT be called on a packet queue.
- *
- * The ->tot_len fields of all pbufs of the head chain are adjusted.
- * The ->next field of the last pbuf of the head chain is adjusted.
- * The ->ref field of the first pbuf of the tail chain is adjusted.
- *
- */
-void
-pbuf_chain(struct pbuf *h, struct pbuf *t)
-{
-  pbuf_cat(h, t);
-  /* t is now referenced by h */
-  pbuf_ref(t);
-  LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, ("pbuf_chain: %p references %p\n", (void *)h, (void *)t));
-}
-
-/* For packet queueing. Note that queued packets MUST be dequeued first
- * using pbuf_dequeue() before calling other pbuf_() functions. */
-#if ARP_QUEUEING
-/**
- * Add a packet to the end of a queue.
- *
- * @param q pointer to first packet on the queue
- * @param n packet to be queued
- *
- * Both packets MUST be given, and must be different.
- */
-void
-pbuf_queue(struct pbuf *p, struct pbuf *n)
-{
-#if PBUF_DEBUG /* remember head of queue */
-  struct pbuf *q = p;
-#endif
-  /* programmer stupidity checks */
-  LWIP_ASSERT("p == NULL in pbuf_queue: this indicates a programmer error\n", p != NULL);
-  LWIP_ASSERT("n == NULL in pbuf_queue: this indicates a programmer error\n", n != NULL);
-  LWIP_ASSERT("p == n in pbuf_queue: this indicates a programmer error\n", p != n);
-  if ((p == NULL) || (n == NULL) || (p == n)){
-    LWIP_DEBUGF(PBUF_DEBUG | DBG_HALT | 3, ("pbuf_queue: programmer argument error\n"))
-    return;
-  }
-
-  /* iterate through all packets on queue */
-  while (p->next != NULL) {
-/* be very picky about pbuf chain correctness */
-#if PBUF_DEBUG
-    /* iterate through all pbufs in packet */
-    while (p->tot_len != p->len) {
-      /* make sure invariant condition holds */
-      LWIP_ASSERT("p->len < p->tot_len", p->len < p->tot_len);
-      /* make sure each packet is complete */
-      LWIP_ASSERT("p->next != NULL", p->next != NULL);
-      p = p->next;
-      /* { p->tot_len == p->len => p is last pbuf of a packet } */
-    }
-    /* { p is last pbuf of a packet } */
-    /* proceed to next packet on queue */
-#endif
-    /* proceed to next pbuf */
-    if (p->next != NULL) p = p->next;
-  }
-  /* { p->tot_len == p->len and p->next == NULL } ==>
-   * { p is last pbuf of last packet on queue } */
-  /* chain last pbuf of queue with n */
-  p->next = n;
-  /* n is now referenced to by the (packet p in the) queue */
-  pbuf_ref(n);
-#if PBUF_DEBUG
-  LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2,
-    ("pbuf_queue: newly queued packet %p sits after packet %p in queue %p\n",
-    (void *)n, (void *)p, (void *)q));
-#endif
-}
-
-/**
- * Remove a packet from the head of a queue.
- *
- * The caller MUST reference the remainder of the queue (as returned). The
- * caller MUST NOT call pbuf_ref() as it implicitly takes over the reference
- * from p.
- * 
- * @param p pointer to first packet on the queue which will be dequeued.
- * @return first packet on the remaining queue (NULL if no further packets).
- *
- */
-struct pbuf *
-pbuf_dequeue(struct pbuf *p)
-{
-  struct pbuf *q;
-  LWIP_ASSERT("p != NULL", p != NULL);
-
-  /* iterate through all pbufs in packet p */
-  while (p->tot_len != p->len) {
-    /* make sure invariant condition holds */
-    LWIP_ASSERT("p->len < p->tot_len", p->len < p->tot_len);
-    /* make sure each packet is complete */
-    LWIP_ASSERT("p->next != NULL", p->next != NULL);
-    p = p->next;
-  }
-  /* { p->tot_len == p->len } => p is the last pbuf of the first packet */
-  /* remember next packet on queue in q */
-  q = p->next;
-  /* dequeue packet p from queue */
-  p->next = NULL;
-  /* any next packet on queue? */
-  if (q != NULL) {
-    /* although q is no longer referenced by p, it MUST be referenced by
-     * the caller, who is maintaining this packet queue. So, we do not call
-     * pbuf_free(q) here, resulting in an implicit pbuf_ref(q) for the caller. */
-    LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, ("pbuf_dequeue: first remaining packet on queue is %p\n", (void *)q));
-  } else {
-    LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, ("pbuf_dequeue: no further packets on queue\n"));
-  }
-  return q;
-}
-#endif
-
-/**
- *
- * Create PBUF_POOL (or PBUF_RAM) copies of PBUF_REF pbufs.
- *
- * Used to queue packets on behalf of the lwIP stack, such as
- * ARP based queueing.
- *
- * Go through a pbuf chain and replace any PBUF_REF buffers
- * with PBUF_POOL (or PBUF_RAM) pbufs, each taking a copy of
- * the referenced data.
- *
- * @note You MUST explicitly use p = pbuf_take(p);
- * The pbuf you give as argument, may have been replaced
- * by a (differently located) copy through pbuf_take()!
- *
- * @note Any replaced pbufs will be freed through pbuf_free().
- * This may deallocate them if they become no longer referenced.
- *
- * @param p Head of pbuf chain to process
- *
- * @return Pointer to head of pbuf chain
- */
-struct pbuf *
-pbuf_take(struct pbuf *p)
-{
-  struct pbuf *q , *prev, *head;
-  LWIP_ASSERT("pbuf_take: p != NULL\n", p != NULL);
-  LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_take(%p)\n", (void*)p));
-
-  prev = NULL;
-  head = p;
-  /* iterate through pbuf chain */
-  do
-  {
-    /* pbuf is of type PBUF_REF? */
-    if (p->flags == PBUF_FLAG_REF) {
-      LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE, ("pbuf_take: encountered PBUF_REF %p\n", (void *)p));
-      /* allocate a pbuf (w/ payload) fully in RAM */
-      /* PBUF_POOL buffers are faster if we can use them */
-      if (p->len <= PBUF_POOL_BUFSIZE) {
-        q = pbuf_alloc(PBUF_RAW, p->len, PBUF_POOL);
-        if (q == NULL) {
-          LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_take: Could not allocate PBUF_POOL\n"));
-        }
-      } else {
-        /* no replacement pbuf yet */
-        q = NULL;
-        LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_take: PBUF_POOL too small to replace PBUF_REF\n"));
-      }
-      /* no (large enough) PBUF_POOL was available? retry with PBUF_RAM */
-      if (q == NULL) {
-        q = pbuf_alloc(PBUF_RAW, p->len, PBUF_RAM);
-        if (q == NULL) {
-          LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_take: Could not allocate PBUF_RAM\n"));
-        }
-      }
-      /* replacement pbuf could be allocated? */
-      if (q != NULL)
-      {
-        /* copy p to q */
-        /* copy successor */
-        q->next = p->next;
-        /* remove linkage from original pbuf */
-        p->next = NULL;
-        /* remove linkage to original pbuf */
-        if (prev != NULL) {
-          /* prev->next == p at this point */
-          LWIP_ASSERT("prev->next == p", prev->next == p);
-          /* break chain and insert new pbuf instead */
-          prev->next = q;
-        /* prev == NULL, so we replaced the head pbuf of the chain */
-        } else {
-          head = q;
-        }
-        /* copy pbuf payload */
-        memcpy(q->payload, p->payload, p->len);
-        q->tot_len = p->tot_len;
-        q->len = p->len;
-        /* in case p was the first pbuf, it is no longer refered to by
-         * our caller, as the caller MUST do p = pbuf_take(p);
-         * in case p was not the first pbuf, it is no longer refered to
-         * by prev. we can safely free the pbuf here.
-         * (note that we have set p->next to NULL already so that
-         * we will not free the rest of the chain by accident.)
-         */
-        pbuf_free(p);
-        /* do not copy ref, since someone else might be using the old buffer */
-        LWIP_DEBUGF(PBUF_DEBUG, ("pbuf_take: replaced PBUF_REF %p with %p\n", (void *)p, (void *)q));
-        p = q;
-      } else {
-        /* deallocate chain */
-        pbuf_free(head);
-        LWIP_DEBUGF(PBUF_DEBUG | 2, ("pbuf_take: failed to allocate replacement pbuf for %p\n", (void *)p));
-        return NULL;
-      }
-    /* p->flags != PBUF_FLAG_REF */
-    } else {
-      LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 1, ("pbuf_take: skipping pbuf not of type PBUF_REF\n"));
-    }
-    /* remember this pbuf */
-    prev = p;
-    /* proceed to next pbuf in original chain */
-    p = p->next;
-  } while (p);
-  LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 1, ("pbuf_take: end of chain reached.\n"));
-
-  return head;
-}
-
-/**
- * Dechains the first pbuf from its succeeding pbufs in the chain.
- *
- * Makes p->tot_len field equal to p->len.
- * @param p pbuf to dechain
- * @return remainder of the pbuf chain, or NULL if it was de-allocated.
- * @note May not be called on a packet queue.
- */
-struct pbuf *
-pbuf_dechain(struct pbuf *p)
-{
-  struct pbuf *q;
-  u8_t tail_gone = 1;
-  /* tail */
-  q = p->next;
-  /* pbuf has successor in chain? */
-  if (q != NULL) {
-    /* assert tot_len invariant: (p->tot_len == p->len + (p->next? p->next->tot_len: 0) */
-    LWIP_ASSERT("p->tot_len == p->len + q->tot_len", q->tot_len == p->tot_len - p->len);
-    /* enforce invariant if assertion is disabled */
-    q->tot_len = p->tot_len - p->len;
-    /* decouple pbuf from remainder */
-    p->next = NULL;
-    /* total length of pbuf p is its own length only */
-    p->tot_len = p->len;
-    /* q is no longer referenced by p, free it */
-    LWIP_DEBUGF(PBUF_DEBUG | DBG_STATE, ("pbuf_dechain: unreferencing %p\n", (void *)q));
-    tail_gone = pbuf_free(q);
-    if (tail_gone > 0) {
-      LWIP_DEBUGF(PBUF_DEBUG | DBG_STATE,
-                  ("pbuf_dechain: deallocated %p (as it is no longer referenced)\n", (void *)q));
-    }
-    /* return remaining tail or NULL if deallocated */
-  }
-  /* assert tot_len invariant: (p->tot_len == p->len + (p->next? p->next->tot_len: 0) */
-  LWIP_ASSERT("p->tot_len == p->len", p->tot_len == p->len);
-  return (tail_gone > 0? NULL: q);
-}
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/raw.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/raw.c
deleted file mode 100644
index 5f1f5b24e..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/raw.c
+++ /dev/null
@@ -1,328 +0,0 @@
-/**
- * @file
- * 
- * Implementation of raw protocol PCBs for low-level handling of
- * different types of protocols besides (or overriding) those
- * already available in lwIP.
- *
- */
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels 
- *
- */
-
-#include 
-
-#include "lwip/opt.h"
-
-#include "lwip/def.h"
-#include "lwip/memp.h"
-#include "lwip/inet.h"
-#include "lwip/ip_addr.h"
-#include "lwip/netif.h"
-#include "lwip/raw.h"
-
-#include "lwip/stats.h"
-
-#include "arch/perf.h"
-#include "lwip/snmp.h"
-
-#if LWIP_RAW
-
-/** The list of RAW PCBs */
-static struct raw_pcb *raw_pcbs = NULL;
-
-void
-raw_init(void)
-{
-  raw_pcbs = NULL;
-}
-
-/**
- * Determine if in incoming IP packet is covered by a RAW PCB
- * and if so, pass it to a user-provided receive callback function.
- *
- * Given an incoming IP datagram (as a chain of pbufs) this function
- * finds a corresponding RAW PCB and calls the corresponding receive
- * callback function.
- *
- * @param pbuf pbuf to be demultiplexed to a RAW PCB.
- * @param netif network interface on which the datagram was received.
- * @Return - 1 if the packet has been eaten by a RAW PCB receive
- *           callback function. The caller MAY NOT not reference the
- *           packet any longer, and MAY NOT call pbuf_free().
- * @return - 0 if packet is not eaten (pbuf is still referenced by the
- *           caller).
- *
- */
-u8_t
-raw_input(struct pbuf *p, struct netif *inp)
-{
-  struct raw_pcb *pcb;
-  struct ip_hdr *iphdr;
-  int proto;
-  u8_t eaten = 0;
-
-  ( void ) inp;
-
-  iphdr = p->payload;
-  proto = IPH_PROTO(iphdr);
-
-  pcb = raw_pcbs;
-  /* loop through all raw pcbs until the packet is eaten by one */
-  /* this allows multiple pcbs to match against the packet by design */
-  while ((eaten == 0) && (pcb != NULL)) {
-    if (pcb->protocol == proto) {
-      /* receive callback function available? */
-      if (pcb->recv != NULL) {
-        /* the receive callback function did not eat the packet? */
-        if (pcb->recv(pcb->recv_arg, pcb, p, &(iphdr->src)) != 0)
-        {
-          /* receive function ate the packet */
-          p = NULL;
-          eaten = 1;
-        }
-      }
-      /* no receive callback function was set for this raw PCB */
-      /* drop the packet */
-    }
-    pcb = pcb->next;
-  }
-  return eaten;
-}
-
-/**
- * Bind a RAW PCB.
- *
- * @param pcb RAW PCB to be bound with a local address ipaddr.
- * @param ipaddr local IP address to bind with. Use IP_ADDR_ANY to
- * bind to all local interfaces.
- *
- * @return lwIP error code.
- * - ERR_OK. Successful. No error occured.
- * - ERR_USE. The specified IP address is already bound to by
- * another RAW PCB.
- *
- * @see raw_disconnect()
- */
-err_t
-raw_bind(struct raw_pcb *pcb, struct ip_addr *ipaddr)
-{
-  ip_addr_set(&pcb->local_ip, ipaddr);
-  return ERR_OK;
-}
-
-/**
- * Connect an RAW PCB. This function is required by upper layers
- * of lwip. Using the raw api you could use raw_sendto() instead
- *
- * This will associate the RAW PCB with the remote address.
- *
- * @param pcb RAW PCB to be connected with remote address ipaddr and port.
- * @param ipaddr remote IP address to connect with.
- *
- * @return lwIP error code
- *
- * @see raw_disconnect() and raw_sendto()
- */
-err_t
-raw_connect(struct raw_pcb *pcb, struct ip_addr *ipaddr)
-{
-  ip_addr_set(&pcb->remote_ip, ipaddr);
-  return ERR_OK;
-}
-
-
-/**
- * Set the callback function for received packets that match the
- * raw PCB's protocol and binding. 
- * 
- * The callback function MUST either
- * - eat the packet by calling pbuf_free() and returning non-zero. The
- *   packet will not be passed to other raw PCBs or other protocol layers.
- * - not free the packet, and return zero. The packet will be matched
- *   against further PCBs and/or forwarded to another protocol layers.
- * 
- * @return non-zero if the packet was free()d, zero if the packet remains
- * available for others.
- */
-void
-raw_recv(struct raw_pcb *pcb,
-         u8_t (* recv)(void *arg, struct raw_pcb *upcb, struct pbuf *p,
-                      struct ip_addr *addr),
-         void *recv_arg)
-{
-  /* remember recv() callback and user data */
-  pcb->recv = recv;
-  pcb->recv_arg = recv_arg;
-}
-
-/**
- * Send the raw IP packet to the given address. Note that actually you cannot
- * modify the IP headers (this is inconsistent with the receive callback where
- * you actually get the IP headers), you can only specify the IP payload here.
- * It requires some more changes in lwIP. (there will be a raw_send() function
- * then.)
- *
- * @param pcb the raw pcb which to send
- * @param p the IP payload to send
- * @param ipaddr the destination address of the IP packet
- *
- */
-err_t
-raw_sendto(struct raw_pcb *pcb, struct pbuf *p, struct ip_addr *ipaddr)
-{
-  err_t err;
-  struct netif *netif;
-  struct ip_addr *src_ip;
-  struct pbuf *q; /* q will be sent down the stack */
-  
-  LWIP_DEBUGF(RAW_DEBUG | DBG_TRACE | 3, ("raw_sendto\n"));
-  
-  /* not enough space to add an IP header to first pbuf in given p chain? */
-  if (pbuf_header(p, IP_HLEN)) {
-    /* allocate header in new pbuf */
-    q = pbuf_alloc(PBUF_IP, 0, PBUF_RAM);
-    /* new header pbuf could not be allocated? */
-    if (q == NULL) {
-      LWIP_DEBUGF(RAW_DEBUG | DBG_TRACE | 2, ("raw_sendto: could not allocate header\n"));
-      return ERR_MEM;
-    }
-    /* chain header q in front of given pbuf p */
-    pbuf_chain(q, p);
-    /* { first pbuf q points to header pbuf } */
-    LWIP_DEBUGF(RAW_DEBUG, ("raw_sendto: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p));
-  }  else {
-    /* first pbuf q equals given pbuf */
-    q = p;
-    pbuf_header(q, -IP_HLEN);
-  }
-  
-  if ((netif = ip_route(ipaddr)) == NULL) {
-    LWIP_DEBUGF(RAW_DEBUG | 1, ("raw_sendto: No route to 0x%lx\n", ipaddr->addr));
-#if RAW_STATS
-    /*    ++lwip_stats.raw.rterr;*/
-#endif /* RAW_STATS */
-    /* free any temporary header pbuf allocated by pbuf_header() */
-    if (q != p) {
-      pbuf_free(q);
-    }
-    return ERR_RTE;
-  }
-
-  if (ip_addr_isany(&pcb->local_ip)) {
-    /* use outgoing network interface IP address as source address */
-    src_ip = &(netif->ip_addr);
-  } else {
-    /* use RAW PCB local IP address as source address */
-    src_ip = &(pcb->local_ip);
-  }
-
-  err = ip_output_if (q, src_ip, ipaddr, pcb->ttl, pcb->tos, pcb->protocol, netif);
-
-  /* did we chain a header earlier? */
-  if (q != p) {
-    /* free the header */
-    pbuf_free(q);
-  }
-  return err;
-}
-
-/**
- * Send the raw IP packet to the address given by raw_connect()
- *
- * @param pcb the raw pcb which to send
- * @param p the IP payload to send
- * @param ipaddr the destination address of the IP packet
- *
- */
-err_t
-raw_send(struct raw_pcb *pcb, struct pbuf *p)
-{
-  return raw_sendto(pcb, p, &pcb->remote_ip);
-}
-
-/**
- * Remove an RAW PCB.
- *
- * @param pcb RAW PCB to be removed. The PCB is removed from the list of
- * RAW PCB's and the data structure is freed from memory.
- *
- * @see raw_new()
- */
-void
-raw_remove(struct raw_pcb *pcb)
-{
-  struct raw_pcb *pcb2;
-  /* pcb to be removed is first in list? */
-  if (raw_pcbs == pcb) {
-    /* make list start at 2nd pcb */
-    raw_pcbs = raw_pcbs->next;
-    /* pcb not 1st in list */
-  } else for(pcb2 = raw_pcbs; pcb2 != NULL; pcb2 = pcb2->next) {
-    /* find pcb in raw_pcbs list */
-    if (pcb2->next != NULL && pcb2->next == pcb) {
-      /* remove pcb from list */
-      pcb2->next = pcb->next;
-    }
-  }
-  memp_free(MEMP_RAW_PCB, pcb);
-}
-
-/**
- * Create a RAW PCB.
- *
- * @return The RAW PCB which was created. NULL if the PCB data structure
- * could not be allocated.
- *
- * @param proto the protocol number of the IPs payload (e.g. IP_PROTO_ICMP)
- *
- * @see raw_remove()
- */
-struct raw_pcb *
-raw_new(u16_t proto) {
-  struct raw_pcb *pcb;
-
-  LWIP_DEBUGF(RAW_DEBUG | DBG_TRACE | 3, ("raw_new\n"));
-
-  pcb = memp_malloc(MEMP_RAW_PCB);
-  /* could allocate RAW PCB? */
-  if (pcb != NULL) {
-    /* initialize PCB to all zeroes */
-    memset(pcb, 0, sizeof(struct raw_pcb));
-    pcb->protocol = proto;
-    pcb->ttl = RAW_TTL;
-    pcb->next = raw_pcbs;
-    raw_pcbs = pcb;
-  }
-  return pcb;
-}
-
-#endif /* LWIP_RAW */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/stats.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/stats.c
deleted file mode 100644
index 56768896b..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/stats.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-
-#include 
-
-#include "lwip/opt.h"
-
-#include "lwip/def.h"
-
-#include "lwip/stats.h"
-#include "lwip/mem.h"
-
-
-#if LWIP_STATS
-struct stats_ lwip_stats;
-
-void
-stats_init(void)
-{
-  memset(&lwip_stats, 0, sizeof(struct stats_));
-}
-#if LWIP_STATS_DISPLAY
-void
-stats_display_proto(struct stats_proto *proto, char *name)
-{
-  LWIP_PLATFORM_DIAG(("\n%s\n\t", name));
-  LWIP_PLATFORM_DIAG(("xmit: %d\n\t", proto->xmit)); 
-  LWIP_PLATFORM_DIAG(("rexmit: %d\n\t", proto->rexmit)); 
-  LWIP_PLATFORM_DIAG(("recv: %d\n\t", proto->recv)); 
-  LWIP_PLATFORM_DIAG(("fw: %d\n\t", proto->fw)); 
-  LWIP_PLATFORM_DIAG(("drop: %d\n\t", proto->drop)); 
-  LWIP_PLATFORM_DIAG(("chkerr: %d\n\t", proto->chkerr)); 
-  LWIP_PLATFORM_DIAG(("lenerr: %d\n\t", proto->lenerr)); 
-  LWIP_PLATFORM_DIAG(("memerr: %d\n\t", proto->memerr)); 
-  LWIP_PLATFORM_DIAG(("rterr: %d\n\t", proto->rterr)); 
-  LWIP_PLATFORM_DIAG(("proterr: %d\n\t", proto->proterr)); 
-  LWIP_PLATFORM_DIAG(("opterr: %d\n\t", proto->opterr)); 
-  LWIP_PLATFORM_DIAG(("err: %d\n\t", proto->err)); 
-  LWIP_PLATFORM_DIAG(("cachehit: %d\n", proto->cachehit)); 
-}
-
-void
-stats_display_pbuf(struct stats_pbuf *pbuf)
-{
-  LWIP_PLATFORM_DIAG(("\nPBUF\n\t"));
-  LWIP_PLATFORM_DIAG(("avail: %d\n\t", pbuf->avail)); 
-  LWIP_PLATFORM_DIAG(("used: %d\n\t", pbuf->used)); 
-  LWIP_PLATFORM_DIAG(("max: %d\n\t", pbuf->max)); 
-  LWIP_PLATFORM_DIAG(("err: %d\n\t", pbuf->err)); 
-  LWIP_PLATFORM_DIAG(("alloc_locked: %d\n\t", pbuf->alloc_locked)); 
-  LWIP_PLATFORM_DIAG(("refresh_locked: %d\n", pbuf->refresh_locked)); 
-}
-
-void
-stats_display_mem(struct stats_mem *mem, char *name)
-{
-  LWIP_PLATFORM_DIAG(("\n MEM %s\n\t", name));
-  LWIP_PLATFORM_DIAG(("avail: %d\n\t", mem->avail)); 
-  LWIP_PLATFORM_DIAG(("used: %d\n\t", mem->used)); 
-  LWIP_PLATFORM_DIAG(("max: %d\n\t", mem->max)); 
-  LWIP_PLATFORM_DIAG(("err: %d\n", mem->err));
-  
-}
-
-void
-stats_display(void)
-{
-  int i;
-  char * memp_names[] = {"PBUF", "RAW_PCB", "UDP_PCB", "TCP_PCB", "TCP_PCB_LISTEN",
-	  		"TCP_SEG", "NETBUF", "NETCONN", "API_MSG", "TCP_MSG", "TIMEOUT"};
-  stats_display_proto(&lwip_stats.link, "LINK");
-  stats_display_proto(&lwip_stats.ip_frag, "IP_FRAG");
-  stats_display_proto(&lwip_stats.ip, "IP");
-  stats_display_proto(&lwip_stats.icmp, "ICMP");
-  stats_display_proto(&lwip_stats.udp, "UDP");
-  stats_display_proto(&lwip_stats.tcp, "TCP");
-  stats_display_pbuf(&lwip_stats.pbuf);
-  stats_display_mem(&lwip_stats.mem, "HEAP");
-  for (i = 0; i < MEMP_MAX; i++) {
-    stats_display_mem(&lwip_stats.memp[i], memp_names[i]);
-  }
-	
-}
-#endif /* LWIP_STATS_DISPLAY */
-#endif /* LWIP_STATS */
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/sys.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/sys.c
deleted file mode 100644
index a07a839a6..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/sys.c
+++ /dev/null
@@ -1,294 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels 
- *
- */
-
-#include "lwip/sys.h"
-#include "lwip/opt.h"
-#include "lwip/def.h"
-#include "lwip/memp.h"
-
-#if (NO_SYS == 0)
-
-struct sswt_cb
-{
-    int timeflag;
-    sys_sem_t *psem;
-};
-
-
-
-void
-sys_mbox_fetch(sys_mbox_t mbox, void **msg)
-{
-  u32_t time;
-  struct sys_timeouts *timeouts;
-  struct sys_timeout *tmptimeout;
-  sys_timeout_handler h;
-  void *arg;
-
-
- again:
-  timeouts = sys_arch_timeouts();
-
-  if (!timeouts || !timeouts->next) {
-    sys_arch_mbox_fetch(mbox, msg, 0);
-  } else {
-    if (timeouts->next->time > 0) {
-      time = sys_arch_mbox_fetch(mbox, msg, timeouts->next->time);
-    } else {
-      time = SYS_ARCH_TIMEOUT;
-    }
-
-    if (time == SYS_ARCH_TIMEOUT) {
-      /* If time == SYS_ARCH_TIMEOUT, a timeout occured before a message
-   could be fetched. We should now call the timeout handler and
-   deallocate the memory allocated for the timeout. */
-      tmptimeout = timeouts->next;
-      timeouts->next = tmptimeout->next;
-      h = tmptimeout->h;
-      arg = tmptimeout->arg;
-      memp_free(MEMP_SYS_TIMEOUT, tmptimeout);
-      if (h != NULL) {
-        LWIP_DEBUGF(SYS_DEBUG, ("smf calling h=%p(%p)\n", (void *)h, (void *)arg));
-      	h(arg);
-      }
-
-      /* We try again to fetch a message from the mbox. */
-      goto again;
-    } else {
-      /* If time != SYS_ARCH_TIMEOUT, a message was received before the timeout
-   occured. The time variable is set to the number of
-   milliseconds we waited for the message. */
-      if (time <= timeouts->next->time) {
-  timeouts->next->time -= time;
-      } else {
-  timeouts->next->time = 0;
-      }
-    }
-
-  }
-}
-
-void
-sys_sem_wait(sys_sem_t sem)
-{
-  u32_t time;
-  struct sys_timeouts *timeouts;
-  struct sys_timeout *tmptimeout;
-  sys_timeout_handler h;
-  void *arg;
-
-  /*  while (sys_arch_sem_wait(sem, 1000) == 0);
-      return;*/
-
- again:
-
-  timeouts = sys_arch_timeouts();
-
-  if (!timeouts || !timeouts->next) {
-    sys_arch_sem_wait(sem, 0);
-  } else {
-    if (timeouts->next->time > 0) {
-      time = sys_arch_sem_wait(sem, timeouts->next->time);
-    } else {
-      time = SYS_ARCH_TIMEOUT;
-    }
-
-    if (time == SYS_ARCH_TIMEOUT) {
-      /* If time == SYS_ARCH_TIMEOUT, a timeout occured before a message
-   could be fetched. We should now call the timeout handler and
-   deallocate the memory allocated for the timeout. */
-      tmptimeout = timeouts->next;
-      timeouts->next = tmptimeout->next;
-      h = tmptimeout->h;
-      arg = tmptimeout->arg;
-      memp_free(MEMP_SYS_TIMEOUT, tmptimeout);
-      if (h != NULL) {
-        LWIP_DEBUGF(SYS_DEBUG, ("ssw h=%p(%p)\n", (void *)h, (void *)arg));
-        h(arg);
-      }
-
-
-      /* We try again to fetch a message from the mbox. */
-      goto again;
-    } else {
-      /* If time != SYS_ARCH_TIMEOUT, a message was received before the timeout
-   occured. The time variable is set to the number of
-   milliseconds we waited for the message. */
-      if (time <= timeouts->next->time) {
-  timeouts->next->time -= time;
-      } else {
-  timeouts->next->time = 0;
-      }
-    }
-
-  }
-}
-
-void
-sys_timeout(u32_t msecs, sys_timeout_handler h, void *arg)
-{
-  struct sys_timeouts *timeouts;
-  struct sys_timeout *timeout, *t;
-
-  timeout = memp_malloc(MEMP_SYS_TIMEOUT);
-  if (timeout == NULL) {
-    return;
-  }
-  timeout->next = NULL;
-  timeout->h = h;
-  timeout->arg = arg;
-  timeout->time = msecs;
-
-  timeouts = sys_arch_timeouts();
-
-  LWIP_DEBUGF(SYS_DEBUG, ("sys_timeout: %p msecs=%lu h=%p arg=%p\n",
-    (void *)timeout, msecs, (void *)h, (void *)arg));
-
-  LWIP_ASSERT("sys_timeout: timeouts != NULL", timeouts != NULL);
-
-  if (timeouts->next == NULL) {
-    timeouts->next = timeout;
-    return;
-  }
-
-  if (timeouts->next->time > msecs) {
-    timeouts->next->time -= msecs;
-    timeout->next = timeouts->next;
-    timeouts->next = timeout;
-  } else {
-    for(t = timeouts->next; t != NULL; t = t->next) {
-      timeout->time -= t->time;
-      if (t->next == NULL || t->next->time > timeout->time) {
-        if (t->next != NULL) {
-          t->next->time -= timeout->time;
-        }
-        timeout->next = t->next;
-        t->next = timeout;
-        break;
-      }
-    }
-  }
-
-}
-
-/* Go through timeout list (for this task only) and remove the first matching entry,
-   even though the timeout has not triggered yet.
-*/
-
-void
-sys_untimeout(sys_timeout_handler h, void *arg)
-{
-    struct sys_timeouts *timeouts;
-    struct sys_timeout *prev_t, *t;
-
-    timeouts = sys_arch_timeouts();
-
-    if (timeouts->next == NULL)
-        return;
-
-    for (t = timeouts->next, prev_t = NULL; t != NULL; prev_t = t, t = t->next)
-    {
-        if ((t->h == h) && (t->arg == arg))
-        {
-            /* We have a match */
-            /* Unlink from previous in list */
-            if (prev_t == NULL)
-                timeouts->next = t->next;
-            else
-                prev_t->next = t->next;
-            /* If not the last one, add time of this one back to next */
-            if (t->next != NULL)
-                t->next->time += t->time;
-            memp_free(MEMP_SYS_TIMEOUT, t);
-            return;
-        }
-    }
-    return;
-}
-
-
-
-
-
-static void
-sswt_handler(void *arg)
-{
-    struct sswt_cb *sswt_cb = (struct sswt_cb *) arg;
-
-    /* Timeout. Set flag to TRUE and signal semaphore */
-    sswt_cb->timeflag = 1;
-    sys_sem_signal(*(sswt_cb->psem));
-}
-
-/* Wait for a semaphore with timeout (specified in ms) */
-/* timeout = 0: wait forever */
-/* Returns 0 on timeout. 1 otherwise */
-
-int
-sys_sem_wait_timeout(sys_sem_t sem, u32_t timeout)
-{
-    struct sswt_cb sswt_cb;
-
-    sswt_cb.psem = &sem;
-    sswt_cb.timeflag = 0;
-
-    /* If timeout is zero, then just wait forever */
-    if (timeout > 0)
-        /* Create a timer and pass it the address of our flag */
-        sys_timeout(timeout, sswt_handler, &sswt_cb);
-    sys_sem_wait(sem);
-    /* Was it a timeout? */
-    if (sswt_cb.timeflag)
-    {
-        /* timeout */
-        return 0;
-    } else {
-        /* Not a timeout. Remove timeout entry */
-        sys_untimeout(sswt_handler, &sswt_cb);
-        return 1;
-    }
-
-}
-
-
-void
-sys_msleep(u32_t ms)
-{
-  sys_sem_t delaysem = sys_sem_new(0);
-
-  sys_sem_wait_timeout(delaysem, ms);
-
-  sys_sem_free(delaysem);
-}
-
-
-#endif /* NO_SYS */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/tcp.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/tcp.c
deleted file mode 100644
index b36b79416..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/tcp.c
+++ /dev/null
@@ -1,1263 +0,0 @@
-/**
- * @file
- *
- * Transmission Control Protocol for IP
- *
- * This file contains common functions for the TCP implementation, such as functinos
- * for manipulating the data structures and the TCP timer functions. TCP functions
- * related to input and output is found in tcp_in.c and tcp_out.c respectively.
- *
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-
-#include 
-
-#include "lwip/opt.h"
-#include "lwip/def.h"
-#include "lwip/mem.h"
-#include "lwip/memp.h"
-
-#include "lwip/tcp.h"
-#if LWIP_TCP
-
-/* Incremented every coarse grained timer shot
-   (typically every 500 ms, determined by TCP_COARSE_TIMEOUT). */
-u32_t tcp_ticks;
-const u8_t tcp_backoff[13] =
-    { 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7};
-
-/* The TCP PCB lists. */
-
-/** List of all TCP PCBs in LISTEN state */
-union tcp_listen_pcbs_t tcp_listen_pcbs;
-/** List of all TCP PCBs that are in a state in which
- * they accept or send data. */
-struct tcp_pcb *tcp_active_pcbs;  
-/** List of all TCP PCBs in TIME-WAIT state */
-struct tcp_pcb *tcp_tw_pcbs;
-
-struct tcp_pcb *tcp_tmp_pcb;
-
-static u8_t tcp_timer;
-static u16_t tcp_new_port(void);
-
-/**
- * Initializes the TCP layer.
- */
-void
-tcp_init(void)
-{
-  /* Clear globals. */
-  tcp_listen_pcbs.listen_pcbs = NULL;
-  tcp_active_pcbs = NULL;
-  tcp_tw_pcbs = NULL;
-  tcp_tmp_pcb = NULL;
-  
-  /* initialize timer */
-  tcp_ticks = 0;
-  tcp_timer = 0;
-  
-}
-
-/**
- * Called periodically to dispatch TCP timers.
- *
- */
-void
-tcp_tmr(void)
-{
-  /* Call tcp_fasttmr() every 250 ms */
-  tcp_fasttmr();
-
-  if (++tcp_timer & 1) {
-    /* Call tcp_tmr() every 500 ms, i.e., every other timer
-       tcp_tmr() is called. */
-    tcp_slowtmr();
-  }
-}
-
-/**
- * Closes the connection held by the PCB.
- *
- */
-err_t
-tcp_close(struct tcp_pcb *pcb)
-{
-  err_t err;
-
-#if TCP_DEBUG
-  LWIP_DEBUGF(TCP_DEBUG, ("tcp_close: closing in state "));
-  tcp_debug_print_state(pcb->state);
-  LWIP_DEBUGF(TCP_DEBUG, ("\n"));
-#endif /* TCP_DEBUG */
-  switch (pcb->state) {
-  case CLOSED:
-    /* Closing a pcb in the CLOSED state might seem erroneous,
-     * however, it is in this state once allocated and as yet unused
-     * and the user needs some way to free it should the need arise.
-     * Calling tcp_close() with a pcb that has already been closed, (i.e. twice)
-     * or for a pcb that has been used and then entered the CLOSED state 
-     * is erroneous, but this should never happen as the pcb has in those cases
-     * been freed, and so any remaining handles are bogus. */
-    err = ERR_OK;
-    memp_free(MEMP_TCP_PCB, pcb);
-    pcb = NULL;
-    break;
-  case LISTEN:
-    err = ERR_OK;
-    tcp_pcb_remove((struct tcp_pcb **)&tcp_listen_pcbs.pcbs, pcb);
-    memp_free(MEMP_TCP_PCB_LISTEN, pcb);
-    pcb = NULL;
-    break;
-  case SYN_SENT:
-    err = ERR_OK;
-    tcp_pcb_remove(&tcp_active_pcbs, pcb);
-    memp_free(MEMP_TCP_PCB, pcb);
-    pcb = NULL;
-    break;
-  case SYN_RCVD:
-  case ESTABLISHED:
-    err = tcp_send_ctrl(pcb, TCP_FIN);
-    if (err == ERR_OK) {
-      pcb->state = FIN_WAIT_1;
-    }
-    break;
-  case CLOSE_WAIT:
-    err = tcp_send_ctrl(pcb, TCP_FIN);
-    if (err == ERR_OK) {
-      pcb->state = LAST_ACK;
-    }
-    break;
-  default:
-    /* Has already been closed, do nothing. */
-    err = ERR_OK;
-    pcb = NULL;
-    break;
-  }
-
-  if (pcb != NULL && err == ERR_OK) {
-    err = tcp_output(pcb);
-  }
-  return err;
-}
-
-/**
- * Aborts a connection by sending a RST to the remote host and deletes
- * the local protocol control block. This is done when a connection is
- * killed because of shortage of memory.
- *
- */
-void
-tcp_abort(struct tcp_pcb *pcb)
-{
-  u32_t seqno, ackno;
-  u16_t remote_port, local_port;
-  struct ip_addr remote_ip, local_ip;
-#if LWIP_CALLBACK_API  
-  void (* errf)(void *arg, err_t err);
-#endif /* LWIP_CALLBACK_API */
-  void *errf_arg;
-
-  
-  /* Figure out on which TCP PCB list we are, and remove us. If we
-     are in an active state, call the receive function associated with
-     the PCB with a NULL argument, and send an RST to the remote end. */
-  if (pcb->state == TIME_WAIT) {
-    tcp_pcb_remove(&tcp_tw_pcbs, pcb);
-    memp_free(MEMP_TCP_PCB, pcb);
-  } else {
-    seqno = pcb->snd_nxt;
-    ackno = pcb->rcv_nxt;
-    ip_addr_set(&local_ip, &(pcb->local_ip));
-    ip_addr_set(&remote_ip, &(pcb->remote_ip));
-    local_port = pcb->local_port;
-    remote_port = pcb->remote_port;
-#if LWIP_CALLBACK_API
-    errf = pcb->errf;
-#endif /* LWIP_CALLBACK_API */
-    errf_arg = pcb->callback_arg;
-    tcp_pcb_remove(&tcp_active_pcbs, pcb);
-    if (pcb->unacked != NULL) {
-      tcp_segs_free(pcb->unacked);
-    }
-    if (pcb->unsent != NULL) {
-      tcp_segs_free(pcb->unsent);
-    }
-#if TCP_QUEUE_OOSEQ    
-    if (pcb->ooseq != NULL) {
-      tcp_segs_free(pcb->ooseq);
-    }
-#endif /* TCP_QUEUE_OOSEQ */
-    memp_free(MEMP_TCP_PCB, pcb);
-    TCP_EVENT_ERR(errf, errf_arg, ERR_ABRT);
-    LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_abort: sending RST\n"));
-    tcp_rst(seqno, ackno, &local_ip, &remote_ip, local_port, remote_port);
-  }
-}
-
-/**
- * Binds the connection to a local portnumber and IP address. If the
- * IP address is not given (i.e., ipaddr == NULL), the IP address of
- * the outgoing network interface is used instead.
- *
- */
-
-err_t
-tcp_bind(struct tcp_pcb *pcb, struct ip_addr *ipaddr, u16_t port)
-{
-  struct tcp_pcb *cpcb;
-#if SO_REUSE
-  int reuse_port_all_set = 1;
-#endif /* SO_REUSE */
-
-  if (port == 0) {
-    port = tcp_new_port();
-  }
-#if SO_REUSE == 0
-  /* Check if the address already is in use. */
-  for(cpcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs;
-      cpcb != NULL; cpcb = cpcb->next) {
-    if (cpcb->local_port == port) {
-      if (ip_addr_isany(&(cpcb->local_ip)) ||
-        ip_addr_isany(ipaddr) ||
-        ip_addr_cmp(&(cpcb->local_ip), ipaddr)) {
-          return ERR_USE;
-      }
-    }
-  }
-  for(cpcb = tcp_active_pcbs;
-      cpcb != NULL; cpcb = cpcb->next) {
-    if (cpcb->local_port == port) {
-      if (ip_addr_isany(&(cpcb->local_ip)) ||
-   ip_addr_isany(ipaddr) ||
-   ip_addr_cmp(&(cpcb->local_ip), ipaddr)) {
-  return ERR_USE;
-      }
-    }
-  }
-#else /* SO_REUSE */
-  /* Search through list of PCB's in LISTEN state. 
-     
-  If there is a PCB bound to specified port and IP_ADDR_ANY another PCB can be bound to the interface IP
-  or to the loopback address on the same port if SOF_REUSEADDR is set. Any combination of PCB's bound to 
-  the same local port, but to one address out of {IP_ADDR_ANY, 127.0.0.1, interface IP} at a time is valid.
-  But no two PCB's bound to same local port and same local address is valid.
-  
-  If SOF_REUSEPORT is set several PCB's can be bound to same local port and same local address also. But then 
-  all PCB's must have the SOF_REUSEPORT option set.
-  
-  When the two options aren't set and specified port is already bound, ERR_USE is returned saying that 
-  address is already in use. */
-  for(cpcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; cpcb != NULL; cpcb = cpcb->next) {
-    if(cpcb->local_port == port) {
-      if(ip_addr_cmp(&(cpcb->local_ip), ipaddr)) {
-        if(pcb->so_options & SOF_REUSEPORT) {
-          LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in listening PCB's: SO_REUSEPORT set and same address.\n"));
-          reuse_port_all_set = (reuse_port_all_set && (cpcb->so_options & SOF_REUSEPORT));
-        }
-        else {
-          LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in listening PCB's: SO_REUSEPORT not set and same address.\n"));
-          return ERR_USE;
-        }
-      }
-      else if((ip_addr_isany(ipaddr) && !ip_addr_isany(&(cpcb->local_ip))) ||
-              (!ip_addr_isany(ipaddr) && ip_addr_isany(&(cpcb->local_ip)))) {
-        if(!(pcb->so_options & SOF_REUSEADDR) && !(pcb->so_options & SOF_REUSEPORT)) {
-          LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in listening PCB's SO_REUSEPORT or SO_REUSEADDR not set and not the same address.\n"));
-          return ERR_USE;
-        }      
-        else {
-          LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in listening PCB's SO_REUSEPORT or SO_REUSEADDR set and not the same address.\n"));
-        }     
-      }
-    }
-  }
-
-  /* Search through list of PCB's in a state in which they can accept or send data. Same decription as for 
-     PCB's in state LISTEN applies to this PCB's regarding the options SOF_REUSEADDR and SOF_REUSEPORT. */
-  for(cpcb = tcp_active_pcbs; cpcb != NULL; cpcb = cpcb->next) {
-    if(cpcb->local_port == port) {
-      if(ip_addr_cmp(&(cpcb->local_ip), ipaddr)) {
-        if(pcb->so_options & SOF_REUSEPORT) {
-          LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in active PCB's SO_REUSEPORT set and same address.\n"));
-          reuse_port_all_set = (reuse_port_all_set && (cpcb->so_options & SOF_REUSEPORT));
-        }
-        else {
-          LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in active PCB's SO_REUSEPORT not set and same address.\n"));
-          return ERR_USE;
-        }
-      }
-      else if((ip_addr_isany(ipaddr) && !ip_addr_isany(&(cpcb->local_ip))) ||
-              (!ip_addr_isany(ipaddr) && ip_addr_isany(&(cpcb->local_ip)))) {
-        if(!(pcb->so_options & SOF_REUSEADDR) && !(pcb->so_options & SOF_REUSEPORT)) {
-          LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in active PCB's SO_REUSEPORT or SO_REUSEADDR not set and not the same address.\n"));
-          return ERR_USE;
-        }   
-        else {
-          LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in active PCB's SO_REUSEPORT or SO_REUSEADDR set and not the same address.\n"));
-        }        
-      }
-    }
-  }
-
-  /* Search through list of PCB's in TIME_WAIT state. If SO_REUSEADDR is set a bound combination [IP, port} 
-     can be rebound. The same applies when SOF_REUSEPORT is set. 
-     
-     If SOF_REUSEPORT is set several PCB's can be bound to same local port and same local address also. But then 
-     all PCB's must have the SOF_REUSEPORT option set.
-     
-     When the two options aren't set and specified port is already bound, ERR_USE is returned saying that 
-     address is already in use. */
-  for(cpcb = tcp_tw_pcbs; cpcb != NULL; cpcb = cpcb->next) {
-    if(cpcb->local_port == port) {
-      if(ip_addr_cmp(&(cpcb->local_ip), ipaddr)) {
-        if(!(pcb->so_options & SOF_REUSEADDR) && !(pcb->so_options & SOF_REUSEPORT)) {
-          LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in TIME_WAIT PCB's SO_REUSEPORT or SO_REUSEADDR not set and same address.\n"));
-          return ERR_USE;
-        }
-        else if(pcb->so_options & SOF_REUSEPORT) {
-          LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: in TIME_WAIT PCB's SO_REUSEPORT set and same address.\n"));
-          reuse_port_all_set = (reuse_port_all_set && (cpcb->so_options & SOF_REUSEPORT));
-        }
-      }
-    }
-  }
-
-  /* If SOF_REUSEPORT isn't set in all PCB's bound to specified port and local address specified then 
-     {IP, port} can't be reused. */
-  if(!reuse_port_all_set) {
-    LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: not all sockets have SO_REUSEPORT set.\n"));
-    return ERR_USE;
-  }
-#endif /* SO_REUSE */
-
-  if (!ip_addr_isany(ipaddr)) {
-    pcb->local_ip = *ipaddr;
-  }
-  pcb->local_port = port;
-  LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: bind to port %u\n", port));
-  return ERR_OK;
-}
-#if LWIP_CALLBACK_API
-static err_t
-tcp_accept_null(void *arg, struct tcp_pcb *pcb, err_t err)
-{
-  (void)arg;
-  (void)pcb;
-  (void)err;
-
-  return ERR_ABRT;
-}
-#endif /* LWIP_CALLBACK_API */
-
-/**
- * Set the state of the connection to be LISTEN, which means that it
- * is able to accept incoming connections. The protocol control block
- * is reallocated in order to consume less memory. Setting the
- * connection to LISTEN is an irreversible process.
- *
- */
-struct tcp_pcb *
-tcp_listen(struct tcp_pcb *pcb)
-{
-  struct tcp_pcb_listen *lpcb;
-
-  /* already listening? */
-  if (pcb->state == LISTEN) {
-    return pcb;
-  }
-  lpcb = memp_malloc(MEMP_TCP_PCB_LISTEN);
-  if (lpcb == NULL) {
-    return NULL;
-  }
-  lpcb->callback_arg = pcb->callback_arg;
-  lpcb->local_port = pcb->local_port;
-  lpcb->state = LISTEN;
-  lpcb->so_options = pcb->so_options;
-  lpcb->so_options |= SOF_ACCEPTCONN;
-  lpcb->ttl = pcb->ttl;
-  lpcb->tos = pcb->tos;
-  ip_addr_set(&lpcb->local_ip, &pcb->local_ip);
-  memp_free(MEMP_TCP_PCB, pcb);
-#if LWIP_CALLBACK_API
-  lpcb->accept = tcp_accept_null;
-#endif /* LWIP_CALLBACK_API */
-  TCP_REG(&tcp_listen_pcbs.listen_pcbs, lpcb);
-  return (struct tcp_pcb *)lpcb;
-}
-
-/**
- * This function should be called by the application when it has
- * processed the data. The purpose is to advertise a larger window
- * when the data has been processed.
- *
- */
-void
-tcp_recved(struct tcp_pcb *pcb, u16_t len)
-{
-  if ((u32_t)pcb->rcv_wnd + len > TCP_WND) {
-    pcb->rcv_wnd = TCP_WND;
-  } else {
-    pcb->rcv_wnd += len;
-  }
-  if (!(pcb->flags & TF_ACK_DELAY) &&
-     !(pcb->flags & TF_ACK_NOW)) {
-    /*
-     * We send an ACK here (if one is not already pending, hence
-     * the above tests) as tcp_recved() implies that the application
-     * has processed some data, and so we can open the receiver's
-     * window to allow more to be transmitted.  This could result in
-     * two ACKs being sent for each received packet in some limited cases
-     * (where the application is only receiving data, and is slow to
-     * process it) but it is necessary to guarantee that the sender can
-     * continue to transmit.
-     */
-    tcp_ack(pcb);
-  } 
-  else if (pcb->flags & TF_ACK_DELAY && pcb->rcv_wnd >= TCP_WND/2) {
-    /* If we can send a window update such that there is a full
-     * segment available in the window, do so now.  This is sort of
-     * nagle-like in its goals, and tries to hit a compromise between
-     * sending acks each time the window is updated, and only sending
-     * window updates when a timer expires.  The "threshold" used
-     * above (currently TCP_WND/2) can be tuned to be more or less
-     * aggressive  */
-    tcp_ack_now(pcb);
-  }
-
-  LWIP_DEBUGF(TCP_DEBUG, ("tcp_recved: recveived %u bytes, wnd %u (%u).\n",
-         len, pcb->rcv_wnd, TCP_WND - pcb->rcv_wnd));
-}
-
-/**
- * A nastly hack featuring 'goto' statements that allocates a
- * new TCP local port.
- */
-static u16_t
-tcp_new_port(void)
-{
-  struct tcp_pcb *pcb;
-#ifndef TCP_LOCAL_PORT_RANGE_START
-#define TCP_LOCAL_PORT_RANGE_START 4096
-#define TCP_LOCAL_PORT_RANGE_END   0x7fff
-#endif
-  static u16_t port = TCP_LOCAL_PORT_RANGE_START;
-  
- again:
-  if (++port > TCP_LOCAL_PORT_RANGE_END) {
-    port = TCP_LOCAL_PORT_RANGE_START;
-  }
-  
-  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
-    if (pcb->local_port == port) {
-      goto again;
-    }
-  }
-  for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
-    if (pcb->local_port == port) {
-      goto again;
-    }
-  }
-  for(pcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; pcb != NULL; pcb = pcb->next) {
-    if (pcb->local_port == port) {
-      goto again;
-    }
-  }
-  return port;
-}
-
-/**
- * Connects to another host. The function given as the "connected"
- * argument will be called when the connection has been established.
- *
- */
-err_t
-tcp_connect(struct tcp_pcb *pcb, struct ip_addr *ipaddr, u16_t port,
-      err_t (* connected)(void *arg, struct tcp_pcb *tpcb, err_t err))
-{
-  u32_t optdata;
-  err_t ret;
-  u32_t iss;
-
-  LWIP_DEBUGF(TCP_DEBUG, ("tcp_connect to port %u\n", port));
-  if (ipaddr != NULL) {
-    pcb->remote_ip = *ipaddr;
-  } else {
-    return ERR_VAL;
-  }
-  pcb->remote_port = port;
-  if (pcb->local_port == 0) {
-    pcb->local_port = tcp_new_port();
-  }
-  iss = tcp_next_iss();
-  pcb->rcv_nxt = 0;
-  pcb->snd_nxt = iss;
-  pcb->lastack = iss - 1;
-  pcb->snd_lbb = iss - 1;
-  pcb->rcv_wnd = TCP_WND;
-  pcb->snd_wnd = TCP_WND;
-  pcb->mss = TCP_MSS;
-  pcb->cwnd = 1;
-  pcb->ssthresh = pcb->mss * 10;
-  pcb->state = SYN_SENT;
-#if LWIP_CALLBACK_API  
-  pcb->connected = connected;
-#endif /* LWIP_CALLBACK_API */  
-  TCP_REG(&tcp_active_pcbs, pcb);
-  
-  /* Build an MSS option */
-  optdata = htonl(((u32_t)2 << 24) | 
-      ((u32_t)4 << 16) | 
-      (((u32_t)pcb->mss / 256) << 8) |
-      (pcb->mss & 255));
-
-  ret = tcp_enqueue(pcb, NULL, 0, TCP_SYN, 0, (u8_t *)&optdata, 4);
-  if (ret == ERR_OK) { 
-    tcp_output(pcb);
-  }
-  return ret;
-} 
-
-/**
- * Called every 500 ms and implements the retransmission timer and the timer that
- * removes PCBs that have been in TIME-WAIT for enough time. It also increments
- * various timers such as the inactivity timer in each PCB.
- */
-void
-tcp_slowtmr(void)
-{
-  struct tcp_pcb *pcb, *pcb2, *prev;
-  u32_t eff_wnd;
-  u8_t pcb_remove;      /* flag if a PCB should be removed */
-  err_t err;
-
-  err = ERR_OK;
-
-  ++tcp_ticks;
-
-  /* Steps through all of the active PCBs. */
-  prev = NULL;
-  pcb = tcp_active_pcbs;
-  if (pcb == NULL) {
-    LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: no active pcbs\n"));
-  }
-  while (pcb != NULL) {
-    LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: processing active pcb\n"));
-    LWIP_ASSERT("tcp_slowtmr: active pcb->state != CLOSED\n", pcb->state != CLOSED);
-    LWIP_ASSERT("tcp_slowtmr: active pcb->state != LISTEN\n", pcb->state != LISTEN);
-    LWIP_ASSERT("tcp_slowtmr: active pcb->state != TIME-WAIT\n", pcb->state != TIME_WAIT);
-
-    pcb_remove = 0;
-
-    if (pcb->state == SYN_SENT && pcb->nrtx == TCP_SYNMAXRTX) {
-      ++pcb_remove;
-      LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max SYN retries reached\n"));
-    }
-    else if (pcb->nrtx == TCP_MAXRTX) {
-      ++pcb_remove;
-      LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max DATA retries reached\n"));
-    } else {
-      ++pcb->rtime;
-      if (pcb->unacked != NULL && pcb->rtime >= pcb->rto) {
-
-        /* Time for a retransmission. */
-        LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_slowtmr: rtime %u pcb->rto %u\n",
-          pcb->rtime, pcb->rto));
-
-        /* Double retransmission time-out unless we are trying to
-         * connect to somebody (i.e., we are in SYN_SENT). */
-        if (pcb->state != SYN_SENT) {
-          pcb->rto = ((pcb->sa >> 3) + pcb->sv) << tcp_backoff[pcb->nrtx];
-        }
-        /* Reduce congestion window and ssthresh. */
-        eff_wnd = LWIP_MIN(pcb->cwnd, pcb->snd_wnd);
-        pcb->ssthresh = eff_wnd >> 1;
-        if (pcb->ssthresh < pcb->mss) {
-          pcb->ssthresh = pcb->mss * 2;
-        }
-        pcb->cwnd = pcb->mss;
-        LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: cwnd %u ssthresh %u\n",
-                                pcb->cwnd, pcb->ssthresh));
- 
-        /* The following needs to be called AFTER cwnd is set to one mss - STJ */
-        tcp_rexmit_rto(pcb);
-     }
-    }
-    /* Check if this PCB has stayed too long in FIN-WAIT-2 */
-    if (pcb->state == FIN_WAIT_2) {
-      if ((u32_t)(tcp_ticks - pcb->tmr) >
-        TCP_FIN_WAIT_TIMEOUT / TCP_SLOW_INTERVAL) {
-        ++pcb_remove;
-        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in FIN-WAIT-2\n"));
-      }
-    }
-
-   /* Check if KEEPALIVE should be sent */
-   if((pcb->so_options & SOF_KEEPALIVE) && ((pcb->state == ESTABLISHED) || (pcb->state == CLOSE_WAIT))) {
-      if((u32_t)(tcp_ticks - pcb->tmr) > (pcb->keepalive + TCP_MAXIDLE) / TCP_SLOW_INTERVAL)  {
-         LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: KEEPALIVE timeout. Aborting connection to %u.%u.%u.%u.\n",
-                                 ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip),
-                                 ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip)));
-
-         tcp_abort(pcb);
-      }
-      else if((u32_t)(tcp_ticks - pcb->tmr) > (pcb->keepalive + pcb->keep_cnt * TCP_KEEPINTVL) / TCP_SLOW_INTERVAL) {
-         tcp_keepalive(pcb);
-         pcb->keep_cnt++;
-      }
-   }
-
-    /* If this PCB has queued out of sequence data, but has been
-       inactive for too long, will drop the data (it will eventually
-       be retransmitted). */
-#if TCP_QUEUE_OOSEQ    
-    if (pcb->ooseq != NULL &&
-       (u32_t)tcp_ticks - pcb->tmr >=
-       pcb->rto * (u32_t)TCP_OOSEQ_TIMEOUT) {
-      tcp_segs_free(pcb->ooseq);
-      pcb->ooseq = NULL;
-      LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: dropping OOSEQ queued data\n"));
-    }
-#endif /* TCP_QUEUE_OOSEQ */
-
-    /* Check if this PCB has stayed too long in SYN-RCVD */
-    if (pcb->state == SYN_RCVD) {
-      if ((u32_t)(tcp_ticks - pcb->tmr) >
-   TCP_SYN_RCVD_TIMEOUT / TCP_SLOW_INTERVAL) {
-        ++pcb_remove;
-        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in SYN-RCVD\n"));
-      }
-    }
-
-
-    /* If the PCB should be removed, do it. */
-    if (pcb_remove) {
-      tcp_pcb_purge(pcb);      
-      /* Remove PCB from tcp_active_pcbs list. */
-      if (prev != NULL) {
-  LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_active_pcbs", pcb != tcp_active_pcbs);
-        prev->next = pcb->next;
-      } else {
-        /* This PCB was the first. */
-        LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_active_pcbs", tcp_active_pcbs == pcb);
-        tcp_active_pcbs = pcb->next;
-      }
-
-      TCP_EVENT_ERR(pcb->errf, pcb->callback_arg, ERR_ABRT);
-
-      pcb2 = pcb->next;
-      memp_free(MEMP_TCP_PCB, pcb);
-      pcb = pcb2;
-    } else {
-
-      /* We check if we should poll the connection. */
-      ++pcb->polltmr;
-      if (pcb->polltmr >= pcb->pollinterval) {
-        pcb->polltmr = 0;
-        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: polling application\n"));
-        TCP_EVENT_POLL(pcb, err);
-        if (err == ERR_OK) {
-          tcp_output(pcb);
-        }
-      }
-      
-      prev = pcb;
-      pcb = pcb->next;
-    }
-  }
-
-  
-  /* Steps through all of the TIME-WAIT PCBs. */
-  prev = NULL;    
-  pcb = tcp_tw_pcbs;
-  while (pcb != NULL) {
-    LWIP_ASSERT("tcp_slowtmr: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT);
-    pcb_remove = 0;
-
-    /* Check if this PCB has stayed long enough in TIME-WAIT */
-    if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) {
-      ++pcb_remove;
-    }
-    
-
-
-    /* If the PCB should be removed, do it. */
-    if (pcb_remove) {
-      tcp_pcb_purge(pcb);      
-      /* Remove PCB from tcp_tw_pcbs list. */
-      if (prev != NULL) {
-  LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_tw_pcbs", pcb != tcp_tw_pcbs);
-        prev->next = pcb->next;
-      } else {
-        /* This PCB was the first. */
-        LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_tw_pcbs", tcp_tw_pcbs == pcb);
-        tcp_tw_pcbs = pcb->next;
-      }
-      pcb2 = pcb->next;
-      memp_free(MEMP_TCP_PCB, pcb);
-      pcb = pcb2;
-    } else {
-      prev = pcb;
-      pcb = pcb->next;
-    }
-  }
-}
-
-/**
- * Is called every TCP_FAST_INTERVAL (250 ms) and sends delayed ACKs.
- */
-void
-tcp_fasttmr(void)
-{
-  struct tcp_pcb *pcb;
-
-  /* send delayed ACKs */  
-  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
-    if (pcb->flags & TF_ACK_DELAY) {
-      LWIP_DEBUGF(TCP_DEBUG, ("tcp_fasttmr: delayed ACK\n"));
-      tcp_ack_now(pcb);
-      pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW);
-    }
-  }
-}
-
-/**
- * Deallocates a list of TCP segments (tcp_seg structures).
- *
- */
-u8_t
-tcp_segs_free(struct tcp_seg *seg)
-{
-  u8_t count = 0;
-  struct tcp_seg *next;
-  while (seg != NULL) {
-    next = seg->next;
-    count += tcp_seg_free(seg);
-    seg = next;
-  }
-  return count;
-}
-
-/**
- * Frees a TCP segment.
- *
- */
-u8_t
-tcp_seg_free(struct tcp_seg *seg)
-{
-  u8_t count = 0;
-  
-  if (seg != NULL) {
-    if (seg->p != NULL) {
-      count = pbuf_free(seg->p);
-#if TCP_DEBUG
-      seg->p = NULL;
-#endif /* TCP_DEBUG */
-    }
-    memp_free(MEMP_TCP_SEG, seg);
-  }
-  return count;
-}
-
-/**
- * Sets the priority of a connection.
- *
- */
-void
-tcp_setprio(struct tcp_pcb *pcb, u8_t prio)
-{
-  pcb->prio = prio;
-}
-#if TCP_QUEUE_OOSEQ
-
-/**
- * Returns a copy of the given TCP segment.
- *
- */ 
-struct tcp_seg *
-tcp_seg_copy(struct tcp_seg *seg)
-{
-  struct tcp_seg *cseg;
-
-  cseg = memp_malloc(MEMP_TCP_SEG);
-  if (cseg == NULL) {
-    return NULL;
-  }
-  memcpy((char *)cseg, (const char *)seg, sizeof(struct tcp_seg)); 
-  pbuf_ref(cseg->p);
-  return cseg;
-}
-#endif
-
-#if LWIP_CALLBACK_API
-static err_t
-tcp_recv_null(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err)
-{
-  arg = arg;
-  if (p != NULL) {
-    pbuf_free(p);
-  } else if (err == ERR_OK) {
-    return tcp_close(pcb);
-  }
-  return ERR_OK;
-}
-#endif /* LWIP_CALLBACK_API */
-
-static void
-tcp_kill_prio(u8_t prio)
-{
-  struct tcp_pcb *pcb, *inactive;
-  u32_t inactivity;
-  u8_t mprio;
-
-
-  mprio = TCP_PRIO_MAX;
-  
-  /* We kill the oldest active connection that has lower priority than
-     prio. */
-  inactivity = 0;
-  inactive = NULL;
-  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
-    if (pcb->prio <= prio &&
-       pcb->prio <= mprio &&
-       (u32_t)(tcp_ticks - pcb->tmr) >= inactivity) {
-      inactivity = tcp_ticks - pcb->tmr;
-      inactive = pcb;
-      mprio = pcb->prio;
-    }
-  }
-  if (inactive != NULL) {
-    LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_prio: killing oldest PCB %p (%ld)\n",
-           (void *)inactive, inactivity));
-    tcp_abort(inactive);
-  }      
-}
-
-
-static void
-tcp_kill_timewait(void)
-{
-  struct tcp_pcb *pcb, *inactive;
-  u32_t inactivity;
-
-  inactivity = 0;
-  inactive = NULL;
-  for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
-    if ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity) {
-      inactivity = tcp_ticks - pcb->tmr;
-      inactive = pcb;
-    }
-  }
-  if (inactive != NULL) {
-    LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_timewait: killing oldest TIME-WAIT PCB %p (%ld)\n",
-           (void *)inactive, inactivity));
-    tcp_abort(inactive);
-  }      
-}
-
-
-
-struct tcp_pcb *
-tcp_alloc(u8_t prio)
-{
-  struct tcp_pcb *pcb;
-  u32_t iss;
-  
-  pcb = memp_malloc(MEMP_TCP_PCB);
-  if (pcb == NULL) {
-    /* Try killing oldest connection in TIME-WAIT. */
-    LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest TIME-WAIT connection\n"));
-    tcp_kill_timewait();
-    pcb = memp_malloc(MEMP_TCP_PCB);
-    if (pcb == NULL) {
-      tcp_kill_prio(prio);    
-      pcb = memp_malloc(MEMP_TCP_PCB);
-    }
-  }
-  if (pcb != NULL) {
-    memset(pcb, 0, sizeof(struct tcp_pcb));
-    pcb->prio = TCP_PRIO_NORMAL;
-    pcb->snd_buf = TCP_SND_BUF;
-    pcb->snd_queuelen = 0;
-    pcb->rcv_wnd = TCP_WND;
-    pcb->tos = 0;
-    pcb->ttl = TCP_TTL;
-    pcb->mss = TCP_MSS;
-    pcb->rto = 3000 / TCP_SLOW_INTERVAL;
-    pcb->sa = 0;
-    pcb->sv = 3000 / TCP_SLOW_INTERVAL;
-    pcb->rtime = 0;
-    pcb->cwnd = 1;
-    iss = tcp_next_iss();
-    pcb->snd_wl2 = iss;
-    pcb->snd_nxt = iss;
-    pcb->snd_max = iss;
-    pcb->lastack = iss;
-    pcb->snd_lbb = iss;   
-    pcb->tmr = tcp_ticks;
-
-    pcb->polltmr = 0;
-
-#if LWIP_CALLBACK_API
-    pcb->recv = tcp_recv_null;
-#endif /* LWIP_CALLBACK_API */  
-    
-    /* Init KEEPALIVE timer */
-    pcb->keepalive = TCP_KEEPDEFAULT;
-    pcb->keep_cnt = 0;
-  }
-  return pcb;
-}
-
-/**
- * Creates a new TCP protocol control block but doesn't place it on
- * any of the TCP PCB lists.
- *
- * @internal: Maybe there should be a idle TCP PCB list where these
- * PCBs are put on. We can then implement port reservation using
- * tcp_bind(). Currently, we lack this (BSD socket type of) feature.
- */
-
-struct tcp_pcb *
-tcp_new(void)
-{
-  return tcp_alloc(TCP_PRIO_NORMAL);
-}
-
-/*
- * tcp_arg():
- *
- * Used to specify the argument that should be passed callback
- * functions.
- *
- */ 
-
-void
-tcp_arg(struct tcp_pcb *pcb, void *arg)
-{  
-  pcb->callback_arg = arg;
-}
-#if LWIP_CALLBACK_API
-
-/**
- * Used to specify the function that should be called when a TCP
- * connection receives data.
- *
- */ 
-void
-tcp_recv(struct tcp_pcb *pcb,
-   err_t (* recv)(void *arg, struct tcp_pcb *tpcb, struct pbuf *p, err_t err))
-{
-  pcb->recv = recv;
-}
-
-/**
- * Used to specify the function that should be called when TCP data
- * has been successfully delivered to the remote host.
- *
- */ 
-
-void
-tcp_sent(struct tcp_pcb *pcb,
-   err_t (* sent)(void *arg, struct tcp_pcb *tpcb, u16_t len))
-{
-  pcb->sent = sent;
-}
-
-/**
- * Used to specify the function that should be called when a fatal error
- * has occured on the connection.
- *
- */ 
-void
-tcp_err(struct tcp_pcb *pcb,
-   void (* errf)(void *arg, err_t err))
-{
-  pcb->errf = errf;
-}
-
-/**
- * Used for specifying the function that should be called when a
- * LISTENing connection has been connected to another host.
- *
- */ 
-void
-tcp_accept(struct tcp_pcb *pcb,
-     err_t (* accept)(void *arg, struct tcp_pcb *newpcb, err_t err))
-{
-  ((struct tcp_pcb_listen *)pcb)->accept = accept;
-}
-#endif /* LWIP_CALLBACK_API */
-
-
-/**
- * Used to specify the function that should be called periodically
- * from TCP. The interval is specified in terms of the TCP coarse
- * timer interval, which is called twice a second.
- *
- */ 
-void
-tcp_poll(struct tcp_pcb *pcb,
-   err_t (* poll)(void *arg, struct tcp_pcb *tpcb), u8_t interval)
-{
-#if LWIP_CALLBACK_API
-  pcb->poll = poll;
-#endif /* LWIP_CALLBACK_API */  
-  pcb->pollinterval = interval;
-}
-
-/**
- * Purges a TCP PCB. Removes any buffered data and frees the buffer memory.
- *
- */
-void
-tcp_pcb_purge(struct tcp_pcb *pcb)
-{
-  if (pcb->state != CLOSED &&
-     pcb->state != TIME_WAIT &&
-     pcb->state != LISTEN) {
-
-    LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge\n"));
-    
-    if (pcb->unsent != NULL) {    
-      LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: not all data sent\n"));
-    }
-    if (pcb->unacked != NULL) {    
-      LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->unacked\n"));
-    }
-#if TCP_QUEUE_OOSEQ /* LW */
-    if (pcb->ooseq != NULL) {    
-      LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->ooseq\n"));
-    }
-    
-    tcp_segs_free(pcb->ooseq);
-    pcb->ooseq = NULL;
-#endif /* TCP_QUEUE_OOSEQ */
-    tcp_segs_free(pcb->unsent);
-    tcp_segs_free(pcb->unacked);
-    pcb->unacked = pcb->unsent = NULL;
-  }
-}
-
-/**
- * Purges the PCB and removes it from a PCB list. Any delayed ACKs are sent first.
- *
- */
-void
-tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb)
-{
-  TCP_RMV(pcblist, pcb);
-
-  tcp_pcb_purge(pcb);
-  
-  /* if there is an outstanding delayed ACKs, send it */
-  if (pcb->state != TIME_WAIT &&
-     pcb->state != LISTEN &&
-     pcb->flags & TF_ACK_DELAY) {
-    pcb->flags |= TF_ACK_NOW;
-    tcp_output(pcb);
-  }  
-  pcb->state = CLOSED;
-
-  LWIP_ASSERT("tcp_pcb_remove: tcp_pcbs_sane()", tcp_pcbs_sane());
-}
-
-/**
- * Calculates a new initial sequence number for new connections.
- *
- */
-u32_t
-tcp_next_iss(void)
-{
-  static u32_t iss = 6510;
-  
-  iss += tcp_ticks;       /* XXX */
-  return iss;
-}
-
-#if TCP_DEBUG || TCP_INPUT_DEBUG || TCP_OUTPUT_DEBUG
-void
-tcp_debug_print(struct tcp_hdr *tcphdr)
-{
-  LWIP_DEBUGF(TCP_DEBUG, ("TCP header:\n"));
-  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
-  LWIP_DEBUGF(TCP_DEBUG, ("|    %5u      |    %5u      | (src port, dest port)\n",
-         ntohs(tcphdr->src), ntohs(tcphdr->dest)));
-  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
-  LWIP_DEBUGF(TCP_DEBUG, ("|           %010lu          | (seq no)\n",
-          ntohl(tcphdr->seqno)));
-  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
-  LWIP_DEBUGF(TCP_DEBUG, ("|           %010lu          | (ack no)\n",
-         ntohl(tcphdr->ackno)));
-  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
-  LWIP_DEBUGF(TCP_DEBUG, ("| %2u |   |%u%u%u%u%u%u|     %5u     | (hdrlen, flags (",
-       TCPH_HDRLEN(tcphdr),
-         TCPH_FLAGS(tcphdr) >> 5 & 1,
-         TCPH_FLAGS(tcphdr) >> 4 & 1,
-         TCPH_FLAGS(tcphdr) >> 3 & 1,
-         TCPH_FLAGS(tcphdr) >> 2 & 1,
-         TCPH_FLAGS(tcphdr) >> 1 & 1,
-         TCPH_FLAGS(tcphdr) & 1,
-         ntohs(tcphdr->wnd)));
-  tcp_debug_print_flags(TCPH_FLAGS(tcphdr));
-  LWIP_DEBUGF(TCP_DEBUG, ("), win)\n"));
-  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
-  LWIP_DEBUGF(TCP_DEBUG, ("|    0x%04x     |     %5u     | (chksum, urgp)\n",
-         ntohs(tcphdr->chksum), ntohs(tcphdr->urgp)));
-  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
-}
-
-void
-tcp_debug_print_state(enum tcp_state s)
-{
-  LWIP_DEBUGF(TCP_DEBUG, ("State: "));
-  switch (s) {
-  case CLOSED:
-    LWIP_DEBUGF(TCP_DEBUG, ("CLOSED\n"));
-    break;
- case LISTEN:
-   LWIP_DEBUGF(TCP_DEBUG, ("LISTEN\n"));
-   break;
-  case SYN_SENT:
-    LWIP_DEBUGF(TCP_DEBUG, ("SYN_SENT\n"));
-    break;
-  case SYN_RCVD:
-    LWIP_DEBUGF(TCP_DEBUG, ("SYN_RCVD\n"));
-    break;
-  case ESTABLISHED:
-    LWIP_DEBUGF(TCP_DEBUG, ("ESTABLISHED\n"));
-    break;
-  case FIN_WAIT_1:
-    LWIP_DEBUGF(TCP_DEBUG, ("FIN_WAIT_1\n"));
-    break;
-  case FIN_WAIT_2:
-    LWIP_DEBUGF(TCP_DEBUG, ("FIN_WAIT_2\n"));
-    break;
-  case CLOSE_WAIT:
-    LWIP_DEBUGF(TCP_DEBUG, ("CLOSE_WAIT\n"));
-    break;
-  case CLOSING:
-    LWIP_DEBUGF(TCP_DEBUG, ("CLOSING\n"));
-    break;
-  case LAST_ACK:
-    LWIP_DEBUGF(TCP_DEBUG, ("LAST_ACK\n"));
-    break;
-  case TIME_WAIT:
-    LWIP_DEBUGF(TCP_DEBUG, ("TIME_WAIT\n"));
-   break;
-  }
-}
-
-void
-tcp_debug_print_flags(u8_t flags)
-{
-  if (flags & TCP_FIN) {
-    LWIP_DEBUGF(TCP_DEBUG, ("FIN "));
-  }
-  if (flags & TCP_SYN) {
-    LWIP_DEBUGF(TCP_DEBUG, ("SYN "));
-  }
-  if (flags & TCP_RST) {
-    LWIP_DEBUGF(TCP_DEBUG, ("RST "));
-  }
-  if (flags & TCP_PSH) {
-    LWIP_DEBUGF(TCP_DEBUG, ("PSH "));
-  }
-  if (flags & TCP_ACK) {
-    LWIP_DEBUGF(TCP_DEBUG, ("ACK "));
-  }
-  if (flags & TCP_URG) {
-    LWIP_DEBUGF(TCP_DEBUG, ("URG "));
-  }
-  if (flags & TCP_ECE) {
-    LWIP_DEBUGF(TCP_DEBUG, ("ECE "));
-  }
-  if (flags & TCP_CWR) {
-    LWIP_DEBUGF(TCP_DEBUG, ("CWR "));
-  }
-}
-
-void
-tcp_debug_print_pcbs(void)
-{
-  struct tcp_pcb *pcb;
-  LWIP_DEBUGF(TCP_DEBUG, ("Active PCB states:\n"));
-  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
-    LWIP_DEBUGF(TCP_DEBUG, ("Local port %u, foreign port %u snd_nxt %lu rcv_nxt %lu ",
-                       pcb->local_port, pcb->remote_port,
-                       pcb->snd_nxt, pcb->rcv_nxt));
-    tcp_debug_print_state(pcb->state);
-  }    
-  LWIP_DEBUGF(TCP_DEBUG, ("Listen PCB states:\n"));
-  for(pcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; pcb != NULL; pcb = pcb->next) {
-    LWIP_DEBUGF(TCP_DEBUG, ("Local port %u, foreign port %u snd_nxt %lu rcv_nxt %lu ",
-                       pcb->local_port, pcb->remote_port,
-                       pcb->snd_nxt, pcb->rcv_nxt));
-    tcp_debug_print_state(pcb->state);
-  }    
-  LWIP_DEBUGF(TCP_DEBUG, ("TIME-WAIT PCB states:\n"));
-  for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
-    LWIP_DEBUGF(TCP_DEBUG, ("Local port %u, foreign port %u snd_nxt %lu rcv_nxt %lu ",
-                       pcb->local_port, pcb->remote_port,
-                       pcb->snd_nxt, pcb->rcv_nxt));
-    tcp_debug_print_state(pcb->state);
-  }    
-}
-
-int
-tcp_pcbs_sane(void)
-{
-  struct tcp_pcb *pcb;
-  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
-    LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != CLOSED", pcb->state != CLOSED);
-    LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != LISTEN", pcb->state != LISTEN);
-    LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT);
-  }
-  for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
-    LWIP_ASSERT("tcp_pcbs_sane: tw pcb->state == TIME-WAIT", pcb->state == TIME_WAIT);
-  }
-  return 1;
-}
-#endif /* TCP_DEBUG */
-#endif /* LWIP_TCP */
-
-
-
-
-
-
-
-
-
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/tcp_in.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/tcp_in.c
deleted file mode 100644
index c050a05ae..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/tcp_in.c
+++ /dev/null
@@ -1,1240 +0,0 @@
-/**
- * @file
- *
- * Transmission Control Protocol, incoming traffic
- *
- * The input processing functions of TCP.
- *
- * These functions are generally called in the order (ip_input() ->) tcp_input() ->
- * tcp_process() -> tcp_receive() (-> application).
- * 
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels 
- *
- */
-
-#include "lwip/def.h"
-#include "lwip/opt.h"
-
-#include "lwip/ip_addr.h"
-#include "lwip/netif.h"
-#include "lwip/mem.h"
-#include "lwip/memp.h"
-
-#include "lwip/inet.h"
-#include "lwip/tcp.h"
-
-#include "lwip/stats.h"
-
-#include "arch/perf.h"
-#if LWIP_TCP
-/* These variables are global to all functions involved in the input
-   processing of TCP segments. They are set by the tcp_input()
-   function. */
-static struct tcp_seg inseg;
-static struct tcp_hdr *tcphdr;
-static struct ip_hdr *iphdr;
-static u32_t seqno, ackno;
-static u8_t flags;
-static u16_t tcplen;
-
-static u8_t recv_flags;
-static struct pbuf *recv_data;
-
-struct tcp_pcb *tcp_input_pcb;
-
-/* Forward declarations. */
-static err_t tcp_process(struct tcp_pcb *pcb);
-static void tcp_receive(struct tcp_pcb *pcb);
-static void tcp_parseopt(struct tcp_pcb *pcb);
-
-static err_t tcp_listen_input(struct tcp_pcb_listen *pcb);
-static err_t tcp_timewait_input(struct tcp_pcb *pcb);
-
-
-/* tcp_input:
- *
- * The initial input processing of TCP. It verifies the TCP header, demultiplexes
- * the segment between the PCBs and passes it on to tcp_process(), which implements
- * the TCP finite state machine. This function is called by the IP layer (in
- * ip_input()).
- */
-
-void
-tcp_input(struct pbuf *p, struct netif *inp)
-{
-  struct tcp_pcb *pcb, *prev;
-  struct tcp_pcb_listen *lpcb;
-  u8_t hdrlen;
-  err_t err;
-
-#if SO_REUSE
-  struct tcp_pcb *pcb_temp;
-  int reuse = 0;
-  int reuse_port = 0;
-#endif /* SO_REUSE */
-
-  PERF_START;
-
-  TCP_STATS_INC(tcp.recv);
-
-  iphdr = p->payload;
-  tcphdr = (struct tcp_hdr *)((u8_t *)p->payload + IPH_HL(iphdr) * 4);
-
-#if TCP_INPUT_DEBUG
-  tcp_debug_print(tcphdr);
-#endif
-
-  /* remove header from payload */
-  if (pbuf_header(p, -((s16_t)(IPH_HL(iphdr) * 4))) || (p->tot_len < sizeof(struct tcp_hdr))) {
-    /* drop short packets */
-    LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: short packet (%u bytes) discarded\n", p->tot_len));
-    TCP_STATS_INC(tcp.lenerr);
-    TCP_STATS_INC(tcp.drop);
-    pbuf_free(p);
-    return;
-  }
-
-  /* Don't even process incoming broadcasts/multicasts. */
-  if (ip_addr_isbroadcast(&(iphdr->dest), inp) ||
-      ip_addr_ismulticast(&(iphdr->dest))) {
-    pbuf_free(p);
-    return;
-  }
-
-#if CHECKSUM_CHECK_TCP
-  /* Verify TCP checksum. */
-  if (inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src),
-      (struct ip_addr *)&(iphdr->dest),
-      IP_PROTO_TCP, p->tot_len) != 0) {
-      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packet discarded due to failing checksum 0x%04x\n",
-        inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src), (struct ip_addr *)&(iphdr->dest),
-      IP_PROTO_TCP, p->tot_len)));
-#if TCP_DEBUG
-    tcp_debug_print(tcphdr);
-#endif /* TCP_DEBUG */
-    TCP_STATS_INC(tcp.chkerr);
-    TCP_STATS_INC(tcp.drop);
-
-    pbuf_free(p);
-    return;
-  }
-#endif
-
-  /* Move the payload pointer in the pbuf so that it points to the
-     TCP data instead of the TCP header. */
-  hdrlen = TCPH_HDRLEN(tcphdr);
-  pbuf_header(p, -(hdrlen * 4));
-
-  /* Convert fields in TCP header to host byte order. */
-  tcphdr->src = ntohs(tcphdr->src);
-  tcphdr->dest = ntohs(tcphdr->dest);
-  seqno = tcphdr->seqno = ntohl(tcphdr->seqno);
-  ackno = tcphdr->ackno = ntohl(tcphdr->ackno);
-  tcphdr->wnd = ntohs(tcphdr->wnd);
-
-  flags = TCPH_FLAGS(tcphdr) & TCP_FLAGS;
-  tcplen = p->tot_len + ((flags & TCP_FIN || flags & TCP_SYN)? 1: 0);
-
-  /* Demultiplex an incoming segment. First, we check if it is destined
-     for an active connection. */
-  prev = NULL;
-
-#if SO_REUSE
-  pcb_temp = tcp_active_pcbs;
-  
- again_1:
-  
-  /* Iterate through the TCP pcb list for a fully matching pcb */
-  for(pcb = pcb_temp; pcb != NULL; pcb = pcb->next) {
-#else  /* SO_REUSE */
-  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
-#endif  /* SO_REUSE */
-    LWIP_ASSERT("tcp_input: active pcb->state != CLOSED", pcb->state != CLOSED);
-    LWIP_ASSERT("tcp_input: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT);
-    LWIP_ASSERT("tcp_input: active pcb->state != LISTEN", pcb->state != LISTEN);
-    if (pcb->remote_port == tcphdr->src &&
-       pcb->local_port == tcphdr->dest &&
-       ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src)) &&
-       ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest))) {
-
-#if SO_REUSE
-      if(pcb->so_options & SOF_REUSEPORT) {
-        if(reuse) {
-          /* We processed one PCB already */
-          LWIP_DEBUGF(TCP_INPUT_DEBUG,("tcp_input: second or later PCB and SOF_REUSEPORT set.\n"));
-        } else {
-          /* First PCB with this address */
-          LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: first PCB and SOF_REUSEPORT set.\n"));
-          reuse = 1;
-        }
-        
-        reuse_port = 1; 
-        p->ref++;
-        
-        /* We want to search on next socket after receiving */
-        pcb_temp = pcb->next;
-        
-        LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: reference counter on PBUF set to %i\n", p->ref));
-      } else  {
-        if(reuse) {
-          /* We processed one PCB already */
-          LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: second or later PCB but SOF_REUSEPORT not set !\n"));
-        }
-      }
-#endif /* SO_REUSE */
-
-      /* Move this PCB to the front of the list so that subsequent
-   lookups will be faster (we exploit locality in TCP segment
-   arrivals). */
-      LWIP_ASSERT("tcp_input: pcb->next != pcb (before cache)", pcb->next != pcb);
-      if (prev != NULL) {
-  prev->next = pcb->next;
-  pcb->next = tcp_active_pcbs;
-  tcp_active_pcbs = pcb;
-      }
-      LWIP_ASSERT("tcp_input: pcb->next != pcb (after cache)", pcb->next != pcb);
-      break;
-    }
-    prev = pcb;
-  }
-
-  if (pcb == NULL) {
-    /* If it did not go to an active connection, we check the connections
-       in the TIME-WAIT state. */
-
-    for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
-      LWIP_ASSERT("tcp_input: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT);
-      if (pcb->remote_port == tcphdr->src &&
-   pcb->local_port == tcphdr->dest &&
-   ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src)) &&
-         ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest))) {
-  /* We don't really care enough to move this PCB to the front
-     of the list since we are not very likely to receive that
-     many segments for connections in TIME-WAIT. */
-  LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packed for TIME_WAITing connection.\n"));
-  tcp_timewait_input(pcb);
-  pbuf_free(p);
-  return;
-      }
-    }
-
-  /* Finally, if we still did not get a match, we check all PCBs that
-     are LISTENing for incoming connections. */
-    prev = NULL;
-    for(lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
-      if ((ip_addr_isany(&(lpcb->local_ip)) ||
-    ip_addr_cmp(&(lpcb->local_ip), &(iphdr->dest))) &&
-   lpcb->local_port == tcphdr->dest) {
-  /* Move this PCB to the front of the list so that subsequent
-     lookups will be faster (we exploit locality in TCP segment
-     arrivals). */
-  if (prev != NULL) {
-    ((struct tcp_pcb_listen *)prev)->next = lpcb->next;
-          /* our successor is the remainder of the listening list */
-    lpcb->next = tcp_listen_pcbs.listen_pcbs;
-          /* put this listening pcb at the head of the listening list */
-    tcp_listen_pcbs.listen_pcbs = lpcb;
-  }
-
-  LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packed for LISTENing connection.\n"));
-  tcp_listen_input(lpcb);
-  pbuf_free(p);
-  return;
-      }
-      prev = (struct tcp_pcb *)lpcb;
-    }
-  }
-
-#if TCP_INPUT_DEBUG
-  LWIP_DEBUGF(TCP_INPUT_DEBUG, ("+-+-+-+-+-+-+-+-+-+-+-+-+-+- tcp_input: flags "));
-  tcp_debug_print_flags(TCPH_FLAGS(tcphdr));
-  LWIP_DEBUGF(TCP_INPUT_DEBUG, ("-+-+-+-+-+-+-+-+-+-+-+-+-+-+\n"));
-#endif /* TCP_INPUT_DEBUG */
-
-
-  if (pcb != NULL) {
-    /* The incoming segment belongs to a connection. */
-#if TCP_INPUT_DEBUG
-#if TCP_DEBUG
-    tcp_debug_print_state(pcb->state);
-#endif /* TCP_DEBUG */
-#endif /* TCP_INPUT_DEBUG */
-
-    /* Set up a tcp_seg structure. */
-    inseg.next = NULL;
-    inseg.len = p->tot_len;
-    inseg.dataptr = p->payload;
-    inseg.p = p;
-    inseg.tcphdr = tcphdr;
-
-    recv_data = NULL;
-    recv_flags = 0;
-
-    tcp_input_pcb = pcb;
-    err = tcp_process(pcb);
-    tcp_input_pcb = NULL;
-    /* A return value of ERR_ABRT means that tcp_abort() was called
-       and that the pcb has been freed. If so, we don't do anything. */
-    if (err != ERR_ABRT) {
-      if (recv_flags & TF_RESET) {
-  /* TF_RESET means that the connection was reset by the other
-     end. We then call the error callback to inform the
-     application that the connection is dead before we
-     deallocate the PCB. */
-  TCP_EVENT_ERR(pcb->errf, pcb->callback_arg, ERR_RST);
-  tcp_pcb_remove(&tcp_active_pcbs, pcb);
-  memp_free(MEMP_TCP_PCB, pcb);
-      } else if (recv_flags & TF_CLOSED) {
-  /* The connection has been closed and we will deallocate the
-     PCB. */
-  tcp_pcb_remove(&tcp_active_pcbs, pcb);
-  memp_free(MEMP_TCP_PCB, pcb);
-      } else {
-  err = ERR_OK;
-  /* If the application has registered a "sent" function to be
-     called when new send buffer space is available, we call it
-     now. */
-  if (pcb->acked > 0) {
-    TCP_EVENT_SENT(pcb, pcb->acked, err);
-  }
-
-  if (recv_data != NULL) {
-    /* Notify application that data has been received. */
-    TCP_EVENT_RECV(pcb, recv_data, ERR_OK, err);
-  }
-
-  /* If a FIN segment was received, we call the callback
-     function with a NULL buffer to indicate EOF. */
-  if (recv_flags & TF_GOT_FIN) {
-    TCP_EVENT_RECV(pcb, NULL, ERR_OK, err);
-  }
-  /* If there were no errors, we try to send something out. */
-  if (err == ERR_OK) {
-    tcp_output(pcb);
-  }
-      }
-    }
-
-
-    /* We deallocate the incoming pbuf. If it was buffered by the
-       application, the application should have called pbuf_ref() to
-       increase the reference counter in the pbuf. If so, the buffer
-       isn't actually deallocated by the call to pbuf_free(), only the
-       reference count is decreased. */
-    if (inseg.p != NULL) pbuf_free(inseg.p);
-#if TCP_INPUT_DEBUG
-#if TCP_DEBUG
-    tcp_debug_print_state(pcb->state);
-#endif /* TCP_DEBUG */
-#endif /* TCP_INPUT_DEBUG */
-#if SO_REUSE
-    /* First socket should receive now */
-    if(reuse_port) {
-      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: searching next PCB.\n"));
-      reuse_port = 0;
-      
-      /* We are searching connected sockets */
-      goto again_1;
-    }
-#endif /* SO_REUSE */
-
-  } else {
-#if SO_REUSE
-    if(reuse) {
-      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: freeing PBUF with reference counter set to %i\n", p->ref));
-      pbuf_free(p);
-      goto end;
-    }
-#endif /* SO_REUSE */
-    /* If no matching PCB was found, send a TCP RST (reset) to the
-       sender. */
-    LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_input: no PCB match found, resetting.\n"));
-    if (!(TCPH_FLAGS(tcphdr) & TCP_RST)) {
-      TCP_STATS_INC(tcp.proterr);
-      TCP_STATS_INC(tcp.drop);
-      tcp_rst(ackno, seqno + tcplen,
-        &(iphdr->dest), &(iphdr->src),
-        tcphdr->dest, tcphdr->src);
-    }
-    pbuf_free(p);
-  }
-#if SO_REUSE
- end:
-#endif /* SO_REUSE */
-  LWIP_ASSERT("tcp_input: tcp_pcbs_sane()", tcp_pcbs_sane());
-  PERF_STOP("tcp_input");
-}
-
-/* tcp_listen_input():
- *
- * Called by tcp_input() when a segment arrives for a listening
- * connection.
- */
-
-static err_t
-tcp_listen_input(struct tcp_pcb_listen *pcb)
-{
-  struct tcp_pcb *npcb;
-  u32_t optdata;
-
-  /* In the LISTEN state, we check for incoming SYN segments,
-     creates a new PCB, and responds with a SYN|ACK. */
-  if (flags & TCP_ACK) {
-    /* For incoming segments with the ACK flag set, respond with a
-       RST. */
-    LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_listen_input: ACK in LISTEN, sending reset\n"));
-    tcp_rst(ackno + 1, seqno + tcplen,
-      &(iphdr->dest), &(iphdr->src),
-      tcphdr->dest, tcphdr->src);
-  } else if (flags & TCP_SYN) {
-    LWIP_DEBUGF(TCP_DEBUG, ("TCP connection request %u -> %u.\n", tcphdr->src, tcphdr->dest));
-    npcb = tcp_alloc(pcb->prio);
-    /* If a new PCB could not be created (probably due to lack of memory),
-       we don't do anything, but rely on the sender will retransmit the
-       SYN at a time when we have more memory available. */
-    if (npcb == NULL) {
-      LWIP_DEBUGF(TCP_DEBUG, ("tcp_listen_input: could not allocate PCB\n"));
-      TCP_STATS_INC(tcp.memerr);
-      return ERR_MEM;
-    }
-    /* Set up the new PCB. */
-    ip_addr_set(&(npcb->local_ip), &(iphdr->dest));
-    npcb->local_port = pcb->local_port;
-    ip_addr_set(&(npcb->remote_ip), &(iphdr->src));
-    npcb->remote_port = tcphdr->src;
-    npcb->state = SYN_RCVD;
-    npcb->rcv_nxt = seqno + 1;
-    npcb->snd_wnd = tcphdr->wnd;
-    npcb->ssthresh = npcb->snd_wnd;
-    npcb->snd_wl1 = seqno - 1;/* initialise to seqno-1 to force window update */
-    npcb->callback_arg = pcb->callback_arg;
-#if LWIP_CALLBACK_API
-    npcb->accept = pcb->accept;
-#endif /* LWIP_CALLBACK_API */
-    /* inherit socket options */
-    npcb->so_options = pcb->so_options & (SOF_DEBUG|SOF_DONTROUTE|SOF_KEEPALIVE|SOF_OOBINLINE|SOF_LINGER);
-    /* Register the new PCB so that we can begin receiving segments
-       for it. */
-    TCP_REG(&tcp_active_pcbs, npcb);
-
-    /* Parse any options in the SYN. */
-    tcp_parseopt(npcb);
-
-    /* Build an MSS option. */
-    optdata = htonl(((u32_t)2 << 24) |
-        ((u32_t)4 << 16) |
-        (((u32_t)npcb->mss / 256) << 8) |
-        (npcb->mss & 255));
-    /* Send a SYN|ACK together with the MSS option. */
-    tcp_enqueue(npcb, NULL, 0, TCP_SYN | TCP_ACK, 0, (u8_t *)&optdata, 4);
-    return tcp_output(npcb);
-  }
-  return ERR_OK;
-}
-
-/* tcp_timewait_input():
- *
- * Called by tcp_input() when a segment arrives for a connection in
- * TIME_WAIT.
- */
-
-static err_t
-tcp_timewait_input(struct tcp_pcb *pcb)
-{
-  if (TCP_SEQ_GT(seqno + tcplen, pcb->rcv_nxt)) {
-    pcb->rcv_nxt = seqno + tcplen;
-  }
-  if (tcplen > 0) {
-    tcp_ack_now(pcb);
-  }
-  return tcp_output(pcb);
-}
-
-/* tcp_process
- *
- * Implements the TCP state machine. Called by tcp_input. In some
- * states tcp_receive() is called to receive data. The tcp_seg
- * argument will be freed by the caller (tcp_input()) unless the
- * recv_data pointer in the pcb is set.
- */
-
-static err_t
-tcp_process(struct tcp_pcb *pcb)
-{
-  struct tcp_seg *rseg;
-  u8_t acceptable = 0;
-  err_t err;
-
-
-  err = ERR_OK;
-
-  /* Process incoming RST segments. */
-  if (flags & TCP_RST) {
-    /* First, determine if the reset is acceptable. */
-    if (pcb->state == SYN_SENT) {
-      if (ackno == pcb->snd_nxt) {
-        acceptable = 1;
-      }
-    } else {
-      /*if (TCP_SEQ_GEQ(seqno, pcb->rcv_nxt) &&
-          TCP_SEQ_LEQ(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {
-      */
-      if(TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt+pcb->rcv_wnd)){
-        acceptable = 1;
-      }
-    }
-
-    if (acceptable) {
-      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: Connection RESET\n"));
-      LWIP_ASSERT("tcp_input: pcb->state != CLOSED", pcb->state != CLOSED);
-      recv_flags = TF_RESET;
-      pcb->flags &= ~TF_ACK_DELAY;
-      return ERR_RST;
-    } else {
-      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: unacceptable reset seqno %lu rcv_nxt %lu\n",
-       seqno, pcb->rcv_nxt));
-      LWIP_DEBUGF(TCP_DEBUG, ("tcp_process: unacceptable reset seqno %lu rcv_nxt %lu\n",
-       seqno, pcb->rcv_nxt));
-      return ERR_OK;
-    }
-  }
-
-  /* Update the PCB (in)activity timer. */
-  pcb->tmr = tcp_ticks;
-  pcb->keep_cnt = 0;
-
-  /* Do different things depending on the TCP state. */
-  switch (pcb->state) {
-  case SYN_SENT:
-    LWIP_DEBUGF(TCP_INPUT_DEBUG, ("SYN-SENT: ackno %lu pcb->snd_nxt %lu unacked %lu\n", ackno,
-     pcb->snd_nxt, ntohl(pcb->unacked->tcphdr->seqno)));
-    if ((flags & TCP_ACK) && (flags & TCP_SYN)
-        && ackno == ntohl(pcb->unacked->tcphdr->seqno) + 1) {
-      pcb->snd_buf ++;
-      pcb->rcv_nxt = seqno + 1;
-      pcb->lastack = ackno;
-      pcb->snd_wnd = tcphdr->wnd;
-      pcb->snd_wl1 = seqno - 1; /* initialise to seqno - 1 to force window update */
-      pcb->state = ESTABLISHED;
-      pcb->cwnd = pcb->mss;
-      --pcb->snd_queuelen;
-      LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_process: SYN-SENT --queuelen %u\n", (unsigned int)pcb->snd_queuelen));
-      rseg = pcb->unacked;
-      pcb->unacked = rseg->next;
-      tcp_seg_free(rseg);
-
-      /* Parse any options in the SYNACK. */
-      tcp_parseopt(pcb);
-
-      /* Call the user specified function to call when sucessfully
-       * connected. */
-      TCP_EVENT_CONNECTED(pcb, ERR_OK, err);
-      tcp_ack(pcb);
-    }
-    break;
-  case SYN_RCVD:
-    if (flags & TCP_ACK &&
-       !(flags & TCP_RST)) {
-      /*if (TCP_SEQ_LT(pcb->lastack, ackno) &&
-        TCP_SEQ_LEQ(ackno, pcb->snd_nxt)) { */
-      if(TCP_SEQ_BETWEEN(ackno, pcb->lastack+1, pcb->snd_nxt)){
-        pcb->state = ESTABLISHED;
-        LWIP_DEBUGF(TCP_DEBUG, ("TCP connection established %u -> %u.\n", inseg.tcphdr->src, inseg.tcphdr->dest));
-#if LWIP_CALLBACK_API
-        LWIP_ASSERT("pcb->accept != NULL", pcb->accept != NULL);
-#endif
-        /* Call the accept function. */
-        TCP_EVENT_ACCEPT(pcb, ERR_OK, err);
-        if (err != ERR_OK) {
-          /* If the accept function returns with an error, we abort
-           * the connection. */
-          tcp_abort(pcb);
-          return ERR_ABRT;
-        }
-        /* If there was any data contained within this ACK,
-         * we'd better pass it on to the application as well. */
-        tcp_receive(pcb);
-        pcb->cwnd = pcb->mss;
-      }
-    }
-    break;
-  case CLOSE_WAIT:
-    /* FALLTHROUGH */
-  case ESTABLISHED:
-    tcp_receive(pcb);
-    if (flags & TCP_FIN) {
-      tcp_ack_now(pcb);
-      pcb->state = CLOSE_WAIT;
-    }
-    break;
-  case FIN_WAIT_1:
-    tcp_receive(pcb);
-    if (flags & TCP_FIN) {
-      if (flags & TCP_ACK && ackno == pcb->snd_nxt) {
-        LWIP_DEBUGF(TCP_DEBUG,
-         ("TCP connection closed %d -> %d.\n", inseg.tcphdr->src, inseg.tcphdr->dest));
-  tcp_ack_now(pcb);
-  tcp_pcb_purge(pcb);
-  TCP_RMV(&tcp_active_pcbs, pcb);
-  pcb->state = TIME_WAIT;
-  TCP_REG(&tcp_tw_pcbs, pcb);
-      } else {
-  tcp_ack_now(pcb);
-  pcb->state = CLOSING;
-      }
-    } else if (flags & TCP_ACK && ackno == pcb->snd_nxt) {
-      pcb->state = FIN_WAIT_2;
-    }
-    break;
-  case FIN_WAIT_2:
-    tcp_receive(pcb);
-    if (flags & TCP_FIN) {
-      LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed %u -> %u.\n", inseg.tcphdr->src, inseg.tcphdr->dest));
-      tcp_ack_now(pcb);
-      tcp_pcb_purge(pcb);
-      TCP_RMV(&tcp_active_pcbs, pcb);
-      pcb->state = TIME_WAIT;
-      TCP_REG(&tcp_tw_pcbs, pcb);
-    }
-    break;
-  case CLOSING:
-    tcp_receive(pcb);
-    if (flags & TCP_ACK && ackno == pcb->snd_nxt) {
-      LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed %u -> %u.\n", inseg.tcphdr->src, inseg.tcphdr->dest));
-      tcp_ack_now(pcb);
-      tcp_pcb_purge(pcb);
-      TCP_RMV(&tcp_active_pcbs, pcb);
-      pcb->state = TIME_WAIT;
-      TCP_REG(&tcp_tw_pcbs, pcb);
-    }
-    break;
-  case LAST_ACK:
-    tcp_receive(pcb);
-    if (flags & TCP_ACK && ackno == pcb->snd_nxt) {
-      LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed %u -> %u.\n", inseg.tcphdr->src, inseg.tcphdr->dest));
-      pcb->state = CLOSED;
-      recv_flags = TF_CLOSED;
-    }
-    break;
-  default:
-    break;
-  }
-
-  return ERR_OK;
-}
-
-/* tcp_receive:
- *
- * Called by tcp_process. Checks if the given segment is an ACK for outstanding
- * data, and if so frees the memory of the buffered data. Next, is places the
- * segment on any of the receive queues (pcb->recved or pcb->ooseq). If the segment
- * is buffered, the pbuf is referenced by pbuf_ref so that it will not be freed until
- * i it has been removed from the buffer.
- *
- * If the incoming segment constitutes an ACK for a segment that was used for RTT
- * estimation, the RTT is estimated here as well.
- */
-
-static void
-tcp_receive(struct tcp_pcb *pcb)
-{
-  struct tcp_seg *next;
-#if TCP_QUEUE_OOSEQ
-  struct tcp_seg *prev, *cseg;
-#endif
-  struct pbuf *p;
-  s32_t off;
-  int m;
-  u32_t right_wnd_edge;
-  u16_t new_tot_len;
-
-
-  if (flags & TCP_ACK) {
-    right_wnd_edge = pcb->snd_wnd + pcb->snd_wl1;
-
-    /* Update window. */
-    if (TCP_SEQ_LT(pcb->snd_wl1, seqno) ||
-       (pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) ||
-       (pcb->snd_wl2 == ackno && tcphdr->wnd > pcb->snd_wnd)) {
-      pcb->snd_wnd = tcphdr->wnd;
-      pcb->snd_wl1 = seqno;
-      pcb->snd_wl2 = ackno;
-      LWIP_DEBUGF(TCP_WND_DEBUG, ("tcp_receive: window update %lu\n", pcb->snd_wnd));
-#if TCP_WND_DEBUG
-    } else {
-      if (pcb->snd_wnd != tcphdr->wnd) {
-        LWIP_DEBUGF(TCP_WND_DEBUG, ("tcp_receive: no window update lastack %lu snd_max %lu ackno %lu wl1 %lu seqno %lu wl2 %lu\n",
-                               pcb->lastack, pcb->snd_max, ackno, pcb->snd_wl1, seqno, pcb->snd_wl2));
-      }
-#endif /* TCP_WND_DEBUG */
-    }
-
-
-    if (pcb->lastack == ackno) {
-      pcb->acked = 0;
-
-      if (pcb->snd_wl1 + pcb->snd_wnd == right_wnd_edge){
-        ++pcb->dupacks;
-        if (pcb->dupacks >= 3 && pcb->unacked != NULL) {
-          if (!(pcb->flags & TF_INFR)) {
-            /* This is fast retransmit. Retransmit the first unacked segment. */
-            LWIP_DEBUGF(TCP_FR_DEBUG, ("tcp_receive: dupacks %u (%lu), fast retransmit %lu\n",
-                                       (unsigned int)pcb->dupacks, pcb->lastack,
-                                       ntohl(pcb->unacked->tcphdr->seqno)));
-            tcp_rexmit(pcb);
-            /* Set ssthresh to max (FlightSize / 2, 2*SMSS) */
-            /*pcb->ssthresh = LWIP_MAX((pcb->snd_max -
-                                      pcb->lastack) / 2,
-                                      2 * pcb->mss);*/
-            /* Set ssthresh to half of the minimum of the currenct cwnd and the advertised window */
-            if(pcb->cwnd > pcb->snd_wnd)
-              pcb->ssthresh = pcb->snd_wnd / 2;
-            else
-              pcb->ssthresh = pcb->cwnd / 2;
-
-            pcb->cwnd = pcb->ssthresh + 3 * pcb->mss;
-            pcb->flags |= TF_INFR;
-          } else {
-            /* Inflate the congestion window, but not if it means that
-               the value overflows. */
-            if ((u16_t)(pcb->cwnd + pcb->mss) > pcb->cwnd) {
-              pcb->cwnd += pcb->mss;
-            }
-          }
-        }
-      } else {
-        LWIP_DEBUGF(TCP_FR_DEBUG, ("tcp_receive: dupack averted %lu %lu\n",
-                                   pcb->snd_wl1 + pcb->snd_wnd, right_wnd_edge));
-      }
-    } else
-      /*if (TCP_SEQ_LT(pcb->lastack, ackno) &&
-        TCP_SEQ_LEQ(ackno, pcb->snd_max)) { */
-      if(TCP_SEQ_BETWEEN(ackno, pcb->lastack+1, pcb->snd_max)){
-      /* We come here when the ACK acknowledges new data. */
-      
-      /* Reset the "IN Fast Retransmit" flag, since we are no longer
-         in fast retransmit. Also reset the congestion window to the
-         slow start threshold. */
-      if (pcb->flags & TF_INFR) {
-        pcb->flags &= ~TF_INFR;
-        pcb->cwnd = pcb->ssthresh;
-      }
-
-      /* Reset the number of retransmissions. */
-      pcb->nrtx = 0;
-
-      /* Reset the retransmission time-out. */
-      pcb->rto = (pcb->sa >> 3) + pcb->sv;
-
-      /* Update the send buffer space. */
-      pcb->acked = ackno - pcb->lastack;
-      pcb->snd_buf += pcb->acked;
-
-      /* Reset the fast retransmit variables. */
-      pcb->dupacks = 0;
-      pcb->lastack = ackno;
-
-      /* Update the congestion control variables (cwnd and
-         ssthresh). */
-      if (pcb->state >= ESTABLISHED) {
-        if (pcb->cwnd < pcb->ssthresh) {
-          if ((u16_t)(pcb->cwnd + pcb->mss) > pcb->cwnd) {
-            pcb->cwnd += pcb->mss;
-          }
-          LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: slow start cwnd %u\n", pcb->cwnd));
-        } else {
-          u16_t new_cwnd = (pcb->cwnd + pcb->mss * pcb->mss / pcb->cwnd);
-          if (new_cwnd > pcb->cwnd) {
-            pcb->cwnd = new_cwnd;
-          }
-          LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: congestion avoidance cwnd %u\n", pcb->cwnd));
-        }
-      }
-      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: ACK for %lu, unacked->seqno %lu:%lu\n",
-                                    ackno,
-                                    pcb->unacked != NULL?
-                                    ntohl(pcb->unacked->tcphdr->seqno): 0,
-                                    pcb->unacked != NULL?
-                                    ntohl(pcb->unacked->tcphdr->seqno) + TCP_TCPLEN(pcb->unacked): 0));
-
-      /* Remove segment from the unacknowledged list if the incoming
-         ACK acknowlegdes them. */
-      while (pcb->unacked != NULL &&
-             TCP_SEQ_LEQ(ntohl(pcb->unacked->tcphdr->seqno) +
-                         TCP_TCPLEN(pcb->unacked), ackno)) {
-        LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %lu:%lu from pcb->unacked\n",
-                                      ntohl(pcb->unacked->tcphdr->seqno),
-                                      ntohl(pcb->unacked->tcphdr->seqno) +
-                                      TCP_TCPLEN(pcb->unacked)));
-
-        next = pcb->unacked;
-        pcb->unacked = pcb->unacked->next;
-
-        LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %u ... ", (unsigned int)pcb->snd_queuelen));
-        pcb->snd_queuelen -= pbuf_clen(next->p);
-        tcp_seg_free(next);
-
-        LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%u (after freeing unacked)\n", (unsigned int)pcb->snd_queuelen));
-        if (pcb->snd_queuelen != 0) {
-          LWIP_ASSERT("tcp_receive: valid queue length", pcb->unacked != NULL ||
-                      pcb->unsent != NULL);
-        }
-      }
-      pcb->polltmr = 0;
-    }
-
-    /* We go through the ->unsent list to see if any of the segments
-       on the list are acknowledged by the ACK. This may seem
-       strange since an "unsent" segment shouldn't be acked. The
-       rationale is that lwIP puts all outstanding segments on the
-       ->unsent list after a retransmission, so these segments may
-       in fact have been sent once. */
-    while (pcb->unsent != NULL &&
-           /*TCP_SEQ_LEQ(ntohl(pcb->unsent->tcphdr->seqno) + TCP_TCPLEN(pcb->unsent), ackno) &&
-             TCP_SEQ_LEQ(ackno, pcb->snd_max)*/
-           TCP_SEQ_BETWEEN(ackno, ntohl(pcb->unsent->tcphdr->seqno) + TCP_TCPLEN(pcb->unsent), pcb->snd_max)
-           ) {
-      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %lu:%lu from pcb->unsent\n",
-                                    ntohl(pcb->unsent->tcphdr->seqno), ntohl(pcb->unsent->tcphdr->seqno) +
-                                    TCP_TCPLEN(pcb->unsent)));
-
-      next = pcb->unsent;
-      pcb->unsent = pcb->unsent->next;
-      LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %u ... ", (unsigned int)pcb->snd_queuelen));
-      pcb->snd_queuelen -= pbuf_clen(next->p);
-      tcp_seg_free(next);
-      LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%u (after freeing unsent)\n", (unsigned int)pcb->snd_queuelen));
-      if (pcb->snd_queuelen != 0) {
-        LWIP_ASSERT("tcp_receive: valid queue length",
-          pcb->unacked != NULL || pcb->unsent != NULL);
-      }
-
-      if (pcb->unsent != NULL) {
-        pcb->snd_nxt = htonl(pcb->unsent->tcphdr->seqno);
-      }
-    }
-    /* End of ACK for new data processing. */
-
-    LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: pcb->rttest %u rtseq %lu ackno %lu\n",
-                                pcb->rttest, pcb->rtseq, ackno));
-
-    /* RTT estimation calculations. This is done by checking if the
-       incoming segment acknowledges the segment we use to take a
-       round-trip time measurement. */
-    if (pcb->rttest && TCP_SEQ_LT(pcb->rtseq, ackno)) {
-      m = tcp_ticks - pcb->rttest;
-
-      LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: experienced rtt %u ticks (%u msec).\n",
-                                  m, m * TCP_SLOW_INTERVAL));
-
-      /* This is taken directly from VJs original code in his paper */
-      m = m - (pcb->sa >> 3);
-      pcb->sa += m;
-      if (m < 0) {
-        m = -m;
-      }
-      m = m - (pcb->sv >> 2);
-      pcb->sv += m;
-      pcb->rto = (pcb->sa >> 3) + pcb->sv;
-
-      LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: RTO %u (%u miliseconds)\n",
-                                  pcb->rto, pcb->rto * TCP_SLOW_INTERVAL));
-
-      pcb->rttest = 0;
-    }
-  }
-
-  /* If the incoming segment contains data, we must process it
-     further. */
-  if (tcplen > 0) {
-    /* This code basically does three things:
-
-    +) If the incoming segment contains data that is the next
-    in-sequence data, this data is passed to the application. This
-    might involve trimming the first edge of the data. The rcv_nxt
-    variable and the advertised window are adjusted.
-
-    +) If the incoming segment has data that is above the next
-    sequence number expected (->rcv_nxt), the segment is placed on
-    the ->ooseq queue. This is done by finding the appropriate
-    place in the ->ooseq queue (which is ordered by sequence
-    number) and trim the segment in both ends if needed. An
-    immediate ACK is sent to indicate that we received an
-    out-of-sequence segment.
-
-    +) Finally, we check if the first segment on the ->ooseq queue
-    now is in sequence (i.e., if rcv_nxt >= ooseq->seqno). If
-    rcv_nxt > ooseq->seqno, we must trim the first edge of the
-    segment on ->ooseq before we adjust rcv_nxt. The data in the
-    segments that are now on sequence are chained onto the
-    incoming segment so that we only need to call the application
-    once.
-    */
-
-    /* First, we check if we must trim the first edge. We have to do
-       this if the sequence number of the incoming segment is less
-       than rcv_nxt, and the sequence number plus the length of the
-       segment is larger than rcv_nxt. */
-    /*    if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)){
-          if (TCP_SEQ_LT(pcb->rcv_nxt, seqno + tcplen)) {*/
-    if(TCP_SEQ_BETWEEN(pcb->rcv_nxt, seqno+1, seqno+tcplen-1)){
-      /* Trimming the first edge is done by pushing the payload
-         pointer in the pbuf downwards. This is somewhat tricky since
-         we do not want to discard the full contents of the pbuf up to
-         the new starting point of the data since we have to keep the
-         TCP header which is present in the first pbuf in the chain.
-         
-         What is done is really quite a nasty hack: the first pbuf in
-         the pbuf chain is pointed to by inseg.p. Since we need to be
-         able to deallocate the whole pbuf, we cannot change this
-         inseg.p pointer to point to any of the later pbufs in the
-         chain. Instead, we point the ->payload pointer in the first
-         pbuf to data in one of the later pbufs. We also set the
-         inseg.data pointer to point to the right place. This way, the
-         ->p pointer will still point to the first pbuf, but the
-         ->p->payload pointer will point to data in another pbuf.
-         
-         After we are done with adjusting the pbuf pointers we must
-         adjust the ->data pointer in the seg and the segment
-         length.*/
-      
-      off = pcb->rcv_nxt - seqno;
-      p = inseg.p;
-      if (inseg.p->len < off) {
-        new_tot_len = inseg.p->tot_len - off;
-        while (p->len < off) {
-          off -= p->len;
-          /* KJM following line changed (with addition of new_tot_len var)
-             to fix bug #9076
-             inseg.p->tot_len -= p->len; */
-          p->tot_len = new_tot_len;
-          p->len = 0;
-          p = p->next;
-        }
-        pbuf_header(p, -off);
-      } else {
-        pbuf_header(inseg.p, -off);
-      }
-      /* KJM following line changed to use p->payload rather than inseg->p->payload
-         to fix bug #9076 */
-      inseg.dataptr = p->payload;
-      inseg.len -= pcb->rcv_nxt - seqno;
-      inseg.tcphdr->seqno = seqno = pcb->rcv_nxt;
-    }
-    else{
-      if(TCP_SEQ_LT(seqno, pcb->rcv_nxt)){
-        /* the whole segment is < rcv_nxt */
-        /* must be a duplicate of a packet that has already been correctly handled */
-        
-        LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: duplicate seqno %lu\n", seqno));
-        tcp_ack_now(pcb);
-      }
-    }
-
-    /* The sequence number must be within the window (above rcv_nxt
-       and below rcv_nxt + rcv_wnd) in order to be further
-       processed. */
-    /*if (TCP_SEQ_GEQ(seqno, pcb->rcv_nxt) &&
-      TCP_SEQ_LT(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {*/
-    if(TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd - 1)){
-      if (pcb->rcv_nxt == seqno) {
-        /* The incoming segment is the next in sequence. We check if
-           we have to trim the end of the segment and update rcv_nxt
-           and pass the data to the application. */
-#if TCP_QUEUE_OOSEQ
-        if (pcb->ooseq != NULL &&
-            TCP_SEQ_LEQ(pcb->ooseq->tcphdr->seqno, seqno + inseg.len)) {
-          /* We have to trim the second edge of the incoming
-             segment. */
-          inseg.len = pcb->ooseq->tcphdr->seqno - seqno;
-          pbuf_realloc(inseg.p, inseg.len);
-        }
-#endif /* TCP_QUEUE_OOSEQ */
-
-        tcplen = TCP_TCPLEN(&inseg);
-
-        pcb->rcv_nxt += tcplen;
-
-        /* Update the receiver's (our) window. */
-        if (pcb->rcv_wnd < tcplen) {
-          pcb->rcv_wnd = 0;
-        } else {
-          pcb->rcv_wnd -= tcplen;
-        }
-
-        /* If there is data in the segment, we make preparations to
-           pass this up to the application. The ->recv_data variable
-           is used for holding the pbuf that goes to the
-           application. The code for reassembling out-of-sequence data
-           chains its data on this pbuf as well.
-
-           If the segment was a FIN, we set the TF_GOT_FIN flag that will
-           be used to indicate to the application that the remote side has
-           closed its end of the connection. */
-        if (inseg.p->tot_len > 0) {
-          recv_data = inseg.p;
-          /* Since this pbuf now is the responsibility of the
-             application, we delete our reference to it so that we won't
-             (mistakingly) deallocate it. */
-          inseg.p = NULL;
-        }
-        if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) {
-          LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: received FIN.\n"));
-          recv_flags = TF_GOT_FIN;
-        }
-
-#if TCP_QUEUE_OOSEQ
-        /* We now check if we have segments on the ->ooseq queue that
-           is now in sequence. */
-        while (pcb->ooseq != NULL &&
-               pcb->ooseq->tcphdr->seqno == pcb->rcv_nxt) {
-
-          cseg = pcb->ooseq;
-          seqno = pcb->ooseq->tcphdr->seqno;
-
-          pcb->rcv_nxt += TCP_TCPLEN(cseg);
-          if (pcb->rcv_wnd < TCP_TCPLEN(cseg)) {
-            pcb->rcv_wnd = 0;
-          } else {
-            pcb->rcv_wnd -= TCP_TCPLEN(cseg);
-          }
-          if (cseg->p->tot_len > 0) {
-            /* Chain this pbuf onto the pbuf that we will pass to
-               the application. */
-            if (recv_data) {
-              pbuf_cat(recv_data, cseg->p);
-            } else {
-              recv_data = cseg->p;
-            }
-            cseg->p = NULL;
-          }
-          if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) {
-            LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: dequeued FIN.\n"));
-            recv_flags = TF_GOT_FIN;
-          }
-
-
-          pcb->ooseq = cseg->next;
-          tcp_seg_free(cseg);
-        }
-#endif /* TCP_QUEUE_OOSEQ */
-
-
-        /* Acknowledge the segment(s). */
-        tcp_ack(pcb);
-
-      } else {
-        /* We get here if the incoming segment is out-of-sequence. */
-        tcp_ack_now(pcb);
-#if TCP_QUEUE_OOSEQ
-        /* We queue the segment on the ->ooseq queue. */
-        if (pcb->ooseq == NULL) {
-          pcb->ooseq = tcp_seg_copy(&inseg);
-        } else {
-          /* If the queue is not empty, we walk through the queue and
-             try to find a place where the sequence number of the
-             incoming segment is between the sequence numbers of the
-             previous and the next segment on the ->ooseq queue. That is
-             the place where we put the incoming segment. If needed, we
-             trim the second edges of the previous and the incoming
-             segment so that it will fit into the sequence.
-
-             If the incoming segment has the same sequence number as a
-             segment on the ->ooseq queue, we discard the segment that
-             contains less data. */
-
-          prev = NULL;
-          for(next = pcb->ooseq; next != NULL; next = next->next) {
-            if (seqno == next->tcphdr->seqno) {
-              /* The sequence number of the incoming segment is the
-                 same as the sequence number of the segment on
-                 ->ooseq. We check the lengths to see which one to
-                 discard. */
-              if (inseg.len > next->len) {
-                /* The incoming segment is larger than the old
-                   segment. We replace the old segment with the new
-                   one. */
-                cseg = tcp_seg_copy(&inseg);
-                if (cseg != NULL) {
-                  cseg->next = next->next;
-                  if (prev != NULL) {
-                    prev->next = cseg;
-                  } else {
-                    pcb->ooseq = cseg;
-                  }
-                }
-                break;
-              } else {
-                /* Either the lenghts are the same or the incoming
-                   segment was smaller than the old one; in either
-                   case, we ditch the incoming segment. */
-                break;
-              }
-            } else {
-              if (prev == NULL) {
-                if (TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {
-                  /* The sequence number of the incoming segment is lower
-                     than the sequence number of the first segment on the
-                     queue. We put the incoming segment first on the
-                     queue. */
-
-                  if (TCP_SEQ_GT(seqno + inseg.len, next->tcphdr->seqno)) {
-                    /* We need to trim the incoming segment. */
-                    inseg.len = next->tcphdr->seqno - seqno;
-                    pbuf_realloc(inseg.p, inseg.len);
-                  }
-                  cseg = tcp_seg_copy(&inseg);
-                  if (cseg != NULL) {
-                    cseg->next = next;
-                    pcb->ooseq = cseg;
-                  }
-                  break;
-                }
-              } else 
-                /*if (TCP_SEQ_LT(prev->tcphdr->seqno, seqno) &&
-                  TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {*/
-                if(TCP_SEQ_BETWEEN(seqno, prev->tcphdr->seqno+1, next->tcphdr->seqno-1)){
-                /* The sequence number of the incoming segment is in
-                   between the sequence numbers of the previous and
-                   the next segment on ->ooseq. We trim and insert the
-                   incoming segment and trim the previous segment, if
-                   needed. */
-                if (TCP_SEQ_GT(seqno + inseg.len, next->tcphdr->seqno)) {
-                  /* We need to trim the incoming segment. */
-                  inseg.len = next->tcphdr->seqno - seqno;
-                  pbuf_realloc(inseg.p, inseg.len);
-                }
-
-                cseg = tcp_seg_copy(&inseg);
-                if (cseg != NULL) {
-                  cseg->next = next;
-                  prev->next = cseg;
-                  if (TCP_SEQ_GT(prev->tcphdr->seqno + prev->len, seqno)) {
-                    /* We need to trim the prev segment. */
-                    prev->len = seqno - prev->tcphdr->seqno;
-                    pbuf_realloc(prev->p, prev->len);
-                  }
-                }
-                break;
-              }
-              /* If the "next" segment is the last segment on the
-                 ooseq queue, we add the incoming segment to the end
-                 of the list. */
-              if (next->next == NULL &&
-                  TCP_SEQ_GT(seqno, next->tcphdr->seqno)) {
-                next->next = tcp_seg_copy(&inseg);
-                if (next->next != NULL) {
-                  if (TCP_SEQ_GT(next->tcphdr->seqno + next->len, seqno)) {
-                    /* We need to trim the last segment. */
-                    next->len = seqno - next->tcphdr->seqno;
-                    pbuf_realloc(next->p, next->len);
-                  }
-                }
-                break;
-              }
-            }
-            prev = next;
-          }
-        }
-#endif /* TCP_QUEUE_OOSEQ */
-
-      }
-    } else {
-      /*if (TCP_SEQ_GT(pcb->rcv_nxt, seqno) ||
-        TCP_SEQ_GEQ(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {*/
-      if(!TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd-1)){
-        tcp_ack_now(pcb);
-      }
-    }
-  } else {
-    /* Segments with length 0 is taken care of here. Segments that
-       fall out of the window are ACKed. */
-    /*if (TCP_SEQ_GT(pcb->rcv_nxt, seqno) ||
-      TCP_SEQ_GEQ(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {*/
-    if(!TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd-1)){
-      tcp_ack_now(pcb);
-    }
-  }
-}
-
-/*
- * tcp_parseopt:
- *
- * Parses the options contained in the incoming segment. (Code taken
- * from uIP with only small changes.)
- *
- */
-
-static void
-tcp_parseopt(struct tcp_pcb *pcb)
-{
-  u8_t c;
-  u8_t *opts, opt;
-  u16_t mss;
-
-  opts = (u8_t *)tcphdr + TCP_HLEN;
-
-  /* Parse the TCP MSS option, if present. */
-  if(TCPH_HDRLEN(tcphdr) > 0x5) {
-    for(c = 0; c < (TCPH_HDRLEN(tcphdr) - 5) << 2 ;) {
-      opt = opts[c];
-      if (opt == 0x00) {
-        /* End of options. */
-  break;
-      } else if (opt == 0x01) {
-        ++c;
-        /* NOP option. */
-      } else if (opt == 0x02 &&
-        opts[c + 1] == 0x04) {
-        /* An MSS option with the right option length. */
-        mss = (opts[c + 2] << 8) | opts[c + 3];
-        pcb->mss = mss > TCP_MSS? TCP_MSS: mss;
-
-        /* And we are done processing options. */
-        break;
-      } else {
-  if (opts[c + 1] == 0) {
-          /* If the length field is zero, the options are malformed
-             and we don't process them further. */
-          break;
-        }
-        /* All other options have a length field, so that we easily
-           can skip past them. */
-        c += opts[c + 1];
-      }
-    }
-  }
-}
-#endif /* LWIP_TCP */
-
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/tcp_out.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/tcp_out.c
deleted file mode 100644
index a2ecb2faa..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/tcp_out.c
+++ /dev/null
@@ -1,724 +0,0 @@
-/**
- * @file
- *
- * Transmission Control Protocol, outgoing traffic
- *
- * The output functions of TCP.
- *
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels 
- *
- */
-
-#include "lwip/def.h"
-#include "lwip/opt.h"
-
-#include "lwip/mem.h"
-#include "lwip/memp.h"
-#include "lwip/sys.h"
-
-#include "lwip/ip_addr.h"
-#include "lwip/netif.h"
-
-#include "lwip/inet.h"
-#include "lwip/tcp.h"
-
-#include "lwip/stats.h"
-
-#include 
-
-#if LWIP_TCP
-
-/* Forward declarations.*/
-static void tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb);
-
-err_t
-tcp_send_ctrl(struct tcp_pcb *pcb, u8_t flags)
-{
-  /* no data, no length, flags, copy=1, no optdata, no optdatalen */
-  return tcp_enqueue(pcb, NULL, 0, flags, 1, NULL, 0);
-}
-
-/**
- * Write data for sending (but does not send it immediately).
- *
- * It waits in the expectation of more data being sent soon (as
- * it can send them more efficiently by combining them together).
- * To prompt the system to send data now, call tcp_output() after
- * calling tcp_write().
- * 
- * @arg pcb Protocol control block of the TCP connection to enqueue data for. 
- * 
- * @see tcp_write()
- */
-
-err_t
-tcp_write(struct tcp_pcb *pcb, const void *arg, u16_t len, u8_t copy)
-{
-  LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_write(pcb=%p, arg=%p, len=%u, copy=%d)\n", (void *)pcb,
-    arg, len, (unsigned int)copy));
-  /* connection is in valid state for data transmission? */
-  if (pcb->state == ESTABLISHED ||
-     pcb->state == CLOSE_WAIT ||
-     pcb->state == SYN_SENT ||
-     pcb->state == SYN_RCVD) {
-    if (len > 0) {
-      return tcp_enqueue(pcb, (void *)arg, len, 0, copy, NULL, 0);
-    }
-    return ERR_OK;
-  } else {
-    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | DBG_STATE | 3, ("tcp_write() called in invalid state\n"));
-    return ERR_CONN;
-  }
-}
-
-/**
- * Enqueue either data or TCP options (but not both) for tranmission
- * 
- * 
- * 
- * @arg pcb Protocol control block for the TCP connection to enqueue data for.
- * @arg arg Pointer to the data to be enqueued for sending.
- * @arg len Data length in bytes
- * @arg flags
- * @arg copy 1 if data must be copied, 0 if data is non-volatile and can be
- * referenced.
- * @arg optdata
- * @arg optlen
- */
-err_t
-tcp_enqueue(struct tcp_pcb *pcb, void *arg, u16_t len,
-  u8_t flags, u8_t copy,
-  u8_t *optdata, u8_t optlen)
-{
-  struct pbuf *p;
-  struct tcp_seg *seg, *useg, *queue=NULL;
-  u32_t left, seqno;
-  u16_t seglen;
-  void *ptr;
-  u8_t queuelen;
-
-  LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_enqueue(pcb=%p, arg=%p, len=%u, flags=%x, copy=%u)\n",
-    (void *)pcb, arg, len, (unsigned int)flags, (unsigned int)copy));
-  LWIP_ASSERT("tcp_enqueue: len == 0 || optlen == 0 (programmer violates API)",
-      len == 0 || optlen == 0);
-  LWIP_ASSERT("tcp_enqueue: arg == NULL || optdata == NULL (programmer violates API)",
-      arg == NULL || optdata == NULL);
-  /* fail on too much data */
-  if (len > pcb->snd_buf) {
-    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 3, ("tcp_enqueue: too much data (len=%u > snd_buf=%u)\n", len, pcb->snd_buf));
-    return ERR_MEM;
-  }
-  left = len;
-  ptr = arg;
-
-  /* seqno will be the sequence number of the first segment enqueued
-   * by the call to this function. */
-  seqno = pcb->snd_lbb;
-
-  LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue: queuelen: %u\n", (unsigned int)pcb->snd_queuelen));
-
-  /* If total number of pbufs on the unsent/unacked queues exceeds the
-   * configured maximum, return an error */
-  queuelen = pcb->snd_queuelen;
-  if (queuelen >= TCP_SND_QUEUELEN) {
-    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 3, ("tcp_enqueue: too long queue %u (max %u)\n", queuelen, TCP_SND_QUEUELEN));
-    goto memerr;
-  }
-  if (queuelen != 0) {
-    LWIP_ASSERT("tcp_enqueue: pbufs on queue => at least one queue non-empty",
-      pcb->unacked != NULL || pcb->unsent != NULL);
-  } else {
-    LWIP_ASSERT("tcp_enqueue: no pbufs on queue => both queues empty",
-      pcb->unacked == NULL && pcb->unsent == NULL);
-  }
-
-  /* First, break up the data into segments and tuck them together in
-   * the local "queue" variable. */
-  useg = NULL;
-  queue = NULL;
-  seg = NULL;
-  seglen = 0;
-  while (queue == NULL || left > 0) {
-
-    /* The segment length should be the MSS if the data to be enqueued
-     * is larger than the MSS. */
-    seglen = left > pcb->mss? pcb->mss: left;
-
-    /* Allocate memory for tcp_seg, and fill in fields. */
-    seg = memp_malloc(MEMP_TCP_SEG);
-    if (seg == NULL) {
-      LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: could not allocate memory for tcp_seg\n"));
-      goto memerr;
-    }
-    seg->next = NULL;
-    seg->p = NULL;
-
-    /* first segment of to-be-queued data? */
-    if (queue == NULL) {
-      queue = seg;
-    }
-    /* subsequent segments of to-be-queued data */
-    else {
-      /* Attach the segment to the end of the queued segments */
-      LWIP_ASSERT("useg != NULL", useg != NULL);
-      useg->next = seg;
-    }
-    /* remember last segment of to-be-queued data for next iteration */
-    useg = seg;
-
-    /* If copy is set, memory should be allocated
-     * and data copied into pbuf, otherwise data comes from
-     * ROM or other static memory, and need not be copied. If
-     * optdata is != NULL, we have options instead of data. */
-     
-    /* options? */
-    if (optdata != NULL) {
-      if ((seg->p = pbuf_alloc(PBUF_TRANSPORT, optlen, PBUF_RAM)) == NULL) {
-        goto memerr;
-      }
-      ++queuelen;
-      seg->dataptr = seg->p->payload;
-    }
-    /* copy from volatile memory? */
-    else if (copy) {
-      if ((seg->p = pbuf_alloc(PBUF_TRANSPORT, seglen, PBUF_RAM)) == NULL) {
-        LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue : could not allocate memory for pbuf copy size %u\n", seglen));
-        goto memerr;
-      }
-      ++queuelen;
-      if (arg != NULL) {
-        memcpy(seg->p->payload, ptr, seglen);
-      }
-      seg->dataptr = seg->p->payload;
-    }
-    /* do not copy data */
-    else {
-      /* First, allocate a pbuf for holding the data.
-       * since the referenced data is available at least until it is sent out on the
-       * link (as it has to be ACKed by the remote party) we can safely use PBUF_ROM
-       * instead of PBUF_REF here.
-       */
-      if ((p = pbuf_alloc(PBUF_TRANSPORT, seglen, PBUF_ROM)) == NULL) {
-        LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: could not allocate memory for zero-copy pbuf\n"));
-        goto memerr;
-      }
-      ++queuelen;
-      /* reference the non-volatile payload data */
-      p->payload = ptr;
-      seg->dataptr = ptr;
-
-      /* Second, allocate a pbuf for the headers. */
-      if ((seg->p = pbuf_alloc(PBUF_TRANSPORT, 0, PBUF_RAM)) == NULL) {
-        /* If allocation fails, we have to deallocate the data pbuf as
-         * well. */
-        pbuf_free(p);
-        LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: could not allocate memory for header pbuf\n"));
-        goto memerr;
-      }
-      ++queuelen;
-
-      /* Concatenate the headers and data pbufs together. */
-      pbuf_cat(seg->p/*header*/, p/*data*/);
-      p = NULL;
-    }
-
-    /* Now that there are more segments queued, we check again if the
-    length of the queue exceeds the configured maximum. */
-    if (queuelen > TCP_SND_QUEUELEN) {
-      LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: queue too long %u (%u)\n", queuelen, TCP_SND_QUEUELEN));
-      goto memerr;
-    }
-
-    seg->len = seglen;
-
-    /* build TCP header */
-    if (pbuf_header(seg->p, TCP_HLEN)) {
-      LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: no room for TCP header in pbuf.\n"));
-      TCP_STATS_INC(tcp.err);
-      goto memerr;
-    }
-    seg->tcphdr = seg->p->payload;
-    seg->tcphdr->src = htons(pcb->local_port);
-    seg->tcphdr->dest = htons(pcb->remote_port);
-    seg->tcphdr->seqno = htonl(seqno);
-    seg->tcphdr->urgp = 0;
-    TCPH_FLAGS_SET(seg->tcphdr, flags);
-    /* don't fill in tcphdr->ackno and tcphdr->wnd until later */
-
-    /* Copy the options into the header, if they are present. */
-    if (optdata == NULL) {
-      TCPH_HDRLEN_SET(seg->tcphdr, 5);
-    }
-    else {
-      TCPH_HDRLEN_SET(seg->tcphdr, (5 + optlen / 4));
-      /* Copy options into data portion of segment.
-       Options can thus only be sent in non data carrying
-       segments such as SYN|ACK. */
-      memcpy(seg->dataptr, optdata, optlen);
-    }
-    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | DBG_TRACE, ("tcp_enqueue: queueing %lu:%lu (0x%x)\n",
-      ntohl(seg->tcphdr->seqno),
-      ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg),
-      flags));
-
-    left -= seglen;
-    seqno += seglen;
-    ptr = (void *)((char *)ptr + seglen);
-  }
-
-  /* Now that the data to be enqueued has been broken up into TCP
-  segments in the queue variable, we add them to the end of the
-  pcb->unsent queue. */
-  if (pcb->unsent == NULL) {
-    useg = NULL;
-  }
-  else {
-    for (useg = pcb->unsent; useg->next != NULL; useg = useg->next);
-  }
-  /* { useg is last segment on the unsent queue, NULL if list is empty } */
-
-  /* If there is room in the last pbuf on the unsent queue,
-  chain the first pbuf on the queue together with that. */
-  if (useg != NULL &&
-    TCP_TCPLEN(useg) != 0 &&
-    !(TCPH_FLAGS(useg->tcphdr) & (TCP_SYN | TCP_FIN)) &&
-    !(flags & (TCP_SYN | TCP_FIN)) &&
-    /* fit within max seg size */
-    useg->len + queue->len <= pcb->mss) {
-    /* Remove TCP header from first segment of our to-be-queued list */
-    pbuf_header(queue->p, -TCP_HLEN);
-    pbuf_cat(useg->p, queue->p);
-    useg->len += queue->len;
-    useg->next = queue->next;
-
-    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | DBG_TRACE | DBG_STATE, ("tcp_enqueue: chaining segments, new len %u\n", useg->len));
-    if (seg == queue) {
-      seg = NULL;
-    }
-    memp_free(MEMP_TCP_SEG, queue);
-  }
-  else {
-    /* empty list */
-    if (useg == NULL) {
-      /* initialize list with this segment */
-      pcb->unsent = queue;
-    }
-    /* enqueue segment */
-    else {
-      useg->next = queue;
-    }
-  }
-  if ((flags & TCP_SYN) || (flags & TCP_FIN)) {
-    ++len;
-  }
-  pcb->snd_lbb += len;
-  pcb->snd_buf -= len;
-  /* update number of segments on the queues */
-  pcb->snd_queuelen = queuelen;
-  LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue: %d (after enqueued)\n", pcb->snd_queuelen));
-  if (pcb->snd_queuelen != 0) {
-    LWIP_ASSERT("tcp_enqueue: valid queue length",
-      pcb->unacked != NULL || pcb->unsent != NULL);
-  }
-
-  /* Set the PSH flag in the last segment that we enqueued, but only
-  if the segment has data (indicated by seglen > 0). */
-  if (seg != NULL && seglen > 0 && seg->tcphdr != NULL) {
-    TCPH_SET_FLAG(seg->tcphdr, TCP_PSH);
-  }
-
-  return ERR_OK;
-  memerr:
-  TCP_STATS_INC(tcp.memerr);
-
-  if (queue != NULL) {
-    tcp_segs_free(queue);
-  }
-  if (pcb->snd_queuelen != 0) {
-    LWIP_ASSERT("tcp_enqueue: valid queue length", pcb->unacked != NULL ||
-      pcb->unsent != NULL);
-  }
-  LWIP_DEBUGF(TCP_QLEN_DEBUG | DBG_STATE, ("tcp_enqueue: %d (with mem err)\n", pcb->snd_queuelen));
-  return ERR_MEM;
-}
-
-/* find out what we can send and send it */
-err_t
-tcp_output(struct tcp_pcb *pcb)
-{
-  struct pbuf *p;
-  struct tcp_hdr *tcphdr;
-  struct tcp_seg *seg, *useg;
-  u32_t wnd;
-#if TCP_CWND_DEBUG
-  int i = 0;
-#endif /* TCP_CWND_DEBUG */
-
-  /* First, check if we are invoked by the TCP input processing
-     code. If so, we do not output anything. Instead, we rely on the
-     input processing code to call us when input processing is done
-     with. */
-  if (tcp_input_pcb == pcb) {
-    return ERR_OK;
-  }
-
-  wnd = LWIP_MIN(pcb->snd_wnd, pcb->cwnd);
-
-  seg = pcb->unsent;
-
-  /* useg should point to last segment on unacked queue */
-  useg = pcb->unacked;
-  if (useg != NULL) {
-    for (; useg->next != NULL; useg = useg->next);
-  }                                                                             
-   
-  /* If the TF_ACK_NOW flag is set and no data will be sent (either
-   * because the ->unsent queue is empty or because the window does
-   * not allow it), construct an empty ACK segment and send it.
-   *
-   * If data is to be sent, we will just piggyback the ACK (see below).
-   */
-  if (pcb->flags & TF_ACK_NOW &&
-     (seg == NULL ||
-      ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len > wnd)) {
-    p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM);
-    if (p == NULL) {
-      LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: (ACK) could not allocate pbuf\n"));
-      return ERR_BUF;
-    }
-    LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: sending ACK for %lu\n", pcb->rcv_nxt));
-    /* remove ACK flags from the PCB, as we send an empty ACK now */
-    pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW);
-
-    tcphdr = p->payload;
-    tcphdr->src = htons(pcb->local_port);
-    tcphdr->dest = htons(pcb->remote_port);
-    tcphdr->seqno = htonl(pcb->snd_nxt);
-    tcphdr->ackno = htonl(pcb->rcv_nxt);
-    TCPH_FLAGS_SET(tcphdr, TCP_ACK);
-    tcphdr->wnd = htons(pcb->rcv_wnd);
-    tcphdr->urgp = 0;
-    TCPH_HDRLEN_SET(tcphdr, 5);
-
-    tcphdr->chksum = 0;
-#if CHECKSUM_GEN_TCP
-    tcphdr->chksum = inet_chksum_pseudo(p, &(pcb->local_ip), &(pcb->remote_ip),
-          IP_PROTO_TCP, p->tot_len);
-#endif
-    ip_output(p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl, pcb->tos,
-        IP_PROTO_TCP);
-    pbuf_free(p);
-
-    return ERR_OK;
-  }
-
-#if TCP_OUTPUT_DEBUG
-  if (seg == NULL) {
-    LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: nothing to send (%p)\n", pcb->unsent));
-  }
-#endif /* TCP_OUTPUT_DEBUG */
-#if TCP_CWND_DEBUG
-  if (seg == NULL) {
-    LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %lu, cwnd %lu, wnd %lu, seg == NULL, ack %lu\n",
-                            pcb->snd_wnd, pcb->cwnd, wnd,
-                            pcb->lastack));
-  } else {
-    LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %lu, cwnd %lu, wnd %lu, effwnd %lu, seq %lu, ack %lu\n",
-                            pcb->snd_wnd, pcb->cwnd, wnd,
-                            ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len,
-                            ntohl(seg->tcphdr->seqno), pcb->lastack));
-  }
-#endif /* TCP_CWND_DEBUG */
-  /* data available and window allows it to be sent? */
-  while (seg != NULL &&
-  ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len <= wnd) {
-#if TCP_CWND_DEBUG
-    LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %lu, cwnd %lu, wnd %lu, effwnd %lu, seq %lu, ack %lu, i%d\n",
-                            pcb->snd_wnd, pcb->cwnd, wnd,
-                            ntohl(seg->tcphdr->seqno) + seg->len -
-                            pcb->lastack,
-                            ntohl(seg->tcphdr->seqno), pcb->lastack, i));
-    ++i;
-#endif /* TCP_CWND_DEBUG */
-
-    pcb->unsent = seg->next;
-
-    if (pcb->state != SYN_SENT) {
-      TCPH_SET_FLAG(seg->tcphdr, TCP_ACK);
-      pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW);
-    }
-
-    tcp_output_segment(seg, pcb);
-    pcb->snd_nxt = ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg);
-    if (TCP_SEQ_LT(pcb->snd_max, pcb->snd_nxt)) {
-      pcb->snd_max = pcb->snd_nxt;
-    }
-    /* put segment on unacknowledged list if length > 0 */
-    if (TCP_TCPLEN(seg) > 0) {
-      seg->next = NULL;
-      /* unacked list is empty? */
-      if (pcb->unacked == NULL) {
-        pcb->unacked = seg;
-        useg = seg;
-      /* unacked list is not empty? */
-      } else {
-        /* In the case of fast retransmit, the packet should not go to the tail
-         * of the unacked queue, but rather at the head. We need to check for
-         * this case. -STJ Jul 27, 2004 */
-        if (TCP_SEQ_LT(ntohl(seg->tcphdr->seqno), ntohl(useg->tcphdr->seqno))){
-          /* add segment to head of unacked list */
-          seg->next = pcb->unacked;
-          pcb->unacked = seg;
-        } else {
-          /* add segment to tail of unacked list */
-          useg->next = seg;
-          useg = useg->next;
-        }
-      }
-    /* do not queue empty segments on the unacked list */
-    } else {
-      tcp_seg_free(seg);
-    }
-    seg = pcb->unsent;
-  }
-  return ERR_OK;
-}
-
-/**
- * Actually send a TCP segment over IP
- */
-static void
-tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb)
-{
-  u16_t len;
-  struct netif *netif;
-
-  /* The TCP header has already been constructed, but the ackno and
-   wnd fields remain. */
-  seg->tcphdr->ackno = htonl(pcb->rcv_nxt);
-
-  /* silly window avoidance */
-  if (pcb->rcv_wnd < pcb->mss) {
-    seg->tcphdr->wnd = 0;
-  } else {
-    /* advertise our receive window size in this TCP segment */
-    seg->tcphdr->wnd = htons(pcb->rcv_wnd);
-  }
-
-  /* If we don't have a local IP address, we get one by
-     calling ip_route(). */
-  if (ip_addr_isany(&(pcb->local_ip))) {
-    netif = ip_route(&(pcb->remote_ip));
-    if (netif == NULL) {
-      return;
-    }
-    ip_addr_set(&(pcb->local_ip), &(netif->ip_addr));
-  }
-
-  pcb->rtime = 0;
-
-  if (pcb->rttest == 0) {
-    pcb->rttest = tcp_ticks;
-    pcb->rtseq = ntohl(seg->tcphdr->seqno);
-
-    LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_output_segment: rtseq %lu\n", pcb->rtseq));
-  }
-  LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output_segment: %lu:%lu\n",
-          htonl(seg->tcphdr->seqno), htonl(seg->tcphdr->seqno) +
-          seg->len));
-
-  len = (u16_t)((u8_t *)seg->tcphdr - (u8_t *)seg->p->payload);
-
-  seg->p->len -= len;
-  seg->p->tot_len -= len;
-
-  seg->p->payload = seg->tcphdr;
-
-  seg->tcphdr->chksum = 0;
-#if CHECKSUM_GEN_TCP
-  seg->tcphdr->chksum = inet_chksum_pseudo(seg->p,
-             &(pcb->local_ip),
-             &(pcb->remote_ip),
-             IP_PROTO_TCP, seg->p->tot_len);
-#endif
-  TCP_STATS_INC(tcp.xmit);
-
-  ip_output(seg->p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl, pcb->tos,
-      IP_PROTO_TCP);
-}
-
-void
-tcp_rst(u32_t seqno, u32_t ackno,
-  struct ip_addr *local_ip, struct ip_addr *remote_ip,
-  u16_t local_port, u16_t remote_port)
-{
-  struct pbuf *p;
-  struct tcp_hdr *tcphdr;
-  p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM);
-  if (p == NULL) {
-      LWIP_DEBUGF(TCP_DEBUG, ("tcp_rst: could not allocate memory for pbuf\n"));
-      return;
-  }
-
-  tcphdr = p->payload;
-  tcphdr->src = htons(local_port);
-  tcphdr->dest = htons(remote_port);
-  tcphdr->seqno = htonl(seqno);
-  tcphdr->ackno = htonl(ackno);
-  TCPH_FLAGS_SET(tcphdr, TCP_RST | TCP_ACK);
-  tcphdr->wnd = htons(TCP_WND);
-  tcphdr->urgp = 0;
-  TCPH_HDRLEN_SET(tcphdr, 5);
-
-  tcphdr->chksum = 0;
-#if CHECKSUM_GEN_TCP
-  tcphdr->chksum = inet_chksum_pseudo(p, local_ip, remote_ip,
-              IP_PROTO_TCP, p->tot_len);
-#endif
-  TCP_STATS_INC(tcp.xmit);
-   /* Send output with hardcoded TTL since we have no access to the pcb */
-  ip_output(p, local_ip, remote_ip, TCP_TTL, 0, IP_PROTO_TCP);
-  pbuf_free(p);
-  LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_rst: seqno %lu ackno %lu.\n", seqno, ackno));
-}
-
-/* requeue all unacked segments for retransmission */
-void
-tcp_rexmit_rto(struct tcp_pcb *pcb)
-{
-  struct tcp_seg *seg;
-
-  if (pcb->unacked == NULL) {
-    return;
-  }
-
-  /* Move all unacked segments to the head of the unsent queue */
-  for (seg = pcb->unacked; seg->next != NULL; seg = seg->next);
-  /* concatenate unsent queue after unacked queue */
-  seg->next = pcb->unsent;
-  /* unsent queue is the concatenated queue (of unacked, unsent) */
-  pcb->unsent = pcb->unacked;
-  /* unacked queue is now empty */
-  pcb->unacked = NULL;
-
-  pcb->snd_nxt = ntohl(pcb->unsent->tcphdr->seqno);
-  /* increment number of retransmissions */
-  ++pcb->nrtx;
-
-  /* Don't take any RTT measurements after retransmitting. */
-  pcb->rttest = 0;
-
-  /* Do the actual retransmission */
-  tcp_output(pcb);
-}
-
-void
-tcp_rexmit(struct tcp_pcb *pcb)
-{
-  struct tcp_seg *seg;
-
-  if (pcb->unacked == NULL) {
-    return;
-  }
-
-  /* Move the first unacked segment to the unsent queue */
-  seg = pcb->unacked->next;
-  pcb->unacked->next = pcb->unsent;
-  pcb->unsent = pcb->unacked;
-  pcb->unacked = seg;
-
-  pcb->snd_nxt = ntohl(pcb->unsent->tcphdr->seqno);
-
-  ++pcb->nrtx;
-
-  /* Don't take any rtt measurements after retransmitting. */
-  pcb->rttest = 0;
-
-  /* Do the actual retransmission. */
-  tcp_output(pcb);
-
-}
-
-
-void
-tcp_keepalive(struct tcp_pcb *pcb)
-{
-   struct pbuf *p;
-   struct tcp_hdr *tcphdr;
-
-   LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: sending KEEPALIVE probe to %u.%u.%u.%u\n",
-                           ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip),
-                           ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip)));
-
-   LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: tcp_ticks %lu   pcb->tmr %lu  pcb->keep_cnt %u\n", tcp_ticks, pcb->tmr, pcb->keep_cnt));
-   
-   p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM);
-
-   if(p == NULL) {
-      LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: could not allocate memory for pbuf\n"));
-      return;
-   }
-
-   tcphdr = p->payload;
-   tcphdr->src = htons(pcb->local_port);
-   tcphdr->dest = htons(pcb->remote_port);
-   tcphdr->seqno = htonl(pcb->snd_nxt - 1);
-   tcphdr->ackno = htonl(pcb->rcv_nxt);
-   tcphdr->wnd = htons(pcb->rcv_wnd);
-   tcphdr->urgp = 0;
-   TCPH_HDRLEN_SET(tcphdr, 5);
-   
-   tcphdr->chksum = 0;
-#if CHECKSUM_GEN_TCP
-   tcphdr->chksum = inet_chksum_pseudo(p, &pcb->local_ip, &pcb->remote_ip, IP_PROTO_TCP, p->tot_len);
-#endif
-  TCP_STATS_INC(tcp.xmit);
-
-   /* Send output to IP */
-  ip_output(p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl, 0, IP_PROTO_TCP);
-
-  pbuf_free(p);
-
-  LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_keepalive: seqno %lu ackno %lu.\n", pcb->snd_nxt - 1, pcb->rcv_nxt));
-}
-
-#endif /* LWIP_TCP */
-
-
-
-
-
-
-
-
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/udp.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/udp.c
deleted file mode 100644
index 8343d34dc..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/core/udp.c
+++ /dev/null
@@ -1,801 +0,0 @@
-/**
- * @file
- * User Datagram Protocol module
- *
- */
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels 
- *
- */
-
-
-/* udp.c
- *
- * The code for the User Datagram Protocol UDP.
- *
- */
-
-#include 
-
-#include "lwip/opt.h"
-
-#include "lwip/def.h"
-#include "lwip/memp.h"
-#include "lwip/inet.h"
-#include "lwip/ip_addr.h"
-#include "lwip/netif.h"
-#include "lwip/udp.h"
-#include "lwip/icmp.h"
-
-#include "lwip/stats.h"
-
-#include "arch/perf.h"
-#include "lwip/snmp.h"
-
-/* The list of UDP PCBs */
-#if LWIP_UDP
-/* was static, but we may want to access this from a socket layer */
-struct udp_pcb *udp_pcbs = NULL;
-
-static struct udp_pcb *pcb_cache = NULL;
-
-
-void
-udp_init(void)
-{
-  udp_pcbs = pcb_cache = NULL;
-}
-
-/**
- * Process an incoming UDP datagram.
- *
- * Given an incoming UDP datagram (as a chain of pbufs) this function
- * finds a corresponding UDP PCB and
- *
- * @param pbuf pbuf to be demultiplexed to a UDP PCB.
- * @param netif network interface on which the datagram was received.
- *
- */
-void
-udp_input(struct pbuf *p, struct netif *inp)
-{
-  struct udp_hdr *udphdr;
-  struct udp_pcb *pcb;
-  struct ip_hdr *iphdr;
-  u16_t src, dest;
-
-#if SO_REUSE
-  struct udp_pcb *pcb_temp;
-  int reuse = 0;
-  int reuse_port_1 = 0;
-  int reuse_port_2 = 0;
-#endif /* SO_REUSE */
-  
-  PERF_START;
-
-  UDP_STATS_INC(udp.recv);
-
-  iphdr = p->payload;
-
-  if (pbuf_header(p, -((s16_t)(UDP_HLEN + IPH_HL(iphdr) * 4)))) {
-    /* drop short packets */
-    LWIP_DEBUGF(UDP_DEBUG, ("udp_input: short UDP datagram (%u bytes) discarded\n", p->tot_len));
-    UDP_STATS_INC(udp.lenerr);
-    UDP_STATS_INC(udp.drop);
-    snmp_inc_udpinerrors();
-    pbuf_free(p);
-    goto end;
-  }
-
-  udphdr = (struct udp_hdr *)((u8_t *)p->payload - UDP_HLEN);
-
-  LWIP_DEBUGF(UDP_DEBUG, ("udp_input: received datagram of length %u\n", p->tot_len));
-
-  src = ntohs(udphdr->src);
-  dest = ntohs(udphdr->dest);
-
-  udp_debug_print(udphdr);
-
-  /* print the UDP source and destination */
-  LWIP_DEBUGF(UDP_DEBUG, ("udp (%u.%u.%u.%u, %u) <-- (%u.%u.%u.%u, %u)\n",
-    ip4_addr1(&iphdr->dest), ip4_addr2(&iphdr->dest),
-    ip4_addr3(&iphdr->dest), ip4_addr4(&iphdr->dest), ntohs(udphdr->dest),
-    ip4_addr1(&iphdr->src), ip4_addr2(&iphdr->src),
-    ip4_addr3(&iphdr->src), ip4_addr4(&iphdr->src), ntohs(udphdr->src)));
-
-#if SO_REUSE
-  pcb_temp = udp_pcbs;
-  
- again_1:
-  
-  /* Iterate through the UDP pcb list for a fully matching pcb */
-  for (pcb = pcb_temp; pcb != NULL; pcb = pcb->next) {
-#else  /* SO_REUSE */ 
-  /* Iterate through the UDP pcb list for a fully matching pcb */
-  for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) {
-#endif  /* SO_REUSE */ 
-    /* print the PCB local and remote address */
-    LWIP_DEBUGF(UDP_DEBUG, ("pcb (%u.%u.%u.%u, %u) --- (%u.%u.%u.%u, %u)\n",
-      ip4_addr1(&pcb->local_ip), ip4_addr2(&pcb->local_ip),
-      ip4_addr3(&pcb->local_ip), ip4_addr4(&pcb->local_ip), pcb->local_port,
-      ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip),
-      ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip), pcb->remote_port));
-
-       /* PCB remote port matches UDP source port? */
-    if ((pcb->remote_port == src) &&
-       /* PCB local port matches UDP destination port? */
-       (pcb->local_port == dest) &&
-       /* accepting from any remote (source) IP address? or... */
-       (ip_addr_isany(&pcb->remote_ip) ||
-       /* PCB remote IP address matches UDP source IP address? */
-        ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src))) &&
-       /* accepting on any local (netif) IP address? or... */
-       (ip_addr_isany(&pcb->local_ip) ||
-       /* PCB local IP address matches UDP destination IP address? */
-        ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest)))) {
-#if SO_REUSE
-      if (pcb->so_options & SOF_REUSEPORT) {
-        if(reuse) {
-          /* We processed one PCB already */
-          LWIP_DEBUGF(UDP_DEBUG, ("udp_input: second or later PCB and SOF_REUSEPORT set.\n"));
-        } else {
-          /* First PCB with this address */
-          LWIP_DEBUGF(UDP_DEBUG, ("udp_input: first PCB and SOF_REUSEPORT set.\n"));
-          reuse = 1;
-        }
-        
-        reuse_port_1 = 1; 
-        p->ref++;
-        LWIP_DEBUGF(UDP_DEBUG, ("udp_input: reference counter on PBUF set to %i\n", p->ref));
-      } else {
-        if (reuse) {
-          /* We processed one PCB already */
-          LWIP_DEBUGF(UDP_DEBUG, ("udp_input: second or later PCB but SOF_REUSEPORT not set !\n"));
-        }
-      }
-#endif /* SO_REUSE */
-      break;
-    }
-  }
-  /* no fully matching pcb found? then look for an unconnected pcb */
-  if (pcb == NULL) {
-    /* Iterate through the UDP PCB list for a pcb that matches
-       the local address. */
-
-#if SO_REUSE
-    pcb_temp = udp_pcbs;
-    
-  again_2:
-
-    for (pcb = pcb_temp; pcb != NULL; pcb = pcb->next) {
-#else  /* SO_REUSE */ 
-    for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) {
-#endif  /* SO_REUSE */ 
-      LWIP_DEBUGF(UDP_DEBUG, ("pcb (%u.%u.%u.%u, %u) --- (%u.%u.%u.%u, %u)\n",
-        ip4_addr1(&pcb->local_ip), ip4_addr2(&pcb->local_ip),
-        ip4_addr3(&pcb->local_ip), ip4_addr4(&pcb->local_ip), pcb->local_port,
-        ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip),
-        ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip), pcb->remote_port));
-      /* unconnected? */
-      if (((pcb->flags & UDP_FLAGS_CONNECTED) == 0) &&
-         /* destination port matches? */
-        (pcb->local_port == dest) &&
-        /* not bound to a specific (local) interface address? or... */
-        (ip_addr_isany(&pcb->local_ip) ||
-        /* ...matching interface address? */
-        ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest)))) {
-#if SO_REUSE
-        if (pcb->so_options & SOF_REUSEPORT) {
-          if (reuse) {
-            /* We processed one PCB already */
-            LWIP_DEBUGF(UDP_DEBUG, ("udp_input: second or later PCB and SOF_REUSEPORT set.\n"));
-          } else {
-            /* First PCB with this address */
-            LWIP_DEBUGF(UDP_DEBUG, ("udp_input: first PCB and SOF_REUSEPORT set.\n"));
-            reuse = 1;
-          }
-          
-          reuse_port_2 = 1; 
-          p->ref++;
-          LWIP_DEBUGF(UDP_DEBUG, ("udp_input: reference counter on PBUF set to %i\n", p->ref));
-        } else {
-          if (reuse) {
-            /* We processed one PCB already */
-            LWIP_DEBUGF(UDP_DEBUG, ("udp_input: second or later PCB but SOF_REUSEPORT not set !\n"));
-          }
-        }
-#endif /* SO_REUSE */
-        break;
-      }
-    }
-  }
-
-  /* Check checksum if this is a match or if it was directed at us. */
-  if (pcb != NULL  || ip_addr_cmp(&inp->ip_addr, &iphdr->dest))
-    {
-    LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE, ("udp_input: calculating checksum\n"));
-    pbuf_header(p, UDP_HLEN);
-#ifdef IPv6
-    if (iphdr->nexthdr == IP_PROTO_UDPLITE) {
-#else
-    if (IPH_PROTO(iphdr) == IP_PROTO_UDPLITE) {
-#endif /* IPv4 */
-      /* Do the UDP Lite checksum */
-#if CHECKSUM_CHECK_UDP
-      if (inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src),
-         (struct ip_addr *)&(iphdr->dest),
-         IP_PROTO_UDPLITE, ntohs(udphdr->len)) != 0) {
-  LWIP_DEBUGF(UDP_DEBUG | 2, ("udp_input: UDP Lite datagram discarded due to failing checksum\n"));
-  UDP_STATS_INC(udp.chkerr);
-  UDP_STATS_INC(udp.drop);
-  snmp_inc_udpinerrors();
-  pbuf_free(p);
-  goto end;
-      }
-#endif
-    } else {
-#if CHECKSUM_CHECK_UDP
-      if (udphdr->chksum != 0) {
-  if (inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src),
-       (struct ip_addr *)&(iphdr->dest),
-        IP_PROTO_UDP, p->tot_len) != 0) {
-    LWIP_DEBUGF(UDP_DEBUG | 2, ("udp_input: UDP datagram discarded due to failing checksum\n"));
-
-    UDP_STATS_INC(udp.chkerr);
-    UDP_STATS_INC(udp.drop);
-    snmp_inc_udpinerrors();
-    pbuf_free(p);
-    goto end;
-  }
-      }
-#endif
-    }
-    pbuf_header(p, -UDP_HLEN);
-    if (pcb != NULL) {
-      snmp_inc_udpindatagrams();
-      pcb->recv(pcb->recv_arg, pcb, p, &(iphdr->src), src);
-#if SO_REUSE
-      /* First socket should receive now */
-      if(reuse_port_1 || reuse_port_2) {
-        /* We want to search on next socket after receiving */
-        pcb_temp = pcb->next;
-        
-        if(reuse_port_1) {
-          /* We are searching connected sockets */
-          reuse_port_1 = 0;
-          reuse_port_2 = 0;
-          goto again_1;
-        } else {
-          /* We are searching unconnected sockets */
-          reuse_port_1 = 0;
-          reuse_port_2 = 0;
-          goto again_2;
-        }
-      }
-#endif /* SO_REUSE */ 
-    } else {
-#if SO_REUSE
-      if(reuse) {
-        LWIP_DEBUGF(UDP_DEBUG, ("udp_input: freeing PBUF with reference counter set to %i\n", p->ref));
-        pbuf_free(p);
-        goto end;
-      }
-#endif /* SO_REUSE */
-      LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE, ("udp_input: not for us.\n"));
-
-      /* No match was found, send ICMP destination port unreachable unless
-      destination address was broadcast/multicast. */
-
-      if (!ip_addr_isbroadcast(&iphdr->dest, inp) &&
-          !ip_addr_ismulticast(&iphdr->dest)) {
-
-  /* adjust pbuf pointer */
-  p->payload = iphdr;
-  icmp_dest_unreach(p, ICMP_DUR_PORT);
-      }
-      UDP_STATS_INC(udp.proterr);
-      UDP_STATS_INC(udp.drop);
-    snmp_inc_udpnoports();
-      pbuf_free(p);
-    }
-  } else {
-    pbuf_free(p);
-  }
-  end:
-
-  PERF_STOP("udp_input");
-}
-
-/**
- * Send data to a specified address using UDP.
- *
- * @param pcb UDP PCB used to send the data.
- * @param pbuf chain of pbuf's to be sent.
- * @param dst_ip Destination IP address.
- * @param dst_port Destination UDP port.
- *
- * If the PCB already has a remote address association, it will
- * be restored after the data is sent.
- * 
- * @return lwIP error code.
- * - ERR_OK. Successful. No error occured.
- * - ERR_MEM. Out of memory.
- * - ERR_RTE. Could not find route to destination address.
- *
- * @see udp_disconnect() udp_send()
- */
-err_t
-udp_sendto(struct udp_pcb *pcb, struct pbuf *p,
-  struct ip_addr *dst_ip, u16_t dst_port)
-{
-  err_t err;
-  /* temporary space for current PCB remote address */
-  struct ip_addr pcb_remote_ip;
-  u16_t pcb_remote_port;
-  /* remember current remote peer address of PCB */
-  pcb_remote_ip.addr = pcb->remote_ip.addr;
-  pcb_remote_port = pcb->remote_port;
-  /* copy packet destination address to PCB remote peer address */
-  pcb->remote_ip.addr = dst_ip->addr;
-  pcb->remote_port = dst_port;
-  /* send to the packet destination address */
-  err = udp_send(pcb, p);
-  /* restore PCB remote peer address */
-  pcb->remote_ip.addr = pcb_remote_ip.addr;
-  pcb->remote_port = pcb_remote_port;
-  return err;
-}
-
-/**
- * Send data using UDP.
- *
- * @param pcb UDP PCB used to send the data.
- * @param pbuf chain of pbuf's to be sent.
- *
- * @return lwIP error code.
- * - ERR_OK. Successful. No error occured.
- * - ERR_MEM. Out of memory.
- * - ERR_RTE. Could not find route to destination address.
- *
- * @see udp_disconnect() udp_sendto()
- */
-err_t
-udp_send(struct udp_pcb *pcb, struct pbuf *p)
-{
-  struct udp_hdr *udphdr;
-  struct netif *netif;
-  struct ip_addr *src_ip;
-  err_t err;
-  struct pbuf *q; /* q will be sent down the stack */
-
-  LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 3, ("udp_send\n"));
-
-  /* if the PCB is not yet bound to a port, bind it here */
-  if (pcb->local_port == 0) {
-    LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 2, ("udp_send: not yet bound to a port, binding now\n"));
-    err = udp_bind(pcb, &pcb->local_ip, pcb->local_port);
-    if (err != ERR_OK) {
-      LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 2, ("udp_send: forced port bind failed\n"));
-      return err;
-    }
-  }
-
-  /* not enough space to add an UDP header to first pbuf in given p chain? */
-  if (pbuf_header(p, UDP_HLEN)) {
-    /* allocate header in a seperate new pbuf */
-    q = pbuf_alloc(PBUF_IP, UDP_HLEN, PBUF_RAM);
-    /* new header pbuf could not be allocated? */
-    if (q == NULL) {
-      LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 2, ("udp_send: could not allocate header\n"));
-      return ERR_MEM;
-    }
-    /* chain header q in front of given pbuf p */
-    pbuf_chain(q, p);
-    /* { first pbuf q points to header pbuf } */
-    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p));
-  /* adding a header within p succeeded */
-  } else {
-    /* first pbuf q equals given pbuf */
-    q = p;
-    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: added header in given pbuf %p\n", (void *)p));
-  }
-  /* { q now represents the packet to be sent } */
-  udphdr = q->payload;
-  udphdr->src = htons(pcb->local_port);
-  udphdr->dest = htons(pcb->remote_port);
-  /* in UDP, 0 checksum means 'no checksum' */
-  udphdr->chksum = 0x0000; 
-
-  /* find the outgoing network interface for this packet */
-  netif = ip_route(&(pcb->remote_ip));
-  /* no outgoing network interface could be found? */
-  if (netif == NULL) {
-    LWIP_DEBUGF(UDP_DEBUG | 1, ("udp_send: No route to 0x%lx\n", pcb->remote_ip.addr));
-    UDP_STATS_INC(udp.rterr);
-    return ERR_RTE;
-  }
-  /* PCB local address is IP_ANY_ADDR? */
-  if (ip_addr_isany(&pcb->local_ip)) {
-    /* use outgoing network interface IP address as source address */
-    src_ip = &(netif->ip_addr);
-  } else {
-    /* use UDP PCB local IP address as source address */
-    src_ip = &(pcb->local_ip);
-  }
-
-  LWIP_DEBUGF(UDP_DEBUG, ("udp_send: sending datagram of length %u\n", q->tot_len));
-
-  /* UDP Lite protocol? */
-  if (pcb->flags & UDP_FLAGS_UDPLITE) {
-    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP LITE packet length %u\n", q->tot_len));
-    /* set UDP message length in UDP header */
-    udphdr->len = htons(pcb->chksum_len);
-    /* calculate checksum */
-#if CHECKSUM_GEN_UDP
-    udphdr->chksum = inet_chksum_pseudo(q, src_ip, &(pcb->remote_ip),
-          IP_PROTO_UDP, pcb->chksum_len);
-    /* chksum zero must become 0xffff, as zero means 'no checksum' */
-    if (udphdr->chksum == 0x0000) udphdr->chksum = 0xffff;
-#else
-    udphdr->chksum = 0x0000;
-#endif
-    /* output to IP */
-    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: ip_output_if (,,,,IP_PROTO_UDPLITE,)\n"));
-    err = ip_output_if (q, src_ip, &pcb->remote_ip, pcb->ttl, pcb->tos, IP_PROTO_UDPLITE, netif);    
-  /* UDP */
-  } else {
-    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP packet length %u\n", q->tot_len));
-    udphdr->len = htons(q->tot_len);
-    /* calculate checksum */
-#if CHECKSUM_GEN_UDP
-    if ((pcb->flags & UDP_FLAGS_NOCHKSUM) == 0) {
-      udphdr->chksum = inet_chksum_pseudo(q, src_ip, &pcb->remote_ip, IP_PROTO_UDP, q->tot_len);
-      /* chksum zero must become 0xffff, as zero means 'no checksum' */
-      if (udphdr->chksum == 0x0000) udphdr->chksum = 0xffff;
-    }
-#else
-    udphdr->chksum = 0x0000;
-#endif
-    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP checksum 0x%04x\n", udphdr->chksum));
-    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: ip_output_if (,,,,IP_PROTO_UDP,)\n"));
-    /* output to IP */
-    err = ip_output_if(q, src_ip, &pcb->remote_ip, pcb->ttl, pcb->tos, IP_PROTO_UDP, netif);    
-  }
-  /* TODO: must this be increased even if error occured? */
-  snmp_inc_udpoutdatagrams();
-
-  /* did we chain a seperate header pbuf earlier? */
-  if (q != p) {
-    /* free the header pbuf */
-    pbuf_free(q); q = NULL;
-    /* { p is still referenced by the caller, and will live on } */
-  }
-
-  UDP_STATS_INC(udp.xmit);
-  return err;
-}
-
-/**
- * Bind an UDP PCB.
- *
- * @param pcb UDP PCB to be bound with a local address ipaddr and port.
- * @param ipaddr local IP address to bind with. Use IP_ADDR_ANY to
- * bind to all local interfaces.
- * @param port local UDP port to bind with.
- *
- * @return lwIP error code.
- * - ERR_OK. Successful. No error occured.
- * - ERR_USE. The specified ipaddr and port are already bound to by
- * another UDP PCB.
- *
- * @see udp_disconnect()
- */
-err_t
-udp_bind(struct udp_pcb *pcb, struct ip_addr *ipaddr, u16_t port)
-{
-  struct udp_pcb *ipcb;
-  u8_t rebind;
-#if SO_REUSE
-  int reuse_port_all_set = 1;
-#endif /* SO_REUSE */
-  LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 3, ("udp_bind(ipaddr = "));
-  ip_addr_debug_print(UDP_DEBUG, ipaddr);
-  LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 3, (", port = %u)\n", port));
-
-  rebind = 0;
-  /* Check for double bind and rebind of the same pcb */
-  for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
-    /* is this UDP PCB already on active list? */
-    if (pcb == ipcb) {
-      /* pcb may occur at most once in active list */
-      LWIP_ASSERT("rebind == 0", rebind == 0);
-      /* pcb already in list, just rebind */
-      rebind = 1;
-    }
-
-#if SO_REUSE == 0
-/* this code does not allow upper layer to share a UDP port for
-   listening to broadcast or multicast traffic (See SO_REUSE_ADDR and
-   SO_REUSE_PORT under *BSD). TODO: See where it fits instead, OR
-   combine with implementation of UDP PCB flags. Leon Woestenberg. */
-#ifdef LWIP_UDP_TODO
-    /* port matches that of PCB in list? */
-    else if ((ipcb->local_port == port) &&
-       /* IP address matches, or one is IP_ADDR_ANY? */
-       (ip_addr_isany(&(ipcb->local_ip)) ||
-       ip_addr_isany(ipaddr) ||
-       ip_addr_cmp(&(ipcb->local_ip), ipaddr))) {
-      /* other PCB already binds to this local IP and port */
-      LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: local port %u already bound by another pcb\n", port));
-      return ERR_USE;
-    }
-#endif
-
-#else /* SO_REUSE */
-      /* Search through list of PCB's. 
-         
-      If there is a PCB bound to specified port and IP_ADDR_ANY another PCB can be bound to the interface IP
-      or to the loopback address on the same port if SOF_REUSEADDR is set. Any combination of PCB's bound to 
-      the same local port, but to one address out of {IP_ADDR_ANY, 127.0.0.1, interface IP} at a time is valid.
-      But no two PCB's bound to same local port and same local address is valid.
-      
-      If SOF_REUSEPORT is set several PCB's can be bound to same local port and same local address also. But then 
-      all PCB's must have the SOF_REUSEPORT option set.
-      
-      When the two options aren't set and specified port is already bound, ERR_USE is returned saying that 
-      address is already in use. */
-    else if (ipcb->local_port == port) {
-      if(ip_addr_cmp(&(ipcb->local_ip), ipaddr)) {
-        if(pcb->so_options & SOF_REUSEPORT) {
-          LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: in UDP PCB's SO_REUSEPORT set and same address.\n"));
-          reuse_port_all_set = (reuse_port_all_set && (ipcb->so_options & SOF_REUSEPORT));
-        }
-        else {
-          LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: in UDP PCB's SO_REUSEPORT not set and same address.\n"));
-          return ERR_USE;
-        }
-      }
-      else if((ip_addr_isany(ipaddr) && !ip_addr_isany(&(ipcb->local_ip))) ||
-              (!ip_addr_isany(ipaddr) && ip_addr_isany(&(ipcb->local_ip)))) {
-        if(!(pcb->so_options & SOF_REUSEADDR) && !(pcb->so_options & SOF_REUSEPORT)) {
-          LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: in UDP PCB's SO_REUSEPORT or SO_REUSEADDR not set and not the same address.\n"));
-          return ERR_USE;
-        }           
-      }
-    }
-#endif /* SO_REUSE */
-
-  }
-
-#if SO_REUSE
-  /* If SOF_REUSEPORT isn't set in all PCB's bound to specified port and local address specified then 
-     {IP, port} can't be reused. */
-  if(!reuse_port_all_set) {
-    LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: not all sockets have SO_REUSEPORT set.\n"));
-    return ERR_USE;
-  }
-#endif /* SO_REUSE */
-
-  ip_addr_set(&pcb->local_ip, ipaddr);
-  /* no port specified? */
-  if (port == 0) {
-#ifndef UDP_LOCAL_PORT_RANGE_START
-#define UDP_LOCAL_PORT_RANGE_START 4096
-#define UDP_LOCAL_PORT_RANGE_END   0x7fff
-#endif
-    port = UDP_LOCAL_PORT_RANGE_START;
-    ipcb = udp_pcbs;
-    while ((ipcb != NULL) && (port != UDP_LOCAL_PORT_RANGE_END)) {
-      if (ipcb->local_port == port) {
-        port++;
-        ipcb = udp_pcbs;
-      } else
-        ipcb = ipcb->next;
-    }
-    if (ipcb != NULL) {
-      /* no more ports available in local range */
-      LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: out of free UDP ports\n"));
-      return ERR_USE;
-    }
-  }
-  pcb->local_port = port;
-  /* pcb not active yet? */
-  if (rebind == 0) {
-    /* place the PCB on the active list if not already there */
-    pcb->next = udp_pcbs;
-    udp_pcbs = pcb;
-  }
-  LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | DBG_STATE, ("udp_bind: bound to %u.%u.%u.%u, port %u\n",
-   (unsigned int)(ntohl(pcb->local_ip.addr) >> 24 & 0xff),
-   (unsigned int)(ntohl(pcb->local_ip.addr) >> 16 & 0xff),
-   (unsigned int)(ntohl(pcb->local_ip.addr) >> 8 & 0xff),
-   (unsigned int)(ntohl(pcb->local_ip.addr) & 0xff), pcb->local_port));
-  return ERR_OK;
-}
-/**
- * Connect an UDP PCB.
- *
- * This will associate the UDP PCB with the remote address.
- *
- * @param pcb UDP PCB to be connected with remote address ipaddr and port.
- * @param ipaddr remote IP address to connect with.
- * @param port remote UDP port to connect with.
- *
- * @return lwIP error code
- *
- * @see udp_disconnect()
- */
-err_t
-udp_connect(struct udp_pcb *pcb, struct ip_addr *ipaddr, u16_t port)
-{
-  struct udp_pcb *ipcb;
-
-  if (pcb->local_port == 0) {
-    err_t err = udp_bind(pcb, &pcb->local_ip, pcb->local_port);
-    if (err != ERR_OK)
-      return err;
-  }
-
-  ip_addr_set(&pcb->remote_ip, ipaddr);
-  pcb->remote_port = port;
-  pcb->flags |= UDP_FLAGS_CONNECTED;
-/** TODO: this functionality belongs in upper layers */
-#ifdef LWIP_UDP_TODO
-  /* Nail down local IP for netconn_addr()/getsockname() */
-  if (ip_addr_isany(&pcb->local_ip) && !ip_addr_isany(&pcb->remote_ip)) {
-    struct netif *netif;
-
-    if ((netif = ip_route(&(pcb->remote_ip))) == NULL) {
-      LWIP_DEBUGF(UDP_DEBUG, ("udp_connect: No route to 0x%lx\n", pcb->remote_ip.addr));
-        UDP_STATS_INC(udp.rterr);
-      return ERR_RTE;
-    }
-    /** TODO: this will bind the udp pcb locally, to the interface which
-        is used to route output packets to the remote address. However, we
-        might want to accept incoming packets on any interface! */
-    pcb->local_ip = netif->ip_addr;
-  } else if (ip_addr_isany(&pcb->remote_ip)) {
-    pcb->local_ip.addr = 0;
-  }
-#endif
-  LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | DBG_STATE, ("udp_connect: connected to %u.%u.%u.%u, port %u\n",
-   (unsigned int)(ntohl(pcb->remote_ip.addr) >> 24 & 0xff),
-   (unsigned int)(ntohl(pcb->remote_ip.addr) >> 16 & 0xff),
-   (unsigned int)(ntohl(pcb->remote_ip.addr) >> 8 & 0xff),
-   (unsigned int)(ntohl(pcb->remote_ip.addr) & 0xff), pcb->remote_port));
-
-  /* Insert UDP PCB into the list of active UDP PCBs. */
-  for(ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
-    if (pcb == ipcb) {
-      /* already on the list, just return */
-      return ERR_OK;
-    }
-  }
-  /* PCB not yet on the list, add PCB now */
-  pcb->next = udp_pcbs;
-  udp_pcbs = pcb;
-  return ERR_OK;
-}
-
-void
-udp_disconnect(struct udp_pcb *pcb)
-{
-  /* reset remote address association */
-  ip_addr_set(&pcb->remote_ip, IP_ADDR_ANY);
-  pcb->remote_port = 0;
-  /* mark PCB as unconnected */
-  pcb->flags &= ~UDP_FLAGS_CONNECTED;
-}
-
-void
-udp_recv(struct udp_pcb *pcb,
-   void (* recv)(void *arg, struct udp_pcb *upcb, struct pbuf *p,
-           struct ip_addr *addr, u16_t port),
-   void *recv_arg)
-{
-  /* remember recv() callback and user data */
-  pcb->recv = recv;
-  pcb->recv_arg = recv_arg;
-}
-/**
- * Remove an UDP PCB.
- *
- * @param pcb UDP PCB to be removed. The PCB is removed from the list of
- * UDP PCB's and the data structure is freed from memory.
- *
- * @see udp_new()
- */
-void
-udp_remove(struct udp_pcb *pcb)
-{
-  struct udp_pcb *pcb2;
-  /* pcb to be removed is first in list? */
-  if (udp_pcbs == pcb) {
-    /* make list start at 2nd pcb */
-    udp_pcbs = udp_pcbs->next;
-  /* pcb not 1st in list */
-  } else for(pcb2 = udp_pcbs; pcb2 != NULL; pcb2 = pcb2->next) {
-    /* find pcb in udp_pcbs list */
-    if (pcb2->next != NULL && pcb2->next == pcb) {
-      /* remove pcb from list */
-      pcb2->next = pcb->next;
-    }
-  }
-  memp_free(MEMP_UDP_PCB, pcb);
-}
-/**
- * Create a UDP PCB.
- *
- * @return The UDP PCB which was created. NULL if the PCB data structure
- * could not be allocated.
- *
- * @see udp_remove()
- */
-struct udp_pcb *
-udp_new(void) {
-  struct udp_pcb *pcb;
-  pcb = memp_malloc(MEMP_UDP_PCB);
-  /* could allocate UDP PCB? */
-  if (pcb != NULL) {
-    /* initialize PCB to all zeroes */
-    memset(pcb, 0, sizeof(struct udp_pcb));
-    pcb->ttl = UDP_TTL;
-  }
-  
-  
-  return pcb;
-}
-
-#if UDP_DEBUG
-int
-udp_debug_print(struct udp_hdr *udphdr)
-{
-  LWIP_DEBUGF(UDP_DEBUG, ("UDP header:\n"));
-  LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n"));
-  LWIP_DEBUGF(UDP_DEBUG, ("|     %5u     |     %5u     | (src port, dest port)\n",
-         ntohs(udphdr->src), ntohs(udphdr->dest)));
-  LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n"));
-  LWIP_DEBUGF(UDP_DEBUG, ("|     %5u     |     0x%04x    | (len, chksum)\n",
-         ntohs(udphdr->len), ntohs(udphdr->chksum)));
-  LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n"));
-  return 0;
-}
-#endif /* UDP_DEBUG */
-
-#endif /* LWIP_UDP */
-
-
-
-
-
-
-
-
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv4/lwip/icmp.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv4/lwip/icmp.h
deleted file mode 100644
index 634405b71..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv4/lwip/icmp.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_ICMP_H__
-#define __LWIP_ICMP_H__
-
-#include "lwip/arch.h"
-
-#include "lwip/opt.h"
-#include "lwip/pbuf.h"
-
-#include "lwip/ip_addr.h"
-#include "lwip/netif.h"
-
-#define ICMP_ER 0      /* echo reply */
-#define ICMP_DUR 3     /* destination unreachable */
-#define ICMP_SQ 4      /* source quench */
-#define ICMP_RD 5      /* redirect */
-#define ICMP_ECHO 8    /* echo */
-#define ICMP_TE 11     /* time exceeded */
-#define ICMP_PP 12     /* parameter problem */
-#define ICMP_TS 13     /* timestamp */
-#define ICMP_TSR 14    /* timestamp reply */
-#define ICMP_IRQ 15    /* information request */
-#define ICMP_IR 16     /* information reply */
-
-enum icmp_dur_type {
-  ICMP_DUR_NET = 0,    /* net unreachable */
-  ICMP_DUR_HOST = 1,   /* host unreachable */
-  ICMP_DUR_PROTO = 2,  /* protocol unreachable */
-  ICMP_DUR_PORT = 3,   /* port unreachable */
-  ICMP_DUR_FRAG = 4,   /* fragmentation needed and DF set */
-  ICMP_DUR_SR = 5      /* source route failed */
-};
-
-enum icmp_te_type {
-  ICMP_TE_TTL = 0,     /* time to live exceeded in transit */
-  ICMP_TE_FRAG = 1     /* fragment reassembly time exceeded */
-};
-
-void icmp_input(struct pbuf *p, struct netif *inp);
-
-void icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t);
-void icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t);
-
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-struct icmp_echo_hdr {
-  PACK_STRUCT_FIELD(u16_t _type_code);
-  PACK_STRUCT_FIELD(u16_t chksum);
-  PACK_STRUCT_FIELD(u16_t id);
-  PACK_STRUCT_FIELD(u16_t seqno);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-
-PACK_STRUCT_BEGIN
-struct icmp_dur_hdr {
-  PACK_STRUCT_FIELD(u16_t _type_code);
-  PACK_STRUCT_FIELD(u16_t chksum);
-  PACK_STRUCT_FIELD(u32_t unused);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-
-PACK_STRUCT_BEGIN
-struct icmp_te_hdr {
-  PACK_STRUCT_FIELD(u16_t _type_code);
-  PACK_STRUCT_FIELD(u16_t chksum);
-  PACK_STRUCT_FIELD(u32_t unused);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-#define ICMPH_TYPE(hdr) (ntohs((hdr)->_type_code) >> 8)
-#define ICMPH_CODE(hdr) (ntohs((hdr)->_type_code) & 0xff)
-
-#define ICMPH_TYPE_SET(hdr, type) ((hdr)->_type_code = htons(ICMPH_CODE(hdr) | ((type) << 8)))
-#define ICMPH_CODE_SET(hdr, code) ((hdr)->_type_code = htons((code) | (ICMPH_TYPE(hdr) << 8)))
-
-#endif /* __LWIP_ICMP_H__ */
-    
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv4/lwip/inet.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv4/lwip/inet.h
deleted file mode 100644
index beab85183..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv4/lwip/inet.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_INET_H__
-#define __LWIP_INET_H__
-
-#include "lwip/arch.h"
-
-#include "lwip/opt.h"
-#include "lwip/pbuf.h"
-#include "lwip/ip_addr.h"
-
-u16_t inet_chksum(void *dataptr, u16_t len);
-u16_t inet_chksum_pbuf(struct pbuf *p);
-u16_t inet_chksum_pseudo(struct pbuf *p,
-       struct ip_addr *src, struct ip_addr *dest,
-       u8_t proto, u16_t proto_len);
-
-u32_t inet_addr(const char *cp);
-int inet_aton(const char *cp, struct in_addr *addr);
-char *inet_ntoa(struct in_addr addr); /* returns ptr to static buffer; not reentrant! */
-
-#ifdef htons
-#undef htons
-#endif /* htons */
-#ifdef htonl
-#undef htonl
-#endif /* htonl */
-#ifdef ntohs
-#undef ntohs
-#endif /* ntohs */
-#ifdef ntohl
-#undef ntohl
-#endif /* ntohl */
-
-#if BYTE_ORDER == BIG_ENDIAN
-#define htons(x) (x)
-#define ntohs(x) (x)
-#define htonl(x) (x)
-#define ntohl(x) (x)
-#else
-#ifdef LWIP_PREFIX_BYTEORDER_FUNCS
-/* workaround for naming collisions on some platforms */
-#define htons lwip_htons
-#define ntohs lwip_ntohs
-#define htonl lwip_htonl
-#define ntohl lwip_ntohl
-#endif
-u16_t htons(u16_t x);
-u16_t ntohs(u16_t x);
-u32_t htonl(u32_t x);
-u32_t ntohl(u32_t x);
-#endif
-
-#endif /* __LWIP_INET_H__ */
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv4/lwip/ip.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv4/lwip/ip.h
deleted file mode 100644
index 4c15e1a0e..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv4/lwip/ip.h
+++ /dev/null
@@ -1,154 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_IP_H__
-#define __LWIP_IP_H__
-
-#include "lwip/arch.h"
-
-#include "lwip/def.h"
-#include "lwip/pbuf.h"
-#include "lwip/ip_addr.h"
-
-#include "lwip/err.h"
-
-
-void ip_init(void);
-struct netif *ip_route(struct ip_addr *dest);
-err_t ip_input(struct pbuf *p, struct netif *inp);
-err_t ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
-		u8_t ttl, u8_t tos, u8_t proto);
-err_t ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
-		   u8_t ttl, u8_t tos, u8_t proto,
-       struct netif *netif);
-
-#define IP_HLEN 20
-
-#define IP_PROTO_ICMP 1
-#define IP_PROTO_UDP 17
-#define IP_PROTO_UDPLITE 170
-#define IP_PROTO_TCP 6
-
-/* This is passed as the destination address to ip_output_if (not
-   to ip_output), meaning that an IP header already is constructed
-   in the pbuf. This is used when TCP retransmits. */
-#ifdef IP_HDRINCL
-#undef IP_HDRINCL
-#endif /* IP_HDRINCL */
-#define IP_HDRINCL  NULL
-
-
-/* This is the common part of all PCB types. It needs to be at the
-   beginning of a PCB type definition. It is located here so that
-   changes to this common part are made in one location instead of
-   having to change all PCB structs. */
-#define IP_PCB struct ip_addr local_ip; \
-  struct ip_addr remote_ip; \
-   /* Socket options */  \
-  u16_t so_options;      \
-   /* Type Of Service */ \
-  u8_t tos;              \
-  /* Time To Live */     \
-  u8_t ttl
-
-/*
- * Option flags per-socket. These are the same like SO_XXX.
- */
-#define	SOF_DEBUG	    (u16_t)0x0001U		/* turn on debugging info recording */
-#define	SOF_ACCEPTCONN	(u16_t)0x0002U		/* socket has had listen() */
-#define	SOF_REUSEADDR	(u16_t)0x0004U		/* allow local address reuse */
-#define	SOF_KEEPALIVE	(u16_t)0x0008U		/* keep connections alive */
-#define	SOF_DONTROUTE	(u16_t)0x0010U		/* just use interface addresses */
-#define	SOF_BROADCAST	(u16_t)0x0020U		/* permit sending of broadcast msgs */
-#define	SOF_USELOOPBACK	(u16_t)0x0040U		/* bypass hardware when possible */
-#define	SOF_LINGER	    (u16_t)0x0080U		/* linger on close if data present */
-#define	SOF_OOBINLINE	(u16_t)0x0100U		/* leave received OOB data in line */
-#define	SOF_REUSEPORT	(u16_t)0x0200U		/* allow local address & port reuse */
-
-
-
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-struct ip_hdr {
-  /* version / header length / type of service */
-  PACK_STRUCT_FIELD(u16_t _v_hl_tos);
-  /* total length */
-  PACK_STRUCT_FIELD(u16_t _len);
-  /* identification */
-  PACK_STRUCT_FIELD(u16_t _id);
-  /* fragment offset field */
-  PACK_STRUCT_FIELD(u16_t _offset);
-#define IP_RF 0x8000        /* reserved fragment flag */
-#define IP_DF 0x4000        /* dont fragment flag */
-#define IP_MF 0x2000        /* more fragments flag */
-#define IP_OFFMASK 0x1fff   /* mask for fragmenting bits */
-  /* time to live / protocol*/
-  PACK_STRUCT_FIELD(u16_t _ttl_proto);
-  /* checksum */
-  PACK_STRUCT_FIELD(u16_t _chksum);
-  /* source and destination IP addresses */
-  PACK_STRUCT_FIELD(struct ip_addr src);
-  PACK_STRUCT_FIELD(struct ip_addr dest); 
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-#define IPH_V(hdr)  (ntohs((hdr)->_v_hl_tos) >> 12)
-#define IPH_HL(hdr) ((ntohs((hdr)->_v_hl_tos) >> 8) & 0x0f)
-#define IPH_TOS(hdr) (ntohs((hdr)->_v_hl_tos) & 0xff)
-#define IPH_LEN(hdr) ((hdr)->_len)
-#define IPH_ID(hdr) ((hdr)->_id)
-#define IPH_OFFSET(hdr) ((hdr)->_offset)
-#define IPH_TTL(hdr) (ntohs((hdr)->_ttl_proto) >> 8)
-#define IPH_PROTO(hdr) (ntohs((hdr)->_ttl_proto) & 0xff)
-#define IPH_CHKSUM(hdr) ((hdr)->_chksum)
-
-#define IPH_VHLTOS_SET(hdr, v, hl, tos) (hdr)->_v_hl_tos = (htons(((v) << 12) | ((hl) << 8) | (tos)))
-#define IPH_LEN_SET(hdr, len) (hdr)->_len = (len)
-#define IPH_ID_SET(hdr, id) (hdr)->_id = (id)
-#define IPH_OFFSET_SET(hdr, off) (hdr)->_offset = (off)
-#define IPH_TTL_SET(hdr, ttl) (hdr)->_ttl_proto = (htons(IPH_PROTO(hdr) | ((ttl) << 8)))
-#define IPH_PROTO_SET(hdr, proto) (hdr)->_ttl_proto = (htons((proto) | (IPH_TTL(hdr) << 8)))
-#define IPH_CHKSUM_SET(hdr, chksum) (hdr)->_chksum = (chksum)
-
-#if IP_DEBUG
-void ip_debug_print(struct pbuf *p);
-#else
-#define ip_debug_print(p)
-#endif /* IP_DEBUG */
-
-#endif /* __LWIP_IP_H__ */
-
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv4/lwip/ip_addr.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv4/lwip/ip_addr.h
deleted file mode 100644
index 0ef99937b..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv4/lwip/ip_addr.h
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_IP_ADDR_H__
-#define __LWIP_IP_ADDR_H__
-
-#include "lwip/arch.h"
-
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-struct ip_addr {
-  PACK_STRUCT_FIELD(u32_t addr);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-struct ip_addr2 {
-  PACK_STRUCT_FIELD(u16_t addrw[2]);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-/* For compatibility with BSD code */
-struct in_addr {
-  u32_t s_addr;
-};
-
-struct netif;
-
-extern const struct ip_addr ip_addr_any;
-extern const struct ip_addr ip_addr_broadcast;
-
-/** IP_ADDR_ can be used as a fixed IP address
- *  for the wildcard and the broadcast address
- */
-#define IP_ADDR_ANY ((struct ip_addr *)&ip_addr_any)
-#define IP_ADDR_BROADCAST ((struct ip_addr *)&ip_addr_broadcast)
-
-#define INADDR_NONE    ((u32_t) 0xffffffff)  /* 255.255.255.255 */
-#define INADDR_LOOPBACK    ((u32_t) 0x7f000001)  /* 127.0.0.1 */
-
-/* Definitions of the bits in an Internet address integer.
-
-   On subnets, host and network parts are found according to
-   the subnet mask, not these masks.  */
-
-#define  IN_CLASSA(a)    ((((u32_t)(a)) & 0x80000000) == 0)
-#define  IN_CLASSA_NET    0xff000000
-#define  IN_CLASSA_NSHIFT  24
-#define  IN_CLASSA_HOST    (0xffffffff & ~IN_CLASSA_NET)
-#define  IN_CLASSA_MAX    128
-
-#define  IN_CLASSB(a)    ((((u32_t)(a)) & 0xc0000000) == 0x80000000)
-#define  IN_CLASSB_NET    0xffff0000
-#define  IN_CLASSB_NSHIFT  16
-#define  IN_CLASSB_HOST    (0xffffffff & ~IN_CLASSB_NET)
-#define  IN_CLASSB_MAX    65536
-
-#define  IN_CLASSC(a)    ((((u32_t)(a)) & 0xe0000000) == 0xc0000000)
-#define  IN_CLASSC_NET    0xffffff00
-#define  IN_CLASSC_NSHIFT  8
-#define  IN_CLASSC_HOST    (0xffffffff & ~IN_CLASSC_NET)
-
-#define IN_CLASSD(a)        (((u32_t)(a) & 0xf0000000) == 0xe0000000)
-#define IN_CLASSD_NET       0xf0000000  /* These ones aren't really */
-#define IN_CLASSD_NSHIFT    28      /* net and host fields, but */
-#define IN_CLASSD_HOST      0x0fffffff  /* routing needn't know.    */
-#define IN_MULTICAST(a)     IN_CLASSD(a)
-
-#define IN_EXPERIMENTAL(a)  (((u32_t)(a) & 0xf0000000) == 0xf0000000)
-#define IN_BADCLASS(a)      (((u32_t)(a) & 0xf0000000) == 0xf0000000)
-
-#define IN_LOOPBACKNET      127         /* official! */
-
-
-#define IP4_ADDR(ipaddr, a,b,c,d) (ipaddr)->addr = htonl(((u32_t)(a & 0xff) << 24) | ((u32_t)(b & 0xff) << 16) | \
-                                                         ((u32_t)(c & 0xff) << 8) | (u32_t)(d & 0xff))
-
-#define ip_addr_set(dest, src) (dest)->addr = \
-                               ((src) == NULL? 0:\
-                               (src)->addr)
-/**
- * Determine if two address are on the same network.
- *
- * @arg addr1 IP address 1
- * @arg addr2 IP address 2
- * @arg mask network identifier mask
- * @return !0 if the network identifiers of both address match
- */
-#define ip_addr_netcmp(addr1, addr2, mask) (((addr1)->addr & \
-                                              (mask)->addr) == \
-                                             ((addr2)->addr & \
-                                              (mask)->addr))
-#define ip_addr_cmp(addr1, addr2) ((addr1)->addr == (addr2)->addr)
-
-#define ip_addr_isany(addr1) ((addr1) == NULL || (addr1)->addr == 0)
-
-u8_t ip_addr_isbroadcast(struct ip_addr *, struct netif *);
-
-#define ip_addr_ismulticast(addr1) (((addr1)->addr & ntohl(0xf0000000)) == ntohl(0xe0000000))
-
-
-#define ip_addr_debug_print(debug, ipaddr) LWIP_DEBUGF(debug, ("%u.%u.%u.%u", \
-        ipaddr?(unsigned int)(ntohl((ipaddr)->addr) >> 24) & 0xff:0, \
-        ipaddr?(unsigned int)(ntohl((ipaddr)->addr) >> 16) & 0xff:0, \
-        ipaddr?(unsigned int)(ntohl((ipaddr)->addr) >> 8) & 0xff:0, \
-        ipaddr?(unsigned int)ntohl((ipaddr)->addr) & 0xff:0U))
-
-/* cast to unsigned int, as it is used as argument to printf functions
- * which expect integer arguments */
-#define ip4_addr1(ipaddr) ((unsigned int)(ntohl((ipaddr)->addr) >> 24) & 0xff)
-#define ip4_addr2(ipaddr) ((unsigned int)(ntohl((ipaddr)->addr) >> 16) & 0xff)
-#define ip4_addr3(ipaddr) ((unsigned int)(ntohl((ipaddr)->addr) >> 8) & 0xff)
-#define ip4_addr4(ipaddr) ((unsigned int)(ntohl((ipaddr)->addr)) & 0xff)
-#endif /* __LWIP_IP_ADDR_H__ */
-
-
-
-
-
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv4/lwip/ip_frag.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv4/lwip/ip_frag.h
deleted file mode 100644
index 654b4d7f8..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv4/lwip/ip_frag.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Jani Monoses 
- *
- */
-
-#ifndef __LWIP_IP_FRAG_H__
-#define __LWIP_IP_FRAG_H__
-
-#include "lwip/err.h"
-#include "lwip/pbuf.h"
-#include "lwip/netif.h"
-#include "lwip/ip_addr.h"
-
-struct pbuf * ip_reass(struct pbuf *);
-err_t ip_frag(struct pbuf *, struct netif *, struct ip_addr *);
-
-#endif /* __LWIP_IP_FRAG_H__ */
-
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv6/lwip/icmp.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv6/lwip/icmp.h
deleted file mode 100644
index 2b6adb122..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv6/lwip/icmp.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_ICMP_H__
-#define __LWIP_ICMP_H__
-
-#include "lwip/arch.h"
-
-#include "lwip/opt.h"
-#include "lwip/pbuf.h"
-
-#include "lwip/netif.h"
-
-#define ICMP6_DUR  1
-#define ICMP6_TE   3
-#define ICMP6_ECHO 128    /* echo */
-#define ICMP6_ER   129      /* echo reply */
-
-
-enum icmp_dur_type {
-  ICMP_DUR_NET = 0,    /* net unreachable */
-  ICMP_DUR_HOST = 1,   /* host unreachable */
-  ICMP_DUR_PROTO = 2,  /* protocol unreachable */
-  ICMP_DUR_PORT = 3,   /* port unreachable */
-  ICMP_DUR_FRAG = 4,   /* fragmentation needed and DF set */
-  ICMP_DUR_SR = 5      /* source route failed */
-};
-
-enum icmp_te_type {
-  ICMP_TE_TTL = 0,     /* time to live exceeded in transit */
-  ICMP_TE_FRAG = 1     /* fragment reassembly time exceeded */
-};
-
-void icmp_input(struct pbuf *p, struct netif *inp);
-
-void icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t);
-void icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t);
-
-struct icmp_echo_hdr {
-  u8_t type;
-  u8_t icode;
-  u16_t chksum;
-  u16_t id;
-  u16_t seqno;
-};
-
-struct icmp_dur_hdr {
-  u8_t type;
-  u8_t icode;
-  u16_t chksum;
-  u32_t unused;
-};
-
-struct icmp_te_hdr {
-  u8_t type;
-  u8_t icode;
-  u16_t chksum;
-  u32_t unused;
-};
-
-#endif /* __LWIP_ICMP_H__ */
-    
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv6/lwip/inet.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv6/lwip/inet.h
deleted file mode 100644
index 3cdd7407a..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv6/lwip/inet.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_INET_H__
-#define __LWIP_INET_H__
-
-#include "lwip/arch.h"
-
-#include "lwip/opt.h"
-#include "lwip/pbuf.h"
-#include "lwip/ip_addr.h"
-
-u16_t inet_chksum(void *data, u16_t len);
-u16_t inet_chksum_pbuf(struct pbuf *p);
-u16_t inet_chksum_pseudo(struct pbuf *p,
-       struct ip_addr *src, struct ip_addr *dest,
-       u8_t proto, u32_t proto_len);
-
-u32_t inet_addr(const char *cp);
-int inet_aton(const char *cp, struct in_addr *addr);
-
-#ifndef _MACHINE_ENDIAN_H_
-#ifndef _NETINET_IN_H
-#ifndef _LINUX_BYTEORDER_GENERIC_H
-u16_t htons(u16_t n);
-u16_t ntohs(u16_t n);
-u32_t htonl(u32_t n);
-u32_t ntohl(u32_t n);
-#endif /* _LINUX_BYTEORDER_GENERIC_H */
-#endif /* _NETINET_IN_H */
-#endif /* _MACHINE_ENDIAN_H_ */
-
-#endif /* __LWIP_INET_H__ */
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv6/lwip/ip.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv6/lwip/ip.h
deleted file mode 100644
index 432ca36e0..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv6/lwip/ip.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_IP_H__
-#define __LWIP_IP_H__
-
-#include "lwip/opt.h"
-#include "lwip/def.h"
-#include "lwip/pbuf.h"
-#include "lwip/ip_addr.h"
-
-#include "lwip/err.h"
-
-#define IP_HLEN 40
-
-#define IP_PROTO_ICMP 58
-#define IP_PROTO_UDP 17
-#define IP_PROTO_UDPLITE 170
-#define IP_PROTO_TCP 6
-
-/* This is passed as the destination address to ip_output_if (not
-   to ip_output), meaning that an IP header already is constructed
-   in the pbuf. This is used when TCP retransmits. */
-#ifdef IP_HDRINCL
-#undef IP_HDRINCL
-#endif /* IP_HDRINCL */
-#define IP_HDRINCL  NULL
-
-
-/* The IPv6 header. */
-struct ip_hdr {
-#if BYTE_ORDER == LITTLE_ENDIAN
-  u8_t tclass1:4, v:4;
-  u8_t flow1:4, tclass2:4;  
-#else
-  u8_t v:4, tclass1:4;
-  u8_t tclass2:8, flow1:4;
-#endif
-  u16_t flow2;
-  u16_t len;                /* payload length */
-  u8_t nexthdr;             /* next header */
-  u8_t hoplim;              /* hop limit (TTL) */
-  struct ip_addr src, dest;          /* source and destination IP addresses */
-};
-
-void ip_init(void);
-
-#include "lwip/netif.h"
-
-struct netif *ip_route(struct ip_addr *dest);
-
-void ip_input(struct pbuf *p, struct netif *inp);
-
-/* source and destination addresses in network byte order, please */
-err_t ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
-         unsigned char ttl, unsigned char proto);
-
-err_t ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
-      unsigned char ttl, unsigned char proto,
-      struct netif *netif);
-
-#if IP_DEBUG
-void ip_debug_print(struct pbuf *p);
-#endif /* IP_DEBUG */
-
-#endif /* __LWIP_IP_H__ */
-
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv6/lwip/ip_addr.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv6/lwip/ip_addr.h
deleted file mode 100644
index 08e962ddd..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/ipv6/lwip/ip_addr.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_IP_ADDR_H__
-#define __LWIP_IP_ADDR_H__
-
-#include "lwip/arch.h"
-
-#define IP_ADDR_ANY 0
-
-struct ip_addr {
-  u32_t addr[4];
-};
-
-#define IP6_ADDR(ipaddr, a,b,c,d,e,f,g,h) do { (ipaddr)->addr[0] = htonl((u32_t)((a & 0xffff) << 16) | (b & 0xffff)); \
-                                               (ipaddr)->addr[1] = htonl(((c & 0xffff) << 16) | (d & 0xffff)); \
-                                               (ipaddr)->addr[2] = htonl(((e & 0xffff) << 16) | (f & 0xffff)); \
-                                               (ipaddr)->addr[3] = htonl(((g & 0xffff) << 16) | (h & 0xffff)); } while(0)
-
-int ip_addr_netcmp(struct ip_addr *addr1, struct ip_addr *addr2,
-        struct ip_addr *mask);
-int ip_addr_cmp(struct ip_addr *addr1, struct ip_addr *addr2);
-void ip_addr_set(struct ip_addr *dest, struct ip_addr *src);
-int ip_addr_isany(struct ip_addr *addr);
-
-
-#if IP_DEBUG
-void ip_addr_debug_print(struct ip_addr *addr);
-#endif /* IP_DEBUG */
-
-#endif /* __LWIP_IP_ADDR_H__ */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/api.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/api.h
deleted file mode 100644
index 7f0ad5966..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/api.h
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_API_H__
-#define __LWIP_API_H__
-
-#include "lwip/opt.h"
-#include "lwip/pbuf.h"
-#include "lwip/sys.h"
-
-#include "lwip/ip.h"
-
-#include "lwip/raw.h"
-#include "lwip/udp.h"
-#include "lwip/tcp.h"
-
-#include "lwip/err.h"
-
-#define NETCONN_NOCOPY 0x00
-#define NETCONN_COPY   0x01
-
-enum netconn_type {
-  NETCONN_TCP,
-  NETCONN_UDP,
-  NETCONN_UDPLITE,
-  NETCONN_UDPNOCHKSUM,
-  NETCONN_RAW
-};
-
-enum netconn_state {
-  NETCONN_NONE,
-  NETCONN_WRITE,
-  NETCONN_ACCEPT,
-  NETCONN_RECV,
-  NETCONN_CONNECT,
-  NETCONN_CLOSE
-};
-
-enum netconn_evt {
-  NETCONN_EVT_RCVPLUS,
-  NETCONN_EVT_RCVMINUS,
-  NETCONN_EVT_SENDPLUS,
-  NETCONN_EVT_SENDMINUS
-};
-
-struct netbuf {
-  struct pbuf *p, *ptr;
-  struct ip_addr *fromaddr;
-  u16_t fromport;
-  err_t err;
-};
-
-struct netconn {
-  enum netconn_type type;
-  enum netconn_state state;
-  union {
-    struct tcp_pcb *tcp;
-    struct udp_pcb *udp;
-    struct raw_pcb *raw;
-  } pcb;
-  err_t err;
-  sys_mbox_t mbox;
-  sys_mbox_t recvmbox;
-  sys_mbox_t acceptmbox;
-  sys_sem_t sem;
-  int socket;
-  u16_t recv_avail;
-  void (* callback)(struct netconn *, enum netconn_evt, u16_t len);
-};
-
-/* Network buffer functions: */
-struct netbuf *   netbuf_new      (void);
-void              netbuf_delete   (struct netbuf *buf);
-void *            netbuf_alloc    (struct netbuf *buf, u16_t size);
-void              netbuf_free     (struct netbuf *buf);
-void              netbuf_ref      (struct netbuf *buf,
-           void *dataptr, u16_t size);
-void              netbuf_chain    (struct netbuf *head,
-           struct netbuf *tail);
-
-u16_t             netbuf_len      (struct netbuf *buf);
-err_t             netbuf_data     (struct netbuf *buf,
-           void **dataptr, u16_t *len);
-s8_t              netbuf_next     (struct netbuf *buf);
-void              netbuf_first    (struct netbuf *buf);
-
-void              netbuf_copy     (struct netbuf *buf,
-           void *dataptr, u16_t len);
-void              netbuf_copy_partial(struct netbuf *buf, void *dataptr, 
-              u16_t len, u16_t offset);
-struct ip_addr *  netbuf_fromaddr (struct netbuf *buf);
-u16_t             netbuf_fromport (struct netbuf *buf);
-
-/* Network connection functions: */
-struct netconn *  netconn_new     (enum netconn_type type);
-struct
-netconn *netconn_new_with_callback(enum netconn_type t,
-                                   void (*callback)(struct netconn *, enum netconn_evt, u16_t len));
-struct
-netconn *netconn_new_with_proto_and_callback(enum netconn_type t, u16_t proto,
-                                   void (*callback)(struct netconn *, enum netconn_evt, u16_t len));
-err_t             netconn_delete  (struct netconn *conn);
-enum netconn_type netconn_type    (struct netconn *conn);
-err_t             netconn_peer    (struct netconn *conn,
-           struct ip_addr *addr,
-           u16_t *port);
-err_t             netconn_addr    (struct netconn *conn,
-           struct ip_addr **addr,
-           u16_t *port);
-err_t             netconn_bind    (struct netconn *conn,
-           struct ip_addr *addr,
-           u16_t port);
-err_t             netconn_connect (struct netconn *conn,
-           struct ip_addr *addr,
-           u16_t port);
-err_t             netconn_disconnect (struct netconn *conn);
-err_t             netconn_listen  (struct netconn *conn);
-struct netconn *  netconn_accept  (struct netconn *conn);
-struct netbuf *   netconn_recv    (struct netconn *conn);
-err_t             netconn_send    (struct netconn *conn,
-           struct netbuf *buf);
-err_t             netconn_write   (struct netconn *conn,
-           void *dataptr, u16_t size,
-           u8_t copy);
-err_t             netconn_close   (struct netconn *conn);
-
-err_t             netconn_err     (struct netconn *conn);
-
-#endif /* __LWIP_API_H__ */
-
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/api_msg.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/api_msg.h
deleted file mode 100644
index 1957abc5e..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/api_msg.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_API_MSG_H__
-#define __LWIP_API_MSG_H__
-
-#include "lwip/opt.h"
-#include "lwip/pbuf.h"
-#include "lwip/sys.h"
-
-#include "lwip/ip.h"
-
-#include "lwip/udp.h"
-#include "lwip/tcp.h"
-
-#include "lwip/api.h"
-
-enum api_msg_type {
-  API_MSG_NEWCONN,
-  API_MSG_DELCONN,
-  
-  API_MSG_BIND,
-  API_MSG_CONNECT,
-  API_MSG_DISCONNECT,
-
-  API_MSG_LISTEN,
-  API_MSG_ACCEPT,
-
-  API_MSG_SEND,
-  API_MSG_RECV,
-  API_MSG_WRITE,
-
-  API_MSG_CLOSE,
-  
-  API_MSG_MAX
-};
-
-struct api_msg_msg {
-  struct netconn *conn;
-  enum netconn_type conntype;
-  union {
-    struct pbuf *p;   
-    struct  {
-      struct ip_addr *ipaddr;
-      u16_t port;
-    } bc;
-    struct {
-      void *dataptr;
-      u16_t len;
-      unsigned char copy;
-    } w;    
-    sys_mbox_t mbox;
-    u16_t len;
-  } msg;
-};
-
-struct api_msg {
-  enum api_msg_type type;
-  struct api_msg_msg msg;
-};
-
-void api_msg_input(struct api_msg *msg);
-void api_msg_post(struct api_msg *msg);
-
-#endif /* __LWIP_API_MSG_H__ */
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/arch.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/arch.h
deleted file mode 100644
index e0d622a4b..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/arch.h
+++ /dev/null
@@ -1,216 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_ARCH_H__
-#define __LWIP_ARCH_H__
-
-#ifndef LITTLE_ENDIAN
-#define LITTLE_ENDIAN 1234
-#endif
-
-#ifndef BIG_ENDIAN
-#define BIG_ENDIAN 4321
-#endif
-
-#include "arch/cc.h"
-
-#ifndef PACK_STRUCT_BEGIN
-#define PACK_STRUCT_BEGIN
-#endif /* PACK_STRUCT_BEGIN */
-
-#ifndef PACK_STRUCT_END
-#define PACK_STRUCT_END
-#endif /* PACK_STRUCT_END */
-
-#ifndef PACK_STRUCT_FIELD
-#define PACK_STRUCT_FIELD(x) x
-#endif /* PACK_STRUCT_FIELD */
-
-
-
-#ifdef LWIP_PROVIDE_ERRNO
-
-#define  EPERM     1  /* Operation not permitted */
-#define  ENOENT     2  /* No such file or directory */
-#define  ESRCH     3  /* No such process */
-#define  EINTR     4  /* Interrupted system call */
-#define  EIO     5  /* I/O error */
-#define  ENXIO     6  /* No such device or address */
-#define  E2BIG     7  /* Arg list too long */
-#define  ENOEXEC     8  /* Exec format error */
-#define  EBADF     9  /* Bad file number */
-#define  ECHILD    10  /* No child processes */
-#define  EAGAIN    11  /* Try again */
-#define  ENOMEM    12  /* Out of memory */
-#define  EACCES    13  /* Permission denied */
-#define  EFAULT    14  /* Bad address */
-#define  ENOTBLK    15  /* Block device required */
-#define  EBUSY    16  /* Device or resource busy */
-#define  EEXIST    17  /* File exists */
-#define  EXDEV    18  /* Cross-device link */
-#define  ENODEV    19  /* No such device */
-#define  ENOTDIR    20  /* Not a directory */
-#define  EISDIR    21  /* Is a directory */
-#define  EINVAL    22  /* Invalid argument */
-#define  ENFILE    23  /* File table overflow */
-#define  EMFILE    24  /* Too many open files */
-#define  ENOTTY    25  /* Not a typewriter */
-#define  ETXTBSY    26  /* Text file busy */
-#define  EFBIG    27  /* File too large */
-#define  ENOSPC    28  /* No space left on device */
-#define  ESPIPE    29  /* Illegal seek */
-#define  EROFS    30  /* Read-only file system */
-#define  EMLINK    31  /* Too many links */
-#define  EPIPE    32  /* Broken pipe */
-#define  EDOM    33  /* Math argument out of domain of func */
-#define  ERANGE    34  /* Math result not representable */
-#define  EDEADLK    35  /* Resource deadlock would occur */
-#define  ENAMETOOLONG  36  /* File name too long */
-#define  ENOLCK    37  /* No record locks available */
-#define  ENOSYS    38  /* Function not implemented */
-#define  ENOTEMPTY  39  /* Directory not empty */
-#define  ELOOP    40  /* Too many symbolic links encountered */
-#define  EWOULDBLOCK  EAGAIN  /* Operation would block */
-#define  ENOMSG    42  /* No message of desired type */
-#define  EIDRM    43  /* Identifier removed */
-#define  ECHRNG    44  /* Channel number out of range */
-#define  EL2NSYNC  45  /* Level 2 not synchronized */
-#define  EL3HLT    46  /* Level 3 halted */
-#define  EL3RST    47  /* Level 3 reset */
-#define  ELNRNG    48  /* Link number out of range */
-#define  EUNATCH    49  /* Protocol driver not attached */
-#define  ENOCSI    50  /* No CSI structure available */
-#define  EL2HLT    51  /* Level 2 halted */
-#define  EBADE    52  /* Invalid exchange */
-#define  EBADR    53  /* Invalid request descriptor */
-#define  EXFULL    54  /* Exchange full */
-#define  ENOANO    55  /* No anode */
-#define  EBADRQC    56  /* Invalid request code */
-#define  EBADSLT    57  /* Invalid slot */
-
-#define  EDEADLOCK  EDEADLK
-
-#define  EBFONT    59  /* Bad font file format */
-#define  ENOSTR    60  /* Device not a stream */
-#define  ENODATA    61  /* No data available */
-#define  ETIME    62  /* Timer expired */
-#define  ENOSR    63  /* Out of streams resources */
-#define  ENONET    64  /* Machine is not on the network */
-#define  ENOPKG    65  /* Package not installed */
-#define  EREMOTE    66  /* Object is remote */
-#define  ENOLINK    67  /* Link has been severed */
-#define  EADV    68  /* Advertise error */
-#define  ESRMNT    69  /* Srmount error */
-#define  ECOMM    70  /* Communication error on send */
-#define  EPROTO    71  /* Protocol error */
-#define  EMULTIHOP  72  /* Multihop attempted */
-#define  EDOTDOT    73  /* RFS specific error */
-#define  EBADMSG    74  /* Not a data message */
-#define  EOVERFLOW  75  /* Value too large for defined data type */
-#define  ENOTUNIQ  76  /* Name not unique on network */
-#define  EBADFD    77  /* File descriptor in bad state */
-#define  EREMCHG    78  /* Remote address changed */
-#define  ELIBACC    79  /* Can not access a needed shared library */
-#define  ELIBBAD    80  /* Accessing a corrupted shared library */
-#define  ELIBSCN    81  /* .lib section in a.out corrupted */
-#define  ELIBMAX    82  /* Attempting to link in too many shared libraries */
-#define  ELIBEXEC  83  /* Cannot exec a shared library directly */
-#define  EILSEQ    84  /* Illegal byte sequence */
-#define  ERESTART  85  /* Interrupted system call should be restarted */
-#define  ESTRPIPE  86  /* Streams pipe error */
-#define  EUSERS    87  /* Too many users */
-#define  ENOTSOCK  88  /* Socket operation on non-socket */
-#define  EDESTADDRREQ  89  /* Destination address required */
-#define  EMSGSIZE  90  /* Message too long */
-#define  EPROTOTYPE  91  /* Protocol wrong type for socket */
-#define  ENOPROTOOPT  92  /* Protocol not available */
-#define  EPROTONOSUPPORT  93  /* Protocol not supported */
-#define  ESOCKTNOSUPPORT  94  /* Socket type not supported */
-#define  EOPNOTSUPP  95  /* Operation not supported on transport endpoint */
-#define  EPFNOSUPPORT  96  /* Protocol family not supported */
-#define  EAFNOSUPPORT  97  /* Address family not supported by protocol */
-#define  EADDRINUSE  98  /* Address already in use */
-#define  EADDRNOTAVAIL  99  /* Cannot assign requested address */
-#define  ENETDOWN  100  /* Network is down */
-#define  ENETUNREACH  101  /* Network is unreachable */
-#define  ENETRESET  102  /* Network dropped connection because of reset */
-#define  ECONNABORTED  103  /* Software caused connection abort */
-#define  ECONNRESET  104  /* Connection reset by peer */
-#define  ENOBUFS    105  /* No buffer space available */
-#define  EISCONN    106  /* Transport endpoint is already connected */
-#define  ENOTCONN  107  /* Transport endpoint is not connected */
-#define  ESHUTDOWN  108  /* Cannot send after transport endpoint shutdown */
-#define  ETOOMANYREFS  109  /* Too many references: cannot splice */
-#define  ETIMEDOUT  110  /* Connection timed out */
-#define  ECONNREFUSED  111  /* Connection refused */
-#define  EHOSTDOWN  112  /* Host is down */
-#define  EHOSTUNREACH  113  /* No route to host */
-#define  EALREADY  114  /* Operation already in progress */
-#define  EINPROGRESS  115  /* Operation now in progress */
-#define  ESTALE    116  /* Stale NFS file handle */
-#define  EUCLEAN    117  /* Structure needs cleaning */
-#define  ENOTNAM    118  /* Not a XENIX named type file */
-#define  ENAVAIL    119  /* No XENIX semaphores available */
-#define  EISNAM    120  /* Is a named type file */
-#define  EREMOTEIO  121  /* Remote I/O error */
-#define  EDQUOT    122  /* Quota exceeded */
-
-#define  ENOMEDIUM  123  /* No medium found */
-#define  EMEDIUMTYPE  124  /* Wrong medium type */
-
-
-#define	ENSROK		0	/* DNS server returned answer with no data */
-#define	ENSRNODATA	160	/* DNS server returned answer with no data */
-#define	ENSRFORMERR	161	/* DNS server claims query was misformatted */
-#define	ENSRSERVFAIL 162	/* DNS server returned general failure */
-#define	ENSRNOTFOUND 163	/* Domain name not found */
-#define	ENSRNOTIMP	164	/* DNS server does not implement requested operation */
-#define	ENSRREFUSED	165	/* DNS server refused query */
-#define	ENSRBADQUERY 166	/* Misformatted DNS query */
-#define	ENSRBADNAME	167	/* Misformatted domain name */
-#define	ENSRBADFAMILY 168	/* Unsupported address family */
-#define	ENSRBADRESP	169	/* Misformatted DNS reply */
-#define	ENSRCONNREFUSED	170	/* Could not contact DNS servers */
-#define	ENSRTIMEOUT	171	/* Timeout while contacting DNS servers */
-#define	ENSROF		172	/* End of file */
-#define	ENSRFILE	173	/* Error reading file */
-#define	ENSRNOMEM	174	/* Out of memory */
-#define	ENSRDESTRUCTION	175	/* Application terminated lookup */
-#define	ENSRQUERYDOMAINTOOLONG	176	/* Domain name is too long */
-#define	ENSRCNAMELOOP	177	/* Domain name is too long */
-
-#ifndef errno
-extern int errno;
-#endif
-
-#endif /* LWIP_PROVIDE_ERRNO */
-
-#endif /* __LWIP_ARCH_H__ */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/debug.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/debug.h
deleted file mode 100644
index 4d3425c07..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/debug.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_DEBUG_H__
-#define __LWIP_DEBUG_H__
-
-#include "arch/cc.h"
-
-/** lower two bits indicate debug level
- * - 0 off
- * - 1 warning
- * - 2 serious
- * - 3 severe
- */
-
-#define DBG_LEVEL_OFF     0
-#define DBG_LEVEL_WARNING 1  /* bad checksums, dropped packets, ... */
-#define DBG_LEVEL_SERIOUS 2  /* memory allocation failures, ... */
-#define DBG_LEVEL_SEVERE  3  /* */ 
-#define DBG_MASK_LEVEL    3
-
-/** flag for LWIP_DEBUGF to enable that debug message */
-#define DBG_ON  0x80U
-/** flag for LWIP_DEBUGF to disable that debug message */
-#define DBG_OFF 0x00U
-
-/** flag for LWIP_DEBUGF indicating a tracing message (to follow program flow) */
-#define DBG_TRACE   0x40U
-/** flag for LWIP_DEBUGF indicating a state debug message (to follow module states) */
-#define DBG_STATE   0x20U
-/** flag for LWIP_DEBUGF indicating newly added code, not thoroughly tested yet */
-#define DBG_FRESH   0x10U
-/** flag for LWIP_DEBUGF to halt after printing this debug message */
-#define DBG_HALT    0x08U
-
-#ifndef LWIP_NOASSERT
-#  define LWIP_ASSERT(x,y) do { if(!(y)) LWIP_PLATFORM_ASSERT(x); } while(0)
-#else
-#  define LWIP_ASSERT(x,y) 
-#endif
-
-#ifdef LWIP_DEBUG
-/** print debug message only if debug message type is enabled...
- *  AND is of correct type AND is at least DBG_LEVEL
- */
-#  define LWIP_DEBUGF(debug,x) do { if (((debug) & DBG_ON) && ((debug) & DBG_TYPES_ON) && ((int)((debug) & DBG_MASK_LEVEL) >= DBG_MIN_LEVEL)) { LWIP_PLATFORM_DIAG(x); if ((debug) & DBG_HALT) while(1); } } while(0)
-#  define LWIP_ERROR(x)   do { LWIP_PLATFORM_DIAG(x); } while(0)  
-#else /* LWIP_DEBUG */
-#  define LWIP_DEBUGF(debug,x) 
-#  define LWIP_ERROR(x)  
-#endif /* LWIP_DEBUG */
-
-#endif /* __LWIP_DEBUG_H__ */
-
-
-
-
-
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/def.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/def.h
deleted file mode 100644
index eba9b8774..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/def.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_DEF_H__
-#define __LWIP_DEF_H__
-
-/* this might define NULL already */
-#include "arch/cc.h"
-
-#define LWIP_MAX(x , y)  (x) > (y) ? (x) : (y)
-#define LWIP_MIN(x , y)  (x) < (y) ? (x) : (y)
-
-#ifndef NULL
-#define NULL ((void *)0)
-#endif
-
-
-#endif /* __LWIP_DEF_H__ */
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/dhcp.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/dhcp.h
deleted file mode 100644
index bfe753f26..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/dhcp.h
+++ /dev/null
@@ -1,223 +0,0 @@
-/** @file
- */
-
-#ifndef __LWIP_DHCP_H__
-#define __LWIP_DHCP_H__
-
-#include "lwip/opt.h"
-#include "lwip/netif.h"
-#include "lwip/udp.h"
-
-/** period (in seconds) of the application calling dhcp_coarse_tmr() */
-#define DHCP_COARSE_TIMER_SECS 60 
-/** period (in milliseconds) of the application calling dhcp_fine_tmr() */
-#define DHCP_FINE_TIMER_MSECS 500 
-
-struct dhcp
-{
-  /** current DHCP state machine state */
-  u8_t state;
-  /** retries of current request */
-  u8_t tries;
-  /** transaction identifier of last sent request */ 
-  u32_t xid;
-  /** our connection to the DHCP server */ 
-  struct udp_pcb *pcb;
-  /** (first) pbuf of incoming msg */
-  struct pbuf *p;
-  /** incoming msg */
-  struct dhcp_msg *msg_in;
-  /** incoming msg options */
-  struct dhcp_msg *options_in; 
-  /** ingoing msg options length */
-  u16_t options_in_len;
-
-  struct pbuf *p_out; /* pbuf of outcoming msg */
-  struct dhcp_msg *msg_out; /* outgoing msg */
-  u16_t options_out_len; /* outgoing msg options length */
-  u16_t request_timeout; /* #ticks with period DHCP_FINE_TIMER_SECS for request timeout */
-  u16_t t1_timeout;  /* #ticks with period DHCP_COARSE_TIMER_SECS for renewal time */
-  u16_t t2_timeout;  /* #ticks with period DHCP_COARSE_TIMER_SECS for rebind time */
-  struct ip_addr server_ip_addr; /* dhcp server address that offered this lease */
-  struct ip_addr offered_ip_addr;
-  struct ip_addr offered_sn_mask;
-  struct ip_addr offered_gw_addr;
-  struct ip_addr offered_bc_addr;
-#define DHCP_MAX_DNS 2
-  u32_t dns_count; /* actual number of DNS servers obtained */
-  struct ip_addr offered_dns_addr[DHCP_MAX_DNS]; /* DNS server addresses */
- 
-  u32_t offered_t0_lease; /* lease period (in seconds) */
-  u32_t offered_t1_renew; /* recommended renew time (usually 50% of lease period) */
-  u32_t offered_t2_rebind; /* recommended rebind time (usually 66% of lease period)  */
-/** Patch #1308
- *  TODO: See dhcp.c "TODO"s
- */
-#if 0
-  struct ip_addr offered_si_addr;
-  u8_t *boot_file_name;
-#endif
-};
-
-/* MUST be compiled with "pack structs" or equivalent! */
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-/** minimum set of fields of any DHCP message */
-struct dhcp_msg
-{
-  PACK_STRUCT_FIELD(u8_t op);
-  PACK_STRUCT_FIELD(u8_t htype);
-  PACK_STRUCT_FIELD(u8_t hlen);
-  PACK_STRUCT_FIELD(u8_t hops);
-  PACK_STRUCT_FIELD(u32_t xid);
-  PACK_STRUCT_FIELD(u16_t secs);
-  PACK_STRUCT_FIELD(u16_t flags);
-  PACK_STRUCT_FIELD(struct ip_addr ciaddr);
-  PACK_STRUCT_FIELD(struct ip_addr yiaddr);
-  PACK_STRUCT_FIELD(struct ip_addr siaddr);
-  PACK_STRUCT_FIELD(struct ip_addr giaddr);
-#define DHCP_CHADDR_LEN 16U
-  PACK_STRUCT_FIELD(u8_t chaddr[DHCP_CHADDR_LEN]);
-#define DHCP_SNAME_LEN 64U
-  PACK_STRUCT_FIELD(u8_t sname[DHCP_SNAME_LEN]);
-#define DHCP_FILE_LEN 128U
-  PACK_STRUCT_FIELD(u8_t file[DHCP_FILE_LEN]);
-  PACK_STRUCT_FIELD(u32_t cookie);
-#define DHCP_MIN_OPTIONS_LEN 68U
-/** make sure user does not configure this too small */
-#if ((defined(DHCP_OPTIONS_LEN)) && (DHCP_OPTIONS_LEN < DHCP_MIN_OPTIONS_LEN))
-#  undef DHCP_OPTIONS_LEN
-#endif
-/** allow this to be configured in lwipopts.h, but not too small */
-#if (!defined(DHCP_OPTIONS_LEN))
-/** set this to be sufficient for your options in outgoing DHCP msgs */
-#  define DHCP_OPTIONS_LEN DHCP_MIN_OPTIONS_LEN
-#endif
-  PACK_STRUCT_FIELD(u8_t options[DHCP_OPTIONS_LEN]);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-/** start DHCP configuration */
-err_t dhcp_start(struct netif *netif);
-/** enforce early lease renewal (not needed normally)*/
-err_t dhcp_renew(struct netif *netif);
-/** release the DHCP lease, usually called before dhcp_stop()*/
-err_t dhcp_release(struct netif *netif);
-/** stop DHCP configuration */
-void dhcp_stop(struct netif *netif);
-/** inform server of our manual IP address */
-void dhcp_inform(struct netif *netif);
-
-/** if enabled, check whether the offered IP address is not in use, using ARP */
-#if DHCP_DOES_ARP_CHECK
-void dhcp_arp_reply(struct netif *netif, struct ip_addr *addr);
-#endif
-
-/** to be called every minute */
-void dhcp_coarse_tmr(void);
-/** to be called every half second */
-void dhcp_fine_tmr(void);
- 
-/** DHCP message item offsets and length */
-#define DHCP_MSG_OFS (UDP_DATA_OFS)  
-  #define DHCP_OP_OFS (DHCP_MSG_OFS + 0)
-  #define DHCP_HTYPE_OFS (DHCP_MSG_OFS + 1)
-  #define DHCP_HLEN_OFS (DHCP_MSG_OFS + 2)
-  #define DHCP_HOPS_OFS (DHCP_MSG_OFS + 3)
-  #define DHCP_XID_OFS (DHCP_MSG_OFS + 4)
-  #define DHCP_SECS_OFS (DHCP_MSG_OFS + 8)
-  #define DHCP_FLAGS_OFS (DHCP_MSG_OFS + 10)
-  #define DHCP_CIADDR_OFS (DHCP_MSG_OFS + 12)
-  #define DHCP_YIADDR_OFS (DHCP_MSG_OFS + 16)
-  #define DHCP_SIADDR_OFS (DHCP_MSG_OFS + 20)
-  #define DHCP_GIADDR_OFS (DHCP_MSG_OFS + 24)
-  #define DHCP_CHADDR_OFS (DHCP_MSG_OFS + 28)
-  #define DHCP_SNAME_OFS (DHCP_MSG_OFS + 44)
-  #define DHCP_FILE_OFS (DHCP_MSG_OFS + 108)
-#define DHCP_MSG_LEN 236
-
-#define DHCP_COOKIE_OFS (DHCP_MSG_OFS + DHCP_MSG_LEN)
-#define DHCP_OPTIONS_OFS (DHCP_MSG_OFS + DHCP_MSG_LEN + 4)
-
-#define DHCP_CLIENT_PORT 68  
-#define DHCP_SERVER_PORT 67
-
-/** DHCP client states */
-#define DHCP_REQUESTING 1
-#define DHCP_INIT 2
-#define DHCP_REBOOTING 3
-#define DHCP_REBINDING 4
-#define DHCP_RENEWING 5
-#define DHCP_SELECTING 6
-#define DHCP_INFORMING 7
-#define DHCP_CHECKING 8
-#define DHCP_PERMANENT 9
-#define DHCP_BOUND 10
-/** not yet implemented #define DHCP_RELEASING 11 */
-#define DHCP_BACKING_OFF 12
-#define DHCP_OFF 13
- 
-#define DHCP_BOOTREQUEST 1
-#define DHCP_BOOTREPLY 2
-
-#define DHCP_DISCOVER 1
-#define DHCP_OFFER 2
-#define DHCP_REQUEST 3
-#define DHCP_DECLINE 4
-#define DHCP_ACK 5
-#define DHCP_NAK 6
-#define DHCP_RELEASE 7
-#define DHCP_INFORM 8
-
-#define DHCP_HTYPE_ETH 1
-
-#define DHCP_HLEN_ETH 6
-
-#define DHCP_BROADCAST_FLAG 15
-#define DHCP_BROADCAST_MASK (1 << DHCP_FLAG_BROADCAST)
-
-/** BootP options */
-#define DHCP_OPTION_PAD 0
-#define DHCP_OPTION_SUBNET_MASK 1 /* RFC 2132 3.3 */
-#define DHCP_OPTION_ROUTER 3
-#define DHCP_OPTION_DNS_SERVER 6 
-#define DHCP_OPTION_HOSTNAME 12
-#define DHCP_OPTION_IP_TTL 23
-#define DHCP_OPTION_MTU 26
-#define DHCP_OPTION_BROADCAST 28
-#define DHCP_OPTION_TCP_TTL 37
-#define DHCP_OPTION_END 255
-
-/** DHCP options */
-#define DHCP_OPTION_REQUESTED_IP 50 /* RFC 2132 9.1, requested IP address */
-#define DHCP_OPTION_LEASE_TIME 51 /* RFC 2132 9.2, time in seconds, in 4 bytes */
-#define DHCP_OPTION_OVERLOAD 52 /* RFC2132 9.3, use file and/or sname field for options */
-
-#define DHCP_OPTION_MESSAGE_TYPE 53 /* RFC 2132 9.6, important for DHCP */
-#define DHCP_OPTION_MESSAGE_TYPE_LEN 1
-
-
-#define DHCP_OPTION_SERVER_ID 54 /* RFC 2132 9.7, server IP address */
-#define DHCP_OPTION_PARAMETER_REQUEST_LIST 55 /* RFC 2132 9.8, requested option types */
-
-#define DHCP_OPTION_MAX_MSG_SIZE 57 /* RFC 2132 9.10, message size accepted >= 576 */
-#define DHCP_OPTION_MAX_MSG_SIZE_LEN 2
-
-#define DHCP_OPTION_T1 58 /* T1 renewal time */
-#define DHCP_OPTION_T2 59 /* T2 rebinding time */
-#define DHCP_OPTION_CLIENT_ID 61
-#define DHCP_OPTION_TFTP_SERVERNAME 66
-#define DHCP_OPTION_BOOTFILE 67
-
-/** possible combinations of overloading the file and sname fields with options */
-#define DHCP_OVERLOAD_NONE 0
-#define DHCP_OVERLOAD_FILE 1
-#define DHCP_OVERLOAD_SNAME  2
-#define DHCP_OVERLOAD_SNAME_FILE 3
-
-#endif /*__LWIP_DHCP_H__*/
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/err.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/err.h
deleted file mode 100644
index c92cb26d7..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/err.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_ERR_H__
-#define __LWIP_ERR_H__
-
-#include "lwip/opt.h"
-
-#include "arch/cc.h"
-
-typedef s8_t err_t;
-
-/* Definitions for error constants. */
-
-#define ERR_OK    0      /* No error, everything OK. */
-#define ERR_MEM  -1      /* Out of memory error.     */
-#define ERR_BUF  -2      /* Buffer error.            */
-
-
-#define ERR_ABRT -3      /* Connection aborted.      */
-#define ERR_RST  -4      /* Connection reset.        */
-#define ERR_CLSD -5      /* Connection closed.       */
-#define ERR_CONN -6      /* Not connected.           */
-
-#define ERR_VAL  -7      /* Illegal value.           */
-
-#define ERR_ARG  -8      /* Illegal argument.        */
-
-#define ERR_RTE  -9      /* Routing problem.         */
-
-#define ERR_USE  -10     /* Address in use.          */
-
-#define ERR_IF   -11     /* Low-level netif error    */
-#define ERR_ISCONN -12   /* Already connected.       */
-
-
-#ifdef LWIP_DEBUG
-extern char *lwip_strerr(err_t err);
-#else
-#define lwip_strerr(x) ""
-#endif /* LWIP_DEBUG */
-#endif /* __LWIP_ERR_H__ */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/mem.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/mem.h
deleted file mode 100644
index ee6fea7d8..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/mem.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_MEM_H__
-#define __LWIP_MEM_H__
-
-#include "lwip/opt.h"
-#include "lwip/arch.h"
-
-#if MEM_SIZE > 64000l
-typedef u32_t mem_size_t;
-#else
-typedef u16_t mem_size_t;
-#endif /* MEM_SIZE > 64000 */
-
-
-void mem_init(void);
-
-void *mem_malloc(mem_size_t size);
-void mem_free(void *mem);
-void *mem_realloc(void *mem, mem_size_t size);
-void *mem_reallocm(void *mem, mem_size_t size);
-
-#ifndef MEM_ALIGN_SIZE
-#define MEM_ALIGN_SIZE(size) (((size) + MEM_ALIGNMENT - 1) & ~(MEM_ALIGNMENT-1))
-#endif
-
-#ifndef MEM_ALIGN
-#define MEM_ALIGN(addr) ((void *)(((mem_ptr_t)(addr) + MEM_ALIGNMENT - 1) & ~(mem_ptr_t)(MEM_ALIGNMENT-1)))
-#endif
-
-#endif /* __LWIP_MEM_H__ */
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/memp.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/memp.h
deleted file mode 100644
index 1cd46fa3f..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/memp.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-
-#ifndef __LWIP_MEMP_H__
-#define __LWIP_MEMP_H__
-
-#include "lwip/opt.h"
-
-typedef enum {
-  MEMP_PBUF,
-  MEMP_RAW_PCB,
-  MEMP_UDP_PCB,
-  MEMP_TCP_PCB,
-  MEMP_TCP_PCB_LISTEN,
-  MEMP_TCP_SEG,
-
-  MEMP_NETBUF,
-  MEMP_NETCONN,
-  MEMP_API_MSG,
-  MEMP_TCPIP_MSG,
-
-  MEMP_SYS_TIMEOUT,
-  
-  MEMP_MAX
-} memp_t;
-
-void memp_init(void);
-
-void *memp_malloc(memp_t type);
-void *memp_realloc(memp_t fromtype, memp_t totype, void *mem);
-void memp_free(memp_t type, void *mem);
-
-#endif /* __LWIP_MEMP_H__  */
-    
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/netif.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/netif.h
deleted file mode 100644
index d0bda2df9..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/netif.h
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_NETIF_H__
-#define __LWIP_NETIF_H__
-
-#include "lwip/opt.h"
-
-#include "lwip/err.h"
-
-#include "lwip/ip_addr.h"
-
-#include "lwip/inet.h"
-#include "lwip/pbuf.h"
-#if LWIP_DHCP
-#  include "lwip/dhcp.h"
-#endif
-
-/** must be the maximum of all used hardware address lengths
-    across all types of interfaces in use */
-#define NETIF_MAX_HWADDR_LEN 6U
-
-/** TODO: define the use (where, when, whom) of netif flags */
-
-/** whether the network interface is 'up'. this is
- * a software flag used to control whether this network
- * interface is enabled and processes traffic.
- */
-#define NETIF_FLAG_UP 0x1U
-/** if set, the netif has broadcast capability */
-#define NETIF_FLAG_BROADCAST 0x2U
-/** if set, the netif is one end of a point-to-point connection */
-#define NETIF_FLAG_POINTTOPOINT 0x4U
-/** if set, the interface is configured using DHCP */
-#define NETIF_FLAG_DHCP 0x08U
-/** if set, the interface has an active link
- *  (set by the network interface driver) */
-#define NETIF_FLAG_LINK_UP 0x10U
-
-/** Generic data structure used for all lwIP network interfaces.
- *  The following fields should be filled in by the initialization
- *  function for the device driver: hwaddr_len, hwaddr[], mtu, flags */
-
-struct netif {
-  /** pointer to next in linked list */
-  struct netif *next;
-
-  /** IP address configuration in network byte order */
-  struct ip_addr ip_addr;
-  struct ip_addr netmask;
-  struct ip_addr gw;
-
-  /** This function is called by the network device driver
-   *  to pass a packet up the TCP/IP stack. */
-  err_t (* input)(struct pbuf *p, struct netif *inp);
-  /** This function is called by the IP module when it wants
-   *  to send a packet on the interface. This function typically
-   *  first resolves the hardware address, then sends the packet. */
-  err_t (* output)(struct netif *netif, struct pbuf *p,
-       struct ip_addr *ipaddr);
-  /** This function is called by the ARP module when it wants
-   *  to send a packet on the interface. This function outputs
-   *  the pbuf as-is on the link medium. */
-  err_t (* linkoutput)(struct netif *netif, struct pbuf *p);
-  /** This field can be set by the device driver and could point
-   *  to state information for the device. */
-  void *state;
-#if LWIP_DHCP
-  /** the DHCP client state information for this netif */
-  struct dhcp *dhcp;
-#endif
-  /** number of bytes used in hwaddr */
-  unsigned char hwaddr_len;
-  /** link level hardware address of this interface */
-  unsigned char hwaddr[NETIF_MAX_HWADDR_LEN];
-  /** maximum transfer unit (in bytes) */
-  u16_t mtu;
-  /** flags (see NETIF_FLAG_ above) */
-  u8_t flags;
-  /** link type */
-  u8_t link_type;
-  /** descriptive abbreviation */
-  char name[2];
-  /** number of this interface */
-  u8_t num;
-};
-
-/** The list of network interfaces. */
-extern struct netif *netif_list;
-/** The default network interface. */
-extern struct netif *netif_default;
-
-/* netif_init() must be called first. */
-void netif_init(void);
-
-struct netif *netif_add(struct netif *netif, struct ip_addr *ipaddr, struct ip_addr *netmask,
-      struct ip_addr *gw,
-      void *state,
-      err_t (* init)(struct netif *netif),
-      err_t (* input)(struct pbuf *p, struct netif *netif));
-
-void
-netif_set_addr(struct netif *netif,struct ip_addr *ipaddr, struct ip_addr *netmask,
-    struct ip_addr *gw);
-void netif_remove(struct netif * netif);
-
-/* Returns a network interface given its name. The name is of the form
-   "et0", where the first two letters are the "name" field in the
-   netif structure, and the digit is in the num field in the same
-   structure. */
-struct netif *netif_find(char *name);
-
-void netif_set_default(struct netif *netif);
-
-void netif_set_ipaddr(struct netif *netif, struct ip_addr *ipaddr);
-void netif_set_netmask(struct netif *netif, struct ip_addr *netmast);
-void netif_set_gw(struct netif *netif, struct ip_addr *gw);
-void netif_set_up(struct netif *netif);
-void netif_set_down(struct netif *netif);
-u8_t netif_is_up(struct netif *netif);
-
-#endif /* __LWIP_NETIF_H__ */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/opt.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/opt.h
deleted file mode 100644
index 8e3910d52..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/opt.h
+++ /dev/null
@@ -1,669 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_OPT_H__
-#define __LWIP_OPT_H__
-
-/* Include user defined options first */
-#include "lwipopts.h"
-#include "lwip/debug.h"
-
-/* Define default values for unconfigured parameters. */
-
-/* Platform specific locking */
-
-/*
- * enable SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection
- * for certain critical regions during buffer allocation, deallocation and memory
- * allocation and deallocation.
- */
-#ifndef SYS_LIGHTWEIGHT_PROT
-#define SYS_LIGHTWEIGHT_PROT            0
-#endif
-
-#ifndef NO_SYS
-#define NO_SYS                          0
-#endif
-/* ---------- Memory options ---------- */
-/* MEM_ALIGNMENT: should be set to the alignment of the CPU for which
-   lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4, 2
-   byte alignment -> define MEM_ALIGNMENT to 2. */
-
-#ifndef MEM_ALIGNMENT
-#define MEM_ALIGNMENT                   1
-#endif
-
-/* MEM_SIZE: the size of the heap memory. If the application will send
-a lot of data that needs to be copied, this should be set high. */
-#ifndef MEM_SIZE
-#define MEM_SIZE                        1600
-#endif
-
-#ifndef MEMP_SANITY_CHECK
-#define MEMP_SANITY_CHECK		0
-#endif
-
-/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application
-   sends a lot of data out of ROM (or other static memory), this
-   should be set high. */
-#ifndef MEMP_NUM_PBUF
-#define MEMP_NUM_PBUF                   16
-#endif
-
-/* Number of raw connection PCBs */
-#ifndef MEMP_NUM_RAW_PCB
-#define MEMP_NUM_RAW_PCB                4
-#endif
-
-/* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One
-   per active UDP "connection". */
-#ifndef MEMP_NUM_UDP_PCB
-#define MEMP_NUM_UDP_PCB                4
-#endif
-/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP
-   connections. */
-#ifndef MEMP_NUM_TCP_PCB
-#define MEMP_NUM_TCP_PCB                5
-#endif
-/* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP
-   connections. */
-#ifndef MEMP_NUM_TCP_PCB_LISTEN
-#define MEMP_NUM_TCP_PCB_LISTEN         8
-#endif
-/* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP
-   segments. */
-#ifndef MEMP_NUM_TCP_SEG
-#define MEMP_NUM_TCP_SEG                16
-#endif
-/* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active
-   timeouts. */
-#ifndef MEMP_NUM_SYS_TIMEOUT
-#define MEMP_NUM_SYS_TIMEOUT            3
-#endif
-
-/* The following four are used only with the sequential API and can be
-   set to 0 if the application only will use the raw API. */
-/* MEMP_NUM_NETBUF: the number of struct netbufs. */
-#ifndef MEMP_NUM_NETBUF
-#define MEMP_NUM_NETBUF                 2
-#endif
-/* MEMP_NUM_NETCONN: the number of struct netconns. */
-#ifndef MEMP_NUM_NETCONN
-#define MEMP_NUM_NETCONN                4
-#endif
-/* MEMP_NUM_APIMSG: the number of struct api_msg, used for
-   communication between the TCP/IP stack and the sequential
-   programs. */
-#ifndef MEMP_NUM_API_MSG
-#define MEMP_NUM_API_MSG                8
-#endif
-/* MEMP_NUM_TCPIPMSG: the number of struct tcpip_msg, which is used
-   for sequential API communication and incoming packets. Used in
-   src/api/tcpip.c. */
-#ifndef MEMP_NUM_TCPIP_MSG
-#define MEMP_NUM_TCPIP_MSG              8
-#endif
-
-/* ---------- Pbuf options ---------- */
-/* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */
-
-#ifndef PBUF_POOL_SIZE
-#define PBUF_POOL_SIZE                  16
-#endif
-
-/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */
-
-#ifndef PBUF_POOL_BUFSIZE
-#define PBUF_POOL_BUFSIZE               128
-#endif
-
-/* PBUF_LINK_HLEN: the number of bytes that should be allocated for a
-   link level header. Defaults to 14 for Ethernet. */
-
-#ifndef PBUF_LINK_HLEN
-#define PBUF_LINK_HLEN                  14
-#endif
-
-
-
-/* ---------- ARP options ---------- */
-
-/** Number of active hardware address, IP address pairs cached */
-#ifndef ARP_TABLE_SIZE
-#define ARP_TABLE_SIZE                  10
-#endif
-
-/**
- * If enabled, outgoing packets are queued during hardware address
- * resolution.
- *
- * This feature has not stabilized yet. Single-packet queueing is
- * believed to be stable, multi-packet queueing is believed to
- * clash with the TCP segment queueing.
- * 
- * As multi-packet-queueing is currently disabled, enabling this
- * _should_ work, but we need your testing feedback on lwip-users.
- *
- */
-#ifndef ARP_QUEUEING
-#define ARP_QUEUEING                    1
-#endif
-
-/* This option is deprecated */
-#ifdef ETHARP_QUEUE_FIRST
-#error ETHARP_QUEUE_FIRST option is deprecated. Remove it from your lwipopts.h.
-#endif
-
-/* This option is removed to comply with the ARP standard */
-#ifdef ETHARP_ALWAYS_INSERT
-#error ETHARP_ALWAYS_INSERT option is deprecated. Remove it from your lwipopts.h.
-#endif
-
-/* ---------- IP options ---------- */
-/* Define IP_FORWARD to 1 if you wish to have the ability to forward
-   IP packets across network interfaces. If you are going to run lwIP
-   on a device with only one network interface, define this to 0. */
-#ifndef IP_FORWARD
-#define IP_FORWARD                      0
-#endif
-
-/* If defined to 1, IP options are allowed (but not parsed). If
-   defined to 0, all packets with IP options are dropped. */
-#ifndef IP_OPTIONS
-#define IP_OPTIONS                      1
-#endif
-
-/** IP reassembly and segmentation. Even if they both deal with IP
- *  fragments, note that these are orthogonal, one dealing with incoming
- *  packets, the other with outgoing packets
- */
-
-/** Reassemble incoming fragmented IP packets */
-#ifndef IP_REASSEMBLY
-#define IP_REASSEMBLY                   1
-#endif
-
-/** Fragment outgoing IP packets if their size exceeds MTU */
-#ifndef IP_FRAG
-#define IP_FRAG                         1
-#endif
-
-/* ---------- ICMP options ---------- */
-
-#ifndef ICMP_TTL
-#define ICMP_TTL                        255
-#endif
-
-/* ---------- RAW options ---------- */
-
-#ifndef LWIP_RAW
-#define LWIP_RAW                        1
-#endif
-
-#ifndef RAW_TTL
-#define RAW_TTL                        255
-#endif
-
-/* ---------- DHCP options ---------- */
-
-#ifndef LWIP_DHCP
-#define LWIP_DHCP                       0
-#endif
-
-/* 1 if you want to do an ARP check on the offered address
-   (recommended). */
-#ifndef DHCP_DOES_ARP_CHECK
-#define DHCP_DOES_ARP_CHECK             1
-#endif
-
-/* ---------- UDP options ---------- */
-#ifndef LWIP_UDP
-#define LWIP_UDP                        1
-#endif
-
-#ifndef UDP_TTL
-#define UDP_TTL                         255
-#endif
-
-/* ---------- TCP options ---------- */
-#ifndef LWIP_TCP
-#define LWIP_TCP                        1
-#endif
-
-#ifndef TCP_TTL
-#define TCP_TTL                         255
-#endif
-
-#ifndef TCP_WND
-#define TCP_WND                         2048
-#endif 
-
-#ifndef TCP_MAXRTX
-#define TCP_MAXRTX                      12
-#endif
-
-#ifndef TCP_SYNMAXRTX
-#define TCP_SYNMAXRTX                   6
-#endif
-
-
-/* Controls if TCP should queue segments that arrive out of
-   order. Define to 0 if your device is low on memory. */
-#ifndef TCP_QUEUE_OOSEQ
-#define TCP_QUEUE_OOSEQ                 1
-#endif
-
-/* TCP Maximum segment size. */
-#ifndef TCP_MSS
-#define TCP_MSS                         128 /* A *very* conservative default. */
-#endif
-
-/* TCP sender buffer space (bytes). */
-#ifndef TCP_SND_BUF
-#define TCP_SND_BUF                     256
-#endif
-
-/* TCP sender buffer space (pbufs). This must be at least = 2 *
-   TCP_SND_BUF/TCP_MSS for things to work. */
-#ifndef TCP_SND_QUEUELEN
-#define TCP_SND_QUEUELEN                4 * TCP_SND_BUF/TCP_MSS
-#endif
-
-
-/* Maximum number of retransmissions of data segments. */
-
-/* Maximum number of retransmissions of SYN segments. */
-
-/* TCP writable space (bytes). This must be less than or equal
-   to TCP_SND_BUF. It is the amount of space which must be
-   available in the tcp snd_buf for select to return writable */
-#ifndef TCP_SNDLOWAT
-#define TCP_SNDLOWAT                    TCP_SND_BUF/2
-#endif
-
-/* Support loop interface (127.0.0.1) */
-#ifndef LWIP_HAVE_LOOPIF
-#define LWIP_HAVE_LOOPIF		1
-#endif
-
-#ifndef LWIP_EVENT_API
-#define LWIP_EVENT_API                  0
-#define LWIP_CALLBACK_API               1
-#else 
-#define LWIP_EVENT_API                  1
-#define LWIP_CALLBACK_API               0
-#endif 
-
-#ifndef LWIP_COMPAT_SOCKETS
-#define LWIP_COMPAT_SOCKETS             1
-#endif
-
-
-#ifndef TCPIP_THREAD_PRIO
-#define TCPIP_THREAD_PRIO               1
-#endif
-
-#ifndef SLIPIF_THREAD_PRIO
-#define SLIPIF_THREAD_PRIO              1
-#endif
-
-#ifndef PPP_THREAD_PRIO
-#define PPP_THREAD_PRIO                 1
-#endif
-
-#ifndef DEFAULT_THREAD_PRIO
-#define DEFAULT_THREAD_PRIO             1
-#endif
-
-
-/* ---------- Socket Options ---------- */
-/* Enable SO_REUSEADDR and SO_REUSEPORT options */ 
-#ifndef SO_REUSE
-# define SO_REUSE 0
-#endif                                                                        
-
-
-/* ---------- Statistics options ---------- */
-#ifndef LWIP_STATS
-#define LWIP_STATS                      1
-#endif
-
-#if LWIP_STATS
-
-#ifndef LWIP_STATS_DISPLAY
-#define LWIP_STATS_DISPLAY 0
-#endif
-
-#ifndef LINK_STATS
-#define LINK_STATS	1
-#endif
-
-#ifndef IP_STATS
-#define IP_STATS	1
-#endif
-
-#ifndef IPFRAG_STATS
-#define IPFRAG_STATS	1
-#endif
-
-#ifndef ICMP_STATS
-#define ICMP_STATS	1
-#endif
-
-#ifndef UDP_STATS
-#define UDP_STATS	1
-#endif
-
-#ifndef TCP_STATS
-#define TCP_STATS	1
-#endif
-
-#ifndef MEM_STATS
-#define MEM_STATS	1
-#endif
-
-#ifndef MEMP_STATS
-#define MEMP_STATS	1
-#endif
-
-#ifndef PBUF_STATS
-#define PBUF_STATS	1
-#endif
-
-#ifndef SYS_STATS
-#define SYS_STATS	1
-#endif
-
-#ifndef RAW_STATS
-#define RAW_STATS	0
-#endif
-
-#else
-
-#define LINK_STATS	0
-#define IP_STATS	0
-#define IPFRAG_STATS	0
-#define ICMP_STATS	0
-#define UDP_STATS	0
-#define TCP_STATS	0
-#define MEM_STATS	0
-#define MEMP_STATS	0
-#define PBUF_STATS	0
-#define SYS_STATS	0
-#define RAW_STATS	0
-#define LWIP_STATS_DISPLAY	0
-
-#endif /* LWIP_STATS */
-
-/* ---------- PPP options ---------- */
-
-#ifndef PPP_SUPPORT
-#define PPP_SUPPORT                     0      /* Set for PPP */
-#endif
-
-#if PPP_SUPPORT 
-
-#define NUM_PPP                         1      /* Max PPP sessions. */
-
-
-
-#ifndef PAP_SUPPORT
-#define PAP_SUPPORT                     0      /* Set for PAP. */
-#endif
-
-#ifndef CHAP_SUPPORT
-#define CHAP_SUPPORT                    0      /* Set for CHAP. */
-#endif
-
-#define MSCHAP_SUPPORT                  0      /* Set for MSCHAP (NOT FUNCTIONAL!) */
-#define CBCP_SUPPORT                    0      /* Set for CBCP (NOT FUNCTIONAL!) */
-#define CCP_SUPPORT                     0      /* Set for CCP (NOT FUNCTIONAL!) */
-
-#ifndef VJ_SUPPORT
-#define VJ_SUPPORT                      0      /* Set for VJ header compression. */
-#endif
-
-#ifndef MD5_SUPPORT
-#define MD5_SUPPORT                     0      /* Set for MD5 (see also CHAP) */
-#endif
-
-
-/*
- * Timeouts.
- */
-#define FSM_DEFTIMEOUT                  6       /* Timeout time in seconds */
-#define FSM_DEFMAXTERMREQS              2       /* Maximum Terminate-Request transmissions */
-#define FSM_DEFMAXCONFREQS              10      /* Maximum Configure-Request transmissions */
-#define FSM_DEFMAXNAKLOOPS              5       /* Maximum number of nak loops */
-
-#define UPAP_DEFTIMEOUT                 6       /* Timeout (seconds) for retransmitting req */
-#define UPAP_DEFREQTIME                 30      /* Time to wait for auth-req from peer */
-
-#define CHAP_DEFTIMEOUT                 6       /* Timeout time in seconds */
-#define CHAP_DEFTRANSMITS               10      /* max # times to send challenge */
-
-
-/* Interval in seconds between keepalive echo requests, 0 to disable. */
-#if 1
-#define LCP_ECHOINTERVAL                0
-#else
-#define LCP_ECHOINTERVAL                10
-#endif
-
-/* Number of unanswered echo requests before failure. */
-#define LCP_MAXECHOFAILS                3
-
-/* Max Xmit idle time (in jiffies) before resend flag char. */
-#define PPP_MAXIDLEFLAG                 100
-
-/*
- * Packet sizes
- *
- * Note - lcp shouldn't be allowed to negotiate stuff outside these
- *    limits.  See lcp.h in the pppd directory.
- * (XXX - these constants should simply be shared by lcp.c instead
- *    of living in lcp.h)
- */
-#define PPP_MTU                         1500     /* Default MTU (size of Info field) */
-#if 0
-#define PPP_MAXMTU  65535 - (PPP_HDRLEN + PPP_FCSLEN)
-#else
-#define PPP_MAXMTU                      1500 /* Largest MTU we allow */
-#endif
-#define PPP_MINMTU                      64
-#define PPP_MRU                         1500     /* default MRU = max length of info field */
-#define PPP_MAXMRU                      1500     /* Largest MRU we allow */
-#define PPP_DEFMRU                      296             /* Try for this */
-#define PPP_MINMRU                      128             /* No MRUs below this */
-
-
-#define MAXNAMELEN                      256     /* max length of hostname or name for auth */
-#define MAXSECRETLEN                    256     /* max length of password or secret */
-
-#endif /* PPP_SUPPORT */
-
-/* checksum options - set to zero for hardware checksum support */
-
-#ifndef CHECKSUM_GEN_IP
-#define CHECKSUM_GEN_IP                 1
-#endif
- 
-#ifndef CHECKSUM_GEN_UDP
-#define CHECKSUM_GEN_UDP                1
-#endif
- 
-#ifndef CHECKSUM_GEN_TCP
-#define CHECKSUM_GEN_TCP                1
-#endif
- 
-#ifndef CHECKSUM_CHECK_IP
-#define CHECKSUM_CHECK_IP               1
-#endif
- 
-#ifndef CHECKSUM_CHECK_UDP
-#define CHECKSUM_CHECK_UDP              1
-#endif
-
-#ifndef CHECKSUM_CHECK_TCP
-#define CHECKSUM_CHECK_TCP              1
-#endif
-
-/* Debugging options all default to off */
-
-#ifndef DBG_TYPES_ON
-#define DBG_TYPES_ON                    0
-#endif
-
-#ifndef ETHARP_DEBUG
-#define ETHARP_DEBUG                    DBG_OFF
-#endif
-
-#ifndef NETIF_DEBUG
-#define NETIF_DEBUG                     DBG_OFF
-#endif
-
-#ifndef PBUF_DEBUG
-#define PBUF_DEBUG                      DBG_OFF
-#endif
-
-#ifndef API_LIB_DEBUG
-#define API_LIB_DEBUG                   DBG_OFF
-#endif
-
-#ifndef API_MSG_DEBUG
-#define API_MSG_DEBUG                   DBG_OFF
-#endif
-
-#ifndef SOCKETS_DEBUG
-#define SOCKETS_DEBUG                   DBG_OFF
-#endif
-
-#ifndef ICMP_DEBUG
-#define ICMP_DEBUG                      DBG_OFF
-#endif
-
-#ifndef INET_DEBUG
-#define INET_DEBUG                      DBG_OFF
-#endif
-
-#ifndef IP_DEBUG
-#define IP_DEBUG                        DBG_OFF
-#endif
-
-#ifndef IP_REASS_DEBUG
-#define IP_REASS_DEBUG                  DBG_OFF
-#endif
-
-#ifndef RAW_DEBUG
-#define RAW_DEBUG                       DBG_OFF
-#endif
-
-#ifndef MEM_DEBUG
-#define MEM_DEBUG                       DBG_OFF
-#endif
-
-#ifndef MEMP_DEBUG
-#define MEMP_DEBUG                      DBG_OFF
-#endif
-
-#ifndef SYS_DEBUG
-#define SYS_DEBUG                       DBG_OFF
-#endif
-
-#ifndef TCP_DEBUG
-#define TCP_DEBUG                       DBG_OFF
-#endif
-
-#ifndef TCP_INPUT_DEBUG
-#define TCP_INPUT_DEBUG                 DBG_OFF
-#endif
-
-#ifndef TCP_FR_DEBUG
-#define TCP_FR_DEBUG                    DBG_OFF
-#endif
-
-#ifndef TCP_RTO_DEBUG
-#define TCP_RTO_DEBUG                   DBG_OFF
-#endif
-
-#ifndef TCP_REXMIT_DEBUG
-#define TCP_REXMIT_DEBUG                DBG_OFF
-#endif
-
-#ifndef TCP_CWND_DEBUG
-#define TCP_CWND_DEBUG                  DBG_OFF
-#endif
-
-#ifndef TCP_WND_DEBUG
-#define TCP_WND_DEBUG                   DBG_OFF
-#endif
-
-#ifndef TCP_OUTPUT_DEBUG
-#define TCP_OUTPUT_DEBUG                DBG_OFF
-#endif
-
-#ifndef TCP_RST_DEBUG
-#define TCP_RST_DEBUG                   DBG_OFF
-#endif
-
-#ifndef TCP_QLEN_DEBUG
-#define TCP_QLEN_DEBUG                  DBG_OFF
-#endif
-
-#ifndef UDP_DEBUG
-#define UDP_DEBUG                       DBG_OFF
-#endif
-
-#ifndef TCPIP_DEBUG
-#define TCPIP_DEBUG                     DBG_OFF
-#endif
-
-#ifndef PPP_DEBUG 
-#define PPP_DEBUG                       DBG_OFF
-#endif
-
-#ifndef SLIP_DEBUG 
-#define SLIP_DEBUG                      DBG_OFF
-#endif
-
-#ifndef DHCP_DEBUG 
-#define DHCP_DEBUG                      DBG_OFF
-#endif
-
-
-#ifndef DBG_MIN_LEVEL
-#define DBG_MIN_LEVEL                   DBG_LEVEL_OFF
-#endif
-
-#endif /* __LWIP_OPT_H__ */
-
-
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/pbuf.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/pbuf.h
deleted file mode 100644
index 546aa3035..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/pbuf.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-
-#ifndef __LWIP_PBUF_H__
-#define __LWIP_PBUF_H__
-
-#include "arch/cc.h"
-
-
-#define PBUF_TRANSPORT_HLEN 20
-#define PBUF_IP_HLEN        20
-
-typedef enum {
-  PBUF_TRANSPORT,
-  PBUF_IP,
-  PBUF_LINK,
-  PBUF_RAW
-} pbuf_layer;
-
-typedef enum {
-  PBUF_RAM,
-  PBUF_ROM,
-  PBUF_REF,
-  PBUF_POOL
-} pbuf_flag;
-
-/* Definitions for the pbuf flag field. These are NOT the flags that
- * are passed to pbuf_alloc(). */
-#define PBUF_FLAG_RAM   0x00U    /* Flags that pbuf data is stored in RAM */
-#define PBUF_FLAG_ROM   0x01U    /* Flags that pbuf data is stored in ROM */
-#define PBUF_FLAG_POOL  0x02U    /* Flags that the pbuf comes from the pbuf pool */
-#define PBUF_FLAG_REF   0x04U    /* Flags thet the pbuf payload refers to RAM */
-
-/** indicates this packet was broadcast on the link */
-#define PBUF_FLAG_LINK_BROADCAST 0x80U
-
-struct pbuf {
-  /** next pbuf in singly linked pbuf chain */
-  struct pbuf *next;
-
-  /** pointer to the actual data in the buffer */
-  void *payload;
-  
-  /**
-   * total length of this buffer and all next buffers in chain
-   * belonging to the same packet.
-   *
-   * For non-queue packet chains this is the invariant:
-   * p->tot_len == p->len + (p->next? p->next->tot_len: 0)
-   */
-  u16_t tot_len;
-  
-  /** length of this buffer */
-  u16_t len;  
-
-  /** flags telling the type of pbuf, see PBUF_FLAG_ */
-  u16_t flags;
-  
-  /**
-   * the reference count always equals the number of pointers
-   * that refer to this pbuf. This can be pointers from an application,
-   * the stack itself, or pbuf->next pointers from a chain.
-   */
-  u16_t ref;
-  
-};
-
-void pbuf_init(void);
-
-struct pbuf *pbuf_alloc(pbuf_layer l, u16_t size, pbuf_flag flag);
-void pbuf_realloc(struct pbuf *p, u16_t size); 
-u8_t pbuf_header(struct pbuf *p, s16_t header_size);
-void pbuf_ref(struct pbuf *p);
-void pbuf_ref_chain(struct pbuf *p);
-u8_t pbuf_free(struct pbuf *p);
-u8_t pbuf_clen(struct pbuf *p);  
-void pbuf_cat(struct pbuf *h, struct pbuf *t);
-void pbuf_chain(struct pbuf *h, struct pbuf *t);
-struct pbuf *pbuf_take(struct pbuf *f);
-struct pbuf *pbuf_dechain(struct pbuf *p);
-void pbuf_queue(struct pbuf *p, struct pbuf *n);
-struct pbuf * pbuf_dequeue(struct pbuf *p);
-
-#endif /* __LWIP_PBUF_H__ */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/raw.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/raw.h
deleted file mode 100644
index 6f7a98717..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/raw.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_RAW_H__
-#define __LWIP_RAW_H__
-
-#include "lwip/arch.h"
-
-#include "lwip/pbuf.h"
-#include "lwip/inet.h"
-#include "lwip/ip.h"
-
-struct raw_pcb {
-/* Common members of all PCB types */
-  IP_PCB;
-
-  struct raw_pcb *next;
-
-  u16_t protocol;
-
-  u8_t (* recv)(void *arg, struct raw_pcb *pcb, struct pbuf *p,
-    struct ip_addr *addr);
-  void *recv_arg;
-};
-
-/* The following functions is the application layer interface to the
-   RAW code. */
-struct raw_pcb * raw_new        (u16_t proto);
-void             raw_remove     (struct raw_pcb *pcb);
-err_t            raw_bind       (struct raw_pcb *pcb, struct ip_addr *ipaddr);
-err_t            raw_connect    (struct raw_pcb *pcb, struct ip_addr *ipaddr);
-
-void             raw_recv       (struct raw_pcb *pcb,
-                                 u8_t (* recv)(void *arg, struct raw_pcb *pcb,
-                                              struct pbuf *p,
-                                              struct ip_addr *addr),
-                                 void *recv_arg);
-err_t            raw_sendto    (struct raw_pcb *pcb, struct pbuf *p, struct ip_addr *ipaddr);
-err_t            raw_send       (struct raw_pcb *pcb, struct pbuf *p);
-
-/* The following functions are the lower layer interface to RAW. */
-u8_t              raw_input      (struct pbuf *p, struct netif *inp);
-void             raw_init       (void);
-
-
-#endif /* __LWIP_RAW_H__ */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/sio.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/sio.h
deleted file mode 100644
index 8a37aa35a..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/sio.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- */
-
-/*
- * This is the interface to the platform specific serial IO module
- * It needs to be implemented by those platforms which need SLIP or PPP
- */
-
-#include "arch/cc.h"
-
-#ifndef __sio_fd_t_defined
-typedef void * sio_fd_t;
-#endif
-
-#ifndef sio_open
-sio_fd_t sio_open(u8_t);
-#endif
-
-#ifndef sio_send
-void sio_send(u8_t, sio_fd_t);
-#endif
-
-#ifndef sio_recv
-u8_t sio_recv(sio_fd_t);
-#endif
-
-#ifndef sio_read
-u32_t sio_read(sio_fd_t, u8_t *, u32_t);
-#endif
-
-#ifndef sio_write
-u32_t sio_write(sio_fd_t, u8_t *, u32_t);
-#endif
-
-#ifndef sio_read_abort
-void sio_read_abort(sio_fd_t);
-#endif
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/snmp.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/snmp.h
deleted file mode 100644
index 7d160aaa4..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/snmp.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * Copyright (c) 2001, 2002 Leon Woestenberg 
- * Copyright (c) 2001, 2002 Axon Digital Design B.V., The Netherlands.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Leon Woestenberg 
- *
- */
-#ifndef __LWIP_SNMP_H__
-#define __LWIP_SNMP_H__
-
-#include "lwip/opt.h"
-
-/* SNMP support available? */
-#if defined(LWIP_SNMP) && (LWIP_SNMP > 0)
-
-/* network interface */
-void snmp_add_ifinoctets(unsigned long value); 
-void snmp_inc_ifinucastpkts(void);
-void snmp_inc_ifinnucastpkts(void);
-void snmp_inc_ifindiscards(void);
-void snmp_add_ifoutoctets(unsigned long value);
-void snmp_inc_ifoutucastpkts(void);
-void snmp_inc_ifoutnucastpkts(void);
-void snmp_inc_ifoutdiscards(void);
-
-/* IP */
-void snmp_inc_ipinreceives(void);
-void snmp_inc_ipindelivers(void);
-void snmp_inc_ipindiscards(void);
-void snmp_inc_ipoutdiscards(void);
-void snmp_inc_ipoutrequests(void);
-void snmp_inc_ipunknownprotos(void);
-void snmp_inc_ipnoroutes(void);
-void snmp_inc_ipforwdatagrams(void);
-
-/* ICMP */
-void snmp_inc_icmpinmsgs(void);
-void snmp_inc_icmpinerrors(void);
-void snmp_inc_icmpindestunreachs(void);
-void snmp_inc_icmpintimeexcds(void);
-void snmp_inc_icmpinparmprobs(void);
-void snmp_inc_icmpinsrcquenchs(void);
-void snmp_inc_icmpinredirects(void);
-void snmp_inc_icmpinechos(void);
-void snmp_inc_icmpinechoreps(void);
-void snmp_inc_icmpintimestamps(void);
-void snmp_inc_icmpintimestampreps(void);
-void snmp_inc_icmpinaddrmasks(void);
-void snmp_inc_icmpinaddrmaskreps(void);
-void snmp_inc_icmpoutmsgs(void);
-void snmp_inc_icmpouterrors(void);
-void snmp_inc_icmpoutdestunreachs(void);
-void snmp_inc_icmpouttimeexcds(void);
-void snmp_inc_icmpoutparmprobs(void);
-void snmp_inc_icmpoutsrcquenchs(void);
-void snmp_inc_icmpoutredirects(void); 
-void snmp_inc_icmpoutechos(void);
-void snmp_inc_icmpoutechoreps(void);
-void snmp_inc_icmpouttimestamps(void);
-void snmp_inc_icmpouttimestampreps(void);
-void snmp_inc_icmpoutaddrmasks(void);
-void snmp_inc_icmpoutaddrmaskreps(void);
-
-/* TCP */
-void snmp_inc_tcpactiveopens(void);
-void snmp_inc_tcppassiveopens(void);
-void snmp_inc_tcpattemptfails(void);
-void snmp_inc_tcpestabresets(void);
-void snmp_inc_tcpcurrestab(void);
-void snmp_inc_tcpinsegs(void);
-void snmp_inc_tcpoutsegs(void);
-void snmp_inc_tcpretranssegs(void);
-void snmp_inc_tcpinerrs(void);
-void snmp_inc_tcpoutrsts(void);
-
-/* UDP */
-void snmp_inc_udpindatagrams(void);
-void snmp_inc_udpnoports(void);
-void snmp_inc_udpinerrors(void);
-void snmp_inc_udpoutdatagrams(void);
-
-/* LWIP_SNMP support not available */
-/* define everything to be empty */
-#else
-
-/* network interface */
-#define snmp_add_ifinoctets(value) 
-#define snmp_inc_ifinucastpkts()
-#define snmp_inc_ifinnucastpkts()
-#define snmp_inc_ifindiscards()
-#define snmp_add_ifoutoctets(value)
-#define snmp_inc_ifoutucastpkts()
-#define snmp_inc_ifoutnucastpkts()
-#define snmp_inc_ifoutdiscards()
-
-/* IP */
-#define snmp_inc_ipinreceives()
-#define snmp_inc_ipindelivers()
-#define snmp_inc_ipindiscards()
-#define snmp_inc_ipoutdiscards()
-#define snmp_inc_ipoutrequests()
-#define snmp_inc_ipunknownprotos()
-#define snmp_inc_ipnoroutes()
-#define snmp_inc_ipforwdatagrams()
-
-/* ICMP */
-#define snmp_inc_icmpinmsgs()
-#define snmp_inc_icmpinerrors() 
-#define snmp_inc_icmpindestunreachs() 
-#define snmp_inc_icmpintimeexcds()
-#define snmp_inc_icmpinparmprobs() 
-#define snmp_inc_icmpinsrcquenchs() 
-#define snmp_inc_icmpinredirects() 
-#define snmp_inc_icmpinechos() 
-#define snmp_inc_icmpinechoreps()
-#define snmp_inc_icmpintimestamps() 
-#define snmp_inc_icmpintimestampreps()
-#define snmp_inc_icmpinaddrmasks()
-#define snmp_inc_icmpinaddrmaskreps()
-#define snmp_inc_icmpoutmsgs()
-#define snmp_inc_icmpouterrors()
-#define snmp_inc_icmpoutdestunreachs() 
-#define snmp_inc_icmpouttimeexcds() 
-#define snmp_inc_icmpoutparmprobs()
-#define snmp_inc_icmpoutsrcquenchs()
-#define snmp_inc_icmpoutredirects() 
-#define snmp_inc_icmpoutechos() 
-#define snmp_inc_icmpoutechoreps()
-#define snmp_inc_icmpouttimestamps()
-#define snmp_inc_icmpouttimestampreps()
-#define snmp_inc_icmpoutaddrmasks()
-#define snmp_inc_icmpoutaddrmaskreps()
-/* TCP */
-#define snmp_inc_tcpactiveopens()
-#define snmp_inc_tcppassiveopens()
-#define snmp_inc_tcpattemptfails()
-#define snmp_inc_tcpestabresets()
-#define snmp_inc_tcpcurrestab()
-#define snmp_inc_tcpinsegs()
-#define snmp_inc_tcpoutsegs()
-#define snmp_inc_tcpretranssegs()
-#define snmp_inc_tcpinerrs()
-#define snmp_inc_tcpoutrsts()
-
-/* UDP */
-#define snmp_inc_udpindatagrams()
-#define snmp_inc_udpnoports()
-#define snmp_inc_udpinerrors()
-#define snmp_inc_udpoutdatagrams()
-
-#endif
-
-#endif /* __LWIP_SNMP_H__ */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/sockets.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/sockets.h
deleted file mode 100644
index d5f8ccf74..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/sockets.h
+++ /dev/null
@@ -1,271 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-
-
-#ifndef __LWIP_SOCKETS_H__
-#define __LWIP_SOCKETS_H__
-#include "lwip/ip_addr.h"
-
-struct sockaddr_in {
-  u8_t sin_len;
-  u8_t sin_family;
-  u16_t sin_port;
-  struct in_addr sin_addr;
-  char sin_zero[8];
-};
-
-struct sockaddr {
-  u8_t sa_len;
-  u8_t sa_family;
-  char sa_data[14];
-};
-
-#ifndef socklen_t
-#  define socklen_t int
-#endif
-
-
-#define SOCK_STREAM     1
-#define SOCK_DGRAM      2
-#define SOCK_RAW        3
-
-/*
- * Option flags per-socket.
- */
-#define  SO_DEBUG  0x0001    /* turn on debugging info recording */
-#define  SO_ACCEPTCONN  0x0002    /* socket has had listen() */
-#define  SO_REUSEADDR  0x0004    /* allow local address reuse */
-#define  SO_KEEPALIVE  0x0008    /* keep connections alive */
-#define  SO_DONTROUTE  0x0010    /* just use interface addresses */
-#define  SO_BROADCAST  0x0020    /* permit sending of broadcast msgs */
-#define  SO_USELOOPBACK  0x0040    /* bypass hardware when possible */
-#define  SO_LINGER  0x0080    /* linger on close if data present */
-#define  SO_OOBINLINE  0x0100    /* leave received OOB data in line */
-#define	 SO_REUSEPORT	0x0200		/* allow local address & port reuse */
-
-#define SO_DONTLINGER   (int)(~SO_LINGER)
-
-/*
- * Additional options, not kept in so_options.
- */
-#define SO_SNDBUF  0x1001    /* send buffer size */
-#define SO_RCVBUF  0x1002    /* receive buffer size */
-#define SO_SNDLOWAT  0x1003    /* send low-water mark */
-#define SO_RCVLOWAT  0x1004    /* receive low-water mark */
-#define SO_SNDTIMEO  0x1005    /* send timeout */
-#define SO_RCVTIMEO  0x1006    /* receive timeout */
-#define  SO_ERROR  0x1007    /* get error status and clear */
-#define  SO_TYPE    0x1008    /* get socket type */
-
-
-
-/*
- * Structure used for manipulating linger option.
- */
-struct linger {
-       int l_onoff;                /* option on/off */
-       int l_linger;               /* linger time */
-};
-
-/*
- * Level number for (get/set)sockopt() to apply to socket itself.
- */
-#define  SOL_SOCKET  0xfff    /* options for socket level */
-
-
-#define AF_UNSPEC       0
-#define AF_INET         2
-#define PF_INET         AF_INET
-#define PF_UNSPEC       AF_UNSPEC
-
-#define IPPROTO_IP      0
-#define IPPROTO_TCP     6
-#define IPPROTO_UDP     17
-
-#define INADDR_ANY      0
-#define INADDR_BROADCAST 0xffffffff
-
-/* Flags we can use with send and recv. */
-#define MSG_DONTWAIT    0x40            /* Nonblocking i/o for this operation only */
-
-
-/*
- * Options for level IPPROTO_IP
- */
-#define IP_TOS       1
-#define IP_TTL       2
-
-
-#define IPTOS_TOS_MASK          0x1E
-#define IPTOS_TOS(tos)          ((tos) & IPTOS_TOS_MASK)
-#define IPTOS_LOWDELAY          0x10
-#define IPTOS_THROUGHPUT        0x08
-#define IPTOS_RELIABILITY       0x04
-#define IPTOS_LOWCOST           0x02
-#define IPTOS_MINCOST           IPTOS_LOWCOST
-
-/*
- * Definitions for IP precedence (also in ip_tos) (hopefully unused)
- */
-#define IPTOS_PREC_MASK                 0xe0
-#define IPTOS_PREC(tos)                ((tos) & IPTOS_PREC_MASK)
-#define IPTOS_PREC_NETCONTROL           0xe0
-#define IPTOS_PREC_INTERNETCONTROL      0xc0
-#define IPTOS_PREC_CRITIC_ECP           0xa0
-#define IPTOS_PREC_FLASHOVERRIDE        0x80
-#define IPTOS_PREC_FLASH                0x60
-#define IPTOS_PREC_IMMEDIATE            0x40
-#define IPTOS_PREC_PRIORITY             0x20
-#define IPTOS_PREC_ROUTINE              0x00
-
-
-/*
- * Commands for ioctlsocket(),  taken from the BSD file fcntl.h.
- *
- *
- * Ioctl's have the command encoded in the lower word,
- * and the size of any in or out parameters in the upper
- * word.  The high 2 bits of the upper word are used
- * to encode the in/out status of the parameter; for now
- * we restrict parameters to at most 128 bytes.
- */
-#if !defined(FIONREAD) || !defined(FIONBIO)
-#define IOCPARM_MASK    0x7f            /* parameters must be < 128 bytes */
-#define IOC_VOID        0x20000000      /* no parameters */
-#define IOC_OUT         0x40000000      /* copy out parameters */
-#define IOC_IN          0x80000000      /* copy in parameters */
-#define IOC_INOUT       (IOC_IN|IOC_OUT)
-                                        /* 0x20000000 distinguishes new &
-                                           old ioctl's */
-#define _IO(x,y)        (IOC_VOID|((x)<<8)|(y))
-
-#define _IOR(x,y,t)     (IOC_OUT|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y))
-
-#define _IOW(x,y,t)     (IOC_IN|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y))
-#endif
-
-#ifndef FIONREAD
-#define FIONREAD    _IOR('f', 127, unsigned long) /* get # bytes to read */
-#endif
-#ifndef FIONBIO
-#define FIONBIO     _IOW('f', 126, unsigned long) /* set/clear non-blocking i/o */
-#endif
-
-/* Socket I/O Controls */
-#ifndef SIOCSHIWAT
-#define SIOCSHIWAT  _IOW('s',  0, unsigned long)  /* set high watermark */
-#define SIOCGHIWAT  _IOR('s',  1, unsigned long)  /* get high watermark */
-#define SIOCSLOWAT  _IOW('s',  2, unsigned long)  /* set low watermark */
-#define SIOCGLOWAT  _IOR('s',  3, unsigned long)  /* get low watermark */
-#define SIOCATMARK  _IOR('s',  7, unsigned long)  /* at oob mark? */
-#endif
-
-#ifndef O_NONBLOCK
-#define O_NONBLOCK    04000U
-#endif
-
-#ifndef FD_SET
-  #undef  FD_SETSIZE
-  #define FD_SETSIZE    16
-  #define FD_SET(n, p)  ((p)->fd_bits[(n)/8] |=  (1 << ((n) & 7)))
-  #define FD_CLR(n, p)  ((p)->fd_bits[(n)/8] &= ~(1 << ((n) & 7)))
-  #define FD_ISSET(n,p) ((p)->fd_bits[(n)/8] &   (1 << ((n) & 7)))
-  #define FD_ZERO(p)    memset((void*)(p),0,sizeof(*(p)))
-
-  typedef struct fd_set {
-          unsigned char fd_bits [(FD_SETSIZE+7)/8];
-        } fd_set;
-
-/* 
- * only define this in sockets.c so it does not interfere
- * with other projects namespaces where timeval is present
- */ 
-#ifndef LWIP_TIMEVAL_PRIVATE
-#define LWIP_TIMEVAL_PRIVATE 1
-#endif
-
-#if LWIP_TIMEVAL_PRIVATE
-  struct timeval {
-    long    tv_sec;         /* seconds */
-    long    tv_usec;        /* and microseconds */
-  };
-#endif
-
-#endif
-
-int lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen);
-int lwip_bind(int s, struct sockaddr *name, socklen_t namelen);
-int lwip_shutdown(int s, int how);
-int lwip_getpeername (int s, struct sockaddr *name, socklen_t *namelen);
-int lwip_getsockname (int s, struct sockaddr *name, socklen_t *namelen);
-int lwip_getsockopt (int s, int level, int optname, void *optval, socklen_t *optlen);
-int lwip_setsockopt (int s, int level, int optname, const void *optval, socklen_t optlen);
-int lwip_close(int s);
-int lwip_connect(int s, struct sockaddr *name, socklen_t namelen);
-int lwip_listen(int s, int backlog);
-int lwip_recv(int s, void *mem, int len, unsigned int flags);
-int lwip_read(int s, void *mem, int len);
-int lwip_recvfrom(int s, void *mem, int len, unsigned int flags,
-      struct sockaddr *from, socklen_t *fromlen);
-int lwip_send(int s, void *dataptr, int size, unsigned int flags);
-int lwip_sendto(int s, void *dataptr, int size, unsigned int flags,
-    struct sockaddr *to, socklen_t tolen);
-int lwip_socket(int domain, int type, int protocol);
-int lwip_write(int s, void *dataptr, int size);
-int lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset,
-                struct timeval *timeout);
-int lwip_ioctl(int s, long cmd, void *argp);
-
-#if LWIP_COMPAT_SOCKETS
-#define accept(a,b,c)         lwip_accept(a,b,c)
-#define bind(a,b,c)           lwip_bind(a,b,c)
-#define shutdown(a,b)         lwip_shutdown(a,b)
-#define close(s)              lwip_close(s)
-#define connect(a,b,c)        lwip_connect(a,b,c)
-#define getsockname(a,b,c)    lwip_getsockname(a,b,c)
-#define getpeername(a,b,c)    lwip_getpeername(a,b,c)
-#define setsockopt(a,b,c,d,e) lwip_setsockopt(a,b,c,d,e)
-#define getsockopt(a,b,c,d,e) lwip_getsockopt(a,b,c,d,e)
-#define listen(a,b)           lwip_listen(a,b)
-#define recv(a,b,c,d)         lwip_recv(a,b,c,d)
-#define read(a,b,c)           lwip_read(a,b,c)
-#define recvfrom(a,b,c,d,e,f) lwip_recvfrom(a,b,c,d,e,f)
-#define send(a,b,c,d)         lwip_send(a,b,c,d)
-#define sendto(a,b,c,d,e,f)   lwip_sendto(a,b,c,d,e,f)
-#define socket(a,b,c)         lwip_socket(a,b,c)
-#define write(a,b,c)          lwip_write(a,b,c)
-#define select(a,b,c,d,e)     lwip_select(a,b,c,d,e)
-#define ioctlsocket(a,b,c)    lwip_ioctl(a,b,c)
-#endif /* LWIP_COMPAT_SOCKETS */
-
-#endif /* __LWIP_SOCKETS_H__ */
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/stats.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/stats.h
deleted file mode 100644
index 71acfd068..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/stats.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_STATS_H__
-#define __LWIP_STATS_H__
-
-#include "lwip/opt.h"
-#include "arch/cc.h"
-
-#include "lwip/mem.h"
-#include "lwip/memp.h"
-
-#if LWIP_STATS
-
-struct stats_proto {
-  u16_t xmit;    /* Transmitted packets. */
-  u16_t rexmit;  /* Retransmitted packets. */
-  u16_t recv;    /* Received packets. */
-  u16_t fw;      /* Forwarded packets. */
-  u16_t drop;    /* Dropped packets. */
-  u16_t chkerr;  /* Checksum error. */
-  u16_t lenerr;  /* Invalid length error. */
-  u16_t memerr;  /* Out of memory error. */
-  u16_t rterr;   /* Routing error. */
-  u16_t proterr; /* Protocol error. */
-  u16_t opterr;  /* Error in options. */
-  u16_t err;     /* Misc error. */
-  u16_t cachehit;
-};
-
-struct stats_mem {
-  mem_size_t avail;
-  mem_size_t used;
-  mem_size_t max;  
-  mem_size_t err;
-};
-
-struct stats_pbuf {
-  u16_t avail;
-  u16_t used;
-  u16_t max;  
-  u16_t err;
-
-  u16_t alloc_locked;
-  u16_t refresh_locked;
-};
-
-struct stats_syselem {
-  u16_t used;
-  u16_t max;
-  u16_t err;
-};
-
-struct stats_sys {
-  struct stats_syselem sem;
-  struct stats_syselem mbox;
-};
-
-struct stats_ {
-  struct stats_proto link;
-  struct stats_proto ip_frag;
-  struct stats_proto ip;
-  struct stats_proto icmp;
-  struct stats_proto udp;
-  struct stats_proto tcp;
-  struct stats_pbuf pbuf;
-  struct stats_mem mem;
-  struct stats_mem memp[MEMP_MAX];
-  struct stats_sys sys;
-};
-
-extern struct stats_ lwip_stats;
-
-
-void stats_init(void);
-
-#define STATS_INC(x) ++lwip_stats.x
-#else
-#define stats_init()
-#define STATS_INC(x)
-#endif /* LWIP_STATS */
-
-#if TCP_STATS
-#define TCP_STATS_INC(x) STATS_INC(x)
-#else
-#define TCP_STATS_INC(x)
-#endif
-
-#if UDP_STATS
-#define UDP_STATS_INC(x) STATS_INC(x)
-#else
-#define UDP_STATS_INC(x)
-#endif
-
-#if ICMP_STATS
-#define ICMP_STATS_INC(x) STATS_INC(x)
-#else
-#define ICMP_STATS_INC(x)
-#endif
-
-#if IP_STATS
-#define IP_STATS_INC(x) STATS_INC(x)
-#else
-#define IP_STATS_INC(x)
-#endif
-
-#if IPFRAG_STATS
-#define IPFRAG_STATS_INC(x) STATS_INC(x)
-#else
-#define IPFRAG_STATS_INC(x)
-#endif
-
-#if LINK_STATS
-#define LINK_STATS_INC(x) STATS_INC(x)
-#else
-#define LINK_STATS_INC(x)
-#endif
-
-/* Display of statistics */
-#if LWIP_STATS_DISPLAY
-void stats_display(void);
-#else
-#define stats_display()
-#endif
-
-#endif /* __LWIP_STATS_H__ */
-
-
-
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/sys.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/sys.h
deleted file mode 100644
index 68926e954..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/sys.h
+++ /dev/null
@@ -1,183 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_SYS_H__
-#define __LWIP_SYS_H__
-
-#include "arch/cc.h"
-
-#include "lwip/opt.h"
-
-
-#if NO_SYS
-
-/* For a totally minimal and standalone system, we provide null
-   definitions of the sys_ functions. */
-typedef u8_t sys_sem_t;
-typedef u8_t sys_mbox_t;
-struct sys_timeout {u8_t dummy;};
-
-#define sys_init()
-#define sys_timeout(m,h,a)
-#define sys_untimeout(m,a)
-#define sys_sem_new(c) c
-#define sys_sem_signal(s)
-#define sys_sem_wait(s)
-#define sys_sem_free(s)
-#define sys_mbox_new() 0
-#define sys_mbox_fetch(m,d)
-#define sys_mbox_post(m,d)
-#define sys_mbox_free(m)
-
-#define sys_thread_new(t,a,p)
-
-#else /* NO_SYS */
-
-#include "arch/sys_arch.h"
-
-/** Return code for timeouts from sys_arch_mbox_fetch and sys_arch_sem_wait */
-#define SYS_ARCH_TIMEOUT 0xffffffff
-
-typedef void (* sys_timeout_handler)(void *arg);
-
-struct sys_timeout {
-  struct sys_timeout *next;
-  u32_t time;
-  sys_timeout_handler h;
-  void *arg;
-};
-
-struct sys_timeouts {
-  struct sys_timeout *next;
-};
-
-/* sys_init() must be called before anthing else. */
-void sys_init(void);
-
-/*
- * sys_timeout():
- *
- * Schedule a timeout a specified amount of milliseconds in the
- * future. When the timeout occurs, the specified timeout handler will
- * be called. The handler will be passed the "arg" argument when
- * called.
- *
- */
-void sys_timeout(u32_t msecs, sys_timeout_handler h, void *arg);
-void sys_untimeout(sys_timeout_handler h, void *arg);
-struct sys_timeouts *sys_arch_timeouts(void);
-
-/* Semaphore functions. */
-sys_sem_t sys_sem_new(u8_t count);
-void sys_sem_signal(sys_sem_t sem);
-u32_t sys_arch_sem_wait(sys_sem_t sem, u32_t timeout);
-void sys_sem_free(sys_sem_t sem);
-void sys_sem_wait(sys_sem_t sem);
-int sys_sem_wait_timeout(sys_sem_t sem, u32_t timeout);
-
-/* Time functions. */
-#ifndef sys_msleep
-void sys_msleep(u32_t ms); /* only has a (close to) 1 jiffy resolution. */
-#endif
-#ifndef sys_jiffies
-u32_t sys_jiffies(void); /* since power up. */
-#endif
-
-/* Mailbox functions. */
-sys_mbox_t sys_mbox_new(void);
-void sys_mbox_post(sys_mbox_t mbox, void *msg);
-u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout);
-void sys_mbox_free(sys_mbox_t mbox);
-void sys_mbox_fetch(sys_mbox_t mbox, void **msg);
-
-
-/* Thread functions. */
-sys_thread_t sys_thread_new(void (* thread)(void *arg), void *arg, int prio);
-
-/* The following functions are used only in Unix code, and
-   can be omitted when porting the stack. */
-/* Returns the current time in microseconds. */
-unsigned long sys_now(void);
-
-#endif /* NO_SYS */
-
-/* Critical Region Protection */
-/* These functions must be implemented in the sys_arch.c file.
-   In some implementations they can provide a more light-weight protection
-   mechanism than using semaphores. Otherwise semaphores can be used for
-   implementation */
-#ifndef SYS_ARCH_PROTECT
-/** SYS_LIGHTWEIGHT_PROT
- * define SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection
- * for certain critical regions during buffer allocation, deallocation and memory
- * allocation and deallocation.
- */
-#if SYS_LIGHTWEIGHT_PROT
-
-/** SYS_ARCH_DECL_PROTECT
- * declare a protection variable. This macro will default to defining a variable of
- * type sys_prot_t. If a particular port needs a different implementation, then
- * this macro may be defined in sys_arch.h.
- */
-#define SYS_ARCH_DECL_PROTECT(lev) sys_prot_t lev
-/** SYS_ARCH_PROTECT
- * Perform a "fast" protect. This could be implemented by
- * disabling interrupts for an embedded system or by using a semaphore or
- * mutex. The implementation should allow calling SYS_ARCH_PROTECT when
- * already protected. The old protection level is returned in the variable
- * "lev". This macro will default to calling the sys_arch_protect() function
- * which should be implemented in sys_arch.c. If a particular port needs a
- * different implementation, then this macro may be defined in sys_arch.h
- */
-#define SYS_ARCH_PROTECT(lev) lev = sys_arch_protect()
-/** SYS_ARCH_UNPROTECT
- * Perform a "fast" set of the protection level to "lev". This could be
- * implemented by setting the interrupt level to "lev" within the MACRO or by
- * using a semaphore or mutex.  This macro will default to calling the
- * sys_arch_unprotect() function which should be implemented in
- * sys_arch.c. If a particular port needs a different implementation, then
- * this macro may be defined in sys_arch.h
- */
-#define SYS_ARCH_UNPROTECT(lev) sys_arch_unprotect(lev)
-sys_prot_t sys_arch_protect(void);
-void sys_arch_unprotect(sys_prot_t pval);
-
-#else
-
-#define SYS_ARCH_DECL_PROTECT(lev)
-#define SYS_ARCH_PROTECT(lev)
-#define SYS_ARCH_UNPROTECT(lev)
-
-#endif /* SYS_LIGHTWEIGHT_PROT */
-
-#endif /* SYS_ARCH_PROTECT */
-
-#endif /* __LWIP_SYS_H__ */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/tcp.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/tcp.h
deleted file mode 100644
index 301a3f023..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/tcp.h
+++ /dev/null
@@ -1,531 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_TCP_H__
-#define __LWIP_TCP_H__
-
-#include "lwip/sys.h"
-#include "lwip/mem.h"
-
-#include "lwip/pbuf.h"
-#include "lwip/opt.h"
-#include "lwip/ip.h"
-#include "lwip/icmp.h"
-
-#include "lwip/err.h"
-
-struct tcp_pcb;
-
-/* Functions for interfacing with TCP: */
-
-/* Lower layer interface to TCP: */
-void             tcp_init    (void);  /* Must be called first to
-           initialize TCP. */
-void             tcp_tmr     (void);  /* Must be called every
-           TCP_TMR_INTERVAL
-           ms. (Typically 250 ms). */
-/* Application program's interface: */
-struct tcp_pcb * tcp_new     (void);
-struct tcp_pcb * tcp_alloc   (u8_t prio);
-
-void             tcp_arg     (struct tcp_pcb *pcb, void *arg);
-void             tcp_accept  (struct tcp_pcb *pcb,
-            err_t (* accept)(void *arg, struct tcp_pcb *newpcb,
-                 err_t err));
-void             tcp_recv    (struct tcp_pcb *pcb,
-            err_t (* recv)(void *arg, struct tcp_pcb *tpcb,
-          struct pbuf *p, err_t err));
-void             tcp_sent    (struct tcp_pcb *pcb,
-            err_t (* sent)(void *arg, struct tcp_pcb *tpcb,
-               u16_t len));
-void             tcp_poll    (struct tcp_pcb *pcb,
-            err_t (* poll)(void *arg, struct tcp_pcb *tpcb),
-            u8_t interval);
-void             tcp_err     (struct tcp_pcb *pcb,
-            void (* err)(void *arg, err_t err));
-
-#define          tcp_mss(pcb)      ((pcb)->mss)
-#define          tcp_sndbuf(pcb)   ((pcb)->snd_buf)
-
-void             tcp_recved  (struct tcp_pcb *pcb, u16_t len);
-err_t            tcp_bind    (struct tcp_pcb *pcb, struct ip_addr *ipaddr,
-            u16_t port);
-err_t            tcp_connect (struct tcp_pcb *pcb, struct ip_addr *ipaddr,
-            u16_t port, err_t (* connected)(void *arg,
-                    struct tcp_pcb *tpcb,
-                    err_t err));
-struct tcp_pcb * tcp_listen  (struct tcp_pcb *pcb);
-void             tcp_abort   (struct tcp_pcb *pcb);
-err_t            tcp_close   (struct tcp_pcb *pcb);
-err_t            tcp_write   (struct tcp_pcb *pcb, const void *dataptr, u16_t len,
-            u8_t copy);
-
-void             tcp_setprio (struct tcp_pcb *pcb, u8_t prio);
-
-#define TCP_PRIO_MIN    1
-#define TCP_PRIO_NORMAL 64
-#define TCP_PRIO_MAX    127
-
-/* It is also possible to call these two functions at the right
-   intervals (instead of calling tcp_tmr()). */
-void             tcp_slowtmr (void);
-void             tcp_fasttmr (void);
-
-
-/* Only used by IP to pass a TCP segment to TCP: */
-void             tcp_input   (struct pbuf *p, struct netif *inp);
-/* Used within the TCP code only: */
-err_t            tcp_output  (struct tcp_pcb *pcb);
-void             tcp_rexmit  (struct tcp_pcb *pcb);
-void             tcp_rexmit_rto  (struct tcp_pcb *pcb);
-
-
-
-#define TCP_SEQ_LT(a,b)     ((s32_t)((a)-(b)) < 0)
-#define TCP_SEQ_LEQ(a,b)    ((s32_t)((a)-(b)) <= 0)
-#define TCP_SEQ_GT(a,b)     ((s32_t)((a)-(b)) > 0)
-#define TCP_SEQ_GEQ(a,b)    ((s32_t)((a)-(b)) >= 0)
-/* is b<=a<=c? */
-#if 0 /* see bug #10548 */
-#define TCP_SEQ_BETWEEN(a,b,c) ((c)-(b) >= (a)-(b))
-#endif
-#define TCP_SEQ_BETWEEN(a,b,c) (TCP_SEQ_GEQ(a,b) && TCP_SEQ_LEQ(a,c))
-#define TCP_FIN 0x01U
-#define TCP_SYN 0x02U
-#define TCP_RST 0x04U
-#define TCP_PSH 0x08U
-#define TCP_ACK 0x10U
-#define TCP_URG 0x20U
-#define TCP_ECE 0x40U
-#define TCP_CWR 0x80U
-
-#define TCP_FLAGS 0x3fU
-
-/* Length of the TCP header, excluding options. */
-#define TCP_HLEN 20
-
-#ifndef TCP_TMR_INTERVAL
-#define TCP_TMR_INTERVAL       250  /* The TCP timer interval in
-                                       milliseconds. */
-#endif /* TCP_TMR_INTERVAL */
-
-#ifndef TCP_FAST_INTERVAL
-#define TCP_FAST_INTERVAL      TCP_TMR_INTERVAL /* the fine grained timeout in
-                                       milliseconds */
-#endif /* TCP_FAST_INTERVAL */
-
-#ifndef TCP_SLOW_INTERVAL
-#define TCP_SLOW_INTERVAL      (2*TCP_TMR_INTERVAL)  /* the coarse grained timeout in
-                                       milliseconds */
-#endif /* TCP_SLOW_INTERVAL */
-
-#define TCP_FIN_WAIT_TIMEOUT 20000 /* milliseconds */
-#define TCP_SYN_RCVD_TIMEOUT 20000 /* milliseconds */
-
-#define TCP_OOSEQ_TIMEOUT        6 /* x RTO */
-
-#define TCP_MSL 60000  /* The maximum segment lifetime in microseconds */
-
-/*
- * User-settable options (used with setsockopt).
- */
-#define	TCP_NODELAY	   0x01	   /* don't delay send to coalesce packets */
-#define TCP_KEEPALIVE  0x02    /* send KEEPALIVE probes when idle for pcb->keepalive miliseconds */
-
-/* Keepalive values */
-#define  TCP_KEEPDEFAULT   7200000                       /* KEEPALIVE timer in miliseconds */
-#define  TCP_KEEPINTVL     75000                         /* Time between KEEPALIVE probes in miliseconds */
-#define  TCP_KEEPCNT       9                             /* Counter for KEEPALIVE probes */
-#define  TCP_MAXIDLE       TCP_KEEPCNT * TCP_KEEPINTVL   /* Maximum KEEPALIVE probe time */
-
-
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-struct tcp_hdr {
-  PACK_STRUCT_FIELD(u16_t src);
-  PACK_STRUCT_FIELD(u16_t dest);
-  PACK_STRUCT_FIELD(u32_t seqno);
-  PACK_STRUCT_FIELD(u32_t ackno);
-  PACK_STRUCT_FIELD(u16_t _hdrlen_rsvd_flags);
-  PACK_STRUCT_FIELD(u16_t wnd);
-  PACK_STRUCT_FIELD(u16_t chksum);
-  PACK_STRUCT_FIELD(u16_t urgp);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-#define TCPH_OFFSET(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) >> 8)
-#define TCPH_HDRLEN(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) >> 12)
-#define TCPH_FLAGS(phdr)  (ntohs((phdr)->_hdrlen_rsvd_flags) & TCP_FLAGS)
-
-#define TCPH_OFFSET_SET(phdr, offset) (phdr)->_hdrlen_rsvd_flags = htons(((offset) << 8) | TCPH_FLAGS(phdr))
-#define TCPH_HDRLEN_SET(phdr, len) (phdr)->_hdrlen_rsvd_flags = htons(((len) << 12) | TCPH_FLAGS(phdr))
-#define TCPH_FLAGS_SET(phdr, flags) (phdr)->_hdrlen_rsvd_flags = htons((ntohs((phdr)->_hdrlen_rsvd_flags) & ~TCP_FLAGS) | (flags))
-#define TCPH_SET_FLAG(phdr, flags ) (phdr)->_hdrlen_rsvd_flags = htons(ntohs((phdr)->_hdrlen_rsvd_flags) | (flags))
-#define TCPH_UNSET_FLAG(phdr, flags) (phdr)->_hdrlen_rsvd_flags = htons(ntohs((phdr)->_hdrlen_rsvd_flags) | (TCPH_FLAGS(phdr) & ~(flags)) )
-
-#define TCP_TCPLEN(seg) ((seg)->len + ((TCPH_FLAGS((seg)->tcphdr) & TCP_FIN || \
-          TCPH_FLAGS((seg)->tcphdr) & TCP_SYN)? 1: 0))
-
-enum tcp_state {
-  CLOSED      = 0,
-  LISTEN      = 1,
-  SYN_SENT    = 2,
-  SYN_RCVD    = 3,
-  ESTABLISHED = 4,
-  FIN_WAIT_1  = 5,
-  FIN_WAIT_2  = 6,
-  CLOSE_WAIT  = 7,
-  CLOSING     = 8,
-  LAST_ACK    = 9,
-  TIME_WAIT   = 10
-};
-
-/* the TCP protocol control block */
-struct tcp_pcb {
-/** common PCB members */
-  IP_PCB;
-/** protocol specific PCB members */
-  struct tcp_pcb *next; /* for the linked list */
-  enum tcp_state state; /* TCP state */
-  u8_t prio;
-  void *callback_arg;
-
-  u16_t local_port;
-  u16_t remote_port;
-  
-  u8_t flags;
-#define TF_ACK_DELAY (u8_t)0x01U   /* Delayed ACK. */
-#define TF_ACK_NOW   (u8_t)0x02U   /* Immediate ACK. */
-#define TF_INFR      (u8_t)0x04U   /* In fast recovery. */
-#define TF_RESET     (u8_t)0x08U   /* Connection was reset. */
-#define TF_CLOSED    (u8_t)0x10U   /* Connection was sucessfully closed. */
-#define TF_GOT_FIN   (u8_t)0x20U   /* Connection was closed by the remote end. */
-#define TF_NODELAY   (u8_t)0x40U   /* Disable Nagle algorithm */
-
-  /* receiver variables */
-  u32_t rcv_nxt;   /* next seqno expected */
-  u16_t rcv_wnd;   /* receiver window */
-  
-  /* Timers */
-  u32_t tmr;
-  u8_t polltmr, pollinterval;
-  
-  /* Retransmission timer. */
-  u16_t rtime;
-  
-  u16_t mss;   /* maximum segment size */
-  
-  /* RTT (round trip time) estimation variables */
-  u32_t rttest; /* RTT estimate in 500ms ticks */
-  u32_t rtseq;  /* sequence number being timed */
-  s16_t sa, sv; /* @todo document this */
-
-  u16_t rto;    /* retransmission time-out */
-  u8_t nrtx;    /* number of retransmissions */
-
-  /* fast retransmit/recovery */
-  u32_t lastack; /* Highest acknowledged seqno. */
-  u8_t dupacks;
-  
-  /* congestion avoidance/control variables */
-  u16_t cwnd;  
-  u16_t ssthresh;
-
-  /* sender variables */
-  u32_t snd_nxt,       /* next seqno to be sent */
-    snd_max,       /* Highest seqno sent. */
-    snd_wnd,       /* sender window */
-    snd_wl1, snd_wl2, /* Sequence and acknowledgement numbers of last
-       window update. */
-    snd_lbb;       /* Sequence number of next byte to be buffered. */
-
-  u16_t acked;
-  
-  u16_t snd_buf;   /* Available buffer space for sending (in bytes). */
-  u8_t snd_queuelen; /* Available buffer space for sending (in tcp_segs). */
-  
-  
-  /* These are ordered by sequence number: */
-  struct tcp_seg *unsent;   /* Unsent (queued) segments. */
-  struct tcp_seg *unacked;  /* Sent but unacknowledged segments. */
-#if TCP_QUEUE_OOSEQ  
-  struct tcp_seg *ooseq;    /* Received out of sequence segments. */
-#endif /* TCP_QUEUE_OOSEQ */
-
-#if LWIP_CALLBACK_API
-  /* Function to be called when more send buffer space is available. */
-  err_t (* sent)(void *arg, struct tcp_pcb *pcb, u16_t space);
-  
-  /* Function to be called when (in-sequence) data has arrived. */
-  err_t (* recv)(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err);
-
-  /* Function to be called when a connection has been set up. */
-  err_t (* connected)(void *arg, struct tcp_pcb *pcb, err_t err);
-
-  /* Function to call when a listener has been connected. */
-  err_t (* accept)(void *arg, struct tcp_pcb *newpcb, err_t err);
-
-  /* Function which is called periodically. */
-  err_t (* poll)(void *arg, struct tcp_pcb *pcb);
-
-  /* Function to be called whenever a fatal error occurs. */
-  void (* errf)(void *arg, err_t err);
-#endif /* LWIP_CALLBACK_API */
-
-  /* idle time before KEEPALIVE is sent */
-  u32_t keepalive;
-  
-  /* KEEPALIVE counter */
-  u8_t keep_cnt;
-};
-
-struct tcp_pcb_listen {  
-/* Common members of all PCB types */
-  IP_PCB;
-
-/* Protocol specific PCB members */
-  struct tcp_pcb_listen *next;   /* for the linked list */
-  
-  /* Even if state is obviously LISTEN this is here for
-   * field compatibility with tpc_pcb to which it is cast sometimes
-   * Until a cleaner solution emerges this is here.FIXME
-   */ 
-  enum tcp_state state;   /* TCP state */
-
-  u8_t prio;
-  void *callback_arg;
-  
-  u16_t local_port; 
-
-#if LWIP_CALLBACK_API
-  /* Function to call when a listener has been connected. */
-  err_t (* accept)(void *arg, struct tcp_pcb *newpcb, err_t err);
-#endif /* LWIP_CALLBACK_API */
-};
-
-#if LWIP_EVENT_API
-
-enum lwip_event {
-  LWIP_EVENT_ACCEPT,
-  LWIP_EVENT_SENT,
-  LWIP_EVENT_RECV,
-  LWIP_EVENT_CONNECTED,
-  LWIP_EVENT_POLL,
-  LWIP_EVENT_ERR
-};
-
-err_t lwip_tcp_event(void *arg, struct tcp_pcb *pcb,
-         enum lwip_event,
-         struct pbuf *p,
-         u16_t size,
-         err_t err);
-
-#define TCP_EVENT_ACCEPT(pcb,err,ret)    ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
-                LWIP_EVENT_ACCEPT, NULL, 0, err)
-#define TCP_EVENT_SENT(pcb,space,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
-                   LWIP_EVENT_SENT, NULL, space, ERR_OK)
-#define TCP_EVENT_RECV(pcb,p,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
-                LWIP_EVENT_RECV, (p), 0, (err))
-#define TCP_EVENT_CONNECTED(pcb,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
-                LWIP_EVENT_CONNECTED, NULL, 0, (err))
-#define TCP_EVENT_POLL(pcb,ret)       ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
-                LWIP_EVENT_POLL, NULL, 0, ERR_OK)
-#define TCP_EVENT_ERR(errf,arg,err)  lwip_tcp_event((arg), NULL, \
-                LWIP_EVENT_ERR, NULL, 0, (err))
-#else /* LWIP_EVENT_API */
-#define TCP_EVENT_ACCEPT(pcb,err,ret)     \
-                        if((pcb)->accept != NULL) \
-                        (ret = (pcb)->accept((pcb)->callback_arg,(pcb),(err)))
-#define TCP_EVENT_SENT(pcb,space,ret) \
-                        if((pcb)->sent != NULL) \
-                        (ret = (pcb)->sent((pcb)->callback_arg,(pcb),(space)))
-#define TCP_EVENT_RECV(pcb,p,err,ret) \
-                        if((pcb)->recv != NULL) \
-                        { ret = (pcb)->recv((pcb)->callback_arg,(pcb),(p),(err)); } else { \
-                          if (p) pbuf_free(p); }
-#define TCP_EVENT_CONNECTED(pcb,err,ret) \
-                        if((pcb)->connected != NULL) \
-                        (ret = (pcb)->connected((pcb)->callback_arg,(pcb),(err)))
-#define TCP_EVENT_POLL(pcb,ret) \
-                        if((pcb)->poll != NULL) \
-                        (ret = (pcb)->poll((pcb)->callback_arg,(pcb)))
-#define TCP_EVENT_ERR(errf,arg,err) \
-                        if((errf) != NULL) \
-                        (errf)((arg),(err))
-#endif /* LWIP_EVENT_API */
-
-/* This structure represents a TCP segment on the unsent and unacked queues */
-struct tcp_seg {
-  struct tcp_seg *next;    /* used when putting segements on a queue */
-  struct pbuf *p;          /* buffer containing data + TCP header */
-  void *dataptr;           /* pointer to the TCP data in the pbuf */
-  u16_t len;               /* the TCP length of this segment */
-  struct tcp_hdr *tcphdr;  /* the TCP header */
-};
-
-/* Internal functions and global variables: */
-struct tcp_pcb *tcp_pcb_copy(struct tcp_pcb *pcb);
-void tcp_pcb_purge(struct tcp_pcb *pcb);
-void tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb);
-
-u8_t tcp_segs_free(struct tcp_seg *seg);
-u8_t tcp_seg_free(struct tcp_seg *seg);
-struct tcp_seg *tcp_seg_copy(struct tcp_seg *seg);
-
-#define tcp_ack(pcb)     if((pcb)->flags & TF_ACK_DELAY) { \
-                            (pcb)->flags &= ~TF_ACK_DELAY; \
-                            (pcb)->flags |= TF_ACK_NOW; \
-                            tcp_output(pcb); \
-                         } else { \
-                            (pcb)->flags |= TF_ACK_DELAY; \
-                         }
-
-#define tcp_ack_now(pcb) (pcb)->flags |= TF_ACK_NOW; \
-                         tcp_output(pcb)
-
-err_t tcp_send_ctrl(struct tcp_pcb *pcb, u8_t flags);
-err_t tcp_enqueue(struct tcp_pcb *pcb, void *dataptr, u16_t len,
-    u8_t flags, u8_t copy,
-                u8_t *optdata, u8_t optlen);
-
-void tcp_rexmit_seg(struct tcp_pcb *pcb, struct tcp_seg *seg);
-
-void tcp_rst(u32_t seqno, u32_t ackno,
-       struct ip_addr *local_ip, struct ip_addr *remote_ip,
-       u16_t local_port, u16_t remote_port);
-
-u32_t tcp_next_iss(void);
-
-void tcp_keepalive(struct tcp_pcb *pcb);
-
-extern struct tcp_pcb *tcp_input_pcb;
-extern u32_t tcp_ticks;
-
-#if TCP_DEBUG || TCP_INPUT_DEBUG || TCP_OUTPUT_DEBUG
-void tcp_debug_print(struct tcp_hdr *tcphdr);
-void tcp_debug_print_flags(u8_t flags);
-void tcp_debug_print_state(enum tcp_state s);
-void tcp_debug_print_pcbs(void);
-int tcp_pcbs_sane(void);
-#else
-#  define tcp_debug_print(tcphdr)
-#  define tcp_debug_print_flags(flags)
-#  define tcp_debug_print_state(s)
-#  define tcp_debug_print_pcbs()
-#  define tcp_pcbs_sane() 1
-#endif /* TCP_DEBUG */
-
-#if NO_SYS
-#define tcp_timer_needed()
-#else
-void tcp_timer_needed(void);
-#endif
-
-/* The TCP PCB lists. */
-union tcp_listen_pcbs_t { /* List of all TCP PCBs in LISTEN state. */
-	struct tcp_pcb_listen *listen_pcbs; 
-	struct tcp_pcb *pcbs;
-};
-extern union tcp_listen_pcbs_t tcp_listen_pcbs;
-extern struct tcp_pcb *tcp_active_pcbs;  /* List of all TCP PCBs that are in a
-              state in which they accept or send
-              data. */
-extern struct tcp_pcb *tcp_tw_pcbs;      /* List of all TCP PCBs in TIME-WAIT. */
-
-extern struct tcp_pcb *tcp_tmp_pcb;      /* Only used for temporary storage. */
-
-/* Axioms about the above lists:   
-   1) Every TCP PCB that is not CLOSED is in one of the lists.
-   2) A PCB is only in one of the lists.
-   3) All PCBs in the tcp_listen_pcbs list is in LISTEN state.
-   4) All PCBs in the tcp_tw_pcbs list is in TIME-WAIT state.
-*/
-
-/* Define two macros, TCP_REG and TCP_RMV that registers a TCP PCB
-   with a PCB list or removes a PCB from a list, respectively. */
-#if 0
-#define TCP_REG(pcbs, npcb) do {\
-                            LWIP_DEBUGF(TCP_DEBUG, ("TCP_REG %p local port %d\n", npcb, npcb->local_port)); \
-                            for(tcp_tmp_pcb = *pcbs; \
-          tcp_tmp_pcb != NULL; \
-        tcp_tmp_pcb = tcp_tmp_pcb->next) { \
-                                LWIP_ASSERT("TCP_REG: already registered\n", tcp_tmp_pcb != npcb); \
-                            } \
-                            LWIP_ASSERT("TCP_REG: pcb->state != CLOSED", npcb->state != CLOSED); \
-                            npcb->next = *pcbs; \
-                            LWIP_ASSERT("TCP_REG: npcb->next != npcb", npcb->next != npcb); \
-                            *(pcbs) = npcb; \
-                            LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \
-              tcp_timer_needed(); \
-                            } while(0)
-#define TCP_RMV(pcbs, npcb) do { \
-                            LWIP_ASSERT("TCP_RMV: pcbs != NULL", *pcbs != NULL); \
-                            LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removing %p from %p\n", npcb, *pcbs)); \
-                            if(*pcbs == npcb) { \
-                               *pcbs = (*pcbs)->next; \
-                            } else for(tcp_tmp_pcb = *pcbs; tcp_tmp_pcb != NULL; tcp_tmp_pcb = tcp_tmp_pcb->next) { \
-                               if(tcp_tmp_pcb->next != NULL && tcp_tmp_pcb->next == npcb) { \
-                                  tcp_tmp_pcb->next = npcb->next; \
-                                  break; \
-                               } \
-                            } \
-                            npcb->next = NULL; \
-                            LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \
-                            LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removed %p from %p\n", npcb, *pcbs)); \
-                            } while(0)
-
-#else /* LWIP_DEBUG */
-#define TCP_REG(pcbs, npcb) do { \
-                            npcb->next = *pcbs; \
-                            *(pcbs) = npcb; \
-              tcp_timer_needed(); \
-                            } while(0)
-#define TCP_RMV(pcbs, npcb) do { \
-                            if(*(pcbs) == npcb) { \
-                               (*(pcbs)) = (*pcbs)->next; \
-                            } else for(tcp_tmp_pcb = *pcbs; tcp_tmp_pcb != NULL; tcp_tmp_pcb = tcp_tmp_pcb->next) { \
-                               if(tcp_tmp_pcb->next != NULL && tcp_tmp_pcb->next == npcb) { \
-                                  tcp_tmp_pcb->next = npcb->next; \
-                                  break; \
-                               } \
-                            } \
-                            npcb->next = NULL; \
-                            } while(0)
-#endif /* LWIP_DEBUG */
-#endif /* __LWIP_TCP_H__ */
-
-
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/tcpip.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/tcpip.h
deleted file mode 100644
index 316ae4fc5..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/tcpip.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_TCPIP_H__
-#define __LWIP_TCPIP_H__
-
-#include "lwip/api_msg.h"
-#include "lwip/pbuf.h"
-
-void tcpip_init(void (* tcpip_init_done)(void *), void *arg);
-void tcpip_apimsg(struct api_msg *apimsg);
-err_t tcpip_input(struct pbuf *p, struct netif *inp);
-err_t tcpip_callback(void (*f)(void *ctx), void *ctx);
-
-void tcpip_tcp_timer_needed(void);
-
-enum tcpip_msg_type {
-  TCPIP_MSG_API,
-  TCPIP_MSG_INPUT,
-  TCPIP_MSG_CALLBACK
-};
-
-struct tcpip_msg {
-  enum tcpip_msg_type type;
-  sys_sem_t *sem;
-  union {
-    struct api_msg *apimsg;
-    struct {
-      struct pbuf *p;
-      struct netif *netif;
-    } inp;
-    struct {
-      void (*f)(void *ctx);
-      void *ctx;
-    } cb;
-  } msg;
-};
-
-
-#endif /* __LWIP_TCPIP_H__ */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/udp.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/udp.h
deleted file mode 100644
index c54859476..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/lwip/udp.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_UDP_H__
-#define __LWIP_UDP_H__
-
-#include "lwip/arch.h"
-
-#include "lwip/pbuf.h"
-#include "lwip/inet.h"
-#include "lwip/ip.h"
-
-#define UDP_HLEN 8
-
-struct udp_hdr {
-  PACK_STRUCT_FIELD(u16_t src);
-  PACK_STRUCT_FIELD(u16_t dest);  /* src/dest UDP ports */
-  PACK_STRUCT_FIELD(u16_t len);
-  PACK_STRUCT_FIELD(u16_t chksum);
-} PACK_STRUCT_STRUCT;
-
-#define UDP_FLAGS_NOCHKSUM 0x01U
-#define UDP_FLAGS_UDPLITE  0x02U
-#define UDP_FLAGS_CONNECTED  0x04U
-
-struct udp_pcb {
-/* Common members of all PCB types */
-  IP_PCB;
-
-/* Protocol specific PCB members */
-
-  struct udp_pcb *next;
-
-  u8_t flags;
-  u16_t local_port, remote_port;
-  
-  u16_t chksum_len;
-  
-  void (* recv)(void *arg, struct udp_pcb *pcb, struct pbuf *p,
-    struct ip_addr *addr, u16_t port);
-  void *recv_arg;  
-};
-
-/* The following functions is the application layer interface to the
-   UDP code. */
-struct udp_pcb * udp_new        (void);
-void             udp_remove     (struct udp_pcb *pcb);
-err_t            udp_bind       (struct udp_pcb *pcb, struct ip_addr *ipaddr,
-                 u16_t port);
-err_t            udp_connect    (struct udp_pcb *pcb, struct ip_addr *ipaddr,
-                 u16_t port);
-void             udp_disconnect    (struct udp_pcb *pcb);
-void             udp_recv       (struct udp_pcb *pcb,
-         void (* recv)(void *arg, struct udp_pcb *upcb,
-                 struct pbuf *p,
-                 struct ip_addr *addr,
-                 u16_t port),
-         void *recv_arg);
-err_t            udp_sendto     (struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *dst_ip, u16_t dst_port);
-err_t            udp_send       (struct udp_pcb *pcb, struct pbuf *p);
-
-#define          udp_flags(pcb)  ((pcb)->flags)
-#define          udp_setflags(pcb, f)  ((pcb)->flags = (f))
-
-/* The following functions are the lower layer interface to UDP. */
-void             udp_input      (struct pbuf *p, struct netif *inp);
-void             udp_init       (void);
-
-#if UDP_DEBUG
-int udp_debug_print(struct udp_hdr *udphdr);
-#else
-#define udp_debug_print(udphdr)
-#endif
-#endif /* __LWIP_UDP_H__ */
-
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/netif/etharp.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/netif/etharp.h
deleted file mode 100644
index 08437afe5..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/netif/etharp.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
- * Copyright (c) 2003-2004 Leon Woestenberg 
- * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-
-#ifndef __NETIF_ETHARP_H__
-#define __NETIF_ETHARP_H__
-
-#ifndef ETH_PAD_SIZE
-#define ETH_PAD_SIZE 0
-#endif
-
-#include "lwip/pbuf.h"
-#include "lwip/ip_addr.h"
-#include "lwip/netif.h"
-#include "lwip/ip.h"
-
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-struct eth_addr {
-  PACK_STRUCT_FIELD(u8_t addr[6]);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-struct eth_hdr {
-#if ETH_PAD_SIZE
-  PACK_STRUCT_FIELD(u8_t padding[ETH_PAD_SIZE]);
-#endif
-  PACK_STRUCT_FIELD(struct eth_addr dest);
-  PACK_STRUCT_FIELD(struct eth_addr src);
-  PACK_STRUCT_FIELD(u16_t type);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-/** the ARP message */
-struct etharp_hdr {
-  PACK_STRUCT_FIELD(struct eth_hdr ethhdr);
-  PACK_STRUCT_FIELD(u16_t hwtype);
-  PACK_STRUCT_FIELD(u16_t proto);
-  PACK_STRUCT_FIELD(u16_t _hwlen_protolen);
-  PACK_STRUCT_FIELD(u16_t opcode);
-  PACK_STRUCT_FIELD(struct eth_addr shwaddr);
-  PACK_STRUCT_FIELD(struct ip_addr2 sipaddr);
-  PACK_STRUCT_FIELD(struct eth_addr dhwaddr);
-  PACK_STRUCT_FIELD(struct ip_addr2 dipaddr);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-struct ethip_hdr {
-  PACK_STRUCT_FIELD(struct eth_hdr eth);
-  PACK_STRUCT_FIELD(struct ip_hdr ip);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-/** 5 seconds period */
-#define ARP_TMR_INTERVAL 5000
-
-#define ETHTYPE_ARP 0x0806
-#define ETHTYPE_IP  0x0800
-
-void etharp_init(void);
-void etharp_tmr(void);
-void etharp_ip_input(struct netif *netif, struct pbuf *p);
-void etharp_arp_input(struct netif *netif, struct eth_addr *ethaddr,
-         struct pbuf *p);
-err_t etharp_output(struct netif *netif, struct ip_addr *ipaddr,
-         struct pbuf *q);
-err_t etharp_query(struct netif *netif, struct ip_addr *ipaddr, struct pbuf *q);
-err_t etharp_request(struct netif *netif, struct ip_addr *ipaddr);
-
-#endif /* __NETIF_ARP_H__ */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/netif/loopif.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/netif/loopif.h
deleted file mode 100644
index 97b3c6764..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/netif/loopif.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __NETIF_LOOPIF_H__
-#define __NETIF_LOOPIF_H__
-
-#include "lwip/netif.h"
-
-err_t loopif_init(struct netif *netif);
-
-#endif /* __NETIF_LOOPIF_H__ */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/netif/slipif.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/netif/slipif.h
deleted file mode 100644
index bf70046a9..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/include/netif/slipif.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (c) 2001, Swedish Institute of Computer Science.
- * All rights reserved. 
- *
- * Redistribution and use in source and binary forms, with or without 
- * modification, are permitted provided that the following conditions 
- * are met: 
- * 1. Redistributions of source code must retain the above copyright 
- *    notice, this list of conditions and the following disclaimer. 
- * 2. Redistributions in binary form must reproduce the above copyright 
- *    notice, this list of conditions and the following disclaimer in the 
- *    documentation and/or other materials provided with the distribution. 
- * 3. Neither the name of the Institute nor the names of its contributors 
- *    may be used to endorse or promote products derived from this software 
- *    without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
- * SUCH DAMAGE. 
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __NETIF_SLIPIF_H__
-#define __NETIF_SLIPIF_H__
-
-#include "lwip/netif.h"
-
-err_t slipif_init(struct netif * netif);
- 
-#endif 
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/FILES b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/FILES
deleted file mode 100644
index 825d40715..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/FILES
+++ /dev/null
@@ -1,27 +0,0 @@
-This directory contains generic network interface device drivers that
-do not contain any hardware or architecture specific code. The files
-are:
-
-etharp.c
-          Implements the ARP (Address Resolution Protocol) over
-          Ethernet. The code in this file should be used together with
-          Ethernet device drivers. Note that this module has been
-          largely made Ethernet independent so you should be able to
-          adapt this for other link layers (such as Firewire).
-
-ethernetif.c
-          An example of how an Ethernet device driver could look. This
-          file can be used as a "skeleton" for developing new Ethernet
-          network device drivers. It uses the etharp.c ARP code.
-
-loopif.c
-          An example network interface that shows how a "loopback"
-          interface would work. This is not really intended for actual
-          use, but as a very basic example of how initialization and
-          output functions work.
-
-slipif.c
-          A generic implementation of the SLIP (Serial Line IP)
-          protocol. It requires a sio (serial I/O) module to work.
-	  
-ppp/      Point-to-Point Protocol stack
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/etharp.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/etharp.c
deleted file mode 100644
index 11f4973bd..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/etharp.c
+++ /dev/null
@@ -1,828 +0,0 @@
-/**
- * @file
- * Address Resolution Protocol module for IP over Ethernet
- *
- * Functionally, ARP is divided into two parts. The first maps an IP address
- * to a physical address when sending a packet, and the second part answers
- * requests from other machines for our physical address.
- *
- * This implementation complies with RFC 826 (Ethernet ARP). It supports
- * Gratuitious ARP from RFC3220 (IP Mobility Support for IPv4) section 4.6
- * if an interface calls etharp_query(our_netif, its_ip_addr, NULL) upon
- * address change.
- */
-
-/*
- * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
- * Copyright (c) 2003-2004 Leon Woestenberg 
- * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- */
-
-#include "lwip/opt.h"
-#include "lwip/inet.h"
-#include "netif/etharp.h"
-#include "lwip/ip.h"
-#include "lwip/stats.h"
-
-/* ARP needs to inform DHCP of any ARP replies? */
-#if (LWIP_DHCP && DHCP_DOES_ARP_CHECK)
-#  include "lwip/dhcp.h"
-#endif
-
-/** the time an ARP entry stays valid after its last update,
- * (240 * 5) seconds = 20 minutes.
- */
-#define ARP_MAXAGE 240
-/** the time an ARP entry stays pending after first request,
- * (2 * 5) seconds = 10 seconds.
- * 
- * @internal Keep this number at least 2, otherwise it might
- * run out instantly if the timeout occurs directly after a request.
- */
-#define ARP_MAXPENDING 2
-
-#define HWTYPE_ETHERNET 1
-
-/** ARP message types */
-#define ARP_REQUEST 1
-#define ARP_REPLY 2
-
-#define ARPH_HWLEN(hdr) (ntohs((hdr)->_hwlen_protolen) >> 8)
-#define ARPH_PROTOLEN(hdr) (ntohs((hdr)->_hwlen_protolen) & 0xff)
-
-#define ARPH_HWLEN_SET(hdr, len) (hdr)->_hwlen_protolen = htons(ARPH_PROTOLEN(hdr) | ((len) << 8))
-#define ARPH_PROTOLEN_SET(hdr, len) (hdr)->_hwlen_protolen = htons((len) | (ARPH_HWLEN(hdr) << 8))
-
-enum etharp_state {
-  ETHARP_STATE_EMPTY,
-  ETHARP_STATE_PENDING,
-  ETHARP_STATE_STABLE,
-  /** @internal transitional state used in etharp_tmr() for convenience*/
-  ETHARP_STATE_EXPIRED
-};
-
-struct etharp_entry {
-#if ARP_QUEUEING
-  /** 
-   * Pointer to queue of pending outgoing packets on this ARP entry.
-   */
-   struct pbuf *p;
-#endif
-  struct ip_addr ipaddr;
-  struct eth_addr ethaddr;
-  enum etharp_state state;
-  u8_t ctime;
-};
-
-static const struct eth_addr ethbroadcast = {{0xff,0xff,0xff,0xff,0xff,0xff}};
-static struct etharp_entry arp_table[ARP_TABLE_SIZE];
-
-/**
- * Try hard to create a new entry - we want the IP address to appear in
- * the cache (even if this means removing an active entry or so). */
-#define ETHARP_TRY_HARD 1
-
-static s8_t find_entry(struct ip_addr *ipaddr, u8_t flags);
-static err_t update_arp_entry(struct netif *netif, struct ip_addr *ipaddr, struct eth_addr *ethaddr, u8_t flags);
-/**
- * Initializes ARP module.
- */
-void
-etharp_init(void)
-{
-  u8_t i;
-  /* clear ARP entries */
-  for(i = 0; i < ARP_TABLE_SIZE; ++i) {
-    arp_table[i].state = ETHARP_STATE_EMPTY;
-#if ARP_QUEUEING
-    arp_table[i].p = NULL;
-#endif
-    arp_table[i].ctime = 0;
-  }
-}
-
-/**
- * Clears expired entries in the ARP table.
- *
- * This function should be called every ETHARP_TMR_INTERVAL microseconds (5 seconds),
- * in order to expire entries in the ARP table.
- */
-void
-etharp_tmr(void)
-{
-  u8_t i;
-
-  LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer\n"));
-  /* remove expired entries from the ARP table */
-  for (i = 0; i < ARP_TABLE_SIZE; ++i) {
-    arp_table[i].ctime++;
-    /* stable entry? */
-    if ((arp_table[i].state == ETHARP_STATE_STABLE) &&
-         /* entry has become old? */
-        (arp_table[i].ctime >= ARP_MAXAGE)) {
-      LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: expired stable entry %u.\n", i));
-      arp_table[i].state = ETHARP_STATE_EXPIRED;
-    /* pending entry? */
-    } else if (arp_table[i].state == ETHARP_STATE_PENDING) {
-      /* entry unresolved/pending for too long? */
-      if (arp_table[i].ctime >= ARP_MAXPENDING) {
-        LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: expired pending entry %u.\n", i));
-        arp_table[i].state = ETHARP_STATE_EXPIRED;
-#if ARP_QUEUEING
-      } else if (arp_table[i].p != NULL) {
-        /* resend an ARP query here */
-#endif
-      }
-    }
-    /* clean up entries that have just been expired */
-    if (arp_table[i].state == ETHARP_STATE_EXPIRED) {
-#if ARP_QUEUEING
-      /* and empty packet queue */
-      if (arp_table[i].p != NULL) {
-        /* remove all queued packets */
-        LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: freeing entry %u, packet queue %p.\n", i, (void *)(arp_table[i].p)));
-        pbuf_free(arp_table[i].p);
-        arp_table[i].p = NULL;
-      }
-#endif
-      /* recycle entry for re-use */      
-      arp_table[i].state = ETHARP_STATE_EMPTY;
-    }
-  }
-}
-
-/**
- * Search the ARP table for a matching or new entry.
- * 
- * If an IP address is given, return a pending or stable ARP entry that matches
- * the address. If no match is found, create a new entry with this address set,
- * but in state ETHARP_EMPTY. The caller must check and possibly change the
- * state of the returned entry.
- * 
- * If ipaddr is NULL, return a initialized new entry in state ETHARP_EMPTY.
- * 
- * In all cases, attempt to create new entries from an empty entry. If no
- * empty entries are available and ETHARP_TRY_HARD flag is set, recycle
- * old entries. Heuristic choose the least important entry for recycling.
- *
- * @param ipaddr IP address to find in ARP cache, or to add if not found.
- * @param flags
- * - ETHARP_TRY_HARD: Try hard to create a entry by allowing recycling of
- * active (stable or pending) entries.
- *  
- * @return The ARP entry index that matched or is created, ERR_MEM if no
- * entry is found or could be recycled.
- */
-static s8_t find_entry(struct ip_addr *ipaddr, u8_t flags)
-{
-  s8_t old_pending = ARP_TABLE_SIZE, old_stable = ARP_TABLE_SIZE;
-  s8_t empty = ARP_TABLE_SIZE;
-  u8_t i = 0, age_pending = 0, age_stable = 0;
-#if ARP_QUEUEING
-  /* oldest entry with packets on queue */
-  s8_t old_queue = ARP_TABLE_SIZE;
-  /* its age */
-  u8_t age_queue = 0;
-#endif
-
-  /**
-   * a) do a search through the cache, remember candidates
-   * b) select candidate entry
-   * c) create new entry
-   */
-
-  /* a) in a single search sweep, do all of this
-   * 1) remember the first empty entry (if any)
-   * 2) remember the oldest stable entry (if any)
-   * 3) remember the oldest pending entry without queued packets (if any)
-   * 4) remember the oldest pending entry with queued packets (if any)
-   * 5) search for a matching IP entry, either pending or stable
-   *    until 5 matches, or all entries are searched for.
-   */
-
-  for (i = 0; i < ARP_TABLE_SIZE; ++i) {
-    /* no empty entry found yet and now we do find one? */
-    if ((empty == ARP_TABLE_SIZE) && (arp_table[i].state == ETHARP_STATE_EMPTY)) {
-      LWIP_DEBUGF(ETHARP_DEBUG, ("find_entry: found empty entry %d\n", i));
-      /* remember first empty entry */
-      empty = i;
-    }
-    /* pending entry? */
-    else if (arp_table[i].state == ETHARP_STATE_PENDING) {
-      /* if given, does IP address match IP address in ARP entry? */
-      if (ipaddr && ip_addr_cmp(ipaddr, &arp_table[i].ipaddr)) {
-        LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: found matching pending entry %d\n", i));
-        /* found exact IP address match, simply bail out */
-        return i;
-#if ARP_QUEUEING
-      /* pending with queued packets? */
-      } else if (arp_table[i].p != NULL) {
-        if (arp_table[i].ctime >= age_queue) {
-          old_queue = i;
-          age_queue = arp_table[i].ctime;
-        }
-#endif
-      /* pending without queued packets? */
-      } else {
-        if (arp_table[i].ctime >= age_pending) {
-          old_pending = i;
-          age_pending = arp_table[i].ctime;
-        }
-      }        
-    }
-    /* stable entry? */
-    else if (arp_table[i].state == ETHARP_STATE_STABLE) {
-      /* if given, does IP address match IP address in ARP entry? */
-      if (ipaddr && ip_addr_cmp(ipaddr, &arp_table[i].ipaddr)) {
-        LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: found matching stable entry %d\n", i));
-        /* found exact IP address match, simply bail out */
-        return i;
-      /* remember entry with oldest stable entry in oldest, its age in maxtime */
-      } else if (arp_table[i].ctime >= age_stable) {
-        old_stable = i;
-        age_stable = arp_table[i].ctime;
-      }
-    }
-  }
-  /* { we have no match } => try to create a new entry */
-   
-  /* no empty entry found and not allowed to recycle? */
-  if ((empty == ARP_TABLE_SIZE) && ((flags & ETHARP_TRY_HARD) == 0))
-  {
-  	return (s8_t)ERR_MEM;
-  }
-  
-  /* b) choose the least destructive entry to recycle:
-   * 1) empty entry
-   * 2) oldest stable entry
-   * 3) oldest pending entry without queued packets
-   * 4) oldest pending entry without queued packets
-   * 
-   * { ETHARP_TRY_HARD is set at this point }
-   */ 
-
-  /* 1) empty entry available? */
-  if (empty < ARP_TABLE_SIZE) {
-    i = empty;
-    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting empty entry %d\n", i));
-  }
-  /* 2) found recyclable stable entry? */
-  else if (old_stable < ARP_TABLE_SIZE) {
-    /* recycle oldest stable*/
-    i = old_stable;
-    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting oldest stable entry %d\n", i));
-#if ARP_QUEUEING
-    /* no queued packets should exist on stable entries */
-    LWIP_ASSERT("arp_table[i].p == NULL", arp_table[i].p == NULL);
-#endif
-  /* 3) found recyclable pending entry without queued packets? */
-  } else if (old_pending < ARP_TABLE_SIZE) {
-    /* recycle oldest pending */
-    i = old_pending;
-    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting oldest pending entry %d (without queue)\n", i));
-#if ARP_QUEUEING
-  /* 4) found recyclable pending entry with queued packets? */
-  } else if (old_queue < ARP_TABLE_SIZE) {
-    /* recycle oldest pending */
-    i = old_queue;
-    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting oldest pending entry %d, freeing packet queue %p\n", i, (void *)(arp_table[i].p)));
-    pbuf_free(arp_table[i].p);
-    arp_table[i].p = NULL;
-#endif
-    /* no empty or recyclable entries found */
-  } else {
-    return (s8_t)ERR_MEM;
-  }
-
-  /* { empty or recyclable entry found } */
-  LWIP_ASSERT("i < ARP_TABLE_SIZE", i < ARP_TABLE_SIZE);
-
-  /* recycle entry (no-op for an already empty entry) */
-  arp_table[i].state = ETHARP_STATE_EMPTY;
-
-  /* IP address given? */
-  if (ipaddr != NULL) {
-    /* set IP address */
-    ip_addr_set(&arp_table[i].ipaddr, ipaddr);
-  }
-  arp_table[i].ctime = 0;
-  return (err_t)i;
-}
-
-/**
- * Update (or insert) a IP/MAC address pair in the ARP cache.
- *
- * If a pending entry is resolved, any queued packets will be sent
- * at this point.
- * 
- * @param ipaddr IP address of the inserted ARP entry.
- * @param ethaddr Ethernet address of the inserted ARP entry.
- * @param flags Defines behaviour:
- * - ETHARP_TRY_HARD Allows ARP to insert this as a new item. If not specified,
- * only existing ARP entries will be updated.
- *
- * @return
- * - ERR_OK Succesfully updated ARP cache.
- * - ERR_MEM If we could not add a new ARP entry when ETHARP_TRY_HARD was set.
- * - ERR_ARG Non-unicast address given, those will not appear in ARP cache.
- *
- * @see pbuf_free()
- */
-static err_t
-update_arp_entry(struct netif *netif, struct ip_addr *ipaddr, struct eth_addr *ethaddr, u8_t flags)
-{
-  s8_t i, k;
-  LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 3, ("update_arp_entry()\n"));
-  LWIP_ASSERT("netif->hwaddr_len != 0", netif->hwaddr_len != 0);
-  LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: %u.%u.%u.%u - %02x:%02x:%02x:%02x:%02x:%02x\n",
-                                        ip4_addr1(ipaddr), ip4_addr2(ipaddr), ip4_addr3(ipaddr), ip4_addr4(ipaddr), 
-                                        ethaddr->addr[0], ethaddr->addr[1], ethaddr->addr[2],
-                                        ethaddr->addr[3], ethaddr->addr[4], ethaddr->addr[5]));
-  /* non-unicast address? */
-  if (ip_addr_isany(ipaddr) ||
-      ip_addr_isbroadcast(ipaddr, netif) ||
-      ip_addr_ismulticast(ipaddr)) {
-    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: will not add non-unicast IP address to ARP cache\n"));
-    return ERR_ARG;
-  }
-  /* find or create ARP entry */
-  i = find_entry(ipaddr, flags);
-  /* bail out if no entry could be found */
-  if (i < 0) return (err_t)i;
-  
-  /* mark it stable */
-  arp_table[i].state = ETHARP_STATE_STABLE;
-
-  LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: updating stable entry %u\n", i));
-  /* update address */
-  for (k = 0; k < netif->hwaddr_len; ++k) {
-    arp_table[i].ethaddr.addr[k] = ethaddr->addr[k];
-  }
-  /* reset time stamp */
-  arp_table[i].ctime = 0;
-/* this is where we will send out queued packets! */
-#if ARP_QUEUEING
-  while (arp_table[i].p != NULL) {
-    /* get the first packet on the queue */
-    struct pbuf *p = arp_table[i].p;
-    /* Ethernet header */
-    struct eth_hdr *ethhdr = p->payload;
-    /* remember (and reference) remainder of queue */
-    /* note: this will also terminate the p pbuf chain */
-    arp_table[i].p = pbuf_dequeue(p);
-    /* fill-in Ethernet header */
-    for (k = 0; k < netif->hwaddr_len; ++k) {
-      ethhdr->dest.addr[k] = ethaddr->addr[k];
-      ethhdr->src.addr[k] = netif->hwaddr[k];
-    }
-    ethhdr->type = htons(ETHTYPE_IP);
-    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: sending queued IP packet %p.\n", (void *)p));
-    /* send the queued IP packet */
-    netif->linkoutput(netif, p);
-    /* free the queued IP packet */
-    pbuf_free(p);
-  }
-#endif
-  return ERR_OK;
-}
-
-/**
- * Updates the ARP table using the given IP packet.
- *
- * Uses the incoming IP packet's source address to update the
- * ARP cache for the local network. The function does not alter
- * or free the packet. This function must be called before the
- * packet p is passed to the IP layer.
- *
- * @param netif The lwIP network interface on which the IP packet pbuf arrived.
- * @param pbuf The IP packet that arrived on netif.
- *
- * @return NULL
- *
- * @see pbuf_free()
- */
-void
-etharp_ip_input(struct netif *netif, struct pbuf *p)
-{
-  struct ethip_hdr *hdr;
-
-  /* Only insert an entry if the source IP address of the
-     incoming IP packet comes from a host on the local network. */
-  hdr = p->payload;
-  /* source is not on the local network? */
-  if (!ip_addr_netcmp(&(hdr->ip.src), &(netif->ip_addr), &(netif->netmask))) {
-    /* do nothing */
-    return;
-  }
-
-  LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_ip_input: updating ETHARP table.\n"));
-  /* update ARP table */
-  /* @todo We could use ETHARP_TRY_HARD if we think we are going to talk
-   * back soon (for example, if the destination IP address is ours. */
-  update_arp_entry(netif, &(hdr->ip.src), &(hdr->eth.src), 0);
-}
-
-
-/**
- * Responds to ARP requests to us. Upon ARP replies to us, add entry to cache  
- * send out queued IP packets. Updates cache with snooped address pairs.
- *
- * Should be called for incoming ARP packets. The pbuf in the argument
- * is freed by this function.
- *
- * @param netif The lwIP network interface on which the ARP packet pbuf arrived.
- * @param pbuf The ARP packet that arrived on netif. Is freed by this function.
- * @param ethaddr Ethernet address of netif.
- *
- * @return NULL
- *
- * @see pbuf_free()
- */
-void
-etharp_arp_input(struct netif *netif, struct eth_addr *ethaddr, struct pbuf *p)
-{
-  struct etharp_hdr *hdr;
-  /* these are aligned properly, whereas the ARP header fields might not be */
-  struct ip_addr sipaddr, dipaddr;
-  u8_t i;
-  u8_t for_us;
-
-  /* drop short ARP packets */
-  if (p->tot_len < sizeof(struct etharp_hdr)) {
-    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 1, ("etharp_arp_input: packet dropped, too short (%d/%d)\n", p->tot_len, sizeof(struct etharp_hdr)));
-    pbuf_free(p);
-    return;
-  }
-
-  hdr = p->payload;
- 
-  /* get aligned copies of addresses */
-  *(struct ip_addr2 *)&sipaddr = hdr->sipaddr;
-  *(struct ip_addr2 *)&dipaddr = hdr->dipaddr;
-
-  /* this interface is not configured? */
-  if (netif->ip_addr.addr == 0) {
-    for_us = 0;
-  } else {
-    /* ARP packet directed to us? */
-    for_us = ip_addr_cmp(&dipaddr, &(netif->ip_addr));
-  }
-
-  /* ARP message directed to us? */
-  if (for_us) {
-    /* add IP address in ARP cache; assume requester wants to talk to us.
-     * can result in directly sending the queued packets for this host. */
-    update_arp_entry(netif, &sipaddr, &(hdr->shwaddr), ETHARP_TRY_HARD);
-  /* ARP message not directed to us? */
-  } else {
-    /* update the source IP address in the cache, if present */
-    update_arp_entry(netif, &sipaddr, &(hdr->shwaddr), 0);
-  }
-
-  /* now act on the message itself */
-  switch (htons(hdr->opcode)) {
-  /* ARP request? */
-  case ARP_REQUEST:
-    /* ARP request. If it asked for our address, we send out a
-     * reply. In any case, we time-stamp any existing ARP entry,
-     * and possiby send out an IP packet that was queued on it. */
-
-    LWIP_DEBUGF (ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: incoming ARP request\n"));
-    /* ARP request for our address? */
-    if (for_us) {
-
-      LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: replying to ARP request for our IP address\n"));
-      /* re-use pbuf to send ARP reply */
-      hdr->opcode = htons(ARP_REPLY);
-
-      hdr->dipaddr = hdr->sipaddr;
-      hdr->sipaddr = *(struct ip_addr2 *)&netif->ip_addr;
-
-      for(i = 0; i < netif->hwaddr_len; ++i) {
-        hdr->dhwaddr.addr[i] = hdr->shwaddr.addr[i];
-        hdr->shwaddr.addr[i] = ethaddr->addr[i];
-        hdr->ethhdr.dest.addr[i] = hdr->dhwaddr.addr[i];
-        hdr->ethhdr.src.addr[i] = ethaddr->addr[i];
-      }
-
-      hdr->hwtype = htons(HWTYPE_ETHERNET);
-      ARPH_HWLEN_SET(hdr, netif->hwaddr_len);
-
-      hdr->proto = htons(ETHTYPE_IP);
-      ARPH_PROTOLEN_SET(hdr, sizeof(struct ip_addr));
-
-      hdr->ethhdr.type = htons(ETHTYPE_ARP);
-      /* return ARP reply */
-      netif->linkoutput(netif, p);
-    /* we are not configured? */
-    } else if (netif->ip_addr.addr == 0) {
-      /* { for_us == 0 and netif->ip_addr.addr == 0 } */
-      LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: we are unconfigured, ARP request ignored.\n"));
-    /* request was not directed to us */
-    } else {
-      /* { for_us == 0 and netif->ip_addr.addr != 0 } */
-      LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: ARP request was not for us.\n"));
-    }
-    break;
-  case ARP_REPLY:
-    /* ARP reply. We already updated the ARP cache earlier. */
-    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: incoming ARP reply\n"));
-#if (LWIP_DHCP && DHCP_DOES_ARP_CHECK)
-    /* When unconfigured, DHCP wants to know about ARP replies from the
-     * address offered to us, as that means someone else uses it already! */
-    if (netif->ip_addr.addr == 0) dhcp_arp_reply(netif, &sipaddr);
-#endif
-    break;
-  default:
-    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: ARP unknown opcode type %d\n", htons(hdr->opcode)));
-    break;
-  }
-  /* free ARP packet */
-  pbuf_free(p);
-}
-
-/**
- * Resolve and fill-in Ethernet address header for outgoing packet.
- *
- * For IP multicast and broadcast, corresponding Ethernet addresses
- * are selected and the packet is transmitted on the link.
- *
- * For unicast addresses, the packet is submitted to etharp_query(). In
- * case the IP address is outside the local network, the IP address of
- * the gateway is used.
- *
- * @param netif The lwIP network interface which the IP packet will be sent on.
- * @param ipaddr The IP address of the packet destination.
- * @param pbuf The pbuf(s) containing the IP packet to be sent.
- *
- * @return
- * - ERR_RTE No route to destination (no gateway to external networks),
- * or the return type of either etharp_query() or netif->linkoutput().
- */
-err_t
-etharp_output(struct netif *netif, struct ip_addr *ipaddr, struct pbuf *q)
-{
-  struct eth_addr *dest, *srcaddr, mcastaddr;
-  struct eth_hdr *ethhdr;
-  u8_t i;
-
-  /* make room for Ethernet header - should not fail */
-  if (pbuf_header(q, sizeof(struct eth_hdr)) != 0) {
-    /* bail out */
-    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 2, ("etharp_output: could not allocate room for header.\n"));
-    LINK_STATS_INC(link.lenerr);
-    return ERR_BUF;
-  }
-
-  /* assume unresolved Ethernet address */
-  dest = NULL;
-  /* Determine on destination hardware address. Broadcasts and multicasts
-   * are special, other IP addresses are looked up in the ARP table. */
-
-  /* broadcast destination IP address? */
-  if (ip_addr_isbroadcast(ipaddr, netif)) {
-    /* broadcast on Ethernet also */
-    dest = (struct eth_addr *)ðbroadcast;
-  /* multicast destination IP address? */
-  } else if (ip_addr_ismulticast(ipaddr)) {
-    /* Hash IP multicast address to MAC address.*/
-    mcastaddr.addr[0] = 0x01;
-    mcastaddr.addr[1] = 0x00;
-    mcastaddr.addr[2] = 0x5e;
-    mcastaddr.addr[3] = ip4_addr2(ipaddr) & 0x7f;
-    mcastaddr.addr[4] = ip4_addr3(ipaddr);
-    mcastaddr.addr[5] = ip4_addr4(ipaddr);
-    /* destination Ethernet address is multicast */
-    dest = &mcastaddr;
-  /* unicast destination IP address? */
-  } else {
-    /* outside local network? */
-    if (!ip_addr_netcmp(ipaddr, &(netif->ip_addr), &(netif->netmask))) {
-      /* interface has default gateway? */
-      if (netif->gw.addr != 0) {
-        /* send to hardware address of default gateway IP address */
-        ipaddr = &(netif->gw);
-      /* no default gateway available */
-      } else {
-        /* no route to destination error (default gateway missing) */
-        return ERR_RTE;
-      }
-    }
-    /* queue on destination Ethernet address belonging to ipaddr */
-    return etharp_query(netif, ipaddr, q);
-  }
-
-  /* continuation for multicast/broadcast destinations */
-  /* obtain source Ethernet address of the given interface */
-  srcaddr = (struct eth_addr *)netif->hwaddr;
-  ethhdr = q->payload;
-  for (i = 0; i < netif->hwaddr_len; i++) {
-    ethhdr->dest.addr[i] = dest->addr[i];
-    ethhdr->src.addr[i] = srcaddr->addr[i];
-  }
-  ethhdr->type = htons(ETHTYPE_IP);
-  /* send packet directly on the link */
-  return netif->linkoutput(netif, q);
-}
-
-/**
- * Send an ARP request for the given IP address and/or queue a packet.
- *
- * If the IP address was not yet in the cache, a pending ARP cache entry
- * is added and an ARP request is sent for the given address. The packet
- * is queued on this entry.
- *
- * If the IP address was already pending in the cache, a new ARP request
- * is sent for the given address. The packet is queued on this entry.
- *
- * If the IP address was already stable in the cache, and a packet is
- * given, it is directly sent and no ARP request is sent out. 
- * 
- * If the IP address was already stable in the cache, and no packet is
- * given, an ARP request is sent out.
- * 
- * @param netif The lwIP network interface on which ipaddr
- * must be queried for.
- * @param ipaddr The IP address to be resolved.
- * @param q If non-NULL, a pbuf that must be delivered to the IP address.
- * q is not freed by this function.
- *
- * @return
- * - ERR_BUF Could not make room for Ethernet header.
- * - ERR_MEM Hardware address unknown, and no more ARP entries available
- *   to query for address or queue the packet.
- * - ERR_MEM Could not queue packet due to memory shortage.
- * - ERR_RTE No route to destination (no gateway to external networks).
- * - ERR_ARG Non-unicast address given, those will not appear in ARP cache.
- *
- */
-err_t etharp_query(struct netif *netif, struct ip_addr *ipaddr, struct pbuf *q)
-{
-  struct pbuf *p;
-  struct eth_addr * srcaddr = (struct eth_addr *)netif->hwaddr;
-  err_t result = ERR_MEM;
-  s8_t i; /* ARP entry index */
-  u8_t k; /* Ethernet address octet index */
-
-  /* non-unicast address? */
-  if (ip_addr_isbroadcast(ipaddr, netif) ||
-      ip_addr_ismulticast(ipaddr) ||
-      ip_addr_isany(ipaddr)) {
-    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: will not add non-unicast IP address to ARP cache\n"));
-    return ERR_ARG;
-  }
-
-  /* find entry in ARP cache, ask to create entry if queueing packet */
-  i = find_entry(ipaddr, ETHARP_TRY_HARD);
-
-  /* could not find or create entry? */
-  if (i < 0)
-  {
-    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: could not create ARP entry\n"));
-	#ifdef LWIP_DEBUG
-    if (q) LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: packet dropped\n"));
-	#endif
-    return (err_t)i;
-  }
-
-  /* mark a fresh entry as pending (we just sent a request) */
-  if (arp_table[i].state == ETHARP_STATE_EMPTY) {
-    arp_table[i].state = ETHARP_STATE_PENDING;
-  }
-
-  /* { i is either a STABLE or (new or existing) PENDING entry } */
-  LWIP_ASSERT("arp_table[i].state == PENDING or STABLE",
-  ((arp_table[i].state == ETHARP_STATE_PENDING) ||
-   (arp_table[i].state == ETHARP_STATE_STABLE)));
-
-  /* do we have a pending entry? or an implicit query request? */
-  if ((arp_table[i].state == ETHARP_STATE_PENDING) || (q == NULL)) {
-    /* try to resolve it; send out ARP request */
-    result = etharp_request(netif, ipaddr);
-  }
-  
-  /* packet given? */
-  if (q != NULL) {
-    /* stable entry? */
-    if (arp_table[i].state == ETHARP_STATE_STABLE) {
-      /* we have a valid IP->Ethernet address mapping,
-       * fill in the Ethernet header for the outgoing packet */
-      struct eth_hdr *ethhdr = q->payload;
-      for(k = 0; k < netif->hwaddr_len; k++) {
-        ethhdr->dest.addr[k] = arp_table[i].ethaddr.addr[k];
-        ethhdr->src.addr[k]  = srcaddr->addr[k];
-      }
-      ethhdr->type = htons(ETHTYPE_IP);
-      LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: sending packet %p\n", (void *)q));
-      /* send the packet */
-      result = netif->linkoutput(netif, q);
-    /* pending entry? (either just created or already pending */
-    } else if (arp_table[i].state == ETHARP_STATE_PENDING) {
-#if ARP_QUEUEING /* queue the given q packet */
-      /* copy any PBUF_REF referenced payloads into PBUF_RAM */
-      /* (the caller of lwIP assumes the referenced payload can be
-       * freed after it returns from the lwIP call that brought us here) */
-      p = pbuf_take(q);
-      /* packet could be taken over? */
-      if (p != NULL) {
-        /* queue packet ... */
-        if (arp_table[i].p == NULL) {
-        	/* ... in the empty queue */
-        	pbuf_ref(p);
-        	arp_table[i].p = p;
-#if 0 /* multi-packet-queueing disabled, see bug #11400 */
-        } else {
-        	/* ... at tail of non-empty queue */
-          pbuf_queue(arp_table[i].p, p);
-#endif
-        }
-        LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: queued packet %p on ARP entry %d\n", (void *)q, i));
-        result = ERR_OK;
-      } else {
-        LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q));
-        /* { result == ERR_MEM } through initialization */
-      }
-#else /* ARP_QUEUEING == 0 */
-      /* q && state == PENDING && ARP_QUEUEING == 0 => result = ERR_MEM */
-      /* { result == ERR_MEM } through initialization */
-      LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: Ethernet destination address unknown, queueing disabled, packet %p dropped\n", (void *)q));
-#endif
-    }
-  }
-  return result;
-}
-
-err_t etharp_request(struct netif *netif, struct ip_addr *ipaddr)
-{
-  struct pbuf *p;
-  struct eth_addr * srcaddr = (struct eth_addr *)netif->hwaddr;
-  err_t result = ERR_OK;
-  u8_t k; /* ARP entry index */
-
-  /* allocate a pbuf for the outgoing ARP request packet */
-  p = pbuf_alloc(PBUF_LINK, sizeof(struct etharp_hdr), PBUF_RAM);
-  /* could allocate a pbuf for an ARP request? */
-  if (p != NULL) {
-    struct etharp_hdr *hdr = p->payload;
-    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_request: sending ARP request.\n"));
-    hdr->opcode = htons(ARP_REQUEST);
-    for (k = 0; k < netif->hwaddr_len; k++)
-    {
-      hdr->shwaddr.addr[k] = srcaddr->addr[k];
-      /* the hardware address is what we ask for, in
-       * a request it is a don't-care value, we use zeroes */
-      hdr->dhwaddr.addr[k] = 0x00;
-    }
-    hdr->dipaddr = *(struct ip_addr2 *)ipaddr;
-    hdr->sipaddr = *(struct ip_addr2 *)&netif->ip_addr;
-
-    hdr->hwtype = htons(HWTYPE_ETHERNET);
-    ARPH_HWLEN_SET(hdr, netif->hwaddr_len);
-
-    hdr->proto = htons(ETHTYPE_IP);
-    ARPH_PROTOLEN_SET(hdr, sizeof(struct ip_addr));
-    for (k = 0; k < netif->hwaddr_len; ++k)
-    {
-      /* broadcast to all network interfaces on the local network */
-      hdr->ethhdr.dest.addr[k] = 0xff;
-      hdr->ethhdr.src.addr[k] = srcaddr->addr[k];
-    }
-    hdr->ethhdr.type = htons(ETHTYPE_ARP);
-    /* send ARP query */
-    result = netif->linkoutput(netif, p);
-    /* free ARP query packet */
-    pbuf_free(p);
-    p = NULL;
-  /* could not allocate pbuf for ARP request */
-  } else {
-    result = ERR_MEM;
-    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 2, ("etharp_request: could not allocate pbuf for ARP request.\n"));
-  }
-  return result;
-}
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ethernetif.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ethernetif.c
deleted file mode 100644
index 7d4719ec9..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ethernetif.c
+++ /dev/null
@@ -1,354 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels 
- *
- */
-
-/* lwIP includes. */
-#include 
-#include "lwip/opt.h"
-#include "lwip/def.h"
-#include "lwip/mem.h"
-#include "lwip/pbuf.h"
-#include "lwip/sys.h"
-#include 
-#include "netif/etharp.h"
-
-/* FreeRTOS includes. */
-#include "FreeRTOS.h"
-#include "SAM7_EMAC.h"
-#include "Emac.h"
-
-#define netifMTU							( 1500 )
-#define netifINTERFACE_TASK_STACK_SIZE		( 350 )
-#define netifINTERFACE_TASK_PRIORITY		( configMAX_PRIORITIES - 1 )
-#define netifGUARD_BLOCK_TIME				( 250 )
-#define IFNAME0 'e'
-#define IFNAME1 'm'
-
-/* lwIP definitions. */
-struct ethernetif
-{
-	struct eth_addr *ethaddr;
-};
-static const struct eth_addr    ethbroadcast = { { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff } };
-static struct netif *xNetIf = NULL;
-
-/* Forward declarations. */
-static void ethernetif_input( void * );
-static err_t ethernetif_output( struct netif *netif, struct pbuf *p, struct ip_addr *ipaddr );
-err_t ethernetif_init( struct netif *netif );
-
-
-/*-----------------------------------------------------------*/
-
-static void low_level_init( struct netif *netif )
-{
-unsigned portBASE_TYPE uxPriority;
-
-	/* set MAC hardware address length */
-	netif->hwaddr_len = 6;
-
-	/* set MAC hardware address */
-	netif->hwaddr[0] = emacETHADDR0;
-	netif->hwaddr[1] = emacETHADDR1;
-	netif->hwaddr[2] = emacETHADDR2;
-	netif->hwaddr[3] = emacETHADDR3;
-	netif->hwaddr[4] = emacETHADDR4;
-	netif->hwaddr[5] = emacETHADDR5;
-
-	/* maximum transfer unit */
-	netif->mtu = netifMTU;
-
-	/* broadcast capability */
-	netif->flags = NETIF_FLAG_BROADCAST;
-
-	xNetIf = netif;
-
-	/* Initialise the EMAC.  This routine contains code that polls status bits.  
-	If the Ethernet cable is not plugged in then this can take a considerable 
-	time.  To prevent this starving lower priority tasks of processing time we
-	lower our priority prior to the call, then raise it back again once the
-	initialisation is complete. */
-	uxPriority = uxTaskPriorityGet( NULL );
-	vTaskPrioritySet( NULL, tskIDLE_PRIORITY );
-	while( xEMACInit() == NULL )
-	{
-		__asm( "NOP" );
-	}
-	vTaskPrioritySet( NULL, uxPriority );
-
-	/* Create the task that handles the EMAC. */
-	xTaskCreate( ethernetif_input, ( signed portCHAR * ) "ETH_INT", netifINTERFACE_TASK_STACK_SIZE, NULL, netifINTERFACE_TASK_PRIORITY, NULL );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * low_level_output(): Should do the actual transmission of the packet. The 
- * packet is contained in the pbuf that is passed to the function. This pbuf 
- * might be chained.
- */
-static err_t low_level_output( struct netif *netif, struct pbuf *p )
-{
-struct pbuf *q;
-static xSemaphoreHandle xTxSemaphore = NULL;
-err_t xReturn = ERR_OK;
-
-	/* Parameter not used. */
-	( void ) netif;
-
-	if( xTxSemaphore == NULL )
-	{
-		vSemaphoreCreateBinary( xTxSemaphore );
-	}
-
-	#if ETH_PAD_SIZE
-		pbuf_header( p, -ETH_PAD_SIZE );    /* drop the padding word */
-	#endif
-
-	/* Access to the EMAC is guarded using a semaphore. */
-	if( xSemaphoreTake( xTxSemaphore, netifGUARD_BLOCK_TIME ) )
-	{
-		for( q = p; q != NULL; q = q->next )
-		{
-			/* Send the data from the pbuf to the interface, one pbuf at a 
-			time. The size of the data in each pbuf is kept in the ->len 
-			variable.  if q->next == NULL then this is the last pbuf in the
-			chain. */
-			if( !lEMACSend( q->payload, q->len, ( q->next == NULL ) ) )
-			{
-				xReturn = ~ERR_OK;
-			}
-		}
-
-        xSemaphoreGive( xTxSemaphore );
-	}
-	
-
-	#if ETH_PAD_SIZE
-		pbuf_header( p, ETH_PAD_SIZE );     /* reclaim the padding word */
-	#endif
-
-	#if LINK_STATS
-		lwip_stats.link.xmit++;
-	#endif /* LINK_STATS */
-
-    return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-/*
- * low_level_input(): Should allocate a pbuf and transfer the bytes of the 
- * incoming packet from the interface into the pbuf. 
- */
-static struct pbuf *low_level_input( struct netif *netif )
-{
-struct pbuf         *p = NULL, *q;
-u16_t               len = 0;
-static xSemaphoreHandle xRxSemaphore = NULL;
-
-	/* Parameter not used. */
-	( void ) netif;
-
-	if( xRxSemaphore == NULL )
-	{
-		vSemaphoreCreateBinary( xRxSemaphore );
-	}
-
-	/* Access to the emac is guarded using a semaphore. */
-   	if( xSemaphoreTake( xRxSemaphore, netifGUARD_BLOCK_TIME ) )
-	{
-		/* Obtain the size of the packet. */
-		len = ulEMACInputLength();
-	
-		if( len )
-		{
-			#if ETH_PAD_SIZE
-				len += ETH_PAD_SIZE;    /* allow room for Ethernet padding */
-			#endif
-	
-			/* We allocate a pbuf chain of pbufs from the pool. */
-			p = pbuf_alloc( PBUF_RAW, len, PBUF_POOL );
-		
-			if( p != NULL )
-			{
-				#if ETH_PAD_SIZE
-					pbuf_header( p, -ETH_PAD_SIZE );    /* drop the padding word */
-				#endif
-		
-				/* Let the driver know we are going to read a new packet. */
-				vEMACRead( NULL, 0, len );
-					
-				/* We iterate over the pbuf chain until we have read the entire
-				packet into the pbuf. */				
-				for( q = p; q != NULL; q = q->next )
-				{
-					/* Read enough bytes to fill this pbuf in the chain. The 
-					available data in the pbuf is given by the q->len variable. */
-					vEMACRead( q->payload, q->len, len );
-				}
-		
-				#if ETH_PAD_SIZE
-					pbuf_header( p, ETH_PAD_SIZE );     /* reclaim the padding word */
-				#endif
-				#if LINK_STATS
-					lwip_stats.link.recv++;
-				#endif /* LINK_STATS */
-			}
-			else
-			{
-				#if LINK_STATS
-					lwip_stats.link.memerr++;
-					lwip_stats.link.drop++;
-				#endif /* LINK_STATS */
-			}
-		}
-
-		xSemaphoreGive( xRxSemaphore );
-	}
-
-	return p;
-}
-/*-----------------------------------------------------------*/
-
-/*
- * ethernetif_output(): This function is called by the TCP/IP stack when an 
- * IP packet should be sent. It calls the function called low_level_output() 
- * to do the actual transmission of the packet.
- */
-static err_t ethernetif_output( struct netif *netif, struct pbuf *p, struct ip_addr *ipaddr )
-{
-    /* resolve hardware address, then send (or queue) packet */
-    return etharp_output( netif, ipaddr, p );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * ethernetif_input(): This function should be called when a packet is ready to 
- * be read from the interface. It uses the function low_level_input() that 
- * should handle the actual reception of bytes from the network interface.
- */
-static void ethernetif_input( void * pvParameters )
-{
-struct ethernetif   *ethernetif;
-struct eth_hdr      *ethhdr;
-struct pbuf         *p;
-
-	( void ) pvParameters;
-
-	for( ;; )
-	{
-		do
-		{
-			ethernetif = xNetIf->state;
-
-			/* move received packet into a new pbuf */
-			p = low_level_input( xNetIf );
-
-			if( p == NULL )
-			{
-				/* No packet could be read.  Wait a for an interrupt to tell us 
-				there is more data available. */
-				vEMACWaitForInput();
-			}
-
-		} while( p == NULL );
-	
-		/* points to packet payload, which starts with an Ethernet header */
-		ethhdr = p->payload;
-	
-		#if LINK_STATS
-			lwip_stats.link.recv++;
-		#endif /* LINK_STATS */
-	
-		ethhdr = p->payload;
-	
-		switch( htons( ethhdr->type ) )
-		{
-			/* IP packet? */
-			case ETHTYPE_IP:
-				/* update ARP table */
-				etharp_ip_input( xNetIf, p );
-		
-				/* skip Ethernet header */
-				pbuf_header( p, (s16_t)-sizeof(struct eth_hdr) );
-		
-				/* pass to network layer */
-				xNetIf->input( p, xNetIf );
-				break;
-		
-			case ETHTYPE_ARP:
-				/* pass p to ARP module */
-				etharp_arp_input( xNetIf, ethernetif->ethaddr, p );
-				break;
-		
-			default:
-				pbuf_free( p );
-				p = NULL;
-				break;
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-static void arp_timer( void *arg )
-{
-	( void ) arg;
-
-    etharp_tmr();
-    sys_timeout( ARP_TMR_INTERVAL, arp_timer, NULL );
-}
-/*-----------------------------------------------------------*/
-
-err_t ethernetif_init( struct netif *netif )
-{
-struct ethernetif   *ethernetif;
-
-	ethernetif = mem_malloc( sizeof(struct ethernetif) );
-
-	if( ethernetif == NULL )
-	{
-		LWIP_DEBUGF( NETIF_DEBUG, ("ethernetif_init: out of memory\n") );
-		return ERR_MEM;
-	}
-
-	netif->state = ethernetif;
-	netif->name[0] = IFNAME0;
-	netif->name[1] = IFNAME1;
-	netif->output = ethernetif_output;
-	netif->linkoutput = low_level_output;
-
-	ethernetif->ethaddr = ( struct eth_addr * ) &( netif->hwaddr[0] );
-
-	low_level_init( netif );
-	etharp_init();
-	sys_timeout( ARP_TMR_INTERVAL, arp_timer, NULL );
-
-	return ERR_OK;
-}
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/loopif.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/loopif.c
deleted file mode 100644
index f5bcc07cf..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/loopif.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#include "lwip/opt.h"
-
-#if LWIP_HAVE_LOOPIF
-
-#include "netif/loopif.h"
-#include "lwip/mem.h"
-
-#if defined(LWIP_DEBUG) && defined(LWIP_TCPDUMP)
-#include "netif/tcpdump.h"
-#endif /* LWIP_DEBUG && LWIP_TCPDUMP */
-
-#include "lwip/tcp.h"
-#include "lwip/ip.h"
-
-static void
-loopif_input( void * arg )
-{
-	struct netif *netif = (struct netif *)( ((void **)arg)[ 0 ] );
-	struct pbuf *r = (struct pbuf *)( ((void **)arg)[ 1 ] );
-
-	mem_free( arg );
-	netif -> input( r, netif );
-}
-
-static err_t
-loopif_output(struct netif *netif, struct pbuf *p,
-       struct ip_addr *ipaddr)
-{
-  struct pbuf *q, *r;
-  char *ptr;
-  void **arg;
-
-#if defined(LWIP_DEBUG) && defined(LWIP_TCPDUMP)
-  tcpdump(p);
-#endif /* LWIP_DEBUG && LWIP_TCPDUMP */
-  
-  r = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM);
-  if (r != NULL) {
-    ptr = r->payload;
-    
-    for(q = p; q != NULL; q = q->next) {
-      memcpy(ptr, q->payload, q->len);
-      ptr += q->len;
-    }
-
-    arg = mem_malloc( sizeof( void *[2]));
-	if( NULL == arg ) {
-		return ERR_MEM;
-	}
-	
-	arg[0] = netif;
-	arg[1] = r;
-	/**
-	 * workaround (patch #1779) to try to prevent bug #2595:
-	 * When connecting to "localhost" with the loopif interface,
-	 * tcp_output doesn't get the opportunity to finnish sending the
-	 * segment before tcp_process gets it, resulting in tcp_process
-	 * referencing pcb->unacked-> which still is NULL.
-	 * 
-	 * TODO: Is there still a race condition here? Leon
-	 */
-	sys_timeout( 1, loopif_input, arg );
-	
-    return ERR_OK;    
-  }
-  return ERR_MEM;
-}
-
-err_t
-loopif_init(struct netif *netif)
-{
-  netif->name[0] = 'l';
-  netif->name[1] = 'o';
-#if 0 /** TODO: I think this should be enabled, or not? Leon */
-  netif->input = loopif_input;
-#endif
-  netif->output = loopif_output;
-  return ERR_OK;
-}
-
-#endif /* LWIP_HAVE_LOOPIF */
-
-
-
-
-
-
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/auth.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/auth.c
deleted file mode 100644
index 333496402..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/auth.c
+++ /dev/null
@@ -1,927 +0,0 @@
-/*****************************************************************************
-* auth.c - Network Authentication and Phase Control program file.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* Copyright (c) 1997 by Global Election Systems Inc.  All rights reserved.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY
-*
-* 03-01-01 Marc Boucher 
-*   Ported to lwIP.
-* 97-12-08 Guy Lancaster , Global Election Systems Inc.
-*   Ported from public pppd code.
-*****************************************************************************/
-/*
- * auth.c - PPP authentication and phase control.
- *
- * Copyright (c) 1993 The Australian National University.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by the Australian National University.  The name of the University
- * may not be used to endorse or promote products derived from this
- * software without specific prior written permission.
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- *
- * Copyright (c) 1989 Carnegie Mellon University.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by Carnegie Mellon University.  The name of the
- * University may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- */
-
-#include "ppp.h"
-#if PPP_SUPPORT > 0
-#include "fsm.h"
-#include "lcp.h"
-#include "pap.h"
-#include "chap.h"
-#include "auth.h"
-#include "ipcp.h"
-
-#if CBCP_SUPPORT > 0
-#include "cbcp.h"
-#endif
-
-#include "pppdebug.h"
-
-
-/*************************/
-/*** LOCAL DEFINITIONS ***/
-/*************************/
-
-/* Bits in auth_pending[] */
-#define PAP_WITHPEER    1
-#define PAP_PEER    2
-#define CHAP_WITHPEER   4
-#define CHAP_PEER   8
-
-
-                                                                    
-/************************/
-/*** LOCAL DATA TYPES ***/
-/************************/
-/* Used for storing a sequence of words.  Usually malloced. */
-struct wordlist {
-    struct wordlist *next;
-    char        word[1];
-};
-
-
-
-/***********************************/
-/*** LOCAL FUNCTION DECLARATIONS ***/
-/***********************************/
-extern char *crypt (const char *, const char *);
-
-/* Prototypes for procedures local to this file. */
-
-static void network_phase (int);
-static void check_idle (void *);
-static void connect_time_expired (void *);
-#if 0
-static int  login (char *, char *, char **, int *);
-#endif
-static void logout (void);
-static int  null_login (int);
-static int  get_pap_passwd (int, char *, char *);
-static int  have_pap_secret (void);
-static int  have_chap_secret (char *, char *, u32_t);
-static int  ip_addr_check (u32_t, struct wordlist *);
-#if 0 /* PAP_SUPPORT > 0 || CHAP_SUPPORT > 0 */
-static void set_allowed_addrs(int unit, struct wordlist *addrs);
-static void free_wordlist (struct wordlist *);
-#endif
-#if CBCP_SUPPORT > 0
-static void callback_phase (int);
-#endif
-
-
-/******************************/
-/*** PUBLIC DATA STRUCTURES ***/
-/******************************/
-
-
-/*****************************/
-/*** LOCAL DATA STRUCTURES ***/
-/*****************************/
-#if PAP_SUPPORT > 0 || CHAP_SUPPORT > 0
-/* The name by which the peer authenticated itself to us. */
-static char peer_authname[MAXNAMELEN];
-#endif
-
-/* Records which authentication operations haven't completed yet. */
-static int auth_pending[NUM_PPP];
-
-/* Set if we have successfully called login() */
-static int logged_in;
-
-/* Set if we have run the /etc/ppp/auth-up script. */
-static int did_authup;
-
-/* List of addresses which the peer may use. */
-static struct wordlist *addresses[NUM_PPP];
-
-/* Number of network protocols which we have opened. */
-static int num_np_open;
-
-/* Number of network protocols which have come up. */
-static int num_np_up;
-
-#if PAP_SUPPORT > 0 || CHAP_SUPPORT > 0
-/* Set if we got the contents of passwd[] from the pap-secrets file. */
-static int passwd_from_file;
-#endif
-
-
-
-/***********************************/
-/*** PUBLIC FUNCTION DEFINITIONS ***/
-/***********************************/
-/*
- * An Open on LCP has requested a change from Dead to Establish phase.
- * Do what's necessary to bring the physical layer up.
- */
-void link_required(int unit)
-{
-    AUTHDEBUG((LOG_INFO, "link_required: %d\n", unit));
-}
-
-/*
- * LCP has terminated the link; go to the Dead phase and take the
- * physical layer down.
- */
-void link_terminated(int unit)
-{
-    AUTHDEBUG((LOG_INFO, "link_terminated: %d\n", unit));
-    
-    if (lcp_phase[unit] == PHASE_DEAD)
-        return;
-    if (logged_in)
-        logout();
-    lcp_phase[unit] = PHASE_DEAD;
-    AUTHDEBUG((LOG_NOTICE, "Connection terminated.\n"));
-	pppMainWakeup(unit);
-}
-
-/*
- * LCP has gone down; it will either die or try to re-establish.
- */
-void link_down(int unit)
-{
-    int i;
-    struct protent *protp;
-    
-    AUTHDEBUG((LOG_INFO, "link_down: %d\n", unit));
-    if (did_authup) {
-        /* XXX Do link down processing. */
-        did_authup = 0;
-    }
-    for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) {
-        if (!protp->enabled_flag)
-            continue;
-        if (protp->protocol != PPP_LCP && protp->lowerdown != NULL)
-            (*protp->lowerdown)(unit);
-        if (protp->protocol < 0xC000 && protp->close != NULL)
-            (*protp->close)(unit, "LCP down");
-    }
-    num_np_open = 0;
-    num_np_up = 0;
-    if (lcp_phase[unit] != PHASE_DEAD)
-        lcp_phase[unit] = PHASE_TERMINATE;
-	pppMainWakeup(unit);
-}
-
-/*
- * The link is established.
- * Proceed to the Dead, Authenticate or Network phase as appropriate.
- */
-void link_established(int unit)
-{
-    int auth;
-    int i;
-    struct protent *protp;
-    lcp_options *wo = &lcp_wantoptions[unit];
-    lcp_options *go = &lcp_gotoptions[unit];
-#if PAP_SUPPORT > 0 || CHAP_SUPPORT > 0
-    lcp_options *ho = &lcp_hisoptions[unit];
-#endif
-    
-    AUTHDEBUG((LOG_INFO, "link_established: %d\n", unit));
-    /*
-     * Tell higher-level protocols that LCP is up.
-     */
-    for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i)
-        if (protp->protocol != PPP_LCP && protp->enabled_flag
-                && protp->lowerup != NULL)
-            (*protp->lowerup)(unit);
-    
-    if (ppp_settings.auth_required && !(go->neg_chap || go->neg_upap)) {
-        /*
-         * We wanted the peer to authenticate itself, and it refused:
-         * treat it as though it authenticated with PAP using a username
-         * of "" and a password of "".  If that's not OK, boot it out.
-         */
-        if (!wo->neg_upap || !null_login(unit)) {
-            AUTHDEBUG((LOG_WARNING, "peer refused to authenticate\n"));
-            lcp_close(unit, "peer refused to authenticate");
-            return;
-        }
-    }
-    
-    lcp_phase[unit] = PHASE_AUTHENTICATE;
-    auth = 0;
-#if CHAP_SUPPORT > 0
-    if (go->neg_chap) {
-        ChapAuthPeer(unit, ppp_settings.our_name, go->chap_mdtype);
-        auth |= CHAP_PEER;
-    } 
-#endif
-#if PAP_SUPPORT > 0 && CHAP_SUPPORT > 0
-    else
-#endif
-#if PAP_SUPPORT > 0
-    if (go->neg_upap) {
-        upap_authpeer(unit);
-        auth |= PAP_PEER;
-    }
-#endif
-#if CHAP_SUPPORT > 0
-    if (ho->neg_chap) {
-        ChapAuthWithPeer(unit, ppp_settings.user, ho->chap_mdtype);
-        auth |= CHAP_WITHPEER;
-    }
-#endif
-#if PAP_SUPPORT > 0 && CHAP_SUPPORT > 0
-    else
-#endif
-#if PAP_SUPPORT > 0
-    if (ho->neg_upap) {
-        if (ppp_settings.passwd[0] == 0) {
-            passwd_from_file = 1;
-            if (!get_pap_passwd(unit, ppp_settings.user, ppp_settings.passwd))
-                AUTHDEBUG((LOG_ERR, "No secret found for PAP login\n"));
-        }
-        upap_authwithpeer(unit, ppp_settings.user, ppp_settings.passwd);
-        auth |= PAP_WITHPEER;
-    }
-#endif
-    auth_pending[unit] = auth;
-    
-    if (!auth)
-        network_phase(unit);
-}
-
-
-/*
- * The peer has failed to authenticate himself using `protocol'.
- */
-void auth_peer_fail(int unit, u16_t protocol)
-{
-    AUTHDEBUG((LOG_INFO, "auth_peer_fail: %d proto=%X\n", unit, protocol));
-    /*
-     * Authentication failure: take the link down
-     */
-    lcp_close(unit, "Authentication failed");
-}
-
-
-#if PAP_SUPPORT > 0 || CHAP_SUPPORT > 0
-/*
- * The peer has been successfully authenticated using `protocol'.
- */
-void auth_peer_success(int unit, u16_t protocol, char *name, int namelen)
-{
-    int pbit;
-    
-    AUTHDEBUG((LOG_INFO, "auth_peer_success: %d proto=%X\n", unit, protocol));
-    switch (protocol) {
-    case PPP_CHAP:
-        pbit = CHAP_PEER;
-        break;
-    case PPP_PAP:
-        pbit = PAP_PEER;
-        break;
-    default:
-        AUTHDEBUG((LOG_WARNING, "auth_peer_success: unknown protocol %x\n",
-               protocol));
-        return;
-    }
-    
-    /*
-     * Save the authenticated name of the peer for later.
-     */
-    if (namelen > sizeof(peer_authname) - 1)
-        namelen = sizeof(peer_authname) - 1;
-    BCOPY(name, peer_authname, namelen);
-    peer_authname[namelen] = 0;
-    
-    /*
-     * If there is no more authentication still to be done,
-     * proceed to the network (or callback) phase.
-     */
-    if ((auth_pending[unit] &= ~pbit) == 0)
-        network_phase(unit);
-}
-
-/*
- * We have failed to authenticate ourselves to the peer using `protocol'.
- */
-void auth_withpeer_fail(int unit, u16_t protocol)
-{
-    int errCode = PPPERR_AUTHFAIL;
-    
-    AUTHDEBUG((LOG_INFO, "auth_withpeer_fail: %d proto=%X\n", unit, protocol));
-    if (passwd_from_file)
-        BZERO(ppp_settings.passwd, MAXSECRETLEN);
-    /* 
-     * XXX Warning: the unit number indicates the interface which is
-     * not necessarily the PPP connection.  It works here as long
-     * as we are only supporting PPP interfaces.
-     */
-    pppIOCtl(unit, PPPCTLS_ERRCODE, &errCode);
-
-    /*
-     * We've failed to authenticate ourselves to our peer.
-     * He'll probably take the link down, and there's not much
-     * we can do except wait for that.
-     */
-}
-
-/*
- * We have successfully authenticated ourselves with the peer using `protocol'.
- */
-void auth_withpeer_success(int unit, u16_t protocol)
-{
-    int pbit;
-    
-    AUTHDEBUG((LOG_INFO, "auth_withpeer_success: %d proto=%X\n", unit, protocol));
-    switch (protocol) {
-    case PPP_CHAP:
-        pbit = CHAP_WITHPEER;
-        break;
-    case PPP_PAP:
-        if (passwd_from_file)
-            BZERO(ppp_settings.passwd, MAXSECRETLEN);
-        pbit = PAP_WITHPEER;
-        break;
-    default:
-        AUTHDEBUG((LOG_WARNING, "auth_peer_success: unknown protocol %x\n",
-               protocol));
-        pbit = 0;
-    }
-    
-    /*
-     * If there is no more authentication still being done,
-     * proceed to the network (or callback) phase.
-     */
-    if ((auth_pending[unit] &= ~pbit) == 0)
-        network_phase(unit);
-}
-#endif
-
-
-/*
- * np_up - a network protocol has come up.
- */
-void np_up(int unit, u16_t proto)
-{
-    AUTHDEBUG((LOG_INFO, "np_up: %d proto=%X\n", unit, proto));
-    if (num_np_up == 0) {
-	AUTHDEBUG((LOG_INFO, "np_up: maxconnect=%d idle_time_limit=%d\n",ppp_settings.maxconnect,ppp_settings.idle_time_limit));
-        /*
-         * At this point we consider that the link has come up successfully.
-         */
-        if (ppp_settings.idle_time_limit > 0)
-            TIMEOUT(check_idle, NULL, ppp_settings.idle_time_limit);
-        
-        /*
-         * Set a timeout to close the connection once the maximum
-         * connect time has expired.
-         */
-        if (ppp_settings.maxconnect > 0)
-            TIMEOUT(connect_time_expired, 0, ppp_settings.maxconnect);
-    }
-    ++num_np_up;
-}
-
-/*
- * np_down - a network protocol has gone down.
- */
-void np_down(int unit, u16_t proto)
-{
-    AUTHDEBUG((LOG_INFO, "np_down: %d proto=%X\n", unit, proto));
-    if (--num_np_up == 0 && ppp_settings.idle_time_limit > 0) {
-        UNTIMEOUT(check_idle, NULL);
-    }
-}
-
-/*
- * np_finished - a network protocol has finished using the link.
- */
-void np_finished(int unit, u16_t proto)
-{
-    AUTHDEBUG((LOG_INFO, "np_finished: %d proto=%X\n", unit, proto));
-    if (--num_np_open <= 0) {
-        /* no further use for the link: shut up shop. */
-        lcp_close(0, "No network protocols running");
-    }
-}
-
-/*
- * auth_reset - called when LCP is starting negotiations to recheck
- * authentication options, i.e. whether we have appropriate secrets
- * to use for authenticating ourselves and/or the peer.
- */
-void auth_reset(int unit)
-{
-    lcp_options *go = &lcp_gotoptions[unit];
-    lcp_options *ao = &lcp_allowoptions[0];
-    ipcp_options *ipwo = &ipcp_wantoptions[0];
-    u32_t remote;
-    
-    AUTHDEBUG((LOG_INFO, "auth_reset: %d\n", unit));
-    ao->neg_upap = !ppp_settings.refuse_pap && (ppp_settings.passwd[0] != 0 || get_pap_passwd(unit, NULL, NULL));
-    ao->neg_chap = !ppp_settings.refuse_chap && ppp_settings.passwd[0] != 0 /*have_chap_secret(ppp_settings.user, ppp_settings.remote_name, (u32_t)0)*/;
-    
-    if (go->neg_upap && !have_pap_secret())
-        go->neg_upap = 0;
-    if (go->neg_chap) {
-        remote = ipwo->accept_remote? 0: ipwo->hisaddr;
-        if (!have_chap_secret(ppp_settings.remote_name, ppp_settings.our_name, remote))
-            go->neg_chap = 0;
-    }
-}
-
-
-#if PAP_SUPPORT > 0
-/*
- * check_passwd - Check the user name and passwd against the PAP secrets
- * file.  If requested, also check against the system password database,
- * and login the user if OK.
- *
- * returns:
- *  UPAP_AUTHNAK: Authentication failed.
- *  UPAP_AUTHACK: Authentication succeeded.
- * In either case, msg points to an appropriate message.
- */
-int check_passwd(
-	int unit,
-	char *auser,
-	int userlen,
-	char *apasswd,
-	int passwdlen,
-	char **msg,
-	int *msglen
-)
-{
-#if 1
-	*msg = (char *) 0;
-	return UPAP_AUTHACK;     /* XXX Assume all entries OK. */
-#else
-    int ret = 0;
-    struct wordlist *addrs = NULL;
-    char passwd[256], user[256];
-    char secret[MAXWORDLEN];
-    static u_short attempts = 0;
-    
-    /*
-     * Make copies of apasswd and auser, then null-terminate them.
-     */
-    BCOPY(apasswd, passwd, passwdlen);
-    passwd[passwdlen] = '\0';
-    BCOPY(auser, user, userlen);
-    user[userlen] = '\0';
-    *msg = (char *) 0;
-
-    /* XXX Validate user name and password. */
-    ret = UPAP_AUTHACK;     /* XXX Assume all entries OK. */
-        
-    if (ret == UPAP_AUTHNAK) {
-        if (*msg == (char *) 0)
-            *msg = "Login incorrect";
-        *msglen = strlen(*msg);
-        /*
-         * Frustrate passwd stealer programs.
-         * Allow 10 tries, but start backing off after 3 (stolen from login).
-         * On 10'th, drop the connection.
-         */
-        if (attempts++ >= 10) {
-            AUTHDEBUG((LOG_WARNING, "%d LOGIN FAILURES BY %s\n", attempts, user));
-            /*ppp_panic("Excess Bad Logins");*/
-        }
-        if (attempts > 3) {
-            sys_msleep((attempts - 3) * 5);
-        }
-        if (addrs != NULL) {
-            free_wordlist(addrs);
-        }
-    } else {
-        attempts = 0;           /* Reset count */
-        if (*msg == (char *) 0)
-            *msg = "Login ok";
-        *msglen = strlen(*msg);
-        set_allowed_addrs(unit, addrs);
-    }
-    
-    BZERO(passwd, sizeof(passwd));
-    BZERO(secret, sizeof(secret));
-    
-    return ret;
-#endif
-}
-#endif
-
-
-/*
- * auth_ip_addr - check whether the peer is authorized to use
- * a given IP address.  Returns 1 if authorized, 0 otherwise.
- */
-int auth_ip_addr(int unit, u32_t addr)
-{
-    return ip_addr_check(addr, addresses[unit]);
-}
-
-/*
- * bad_ip_adrs - return 1 if the IP address is one we don't want
- * to use, such as an address in the loopback net or a multicast address.
- * addr is in network byte order.
- */
-int bad_ip_adrs(u32_t addr)
-{
-    addr = ntohl(addr);
-    return (addr >> IN_CLASSA_NSHIFT) == IN_LOOPBACKNET
-        || IN_MULTICAST(addr) || IN_BADCLASS(addr);
-}
-
-
-#if CHAP_SUPPORT > 0
-/*
- * get_secret - open the CHAP secret file and return the secret
- * for authenticating the given client on the given server.
- * (We could be either client or server).
- */
-int get_secret(
-    int unit,
-    char *client,
-    char *server,
-    char *secret,
-    int *secret_len,
-    int save_addrs
-)
-{
-#if 1
-    int len;
-    struct wordlist *addrs;
-    
-    addrs = NULL;
-
-    if(!client || !client[0] || strcmp(client, ppp_settings.user)) {
-	return 0;
-    }
-
-    len = strlen(ppp_settings.passwd);
-    if (len > MAXSECRETLEN) {
-        AUTHDEBUG((LOG_ERR, "Secret for %s on %s is too long\n", client, server));
-        len = MAXSECRETLEN;
-    }
-    BCOPY(ppp_settings.passwd, secret, len);
-    *secret_len = len;
-    
-    return 1;
-#else
-    int ret = 0, len;
-    struct wordlist *addrs;
-    char secbuf[MAXWORDLEN];
-    
-    addrs = NULL;
-    secbuf[0] = 0;
-
-    /* XXX Find secret. */  
-    if (ret < 0)
-        return 0;
-    
-    if (save_addrs)
-        set_allowed_addrs(unit, addrs);
-    
-    len = strlen(secbuf);
-    if (len > MAXSECRETLEN) {
-        AUTHDEBUG((LOG_ERR, "Secret for %s on %s is too long\n", client, server));
-        len = MAXSECRETLEN;
-    }
-    BCOPY(secbuf, secret, len);
-    BZERO(secbuf, sizeof(secbuf));
-    *secret_len = len;
-    
-    return 1;
-#endif
-}
-#endif
-
-
-#if 0 /* UNUSED */
-/*
- * auth_check_options - called to check authentication options.
- */
-void auth_check_options(void)
-{
-    lcp_options *wo = &lcp_wantoptions[0];
-    int can_auth;
-    ipcp_options *ipwo = &ipcp_wantoptions[0];
-    u32_t remote;
-    
-    /* Default our_name to hostname, and user to our_name */
-    if (ppp_settings.our_name[0] == 0 || ppp_settings.usehostname)
-        strcpy(ppp_settings.our_name, ppp_settings.hostname);
-    if (ppp_settings.user[0] == 0)
-        strcpy(ppp_settings.user, ppp_settings.our_name);
-    
-    /* If authentication is required, ask peer for CHAP or PAP. */
-    if (ppp_settings.auth_required && !wo->neg_chap && !wo->neg_upap) {
-        wo->neg_chap = 1;
-        wo->neg_upap = 1;
-    }
-    
-    /*
-     * Check whether we have appropriate secrets to use
-     * to authenticate the peer.
-     */
-    can_auth = wo->neg_upap && have_pap_secret();
-    if (!can_auth && wo->neg_chap) {
-        remote = ipwo->accept_remote? 0: ipwo->hisaddr;
-        can_auth = have_chap_secret(ppp_settings.remote_name, ppp_settings.our_name, remote);
-    }
-    
-    if (ppp_settings.auth_required && !can_auth) {
-        ppp_panic("No auth secret");
-    }
-}
-#endif
-
-
-/**********************************/
-/*** LOCAL FUNCTION DEFINITIONS ***/
-/**********************************/
-/*
- * Proceed to the network phase.
- */
-static void network_phase(int unit)
-{
-    int i;
-    struct protent *protp;
-    lcp_options *go = &lcp_gotoptions[unit];
-    
-    /*
-     * If the peer had to authenticate, run the auth-up script now.
-     */
-    if ((go->neg_chap || go->neg_upap) && !did_authup) {
-        /* XXX Do setup for peer authentication. */
-        did_authup = 1;
-    }
-    
-#if CBCP_SUPPORT > 0
-    /*
-     * If we negotiated callback, do it now.
-     */
-    if (go->neg_cbcp) {
-        lcp_phase[unit] = PHASE_CALLBACK;
-        (*cbcp_protent.open)(unit);
-        return;
-    }
-#endif
-    
-    lcp_phase[unit] = PHASE_NETWORK;
-    for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i)
-        if (protp->protocol < 0xC000 && protp->enabled_flag
-                && protp->open != NULL) {
-            (*protp->open)(unit);
-            if (protp->protocol != PPP_CCP)
-                ++num_np_open;
-        }
-    
-    if (num_np_open == 0)
-        /* nothing to do */
-        lcp_close(0, "No network protocols running");
-}
-
-/*
- * check_idle - check whether the link has been idle for long
- * enough that we can shut it down.
- */
-static void check_idle(void *arg)
-{
-    struct ppp_idle idle;
-    u_short itime;
-    
-	(void)arg;
-    if (!get_idle_time(0, &idle))
-        return;
-    itime = LWIP_MIN(idle.xmit_idle, idle.recv_idle);
-    if (itime >= ppp_settings.idle_time_limit) {
-        /* link is idle: shut it down. */
-        AUTHDEBUG((LOG_INFO, "Terminating connection due to lack of activity.\n"));
-        lcp_close(0, "Link inactive");
-    } else {
-        TIMEOUT(check_idle, NULL, ppp_settings.idle_time_limit - itime);
-    }
-}
-
-/*
- * connect_time_expired - log a message and close the connection.
- */
-static void connect_time_expired(void *arg)
-{
-	(void)arg;
-
-    AUTHDEBUG((LOG_INFO, "Connect time expired\n"));
-    lcp_close(0, "Connect time expired");   /* Close connection */
-}
-
-#if 0
-/*
- * login - Check the user name and password against the system
- * password database, and login the user if OK.
- *
- * returns:
- *  UPAP_AUTHNAK: Login failed.
- *  UPAP_AUTHACK: Login succeeded.
- * In either case, msg points to an appropriate message.
- */
-static int login(char *user, char *passwd, char **msg, int *msglen)
-{
-    /* XXX Fail until we decide that we want to support logins. */
-    return (UPAP_AUTHNAK);
-}
-#endif
-
-/*
- * logout - Logout the user.
- */
-static void logout(void)
-{
-    logged_in = 0;
-}
-
-
-/*
- * null_login - Check if a username of "" and a password of "" are
- * acceptable, and iff so, set the list of acceptable IP addresses
- * and return 1.
- */
-static int null_login(int unit)
-{
-	(void)unit;
-    /* XXX Fail until we decide that we want to support logins. */
-    return 0;
-}
-
-
-/*
- * get_pap_passwd - get a password for authenticating ourselves with
- * our peer using PAP.  Returns 1 on success, 0 if no suitable password
- * could be found.
- */
-static int get_pap_passwd(int unit, char *user, char *passwd)
-{
-/* normally we would reject PAP if no password is provided,
-   but this causes problems with some providers (like CHT in Taiwan)
-   who incorrectly request PAP and expect a bogus/empty password, so
-   always provide a default user/passwd of "none"/"none"
-*/
-    if(user)
-    	strcpy(user,   "none");
-    if(passwd)
-    	strcpy(passwd, "none");
-
-    return 1;
-}
-
-
-/*
- * have_pap_secret - check whether we have a PAP file with any
- * secrets that we could possibly use for authenticating the peer.
- */
-static int have_pap_secret(void)
-{
-    /* XXX Fail until we set up our passwords. */
-    return 0;
-}
-
-
-/*
- * have_chap_secret - check whether we have a CHAP file with a
- * secret that we could possibly use for authenticating `client'
- * on `server'.  Either can be the null string, meaning we don't
- * know the identity yet.
- */
-static int have_chap_secret(char *client, char *server, u32_t remote)
-{
-	(void)client;
-	(void)server;
-	(void)remote;
-    /* XXX Fail until we set up our passwords. */
-    return 0;
-}
-
-
-#if 0 /* PAP_SUPPORT > 0 || CHAP_SUPPORT > 0 */
-/*
- * set_allowed_addrs() - set the list of allowed addresses.
- */
-static void set_allowed_addrs(int unit, struct wordlist *addrs)
-{
-    if (addresses[unit] != NULL)
-        free_wordlist(addresses[unit]);
-    addresses[unit] = addrs;
-
-#if 0
-    /*
-     * If there's only one authorized address we might as well
-     * ask our peer for that one right away
-     */
-    if (addrs != NULL && addrs->next == NULL) {
-        char *p = addrs->word;
-        struct ipcp_options *wo = &ipcp_wantoptions[unit];
-        u32_t a;
-        struct hostent *hp;
-        
-        if (wo->hisaddr == 0 && *p != '!' && *p != '-'
-                && strchr(p, '/') == NULL) {
-            hp = gethostbyname(p);
-            if (hp != NULL && hp->h_addrtype == AF_INET)
-                a = *(u32_t *)hp->h_addr;
-            else
-                a = inet_addr(p);
-            if (a != (u32_t) -1)
-                wo->hisaddr = a;
-        }
-    }
-#endif
-}
-#endif
-
-static int ip_addr_check(u32_t addr, struct wordlist *addrs)
-{
-    
-    /* don't allow loopback or multicast address */
-    if (bad_ip_adrs(addr))
-        return 0;
-    
-    if (addrs == NULL)
-        return !ppp_settings.auth_required;      /* no addresses authorized */
-    
-    /* XXX All other addresses allowed. */
-    return 1;
-}
-
-#if 0 /* PAP_SUPPORT > 0 || CHAP_SUPPORT */
-/*
- * free_wordlist - release memory allocated for a wordlist.
- */
-static void free_wordlist(struct wordlist *wp)
-{
-    struct wordlist *next;
-    
-    while (wp != NULL) {
-        next = wp->next;
-        free(wp);
-        wp = next;
-    }
-}
-#endif
-
-#endif /* PPP_SUPPORT */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/auth.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/auth.h
deleted file mode 100644
index d6a5de5b7..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/auth.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*****************************************************************************
-* auth.h -  PPP Authentication and phase control header file.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* portions Copyright (c) 1998 Global Election Systems Inc.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY
-*
-* 03-01-01 Marc Boucher 
-*   Ported to lwIP.
-* 97-12-04 Guy Lancaster , Global Election Systems Inc.
-*	Original derived from BSD pppd.h.
-*****************************************************************************/
-/*
- * pppd.h - PPP daemon global declarations.
- *
- * Copyright (c) 1989 Carnegie Mellon University.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by Carnegie Mellon University.  The name of the
- * University may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- *
- */
-
-#ifndef AUTH_H
-#define AUTH_H
-
-/***********************
-*** PUBLIC FUNCTIONS ***
-***********************/
-void link_required (int);		/* we are starting to use the link */
-void link_terminated (int);	/* we are finished with the link */
-void link_down (int);			/* the LCP layer has left the Opened state */
-void link_established (int);	/* the link is up; authenticate now */
-void np_up (int, u16_t);			/* a network protocol has come up */
-void np_down (int, u16_t);		/* a network protocol has gone down */
-void np_finished (int, u16_t);	/* a network protocol no longer needs link */
-void auth_peer_fail (int, u16_t);/* peer failed to authenticate itself */
-
-/* peer successfully authenticated itself */
-void auth_peer_success (int, u16_t, char *, int);
-
-/* we failed to authenticate ourselves */
-void auth_withpeer_fail (int, u16_t);
-
-/* we successfully authenticated ourselves */
-void auth_withpeer_success (int, u16_t);
-
-/* check authentication options supplied */
-void auth_check_options (void);
-void auth_reset (int);			/* check what secrets we have */
-
-/* Check peer-supplied username/password */
-int  check_passwd (int, char *, int, char *, int, char **, int *);
-
-/* get "secret" for chap */
-int  get_secret (int, char *, char *, char *, int *, int);
-
-/* check if IP address is authorized */
-int  auth_ip_addr (int, u32_t);
-
-/* check if IP address is unreasonable */
-int  bad_ip_adrs (u32_t);
-
-
-#endif /* AUTH_H */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/chap.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/chap.c
deleted file mode 100644
index 4d1dc0d24..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/chap.c
+++ /dev/null
@@ -1,872 +0,0 @@
-/*** WARNING - THIS HAS NEVER BEEN FINISHED ***/
-/*****************************************************************************
-* chap.c - Network Challenge Handshake Authentication Protocol program file.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* portions Copyright (c) 1997 by Global Election Systems Inc.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY
-*
-* 03-01-01 Marc Boucher 
-*   Ported to lwIP.
-* 97-12-04 Guy Lancaster , Global Election Systems Inc.
-*	Original based on BSD chap.c.
-*****************************************************************************/
-/*
- * chap.c - Challenge Handshake Authentication Protocol.
- *
- * Copyright (c) 1993 The Australian National University.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by the Australian National University.  The name of the University
- * may not be used to endorse or promote products derived from this
- * software without specific prior written permission.
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- *
- * Copyright (c) 1991 Gregory M. Christy.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by Gregory M. Christy.  The name of the author may not be used to
- * endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- */
-
-#include "ppp.h"
-#if PPP_SUPPORT > 0
-#include "magic.h"
-
-#if CHAP_SUPPORT > 0
-
-#include "randm.h"
-#include "auth.h"
-#include "md5.h"
-#include "chap.h"
-#include "chpms.h"
-#include "pppdebug.h"
-
-
-/*************************/
-/*** LOCAL DEFINITIONS ***/
-/*************************/
-
-
-/************************/
-/*** LOCAL DATA TYPES ***/
-/************************/
-
-
-/***********************************/
-/*** LOCAL FUNCTION DECLARATIONS ***/
-/***********************************/
-/*
- * Protocol entry points.
- */
-static void ChapInit (int);
-static void ChapLowerUp (int);
-static void ChapLowerDown (int);
-static void ChapInput (int, u_char *, int);
-static void ChapProtocolReject (int);
-static int  ChapPrintPkt (u_char *, int,
-			      void (*) (void *, char *, ...), void *);
-
-static void ChapChallengeTimeout (void *);
-static void ChapResponseTimeout (void *);
-static void ChapReceiveChallenge (chap_state *, u_char *, int, int);
-static void ChapRechallenge (void *);
-static void ChapReceiveResponse (chap_state *, u_char *, int, int);
-static void ChapReceiveSuccess(chap_state *cstate, u_char *inp, u_char id, int len);
-static void ChapReceiveFailure(chap_state *cstate, u_char *inp, u_char id, int len);
-static void ChapSendStatus (chap_state *, int);
-static void ChapSendChallenge (chap_state *);
-static void ChapSendResponse (chap_state *);
-static void ChapGenChallenge (chap_state *);
-
-
-/******************************/
-/*** PUBLIC DATA STRUCTURES ***/
-/******************************/
-chap_state chap[NUM_PPP];		/* CHAP state; one for each unit */
-
-struct protent chap_protent = {
-    PPP_CHAP,
-    ChapInit,
-    ChapInput,
-    ChapProtocolReject,
-    ChapLowerUp,
-    ChapLowerDown,
-    NULL,
-    NULL,
-#if 0
-    ChapPrintPkt,
-    NULL,
-#endif
-    1,
-    "CHAP",
-#if 0
-    NULL,
-    NULL,
-    NULL
-#endif
-};
-
-
-
-/*****************************/
-/*** LOCAL DATA STRUCTURES ***/
-/*****************************/
-static char *ChapCodenames[] = {
-	"Challenge", "Response", "Success", "Failure"
-};
-
-
-
-/***********************************/
-/*** PUBLIC FUNCTION DEFINITIONS ***/
-/***********************************/
-/*
- * ChapAuthWithPeer - Authenticate us with our peer (start client).
- *
- */
-void ChapAuthWithPeer(int unit, char *our_name, int digest)
-{
-	chap_state *cstate = &chap[unit];
-	
-	cstate->resp_name = our_name;
-	cstate->resp_type = digest;
-	
-	if (cstate->clientstate == CHAPCS_INITIAL ||
-			cstate->clientstate == CHAPCS_PENDING) {
-		/* lower layer isn't up - wait until later */
-		cstate->clientstate = CHAPCS_PENDING;
-		return;
-	}
-	
-	/*
-	 * We get here as a result of LCP coming up.
-	 * So even if CHAP was open before, we will 
-	 * have to re-authenticate ourselves.
-	 */
-	cstate->clientstate = CHAPCS_LISTEN;
-}
-
-
-/*
- * ChapAuthPeer - Authenticate our peer (start server).
- */
-void ChapAuthPeer(int unit, char *our_name, int digest)
-{
-	chap_state *cstate = &chap[unit];
-	
-	cstate->chal_name = our_name;
-	cstate->chal_type = digest;
-	
-	if (cstate->serverstate == CHAPSS_INITIAL ||
-			cstate->serverstate == CHAPSS_PENDING) {
-		/* lower layer isn't up - wait until later */
-		cstate->serverstate = CHAPSS_PENDING;
-		return;
-	}
-	
-	ChapGenChallenge(cstate);
-	ChapSendChallenge(cstate);		/* crank it up dude! */
-	cstate->serverstate = CHAPSS_INITIAL_CHAL;
-}
-
-
-
-
-/**********************************/
-/*** LOCAL FUNCTION DEFINITIONS ***/
-/**********************************/
-/*
- * ChapInit - Initialize a CHAP unit.
- */
-static void ChapInit(int unit)
-{
-	chap_state *cstate = &chap[unit];
-	
-	BZERO(cstate, sizeof(*cstate));
-	cstate->unit = unit;
-	cstate->clientstate = CHAPCS_INITIAL;
-	cstate->serverstate = CHAPSS_INITIAL;
-	cstate->timeouttime = CHAP_DEFTIMEOUT;
-	cstate->max_transmits = CHAP_DEFTRANSMITS;
-	/* random number generator is initialized in magic_init */
-}
-
-
-/*
- * ChapChallengeTimeout - Timeout expired on sending challenge.
- */
-static void ChapChallengeTimeout(void *arg)
-{
-	chap_state *cstate = (chap_state *) arg;
-	
-	/* if we aren't sending challenges, don't worry.  then again we */
-	/* probably shouldn't be here either */
-	if (cstate->serverstate != CHAPSS_INITIAL_CHAL &&
-			cstate->serverstate != CHAPSS_RECHALLENGE)
-		return;
-	
-	if (cstate->chal_transmits >= cstate->max_transmits) {
-		/* give up on peer */
-		CHAPDEBUG((LOG_ERR, "Peer failed to respond to CHAP challenge\n"));
-		cstate->serverstate = CHAPSS_BADAUTH;
-		auth_peer_fail(cstate->unit, PPP_CHAP);
-		return;
-	}
-	
-	ChapSendChallenge(cstate);		/* Re-send challenge */
-}
-
-
-/*
- * ChapResponseTimeout - Timeout expired on sending response.
- */
-static void ChapResponseTimeout(void *arg)
-{
-	chap_state *cstate = (chap_state *) arg;
-	
-	/* if we aren't sending a response, don't worry. */
-	if (cstate->clientstate != CHAPCS_RESPONSE)
-		return;
-	
-	ChapSendResponse(cstate);		/* re-send response */
-}
-
-
-/*
- * ChapRechallenge - Time to challenge the peer again.
- */
-static void ChapRechallenge(void *arg)
-{
-	chap_state *cstate = (chap_state *) arg;
-	
-	/* if we aren't sending a response, don't worry. */
-	if (cstate->serverstate != CHAPSS_OPEN)
-		return;
-	
-	ChapGenChallenge(cstate);
-	ChapSendChallenge(cstate);
-	cstate->serverstate = CHAPSS_RECHALLENGE;
-}
-
-
-/*
- * ChapLowerUp - The lower layer is up.
- *
- * Start up if we have pending requests.
- */
-static void ChapLowerUp(int unit)
-{
-	chap_state *cstate = &chap[unit];
-	
-	if (cstate->clientstate == CHAPCS_INITIAL)
-		cstate->clientstate = CHAPCS_CLOSED;
-	else if (cstate->clientstate == CHAPCS_PENDING)
-		cstate->clientstate = CHAPCS_LISTEN;
-	
-	if (cstate->serverstate == CHAPSS_INITIAL)
-		cstate->serverstate = CHAPSS_CLOSED;
-	else if (cstate->serverstate == CHAPSS_PENDING) {
-		ChapGenChallenge(cstate);
-		ChapSendChallenge(cstate);
-		cstate->serverstate = CHAPSS_INITIAL_CHAL;
-	}
-}
-
-
-/*
- * ChapLowerDown - The lower layer is down.
- *
- * Cancel all timeouts.
- */
-static void ChapLowerDown(int unit)
-{
-	chap_state *cstate = &chap[unit];
-	
-	/* Timeout(s) pending?  Cancel if so. */
-	if (cstate->serverstate == CHAPSS_INITIAL_CHAL ||
-			cstate->serverstate == CHAPSS_RECHALLENGE)
-		UNTIMEOUT(ChapChallengeTimeout, cstate);
-	else if (cstate->serverstate == CHAPSS_OPEN
-			&& cstate->chal_interval != 0)
-		UNTIMEOUT(ChapRechallenge, cstate);
-	if (cstate->clientstate == CHAPCS_RESPONSE)
-		UNTIMEOUT(ChapResponseTimeout, cstate);
-	
-	cstate->clientstate = CHAPCS_INITIAL;
-	cstate->serverstate = CHAPSS_INITIAL;
-}
-
-
-/*
- * ChapProtocolReject - Peer doesn't grok CHAP.
- */
-static void ChapProtocolReject(int unit)
-{
-	chap_state *cstate = &chap[unit];
-	
-	if (cstate->serverstate != CHAPSS_INITIAL &&
-			cstate->serverstate != CHAPSS_CLOSED)
-		auth_peer_fail(unit, PPP_CHAP);
-	if (cstate->clientstate != CHAPCS_INITIAL &&
-			cstate->clientstate != CHAPCS_CLOSED)
-		auth_withpeer_fail(unit, PPP_CHAP);
-	ChapLowerDown(unit);		/* shutdown chap */
-}
-
-
-/*
- * ChapInput - Input CHAP packet.
- */
-static void ChapInput(int unit, u_char *inpacket, int packet_len)
-{
-	chap_state *cstate = &chap[unit];
-	u_char *inp;
-	u_char code, id;
-	int len;
-	
-	/*
-	 * Parse header (code, id and length).
-	 * If packet too short, drop it.
-	 */
-	inp = inpacket;
-	if (packet_len < CHAP_HEADERLEN) {
-		CHAPDEBUG((LOG_INFO, "ChapInput: rcvd short header.\n"));
-		return;
-	}
-	GETCHAR(code, inp);
-	GETCHAR(id, inp);
-	GETSHORT(len, inp);
-	if (len < CHAP_HEADERLEN) {
-		CHAPDEBUG((LOG_INFO, "ChapInput: rcvd illegal length.\n"));
-		return;
-	}
-	if (len > packet_len) {
-		CHAPDEBUG((LOG_INFO, "ChapInput: rcvd short packet.\n"));
-		return;
-	}
-	len -= CHAP_HEADERLEN;
-	
-	/*
-	 * Action depends on code (as in fact it usually does :-).
-	 */
-	switch (code) {
-	case CHAP_CHALLENGE:
-		ChapReceiveChallenge(cstate, inp, id, len);
-		break;
-	
-	case CHAP_RESPONSE:
-		ChapReceiveResponse(cstate, inp, id, len);
-		break;
-	
-	case CHAP_FAILURE:
-		ChapReceiveFailure(cstate, inp, id, len);
-		break;
-	
-	case CHAP_SUCCESS:
-		ChapReceiveSuccess(cstate, inp, id, len);
-		break;
-	
-	default:				/* Need code reject? */
-		CHAPDEBUG((LOG_WARNING, "Unknown CHAP code (%d) received.\n", code));
-		break;
-	}
-}
-
-
-/*
- * ChapReceiveChallenge - Receive Challenge and send Response.
- */
-static void ChapReceiveChallenge(chap_state *cstate, u_char *inp, int id, int len)
-{
-	int rchallenge_len;
-	u_char *rchallenge;
-	int secret_len;
-	char secret[MAXSECRETLEN];
-	char rhostname[256];
-	MD5_CTX mdContext;
-	u_char hash[MD5_SIGNATURE_SIZE];
-	
-	CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: Rcvd id %d.\n", id));
-	if (cstate->clientstate == CHAPCS_CLOSED ||
-		cstate->clientstate == CHAPCS_PENDING) {
-		CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: in state %d\n",
-			   cstate->clientstate));
-		return;
-	}
-	
-	if (len < 2) {
-		CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: rcvd short packet.\n"));
-		return;
-	}
-	
-	GETCHAR(rchallenge_len, inp);
-	len -= sizeof (u_char) + rchallenge_len;	/* now name field length */
-	if (len < 0) {
-		CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: rcvd short packet.\n"));
-		return;
-	}
-	rchallenge = inp;
-	INCPTR(rchallenge_len, inp);
-	
-	if (len >= sizeof(rhostname))
-		len = sizeof(rhostname) - 1;
-	BCOPY(inp, rhostname, len);
-	rhostname[len] = '\000';
-	
-	CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: received name field '%s'\n",
-	       rhostname));
-	
-	/* Microsoft doesn't send their name back in the PPP packet */
-	if (ppp_settings.remote_name[0] != 0 && (ppp_settings.explicit_remote || rhostname[0] == 0)) {
-		strncpy(rhostname, ppp_settings.remote_name, sizeof(rhostname));
-		rhostname[sizeof(rhostname) - 1] = 0;
-		CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: using '%s' as remote name\n",
-			   rhostname));
-	}
-	
-	/* get secret for authenticating ourselves with the specified host */
-	if (!get_secret(cstate->unit, cstate->resp_name, rhostname,
-			    secret, &secret_len, 0)) {
-		secret_len = 0;		/* assume null secret if can't find one */
-		CHAPDEBUG((LOG_WARNING, "No CHAP secret found for authenticating us to %s\n", rhostname));
-	}
-	
-	/* cancel response send timeout if necessary */
-	if (cstate->clientstate == CHAPCS_RESPONSE)
-		UNTIMEOUT(ChapResponseTimeout, cstate);
-	
-	cstate->resp_id = id;
-	cstate->resp_transmits = 0;
-	
-	/*  generate MD based on negotiated type */
-	switch (cstate->resp_type) { 
-	
-	case CHAP_DIGEST_MD5:
-		MD5Init(&mdContext);
-		MD5Update(&mdContext, &cstate->resp_id, 1);
-		MD5Update(&mdContext, (u_char*)secret, secret_len);
-		MD5Update(&mdContext, rchallenge, rchallenge_len);
-		MD5Final(hash, &mdContext);
-		BCOPY(hash, cstate->response, MD5_SIGNATURE_SIZE);
-		cstate->resp_length = MD5_SIGNATURE_SIZE;
-		break;
-	
-#ifdef CHAPMS
-	case CHAP_MICROSOFT:
-		ChapMS(cstate, rchallenge, rchallenge_len, secret, secret_len);
-		break;
-#endif
-	
-	default:
-		CHAPDEBUG((LOG_INFO, "unknown digest type %d\n", cstate->resp_type));
-		return;
-	}
-	
-	BZERO(secret, sizeof(secret));
-	ChapSendResponse(cstate);
-}
-
-
-/*
- * ChapReceiveResponse - Receive and process response.
- */
-static void ChapReceiveResponse(chap_state *cstate, u_char *inp, int id, int len)
-{
-	u_char *remmd, remmd_len;
-	int secret_len, old_state;
-	int code;
-	char rhostname[256];
-	MD5_CTX mdContext;
-	char secret[MAXSECRETLEN];
-	u_char hash[MD5_SIGNATURE_SIZE];
-	
-	CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: Rcvd id %d.\n", id));
-	
-	if (cstate->serverstate == CHAPSS_CLOSED ||
-			cstate->serverstate == CHAPSS_PENDING) {
-		CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: in state %d\n",
-		cstate->serverstate));
-		return;
-	}
-	
-	if (id != cstate->chal_id)
-		return;			/* doesn't match ID of last challenge */
-	
-	/*
-	* If we have received a duplicate or bogus Response,
-	* we have to send the same answer (Success/Failure)
-	* as we did for the first Response we saw.
-	*/
-	if (cstate->serverstate == CHAPSS_OPEN) {
-		ChapSendStatus(cstate, CHAP_SUCCESS);
-		return;
-	}
-	if (cstate->serverstate == CHAPSS_BADAUTH) {
-		ChapSendStatus(cstate, CHAP_FAILURE);
-		return;
-	}
-	
-	if (len < 2) {
-		CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: rcvd short packet.\n"));
-		return;
-	}
-	GETCHAR(remmd_len, inp);		/* get length of MD */
-	remmd = inp;			/* get pointer to MD */
-	INCPTR(remmd_len, inp);
-	
-	len -= sizeof (u_char) + remmd_len;
-	if (len < 0) {
-		CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: rcvd short packet.\n"));
-		return;
-	}
-	
-	UNTIMEOUT(ChapChallengeTimeout, cstate);
-	
-	if (len >= sizeof(rhostname))
-		len = sizeof(rhostname) - 1;
-	BCOPY(inp, rhostname, len);
-	rhostname[len] = '\000';
-	
-	CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: received name field: %s\n",
-				rhostname));
-	
-	/*
-	* Get secret for authenticating them with us,
-	* do the hash ourselves, and compare the result.
-	*/
-	code = CHAP_FAILURE;
-	if (!get_secret(cstate->unit, rhostname, cstate->chal_name,
-	secret, &secret_len, 1)) {
-/*        CHAPDEBUG((LOG_WARNING, TL_CHAP, "No CHAP secret found for authenticating %s\n", rhostname)); */
-		CHAPDEBUG((LOG_WARNING, "No CHAP secret found for authenticating %s\n",
-		rhostname));
-	} else {
-	
-		/*  generate MD based on negotiated type */
-		switch (cstate->chal_type) { 
-		
-		case CHAP_DIGEST_MD5:		/* only MD5 is defined for now */
-			if (remmd_len != MD5_SIGNATURE_SIZE)
-				break;			/* it's not even the right length */
-			MD5Init(&mdContext);
-			MD5Update(&mdContext, &cstate->chal_id, 1);
-			MD5Update(&mdContext, (u_char*)secret, secret_len);
-			MD5Update(&mdContext, cstate->challenge, cstate->chal_len);
-			MD5Final(hash, &mdContext); 
-			
-			/* compare local and remote MDs and send the appropriate status */
-			if (memcmp (hash, remmd, MD5_SIGNATURE_SIZE) == 0)
-				code = CHAP_SUCCESS;	/* they are the same! */
-			break;
-		
-		default:
-			CHAPDEBUG((LOG_INFO, "unknown digest type %d\n", cstate->chal_type));
-		}
-	}
-	
-	BZERO(secret, sizeof(secret));
-	ChapSendStatus(cstate, code);
-	
-	if (code == CHAP_SUCCESS) {
-		old_state = cstate->serverstate;
-		cstate->serverstate = CHAPSS_OPEN;
-		if (old_state == CHAPSS_INITIAL_CHAL) {
-			auth_peer_success(cstate->unit, PPP_CHAP, rhostname, len);
-		}
-		if (cstate->chal_interval != 0)
-			TIMEOUT(ChapRechallenge, cstate, cstate->chal_interval);
-	} else {
-		CHAPDEBUG((LOG_ERR, "CHAP peer authentication failed\n"));
-		cstate->serverstate = CHAPSS_BADAUTH;
-		auth_peer_fail(cstate->unit, PPP_CHAP);
-	}
-}
-
-/*
- * ChapReceiveSuccess - Receive Success
- */
-static void ChapReceiveSuccess(chap_state *cstate, u_char *inp, u_char id, int len)
-{
-
-	CHAPDEBUG((LOG_INFO, "ChapReceiveSuccess: Rcvd id %d.\n", id));
-	
-	if (cstate->clientstate == CHAPCS_OPEN)
-		/* presumably an answer to a duplicate response */
-		return;
-	
-	if (cstate->clientstate != CHAPCS_RESPONSE) {
-		/* don't know what this is */
-		CHAPDEBUG((LOG_INFO, "ChapReceiveSuccess: in state %d\n",
-			   cstate->clientstate));
-		return;
-	}
-	
-	UNTIMEOUT(ChapResponseTimeout, cstate);
-	
-	/*
-	 * Print message.
-	 */
-	if (len > 0)
-		PRINTMSG(inp, len);
-	
-	cstate->clientstate = CHAPCS_OPEN;
-	
-	auth_withpeer_success(cstate->unit, PPP_CHAP);
-}
-
-
-/*
- * ChapReceiveFailure - Receive failure.
- */
-static void ChapReceiveFailure(chap_state *cstate, u_char *inp, u_char id, int len)
-{
-	CHAPDEBUG((LOG_INFO, "ChapReceiveFailure: Rcvd id %d.\n", id));
-	
-	if (cstate->clientstate != CHAPCS_RESPONSE) {
-		/* don't know what this is */
-		CHAPDEBUG((LOG_INFO, "ChapReceiveFailure: in state %d\n",
-			   cstate->clientstate));
-		return;
-	}
-	
-	UNTIMEOUT(ChapResponseTimeout, cstate);
-	
-	/*
-	 * Print message.
-	 */
-	if (len > 0)
-		PRINTMSG(inp, len);
-	
-	CHAPDEBUG((LOG_ERR, "CHAP authentication failed\n"));
-	auth_withpeer_fail(cstate->unit, PPP_CHAP);
-}
-
-
-/*
- * ChapSendChallenge - Send an Authenticate challenge.
- */
-static void ChapSendChallenge(chap_state *cstate)
-{
-	u_char *outp;
-	int chal_len, name_len;
-	int outlen;
-	
-	chal_len = cstate->chal_len;
-	name_len = strlen(cstate->chal_name);
-	outlen = CHAP_HEADERLEN + sizeof (u_char) + chal_len + name_len;
-	outp = outpacket_buf[cstate->unit];
-	
-	MAKEHEADER(outp, PPP_CHAP);		/* paste in a CHAP header */
-	
-	PUTCHAR(CHAP_CHALLENGE, outp);
-	PUTCHAR(cstate->chal_id, outp);
-	PUTSHORT(outlen, outp);
-	
-	PUTCHAR(chal_len, outp);		/* put length of challenge */
-	BCOPY(cstate->challenge, outp, chal_len);
-	INCPTR(chal_len, outp);
-	
-	BCOPY(cstate->chal_name, outp, name_len);	/* append hostname */
-	
-	pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN);
-	
-	CHAPDEBUG((LOG_INFO, "ChapSendChallenge: Sent id %d.\n", cstate->chal_id));
-	
-	TIMEOUT(ChapChallengeTimeout, cstate, cstate->timeouttime);
-	++cstate->chal_transmits;
-}
-
-
-/*
- * ChapSendStatus - Send a status response (ack or nak).
- */
-static void ChapSendStatus(chap_state *cstate, int code)
-{
-	u_char *outp;
-	int outlen, msglen;
-	char msg[256];
-	
-	if (code == CHAP_SUCCESS)
-		strcpy(msg, "Welcome!");
-	else
-		strcpy(msg, "I don't like you.  Go 'way.");
-	msglen = strlen(msg);
-	
-	outlen = CHAP_HEADERLEN + msglen;
-	outp = outpacket_buf[cstate->unit];
-	
-	MAKEHEADER(outp, PPP_CHAP);		/* paste in a header */
-	
-	PUTCHAR(code, outp);
-	PUTCHAR(cstate->chal_id, outp);
-	PUTSHORT(outlen, outp);
-	BCOPY(msg, outp, msglen);
-	pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN);
-	
-	CHAPDEBUG((LOG_INFO, "ChapSendStatus: Sent code %d, id %d.\n", code,
-	       cstate->chal_id));
-}
-
-/*
- * ChapGenChallenge is used to generate a pseudo-random challenge string of
- * a pseudo-random length between min_len and max_len.  The challenge
- * string and its length are stored in *cstate, and various other fields of
- * *cstate are initialized.
- */
-
-static void ChapGenChallenge(chap_state *cstate)
-{
-	int chal_len;
-	u_char *ptr = cstate->challenge;
-	int i;
-	
-	/* pick a random challenge length between MIN_CHALLENGE_LENGTH and 
-	   MAX_CHALLENGE_LENGTH */  
-	chal_len = (unsigned)
-				((((magic() >> 16) *
-			        (MAX_CHALLENGE_LENGTH - MIN_CHALLENGE_LENGTH)) >> 16)
-			     + MIN_CHALLENGE_LENGTH);
-	cstate->chal_len = chal_len;
-	cstate->chal_id = ++cstate->id;
-	cstate->chal_transmits = 0;
-	
-	/* generate a random string */
-	for (i = 0; i < chal_len; i++ )
-		*ptr++ = (char) (magic() & 0xff);
-}
-
-/*
- * ChapSendResponse - send a response packet with values as specified
- * in *cstate.
- */
-/* ARGSUSED */
-static void ChapSendResponse(chap_state *cstate)
-{
-	u_char *outp;
-	int outlen, md_len, name_len;
-	
-	md_len = cstate->resp_length;
-	name_len = strlen(cstate->resp_name);
-	outlen = CHAP_HEADERLEN + sizeof (u_char) + md_len + name_len;
-	outp = outpacket_buf[cstate->unit];
-	
-	MAKEHEADER(outp, PPP_CHAP);
-	
-	PUTCHAR(CHAP_RESPONSE, outp);	/* we are a response */
-	PUTCHAR(cstate->resp_id, outp);	/* copy id from challenge packet */
-	PUTSHORT(outlen, outp);			/* packet length */
-	
-	PUTCHAR(md_len, outp);			/* length of MD */
-	BCOPY(cstate->response, outp, md_len);		/* copy MD to buffer */
-	INCPTR(md_len, outp);
-	
-	BCOPY(cstate->resp_name, outp, name_len);	/* append our name */
-	
-	/* send the packet */
-	pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN);
-	
-	cstate->clientstate = CHAPCS_RESPONSE;
-	TIMEOUT(ChapResponseTimeout, cstate, cstate->timeouttime);
-	++cstate->resp_transmits;
-}
-
-/*
- * ChapPrintPkt - print the contents of a CHAP packet.
- */
-static int ChapPrintPkt(
-	u_char *p,
-	int plen,
-	void (*printer) (void *, char *, ...),
-	void *arg
-)
-{
-	int code, id, len;
-	int clen, nlen;
-	u_char x;
-	
-	if (plen < CHAP_HEADERLEN)
-		return 0;
-	GETCHAR(code, p);
-	GETCHAR(id, p);
-	GETSHORT(len, p);
-	if (len < CHAP_HEADERLEN || len > plen)
-		return 0;
-	
-	if (code >= 1 && code <= sizeof(ChapCodenames) / sizeof(char *))
-		printer(arg, " %s", ChapCodenames[code-1]);
-	else
-		printer(arg, " code=0x%x", code);
-	printer(arg, " id=0x%x", id);
-	len -= CHAP_HEADERLEN;
-	switch (code) {
-	case CHAP_CHALLENGE:
-	case CHAP_RESPONSE:
-		if (len < 1)
-			break;
-		clen = p[0];
-		if (len < clen + 1)
-			break;
-		++p;
-		nlen = len - clen - 1;
-		printer(arg, " <");
-		for (; clen > 0; --clen) {
-			GETCHAR(x, p);
-			printer(arg, "%.2x", x);
-		}
-		printer(arg, ">, name = %.*Z", nlen, p);
-		break;
-	case CHAP_FAILURE:
-	case CHAP_SUCCESS:
-		printer(arg, " %.*Z", len, p);
-		break;
-	default:
-		for (clen = len; clen > 0; --clen) {
-			GETCHAR(x, p);
-			printer(arg, " %.2x", x);
-		}
-	}
-	
-	return len + CHAP_HEADERLEN;
-}
-
-#endif
-
-#endif /* PPP_SUPPORT */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/chap.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/chap.h
deleted file mode 100644
index 6fd972752..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/chap.h
+++ /dev/null
@@ -1,167 +0,0 @@
-/*****************************************************************************
-* chap.h - Network Challenge Handshake Authentication Protocol header file.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* portions Copyright (c) 1998 Global Election Systems Inc.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY
-*
-* 03-01-01 Marc Boucher 
-*   Ported to lwIP.
-* 97-12-03 Guy Lancaster , Global Election Systems Inc.
-*	Original built from BSD network code.
-******************************************************************************/
-/*
- * chap.h - Challenge Handshake Authentication Protocol definitions.
- *
- * Copyright (c) 1993 The Australian National University.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by the Australian National University.  The name of the University
- * may not be used to endorse or promote products derived from this
- * software without specific prior written permission.
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- *
- * Copyright (c) 1991 Gregory M. Christy
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by the author.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- *
- * $Id: chap.h,v 1.1 2003/05/27 14:37:56 jani Exp $
- */
-
-#ifndef CHAP_H
-#define CHAP_H
-
-/*************************
-*** PUBLIC DEFINITIONS ***
-*************************/
-
-/* Code + ID + length */
-#define CHAP_HEADERLEN		4
-
-/*
- * CHAP codes.
- */
-
-#define CHAP_DIGEST_MD5		5	/* use MD5 algorithm */
-#define MD5_SIGNATURE_SIZE	16	/* 16 bytes in a MD5 message digest */
-#define CHAP_MICROSOFT		0x80	/* use Microsoft-compatible alg. */
-#define MS_CHAP_RESPONSE_LEN	49	/* Response length for MS-CHAP */
-
-#define CHAP_CHALLENGE		1
-#define CHAP_RESPONSE		2
-#define CHAP_SUCCESS		3
-#define CHAP_FAILURE    	4
-
-/*
- *  Challenge lengths (for challenges we send) and other limits.
- */
-#define MIN_CHALLENGE_LENGTH	32
-#define MAX_CHALLENGE_LENGTH	64
-#define MAX_RESPONSE_LENGTH	64	/* sufficient for MD5 or MS-CHAP */
-
-/*
- * Client (peer) states.
- */
-#define CHAPCS_INITIAL		0	/* Lower layer down, not opened */
-#define CHAPCS_CLOSED		1	/* Lower layer up, not opened */
-#define CHAPCS_PENDING		2	/* Auth us to peer when lower up */
-#define CHAPCS_LISTEN		3	/* Listening for a challenge */
-#define CHAPCS_RESPONSE		4	/* Sent response, waiting for status */
-#define CHAPCS_OPEN		5	/* We've received Success */
-
-/*
- * Server (authenticator) states.
- */
-#define CHAPSS_INITIAL		0	/* Lower layer down, not opened */
-#define CHAPSS_CLOSED		1	/* Lower layer up, not opened */
-#define CHAPSS_PENDING		2	/* Auth peer when lower up */
-#define CHAPSS_INITIAL_CHAL	3	/* We've sent the first challenge */
-#define CHAPSS_OPEN		4	/* We've sent a Success msg */
-#define CHAPSS_RECHALLENGE	5	/* We've sent another challenge */
-#define CHAPSS_BADAUTH		6	/* We've sent a Failure msg */
-
-/************************
-*** PUBLIC DATA TYPES ***
-************************/
-
-/*
- * Each interface is described by a chap structure.
- */
-
-typedef struct chap_state {
-    int unit;			/* Interface unit number */
-    int clientstate;		/* Client state */
-    int serverstate;		/* Server state */
-    u_char challenge[MAX_CHALLENGE_LENGTH]; /* last challenge string sent */
-    u_char chal_len;		/* challenge length */
-    u_char chal_id;		/* ID of last challenge */
-    u_char chal_type;		/* hash algorithm for challenges */
-    u_char id;			/* Current id */
-    char *chal_name;		/* Our name to use with challenge */
-    int chal_interval;		/* Time until we challenge peer again */
-    int timeouttime;		/* Timeout time in seconds */
-    int max_transmits;		/* Maximum # of challenge transmissions */
-    int chal_transmits;		/* Number of transmissions of challenge */
-    int resp_transmits;		/* Number of transmissions of response */
-    u_char response[MAX_RESPONSE_LENGTH];	/* Response to send */
-    u_char resp_length;		/* length of response */
-    u_char resp_id;		/* ID for response messages */
-    u_char resp_type;		/* hash algorithm for responses */
-    char *resp_name;		/* Our name to send with response */
-} chap_state;
-
-
-/******************
-*** PUBLIC DATA ***
-******************/
-extern chap_state chap[];
-
-extern struct protent chap_protent;
-
-
-/***********************
-*** PUBLIC FUNCTIONS ***
-***********************/
-
-void ChapAuthWithPeer (int, char *, int);
-void ChapAuthPeer (int, char *, int);
-
-#endif /* CHAP_H */
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/chpms.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/chpms.c
deleted file mode 100644
index 01755ba39..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/chpms.c
+++ /dev/null
@@ -1,398 +0,0 @@
-/*** WARNING - THIS CODE HAS NOT BEEN FINISHED! ***/
-/*****************************************************************************
-* chpms.c - Network MicroSoft Challenge Handshake Authentication Protocol program file.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* Copyright (c) 1997 by Global Election Systems Inc.  All rights reserved.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY
-*
-* 03-01-01 Marc Boucher 
-*   Ported to lwIP.
-* 97-12-08 Guy Lancaster , Global Election Systems Inc.
-*	Original based on BSD chap_ms.c.
-*****************************************************************************/
-/*
- * chap_ms.c - Microsoft MS-CHAP compatible implementation.
- *
- * Copyright (c) 1995 Eric Rosenquist, Strata Software Limited.
- * http://www.strataware.com/
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by Eric Rosenquist.  The name of the author may not be used to
- * endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- */
-
-/*
- * Modifications by Lauri Pesonen / lpesonen@clinet.fi, april 1997
- *
- *   Implemented LANManager type password response to MS-CHAP challenges.
- *   Now pppd provides both NT style and LANMan style blocks, and the
- *   prefered is set by option "ms-lanman". Default is to use NT.
- *   The hash text (StdText) was taken from Win95 RASAPI32.DLL.
- *
- *   You should also use DOMAIN\\USERNAME as described in README.MSCHAP80
- */
-
-#define USE_CRYPT
-
-
-#include "ppp.h"
-
-#if MSCHAP_SUPPORT > 0
-
-#include "md4.h"
-#ifndef USE_CRYPT
-#include "des.h"
-#endif
-#include "chap.h"
-#include "chpms.h"
-#include "pppdebug.h"
-
-
-/*************************/
-/*** LOCAL DEFINITIONS ***/
-/*************************/
-
-
-/************************/
-/*** LOCAL DATA TYPES ***/
-/************************/
-typedef struct {
-    u_char LANManResp[24];
-    u_char NTResp[24];
-    u_char UseNT;		/* If 1, ignore the LANMan response field */
-} MS_ChapResponse;
-/* We use MS_CHAP_RESPONSE_LEN, rather than sizeof(MS_ChapResponse),
-   in case this struct gets padded. */
-
-
-
-/***********************************/
-/*** LOCAL FUNCTION DECLARATIONS ***/
-/***********************************/
-
-/* XXX Don't know what to do with these. */
-extern void setkey(const char *);
-extern void encrypt(char *, int);
-
-static void	DesEncrypt (u_char *, u_char *, u_char *);
-static void	MakeKey (u_char *, u_char *);
-
-#ifdef USE_CRYPT
-static void	Expand (u_char *, u_char *);
-static void	Collapse (u_char *, u_char *);
-#endif
-
-static void ChallengeResponse(
-	u_char *challenge,	/* IN   8 octets */
-	u_char *pwHash,		/* IN  16 octets */
-	u_char *response	/* OUT 24 octets */
-);
-static void ChapMS_NT(
-	char *rchallenge,
-	int rchallenge_len,
-	char *secret,
-	int secret_len,
-	MS_ChapResponse *response
-);
-static u_char Get7Bits(
-	u_char *input,
-	int startBit
-);
-
-
-/***********************************/
-/*** PUBLIC FUNCTION DEFINITIONS ***/
-/***********************************/
-void ChapMS(
-	chap_state *cstate,
-	char *rchallenge,
-	int rchallenge_len,
-	char *secret,
-	int secret_len
-)
-{
-	MS_ChapResponse	response;
-#ifdef MSLANMAN
-	extern int ms_lanman;
-#endif
-	
-#if 0
-	CHAPDEBUG((LOG_INFO, "ChapMS: secret is '%.*s'\n", secret_len, secret));
-#endif
-	BZERO(&response, sizeof(response));
-	
-	/* Calculate both always */
-	ChapMS_NT(rchallenge, rchallenge_len, secret, secret_len, &response);
-	
-#ifdef MSLANMAN
-	ChapMS_LANMan(rchallenge, rchallenge_len, secret, secret_len, &response);
-	
-	/* prefered method is set by option  */
-	response.UseNT = !ms_lanman;
-#else
-	response.UseNT = 1;
-#endif
-	
-	BCOPY(&response, cstate->response, MS_CHAP_RESPONSE_LEN);
-	cstate->resp_length = MS_CHAP_RESPONSE_LEN;
-}
-
-
-/**********************************/
-/*** LOCAL FUNCTION DEFINITIONS ***/
-/**********************************/
-static void ChallengeResponse(
-	u_char *challenge,	/* IN   8 octets */
-	u_char *pwHash,		/* IN  16 octets */
-	u_char *response	/* OUT 24 octets */
-)
-{
-	char    ZPasswordHash[21];
-	
-	BZERO(ZPasswordHash, sizeof(ZPasswordHash));
-	BCOPY(pwHash, ZPasswordHash, 16);
-	
-#if 0
-	log_packet(ZPasswordHash, sizeof(ZPasswordHash), "ChallengeResponse - ZPasswordHash", LOG_DEBUG);
-#endif
-	
-	DesEncrypt(challenge, ZPasswordHash +  0, response + 0);
-	DesEncrypt(challenge, ZPasswordHash +  7, response + 8);
-	DesEncrypt(challenge, ZPasswordHash + 14, response + 16);
-	
-#if 0
-	log_packet(response, 24, "ChallengeResponse - response", LOG_DEBUG);
-#endif
-}
-
-
-#ifdef USE_CRYPT
-static void DesEncrypt(
-	u_char *clear,	/* IN  8 octets */
-	u_char *key,	/* IN  7 octets */
-	u_char *cipher	/* OUT 8 octets */
-)
-{
-	u_char des_key[8];
-	u_char crypt_key[66];
-	u_char des_input[66];
-	
-	MakeKey(key, des_key);
-	
-	Expand(des_key, crypt_key);
-	setkey(crypt_key);
-	
-#if 0
-	CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet input : %02X%02X%02X%02X%02X%02X%02X%02X\n",
-	       clear[0], clear[1], clear[2], clear[3], clear[4], clear[5], clear[6], clear[7]));
-#endif
-	
-	Expand(clear, des_input);
-	encrypt(des_input, 0);
-	Collapse(des_input, cipher);
-	
-#if 0
-	CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet output: %02X%02X%02X%02X%02X%02X%02X%02X\n",
-	       cipher[0], cipher[1], cipher[2], cipher[3], cipher[4], cipher[5], cipher[6], cipher[7]));
-#endif
-}
-
-#else /* USE_CRYPT */
-
-static void DesEncrypt(
-	u_char *clear,	/* IN  8 octets */
-	u_char *key,	/* IN  7 octets */
-	u_char *cipher	/* OUT 8 octets */
-)
-{
-	des_cblock		des_key;
-	des_key_schedule	key_schedule;
-	
-	MakeKey(key, des_key);
-	
-	des_set_key(&des_key, key_schedule);
-	
-#if 0
-	CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet input : %02X%02X%02X%02X%02X%02X%02X%02X\n",
-	       clear[0], clear[1], clear[2], clear[3], clear[4], clear[5], clear[6], clear[7]));
-#endif
-	
-	des_ecb_encrypt((des_cblock *)clear, (des_cblock *)cipher, key_schedule, 1);
-	
-#if 0
-	CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet output: %02X%02X%02X%02X%02X%02X%02X%02X\n",
-	       cipher[0], cipher[1], cipher[2], cipher[3], cipher[4], cipher[5], cipher[6], cipher[7]));
-#endif
-}
-
-#endif /* USE_CRYPT */
-
-
-static u_char Get7Bits(
-	u_char *input,
-	int startBit
-)
-{
-	register unsigned int	word;
-	
-	word  = (unsigned)input[startBit / 8] << 8;
-	word |= (unsigned)input[startBit / 8 + 1];
-	
-	word >>= 15 - (startBit % 8 + 7);
-	
-	return word & 0xFE;
-}
-
-#ifdef USE_CRYPT
-
-/* in == 8-byte string (expanded version of the 56-bit key)
- * out == 64-byte string where each byte is either 1 or 0
- * Note that the low-order "bit" is always ignored by by setkey()
- */
-static void Expand(u_char *in, u_char *out)
-{
-	int j, c;
-	int i;
-	
-	for(i = 0; i < 64; in++){
-		c = *in;
-		for(j = 7; j >= 0; j--)
-			*out++ = (c >> j) & 01;
-		i += 8;
-	}
-}
-
-/* The inverse of Expand
- */
-static void Collapse(u_char *in, u_char *out)
-{
-	int j;
-	int i;
-	unsigned int c;
-	
-	for (i = 0; i < 64; i += 8, out++) {
-		c = 0;
-		for (j = 7; j >= 0; j--, in++)
-			c |= *in << j;
-		*out = c & 0xff;
-	}
-}
-#endif
-
-static void MakeKey(
-	u_char *key,		/* IN  56 bit DES key missing parity bits */
-	u_char *des_key		/* OUT 64 bit DES key with parity bits added */
-)
-{
-	des_key[0] = Get7Bits(key,  0);
-	des_key[1] = Get7Bits(key,  7);
-	des_key[2] = Get7Bits(key, 14);
-	des_key[3] = Get7Bits(key, 21);
-	des_key[4] = Get7Bits(key, 28);
-	des_key[5] = Get7Bits(key, 35);
-	des_key[6] = Get7Bits(key, 42);
-	des_key[7] = Get7Bits(key, 49);
-	
-#ifndef USE_CRYPT
-	des_set_odd_parity((des_cblock *)des_key);
-#endif
-	
-#if 0
-	CHAPDEBUG((LOG_INFO, "MakeKey: 56-bit input : %02X%02X%02X%02X%02X%02X%02X\n",
-	       key[0], key[1], key[2], key[3], key[4], key[5], key[6]));
-	CHAPDEBUG((LOG_INFO, "MakeKey: 64-bit output: %02X%02X%02X%02X%02X%02X%02X%02X\n",
-	       des_key[0], des_key[1], des_key[2], des_key[3], des_key[4], des_key[5], des_key[6], des_key[7]));
-#endif
-}
-
-static void ChapMS_NT(
-	char *rchallenge,
-	int rchallenge_len,
-	char *secret,
-	int secret_len,
-	MS_ChapResponse *response
-)
-{
-	int			i;
-	MDstruct	md4Context;
-	u_char		unicodePassword[MAX_NT_PASSWORD * 2];
-	static int	low_byte_first = -1;
-	
-	/* Initialize the Unicode version of the secret (== password). */
-	/* This implicitly supports 8-bit ISO8859/1 characters. */
-	BZERO(unicodePassword, sizeof(unicodePassword));
-	for (i = 0; i < secret_len; i++)
-		unicodePassword[i * 2] = (u_char)secret[i];
-	
-	MDbegin(&md4Context);
-	MDupdate(&md4Context, unicodePassword, secret_len * 2 * 8);	/* Unicode is 2 bytes/char, *8 for bit count */
-	
-	if (low_byte_first == -1)
-		low_byte_first = (htons((unsigned short int)1) != 1);
-	if (low_byte_first == 0)
-		MDreverse((u_long *)&md4Context);  /*  sfb 961105 */
-	
-	MDupdate(&md4Context, NULL, 0);	/* Tell MD4 we're done */
-	
-	ChallengeResponse(rchallenge, (char *)md4Context.buffer, response->NTResp);
-}
-
-#ifdef MSLANMAN
-static u_char *StdText = (u_char *)"KGS!@#$%"; /* key from rasapi32.dll */
-
-static ChapMS_LANMan(
-	char *rchallenge,
-	int rchallenge_len,
-	char *secret,
-	int secret_len,
-	MS_ChapResponse	*response
-)
-{
-	int			i;
-	u_char		UcasePassword[MAX_NT_PASSWORD]; /* max is actually 14 */
-	u_char		PasswordHash[16];
-	
-	/* LANMan password is case insensitive */
-	BZERO(UcasePassword, sizeof(UcasePassword));
-	for (i = 0; i < secret_len; i++)
-		UcasePassword[i] = (u_char)toupper(secret[i]);
-	DesEncrypt( StdText, UcasePassword + 0, PasswordHash + 0 );
-	DesEncrypt( StdText, UcasePassword + 7, PasswordHash + 8 );
-	ChallengeResponse(rchallenge, PasswordHash, response->LANManResp);
-}
-#endif
-
-#endif /* MSCHAP_SUPPORT */
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/chpms.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/chpms.h
deleted file mode 100644
index c58447215..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/chpms.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*****************************************************************************
-* chpms.h - Network Microsoft Challenge Handshake Protocol header file.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* portions Copyright (c) 1998 Global Election Systems Inc.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY
-*
-* 03-01-01 Marc Boucher 
-*   Ported to lwIP.
-* 98-01-30 Guy Lancaster , Global Election Systems Inc.
-*	Original built from BSD network code.
-******************************************************************************/
-/*
- * chap.h - Challenge Handshake Authentication Protocol definitions.
- *
- * Copyright (c) 1995 Eric Rosenquist, Strata Software Limited.
- * http://www.strataware.com/
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by Eric Rosenquist.  The name of the author may not be used to
- * endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- *
- * $Id: chpms.h,v 1.3 2004/02/07 00:30:03 likewise Exp $
- */
-
-#ifndef CHPMS_H
-#define CHPMS_H
-
-#define MAX_NT_PASSWORD	256	/* Maximum number of (Unicode) chars in an NT password */
-
-void ChapMS (chap_state *, char *, int, char *, int);
-
-#endif /* CHPMS_H */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/fsm.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/fsm.c
deleted file mode 100644
index fe8b38a93..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/fsm.c
+++ /dev/null
@@ -1,838 +0,0 @@
-/*****************************************************************************
-* fsm.c - Network Control Protocol Finite State Machine program file.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* portions Copyright (c) 1997 by Global Election Systems Inc.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY
-*
-* 03-01-01 Marc Boucher 
-*   Ported to lwIP.
-* 97-12-01 Guy Lancaster , Global Election Systems Inc.
-*	Original based on BSD fsm.c.
-*****************************************************************************/
-/*
- * fsm.c - {Link, IP} Control Protocol Finite State Machine.
- *
- * Copyright (c) 1989 Carnegie Mellon University.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by Carnegie Mellon University.  The name of the
- * University may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- */
-
-
-/*
- * TODO:
- * Randomize fsm id on link/init.
- * Deal with variable outgoing MTU.
- */
-
-#include "ppp.h"
-#if PPP_SUPPORT > 0
-#include "fsm.h"
-#include "pppdebug.h"
-
-
-/*************************/
-/*** LOCAL DEFINITIONS ***/
-/*************************/
-
-
-/************************/
-/*** LOCAL DATA TYPES ***/
-/************************/
-
-
-/***********************************/
-/*** LOCAL FUNCTION DECLARATIONS ***/
-/***********************************/
-static void fsm_timeout (void *);
-static void fsm_rconfreq (fsm *, u_char, u_char *, int);
-static void fsm_rconfack (fsm *, int, u_char *, int);
-static void fsm_rconfnakrej (fsm *, int, int, u_char *, int);
-static void fsm_rtermreq (fsm *, int, u_char *, int);
-static void fsm_rtermack (fsm *);
-static void fsm_rcoderej (fsm *, u_char *, int);
-static void fsm_sconfreq (fsm *, int);
-
-#define PROTO_NAME(f)	((f)->callbacks->proto_name)
-
-
-/******************************/
-/*** PUBLIC DATA STRUCTURES ***/
-/******************************/
-
-
-/*****************************/
-/*** LOCAL DATA STRUCTURES ***/
-/*****************************/
-int peer_mru[NUM_PPP];
-
-
-/***********************************/
-/*** PUBLIC FUNCTION DEFINITIONS ***/
-/***********************************/
-
-/*
- * fsm_init - Initialize fsm.
- *
- * Initialize fsm state.
- */
-void fsm_init(fsm *f)
-{
-	f->state = INITIAL;
-	f->flags = 0;
-	f->id = 0;				/* XXX Start with random id? */
-	f->timeouttime = FSM_DEFTIMEOUT;
-	f->maxconfreqtransmits = FSM_DEFMAXCONFREQS;
-	f->maxtermtransmits = FSM_DEFMAXTERMREQS;
-	f->maxnakloops = FSM_DEFMAXNAKLOOPS;
-	f->term_reason_len = 0;
-}
-
-
-/*
- * fsm_lowerup - The lower layer is up.
- */
-void fsm_lowerup(fsm *f)
-{
-	int oldState = f->state;
-
-	switch( f->state ){
-	case INITIAL:
-		f->state = CLOSED;
-		break;
-	
-	case STARTING:
-		if( f->flags & OPT_SILENT )
-			f->state = STOPPED;
-		else {
-			/* Send an initial configure-request */
-			fsm_sconfreq(f, 0);
-			f->state = REQSENT;
-		}
-	break;
-	
-	default:
-		FSMDEBUG((LOG_INFO, "%s: Up event in state %d!\n",
-				PROTO_NAME(f), f->state));
-	}
-	
-	FSMDEBUG((LOG_INFO, "%s: lowerup state %d -> %d\n",
-			PROTO_NAME(f), oldState, f->state));
-}
-
-
-/*
- * fsm_lowerdown - The lower layer is down.
- *
- * Cancel all timeouts and inform upper layers.
- */
-void fsm_lowerdown(fsm *f)
-{
-	int oldState = f->state;
-	
-	switch( f->state ){
-	case CLOSED:
-		f->state = INITIAL;
-		break;
-	
-	case STOPPED:
-		f->state = STARTING;
-		if( f->callbacks->starting )
-			(*f->callbacks->starting)(f);
-		break;
-	
-	case CLOSING:
-		f->state = INITIAL;
-		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
-		break;
-	
-	case STOPPING:
-	case REQSENT:
-	case ACKRCVD:
-	case ACKSENT:
-		f->state = STARTING;
-		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
-		break;
-	
-	case OPENED:
-		if( f->callbacks->down )
-			(*f->callbacks->down)(f);
-		f->state = STARTING;
-		break;
-	
-	default:
-		FSMDEBUG((LOG_INFO, "%s: Down event in state %d!\n",
-				PROTO_NAME(f), f->state));
-	}
-	
-	FSMDEBUG((LOG_INFO, "%s: lowerdown state %d -> %d\n",
-			PROTO_NAME(f), oldState, f->state));
-}
-
-
-/*
- * fsm_open - Link is allowed to come up.
- */
-void fsm_open(fsm *f)
-{
-	int oldState = f->state;
-	
-	switch( f->state ){
-		case INITIAL:
-			f->state = STARTING;
-			if( f->callbacks->starting )
-				(*f->callbacks->starting)(f);
-			break;
-		
-		case CLOSED:
-		if( f->flags & OPT_SILENT )
-			f->state = STOPPED;
-		else {
-			/* Send an initial configure-request */
-			fsm_sconfreq(f, 0);
-			f->state = REQSENT;
-		}
-		break;
-	
-	case CLOSING:
-		f->state = STOPPING;
-		/* fall through */
-	case STOPPED:
-	case OPENED:
-		if( f->flags & OPT_RESTART ){
-			fsm_lowerdown(f);
-			fsm_lowerup(f);
-		}
-		break;
-	}
-	
-	FSMDEBUG((LOG_INFO, "%s: open state %d -> %d\n",
-			PROTO_NAME(f), oldState, f->state));
-}
-
-
-/*
- * fsm_close - Start closing connection.
- *
- * Cancel timeouts and either initiate close or possibly go directly to
- * the CLOSED state.
- */
-void fsm_close(fsm *f, char *reason)
-{
-	int oldState = f->state;
-	
-	f->term_reason = reason;
-	f->term_reason_len = (reason == NULL? 0: strlen(reason));
-	switch( f->state ){
-	case STARTING:
-		f->state = INITIAL;
-		break;
-	case STOPPED:
-		f->state = CLOSED;
-		break;
-	case STOPPING:
-		f->state = CLOSING;
-		break;
-	
-	case REQSENT:
-	case ACKRCVD:
-	case ACKSENT:
-	case OPENED:
-		if( f->state != OPENED )
-			UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
-		else if( f->callbacks->down )
-			(*f->callbacks->down)(f);	/* Inform upper layers we're down */
-		
-		/* Init restart counter, send Terminate-Request */
-		f->retransmits = f->maxtermtransmits;
-		fsm_sdata(f, TERMREQ, f->reqid = ++f->id,
-					(u_char *) f->term_reason, f->term_reason_len);
-		TIMEOUT(fsm_timeout, f, f->timeouttime);
-		--f->retransmits;
-		
-		f->state = CLOSING;
-		break;
-	}
-	
-	FSMDEBUG((LOG_INFO, "%s: close reason=%s state %d -> %d\n",
-			PROTO_NAME(f), reason, oldState, f->state));
-}
-
-
-/*
- * fsm_sdata - Send some data.
- *
- * Used for all packets sent to our peer by this module.
- */
-void fsm_sdata(
-	fsm *f,
-	u_char code, 
-	u_char id,
-	u_char *data,
-	int datalen
-)
-{
-	u_char *outp;
-	int outlen;
-	
-	/* Adjust length to be smaller than MTU */
-	outp = outpacket_buf[f->unit];
-	if (datalen > peer_mru[f->unit] - (int)HEADERLEN)
-		datalen = peer_mru[f->unit] - HEADERLEN;
-	if (datalen && data != outp + PPP_HDRLEN + HEADERLEN)
-		BCOPY(data, outp + PPP_HDRLEN + HEADERLEN, datalen);
-	outlen = datalen + HEADERLEN;
-	MAKEHEADER(outp, f->protocol);
-	PUTCHAR(code, outp);
-	PUTCHAR(id, outp);
-	PUTSHORT(outlen, outp);
-	pppWrite(f->unit, outpacket_buf[f->unit], outlen + PPP_HDRLEN);
-	FSMDEBUG((LOG_INFO, "fsm_sdata(%s): Sent code %d,%d,%d.\n",
-				PROTO_NAME(f), code, id, outlen));
-}
-
-
-/*
- * fsm_input - Input packet.
- */
-void fsm_input(fsm *f, u_char *inpacket, int l)
-{
-	u_char *inp = inpacket;
-	u_char code, id;
-	int len;
-	
-	/*
-	* Parse header (code, id and length).
-	* If packet too short, drop it.
-	*/
-	if (l < HEADERLEN) {
-		FSMDEBUG((LOG_WARNING, "fsm_input(%x): Rcvd short header.\n",
-					f->protocol));
-		return;
-	}
-	GETCHAR(code, inp);
-	GETCHAR(id, inp);
-	GETSHORT(len, inp);
-	if (len < HEADERLEN) {
-		FSMDEBUG((LOG_INFO, "fsm_input(%x): Rcvd illegal length.\n",
-				f->protocol));
-		return;
-	}
-	if (len > l) {
-		FSMDEBUG((LOG_INFO, "fsm_input(%x): Rcvd short packet.\n",
-				f->protocol));
-		return;
-	}
-	len -= HEADERLEN;		/* subtract header length */
-	
-	if( f->state == INITIAL || f->state == STARTING ){
-		FSMDEBUG((LOG_INFO, "fsm_input(%x): Rcvd packet in state %d.\n",
-				f->protocol, f->state));
-		return;
-	}
-	FSMDEBUG((LOG_INFO, "fsm_input(%s):%d,%d,%d\n", PROTO_NAME(f), code, id, l));
-	/*
-	 * Action depends on code.
-	 */
-	switch (code) {
-	case CONFREQ:
-		fsm_rconfreq(f, id, inp, len);
-		break;
-	
-	case CONFACK:
-		fsm_rconfack(f, id, inp, len);
-		break;
-	
-	case CONFNAK:
-	case CONFREJ:
-		fsm_rconfnakrej(f, code, id, inp, len);
-		break;
-	
-	case TERMREQ:
-		fsm_rtermreq(f, id, inp, len);
-		break;
-	
-	case TERMACK:
-		fsm_rtermack(f);
-		break;
-	
-	case CODEREJ:
-		fsm_rcoderej(f, inp, len);
-		break;
-	
-	default:
-		if( !f->callbacks->extcode
-				|| !(*f->callbacks->extcode)(f, code, id, inp, len) )
-			fsm_sdata(f, CODEREJ, ++f->id, inpacket, len + HEADERLEN);
-		break;
-	}
-}
-
-
-/*
- * fsm_protreject - Peer doesn't speak this protocol.
- *
- * Treat this as a catastrophic error (RXJ-).
- */
-void fsm_protreject(fsm *f)
-{
-	switch( f->state ){
-	case CLOSING:
-		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
-		/* fall through */
-	case CLOSED:
-		f->state = CLOSED;
-		if( f->callbacks->finished )
-			(*f->callbacks->finished)(f);
-		break;
-	
-	case STOPPING:
-	case REQSENT:
-	case ACKRCVD:
-	case ACKSENT:
-		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
-		/* fall through */
-	case STOPPED:
-		f->state = STOPPED;
-		if( f->callbacks->finished )
-			(*f->callbacks->finished)(f);
-		break;
-	
-	case OPENED:
-		if( f->callbacks->down )
-			(*f->callbacks->down)(f);
-		
-		/* Init restart counter, send Terminate-Request */
-		f->retransmits = f->maxtermtransmits;
-		fsm_sdata(f, TERMREQ, f->reqid = ++f->id,
-					(u_char *) f->term_reason, f->term_reason_len);
-		TIMEOUT(fsm_timeout, f, f->timeouttime);
-		--f->retransmits;
-		
-		f->state = STOPPING;
-		break;
-	
-	default:
-		FSMDEBUG((LOG_INFO, "%s: Protocol-reject event in state %d!\n",
-					PROTO_NAME(f), f->state));
-	}
-}
-
-
-
-
-
-/**********************************/
-/*** LOCAL FUNCTION DEFINITIONS ***/
-/**********************************/
-
-/*
- * fsm_timeout - Timeout expired.
- */
-static void fsm_timeout(void *arg)
-{
-    fsm *f = (fsm *) arg;
-
-    switch (f->state) {
-    case CLOSING:
-    case STOPPING:
-		if( f->retransmits <= 0 ){
-		    FSMDEBUG((LOG_WARNING, "%s: timeout sending Terminate-Request state=%d\n",
-					   PROTO_NAME(f), f->state));
-		    /*
-		     * We've waited for an ack long enough.  Peer probably heard us.
-		     */
-		    f->state = (f->state == CLOSING)? CLOSED: STOPPED;
-		    if( f->callbacks->finished )
-			(*f->callbacks->finished)(f);
-		} else {
-		    FSMDEBUG((LOG_WARNING, "%s: timeout resending Terminate-Requests state=%d\n",
-					   PROTO_NAME(f), f->state));
-		    /* Send Terminate-Request */
-		    fsm_sdata(f, TERMREQ, f->reqid = ++f->id,
-			      (u_char *) f->term_reason, f->term_reason_len);
-		    TIMEOUT(fsm_timeout, f, f->timeouttime);
-		    --f->retransmits;
-		}
-		break;
-
-    case REQSENT:
-    case ACKRCVD:
-    case ACKSENT:
-		if (f->retransmits <= 0) {
-		    FSMDEBUG((LOG_WARNING, "%s: timeout sending Config-Requests state=%d\n",
-			   PROTO_NAME(f), f->state));
-		    f->state = STOPPED;
-		    if( (f->flags & OPT_PASSIVE) == 0 && f->callbacks->finished )
-				(*f->callbacks->finished)(f);
-	
-		} else {
-		    FSMDEBUG((LOG_WARNING, "%s: timeout resending Config-Request state=%d\n",
-			   PROTO_NAME(f), f->state));
-		    /* Retransmit the configure-request */
-		    if (f->callbacks->retransmit)
-				(*f->callbacks->retransmit)(f);
-		    fsm_sconfreq(f, 1);		/* Re-send Configure-Request */
-		    if( f->state == ACKRCVD )
-				f->state = REQSENT;
-		}
-		break;
-
-    default:
-		FSMDEBUG((LOG_INFO, "%s: Timeout event in state %d!\n",
-				  PROTO_NAME(f), f->state));
-	    }
-}
-
-
-/*
- * fsm_rconfreq - Receive Configure-Request.
- */
-static void fsm_rconfreq(fsm *f, u_char id, u_char *inp, int len)
-{
-	int code, reject_if_disagree;
-	
-	FSMDEBUG((LOG_INFO, "fsm_rconfreq(%s): Rcvd id %d state=%d\n", 
-				PROTO_NAME(f), id, f->state));
-	switch( f->state ){
-	case CLOSED:
-		/* Go away, we're closed */
-		fsm_sdata(f, TERMACK, id, NULL, 0);
-		return;
-	case CLOSING:
-	case STOPPING:
-		return;
-	
-	case OPENED:
-		/* Go down and restart negotiation */
-		if( f->callbacks->down )
-			(*f->callbacks->down)(f);	/* Inform upper layers */
-		fsm_sconfreq(f, 0);		/* Send initial Configure-Request */
-		break;
-	
-	case STOPPED:
-		/* Negotiation started by our peer */
-		fsm_sconfreq(f, 0);		/* Send initial Configure-Request */
-		f->state = REQSENT;
-		break;
-	}
-	
-	/*
-	* Pass the requested configuration options
-	* to protocol-specific code for checking.
-	*/
-	if (f->callbacks->reqci){		/* Check CI */
-		reject_if_disagree = (f->nakloops >= f->maxnakloops);
-		code = (*f->callbacks->reqci)(f, inp, &len, reject_if_disagree);
-	} 
-	else if (len)
-		code = CONFREJ;			/* Reject all CI */
-	else
-		code = CONFACK;
-	
-	/* send the Ack, Nak or Rej to the peer */
-	fsm_sdata(f, (u_char)code, id, inp, len);
-	
-	if (code == CONFACK) {
-		if (f->state == ACKRCVD) {
-			UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
-			f->state = OPENED;
-			if (f->callbacks->up)
-				(*f->callbacks->up)(f);	/* Inform upper layers */
-		} 
-		else
-			f->state = ACKSENT;
-		f->nakloops = 0;
-	} 
-	else {
-		/* we sent CONFACK or CONFREJ */
-		if (f->state != ACKRCVD)
-			f->state = REQSENT;
-		if( code == CONFNAK )
-			++f->nakloops;
-	}
-}
-
-
-/*
- * fsm_rconfack - Receive Configure-Ack.
- */
-static void fsm_rconfack(fsm *f, int id, u_char *inp, int len)
-{
-	FSMDEBUG((LOG_INFO, "fsm_rconfack(%s): Rcvd id %d state=%d\n",
-				PROTO_NAME(f), id, f->state));
-	
-	if (id != f->reqid || f->seen_ack)		/* Expected id? */
-		return;					/* Nope, toss... */
-	if( !(f->callbacks->ackci? (*f->callbacks->ackci)(f, inp, len):
-								(len == 0)) ){
-		/* Ack is bad - ignore it */
-		FSMDEBUG((LOG_INFO, "%s: received bad Ack (length %d)\n",
-					PROTO_NAME(f), len));
-		return;
-	}
-	f->seen_ack = 1;
-	
-	switch (f->state) {
-	case CLOSED:
-	case STOPPED:
-		fsm_sdata(f, TERMACK, (u_char)id, NULL, 0);
-		break;
-	
-	case REQSENT:
-		f->state = ACKRCVD;
-		f->retransmits = f->maxconfreqtransmits;
-		break;
-	
-	case ACKRCVD:
-		/* Huh? an extra valid Ack? oh well... */
-		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
-		fsm_sconfreq(f, 0);
-		f->state = REQSENT;
-		break;
-	
-	case ACKSENT:
-		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
-		f->state = OPENED;
-		f->retransmits = f->maxconfreqtransmits;
-		if (f->callbacks->up)
-			(*f->callbacks->up)(f);	/* Inform upper layers */
-		break;
-	
-	case OPENED:
-		/* Go down and restart negotiation */
-		if (f->callbacks->down)
-			(*f->callbacks->down)(f);	/* Inform upper layers */
-		fsm_sconfreq(f, 0);		/* Send initial Configure-Request */
-		f->state = REQSENT;
-		break;
-	}
-}
-
-
-/*
- * fsm_rconfnakrej - Receive Configure-Nak or Configure-Reject.
- */
-static void fsm_rconfnakrej(fsm *f, int code, int id, u_char *inp, int len)
-{
-	int (*proc) (fsm *, u_char *, int);
-	int ret;
-	
-	FSMDEBUG((LOG_INFO, "fsm_rconfnakrej(%s): Rcvd id %d state=%d\n",
-				PROTO_NAME(f), id, f->state));
-	
-	if (id != f->reqid || f->seen_ack)	/* Expected id? */
-		return;				/* Nope, toss... */
-	proc = (code == CONFNAK)? f->callbacks->nakci: f->callbacks->rejci;
-	if (!proc || !(ret = proc(f, inp, len))) {
-		/* Nak/reject is bad - ignore it */
-		FSMDEBUG((LOG_INFO, "%s: received bad %s (length %d)\n",
-					PROTO_NAME(f), (code==CONFNAK? "Nak": "reject"), len));
-		return;
-	}
-	f->seen_ack = 1;
-	
-	switch (f->state) {
-	case CLOSED:
-	case STOPPED:
-		fsm_sdata(f, TERMACK, (u_char)id, NULL, 0);
-		break;
-	
-	case REQSENT:
-	case ACKSENT:
-		/* They didn't agree to what we wanted - try another request */
-		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
-		if (ret < 0)
-			f->state = STOPPED;		/* kludge for stopping CCP */
-		else
-			fsm_sconfreq(f, 0);		/* Send Configure-Request */
-		break;
-	
-	case ACKRCVD:
-		/* Got a Nak/reject when we had already had an Ack?? oh well... */
-		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
-		fsm_sconfreq(f, 0);
-		f->state = REQSENT;
-		break;
-	
-	case OPENED:
-		/* Go down and restart negotiation */
-		if (f->callbacks->down)
-			(*f->callbacks->down)(f);	/* Inform upper layers */
-		fsm_sconfreq(f, 0);		/* Send initial Configure-Request */
-		f->state = REQSENT;
-		break;
-	}
-}
-
-
-/*
- * fsm_rtermreq - Receive Terminate-Req.
- */
-static void fsm_rtermreq(fsm *f, int id, u_char *p, int len)
-{
-	FSMDEBUG((LOG_INFO, "fsm_rtermreq(%s): Rcvd id %d state=%d\n",
-				PROTO_NAME(f), id, f->state));
-	
-	switch (f->state) {
-	case ACKRCVD:
-	case ACKSENT:
-		f->state = REQSENT;		/* Start over but keep trying */
-		break;
-	
-	case OPENED:
-		if (len > 0) {
-			FSMDEBUG((LOG_INFO, "%s terminated by peer (%x)\n", PROTO_NAME(f), p));
-		} else {
-			FSMDEBUG((LOG_INFO, "%s terminated by peer\n", PROTO_NAME(f)));
-		}
-		if (f->callbacks->down)
-			(*f->callbacks->down)(f);	/* Inform upper layers */
-		f->retransmits = 0;
-		f->state = STOPPING;
-		TIMEOUT(fsm_timeout, f, f->timeouttime);
-		break;
-	}
-	
-	fsm_sdata(f, TERMACK, (u_char)id, NULL, 0);
-}
-
-
-/*
- * fsm_rtermack - Receive Terminate-Ack.
- */
-static void fsm_rtermack(fsm *f)
-{
-	FSMDEBUG((LOG_INFO, "fsm_rtermack(%s): state=%d\n", 
-				PROTO_NAME(f), f->state));
-	
-	switch (f->state) {
-	case CLOSING:
-		UNTIMEOUT(fsm_timeout, f);
-		f->state = CLOSED;
-		if( f->callbacks->finished )
-			(*f->callbacks->finished)(f);
-		break;
-	case STOPPING:
-		UNTIMEOUT(fsm_timeout, f);
-		f->state = STOPPED;
-		if( f->callbacks->finished )
-			(*f->callbacks->finished)(f);
-		break;
-	
-	case ACKRCVD:
-		f->state = REQSENT;
-		break;
-	
-	case OPENED:
-		if (f->callbacks->down)
-			(*f->callbacks->down)(f);	/* Inform upper layers */
-		fsm_sconfreq(f, 0);
-		break;
-	}
-}
-
-
-/*
- * fsm_rcoderej - Receive an Code-Reject.
- */
-static void fsm_rcoderej(fsm *f, u_char *inp, int len)
-{
-	u_char code, id;
-	
-	FSMDEBUG((LOG_INFO, "fsm_rcoderej(%s): state=%d\n", 
-				PROTO_NAME(f), f->state));
-	
-	if (len < HEADERLEN) {
-		FSMDEBUG((LOG_INFO, "fsm_rcoderej: Rcvd short Code-Reject packet!\n"));
-		return;
-	}
-	GETCHAR(code, inp);
-	GETCHAR(id, inp);
-	FSMDEBUG((LOG_WARNING, "%s: Rcvd Code-Reject for code %d, id %d\n",
-				PROTO_NAME(f), code, id));
-	
-	if( f->state == ACKRCVD )
-		f->state = REQSENT;
-}
-
-
-/*
- * fsm_sconfreq - Send a Configure-Request.
- */
-static void fsm_sconfreq(fsm *f, int retransmit)
-{
-	u_char *outp;
-	int cilen;
-	
-	if( f->state != REQSENT && f->state != ACKRCVD && f->state != ACKSENT ){
-		/* Not currently negotiating - reset options */
-		if( f->callbacks->resetci )
-			(*f->callbacks->resetci)(f);
-		f->nakloops = 0;
-		}
-	
-	if( !retransmit ){
-		/* New request - reset retransmission counter, use new ID */
-		f->retransmits = f->maxconfreqtransmits;
-		f->reqid = ++f->id;
-	}
-	
-	f->seen_ack = 0;
-	
-	/*
-	 * Make up the request packet
-	 */
-	outp = outpacket_buf[f->unit] + PPP_HDRLEN + HEADERLEN;
-	if( f->callbacks->cilen && f->callbacks->addci ){
-		cilen = (*f->callbacks->cilen)(f);
-		if( cilen > peer_mru[f->unit] - (int)HEADERLEN )
-			cilen = peer_mru[f->unit] - HEADERLEN;
-		if (f->callbacks->addci)
-			(*f->callbacks->addci)(f, outp, &cilen);
-	} else
-		cilen = 0;
-	
-	/* send the request to our peer */
-	fsm_sdata(f, CONFREQ, f->reqid, outp, cilen);
-	
-	/* start the retransmit timer */
-	--f->retransmits;
-	TIMEOUT(fsm_timeout, f, f->timeouttime);
-	
-	FSMDEBUG((LOG_INFO, "%s: sending Configure-Request, id %d\n",
-				PROTO_NAME(f), f->reqid));
-}
-
-#endif /* PPP_SUPPORT */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/fsm.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/fsm.h
deleted file mode 100644
index 0e1d9f61a..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/fsm.h
+++ /dev/null
@@ -1,187 +0,0 @@
-/*****************************************************************************
-* fsm.h - Network Control Protocol Finite State Machine header file.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* Copyright (c) 1997 Global Election Systems Inc.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY
-*
-* 03-01-01 Marc Boucher 
-*   Ported to lwIP.
-* 97-11-05 Guy Lancaster , Global Election Systems Inc.
-*	Original based on BSD code.
-*****************************************************************************/
-/*
- * fsm.h - {Link, IP} Control Protocol Finite State Machine definitions.
- *
- * Copyright (c) 1989 Carnegie Mellon University.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by Carnegie Mellon University.  The name of the
- * University may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- *
- * $Id: fsm.h,v 1.1 2003/05/27 14:37:56 jani Exp $
- */
-
-#ifndef FSM_H
-#define FSM_H
-
-
-/*****************************************************************************
-************************* PUBLIC DEFINITIONS *********************************
-*****************************************************************************/
-/*
- * LCP Packet header = Code, id, length.
- */
-#define HEADERLEN	(sizeof (u_char) + sizeof (u_char) + sizeof (u_short))
-
-
-/*
- *  CP (LCP, IPCP, etc.) codes.
- */
-#define CONFREQ		1		/* Configuration Request */
-#define CONFACK		2		/* Configuration Ack */
-#define CONFNAK		3		/* Configuration Nak */
-#define CONFREJ		4		/* Configuration Reject */
-#define TERMREQ		5		/* Termination Request */
-#define TERMACK		6		/* Termination Ack */
-#define CODEREJ		7		/* Code Reject */
-
-/*
- * Link states.
- */
-#define INITIAL		0		/* Down, hasn't been opened */
-#define STARTING	1		/* Down, been opened */
-#define CLOSED		2		/* Up, hasn't been opened */
-#define STOPPED		3		/* Open, waiting for down event */
-#define CLOSING		4		/* Terminating the connection, not open */
-#define STOPPING	5		/* Terminating, but open */
-#define REQSENT		6		/* We've sent a Config Request */
-#define ACKRCVD		7		/* We've received a Config Ack */
-#define ACKSENT		8		/* We've sent a Config Ack */
-#define OPENED		9		/* Connection available */
-
-
-/*
- * Flags - indicate options controlling FSM operation
- */
-#define OPT_PASSIVE	1		/* Don't die if we don't get a response */
-#define OPT_RESTART	2		/* Treat 2nd OPEN as DOWN, UP */
-#define OPT_SILENT	4		/* Wait for peer to speak first */
-
-
-/*****************************************************************************
-************************* PUBLIC DATA TYPES **********************************
-*****************************************************************************/
-/*
- * Each FSM is described by an fsm structure and fsm callbacks.
- */
-typedef struct fsm {
-    int unit;				/* Interface unit number */
-    u_short protocol;		/* Data Link Layer Protocol field value */
-    int state;				/* State */
-    int flags;				/* Contains option bits */
-    u_char id;				/* Current id */
-    u_char reqid;			/* Current request id */
-    u_char seen_ack;		/* Have received valid Ack/Nak/Rej to Req */
-    int timeouttime;		/* Timeout time in milliseconds */
-    int maxconfreqtransmits;/* Maximum Configure-Request transmissions */
-    int retransmits;		/* Number of retransmissions left */
-    int maxtermtransmits;	/* Maximum Terminate-Request transmissions */
-    int nakloops;			/* Number of nak loops since last ack */
-    int maxnakloops;		/* Maximum number of nak loops tolerated */
-    struct fsm_callbacks* callbacks;/* Callback routines */
-    char* term_reason;		/* Reason for closing protocol */
-    int term_reason_len;	/* Length of term_reason */
-} fsm;
-
-
-typedef struct fsm_callbacks {
-    void (*resetci)			/* Reset our Configuration Information */
-		(fsm*);
-    int  (*cilen)			/* Length of our Configuration Information */
-		(fsm*);
-    void (*addci) 			/* Add our Configuration Information */
-		(fsm*, u_char*, int*);
-    int  (*ackci)			/* ACK our Configuration Information */
-		(fsm*, u_char*, int);
-    int  (*nakci)			/* NAK our Configuration Information */
-		(fsm*, u_char*, int);
-    int  (*rejci)			/* Reject our Configuration Information */
-		(fsm*, u_char*, int);
-    int  (*reqci)			/* Request peer's Configuration Information */
-		(fsm*, u_char*, int*, int);
-    void (*up)				/* Called when fsm reaches OPENED state */
-		(fsm*);
-    void (*down)			/* Called when fsm leaves OPENED state */
-		(fsm*);
-    void (*starting)		/* Called when we want the lower layer */
-		(fsm*);
-    void (*finished)		/* Called when we don't want the lower layer */
-		(fsm*);
-    void (*protreject)		/* Called when Protocol-Reject received */
-		(int);
-    void (*retransmit)		/* Retransmission is necessary */
-		(fsm*);
-    int  (*extcode)			/* Called when unknown code received */
-		(fsm*, int, u_char, u_char*, int);
-    char *proto_name;		/* String name for protocol (for messages) */
-} fsm_callbacks;
-
-
-/*****************************************************************************
-*********************** PUBLIC DATA STRUCTURES *******************************
-*****************************************************************************/
-/*
- * Variables
- */
-extern int peer_mru[];		/* currently negotiated peer MRU (per unit) */
-
-
-/*****************************************************************************
-************************** PUBLIC FUNCTIONS **********************************
-*****************************************************************************/
-
-/*
- * Prototypes
- */
-void fsm_init (fsm*);
-void fsm_lowerup (fsm*);
-void fsm_lowerdown (fsm*);
-void fsm_open (fsm*);
-void fsm_close (fsm*, char*);
-void fsm_input (fsm*, u_char*, int);
-void fsm_protreject (fsm*);
-void fsm_sdata (fsm*, u_char, u_char, u_char*, int);
-
-
-#endif /* FSM_H */
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/ipcp.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/ipcp.c
deleted file mode 100644
index d5b251880..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/ipcp.c
+++ /dev/null
@@ -1,1377 +0,0 @@
-/*****************************************************************************
-* ipcp.c - Network PPP IP Control Protocol program file.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* portions Copyright (c) 1997 by Global Election Systems Inc.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY
-*
-* 03-01-01 Marc Boucher 
-*   Ported to lwIP.
-* 97-12-08 Guy Lancaster , Global Election Systems Inc.
-*	Original.
-*****************************************************************************/
-/*
- * ipcp.c - PPP IP Control Protocol.
- *
- * Copyright (c) 1989 Carnegie Mellon University.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by Carnegie Mellon University.  The name of the
- * University may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- */
-
-#include 
-
-#include "ppp.h"
-#if PPP_SUPPORT > 0
-#include "auth.h"
-#include "fsm.h"
-#include "vj.h"
-#include "ipcp.h"
-#include "pppdebug.h"
-
-
-/*************************/
-/*** LOCAL DEFINITIONS ***/
-/*************************/
-/* #define OLD_CI_ADDRS 1 */	/* Support deprecated address negotiation. */
-
-/*
- * Lengths of configuration options.
- */
-#define CILEN_VOID	2
-#define CILEN_COMPRESS	4	/* min length for compression protocol opt. */
-#define CILEN_VJ	6	/* length for RFC1332 Van-Jacobson opt. */
-#define CILEN_ADDR	6	/* new-style single address option */
-#define CILEN_ADDRS	10	/* old-style dual address option */
-
-
-
-/***********************************/
-/*** LOCAL FUNCTION DECLARATIONS ***/
-/***********************************/
-/*
- * Callbacks for fsm code.  (CI = Configuration Information)
- */
-static void ipcp_resetci (fsm *);	/* Reset our CI */
-static int  ipcp_cilen (fsm *);	        /* Return length of our CI */
-static void ipcp_addci (fsm *, u_char *, int *); /* Add our CI */
-static int  ipcp_ackci (fsm *, u_char *, int);	/* Peer ack'd our CI */
-static int  ipcp_nakci (fsm *, u_char *, int);	/* Peer nak'd our CI */
-static int  ipcp_rejci (fsm *, u_char *, int);	/* Peer rej'd our CI */
-static int  ipcp_reqci (fsm *, u_char *, int *, int); /* Rcv CI */
-static void ipcp_up (fsm *);		/* We're UP */
-static void ipcp_down (fsm *);		/* We're DOWN */
-#if 0
-static void ipcp_script (fsm *, char *); /* Run an up/down script */
-#endif
-static void ipcp_finished (fsm *);	/* Don't need lower layer */
-
-/*
- * Protocol entry points from main code.
- */
-static void ipcp_init (int);
-static void ipcp_open (int);
-static void ipcp_close (int, char *);
-static void ipcp_lowerup (int);
-static void ipcp_lowerdown (int);
-static void ipcp_input (int, u_char *, int);
-static void ipcp_protrej (int);
-
-static void ipcp_clear_addrs (int);
-
-#define CODENAME(x)	((x) == CONFACK ? "ACK" : \
-			 (x) == CONFNAK ? "NAK" : "REJ")
-
-
-
-/******************************/
-/*** PUBLIC DATA STRUCTURES ***/
-/******************************/
-/* global vars */
-ipcp_options ipcp_wantoptions[NUM_PPP];	/* Options that we want to request */
-ipcp_options ipcp_gotoptions[NUM_PPP];	/* Options that peer ack'd */
-ipcp_options ipcp_allowoptions[NUM_PPP];	/* Options we allow peer to request */
-ipcp_options ipcp_hisoptions[NUM_PPP];	/* Options that we ack'd */
-
-fsm ipcp_fsm[NUM_PPP];		/* IPCP fsm structure */
-
-struct protent ipcp_protent = {
-    PPP_IPCP,
-    ipcp_init,
-    ipcp_input,
-    ipcp_protrej,
-    ipcp_lowerup,
-    ipcp_lowerdown,
-    ipcp_open,
-    ipcp_close,
-#if 0
-    ipcp_printpkt,
-    NULL,
-#endif
-    1,
-    "IPCP",
-#if 0
-    ip_check_options,
-    NULL,
-    ip_active_pkt
-#endif
-};
-
-
-
-/*****************************/
-/*** LOCAL DATA STRUCTURES ***/
-/*****************************/
-/* local vars */
-static int cis_received[NUM_PPP];		/* # Conf-Reqs received */
-static int default_route_set[NUM_PPP];	/* Have set up a default route */
-
-static fsm_callbacks ipcp_callbacks = { /* IPCP callback routines */
-    ipcp_resetci,		/* Reset our Configuration Information */
-    ipcp_cilen,			/* Length of our Configuration Information */
-    ipcp_addci,			/* Add our Configuration Information */
-    ipcp_ackci,			/* ACK our Configuration Information */
-    ipcp_nakci,			/* NAK our Configuration Information */
-    ipcp_rejci,			/* Reject our Configuration Information */
-    ipcp_reqci,			/* Request peer's Configuration Information */
-    ipcp_up,			/* Called when fsm reaches OPENED state */
-    ipcp_down,			/* Called when fsm leaves OPENED state */
-    NULL,				/* Called when we want the lower layer up */
-    ipcp_finished,		/* Called when we want the lower layer down */
-    NULL,				/* Called when Protocol-Reject received */
-    NULL,				/* Retransmission is necessary */
-    NULL,				/* Called to handle protocol-specific codes */
-    "IPCP"				/* String name of protocol */
-};
-
-
-
-/**********************************/
-/*** LOCAL FUNCTION DEFINITIONS ***/
-/**********************************/
-
-/*
- * Non-standard inet_ntoa left here for compat with original ppp
- * sources. Assumes u32_t instead of struct in_addr.
- */ 
-
-char * _inet_ntoa(u32_t n)
-{
-	struct in_addr ia;
-	ia.s_addr = n;
-	return inet_ntoa(ia);
-}
-
-#define inet_ntoa _inet_ntoa
-
-/*
- * ipcp_init - Initialize IPCP.
- */
-static void ipcp_init(int unit)
-{
-	fsm *f = &ipcp_fsm[unit];
-	ipcp_options *wo = &ipcp_wantoptions[unit];
-	ipcp_options *ao = &ipcp_allowoptions[unit];
-	
-	f->unit = unit;
-	f->protocol = PPP_IPCP;
-	f->callbacks = &ipcp_callbacks;
-	fsm_init(&ipcp_fsm[unit]);
-	
-	memset(wo, 0, sizeof(*wo));
-	memset(ao, 0, sizeof(*ao));
-	
-	wo->neg_addr = 1;
-	wo->ouraddr = 0;
-#if VJ_SUPPORT > 0
-	wo->neg_vj = 1;
-#else
-	wo->neg_vj = 0;
-#endif
-	wo->vj_protocol = IPCP_VJ_COMP;
-	wo->maxslotindex = MAX_SLOTS - 1;
-	wo->cflag = 0;
-	
-	wo->default_route = 1;
-	
-	ao->neg_addr = 1;
-#if VJ_SUPPORT > 0
-	ao->neg_vj = 1;
-#else
-	ao->neg_vj = 0;
-#endif
-	ao->maxslotindex = MAX_SLOTS - 1;
-	ao->cflag = 1;
-	
-	ao->default_route = 1;
-}
-
-
-/*
- * ipcp_open - IPCP is allowed to come up.
- */
-static void ipcp_open(int unit)
-{
-	fsm_open(&ipcp_fsm[unit]);
-}
-
-
-/*
- * ipcp_close - Take IPCP down.
- */
-static void ipcp_close(int unit, char *reason)
-{
-	fsm_close(&ipcp_fsm[unit], reason);
-}
-
-
-/*
- * ipcp_lowerup - The lower layer is up.
- */
-static void ipcp_lowerup(int unit)
-{
-	fsm_lowerup(&ipcp_fsm[unit]);
-}
-
-
-/*
- * ipcp_lowerdown - The lower layer is down.
- */
-static void ipcp_lowerdown(int unit)
-{
-	fsm_lowerdown(&ipcp_fsm[unit]);
-}
-
-
-/*
- * ipcp_input - Input IPCP packet.
- */
-static void ipcp_input(int unit, u_char *p, int len)
-{
-	fsm_input(&ipcp_fsm[unit], p, len);
-}
-
-
-/*
- * ipcp_protrej - A Protocol-Reject was received for IPCP.
- *
- * Pretend the lower layer went down, so we shut up.
- */
-static void ipcp_protrej(int unit)
-{
-	fsm_lowerdown(&ipcp_fsm[unit]);
-}
-
-
-/*
- * ipcp_resetci - Reset our CI.
- */
-static void ipcp_resetci(fsm *f)
-{
-	ipcp_options *wo = &ipcp_wantoptions[f->unit];
-	
-	wo->req_addr = wo->neg_addr && ipcp_allowoptions[f->unit].neg_addr;
-	if (wo->ouraddr == 0)
-		wo->accept_local = 1;
-	if (wo->hisaddr == 0)
-		wo->accept_remote = 1;
-	/* Request DNS addresses from the peer */
-	wo->req_dns1 = ppp_settings.usepeerdns;
-	wo->req_dns2 = ppp_settings.usepeerdns;
-	ipcp_gotoptions[f->unit] = *wo;
-	cis_received[f->unit] = 0;
-}
-
-
-/*
- * ipcp_cilen - Return length of our CI.
- */
-static int ipcp_cilen(fsm *f)
-{
-	ipcp_options *go = &ipcp_gotoptions[f->unit];
-	ipcp_options *wo = &ipcp_wantoptions[f->unit];
-	ipcp_options *ho = &ipcp_hisoptions[f->unit];
-	
-#define LENCIVJ(neg, old)	(neg ? (old? CILEN_COMPRESS : CILEN_VJ) : 0)
-#define LENCIADDR(neg, old)	(neg ? (old? CILEN_ADDRS : CILEN_ADDR) : 0)
-#define LENCIDNS(neg)		(neg ? (CILEN_ADDR) : 0)
-	
-	/*
-	 * First see if we want to change our options to the old
-	 * forms because we have received old forms from the peer.
-	 */
-	if (wo->neg_addr && !go->neg_addr && !go->old_addrs) {
-		/* use the old style of address negotiation */
-		go->neg_addr = 1;
-		go->old_addrs = 1;
-	}
-	if (wo->neg_vj && !go->neg_vj && !go->old_vj) {
-		/* try an older style of VJ negotiation */
-		if (cis_received[f->unit] == 0) {
-			/* keep trying the new style until we see some CI from the peer */
-			go->neg_vj = 1;
-		} else {
-			/* use the old style only if the peer did */
-			if (ho->neg_vj && ho->old_vj) {
-				go->neg_vj = 1;
-				go->old_vj = 1;
-				go->vj_protocol = ho->vj_protocol;
-			}
-		}
-	}
-	
-	return (LENCIADDR(go->neg_addr, go->old_addrs)
-			+ LENCIVJ(go->neg_vj, go->old_vj) +
-			LENCIDNS(go->req_dns1) +
-			LENCIDNS(go->req_dns2));
-}
-
-
-/*
- * ipcp_addci - Add our desired CIs to a packet.
- */
-static void ipcp_addci(fsm *f, u_char *ucp, int *lenp)
-{
-	ipcp_options *go = &ipcp_gotoptions[f->unit];
-	int len = *lenp;
-	
-#define ADDCIVJ(opt, neg, val, old, maxslotindex, cflag) \
-	if (neg) { \
-		int vjlen = old? CILEN_COMPRESS : CILEN_VJ; \
-		if (len >= vjlen) { \
-			PUTCHAR(opt, ucp); \
-			PUTCHAR(vjlen, ucp); \
-			PUTSHORT(val, ucp); \
-			if (!old) { \
-				PUTCHAR(maxslotindex, ucp); \
-				PUTCHAR(cflag, ucp); \
-			} \
-			len -= vjlen; \
-		} else \
-			neg = 0; \
-	}
-	
-#define ADDCIADDR(opt, neg, old, val1, val2) \
-	if (neg) { \
-		int addrlen = (old? CILEN_ADDRS: CILEN_ADDR); \
-		if (len >= addrlen) { \
-			u32_t l; \
-			PUTCHAR(opt, ucp); \
-			PUTCHAR(addrlen, ucp); \
-			l = ntohl(val1); \
-			PUTLONG(l, ucp); \
-			if (old) { \
-				l = ntohl(val2); \
-				PUTLONG(l, ucp); \
-			} \
-			len -= addrlen; \
-		} else \
-			neg = 0; \
-	}
-
-#define ADDCIDNS(opt, neg, addr) \
-	if (neg) { \
-		if (len >= CILEN_ADDR) { \
-			u32_t l; \
-			PUTCHAR(opt, ucp); \
-			PUTCHAR(CILEN_ADDR, ucp); \
-			l = ntohl(addr); \
-			PUTLONG(l, ucp); \
-			len -= CILEN_ADDR; \
-		} else \
-			neg = 0; \
-	}
-	
-	ADDCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), go->neg_addr,
-			  go->old_addrs, go->ouraddr, go->hisaddr);
-	
-	ADDCIVJ(CI_COMPRESSTYPE, go->neg_vj, go->vj_protocol, go->old_vj,
-			go->maxslotindex, go->cflag);
-	
-	ADDCIDNS(CI_MS_DNS1, go->req_dns1, go->dnsaddr[0]);
-
-	ADDCIDNS(CI_MS_DNS2, go->req_dns2, go->dnsaddr[1]);
-
-	*lenp -= len;
-}
-
-
-/*
- * ipcp_ackci - Ack our CIs.
- *
- * Returns:
- *	0 - Ack was bad.
- *	1 - Ack was good.
- */
-static int ipcp_ackci(fsm *f, u_char *p, int len)
-{
-	ipcp_options *go = &ipcp_gotoptions[f->unit];
-	u_short cilen, citype, cishort;
-	u32_t cilong;
-	u_char cimaxslotindex, cicflag;
-	
-	/*
-	 * CIs must be in exactly the same order that we sent...
-	 * Check packet length and CI length at each step.
-	 * If we find any deviations, then this packet is bad.
-	 */
-	
-#define ACKCIVJ(opt, neg, val, old, maxslotindex, cflag) \
-	if (neg) { \
-		int vjlen = old? CILEN_COMPRESS : CILEN_VJ; \
-		if ((len -= vjlen) < 0) \
-			goto bad; \
-		GETCHAR(citype, p); \
-		GETCHAR(cilen, p); \
-		if (cilen != vjlen || \
-				citype != opt)  \
-			goto bad; \
-		GETSHORT(cishort, p); \
-		if (cishort != val) \
-			goto bad; \
-		if (!old) { \
-			GETCHAR(cimaxslotindex, p); \
-			if (cimaxslotindex != maxslotindex) \
-				goto bad; \
-			GETCHAR(cicflag, p); \
-			if (cicflag != cflag) \
-				goto bad; \
-		} \
-	}
-	
-#define ACKCIADDR(opt, neg, old, val1, val2) \
-	if (neg) { \
-		int addrlen = (old? CILEN_ADDRS: CILEN_ADDR); \
-		u32_t l; \
-		if ((len -= addrlen) < 0) \
-			goto bad; \
-		GETCHAR(citype, p); \
-		GETCHAR(cilen, p); \
-		if (cilen != addrlen || \
-				citype != opt) \
-			goto bad; \
-		GETLONG(l, p); \
-		cilong = htonl(l); \
-		if (val1 != cilong) \
-			goto bad; \
-		if (old) { \
-			GETLONG(l, p); \
-			cilong = htonl(l); \
-			if (val2 != cilong) \
-				goto bad; \
-		} \
-	}
-
-#define ACKCIDNS(opt, neg, addr) \
-	if (neg) { \
-		u32_t l; \
-		if ((len -= CILEN_ADDR) < 0) \
-			goto bad; \
-		GETCHAR(citype, p); \
-		GETCHAR(cilen, p); \
-		if (cilen != CILEN_ADDR || \
-				citype != opt) \
-			goto bad; \
-		GETLONG(l, p); \
-		cilong = htonl(l); \
-		if (addr != cilong) \
-			goto bad; \
-	}
-	
-	ACKCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), go->neg_addr,
-			  go->old_addrs, go->ouraddr, go->hisaddr);
-	
-	ACKCIVJ(CI_COMPRESSTYPE, go->neg_vj, go->vj_protocol, go->old_vj,
-			go->maxslotindex, go->cflag);
-	
-	ACKCIDNS(CI_MS_DNS1, go->req_dns1, go->dnsaddr[0]);
-
-	ACKCIDNS(CI_MS_DNS2, go->req_dns2, go->dnsaddr[1]);
-
-	/*
-	 * If there are any remaining CIs, then this packet is bad.
-	 */
-	if (len != 0)
-		goto bad;
-	return (1);
-	
-bad:
-	IPCPDEBUG((LOG_INFO, "ipcp_ackci: received bad Ack!\n"));
-	return (0);
-}
-
-/*
- * ipcp_nakci - Peer has sent a NAK for some of our CIs.
- * This should not modify any state if the Nak is bad
- * or if IPCP is in the OPENED state.
- *
- * Returns:
- *	0 - Nak was bad.
- *	1 - Nak was good.
- */
-static int ipcp_nakci(fsm *f, u_char *p, int len)
-{
-	ipcp_options *go = &ipcp_gotoptions[f->unit];
-	u_char cimaxslotindex, cicflag;
-	u_char citype, cilen, *next;
-	u_short cishort;
-	u32_t ciaddr1, ciaddr2, l, cidnsaddr;
-	ipcp_options no;		/* options we've seen Naks for */
-	ipcp_options try;		/* options to request next time */
-	
-	BZERO(&no, sizeof(no));
-	try = *go;
-	
-	/*
-	 * Any Nak'd CIs must be in exactly the same order that we sent.
-	 * Check packet length and CI length at each step.
-	 * If we find any deviations, then this packet is bad.
-	 */
-#define NAKCIADDR(opt, neg, old, code) \
-	if (go->neg && \
-			len >= (cilen = (old? CILEN_ADDRS: CILEN_ADDR)) && \
-			p[1] == cilen && \
-			p[0] == opt) { \
-		len -= cilen; \
-		INCPTR(2, p); \
-		GETLONG(l, p); \
-		ciaddr1 = htonl(l); \
-		if (old) { \
-			GETLONG(l, p); \
-			ciaddr2 = htonl(l); \
-			no.old_addrs = 1; \
-		} else \
-			ciaddr2 = 0; \
-		no.neg = 1; \
-		code \
-	}
-	
-#define NAKCIVJ(opt, neg, code) \
-	if (go->neg && \
-			((cilen = p[1]) == CILEN_COMPRESS || cilen == CILEN_VJ) && \
-			len >= cilen && \
-			p[0] == opt) { \
-		len -= cilen; \
-		INCPTR(2, p); \
-		GETSHORT(cishort, p); \
-		no.neg = 1; \
-		code \
-	}
-	
-#define NAKCIDNS(opt, neg, code) \
-	if (go->neg && \
-			((cilen = p[1]) == CILEN_ADDR) && \
-			len >= cilen && \
-			p[0] == opt) { \
-		len -= cilen; \
-		INCPTR(2, p); \
-		GETLONG(l, p); \
-		cidnsaddr = htonl(l); \
-		no.neg = 1; \
-		code \
-	}
-	
-	/*
-	 * Accept the peer's idea of {our,his} address, if different
-	 * from our idea, only if the accept_{local,remote} flag is set.
-	 */
-	NAKCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), neg_addr, go->old_addrs,
-	  if (go->accept_local && ciaddr1) { /* Do we know our address? */
-		  try.ouraddr = ciaddr1;
-		  IPCPDEBUG((LOG_INFO, "local IP address %s\n",
-			     inet_ntoa(ciaddr1)));
-	  }
-	  if (go->accept_remote && ciaddr2) { /* Does he know his? */
-		  try.hisaddr = ciaddr2;
-		  IPCPDEBUG((LOG_INFO, "remote IP address %s\n",
-			     inet_ntoa(ciaddr2)));
-	  }
-	);
-	
-	/*
-	 * Accept the peer's value of maxslotindex provided that it
-	 * is less than what we asked for.  Turn off slot-ID compression
-	 * if the peer wants.  Send old-style compress-type option if
-	 * the peer wants.
-	 */
-	NAKCIVJ(CI_COMPRESSTYPE, neg_vj,
-		if (cilen == CILEN_VJ) {
-			GETCHAR(cimaxslotindex, p);
-			GETCHAR(cicflag, p);
-			if (cishort == IPCP_VJ_COMP) {
-				try.old_vj = 0;
-				if (cimaxslotindex < go->maxslotindex)
-					try.maxslotindex = cimaxslotindex;
-				if (!cicflag)
-					try.cflag = 0;
-			} else {
-				try.neg_vj = 0;
-			}
-		} else {
-			if (cishort == IPCP_VJ_COMP || cishort == IPCP_VJ_COMP_OLD) {
-				try.old_vj = 1;
-				try.vj_protocol = cishort;
-			} else {
-				try.neg_vj = 0;
-			}
-		}
-	);
-	
-	NAKCIDNS(CI_MS_DNS1, req_dns1,
-			try.dnsaddr[0] = cidnsaddr;
-		  	IPCPDEBUG((LOG_INFO, "primary DNS address %s\n", inet_ntoa(cidnsaddr)));
-			);
-
-	NAKCIDNS(CI_MS_DNS2, req_dns2,
-			try.dnsaddr[1] = cidnsaddr;
-		  	IPCPDEBUG((LOG_INFO, "secondary DNS address %s\n", inet_ntoa(cidnsaddr)));
-			);
-
-	/*
-	* There may be remaining CIs, if the peer is requesting negotiation
-	* on an option that we didn't include in our request packet.
-	* If they want to negotiate about IP addresses, we comply.
-	* If they want us to ask for compression, we refuse.
-	*/
-	while (len > CILEN_VOID) {
-		GETCHAR(citype, p);
-		GETCHAR(cilen, p);
-		if( (len -= cilen) < 0 )
-			goto bad;
-		next = p + cilen - 2;
-		
-		switch (citype) {
-		case CI_COMPRESSTYPE:
-			if (go->neg_vj || no.neg_vj ||
-					(cilen != CILEN_VJ && cilen != CILEN_COMPRESS))
-				goto bad;
-			no.neg_vj = 1;
-			break;
-		case CI_ADDRS:
-			if ((go->neg_addr && go->old_addrs) || no.old_addrs
-					|| cilen != CILEN_ADDRS)
-				goto bad;
-			try.neg_addr = 1;
-			try.old_addrs = 1;
-			GETLONG(l, p);
-			ciaddr1 = htonl(l);
-			if (ciaddr1 && go->accept_local)
-				try.ouraddr = ciaddr1;
-			GETLONG(l, p);
-			ciaddr2 = htonl(l);
-			if (ciaddr2 && go->accept_remote)
-				try.hisaddr = ciaddr2;
-			no.old_addrs = 1;
-			break;
-		case CI_ADDR:
-			if (go->neg_addr || no.neg_addr || cilen != CILEN_ADDR)
-				goto bad;
-			try.old_addrs = 0;
-			GETLONG(l, p);
-			ciaddr1 = htonl(l);
-			if (ciaddr1 && go->accept_local)
-				try.ouraddr = ciaddr1;
-			if (try.ouraddr != 0)
-				try.neg_addr = 1;
-			no.neg_addr = 1;
-			break;
-		}
-		p = next;
-	}
-	
-	/* If there is still anything left, this packet is bad. */
-	if (len != 0)
-		goto bad;
-	
-	/*
-	 * OK, the Nak is good.  Now we can update state.
-	 */
-	if (f->state != OPENED)
-		*go = try;
-	
-	return 1;
-	
-bad:
-	IPCPDEBUG((LOG_INFO, "ipcp_nakci: received bad Nak!\n"));
-	return 0;
-}
-
-
-/*
- * ipcp_rejci - Reject some of our CIs.
- */
-static int ipcp_rejci(fsm *f, u_char *p, int len)
-{
-	ipcp_options *go = &ipcp_gotoptions[f->unit];
-	u_char cimaxslotindex, ciflag, cilen;
-	u_short cishort;
-	u32_t cilong;
-	ipcp_options try;		/* options to request next time */
-	
-	try = *go;
-	/*
-	 * Any Rejected CIs must be in exactly the same order that we sent.
-	 * Check packet length and CI length at each step.
-	 * If we find any deviations, then this packet is bad.
-	 */
-#define REJCIADDR(opt, neg, old, val1, val2) \
-	if (go->neg && \
-			len >= (cilen = old? CILEN_ADDRS: CILEN_ADDR) && \
-			p[1] == cilen && \
-			p[0] == opt) { \
-		u32_t l; \
-		len -= cilen; \
-		INCPTR(2, p); \
-		GETLONG(l, p); \
-		cilong = htonl(l); \
-		/* Check rejected value. */ \
-		if (cilong != val1) \
-			goto bad; \
-		if (old) { \
-			GETLONG(l, p); \
-			cilong = htonl(l); \
-			/* Check rejected value. */ \
-			if (cilong != val2) \
-				goto bad; \
-		} \
-		try.neg = 0; \
-	}
-	
-#define REJCIVJ(opt, neg, val, old, maxslot, cflag) \
-	if (go->neg && \
-			p[1] == (old? CILEN_COMPRESS : CILEN_VJ) && \
-			len >= p[1] && \
-			p[0] == opt) { \
-		len -= p[1]; \
-		INCPTR(2, p); \
-		GETSHORT(cishort, p); \
-		/* Check rejected value. */  \
-		if (cishort != val) \
-			goto bad; \
-		if (!old) { \
-			GETCHAR(cimaxslotindex, p); \
-			if (cimaxslotindex != maxslot) \
-				goto bad; \
-			GETCHAR(ciflag, p); \
-			if (ciflag != cflag) \
-				goto bad; \
-		} \
-		try.neg = 0; \
-	}
-	
-#define REJCIDNS(opt, neg, dnsaddr) \
-	if (go->neg && \
-			((cilen = p[1]) == CILEN_ADDR) && \
-			len >= cilen && \
-			p[0] == opt) { \
-		u32_t l; \
-		len -= cilen; \
-		INCPTR(2, p); \
-		GETLONG(l, p); \
-		cilong = htonl(l); \
-		/* Check rejected value. */ \
-		if (cilong != dnsaddr) \
-			goto bad; \
-		try.neg = 0; \
-	}
-
-	REJCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), neg_addr,
-			  go->old_addrs, go->ouraddr, go->hisaddr);
-	
-	REJCIVJ(CI_COMPRESSTYPE, neg_vj, go->vj_protocol, go->old_vj,
-			go->maxslotindex, go->cflag);
-	
-	REJCIDNS(CI_MS_DNS1, req_dns1, go->dnsaddr[0]);
-
-	REJCIDNS(CI_MS_DNS2, req_dns2, go->dnsaddr[1]);
-
-	/*
-	 * If there are any remaining CIs, then this packet is bad.
-	 */
-	if (len != 0)
-		goto bad;
-	/*
-	 * Now we can update state.
-	 */
-	if (f->state != OPENED)
-		*go = try;
-	return 1;
-	
-bad:
-	IPCPDEBUG((LOG_INFO, "ipcp_rejci: received bad Reject!\n"));
-	return 0;
-}
-
-
-/*
- * ipcp_reqci - Check the peer's requested CIs and send appropriate response.
- *
- * Returns: CONFACK, CONFNAK or CONFREJ and input packet modified
- * appropriately.  If reject_if_disagree is non-zero, doesn't return
- * CONFNAK; returns CONFREJ if it can't return CONFACK.
- */
-static int ipcp_reqci(
-	fsm *f,
-	u_char *inp,		/* Requested CIs */
-	int *len,			/* Length of requested CIs */
-	int reject_if_disagree
-)
-{
-	ipcp_options *wo = &ipcp_wantoptions[f->unit];
-	ipcp_options *ho = &ipcp_hisoptions[f->unit];
-	ipcp_options *ao = &ipcp_allowoptions[f->unit];
-#ifdef OLD_CI_ADDRS
-	ipcp_options *go = &ipcp_gotoptions[f->unit];
-#endif
-	u_char *cip, *next;				/* Pointer to current and next CIs */
-	u_short cilen, citype;			/* Parsed len, type */
-	u_short cishort;				/* Parsed short value */
-	u32_t tl, ciaddr1;			/* Parsed address values */
-#ifdef OLD_CI_ADDRS
-	u32_t ciaddr2;				/* Parsed address values */
-#endif
-	int rc = CONFACK;				/* Final packet return code */
-	int orc;						/* Individual option return code */
-	u_char *p;						/* Pointer to next char to parse */
-	u_char *ucp = inp;				/* Pointer to current output char */
-	int l = *len;					/* Length left */
-	u_char maxslotindex, cflag;
-	int d;
-	
-	cis_received[f->unit] = 1;
-	
-	/*
-	 * Reset all his options.
-	 */
-	BZERO(ho, sizeof(*ho));
-	
-	/*
-	 * Process all his options.
-	 */
-	next = inp;
-	while (l) {
-		orc = CONFACK;				/* Assume success */
-		cip = p = next;				/* Remember begining of CI */
-		if (l < 2 ||				/* Not enough data for CI header or */
-				p[1] < 2 ||			/*  CI length too small or */
-				p[1] > l) {			/*  CI length too big? */
-			IPCPDEBUG((LOG_INFO, "ipcp_reqci: bad CI length!\n"));
-			orc = CONFREJ;			/* Reject bad CI */
-			cilen = l;				/* Reject till end of packet */
-			l = 0;					/* Don't loop again */
-			goto endswitch;
-		}
-		GETCHAR(citype, p);			/* Parse CI type */
-		GETCHAR(cilen, p);			/* Parse CI length */
-		l -= cilen;					/* Adjust remaining length */
-		next += cilen;				/* Step to next CI */
-
-		switch (citype) {			/* Check CI type */
-#ifdef OLD_CI_ADDRS /* Need to save space... */
-		case CI_ADDRS:
-			IPCPDEBUG((LOG_INFO, "ipcp_reqci: received ADDRS\n"));
-			if (!ao->neg_addr ||
-					cilen != CILEN_ADDRS) {	/* Check CI length */
-				orc = CONFREJ;		/* Reject CI */
-				break;
-			}
-			
-			/*
-			 * If he has no address, or if we both have his address but
-			 * disagree about it, then NAK it with our idea.
-			 * In particular, if we don't know his address, but he does,
-			 * then accept it.
-			 */
-			GETLONG(tl, p);		/* Parse source address (his) */
-			ciaddr1 = htonl(tl);
-			IPCPDEBUG((LOG_INFO, "his addr %s\n", inet_ntoa(ciaddr1)));
-			if (ciaddr1 != wo->hisaddr
-					&& (ciaddr1 == 0 || !wo->accept_remote)) {
-				orc = CONFNAK;
-				if (!reject_if_disagree) {
-					DECPTR(sizeof(u32_t), p);
-					tl = ntohl(wo->hisaddr);
-					PUTLONG(tl, p);
-				}
-			} else if (ciaddr1 == 0 && wo->hisaddr == 0) {
-				/*
-				 * If neither we nor he knows his address, reject the option.
-				 */
-				orc = CONFREJ;
-				wo->req_addr = 0;	/* don't NAK with 0.0.0.0 later */
-				break;
-			}
-			
-			/*
-			 * If he doesn't know our address, or if we both have our address
-			 * but disagree about it, then NAK it with our idea.
-			 */
-			GETLONG(tl, p);		/* Parse desination address (ours) */
-			ciaddr2 = htonl(tl);
-			IPCPDEBUG((LOG_INFO, "our addr %s\n", inet_ntoa(ciaddr2)));
-			if (ciaddr2 != wo->ouraddr) {
-				if (ciaddr2 == 0 || !wo->accept_local) {
-					orc = CONFNAK;
-					if (!reject_if_disagree) {
-						DECPTR(sizeof(u32_t), p);
-						tl = ntohl(wo->ouraddr);
-						PUTLONG(tl, p);
-					}
-				} else {
-					go->ouraddr = ciaddr2;	/* accept peer's idea */
-				}
-			}
-			
-			ho->neg_addr = 1;
-			ho->old_addrs = 1;
-			ho->hisaddr = ciaddr1;
-			ho->ouraddr = ciaddr2;
-			break;
-#endif
-		
-		case CI_ADDR:
-			if (!ao->neg_addr) {
-				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Reject ADDR not allowed\n"));
-				orc = CONFREJ;				/* Reject CI */
-				break;
-			} else if (cilen != CILEN_ADDR) {	/* Check CI length */
-				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Reject ADDR bad len\n"));
-				orc = CONFREJ;				/* Reject CI */
-				break;
-			}
-			
-			/*
-			 * If he has no address, or if we both have his address but
-			 * disagree about it, then NAK it with our idea.
-			 * In particular, if we don't know his address, but he does,
-			 * then accept it.
-			 */
-			GETLONG(tl, p);	/* Parse source address (his) */
-			ciaddr1 = htonl(tl);
-			if (ciaddr1 != wo->hisaddr
-					&& (ciaddr1 == 0 || !wo->accept_remote)) {
-				orc = CONFNAK;
-				if (!reject_if_disagree) {
-					DECPTR(sizeof(u32_t), p);
-					tl = ntohl(wo->hisaddr);
-					PUTLONG(tl, p);
-				}
-				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Nak ADDR %s\n", inet_ntoa(ciaddr1)));
-			} else if (ciaddr1 == 0 && wo->hisaddr == 0) {
-				/*
-				 * Don't ACK an address of 0.0.0.0 - reject it instead.
-				 */
-				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Reject ADDR %s\n", inet_ntoa(ciaddr1)));
-				orc = CONFREJ;
-				wo->req_addr = 0;	/* don't NAK with 0.0.0.0 later */
-				break;
-			}
-			
-			ho->neg_addr = 1;
-			ho->hisaddr = ciaddr1;
-			IPCPDEBUG((LOG_INFO, "ipcp_reqci: ADDR %s\n", inet_ntoa(ciaddr1)));
-			break;
-		
-		case CI_MS_DNS1:
-		case CI_MS_DNS2:
-			/* Microsoft primary or secondary DNS request */
-			d = citype == CI_MS_DNS2;
-			
-			/* If we do not have a DNS address then we cannot send it */
-			if (ao->dnsaddr[d] == 0 ||
-					cilen != CILEN_ADDR) {	/* Check CI length */
-				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting DNS%d Request\n", d+1));
-				orc = CONFREJ;				/* Reject CI */
-				break;
-			}
-			GETLONG(tl, p);
-			if (htonl(tl) != ao->dnsaddr[d]) {
-				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Naking DNS%d Request %d\n",
-							d+1, inet_ntoa(tl)));
-				DECPTR(sizeof(u32_t), p);
-				tl = ntohl(ao->dnsaddr[d]);
-				PUTLONG(tl, p);
-				orc = CONFNAK;
-			}
-			IPCPDEBUG((LOG_INFO, "ipcp_reqci: received DNS%d Request\n", d+1));
-			break;
-		
-		case CI_MS_WINS1:
-		case CI_MS_WINS2:
-			/* Microsoft primary or secondary WINS request */
-			d = citype == CI_MS_WINS2;
-			IPCPDEBUG((LOG_INFO, "ipcp_reqci: received WINS%d Request\n", d+1));
-			
-			/* If we do not have a DNS address then we cannot send it */
-			if (ao->winsaddr[d] == 0 ||
-				cilen != CILEN_ADDR) {	/* Check CI length */
-				orc = CONFREJ;			/* Reject CI */
-				break;
-			}
-			GETLONG(tl, p);
-			if (htonl(tl) != ao->winsaddr[d]) {
-				DECPTR(sizeof(u32_t), p);
-				tl = ntohl(ao->winsaddr[d]);
-				PUTLONG(tl, p);
-				orc = CONFNAK;
-			}
-			break;
-		
-		case CI_COMPRESSTYPE:
-			if (!ao->neg_vj) {
-				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting COMPRESSTYPE not allowed\n"));
-				orc = CONFREJ;
-				break;
-			} else if (cilen != CILEN_VJ && cilen != CILEN_COMPRESS) {
-				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting COMPRESSTYPE len=%d\n", cilen));
-				orc = CONFREJ;
-				break;
-			}
-			GETSHORT(cishort, p);
-			
-			if (!(cishort == IPCP_VJ_COMP ||
-					(cishort == IPCP_VJ_COMP_OLD && cilen == CILEN_COMPRESS))) {
-				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting COMPRESSTYPE %d\n", cishort));
-				orc = CONFREJ;
-				break;
-			}
-			
-			ho->neg_vj = 1;
-			ho->vj_protocol = cishort;
-			if (cilen == CILEN_VJ) {
-				GETCHAR(maxslotindex, p);
-				if (maxslotindex > ao->maxslotindex) { 
-					IPCPDEBUG((LOG_INFO, "ipcp_reqci: Naking VJ max slot %d\n", maxslotindex));
-					orc = CONFNAK;
-					if (!reject_if_disagree){
-						DECPTR(1, p);
-						PUTCHAR(ao->maxslotindex, p);
-					}
-				}
-				GETCHAR(cflag, p);
-				if (cflag && !ao->cflag) {
-					IPCPDEBUG((LOG_INFO, "ipcp_reqci: Naking VJ cflag %d\n", cflag));
-					orc = CONFNAK;
-					if (!reject_if_disagree){
-						DECPTR(1, p);
-						PUTCHAR(wo->cflag, p);
-					}
-				}
-				ho->maxslotindex = maxslotindex;
-				ho->cflag = cflag;
-			} else {
-				ho->old_vj = 1;
-				ho->maxslotindex = MAX_SLOTS - 1;
-				ho->cflag = 1;
-			}
-			IPCPDEBUG((LOG_INFO, 
-						"ipcp_reqci: received COMPRESSTYPE p=%d old=%d maxslot=%d cflag=%d\n",
-						ho->vj_protocol, ho->old_vj, ho->maxslotindex, ho->cflag));
-			break;
-			
-		default:
-			IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting unknown CI type %d\n", citype));
-			orc = CONFREJ;
-			break;
-		}
-		
-endswitch:
-		if (orc == CONFACK &&		/* Good CI */
-				rc != CONFACK)		/*  but prior CI wasnt? */
-			continue;				/* Don't send this one */
-		
-		if (orc == CONFNAK) {		/* Nak this CI? */
-			if (reject_if_disagree) {	/* Getting fed up with sending NAKs? */
-				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting too many naks\n"));
-				orc = CONFREJ;		/* Get tough if so */
-			} else {
-				if (rc == CONFREJ)	/* Rejecting prior CI? */
-					continue;		/* Don't send this one */
-				if (rc == CONFACK) {	/* Ack'd all prior CIs? */
-					rc = CONFNAK;	/* Not anymore... */
-					ucp = inp;		/* Backup */
-				}
-			}
-		}
-		
-		if (orc == CONFREJ &&		/* Reject this CI */
-				rc != CONFREJ) {	/*  but no prior ones? */
-			rc = CONFREJ;
-			ucp = inp;				/* Backup */
-		}
-		
-		/* Need to move CI? */
-		if (ucp != cip)
-			BCOPY(cip, ucp, cilen);	/* Move it */
-		
-		/* Update output pointer */
-		INCPTR(cilen, ucp);
-	}
-	
-	/*
-	 * If we aren't rejecting this packet, and we want to negotiate
-	 * their address, and they didn't send their address, then we
-	 * send a NAK with a CI_ADDR option appended.  We assume the
-	 * input buffer is long enough that we can append the extra
-	 * option safely.
-	 */
-	if (rc != CONFREJ && !ho->neg_addr &&
-			wo->req_addr && !reject_if_disagree) {
-		IPCPDEBUG((LOG_INFO, "ipcp_reqci: Requesting peer address\n"));
-		if (rc == CONFACK) {
-			rc = CONFNAK;
-			ucp = inp;				/* reset pointer */
-			wo->req_addr = 0;		/* don't ask again */
-		}
-		PUTCHAR(CI_ADDR, ucp);
-		PUTCHAR(CILEN_ADDR, ucp);
-		tl = ntohl(wo->hisaddr);
-		PUTLONG(tl, ucp);
-	}
-	
-	*len = (int)(ucp - inp);		/* Compute output length */
-	IPCPDEBUG((LOG_INFO, "ipcp_reqci: returning Configure-%s\n", CODENAME(rc)));
-	return (rc);			/* Return final code */
-}
-
-
-#if 0
-/*
- * ip_check_options - check that any IP-related options are OK,
- * and assign appropriate defaults.
- */
-static void ip_check_options(u_long localAddr)
-{
-	ipcp_options *wo = &ipcp_wantoptions[0];
-
-	/*
-	 * Load our default IP address but allow the remote host to give us
-	 * a new address.
-	 */
-	if (wo->ouraddr == 0 && !ppp_settings.disable_defaultip) {
-		wo->accept_local = 1;	/* don't insist on this default value */
-		wo->ouraddr = htonl(localAddr);
-	}
-}
-#endif
-
-
-/*
- * ipcp_up - IPCP has come UP.
- *
- * Configure the IP network interface appropriately and bring it up.
- */
-static void ipcp_up(fsm *f)
-{
-	u32_t mask;
-	ipcp_options *ho = &ipcp_hisoptions[f->unit];
-	ipcp_options *go = &ipcp_gotoptions[f->unit];
-	ipcp_options *wo = &ipcp_wantoptions[f->unit];
-	
-	np_up(f->unit, PPP_IP);
-	IPCPDEBUG((LOG_INFO, "ipcp: up\n"));
-	
-	/*
-	 * We must have a non-zero IP address for both ends of the link.
-	 */
-	if (!ho->neg_addr)
-		ho->hisaddr = wo->hisaddr;
-	
-	if (ho->hisaddr == 0) {
-		IPCPDEBUG((LOG_ERR, "Could not determine remote IP address\n"));
-		ipcp_close(f->unit, "Could not determine remote IP address");
-		return;
-	}
-	if (go->ouraddr == 0) {
-		IPCPDEBUG((LOG_ERR, "Could not determine local IP address\n"));
-		ipcp_close(f->unit, "Could not determine local IP address");
-		return;
-	}
-	
-	if (ppp_settings.usepeerdns && (go->dnsaddr[0] || go->dnsaddr[1])) {
-		/*pppGotDNSAddrs(go->dnsaddr[0], go->dnsaddr[1]);*/
-	}
-
-	/*
-	 * Check that the peer is allowed to use the IP address it wants.
-	 */
-	if (!auth_ip_addr(f->unit, ho->hisaddr)) {
-		IPCPDEBUG((LOG_ERR, "Peer is not authorized to use remote address %s\n",
-				inet_ntoa(ho->hisaddr)));
-		ipcp_close(f->unit, "Unauthorized remote IP address");
-		return;
-	}
-	
-	/* set tcp compression */
-	sifvjcomp(f->unit, ho->neg_vj, ho->cflag, ho->maxslotindex);
-	
-	/*
-	 * Set IP addresses and (if specified) netmask.
-	 */
-	mask = GetMask(go->ouraddr);
-	
-	if (!sifaddr(f->unit, go->ouraddr, ho->hisaddr, mask, go->dnsaddr[0], go->dnsaddr[1])) {
-		IPCPDEBUG((LOG_WARNING, "sifaddr failed\n"));
-		ipcp_close(f->unit, "Interface configuration failed");
-		return;
-	}
-	
-	/* bring the interface up for IP */
-	if (!sifup(f->unit)) {
-		IPCPDEBUG((LOG_WARNING, "sifup failed\n"));
-		ipcp_close(f->unit, "Interface configuration failed");
-		return;
-	}
-	
-	sifnpmode(f->unit, PPP_IP, NPMODE_PASS);
-	
-	/* assign a default route through the interface if required */
-	if (ipcp_wantoptions[f->unit].default_route) 
-		if (sifdefaultroute(f->unit, go->ouraddr, ho->hisaddr))
-			default_route_set[f->unit] = 1;
-	
-	IPCPDEBUG((LOG_NOTICE, "local  IP address %s\n", inet_ntoa(go->ouraddr)));
-	IPCPDEBUG((LOG_NOTICE, "remote IP address %s\n", inet_ntoa(ho->hisaddr)));
-	if (go->dnsaddr[0]) {
-		IPCPDEBUG((LOG_NOTICE, "primary   DNS address %s\n", inet_ntoa(go->dnsaddr[0])));
-	}
-	if (go->dnsaddr[1]) {
-		IPCPDEBUG((LOG_NOTICE, "secondary DNS address %s\n", inet_ntoa(go->dnsaddr[1])));
-	}
-}
-
-
-/*
- * ipcp_down - IPCP has gone DOWN.
- *
- * Take the IP network interface down, clear its addresses
- * and delete routes through it.
- */
-static void ipcp_down(fsm *f)
-{
-	IPCPDEBUG((LOG_INFO, "ipcp: down\n"));
-	np_down(f->unit, PPP_IP);
-	sifvjcomp(f->unit, 0, 0, 0);
-	
-	sifdown(f->unit);
-	ipcp_clear_addrs(f->unit);
-}
-
-
-/*
- * ipcp_clear_addrs() - clear the interface addresses, routes, etc.
- */
-static void ipcp_clear_addrs(int unit)
-{
-	u32_t ouraddr, hisaddr;
-	
-	ouraddr = ipcp_gotoptions[unit].ouraddr;
-	hisaddr = ipcp_hisoptions[unit].hisaddr;
-	if (default_route_set[unit]) {
-		cifdefaultroute(unit, ouraddr, hisaddr);
-		default_route_set[unit] = 0;
-	}
-	cifaddr(unit, ouraddr, hisaddr);
-}
-
-
-/*
- * ipcp_finished - possibly shut down the lower layers.
- */
-static void ipcp_finished(fsm *f)
-{
-	np_finished(f->unit, PPP_IP);
-}
-
-#if 0
-static int ipcp_printpkt(
-	u_char *p,
-	int plen,
-	void (*printer) (void *, char *, ...),
-	void *arg
-)
-{
-	(void)p;
-	(void)plen;
-	(void)printer;
-	(void)arg;
-	return 0;
-}
-
-/*
- * ip_active_pkt - see if this IP packet is worth bringing the link up for.
- * We don't bring the link up for IP fragments or for TCP FIN packets
- * with no data.
- */
-#define IP_HDRLEN	20	/* bytes */
-#define IP_OFFMASK	0x1fff
-#define IPPROTO_TCP	6
-#define TCP_HDRLEN	20
-#define TH_FIN		0x01
-
-/*
- * We use these macros because the IP header may be at an odd address,
- * and some compilers might use word loads to get th_off or ip_hl.
- */
-
-#define net_short(x)	(((x)[0] << 8) + (x)[1])
-#define get_iphl(x)	(((unsigned char *)(x))[0] & 0xF)
-#define get_ipoff(x)	net_short((unsigned char *)(x) + 6)
-#define get_ipproto(x)	(((unsigned char *)(x))[9])
-#define get_tcpoff(x)	(((unsigned char *)(x))[12] >> 4)
-#define get_tcpflags(x)	(((unsigned char *)(x))[13])
-
-static int ip_active_pkt(u_char *pkt, int len)
-{
-	u_char *tcp;
-	int hlen;
-	
-	len -= PPP_HDRLEN;
-	pkt += PPP_HDRLEN;
-	if (len < IP_HDRLEN)
-		return 0;
-	if ((get_ipoff(pkt) & IP_OFFMASK) != 0)
-		return 0;
-	if (get_ipproto(pkt) != IPPROTO_TCP)
-		return 1;
-	hlen = get_iphl(pkt) * 4;
-	if (len < hlen + TCP_HDRLEN)
-		return 0;
-	tcp = pkt + hlen;
-	if ((get_tcpflags(tcp) & TH_FIN) != 0 && len == hlen + get_tcpoff(tcp) * 4)
-		return 0;
-	return 1;
-}
-#endif
-
-#endif /* PPP_SUPPORT */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/ipcp.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/ipcp.h
deleted file mode 100644
index 416aa79a2..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/ipcp.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/*****************************************************************************
-* ipcp.h -  PPP IP NCP: Internet Protocol Network Control Protocol header file.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* portions Copyright (c) 1997 Global Election Systems Inc.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY
-*
-* 03-01-01 Marc Boucher 
-*   Ported to lwIP.
-* 97-12-04 Guy Lancaster , Global Election Systems Inc.
-*	Original derived from BSD codes.
-*****************************************************************************/
-/*
- * ipcp.h - IP Control Protocol definitions.
- *
- * Copyright (c) 1989 Carnegie Mellon University.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by Carnegie Mellon University.  The name of the
- * University may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- *
- * $Id: ipcp.h,v 1.1 2003/05/27 14:37:56 jani Exp $
- */
-
-#ifndef IPCP_H
-#define IPCP_H
-
-/*************************
-*** PUBLIC DEFINITIONS ***
-*************************/
-/*
- * Options.
- */
-#define CI_ADDRS	1			/* IP Addresses */
-#define CI_COMPRESSTYPE	2		/* Compression Type */
-#define	CI_ADDR		3
-
-#define CI_MS_WINS1	128			/* Primary WINS value */
-#define CI_MS_DNS1	129			/* Primary DNS value */
-#define CI_MS_WINS2	130			/* Secondary WINS value */
-#define CI_MS_DNS2	131			/* Secondary DNS value */
-
-#define IPCP_VJMODE_OLD 1		/* "old" mode (option # = 0x0037) */
-#define IPCP_VJMODE_RFC1172 2	/* "old-rfc"mode (option # = 0x002d) */
-#define IPCP_VJMODE_RFC1332 3	/* "new-rfc"mode (option # = 0x002d, */
-                                /*  maxslot and slot number compression) */
-
-#define IPCP_VJ_COMP 0x002d		/* current value for VJ compression option*/
-#define IPCP_VJ_COMP_OLD 0x0037	/* "old" (i.e, broken) value for VJ */
-								/* compression option*/ 
-
-
-/************************
-*** PUBLIC DATA TYPES ***
-************************/
-
-typedef struct ipcp_options {
-    u_int neg_addr : 1;			/* Negotiate IP Address? */
-    u_int old_addrs : 1;			/* Use old (IP-Addresses) option? */
-    u_int req_addr : 1;			/* Ask peer to send IP address? */
-    u_int default_route : 1;		/* Assign default route through interface? */
-    u_int proxy_arp : 1;			/* Make proxy ARP entry for peer? */
-    u_int neg_vj : 1;				/* Van Jacobson Compression? */
-    u_int old_vj : 1;				/* use old (short) form of VJ option? */
-    u_int accept_local : 1;		/* accept peer's value for ouraddr */
-    u_int accept_remote : 1;		/* accept peer's value for hisaddr */
-    u_int req_dns1 : 1;			/* Ask peer to send primary DNS address? */
-    u_int req_dns2 : 1;			/* Ask peer to send secondary DNS address? */
-    u_short vj_protocol;		/* protocol value to use in VJ option */
-    u_char maxslotindex;		/* VJ slots - 1. */
-    u_char cflag;				/* VJ slot compression flag. */
-    u32_t ouraddr, hisaddr;	/* Addresses in NETWORK BYTE ORDER */
-    u32_t dnsaddr[2];		/* Primary and secondary MS DNS entries */
-    u32_t winsaddr[2];		/* Primary and secondary MS WINS entries */
-} ipcp_options;
-
-
-/*****************************
-*** PUBLIC DATA STRUCTURES ***
-*****************************/
-
-extern fsm ipcp_fsm[];
-extern ipcp_options ipcp_wantoptions[];
-extern ipcp_options ipcp_gotoptions[];
-extern ipcp_options ipcp_allowoptions[];
-extern ipcp_options ipcp_hisoptions[];
-
-extern struct protent ipcp_protent;
-
-
-/***********************
-*** PUBLIC FUNCTIONS ***
-***********************/
-
-
-#endif /* IPCP_H */
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/lcp.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/lcp.c
deleted file mode 100644
index e974a2d44..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/lcp.c
+++ /dev/null
@@ -1,1991 +0,0 @@
-/*****************************************************************************
-* lcp.c - Network Link Control Protocol program file.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* portions Copyright (c) 1997 by Global Election Systems Inc.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY
-*
-* 03-01-01 Marc Boucher 
-*   Ported to lwIP.
-* 97-12-01 Guy Lancaster , Global Election Systems Inc.
-*	Original.
-*****************************************************************************/
-
-/*
- * lcp.c - PPP Link Control Protocol.
- *
- * Copyright (c) 1989 Carnegie Mellon University.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by Carnegie Mellon University.  The name of the
- * University may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- */
- 
-#include 
- 
-#include "ppp.h"
-#if PPP_SUPPORT > 0
-#include "fsm.h"
-#include "chap.h"
-#include "magic.h"
-#include "auth.h"
-#include "lcp.h"
-#include "pppdebug.h"
-
-
-/*************************/
-/*** LOCAL DEFINITIONS ***/
-/*************************/
-/*
- * Length of each type of configuration option (in octets)
- */
-#define CILEN_VOID	2
-#define CILEN_CHAR	3
-#define CILEN_SHORT	4	/* CILEN_VOID + sizeof(short) */
-#define CILEN_CHAP	5	/* CILEN_VOID + sizeof(short) + 1 */
-#define CILEN_LONG	6	/* CILEN_VOID + sizeof(long) */
-#define CILEN_LQR	8	/* CILEN_VOID + sizeof(short) + sizeof(long) */
-#define CILEN_CBCP	3
-
-
-/***********************************/
-/*** LOCAL FUNCTION DECLARATIONS ***/
-/***********************************/
-/*
- * Callbacks for fsm code.  (CI = Configuration Information)
- */
-static void lcp_resetci (fsm*);	        /* Reset our CI */
-static int  lcp_cilen (fsm*);		        /* Return length of our CI */
-static void lcp_addci (fsm*, u_char*, int*);       /* Add our CI to pkt */
-static int  lcp_ackci (fsm*, u_char*, int);/* Peer ack'd our CI */
-static int  lcp_nakci (fsm*, u_char*, int);/* Peer nak'd our CI */
-static int  lcp_rejci (fsm*, u_char*, int);/* Peer rej'd our CI */
-static int  lcp_reqci (fsm*, u_char*, int*, int);  /* Rcv peer CI */
-static void lcp_up (fsm*);		            /* We're UP */
-static void lcp_down (fsm*);	    	    /* We're DOWN */
-static void lcp_starting (fsm*);   	    /* We need lower layer up */
-static void lcp_finished (fsm*);	        /* We need lower layer down */
-static int  lcp_extcode (fsm*, int, u_char, u_char*, int);
-
-static void lcp_rprotrej (fsm*, u_char*, int);
-
-/*
- * routines to send LCP echos to peer
- */
-static void lcp_echo_lowerup (int);
-static void lcp_echo_lowerdown (int);
-static void LcpEchoTimeout (void*);
-static void lcp_received_echo_reply (fsm*, int, u_char*, int);
-static void LcpSendEchoRequest (fsm*);
-static void LcpLinkFailure (fsm*);
-static void LcpEchoCheck (fsm*);
-
-/*
- * Protocol entry points.
- * Some of these are called directly.
- */
-static void lcp_input (int, u_char *, int);
-static void lcp_protrej (int);
-
-#define CODENAME(x)	((x) == CONFACK ? "ACK" : \
-			 (x) == CONFNAK ? "NAK" : "REJ")
-
-
-/******************************/
-/*** PUBLIC DATA STRUCTURES ***/
-/******************************/
-/* global vars */
-LinkPhase lcp_phase[NUM_PPP];			/* Phase of link session (RFC 1661) */
-lcp_options lcp_wantoptions[NUM_PPP];	/* Options that we want to request */
-lcp_options lcp_gotoptions[NUM_PPP];	/* Options that peer ack'd */
-lcp_options lcp_allowoptions[NUM_PPP];	/* Options we allow peer to request */
-lcp_options lcp_hisoptions[NUM_PPP];	/* Options that we ack'd */
-ext_accm xmit_accm[NUM_PPP];			/* extended transmit ACCM */
-
-
-
-/*****************************/
-/*** LOCAL DATA STRUCTURES ***/
-/*****************************/
-static fsm lcp_fsm[NUM_PPP];			/* LCP fsm structure (global)*/
-static u_int	 lcp_echo_interval = LCP_ECHOINTERVAL; /* Interval between LCP echo-requests */
-static u_int	 lcp_echo_fails = LCP_MAXECHOFAILS; /* Tolerance to unanswered echo-requests */
-static u32_t lcp_echos_pending = 0;	/* Number of outstanding echo msgs */
-static u32_t lcp_echo_number   = 0;	/* ID number of next echo frame */
-static u32_t lcp_echo_timer_running = 0;  /* TRUE if a timer is running */
-
-static u_char nak_buffer[PPP_MRU];	/* where we construct a nak packet */
-
-static fsm_callbacks lcp_callbacks = {	/* LCP callback routines */
-    lcp_resetci,		/* Reset our Configuration Information */
-    lcp_cilen,			/* Length of our Configuration Information */
-    lcp_addci,			/* Add our Configuration Information */
-    lcp_ackci,			/* ACK our Configuration Information */
-    lcp_nakci,			/* NAK our Configuration Information */
-    lcp_rejci,			/* Reject our Configuration Information */
-    lcp_reqci,			/* Request peer's Configuration Information */
-    lcp_up,				/* Called when fsm reaches OPENED state */
-    lcp_down,			/* Called when fsm leaves OPENED state */
-    lcp_starting,		/* Called when we want the lower layer up */
-    lcp_finished,		/* Called when we want the lower layer down */
-    NULL,				/* Called when Protocol-Reject received */
-    NULL,				/* Retransmission is necessary */
-    lcp_extcode,		/* Called to handle LCP-specific codes */
-    "LCP"				/* String name of protocol */
-};
-
-struct protent lcp_protent = {
-    PPP_LCP,
-    lcp_init,
-    lcp_input,
-    lcp_protrej,
-    lcp_lowerup,
-    lcp_lowerdown,
-    lcp_open,
-    lcp_close,
-#if 0
-    lcp_printpkt,
-    NULL,
-#endif
-    1,
-    "LCP",
-#if 0
-    NULL,
-    NULL,
-    NULL
-#endif
-};
-
-int lcp_loopbackfail = DEFLOOPBACKFAIL;
-
-
-
-/***********************************/
-/*** PUBLIC FUNCTION DEFINITIONS ***/
-/***********************************/
-/*
- * lcp_init - Initialize LCP.
- */
-void lcp_init(int unit)
-{
-	fsm *f = &lcp_fsm[unit];
-	lcp_options *wo = &lcp_wantoptions[unit];
-	lcp_options *ao = &lcp_allowoptions[unit];
-	
-	f->unit = unit;
-	f->protocol = PPP_LCP;
-	f->callbacks = &lcp_callbacks;
-	
-	fsm_init(f);
-	
-	wo->passive = 0;
-	wo->silent = 0;
-	wo->restart = 0;			/* Set to 1 in kernels or multi-line
-								 * implementations */
-	wo->neg_mru = 1;
-	wo->mru = PPP_DEFMRU;
-	wo->neg_asyncmap = 1;
-	wo->asyncmap = 0x00000000l;	/* Assume don't need to escape any ctl chars. */
-	wo->neg_chap = 0;			/* Set to 1 on server */
-	wo->neg_upap = 0;			/* Set to 1 on server */
-	wo->chap_mdtype = CHAP_DIGEST_MD5;
-	wo->neg_magicnumber = 1;
-	wo->neg_pcompression = 1;
-	wo->neg_accompression = 1;
-	wo->neg_lqr = 0;			/* no LQR implementation yet */
-	wo->neg_cbcp = 0;
-	
-	ao->neg_mru = 1;
-	ao->mru = PPP_MAXMRU;
-	ao->neg_asyncmap = 1;
-	ao->asyncmap = 0x00000000l;	/* Assume don't need to escape any ctl chars. */
-	ao->neg_chap = (CHAP_SUPPORT != 0);
-	ao->chap_mdtype = CHAP_DIGEST_MD5;
-	ao->neg_upap = (PAP_SUPPORT != 0);
-	ao->neg_magicnumber = 1;
-	ao->neg_pcompression = 1;
-	ao->neg_accompression = 1;
-	ao->neg_lqr = 0;			/* no LQR implementation yet */
-	ao->neg_cbcp = (CBCP_SUPPORT != 0);
-
-	/* 
-	 * Set transmit escape for the flag and escape characters plus anything
-	 * set for the allowable options.
-	 */
-	memset(xmit_accm[unit], 0, sizeof(xmit_accm[0]));
-	xmit_accm[unit][15] = 0x60;
-	xmit_accm[unit][0] = (u_char)(ao->asyncmap & 0xFF);
-	xmit_accm[unit][1] = (u_char)((ao->asyncmap >> 8) & 0xFF);
-	xmit_accm[unit][2] = (u_char)((ao->asyncmap >> 16) & 0xFF);
-	xmit_accm[unit][3] = (u_char)((ao->asyncmap >> 24) & 0xFF);
-	LCPDEBUG((LOG_INFO, "lcp_init: xmit_accm=%X %X %X %X\n",
-				xmit_accm[unit][0],
-				xmit_accm[unit][1],
-				xmit_accm[unit][2],
-				xmit_accm[unit][3]));
-	
-	lcp_phase[unit] = PHASE_INITIALIZE;
-}
-
-
-/*
- * lcp_open - LCP is allowed to come up.
- */
-void lcp_open(int unit)
-{
-	fsm *f = &lcp_fsm[unit];
-	lcp_options *wo = &lcp_wantoptions[unit];
-	
-	f->flags = 0;
-	if (wo->passive)
-		f->flags |= OPT_PASSIVE;
-	if (wo->silent)
-		f->flags |= OPT_SILENT;
-	fsm_open(f);
-	
-	lcp_phase[unit] = PHASE_ESTABLISH; 
-}
-
-
-/*
- * lcp_close - Take LCP down.
- */
-void lcp_close(int unit, char *reason)
-{
-	fsm *f = &lcp_fsm[unit];
-	
-	if (lcp_phase[unit] != PHASE_DEAD)
-		lcp_phase[unit] = PHASE_TERMINATE;
-	if (f->state == STOPPED && f->flags & (OPT_PASSIVE|OPT_SILENT)) {
-		/*
-		 * This action is not strictly according to the FSM in RFC1548,
-		 * but it does mean that the program terminates if you do an
-		 * lcp_close() in passive/silent mode when a connection hasn't
-		 * been established.
-		 */
-		f->state = CLOSED;
-		lcp_finished(f);
-	}
-	else
-		fsm_close(&lcp_fsm[unit], reason);
-}
-
-
-/*
- * lcp_lowerup - The lower layer is up.
- */
-void lcp_lowerup(int unit)
-{
-	lcp_options *wo = &lcp_wantoptions[unit];
-	
-	/*
-	* Don't use A/C or protocol compression on transmission,
-	* but accept A/C and protocol compressed packets
-	* if we are going to ask for A/C and protocol compression.
-	*/
-	ppp_set_xaccm(unit, &xmit_accm[unit]);
-	ppp_send_config(unit, PPP_MRU, 0xffffffffl, 0, 0);
-	ppp_recv_config(unit, PPP_MRU, 0x00000000l,
-					wo->neg_pcompression, wo->neg_accompression);
-	peer_mru[unit] = PPP_MRU;
-	lcp_allowoptions[unit].asyncmap 
-		= (u_long)xmit_accm[unit][0]
-			| ((u_long)xmit_accm[unit][1] << 8)
-			| ((u_long)xmit_accm[unit][2] << 16)
-			| ((u_long)xmit_accm[unit][3] << 24);
-	LCPDEBUG((LOG_INFO, "lcp_lowerup: asyncmap=%X %X %X %X\n",
-				xmit_accm[unit][3],
-				xmit_accm[unit][2],
-				xmit_accm[unit][1],
-				xmit_accm[unit][0]));
-	
-	fsm_lowerup(&lcp_fsm[unit]);
-}
-
-
-/*
- * lcp_lowerdown - The lower layer is down.
- */
-void lcp_lowerdown(int unit)
-{
-	fsm_lowerdown(&lcp_fsm[unit]);
-}
-
-/*
- * lcp_sprotrej - Send a Protocol-Reject for some protocol.
- */
-void lcp_sprotrej(int unit, u_char *p, int len)
-{
-	/*
-	* Send back the protocol and the information field of the
-	* rejected packet.  We only get here if LCP is in the OPENED state.
-	*/
-
-	fsm_sdata(&lcp_fsm[unit], PROTREJ, ++lcp_fsm[unit].id,
-				p, len);
-}
-
-
-
-/**********************************/
-/*** LOCAL FUNCTION DEFINITIONS ***/
-/**********************************/
-/*
- * lcp_input - Input LCP packet.
- */
-static void lcp_input(int unit, u_char *p, int len)
-{
-	fsm *f = &lcp_fsm[unit];
-	
-	fsm_input(f, p, len);
-}
-
-
-/*
- * lcp_extcode - Handle a LCP-specific code.
- */
-static int lcp_extcode(fsm *f, int code, u_char id, u_char *inp, int len)
-{
-	u_char *magp;
-	
-	switch( code ){
-	case PROTREJ:
-		lcp_rprotrej(f, inp, len);
-		break;
-	
-	case ECHOREQ:
-		if (f->state != OPENED)
-			break;
-		LCPDEBUG((LOG_INFO, "lcp: Echo-Request, Rcvd id %d\n", id));
-		magp = inp;
-		PUTLONG(lcp_gotoptions[f->unit].magicnumber, magp);
-		fsm_sdata(f, ECHOREP, id, inp, len);
-		break;
-	
-	case ECHOREP:
-		lcp_received_echo_reply(f, id, inp, len);
-		break;
-	
-	case DISCREQ:
-		break;
-	
-	default:
-		return 0;
-	}
-	return 1;
-}
-
-    
-/*
- * lcp_rprotrej - Receive an Protocol-Reject.
- *
- * Figure out which protocol is rejected and inform it.
- */
-static void lcp_rprotrej(fsm *f, u_char *inp, int len)
-{
-	int i;
-	struct protent *protp;
-	u_short prot;
-	
-	if (len < sizeof (u_short)) {
-		LCPDEBUG((LOG_INFO,
-				"lcp_rprotrej: Rcvd short Protocol-Reject packet!\n"));
-		return;
-	}
-	
-	GETSHORT(prot, inp);
-	
-	LCPDEBUG((LOG_INFO,
-			"lcp_rprotrej: Rcvd Protocol-Reject packet for %x!\n",
-			prot));
-	
-	/*
-	* Protocol-Reject packets received in any state other than the LCP
-	* OPENED state SHOULD be silently discarded.
-	*/
-	if( f->state != OPENED ){
-		LCPDEBUG((LOG_INFO, "Protocol-Reject discarded: LCP in state %d\n",
-				f->state));
-		return;
-	}
-	
-	/*
-	* Upcall the proper Protocol-Reject routine.
-	*/
-	for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i)
-		if (protp->protocol == prot && protp->enabled_flag) {
-			(*protp->protrej)(f->unit);
-			return;
-		}
-	
-	LCPDEBUG((LOG_WARNING, "Protocol-Reject for unsupported protocol 0x%x\n",
-			prot));
-}
-
-
-/*
- * lcp_protrej - A Protocol-Reject was received.
- */
-static void lcp_protrej(int unit)
-{
-	(void)unit;
-	/*
-	* Can't reject LCP!
-	*/
-	LCPDEBUG((LOG_WARNING,
-			"lcp_protrej: Received Protocol-Reject for LCP!\n"));
-	fsm_protreject(&lcp_fsm[unit]);
-}
-
-
-/*
- * lcp_resetci - Reset our CI.
- */
-static void lcp_resetci(fsm *f)
-{
-	lcp_wantoptions[f->unit].magicnumber = magic();
-	lcp_wantoptions[f->unit].numloops = 0;
-	lcp_gotoptions[f->unit] = lcp_wantoptions[f->unit];
-	peer_mru[f->unit] = PPP_MRU;
-	auth_reset(f->unit);
-}
-
-
-/*
- * lcp_cilen - Return length of our CI.
- */
-static int lcp_cilen(fsm *f)
-{
-	lcp_options *go = &lcp_gotoptions[f->unit];
-
-#define LENCIVOID(neg)	((neg) ? CILEN_VOID : 0)
-#define LENCICHAP(neg)	((neg) ? CILEN_CHAP : 0)
-#define LENCISHORT(neg)	((neg) ? CILEN_SHORT : 0)
-#define LENCILONG(neg)	((neg) ? CILEN_LONG : 0)
-#define LENCILQR(neg)	((neg) ? CILEN_LQR: 0)
-#define LENCICBCP(neg)	((neg) ? CILEN_CBCP: 0)
-	/*
-	* NB: we only ask for one of CHAP and UPAP, even if we will
-	* accept either.
-	*/
-	return (LENCISHORT(go->neg_mru && go->mru != PPP_DEFMRU) +
-		LENCILONG(go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl) +
-		LENCICHAP(go->neg_chap) +
-		LENCISHORT(!go->neg_chap && go->neg_upap) +
-		LENCILQR(go->neg_lqr) +
-		LENCICBCP(go->neg_cbcp) +
-		LENCILONG(go->neg_magicnumber) +
-		LENCIVOID(go->neg_pcompression) +
-		LENCIVOID(go->neg_accompression));
-}
-
-
-/*
- * lcp_addci - Add our desired CIs to a packet.
- */
-static void lcp_addci(fsm *f, u_char *ucp, int *lenp)
-{
-	lcp_options *go = &lcp_gotoptions[f->unit];
-	u_char *start_ucp = ucp;
-	
-#define ADDCIVOID(opt, neg) \
-	if (neg) { \
-	    LCPDEBUG((LOG_INFO, "lcp_addci: opt=%d\n", opt)); \
-		PUTCHAR(opt, ucp); \
-		PUTCHAR(CILEN_VOID, ucp); \
-	}
-#define ADDCISHORT(opt, neg, val) \
-	if (neg) { \
-	    LCPDEBUG((LOG_INFO, "lcp_addci: INT opt=%d %X\n", opt, val)); \
-		PUTCHAR(opt, ucp); \
-		PUTCHAR(CILEN_SHORT, ucp); \
-		PUTSHORT(val, ucp); \
-	}
-#define ADDCICHAP(opt, neg, val, digest) \
-	if (neg) { \
-	    LCPDEBUG((LOG_INFO, "lcp_addci: CHAP opt=%d %X\n", opt, val)); \
-		PUTCHAR(opt, ucp); \
-		PUTCHAR(CILEN_CHAP, ucp); \
-		PUTSHORT(val, ucp); \
-		PUTCHAR(digest, ucp); \
-	}
-#define ADDCILONG(opt, neg, val) \
-	if (neg) { \
-	    LCPDEBUG((LOG_INFO, "lcp_addci: L opt=%d %lX\n", opt, val)); \
-		PUTCHAR(opt, ucp); \
-		PUTCHAR(CILEN_LONG, ucp); \
-		PUTLONG(val, ucp); \
-	}
-#define ADDCILQR(opt, neg, val) \
-	if (neg) { \
-	    LCPDEBUG((LOG_INFO, "lcp_addci: LQR opt=%d %lX\n", opt, val)); \
-		PUTCHAR(opt, ucp); \
-		PUTCHAR(CILEN_LQR, ucp); \
-		PUTSHORT(PPP_LQR, ucp); \
-		PUTLONG(val, ucp); \
-	}
-#define ADDCICHAR(opt, neg, val) \
-	if (neg) { \
-	    LCPDEBUG((LOG_INFO, "lcp_addci: CHAR opt=%d %X '%z'\n", opt, val, val)); \
-		PUTCHAR(opt, ucp); \
-		PUTCHAR(CILEN_CHAR, ucp); \
-		PUTCHAR(val, ucp); \
-	}
-	
-	ADDCISHORT(CI_MRU, go->neg_mru && go->mru != PPP_DEFMRU, go->mru);
-	ADDCILONG(CI_ASYNCMAP, go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl,
-			go->asyncmap);
-	ADDCICHAP(CI_AUTHTYPE, go->neg_chap, PPP_CHAP, go->chap_mdtype);
-	ADDCISHORT(CI_AUTHTYPE, !go->neg_chap && go->neg_upap, PPP_PAP);
-	ADDCILQR(CI_QUALITY, go->neg_lqr, go->lqr_period);
-	ADDCICHAR(CI_CALLBACK, go->neg_cbcp, CBCP_OPT);
-	ADDCILONG(CI_MAGICNUMBER, go->neg_magicnumber, go->magicnumber);
-	ADDCIVOID(CI_PCOMPRESSION, go->neg_pcompression);
-	ADDCIVOID(CI_ACCOMPRESSION, go->neg_accompression);
-	
-	if (ucp - start_ucp != *lenp) {
-		/* this should never happen, because peer_mtu should be 1500 */
-		LCPDEBUG((LOG_ERR, "Bug in lcp_addci: wrong length\n"));
-	}
-}
-
-
-/*
- * lcp_ackci - Ack our CIs.
- * This should not modify any state if the Ack is bad.
- *
- * Returns:
- *	0 - Ack was bad.
- *	1 - Ack was good.
- */
-static int lcp_ackci(fsm *f, u_char *p, int len)
-{
-	lcp_options *go = &lcp_gotoptions[f->unit];
-	u_char cilen, citype, cichar;
-	u_short cishort;
-	u32_t cilong;
-	
-	/*
-	* CIs must be in exactly the same order that we sent.
-	* Check packet length and CI length at each step.
-	* If we find any deviations, then this packet is bad.
-	*/
-#define ACKCIVOID(opt, neg) \
-	if (neg) { \
-		if ((len -= CILEN_VOID) < 0) \
-			goto bad; \
-		GETCHAR(citype, p); \
-		GETCHAR(cilen, p); \
-		if (cilen != CILEN_VOID || \
-				citype != opt) \
-			goto bad; \
-	}
-#define ACKCISHORT(opt, neg, val) \
-	if (neg) { \
-		if ((len -= CILEN_SHORT) < 0) \
-			goto bad; \
-		GETCHAR(citype, p); \
-		GETCHAR(cilen, p); \
-		if (cilen != CILEN_SHORT || \
-				citype != opt) \
-			goto bad; \
-		GETSHORT(cishort, p); \
-		if (cishort != val) \
-			goto bad; \
-	}
-#define ACKCICHAR(opt, neg, val) \
-	if (neg) { \
-		if ((len -= CILEN_CHAR) < 0) \
-			goto bad; \
-		GETCHAR(citype, p); \
-		GETCHAR(cilen, p); \
-		if (cilen != CILEN_CHAR || \
-				citype != opt) \
-			goto bad; \
-		GETCHAR(cichar, p); \
-		if (cichar != val) \
-			goto bad; \
-	}
-#define ACKCICHAP(opt, neg, val, digest) \
-	if (neg) { \
-		if ((len -= CILEN_CHAP) < 0) \
-			goto bad; \
-		GETCHAR(citype, p); \
-		GETCHAR(cilen, p); \
-		if (cilen != CILEN_CHAP || \
-				citype != opt) \
-			goto bad; \
-		GETSHORT(cishort, p); \
-		if (cishort != val) \
-			goto bad; \
-		GETCHAR(cichar, p); \
-		if (cichar != digest) \
-			goto bad; \
-	}
-#define ACKCILONG(opt, neg, val) \
-	if (neg) { \
-		if ((len -= CILEN_LONG) < 0) \
-			goto bad; \
-		GETCHAR(citype, p); \
-		GETCHAR(cilen, p); \
-		if (cilen != CILEN_LONG || \
-				citype != opt) \
-			goto bad; \
-		GETLONG(cilong, p); \
-		if (cilong != val) \
-			goto bad; \
-	}
-#define ACKCILQR(opt, neg, val) \
-	if (neg) { \
-		if ((len -= CILEN_LQR) < 0) \
-			goto bad; \
-		GETCHAR(citype, p); \
-		GETCHAR(cilen, p); \
-		if (cilen != CILEN_LQR || \
-				citype != opt) \
-			goto bad; \
-		GETSHORT(cishort, p); \
-		if (cishort != PPP_LQR) \
-			goto bad; \
-		GETLONG(cilong, p); \
-		if (cilong != val) \
-			goto bad; \
-	}
-	
-	ACKCISHORT(CI_MRU, go->neg_mru && go->mru != PPP_DEFMRU, go->mru);
-	ACKCILONG(CI_ASYNCMAP, go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl,
-			go->asyncmap);
-	ACKCICHAP(CI_AUTHTYPE, go->neg_chap, PPP_CHAP, go->chap_mdtype);
-	ACKCISHORT(CI_AUTHTYPE, !go->neg_chap && go->neg_upap, PPP_PAP);
-	ACKCILQR(CI_QUALITY, go->neg_lqr, go->lqr_period);
-	ACKCICHAR(CI_CALLBACK, go->neg_cbcp, CBCP_OPT);
-	ACKCILONG(CI_MAGICNUMBER, go->neg_magicnumber, go->magicnumber);
-	ACKCIVOID(CI_PCOMPRESSION, go->neg_pcompression);
-	ACKCIVOID(CI_ACCOMPRESSION, go->neg_accompression);
-	
-	/*
-	 * If there are any remaining CIs, then this packet is bad.
-	 */
-	if (len != 0)
-		goto bad;
-	LCPDEBUG((LOG_INFO, "lcp_acki: Ack\n"));
-	return (1);
-bad:
-	LCPDEBUG((LOG_WARNING, "lcp_acki: received bad Ack!\n"));
-	return (0);
-}
-
-
-/*
- * lcp_nakci - Peer has sent a NAK for some of our CIs.
- * This should not modify any state if the Nak is bad
- * or if LCP is in the OPENED state.
- *
- * Returns:
- *	0 - Nak was bad.
- *	1 - Nak was good.
- */
-static int lcp_nakci(fsm *f, u_char *p, int len)
-{
-	lcp_options *go = &lcp_gotoptions[f->unit];
-	lcp_options *wo = &lcp_wantoptions[f->unit];
-	u_char citype, cichar, *next;
-	u_short cishort;
-	u32_t cilong;
-	lcp_options no;		/* options we've seen Naks for */
-	lcp_options try;		/* options to request next time */
-	int looped_back = 0;
-	int cilen;
-	
-	BZERO(&no, sizeof(no));
-	try = *go;
-	
-	/*
-	* Any Nak'd CIs must be in exactly the same order that we sent.
-	* Check packet length and CI length at each step.
-	* If we find any deviations, then this packet is bad.
-	*/
-#define NAKCIVOID(opt, neg, code) \
-	if (go->neg && \
-			len >= CILEN_VOID && \
-			p[1] == CILEN_VOID && \
-			p[0] == opt) { \
-		len -= CILEN_VOID; \
-		INCPTR(CILEN_VOID, p); \
-		no.neg = 1; \
-		code \
-	}
-#define NAKCICHAP(opt, neg, code) \
-	if (go->neg && \
-			len >= CILEN_CHAP && \
-			p[1] == CILEN_CHAP && \
-			p[0] == opt) { \
-		len -= CILEN_CHAP; \
-		INCPTR(2, p); \
-		GETSHORT(cishort, p); \
-		GETCHAR(cichar, p); \
-		no.neg = 1; \
-		code \
-	}
-#define NAKCICHAR(opt, neg, code) \
-	if (go->neg && \
-			len >= CILEN_CHAR && \
-			p[1] == CILEN_CHAR && \
-			p[0] == opt) { \
-		len -= CILEN_CHAR; \
-		INCPTR(2, p); \
-		GETCHAR(cichar, p); \
-		no.neg = 1; \
-		code \
-	}
-#define NAKCISHORT(opt, neg, code) \
-	if (go->neg && \
-			len >= CILEN_SHORT && \
-			p[1] == CILEN_SHORT && \
-			p[0] == opt) { \
-		len -= CILEN_SHORT; \
-		INCPTR(2, p); \
-		GETSHORT(cishort, p); \
-		no.neg = 1; \
-		code \
-	}
-#define NAKCILONG(opt, neg, code) \
-	if (go->neg && \
-			len >= CILEN_LONG && \
-			p[1] == CILEN_LONG && \
-			p[0] == opt) { \
-		len -= CILEN_LONG; \
-		INCPTR(2, p); \
-		GETLONG(cilong, p); \
-		no.neg = 1; \
-		code \
-	}
-#define NAKCILQR(opt, neg, code) \
-	if (go->neg && \
-			len >= CILEN_LQR && \
-			p[1] == CILEN_LQR && \
-			p[0] == opt) { \
-		len -= CILEN_LQR; \
-		INCPTR(2, p); \
-		GETSHORT(cishort, p); \
-		GETLONG(cilong, p); \
-		no.neg = 1; \
-		code \
-	}
-	
-	/*
-	* We don't care if they want to send us smaller packets than
-	* we want.  Therefore, accept any MRU less than what we asked for,
-	* but then ignore the new value when setting the MRU in the kernel.
-	* If they send us a bigger MRU than what we asked, accept it, up to
-	* the limit of the default MRU we'd get if we didn't negotiate.
-	*/
-	if (go->neg_mru && go->mru != PPP_DEFMRU) {
-		NAKCISHORT(CI_MRU, neg_mru,
-			if (cishort <= wo->mru || cishort < PPP_DEFMRU)
-				try.mru = cishort;
-		);
-	}
-	
-	/*
-	* Add any characters they want to our (receive-side) asyncmap.
-	*/
-	if (go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl) {
-		NAKCILONG(CI_ASYNCMAP, neg_asyncmap,
-			try.asyncmap = go->asyncmap | cilong;
-		);
-	}
-	
-	/*
-	* If they've nak'd our authentication-protocol, check whether
-	* they are proposing a different protocol, or a different
-	* hash algorithm for CHAP.
-	*/
-	if ((go->neg_chap || go->neg_upap)
-			&& len >= CILEN_SHORT
-			&& p[0] == CI_AUTHTYPE && p[1] >= CILEN_SHORT && p[1] <= len) {
-		cilen = p[1];
-	len -= cilen;
-	no.neg_chap = go->neg_chap;
-	no.neg_upap = go->neg_upap;
-	INCPTR(2, p);
-	GETSHORT(cishort, p);
-	if (cishort == PPP_PAP && cilen == CILEN_SHORT) {
-		/*
-		 * If we were asking for CHAP, they obviously don't want to do it.
-		 * If we weren't asking for CHAP, then we were asking for PAP,
-		 * in which case this Nak is bad.
-		 */
-		if (!go->neg_chap)
-			goto bad;
-		try.neg_chap = 0;
-	
-	} else if (cishort == PPP_CHAP && cilen == CILEN_CHAP) {
-		GETCHAR(cichar, p);
-		if (go->neg_chap) {
-			/*
-			 * We were asking for CHAP/MD5; they must want a different
-			 * algorithm.  If they can't do MD5, we'll have to stop
-			 * asking for CHAP.
-			 */
-			if (cichar != go->chap_mdtype)
-				try.neg_chap = 0;
-		} else {
-			/*
-			 * Stop asking for PAP if we were asking for it.
-			 */
-			try.neg_upap = 0;
-		}
-	
-	} else {
-		/*
-		 * We don't recognize what they're suggesting.
-		 * Stop asking for what we were asking for.
-		 */
-		if (go->neg_chap)
-			try.neg_chap = 0;
-		else
-			try.neg_upap = 0;
-		p += cilen - CILEN_SHORT;
-	}
-	}
-	
-	/*
-	* If they can't cope with our link quality protocol, we'll have
-	* to stop asking for LQR.  We haven't got any other protocol.
-	* If they Nak the reporting period, take their value XXX ?
-	*/
-	NAKCILQR(CI_QUALITY, neg_lqr,
-		if (cishort != PPP_LQR)
-			try.neg_lqr = 0;
-		else
-			try.lqr_period = cilong;
-	);
-	
-	/*
-	* Only implementing CBCP...not the rest of the callback options
-	*/
-	NAKCICHAR(CI_CALLBACK, neg_cbcp,
-		try.neg_cbcp = 0;
-	);
-	
-	/*
-	* Check for a looped-back line.
-	*/
-	NAKCILONG(CI_MAGICNUMBER, neg_magicnumber,
-		try.magicnumber = magic();
-		looped_back = 1;
-	);
-	
-	/*
-	* Peer shouldn't send Nak for protocol compression or
-	* address/control compression requests; they should send
-	* a Reject instead.  If they send a Nak, treat it as a Reject.
-	*/
-	NAKCIVOID(CI_PCOMPRESSION, neg_pcompression,
-		try.neg_pcompression = 0;
-	);
-	NAKCIVOID(CI_ACCOMPRESSION, neg_accompression,
-		try.neg_accompression = 0;
-	);
-	
-	/*
-	* There may be remaining CIs, if the peer is requesting negotiation
-	* on an option that we didn't include in our request packet.
-	* If we see an option that we requested, or one we've already seen
-	* in this packet, then this packet is bad.
-	* If we wanted to respond by starting to negotiate on the requested
-	* option(s), we could, but we don't, because except for the
-	* authentication type and quality protocol, if we are not negotiating
-	* an option, it is because we were told not to.
-	* For the authentication type, the Nak from the peer means
-	* `let me authenticate myself with you' which is a bit pointless.
-	* For the quality protocol, the Nak means `ask me to send you quality
-	* reports', but if we didn't ask for them, we don't want them.
-	* An option we don't recognize represents the peer asking to
-	* negotiate some option we don't support, so ignore it.
-	*/
-	while (len > CILEN_VOID) {
-		GETCHAR(citype, p);
-		GETCHAR(cilen, p);
-		if (cilen < CILEN_VOID || (len -= cilen) < 0)
-			goto bad;
-		next = p + cilen - 2;
-		
-		switch (citype) {
-		case CI_MRU:
-			if ((go->neg_mru && go->mru != PPP_DEFMRU)
-					|| no.neg_mru || cilen != CILEN_SHORT)
-				goto bad;
-			GETSHORT(cishort, p);
-			if (cishort < PPP_DEFMRU)
-				try.mru = cishort;
-			break;
-		case CI_ASYNCMAP:
-			if ((go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl)
-					|| no.neg_asyncmap || cilen != CILEN_LONG)
-				goto bad;
-			break;
-		case CI_AUTHTYPE:
-			if (go->neg_chap || no.neg_chap || go->neg_upap || no.neg_upap)
-				goto bad;
-			break;
-		case CI_MAGICNUMBER:
-			if (go->neg_magicnumber || no.neg_magicnumber ||
-					cilen != CILEN_LONG)
-				goto bad;
-			break;
-		case CI_PCOMPRESSION:
-			if (go->neg_pcompression || no.neg_pcompression
-					|| cilen != CILEN_VOID)
-				goto bad;
-			break;
-		case CI_ACCOMPRESSION:
-			if (go->neg_accompression || no.neg_accompression
-					|| cilen != CILEN_VOID)
-				goto bad;
-			break;
-		case CI_QUALITY:
-			if (go->neg_lqr || no.neg_lqr || cilen != CILEN_LQR)
-				goto bad;
-			break;
-		}
-		p = next;
-	}
-	
-	/* If there is still anything left, this packet is bad. */
-	if (len != 0)
-		goto bad;
-	
-	/*
-	* OK, the Nak is good.  Now we can update state.
-	*/
-	if (f->state != OPENED) {
-		if (looped_back) {
-			if (++try.numloops >= lcp_loopbackfail) {
-				LCPDEBUG((LOG_NOTICE, "Serial line is looped back.\n"));
-				lcp_close(f->unit, "Loopback detected");
-			}
-		} 
-		else
-			try.numloops = 0;
-		*go = try;
-	}
-	
-	return 1;
-	
-bad:
-	LCPDEBUG((LOG_WARNING, "lcp_nakci: received bad Nak!\n"));
-	return 0;
-}
-
-
-/*
- * lcp_rejci - Peer has Rejected some of our CIs.
- * This should not modify any state if the Reject is bad
- * or if LCP is in the OPENED state.
- *
- * Returns:
- *	0 - Reject was bad.
- *	1 - Reject was good.
- */
-static int lcp_rejci(fsm *f, u_char *p, int len)
-{
-	lcp_options *go = &lcp_gotoptions[f->unit];
-	u_char cichar;
-	u_short cishort;
-	u32_t cilong;
-	lcp_options try;		/* options to request next time */
-	
-	try = *go;
-	
-	/*
-	* Any Rejected CIs must be in exactly the same order that we sent.
-	* Check packet length and CI length at each step.
-	* If we find any deviations, then this packet is bad.
-	*/
-#define REJCIVOID(opt, neg) \
-	if (go->neg && \
-			len >= CILEN_VOID && \
-			p[1] == CILEN_VOID && \
-			p[0] == opt) { \
-		len -= CILEN_VOID; \
-		INCPTR(CILEN_VOID, p); \
-		try.neg = 0; \
-		LCPDEBUG((LOG_INFO, "lcp_rejci: void opt %d rejected\n", opt)); \
-	}
-#define REJCISHORT(opt, neg, val) \
-	if (go->neg && \
-			len >= CILEN_SHORT && \
-			p[1] == CILEN_SHORT && \
-			p[0] == opt) { \
-		len -= CILEN_SHORT; \
-		INCPTR(2, p); \
-		GETSHORT(cishort, p); \
-		/* Check rejected value. */ \
-		if (cishort != val) \
-			goto bad; \
-		try.neg = 0; \
-		LCPDEBUG((LOG_INFO,"lcp_rejci: short opt %d rejected\n", opt)); \
-	}
-#define REJCICHAP(opt, neg, val, digest) \
-	if (go->neg && \
-			len >= CILEN_CHAP && \
-			p[1] == CILEN_CHAP && \
-			p[0] == opt) { \
-		len -= CILEN_CHAP; \
-		INCPTR(2, p); \
-		GETSHORT(cishort, p); \
-		GETCHAR(cichar, p); \
-		/* Check rejected value. */ \
-		if (cishort != val || cichar != digest) \
-			goto bad; \
-		try.neg = 0; \
-		try.neg_upap = 0; \
-		LCPDEBUG((LOG_INFO,"lcp_rejci: chap opt %d rejected\n", opt)); \
-	}
-#define REJCILONG(opt, neg, val) \
-	if (go->neg && \
-			len >= CILEN_LONG && \
-			p[1] == CILEN_LONG && \
-			p[0] == opt) { \
-		len -= CILEN_LONG; \
-		INCPTR(2, p); \
-		GETLONG(cilong, p); \
-		/* Check rejected value. */ \
-		if (cilong != val) \
-			goto bad; \
-		try.neg = 0; \
-		LCPDEBUG((LOG_INFO,"lcp_rejci: long opt %d rejected\n", opt)); \
-	}
-#define REJCILQR(opt, neg, val) \
-	if (go->neg && \
-			len >= CILEN_LQR && \
-			p[1] == CILEN_LQR && \
-			p[0] == opt) { \
-		len -= CILEN_LQR; \
-		INCPTR(2, p); \
-		GETSHORT(cishort, p); \
-		GETLONG(cilong, p); \
-		/* Check rejected value. */ \
-		if (cishort != PPP_LQR || cilong != val) \
-			goto bad; \
-		try.neg = 0; \
-		LCPDEBUG((LOG_INFO,"lcp_rejci: LQR opt %d rejected\n", opt)); \
-	}
-#define REJCICBCP(opt, neg, val) \
-	if (go->neg && \
-			len >= CILEN_CBCP && \
-			p[1] == CILEN_CBCP && \
-			p[0] == opt) { \
-		len -= CILEN_CBCP; \
-		INCPTR(2, p); \
-		GETCHAR(cichar, p); \
-		/* Check rejected value. */ \
-		if (cichar != val) \
-			goto bad; \
-		try.neg = 0; \
-		LCPDEBUG((LOG_INFO,"lcp_rejci: Callback opt %d rejected\n", opt)); \
-	}
-	
-	REJCISHORT(CI_MRU, neg_mru, go->mru);
-	REJCILONG(CI_ASYNCMAP, neg_asyncmap, go->asyncmap);
-	REJCICHAP(CI_AUTHTYPE, neg_chap, PPP_CHAP, go->chap_mdtype);
-	if (!go->neg_chap) {
-		REJCISHORT(CI_AUTHTYPE, neg_upap, PPP_PAP);
-	}
-	REJCILQR(CI_QUALITY, neg_lqr, go->lqr_period);
-	REJCICBCP(CI_CALLBACK, neg_cbcp, CBCP_OPT);
-	REJCILONG(CI_MAGICNUMBER, neg_magicnumber, go->magicnumber);
-	REJCIVOID(CI_PCOMPRESSION, neg_pcompression);
-	REJCIVOID(CI_ACCOMPRESSION, neg_accompression);
-	
-	/*
-	* If there are any remaining CIs, then this packet is bad.
-	*/
-	if (len != 0)
-		goto bad;
-	/*
-	* Now we can update state.
-	*/
-	if (f->state != OPENED)
-		*go = try;
-	return 1;
-	
-bad:
-	LCPDEBUG((LOG_WARNING, "lcp_rejci: received bad Reject!\n"));
-	return 0;
-}
-
-
-/*
- * lcp_reqci - Check the peer's requested CIs and send appropriate response.
- *
- * Returns: CONFACK, CONFNAK or CONFREJ and input packet modified
- * appropriately.  If reject_if_disagree is non-zero, doesn't return
- * CONFNAK; returns CONFREJ if it can't return CONFACK.
- */
-static int lcp_reqci(fsm *f, 
-						u_char *inp,		/* Requested CIs */
-						int *lenp,			/* Length of requested CIs */
-						int reject_if_disagree)
-{
-	lcp_options *go = &lcp_gotoptions[f->unit];
-	lcp_options *ho = &lcp_hisoptions[f->unit];
-	lcp_options *ao = &lcp_allowoptions[f->unit];
-	u_char *cip, *next;			/* Pointer to current and next CIs */
-	int cilen, citype, cichar;	/* Parsed len, type, char value */
-	u_short cishort;			/* Parsed short value */
-	u32_t cilong;			/* Parse long value */
-	int rc = CONFACK;			/* Final packet return code */
-	int orc;					/* Individual option return code */
-	u_char *p;					/* Pointer to next char to parse */
-	u_char *rejp;				/* Pointer to next char in reject frame */
-	u_char *nakp;				/* Pointer to next char in Nak frame */
-	int l = *lenp;				/* Length left */
-#if TRACELCP > 0
-	char traceBuf[80];
-	int traceNdx = 0;
-#endif
-	
-	/*
-	 * Reset all his options.
-	 */
-	BZERO(ho, sizeof(*ho));
-	
-	/*
-	 * Process all his options.
-	 */
-	next = inp;
-	nakp = nak_buffer;
-	rejp = inp;
-	while (l) {
-		orc = CONFACK;			/* Assume success */
-		cip = p = next;			/* Remember begining of CI */
-		if (l < 2 ||			/* Not enough data for CI header or */
-				p[1] < 2 ||			/*  CI length too small or */
-				p[1] > l) {			/*  CI length too big? */
-			LCPDEBUG((LOG_WARNING, "lcp_reqci: bad CI length!\n"));
-			orc = CONFREJ;		/* Reject bad CI */
-			cilen = l;			/* Reject till end of packet */
-			l = 0;			/* Don't loop again */
-			citype = 0;
-			goto endswitch;
-		}
-		GETCHAR(citype, p);		/* Parse CI type */
-		GETCHAR(cilen, p);		/* Parse CI length */
-		l -= cilen;			/* Adjust remaining length */
-		next += cilen;			/* Step to next CI */
-		
-		switch (citype) {		/* Check CI type */
-		case CI_MRU:
-			if (!ao->neg_mru) {		/* Allow option? */
-				LCPDEBUG((LOG_INFO, "lcp_reqci: Reject MRU - not allowed\n"));
-				orc = CONFREJ;		/* Reject CI */
-				break;
-			} else if (cilen != CILEN_SHORT) {	/* Check CI length */
-				LCPDEBUG((LOG_INFO, "lcp_reqci: Reject MRU - bad length\n"));
-				orc = CONFREJ;		/* Reject CI */
-				break;
-			}
-			GETSHORT(cishort, p);	/* Parse MRU */
-			
-			/*
-			 * He must be able to receive at least our minimum.
-			 * No need to check a maximum.  If he sends a large number,
-			 * we'll just ignore it.
-			 */
-			if (cishort < PPP_MINMRU) {
-				LCPDEBUG((LOG_INFO, "lcp_reqci: Nak - MRU too small\n"));
-				orc = CONFNAK;		/* Nak CI */
-				PUTCHAR(CI_MRU, nakp);
-				PUTCHAR(CILEN_SHORT, nakp);
-				PUTSHORT(PPP_MINMRU, nakp);	/* Give him a hint */
-				break;
-			}
-			ho->neg_mru = 1;		/* Remember he sent MRU */
-			ho->mru = cishort;		/* And remember value */
-#if TRACELCP > 0
-			sprintf(&traceBuf[traceNdx], " MRU %d", cishort);
-			traceNdx = strlen(traceBuf);
-#endif
-			break;
-		
-		case CI_ASYNCMAP:
-			if (!ao->neg_asyncmap) {
-				LCPDEBUG((LOG_INFO, "lcp_reqci: Reject ASYNCMAP not allowed\n"));
-				orc = CONFREJ;
-				break;
-			} else if (cilen != CILEN_LONG) {
-				LCPDEBUG((LOG_INFO, "lcp_reqci: Reject ASYNCMAP bad length\n"));
-				orc = CONFREJ;
-				break;
-			}
-			GETLONG(cilong, p);
-			
-			/*
-			 * Asyncmap must have set at least the bits
-			 * which are set in lcp_allowoptions[unit].asyncmap.
-			 */
-			if ((ao->asyncmap & ~cilong) != 0) {
-				LCPDEBUG((LOG_INFO, "lcp_reqci: Nak ASYNCMAP %lX missing %lX\n", 
-							cilong, ao->asyncmap));
-				orc = CONFNAK;
-				PUTCHAR(CI_ASYNCMAP, nakp);
-				PUTCHAR(CILEN_LONG, nakp);
-				PUTLONG(ao->asyncmap | cilong, nakp);
-				break;
-			}
-			ho->neg_asyncmap = 1;
-			ho->asyncmap = cilong;
-#if TRACELCP > 0
-			sprintf(&traceBuf[traceNdx], " ASYNCMAP=%lX", cilong);
-			traceNdx = strlen(traceBuf);
-#endif
-			break;
-		
-		case CI_AUTHTYPE:
-			if (cilen < CILEN_SHORT) {
-				LCPDEBUG((LOG_INFO, "lcp_reqci: Reject AUTHTYPE missing arg\n"));
-				orc = CONFREJ;
-				break;
-			} else if (!(ao->neg_upap || ao->neg_chap)) {
-				/*
-				 * Reject the option if we're not willing to authenticate.
-				 */
-				LCPDEBUG((LOG_INFO, "lcp_reqci: Reject AUTHTYPE not allowed\n"));
-				orc = CONFREJ;
-				break;
-			}
-			GETSHORT(cishort, p);
-			
-			/*
-			 * Authtype must be UPAP or CHAP.
-			 *
-			 * Note: if both ao->neg_upap and ao->neg_chap are set,
-			 * and the peer sends a Configure-Request with two
-			 * authenticate-protocol requests, one for CHAP and one
-			 * for UPAP, then we will reject the second request.
-			 * Whether we end up doing CHAP or UPAP depends then on
-			 * the ordering of the CIs in the peer's Configure-Request.
-			 */
-			
-			if (cishort == PPP_PAP) {
-				if (ho->neg_chap) {	/* we've already accepted CHAP */
-					LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE PAP already accepted\n"));
-					orc = CONFREJ;
-					break;
-				} else if (cilen != CILEN_SHORT) {
-					LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE PAP bad len\n"));
-					orc = CONFREJ;
-					break;
-				}
-				if (!ao->neg_upap) {	/* we don't want to do PAP */
-					LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE PAP not allowed\n"));
-					orc = CONFNAK;	/* NAK it and suggest CHAP */
-					PUTCHAR(CI_AUTHTYPE, nakp);
-					PUTCHAR(CILEN_CHAP, nakp);
-					PUTSHORT(PPP_CHAP, nakp);
-					PUTCHAR(ao->chap_mdtype, nakp);
-					break;
-				}
-				ho->neg_upap = 1;
-#if TRACELCP > 0
-				sprintf(&traceBuf[traceNdx], " PAP (%X)", cishort);
-				traceNdx = strlen(traceBuf);
-#endif
-				break;
-			}
-			if (cishort == PPP_CHAP) {
-				if (ho->neg_upap) {	/* we've already accepted PAP */
-					LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE CHAP accepted PAP\n"));
-					orc = CONFREJ;
-					break;
-				} else if (cilen != CILEN_CHAP) {
-					LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE CHAP bad len\n"));
-					orc = CONFREJ;
-					break;
-				}
-				if (!ao->neg_chap) {	/* we don't want to do CHAP */
-					LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE CHAP not allowed\n"));
-					orc = CONFNAK;	/* NAK it and suggest PAP */
-					PUTCHAR(CI_AUTHTYPE, nakp);
-					PUTCHAR(CILEN_SHORT, nakp);
-					PUTSHORT(PPP_PAP, nakp);
-					break;
-				}
-				GETCHAR(cichar, p);	/* get digest type*/
-				if (cichar != CHAP_DIGEST_MD5
-#ifdef CHAPMS
-						&& cichar != CHAP_MICROSOFT
-#endif
-				) {
-					LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE CHAP digest=%d\n", cichar));
-					orc = CONFNAK;
-					PUTCHAR(CI_AUTHTYPE, nakp);
-					PUTCHAR(CILEN_CHAP, nakp);
-					PUTSHORT(PPP_CHAP, nakp);
-					PUTCHAR(ao->chap_mdtype, nakp);
-					break;
-				}
-#if TRACELCP > 0
-				sprintf(&traceBuf[traceNdx], " CHAP %X,%d", cishort, cichar);
-				traceNdx = strlen(traceBuf);
-#endif
-				ho->chap_mdtype = cichar; /* save md type */
-				ho->neg_chap = 1;
-				break;
-			}
-			
-			/*
-			 * We don't recognize the protocol they're asking for.
-			 * Nak it with something we're willing to do.
-			 * (At this point we know ao->neg_upap || ao->neg_chap.)
-			 */
-			orc = CONFNAK;
-			PUTCHAR(CI_AUTHTYPE, nakp);
-			if (ao->neg_chap) {
-				LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE %d req CHAP\n", cishort));
-				PUTCHAR(CILEN_CHAP, nakp);
-				PUTSHORT(PPP_CHAP, nakp);
-				PUTCHAR(ao->chap_mdtype, nakp);
-			} 
-			else {
-				LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE %d req PAP\n", cishort));
-				PUTCHAR(CILEN_SHORT, nakp);
-				PUTSHORT(PPP_PAP, nakp);
-			}
-			break;
-		
-		case CI_QUALITY:
-			GETSHORT(cishort, p);
-			GETLONG(cilong, p);
-#if TRACELCP > 0
-			sprintf(&traceBuf[traceNdx], " QUALITY (%x %x)", cishort, (unsigned int) cilong);
-			traceNdx = strlen(traceBuf);
-#endif
-
-			if (!ao->neg_lqr ||
-					cilen != CILEN_LQR) {
-				orc = CONFREJ;
-				break;
-			}
-			
-			/*
-			 * Check the protocol and the reporting period.
-			 * XXX When should we Nak this, and what with?
-			 */
-			if (cishort != PPP_LQR) {
-				orc = CONFNAK;
-				PUTCHAR(CI_QUALITY, nakp);
-				PUTCHAR(CILEN_LQR, nakp);
-				PUTSHORT(PPP_LQR, nakp);
-				PUTLONG(ao->lqr_period, nakp);
-				break;
-			}
-			break;
-		
-		case CI_MAGICNUMBER:
-			if (!(ao->neg_magicnumber || go->neg_magicnumber) ||
-					cilen != CILEN_LONG) {
-				orc = CONFREJ;
-				break;
-			}
-			GETLONG(cilong, p);
-#if TRACELCP > 0
-			sprintf(&traceBuf[traceNdx], " MAGICNUMBER (%lX)", cilong);
-			traceNdx = strlen(traceBuf);
-#endif
-
-			/*
-			 * He must have a different magic number.
-			 */
-			if (go->neg_magicnumber &&
-					cilong == go->magicnumber) {
-				cilong = magic();	/* Don't put magic() inside macro! */
-				orc = CONFNAK;
-				PUTCHAR(CI_MAGICNUMBER, nakp);
-				PUTCHAR(CILEN_LONG, nakp);
-				PUTLONG(cilong, nakp);
-				break;
-			}
-			ho->neg_magicnumber = 1;
-			ho->magicnumber = cilong;
-			break;
-		
-		
-		case CI_PCOMPRESSION:
-#if TRACELCP > 0
-			sprintf(&traceBuf[traceNdx], " PCOMPRESSION");
-			traceNdx = strlen(traceBuf);
-#endif
-			if (!ao->neg_pcompression ||
-					cilen != CILEN_VOID) {
-				orc = CONFREJ;
-				break;
-			}
-			ho->neg_pcompression = 1;
-			break;
-		
-		case CI_ACCOMPRESSION:
-#if TRACELCP > 0
-			sprintf(&traceBuf[traceNdx], " ACCOMPRESSION");
-			traceNdx = strlen(traceBuf);
-#endif
-			if (!ao->neg_accompression ||
-					cilen != CILEN_VOID) {
-				orc = CONFREJ;
-				break;
-			}
-			ho->neg_accompression = 1;
-			break;
-		
-		case CI_MRRU:
-#if TRACELCP > 0
-			sprintf(&traceBuf[traceNdx], " CI_MRRU");
-			traceNdx = strlen(traceBuf);
-#endif
-			orc = CONFREJ;
-			break;
-		
-		case CI_SSNHF:
-#if TRACELCP > 0
-			sprintf(&traceBuf[traceNdx], " CI_SSNHF");
-			traceNdx = strlen(traceBuf);
-#endif
-			orc = CONFREJ;
-			break;
-		
-		case CI_EPDISC:
-#if TRACELCP > 0
-			sprintf(&traceBuf[traceNdx], " CI_EPDISC");
-			traceNdx = strlen(traceBuf);
-#endif
-			orc = CONFREJ;
-			break;
-		
-		default:
-#if TRACELCP
-			sprintf(&traceBuf[traceNdx], " unknown %d", citype);
-			traceNdx = strlen(traceBuf);
-#endif
-			orc = CONFREJ;
-			break;
-		}
-		
-	endswitch:
-#if TRACELCP
-		if (traceNdx >= 80 - 32) {
-			LCPDEBUG((LOG_INFO, "lcp_reqci: rcvd%s\n", traceBuf));
-			traceNdx = 0;
-		}
-#endif
-		if (orc == CONFACK &&		/* Good CI */
-				rc != CONFACK)		/*  but prior CI wasnt? */
-			continue;			/* Don't send this one */
-		
-		if (orc == CONFNAK) {		/* Nak this CI? */
-			if (reject_if_disagree	/* Getting fed up with sending NAKs? */
-					&& citype != CI_MAGICNUMBER) {
-				orc = CONFREJ;		/* Get tough if so */
-			} 
-			else {
-				if (rc == CONFREJ)	/* Rejecting prior CI? */
-					continue;		/* Don't send this one */
-				rc = CONFNAK;
-			}
-		}
-		if (orc == CONFREJ) {		/* Reject this CI */
-			rc = CONFREJ;
-			if (cip != rejp)		/* Need to move rejected CI? */
-				BCOPY(cip, rejp, cilen); /* Move it */
-			INCPTR(cilen, rejp);	/* Update output pointer */
-		}
-	}
-	
-	/*
-	 * If we wanted to send additional NAKs (for unsent CIs), the
-	 * code would go here.  The extra NAKs would go at *nakp.
-	 * At present there are no cases where we want to ask the
-	 * peer to negotiate an option.
-	 */
-	
-	switch (rc) {
-	case CONFACK:
-		*lenp = (int)(next - inp);
-		break;
-	case CONFNAK:
-		/*
-		 * Copy the Nak'd options from the nak_buffer to the caller's buffer.
-		 */
-		*lenp = (int)(nakp - nak_buffer);
-		BCOPY(nak_buffer, inp, *lenp);
-		break;
-	case CONFREJ:
-		*lenp = (int)(rejp - inp);
-		break;
-	}
-	
-#if TRACELCP > 0
-	if (traceNdx > 0) {
-		LCPDEBUG((LOG_INFO, "lcp_reqci: %s\n", traceBuf));
-	}
-#endif
-	LCPDEBUG((LOG_INFO, "lcp_reqci: returning CONF%s.\n", CODENAME(rc)));
-	return (rc);			/* Return final code */
-}
-
-
-/*
- * lcp_up - LCP has come UP.
- */
-static void lcp_up(fsm *f)
-{
-	lcp_options *wo = &lcp_wantoptions[f->unit];
-	lcp_options *ho = &lcp_hisoptions[f->unit];
-	lcp_options *go = &lcp_gotoptions[f->unit];
-	lcp_options *ao = &lcp_allowoptions[f->unit];
-	
-	if (!go->neg_magicnumber)
-		go->magicnumber = 0;
-	if (!ho->neg_magicnumber)
-		ho->magicnumber = 0;
-	
-	/*
-	* Set our MTU to the smaller of the MTU we wanted and
-	* the MRU our peer wanted.  If we negotiated an MRU,
-	* set our MRU to the larger of value we wanted and
-	* the value we got in the negotiation.
-	*/
-	ppp_send_config(f->unit, LWIP_MIN(ao->mru, (ho->neg_mru? ho->mru: PPP_MRU)),
-				(ho->neg_asyncmap? ho->asyncmap: 0xffffffffl),
-				ho->neg_pcompression, ho->neg_accompression);
-	/*
-	* If the asyncmap hasn't been negotiated, we really should
-	* set the receive asyncmap to ffffffff, but we set it to 0
-	* for backwards contemptibility.
-	*/
-	ppp_recv_config(f->unit, (go->neg_mru? LWIP_MAX(wo->mru, go->mru): PPP_MRU),
-				(go->neg_asyncmap? go->asyncmap: 0x00000000),
-				go->neg_pcompression, go->neg_accompression);
-	
-	if (ho->neg_mru)
-		peer_mru[f->unit] = ho->mru;
-	
-	lcp_echo_lowerup(f->unit);  /* Enable echo messages */
-	
-	link_established(f->unit);
-}
-
-
-/*
- * lcp_down - LCP has gone DOWN.
- *
- * Alert other protocols.
- */
-static void lcp_down(fsm *f)
-{
-	lcp_options *go = &lcp_gotoptions[f->unit];
-	
-	lcp_echo_lowerdown(f->unit);
-	
-	link_down(f->unit);
-	
-	ppp_send_config(f->unit, PPP_MRU, 0xffffffffl, 0, 0);
-	ppp_recv_config(f->unit, PPP_MRU,
-				(go->neg_asyncmap? go->asyncmap: 0x00000000),
-				go->neg_pcompression, go->neg_accompression);
-	peer_mru[f->unit] = PPP_MRU;
-}
-
-
-/*
- * lcp_starting - LCP needs the lower layer up.
- */
-static void lcp_starting(fsm *f)
-{
-	link_required(f->unit);
-}
-
-
-/*
- * lcp_finished - LCP has finished with the lower layer.
- */
-static void lcp_finished(fsm *f)
-{
-	link_terminated(f->unit);
-}
-
-
-#if 0
-/*
- * print_string - print a readable representation of a string using
- * printer.
- */
-static void print_string(
-    char *p,
-    int len,
-    void (*printer) (void *, char *, ...),
-    void *arg
-)
-{
-    int c;
-    
-    printer(arg, "\"");
-    for (; len > 0; --len) {
-        c = *p++;
-        if (' ' <= c && c <= '~') {
-            if (c == '\\' || c == '"')
-                printer(arg, "\\");
-            printer(arg, "%c", c);
-        } else {
-            switch (c) {
-            case '\n':
-                printer(arg, "\\n");
-                break;
-            case '\r':
-                printer(arg, "\\r");
-                break;
-            case '\t':
-                printer(arg, "\\t");
-                break;
-            default:
-                printer(arg, "\\%.3o", c);
-            }
-        }
-    }
-    printer(arg, "\"");
-}
-
-
-/*
- * lcp_printpkt - print the contents of an LCP packet.
- */
-static char *lcp_codenames[] = {
-	"ConfReq", "ConfAck", "ConfNak", "ConfRej",
-	"TermReq", "TermAck", "CodeRej", "ProtRej",
-	"EchoReq", "EchoRep", "DiscReq"
-};
-
-static int lcp_printpkt(
-	u_char *p,
-	int plen,
-	void (*printer) (void *, char *, ...),
-	void *arg
-)
-{
-	int code, id, len, olen;
-	u_char *pstart, *optend;
-	u_short cishort;
-	u32_t cilong;
-	
-	if (plen < HEADERLEN)
-		return 0;
-	pstart = p;
-	GETCHAR(code, p);
-	GETCHAR(id, p);
-	GETSHORT(len, p);
-	if (len < HEADERLEN || len > plen)
-		return 0;
-	
-	if (code >= 1 && code <= sizeof(lcp_codenames) / sizeof(char *))
-		printer(arg, " %s", lcp_codenames[code-1]);
-	else
-		printer(arg, " code=0x%x", code);
-	printer(arg, " id=0x%x", id);
-	len -= HEADERLEN;
-	switch (code) {
-	case CONFREQ:
-	case CONFACK:
-	case CONFNAK:
-	case CONFREJ:
-		/* print option list */
-		while (len >= 2) {
-			GETCHAR(code, p);
-			GETCHAR(olen, p);
-			p -= 2;
-			if (olen < 2 || olen > len) {
-				break;
-			}
-			printer(arg, " <");
-			len -= olen;
-			optend = p + olen;
-			switch (code) {
-			case CI_MRU:
-				if (olen == CILEN_SHORT) {
-					p += 2;
-					GETSHORT(cishort, p);
-					printer(arg, "mru %d", cishort);
-				}
-				break;
-			case CI_ASYNCMAP:
-				if (olen == CILEN_LONG) {
-					p += 2;
-					GETLONG(cilong, p);
-					printer(arg, "asyncmap 0x%lx", cilong);
-				}
-				break;
-			case CI_AUTHTYPE:
-				if (olen >= CILEN_SHORT) {
-					p += 2;
-					printer(arg, "auth ");
-					GETSHORT(cishort, p);
-					switch (cishort) {
-					case PPP_PAP:
-						printer(arg, "pap");
-						break;
-					case PPP_CHAP:
-						printer(arg, "chap");
-						break;
-					default:
-						printer(arg, "0x%x", cishort);
-					}
-				}
-				break;
-			case CI_QUALITY:
-				if (olen >= CILEN_SHORT) {
-					p += 2;
-					printer(arg, "quality ");
-					GETSHORT(cishort, p);
-					switch (cishort) {
-					case PPP_LQR:
-						printer(arg, "lqr");
-						break;
-					default:
-						printer(arg, "0x%x", cishort);
-					}
-				}
-				break;
-			case CI_CALLBACK:
-				if (olen >= CILEN_CHAR) {
-					p += 2;
-					printer(arg, "callback ");
-					GETSHORT(cishort, p);
-					switch (cishort) {
-					case CBCP_OPT:
-						printer(arg, "CBCP");
-						break;
-					default:
-						printer(arg, "0x%x", cishort);
-					}
-				}
-				break;
-			case CI_MAGICNUMBER:
-				if (olen == CILEN_LONG) {
-					p += 2;
-					GETLONG(cilong, p);
-					printer(arg, "magic 0x%x", cilong);
-				}
-				break;
-			case CI_PCOMPRESSION:
-				if (olen == CILEN_VOID) {
-					p += 2;
-					printer(arg, "pcomp");
-				}
-				break;
-			case CI_ACCOMPRESSION:
-				if (olen == CILEN_VOID) {
-					p += 2;
-					printer(arg, "accomp");
-				}
-				break;
-			}
-			while (p < optend) {
-				GETCHAR(code, p);
-				printer(arg, " %.2x", code);
-			}
-			printer(arg, ">");
-		}
-		break;
-	
-	case TERMACK:
-	case TERMREQ:
-		if (len > 0 && *p >= ' ' && *p < 0x7f) {
-			printer(arg, " ");
-			print_string((char*)p, len, printer, arg);
-			p += len;
-			len = 0;
-		}
-		break;
-	
-	case ECHOREQ:
-	case ECHOREP:
-	case DISCREQ:
-		if (len >= 4) {
-			GETLONG(cilong, p);
-			printer(arg, " magic=0x%x", cilong);
-			p += 4;
-			len -= 4;
-		}
-		break;
-	}
-	
-	/* print the rest of the bytes in the packet */
-	for (; len > 0; --len) {
-		GETCHAR(code, p);
-		printer(arg, " %.2x", code);
-	}
-	
-	return (int)(p - pstart);
-}
-#endif
-
-/*
- * Time to shut down the link because there is nothing out there.
- */
-
-static void LcpLinkFailure (fsm *f)
-{
-	if (f->state == OPENED) {
-		LCPDEBUG((LOG_INFO, "No response to %d echo-requests\n", lcp_echos_pending));
-		LCPDEBUG((LOG_NOTICE, "Serial link appears to be disconnected.\n"));
-		lcp_close(f->unit, "Peer not responding");
-	}
-}
-
-/*
- * Timer expired for the LCP echo requests from this process.
- */
-
-static void LcpEchoCheck (fsm *f)
-{
-	LcpSendEchoRequest (f);
-	
-	/*
-	 * Start the timer for the next interval.
-	 */
-	LWIP_ASSERT("lcp_echo_timer_running == 0", lcp_echo_timer_running == 0);
-
-	TIMEOUT (LcpEchoTimeout, f, lcp_echo_interval);
-	lcp_echo_timer_running = 1;
-}
-
-/*
- * LcpEchoTimeout - Timer expired on the LCP echo
- */
-
-static void LcpEchoTimeout (void *arg)
-{
-	if (lcp_echo_timer_running != 0) {
-		lcp_echo_timer_running = 0;
-		LcpEchoCheck ((fsm *) arg);
-	}
-}
-
-/*
- * LcpEchoReply - LCP has received a reply to the echo
- */
-static void lcp_received_echo_reply (fsm *f, int id, u_char *inp, int len)
-{
-	u32_t magic;
-	
-	(void)id;
-
-	/* Check the magic number - don't count replies from ourselves. */
-	if (len < 4) {
-		LCPDEBUG((LOG_WARNING, "lcp: received short Echo-Reply, length %d\n", len));
-		return;
-	}
-	GETLONG(magic, inp);
-	if (lcp_gotoptions[f->unit].neg_magicnumber
-			&& magic == lcp_gotoptions[f->unit].magicnumber) {
-		LCPDEBUG((LOG_WARNING, "appear to have received our own echo-reply!\n"));
-		return;
-	}
-	
-	/* Reset the number of outstanding echo frames */
-	lcp_echos_pending = 0;
-}
-
-/*
- * LcpSendEchoRequest - Send an echo request frame to the peer
- */
-
-static void LcpSendEchoRequest (fsm *f)
-{
-	u32_t lcp_magic;
-	u_char pkt[4], *pktp;
-	
-	/*
-	* Detect the failure of the peer at this point.
-	*/
-	if (lcp_echo_fails != 0) {
-		if (lcp_echos_pending++ >= lcp_echo_fails) {
-			LcpLinkFailure(f);
-			lcp_echos_pending = 0;
-		}
-	}
-	
-	/*
-	* Make and send the echo request frame.
-	*/
-	if (f->state == OPENED) {
-		lcp_magic = lcp_gotoptions[f->unit].magicnumber;
-		pktp = pkt;
-		PUTLONG(lcp_magic, pktp);
-		fsm_sdata(f, ECHOREQ, (u_char)(lcp_echo_number++ & 0xFF), pkt, (int)(pktp - pkt));
-	}
-}
-
-/*
- * lcp_echo_lowerup - Start the timer for the LCP frame
- */
-
-static void lcp_echo_lowerup (int unit)
-{
-	fsm *f = &lcp_fsm[unit];
-	
-	/* Clear the parameters for generating echo frames */
-	lcp_echos_pending      = 0;
-	lcp_echo_number        = 0;
-	lcp_echo_timer_running = 0;
-	
-	/* If a timeout interval is specified then start the timer */
-	if (lcp_echo_interval != 0)
-		LcpEchoCheck (f);
-}
-
-/*
- * lcp_echo_lowerdown - Stop the timer for the LCP frame
- */
-
-static void lcp_echo_lowerdown (int unit)
-{
-	fsm *f = &lcp_fsm[unit];
-	
-	if (lcp_echo_timer_running != 0) {
-		UNTIMEOUT (LcpEchoTimeout, f);
-		lcp_echo_timer_running = 0;
-	}
-}
-
-#endif /* PPP_SUPPORT */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/lcp.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/lcp.h
deleted file mode 100644
index 3876d39ae..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/lcp.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/*****************************************************************************
-* lcp.h - Network Link Control Protocol header file.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* portions Copyright (c) 1997 Global Election Systems Inc.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY
-*
-* 03-01-01 Marc Boucher 
-*   Ported to lwIP.
-* 97-11-05 Guy Lancaster , Global Election Systems Inc.
-*	Original derived from BSD codes.
-*****************************************************************************/
-/*
- * lcp.h - Link Control Protocol definitions.
- *
- * Copyright (c) 1989 Carnegie Mellon University.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by Carnegie Mellon University.  The name of the
- * University may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- *
- * $Id: lcp.h,v 1.1 2003/05/27 14:37:56 jani Exp $
- */
-
-#ifndef LCP_H
-#define LCP_H
-
-
-/*************************
-*** PUBLIC DEFINITIONS ***
-*************************/
-/*
- * Options.
- */
-#define CI_MRU		1	/* Maximum Receive Unit */
-#define CI_ASYNCMAP	2	/* Async Control Character Map */
-#define CI_AUTHTYPE	3	/* Authentication Type */
-#define CI_QUALITY	4	/* Quality Protocol */
-#define CI_MAGICNUMBER	5	/* Magic Number */
-#define CI_PCOMPRESSION	7	/* Protocol Field Compression */
-#define CI_ACCOMPRESSION 8	/* Address/Control Field Compression */
-#define CI_CALLBACK	13	/* callback */
-#define CI_MRRU		17	/* max reconstructed receive unit; multilink */
-#define CI_SSNHF	18	/* short sequence numbers for multilink */
-#define CI_EPDISC	19	/* endpoint discriminator */
-
-/*
- * LCP-specific packet types.
- */
-#define PROTREJ		8	/* Protocol Reject */
-#define ECHOREQ		9	/* Echo Request */
-#define ECHOREP		10	/* Echo Reply */
-#define DISCREQ		11	/* Discard Request */
-#define CBCP_OPT	6	/* Use callback control protocol */
-
-
-/************************
-*** PUBLIC DATA TYPES ***
-************************/
-
-/*
- * The state of options is described by an lcp_options structure.
- */
-typedef struct lcp_options {
-    u_int passive : 1;			/* Don't die if we don't get a response */
-    u_int silent : 1;				/* Wait for the other end to start first */
-    u_int restart : 1;			/* Restart vs. exit after close */
-    u_int neg_mru : 1;			/* Negotiate the MRU? */
-    u_int neg_asyncmap : 1;		/* Negotiate the async map? */
-    u_int neg_upap : 1;			/* Ask for UPAP authentication? */
-    u_int neg_chap : 1;			/* Ask for CHAP authentication? */
-    u_int neg_magicnumber : 1;	/* Ask for magic number? */
-    u_int neg_pcompression : 1;	/* HDLC Protocol Field Compression? */
-    u_int neg_accompression : 1;	/* HDLC Address/Control Field Compression? */
-    u_int neg_lqr : 1;			/* Negotiate use of Link Quality Reports */
-    u_int neg_cbcp : 1;			/* Negotiate use of CBCP */
-#ifdef PPP_MULTILINK
-    u_int neg_mrru : 1;			/* Negotiate multilink MRRU */
-    u_int neg_ssnhf : 1;		/* Negotiate short sequence numbers */
-    u_int neg_endpoint : 1;		/* Negotiate endpoint discriminator */
-#endif
-    u_short mru;			/* Value of MRU */
-#ifdef PPP_MULTILINK
-    u_short mrru;			/* Value of MRRU, and multilink enable */
-#endif
-    u_char chap_mdtype;			/* which MD type (hashing algorithm) */
-    u32_t asyncmap;			/* Value of async map */
-    u32_t magicnumber;
-    int numloops;				/* Number of loops during magic number neg. */
-    u32_t lqr_period;		/* Reporting period for LQR 1/100ths second */
-#ifdef PPP_MULTILINK
-    struct epdisc endpoint;	/* endpoint discriminator */
-#endif
-} lcp_options;
-
-/*
- * Values for phase from BSD pppd.h based on RFC 1661.
- */
-typedef enum {
-	PHASE_DEAD = 0,
-	PHASE_INITIALIZE,
-	PHASE_ESTABLISH,
-	PHASE_AUTHENTICATE,
-	PHASE_CALLBACK,
-	PHASE_NETWORK,
-	PHASE_TERMINATE
-} LinkPhase;
-
-
-/*****************************
-*** PUBLIC DATA STRUCTURES ***
-*****************************/
-
-extern LinkPhase lcp_phase[NUM_PPP];	/* Phase of link session (RFC 1661) */
-extern lcp_options lcp_wantoptions[];
-extern lcp_options lcp_gotoptions[];
-extern lcp_options lcp_allowoptions[];
-extern lcp_options lcp_hisoptions[];
-extern ext_accm xmit_accm[];
-
-
-/***********************
-*** PUBLIC FUNCTIONS ***
-***********************/
-
-void lcp_init (int);
-void lcp_open (int);
-void lcp_close (int, char *);
-void lcp_lowerup (int);
-void lcp_lowerdown (int);
-void lcp_sprotrej (int, u_char *, int);	/* send protocol reject */
-
-extern struct protent lcp_protent;
-
-/* Default number of times we receive our magic number from the peer
-   before deciding the link is looped-back. */
-#define DEFLOOPBACKFAIL	10
-
-#endif /* LCP_H */
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/magic.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/magic.c
deleted file mode 100644
index 427401691..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/magic.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*****************************************************************************
-* magic.c - Network Random Number Generator program file.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* portions Copyright (c) 1997 by Global Election Systems Inc.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY
-*
-* 03-01-01 Marc Boucher 
-*   Ported to lwIP.
-* 97-12-04 Guy Lancaster , Global Election Systems Inc.
-*	Original based on BSD magic.c.
-*****************************************************************************/
-/*
- * magic.c - PPP Magic Number routines.
- *
- * Copyright (c) 1989 Carnegie Mellon University.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by Carnegie Mellon University.  The name of the
- * University may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- */
-
-#include "ppp.h"
-#include "randm.h"
-#include "magic.h"
-
-
-/***********************************/
-/*** PUBLIC FUNCTION DEFINITIONS ***/
-/***********************************/
-/*
- * magicInit - Initialize the magic number generator.
- *
- * Since we use another random number generator that has its own
- * initialization, we do nothing here.
- */
-void magicInit()
-{
-	return;
-}
-
-/*
- * magic - Returns the next magic number.
- */
-u32_t magic()
-{
-    return avRandom();
-}
-
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/magic.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/magic.h
deleted file mode 100644
index 7574f32b9..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/magic.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*****************************************************************************
-* magic.h - Network Random Number Generator header file.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* portions Copyright (c) 1997 Global Election Systems Inc.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY
-*
-* 03-01-01 Marc Boucher 
-*   Ported to lwIP.
-* 97-12-04 Guy Lancaster , Global Election Systems Inc.
-*   Original derived from BSD codes.
-*****************************************************************************/
-/*
- * magic.h - PPP Magic Number definitions.
- *
- * Copyright (c) 1989 Carnegie Mellon University.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by Carnegie Mellon University.  The name of the
- * University may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- *
- * $Id: magic.h,v 1.1 2003/05/27 14:37:56 jani Exp $
- */
-
-#ifndef MAGIC_H
-#define MAGIC_H
-
-/*****************************************************************************
-************************** PUBLIC FUNCTIONS **********************************
-*****************************************************************************/
-
-void magicInit(void);   /* Initialize the magic number generator */
-u32_t magic(void);  /* Returns the next magic number */
-
-#endif /* MAGIC_H */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/md5.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/md5.c
deleted file mode 100644
index e077cdea5..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/md5.c
+++ /dev/null
@@ -1,306 +0,0 @@
-/*
- ***********************************************************************
- ** md5.c -- the source code for MD5 routines                         **
- ** RSA Data Security, Inc. MD5 Message-Digest Algorithm              **
- ** Created: 2/17/90 RLR                                              **
- ** Revised: 1/91 SRD,AJ,BSK,JT Reference C ver., 7/10 constant corr. **
- ***********************************************************************
- */
-
-/*
- ***********************************************************************
- ** Copyright (C) 1990, RSA Data Security, Inc. All rights reserved.  **
- **                                                                   **
- ** License to copy and use this software is granted provided that    **
- ** it is identified as the "RSA Data Security, Inc. MD5 Message-     **
- ** Digest Algorithm" in all material mentioning or referencing this  **
- ** software or this function.                                        **
- **                                                                   **
- ** License is also granted to make and use derivative works          **
- ** provided that such works are identified as "derived from the RSA  **
- ** Data Security, Inc. MD5 Message-Digest Algorithm" in all          **
- ** material mentioning or referencing the derived work.              **
- **                                                                   **
- ** RSA Data Security, Inc. makes no representations concerning       **
- ** either the merchantability of this software or the suitability    **
- ** of this software for any particular purpose.  It is provided "as  **
- ** is" without express or implied warranty of any kind.              **
- **                                                                   **
- ** These notices must be retained in any copies of any part of this  **
- ** documentation and/or software.                                    **
- ***********************************************************************
- */
-
-#include "ppp.h"
-#include "md5.h"
-#include "pppdebug.h"
-
-#if CHAP_SUPPORT > 0 || MD5_SUPPORT > 0
-
-/*
- ***********************************************************************
- **  Message-digest routines:                                         **
- **  To form the message digest for a message M                       **
- **    (1) Initialize a context buffer mdContext using MD5Init        **
- **    (2) Call MD5Update on mdContext and M                          **
- **    (3) Call MD5Final on mdContext                                 **
- **  The message digest is now in mdContext->digest[0...15]           **
- ***********************************************************************
- */
-
-/* forward declaration */
-static void Transform (u32_t *buf, u32_t *in);
-
-static unsigned char PADDING[64] = {
-  0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
-};
-
-/* F, G, H and I are basic MD5 functions */
-#define F(x, y, z) (((x) & (y)) | ((~x) & (z)))
-#define G(x, y, z) (((x) & (z)) | ((y) & (~z)))
-#define H(x, y, z) ((x) ^ (y) ^ (z))
-#define I(x, y, z) ((y) ^ ((x) | (~z)))
-
-/* ROTATE_LEFT rotates x left n bits */
-#define ROTATE_LEFT(x, n) (((x) << (n)) | ((x) >> (32-(n))))
-
-/* FF, GG, HH, and II transformations for rounds 1, 2, 3, and 4 */
-/* Rotation is separate from addition to prevent recomputation */
-#define FF(a, b, c, d, x, s, ac) \
-  {(a) += F ((b), (c), (d)) + (x) + (u32_t)(ac); \
-   (a) = ROTATE_LEFT ((a), (s)); \
-   (a) += (b); \
-  }
-#define GG(a, b, c, d, x, s, ac) \
-  {(a) += G ((b), (c), (d)) + (x) + (u32_t)(ac); \
-   (a) = ROTATE_LEFT ((a), (s)); \
-   (a) += (b); \
-  }
-#define HH(a, b, c, d, x, s, ac) \
-  {(a) += H ((b), (c), (d)) + (x) + (u32_t)(ac); \
-   (a) = ROTATE_LEFT ((a), (s)); \
-   (a) += (b); \
-  }
-#define II(a, b, c, d, x, s, ac) \
-  {(a) += I ((b), (c), (d)) + (x) + (u32_t)(ac); \
-   (a) = ROTATE_LEFT ((a), (s)); \
-   (a) += (b); \
-  }
-
-#ifdef __STDC__
-#define UL(x)	x##UL
-#else
-#ifdef WIN32
-#define UL(x)	x##UL
-#else
-#define UL(x)	x
-#endif
-#endif
-
-/* The routine MD5Init initializes the message-digest context
-   mdContext. All fields are set to zero.
- */
-void MD5Init (MD5_CTX *mdContext)
-{
-  mdContext->i[0] = mdContext->i[1] = (u32_t)0;
-
-  /* Load magic initialization constants.
-   */
-  mdContext->buf[0] = (u32_t)0x67452301UL;
-  mdContext->buf[1] = (u32_t)0xefcdab89UL;
-  mdContext->buf[2] = (u32_t)0x98badcfeUL;
-  mdContext->buf[3] = (u32_t)0x10325476UL;
-}
-
-/* The routine MD5Update updates the message-digest context to
-   account for the presence of each of the characters inBuf[0..inLen-1]
-   in the message whose digest is being computed.
- */
-void MD5Update(MD5_CTX *mdContext, unsigned char *inBuf, unsigned int inLen)
-{
-  u32_t in[16];
-  int mdi;
-  unsigned int i, ii;
-
-#if 0
-  ppp_trace(LOG_INFO, "MD5Update: %u:%.*H\n", inLen, MIN(inLen, 20) * 2, inBuf);
-  ppp_trace(LOG_INFO, "MD5Update: %u:%s\n", inLen, inBuf);
-#endif
-  
-  /* compute number of bytes mod 64 */
-  mdi = (int)((mdContext->i[0] >> 3) & 0x3F);
-
-  /* update number of bits */
-  if ((mdContext->i[0] + ((u32_t)inLen << 3)) < mdContext->i[0])
-    mdContext->i[1]++;
-  mdContext->i[0] += ((u32_t)inLen << 3);
-  mdContext->i[1] += ((u32_t)inLen >> 29);
-
-  while (inLen--) {
-    /* add new character to buffer, increment mdi */
-    mdContext->in[mdi++] = *inBuf++;
-
-    /* transform if necessary */
-    if (mdi == 0x40) {
-      for (i = 0, ii = 0; i < 16; i++, ii += 4)
-        in[i] = (((u32_t)mdContext->in[ii+3]) << 24) |
-                (((u32_t)mdContext->in[ii+2]) << 16) |
-				(((u32_t)mdContext->in[ii+1]) << 8) |
-                ((u32_t)mdContext->in[ii]);
-      Transform (mdContext->buf, in);
-      mdi = 0;
-    }
-  }
-}
-
-/* The routine MD5Final terminates the message-digest computation and
-   ends with the desired message digest in mdContext->digest[0...15].
- */
-void MD5Final (unsigned char hash[], MD5_CTX *mdContext)
-{
-  u32_t in[16];
-  int mdi;
-  unsigned int i, ii;
-  unsigned int padLen;
-
-  /* save number of bits */
-  in[14] = mdContext->i[0];
-  in[15] = mdContext->i[1];
-
-  /* compute number of bytes mod 64 */
-  mdi = (int)((mdContext->i[0] >> 3) & 0x3F);
-
-  /* pad out to 56 mod 64 */
-  padLen = (mdi < 56) ? (56 - mdi) : (120 - mdi);
-  MD5Update (mdContext, PADDING, padLen);
-
-  /* append length in bits and transform */
-  for (i = 0, ii = 0; i < 14; i++, ii += 4)
-    in[i] = (((u32_t)mdContext->in[ii+3]) << 24) |
-            (((u32_t)mdContext->in[ii+2]) << 16) |
-            (((u32_t)mdContext->in[ii+1]) << 8) |
-            ((u32_t)mdContext->in[ii]);
-  Transform (mdContext->buf, in);
-
-  /* store buffer in digest */
-  for (i = 0, ii = 0; i < 4; i++, ii += 4) {
-    mdContext->digest[ii] = (unsigned char)(mdContext->buf[i] & 0xFF);
-	mdContext->digest[ii+1] =
-      (unsigned char)((mdContext->buf[i] >> 8) & 0xFF);
-    mdContext->digest[ii+2] =
-      (unsigned char)((mdContext->buf[i] >> 16) & 0xFF);
-    mdContext->digest[ii+3] =
-      (unsigned char)((mdContext->buf[i] >> 24) & 0xFF);
-  }
-  memcpy(hash, mdContext->digest, 16);
-}
-
-/* Basic MD5 step. Transforms buf based on in.
- */
-static void Transform (u32_t *buf, u32_t *in)
-{
-  u32_t a = buf[0], b = buf[1], c = buf[2], d = buf[3];
-
-  /* Round 1 */
-#define S11 7
-#define S12 12
-#define S13 17
-#define S14 22
-  FF ( a, b, c, d, in[ 0], S11, UL(3614090360)); /* 1 */
-  FF ( d, a, b, c, in[ 1], S12, UL(3905402710)); /* 2 */
-  FF ( c, d, a, b, in[ 2], S13, UL( 606105819)); /* 3 */
-  FF ( b, c, d, a, in[ 3], S14, UL(3250441966)); /* 4 */
-  FF ( a, b, c, d, in[ 4], S11, UL(4118548399)); /* 5 */
-  FF ( d, a, b, c, in[ 5], S12, UL(1200080426)); /* 6 */
-  FF ( c, d, a, b, in[ 6], S13, UL(2821735955)); /* 7 */
-  FF ( b, c, d, a, in[ 7], S14, UL(4249261313)); /* 8 */
-  FF ( a, b, c, d, in[ 8], S11, UL(1770035416)); /* 9 */
-  FF ( d, a, b, c, in[ 9], S12, UL(2336552879)); /* 10 */
-  FF ( c, d, a, b, in[10], S13, UL(4294925233)); /* 11 */
-  FF ( b, c, d, a, in[11], S14, UL(2304563134)); /* 12 */
-  FF ( a, b, c, d, in[12], S11, UL(1804603682)); /* 13 */
-  FF ( d, a, b, c, in[13], S12, UL(4254626195)); /* 14 */
-  FF ( c, d, a, b, in[14], S13, UL(2792965006)); /* 15 */
-  FF ( b, c, d, a, in[15], S14, UL(1236535329)); /* 16 */
-
-  /* Round 2 */
-#define S21 5
-#define S22 9
-#define S23 14
-#define S24 20
-  GG ( a, b, c, d, in[ 1], S21, UL(4129170786)); /* 17 */
-  GG ( d, a, b, c, in[ 6], S22, UL(3225465664)); /* 18 */
-  GG ( c, d, a, b, in[11], S23, UL( 643717713)); /* 19 */
-  GG ( b, c, d, a, in[ 0], S24, UL(3921069994)); /* 20 */
-  GG ( a, b, c, d, in[ 5], S21, UL(3593408605)); /* 21 */
-  GG ( d, a, b, c, in[10], S22, UL(  38016083)); /* 22 */
-  GG ( c, d, a, b, in[15], S23, UL(3634488961)); /* 23 */
-  GG ( b, c, d, a, in[ 4], S24, UL(3889429448)); /* 24 */
-  GG ( a, b, c, d, in[ 9], S21, UL( 568446438)); /* 25 */
-  GG ( d, a, b, c, in[14], S22, UL(3275163606)); /* 26 */
-  GG ( c, d, a, b, in[ 3], S23, UL(4107603335)); /* 27 */
-  GG ( b, c, d, a, in[ 8], S24, UL(1163531501)); /* 28 */
-  GG ( a, b, c, d, in[13], S21, UL(2850285829)); /* 29 */
-  GG ( d, a, b, c, in[ 2], S22, UL(4243563512)); /* 30 */
-  GG ( c, d, a, b, in[ 7], S23, UL(1735328473)); /* 31 */
-  GG ( b, c, d, a, in[12], S24, UL(2368359562)); /* 32 */
-
-  /* Round 3 */
-#define S31 4
-#define S32 11
-#define S33 16
-#define S34 23
-  HH ( a, b, c, d, in[ 5], S31, UL(4294588738)); /* 33 */
-  HH ( d, a, b, c, in[ 8], S32, UL(2272392833)); /* 34 */
-  HH ( c, d, a, b, in[11], S33, UL(1839030562)); /* 35 */
-  HH ( b, c, d, a, in[14], S34, UL(4259657740)); /* 36 */
-  HH ( a, b, c, d, in[ 1], S31, UL(2763975236)); /* 37 */
-  HH ( d, a, b, c, in[ 4], S32, UL(1272893353)); /* 38 */
-  HH ( c, d, a, b, in[ 7], S33, UL(4139469664)); /* 39 */
-  HH ( b, c, d, a, in[10], S34, UL(3200236656)); /* 40 */
-  HH ( a, b, c, d, in[13], S31, UL( 681279174)); /* 41 */
-  HH ( d, a, b, c, in[ 0], S32, UL(3936430074)); /* 42 */
-  HH ( c, d, a, b, in[ 3], S33, UL(3572445317)); /* 43 */
-  HH ( b, c, d, a, in[ 6], S34, UL(  76029189)); /* 44 */
-  HH ( a, b, c, d, in[ 9], S31, UL(3654602809)); /* 45 */
-  HH ( d, a, b, c, in[12], S32, UL(3873151461)); /* 46 */
-  HH ( c, d, a, b, in[15], S33, UL( 530742520)); /* 47 */
-  HH ( b, c, d, a, in[ 2], S34, UL(3299628645)); /* 48 */
-
-  /* Round 4 */
-#define S41 6
-#define S42 10
-#define S43 15
-#define S44 21
-  II ( a, b, c, d, in[ 0], S41, UL(4096336452)); /* 49 */
-  II ( d, a, b, c, in[ 7], S42, UL(1126891415)); /* 50 */
-  II ( c, d, a, b, in[14], S43, UL(2878612391)); /* 51 */
-  II ( b, c, d, a, in[ 5], S44, UL(4237533241)); /* 52 */
-  II ( a, b, c, d, in[12], S41, UL(1700485571)); /* 53 */
-  II ( d, a, b, c, in[ 3], S42, UL(2399980690)); /* 54 */
-  II ( c, d, a, b, in[10], S43, UL(4293915773)); /* 55 */
-  II ( b, c, d, a, in[ 1], S44, UL(2240044497)); /* 56 */
-  II ( a, b, c, d, in[ 8], S41, UL(1873313359)); /* 57 */
-  II ( d, a, b, c, in[15], S42, UL(4264355552)); /* 58 */
-  II ( c, d, a, b, in[ 6], S43, UL(2734768916)); /* 59 */
-  II ( b, c, d, a, in[13], S44, UL(1309151649)); /* 60 */
-  II ( a, b, c, d, in[ 4], S41, UL(4149444226)); /* 61 */
-  II ( d, a, b, c, in[11], S42, UL(3174756917)); /* 62 */
-  II ( c, d, a, b, in[ 2], S43, UL( 718787259)); /* 63 */
-  II ( b, c, d, a, in[ 9], S44, UL(3951481745)); /* 64 */
-
-  buf[0] += a;
-  buf[1] += b;
-  buf[2] += c;
-  buf[3] += d;
-}
-
-#endif
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/md5.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/md5.h
deleted file mode 100644
index 0e81cdc34..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/md5.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- ***********************************************************************
- ** md5.h -- header file for implementation of MD5                    **
- ** RSA Data Security, Inc. MD5 Message-Digest Algorithm              **
- ** Created: 2/17/90 RLR                                              **
- ** Revised: 12/27/90 SRD,AJ,BSK,JT Reference C version               **
- ** Revised (for MD5): RLR 4/27/91                                    **
- **   -- G modified to have y&~z instead of y&z                       **
- **   -- FF, GG, HH modified to add in last register done             **
- **   -- Access pattern: round 2 works mod 5, round 3 works mod 3     **
- **   -- distinct additive constant for each step                     **
- **   -- round 4 added, working mod 7                                 **
- ***********************************************************************
- */
-
-/*
- ***********************************************************************
- ** Copyright (C) 1990, RSA Data Security, Inc. All rights reserved.  **
- **                                                                   **
- ** License to copy and use this software is granted provided that    **
- ** it is identified as the "RSA Data Security, Inc. MD5 Message-     **
- ** Digest Algorithm" in all material mentioning or referencing this  **
- ** software or this function.                                        **
- **                                                                   **
- ** License is also granted to make and use derivative works          **
- ** provided that such works are identified as "derived from the RSA  **
- ** Data Security, Inc. MD5 Message-Digest Algorithm" in all          **
- ** material mentioning or referencing the derived work.              **
- **                                                                   **
- ** RSA Data Security, Inc. makes no representations concerning       **
- ** either the merchantability of this software or the suitability    **
- ** of this software for any particular purpose.  It is provided "as  **
- ** is" without express or implied warranty of any kind.              **
- **                                                                   **
- ** These notices must be retained in any copies of any part of this  **
- ** documentation and/or software.                                    **
- ***********************************************************************
- */
-
-#ifndef MD5_H
-#define MD5_H
-
-/* Data structure for MD5 (Message-Digest) computation */
-typedef struct {
-  u32_t i[2];                   /* number of _bits_ handled mod 2^64 */
-  u32_t buf[4];                                    /* scratch buffer */
-  unsigned char in[64];                              /* input buffer */
-  unsigned char digest[16];     /* actual digest after MD5Final call */
-} MD5_CTX;
-
-void MD5Init (MD5_CTX *mdContext);
-void MD5Update (MD5_CTX *mdContext, unsigned char *inBuf, unsigned int inLen);
-void MD5Final (unsigned char hash[], MD5_CTX *mdContext);
-
-#endif /* MD5_H */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/pap.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/pap.c
deleted file mode 100644
index 23e438ff2..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/pap.c
+++ /dev/null
@@ -1,608 +0,0 @@
-/*****************************************************************************
-* pap.c - Network Password Authentication Protocol program file.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* portions Copyright (c) 1997 by Global Election Systems Inc.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY
-*
-* 03-01-01 Marc Boucher 
-*   Ported to lwIP.
-* 97-12-12 Guy Lancaster , Global Election Systems Inc.
-*	Original.
-*****************************************************************************/
-/*
- * upap.c - User/Password Authentication Protocol.
- *
- * Copyright (c) 1989 Carnegie Mellon University.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by Carnegie Mellon University.  The name of the
- * University may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- */
-
-#include "ppp.h"
-#include "auth.h"
-#include "pap.h"
-#include "pppdebug.h"
-
-
-#if PAP_SUPPORT > 0
-
-/***********************************/
-/*** LOCAL FUNCTION DECLARATIONS ***/
-/***********************************/
-/*
- * Protocol entry points.
- */
-static void upap_init (int);
-static void upap_lowerup (int);
-static void upap_lowerdown (int);
-static void upap_input (int, u_char *, int);
-static void upap_protrej (int);
-
-static void upap_timeout (void *);
-static void upap_reqtimeout (void *);
-static void upap_rauthreq (upap_state *, u_char *, int, int);
-static void upap_rauthack (upap_state *, u_char *, int, int);
-static void upap_rauthnak (upap_state *, u_char *, int, int);
-static void upap_sauthreq (upap_state *);
-static void upap_sresp (upap_state *, u_char, u_char, char *, int);
-
-
-
-
-/******************************/
-/*** PUBLIC DATA STRUCTURES ***/
-/******************************/
-struct protent pap_protent = {
-    PPP_PAP,
-    upap_init,
-    upap_input,
-    upap_protrej,
-    upap_lowerup,
-    upap_lowerdown,
-    NULL,
-    NULL,
-#if 0
-    upap_printpkt,
-    NULL,
-#endif
-    1,
-    "PAP",
-#if 0
-    NULL,
-    NULL,
-    NULL
-#endif
-};
-
-upap_state upap[NUM_PPP];		/* UPAP state; one for each unit */
-
-
-
-/***********************************/
-/*** PUBLIC FUNCTION DEFINITIONS ***/
-/***********************************/
-/*
- *  Set the default login name and password for the pap sessions
- */
-void upap_setloginpasswd(int unit, const char *luser, const char *lpassword)
-{
-	upap_state *u = &upap[unit];
-	
-	/* Save the username and password we're given */
-	u->us_user = luser;
-	u->us_userlen = strlen(luser);
-	u->us_passwd = lpassword;
-	u->us_passwdlen = strlen(lpassword);
-}
-
-
-/*
- * upap_authwithpeer - Authenticate us with our peer (start client).
- *
- * Set new state and send authenticate's.
- */
-void upap_authwithpeer(int unit, char *user, char *password)
-{
-	upap_state *u = &upap[unit];
-	
-	UPAPDEBUG((LOG_INFO, "upap_authwithpeer: %d user=%s password=%s s=%d\n",
-				unit, user, password, u->us_clientstate));
-	
-	upap_setloginpasswd(unit, user, password);
-
-	u->us_transmits = 0;
-	
-	/* Lower layer up yet? */
-	if (u->us_clientstate == UPAPCS_INITIAL ||
-			u->us_clientstate == UPAPCS_PENDING) {
-		u->us_clientstate = UPAPCS_PENDING;
-		return;
-	}
-	
-	upap_sauthreq(u);			/* Start protocol */
-}
-
-
-/*
- * upap_authpeer - Authenticate our peer (start server).
- *
- * Set new state.
- */
-void upap_authpeer(int unit)
-{
-	upap_state *u = &upap[unit];
-	
-	/* Lower layer up yet? */
-	if (u->us_serverstate == UPAPSS_INITIAL ||
-			u->us_serverstate == UPAPSS_PENDING) {
-		u->us_serverstate = UPAPSS_PENDING;
-		return;
-	}
-	
-	u->us_serverstate = UPAPSS_LISTEN;
-	if (u->us_reqtimeout > 0)
-		TIMEOUT(upap_reqtimeout, u, u->us_reqtimeout);
-}
-
-
-
-/**********************************/
-/*** LOCAL FUNCTION DEFINITIONS ***/
-/**********************************/
-/*
- * upap_init - Initialize a UPAP unit.
- */
-static void upap_init(int unit)
-{
-	upap_state *u = &upap[unit];
-
-	UPAPDEBUG((LOG_INFO, "upap_init: %d\n", unit));	
-	u->us_unit = unit;
-	u->us_user = NULL;
-	u->us_userlen = 0;
-	u->us_passwd = NULL;
-	u->us_passwdlen = 0;
-	u->us_clientstate = UPAPCS_INITIAL;
-	u->us_serverstate = UPAPSS_INITIAL;
-	u->us_id = 0;
-	u->us_timeouttime = UPAP_DEFTIMEOUT;
-	u->us_maxtransmits = 10;
-	u->us_reqtimeout = UPAP_DEFREQTIME;
-}
-
-/*
- * upap_timeout - Retransmission timer for sending auth-reqs expired.
- */
-static void upap_timeout(void *arg)
-{
-	upap_state *u = (upap_state *) arg;
-	
-	UPAPDEBUG((LOG_INFO, "upap_timeout: %d timeout %d expired s=%d\n", 
-				u->us_unit, u->us_timeouttime, u->us_clientstate));
-	
-	if (u->us_clientstate != UPAPCS_AUTHREQ)
-		return;
-	
-	if (u->us_transmits >= u->us_maxtransmits) {
-		/* give up in disgust */
-		UPAPDEBUG((LOG_ERR, "No response to PAP authenticate-requests\n"));
-		u->us_clientstate = UPAPCS_BADAUTH;
-		auth_withpeer_fail(u->us_unit, PPP_PAP);
-		return;
-	}
-	
-	upap_sauthreq(u);		/* Send Authenticate-Request */
-}
-
-
-/*
- * upap_reqtimeout - Give up waiting for the peer to send an auth-req.
- */
-static void upap_reqtimeout(void *arg)
-{
-	upap_state *u = (upap_state *) arg;
-	
-	if (u->us_serverstate != UPAPSS_LISTEN)
-		return;			/* huh?? */
-	
-	auth_peer_fail(u->us_unit, PPP_PAP);
-	u->us_serverstate = UPAPSS_BADAUTH;
-}
-
-
-/*
- * upap_lowerup - The lower layer is up.
- *
- * Start authenticating if pending.
- */
-static void upap_lowerup(int unit)
-{
-	upap_state *u = &upap[unit];
-	
-	UPAPDEBUG((LOG_INFO, "upap_lowerup: %d s=%d\n", unit, u->us_clientstate));
-	
-	if (u->us_clientstate == UPAPCS_INITIAL)
-		u->us_clientstate = UPAPCS_CLOSED;
-	else if (u->us_clientstate == UPAPCS_PENDING) {
-		upap_sauthreq(u);	/* send an auth-request */
-	}
-	
-	if (u->us_serverstate == UPAPSS_INITIAL)
-		u->us_serverstate = UPAPSS_CLOSED;
-	else if (u->us_serverstate == UPAPSS_PENDING) {
-		u->us_serverstate = UPAPSS_LISTEN;
-		if (u->us_reqtimeout > 0)
-			TIMEOUT(upap_reqtimeout, u, u->us_reqtimeout);
-	}
-}
-
-
-/*
- * upap_lowerdown - The lower layer is down.
- *
- * Cancel all timeouts.
- */
-static void upap_lowerdown(int unit)
-{
-	upap_state *u = &upap[unit];
-	
-	UPAPDEBUG((LOG_INFO, "upap_lowerdown: %d s=%d\n", unit, u->us_clientstate));
-	
-	if (u->us_clientstate == UPAPCS_AUTHREQ)	/* Timeout pending? */
-		UNTIMEOUT(upap_timeout, u);		/* Cancel timeout */
-	if (u->us_serverstate == UPAPSS_LISTEN && u->us_reqtimeout > 0)
-		UNTIMEOUT(upap_reqtimeout, u);
-	
-	u->us_clientstate = UPAPCS_INITIAL;
-	u->us_serverstate = UPAPSS_INITIAL;
-}
-
-
-/*
- * upap_protrej - Peer doesn't speak this protocol.
- *
- * This shouldn't happen.  In any case, pretend lower layer went down.
- */
-static void upap_protrej(int unit)
-{
-	upap_state *u = &upap[unit];
-	
-	if (u->us_clientstate == UPAPCS_AUTHREQ) {
-		UPAPDEBUG((LOG_ERR, "PAP authentication failed due to protocol-reject\n"));
-		auth_withpeer_fail(unit, PPP_PAP);
-	}
-	if (u->us_serverstate == UPAPSS_LISTEN) {
-		UPAPDEBUG((LOG_ERR, "PAP authentication of peer failed (protocol-reject)\n"));
-		auth_peer_fail(unit, PPP_PAP);
-	}
-	upap_lowerdown(unit);
-}
-
-
-/*
- * upap_input - Input UPAP packet.
- */
-static void upap_input(int unit, u_char *inpacket, int l)
-{
-	upap_state *u = &upap[unit];
-	u_char *inp;
-	u_char code, id;
-	int len;
-	
-	/*
-	 * Parse header (code, id and length).
-	 * If packet too short, drop it.
-	 */
-	inp = inpacket;
-	if (l < UPAP_HEADERLEN) {
-		UPAPDEBUG((LOG_INFO, "pap_input: rcvd short header.\n"));
-		return;
-	}
-	GETCHAR(code, inp);
-	GETCHAR(id, inp);
-	GETSHORT(len, inp);
-	if (len < UPAP_HEADERLEN) {
-		UPAPDEBUG((LOG_INFO, "pap_input: rcvd illegal length.\n"));
-		return;
-	}
-	if (len > l) {
-		UPAPDEBUG((LOG_INFO, "pap_input: rcvd short packet.\n"));
-		return;
-	}
-	len -= UPAP_HEADERLEN;
-	
-	/*
-	 * Action depends on code.
-	 */
-	switch (code) {
-	case UPAP_AUTHREQ:
-		upap_rauthreq(u, inp, id, len);
-		break;
-	
-	case UPAP_AUTHACK:
-		upap_rauthack(u, inp, id, len);
-		break;
-	
-	case UPAP_AUTHNAK:
-		upap_rauthnak(u, inp, id, len);
-		break;
-	
-	default:				/* XXX Need code reject */
-		break;
-	}
-}
-
-
-/*
- * upap_rauth - Receive Authenticate.
- */
-static void upap_rauthreq(
-	upap_state *u, 
-	u_char *inp, 
-	int id,
-	int len
-)
-{
-	u_char ruserlen, rpasswdlen;
-	char *ruser, *rpasswd;
-	int retcode;
-	char *msg;
-	int msglen;
-	
-	UPAPDEBUG((LOG_INFO, "pap_rauth: Rcvd id %d.\n", id));
-	
-	if (u->us_serverstate < UPAPSS_LISTEN)
-		return;
-	
-	/*
-	 * If we receive a duplicate authenticate-request, we are
-	 * supposed to return the same status as for the first request.
-	 */
-	if (u->us_serverstate == UPAPSS_OPEN) {
-		upap_sresp(u, UPAP_AUTHACK, id, "", 0);	/* return auth-ack */
-		return;
-	}
-	if (u->us_serverstate == UPAPSS_BADAUTH) {
-		upap_sresp(u, UPAP_AUTHNAK, id, "", 0);	/* return auth-nak */
-		return;
-	}
-	
-	/*
-	 * Parse user/passwd.
-	 */
-	if (len < sizeof (u_char)) {
-		UPAPDEBUG((LOG_INFO, "pap_rauth: rcvd short packet.\n"));
-		return;
-	}
-	GETCHAR(ruserlen, inp);
-	len -= sizeof (u_char) + ruserlen + sizeof (u_char);
-	if (len < 0) {
-		UPAPDEBUG((LOG_INFO, "pap_rauth: rcvd short packet.\n"));
-		return;
-	}
-	ruser = (char *) inp;
-	INCPTR(ruserlen, inp);
-	GETCHAR(rpasswdlen, inp);
-	if (len < rpasswdlen) {
-		UPAPDEBUG((LOG_INFO, "pap_rauth: rcvd short packet.\n"));
-		return;
-	}
-	rpasswd = (char *) inp;
-	
-	/*
-	 * Check the username and password given.
-	 */
-	retcode = check_passwd(u->us_unit, ruser, ruserlen, rpasswd,
-			   rpasswdlen, &msg, &msglen);
-	BZERO(rpasswd, rpasswdlen);
-	
-	upap_sresp(u, retcode, id, msg, msglen);
-	
-	if (retcode == UPAP_AUTHACK) {
-		u->us_serverstate = UPAPSS_OPEN;
-		auth_peer_success(u->us_unit, PPP_PAP, ruser, ruserlen);
-	} else {
-		u->us_serverstate = UPAPSS_BADAUTH;
-		auth_peer_fail(u->us_unit, PPP_PAP);
-	}
-	
-	if (u->us_reqtimeout > 0)
-		UNTIMEOUT(upap_reqtimeout, u);
-}
-
-
-/*
- * upap_rauthack - Receive Authenticate-Ack.
- */
-static void upap_rauthack(
-	upap_state *u,
-	u_char *inp,
-	int id,
-	int len
-)
-{
-	u_char msglen;
-	char *msg;
-	
-	UPAPDEBUG((LOG_INFO, "pap_rauthack: Rcvd id %d s=%d\n", id, u->us_clientstate));
-	
-	if (u->us_clientstate != UPAPCS_AUTHREQ) /* XXX */
-		return;
-	
-	/*
-	 * Parse message.
-	 */
-	if (len < sizeof (u_char)) {
-		UPAPDEBUG((LOG_INFO, "pap_rauthack: rcvd short packet.\n"));
-		return;
-	}
-	GETCHAR(msglen, inp);
-	len -= sizeof (u_char);
-	if (len < msglen) {
-		UPAPDEBUG((LOG_INFO, "pap_rauthack: rcvd short packet.\n"));
-		return;
-	}
-	msg = (char *) inp;
-	PRINTMSG(msg, msglen);
-	
-	u->us_clientstate = UPAPCS_OPEN;
-	
-	auth_withpeer_success(u->us_unit, PPP_PAP);
-}
-
-
-/*
- * upap_rauthnak - Receive Authenticate-Nakk.
- */
-static void upap_rauthnak(
-	upap_state *u,
-	u_char *inp,
-	int id,
-	int len
-)
-{
-	u_char msglen;
-	char *msg;
-	
-	UPAPDEBUG((LOG_INFO, "pap_rauthnak: Rcvd id %d s=%d\n", id, u->us_clientstate));
-	
-	if (u->us_clientstate != UPAPCS_AUTHREQ) /* XXX */
-		return;
-	
-	/*
-	 * Parse message.
-	 */
-	if (len < sizeof (u_char)) {
-		UPAPDEBUG((LOG_INFO, "pap_rauthnak: rcvd short packet.\n"));
-		return;
-	}
-	GETCHAR(msglen, inp);
-	len -= sizeof (u_char);
-	if (len < msglen) {
-		UPAPDEBUG((LOG_INFO, "pap_rauthnak: rcvd short packet.\n"));
-		return;
-	}
-	msg = (char *) inp;
-	PRINTMSG(msg, msglen);
-	
-	u->us_clientstate = UPAPCS_BADAUTH;
-	
-	UPAPDEBUG((LOG_ERR, "PAP authentication failed\n"));
-	auth_withpeer_fail(u->us_unit, PPP_PAP);
-}
-
-
-/*
- * upap_sauthreq - Send an Authenticate-Request.
- */
-static void upap_sauthreq(upap_state *u)
-{
-	u_char *outp;
-	int outlen;
-	
-	outlen = UPAP_HEADERLEN + 2 * sizeof (u_char) 
-			+ u->us_userlen + u->us_passwdlen;
-	outp = outpacket_buf[u->us_unit];
-	
-	MAKEHEADER(outp, PPP_PAP);
-	
-	PUTCHAR(UPAP_AUTHREQ, outp);
-	PUTCHAR(++u->us_id, outp);
-	PUTSHORT(outlen, outp);
-	PUTCHAR(u->us_userlen, outp);
-	BCOPY(u->us_user, outp, u->us_userlen);
-	INCPTR(u->us_userlen, outp);
-	PUTCHAR(u->us_passwdlen, outp);
-	BCOPY(u->us_passwd, outp, u->us_passwdlen);
-	
-	pppWrite(u->us_unit, outpacket_buf[u->us_unit], outlen + PPP_HDRLEN);
-	
-	UPAPDEBUG((LOG_INFO, "pap_sauth: Sent id %d\n", u->us_id));
-	
-	TIMEOUT(upap_timeout, u, u->us_timeouttime);
-	++u->us_transmits;
-	u->us_clientstate = UPAPCS_AUTHREQ;
-}
-
-
-/*
- * upap_sresp - Send a response (ack or nak).
- */
-static void upap_sresp(
-	upap_state *u,
-	u_char code, 
-	u_char id,
-	char *msg,
-	int msglen
-)
-{
-	u_char *outp;
-	int outlen;
-	
-	outlen = UPAP_HEADERLEN + sizeof (u_char) + msglen;
-	outp = outpacket_buf[u->us_unit];
-	MAKEHEADER(outp, PPP_PAP);
-	
-	PUTCHAR(code, outp);
-	PUTCHAR(id, outp);
-	PUTSHORT(outlen, outp);
-	PUTCHAR(msglen, outp);
-	BCOPY(msg, outp, msglen);
-	pppWrite(u->us_unit, outpacket_buf[u->us_unit], outlen + PPP_HDRLEN);
-	
-	UPAPDEBUG((LOG_INFO, "pap_sresp: Sent code %d, id %d s=%d\n", 
-				code, id, u->us_clientstate));
-}
-
-#if 0
-/*
- * upap_printpkt - print the contents of a PAP packet.
- */
-static int upap_printpkt(
-	u_char *p,
-	int plen,
-	void (*printer) (void *, char *, ...),
-	void *arg
-)
-{
-	(void)p;
-	(void)plen;
-	(void)printer;
-	(void)arg;
-	return 0;
-}
-#endif
-
-#endif /* PAP_SUPPORT */
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/pap.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/pap.h
deleted file mode 100644
index 215c8a4f2..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/pap.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/*****************************************************************************
-* pap.h -  PPP Password Authentication Protocol header file.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* portions Copyright (c) 1997 Global Election Systems Inc.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY
-*
-* 03-01-01 Marc Boucher 
-*   Ported to lwIP.
-* 97-12-04 Guy Lancaster , Global Election Systems Inc.
-*	Original derived from BSD codes.
-*****************************************************************************/
-/*
- * upap.h - User/Password Authentication Protocol definitions.
- *
- * Copyright (c) 1989 Carnegie Mellon University.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by Carnegie Mellon University.  The name of the
- * University may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- */
-
-
-#ifndef PAP_H
-#define PAP_H
-
-/*************************
-*** PUBLIC DEFINITIONS ***
-*************************/
-/*
- * Packet header = Code, id, length.
- */
-#define UPAP_HEADERLEN	(sizeof (u_char) + sizeof (u_char) + sizeof (u_short))
-
-
-/*
- * UPAP codes.
- */
-#define UPAP_AUTHREQ	1	/* Authenticate-Request */
-#define UPAP_AUTHACK	2	/* Authenticate-Ack */
-#define UPAP_AUTHNAK	3	/* Authenticate-Nak */
-
-/*
- * Client states.
- */
-#define UPAPCS_INITIAL	0	/* Connection down */
-#define UPAPCS_CLOSED	1	/* Connection up, haven't requested auth */
-#define UPAPCS_PENDING	2	/* Connection down, have requested auth */
-#define UPAPCS_AUTHREQ	3	/* We've sent an Authenticate-Request */
-#define UPAPCS_OPEN		4	/* We've received an Ack */
-#define UPAPCS_BADAUTH	5	/* We've received a Nak */
-
-/*
- * Server states.
- */
-#define UPAPSS_INITIAL	0	/* Connection down */
-#define UPAPSS_CLOSED	1	/* Connection up, haven't requested auth */
-#define UPAPSS_PENDING	2	/* Connection down, have requested auth */
-#define UPAPSS_LISTEN	3	/* Listening for an Authenticate */
-#define UPAPSS_OPEN		4	/* We've sent an Ack */
-#define UPAPSS_BADAUTH	5	/* We've sent a Nak */
-
-
-/************************
-*** PUBLIC DATA TYPES ***
-************************/
-
-/*
- * Each interface is described by upap structure.
- */
-typedef struct upap_state {
-    int us_unit;			/* Interface unit number */
-    const char *us_user;	/* User */
-    int us_userlen;			/* User length */
-    const char *us_passwd;	/* Password */
-    int us_passwdlen;		/* Password length */
-    int us_clientstate;		/* Client state */
-    int us_serverstate;		/* Server state */
-    u_char us_id;			/* Current id */
-    int us_timeouttime;		/* Timeout (seconds) for auth-req retrans. */
-    int us_transmits;		/* Number of auth-reqs sent */
-    int us_maxtransmits;	/* Maximum number of auth-reqs to send */
-    int us_reqtimeout;		/* Time to wait for auth-req from peer */
-} upap_state;
-
-
-/***********************
-*** PUBLIC FUNCTIONS ***
-***********************/
-
-extern upap_state upap[];
-
-void upap_setloginpasswd(int unit, const char *luser, const char *lpassword);
-void upap_authwithpeer (int, char *, char *);
-void upap_authpeer (int);
-
-extern struct protent pap_protent;
-
-#endif /* PAP_H */
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/ppp.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/ppp.c
deleted file mode 100644
index df402189e..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/ppp.c
+++ /dev/null
@@ -1,1623 +0,0 @@
-/*****************************************************************************
-* ppp.c - Network Point to Point Protocol program file.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* portions Copyright (c) 1997 by Global Election Systems Inc.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY
-*
-* 03-01-01 Marc Boucher 
-*   Ported to lwIP.
-* 97-11-05 Guy Lancaster , Global Election Systems Inc.
-*   Original.
-*****************************************************************************/
-
-/*
- * ppp_defs.h - PPP definitions.
- *
- * if_pppvar.h - private structures and declarations for PPP.
- *
- * Copyright (c) 1994 The Australian National University.
- * All rights reserved.
- *
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, provided that the above copyright
- * notice appears in all copies.  This software is provided without any
- * warranty, express or implied. The Australian National University
- * makes no representations about the suitability of this software for
- * any purpose.
- *
- * IN NO EVENT SHALL THE AUSTRALIAN NATIONAL UNIVERSITY BE LIABLE TO ANY
- * PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES
- * ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF
- * THE AUSTRALIAN NATIONAL UNIVERSITY HAVE BEEN ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * THE AUSTRALIAN NATIONAL UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
- * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
- * AND FITNESS FOR A PARTICULAR PURPOSE.  THE SOFTWARE PROVIDED HEREUNDER IS
- * ON AN "AS IS" BASIS, AND THE AUSTRALIAN NATIONAL UNIVERSITY HAS NO
- * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS,
- * OR MODIFICATIONS.
- */
-
-/*
- * if_ppp.h - Point-to-Point Protocol definitions.
- *
- * Copyright (c) 1989 Carnegie Mellon University.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by Carnegie Mellon University.  The name of the
- * University may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- */
- 
-#include 
- 
-#include "ppp.h"
-#if PPP_SUPPORT > 0
-#include "randm.h"
-#include "fsm.h"
-#if PAP_SUPPORT > 0
-#include "pap.h"
-#endif
-#if CHAP_SUPPORT > 0
-#include "chap.h"
-#endif
-#include "ipcp.h"
-#include "lcp.h"
-#include "magic.h"
-#include "auth.h"
-#if VJ_SUPPORT > 0
-#include "vj.h"
-#endif
-
-#include "pppdebug.h"
-
-/*************************/
-/*** LOCAL DEFINITIONS ***/
-/*************************/
-
-/*
- * The basic PPP frame.
- */
-#define PPP_ADDRESS(p)  (((u_char *)(p))[0])
-#define PPP_CONTROL(p)  (((u_char *)(p))[1])
-#define PPP_PROTOCOL(p) ((((u_char *)(p))[2] << 8) + ((u_char *)(p))[3])
-
-/* PPP packet parser states.  Current state indicates operation yet to be
- * completed. */
-typedef enum {
-    PDIDLE = 0,                 /* Idle state - waiting. */
-    PDSTART,                    /* Process start flag. */
-    PDADDRESS,                  /* Process address field. */
-    PDCONTROL,                  /* Process control field. */
-    PDPROTOCOL1,                /* Process protocol field 1. */
-    PDPROTOCOL2,                /* Process protocol field 2. */
-    PDDATA                      /* Process data byte. */
-} PPPDevStates;
-
-#define ESCAPE_P(accm, c) ((accm)[(c) >> 3] & pppACCMMask[c & 0x07])
-
-/************************/
-/*** LOCAL DATA TYPES ***/
-/************************/
-/*
- * PPP interface control block.
- */
-typedef struct PPPControl_s {
-    char openFlag;                      /* True when in use. */
-    char oldFrame;                      /* Old framing character for fd. */
-    sio_fd_t fd;                    /* File device ID of port. */
-    int  kill_link;                     /* Shut the link down. */
-    int  sig_hup;                       /* Carrier lost. */
-    int  if_up;                         /* True when the interface is up. */
-    int  errCode;                       /* Code indicating why interface is down. */
-    struct pbuf *inHead, *inTail;       /* The input packet. */
-    PPPDevStates inState;               /* The input process state. */
-    char inEscaped;                     /* Escape next character. */
-    u16_t inProtocol;                   /* The input protocol code. */
-    u16_t inFCS;                        /* Input Frame Check Sequence value. */
-    int  mtu;                           /* Peer's mru */
-    int  pcomp;                         /* Does peer accept protocol compression? */
-    int  accomp;                        /* Does peer accept addr/ctl compression? */
-    u_long lastXMit;                    /* Time of last transmission. */
-    ext_accm inACCM;                    /* Async-Ctl-Char-Map for input. */
-    ext_accm outACCM;                   /* Async-Ctl-Char-Map for output. */
-#if VJ_SUPPORT > 0
-    int  vjEnabled;                     /* Flag indicating VJ compression enabled. */
-    struct vjcompress vjComp;           /* Van Jabobsen compression header. */
-#endif
-
-    struct netif netif;
-
-    struct ppp_addrs addrs;
-
-    void (*linkStatusCB)(void *ctx, int errCode, void *arg);
-    void *linkStatusCtx;
-
-} PPPControl;
-
-
-/*
- * Ioctl definitions.
- */
-
-struct npioctl {
-    int     protocol;           /* PPP procotol, e.g. PPP_IP */
-    enum NPmode mode;
-};
-
-
-
-/***********************************/
-/*** LOCAL FUNCTION DECLARATIONS ***/
-/***********************************/
-static void pppMain(void *pd);
-static void pppDrop(PPPControl *pc);
-static void pppInProc(int pd, u_char *s, int l);
-
-
-/******************************/
-/*** PUBLIC DATA STRUCTURES ***/
-/******************************/
-u_long subnetMask;
-
-static PPPControl pppControl[NUM_PPP]; /* The PPP interface control blocks. */
-
-/*
- * PPP Data Link Layer "protocol" table.
- * One entry per supported protocol.
- * The last entry must be NULL.
- */
-struct protent *ppp_protocols[] = {
-    &lcp_protent,
-#if PAP_SUPPORT > 0
-    &pap_protent,
-#endif
-#if CHAP_SUPPORT > 0
-    &chap_protent,
-#endif
-#if CBCP_SUPPORT > 0
-    &cbcp_protent,
-#endif
-    &ipcp_protent,
-#if CCP_SUPPORT > 0
-    &ccp_protent,
-#endif
-    NULL
-};
-
-
-/*
- * Buffers for outgoing packets.  This must be accessed only from the appropriate
- * PPP task so that it doesn't need to be protected to avoid collisions.
- */
-u_char outpacket_buf[NUM_PPP][PPP_MRU+PPP_HDRLEN];  
-
-
-/*****************************/
-/*** LOCAL DATA STRUCTURES ***/
-/*****************************/
-
-/*
- * FCS lookup table as calculated by genfcstab.
- */
-static const u_short fcstab[256] = {
-    0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf,
-    0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7,
-    0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e,
-    0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876,
-    0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd,
-    0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5,
-    0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c,
-    0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974,
-    0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb,
-    0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3,
-    0x5285, 0x430c, 0x7197, 0x601e, 0x14a1, 0x0528, 0x37b3, 0x263a,
-    0xdecd, 0xcf44, 0xfddf, 0xec56, 0x98e9, 0x8960, 0xbbfb, 0xaa72,
-    0x6306, 0x728f, 0x4014, 0x519d, 0x2522, 0x34ab, 0x0630, 0x17b9,
-    0xef4e, 0xfec7, 0xcc5c, 0xddd5, 0xa96a, 0xb8e3, 0x8a78, 0x9bf1,
-    0x7387, 0x620e, 0x5095, 0x411c, 0x35a3, 0x242a, 0x16b1, 0x0738,
-    0xffcf, 0xee46, 0xdcdd, 0xcd54, 0xb9eb, 0xa862, 0x9af9, 0x8b70,
-    0x8408, 0x9581, 0xa71a, 0xb693, 0xc22c, 0xd3a5, 0xe13e, 0xf0b7,
-    0x0840, 0x19c9, 0x2b52, 0x3adb, 0x4e64, 0x5fed, 0x6d76, 0x7cff,
-    0x9489, 0x8500, 0xb79b, 0xa612, 0xd2ad, 0xc324, 0xf1bf, 0xe036,
-    0x18c1, 0x0948, 0x3bd3, 0x2a5a, 0x5ee5, 0x4f6c, 0x7df7, 0x6c7e,
-    0xa50a, 0xb483, 0x8618, 0x9791, 0xe32e, 0xf2a7, 0xc03c, 0xd1b5,
-    0x2942, 0x38cb, 0x0a50, 0x1bd9, 0x6f66, 0x7eef, 0x4c74, 0x5dfd,
-    0xb58b, 0xa402, 0x9699, 0x8710, 0xf3af, 0xe226, 0xd0bd, 0xc134,
-    0x39c3, 0x284a, 0x1ad1, 0x0b58, 0x7fe7, 0x6e6e, 0x5cf5, 0x4d7c,
-    0xc60c, 0xd785, 0xe51e, 0xf497, 0x8028, 0x91a1, 0xa33a, 0xb2b3,
-    0x4a44, 0x5bcd, 0x6956, 0x78df, 0x0c60, 0x1de9, 0x2f72, 0x3efb,
-    0xd68d, 0xc704, 0xf59f, 0xe416, 0x90a9, 0x8120, 0xb3bb, 0xa232,
-    0x5ac5, 0x4b4c, 0x79d7, 0x685e, 0x1ce1, 0x0d68, 0x3ff3, 0x2e7a,
-    0xe70e, 0xf687, 0xc41c, 0xd595, 0xa12a, 0xb0a3, 0x8238, 0x93b1,
-    0x6b46, 0x7acf, 0x4854, 0x59dd, 0x2d62, 0x3ceb, 0x0e70, 0x1ff9,
-    0xf78f, 0xe606, 0xd49d, 0xc514, 0xb1ab, 0xa022, 0x92b9, 0x8330,
-    0x7bc7, 0x6a4e, 0x58d5, 0x495c, 0x3de3, 0x2c6a, 0x1ef1, 0x0f78
-};
-
-/* PPP's Asynchronous-Control-Character-Map.  The mask array is used
- * to select the specific bit for a character. */
-static u_char pppACCMMask[] = {
-    0x01,
-    0x02,
-    0x04,
-    0x08,
-    0x10,
-    0x20,
-    0x40,
-    0x80
-};
-
-
-/***********************************/
-/*** PUBLIC FUNCTION DEFINITIONS ***/
-/***********************************/
-/* Initialize the PPP subsystem. */
-
-struct ppp_settings ppp_settings;
-
-void pppInit(void)
-{
-    struct protent *protp;
-    int i, j;
-    
-	memset(&ppp_settings, 0, sizeof(ppp_settings));
-	ppp_settings.usepeerdns = 1;
-	pppSetAuth(PPPAUTHTYPE_NONE, NULL, NULL);
-
-	magicInit();
-
-    for (i = 0; i < NUM_PPP; i++) {
-        pppControl[i].openFlag = 0;
-
-		subnetMask = htonl(0xffffff00);
-    
-        /*
-         * Initialize to the standard option set.
-         */
-        for (j = 0; (protp = ppp_protocols[j]) != NULL; ++j)
-            (*protp->init)(i);
-    }
-
-#if LINK_STATS
-    /* Clear the statistics. */
-    memset(&lwip_stats.link, 0, sizeof(lwip_stats.link));
-#endif
-}
-
-void pppSetAuth(enum pppAuthType authType, const char *user, const char *passwd)
-{
-    switch(authType) {
-	case PPPAUTHTYPE_NONE:
-	default:
-#ifdef LWIP_PPP_STRICT_PAP_REJECT
-	    ppp_settings.refuse_pap = 1;
-#else
-	    /* some providers request pap and accept an empty login/pw */
-	    ppp_settings.refuse_pap = 0;
-#endif
-	    ppp_settings.refuse_chap = 1;
-	    break;
-	case PPPAUTHTYPE_ANY:
-/* Warning: Using PPPAUTHTYPE_ANY might have security consequences.
- * RFC 1994 says:
- *
- * In practice, within or associated with each PPP server, there is a
- * database which associates "user" names with authentication
- * information ("secrets").  It is not anticipated that a particular
- * named user would be authenticated by multiple methods.  This would
- * make the user vulnerable to attacks which negotiate the least secure
- * method from among a set (such as PAP rather than CHAP).  If the same
- * secret was used, PAP would reveal the secret to be used later with
- * CHAP.
- *
- * Instead, for each user name there should be an indication of exactly
- * one method used to authenticate that user name.  If a user needs to
- * make use of different authentication methods under different
- * circumstances, then distinct user names SHOULD be employed, each of
- * which identifies exactly one authentication method.
- *
- */
-	    ppp_settings.refuse_pap = 0;
-	    ppp_settings.refuse_chap = 0;
-	    break;
-	case PPPAUTHTYPE_PAP:
-	    ppp_settings.refuse_pap = 0;
-	    ppp_settings.refuse_chap = 1;
-	    break;
-	case PPPAUTHTYPE_CHAP:
-	    ppp_settings.refuse_pap = 1;
-	    ppp_settings.refuse_chap = 0;
-	    break;
-    }
-
-    if(user) {
-	strncpy(ppp_settings.user, user, sizeof(ppp_settings.user)-1);
-	ppp_settings.user[sizeof(ppp_settings.user)-1] = '\0';
-    } else
-	ppp_settings.user[0] = '\0';
-
-    if(passwd) {
-	strncpy(ppp_settings.passwd, passwd, sizeof(ppp_settings.passwd)-1);
-	ppp_settings.passwd[sizeof(ppp_settings.passwd)-1] = '\0';
-    } else
-	ppp_settings.passwd[0] = '\0';
-}
-
-/* Open a new PPP connection using the given I/O device.
- * This initializes the PPP control block but does not
- * attempt to negotiate the LCP session.  If this port
- * connects to a modem, the modem connection must be
- * established before calling this.
- * Return a new PPP connection descriptor on success or
- * an error code (negative) on failure. */
-int pppOpen(sio_fd_t fd, void (*linkStatusCB)(void *ctx, int errCode, void *arg), void *linkStatusCtx)
-{
-    PPPControl *pc;
-    int pd;
-
-    /* Find a free PPP session descriptor. Critical region? */
-    for (pd = 0; pd < NUM_PPP && pppControl[pd].openFlag != 0; pd++);
-    if (pd >= NUM_PPP)
-        pd = PPPERR_OPEN;
-    else
-        pppControl[pd].openFlag = !0;
-
-    /* Launch a deamon thread. */
-    if (pd >= 0) {
-
-        pppControl[pd].openFlag = 1;
-
-        lcp_init(pd);
-        pc = &pppControl[pd];
-        pc->fd = fd;
-        pc->kill_link = 0;
-        pc->sig_hup = 0;
-        pc->if_up = 0;
-        pc->errCode = 0;
-        pc->inState = PDIDLE;
-        pc->inHead = NULL;
-        pc->inTail = NULL;
-        pc->inEscaped = 0;
-        pc->lastXMit = 0;
-
-#if VJ_SUPPORT > 0
-        pc->vjEnabled = 0;
-        vj_compress_init(&pc->vjComp);
-#endif
-
-        /* 
-         * Default the in and out accm so that escape and flag characters
-         * are always escaped. 
-         */
-        memset(pc->inACCM, 0, sizeof(ext_accm));
-        pc->inACCM[15] = 0x60;
-        memset(pc->outACCM, 0, sizeof(ext_accm));
-        pc->outACCM[15] = 0x60;
-
-	pc->linkStatusCB = linkStatusCB;
-	pc->linkStatusCtx = linkStatusCtx;
-
-	sys_thread_new(pppMain, (void*)pd, PPP_THREAD_PRIO);
-	if(!linkStatusCB) {
-		while(pd >= 0 && !pc->if_up) {
-			sys_msleep(500);
-			if (lcp_phase[pd] == PHASE_DEAD) {
-				pppClose(pd);
-				if (pc->errCode)
-					pd = pc->errCode;
-				else
-					pd = PPPERR_CONNECT;
-			}
-		}
-	}
-    }
-    return pd;
-}
-
-/* Close a PPP connection and release the descriptor. 
- * Any outstanding packets in the queues are dropped.
- * Return 0 on success, an error code on failure. */
-int pppClose(int pd)
-{
-    PPPControl *pc = &pppControl[pd];
-    int st = 0;
-
-    /* Disconnect */
-    pc->kill_link = !0;
-    pppMainWakeup(pd);
-    
-    if(!pc->linkStatusCB) {
-	    while(st >= 0 && lcp_phase[pd] != PHASE_DEAD) {
-		    sys_msleep(500);
-		    break;
-	    }
-    }
-    return st;
-}
-
-/* This function is called when carrier is lost on the PPP channel. */
-void pppSigHUP(int pd)
-{
-    PPPControl *pc = &pppControl[pd];
-
-    pc->sig_hup = 1;
-    pppMainWakeup(pd);
-}
-
-static void nPut(PPPControl *pc, struct pbuf *nb)
-{
-	struct pbuf *b;
-	int c;
-
-	for(b = nb; b != NULL; b = b->next) {
-	    if((c = sio_write(pc->fd, b->payload, b->len)) != b->len) {
-		PPPDEBUG((LOG_WARNING,
-			    "PPP nPut: incomplete sio_write(%d,, %u) = %d\n", pc->fd, b->len, c));
-#if LINK_STATS
-		lwip_stats.link.err++;
-#endif /* LINK_STATS */
-		pc->lastXMit = 0; /* prepend PPP_FLAG to next packet */
-		break;
-	    }
-	}
-	pbuf_free(nb);
-
-#if LINK_STATS
-	lwip_stats.link.xmit++;
-#endif /* LINK_STATS */
-}
-
-/* 
- * pppAppend - append given character to end of given pbuf.  If outACCM
- * is not NULL and the character needs to be escaped, do so.
- * If pbuf is full, append another.
- * Return the current pbuf.
- */
-static struct pbuf *pppAppend(u_char c, struct pbuf *nb, ext_accm *outACCM)
-{
-    struct pbuf *tb = nb;
-    
-    /* Make sure there is room for the character and an escape code.
-     * Sure we don't quite fill the buffer if the character doesn't
-     * get escaped but is one character worth complicating this? */
-    /* Note: We assume no packet header. */
-    if (nb && (PBUF_POOL_BUFSIZE - nb->len) < 2) {
-	tb = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL);
-	if (tb) {
-	    nb->next = tb;
-        }
-#if LINK_STATS
-	else {
-	    lwip_stats.link.memerr++;
-	}
-#endif /* LINK_STATS */
-	nb = tb;
-    }
-    if (nb) {
-	if (outACCM && ESCAPE_P(*outACCM, c)) {
-            *((u_char*)nb->payload + nb->len++) = PPP_ESCAPE;
-            *((u_char*)nb->payload + nb->len++) = c ^ PPP_TRANS;
-        }
-        else
-            *((u_char*)nb->payload + nb->len++) = c;
-    }
-        
-    return tb;
-}
-
-/* Send a packet on the given connection. */
-static err_t pppifOutput(struct netif *netif, struct pbuf *pb, struct ip_addr *ipaddr)
-{
-    int pd = (int)netif->state;
-    u_short protocol = PPP_IP;
-    PPPControl *pc = &pppControl[pd];
-    u_int fcsOut = PPP_INITFCS;
-    struct pbuf *headMB = NULL, *tailMB = NULL, *p;
-    u_char c;
-
-    (void)ipaddr;
-
-    /* Validate parameters. */
-    /* We let any protocol value go through - it can't hurt us
-     * and the peer will just drop it if it's not accepting it. */
-	if (pd < 0 || pd >= NUM_PPP || !pc->openFlag || !pb) {
-        PPPDEBUG((LOG_WARNING, "pppifOutput[%d]: bad parms prot=%d pb=%p\n",
-                    pd, protocol, pb));
-#if LINK_STATS
-		lwip_stats.link.opterr++;
-		lwip_stats.link.drop++;
-#endif
-		return ERR_ARG;
-	}
-
-    /* Check that the link is up. */
-	if (lcp_phase[pd] == PHASE_DEAD) {
-        PPPDEBUG((LOG_ERR, "pppifOutput[%d]: link not up\n", pd));
-#if LINK_STATS
-		lwip_stats.link.rterr++;
-		lwip_stats.link.drop++;
-#endif
-		return ERR_RTE;
-	}
-
-    /* Grab an output buffer. */
-	headMB = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL);
-    if (headMB == NULL) {
-        PPPDEBUG((LOG_WARNING, "pppifOutput[%d]: first alloc fail\n", pd));
-#if LINK_STATS
-		lwip_stats.link.memerr++;
-		lwip_stats.link.drop++;
-#endif /* LINK_STATS */
-        return ERR_MEM;
-    }
-        
-#if VJ_SUPPORT > 0
-    /* 
-     * Attempt Van Jacobson header compression if VJ is configured and
-     * this is an IP packet. 
-     */
-    if (protocol == PPP_IP && pc->vjEnabled) {
-        switch (vj_compress_tcp(&pc->vjComp, pb)) {
-        case TYPE_IP:
-            /* No change...
-            protocol = PPP_IP_PROTOCOL;
-             */
-            break;
-        case TYPE_COMPRESSED_TCP:
-            protocol = PPP_VJC_COMP;
-            break;
-        case TYPE_UNCOMPRESSED_TCP:
-            protocol = PPP_VJC_UNCOMP;
-            break;
-        default:
-            PPPDEBUG((LOG_WARNING, "pppifOutput[%d]: bad IP packet\n", pd));
-#if LINK_STATS
-			lwip_stats.link.proterr++;
-			lwip_stats.link.drop++;
-#endif
-        	pbuf_free(headMB);
-            return ERR_VAL;
-        }
-    }
-#endif
-        
-    tailMB = headMB;
-        
-    /* Build the PPP header. */
-    if ((sys_jiffies() - pc->lastXMit) >= PPP_MAXIDLEFLAG)
-        tailMB = pppAppend(PPP_FLAG, tailMB, NULL);
-    pc->lastXMit = sys_jiffies();
-    if (!pc->accomp) {
-        fcsOut = PPP_FCS(fcsOut, PPP_ALLSTATIONS);
-        tailMB = pppAppend(PPP_ALLSTATIONS, tailMB, &pc->outACCM);
-        fcsOut = PPP_FCS(fcsOut, PPP_UI);
-        tailMB = pppAppend(PPP_UI, tailMB, &pc->outACCM);
-    }
-    if (!pc->pcomp || protocol > 0xFF) {
-        c = (protocol >> 8) & 0xFF;
-        fcsOut = PPP_FCS(fcsOut, c);
-        tailMB = pppAppend(c, tailMB, &pc->outACCM);
-    }
-    c = protocol & 0xFF;
-    fcsOut = PPP_FCS(fcsOut, c);
-    tailMB = pppAppend(c, tailMB, &pc->outACCM);
-    
-    /* Load packet. */
-	for(p = pb; p; p = p->next) {
-    	int n;
-    	u_char *sPtr;
-
-        sPtr = (u_char*)p->payload;
-        n = p->len;
-        while (n-- > 0) {
-            c = *sPtr++;
-            
-            /* Update FCS before checking for special characters. */
-            fcsOut = PPP_FCS(fcsOut, c);
-            
-            /* Copy to output buffer escaping special characters. */
-            tailMB = pppAppend(c, tailMB, &pc->outACCM);
-        }
-    }
-
-    /* Add FCS and trailing flag. */
-    c = ~fcsOut & 0xFF;
-    tailMB = pppAppend(c, tailMB, &pc->outACCM);
-    c = (~fcsOut >> 8) & 0xFF;
-    tailMB = pppAppend(c, tailMB, &pc->outACCM);
-    tailMB = pppAppend(PPP_FLAG, tailMB, NULL);
-        
-    /* If we failed to complete the packet, throw it away. */
-    if (!tailMB) {
-        PPPDEBUG((LOG_WARNING,
-                    "pppifOutput[%d]: Alloc err - dropping proto=%d\n", 
-                    pd, protocol));
-        pbuf_free(headMB);
-#if LINK_STATS
-		lwip_stats.link.memerr++;
-		lwip_stats.link.drop++;
-#endif
-        return ERR_MEM;
-    }
-
-	/* Send it. */
-    PPPDEBUG((LOG_INFO, "pppifOutput[%d]: proto=0x%04X\n", pd, protocol));
-
-    nPut(pc, headMB);
-
-    return ERR_OK;
-}
-
-/* Get and set parameters for the given connection.
- * Return 0 on success, an error code on failure. */
-int  pppIOCtl(int pd, int cmd, void *arg)
-{
-    PPPControl *pc = &pppControl[pd];
-    int st = 0;
-
-    if (pd < 0 || pd >= NUM_PPP)
-        st = PPPERR_PARAM;
-    else {
-        switch(cmd) {
-        case PPPCTLG_UPSTATUS:      /* Get the PPP up status. */
-            if (arg) 
-                *(int *)arg = (int)(pc->if_up);
-            else
-                st = PPPERR_PARAM;
-            break;
-        case PPPCTLS_ERRCODE:       /* Set the PPP error code. */
-            if (arg) 
-                pc->errCode = *(int *)arg;
-            else
-                st = PPPERR_PARAM;
-            break;
-        case PPPCTLG_ERRCODE:       /* Get the PPP error code. */
-            if (arg) 
-                *(int *)arg = (int)(pc->errCode);
-            else
-                st = PPPERR_PARAM;
-            break;
-        case PPPCTLG_FD:
-            if (arg) 
-                *(sio_fd_t *)arg = pc->fd;
-            else
-                st = PPPERR_PARAM;
-            break;
-        default:
-            st = PPPERR_PARAM;
-            break;
-        }
-    }
-    
-    return st;
-}
-
-/*
- * Return the Maximum Transmission Unit for the given PPP connection.
- */
-u_int pppMTU(int pd)
-{
-    PPPControl *pc = &pppControl[pd];
-    u_int st;
-    
-    /* Validate parameters. */
-    if (pd < 0 || pd >= NUM_PPP || !pc->openFlag)
-        st = 0;
-    else
-        st = pc->mtu;
-        
-    return st;
-}
-
-/*
- * Write n characters to a ppp link.
- *  RETURN: >= 0 Number of characters written
- *           -1 Failed to write to device
- */
-int pppWrite(int pd, const u_char *s, int n)
-{
-    PPPControl *pc = &pppControl[pd];
-    u_char c;
-    u_int fcsOut = PPP_INITFCS;
-    struct pbuf *headMB = NULL, *tailMB;
-	headMB = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL);
-    if (headMB == NULL) {
-#if LINK_STATS
-		lwip_stats.link.memerr++;
-		lwip_stats.link.proterr++;
-#endif /* LINK_STATS */
-		return PPPERR_ALLOC;
-    }
-
-    tailMB = headMB;
-        
-    /* If the link has been idle, we'll send a fresh flag character to
-     * flush any noise. */
-    if ((sys_jiffies() - pc->lastXMit) >= PPP_MAXIDLEFLAG)
-        tailMB = pppAppend(PPP_FLAG, tailMB, NULL);
-    pc->lastXMit = sys_jiffies();
-     
-    /* Load output buffer. */
-    while (n-- > 0) {
-        c = *s++;
-        
-        /* Update FCS before checking for special characters. */
-        fcsOut = PPP_FCS(fcsOut, c);
-        
-        /* Copy to output buffer escaping special characters. */
-        tailMB = pppAppend(c, tailMB, &pc->outACCM);
-    }
-    
-    /* Add FCS and trailing flag. */
-    c = ~fcsOut & 0xFF;
-    tailMB = pppAppend(c, tailMB, &pc->outACCM);
-    c = (~fcsOut >> 8) & 0xFF;
-    tailMB = pppAppend(c, tailMB, &pc->outACCM);
-    tailMB = pppAppend(PPP_FLAG, tailMB, NULL);
-        
-    /* If we failed to complete the packet, throw it away.
-     * Otherwise send it. */
-    if (!tailMB) {
-		PPPDEBUG((LOG_WARNING,
-                "pppWrite[%d]: Alloc err - dropping pbuf len=%d\n", pd, headMB->len));
-/*                "pppWrite[%d]: Alloc err - dropping %d:%.*H", pd, headMB->len, LWIP_MIN(headMB->len * 2, 40), headMB->payload)); */
-		pbuf_free(headMB);
-#if LINK_STATS
-		lwip_stats.link.memerr++;
-		lwip_stats.link.proterr++;
-#endif /* LINK_STATS */
-		return PPPERR_ALLOC;
-	}
-
-    PPPDEBUG((LOG_INFO, "pppWrite[%d]: len=%d\n", pd, headMB->len));
-/*     "pppWrite[%d]: %d:%.*H", pd, headMB->len, LWIP_MIN(headMB->len * 2, 40), headMB->payload)); */
-    nPut(pc, headMB);
-
-    return PPPERR_NONE;
-}
-
-/*
- * ppp_send_config - configure the transmit characteristics of
- * the ppp interface.
- */
-void ppp_send_config(
-    int unit, 
-    int mtu,
-    u32_t asyncmap,
-    int pcomp, 
-    int accomp
-)
-{
-    PPPControl *pc = &pppControl[unit];
-    int i;
-    
-    pc->mtu = mtu;
-    pc->pcomp = pcomp;
-    pc->accomp = accomp;
-    
-    /* Load the ACCM bits for the 32 control codes. */
-    for (i = 0; i < 32/8; i++)
-        pc->outACCM[i] = (u_char)((asyncmap >> (8 * i)) & 0xFF);
-    PPPDEBUG((LOG_INFO, "ppp_send_config[%d]: outACCM=%X %X %X %X\n",
-                unit,
-                pc->outACCM[0], pc->outACCM[1], pc->outACCM[2], pc->outACCM[3]));
-}
-
-
-/*
- * ppp_set_xaccm - set the extended transmit ACCM for the interface.
- */
-void ppp_set_xaccm(int unit, ext_accm *accm)
-{
-    memcpy(pppControl[unit].outACCM, accm, sizeof(ext_accm));
-    PPPDEBUG((LOG_INFO, "ppp_set_xaccm[%d]: outACCM=%X %X %X %X\n",
-                unit,
-                pppControl[unit].outACCM[0],
-                pppControl[unit].outACCM[1],
-                pppControl[unit].outACCM[2],
-                pppControl[unit].outACCM[3]));
-}
-
-
-/*
- * ppp_recv_config - configure the receive-side characteristics of
- * the ppp interface.
- */
-void ppp_recv_config(
-    int unit, 
-    int mru,
-    u32_t asyncmap,
-    int pcomp, 
-    int accomp
-)
-{
-    PPPControl *pc = &pppControl[unit];
-    int i;
-    
-	(void)accomp;
-	(void)pcomp;
-	(void)mru;
-
-    /* Load the ACCM bits for the 32 control codes. */
-    for (i = 0; i < 32 / 8; i++)
-        pc->inACCM[i] = (u_char)(asyncmap >> (i * 8));
-    PPPDEBUG((LOG_INFO, "ppp_recv_config[%d]: inACCM=%X %X %X %X\n",
-                unit,
-                pc->inACCM[0], pc->inACCM[1], pc->inACCM[2], pc->inACCM[3]));
-}
-
-#if 0
-/*
- * ccp_test - ask kernel whether a given compression method
- * is acceptable for use.  Returns 1 if the method and parameters
- * are OK, 0 if the method is known but the parameters are not OK
- * (e.g. code size should be reduced), or -1 if the method is unknown.
- */
-int ccp_test(
-    int unit, 
-    int opt_len, 
-    int for_transmit,
-    u_char *opt_ptr
-)
-{
-    return 0;   /* XXX Currently no compression. */
-}
-
-/*
- * ccp_flags_set - inform kernel about the current state of CCP.
- */
-void ccp_flags_set(int unit, int isopen, int isup)
-{
-    /* XXX */
-}
-
-/*
- * ccp_fatal_error - returns 1 if decompression was disabled as a
- * result of an error detected after decompression of a packet,
- * 0 otherwise.  This is necessary because of patent nonsense.
- */
-int ccp_fatal_error(int unit)
-{
-    /* XXX */
-    return 0;
-}
-#endif
-
-/*
- * get_idle_time - return how long the link has been idle.
- */
-int get_idle_time(int u, struct ppp_idle *ip)
-{   
-    /* XXX */
-	(void)u;
-	(void)ip;
-
-    return 0;
-}
-
-
-/*
- * Return user specified netmask, modified by any mask we might determine
- * for address `addr' (in network byte order).
- * Here we scan through the system's list of interfaces, looking for
- * any non-point-to-point interfaces which might appear to be on the same
- * network as `addr'.  If we find any, we OR in their netmask to the
- * user-specified netmask.
- */
-u32_t GetMask(u32_t addr)
-{
-    u32_t mask, nmask;
-    
-    htonl(addr);
-    if (IN_CLASSA(addr))    /* determine network mask for address class */
-        nmask = IN_CLASSA_NET;
-    else if (IN_CLASSB(addr))
-        nmask = IN_CLASSB_NET;
-    else
-        nmask = IN_CLASSC_NET;
-    /* class D nets are disallowed by bad_ip_adrs */
-    mask = subnetMask | htonl(nmask);
-    
-    /* XXX
-     * Scan through the system's network interfaces.
-     * Get each netmask and OR them into our mask.
-     */
-    
-    return mask;
-}
-
-/*
- * sifvjcomp - config tcp header compression
- */
-int sifvjcomp(
-    int pd, 
-    int vjcomp, 
-    int cidcomp, 
-    int maxcid
-)
-{
-#if VJ_SUPPORT > 0
-    PPPControl *pc = &pppControl[pd];
-    
-    pc->vjEnabled = vjcomp;
-    pc->vjComp.compressSlot = cidcomp;
-    pc->vjComp.maxSlotIndex = maxcid;
-    PPPDEBUG((LOG_INFO, "sifvjcomp: VJ compress enable=%d slot=%d max slot=%d\n",
-                vjcomp, cidcomp, maxcid));
-#endif
-
-    return 0;
-}
-
-/*
- * pppifNetifInit - netif init callback
- */
-static err_t pppifNetifInit(struct netif *netif)
-{
-	netif->name[0] = 'p';
-	netif->name[1] = 'p';
-	netif->output = pppifOutput;
-	netif->mtu = pppMTU((int)netif->state);
-	return ERR_OK;
-}
-
-
-/*
- * sifup - Config the interface up and enable IP packets to pass.
- */
-int sifup(int pd)
-{
-    PPPControl *pc = &pppControl[pd];
-    int st = 1;
-    
-    if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
-        st = 0;
-        PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd));
-    } else {
-		netif_remove(&pc->netif);
-		if (netif_add(&pc->netif, &pc->addrs.our_ipaddr, &pc->addrs.netmask, &pc->addrs.his_ipaddr, (void *)pd, pppifNetifInit, ip_input)) {
-        		pc->if_up = 1;
-        		pc->errCode = PPPERR_NONE;
-
-			PPPDEBUG((LOG_DEBUG, "sifup: unit %d: linkStatusCB=%lx errCode=%d\n", pd, pc->linkStatusCB, pc->errCode));
-			if(pc->linkStatusCB)
-				pc->linkStatusCB(pc->linkStatusCtx, pc->errCode, &pc->addrs);
-		} else {
-        	st = 0;
-        	PPPDEBUG((LOG_ERR, "sifup[%d]: netif_add failed\n", pd));
-		}
-    }
-
-    return st;
-}
-
-/*
- * sifnpmode - Set the mode for handling packets for a given NP.
- */
-int sifnpmode(int u, int proto, enum NPmode mode)
-{
-	(void)u;
-	(void)proto;
-	(void)mode;
-    return 0;
-}
-
-/*
- * sifdown - Config the interface down and disable IP.
- */
-int sifdown(int pd)
-{
-    PPPControl *pc = &pppControl[pd];
-    int st = 1;
-    
-    if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
-        st = 0;
-        PPPDEBUG((LOG_WARNING, "sifdown[%d]: bad parms\n", pd));
-    } else {
-        pc->if_up = 0;
-	netif_remove(&pc->netif);
-	PPPDEBUG((LOG_DEBUG, "sifdown: unit %d: linkStatusCB=%lx errCode=%d\n", pd, pc->linkStatusCB, pc->errCode));
-	if(pc->linkStatusCB)
-		pc->linkStatusCB(pc->linkStatusCtx, PPPERR_CONNECT, NULL);
-	}
-    return st;
-}
-
-/*
- * sifaddr - Config the interface IP addresses and netmask.
- */
-int sifaddr(
-    int pd,             /* Interface unit ??? */
-    u32_t o,        /* Our IP address ??? */
-    u32_t h,        /* His IP address ??? */
-    u32_t m,        /* IP subnet mask ??? */
-    u32_t ns1,      /* Primary DNS */
-    u32_t ns2       /* Secondary DNS */
-)
-{
-    PPPControl *pc = &pppControl[pd];
-    int st = 1;
-    
-    if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
-        st = 0;
-        PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd));
-    } else {
-		memcpy(&pc->addrs.our_ipaddr, &o, sizeof(o));
-		memcpy(&pc->addrs.his_ipaddr, &h, sizeof(h));
-		memcpy(&pc->addrs.netmask, &m, sizeof(m));
-		memcpy(&pc->addrs.dns1, &ns1, sizeof(ns1));
-		memcpy(&pc->addrs.dns2, &ns2, sizeof(ns2));
-    }
-    return st;
-}
-
-/*
- * cifaddr - Clear the interface IP addresses, and delete routes
- * through the interface if possible.
- */
-int cifaddr(
-    int pd,         /* Interface unit ??? */
-    u32_t o,    /* Our IP address ??? */
-    u32_t h     /* IP broadcast address ??? */
-)
-{
-    PPPControl *pc = &pppControl[pd];
-    int st = 1;
-    
-	(void)o;
-	(void)h;
-    if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
-        st = 0;
-        PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd));
-    } else {
-		IP4_ADDR(&pc->addrs.our_ipaddr, 0,0,0,0);
-		IP4_ADDR(&pc->addrs.his_ipaddr, 0,0,0,0);
-		IP4_ADDR(&pc->addrs.netmask, 255,255,255,0);
-		IP4_ADDR(&pc->addrs.dns1, 0,0,0,0);
-		IP4_ADDR(&pc->addrs.dns2, 0,0,0,0);
-    }
-    return st;
-}
-
-/*
- * sifdefaultroute - assign a default route through the address given.
- */
-int sifdefaultroute(int pd, u32_t l, u32_t g)
-{
-    PPPControl *pc = &pppControl[pd];
-    int st = 1;
-    
-	(void)l;
-	(void)g;
-    if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
-        st = 0;
-        PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd));
-    } else {
-		netif_set_default(&pc->netif);
-    }
-
-    /* TODO: check how PPP handled the netMask, previously not set by ipSetDefault */
-
-    return st;
-}
-
-/*
- * cifdefaultroute - delete a default route through the address given.
- */
-int cifdefaultroute(int pd, u32_t l, u32_t g)
-{
-    PPPControl *pc = &pppControl[pd];
-    int st = 1;
-    
-	(void)l;
-	(void)g;
-    if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
-        st = 0;
-        PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd));
-    } else {
-		netif_set_default(NULL);
-    }
-
-    return st;
-}
-
-void
-pppMainWakeup(int pd)
-{
-	PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d\n", pd));
-	sio_read_abort(pppControl[pd].fd);
-}
-
-/* these callbacks are necessary because lcp_* functions
-   must be called in the same context as pppInput(),
-   namely the tcpip_thread(), essentially because
-   they manipulate timeouts which are thread-private
-*/
-
-static void
-pppStartCB(void *arg)
-{
-    int pd = (int)arg;
-
-	PPPDEBUG((LOG_DEBUG, "pppStartCB: unit %d\n", pd));
-    lcp_lowerup(pd);
-    lcp_open(pd);      /* Start protocol */
-}
-
-static void
-pppStopCB(void *arg)
-{
-    int pd = (int)arg;
-
-	PPPDEBUG((LOG_DEBUG, "pppStopCB: unit %d\n", pd));
-    lcp_close(pd, "User request");
-}
-
-static void
-pppHupCB(void *arg)
-{
-    int pd = (int)arg;
-
-	PPPDEBUG((LOG_DEBUG, "pppHupCB: unit %d\n", pd));
-    lcp_lowerdown(pd);
-    link_terminated(pd);
-}
-/**********************************/
-/*** LOCAL FUNCTION DEFINITIONS ***/
-/**********************************/
-/* The main PPP process function.  This implements the state machine according
- * to section 4 of RFC 1661: The Point-To-Point Protocol. */
-static void pppMain(void *arg)
-{
-    int pd = (int)arg;
-    struct pbuf *p;
-    PPPControl* pc;
-
-    pc = &pppControl[pd];
-
-    p = pbuf_alloc(PBUF_RAW, PPP_MRU+PPP_HDRLEN, PBUF_RAM);
-    if(!p) {
-		LWIP_ASSERT("p != NULL", p);
-		pc->errCode = PPPERR_ALLOC;
-		goto out;
-    }
-
-    /*
-     * Start the connection and handle incoming events (packet or timeout).
-     */
-	PPPDEBUG((LOG_INFO, "pppMain: unit %d: Connecting\n", pd));
-    tcpip_callback(pppStartCB, arg);
-    while (lcp_phase[pd] != PHASE_DEAD) {
-        if (pc->kill_link) {
-	    	PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d kill_link -> pppStopCB\n", pd));
-		pc->errCode = PPPERR_USER;
-		/* This will leave us at PHASE_DEAD. */
-    		tcpip_callback(pppStopCB, arg);
-		pc->kill_link = 0;
-        }
-        else if (pc->sig_hup) {
-	    	PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d sig_hup -> pppHupCB\n", pd));
-		pc->sig_hup = 0;
-    		tcpip_callback(pppHupCB, arg);
-        } else {
-		int c = sio_read(pc->fd, p->payload, p->len);
-		if(c > 0) {
-			pppInProc(pd, p->payload, c);
-		} else {
-		    PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d sio_read len=%d returned %d\n", pd, p->len, c));
-		    sys_msleep(1); /* give other tasks a chance to run */
-		}
-        }
-    }
-	PPPDEBUG((LOG_INFO, "pppMain: unit %d: PHASE_DEAD\n", pd));
-    pbuf_free(p);
-
-out:
-	PPPDEBUG((LOG_DEBUG, "pppMain: unit %d: linkStatusCB=%lx errCode=%d\n", pd, pc->linkStatusCB, pc->errCode));
-    if(pc->linkStatusCB)
-	    pc->linkStatusCB(pc->linkStatusCtx, pc->errCode ? pc->errCode : PPPERR_PROTOCOL, NULL);
-
-    pc->openFlag = 0;
-}
-
-static struct pbuf *pppSingleBuf(struct pbuf *p)
-{
-	struct pbuf *q, *b;
-	u_char *pl;
-
-	if(p->tot_len == p->len)
-		return p;
-
-	q = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM);
-	if(!q) {
-		PPPDEBUG((LOG_ERR,
-                        "pppSingleBuf: unable to alloc new buf (%d)\n", p->tot_len));
-		return p; /* live dangerously */
-	}
-
-	for(b = p, pl = q->payload; b != NULL; b = b->next) {
-		memcpy(pl, b->payload, b->len);
-		pl += b->len;
-	}
-
-	pbuf_free(p);
-
-	return q;
-}
-
-struct pppInputHeader {
-	int unit;
-	u16_t proto;
-};
-
-/*
- * Pass the processed input packet to the appropriate handler.
- * This function and all handlers run in the context of the tcpip_thread
- */
-static void pppInput(void *arg)
-{
-	struct pbuf *nb = (struct pbuf *)arg;
-    u16_t protocol;
-    int pd;
-
-	pd = ((struct pppInputHeader *)nb->payload)->unit;
-	protocol = ((struct pppInputHeader *)nb->payload)->proto;
-
-    pbuf_header(nb, -(int)sizeof(struct pppInputHeader));
-
-#if LINK_STATS
-    lwip_stats.link.recv++;
-#endif /* LINK_STATS */
-
-    /*
-     * Toss all non-LCP packets unless LCP is OPEN.
-     * Until we get past the authentication phase, toss all packets
-     * except LCP, LQR and authentication packets.
-     */
-    if((lcp_phase[pd] <= PHASE_AUTHENTICATE) && (protocol != PPP_LCP)) {
-	    if(!((protocol == PPP_LQR) || (protocol == PPP_PAP) || (protocol == PPP_CHAP)) ||
-			(lcp_phase[pd] != PHASE_AUTHENTICATE)) {
-		PPPDEBUG((LOG_INFO, "pppInput: discarding proto 0x%04X in phase %d\n", protocol, lcp_phase[pd]));
-		goto drop;
-	    }
-    }
-
-    switch(protocol) {
-    case PPP_VJC_COMP:      /* VJ compressed TCP */
-#if VJ_SUPPORT > 0
-        PPPDEBUG((LOG_INFO, "pppInput[%d]: vj_comp in pbuf len=%d\n", pd, nb->len));
-        /*
-         * Clip off the VJ header and prepend the rebuilt TCP/IP header and
-         * pass the result to IP.
-         */
-        if (vj_uncompress_tcp(&nb, &pppControl[pd].vjComp) >= 0) {
-            pppControl[pd].netif.input(nb, &pppControl[pd].netif);
-			return;
-        }
-	/* Something's wrong so drop it. */
-	PPPDEBUG((LOG_WARNING, "pppInput[%d]: Dropping VJ compressed\n", pd));
-#else
-        /* No handler for this protocol so drop the packet. */
-        PPPDEBUG((LOG_INFO, "pppInput[%d]: drop VJ Comp in %d:%s\n", pd, nb->len, nb->payload));
-#endif /* VJ_SUPPORT > 0 */
-	break;
-    case PPP_VJC_UNCOMP:    /* VJ uncompressed TCP */
-#if VJ_SUPPORT > 0
-        PPPDEBUG((LOG_INFO, "pppInput[%d]: vj_un in pbuf len=%d\n", pd, nb->len));
-        /*
-         * Process the TCP/IP header for VJ header compression and then pass
-         * the packet to IP.
-         */
-        if (vj_uncompress_uncomp(nb, &pppControl[pd].vjComp) >= 0) {
-            pppControl[pd].netif.input(nb, &pppControl[pd].netif);
-			return;
-        }
-	/* Something's wrong so drop it. */
-	PPPDEBUG((LOG_WARNING, "pppInput[%d]: Dropping VJ uncompressed\n", pd));
-#else
-        /* No handler for this protocol so drop the packet. */
-        PPPDEBUG((LOG_INFO,
-                    "pppInput[%d]: drop VJ UnComp in %d:.*H\n", 
-                    pd, nb->len, LWIP_MIN(nb->len * 2, 40), nb->payload));
-#endif /* VJ_SUPPORT > 0 */
-	break;
-    case PPP_IP:            /* Internet Protocol */
-        PPPDEBUG((LOG_INFO, "pppInput[%d]: ip in pbuf len=%d\n", pd, nb->len));
-        pppControl[pd].netif.input(nb, &pppControl[pd].netif);
-		return;
-    default:
-	{
-		struct protent *protp;
-		int i;
-
-		/*
-		 * Upcall the proper protocol input routine.
-		 */
-		for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) {
-			if (protp->protocol == protocol && protp->enabled_flag) {
-				PPPDEBUG((LOG_INFO, "pppInput[%d]: %s len=%d\n", pd, protp->name, nb->len));
-				nb = pppSingleBuf(nb);
-				(*protp->input)(pd, nb->payload, nb->len);
-				goto out;
-			}
-		}
-
-		/* No handler for this protocol so reject the packet. */
-		PPPDEBUG((LOG_INFO, "pppInput[%d]: rejecting unsupported proto 0x%04X len=%d\n", pd, protocol, nb->len));
-		pbuf_header(nb, sizeof(protocol));
-#if BYTE_ORDER == LITTLE_ENDIAN
-		protocol = htons(protocol);
-		memcpy(nb->payload, &protocol, sizeof(protocol));
-#endif
-		lcp_sprotrej(pd, nb->payload, nb->len);
-	}
-	break;
-    }
-
-drop:
-#if LINK_STATS
-    lwip_stats.link.drop++;
-#endif
-
-out:
-    pbuf_free(nb);
-    return;
-}
-
-
-/*
- * Drop the input packet.
- */
-static void pppDrop(PPPControl *pc)
-{
-    if (pc->inHead != NULL) {
-#if 0	    
-        PPPDEBUG((LOG_INFO, "pppDrop: %d:%.*H\n", pc->inHead->len, min(60, pc->inHead->len * 2), pc->inHead->payload));
-#endif	
-        PPPDEBUG((LOG_INFO, "pppDrop: pbuf len=%d\n", pc->inHead->len));
-	if (pc->inTail && (pc->inTail != pc->inHead))
-	    pbuf_free(pc->inTail);
-        pbuf_free(pc->inHead);
-        pc->inHead = NULL;
-        pc->inTail = NULL;
-    }
-#if VJ_SUPPORT > 0
-    vj_uncompress_err(&pc->vjComp);
-#endif
-
-#if LINK_STATS
-    lwip_stats.link.drop++;
-#endif /* LINK_STATS */
-}
-
-
-/*
- * Process a received octet string.
- */
-static void pppInProc(int pd, u_char *s, int l)
-{
-    PPPControl *pc = &pppControl[pd];
-    struct pbuf *nextNBuf;
-    u_char curChar;
-
-    PPPDEBUG((LOG_DEBUG, "pppInProc[%d]: got %d bytes\n", pd, l));
-    while (l-- > 0) {
-        curChar = *s++;
-        
-        /* Handle special characters. */
-        if (ESCAPE_P(pc->inACCM, curChar)) {
-            /* Check for escape sequences. */
-            /* XXX Note that this does not handle an escaped 0x5d character which
-             * would appear as an escape character.  Since this is an ASCII ']'
-             * and there is no reason that I know of to escape it, I won't complicate
-             * the code to handle this case. GLL */
-            if (curChar == PPP_ESCAPE)
-                pc->inEscaped = 1;
-            /* Check for the flag character. */
-            else if (curChar == PPP_FLAG) {
-                /* If this is just an extra flag character, ignore it. */
-                if (pc->inState <= PDADDRESS)
-                    ;
-                /* If we haven't received the packet header, drop what has come in. */
-                else if (pc->inState < PDDATA) {
-                    PPPDEBUG((LOG_WARNING,
-                                "pppInProc[%d]: Dropping incomplete packet %d\n", 
-                                pd, pc->inState));
-#if LINK_STATS
-					lwip_stats.link.lenerr++;
-#endif
-                    pppDrop(pc);
-                }
-                /* If the fcs is invalid, drop the packet. */
-                else if (pc->inFCS != PPP_GOODFCS) {
-                    PPPDEBUG((LOG_INFO,
-                                "pppInProc[%d]: Dropping bad fcs 0x%04X proto=0x%04X\n", 
-                                pd, pc->inFCS, pc->inProtocol));
-#if LINK_STATS
-					lwip_stats.link.chkerr++;
-#endif
-                    pppDrop(pc);
-                }
-                /* Otherwise it's a good packet so pass it on. */
-                else {
-                    
-                    /* Trim off the checksum. */
-		    if(pc->inTail->len >= 2) {
-			pc->inTail->len -= 2;
-
-			pc->inTail->tot_len = pc->inTail->len;
-			if (pc->inTail != pc->inHead) {
-			    pbuf_cat(pc->inHead, pc->inTail);
-			}
-		    } else {
-			pc->inTail->tot_len = pc->inTail->len;
-			if (pc->inTail != pc->inHead) {
-			    pbuf_cat(pc->inHead, pc->inTail);
-			}
-
-			pbuf_realloc(pc->inHead, pc->inHead->tot_len - 2);
-		    }
-
-                    /* Dispatch the packet thereby consuming it. */
-		    if(tcpip_callback(pppInput, pc->inHead) != ERR_OK) {
-                    	PPPDEBUG((LOG_ERR,
-				    "pppInProc[%d]: tcpip_callback() failed, dropping packet\n", pd));
-			pbuf_free(pc->inHead);
-#if LINK_STATS
-			lwip_stats.link.drop++;
-#endif
-		    }
-                    pc->inHead = NULL;
-                    pc->inTail = NULL;
-                }
-                    
-                /* Prepare for a new packet. */
-                pc->inFCS = PPP_INITFCS;
-                pc->inState = PDADDRESS;
-                pc->inEscaped = 0;
-            }
-            /* Other characters are usually control characters that may have
-             * been inserted by the physical layer so here we just drop them. */
-            else {
-                PPPDEBUG((LOG_WARNING,
-                            "pppInProc[%d]: Dropping ACCM char <%d>\n", pd, curChar));
-            }
-        }
-        /* Process other characters. */
-        else {
-            /* Unencode escaped characters. */
-            if (pc->inEscaped) {
-                pc->inEscaped = 0;
-                curChar ^= PPP_TRANS;
-            }
-            
-            /* Process character relative to current state. */
-            switch(pc->inState) {
-            case PDIDLE:                    /* Idle state - waiting. */
-                /* Drop the character if it's not 0xff
-                 * we would have processed a flag character above. */
-                if (curChar != PPP_ALLSTATIONS) {
-                	break;
-				}
-
-				/* Fall through */
-            case PDSTART:                   /* Process start flag. */
-                /* Prepare for a new packet. */
-                pc->inFCS = PPP_INITFCS;
-
-				/* Fall through */
-            case PDADDRESS:                 /* Process address field. */
-                if (curChar == PPP_ALLSTATIONS) {
-                    pc->inState = PDCONTROL;
-                    break;
-                }
-                /* Else assume compressed address and control fields so
-                 * fall through to get the protocol... */
-            case PDCONTROL:                 /* Process control field. */
-                /* If we don't get a valid control code, restart. */
-                if (curChar == PPP_UI) {
-                    pc->inState = PDPROTOCOL1;
-                	break;
-                }
-#if 0
-                else {
-                    PPPDEBUG((LOG_WARNING,
-                                "pppInProc[%d]: Invalid control <%d>\n", pd, curChar));
-                    pc->inState = PDSTART;
-                }
-#endif
-            case PDPROTOCOL1:               /* Process protocol field 1. */
-                /* If the lower bit is set, this is the end of the protocol
-                 * field. */
-                if (curChar & 1) {
-                    pc->inProtocol = curChar;
-                    pc->inState = PDDATA;
-                }
-                else {
-                    pc->inProtocol = (u_int)curChar << 8;
-                    pc->inState = PDPROTOCOL2;
-                }
-                break;
-            case PDPROTOCOL2:               /* Process protocol field 2. */
-                pc->inProtocol |= curChar;
-                pc->inState = PDDATA;
-                break;
-            case PDDATA:                    /* Process data byte. */
-                /* Make space to receive processed data. */
-                if (pc->inTail == NULL || pc->inTail->len == PBUF_POOL_BUFSIZE) {
-		    if(pc->inTail) {
-			pc->inTail->tot_len = pc->inTail->len;
-			if (pc->inTail != pc->inHead) {
-			    pbuf_cat(pc->inHead, pc->inTail);
-			}
-		    }
-                    /* If we haven't started a packet, we need a packet header. */
-                    nextNBuf = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL);
-                    if (nextNBuf == NULL) {
-                        /* No free buffers.  Drop the input packet and let the
-                         * higher layers deal with it.  Continue processing
-                         * the received pbuf chain in case a new packet starts. */
-                        PPPDEBUG((LOG_ERR, "pppInProc[%d]: NO FREE MBUFS!\n", pd));
-#if LINK_STATS
-						lwip_stats.link.memerr++;
-#endif /* LINK_STATS */
-                        pppDrop(pc);
-                        pc->inState = PDSTART;  /* Wait for flag sequence. */
-			break;
-                    }
-		    if (pc->inHead == NULL) {
-			struct pppInputHeader *pih = nextNBuf->payload;
-
-			pih->unit = pd;
-			pih->proto = pc->inProtocol;
-
-			nextNBuf->len += sizeof(*pih);
-
-			pc->inHead = nextNBuf;
-		    }
-		    pc->inTail = nextNBuf;
-                }
-                /* Load character into buffer. */
-                ((u_char*)pc->inTail->payload)[pc->inTail->len++] = curChar;
-                break;
-            }
-
-            /* update the frame check sequence number. */
-            pc->inFCS = PPP_FCS(pc->inFCS, curChar);
-        }
-    }
-	avRandomize();
-}
-
-#endif /* PPP_SUPPORT */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/ppp.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/ppp.h
deleted file mode 100644
index dbe12171e..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/ppp.h
+++ /dev/null
@@ -1,446 +0,0 @@
-/*****************************************************************************
-* ppp.h - Network Point to Point Protocol header file.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* portions Copyright (c) 1997 Global Election Systems Inc.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY
-*
-* 03-01-01 Marc Boucher 
-*   Ported to lwIP.
-* 97-11-05 Guy Lancaster , Global Election Systems Inc.
-*	Original derived from BSD codes.
-*****************************************************************************/
-
-#ifndef PPP_H
-#define PPP_H
-
-#include "lwip/opt.h"
-
-#if PPP_SUPPORT > 0
-#include "lwip/sio.h"
-#include "lwip/api.h"
-#include "lwip/sockets.h"
-#include "lwip/stats.h"
-#include "lwip/mem.h"
-#include "lwip/tcpip.h"
-#include "lwip/netif.h"
-
-/*
- * pppd.h - PPP daemon global declarations.
- *
- * Copyright (c) 1989 Carnegie Mellon University.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by Carnegie Mellon University.  The name of the
- * University may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- *
- */
-/*
- * ppp_defs.h - PPP definitions.
- *
- * Copyright (c) 1994 The Australian National University.
- * All rights reserved.
- *
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, provided that the above copyright
- * notice appears in all copies.  This software is provided without any
- * warranty, express or implied. The Australian National University
- * makes no representations about the suitability of this software for
- * any purpose.
- *
- * IN NO EVENT SHALL THE AUSTRALIAN NATIONAL UNIVERSITY BE LIABLE TO ANY
- * PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES
- * ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF
- * THE AUSTRALIAN NATIONAL UNIVERSITY HAVE BEEN ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * THE AUSTRALIAN NATIONAL UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
- * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
- * AND FITNESS FOR A PARTICULAR PURPOSE.  THE SOFTWARE PROVIDED HEREUNDER IS
- * ON AN "AS IS" BASIS, AND THE AUSTRALIAN NATIONAL UNIVERSITY HAS NO
- * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS,
- * OR MODIFICATIONS.
- */
-
-#define TIMEOUT(f, a, t)    sys_untimeout((f), (a)), sys_timeout((t)*1000, (f), (a))
-#define UNTIMEOUT(f, a)     sys_untimeout((f), (a))
-
-
-# ifndef __u_char_defined
-
-/* Type definitions for BSD code. */
-typedef unsigned long u_long;
-typedef unsigned int u_int;
-typedef unsigned short u_short;
-typedef unsigned char u_char;
-
-#endif
-
-/*
- * Constants and structures defined by the internet system,
- * Per RFC 790, September 1981, and numerous additions.
- */
-
-/*
- * The basic PPP frame.
- */
-#define PPP_HDRLEN  4       /* octets for standard ppp header */
-#define PPP_FCSLEN  2       /* octets for FCS */
-
-
-/*
- * Significant octet values.
- */
-#define PPP_ALLSTATIONS 0xff    /* All-Stations broadcast address */
-#define PPP_UI          0x03    /* Unnumbered Information */
-#define PPP_FLAG        0x7e    /* Flag Sequence */
-#define PPP_ESCAPE      0x7d    /* Asynchronous Control Escape */
-#define PPP_TRANS       0x20    /* Asynchronous transparency modifier */
-
-/*
- * Protocol field values.
- */
-#define PPP_IP          0x21    /* Internet Protocol */
-#define PPP_AT          0x29    /* AppleTalk Protocol */
-#define PPP_VJC_COMP    0x2d    /* VJ compressed TCP */
-#define PPP_VJC_UNCOMP  0x2f    /* VJ uncompressed TCP */
-#define PPP_COMP        0xfd    /* compressed packet */
-#define PPP_IPCP        0x8021  /* IP Control Protocol */
-#define PPP_ATCP        0x8029  /* AppleTalk Control Protocol */
-#define PPP_CCP         0x80fd  /* Compression Control Protocol */
-#define PPP_LCP         0xc021  /* Link Control Protocol */
-#define PPP_PAP         0xc023  /* Password Authentication Protocol */
-#define PPP_LQR         0xc025  /* Link Quality Report protocol */
-#define PPP_CHAP        0xc223  /* Cryptographic Handshake Auth. Protocol */
-#define PPP_CBCP        0xc029  /* Callback Control Protocol */
-
-/*
- * Values for FCS calculations.
- */
-#define PPP_INITFCS 0xffff  /* Initial FCS value */
-#define PPP_GOODFCS 0xf0b8  /* Good final FCS value */
-#define PPP_FCS(fcs, c) (((fcs) >> 8) ^ fcstab[((fcs) ^ (c)) & 0xff])
-
-/*
- * Extended asyncmap - allows any character to be escaped.
- */
-typedef u_char  ext_accm[32];
-
-/*
- * What to do with network protocol (NP) packets.
- */
-enum NPmode {
-    NPMODE_PASS,        /* pass the packet through */
-    NPMODE_DROP,        /* silently drop the packet */
-    NPMODE_ERROR,       /* return an error */
-    NPMODE_QUEUE        /* save it up for later. */
-};
-
-/*
- * Inline versions of get/put char/short/long.
- * Pointer is advanced; we assume that both arguments
- * are lvalues and will already be in registers.
- * cp MUST be u_char *.
- */
-#define GETCHAR(c, cp) { \
-    (c) = *(cp)++; \
-}
-#define PUTCHAR(c, cp) { \
-    *(cp)++ = (u_char) (c); \
-}
-
-
-#define GETSHORT(s, cp) { \
-    (s) = *(cp)++ << 8; \
-    (s) |= *(cp)++; \
-}
-#define PUTSHORT(s, cp) { \
-    *(cp)++ = (u_char) ((s) >> 8); \
-    *(cp)++ = (u_char) (s); \
-}
-
-#define GETLONG(l, cp) { \
-    (l) = *(cp)++ << 8; \
-    (l) |= *(cp)++; (l) <<= 8; \
-    (l) |= *(cp)++; (l) <<= 8; \
-    (l) |= *(cp)++; \
-}
-#define PUTLONG(l, cp) { \
-    *(cp)++ = (u_char) ((l) >> 24); \
-    *(cp)++ = (u_char) ((l) >> 16); \
-    *(cp)++ = (u_char) ((l) >> 8); \
-    *(cp)++ = (u_char) (l); \
-}
-
-
-#define INCPTR(n, cp)   ((cp) += (n))
-#define DECPTR(n, cp)   ((cp) -= (n))
-
-#define BCMP(s0, s1, l)     memcmp((u_char *)(s0), (u_char *)(s1), (l))
-#define BCOPY(s, d, l)      memcpy((d), (s), (l))
-#define BZERO(s, n)         memset(s, 0, n)
-#if PPP_DEBUG
-#define PRINTMSG(m, l)  { m[l] = '\0'; ppp_trace(LOG_INFO, "Remote message: %s\n", m); }
-#else
-#define PRINTMSG(m, l)
-#endif
-
-/*
- * MAKEHEADER - Add PPP Header fields to a packet.
- */
-#define MAKEHEADER(p, t) { \
-    PUTCHAR(PPP_ALLSTATIONS, p); \
-    PUTCHAR(PPP_UI, p); \
-    PUTSHORT(t, p); }
-
-/*************************
-*** PUBLIC DEFINITIONS ***
-*************************/
-
-/* Error codes. */
-#define PPPERR_NONE 0				/* No error. */
-#define PPPERR_PARAM -1				/* Invalid parameter. */
-#define PPPERR_OPEN -2				/* Unable to open PPP session. */
-#define PPPERR_DEVICE -3			/* Invalid I/O device for PPP. */
-#define PPPERR_ALLOC -4				/* Unable to allocate resources. */
-#define PPPERR_USER -5				/* User interrupt. */
-#define PPPERR_CONNECT -6			/* Connection lost. */
-#define PPPERR_AUTHFAIL -7			/* Failed authentication challenge. */
-#define PPPERR_PROTOCOL -8			/* Failed to meet protocol. */
-
-/*
- * PPP IOCTL commands.
- */
-/*
- * Get the up status - 0 for down, non-zero for up.  The argument must
- * point to an int.
- */
-#define PPPCTLG_UPSTATUS 100	/* Get the up status - 0 down else up */
-#define PPPCTLS_ERRCODE 101		/* Set the error code */
-#define PPPCTLG_ERRCODE 102		/* Get the error code */
-#define	PPPCTLG_FD		103		/* Get the fd associated with the ppp */
-
-/************************
-*** PUBLIC DATA TYPES ***
-************************/
-
-/*
- * The following struct gives the addresses of procedures to call
- * for a particular protocol.
- */
-struct protent {
-    u_short protocol;       /* PPP protocol number */
-    /* Initialization procedure */
-    void (*init) (int unit);
-    /* Process a received packet */
-    void (*input) (int unit, u_char *pkt, int len);
-    /* Process a received protocol-reject */
-    void (*protrej) (int unit);
-    /* Lower layer has come up */
-    void (*lowerup) (int unit);
-    /* Lower layer has gone down */
-    void (*lowerdown) (int unit);
-    /* Open the protocol */
-    void (*open) (int unit);
-    /* Close the protocol */
-    void (*close) (int unit, char *reason);
-#if 0
-    /* Print a packet in readable form */
-    int  (*printpkt) (u_char *pkt, int len,
-              void (*printer) (void *, char *, ...),
-              void *arg);
-    /* Process a received data packet */
-    void (*datainput) (int unit, u_char *pkt, int len);
-#endif
-    int  enabled_flag;      /* 0 iff protocol is disabled */
-    char *name;         /* Text name of protocol */
-#if 0
-    /* Check requested options, assign defaults */
-    void (*check_options) (u_long);
-    /* Configure interface for demand-dial */
-    int  (*demand_conf) (int unit);
-    /* Say whether to bring up link for this pkt */
-    int  (*active_pkt) (u_char *pkt, int len);
-#endif
-};
-
-/*
- * The following structure records the time in seconds since
- * the last NP packet was sent or received.
- */
-struct ppp_idle {
-    u_short xmit_idle;      /* seconds since last NP packet sent */
-    u_short recv_idle;      /* seconds since last NP packet received */
-};
-
-struct ppp_settings {
-
-	u_int  disable_defaultip : 1;   /* Don't use hostname for default IP addrs */
-	u_int  auth_required : 1;      /* Peer is required to authenticate */
-	u_int  explicit_remote : 1;    /* remote_name specified with remotename opt */
-	u_int  refuse_pap : 1;         /* Don't wanna auth. ourselves with PAP */
-	u_int  refuse_chap : 1;        /* Don't wanna auth. ourselves with CHAP */
-	u_int  usehostname : 1;        /* Use hostname for our_name */
-	u_int  usepeerdns : 1;         /* Ask peer for DNS adds */
-
-	u_short idle_time_limit; /* Shut down link if idle for this long */
-	int  maxconnect;         /* Maximum connect time (seconds) */
-
-	char user[MAXNAMELEN + 1];/* Username for PAP */
-	char passwd[MAXSECRETLEN + 1];           /* Password for PAP, secret for CHAP */
-	char our_name[MAXNAMELEN + 1];         /* Our name for authentication purposes */
-	char remote_name[MAXNAMELEN + 1];      /* Peer's name for authentication */
-};
-
-struct ppp_addrs {
-    struct ip_addr our_ipaddr, his_ipaddr, netmask, dns1, dns2;
-};
-
-/*****************************
-*** PUBLIC DATA STRUCTURES ***
-*****************************/
-/* Buffers for outgoing packets. */
-extern u_char outpacket_buf[NUM_PPP][PPP_MRU+PPP_HDRLEN];
-
-extern struct ppp_settings ppp_settings;
-
-extern struct protent *ppp_protocols[];/* Table of pointers to supported protocols */
-
-
-/***********************
-*** PUBLIC FUNCTIONS ***
-***********************/
-
-/* Initialize the PPP subsystem. */
-void pppInit(void);
-
-/* Warning: Using PPPAUTHTYPE_ANY might have security consequences.
- * RFC 1994 says:
- *
- * In practice, within or associated with each PPP server, there is a
- * database which associates "user" names with authentication
- * information ("secrets").  It is not anticipated that a particular
- * named user would be authenticated by multiple methods.  This would
- * make the user vulnerable to attacks which negotiate the least secure
- * method from among a set (such as PAP rather than CHAP).  If the same
- * secret was used, PAP would reveal the secret to be used later with
- * CHAP.
- *
- * Instead, for each user name there should be an indication of exactly
- * one method used to authenticate that user name.  If a user needs to
- * make use of different authentication methods under different
- * circumstances, then distinct user names SHOULD be employed, each of
- * which identifies exactly one authentication method.
- *
- */
-enum pppAuthType {
-    PPPAUTHTYPE_NONE,
-    PPPAUTHTYPE_ANY,
-    PPPAUTHTYPE_PAP,
-    PPPAUTHTYPE_CHAP
-};
-
-void pppSetAuth(enum pppAuthType authType, const char *user, const char *passwd);
-
-/*
- * Open a new PPP connection using the given I/O device.
- * This initializes the PPP control block but does not
- * attempt to negotiate the LCP session.
- * Return a new PPP connection descriptor on success or
- * an error code (negative) on failure. 
- */
-int pppOpen(sio_fd_t fd, void (*linkStatusCB)(void *ctx, int errCode, void *arg), void *linkStatusCtx);
-
-/*
- * Close a PPP connection and release the descriptor. 
- * Any outstanding packets in the queues are dropped.
- * Return 0 on success, an error code on failure. 
- */
-int pppClose(int pd);
-
-/*
- * Indicate to the PPP process that the line has disconnected.
- */
-void pppSigHUP(int pd);
-
-/*
- * Get and set parameters for the given connection.
- * Return 0 on success, an error code on failure. 
- */
-int  pppIOCtl(int pd, int cmd, void *arg);
-
-/*
- * Return the Maximum Transmission Unit for the given PPP connection.
- */
-u_int pppMTU(int pd);
-
-/*
- * Write n characters to a ppp link.
- *	RETURN: >= 0 Number of characters written
- *		 	 -1 Failed to write to device
- */
-int pppWrite(int pd, const u_char *s, int n);
-
-void pppMainWakeup(int pd);
-
-/* Configure i/f transmit parameters */
-void ppp_send_config (int, int, u32_t, int, int);
-/* Set extended transmit ACCM */
-void ppp_set_xaccm (int, ext_accm *);
-/* Configure i/f receive parameters */
-void ppp_recv_config (int, int, u32_t, int, int);
-/* Find out how long link has been idle */
-int  get_idle_time (int, struct ppp_idle *);
-
-/* Configure VJ TCP header compression */
-int  sifvjcomp (int, int, int, int);
-/* Configure i/f down (for IP) */
-int  sifup (int);		
-/* Set mode for handling packets for proto */
-int  sifnpmode (int u, int proto, enum NPmode mode);
-/* Configure i/f down (for IP) */
-int  sifdown (int);	
-/* Configure IP addresses for i/f */
-int  sifaddr (int, u32_t, u32_t, u32_t, u32_t, u32_t);
-/* Reset i/f IP addresses */
-int  cifaddr (int, u32_t, u32_t);
-/* Create default route through i/f */
-int  sifdefaultroute (int, u32_t, u32_t);
-/* Delete default route through i/f */
-int  cifdefaultroute (int, u32_t, u32_t);
-
-/* Get appropriate netmask for address */
-u32_t GetMask (u32_t); 
-
-#endif /* PPP_SUPPORT */
-
-#endif /* PPP_H */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/pppdebug.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/pppdebug.h
deleted file mode 100644
index de1478cee..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/pppdebug.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/*****************************************************************************
-* pppdebug.h - System debugging utilities.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* portions Copyright (c) 1998 Global Election Systems Inc.
-* portions Copyright (c) 2001 by Cognizant Pty Ltd.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY (please don't use tabs!)
-*
-* 03-01-01 Marc Boucher 
-*   Ported to lwIP.
-* 98-07-29 Guy Lancaster , Global Election Systems Inc.
-*	Original.
-*
-*****************************************************************************
-*/
-#ifndef PPPDEBUG_H
-#define PPPDEBUG_H
-
-/************************
-*** PUBLIC DATA TYPES ***
-************************/
-/* Trace levels. */
-typedef enum {
-	LOG_CRITICAL = 0,
-	LOG_ERR = 1,
-	LOG_NOTICE = 2,
-	LOG_WARNING = 3,
-	LOG_INFO = 5,
-	LOG_DETAIL = 6,
-	LOG_DEBUG = 7
-} LogCodes;
-
-
-/***********************
-*** PUBLIC FUNCTIONS ***
-***********************/
-/*
- *	ppp_trace - a form of printf to send tracing information to stderr
- */
-void ppp_trace(int level, const char *format,...);
-
-#if PPP_DEBUG > 0
-
-#define AUTHDEBUG(a) ppp_trace a
-#define IPCPDEBUG(a) ppp_trace a
-#define UPAPDEBUG(a) ppp_trace a
-#define LCPDEBUG(a) ppp_trace a
-#define FSMDEBUG(a) ppp_trace a
-#define CHAPDEBUG(a) ppp_trace a
-#define PPPDEBUG(a) ppp_trace a
-
-#define TRACELCP 1
-
-#else
-
-#define AUTHDEBUG(a)
-#define IPCPDEBUG(a)
-#define UPAPDEBUG(a)
-#define LCPDEBUG(a)
-#define FSMDEBUG(a)
-#define CHAPDEBUG(a)
-
-#define PPPDEBUG(a)
-
-#define TRACELCP 0
-
-#endif
-
-#endif /* PPPDEBUG_H */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/randm.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/randm.c
deleted file mode 100644
index 05eeb4410..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/randm.c
+++ /dev/null
@@ -1,242 +0,0 @@
-/*****************************************************************************
-* randm.c - Random number generator program file.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* Copyright (c) 1998 by Global Election Systems Inc.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY
-*
-* 03-01-01 Marc Boucher 
-*   Ported to lwIP.
-* 98-06-03 Guy Lancaster , Global Election Systems Inc.
-*   Extracted from avos.
-*****************************************************************************/
-
-#include "ppp.h"
-#if PPP_SUPPORT > 0
-#include "md5.h"
-#include "randm.h"
-
-#include "pppdebug.h"
-
-
-#if MD5_SUPPORT>0   /* this module depends on MD5 */
-#define RANDPOOLSZ 16   /* Bytes stored in the pool of randomness. */
-
-/*****************************/
-/*** LOCAL DATA STRUCTURES ***/
-/*****************************/
-static char randPool[RANDPOOLSZ];   /* Pool of randomness. */
-static long randCount = 0;      /* Pseudo-random incrementer */
-
-
-/***********************************/
-/*** PUBLIC FUNCTION DEFINITIONS ***/
-/***********************************/
-/*
- * Initialize the random number generator.
- *
- * Since this is to be called on power up, we don't have much
- *  system randomess to work with.  Here all we use is the
- *  real-time clock.  We'll accumulate more randomness as soon
- *  as things start happening.
- */
-void avRandomInit()
-{
-    avChurnRand(NULL, 0);
-}
-
-/*
- * Churn the randomness pool on a random event.  Call this early and often
- *  on random and semi-random system events to build randomness in time for
- *  usage.  For randomly timed events, pass a null pointer and a zero length
- *  and this will use the system timer and other sources to add randomness.
- *  If new random data is available, pass a pointer to that and it will be
- *  included.
- *
- * Ref: Applied Cryptography 2nd Ed. by Bruce Schneier p. 427
- */
-void avChurnRand(char *randData, u32_t randLen)
-{
-    MD5_CTX md5;
-
-/*  ppp_trace(LOG_INFO, "churnRand: %u@%P\n", randLen, randData); */
-    MD5Init(&md5);
-    MD5Update(&md5, (u_char *)randPool, sizeof(randPool));
-    if (randData)
-        MD5Update(&md5, (u_char *)randData, randLen);
-    else {
-        struct {
-            /* INCLUDE fields for any system sources of randomness */
-            char foobar;
-        } sysData;
-
-        /* Load sysData fields here. */
-        ;
-        MD5Update(&md5, (u_char *)&sysData, sizeof(sysData));
-    }
-    MD5Final((u_char *)randPool, &md5);
-/*  ppp_trace(LOG_INFO, "churnRand: -> 0\n"); */
-}
-
-/*
- * Use the random pool to generate random data.  This degrades to pseudo
- *  random when used faster than randomness is supplied using churnRand().
- * Note: It's important that there be sufficient randomness in randPool
- *  before this is called for otherwise the range of the result may be
- *  narrow enough to make a search feasible.
- *
- * Ref: Applied Cryptography 2nd Ed. by Bruce Schneier p. 427
- *
- * XXX Why does he not just call churnRand() for each block?  Probably
- *  so that you don't ever publish the seed which could possibly help
- *  predict future values.
- * XXX Why don't we preserve md5 between blocks and just update it with
- *  randCount each time?  Probably there is a weakness but I wish that
- *  it was documented.
- */
-void avGenRand(char *buf, u32_t bufLen)
-{
-    MD5_CTX md5;
-    u_char tmp[16];
-    u32_t n;
-
-    while (bufLen > 0) {
-        n = LWIP_MIN(bufLen, RANDPOOLSZ);
-        MD5Init(&md5);
-        MD5Update(&md5, (u_char *)randPool, sizeof(randPool));
-        MD5Update(&md5, (u_char *)&randCount, sizeof(randCount));
-        MD5Final(tmp, &md5);
-        randCount++;
-        memcpy(buf, tmp, n);
-        buf += n;
-        bufLen -= n;
-    }
-}
-
-/*
- * Return a new random number.
- */
-u32_t avRandom()
-{
-    u32_t newRand;
-
-    avGenRand((char *)&newRand, sizeof(newRand));
-
-    return newRand;
-}
-
-#else /* MD5_SUPPORT */
-
-
-/*****************************/
-/*** LOCAL DATA STRUCTURES ***/
-/*****************************/
-static int  avRandomized = 0;       /* Set when truely randomized. */
-static u32_t avRandomSeed = 0;      /* Seed used for random number generation. */
-
-
-/***********************************/
-/*** PUBLIC FUNCTION DEFINITIONS ***/
-/***********************************/
-/*
- * Initialize the random number generator.
- *
- * Here we attempt to compute a random number seed but even if
- * it isn't random, we'll randomize it later.
- *
- * The current method uses the fields from the real time clock,
- * the idle process counter, the millisecond counter, and the
- * hardware timer tick counter.  When this is invoked
- * in startup(), then the idle counter and timer values may
- * repeat after each boot and the real time clock may not be
- * operational.  Thus we call it again on the first random
- * event.
- */
-void avRandomInit()
-{
-#if 0
-    /* Get a pointer into the last 4 bytes of clockBuf. */
-    u32_t *lptr1 = (u32_t *)((char *)&clockBuf[3]);
-
-    /*
-     * Initialize our seed using the real-time clock, the idle
-     * counter, the millisecond timer, and the hardware timer
-     * tick counter.  The real-time clock and the hardware
-     * tick counter are the best sources of randomness but
-     * since the tick counter is only 16 bit (and truncated
-     * at that), the idle counter and millisecond timer
-     * (which may be small values) are added to help
-     * randomize the lower 16 bits of the seed.
-     */
-    readClk();
-    avRandomSeed += *(u32_t *)clockBuf + *lptr1 + OSIdleCtr
-             + ppp_mtime() + ((u32_t)TM1 << 16) + TM1;
-#else
-    avRandomSeed += sys_jiffies(); /* XXX */
-#endif
-        
-    /* Initialize the Borland random number generator. */
-    srand((unsigned)avRandomSeed);
-}
-
-/*
- * Randomize our random seed value.  Here we use the fact that
- * this function is called at *truely random* times by the polling
- * and network functions.  Here we only get 16 bits of new random
- * value but we use the previous value to randomize the other 16
- * bits.
- */
-void avRandomize(void)
-{
-    static u32_t last_jiffies;
-
-    if (!avRandomized) {
-        avRandomized = !0;
-        avRandomInit();
-        /* The initialization function also updates the seed. */
-    } else {
-/*        avRandomSeed += (avRandomSeed << 16) + TM1; */
-    	avRandomSeed += (sys_jiffies() - last_jiffies); /* XXX */
-    }
-    last_jiffies = sys_jiffies();
-}
-
-/*
- * Return a new random number.
- * Here we use the Borland rand() function to supply a pseudo random
- * number which we make truely random by combining it with our own
- * seed which is randomized by truely random events. 
- * Thus the numbers will be truely random unless there have been no
- * operator or network events in which case it will be pseudo random
- * seeded by the real time clock.
- */
-u32_t avRandom()
-{
-    return ((((u32_t)rand() << 16) + rand()) + avRandomSeed);
-}
-
-
-
-#endif /* MD5_SUPPORT */
-#endif /* PPP_SUPPORT */
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/randm.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/randm.h
deleted file mode 100644
index baa42f0c2..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/randm.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/*****************************************************************************
-* randm.h - Random number generator header file.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* Copyright (c) 1998 Global Election Systems Inc.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY
-*
-* 03-01-01 Marc Boucher 
-*   Ported to lwIP.
-* 98-05-29 Guy Lancaster , Global Election Systems Inc.
-*	Extracted from avos.
-*****************************************************************************/
-
-#ifndef RANDM_H
-#define RANDM_H
-
-/***********************
-*** PUBLIC FUNCTIONS ***
-***********************/
-/*
- * Initialize the random number generator.
- */
-void avRandomInit(void);
-
-/*
- * Churn the randomness pool on a random event.  Call this early and often
- *	on random and semi-random system events to build randomness in time for
- *	usage.  For randomly timed events, pass a null pointer and a zero length
- *	and this will use the system timer and other sources to add randomness.
- *	If new random data is available, pass a pointer to that and it will be
- *	included.
- */
-void avChurnRand(char *randData, u32_t randLen);
-
-/*
- * Randomize our random seed value.  To be called for truely random events
- * such as user operations and network traffic.
- */
-#if MD5_SUPPORT
-#define avRandomize()	avChurnRand(NULL, 0)
-#else
-void avRandomize(void);
-#endif
-
-/*
- * Use the random pool to generate random data.  This degrades to pseudo
- *	random when used faster than randomness is supplied using churnRand().
- *	Thus it's important to make sure that the results of this are not
- *	published directly because one could predict the next result to at
- *	least some degree.  Also, it's important to get a good seed before
- *	the first use.
- */
-void avGenRand(char *buf, u32_t bufLen);
-
-/*
- * Return a new random number.
- */
-u32_t avRandom(void);
-
-
-#endif /* RANDM_H */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/vj.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/vj.c
deleted file mode 100644
index 0636ee11b..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/vj.c
+++ /dev/null
@@ -1,633 +0,0 @@
-/*
- * Routines to compress and uncompess tcp packets (for transmission
- * over low speed serial lines.
- *
- * Copyright (c) 1989 Regents of the University of California.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by the University of California, Berkeley.  The name of the
- * University may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- *
- *	Van Jacobson (van@helios.ee.lbl.gov), Dec 31, 1989:
- *	- Initial distribution.
- *
- * Modified June 1993 by Paul Mackerras, paulus@cs.anu.edu.au,
- * so that the entire packet being decompressed doesn't have
- * to be in contiguous memory (just the compressed header).
- *
- * Modified March 1998 by Guy Lancaster, glanca@gesn.com,
- * for a 16 bit processor.
- */
-
-#include 
-
-#include "ppp.h"
-#include "vj.h"
-#include "pppdebug.h"
-
-#if VJ_SUPPORT > 0
-
-#if LINK_STATS
-#define INCR(counter) ++comp->stats.counter
-#else
-#define INCR(counter)
-#endif
-
-#if defined(NO_CHAR_BITFIELDS)
-#define getip_hl(base)	((base).ip_hl_v&0xf)
-#define getth_off(base)	(((base).th_x2_off&0xf0)>>4)
-#else
-#define getip_hl(base)	((base).ip_hl)
-#define getth_off(base)	((base).th_off)
-#endif
-
-void vj_compress_init(struct vjcompress *comp)
-{
-	register u_int i;
-	register struct cstate *tstate = comp->tstate;
-	
-#if MAX_SLOTS == 0
-	memset((char *)comp, 0, sizeof(*comp));
-#endif
-	comp->maxSlotIndex = MAX_SLOTS - 1;
-	comp->compressSlot = 0;		/* Disable slot ID compression by default. */
-	for (i = MAX_SLOTS - 1; i > 0; --i) {
-		tstate[i].cs_id = i;
-		tstate[i].cs_next = &tstate[i - 1];
-	}
-	tstate[0].cs_next = &tstate[MAX_SLOTS - 1];
-	tstate[0].cs_id = 0;
-	comp->last_cs = &tstate[0];
-	comp->last_recv = 255;
-	comp->last_xmit = 255;
-	comp->flags = VJF_TOSS;
-}
-
-
-/* ENCODE encodes a number that is known to be non-zero.  ENCODEZ
- * checks for zero (since zero has to be encoded in the long, 3 byte
- * form).
- */
-#define ENCODE(n) { \
-	if ((u_short)(n) >= 256) { \
-		*cp++ = 0; \
-		cp[1] = (n); \
-		cp[0] = (n) >> 8; \
-		cp += 2; \
-	} else { \
-		*cp++ = (n); \
-	} \
-}
-#define ENCODEZ(n) { \
-	if ((u_short)(n) >= 256 || (u_short)(n) == 0) { \
-		*cp++ = 0; \
-		cp[1] = (n); \
-		cp[0] = (n) >> 8; \
-		cp += 2; \
-	} else { \
-		*cp++ = (n); \
-	} \
-}
-
-#define DECODEL(f) { \
-	if (*cp == 0) {\
-		u32_t tmp = ntohl(f) + ((cp[1] << 8) | cp[2]); \
-		(f) = htonl(tmp); \
-		cp += 3; \
-	} else { \
-		u32_t tmp = ntohl(f) + (u32_t)*cp++; \
-		(f) = htonl(tmp); \
-	} \
-}
-
-#define DECODES(f) { \
-	if (*cp == 0) {\
-		u_short tmp = ntohs(f) + (((u_short)cp[1] << 8) | cp[2]); \
-		(f) = htons(tmp); \
-		cp += 3; \
-	} else { \
-		u_short tmp = ntohs(f) + (u_short)*cp++; \
-		(f) = htons(tmp); \
-	} \
-}
-
-#define DECODEU(f) { \
-	if (*cp == 0) {\
-		(f) = htons(((u_short)cp[1] << 8) | cp[2]); \
-		cp += 3; \
-	} else { \
-		(f) = htons((u_short)*cp++); \
-	} \
-}
-
-/*
- * vj_compress_tcp - Attempt to do Van Jacobsen header compression on a
- * packet.  This assumes that nb and comp are not null and that the first
- * buffer of the chain contains a valid IP header.
- * Return the VJ type code indicating whether or not the packet was
- * compressed.
- */
-u_int vj_compress_tcp(
-	struct vjcompress *comp,
-	struct pbuf *pb
-)
-{
-	register struct ip *ip = (struct ip *)pb->payload;
-	register struct cstate *cs = comp->last_cs->cs_next;
-	register u_short hlen = getip_hl(*ip);
-	register struct tcphdr *oth;
-	register struct tcphdr *th;
-	register u_short deltaS, deltaA;
-	register u_long deltaL;
-	register u_int changes = 0;
-	u_char new_seq[16];
-	register u_char *cp = new_seq;
-
-	/*	
-	 * Check that the packet is IP proto TCP.
-	 */
-	if (ip->ip_p != IPPROTO_TCP)
-		return (TYPE_IP);
-		
-	/*
-	 * Bail if this is an IP fragment or if the TCP packet isn't
-	 * `compressible' (i.e., ACK isn't set or some other control bit is
-	 * set).  
-	 */
-	if ((ip->ip_off & htons(0x3fff)) || pb->tot_len < 40)
-		return (TYPE_IP);
-	th = (struct tcphdr *)&((long *)ip)[hlen];
-	if ((th->th_flags & (TCP_SYN|TCP_FIN|TCP_RST|TCP_ACK)) != TCP_ACK)
-		return (TYPE_IP);
-		
-	/*
-	 * Packet is compressible -- we're going to send either a
-	 * COMPRESSED_TCP or UNCOMPRESSED_TCP packet.  Either way we need
-	 * to locate (or create) the connection state.  Special case the
-	 * most recently used connection since it's most likely to be used
-	 * again & we don't have to do any reordering if it's used.
-	 */
-	INCR(vjs_packets);
-	if (ip->ip_src.s_addr != cs->cs_ip.ip_src.s_addr 
-			|| ip->ip_dst.s_addr != cs->cs_ip.ip_dst.s_addr 
-			|| *(long *)th != ((long *)&cs->cs_ip)[getip_hl(cs->cs_ip)]) {
-		/*
-		 * Wasn't the first -- search for it.
-		 *
-		 * States are kept in a circularly linked list with
-		 * last_cs pointing to the end of the list.  The
-		 * list is kept in lru order by moving a state to the
-		 * head of the list whenever it is referenced.  Since
-		 * the list is short and, empirically, the connection
-		 * we want is almost always near the front, we locate
-		 * states via linear search.  If we don't find a state
-		 * for the datagram, the oldest state is (re-)used.
-		 */
-		register struct cstate *lcs;
-		register struct cstate *lastcs = comp->last_cs;
-		
-		do {
-			lcs = cs; cs = cs->cs_next;
-			INCR(vjs_searches);
-			if (ip->ip_src.s_addr == cs->cs_ip.ip_src.s_addr
-					&& ip->ip_dst.s_addr == cs->cs_ip.ip_dst.s_addr
-					&& *(long *)th == ((long *)&cs->cs_ip)[getip_hl(cs->cs_ip)])
-				goto found;
-		} while (cs != lastcs);
-		
-		/*
-		 * Didn't find it -- re-use oldest cstate.  Send an
-		 * uncompressed packet that tells the other side what
-		 * connection number we're using for this conversation.
-		 * Note that since the state list is circular, the oldest
-		 * state points to the newest and we only need to set
-		 * last_cs to update the lru linkage.
-		 */
-		INCR(vjs_misses);
-		comp->last_cs = lcs;
-		hlen += getth_off(*th);
-		hlen <<= 2;
-		/* Check that the IP/TCP headers are contained in the first buffer. */
-		if (hlen > pb->len)
-			return (TYPE_IP);
-		goto uncompressed;
-		
-		found:
-		/*
-		 * Found it -- move to the front on the connection list.
-		 */
-		if (cs == lastcs)
-			comp->last_cs = lcs;
-		else {
-			lcs->cs_next = cs->cs_next;
-			cs->cs_next = lastcs->cs_next;
-			lastcs->cs_next = cs;
-		}
-	}
-	
-	oth = (struct tcphdr *)&((long *)&cs->cs_ip)[hlen];
-	deltaS = hlen;
-	hlen += getth_off(*th);
-	hlen <<= 2;
-	/* Check that the IP/TCP headers are contained in the first buffer. */
-	if (hlen > pb->len) {
-		PPPDEBUG((LOG_INFO, "vj_compress_tcp: header len %d spans buffers\n", 
-					hlen));
-		return (TYPE_IP);
-	}
-	
-	/*
-	 * Make sure that only what we expect to change changed. The first
-	 * line of the `if' checks the IP protocol version, header length &
-	 * type of service.  The 2nd line checks the "Don't fragment" bit.
-	 * The 3rd line checks the time-to-live and protocol (the protocol
-	 * check is unnecessary but costless).  The 4th line checks the TCP
-	 * header length.  The 5th line checks IP options, if any.  The 6th
-	 * line checks TCP options, if any.  If any of these things are
-	 * different between the previous & current datagram, we send the
-	 * current datagram `uncompressed'.
-	 */
-	if (((u_short *)ip)[0] != ((u_short *)&cs->cs_ip)[0] 
-			|| ((u_short *)ip)[3] != ((u_short *)&cs->cs_ip)[3] 
-			|| ((u_short *)ip)[4] != ((u_short *)&cs->cs_ip)[4] 
-			|| getth_off(*th) != getth_off(*oth) 
-			|| (deltaS > 5 && BCMP(ip + 1, &cs->cs_ip + 1, (deltaS - 5) << 2)) 
-			|| (getth_off(*th) > 5 && BCMP(th + 1, oth + 1, (getth_off(*th) - 5) << 2)))
-		goto uncompressed;
-	
-	/*
-	 * Figure out which of the changing fields changed.  The
-	 * receiver expects changes in the order: urgent, window,
-	 * ack, seq (the order minimizes the number of temporaries
-	 * needed in this section of code).
-	 */
-	if (th->th_flags & TCP_URG) {
-		deltaS = ntohs(th->th_urp);
-		ENCODEZ(deltaS);
-		changes |= NEW_U;
-	} else if (th->th_urp != oth->th_urp)
-		/* argh! URG not set but urp changed -- a sensible
-		 * implementation should never do this but RFC793
-		 * doesn't prohibit the change so we have to deal
-		 * with it. */
-		goto uncompressed;
-	
-	if ((deltaS = (u_short)(ntohs(th->th_win) - ntohs(oth->th_win))) != 0) {
-		ENCODE(deltaS);
-		changes |= NEW_W;
-	}
-	
-	if ((deltaL = ntohl(th->th_ack) - ntohl(oth->th_ack)) != 0) {
-		if (deltaL > 0xffff)
-			goto uncompressed;
-		deltaA = (u_short)deltaL;
-		ENCODE(deltaA);
-		changes |= NEW_A;
-	}
-	
-	if ((deltaL = ntohl(th->th_seq) - ntohl(oth->th_seq)) != 0) {
-		if (deltaL > 0xffff)
-			goto uncompressed;
-		deltaS = (u_short)deltaL;
-		ENCODE(deltaS);
-		changes |= NEW_S;
-	}
-	
-	switch(changes) {
-	
-	case 0:
-		/*
-		 * Nothing changed. If this packet contains data and the
-		 * last one didn't, this is probably a data packet following
-		 * an ack (normal on an interactive connection) and we send
-		 * it compressed.  Otherwise it's probably a retransmit,
-		 * retransmitted ack or window probe.  Send it uncompressed
-		 * in case the other side missed the compressed version.
-		 */
-		if (ip->ip_len != cs->cs_ip.ip_len &&
-			ntohs(cs->cs_ip.ip_len) == hlen)
-		break;
-	
-	/* (fall through) */
-	
-	case SPECIAL_I:
-	case SPECIAL_D:
-		/*
-		 * actual changes match one of our special case encodings --
-		 * send packet uncompressed.
-		 */
-		goto uncompressed;
-	
-	case NEW_S|NEW_A:
-		if (deltaS == deltaA && deltaS == ntohs(cs->cs_ip.ip_len) - hlen) {
-			/* special case for echoed terminal traffic */
-			changes = SPECIAL_I;
-			cp = new_seq;
-		}
-		break;
-	
-	case NEW_S:
-		if (deltaS == ntohs(cs->cs_ip.ip_len) - hlen) {
-			/* special case for data xfer */
-			changes = SPECIAL_D;
-			cp = new_seq;
-		}
-		break;
-	}
-	
-	deltaS = (u_short)(ntohs(ip->ip_id) - ntohs(cs->cs_ip.ip_id));
-	if (deltaS != 1) {
-		ENCODEZ(deltaS);
-		changes |= NEW_I;
-	}
-	if (th->th_flags & TCP_PSH)
-	changes |= TCP_PUSH_BIT;
-	/*
-	 * Grab the cksum before we overwrite it below.  Then update our
-	 * state with this packet's header.
-	 */
-	deltaA = ntohs(th->th_sum);
-	BCOPY(ip, &cs->cs_ip, hlen);
-	
-	/*
-	 * We want to use the original packet as our compressed packet.
-	 * (cp - new_seq) is the number of bytes we need for compressed
-	 * sequence numbers.  In addition we need one byte for the change
-	 * mask, one for the connection id and two for the tcp checksum.
-	 * So, (cp - new_seq) + 4 bytes of header are needed.  hlen is how
-	 * many bytes of the original packet to toss so subtract the two to
-	 * get the new packet size.
-	 */
-	deltaS = (u_short)(cp - new_seq);
-	if (!comp->compressSlot || comp->last_xmit != cs->cs_id) {
-		comp->last_xmit = cs->cs_id;
-		hlen -= deltaS + 4;
-		pbuf_header(pb, -hlen);
-		cp = (u_char *)pb->payload;
-		*cp++ = changes | NEW_C;
-		*cp++ = cs->cs_id;
-	} else {
-		hlen -= deltaS + 3;
-		pbuf_header(pb, -hlen);
-		cp = (u_char *)pb->payload;
-		*cp++ = changes;
-	}
-	*cp++ = deltaA >> 8;
-	*cp++ = deltaA;
-	BCOPY(new_seq, cp, deltaS);
-	INCR(vjs_compressed);
-	return (TYPE_COMPRESSED_TCP);
-
-	/*
-	 * Update connection state cs & send uncompressed packet (that is,
-	 * a regular ip/tcp packet but with the 'conversation id' we hope
-	 * to use on future compressed packets in the protocol field).
-	 */
-uncompressed:
-	BCOPY(ip, &cs->cs_ip, hlen);
-	ip->ip_p = cs->cs_id;
-	comp->last_xmit = cs->cs_id;
-	return (TYPE_UNCOMPRESSED_TCP);
-}
-
-/*
- * Called when we may have missed a packet.
- */
-void vj_uncompress_err(struct vjcompress *comp)
-{
-    comp->flags |= VJF_TOSS;
-	INCR(vjs_errorin);
-}
-
-/*
- * "Uncompress" a packet of type TYPE_UNCOMPRESSED_TCP.
- * Return 0 on success, -1 on failure.
- */
-int vj_uncompress_uncomp(
-	struct pbuf *nb,
-	struct vjcompress *comp
-)
-{
-	register u_int hlen;
-	register struct cstate *cs;
-	register struct ip *ip;
-	
-	ip = (struct ip *)nb->payload;
-	hlen = getip_hl(*ip) << 2;
-	if (ip->ip_p >= MAX_SLOTS
-			|| hlen + sizeof(struct tcphdr) > nb->len
-			|| (hlen += getth_off(*((struct tcphdr *)&((char *)ip)[hlen])) << 2)
-			    > nb->len
-			|| hlen > MAX_HDR) {
-		PPPDEBUG((LOG_INFO, "vj_uncompress_uncomp: bad cid=%d, hlen=%d buflen=%d\n", 
-					ip->ip_p, hlen, nb->len));
-		comp->flags |= VJF_TOSS;
-		INCR(vjs_errorin);
-		return -1;
-	}
-	cs = &comp->rstate[comp->last_recv = ip->ip_p];
-	comp->flags &=~ VJF_TOSS;
-	ip->ip_p = IPPROTO_TCP;
-	BCOPY(ip, &cs->cs_ip, hlen);
-	cs->cs_hlen = hlen;
-	INCR(vjs_uncompressedin);
-	return 0;
-}
-
-/*
- * Uncompress a packet of type TYPE_COMPRESSED_TCP.
- * The packet is composed of a buffer chain and the first buffer
- * must contain an accurate chain length.
- * The first buffer must include the entire compressed TCP/IP header. 
- * This procedure replaces the compressed header with the uncompressed
- * header and returns the length of the VJ header.
- */
-int vj_uncompress_tcp(
-	struct pbuf **nb,
-	struct vjcompress *comp
-)
-{
-	u_char *cp;
-	struct tcphdr *th;
-	struct cstate *cs;
-	u_short *bp;
-	struct pbuf *n0 = *nb;
-	u32_t tmp;
-	u_int vjlen, hlen, changes;
-	
-	INCR(vjs_compressedin);
-	cp = (u_char *)n0->payload;
-	changes = *cp++;
-	if (changes & NEW_C) {
-		/* 
-		 * Make sure the state index is in range, then grab the state.
-		 * If we have a good state index, clear the 'discard' flag. 
-		 */
-		if (*cp >= MAX_SLOTS) {
-			PPPDEBUG((LOG_INFO, "vj_uncompress_tcp: bad cid=%d\n", *cp));
-			goto bad;
-		}
-		
-		comp->flags &=~ VJF_TOSS;
-		comp->last_recv = *cp++;
-	} else {
-		/* 
-		 * this packet has an implicit state index.  If we've
-		 * had a line error since the last time we got an
-		 * explicit state index, we have to toss the packet. 
-		 */
-		if (comp->flags & VJF_TOSS) {
-			PPPDEBUG((LOG_INFO, "vj_uncompress_tcp: tossing\n"));
-			INCR(vjs_tossed);
-			return (-1);
-		}
-	}
-	cs = &comp->rstate[comp->last_recv];
-	hlen = getip_hl(cs->cs_ip) << 2;
-	th = (struct tcphdr *)&((u_char *)&cs->cs_ip)[hlen];
-	th->th_sum = htons((*cp << 8) | cp[1]);
-	cp += 2;
-	if (changes & TCP_PUSH_BIT)
-		th->th_flags |= TCP_PSH;
-	else
-		th->th_flags &=~ TCP_PSH;
-	
-	switch (changes & SPECIALS_MASK) {
-	case SPECIAL_I:
-		{
-			register u32_t i = ntohs(cs->cs_ip.ip_len) - cs->cs_hlen;
-			/* some compilers can't nest inline assembler.. */
-			tmp = ntohl(th->th_ack) + i;
-			th->th_ack = htonl(tmp);
-			tmp = ntohl(th->th_seq) + i;
-			th->th_seq = htonl(tmp);
-		}
-		break;
-	
-	case SPECIAL_D:
-		/* some compilers can't nest inline assembler.. */
-		tmp = ntohl(th->th_seq) + ntohs(cs->cs_ip.ip_len) - cs->cs_hlen;
-		th->th_seq = htonl(tmp);
-		break;
-	
-	default:
-		if (changes & NEW_U) {
-			th->th_flags |= TCP_URG;
-			DECODEU(th->th_urp);
-		} else
-			th->th_flags &=~ TCP_URG;
-		if (changes & NEW_W)
-			DECODES(th->th_win);
-		if (changes & NEW_A)
-			DECODEL(th->th_ack);
-		if (changes & NEW_S)
-			DECODEL(th->th_seq);
-		break;
-	}
-	if (changes & NEW_I) {
-		DECODES(cs->cs_ip.ip_id);
-	} else {
-		cs->cs_ip.ip_id = ntohs(cs->cs_ip.ip_id) + 1;
-		cs->cs_ip.ip_id = htons(cs->cs_ip.ip_id);
-	}
-	
-	/*
-	 * At this point, cp points to the first byte of data in the
-	 * packet.  Fill in the IP total length and update the IP
-	 * header checksum.
-	 */
-	vjlen = (u_short)(cp - (u_char*)n0->payload);
-	if (n0->len < vjlen) {
-		/* 
-		 * We must have dropped some characters (crc should detect
-		 * this but the old slip framing won't) 
-		 */
-		PPPDEBUG((LOG_INFO, "vj_uncompress_tcp: head buffer %d too short %d\n", 
-				  n0->len, vjlen));
-		goto bad;
-	}
-	
-#if BYTE_ORDER == LITTLE_ENDIAN
-	tmp = n0->tot_len - vjlen + cs->cs_hlen;
-	cs->cs_ip.ip_len = htons(tmp);
-#else
-	cs->cs_ip.ip_len = htons(n0->tot_len - vjlen + cs->cs_hlen);
-#endif
-	
-	/* recompute the ip header checksum */
-	bp = (u_short *) &cs->cs_ip;
-	cs->cs_ip.ip_sum = 0;
-	for (tmp = 0; hlen > 0; hlen -= 2)
-		tmp += *bp++;
-	tmp = (tmp & 0xffff) + (tmp >> 16);
-	tmp = (tmp & 0xffff) + (tmp >> 16);
-	cs->cs_ip.ip_sum = (u_short)(~tmp);
-	
-	/* Remove the compressed header and prepend the uncompressed header. */
-	pbuf_header(n0, -vjlen);
-
-	if(MEM_ALIGN(n0->payload) != n0->payload) {
-		struct pbuf *np, *q;
-		u8_t *bufptr;
-
-		np = pbuf_alloc(PBUF_RAW, n0->len + cs->cs_hlen, PBUF_POOL);
-		if(!np) {
-			PPPDEBUG((LOG_WARNING, "vj_uncompress_tcp: realign failed\n"));
-			*nb = NULL;
-			goto bad;
-		}
-
-		pbuf_header(np, -cs->cs_hlen);
-
-		bufptr = n0->payload;
-		for(q = np; q != NULL; q = q->next) {
-			memcpy(q->payload, bufptr, q->len);
-			bufptr += q->len;
-		}
-
-		if(n0->next) {
-			pbuf_chain(np, n0->next);
-			pbuf_dechain(n0);
-		}
-		pbuf_free(n0);
-		n0 = np;
-	}
-
-	if(pbuf_header(n0, cs->cs_hlen)) {
-		struct pbuf *np;
-
-		LWIP_ASSERT("vj_uncompress_tcp: cs->cs_hlen <= PBUF_POOL_BUFSIZE", cs->cs_hlen <= PBUF_POOL_BUFSIZE);
-		np = pbuf_alloc(PBUF_RAW, cs->cs_hlen, PBUF_POOL);
-		if(!np) {
-			PPPDEBUG((LOG_WARNING, "vj_uncompress_tcp: prepend failed\n"));
-			*nb = NULL;
-			goto bad;
-		}
-		pbuf_cat(np, n0);
-		n0 = np;
-	}
-	LWIP_ASSERT("n0->len >= cs->cs_hlen", n0->len >= cs->cs_hlen);
-	memcpy(n0->payload, &cs->cs_ip, cs->cs_hlen);
-
-	*nb = n0;
-
-	return vjlen;
-	
-bad:
-	comp->flags |= VJF_TOSS;
-	INCR(vjs_errorin);
-	return (-1);
-}
-
-#endif
-
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/vj.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/vj.h
deleted file mode 100644
index 717208145..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/vj.h
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * Definitions for tcp compression routines.
- *
- * $Id: vj.h,v 1.4 2004/02/07 00:30:03 likewise Exp $
- *
- * Copyright (c) 1989 Regents of the University of California.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by the University of California, Berkeley.  The name of the
- * University may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- *
- *	Van Jacobson (van@helios.ee.lbl.gov), Dec 31, 1989:
- *	- Initial distribution.
- */
-
-#ifndef VJ_H
-#define VJ_H
-
-#include "vjbsdhdr.h"
-
-#define MAX_SLOTS	16			/* must be > 2 and < 256 */
-#define MAX_HDR		128
-
-/*
- * Compressed packet format:
- *
- * The first octet contains the packet type (top 3 bits), TCP
- * 'push' bit, and flags that indicate which of the 4 TCP sequence
- * numbers have changed (bottom 5 bits).  The next octet is a
- * conversation number that associates a saved IP/TCP header with
- * the compressed packet.  The next two octets are the TCP checksum
- * from the original datagram.  The next 0 to 15 octets are
- * sequence number changes, one change per bit set in the header
- * (there may be no changes and there are two special cases where
- * the receiver implicitly knows what changed -- see below).
- * 
- * There are 5 numbers which can change (they are always inserted
- * in the following order): TCP urgent pointer, window,
- * acknowlegement, sequence number and IP ID.  (The urgent pointer
- * is different from the others in that its value is sent, not the
- * change in value.)  Since typical use of SLIP links is biased
- * toward small packets (see comments on MTU/MSS below), changes
- * use a variable length coding with one octet for numbers in the
- * range 1 - 255 and 3 octets (0, MSB, LSB) for numbers in the
- * range 256 - 65535 or 0.  (If the change in sequence number or
- * ack is more than 65535, an uncompressed packet is sent.)
- */
-
-/*
- * Packet types (must not conflict with IP protocol version)
- *
- * The top nibble of the first octet is the packet type.  There are
- * three possible types: IP (not proto TCP or tcp with one of the
- * control flags set); uncompressed TCP (a normal IP/TCP packet but
- * with the 8-bit protocol field replaced by an 8-bit connection id --
- * this type of packet syncs the sender & receiver); and compressed
- * TCP (described above).
- *
- * LSB of 4-bit field is TCP "PUSH" bit (a worthless anachronism) and
- * is logically part of the 4-bit "changes" field that follows.  Top
- * three bits are actual packet type.  For backward compatibility
- * and in the interest of conserving bits, numbers are chosen so the
- * IP protocol version number (4) which normally appears in this nibble
- * means "IP packet".
- */
-
-/* packet types */
-#define TYPE_IP 0x40
-#define TYPE_UNCOMPRESSED_TCP 0x70
-#define TYPE_COMPRESSED_TCP 0x80
-#define TYPE_ERROR 0x00
-
-/* Bits in first octet of compressed packet */
-#define NEW_C	0x40	/* flag bits for what changed in a packet */
-#define NEW_I	0x20
-#define NEW_S	0x08
-#define NEW_A	0x04
-#define NEW_W	0x02
-#define NEW_U	0x01
-
-/* reserved, special-case values of above */
-#define SPECIAL_I (NEW_S|NEW_W|NEW_U)		/* echoed interactive traffic */
-#define SPECIAL_D (NEW_S|NEW_A|NEW_W|NEW_U)	/* unidirectional data */
-#define SPECIALS_MASK (NEW_S|NEW_A|NEW_W|NEW_U)
-
-#define TCP_PUSH_BIT 0x10
-
-
-/*
- * "state" data for each active tcp conversation on the wire.  This is
- * basically a copy of the entire IP/TCP header from the last packet
- * we saw from the conversation together with a small identifier
- * the transmit & receive ends of the line use to locate saved header.
- */
-struct cstate {
-    struct cstate *cs_next;	/* next most recently used state (xmit only) */
-    u_short cs_hlen;		/* size of hdr (receive only) */
-    u_char cs_id;			/* connection # associated with this state */
-    u_char cs_filler;
-    union {
-		char csu_hdr[MAX_HDR];
-		struct ip csu_ip;	/* ip/tcp hdr from most recent packet */
-    } vjcs_u;
-};
-#define cs_ip vjcs_u.csu_ip
-#define cs_hdr vjcs_u.csu_hdr
-
-
-struct vjstat {
-    unsigned long vjs_packets;			/* outbound packets */
-    unsigned long vjs_compressed;		/* outbound compressed packets */
-    unsigned long vjs_searches;			/* searches for connection state */
-    unsigned long vjs_misses;			/* times couldn't find conn. state */
-    unsigned long vjs_uncompressedin;	/* inbound uncompressed packets */
-    unsigned long vjs_compressedin;		/* inbound compressed packets */
-    unsigned long vjs_errorin;			/* inbound unknown type packets */
-    unsigned long vjs_tossed;			/* inbound packets tossed because of error */
-};
-
-/*
- * all the state data for one serial line (we need one of these per line).
- */
-struct vjcompress {
-    struct cstate *last_cs;	/* most recently used tstate */
-    u_char last_recv;		/* last rcvd conn. id */
-    u_char last_xmit;		/* last sent conn. id */
-    u_short flags;
-    u_char maxSlotIndex;
-    u_char compressSlot;	/* Flag indicating OK to compress slot ID. */
-#if LINK_STATS
-    struct vjstat stats;
-#endif
-    struct cstate tstate[MAX_SLOTS];	/* xmit connection states */
-    struct cstate rstate[MAX_SLOTS];	/* receive connection states */
-};
-
-/* flag values */
-#define VJF_TOSS 1U		/* tossing rcvd frames because of input err */
-
-extern void  vj_compress_init (struct vjcompress *comp);
-extern u_int vj_compress_tcp (struct vjcompress *comp, struct pbuf *pb);
-extern void  vj_uncompress_err (struct vjcompress *comp);
-extern int vj_uncompress_uncomp(struct pbuf *nb, struct vjcompress *comp);
-extern int vj_uncompress_tcp(struct pbuf **nb, struct vjcompress *comp);
-
-#endif /* VJ_H */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/vjbsdhdr.h b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/vjbsdhdr.h
deleted file mode 100644
index a089352ad..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/ppp/vjbsdhdr.h
+++ /dev/null
@@ -1,76 +0,0 @@
-#ifndef VJBSDHDR_H
-#define VJBSDHDR_H
-
-#include "lwip/tcp.h"
-
-
-/*
- * Structure of an internet header, naked of options.
- *
- * We declare ip_len and ip_off to be short, rather than u_short
- * pragmatically since otherwise unsigned comparisons can result
- * against negative integers quite easily, and fail in subtle ways.
- */
-PACK_STRUCT_BEGIN
-struct ip
-{
-#if defined(NO_CHAR_BITFIELDS)
-	u_char ip_hl_v;	/* bug in GCC for mips means the bitfield stuff will sometimes break - so we use a char for both and get round it with macro's instead... */
-#else
-#if BYTE_ORDER == LITTLE_ENDIAN
-	unsigned ip_hl:4,				/* header length */
-		ip_v:4;						/* version */
-#elif BYTE_ORDER == BIG_ENDIAN 
-	unsigned ip_v:4,					/* version */
-		ip_hl:4;					/* header length */
-#else
-	COMPLAIN - NO BYTE ORDER SELECTED!
-#endif
-#endif
-	u_char	ip_tos;					/* type of service */
-	u_short	ip_len;					/* total length */
-	u_short	ip_id;					/* identification */
-	u_short	ip_off;					/* fragment offset field */
-#define	IP_DF 0x4000				/* dont fragment flag */
-#define	IP_MF 0x2000				/* more fragments flag */
-#define	IP_OFFMASK 0x1fff			/* mask for fragmenting bits */
-	u_char	ip_ttl;					/* time to live */
-	u_char	ip_p;					/* protocol */
-	u_short	ip_sum;					/* checksum */
-	struct	in_addr ip_src,ip_dst;	/* source and dest address */
-};
-PACK_STRUCT_END
-
-typedef u32_t tcp_seq;
-
-/*
- * TCP header.
- * Per RFC 793, September, 1981.
- */
-PACK_STRUCT_BEGIN
-struct tcphdr  
-{
-	u_short	th_sport;		/* source port */
-	u_short	th_dport;		/* destination port */
-	tcp_seq	th_seq;			/* sequence number */
-	tcp_seq	th_ack;			/* acknowledgement number */
-#if defined(NO_CHAR_BITFIELDS)
-	u_char th_x2_off;
-#else
-#if BYTE_ORDER == LITTLE_ENDIAN
-	unsigned	th_x2:4,		/* (unused) */
-			th_off:4;		/* data offset */
-#endif
-#if BYTE_ORDER == BIG_ENDIAN 
-	unsigned	th_off:4,		/* data offset */
-			th_x2:4;		/* (unused) */
-#endif
-#endif
-	u_char	th_flags;
-	u_short	th_win;			/* window */
-	u_short	th_sum;			/* checksum */
-	u_short	th_urp;			/* urgent pointer */
-};
-PACK_STRUCT_END
-
-#endif /* VJBSDHDR_H */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/slipif.c b/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/slipif.c
deleted file mode 100644
index 776c13f7a..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwip-1.1.0/src/netif/slipif.c
+++ /dev/null
@@ -1,210 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- *
- * Redistribution and use in source and binary forms, with or without 
- * modification, are permitted provided that the following conditions 
- * are met: 
- * 1. Redistributions of source code must retain the above copyright 
- *    notice, this list of conditions and the following disclaimer. 
- * 2. Redistributions in binary form must reproduce the above copyright 
- *    notice, this list of conditions and the following disclaimer in the 
- *    documentation and/or other materials provided with the distribution. 
- * 3. Neither the name of the Institute nor the names of its contributors 
- *    may be used to endorse or promote products derived from this software 
- *    without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
- * SUCH DAMAGE. 
- *
- * This file is built upon the file: src/arch/rtxc/netif/sioslip.c
- *
- * Author: Magnus Ivarsson  
- */
-
-/* 
- * This is an arch independent SLIP netif. The specific serial hooks must be provided 
- * by another file.They are sio_open, sio_recv and sio_send
- */ 
-
-#include "netif/slipif.h"
-#include "lwip/opt.h"
-#include "lwip/def.h"
-#include "lwip/pbuf.h"
-#include "lwip/sys.h"
-#include "lwip/stats.h"
-#include "lwip/sio.h"
-
-#define SLIP_END     0300
-#define SLIP_ESC     0333
-#define SLIP_ESC_END 0334
-#define SLIP_ESC_ESC 0335
-
-#define MAX_SIZE     1500
-
-/**
- * Send a pbuf doing the necessary SLIP encapsulation
- *
- * Uses the serial layer's sio_send() 
- */ 
-err_t
-slipif_output(struct netif *netif, struct pbuf *p, struct ip_addr *ipaddr)
-{
-  struct pbuf *q;
-  int i;
-  u8_t c;
-
-  /* Send pbuf out on the serial I/O device. */
-  sio_send(SLIP_END, netif->state);
-
-  for(q = p; q != NULL; q = q->next) {
-    for(i = 0; i < q->len; i++) {
-      c = ((u8_t *)q->payload)[i];
-      switch (c) {
-      case SLIP_END:
-  sio_send(SLIP_ESC, netif->state);
-  sio_send(SLIP_ESC_END, netif->state);
-  break;
-      case SLIP_ESC:
-  sio_send(SLIP_ESC, netif->state);
-  sio_send(SLIP_ESC_ESC, netif->state);
-  break;
-      default:
-  sio_send(c, netif->state);
-  break;
-      }
-    }
-  }
-  sio_send(SLIP_END, netif->state);
-  return 0;
-}
-
-/**
- * Handle the incoming SLIP stream character by character
- *
- * Poll the serial layer by calling sio_recv()
- * 
- * @return The IP packet when SLIP_END is received 
- */ 
-static struct pbuf *
-slipif_input( struct netif * netif )
-{
-  u8_t c;
-  struct pbuf *p, *q;
-  int recved;
-  int i;
-
-  q = p = NULL;
-  recved = i = 0;
-  c = 0;
-
-  while (1) {
-    c = sio_recv(netif->state);
-    switch (c) {
-    case SLIP_END:
-      if (recved > 0) {
-  /* Received whole packet. */
-  pbuf_realloc(q, recved);
-  
-  LINK_STATS_INC(link.recv);
-  
-  LWIP_DEBUGF(SLIP_DEBUG, ("slipif: Got packet\n"));
-  return q;
-      }
-      break;
-
-    case SLIP_ESC:
-      c = sio_recv(netif->state);
-      switch (c) {
-      case SLIP_ESC_END:
-  c = SLIP_END;
-  break;
-      case SLIP_ESC_ESC:
-  c = SLIP_ESC;
-  break;
-      }
-      /* FALLTHROUGH */
-      
-    default:
-      if (p == NULL) {
-  LWIP_DEBUGF(SLIP_DEBUG, ("slipif_input: alloc\n"));
-  p = pbuf_alloc(PBUF_LINK, PBUF_POOL_BUFSIZE, PBUF_POOL);
-
-  if (p == NULL) {
-    LINK_STATS_INC(link.drop);
-    LWIP_DEBUGF(SLIP_DEBUG, ("slipif_input: no new pbuf! (DROP)\n"));
-  }
-  
-  if (q != NULL) {
-    pbuf_cat(q, p);
-  } else {
-    q = p;
-  }
-      }
-      if (p != NULL && recved < MAX_SIZE) {
-  ((u8_t *)p->payload)[i] = c;
-  recved++;
-  i++;
-  if (i >= p->len) {
-    i = 0;
-    p = NULL;
-  }
-      }
-      break;
-    }
-    
-  }
-  return NULL;
-}
-
-/**
- * The SLIP input thread 
- *
- * Feed the IP layer with incoming packets
- */ 
-static void
-slipif_loop(void *nf)
-{
-  struct pbuf *p;
-  struct netif *netif = (struct netif *)nf;
-
-  while (1) {
-    p = slipif_input(netif);
-    netif->input(p, netif);
-  }
-}
-
-/**
- * SLIP netif initialization
- *
- * Call the arch specific sio_open and remember
- * the opened device in the state field of the netif.
- */ 
-err_t
-slipif_init(struct netif *netif)
-{
-  
-  LWIP_DEBUGF(SLIP_DEBUG, ("slipif_init: netif->num=%x\n", (int)netif->num));
-
-  netif->name[0] = 's';
-  netif->name[1] = 'l';
-  netif->output = slipif_output;
-  netif->mtu = 1500;  
-  netif->flags = NETIF_FLAG_POINTTOPOINT;
-
-  netif->state = sio_open(netif->num);
-  if (!netif->state)
-      return ERR_IF;
-
-  sys_thread_new(slipif_loop, netif, SLIPIF_THREAD_PRIO);
-  return ERR_OK;
-}
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/lwipopts.h b/Demo/lwIP_Demo_Rowley_ARM7/lwipopts.h
deleted file mode 100644
index f58fe2e1a..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/lwipopts.h
+++ /dev/null
@@ -1,179 +0,0 @@
-/*
- * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIPOPTS_H__
-#define __LWIPOPTS_H__
-
-#define LWIP_NOASSERT 1 // To suppress some errors for now (no debug output)
-#define SYS_LIGHTWEIGHT_PROT            1
-
-#define TCPIP_THREAD_PRIO	3
-
-/* ---------- Memory options ---------- */
-/* MEM_ALIGNMENT: should be set to the alignment of the CPU for which
-   lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4, 2
-   byte alignment -> define MEM_ALIGNMENT to 2. */
-#define MEM_ALIGNMENT           4
-
-/* MEM_SIZE: the size of the heap memory. If the application will send
-a lot of data that needs to be copied, this should be set high. */
-#define MEM_SIZE                2000
-
-/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application
-   sends a lot of data out of ROM (or other static memory), this
-   should be set high. */
-#define MEMP_NUM_PBUF           20
-/* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One
-   per active UDP "connection". */
-#define MEMP_NUM_UDP_PCB        4
-/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP
-   connections. */
-#define MEMP_NUM_TCP_PCB        10
-/* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP
-   connections. */
-#define MEMP_NUM_TCP_PCB_LISTEN 8
-/* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP
-   segments. */
-#define MEMP_NUM_TCP_SEG        8
-/* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active
-   timeouts. */
-#define MEMP_NUM_SYS_TIMEOUT    3
-
-
-/* The following four are used only with the sequential API and can be
-   set to 0 if the application only will use the raw API. */
-/* MEMP_NUM_NETBUF: the number of struct netbufs. */
-#define MEMP_NUM_NETBUF         4
-/* MEMP_NUM_NETCONN: the number of struct netconns. */
-#define MEMP_NUM_NETCONN        4
-/* MEMP_NUM_APIMSG: the number of struct api_msg, used for
-   communication between the TCP/IP stack and the sequential
-   programs. */
-#define MEMP_NUM_API_MSG        8
-/* MEMP_NUM_TCPIPMSG: the number of struct tcpip_msg, which is used
-   for sequential API communication and incoming packets. Used in
-   src/api/tcpip.c. */
-#define MEMP_NUM_TCPIP_MSG      8
-
-/* These two control is reclaimer functions should be compiled
-   in. Should always be turned on (1). */
-#define MEM_RECLAIM             1
-#define MEMP_RECLAIM            1
-
-/* ---------- Pbuf options ---------- */
-/* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */
-#define PBUF_POOL_SIZE          4
-
-/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */
-#define PBUF_POOL_BUFSIZE       1500
-
-/* PBUF_LINK_HLEN: the number of bytes that should be allocated for a
-   link level header. */
-#define PBUF_LINK_HLEN          16
-
-/* ---------- TCP options ---------- */
-#define LWIP_TCP                1
-#define TCP_TTL                 255
-
-/* Controls if TCP should queue segments that arrive out of
-   order. Define to 0 if your device is low on memory. */
-#define TCP_QUEUE_OOSEQ         1
-
-/* TCP Maximum segment size. */
-#define TCP_MSS                 1500
-
-/* TCP sender buffer space (bytes). */
-#define TCP_SND_BUF             1500
-
-/* TCP sender buffer space (pbufs). This must be at least = 2 *
-   TCP_SND_BUF/TCP_MSS for things to work. */
-#define TCP_SND_QUEUELEN        6 * TCP_SND_BUF/TCP_MSS
-
-/* TCP receive window. */
-#define TCP_WND                 1500
-
-/* Maximum number of retransmissions of data segments. */
-#define TCP_MAXRTX              12
-
-/* Maximum number of retransmissions of SYN segments. */
-#define TCP_SYNMAXRTX           4
-
-/* ---------- ARP options ---------- */
-#define ARP_TABLE_SIZE 10
-#define ARP_QUEUEING 1
-
-/* ---------- IP options ---------- */
-/* Define IP_FORWARD to 1 if you wish to have the ability to forward
-   IP packets across network interfaces. If you are going to run lwIP
-   on a device with only one network interface, define this to 0. */
-#define IP_FORWARD              1
-
-/* If defined to 1, IP options are allowed (but not parsed). If
-   defined to 0, all packets with IP options are dropped. */
-#define IP_OPTIONS              1
-
-/* ---------- ICMP options ---------- */
-#define ICMP_TTL                255
-
-
-/* ---------- DHCP options ---------- */
-/* Define LWIP_DHCP to 1 if you want DHCP configuration of
-   interfaces. DHCP is not implemented in lwIP 0.5.1, however, so
-   turning this on does currently not work. */
-#define LWIP_DHCP               0
-
-/* 1 if you want to do an ARP check on the offered address
-   (recommended). */
-#define DHCP_DOES_ARP_CHECK     1
-
-/* ---------- UDP options ---------- */
-#define LWIP_UDP                1
-#define UDP_TTL                 255
-
-
-/* ---------- Statistics options ---------- */
-#define STATS
-
-#ifdef STATS
-#define LINK_STATS 1
-#define IP_STATS   1
-#define ICMP_STATS 1
-#define UDP_STATS  1
-#define TCP_STATS  1
-#define MEM_STATS  1
-#define MEMP_STATS 1
-#define PBUF_STATS 1
-#define SYS_STATS  1
-#endif /* STATS */
-
-#define LWIP_PROVIDE_ERRNO 1
-
-#endif /* __LWIPOPTS_H__ */
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/main.c b/Demo/lwIP_Demo_Rowley_ARM7/main.c
deleted file mode 100644
index a4f421413..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/main.c
+++ /dev/null
@@ -1,298 +0,0 @@
-/*
-	FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
-
-	This file is part of the FreeRTOS.org distribution.
-
-	FreeRTOS.org is free software; you can redistribute it and/or modify
-	it under the terms of the GNU General Public License as published by
-	the Free Software Foundation; either version 2 of the License, or
-	(at your option) any later version.
-
-	FreeRTOS.org is distributed in the hope that it will be useful,
-	but WITHOUT ANY WARRANTY; without even the implied warranty of
-	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-	GNU General Public License for more details.
-
-	You should have received a copy of the GNU General Public License
-	along with FreeRTOS.org; if not, write to the Free Software
-	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-
-	A special exception to the GPL can be applied should you wish to distribute
-	a combined work that includes FreeRTOS.org, without being obliged to provide
-	the source code for any proprietary components.  See the licensing section
-	of http://www.FreeRTOS.org for full details of how and when the exception
-	can be applied.
-
-	***************************************************************************
-	See http://www.FreeRTOS.org for documentation, latest information, license
-	and contact details.  Please ensure to read the configuration and relevant
-	port sections of the online documentation.
-	***************************************************************************
-*/
-
-/* 
-	NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.
-	The processor MUST be in supervisor mode when vTaskStartScheduler is 
-	called.  The demo applications included in the FreeRTOS.org download switch
-	to supervisor mode prior to main being called.  If you are not using one of
-	these demo application projects then ensure Supervisor mode is used.
-*/
-
-
-/*
- * Creates all the application tasks, then starts the scheduler.
- *
- * A task defined by the function vBasicWEBServer is created.  This executes 
- * the lwIP stack and basic WEB server sample.  A task defined by the function
- * vUSBCDCTask.  This executes the USB to serial CDC example.  All the other 
- * tasks are from the set of standard demo tasks.  The WEB documentation 
- * provides more details of the standard demo application tasks.
- *
- * Main.c also creates a task called "Check".  This only executes every three
- * seconds but has the highest priority so is guaranteed to get processor time.
- * Its main function is to check the status of all the other demo application
- * tasks.  LED mainCHECK_LED is toggled every three seconds by the check task
- * should no error conditions be detected in any of the standard demo tasks.
- * The toggle rate increasing to 500ms indicates that at least one error has
- * been detected.
- *
- * Main.c includes an idle hook function that simply periodically sends data
- * to the USB task for transmission.
- */
-
-/*
-	Changes from V3.2.2
-
-	+ Modified the stack sizes used by some tasks to permit use of the 
-	  command line GCC tools.
-*/
-
-/* Library includes. */
-#include 
-#include 
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Demo application includes. */
-#include "partest.h"
-#include "PollQ.h"
-#include "semtest.h"
-#include "flash.h"
-#include "integer.h"
-#include "BlockQ.h"
-#include "BasicWEB.h"
-#include "USB-CDC.h"
-
-/* lwIP includes. */
-#include "lwip/api.h" 
-
-/* Hardware specific headers. */
-#include "Board.h"
-#include "AT91SAM7X256.h"
-
-/* Priorities/stacks for the various tasks within the demo application. */
-#define mainQUEUE_POLL_PRIORITY		( tskIDLE_PRIORITY + 1 )
-#define mainCHECK_TASK_PRIORITY		( tskIDLE_PRIORITY + 3 )
-#define mainSEM_TEST_PRIORITY		( tskIDLE_PRIORITY + 1 )
-#define mainFLASH_PRIORITY			( tskIDLE_PRIORITY + 2 )
-#define mainBLOCK_Q_PRIORITY		( tskIDLE_PRIORITY + 1 )
-#define mainWEBSERVER_PRIORITY      ( tskIDLE_PRIORITY + 2 )
-#define mainUSB_PRIORITY			( tskIDLE_PRIORITY + 1 )
-#define mainUSB_TASK_STACK			( 200 )
-
-/* The rate at which the on board LED will toggle when there is/is not an
-error. */
-#define mainNO_ERROR_FLASH_PERIOD	( ( portTickType ) 3000 / portTICK_RATE_MS  )
-#define mainERROR_FLASH_PERIOD		( ( portTickType ) 500 / portTICK_RATE_MS  )
-
-/* The rate at which the idle hook sends data to the USB port. */
-#define mainUSB_TX_FREQUENCY		( 100 / portTICK_RATE_MS )
-
-/* The string that is transmitted down the USB port. */
-#define mainFIRST_TX_CHAR			'a'
-#define mainLAST_TX_CHAR			'z'
-
-/* The LED used by the check task to indicate the system status. */
-#define mainCHECK_LED 				( 3 )
-/*-----------------------------------------------------------*/
-
-/*
- * Checks that all the demo application tasks are still executing without error
- * - as described at the top of the file.
- */
-static portLONG prvCheckOtherTasksAreStillRunning( void );
-
-/*
- * The task that executes at the highest priority and calls
- * prvCheckOtherTasksAreStillRunning().  See the description at the top
- * of the file.
- */
-static void vErrorChecks( void *pvParameters );
-
-/*
- * Configure the processor for use with the Atmel demo board.  This is very
- * minimal as most of the setup is performed in the startup code.
- */
-static void prvSetupHardware( void );
-
-/*
- * The idle hook is just used to stream data to the USB port.
- */
-void vApplicationIdleHook( void );
-/*-----------------------------------------------------------*/
-
-/*
- * Setup hardware then start all the demo application tasks.
- */
-int main( void )
-{
-	/* Setup the ports. */
-	prvSetupHardware();
-
-	/* Setup the IO required for the LED's. */
-	vParTestInitialise();
-
-	/* Setup lwIP. */
-    vlwIPInit();
-
-	/* Create the lwIP task.  This uses the lwIP RTOS abstraction layer.*/
-    sys_thread_new( vBasicWEBServer, ( void * ) NULL, mainWEBSERVER_PRIORITY );
-
-	/* Create the demo USB CDC task. */
-	xTaskCreate( vUSBCDCTask, ( signed portCHAR * ) "USB", mainUSB_TASK_STACK, NULL, mainUSB_PRIORITY, NULL );
-
-	/* Create the standard demo application tasks. */
-	vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
-	vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
-	vStartLEDFlashTasks( mainFLASH_PRIORITY );
-	vStartIntegerMathTasks( tskIDLE_PRIORITY );
-	vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
-
-	/* Start the check task - which is defined in this file. */	
-    xTaskCreate( vErrorChecks, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
-
-	/* Finally, start the scheduler. 
-
-	NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.
-	The processor MUST be in supervisor mode when vTaskStartScheduler is 
-	called.  The demo applications included in the FreeRTOS.org download switch
-	to supervisor mode prior to main being called.  If you are not using one of
-	these demo application projects then ensure Supervisor mode is used here. */
-	vTaskStartScheduler();
-
-	/* Should never get here! */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-
-static void prvSetupHardware( void )
-{
-	/* When using the JTAG debugger the hardware is not always initialised to
-	the correct default state.  This line just ensures that this does not
-	cause all interrupts to be masked at the start. */
-	AT91C_BASE_AIC->AIC_EOICR = 0;
-	
-	/* Most setup is performed by the low level init function called from the
-	startup asm file.
-
-	Configure the PIO Lines corresponding to LED1 to LED4 to be outputs as
-	well as the UART Tx line. */
-	AT91C_BASE_PIOB->PIO_PER = LED_MASK; // Set in PIO mode
-	AT91C_BASE_PIOB->PIO_OER = LED_MASK; // Configure in Output
-
-
-	/* Enable the peripheral clock. */
-    AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOA;
-    AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOB;
-	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_EMAC;
-}
-/*-----------------------------------------------------------*/
-
-static void vErrorChecks( void *pvParameters )
-{
-portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD;
-portTickType xLastWakeTime;
-
-	/* The parameters are not used. */
-	( void ) pvParameters;
-
-	/* Initialise xLastWakeTime to ensure the first call to vTaskDelayUntil()
-	functions correctly. */
-	xLastWakeTime = xTaskGetTickCount();
-
-	/* Cycle for ever, delaying then checking all the other tasks are still
-	operating without error.  If an error is detected then the delay period
-	is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so
-	the Check LED flash rate will increase. */
-	for( ;; )
-	{
-		/* Delay until it is time to execute again.  The delay period is
-		shorter following an error. */
-		vTaskDelayUntil( &xLastWakeTime, xDelayPeriod );
-	
-		/* Check all the standard demo application tasks are executing without
-		error.  */
-		if( prvCheckOtherTasksAreStillRunning() != pdPASS )
-		{
-			/* An error has been detected in one of the tasks - flash faster. */
-			xDelayPeriod = mainERROR_FLASH_PERIOD;
-		}
-
-		vParTestToggleLED( mainCHECK_LED );
-	}
-}
-/*-----------------------------------------------------------*/
-
-static portLONG prvCheckOtherTasksAreStillRunning( void )
-{
-portLONG lReturn = ( portLONG ) pdPASS;
-
-	/* Check all the demo tasks (other than the flash tasks) to ensure
-	that they are all still running, and that none of them have detected
-	an error. */
-
-	if( xArePollingQueuesStillRunning() != pdTRUE )
-	{
-		lReturn = ( portLONG ) pdFAIL;
-	}
-
-	if( xAreSemaphoreTasksStillRunning() != pdTRUE )
-	{
-		lReturn = ( portLONG ) pdFAIL;
-	}
-
-	if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
-	{
-		lReturn = ( portLONG ) pdFAIL;
-	}
-
-	if( xAreBlockingQueuesStillRunning() != pdTRUE )
-	{
-		lReturn = ( portLONG ) pdFAIL;
-	}
-
-	return lReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vApplicationIdleHook( void )
-{
-static portTickType xLastTx = 0;
-portCHAR cTxByte;
-
-	/* The idle hook simply sends a string of characters to the USB port.
-	The characters will be buffered and sent once the port is connected. */
-	if( ( xTaskGetTickCount() - xLastTx ) > mainUSB_TX_FREQUENCY )
-	{
-		xLastTx = xTaskGetTickCount();
-		for( cTxByte = mainFIRST_TX_CHAR; cTxByte <= mainLAST_TX_CHAR; cTxByte++ )
-		{
-			vUSBSendByte( cTxByte );
-		}		
-	}
-}
-
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/makefile b/Demo/lwIP_Demo_Rowley_ARM7/makefile
deleted file mode 100644
index cdc1e68ee..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/makefile
+++ /dev/null
@@ -1,158 +0,0 @@
-#	FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
-#
-#	This file is part of the FreeRTOS.org distribution.
-#
-#	FreeRTOS.org is free software; you can redistribute it and/or modify
-#	it under the terms of the GNU General Public License as published by
-#	the Free Software Foundation; either version 2 of the License, or
-#	(at your option) any later version.
-#
-#	FreeRTOS.org is distributed in the hope that it will be useful,
-#	but WITHOUT ANY WARRANTY; without even the implied warranty of
-#	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-#	GNU General Public License for more details.
-#
-#	You should have received a copy of the GNU General Public License
-#	along with FreeRTOS.org; if not, write to the Free Software
-#	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-#
-#	A special exception to the GPL can be applied should you wish to distribute
-#	a combined work that includes FreeRTOS.org, without being obliged to provide
-#	the source code for any proprietary components.  See the licensing section 
-#	of http://www.FreeRTOS.org for full details of how and when the exception
-#	can be applied.
-#
-#	***************************************************************************
-#	See http://www.FreeRTOS.org for documentation, latest information, license 
-#	and contact details.  Please ensure to read the configuration and relevant 
-#	port sections of the online documentation.
-#	***************************************************************************
-
-CC=arm-elf-gcc
-OBJCOPY=arm-elf-objcopy
-ARCH=arm-elf-ar
-CRT0=boot.s
-DEBUG=-g
-OPTIM=-O0
-LDSCRIPT=atmel-rom.ld
-
-#
-# CFLAGS common to both the THUMB and ARM mode builds
-#
-
-CFLAGS= \
--I.  \
--I./EMAC  \
--I../Common/include  \
--I./USB  \
--I./lwip-1.1.0/src/include  \
--I./lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X  \
--I../../Source/include  \
--I../../Source/portable/GCC/ARM7_AT91SAM7S  \
--I./lwip-1.1.0/src/include/ipv4 \
--Wall  \
--Wextra  \
--Wstrict-prototypes  \
--Wmissing-prototypes  \
--Wmissing-declarations  \
--Wno-strict-aliasing  \
--D SAM7_GCC  \
--D THUMB_INTERWORK \
--mthumb-interwork \
--mcpu=arm7tdmi  \
--T$(LDSCRIPT) \
-$(DEBUG)  \
-$(OPTIM)
-
-THUMB_FLAGS=-mthumb
-LINKER_FLAGS=-Xlinker -ortosdemo.elf -Xlinker -M -Xlinker -Map=rtosdemo.map
-
-#
-# Source files that can be built to THUMB mode.
-#
-FREERTOS_THUMB_SRC= \
-  ../../Source/tasks.c \
-  ../../Source/queue.c \
-  ../../Source/list.c \
-  ../../Source/portable/GCC/ARM7_AT91SAM7S/port.c
-
-DEMO_APP_THMUB_SRC= \
-  ../../Source/portable/MemMang/heap_2.c \
-  ParTest/ParTest.c \
-  main.c \
-  ../Common/Minimal/flash.c \
-  ../Common/Minimal/BlockQ.c \
-  ../Common/Minimal/integer.c \
-  ../Common/Minimal/PollQ.c \
-  ../Common/Minimal/semtest.c \
-  BasicWEB.c \
-  USB/USB-CDC.c 
-
-LWIP_THUMB_SRC= \
-  lwip-1.1.0/src/core/tcp_out.c \
-  lwip-1.1.0/src/core/inet.c \
-  lwip-1.1.0/src/core/mem.c \
-  lwip-1.1.0/src/core/memp.c \
-  lwip-1.1.0/src/core/netif.c \
-  lwip-1.1.0/src/core/pbuf.c \
-  lwip-1.1.0/src/core/raw.c \
-  lwip-1.1.0/src/core/stats.c \
-  lwip-1.1.0/src/core/sys.c \
-  lwip-1.1.0/src/core/tcp.c \
-  lwip-1.1.0/src/core/tcp_in.c \
-  lwip-1.1.0/src/core/ipv4/ip.c \
-  lwip-1.1.0/src/core/ipv4/ip_addr.c \
-  lwip-1.1.0/src/core/ipv4/icmp.c \
-  lwip-1.1.0/src/api/tcpip.c \
-  lwip-1.1.0/src/api/api_msg.c \
-  lwip-1.1.0/src/api/err.c \
-  lwip-1.1.0/src/api/api_lib.c \
-  lwip-1.1.0/src/netif/etharp.c \
-  lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X/sys_arch.c \
-  lwip-1.1.0/src/netif/ethernetif.c \
-  EMAC/SAM7_EMAC.c \
-  lwip-1.1.0/src/core/udp.c \
-  lwip-1.1.0/src/core/ipv4/ip_frag.c
-
-#
-# Source files that must be built to ARM mode.
-#
-ARM_SRC= \
-  ../../Source/portable/GCC/ARM7_AT91SAM7S/portISR.c \
-  EMAC/SAM7_EMAC_ISR.c \
-  USB/USBIsr.c \
-  Cstartup_SAM7.c  
-
-
-#
-# Define all object files.
-#
-ARM_OBJ = $(ARM_SRC:.c=.o)
-FREERTOS_THUMB_OBJ = $(FREERTOS_THUMB_SRC:.c=.o)
-DEMO_APP_THMUB_OBJ = $(DEMO_APP_THMUB_SRC:.c=.o)
-LWIP_THUMB_OBJ = $(LWIP_THUMB_SRC:.c=.o)
-
-rtosdemo.bin : rtosdemo.elf
-	$(OBJCOPY) rtosdemo.elf -O binary rtosdemo.bin
-
-rtosdemo.hex : rtosdemo.elf
-	$(OBJCOPY) rtosdemo.elf -O ihex rtosdemo.hex
-
-rtosdemo.elf : $(ARM_OBJ) $(DEMO_APP_THMUB_OBJ) $(LWIP_THUMB_OBJ) $(FREERTOS_THUMB_OBJ) $(CRT0) Makefile FreeRTOSConfig.h
-	$(CC) $(CFLAGS) $(ARM_OBJ) $(DEMO_APP_THMUB_OBJ) $(LWIP_THUMB_OBJ) $(FREERTOS_THUMB_OBJ) -nostartfiles $(CRT0) $(LINKER_FLAGS)
-
-$(DEMO_APP_THMUB_OBJ)  : %.o : %.c $(LDSCRIPT) Makefile FreeRTOSConfig.h
-	$(CC) -c $(THUMB_FLAGS) $(CFLAGS) $< -o $@
-
-$(LWIP_THUMB_OBJ)  : %.o : %.c $(LDSCRIPT) Makefile FreeRTOSConfig.h
-	$(CC) -c $(THUMB_FLAGS) $(CFLAGS) $< -o $@
-
-$(FREERTOS_THUMB_OBJ)  : %.o : %.c $(LDSCRIPT) Makefile FreeRTOSConfig.h
-	$(CC) -c $(THUMB_FLAGS) $(CFLAGS) $< -o $@
-
-$(ARM_OBJ) : %.o : %.c $(LDSCRIPT) Makefile FreeRTOSConfig.h
-	$(CC) -c $(CFLAGS) $< -o $@
-
-clean :
-	touch Makefile
-
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/rtosdemo.hzp b/Demo/lwIP_Demo_Rowley_ARM7/rtosdemo.hzp
deleted file mode 100644
index 0c26e03ef..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/rtosdemo.hzp
+++ /dev/null
@@ -1,86 +0,0 @@
-
-
-  
-    
-    
-    
-    
-      
-      
-        
-        
-        
-        
-          
-        
-        
-      
-      
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
-          
-          
-        
-        
-      
-      
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
-        
-          
-        
-        
-        
-      
-    
-    
-      
-      
-      
-        
-      
-      
-      
-        
-      
-      
-    
-    
-    
-  
-  
-  
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/rtosdemo.hzs b/Demo/lwIP_Demo_Rowley_ARM7/rtosdemo.hzs
deleted file mode 100644
index c6f7b80c2..000000000
--- a/Demo/lwIP_Demo_Rowley_ARM7/rtosdemo.hzs
+++ /dev/null
@@ -1,77 +0,0 @@
-
-
- 
-  
- 
- 
- 
-  
-  
-  
-  
-  
-  
-  
-  
-  
-  
-  
-  
-  
-  
-  
- 
- 
- 
-  
- 
- 
-  
- 
- 
-  
- 
- 
-  
- 
- 
-  
-  
-  
- 
- 
-  
- 
- 
-  
- 
- 
-  
- 
- 
-  
- 
- 
- 
-  
- 
- 
-  
-   
-   
-   
-   
-  
- 
- 
-  
- 
- 
-  
- 
- 
-  
- 
- 
- 
-
diff --git a/Demo/lwIP_MCF5235_GCC/Changelog.txt b/Demo/lwIP_MCF5235_GCC/Changelog.txt
deleted file mode 100644
index 4aa9892f2..000000000
--- a/Demo/lwIP_MCF5235_GCC/Changelog.txt
+++ /dev/null
@@ -1,46 +0,0 @@
-
-2006-08-31 (REL_1_3) Christian Walter :
- Notes: Fixed some bugs in the lwIP porting layer. This includes a 
-   memory leak, wrong tasknames and an unnecessary lock of the
-   scheduler.
-
- Detailed notes:
-   - BUG: Sys_arch_thread_remove did not free the memory from
-       the TCB.
-   - BUG: Unnecessary call to vTaskSuspendAll removed.
-   - BUG: Bug with counting variable. The first to lwIP tasks
-       got the same name (lwIP0).
-
-2006-08-31 (REL_1_2) Christian Walter :
- Notes: Added HTML documentation used for FreeRTOS. Fixed copyright
-   issues.
-
-2006-08-30 (REL_1_2) Christian Walter :
- Notes: Fixed bug in serial transmission function vSerialPutString which
-   gives unintended behaviour. 
-
- Detailed notes:
-   - BUG: vSerialPutString should call xSerialPutChar with a small timeout
-       such that a retransmission is tried rather fast. The previous 
-       port uses portMAX_DELAY which blocked it to long. 
-
-2006-08-29 (REL_1_1) Christian Walter :
- Notes: Updated lwip to 1.1.1 and fixed bugs in FEC driver as well as in
-   the FreeRTOS porting layer (sys_arch.c)
-
- Detailed notes:
-   - BUG: Fixed thread creation in sys_thread_new which needs the scheduler
-       disabled because otherwise a task could ge started immediately by
-       portYIELD( ) leaving the lwIP thread datatstructures uninitialized.
-   - BUG: The FEC driver must guard the ARP layer with a semaphore because
-       it is not thread safe.
-   - BUG: Repaired sys_mbox_free to work around an lwIP bug with a non empty
-       mbox. An assertion is only triggered if a real memory leak is detected.
-   - BUG: Timeouts are now correctly converted to ticks within the sys_arch 
-       layer.
-   - FEATURES: General improvements in the sys_arch layer.
-       author in this project.
-
-2006-08-28 (REL_1_0) Christian Walter :
- Notes: Initial version of FreeRTOS/lwIP port for MCF5235.
-
diff --git a/Demo/lwIP_MCF5235_GCC/FreeRTOSConfig.h b/Demo/lwIP_MCF5235_GCC/FreeRTOSConfig.h
deleted file mode 100644
index 163535978..000000000
--- a/Demo/lwIP_MCF5235_GCC/FreeRTOSConfig.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
-    FreeRTOS V4.1.0 - Copyright (C) 2003-2006 Richard Barry.
-    MCF5235 Port - Copyright (C) 2006 Christian Walter.
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-
-    FreeRTOS is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with FreeRTOS; if not, write to the Free Software
-    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-
-    A special exception to the GPL can be applied should you wish to distribute
-    a combined work that includes FreeRTOS, without being obliged to provide
-    the source code for any proprietary components.  See the licensing section
-    of http://www.FreeRTOS.org for full details of how and when the exception
-    can be applied.
-
-    ***************************************************************************
-    See http://www.FreeRTOS.org for documentation, latest information, license
-    and contact details.  Please ensure to read the configuration and relevant
-    port sections of the online documentation.
-    ***************************************************************************
-*/
-
-#ifndef FREERTOS_CONFIG_H
-#define FREERTOS_CONFIG_H
-
-/*-----------------------------------------------------------
- * Application specific definitions.
- *
- * These definitions should be adjusted for your particular hardware and
- * application requirements.
- *
- * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
- * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
- *----------------------------------------------------------*/
-
-#define configUSE_PREEMPTION        1
-#define configUSE_IDLE_HOOK         0
-#define configUSE_TICK_HOOK         0
-#define configCPU_CLOCK_HZ          ( ( unsigned portLONG ) 25000000 )
-#define configTICK_RATE_HZ          ( ( portTickType ) 1000 )
-#define configMAX_PRIORITIES        ( ( unsigned portBASE_TYPE ) 5 )
-#define configMINIMAL_STACK_SIZE    ( ( unsigned portSHORT ) 128 )
-#define configMAX_TASK_NAME_LEN     ( 16 )
-#define configUSE_TRACE_FACILITY    1
-#define configUSE_16_BIT_TICKS      0
-#define configIDLE_SHOULD_YIELD     1
-
-/* Co-routine definitions. */
-#define configUSE_CO_ROUTINES       0 
-#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
-
-/* Set the following definitions to 1 to include the API function, or zero
-to exclude the API function. */
-
-#define INCLUDE_vTaskPrioritySet            1
-#define INCLUDE_uxTaskPriorityGet           1
-#define INCLUDE_vTaskDelete                 1
-#define INCLUDE_vTaskCleanUpResources       0
-#define INCLUDE_vTaskSuspend                1
-#define INCLUDE_vTaskDelayUntil             1
-#define INCLUDE_vTaskDelay                  1
-#define INCLUDE_xTaskGetCurrentTaskHandle   1
-
-#endif  /* FREERTOS_CONFIG_H */
diff --git a/Demo/lwIP_MCF5235_GCC/LICENSE_FREESCALE.TXT b/Demo/lwIP_MCF5235_GCC/LICENSE_FREESCALE.TXT
deleted file mode 100644
index 7e58b1174..000000000
--- a/Demo/lwIP_MCF5235_GCC/LICENSE_FREESCALE.TXT
+++ /dev/null
@@ -1,35 +0,0 @@
-MCF523x example code
-	
-IMPORTANT. Read the following Freescale Semiconductor Software License Agreement (“Agreement”) completely. By selecting the "I Accept" button at the end of this page, you indicate that you accept the terms of this Agreement. You may then download the file.
-
-FREESCALE SEMICONDUCTOR SOFTWARE LICENSE AGREEMENT
-
-This is a legal agreement between you (either as an individual or as an authorized representative of your employer) and Freescale Semiconductor, Inc. ("Freescale"). It concerns your rights to use this file and any accompanying written materials (the "Software"). In consideration for Freescale allowing you to access the Software, you are agreeing to be bound by the terms of this Agreement. If you do not agree to all of the terms of this Agreement, do not download the Software. If you change your mind later, stop using the Software and delete all copies of the Software in your possession or control. Any copies of the Software that you have already distributed, where permitted, and do not destroy will continue to be governed by this Agreement. Your prior use will also continue to be governed by this Agreement.
-
-LICENSE GRANT.  Freescale grants to you, free of charge, the non-exclusive, non-transferable right (1) to use the Software, (2) to reproduce the Software, (3) to prepare derivative works of the Software, (4) to distribute the Software and derivative works thereof in source (human-readable) form and object (machine–readable) form, and (5) to sublicense to others the right to use the distributed Software. If you violate any of the terms or restrictions of this Agreement, Freescale may immediately terminate this Agreement, and require that you stop using and delete all copies of the Software in your possession or control.
-
-COPYRIGHT.  The Software is licensed to you, not sold. Freescale owns the Software, and United States copyright laws and international treaty provisions protect the Software. Therefore, you must treat the Software like any other copyrighted material (e.g. a book or musical recording). You may not use or copy the Software for any other purpose than what is described in this Agreement. Except as expressly provided herein, Freescale does not grant to you any express or implied rights under any Freescale or third-party patents, copyrights, trademarks, or trade secrets. Additionally, you must reproduce and apply any copyright or other proprietary rights notices included on or embedded in the Software to any copies or derivative works made thereof, in whole or in part, if any.
-
-SUPPORT.  Freescale is NOT obligated to provide any support, upgrades or new releases of the Software. If you wish, you may contact Freescale and report problems and provide suggestions regarding the Software. Freescale has no obligation whatsoever to respond in any way to such a problem report or suggestion. Freescale may make changes to the Software at any time, without any obligation to notify or provide updated versions of the Software to you.
-
-NO WARRANTY.  TO THE MAXIMUM EXTENT PERMITTED BY LAW, FREESCALE EXPRESSLY DISCLAIMS ANY WARRANTY FOR THE SOFTWARE. THE SOFTWARE IS PROVIDED “AS IS”, WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. YOU ASSUME THE ENTIRE RISK ARISING OUT OF THE USE OR PERFORMANCE OF THE SOFTWARE, OR ANY SYSTEMS YOU DESIGN USING THE SOFTWARE (IF ANY). NOTHING IN THIS AGREEMENT MAY BE CONSTRUED AS A WARRANTY OR REPRESENTATION BY FREESCALE THAT THE SOFTWARE OR ANY DERIVATIVE WORK DEVELOPED WITH OR INCORPORATING THE SOFTWARE WILL BE FREE FROM INFRINGEMENT OF THE INTELLECTUAL PROPERTY RIGHTS OF THIRD PARTIES.
-
-INDEMNITY.  You agree to fully defend and indemnify Freescale from any and all claims, liabilities, and costs (including reasonable attorney’s fees) related to (1) your use (including your sublicensee’s use, if permitted) of the Software or (2) your violation of the terms and conditions of this Agreement.
-
-LIMITATION OF LIABILITY.  IN NO EVENT WILL FREESCALE BE LIABLE, WHETHER IN CONTRACT, TORT, OR OTHERWISE, FOR ANY INCIDENTAL, SPECIAL, INDIRECT, CONSEQUENTIAL OR PUNITIVE DAMAGES, INCLUDING, BUT NOT LIMITED TO, DAMAGES FOR ANY LOSS OF USE, LOSS OF TIME, INCONVENIENCE, COMMERCIAL LOSS, OR LOST PROFITS, SAVINGS, OR REVENUES TO THE FULL EXTENT SUCH MAY BE DISCLAIMED BY LAW.
-
-COMPLIANCE WITH LAWS; EXPORT RESTRICTIONS.  This software may be subject to the U.S. Export Regulations and/or the regulatory authority of the country in which the download takes place. By downloading this software you understand and agree to comply with all applicable export control regulations when further transferring or exporting the software either as downloaded or as integrated into other software or commodities.
-
-GOVERNMENT USE.  Use of the Software and any corresponding documentation, if any, is provided with RESTRICTED RIGHTS. Use, duplication or disclosure by the Government is subject to restrictions as set forth in subparagraph (c)(1)(ii) of The Rights in Technical Data and Computer Software clause at DFARS 252.227-7013 or subparagraphs (c)(l) and (2) of the Commercial Computer Software--Restricted Rights at 48 CFR 52.227-19, as applicable. Manufacturer is Freescale Semiconductor, Inc., 6501 William Cannon Drive West, Austin, TX, 78735.
-
-HIGH RISK ACTIVITIES.  You acknowledge that the Software is not fault tolerant and is not designed, manufactured or intended by Freescale for incorporation into products intended for use or resale in on-line control equipment in hazardous, dangerous to life or potentially life-threatening environments requiring fail-safe performance, such as in the operation of nuclear facilities, aircraft navigation or communication systems, air traffic control, direct life support machines or weapons systems, in which the failure of products could lead directly to death, personal injury or severe physical or environmental damage (“High Risk Activities”). You specifically represent and warrant that you will not use the Software or any derivative work of the Software for High Risk Activities.
-
-CHOICE OF LAW; VENUE; LIMITATIONS.  You agree that the statutes and laws of the United States and the State of Texas, USA, without regard to conflicts of laws principles, will apply to all matters relating to this Agreement or the Software, and you agree that any litigation will be subject to the exclusive jurisdiction of the state or federal courts in Texas, USA. You agree that regardless of any statute or law to the contrary, any claim or cause of action arising out of or related to this Agreement or the Software must be filed within one (1) year after such claim or cause of action arose or be forever barred.
-
-PRODUCT LABELING.  You are not authorized to use any Freescale trademarks, brand names, or logos.
-
-ENTIRE AGREEMENT.  This Agreement constitutes the entire agreement between you and Freescale regarding the subject matter of this Agreement, and supersedes all prior communications, negotiations, understandings, agreements or representations, either written or oral, if any. This Agreement may only be amended in written form, executed by you and Freescale.
-
-SEVERABILITY.  If any provision of this Agreement is held for any reason to be invalid or unenforceable, then the remaining provisions of this Agreement will be unimpaired and, unless a modification or replacement of the invalid or unenforceable provision is further held to deprive you or Freescale of a material benefit, in which case the Agreement will immediately terminate, the invalid or unenforceable provision will be replaced with a provision that is valid and enforceable and that comes closest to the intention underlying the invalid or unenforceable provision.
-
-NO WAIVER.  The waiver by Freescale of any breach of any provision of this Agreement will not operate or be construed as a waiver of any other or a subsequent breach of the same or a different provision.
diff --git a/Demo/lwIP_MCF5235_GCC/Makefile b/Demo/lwIP_MCF5235_GCC/Makefile
deleted file mode 100644
index a76e61176..000000000
--- a/Demo/lwIP_MCF5235_GCC/Makefile
+++ /dev/null
@@ -1,94 +0,0 @@
-#
-# FreeRTOS 4.1.0 - MCF5235 Coldfire Port
-#
-# Copyright (c) 2006 Christian Walter, Vienna 2006.
-#
-# $Id: Makefile,v 1.4 2006/09/06 19:55:07 wolti Exp $
-#
-# ---------------------------------------------------------------------------
-BASE        = /opt/gcc-m68k/bin
-CC	        = $(BASE)/m68k-elf-gcc
-CXX	        = $(BASE)/m68k-elf-g++
-OBJCOPY	    = $(BASE)/m68k-elf-objcopy
-SIZE	    = $(BASE)/m68k-elf-size
-INSIGHT     = $(BASE)/m68k-bdm-elf-insight
-BDMFLASH    = $(BASE)/bdmflash
-
-#CFLAGS	    = -MD -gdwarf-2 -g3 -m528x -Wall 
-CFLAGS	    = -MD -O2 -m528x -Wall \
-			  -D'GCC_MCF5235=1' -D'_GCC_USES_FP=1' \
-			  -D'__IPSBAR=((vuint8 *) 0x40000000)' -D'FSYS_2=25000000UL' \
-			  -I. -Iinclude -Iinclude/arch -Ifec \
-			  -I../../Source/include -I../Common/include \
-              -Ilwip/src/include -Ilwip/src/include/ipv4 \
-              -Ilwip/contrib/port/FreeRTOS/MCF5235 \
-              -Ilwip/contrib/port/FreeRTOS/MCF5235/netif
-
-ASFLAGS     = -MD -gdwarf-2 -g3 -m528x -Wa,--register-prefix-optional \
-              -Wa,--bitwise-or -Wa,--defsym,IPSBAR=0x40000000
-LDSCRIPT    = m5235-ram.ld
-LDFLAGS	    = -nostartfiles -m528x -Wl,--script=$(LDSCRIPT)
-
-TGT         = demo
-OTHER_CSRC  = 
-OTHER_ASRC  = $(addprefix system/, crt0.S vector.S)
-CSRC        = demo.c web.c \
-              $(addprefix system/, init.c newlib.c serial.c) \
-              $(addprefix ../Common/Minimal/, PollQ.c integer.c flop.c BlockQ.c semtest.c dynamic.c ) \
-			  $(addprefix ../../Source/, tasks.c queue.c list.c) \
-			  $(addprefix ../../Source/portable/MemMang/, heap_3.c) \
-			  $(addprefix ../../Source/portable/GCC/MCF5235/, port.c) \
-              $(addprefix lwip/src/core/, tcp_out.c inet.c mem.c memp.c netif.c pbuf.c raw.c stats.c sys.c tcp.c tcp_in.c udp.c ipv4/ip.c ipv4/ip_addr.c ipv4/icmp.c ipv4/ip_frag.c) \
-              $(addprefix lwip/src/api/, tcpip.c api_msg.c err.c api_lib.c ) \
-              $(addprefix lwip/src/netif/, etharp.c ) \
-              $(addprefix lwip/contrib/port/FreeRTOS/MCF5235/, sys_arch.c netif/fec.c netif/nbuf.c) 
-
-ASRC        = $(addprefix system/, mcf5xxx.S ) 
-OBJS        = $(CSRC:.c=.o) $(ASRC:.S=.o)
-NOLINK_OBJS = $(OTHER_CSRC:.c=.o) $(OTHER_ASRC:.S=.o)
-DEPS        = $(OBJS:.o=.d) $(NOLINK_OBJS:.o=.d)
-BIN         = $(TGT).elf
-
-.PHONY: clean all
-
-all: $(BIN)
-
-flash-programm: $(TGT).elf
-	$(OBJCOPY) -O binary $(TGT).elf $(TGT).bin
-	@BIN_SIZE=`du -b $(TGT).bin | awk '//{ print $$1; }'`; \
-	echo "programming $(TGT).bin with size $$BIN_SIZE to flash..."; \
-	$(BDMFLASH) /dev/bdmcf20 0x00000000 1 2 write $(TGT).bin 0
-
-flash-verify:
-	@BIN_SIZE=`du -b $(TGT).bin | awk '//{ print $$1; }'`; \
-	echo "loading $$BIN_SIZE bytes from target into $(TGT).vrf..."; \
-	$(BDMFLASH) /dev/bdmcf20 0x00000000 1 2 read $(TGT).vrf 0 $$BIN_SIZE
-
-flash-erase:
-	$(BDMFLASH) /dev/bdmcf20 0x00000000 1 2 erase
-
-debug:
-	$(INSIGHT) --command=m5235.gdb --se=$(TGT).elf
-
-$(BIN): $(OBJS) $(NOLINK_OBJS)
-	$(CC) $(LDFLAGS) -Wl,-Map=$(TGT).map $(OBJS) $(LDLIBS) -o $@
-
-clean:
-	rm -f $(DEPS)
-	rm -f $(OBJS) $(NOLINK_OBJS)
-	rm -f $(BIN) $(TGT).map
-
-# ---------------------------------------------------------------------------
-# rules for code generation
-# ---------------------------------------------------------------------------
-%.o:    %.c
-	$(CC) $(CFLAGS) -o $@ -c $<
-
-%.o:    %.S
-	$(CC) $(ASFLAGS) -o $@ -c $<
-
-# ---------------------------------------------------------------------------
-#  # compiler generated dependencies
-# ---------------------------------------------------------------------------
--include $(DEPS)
-
diff --git a/Demo/lwIP_MCF5235_GCC/README.txt b/Demo/lwIP_MCF5235_GCC/README.txt
deleted file mode 100644
index eedebc902..000000000
--- a/Demo/lwIP_MCF5235_GCC/README.txt
+++ /dev/null
@@ -1,56 +0,0 @@
-
-                FREERTOS COLDFIRE MCF523x PORT with lwIP
-
-REQUIREMENTS
-============
-
-The FreeRTOS port is designed for the MCF523x processor where the hardware
-dependent part consists of the CPU and the peripherals used in this  port.
-This includes a programmable timer  (PIT)  for  the  preemptive  scheduler
-and a UART for the demo application.  The Coldfire specific part  includes
-the number and type of processor registers, the  stack  frame  layout  and
-the usage of a software interrupt (trap) for the yield call.
-
-The development environment used is  based  on  the  GNU  C  Compiler  for
-a m68k-elf target as well as the insight debugger with  some  patches  for
-the BDM interface[1].  GDB startup and linker scripts  are  supplied  with
-the demo for the M5235BCC evaluation kit from Freescale.
-
- [1] ... BDM tools: http://sourceforge.net/projects/bdm/
-
-USAGE
-=====
-
-A makefile is supplied with the demo  application  and  a  binary  can  be
-produced by calling 'make all'.  A  special  target  'debug'  is  provided
-which executes the insight  debugger.   At  the  insight  debugger  prompt
-one should select the  appropriate  target  interface  (either  BDM/Direct
-or BDM/TCP)  and  should  download  the  application  to  the  development
-board.  It is important that the GDB  script  setup-and-load  is  executed
-prior to downloading to  initialize  the  SDRAM.   After  downloading  one
-should call the GDB function 'execute' and the PC  is  set  to  the  start
-of the executable.  Execution can  be  started  by  typing  'continue'  at
-the Insight console interface.
-After this  startup phase the  insight debugger should work as usual, i.e.
-no grayed out buttons, ...
-
-
-COMMON PROBLEMS
-===============
- 
-Most of the problems have  their  origin  in  the  startup  scripts.   The
-following list should serve as  a  checklist  where  each  point  must  be
-satisfied for the port to work.
-
- - The FreeRTOS port only works correctly in the supervisor mode.   There-
-   fore the Coldfire CPU must run in the supervisor mode.
-
- - portVECTOR_TABLE does not point to the currently active  vector  table.
-   Please also note that the vector table must be in  RAM  such  that  the
-   FreeRTOS port can install a traphandler for the portYIELD() call.
-
-
-$Id: README.txt,v 1.1 2006/08/29 02:24:03 wolti Exp $
-
-MCF5235 + lwIP port - Copyright (c) 2006 Christian Walter.
-
diff --git a/Demo/lwIP_MCF5235_GCC/demo.c b/Demo/lwIP_MCF5235_GCC/demo.c
deleted file mode 100644
index c5e0a7ca4..000000000
--- a/Demo/lwIP_MCF5235_GCC/demo.c
+++ /dev/null
@@ -1,287 +0,0 @@
-/*
-    FreeRTOS V4.1.0 - copyright (C) 2003-2006 Richard Barry.
-    MCF5235 Port - Copyright (C) 2006 Christian Walter.
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-
-    FreeRTOS is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with FreeRTOS; if not, write to the Free Software
-    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-
-    A special exception to the GPL can be applied should you wish to distribute
-    a combined work that includes FreeRTOS, without being obliged to provide
-    the source code for any proprietary components.  See the licensing section
-    of http://www.FreeRTOS.org for full details of how and when the exception
-    can be applied.
-
-    ***************************************************************************
-    See http://www.FreeRTOS.org for documentation, latest information, license
-    and contact details.  Please ensure to read the configuration and relevant
-    port sections of the online documentation.
-    ***************************************************************************
-*/
-
-/* ------------------------ System includes ------------------------------- */
-#include 
-#include 
-#include 
-#include 
-
-/* ------------------------ FreeRTOS includes ----------------------------- */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* ------------------------ LWIP includes --------------------------------- */
-#include "lwip/api.h"
-#include "lwip/tcpip.h"
-#include "lwip/memp.h"
-
-/* ------------------------ Project includes ------------------------------ */
-#include "mcf5xxx.h"
-#include "mcf523x.h"
-#include "serial.h"
-
-#include "web.h"
-#include "integer.h"
-#include "PollQ.h"
-#include "semtest.h"
-#include "BlockQ.h"
-#include "dynamic.h"
-#include "flop.h"
-
-/* ------------------------ Defines --------------------------------------- */
-#define mainCOM_TEST_BAUD_RATE      ( ( unsigned portLONG ) 38400 )
-
-/* Priorities for the demo application tasks. */
-#define mainLED_TASK_PRIORITY       ( tskIDLE_PRIORITY + 3 )
-#define mainCOM_TEST_PRIORITY       ( tskIDLE_PRIORITY + 2 )
-#define mainQUEUE_POLL_PRIORITY     ( tskIDLE_PRIORITY + 2 )
-#define mainCHECK_TASK_PRIORITY     ( tskIDLE_PRIORITY + 4 )
-#define mainSEM_TEST_PRIORITY       ( tskIDLE_PRIORITY + 1 )
-#define mainBLOCK_Q_PRIORITY        ( tskIDLE_PRIORITY + 2 )
-#define mainWEB_TASK_PRIORITY       ( tskIDLE_PRIORITY + 3 )
-#define STACK_DEFAULT               ( 1024 )
-
-/* Interval in which tasks are checked. */
-#define mainCHECK_PERIOD            ( ( portTickType ) 2000 / portTICK_RATE_MS  )
-
-/* Constants used by the vMemCheckTask() task. */
-#define mainCOUNT_INITIAL_VALUE     ( ( unsigned portLONG ) 0 )
-#define mainNO_TASK                 ( 0 )
-
-/* The size of the memory blocks allocated by the vMemCheckTask() task. */
-#define mainMEM_CHECK_SIZE_1        ( ( size_t ) 51 )
-#define mainMEM_CHECK_SIZE_2        ( ( size_t ) 52 )
-#define mainMEM_CHECK_SIZE_3        ( ( size_t ) 151 )
-
-/* ------------------------ Static variables ------------------------------ */
-xComPortHandle  xSTDComPort = NULL;
-
-/* ------------------------ Static functions ------------------------------ */
-static          portTASK_FUNCTION( vErrorChecks, pvParameters );
-static portLONG prvCheckOtherTasksAreStillRunning( unsigned portLONG
-                                                   ulMemCheckTaskCount );
-static          portTASK_FUNCTION( vMemCheckTask, pvParameters );
-
-/* ------------------------ Implementation -------------------------------- */
-int
-main( int argc, char *argv[] )
-{
-    asm volatile    ( "move.w  #0x2000, %sr\n\t" );
-
-    xSTDComPort = xSerialPortInitMinimal( 38400, 8 );
-    vlwIPInit(  );
-
-    /* Start the demo/test application tasks. */
-    vStartIntegerMathTasks( tskIDLE_PRIORITY );
-    vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
-    //vStartMathTasks( tskIDLE_PRIORITY );
-    vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
-    vStartDynamicPriorityTasks(  );
-    vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
-
-    /* Start the webserver. */
-    ( void )sys_thread_new( vBasicWEBServer, NULL, mainWEB_TASK_PRIORITY );
-
-    /* Start the check task - which is defined in this file. */
-    xTaskCreate( vErrorChecks, ( signed portCHAR * )"Check", 512, NULL,
-                 mainCHECK_TASK_PRIORITY, NULL );
-        /* Now all the tasks have been started - start the scheduler. */
-    vTaskStartScheduler(  );
-
-    /* Should never get here! */
-    return 0;
-}
-
-static
-portTASK_FUNCTION( vErrorChecks, pvParameters )
-{
-    unsigned portLONG ulMemCheckTaskRunningCount;
-    xTaskHandle     xCreatedTask;
-
-    /* The parameters are not used in this function. */
-    ( void )pvParameters;
-
-    for( ;; )
-    {
-        ulMemCheckTaskRunningCount = mainCOUNT_INITIAL_VALUE;
-        xCreatedTask = mainNO_TASK;
-        if( xTaskCreate( vMemCheckTask, ( signed portCHAR * )"MEM",
-                         configMINIMAL_STACK_SIZE, ( void * )&ulMemCheckTaskRunningCount,
-                         tskIDLE_PRIORITY, &xCreatedTask ) != pdPASS )
-        {
-            xSerialPutChar( xSTDComPort, 'E', portMAX_DELAY );
-        }
-        /* Delay until it is time to execute again. */
-        vTaskDelay( mainCHECK_PERIOD );
-
-        /* Delete the dynamically created task. */
-        if( xCreatedTask != mainNO_TASK )
-        {
-            vTaskDelete( xCreatedTask );
-        }
-
-        if( prvCheckOtherTasksAreStillRunning( ulMemCheckTaskRunningCount ) != pdPASS )
-        {
-            xSerialPutChar( xSTDComPort, 'E', portMAX_DELAY );
-        }
-        else
-        {
-            xSerialPutChar( xSTDComPort, '.', portMAX_DELAY );
-        }
-    }
-}
-
-static portLONG
-prvCheckOtherTasksAreStillRunning( unsigned portLONG ulMemCheckTaskCount )
-{
-    portLONG        lReturn = ( portLONG ) pdPASS;
-
-    /* Check all the demo tasks (other than the flash tasks) to ensure
-     * that they are all still running, and that none of them have detected
-     * an error.
-     */
-    if( xAreIntegerMathsTaskStillRunning(  ) != pdTRUE )
-    {
-        lReturn = ( portLONG ) pdFAIL;
-    }
-
-    if( xArePollingQueuesStillRunning(  ) != pdTRUE )
-    {
-        lReturn = ( portLONG ) pdFAIL;
-    }
-
-    if( xAreSemaphoreTasksStillRunning(  ) != pdTRUE )
-    {
-        lReturn = ( portLONG ) pdFAIL;
-    }
-
-    if( xAreDynamicPriorityTasksStillRunning(  ) != pdTRUE )
-    {
-        lReturn = ( portLONG ) pdFAIL;
-    }
-
-    if( xAreBlockingQueuesStillRunning(  ) != pdTRUE )
-    {
-        lReturn = ( portLONG ) pdFAIL;
-    }
-
-    if( ulMemCheckTaskCount == mainCOUNT_INITIAL_VALUE )
-    {
-        /* The vMemCheckTask did not increment the counter - it must
-         * have failed.
-         */
-        lReturn = ( portLONG ) pdFAIL;
-    }
-    return lReturn;
-}
-
-static void
-vMemCheckTask( void *pvParameters )
-{
-    unsigned portLONG *pulMemCheckTaskRunningCounter;
-    void           *pvMem1, *pvMem2, *pvMem3;
-    static portLONG lErrorOccurred = pdFALSE;
-
-    /* This task is dynamically created then deleted during each cycle of the
-       vErrorChecks task to check the operation of the memory allocator.  Each time
-       the task is created memory is allocated for the stack and TCB.  Each time
-       the task is deleted this memory is returned to the heap.  This task itself
-       exercises the allocator by allocating and freeing blocks.
-
-       The task executes at the idle priority so does not require a delay.
-
-       pulMemCheckTaskRunningCounter is incremented each cycle to indicate to the
-       vErrorChecks() task that this task is still executing without error. */
-
-    pulMemCheckTaskRunningCounter = ( unsigned portLONG * )pvParameters;
-
-    for( ;; )
-    {
-        if( lErrorOccurred == pdFALSE )
-        {
-            /* We have never seen an error so increment the counter. */
-            ( *pulMemCheckTaskRunningCounter )++;
-        }
-
-        /* Allocate some memory - just to give the allocator some extra
-           exercise.  This has to be in a critical section to ensure the
-           task does not get deleted while it has memory allocated. */
-        vTaskSuspendAll(  );
-        {
-            pvMem1 = pvPortMalloc( mainMEM_CHECK_SIZE_1 );
-            if( pvMem1 == NULL )
-            {
-                lErrorOccurred = pdTRUE;
-            }
-            else
-            {
-                memset( pvMem1, 0xaa, mainMEM_CHECK_SIZE_1 );
-                vPortFree( pvMem1 );
-            }
-        }
-        xTaskResumeAll(  );
-
-        /* Again - with a different size block. */
-        vTaskSuspendAll(  );
-        {
-            pvMem2 = pvPortMalloc( mainMEM_CHECK_SIZE_2 );
-            if( pvMem2 == NULL )
-            {
-                lErrorOccurred = pdTRUE;
-            }
-            else
-            {
-                memset( pvMem2, 0xaa, mainMEM_CHECK_SIZE_2 );
-                vPortFree( pvMem2 );
-            }
-        }
-        xTaskResumeAll(  );
-
-        /* Again - with a different size block. */
-        vTaskSuspendAll(  );
-        {
-            pvMem3 = pvPortMalloc( mainMEM_CHECK_SIZE_3 );
-            if( pvMem3 == NULL )
-            {
-                lErrorOccurred = pdTRUE;
-            }
-            else
-            {
-                memset( pvMem3, 0xaa, mainMEM_CHECK_SIZE_3 );
-                vPortFree( pvMem3 );
-            }
-        }
-        xTaskResumeAll(  );
-    }
-}
diff --git a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x.h b/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x.h
deleted file mode 100644
index 4b7761fd5..000000000
--- a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly 
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file 
- * LICENSE_FREESCALE.TXT.
- *
- * File:	mcf523x.h
- * Purpose:	Register and bit definitions for the MCF523X
- *
- * Notes:	
- *	
- */
-
-#ifndef __MCF523X_H__
-#define __MCF523X_H__
-
-/*********************************************************************/
-
-#include "mcf523x/mcf523x_fec.h"
-#include "mcf523x/mcf523x_rng.h"
-#include "mcf523x/mcf523x_fmpll.h"
-#include "mcf523x/mcf523x_cs.h"
-#include "mcf523x/mcf523x_intc0.h"
-#include "mcf523x/mcf523x_intc1.h"
-#include "mcf523x/mcf523x_sdramc.h"
-#include "mcf523x/mcf523x_sram.h"
-#include "mcf523x/mcf523x_uart.h"
-#include "mcf523x/mcf523x_timer.h"
-#include "mcf523x/mcf523x_qspi.h"
-#include "mcf523x/mcf523x_eport.h"
-#include "mcf523x/mcf523x_i2c.h"
-#include "mcf523x/mcf523x_scm.h"
-#include "mcf523x/mcf523x_pit.h"
-#include "mcf523x/mcf523x_can.h"
-#include "mcf523x/mcf523x_wtm.h"
-#include "mcf523x/mcf523x_gpio.h"
-#include "mcf523x/mcf523x_mdha.h"
-#include "mcf523x/mcf523x_ccm.h"
-#include "mcf523x/mcf523x_rcm.h"
-#include "mcf523x/mcf523x_etpu.h"
-
-
-/********************************************************************/
-
-#endif /* __MCF523X_H__ */
diff --git a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_can.h b/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_can.h
deleted file mode 100644
index 7aaa34496..000000000
--- a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_can.h
+++ /dev/null
@@ -1,325 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly 
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file 
- * LICENSE_FREESCALE.TXT.
- *
- * File:	mcf523x_can.h
- * Purpose:	Register and bit definitions for the MCF523X
- *
- * Notes:	
- *	
- */
-
-#ifndef __MCF523X_CAN_H__
-#define __MCF523X_CAN_H__
-
-/*********************************************************************
-*
-* FlexCAN Module (CAN)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_CAN_CANMCR0        (*(vuint32*)(void*)(&__IPSBAR[0x1C0000]))
-#define MCF_CAN_CANCTRL0       (*(vuint32*)(void*)(&__IPSBAR[0x1C0004]))
-#define MCF_CAN_TIMER0         (*(vuint32*)(void*)(&__IPSBAR[0x1C0008]))
-#define MCF_CAN_RXGMASK0       (*(vuint32*)(void*)(&__IPSBAR[0x1C0010]))
-#define MCF_CAN_RX14MASK0      (*(vuint32*)(void*)(&__IPSBAR[0x1C0014]))
-#define MCF_CAN_RX15MASK0      (*(vuint32*)(void*)(&__IPSBAR[0x1C0018]))
-#define MCF_CAN_ERRCNT0        (*(vuint32*)(void*)(&__IPSBAR[0x1C001C]))
-#define MCF_CAN_ERRSTAT0       (*(vuint32*)(void*)(&__IPSBAR[0x1C0020]))
-#define MCF_CAN_IMASK0         (*(vuint16*)(void*)(&__IPSBAR[0x1C002A]))
-#define MCF_CAN_IFLAG0         (*(vuint16*)(void*)(&__IPSBAR[0x1C0032]))
-#define MCF_CAN_CANMCR1        (*(vuint32*)(void*)(&__IPSBAR[0x1F0000]))
-#define MCF_CAN_CANCTRL1       (*(vuint32*)(void*)(&__IPSBAR[0x1F0004]))
-#define MCF_CAN_TIMER1         (*(vuint32*)(void*)(&__IPSBAR[0x1F0008]))
-#define MCF_CAN_RXGMASK1       (*(vuint32*)(void*)(&__IPSBAR[0x1F0010]))
-#define MCF_CAN_RX14MASK1      (*(vuint32*)(void*)(&__IPSBAR[0x1F0014]))
-#define MCF_CAN_RX15MASK1      (*(vuint32*)(void*)(&__IPSBAR[0x1F0018]))
-#define MCF_CAN_ERRCNT1        (*(vuint32*)(void*)(&__IPSBAR[0x1F001C]))
-#define MCF_CAN_ERRSTAT1       (*(vuint32*)(void*)(&__IPSBAR[0x1F0020]))
-#define MCF_CAN_IMASK1         (*(vuint16*)(void*)(&__IPSBAR[0x1F002A]))
-#define MCF_CAN_IFLAG1         (*(vuint16*)(void*)(&__IPSBAR[0x1F0032]))
-#define MCF_CAN_CANMCR(x)      (*(vuint32*)(void*)(&__IPSBAR[0x1C0000+((x)*0x30000)]))
-#define MCF_CAN_CANCTRL(x)     (*(vuint32*)(void*)(&__IPSBAR[0x1C0004+((x)*0x30000)]))
-#define MCF_CAN_TIMER(x)       (*(vuint32*)(void*)(&__IPSBAR[0x1C0008+((x)*0x30000)]))
-#define MCF_CAN_RXGMASK(x)     (*(vuint32*)(void*)(&__IPSBAR[0x1C0010+((x)*0x30000)]))
-#define MCF_CAN_RX14MASK(x)    (*(vuint32*)(void*)(&__IPSBAR[0x1C0014+((x)*0x30000)]))
-#define MCF_CAN_RX15MASK(x)    (*(vuint32*)(void*)(&__IPSBAR[0x1C0018+((x)*0x30000)]))
-#define MCF_CAN_ERRCNT(x)      (*(vuint32*)(void*)(&__IPSBAR[0x1C001C+((x)*0x30000)]))
-#define MCF_CAN_ERRSTAT(x)     (*(vuint32*)(void*)(&__IPSBAR[0x1C0020+((x)*0x30000)]))
-#define MCF_CAN_IMASK(x)       (*(vuint16*)(void*)(&__IPSBAR[0x1C002A+((x)*0x30000)]))
-#define MCF_CAN_IFLAG(x)       (*(vuint16*)(void*)(&__IPSBAR[0x1C0032+((x)*0x30000)]))
-
-#define MCF_CAN_MBUF0_CTRL(x)		(*(vuint16 *)(void *)(&__IPSBAR[0x1C0080+((x)*0x30000)]))
-#define MCF_CAN_MBUF0_TMSTP(x)		(*(vuint16 *)(void *)(&__IPSBAR[0x1C0082+((x)*0x30000)]))
-#define MCF_CAN_MBUF0_ID(x) 	    (*(vuint32 *)(void *)(&__IPSBAR[0x1C0084+((x)*0x30000)]))
-#define MCF_CAN_MBUF0_BYTE0(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C0088+((x)*0x30000)]))
-#define MCF_CAN_MBUF0_BYTE1(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C0089+((x)*0x30000)]))
-#define MCF_CAN_MBUF0_BYTE2(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C008A+((x)*0x30000)]))
-#define MCF_CAN_MBUF0_BYTE3(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C008B+((x)*0x30000)]))
-#define MCF_CAN_MBUF0_BYTE4(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C008C+((x)*0x30000)]))
-#define MCF_CAN_MBUF0_BYTE5(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C008D+((x)*0x30000)]))
-#define MCF_CAN_MBUF0_BYTE6(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C008E+((x)*0x30000)]))
-#define MCF_CAN_MBUF0_BYTE7(x)      (*(vuint8  *)(void *)(&__IPSBAR[0x1C008F+((x)*0x30000)]))
-#define MCF_CAN_MBUF1_CTRL(x)		(*(vuint16 *)(void *)(&__IPSBAR[0x1C0090+((x)*0x30000)]))
-#define MCF_CAN_MBUF1_TMSTP(x)		(*(vuint16 *)(void *)(&__IPSBAR[0x1C0092+((x)*0x30000)]))
-#define MCF_CAN_MBUF1_ID(x)			(*(vuint32 *)(void *)(&__IPSBAR[0x1C0094+((x)*0x30000)]))
-#define MCF_CAN_MBUF1_BYTE0(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C0098+((x)*0x30000)]))
-#define MCF_CAN_MBUF1_BYTE1(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C0099+((x)*0x30000)]))
-#define MCF_CAN_MBUF1_BYTE2(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C009A+((x)*0x30000)]))
-#define MCF_CAN_MBUF1_BYTE3(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C009B+((x)*0x30000)]))
-#define MCF_CAN_MBUF1_BYTE4(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C009C+((x)*0x30000)]))
-#define MCF_CAN_MBUF1_BYTE5(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C009D+((x)*0x30000)]))
-#define MCF_CAN_MBUF1_BYTE6(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C009E+((x)*0x30000)]))
-#define MCF_CAN_MBUF1_BYTE7(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C009F+((x)*0x30000)]))
-#define MCF_CAN_MBUF2_CTRL(x)		(*(vuint16 *)(void *)(&__IPSBAR[0x1C00A0+((x)*0x30000)]))
-#define MCF_CAN_MBUF2_ID(x) 	    (*(vuint32 *)(void *)(&__IPSBAR[0x1C00A4+((x)*0x30000)]))
-#define MCF_CAN_MBUF2_BYTE0(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C00A8+((x)*0x30000)]))
-#define MCF_CAN_MBUF2_BYTE1(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C00A9+((x)*0x30000)]))
-#define MCF_CAN_MBUF2_BYTE2(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C00AA+((x)*0x30000)]))
-#define MCF_CAN_MBUF2_BYTE3(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C00AB+((x)*0x30000)]))
-#define MCF_CAN_MBUF2_BYTE4(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C00AC+((x)*0x30000)]))
-#define MCF_CAN_MBUF2_BYTE5(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C00AD+((x)*0x30000)]))
-#define MCF_CAN_MBUF2_BYTE6(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C00AE+((x)*0x30000)]))
-#define MCF_CAN_MBUF2_BYTE7(x)      (*(vuint8  *)(void *)(&__IPSBAR[0x1C00AF+((x)*0x30000)]))
-#define MCF_CAN_MBUF3_CTRL(x)		(*(vuint16 *)(void *)(&__IPSBAR[0x1C00B0+((x)*0x30000)]))
-#define MCF_CAN_MBUF3_ID(x)			(*(vuint32 *)(void *)(&__IPSBAR[0x1C00B4+((x)*0x30000)]))
-#define MCF_CAN_MBUF3_BYTE0(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00B8+((x)*0x30000)]))
-#define MCF_CAN_MBUF3_BYTE1(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00B9+((x)*0x30000)]))
-#define MCF_CAN_MBUF3_BYTE2(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00BA+((x)*0x30000)]))
-#define MCF_CAN_MBUF3_BYTE3(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00BB+((x)*0x30000)]))
-#define MCF_CAN_MBUF3_BYTE4(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00BC+((x)*0x30000)]))
-#define MCF_CAN_MBUF3_BYTE5(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00BD+((x)*0x30000)]))
-#define MCF_CAN_MBUF3_BYTE6(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00BE+((x)*0x30000)]))
-#define MCF_CAN_MBUF3_BYTE7(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00BF+((x)*0x30000)]))
-#define MCF_CAN_MBUF4_CTRL(x)		(*(vuint16 *)(void *)(&__IPSBAR[0x1C00C0+((x)*0x30000)]))
-#define MCF_CAN_MBUF4_ID(x) 	    (*(vuint32 *)(void *)(&__IPSBAR[0x1C00C4+((x)*0x30000)]))
-#define MCF_CAN_MBUF4_BYTE0(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C00C8+((x)*0x30000)]))
-#define MCF_CAN_MBUF4_BYTE1(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C00C9+((x)*0x30000)]))
-#define MCF_CAN_MBUF4_BYTE2(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C00CA+((x)*0x30000)]))
-#define MCF_CAN_MBUF4_BYTE3(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C00CB+((x)*0x30000)]))
-#define MCF_CAN_MBUF4_BYTE4(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C00CC+((x)*0x30000)]))
-#define MCF_CAN_MBUF4_BYTE5(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C00CD+((x)*0x30000)]))
-#define MCF_CAN_MBUF4_BYTE6(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C00CE+((x)*0x30000)]))
-#define MCF_CAN_MBUF4_BYTE7(x)      (*(vuint8  *)(void *)(&__IPSBAR[0x1C00CF+((x)*0x30000)]))
-#define MCF_CAN_MBUF5_CTRL(x)		(*(vuint16 *)(void *)(&__IPSBAR[0x1C00D0+((x)*0x30000)]))
-#define MCF_CAN_MBUF5_ID(x)			(*(vuint32 *)(void *)(&__IPSBAR[0x1C00D4+((x)*0x30000)]))
-#define MCF_CAN_MBUF5_BYTE0(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00D8+((x)*0x30000)]))
-#define MCF_CAN_MBUF5_BYTE1(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00D9+((x)*0x30000)]))
-#define MCF_CAN_MBUF5_BYTE2(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00DA+((x)*0x30000)]))
-#define MCF_CAN_MBUF5_BYTE3(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00DB+((x)*0x30000)]))
-#define MCF_CAN_MBUF5_BYTE4(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00DC+((x)*0x30000)]))
-#define MCF_CAN_MBUF5_BYTE5(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00DD+((x)*0x30000)]))
-#define MCF_CAN_MBUF5_BYTE6(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00DE+((x)*0x30000)]))
-#define MCF_CAN_MBUF5_BYTE7(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00DF+((x)*0x30000)]))
-#define MCF_CAN_MBUF6_CTRL(x)		(*(vuint16 *)(void *)(&__IPSBAR[0x1C00E0+((x)*0x30000)]))
-#define MCF_CAN_MBUF6_ID(x) 	    (*(vuint32 *)(void *)(&__IPSBAR[0x1C00E4+((x)*0x30000)]))
-#define MCF_CAN_MBUF6_BYTE0(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C00E8+((x)*0x30000)]))
-#define MCF_CAN_MBUF6_BYTE1(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C00E9+((x)*0x30000)]))
-#define MCF_CAN_MBUF6_BYTE2(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C00EA+((x)*0x30000)]))
-#define MCF_CAN_MBUF6_BYTE3(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C00EB+((x)*0x30000)]))
-#define MCF_CAN_MBUF6_BYTE4(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C00EC+((x)*0x30000)]))
-#define MCF_CAN_MBUF6_BYTE5(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C00ED+((x)*0x30000)]))
-#define MCF_CAN_MBUF6_BYTE6(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C00EE+((x)*0x30000)]))
-#define MCF_CAN_MBUF6_BYTE7(x)      (*(vuint8  *)(void *)(&__IPSBAR[0x1C00EF+((x)*0x30000)]))
-#define MCF_CAN_MBUF7_CTRL(x)		(*(vuint16 *)(void *)(&__IPSBAR[0x1C00F0+((x)*0x30000)]))
-#define MCF_CAN_MBUF7_ID(x)			(*(vuint32 *)(void *)(&__IPSBAR[0x1C00F4+((x)*0x30000)]))
-#define MCF_CAN_MBUF7_BYTE0(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00F8+((x)*0x30000)]))
-#define MCF_CAN_MBUF7_BYTE1(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00F9+((x)*0x30000)]))
-#define MCF_CAN_MBUF7_BYTE2(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00FA+((x)*0x30000)]))
-#define MCF_CAN_MBUF7_BYTE3(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00FB+((x)*0x30000)]))
-#define MCF_CAN_MBUF7_BYTE4(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00FC+((x)*0x30000)]))
-#define MCF_CAN_MBUF7_BYTE5(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00FD+((x)*0x30000)]))
-#define MCF_CAN_MBUF7_BYTE6(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00FE+((x)*0x30000)]))
-#define MCF_CAN_MBUF7_BYTE7(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C00FF+((x)*0x30000)]))
-#define MCF_CAN_MBUF8_CTRL(x)		(*(vuint16 *)(void *)(&__IPSBAR[0x1C0100+((x)*0x30000)]))
-#define MCF_CAN_MBUF8_ID(x) 	    (*(vuint32 *)(void *)(&__IPSBAR[0x1C0104+((x)*0x30000)]))
-#define MCF_CAN_MBUF8_BYTE0(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C0108+((x)*0x30000)]))
-#define MCF_CAN_MBUF8_BYTE1(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C0109+((x)*0x30000)]))
-#define MCF_CAN_MBUF8_BYTE2(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C010A+((x)*0x30000)]))
-#define MCF_CAN_MBUF8_BYTE3(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C010B+((x)*0x30000)]))
-#define MCF_CAN_MBUF8_BYTE4(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C010C+((x)*0x30000)]))
-#define MCF_CAN_MBUF8_BYTE5(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C010D+((x)*0x30000)]))
-#define MCF_CAN_MBUF8_BYTE6(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C010E+((x)*0x30000)]))
-#define MCF_CAN_MBUF8_BYTE7(x)      (*(vuint8  *)(void *)(&__IPSBAR[0x1C010F+((x)*0x30000)]))
-#define MCF_CAN_MBUF9_CTRL(x)		(*(vuint16 *)(void *)(&__IPSBAR[0x1C0100+((x)*0x30000)]))
-#define MCF_CAN_MBUF9_ID(x)			(*(vuint32 *)(void *)(&__IPSBAR[0x1C0114+((x)*0x30000)]))
-#define MCF_CAN_MBUF9_BYTE0(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C0118+((x)*0x30000)]))
-#define MCF_CAN_MBUF9_BYTE1(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C0119+((x)*0x30000)]))
-#define MCF_CAN_MBUF9_BYTE2(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C011A+((x)*0x30000)]))
-#define MCF_CAN_MBUF9_BYTE3(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C011B+((x)*0x30000)]))
-#define MCF_CAN_MBUF9_BYTE4(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C011C+((x)*0x30000)]))
-#define MCF_CAN_MBUF9_BYTE5(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C011D+((x)*0x30000)]))
-#define MCF_CAN_MBUF9_BYTE6(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C011E+((x)*0x30000)]))
-#define MCF_CAN_MBUF9_BYTE7(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C011F+((x)*0x30000)]))
-#define MCF_CAN_MBUF10_CTRL(x)		(*(vuint16 *)(void *)(&__IPSBAR[0x1C0120+((x)*0x30000)]))
-#define MCF_CAN_MBUF10_ID(x) 	    (*(vuint32 *)(void *)(&__IPSBAR[0x1C0124+((x)*0x30000)]))
-#define MCF_CAN_MBUF10_BYTE0(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C0128+((x)*0x30000)]))
-#define MCF_CAN_MBUF10_BYTE1(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C0129+((x)*0x30000)]))
-#define MCF_CAN_MBUF10_BYTE2(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C012A+((x)*0x30000)]))
-#define MCF_CAN_MBUF10_BYTE3(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C012B+((x)*0x30000)]))
-#define MCF_CAN_MBUF10_BYTE4(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C012C+((x)*0x30000)]))
-#define MCF_CAN_MBUF10_BYTE5(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C012D+((x)*0x30000)]))
-#define MCF_CAN_MBUF10_BYTE6(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C012E+((x)*0x30000)]))
-#define MCF_CAN_MBUF10_BYTE7(x)     (*(vuint8  *)(void *)(&__IPSBAR[0x1C012F+((x)*0x30000)]))
-#define MCF_CAN_MBUF11_CTRL(x)		(*(vuint16 *)(void *)(&__IPSBAR[0x1C0130+((x)*0x30000)]))
-#define MCF_CAN_MBUF11_ID(x)		(*(vuint32 *)(void *)(&__IPSBAR[0x1C0134+((x)*0x30000)]))
-#define MCF_CAN_MBUF11_BYTE0(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C0138+((x)*0x30000)]))
-#define MCF_CAN_MBUF11_BYTE1(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C0139+((x)*0x30000)]))
-#define MCF_CAN_MBUF11_BYTE2(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C013A+((x)*0x30000)]))
-#define MCF_CAN_MBUF11_BYTE3(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C013B+((x)*0x30000)]))
-#define MCF_CAN_MBUF11_BYTE4(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C013C+((x)*0x30000)]))
-#define MCF_CAN_MBUF11_BYTE5(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C013D+((x)*0x30000)]))
-#define MCF_CAN_MBUF11_BYTE6(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C013E+((x)*0x30000)]))
-#define MCF_CAN_MBUF11_BYTE7(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C013F+((x)*0x30000)]))
-#define MCF_CAN_MBUF12_CTRL(x)		(*(vuint16 *)(void *)(&__IPSBAR[0x1C0140+((x)*0x30000)]))
-#define MCF_CAN_MBUF12_ID(x) 	    (*(vuint32 *)(void *)(&__IPSBAR[0x1C0144+((x)*0x30000)]))
-#define MCF_CAN_MBUF12_BYTE0(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C0148+((x)*0x30000)]))
-#define MCF_CAN_MBUF12_BYTE1(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C0149+((x)*0x30000)]))
-#define MCF_CAN_MBUF12_BYTE2(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C014A+((x)*0x30000)]))
-#define MCF_CAN_MBUF12_BYTE3(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C014B+((x)*0x30000)]))
-#define MCF_CAN_MBUF12_BYTE4(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C014C+((x)*0x30000)]))
-#define MCF_CAN_MBUF12_BYTE5(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C014D+((x)*0x30000)]))
-#define MCF_CAN_MBUF12_BYTE6(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C014E+((x)*0x30000)]))
-#define MCF_CAN_MBUF12_BYTE7(x)     (*(vuint8  *)(void *)(&__IPSBAR[0x1C014F+((x)*0x30000)]))
-#define MCF_CAN_MBUF13_CTRL(x)		(*(vuint16 *)(void *)(&__IPSBAR[0x1C0150+((x)*0x30000)]))
-#define MCF_CAN_MBUF13_ID(x)		(*(vuint32 *)(void *)(&__IPSBAR[0x1C0154+((x)*0x30000)]))
-#define MCF_CAN_MBUF13_BYTE0(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C0158+((x)*0x30000)]))
-#define MCF_CAN_MBUF13_BYTE1(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C0159+((x)*0x30000)]))
-#define MCF_CAN_MBUF13_BYTE2(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C015A+((x)*0x30000)]))
-#define MCF_CAN_MBUF13_BYTE3(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C015B+((x)*0x30000)]))
-#define MCF_CAN_MBUF13_BYTE4(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C015C+((x)*0x30000)]))
-#define MCF_CAN_MBUF13_BYTE5(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C015D+((x)*0x30000)]))
-#define MCF_CAN_MBUF13_BYTE6(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C015E+((x)*0x30000)]))
-#define MCF_CAN_MBUF13_BYTE7(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C015F+((x)*0x30000)]))
-#define MCF_CAN_MBUF14_CTRL(x)		(*(vuint16 *)(void *)(&__IPSBAR[0x1C0160+((x)*0x30000)]))
-#define MCF_CAN_MBUF14_ID(x) 	    (*(vuint32 *)(void *)(&__IPSBAR[0x1C0164+((x)*0x30000)]))
-#define MCF_CAN_MBUF14_BYTE0(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C0168+((x)*0x30000)]))
-#define MCF_CAN_MBUF14_BYTE1(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C0169+((x)*0x30000)]))
-#define MCF_CAN_MBUF14_BYTE2(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C016A+((x)*0x30000)]))
-#define MCF_CAN_MBUF14_BYTE3(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C016B+((x)*0x30000)]))
-#define MCF_CAN_MBUF14_BYTE4(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C016C+((x)*0x30000)]))
-#define MCF_CAN_MBUF14_BYTE5(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C016D+((x)*0x30000)]))
-#define MCF_CAN_MBUF14_BYTE6(x)	    (*(vuint8  *)(void *)(&__IPSBAR[0x1C016E+((x)*0x30000)]))
-#define MCF_CAN_MBUF14_BYTE7(x)     (*(vuint8  *)(void *)(&__IPSBAR[0x1C016F+((x)*0x30000)]))
-#define MCF_CAN_MBUF15_CTRL(x)		(*(vuint16 *)(void *)(&__IPSBAR[0x1C0170+((x)*0x30000)]))
-#define MCF_CAN_MBUF15_ID(x)		(*(vuint32 *)(void *)(&__IPSBAR[0x1C0174+((x)*0x30000)]))
-#define MCF_CAN_MBUF15_BYTE0(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C0178+((x)*0x30000)]))
-#define MCF_CAN_MBUF15_BYTE1(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C0179+((x)*0x30000)]))
-#define MCF_CAN_MBUF15_BYTE2(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C017A+((x)*0x30000)]))
-#define MCF_CAN_MBUF15_BYTE3(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C017B+((x)*0x30000)]))
-#define MCF_CAN_MBUF15_BYTE4(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C017C+((x)*0x30000)]))
-#define MCF_CAN_MBUF15_BYTE5(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C017D+((x)*0x30000)]))
-#define MCF_CAN_MBUF15_BYTE6(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C017E+((x)*0x30000)]))
-#define MCF_CAN_MBUF15_BYTE7(x)		(*(vuint8  *)(void *)(&__IPSBAR[0x1C017F+((x)*0x30000)]))
-																				  
-																				  
-#define MCF_CAN_MBUF0_DATAL(x)	    (*(vuint32  *)(void *)(&__IPSBAR[0x1C0088+((x)*0x30000)]))
-#define MCF_CAN_MBUF0_DATAH(x)	    (*(vuint32  *)(void *)(&__IPSBAR[0x1C008C+((x)*0x30000)]))
-#define MCF_CAN_MBUF1_DATAL(x)		(*(vuint32  *)(void *)(&__IPSBAR[0x1C0098+((x)*0x30000)]))
-#define MCF_CAN_MBUF1_DATAH(x)		(*(vuint32  *)(void *)(&__IPSBAR[0x1C009C+((x)*0x30000)]))
-#define MCF_CAN_MBUF2_DATAL(x)	    (*(vuint32  *)(void *)(&__IPSBAR[0x1C00A8+((x)*0x30000)]))
-#define MCF_CAN_MBUF2_DATAH(x)	    (*(vuint32  *)(void *)(&__IPSBAR[0x1C00AC+((x)*0x30000)]))
-																				  
-																				  
-/* Bit definitions and macros for MCF_CAN_CANMCR */								  
-#define MCF_CAN_CANMCR_MAXMB(x)            (((x)&0x0000000F)<<0)				  
-#define MCF_CAN_CANMCR_SUPV                (0x00800000)							  
-#define MCF_CAN_CANMCR_FRZACK              (0x01000000)							  
-#define MCF_CAN_CANMCR_SOFTRST             (0x02000000)							  
-#define MCF_CAN_CANMCR_HALT                (0x10000000)							  
-#define MCF_CAN_CANMCR_FRZ                 (0x40000000)							  
-#define MCF_CAN_CANMCR_MDIS                (0x80000000)							  
-
-/* Bit definitions and macros for MCF_CAN_CANCTRL */
-#define MCF_CAN_CANCTRL_PROPSEG(x)         (((x)&0x00000007)<<0)
-#define MCF_CAN_CANCTRL_LOM                (0x00000008)
-#define MCF_CAN_CANCTRL_LBUF               (0x00000010)
-#define MCF_CAN_CANCTRL_TSYNC              (0x00000020)
-#define MCF_CAN_CANCTRL_BOFFREC            (0x00000040)
-#define MCF_CAN_CANCTRL_SAMP               (0x00000080)
-#define MCF_CAN_CANCTRL_LPB                (0x00001000)
-#define MCF_CAN_CANCTRL_CLKSRC             (0x00002000)
-#define MCF_CAN_CANCTRL_ERRMSK             (0x00004000)
-#define MCF_CAN_CANCTRL_BOFFMSK            (0x00008000)
-#define MCF_CAN_CANCTRL_PSEG2(x)           (((x)&0x00000007)<<16)
-#define MCF_CAN_CANCTRL_PSEG1(x)           (((x)&0x00000007)<<19)
-#define MCF_CAN_CANCTRL_RJW(x)             (((x)&0x00000003)<<22)
-#define MCF_CAN_CANCTRL_PRESDIV(x)         (((x)&0x000000FF)<<24)
-
-/* Bit definitions and macros for MCF_CAN_TIMER */
-#define MCF_CAN_TIMER_TIMER(x)             (((x)&0x0000FFFF)<<0)
-
-/* Bit definitions and macros for MCF_CAN_RXGMASK */
-#define MCF_CAN_RXGMASK_MI(x)              (((x)&0x1FFFFFFF)<<0)
-
-/* Bit definitions and macros for MCF_CAN_RX14MASK */
-#define MCF_CAN_RX14MASK_MI(x)             (((x)&0x1FFFFFFF)<<0)
-
-/* Bit definitions and macros for MCF_CAN_RX15MASK */
-#define MCF_CAN_RX15MASK_MI(x)             (((x)&0x1FFFFFFF)<<0)
-
-/* Bit definitions and macros for MCF_CAN_ERRCNT */
-#define MCF_CAN_ERRCNT_TXECTR(x)           (((x)&0x000000FF)<<0)
-#define MCF_CAN_ERRCNT_RXECTR(x)           (((x)&0x000000FF)<<8)
-
-/* Bit definitions and macros for MCF_CAN_ERRSTAT */
-#define MCF_CAN_ERRSTAT_WAKINT             (0x00000001)
-#define MCF_CAN_ERRSTAT_ERRINT             (0x00000002)
-#define MCF_CAN_ERRSTAT_BOFFINT            (0x00000004)
-#define MCF_CAN_ERRSTAT_FLTCONF(x)         (((x)&0x00000003)<<4)
-#define MCF_CAN_ERRSTAT_TXRX               (0x00000040)
-#define MCF_CAN_ERRSTAT_IDLE               (0x00000080)
-#define MCF_CAN_ERRSTAT_RXWRN              (0x00000100)
-#define MCF_CAN_ERRSTAT_TXWRN              (0x00000200)
-#define MCF_CAN_ERRSTAT_STFERR             (0x00000400)
-#define MCF_CAN_ERRSTAT_FRMERR             (0x00000800)
-#define MCF_CAN_ERRSTAT_CRCERR             (0x00001000)
-#define MCF_CAN_ERRSTAT_ACKERR             (0x00002000)
-#define MCF_CAN_ERRSTAT_BITERR(x)          (((x)&0x00000003)<<14)
-#define MCF_CAN_ERRSTAT_FLTCONF_ACTIVE     (0x00000000)
-#define MCF_CAN_ERRSTAT_FLTCONF_PASSIVE    (0x00000010)
-#define MCF_CAN_ERRSTAT_FLTCONF_BUSOFF     (0x00000020)
-
-/* Bit definitions and macros for MCF_CAN_IMASK */
-#define MCF_CAN_IMASK_BUF0M                (0x0001)
-#define MCF_CAN_IMASK_BUF1M                (0x0002)
-#define MCF_CAN_IMASK_BUF2M                (0x0004)
-#define MCF_CAN_IMASK_BUF3M                (0x0008)
-#define MCF_CAN_IMASK_BUF4M                (0x0010)
-#define MCF_CAN_IMASK_BUF5M                (0x0020)
-#define MCF_CAN_IMASK_BUF6M                (0x0040)
-#define MCF_CAN_IMASK_BUF7M                (0x0080)
-#define MCF_CAN_IMASK_BUF8M                (0x0100)
-#define MCF_CAN_IMASK_BUF9M                (0x0200)
-#define MCF_CAN_IMASK_BUF10M               (0x0400)
-#define MCF_CAN_IMASK_BUF11M               (0x0800)
-#define MCF_CAN_IMASK_BUF12M               (0x1000)
-#define MCF_CAN_IMASK_BUF13M               (0x2000)
-#define MCF_CAN_IMASK_BUF14M               (0x4000)
-#define MCF_CAN_IMASK_BUF15M               (0x8000)
-
-/* Bit definitions and macros for MCF_CAN_IFLAG */
-#define MCF_CAN_IFLAG_BUF0I                (0x0001)
-#define MCF_CAN_IFLAG_BUF1I                (0x0002)
-#define MCF_CAN_IFLAG_BUF2I                (0x0004)
-#define MCF_CAN_IFLAG_BUF3I                (0x0008)
-#define MCF_CAN_IFLAG_BUF4I                (0x0010)
-#define MCF_CAN_IFLAG_BUF5I                (0x0020)
-#define MCF_CAN_IFLAG_BUF6I                (0x0040)
-#define MCF_CAN_IFLAG_BUF7I                (0x0080)
-#define MCF_CAN_IFLAG_BUF8I                (0x0100)
-#define MCF_CAN_IFLAG_BUF9I                (0x0200)
-#define MCF_CAN_IFLAG_BUF10I               (0x0400)
-#define MCF_CAN_IFLAG_BUF11I               (0x0800)
-#define MCF_CAN_IFLAG_BUF12I               (0x1000)
-#define MCF_CAN_IFLAG_BUF13I               (0x2000)
-#define MCF_CAN_IFLAG_BUF14I               (0x4000)
-#define MCF_CAN_IFLAG_BUF15I               (0x8000)
-
-/********************************************************************/
-
-#endif /* __MCF523X_CAN_H__ */
diff --git a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_ccm.h b/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_ccm.h
deleted file mode 100644
index da9bdb79e..000000000
--- a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_ccm.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly 
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file 
- * LICENSE_FREESCALE.TXT.
- *
- * File:	mcf523x_ccm.h
- * Purpose:	Register and bit definitions for the MCF523X
- *
- * Notes:	
- *	
- */
-
-#ifndef __MCF523X_CCM_H__
-#define __MCF523X_CCM_H__
-
-/*********************************************************************
-*
-* Chip Configuration Module (CCM)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_CCM_CCR     (*(vuint16*)(void*)(&__IPSBAR[0x110004]))
-#define MCF_CCM_LPCR    (*(vuint8 *)(void*)(&__IPSBAR[0x110007]))
-#define MCF_CCM_CIR     (*(vuint16*)(void*)(&__IPSBAR[0x11000A]))
-#define MCF_CCM_RCON    (*(vuint16*)(void*)(&__IPSBAR[0x110008]))
-
-/* Bit definitions and macros for MCF_CCM_CCR */
-#define MCF_CCM_CCR_BMT(x)        (((x)&0x0007)<<0)
-#define MCF_CCM_CCR_BME           (0x0008)
-#define MCF_CCM_CCR_SZEN          (0x0040)
-#define MCF_CCM_CCR_MODE(x)       (((x)&0x0007)<<8)
-
-/* Bit definitions and macros for MCF_CCM_LPCR */
-#define MCF_CCM_LPCR_STPMD(x)     (((x)&0x03)<<3)
-#define MCF_CCM_LPCR_LPMD(x)      (((x)&0x03)<<6)
-#define MCF_CCM_LPCR_LPMD_STOP    (0xC0)
-#define MCF_CCM_LPCR_LPMD_WAIT    (0x80)
-#define MCF_CCM_LPCR_LPMD_DOZE    (0x40)
-#define MCF_CCM_LPCR_LPMD_RUN     (0x00)
-
-/* Bit definitions and macros for MCF_CCM_CIR */
-#define MCF_CCM_CIR_PRN(x)        (((x)&0x003F)<<0)
-#define MCF_CCM_CIR_PIN(x)        (((x)&0x03FF)<<6)
-
-/* Bit definitions and macros for MCF_CCM_RCON */
-#define MCF_CCM_RCON_MODE         (0x0001)
-#define MCF_CCM_RCON_BOOTPS(x)    (((x)&0x0003)<<3)
-#define MCF_CCM_RCON_RLOAD        (0x0020)
-#define MCF_CCM_RCON_RCSC(x)      (((x)&0x0003)<<8)
-
-/********************************************************************/
-
-#endif /* __MCF523X_CCM_H__ */
diff --git a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_cs.h b/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_cs.h
deleted file mode 100644
index 27251c80a..000000000
--- a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_cs.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly 
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file 
- * LICENSE_FREESCALE.TXT.
- *
- * File:	mcf523x_cs.h
- * Purpose:	Register and bit definitions for the MCF523X
- *
- * Notes:	
- *	
- */
-
-#ifndef __MCF523X_CS_H__
-#define __MCF523X_CS_H__
-
-/*********************************************************************
-*
-* Chip Selects (CS)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_CS_CSAR0      (*(vuint16*)(void*)(&__IPSBAR[0x000080]))
-#define MCF_CS_CSMR0      (*(vuint32*)(void*)(&__IPSBAR[0x000084]))
-#define MCF_CS_CSCR0      (*(vuint16*)(void*)(&__IPSBAR[0x00008A]))
-#define MCF_CS_CSAR1      (*(vuint16*)(void*)(&__IPSBAR[0x00008C]))
-#define MCF_CS_CSMR1      (*(vuint32*)(void*)(&__IPSBAR[0x000090]))
-#define MCF_CS_CSCR1      (*(vuint16*)(void*)(&__IPSBAR[0x000096]))
-#define MCF_CS_CSAR2      (*(vuint16*)(void*)(&__IPSBAR[0x000098]))
-#define MCF_CS_CSMR2      (*(vuint32*)(void*)(&__IPSBAR[0x00009C]))
-#define MCF_CS_CSCR2      (*(vuint16*)(void*)(&__IPSBAR[0x0000A2]))
-#define MCF_CS_CSAR3      (*(vuint16*)(void*)(&__IPSBAR[0x0000A4]))
-#define MCF_CS_CSMR3      (*(vuint32*)(void*)(&__IPSBAR[0x0000A8]))
-#define MCF_CS_CSCR3      (*(vuint16*)(void*)(&__IPSBAR[0x0000AE]))
-#define MCF_CS_CSAR4      (*(vuint16*)(void*)(&__IPSBAR[0x0000B0]))
-#define MCF_CS_CSMR4      (*(vuint32*)(void*)(&__IPSBAR[0x0000B4]))
-#define MCF_CS_CSCR4      (*(vuint16*)(void*)(&__IPSBAR[0x0000BA]))
-#define MCF_CS_CSAR5      (*(vuint16*)(void*)(&__IPSBAR[0x0000BC]))
-#define MCF_CS_CSMR5      (*(vuint32*)(void*)(&__IPSBAR[0x0000C0]))
-#define MCF_CS_CSCR5      (*(vuint16*)(void*)(&__IPSBAR[0x0000C6]))
-#define MCF_CS_CSAR6      (*(vuint16*)(void*)(&__IPSBAR[0x0000C8]))
-#define MCF_CS_CSMR6      (*(vuint32*)(void*)(&__IPSBAR[0x0000CC]))
-#define MCF_CS_CSCR6      (*(vuint16*)(void*)(&__IPSBAR[0x0000D2]))
-#define MCF_CS_CSAR7      (*(vuint16*)(void*)(&__IPSBAR[0x0000D4]))
-#define MCF_CS_CSMR7      (*(vuint32*)(void*)(&__IPSBAR[0x0000D8]))
-#define MCF_CS_CSCR7      (*(vuint16*)(void*)(&__IPSBAR[0x0000DE]))
-#define MCF_CS_CSAR(x)    (*(vuint16*)(void*)(&__IPSBAR[0x000080+((x)*0x00C)]))
-#define MCF_CS_CSMR(x)    (*(vuint32*)(void*)(&__IPSBAR[0x000084+((x)*0x00C)]))
-#define MCF_CS_CSCR(x)    (*(vuint16*)(void*)(&__IPSBAR[0x00008A+((x)*0x00C)]))
-
-/* Bit definitions and macros for MCF_CS_CSAR */
-#define MCF_CS_CSAR_BA(x)        ((uint16)(((x)&0xFFFF0000)>>16))
-
-/* Bit definitions and macros for MCF_CS_CSMR */
-#define MCF_CS_CSMR_V            (0x00000001)
-#define MCF_CS_CSMR_UD           (0x00000002)
-#define MCF_CS_CSMR_UC           (0x00000004)
-#define MCF_CS_CSMR_SD           (0x00000008)
-#define MCF_CS_CSMR_SC           (0x00000010)
-#define MCF_CS_CSMR_CI           (0x00000020)
-#define MCF_CS_CSMR_AM           (0x00000040)
-#define MCF_CS_CSMR_WP           (0x00000100)
-#define MCF_CS_CSMR_BAM(x)       (((x)&0x0000FFFF)<<16)
-#define MCF_CS_CSMR_BAM_4G       (0xFFFF0000)
-#define MCF_CS_CSMR_BAM_2G       (0x7FFF0000)
-#define MCF_CS_CSMR_BAM_1G       (0x3FFF0000)
-#define MCF_CS_CSMR_BAM_1024M    (0x3FFF0000)
-#define MCF_CS_CSMR_BAM_512M     (0x1FFF0000)
-#define MCF_CS_CSMR_BAM_256M     (0x0FFF0000)
-#define MCF_CS_CSMR_BAM_128M     (0x07FF0000)
-#define MCF_CS_CSMR_BAM_64M      (0x03FF0000)
-#define MCF_CS_CSMR_BAM_32M      (0x01FF0000)
-#define MCF_CS_CSMR_BAM_16M      (0x00FF0000)
-#define MCF_CS_CSMR_BAM_8M       (0x007F0000)
-#define MCF_CS_CSMR_BAM_4M       (0x003F0000)
-#define MCF_CS_CSMR_BAM_2M       (0x001F0000)
-#define MCF_CS_CSMR_BAM_1M       (0x000F0000)
-#define MCF_CS_CSMR_BAM_1024K    (0x000F0000)
-#define MCF_CS_CSMR_BAM_512K     (0x00070000)
-#define MCF_CS_CSMR_BAM_256K     (0x00030000)
-#define MCF_CS_CSMR_BAM_128K     (0x00010000)
-#define MCF_CS_CSMR_BAM_64K      (0x00000000)
-
-/* Bit definitions and macros for MCF_CS_CSCR */
-#define MCF_CS_CSCR_SWWS(x)      (((x)&0x0007)<<0)
-#define MCF_CS_CSCR_BSTW         (0x0008)
-#define MCF_CS_CSCR_BSTR         (0x0010)
-#define MCF_CS_CSCR_BEM          (0x0020)
-#define MCF_CS_CSCR_PS(x)        (((x)&0x0003)<<6)
-#define MCF_CS_CSCR_AA           (0x0100)
-#define MCF_CS_CSCR_IWS(x)       (((x)&0x000F)<<10)
-#define MCF_CS_CSCR_SRWS(x)      (((x)&0x0003)<<14)
-#define MCF_CS_CSCR_PS_8         (0x0040)
-#define MCF_CS_CSCR_PS_16        (0x0080)
-#define MCF_CS_CSCR_PS_32        (0x0000)
-
-/********************************************************************/
-
-#endif /* __MCF523X_CS_H__ */
diff --git a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_eport.h b/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_eport.h
deleted file mode 100644
index 5629ebfa4..000000000
--- a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_eport.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly 
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file 
- * LICENSE_FREESCALE.TXT.
- *
- * File:	mcf523x_eport.h
- * Purpose:	Register and bit definitions for the MCF523X
- *
- * Notes:	
- *	
- */
-
-#ifndef __MCF523X_EPORT_H__
-#define __MCF523X_EPORT_H__
-
-/*********************************************************************
-*
-* Edge Port Module (EPORT)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_EPORT_EPPAR    (*(vuint16*)(void*)(&__IPSBAR[0x130000]))
-#define MCF_EPORT_EPDDR    (*(vuint8 *)(void*)(&__IPSBAR[0x130002]))
-#define MCF_EPORT_EPIER    (*(vuint8 *)(void*)(&__IPSBAR[0x130003]))
-#define MCF_EPORT_EPDR     (*(vuint8 *)(void*)(&__IPSBAR[0x130004]))
-#define MCF_EPORT_EPPDR    (*(vuint8 *)(void*)(&__IPSBAR[0x130005]))
-#define MCF_EPORT_EPFR     (*(vuint8 *)(void*)(&__IPSBAR[0x130006]))
-
-/* Bit definitions and macros for MCF_EPORT_EPPAR */
-#define MCF_EPORT_EPPAR_EPPA1(x)         (((x)&0x0003)<<2)
-#define MCF_EPORT_EPPAR_EPPA2(x)         (((x)&0x0003)<<4)
-#define MCF_EPORT_EPPAR_EPPA3(x)         (((x)&0x0003)<<6)
-#define MCF_EPORT_EPPAR_EPPA4(x)         (((x)&0x0003)<<8)
-#define MCF_EPORT_EPPAR_EPPA5(x)         (((x)&0x0003)<<10)
-#define MCF_EPORT_EPPAR_EPPA6(x)         (((x)&0x0003)<<12)
-#define MCF_EPORT_EPPAR_EPPA7(x)         (((x)&0x0003)<<14)
-#define MCF_EPORT_EPPAR_EPPAx_LEVEL      (0)
-#define MCF_EPORT_EPPAR_EPPAx_RISING     (1)
-#define MCF_EPORT_EPPAR_EPPAx_FALLING    (2)
-#define MCF_EPORT_EPPAR_EPPAx_BOTH       (3)
-
-/* Bit definitions and macros for MCF_EPORT_EPDDR */
-#define MCF_EPORT_EPDDR_EPDD1            (0x02)
-#define MCF_EPORT_EPDDR_EPDD2            (0x04)
-#define MCF_EPORT_EPDDR_EPDD3            (0x08)
-#define MCF_EPORT_EPDDR_EPDD4            (0x10)
-#define MCF_EPORT_EPDDR_EPDD5            (0x20)
-#define MCF_EPORT_EPDDR_EPDD6            (0x40)
-#define MCF_EPORT_EPDDR_EPDD7            (0x80)
-
-/* Bit definitions and macros for MCF_EPORT_EPIER */
-#define MCF_EPORT_EPIER_EPIE1            (0x02)
-#define MCF_EPORT_EPIER_EPIE2            (0x04)
-#define MCF_EPORT_EPIER_EPIE3            (0x08)
-#define MCF_EPORT_EPIER_EPIE4            (0x10)
-#define MCF_EPORT_EPIER_EPIE5            (0x20)
-#define MCF_EPORT_EPIER_EPIE6            (0x40)
-#define MCF_EPORT_EPIER_EPIE7            (0x80)
-
-/* Bit definitions and macros for MCF_EPORT_EPDR */
-#define MCF_EPORT_EPDR_EPD1              (0x02)
-#define MCF_EPORT_EPDR_EPD2              (0x04)
-#define MCF_EPORT_EPDR_EPD3              (0x08)
-#define MCF_EPORT_EPDR_EPD4              (0x10)
-#define MCF_EPORT_EPDR_EPD5              (0x20)
-#define MCF_EPORT_EPDR_EPD6              (0x40)
-#define MCF_EPORT_EPDR_EPD7              (0x80)
-
-/* Bit definitions and macros for MCF_EPORT_EPPDR */
-#define MCF_EPORT_EPPDR_EPPD1            (0x02)
-#define MCF_EPORT_EPPDR_EPPD2            (0x04)
-#define MCF_EPORT_EPPDR_EPPD3            (0x08)
-#define MCF_EPORT_EPPDR_EPPD4            (0x10)
-#define MCF_EPORT_EPPDR_EPPD5            (0x20)
-#define MCF_EPORT_EPPDR_EPPD6            (0x40)
-#define MCF_EPORT_EPPDR_EPPD7            (0x80)
-
-/* Bit definitions and macros for MCF_EPORT_EPFR */
-#define MCF_EPORT_EPFR_EPF1              (0x02)
-#define MCF_EPORT_EPFR_EPF2              (0x04)
-#define MCF_EPORT_EPFR_EPF3              (0x08)
-#define MCF_EPORT_EPFR_EPF4              (0x10)
-#define MCF_EPORT_EPFR_EPF5              (0x20)
-#define MCF_EPORT_EPFR_EPF6              (0x40)
-#define MCF_EPORT_EPFR_EPF7              (0x80)
-
-/********************************************************************/
-
-#endif /* __MCF523X_EPORT_H__ */
diff --git a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_etpu.h b/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_etpu.h
deleted file mode 100644
index 91075acf8..000000000
--- a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_etpu.h
+++ /dev/null
@@ -1,493 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly 
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file 
- * LICENSE_FREESCALE.TXT.
- *
- * File:	mcf523x_etpu.h
- * Purpose:	Register and bit definitions for the MCF523X
- *
- * Notes:	
- *	
- */
-
-#ifndef __MCF523X_ETPU_H__
-#define __MCF523X_ETPU_H__
-
-/*********************************************************************
-*
-* enhanced Time Processor Unit (ETPU)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_ETPU_EMCR          (*(vuint32*)(void*)(&__IPSBAR[0x1D0000]))
-#define MCF_ETPU_ECDCR         (*(vuint32*)(void*)(&__IPSBAR[0x1D0004]))
-#define MCF_ETPU_EMISCCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D000C]))
-#define MCF_ETPU_ESCMODR       (*(vuint32*)(void*)(&__IPSBAR[0x1D0010]))
-#define MCF_ETPU_EECR          (*(vuint32*)(void*)(&__IPSBAR[0x1D0014]))
-#define MCF_ETPU_ETBCR         (*(vuint32*)(void*)(&__IPSBAR[0x1D0020]))
-#define MCF_ETPU_ETB1R         (*(vuint32*)(void*)(&__IPSBAR[0x1D0024]))
-#define MCF_ETPU_ETB2R         (*(vuint32*)(void*)(&__IPSBAR[0x1D0028]))
-#define MCF_ETPU_EREDCR        (*(vuint32*)(void*)(&__IPSBAR[0x1D002C]))
-#define MCF_ETPU_ECISR         (*(vuint32*)(void*)(&__IPSBAR[0x1D0200]))
-#define MCF_ETPU_ECDTRSR       (*(vuint32*)(void*)(&__IPSBAR[0x1D0210]))
-#define MCF_ETPU_ECIOSR        (*(vuint32*)(void*)(&__IPSBAR[0x1D0220]))
-#define MCF_ETPU_ECDTROSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D0230]))
-#define MCF_ETPU_ECIER         (*(vuint32*)(void*)(&__IPSBAR[0x1D0240]))
-#define MCF_ETPU_ECDTRER       (*(vuint32*)(void*)(&__IPSBAR[0x1D0250]))
-#define MCF_ETPU_ECPSSR        (*(vuint32*)(void*)(&__IPSBAR[0x1D0280]))
-#define MCF_ETPU_ECSSR         (*(vuint32*)(void*)(&__IPSBAR[0x1D0290]))
-#define MCF_ETPU_EC0SCR        (*(vuint32*)(void*)(&__IPSBAR[0x1D0404]))
-#define MCF_ETPU_EC1SCR        (*(vuint32*)(void*)(&__IPSBAR[0x1D0414]))
-#define MCF_ETPU_EC2SCR        (*(vuint32*)(void*)(&__IPSBAR[0x1D0424]))
-#define MCF_ETPU_EC3SCR        (*(vuint32*)(void*)(&__IPSBAR[0x1D0434]))
-#define MCF_ETPU_EC4SCR        (*(vuint32*)(void*)(&__IPSBAR[0x1D0444]))
-#define MCF_ETPU_EC5SCR        (*(vuint32*)(void*)(&__IPSBAR[0x1D0454]))
-#define MCF_ETPU_EC6SCR        (*(vuint32*)(void*)(&__IPSBAR[0x1D0464]))
-#define MCF_ETPU_EC7SCR        (*(vuint32*)(void*)(&__IPSBAR[0x1D0474]))
-#define MCF_ETPU_EC8SCR        (*(vuint32*)(void*)(&__IPSBAR[0x1D0484]))
-#define MCF_ETPU_EC9SCR        (*(vuint32*)(void*)(&__IPSBAR[0x1D0494]))
-#define MCF_ETPU_EC10SCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D04A4]))
-#define MCF_ETPU_EC11SCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D04B4]))
-#define MCF_ETPU_EC12SCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D04C4]))
-#define MCF_ETPU_EC13SCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D04D4]))
-#define MCF_ETPU_EC14SCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D04E4]))
-#define MCF_ETPU_EC15SCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D04F4]))
-#define MCF_ETPU_EC16SCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D0504]))
-#define MCF_ETPU_EC17SCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D0514]))
-#define MCF_ETPU_EC18SCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D0524]))
-#define MCF_ETPU_EC19SCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D0534]))
-#define MCF_ETPU_EC20SCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D0544]))
-#define MCF_ETPU_EC21SCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D0554]))
-#define MCF_ETPU_EC22SCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D0564]))
-#define MCF_ETPU_EC23SCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D0574]))
-#define MCF_ETPU_EC24SCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D0584]))
-#define MCF_ETPU_EC25SCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D0594]))
-#define MCF_ETPU_EC26SCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D05A4]))
-#define MCF_ETPU_EC27SCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D05B4]))
-#define MCF_ETPU_EC28SCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D05C4]))
-#define MCF_ETPU_EC29SCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D05D4]))
-#define MCF_ETPU_EC30SCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D05E4]))
-#define MCF_ETPU_EC31SCR       (*(vuint32*)(void*)(&__IPSBAR[0x1D05F4]))
-#define MCF_ETPU_ECnSCR(x)     (*(vuint32*)(void*)(&__IPSBAR[0x1D0404+((x)*0x010)]))
-#define MCF_ETPU_EC0CR         (*(vuint32*)(void*)(&__IPSBAR[0x1D0400]))
-#define MCF_ETPU_EC1CR         (*(vuint32*)(void*)(&__IPSBAR[0x1D0410]))
-#define MCF_ETPU_EC2CR         (*(vuint32*)(void*)(&__IPSBAR[0x1D0420]))
-#define MCF_ETPU_EC3CR         (*(vuint32*)(void*)(&__IPSBAR[0x1D0430]))
-#define MCF_ETPU_EC4CR         (*(vuint32*)(void*)(&__IPSBAR[0x1D0440]))
-#define MCF_ETPU_EC5CR         (*(vuint32*)(void*)(&__IPSBAR[0x1D0450]))
-#define MCF_ETPU_EC6CR         (*(vuint32*)(void*)(&__IPSBAR[0x1D0460]))
-#define MCF_ETPU_EC7CR         (*(vuint32*)(void*)(&__IPSBAR[0x1D0470]))
-#define MCF_ETPU_EC8CR         (*(vuint32*)(void*)(&__IPSBAR[0x1D0480]))
-#define MCF_ETPU_EC9CR         (*(vuint32*)(void*)(&__IPSBAR[0x1D0490]))
-#define MCF_ETPU_EC10CR        (*(vuint32*)(void*)(&__IPSBAR[0x1D04A0]))
-#define MCF_ETPU_EC11CR        (*(vuint32*)(void*)(&__IPSBAR[0x1D04B0]))
-#define MCF_ETPU_EC12CR        (*(vuint32*)(void*)(&__IPSBAR[0x1D04C0]))
-#define MCF_ETPU_EC13CR        (*(vuint32*)(void*)(&__IPSBAR[0x1D04D0]))
-#define MCF_ETPU_EC14CR        (*(vuint32*)(void*)(&__IPSBAR[0x1D04E0]))
-#define MCF_ETPU_EC15CR        (*(vuint32*)(void*)(&__IPSBAR[0x1D04F0]))
-#define MCF_ETPU_EC16CR        (*(vuint32*)(void*)(&__IPSBAR[0x1D0500]))
-#define MCF_ETPU_EC17CR        (*(vuint32*)(void*)(&__IPSBAR[0x1D0510]))
-#define MCF_ETPU_EC18CR        (*(vuint32*)(void*)(&__IPSBAR[0x1D0520]))
-#define MCF_ETPU_EC19CR        (*(vuint32*)(void*)(&__IPSBAR[0x1D0530]))
-#define MCF_ETPU_EC20CR        (*(vuint32*)(void*)(&__IPSBAR[0x1D0540]))
-#define MCF_ETPU_EC21CR        (*(vuint32*)(void*)(&__IPSBAR[0x1D0550]))
-#define MCF_ETPU_EC22CR        (*(vuint32*)(void*)(&__IPSBAR[0x1D0560]))
-#define MCF_ETPU_EC23CR        (*(vuint32*)(void*)(&__IPSBAR[0x1D0570]))
-#define MCF_ETPU_EC24CR        (*(vuint32*)(void*)(&__IPSBAR[0x1D0580]))
-#define MCF_ETPU_EC25CR        (*(vuint32*)(void*)(&__IPSBAR[0x1D0590]))
-#define MCF_ETPU_EC26CR        (*(vuint32*)(void*)(&__IPSBAR[0x1D05A0]))
-#define MCF_ETPU_EC27CR        (*(vuint32*)(void*)(&__IPSBAR[0x1D05B0]))
-#define MCF_ETPU_EC28CR        (*(vuint32*)(void*)(&__IPSBAR[0x1D05C0]))
-#define MCF_ETPU_EC29CR        (*(vuint32*)(void*)(&__IPSBAR[0x1D05D0]))
-#define MCF_ETPU_EC30CR        (*(vuint32*)(void*)(&__IPSBAR[0x1D05E0]))
-#define MCF_ETPU_EC31CR        (*(vuint32*)(void*)(&__IPSBAR[0x1D05F0]))
-#define MCF_ETPU_ECnCR(x)      (*(vuint32*)(void*)(&__IPSBAR[0x1D0400+((x)*0x010)]))
-#define MCF_ETPU_EC0HSSR       (*(vuint32*)(void*)(&__IPSBAR[0x1D0408]))
-#define MCF_ETPU_EC1HSSR       (*(vuint32*)(void*)(&__IPSBAR[0x1D0418]))
-#define MCF_ETPU_EC2HSSR       (*(vuint32*)(void*)(&__IPSBAR[0x1D0428]))
-#define MCF_ETPU_EC3HSSR       (*(vuint32*)(void*)(&__IPSBAR[0x1D0438]))
-#define MCF_ETPU_EC4HSSR       (*(vuint32*)(void*)(&__IPSBAR[0x1D0448]))
-#define MCF_ETPU_EC5HSSR       (*(vuint32*)(void*)(&__IPSBAR[0x1D0458]))
-#define MCF_ETPU_EC6HSSR       (*(vuint32*)(void*)(&__IPSBAR[0x1D0468]))
-#define MCF_ETPU_EC7HSSR       (*(vuint32*)(void*)(&__IPSBAR[0x1D0478]))
-#define MCF_ETPU_EC8HSSR       (*(vuint32*)(void*)(&__IPSBAR[0x1D0488]))
-#define MCF_ETPU_EC9HSSR       (*(vuint32*)(void*)(&__IPSBAR[0x1D0498]))
-#define MCF_ETPU_EC10HSSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D04A8]))
-#define MCF_ETPU_EC11HSSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D04B8]))
-#define MCF_ETPU_EC12HSSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D04C8]))
-#define MCF_ETPU_EC13HSSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D04D8]))
-#define MCF_ETPU_EC14HSSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D04E8]))
-#define MCF_ETPU_EC15HSSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D04F8]))
-#define MCF_ETPU_EC16HSSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D0508]))
-#define MCF_ETPU_EC17HSSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D0518]))
-#define MCF_ETPU_EC18HSSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D0528]))
-#define MCF_ETPU_EC19HSSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D0538]))
-#define MCF_ETPU_EC20HSSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D0548]))
-#define MCF_ETPU_EC21HSSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D0558]))
-#define MCF_ETPU_EC22HSSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D0568]))
-#define MCF_ETPU_EC23HSSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D0578]))
-#define MCF_ETPU_EC24HSSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D0588]))
-#define MCF_ETPU_EC25HSSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D0598]))
-#define MCF_ETPU_EC26HSSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D05A8]))
-#define MCF_ETPU_EC27HSSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D05B8]))
-#define MCF_ETPU_EC28HSSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D05C8]))
-#define MCF_ETPU_EC29HSSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D05D8]))
-#define MCF_ETPU_EC30HSSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D05E8]))
-#define MCF_ETPU_EC31HSSR      (*(vuint32*)(void*)(&__IPSBAR[0x1D05F8]))
-#define MCF_ETPU_ECnHSSR(x)    (*(vuint32*)(void*)(&__IPSBAR[0x1D0408+((x)*0x010)]))
-
-/* Bit definitions and macros for MCF_ETPU_EMCR */
-#define MCF_ETPU_EMCR_GTBE               (0x00000001)
-#define MCF_ETPU_EMCR_VIS                (0x00000040)
-#define MCF_ETPU_EMCR_SCMMISEN           (0x00000200)
-#define MCF_ETPU_EMCR_SCMMISF            (0x00000400)
-#define MCF_ETPU_EMCR_SCMSIZE(x)         (((x)&0x0000001F)<<16)
-#define MCF_ETPU_EMCR_ILF2               (0x01000000)
-#define MCF_ETPU_EMCR_ILF1               (0x02000000)
-#define MCF_ETPU_EMCR_MGE2               (0x04000000)
-#define MCF_ETPU_EMCR_MGE1               (0x08000000)
-#define MCF_ETPU_EMCR_GEC                (0x80000000)
-
-/* Bit definitions and macros for MCF_ETPU_ECDCR */
-#define MCF_ETPU_ECDCR_PARM1(x)          (((x)&0x0000007F)<<0)
-#define MCF_ETPU_ECDCR_WR                (0x00000080)
-#define MCF_ETPU_ECDCR_PARM0(x)          (((x)&0x0000007F)<<8)
-#define MCF_ETPU_ECDCR_PWIDTH            (0x00008000)
-#define MCF_ETPU_ECDCR_PBASE(x)          (((x)&0x000003FF)<<16)
-#define MCF_ETPU_ECDCR_CTBASE(x)         (((x)&0x0000001F)<<26)
-#define MCF_ETPU_ECDCR_STS               (0x80000000)
-
-/* Bit definitions and macros for MCF_ETPU_EECR */
-#define MCF_ETPU_EECR_ETB(x)             (((x)&0x0000001F)<<0)
-#define MCF_ETPU_EECR_CDFC(x)            (((x)&0x00000003)<<14)
-#define MCF_ETPU_EECR_FPSK(x)            (((x)&0x00000007)<<16)
-#define MCF_ETPU_EECR_HLTF               (0x00800000)
-#define MCF_ETPU_EECR_STF                (0x10000000)
-#define MCF_ETPU_EECR_MDIS               (0x40000000)
-#define MCF_ETPU_EECR_FEND               (0x80000000)
-
-/* Bit definitions and macros for MCF_ETPU_ETBCR */
-#define MCF_ETPU_ETBCR_TCR1P(x)          (((x)&0x000000FF)<<0)
-#define MCF_ETPU_ETBCR_TCR1CTL(x)        (((x)&0x00000003)<<14)
-#define MCF_ETPU_ETBCR_TCR2P(x)          (((x)&0x0000003F)<<16)
-#define MCF_ETPU_ETBCR_AM                (0x02000000)
-#define MCF_ETPU_ETBCR_TCRCF(x)          (((x)&0x00000003)<<27)
-#define MCF_ETPU_ETBCR_TCR2CTL(x)        (((x)&0x00000007)<<29)
-
-/* Bit definitions and macros for MCF_ETPU_ETB1R */
-#define MCF_ETPU_ETB1R_TCR1(x)           (((x)&0x00FFFFFF)<<0)
-
-/* Bit definitions and macros for MCF_ETPU_ETB2R */
-#define MCF_ETPU_ETB2R_TCR2(x)           (((x)&0x00FFFFFF)<<0)
-
-/* Bit definitions and macros for MCF_ETPU_EREDCR */
-#define MCF_ETPU_EREDCR_SRV2(x)          (((x)&0x0000000F)<<0)
-#define MCF_ETPU_EREDCR_SERVER_ID2(x)    (((x)&0x0000000F)<<8)
-#define MCF_ETPU_EREDCR_RSC2             (0x00004000)
-#define MCF_ETPU_EREDCR_REN2             (0x00008000)
-#define MCF_ETPU_EREDCR_SRV1(x)          (((x)&0x0000000F)<<16)
-#define MCF_ETPU_EREDCR_SERVER_ID1(x)    (((x)&0x0000000F)<<24)
-#define MCF_ETPU_EREDCR_RSC1             (0x40000000)
-#define MCF_ETPU_EREDCR_REN1             (0x80000000)
-
-/* Bit definitions and macros for MCF_ETPU_ECISR */
-#define MCF_ETPU_ECISR_CIS0              (0x00000001)
-#define MCF_ETPU_ECISR_CIS1              (0x00000002)
-#define MCF_ETPU_ECISR_CIS2              (0x00000004)
-#define MCF_ETPU_ECISR_CIS3              (0x00000008)
-#define MCF_ETPU_ECISR_CIS4              (0x00000010)
-#define MCF_ETPU_ECISR_CIS5              (0x00000020)
-#define MCF_ETPU_ECISR_CIS6              (0x00000040)
-#define MCF_ETPU_ECISR_CIS7              (0x00000080)
-#define MCF_ETPU_ECISR_CIS8              (0x00000100)
-#define MCF_ETPU_ECISR_CIS9              (0x00000200)
-#define MCF_ETPU_ECISR_CIS10             (0x00000400)
-#define MCF_ETPU_ECISR_CIS11             (0x00000800)
-#define MCF_ETPU_ECISR_CIS12             (0x00001000)
-#define MCF_ETPU_ECISR_CIS13             (0x00002000)
-#define MCF_ETPU_ECISR_CIS14             (0x00004000)
-#define MCF_ETPU_ECISR_CIS15             (0x00008000)
-#define MCF_ETPU_ECISR_CIS16             (0x00010000)
-#define MCF_ETPU_ECISR_CIS17             (0x00020000)
-#define MCF_ETPU_ECISR_CIS18             (0x00040000)
-#define MCF_ETPU_ECISR_CIS19             (0x00080000)
-#define MCF_ETPU_ECISR_CIS20             (0x00100000)
-#define MCF_ETPU_ECISR_CIS21             (0x00200000)
-#define MCF_ETPU_ECISR_CIS22             (0x00400000)
-#define MCF_ETPU_ECISR_CIS23             (0x00800000)
-#define MCF_ETPU_ECISR_CIS24             (0x01000000)
-#define MCF_ETPU_ECISR_CIS25             (0x02000000)
-#define MCF_ETPU_ECISR_CIS26             (0x04000000)
-#define MCF_ETPU_ECISR_CIS27             (0x08000000)
-#define MCF_ETPU_ECISR_CIS28             (0x10000000)
-#define MCF_ETPU_ECISR_CIS29             (0x20000000)
-#define MCF_ETPU_ECISR_CIS30             (0x40000000)
-#define MCF_ETPU_ECISR_CIS31             (0x80000000)
-
-/* Bit definitions and macros for MCF_ETPU_ECDTRSR */
-#define MCF_ETPU_ECDTRSR_DTRS0           (0x00000001)
-#define MCF_ETPU_ECDTRSR_DTRS1           (0x00000002)
-#define MCF_ETPU_ECDTRSR_DTRS2           (0x00000004)
-#define MCF_ETPU_ECDTRSR_DTRS3           (0x00000008)
-#define MCF_ETPU_ECDTRSR_DTRS4           (0x00000010)
-#define MCF_ETPU_ECDTRSR_DTRS5           (0x00000020)
-#define MCF_ETPU_ECDTRSR_DTRS6           (0x00000040)
-#define MCF_ETPU_ECDTRSR_DTRS7           (0x00000080)
-#define MCF_ETPU_ECDTRSR_DTRS8           (0x00000100)
-#define MCF_ETPU_ECDTRSR_DTRS9           (0x00000200)
-#define MCF_ETPU_ECDTRSR_DTRS10          (0x00000400)
-#define MCF_ETPU_ECDTRSR_DTRS11          (0x00000800)
-#define MCF_ETPU_ECDTRSR_DTRS12          (0x00001000)
-#define MCF_ETPU_ECDTRSR_DTRS13          (0x00002000)
-#define MCF_ETPU_ECDTRSR_DTRS14          (0x00004000)
-#define MCF_ETPU_ECDTRSR_DTRS15          (0x00008000)
-#define MCF_ETPU_ECDTRSR_DTRS16          (0x00010000)
-#define MCF_ETPU_ECDTRSR_DTRS17          (0x00020000)
-#define MCF_ETPU_ECDTRSR_DTRS18          (0x00040000)
-#define MCF_ETPU_ECDTRSR_DTRS19          (0x00080000)
-#define MCF_ETPU_ECDTRSR_DTRS20          (0x00100000)
-#define MCF_ETPU_ECDTRSR_DTRS21          (0x00200000)
-#define MCF_ETPU_ECDTRSR_DTRS22          (0x00400000)
-#define MCF_ETPU_ECDTRSR_DTRS23          (0x00800000)
-#define MCF_ETPU_ECDTRSR_DTRS24          (0x01000000)
-#define MCF_ETPU_ECDTRSR_DTRS25          (0x02000000)
-#define MCF_ETPU_ECDTRSR_DTRS26          (0x04000000)
-#define MCF_ETPU_ECDTRSR_DTRS27          (0x08000000)
-#define MCF_ETPU_ECDTRSR_DTRS28          (0x10000000)
-#define MCF_ETPU_ECDTRSR_DTRS29          (0x20000000)
-#define MCF_ETPU_ECDTRSR_DTRS30          (0x40000000)
-#define MCF_ETPU_ECDTRSR_DTRS31          (0x80000000)
-
-/* Bit definitions and macros for MCF_ETPU_ECIOSR */
-#define MCF_ETPU_ECIOSR_CIOS0            (0x00000001)
-#define MCF_ETPU_ECIOSR_CIOS1            (0x00000002)
-#define MCF_ETPU_ECIOSR_CIOS2            (0x00000004)
-#define MCF_ETPU_ECIOSR_CIOS3            (0x00000008)
-#define MCF_ETPU_ECIOSR_CIOS4            (0x00000010)
-#define MCF_ETPU_ECIOSR_CIOS5            (0x00000020)
-#define MCF_ETPU_ECIOSR_CIOS6            (0x00000040)
-#define MCF_ETPU_ECIOSR_CIOS7            (0x00000080)
-#define MCF_ETPU_ECIOSR_CIOS8            (0x00000100)
-#define MCF_ETPU_ECIOSR_CIOS9            (0x00000200)
-#define MCF_ETPU_ECIOSR_CIOS10           (0x00000400)
-#define MCF_ETPU_ECIOSR_CIOS11           (0x00000800)
-#define MCF_ETPU_ECIOSR_CIOS12           (0x00001000)
-#define MCF_ETPU_ECIOSR_CIOS13           (0x00002000)
-#define MCF_ETPU_ECIOSR_CIOS14           (0x00004000)
-#define MCF_ETPU_ECIOSR_CIOS15           (0x00008000)
-#define MCF_ETPU_ECIOSR_CIOS16           (0x00010000)
-#define MCF_ETPU_ECIOSR_CIOS17           (0x00020000)
-#define MCF_ETPU_ECIOSR_CIOS18           (0x00040000)
-#define MCF_ETPU_ECIOSR_CIOS19           (0x00080000)
-#define MCF_ETPU_ECIOSR_CIOS20           (0x00100000)
-#define MCF_ETPU_ECIOSR_CIOS21           (0x00200000)
-#define MCF_ETPU_ECIOSR_CIOS22           (0x00400000)
-#define MCF_ETPU_ECIOSR_CIOS23           (0x00800000)
-#define MCF_ETPU_ECIOSR_CIOS24           (0x01000000)
-#define MCF_ETPU_ECIOSR_CIOS25           (0x02000000)
-#define MCF_ETPU_ECIOSR_CIOS26           (0x04000000)
-#define MCF_ETPU_ECIOSR_CIOS27           (0x08000000)
-#define MCF_ETPU_ECIOSR_CIOS28           (0x10000000)
-#define MCF_ETPU_ECIOSR_CIOS29           (0x20000000)
-#define MCF_ETPU_ECIOSR_CIOS30           (0x40000000)
-#define MCF_ETPU_ECIOSR_CIOS31           (0x80000000)
-
-/* Bit definitions and macros for MCF_ETPU_ECDTROSR */
-#define MCF_ETPU_ECDTROSR_DTROS0         (0x00000001)
-#define MCF_ETPU_ECDTROSR_DTROS1         (0x00000002)
-#define MCF_ETPU_ECDTROSR_DTROS2         (0x00000004)
-#define MCF_ETPU_ECDTROSR_DTROS3         (0x00000008)
-#define MCF_ETPU_ECDTROSR_DTROS4         (0x00000010)
-#define MCF_ETPU_ECDTROSR_DTROS5         (0x00000020)
-#define MCF_ETPU_ECDTROSR_DTROS6         (0x00000040)
-#define MCF_ETPU_ECDTROSR_DTROS7         (0x00000080)
-#define MCF_ETPU_ECDTROSR_DTROS8         (0x00000100)
-#define MCF_ETPU_ECDTROSR_DTROS9         (0x00000200)
-#define MCF_ETPU_ECDTROSR_DTROS10        (0x00000400)
-#define MCF_ETPU_ECDTROSR_DTROS11        (0x00000800)
-#define MCF_ETPU_ECDTROSR_DTROS12        (0x00001000)
-#define MCF_ETPU_ECDTROSR_DTROS13        (0x00002000)
-#define MCF_ETPU_ECDTROSR_DTROS14        (0x00004000)
-#define MCF_ETPU_ECDTROSR_DTROS15        (0x00008000)
-#define MCF_ETPU_ECDTROSR_DTROS16        (0x00010000)
-#define MCF_ETPU_ECDTROSR_DTROS17        (0x00020000)
-#define MCF_ETPU_ECDTROSR_DTROS18        (0x00040000)
-#define MCF_ETPU_ECDTROSR_DTROS19        (0x00080000)
-#define MCF_ETPU_ECDTROSR_DTROS20        (0x00100000)
-#define MCF_ETPU_ECDTROSR_DTROS21        (0x00200000)
-#define MCF_ETPU_ECDTROSR_DTROS22        (0x00400000)
-#define MCF_ETPU_ECDTROSR_DTROS23        (0x00800000)
-#define MCF_ETPU_ECDTROSR_DTROS24        (0x01000000)
-#define MCF_ETPU_ECDTROSR_DTROS25        (0x02000000)
-#define MCF_ETPU_ECDTROSR_DTROS26        (0x04000000)
-#define MCF_ETPU_ECDTROSR_DTROS27        (0x08000000)
-#define MCF_ETPU_ECDTROSR_DTROS28        (0x10000000)
-#define MCF_ETPU_ECDTROSR_DTROS29        (0x20000000)
-#define MCF_ETPU_ECDTROSR_DTROS30        (0x40000000)
-#define MCF_ETPU_ECDTROSR_DTROS31        (0x80000000)
-
-/* Bit definitions and macros for MCF_ETPU_ECIER */
-#define MCF_ETPU_ECIER_CIE0              (0x00000001)
-#define MCF_ETPU_ECIER_CIE1              (0x00000002)
-#define MCF_ETPU_ECIER_CIE2              (0x00000004)
-#define MCF_ETPU_ECIER_CIE3              (0x00000008)
-#define MCF_ETPU_ECIER_CIE4              (0x00000010)
-#define MCF_ETPU_ECIER_CIE5              (0x00000020)
-#define MCF_ETPU_ECIER_CIE6              (0x00000040)
-#define MCF_ETPU_ECIER_CIE7              (0x00000080)
-#define MCF_ETPU_ECIER_CIE8              (0x00000100)
-#define MCF_ETPU_ECIER_CIE9              (0x00000200)
-#define MCF_ETPU_ECIER_CIE10             (0x00000400)
-#define MCF_ETPU_ECIER_CIE11             (0x00000800)
-#define MCF_ETPU_ECIER_CIE12             (0x00001000)
-#define MCF_ETPU_ECIER_CIE13             (0x00002000)
-#define MCF_ETPU_ECIER_CIE14             (0x00004000)
-#define MCF_ETPU_ECIER_CIE15             (0x00008000)
-#define MCF_ETPU_ECIER_CIE16             (0x00010000)
-#define MCF_ETPU_ECIER_CIE17             (0x00020000)
-#define MCF_ETPU_ECIER_CIE18             (0x00040000)
-#define MCF_ETPU_ECIER_CIE19             (0x00080000)
-#define MCF_ETPU_ECIER_CIE20             (0x00100000)
-#define MCF_ETPU_ECIER_CIE21             (0x00200000)
-#define MCF_ETPU_ECIER_CIE22             (0x00400000)
-#define MCF_ETPU_ECIER_CIE23             (0x00800000)
-#define MCF_ETPU_ECIER_CIE24             (0x01000000)
-#define MCF_ETPU_ECIER_CIE25             (0x02000000)
-#define MCF_ETPU_ECIER_CIE26             (0x04000000)
-#define MCF_ETPU_ECIER_CIE27             (0x08000000)
-#define MCF_ETPU_ECIER_CIE28             (0x10000000)
-#define MCF_ETPU_ECIER_CIE29             (0x20000000)
-#define MCF_ETPU_ECIER_CIE30             (0x40000000)
-#define MCF_ETPU_ECIER_CIE31             (0x80000000)
-
-/* Bit definitions and macros for MCF_ETPU_ECDTRER */
-#define MCF_ETPU_ECDTRER_DTRE0           (0x00000001)
-#define MCF_ETPU_ECDTRER_DTRE1           (0x00000002)
-#define MCF_ETPU_ECDTRER_DTRE2           (0x00000004)
-#define MCF_ETPU_ECDTRER_DTRE3           (0x00000008)
-#define MCF_ETPU_ECDTRER_DTRE4           (0x00000010)
-#define MCF_ETPU_ECDTRER_DTRE5           (0x00000020)
-#define MCF_ETPU_ECDTRER_DTRE6           (0x00000040)
-#define MCF_ETPU_ECDTRER_DTRE7           (0x00000080)
-#define MCF_ETPU_ECDTRER_DTRE8           (0x00000100)
-#define MCF_ETPU_ECDTRER_DTRE9           (0x00000200)
-#define MCF_ETPU_ECDTRER_DTRE10          (0x00000400)
-#define MCF_ETPU_ECDTRER_DTRE11          (0x00000800)
-#define MCF_ETPU_ECDTRER_DTRE12          (0x00001000)
-#define MCF_ETPU_ECDTRER_DTRE13          (0x00002000)
-#define MCF_ETPU_ECDTRER_DTRE14          (0x00004000)
-#define MCF_ETPU_ECDTRER_DTRE15          (0x00008000)
-#define MCF_ETPU_ECDTRER_DTRE16          (0x00010000)
-#define MCF_ETPU_ECDTRER_DTRE17          (0x00020000)
-#define MCF_ETPU_ECDTRER_DTRE18          (0x00040000)
-#define MCF_ETPU_ECDTRER_DTRE19          (0x00080000)
-#define MCF_ETPU_ECDTRER_DTRE20          (0x00100000)
-#define MCF_ETPU_ECDTRER_DTRE21          (0x00200000)
-#define MCF_ETPU_ECDTRER_DTRE22          (0x00400000)
-#define MCF_ETPU_ECDTRER_DTRE23          (0x00800000)
-#define MCF_ETPU_ECDTRER_DTRE24          (0x01000000)
-#define MCF_ETPU_ECDTRER_DTRE25          (0x02000000)
-#define MCF_ETPU_ECDTRER_DTRE26          (0x04000000)
-#define MCF_ETPU_ECDTRER_DTRE27          (0x08000000)
-#define MCF_ETPU_ECDTRER_DTRE28          (0x10000000)
-#define MCF_ETPU_ECDTRER_DTRE29          (0x20000000)
-#define MCF_ETPU_ECDTRER_DTRE30          (0x40000000)
-#define MCF_ETPU_ECDTRER_DTRE31          (0x80000000)
-
-/* Bit definitions and macros for MCF_ETPU_ECPSSR */
-#define MCF_ETPU_ECPSSR_SR0              (0x00000001)
-#define MCF_ETPU_ECPSSR_SR1              (0x00000002)
-#define MCF_ETPU_ECPSSR_SR2              (0x00000004)
-#define MCF_ETPU_ECPSSR_SR3              (0x00000008)
-#define MCF_ETPU_ECPSSR_SR4              (0x00000010)
-#define MCF_ETPU_ECPSSR_SR5              (0x00000020)
-#define MCF_ETPU_ECPSSR_SR6              (0x00000040)
-#define MCF_ETPU_ECPSSR_SR7              (0x00000080)
-#define MCF_ETPU_ECPSSR_SR8              (0x00000100)
-#define MCF_ETPU_ECPSSR_SR9              (0x00000200)
-#define MCF_ETPU_ECPSSR_SR10             (0x00000400)
-#define MCF_ETPU_ECPSSR_SR11             (0x00000800)
-#define MCF_ETPU_ECPSSR_SR12             (0x00001000)
-#define MCF_ETPU_ECPSSR_SR13             (0x00002000)
-#define MCF_ETPU_ECPSSR_SR14             (0x00004000)
-#define MCF_ETPU_ECPSSR_SR15             (0x00008000)
-#define MCF_ETPU_ECPSSR_SR16             (0x00010000)
-#define MCF_ETPU_ECPSSR_SR17             (0x00020000)
-#define MCF_ETPU_ECPSSR_SR18             (0x00040000)
-#define MCF_ETPU_ECPSSR_SR19             (0x00080000)
-#define MCF_ETPU_ECPSSR_SR20             (0x00100000)
-#define MCF_ETPU_ECPSSR_SR21             (0x00200000)
-#define MCF_ETPU_ECPSSR_SR22             (0x00400000)
-#define MCF_ETPU_ECPSSR_SR23             (0x00800000)
-#define MCF_ETPU_ECPSSR_SR24             (0x01000000)
-#define MCF_ETPU_ECPSSR_SR25             (0x02000000)
-#define MCF_ETPU_ECPSSR_SR26             (0x04000000)
-#define MCF_ETPU_ECPSSR_SR27             (0x08000000)
-#define MCF_ETPU_ECPSSR_SR28             (0x10000000)
-#define MCF_ETPU_ECPSSR_SR29             (0x20000000)
-#define MCF_ETPU_ECPSSR_SR30             (0x40000000)
-#define MCF_ETPU_ECPSSR_SR31             (0x80000000)
-
-/* Bit definitions and macros for MCF_ETPU_ECSSR */
-#define MCF_ETPU_ECSSR_SS0               (0x00000001)
-#define MCF_ETPU_ECSSR_SS1               (0x00000002)
-#define MCF_ETPU_ECSSR_SS2               (0x00000004)
-#define MCF_ETPU_ECSSR_SS3               (0x00000008)
-#define MCF_ETPU_ECSSR_SS4               (0x00000010)
-#define MCF_ETPU_ECSSR_SS5               (0x00000020)
-#define MCF_ETPU_ECSSR_SS6               (0x00000040)
-#define MCF_ETPU_ECSSR_SS7               (0x00000080)
-#define MCF_ETPU_ECSSR_SS8               (0x00000100)
-#define MCF_ETPU_ECSSR_SS9               (0x00000200)
-#define MCF_ETPU_ECSSR_SS10              (0x00000400)
-#define MCF_ETPU_ECSSR_SS11              (0x00000800)
-#define MCF_ETPU_ECSSR_SS12              (0x00001000)
-#define MCF_ETPU_ECSSR_SS13              (0x00002000)
-#define MCF_ETPU_ECSSR_SS14              (0x00004000)
-#define MCF_ETPU_ECSSR_SS15              (0x00008000)
-#define MCF_ETPU_ECSSR_SS16              (0x00010000)
-#define MCF_ETPU_ECSSR_SS17              (0x00020000)
-#define MCF_ETPU_ECSSR_SS18              (0x00040000)
-#define MCF_ETPU_ECSSR_SS19              (0x00080000)
-#define MCF_ETPU_ECSSR_SS20              (0x00100000)
-#define MCF_ETPU_ECSSR_SS21              (0x00200000)
-#define MCF_ETPU_ECSSR_SS22              (0x00400000)
-#define MCF_ETPU_ECSSR_SS23              (0x00800000)
-#define MCF_ETPU_ECSSR_SS24              (0x01000000)
-#define MCF_ETPU_ECSSR_SS25              (0x02000000)
-#define MCF_ETPU_ECSSR_SS26              (0x04000000)
-#define MCF_ETPU_ECSSR_SS27              (0x08000000)
-#define MCF_ETPU_ECSSR_SS28              (0x10000000)
-#define MCF_ETPU_ECSSR_SS29              (0x20000000)
-#define MCF_ETPU_ECSSR_SS30              (0x40000000)
-#define MCF_ETPU_ECSSR_SS31              (0x80000000)
-
-/* Bit definitions and macros for MCF_ETPU_ECnSCR */
-#define MCF_ETPU_ECnSCR_FM(x)            (((x)&0x00000003)<<0)
-#define MCF_ETPU_ECnSCR_OBE              (0x00002000)
-#define MCF_ETPU_ECnSCR_OPS              (0x00004000)
-#define MCF_ETPU_ECnSCR_IPS              (0x00008000)
-#define MCF_ETPU_ECnSCR_DTROS            (0x00400000)
-#define MCF_ETPU_ECnSCR_DTRS             (0x00800000)
-#define MCF_ETPU_ECnSCR_CIOS             (0x40000000)
-#define MCF_ETPU_ECnSCR_CIS              (0x80000000)
-
-/* Bit definitions and macros for MCF_ETPU_ECnCR */
-#define MCF_ETPU_ECnCR_CPBA(x)           (((x)&0x000007FF)<<0)
-#define MCF_ETPU_ECnCR_OPOL              (0x00004000)
-#define MCF_ETPU_ECnCR_ODIS              (0x00008000)
-#define MCF_ETPU_ECnCR_CFS(x)            (((x)&0x0000001F)<<16)
-#define MCF_ETPU_ECnCR_ETCS              (0x01000000)
-#define MCF_ETPU_ECnCR_CPR(x)            (((x)&0x00000003)<<28)
-#define MCF_ETPU_ECnCR_DTRE              (0x40000000)
-#define MCF_ETPU_ECnCR_CIE               (0x80000000)
-
-/* Bit definitions and macros for MCF_ETPU_ECnHSSR */
-#define MCF_ETPU_ECnHSSR_HSR(x)          (((x)&0x00000007)<<0)
-
-/********************************************************************/
-
-#endif /* __MCF523X_ETPU_H__ */
diff --git a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_fec.h b/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_fec.h
deleted file mode 100644
index 2b20a153f..000000000
--- a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_fec.h
+++ /dev/null
@@ -1,208 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly 
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file 
- * LICENSE_FREESCALE.TXT.
- *
- * File:	mcf523x_fec.h
- * Purpose:	Register and bit definitions for the MCF523X
- *
- * Notes:	
- *	
- */
-
-#ifndef __MCF523X_FEC_H__
-#define __MCF523X_FEC_H__
-
-/*********************************************************************
-*
-* Fast Ethernet Controller (FEC)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_FEC_EIR                   (*(vuint32*)(void*)(&__IPSBAR[0x001004]))
-#define MCF_FEC_EIMR                  (*(vuint32*)(void*)(&__IPSBAR[0x001008]))
-#define MCF_FEC_RDAR                  (*(vuint32*)(void*)(&__IPSBAR[0x001010]))
-#define MCF_FEC_TDAR                  (*(vuint32*)(void*)(&__IPSBAR[0x001014]))
-#define MCF_FEC_ECR                   (*(vuint32*)(void*)(&__IPSBAR[0x001024]))
-#define MCF_FEC_MMFR                  (*(vuint32*)(void*)(&__IPSBAR[0x001040]))
-#define MCF_FEC_MSCR                  (*(vuint32*)(void*)(&__IPSBAR[0x001044]))
-#define MCF_FEC_MIBC                  (*(vuint32*)(void*)(&__IPSBAR[0x001064]))
-#define MCF_FEC_RCR                   (*(vuint32*)(void*)(&__IPSBAR[0x001084]))
-#define MCF_FEC_TCR                   (*(vuint32*)(void*)(&__IPSBAR[0x0010C4]))
-#define MCF_FEC_PALR                  (*(vuint32*)(void*)(&__IPSBAR[0x0010E4]))
-#define MCF_FEC_PAUR                  (*(vuint32*)(void*)(&__IPSBAR[0x0010E8]))
-#define MCF_FEC_OPD                   (*(vuint32*)(void*)(&__IPSBAR[0x0010EC]))
-#define MCF_FEC_IAUR                  (*(vuint32*)(void*)(&__IPSBAR[0x001118]))
-#define MCF_FEC_IALR                  (*(vuint32*)(void*)(&__IPSBAR[0x00111C]))
-#define MCF_FEC_GAUR                  (*(vuint32*)(void*)(&__IPSBAR[0x001120]))
-#define MCF_FEC_GALR                  (*(vuint32*)(void*)(&__IPSBAR[0x001124]))
-#define MCF_FEC_TFWR                  (*(vuint32*)(void*)(&__IPSBAR[0x001144]))
-#define MCF_FEC_FRBR                  (*(vuint32*)(void*)(&__IPSBAR[0x00114C]))
-#define MCF_FEC_FRSR                  (*(vuint32*)(void*)(&__IPSBAR[0x001150]))
-#define MCF_FEC_ERDSR                 (*(vuint32*)(void*)(&__IPSBAR[0x001180]))
-#define MCF_FEC_ETDSR                 (*(vuint32*)(void*)(&__IPSBAR[0x001184]))
-#define MCF_FEC_EMRBR                 (*(vuint32*)(void*)(&__IPSBAR[0x001188]))
-#define MCF_FEC_RMON_T_DROP           (*(vuint32*)(void*)(&__IPSBAR[0x001200]))
-#define MCF_FEC_RMON_T_PACKETS        (*(vuint32*)(void*)(&__IPSBAR[0x001204]))
-#define MCF_FEC_RMON_T_BC_PKT         (*(vuint32*)(void*)(&__IPSBAR[0x001208]))
-#define MCF_FEC_RMON_T_MC_PKT         (*(vuint32*)(void*)(&__IPSBAR[0x00120C]))
-#define MCF_FEC_RMON_T_CRC_ALIGN      (*(vuint32*)(void*)(&__IPSBAR[0x001210]))
-#define MCF_FEC_RMON_T_UNDERSIZE      (*(vuint32*)(void*)(&__IPSBAR[0x001214]))
-#define MCF_FEC_RMON_T_OVERSIZE       (*(vuint32*)(void*)(&__IPSBAR[0x001218]))
-#define MCF_FEC_RMON_T_FRAG           (*(vuint32*)(void*)(&__IPSBAR[0x00121C]))
-#define MCF_FEC_RMON_T_JAB            (*(vuint32*)(void*)(&__IPSBAR[0x001220]))
-#define MCF_FEC_RMON_T_COL            (*(vuint32*)(void*)(&__IPSBAR[0x001224]))
-#define MCF_FEC_RMON_T_P64            (*(vuint32*)(void*)(&__IPSBAR[0x001228]))
-#define MCF_FEC_RMON_T_P65TO127       (*(vuint32*)(void*)(&__IPSBAR[0x00122C]))
-#define MCF_FEC_RMON_T_P128TO255      (*(vuint32*)(void*)(&__IPSBAR[0x001230]))
-#define MCF_FEC_RMON_T_P256TO511      (*(vuint32*)(void*)(&__IPSBAR[0x001234]))
-#define MCF_FEC_RMON_T_P512TO1023     (*(vuint32*)(void*)(&__IPSBAR[0x001238]))
-#define MCF_FEC_RMON_T_P1024TO2047    (*(vuint32*)(void*)(&__IPSBAR[0x00123C]))
-#define MCF_FEC_RMON_T_P_GTE2048      (*(vuint32*)(void*)(&__IPSBAR[0x001240]))
-#define MCF_FEC_RMON_T_OCTETS         (*(vuint32*)(void*)(&__IPSBAR[0x001244]))
-#define MCF_FEC_IEEE_T_DROP           (*(vuint32*)(void*)(&__IPSBAR[0x001248]))
-#define MCF_FEC_IEEE_T_FRAME_OK       (*(vuint32*)(void*)(&__IPSBAR[0x00124C]))
-#define MCF_FEC_IEEE_T_1COL           (*(vuint32*)(void*)(&__IPSBAR[0x001250]))
-#define MCF_FEC_IEEE_T_MCOL           (*(vuint32*)(void*)(&__IPSBAR[0x001254]))
-#define MCF_FEC_IEEE_T_DEF            (*(vuint32*)(void*)(&__IPSBAR[0x001258]))
-#define MCF_FEC_IEEE_T_LCOL           (*(vuint32*)(void*)(&__IPSBAR[0x00125C]))
-#define MCF_FEC_IEEE_T_EXCOL          (*(vuint32*)(void*)(&__IPSBAR[0x001260]))
-#define MCF_FEC_IEEE_T_MACERR         (*(vuint32*)(void*)(&__IPSBAR[0x001264]))
-#define MCF_FEC_IEEE_T_CSERR          (*(vuint32*)(void*)(&__IPSBAR[0x001268]))
-#define MCF_FEC_IEEE_T_SQE            (*(vuint32*)(void*)(&__IPSBAR[0x00126C]))
-#define MCF_FEC_IEEE_T_FDXFC          (*(vuint32*)(void*)(&__IPSBAR[0x001270]))
-#define MCF_FEC_IEEE_T_OCTETS_OK      (*(vuint32*)(void*)(&__IPSBAR[0x001274]))
-#define MCF_FEC_RMON_R_PACKETS        (*(vuint32*)(void*)(&__IPSBAR[0x001284]))
-#define MCF_FEC_RMON_R_BC_PKT         (*(vuint32*)(void*)(&__IPSBAR[0x001288]))
-#define MCF_FEC_RMON_R_MC_PKT         (*(vuint32*)(void*)(&__IPSBAR[0x00128C]))
-#define MCF_FEC_RMON_R_CRC_ALIGN      (*(vuint32*)(void*)(&__IPSBAR[0x001290]))
-#define MCF_FEC_RMON_R_UNDERSIZE      (*(vuint32*)(void*)(&__IPSBAR[0x001294]))
-#define MCF_FEC_RMON_R_OVERSIZE       (*(vuint32*)(void*)(&__IPSBAR[0x001298]))
-#define MCF_FEC_RMON_R_FRAG           (*(vuint32*)(void*)(&__IPSBAR[0x00129C]))
-#define MCF_FEC_RMON_R_JAB            (*(vuint32*)(void*)(&__IPSBAR[0x0012A0]))
-#define MCF_FEC_RMON_R_RESVD_0        (*(vuint32*)(void*)(&__IPSBAR[0x0012A4]))
-#define MCF_FEC_RMON_R_P64            (*(vuint32*)(void*)(&__IPSBAR[0x0012A8]))
-#define MCF_FEC_RMON_R_P65TO127       (*(vuint32*)(void*)(&__IPSBAR[0x0012AC]))
-#define MCF_FEC_RMON_R_P128TO255      (*(vuint32*)(void*)(&__IPSBAR[0x0012B0]))
-#define MCF_FEC_RMON_R_P256TO511      (*(vuint32*)(void*)(&__IPSBAR[0x0012B4]))
-#define MCF_FEC_RMON_R_512TO1023      (*(vuint32*)(void*)(&__IPSBAR[0x0012B8]))
-#define MCF_FEC_RMON_R_P_GTE2048      (*(vuint32*)(void*)(&__IPSBAR[0x0012C0]))
-#define MCF_FEC_RMON_R_1024TO2047     (*(vuint32*)(void*)(&__IPSBAR[0x0012BC]))
-#define MCF_FEC_RMON_R_OCTETS         (*(vuint32*)(void*)(&__IPSBAR[0x0012C4]))
-#define MCF_FEC_IEEE_R_DROP           (*(vuint32*)(void*)(&__IPSBAR[0x0012C8]))
-#define MCF_FEC_IEEE_R_FRAME_OK       (*(vuint32*)(void*)(&__IPSBAR[0x0012CC]))
-#define MCF_FEC_IEEE_R_CRC            (*(vuint32*)(void*)(&__IPSBAR[0x0012D0]))
-#define MCF_FEC_IEEE_R_ALIGN          (*(vuint32*)(void*)(&__IPSBAR[0x0012D4]))
-#define MCF_FEC_IEEE_R_MACERR         (*(vuint32*)(void*)(&__IPSBAR[0x0012D8]))
-#define MCF_FEC_IEEE_R_FDXFC          (*(vuint32*)(void*)(&__IPSBAR[0x0012DC]))
-#define MCF_FEC_IEEE_R_OCTETS_OK      (*(vuint32*)(void*)(&__IPSBAR[0x0012E0]))
-
-/* Bit definitions and macros for MCF_FEC_EIR */
-#define MCF_FEC_EIR_UN                  (0x00080000)
-#define MCF_FEC_EIR_RL                  (0x00100000)
-#define MCF_FEC_EIR_LC                  (0x00200000)
-#define MCF_FEC_EIR_EBERR               (0x00400000)
-#define MCF_FEC_EIR_MII                 (0x00800000)
-#define MCF_FEC_EIR_RXB                 (0x01000000)
-#define MCF_FEC_EIR_RXF                 (0x02000000)
-#define MCF_FEC_EIR_TXB                 (0x04000000)
-#define MCF_FEC_EIR_TXF                 (0x08000000)
-#define MCF_FEC_EIR_GRA                 (0x10000000)
-#define MCF_FEC_EIR_BABT                (0x20000000)
-#define MCF_FEC_EIR_BABR                (0x40000000)
-#define MCF_FEC_EIR_HBERR               (0x80000000)
-
-/* Bit definitions and macros for MCF_FEC_EIMR */
-#define MCF_FEC_EIMR_UN                 (0x00080000)
-#define MCF_FEC_EIMR_RL                 (0x00100000)
-#define MCF_FEC_EIMR_LC                 (0x00200000)
-#define MCF_FEC_EIMR_EBERR              (0x00400000)
-#define MCF_FEC_EIMR_MII                (0x00800000)
-#define MCF_FEC_EIMR_RXB                (0x01000000)
-#define MCF_FEC_EIMR_RXF                (0x02000000)
-#define MCF_FEC_EIMR_TXB                (0x04000000)
-#define MCF_FEC_EIMR_TXF                (0x08000000)
-#define MCF_FEC_EIMR_GRA                (0x10000000)
-#define MCF_FEC_EIMR_BABT               (0x20000000)
-#define MCF_FEC_EIMR_BABR               (0x40000000)
-#define MCF_FEC_EIMR_HBERR              (0x80000000)
-
-/* Bit definitions and macros for MCF_FEC_RDAR */
-#define MCF_FEC_RDAR_R_DES_ACTIVE       (0x01000000)
-
-/* Bit definitions and macros for MCF_FEC_TDAR */
-#define MCF_FEC_TDAR_X_DES_ACTIVE       (0x01000000)
-
-/* Bit definitions and macros for MCF_FEC_ECR */
-#define MCF_FEC_ECR_RESET               (0x00000001)
-#define MCF_FEC_ECR_ETHER_EN            (0x00000002)
-
-/* Bit definitions and macros for MCF_FEC_MMFR */
-#define MCF_FEC_MMFR_DATA(x)            (((x)&0x0000FFFF)<<0)
-#define MCF_FEC_MMFR_TA(x)              (((x)&0x00000003)<<16)
-#define MCF_FEC_MMFR_RA(x)              (((x)&0x0000001F)<<18)
-#define MCF_FEC_MMFR_PA(x)              (((x)&0x0000001F)<<23)
-#define MCF_FEC_MMFR_OP(x)              (((x)&0x00000003)<<28)
-#define MCF_FEC_MMFR_ST(x)              (((x)&0x00000003)<<30)
-#define MCF_FEC_MMFR_ST_01             (0x40000000)
-#define MCF_FEC_MMFR_OP_READ           (0x20000000)
-#define MCF_FEC_MMFR_OP_WRITE          (0x10000000)
-#define MCF_FEC_MMFR_TA_10             (0x00020000)
-
-
-/* Bit definitions and macros for MCF_FEC_MSCR */
-#define MCF_FEC_MSCR_MII_SPEED(x)       (((x)&0x0000003F)<<1)
-#define MCF_FEC_MSCR_DIS_PREAMBLE       (0x00000080)
-
-/* Bit definitions and macros for MCF_FEC_MIBC */
-#define MCF_FEC_MIBC_MIB_IDLE           (0x40000000)
-#define MCF_FEC_MIBC_MIB_DISABLE        (0x80000000)
-
-/* Bit definitions and macros for MCF_FEC_RCR */
-#define MCF_FEC_RCR_LOOP                (0x00000001)
-#define MCF_FEC_RCR_DRT                 (0x00000002)
-#define MCF_FEC_RCR_MII_MODE            (0x00000004)
-#define MCF_FEC_RCR_PROM                (0x00000008)
-#define MCF_FEC_RCR_BC_REJ              (0x00000010)
-#define MCF_FEC_RCR_FCE                 (0x00000020)
-#define MCF_FEC_RCR_MAX_FL(x)           (((x)&0x000007FF)<<16)
-
-/* Bit definitions and macros for MCF_FEC_TCR */
-#define MCF_FEC_TCR_GTS                 (0x00000001)
-#define MCF_FEC_TCR_HBC                 (0x00000002)
-#define MCF_FEC_TCR_FDEN                (0x00000004)
-#define MCF_FEC_TCR_TFC_PAUSE           (0x00000008)
-#define MCF_FEC_TCR_RFC_PAUSE           (0x00000010)
-
-/* Bit definitions and macros for MCF_FEC_PAUR */
-#define MCF_FEC_PAUR_TYPE(x)            (((x)&0x0000FFFF)<<0)
-#define MCF_FEC_PAUR_PADDR2(x)          (((x)&0x0000FFFF)<<16)
-
-/* Bit definitions and macros for MCF_FEC_OPD */
-#define MCF_FEC_OPD_PAUSE_DUR(x)        (((x)&0x0000FFFF)<<0)
-#define MCF_FEC_OPD_OPCODE(x)           (((x)&0x0000FFFF)<<16)
-
-/* Bit definitions and macros for MCF_FEC_TFWR */
-#define MCF_FEC_TFWR_X_WMRK(x)          (((x)&0x00000003)<<0)
-
-/* Bit definitions and macros for MCF_FEC_FRBR */
-#define MCF_FEC_FRBR_R_BOUND(x)         (((x)&0x000000FF)<<2)
-
-/* Bit definitions and macros for MCF_FEC_FRSR */
-#define MCF_FEC_FRSR_R_FSTART(x)        (((x)&0x000000FF)<<2)
-
-/* Bit definitions and macros for MCF_FEC_ERDSR */
-#define MCF_FEC_ERDSR_R_DES_START(x)    (((x)&0x3FFFFFFF)<<2)
-
-/* Bit definitions and macros for MCF_FEC_ETDSR */
-#define MCF_FEC_ETDSR_X_DES_START(x)    (((x)&0x3FFFFFFF)<<2)
-
-/* Bit definitions and macros for MCF_FEC_EMRBR */
-#define MCF_FEC_EMRBR_R_BUF_SIZE(x)     (((x)&0x0000007F)<<4)
-
-/********************************************************************/
-
-#endif /* __MCF523X_FEC_H__ */
diff --git a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_fmpll.h b/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_fmpll.h
deleted file mode 100644
index d9dc941d4..000000000
--- a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_fmpll.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly 
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file 
- * LICENSE_FREESCALE.TXT.
- *
- * File:	mcf523x_fmpll.h
- * Purpose:	Register and bit definitions for the MCF523X
- *
- * Notes:	
- *	
- */
-
-#ifndef __MCF523X_FMPLL_H__
-#define __MCF523X_FMPLL_H__
-
-/*********************************************************************
-*
-* Frequency Modulated Phase Locked Loop (FMPLL)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_FMPLL_SYNCR    (*(vuint32*)(void*)(&__IPSBAR[0x120000]))
-#define MCF_FMPLL_SYNSR    (*(vuint32*)(void*)(&__IPSBAR[0x120004]))
-
-/* Bit definitions and macros for MCF_FMPLL_SYNCR */
-#define MCF_FMPLL_SYNCR_EXP(x)       (((x)&0x000003FF)<<0)
-#define MCF_FMPLL_SYNCR_DEPTH(x)     (((x)&0x00000003)<<10)
-#define MCF_FMPLL_SYNCR_RATE         (0x00001000)
-#define MCF_FMPLL_SYNCR_LOCIRQ       (0x00002000)
-#define MCF_FMPLL_SYNCR_LOLIRQ       (0x00004000)
-#define MCF_FMPLL_SYNCR_DISCLK       (0x00008000)
-#define MCF_FMPLL_SYNCR_LOCRE        (0x00010000)
-#define MCF_FMPLL_SYNCR_LOLRE        (0x00020000)
-#define MCF_FMPLL_SYNCR_LOCEN        (0x00040000)
-#define MCF_FMPLL_SYNCR_RFD(x)       (((x)&0x00000007)<<19)
-#define MCF_FMPLL_SYNCR_MFD(x)       (((x)&0x00000007)<<24)
-
-/* Bit definitions and macros for MCF_FMPLL_SYNSR */
-#define MCF_FMPLL_SYNSR_CALPASS      (0x00000001)
-#define MCF_FMPLL_SYNSR_CALDONE      (0x00000002)
-#define MCF_FMPLL_SYNSR_LOCF         (0x00000004)
-#define MCF_FMPLL_SYNSR_LOCK         (0x00000008)
-#define MCF_FMPLL_SYNSR_LOCKS        (0x00000010)
-#define MCF_FMPLL_SYNSR_PLLREF       (0x00000020)
-#define MCF_FMPLL_SYNSR_PLLSEL       (0x00000040)
-#define MCF_FMPLL_SYNSR_MODE         (0x00000080)
-#define MCF_FMPLL_SYNSR_LOC          (0x00000100)
-#define MCF_FMPLL_SYNSR_LOLF         (0x00000200)
-
-/********************************************************************/
-
-#endif /* __MCF523X_FMPLL_H__ */
diff --git a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_gpio.h b/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_gpio.h
deleted file mode 100644
index 455ac850d..000000000
--- a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_gpio.h
+++ /dev/null
@@ -1,676 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly 
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file 
- * LICENSE_FREESCALE.TXT.
- *
- * File:	mcf523x_gpio.h
- * Purpose:	Register and bit definitions for the MCF523X
- *
- * Notes:	
- *	
- */
-
-#ifndef __MCF523X_GPIO_H__
-#define __MCF523X_GPIO_H__
-
-/*********************************************************************
-*
-* General Purpose I/O (GPIO)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_GPIO_PODR_ADDR        (*(vuint8 *)(void*)(&__IPSBAR[0x100000]))
-#define MCF_GPIO_PODR_DATAH       (*(vuint8 *)(void*)(&__IPSBAR[0x100001]))
-#define MCF_GPIO_PODR_DATAL       (*(vuint8 *)(void*)(&__IPSBAR[0x100002]))
-#define MCF_GPIO_PODR_BUSCTL      (*(vuint8 *)(void*)(&__IPSBAR[0x100003]))
-#define MCF_GPIO_PODR_BS          (*(vuint8 *)(void*)(&__IPSBAR[0x100004]))
-#define MCF_GPIO_PODR_CS          (*(vuint8 *)(void*)(&__IPSBAR[0x100005]))
-#define MCF_GPIO_PODR_SDRAM       (*(vuint8 *)(void*)(&__IPSBAR[0x100006]))
-#define MCF_GPIO_PODR_FECI2C      (*(vuint8 *)(void*)(&__IPSBAR[0x100007]))
-#define MCF_GPIO_PODR_UARTH       (*(vuint8 *)(void*)(&__IPSBAR[0x100008]))
-#define MCF_GPIO_PODR_UARTL       (*(vuint8 *)(void*)(&__IPSBAR[0x100009]))
-#define MCF_GPIO_PODR_QSPI        (*(vuint8 *)(void*)(&__IPSBAR[0x10000A]))
-#define MCF_GPIO_PODR_TIMER       (*(vuint8 *)(void*)(&__IPSBAR[0x10000B]))
-#define MCF_GPIO_PODR_ETPU        (*(vuint8 *)(void*)(&__IPSBAR[0x10000C]))
-#define MCF_GPIO_PDDR_APDDR       (*(vuint8 *)(void*)(&__IPSBAR[0x100010]))
-#define MCF_GPIO_PDDR_DATAH       (*(vuint8 *)(void*)(&__IPSBAR[0x100011]))
-#define MCF_GPIO_PDDR_DATAL       (*(vuint8 *)(void*)(&__IPSBAR[0x100012]))
-#define MCF_GPIO_PDDR_BUSCTL      (*(vuint8 *)(void*)(&__IPSBAR[0x100013]))
-#define MCF_GPIO_PDDR_BS          (*(vuint8 *)(void*)(&__IPSBAR[0x100014]))
-#define MCF_GPIO_PDDR_CS          (*(vuint8 *)(void*)(&__IPSBAR[0x100015]))
-#define MCF_GPIO_PDDR_SDRAM       (*(vuint8 *)(void*)(&__IPSBAR[0x100016]))
-#define MCF_GPIO_PDDR_FECI2C      (*(vuint8 *)(void*)(&__IPSBAR[0x100017]))
-#define MCF_GPIO_PDDR_UARTH       (*(vuint8 *)(void*)(&__IPSBAR[0x100018]))
-#define MCF_GPIO_PDDR_UARTL       (*(vuint8 *)(void*)(&__IPSBAR[0x100019]))
-#define MCF_GPIO_PDDR_QSPI        (*(vuint8 *)(void*)(&__IPSBAR[0x10001A]))
-#define MCF_GPIO_PDDR_TIMER       (*(vuint8 *)(void*)(&__IPSBAR[0x10001B]))
-#define MCF_GPIO_PDDR_ETPU        (*(vuint8 *)(void*)(&__IPSBAR[0x10001C]))
-#define MCF_GPIO_PPDSDR_ADDR      (*(vuint8 *)(void*)(&__IPSBAR[0x100020]))
-#define MCF_GPIO_PPDSDR_DATAH     (*(vuint8 *)(void*)(&__IPSBAR[0x100021]))
-#define MCF_GPIO_PPDSDR_DATAL     (*(vuint8 *)(void*)(&__IPSBAR[0x100022]))
-#define MCF_GPIO_PPDSDR_BUSCTL    (*(vuint8 *)(void*)(&__IPSBAR[0x100023]))
-#define MCF_GPIO_PPDSDR_BS        (*(vuint8 *)(void*)(&__IPSBAR[0x100024]))
-#define MCF_GPIO_PPDSDR_FECI2C    (*(vuint8 *)(void*)(&__IPSBAR[0x100027]))
-#define MCF_GPIO_PPDSDR_CS        (*(vuint8 *)(void*)(&__IPSBAR[0x100025]))
-#define MCF_GPIO_PPDSDR_SDRAM     (*(vuint8 *)(void*)(&__IPSBAR[0x100026]))
-#define MCF_GPIO_PPDSDR_UARTH     (*(vuint8 *)(void*)(&__IPSBAR[0x100028]))
-#define MCF_GPIO_PPDSDR_UARTL     (*(vuint8 *)(void*)(&__IPSBAR[0x100029]))
-#define MCF_GPIO_PPDSDR_QSPI      (*(vuint8 *)(void*)(&__IPSBAR[0x10002A]))
-#define MCF_GPIO_PPDSDR_TIMER     (*(vuint8 *)(void*)(&__IPSBAR[0x10002B]))
-#define MCF_GPIO_PPDSDR_ETPU      (*(vuint8 *)(void*)(&__IPSBAR[0x10002C]))
-#define MCF_GPIO_PCLRR_ADDR       (*(vuint8 *)(void*)(&__IPSBAR[0x100030]))
-#define MCF_GPIO_PCLRR_DATAH      (*(vuint8 *)(void*)(&__IPSBAR[0x100031]))
-#define MCF_GPIO_PCLRR_DATAL      (*(vuint8 *)(void*)(&__IPSBAR[0x100032]))
-#define MCF_GPIO_PCLRR_BUSCTL     (*(vuint8 *)(void*)(&__IPSBAR[0x100033]))
-#define MCF_GPIO_PCLRR_BS         (*(vuint8 *)(void*)(&__IPSBAR[0x100034]))
-#define MCF_GPIO_PCLRR_CS         (*(vuint8 *)(void*)(&__IPSBAR[0x100035]))
-#define MCF_GPIO_PCLRR_SDRAM      (*(vuint8 *)(void*)(&__IPSBAR[0x100036]))
-#define MCF_GPIO_PCLRR_FECI2C     (*(vuint8 *)(void*)(&__IPSBAR[0x100037]))
-#define MCF_GPIO_PCLRR_UARTH      (*(vuint8 *)(void*)(&__IPSBAR[0x100038]))
-#define MCF_GPIO_PCLRR_UARTL      (*(vuint8 *)(void*)(&__IPSBAR[0x100039]))
-#define MCF_GPIO_PCLRR_QSPI       (*(vuint8 *)(void*)(&__IPSBAR[0x10003A]))
-#define MCF_GPIO_PCLRR_TIMER      (*(vuint8 *)(void*)(&__IPSBAR[0x10003B]))
-#define MCF_GPIO_PCLRR_ETPU       (*(vuint8 *)(void*)(&__IPSBAR[0x10003C]))
-#define MCF_GPIO_PAR_AD           (*(vuint8 *)(void*)(&__IPSBAR[0x100040]))
-#define MCF_GPIO_PAR_BUSCTL       (*(vuint16*)(void*)(&__IPSBAR[0x100042]))
-#define MCF_GPIO_PAR_BS           (*(vuint8 *)(void*)(&__IPSBAR[0x100044]))
-#define MCF_GPIO_PAR_CS           (*(vuint8 *)(void*)(&__IPSBAR[0x100045]))
-#define MCF_GPIO_PAR_SDRAM        (*(vuint8 *)(void*)(&__IPSBAR[0x100046]))
-#define MCF_GPIO_PAR_FECI2C       (*(vuint8 *)(void*)(&__IPSBAR[0x100047]))
-#define MCF_GPIO_PAR_UART         (*(vuint16*)(void*)(&__IPSBAR[0x100048]))
-#define MCF_GPIO_PAR_QSPI         (*(vuint8 *)(void*)(&__IPSBAR[0x10004A]))
-#define MCF_GPIO_PAR_TIMER        (*(vuint16*)(void*)(&__IPSBAR[0x10004C]))
-#define MCF_GPIO_PAR_ETPU         (*(vuint8 *)(void*)(&__IPSBAR[0x10004E]))
-#define MCF_GPIO_DSCR_EIM         (*(vuint8 *)(void*)(&__IPSBAR[0x100050]))
-#define MCF_GPIO_DSCR_ETPU        (*(vuint8 *)(void*)(&__IPSBAR[0x100051]))
-#define MCF_GPIO_DSCR_FECI2C      (*(vuint8 *)(void*)(&__IPSBAR[0x100052]))
-#define MCF_GPIO_DSCR_UART        (*(vuint8 *)(void*)(&__IPSBAR[0x100053]))
-#define MCF_GPIO_DSCR_QSPI        (*(vuint8 *)(void*)(&__IPSBAR[0x100054]))
-#define MCF_GPIO_DSCR_TIMER       (*(vuint8 *)(void*)(&__IPSBAR[0x100055]))
-
-/* Bit definitions and macros for MCF_GPIO_PODR_ADDR */
-#define MCF_GPIO_PODR_ADDR_PODR_ADDR5            (0x20)
-#define MCF_GPIO_PODR_ADDR_PODR_ADDR6            (0x40)
-#define MCF_GPIO_PODR_ADDR_PODR_ADDR7            (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PODR_DATAH */
-#define MCF_GPIO_PODR_DATAH_PODR_DATAH0          (0x01)
-#define MCF_GPIO_PODR_DATAH_PODR_DATAH1          (0x02)
-#define MCF_GPIO_PODR_DATAH_PODR_DATAH2          (0x04)
-#define MCF_GPIO_PODR_DATAH_PODR_DATAH3          (0x08)
-#define MCF_GPIO_PODR_DATAH_PODR_DATAH4          (0x10)
-#define MCF_GPIO_PODR_DATAH_PODR_DATAH5          (0x20)
-#define MCF_GPIO_PODR_DATAH_PODR_DATAH6          (0x40)
-#define MCF_GPIO_PODR_DATAH_PODR_DATAH7          (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PODR_DATAL */
-#define MCF_GPIO_PODR_DATAL_PODR_DATAL0          (0x01)
-#define MCF_GPIO_PODR_DATAL_PODR_DATAL1          (0x02)
-#define MCF_GPIO_PODR_DATAL_PODR_DATAL2          (0x04)
-#define MCF_GPIO_PODR_DATAL_PODR_DATAL3          (0x08)
-#define MCF_GPIO_PODR_DATAL_PODR_DATAL4          (0x10)
-#define MCF_GPIO_PODR_DATAL_PODR_DATAL5          (0x20)
-#define MCF_GPIO_PODR_DATAL_PODR_DATAL6          (0x40)
-#define MCF_GPIO_PODR_DATAL_PODR_DATAL7          (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PODR_BUSCTL */
-#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL0        (0x01)
-#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL1        (0x02)
-#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL2        (0x04)
-#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL3        (0x08)
-#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL4        (0x10)
-#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL5        (0x20)
-#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL6        (0x40)
-#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL7        (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PODR_BS */
-#define MCF_GPIO_PODR_BS_PODR_BS0                (0x01)
-#define MCF_GPIO_PODR_BS_PODR_BS1                (0x02)
-#define MCF_GPIO_PODR_BS_PODR_BS2                (0x04)
-#define MCF_GPIO_PODR_BS_PODR_BS3                (0x08)
-
-/* Bit definitions and macros for MCF_GPIO_PODR_CS */
-#define MCF_GPIO_PODR_CS_PODR_CS1                (0x02)
-#define MCF_GPIO_PODR_CS_PODR_CS2                (0x04)
-#define MCF_GPIO_PODR_CS_PODR_CS3                (0x08)
-#define MCF_GPIO_PODR_CS_PODR_CS4                (0x10)
-#define MCF_GPIO_PODR_CS_PODR_CS5                (0x20)
-#define MCF_GPIO_PODR_CS_PODR_CS6                (0x40)
-#define MCF_GPIO_PODR_CS_PODR_CS7                (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PODR_SDRAM */
-#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM0          (0x01)
-#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM1          (0x02)
-#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM2          (0x04)
-#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM3          (0x08)
-#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM4          (0x10)
-#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM5          (0x20)
-
-/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */
-#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0        (0x01)
-#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1        (0x02)
-#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2        (0x04)
-#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3        (0x08)
-
-/* Bit definitions and macros for MCF_GPIO_PODR_UARTH */
-#define MCF_GPIO_PODR_UARTH_PODR_UARTH0          (0x01)
-#define MCF_GPIO_PODR_UARTH_PODR_UARTH1          (0x02)
-
-/* Bit definitions and macros for MCF_GPIO_PODR_UARTL */
-#define MCF_GPIO_PODR_UARTL_PODR_UARTL0          (0x01)
-#define MCF_GPIO_PODR_UARTL_PODR_UARTL1          (0x02)
-#define MCF_GPIO_PODR_UARTL_PODR_UARTL2          (0x04)
-#define MCF_GPIO_PODR_UARTL_PODR_UARTL3          (0x08)
-#define MCF_GPIO_PODR_UARTL_PODR_UARTL4          (0x10)
-#define MCF_GPIO_PODR_UARTL_PODR_UARTL5          (0x20)
-#define MCF_GPIO_PODR_UARTL_PODR_UARTL6          (0x40)
-#define MCF_GPIO_PODR_UARTL_PODR_UARTL7          (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PODR_QSPI */
-#define MCF_GPIO_PODR_QSPI_PODR_QSPI0            (0x01)
-#define MCF_GPIO_PODR_QSPI_PODR_QSPI1            (0x02)
-#define MCF_GPIO_PODR_QSPI_PODR_QSPI2            (0x04)
-#define MCF_GPIO_PODR_QSPI_PODR_QSPI3            (0x08)
-#define MCF_GPIO_PODR_QSPI_PODR_QSPI4            (0x10)
-
-/* Bit definitions and macros for MCF_GPIO_PODR_TIMER */
-#define MCF_GPIO_PODR_TIMER_PODR_TIMER0          (0x01)
-#define MCF_GPIO_PODR_TIMER_PODR_TIMER1          (0x02)
-#define MCF_GPIO_PODR_TIMER_PODR_TIMER2          (0x04)
-#define MCF_GPIO_PODR_TIMER_PODR_TIMER3          (0x08)
-#define MCF_GPIO_PODR_TIMER_PODR_TIMER4          (0x10)
-#define MCF_GPIO_PODR_TIMER_PODR_TIMER5          (0x20)
-#define MCF_GPIO_PODR_TIMER_PODR_TIMER6          (0x40)
-#define MCF_GPIO_PODR_TIMER_PODR_TIMER7          (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PODR_ETPU */
-#define MCF_GPIO_PODR_ETPU_PODR_ETPU0            (0x01)
-#define MCF_GPIO_PODR_ETPU_PODR_ETPU1            (0x02)
-#define MCF_GPIO_PODR_ETPU_PODR_ETPU2            (0x04)
-
-/* Bit definitions and macros for MCF_GPIO_PDDR_APDDR */
-#define MCF_GPIO_PDDR_APDDR_PDDR_APDDR5          (0x20)
-#define MCF_GPIO_PDDR_APDDR_PDDR_APDDR6          (0x40)
-#define MCF_GPIO_PDDR_APDDR_PDDR_APDDR7          (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PDDR_DATAH */
-#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH0          (0x01)
-#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH1          (0x02)
-#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH2          (0x04)
-#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH3          (0x08)
-#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH4          (0x10)
-#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH5          (0x20)
-#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH6          (0x40)
-#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH7          (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PDDR_DATAL */
-#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL0          (0x01)
-#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL1          (0x02)
-#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL2          (0x04)
-#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL3          (0x08)
-#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL4          (0x10)
-#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL5          (0x20)
-#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL6          (0x40)
-#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL7          (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PDDR_BUSCTL */
-#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL0        (0x01)
-#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL1        (0x02)
-#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL2        (0x04)
-#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL3        (0x08)
-#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL4        (0x10)
-#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL5        (0x20)
-#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL6        (0x40)
-#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL7        (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PDDR_BS */
-#define MCF_GPIO_PDDR_BS_PDDR_BS0                (0x01)
-#define MCF_GPIO_PDDR_BS_PDDR_BS3(x)             (((x)&0x07)<<1)
-
-/* Bit definitions and macros for MCF_GPIO_PDDR_CS */
-#define MCF_GPIO_PDDR_CS_PDDR_CS1                (0x02)
-#define MCF_GPIO_PDDR_CS_PDDR_CS2                (0x04)
-#define MCF_GPIO_PDDR_CS_PDDR_CS3                (0x08)
-#define MCF_GPIO_PDDR_CS_PDDR_CS4                (0x10)
-#define MCF_GPIO_PDDR_CS_PDDR_CS5                (0x20)
-#define MCF_GPIO_PDDR_CS_PDDR_CS6                (0x40)
-#define MCF_GPIO_PDDR_CS_PDDR_CS7                (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PDDR_SDRAM */
-#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM0          (0x01)
-#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM1          (0x02)
-#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM2          (0x04)
-#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM3          (0x08)
-#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM4          (0x10)
-#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM5          (0x20)
-
-/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */
-#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0        (0x01)
-#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1        (0x02)
-#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2        (0x04)
-#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3        (0x08)
-
-/* Bit definitions and macros for MCF_GPIO_PDDR_UARTH */
-#define MCF_GPIO_PDDR_UARTH_PDDR_UARTH0          (0x01)
-#define MCF_GPIO_PDDR_UARTH_PDDR_UARTH1          (0x02)
-
-/* Bit definitions and macros for MCF_GPIO_PDDR_UARTL */
-#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL0          (0x01)
-#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL1          (0x02)
-#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL2          (0x04)
-#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL3          (0x08)
-#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL4          (0x10)
-#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL5          (0x20)
-#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL6          (0x40)
-#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL7          (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PDDR_QSPI */
-#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI0            (0x01)
-#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI1            (0x02)
-#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI2            (0x04)
-#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI3            (0x08)
-#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI4            (0x10)
-
-/* Bit definitions and macros for MCF_GPIO_PDDR_TIMER */
-#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER0          (0x01)
-#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER1          (0x02)
-#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER2          (0x04)
-#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER3          (0x08)
-#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER4          (0x10)
-#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER5          (0x20)
-#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER6          (0x40)
-#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER7          (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PDDR_ETPU */
-#define MCF_GPIO_PDDR_ETPU_PDDR_ETPU0            (0x01)
-#define MCF_GPIO_PDDR_ETPU_PDDR_ETPU1            (0x02)
-#define MCF_GPIO_PDDR_ETPU_PDDR_ETPU2            (0x04)
-
-/* Bit definitions and macros for MCF_GPIO_PPDSDR_ADDR */
-#define MCF_GPIO_PPDSDR_ADDR_PPDSDR_ADDR5        (0x20)
-#define MCF_GPIO_PPDSDR_ADDR_PPDSDR_ADDR6        (0x40)
-#define MCF_GPIO_PPDSDR_ADDR_PPDSDR_ADDR7        (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PPDSDR_DATAH */
-#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH0      (0x01)
-#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH1      (0x02)
-#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH2      (0x04)
-#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH3      (0x08)
-#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH4      (0x10)
-#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH5      (0x20)
-#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH6      (0x40)
-#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH7      (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PPDSDR_DATAL */
-#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL0      (0x01)
-#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL1      (0x02)
-#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL2      (0x04)
-#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL3      (0x08)
-#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL4      (0x10)
-#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL5      (0x20)
-#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL6      (0x40)
-#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL7      (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PPDSDR_BUSCTL */
-#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL0    (0x01)
-#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL1    (0x02)
-#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL2    (0x04)
-#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL3    (0x08)
-#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL4    (0x10)
-#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL5    (0x20)
-#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL6    (0x40)
-#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL7    (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PPDSDR_BS */
-#define MCF_GPIO_PPDSDR_BS_PPDSDR_BS0            (0x01)
-#define MCF_GPIO_PPDSDR_BS_PPDSDR_BS1            (0x02)
-#define MCF_GPIO_PPDSDR_BS_PPDSDR_BS2            (0x04)
-#define MCF_GPIO_PPDSDR_BS_PPDSDR_BS3            (0x08)
-
-/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */
-#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0    (0x01)
-#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1    (0x02)
-#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2    (0x04)
-#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3    (0x08)
-
-/* Bit definitions and macros for MCF_GPIO_PPDSDR_CS */
-#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS1            (0x02)
-#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS2            (0x04)
-#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS3            (0x08)
-#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS4            (0x10)
-#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS5            (0x20)
-#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS6            (0x40)
-#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS7            (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PPDSDR_SDRAM */
-#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM0      (0x01)
-#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM1      (0x02)
-#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM2      (0x04)
-#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM3      (0x08)
-#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM4      (0x10)
-#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM5      (0x20)
-#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM6      (0x40)
-#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM7      (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PPDSDR_UARTH */
-#define MCF_GPIO_PPDSDR_UARTH_PPDSDR_UARTH0      (0x01)
-#define MCF_GPIO_PPDSDR_UARTH_PPDSDR_UARTH1      (0x02)
-
-/* Bit definitions and macros for MCF_GPIO_PPDSDR_UARTL */
-#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL0      (0x01)
-#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL1      (0x02)
-#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL2      (0x04)
-#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL3      (0x08)
-#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL4      (0x10)
-#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL5      (0x20)
-#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL6      (0x40)
-#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL7      (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PPDSDR_QSPI */
-#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI0        (0x01)
-#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI1        (0x02)
-#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI2        (0x04)
-#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI3        (0x08)
-#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI4        (0x10)
-
-/* Bit definitions and macros for MCF_GPIO_PPDSDR_TIMER */
-#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER0      (0x01)
-#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER1      (0x02)
-#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER2      (0x04)
-#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER3      (0x08)
-#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER4      (0x10)
-#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER5      (0x20)
-#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER6      (0x40)
-#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER7      (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PPDSDR_ETPU */
-#define MCF_GPIO_PPDSDR_ETPU_PPDSDR_ETPU0        (0x01)
-#define MCF_GPIO_PPDSDR_ETPU_PPDSDR_ETPU1        (0x02)
-#define MCF_GPIO_PPDSDR_ETPU_PPDSDR_ETPU2        (0x04)
-
-/* Bit definitions and macros for MCF_GPIO_PCLRR_ADDR */
-#define MCF_GPIO_PCLRR_ADDR_PCLRR_ADDR5          (0x20)
-#define MCF_GPIO_PCLRR_ADDR_PCLRR_ADDR6          (0x40)
-#define MCF_GPIO_PCLRR_ADDR_PCLRR_ADDR7          (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PCLRR_DATAH */
-#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH0        (0x01)
-#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH1        (0x02)
-#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH2        (0x04)
-#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH3        (0x08)
-#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH4        (0x10)
-#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH5        (0x20)
-#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH6        (0x40)
-#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH7        (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PCLRR_DATAL */
-#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL0        (0x01)
-#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL1        (0x02)
-#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL2        (0x04)
-#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL3        (0x08)
-#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL4        (0x10)
-#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL5        (0x20)
-#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL6        (0x40)
-#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL7        (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PCLRR_BUSCTL */
-#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL0      (0x01)
-#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL1      (0x02)
-#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL2      (0x04)
-#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL3      (0x08)
-#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL4      (0x10)
-#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL5      (0x20)
-#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL6      (0x40)
-#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL7      (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PCLRR_BS */
-#define MCF_GPIO_PCLRR_BS_PCLRR_BS0              (0x01)
-#define MCF_GPIO_PCLRR_BS_PCLRR_BS1              (0x02)
-#define MCF_GPIO_PCLRR_BS_PCLRR_BS2              (0x04)
-#define MCF_GPIO_PCLRR_BS_PCLRR_BS3              (0x08)
-
-/* Bit definitions and macros for MCF_GPIO_PCLRR_CS */
-#define MCF_GPIO_PCLRR_CS_PCLRR_CS1              (0x02)
-#define MCF_GPIO_PCLRR_CS_PCLRR_CS2              (0x04)
-#define MCF_GPIO_PCLRR_CS_PCLRR_CS3              (0x08)
-#define MCF_GPIO_PCLRR_CS_PCLRR_CS4              (0x10)
-#define MCF_GPIO_PCLRR_CS_PCLRR_CS5              (0x20)
-#define MCF_GPIO_PCLRR_CS_PCLRR_CS6              (0x40)
-#define MCF_GPIO_PCLRR_CS_PCLRR_CS7              (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PCLRR_SDRAM */
-#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM0        (0x01)
-#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM1        (0x02)
-#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM2        (0x04)
-#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM3        (0x08)
-#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM4        (0x10)
-#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM5        (0x20)
-
-/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */
-#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0      (0x01)
-#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1      (0x02)
-#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2      (0x04)
-#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3      (0x08)
-
-/* Bit definitions and macros for MCF_GPIO_PCLRR_UARTH */
-#define MCF_GPIO_PCLRR_UARTH_PCLRR_UARTH0        (0x01)
-#define MCF_GPIO_PCLRR_UARTH_PCLRR_UARTH1        (0x02)
-
-/* Bit definitions and macros for MCF_GPIO_PCLRR_UARTL */
-#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL0        (0x01)
-#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL1        (0x02)
-#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL2        (0x04)
-#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL3        (0x08)
-#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL4        (0x10)
-#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL5        (0x20)
-#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL6        (0x40)
-#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL7        (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PCLRR_QSPI */
-#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI0          (0x01)
-#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI1          (0x02)
-#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI2          (0x04)
-#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI3          (0x08)
-#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI4          (0x10)
-
-/* Bit definitions and macros for MCF_GPIO_PCLRR_TIMER */
-#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER0        (0x01)
-#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER1        (0x02)
-#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER2        (0x04)
-#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER3        (0x08)
-#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER4        (0x10)
-#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER5        (0x20)
-#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER6        (0x40)
-#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER7        (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PCLRR_ETPU */
-#define MCF_GPIO_PCLRR_ETPU_PCLRR_ETPU0          (0x01)
-#define MCF_GPIO_PCLRR_ETPU_PCLRR_ETPU1          (0x02)
-#define MCF_GPIO_PCLRR_ETPU_PCLRR_ETPU2          (0x04)
-
-/* Bit definitions and macros for MCF_GPIO_PAR_AD */
-#define MCF_GPIO_PAR_AD_PAR_DATAL                (0x01)
-#define MCF_GPIO_PAR_AD_PAR_ADDR21               (0x20)
-#define MCF_GPIO_PAR_AD_PAR_ADDR22               (0x40)
-#define MCF_GPIO_PAR_AD_PAR_ADDR23               (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PAR_BUSCTL */
-#define MCF_GPIO_PAR_BUSCTL_PAR_TIP(x)           (((x)&0x0003)<<0)
-#define MCF_GPIO_PAR_BUSCTL_PAR_TS(x)            (((x)&0x0003)<<2)
-#define MCF_GPIO_PAR_BUSCTL_PAR_TSIZ0            (0x0010)
-#define MCF_GPIO_PAR_BUSCTL_PAR_TSIZ1            (0x0040)
-#define MCF_GPIO_PAR_BUSCTL_PAR_RWB              (0x0100)
-#define MCF_GPIO_PAR_BUSCTL_PAR_TEA(x)           (((x)&0x0003)<<10)
-#define MCF_GPIO_PAR_BUSCTL_PAR_TA               (0x1000)
-#define MCF_GPIO_PAR_BUSCTL_PAR_OE               (0x4000)
-#define MCF_GPIO_PAR_BUSCTL_PAR_TEA_GPIO         (0x0000)
-#define MCF_GPIO_PAR_BUSCTL_PAR_TEA_DMA          (0x0800)
-#define MCF_GPIO_PAR_BUSCTL_PAR_TEA_TEA          (0x0C00)
-#define MCF_GPIO_PAR_BUSCTL_PAR_TS_GPIO          (0x0000)
-#define MCF_GPIO_PAR_BUSCTL_PAR_TS_DMA           (0x0080)
-#define MCF_GPIO_PAR_BUSCTL_PAR_TS_TS            (0x00C0)
-#define MCF_GPIO_PAR_BUSCTL_PAR_TIP_GPIO         (0x0000)
-#define MCF_GPIO_PAR_BUSCTL_PAR_TIP_DMA          (0x0002)
-#define MCF_GPIO_PAR_BUSCTL_PAR_TIP_TEA          (0x0003)
-
-/* Bit definitions and macros for MCF_GPIO_PAR_BS */
-#define MCF_GPIO_PAR_BS_PAR_BS0                  (0x01)
-#define MCF_GPIO_PAR_BS_PAR_BS1                  (0x02)
-#define MCF_GPIO_PAR_BS_PAR_BS2                  (0x04)
-#define MCF_GPIO_PAR_BS_PAR_BS3                  (0x08)
-
-/* Bit definitions and macros for MCF_GPIO_PAR_CS */
-#define MCF_GPIO_PAR_CS_PAR_CS1                  (0x02)
-#define MCF_GPIO_PAR_CS_PAR_CS2                  (0x04)
-#define MCF_GPIO_PAR_CS_PAR_CS3                  (0x08)
-#define MCF_GPIO_PAR_CS_PAR_CS4                  (0x10)
-#define MCF_GPIO_PAR_CS_PAR_CS5                  (0x20)
-#define MCF_GPIO_PAR_CS_PAR_CS6                  (0x40)
-#define MCF_GPIO_PAR_CS_PAR_CS7                  (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PAR_SDRAM */
-#define MCF_GPIO_PAR_SDRAM_PAR_SDCS0             (0x01)
-#define MCF_GPIO_PAR_SDRAM_PAR_SDCS1             (0x02)
-#define MCF_GPIO_PAR_SDRAM_PAR_SCKE              (0x04)
-#define MCF_GPIO_PAR_SDRAM_PAR_SRAS              (0x08)
-#define MCF_GPIO_PAR_SDRAM_PAR_SCAS              (0x10)
-#define MCF_GPIO_PAR_SDRAM_PAR_SDWE              (0x20)
-#define MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(x)         (((x)&0x03)<<6)
-
-/* Bit definitions and macros for MCF_GPIO_PAR_FECI2C */
-#define MCF_GPIO_PAR_FECI2C_PAR_SDA(x)           (((x)&0x03)<<0)
-#define MCF_GPIO_PAR_FECI2C_PAR_SCL(x)           (((x)&0x03)<<2)
-#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO(x)         (((x)&0x03)<<4)
-#define MCF_GPIO_PAR_FECI2C_PAR_EMDC(x)          (((x)&0x03)<<6)
-#define MCF_GPIO_PAR_FECI2C_PAR_EMDC_GPIO        (0x00)
-#define MCF_GPIO_PAR_FECI2C_PAR_EMDC_UART2       (0x40)
-#define MCF_GPIO_PAR_FECI2C_PAR_EMDC_I2C         (0x80)
-#define MCF_GPIO_PAR_FECI2C_PAR_EMDC_FEC         (0xC0)
-#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO_GPIO       (0x00)
-#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO_UART2      (0x10)
-#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO_I2C        (0x20)
-#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO_FEC        (0x30)
-#define MCF_GPIO_PAR_FECI2C_PAR_SCL_GPIO         (0x00)
-#define MCF_GPIO_PAR_FECI2C_PAR_SCL_FLEX         (0x08)
-#define MCF_GPIO_PAR_FECI2C_PAR_SCL_I2C          (0x0C)
-#define MCF_GPIO_PAR_FECI2C_PAR_SDA_GPIO         (0x00)
-#define MCF_GPIO_PAR_FECI2C_PAR_SDA_FLEX         (0x02)
-#define MCF_GPIO_PAR_FECI2C_PAR_SDA_I2C          (0x03)
-
-/* Bit definitions and macros for MCF_GPIO_PAR_UART */
-#define MCF_GPIO_PAR_UART_PAR_U0RTS              (0x0001)
-#define MCF_GPIO_PAR_UART_PAR_U0CTS              (0x0002)
-#define MCF_GPIO_PAR_UART_PAR_U0TXD              (0x0004)
-#define MCF_GPIO_PAR_UART_PAR_U0RXD              (0x0008)
-#define MCF_GPIO_PAR_UART_PAR_U1RTS(x)           (((x)&0x0003)<<4)
-#define MCF_GPIO_PAR_UART_PAR_U1CTS(x)           (((x)&0x0003)<<6)
-#define MCF_GPIO_PAR_UART_PAR_U1TXD(x)           (((x)&0x0003)<<8)
-#define MCF_GPIO_PAR_UART_PAR_U1RXD(x)           (((x)&0x0003)<<10)
-#define MCF_GPIO_PAR_UART_PAR_U2TXD              (0x1000)
-#define MCF_GPIO_PAR_UART_PAR_U2RXD              (0x2000)
-#define MCF_GPIO_PAR_UART_PAR_CAN1EN             (0x4000)
-#define MCF_GPIO_PAR_UART_PAR_DREQ2              (0x8000)
-#define MCF_GPIO_PAR_UART_PAR_U1RXD_GPIO         (0x0000)
-#define MCF_GPIO_PAR_UART_PAR_U1RXD_FLEX         (0x0800)
-#define MCF_GPIO_PAR_UART_PAR_U1RXD_UART1        (0x0C00)
-#define MCF_GPIO_PAR_UART_PAR_U1TXD_GPIO         (0x0000)
-#define MCF_GPIO_PAR_UART_PAR_U1TXD_FLEX         (0x0200)
-#define MCF_GPIO_PAR_UART_PAR_U1TXD_UART1        (0x0300)
-#define MCF_GPIO_PAR_UART_PAR_U1CTS_GPIO         (0x0000)
-#define MCF_GPIO_PAR_UART_PAR_U1CTS_UART2        (0x0080)
-#define MCF_GPIO_PAR_UART_PAR_U1CTS_UART1        (0x00C0)
-#define MCF_GPIO_PAR_UART_PAR_U1RTS_GPIO         (0x0000)
-#define MCF_GPIO_PAR_UART_PAR_U1RTS_UART2        (0x0020)
-#define MCF_GPIO_PAR_UART_PAR_U1RTS_UART1        (0x0030)
-
-/* Bit definitions and macros for MCF_GPIO_PAR_QSPI */
-#define MCF_GPIO_PAR_QSPI_PAR_SCK(x)             (((x)&0x03)<<0)
-#define MCF_GPIO_PAR_QSPI_PAR_DOUT               (0x04)
-#define MCF_GPIO_PAR_QSPI_PAR_DIN(x)             (((x)&0x03)<<3)
-#define MCF_GPIO_PAR_QSPI_PAR_PCS0               (0x20)
-#define MCF_GPIO_PAR_QSPI_PAR_PCS1(x)            (((x)&0x03)<<6)
-#define MCF_GPIO_PAR_QSPI_PAR_PCS1_GPIO          (0x00)
-#define MCF_GPIO_PAR_QSPI_PAR_PCS1_SDRAMC        (0x80)
-#define MCF_GPIO_PAR_QSPI_PAR_PCS1_QSPI          (0xC0)
-#define MCF_GPIO_PAR_QSPI_PAR_DIN_GPIO           (0x00)
-#define MCF_GPIO_PAR_QSPI_PAR_DIN_I2C            (0x10)
-#define MCF_GPIO_PAR_QSPI_PAR_DIN_QSPI           (0x1C)
-#define MCF_GPIO_PAR_QSPI_PAR_SCK_GPIO           (0x00)
-#define MCF_GPIO_PAR_QSPI_PAR_SCK_I2C            (0x02)
-#define MCF_GPIO_PAR_QSPI_PAR_SCK_QSPI           (0x03)
-
-/* Bit definitions and macros for MCF_GPIO_PAR_TIMER */
-#define MCF_GPIO_PAR_TIMER_PAR_T0OUT(x)          (((x)&0x0003)<<0)
-#define MCF_GPIO_PAR_TIMER_PAR_T1OUT(x)          (((x)&0x0003)<<2)
-#define MCF_GPIO_PAR_TIMER_PAR_T2OUT(x)          (((x)&0x0003)<<4)
-#define MCF_GPIO_PAR_TIMER_PAR_T3OUT(x)          (((x)&0x0003)<<6)
-#define MCF_GPIO_PAR_TIMER_PAR_T0IN(x)           (((x)&0x0003)<<8)
-#define MCF_GPIO_PAR_TIMER_PAR_T1IN(x)           (((x)&0x0003)<<10)
-#define MCF_GPIO_PAR_TIMER_PAR_T2IN(x)           (((x)&0x0003)<<12)
-#define MCF_GPIO_PAR_TIMER_PAR_T3IN(x)           (((x)&0x0003)<<14)
-#define MCF_GPIO_PAR_TIMER_PAR_T3IN_GPIO         (0x0000)
-#define MCF_GPIO_PAR_TIMER_PAR_T3IN_QSPI         (0x4000)
-#define MCF_GPIO_PAR_TIMER_PAR_T3IN_UART2        (0x8000)
-#define MCF_GPIO_PAR_TIMER_PAR_T3IN_T3IN         (0xC000)
-#define MCF_GPIO_PAR_TIMER_PAR_T2IN_GPIO         (0x0000)
-#define MCF_GPIO_PAR_TIMER_PAR_T2IN_T2OUT        (0x1000)
-#define MCF_GPIO_PAR_TIMER_PAR_T2IN_DMA          (0x2000)
-#define MCF_GPIO_PAR_TIMER_PAR_T2IN_T2IN         (0x3000)
-#define MCF_GPIO_PAR_TIMER_PAR_T1IN_GPIO         (0x0000)
-#define MCF_GPIO_PAR_TIMER_PAR_T1IN_T1OUT        (0x0400)
-#define MCF_GPIO_PAR_TIMER_PAR_T1IN_DMA          (0x0800)
-#define MCF_GPIO_PAR_TIMER_PAR_T1IN_T1IN         (0x0C00)
-#define MCF_GPIO_PAR_TIMER_PAR_T0IN_GPIO         (0x0000)
-#define MCF_GPIO_PAR_TIMER_PAR_T0IN_DMA          (0x0200)
-#define MCF_GPIO_PAR_TIMER_PAR_T0IN_T0IN         (0x0300)
-#define MCF_GPIO_PAR_TIMER_PAR_T3OUT_GPIO        (0x0000)
-#define MCF_GPIO_PAR_TIMER_PAR_T3OUT_QSPI        (0x0040)
-#define MCF_GPIO_PAR_TIMER_PAR_T3OUT_UART2       (0x0080)
-#define MCF_GPIO_PAR_TIMER_PAR_T3OUT_T3OUT       (0x00C0)
-#define MCF_GPIO_PAR_TIMER_PAR_T2OUT_GPIO        (0x0000)
-#define MCF_GPIO_PAR_TIMER_PAR_T2OUT_DMA         (0x0020)
-#define MCF_GPIO_PAR_TIMER_PAR_T2OUT_T2OUT       (0x0030)
-#define MCF_GPIO_PAR_TIMER_PAR_T1OUT_GPIO        (0x0000)
-#define MCF_GPIO_PAR_TIMER_PAR_T1OUT_DMA         (0x0008)
-#define MCF_GPIO_PAR_TIMER_PAR_T1OUT_T1OUT       (0x000C)
-#define MCF_GPIO_PAR_TIMER_PAR_T0OUT_GPIO        (0x0000)
-#define MCF_GPIO_PAR_TIMER_PAR_T0OUT_DMA         (0x0002)
-#define MCF_GPIO_PAR_TIMER_PAR_T0OUT_T0OUT       (0x0003)
-
-/* Bit definitions and macros for MCF_GPIO_PAR_ETPU */
-#define MCF_GPIO_PAR_ETPU_PAR_LTPU_ODIS          (0x01)
-#define MCF_GPIO_PAR_ETPU_PAR_UTPU_ODIS          (0x02)
-#define MCF_GPIO_PAR_ETPU_PAR_TCRCLK             (0x04)
-
-/* Bit definitions and macros for MCF_GPIO_DSCR_EIM */
-#define MCF_GPIO_DSCR_EIM_DSCR_EIM0              (0x01)
-#define MCF_GPIO_DSCR_EIM_DSCR_EIM1              (0x10)
-
-/* Bit definitions and macros for MCF_GPIO_DSCR_ETPU */
-#define MCF_GPIO_DSCR_ETPU_DSCR_ETPU_7_0         (0x01)
-#define MCF_GPIO_DSCR_ETPU_DSCR_ETPU_15_8        (0x04)
-#define MCF_GPIO_DSCR_ETPU_DSCR_ETPU_23_16       (0x10)
-#define MCF_GPIO_DSCR_ETPU_DSCR_ETPU_31_24       (0x40)
-
-/* Bit definitions and macros for MCF_GPIO_DSCR_FECI2C */
-#define MCF_GPIO_DSCR_FECI2C_DSCR_I2C            (0x01)
-#define MCF_GPIO_DSCR_FECI2C_DSCR_FEC            (0x10)
-
-/* Bit definitions and macros for MCF_GPIO_DSCR_UART */
-#define MCF_GPIO_DSCR_UART_DSCR_UART0            (0x01)
-#define MCF_GPIO_DSCR_UART_DSCR_UART1            (0x04)
-#define MCF_GPIO_DSCR_UART_DSCR_UART2            (0x10)
-#define MCF_GPIO_DSCR_UART_DSCR_IRQ              (0x40)
-
-/* Bit definitions and macros for MCF_GPIO_DSCR_QSPI */
-#define MCF_GPIO_DSCR_QSPI_DSCR_QSPI             (0x01)
-
-/* Bit definitions and macros for MCF_GPIO_DSCR_TIMER */
-#define MCF_GPIO_DSCR_TIMER_DSCR_TIMER           (0x01)
-
-/********************************************************************/
-
-#endif /* __MCF523X_GPIO_H__ */
diff --git a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_i2c.h b/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_i2c.h
deleted file mode 100644
index ee4665507..000000000
--- a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_i2c.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly 
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file 
- * LICENSE_FREESCALE.TXT.
- *
- * File:	mcf523x_i2c.h
- * Purpose:	Register and bit definitions for the MCF523X
- *
- * Notes:	
- *	
- */
-
-#ifndef __MCF523X_I2C_H__
-#define __MCF523X_I2C_H__
-
-/*********************************************************************
-*
-* I2C Module (I2C)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_I2C_I2AR     (*(vuint8 *)(void*)(&__IPSBAR[0x000300]))
-#define MCF_I2C_I2FDR    (*(vuint8 *)(void*)(&__IPSBAR[0x000304]))
-#define MCF_I2C_I2CR     (*(vuint8 *)(void*)(&__IPSBAR[0x000308]))
-#define MCF_I2C_I2SR     (*(vuint8 *)(void*)(&__IPSBAR[0x00030C]))
-#define MCF_I2C_I2DR     (*(vuint8 *)(void*)(&__IPSBAR[0x000310]))
-#define MCF_I2C_I2ICR    (*(vuint8 *)(void*)(&__IPSBAR[0x000320]))
-
-/* Bit definitions and macros for MCF_I2C_I2AR */
-#define MCF_I2C_I2AR_ADR(x)    (((x)&0x7F)<<1)
-
-/* Bit definitions and macros for MCF_I2C_I2FDR */
-#define MCF_I2C_I2FDR_IC(x)    (((x)&0x3F)<<0)
-
-/* Bit definitions and macros for MCF_I2C_I2CR */
-#define MCF_I2C_I2CR_RSTA      (0x04)
-#define MCF_I2C_I2CR_TXAK      (0x08)
-#define MCF_I2C_I2CR_MTX       (0x10)
-#define MCF_I2C_I2CR_MSTA      (0x20)
-#define MCF_I2C_I2CR_IIEN      (0x40)
-#define MCF_I2C_I2CR_IEN       (0x80)
-
-/* Bit definitions and macros for MCF_I2C_I2SR */
-#define MCF_I2C_I2SR_RXAK      (0x01)
-#define MCF_I2C_I2SR_IIF       (0x02)
-#define MCF_I2C_I2SR_SRW       (0x04)
-#define MCF_I2C_I2SR_IAL       (0x10)
-#define MCF_I2C_I2SR_IBB       (0x20)
-#define MCF_I2C_I2SR_IAAS      (0x40)
-#define MCF_I2C_I2SR_ICF       (0x80)
-
-/* Bit definitions and macros for MCF_I2C_I2ICR */
-#define MCF_I2C_I2ICR_IE       (0x01)
-#define MCF_I2C_I2ICR_RE       (0x02)
-#define MCF_I2C_I2ICR_TE       (0x04)
-#define MCF_I2C_I2ICR_BNBE     (0x08)
-
-/********************************************************************/
-
-#endif /* __MCF523X_I2C_H__ */
diff --git a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_intc0.h b/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_intc0.h
deleted file mode 100644
index 7d19e9863..000000000
--- a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_intc0.h
+++ /dev/null
@@ -1,323 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly 
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file 
- * LICENSE_FREESCALE.TXT.
- *
- * File:	mcf523x_intc0.h
- * Purpose:	Register and bit definitions for the MCF523X
- *
- * Notes:	
- *	
- */
-
-#ifndef __MCF523X_INTC0_H__
-#define __MCF523X_INTC0_H__
-
-/*********************************************************************
-*
-* Interrupt Controller 0 (INTC0)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_INTC0_IPRH         (*(vuint32*)(void*)(&__IPSBAR[0x000C00]))
-#define MCF_INTC0_IPRL         (*(vuint32*)(void*)(&__IPSBAR[0x000C04]))
-#define MCF_INTC0_IMRH         (*(vuint32*)(void*)(&__IPSBAR[0x000C08]))
-#define MCF_INTC0_IMRL         (*(vuint32*)(void*)(&__IPSBAR[0x000C0C]))
-#define MCF_INTC0_INTFRCH      (*(vuint32*)(void*)(&__IPSBAR[0x000C10]))
-#define MCF_INTC0_INTFRCL      (*(vuint32*)(void*)(&__IPSBAR[0x000C14]))
-#define MCF_INTC0_IRLR         (*(vuint8 *)(void*)(&__IPSBAR[0x000C18]))
-#define MCF_INTC0_IACKLPR      (*(vuint8 *)(void*)(&__IPSBAR[0x000C19]))
-#define MCF_INTC0_ICR0         (*(vuint8 *)(void*)(&__IPSBAR[0x000C40]))
-#define MCF_INTC0_ICR1         (*(vuint8 *)(void*)(&__IPSBAR[0x000C41]))
-#define MCF_INTC0_ICR2         (*(vuint8 *)(void*)(&__IPSBAR[0x000C42]))
-#define MCF_INTC0_ICR3         (*(vuint8 *)(void*)(&__IPSBAR[0x000C43]))
-#define MCF_INTC0_ICR4         (*(vuint8 *)(void*)(&__IPSBAR[0x000C44]))
-#define MCF_INTC0_ICR5         (*(vuint8 *)(void*)(&__IPSBAR[0x000C45]))
-#define MCF_INTC0_ICR6         (*(vuint8 *)(void*)(&__IPSBAR[0x000C46]))
-#define MCF_INTC0_ICR7         (*(vuint8 *)(void*)(&__IPSBAR[0x000C47]))
-#define MCF_INTC0_ICR8         (*(vuint8 *)(void*)(&__IPSBAR[0x000C48]))
-#define MCF_INTC0_ICR9         (*(vuint8 *)(void*)(&__IPSBAR[0x000C49]))
-#define MCF_INTC0_ICR10        (*(vuint8 *)(void*)(&__IPSBAR[0x000C4A]))
-#define MCF_INTC0_ICR11        (*(vuint8 *)(void*)(&__IPSBAR[0x000C4B]))
-#define MCF_INTC0_ICR12        (*(vuint8 *)(void*)(&__IPSBAR[0x000C4C]))
-#define MCF_INTC0_ICR13        (*(vuint8 *)(void*)(&__IPSBAR[0x000C4D]))
-#define MCF_INTC0_ICR14        (*(vuint8 *)(void*)(&__IPSBAR[0x000C4E]))
-#define MCF_INTC0_ICR15        (*(vuint8 *)(void*)(&__IPSBAR[0x000C4F]))
-#define MCF_INTC0_ICR16        (*(vuint8 *)(void*)(&__IPSBAR[0x000C50]))
-#define MCF_INTC0_ICR17        (*(vuint8 *)(void*)(&__IPSBAR[0x000C51]))
-#define MCF_INTC0_ICR18        (*(vuint8 *)(void*)(&__IPSBAR[0x000C52]))
-#define MCF_INTC0_ICR19        (*(vuint8 *)(void*)(&__IPSBAR[0x000C53]))
-#define MCF_INTC0_ICR20        (*(vuint8 *)(void*)(&__IPSBAR[0x000C54]))
-#define MCF_INTC0_ICR21        (*(vuint8 *)(void*)(&__IPSBAR[0x000C55]))
-#define MCF_INTC0_ICR22        (*(vuint8 *)(void*)(&__IPSBAR[0x000C56]))
-#define MCF_INTC0_ICR23        (*(vuint8 *)(void*)(&__IPSBAR[0x000C57]))
-#define MCF_INTC0_ICR24        (*(vuint8 *)(void*)(&__IPSBAR[0x000C58]))
-#define MCF_INTC0_ICR25        (*(vuint8 *)(void*)(&__IPSBAR[0x000C59]))
-#define MCF_INTC0_ICR26        (*(vuint8 *)(void*)(&__IPSBAR[0x000C5A]))
-#define MCF_INTC0_ICR27        (*(vuint8 *)(void*)(&__IPSBAR[0x000C5B]))
-#define MCF_INTC0_ICR28        (*(vuint8 *)(void*)(&__IPSBAR[0x000C5C]))
-#define MCF_INTC0_ICR29        (*(vuint8 *)(void*)(&__IPSBAR[0x000C5D]))
-#define MCF_INTC0_ICR30        (*(vuint8 *)(void*)(&__IPSBAR[0x000C5E]))
-#define MCF_INTC0_ICR31        (*(vuint8 *)(void*)(&__IPSBAR[0x000C5F]))
-#define MCF_INTC0_ICR32        (*(vuint8 *)(void*)(&__IPSBAR[0x000C60]))
-#define MCF_INTC0_ICR33        (*(vuint8 *)(void*)(&__IPSBAR[0x000C61]))
-#define MCF_INTC0_ICR34        (*(vuint8 *)(void*)(&__IPSBAR[0x000C62]))
-#define MCF_INTC0_ICR35        (*(vuint8 *)(void*)(&__IPSBAR[0x000C63]))
-#define MCF_INTC0_ICR36        (*(vuint8 *)(void*)(&__IPSBAR[0x000C64]))
-#define MCF_INTC0_ICR37        (*(vuint8 *)(void*)(&__IPSBAR[0x000C65]))
-#define MCF_INTC0_ICR38        (*(vuint8 *)(void*)(&__IPSBAR[0x000C66]))
-#define MCF_INTC0_ICR39        (*(vuint8 *)(void*)(&__IPSBAR[0x000C67]))
-#define MCF_INTC0_ICR40        (*(vuint8 *)(void*)(&__IPSBAR[0x000C68]))
-#define MCF_INTC0_ICR41        (*(vuint8 *)(void*)(&__IPSBAR[0x000C69]))
-#define MCF_INTC0_ICR42        (*(vuint8 *)(void*)(&__IPSBAR[0x000C6A]))
-#define MCF_INTC0_ICR43        (*(vuint8 *)(void*)(&__IPSBAR[0x000C6B]))
-#define MCF_INTC0_ICR44        (*(vuint8 *)(void*)(&__IPSBAR[0x000C6C]))
-#define MCF_INTC0_ICR45        (*(vuint8 *)(void*)(&__IPSBAR[0x000C6D]))
-#define MCF_INTC0_ICR46        (*(vuint8 *)(void*)(&__IPSBAR[0x000C6E]))
-#define MCF_INTC0_ICR47        (*(vuint8 *)(void*)(&__IPSBAR[0x000C6F]))
-#define MCF_INTC0_ICR48        (*(vuint8 *)(void*)(&__IPSBAR[0x000C70]))
-#define MCF_INTC0_ICR49        (*(vuint8 *)(void*)(&__IPSBAR[0x000C71]))
-#define MCF_INTC0_ICR50        (*(vuint8 *)(void*)(&__IPSBAR[0x000C72]))
-#define MCF_INTC0_ICR51        (*(vuint8 *)(void*)(&__IPSBAR[0x000C73]))
-#define MCF_INTC0_ICR52        (*(vuint8 *)(void*)(&__IPSBAR[0x000C74]))
-#define MCF_INTC0_ICR53        (*(vuint8 *)(void*)(&__IPSBAR[0x000C75]))
-#define MCF_INTC0_ICR54        (*(vuint8 *)(void*)(&__IPSBAR[0x000C76]))
-#define MCF_INTC0_ICR55        (*(vuint8 *)(void*)(&__IPSBAR[0x000C77]))
-#define MCF_INTC0_ICR56        (*(vuint8 *)(void*)(&__IPSBAR[0x000C78]))
-#define MCF_INTC0_ICR57        (*(vuint8 *)(void*)(&__IPSBAR[0x000C79]))
-#define MCF_INTC0_ICR58        (*(vuint8 *)(void*)(&__IPSBAR[0x000C7A]))
-#define MCF_INTC0_ICR59        (*(vuint8 *)(void*)(&__IPSBAR[0x000C7B]))
-#define MCF_INTC0_ICR60        (*(vuint8 *)(void*)(&__IPSBAR[0x000C7C]))
-#define MCF_INTC0_ICR61        (*(vuint8 *)(void*)(&__IPSBAR[0x000C7D]))
-#define MCF_INTC0_ICR62        (*(vuint8 *)(void*)(&__IPSBAR[0x000C7E]))
-#define MCF_INTC0_ICR63        (*(vuint8 *)(void*)(&__IPSBAR[0x000C7F]))
-#define MCF_INTC0_ICRn(x)      (*(vuint8 *)(void*)(&__IPSBAR[0x000C40+((x)*0x001)]))
-#define MCF_INTC0_SWIACK       (*(vuint8 *)(void*)(&__IPSBAR[0x000CE0]))
-#define MCF_INTC0_L1IACK       (*(vuint8 *)(void*)(&__IPSBAR[0x000CE4]))
-#define MCF_INTC0_L2IACK       (*(vuint8 *)(void*)(&__IPSBAR[0x000CE8]))
-#define MCF_INTC0_L3IACK       (*(vuint8 *)(void*)(&__IPSBAR[0x000CEC]))
-#define MCF_INTC0_L4IACK       (*(vuint8 *)(void*)(&__IPSBAR[0x000CF0]))
-#define MCF_INTC0_L5IACK       (*(vuint8 *)(void*)(&__IPSBAR[0x000CF4]))
-#define MCF_INTC0_L6IACK       (*(vuint8 *)(void*)(&__IPSBAR[0x000CF8]))
-#define MCF_INTC0_L7IACK       (*(vuint8 *)(void*)(&__IPSBAR[0x000CFC]))
-#define MCF_INTC0_LnIACK(x)    (*(vuint8 *)(void*)(&__IPSBAR[0x000CE4+((x)*0x004)]))
-
-/* Bit definitions and macros for MCF_INTC0_IPRH */
-#define MCF_INTC0_IPRH_INT32          (0x00000001)
-#define MCF_INTC0_IPRH_INT33          (0x00000002)
-#define MCF_INTC0_IPRH_INT34          (0x00000004)
-#define MCF_INTC0_IPRH_INT35          (0x00000008)
-#define MCF_INTC0_IPRH_INT36          (0x00000010)
-#define MCF_INTC0_IPRH_INT37          (0x00000020)
-#define MCF_INTC0_IPRH_INT38          (0x00000040)
-#define MCF_INTC0_IPRH_INT39          (0x00000080)
-#define MCF_INTC0_IPRH_INT40          (0x00000100)
-#define MCF_INTC0_IPRH_INT41          (0x00000200)
-#define MCF_INTC0_IPRH_INT42          (0x00000400)
-#define MCF_INTC0_IPRH_INT43          (0x00000800)
-#define MCF_INTC0_IPRH_INT44          (0x00001000)
-#define MCF_INTC0_IPRH_INT45          (0x00002000)
-#define MCF_INTC0_IPRH_INT46          (0x00004000)
-#define MCF_INTC0_IPRH_INT47          (0x00008000)
-#define MCF_INTC0_IPRH_INT48          (0x00010000)
-#define MCF_INTC0_IPRH_INT49          (0x00020000)
-#define MCF_INTC0_IPRH_INT50          (0x00040000)
-#define MCF_INTC0_IPRH_INT51          (0x00080000)
-#define MCF_INTC0_IPRH_INT52          (0x00100000)
-#define MCF_INTC0_IPRH_INT53          (0x00200000)
-#define MCF_INTC0_IPRH_INT54          (0x00400000)
-#define MCF_INTC0_IPRH_INT55          (0x00800000)
-#define MCF_INTC0_IPRH_INT56          (0x01000000)
-#define MCF_INTC0_IPRH_INT57          (0x02000000)
-#define MCF_INTC0_IPRH_INT58          (0x04000000)
-#define MCF_INTC0_IPRH_INT59          (0x08000000)
-#define MCF_INTC0_IPRH_INT60          (0x10000000)
-#define MCF_INTC0_IPRH_INT61          (0x20000000)
-#define MCF_INTC0_IPRH_INT62          (0x40000000)
-#define MCF_INTC0_IPRH_INT63          (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC0_IPRL */
-#define MCF_INTC0_IPRL_INT1           (0x00000002)
-#define MCF_INTC0_IPRL_INT2           (0x00000004)
-#define MCF_INTC0_IPRL_INT3           (0x00000008)
-#define MCF_INTC0_IPRL_INT4           (0x00000010)
-#define MCF_INTC0_IPRL_INT5           (0x00000020)
-#define MCF_INTC0_IPRL_INT6           (0x00000040)
-#define MCF_INTC0_IPRL_INT7           (0x00000080)
-#define MCF_INTC0_IPRL_INT8           (0x00000100)
-#define MCF_INTC0_IPRL_INT9           (0x00000200)
-#define MCF_INTC0_IPRL_INT10          (0x00000400)
-#define MCF_INTC0_IPRL_INT11          (0x00000800)
-#define MCF_INTC0_IPRL_INT12          (0x00001000)
-#define MCF_INTC0_IPRL_INT13          (0x00002000)
-#define MCF_INTC0_IPRL_INT14          (0x00004000)
-#define MCF_INTC0_IPRL_INT15          (0x00008000)
-#define MCF_INTC0_IPRL_INT16          (0x00010000)
-#define MCF_INTC0_IPRL_INT17          (0x00020000)
-#define MCF_INTC0_IPRL_INT18          (0x00040000)
-#define MCF_INTC0_IPRL_INT19          (0x00080000)
-#define MCF_INTC0_IPRL_INT20          (0x00100000)
-#define MCF_INTC0_IPRL_INT21          (0x00200000)
-#define MCF_INTC0_IPRL_INT22          (0x00400000)
-#define MCF_INTC0_IPRL_INT23          (0x00800000)
-#define MCF_INTC0_IPRL_INT24          (0x01000000)
-#define MCF_INTC0_IPRL_INT25          (0x02000000)
-#define MCF_INTC0_IPRL_INT26          (0x04000000)
-#define MCF_INTC0_IPRL_INT27          (0x08000000)
-#define MCF_INTC0_IPRL_INT28          (0x10000000)
-#define MCF_INTC0_IPRL_INT29          (0x20000000)
-#define MCF_INTC0_IPRL_INT30          (0x40000000)
-#define MCF_INTC0_IPRL_INT31          (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC0_IMRH */
-#define MCF_INTC0_IMRH_INT_MASK32     (0x00000001)
-#define MCF_INTC0_IMRH_INT_MASK33     (0x00000002)
-#define MCF_INTC0_IMRH_INT_MASK34     (0x00000004)
-#define MCF_INTC0_IMRH_INT_MASK35     (0x00000008)
-#define MCF_INTC0_IMRH_INT_MASK36     (0x00000010)
-#define MCF_INTC0_IMRH_INT_MASK37     (0x00000020)
-#define MCF_INTC0_IMRH_INT_MASK38     (0x00000040)
-#define MCF_INTC0_IMRH_INT_MASK39     (0x00000080)
-#define MCF_INTC0_IMRH_INT_MASK40     (0x00000100)
-#define MCF_INTC0_IMRH_INT_MASK41     (0x00000200)
-#define MCF_INTC0_IMRH_INT_MASK42     (0x00000400)
-#define MCF_INTC0_IMRH_INT_MASK43     (0x00000800)
-#define MCF_INTC0_IMRH_INT_MASK44     (0x00001000)
-#define MCF_INTC0_IMRH_INT_MASK45     (0x00002000)
-#define MCF_INTC0_IMRH_INT_MASK46     (0x00004000)
-#define MCF_INTC0_IMRH_INT_MASK47     (0x00008000)
-#define MCF_INTC0_IMRH_INT_MASK48     (0x00010000)
-#define MCF_INTC0_IMRH_INT_MASK49     (0x00020000)
-#define MCF_INTC0_IMRH_INT_MASK50     (0x00040000)
-#define MCF_INTC0_IMRH_INT_MASK51     (0x00080000)
-#define MCF_INTC0_IMRH_INT_MASK52     (0x00100000)
-#define MCF_INTC0_IMRH_INT_MASK53     (0x00200000)
-#define MCF_INTC0_IMRH_INT_MASK54     (0x00400000)
-#define MCF_INTC0_IMRH_INT_MASK55     (0x00800000)
-#define MCF_INTC0_IMRH_INT_MASK56     (0x01000000)
-#define MCF_INTC0_IMRH_INT_MASK57     (0x02000000)
-#define MCF_INTC0_IMRH_INT_MASK58     (0x04000000)
-#define MCF_INTC0_IMRH_INT_MASK59     (0x08000000)
-#define MCF_INTC0_IMRH_INT_MASK60     (0x10000000)
-#define MCF_INTC0_IMRH_INT_MASK61     (0x20000000)
-#define MCF_INTC0_IMRH_INT_MASK62     (0x40000000)
-#define MCF_INTC0_IMRH_INT_MASK63     (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC0_IMRL */
-#define MCF_INTC0_IMRL_MASKALL        (0x00000001)
-#define MCF_INTC0_IMRL_INT_MASK1      (0x00000002)
-#define MCF_INTC0_IMRL_INT_MASK2      (0x00000004)
-#define MCF_INTC0_IMRL_INT_MASK3      (0x00000008)
-#define MCF_INTC0_IMRL_INT_MASK4      (0x00000010)
-#define MCF_INTC0_IMRL_INT_MASK5      (0x00000020)
-#define MCF_INTC0_IMRL_INT_MASK6      (0x00000040)
-#define MCF_INTC0_IMRL_INT_MASK7      (0x00000080)
-#define MCF_INTC0_IMRL_INT_MASK8      (0x00000100)
-#define MCF_INTC0_IMRL_INT_MASK9      (0x00000200)
-#define MCF_INTC0_IMRL_INT_MASK10     (0x00000400)
-#define MCF_INTC0_IMRL_INT_MASK11     (0x00000800)
-#define MCF_INTC0_IMRL_INT_MASK12     (0x00001000)
-#define MCF_INTC0_IMRL_INT_MASK13     (0x00002000)
-#define MCF_INTC0_IMRL_INT_MASK14     (0x00004000)
-#define MCF_INTC0_IMRL_INT_MASK15     (0x00008000)
-#define MCF_INTC0_IMRL_INT_MASK16     (0x00010000)
-#define MCF_INTC0_IMRL_INT_MASK17     (0x00020000)
-#define MCF_INTC0_IMRL_INT_MASK18     (0x00040000)
-#define MCF_INTC0_IMRL_INT_MASK19     (0x00080000)
-#define MCF_INTC0_IMRL_INT_MASK20     (0x00100000)
-#define MCF_INTC0_IMRL_INT_MASK21     (0x00200000)
-#define MCF_INTC0_IMRL_INT_MASK22     (0x00400000)
-#define MCF_INTC0_IMRL_INT_MASK23     (0x00800000)
-#define MCF_INTC0_IMRL_INT_MASK24     (0x01000000)
-#define MCF_INTC0_IMRL_INT_MASK25     (0x02000000)
-#define MCF_INTC0_IMRL_INT_MASK26     (0x04000000)
-#define MCF_INTC0_IMRL_INT_MASK27     (0x08000000)
-#define MCF_INTC0_IMRL_INT_MASK28     (0x10000000)
-#define MCF_INTC0_IMRL_INT_MASK29     (0x20000000)
-#define MCF_INTC0_IMRL_INT_MASK30     (0x40000000)
-#define MCF_INTC0_IMRL_INT_MASK31     (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC0_INTFRCH */
-#define MCF_INTC0_INTFRCH_INTFRC32    (0x00000001)
-#define MCF_INTC0_INTFRCH_INTFRC33    (0x00000002)
-#define MCF_INTC0_INTFRCH_INTFRC34    (0x00000004)
-#define MCF_INTC0_INTFRCH_INTFRC35    (0x00000008)
-#define MCF_INTC0_INTFRCH_INTFRC36    (0x00000010)
-#define MCF_INTC0_INTFRCH_INTFRC37    (0x00000020)
-#define MCF_INTC0_INTFRCH_INTFRC38    (0x00000040)
-#define MCF_INTC0_INTFRCH_INTFRC39    (0x00000080)
-#define MCF_INTC0_INTFRCH_INTFRC40    (0x00000100)
-#define MCF_INTC0_INTFRCH_INTFRC41    (0x00000200)
-#define MCF_INTC0_INTFRCH_INTFRC42    (0x00000400)
-#define MCF_INTC0_INTFRCH_INTFRC43    (0x00000800)
-#define MCF_INTC0_INTFRCH_INTFRC44    (0x00001000)
-#define MCF_INTC0_INTFRCH_INTFRC45    (0x00002000)
-#define MCF_INTC0_INTFRCH_INTFRC46    (0x00004000)
-#define MCF_INTC0_INTFRCH_INTFRC47    (0x00008000)
-#define MCF_INTC0_INTFRCH_INTFRC48    (0x00010000)
-#define MCF_INTC0_INTFRCH_INTFRC49    (0x00020000)
-#define MCF_INTC0_INTFRCH_INTFRC50    (0x00040000)
-#define MCF_INTC0_INTFRCH_INTFRC51    (0x00080000)
-#define MCF_INTC0_INTFRCH_INTFRC52    (0x00100000)
-#define MCF_INTC0_INTFRCH_INTFRC53    (0x00200000)
-#define MCF_INTC0_INTFRCH_INTFRC54    (0x00400000)
-#define MCF_INTC0_INTFRCH_INTFRC55    (0x00800000)
-#define MCF_INTC0_INTFRCH_INTFRC56    (0x01000000)
-#define MCF_INTC0_INTFRCH_INTFRC57    (0x02000000)
-#define MCF_INTC0_INTFRCH_INTFRC58    (0x04000000)
-#define MCF_INTC0_INTFRCH_INTFRC59    (0x08000000)
-#define MCF_INTC0_INTFRCH_INTFRC60    (0x10000000)
-#define MCF_INTC0_INTFRCH_INTFRC61    (0x20000000)
-#define MCF_INTC0_INTFRCH_INTFRC62    (0x40000000)
-#define MCF_INTC0_INTFRCH_INTFRC63    (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC0_INTFRCL */
-#define MCF_INTC0_INTFRCL_INTFRC1     (0x00000002)
-#define MCF_INTC0_INTFRCL_INTFRC2     (0x00000004)
-#define MCF_INTC0_INTFRCL_INTFRC3     (0x00000008)
-#define MCF_INTC0_INTFRCL_INTFRC4     (0x00000010)
-#define MCF_INTC0_INTFRCL_INTFRC5     (0x00000020)
-#define MCF_INTC0_INTFRCL_INT6        (0x00000040)
-#define MCF_INTC0_INTFRCL_INT7        (0x00000080)
-#define MCF_INTC0_INTFRCL_INT8        (0x00000100)
-#define MCF_INTC0_INTFRCL_INT9        (0x00000200)
-#define MCF_INTC0_INTFRCL_INT10       (0x00000400)
-#define MCF_INTC0_INTFRCL_INTFRC11    (0x00000800)
-#define MCF_INTC0_INTFRCL_INTFRC12    (0x00001000)
-#define MCF_INTC0_INTFRCL_INTFRC13    (0x00002000)
-#define MCF_INTC0_INTFRCL_INTFRC14    (0x00004000)
-#define MCF_INTC0_INTFRCL_INT15       (0x00008000)
-#define MCF_INTC0_INTFRCL_INTFRC16    (0x00010000)
-#define MCF_INTC0_INTFRCL_INTFRC17    (0x00020000)
-#define MCF_INTC0_INTFRCL_INTFRC18    (0x00040000)
-#define MCF_INTC0_INTFRCL_INTFRC19    (0x00080000)
-#define MCF_INTC0_INTFRCL_INTFRC20    (0x00100000)
-#define MCF_INTC0_INTFRCL_INTFRC21    (0x00200000)
-#define MCF_INTC0_INTFRCL_INTFRC22    (0x00400000)
-#define MCF_INTC0_INTFRCL_INTFRC23    (0x00800000)
-#define MCF_INTC0_INTFRCL_INTFRC24    (0x01000000)
-#define MCF_INTC0_INTFRCL_INTFRC25    (0x02000000)
-#define MCF_INTC0_INTFRCL_INTFRC26    (0x04000000)
-#define MCF_INTC0_INTFRCL_INTFRC27    (0x08000000)
-#define MCF_INTC0_INTFRCL_INTFRC28    (0x10000000)
-#define MCF_INTC0_INTFRCL_INTFRC29    (0x20000000)
-#define MCF_INTC0_INTFRCL_INTFRC30    (0x40000000)
-#define MCF_INTC0_INTFRCL_INTFRC31    (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC0_IRLR */
-#define MCF_INTC0_IRLR_IRQ(x)         (((x)&0x7F)<<1)
-
-/* Bit definitions and macros for MCF_INTC0_IACKLPR */
-#define MCF_INTC0_IACKLPR_PRI(x)      (((x)&0x0F)<<0)
-#define MCF_INTC0_IACKLPR_LEVEL(x)    (((x)&0x07)<<4)
-
-/* Bit definitions and macros for MCF_INTC0_ICRn */
-#define MCF_INTC0_ICRn_IP(x)          (((x)&0x07)<<0)
-#define MCF_INTC0_ICRn_IL(x)          (((x)&0x07)<<3)
-
-/********************************************************************/
-
-#endif /* __MCF523X_INTC0_H__ */
diff --git a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_intc1.h b/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_intc1.h
deleted file mode 100644
index 45613eaaf..000000000
--- a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_intc1.h
+++ /dev/null
@@ -1,323 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly 
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file 
- * LICENSE_FREESCALE.TXT.
- *
- * File:	mcf523x_intc1.h
- * Purpose:	Register and bit definitions for the MCF523X
- *
- * Notes:	
- *	
- */
-
-#ifndef __MCF523X_INTC1_H__
-#define __MCF523X_INTC1_H__
-
-/*********************************************************************
-*
-* Interrupt Controller 1 (INTC1)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_INTC1_IPRH         (*(vuint32*)(void*)(&__IPSBAR[0x000D00]))
-#define MCF_INTC1_IPRL         (*(vuint32*)(void*)(&__IPSBAR[0x000D04]))
-#define MCF_INTC1_IMRH         (*(vuint32*)(void*)(&__IPSBAR[0x000D08]))
-#define MCF_INTC1_IMRL         (*(vuint32*)(void*)(&__IPSBAR[0x000D0C]))
-#define MCF_INTC1_INTFRCH      (*(vuint32*)(void*)(&__IPSBAR[0x000D10]))
-#define MCF_INTC1_INTFRCL      (*(vuint32*)(void*)(&__IPSBAR[0x000D14]))
-#define MCF_INTC1_IRLR         (*(vuint8 *)(void*)(&__IPSBAR[0x000D18]))
-#define MCF_INTC1_IACKLPR      (*(vuint8 *)(void*)(&__IPSBAR[0x000D19]))
-#define MCF_INTC1_ICR0         (*(vuint8 *)(void*)(&__IPSBAR[0x000D40]))
-#define MCF_INTC1_ICR1         (*(vuint8 *)(void*)(&__IPSBAR[0x000D41]))
-#define MCF_INTC1_ICR2         (*(vuint8 *)(void*)(&__IPSBAR[0x000D42]))
-#define MCF_INTC1_ICR3         (*(vuint8 *)(void*)(&__IPSBAR[0x000D43]))
-#define MCF_INTC1_ICR4         (*(vuint8 *)(void*)(&__IPSBAR[0x000D44]))
-#define MCF_INTC1_ICR5         (*(vuint8 *)(void*)(&__IPSBAR[0x000D45]))
-#define MCF_INTC1_ICR6         (*(vuint8 *)(void*)(&__IPSBAR[0x000D46]))
-#define MCF_INTC1_ICR7         (*(vuint8 *)(void*)(&__IPSBAR[0x000D47]))
-#define MCF_INTC1_ICR8         (*(vuint8 *)(void*)(&__IPSBAR[0x000D48]))
-#define MCF_INTC1_ICR9         (*(vuint8 *)(void*)(&__IPSBAR[0x000D49]))
-#define MCF_INTC1_ICR10        (*(vuint8 *)(void*)(&__IPSBAR[0x000D4A]))
-#define MCF_INTC1_ICR11        (*(vuint8 *)(void*)(&__IPSBAR[0x000D4B]))
-#define MCF_INTC1_ICR12        (*(vuint8 *)(void*)(&__IPSBAR[0x000D4C]))
-#define MCF_INTC1_ICR13        (*(vuint8 *)(void*)(&__IPSBAR[0x000D4D]))
-#define MCF_INTC1_ICR14        (*(vuint8 *)(void*)(&__IPSBAR[0x000D4E]))
-#define MCF_INTC1_ICR15        (*(vuint8 *)(void*)(&__IPSBAR[0x000D4F]))
-#define MCF_INTC1_ICR16        (*(vuint8 *)(void*)(&__IPSBAR[0x000D50]))
-#define MCF_INTC1_ICR17        (*(vuint8 *)(void*)(&__IPSBAR[0x000D51]))
-#define MCF_INTC1_ICR18        (*(vuint8 *)(void*)(&__IPSBAR[0x000D52]))
-#define MCF_INTC1_ICR19        (*(vuint8 *)(void*)(&__IPSBAR[0x000D53]))
-#define MCF_INTC1_ICR20        (*(vuint8 *)(void*)(&__IPSBAR[0x000D54]))
-#define MCF_INTC1_ICR21        (*(vuint8 *)(void*)(&__IPSBAR[0x000D55]))
-#define MCF_INTC1_ICR22        (*(vuint8 *)(void*)(&__IPSBAR[0x000D56]))
-#define MCF_INTC1_ICR23        (*(vuint8 *)(void*)(&__IPSBAR[0x000D57]))
-#define MCF_INTC1_ICR24        (*(vuint8 *)(void*)(&__IPSBAR[0x000D58]))
-#define MCF_INTC1_ICR25        (*(vuint8 *)(void*)(&__IPSBAR[0x000D59]))
-#define MCF_INTC1_ICR26        (*(vuint8 *)(void*)(&__IPSBAR[0x000D5A]))
-#define MCF_INTC1_ICR27        (*(vuint8 *)(void*)(&__IPSBAR[0x000D5B]))
-#define MCF_INTC1_ICR28        (*(vuint8 *)(void*)(&__IPSBAR[0x000D5C]))
-#define MCF_INTC1_ICR29        (*(vuint8 *)(void*)(&__IPSBAR[0x000D5D]))
-#define MCF_INTC1_ICR30        (*(vuint8 *)(void*)(&__IPSBAR[0x000D5E]))
-#define MCF_INTC1_ICR31        (*(vuint8 *)(void*)(&__IPSBAR[0x000D5F]))
-#define MCF_INTC1_ICR32        (*(vuint8 *)(void*)(&__IPSBAR[0x000D60]))
-#define MCF_INTC1_ICR33        (*(vuint8 *)(void*)(&__IPSBAR[0x000D61]))
-#define MCF_INTC1_ICR34        (*(vuint8 *)(void*)(&__IPSBAR[0x000D62]))
-#define MCF_INTC1_ICR35        (*(vuint8 *)(void*)(&__IPSBAR[0x000D63]))
-#define MCF_INTC1_ICR36        (*(vuint8 *)(void*)(&__IPSBAR[0x000D64]))
-#define MCF_INTC1_ICR37        (*(vuint8 *)(void*)(&__IPSBAR[0x000D65]))
-#define MCF_INTC1_ICR38        (*(vuint8 *)(void*)(&__IPSBAR[0x000D66]))
-#define MCF_INTC1_ICR39        (*(vuint8 *)(void*)(&__IPSBAR[0x000D67]))
-#define MCF_INTC1_ICR40        (*(vuint8 *)(void*)(&__IPSBAR[0x000D68]))
-#define MCF_INTC1_ICR41        (*(vuint8 *)(void*)(&__IPSBAR[0x000D69]))
-#define MCF_INTC1_ICR42        (*(vuint8 *)(void*)(&__IPSBAR[0x000D6A]))
-#define MCF_INTC1_ICR43        (*(vuint8 *)(void*)(&__IPSBAR[0x000D6B]))
-#define MCF_INTC1_ICR44        (*(vuint8 *)(void*)(&__IPSBAR[0x000D6C]))
-#define MCF_INTC1_ICR45        (*(vuint8 *)(void*)(&__IPSBAR[0x000D6D]))
-#define MCF_INTC1_ICR46        (*(vuint8 *)(void*)(&__IPSBAR[0x000D6E]))
-#define MCF_INTC1_ICR47        (*(vuint8 *)(void*)(&__IPSBAR[0x000D6F]))
-#define MCF_INTC1_ICR48        (*(vuint8 *)(void*)(&__IPSBAR[0x000D70]))
-#define MCF_INTC1_ICR49        (*(vuint8 *)(void*)(&__IPSBAR[0x000D71]))
-#define MCF_INTC1_ICR50        (*(vuint8 *)(void*)(&__IPSBAR[0x000D72]))
-#define MCF_INTC1_ICR51        (*(vuint8 *)(void*)(&__IPSBAR[0x000D73]))
-#define MCF_INTC1_ICR52        (*(vuint8 *)(void*)(&__IPSBAR[0x000D74]))
-#define MCF_INTC1_ICR53        (*(vuint8 *)(void*)(&__IPSBAR[0x000D75]))
-#define MCF_INTC1_ICR54        (*(vuint8 *)(void*)(&__IPSBAR[0x000D76]))
-#define MCF_INTC1_ICR55        (*(vuint8 *)(void*)(&__IPSBAR[0x000D77]))
-#define MCF_INTC1_ICR56        (*(vuint8 *)(void*)(&__IPSBAR[0x000D78]))
-#define MCF_INTC1_ICR57        (*(vuint8 *)(void*)(&__IPSBAR[0x000D79]))
-#define MCF_INTC1_ICR58        (*(vuint8 *)(void*)(&__IPSBAR[0x000D7A]))
-#define MCF_INTC1_ICR59        (*(vuint8 *)(void*)(&__IPSBAR[0x000D7B]))
-#define MCF_INTC1_ICR60        (*(vuint8 *)(void*)(&__IPSBAR[0x000D7C]))
-#define MCF_INTC1_ICR61        (*(vuint8 *)(void*)(&__IPSBAR[0x000D7D]))
-#define MCF_INTC1_ICR62        (*(vuint8 *)(void*)(&__IPSBAR[0x000D7E]))
-#define MCF_INTC1_ICR63        (*(vuint8 *)(void*)(&__IPSBAR[0x000D7F]))
-#define MCF_INTC1_ICRn(x)      (*(vuint8 *)(void*)(&__IPSBAR[0x000D40+((x)*0x001)]))
-#define MCF_INTC1_SWIACK       (*(vuint8 *)(void*)(&__IPSBAR[0x000DE0]))
-#define MCF_INTC1_L1IACK       (*(vuint8 *)(void*)(&__IPSBAR[0x000DE4]))
-#define MCF_INTC1_L2IACK       (*(vuint8 *)(void*)(&__IPSBAR[0x000DE8]))
-#define MCF_INTC1_L3IACK       (*(vuint8 *)(void*)(&__IPSBAR[0x000DEC]))
-#define MCF_INTC1_L4IACK       (*(vuint8 *)(void*)(&__IPSBAR[0x000DF0]))
-#define MCF_INTC1_L5IACK       (*(vuint8 *)(void*)(&__IPSBAR[0x000DF4]))
-#define MCF_INTC1_L6IACK       (*(vuint8 *)(void*)(&__IPSBAR[0x000DF8]))
-#define MCF_INTC1_L7IACK       (*(vuint8 *)(void*)(&__IPSBAR[0x000DFC]))
-#define MCF_INTC1_LnIACK(x)    (*(vuint8 *)(void*)(&__IPSBAR[0x000DE4+((x)*0x004)]))
-
-/* Bit definitions and macros for MCF_INTC1_IPRH */
-#define MCF_INTC1_IPRH_INT32          (0x00000001)
-#define MCF_INTC1_IPRH_INT33          (0x00000002)
-#define MCF_INTC1_IPRH_INT34          (0x00000004)
-#define MCF_INTC1_IPRH_INT35          (0x00000008)
-#define MCF_INTC1_IPRH_INT36          (0x00000010)
-#define MCF_INTC1_IPRH_INT37          (0x00000020)
-#define MCF_INTC1_IPRH_INT38          (0x00000040)
-#define MCF_INTC1_IPRH_INT39          (0x00000080)
-#define MCF_INTC1_IPRH_INT40          (0x00000100)
-#define MCF_INTC1_IPRH_INT41          (0x00000200)
-#define MCF_INTC1_IPRH_INT42          (0x00000400)
-#define MCF_INTC1_IPRH_INT43          (0x00000800)
-#define MCF_INTC1_IPRH_INT44          (0x00001000)
-#define MCF_INTC1_IPRH_INT45          (0x00002000)
-#define MCF_INTC1_IPRH_INT46          (0x00004000)
-#define MCF_INTC1_IPRH_INT47          (0x00008000)
-#define MCF_INTC1_IPRH_INT48          (0x00010000)
-#define MCF_INTC1_IPRH_INT49          (0x00020000)
-#define MCF_INTC1_IPRH_INT50          (0x00040000)
-#define MCF_INTC1_IPRH_INT51          (0x00080000)
-#define MCF_INTC1_IPRH_INT52          (0x00100000)
-#define MCF_INTC1_IPRH_INT53          (0x00200000)
-#define MCF_INTC1_IPRH_INT54          (0x00400000)
-#define MCF_INTC1_IPRH_INT55          (0x00800000)
-#define MCF_INTC1_IPRH_INT56          (0x01000000)
-#define MCF_INTC1_IPRH_INT57          (0x02000000)
-#define MCF_INTC1_IPRH_INT58          (0x04000000)
-#define MCF_INTC1_IPRH_INT59          (0x08000000)
-#define MCF_INTC1_IPRH_INT60          (0x10000000)
-#define MCF_INTC1_IPRH_INT61          (0x20000000)
-#define MCF_INTC1_IPRH_INT62          (0x40000000)
-#define MCF_INTC1_IPRH_INT63          (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC1_IPRL */
-#define MCF_INTC1_IPRL_INT1           (0x00000002)
-#define MCF_INTC1_IPRL_INT2           (0x00000004)
-#define MCF_INTC1_IPRL_INT3           (0x00000008)
-#define MCF_INTC1_IPRL_INT4           (0x00000010)
-#define MCF_INTC1_IPRL_INT5           (0x00000020)
-#define MCF_INTC1_IPRL_INT6           (0x00000040)
-#define MCF_INTC1_IPRL_INT7           (0x00000080)
-#define MCF_INTC1_IPRL_INT8           (0x00000100)
-#define MCF_INTC1_IPRL_INT9           (0x00000200)
-#define MCF_INTC1_IPRL_INT10          (0x00000400)
-#define MCF_INTC1_IPRL_INT11          (0x00000800)
-#define MCF_INTC1_IPRL_INT12          (0x00001000)
-#define MCF_INTC1_IPRL_INT13          (0x00002000)
-#define MCF_INTC1_IPRL_INT14          (0x00004000)
-#define MCF_INTC1_IPRL_INT15          (0x00008000)
-#define MCF_INTC1_IPRL_INT16          (0x00010000)
-#define MCF_INTC1_IPRL_INT17          (0x00020000)
-#define MCF_INTC1_IPRL_INT18          (0x00040000)
-#define MCF_INTC1_IPRL_INT19          (0x00080000)
-#define MCF_INTC1_IPRL_INT20          (0x00100000)
-#define MCF_INTC1_IPRL_INT21          (0x00200000)
-#define MCF_INTC1_IPRL_INT22          (0x00400000)
-#define MCF_INTC1_IPRL_INT23          (0x00800000)
-#define MCF_INTC1_IPRL_INT24          (0x01000000)
-#define MCF_INTC1_IPRL_INT25          (0x02000000)
-#define MCF_INTC1_IPRL_INT26          (0x04000000)
-#define MCF_INTC1_IPRL_INT27          (0x08000000)
-#define MCF_INTC1_IPRL_INT28          (0x10000000)
-#define MCF_INTC1_IPRL_INT29          (0x20000000)
-#define MCF_INTC1_IPRL_INT30          (0x40000000)
-#define MCF_INTC1_IPRL_INT31          (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC1_IMRH */
-#define MCF_INTC1_IMRH_INT_MASK32     (0x00000001)
-#define MCF_INTC1_IMRH_INT_MASK33     (0x00000002)
-#define MCF_INTC1_IMRH_INT_MASK34     (0x00000004)
-#define MCF_INTC1_IMRH_INT_MASK35     (0x00000008)
-#define MCF_INTC1_IMRH_INT_MASK36     (0x00000010)
-#define MCF_INTC1_IMRH_INT_MASK37     (0x00000020)
-#define MCF_INTC1_IMRH_INT_MASK38     (0x00000040)
-#define MCF_INTC1_IMRH_INT_MASK39     (0x00000080)
-#define MCF_INTC1_IMRH_INT_MASK40     (0x00000100)
-#define MCF_INTC1_IMRH_INT_MASK41     (0x00000200)
-#define MCF_INTC1_IMRH_INT_MASK42     (0x00000400)
-#define MCF_INTC1_IMRH_INT_MASK43     (0x00000800)
-#define MCF_INTC1_IMRH_INT_MASK44     (0x00001000)
-#define MCF_INTC1_IMRH_INT_MASK45     (0x00002000)
-#define MCF_INTC1_IMRH_INT_MASK46     (0x00004000)
-#define MCF_INTC1_IMRH_INT_MASK47     (0x00008000)
-#define MCF_INTC1_IMRH_INT_MASK48     (0x00010000)
-#define MCF_INTC1_IMRH_INT_MASK49     (0x00020000)
-#define MCF_INTC1_IMRH_INT_MASK50     (0x00040000)
-#define MCF_INTC1_IMRH_INT_MASK51     (0x00080000)
-#define MCF_INTC1_IMRH_INT_MASK52     (0x00100000)
-#define MCF_INTC1_IMRH_INT_MASK53     (0x00200000)
-#define MCF_INTC1_IMRH_INT_MASK54     (0x00400000)
-#define MCF_INTC1_IMRH_INT_MASK55     (0x00800000)
-#define MCF_INTC1_IMRH_INT_MASK56     (0x01000000)
-#define MCF_INTC1_IMRH_INT_MASK57     (0x02000000)
-#define MCF_INTC1_IMRH_INT_MASK58     (0x04000000)
-#define MCF_INTC1_IMRH_INT_MASK59     (0x08000000)
-#define MCF_INTC1_IMRH_INT_MASK60     (0x10000000)
-#define MCF_INTC1_IMRH_INT_MASK61     (0x20000000)
-#define MCF_INTC1_IMRH_INT_MASK62     (0x40000000)
-#define MCF_INTC1_IMRH_INT_MASK63     (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC1_IMRL */
-#define MCF_INTC1_IMRL_MASKALL        (0x00000001)
-#define MCF_INTC1_IMRL_INT_MASK1      (0x00000002)
-#define MCF_INTC1_IMRL_INT_MASK2      (0x00000004)
-#define MCF_INTC1_IMRL_INT_MASK3      (0x00000008)
-#define MCF_INTC1_IMRL_INT_MASK4      (0x00000010)
-#define MCF_INTC1_IMRL_INT_MASK5      (0x00000020)
-#define MCF_INTC1_IMRL_INT_MASK6      (0x00000040)
-#define MCF_INTC1_IMRL_INT_MASK7      (0x00000080)
-#define MCF_INTC1_IMRL_INT_MASK8      (0x00000100)
-#define MCF_INTC1_IMRL_INT_MASK9      (0x00000200)
-#define MCF_INTC1_IMRL_INT_MASK10     (0x00000400)
-#define MCF_INTC1_IMRL_INT_MASK11     (0x00000800)
-#define MCF_INTC1_IMRL_INT_MASK12     (0x00001000)
-#define MCF_INTC1_IMRL_INT_MASK13     (0x00002000)
-#define MCF_INTC1_IMRL_INT_MASK14     (0x00004000)
-#define MCF_INTC1_IMRL_INT_MASK15     (0x00008000)
-#define MCF_INTC1_IMRL_INT_MASK16     (0x00010000)
-#define MCF_INTC1_IMRL_INT_MASK17     (0x00020000)
-#define MCF_INTC1_IMRL_INT_MASK18     (0x00040000)
-#define MCF_INTC1_IMRL_INT_MASK19     (0x00080000)
-#define MCF_INTC1_IMRL_INT_MASK20     (0x00100000)
-#define MCF_INTC1_IMRL_INT_MASK21     (0x00200000)
-#define MCF_INTC1_IMRL_INT_MASK22     (0x00400000)
-#define MCF_INTC1_IMRL_INT_MASK23     (0x00800000)
-#define MCF_INTC1_IMRL_INT_MASK24     (0x01000000)
-#define MCF_INTC1_IMRL_INT_MASK25     (0x02000000)
-#define MCF_INTC1_IMRL_INT_MASK26     (0x04000000)
-#define MCF_INTC1_IMRL_INT_MASK27     (0x08000000)
-#define MCF_INTC1_IMRL_INT_MASK28     (0x10000000)
-#define MCF_INTC1_IMRL_INT_MASK29     (0x20000000)
-#define MCF_INTC1_IMRL_INT_MASK30     (0x40000000)
-#define MCF_INTC1_IMRL_INT_MASK31     (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC1_INTFRCH */
-#define MCF_INTC1_INTFRCH_INTFRC32    (0x00000001)
-#define MCF_INTC1_INTFRCH_INTFRC33    (0x00000002)
-#define MCF_INTC1_INTFRCH_INTFRC34    (0x00000004)
-#define MCF_INTC1_INTFRCH_INTFRC35    (0x00000008)
-#define MCF_INTC1_INTFRCH_INTFRC36    (0x00000010)
-#define MCF_INTC1_INTFRCH_INTFRC37    (0x00000020)
-#define MCF_INTC1_INTFRCH_INTFRC38    (0x00000040)
-#define MCF_INTC1_INTFRCH_INTFRC39    (0x00000080)
-#define MCF_INTC1_INTFRCH_INTFRC40    (0x00000100)
-#define MCF_INTC1_INTFRCH_INTFRC41    (0x00000200)
-#define MCF_INTC1_INTFRCH_INTFRC42    (0x00000400)
-#define MCF_INTC1_INTFRCH_INTFRC43    (0x00000800)
-#define MCF_INTC1_INTFRCH_INTFRC44    (0x00001000)
-#define MCF_INTC1_INTFRCH_INTFRC45    (0x00002000)
-#define MCF_INTC1_INTFRCH_INTFRC46    (0x00004000)
-#define MCF_INTC1_INTFRCH_INTFRC47    (0x00008000)
-#define MCF_INTC1_INTFRCH_INTFRC48    (0x00010000)
-#define MCF_INTC1_INTFRCH_INTFRC49    (0x00020000)
-#define MCF_INTC1_INTFRCH_INTFRC50    (0x00040000)
-#define MCF_INTC1_INTFRCH_INTFRC51    (0x00080000)
-#define MCF_INTC1_INTFRCH_INTFRC52    (0x00100000)
-#define MCF_INTC1_INTFRCH_INTFRC53    (0x00200000)
-#define MCF_INTC1_INTFRCH_INTFRC54    (0x00400000)
-#define MCF_INTC1_INTFRCH_INTFRC55    (0x00800000)
-#define MCF_INTC1_INTFRCH_INTFRC56    (0x01000000)
-#define MCF_INTC1_INTFRCH_INTFRC57    (0x02000000)
-#define MCF_INTC1_INTFRCH_INTFRC58    (0x04000000)
-#define MCF_INTC1_INTFRCH_INTFRC59    (0x08000000)
-#define MCF_INTC1_INTFRCH_INTFRC60    (0x10000000)
-#define MCF_INTC1_INTFRCH_INTFRC61    (0x20000000)
-#define MCF_INTC1_INTFRCH_INTFRC62    (0x40000000)
-#define MCF_INTC1_INTFRCH_INTFRC63    (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC1_INTFRCL */
-#define MCF_INTC1_INTFRCL_INTFRC1     (0x00000002)
-#define MCF_INTC1_INTFRCL_INTFRC2     (0x00000004)
-#define MCF_INTC1_INTFRCL_INTFRC3     (0x00000008)
-#define MCF_INTC1_INTFRCL_INTFRC4     (0x00000010)
-#define MCF_INTC1_INTFRCL_INTFRC5     (0x00000020)
-#define MCF_INTC1_INTFRCL_INT6        (0x00000040)
-#define MCF_INTC1_INTFRCL_INT7        (0x00000080)
-#define MCF_INTC1_INTFRCL_INT8        (0x00000100)
-#define MCF_INTC1_INTFRCL_INT9        (0x00000200)
-#define MCF_INTC1_INTFRCL_INT10       (0x00000400)
-#define MCF_INTC1_INTFRCL_INTFRC11    (0x00000800)
-#define MCF_INTC1_INTFRCL_INTFRC12    (0x00001000)
-#define MCF_INTC1_INTFRCL_INTFRC13    (0x00002000)
-#define MCF_INTC1_INTFRCL_INTFRC14    (0x00004000)
-#define MCF_INTC1_INTFRCL_INT15       (0x00008000)
-#define MCF_INTC1_INTFRCL_INTFRC16    (0x00010000)
-#define MCF_INTC1_INTFRCL_INTFRC17    (0x00020000)
-#define MCF_INTC1_INTFRCL_INTFRC18    (0x00040000)
-#define MCF_INTC1_INTFRCL_INTFRC19    (0x00080000)
-#define MCF_INTC1_INTFRCL_INTFRC20    (0x00100000)
-#define MCF_INTC1_INTFRCL_INTFRC21    (0x00200000)
-#define MCF_INTC1_INTFRCL_INTFRC22    (0x00400000)
-#define MCF_INTC1_INTFRCL_INTFRC23    (0x00800000)
-#define MCF_INTC1_INTFRCL_INTFRC24    (0x01000000)
-#define MCF_INTC1_INTFRCL_INTFRC25    (0x02000000)
-#define MCF_INTC1_INTFRCL_INTFRC26    (0x04000000)
-#define MCF_INTC1_INTFRCL_INTFRC27    (0x08000000)
-#define MCF_INTC1_INTFRCL_INTFRC28    (0x10000000)
-#define MCF_INTC1_INTFRCL_INTFRC29    (0x20000000)
-#define MCF_INTC1_INTFRCL_INTFRC30    (0x40000000)
-#define MCF_INTC1_INTFRCL_INTFRC31    (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC1_IRLR */
-#define MCF_INTC1_IRLR_IRQ(x)         (((x)&0x7F)<<1)
-
-/* Bit definitions and macros for MCF_INTC1_IACKLPR */
-#define MCF_INTC1_IACKLPR_PRI(x)      (((x)&0x0F)<<0)
-#define MCF_INTC1_IACKLPR_LEVEL(x)    (((x)&0x07)<<4)
-
-/* Bit definitions and macros for MCF_INTC1_ICRn */
-#define MCF_INTC1_ICRn_IP(x)          (((x)&0x07)<<0)
-#define MCF_INTC1_ICRn_IL(x)          (((x)&0x07)<<3)
-
-/********************************************************************/
-
-#endif /* __MCF523X_INTC1_H__ */
diff --git a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_mdha.h b/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_mdha.h
deleted file mode 100644
index adc714f6d..000000000
--- a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_mdha.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly 
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file 
- * LICENSE_FREESCALE.TXT.
- *
- * File:	mcf523x_mdha.h
- * Purpose:	Register and bit definitions for the MCF523X
- *
- * Notes:	
- *	
- */
-
-#ifndef __MCF523X_MDHA_H__
-#define __MCF523X_MDHA_H__
-
-/*********************************************************************
-*
-* Message Digest Hardware Accelerator (MDHA)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_MDHA_MDMR     (*(vuint32*)(void*)(&__IPSBAR[0x190000]))
-#define MCF_MDHA_MDCR     (*(vuint32*)(void*)(&__IPSBAR[0x190004]))
-#define MCF_MDHA_MDCMR    (*(vuint32*)(void*)(&__IPSBAR[0x190008]))
-#define MCF_MDHA_MDSR     (*(vuint32*)(void*)(&__IPSBAR[0x19000C]))
-#define MCF_MDHA_MDISR     (*(vuint32*)(void*)(&__IPSBAR[0x190010]))
-#define MCF_MDHA_MDIMR    (*(vuint32*)(void*)(&__IPSBAR[0x190014]))
-#define MCF_MDHA_MDDSR    (*(vuint32*)(void*)(&__IPSBAR[0x19001C]))
-#define MCF_MDHA_MDIN     (*(vuint32*)(void*)(&__IPSBAR[0x190020]))
-#define MCF_MDHA_MDA0     (*(vuint32*)(void*)(&__IPSBAR[0x190030]))
-#define MCF_MDHA_MDB0     (*(vuint32*)(void*)(&__IPSBAR[0x190034]))
-#define MCF_MDHA_MDC0     (*(vuint32*)(void*)(&__IPSBAR[0x190038]))
-#define MCF_MDHA_MDD0     (*(vuint32*)(void*)(&__IPSBAR[0x19003C]))
-#define MCF_MDHA_MDE0     (*(vuint32*)(void*)(&__IPSBAR[0x190040]))
-#define MCF_MDHA_MDMDS    (*(vuint32*)(void*)(&__IPSBAR[0x190044]))
-#define MCF_MDHA_MDA1     (*(vuint32*)(void*)(&__IPSBAR[0x190070]))
-#define MCF_MDHA_MDB1     (*(vuint32*)(void*)(&__IPSBAR[0x190074]))
-#define MCF_MDHA_MDC1     (*(vuint32*)(void*)(&__IPSBAR[0x190078]))
-#define MCF_MDHA_MDD1     (*(vuint32*)(void*)(&__IPSBAR[0x19007C]))
-#define MCF_MDHA_MDE1     (*(vuint32*)(void*)(&__IPSBAR[0x190080]))
-
-/* Bit definitions and macros for MCF_MDHA_MDMR */
-#define MCF_MDHA_MDMR_ALG             (0x00000001)
-#define MCF_MDHA_MDMR_PDATA           (0x00000004)
-#define MCF_MDHA_MDMR_MAC(x)          (((x)&0x00000003)<<3)
-#define MCF_MDHA_MDMR_INIT            (0x00000020)
-#define MCF_MDHA_MDMR_IPAD            (0x00000040)
-#define MCF_MDHA_MDMR_OPAD            (0x00000080)
-#define MCF_MDHA_MDMR_SWAP            (0x00000100)
-#define MCF_MDHA_MDMR_MACFULL         (0x00000200)
-#define MCF_MDHA_MDMR_SSL             (0x00000400)
-
-/* Bit definitions and macros for MCF_MDHA_MDCR */
-#define MCF_MDHA_MDCR_IE              (0x00000001)
-
-/* Bit definitions and macros for MCF_MDHA_MDCMR */
-#define MCF_MDHA_MDCMR_SWR             (0x00000001)
-#define MCF_MDHA_MDCMR_RI             (0x00000002)
-#define MCF_MDHA_MDCMR_CI             (0x00000004)
-#define MCF_MDHA_MDCMR_GO             (0x00000008)
-
-/* Bit definitions and macros for MCF_MDHA_MDSR */
-#define MCF_MDHA_MDSR_INT             (0x00000001)
-#define MCF_MDHA_MDSR_DONE            (0x00000002)
-#define MCF_MDHA_MDSR_ERR             (0x00000004)
-#define MCF_MDHA_MDSR_RD              (0x00000008)
-#define MCF_MDHA_MDSR_BUSY            (0x00000010)
-#define MCF_MDHA_MDSR_END             (0x00000020)
-#define MCF_MDHA_MDSR_HSH             (0x00000040)
-#define MCF_MDHA_MDSR_GNW             (0x00000080)
-#define MCF_MDHA_MDSR_FS(x)           (((x)&0x00000007)<<8)
-#define MCF_MDHA_MDSR_APD(x)          (((x)&0x00000007)<<13)
-#define MCF_MDHA_MDSR_IFL(x)          (((x)&0x000000FF)<<16)
-
-/* Bit definitions and macros for MCF_MDHA_MDIR */
-#define MCF_MDHA_MDIR_IFO             (0x00000001)
-#define MCF_MDHA_MDIR_NON             (0x00000004)
-#define MCF_MDHA_MDIR_IME             (0x00000010)
-#define MCF_MDHA_MDIR_IDS             (0x00000020)
-#define MCF_MDHA_MDIR_RMDP            (0x00000080)
-#define MCF_MDHA_MDIR_ERE             (0x00000100)
-#define MCF_MDHA_MDIR_GTDS            (0x00000200)
-
-/* Bit definitions and macros for MCF_MDHA_MDIMR */
-#define MCF_MDHA_MDIMR_IFO            (0x00000001)
-#define MCF_MDHA_MDIMR_NON            (0x00000004)
-#define MCF_MDHA_MDIMR_IME            (0x00000010)
-#define MCF_MDHA_MDIMR_IDS            (0x00000020)
-#define MCF_MDHA_MDIMR_RMDP           (0x00000080)
-#define MCF_MDHA_MDIMR_ERE            (0x00000100)
-#define MCF_MDHA_MDIMR_GTDS           (0x00000200)
-
-/* Bit definitions and macros for MCF_MDHA_MDDSR */
-#define MCF_MDHA_MDDSR_DATASIZE(x)    (((x)&0x1FFFFFFF)<<0)
-
-/********************************************************************/
-
-#endif /* __MCF523X_MDHA_H__ */
diff --git a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_pit.h b/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_pit.h
deleted file mode 100644
index 0763d20f2..000000000
--- a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_pit.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly 
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file 
- * LICENSE_FREESCALE.TXT.
- *
- * File:	mcf523x_pit.h
- * Purpose:	Register and bit definitions for the MCF523X
- *
- * Notes:	
- *	
- */
-
-#ifndef __MCF523X_PIT_H__
-#define __MCF523X_PIT_H__
-
-/*********************************************************************
-*
-* Programmable Interrupt Timer Modules (PIT)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_PIT_PCSR0       (*(vuint16*)(void*)(&__IPSBAR[0x150000]))
-#define MCF_PIT_PMR0        (*(vuint16*)(void*)(&__IPSBAR[0x150002]))
-#define MCF_PIT_PCNTR0      (*(vuint16*)(void*)(&__IPSBAR[0x150004]))
-#define MCF_PIT_PCSR1       (*(vuint16*)(void*)(&__IPSBAR[0x160000]))
-#define MCF_PIT_PMR1        (*(vuint16*)(void*)(&__IPSBAR[0x160002]))
-#define MCF_PIT_PCNTR1      (*(vuint16*)(void*)(&__IPSBAR[0x160004]))
-#define MCF_PIT_PCSR2       (*(vuint16*)(void*)(&__IPSBAR[0x170000]))
-#define MCF_PIT_PMR2        (*(vuint16*)(void*)(&__IPSBAR[0x170002]))
-#define MCF_PIT_PCNTR2      (*(vuint16*)(void*)(&__IPSBAR[0x170004]))
-#define MCF_PIT_PCSR3       (*(vuint16*)(void*)(&__IPSBAR[0x180000]))
-#define MCF_PIT_PMR3        (*(vuint16*)(void*)(&__IPSBAR[0x180002]))
-#define MCF_PIT_PCNTR3      (*(vuint16*)(void*)(&__IPSBAR[0x180004]))
-#define MCF_PIT_PCSR(x)     (*(vuint16*)(void*)(&__IPSBAR[0x150000+((x)*0x10000)]))
-#define MCF_PIT_PMR(x)      (*(vuint16*)(void*)(&__IPSBAR[0x150002+((x)*0x10000)]))
-#define MCF_PIT_PCNTR(x)    (*(vuint16*)(void*)(&__IPSBAR[0x150004+((x)*0x10000)]))
-
-/* Bit definitions and macros for MCF_PIT_PCSR */
-#define MCF_PIT_PCSR_EN        (0x0001)
-#define MCF_PIT_PCSR_RLD       (0x0002)
-#define MCF_PIT_PCSR_PIF       (0x0004)
-#define MCF_PIT_PCSR_PIE       (0x0008)
-#define MCF_PIT_PCSR_OVW       (0x0010)
-#define MCF_PIT_PCSR_HALTED    (0x0020)
-#define MCF_PIT_PCSR_DOZE      (0x0040)
-#define MCF_PIT_PCSR_PRE(x)    (((x)&0x000F)<<8)
-
-/* Bit definitions and macros for MCF_PIT_PMR */
-#define MCF_PIT_PMR_PM0        (0x0001)
-#define MCF_PIT_PMR_PM1        (0x0002)
-#define MCF_PIT_PMR_PM2        (0x0004)
-#define MCF_PIT_PMR_PM3        (0x0008)
-#define MCF_PIT_PMR_PM4        (0x0010)
-#define MCF_PIT_PMR_PM5        (0x0020)
-#define MCF_PIT_PMR_PM6        (0x0040)
-#define MCF_PIT_PMR_PM7        (0x0080)
-#define MCF_PIT_PMR_PM8        (0x0100)
-#define MCF_PIT_PMR_PM9        (0x0200)
-#define MCF_PIT_PMR_PM10       (0x0400)
-#define MCF_PIT_PMR_PM11       (0x0800)
-#define MCF_PIT_PMR_PM12       (0x1000)
-#define MCF_PIT_PMR_PM13       (0x2000)
-#define MCF_PIT_PMR_PM14       (0x4000)
-#define MCF_PIT_PMR_PM15       (0x8000)
-
-/* Bit definitions and macros for MCF_PIT_PCNTR */
-#define MCF_PIT_PCNTR_PC0      (0x0001)
-#define MCF_PIT_PCNTR_PC1      (0x0002)
-#define MCF_PIT_PCNTR_PC2      (0x0004)
-#define MCF_PIT_PCNTR_PC3      (0x0008)
-#define MCF_PIT_PCNTR_PC4      (0x0010)
-#define MCF_PIT_PCNTR_PC5      (0x0020)
-#define MCF_PIT_PCNTR_PC6      (0x0040)
-#define MCF_PIT_PCNTR_PC7      (0x0080)
-#define MCF_PIT_PCNTR_PC8      (0x0100)
-#define MCF_PIT_PCNTR_PC9      (0x0200)
-#define MCF_PIT_PCNTR_PC10     (0x0400)
-#define MCF_PIT_PCNTR_PC11     (0x0800)
-#define MCF_PIT_PCNTR_PC12     (0x1000)
-#define MCF_PIT_PCNTR_PC13     (0x2000)
-#define MCF_PIT_PCNTR_PC14     (0x4000)
-#define MCF_PIT_PCNTR_PC15     (0x8000)
-
-/********************************************************************/
-
-#endif /* __MCF523X_PIT_H__ */
diff --git a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_qspi.h b/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_qspi.h
deleted file mode 100644
index ed32d6d40..000000000
--- a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_qspi.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly 
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file 
- * LICENSE_FREESCALE.TXT.
- *
- * File:	mcf523x_qspi.h
- * Purpose:	Register and bit definitions for the MCF523X
- *
- * Notes:	
- *	
- */
-
-#ifndef __MCF523X_QSPI_H__
-#define __MCF523X_QSPI_H__
-
-/*********************************************************************
-*
-* Queued Serial Peripheral Interface (QSPI)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_QSPI_QMR      (*(vuint16*)(void*)(&__IPSBAR[0x000340]))
-#define MCF_QSPI_QDLYR    (*(vuint16*)(void*)(&__IPSBAR[0x000344]))
-#define MCF_QSPI_QWR      (*(vuint16*)(void*)(&__IPSBAR[0x000348]))
-#define MCF_QSPI_QIR      (*(vuint16*)(void*)(&__IPSBAR[0x00034C]))
-#define MCF_QSPI_QAR      (*(vuint16*)(void*)(&__IPSBAR[0x000350]))
-#define MCF_QSPI_QDR      (*(vuint16*)(void*)(&__IPSBAR[0x000354]))
-
-/* Bit definitions and macros for MCF_QSPI_QMR */
-#define MCF_QSPI_QMR_BAUD(x)     (((x)&0x00FF)<<0)
-#define MCF_QSPI_QMR_CPHA        (0x0100)
-#define MCF_QSPI_QMR_CPOL        (0x0200)
-#define MCF_QSPI_QMR_BITS(x)     (((x)&0x000F)<<10)
-#define MCF_QSPI_QMR_DOHIE       (0x4000)
-#define MCF_QSPI_QMR_MSTR        (0x8000)
-
-/* Bit definitions and macros for MCF_QSPI_QDLYR */
-#define MCF_QSPI_QDLYR_DTL(x)    (((x)&0x00FF)<<0)
-#define MCF_QSPI_QDLYR_QCD(x)    (((x)&0x007F)<<8)
-#define MCF_QSPI_QDLYR_SPE       (0x8000)
-
-/* Bit definitions and macros for MCF_QSPI_QWR */
-#define MCF_QSPI_QWR_NEWQP(x)    (((x)&0x000F)<<0)
-#define MCF_QSPI_QWR_ENDQP(x)    (((x)&0x000F)<<8)
-#define MCF_QSPI_QWR_CSIV        (0x1000)
-#define MCF_QSPI_QWR_WRTO        (0x2000)
-#define MCF_QSPI_QWR_WREN        (0x4000)
-#define MCF_QSPI_QWR_HALT        (0x8000)
-
-/* Bit definitions and macros for MCF_QSPI_QIR */
-#define MCF_QSPI_QIR_SPIF        (0x0001)
-#define MCF_QSPI_QIR_ABRT        (0x0004)
-#define MCF_QSPI_QIR_WCEF        (0x0008)
-#define MCF_QSPI_QIR_SPIFE       (0x0100)
-#define MCF_QSPI_QIR_ABRTE       (0x0400)
-#define MCF_QSPI_QIR_WCEFE       (0x0800)
-#define MCF_QSPI_QIR_ABRTL       (0x1000)
-#define MCF_QSPI_QIR_ABRTB       (0x4000)
-#define MCF_QSPI_QIR_WCEFB       (0x8000)
-
-/* Bit definitions and macros for MCF_QSPI_QAR */
-#define MCF_QSPI_QAR_ADDR(x)     (((x)&0x003F)<<0)
-
-/********************************************************************/
-
-#endif /* __MCF523X_QSPI_H__ */
diff --git a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_rcm.h b/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_rcm.h
deleted file mode 100644
index 784d0fab0..000000000
--- a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_rcm.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly 
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file 
- * LICENSE_FREESCALE.TXT.
- *
- * File:	mcf523x_rcm.h
- * Purpose:	Register and bit definitions for the MCF523X
- *
- * Notes:	
- *	
- */
-
-#ifndef __MCF523X_RCM_H__
-#define __MCF523X_RCM_H__
-
-/*********************************************************************
-*
-* Reset Configuration Module (RCM)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_RCM_RCR    (*(vuint8 *)(void*)(&__IPSBAR[0x110000]))
-#define MCF_RCM_RSR    (*(vuint8 *)(void*)(&__IPSBAR[0x110001]))
-
-/* Bit definitions and macros for MCF_RCM_RCR */
-#define MCF_RCM_RCR_FRCRSTOUT    (0x40)
-#define MCF_RCM_RCR_SOFTRST      (0x80)
-
-/* Bit definitions and macros for MCF_RCM_RSR */
-#define MCF_RCM_RSR_LOL          (0x01)
-#define MCF_RCM_RSR_LOC          (0x02)
-#define MCF_RCM_RSR_EXT          (0x04)
-#define MCF_RCM_RSR_POR          (0x08)
-#define MCF_RCM_RSR_WDR          (0x10)
-#define MCF_RCM_RSR_SOFT         (0x20)
-
-/********************************************************************/
-
-#endif /* __MCF523X_RCM_H__ */
diff --git a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_rng.h b/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_rng.h
deleted file mode 100644
index 744bd0ae3..000000000
--- a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_rng.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly 
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file 
- * LICENSE_FREESCALE.TXT.
- *
- * File:	mcf523x_rng.h
- * Purpose:	Register and bit definitions for the MCF523X
- *
- * Notes:	
- *	
- */
-
-#ifndef __MCF523X_RNG_H__
-#define __MCF523X_RNG_H__
-
-/*********************************************************************
-*
-* Random Number Generator (RNG)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_RNG_RNGCR     (*(vuint32*)(void*)(&__IPSBAR[0x1A0000]))
-#define MCF_RNG_RNGSR     (*(vuint32*)(void*)(&__IPSBAR[0x1A0004]))
-#define MCF_RNG_RNGER     (*(vuint32*)(void*)(&__IPSBAR[0x1A0008]))
-#define MCF_RNG_RNGOUT    (*(vuint32*)(void*)(&__IPSBAR[0x1A000C]))
-
-/* Bit definitions and macros for MCF_RNG_RNGCR */
-#define MCF_RNG_RNGCR_GO        (0x00000001)
-#define MCF_RNG_RNGCR_HA        (0x00000002)
-#define MCF_RNG_RNGCR_IM        (0x00000004)
-#define MCF_RNG_RNGCR_CI        (0x00000008)
-
-/* Bit definitions and macros for MCF_RNG_RNGSR */
-#define MCF_RNG_RNGSR_SV        (0x00000001)
-#define MCF_RNG_RNGSR_LRS       (0x00000002)
-#define MCF_RNG_RNGSR_FUF       (0x00000004)
-#define MCF_RNG_RNGSR_EI        (0x00000008)
-#define MCF_RNG_RNGSR_OFL(x)    (((x)&0x000000FF)<<8)
-#define MCF_RNG_RNGSR_OFS(x)    (((x)&0x000000FF)<<16)
-
-/********************************************************************/
-
-#endif /* __MCF523X_RNG_H__ */
diff --git a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_scm.h b/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_scm.h
deleted file mode 100644
index d9ef0f0eb..000000000
--- a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_scm.h
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly 
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file 
- * LICENSE_FREESCALE.TXT.
- *
- * File:	mcf523x_scm.h
- * Purpose:	Register and bit definitions for the MCF523X
- *
- * Notes:	
- *	
- */
-
-#ifndef __MCF523X_SCM_H__
-#define __MCF523X_SCM_H__
-
-/*********************************************************************
-*
-* System Control Module (SCM)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_SCM_IPSBAR     (*(vuint32*)(void*)(&__IPSBAR[0x000000]))
-#define MCF_SCM_RAMBAR     (*(vuint32*)(void*)(&__IPSBAR[0x000008]))
-#define MCF_SCM_CRSR       (*(vuint8 *)(void*)(&__IPSBAR[0x000010]))
-#define MCF_SCM_CWCR       (*(vuint8 *)(void*)(&__IPSBAR[0x000011]))
-#define MCF_SCM_LPICR      (*(vuint8 *)(void*)(&__IPSBAR[0x000012]))
-#define MCF_SCM_CWSR       (*(vuint8 *)(void*)(&__IPSBAR[0x000013]))
-#define MCF_SCM_DMAREQC    (*(vuint32*)(void*)(&__IPSBAR[0x000014]))
-#define MCF_SCM_MPARK      (*(vuint32*)(void*)(&__IPSBAR[0x00001C]))
-#define MCF_SCM_MPR        (*(vuint8 *)(void*)(&__IPSBAR[0x000020]))
-#define MCF_SCM_PACR0      (*(vuint8 *)(void*)(&__IPSBAR[0x000024]))
-#define MCF_SCM_PACR1      (*(vuint8 *)(void*)(&__IPSBAR[0x000025]))
-#define MCF_SCM_PACR2      (*(vuint8 *)(void*)(&__IPSBAR[0x000026]))
-#define MCF_SCM_PACR3      (*(vuint8 *)(void*)(&__IPSBAR[0x000027]))
-#define MCF_SCM_PACR4      (*(vuint8 *)(void*)(&__IPSBAR[0x000028]))
-#define MCF_SCM_PACR5      (*(vuint8 *)(void*)(&__IPSBAR[0x00002A]))
-#define MCF_SCM_PACR6      (*(vuint8 *)(void*)(&__IPSBAR[0x00002B]))
-#define MCF_SCM_PACR7      (*(vuint8 *)(void*)(&__IPSBAR[0x00002C]))
-#define MCF_SCM_PACR8      (*(vuint8 *)(void*)(&__IPSBAR[0x00002E]))
-#define MCF_SCM_GPACR0     (*(vuint8 *)(void*)(&__IPSBAR[0x000030]))
-
-/* Bit definitions and macros for MCF_SCM_IPSBAR */
-#define MCF_SCM_IPSBAR_V                 (0x00000001)
-#define MCF_SCM_IPSBAR_BA(x)             (((x)&0x00000003)<<30)
-
-/* Bit definitions and macros for MCF_SCM_RAMBAR */
-#define MCF_SCM_RAMBAR_BDE               (0x00000200)
-#define MCF_SCM_RAMBAR_BA(x)             (((x)&0x0000FFFF)<<16)
-
-/* Bit definitions and macros for MCF_SCM_CRSR */
-#define MCF_SCM_CRSR_CWDR                (0x20)
-#define MCF_SCM_CRSR_EXT                 (0x80)
-
-/* Bit definitions and macros for MCF_SCM_CWCR */
-#define MCF_SCM_CWCR_CWTIC               (0x01)
-#define MCF_SCM_CWCR_CWTAVAL             (0x02)
-#define MCF_SCM_CWCR_CWTA                (0x04)
-#define MCF_SCM_CWCR_CWT(x)              (((x)&0x07)<<3)
-#define MCF_SCM_CWCR_CWRI                (0x40)
-#define MCF_SCM_CWCR_CWE                 (0x80)
-
-/* Bit definitions and macros for MCF_SCM_LPICR */
-#define MCF_SCM_LPICR_XLPM_IPL(x)        (((x)&0x07)<<4)
-#define MCF_SCM_LPICR_ENBSTOP            (0x80)
-
-/* Bit definitions and macros for MCF_SCM_DMAREQC */
-#define MCF_SCM_DMAREQC_DMAC0(x)         (((x)&0x0000000F)<<0)
-#define MCF_SCM_DMAREQC_DMAC1(x)         (((x)&0x0000000F)<<4)
-#define MCF_SCM_DMAREQC_DMAC2(x)         (((x)&0x0000000F)<<8)
-#define MCF_SCM_DMAREQC_DMAC3(x)         (((x)&0x0000000F)<<12)
-
-/* Bit definitions and macros for MCF_SCM_MPARK */
-#define MCF_SCM_MPARK_LCKOUT_TIME(x)     (((x)&0x0000000F)<<8)
-#define MCF_SCM_MPARK_PRKLAST            (0x00001000)
-#define MCF_SCM_MPARK_TIMEOUT            (0x00002000)
-#define MCF_SCM_MPARK_FIXED              (0x00004000)
-#define MCF_SCM_MPARK_M1_PRTY(x)         (((x)&0x00000003)<<16)
-#define MCF_SCM_MPARK_M0_PRTY(x)         (((x)&0x00000003)<<18)
-#define MCF_SCM_MPARK_M2_PRTY(x)         (((x)&0x00000003)<<20)
-#define MCF_SCM_MPARK_M3_PRTY(x)         (((x)&0x00000003)<<22)
-#define MCF_SCM_MPARK_BCR24BIT           (0x01000000)
-#define MCF_SCM_MPARK_M2_P_EN            (0x02000000)
-
-/* Bit definitions and macros for MCF_SCM_MPR */
-#define MCF_SCM_MPR_MPR(x)               (((x)&0x0F)<<0)
-
-/* Bit definitions and macros for MCF_SCM_PACR0 */
-#define MCF_SCM_PACR0_ACCESS_CTRL0(x)    (((x)&0x07)<<0)
-#define MCF_SCM_PACR0_LOCK0              (0x08)
-#define MCF_SCM_PACR0_ACCESS_CTRL1(x)    (((x)&0x07)<<4)
-#define MCF_SCM_PACR0_LOCK1              (0x80)
-
-/* Bit definitions and macros for MCF_SCM_PACR1 */
-#define MCF_SCM_PACR1_ACCESS_CTRL0(x)    (((x)&0x07)<<0)
-#define MCF_SCM_PACR1_LOCK0              (0x08)
-#define MCF_SCM_PACR1_ACCESS_CTRL1(x)    (((x)&0x07)<<4)
-#define MCF_SCM_PACR1_LOCK1              (0x80)
-
-/* Bit definitions and macros for MCF_SCM_PACR2 */
-#define MCF_SCM_PACR2_ACCESS_CTRL0(x)    (((x)&0x07)<<0)
-#define MCF_SCM_PACR2_LOCK0              (0x08)
-#define MCF_SCM_PACR2_ACCESS_CTRL1(x)    (((x)&0x07)<<4)
-#define MCF_SCM_PACR2_LOCK1              (0x80)
-
-/* Bit definitions and macros for MCF_SCM_PACR3 */
-#define MCF_SCM_PACR3_ACCESS_CTRL0(x)    (((x)&0x07)<<0)
-#define MCF_SCM_PACR3_LOCK0              (0x08)
-#define MCF_SCM_PACR3_ACCESS_CTRL1(x)    (((x)&0x07)<<4)
-#define MCF_SCM_PACR3_LOCK1              (0x80)
-
-/* Bit definitions and macros for MCF_SCM_PACR4 */
-#define MCF_SCM_PACR4_ACCESS_CTRL0(x)    (((x)&0x07)<<0)
-#define MCF_SCM_PACR4_LOCK0              (0x08)
-#define MCF_SCM_PACR4_ACCESS_CTRL1(x)    (((x)&0x07)<<4)
-#define MCF_SCM_PACR4_LOCK1              (0x80)
-
-/* Bit definitions and macros for MCF_SCM_PACR5 */
-#define MCF_SCM_PACR5_ACCESS_CTRL0(x)    (((x)&0x07)<<0)
-#define MCF_SCM_PACR5_LOCK0              (0x08)
-#define MCF_SCM_PACR5_ACCESS_CTRL1(x)    (((x)&0x07)<<4)
-#define MCF_SCM_PACR5_LOCK1              (0x80)
-
-/* Bit definitions and macros for MCF_SCM_PACR6 */
-#define MCF_SCM_PACR6_ACCESS_CTRL0(x)    (((x)&0x07)<<0)
-#define MCF_SCM_PACR6_LOCK0              (0x08)
-#define MCF_SCM_PACR6_ACCESS_CTRL1(x)    (((x)&0x07)<<4)
-#define MCF_SCM_PACR6_LOCK1              (0x80)
-
-/* Bit definitions and macros for MCF_SCM_PACR7 */
-#define MCF_SCM_PACR7_ACCESS_CTRL0(x)    (((x)&0x07)<<0)
-#define MCF_SCM_PACR7_LOCK0              (0x08)
-#define MCF_SCM_PACR7_ACCESS_CTRL1(x)    (((x)&0x07)<<4)
-#define MCF_SCM_PACR7_LOCK1              (0x80)
-
-/* Bit definitions and macros for MCF_SCM_PACR8 */
-#define MCF_SCM_PACR8_ACCESS_CTRL0(x)    (((x)&0x07)<<0)
-#define MCF_SCM_PACR8_LOCK0              (0x08)
-#define MCF_SCM_PACR8_ACCESS_CTRL1(x)    (((x)&0x07)<<4)
-#define MCF_SCM_PACR8_LOCK1              (0x80)
-
-/* Bit definitions and macros for MCF_SCM_GPACR0 */
-#define MCF_SCM_GPACR0_ACCESS_CTRL(x)    (((x)&0x0F)<<0)
-#define MCF_SCM_GPACR0_LOCK              (0x80)
-
-/********************************************************************/
-
-#endif /* __MCF523X_SCM_H__ */
diff --git a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_sdramc.h b/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_sdramc.h
deleted file mode 100644
index dbf38f8b6..000000000
--- a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_sdramc.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly 
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file 
- * LICENSE_FREESCALE.TXT.
- *
- * File:	mcf523x_sdramc.h
- * Purpose:	Register and bit definitions for the MCF523X
- *
- * Notes:	
- *	
- */
-
-#ifndef __MCF523X_SDRAMC_H__
-#define __MCF523X_SDRAMC_H__
-
-/*********************************************************************
-*
-* SDRAM Controller (SDRAMC)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_SDRAMC_DCR      (*(vuint16*)(void*)(&__IPSBAR[0x000040]))
-#define MCF_SDRAMC_DACR0    (*(vuint32*)(void*)(&__IPSBAR[0x000048]))
-#define MCF_SDRAMC_DMR0     (*(vuint32*)(void*)(&__IPSBAR[0x00004C]))
-#define MCF_SDRAMC_DACR1    (*(vuint32*)(void*)(&__IPSBAR[0x000050]))
-#define MCF_SDRAMC_DMR1     (*(vuint32*)(void*)(&__IPSBAR[0x000054]))
-
-/* Bit definitions and macros for MCF_SDRAMC_DCR */
-#define MCF_SDRAMC_DCR_RC(x)        (((x)&0x01FF)<<0)
-#define MCF_SDRAMC_DCR_RTIM(x)      (((x)&0x0003)<<9)
-#define MCF_SDRAMC_DCR_IS           (0x0800)
-#define MCF_SDRAMC_DCR_COC          (0x1000)
-#define MCF_SDRAMC_DCR_NAM          (0x2000)
-
-/* Bit definitions and macros for MCF_SDRAMC_DACR0 */
-#define MCF_SDRAMC_DACR0_IP         (0x00000008)
-#define MCF_SDRAMC_DACR0_PS(x)      (((x)&0x00000003)<<4)
-#define MCF_SDRAMC_DACR0_MRS        (0x00000040)
-#define MCF_SDRAMC_DACR0_CBM(x)     (((x)&0x00000007)<<8)
-#define MCF_SDRAMC_DACR0_CASL(x)    (((x)&0x00000003)<<12)
-#define MCF_SDRAMC_DACR0_RE         (0x00008000)
-#define MCF_SDRAMC_DACR0_BA(x)      (((x)&0x00003FFF)<<18)
-
-/* Bit definitions and macros for MCF_SDRAMC_DMR0 */
-#define MCF_SDRAMC_DMR0_V           (0x00000001)
-#define MCF_SDRAMC_DMR0_WP          (0x00000100)
-#define MCF_SDRAMC_DMR0_BAM(x)      (((x)&0x00003FFF)<<18)
-
-/* Bit definitions and macros for MCF_SDRAMC_DACR1 */
-#define MCF_SDRAMC_DACR1_IP         (0x00000008)
-#define MCF_SDRAMC_DACR1_PS(x)      (((x)&0x00000003)<<4)
-#define MCF_SDRAMC_DACR1_MRS        (0x00000040)
-#define MCF_SDRAMC_DACR1_CBM(x)     (((x)&0x00000007)<<8)
-#define MCF_SDRAMC_DACR1_CASL(x)    (((x)&0x00000003)<<12)
-#define MCF_SDRAMC_DACR1_RE         (0x00008000)
-#define MCF_SDRAMC_DACR1_BA(x)      (((x)&0x00003FFF)<<18)
-
-/* Bit definitions and macros for MCF_SDRAMC_DMR1 */
-#define MCF_SDRAMC_DMR1_V           (0x00000001)
-#define MCF_SDRAMC_DMR1_WP          (0x00000100)
-#define MCF_SDRAMC_DMR1_BAM(x)      (((x)&0x00003FFF)<<18)
-
-/********************************************************************/
-
-#define MCF_SDRAMC_DMR_BAM_4G			(0xFFFC0000)
-#define MCF_SDRAMC_DMR_BAM_2G			(0x7FFC0000)
-#define MCF_SDRAMC_DMR_BAM_1G			(0x3FFC0000)
-#define MCF_SDRAMC_DMR_BAM_1024M		(0x3FFC0000)
-#define MCF_SDRAMC_DMR_BAM_512M			(0x1FFC0000)
-#define MCF_SDRAMC_DMR_BAM_256M			(0x0FFC0000)
-#define MCF_SDRAMC_DMR_BAM_128M			(0x07FC0000)
-#define MCF_SDRAMC_DMR_BAM_64M			(0x03FC0000)
-#define MCF_SDRAMC_DMR_BAM_32M			(0x01FC0000)
-#define MCF_SDRAMC_DMR_BAM_16M			(0x00FC0000)
-#define MCF_SDRAMC_DMR_BAM_8M			(0x007C0000)
-#define MCF_SDRAMC_DMR_BAM_4M			(0x003C0000)
-#define MCF_SDRAMC_DMR_BAM_2M			(0x001C0000)
-#define MCF_SDRAMC_DMR_BAM_1M			(0x000C0000)
-#define MCF_SDRAMC_DMR_BAM_1024K		(0x000C0000)
-#define MCF_SDRAMC_DMR_BAM_512K			(0x00040000)
-#define MCF_SDRAMC_DMR_BAM_256K			(0x00000000)
-#define MCF_SDRAMC_DMR_WP				(0x00000100)
-#define MCF_SDRAMC_DMR_CI				(0x00000040)
-#define MCF_SDRAMC_DMR_AM				(0x00000020)
-#define MCF_SDRAMC_DMR_SC				(0x00000010)
-#define MCF_SDRAMC_DMR_SD				(0x00000008)
-#define MCF_SDRAMC_DMR_UC				(0x00000004)
-#define MCF_SDRAMC_DMR_UD				(0x00000002)
-#define MCF_SDRAMC_DMR_V				(0x00000001)
-
-#endif /* __MCF523X_SDRAMC_H__ */
diff --git a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_skha.h b/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_skha.h
deleted file mode 100644
index e03d2e05c..000000000
--- a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_skha.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly 
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file 
- * LICENSE_FREESCALE.TXT.
- *
- * File:	mcf523x_skha.h
- * Purpose:	Register and bit definitions for the MCF523X
- *
- * Notes:	
- *	
- */
-
-#ifndef __MCF523X_SKHA_H__
-#define __MCF523X_SKHA_H__
-
-/*********************************************************************
-*
-* Symmetric Key Hardware Accelerator (SKHA)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_SKHA_SKMR         (*(vuint32*)(void*)(&__IPSBAR[0x1B0000]))
-#define MCF_SKHA_SKCR         (*(vuint32*)(void*)(&__IPSBAR[0x1B0004]))
-#define MCF_SKHA_SKCMR        (*(vuint32*)(void*)(&__IPSBAR[0x1B0008]))
-#define MCF_SKHA_SKSR         (*(vuint32*)(void*)(&__IPSBAR[0x1B000C]))
-#define MCF_SKHA_SKIR         (*(vuint32*)(void*)(&__IPSBAR[0x1B0010]))
-#define MCF_SKHA_SKIMR        (*(vuint32*)(void*)(&__IPSBAR[0x1B0014]))
-#define MCF_SKHA_SKKSR        (*(vuint32*)(void*)(&__IPSBAR[0x1B0018]))
-#define MCF_SKHA_SKDSR        (*(vuint32*)(void*)(&__IPSBAR[0x1B001C]))
-#define MCF_SKHA_SKIN         (*(vuint32*)(void*)(&__IPSBAR[0x1B0020]))
-#define MCF_SKHA_SKOUT        (*(vuint32*)(void*)(&__IPSBAR[0x1B0024]))
-#define MCF_SKHA_SKKDR0       (*(vuint32*)(void*)(&__IPSBAR[0x1B0030]))
-#define MCF_SKHA_SKKDR1       (*(vuint32*)(void*)(&__IPSBAR[0x1B0034]))
-#define MCF_SKHA_SKKDR2       (*(vuint32*)(void*)(&__IPSBAR[0x1B0038]))
-#define MCF_SKHA_SKKDR3       (*(vuint32*)(void*)(&__IPSBAR[0x1B003C]))
-#define MCF_SKHA_SKKDR4       (*(vuint32*)(void*)(&__IPSBAR[0x1B0040]))
-#define MCF_SKHA_SKKDR5       (*(vuint32*)(void*)(&__IPSBAR[0x1B0044]))
-#define MCF_SKHA_SKKDRn(x)    (*(vuint32*)(void*)(&__IPSBAR[0x1B0030+((x)*0x004)]))
-#define MCF_SKHA_SKCR0        (*(vuint32*)(void*)(&__IPSBAR[0x1B0070]))
-#define MCF_SKHA_SKCR1        (*(vuint32*)(void*)(&__IPSBAR[0x1B0074]))
-#define MCF_SKHA_SKCR2        (*(vuint32*)(void*)(&__IPSBAR[0x1B0078]))
-#define MCF_SKHA_SKCR3        (*(vuint32*)(void*)(&__IPSBAR[0x1B007C]))
-#define MCF_SKHA_SKCR4        (*(vuint32*)(void*)(&__IPSBAR[0x1B0080]))
-#define MCF_SKHA_SKCR5        (*(vuint32*)(void*)(&__IPSBAR[0x1B0084]))
-#define MCF_SKHA_SKCR6        (*(vuint32*)(void*)(&__IPSBAR[0x1B0088]))
-#define MCF_SKHA_SKCR7        (*(vuint32*)(void*)(&__IPSBAR[0x1B008C]))
-#define MCF_SKHA_SKCR8        (*(vuint32*)(void*)(&__IPSBAR[0x1B0090]))
-#define MCF_SKHA_SKCR9        (*(vuint32*)(void*)(&__IPSBAR[0x1B0094]))
-#define MCF_SKHA_SKCR10       (*(vuint32*)(void*)(&__IPSBAR[0x1B0098]))
-#define MCF_SKHA_SKCR11       (*(vuint32*)(void*)(&__IPSBAR[0x1B009C]))
-#define MCF_SKHA_SKCRn(x)     (*(vuint32*)(void*)(&__IPSBAR[0x1B0070+((x)*0x004)]))
-
-/* Bit definitions and macros for MCF_SKHA_SKMR */
-#define MCF_SKHA_SKMR_ALG(x)         (((x)&0x00000003)<<0)
-#define MCF_SKHA_SKMR_DIR            (0x00000004)
-#define MCF_SKHA_SKMR_CM(x)          (((x)&0x00000003)<<3)
-#define MCF_SKHA_SKMR_DKP            (0x00000100)
-#define MCF_SKHA_SKMR_CTRM(x)        (((x)&0x0000000F)<<9)
-#define MCF_SKHA_SKMR_CM_ECB         (0x00000000)
-#define MCF_SKHA_SKMR_CM_CBC         (0x00000008)
-#define MCF_SKHA_SKMR_CM_CTR         (0x00000018)
-#define MCF_SKHA_SKMR_DIR_DEC        (0x00000000)
-#define MCF_SKHA_SKMR_DIR_ENC        (0x00000004)
-#define MCF_SKHA_SKMR_ALG_AES        (0x00000000)
-#define MCF_SKHA_SKMR_ALG_DES        (0x00000001)
-#define MCF_SKHA_SKMR_ALG_TDES       (0x00000002)
-
-/* Bit definitions and macros for MCF_SKHA_SKCR */
-#define MCF_SKHA_SKCR_IE             (0x00000001)
-
-/* Bit definitions and macros for MCF_SKHA_SKCMR */
-#define MCF_SKHA_SKCMR_SWR           (0x00000001)
-#define MCF_SKHA_SKCMR_RI            (0x00000002)
-#define MCF_SKHA_SKCMR_CI            (0x00000004)
-#define MCF_SKHA_SKCMR_GO            (0x00000008)
-
-/* Bit definitions and macros for MCF_SKHA_SKSR */
-#define MCF_SKHA_SKSR_INT            (0x00000001)
-#define MCF_SKHA_SKSR_DONE           (0x00000002)
-#define MCF_SKHA_SKSR_ERR            (0x00000004)
-#define MCF_SKHA_SKSR_RD             (0x00000008)
-#define MCF_SKHA_SKSR_BUSY           (0x00000010)
-#define MCF_SKHA_SKSR_IFL(x)         (((x)&0x000000FF)<<16)
-#define MCF_SKHA_SKSR_OFL(x)         (((x)&0x000000FF)<<24)
-
-/* Bit definitions and macros for MCF_SKHA_SKIR */
-#define MCF_SKHA_SKIR_IFO            (0x00000001)
-#define MCF_SKHA_SKIR_OFU            (0x00000002)
-#define MCF_SKHA_SKIR_NEIF           (0x00000004)
-#define MCF_SKHA_SKIR_NEOF           (0x00000008)
-#define MCF_SKHA_SKIR_IME            (0x00000010)
-#define MCF_SKHA_SKIR_DSE            (0x00000020)
-#define MCF_SKHA_SKIR_KSE            (0x00000040)
-#define MCF_SKHA_SKIR_RMDP           (0x00000080)
-#define MCF_SKHA_SKIR_ERE            (0x00000100)
-#define MCF_SKHA_SKIR_KPE            (0x00000200)
-#define MCF_SKHA_SKIR_KRE            (0x00000400)
-
-/* Bit definitions and macros for MCF_SKHA_SKIMR */
-#define MCF_SKHA_SKIMR_IFO           (0x00000001)
-#define MCF_SKHA_SKIMR_OFU           (0x00000002)
-#define MCF_SKHA_SKIMR_NEIF          (0x00000004)
-#define MCF_SKHA_SKIMR_NEOF          (0x00000008)
-#define MCF_SKHA_SKIMR_IME           (0x00000010)
-#define MCF_SKHA_SKIMR_DSE           (0x00000020)
-#define MCF_SKHA_SKIMR_KSE           (0x00000040)
-#define MCF_SKHA_SKIMR_RMDP          (0x00000080)
-#define MCF_SKHA_SKIMR_ERE           (0x00000100)
-#define MCF_SKHA_SKIMR_KPE           (0x00000200)
-#define MCF_SKHA_SKIMR_KRE           (0x00000400)
-
-/* Bit definitions and macros for MCF_SKHA_SKKSR */
-#define MCF_SKHA_SKKSR_KEYSIZE(x)    (((x)&0x0000003F)<<0)
-
-/********************************************************************/
-
-#endif /* __MCF523X_SKHA_H__ */
diff --git a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_sram.h b/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_sram.h
deleted file mode 100644
index b40dda0e6..000000000
--- a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_sram.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly 
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file 
- * LICENSE_FREESCALE.TXT.
- *
- * File:	mcf523x_sram.h
- * Purpose:	Register and bit definitions for the MCF523X
- *
- * Notes:	
- *	
- */
-
-#ifndef __MCF523X_SRAM_H__
-#define __MCF523X_SRAM_H__
-
-/*********************************************************************
-*
-* 64KByte System SRAM (SRAM)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_SRAM_RAMBAR    (*(vuint32*)(void*)(&__IPSBAR[0x20000000]))
-
-/* Bit definitions and macros for MCF_SRAM_RAMBAR */
-#define MCF_SRAM_RAMBAR_V        (0x00000001)
-#define MCF_SRAM_RAMBAR_UD       (0x00000002)
-#define MCF_SRAM_RAMBAR_UC       (0x00000004)
-#define MCF_SRAM_RAMBAR_SD       (0x00000008)
-#define MCF_SRAM_RAMBAR_SC       (0x00000010)
-#define MCF_SRAM_RAMBAR_CI       (0x00000020)
-#define MCF_SRAM_RAMBAR_WP       (0x00000100)
-#define MCF_SRAM_RAMBAR_SPV      (0x00000200)
-#define MCF_SRAM_RAMBAR_PRI2     (0x00000400)
-#define MCF_SRAM_RAMBAR_PRI1     (0x00000800)
-#define MCF_SRAM_RAMBAR_BA(x)    (((x)&0x0000FFFF)<<16)
-
-/********************************************************************/
-
-#endif /* __MCF523X_SRAM_H__ */
diff --git a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_timer.h b/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_timer.h
deleted file mode 100644
index e9db74c27..000000000
--- a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_timer.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly 
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file 
- * LICENSE_FREESCALE.TXT.
- *
- * File:	mcf523x_timer.h
- * Purpose:	Register and bit definitions for the MCF523X
- *
- * Notes:	
- *	
- */
-
-#ifndef __MCF523X_TIMER_H__
-#define __MCF523X_TIMER_H__
-
-/*********************************************************************
-*
-* DMA Timers (TIMER)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_TIMER_DTMR0       (*(vuint16*)(void*)(&__IPSBAR[0x000400]))
-#define MCF_TIMER_DTXMR0      (*(vuint8 *)(void*)(&__IPSBAR[0x000402]))
-#define MCF_TIMER_DTER0       (*(vuint8 *)(void*)(&__IPSBAR[0x000403]))
-#define MCF_TIMER_DTRR0       (*(vuint32*)(void*)(&__IPSBAR[0x000404]))
-#define MCF_TIMER_DTCR0       (*(vuint32*)(void*)(&__IPSBAR[0x000408]))
-#define MCF_TIMER_DTCN0       (*(vuint32*)(void*)(&__IPSBAR[0x00040C]))
-#define MCF_TIMER_DTMR1       (*(vuint16*)(void*)(&__IPSBAR[0x000440]))
-#define MCF_TIMER_DTXMR1      (*(vuint8 *)(void*)(&__IPSBAR[0x000442]))
-#define MCF_TIMER_DTER1       (*(vuint8 *)(void*)(&__IPSBAR[0x000443]))
-#define MCF_TIMER_DTRR1       (*(vuint32*)(void*)(&__IPSBAR[0x000444]))
-#define MCF_TIMER_DTCR1       (*(vuint32*)(void*)(&__IPSBAR[0x000448]))
-#define MCF_TIMER_DTCN1       (*(vuint32*)(void*)(&__IPSBAR[0x00044C]))
-#define MCF_TIMER_DTMR2       (*(vuint16*)(void*)(&__IPSBAR[0x000480]))
-#define MCF_TIMER_DTXMR2      (*(vuint8 *)(void*)(&__IPSBAR[0x000482]))
-#define MCF_TIMER_DTER2       (*(vuint8 *)(void*)(&__IPSBAR[0x000483]))
-#define MCF_TIMER_DTRR2       (*(vuint32*)(void*)(&__IPSBAR[0x000484]))
-#define MCF_TIMER_DTCR2       (*(vuint32*)(void*)(&__IPSBAR[0x000488]))
-#define MCF_TIMER_DTCN2       (*(vuint32*)(void*)(&__IPSBAR[0x00048C]))
-#define MCF_TIMER_DTMR3       (*(vuint16*)(void*)(&__IPSBAR[0x0004C0]))
-#define MCF_TIMER_DTXMR3      (*(vuint8 *)(void*)(&__IPSBAR[0x0004C2]))
-#define MCF_TIMER_DTER3       (*(vuint8 *)(void*)(&__IPSBAR[0x0004C3]))
-#define MCF_TIMER_DTRR3       (*(vuint32*)(void*)(&__IPSBAR[0x0004C4]))
-#define MCF_TIMER_DTCR3       (*(vuint32*)(void*)(&__IPSBAR[0x0004C8]))
-#define MCF_TIMER_DTCN3       (*(vuint32*)(void*)(&__IPSBAR[0x0004CC]))
-#define MCF_TIMER_DTMR(x)     (*(vuint16*)(void*)(&__IPSBAR[0x000400+((x)*0x040)]))
-#define MCF_TIMER_DTXMR(x)    (*(vuint8 *)(void*)(&__IPSBAR[0x000402+((x)*0x040)]))
-#define MCF_TIMER_DTER(x)     (*(vuint8 *)(void*)(&__IPSBAR[0x000403+((x)*0x040)]))
-#define MCF_TIMER_DTRR(x)     (*(vuint32*)(void*)(&__IPSBAR[0x000404+((x)*0x040)]))
-#define MCF_TIMER_DTCR(x)     (*(vuint32*)(void*)(&__IPSBAR[0x000408+((x)*0x040)]))
-#define MCF_TIMER_DTCN(x)     (*(vuint32*)(void*)(&__IPSBAR[0x00040C+((x)*0x040)]))
-
-/* Bit definitions and macros for MCF_TIMER_DTMR */
-#define MCF_TIMER_DTMR_RST          (0x0001)
-#define MCF_TIMER_DTMR_CLK(x)       (((x)&0x0003)<<1)
-#define MCF_TIMER_DTMR_FRR          (0x0008)
-#define MCF_TIMER_DTMR_ORRI         (0x0010)
-#define MCF_TIMER_DTMR_OM           (0x0020)
-#define MCF_TIMER_DTMR_CE(x)        (((x)&0x0003)<<6)
-#define MCF_TIMER_DTMR_PS(x)        (((x)&0x00FF)<<8)
-#define MCF_TIMER_DTMR_CE_ANY       (0x00C0)
-#define MCF_TIMER_DTMR_CE_FALL      (0x0080)
-#define MCF_TIMER_DTMR_CE_RISE      (0x0040)
-#define MCF_TIMER_DTMR_CE_NONE      (0x0000)
-#define MCF_TIMER_DTMR_CLK_DTIN     (0x0006)
-#define MCF_TIMER_DTMR_CLK_DIV16    (0x0004)
-#define MCF_TIMER_DTMR_CLK_DIV1     (0x0002)
-#define MCF_TIMER_DTMR_CLK_STOP     (0x0000)
-
-/* Bit definitions and macros for MCF_TIMER_DTXMR */
-#define MCF_TIMER_DTXMR_MODE16      (0x01)
-#define MCF_TIMER_DTXMR_DMAEN       (0x80)
-
-/* Bit definitions and macros for MCF_TIMER_DTER */
-#define MCF_TIMER_DTER_CAP          (0x01)
-#define MCF_TIMER_DTER_REF          (0x02)
-
-/********************************************************************/
-
-#endif /* __MCF523X_TIMER_H__ */
diff --git a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_uart.h b/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_uart.h
deleted file mode 100644
index 43a44a67f..000000000
--- a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_uart.h
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly 
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file 
- * LICENSE_FREESCALE.TXT.
- *
- * File:	mcf523x_uart.h
- * Purpose:	Register and bit definitions for the MCF523X
- *
- * Notes:	
- *	
- */
-
-#ifndef __MCF523X_UART_H__
-#define __MCF523X_UART_H__
-
-/*********************************************************************
-*
-* Universal Asynchronous Receiver Transmitter (UART)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_UART_UMR0        (*(vuint8 *)(void*)(&__IPSBAR[0x000200]))
-#define MCF_UART_USR0        (*(vuint8 *)(void*)(&__IPSBAR[0x000204]))
-#define MCF_UART_UCSR0       (*(vuint8 *)(void*)(&__IPSBAR[0x000204]))
-#define MCF_UART_UCR0        (*(vuint8 *)(void*)(&__IPSBAR[0x000208]))
-#define MCF_UART_URB0        (*(vuint8 *)(void*)(&__IPSBAR[0x00020C]))
-#define MCF_UART_UTB0        (*(vuint8 *)(void*)(&__IPSBAR[0x00020C]))
-#define MCF_UART_UIPCR0      (*(vuint8 *)(void*)(&__IPSBAR[0x000210]))
-#define MCF_UART_UACR0       (*(vuint8 *)(void*)(&__IPSBAR[0x000210]))
-#define MCF_UART_UISR0       (*(vuint8 *)(void*)(&__IPSBAR[0x000214]))
-#define MCF_UART_UIMR0       (*(vuint8 *)(void*)(&__IPSBAR[0x000214]))
-#define MCF_UART_UBG10       (*(vuint8 *)(void*)(&__IPSBAR[0x000218]))
-#define MCF_UART_UBG20       (*(vuint8 *)(void*)(&__IPSBAR[0x00021C]))
-#define MCF_UART_UIP0        (*(vuint8 *)(void*)(&__IPSBAR[0x000234]))
-#define MCF_UART_UOP10       (*(vuint8 *)(void*)(&__IPSBAR[0x000238]))
-#define MCF_UART_UOP00       (*(vuint8 *)(void*)(&__IPSBAR[0x00023C]))
-#define MCF_UART_UMR1        (*(vuint8 *)(void*)(&__IPSBAR[0x000240]))
-#define MCF_UART_USR1        (*(vuint8 *)(void*)(&__IPSBAR[0x000244]))
-#define MCF_UART_UCSR1       (*(vuint8 *)(void*)(&__IPSBAR[0x000244]))
-#define MCF_UART_UCR1        (*(vuint8 *)(void*)(&__IPSBAR[0x000248]))
-#define MCF_UART_URB1        (*(vuint8 *)(void*)(&__IPSBAR[0x00024C]))
-#define MCF_UART_UTB1        (*(vuint8 *)(void*)(&__IPSBAR[0x00024C]))
-#define MCF_UART_UIPCR1      (*(vuint8 *)(void*)(&__IPSBAR[0x000250]))
-#define MCF_UART_UACR1       (*(vuint8 *)(void*)(&__IPSBAR[0x000250]))
-#define MCF_UART_UISR1       (*(vuint8 *)(void*)(&__IPSBAR[0x000254]))
-#define MCF_UART_UIMR1       (*(vuint8 *)(void*)(&__IPSBAR[0x000254]))
-#define MCF_UART_UBG11       (*(vuint8 *)(void*)(&__IPSBAR[0x000258]))
-#define MCF_UART_UBG21       (*(vuint8 *)(void*)(&__IPSBAR[0x00025C]))
-#define MCF_UART_UIP1        (*(vuint8 *)(void*)(&__IPSBAR[0x000274]))
-#define MCF_UART_UOP11       (*(vuint8 *)(void*)(&__IPSBAR[0x000278]))
-#define MCF_UART_UOP01       (*(vuint8 *)(void*)(&__IPSBAR[0x00027C]))
-#define MCF_UART_UMR2        (*(vuint8 *)(void*)(&__IPSBAR[0x000280]))
-#define MCF_UART_USR2        (*(vuint8 *)(void*)(&__IPSBAR[0x000284]))
-#define MCF_UART_UCSR2       (*(vuint8 *)(void*)(&__IPSBAR[0x000284]))
-#define MCF_UART_UCR2        (*(vuint8 *)(void*)(&__IPSBAR[0x000288]))
-#define MCF_UART_URB2        (*(vuint8 *)(void*)(&__IPSBAR[0x00028C]))
-#define MCF_UART_UTB2        (*(vuint8 *)(void*)(&__IPSBAR[0x00028C]))
-#define MCF_UART_UIPCR2      (*(vuint8 *)(void*)(&__IPSBAR[0x000290]))
-#define MCF_UART_UACR2       (*(vuint8 *)(void*)(&__IPSBAR[0x000290]))
-#define MCF_UART_UISR2       (*(vuint8 *)(void*)(&__IPSBAR[0x000294]))
-#define MCF_UART_UIMR2       (*(vuint8 *)(void*)(&__IPSBAR[0x000294]))
-#define MCF_UART_UBG12       (*(vuint8 *)(void*)(&__IPSBAR[0x000298]))
-#define MCF_UART_UBG22       (*(vuint8 *)(void*)(&__IPSBAR[0x00029C]))
-#define MCF_UART_UIP2        (*(vuint8 *)(void*)(&__IPSBAR[0x0002B4]))
-#define MCF_UART_UOP12       (*(vuint8 *)(void*)(&__IPSBAR[0x0002B8]))
-#define MCF_UART_UOP02       (*(vuint8 *)(void*)(&__IPSBAR[0x0002BC]))
-#define MCF_UART_UMR(x)      (*(vuint8 *)(void*)(&__IPSBAR[0x000200+((x)*0x040)]))
-#define MCF_UART_USR(x)      (*(vuint8 *)(void*)(&__IPSBAR[0x000204+((x)*0x040)]))
-#define MCF_UART_UCSR(x)     (*(vuint8 *)(void*)(&__IPSBAR[0x000204+((x)*0x040)]))
-#define MCF_UART_UCR(x)      (*(vuint8 *)(void*)(&__IPSBAR[0x000208+((x)*0x040)]))
-#define MCF_UART_URB(x)      (*(vuint8 *)(void*)(&__IPSBAR[0x00020C+((x)*0x040)]))
-#define MCF_UART_UTB(x)      (*(vuint8 *)(void*)(&__IPSBAR[0x00020C+((x)*0x040)]))
-#define MCF_UART_UIPCR(x)    (*(vuint8 *)(void*)(&__IPSBAR[0x000210+((x)*0x040)]))
-#define MCF_UART_UACR(x)     (*(vuint8 *)(void*)(&__IPSBAR[0x000210+((x)*0x040)]))
-#define MCF_UART_UISR(x)     (*(vuint8 *)(void*)(&__IPSBAR[0x000214+((x)*0x040)]))
-#define MCF_UART_UIMR(x)     (*(vuint8 *)(void*)(&__IPSBAR[0x000214+((x)*0x040)]))
-#define MCF_UART_UBG1(x)     (*(vuint8 *)(void*)(&__IPSBAR[0x000218+((x)*0x040)]))
-#define MCF_UART_UBG2(x)     (*(vuint8 *)(void*)(&__IPSBAR[0x00021C+((x)*0x040)]))
-#define MCF_UART_UIP(x)      (*(vuint8 *)(void*)(&__IPSBAR[0x000234+((x)*0x040)]))
-#define MCF_UART_UOP1(x)     (*(vuint8 *)(void*)(&__IPSBAR[0x000238+((x)*0x040)]))
-#define MCF_UART_UOP0(x)     (*(vuint8 *)(void*)(&__IPSBAR[0x00023C+((x)*0x040)]))
-
-/* Bit definitions and macros for MCF_UART_UMR */
-#define MCF_UART_UMR_BC(x)              (((x)&0x03)<<0)
-#define MCF_UART_UMR_PT                 (0x04)
-#define MCF_UART_UMR_PM(x)              (((x)&0x03)<<3)
-#define MCF_UART_UMR_ERR                (0x20)
-#define MCF_UART_UMR_RXIRQ              (0x40)
-#define MCF_UART_UMR_RXRTS              (0x80)
-#define MCF_UART_UMR_SB(x)              (((x)&0x0F)<<0)
-#define MCF_UART_UMR_TXCTS              (0x10)
-#define MCF_UART_UMR_TXRTS              (0x20)
-#define MCF_UART_UMR_CM(x)              (((x)&0x03)<<6)
-#define MCF_UART_UMR_PM_MULTI_ADDR      (0x1C)
-#define MCF_UART_UMR_PM_MULTI_DATA      (0x18)
-#define MCF_UART_UMR_PM_NONE            (0x10)
-#define MCF_UART_UMR_PM_FORCE_HI        (0x0C)
-#define MCF_UART_UMR_PM_FORCE_LO        (0x08)
-#define MCF_UART_UMR_PM_ODD             (0x04)
-#define MCF_UART_UMR_PM_EVEN            (0x00)
-#define MCF_UART_UMR_BC_5               (0x00)
-#define MCF_UART_UMR_BC_6               (0x01)
-#define MCF_UART_UMR_BC_7               (0x02)
-#define MCF_UART_UMR_BC_8               (0x03)
-#define MCF_UART_UMR_CM_NORMAL          (0x00)
-#define MCF_UART_UMR_CM_ECHO            (0x40)
-#define MCF_UART_UMR_CM_LOCAL_LOOP      (0x80)
-#define MCF_UART_UMR_CM_REMOTE_LOOP     (0xC0)
-#define MCF_UART_UMR_SB_STOP_BITS_1     (0x07)
-#define MCF_UART_UMR_SB_STOP_BITS_15    (0x08)
-#define MCF_UART_UMR_SB_STOP_BITS_2     (0x0F)
-
-/* Bit definitions and macros for MCF_UART_USR */
-#define MCF_UART_USR_RXRDY              (0x01)
-#define MCF_UART_USR_FFULL              (0x02)
-#define MCF_UART_USR_TXRDY              (0x04)
-#define MCF_UART_USR_TXEMP              (0x08)
-#define MCF_UART_USR_OE                 (0x10)
-#define MCF_UART_USR_PE                 (0x20)
-#define MCF_UART_USR_FE                 (0x40)
-#define MCF_UART_USR_RB                 (0x80)
-
-/* Bit definitions and macros for MCF_UART_UCSR */
-#define MCF_UART_UCSR_TCS(x)            (((x)&0x0F)<<0)
-#define MCF_UART_UCSR_RCS(x)            (((x)&0x0F)<<4)
-#define MCF_UART_UCSR_RCS_SYS_CLK       (0xD0)
-#define MCF_UART_UCSR_RCS_CTM16         (0xE0)
-#define MCF_UART_UCSR_RCS_CTM           (0xF0)
-#define MCF_UART_UCSR_TCS_SYS_CLK       (0x0D)
-#define MCF_UART_UCSR_TCS_CTM16         (0x0E)
-#define MCF_UART_UCSR_TCS_CTM           (0x0F)
-
-/* Bit definitions and macros for MCF_UART_UCR */
-#define MCF_UART_UCR_RXC(x)             (((x)&0x03)<<0)
-#define MCF_UART_UCR_TXC(x)             (((x)&0x03)<<2)
-#define MCF_UART_UCR_MISC(x)            (((x)&0x07)<<4)
-#define MCF_UART_UCR_NONE               (0x00)
-#define MCF_UART_UCR_STOP_BREAK         (0x70)
-#define MCF_UART_UCR_START_BREAK        (0x60)
-#define MCF_UART_UCR_BKCHGINT           (0x50)
-#define MCF_UART_UCR_RESET_ERROR        (0x40)
-#define MCF_UART_UCR_RESET_TX           (0x30)
-#define MCF_UART_UCR_RESET_RX           (0x20)
-#define MCF_UART_UCR_RESET_MR           (0x10)
-#define MCF_UART_UCR_TX_DISABLED        (0x08)
-#define MCF_UART_UCR_TX_ENABLED         (0x04)
-#define MCF_UART_UCR_RX_DISABLED        (0x02)
-#define MCF_UART_UCR_RX_ENABLED         (0x01)
-
-/* Bit definitions and macros for MCF_UART_UIPCR */
-#define MCF_UART_UIPCR_CTS              (0x01)
-#define MCF_UART_UIPCR_COS              (0x10)
-
-/* Bit definitions and macros for MCF_UART_UACR */
-#define MCF_UART_UACR_IEC               (0x01)
-
-/* Bit definitions and macros for MCF_UART_UISR */
-#define MCF_UART_UISR_TXRDY             (0x01)
-#define MCF_UART_UISR_RXRDY_FU          (0x02)
-#define MCF_UART_UISR_DB                (0x04)
-#define MCF_UART_UISR_RXFTO             (0x08)
-#define MCF_UART_UISR_TXFIFO            (0x10)
-#define MCF_UART_UISR_RXFIFO            (0x20)
-#define MCF_UART_UISR_COS               (0x80)
-
-/* Bit definitions and macros for MCF_UART_UIMR */
-#define MCF_UART_UIMR_TXRDY             (0x01)
-#define MCF_UART_UIMR_RXRDY_FU          (0x02)
-#define MCF_UART_UIMR_DB                (0x04)
-#define MCF_UART_UIMR_COS               (0x80)
-
-/* Bit definitions and macros for MCF_UART_UIP */
-#define MCF_UART_UIP_CTS                (0x01)
-
-/* Bit definitions and macros for MCF_UART_UOP1 */
-#define MCF_UART_UOP1_RTS               (0x01)
-
-/* Bit definitions and macros for MCF_UART_UOP0 */
-#define MCF_UART_UOP0_RTS               (0x01)
-
-/********************************************************************/
-
-#endif /* __MCF523X_UART_H__ */
diff --git a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_wtm.h b/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_wtm.h
deleted file mode 100644
index 489486791..000000000
--- a/Demo/lwIP_MCF5235_GCC/include/arch/mcf523x/mcf523x_wtm.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly 
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file 
- * LICENSE_FREESCALE.TXT.
- *
- * File:	mcf523x_wtm.h
- * Purpose:	Register and bit definitions for the MCF523X
- *
- * Notes:	
- *	
- */
-
-#ifndef __MCF523X_WTM_H__
-#define __MCF523X_WTM_H__
-
-/*********************************************************************
-*
-* Watchdog Timer Modules (WTM)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_WTM_WCR      (*(vuint16*)(void*)(&__IPSBAR[0x140000]))
-#define MCF_WTM_WMR      (*(vuint16*)(void*)(&__IPSBAR[0x140002]))
-#define MCF_WTM_WCNTR    (*(vuint16*)(void*)(&__IPSBAR[0x140004]))
-#define MCF_WTM_WSR      (*(vuint16*)(void*)(&__IPSBAR[0x140006]))
-
-/* Bit definitions and macros for MCF_WTM_WCR */
-#define MCF_WTM_WCR_EN        (0x0001)
-#define MCF_WTM_WCR_HALTED    (0x0002)
-#define MCF_WTM_WCR_DOZE      (0x0004)
-#define MCF_WTM_WCR_WAIT      (0x0008)
-
-/* Bit definitions and macros for MCF_WTM_WMR */
-#define MCF_WTM_WMR_WM0       (0x0001)
-#define MCF_WTM_WMR_WM1       (0x0002)
-#define MCF_WTM_WMR_WM2       (0x0004)
-#define MCF_WTM_WMR_WM3       (0x0008)
-#define MCF_WTM_WMR_WM4       (0x0010)
-#define MCF_WTM_WMR_WM5       (0x0020)
-#define MCF_WTM_WMR_WM6       (0x0040)
-#define MCF_WTM_WMR_WM7       (0x0080)
-#define MCF_WTM_WMR_WM8       (0x0100)
-#define MCF_WTM_WMR_WM9       (0x0200)
-#define MCF_WTM_WMR_WM10      (0x0400)
-#define MCF_WTM_WMR_WM11      (0x0800)
-#define MCF_WTM_WMR_WM12      (0x1000)
-#define MCF_WTM_WMR_WM13      (0x2000)
-#define MCF_WTM_WMR_WM14      (0x4000)
-#define MCF_WTM_WMR_WM15      (0x8000)
-
-/* Bit definitions and macros for MCF_WTM_WCNTR */
-#define MCF_WTM_WCNTR_WC0     (0x0001)
-#define MCF_WTM_WCNTR_WC1     (0x0002)
-#define MCF_WTM_WCNTR_WC2     (0x0004)
-#define MCF_WTM_WCNTR_WC3     (0x0008)
-#define MCF_WTM_WCNTR_WC4     (0x0010)
-#define MCF_WTM_WCNTR_WC5     (0x0020)
-#define MCF_WTM_WCNTR_WC6     (0x0040)
-#define MCF_WTM_WCNTR_WC7     (0x0080)
-#define MCF_WTM_WCNTR_WC8     (0x0100)
-#define MCF_WTM_WCNTR_WC9     (0x0200)
-#define MCF_WTM_WCNTR_WC10    (0x0400)
-#define MCF_WTM_WCNTR_WC11    (0x0800)
-#define MCF_WTM_WCNTR_WC12    (0x1000)
-#define MCF_WTM_WCNTR_WC13    (0x2000)
-#define MCF_WTM_WCNTR_WC14    (0x4000)
-#define MCF_WTM_WCNTR_WC15    (0x8000)
-
-/* Bit definitions and macros for MCF_WTM_WSR */
-#define MCF_WTM_WSR_WS0       (0x0001)
-#define MCF_WTM_WSR_WS1       (0x0002)
-#define MCF_WTM_WSR_WS2       (0x0004)
-#define MCF_WTM_WSR_WS3       (0x0008)
-#define MCF_WTM_WSR_WS4       (0x0010)
-#define MCF_WTM_WSR_WS5       (0x0020)
-#define MCF_WTM_WSR_WS6       (0x0040)
-#define MCF_WTM_WSR_WS7       (0x0080)
-#define MCF_WTM_WSR_WS8       (0x0100)
-#define MCF_WTM_WSR_WS9       (0x0200)
-#define MCF_WTM_WSR_WS10      (0x0400)
-#define MCF_WTM_WSR_WS11      (0x0800)
-#define MCF_WTM_WSR_WS12      (0x1000)
-#define MCF_WTM_WSR_WS13      (0x2000)
-#define MCF_WTM_WSR_WS14      (0x4000)
-#define MCF_WTM_WSR_WS15      (0x8000)
-
-/********************************************************************/
-
-#endif /* __MCF523X_WTM_H__ */
diff --git a/Demo/lwIP_MCF5235_GCC/include/arch/mcf5xxx.h b/Demo/lwIP_MCF5235_GCC/include/arch/mcf5xxx.h
deleted file mode 100644
index 692d690e1..000000000
--- a/Demo/lwIP_MCF5235_GCC/include/arch/mcf5xxx.h
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly 
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file 
- * LICENSE_FREESCALE.TXT.
- *
- * File:		mcf5xxx.h
- * Purpose:		Definitions common to all ColdFire processors
- *
- * Notes:
- */
-
-#ifndef _CPU_MCF5XXX_H
-#define _CPU_MCF5XXX_H
-
-/***********************************************************************/
-/*
- * Misc. Defines
- */
-
-#ifdef	FALSE
-#undef	FALSE
-#endif
-#define FALSE	(0)
-
-#ifdef	TRUE
-#undef	TRUE
-#endif
-#define	TRUE	(1)
-
-#ifdef	NULL
-#undef	NULL
-#endif
-#define NULL	(0)
-
-/***********************************************************************/
-/*
- * The basic data types
- */
-
-typedef unsigned char		uint8;  /*  8 bits */
-typedef unsigned short int	uint16; /* 16 bits */
-typedef unsigned long int	uint32; /* 32 bits */
-
-typedef signed char			int8;   /*  8 bits */
-typedef signed short int	int16;  /* 16 bits */
-typedef signed long int		int32;  /* 32 bits */
-
-typedef volatile uint8		vuint8;  /*  8 bits */
-typedef volatile uint16		vuint16; /* 16 bits */
-typedef volatile uint32		vuint32; /* 32 bits */
-
-/***********************************************************************/
-/*
- * Common M68K & ColdFire definitions
- */
-
-#define ADDRESS			uint32
-#define INSTRUCTION		uint16
-#define ILLEGAL			0x4AFC
-#define CPU_WORD_SIZE	16
-
-#define MCF5XXX_SR_T		(0x8000)
-#define MCF5XXX_SR_S		(0x2000)
-#define MCF5XXX_SR_M		(0x1000)
-#define MCF5XXX_SR_IPL		(0x0700)
-#define MCF5XXX_SR_IPL_0	(0x0000)
-#define MCF5XXX_SR_IPL_1	(0x0100)
-#define MCF5XXX_SR_IPL_2	(0x0200)
-#define MCF5XXX_SR_IPL_3	(0x0300)
-#define MCF5XXX_SR_IPL_4	(0x0400)
-#define MCF5XXX_SR_IPL_5	(0x0500)
-#define MCF5XXX_SR_IPL_6	(0x0600)
-#define MCF5XXX_SR_IPL_7	(0x0700)
-#define MCF5XXX_SR_X		(0x0010)
-#define MCF5XXX_SR_N		(0x0008)
-#define MCF5XXX_SR_Z		(0x0004)
-#define MCF5XXX_SR_V		(0x0002)
-#define MCF5XXX_SR_C		(0x0001)
-
-#define MCF5XXX_CACR_CENB		(0x80000000)
-#define MCF5XXX_CACR_CPDI		(0x10000000)
-#define MCF5XXX_CACR_CPD		(0x10000000)
-#define MCF5XXX_CACR_CFRZ		(0x08000000)
-#define MCF5XXX_CACR_CINV		(0x01000000)
-#define MCF5XXX_CACR_DIDI		(0x00800000)
-#define MCF5XXX_CACR_DISD		(0x00400000)
-#define MCF5XXX_CACR_INVI		(0x00200000)
-#define MCF5XXX_CACR_INVD		(0x00100000)
-#define MCF5XXX_CACR_CEIB		(0x00000400)
-#define MCF5XXX_CACR_DCM_WR		(0x00000000)
-#define MCF5XXX_CACR_DCM_CB		(0x00000100)
-#define MCF5XXX_CACR_DCM_IP		(0x00000200)
-#define MCF5XXX_CACR_DCM		(0x00000200)
-#define MCF5XXX_CACR_DCM_II		(0x00000300)
-#define MCF5XXX_CACR_DBWE		(0x00000100)
-#define MCF5XXX_CACR_DWP		(0x00000020)
-#define MCF5XXX_CACR_EUST		(0x00000010)
-#define MCF5XXX_CACR_CLNF_00	(0x00000000)
-#define MCF5XXX_CACR_CLNF_01	(0x00000002)
-#define MCF5XXX_CACR_CLNF_10	(0x00000004)
-#define MCF5XXX_CACR_CLNF_11	(0x00000006)
-
-#define MCF5XXX_ACR_AB(a)		((a)&0xFF000000)
-#define MCF5XXX_ACR_AM(a)		(((a)&0xFF000000) >> 8)
-#define MCF5XXX_ACR_EN			(0x00008000)
-#define MCF5XXX_ACR_SM_USER		(0x00000000)
-#define MCF5XXX_ACR_SM_SUPER	(0x00002000)
-#define MCF5XXX_ACR_SM_IGNORE	(0x00006000)
-#define MCF5XXX_ACR_ENIB		(0x00000080)
-#define MCF5XXX_ACR_CM			(0x00000040)
-#define MCF5XXX_ACR_DCM_WR		(0x00000000)
-#define MCF5XXX_ACR_DCM_CB		(0x00000020)
-#define MCF5XXX_ACR_DCM_IP		(0x00000040)
-#define MCF5XXX_ACR_DCM_II		(0x00000060)
-#define MCF5XXX_ACR_CM			(0x00000040)
-#define MCF5XXX_ACR_BWE			(0x00000020)
-#define MCF5XXX_ACR_WP			(0x00000004)
-
-#define MCF5XXX_RAMBAR_BA(a)	((a)&0xFFFFC000)
-#define MCF5XXX_RAMBAR_PRI_00	(0x00000000)
-#define MCF5XXX_RAMBAR_PRI_01	(0x00004000)
-#define MCF5XXX_RAMBAR_PRI_10	(0x00008000)
-#define MCF5XXX_RAMBAR_PRI_11	(0x0000C000)
-#define MCF5XXX_RAMBAR_WP		(0x00000100)
-#define MCF5XXX_RAMBAR_CI		(0x00000020)
-#define MCF5XXX_RAMBAR_SC		(0x00000010)
-#define MCF5XXX_RAMBAR_SD		(0x00000008)
-#define MCF5XXX_RAMBAR_UC		(0x00000004)
-#define MCF5XXX_RAMBAR_UD		(0x00000002)
-#define MCF5XXX_RAMBAR_V		(0x00000001)
-
-/***********************************************************************/
-/*
- * The ColdFire family of processors has a simplified exception stack
- * frame that looks like the following:
- *
- *              3322222222221111 111111
- *              1098765432109876 5432109876543210
- *           8 +----------------+----------------+
- *             |         Program Counter         |
- *           4 +----------------+----------------+
- *             |FS/Fmt/Vector/FS|      SR        |
- *   SP -->  0 +----------------+----------------+
- *
- * The stack self-aligns to a 4-byte boundary at an exception, with
- * the FS/Fmt/Vector/FS field indicating the size of the adjustment
- * (SP += 0,1,2,3 bytes).
- */
-
-#define MCF5XXX_RD_SF_FORMAT(PTR)	\
-	((*((uint16 *)(PTR)) >> 12) & 0x00FF)
-
-#define MCF5XXX_RD_SF_VECTOR(PTR)	\
-	((*((uint16 *)(PTR)) >>  2) & 0x00FF)
-
-#define MCF5XXX_RD_SF_FS(PTR)		\
-	( ((*((uint16 *)(PTR)) & 0x0C00) >> 8) | (*((uint16 *)(PTR)) & 0x0003) )
-
-#define MCF5XXX_SF_SR(PTR)	*((uint16 *)(PTR)+1)
-#define MCF5XXX_SF_PC(PTR)	*((uint32 *)(PTR)+1)
-
-/********************************************************************/
-/*
- * Functions provided by mcf5xxx.s
- */
- 
-int 	asm_set_ipl (uint32);
-void	mcf5xxx_wr_cacr (uint32);
-void	mcf5xxx_wr_acr0 (uint32);
-void	mcf5xxx_wr_acr1 (uint32);
-void	mcf5xxx_wr_acr2 (uint32);
-void	mcf5xxx_wr_acr3 (uint32);
-void	mcf5xxx_wr_other_a7 (uint32);
-void	mcf5xxx_wr_other_sp (uint32);
-void	mcf5xxx_wr_vbr (uint32);
-void	mcf5xxx_wr_macsr (uint32);
-void	mcf5xxx_wr_mask (uint32);
-void	mcf5xxx_wr_acc0 (uint32);
-void	mcf5xxx_wr_accext01 (uint32);
-void	mcf5xxx_wr_accext23 (uint32);
-void	mcf5xxx_wr_acc1 (uint32);
-void	mcf5xxx_wr_acc2 (uint32);
-void	mcf5xxx_wr_acc3 (uint32);
-void	mcf5xxx_wr_sr (uint32);
-void	mcf5xxx_wr_rambar0 (uint32);
-void	mcf5xxx_wr_rambar1 (uint32);
-void	mcf5xxx_wr_mbar (uint32);
-void	mcf5xxx_wr_mbar0 (uint32);
-void	mcf5xxx_wr_mbar1 (uint32);
-
-/********************************************************************/
-
-#endif	/* _CPU_MCF5XXX_H */
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/CHANGELOG b/Demo/lwIP_MCF5235_GCC/lwip/CHANGELOG
deleted file mode 100644
index 0bf28ac56..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/CHANGELOG
+++ /dev/null
@@ -1,596 +0,0 @@
-FUTURE
-
-  * TODO: The lwIP source code makes some invalid assumptions on processor
-    word-length, storage sizes and alignment. See the mailing lists for
-    problems with exoteric (/DSP) architectures showing these problems.
-    We still have to fix some of these issues neatly.
-
-  * TODO: the ARP layer is not protected against concurrent access. If
-    you run from a multitasking OS, serialize access to ARP (called from
-    your network device driver and from a timeout thread.)
-
-  * TODO: the PPP code is broken in a few ways. There are namespace
-    collisions on BSD systems and many assumptions on word-length
-    (sizeof(int)). In ppp.c an assumption is made on the availability of
-    a thread subsystem. Either PPP needs to be moved to contrib/ports/???
-    or rearranged to be more generic.
-
-HISTORY
-
-(CVS HEAD)
-
-  * [New changes go here]
-
-(STABLE-1_1_1)
-
-  2006-03-03  Christiaan Simons
-  * ipv4/ip_frag.c: Added bound-checking assertions on ip_reassbitmap
-    access and added pbuf_alloc() return value checks.
-
-  2006-01-01  Leon Woestenberg 
-  * tcp_{in,out}.c, tcp_out.c: Removed 'even sndbuf' fix in TCP, which is
-    now handled by the checksum routine properly.
-
-  2006-02-27  Leon Woestenberg 
-   * pbuf.c: Fix alignment; pbuf_init() would not work unless
-     pbuf_pool_memory[] was properly aligned. (Patch by Curt McDowell.)
-
-  2005-12-20  Leon Woestenberg 
-  * tcp.c: Remove PCBs which stay in LAST_ACK state too long. Patch
-    submitted by Mitrani Hiroshi.
-    
-  2005-12-15  Christiaan Simons
-  * inet.c: Disabled the added summing routine to preserve code space.
-
-  2005-12-14  Leon Woestenberg 
-  * tcp_in.c: Duplicate FIN ACK race condition fix by Kelvin Lawson.
-    Added Curt McDowell's optimized checksumming routine for future
-    inclusion. Need to create test case for unaliged, aligned, odd,
-    even length combination of cases on various endianess machines.
-
-  2005-12-09  Christiaan Simons
-  * inet.c: Rewrote standard checksum routine in proper portable C.
-
-  2005-11-25  Christiaan Simons
-  * udp.c tcp.c: Removed SO_REUSE hack. Should reside in socket code only.
-  * *.c: introduced cc.h LWIP_DEBUG formatters matching the u16_t, s16_t,
-    u32_t, s32_t typedefs. This solves most debug word-length assumes.  
-
-  2005-07-17 Leon Woestenberg 
-  * inet.c: Fixed unaligned 16-bit access in the standard checksum
-    routine by Peter Jolasson.
-  * slipif.c: Fixed implementation assumption of single-pbuf datagrams.
-
-  2005-02-04 Leon Woestenberg 
-  * tcp_out.c: Fixed uninitialized 'queue' referenced in memerr branch.
-  * tcp_{out|in}.c: Applied patch fixing unaligned access.
-
-  2005-01-04 Leon Woestenberg 
-  * pbuf.c: Fixed missing semicolon after LWIP_DEBUG statement.
-
-  2005-01-03 Leon Woestenberg 
-  * udp.c: UDP pcb->recv() was called even when it was NULL.
-
-(STABLE-1_1_0)
-
-  2004-12-28 Leon Woestenberg 
-  * etharp.*: Disabled multiple packets on the ARP queue.
-    This clashes with TCP queueing.
-
-  2004-11-28 Leon Woestenberg 
-  * etharp.*: Fixed race condition from ARP request to ARP timeout.
-    Halved the ARP period, doubled the period counts.
-    ETHARP_MAX_PENDING now should be at least 2. This prevents
-    the counter from reaching 0 right away (which would allow
-    too little time for ARP responses to be received).
-    
-  2004-11-25 Leon Woestenberg 
-  * dhcp.c: Decline messages were not multicast but unicast.
-  * etharp.c: ETHARP_CREATE is renamed to ETHARP_TRY_HARD.
-    Do not try hard to insert arbitrary packet's source address,
-    etharp_ip_input() now calls etharp_update() without ETHARP_TRY_HARD. 
-    etharp_query() now always DOES call ETHARP_TRY_HARD so that users
-    querying an address will see it appear in the cache (DHCP could
-    suffer from this when a server invalidly gave an in-use address.)
-  * ipv4/ip_addr.h: Renamed ip_addr_maskcmp() to _netcmp() as we are
-    comparing network addresses (identifiers), not the network masks
-    themselves.
-  * ipv4/ip_addr.c: ip_addr_isbroadcast() now checks that the given
-    IP address actually belongs to the network of the given interface.
-
-  2004-11-24 Kieran Mansley 
-  * tcp.c: Increment pcb->snd_buf when ACK is received in SYN_SENT state.
-
-(STABLE-1_1_0-RC1)
-
-  2004-10-16 Kieran Mansley 
-  * tcp.c: Add code to tcp_recved() to send an ACK (window update) immediately,
-	even if one is already pending, if the rcv_wnd is above a threshold
-	(currently TCP_WND/2). This avoids waiting for a timer to expire to send a
-	delayed ACK in order to open the window if the stack is only receiving data.
-
-  2004-09-12 Kieran Mansley 
-  * tcp*.*: Retransmit time-out handling improvement by Sam Jansen.
-
-  2004-08-20 Tony Mountifield 
-  * etharp.c: Make sure the first pbuf queued on an ARP entry
-    is properly ref counted.
-
-  2004-07-27 Tony Mountifield 
-  * debug.h: Added (int) cast in LWIP_DEBUGF() to avoid compiler
-    warnings about comparison.
-  * pbuf.c: Stopped compiler complaining of empty if statement
-    when LWIP_DEBUGF() empty.  Closed an unclosed comment.
-  * tcp.c: Stopped compiler complaining of empty if statement
-    when LWIP_DEBUGF() empty.
-  * ip.h Corrected IPH_TOS() macro: returns a byte, so doesn't need htons().
-  * inet.c: Added a couple of casts to quiet the compiler.
-    No need to test isascii(c) before isdigit(c) or isxdigit(c).
-
-  2004-07-22 Tony Mountifield 
-  * inet.c: Made data types consistent in inet_ntoa().
-    Added casts for return values of checksum routines, to pacify compiler.
-  * ip_frag.c, tcp_out.c, sockets.c, pbuf.c
-    Small corrections to some debugging statements, to pacify compiler.
-
-  2004-07-21 Tony Mountifield 
-  * etharp.c: Removed spurious semicolon and added missing end-of-comment.
-  * ethernetif.c Updated low_level_output() to match prototype for
-    netif->linkoutput and changed low_level_input() similarly for consistency.
-  * api_msg.c: Changed recv_raw() from int to u8_t, to match prototype
-    of raw_recv() in raw.h and so avoid compiler error.
-  * sockets.c: Added trivial (int) cast to keep compiler happier.
-  * ip.c, netif.c Changed debug statements to use the tidier ip4_addrN() macros.
-  
-(STABLE-1_0_0)
-
-  ++ Changes:
-
-  2004-07-05 Leon Woestenberg 
-  * sockets.*: Restructured LWIP_PRIVATE_TIMEVAL. Make sure
-    your cc.h file defines this either 1 or 0. If non-defined,
-    defaults to 1.
-  * .c: Added  and  includes where used.
-  * etharp.c: Made some array indices unsigned.
-
-  2004-06-27 Leon Woestenberg 
-  * netif.*: Added netif_set_up()/down().
-  * dhcp.c: Changes to restart program flow.
-
-  2004-05-07 Leon Woestenberg 
-  * etharp.c: In find_entry(), instead of a list traversal per candidate, do a
-    single-pass lookup for different candidates. Should exploit locality.
-
-  2004-04-29 Leon Woestenberg 
-  * tcp*.c: Cleaned up source comment documentation for Doxygen processing.
-  * opt.h: ETHARP_ALWAYS_INSERT option removed to comply with ARP RFC.
-  * etharp.c: update_arp_entry() only adds new ARP entries when adviced to by
-    the caller. This deprecates the ETHARP_ALWAYS_INSERT overrule option.
-
-  ++ Bug fixes:
-
-  2004-04-27 Leon Woestenberg 
-  * etharp.c: Applied patch of bug #8708 by Toni Mountifield with a solution
-    suggested by Timmy Brolin. Fix for 32-bit processors that cannot access
-    non-aligned 32-bit words, such as soms 32-bit TCP/IP header fields. Fix
-    is to prefix the 14-bit Ethernet headers with two padding bytes.
-
-  2004-04-23 Leon Woestenberg 
-  * ip_addr.c: Fix in the ip_addr_isbroadcast() check.
-  * etharp.c: Fixed the case where the packet that initiates the ARP request
-    is not queued, and gets lost. Fixed the case where the packets destination
-    address is already known; we now always queue the packet and perform an ARP
-    request.
-  
-(STABLE-0_7_0)
-
-  ++ Bug fixes:
-
-  * Fixed TCP bug for SYN_SENT to ESTABLISHED state transition.
-  * Fixed TCP bug in dequeueing of FIN from out of order segment queue.
-  * Fixed two possible NULL references in rare cases.
-
-(STABLE-0_6_6)
-
-  ++ Bug fixes:
-
-  * Fixed DHCP which did not include the IP address in DECLINE messages.
-
-  ++ Changes:
-
-  * etharp.c has been hauled over a bit.
-
-(STABLE-0_6_5)
-
-  ++ Bug fixes:
-
-  * Fixed TCP bug induced by bad window resizing with unidirectional TCP traffic.
-  * Packets sent from ARP queue had invalid source hardware address.
-
-  ++ Changes:
-
-  * Pass-by ARP requests do now update the cache.
-
-  ++ New features:
-
-  * No longer dependent on ctype.h.
-  * New socket options.
-  * Raw IP pcb support.
-
-(STABLE-0_6_4)
-
-  ++ Bug fixes:
-
-  * Some debug formatters and casts fixed.
-  * Numereous fixes in PPP.
-
-  ++ Changes:
-
-  * DEBUGF now is LWIP_DEBUGF
-  * pbuf_dechain() has been re-enabled.
-  * Mentioned the changed use of CVS branches in README.
-
-(STABLE-0_6_3)
-
-  ++ Bug fixes:
-
-  * Fixed pool pbuf memory leak in pbuf_alloc().
-    Occured if not enough PBUF_POOL pbufs for a packet pbuf chain.
-    Reported by Savin Zlobec.
-
-  * PBUF_POOL chains had their tot_len field not set for non-first
-    pbufs. Fixed in pbuf_alloc().
-
-  ++ New features:
-
-  * Added PPP stack contributed by Marc Boucher
-
-  ++ Changes:
-
-  * Now drops short packets for ICMP/UDP/TCP protocols. More robust.
-
-  * ARP queueuing now queues the latest packet instead of the first.
-    This is the RFC recommended behaviour, but can be overridden in
-    lwipopts.h.
-
-(0.6.2)
-
-  ++ Bugfixes:
-
-  * TCP has been fixed to deal with the new use of the pbuf->ref
-    counter.
-
-  * DHCP dhcp_inform() crash bug fixed.
-
-  ++ Changes:
-
-  * Removed pbuf_pool_free_cache and pbuf_pool_alloc_cache. Also removed
-    pbuf_refresh(). This has sped up pbuf pool operations considerably.
-    Implemented by David Haas.
-
-(0.6.1)
-
-  ++ New features:
-
-  * The packet buffer implementation has been enhanced to support
-    zero-copy and copy-on-demand for packet buffers which have their
-    payloads in application-managed memory.
-    Implemented by David Haas.
-
-    Use PBUF_REF to make a pbuf refer to RAM. lwIP will use zero-copy
-    if an outgoing packet can be directly sent on the link, or perform
-    a copy-on-demand when necessary.
-
-    The application can safely assume the packet is sent, and the RAM
-    is available to the application directly after calling udp_send()
-    or similar function.
-
-  ++ Bugfixes:
-
-  * ARP_QUEUEING should now correctly work for all cases, including
-    PBUF_REF.
-    Implemented by Leon Woestenberg.
-
-  ++ Changes:
-
-  * IP_ADDR_ANY is no longer a NULL pointer. Instead, it is a pointer
-    to a '0.0.0.0' IP address.
-
-  * The packet buffer implementation is changed. The pbuf->ref counter
-    meaning has changed, and several pbuf functions have been
-    adapted accordingly.
-
-  * netif drivers have to be changed to set the hardware address length field
-    that must be initialized correctly by the driver (hint: 6 for Ethernet MAC).
-    See the contrib/ports/c16x cs8900 driver as a driver example.
-
-  * netif's have a dhcp field that must be initialized to NULL by the driver.
-    See the contrib/ports/c16x cs8900 driver as a driver example.
-
-(0.5.x) This file has been unmaintained up to 0.6.1. All changes are
-  logged in CVS but have not been explained here.
-
-(0.5.3) Changes since version 0.5.2
-
-  ++ Bugfixes:
-
-  * memp_malloc(MEMP_API_MSG) could fail with multiple application
-    threads because it wasn't protected by semaphores.
-
-  ++ Other changes:
-
-  * struct ip_addr now packed.
-
-  * The name of the time variable in arp.c has been changed to ctime
-    to avoid conflicts with the time() function.
-
-(0.5.2) Changes since version 0.5.1
-
-  ++ New features:
-
-  * A new TCP function, tcp_tmr(), now handles both TCP timers.
-
-  ++ Bugfixes:
-
-  * A bug in tcp_parseopt() could cause the stack to hang because of a
-    malformed TCP option.
-
-  * The address of new connections in the accept() function in the BSD
-    socket library was not handled correctly.
-
-  * pbuf_dechain() did not update the ->tot_len field of the tail.
-
-  * Aborted TCP connections were not handled correctly in all
-    situations.
-
-  ++ Other changes:
-
-  * All protocol header structs are now packed.
-
-  * The ->len field in the tcp_seg structure now counts the actual
-    amount of data, and does not add one for SYN and FIN segments.
-
-(0.5.1) Changes since version 0.5.0
-
-  ++ New features:
-
-  * Possible to run as a user process under Linux.
-
-  * Preliminary support for cross platform packed structs.
-
-  * ARP timer now implemented.
-
-  ++ Bugfixes:
-
-  * TCP output queue length was badly initialized when opening
-    connections.
-
-  * TCP delayed ACKs were not sent correctly.
-
-  * Explicit initialization of BSS segment variables.
-
-  * read() in BSD socket library could drop data.
-
-  * Problems with memory alignment.
-
-  * Situations when all TCP buffers were used could lead to
-    starvation.
-
-  * TCP MSS option wasn't parsed correctly.
-
-  * Problems with UDP checksum calculation.
-
-  * IP multicast address tests had endianess problems.
-
-  * ARP requests had wrong destination hardware address.
-
-  ++ Other changes:
-
-  * struct eth_addr changed from u16_t[3] array to u8_t[6].
-
-  * A ->linkoutput() member was added to struct netif.
-
-  * TCP and UDP ->dest_* struct members where changed to ->remote_*.
-
-  * ntoh* macros are now null definitions for big endian CPUs.
-
-(0.5.0) Changes since version 0.4.2
-
-  ++ New features:
-
-  * Redesigned operating system emulation layer to make porting easier.
-
-  * Better control over TCP output buffers.
-
-  * Documenation added.
-
-  ++ Bugfixes:
-
-  * Locking issues in buffer management.
-
-  * Bugfixes in the sequential API.
-
-  * IP forwarding could cause memory leakage. This has been fixed.
-
-  ++ Other changes:
-
-  * Directory structure somewhat changed; the core/ tree has been
-    collapsed.
-
-(0.4.2) Changes since version 0.4.1
-
-  ++ New features:
-
-  * Experimental ARP implementation added.
-
-  * Skeleton Ethernet driver added.
-
-  * Experimental BSD socket API library added.
-
-  ++ Bugfixes:
-
-  * In very intense situations, memory leakage could occur. This has
-    been fixed.
-
-  ++ Other changes:
-
-  * Variables named "data" and "code" have been renamed in order to
-    avoid name conflicts in certain compilers.
-
-  * Variable++ have in appliciable cases been translated to ++variable
-    since some compilers generate better code in the latter case.
-
-(0.4.1) Changes since version 0.4
-
-  ++ New features:
-
-  * TCP: Connection attempts time out earlier than data
-    transmissions. Nagle algorithm implemented. Push flag set on the
-    last segment in a burst.
-
-  * UDP: experimental support for UDP-Lite extensions.
-
-  ++ Bugfixes:
-
-  * TCP: out of order segments were in some cases handled incorrectly,
-    and this has now been fixed. Delayed acknowledgements was broken
-    in 0.4, has now been fixed. Binding to an address that is in use
-    now results in an error. Reset connections sometimes hung an
-    application; this has been fixed.
-
-  * Checksum calculation sometimes failed for chained pbufs with odd
-    lengths. This has been fixed.
-
-  * API: a lot of bug fixes in the API. The UDP API has been improved
-    and tested. Error reporting and handling has been
-    improved. Logical flaws and race conditions for incoming TCP
-    connections has been found and removed.
-
-  * Memory manager: alignment issues. Reallocating memory sometimes
-    failed, this has been fixed.
-
-  * Generic library: bcopy was flawed and has been fixed.
-
-  ++ Other changes:
-
-  * API: all datatypes has been changed from generic ones such as
-    ints, to specified ones such as u16_t. Functions that return
-    errors now have the correct type (err_t).
-
-  * General: A lot of code cleaned up and debugging code removed. Many
-    portability issues have been fixed.
-
-  * The license was changed; the advertising clause was removed.
-
-  * C64 port added.
-
-  * Thanks: Huge thanks go to Dagan Galarneau, Horst Garnetzke, Petri
-    Kosunen, Mikael Caleres, and Frits Wilmink for reporting and
-    fixing bugs!
-
-(0.4) Changes since version 0.3.1
-
-  * Memory management has been radically changed; instead of
-    allocating memory from a shared heap, memory for objects that are
-    rapidly allocated and deallocated is now kept in pools. Allocation
-    and deallocation from those memory pools is very fast. The shared
-    heap is still present but is used less frequently.
-
-  * The memory, memory pool, and packet buffer subsystems now support
-    4-, 2-, or 1-byte alignment.
-
-  * "Out of memory" situations are handled in a more robust way.
-
-  * Stack usage has been reduced.
-
-  * Easier configuration of lwIP parameters such as memory usage,
-    TTLs, statistics gathering, etc. All configuration parameters are
-    now kept in a single header file "lwipopts.h".
-
-  * The directory structure has been changed slightly so that all
-    architecture specific files are kept under the src/arch
-    hierarchy.
-
-  * Error propagation has been improved, both in the protocol modules
-    and in the API.
-
-  * The code for the RTXC architecture has been implemented, tested
-    and put to use.
-
-  * Bugs have been found and corrected in the TCP, UDP, IP, API, and
-    the Internet checksum modules.
-
-  * Bugs related to porting between a 32-bit and a 16-bit architecture
-    have been found and corrected.
-
-  * The license has been changed slightly to conform more with the
-    original BSD license, including the advertisement clause.
-
-(0.3.1) Changes since version 0.3
-
-  * Fix of a fatal bug in the buffer management. Pbufs with allocated
-    RAM never returned the RAM when the pbuf was deallocated.
-
-  * TCP congestion control, window updates and retransmissions did not
-    work correctly. This has now been fixed.
-
-  * Bugfixes in the API.
-
-(0.3) Changes since version 0.2
-
-  * New and improved directory structure. All include files are now
-    kept in a dedicated include/ directory.
-
-  * The API now has proper error handling. A new function,
-    netconn_err(), now returns an error code for the connection in
-    case of errors.
-
-  * Improvements in the memory management subsystem. The system now
-    keeps a pointer to the lowest free memory block. A new function,
-    mem_malloc2() tries to allocate memory once, and if it fails tries
-    to free some memory and retry the allocation.
-
-  * Much testing has been done with limited memory
-    configurations. lwIP now does a better job when overloaded.
-
-  * Some bugfixes and improvements to the buffer (pbuf) subsystem.
-
-  * Many bugfixes in the TCP code:
-
-    - Fixed a bug in tcp_close().
-
-    - The TCP receive window was incorrectly closed when out of
-      sequence segments was received. This has been fixed.
-
-    - Connections are now timed-out of the FIN-WAIT-2 state.
-
-    - The initial congestion window could in some cases be too
-      large. This has been fixed.
-
-    - The retransmission queue could in some cases be screwed up. This
-      has been fixed.
-
-    - TCP RST flag now handled correctly.
-
-    - Out of sequence data was in some cases never delivered to the
-      application. This has been fixed.
-
-    - Retransmitted segments now contain the correct acknowledgment
-      number and advertised window.
-
-    - TCP retransmission timeout backoffs are not correctly computed
-      (ala BSD). After a number of retransmissions, TCP now gives up
-      the connection.
-
-  * TCP connections now are kept on three lists, one for active
-    connections, one for listening connections, and one for
-    connections that are in TIME-WAIT. This greatly speeds up the fast
-    timeout processing for sending delayed ACKs.
-
-  * TCP now provides proper feedback to the application when a
-    connection has been successfully set up.
-
-  * More comments have been added to the code. The code has also been
-    somewhat cleaned up.
-
-(0.2) Initial public release.
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/COPYING b/Demo/lwIP_MCF5235_GCC/lwip/COPYING
deleted file mode 100644
index e23898b5e..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/COPYING
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright (c) 2001, 2002 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/FILES b/Demo/lwIP_MCF5235_GCC/lwip/FILES
deleted file mode 100644
index 66253196f..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/FILES
+++ /dev/null
@@ -1,4 +0,0 @@
-src/      - The source code for the lwIP TCP/IP stack.
-doc/      - The documentation for lwIP.
-
-See also the FILES file in each subdirectory.
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/README b/Demo/lwIP_MCF5235_GCC/lwip/README
deleted file mode 100644
index d9102826f..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/README
+++ /dev/null
@@ -1,74 +0,0 @@
-INTRODUCTION
-
-lwIP is a small independent implementation of the TCP/IP protocol
-suite that has been developed by Adam Dunkels at the Computer and
-Networks Architectures (CNA) lab at the Swedish Institute of Computer
-Science (SICS).
-
-The focus of the lwIP TCP/IP implementation is to reduce the RAM usage
-while still having a full scale TCP. This making lwIP suitable for use
-in embedded systems with tens of kilobytes of free RAM and room for
-around 40 kilobytes of code ROM.
-
-FEATURES
-
- * IP (Internet Protocol) including packet forwarding over multiple
-   network interfaces
- * ICMP (Internet Control Message Protocol) for network maintenance
-   and debugging
- * UDP (User Datagram Protocol) including experimental UDP-lite
-   extensions
- * TCP (Transmission Control Protocol) with congestion control, RTT
-   estimation and fast recovery/fast retransmit
- * Specialized API for enhanced performance
- * Optional Berkeley socket API
-
-LICENSE
-
-lwIP is freely available under a BSD license.
-
-DEVELOPMENT
-
-lwIP has grown into an excellent TCP/IP stack for embedded devices,
-and developers using the stack often submit bug fixes, improvements,
-and additions to the stack to further increase its usefulness.
-
-Development of lwIP is hosted on Savannah, a central point for
-software development, maintenance and distribution. Everyone can
-help improve lwIP by use of Savannah's interface, CVS and the
-mailing list. A core team of developers will commit changes to the
-CVS source tree.
-
-The lwIP TCP/IP stack is maintained in the 'lwip' CVS module and
-contributions (such as platform ports) are in the 'contrib' module.
-
-See doc/savannah.txt for details on CVS server access for users and
-developers.
-
-Last night's CVS tar ball can be downloaded from:
-  http://savannah.gnu.org/cvs.backups/lwip.tar.gz [CHANGED - NEEDS FIXING]
-
-The current CVS trees are web-browsable:
-  http://savannah.nongnu.org/cgi-bin/viewcvs/lwip/lwip/
-  http://savannah.nongnu.org/cgi-bin/viewcvs/lwip/contrib/
-
-Submit patches and bugs via the lwIP project page:
-  http://savannah.nongnu.org/projects/lwip/
-
-
-DOCUMENTATION
-
-The original out-dated homepage of lwIP and Adam Dunkels' papers on
-lwIP are at the official lwIP home page:
-  http://www.sics.se/~adam/lwip/
-
-Self documentation of the source code is regularly extracted from the
-current CVS sources and is available from this web page:
-  http://www.nongnu.org/lwip/
-
-Reading Adam's papers, the files in docs/, browsing the source code
-documentation and browsing the mailing list archives is a good way to
-become familiar with the design of lwIP.
-
-Adam Dunkels 
-Leon Woestenberg 		    
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/arch/cc.h b/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/arch/cc.h
deleted file mode 100644
index 377f219f8..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/arch/cc.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels 
- * Modifcations: Christian Walter 
- */
-#ifndef __CC_H__
-#define __CC_H__
-
-/* ------------------------ System includes ------------------------------- */
-#include 
-
-/* ------------------------ Project includes ------------------------------ */
-#include "cpu.h"
-#include "sys_arch.h"
-
-/* ------------------------ Defines --------------------------------------- */
-
-#define PACK_STRUCT_BEGIN
-#define PACK_STRUCT_STRUCT      __attribute__ ((__packed__))
-#define PACK_STRUCT_END
-
-#define PACK_STRUCT_FIELD( x )  x
-
-#define ALIGN_STRUCT_8_BEGIN
-#define ALIGN_STRUCT_8          __attribute__ ((aligned (8)))
-#define ALIGN_STRUCT_8_END
-
-#define LWIP_PLATFORM_ASSERT( x ) sys_assert( x )
-#define LWIP_PLATFORM_DIAG( x, ... ) do{ sys_debug x; } while( 0 );
-
-/* Define (sn)printf formatters for these lwIP types */
-#define U16_F                   "hu"
-#define S16_F                   "hd"
-#define X16_F                   "hx"
-#define U32_F                   "lu"
-#define S32_F                   "ld"
-#define X32_F                   "lx"
-
-/* ------------------------ Type definitions (lwIP) ----------------------- */
-typedef unsigned char u8_t;
-typedef signed char s8_t;
-typedef unsigned short u16_t;
-typedef signed short s16_t;
-typedef unsigned long u32_t;
-typedef signed long s32_t;
-typedef u32_t   mem_ptr_t;
-typedef int     sys_prot_t;
-
-/* ------------------------ Prototypes ------------------------------------ */
-
-#endif
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/arch/cpu.h b/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/arch/cpu.h
deleted file mode 100644
index 743f80810..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/arch/cpu.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels 
- *
- */
-#ifndef __CPU_H__
-#define __CPU_H__
-
-/* ------------------------ Defines --------------------------------------- */
-#define BYTE_ORDER BIG_ENDIAN
-
-#endif
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/arch/perf.h b/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/arch/perf.h
deleted file mode 100644
index f94640e9f..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/arch/perf.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels 
- *
- */
-#ifndef __PERF_H__
-#define __PERF_H__
-
-/* ------------------------ Defines --------------------------------------- */
-#define PERF_START              /* null definition */
-#define PERF_STOP(x)            /* null definition */
-
-#endif
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/arch/sys_arch.h b/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/arch/sys_arch.h
deleted file mode 100644
index 9e47406ca..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/arch/sys_arch.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels 
- *
- */
-#ifndef __SYS_ARCH_H__
-#define __SYS_ARCH_H__
-
-/* ------------------------ Project includes ------------------------------ */
-#include "FreeRTOS.h"
-#include "task.h"
-#include "queue.h"
-#include "semphr.h"
-
-/* ------------------------ Defines --------------------------------------- */
-#define SYS_MBOX_NULL           ( xQueueHandle )0
-#define SYS_THREAD_NULL         NULL
-#define SYS_SEM_NULL            ( xSemaphoreHandle )0
-#define SIO_FD_NULL             ( sio_fd_t )NULL
-
-/* ------------------------ Type definitions ------------------------------ */
-
-
-typedef xSemaphoreHandle sys_sem_t;
-typedef xQueueHandle sys_mbox_t;
-typedef void   *sys_thread_t;
-
-/* ------------------------ Prototypes ------------------------------------ */
-sys_thread_t    sys_arch_thread_new( void ( *thread ) ( void *arg ), void *arg,
-                                     int prio, size_t ssize );
-sys_thread_t    sys_arch_thread_current( void );
-void            sys_arch_thread_remove( sys_thread_t hdl );
-void            sys_assert( const char *const msg );
-void            sys_debug( const char *const fmt, ... );
-
-#endif
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/netif/fec.c b/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/netif/fec.c
deleted file mode 100644
index d114dfb7c..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/netif/fec.c
+++ /dev/null
@@ -1,582 +0,0 @@
-/*
- * Copyright (c) 2006 Christian Walter
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * Author: Christian Walter 
- *
- * TODO:
- *  - Introduce another task create function in the sys_arch layer which allows
- *    for passing the stack size.
- *  - Avoid copying the buffers - this requires changeing the nbuf driver code
- *    to use the lwIP pbuf buffer implementation.
- *
- * File: $Id: fec.c,v 1.3 2006/08/29 18:53:46 wolti Exp $
- */
-
-/* ------------------------ System includes ------------------------------- */
-#include 
-
-/* ------------------------ Platform includes ----------------------------- */
-#include "mcf5xxx.h"
-#include "mcf523x.h"
-
-#include "nbuf.h"
-
-/* ------------------------ lwIP includes --------------------------------- */
-#include "lwip/opt.h"
-#include "lwip/def.h"
-#include "lwip/mem.h"
-#include "lwip/pbuf.h"
-#include "lwip/sys.h"
-#include "lwip/stats.h"
-#include "lwip/debug.h"
-#include "netif/etharp.h"
-
-/* ------------------------ Defines --------------------------------------- */
-#ifdef FEC_DEBUG
-#define FEC_DEBUG_INIT \
-    do \
-    { \
-        MCF_GPIO_PDDR_FECI2C = ( MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 | \
-                                 MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 ); \
-    } while( 0 )
-
-#define FEC_DEBUG_RX_TIMING( x ) \
-    do \
-    { \
-        if( x ) \
-            MCF_GPIO_PPDSDR_FECI2C = MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0; \
-        else \
-            MCF_GPIO_PCLRR_FECI2C = ~( MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 ); \
-    } while( 0 )
-
-#define FEC_DEBUG_TX_TIMING( x ) \
-    do \
-    { \
-        if( x ) \
-            MCF_GPIO_PPDSDR_FECI2C = MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1; \
-        else \
-            MCF_GPIO_PCLRR_FECI2C = ~( MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 ); \
-    } while( 0 )
-
-#else
-#define FEC_DEBUG               DBG_OFF
-#define FEC_DEBUG_INIT
-#define FEC_DEBUG_RX_TIMING( x )
-#define FEC_DEBUG_TX_TIMING( x )
-#endif
-
-#define MCF_FEC_INT_LEVEL       ( 6 )
-#define MCF_FEC_INT_PRIORITY    ( 0 )
-#define MCF_FEC_VEC_RXF         ( 64 + 27 )
-#define MCF_FEC_MTU             ( 1518 )
-
-#define ETH_ADDR_LEN            ( 6 )
-
-#define TASK_PRIORITY           ( configMAX_PRIORITIES - 1 )
-
-/* ------------------------ Type definitions ------------------------------ */
-typedef struct
-{
-    struct netif   *netif;      /* lwIP network interface. */
-    struct eth_addr *self;      /* MAC address of FEC interface. */
-    sys_sem_t       tx_sem;     /* Control access to transmitter. */
-    sys_sem_t       rx_sem;     /* Semaphore to signal receive thread. */
-} mcf523xfec_if_t;
-
-/* ------------------------ Static variables ------------------------------ */
-static mcf523xfec_if_t *fecif_g;
-
-/* ------------------------ Static functions ------------------------------ */
-static err_t    mcf523xfec_output( struct netif *, struct pbuf *, struct ip_addr * );
-static err_t    mcf523xfec_output_raw( struct netif *, struct pbuf * );
-
-static void     mcf523xfec_reset( mcf523xfec_if_t * fecif );
-static void     mcf523xfec_enable( mcf523xfec_if_t * fecif );
-static void     mcf523xfec_disable( mcf523xfec_if_t * fecif );
-static void     mcf523xfec_get_mac( mcf523xfec_if_t * fecif, struct eth_addr *mac );
-static void     mcf523xfec_rx_irq( void );
-static void     mcf523xfec_rx_task( void *arg );
-
-static void     arp_timer( void *arg );
-static void     eth_input( struct netif *netif, struct pbuf *p );
-
-/* ------------------------ Start implementation -------------------------- */
-
-static void
-arp_timer( void *arg )
-{
-    ( void )arg;
-    etharp_tmr(  );
-    sys_timeout( ARP_TMR_INTERVAL, arp_timer, NULL );
-}
-
-err_t
-mcf523xfec_output_raw( struct netif *netif, struct pbuf *p )
-{
-    err_t           res;
-    nbuf_t         *pNBuf;
-    mcf523xfec_if_t *fecif = netif->state;
-    int             i;
-    struct pbuf    *q;
-
-#if ETH_PAD_SIZE
-    pbuf_header( p, -ETH_PAD_SIZE );    /* drop the padding word */
-#endif
-
-
-    /* Test if we can handle such big frames. If not drop it. */
-    if( p->tot_len > MCF_FEC_MTU )
-    {
-#if LINK_STATS
-        lwip_stats.link.lenerr++;
-#endif
-        res = ERR_BUF;
-    }
-    /* Test if our network buffer scheme can handle a packet of this size. If
-     * not drop it and return a memory error. */
-    else if( p->tot_len > TX_BUFFER_SIZE )
-    {
-#ifdef LINK_STATS
-        lwip_stats.link.memerr++;
-#endif
-        res = ERR_MEM;
-    }
-    /* Allocate a transmit buffer. If no buffer is available drop the frame. */
-    else if( ( pNBuf = nbuf_tx_allocate(  ) ) == NULL )
-    {
-        LWIP_ASSERT( "mcf523xfec_output_raw: pNBuf != NULL\n", pNBuf != NULL );
-#ifdef LINK_STATS
-        lwip_stats.link.memerr++;
-#endif
-        res = ERR_MEM;
-    }
-    else
-    {
-        q = p;
-        i = 0;
-        do
-        {
-            memcpy( &pNBuf->data[i], q->payload, q->len );
-            i += q->len;
-        }
-        while( ( q = q->next ) != NULL );
-        pNBuf->length = p->tot_len;
-
-        /* Set Frame ready for transmission. */
-        pNBuf->status |= TX_BD_R;
-        /* Mark the buffer as not in use so the FEC can take it. */
-        nbuf_tx_release( pNBuf );
-        /* Indicate that a new transmit buffer has been produced. */
-        MCF_FEC_TDAR = 1;
-#if LINK_STATS
-        lwip_stats.link.xmit++;
-#endif
-        res = ERR_OK;
-    }
-
-    sys_sem_signal( fecif->tx_sem );
-#if ETH_PAD_SIZE
-    buf_header( p, ETH_PAD_SIZE );
-#endif
-
-    return res;
-}
-
-/* This function is called by the TCP/IP stack when an IP packet should be
- * sent. It uses the ethernet ARP module provided by lwIP to resolve the
- * destination MAC address. The ARP module will later call our low level
- * output function mcf523xfec_output_raw.
- */
-err_t
-mcf523xfec_output( struct netif * netif, struct pbuf * p, struct ip_addr * ipaddr )
-{
-    err_t           res;
-    mcf523xfec_if_t *fecif = netif->state;
-
-    FEC_DEBUG_TX_TIMING( 1 );
-    /* Make sure only one thread is in this function. */
-    sys_sem_wait( fecif->tx_sem );
-    res = etharp_output( netif, ipaddr, p );
-    FEC_DEBUG_TX_TIMING( 0 );
-    return res;
-}
-
-void
-mcf523xfec_rx_task( void *arg )
-{
-    mcf523xfec_if_t *fecif = arg;
-    struct pbuf    *p, *q;
-    nbuf_t         *pNBuf;
-    uint8          *pPayLoad;
-
-    do
-    {
-        sys_sem_wait( fecif->rx_sem );
-        while( nbuf_rx_next_ready(  ) )
-        {
-            pNBuf = nbuf_rx_allocate(  );
-            if( pNBuf != NULL )
-            {
-                LWIP_ASSERT( "mcf523xfec_rx_task: pNBuf->status & RX_BD_L ",
-                             pNBuf->status & RX_BD_L );
-
-                /* This flags indicate that the frame has been damaged. In
-                 * this case we must update the link stats if enabled and
-                 * remove the frame from the FEC. */
-                if ( pNBuf->status & ( RX_BD_LG | RX_BD_NO |
-                                       RX_BD_CR | RX_BD_OV ) )
-                {
-#ifdef LINK_STATS
-                    lwip_stats.link.drop++;
-                    if ( pNBuf->status & RX_BD_LG)
-                    {
-                        lwip_stats.link.lenerr++;
-                    }
-                    else if ( pNBuf->status & ( RX_BD_NO | RX_BD_OV ) )
-                    {
-                        lwip_stats.link.err++;
-                    }
-                    else
-                    {
-                        lwip_stats.link.chkerr++;
-                    }
-#endif
-                }
-                else
-                {
-                    /* The frame must no be valid. Perform some checks to see if the FEC
-                     * driver is working correctly.
-                     */
-                    LWIP_ASSERT( "mcf523xfec_rx_task: pNBuf->length != 0", pNBuf->length != 0 );
-                    p = pbuf_alloc( PBUF_RAW, pNBuf->length, PBUF_POOL );
-                    if( p != NULL )
-                    {
-#if ETH_PAD_SIZE
-                        pbuf_header( p, -ETH_PAD_SIZE );
-#endif
-                        pPayLoad = pNBuf->data;
-                        for( q = p; q != NULL; q = q->next )
-                        {
-                            memcpy( q->payload, pPayLoad, q->len );
-                            pPayLoad += q->len;
-                        }
-#if ETH_PAD_SIZE
-                        pbuf_header( p, ETH_PAD_SIZE );
-#endif
-
-                        /* Ethernet frame received. Handling it is not device
-                         * dependent and therefore done in another function.
-                         */
-                        eth_input( fecif->netif, p );
-                    }
-                }
-                nbuf_rx_release( pNBuf );
-
-                /* Tell the HW that there are new free RX buffers. */
-                MCF_FEC_RDAR = 1;
-            }
-            else
-            {
-#if LINK_STATS
-                lwip_stats.link.memerr++;
-                lwip_stats.link.drop++;
-#endif
-            }
-        }
-        /* Set RX Debug PIN to low since handling of next frame is possible. */
-        FEC_DEBUG_RX_TIMING( 0 );
-    }
-    while( 1 );
-}
-
-void
-eth_input( struct netif *netif, struct pbuf *p )
-{
-    struct eth_hdr *eth_hdr = p->payload;
-
-    LWIP_ASSERT( "eth_input: p != NULL ", p != NULL );
-
-    switch ( htons( eth_hdr->type ) )
-    {
-    case ETHTYPE_IP:
-        /* Pass to ARP layer. */
-        etharp_ip_input( netif, p );
-
-        /* Skip Ethernet header. */
-        pbuf_header( p, ( s16_t ) - sizeof( struct eth_hdr ) );
-
-        /* Pass to network layer. */
-        netif->input( p, netif );
-        break;
-
-    case ETHTYPE_ARP:
-        /* Pass to ARP layer. */
-        etharp_arp_input( netif, ( struct eth_addr * )netif->hwaddr, p );
-        break;
-
-    default:
-        pbuf_free( p );
-        break;
-    }
-}
-
-void
-mcf523xfec_rx_irq( void )
-{
-    static portBASE_TYPE xNeedSwitch = pdFALSE;
-
-    /* Workaround GCC if frame pointers are enabled. This is an ISR and
-     * we must not modify the stack before portENTER_SWITCHING_ISR( )
-     * has been called. */
-#if _GCC_USES_FP == 1
-    asm volatile    ( "unlk %fp\n\t" );
-#endif
-
-    /* This ISR can cause a context switch, so the first statement must be
-     * a call to the portENTER_SWITCHING_ISR() macro.
-     */
-    portENTER_SWITCHING_ISR(  );
-
-    /* Set Debug PIN to high to measure RX latency. */
-    FEC_DEBUG_RX_TIMING( 1 );
-
-    /* Clear FEC RX Event from the Event Register (by writing 1) */
-    if( MCF_FEC_EIR & ( MCF_FEC_EIR_RXB | MCF_FEC_EIR_RXF ) )
-    {
-        /* Clear interrupt from EIR register immediately */
-        MCF_FEC_EIR = ( MCF_FEC_EIR_RXB | MCF_FEC_EIR_RXF );
-        xNeedSwitch = xSemaphoreGiveFromISR( fecif_g->rx_sem, pdFALSE );
-    }
-    portEXIT_SWITCHING_ISR( xNeedSwitch );
-}
-
-void
-mcf523xfec_reset( mcf523xfec_if_t * fecif )
-{
-    extern void     ( *__RAMVEC[] ) (  );
-
-    int             old_ipl = asm_set_ipl( 7 );
-
-    /* Reset the FEC - equivalent to a hard reset */
-    MCF_FEC_ECR = MCF_FEC_ECR_RESET;
-
-    /* Wait for the reset sequence to complete */
-    while( MCF_FEC_ECR & MCF_FEC_ECR_RESET );
-
-    /* Disable all FEC interrupts by clearing the EIMR register */
-    MCF_FEC_EIMR = 0;
-
-    /* Clear any interrupts by setting all bits in the EIR register */
-    MCF_FEC_EIR = 0xFFFFFFFFUL;
-
-    /* Configure Interrupt vectors. */
-    __RAMVEC[MCF_FEC_VEC_RXF] = mcf523xfec_rx_irq;
-
-    /* Set the source address for the controller */
-    MCF_FEC_PALR =
-        ( fecif->self->addr[0] << 24U ) | ( fecif->self->addr[1] << 16U ) |
-        ( fecif->self->addr[2] << 8U ) | ( fecif->self->addr[3] << 0U );
-    MCF_FEC_PAUR = ( fecif->self->addr[4] << 24U ) | ( fecif->self->addr[5] << 16U );
-
-    /* Initialize the hash table registers */
-    MCF_FEC_IAUR = 0;
-    MCF_FEC_IALR = 0;
-
-    /* Set Receive Buffer Size */
-#if RX_BUFFER_SIZE != 2048
-#error "RX_BUFFER_SIZE must be set to 2048 for safe FEC operation."
-#endif
-    MCF_FEC_EMRBR = RX_BUFFER_SIZE - 1;
-
-    /* Point to the start of the circular Rx buffer descriptor queue */
-    MCF_FEC_ERDSR = nbuf_get_start( NBUF_RX );
-
-    /* Point to the start of the circular Tx buffer descriptor queue */
-    MCF_FEC_ETDSR = nbuf_get_start( NBUF_TX );
-
-    /* Set the tranceiver interface to MII mode */
-    MCF_FEC_RCR = MCF_FEC_RCR_MAX_FL( MCF_FEC_MTU ) | MCF_FEC_RCR_MII_MODE;
-
-    /* Set MII Speed Control Register for 2.5Mhz */
-    MCF_FEC_MSCR = MCF_FEC_MSCR_MII_SPEED( FSYS_2 / ( 2UL * 2500000UL ) );
-
-    /* Only operate in half-duplex, no heart beat control */
-    MCF_FEC_TCR = 0;
-
-    /* Enable Debug support */
-    FEC_DEBUG_INIT;
-    FEC_DEBUG_RX_TIMING( 0 );
-    FEC_DEBUG_TX_TIMING( 0 );
-    ( void )asm_set_ipl( old_ipl );
-}
-
-void
-mcf523xfec_get_mac( mcf523xfec_if_t * hw, struct eth_addr *mac )
-{
-    int             i;
-    static const struct eth_addr mac_default = {
-        {0x00, 0xCF, 0x52, 0x35, 0x00, 0x01}
-    };
-
-    ( void )hw;
-
-    for( i = 0; i < ETH_ADDR_LEN; i++ )
-    {
-        mac->addr[i] = mac_default.addr[i];
-    }
-}
-
-void
-mcf523xfec_enable( mcf523xfec_if_t * fecif )
-{
-    ( void )fecif;
-
-    int             old_ipl = asm_set_ipl( 7 );
-
-    /* Configure I/O pins for the FEC. */
-    MCF_GPIO_PAR_FECI2C = ( MCF_GPIO_PAR_FECI2C_PAR_EMDC_FEC | MCF_GPIO_PAR_FECI2C_PAR_EMDIO_FEC );
-
-    /* Allow interrupts by setting IMR register */
-    MCF_FEC_EIMR = MCF_FEC_EIMR_RXF;
-
-    /* Configure the interrupt controller. */
-    MCF_INTC0_ICR27 = ( MCF_INTC0_ICRn_IL( MCF_FEC_INT_LEVEL ) |
-                        MCF_INTC0_ICRn_IP( MCF_FEC_INT_PRIORITY ) );
-    MCF_INTC0_IMRL &= ~( MCF_INTC0_IMRL_INT_MASK27 | MCF_INTC0_IMRL_MASKALL );
-
-    /* Enable FEC */
-    MCF_FEC_ECR = MCF_FEC_ECR_ETHER_EN;
-
-    /* Indicate that there have been empty receive buffers produced */
-    MCF_FEC_RDAR = 1;
-    ( void )asm_set_ipl( old_ipl );
-}
-
-void
-mcf523xfec_disable( mcf523xfec_if_t * fecif )
-{
-    ( void )fecif;
-
-    int             old_ipl = asm_set_ipl( 7 );
-
-    /* Set the Graceful Transmit Stop bit */
-    MCF_FEC_TCR = ( MCF_FEC_TCR | MCF_FEC_TCR_GTS );
-
-    /* Wait for the current transmission to complete */
-    while( !( MCF_FEC_EIR & MCF_FEC_EIR_GRA ) );
-
-    /* Clear the GRA event */
-    MCF_FEC_EIR = MCF_FEC_EIR_GRA;
-
-    /* Disable the FEC */
-    MCF_FEC_ECR = 0;
-
-    /* Disable all FEC interrupts by clearing the IMR register */
-    MCF_FEC_EIMR = 0;
-
-    /* Unconfigure the interrupt controller. */
-    MCF_INTC0_ICR27 = MCF_INTC0_ICRn_IL( 0 ) | MCF_INTC0_ICRn_IP( 0 );
-    MCF_INTC0_IMRL |= MCF_INTC0_IMRL_INT_MASK27;
-
-    /* Clear the GTS bit so frames can be tranmitted when restarted */
-    MCF_FEC_TCR = ( MCF_FEC_TCR & ~MCF_FEC_TCR_GTS );
-
-    /* Disable I/O pins used by the FEC. */
-    MCF_GPIO_PAR_FECI2C &= ~( MCF_GPIO_PAR_FECI2C_PAR_EMDC_FEC |
-                              MCF_GPIO_PAR_FECI2C_PAR_EMDIO_FEC );
-    ( void )asm_set_ipl( old_ipl );
-}
-
-err_t
-mcf523xfec_init( struct netif *netif )
-{
-    err_t           res;
-
-    mcf523xfec_if_t *fecif = mem_malloc( sizeof( mcf523xfec_if_t ) );
-
-    if( fecif != NULL )
-    {
-        /* Global copy used in ISR. */
-        fecif_g = fecif;
-        fecif->self = ( struct eth_addr * )&netif->hwaddr[0];
-        fecif->netif = netif;
-        fecif->tx_sem = NULL;
-        fecif->rx_sem = NULL;
-
-        if( ( fecif->tx_sem = sys_sem_new( 1 ) ) == NULL )
-        {
-            res = ERR_MEM;
-        }
-        else if( ( fecif->rx_sem = sys_sem_new( 0 ) ) == NULL )
-        {
-            res = ERR_MEM;
-        }
-        else if( sys_thread_new( mcf523xfec_rx_task, fecif, TASK_PRIORITY ) == NULL )
-        {
-            res = ERR_MEM;
-        }
-        else
-        {
-            netif->state = fecif;
-            netif->name[0] = 'C';
-            netif->name[1] = 'F';
-            netif->hwaddr_len = ETH_ADDR_LEN;
-            netif->mtu = MCF_FEC_MTU;
-            netif->flags = NETIF_FLAG_BROADCAST;
-            netif->output = mcf523xfec_output;
-            netif->linkoutput = mcf523xfec_output_raw;
-
-            nbuf_init(  );
-            mcf523xfec_get_mac( fecif, fecif->self );
-            mcf523xfec_reset( fecif );
-            mcf523xfec_enable( fecif );
-
-            etharp_init(  );
-            sys_timeout( ARP_TMR_INTERVAL, arp_timer, NULL );
-
-            res = ERR_OK;
-        }
-
-        if( res != ERR_OK )
-        {
-            free( fecif );
-            if( fecif->tx_sem != NULL )
-            {
-                mem_free( fecif->tx_sem );
-            }
-            if( fecif->rx_sem != NULL )
-            {
-                mem_free( fecif->rx_sem );
-            }
-        }
-    }
-    else
-    {
-        res = ERR_MEM;
-    }
-
-    return res;
-}
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/netif/fec.h b/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/netif/fec.h
deleted file mode 100644
index 5663f0343..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/netif/fec.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright (c) 2006 Christian Walter
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * Author: Christian Walter 
- *
- * File: $Id: fec.h,v 1.1 2006/08/29 00:04:06 wolti Exp $
- */
-
-#ifndef _FEC_H
-#define _FEC_H
-
-/* ------------------------ Defines --------------------------------------- */
-
-/* ------------------------ Prototypes ------------------------------------ */
-err_t           mcf523xfec_init( struct netif *netif );
-
-#endif
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/netif/nbuf.c b/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/netif/nbuf.c
deleted file mode 100644
index b4e70556a..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/netif/nbuf.c
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- * Network buffer code based on the MCF523x examples from Freescale.
- *
- * File: $Id: nbuf.c,v 1.2 2006/08/31 22:28:21 wolti Exp $
- */
-
-/* ------------------------ Platform includes ----------------------------- */
-#include "mcf5xxx.h"
-#include "mcf523x.h"
-
-#include "nbuf.h"
-
-/* ------------------------ Static variables ------------------------------ */
-
-/* Buffer descriptor indexes */
-static uint8    tx_bd_idx;
-static uint8    rx_bd_idx;
-
-/* Buffer Descriptors -- must be aligned on a 4-byte boundary but a
- * 16-byte boundary is recommended. */
-static nbuf_t   tx_nbuf[sizeof( nbuf_t ) * NUM_TXBDS] ATTR_FECMEM;
-static nbuf_t   rx_nbuf[sizeof( nbuf_t ) * NUM_RXBDS] ATTR_FECMEM;
-
-/* Data Buffers -- must be aligned on a 16-byte boundary. */
-static uint8    tx_buf[TX_BUFFER_SIZE * NUM_TXBDS] ATTR_FECMEM;
-static uint8    rx_buf[RX_BUFFER_SIZE * NUM_RXBDS] ATTR_FECMEM;
-
-/* ------------------------ Start implementation -------------------------- */
-void
-nbuf_init(  )
-{
-
-    uint8           i;
-
-    /* Initialize receive descriptor ring */
-    for( i = 0; i < NUM_RXBDS; i++ )
-    {
-        rx_nbuf[i].status = RX_BD_E;
-        rx_nbuf[i].length = 0;
-        rx_nbuf[i].data = &rx_buf[i * RX_BUFFER_SIZE];
-    }
-
-    /* Set the Wrap bit on the last one in the ring */
-    rx_nbuf[NUM_RXBDS - 1].status |= RX_BD_W;
-
-    /* Initialize transmit descriptor ring */
-    for( i = 0; i < NUM_TXBDS; i++ )
-    {
-        tx_nbuf[i].status = TX_BD_L | TX_BD_TC;
-        tx_nbuf[i].length = 0;
-        tx_nbuf[i].data = &tx_buf[i * TX_BUFFER_SIZE];
-    }
-
-    /* Set the Wrap bit on the last one in the ring */
-    tx_nbuf[NUM_TXBDS - 1].status |= TX_BD_W;
-
-    /* Initialize the buffer descriptor indexes */
-    tx_bd_idx = rx_bd_idx = 0;
-
-    return;
-}
-
-
-/********************************************************************/
-uint32
-nbuf_get_start( uint8 direction )
-{
-    /*
-     * Return the address of the first buffer descriptor in the ring.
-     * This routine is needed by the FEC of the MPC860T , MCF5282, and MCF523x
-     * in order to write the Rx/Tx descriptor ring start registers
-     */
-    switch ( direction )
-    {
-    case NBUF_RX:
-        return ( uint32 ) rx_nbuf;
-    case NBUF_TX:
-    default:
-        return ( uint32 ) tx_nbuf;
-    }
-}
-
-
-/********************************************************************/
-nbuf_t         *
-nbuf_rx_allocate(  )
-{
-    /* This routine alters shared data. Disable interrupts! */
-    int             old_ipl = asm_set_ipl( 6 );
-
-    /* Return a pointer to the next empty Rx Buffer Descriptor */
-    int             i = rx_bd_idx;
-
-
-    /* Check to see if the ring of BDs is full */
-    if( rx_nbuf[i].status & RX_BD_INUSE )
-        return NULL;
-
-    /* Mark the buffer as in use */
-    rx_nbuf[i].status |= RX_BD_INUSE;
-
-    /* increment the circular index */
-    rx_bd_idx = ( uint8 ) ( ( rx_bd_idx + 1 ) % NUM_RXBDS );
-
-    /* Restore previous IPL */
-    asm_set_ipl( old_ipl );
-
-    return &rx_nbuf[i];
-}
-
-
-/********************************************************************/
-nbuf_t         *
-nbuf_tx_allocate(  )
-{
-    /* This routine alters shared data. Disable interrupts! */
-    int             old_ipl = asm_set_ipl( 6 );
-
-    /* Return a pointer to the next empty Tx Buffer Descriptor */
-    int             i = tx_bd_idx;
-
-    /* Check to see if ring of BDs is full */
-    if( ( tx_nbuf[i].status & TX_BD_INUSE ) || ( tx_nbuf[i].status & TX_BD_R ) )
-        return NULL;
-
-    /* Mark the buffer as Ready (in use) */
-    /* FEC must set R bit in transmit routine */
-    tx_nbuf[i].status |= TX_BD_INUSE;
-
-    /* increment the circular index */
-    tx_bd_idx = ( uint8 ) ( ( tx_bd_idx + 1 ) % NUM_TXBDS );
-
-    /* Restore previous IPL */
-    asm_set_ipl( old_ipl );
-
-    return &tx_nbuf[i];
-}
-
-
-/********************************************************************/
-void
-nbuf_rx_release( nbuf_t * pNbuf )
-{
-    /* This routine alters shared data. Disable interrupts! */
-    int             old_ipl = asm_set_ipl( 6 );
-
-    /* Mark the buffer as empty and not in use */
-    pNbuf->status |= RX_BD_E;
-    pNbuf->status &= ~RX_BD_INUSE;
-
-    /* Restore previous IPL */
-    asm_set_ipl( old_ipl );
-}
-
-/********************************************************************/
-void
-nbuf_tx_release( nbuf_t * pNbuf )
-{
-    /* This routine alters shared data. Disable interrupts! */
-    int             old_ipl = asm_set_ipl( 6 );
-
-    /* Mark the buffer as not in use */
-    pNbuf->status &= ~TX_BD_INUSE;
-
-    /* Restore previous IPL */
-    asm_set_ipl( old_ipl );
-}
-
-/********************************************************************/
-int
-nbuf_rx_next_ready(  )
-{
-    /****************************************************************
- This function checks the EMPTY bit of the next Rx buffer to be
- allocated. If the EMPTY bit is cleared, then the next buffer in
- the ring has been filled by the FEC and has not already been
- allocated and passed up the stack. In this case, the next buffer
- in the ring is ready to be allocated. Otherwise, the  buffer is
- either empty or not empty but still in use by a higher level
- protocol. The FEC receive routine uses this function to determine
- if multiple buffers where filled by the FEC during a single
- interrupt event.
- ****************************************************************/
-
-    return ( !( rx_nbuf[rx_bd_idx].status & RX_BD_E ) );
-}
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/netif/nbuf.h b/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/netif/nbuf.h
deleted file mode 100644
index ecbc70a23..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/netif/nbuf.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * Network buffer code based on the MCF523x examples from Freescale.
- *
- * Freescale explicitly grants the redistribution and modification
- * of these source files. The complete licensing information is
- * available in the file LICENSE_FREESCALE.TXT.
- *
- * Modifications Copyright (c) 2006 Christian Walter 
- *
- * File: $Id: nbuf.h,v 1.3 2006/09/24 22:50:23 wolti Exp $
- */
-
-#ifndef _NBUF_H
-#define _NBUF_H
-
-/* ------------------------ Defines --------------------------------------- */
-
-#ifdef __GNUC__
-#define ATTR_FECMEM             \
-    __attribute__((section(".nbuf"),aligned(16)))
-#endif
-
-#define NBUF_RX                 ( 1 )
-#define NBUF_TX                 ( 0 )
-
-/* We set the receiver buffers to the maximum size the FEC supports ( See
- * MCF5235 reference manual 19.2.5.1.2 - Driver/DMA Operation with Receive
- * BDs). This gives us the benefit that any frame fits into one buffer. A
- * maximum size of 2047 is guaranteed by the FEC and 2048 is therefore a
- * safe value.
- * Note: The value MUST be dividable by 16!
- */
-#define RX_BUFFER_SIZE          ( 2048 )
-
-/* Size of the transmit buffers. If you set this value to small all frames
- * greater than this size will be dropped. The value 1520 was choosen because
- * it is bigger than the FEC MTU (1518) and is dividable by 16.
- * Note: The value MUST be dividable by 16! */
-#define TX_BUFFER_SIZE          ( 1520 )
-
-/* Number of Receive and Transmit Buffers and Buffer Descriptors */
-#define NUM_RXBDS               ( 2 )
-#define NUM_TXBDS               ( 2 )
-
-/* ------------------------ Defines ( Buffer Descriptor Flags )------------ */
-
-#define TX_BD_R                 ( 0x8000 )
-#define TX_BD_INUSE             ( 0x4000 )
-#define TX_BD_TO1               ( 0x4000 )
-#define TX_BD_W                 ( 0x2000 )
-#define TX_BD_TO2               ( 0x1000 )
-#define TX_BD_L                 ( 0x0800 )
-#define TX_BD_TC                ( 0x0400 )
-#define TX_BD_DEF               ( 0x0200 )
-#define TX_BD_HB                ( 0x0100 )
-#define TX_BD_LC                ( 0x0080 )
-#define TX_BD_RL                ( 0x0040 )
-#define TX_BD_UN                ( 0x0002 )
-#define TX_BD_CSL               ( 0x0001 )
-
-#define RX_BD_E                 ( 0x8000 )
-#define RX_BD_INUSE             ( 0x4000 )
-#define RX_BD_R01               ( 0x4000 )
-#define RX_BD_W                 ( 0x2000 )
-#define RX_BD_R02               ( 0x1000 )
-#define RX_BD_L                 ( 0x0800 )
-#define RX_BD_M                 ( 0x0100 )
-#define RX_BD_BC                ( 0x0080 )
-#define RX_BD_MC                ( 0x0040 )
-#define RX_BD_LG                ( 0x0020 )
-#define RX_BD_NO                ( 0x0010 )
-#define RX_BD_SH                ( 0x0008 )
-#define RX_BD_CR                ( 0x0004 )
-#define RX_BD_OV                ( 0x0002 )
-#define RX_BD_TR                ( 0x0001 )
-
-/* ------------------------ Type definitions ------------------------------ */
-typedef struct
-{
-    uint16          status;     /* control and status */
-    uint16          length;     /* transfer length */
-    uint8          *data;       /* buffer address */
-} nbuf_t;
-
-/* ------------------------ Prototypes ------------------------------------ */
-
-void            nbuf_init( void );
-uint32          nbuf_get_start( uint8 );
-nbuf_t         *nbuf_rx_allocate( void );
-nbuf_t         *nbuf_tx_allocate( void );
-void            nbuf_rx_release( nbuf_t * );
-void            nbuf_tx_release( nbuf_t * );
-int             nbuf_rx_next_ready( void );
-
-#endif
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/sys_arch.c b/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/sys_arch.c
deleted file mode 100644
index dc46d5a31..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/contrib/port/FreeRTOS/MCF5235/sys_arch.c
+++ /dev/null
@@ -1,561 +0,0 @@
-/*
- * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
- * Modifications Copyright (c) 2006 Christian Walter 
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels 
- * Modifcations: Christian Walter 
- *
- * $Id: sys_arch.c,v 1.6 2006/09/24 22:04:53 wolti Exp $
- */
-
-/* ------------------------ System includes ------------------------------- */
-#include 
-#include 
-#include 
-#include 
-
-/* ------------------------ FreeRTOS includes ----------------------------- */
-#include "FreeRTOS.h"
-#include "task.h"
-#include "semphr.h"
-
-/* ------------------------ lwIP includes --------------------------------- */
-#include "lwip/debug.h"
-#include "lwip/def.h"
-#include "lwip/sys.h"
-#include "lwip/mem.h"
-#include "lwip/sio.h"
-#include "lwip/stats.h"
-
-/* ------------------------ Project includes ------------------------------ */
-
-/* ------------------------ Defines --------------------------------------- */
-/* This is the number of threads that can be started with sys_thead_new() */
-#define SYS_MBOX_SIZE               ( 16 )
-#define MS_TO_TICKS( ms )           \
-    ( portTickType )( ( portTickType ) ( ms ) / portTICK_RATE_MS )
-#define TICKS_TO_MS( ticks )        \
-    ( unsigned portLONG )( ( portTickType ) ( ticks ) * portTICK_RATE_MS )
-#define THREAD_STACK_SIZE           ( 1024 )
-#define THREAD_NAME                 "lwIP"
-
-#define THREAD_INIT( tcb ) \
-    do { \
-        tcb->next = NULL; \
-        tcb->pid = ( xTaskHandle )0; \
-        tcb->timeouts.next = NULL; \
-    } while( 0 )
-
-/* ------------------------ Type definitions ------------------------------ */
-typedef struct sys_tcb
-{
-    struct sys_tcb *next;
-    struct sys_timeouts timeouts;
-    xTaskHandle     pid;
-} sys_tcb_t;
-
-/* ------------------------ Prototypes ------------------------------------ */
-
-/* ------------------------ Static functions ------------------------------ */
-sys_tcb_t      *sys_thread_current( void );
-
-/* ------------------------ Static variables ------------------------------ */
-static sys_tcb_t *tasks = NULL;
-
-/* ------------------------ Start implementation -------------------------- */
-void
-sys_init( void )
-{
-    LWIP_ASSERT( "sys_init: not called first", tasks == NULL );
-    tasks = NULL;
-}
-
-/*
- * This optional function does a "fast" critical region protection and returns
- * the previous protection level. This function is only called during very short
- * critical regions. An embedded system which supports ISR-based drivers might
- * want to implement this function by disabling interrupts. Task-based systems
- * might want to implement this by using a mutex or disabling tasking. This
- * function should support recursive calls from the same task or interrupt. In
- * other words, sys_arch_protect() could be called while already protected. In
- * that case the return value indicates that it is already protected.
- *
- * sys_arch_protect() is only required if your port is supporting an operating
- * system.
- */
-sys_prot_t
-sys_arch_protect( void )
-{
-    vPortEnterCritical(  );
-    return 1;
-}
-
-/*
- * This optional function does a "fast" set of critical region protection to the
- * value specified by pval. See the documentation for sys_arch_protect() for
- * more information. This function is only required if your port is supporting
- * an operating system.
- */
-void
-sys_arch_unprotect( sys_prot_t pval )
-{
-    ( void )pval;
-    vPortExitCritical(  );
-}
-
-/*
- * Prints an assertion messages and aborts execution.
- */
-void
-sys_assert( const char *msg )
-{
-	fputs( msg, stderr );
-	fputs( "\n\r", stderr );
-    vPortEnterCritical(  );
-    for( ;; );
-}
-
-void
-sys_debug( const char *const fmt, ... )
-{
-    va_list         ap;
-
-    va_start( ap, fmt );
-    ( void )vprintf( fmt, ap );
-    ( void )putchar( '\r' );
-    va_end( ap );
-}
-
-/* ------------------------ Start implementation ( Threads ) -------------- */
-
-sys_thread_t
-sys_thread_new( void ( *thread ) ( void *arg ), void *arg, int prio )
-{
-    return sys_arch_thread_new( thread, arg, prio, THREAD_STACK_SIZE );
-}
-
-/*
- * Starts a new thread with priority "prio" that will begin its execution in the
- * function "thread()". The "arg" argument will be passed as an argument to the
- * thread() function. The argument "ssize" is the requested stack size for the
- * new thread. The id of the new thread is returned. Both the id and the
-  * priority are system dependent.
- */
-sys_thread_t
-sys_arch_thread_new( void ( *thread ) ( void *arg ), void *arg, int prio, size_t ssize )
-{
-    sys_thread_t    thread_hdl = SYS_THREAD_NULL;
-    int             i;
-    sys_tcb_t      *p;
-    char            thread_name[ configMAX_TASK_NAME_LEN ];
-
-    /* We disable the FreeRTOS scheduler because it might be the case that the new
-     * tasks gets scheduled inside the xTaskCreate function. To prevent this we
-     * disable the scheduling. Note that this can happen although we have interrupts
-     * disabled because xTaskCreate contains a call to taskYIELD( ).
-     */
-    vPortEnterCritical(  );
-
-    p = tasks;
-    i = 0;
-    /* We are called the first time. Initialize it. */
-    if( p == NULL )
-    {
-        p = pvPortMalloc( sizeof( sys_tcb_t ) );
-        if( p != NULL )
-        {
-            tasks = p;
-        }
-    }
-    else
-    {
-        /* First task already counter. */
-        i++;
-        /* Cycle to the end of the list. */
-        while( p->next != NULL )
-        {
-            i++;
-            p = p->next;
-        }
-        p->next = pvPortMalloc( sizeof( sys_tcb_t ) );
-        p = p->next;
-    }
-
-    if( p != NULL )
-    {
-        /* Memory allocated. Initialize the data structure. */
-        THREAD_INIT( p );
-        ( void )snprintf( thread_name, configMAX_TASK_NAME_LEN, "lwIP%d", i );
-
-        /* Now q points to a free element in the list. */
-        if( xTaskCreate( thread, thread_name, ssize, arg, prio, &p->pid ) == pdPASS )
-        {
-            thread_hdl = p;
-        }
-        else
-        {
-            vPortFree( p );
-        }
-    }
-
-    vPortExitCritical(  );
-    return thread_hdl;
-}
-
-void
-sys_arch_thread_remove( sys_thread_t hdl )
-{
-    sys_tcb_t      *current = tasks, *prev;
-    sys_tcb_t      *toremove = hdl;
-    xTaskHandle     pid = ( xTaskHandle ) 0;
-
-    LWIP_ASSERT( "sys_arch_thread_remove: assertion hdl != NULL failed!", hdl != NULL );
-
-    /* If we have to remove the first task we must update the global "tasks"
-     * variable. */
-    vPortEnterCritical(  );
-    if( hdl != NULL )
-    {
-        prev = NULL;
-        while( ( current != NULL ) && ( current != toremove ) )
-        {
-            prev = current;
-            current = current->next;
-        }
-        /* Found it. */
-        if( current == toremove )
-        {
-            /* Not the first entry in the list. */
-            if( prev != NULL )
-            {
-                prev->next = toremove->next;
-            }
-            else
-            {
-                tasks = toremove->next;
-            }
-            LWIP_ASSERT( "sys_arch_thread_remove: can't remove thread with timeouts!",
-                         toremove->timeouts.next == NULL );
-            pid = toremove->pid;
-            THREAD_INIT( toremove );
-            vPortFree( toremove );
-        }
-    }
-    /* We are done with accessing the shared datastructure. Release the 
-     * resources.
-     */
-    vPortExitCritical(  );
-    if( pid != ( xTaskHandle ) 0 )
-    {
-        vTaskDelete( pid );
-        /* not reached. */
-    }
-}
-
-/*
- * Returns the thread control block for the currently active task. In case
- * of an error the functions returns NULL.
- */
-sys_thread_t
-sys_arch_thread_current( void )
-{
-    sys_tcb_t      *p = tasks;
-    xTaskHandle     pid = xTaskGetCurrentTaskHandle(  );
-
-    vPortEnterCritical(  );
-    while( ( p != NULL ) && ( p->pid != pid ) )
-    {
-        p = p->next;
-    }
-    vPortExitCritical(  );
-    return p;
-}
-
-/*
- * Returns a pointer to the per-thread sys_timeouts structure. In lwIP,
- * each thread has a list of timeouts which is represented as a linked
- * list of sys_timeout structures. The sys_timeouts structure holds a
- * pointer to a linked list of timeouts. This function is called by
- * the lwIP timeout scheduler and must not return a NULL value.
- *
- * In a single threaded sys_arch implementation, this function will
- * simply return a pointer to a global sys_timeouts variable stored in
- * the sys_arch module.
- */
-struct sys_timeouts *
-sys_arch_timeouts( void )
-{
-    sys_tcb_t      *ptask;
-
-    ptask = sys_arch_thread_current(  );
-    LWIP_ASSERT( "sys_arch_timeouts: ptask != NULL", ptask != NULL );
-    return ptask != NULL ? &( ptask->timeouts ) : NULL;
-}
-
-/* ------------------------ Start implementation ( Semaphores ) ----------- */
-
-/* Creates and returns a new semaphore. The "count" argument specifies
- * the initial state of the semaphore.
- */
-sys_sem_t
-sys_sem_new( u8_t count )
-{
-    xSemaphoreHandle xSemaphore;
-
-    vSemaphoreCreateBinary( xSemaphore );
-    if( xSemaphore != SYS_SEM_NULL )
-    {
-        if( count == 0 )
-        {
-            xSemaphoreTake( xSemaphore, 1 );
-        }
-#ifdef SYS_STATS
-        vPortEnterCritical(  );
-        lwip_stats.sys.sem.used++;
-        if( lwip_stats.sys.sem.used > lwip_stats.sys.sem.max )
-        {
-            lwip_stats.sys.sem.max = lwip_stats.sys.sem.used;
-        }
-        vPortExitCritical(  );
-#endif
-    }
-    else
-    {
-        LWIP_ASSERT( "sys_sem_new: xSemaphore == SYS_SEM_NULL", xSemaphore != SYS_SEM_NULL );
-    }
-
-    return xSemaphore;
-}
-
-/* Deallocates a semaphore */
-void
-sys_sem_free( sys_sem_t sem )
-{
-    LWIP_ASSERT( "sys_sem_free: sem != SYS_SEM_NULL", sem != SYS_SEM_NULL );
-    if( sem != SYS_SEM_NULL )
-    {
-#ifdef SYS_STATS
-        vPortEnterCritical(  );
-        lwip_stats.sys.sem.used--;
-        vPortExitCritical(  );
-#endif
-        vQueueDelete( sem );
-    }
-}
-
-/* Signals a semaphore */
-void
-sys_sem_signal( sys_sem_t sem )
-{
-    LWIP_ASSERT( "sys_sem_signal: sem != SYS_SEM_NULL", sem != SYS_SEM_NULL );
-    xSemaphoreGive( sem );
-}
-
-/*
- * Blocks the thread while waiting for the semaphore to be
- * signaled. If the "timeout" argument is non-zero, the thread should
- * only be blocked for the specified time (measured in
- * milliseconds).
- *
- * If the timeout argument is non-zero, the return value is the number of
- * milliseconds spent waiting for the semaphore to be signaled. If the
- * semaphore wasn't signaled within the specified time, the return value is
- * SYS_ARCH_TIMEOUT. If the thread didn't have to wait for the semaphore
- * (i.e., it was already signaled), the function may return zero.
- *
- * Notice that lwIP implements a function with a similar name,
- * sys_sem_wait(), that uses the sys_arch_sem_wait() function.
- */
-u32_t
-sys_arch_sem_wait( sys_sem_t sem, u32_t timeout )
-{
-    portBASE_TYPE   xStatus;
-    portTickType    xTicksStart, xTicksEnd, xTicksElapsed;
-    u32_t           timespent;
-
-    LWIP_ASSERT( "sys_arch_sem_wait: sem != SYS_SEM_NULL", sem != SYS_SEM_NULL );
-    xTicksStart = xTaskGetTickCount(  );
-    if( timeout == 0 )
-    {
-        do
-        {
-            xStatus = xSemaphoreTake( sem, MS_TO_TICKS( 100 ) );
-        }
-        while( xStatus != pdTRUE );
-    }
-    else
-    {
-        xStatus = xSemaphoreTake( sem, MS_TO_TICKS( timeout ) );
-    }
-
-    /* Semaphore was signaled. */
-    if( xStatus == pdTRUE )
-    {
-        xTicksEnd = xTaskGetTickCount(  );
-        xTicksElapsed = xTicksEnd - xTicksStart;
-        timespent = TICKS_TO_MS( xTicksElapsed );
-    }
-    else
-    {
-        timespent = SYS_ARCH_TIMEOUT;
-    }
-    return timespent;
-}
-
-
-/* ------------------------ Start implementation ( Mailboxes ) ------------ */
-
-/* Creates an empty mailbox. */
-sys_mbox_t
-sys_mbox_new( void )
-{
-    xQueueHandle    mbox;
-
-    mbox = xQueueCreate( SYS_MBOX_SIZE, sizeof( void * ) );
-    if( mbox != SYS_MBOX_NULL )
-    {
-#ifdef SYS_STATS
-        vPortEnterCritical(  );
-        lwip_stats.sys.mbox.used++;
-        if( lwip_stats.sys.mbox.used > lwip_stats.sys.mbox.max )
-        {
-            lwip_stats.sys.mbox.max = lwip_stats.sys.mbox.used;
-        }
-        vPortExitCritical(  );
-#endif
-    }
-    return mbox;
-}
-
-/*
-  Deallocates a mailbox. If there are messages still present in the
-  mailbox when the mailbox is deallocated, it is an indication of a
-  programming error in lwIP and the developer should be notified.
-*/
-void
-sys_mbox_free( sys_mbox_t mbox )
-{
-    void           *msg;
-
-    LWIP_ASSERT( "sys_mbox_free: mbox != SYS_MBOX_NULL", mbox != SYS_MBOX_NULL );
-    if( mbox != SYS_MBOX_NULL )
-    {
-        while( uxQueueMessagesWaiting( mbox ) != 0 )
-        {
-            if( sys_arch_mbox_fetch( mbox, &msg, 1 ) != SYS_ARCH_TIMEOUT )
-            {
-                LWIP_ASSERT( "sys_mbox_free: memory leak (msg != NULL)", msg == NULL );
-            }
-        }
-        vQueueDelete( mbox );
-#ifdef SYS_STATS
-        vPortEnterCritical(  );
-        lwip_stats.sys.mbox.used--;
-        vPortExitCritical(  );
-#endif
-    }
-}
-
-/*
- * This function sends a message to a mailbox. It is unusual in that no error
- * return is made. This is because the caller is responsible for ensuring that
- * the mailbox queue will not fail. The caller does this by limiting the number
- * of msg structures which exist for a given mailbox.
- */
-void
-sys_mbox_post( sys_mbox_t mbox, void *data )
-{
-    portBASE_TYPE   xQueueSent;
-
-    /* Queue must not be full - Otherwise it is an error. */
-    xQueueSent = xQueueSend( mbox, &data, 0 );
-    LWIP_ASSERT( "sys_mbox_post: xQueueSent == pdPASS", xQueueSent == pdPASS );
-}
-
-/*
- * Blocks the thread until a message arrives in the mailbox, but does
- * not block the thread longer than "timeout" milliseconds (similar to
- * the sys_arch_sem_wait() function). The "msg" argument is a result
- * parameter that is set by the function (i.e., by doing "*msg =
- * ptr"). The "msg" parameter maybe NULL to indicate that the message
- * should be dropped.
- *
- * Note that a function with a similar name, sys_mbox_fetch(), is
- * implemented by lwIP.
- */
-u32_t
-sys_arch_mbox_fetch( sys_mbox_t mbox, void **msg, u32_t timeout )
-{
-    void           *ret_msg;
-    portBASE_TYPE   xStatus;
-    portTickType    xTicksStart, xTicksEnd, xTicksElapsed;
-    u32_t           timespent;
-
-    LWIP_ASSERT( "sys_arch_mbox_fetch: mbox != SYS_MBOX_NULL", mbox != SYS_MBOX_NULL );
-    xTicksStart = xTaskGetTickCount(  );
-    if( timeout == 0 )
-    {
-        do
-        {
-            xStatus = xQueueReceive( mbox, &ret_msg, MS_TO_TICKS( 100 ) );
-        }
-        while( xStatus != pdTRUE );
-    }
-    else
-    {
-        xStatus = xQueueReceive( mbox, &ret_msg, MS_TO_TICKS( timeout ) );
-    }
-
-    if( xStatus == pdTRUE )
-    {
-        if( msg )
-        {
-            *msg = ret_msg;
-        }
-        xTicksEnd = xTaskGetTickCount(  );
-        xTicksElapsed = xTicksEnd - xTicksStart;
-        timespent = TICKS_TO_MS( xTicksElapsed );
-    }
-    else
-    {
-        if( msg )
-        {
-            *msg = NULL;
-        }
-        timespent = SYS_ARCH_TIMEOUT;
-    }
-    return timespent;
-}
-
-u32_t
-sys_jiffies( void )
-{
-    portTickType    xTicks = xTaskGetTickCount(  );
-
-    return ( u32_t )TICKS_TO_MS( xTicks );
-}
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/doc/contrib.txt b/Demo/lwIP_MCF5235_GCC/lwip/doc/contrib.txt
deleted file mode 100644
index 7c99b9be2..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/doc/contrib.txt
+++ /dev/null
@@ -1,62 +0,0 @@
-1 Introduction
-
-This document describes some guidelines for people participating
-in lwIP development.
-
-2 How to contribute to lwIP
-
-Here is a short list of suggestions to anybody working with lwIP and 
-trying to contribute bug reports, fixes, enhancements, platform ports etc.
-First of all as you may already know lwIP is a volunteer project so feedback
-to fixes or questions might often come late. Hopefully the bug and patch tracking 
-features of Savannah help us not lose users' input.
-
-2.1 Source code style:
-
-1. do not use tabs.
-2. indentation is two spaces per level (i.e. per tab).
-3. end debug messages with a trailing newline (\n).
-4. one space between keyword and opening bracket.
-5. no space between function and opening bracket.
-6. one space and no newline before opening curly braces of a block.
-7. closing curly brace on a single line.
-8. spaces surrounding assignment and comparisons.
-9. use current source code style as further reference.
-
-2.2 Source code documentation style:
-
-1. JavaDoc compliant and Doxygen compatible.
-2. Function documentation above functions in .c files, not .h files.
-   (This forces you to synchronize documentation and implementation.)
-3. Use current documentation style as further reference.
- 
-2.3 Bug reports and patches:
-
-1. Make sure you are reporting bugs or send patches against the latest
-   sources. (From the latest release and/or the current CVS sources.)
-2. If you think you found a bug make sure it's not already filed in the
-   bugtracker at Savannah.
-3. If you have a fix put the patch on Savannah. If it is a patch that affects
-   both core and arch specific stuff please separate them so that the core can
-   be applied separately while leaving the other patch 'open'. The prefered way
-   is to NOT touch archs you can't test and let maintainers take care of them.
-   This is a good way to see if they are used at all - the same goes for unix
-   netifs except tapif.
-4. Do not file a bug and post a fix to it to the patch area. Either a bug report
-   or a patch will be enough.
-   If you correct an existing bug then attach the patch to the bug rather than creating a new entry in the patch area.
-5. Trivial patches (compiler warning, indentation and spelling fixes or anything obvious which takes a line or two)
-   can go to the lwip-users list. This is still the fastest way of interaction and the list is not so crowded
-   as to allow for loss of fixes. Putting bugs on Savannah and subsequently closing them is too much an overhead
-   for reporting a compiler warning fix.
-6. Patches should be specific to a single change or to related changes.Do not mix bugfixes with spelling and other
-   trivial fixes unless the bugfix is trivial too.Do not reorganize code and rename identifiers in the same patch you
-   change behaviour if not necessary.A patch is easier to read and understand if it's to the point and short than
-   if it's not to the point and long :) so the chances for it to be applied are greater. 
-
-2.4 Platform porters:
-
-1. If you have ported lwIP to a platform (an OS, a uC/processor or a combination of these) and
-   you think it could benefit others[1] you might want discuss this on the mailing list. You
-   can also ask for CVS access to submit and maintain your port in the contrib CVS module.
-   
\ No newline at end of file
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/doc/rawapi.txt b/Demo/lwIP_MCF5235_GCC/lwip/doc/rawapi.txt
deleted file mode 100644
index f84e0d2eb..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/doc/rawapi.txt
+++ /dev/null
@@ -1,386 +0,0 @@
-Raw TCP/IP interface for lwIP
-
-Authors: Adam Dunkels, Leon Woestenberg, Christiaan Simons
-
-lwIP provides two Application Program's Interfaces (APIs) for programs
-to use for communication with the TCP/IP code:
-* low-level "core" / "callback" or "raw" API.
-* higher-level "sequential" API.
-
-The sequential API provides a way for ordinary, sequential, programs
-to use the lwIP stack. It is quite similar to the BSD socket API. The
-model of execution is based on the blocking open-read-write-close
-paradigm. Since the TCP/IP stack is event based by nature, the TCP/IP
-code and the application program must reside in different execution
-contexts (threads).
-
-** The remainder of this document discusses the "raw" API. **
-
-The raw TCP/IP interface allows the application program to integrate
-better with the TCP/IP code. Program execution is event based by
-having callback functions being called from within the TCP/IP
-code. The TCP/IP code and the application program both run in the same
-thread. The sequential API has a much higher overhead and is not very
-well suited for small systems since it forces a multithreaded paradigm
-on the application.
-
-The raw TCP/IP interface is not only faster in terms of code execution
-time but is also less memory intensive. The drawback is that program
-development is somewhat harder and application programs written for
-the raw TCP/IP interface are more difficult to understand. Still, this
-is the preferred way of writing applications that should be small in
-code size and memory usage.
-
-Both APIs can be used simultaneously by different application
-programs. In fact, the sequential API is implemented as an application
-program using the raw TCP/IP interface.
-
---- Callbacks
-
-Program execution is driven by callbacks. Each callback is an ordinary
-C function that is called from within the TCP/IP code. Every callback
-function is passed the current TCP or UDP connection state as an
-argument. Also, in order to be able to keep program specific state,
-the callback functions are called with a program specified argument
-that is independent of the TCP/IP state.
-
-The function for setting the application connection state is:
-
-- void tcp_arg(struct tcp_pcb *pcb, void *arg)
-
-  Specifies the program specific state that should be passed to all
-  other callback functions. The "pcb" argument is the current TCP
-  connection control block, and the "arg" argument is the argument
-  that will be passed to the callbacks.
-
-  
---- TCP connection setup
-
-The functions used for setting up connections is similar to that of
-the sequential API and of the BSD socket API. A new TCP connection
-identifier (i.e., a protocol control block - PCB) is created with the
-tcp_new() function. This PCB can then be either set to listen for new
-incoming connections or be explicitly connected to another host.
-
-- struct tcp_pcb *tcp_new(void)
-
-  Creates a new connection identifier (PCB). If memory is not
-  available for creating the new pcb, NULL is returned.
-
-- err_t tcp_bind(struct tcp_pcb *pcb, struct ip_addr *ipaddr,
-                 u16_t port)
-
-  Binds the pcb to a local IP address and port number. The IP address
-  can be specified as IP_ADDR_ANY in order to bind the connection to
-  all local IP addresses.
-
-  If another connection is bound to the same port, the function will
-  return ERR_USE, otherwise ERR_OK is returned.
-
-- struct tcp_pcb *tcp_listen(struct tcp_pcb *pcb)
-
-  Commands a pcb to start listening for incoming connections. When an
-  incoming connection is accepted, the function specified with the
-  tcp_accept() function will be called. The pcb will have to be bound
-  to a local port with the tcp_bind() function.
-
-  The tcp_listen() function returns a new connection identifier, and
-  the one passed as an argument to the function will be
-  deallocated. The reason for this behavior is that less memory is
-  needed for a connection that is listening, so tcp_listen() will
-  reclaim the memory needed for the original connection and allocate a
-  new smaller memory block for the listening connection.
-
-  tcp_listen() may return NULL if no memory was available for the
-  listening connection. If so, the memory associated with the pcb
-  passed as an argument to tcp_listen() will not be deallocated.
-
-- void tcp_accept(struct tcp_pcb *pcb,
-                  err_t (* accept)(void *arg, struct tcp_pcb *newpcb,
-                                   err_t err))
-
-  Specified the callback function that should be called when a new
-  connection arrives on a listening connection.
-      
-- err_t tcp_connect(struct tcp_pcb *pcb, struct ip_addr *ipaddr,
-                    u16_t port, err_t (* connected)(void *arg,
-                                                    struct tcp_pcb *tpcb,
-                                                    err_t err));
-
-  Sets up the pcb to connect to the remote host and sends the
-  initial SYN segment which opens the connection. 
-
-  The tcp_connect() function returns immediately; it does not wait for
-  the connection to be properly setup. Instead, it will call the
-  function specified as the fourth argument (the "connected" argument)
-  when the connection is established. If the connection could not be
-  properly established, either because the other host refused the
-  connection or because the other host didn't answer, the "connected"
-  function will be called with an the "err" argument set accordingly.
-
-  The tcp_connect() function can return ERR_MEM if no memory is
-  available for enqueueing the SYN segment. If the SYN indeed was
-  enqueued successfully, the tcp_connect() function returns ERR_OK.
-
-  
---- Sending TCP data
-
-TCP data is sent by enqueueing the data with a call to
-tcp_write(). When the data is successfully transmitted to the remote
-host, the application will be notified with a call to a specified
-callback function.
-
-- err_t tcp_write(struct tcp_pcb *pcb, void *dataptr, u16_t len,
-                  u8_t copy)
-
-  Enqueues the data pointed to by the argument dataptr. The length of
-  the data is passed as the len parameter. The copy argument is either
-  0 or 1 and indicates whether the new memory should be allocated for
-  the data to be copied into. If the argument is 0, no new memory
-  should be allocated and the data should only be referenced by
-  pointer.
-
-  The tcp_write() function will fail and return ERR_MEM if the length
-  of the data exceeds the current send buffer size or if the length of
-  the queue of outgoing segment is larger than the upper limit defined
-  in lwipopts.h. The number of bytes available in the output queue can
-  be retrieved with the tcp_sndbuf() function.
-
-  The proper way to use this function is to call the function with at
-  most tcp_sndbuf() bytes of data. If the function returns ERR_MEM,
-  the application should wait until some of the currently enqueued
-  data has been successfully received by the other host and try again.
-
-- void tcp_sent(struct tcp_pcb *pcb,
-                err_t (* sent)(void *arg, struct tcp_pcb *tpcb,
-		               u16_t len))
-
-  Specifies the callback function that should be called when data has
-  successfully been received (i.e., acknowledged) by the remote
-  host. The len argument passed to the callback function gives the
-  amount bytes that was acknowledged by the last acknowledgment.
-
-  
---- Receiving TCP data
-
-TCP data reception is callback based - an application specified
-callback function is called when new data arrives. When the
-application has taken the data, it has to call the tcp_recved()
-function to indicate that TCP can advertise increase the receive
-window.
-
-- void tcp_recv(struct tcp_pcb *pcb,
-                err_t (* recv)(void *arg, struct tcp_pcb *tpcb,
-                               struct pbuf *p, err_t err))
-
-  Sets the callback function that will be called when new data
-  arrives. The callback function will be passed a NULL pbuf to
-  indicate that the remote host has closed the connection.
-
-- void tcp_recved(struct tcp_pcb *pcb, u16_t len)
-
-  Must be called when the application has received the data. The len
-  argument indicates the length of the received data.
-    
-
---- Application polling
-
-When a connection is idle (i.e., no data is either transmitted or
-received), lwIP will repeatedly poll the application by calling a
-specified callback function. This can be used either as a watchdog
-timer for killing connections that have stayed idle for too long, or
-as a method of waiting for memory to become available. For instance,
-if a call to tcp_write() has failed because memory wasn't available,
-the application may use the polling functionality to call tcp_write()
-again when the connection has been idle for a while.
-
-- void tcp_poll(struct tcp_pcb *pcb, u8_t interval,
-                err_t (* poll)(void *arg, struct tcp_pcb *tpcb))
-
-  Specifies the polling interval and the callback function that should
-  be called to poll the application. The interval is specified in
-  number of TCP coarse grained timer shots, which typically occurs
-  twice a second. An interval of 10 means that the application would
-  be polled every 5 seconds.
-
-
---- Closing and aborting connections
-
-- err_t tcp_close(struct tcp_pcb *pcb)
-
-  Closes the connection. The function may return ERR_MEM if no memory
-  was available for closing the connection. If so, the application
-  should wait and try again either by using the acknowledgment
-  callback or the polling functionality. If the close succeeds, the
-  function returns ERR_OK.
-
-  The pcb is deallocated by the TCP code after a call to tcp_close(). 
-
-- void tcp_abort(struct tcp_pcb *pcb)
-
-  Aborts the connection by sending a RST (reset) segment to the remote
-  host. The pcb is deallocated. This function never fails.
-
-If a connection is aborted because of an error, the application is
-alerted of this event by the err callback. Errors that might abort a
-connection are when there is a shortage of memory. The callback
-function to be called is set using the tcp_err() function.
-
-- void tcp_err(struct tcp_pcb *pcb, void (* err)(void *arg,
-	       err_t err))
-
-  The error callback function does not get the pcb passed to it as a
-  parameter since the pcb may already have been deallocated.
-
-
---- Lower layer TCP interface
-
-TCP provides a simple interface to the lower layers of the
-system. During system initialization, the function tcp_init() has
-to be called before any other TCP function is called. When the system
-is running, the two timer functions tcp_fasttmr() and tcp_slowtmr()
-must be called with regular intervals. The tcp_fasttmr() should be
-called every TCP_FAST_INTERVAL milliseconds (defined in tcp.h) and
-tcp_slowtmr() should be called every TCP_SLOW_INTERVAL milliseconds. 
-
-
---- UDP interface
-
-The UDP interface is similar to that of TCP, but due to the lower
-level of complexity of UDP, the interface is significantly simpler.
-
-- struct udp_pcb *udp_new(void)
-
-  Creates a new UDP pcb which can be used for UDP communication. The
-  pcb is not active until it has either been bound to a local address
-  or connected to a remote address.
-
-- void udp_remove(struct udp_pcb *pcb)
-
-  Removes and deallocates the pcb.  
-  
-- err_t udp_bind(struct udp_pcb *pcb, struct ip_addr *ipaddr,
-                 u16_t port)
-
-  Binds the pcb to a local address. The IP-address argument "ipaddr"
-  can be IP_ADDR_ANY to indicate that it should listen to any local IP
-  address. The function currently always return ERR_OK.
-
-- err_t udp_connect(struct udp_pcb *pcb, struct ip_addr *ipaddr,
-                    u16_t port)
-
-  Sets the remote end of the pcb. This function does not generate any
-  network traffic, but only set the remote address of the pcb.
-
-- err_t udp_disconnect(struct udp_pcb *pcb)
-
-  Remove the remote end of the pcb. This function does not generate
-  any network traffic, but only removes the remote address of the pcb.
-
-- err_t udp_send(struct udp_pcb *pcb, struct pbuf *p)
-
-  Sends the pbuf p. The pbuf is not deallocated.
-
-- void udp_recv(struct udp_pcb *pcb,
-                void (* recv)(void *arg, struct udp_pcb *upcb,
-                                         struct pbuf *p,
-                                         struct ip_addr *addr,
-                                         u16_t port),
-                              void *recv_arg)
-
-  Specifies a callback function that should be called when a UDP
-  datagram is received.
-  
-
---- System initalization
-
-A truly complete and generic sequence for initializing the lwip stack
-cannot be given because it depends on the build configuration (lwipopts.h)
-and additional initializations for your runtime environment (e.g. timers).
-
-We can give you some idea on how to proceed when using the raw API.
-We assume a configuration using a single Ethernet netif and the
-UDP and TCP transport layers, IPv4 and the DHCP client.
-
-Call these functions in the order of appearance:
-
-- stats_init()
-
-  Clears the structure where runtime statistics are gathered.
-
-- sys_init()
-  
-  Not of much use since we set the NO_SYS 1 option in lwipopts.h,
-  to be called for easy configuration changes.
-
-- mem_init()
-
-  Initializes the dynamic memory heap defined by MEM_SIZE.
-
-- memp_init()
-
-  Initializes the memory pools defined by MEMP_NUM_x.
-
-- pbuf_init()
-
-  Initializes the pbuf memory pool defined by PBUF_POOL_SIZE.
-  
-- etharp_init()
-
-  Initializes the ARP table and queue.
-  Note: you must call etharp_tmr at a 10 second regular interval
-  after this initialization.
-
-- ip_init()
-
-  Doesn't do much, it should be called to handle future changes.
-
-- udp_init()
-
-  Clears the UDP PCB list.
-
-- tcp_init()
-
-  Clears the TCP PCB list and clears some internal TCP timers.
-  Note: you must call tcp_fasttmr() and tcp_slowtmr() at the
-  predefined regular intervals after this initialization. 
-  
-- netif_add(struct netif *netif, struct ip_addr *ipaddr,
-            struct ip_addr *netmask, struct ip_addr *gw,
-            void *state, err_t (* init)(struct netif *netif),
-            err_t (* input)(struct pbuf *p, struct netif *netif))
-
-  Adds your network interface to the netif_list. Allocate a struct
-  netif and pass a pointer to this structure as the first argument.
-  Give pointers to cleared ip_addr structures when using DHCP,
-  or fill them with sane numbers otherwise. The state pointer may be NULL.
-
-  The init function pointer must point to a initialization function for
-  your ethernet netif interface. The following code illustrates it's use.
-  
-  err_t netif_if_init(struct netif *netif)
-  {
-    u8_t i;
-    
-    for(i = 0; i < 6; i++) netif->hwaddr[i] = some_eth_addr[i];
-    init_my_eth_device();
-    return ERR_OK;
-  }
-  
-  The input function pointer must point to the lwip ip_input().
-  
-- netif_set_default(struct netif *netif)
-
-  Registers the default network interface.
-
-- netif_set_up(struct netif *netif)
-
-  When the netif is fully configured this function must be called.
-
-- dhcp_start(struct netif *netif)
-
-  Creates a new DHCP client for this interface on the first call.
-  Note: you must call dhcp_fine_tmr() and dhcp_coarse_tmr() at
-  the predefined regular intervals after starting the client.
-  
-  You can peek in the netif->dhcp struct for the actual DHCP status.
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/doc/savannah.txt b/Demo/lwIP_MCF5235_GCC/lwip/doc/savannah.txt
deleted file mode 100644
index 409905b10..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/doc/savannah.txt
+++ /dev/null
@@ -1,135 +0,0 @@
-Daily Use Guide for using Savannah for lwIP
-
-Table of Contents:
-
-1 - Obtaining lwIP from the CVS repository
-2 - Committers/developers CVS access using SSH (to be written)
-3 - Merging from DEVEL branch to main trunk (stable branch)
-4 - How to release lwIP
-
-
-
-1 Obtaining lwIP from the CVS repository
-----------------------------------------
-
-To perform an anonymous CVS checkout of the main trunk (this is where
-bug fixes and incremental enhancements occur), do this:
-
-cvs -z3 -d:pserver:anonymous@cvs.sv.gnu.org:/sources/lwip checkout lwip
- 
-Or, obtain a stable branch (updated with bug fixes only) as follows:
-cvs -z3 -d:pserver:anonymous@cvs.sv.gnu.org:/sources/lwip checkout \
-  -r STABLE-0_7 -d lwip-0.7 lwip
-
-Or, obtain a specific (fixed) release as follows:
-cvs -z3 -d:pserver:anonymous@cvs.sv.gnu.org:/sources/lwip checkout \
-  -r STABLE-0_7_0 -d lwip-0.7.0 lwip
-
-3 Committers/developers CVS access using SSH
---------------------------------------------
-
-The Savannah server uses SSH (Secure Shell) protocol 2 authentication and encryption.
-As such, CVS commits to the server occur through a SSH tunnel for project members.
-To create a SSH2 key pair in UNIX-like environments, do this:
-
-ssh-keygen -t dsa
-
-Under Windows, a recommended SSH client is "PuTTY", freely available with good
-documentation and a graphic user interface. Use its key generator.
-
-Now paste the id_dsa.pub contents into your Savannah account public key list. Wait
-a while so that Savannah can update its configuration (This can take minutes).
-
-Try to login using SSH:
-
-ssh -v your_login@cvs.sv.gnu.org
-
-If it tells you:
-
-Authenticating with public key "your_key_name"...
-Server refused to allocate pty
-
-then you could login; Savannah refuses to give you a shell - which is OK, as we
-are allowed to use SSH for CVS only. Now, you should be able to do this:
-
-export CVS_RSH=ssh
-cvs -z3 -d:ext:your_login@cvs.sv.gnu.org:/sources/lwip co lwip
- 
-after which you can edit your local files with bug fixes or new features and
-commit them. Make sure you know what you are doing when using CVS to make
-changes on the repository. If in doubt, ask on the lwip-members mailing list.
-
-(If SSH asks about authenticity of the host, you can check the key
- fingerprint against http://savannah.nongnu.org/cvs/?group=lwip)
-
-
-3 Merging from DEVEL branch to main trunk (stable)
---------------------------------------------------
-
-Merging is a delicate process in CVS and requires the
-following disciplined steps in order to prevent conflicts
-in the future. Conflicts can be hard to solve!
-
-Merging from branch A to branch B requires that the A branch
-has a tag indicating the previous merger. This tag is called
-'merged_from_A_to_B'. After merging, the tag is moved in the
-A branch to remember this merger for future merge actions.
-
-IMPORTANT: AFTER COMMITTING A SUCCESFUL MERGE IN THE
-REPOSITORY, THE TAG MUST BE SET ON THE SOURCE BRANCH OF THE
-MERGE ACTION (REPLACING EXISTING TAGS WITH THE SAME NAME).
-
-Merge all changes in DEVEL since our last merge to main:
-
-In the working copy of the main trunk:
-cvs update -P -jmerged_from_DEVEL_to_main -jDEVEL 
-
-(This will apply the changes between 'merged_from_DEVEL_to_main'
-and 'DEVEL' to your work set of files)
-
-We can now commit the merge result.
-cvs commit -R -m "Merged from DEVEL to main." 
-
-If this worked out OK, we now move the tag in the DEVEL branch
-to this merge point, so we can use this point for future merges:
-
-cvs rtag -F -r DEVEL merged_from_DEVEL_to_main lwip 
-
-4 How to release lwIP
----------------------
-
-First, checkout a clean copy of the branch to be released. Tag this set with
-tag name "STABLE-0_6_3". (I use release number 0.6.3 throughout this example).
-
-Login CVS using pserver authentication, then export a clean copy of the
-tagged tree. Export is similar to a checkout, except that the CVS metadata
-is not created locally. 
-
-export CVS_RSH=ssh
-cvs -z3 -d:pserver:anonymous@cvs.sv.gnu.org:/sources/lwip checkout \
-  -r STABLE-0_6_3 -d lwip-0.6.3 lwip
-
-Archive this directory using tar, gzip'd, bzip2'd and zip'd.
-
-tar czvf lwip-0.6.3.tar.gz lwip-0.6.3
-tar cjvf lwip-0.6.3.tar.bz2 lwip-0.6.3
-zip -r lwip-0.6.3.zip lwip-0.6.3
-
-Now, sign the archives with a detached GPG binary signature as follows:
-
-gpg -b lwip-0.6.3.tar.gz
-gpg -b lwip-0.6.3.tar.bz2
-gpg -b lwip-0.6.3.zip
-
-Upload these files using anonymous FTP:
-ncftp ftp://savannah.gnu.org/incoming/savannah/lwip
-
-ncftp>mput *0.6.3.*
-
-Additionally, you may post a news item on Savannah, like this:
-
-A new 0.6.3 release is now available here:
-http://savannah.nongnu.org/files/?group=lwip&highlight=0.6.3
-
-You will have to submit this via the user News interface, then approve
-this via the Administrator News interface.
\ No newline at end of file
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/doc/sys_arch.txt b/Demo/lwIP_MCF5235_GCC/lwip/doc/sys_arch.txt
deleted file mode 100644
index 95d0add73..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/doc/sys_arch.txt
+++ /dev/null
@@ -1,194 +0,0 @@
-sys_arch interface for lwIP 0.6++
-
-Author: Adam Dunkels
-
-The operating system emulation layer provides a common interface
-between the lwIP code and the underlying operating system kernel. The
-general idea is that porting lwIP to new architectures requires only
-small changes to a few header files and a new sys_arch
-implementation. It is also possible to do a sys_arch implementation
-that does not rely on any underlying operating system.
-
-The sys_arch provides semaphores and mailboxes to lwIP. For the full
-lwIP functionality, multiple threads support can be implemented in the
-sys_arch, but this is not required for the basic lwIP
-functionality. Previous versions of lwIP required the sys_arch to
-implement timer scheduling as well but as of lwIP 0.5 this is
-implemented in a higher layer.
-
-In addition to the source file providing the functionality of sys_arch,
-the OS emulation layer must provide several header files defining
-macros used throughout lwip.  The files required and the macros they
-must define are listed below the sys_arch description.
-
-Semaphores can be either counting or binary - lwIP works with both
-kinds. Mailboxes are used for message passing and can be implemented
-either as a queue which allows multiple messages to be posted to a
-mailbox, or as a rendez-vous point where only one message can be
-posted at a time. lwIP works with both kinds, but the former type will
-be more efficient. A message in a mailbox is just a pointer, nothing
-more. 
-
-Semaphores are represented by the type "sys_sem_t" which is typedef'd
-in the sys_arch.h file. Mailboxes are equivalently represented by the
-type "sys_mbox_t". lwIP does not place any restrictions on how
-sys_sem_t or sys_mbox_t are represented internally.
-
-The following functions must be implemented by the sys_arch:
-
-- void sys_init(void)
-
-  Is called to initialize the sys_arch layer.
-
-- sys_sem_t sys_sem_new(u8_t count)
-
-  Creates and returns a new semaphore. The "count" argument specifies
-  the initial state of the semaphore.
-
-- void sys_sem_free(sys_sem_t sem)
-
-  Deallocates a semaphore.
-
-- void sys_sem_signal(sys_sem_t sem)
-
-  Signals a semaphore.
-
-- u32_t sys_arch_sem_wait(sys_sem_t sem, u32_t timeout)
-
-  Blocks the thread while waiting for the semaphore to be
-  signaled. If the "timeout" argument is non-zero, the thread should
-  only be blocked for the specified time (measured in
-  milliseconds).
-
-  If the timeout argument is non-zero, the return value is the number of
-  milliseconds spent waiting for the semaphore to be signaled. If the
-  semaphore wasn't signaled within the specified time, the return value is
-  SYS_ARCH_TIMEOUT. If the thread didn't have to wait for the semaphore
-  (i.e., it was already signaled), the function may return zero.
-
-  Notice that lwIP implements a function with a similar name,
-  sys_sem_wait(), that uses the sys_arch_sem_wait() function.
-
-- sys_mbox_t sys_mbox_new(void)
-
-  Creates an empty mailbox.
-
-- void sys_mbox_free(sys_mbox_t mbox)
-
-  Deallocates a mailbox. If there are messages still present in the
-  mailbox when the mailbox is deallocated, it is an indication of a
-  programming error in lwIP and the developer should be notified.
-
-- void sys_mbox_post(sys_mbox_t mbox, void *msg)
-
-  Posts the "msg" to the mailbox.
-
-- u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout)
-
-  Blocks the thread until a message arrives in the mailbox, but does
-  not block the thread longer than "timeout" milliseconds (similar to
-  the sys_arch_sem_wait() function). The "msg" argument is a result
-  parameter that is set by the function (i.e., by doing "*msg =
-  ptr"). The "msg" parameter maybe NULL to indicate that the message
-  should be dropped.
-
-  The return values are the same as for the sys_arch_sem_wait() function:
-  Number of milliseconds spent waiting or SYS_ARCH_TIMEOUT if there was a
-  timeout.
-
-  Note that a function with a similar name, sys_mbox_fetch(), is
-  implemented by lwIP. 
-  
-- struct sys_timeouts *sys_arch_timeouts(void)
-
-  Returns a pointer to the per-thread sys_timeouts structure. In lwIP,
-  each thread has a list of timeouts which is repressented as a linked
-  list of sys_timeout structures. The sys_timeouts structure holds a
-  pointer to a linked list of timeouts. This function is called by
-  the lwIP timeout scheduler and must not return a NULL value. 
-
-  In a single threadd sys_arch implementation, this function will
-  simply return a pointer to a global sys_timeouts variable stored in
-  the sys_arch module.
-  
-If threads are supported by the underlying operating system and if
-such functionality is needed in lwIP, the following function will have
-to be implemented as well:
-
-- sys_thread_t sys_thread_new(void (* thread)(void *arg), void *arg, int prio)
-
-  Starts a new thread with priority "prio" that will begin its execution in the
-  function "thread()". The "arg" argument will be passed as an argument to the
-  thread() function. The id of the new thread is returned. Both the id and
-  the priority are system dependent.
-
-- sys_prot_t sys_arch_protect(void)
-
-  This optional function does a "fast" critical region protection and returns
-  the previous protection level. This function is only called during very short
-  critical regions. An embedded system which supports ISR-based drivers might
-  want to implement this function by disabling interrupts. Task-based systems
-  might want to implement this by using a mutex or disabling tasking. This
-  function should support recursive calls from the same task or interrupt. In
-  other words, sys_arch_protect() could be called while already protected. In
-  that case the return value indicates that it is already protected.
-
-  sys_arch_protect() is only required if your port is supporting an operating
-  system.
-
-- void sys_arch_unprotect(sys_prot_t pval)
-
-  This optional function does a "fast" set of critical region protection to the
-  value specified by pval. See the documentation for sys_arch_protect() for
-  more information. This function is only required if your port is supporting
-  an operating system.
-
--------------------------------------------------------------------------------
-Additional files required for the "OS support" emulation layer:
--------------------------------------------------------------------------------
-
-cc.h       - Architecture environment, some compiler specific, some
-             environment specific (probably should move env stuff 
-             to sys_arch.h.)
-
-  Typedefs for the types used by lwip -
-    u8_t, s8_t, u16_t, s16_t, u32_t, s32_t, mem_ptr_t
-
-  Compiler hints for packing lwip's structures -
-    PACK_STRUCT_FIELD(x)
-    PACK_STRUCT_STRUCT
-    PACK_STRUCT_BEGIN
-    PACK_STRUCT_END
-
-  Platform specific diagnostic output -
-    LWIP_PLATFORM_DIAG(x)    - non-fatal, print a message.
-    LWIP_PLATFORM_ASSERT(x)  - fatal, print message and abandon execution.
-
-  "lightweight" synchronization mechanisms -
-    SYS_ARCH_DECL_PROTECT(x) - declare a protection state variable.
-    SYS_ARCH_PROTECT(x)      - enter protection mode.
-    SYS_ARCH_UNPROTECT(x)    - leave protection mode.
-
-  If the compiler does not provide memset() this file must include a
-  definition of it, or include a file which defines it.
-
-  This file must either include a system-local  which defines
-  the standard *nix error codes, or it should #define LWIP_PROVIDE_ERRNO
-  to make lwip/arch.h define the codes which are used throughout.
-
-
-perf.h     - Architecture specific performance measurement.
-  Measurement calls made throughout lwip, these can be defined to nothing.
-    PERF_START               - start measuring something.
-    PERF_STOP(x)             - stop measuring something, and record the result.
-
-sys_arch.h - Tied to sys_arch.c
-
-  Arch dependent types for the following objects:
-    sys_sem_t, sys_mbox_t, sys_thread_t,
-  And, optionally:
-    sys_prot_t
-
-  Defines to set vars of sys_mbox_t and sys_sem_t to NULL.
-    SYS_MBOX_NULL NULL
-    SYS_SEM_NULL NULL
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/FILES b/Demo/lwIP_MCF5235_GCC/lwip/src/FILES
deleted file mode 100644
index 2b6573185..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/FILES
+++ /dev/null
@@ -1,13 +0,0 @@
-api/      - The code for the high-level wrapper API. Not needed if
-            you use the lowel-level call-back/raw API.
-
-core/     - The core of the TPC/IP stack; protocol implementations,
-            memory and buffer management, and the low-level raw API.
-	    
-include/  - lwIP include files.
-
-netif/    - Generic network interface device drivers are kept here,
-            as well as the ARP module.
-
-For more information on the various subdirectories, check the FILES
-file in each directory.
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/api/api_lib.c b/Demo/lwIP_MCF5235_GCC/lwip/src/api/api_lib.c
deleted file mode 100644
index 3d83d1ea4..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/api/api_lib.c
+++ /dev/null
@@ -1,729 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-
-/* This is the part of the API that is linked with
-   the application */
-
-#include "lwip/opt.h"
-#include "lwip/api.h"
-#include "lwip/api_msg.h"
-#include "lwip/memp.h"
-
-
-struct
-netbuf *netbuf_new(void)
-{
-  struct netbuf *buf;
-
-  buf = memp_malloc(MEMP_NETBUF);
-  if (buf != NULL) {
-    buf->p = NULL;
-    buf->ptr = NULL;
-    return buf;
-  } else {
-    return NULL;
-  }
-}
-
-void
-netbuf_delete(struct netbuf *buf)
-{
-  if (buf != NULL) {
-    if (buf->p != NULL) {
-      pbuf_free(buf->p);
-      buf->p = buf->ptr = NULL;
-    }
-    memp_free(MEMP_NETBUF, buf);
-  }
-}
-
-void *
-netbuf_alloc(struct netbuf *buf, u16_t size)
-{
-  /* Deallocate any previously allocated memory. */
-  if (buf->p != NULL) {
-    pbuf_free(buf->p);
-  }
-  buf->p = pbuf_alloc(PBUF_TRANSPORT, size, PBUF_RAM);
-  if (buf->p == NULL) {
-     return NULL;
-  }
-  buf->ptr = buf->p;
-  return buf->p->payload;
-}
-
-void
-netbuf_free(struct netbuf *buf)
-{
-  if (buf->p != NULL) {
-    pbuf_free(buf->p);
-  }
-  buf->p = buf->ptr = NULL;
-}
-
-void
-netbuf_ref(struct netbuf *buf, void *dataptr, u16_t size)
-{
-  if (buf->p != NULL) {
-    pbuf_free(buf->p);
-  }
-  buf->p = pbuf_alloc(PBUF_TRANSPORT, 0, PBUF_REF);
-  buf->p->payload = dataptr;
-  buf->p->len = buf->p->tot_len = size;
-  buf->ptr = buf->p;
-}
-
-void
-netbuf_chain(struct netbuf *head, struct netbuf *tail)
-{
-  pbuf_chain(head->p, tail->p);
-  head->ptr = head->p;
-  memp_free(MEMP_NETBUF, tail);
-}
-
-u16_t
-netbuf_len(struct netbuf *buf)
-{
-  return buf->p->tot_len;
-}
-
-err_t
-netbuf_data(struct netbuf *buf, void **dataptr, u16_t *len)
-{
-  if (buf->ptr == NULL) {
-    return ERR_BUF;
-  }
-  *dataptr = buf->ptr->payload;
-  *len = buf->ptr->len;
-  return ERR_OK;
-}
-
-s8_t
-netbuf_next(struct netbuf *buf)
-{
-  if (buf->ptr->next == NULL) {
-    return -1;
-  }
-  buf->ptr = buf->ptr->next;
-  if (buf->ptr->next == NULL) {
-    return 1;
-  }
-  return 0;
-}
-
-void
-netbuf_first(struct netbuf *buf)
-{
-  buf->ptr = buf->p;
-}
-
-void
-netbuf_copy_partial(struct netbuf *buf, void *dataptr, u16_t len, u16_t offset)
-{
-  struct pbuf *p;
-  u16_t i, left;
-
-  left = 0;
-
-  if(buf == NULL || dataptr == NULL) {
-    return;
-  }
-  
-  /* This implementation is bad. It should use bcopy
-     instead. */
-  for(p = buf->p; left < len && p != NULL; p = p->next) {
-    if (offset != 0 && offset >= p->len) {
-      offset -= p->len;
-    } else {    
-      for(i = offset; i < p->len; ++i) {
-  ((u8_t *)dataptr)[left] = ((u8_t *)p->payload)[i];
-  if (++left >= len) {
-    return;
-  }
-      }
-      offset = 0;
-    }
-  }
-}
-
-void
-netbuf_copy(struct netbuf *buf, void *dataptr, u16_t len)
-{
-  netbuf_copy_partial(buf, dataptr, len, 0);
-}
-
-struct ip_addr *
-netbuf_fromaddr(struct netbuf *buf)
-{
-  return buf->fromaddr;
-}
-
-u16_t
-netbuf_fromport(struct netbuf *buf)
-{
-  return buf->fromport;
-}
-
-struct
-netconn *netconn_new_with_proto_and_callback(enum netconn_type t, u16_t proto,
-                                   void (*callback)(struct netconn *, enum netconn_evt, u16_t len))
-{
-  struct netconn *conn;
-  struct api_msg *msg;
-
-  conn = memp_malloc(MEMP_NETCONN);
-  if (conn == NULL) {
-    return NULL;
-  }
-  
-  conn->err = ERR_OK;
-  conn->type = t;
-  conn->pcb.tcp = NULL;
-
-  if ((conn->mbox = sys_mbox_new()) == SYS_MBOX_NULL) {
-    memp_free(MEMP_NETCONN, conn);
-    return NULL;
-  }
-  conn->recvmbox = SYS_MBOX_NULL;
-  conn->acceptmbox = SYS_MBOX_NULL;
-  conn->sem = SYS_SEM_NULL;
-  conn->state = NETCONN_NONE;
-  conn->socket = 0;
-  conn->callback = callback;
-  conn->recv_avail = 0;
-
-  if((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
-    memp_free(MEMP_NETCONN, conn);
-    return NULL;
-  }
-  
-  msg->type = API_MSG_NEWCONN;
-  msg->msg.msg.bc.port = proto; /* misusing the port field */
-  msg->msg.conn = conn;
-  api_msg_post(msg);  
-  sys_mbox_fetch(conn->mbox, NULL);
-  memp_free(MEMP_API_MSG, msg);
-
-  if ( conn->err != ERR_OK ) {
-    memp_free(MEMP_NETCONN, conn);
-    return NULL;
-  }
-
-  return conn;
-}
-
-
-struct
-netconn *netconn_new(enum netconn_type t)
-{
-  return netconn_new_with_proto_and_callback(t,0,NULL);
-}
-
-struct
-netconn *netconn_new_with_callback(enum netconn_type t,
-                                   void (*callback)(struct netconn *, enum netconn_evt, u16_t len))
-{
-  return netconn_new_with_proto_and_callback(t,0,callback);
-}
-
-
-err_t
-netconn_delete(struct netconn *conn)
-{
-  struct api_msg *msg;
-  void *mem;
-  
-  if (conn == NULL) {
-    return ERR_OK;
-  }
-  
-  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
-    return ERR_MEM;
-  }
-  
-  msg->type = API_MSG_DELCONN;
-  msg->msg.conn = conn;
-  api_msg_post(msg);  
-  sys_mbox_fetch(conn->mbox, NULL);
-  memp_free(MEMP_API_MSG, msg);
-
-  /* Drain the recvmbox. */
-  if (conn->recvmbox != SYS_MBOX_NULL) {
-    while (sys_arch_mbox_fetch(conn->recvmbox, &mem, 1) != SYS_ARCH_TIMEOUT) {
-      if (conn->type == NETCONN_TCP) {
-        if(mem != NULL)
-          pbuf_free((struct pbuf *)mem);
-      } else {
-        netbuf_delete((struct netbuf *)mem);
-      }
-    }
-    sys_mbox_free(conn->recvmbox);
-    conn->recvmbox = SYS_MBOX_NULL;
-  }
- 
-
-  /* Drain the acceptmbox. */
-  if (conn->acceptmbox != SYS_MBOX_NULL) {
-    while (sys_arch_mbox_fetch(conn->acceptmbox, &mem, 1) != SYS_ARCH_TIMEOUT) {
-      netconn_delete((struct netconn *)mem);
-    }
-    
-    sys_mbox_free(conn->acceptmbox);
-    conn->acceptmbox = SYS_MBOX_NULL;
-  }
-
-  sys_mbox_free(conn->mbox);
-  conn->mbox = SYS_MBOX_NULL;
-  if (conn->sem != SYS_SEM_NULL) {
-    sys_sem_free(conn->sem);
-  }
-  /*  conn->sem = SYS_SEM_NULL;*/
-  memp_free(MEMP_NETCONN, conn);
-  return ERR_OK;
-}
-
-enum netconn_type
-netconn_type(struct netconn *conn)
-{
-  return conn->type;
-}
-
-err_t
-netconn_peer(struct netconn *conn, struct ip_addr *addr,
-       u16_t *port)
-{
-  switch (conn->type) {
-  case NETCONN_RAW:
-    /* return an error as connecting is only a helper for upper layers */
-    return ERR_CONN;
-  case NETCONN_UDPLITE:
-  case NETCONN_UDPNOCHKSUM:
-  case NETCONN_UDP:
-    if (conn->pcb.udp == NULL ||
-  ((conn->pcb.udp->flags & UDP_FLAGS_CONNECTED) == 0))
-     return ERR_CONN;
-    *addr = (conn->pcb.udp->remote_ip);
-    *port = conn->pcb.udp->remote_port;
-    break;
-  case NETCONN_TCP:
-    if (conn->pcb.tcp == NULL)
-      return ERR_CONN;
-    *addr = (conn->pcb.tcp->remote_ip);
-    *port = conn->pcb.tcp->remote_port;
-    break;
-  }
-  return (conn->err = ERR_OK);
-}
-
-err_t
-netconn_addr(struct netconn *conn, struct ip_addr **addr,
-       u16_t *port)
-{
-  switch (conn->type) {
-  case NETCONN_RAW:
-    *addr = &(conn->pcb.raw->local_ip);
-    *port = conn->pcb.raw->protocol;
-    break;
-  case NETCONN_UDPLITE:
-  case NETCONN_UDPNOCHKSUM:
-  case NETCONN_UDP:
-    *addr = &(conn->pcb.udp->local_ip);
-    *port = conn->pcb.udp->local_port;
-    break;
-  case NETCONN_TCP:
-    *addr = &(conn->pcb.tcp->local_ip);
-    *port = conn->pcb.tcp->local_port;
-    break;
-  }
-  return (conn->err = ERR_OK);
-}
-
-err_t
-netconn_bind(struct netconn *conn, struct ip_addr *addr,
-      u16_t port)
-{
-  struct api_msg *msg;
-
-  if (conn == NULL) {
-    return ERR_VAL;
-  }
-
-  if (conn->type != NETCONN_TCP &&
-     conn->recvmbox == SYS_MBOX_NULL) {
-    if ((conn->recvmbox = sys_mbox_new()) == SYS_MBOX_NULL) {
-      return ERR_MEM;
-    }
-  }
-  
-  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
-    return (conn->err = ERR_MEM);
-  }
-  msg->type = API_MSG_BIND;
-  msg->msg.conn = conn;
-  msg->msg.msg.bc.ipaddr = addr;
-  msg->msg.msg.bc.port = port;
-  api_msg_post(msg);
-  sys_mbox_fetch(conn->mbox, NULL);
-  memp_free(MEMP_API_MSG, msg);
-  return conn->err;
-}
-
-
-err_t
-netconn_connect(struct netconn *conn, struct ip_addr *addr,
-       u16_t port)
-{
-  struct api_msg *msg;
-  
-  if (conn == NULL) {
-    return ERR_VAL;
-  }
-
-
-  if (conn->recvmbox == SYS_MBOX_NULL) {
-    if ((conn->recvmbox = sys_mbox_new()) == SYS_MBOX_NULL) {
-      return ERR_MEM;
-    }
-  }
-  
-  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
-    return ERR_MEM;
-  }
-  msg->type = API_MSG_CONNECT;
-  msg->msg.conn = conn;  
-  msg->msg.msg.bc.ipaddr = addr;
-  msg->msg.msg.bc.port = port;
-  api_msg_post(msg);
-  sys_mbox_fetch(conn->mbox, NULL);
-  memp_free(MEMP_API_MSG, msg);
-  return conn->err;
-}
-
-err_t
-netconn_disconnect(struct netconn *conn)
-{
-  struct api_msg *msg;
-  
-  if (conn == NULL) {
-    return ERR_VAL;
-  }
-
-  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
-    return ERR_MEM;
-  }
-  msg->type = API_MSG_DISCONNECT;
-  msg->msg.conn = conn;  
-  api_msg_post(msg);
-  sys_mbox_fetch(conn->mbox, NULL);
-  memp_free(MEMP_API_MSG, msg);
-  return conn->err;
-
-}
-
-err_t
-netconn_listen(struct netconn *conn)
-{
-  struct api_msg *msg;
-
-  if (conn == NULL) {
-    return ERR_VAL;
-  }
-
-  if (conn->acceptmbox == SYS_MBOX_NULL) {
-    conn->acceptmbox = sys_mbox_new();
-    if (conn->acceptmbox == SYS_MBOX_NULL) {
-      return ERR_MEM;
-    }
-  }
-  
-  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
-    return (conn->err = ERR_MEM);
-  }
-  msg->type = API_MSG_LISTEN;
-  msg->msg.conn = conn;
-  api_msg_post(msg);
-  sys_mbox_fetch(conn->mbox, NULL);
-  memp_free(MEMP_API_MSG, msg);
-  return conn->err;
-}
-
-struct netconn *
-netconn_accept(struct netconn *conn)
-{
-  struct netconn *newconn;
-  
-  if (conn == NULL) {
-    return NULL;
-  }
-  
-  sys_mbox_fetch(conn->acceptmbox, (void **)&newconn);
-  /* Register event with callback */
-  if (conn->callback)
-      (*conn->callback)(conn, NETCONN_EVT_RCVMINUS, 0);
-  
-  return newconn;
-}
-
-struct netbuf *
-netconn_recv(struct netconn *conn)
-{
-  struct api_msg *msg;
-  struct netbuf *buf;
-  struct pbuf *p;
-  u16_t len;
-    
-  if (conn == NULL) {
-    return NULL;
-  }
-  
-  if (conn->recvmbox == SYS_MBOX_NULL) {
-    conn->err = ERR_CONN;
-    return NULL;
-  }
-
-  if (conn->err != ERR_OK) {
-    return NULL;
-  }
-
-  if (conn->type == NETCONN_TCP) {
-    if (conn->pcb.tcp->state == LISTEN) {
-      conn->err = ERR_CONN;
-      return NULL;
-    }
-
-
-    buf = memp_malloc(MEMP_NETBUF);
-
-    if (buf == NULL) {
-      conn->err = ERR_MEM;
-      return NULL;
-    }
-    
-    sys_mbox_fetch(conn->recvmbox, (void **)&p);
-
-    if (p != NULL)
-    {
-        len = p->tot_len;
-        conn->recv_avail -= len;
-    }
-    else
-        len = 0;
-    
-    /* Register event with callback */
-      if (conn->callback)
-        (*conn->callback)(conn, NETCONN_EVT_RCVMINUS, len);
-
-    /* If we are closed, we indicate that we no longer wish to receive
-       data by setting conn->recvmbox to SYS_MBOX_NULL. */
-    if (p == NULL) {
-      memp_free(MEMP_NETBUF, buf);
-      sys_mbox_free(conn->recvmbox);
-      conn->recvmbox = SYS_MBOX_NULL;
-      return NULL;
-    }
-
-    buf->p = p;
-    buf->ptr = p;
-    buf->fromport = 0;
-    buf->fromaddr = NULL;
-
-    /* Let the stack know that we have taken the data. */
-    if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
-      conn->err = ERR_MEM;
-      return buf;
-    }
-    msg->type = API_MSG_RECV;
-    msg->msg.conn = conn;
-    if (buf != NULL) {
-      msg->msg.msg.len = buf->p->tot_len;
-    } else {
-      msg->msg.msg.len = 1;
-    }
-    api_msg_post(msg);
-
-    sys_mbox_fetch(conn->mbox, NULL);
-    memp_free(MEMP_API_MSG, msg);
-  } else {
-    sys_mbox_fetch(conn->recvmbox, (void **)&buf);
-  conn->recv_avail -= buf->p->tot_len;
-    /* Register event with callback */
-    if (conn->callback)
-        (*conn->callback)(conn, NETCONN_EVT_RCVMINUS, buf->p->tot_len);
-  }
-
-  
-
-    
-  LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_recv: received %p (err %d)\n", (void *)buf, conn->err));
-
-
-  return buf;
-}
-
-err_t
-netconn_send(struct netconn *conn, struct netbuf *buf)
-{
-  struct api_msg *msg;
-
-  if (conn == NULL) {
-    return ERR_VAL;
-  }
-
-  if (conn->err != ERR_OK) {
-    return conn->err;
-  }
-
-  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
-    return (conn->err = ERR_MEM);
-  }
-
-  LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_send: sending %d bytes\n", buf->p->tot_len));
-  msg->type = API_MSG_SEND;
-  msg->msg.conn = conn;
-  msg->msg.msg.p = buf->p;
-  api_msg_post(msg);
-
-  sys_mbox_fetch(conn->mbox, NULL);
-  memp_free(MEMP_API_MSG, msg);
-  return conn->err;
-}
-
-err_t
-netconn_write(struct netconn *conn, void *dataptr, u16_t size, u8_t copy)
-{
-  struct api_msg *msg;
-  u16_t len;
-  
-  if (conn == NULL) {
-    return ERR_VAL;
-  }
-
-  if (conn->err != ERR_OK) {
-    return conn->err;
-  }
-  
-  if (conn->sem == SYS_SEM_NULL) {
-    conn->sem = sys_sem_new(0);
-    if (conn->sem == SYS_SEM_NULL) {
-      return ERR_MEM;
-    }
-  }
-
-  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
-    return (conn->err = ERR_MEM);
-  }
-  msg->type = API_MSG_WRITE;
-  msg->msg.conn = conn;
-        
-
-  conn->state = NETCONN_WRITE;
-  while (conn->err == ERR_OK && size > 0) {
-    msg->msg.msg.w.dataptr = dataptr;
-    msg->msg.msg.w.copy = copy;
-    
-    if (conn->type == NETCONN_TCP) {
-      if (tcp_sndbuf(conn->pcb.tcp) == 0) {
-  sys_sem_wait(conn->sem);
-  if (conn->err != ERR_OK) {
-    goto ret;
-  }
-      }
-      if (size > tcp_sndbuf(conn->pcb.tcp)) {
-  /* We cannot send more than one send buffer's worth of data at a
-     time. */
-  len = tcp_sndbuf(conn->pcb.tcp);
-      } else {
-  len = size;
-      }
-    } else {
-      len = size;
-    }
-    
-    LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_write: writing %d bytes (%d)\n", len, copy));
-    msg->msg.msg.w.len = len;
-    api_msg_post(msg);
-    sys_mbox_fetch(conn->mbox, NULL);    
-    if (conn->err == ERR_OK) {
-      dataptr = (void *)((u8_t *)dataptr + len);
-      size -= len;
-    } else if (conn->err == ERR_MEM) {
-      conn->err = ERR_OK;
-      sys_sem_wait(conn->sem);
-    } else {
-      goto ret;
-    }
-  }
- ret:
-  memp_free(MEMP_API_MSG, msg);
-  conn->state = NETCONN_NONE;
-  if (conn->sem != SYS_SEM_NULL) {
-    sys_sem_free(conn->sem);
-    conn->sem = SYS_SEM_NULL;
-  }
-  
-  return conn->err;
-}
-
-err_t
-netconn_close(struct netconn *conn)
-{
-  struct api_msg *msg;
-
-  if (conn == NULL) {
-    return ERR_VAL;
-  }
-  if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) {
-    return (conn->err = ERR_MEM);
-  }
-
-  conn->state = NETCONN_CLOSE;
- again:
-  msg->type = API_MSG_CLOSE;
-  msg->msg.conn = conn;
-  api_msg_post(msg);
-  sys_mbox_fetch(conn->mbox, NULL);
-  if (conn->err == ERR_MEM &&
-     conn->sem != SYS_SEM_NULL) {
-    sys_sem_wait(conn->sem);
-    goto again;
-  }
-  conn->state = NETCONN_NONE;
-  memp_free(MEMP_API_MSG, msg);
-  return conn->err;
-}
-
-err_t
-netconn_err(struct netconn *conn)
-{
-  return conn->err;
-}
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/api/api_msg.c b/Demo/lwIP_MCF5235_GCC/lwip/src/api/api_msg.c
deleted file mode 100644
index 0cbe626fb..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/api/api_msg.c
+++ /dev/null
@@ -1,800 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-
-#include "lwip/opt.h"
-#include "lwip/arch.h"
-#include "lwip/api_msg.h"
-#include "lwip/memp.h"
-#include "lwip/sys.h"
-#include "lwip/tcpip.h"
-
-#if LWIP_RAW
-static u8_t
-recv_raw(void *arg, struct raw_pcb *pcb, struct pbuf *p,
-    struct ip_addr *addr)
-{
-  struct netbuf *buf;
-  struct netconn *conn;
-
-  conn = arg;
-  if (!conn) return 0;
-
-  if (conn->recvmbox != SYS_MBOX_NULL) {
-    if (!(buf = memp_malloc(MEMP_NETBUF))) {
-      return 0;
-    }
-    pbuf_ref(p);
-    buf->p = p;
-    buf->ptr = p;
-    buf->fromaddr = addr;
-    buf->fromport = pcb->protocol;
-
-    conn->recv_avail += p->tot_len;
-    /* Register event with callback */
-    if (conn->callback)
-        (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, p->tot_len);
-    sys_mbox_post(conn->recvmbox, buf);
-  }
-
-  return 0; /* do not eat the packet */
-}
-#endif
-#if LWIP_UDP
-static void
-recv_udp(void *arg, struct udp_pcb *pcb, struct pbuf *p,
-   struct ip_addr *addr, u16_t port)
-{
-  struct netbuf *buf;
-  struct netconn *conn;
-
-  conn = arg;
-  
-  if (conn == NULL) {
-    pbuf_free(p);
-    return;
-  }
-  if (conn->recvmbox != SYS_MBOX_NULL) {
-    buf = memp_malloc(MEMP_NETBUF);
-    if (buf == NULL) {
-      pbuf_free(p);
-      return;
-    } else {
-      buf->p = p;
-      buf->ptr = p;
-      buf->fromaddr = addr;
-      buf->fromport = port;
-    }
-
-  conn->recv_avail += p->tot_len;
-    /* Register event with callback */
-    if (conn->callback)
-        (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, p->tot_len);
-    sys_mbox_post(conn->recvmbox, buf);
-  }
-}
-#endif /* LWIP_UDP */
-#if LWIP_TCP
-
-static err_t
-recv_tcp(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err)
-{
-  struct netconn *conn;
-  u16_t len;
-  
-  conn = arg;
-
-  if (conn == NULL) {
-    pbuf_free(p);
-    return ERR_VAL;
-  }
-
-  if (conn->recvmbox != SYS_MBOX_NULL) {
-        
-    conn->err = err;
-    if (p != NULL) {
-        len = p->tot_len;
-        conn->recv_avail += len;
-    }
-    else
-        len = 0;
-    /* Register event with callback */
-    if (conn->callback)
-        (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, len);
-    sys_mbox_post(conn->recvmbox, p);
-  }  
-  return ERR_OK;
-}
-
-
-static err_t
-poll_tcp(void *arg, struct tcp_pcb *pcb)
-{
-  struct netconn *conn;
-
-  conn = arg;
-  if (conn != NULL &&
-     (conn->state == NETCONN_WRITE || conn->state == NETCONN_CLOSE) &&
-     conn->sem != SYS_SEM_NULL) {
-    sys_sem_signal(conn->sem);
-  }
-  return ERR_OK;
-}
-
-static err_t
-sent_tcp(void *arg, struct tcp_pcb *pcb, u16_t len)
-{
-  struct netconn *conn;
-
-  conn = arg;
-  if (conn != NULL && conn->sem != SYS_SEM_NULL) {
-    sys_sem_signal(conn->sem);
-  }
-
-  if (conn && conn->callback)
-      if (tcp_sndbuf(conn->pcb.tcp) > TCP_SNDLOWAT)
-          (*conn->callback)(conn, NETCONN_EVT_SENDPLUS, len);
-  
-  return ERR_OK;
-}
-
-static void
-err_tcp(void *arg, err_t err)
-{
-  struct netconn *conn;
-
-  conn = arg;
-
-  conn->pcb.tcp = NULL;
-
-  
-  conn->err = err;
-  if (conn->recvmbox != SYS_MBOX_NULL) {
-    /* Register event with callback */
-    if (conn->callback)
-      (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, 0);
-    sys_mbox_post(conn->recvmbox, NULL);
-  }
-  if (conn->mbox != SYS_MBOX_NULL) {
-    sys_mbox_post(conn->mbox, NULL);
-  }
-  if (conn->acceptmbox != SYS_MBOX_NULL) {
-     /* Register event with callback */
-    if (conn->callback)
-      (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, 0);
-    sys_mbox_post(conn->acceptmbox, NULL);
-  }
-  if (conn->sem != SYS_SEM_NULL) {
-    sys_sem_signal(conn->sem);
-  }
-}
-
-static void
-setup_tcp(struct netconn *conn)
-{
-  struct tcp_pcb *pcb;
-  
-  pcb = conn->pcb.tcp;
-  tcp_arg(pcb, conn);
-  tcp_recv(pcb, recv_tcp);
-  tcp_sent(pcb, sent_tcp);
-  tcp_poll(pcb, poll_tcp, 4);
-  tcp_err(pcb, err_tcp);
-}
-
-static err_t
-accept_function(void *arg, struct tcp_pcb *newpcb, err_t err)
-{
-  sys_mbox_t mbox;
-  struct netconn *newconn;
-  struct netconn *conn;
-  
-#if API_MSG_DEBUG
-#if TCP_DEBUG
-  tcp_debug_print_state(newpcb->state);
-#endif /* TCP_DEBUG */
-#endif /* API_MSG_DEBUG */
-  conn = (struct netconn *)arg;
-  mbox = conn->acceptmbox;
-  newconn = memp_malloc(MEMP_NETCONN);
-  if (newconn == NULL) {
-    return ERR_MEM;
-  }
-  newconn->type = NETCONN_TCP;
-  newconn->pcb.tcp = newpcb;
-  setup_tcp(newconn);
-  newconn->recvmbox = sys_mbox_new();
-  if (newconn->recvmbox == SYS_MBOX_NULL) {
-    memp_free(MEMP_NETCONN, newconn);
-    return ERR_MEM;
-  }
-  newconn->mbox = sys_mbox_new();
-  if (newconn->mbox == SYS_MBOX_NULL) {
-    sys_mbox_free(newconn->recvmbox);
-    memp_free(MEMP_NETCONN, newconn);
-    return ERR_MEM;
-  }
-  newconn->sem = sys_sem_new(0);
-  if (newconn->sem == SYS_SEM_NULL) {
-    sys_mbox_free(newconn->recvmbox);
-    sys_mbox_free(newconn->mbox);
-    memp_free(MEMP_NETCONN, newconn);
-    return ERR_MEM;
-  }
-  newconn->acceptmbox = SYS_MBOX_NULL;
-  newconn->err = err;
-  /* Register event with callback */
-  if (conn->callback)
-  {
-    (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, 0);
-    /* We have to set the callback here even though
-     * the new socket is unknown. Mark the socket as -1. */
-    newconn->callback = conn->callback;
-    newconn->socket = -1;
-  }
-  
-  sys_mbox_post(mbox, newconn);
-  return ERR_OK;
-}
-#endif /* LWIP_TCP */
-
-static void
-do_newconn(struct api_msg_msg *msg)
-{
-   if(msg->conn->pcb.tcp != NULL) {
-   /* This "new" connection already has a PCB allocated. */
-   /* Is this an error condition? Should it be deleted? 
-      We currently just are happy and return. */
-     sys_mbox_post(msg->conn->mbox, NULL);
-     return;
-   }
-
-   msg->conn->err = ERR_OK;
-
-   /* Allocate a PCB for this connection */
-   switch(msg->conn->type) {
-#if LWIP_RAW
-   case NETCONN_RAW:
-      msg->conn->pcb.raw = raw_new(msg->msg.bc.port); /* misusing the port field */
-      raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn);
-     break;
-#endif
-#if LWIP_UDP
-   case NETCONN_UDPLITE:
-      msg->conn->pcb.udp = udp_new();
-      if(msg->conn->pcb.udp == NULL) {
-         msg->conn->err = ERR_MEM;
-         break;
-      }
-      udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE);
-      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
-      break;
-   case NETCONN_UDPNOCHKSUM:
-      msg->conn->pcb.udp = udp_new();
-      if(msg->conn->pcb.udp == NULL) {
-         msg->conn->err = ERR_MEM;
-         break;
-      }
-      udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM);
-      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
-      break;
-   case NETCONN_UDP:
-      msg->conn->pcb.udp = udp_new();
-      if(msg->conn->pcb.udp == NULL) {
-         msg->conn->err = ERR_MEM;
-         break;
-      }
-      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
-      break;
-#endif /* LWIP_UDP */
-#if LWIP_TCP
-   case NETCONN_TCP:
-      msg->conn->pcb.tcp = tcp_new();
-      if(msg->conn->pcb.tcp == NULL) {
-         msg->conn->err = ERR_MEM;
-         break;
-      }
-      setup_tcp(msg->conn);
-      break;
-#endif
-   }
-   
-  
-  sys_mbox_post(msg->conn->mbox, NULL);
-}
-
-
-static void
-do_delconn(struct api_msg_msg *msg)
-{
-  if (msg->conn->pcb.tcp != NULL) {
-    switch (msg->conn->type) {
-#if LWIP_RAW
-    case NETCONN_RAW:
-      raw_remove(msg->conn->pcb.raw);
-      break;
-#endif
-#if LWIP_UDP
-    case NETCONN_UDPLITE:
-      /* FALLTHROUGH */
-    case NETCONN_UDPNOCHKSUM:
-      /* FALLTHROUGH */
-    case NETCONN_UDP:
-      msg->conn->pcb.udp->recv_arg = NULL;
-      udp_remove(msg->conn->pcb.udp);
-      break;
-#endif /* LWIP_UDP */
-#if LWIP_TCP      
-    case NETCONN_TCP:
-      if (msg->conn->pcb.tcp->state == LISTEN) {
-  tcp_arg(msg->conn->pcb.tcp, NULL);
-  tcp_accept(msg->conn->pcb.tcp, NULL);  
-  tcp_close(msg->conn->pcb.tcp);
-      } else {
-  tcp_arg(msg->conn->pcb.tcp, NULL);
-  tcp_sent(msg->conn->pcb.tcp, NULL);
-  tcp_recv(msg->conn->pcb.tcp, NULL);  
-  tcp_poll(msg->conn->pcb.tcp, NULL, 0);
-  tcp_err(msg->conn->pcb.tcp, NULL);
-  if (tcp_close(msg->conn->pcb.tcp) != ERR_OK) {
-    tcp_abort(msg->conn->pcb.tcp);
-  }
-      }
-#endif
-    default:  
-    break;
-    }
-  }
-  /* Trigger select() in socket layer */
-  if (msg->conn->callback)
-  {
-      (*msg->conn->callback)(msg->conn, NETCONN_EVT_RCVPLUS, 0);
-      (*msg->conn->callback)(msg->conn, NETCONN_EVT_SENDPLUS, 0);
-  }
-  
-  if (msg->conn->mbox != SYS_MBOX_NULL) {
-    sys_mbox_post(msg->conn->mbox, NULL);
-  }
-}
-
-static void
-do_bind(struct api_msg_msg *msg)
-{
-  if (msg->conn->pcb.tcp == NULL) {
-    switch (msg->conn->type) {
-#if LWIP_RAW
-    case NETCONN_RAW:
-      msg->conn->pcb.raw = raw_new(msg->msg.bc.port); /* misusing the port field as protocol */
-      raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn);
-      break;
-#endif
-#if LWIP_UDP
-    case NETCONN_UDPLITE:
-      msg->conn->pcb.udp = udp_new();
-      udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE);
-      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
-      break;
-    case NETCONN_UDPNOCHKSUM:
-      msg->conn->pcb.udp = udp_new();
-      udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM);
-      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
-      break;
-    case NETCONN_UDP:
-      msg->conn->pcb.udp = udp_new();
-      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
-      break;
-#endif /* LWIP_UDP */
-#if LWIP_TCP      
-    case NETCONN_TCP:
-      msg->conn->pcb.tcp = tcp_new();
-      setup_tcp(msg->conn);
-#endif /* LWIP_TCP */
-    default:  
-    break;
-    }
-  }
-  switch (msg->conn->type) {
-#if LWIP_RAW
-  case NETCONN_RAW:
-    msg->conn->err = raw_bind(msg->conn->pcb.raw,msg->msg.bc.ipaddr);
-    break;
-#endif
-#if LWIP_UDP
-  case NETCONN_UDPLITE:
-    /* FALLTHROUGH */
-  case NETCONN_UDPNOCHKSUM:
-    /* FALLTHROUGH */
-  case NETCONN_UDP:
-    msg->conn->err = udp_bind(msg->conn->pcb.udp, msg->msg.bc.ipaddr, msg->msg.bc.port);
-    break;
-#endif /* LWIP_UDP */
-#if LWIP_TCP
-  case NETCONN_TCP:
-    msg->conn->err = tcp_bind(msg->conn->pcb.tcp,
-            msg->msg.bc.ipaddr, msg->msg.bc.port);
-#endif /* LWIP_TCP */
-  default:
-    break;
-  }
-  sys_mbox_post(msg->conn->mbox, NULL);
-}
-#if LWIP_TCP
-
-static err_t
-do_connected(void *arg, struct tcp_pcb *pcb, err_t err)
-{
-  struct netconn *conn;
-
-  conn = arg;
-
-  if (conn == NULL) {
-    return ERR_VAL;
-  }
-  
-  conn->err = err;
-  if (conn->type == NETCONN_TCP && err == ERR_OK) {
-    setup_tcp(conn);
-  }    
-  sys_mbox_post(conn->mbox, NULL);
-  return ERR_OK;
-}
-#endif  
-
-static void
-do_connect(struct api_msg_msg *msg)
-{
-  if (msg->conn->pcb.tcp == NULL) {
-    switch (msg->conn->type) {
-#if LWIP_RAW
-    case NETCONN_RAW:
-      msg->conn->pcb.raw = raw_new(msg->msg.bc.port); /* misusing the port field as protocol */
-      raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn);
-      break;
-#endif
-#if LWIP_UDP
-    case NETCONN_UDPLITE:
-      msg->conn->pcb.udp = udp_new();
-      if (msg->conn->pcb.udp == NULL) {
-  msg->conn->err = ERR_MEM;
-  sys_mbox_post(msg->conn->mbox, NULL);
-  return;
-      }
-      udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE);
-      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
-      break;
-    case NETCONN_UDPNOCHKSUM:
-      msg->conn->pcb.udp = udp_new();
-      if (msg->conn->pcb.udp == NULL) {
-  msg->conn->err = ERR_MEM;
-  sys_mbox_post(msg->conn->mbox, NULL);
-  return;
-      }
-      udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM);
-      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
-      break;
-    case NETCONN_UDP:
-      msg->conn->pcb.udp = udp_new();
-      if (msg->conn->pcb.udp == NULL) {
-  msg->conn->err = ERR_MEM;
-  sys_mbox_post(msg->conn->mbox, NULL);
-  return;
-      }
-      udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn);
-      break;
-#endif /* LWIP_UDP */
-#if LWIP_TCP      
-    case NETCONN_TCP:
-      msg->conn->pcb.tcp = tcp_new();      
-      if (msg->conn->pcb.tcp == NULL) {
-  msg->conn->err = ERR_MEM;
-  sys_mbox_post(msg->conn->mbox, NULL);
-  return;
-      }
-#endif
-    default:
-      break;
-    }
-  }
-  switch (msg->conn->type) {
-#if LWIP_RAW
-  case NETCONN_RAW:
-    raw_connect(msg->conn->pcb.raw, msg->msg.bc.ipaddr);
-    sys_mbox_post(msg->conn->mbox, NULL);
-    break;
-#endif
-#if LWIP_UDP
-  case NETCONN_UDPLITE:
-    /* FALLTHROUGH */
-  case NETCONN_UDPNOCHKSUM:
-    /* FALLTHROUGH */
-  case NETCONN_UDP:
-    udp_connect(msg->conn->pcb.udp, msg->msg.bc.ipaddr, msg->msg.bc.port);
-    sys_mbox_post(msg->conn->mbox, NULL);
-    break;
-#endif 
-#if LWIP_TCP      
-  case NETCONN_TCP:
-    /*    tcp_arg(msg->conn->pcb.tcp, msg->conn);*/
-    setup_tcp(msg->conn);
-    tcp_connect(msg->conn->pcb.tcp, msg->msg.bc.ipaddr, msg->msg.bc.port,
-    do_connected);
-    /*tcp_output(msg->conn->pcb.tcp);*/
-#endif
-
-  default:
-    break;
-  }
-}
-
-static void
-do_disconnect(struct api_msg_msg *msg)
-{
-
-  switch (msg->conn->type) {
-#if LWIP_RAW
-  case NETCONN_RAW:
-    /* Do nothing as connecting is only a helper for upper lwip layers */
-    break;
-#endif
-#if LWIP_UDP
-  case NETCONN_UDPLITE:
-    /* FALLTHROUGH */
-  case NETCONN_UDPNOCHKSUM:
-    /* FALLTHROUGH */
-  case NETCONN_UDP:
-    udp_disconnect(msg->conn->pcb.udp);
-    break;
-#endif 
-  case NETCONN_TCP:
-    break;
-  }
-  sys_mbox_post(msg->conn->mbox, NULL);
-}
-
-
-static void
-do_listen(struct api_msg_msg *msg)
-{
-  if (msg->conn->pcb.tcp != NULL) {
-    switch (msg->conn->type) {
-#if LWIP_RAW
-    case NETCONN_RAW:
-      LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: listen RAW: cannot listen for RAW.\n"));
-      break;
-#endif
-#if LWIP_UDP
-    case NETCONN_UDPLITE:
-      /* FALLTHROUGH */
-    case NETCONN_UDPNOCHKSUM:
-      /* FALLTHROUGH */
-    case NETCONN_UDP:
-      LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: listen UDP: cannot listen for UDP.\n"));
-      break;
-#endif /* LWIP_UDP */
-#if LWIP_TCP      
-    case NETCONN_TCP:
-      msg->conn->pcb.tcp = tcp_listen(msg->conn->pcb.tcp);
-      if (msg->conn->pcb.tcp == NULL) {
-  msg->conn->err = ERR_MEM;
-      } else {
-  if (msg->conn->acceptmbox == SYS_MBOX_NULL) {
-    msg->conn->acceptmbox = sys_mbox_new();
-    if (msg->conn->acceptmbox == SYS_MBOX_NULL) {
-      msg->conn->err = ERR_MEM;
-      break;
-    }
-  }
-  tcp_arg(msg->conn->pcb.tcp, msg->conn);
-  tcp_accept(msg->conn->pcb.tcp, accept_function);
-      }
-#endif
-    default:
-      break;
-    }
-  }
-  sys_mbox_post(msg->conn->mbox, NULL);
-}
-
-static void
-do_accept(struct api_msg_msg *msg)
-{
-  if (msg->conn->pcb.tcp != NULL) {
-    switch (msg->conn->type) {
-#if LWIP_RAW
-    case NETCONN_RAW:
-      LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: accept RAW: cannot accept for RAW.\n"));
-      break;
-#endif
-#if LWIP_UDP
-    case NETCONN_UDPLITE:
-      /* FALLTHROUGH */
-    case NETCONN_UDPNOCHKSUM:
-      /* FALLTHROUGH */
-    case NETCONN_UDP:    
-      LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: accept UDP: cannot accept for UDP.\n"));
-      break;
-#endif /* LWIP_UDP */
-    case NETCONN_TCP:
-      break;
-    }
-  }
-}
-
-static void
-do_send(struct api_msg_msg *msg)
-{
-  if (msg->conn->pcb.tcp != NULL) {
-    switch (msg->conn->type) {
-#if LWIP_RAW
-    case NETCONN_RAW:
-      raw_send(msg->conn->pcb.raw, msg->msg.p);
-      break;
-#endif
-#if LWIP_UDP
-    case NETCONN_UDPLITE:
-      /* FALLTHROUGH */
-    case NETCONN_UDPNOCHKSUM:
-      /* FALLTHROUGH */
-    case NETCONN_UDP:
-      udp_send(msg->conn->pcb.udp, msg->msg.p);
-      break;
-#endif /* LWIP_UDP */
-    case NETCONN_TCP:
-      break;
-    }
-  }
-  sys_mbox_post(msg->conn->mbox, NULL);
-}
-
-static void
-do_recv(struct api_msg_msg *msg)
-{
-#if LWIP_TCP
-  if (msg->conn->pcb.tcp != NULL) {
-    if (msg->conn->type == NETCONN_TCP) {
-      tcp_recved(msg->conn->pcb.tcp, msg->msg.len);
-    }
-  }
-#endif  
-  sys_mbox_post(msg->conn->mbox, NULL);
-}
-
-static void
-do_write(struct api_msg_msg *msg)
-{
-#if LWIP_TCP  
-  err_t err;
-#endif  
-  if (msg->conn->pcb.tcp != NULL) {
-    switch (msg->conn->type) {
-#if LWIP_RAW
-    case NETCONN_RAW:
-      msg->conn->err = ERR_VAL;
-      break;
-#endif
-#if LWIP_UDP 
-    case NETCONN_UDPLITE:
-      /* FALLTHROUGH */
-    case NETCONN_UDPNOCHKSUM:
-      /* FALLTHROUGH */
-    case NETCONN_UDP:
-      msg->conn->err = ERR_VAL;
-      break;
-#endif /* LWIP_UDP */
-#if LWIP_TCP 
-    case NETCONN_TCP:      
-      err = tcp_write(msg->conn->pcb.tcp, msg->msg.w.dataptr,
-                      msg->msg.w.len, msg->msg.w.copy);
-      /* This is the Nagle algorithm: inhibit the sending of new TCP
-   segments when new outgoing data arrives from the user if any
-   previously transmitted data on the connection remains
-   unacknowledged. */
-      if(err == ERR_OK && (msg->conn->pcb.tcp->unacked == NULL || (msg->conn->pcb.tcp->flags & TF_NODELAY)) ) {
-  tcp_output(msg->conn->pcb.tcp);
-      }
-      msg->conn->err = err;
-      if (msg->conn->callback)
-          if (err == ERR_OK)
-          {
-              if (tcp_sndbuf(msg->conn->pcb.tcp) <= TCP_SNDLOWAT)
-                  (*msg->conn->callback)(msg->conn, NETCONN_EVT_SENDMINUS, msg->msg.w.len);
-          }
-#endif
-    default:
-      break;
-    }
-  }
-  sys_mbox_post(msg->conn->mbox, NULL);
-}
-
-static void
-do_close(struct api_msg_msg *msg)
-{
-  err_t err;
-
-  err = ERR_OK;
-
-  if (msg->conn->pcb.tcp != NULL) {
-    switch (msg->conn->type) {
-#if LWIP_RAW
-    case NETCONN_RAW:
-      break;
-#endif
-#if LWIP_UDP
-    case NETCONN_UDPLITE:
-      /* FALLTHROUGH */
-    case NETCONN_UDPNOCHKSUM:
-      /* FALLTHROUGH */
-    case NETCONN_UDP:
-      break;
-#endif /* LWIP_UDP */
-#if LWIP_TCP
-    case NETCONN_TCP:
-      if (msg->conn->pcb.tcp->state == LISTEN) {
-  err = tcp_close(msg->conn->pcb.tcp);
-      }
-      msg->conn->err = err;      
-#endif
-    default:      
-      break;
-    }
-  }
-  sys_mbox_post(msg->conn->mbox, NULL);
-}
-
-typedef void (* api_msg_decode)(struct api_msg_msg *msg);
-static api_msg_decode decode[API_MSG_MAX] = {
-  do_newconn,
-  do_delconn,
-  do_bind,
-  do_connect,
-  do_disconnect,
-  do_listen,
-  do_accept,
-  do_send,
-  do_recv,
-  do_write,
-  do_close
-  };
-void
-api_msg_input(struct api_msg *msg)
-{  
-  decode[msg->type](&(msg->msg));
-}
-
-void
-api_msg_post(struct api_msg *msg)
-{
-  tcpip_apimsg(msg);
-}
-
-
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/api/err.c b/Demo/lwIP_MCF5235_GCC/lwip/src/api/err.c
deleted file mode 100644
index b582d88a2..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/api/err.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-
-#include "lwip/err.h"
-
-#ifdef LWIP_DEBUG
-
-static char *err_strerr[] = {"Ok.",
-           "Out of memory error.",
-           "Buffer error.",
-           "Connection aborted.",
-           "Connection reset.",
-           "Connection closed.",
-           "Not connected.",
-           "Illegal value.",
-           "Illegal argument.",
-           "Routing problem.",
-           "Address in use."
-};
-
-
-char *
-lwip_strerr(err_t err)
-{
-  return err_strerr[-err];
-
-}
-
-
-#endif /* LWIP_DEBUG */
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/api/sockets.c b/Demo/lwIP_MCF5235_GCC/lwip/src/api/sockets.c
deleted file mode 100644
index 290a7b737..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/api/sockets.c
+++ /dev/null
@@ -1,1362 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels 
- *
- * Improved by Marc Boucher  and David Haas 
- *
- */
-
-#include 
-#include 
-
-#include "lwip/opt.h"
-#include "lwip/api.h"
-#include "lwip/arch.h"
-#include "lwip/sys.h"
-
-#include "lwip/sockets.h"
-
-#define NUM_SOCKETS MEMP_NUM_NETCONN
-
-struct lwip_socket {
-  struct netconn *conn;
-  struct netbuf *lastdata;
-  u16_t lastoffset;
-  u16_t rcvevent;
-  u16_t sendevent;
-  u16_t  flags;
-  int err;
-};
-
-struct lwip_select_cb
-{
-    struct lwip_select_cb *next;
-    fd_set *readset;
-    fd_set *writeset;
-    fd_set *exceptset;
-    int sem_signalled;
-    sys_sem_t sem;
-};
-
-static struct lwip_socket sockets[NUM_SOCKETS];
-static struct lwip_select_cb *select_cb_list = 0;
-
-static sys_sem_t socksem = 0;
-static sys_sem_t selectsem = 0;
-
-static void
-event_callback(struct netconn *conn, enum netconn_evt evt, u16_t len);
-
-static int err_to_errno_table[11] = {
-    0,      /* ERR_OK    0      No error, everything OK. */
-    ENOMEM,    /* ERR_MEM  -1      Out of memory error.     */
-    ENOBUFS,    /* ERR_BUF  -2      Buffer error.            */
-    ECONNABORTED,  /* ERR_ABRT -3      Connection aborted.      */
-    ECONNRESET,    /* ERR_RST  -4      Connection reset.        */
-    ESHUTDOWN,    /* ERR_CLSD -5      Connection closed.       */
-    ENOTCONN,    /* ERR_CONN -6      Not connected.           */
-    EINVAL,    /* ERR_VAL  -7      Illegal value.           */
-    EIO,    /* ERR_ARG  -8      Illegal argument.        */
-    EHOSTUNREACH,  /* ERR_RTE  -9      Routing problem.         */
-    EADDRINUSE    /* ERR_USE  -10     Address in use.          */
-};
-
-#define ERR_TO_ERRNO_TABLE_SIZE \
-  (sizeof(err_to_errno_table)/sizeof(err_to_errno_table[0]))
-
-#define err_to_errno(err) \
-  (-(err) >= 0 && -(err) < ERR_TO_ERRNO_TABLE_SIZE ? \
-    err_to_errno_table[-(err)] : EIO)
-
-#ifdef ERRNO
-#define set_errno(err) errno = (err)
-#else
-#define set_errno(err)
-#endif
-
-#define sock_set_errno(sk, e) do { \
-      sk->err = (e); \
-      set_errno(sk->err); \
-} while (0)
-
-
-static struct lwip_socket *
-get_socket(int s)
-{
-  struct lwip_socket *sock;
-
-  if ((s < 0) || (s > NUM_SOCKETS)) {
-    LWIP_DEBUGF(SOCKETS_DEBUG, ("get_socket(%d): invalid\n", s));
-    set_errno(EBADF);
-    return NULL;
-  }
-
-  sock = &sockets[s];
-
-  if (!sock->conn) {
-    LWIP_DEBUGF(SOCKETS_DEBUG, ("get_socket(%d): not active\n", s));
-    set_errno(EBADF);
-    return NULL;
-  }
-
-  return sock;
-}
-
-static int
-alloc_socket(struct netconn *newconn)
-{
-  int i;
-
-  if (!socksem)
-      socksem = sys_sem_new(1);
-
-  /* Protect socket array */
-  sys_sem_wait(socksem);
-
-  /* allocate a new socket identifier */
-  for(i = 0; i < NUM_SOCKETS; ++i) {
-    if (!sockets[i].conn) {
-      sockets[i].conn = newconn;
-      sockets[i].lastdata = NULL;
-      sockets[i].lastoffset = 0;
-      sockets[i].rcvevent = 0;
-      sockets[i].sendevent = 1; /* TCP send buf is empty */
-      sockets[i].flags = 0;
-      sockets[i].err = 0;
-      sys_sem_signal(socksem);
-      return i;
-    }
-  }
-  sys_sem_signal(socksem);
-  return -1;
-}
-
-int
-lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen)
-{
-  struct lwip_socket *sock;
-  struct netconn *newconn;
-  struct ip_addr naddr;
-  u16_t port;
-  int newsock;
-  struct sockaddr_in sin;
-
-  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d)...\n", s));
-  sock = get_socket(s);
-  if (!sock) {
-    set_errno(EBADF);
-    return -1;
-  }
-
-  newconn = netconn_accept(sock->conn);
-
-  /* get the IP address and port of the remote host */
-  netconn_peer(newconn, &naddr, &port);
-
-  memset(&sin, 0, sizeof(sin));
-  sin.sin_len = sizeof(sin);
-  sin.sin_family = AF_INET;
-  sin.sin_port = htons(port);
-  sin.sin_addr.s_addr = naddr.addr;
-
-  if (*addrlen > sizeof(sin))
-      *addrlen = sizeof(sin);
-
-  memcpy(addr, &sin, *addrlen);
-
-  newsock = alloc_socket(newconn);
-  if (newsock == -1) {
-    netconn_delete(newconn);
-  sock_set_errno(sock, ENOBUFS);
-  return -1;
-  }
-  newconn->callback = event_callback;
-  sock = get_socket(newsock);
-
-  sys_sem_wait(socksem);
-  sock->rcvevent += -1 - newconn->socket;
-  newconn->socket = newsock;
-  sys_sem_signal(socksem);
-
-  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d) returning new sock=%d addr=", s, newsock));
-  ip_addr_debug_print(SOCKETS_DEBUG, &naddr);
-  LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u\n", port));
-
-  sock_set_errno(sock, 0);
-  return newsock;
-}
-
-int
-lwip_bind(int s, struct sockaddr *name, socklen_t namelen)
-{
-  struct lwip_socket *sock;
-  struct ip_addr local_addr;
-  u16_t local_port;
-  err_t err;
-
-  sock = get_socket(s);
-  if (!sock) {
-    set_errno(EBADF);
-    return -1;
-  }
-
-  local_addr.addr = ((struct sockaddr_in *)name)->sin_addr.s_addr;
-  local_port = ((struct sockaddr_in *)name)->sin_port;
-
-  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d, addr=", s));
-  ip_addr_debug_print(SOCKETS_DEBUG, &local_addr);
-  LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u)\n", ntohs(local_port)));
-
-  err = netconn_bind(sock->conn, &local_addr, ntohs(local_port));
-
-  if (err != ERR_OK) {
-    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d) failed, err=%d\n", s, err));
-    sock_set_errno(sock, err_to_errno(err));
-    return -1;
-  }
-
-  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d) succeeded\n", s));
-  sock_set_errno(sock, 0);
-  return 0;
-}
-
-int
-lwip_close(int s)
-{
-  struct lwip_socket *sock;
-
-  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_close(%d)\n", s));
-  if (!socksem)
-      socksem = sys_sem_new(1);
-
-  /* We cannot allow multiple closes of the same socket. */
-  sys_sem_wait(socksem);
-
-  sock = get_socket(s);
-  if (!sock) {
-      sys_sem_signal(socksem);
-      set_errno(EBADF);
-      return -1;
-  }
-
-  netconn_delete(sock->conn);
-  if (sock->lastdata) {
-    netbuf_delete(sock->lastdata);
-  }
-  sock->lastdata = NULL;
-  sock->lastoffset = 0;
-  sock->conn = NULL;
-  sys_sem_signal(socksem);
-  sock_set_errno(sock, 0);
-  return 0;
-}
-
-int
-lwip_connect(int s, struct sockaddr *name, socklen_t namelen)
-{
-  struct lwip_socket *sock;
-  err_t err;
-
-  sock = get_socket(s);
-  if (!sock) {
-    set_errno(EBADF);
-    return -1;
-  }
-
-  if (((struct sockaddr_in *)name)->sin_family == AF_UNSPEC) {
-    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d, AF_UNSPEC)\n", s));
-    err = netconn_disconnect(sock->conn);
-  } else {
-    struct ip_addr remote_addr;
-    u16_t remote_port;
-
-    remote_addr.addr = ((struct sockaddr_in *)name)->sin_addr.s_addr;
-    remote_port = ((struct sockaddr_in *)name)->sin_port;
-
-    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d, addr=", s));
-    ip_addr_debug_print(SOCKETS_DEBUG, &remote_addr);
-    LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u)\n", ntohs(remote_port)));
-
-    err = netconn_connect(sock->conn, &remote_addr, ntohs(remote_port));
-   }
-
-  if (err != ERR_OK) {
-    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d) failed, err=%d\n", s, err));
-    sock_set_errno(sock, err_to_errno(err));
-    return -1;
-  }
-
-  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d) succeeded\n", s));
-  sock_set_errno(sock, 0);
-  return 0;
-}
-
-int
-lwip_listen(int s, int backlog)
-{
-  struct lwip_socket *sock;
-  err_t err;
-
-  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_listen(%d, backlog=%d)\n", s, backlog));
-  sock = get_socket(s);
-  if (!sock) {
-    set_errno(EBADF);
-    return -1;
-  }
-
-  err = netconn_listen(sock->conn);
-
-  if (err != ERR_OK) {
-    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_listen(%d) failed, err=%d\n", s, err));
-    sock_set_errno(sock, err_to_errno(err));
-    return -1;
-  }
-
-  sock_set_errno(sock, 0);
-  return 0;
-}
-
-int
-lwip_recvfrom(int s, void *mem, int len, unsigned int flags,
-        struct sockaddr *from, socklen_t *fromlen)
-{
-  struct lwip_socket *sock;
-  struct netbuf *buf;
-  u16_t buflen, copylen;
-  struct ip_addr *addr;
-  u16_t port;
-
-
-  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d, %p, %d, 0x%x, ..)\n", s, mem, len, flags));
-  sock = get_socket(s);
-  if (!sock) {
-    set_errno(EBADF);
-    return -1;
-  }
-
-  /* Check if there is data left from the last recv operation. */
-  if (sock->lastdata) {
-    buf = sock->lastdata;
-  } else {
-    /* If this is non-blocking call, then check first */
-    if (((flags & MSG_DONTWAIT) || (sock->flags & O_NONBLOCK))
-  && !sock->rcvevent)
-    {
-      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): returning EWOULDBLOCK\n", s));
-      sock_set_errno(sock, EWOULDBLOCK);
-      return -1;
-    }
-
-    /* No data was left from the previous operation, so we try to get
-       some from the network. */
-    buf = netconn_recv(sock->conn);
-
-    if (!buf) {
-      /* We should really do some error checking here. */
-      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): buf == NULL!\n", s));
-      sock_set_errno(sock, 0);
-      return 0;
-    }
-  }
-
-  buflen = netbuf_len(buf);
-
-  buflen -= sock->lastoffset;
-
-  if (len > buflen) {
-    copylen = buflen;
-  } else {
-    copylen = len;
-  }
-
-  /* copy the contents of the received buffer into
-     the supplied memory pointer mem */
-  netbuf_copy_partial(buf, mem, copylen, sock->lastoffset);
-
-  /* Check to see from where the data was. */
-  if (from && fromlen) {
-    struct sockaddr_in sin;
-
-    addr = netbuf_fromaddr(buf);
-    port = netbuf_fromport(buf);
-
-    memset(&sin, 0, sizeof(sin));
-    sin.sin_len = sizeof(sin);
-    sin.sin_family = AF_INET;
-    sin.sin_port = htons(port);
-    sin.sin_addr.s_addr = addr->addr;
-
-    if (*fromlen > sizeof(sin))
-      *fromlen = sizeof(sin);
-
-    memcpy(from, &sin, *fromlen);
-
-    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): addr=", s));
-    ip_addr_debug_print(SOCKETS_DEBUG, addr);
-    LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u len=%u\n", port, copylen));
-  } else {
-#if SOCKETS_DEBUG
-    addr = netbuf_fromaddr(buf);
-    port = netbuf_fromport(buf);
-
-    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): addr=", s));
-    ip_addr_debug_print(SOCKETS_DEBUG, addr);
-    LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u len=%u\n", port, copylen));
-#endif
-
-  }
-
-  /* If this is a TCP socket, check if there is data left in the
-     buffer. If so, it should be saved in the sock structure for next
-     time around. */
-  if (netconn_type(sock->conn) == NETCONN_TCP && buflen - copylen > 0) {
-    sock->lastdata = buf;
-    sock->lastoffset += copylen;
-  } else {
-    sock->lastdata = NULL;
-    sock->lastoffset = 0;
-    netbuf_delete(buf);
-  }
-
-
-  sock_set_errno(sock, 0);
-  return copylen;
-}
-
-int
-lwip_read(int s, void *mem, int len)
-{
-  return lwip_recvfrom(s, mem, len, 0, NULL, NULL);
-}
-
-int
-lwip_recv(int s, void *mem, int len, unsigned int flags)
-{
-  return lwip_recvfrom(s, mem, len, flags, NULL, NULL);
-}
-
-int
-lwip_send(int s, void *data, int size, unsigned int flags)
-{
-  struct lwip_socket *sock;
-  struct netbuf *buf;
-  err_t err;
-
-  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d, data=%p, size=%d, flags=0x%x)\n", s, data, size, flags));
-
-  sock = get_socket(s);
-  if (!sock) {
-    set_errno(EBADF);
-    return -1;
-  }
-
-  switch (netconn_type(sock->conn)) {
-  case NETCONN_RAW:
-  case NETCONN_UDP:
-  case NETCONN_UDPLITE:
-  case NETCONN_UDPNOCHKSUM:
-    /* create a buffer */
-    buf = netbuf_new();
-
-    if (!buf) {
-      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d) ENOBUFS\n", s));
-      sock_set_errno(sock, ENOBUFS);
-      return -1;
-    }
-
-    /* make the buffer point to the data that should
-       be sent */
-    netbuf_ref(buf, data, size);
-
-    /* send the data */
-    err = netconn_send(sock->conn, buf);
-
-    /* deallocated the buffer */
-    netbuf_delete(buf);
-    break;
-  case NETCONN_TCP:
-    err = netconn_write(sock->conn, data, size, NETCONN_COPY);
-    break;
-  default:
-    err = ERR_ARG;
-    break;
-  }
-  if (err != ERR_OK) {
-    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d) err=%d\n", s, err));
-    sock_set_errno(sock, err_to_errno(err));
-    return -1;
-  }
-
-  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d) ok size=%d\n", s, size));
-  sock_set_errno(sock, 0);
-  return size;
-}
-
-int
-lwip_sendto(int s, void *data, int size, unsigned int flags,
-       struct sockaddr *to, socklen_t tolen)
-{
-  struct lwip_socket *sock;
-  struct ip_addr remote_addr, addr;
-  u16_t remote_port, port;
-  int ret,connected;
-
-  sock = get_socket(s);
-  if (!sock) {
-    set_errno(EBADF);
-    return -1;
-  }
-
-  /* get the peer if currently connected */
-  connected = (netconn_peer(sock->conn, &addr, &port) == ERR_OK);
-
-  remote_addr.addr = ((struct sockaddr_in *)to)->sin_addr.s_addr;
-  remote_port = ((struct sockaddr_in *)to)->sin_port;
-
-  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_sendto(%d, data=%p, size=%d, flags=0x%x to=", s, data, size, flags));
-  ip_addr_debug_print(SOCKETS_DEBUG, &remote_addr);
-  LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u\n", ntohs(remote_port)));
-
-  netconn_connect(sock->conn, &remote_addr, ntohs(remote_port));
-
-  ret = lwip_send(s, data, size, flags);
-
-  /* reset the remote address and port number
-     of the connection */
-  if (connected)
-    netconn_connect(sock->conn, &addr, port);
-  else
-  netconn_disconnect(sock->conn);
-  return ret;
-}
-
-int
-lwip_socket(int domain, int type, int protocol)
-{
-  struct netconn *conn;
-  int i;
-
-  /* create a netconn */
-  switch (type) {
-  case SOCK_RAW:
-    conn = netconn_new_with_proto_and_callback(NETCONN_RAW, protocol, event_callback);
-    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_RAW, %d) = ", domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol));
-    break;
-  case SOCK_DGRAM:
-    conn = netconn_new_with_callback(NETCONN_UDP, event_callback);
-    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_DGRAM, %d) = ", domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol));
-    break;
-  case SOCK_STREAM:
-    conn = netconn_new_with_callback(NETCONN_TCP, event_callback);
-    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_STREAM, %d) = ", domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol));
-    break;
-  default:
-    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%d, %d/UNKNOWN, %d) = -1\n", domain, type, protocol));
-    set_errno(EINVAL);
-    return -1;
-  }
-
-  if (!conn) {
-    LWIP_DEBUGF(SOCKETS_DEBUG, ("-1 / ENOBUFS (could not create netconn)\n"));
-    set_errno(ENOBUFS);
-    return -1;
-  }
-
-  i = alloc_socket(conn);
-
-  if (i == -1) {
-    netconn_delete(conn);
-  set_errno(ENOBUFS);
-  return -1;
-  }
-  conn->socket = i;
-  LWIP_DEBUGF(SOCKETS_DEBUG, ("%d\n", i));
-  set_errno(0);
-  return i;
-}
-
-int
-lwip_write(int s, void *data, int size)
-{
-   return lwip_send(s, data, size, 0);
-}
-
-
-static int
-lwip_selscan(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset)
-{
-    int i, nready = 0;
-    fd_set lreadset, lwriteset, lexceptset;
-    struct lwip_socket *p_sock;
-
-    FD_ZERO(&lreadset);
-    FD_ZERO(&lwriteset);
-    FD_ZERO(&lexceptset);
-
-    /* Go through each socket in each list to count number of sockets which
-       currently match */
-    for(i = 0; i < maxfdp1; i++)
-    {
-        if (FD_ISSET(i, readset))
-        {
-            /* See if netconn of this socket is ready for read */
-            p_sock = get_socket(i);
-            if (p_sock && (p_sock->lastdata || p_sock->rcvevent))
-            {
-                FD_SET(i, &lreadset);
-		LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for reading\n", i));
-                nready++;
-            }
-        }
-        if (FD_ISSET(i, writeset))
-        {
-            /* See if netconn of this socket is ready for write */
-            p_sock = get_socket(i);
-            if (p_sock && p_sock->sendevent)
-            {
-                FD_SET(i, &lwriteset);
-		LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for writing\n", i));
-                nready++;
-            }
-        }
-    }
-    *readset = lreadset;
-    *writeset = lwriteset;
-    FD_ZERO(exceptset);
-
-    return nready;
-}
-
-
-
-int
-lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset,
-               struct timeval *timeout)
-{
-    int i;
-    int nready;
-    fd_set lreadset, lwriteset, lexceptset;
-    u32_t msectimeout;
-    struct lwip_select_cb select_cb;
-    struct lwip_select_cb *p_selcb;
-
-    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select(%d, %p, %p, %p, tvsec=%ld tvusec=%ld)\n", maxfdp1, (void *)readset, (void *) writeset, (void *) exceptset, timeout ? timeout->tv_sec : -1L, timeout ? timeout->tv_usec : -1L));
-
-    select_cb.next = 0;
-    select_cb.readset = readset;
-    select_cb.writeset = writeset;
-    select_cb.exceptset = exceptset;
-    select_cb.sem_signalled = 0;
-
-    /* Protect ourselves searching through the list */
-    if (!selectsem)
-        selectsem = sys_sem_new(1);
-    sys_sem_wait(selectsem);
-
-    if (readset)
-        lreadset = *readset;
-    else
-        FD_ZERO(&lreadset);
-    if (writeset)
-        lwriteset = *writeset;
-    else
-        FD_ZERO(&lwriteset);
-    if (exceptset)
-        lexceptset = *exceptset;
-    else
-        FD_ZERO(&lexceptset);
-
-    /* Go through each socket in each list to count number of sockets which
-       currently match */
-    nready = lwip_selscan(maxfdp1, &lreadset, &lwriteset, &lexceptset);
-
-    /* If we don't have any current events, then suspend if we are supposed to */
-    if (!nready)
-    {
-        if (timeout && timeout->tv_sec == 0 && timeout->tv_usec == 0)
-        {
-            sys_sem_signal(selectsem);
-            if (readset)
-                FD_ZERO(readset);
-            if (writeset)
-                FD_ZERO(writeset);
-            if (exceptset)
-                FD_ZERO(exceptset);
-
-	    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: no timeout, returning 0\n"));
-	    set_errno(0);
-
-            return 0;
-        }
-
-        /* add our semaphore to list */
-        /* We don't actually need any dynamic memory. Our entry on the
-         * list is only valid while we are in this function, so it's ok
-         * to use local variables */
-
-        select_cb.sem = sys_sem_new(0);
-        /* Note that we are still protected */
-        /* Put this select_cb on top of list */
-        select_cb.next = select_cb_list;
-        select_cb_list = &select_cb;
-
-        /* Now we can safely unprotect */
-        sys_sem_signal(selectsem);
-
-        /* Now just wait to be woken */
-        if (timeout == 0)
-            /* Wait forever */
-            msectimeout = 0;
-        else
-            msectimeout =  ((timeout->tv_sec * 1000) + ((timeout->tv_usec + 500)/1000));
-
-        i = sys_sem_wait_timeout(select_cb.sem, msectimeout);
-
-        /* Take us off the list */
-        sys_sem_wait(selectsem);
-        if (select_cb_list == &select_cb)
-            select_cb_list = select_cb.next;
-        else
-            for (p_selcb = select_cb_list; p_selcb; p_selcb = p_selcb->next)
-                if (p_selcb->next == &select_cb)
-                {
-                    p_selcb->next = select_cb.next;
-                    break;
-                }
-
-        sys_sem_signal(selectsem);
-
-        sys_sem_free(select_cb.sem);
-        if (i == 0)             /* Timeout */
-        {
-            if (readset)
-                FD_ZERO(readset);
-            if (writeset)
-                FD_ZERO(writeset);
-            if (exceptset)
-                FD_ZERO(exceptset);
-
-	    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: timeout expired\n"));
-	    set_errno(0);
-
-            return 0;
-        }
-
-        if (readset)
-            lreadset = *readset;
-        else
-            FD_ZERO(&lreadset);
-        if (writeset)
-            lwriteset = *writeset;
-        else
-            FD_ZERO(&lwriteset);
-        if (exceptset)
-            lexceptset = *exceptset;
-        else
-            FD_ZERO(&lexceptset);
-
-        /* See what's set */
-        nready = lwip_selscan(maxfdp1, &lreadset, &lwriteset, &lexceptset);
-    }
-    else
-        sys_sem_signal(selectsem);
-
-    if (readset)
-        *readset = lreadset;
-    if (writeset)
-        *writeset = lwriteset;
-    if (exceptset)
-        *exceptset = lexceptset;
-
-    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: nready=%d\n", nready));
-    set_errno(0);
-
-    return nready;
-}
-
-
-static void
-event_callback(struct netconn *conn, enum netconn_evt evt, u16_t len)
-{
-    int s;
-    struct lwip_socket *sock;
-    struct lwip_select_cb *scb;
-
-    /* Get socket */
-    if (conn)
-    {
-        s = conn->socket;
-        if (s < 0)
-        {
-            /* Data comes in right away after an accept, even though
-             * the server task might not have created a new socket yet.
-             * Just count down (or up) if that's the case and we
-             * will use the data later. Note that only receive events
-             * can happen before the new socket is set up. */
-            if (evt == NETCONN_EVT_RCVPLUS)
-                conn->socket--;
-            return;
-        }
-
-        sock = get_socket(s);
-        if (!sock)
-            return;
-    }
-    else
-        return;
-
-    if (!selectsem)
-        selectsem = sys_sem_new(1);
-
-    sys_sem_wait(selectsem);
-    /* Set event as required */
-    switch (evt)
-    {
-      case NETCONN_EVT_RCVPLUS:
-        sock->rcvevent++;
-        break;
-      case NETCONN_EVT_RCVMINUS:
-        sock->rcvevent--;
-        break;
-      case NETCONN_EVT_SENDPLUS:
-        sock->sendevent = 1;
-        break;
-      case NETCONN_EVT_SENDMINUS:
-        sock->sendevent = 0;
-        break;
-    }
-    sys_sem_signal(selectsem);
-
-    /* Now decide if anyone is waiting for this socket */
-    /* NOTE: This code is written this way to protect the select link list
-       but to avoid a deadlock situation by releasing socksem before
-       signalling for the select. This means we need to go through the list
-       multiple times ONLY IF a select was actually waiting. We go through
-       the list the number of waiting select calls + 1. This list is
-       expected to be small. */
-    while (1)
-    {
-        sys_sem_wait(selectsem);
-        for (scb = select_cb_list; scb; scb = scb->next)
-        {
-            if (scb->sem_signalled == 0)
-            {
-                /* Test this select call for our socket */
-                if (scb->readset && FD_ISSET(s, scb->readset))
-                    if (sock->rcvevent)
-                        break;
-                if (scb->writeset && FD_ISSET(s, scb->writeset))
-                    if (sock->sendevent)
-                        break;
-            }
-        }
-        if (scb)
-        {
-            scb->sem_signalled = 1;
-            sys_sem_signal(selectsem);
-            sys_sem_signal(scb->sem);
-        } else {
-            sys_sem_signal(selectsem);
-            break;
-        }
-    }
-
-}
-
-
-
-
-int lwip_shutdown(int s, int how)
-{
-  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_shutdown(%d, how=%d)\n", s, how));
-  return lwip_close(s); /* XXX temporary hack until proper implementation */
-}
-
-int lwip_getpeername (int s, struct sockaddr *name, socklen_t *namelen)
-{
-  struct lwip_socket *sock;
-  struct sockaddr_in sin;
-  struct ip_addr naddr;
-
-  sock = get_socket(s);
-  if (!sock) {
-    set_errno(EBADF);
-    return -1;
-  }
-
-  memset(&sin, 0, sizeof(sin));
-  sin.sin_len = sizeof(sin);
-  sin.sin_family = AF_INET;
-
-  /* get the IP address and port of the remote host */
-  netconn_peer(sock->conn, &naddr, &sin.sin_port);
-
-  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getpeername(%d, addr=", s));
-  ip_addr_debug_print(SOCKETS_DEBUG, &naddr);
-  LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%d)\n", sin.sin_port));
-
-  sin.sin_port = htons(sin.sin_port);
-  sin.sin_addr.s_addr = naddr.addr;
-
-  if (*namelen > sizeof(sin))
-      *namelen = sizeof(sin);
-
-  memcpy(name, &sin, *namelen);
-  sock_set_errno(sock, 0);
-  return 0;
-}
-
-int lwip_getsockname (int s, struct sockaddr *name, socklen_t *namelen)
-{
-  struct lwip_socket *sock;
-  struct sockaddr_in sin;
-  struct ip_addr *naddr;
-
-  sock = get_socket(s);
-  if (!sock) {
-    set_errno(EBADF);
-    return -1;
-  }
-
-  memset(&sin, 0, sizeof(sin));
-  sin.sin_len = sizeof(sin);
-  sin.sin_family = AF_INET;
-
-  /* get the IP address and port of the remote host */
-  netconn_addr(sock->conn, &naddr, &sin.sin_port);
-
-  LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockname(%d, addr=", s));
-  ip_addr_debug_print(SOCKETS_DEBUG, naddr);
-  LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%d)\n", sin.sin_port));
-
-  sin.sin_port = htons(sin.sin_port);
-  sin.sin_addr.s_addr = naddr->addr;
-
-  if (*namelen > sizeof(sin))
-      *namelen = sizeof(sin);
-
-  memcpy(name, &sin, *namelen);
-  sock_set_errno(sock, 0);
-  return 0;
-}
-
-int lwip_getsockopt (int s, int level, int optname, void *optval, socklen_t *optlen)
-{
-  int err = 0;
-  struct lwip_socket *sock = get_socket(s);
-
-  if(!sock) {
-   	set_errno(EBADF);
-    return -1;
-  }
-
-  if( NULL == optval || NULL == optlen ) {
-    sock_set_errno( sock, EFAULT );
-    return -1;
-  }
-
-  /* Do length and type checks for the various options first, to keep it readable. */
-  switch( level ) {
-   
-/* Level: SOL_SOCKET */
-  case SOL_SOCKET:
-      switch(optname) {
-         
-      case SO_ACCEPTCONN:
-      case SO_BROADCAST:
-      /* UNIMPL case SO_DEBUG: */
-      /* UNIMPL case SO_DONTROUTE: */
-      case SO_ERROR:
-      case SO_KEEPALIVE:
-      /* UNIMPL case SO_OOBINLINE: */
-      /* UNIMPL case SO_RCVBUF: */
-      /* UNIMPL case SO_SNDBUF: */
-      /* UNIMPL case SO_RCVLOWAT: */
-      /* UNIMPL case SO_SNDLOWAT: */
-#if SO_REUSE
-      case SO_REUSEADDR:
-      case SO_REUSEPORT:
-#endif /* SO_REUSE */
-      case SO_TYPE:
-      /* UNIMPL case SO_USELOOPBACK: */
-        if( *optlen < sizeof(int) ) {
-          err = EINVAL;
-        }
-          break;
-
-      default:
-        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, UNIMPL: optname=0x%x, ..)\n", s, optname));
-        err = ENOPROTOOPT;
-      }  /* switch */
-      break;
-                     
-/* Level: IPPROTO_IP */
-  case IPPROTO_IP:
-      switch(optname) {
-      /* UNIMPL case IP_HDRINCL: */
-      /* UNIMPL case IP_RCVDSTADDR: */
-      /* UNIMPL case IP_RCVIF: */
-      case IP_TTL:
-      case IP_TOS:
-        if( *optlen < sizeof(int) ) {
-          err = EINVAL;
-        }
-        break;
-
-      default:
-        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, UNIMPL: optname=0x%x, ..)\n", s, optname));
-        err = ENOPROTOOPT;
-      }  /* switch */
-      break;
-         
-/* Level: IPPROTO_TCP */
-  case IPPROTO_TCP:
-      if( *optlen < sizeof(int) ) {
-        err = EINVAL;
-        break;
-    }
-      
-      /* If this is no TCP socket, ignore any options. */
-      if ( sock->conn->type != NETCONN_TCP ) return 0;
-
-      switch( optname ) {
-      case TCP_NODELAY:
-      case TCP_KEEPALIVE:
-        break;
-         
-      default:
-        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, UNIMPL: optname=0x%x, ..)\n", s, optname));
-        err = ENOPROTOOPT;
-      }  /* switch */
-      break;
-
-/* UNDEFINED LEVEL */
-  default:
-      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, level=0x%x, UNIMPL: optname=0x%x, ..)\n", s, level, optname));
-      err = ENOPROTOOPT;
-  }  /* switch */
-
-   
-  if( 0 != err ) {
-    sock_set_errno(sock, err);
-    return -1;
-  }
-   
-
-
-  /* Now do the actual option processing */
-
-  switch(level) {
-   
-/* Level: SOL_SOCKET */
-  case SOL_SOCKET:
-    switch( optname ) {
-
-    /* The option flags */
-    case SO_ACCEPTCONN:
-    case SO_BROADCAST:
-    /* UNIMPL case SO_DEBUG: */
-    /* UNIMPL case SO_DONTROUTE: */
-    case SO_KEEPALIVE:
-    /* UNIMPL case SO_OOBINCLUDE: */
-#if SO_REUSE
-    case SO_REUSEADDR:
-    case SO_REUSEPORT:
-#endif /* SO_REUSE */
-    /*case SO_USELOOPBACK: UNIMPL */
-      *(int*)optval = sock->conn->pcb.tcp->so_options & optname;
-      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, optname=0x%x, ..) = %s\n", s, optname, (*(int*)optval?"on":"off")));
-      break;
-
-    case SO_TYPE:
-      switch (sock->conn->type) {
-      case NETCONN_RAW:
-        *(int*)optval = SOCK_RAW;
-        break;
-      case NETCONN_TCP:
-        *(int*)optval = SOCK_STREAM;
-        break;
-      case NETCONN_UDP:
-      case NETCONN_UDPLITE:
-      case NETCONN_UDPNOCHKSUM:
-        *(int*)optval = SOCK_DGRAM;
-        break;
-      default: /* unrecognized socket type */
-        *(int*)optval = sock->conn->type;
-        LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_TYPE): unrecognized socket type %d\n", s, *(int *)optval));
-      }  /* switch */
-      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_TYPE) = %d\n", s, *(int *)optval));
-      break;
-
-    case SO_ERROR:
-      *(int *)optval = sock->err;
-      sock->err = 0;
-      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_ERROR) = %d\n", s, *(int *)optval));
-      break;
-    }  /* switch */
-    break;
-
-/* Level: IPPROTO_IP */
-  case IPPROTO_IP:
-    switch( optname ) {
-    case IP_TTL:
-      *(int*)optval = sock->conn->pcb.tcp->ttl;
-      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_TTL) = %d\n", s, *(int *)optval));
-      break;
-    case IP_TOS:
-      *(int*)optval = sock->conn->pcb.tcp->tos;
-      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_TOS) = %d\n", s, *(int *)optval));
-      break;
-    }  /* switch */
-    break;
-
-/* Level: IPPROTO_TCP */
-  case IPPROTO_TCP:
-    switch( optname ) {
-    case TCP_NODELAY:
-      *(int*)optval = (sock->conn->pcb.tcp->flags & TF_NODELAY);
-      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, TCP_NODELAY) = %s\n", s, (*(int*)optval)?"on":"off") );
-      break;
-    case TCP_KEEPALIVE:
-      *(int*)optval = (int)sock->conn->pcb.tcp->keepalive;
-      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, TCP_KEEPALIVE) = %d\n", s, *(int *)optval));
-      break;
-    }  /* switch */
-    break;
-  }
-
-
-  sock_set_errno(sock, err);
-  return err ? -1 : 0;
-}
-
-int lwip_setsockopt (int s, int level, int optname, const void *optval, socklen_t optlen)
-{
-  struct lwip_socket *sock = get_socket(s);
-  int err = 0;
-
-  if(!sock) {
-   	set_errno(EBADF);
-    return -1;
-  }
-
-  if( NULL == optval ) {
-    sock_set_errno( sock, EFAULT );
-    return -1;
-  }
-
-
-  /* Do length and type checks for the various options first, to keep it readable. */
-  switch( level ) {
-
-/* Level: SOL_SOCKET */
-  case SOL_SOCKET:
-    switch(optname) {
-
-    case SO_BROADCAST:
-    /* UNIMPL case SO_DEBUG: */
-    /* UNIMPL case SO_DONTROUTE: */
-    case SO_KEEPALIVE:
-    /* UNIMPL case SO_OOBINLINE: */
-    /* UNIMPL case SO_RCVBUF: */
-    /* UNIMPL case SO_SNDBUF: */
-    /* UNIMPL case SO_RCVLOWAT: */
-    /* UNIMPL case SO_SNDLOWAT: */
-#if SO_REUSE
-    case SO_REUSEADDR:
-    case SO_REUSEPORT:
-#endif /* SO_REUSE */
-    /* UNIMPL case SO_USELOOPBACK: */
-      if( optlen < sizeof(int) ) {
-        err = EINVAL;
-      }
-      break;
-    default:
-      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, SOL_SOCKET, UNIMPL: optname=0x%x, ..)\n", s, optname));
-      err = ENOPROTOOPT;
-    }  /* switch */
-    break;
-
-/* Level: IPPROTO_IP */
-  case IPPROTO_IP:
-    switch(optname) {
-    /* UNIMPL case IP_HDRINCL: */
-    /* UNIMPL case IP_RCVDSTADDR: */
-    /* UNIMPL case IP_RCVIF: */
-    case IP_TTL:
-    case IP_TOS:
-      if( optlen < sizeof(int) ) {
-        err = EINVAL;
-      }
-        break;
-      default:
-      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, UNIMPL: optname=0x%x, ..)\n", s, optname));
-      err = ENOPROTOOPT;
-    }  /* switch */
-    break;
-
-/* Level: IPPROTO_TCP */
-  case IPPROTO_TCP:
-    if( optlen < sizeof(int) ) {
-      err = EINVAL;
-        break;
-    }
-
-    /* If this is no TCP socket, ignore any options. */
-    if ( sock->conn->type != NETCONN_TCP ) return 0;
-
-    switch( optname ) {
-    case TCP_NODELAY:
-    case TCP_KEEPALIVE:
-      break;
-
-    default:
-      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, UNIMPL: optname=0x%x, ..)\n", s, optname));
-      err = ENOPROTOOPT;
-    }  /* switch */
-    break;
-
-/* UNDEFINED LEVEL */      
-  default:
-    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, level=0x%x, UNIMPL: optname=0x%x, ..)\n", s, level, optname));
-    err = ENOPROTOOPT;
-  }  /* switch */
-
-
-  if( 0 != err ) {
-    sock_set_errno(sock, err);
-    return -1;
-  }
-
-
-
-  /* Now do the actual option processing */
-
-  switch(level) {
-
-/* Level: SOL_SOCKET */
-  case SOL_SOCKET:
-    switch(optname) {
-
-    /* The option flags */
-    case SO_BROADCAST:
-    /* UNIMPL case SO_DEBUG: */
-    /* UNIMPL case SO_DONTROUTE: */
-    case SO_KEEPALIVE:
-    /* UNIMPL case SO_OOBINCLUDE: */
-#if SO_REUSE
-    case SO_REUSEADDR:
-    case SO_REUSEPORT:
-#endif /* SO_REUSE */
-    /* UNIMPL case SO_USELOOPBACK: */
-      if ( *(int*)optval ) {
-        sock->conn->pcb.tcp->so_options |= optname;
-      } else {
-        sock->conn->pcb.tcp->so_options &= ~optname;
-      }
-      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, SOL_SOCKET, optname=0x%x, ..) -> %s\n", s, optname, (*(int*)optval?"on":"off")));
-      break;
-    }  /* switch */
-    break;
-
-/* Level: IPPROTO_IP */
-  case IPPROTO_IP:
-    switch( optname ) {
-    case IP_TTL:
-      sock->conn->pcb.tcp->ttl = (u8_t)(*(int*)optval);
-      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, IP_TTL, ..) -> %u\n", s, sock->conn->pcb.tcp->ttl));
-      break;
-    case IP_TOS:
-      sock->conn->pcb.tcp->tos = (u8_t)(*(int*)optval);
-      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, IP_TOS, ..)-> %u\n", s, sock->conn->pcb.tcp->tos));
-      break;
-    }  /* switch */
-    break;
-
-/* Level: IPPROTO_TCP */
-  case IPPROTO_TCP:
-    switch( optname ) {
-    case TCP_NODELAY:
-      if ( *(int*)optval ) {
-        sock->conn->pcb.tcp->flags |= TF_NODELAY;
-      } else {
-        sock->conn->pcb.tcp->flags &= ~TF_NODELAY;
-      }
-      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_NODELAY) -> %s\n", s, (*(int *)optval)?"on":"off") );
-      break;
-    case TCP_KEEPALIVE:
-      sock->conn->pcb.tcp->keepalive = (u32_t)(*(int*)optval);
-      LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPALIVE) -> %lu\n", s, sock->conn->pcb.tcp->keepalive));
-      break;
-    }  /* switch */
-    break;
-  }  /* switch */
-
-  sock_set_errno(sock, err);
-  return err ? -1 : 0;
-}
-
-int lwip_ioctl(int s, long cmd, void *argp)
-{
-  struct lwip_socket *sock = get_socket(s);
-
-  if(!sock) {
-   	set_errno(EBADF);
-    return -1;
-  }
-
-  switch (cmd) {
-  case FIONREAD:
-    if (!argp) {
-      sock_set_errno(sock, EINVAL);
-      return -1;
-    }
-
-    *((u16_t*)argp) = sock->conn->recv_avail;
-
-    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, FIONREAD, %p) = %u\n", s, argp, *((u16_t*)argp)));
-    sock_set_errno(sock, 0);
-    return 0;
-
-  case FIONBIO:
-    if (argp && *(u32_t*)argp)
-      sock->flags |= O_NONBLOCK;
-    else
-      sock->flags &= ~O_NONBLOCK;
-    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, FIONBIO, %d)\n", s, !!(sock->flags & O_NONBLOCK)));
-    sock_set_errno(sock, 0);
-    return 0;
-
-  default:
-    LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, UNIMPL: 0x%lx, %p)\n", s, cmd, argp));
-    sock_set_errno(sock, ENOSYS); /* not yet implemented */
-    return -1;
-  }
-}
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/api/tcpip.c b/Demo/lwIP_MCF5235_GCC/lwip/src/api/tcpip.c
deleted file mode 100644
index ce8a2ca5d..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/api/tcpip.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-
-#include "lwip/opt.h"
-
-#include "lwip/sys.h"
-
-#include "lwip/memp.h"
-#include "lwip/pbuf.h"
-
-#include "lwip/ip.h"
-#include "lwip/ip_frag.h"
-#include "lwip/udp.h"
-#include "lwip/tcp.h"
-
-#include "lwip/tcpip.h"
-
-static void (* tcpip_init_done)(void *arg) = NULL;
-static void *tcpip_init_done_arg;
-static sys_mbox_t mbox;
-
-#if LWIP_TCP
-static int tcpip_tcp_timer_active = 0;
-
-static void
-tcpip_tcp_timer(void *arg)
-{
-  (void)arg;
-
-  /* call TCP timer handler */
-  tcp_tmr();
-  /* timer still needed? */
-  if (tcp_active_pcbs || tcp_tw_pcbs) {
-    /* restart timer */
-    sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL);
-  } else {
-    /* disable timer */
-    tcpip_tcp_timer_active = 0;
-  }
-}
-
-#if !NO_SYS
-void
-tcp_timer_needed(void)
-{
-  /* timer is off but needed again? */
-  if (!tcpip_tcp_timer_active && (tcp_active_pcbs || tcp_tw_pcbs)) {
-    /* enable and start timer */
-    tcpip_tcp_timer_active = 1;
-    sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL);
-  }
-}
-#endif /* !NO_SYS */
-#endif /* LWIP_TCP */
-
-#if IP_REASSEMBLY
-static void
-ip_timer(void *data)
-{
-  LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip: ip_reass_tmr()\n"));
-  ip_reass_tmr();
-  sys_timeout(1000, ip_timer, NULL);
-}
-#endif
-
-static void
-tcpip_thread(void *arg)
-{
-  struct tcpip_msg *msg;
-
-  (void)arg;
-
-  ip_init();
-#if LWIP_UDP  
-  udp_init();
-#endif
-#if LWIP_TCP
-  tcp_init();
-#endif
-#if IP_REASSEMBLY
-  sys_timeout(1000, ip_timer, NULL);
-#endif
-  if (tcpip_init_done != NULL) {
-    tcpip_init_done(tcpip_init_done_arg);
-  }
-
-  while (1) {                          /* MAIN Loop */
-    sys_mbox_fetch(mbox, (void *)&msg);
-    switch (msg->type) {
-    case TCPIP_MSG_API:
-      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: API message %p\n", (void *)msg));
-      api_msg_input(msg->msg.apimsg);
-      break;
-    case TCPIP_MSG_INPUT:
-      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: IP packet %p\n", (void *)msg));
-      ip_input(msg->msg.inp.p, msg->msg.inp.netif);
-      break;
-    case TCPIP_MSG_CALLBACK:
-      LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: CALLBACK %p\n", (void *)msg));
-      msg->msg.cb.f(msg->msg.cb.ctx);
-      break;
-    default:
-      break;
-    }
-    memp_free(MEMP_TCPIP_MSG, msg);
-  }
-}
-
-err_t
-tcpip_input(struct pbuf *p, struct netif *inp)
-{
-  struct tcpip_msg *msg;
-  
-  msg = memp_malloc(MEMP_TCPIP_MSG);
-  if (msg == NULL) {
-    pbuf_free(p);    
-    return ERR_MEM;  
-  }
-  
-  msg->type = TCPIP_MSG_INPUT;
-  msg->msg.inp.p = p;
-  msg->msg.inp.netif = inp;
-  sys_mbox_post(mbox, msg);
-  return ERR_OK;
-}
-
-err_t
-tcpip_callback(void (*f)(void *ctx), void *ctx)
-{
-  struct tcpip_msg *msg;
-  
-  msg = memp_malloc(MEMP_TCPIP_MSG);
-  if (msg == NULL) {
-    return ERR_MEM;  
-  }
-  
-  msg->type = TCPIP_MSG_CALLBACK;
-  msg->msg.cb.f = f;
-  msg->msg.cb.ctx = ctx;
-  sys_mbox_post(mbox, msg);
-  return ERR_OK;
-}
-
-void
-tcpip_apimsg(struct api_msg *apimsg)
-{
-  struct tcpip_msg *msg;
-  msg = memp_malloc(MEMP_TCPIP_MSG);
-  if (msg == NULL) {
-    memp_free(MEMP_API_MSG, apimsg);
-    return;
-  }
-  msg->type = TCPIP_MSG_API;
-  msg->msg.apimsg = apimsg;
-  sys_mbox_post(mbox, msg);
-}
-
-void
-tcpip_init(void (* initfunc)(void *), void *arg)
-{
-  tcpip_init_done = initfunc;
-  tcpip_init_done_arg = arg;
-  mbox = sys_mbox_new();
-  sys_thread_new(tcpip_thread, NULL, TCPIP_THREAD_PRIO);
-}
-
-
-
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/core/dhcp.c b/Demo/lwIP_MCF5235_GCC/lwip/src/core/dhcp.c
deleted file mode 100644
index b688afa19..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/core/dhcp.c
+++ /dev/null
@@ -1,1455 +0,0 @@
-/**
- * @file
- *
- * Dynamic Host Configuration Protocol client
- */
-
-/*
- *
- * Copyright (c) 2001-2004 Leon Woestenberg 
- * Copyright (c) 2001-2004 Axon Digital Design B.V., The Netherlands.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is a contribution to the lwIP TCP/IP stack.
- * The Swedish Institute of Computer Science and Adam Dunkels
- * are specifically granted permission to redistribute this
- * source code.
- *
- * Author: Leon Woestenberg 
- *
- * This is a DHCP client for the lwIP TCP/IP stack. It aims to conform
- * with RFC 2131 and RFC 2132.
- *
- * TODO:
- * - Proper parsing of DHCP messages exploiting file/sname field overloading.
- * - Add JavaDoc style documentation (API, internals).
- * - Support for interfaces other than Ethernet (SLIP, PPP, ...)
- *
- * Please coordinate changes and requests with Leon Woestenberg
- * 
- *
- * Integration with your code:
- *
- * In lwip/dhcp.h
- * #define DHCP_COARSE_TIMER_SECS (recommended 60 which is a minute)
- * #define DHCP_FINE_TIMER_MSECS (recommended 500 which equals TCP coarse timer)
- *
- * Then have your application call dhcp_coarse_tmr() and
- * dhcp_fine_tmr() on the defined intervals.
- *
- * dhcp_start(struct netif *netif);
- * starts a DHCP client instance which configures the interface by
- * obtaining an IP address lease and maintaining it.
- *
- * Use dhcp_release(netif) to end the lease and use dhcp_stop(netif)
- * to remove the DHCP client.
- *
- */
- 
-#include 
- 
-#include "lwip/stats.h"
-#include "lwip/mem.h"
-#include "lwip/udp.h"
-#include "lwip/ip_addr.h"
-#include "lwip/netif.h"
-#include "lwip/inet.h"
-#include "netif/etharp.h"
-
-#include "lwip/sys.h"
-#include "lwip/opt.h"
-#include "lwip/dhcp.h"
-
-#if LWIP_DHCP /* don't build if not configured for use in lwipopt.h */
-
-/** global transaction identifier, must be
- *  unique for each DHCP request. We simply increment, starting
- *  with this value (easy to match with a packet analyzer) */
-static u32_t xid = 0xABCD0000;
-
-/** DHCP client state machine functions */
-static void dhcp_handle_ack(struct netif *netif);
-static void dhcp_handle_nak(struct netif *netif);
-static void dhcp_handle_offer(struct netif *netif);
-
-static err_t dhcp_discover(struct netif *netif);
-static err_t dhcp_select(struct netif *netif);
-static void dhcp_check(struct netif *netif);
-static void dhcp_bind(struct netif *netif);
-static err_t dhcp_decline(struct netif *netif);
-static err_t dhcp_rebind(struct netif *netif);
-static void dhcp_set_state(struct dhcp *dhcp, u8_t new_state);
-
-/** receive, unfold, parse and free incoming messages */
-static void dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port);
-static err_t dhcp_unfold_reply(struct dhcp *dhcp);
-static u8_t *dhcp_get_option_ptr(struct dhcp *dhcp, u8_t option_type);
-static u8_t dhcp_get_option_byte(u8_t *ptr);
-static u16_t dhcp_get_option_short(u8_t *ptr);
-static u32_t dhcp_get_option_long(u8_t *ptr);
-static void dhcp_free_reply(struct dhcp *dhcp);
-
-/** set the DHCP timers */
-static void dhcp_timeout(struct netif *netif);
-static void dhcp_t1_timeout(struct netif *netif);
-static void dhcp_t2_timeout(struct netif *netif);
-
-/** build outgoing messages */
-/** create a DHCP request, fill in common headers */
-static err_t dhcp_create_request(struct netif *netif);
-/** free a DHCP request */
-static void dhcp_delete_request(struct netif *netif);
-/** add a DHCP option (type, then length in bytes) */
-static void dhcp_option(struct dhcp *dhcp, u8_t option_type, u8_t option_len);
-/** add option values */
-static void dhcp_option_byte(struct dhcp *dhcp, u8_t value);
-static void dhcp_option_short(struct dhcp *dhcp, u16_t value);
-static void dhcp_option_long(struct dhcp *dhcp, u32_t value);
-/** always add the DHCP options trailer to end and pad */
-static void dhcp_option_trailer(struct dhcp *dhcp);
-
-/**
- * Back-off the DHCP client (because of a received NAK response).
- *
- * Back-off the DHCP client because of a received NAK. Receiving a
- * NAK means the client asked for something non-sensible, for
- * example when it tries to renew a lease obtained on another network.
- *
- * We back-off and will end up restarting a fresh DHCP negotiation later.
- *
- * @param state pointer to DHCP state structure
- */
-static void dhcp_handle_nak(struct netif *netif) {
-  struct dhcp *dhcp = netif->dhcp;
-  u16_t msecs = 10 * 1000;
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_handle_nak(netif=%p) %c%c%"U16_F"\n", 
-    (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
-  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_handle_nak(): set request timeout %"U16_F" msecs\n", msecs));
-  dhcp_set_state(dhcp, DHCP_BACKING_OFF);
-}
-
-/**
- * Checks if the offered IP address is already in use.
- *
- * It does so by sending an ARP request for the offered address and
- * entering CHECKING state. If no ARP reply is received within a small
- * interval, the address is assumed to be free for use by us.
- */
-static void dhcp_check(struct netif *netif)
-{
-  struct dhcp *dhcp = netif->dhcp;
-  err_t result;
-  u16_t msecs;
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_check(netif=%p) %c%c\n", (void *)netif, (s16_t)netif->name[0],
-    (s16_t)netif->name[1]));
-  /* create an ARP query for the offered IP address, expecting that no host
-     responds, as the IP address should not be in use. */
-  result = etharp_query(netif, &dhcp->offered_ip_addr, NULL);
-  if (result != ERR_OK) {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_check: could not perform ARP query\n"));
-  }
-  dhcp->tries++;
-  msecs = 500;
-  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_check(): set request timeout %"U16_F" msecs\n", msecs));
-  dhcp_set_state(dhcp, DHCP_CHECKING);
-}
-
-/**
- * Remember the configuration offered by a DHCP server.
- *
- * @param state pointer to DHCP state structure
- */
-static void dhcp_handle_offer(struct netif *netif)
-{
-  struct dhcp *dhcp = netif->dhcp;
-  /* obtain the server address */
-  u8_t *option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_SERVER_ID);
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_handle_offer(netif=%p) %c%c%"U16_F"\n",
-    (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
-  if (option_ptr != NULL)
-  {
-    dhcp->server_ip_addr.addr = htonl(dhcp_get_option_long(&option_ptr[2]));
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_handle_offer(): server 0x%08"X32_F"\n", dhcp->server_ip_addr.addr));
-    /* remember offered address */
-    ip_addr_set(&dhcp->offered_ip_addr, (struct ip_addr *)&dhcp->msg_in->yiaddr);
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_handle_offer(): offer for 0x%08"X32_F"\n", dhcp->offered_ip_addr.addr));
-
-    dhcp_select(netif);
-  }
-}
-
-/**
- * Select a DHCP server offer out of all offers.
- *
- * Simply select the first offer received.
- *
- * @param netif the netif under DHCP control
- * @return lwIP specific error (see error.h)
- */
-static err_t dhcp_select(struct netif *netif)
-{
-  struct dhcp *dhcp = netif->dhcp;
-  err_t result;
-  u32_t msecs;
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_select(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
-
-  /* create and initialize the DHCP message header */
-  result = dhcp_create_request(netif);
-  if (result == ERR_OK)
-  {
-    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
-    dhcp_option_byte(dhcp, DHCP_REQUEST);
-
-    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
-    dhcp_option_short(dhcp, 576);
-
-    /* MUST request the offered IP address */
-    dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4);
-    dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr));
-
-    dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4);
-    dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr));
-
-    dhcp_option(dhcp, DHCP_OPTION_PARAMETER_REQUEST_LIST, 4/*num options*/);
-    dhcp_option_byte(dhcp, DHCP_OPTION_SUBNET_MASK);
-    dhcp_option_byte(dhcp, DHCP_OPTION_ROUTER);
-    dhcp_option_byte(dhcp, DHCP_OPTION_BROADCAST);
-    dhcp_option_byte(dhcp, DHCP_OPTION_DNS_SERVER);
-
-    dhcp_option_trailer(dhcp);
-    /* shrink the pbuf to the actual content length */
-    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
-
-    /* TODO: we really should bind to a specific local interface here
-       but we cannot specify an unconfigured netif as it is addressless */
-    udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
-    /* send broadcast to any DHCP server */
-    udp_connect(dhcp->pcb, IP_ADDR_BROADCAST, DHCP_SERVER_PORT);
-    udp_send(dhcp->pcb, dhcp->p_out);
-    /* reconnect to any (or to server here?!) */
-    udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
-    dhcp_delete_request(netif);
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_select: REQUESTING\n"));
-    dhcp_set_state(dhcp, DHCP_REQUESTING);
-  } else {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_select: could not allocate DHCP request\n"));
-  }
-  dhcp->tries++;
-  msecs = dhcp->tries < 4 ? dhcp->tries * 1000 : 4 * 1000;
-  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_select(): set request timeout %"U32_F" msecs\n", msecs));
-  return result;
-}
-
-/**
- * The DHCP timer that checks for lease renewal/rebind timeouts.
- *
- */
-void dhcp_coarse_tmr()
-{
-  struct netif *netif = netif_list;
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_coarse_tmr()\n"));
-  /* iterate through all network interfaces */
-  while (netif != NULL) {
-    /* only act on DHCP configured interfaces */
-    if (netif->dhcp != NULL) {
-      /* timer is active (non zero), and triggers (zeroes) now? */
-      if (netif->dhcp->t2_timeout-- == 1) {
-        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_coarse_tmr(): t2 timeout\n"));
-        /* this clients' rebind timeout triggered */
-        dhcp_t2_timeout(netif);
-      /* timer is active (non zero), and triggers (zeroes) now */
-      } else if (netif->dhcp->t1_timeout-- == 1) {
-        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_coarse_tmr(): t1 timeout\n"));
-        /* this clients' renewal timeout triggered */
-        dhcp_t1_timeout(netif);
-      }
-    }
-    /* proceed to next netif */
-    netif = netif->next;
-  }
-}
-
-/**
- * DHCP transaction timeout handling
- *
- * A DHCP server is expected to respond within a short period of time.
- * This timer checks whether an outstanding DHCP request is timed out.
- * 
- */
-void dhcp_fine_tmr()
-{
-  struct netif *netif = netif_list;
-  /* loop through netif's */
-  while (netif != NULL) {
-    /* only act on DHCP configured interfaces */
-    if (netif->dhcp != NULL) {
-      /* timer is active (non zero), and is about to trigger now */
-      if (netif->dhcp->request_timeout-- == 1) {
-        /* { netif->dhcp->request_timeout == 0 } */
-        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_fine_tmr(): request timeout\n"));
-        /* this clients' request timeout triggered */
-        dhcp_timeout(netif);
-      }
-    }
-    /* proceed to next network interface */
-    netif = netif->next;
-  }
-}
-
-/**
- * A DHCP negotiation transaction, or ARP request, has timed out.
- *
- * The timer that was started with the DHCP or ARP request has
- * timed out, indicating no response was received in time.
- *
- * @param netif the netif under DHCP control
- *
- */
-static void dhcp_timeout(struct netif *netif)
-{
-  struct dhcp *dhcp = netif->dhcp;
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_timeout()\n"));
-  /* back-off period has passed, or server selection timed out */
-  if ((dhcp->state == DHCP_BACKING_OFF) || (dhcp->state == DHCP_SELECTING)) {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_timeout(): restarting discovery\n"));
-    dhcp_discover(netif);
-  /* receiving the requested lease timed out */
-  } else if (dhcp->state == DHCP_REQUESTING) {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): REQUESTING, DHCP request timed out\n"));
-    if (dhcp->tries <= 5) {
-      dhcp_select(netif);
-    } else {
-      LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): REQUESTING, releasing, restarting\n"));
-      dhcp_release(netif);
-      dhcp_discover(netif);
-    }
-  /* received no ARP reply for the offered address (which is good) */
-  } else if (dhcp->state == DHCP_CHECKING) {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): CHECKING, ARP request timed out\n"));
-    if (dhcp->tries <= 1) {
-      dhcp_check(netif);
-    /* no ARP replies on the offered address,
-       looks like the IP address is indeed free */
-    } else {
-      /* bind the interface to the offered address */
-      dhcp_bind(netif);
-    }
-  }
-  /* did not get response to renew request? */
-  else if (dhcp->state == DHCP_RENEWING) {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): RENEWING, DHCP request timed out\n"));
-    /* just retry renewal */
-    /* note that the rebind timer will eventually time-out if renew does not work */
-    dhcp_renew(netif);
-  /* did not get response to rebind request? */
-  } else if (dhcp->state == DHCP_REBINDING) {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): REBINDING, DHCP request timed out\n"));
-    if (dhcp->tries <= 8) {
-      dhcp_rebind(netif);
-    } else {
-      LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): RELEASING, DISCOVERING\n"));
-      dhcp_release(netif);
-      dhcp_discover(netif);
-    }
-  }
-}
-
-/**
- * The renewal period has timed out.
- *
- * @param netif the netif under DHCP control
- */
-static void dhcp_t1_timeout(struct netif *netif)
-{
-  struct dhcp *dhcp = netif->dhcp;
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_t1_timeout()\n"));
-  if ((dhcp->state == DHCP_REQUESTING) || (dhcp->state == DHCP_BOUND) || (dhcp->state == DHCP_RENEWING)) {
-    /* just retry to renew - note that the rebind timer (t2) will
-     * eventually time-out if renew tries fail. */
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_t1_timeout(): must renew\n"));
-    dhcp_renew(netif);
-  }
-}
-
-/**
- * The rebind period has timed out.
- *
- */
-static void dhcp_t2_timeout(struct netif *netif)
-{
-  struct dhcp *dhcp = netif->dhcp;
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_t2_timeout()\n"));
-  if ((dhcp->state == DHCP_REQUESTING) || (dhcp->state == DHCP_BOUND) || (dhcp->state == DHCP_RENEWING)) {
-    /* just retry to rebind */
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_t2_timeout(): must rebind\n"));
-    dhcp_rebind(netif);
-  }
-}
-
-/**
- *
- * @param netif the netif under DHCP control
- */
-static void dhcp_handle_ack(struct netif *netif)
-{
-  struct dhcp *dhcp = netif->dhcp;
-  u8_t *option_ptr;
-  /* clear options we might not get from the ACK */
-  dhcp->offered_sn_mask.addr = 0;
-  dhcp->offered_gw_addr.addr = 0;
-  dhcp->offered_bc_addr.addr = 0;
-
-  /* lease time given? */
-  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_LEASE_TIME);
-  if (option_ptr != NULL) {
-    /* remember offered lease time */
-    dhcp->offered_t0_lease = dhcp_get_option_long(option_ptr + 2);
-  }
-  /* renewal period given? */
-  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_T1);
-  if (option_ptr != NULL) {
-    /* remember given renewal period */
-    dhcp->offered_t1_renew = dhcp_get_option_long(option_ptr + 2);
-  } else {
-    /* calculate safe periods for renewal */
-    dhcp->offered_t1_renew = dhcp->offered_t0_lease / 2;
-  }
-
-  /* renewal period given? */
-  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_T2);
-  if (option_ptr != NULL) {
-    /* remember given rebind period */
-    dhcp->offered_t2_rebind = dhcp_get_option_long(option_ptr + 2);
-  } else {
-    /* calculate safe periods for rebinding */
-    dhcp->offered_t2_rebind = dhcp->offered_t0_lease;
-  }
-
-  /* (y)our internet address */
-  ip_addr_set(&dhcp->offered_ip_addr, &dhcp->msg_in->yiaddr);
-
-/**
- * Patch #1308
- * TODO: we must check if the file field is not overloaded by DHCP options!
- */
-#if 0
-  /* boot server address */
-  ip_addr_set(&dhcp->offered_si_addr, &dhcp->msg_in->siaddr);
-  /* boot file name */
-  if (dhcp->msg_in->file[0]) {
-    dhcp->boot_file_name = mem_malloc(strlen(dhcp->msg_in->file) + 1);
-    strcpy(dhcp->boot_file_name, dhcp->msg_in->file);
-  }
-#endif
-
-  /* subnet mask */
-  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_SUBNET_MASK);
-  /* subnet mask given? */
-  if (option_ptr != NULL) {
-    dhcp->offered_sn_mask.addr = htonl(dhcp_get_option_long(&option_ptr[2]));
-  }
-
-  /* gateway router */
-  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_ROUTER);
-  if (option_ptr != NULL) {
-    dhcp->offered_gw_addr.addr = htonl(dhcp_get_option_long(&option_ptr[2]));
-  }
-
-  /* broadcast address */
-  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_BROADCAST);
-  if (option_ptr != NULL) {
-    dhcp->offered_bc_addr.addr = htonl(dhcp_get_option_long(&option_ptr[2]));
-  }
-  
-  /* DNS servers */
-  option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_DNS_SERVER);
-  if (option_ptr != NULL) {
-    u8_t n;
-    dhcp->dns_count = dhcp_get_option_byte(&option_ptr[1]);
-    /* limit to at most DHCP_MAX_DNS DNS servers */
-    if (dhcp->dns_count > DHCP_MAX_DNS) dhcp->dns_count = DHCP_MAX_DNS;
-    for (n = 0; n < dhcp->dns_count; n++)
-    {
-      dhcp->offered_dns_addr[n].addr = htonl(dhcp_get_option_long(&option_ptr[2+(n<<2)]));
-    }
-  }
-}
-
-/**
- * Start DHCP negotiation for a network interface.
- *
- * If no DHCP client instance was attached to this interface,
- * a new client is created first. If a DHCP client instance
- * was already present, it restarts negotiation.
- *
- * @param netif The lwIP network interface
- * @return lwIP error code
- * - ERR_OK - No error
- * - ERR_MEM - Out of memory
- *
- */
-err_t dhcp_start(struct netif *netif)
-{
-  struct dhcp *dhcp = netif->dhcp;
-  err_t result = ERR_OK;
-
-  LWIP_ASSERT("netif != NULL", netif != NULL);
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_start(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
-  netif->flags &= ~NETIF_FLAG_DHCP;
-
-  /* no DHCP client attached yet? */
-  if (dhcp == NULL) {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): starting new DHCP client\n"));
-    dhcp = mem_malloc(sizeof(struct dhcp));
-    if (dhcp == NULL) {
-      LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): could not allocate dhcp\n"));
-      return ERR_MEM;
-    }
-    /* store this dhcp client in the netif */
-    netif->dhcp = dhcp;
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): allocated dhcp"));
-  /* already has DHCP client attached */
-  } else {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE | 3, ("dhcp_start(): restarting DHCP configuration\n"));
-  }
-  	
-	/* clear data structure */
-	memset(dhcp, 0, sizeof(struct dhcp));
-  /* allocate UDP PCB */
-	dhcp->pcb = udp_new();
-	if (dhcp->pcb == NULL) {
-	  LWIP_DEBUGF(DHCP_DEBUG  | DBG_TRACE, ("dhcp_start(): could not obtain pcb\n"));
-	  mem_free((void *)dhcp);
-	  netif->dhcp = dhcp = NULL;
-	  return ERR_MEM;
-	}
-	LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): starting DHCP configuration\n"));
-  /* (re)start the DHCP negotiation */
-  result = dhcp_discover(netif);
-  if (result != ERR_OK) {
-    /* free resources allocated above */
-    dhcp_stop(netif);
-    return ERR_MEM;
-  }
-  netif->flags |= NETIF_FLAG_DHCP;
-  return result;
-}
-
-/**
- * Inform a DHCP server of our manual configuration.
- *
- * This informs DHCP servers of our fixed IP address configuration
- * by sending an INFORM message. It does not involve DHCP address
- * configuration, it is just here to be nice to the network.
- *
- * @param netif The lwIP network interface
- *
- */
-void dhcp_inform(struct netif *netif)
-{
-  struct dhcp *dhcp;
-  err_t result = ERR_OK;
-  dhcp = mem_malloc(sizeof(struct dhcp));
-  if (dhcp == NULL) {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_inform(): could not allocate dhcp\n"));
-    return;
-  }
-  netif->dhcp = dhcp;
-  memset(dhcp, 0, sizeof(struct dhcp));
-
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_inform(): allocated dhcp\n"));
-  dhcp->pcb = udp_new();
-  if (dhcp->pcb == NULL) {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_inform(): could not obtain pcb"));
-    mem_free((void *)dhcp);
-    return;
-  }
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_inform(): created new udp pcb\n"));
-  /* create and initialize the DHCP message header */
-  result = dhcp_create_request(netif);
-  if (result == ERR_OK) {
-
-    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
-    dhcp_option_byte(dhcp, DHCP_INFORM);
-
-    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
-    /* TODO: use netif->mtu ?! */
-    dhcp_option_short(dhcp, 576);
-
-    dhcp_option_trailer(dhcp);
-
-    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
-
-    udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
-    udp_connect(dhcp->pcb, IP_ADDR_BROADCAST, DHCP_SERVER_PORT);
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_inform: INFORMING\n"));
-    udp_send(dhcp->pcb, dhcp->p_out);
-    udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
-    dhcp_delete_request(netif);
-  } else {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_inform: could not allocate DHCP request\n"));
-  }
-
-  if (dhcp != NULL)
-  {
-    if (dhcp->pcb != NULL) udp_remove(dhcp->pcb);
-    dhcp->pcb = NULL;
-    mem_free((void *)dhcp);
-    netif->dhcp = NULL;
-  }
-}
-
-#if DHCP_DOES_ARP_CHECK
-/**
- * Match an ARP reply with the offered IP address.
- *
- * @param addr The IP address we received a reply from
- *
- */
-void dhcp_arp_reply(struct netif *netif, struct ip_addr *addr)
-{
-  LWIP_ASSERT("netif != NULL", netif != NULL);
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_arp_reply()\n"));
-  /* is a DHCP client doing an ARP check? */
-  if ((netif->dhcp != NULL) && (netif->dhcp->state == DHCP_CHECKING)) {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_arp_reply(): CHECKING, arp reply for 0x%08"X32_F"\n", addr->addr));
-    /* did a host respond with the address we
-       were offered by the DHCP server? */
-    if (ip_addr_cmp(addr, &netif->dhcp->offered_ip_addr)) {
-      /* we will not accept the offered address */
-      LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE | 1, ("dhcp_arp_reply(): arp reply matched with offered address, declining\n"));
-      dhcp_decline(netif);
-    }
-  }
-}
-
-/**
- * Decline an offered lease.
- *
- * Tell the DHCP server we do not accept the offered address.
- * One reason to decline the lease is when we find out the address
- * is already in use by another host (through ARP).
- */
-static err_t dhcp_decline(struct netif *netif)
-{
-  struct dhcp *dhcp = netif->dhcp;
-  err_t result = ERR_OK;
-  u16_t msecs;
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_decline()\n"));
-  dhcp_set_state(dhcp, DHCP_BACKING_OFF);
-  /* create and initialize the DHCP message header */
-  result = dhcp_create_request(netif);
-  if (result == ERR_OK)
-  {
-    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
-    dhcp_option_byte(dhcp, DHCP_DECLINE);
-
-    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
-    dhcp_option_short(dhcp, 576);
-
-    dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4);
-    dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr));
-
-    dhcp_option_trailer(dhcp);
-    /* resize pbuf to reflect true size of options */
-    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
-
-    udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
-    /* @todo: should we really connect here? we are performing sendto() */
-    udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
-    /* per section 4.4.4, broadcast DECLINE messages */
-    udp_sendto(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT);
-    dhcp_delete_request(netif);
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_decline: BACKING OFF\n"));
-  } else {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_decline: could not allocate DHCP request\n"));
-  }
-  dhcp->tries++;
-  msecs = 10*1000;
-  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
-   LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_decline(): set request timeout %"U16_F" msecs\n", msecs));
-  return result;
-}
-#endif
-
-
-/**
- * Start the DHCP process, discover a DHCP server.
- *
- */
-static err_t dhcp_discover(struct netif *netif)
-{
-  struct dhcp *dhcp = netif->dhcp;
-  err_t result = ERR_OK;
-  u16_t msecs;
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_discover()\n"));
-  ip_addr_set(&dhcp->offered_ip_addr, IP_ADDR_ANY);
-  /* create and initialize the DHCP message header */
-  result = dhcp_create_request(netif);
-  if (result == ERR_OK)
-  {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_discover: making request\n"));
-    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
-    dhcp_option_byte(dhcp, DHCP_DISCOVER);
-
-    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
-    dhcp_option_short(dhcp, 576);
-
-    dhcp_option(dhcp, DHCP_OPTION_PARAMETER_REQUEST_LIST, 4/*num options*/);
-    dhcp_option_byte(dhcp, DHCP_OPTION_SUBNET_MASK);
-    dhcp_option_byte(dhcp, DHCP_OPTION_ROUTER);
-    dhcp_option_byte(dhcp, DHCP_OPTION_BROADCAST);
-    dhcp_option_byte(dhcp, DHCP_OPTION_DNS_SERVER);
-
-    dhcp_option_trailer(dhcp);
-
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_discover: realloc()ing\n"));
-    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
-
-    /* set receive callback function with netif as user data */
-    udp_recv(dhcp->pcb, dhcp_recv, netif);
-    udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
-    udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_discover: sendto(DISCOVER, IP_ADDR_BROADCAST, DHCP_SERVER_PORT)\n"));
-    udp_sendto(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT);
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_discover: deleting()ing\n"));
-    dhcp_delete_request(netif);
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_discover: SELECTING\n"));
-    dhcp_set_state(dhcp, DHCP_SELECTING);
-  } else {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_discover: could not allocate DHCP request\n"));
-  }
-  dhcp->tries++;
-  msecs = dhcp->tries < 4 ? (dhcp->tries + 1) * 1000 : 10 * 1000;
-  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_discover(): set request timeout %"U16_F" msecs\n", msecs));
-  return result;
-}
-
-
-/**
- * Bind the interface to the offered IP address.
- *
- * @param netif network interface to bind to the offered address
- */
-static void dhcp_bind(struct netif *netif)
-{
-  struct dhcp *dhcp = netif->dhcp;
-  struct ip_addr sn_mask, gw_addr;
-  LWIP_ASSERT("dhcp_bind: netif != NULL", netif != NULL);
-  LWIP_ASSERT("dhcp_bind: dhcp != NULL", dhcp != NULL);
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_bind(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
-
-  /* temporary DHCP lease? */
-  if (dhcp->offered_t1_renew != 0xffffffffUL) {
-    /* set renewal period timer */
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_bind(): t1 renewal timer %"U32_F" secs\n", dhcp->offered_t1_renew));
-    dhcp->t1_timeout = (dhcp->offered_t1_renew + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS;
-    if (dhcp->t1_timeout == 0) dhcp->t1_timeout = 1;
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t1_renew*1000));
-  }
-  /* set renewal period timer */
-  if (dhcp->offered_t2_rebind != 0xffffffffUL) {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_bind(): t2 rebind timer %"U32_F" secs\n", dhcp->offered_t2_rebind));
-    dhcp->t2_timeout = (dhcp->offered_t2_rebind + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS;
-    if (dhcp->t2_timeout == 0) dhcp->t2_timeout = 1;
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t2_rebind*1000));
-  }
-  /* copy offered network mask */
-  ip_addr_set(&sn_mask, &dhcp->offered_sn_mask);
-
-  /* subnet mask not given? */
-  /* TODO: this is not a valid check. what if the network mask is 0? */
-  if (sn_mask.addr == 0) {
-    /* choose a safe subnet mask given the network class */
-    u8_t first_octet = ip4_addr1(&sn_mask);
-    if (first_octet <= 127) sn_mask.addr = htonl(0xff000000);
-    else if (first_octet >= 192) sn_mask.addr = htonl(0xffffff00);
-    else sn_mask.addr = htonl(0xffff0000);
-  }
-
-  ip_addr_set(&gw_addr, &dhcp->offered_gw_addr);
-  /* gateway address not given? */
-  if (gw_addr.addr == 0) {
-    /* copy network address */
-    gw_addr.addr = (dhcp->offered_ip_addr.addr & sn_mask.addr);
-    /* use first host address on network as gateway */
-    gw_addr.addr |= htonl(0x00000001);
-  }
-
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_bind(): IP: 0x%08"X32_F"\n", dhcp->offered_ip_addr.addr));
-  netif_set_ipaddr(netif, &dhcp->offered_ip_addr);
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_bind(): SN: 0x%08"X32_F"\n", sn_mask.addr));
-  netif_set_netmask(netif, &sn_mask);
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_bind(): GW: 0x%08"X32_F"\n", gw_addr.addr));
-  netif_set_gw(netif, &gw_addr);
-  /* bring the interface up */
-  netif_set_up(netif);
-  /* netif is now bound to DHCP leased address */
-  dhcp_set_state(dhcp, DHCP_BOUND);
-}
-
-/**
- * Renew an existing DHCP lease at the involved DHCP server.
- *
- * @param netif network interface which must renew its lease
- */
-err_t dhcp_renew(struct netif *netif)
-{
-  struct dhcp *dhcp = netif->dhcp;
-  err_t result;
-  u16_t msecs;
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_renew()\n"));
-  dhcp_set_state(dhcp, DHCP_RENEWING);
-
-  /* create and initialize the DHCP message header */
-  result = dhcp_create_request(netif);
-  if (result == ERR_OK) {
-
-    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
-    dhcp_option_byte(dhcp, DHCP_REQUEST);
-
-    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
-    /* TODO: use netif->mtu in some way */
-    dhcp_option_short(dhcp, 576);
-
-#if 0
-    dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4);
-    dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr));
-#endif
-
-#if 0
-    dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4);
-    dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr));
-#endif
-    /* append DHCP message trailer */
-    dhcp_option_trailer(dhcp);
-
-    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
-
-    udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
-    udp_connect(dhcp->pcb, &dhcp->server_ip_addr, DHCP_SERVER_PORT);
-    udp_send(dhcp->pcb, dhcp->p_out);
-    dhcp_delete_request(netif);
-
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_renew: RENEWING\n"));
-  } else {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_renew: could not allocate DHCP request\n"));
-  }
-  dhcp->tries++;
-  /* back-off on retries, but to a maximum of 20 seconds */
-  msecs = dhcp->tries < 10 ? dhcp->tries * 2000 : 20 * 1000;
-  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
-   LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_renew(): set request timeout %"U16_F" msecs\n", msecs));
-  return result;
-}
-
-/**
- * Rebind with a DHCP server for an existing DHCP lease.
- *
- * @param netif network interface which must rebind with a DHCP server
- */
-static err_t dhcp_rebind(struct netif *netif)
-{
-  struct dhcp *dhcp = netif->dhcp;
-  err_t result;
-  u16_t msecs;
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_rebind()\n"));
-  dhcp_set_state(dhcp, DHCP_REBINDING);
-
-  /* create and initialize the DHCP message header */
-  result = dhcp_create_request(netif);
-  if (result == ERR_OK)
-  {
-
-    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
-    dhcp_option_byte(dhcp, DHCP_REQUEST);
-
-    dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
-    dhcp_option_short(dhcp, 576);
-
-#if 0
-    dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4);
-    dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr));
-
-    dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4);
-    dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr));
-#endif
-
-    dhcp_option_trailer(dhcp);
-
-    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
-
-    /* set remote IP association to any DHCP server */
-    udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
-    udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
-    /* broadcast to server */
-    udp_sendto(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT);
-    dhcp_delete_request(netif);
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_rebind: REBINDING\n"));
-  } else {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_rebind: could not allocate DHCP request\n"));
-  }
-  dhcp->tries++;
-  msecs = dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000;
-  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
-   LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_rebind(): set request timeout %"U16_F" msecs\n", msecs));
-  return result;
-}
-
-/**
- * Release a DHCP lease.
- *
- * @param netif network interface which must release its lease
- */
-err_t dhcp_release(struct netif *netif)
-{
-  struct dhcp *dhcp = netif->dhcp;
-  err_t result;
-  u16_t msecs;
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_release()\n"));
-
-  /* idle DHCP client */
-  dhcp_set_state(dhcp, DHCP_OFF);
-  /* clean old DHCP offer */
-  dhcp->server_ip_addr.addr = 0;
-  dhcp->offered_ip_addr.addr = dhcp->offered_sn_mask.addr = 0;
-  dhcp->offered_gw_addr.addr = dhcp->offered_bc_addr.addr = 0;
-  dhcp->offered_t0_lease = dhcp->offered_t1_renew = dhcp->offered_t2_rebind = 0;
-  dhcp->dns_count = 0;
-  
-  /* create and initialize the DHCP message header */
-  result = dhcp_create_request(netif);
-  if (result == ERR_OK) {
-    dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
-    dhcp_option_byte(dhcp, DHCP_RELEASE);
-
-    dhcp_option_trailer(dhcp);
-
-    pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
-
-    udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
-    udp_connect(dhcp->pcb, &dhcp->server_ip_addr, DHCP_SERVER_PORT);
-    udp_send(dhcp->pcb, dhcp->p_out);
-    dhcp_delete_request(netif);
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_release: RELEASED, DHCP_OFF\n"));
-  } else {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_release: could not allocate DHCP request\n"));
-  }
-  dhcp->tries++;
-  msecs = dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000;
-  dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_release(): set request timeout %"U16_F" msecs\n", msecs));
-  /* bring the interface down */
-  netif_set_down(netif);
-  /* remove IP address from interface */
-  netif_set_ipaddr(netif, IP_ADDR_ANY);
-  netif_set_gw(netif, IP_ADDR_ANY);
-  netif_set_netmask(netif, IP_ADDR_ANY);
-  
-  /* TODO: netif_down(netif); */
-  return result;
-}
-/**
- * Remove the DHCP client from the interface.
- *
- * @param netif The network interface to stop DHCP on
- */
-void dhcp_stop(struct netif *netif)
-{
-  struct dhcp *dhcp = netif->dhcp;
-  LWIP_ASSERT("dhcp_stop: netif != NULL", netif != NULL);
-
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_stop()\n"));
-  /* netif is DHCP configured? */
-  if (dhcp != NULL)
-  {
-    if (dhcp->pcb != NULL)
-    {
-      udp_remove(dhcp->pcb);
-      dhcp->pcb = NULL;
-    }
-    if (dhcp->p != NULL)
-    {
-      pbuf_free(dhcp->p);
-      dhcp->p = NULL;
-    }
-    /* free unfolded reply */
-    dhcp_free_reply(dhcp);
-    mem_free((void *)dhcp);
-    netif->dhcp = NULL;
-  }
-}
-
-/*
- * Set the DHCP state of a DHCP client.
- *
- * If the state changed, reset the number of tries.
- *
- * TODO: we might also want to reset the timeout here?
- */
-static void dhcp_set_state(struct dhcp *dhcp, u8_t new_state)
-{
-  if (new_state != dhcp->state)
-  {
-    dhcp->state = new_state;
-    dhcp->tries = 0;
-  }
-}
-
-/*
- * Concatenate an option type and length field to the outgoing
- * DHCP message.
- *
- */
-static void dhcp_option(struct dhcp *dhcp, u8_t option_type, u8_t option_len)
-{
-  LWIP_ASSERT("dhcp_option_short: dhcp->options_out_len + 2 + option_len <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 2 + option_len <= DHCP_OPTIONS_LEN);
-  dhcp->msg_out->options[dhcp->options_out_len++] = option_type;
-  dhcp->msg_out->options[dhcp->options_out_len++] = option_len;
-}
-/*
- * Concatenate a single byte to the outgoing DHCP message.
- *
- */
-static void dhcp_option_byte(struct dhcp *dhcp, u8_t value)
-{
-  LWIP_ASSERT("dhcp_option_short: dhcp->options_out_len < DHCP_OPTIONS_LEN", dhcp->options_out_len < DHCP_OPTIONS_LEN);
-  dhcp->msg_out->options[dhcp->options_out_len++] = value;
-}
-static void dhcp_option_short(struct dhcp *dhcp, u16_t value)
-{
-  LWIP_ASSERT("dhcp_option_short: dhcp->options_out_len + 2 <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 2 <= DHCP_OPTIONS_LEN);
-  dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0xff00U) >> 8;
-  dhcp->msg_out->options[dhcp->options_out_len++] =  value & 0x00ffU;
-}
-static void dhcp_option_long(struct dhcp *dhcp, u32_t value)
-{
-  LWIP_ASSERT("dhcp_option_long: dhcp->options_out_len + 4 <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 4 <= DHCP_OPTIONS_LEN);
-  dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0xff000000UL) >> 24;
-  dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0x00ff0000UL) >> 16;
-  dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0x0000ff00UL) >> 8;
-  dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0x000000ffUL);
-}
-
-/**
- * Extract the DHCP message and the DHCP options.
- *
- * Extract the DHCP message and the DHCP options, each into a contiguous
- * piece of memory. As a DHCP message is variable sized by its options,
- * and also allows overriding some fields for options, the easy approach
- * is to first unfold the options into a conitguous piece of memory, and
- * use that further on.
- *
- */
-static err_t dhcp_unfold_reply(struct dhcp *dhcp)
-{
-  struct pbuf *p = dhcp->p;
-  u8_t *ptr;
-  u16_t i;
-  u16_t j = 0;
-  LWIP_ASSERT("dhcp->p != NULL", dhcp->p != NULL);
-  /* free any left-overs from previous unfolds */
-  dhcp_free_reply(dhcp);
-  /* options present? */
-  if (dhcp->p->tot_len > (sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN))
-  {
-    dhcp->options_in_len = dhcp->p->tot_len - (sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN);
-    dhcp->options_in = mem_malloc(dhcp->options_in_len);
-    if (dhcp->options_in == NULL)
-    {
-      LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_unfold_reply(): could not allocate dhcp->options\n"));
-      return ERR_MEM;
-    }
-  }
-  dhcp->msg_in = mem_malloc(sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN);
-  if (dhcp->msg_in == NULL)
-  {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_unfold_reply(): could not allocate dhcp->msg_in\n"));
-    mem_free((void *)dhcp->options_in);
-    dhcp->options_in = NULL;
-    return ERR_MEM;
-  }
-
-  ptr = (u8_t *)dhcp->msg_in;
-  /* proceed through struct dhcp_msg */
-  for (i = 0; i < sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN; i++)
-  {
-    *ptr++ = ((u8_t *)p->payload)[j++];
-    /* reached end of pbuf? */
-    if (j == p->len)
-    {
-      /* proceed to next pbuf in chain */
-      p = p->next;
-      j = 0;
-    }
-  }
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_unfold_reply(): copied %"U16_F" bytes into dhcp->msg_in[]\n", i));
-  if (dhcp->options_in != NULL) {
-    ptr = (u8_t *)dhcp->options_in;
-    /* proceed through options */
-    for (i = 0; i < dhcp->options_in_len; i++) {
-      *ptr++ = ((u8_t *)p->payload)[j++];
-      /* reached end of pbuf? */
-      if (j == p->len) {
-        /* proceed to next pbuf in chain */
-        p = p->next;
-        j = 0;
-      }
-    }
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_unfold_reply(): copied %"U16_F" bytes to dhcp->options_in[]\n", i));
-  }
-  return ERR_OK;
-}
-
-/**
- * Free the incoming DHCP message including contiguous copy of
- * its DHCP options.
- *
- */
-static void dhcp_free_reply(struct dhcp *dhcp)
-{
-  if (dhcp->msg_in != NULL) {
-    mem_free((void *)dhcp->msg_in);
-    dhcp->msg_in = NULL;
-  }
-  if (dhcp->options_in) {
-    mem_free((void *)dhcp->options_in);
-    dhcp->options_in = NULL;
-    dhcp->options_in_len = 0;
-  }
-  LWIP_DEBUGF(DHCP_DEBUG, ("dhcp_free_reply(): free'd\n"));
-}
-
-
-/**
- * If an incoming DHCP message is in response to us, then trigger the state machine
- */
-static void dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port)
-{
-  struct netif *netif = (struct netif *)arg;
-  struct dhcp *dhcp = netif->dhcp;
-  struct dhcp_msg *reply_msg = (struct dhcp_msg *)p->payload;
-  u8_t *options_ptr;
-  u8_t msg_type;
-  u8_t i;
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_recv(pbuf = %p) from DHCP server %"U16_F".%"U16_F".%"U16_F".%"U16_F" port %"U16_F"\n", (void*)p,
-    (u16_t)(ntohl(addr->addr) >> 24 & 0xff), (u16_t)(ntohl(addr->addr) >> 16 & 0xff),
-    (u16_t)(ntohl(addr->addr) >>  8 & 0xff), (u16_t)(ntohl(addr->addr) & 0xff), port));
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("pbuf->len = %"U16_F"\n", p->len));
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("pbuf->tot_len = %"U16_F"\n", p->tot_len));
-  /* prevent warnings about unused arguments */
-  (void)pcb; (void)addr; (void)port;
-  dhcp->p = p;
-  /* TODO: check packet length before reading them */
-  if (reply_msg->op != DHCP_BOOTREPLY) {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("not a DHCP reply message, but type %"U16_F"\n", (u16_t)reply_msg->op));
-    pbuf_free(p);
-    dhcp->p = NULL;
-    return;
-  }
-  /* iterate through hardware address and match against DHCP message */
-  for (i = 0; i < netif->hwaddr_len; i++) {
-    if (netif->hwaddr[i] != reply_msg->chaddr[i]) {
-      LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("netif->hwaddr[%"U16_F"]==%02"X16_F" != reply_msg->chaddr[%"U16_F"]==%02"X16_F"\n",
-        (u16_t)i, (u16_t)netif->hwaddr[i], (u16_t)i, (u16_t)reply_msg->chaddr[i]));
-      pbuf_free(p);
-      dhcp->p = NULL;
-      return;
-    }
-  }
-  /* match transaction ID against what we expected */
-  if (ntohl(reply_msg->xid) != dhcp->xid) {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("transaction id mismatch\n"));
-    pbuf_free(p);
-    dhcp->p = NULL;
-    return;
-  }
-  /* option fields could be unfold? */
-  if (dhcp_unfold_reply(dhcp) != ERR_OK) {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("problem unfolding DHCP message - too short on memory?\n"));
-    pbuf_free(p);
-    dhcp->p = NULL;
-    return;
-  }
-
-  LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("searching DHCP_OPTION_MESSAGE_TYPE\n"));
-  /* obtain pointer to DHCP message type */
-  options_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_MESSAGE_TYPE);
-  if (options_ptr == NULL) {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("DHCP_OPTION_MESSAGE_TYPE option not found\n"));
-    pbuf_free(p);
-    dhcp->p = NULL;
-    return;
-  }
-
-  /* read DHCP message type */
-  msg_type = dhcp_get_option_byte(options_ptr + 2);
-  /* message type is DHCP ACK? */
-  if (msg_type == DHCP_ACK) {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("DHCP_ACK received\n"));
-    /* in requesting state? */
-    if (dhcp->state == DHCP_REQUESTING) {
-      dhcp_handle_ack(netif);
-      dhcp->request_timeout = 0;
-#if DHCP_DOES_ARP_CHECK
-      /* check if the acknowledged lease address is already in use */
-      dhcp_check(netif);
-#else
-      /* bind interface to the acknowledged lease address */
-      dhcp_bind(netif);
-#endif
-    }
-    /* already bound to the given lease address? */
-    else if ((dhcp->state == DHCP_REBOOTING) || (dhcp->state == DHCP_REBINDING) || (dhcp->state == DHCP_RENEWING)) {
-      dhcp->request_timeout = 0;
-      dhcp_bind(netif);
-    }
-  }
-  /* received a DHCP_NAK in appropriate state? */
-  else if ((msg_type == DHCP_NAK) &&
-    ((dhcp->state == DHCP_REBOOTING) || (dhcp->state == DHCP_REQUESTING) ||
-     (dhcp->state == DHCP_REBINDING) || (dhcp->state == DHCP_RENEWING  ))) {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("DHCP_NAK received\n"));
-    dhcp->request_timeout = 0;
-    dhcp_handle_nak(netif);
-  }
-  /* received a DHCP_OFFER in DHCP_SELECTING state? */
-  else if ((msg_type == DHCP_OFFER) && (dhcp->state == DHCP_SELECTING)) {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("DHCP_OFFER received in DHCP_SELECTING state\n"));
-    dhcp->request_timeout = 0;
-    /* remember offered lease */
-    dhcp_handle_offer(netif);
-  }
-  pbuf_free(p);
-  dhcp->p = NULL;
-}
-
-
-static err_t dhcp_create_request(struct netif *netif)
-{
-  struct dhcp *dhcp = netif->dhcp;
-  u16_t i;
-  LWIP_ASSERT("dhcp_create_request: dhcp->p_out == NULL", dhcp->p_out == NULL);
-  LWIP_ASSERT("dhcp_create_request: dhcp->msg_out == NULL", dhcp->msg_out == NULL);
-  dhcp->p_out = pbuf_alloc(PBUF_TRANSPORT, sizeof(struct dhcp_msg), PBUF_RAM);
-  if (dhcp->p_out == NULL) {
-    LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_create_request(): could not allocate pbuf\n"));
-    return ERR_MEM;
-  }
-  /* give unique transaction identifier to this request */
-  dhcp->xid = xid++;
-
-  dhcp->msg_out = (struct dhcp_msg *)dhcp->p_out->payload;
-
-  dhcp->msg_out->op = DHCP_BOOTREQUEST;
-  /* TODO: make link layer independent */
-  dhcp->msg_out->htype = DHCP_HTYPE_ETH;
-  /* TODO: make link layer independent */
-  dhcp->msg_out->hlen = DHCP_HLEN_ETH;
-  dhcp->msg_out->hops = 0;
-  dhcp->msg_out->xid = htonl(dhcp->xid);
-  dhcp->msg_out->secs = 0;
-  dhcp->msg_out->flags = 0;
-  dhcp->msg_out->ciaddr.addr = netif->ip_addr.addr;
-  dhcp->msg_out->yiaddr.addr = 0;
-  dhcp->msg_out->siaddr.addr = 0;
-  dhcp->msg_out->giaddr.addr = 0;
-  for (i = 0; i < DHCP_CHADDR_LEN; i++) {
-    /* copy netif hardware address, pad with zeroes */
-    dhcp->msg_out->chaddr[i] = (i < netif->hwaddr_len) ? netif->hwaddr[i] : 0/* pad byte*/;
-  }
-  for (i = 0; i < DHCP_SNAME_LEN; i++) dhcp->msg_out->sname[i] = 0;
-  for (i = 0; i < DHCP_FILE_LEN; i++) dhcp->msg_out->file[i] = 0;
-  dhcp->msg_out->cookie = htonl(0x63825363UL);
-  dhcp->options_out_len = 0;
-  /* fill options field with an incrementing array (for debugging purposes) */
-  for (i = 0; i < DHCP_OPTIONS_LEN; i++) dhcp->msg_out->options[i] = i;
-  return ERR_OK;
-}
-
-static void dhcp_delete_request(struct netif *netif)
-{
-  struct dhcp *dhcp = netif->dhcp;
-  LWIP_ASSERT("dhcp_free_msg: dhcp->p_out != NULL", dhcp->p_out != NULL);
-  LWIP_ASSERT("dhcp_free_msg: dhcp->msg_out != NULL", dhcp->msg_out != NULL);
-  pbuf_free(dhcp->p_out);
-  dhcp->p_out = NULL;
-  dhcp->msg_out = NULL;
-}
-
-/**
- * Add a DHCP message trailer
- *
- * Adds the END option to the DHCP message, and if
- * necessary, up to three padding bytes.
- */
-
-static void dhcp_option_trailer(struct dhcp *dhcp)
-{
-  LWIP_ASSERT("dhcp_option_trailer: dhcp->msg_out != NULL\n", dhcp->msg_out != NULL);
-  LWIP_ASSERT("dhcp_option_trailer: dhcp->options_out_len < DHCP_OPTIONS_LEN\n", dhcp->options_out_len < DHCP_OPTIONS_LEN);
-  dhcp->msg_out->options[dhcp->options_out_len++] = DHCP_OPTION_END;
-  /* packet is too small, or not 4 byte aligned? */
-  while ((dhcp->options_out_len < DHCP_MIN_OPTIONS_LEN) || (dhcp->options_out_len & 3)) {
-    /* LWIP_DEBUGF(DHCP_DEBUG,("dhcp_option_trailer:dhcp->options_out_len=%"U16_F", DHCP_OPTIONS_LEN=%"U16_F, dhcp->options_out_len, DHCP_OPTIONS_LEN)); */
-    LWIP_ASSERT("dhcp_option_trailer: dhcp->options_out_len < DHCP_OPTIONS_LEN\n", dhcp->options_out_len < DHCP_OPTIONS_LEN);
-    /* add a fill/padding byte */
-    dhcp->msg_out->options[dhcp->options_out_len++] = 0;
-  }
-}
-
-/**
- * Find the offset of a DHCP option inside the DHCP message.
- *
- * @param client DHCP client
- * @param option_type
- *
- * @return a byte offset into the UDP message where the option was found, or
- * zero if the given option was not found.
- */
-static u8_t *dhcp_get_option_ptr(struct dhcp *dhcp, u8_t option_type)
-{
-  u8_t overload = DHCP_OVERLOAD_NONE;
-
-  /* options available? */
-  if ((dhcp->options_in != NULL) && (dhcp->options_in_len > 0)) {
-    /* start with options field */
-    u8_t *options = (u8_t *)dhcp->options_in;
-    u16_t offset = 0;
-    /* at least 1 byte to read and no end marker, then at least 3 bytes to read? */
-    while ((offset < dhcp->options_in_len) && (options[offset] != DHCP_OPTION_END)) {
-      /* LWIP_DEBUGF(DHCP_DEBUG, ("msg_offset=%"U16_F", q->len=%"U16_F, msg_offset, q->len)); */
-      /* are the sname and/or file field overloaded with options? */
-      if (options[offset] == DHCP_OPTION_OVERLOAD) {
-        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("overloaded message detected\n"));
-        /* skip option type and length */
-        offset += 2;
-        overload = options[offset++];
-      }
-      /* requested option found */
-      else if (options[offset] == option_type) {
-        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("option found at offset %"U16_F" in options\n", offset));
-        return &options[offset];
-      /* skip option */
-      } else {
-         LWIP_DEBUGF(DHCP_DEBUG, ("skipping option %"U16_F" in options\n", options[offset]));
-        /* skip option type */
-        offset++;
-        /* skip option length, and then length bytes */
-        offset += 1 + options[offset];
-      }
-    }
-    /* is this an overloaded message? */
-    if (overload != DHCP_OVERLOAD_NONE) {
-      u16_t field_len;
-      if (overload == DHCP_OVERLOAD_FILE) {
-        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("overloaded file field\n"));
-        options = (u8_t *)&dhcp->msg_in->file;
-        field_len = DHCP_FILE_LEN;
-      } else if (overload == DHCP_OVERLOAD_SNAME) {
-        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("overloaded sname field\n"));
-        options = (u8_t *)&dhcp->msg_in->sname;
-        field_len = DHCP_SNAME_LEN;
-      /* TODO: check if else if () is necessary */
-      } else {
-        LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("overloaded sname and file field\n"));
-        options = (u8_t *)&dhcp->msg_in->sname;
-        field_len = DHCP_FILE_LEN + DHCP_SNAME_LEN;
-      }
-      offset = 0;
-
-      /* at least 1 byte to read and no end marker */
-      while ((offset < field_len) && (options[offset] != DHCP_OPTION_END)) {
-        if (options[offset] == option_type) {
-           LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("option found at offset=%"U16_F"\n", offset));
-          return &options[offset];
-        /* skip option */
-        } else {
-          LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("skipping option %"U16_F"\n", options[offset]));
-          /* skip option type */
-          offset++;
-          offset += 1 + options[offset];
-        }
-      }
-    }
-  }
-  return 0;
-}
-
-/**
- * Return the byte of DHCP option data.
- *
- * @param client DHCP client.
- * @param ptr pointer obtained by dhcp_get_option_ptr().
- *
- * @return byte value at the given address.
- */
-static u8_t dhcp_get_option_byte(u8_t *ptr)
-{
-  LWIP_DEBUGF(DHCP_DEBUG, ("option byte value=%"U16_F"\n", (u16_t)(*ptr)));
-  return *ptr;
-}
-
-/**
- * Return the 16-bit value of DHCP option data.
- *
- * @param client DHCP client.
- * @param ptr pointer obtained by dhcp_get_option_ptr().
- *
- * @return byte value at the given address.
- */
-static u16_t dhcp_get_option_short(u8_t *ptr)
-{
-  u16_t value;
-  value = *ptr++ << 8;
-  value |= *ptr;
-  LWIP_DEBUGF(DHCP_DEBUG, ("option short value=%"U16_F"\n", value));
-  return value;
-}
-
-/**
- * Return the 32-bit value of DHCP option data.
- *
- * @param client DHCP client.
- * @param ptr pointer obtained by dhcp_get_option_ptr().
- *
- * @return byte value at the given address.
- */
-static u32_t dhcp_get_option_long(u8_t *ptr)
-{
-  u32_t value;
-  value = (u32_t)(*ptr++) << 24;
-  value |= (u32_t)(*ptr++) << 16;
-  value |= (u32_t)(*ptr++) << 8;
-  value |= (u32_t)(*ptr++);
-  LWIP_DEBUGF(DHCP_DEBUG, ("option long value=%"U32_F"\n", value));
-  return value;
-}
-
-#endif /* LWIP_DHCP */
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/core/inet.c b/Demo/lwIP_MCF5235_GCC/lwip/src/core/inet.c
deleted file mode 100644
index 556cbeb5f..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/core/inet.c
+++ /dev/null
@@ -1,525 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels 
- *
- */
-
-
-/* inet.c
- *
- * Functions common to all TCP/IP modules, such as the Internet checksum and the
- * byte order functions.
- *
- */
-
-
-#include "lwip/opt.h"
-
-#include "lwip/arch.h"
-
-#include "lwip/def.h"
-#include "lwip/inet.h"
-
-#include "lwip/sys.h"
-
-/* This is a reference implementation of the checksum algorithm, with the
- * aim of being simple, correct and fully portable. Checksumming is the
- * first thing you would want to optimize for your platform. You will
- * need to port it to your architecture and in your sys_arch.h:
- * 
- * #define LWIP_CHKSUM  
-*/
-#ifndef LWIP_CHKSUM
-#define LWIP_CHKSUM lwip_standard_chksum
-
-/**
- * lwip checksum
- *
- * @param dataptr points to start of data to be summed at any boundary
- * @param len length of data to be summed
- * @return host order (!) lwip checksum (non-inverted Internet sum) 
- *
- * @note accumulator size limits summable lenght to 64k
- * @note host endianess is irrelevant (p3 RFC1071)
- */
-static u16_t
-lwip_standard_chksum(void *dataptr, u16_t len)
-{
-  u32_t acc;
-  u16_t src;
-  u8_t *octetptr;
-
-  acc = 0;
-  /* dataptr may be at odd or even addresses */
-  octetptr = (u8_t*)dataptr;
-  while (len > 1)
-  {
-    /* declare first octet as most significant
-       thus assume network order, ignoring host order */
-    src = (*octetptr) << 8;
-    octetptr++;
-    /* declare second octet as least significant */
-    src |= (*octetptr);
-    octetptr++;
-    acc += src;
-    len -= 2;
-  }
-  if (len > 0)
-  {
-    /* accumulate remaining octet */
-    src = (*octetptr) << 8;
-    acc += src;
-  }
-  /* add deferred carry bits */
-  acc = (acc >> 16) + (acc & 0x0000ffffUL);
-  if ((acc & 0xffff0000) != 0) {
-    acc = (acc >> 16) + (acc & 0x0000ffffUL);
-  }
-  /* This maybe a little confusing: reorder sum using htons()
-     instead of ntohs() since it has a little less call overhead.
-     The caller must invert bits for Internet sum ! */
-  return htons((u16_t)acc);
-}
-
-#endif
-
-#if 0
-/*
- * Curt McDowell
- * Broadcom Corp.
- * csm@broadcom.com
- *
- * IP checksum two bytes at a time with support for
- * unaligned buffer.
- * Works for len up to and including 0x20000.
- * by Curt McDowell, Broadcom Corp. 12/08/2005
- */
-
-static u16_t
-lwip_standard_chksum2(void *dataptr, int len)
-{
-  u8_t *pb = dataptr;
-  u16_t *ps, t = 0;
-  u32_t sum = 0;
-  int odd = ((u32_t)pb & 1);
-
-  /* Get aligned to u16_t */
-  if (odd && len > 0) {
-    ((u8_t *)&t)[1] = *pb++;
-    len--;
-  }
-
-  /* Add the bulk of the data */
-  ps = (u16_t *)pb;
-  while (len > 1) {
-    sum += *ps++;
-    len -= 2;
-  }
-
-  /* Consume left-over byte, if any */
-  if (len > 0)
-    ((u8_t *)&t)[0] = *(u8_t *)ps;;
-
-  /* Add end bytes */
-  sum += t;
-
-  /*  Fold 32-bit sum to 16 bits */
-  while (sum >> 16)
-    sum = (sum & 0xffff) + (sum >> 16);
-
-  /* Swap if alignment was odd */
-  if (odd)
-    sum = ((sum & 0xff) << 8) | ((sum & 0xff00) >> 8);
-
-  return sum;
-}
-
-/**
- * An optimized checksum routine. Basically, it uses loop-unrolling on
- * the checksum loop, treating the head and tail bytes specially, whereas
- * the inner loop acts on 8 bytes at a time. 
- *
- * @arg start of buffer to be checksummed. May be an odd byte address.
- * @len number of bytes in the buffer to be checksummed.
- * 
- * @todo First argument type conflicts with generic checksum routine.
- * 
- * by Curt McDowell, Broadcom Corp. December 8th, 2005
- */
-
-static u16_t
-lwip_standard_chksum4(u8_t *pb, int len)
-{
-  u16_t *ps, t = 0;
-  u32_t *pl;
-  u32_t sum = 0, tmp;
-  /* starts at odd byte address? */
-  int odd = ((u32_t)pb & 1);
-
-  if (odd && len > 0) {
-    ((u8_t *)&t)[1] = *pb++;
-    len--;
-  }
-
-  ps = (u16_t *)pb;
-
-  if (((u32_t)ps & 3) && len > 1) {
-    sum += *ps++;
-    len -= 2;
-  }
-
-  pl = (u32_t *)ps;
-
-  while (len > 7)  {
-    tmp = sum + *pl++;          /* ping */
-    if (tmp < sum)
-      tmp++;                    /* add back carry */
-
-    sum = tmp + *pl++;          /* pong */
-    if (sum < tmp)
-      sum++;                    /* add back carry */
-
-    len -= 8;
-  }
-
-  /* make room in upper bits */
-  sum = (sum >> 16) + (sum & 0xffff);
-
-  ps = (u16_t *)pl;
-
-  /* 16-bit aligned word remaining? */
-  while (len > 1) {
-    sum += *ps++;
-    len -= 2;
-  }
-
-  /* dangling tail byte remaining? */
-  if (len > 0)                  /* include odd byte */
-    ((u8_t *)&t)[0] = *(u8_t *)ps;
-
-  sum += t;                     /* add end bytes */
-
-  while (sum >> 16)             /* combine halves */
-    sum = (sum >> 16) + (sum & 0xffff);
-
-  if (odd)
-    sum = ((sum & 0xff) << 8) | ((sum & 0xff00) >> 8);
-
-  return sum;
-}
-#endif
-
-/* inet_chksum_pseudo:
- *
- * Calculates the pseudo Internet checksum used by TCP and UDP for a pbuf chain.
- */
-
-u16_t
-inet_chksum_pseudo(struct pbuf *p,
-       struct ip_addr *src, struct ip_addr *dest,
-       u8_t proto, u16_t proto_len)
-{
-  u32_t acc;
-  struct pbuf *q;
-  u8_t swapped;
-
-  acc = 0;
-  swapped = 0;
-  /* iterate through all pbuf in chain */
-  for(q = p; q != NULL; q = q->next) {
-    LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): checksumming pbuf %p (has next %p) \n",
-      (void *)q, (void *)q->next));
-    acc += LWIP_CHKSUM(q->payload, q->len);
-    /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): unwrapped lwip_chksum()=%"X32_F" \n", acc));*/
-    while (acc >> 16) {
-      acc = (acc & 0xffffUL) + (acc >> 16);
-    }
-    if (q->len % 2 != 0) {
-      swapped = 1 - swapped;
-      acc = ((acc & 0xff) << 8) | ((acc & 0xff00UL) >> 8);
-    }
-    /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): wrapped lwip_chksum()=%"X32_F" \n", acc));*/
-  }
-
-  if (swapped) {
-    acc = ((acc & 0xff) << 8) | ((acc & 0xff00UL) >> 8);
-  }
-  acc += (src->addr & 0xffffUL);
-  acc += ((src->addr >> 16) & 0xffffUL);
-  acc += (dest->addr & 0xffffUL);
-  acc += ((dest->addr >> 16) & 0xffffUL);
-  acc += (u32_t)htons((u16_t)proto);
-  acc += (u32_t)htons(proto_len);
-
-  while (acc >> 16) {
-    acc = (acc & 0xffffUL) + (acc >> 16);
-  }
-  LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): pbuf chain lwip_chksum()=%"X32_F"\n", acc));
-  return (u16_t)~(acc & 0xffffUL);
-}
-
-/* inet_chksum:
- *
- * Calculates the Internet checksum over a portion of memory. Used primarely for IP
- * and ICMP.
- */
-
-u16_t
-inet_chksum(void *dataptr, u16_t len)
-{
-  u32_t acc;
-
-  acc = LWIP_CHKSUM(dataptr, len);
-  while (acc >> 16) {
-    acc = (acc & 0xffff) + (acc >> 16);
-  }
-  return (u16_t)~(acc & 0xffff);
-}
-
-u16_t
-inet_chksum_pbuf(struct pbuf *p)
-{
-  u32_t acc;
-  struct pbuf *q;
-  u8_t swapped;
-
-  acc = 0;
-  swapped = 0;
-  for(q = p; q != NULL; q = q->next) {
-    acc += LWIP_CHKSUM(q->payload, q->len);
-    while (acc >> 16) {
-      acc = (acc & 0xffffUL) + (acc >> 16);
-    }
-    if (q->len % 2 != 0) {
-      swapped = 1 - swapped;
-      acc = (acc & 0x00ffUL << 8) | (acc & 0xff00UL >> 8);
-    }
-  }
-
-  if (swapped) {
-    acc = ((acc & 0x00ffUL) << 8) | ((acc & 0xff00UL) >> 8);
-  }
-  return (u16_t)~(acc & 0xffffUL);
-}
-
-/* Here for now until needed in other places in lwIP */
-#ifndef isascii
-#define in_range(c, lo, up)  ((u8_t)c >= lo && (u8_t)c <= up)
-#define isascii(c)           in_range(c, 0x20, 0x7f)
-#define isdigit(c)           in_range(c, '0', '9')
-#define isxdigit(c)          (isdigit(c) || in_range(c, 'a', 'f') || in_range(c, 'A', 'F'))
-#define islower(c)           in_range(c, 'a', 'z')
-#define isspace(c)           (c == ' ' || c == '\f' || c == '\n' || c == '\r' || c == '\t' || c == '\v')
-#endif		
-		
-
- /*
-  * Ascii internet address interpretation routine.
-  * The value returned is in network order.
-  */
-
- /*  */
- /* inet_addr */
- u32_t inet_addr(const char *cp)
- {
-     struct in_addr val;
-
-     if (inet_aton(cp, &val)) {
-         return (val.s_addr);
-     }
-     return (INADDR_NONE);
- }
-
- /*
-  * Check whether "cp" is a valid ascii representation
-  * of an Internet address and convert to a binary address.
-  * Returns 1 if the address is valid, 0 if not.
-  * This replaces inet_addr, the return value from which
-  * cannot distinguish between failure and a local broadcast address.
-  */
- /*  */
- /* inet_aton */
- s8_t
- inet_aton(const char *cp, struct in_addr *addr)
- {
-     u32_t val;
-     s32_t base, n;
-     char c;
-     u32_t parts[4];
-     u32_t* pp = parts;
-
-     c = *cp;
-     for (;;) {
-         /*
-          * Collect number up to ``.''.
-          * Values are specified as for C:
-          * 0x=hex, 0=octal, isdigit=decimal.
-          */
-         if (!isdigit(c))
-             return (0);
-         val = 0; base = 10;
-         if (c == '0') {
-             c = *++cp;
-             if (c == 'x' || c == 'X')
-                 base = 16, c = *++cp;
-             else
-                 base = 8;
-         }
-         for (;;) {
-             if (isdigit(c)) {
-                 val = (val * base) + (s16_t)(c - '0');
-                 c = *++cp;
-             } else if (base == 16 && isxdigit(c)) {
-                 val = (val << 4) |
-                     (s16_t)(c + 10 - (islower(c) ? 'a' : 'A'));
-                 c = *++cp;
-             } else
-             break;
-         }
-         if (c == '.') {
-             /*
-              * Internet format:
-              *  a.b.c.d
-              *  a.b.c   (with c treated as 16 bits)
-              *  a.b (with b treated as 24 bits)
-              */
-             if (pp >= parts + 3)
-                 return (0);
-             *pp++ = val;
-             c = *++cp;
-         } else
-             break;
-     }
-     /*
-      * Check for trailing characters.
-      */
-     if (c != '\0' && (!isascii(c) || !isspace(c)))
-         return (0);
-     /*
-      * Concoct the address according to
-      * the number of parts specified.
-      */
-     n = pp - parts + 1;
-     switch (n) {
-
-     case 0:
-         return (0);     /* initial nondigit */
-
-     case 1:             /* a -- 32 bits */
-         break;
-
-     case 2:             /* a.b -- 8.24 bits */
-         if (val > 0xffffff)
-             return (0);
-         val |= parts[0] << 24;
-         break;
-
-     case 3:             /* a.b.c -- 8.8.16 bits */
-         if (val > 0xffff)
-             return (0);
-         val |= (parts[0] << 24) | (parts[1] << 16);
-         break;
-
-     case 4:             /* a.b.c.d -- 8.8.8.8 bits */
-         if (val > 0xff)
-             return (0);
-         val |= (parts[0] << 24) | (parts[1] << 16) | (parts[2] << 8);
-         break;
-     }
-     if (addr)
-         addr->s_addr = htonl(val);
-     return (1);
- }
-
-/* Convert numeric IP address into decimal dotted ASCII representation.
- * returns ptr to static buffer; not reentrant!
- */
-char *inet_ntoa(struct in_addr addr)
-{
-  static char str[16];
-  u32_t s_addr = addr.s_addr;
-  char inv[3];
-  char *rp;
-  u8_t *ap;
-  u8_t rem;
-  u8_t n;
-  u8_t i;
-
-  rp = str;
-  ap = (u8_t *)&s_addr;
-  for(n = 0; n < 4; n++) {
-    i = 0;
-    do {
-      rem = *ap % (u8_t)10;
-      *ap /= (u8_t)10;
-      inv[i++] = '0' + rem;
-    } while(*ap);
-    while(i--)
-      *rp++ = inv[i];
-    *rp++ = '.';
-    ap++;
-  }
-  *--rp = 0;
-  return str;
-}
-
-
-#ifndef BYTE_ORDER
-#error BYTE_ORDER is not defined
-#endif
-#if BYTE_ORDER == LITTLE_ENDIAN
-
-u16_t
-htons(u16_t n)
-{
-  return ((n & 0xff) << 8) | ((n & 0xff00) >> 8);
-}
-
-u16_t
-ntohs(u16_t n)
-{
-  return htons(n);
-}
-
-u32_t
-htonl(u32_t n)
-{
-  return ((n & 0xff) << 24) |
-    ((n & 0xff00) << 8) |
-    ((n & 0xff0000) >> 8) |
-    ((n & 0xff000000) >> 24);
-}
-
-u32_t
-ntohl(u32_t n)
-{
-  return htonl(n);
-}
-
-#endif /* BYTE_ORDER == LITTLE_ENDIAN */
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/core/inet6.c b/Demo/lwIP_MCF5235_GCC/lwip/src/core/inet6.c
deleted file mode 100644
index c04915b73..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/core/inet6.c
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-
-
-/* inet6.c
- *
- * Functions common to all TCP/IP modules, such as the Internet checksum and the
- * byte order functions.
- *
- */
-
-
-#include "lwip/opt.h"
-
-#include "lwip/def.h"
-#include "lwip/inet.h"
-
-
-
-/* chksum:
- *
- * Sums up all 16 bit words in a memory portion. Also includes any odd byte.
- * This function is used by the other checksum functions.
- *
- * For now, this is not optimized. Must be optimized for the particular processor
- * arcitecture on which it is to run. Preferebly coded in assembler.
- */
-
-static u32_t
-chksum(void *dataptr, u16_t len)
-{
-  u16_t *sdataptr = dataptr;
-  u32_t acc;
-  
-  
-  for(acc = 0; len > 1; len -= 2) {
-    acc += *sdataptr++;
-  }
-
-  /* add up any odd byte */
-  if (len == 1) {
-    acc += htons((u16_t)(*(u8_t *)dataptr) << 8);
-  }
-
-  return acc;
-
-}
-
-/* inet_chksum_pseudo:
- *
- * Calculates the pseudo Internet checksum used by TCP and UDP for a pbuf chain.
- */
-
-u16_t
-inet_chksum_pseudo(struct pbuf *p,
-       struct ip_addr *src, struct ip_addr *dest,
-       u8_t proto, u32_t proto_len)
-{
-  u32_t acc;
-  struct pbuf *q;
-  u8_t swapped, i;
-
-  acc = 0;
-  swapped = 0;
-  for(q = p; q != NULL; q = q->next) {    
-    acc += chksum(q->payload, q->len);
-    while (acc >> 16) {
-      acc = (acc & 0xffff) + (acc >> 16);
-    }
-    if (q->len % 2 != 0) {
-      swapped = 1 - swapped;
-      acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8);
-    }
-  }
-
-  if (swapped) {
-    acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8);
-  }
-  
-  for(i = 0; i < 8; i++) {
-    acc += ((u16_t *)src->addr)[i] & 0xffff;
-    acc += ((u16_t *)dest->addr)[i] & 0xffff;
-    while (acc >> 16) {
-      acc = (acc & 0xffff) + (acc >> 16);
-    }
-  }
-  acc += (u16_t)htons((u16_t)proto);
-  acc += ((u16_t *)&proto_len)[0] & 0xffff;
-  acc += ((u16_t *)&proto_len)[1] & 0xffff;
-
-  while (acc >> 16) {
-    acc = (acc & 0xffff) + (acc >> 16);
-  }
-  return ~(acc & 0xffff);
-}
-
-/* inet_chksum:
- *
- * Calculates the Internet checksum over a portion of memory. Used primarely for IP
- * and ICMP.
- */
-
-u16_t
-inet_chksum(void *dataptr, u16_t len)
-{
-  u32_t acc, sum;
-
-  acc = chksum(dataptr, len);
-  sum = (acc & 0xffff) + (acc >> 16);
-  sum += (sum >> 16);
-  return ~(sum & 0xffff);
-}
-
-u16_t
-inet_chksum_pbuf(struct pbuf *p)
-{
-  u32_t acc;
-  struct pbuf *q;
-  u8_t swapped;
-  
-  acc = 0;
-  swapped = 0;
-  for(q = p; q != NULL; q = q->next) {
-    acc += chksum(q->payload, q->len);
-    while (acc >> 16) {
-      acc = (acc & 0xffff) + (acc >> 16);
-    }    
-    if (q->len % 2 != 0) {
-      swapped = 1 - swapped;
-      acc = (acc & 0xff << 8) | (acc & 0xff00 >> 8);
-    }
-  }
- 
-  if (swapped) {
-    acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8);
-  }
-  return ~(acc & 0xffff);
-}
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv4/icmp.c b/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv4/icmp.c
deleted file mode 100644
index db820148b..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv4/icmp.c
+++ /dev/null
@@ -1,202 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels 
- *
- */
-
-/* Some ICMP messages should be passed to the transport protocols. This
-   is not implemented. */
-
-#include 
-
-#include "lwip/opt.h"
-#include "lwip/icmp.h"
-#include "lwip/inet.h"
-#include "lwip/ip.h"
-#include "lwip/def.h"
-#include "lwip/stats.h"
-#include "lwip/snmp.h"
-
-void
-icmp_input(struct pbuf *p, struct netif *inp)
-{
-  u8_t type;
-  u8_t code;
-  struct icmp_echo_hdr *iecho;
-  struct ip_hdr *iphdr;
-  struct ip_addr tmpaddr;
-  u16_t hlen;
-
-  ICMP_STATS_INC(icmp.recv);
-  snmp_inc_icmpinmsgs();
-
-
-  iphdr = p->payload;
-  hlen = IPH_HL(iphdr) * 4;
-  if (pbuf_header(p, -((s16_t)hlen)) || (p->tot_len < sizeof(u16_t)*2)) {
-    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: short ICMP (%"U16_F" bytes) received\n", p->tot_len));
-    pbuf_free(p);
-    ICMP_STATS_INC(icmp.lenerr);
-    snmp_inc_icmpinerrors();
-    return;
-  }
-
-  type = *((u8_t *)p->payload);
-  code = *(((u8_t *)p->payload)+1);
-  switch (type) {
-  case ICMP_ECHO:
-    /* broadcast or multicast destination address? */
-    if (ip_addr_isbroadcast(&iphdr->dest, inp) || ip_addr_ismulticast(&iphdr->dest)) {
-      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: Not echoing to multicast or broadcast pings\n"));
-      ICMP_STATS_INC(icmp.err);
-      pbuf_free(p);
-      return;
-    }
-    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ping\n"));
-    if (p->tot_len < sizeof(struct icmp_echo_hdr)) {
-      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: bad ICMP echo received\n"));
-      pbuf_free(p);
-      ICMP_STATS_INC(icmp.lenerr);
-      snmp_inc_icmpinerrors();
-
-      return;
-    }
-    iecho = p->payload;
-    if (inet_chksum_pbuf(p) != 0) {
-      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo\n"));
-      pbuf_free(p);
-      ICMP_STATS_INC(icmp.chkerr);
-      snmp_inc_icmpinerrors();
-      return;
-    }
-    tmpaddr.addr = iphdr->src.addr;
-    iphdr->src.addr = iphdr->dest.addr;
-    iphdr->dest.addr = tmpaddr.addr;
-    ICMPH_TYPE_SET(iecho, ICMP_ER);
-    /* adjust the checksum */
-    if (iecho->chksum >= htons(0xffff - (ICMP_ECHO << 8))) {
-      iecho->chksum += htons(ICMP_ECHO << 8) + 1;
-    } else {
-      iecho->chksum += htons(ICMP_ECHO << 8);
-    }
-    ICMP_STATS_INC(icmp.xmit);
-    /* increase number of messages attempted to send */
-    snmp_inc_icmpoutmsgs();
-    /* increase number of echo replies attempted to send */
-    snmp_inc_icmpoutechoreps();
-
-    pbuf_header(p, hlen);
-    ip_output_if(p, &(iphdr->src), IP_HDRINCL,
-		 IPH_TTL(iphdr), 0, IP_PROTO_ICMP, inp);
-    break;
-  default:
-  LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ICMP type %"S16_F" code %"S16_F" not supported.\n", (s16_t)type, (s16_t)code));
-    ICMP_STATS_INC(icmp.proterr);
-    ICMP_STATS_INC(icmp.drop);
-  }
-  pbuf_free(p);
-}
-
-void
-icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t)
-{
-  struct pbuf *q;
-  struct ip_hdr *iphdr;
-  struct icmp_dur_hdr *idur;
-
-  q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM);
-  /* ICMP header + IP header + 8 bytes of data */
-
-  iphdr = p->payload;
-
-  idur = q->payload;
-  ICMPH_TYPE_SET(idur, ICMP_DUR);
-  ICMPH_CODE_SET(idur, t);
-
-  memcpy((u8_t *)q->payload + 8, p->payload, IP_HLEN + 8);
-
-  /* calculate checksum */
-  idur->chksum = 0;
-  idur->chksum = inet_chksum(idur, q->len);
-  ICMP_STATS_INC(icmp.xmit);
-  /* increase number of messages attempted to send */
-  snmp_inc_icmpoutmsgs();
-  /* increase number of destination unreachable messages attempted to send */
-  snmp_inc_icmpoutdestunreachs();
-
-  ip_output(q, NULL, &(iphdr->src),
-	    ICMP_TTL, 0, IP_PROTO_ICMP);
-  pbuf_free(q);
-}
-
-#if IP_FORWARD
-void
-icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t)
-{
-  struct pbuf *q;
-  struct ip_hdr *iphdr;
-  struct icmp_te_hdr *tehdr;
-
-  q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM);
-
-  iphdr = p->payload;
-  LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded from "));
-  ip_addr_debug_print(ICMP_DEBUG, &(iphdr->src));
-  LWIP_DEBUGF(ICMP_DEBUG, (" to "));
-  ip_addr_debug_print(ICMP_DEBUG, &(iphdr->dest));
-  LWIP_DEBUGF(ICMP_DEBUG, ("\n"));
-
-  tehdr = q->payload;
-  ICMPH_TYPE_SET(tehdr, ICMP_TE);
-  ICMPH_CODE_SET(tehdr, t);
-
-  /* copy fields from original packet */
-  memcpy((u8_t *)q->payload + 8, (u8_t *)p->payload, IP_HLEN + 8);
-
-  /* calculate checksum */
-  tehdr->chksum = 0;
-  tehdr->chksum = inet_chksum(tehdr, q->len);
-  ICMP_STATS_INC(icmp.xmit);
-  /* increase number of messages attempted to send */
-  snmp_inc_icmpoutmsgs();
-  /* increase number of destination unreachable messages attempted to send */
-  snmp_inc_icmpouttimeexcds();
-  ip_output(q, NULL, &(iphdr->src),
-	    ICMP_TTL, 0, IP_PROTO_ICMP);
-  pbuf_free(q);
-}
-
-#endif /* IP_FORWARD */
-
-
-
-
-
-
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv4/ip.c b/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv4/ip.c
deleted file mode 100644
index 4db68c8e8..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv4/ip.c
+++ /dev/null
@@ -1,508 +0,0 @@
-/* @file
- *
- * This is the IP layer implementation for incoming and outgoing IP traffic.
- * 
- * @see ip_frag.c
- *
- */
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels 
- *
- */
-
-#include "lwip/opt.h"
-
-#include "lwip/def.h"
-#include "lwip/mem.h"
-#include "lwip/ip.h"
-#include "lwip/ip_frag.h"
-#include "lwip/inet.h"
-#include "lwip/netif.h"
-#include "lwip/icmp.h"
-#include "lwip/raw.h"
-#include "lwip/udp.h"
-#include "lwip/tcp.h"
-
-#include "lwip/stats.h"
-
-#include "arch/perf.h"
-
-#include "lwip/snmp.h"
-#if LWIP_DHCP
-#  include "lwip/dhcp.h"
-#endif /* LWIP_DHCP */
-
-
-/**
- * Initializes the IP layer.
- */
-
-void
-ip_init(void)
-{
-  /* no initializations as of yet */
-}
-
-/**
- * Finds the appropriate network interface for a given IP address. It
- * searches the list of network interfaces linearly. A match is found
- * if the masked IP address of the network interface equals the masked
- * IP address given to the function.
- */
-
-struct netif *
-ip_route(struct ip_addr *dest)
-{
-  struct netif *netif;
-
-  /* iterate through netifs */
-  for(netif = netif_list; netif != NULL; netif = netif->next) {
-    /* network mask matches? */
-    if (ip_addr_netcmp(dest, &(netif->ip_addr), &(netif->netmask))) {
-      /* return netif on which to forward IP packet */
-      return netif;
-    }
-  }
-  /* no matching netif found, use default netif */
-  return netif_default;
-}
-#if IP_FORWARD
-
-/**
- * Forwards an IP packet. It finds an appropriate route for the
- * packet, decrements the TTL value of the packet, adjusts the
- * checksum and outputs the packet on the appropriate interface.
- */
-
-static struct netif *
-ip_forward(struct pbuf *p, struct ip_hdr *iphdr, struct netif *inp)
-{
-  struct netif *netif;
-
-  PERF_START;
-  /* Find network interface where to forward this IP packet to. */
-  netif = ip_route((struct ip_addr *)&(iphdr->dest));
-  if (netif == NULL) {
-    LWIP_DEBUGF(IP_DEBUG, ("ip_forward: no forwarding route for 0x%"X32_F" found\n",
-                      iphdr->dest.addr));
-    snmp_inc_ipnoroutes();
-    return (struct netif *)NULL;
-  }
-  /* Do not forward packets onto the same network interface on which
-   * they arrived. */
-  if (netif == inp) {
-    LWIP_DEBUGF(IP_DEBUG, ("ip_forward: not bouncing packets back on incoming interface.\n"));
-    snmp_inc_ipnoroutes();
-    return (struct netif *)NULL;
-  }
-
-  /* decrement TTL */
-  IPH_TTL_SET(iphdr, IPH_TTL(iphdr) - 1);
-  /* send ICMP if TTL == 0 */
-  if (IPH_TTL(iphdr) == 0) {
-    /* Don't send ICMP messages in response to ICMP messages */
-    if (IPH_PROTO(iphdr) != IP_PROTO_ICMP) {
-      icmp_time_exceeded(p, ICMP_TE_TTL);
-      snmp_inc_icmpouttimeexcds();
-    }
-    return (struct netif *)NULL;
-  }
-
-  /* Incrementally update the IP checksum. */
-  if (IPH_CHKSUM(iphdr) >= htons(0xffff - 0x100)) {
-    IPH_CHKSUM_SET(iphdr, IPH_CHKSUM(iphdr) + htons(0x100) + 1);
-  } else {
-    IPH_CHKSUM_SET(iphdr, IPH_CHKSUM(iphdr) + htons(0x100));
-  }
-
-  LWIP_DEBUGF(IP_DEBUG, ("ip_forward: forwarding packet to 0x%"X32_F"\n",
-                    iphdr->dest.addr));
-
-  IP_STATS_INC(ip.fw);
-  IP_STATS_INC(ip.xmit);
-    snmp_inc_ipforwdatagrams();
-
-  PERF_STOP("ip_forward");
-  /* transmit pbuf on chosen interface */
-  netif->output(netif, p, (struct ip_addr *)&(iphdr->dest));
-  return netif;
-}
-#endif /* IP_FORWARD */
-
-/**
- * This function is called by the network interface device driver when
- * an IP packet is received. The function does the basic checks of the
- * IP header such as packet size being at least larger than the header
- * size etc. If the packet was not destined for us, the packet is
- * forwarded (using ip_forward). The IP checksum is always checked.
- *
- * Finally, the packet is sent to the upper layer protocol input function.
- * 
- * 
- * 
- */
-
-err_t
-ip_input(struct pbuf *p, struct netif *inp) {
-  struct ip_hdr *iphdr;
-  struct netif *netif;
-  u16_t iphdrlen;
-
-  IP_STATS_INC(ip.recv);
-  snmp_inc_ipinreceives();
-
-  /* identify the IP header */
-  iphdr = p->payload;
-  if (IPH_V(iphdr) != 4) {
-    LWIP_DEBUGF(IP_DEBUG | 1, ("IP packet dropped due to bad version number %"U16_F"\n", IPH_V(iphdr)));
-    ip_debug_print(p);
-    pbuf_free(p);
-    IP_STATS_INC(ip.err);
-    IP_STATS_INC(ip.drop);
-    snmp_inc_ipunknownprotos();
-    return ERR_OK;
-  }
-  /* obtain IP header length in number of 32-bit words */
-  iphdrlen = IPH_HL(iphdr);
-  /* calculate IP header length in bytes */
-  iphdrlen *= 4;
-
-  /* header length exceeds first pbuf length? */
-  if (iphdrlen > p->len) {
-    LWIP_DEBUGF(IP_DEBUG | 2, ("IP header (len %"U16_F") does not fit in first pbuf (len %"U16_F"), IP packet droppped.\n",
-      iphdrlen, p->len));
-    /* free (drop) packet pbufs */
-    pbuf_free(p);
-    IP_STATS_INC(ip.lenerr);
-    IP_STATS_INC(ip.drop);
-    snmp_inc_ipindiscards();
-    return ERR_OK;
-  }
-
-  /* verify checksum */
-#if CHECKSUM_CHECK_IP
-  if (inet_chksum(iphdr, iphdrlen) != 0) {
-
-    LWIP_DEBUGF(IP_DEBUG | 2, ("Checksum (0x%"X16_F") failed, IP packet dropped.\n", inet_chksum(iphdr, iphdrlen)));
-    ip_debug_print(p);
-    pbuf_free(p);
-    IP_STATS_INC(ip.chkerr);
-    IP_STATS_INC(ip.drop);
-    snmp_inc_ipindiscards();
-    return ERR_OK;
-  }
-#endif
-
-  /* Trim pbuf. This should have been done at the netif layer,
-   * but we'll do it anyway just to be sure that its done. */
-  pbuf_realloc(p, ntohs(IPH_LEN(iphdr)));
-
-  /* match packet against an interface, i.e. is this packet for us? */
-  for (netif = netif_list; netif != NULL; netif = netif->next) {
-
-    LWIP_DEBUGF(IP_DEBUG, ("ip_input: iphdr->dest 0x%"X32_F" netif->ip_addr 0x%"X32_F" (0x%"X32_F", 0x%"X32_F", 0x%"X32_F")\n",
-      iphdr->dest.addr, netif->ip_addr.addr,
-      iphdr->dest.addr & netif->netmask.addr,
-      netif->ip_addr.addr & netif->netmask.addr,
-      iphdr->dest.addr & ~(netif->netmask.addr)));
-
-    /* interface is up and configured? */
-    if ((netif_is_up(netif)) && (!ip_addr_isany(&(netif->ip_addr))))
-    {
-      /* unicast to this interface address? */
-      if (ip_addr_cmp(&(iphdr->dest), &(netif->ip_addr)) ||
-         /* or broadcast on this interface network address? */
-         ip_addr_isbroadcast(&(iphdr->dest), netif)) {
-        LWIP_DEBUGF(IP_DEBUG, ("ip_input: packet accepted on interface %c%c\n",
-          netif->name[0], netif->name[1]));
-        /* break out of for loop */
-        break;
-      }
-    }
-  }
-#if LWIP_DHCP
-  /* Pass DHCP messages regardless of destination address. DHCP traffic is addressed
-   * using link layer addressing (such as Ethernet MAC) so we must not filter on IP.
-   * According to RFC 1542 section 3.1.1, referred by RFC 2131).
-   */
-  if (netif == NULL) {
-    /* remote port is DHCP server? */
-    if (IPH_PROTO(iphdr) == IP_PROTO_UDP) {
-      LWIP_DEBUGF(IP_DEBUG | DBG_TRACE | 1, ("ip_input: UDP packet to DHCP client port %"U16_F"\n",
-        ntohs(((struct udp_hdr *)((u8_t *)iphdr + iphdrlen))->dest)));
-      if (ntohs(((struct udp_hdr *)((u8_t *)iphdr + iphdrlen))->dest) == DHCP_CLIENT_PORT) {
-        LWIP_DEBUGF(IP_DEBUG | DBG_TRACE | 1, ("ip_input: DHCP packet accepted.\n"));
-        netif = inp;
-      }
-    }
-  }
-#endif /* LWIP_DHCP */
-  /* packet not for us? */
-  if (netif == NULL) {
-    /* packet not for us, route or discard */
-    LWIP_DEBUGF(IP_DEBUG | DBG_TRACE | 1, ("ip_input: packet not for us.\n"));
-#if IP_FORWARD
-    /* non-broadcast packet? */
-    if (!ip_addr_isbroadcast(&(iphdr->dest), inp)) {
-      /* try to forward IP packet on (other) interfaces */
-      ip_forward(p, iphdr, inp);
-    }
-    else
-#endif /* IP_FORWARD */
-    {
-      snmp_inc_ipindiscards();
-    }
-    pbuf_free(p);
-    return ERR_OK;
-  }
-  /* packet consists of multiple fragments? */
-  if ((IPH_OFFSET(iphdr) & htons(IP_OFFMASK | IP_MF)) != 0) {
-#if IP_REASSEMBLY /* packet fragment reassembly code present? */
-    LWIP_DEBUGF(IP_DEBUG, ("IP packet is a fragment (id=0x%04"X16_F" tot_len=%"U16_F" len=%"U16_F" MF=%"U16_F" offset=%"U16_F"), calling ip_reass()\n",
-      ntohs(IPH_ID(iphdr)), p->tot_len, ntohs(IPH_LEN(iphdr)), !!(IPH_OFFSET(iphdr) & htons(IP_MF)), (ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK)*8));
-    /* reassemble the packet*/
-    p = ip_reass(p);
-    /* packet not fully reassembled yet? */
-    if (p == NULL) {
-      return ERR_OK;
-    }
-    iphdr = p->payload;
-#else /* IP_REASSEMBLY == 0, no packet fragment reassembly code present */
-    pbuf_free(p);
-    LWIP_DEBUGF(IP_DEBUG | 2, ("IP packet dropped since it was fragmented (0x%"X16_F") (while IP_REASSEMBLY == 0).\n",
-      ntohs(IPH_OFFSET(iphdr))));
-    IP_STATS_INC(ip.opterr);
-    IP_STATS_INC(ip.drop);
-    snmp_inc_ipunknownprotos();
-    return ERR_OK;
-#endif /* IP_REASSEMBLY */
-  }
-
-#if IP_OPTIONS == 0 /* no support for IP options in the IP header? */
-  if (iphdrlen > IP_HLEN) {
-    LWIP_DEBUGF(IP_DEBUG | 2, ("IP packet dropped since there were IP options (while IP_OPTIONS == 0).\n"));
-    pbuf_free(p);
-    IP_STATS_INC(ip.opterr);
-    IP_STATS_INC(ip.drop);
-    snmp_inc_ipunknownprotos();
-    return ERR_OK;
-  }
-#endif /* IP_OPTIONS == 0 */
-
-  /* send to upper layers */
-  LWIP_DEBUGF(IP_DEBUG, ("ip_input: \n"));
-  ip_debug_print(p);
-  LWIP_DEBUGF(IP_DEBUG, ("ip_input: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len));
-
-#if LWIP_RAW
-  /* raw input did not eat the packet? */
-  if (raw_input(p, inp) == 0) {
-#endif /* LWIP_RAW */
-
-  switch (IPH_PROTO(iphdr)) {
-#if LWIP_UDP
-  case IP_PROTO_UDP:
-  case IP_PROTO_UDPLITE:
-    snmp_inc_ipindelivers();
-    udp_input(p, inp);
-    break;
-#endif /* LWIP_UDP */
-#if LWIP_TCP
-  case IP_PROTO_TCP:
-    snmp_inc_ipindelivers();
-    tcp_input(p, inp);
-    break;
-#endif /* LWIP_TCP */
-  case IP_PROTO_ICMP:
-    snmp_inc_ipindelivers();
-    icmp_input(p, inp);
-    break;
-  default:
-    /* send ICMP destination protocol unreachable unless is was a broadcast */
-    if (!ip_addr_isbroadcast(&(iphdr->dest), inp) &&
-        !ip_addr_ismulticast(&(iphdr->dest))) {
-      p->payload = iphdr;
-      icmp_dest_unreach(p, ICMP_DUR_PROTO);
-    }
-    pbuf_free(p);
-
-    LWIP_DEBUGF(IP_DEBUG | 2, ("Unsupported transport protocol %"U16_F"\n", IPH_PROTO(iphdr)));
-
-    IP_STATS_INC(ip.proterr);
-    IP_STATS_INC(ip.drop);
-    snmp_inc_ipunknownprotos();
-  }
-#if LWIP_RAW
-  } /* LWIP_RAW */
-#endif
-  return ERR_OK;
-}
-
-/**
- * Sends an IP packet on a network interface. This function constructs
- * the IP header and calculates the IP header checksum. If the source
- * IP address is NULL, the IP address of the outgoing network
- * interface is filled in as source address.
- */
-
-err_t
-ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
-             u8_t ttl, u8_t tos,
-             u8_t proto, struct netif *netif)
-{
-  struct ip_hdr *iphdr;
-  u16_t ip_id = 0;
-
-  snmp_inc_ipoutrequests();
-
-  if (dest != IP_HDRINCL) {
-    if (pbuf_header(p, IP_HLEN)) {
-      LWIP_DEBUGF(IP_DEBUG | 2, ("ip_output: not enough room for IP header in pbuf\n"));
-
-      IP_STATS_INC(ip.err);
-      snmp_inc_ipoutdiscards();
-      return ERR_BUF;
-    }
-
-    iphdr = p->payload;
-
-    IPH_TTL_SET(iphdr, ttl);
-    IPH_PROTO_SET(iphdr, proto);
-
-    ip_addr_set(&(iphdr->dest), dest);
-
-    IPH_VHLTOS_SET(iphdr, 4, IP_HLEN / 4, tos);
-    IPH_LEN_SET(iphdr, htons(p->tot_len));
-    IPH_OFFSET_SET(iphdr, htons(IP_DF));
-    IPH_ID_SET(iphdr, htons(ip_id));
-    ++ip_id;
-
-    if (ip_addr_isany(src)) {
-      ip_addr_set(&(iphdr->src), &(netif->ip_addr));
-    } else {
-      ip_addr_set(&(iphdr->src), src);
-    }
-
-    IPH_CHKSUM_SET(iphdr, 0);
-#if CHECKSUM_GEN_IP
-    IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN));
-#endif
-  } else {
-    iphdr = p->payload;
-    dest = &(iphdr->dest);
-  }
-
-#if IP_FRAG
-  /* don't fragment if interface has mtu set to 0 [loopif] */
-  if (netif->mtu && (p->tot_len > netif->mtu))
-    return ip_frag(p,netif,dest);
-#endif
-
-  IP_STATS_INC(ip.xmit);
-
-  LWIP_DEBUGF(IP_DEBUG, ("ip_output_if: %c%c%"U16_F"\n", netif->name[0], netif->name[1], netif->num));
-  ip_debug_print(p);
-
-  LWIP_DEBUGF(IP_DEBUG, ("netif->output()"));
-
-  return netif->output(netif, p, dest);
-}
-
-/**
- * Simple interface to ip_output_if. It finds the outgoing network
- * interface and calls upon ip_output_if to do the actual work.
- */
-
-err_t
-ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
-          u8_t ttl, u8_t tos, u8_t proto)
-{
-  struct netif *netif;
-
-  if ((netif = ip_route(dest)) == NULL) {
-    LWIP_DEBUGF(IP_DEBUG | 2, ("ip_output: No route to 0x%"X32_F"\n", dest->addr));
-
-    IP_STATS_INC(ip.rterr);
-    snmp_inc_ipoutdiscards();
-    return ERR_RTE;
-  }
-
-  return ip_output_if(p, src, dest, ttl, tos, proto, netif);
-}
-
-#if IP_DEBUG
-void
-ip_debug_print(struct pbuf *p)
-{
-  struct ip_hdr *iphdr = p->payload;
-  u8_t *payload;
-
-  payload = (u8_t *)iphdr + IP_HLEN;
-
-  LWIP_DEBUGF(IP_DEBUG, ("IP header:\n"));
-  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
-  LWIP_DEBUGF(IP_DEBUG, ("|%2"S16_F" |%2"S16_F" |  0x%02"X16_F" |     %5"U16_F"     | (v, hl, tos, len)\n",
-                    IPH_V(iphdr),
-                    IPH_HL(iphdr),
-                    IPH_TOS(iphdr),
-                    ntohs(IPH_LEN(iphdr))));
-  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
-  LWIP_DEBUGF(IP_DEBUG, ("|    %5"U16_F"      |%"U16_F"%"U16_F"%"U16_F"|    %4"U16_F"   | (id, flags, offset)\n",
-                    ntohs(IPH_ID(iphdr)),
-                    ntohs(IPH_OFFSET(iphdr)) >> 15 & 1,
-                    ntohs(IPH_OFFSET(iphdr)) >> 14 & 1,
-                    ntohs(IPH_OFFSET(iphdr)) >> 13 & 1,
-                    ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK));
-  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
-  LWIP_DEBUGF(IP_DEBUG, ("|  %3"U16_F"  |  %3"U16_F"  |    0x%04"X16_F"     | (ttl, proto, chksum)\n",
-                    IPH_TTL(iphdr),
-                    IPH_PROTO(iphdr),
-                    ntohs(IPH_CHKSUM(iphdr))));
-  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
-  LWIP_DEBUGF(IP_DEBUG, ("|  %3"U16_F"  |  %3"U16_F"  |  %3"U16_F"  |  %3"U16_F"  | (src)\n",
-                    ip4_addr1(&iphdr->src),
-                    ip4_addr2(&iphdr->src),
-                    ip4_addr3(&iphdr->src),
-                    ip4_addr4(&iphdr->src)));
-  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
-  LWIP_DEBUGF(IP_DEBUG, ("|  %3"U16_F"  |  %3"U16_F"  |  %3"U16_F"  |  %3"U16_F"  | (dest)\n",
-                    ip4_addr1(&iphdr->dest),
-                    ip4_addr2(&iphdr->dest),
-                    ip4_addr3(&iphdr->dest),
-                    ip4_addr4(&iphdr->dest)));
-  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
-}
-#endif /* IP_DEBUG */
-
-
-
-
-
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv4/ip_addr.c b/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv4/ip_addr.c
deleted file mode 100644
index 2af526e9f..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv4/ip_addr.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-
-#include "lwip/ip_addr.h"
-#include "lwip/inet.h"
-#include "lwip/netif.h"
-
-/* used by IP_ADDR_ANY and IP_ADDR_BROADCAST in ip_addr.h */
-const struct ip_addr ip_addr_any = { 0x00000000UL };
-const struct ip_addr ip_addr_broadcast = { 0xffffffffUL };
-
-/* Determine if an address is a broadcast address on a network interface 
- * 
- * @param addr address to be checked
- * @param netif the network interface against which the address is checked
- * @return returns non-zero if the address is a broadcast address
- *
- */
-
-u8_t ip_addr_isbroadcast(struct ip_addr *addr, struct netif *netif)
-{
-  /* all ones (broadcast) or all zeroes (old skool broadcast) */
-  if ((addr->addr == ip_addr_broadcast.addr) ||
-      (addr->addr == ip_addr_any.addr))
-    return 1;
-  /* no broadcast support on this network interface? */
-  else if ((netif->flags & NETIF_FLAG_BROADCAST) == 0)
-    /* the given address cannot be a broadcast address
-     * nor can we check against any broadcast addresses */
-    return 0;
-  /* address matches network interface address exactly? => no broadcast */
-  else if (addr->addr == netif->ip_addr.addr)
-    return 0;
-  /*  on the same (sub) network... */
-  else if (ip_addr_netcmp(addr, &(netif->ip_addr), &(netif->netmask))
-         /* ...and host identifier bits are all ones? =>... */
-          && ((addr->addr & ~netif->netmask.addr) ==
-           (ip_addr_broadcast.addr & ~netif->netmask.addr)))
-    /* => network broadcast address */
-    return 1;
-  else
-    return 0;
-}
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv4/ip_frag.c b/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv4/ip_frag.c
deleted file mode 100644
index 5a57138ce..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv4/ip_frag.c
+++ /dev/null
@@ -1,366 +0,0 @@
-/* @file
- * 
- * This is the IP packet segmentation and reassembly implementation.
- *
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Jani Monoses  
- * original reassembly code by Adam Dunkels 
- * 
- */
-
-#include 
-
-#include "lwip/opt.h"
-/* #include "lwip/sys.h" */
-#include "lwip/ip.h"
-#include "lwip/ip_frag.h"
-#include "lwip/netif.h"
-#include "lwip/stats.h"
-
-
-/*
- * Copy len bytes from offset in pbuf to buffer 
- *
- * helper used by both ip_reass and ip_frag
- */
-static struct pbuf *
-copy_from_pbuf(struct pbuf *p, u16_t * offset,
-           u8_t * buffer, u16_t len)
-{
-  u16_t l;
-
-  p->payload = (u8_t *)p->payload + *offset;
-  p->len -= *offset;
-  while (len) {
-    l = len < p->len ? len : p->len;
-    memcpy(buffer, p->payload, l);
-    buffer += l;
-    len -= l;
-    if (len)
-      p = p->next;
-    else
-      *offset = l;
-  }
-  return p;
-}
-
-#define IP_REASS_BUFSIZE 5760
-#define IP_REASS_MAXAGE 30
-#define IP_REASS_TMO 1000
-
-static u8_t ip_reassbuf[IP_HLEN + IP_REASS_BUFSIZE];
-static u8_t ip_reassbitmap[IP_REASS_BUFSIZE / (8 * 8) + 1];
-static const u8_t bitmap_bits[8] = { 0xff, 0x7f, 0x3f, 0x1f,
-  0x0f, 0x07, 0x03, 0x01
-};
-static u16_t ip_reasslen;
-static u8_t ip_reassflags;
-#define IP_REASS_FLAG_LASTFRAG 0x01
-
-static u8_t ip_reasstmr;
-
-/**
- * Reassembly timer base function
- * for both NO_SYS == 0 and 1 (!).
- *
- * Should be called every 1000 msec.
- */
-void
-ip_reass_tmr(void)
-{
-  if (ip_reasstmr > 0) {
-    ip_reasstmr--;
-  }
-}
-
-/**
- * Reassembles incoming IP fragments into an IP datagram.
- *
- * @param p points to a pbuf chain of the fragment
- * @return NULL if reassembly is incomplete, ? otherwise
- */
-struct pbuf *
-ip_reass(struct pbuf *p)
-{
-  struct pbuf *q;
-  struct ip_hdr *fraghdr, *iphdr;
-  u16_t offset, len;
-  u16_t i;
-
-  IPFRAG_STATS_INC(ip_frag.recv);
-
-  iphdr = (struct ip_hdr *) ip_reassbuf;
-  fraghdr = (struct ip_hdr *) p->payload;
-  /* If ip_reasstmr is zero, no packet is present in the buffer, so we
-     write the IP header of the fragment into the reassembly
-     buffer. The timer is updated with the maximum age. */
-  if (ip_reasstmr == 0) {
-    LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass: new packet\n"));
-    memcpy(iphdr, fraghdr, IP_HLEN);
-    ip_reasstmr = IP_REASS_MAXAGE;
-    ip_reassflags = 0;
-    /* Clear the bitmap. */
-    memset(ip_reassbitmap, 0, sizeof(ip_reassbitmap));
-  }
-
-  /* Check if the incoming fragment matches the one currently present
-     in the reasembly buffer. If so, we proceed with copying the
-     fragment into the buffer. */
-  if (ip_addr_cmp(&iphdr->src, &fraghdr->src) &&
-      ip_addr_cmp(&iphdr->dest, &fraghdr->dest) &&
-      IPH_ID(iphdr) == IPH_ID(fraghdr)) {
-    LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass: matching previous fragment ID=%"X16_F"\n",
-      ntohs(IPH_ID(fraghdr))));
-    IPFRAG_STATS_INC(ip_frag.cachehit);
-    /* Find out the offset in the reassembly buffer where we should
-       copy the fragment. */
-    len = ntohs(IPH_LEN(fraghdr)) - IPH_HL(fraghdr) * 4;
-    offset = (ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) * 8;
-
-    /* If the offset or the offset + fragment length overflows the
-       reassembly buffer, we discard the entire packet. */
-    if (offset > IP_REASS_BUFSIZE || offset + len > IP_REASS_BUFSIZE) {
-      LWIP_DEBUGF(IP_REASS_DEBUG,
-       ("ip_reass: fragment outside of buffer (%"S16_F":%"S16_F"/%"S16_F").\n", offset,
-        offset + len, IP_REASS_BUFSIZE));
-      ip_reasstmr = 0;
-      goto nullreturn;
-    }
-
-    /* Copy the fragment into the reassembly buffer, at the right
-       offset. */
-    LWIP_DEBUGF(IP_REASS_DEBUG,
-     ("ip_reass: copying with offset %"S16_F" into %"S16_F":%"S16_F"\n", offset,
-      IP_HLEN + offset, IP_HLEN + offset + len));
-    i = IPH_HL(fraghdr) * 4;
-    copy_from_pbuf(p, &i, &ip_reassbuf[IP_HLEN + offset], len);
-
-    /* Update the bitmap. */
-    if (offset / (8 * 8) == (offset + len) / (8 * 8)) {
-      LWIP_DEBUGF(IP_REASS_DEBUG,
-       ("ip_reass: updating single byte in bitmap.\n"));
-      /* If the two endpoints are in the same byte, we only update that byte. */
-      LWIP_ASSERT("offset / (8 * 8) < sizeof(ip_reassbitmap)",
-                   offset / (8 * 8) < sizeof(ip_reassbitmap));
-      ip_reassbitmap[offset / (8 * 8)] |=
-        bitmap_bits[(offset / 8) & 7] &
-        ~bitmap_bits[((offset + len) / 8) & 7];
-    } else {
-      /* If the two endpoints are in different bytes, we update the
-         bytes in the endpoints and fill the stuff inbetween with
-         0xff. */
-      LWIP_ASSERT("offset / (8 * 8) < sizeof(ip_reassbitmap)",
-                   offset / (8 * 8) < sizeof(ip_reassbitmap));
-      ip_reassbitmap[offset / (8 * 8)] |= bitmap_bits[(offset / 8) & 7];
-      LWIP_DEBUGF(IP_REASS_DEBUG,
-       ("ip_reass: updating many bytes in bitmap (%"S16_F":%"S16_F").\n",
-        1 + offset / (8 * 8), (offset + len) / (8 * 8)));
-      for (i = 1 + offset / (8 * 8); i < (offset + len) / (8 * 8); ++i) {
-        ip_reassbitmap[i] = 0xff;
-      }
-      LWIP_ASSERT("(offset + len) / (8 * 8) < sizeof(ip_reassbitmap)",
-                   (offset + len) / (8 * 8) < sizeof(ip_reassbitmap));
-      ip_reassbitmap[(offset + len) / (8 * 8)] |=
-        ~bitmap_bits[((offset + len) / 8) & 7];
-    }
-
-    /* If this fragment has the More Fragments flag set to zero, we
-       know that this is the last fragment, so we can calculate the
-       size of the entire packet. We also set the
-       IP_REASS_FLAG_LASTFRAG flag to indicate that we have received
-       the final fragment. */
-
-    if ((ntohs(IPH_OFFSET(fraghdr)) & IP_MF) == 0) {
-      ip_reassflags |= IP_REASS_FLAG_LASTFRAG;
-      ip_reasslen = offset + len;
-      LWIP_DEBUGF(IP_REASS_DEBUG,
-       ("ip_reass: last fragment seen, total len %"S16_F"\n",
-        ip_reasslen));
-    }
-
-    /* Finally, we check if we have a full packet in the buffer. We do
-       this by checking if we have the last fragment and if all bits
-       in the bitmap are set. */
-    if (ip_reassflags & IP_REASS_FLAG_LASTFRAG) {
-      /* Check all bytes up to and including all but the last byte in
-         the bitmap. */
-      LWIP_ASSERT("ip_reasslen / (8 * 8) - 1 < sizeof(ip_reassbitmap)",
-                   ip_reasslen / (8 * 8) - 1 < sizeof(ip_reassbitmap));
-      for (i = 0; i < ip_reasslen / (8 * 8) - 1; ++i) {
-        if (ip_reassbitmap[i] != 0xff) {
-          LWIP_DEBUGF(IP_REASS_DEBUG,
-           ("ip_reass: last fragment seen, bitmap %"S16_F"/%"S16_F" failed (%"X16_F")\n",
-            i, ip_reasslen / (8 * 8) - 1, ip_reassbitmap[i]));
-          goto nullreturn;
-        }
-      }
-      /* Check the last byte in the bitmap. It should contain just the
-         right amount of bits. */
-      LWIP_ASSERT("ip_reasslen / (8 * 8) < sizeof(ip_reassbitmap)",
-                   ip_reasslen / (8 * 8) < sizeof(ip_reassbitmap));
-      if (ip_reassbitmap[ip_reasslen / (8 * 8)] !=
-        (u8_t) ~ bitmap_bits[ip_reasslen / 8 & 7]) {
-         LWIP_DEBUGF(IP_REASS_DEBUG,
-          ("ip_reass: last fragment seen, bitmap %"S16_F" didn't contain %"X16_F" (%"X16_F")\n",
-        ip_reasslen / (8 * 8), ~bitmap_bits[ip_reasslen / 8 & 7],
-        ip_reassbitmap[ip_reasslen / (8 * 8)]));
-        goto nullreturn;
-      }
-
-      /* Pretend to be a "normal" (i.e., not fragmented) IP packet
-         from now on. */
-      ip_reasslen += IP_HLEN;
-
-      IPH_LEN_SET(iphdr, htons(ip_reasslen));
-      IPH_OFFSET_SET(iphdr, 0);
-      IPH_CHKSUM_SET(iphdr, 0);
-      IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN));
-
-      /* If we have come this far, we have a full packet in the
-         buffer, so we allocate a pbuf and copy the packet into it. We
-         also reset the timer. */
-      ip_reasstmr = 0;
-      pbuf_free(p);
-      p = pbuf_alloc(PBUF_LINK, ip_reasslen, PBUF_POOL);
-      if (p != NULL) {
-        i = 0;
-        for (q = p; q != NULL; q = q->next) {
-          /* Copy enough bytes to fill this pbuf in the chain. The
-             available data in the pbuf is given by the q->len variable. */
-          LWIP_DEBUGF(IP_REASS_DEBUG,
-           ("ip_reass: memcpy from %p (%"S16_F") to %p, %"S16_F" bytes\n",
-            (void *)&ip_reassbuf[i], i, q->payload,
-            q->len > ip_reasslen - i ? ip_reasslen - i : q->len));
-          memcpy(q->payload, &ip_reassbuf[i],
-            q->len > ip_reasslen - i ? ip_reasslen - i : q->len);
-          i += q->len;
-        }
-        IPFRAG_STATS_INC(ip_frag.fw);
-      } else {
-        IPFRAG_STATS_INC(ip_frag.memerr);
-      }
-      LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass: p %p\n", (void*)p));
-      return p;
-    }
-  }
-
-nullreturn:
-  IPFRAG_STATS_INC(ip_frag.drop);
-  pbuf_free(p);
-  return NULL;
-}
-
-#define MAX_MTU 1500
-static u8_t buf[MEM_ALIGN_SIZE(MAX_MTU)];
-
-/**
- * Fragment an IP datagram if too large for the netif.
- *
- * Chop the datagram in MTU sized chunks and send them in order
- * by using a fixed size static memory buffer (PBUF_ROM)
- */
-err_t 
-ip_frag(struct pbuf *p, struct netif *netif, struct ip_addr *dest)
-{
-  struct pbuf *rambuf;
-  struct pbuf *header;
-  struct ip_hdr *iphdr;
-  u16_t nfb = 0;
-  u16_t left, cop;
-  u16_t mtu = netif->mtu;
-  u16_t ofo, omf;
-  u16_t last;
-  u16_t poff = IP_HLEN;
-  u16_t tmp;
-
-  /* Get a RAM based MTU sized pbuf */
-  rambuf = pbuf_alloc(PBUF_LINK, 0, PBUF_REF);
-  if (rambuf == NULL) {
-    return ERR_MEM;
-  }
-  rambuf->tot_len = rambuf->len = mtu;
-  rambuf->payload = MEM_ALIGN((void *)buf);
-
-  /* Copy the IP header in it */
-  iphdr = rambuf->payload;
-  memcpy(iphdr, p->payload, IP_HLEN);
-
-  /* Save original offset */
-  tmp = ntohs(IPH_OFFSET(iphdr));
-  ofo = tmp & IP_OFFMASK;
-  omf = tmp & IP_MF;
-
-  left = p->tot_len - IP_HLEN;
-
-  while (left) {
-    last = (left <= mtu - IP_HLEN);
-
-    /* Set new offset and MF flag */
-    ofo += nfb;
-    tmp = omf | (IP_OFFMASK & (ofo));
-    if (!last)
-      tmp = tmp | IP_MF;
-    IPH_OFFSET_SET(iphdr, htons(tmp));
-
-    /* Fill this fragment */
-    nfb = (mtu - IP_HLEN) / 8;
-    cop = last ? left : nfb * 8;
-
-    p = copy_from_pbuf(p, &poff, (u8_t *) iphdr + IP_HLEN, cop);
-
-    /* Correct header */
-    IPH_LEN_SET(iphdr, htons(cop + IP_HLEN));
-    IPH_CHKSUM_SET(iphdr, 0);
-    IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN));
-
-    if (last)
-      pbuf_realloc(rambuf, left + IP_HLEN);
-    /* This part is ugly: we alloc a RAM based pbuf for 
-     * the link level header for each chunk and then 
-     * free it.A PBUF_ROM style pbuf for which pbuf_header
-     * worked would make things simpler.
-     */
-    header = pbuf_alloc(PBUF_LINK, 0, PBUF_RAM);
-    if (header != NULL) {
-      pbuf_chain(header, rambuf);
-      netif->output(netif, header, dest);
-      IPFRAG_STATS_INC(ip_frag.xmit);
-      pbuf_free(header);
-    } else {
-      pbuf_free(rambuf);      
-      return ERR_MEM;    
-    }
-    left -= cop;
-  }
-  pbuf_free(rambuf);
-  return ERR_OK;
-}
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv6/README b/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv6/README
deleted file mode 100644
index 362000486..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv6/README
+++ /dev/null
@@ -1 +0,0 @@
-IPv6 support in lwIP is very experimental.
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv6/icmp6.c b/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv6/icmp6.c
deleted file mode 100644
index 10b6903c4..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv6/icmp6.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels 
- *
- */
-
-/* Some ICMP messages should be passed to the transport protocols. This
-   is not implemented. */
-
-#include "lwip/opt.h"
-
-#include "lwip/icmp.h"
-#include "lwip/inet.h"
-#include "lwip/ip.h"
-#include "lwip/def.h"
-
-#include "lwip/stats.h"
-
-
-void
-icmp_input(struct pbuf *p, struct netif *inp)
-{
-  u8_t type;
-  struct icmp_echo_hdr *iecho;
-  struct ip_hdr *iphdr;
-  struct ip_addr tmpaddr;
-
-#ifdef ICMP_STATS
-  ++lwip_stats.icmp.recv;
-#endif /* ICMP_STATS */
-
-  /* TODO: check length before accessing payload! */
-
-  type = ((u8_t *)p->payload)[0];
-
-  switch (type) {
-  case ICMP6_ECHO:
-    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ping\n"));
-
-    if (p->tot_len < sizeof(struct icmp_echo_hdr)) {
-      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: bad ICMP echo received\n"));
-
-      pbuf_free(p);
-#ifdef ICMP_STATS
-      ++lwip_stats.icmp.lenerr;
-#endif /* ICMP_STATS */
-
-      return;
-    }
-    iecho = p->payload;
-    iphdr = (struct ip_hdr *)((u8_t *)p->payload - IP_HLEN);
-    if (inet_chksum_pbuf(p) != 0) {
-      LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo (%"X16_F")\n", inet_chksum_pseudo(p, &(iphdr->src), &(iphdr->dest), IP_PROTO_ICMP, p->tot_len)));
-
-#ifdef ICMP_STATS
-      ++lwip_stats.icmp.chkerr;
-#endif /* ICMP_STATS */
-    /*      return;*/
-    }
-    LWIP_DEBUGF(ICMP_DEBUG, ("icmp: p->len %"S16_F" p->tot_len %"S16_F"\n", p->len, p->tot_len));
-    ip_addr_set(&tmpaddr, &(iphdr->src));
-    ip_addr_set(&(iphdr->src), &(iphdr->dest));
-    ip_addr_set(&(iphdr->dest), &tmpaddr);
-    iecho->type = ICMP6_ER;
-    /* adjust the checksum */
-    if (iecho->chksum >= htons(0xffff - (ICMP6_ECHO << 8))) {
-      iecho->chksum += htons(ICMP6_ECHO << 8) + 1;
-    } else {
-      iecho->chksum += htons(ICMP6_ECHO << 8);
-    }
-    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo (%"X16_F")\n", inet_chksum_pseudo(p, &(iphdr->src), &(iphdr->dest), IP_PROTO_ICMP, p->tot_len)));
-#ifdef ICMP_STATS
-    ++lwip_stats.icmp.xmit;
-#endif /* ICMP_STATS */
-
-    /*    LWIP_DEBUGF("icmp: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len);*/
-    ip_output_if (p, &(iphdr->src), IP_HDRINCL,
-     iphdr->hoplim, IP_PROTO_ICMP, inp);
-    break;
-  default:
-    LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ICMP type %"S16_F" not supported.\n", (s16_t)type));
-#ifdef ICMP_STATS
-    ++lwip_stats.icmp.proterr;
-    ++lwip_stats.icmp.drop;
-#endif /* ICMP_STATS */
-  }
-
-  pbuf_free(p);
-}
-
-void
-icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t)
-{
-  struct pbuf *q;
-  struct ip_hdr *iphdr;
-  struct icmp_dur_hdr *idur;
-
-  q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM);
-  /* ICMP header + IP header + 8 bytes of data */
-
-  iphdr = p->payload;
-
-  idur = q->payload;
-  idur->type = (u8_t)ICMP6_DUR;
-  idur->icode = (u8_t)t;
-
-  memcpy((u8_t *)q->payload + 8, p->payload, IP_HLEN + 8);
-
-  /* calculate checksum */
-  idur->chksum = 0;
-  idur->chksum = inet_chksum(idur, q->len);
-#ifdef ICMP_STATS
-  ++lwip_stats.icmp.xmit;
-#endif /* ICMP_STATS */
-
-  ip_output(q, NULL,
-      (struct ip_addr *)&(iphdr->src), ICMP_TTL, IP_PROTO_ICMP);
-  pbuf_free(q);
-}
-
-void
-icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t)
-{
-  struct pbuf *q;
-  struct ip_hdr *iphdr;
-  struct icmp_te_hdr *tehdr;
-
-  LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded\n"));
-
-  q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM);
-
-  iphdr = p->payload;
-
-  tehdr = q->payload;
-  tehdr->type = (u8_t)ICMP6_TE;
-  tehdr->icode = (u8_t)t;
-
-  /* copy fields from original packet */
-  memcpy((u8_t *)q->payload + 8, (u8_t *)p->payload, IP_HLEN + 8);
-
-  /* calculate checksum */
-  tehdr->chksum = 0;
-  tehdr->chksum = inet_chksum(tehdr, q->len);
-#ifdef ICMP_STATS
-  ++lwip_stats.icmp.xmit;
-#endif /* ICMP_STATS */
-  ip_output(q, NULL,
-      (struct ip_addr *)&(iphdr->src), ICMP_TTL, IP_PROTO_ICMP);
-  pbuf_free(q);
-}
-
-
-
-
-
-
-
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv6/ip6.c b/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv6/ip6.c
deleted file mode 100644
index 03037c818..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv6/ip6.c
+++ /dev/null
@@ -1,386 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels 
- *
- */
-
-
-
-/* ip.c
- *
- * This is the code for the IP layer for IPv6.
- *
- */
-
-
-#include "lwip/opt.h"
-
-#include "lwip/def.h"
-#include "lwip/mem.h"
-#include "lwip/ip.h"
-#include "lwip/inet.h"
-#include "lwip/netif.h"
-#include "lwip/icmp.h"
-#include "lwip/udp.h"
-#include "lwip/tcp.h"
-
-#include "lwip/stats.h"
-
-#include "arch/perf.h"
-
-/* ip_init:
- *
- * Initializes the IP layer.
- */
-
-void
-ip_init(void)
-{
-}
-
-/* ip_route:
- *
- * Finds the appropriate network interface for a given IP address. It searches the
- * list of network interfaces linearly. A match is found if the masked IP address of
- * the network interface equals the masked IP address given to the function.
- */
-
-struct netif *
-ip_route(struct ip_addr *dest)
-{
-  struct netif *netif;
-
-  for(netif = netif_list; netif != NULL; netif = netif->next) {
-    if (ip_addr_netcmp(dest, &(netif->ip_addr), &(netif->netmask))) {
-      return netif;
-    }
-  }
-
-  return netif_default;
-}
-
-/* ip_forward:
- *
- * Forwards an IP packet. It finds an appropriate route for the packet, decrements
- * the TTL value of the packet, adjusts the checksum and outputs the packet on the
- * appropriate interface.
- */
-
-static void
-ip_forward(struct pbuf *p, struct ip_hdr *iphdr)
-{
-  struct netif *netif;
-
-  PERF_START;
-
-  if ((netif = ip_route((struct ip_addr *)&(iphdr->dest))) == NULL) {
-
-    LWIP_DEBUGF(IP_DEBUG, ("ip_input: no forwarding route found for "));
-#if IP_DEBUG
-    ip_addr_debug_print(IP_DEBUG, &(iphdr->dest));
-#endif /* IP_DEBUG */
-    LWIP_DEBUGF(IP_DEBUG, ("\n"));
-    pbuf_free(p);
-    return;
-  }
-  /* Decrement TTL and send ICMP if ttl == 0. */
-  if (--iphdr->hoplim == 0) {
-    /* Don't send ICMP messages in response to ICMP messages */
-    if (iphdr->nexthdr != IP_PROTO_ICMP) {
-      icmp_time_exceeded(p, ICMP_TE_TTL);
-    }
-    pbuf_free(p);
-    return;
-  }
-
-  /* Incremental update of the IP checksum. */
-  /*  if (iphdr->chksum >= htons(0xffff - 0x100)) {
-    iphdr->chksum += htons(0x100) + 1;
-  } else {
-    iphdr->chksum += htons(0x100);
-    }*/
-
-
-  LWIP_DEBUGF(IP_DEBUG, ("ip_forward: forwarding packet to "));
-#if IP_DEBUG
-  ip_addr_debug_print(IP_DEBUG, &(iphdr->dest));
-#endif /* IP_DEBUG */
-  LWIP_DEBUGF(IP_DEBUG, ("\n"));
-
-#ifdef IP_STATS
-  ++lwip_stats.ip.fw;
-  ++lwip_stats.ip.xmit;
-#endif /* IP_STATS */
-
-  PERF_STOP("ip_forward");
-
-  netif->output(netif, p, (struct ip_addr *)&(iphdr->dest));
-}
-
-/* ip_input:
- *
- * This function is called by the network interface device driver when an IP packet is
- * received. The function does the basic checks of the IP header such as packet size
- * being at least larger than the header size etc. If the packet was not destined for
- * us, the packet is forwarded (using ip_forward). The IP checksum is always checked.
- *
- * Finally, the packet is sent to the upper layer protocol input function.
- */
-
-void
-ip_input(struct pbuf *p, struct netif *inp) {
-  struct ip_hdr *iphdr;
-  struct netif *netif;
-
-
-  PERF_START;
-
-#if IP_DEBUG
-  ip_debug_print(p);
-#endif /* IP_DEBUG */
-
-
-#ifdef IP_STATS
-  ++lwip_stats.ip.recv;
-#endif /* IP_STATS */
-
-  /* identify the IP header */
-  iphdr = p->payload;
-
-
-  if (iphdr->v != 6) {
-    LWIP_DEBUGF(IP_DEBUG, ("IP packet dropped due to bad version number\n"));
-#if IP_DEBUG
-    ip_debug_print(p);
-#endif /* IP_DEBUG */
-    pbuf_free(p);
-#ifdef IP_STATS
-    ++lwip_stats.ip.err;
-    ++lwip_stats.ip.drop;
-#endif /* IP_STATS */
-    return;
-  }
-
-  /* is this packet for us? */
-  for(netif = netif_list; netif != NULL; netif = netif->next) {
-#if IP_DEBUG
-    LWIP_DEBUGF(IP_DEBUG, ("ip_input: iphdr->dest "));
-    ip_addr_debug_print(IP_DEBUG, &(iphdr->dest));
-    LWIP_DEBUGF(IP_DEBUG, ("netif->ip_addr "));
-    ip_addr_debug_print(IP_DEBUG, &(netif->ip_addr));
-    LWIP_DEBUGF(IP_DEBUG, ("\n"));
-#endif /* IP_DEBUG */
-    if (ip_addr_cmp(&(iphdr->dest), &(netif->ip_addr))) {
-      break;
-    }
-  }
-
-
-  if (netif == NULL) {
-    /* packet not for us, route or discard */
-#ifdef IP_FORWARD
-    ip_forward(p, iphdr);
-#endif
-    pbuf_free(p);
-    return;
-  }
-
-  pbuf_realloc(p, IP_HLEN + ntohs(iphdr->len));
-
-  /* send to upper layers */
-#if IP_DEBUG
-  /*  LWIP_DEBUGF("ip_input: \n");
-  ip_debug_print(p);
-  LWIP_DEBUGF("ip_input: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len);*/
-#endif /* IP_DEBUG */
-
-
-  pbuf_header(p, -IP_HLEN);
-
-  switch (iphdr->nexthdr) {
-  case IP_PROTO_UDP:
-    udp_input(p);
-    break;
-  case IP_PROTO_TCP:
-    tcp_input(p);
-    break;
-  case IP_PROTO_ICMP:
-    icmp_input(p, inp);
-    break;
-  default:
-    /* send ICMP destination protocol unreachable */
-    icmp_dest_unreach(p, ICMP_DUR_PROTO);
-    pbuf_free(p);
-    LWIP_DEBUGF(IP_DEBUG, ("Unsupported transport protocol %"U16_F"\n",
-          iphdr->nexthdr));
-
-#ifdef IP_STATS
-    ++lwip_stats.ip.proterr;
-    ++lwip_stats.ip.drop;
-#endif /* IP_STATS */
-
-  }
-  PERF_STOP("ip_input");
-}
-
-
-/* ip_output_if:
- *
- * Sends an IP packet on a network interface. This function constructs the IP header
- * and calculates the IP header checksum. If the source IP address is NULL,
- * the IP address of the outgoing network interface is filled in as source address.
- */
-
-err_t
-ip_output_if (struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
-       u8_t ttl,
-       u8_t proto, struct netif *netif)
-{
-  struct ip_hdr *iphdr;
-
-  PERF_START;
-
-  printf("len %"U16_F" tot_len %"U16_F"\n", p->len, p->tot_len);
-  if (pbuf_header(p, IP_HLEN)) {
-    LWIP_DEBUGF(IP_DEBUG, ("ip_output: not enough room for IP header in pbuf\n"));
-#ifdef IP_STATS
-    ++lwip_stats.ip.err;
-#endif /* IP_STATS */
-
-    return ERR_BUF;
-  }
-  printf("len %"U16_F" tot_len %"U16_F"\n", p->len, p->tot_len);
-
-  iphdr = p->payload;
-
-
-  if (dest != IP_HDRINCL) {
-    printf("!IP_HDRLINCL\n");
-    iphdr->hoplim = ttl;
-    iphdr->nexthdr = proto;
-    iphdr->len = htons(p->tot_len - IP_HLEN);
-    ip_addr_set(&(iphdr->dest), dest);
-
-    iphdr->v = 6;
-
-    if (ip_addr_isany(src)) {
-      ip_addr_set(&(iphdr->src), &(netif->ip_addr));
-    } else {
-      ip_addr_set(&(iphdr->src), src);
-    }
-
-  } else {
-    dest = &(iphdr->dest);
-  }
-
-#ifdef IP_STATS
-  ++lwip_stats.ip.xmit;
-#endif /* IP_STATS */
-
-  LWIP_DEBUGF(IP_DEBUG, ("ip_output_if: %c%c (len %"U16_F")\n", netif->name[0], netif->name[1], p->tot_len));
-#if IP_DEBUG
-  ip_debug_print(p);
-#endif /* IP_DEBUG */
-
-  PERF_STOP("ip_output_if");
-  return netif->output(netif, p, dest);
-}
-
-/* ip_output:
- *
- * Simple interface to ip_output_if. It finds the outgoing network interface and
- * calls upon ip_output_if to do the actual work.
- */
-
-err_t
-ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
-    u8_t ttl, u8_t proto)
-{
-  struct netif *netif;
-  if ((netif = ip_route(dest)) == NULL) {
-    LWIP_DEBUGF(IP_DEBUG, ("ip_output: No route to 0x%"X32_F"\n", dest->addr));
-#ifdef IP_STATS
-    ++lwip_stats.ip.rterr;
-#endif /* IP_STATS */
-    return ERR_RTE;
-  }
-
-  return ip_output_if (p, src, dest, ttl, proto, netif);
-}
-
-#if IP_DEBUG
-void
-ip_debug_print(struct pbuf *p)
-{
-  struct ip_hdr *iphdr = p->payload;
-  u8_t *payload;
-
-  payload = (u8_t *)iphdr + IP_HLEN;
-
-  LWIP_DEBUGF(IP_DEBUG, ("IP header:\n"));
-  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
-  LWIP_DEBUGF(IP_DEBUG, ("|%2"S16_F" |  %"X16_F"%"X16_F"  |      %"X16_F"%"X16_F"           | (v, traffic class, flow label)\n",
-        iphdr->v,
-        iphdr->tclass1, iphdr->tclass2,
-        iphdr->flow1, iphdr->flow2));
-  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
-  LWIP_DEBUGF(IP_DEBUG, ("|    %5"U16_F"      | %2"U16_F"  |  %2"U16_F"   | (len, nexthdr, hoplim)\n",
-        ntohs(iphdr->len),
-        iphdr->nexthdr,
-        iphdr->hoplim));
-  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
-  LWIP_DEBUGF(IP_DEBUG, ("|       %4"X32_F"      |       %4"X32_F"     | (src)\n",
-        ntohl(iphdr->src.addr[0]) >> 16 & 0xffff,
-        ntohl(iphdr->src.addr[0]) & 0xffff));
-  LWIP_DEBUGF(IP_DEBUG, ("|       %4"X32_F"      |       %4"X32_F"     | (src)\n",
-        ntohl(iphdr->src.addr[1]) >> 16 & 0xffff,
-        ntohl(iphdr->src.addr[1]) & 0xffff));
-  LWIP_DEBUGF(IP_DEBUG, ("|       %4"X32_F"      |       %4"X32_F"     | (src)\n",
-        ntohl(iphdr->src.addr[2]) >> 16 & 0xffff,
-        ntohl(iphdr->src.addr[2]) & 0xffff));
-  LWIP_DEBUGF(IP_DEBUG, ("|       %4"X32_F"      |       %4"X32_F"     | (src)\n",
-        ntohl(iphdr->src.addr[3]) >> 16 & 0xffff,
-        ntohl(iphdr->src.addr[3]) & 0xffff));
-  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
-  LWIP_DEBUGF(IP_DEBUG, ("|       %4"X32_F"      |       %4"X32_F"     | (dest)\n",
-        ntohl(iphdr->dest.addr[0]) >> 16 & 0xffff,
-        ntohl(iphdr->dest.addr[0]) & 0xffff));
-  LWIP_DEBUGF(IP_DEBUG, ("|       %4"X32_F"      |       %4"X32_F"     | (dest)\n",
-        ntohl(iphdr->dest.addr[1]) >> 16 & 0xffff,
-        ntohl(iphdr->dest.addr[1]) & 0xffff));
-  LWIP_DEBUGF(IP_DEBUG, ("|       %4"X32_F"      |       %4"X32_F"     | (dest)\n",
-        ntohl(iphdr->dest.addr[2]) >> 16 & 0xffff,
-        ntohl(iphdr->dest.addr[2]) & 0xffff));
-  LWIP_DEBUGF(IP_DEBUG, ("|       %4"X32_F"      |       %4"X32_F"     | (dest)\n",
-        ntohl(iphdr->dest.addr[3]) >> 16 & 0xffff,
-        ntohl(iphdr->dest.addr[3]) & 0xffff));
-  LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n"));
-}
-#endif /* IP_DEBUG */
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv6/ip6_addr.c b/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv6/ip6_addr.c
deleted file mode 100644
index dcb507855..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/core/ipv6/ip6_addr.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-
-#include "lwip/ip_addr.h"
-#include "lwip/inet.h"
-
-
-u8_t
-ip_addr_netcmp(struct ip_addr *addr1, struct ip_addr *addr2,
-                struct ip_addr *mask)
-{
-  return((addr1->addr[0] & mask->addr[0]) == (addr2->addr[0] & mask->addr[0]) &&
-         (addr1->addr[1] & mask->addr[1]) == (addr2->addr[1] & mask->addr[1]) &&
-         (addr1->addr[2] & mask->addr[2]) == (addr2->addr[2] & mask->addr[2]) &&
-         (addr1->addr[3] & mask->addr[3]) == (addr2->addr[3] & mask->addr[3]));
-        
-}
-
-u8_t
-ip_addr_cmp(struct ip_addr *addr1, struct ip_addr *addr2)
-{
-  return(addr1->addr[0] == addr2->addr[0] &&
-         addr1->addr[1] == addr2->addr[1] &&
-         addr1->addr[2] == addr2->addr[2] &&
-         addr1->addr[3] == addr2->addr[3]);
-}
-
-void
-ip_addr_set(struct ip_addr *dest, struct ip_addr *src)
-{
-  memcpy(dest, src, sizeof(struct ip_addr));
-  /*  dest->addr[0] = src->addr[0];
-  dest->addr[1] = src->addr[1];
-  dest->addr[2] = src->addr[2];
-  dest->addr[3] = src->addr[3];*/
-}
-
-u8_t
-ip_addr_isany(struct ip_addr *addr)
-{
-  if (addr == NULL) return 1;
-  return((addr->addr[0] | addr->addr[1] | addr->addr[2] | addr->addr[3]) == 0);
-}
-
-
-/*#if IP_DEBUG*/
-void
-ip_addr_debug_print(struct ip_addr *addr)
-{
-  printf("%"X32_F":%"X32_F":%"X32_F":%"X32_F":%"X32_F":%"X32_F":%"X32_F":%"X32_F",
-         ntohl(addr->addr[0]) >> 16 & 0xffff,
-         ntohl(addr->addr[0]) & 0xffff,
-         ntohl(addr->addr[1]) >> 16 & 0xffff,
-         ntohl(addr->addr[1]) & 0xffff,
-         ntohl(addr->addr[2]) >> 16 & 0xffff,
-         ntohl(addr->addr[2]) & 0xffff,
-         ntohl(addr->addr[3]) >> 16 & 0xffff,
-         ntohl(addr->addr[3]) & 0xffff);
-}
-/*#endif*/ /* IP_DEBUG */
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/core/mem.c b/Demo/lwIP_MCF5235_GCC/lwip/src/core/mem.c
deleted file mode 100644
index b38d8f150..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/core/mem.c
+++ /dev/null
@@ -1,310 +0,0 @@
-/** @file
- *
- * Dynamic memory manager
- *
- */
-
-/* 
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-
-#include 
-
-#include "lwip/arch.h"
-#include "lwip/opt.h"
-#include "lwip/def.h"
-#include "lwip/mem.h"
-
-#include "lwip/sys.h"
-
-#include "lwip/stats.h"
-
-struct mem {
-  mem_size_t next, prev;
-#if MEM_ALIGNMENT == 1
-  u8_t used;
-#elif MEM_ALIGNMENT == 2
-  u16_t used;
-#elif MEM_ALIGNMENT == 4
-  u32_t used;
-#elif MEM_ALIGNMENT == 8
-  u64_t used;
-#else
-#error "unhandled MEM_ALIGNMENT size"
-#endif /* MEM_ALIGNMENT */
-}; 
-
-static struct mem *ram_end;
-static u8_t ram[MEM_SIZE + sizeof(struct mem) + MEM_ALIGNMENT];
-
-#define MIN_SIZE 12
-#if 0 /* this one does not align correctly for some, resulting in crashes */
-#define SIZEOF_STRUCT_MEM (unsigned int)MEM_ALIGN_SIZE(sizeof(struct mem))
-#else
-#define SIZEOF_STRUCT_MEM (sizeof(struct mem) + \
-                          (((sizeof(struct mem) % MEM_ALIGNMENT) == 0)? 0 : \
-                          (4 - (sizeof(struct mem) % MEM_ALIGNMENT))))
-#endif
-
-static struct mem *lfree;   /* pointer to the lowest free block */
-
-static sys_sem_t mem_sem;
-
-static void
-plug_holes(struct mem *mem)
-{
-  struct mem *nmem;
-  struct mem *pmem;
-
-  LWIP_ASSERT("plug_holes: mem >= ram", (u8_t *)mem >= ram);
-  LWIP_ASSERT("plug_holes: mem < ram_end", (u8_t *)mem < (u8_t *)ram_end);
-  LWIP_ASSERT("plug_holes: mem->used == 0", mem->used == 0);
-  
-  /* plug hole forward */
-  LWIP_ASSERT("plug_holes: mem->next <= MEM_SIZE", mem->next <= MEM_SIZE);
-  
-  nmem = (struct mem *)&ram[mem->next];
-  if (mem != nmem && nmem->used == 0 && (u8_t *)nmem != (u8_t *)ram_end) {
-    if (lfree == nmem) {
-      lfree = mem;
-    }
-    mem->next = nmem->next;
-    ((struct mem *)&ram[nmem->next])->prev = (u8_t *)mem - ram;
-  }
-
-  /* plug hole backward */
-  pmem = (struct mem *)&ram[mem->prev];
-  if (pmem != mem && pmem->used == 0) {
-    if (lfree == mem) {
-      lfree = pmem;
-    }
-    pmem->next = mem->next;
-    ((struct mem *)&ram[mem->next])->prev = (u8_t *)pmem - ram;
-  }
-
-}
-void
-mem_init(void)
-{
-  struct mem *mem;
-
-  memset(ram, 0, MEM_SIZE);
-  mem = (struct mem *)ram;
-  mem->next = MEM_SIZE;
-  mem->prev = 0;
-  mem->used = 0;
-  ram_end = (struct mem *)&ram[MEM_SIZE];
-  ram_end->used = 1;
-  ram_end->next = MEM_SIZE;
-  ram_end->prev = MEM_SIZE;
-
-  mem_sem = sys_sem_new(1);
-
-  lfree = (struct mem *)ram;
-
-#if MEM_STATS
-  lwip_stats.mem.avail = MEM_SIZE;
-#endif /* MEM_STATS */
-}
-void
-mem_free(void *rmem)
-{
-  struct mem *mem;
-
-  if (rmem == NULL) {
-    LWIP_DEBUGF(MEM_DEBUG | DBG_TRACE | 2, ("mem_free(p == NULL) was called.\n"));
-    return;
-  }
-  
-  sys_sem_wait(mem_sem);
-
-  LWIP_ASSERT("mem_free: legal memory", (u8_t *)rmem >= (u8_t *)ram &&
-    (u8_t *)rmem < (u8_t *)ram_end);
-  
-  if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) {
-    LWIP_DEBUGF(MEM_DEBUG | 3, ("mem_free: illegal memory\n"));
-#if MEM_STATS
-    ++lwip_stats.mem.err;
-#endif /* MEM_STATS */
-    sys_sem_signal(mem_sem);
-    return;
-  }
-  mem = (struct mem *)((u8_t *)rmem - SIZEOF_STRUCT_MEM);
-
-  LWIP_ASSERT("mem_free: mem->used", mem->used);
-  
-  mem->used = 0;
-
-  if (mem < lfree) {
-    lfree = mem;
-  }
-  
-#if MEM_STATS
-  lwip_stats.mem.used -= mem->next - ((u8_t *)mem - ram);
-  
-#endif /* MEM_STATS */
-  plug_holes(mem);
-  sys_sem_signal(mem_sem);
-}
-void *
-mem_reallocm(void *rmem, mem_size_t newsize)
-{
-  void *nmem;
-  nmem = mem_malloc(newsize);
-  if (nmem == NULL) {
-    return mem_realloc(rmem, newsize);
-  }
-  memcpy(nmem, rmem, newsize);
-  mem_free(rmem);
-  return nmem;
-}
-
-void *
-mem_realloc(void *rmem, mem_size_t newsize)
-{
-  mem_size_t size;
-  mem_size_t ptr, ptr2;
-  struct mem *mem, *mem2;
-
-  /* Expand the size of the allocated memory region so that we can
-     adjust for alignment. */
-  if ((newsize % MEM_ALIGNMENT) != 0) {
-   newsize += MEM_ALIGNMENT - ((newsize + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT);
-  }
-  
-  if (newsize > MEM_SIZE) {
-    return NULL;
-  }
-  
-  sys_sem_wait(mem_sem);
-  
-  LWIP_ASSERT("mem_realloc: legal memory", (u8_t *)rmem >= (u8_t *)ram &&
-   (u8_t *)rmem < (u8_t *)ram_end);
-  
-  if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) {
-    LWIP_DEBUGF(MEM_DEBUG | 3, ("mem_realloc: illegal memory\n"));
-    return rmem;
-  }
-  mem = (struct mem *)((u8_t *)rmem - SIZEOF_STRUCT_MEM);
-
-  ptr = (u8_t *)mem - ram;
-
-  size = mem->next - ptr - SIZEOF_STRUCT_MEM;
-#if MEM_STATS
-  lwip_stats.mem.used -= (size - newsize);
-#endif /* MEM_STATS */
-  
-  if (newsize + SIZEOF_STRUCT_MEM + MIN_SIZE < size) {
-    ptr2 = ptr + SIZEOF_STRUCT_MEM + newsize;
-    mem2 = (struct mem *)&ram[ptr2];
-    mem2->used = 0;
-    mem2->next = mem->next;
-    mem2->prev = ptr;
-    mem->next = ptr2;
-    if (mem2->next != MEM_SIZE) {
-      ((struct mem *)&ram[mem2->next])->prev = ptr2;
-    }
-
-    plug_holes(mem2);
-  }
-  sys_sem_signal(mem_sem);  
-  return rmem;
-}
-void *
-mem_malloc(mem_size_t size)
-{
-  mem_size_t ptr, ptr2;
-  struct mem *mem, *mem2;
-
-  if (size == 0) {
-    return NULL;
-  }
-
-  /* Expand the size of the allocated memory region so that we can
-     adjust for alignment. */
-  if ((size % MEM_ALIGNMENT) != 0) {
-    size += MEM_ALIGNMENT - ((size + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT);
-  }
-  
-  if (size > MEM_SIZE) {
-    return NULL;
-  }
-  
-  sys_sem_wait(mem_sem);
-
-  for (ptr = (u8_t *)lfree - ram; ptr < MEM_SIZE; ptr = ((struct mem *)&ram[ptr])->next) {
-    mem = (struct mem *)&ram[ptr];
-    if (!mem->used &&
-       mem->next - (ptr + SIZEOF_STRUCT_MEM) >= size + SIZEOF_STRUCT_MEM) {
-      ptr2 = ptr + SIZEOF_STRUCT_MEM + size;
-      mem2 = (struct mem *)&ram[ptr2];
-
-      mem2->prev = ptr;      
-      mem2->next = mem->next;
-      mem->next = ptr2;      
-      if (mem2->next != MEM_SIZE) {
-        ((struct mem *)&ram[mem2->next])->prev = ptr2;
-      }
-      
-      mem2->used = 0;      
-      mem->used = 1;
-#if MEM_STATS
-      lwip_stats.mem.used += (size + SIZEOF_STRUCT_MEM);
-      /*      if (lwip_stats.mem.max < lwip_stats.mem.used) {
-        lwip_stats.mem.max = lwip_stats.mem.used;
-  } */
-      if (lwip_stats.mem.max < ptr2) {
-        lwip_stats.mem.max = ptr2;
-      }      
-#endif /* MEM_STATS */
-
-      if (mem == lfree) {
-  /* Find next free block after mem */
-        while (lfree->used && lfree != ram_end) {
-    lfree = (struct mem *)&ram[lfree->next];
-        }
-        LWIP_ASSERT("mem_malloc: !lfree->used", !lfree->used);
-      }
-      sys_sem_signal(mem_sem);
-      LWIP_ASSERT("mem_malloc: allocated memory not above ram_end.",
-       (mem_ptr_t)mem + SIZEOF_STRUCT_MEM + size <= (mem_ptr_t)ram_end);
-      LWIP_ASSERT("mem_malloc: allocated memory properly aligned.",
-       (unsigned long)((u8_t *)mem + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT == 0);
-      return (u8_t *)mem + SIZEOF_STRUCT_MEM;
-    }    
-  }
-  LWIP_DEBUGF(MEM_DEBUG | 2, ("mem_malloc: could not allocate %"S16_F" bytes\n", (s16_t)size));
-#if MEM_STATS
-  ++lwip_stats.mem.err;
-#endif /* MEM_STATS */  
-  sys_sem_signal(mem_sem);
-  return NULL;
-}
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/core/memp.c b/Demo/lwIP_MCF5235_GCC/lwip/src/core/memp.c
deleted file mode 100644
index c0cfce29c..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/core/memp.c
+++ /dev/null
@@ -1,274 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-
-#include "lwip/opt.h"
-
-#include "lwip/memp.h"
-
-#include "lwip/pbuf.h"
-#include "lwip/udp.h"
-#include "lwip/raw.h"
-#include "lwip/tcp.h"
-#include "lwip/api.h"
-#include "lwip/api_msg.h"
-#include "lwip/tcpip.h"
-
-#include "lwip/sys.h"
-#include "lwip/stats.h"
-
-struct memp {
-  struct memp *next;
-};
-
-
-
-static struct memp *memp_tab[MEMP_MAX];
-
-static const u16_t memp_sizes[MEMP_MAX] = {
-  sizeof(struct pbuf),
-  sizeof(struct raw_pcb),
-  sizeof(struct udp_pcb),
-  sizeof(struct tcp_pcb),
-  sizeof(struct tcp_pcb_listen),
-  sizeof(struct tcp_seg),
-  sizeof(struct netbuf),
-  sizeof(struct netconn),
-  sizeof(struct api_msg),
-  sizeof(struct tcpip_msg),
-  sizeof(struct sys_timeout)
-};
-
-static const u16_t memp_num[MEMP_MAX] = {
-  MEMP_NUM_PBUF,
-  MEMP_NUM_RAW_PCB,
-  MEMP_NUM_UDP_PCB,
-  MEMP_NUM_TCP_PCB,
-  MEMP_NUM_TCP_PCB_LISTEN,
-  MEMP_NUM_TCP_SEG,
-  MEMP_NUM_NETBUF,
-  MEMP_NUM_NETCONN,
-  MEMP_NUM_API_MSG,
-  MEMP_NUM_TCPIP_MSG,
-  MEMP_NUM_SYS_TIMEOUT
-};
-
-static u8_t memp_memory[(MEMP_NUM_PBUF *
-       MEM_ALIGN_SIZE(sizeof(struct pbuf) +
-          sizeof(struct memp)) +
-      MEMP_NUM_RAW_PCB *
-       MEM_ALIGN_SIZE(sizeof(struct raw_pcb) +
-          sizeof(struct memp)) +
-      MEMP_NUM_UDP_PCB *
-       MEM_ALIGN_SIZE(sizeof(struct udp_pcb) +
-          sizeof(struct memp)) +
-      MEMP_NUM_TCP_PCB *
-       MEM_ALIGN_SIZE(sizeof(struct tcp_pcb) +
-          sizeof(struct memp)) +
-      MEMP_NUM_TCP_PCB_LISTEN *
-       MEM_ALIGN_SIZE(sizeof(struct tcp_pcb_listen) +
-          sizeof(struct memp)) +
-      MEMP_NUM_TCP_SEG *
-       MEM_ALIGN_SIZE(sizeof(struct tcp_seg) +
-          sizeof(struct memp)) +
-      MEMP_NUM_NETBUF *
-       MEM_ALIGN_SIZE(sizeof(struct netbuf) +
-          sizeof(struct memp)) +
-      MEMP_NUM_NETCONN *
-       MEM_ALIGN_SIZE(sizeof(struct netconn) +
-          sizeof(struct memp)) +
-      MEMP_NUM_API_MSG *
-       MEM_ALIGN_SIZE(sizeof(struct api_msg) +
-          sizeof(struct memp)) +
-      MEMP_NUM_TCPIP_MSG *
-       MEM_ALIGN_SIZE(sizeof(struct tcpip_msg) +
-          sizeof(struct memp)) +
-      MEMP_NUM_SYS_TIMEOUT *
-       MEM_ALIGN_SIZE(sizeof(struct sys_timeout) +
-          sizeof(struct memp)))];
-
-
-#if !SYS_LIGHTWEIGHT_PROT
-static sys_sem_t mutex;
-#endif
-
-#if MEMP_SANITY_CHECK
-static int
-memp_sanity(void)
-{
-  s16_t i, c;
-  struct memp *m, *n;
-
-  for(i = 0; i < MEMP_MAX; i++) {
-    for(m = memp_tab[i]; m != NULL; m = m->next) {
-      c = 1;
-      for(n = memp_tab[i]; n != NULL; n = n->next) {
-         if (n == m) {
-          --c;
-        }
-        if (c < 0) return 0; /* LW was: abort(); */
-      }
-    }
-  }
-  return 1;
-}
-#endif /* MEMP_SANITY_CHECK*/
-
-void
-memp_init(void)
-{
-  struct memp *m, *memp;
-  u16_t i, j;
-  u16_t size;
-      
-#if MEMP_STATS
-  for(i = 0; i < MEMP_MAX; ++i) {
-    lwip_stats.memp[i].used = lwip_stats.memp[i].max =
-      lwip_stats.memp[i].err = 0;
-    lwip_stats.memp[i].avail = memp_num[i];
-  }
-#endif /* MEMP_STATS */
-
-  memp = (struct memp *)&memp_memory[0];
-  for(i = 0; i < MEMP_MAX; ++i) {
-    size = MEM_ALIGN_SIZE(memp_sizes[i] + sizeof(struct memp));
-    if (memp_num[i] > 0) {
-      memp_tab[i] = memp;
-      m = memp;
-      
-      for(j = 0; j < memp_num[i]; ++j) {
-  m->next = (struct memp *)MEM_ALIGN((u8_t *)m + size);
-  memp = m;
-  m = m->next;
-      }
-      memp->next = NULL;
-      memp = m;
-    } else {
-      memp_tab[i] = NULL;
-    }
-  }
-
-#if !SYS_LIGHTWEIGHT_PROT
-  mutex = sys_sem_new(1);
-#endif
-
-  
-}
-
-void *
-memp_malloc(memp_t type)
-{
-  struct memp *memp;
-  void *mem;
-#if SYS_LIGHTWEIGHT_PROT
-  SYS_ARCH_DECL_PROTECT(old_level);
-#endif
- 
-  LWIP_ASSERT("memp_malloc: type < MEMP_MAX", type < MEMP_MAX);
-
-#if SYS_LIGHTWEIGHT_PROT
-  SYS_ARCH_PROTECT(old_level);
-#else /* SYS_LIGHTWEIGHT_PROT */  
-  sys_sem_wait(mutex);
-#endif /* SYS_LIGHTWEIGHT_PROT */  
-
-  memp = memp_tab[type];
-  
-  if (memp != NULL) {    
-    memp_tab[type] = memp->next;    
-    memp->next = NULL;
-#if MEMP_STATS
-    ++lwip_stats.memp[type].used;
-    if (lwip_stats.memp[type].used > lwip_stats.memp[type].max) {
-      lwip_stats.memp[type].max = lwip_stats.memp[type].used;
-    }
-#endif /* MEMP_STATS */
-#if SYS_LIGHTWEIGHT_PROT
-    SYS_ARCH_UNPROTECT(old_level);
-#else /* SYS_LIGHTWEIGHT_PROT */
-    sys_sem_signal(mutex);
-#endif /* SYS_LIGHTWEIGHT_PROT */  
-    LWIP_ASSERT("memp_malloc: memp properly aligned",
-     ((mem_ptr_t)MEM_ALIGN((u8_t *)memp + sizeof(struct memp)) % MEM_ALIGNMENT) == 0);
-
-    mem = MEM_ALIGN((u8_t *)memp + sizeof(struct memp));
-    return mem;
-  } else {
-    LWIP_DEBUGF(MEMP_DEBUG | 2, ("memp_malloc: out of memory in pool %"S16_F"\n", type));
-#if MEMP_STATS
-    ++lwip_stats.memp[type].err;
-#endif /* MEMP_STATS */
-#if SYS_LIGHTWEIGHT_PROT
-  SYS_ARCH_UNPROTECT(old_level);
-#else /* SYS_LIGHTWEIGHT_PROT */
-  sys_sem_signal(mutex);
-#endif /* SYS_LIGHTWEIGHT_PROT */  
-    return NULL;
-  }
-}
-
-void
-memp_free(memp_t type, void *mem)
-{
-  struct memp *memp;
-#if SYS_LIGHTWEIGHT_PROT
-  SYS_ARCH_DECL_PROTECT(old_level);
-#endif /* SYS_LIGHTWEIGHT_PROT */  
-
-  if (mem == NULL) {
-    return;
-  }
-  memp = (struct memp *)((u8_t *)mem - sizeof(struct memp));
-
-#if SYS_LIGHTWEIGHT_PROT
-    SYS_ARCH_PROTECT(old_level);
-#else /* SYS_LIGHTWEIGHT_PROT */  
-  sys_sem_wait(mutex);
-#endif /* SYS_LIGHTWEIGHT_PROT */  
-
-#if MEMP_STATS
-  lwip_stats.memp[type].used--; 
-#endif /* MEMP_STATS */
-  
-  memp->next = memp_tab[type]; 
-  memp_tab[type] = memp;
-
-#if MEMP_SANITY_CHECK
-  LWIP_ASSERT("memp sanity", memp_sanity());
-#endif  
-
-#if SYS_LIGHTWEIGHT_PROT
-  SYS_ARCH_UNPROTECT(old_level);
-#else /* SYS_LIGHTWEIGHT_PROT */
-  sys_sem_signal(mutex);
-#endif /* SYS_LIGHTWEIGHT_PROT */  
-}
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/core/netif.c b/Demo/lwIP_MCF5235_GCC/lwip/src/core/netif.c
deleted file mode 100644
index 3525089b2..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/core/netif.c
+++ /dev/null
@@ -1,288 +0,0 @@
-/**
- * @file
- *
- * lwIP network interface abstraction
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels 
- *
- */
-
-#include "lwip/opt.h"
-
-#include "lwip/def.h"
-#include "lwip/ip_addr.h"
-#include "lwip/netif.h"
-#include "lwip/tcp.h"
-
-struct netif *netif_list = NULL;
-struct netif *netif_default = NULL;
-
-/**
- * Add a network interface to the list of lwIP netifs.
- *
- * @param netif a pre-allocated netif structure
- * @param ipaddr IP address for the new netif
- * @param netmask network mask for the new netif
- * @param gw default gateway IP address for the new netif
- * @param state opaque data passed to the new netif
- * @param init callback function that initializes the interface
- * @param input callback function that is called to pass
- * ingress packets up in the protocol layer stack.
- *
- * @return netif, or NULL if failed.
- */
-struct netif *
-netif_add(struct netif *netif, struct ip_addr *ipaddr, struct ip_addr *netmask,
-  struct ip_addr *gw,
-  void *state,
-  err_t (* init)(struct netif *netif),
-  err_t (* input)(struct pbuf *p, struct netif *netif))
-{
-  static s16_t netifnum = 0;
-  
-#if LWIP_DHCP
-  /* netif not under DHCP control by default */
-  netif->dhcp = NULL;
-#endif
-  /* remember netif specific state information data */
-  netif->state = state;
-  netif->num = netifnum++;
-  netif->input = input;
-
-  netif_set_addr(netif, ipaddr, netmask, gw);
-
-  /* call user specified initialization function for netif */
-  if (init(netif) != ERR_OK) {
-    return NULL;
-  }
-
-  /* add this netif to the list */
-  netif->next = netif_list;
-  netif_list = netif;
-  LWIP_DEBUGF(NETIF_DEBUG, ("netif: added interface %c%c IP addr ",
-    netif->name[0], netif->name[1]));
-  ip_addr_debug_print(NETIF_DEBUG, ipaddr);
-  LWIP_DEBUGF(NETIF_DEBUG, (" netmask "));
-  ip_addr_debug_print(NETIF_DEBUG, netmask);
-  LWIP_DEBUGF(NETIF_DEBUG, (" gw "));
-  ip_addr_debug_print(NETIF_DEBUG, gw);
-  LWIP_DEBUGF(NETIF_DEBUG, ("\n"));
-  return netif;
-}
-
-void
-netif_set_addr(struct netif *netif,struct ip_addr *ipaddr, struct ip_addr *netmask,
-    struct ip_addr *gw)
-{
-  netif_set_ipaddr(netif, ipaddr);
-  netif_set_netmask(netif, netmask);
-  netif_set_gw(netif, gw);
-}
-
-void netif_remove(struct netif * netif)
-{
-  if ( netif == NULL ) return;
-
-  /*  is it the first netif? */
-  if (netif_list == netif) {
-    netif_list = netif->next;
-  }
-  else {
-    /*  look for netif further down the list */
-    struct netif * tmpNetif;
-    for (tmpNetif = netif_list; tmpNetif != NULL; tmpNetif = tmpNetif->next) {
-      if (tmpNetif->next == netif) {
-        tmpNetif->next = netif->next;
-        break;
-        }
-    }
-    if (tmpNetif == NULL)
-      return; /*  we didn't find any netif today */
-  }
-  /* this netif is default? */
-  if (netif_default == netif)
-    /* reset default netif */
-    netif_default = NULL;
-  LWIP_DEBUGF( NETIF_DEBUG, ("netif_remove: removed netif\n") );
-}
-
-struct netif *
-netif_find(char *name)
-{
-  struct netif *netif;
-  u8_t num;
-
-  if (name == NULL) {
-    return NULL;
-  }
-
-  num = name[2] - '0';
-
-  for(netif = netif_list; netif != NULL; netif = netif->next) {
-    if (num == netif->num &&
-       name[0] == netif->name[0] &&
-       name[1] == netif->name[1]) {
-      LWIP_DEBUGF(NETIF_DEBUG, ("netif_find: found %c%c\n", name[0], name[1]));
-      return netif;
-    }
-  }
-  LWIP_DEBUGF(NETIF_DEBUG, ("netif_find: didn't find %c%c\n", name[0], name[1]));
-  return NULL;
-}
-
-void
-netif_set_ipaddr(struct netif *netif, struct ip_addr *ipaddr)
-{
-  /* TODO: Handling of obsolete pcbs */
-  /* See:  http://mail.gnu.org/archive/html/lwip-users/2003-03/msg00118.html */
-#if LWIP_TCP
-  struct tcp_pcb *pcb;
-  struct tcp_pcb_listen *lpcb;
-
-  /* address is actually being changed? */
-  if ((ip_addr_cmp(ipaddr, &(netif->ip_addr))) == 0)
-  {
-    /* extern struct tcp_pcb *tcp_active_pcbs; defined by tcp.h */
-    LWIP_DEBUGF(NETIF_DEBUG | 1, ("netif_set_ipaddr: netif address being changed\n"));
-    pcb = tcp_active_pcbs;
-    while (pcb != NULL) {
-      /* PCB bound to current local interface address? */
-      if (ip_addr_cmp(&(pcb->local_ip), &(netif->ip_addr))) {
-        /* this connection must be aborted */
-        struct tcp_pcb *next = pcb->next;
-        LWIP_DEBUGF(NETIF_DEBUG | 1, ("netif_set_ipaddr: aborting TCP pcb %p\n", (void *)pcb));
-        tcp_abort(pcb);
-        pcb = next;
-      } else {
-        pcb = pcb->next;
-      }
-    }
-    for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
-      /* PCB bound to current local interface address? */
-      if (ip_addr_cmp(&(lpcb->local_ip), &(netif->ip_addr))) {
-        /* The PCB is listening to the old ipaddr and
-         * is set to listen to the new one instead */
-        ip_addr_set(&(lpcb->local_ip), ipaddr);
-      }
-    }
-  }
-#endif
-  ip_addr_set(&(netif->ip_addr), ipaddr);
-#if 0 /* only allowed for Ethernet interfaces TODO: how can we check? */
-  /** For Ethernet network interfaces, we would like to send a
-   *  "gratuitous ARP"; this is an ARP packet sent by a node in order
-   *  to spontaneously cause other nodes to update an entry in their
-   *  ARP cache. From RFC 3220 "IP Mobility Support for IPv4" section 4.6.
-   */ 
-  etharp_query(netif, ipaddr, NULL);
-#endif
-  LWIP_DEBUGF(NETIF_DEBUG | DBG_TRACE | DBG_STATE | 3, ("netif: IP address of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
-    netif->name[0], netif->name[1],
-    ip4_addr1(&netif->ip_addr),
-    ip4_addr2(&netif->ip_addr),
-    ip4_addr3(&netif->ip_addr),
-    ip4_addr4(&netif->ip_addr)));
-}
-
-void
-netif_set_gw(struct netif *netif, struct ip_addr *gw)
-{
-  ip_addr_set(&(netif->gw), gw);
-  LWIP_DEBUGF(NETIF_DEBUG | DBG_TRACE | DBG_STATE | 3, ("netif: GW address of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
-    netif->name[0], netif->name[1],
-    ip4_addr1(&netif->gw),
-    ip4_addr2(&netif->gw),
-    ip4_addr3(&netif->gw),
-    ip4_addr4(&netif->gw)));
-}
-
-void
-netif_set_netmask(struct netif *netif, struct ip_addr *netmask)
-{
-  ip_addr_set(&(netif->netmask), netmask);
-  LWIP_DEBUGF(NETIF_DEBUG | DBG_TRACE | DBG_STATE | 3, ("netif: netmask of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
-    netif->name[0], netif->name[1],
-    ip4_addr1(&netif->netmask),
-    ip4_addr2(&netif->netmask),
-    ip4_addr3(&netif->netmask),
-    ip4_addr4(&netif->netmask)));
-}
-
-void
-netif_set_default(struct netif *netif)
-{
-  netif_default = netif;
-  LWIP_DEBUGF(NETIF_DEBUG, ("netif: setting default interface %c%c\n",
-           netif ? netif->name[0] : '\'', netif ? netif->name[1] : '\''));
-}
-
-/**
- * Bring an interface up, available for processing
- * traffic.
- * 
- * @note: Enabling DHCP on a down interface will make it come
- * up once configured.
- * 
- * @see dhcp_start()
- */ 
-void netif_set_up(struct netif *netif)
-{
-  netif->flags |= NETIF_FLAG_UP;
-}
-
-/**
- * Ask if an interface is up
- */ 
-u8_t netif_is_up(struct netif *netif)
-{
-  return (netif->flags & NETIF_FLAG_UP)?1:0;
-}
-
-/**
- * Bring an interface down, disabling any traffic processing.
- *
- * @note: Enabling DHCP on a down interface will make it come
- * up once configured.
- * 
- * @see dhcp_start()
- */ 
-void netif_set_down(struct netif *netif)
-{
-  netif->flags &= ~NETIF_FLAG_UP;
-}
-
-void
-netif_init(void)
-{
-  netif_list = netif_default = NULL;
-}
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/core/pbuf.c b/Demo/lwIP_MCF5235_GCC/lwip/src/core/pbuf.c
deleted file mode 100644
index 2ece4b098..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/core/pbuf.c
+++ /dev/null
@@ -1,957 +0,0 @@
-/**
- * @file
- * Packet buffer management
- *
- * Packets are built from the pbuf data structure. It supports dynamic
- * memory allocation for packet contents or can reference externally
- * managed packet contents both in RAM and ROM. Quick allocation for
- * incoming packets is provided through pools with fixed sized pbufs.
- *
- * A packet may span over multiple pbufs, chained as a singly linked
- * list. This is called a "pbuf chain".
- *
- * Multiple packets may be queued, also using this singly linked list.
- * This is called a "packet queue".
- * 
- * So, a packet queue consists of one or more pbuf chains, each of
- * which consist of one or more pbufs. Currently, queues are only
- * supported in a limited section of lwIP, this is the etharp queueing
- * code. Outside of this section no packet queues are supported yet.
- * 
- * The differences between a pbuf chain and a packet queue are very
- * precise but subtle. 
- *
- * The last pbuf of a packet has a ->tot_len field that equals the
- * ->len field. It can be found by traversing the list. If the last
- * pbuf of a packet has a ->next field other than NULL, more packets
- * are on the queue.
- *
- * Therefore, looping through a pbuf of a single packet, has an
- * loop end condition (tot_len == p->len), NOT (next == NULL).
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels 
- *
- */
-
-#include 
-
-#include "lwip/opt.h"
-#include "lwip/stats.h"
-#include "lwip/def.h"
-#include "lwip/mem.h"
-#include "lwip/memp.h"
-#include "lwip/pbuf.h"
-#include "lwip/sys.h"
-#include "arch/perf.h"
-
-static u8_t pbuf_pool_memory[MEM_ALIGNMENT - 1 + PBUF_POOL_SIZE * MEM_ALIGN_SIZE(PBUF_POOL_BUFSIZE + sizeof(struct pbuf))];
-
-#if !SYS_LIGHTWEIGHT_PROT
-static volatile u8_t pbuf_pool_free_lock, pbuf_pool_alloc_lock;
-static sys_sem_t pbuf_pool_free_sem;
-#endif
-
-static struct pbuf *pbuf_pool = NULL;
-
-/**
- * Initializes the pbuf module.
- *
- * A large part of memory is allocated for holding the pool of pbufs.
- * The size of the individual pbufs in the pool is given by the size
- * parameter, and the number of pbufs in the pool by the num parameter.
- *
- * After the memory has been allocated, the pbufs are set up. The
- * ->next pointer in each pbuf is set up to point to the next pbuf in
- * the pool.
- *
- */
-void
-pbuf_init(void)
-{
-  struct pbuf *p, *q = NULL;
-  u16_t i;
-
-  pbuf_pool = (struct pbuf *)MEM_ALIGN(pbuf_pool_memory);
-
-#if PBUF_STATS
-  lwip_stats.pbuf.avail = PBUF_POOL_SIZE;
-#endif /* PBUF_STATS */
-
-  /* Set up ->next pointers to link the pbufs of the pool together */
-  p = pbuf_pool;
-
-  for(i = 0; i < PBUF_POOL_SIZE; ++i) {
-    p->next = (struct pbuf *)((u8_t *)p + PBUF_POOL_BUFSIZE + sizeof(struct pbuf));
-    p->len = p->tot_len = PBUF_POOL_BUFSIZE;
-    p->payload = MEM_ALIGN((void *)((u8_t *)p + sizeof(struct pbuf)));
-    p->flags = PBUF_FLAG_POOL;
-    q = p;
-    p = p->next;
-  }
-
-  /* The ->next pointer of last pbuf is NULL to indicate that there
-     are no more pbufs in the pool */
-  q->next = NULL;
-
-#if !SYS_LIGHTWEIGHT_PROT
-  pbuf_pool_alloc_lock = 0;
-  pbuf_pool_free_lock = 0;
-  pbuf_pool_free_sem = sys_sem_new(1);
-#endif
-}
-
-/**
- * @internal only called from pbuf_alloc()
- */
-static struct pbuf *
-pbuf_pool_alloc(void)
-{
-  struct pbuf *p = NULL;
-
-  SYS_ARCH_DECL_PROTECT(old_level);
-  SYS_ARCH_PROTECT(old_level);
-
-#if !SYS_LIGHTWEIGHT_PROT
-  /* Next, check the actual pbuf pool, but if the pool is locked, we
-     pretend to be out of buffers and return NULL. */
-  if (pbuf_pool_free_lock) {
-#if PBUF_STATS
-    ++lwip_stats.pbuf.alloc_locked;
-#endif /* PBUF_STATS */
-    return NULL;
-  }
-  pbuf_pool_alloc_lock = 1;
-  if (!pbuf_pool_free_lock) {
-#endif /* SYS_LIGHTWEIGHT_PROT */
-    p = pbuf_pool;
-    if (p) {
-      pbuf_pool = p->next;
-    }
-#if !SYS_LIGHTWEIGHT_PROT
-#if PBUF_STATS
-  } else {
-    ++lwip_stats.pbuf.alloc_locked;
-#endif /* PBUF_STATS */
-  }
-  pbuf_pool_alloc_lock = 0;
-#endif /* SYS_LIGHTWEIGHT_PROT */
-
-#if PBUF_STATS
-  if (p != NULL) {
-    ++lwip_stats.pbuf.used;
-    if (lwip_stats.pbuf.used > lwip_stats.pbuf.max) {
-      lwip_stats.pbuf.max = lwip_stats.pbuf.used;
-    }
-  }
-#endif /* PBUF_STATS */
-
-  SYS_ARCH_UNPROTECT(old_level);
-  return p;
-}
-
-
-/**
- * Allocates a pbuf of the given type (possibly a chain for PBUF_POOL type).
- *
- * The actual memory allocated for the pbuf is determined by the
- * layer at which the pbuf is allocated and the requested size
- * (from the size parameter).
- *
- * @param flag this parameter decides how and where the pbuf
- * should be allocated as follows:
- *
- * - PBUF_RAM: buffer memory for pbuf is allocated as one large
- *             chunk. This includes protocol headers as well.
- * - PBUF_ROM: no buffer memory is allocated for the pbuf, even for
- *             protocol headers. Additional headers must be prepended
- *             by allocating another pbuf and chain in to the front of
- *             the ROM pbuf. It is assumed that the memory used is really
- *             similar to ROM in that it is immutable and will not be
- *             changed. Memory which is dynamic should generally not
- *             be attached to PBUF_ROM pbufs. Use PBUF_REF instead.
- * - PBUF_REF: no buffer memory is allocated for the pbuf, even for
- *             protocol headers. It is assumed that the pbuf is only
- *             being used in a single thread. If the pbuf gets queued,
- *             then pbuf_take should be called to copy the buffer.
- * - PBUF_POOL: the pbuf is allocated as a pbuf chain, with pbufs from
- *              the pbuf pool that is allocated during pbuf_init().
- *
- * @return the allocated pbuf. If multiple pbufs where allocated, this
- * is the first pbuf of a pbuf chain.
- */
-struct pbuf *
-pbuf_alloc(pbuf_layer l, u16_t length, pbuf_flag flag)
-{
-  struct pbuf *p, *q, *r;
-  u16_t offset;
-  s32_t rem_len; /* remaining length */
-  LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_alloc(length=%"U16_F")\n", length));
-
-  /* determine header offset */
-  offset = 0;
-  switch (l) {
-  case PBUF_TRANSPORT:
-    /* add room for transport (often TCP) layer header */
-    offset += PBUF_TRANSPORT_HLEN;
-    /* FALLTHROUGH */
-  case PBUF_IP:
-    /* add room for IP layer header */
-    offset += PBUF_IP_HLEN;
-    /* FALLTHROUGH */
-  case PBUF_LINK:
-    /* add room for link layer header */
-    offset += PBUF_LINK_HLEN;
-    break;
-  case PBUF_RAW:
-    break;
-  default:
-    LWIP_ASSERT("pbuf_alloc: bad pbuf layer", 0);
-    return NULL;
-  }
-
-  switch (flag) {
-  case PBUF_POOL:
-    /* allocate head of pbuf chain into p */
-    p = pbuf_pool_alloc();
-    LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_alloc: allocated pbuf %p\n", (void *)p));
-    if (p == NULL) {
-#if PBUF_STATS
-      ++lwip_stats.pbuf.err;
-#endif /* PBUF_STATS */
-      return NULL;
-    }
-    p->next = NULL;
-
-    /* make the payload pointer point 'offset' bytes into pbuf data memory */
-    p->payload = MEM_ALIGN((void *)((u8_t *)p + (sizeof(struct pbuf) + offset)));
-    LWIP_ASSERT("pbuf_alloc: pbuf p->payload properly aligned",
-            ((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0);
-    /* the total length of the pbuf chain is the requested size */
-    p->tot_len = length;
-    /* set the length of the first pbuf in the chain */
-    p->len = length > PBUF_POOL_BUFSIZE - offset? PBUF_POOL_BUFSIZE - offset: length;
-    /* set reference count (needed here in case we fail) */
-    p->ref = 1;
-
-    /* now allocate the tail of the pbuf chain */
-
-    /* remember first pbuf for linkage in next iteration */
-    r = p;
-    /* remaining length to be allocated */
-    rem_len = length - p->len;
-    /* any remaining pbufs to be allocated? */
-    while (rem_len > 0) {
-      q = pbuf_pool_alloc();
-      if (q == NULL) {
-       LWIP_DEBUGF(PBUF_DEBUG | 2, ("pbuf_alloc: Out of pbufs in pool.\n"));
-#if PBUF_STATS
-        ++lwip_stats.pbuf.err;
-#endif /* PBUF_STATS */
-        /* free chain so far allocated */
-        pbuf_free(p);
-        /* bail out unsuccesfully */
-        return NULL;
-      }
-      q->next = NULL;
-      /* make previous pbuf point to this pbuf */
-      r->next = q;
-      /* set total length of this pbuf and next in chain */
-      q->tot_len = rem_len;
-      /* this pbuf length is pool size, unless smaller sized tail */
-      q->len = rem_len > PBUF_POOL_BUFSIZE? PBUF_POOL_BUFSIZE: rem_len;
-      q->payload = (void *)((u8_t *)q + sizeof(struct pbuf));
-      LWIP_ASSERT("pbuf_alloc: pbuf q->payload properly aligned",
-              ((mem_ptr_t)q->payload % MEM_ALIGNMENT) == 0);
-      q->ref = 1;
-      /* calculate remaining length to be allocated */
-      rem_len -= q->len;
-      /* remember this pbuf for linkage in next iteration */
-      r = q;
-    }
-    /* end of chain */
-    /*r->next = NULL;*/
-
-    break;
-  case PBUF_RAM:
-    /* If pbuf is to be allocated in RAM, allocate memory for it. */
-    p = mem_malloc(MEM_ALIGN_SIZE(sizeof(struct pbuf) + offset) + MEM_ALIGN_SIZE(length));
-    if (p == NULL) {
-      return NULL;
-    }
-    /* Set up internal structure of the pbuf. */
-    p->payload = MEM_ALIGN((void *)((u8_t *)p + sizeof(struct pbuf) + offset));
-    p->len = p->tot_len = length;
-    p->next = NULL;
-    p->flags = PBUF_FLAG_RAM;
-
-    LWIP_ASSERT("pbuf_alloc: pbuf->payload properly aligned",
-           ((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0);
-    break;
-  /* pbuf references existing (non-volatile static constant) ROM payload? */
-  case PBUF_ROM:
-  /* pbuf references existing (externally allocated) RAM payload? */
-  case PBUF_REF:
-    /* only allocate memory for the pbuf structure */
-    p = memp_malloc(MEMP_PBUF);
-    if (p == NULL) {
-      LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_alloc: Could not allocate MEMP_PBUF for PBUF_%s.\n", flag == PBUF_ROM?"ROM":"REF"));
-      return NULL;
-    }
-    /* caller must set this field properly, afterwards */
-    p->payload = NULL;
-    p->len = p->tot_len = length;
-    p->next = NULL;
-    p->flags = (flag == PBUF_ROM? PBUF_FLAG_ROM: PBUF_FLAG_REF);
-    break;
-  default:
-    LWIP_ASSERT("pbuf_alloc: erroneous flag", 0);
-    return NULL;
-  }
-  /* set reference count */
-  p->ref = 1;
-  LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_alloc(length=%"U16_F") == %p\n", length, (void *)p));
-  return p;
-}
-
-
-#if PBUF_STATS
-#define DEC_PBUF_STATS do { --lwip_stats.pbuf.used; } while (0)
-#else /* PBUF_STATS */
-#define DEC_PBUF_STATS
-#endif /* PBUF_STATS */
-
-#define PBUF_POOL_FAST_FREE(p)  do {                                    \
-                                  p->next = pbuf_pool;                  \
-                                  pbuf_pool = p;                        \
-                                  DEC_PBUF_STATS;                       \
-                                } while (0)
-
-#if SYS_LIGHTWEIGHT_PROT
-#define PBUF_POOL_FREE(p)  do {                                         \
-                                SYS_ARCH_DECL_PROTECT(old_level);       \
-                                SYS_ARCH_PROTECT(old_level);            \
-                                PBUF_POOL_FAST_FREE(p);                 \
-                                SYS_ARCH_UNPROTECT(old_level);          \
-                               } while (0)
-#else /* SYS_LIGHTWEIGHT_PROT */
-#define PBUF_POOL_FREE(p)  do {                                         \
-                             sys_sem_wait(pbuf_pool_free_sem);          \
-                             PBUF_POOL_FAST_FREE(p);                    \
-                             sys_sem_signal(pbuf_pool_free_sem);        \
-                           } while (0)
-#endif /* SYS_LIGHTWEIGHT_PROT */
-
-/**
- * Shrink a pbuf chain to a desired length.
- *
- * @param p pbuf to shrink.
- * @param new_len desired new length of pbuf chain
- *
- * Depending on the desired length, the first few pbufs in a chain might
- * be skipped and left unchanged. The new last pbuf in the chain will be
- * resized, and any remaining pbufs will be freed.
- *
- * @note If the pbuf is ROM/REF, only the ->tot_len and ->len fields are adjusted.
- * @note May not be called on a packet queue.
- *
- * @bug Cannot grow the size of a pbuf (chain) (yet).
- */
-void
-pbuf_realloc(struct pbuf *p, u16_t new_len)
-{
-  struct pbuf *q;
-  u16_t rem_len; /* remaining length */
-  s16_t grow;
-
-  LWIP_ASSERT("pbuf_realloc: sane p->flags", p->flags == PBUF_FLAG_POOL ||
-              p->flags == PBUF_FLAG_ROM ||
-              p->flags == PBUF_FLAG_RAM ||
-              p->flags == PBUF_FLAG_REF);
-
-  /* desired length larger than current length? */
-  if (new_len >= p->tot_len) {
-    /* enlarging not yet supported */
-    return;
-  }
-
-  /* the pbuf chain grows by (new_len - p->tot_len) bytes
-   * (which may be negative in case of shrinking) */
-  grow = new_len - p->tot_len;
-
-  /* first, step over any pbufs that should remain in the chain */
-  rem_len = new_len;
-  q = p;
-  /* should this pbuf be kept? */
-  while (rem_len > q->len) {
-    /* decrease remaining length by pbuf length */
-    rem_len -= q->len;
-    /* decrease total length indicator */
-    q->tot_len += grow;
-    /* proceed to next pbuf in chain */
-    q = q->next;
-  }
-  /* we have now reached the new last pbuf (in q) */
-  /* rem_len == desired length for pbuf q */
-
-  /* shrink allocated memory for PBUF_RAM */
-  /* (other types merely adjust their length fields */
-  if ((q->flags == PBUF_FLAG_RAM) && (rem_len != q->len)) {
-    /* reallocate and adjust the length of the pbuf that will be split */
-    mem_realloc(q, (u8_t *)q->payload - (u8_t *)q + rem_len);
-  }
-  /* adjust length fields for new last pbuf */
-  q->len = rem_len;
-  q->tot_len = q->len;
-
-  /* any remaining pbufs in chain? */
-  if (q->next != NULL) {
-    /* free remaining pbufs in chain */
-    pbuf_free(q->next);
-  }
-  /* q is last packet in chain */
-  q->next = NULL;
-
-}
-
-/**
- * Adjusts the payload pointer to hide or reveal headers in the payload.
- *
- * Adjusts the ->payload pointer so that space for a header
- * (dis)appears in the pbuf payload.
- *
- * The ->payload, ->tot_len and ->len fields are adjusted.
- *
- * @param hdr_size_inc Number of bytes to increment header size which
- * increases the size of the pbuf. New space is on the front.
- * (Using a negative value decreases the header size.)
- * If hdr_size_inc is 0, this function does nothing and returns succesful.
- *
- * PBUF_ROM and PBUF_REF type buffers cannot have their sizes increased, so
- * the call will fail. A check is made that the increase in header size does
- * not move the payload pointer in front of the start of the buffer.
- * @return non-zero on failure, zero on success.
- *
- */
-u8_t
-pbuf_header(struct pbuf *p, s16_t header_size_increment)
-{
-  void *payload;
-
-  LWIP_ASSERT("p != NULL", p != NULL);
-  if ((header_size_increment == 0) || (p == NULL)) return 0;
- 
-  /* remember current payload pointer */
-  payload = p->payload;
-
-  /* pbuf types containing payloads? */
-  if (p->flags == PBUF_FLAG_RAM || p->flags == PBUF_FLAG_POOL) {
-    /* set new payload pointer */
-    p->payload = (u8_t *)p->payload - header_size_increment;
-    /* boundary check fails? */
-    if ((u8_t *)p->payload < (u8_t *)p + sizeof(struct pbuf)) {
-      LWIP_DEBUGF( PBUF_DEBUG | 2, ("pbuf_header: failed as %p < %p (not enough space for new header size)\n",
-        (void *)p->payload,
-        (void *)(p + 1)));\
-      /* restore old payload pointer */
-      p->payload = payload;
-      /* bail out unsuccesfully */
-      return 1;
-    }
-  /* pbuf types refering to external payloads? */
-  } else if (p->flags == PBUF_FLAG_REF || p->flags == PBUF_FLAG_ROM) {
-    /* hide a header in the payload? */
-    if ((header_size_increment < 0) && (header_size_increment - p->len <= 0)) {
-      /* increase payload pointer */
-      p->payload = (u8_t *)p->payload - header_size_increment;
-    } else {
-      /* cannot expand payload to front (yet!)
-       * bail out unsuccesfully */
-      return 1;
-    }
-  }
-  /* modify pbuf length fields */
-  p->len += header_size_increment;
-  p->tot_len += header_size_increment;
-
-  LWIP_DEBUGF( PBUF_DEBUG, ("pbuf_header: old %p new %p (%"S16_F")\n",
-    (void *)payload, (void *)p->payload, header_size_increment));
-
-  return 0;
-}
-
-/**
- * Dereference a pbuf chain or queue and deallocate any no-longer-used
- * pbufs at the head of this chain or queue.
- *
- * Decrements the pbuf reference count. If it reaches zero, the pbuf is
- * deallocated.
- *
- * For a pbuf chain, this is repeated for each pbuf in the chain,
- * up to the first pbuf which has a non-zero reference count after
- * decrementing. So, when all reference counts are one, the whole
- * chain is free'd.
- *
- * @param pbuf The pbuf (chain) to be dereferenced.
- *
- * @return the number of pbufs that were de-allocated
- * from the head of the chain.
- *
- * @note MUST NOT be called on a packet queue (Not verified to work yet).
- * @note the reference counter of a pbuf equals the number of pointers
- * that refer to the pbuf (or into the pbuf).
- *
- * @internal examples:
- *
- * Assuming existing chains a->b->c with the following reference
- * counts, calling pbuf_free(a) results in:
- * 
- * 1->2->3 becomes ...1->3
- * 3->3->3 becomes 2->3->3
- * 1->1->2 becomes ......1
- * 2->1->1 becomes 1->1->1
- * 1->1->1 becomes .......
- *
- */
-u8_t
-pbuf_free(struct pbuf *p)
-{
-  struct pbuf *q;
-  u8_t count;
-  SYS_ARCH_DECL_PROTECT(old_level);
-
-  LWIP_ASSERT("p != NULL", p != NULL);
-  /* if assertions are disabled, proceed with debug output */
-  if (p == NULL) {
-    LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_free(p == NULL) was called.\n"));
-    return 0;
-  }
-  LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_free(%p)\n", (void *)p));
-
-  PERF_START;
-
-  LWIP_ASSERT("pbuf_free: sane flags",
-    p->flags == PBUF_FLAG_RAM || p->flags == PBUF_FLAG_ROM ||
-    p->flags == PBUF_FLAG_REF || p->flags == PBUF_FLAG_POOL);
-
-  count = 0;
-  /* Since decrementing ref cannot be guaranteed to be a single machine operation
-   * we must protect it. Also, the later test of ref must be protected.
-   */
-  SYS_ARCH_PROTECT(old_level);
-  /* de-allocate all consecutive pbufs from the head of the chain that
-   * obtain a zero reference count after decrementing*/
-  while (p != NULL) {
-    /* all pbufs in a chain are referenced at least once */
-    LWIP_ASSERT("pbuf_free: p->ref > 0", p->ref > 0);
-    /* decrease reference count (number of pointers to pbuf) */
-    p->ref--;
-    /* this pbuf is no longer referenced to? */
-    if (p->ref == 0) {
-      /* remember next pbuf in chain for next iteration */
-      q = p->next;
-      LWIP_DEBUGF( PBUF_DEBUG | 2, ("pbuf_free: deallocating %p\n", (void *)p));
-      /* is this a pbuf from the pool? */
-      if (p->flags == PBUF_FLAG_POOL) {
-        p->len = p->tot_len = PBUF_POOL_BUFSIZE;
-        p->payload = (void *)((u8_t *)p + sizeof(struct pbuf));
-        PBUF_POOL_FREE(p);
-      /* is this a ROM or RAM referencing pbuf? */
-      } else if (p->flags == PBUF_FLAG_ROM || p->flags == PBUF_FLAG_REF) {
-        memp_free(MEMP_PBUF, p);
-      /* p->flags == PBUF_FLAG_RAM */
-      } else {
-        mem_free(p);
-      }
-      count++;
-      /* proceed to next pbuf */
-      p = q;
-    /* p->ref > 0, this pbuf is still referenced to */
-    /* (and so the remaining pbufs in chain as well) */
-    } else {
-      LWIP_DEBUGF( PBUF_DEBUG | 2, ("pbuf_free: %p has ref %"U16_F", ending here.\n", (void *)p, (u16_t)p->ref));
-      /* stop walking through the chain */
-      p = NULL;
-    }
-  }
-  SYS_ARCH_UNPROTECT(old_level);
-  PERF_STOP("pbuf_free");
-  /* return number of de-allocated pbufs */
-  return count;
-}
-
-/**
- * Count number of pbufs in a chain
- *
- * @param p first pbuf of chain
- * @return the number of pbufs in a chain
- */
-
-u8_t
-pbuf_clen(struct pbuf *p)
-{
-  u8_t len;
-
-  len = 0;
-  while (p != NULL) {
-    ++len;
-    p = p->next;
-  }
-  return len;
-}
-
-/**
- * Increment the reference count of the pbuf.
- *
- * @param p pbuf to increase reference counter of
- *
- */
-void
-pbuf_ref(struct pbuf *p)
-{
-  SYS_ARCH_DECL_PROTECT(old_level);
-  /* pbuf given? */
-  if (p != NULL) {
-    SYS_ARCH_PROTECT(old_level);
-    ++(p->ref);
-    SYS_ARCH_UNPROTECT(old_level);
-  }
-}
-
-/**
- * Concatenate two pbufs (each may be a pbuf chain) and take over
- * the caller's reference of the tail pbuf.
- * 
- * @note The caller MAY NOT reference the tail pbuf afterwards.
- * Use pbuf_chain() for that purpose.
- * 
- * @see pbuf_chain()
- */
-
-void
-pbuf_cat(struct pbuf *h, struct pbuf *t)
-{
-  struct pbuf *p;
-
-  LWIP_ASSERT("h != NULL (programmer violates API)", h != NULL);
-  LWIP_ASSERT("t != NULL (programmer violates API)", t != NULL);
-  if ((h == NULL) || (t == NULL)) return;
-
-  /* proceed to last pbuf of chain */
-  for (p = h; p->next != NULL; p = p->next) {
-    /* add total length of second chain to all totals of first chain */
-    p->tot_len += t->tot_len;
-  }
-  /* { p is last pbuf of first h chain, p->next == NULL } */
-  LWIP_ASSERT("p->tot_len == p->len (of last pbuf in chain)", p->tot_len == p->len);
-  LWIP_ASSERT("p->next == NULL", p->next == NULL);
-  /* add total length of second chain to last pbuf total of first chain */
-  p->tot_len += t->tot_len;
-  /* chain last pbuf of head (p) with first of tail (t) */
-  p->next = t;
-  /* p->next now references t, but the caller will drop its reference to t,
-   * so netto there is no change to the reference count of t.
-   */
-}
-
-/**
- * Chain two pbufs (or pbuf chains) together.
- * 
- * The caller MUST call pbuf_free(t) once it has stopped
- * using it. Use pbuf_cat() instead if you no longer use t.
- * 
- * @param h head pbuf (chain)
- * @param t tail pbuf (chain)
- * @note The pbufs MUST belong to the same packet.
- * @note MAY NOT be called on a packet queue.
- *
- * The ->tot_len fields of all pbufs of the head chain are adjusted.
- * The ->next field of the last pbuf of the head chain is adjusted.
- * The ->ref field of the first pbuf of the tail chain is adjusted.
- *
- */
-void
-pbuf_chain(struct pbuf *h, struct pbuf *t)
-{
-  pbuf_cat(h, t);
-  /* t is now referenced by h */
-  pbuf_ref(t);
-  LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, ("pbuf_chain: %p references %p\n", (void *)h, (void *)t));
-}
-
-/* For packet queueing. Note that queued packets MUST be dequeued first
- * using pbuf_dequeue() before calling other pbuf_() functions. */
-#if ARP_QUEUEING
-/**
- * Add a packet to the end of a queue.
- *
- * @param q pointer to first packet on the queue
- * @param n packet to be queued
- *
- * Both packets MUST be given, and must be different.
- */
-void
-pbuf_queue(struct pbuf *p, struct pbuf *n)
-{
-#if PBUF_DEBUG /* remember head of queue */
-  struct pbuf *q = p;
-#endif
-  /* programmer stupidity checks */
-  LWIP_ASSERT("p == NULL in pbuf_queue: this indicates a programmer error\n", p != NULL);
-  LWIP_ASSERT("n == NULL in pbuf_queue: this indicates a programmer error\n", n != NULL);
-  LWIP_ASSERT("p == n in pbuf_queue: this indicates a programmer error\n", p != n);
-  if ((p == NULL) || (n == NULL) || (p == n)){
-    LWIP_DEBUGF(PBUF_DEBUG | DBG_HALT | 3, ("pbuf_queue: programmer argument error\n"));
-    return;
-  }
-
-  /* iterate through all packets on queue */
-  while (p->next != NULL) {
-/* be very picky about pbuf chain correctness */
-#if PBUF_DEBUG
-    /* iterate through all pbufs in packet */
-    while (p->tot_len != p->len) {
-      /* make sure invariant condition holds */
-      LWIP_ASSERT("p->len < p->tot_len", p->len < p->tot_len);
-      /* make sure each packet is complete */
-      LWIP_ASSERT("p->next != NULL", p->next != NULL);
-      p = p->next;
-      /* { p->tot_len == p->len => p is last pbuf of a packet } */
-    }
-    /* { p is last pbuf of a packet } */
-    /* proceed to next packet on queue */
-#endif
-    /* proceed to next pbuf */
-    if (p->next != NULL) p = p->next;
-  }
-  /* { p->tot_len == p->len and p->next == NULL } ==>
-   * { p is last pbuf of last packet on queue } */
-  /* chain last pbuf of queue with n */
-  p->next = n;
-  /* n is now referenced to by the (packet p in the) queue */
-  pbuf_ref(n);
-#if PBUF_DEBUG
-  LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2,
-    ("pbuf_queue: newly queued packet %p sits after packet %p in queue %p\n",
-    (void *)n, (void *)p, (void *)q));
-#endif
-}
-
-/**
- * Remove a packet from the head of a queue.
- *
- * The caller MUST reference the remainder of the queue (as returned). The
- * caller MUST NOT call pbuf_ref() as it implicitly takes over the reference
- * from p.
- * 
- * @param p pointer to first packet on the queue which will be dequeued.
- * @return first packet on the remaining queue (NULL if no further packets).
- *
- */
-struct pbuf *
-pbuf_dequeue(struct pbuf *p)
-{
-  struct pbuf *q;
-  LWIP_ASSERT("p != NULL", p != NULL);
-
-  /* iterate through all pbufs in packet p */
-  while (p->tot_len != p->len) {
-    /* make sure invariant condition holds */
-    LWIP_ASSERT("p->len < p->tot_len", p->len < p->tot_len);
-    /* make sure each packet is complete */
-    LWIP_ASSERT("p->next != NULL", p->next != NULL);
-    p = p->next;
-  }
-  /* { p->tot_len == p->len } => p is the last pbuf of the first packet */
-  /* remember next packet on queue in q */
-  q = p->next;
-  /* dequeue packet p from queue */
-  p->next = NULL;
-  /* any next packet on queue? */
-  if (q != NULL) {
-    /* although q is no longer referenced by p, it MUST be referenced by
-     * the caller, who is maintaining this packet queue. So, we do not call
-     * pbuf_free(q) here, resulting in an implicit pbuf_ref(q) for the caller. */
-    LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, ("pbuf_dequeue: first remaining packet on queue is %p\n", (void *)q));
-  } else {
-    LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, ("pbuf_dequeue: no further packets on queue\n"));
-  }
-  return q;
-}
-#endif
-
-/**
- *
- * Create PBUF_POOL (or PBUF_RAM) copies of PBUF_REF pbufs.
- *
- * Used to queue packets on behalf of the lwIP stack, such as
- * ARP based queueing.
- *
- * Go through a pbuf chain and replace any PBUF_REF buffers
- * with PBUF_POOL (or PBUF_RAM) pbufs, each taking a copy of
- * the referenced data.
- *
- * @note You MUST explicitly use p = pbuf_take(p);
- * The pbuf you give as argument, may have been replaced
- * by a (differently located) copy through pbuf_take()!
- *
- * @note Any replaced pbufs will be freed through pbuf_free().
- * This may deallocate them if they become no longer referenced.
- *
- * @param p Head of pbuf chain to process
- *
- * @return Pointer to head of pbuf chain
- */
-struct pbuf *
-pbuf_take(struct pbuf *p)
-{
-  struct pbuf *q , *prev, *head;
-  LWIP_ASSERT("pbuf_take: p != NULL\n", p != NULL);
-  LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_take(%p)\n", (void*)p));
-
-  prev = NULL;
-  head = p;
-  /* iterate through pbuf chain */
-  do
-  {
-    /* pbuf is of type PBUF_REF? */
-    if (p->flags == PBUF_FLAG_REF) {
-      LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE, ("pbuf_take: encountered PBUF_REF %p\n", (void *)p));
-      /* allocate a pbuf (w/ payload) fully in RAM */
-      /* PBUF_POOL buffers are faster if we can use them */
-      if (p->len <= PBUF_POOL_BUFSIZE) {
-        q = pbuf_alloc(PBUF_RAW, p->len, PBUF_POOL);
-        if (q == NULL) {
-          LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_take: Could not allocate PBUF_POOL\n"));
-        }
-      } else {
-        /* no replacement pbuf yet */
-        q = NULL;
-        LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_take: PBUF_POOL too small to replace PBUF_REF\n"));
-      }
-      /* no (large enough) PBUF_POOL was available? retry with PBUF_RAM */
-      if (q == NULL) {
-        q = pbuf_alloc(PBUF_RAW, p->len, PBUF_RAM);
-        if (q == NULL) {
-          LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_take: Could not allocate PBUF_RAM\n"));
-        }
-      }
-      /* replacement pbuf could be allocated? */
-      if (q != NULL)
-      {
-        /* copy p to q */
-        /* copy successor */
-        q->next = p->next;
-        /* remove linkage from original pbuf */
-        p->next = NULL;
-        /* remove linkage to original pbuf */
-        if (prev != NULL) {
-          /* prev->next == p at this point */
-          LWIP_ASSERT("prev->next == p", prev->next == p);
-          /* break chain and insert new pbuf instead */
-          prev->next = q;
-        /* prev == NULL, so we replaced the head pbuf of the chain */
-        } else {
-          head = q;
-        }
-        /* copy pbuf payload */
-        memcpy(q->payload, p->payload, p->len);
-        q->tot_len = p->tot_len;
-        q->len = p->len;
-        /* in case p was the first pbuf, it is no longer refered to by
-         * our caller, as the caller MUST do p = pbuf_take(p);
-         * in case p was not the first pbuf, it is no longer refered to
-         * by prev. we can safely free the pbuf here.
-         * (note that we have set p->next to NULL already so that
-         * we will not free the rest of the chain by accident.)
-         */
-        pbuf_free(p);
-        /* do not copy ref, since someone else might be using the old buffer */
-        LWIP_DEBUGF(PBUF_DEBUG, ("pbuf_take: replaced PBUF_REF %p with %p\n", (void *)p, (void *)q));
-        p = q;
-      } else {
-        /* deallocate chain */
-        pbuf_free(head);
-        LWIP_DEBUGF(PBUF_DEBUG | 2, ("pbuf_take: failed to allocate replacement pbuf for %p\n", (void *)p));
-        return NULL;
-      }
-    /* p->flags != PBUF_FLAG_REF */
-    } else {
-      LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 1, ("pbuf_take: skipping pbuf not of type PBUF_REF\n"));
-    }
-    /* remember this pbuf */
-    prev = p;
-    /* proceed to next pbuf in original chain */
-    p = p->next;
-  } while (p);
-  LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 1, ("pbuf_take: end of chain reached.\n"));
-
-  return head;
-}
-
-/**
- * Dechains the first pbuf from its succeeding pbufs in the chain.
- *
- * Makes p->tot_len field equal to p->len.
- * @param p pbuf to dechain
- * @return remainder of the pbuf chain, or NULL if it was de-allocated.
- * @note May not be called on a packet queue.
- */
-struct pbuf *
-pbuf_dechain(struct pbuf *p)
-{
-  struct pbuf *q;
-  u8_t tail_gone = 1;
-  /* tail */
-  q = p->next;
-  /* pbuf has successor in chain? */
-  if (q != NULL) {
-    /* assert tot_len invariant: (p->tot_len == p->len + (p->next? p->next->tot_len: 0) */
-    LWIP_ASSERT("p->tot_len == p->len + q->tot_len", q->tot_len == p->tot_len - p->len);
-    /* enforce invariant if assertion is disabled */
-    q->tot_len = p->tot_len - p->len;
-    /* decouple pbuf from remainder */
-    p->next = NULL;
-    /* total length of pbuf p is its own length only */
-    p->tot_len = p->len;
-    /* q is no longer referenced by p, free it */
-    LWIP_DEBUGF(PBUF_DEBUG | DBG_STATE, ("pbuf_dechain: unreferencing %p\n", (void *)q));
-    tail_gone = pbuf_free(q);
-    if (tail_gone > 0) {
-      LWIP_DEBUGF(PBUF_DEBUG | DBG_STATE,
-                  ("pbuf_dechain: deallocated %p (as it is no longer referenced)\n", (void *)q));
-    }
-    /* return remaining tail or NULL if deallocated */
-  }
-  /* assert tot_len invariant: (p->tot_len == p->len + (p->next? p->next->tot_len: 0) */
-  LWIP_ASSERT("p->tot_len == p->len", p->tot_len == p->len);
-  return (tail_gone > 0? NULL: q);
-}
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/core/raw.c b/Demo/lwIP_MCF5235_GCC/lwip/src/core/raw.c
deleted file mode 100644
index 30199804d..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/core/raw.c
+++ /dev/null
@@ -1,326 +0,0 @@
-/**
- * @file
- * 
- * Implementation of raw protocol PCBs for low-level handling of
- * different types of protocols besides (or overriding) those
- * already available in lwIP.
- *
- */
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels 
- *
- */
-
-#include 
-
-#include "lwip/opt.h"
-
-#include "lwip/def.h"
-#include "lwip/memp.h"
-#include "lwip/inet.h"
-#include "lwip/ip_addr.h"
-#include "lwip/netif.h"
-#include "lwip/raw.h"
-
-#include "lwip/stats.h"
-
-#include "arch/perf.h"
-#include "lwip/snmp.h"
-
-#if LWIP_RAW
-
-/** The list of RAW PCBs */
-static struct raw_pcb *raw_pcbs = NULL;
-
-void
-raw_init(void)
-{
-  raw_pcbs = NULL;
-}
-
-/**
- * Determine if in incoming IP packet is covered by a RAW PCB
- * and if so, pass it to a user-provided receive callback function.
- *
- * Given an incoming IP datagram (as a chain of pbufs) this function
- * finds a corresponding RAW PCB and calls the corresponding receive
- * callback function.
- *
- * @param pbuf pbuf to be demultiplexed to a RAW PCB.
- * @param netif network interface on which the datagram was received.
- * @Return - 1 if the packet has been eaten by a RAW PCB receive
- *           callback function. The caller MAY NOT not reference the
- *           packet any longer, and MAY NOT call pbuf_free().
- * @return - 0 if packet is not eaten (pbuf is still referenced by the
- *           caller).
- *
- */
-u8_t
-raw_input(struct pbuf *p, struct netif *inp)
-{
-  struct raw_pcb *pcb;
-  struct ip_hdr *iphdr;
-  s16_t proto;
-  u8_t eaten = 0;
-
-  iphdr = p->payload;
-  proto = IPH_PROTO(iphdr);
-
-  pcb = raw_pcbs;
-  /* loop through all raw pcbs until the packet is eaten by one */
-  /* this allows multiple pcbs to match against the packet by design */
-  while ((eaten == 0) && (pcb != NULL)) {
-    if (pcb->protocol == proto) {
-      /* receive callback function available? */
-      if (pcb->recv != NULL) {
-        /* the receive callback function did not eat the packet? */
-        if (pcb->recv(pcb->recv_arg, pcb, p, &(iphdr->src)) != 0)
-        {
-          /* receive function ate the packet */
-          p = NULL;
-          eaten = 1;
-        }
-      }
-      /* no receive callback function was set for this raw PCB */
-      /* drop the packet */
-    }
-    pcb = pcb->next;
-  }
-  return eaten;
-}
-
-/**
- * Bind a RAW PCB.
- *
- * @param pcb RAW PCB to be bound with a local address ipaddr.
- * @param ipaddr local IP address to bind with. Use IP_ADDR_ANY to
- * bind to all local interfaces.
- *
- * @return lwIP error code.
- * - ERR_OK. Successful. No error occured.
- * - ERR_USE. The specified IP address is already bound to by
- * another RAW PCB.
- *
- * @see raw_disconnect()
- */
-err_t
-raw_bind(struct raw_pcb *pcb, struct ip_addr *ipaddr)
-{
-  ip_addr_set(&pcb->local_ip, ipaddr);
-  return ERR_OK;
-}
-
-/**
- * Connect an RAW PCB. This function is required by upper layers
- * of lwip. Using the raw api you could use raw_sendto() instead
- *
- * This will associate the RAW PCB with the remote address.
- *
- * @param pcb RAW PCB to be connected with remote address ipaddr and port.
- * @param ipaddr remote IP address to connect with.
- *
- * @return lwIP error code
- *
- * @see raw_disconnect() and raw_sendto()
- */
-err_t
-raw_connect(struct raw_pcb *pcb, struct ip_addr *ipaddr)
-{
-  ip_addr_set(&pcb->remote_ip, ipaddr);
-  return ERR_OK;
-}
-
-
-/**
- * Set the callback function for received packets that match the
- * raw PCB's protocol and binding. 
- * 
- * The callback function MUST either
- * - eat the packet by calling pbuf_free() and returning non-zero. The
- *   packet will not be passed to other raw PCBs or other protocol layers.
- * - not free the packet, and return zero. The packet will be matched
- *   against further PCBs and/or forwarded to another protocol layers.
- * 
- * @return non-zero if the packet was free()d, zero if the packet remains
- * available for others.
- */
-void
-raw_recv(struct raw_pcb *pcb,
-         u8_t (* recv)(void *arg, struct raw_pcb *upcb, struct pbuf *p,
-                      struct ip_addr *addr),
-         void *recv_arg)
-{
-  /* remember recv() callback and user data */
-  pcb->recv = recv;
-  pcb->recv_arg = recv_arg;
-}
-
-/**
- * Send the raw IP packet to the given address. Note that actually you cannot
- * modify the IP headers (this is inconsistent with the receive callback where
- * you actually get the IP headers), you can only specify the IP payload here.
- * It requires some more changes in lwIP. (there will be a raw_send() function
- * then.)
- *
- * @param pcb the raw pcb which to send
- * @param p the IP payload to send
- * @param ipaddr the destination address of the IP packet
- *
- */
-err_t
-raw_sendto(struct raw_pcb *pcb, struct pbuf *p, struct ip_addr *ipaddr)
-{
-  err_t err;
-  struct netif *netif;
-  struct ip_addr *src_ip;
-  struct pbuf *q; /* q will be sent down the stack */
-  
-  LWIP_DEBUGF(RAW_DEBUG | DBG_TRACE | 3, ("raw_sendto\n"));
-  
-  /* not enough space to add an IP header to first pbuf in given p chain? */
-  if (pbuf_header(p, IP_HLEN)) {
-    /* allocate header in new pbuf */
-    q = pbuf_alloc(PBUF_IP, 0, PBUF_RAM);
-    /* new header pbuf could not be allocated? */
-    if (q == NULL) {
-      LWIP_DEBUGF(RAW_DEBUG | DBG_TRACE | 2, ("raw_sendto: could not allocate header\n"));
-      return ERR_MEM;
-    }
-    /* chain header q in front of given pbuf p */
-    pbuf_chain(q, p);
-    /* { first pbuf q points to header pbuf } */
-    LWIP_DEBUGF(RAW_DEBUG, ("raw_sendto: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p));
-  }  else {
-    /* first pbuf q equals given pbuf */
-    q = p;
-    pbuf_header(q, -IP_HLEN);
-  }
-  
-  if ((netif = ip_route(ipaddr)) == NULL) {
-    LWIP_DEBUGF(RAW_DEBUG | 1, ("raw_sendto: No route to 0x%"X32_F"\n", ipaddr->addr));
-#if RAW_STATS
-    /*    ++lwip_stats.raw.rterr;*/
-#endif /* RAW_STATS */
-    /* free any temporary header pbuf allocated by pbuf_header() */
-    if (q != p) {
-      pbuf_free(q);
-    }
-    return ERR_RTE;
-  }
-
-  if (ip_addr_isany(&pcb->local_ip)) {
-    /* use outgoing network interface IP address as source address */
-    src_ip = &(netif->ip_addr);
-  } else {
-    /* use RAW PCB local IP address as source address */
-    src_ip = &(pcb->local_ip);
-  }
-
-  err = ip_output_if (q, src_ip, ipaddr, pcb->ttl, pcb->tos, pcb->protocol, netif);
-
-  /* did we chain a header earlier? */
-  if (q != p) {
-    /* free the header */
-    pbuf_free(q);
-  }
-  return err;
-}
-
-/**
- * Send the raw IP packet to the address given by raw_connect()
- *
- * @param pcb the raw pcb which to send
- * @param p the IP payload to send
- * @param ipaddr the destination address of the IP packet
- *
- */
-err_t
-raw_send(struct raw_pcb *pcb, struct pbuf *p)
-{
-  return raw_sendto(pcb, p, &pcb->remote_ip);
-}
-
-/**
- * Remove an RAW PCB.
- *
- * @param pcb RAW PCB to be removed. The PCB is removed from the list of
- * RAW PCB's and the data structure is freed from memory.
- *
- * @see raw_new()
- */
-void
-raw_remove(struct raw_pcb *pcb)
-{
-  struct raw_pcb *pcb2;
-  /* pcb to be removed is first in list? */
-  if (raw_pcbs == pcb) {
-    /* make list start at 2nd pcb */
-    raw_pcbs = raw_pcbs->next;
-    /* pcb not 1st in list */
-  } else for(pcb2 = raw_pcbs; pcb2 != NULL; pcb2 = pcb2->next) {
-    /* find pcb in raw_pcbs list */
-    if (pcb2->next != NULL && pcb2->next == pcb) {
-      /* remove pcb from list */
-      pcb2->next = pcb->next;
-    }
-  }
-  memp_free(MEMP_RAW_PCB, pcb);
-}
-
-/**
- * Create a RAW PCB.
- *
- * @return The RAW PCB which was created. NULL if the PCB data structure
- * could not be allocated.
- *
- * @param proto the protocol number of the IPs payload (e.g. IP_PROTO_ICMP)
- *
- * @see raw_remove()
- */
-struct raw_pcb *
-raw_new(u16_t proto) {
-  struct raw_pcb *pcb;
-
-  LWIP_DEBUGF(RAW_DEBUG | DBG_TRACE | 3, ("raw_new\n"));
-
-  pcb = memp_malloc(MEMP_RAW_PCB);
-  /* could allocate RAW PCB? */
-  if (pcb != NULL) {
-    /* initialize PCB to all zeroes */
-    memset(pcb, 0, sizeof(struct raw_pcb));
-    pcb->protocol = proto;
-    pcb->ttl = RAW_TTL;
-    pcb->next = raw_pcbs;
-    raw_pcbs = pcb;
-  }
-  return pcb;
-}
-
-#endif /* LWIP_RAW */
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/core/stats.c b/Demo/lwIP_MCF5235_GCC/lwip/src/core/stats.c
deleted file mode 100644
index c94623f7a..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/core/stats.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-
-#include 
-
-#include "lwip/opt.h"
-
-#include "lwip/def.h"
-
-#include "lwip/stats.h"
-#include "lwip/mem.h"
-
-
-#if LWIP_STATS
-struct stats_ lwip_stats;
-
-void
-stats_init(void)
-{
-  memset(&lwip_stats, 0, sizeof(struct stats_));
-}
-#if LWIP_STATS_DISPLAY
-void
-stats_display_proto(struct stats_proto *proto, char *name)
-{
-  LWIP_PLATFORM_DIAG(("\n%s\n\t", name));
-  LWIP_PLATFORM_DIAG(("xmit: %"S16_F"\n\t", proto->xmit)); 
-  LWIP_PLATFORM_DIAG(("rexmit: %"S16_F"\n\t", proto->rexmit)); 
-  LWIP_PLATFORM_DIAG(("recv: %"S16_F"\n\t", proto->recv)); 
-  LWIP_PLATFORM_DIAG(("fw: %"S16_F"\n\t", proto->fw)); 
-  LWIP_PLATFORM_DIAG(("drop: %"S16_F"\n\t", proto->drop)); 
-  LWIP_PLATFORM_DIAG(("chkerr: %"S16_F"\n\t", proto->chkerr)); 
-  LWIP_PLATFORM_DIAG(("lenerr: %"S16_F"\n\t", proto->lenerr)); 
-  LWIP_PLATFORM_DIAG(("memerr: %"S16_F"\n\t", proto->memerr)); 
-  LWIP_PLATFORM_DIAG(("rterr: %"S16_F"\n\t", proto->rterr)); 
-  LWIP_PLATFORM_DIAG(("proterr: %"S16_F"\n\t", proto->proterr)); 
-  LWIP_PLATFORM_DIAG(("opterr: %"S16_F"\n\t", proto->opterr)); 
-  LWIP_PLATFORM_DIAG(("err: %"S16_F"\n\t", proto->err)); 
-  LWIP_PLATFORM_DIAG(("cachehit: %"S16_F"\n", proto->cachehit)); 
-}
-
-void
-stats_display_pbuf(struct stats_pbuf *pbuf)
-{
-  LWIP_PLATFORM_DIAG(("\nPBUF\n\t"));
-  LWIP_PLATFORM_DIAG(("avail: %"S16_F"\n\t", pbuf->avail)); 
-  LWIP_PLATFORM_DIAG(("used: %"S16_F"\n\t", pbuf->used)); 
-  LWIP_PLATFORM_DIAG(("max: %"S16_F"\n\t", pbuf->max)); 
-  LWIP_PLATFORM_DIAG(("err: %"S16_F"\n\t", pbuf->err)); 
-  LWIP_PLATFORM_DIAG(("alloc_locked: %"S16_F"\n\t", pbuf->alloc_locked)); 
-  LWIP_PLATFORM_DIAG(("refresh_locked: %"S16_F"\n", pbuf->refresh_locked)); 
-}
-
-void
-stats_display_mem(struct stats_mem *mem, char *name)
-{
-  LWIP_PLATFORM_DIAG(("\n MEM %s\n\t", name));
-  LWIP_PLATFORM_DIAG(("avail: %"S16_F"\n\t", mem->avail)); 
-  LWIP_PLATFORM_DIAG(("used: %"S16_F"\n\t", mem->used)); 
-  LWIP_PLATFORM_DIAG(("max: %"S16_F"\n\t", mem->max)); 
-  LWIP_PLATFORM_DIAG(("err: %"S16_F"\n", mem->err));
-  
-}
-
-void
-stats_display(void)
-{
-  s16_t i;
-  char * memp_names[] = {"PBUF", "RAW_PCB", "UDP_PCB", "TCP_PCB", "TCP_PCB_LISTEN",
-	  		"TCP_SEG", "NETBUF", "NETCONN", "API_MSG", "TCP_MSG", "TIMEOUT"};
-  stats_display_proto(&lwip_stats.link, "LINK");
-  stats_display_proto(&lwip_stats.ip_frag, "IP_FRAG");
-  stats_display_proto(&lwip_stats.ip, "IP");
-  stats_display_proto(&lwip_stats.icmp, "ICMP");
-  stats_display_proto(&lwip_stats.udp, "UDP");
-  stats_display_proto(&lwip_stats.tcp, "TCP");
-  stats_display_pbuf(&lwip_stats.pbuf);
-  stats_display_mem(&lwip_stats.mem, "HEAP");
-  for (i = 0; i < MEMP_MAX; i++) {
-    stats_display_mem(&lwip_stats.memp[i], memp_names[i]);
-  }
-	
-}
-#endif /* LWIP_STATS_DISPLAY */
-#endif /* LWIP_STATS */
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/core/sys.c b/Demo/lwIP_MCF5235_GCC/lwip/src/core/sys.c
deleted file mode 100644
index a7dbf34da..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/core/sys.c
+++ /dev/null
@@ -1,294 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels 
- *
- */
-
-#include "lwip/sys.h"
-#include "lwip/opt.h"
-#include "lwip/def.h"
-#include "lwip/memp.h"
-
-#if (NO_SYS == 0)
-
-struct sswt_cb
-{
-    s16_t timeflag;
-    sys_sem_t *psem;
-};
-
-
-
-void
-sys_mbox_fetch(sys_mbox_t mbox, void **msg)
-{
-  u32_t time;
-  struct sys_timeouts *timeouts;
-  struct sys_timeout *tmptimeout;
-  sys_timeout_handler h;
-  void *arg;
-
-
- again:
-  timeouts = sys_arch_timeouts();
-
-  if (!timeouts || !timeouts->next) {
-    sys_arch_mbox_fetch(mbox, msg, 0);
-  } else {
-    if (timeouts->next->time > 0) {
-      time = sys_arch_mbox_fetch(mbox, msg, timeouts->next->time);
-    } else {
-      time = SYS_ARCH_TIMEOUT;
-    }
-
-    if (time == SYS_ARCH_TIMEOUT) {
-      /* If time == SYS_ARCH_TIMEOUT, a timeout occured before a message
-   could be fetched. We should now call the timeout handler and
-   deallocate the memory allocated for the timeout. */
-      tmptimeout = timeouts->next;
-      timeouts->next = tmptimeout->next;
-      h = tmptimeout->h;
-      arg = tmptimeout->arg;
-      memp_free(MEMP_SYS_TIMEOUT, tmptimeout);
-      if (h != NULL) {
-        LWIP_DEBUGF(SYS_DEBUG, ("smf calling h=%p(%p)\n", (void *)h, (void *)arg));
-      	h(arg);
-      }
-
-      /* We try again to fetch a message from the mbox. */
-      goto again;
-    } else {
-      /* If time != SYS_ARCH_TIMEOUT, a message was received before the timeout
-   occured. The time variable is set to the number of
-   milliseconds we waited for the message. */
-      if (time <= timeouts->next->time) {
-  timeouts->next->time -= time;
-      } else {
-  timeouts->next->time = 0;
-      }
-    }
-
-  }
-}
-
-void
-sys_sem_wait(sys_sem_t sem)
-{
-  u32_t time;
-  struct sys_timeouts *timeouts;
-  struct sys_timeout *tmptimeout;
-  sys_timeout_handler h;
-  void *arg;
-
-  /*  while (sys_arch_sem_wait(sem, 1000) == 0);
-      return;*/
-
- again:
-
-  timeouts = sys_arch_timeouts();
-
-  if (!timeouts || !timeouts->next) {
-    sys_arch_sem_wait(sem, 0);
-  } else {
-    if (timeouts->next->time > 0) {
-      time = sys_arch_sem_wait(sem, timeouts->next->time);
-    } else {
-      time = SYS_ARCH_TIMEOUT;
-    }
-
-    if (time == SYS_ARCH_TIMEOUT) {
-      /* If time == SYS_ARCH_TIMEOUT, a timeout occured before a message
-   could be fetched. We should now call the timeout handler and
-   deallocate the memory allocated for the timeout. */
-      tmptimeout = timeouts->next;
-      timeouts->next = tmptimeout->next;
-      h = tmptimeout->h;
-      arg = tmptimeout->arg;
-      memp_free(MEMP_SYS_TIMEOUT, tmptimeout);
-      if (h != NULL) {
-        LWIP_DEBUGF(SYS_DEBUG, ("ssw h=%p(%p)\n", (void *)h, (void *)arg));
-        h(arg);
-      }
-
-
-      /* We try again to fetch a message from the mbox. */
-      goto again;
-    } else {
-      /* If time != SYS_ARCH_TIMEOUT, a message was received before the timeout
-   occured. The time variable is set to the number of
-   milliseconds we waited for the message. */
-      if (time <= timeouts->next->time) {
-  timeouts->next->time -= time;
-      } else {
-  timeouts->next->time = 0;
-      }
-    }
-
-  }
-}
-
-void
-sys_timeout(u32_t msecs, sys_timeout_handler h, void *arg)
-{
-  struct sys_timeouts *timeouts;
-  struct sys_timeout *timeout, *t;
-
-  timeout = memp_malloc(MEMP_SYS_TIMEOUT);
-  if (timeout == NULL) {
-    return;
-  }
-  timeout->next = NULL;
-  timeout->h = h;
-  timeout->arg = arg;
-  timeout->time = msecs;
-
-  timeouts = sys_arch_timeouts();
-
-  LWIP_DEBUGF(SYS_DEBUG, ("sys_timeout: %p msecs=%"U32_F" h=%p arg=%p\n",
-    (void *)timeout, msecs, (void *)h, (void *)arg));
-
-  LWIP_ASSERT("sys_timeout: timeouts != NULL", timeouts != NULL);
-
-  if (timeouts->next == NULL) {
-    timeouts->next = timeout;
-    return;
-  }
-
-  if (timeouts->next->time > msecs) {
-    timeouts->next->time -= msecs;
-    timeout->next = timeouts->next;
-    timeouts->next = timeout;
-  } else {
-    for(t = timeouts->next; t != NULL; t = t->next) {
-      timeout->time -= t->time;
-      if (t->next == NULL || t->next->time > timeout->time) {
-        if (t->next != NULL) {
-          t->next->time -= timeout->time;
-        }
-        timeout->next = t->next;
-        t->next = timeout;
-        break;
-      }
-    }
-  }
-
-}
-
-/* Go through timeout list (for this task only) and remove the first matching entry,
-   even though the timeout has not triggered yet.
-*/
-
-void
-sys_untimeout(sys_timeout_handler h, void *arg)
-{
-    struct sys_timeouts *timeouts;
-    struct sys_timeout *prev_t, *t;
-
-    timeouts = sys_arch_timeouts();
-
-    if (timeouts->next == NULL)
-        return;
-
-    for (t = timeouts->next, prev_t = NULL; t != NULL; prev_t = t, t = t->next)
-    {
-        if ((t->h == h) && (t->arg == arg))
-        {
-            /* We have a match */
-            /* Unlink from previous in list */
-            if (prev_t == NULL)
-                timeouts->next = t->next;
-            else
-                prev_t->next = t->next;
-            /* If not the last one, add time of this one back to next */
-            if (t->next != NULL)
-                t->next->time += t->time;
-            memp_free(MEMP_SYS_TIMEOUT, t);
-            return;
-        }
-    }
-    return;
-}
-
-
-
-
-
-static void
-sswt_handler(void *arg)
-{
-    struct sswt_cb *sswt_cb = (struct sswt_cb *) arg;
-
-    /* Timeout. Set flag to TRUE and signal semaphore */
-    sswt_cb->timeflag = 1;
-    sys_sem_signal(*(sswt_cb->psem));
-}
-
-/* Wait for a semaphore with timeout (specified in ms) */
-/* timeout = 0: wait forever */
-/* Returns 0 on timeout. 1 otherwise */
-
-int
-sys_sem_wait_timeout(sys_sem_t sem, u32_t timeout)
-{
-    struct sswt_cb sswt_cb;
-
-    sswt_cb.psem = &sem;
-    sswt_cb.timeflag = 0;
-
-    /* If timeout is zero, then just wait forever */
-    if (timeout > 0)
-        /* Create a timer and pass it the address of our flag */
-        sys_timeout(timeout, sswt_handler, &sswt_cb);
-    sys_sem_wait(sem);
-    /* Was it a timeout? */
-    if (sswt_cb.timeflag)
-    {
-        /* timeout */
-        return 0;
-    } else {
-        /* Not a timeout. Remove timeout entry */
-        sys_untimeout(sswt_handler, &sswt_cb);
-        return 1;
-    }
-
-}
-
-
-void
-sys_msleep(u32_t ms)
-{
-  sys_sem_t delaysem = sys_sem_new(0);
-
-  sys_sem_wait_timeout(delaysem, ms);
-
-  sys_sem_free(delaysem);
-}
-
-
-#endif /* NO_SYS */
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/core/tcp.c b/Demo/lwIP_MCF5235_GCC/lwip/src/core/tcp.c
deleted file mode 100644
index 41a9edb4e..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/core/tcp.c
+++ /dev/null
@@ -1,1171 +0,0 @@
-/**
- * @file
- *
- * Transmission Control Protocol for IP
- *
- * This file contains common functions for the TCP implementation, such as functinos
- * for manipulating the data structures and the TCP timer functions. TCP functions
- * related to input and output is found in tcp_in.c and tcp_out.c respectively.
- *
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-
-#include 
-
-#include "lwip/opt.h"
-#include "lwip/def.h"
-#include "lwip/mem.h"
-#include "lwip/memp.h"
-
-#include "lwip/tcp.h"
-#if LWIP_TCP
-
-/* Incremented every coarse grained timer shot
-   (typically every 500 ms, determined by TCP_COARSE_TIMEOUT). */
-u32_t tcp_ticks;
-const u8_t tcp_backoff[13] =
-    { 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7};
-
-/* The TCP PCB lists. */
-
-/** List of all TCP PCBs in LISTEN state */
-union tcp_listen_pcbs_t tcp_listen_pcbs;
-/** List of all TCP PCBs that are in a state in which
- * they accept or send data. */
-struct tcp_pcb *tcp_active_pcbs;  
-/** List of all TCP PCBs in TIME-WAIT state */
-struct tcp_pcb *tcp_tw_pcbs;
-
-struct tcp_pcb *tcp_tmp_pcb;
-
-static u8_t tcp_timer;
-static u16_t tcp_new_port(void);
-
-/**
- * Initializes the TCP layer.
- */
-void
-tcp_init(void)
-{
-  /* Clear globals. */
-  tcp_listen_pcbs.listen_pcbs = NULL;
-  tcp_active_pcbs = NULL;
-  tcp_tw_pcbs = NULL;
-  tcp_tmp_pcb = NULL;
-  
-  /* initialize timer */
-  tcp_ticks = 0;
-  tcp_timer = 0;
-  
-}
-
-/**
- * Called periodically to dispatch TCP timers.
- *
- */
-void
-tcp_tmr(void)
-{
-  /* Call tcp_fasttmr() every 250 ms */
-  tcp_fasttmr();
-
-  if (++tcp_timer & 1) {
-    /* Call tcp_tmr() every 500 ms, i.e., every other timer
-       tcp_tmr() is called. */
-    tcp_slowtmr();
-  }
-}
-
-/**
- * Closes the connection held by the PCB.
- *
- */
-err_t
-tcp_close(struct tcp_pcb *pcb)
-{
-  err_t err;
-
-#if TCP_DEBUG
-  LWIP_DEBUGF(TCP_DEBUG, ("tcp_close: closing in state "));
-  tcp_debug_print_state(pcb->state);
-  LWIP_DEBUGF(TCP_DEBUG, ("\n"));
-#endif /* TCP_DEBUG */
-  switch (pcb->state) {
-  case CLOSED:
-    /* Closing a pcb in the CLOSED state might seem erroneous,
-     * however, it is in this state once allocated and as yet unused
-     * and the user needs some way to free it should the need arise.
-     * Calling tcp_close() with a pcb that has already been closed, (i.e. twice)
-     * or for a pcb that has been used and then entered the CLOSED state 
-     * is erroneous, but this should never happen as the pcb has in those cases
-     * been freed, and so any remaining handles are bogus. */
-    err = ERR_OK;
-    memp_free(MEMP_TCP_PCB, pcb);
-    pcb = NULL;
-    break;
-  case LISTEN:
-    err = ERR_OK;
-    tcp_pcb_remove((struct tcp_pcb **)&tcp_listen_pcbs.pcbs, pcb);
-    memp_free(MEMP_TCP_PCB_LISTEN, pcb);
-    pcb = NULL;
-    break;
-  case SYN_SENT:
-    err = ERR_OK;
-    tcp_pcb_remove(&tcp_active_pcbs, pcb);
-    memp_free(MEMP_TCP_PCB, pcb);
-    pcb = NULL;
-    break;
-  case SYN_RCVD:
-  case ESTABLISHED:
-    err = tcp_send_ctrl(pcb, TCP_FIN);
-    if (err == ERR_OK) {
-      pcb->state = FIN_WAIT_1;
-    }
-    break;
-  case CLOSE_WAIT:
-    err = tcp_send_ctrl(pcb, TCP_FIN);
-    if (err == ERR_OK) {
-      pcb->state = LAST_ACK;
-    }
-    break;
-  default:
-    /* Has already been closed, do nothing. */
-    err = ERR_OK;
-    pcb = NULL;
-    break;
-  }
-
-  if (pcb != NULL && err == ERR_OK) {
-    err = tcp_output(pcb);
-  }
-  return err;
-}
-
-/**
- * Aborts a connection by sending a RST to the remote host and deletes
- * the local protocol control block. This is done when a connection is
- * killed because of shortage of memory.
- *
- */
-void
-tcp_abort(struct tcp_pcb *pcb)
-{
-  u32_t seqno, ackno;
-  u16_t remote_port, local_port;
-  struct ip_addr remote_ip, local_ip;
-#if LWIP_CALLBACK_API  
-  void (* errf)(void *arg, err_t err);
-#endif /* LWIP_CALLBACK_API */
-  void *errf_arg;
-
-  
-  /* Figure out on which TCP PCB list we are, and remove us. If we
-     are in an active state, call the receive function associated with
-     the PCB with a NULL argument, and send an RST to the remote end. */
-  if (pcb->state == TIME_WAIT) {
-    tcp_pcb_remove(&tcp_tw_pcbs, pcb);
-    memp_free(MEMP_TCP_PCB, pcb);
-  } else {
-    seqno = pcb->snd_nxt;
-    ackno = pcb->rcv_nxt;
-    ip_addr_set(&local_ip, &(pcb->local_ip));
-    ip_addr_set(&remote_ip, &(pcb->remote_ip));
-    local_port = pcb->local_port;
-    remote_port = pcb->remote_port;
-#if LWIP_CALLBACK_API
-    errf = pcb->errf;
-#endif /* LWIP_CALLBACK_API */
-    errf_arg = pcb->callback_arg;
-    tcp_pcb_remove(&tcp_active_pcbs, pcb);
-    if (pcb->unacked != NULL) {
-      tcp_segs_free(pcb->unacked);
-    }
-    if (pcb->unsent != NULL) {
-      tcp_segs_free(pcb->unsent);
-    }
-#if TCP_QUEUE_OOSEQ    
-    if (pcb->ooseq != NULL) {
-      tcp_segs_free(pcb->ooseq);
-    }
-#endif /* TCP_QUEUE_OOSEQ */
-    memp_free(MEMP_TCP_PCB, pcb);
-    TCP_EVENT_ERR(errf, errf_arg, ERR_ABRT);
-    LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_abort: sending RST\n"));
-    tcp_rst(seqno, ackno, &local_ip, &remote_ip, local_port, remote_port);
-  }
-}
-
-/**
- * Binds the connection to a local portnumber and IP address. If the
- * IP address is not given (i.e., ipaddr == NULL), the IP address of
- * the outgoing network interface is used instead.
- *
- */
-
-err_t
-tcp_bind(struct tcp_pcb *pcb, struct ip_addr *ipaddr, u16_t port)
-{
-  struct tcp_pcb *cpcb;
-
-  if (port == 0) {
-    port = tcp_new_port();
-  }
-  /* Check if the address already is in use. */
-  for(cpcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs;
-      cpcb != NULL; cpcb = cpcb->next) {
-    if (cpcb->local_port == port) {
-      if (ip_addr_isany(&(cpcb->local_ip)) ||
-        ip_addr_isany(ipaddr) ||
-        ip_addr_cmp(&(cpcb->local_ip), ipaddr)) {
-          return ERR_USE;
-      }
-    }
-  }
-  for(cpcb = tcp_active_pcbs;
-      cpcb != NULL; cpcb = cpcb->next) {
-    if (cpcb->local_port == port) {
-      if (ip_addr_isany(&(cpcb->local_ip)) ||
-   ip_addr_isany(ipaddr) ||
-   ip_addr_cmp(&(cpcb->local_ip), ipaddr)) {
-  return ERR_USE;
-      }
-    }
-  }
-
-  if (!ip_addr_isany(ipaddr)) {
-    pcb->local_ip = *ipaddr;
-  }
-  pcb->local_port = port;
-  LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: bind to port %"U16_F"\n", port));
-  return ERR_OK;
-}
-#if LWIP_CALLBACK_API
-static err_t
-tcp_accept_null(void *arg, struct tcp_pcb *pcb, err_t err)
-{
-  (void)arg;
-  (void)pcb;
-  (void)err;
-
-  return ERR_ABRT;
-}
-#endif /* LWIP_CALLBACK_API */
-
-/**
- * Set the state of the connection to be LISTEN, which means that it
- * is able to accept incoming connections. The protocol control block
- * is reallocated in order to consume less memory. Setting the
- * connection to LISTEN is an irreversible process.
- *
- */
-struct tcp_pcb *
-tcp_listen(struct tcp_pcb *pcb)
-{
-  struct tcp_pcb_listen *lpcb;
-
-  /* already listening? */
-  if (pcb->state == LISTEN) {
-    return pcb;
-  }
-  lpcb = memp_malloc(MEMP_TCP_PCB_LISTEN);
-  if (lpcb == NULL) {
-    return NULL;
-  }
-  lpcb->callback_arg = pcb->callback_arg;
-  lpcb->local_port = pcb->local_port;
-  lpcb->state = LISTEN;
-  lpcb->so_options = pcb->so_options;
-  lpcb->so_options |= SOF_ACCEPTCONN;
-  lpcb->ttl = pcb->ttl;
-  lpcb->tos = pcb->tos;
-  ip_addr_set(&lpcb->local_ip, &pcb->local_ip);
-  memp_free(MEMP_TCP_PCB, pcb);
-#if LWIP_CALLBACK_API
-  lpcb->accept = tcp_accept_null;
-#endif /* LWIP_CALLBACK_API */
-  TCP_REG(&tcp_listen_pcbs.listen_pcbs, lpcb);
-  return (struct tcp_pcb *)lpcb;
-}
-
-/**
- * This function should be called by the application when it has
- * processed the data. The purpose is to advertise a larger window
- * when the data has been processed.
- *
- */
-void
-tcp_recved(struct tcp_pcb *pcb, u16_t len)
-{
-  if ((u32_t)pcb->rcv_wnd + len > TCP_WND) {
-    pcb->rcv_wnd = TCP_WND;
-  } else {
-    pcb->rcv_wnd += len;
-  }
-  if (!(pcb->flags & TF_ACK_DELAY) &&
-     !(pcb->flags & TF_ACK_NOW)) {
-    /*
-     * We send an ACK here (if one is not already pending, hence
-     * the above tests) as tcp_recved() implies that the application
-     * has processed some data, and so we can open the receiver's
-     * window to allow more to be transmitted.  This could result in
-     * two ACKs being sent for each received packet in some limited cases
-     * (where the application is only receiving data, and is slow to
-     * process it) but it is necessary to guarantee that the sender can
-     * continue to transmit.
-     */
-    tcp_ack(pcb);
-  } 
-  else if (pcb->flags & TF_ACK_DELAY && pcb->rcv_wnd >= TCP_WND/2) {
-    /* If we can send a window update such that there is a full
-     * segment available in the window, do so now.  This is sort of
-     * nagle-like in its goals, and tries to hit a compromise between
-     * sending acks each time the window is updated, and only sending
-     * window updates when a timer expires.  The "threshold" used
-     * above (currently TCP_WND/2) can be tuned to be more or less
-     * aggressive  */
-    tcp_ack_now(pcb);
-  }
-
-  LWIP_DEBUGF(TCP_DEBUG, ("tcp_recved: recveived %"U16_F" bytes, wnd %"U16_F" (%"U16_F").\n",
-         len, pcb->rcv_wnd, TCP_WND - pcb->rcv_wnd));
-}
-
-/**
- * A nastly hack featuring 'goto' statements that allocates a
- * new TCP local port.
- */
-static u16_t
-tcp_new_port(void)
-{
-  struct tcp_pcb *pcb;
-#ifndef TCP_LOCAL_PORT_RANGE_START
-#define TCP_LOCAL_PORT_RANGE_START 4096
-#define TCP_LOCAL_PORT_RANGE_END   0x7fff
-#endif
-  static u16_t port = TCP_LOCAL_PORT_RANGE_START;
-  
- again:
-  if (++port > TCP_LOCAL_PORT_RANGE_END) {
-    port = TCP_LOCAL_PORT_RANGE_START;
-  }
-  
-  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
-    if (pcb->local_port == port) {
-      goto again;
-    }
-  }
-  for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
-    if (pcb->local_port == port) {
-      goto again;
-    }
-  }
-  for(pcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; pcb != NULL; pcb = pcb->next) {
-    if (pcb->local_port == port) {
-      goto again;
-    }
-  }
-  return port;
-}
-
-/**
- * Connects to another host. The function given as the "connected"
- * argument will be called when the connection has been established.
- *
- */
-err_t
-tcp_connect(struct tcp_pcb *pcb, struct ip_addr *ipaddr, u16_t port,
-      err_t (* connected)(void *arg, struct tcp_pcb *tpcb, err_t err))
-{
-  u32_t optdata;
-  err_t ret;
-  u32_t iss;
-
-  LWIP_DEBUGF(TCP_DEBUG, ("tcp_connect to port %"U16_F"\n", port));
-  if (ipaddr != NULL) {
-    pcb->remote_ip = *ipaddr;
-  } else {
-    return ERR_VAL;
-  }
-  pcb->remote_port = port;
-  if (pcb->local_port == 0) {
-    pcb->local_port = tcp_new_port();
-  }
-  iss = tcp_next_iss();
-  pcb->rcv_nxt = 0;
-  pcb->snd_nxt = iss;
-  pcb->lastack = iss - 1;
-  pcb->snd_lbb = iss - 1;
-  pcb->rcv_wnd = TCP_WND;
-  pcb->snd_wnd = TCP_WND;
-  pcb->mss = TCP_MSS;
-  pcb->cwnd = 1;
-  pcb->ssthresh = pcb->mss * 10;
-  pcb->state = SYN_SENT;
-#if LWIP_CALLBACK_API  
-  pcb->connected = connected;
-#endif /* LWIP_CALLBACK_API */  
-  TCP_REG(&tcp_active_pcbs, pcb);
-  
-  /* Build an MSS option */
-  optdata = htonl(((u32_t)2 << 24) | 
-      ((u32_t)4 << 16) | 
-      (((u32_t)pcb->mss / 256) << 8) |
-      (pcb->mss & 255));
-
-  ret = tcp_enqueue(pcb, NULL, 0, TCP_SYN, 0, (u8_t *)&optdata, 4);
-  if (ret == ERR_OK) { 
-    tcp_output(pcb);
-  }
-  return ret;
-} 
-
-/**
- * Called every 500 ms and implements the retransmission timer and the timer that
- * removes PCBs that have been in TIME-WAIT for enough time. It also increments
- * various timers such as the inactivity timer in each PCB.
- */
-void
-tcp_slowtmr(void)
-{
-  struct tcp_pcb *pcb, *pcb2, *prev;
-  u32_t eff_wnd;
-  u8_t pcb_remove;      /* flag if a PCB should be removed */
-  err_t err;
-
-  err = ERR_OK;
-
-  ++tcp_ticks;
-
-  /* Steps through all of the active PCBs. */
-  prev = NULL;
-  pcb = tcp_active_pcbs;
-  if (pcb == NULL) {
-    LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: no active pcbs\n"));
-  }
-  while (pcb != NULL) {
-    LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: processing active pcb\n"));
-    LWIP_ASSERT("tcp_slowtmr: active pcb->state != CLOSED\n", pcb->state != CLOSED);
-    LWIP_ASSERT("tcp_slowtmr: active pcb->state != LISTEN\n", pcb->state != LISTEN);
-    LWIP_ASSERT("tcp_slowtmr: active pcb->state != TIME-WAIT\n", pcb->state != TIME_WAIT);
-
-    pcb_remove = 0;
-
-    if (pcb->state == SYN_SENT && pcb->nrtx == TCP_SYNMAXRTX) {
-      ++pcb_remove;
-      LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max SYN retries reached\n"));
-    }
-    else if (pcb->nrtx == TCP_MAXRTX) {
-      ++pcb_remove;
-      LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max DATA retries reached\n"));
-    } else {
-      ++pcb->rtime;
-      if (pcb->unacked != NULL && pcb->rtime >= pcb->rto) {
-
-        /* Time for a retransmission. */
-        LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_slowtmr: rtime %"U16_F" pcb->rto %"U16_F"\n",
-          pcb->rtime, pcb->rto));
-
-        /* Double retransmission time-out unless we are trying to
-         * connect to somebody (i.e., we are in SYN_SENT). */
-        if (pcb->state != SYN_SENT) {
-          pcb->rto = ((pcb->sa >> 3) + pcb->sv) << tcp_backoff[pcb->nrtx];
-        }
-        /* Reduce congestion window and ssthresh. */
-        eff_wnd = LWIP_MIN(pcb->cwnd, pcb->snd_wnd);
-        pcb->ssthresh = eff_wnd >> 1;
-        if (pcb->ssthresh < pcb->mss) {
-          pcb->ssthresh = pcb->mss * 2;
-        }
-        pcb->cwnd = pcb->mss;
-        LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: cwnd %"U16_F" ssthresh %"U16_F"\n",
-                                pcb->cwnd, pcb->ssthresh));
- 
-        /* The following needs to be called AFTER cwnd is set to one mss - STJ */
-        tcp_rexmit_rto(pcb);
-     }
-    }
-    /* Check if this PCB has stayed too long in FIN-WAIT-2 */
-    if (pcb->state == FIN_WAIT_2) {
-      if ((u32_t)(tcp_ticks - pcb->tmr) >
-        TCP_FIN_WAIT_TIMEOUT / TCP_SLOW_INTERVAL) {
-        ++pcb_remove;
-        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in FIN-WAIT-2\n"));
-      }
-    }
-
-   /* Check if KEEPALIVE should be sent */
-   if((pcb->so_options & SOF_KEEPALIVE) && ((pcb->state == ESTABLISHED) || (pcb->state == CLOSE_WAIT))) {
-      if((u32_t)(tcp_ticks - pcb->tmr) > (pcb->keepalive + TCP_MAXIDLE) / TCP_SLOW_INTERVAL)  {
-         LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: KEEPALIVE timeout. Aborting connection to %"U16_F".%"U16_F".%"U16_F".%"U16_F".\n",
-                                 ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip),
-                                 ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip)));
-
-         tcp_abort(pcb);
-      }
-      else if((u32_t)(tcp_ticks - pcb->tmr) > (pcb->keepalive + pcb->keep_cnt * TCP_KEEPINTVL) / TCP_SLOW_INTERVAL) {
-         tcp_keepalive(pcb);
-         pcb->keep_cnt++;
-      }
-   }
-
-    /* If this PCB has queued out of sequence data, but has been
-       inactive for too long, will drop the data (it will eventually
-       be retransmitted). */
-#if TCP_QUEUE_OOSEQ    
-    if (pcb->ooseq != NULL &&
-       (u32_t)tcp_ticks - pcb->tmr >=
-       pcb->rto * TCP_OOSEQ_TIMEOUT) {
-      tcp_segs_free(pcb->ooseq);
-      pcb->ooseq = NULL;
-      LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: dropping OOSEQ queued data\n"));
-    }
-#endif /* TCP_QUEUE_OOSEQ */
-
-    /* Check if this PCB has stayed too long in SYN-RCVD */
-    if (pcb->state == SYN_RCVD) {
-      if ((u32_t)(tcp_ticks - pcb->tmr) >
-        TCP_SYN_RCVD_TIMEOUT / TCP_SLOW_INTERVAL) {
-        ++pcb_remove;
-        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in SYN-RCVD\n"));
-      }
-    }
-
-    /* Check if this PCB has stayed too long in LAST-ACK */
-    if (pcb->state == LAST_ACK) {
-      if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) {
-        ++pcb_remove;
-        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in LAST-ACK\n"));
-      }
-    }
-
-    /* If the PCB should be removed, do it. */
-    if (pcb_remove) {
-      tcp_pcb_purge(pcb);      
-      /* Remove PCB from tcp_active_pcbs list. */
-      if (prev != NULL) {
-  LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_active_pcbs", pcb != tcp_active_pcbs);
-        prev->next = pcb->next;
-      } else {
-        /* This PCB was the first. */
-        LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_active_pcbs", tcp_active_pcbs == pcb);
-        tcp_active_pcbs = pcb->next;
-      }
-
-      TCP_EVENT_ERR(pcb->errf, pcb->callback_arg, ERR_ABRT);
-
-      pcb2 = pcb->next;
-      memp_free(MEMP_TCP_PCB, pcb);
-      pcb = pcb2;
-    } else {
-
-      /* We check if we should poll the connection. */
-      ++pcb->polltmr;
-      if (pcb->polltmr >= pcb->pollinterval) {
-        pcb->polltmr = 0;
-        LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: polling application\n"));
-        TCP_EVENT_POLL(pcb, err);
-        if (err == ERR_OK) {
-          tcp_output(pcb);
-        }
-      }
-      
-      prev = pcb;
-      pcb = pcb->next;
-    }
-  }
-
-  
-  /* Steps through all of the TIME-WAIT PCBs. */
-  prev = NULL;    
-  pcb = tcp_tw_pcbs;
-  while (pcb != NULL) {
-    LWIP_ASSERT("tcp_slowtmr: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT);
-    pcb_remove = 0;
-
-    /* Check if this PCB has stayed long enough in TIME-WAIT */
-    if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) {
-      ++pcb_remove;
-    }
-    
-
-
-    /* If the PCB should be removed, do it. */
-    if (pcb_remove) {
-      tcp_pcb_purge(pcb);      
-      /* Remove PCB from tcp_tw_pcbs list. */
-      if (prev != NULL) {
-  LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_tw_pcbs", pcb != tcp_tw_pcbs);
-        prev->next = pcb->next;
-      } else {
-        /* This PCB was the first. */
-        LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_tw_pcbs", tcp_tw_pcbs == pcb);
-        tcp_tw_pcbs = pcb->next;
-      }
-      pcb2 = pcb->next;
-      memp_free(MEMP_TCP_PCB, pcb);
-      pcb = pcb2;
-    } else {
-      prev = pcb;
-      pcb = pcb->next;
-    }
-  }
-}
-
-/**
- * Is called every TCP_FAST_INTERVAL (250 ms) and sends delayed ACKs.
- */
-void
-tcp_fasttmr(void)
-{
-  struct tcp_pcb *pcb;
-
-  /* send delayed ACKs */  
-  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
-    if (pcb->flags & TF_ACK_DELAY) {
-      LWIP_DEBUGF(TCP_DEBUG, ("tcp_fasttmr: delayed ACK\n"));
-      tcp_ack_now(pcb);
-      pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW);
-    }
-  }
-}
-
-/**
- * Deallocates a list of TCP segments (tcp_seg structures).
- *
- */
-u8_t
-tcp_segs_free(struct tcp_seg *seg)
-{
-  u8_t count = 0;
-  struct tcp_seg *next;
-  while (seg != NULL) {
-    next = seg->next;
-    count += tcp_seg_free(seg);
-    seg = next;
-  }
-  return count;
-}
-
-/**
- * Frees a TCP segment.
- *
- */
-u8_t
-tcp_seg_free(struct tcp_seg *seg)
-{
-  u8_t count = 0;
-  
-  if (seg != NULL) {
-    if (seg->p != NULL) {
-      count = pbuf_free(seg->p);
-#if TCP_DEBUG
-      seg->p = NULL;
-#endif /* TCP_DEBUG */
-    }
-    memp_free(MEMP_TCP_SEG, seg);
-  }
-  return count;
-}
-
-/**
- * Sets the priority of a connection.
- *
- */
-void
-tcp_setprio(struct tcp_pcb *pcb, u8_t prio)
-{
-  pcb->prio = prio;
-}
-#if TCP_QUEUE_OOSEQ
-
-/**
- * Returns a copy of the given TCP segment.
- *
- */ 
-struct tcp_seg *
-tcp_seg_copy(struct tcp_seg *seg)
-{
-  struct tcp_seg *cseg;
-
-  cseg = memp_malloc(MEMP_TCP_SEG);
-  if (cseg == NULL) {
-    return NULL;
-  }
-  memcpy((u8_t *)cseg, (const u8_t *)seg, sizeof(struct tcp_seg)); 
-  pbuf_ref(cseg->p);
-  return cseg;
-}
-#endif
-
-#if LWIP_CALLBACK_API
-static err_t
-tcp_recv_null(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err)
-{
-  arg = arg;
-  if (p != NULL) {
-    pbuf_free(p);
-  } else if (err == ERR_OK) {
-    return tcp_close(pcb);
-  }
-  return ERR_OK;
-}
-#endif /* LWIP_CALLBACK_API */
-
-static void
-tcp_kill_prio(u8_t prio)
-{
-  struct tcp_pcb *pcb, *inactive;
-  u32_t inactivity;
-  u8_t mprio;
-
-
-  mprio = TCP_PRIO_MAX;
-  
-  /* We kill the oldest active connection that has lower priority than
-     prio. */
-  inactivity = 0;
-  inactive = NULL;
-  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
-    if (pcb->prio <= prio &&
-       pcb->prio <= mprio &&
-       (u32_t)(tcp_ticks - pcb->tmr) >= inactivity) {
-      inactivity = tcp_ticks - pcb->tmr;
-      inactive = pcb;
-      mprio = pcb->prio;
-    }
-  }
-  if (inactive != NULL) {
-    LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_prio: killing oldest PCB %p (%"S32_F")\n",
-           (void *)inactive, inactivity));
-    tcp_abort(inactive);
-  }      
-}
-
-
-static void
-tcp_kill_timewait(void)
-{
-  struct tcp_pcb *pcb, *inactive;
-  u32_t inactivity;
-
-  inactivity = 0;
-  inactive = NULL;
-  for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
-    if ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity) {
-      inactivity = tcp_ticks - pcb->tmr;
-      inactive = pcb;
-    }
-  }
-  if (inactive != NULL) {
-    LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_timewait: killing oldest TIME-WAIT PCB %p (%"S32_F")\n",
-           (void *)inactive, inactivity));
-    tcp_abort(inactive);
-  }      
-}
-
-
-
-struct tcp_pcb *
-tcp_alloc(u8_t prio)
-{
-  struct tcp_pcb *pcb;
-  u32_t iss;
-  
-  pcb = memp_malloc(MEMP_TCP_PCB);
-  if (pcb == NULL) {
-    /* Try killing oldest connection in TIME-WAIT. */
-    LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest TIME-WAIT connection\n"));
-    tcp_kill_timewait();
-    pcb = memp_malloc(MEMP_TCP_PCB);
-    if (pcb == NULL) {
-      tcp_kill_prio(prio);    
-      pcb = memp_malloc(MEMP_TCP_PCB);
-    }
-  }
-  if (pcb != NULL) {
-    memset(pcb, 0, sizeof(struct tcp_pcb));
-    pcb->prio = TCP_PRIO_NORMAL;
-    pcb->snd_buf = TCP_SND_BUF;
-    pcb->snd_queuelen = 0;
-    pcb->rcv_wnd = TCP_WND;
-    pcb->tos = 0;
-    pcb->ttl = TCP_TTL;
-    pcb->mss = TCP_MSS;
-    pcb->rto = 3000 / TCP_SLOW_INTERVAL;
-    pcb->sa = 0;
-    pcb->sv = 3000 / TCP_SLOW_INTERVAL;
-    pcb->rtime = 0;
-    pcb->cwnd = 1;
-    iss = tcp_next_iss();
-    pcb->snd_wl2 = iss;
-    pcb->snd_nxt = iss;
-    pcb->snd_max = iss;
-    pcb->lastack = iss;
-    pcb->snd_lbb = iss;   
-    pcb->tmr = tcp_ticks;
-
-    pcb->polltmr = 0;
-
-#if LWIP_CALLBACK_API
-    pcb->recv = tcp_recv_null;
-#endif /* LWIP_CALLBACK_API */  
-    
-    /* Init KEEPALIVE timer */
-    pcb->keepalive = TCP_KEEPDEFAULT;
-    pcb->keep_cnt = 0;
-  }
-  return pcb;
-}
-
-/**
- * Creates a new TCP protocol control block but doesn't place it on
- * any of the TCP PCB lists.
- *
- * @internal: Maybe there should be a idle TCP PCB list where these
- * PCBs are put on. We can then implement port reservation using
- * tcp_bind(). Currently, we lack this (BSD socket type of) feature.
- */
-
-struct tcp_pcb *
-tcp_new(void)
-{
-  return tcp_alloc(TCP_PRIO_NORMAL);
-}
-
-/*
- * tcp_arg():
- *
- * Used to specify the argument that should be passed callback
- * functions.
- *
- */ 
-
-void
-tcp_arg(struct tcp_pcb *pcb, void *arg)
-{  
-  pcb->callback_arg = arg;
-}
-#if LWIP_CALLBACK_API
-
-/**
- * Used to specify the function that should be called when a TCP
- * connection receives data.
- *
- */ 
-void
-tcp_recv(struct tcp_pcb *pcb,
-   err_t (* recv)(void *arg, struct tcp_pcb *tpcb, struct pbuf *p, err_t err))
-{
-  pcb->recv = recv;
-}
-
-/**
- * Used to specify the function that should be called when TCP data
- * has been successfully delivered to the remote host.
- *
- */ 
-
-void
-tcp_sent(struct tcp_pcb *pcb,
-   err_t (* sent)(void *arg, struct tcp_pcb *tpcb, u16_t len))
-{
-  pcb->sent = sent;
-}
-
-/**
- * Used to specify the function that should be called when a fatal error
- * has occured on the connection.
- *
- */ 
-void
-tcp_err(struct tcp_pcb *pcb,
-   void (* errf)(void *arg, err_t err))
-{
-  pcb->errf = errf;
-}
-
-/**
- * Used for specifying the function that should be called when a
- * LISTENing connection has been connected to another host.
- *
- */ 
-void
-tcp_accept(struct tcp_pcb *pcb,
-     err_t (* accept)(void *arg, struct tcp_pcb *newpcb, err_t err))
-{
-  ((struct tcp_pcb_listen *)pcb)->accept = accept;
-}
-#endif /* LWIP_CALLBACK_API */
-
-
-/**
- * Used to specify the function that should be called periodically
- * from TCP. The interval is specified in terms of the TCP coarse
- * timer interval, which is called twice a second.
- *
- */ 
-void
-tcp_poll(struct tcp_pcb *pcb,
-   err_t (* poll)(void *arg, struct tcp_pcb *tpcb), u8_t interval)
-{
-#if LWIP_CALLBACK_API
-  pcb->poll = poll;
-#endif /* LWIP_CALLBACK_API */  
-  pcb->pollinterval = interval;
-}
-
-/**
- * Purges a TCP PCB. Removes any buffered data and frees the buffer memory.
- *
- */
-void
-tcp_pcb_purge(struct tcp_pcb *pcb)
-{
-  if (pcb->state != CLOSED &&
-     pcb->state != TIME_WAIT &&
-     pcb->state != LISTEN) {
-
-    LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge\n"));
-    
-    if (pcb->unsent != NULL) {    
-      LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: not all data sent\n"));
-    }
-    if (pcb->unacked != NULL) {    
-      LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->unacked\n"));
-    }
-#if TCP_QUEUE_OOSEQ /* LW */
-    if (pcb->ooseq != NULL) {    
-      LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->ooseq\n"));
-    }
-    
-    tcp_segs_free(pcb->ooseq);
-    pcb->ooseq = NULL;
-#endif /* TCP_QUEUE_OOSEQ */
-    tcp_segs_free(pcb->unsent);
-    tcp_segs_free(pcb->unacked);
-    pcb->unacked = pcb->unsent = NULL;
-  }
-}
-
-/**
- * Purges the PCB and removes it from a PCB list. Any delayed ACKs are sent first.
- *
- */
-void
-tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb)
-{
-  TCP_RMV(pcblist, pcb);
-
-  tcp_pcb_purge(pcb);
-  
-  /* if there is an outstanding delayed ACKs, send it */
-  if (pcb->state != TIME_WAIT &&
-     pcb->state != LISTEN &&
-     pcb->flags & TF_ACK_DELAY) {
-    pcb->flags |= TF_ACK_NOW;
-    tcp_output(pcb);
-  }  
-  pcb->state = CLOSED;
-
-  LWIP_ASSERT("tcp_pcb_remove: tcp_pcbs_sane()", tcp_pcbs_sane());
-}
-
-/**
- * Calculates a new initial sequence number for new connections.
- *
- */
-u32_t
-tcp_next_iss(void)
-{
-  static u32_t iss = 6510;
-  
-  iss += tcp_ticks;       /* XXX */
-  return iss;
-}
-
-#if TCP_DEBUG || TCP_INPUT_DEBUG || TCP_OUTPUT_DEBUG
-void
-tcp_debug_print(struct tcp_hdr *tcphdr)
-{
-  LWIP_DEBUGF(TCP_DEBUG, ("TCP header:\n"));
-  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
-  LWIP_DEBUGF(TCP_DEBUG, ("|    %5"U16_F"      |    %5"U16_F"      | (src port, dest port)\n",
-         ntohs(tcphdr->src), ntohs(tcphdr->dest)));
-  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
-  LWIP_DEBUGF(TCP_DEBUG, ("|           %010"U32_F"          | (seq no)\n",
-          ntohl(tcphdr->seqno)));
-  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
-  LWIP_DEBUGF(TCP_DEBUG, ("|           %010"U32_F"          | (ack no)\n",
-         ntohl(tcphdr->ackno)));
-  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
-  LWIP_DEBUGF(TCP_DEBUG, ("| %2"U16_F" |   |%"U16_F"%"U16_F"%"U16_F"%"U16_F"%"U16_F"%"U16_F"|     %5"U16_F"     | (hdrlen, flags (",
-       TCPH_HDRLEN(tcphdr),
-         TCPH_FLAGS(tcphdr) >> 5 & 1,
-         TCPH_FLAGS(tcphdr) >> 4 & 1,
-         TCPH_FLAGS(tcphdr) >> 3 & 1,
-         TCPH_FLAGS(tcphdr) >> 2 & 1,
-         TCPH_FLAGS(tcphdr) >> 1 & 1,
-         TCPH_FLAGS(tcphdr) & 1,
-         ntohs(tcphdr->wnd)));
-  tcp_debug_print_flags(TCPH_FLAGS(tcphdr));
-  LWIP_DEBUGF(TCP_DEBUG, ("), win)\n"));
-  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
-  LWIP_DEBUGF(TCP_DEBUG, ("|    0x%04"X16_F"     |     %5"U16_F"     | (chksum, urgp)\n",
-         ntohs(tcphdr->chksum), ntohs(tcphdr->urgp)));
-  LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n"));
-}
-
-void
-tcp_debug_print_state(enum tcp_state s)
-{
-  LWIP_DEBUGF(TCP_DEBUG, ("State: "));
-  switch (s) {
-  case CLOSED:
-    LWIP_DEBUGF(TCP_DEBUG, ("CLOSED\n"));
-    break;
- case LISTEN:
-   LWIP_DEBUGF(TCP_DEBUG, ("LISTEN\n"));
-   break;
-  case SYN_SENT:
-    LWIP_DEBUGF(TCP_DEBUG, ("SYN_SENT\n"));
-    break;
-  case SYN_RCVD:
-    LWIP_DEBUGF(TCP_DEBUG, ("SYN_RCVD\n"));
-    break;
-  case ESTABLISHED:
-    LWIP_DEBUGF(TCP_DEBUG, ("ESTABLISHED\n"));
-    break;
-  case FIN_WAIT_1:
-    LWIP_DEBUGF(TCP_DEBUG, ("FIN_WAIT_1\n"));
-    break;
-  case FIN_WAIT_2:
-    LWIP_DEBUGF(TCP_DEBUG, ("FIN_WAIT_2\n"));
-    break;
-  case CLOSE_WAIT:
-    LWIP_DEBUGF(TCP_DEBUG, ("CLOSE_WAIT\n"));
-    break;
-  case CLOSING:
-    LWIP_DEBUGF(TCP_DEBUG, ("CLOSING\n"));
-    break;
-  case LAST_ACK:
-    LWIP_DEBUGF(TCP_DEBUG, ("LAST_ACK\n"));
-    break;
-  case TIME_WAIT:
-    LWIP_DEBUGF(TCP_DEBUG, ("TIME_WAIT\n"));
-   break;
-  }
-}
-
-void
-tcp_debug_print_flags(u8_t flags)
-{
-  if (flags & TCP_FIN) {
-    LWIP_DEBUGF(TCP_DEBUG, ("FIN "));
-  }
-  if (flags & TCP_SYN) {
-    LWIP_DEBUGF(TCP_DEBUG, ("SYN "));
-  }
-  if (flags & TCP_RST) {
-    LWIP_DEBUGF(TCP_DEBUG, ("RST "));
-  }
-  if (flags & TCP_PSH) {
-    LWIP_DEBUGF(TCP_DEBUG, ("PSH "));
-  }
-  if (flags & TCP_ACK) {
-    LWIP_DEBUGF(TCP_DEBUG, ("ACK "));
-  }
-  if (flags & TCP_URG) {
-    LWIP_DEBUGF(TCP_DEBUG, ("URG "));
-  }
-  if (flags & TCP_ECE) {
-    LWIP_DEBUGF(TCP_DEBUG, ("ECE "));
-  }
-  if (flags & TCP_CWR) {
-    LWIP_DEBUGF(TCP_DEBUG, ("CWR "));
-  }
-}
-
-void
-tcp_debug_print_pcbs(void)
-{
-  struct tcp_pcb *pcb;
-  LWIP_DEBUGF(TCP_DEBUG, ("Active PCB states:\n"));
-  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
-    LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ",
-                       pcb->local_port, pcb->remote_port,
-                       pcb->snd_nxt, pcb->rcv_nxt));
-    tcp_debug_print_state(pcb->state);
-  }    
-  LWIP_DEBUGF(TCP_DEBUG, ("Listen PCB states:\n"));
-  for(pcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; pcb != NULL; pcb = pcb->next) {
-    LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ",
-                       pcb->local_port, pcb->remote_port,
-                       pcb->snd_nxt, pcb->rcv_nxt));
-    tcp_debug_print_state(pcb->state);
-  }    
-  LWIP_DEBUGF(TCP_DEBUG, ("TIME-WAIT PCB states:\n"));
-  for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
-    LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ",
-                       pcb->local_port, pcb->remote_port,
-                       pcb->snd_nxt, pcb->rcv_nxt));
-    tcp_debug_print_state(pcb->state);
-  }    
-}
-
-s16_t
-tcp_pcbs_sane(void)
-{
-  struct tcp_pcb *pcb;
-  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
-    LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != CLOSED", pcb->state != CLOSED);
-    LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != LISTEN", pcb->state != LISTEN);
-    LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT);
-  }
-  for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
-    LWIP_ASSERT("tcp_pcbs_sane: tw pcb->state == TIME-WAIT", pcb->state == TIME_WAIT);
-  }
-  return 1;
-}
-#endif /* TCP_DEBUG */
-#endif /* LWIP_TCP */
-
-
-
-
-
-
-
-
-
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/core/tcp_in.c b/Demo/lwIP_MCF5235_GCC/lwip/src/core/tcp_in.c
deleted file mode 100644
index 212f9c4db..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/core/tcp_in.c
+++ /dev/null
@@ -1,1199 +0,0 @@
-/**
- * @file
- *
- * Transmission Control Protocol, incoming traffic
- *
- * The input processing functions of TCP.
- *
- * These functions are generally called in the order (ip_input() ->) tcp_input() ->
- * tcp_process() -> tcp_receive() (-> application).
- * 
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels 
- *
- */
-
-#include "lwip/def.h"
-#include "lwip/opt.h"
-
-#include "lwip/ip_addr.h"
-#include "lwip/netif.h"
-#include "lwip/mem.h"
-#include "lwip/memp.h"
-
-#include "lwip/inet.h"
-#include "lwip/tcp.h"
-
-#include "lwip/stats.h"
-
-#include "arch/perf.h"
-#if LWIP_TCP
-/* These variables are global to all functions involved in the input
-   processing of TCP segments. They are set by the tcp_input()
-   function. */
-static struct tcp_seg inseg;
-static struct tcp_hdr *tcphdr;
-static struct ip_hdr *iphdr;
-static u32_t seqno, ackno;
-static u8_t flags;
-static u16_t tcplen;
-
-static u8_t recv_flags;
-static struct pbuf *recv_data;
-
-struct tcp_pcb *tcp_input_pcb;
-
-/* Forward declarations. */
-static err_t tcp_process(struct tcp_pcb *pcb);
-static void tcp_receive(struct tcp_pcb *pcb);
-static void tcp_parseopt(struct tcp_pcb *pcb);
-
-static err_t tcp_listen_input(struct tcp_pcb_listen *pcb);
-static err_t tcp_timewait_input(struct tcp_pcb *pcb);
-
-
-/* tcp_input:
- *
- * The initial input processing of TCP. It verifies the TCP header, demultiplexes
- * the segment between the PCBs and passes it on to tcp_process(), which implements
- * the TCP finite state machine. This function is called by the IP layer (in
- * ip_input()).
- */
-
-void
-tcp_input(struct pbuf *p, struct netif *inp)
-{
-  struct tcp_pcb *pcb, *prev;
-  struct tcp_pcb_listen *lpcb;
-  u8_t hdrlen;
-  err_t err;
-
-  PERF_START;
-
-  TCP_STATS_INC(tcp.recv);
-
-  iphdr = p->payload;
-  tcphdr = (struct tcp_hdr *)((u8_t *)p->payload + IPH_HL(iphdr) * 4);
-
-#if TCP_INPUT_DEBUG
-  tcp_debug_print(tcphdr);
-#endif
-
-  /* remove header from payload */
-  if (pbuf_header(p, -((s16_t)(IPH_HL(iphdr) * 4))) || (p->tot_len < sizeof(struct tcp_hdr))) {
-    /* drop short packets */
-    LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: short packet (%"U16_F" bytes) discarded\n", p->tot_len));
-    TCP_STATS_INC(tcp.lenerr);
-    TCP_STATS_INC(tcp.drop);
-    pbuf_free(p);
-    return;
-  }
-
-  /* Don't even process incoming broadcasts/multicasts. */
-  if (ip_addr_isbroadcast(&(iphdr->dest), inp) ||
-      ip_addr_ismulticast(&(iphdr->dest))) {
-    pbuf_free(p);
-    return;
-  }
-
-#if CHECKSUM_CHECK_TCP
-  /* Verify TCP checksum. */
-  if (inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src),
-      (struct ip_addr *)&(iphdr->dest),
-      IP_PROTO_TCP, p->tot_len) != 0) {
-      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packet discarded due to failing checksum 0x%04"X16_F"\n",
-        inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src), (struct ip_addr *)&(iphdr->dest),
-      IP_PROTO_TCP, p->tot_len)));
-#if TCP_DEBUG
-    tcp_debug_print(tcphdr);
-#endif /* TCP_DEBUG */
-    TCP_STATS_INC(tcp.chkerr);
-    TCP_STATS_INC(tcp.drop);
-
-    pbuf_free(p);
-    return;
-  }
-#endif
-
-  /* Move the payload pointer in the pbuf so that it points to the
-     TCP data instead of the TCP header. */
-  hdrlen = TCPH_HDRLEN(tcphdr);
-  pbuf_header(p, -(hdrlen * 4));
-
-  /* Convert fields in TCP header to host byte order. */
-  tcphdr->src = ntohs(tcphdr->src);
-  tcphdr->dest = ntohs(tcphdr->dest);
-  seqno = tcphdr->seqno = ntohl(tcphdr->seqno);
-  ackno = tcphdr->ackno = ntohl(tcphdr->ackno);
-  tcphdr->wnd = ntohs(tcphdr->wnd);
-
-  flags = TCPH_FLAGS(tcphdr) & TCP_FLAGS;
-  tcplen = p->tot_len + ((flags & TCP_FIN || flags & TCP_SYN)? 1: 0);
-
-  /* Demultiplex an incoming segment. First, we check if it is destined
-     for an active connection. */
-  prev = NULL;
-
-  
-  for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
-    LWIP_ASSERT("tcp_input: active pcb->state != CLOSED", pcb->state != CLOSED);
-    LWIP_ASSERT("tcp_input: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT);
-    LWIP_ASSERT("tcp_input: active pcb->state != LISTEN", pcb->state != LISTEN);
-    if (pcb->remote_port == tcphdr->src &&
-       pcb->local_port == tcphdr->dest &&
-       ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src)) &&
-       ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest))) {
-
-      /* Move this PCB to the front of the list so that subsequent
-   lookups will be faster (we exploit locality in TCP segment
-   arrivals). */
-      LWIP_ASSERT("tcp_input: pcb->next != pcb (before cache)", pcb->next != pcb);
-      if (prev != NULL) {
-  prev->next = pcb->next;
-  pcb->next = tcp_active_pcbs;
-  tcp_active_pcbs = pcb;
-      }
-      LWIP_ASSERT("tcp_input: pcb->next != pcb (after cache)", pcb->next != pcb);
-      break;
-    }
-    prev = pcb;
-  }
-
-  if (pcb == NULL) {
-    /* If it did not go to an active connection, we check the connections
-       in the TIME-WAIT state. */
-
-    for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
-      LWIP_ASSERT("tcp_input: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT);
-      if (pcb->remote_port == tcphdr->src &&
-   pcb->local_port == tcphdr->dest &&
-   ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src)) &&
-         ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest))) {
-  /* We don't really care enough to move this PCB to the front
-     of the list since we are not very likely to receive that
-     many segments for connections in TIME-WAIT. */
-  LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packed for TIME_WAITing connection.\n"));
-  tcp_timewait_input(pcb);
-  pbuf_free(p);
-  return;
-      }
-    }
-
-  /* Finally, if we still did not get a match, we check all PCBs that
-     are LISTENing for incoming connections. */
-    prev = NULL;
-    for(lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
-      if ((ip_addr_isany(&(lpcb->local_ip)) ||
-    ip_addr_cmp(&(lpcb->local_ip), &(iphdr->dest))) &&
-   lpcb->local_port == tcphdr->dest) {
-  /* Move this PCB to the front of the list so that subsequent
-     lookups will be faster (we exploit locality in TCP segment
-     arrivals). */
-  if (prev != NULL) {
-    ((struct tcp_pcb_listen *)prev)->next = lpcb->next;
-          /* our successor is the remainder of the listening list */
-    lpcb->next = tcp_listen_pcbs.listen_pcbs;
-          /* put this listening pcb at the head of the listening list */
-    tcp_listen_pcbs.listen_pcbs = lpcb;
-  }
-
-  LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packed for LISTENing connection.\n"));
-  tcp_listen_input(lpcb);
-  pbuf_free(p);
-  return;
-      }
-      prev = (struct tcp_pcb *)lpcb;
-    }
-  }
-
-#if TCP_INPUT_DEBUG
-  LWIP_DEBUGF(TCP_INPUT_DEBUG, ("+-+-+-+-+-+-+-+-+-+-+-+-+-+- tcp_input: flags "));
-  tcp_debug_print_flags(TCPH_FLAGS(tcphdr));
-  LWIP_DEBUGF(TCP_INPUT_DEBUG, ("-+-+-+-+-+-+-+-+-+-+-+-+-+-+\n"));
-#endif /* TCP_INPUT_DEBUG */
-
-
-  if (pcb != NULL) {
-    /* The incoming segment belongs to a connection. */
-#if TCP_INPUT_DEBUG
-#if TCP_DEBUG
-    tcp_debug_print_state(pcb->state);
-#endif /* TCP_DEBUG */
-#endif /* TCP_INPUT_DEBUG */
-
-    /* Set up a tcp_seg structure. */
-    inseg.next = NULL;
-    inseg.len = p->tot_len;
-    inseg.dataptr = p->payload;
-    inseg.p = p;
-    inseg.tcphdr = tcphdr;
-
-    recv_data = NULL;
-    recv_flags = 0;
-
-    tcp_input_pcb = pcb;
-    err = tcp_process(pcb);
-    tcp_input_pcb = NULL;
-    /* A return value of ERR_ABRT means that tcp_abort() was called
-       and that the pcb has been freed. If so, we don't do anything. */
-    if (err != ERR_ABRT) {
-      if (recv_flags & TF_RESET) {
-  /* TF_RESET means that the connection was reset by the other
-     end. We then call the error callback to inform the
-     application that the connection is dead before we
-     deallocate the PCB. */
-  TCP_EVENT_ERR(pcb->errf, pcb->callback_arg, ERR_RST);
-  tcp_pcb_remove(&tcp_active_pcbs, pcb);
-  memp_free(MEMP_TCP_PCB, pcb);
-      } else if (recv_flags & TF_CLOSED) {
-  /* The connection has been closed and we will deallocate the
-     PCB. */
-  tcp_pcb_remove(&tcp_active_pcbs, pcb);
-  memp_free(MEMP_TCP_PCB, pcb);
-      } else {
-  err = ERR_OK;
-  /* If the application has registered a "sent" function to be
-     called when new send buffer space is available, we call it
-     now. */
-  if (pcb->acked > 0) {
-    TCP_EVENT_SENT(pcb, pcb->acked, err);
-  }
-
-  if (recv_data != NULL) {
-    /* Notify application that data has been received. */
-    TCP_EVENT_RECV(pcb, recv_data, ERR_OK, err);
-  }
-
-  /* If a FIN segment was received, we call the callback
-     function with a NULL buffer to indicate EOF. */
-  if (recv_flags & TF_GOT_FIN) {
-    TCP_EVENT_RECV(pcb, NULL, ERR_OK, err);
-  }
-  /* If there were no errors, we try to send something out. */
-  if (err == ERR_OK) {
-    tcp_output(pcb);
-  }
-      }
-    }
-
-
-    /* We deallocate the incoming pbuf. If it was buffered by the
-       application, the application should have called pbuf_ref() to
-       increase the reference counter in the pbuf. If so, the buffer
-       isn't actually deallocated by the call to pbuf_free(), only the
-       reference count is decreased. */
-    if (inseg.p != NULL) pbuf_free(inseg.p);
-#if TCP_INPUT_DEBUG
-#if TCP_DEBUG
-    tcp_debug_print_state(pcb->state);
-#endif /* TCP_DEBUG */
-#endif /* TCP_INPUT_DEBUG */
-      
-  } else {
-
-    /* If no matching PCB was found, send a TCP RST (reset) to the
-       sender. */
-    LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_input: no PCB match found, resetting.\n"));
-    if (!(TCPH_FLAGS(tcphdr) & TCP_RST)) {
-      TCP_STATS_INC(tcp.proterr);
-      TCP_STATS_INC(tcp.drop);
-      tcp_rst(ackno, seqno + tcplen,
-        &(iphdr->dest), &(iphdr->src),
-        tcphdr->dest, tcphdr->src);
-    }
-    pbuf_free(p);
-  }
-
-  LWIP_ASSERT("tcp_input: tcp_pcbs_sane()", tcp_pcbs_sane());
-  PERF_STOP("tcp_input");
-}
-
-/* tcp_listen_input():
- *
- * Called by tcp_input() when a segment arrives for a listening
- * connection.
- */
-
-static err_t
-tcp_listen_input(struct tcp_pcb_listen *pcb)
-{
-  struct tcp_pcb *npcb;
-  u32_t optdata;
-
-  /* In the LISTEN state, we check for incoming SYN segments,
-     creates a new PCB, and responds with a SYN|ACK. */
-  if (flags & TCP_ACK) {
-    /* For incoming segments with the ACK flag set, respond with a
-       RST. */
-    LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_listen_input: ACK in LISTEN, sending reset\n"));
-    tcp_rst(ackno + 1, seqno + tcplen,
-      &(iphdr->dest), &(iphdr->src),
-      tcphdr->dest, tcphdr->src);
-  } else if (flags & TCP_SYN) {
-    LWIP_DEBUGF(TCP_DEBUG, ("TCP connection request %"U16_F" -> %"U16_F".\n", tcphdr->src, tcphdr->dest));
-    npcb = tcp_alloc(pcb->prio);
-    /* If a new PCB could not be created (probably due to lack of memory),
-       we don't do anything, but rely on the sender will retransmit the
-       SYN at a time when we have more memory available. */
-    if (npcb == NULL) {
-      LWIP_DEBUGF(TCP_DEBUG, ("tcp_listen_input: could not allocate PCB\n"));
-      TCP_STATS_INC(tcp.memerr);
-      return ERR_MEM;
-    }
-    /* Set up the new PCB. */
-    ip_addr_set(&(npcb->local_ip), &(iphdr->dest));
-    npcb->local_port = pcb->local_port;
-    ip_addr_set(&(npcb->remote_ip), &(iphdr->src));
-    npcb->remote_port = tcphdr->src;
-    npcb->state = SYN_RCVD;
-    npcb->rcv_nxt = seqno + 1;
-    npcb->snd_wnd = tcphdr->wnd;
-    npcb->ssthresh = npcb->snd_wnd;
-    npcb->snd_wl1 = seqno - 1;/* initialise to seqno-1 to force window update */
-    npcb->callback_arg = pcb->callback_arg;
-#if LWIP_CALLBACK_API
-    npcb->accept = pcb->accept;
-#endif /* LWIP_CALLBACK_API */
-    /* inherit socket options */
-    npcb->so_options = pcb->so_options & (SOF_DEBUG|SOF_DONTROUTE|SOF_KEEPALIVE|SOF_OOBINLINE|SOF_LINGER);
-    /* Register the new PCB so that we can begin receiving segments
-       for it. */
-    TCP_REG(&tcp_active_pcbs, npcb);
-
-    /* Parse any options in the SYN. */
-    tcp_parseopt(npcb);
-
-    /* Build an MSS option. */
-    optdata = htonl(((u32_t)2 << 24) |
-        ((u32_t)4 << 16) |
-        (((u32_t)npcb->mss / 256) << 8) |
-        (npcb->mss & 255));
-    /* Send a SYN|ACK together with the MSS option. */
-    tcp_enqueue(npcb, NULL, 0, TCP_SYN | TCP_ACK, 0, (u8_t *)&optdata, 4);
-    return tcp_output(npcb);
-  }
-  return ERR_OK;
-}
-
-/* tcp_timewait_input():
- *
- * Called by tcp_input() when a segment arrives for a connection in
- * TIME_WAIT.
- */
-
-static err_t
-tcp_timewait_input(struct tcp_pcb *pcb)
-{
-  if (TCP_SEQ_GT(seqno + tcplen, pcb->rcv_nxt)) {
-    pcb->rcv_nxt = seqno + tcplen;
-  }
-  if (tcplen > 0) {
-    tcp_ack_now(pcb);
-  }
-  return tcp_output(pcb);
-}
-
-/* tcp_process
- *
- * Implements the TCP state machine. Called by tcp_input. In some
- * states tcp_receive() is called to receive data. The tcp_seg
- * argument will be freed by the caller (tcp_input()) unless the
- * recv_data pointer in the pcb is set.
- */
-
-static err_t
-tcp_process(struct tcp_pcb *pcb)
-{
-  struct tcp_seg *rseg;
-  u8_t acceptable = 0;
-  err_t err;
-
-
-  err = ERR_OK;
-
-  /* Process incoming RST segments. */
-  if (flags & TCP_RST) {
-    /* First, determine if the reset is acceptable. */
-    if (pcb->state == SYN_SENT) {
-      if (ackno == pcb->snd_nxt) {
-        acceptable = 1;
-      }
-    } else {
-      /*if (TCP_SEQ_GEQ(seqno, pcb->rcv_nxt) &&
-          TCP_SEQ_LEQ(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {
-      */
-      if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt+pcb->rcv_wnd)) {
-        acceptable = 1;
-      }
-    }
-
-    if (acceptable) {
-      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: Connection RESET\n"));
-      LWIP_ASSERT("tcp_input: pcb->state != CLOSED", pcb->state != CLOSED);
-      recv_flags = TF_RESET;
-      pcb->flags &= ~TF_ACK_DELAY;
-      return ERR_RST;
-    } else {
-      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n",
-       seqno, pcb->rcv_nxt));
-      LWIP_DEBUGF(TCP_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n",
-       seqno, pcb->rcv_nxt));
-      return ERR_OK;
-    }
-  }
-
-  /* Update the PCB (in)activity timer. */
-  pcb->tmr = tcp_ticks;
-  pcb->keep_cnt = 0;
-
-  /* Do different things depending on the TCP state. */
-  switch (pcb->state) {
-  case SYN_SENT:
-    LWIP_DEBUGF(TCP_INPUT_DEBUG, ("SYN-SENT: ackno %"U32_F" pcb->snd_nxt %"U32_F" unacked %"U32_F"\n", ackno,
-     pcb->snd_nxt, ntohl(pcb->unacked->tcphdr->seqno)));
-    /* received SYN ACK with expected sequence number? */
-    if ((flags & TCP_ACK) && (flags & TCP_SYN)
-        && ackno == ntohl(pcb->unacked->tcphdr->seqno) + 1) {
-      pcb->snd_buf++;
-      pcb->rcv_nxt = seqno + 1;
-      pcb->lastack = ackno;
-      pcb->snd_wnd = tcphdr->wnd;
-      pcb->snd_wl1 = seqno - 1; /* initialise to seqno - 1 to force window update */
-      pcb->state = ESTABLISHED;
-      pcb->cwnd = pcb->mss;
-      --pcb->snd_queuelen;
-      LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_process: SYN-SENT --queuelen %"U16_F"\n", (u16_t)pcb->snd_queuelen));
-      rseg = pcb->unacked;
-      pcb->unacked = rseg->next;
-      tcp_seg_free(rseg);
-
-      /* Parse any options in the SYNACK. */
-      tcp_parseopt(pcb);
-
-      /* Call the user specified function to call when sucessfully
-       * connected. */
-      TCP_EVENT_CONNECTED(pcb, ERR_OK, err);
-      tcp_ack(pcb);
-    }
-    /* received ACK? possibly a half-open connection */
-    else if (flags & TCP_ACK) {
-      /* send a RST to bring the other side in a non-synchronized state. */
-      tcp_rst(ackno, seqno + tcplen, &(iphdr->dest), &(iphdr->src),
-        tcphdr->dest, tcphdr->src);
-    }
-    break;
-  case SYN_RCVD:
-    if (flags & TCP_ACK &&
-       !(flags & TCP_RST)) {
-      /* expected ACK number? */
-      if (TCP_SEQ_BETWEEN(ackno, pcb->lastack+1, pcb->snd_nxt)) {
-        pcb->state = ESTABLISHED;
-        LWIP_DEBUGF(TCP_DEBUG, ("TCP connection established %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
-#if LWIP_CALLBACK_API
-        LWIP_ASSERT("pcb->accept != NULL", pcb->accept != NULL);
-#endif
-        /* Call the accept function. */
-        TCP_EVENT_ACCEPT(pcb, ERR_OK, err);
-        if (err != ERR_OK) {
-          /* If the accept function returns with an error, we abort
-           * the connection. */
-          tcp_abort(pcb);
-          return ERR_ABRT;
-        }
-        /* If there was any data contained within this ACK,
-         * we'd better pass it on to the application as well. */
-        tcp_receive(pcb);
-        pcb->cwnd = pcb->mss;
-      }
-      /* incorrect ACK number */
-      else {
-        /* send RST */
-        tcp_rst(ackno, seqno + tcplen, &(iphdr->dest), &(iphdr->src),
-          tcphdr->dest, tcphdr->src);
-      }
-    }
-    break;
-  case CLOSE_WAIT:
-    /* FALLTHROUGH */
-  case ESTABLISHED:
-    tcp_receive(pcb);
-    if (flags & TCP_FIN) {
-      tcp_ack_now(pcb);
-      pcb->state = CLOSE_WAIT;
-    }
-    break;
-  case FIN_WAIT_1:
-    tcp_receive(pcb);
-    if (flags & TCP_FIN) {
-      if (flags & TCP_ACK && ackno == pcb->snd_nxt) {
-        LWIP_DEBUGF(TCP_DEBUG,
-          ("TCP connection closed %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
-        tcp_ack_now(pcb);
-        tcp_pcb_purge(pcb);
-        TCP_RMV(&tcp_active_pcbs, pcb);
-        pcb->state = TIME_WAIT;
-        TCP_REG(&tcp_tw_pcbs, pcb);
-      } else {
-        tcp_ack_now(pcb);
-        pcb->state = CLOSING;
-      }
-    } else if (flags & TCP_ACK && ackno == pcb->snd_nxt) {
-      pcb->state = FIN_WAIT_2;
-    }
-    break;
-  case FIN_WAIT_2:
-    tcp_receive(pcb);
-    if (flags & TCP_FIN) {
-      LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
-      tcp_ack_now(pcb);
-      tcp_pcb_purge(pcb);
-      TCP_RMV(&tcp_active_pcbs, pcb);
-      pcb->state = TIME_WAIT;
-      TCP_REG(&tcp_tw_pcbs, pcb);
-    }
-    break;
-  case CLOSING:
-    tcp_receive(pcb);
-    if (flags & TCP_ACK && ackno == pcb->snd_nxt) {
-      LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
-      tcp_ack_now(pcb);
-      tcp_pcb_purge(pcb);
-      TCP_RMV(&tcp_active_pcbs, pcb);
-      pcb->state = TIME_WAIT;
-      TCP_REG(&tcp_tw_pcbs, pcb);
-    }
-    break;
-  case LAST_ACK:
-    tcp_receive(pcb);
-    if (flags & TCP_ACK && ackno == pcb->snd_nxt) {
-      LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
-      pcb->state = CLOSED;
-      recv_flags = TF_CLOSED;
-    }
-    break;
-  default:
-    break;
-  }
-  return ERR_OK;
-}
-
-/* tcp_receive:
- *
- * Called by tcp_process. Checks if the given segment is an ACK for outstanding
- * data, and if so frees the memory of the buffered data. Next, is places the
- * segment on any of the receive queues (pcb->recved or pcb->ooseq). If the segment
- * is buffered, the pbuf is referenced by pbuf_ref so that it will not be freed until
- * i it has been removed from the buffer.
- *
- * If the incoming segment constitutes an ACK for a segment that was used for RTT
- * estimation, the RTT is estimated here as well.
- */
-
-static void
-tcp_receive(struct tcp_pcb *pcb)
-{
-  struct tcp_seg *next;
-#if TCP_QUEUE_OOSEQ
-  struct tcp_seg *prev, *cseg;
-#endif
-  struct pbuf *p;
-  s32_t off;
-  s16_t m;
-  u32_t right_wnd_edge;
-  u16_t new_tot_len;
-
-
-  if (flags & TCP_ACK) {
-    right_wnd_edge = pcb->snd_wnd + pcb->snd_wl1;
-
-    /* Update window. */
-    if (TCP_SEQ_LT(pcb->snd_wl1, seqno) ||
-       (pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) ||
-       (pcb->snd_wl2 == ackno && tcphdr->wnd > pcb->snd_wnd)) {
-      pcb->snd_wnd = tcphdr->wnd;
-      pcb->snd_wl1 = seqno;
-      pcb->snd_wl2 = ackno;
-      LWIP_DEBUGF(TCP_WND_DEBUG, ("tcp_receive: window update %"U32_F"\n", pcb->snd_wnd));
-#if TCP_WND_DEBUG
-    } else {
-      if (pcb->snd_wnd != tcphdr->wnd) {
-        LWIP_DEBUGF(TCP_WND_DEBUG, ("tcp_receive: no window update lastack %"U32_F" snd_max %"U32_F" ackno %"U32_F" wl1 %"U32_F" seqno %"U32_F" wl2 %"U32_F"\n",
-                               pcb->lastack, pcb->snd_max, ackno, pcb->snd_wl1, seqno, pcb->snd_wl2));
-      }
-#endif /* TCP_WND_DEBUG */
-    }
-
-
-    if (pcb->lastack == ackno) {
-      pcb->acked = 0;
-
-      if (pcb->snd_wl1 + pcb->snd_wnd == right_wnd_edge){
-        ++pcb->dupacks;
-        if (pcb->dupacks >= 3 && pcb->unacked != NULL) {
-          if (!(pcb->flags & TF_INFR)) {
-            /* This is fast retransmit. Retransmit the first unacked segment. */
-            LWIP_DEBUGF(TCP_FR_DEBUG, ("tcp_receive: dupacks %"U16_F" (%"U32_F"), fast retransmit %"U32_F"\n",
-                                       (u16_t)pcb->dupacks, pcb->lastack,
-                                       ntohl(pcb->unacked->tcphdr->seqno)));
-            tcp_rexmit(pcb);
-            /* Set ssthresh to max (FlightSize / 2, 2*SMSS) */
-            /*pcb->ssthresh = LWIP_MAX((pcb->snd_max -
-                                      pcb->lastack) / 2,
-                                      2 * pcb->mss);*/
-            /* Set ssthresh to half of the minimum of the currenct cwnd and the advertised window */
-            if(pcb->cwnd > pcb->snd_wnd)
-              pcb->ssthresh = pcb->snd_wnd / 2;
-            else
-              pcb->ssthresh = pcb->cwnd / 2;
-
-            pcb->cwnd = pcb->ssthresh + 3 * pcb->mss;
-            pcb->flags |= TF_INFR;
-          } else {
-            /* Inflate the congestion window, but not if it means that
-               the value overflows. */
-            if ((u16_t)(pcb->cwnd + pcb->mss) > pcb->cwnd) {
-              pcb->cwnd += pcb->mss;
-            }
-          }
-        }
-      } else {
-        LWIP_DEBUGF(TCP_FR_DEBUG, ("tcp_receive: dupack averted %"U32_F" %"U32_F"\n",
-                                   pcb->snd_wl1 + pcb->snd_wnd, right_wnd_edge));
-      }
-    } else
-      /*if (TCP_SEQ_LT(pcb->lastack, ackno) &&
-        TCP_SEQ_LEQ(ackno, pcb->snd_max)) { */
-      if(TCP_SEQ_BETWEEN(ackno, pcb->lastack+1, pcb->snd_max)){
-      /* We come here when the ACK acknowledges new data. */
-      
-      /* Reset the "IN Fast Retransmit" flag, since we are no longer
-         in fast retransmit. Also reset the congestion window to the
-         slow start threshold. */
-      if (pcb->flags & TF_INFR) {
-        pcb->flags &= ~TF_INFR;
-        pcb->cwnd = pcb->ssthresh;
-      }
-
-      /* Reset the number of retransmissions. */
-      pcb->nrtx = 0;
-
-      /* Reset the retransmission time-out. */
-      pcb->rto = (pcb->sa >> 3) + pcb->sv;
-
-      /* Update the send buffer space. */
-      pcb->acked = ackno - pcb->lastack;
-
-      pcb->snd_buf += pcb->acked;
-
-      /* Reset the fast retransmit variables. */
-      pcb->dupacks = 0;
-      pcb->lastack = ackno;
-
-      /* Update the congestion control variables (cwnd and
-         ssthresh). */
-      if (pcb->state >= ESTABLISHED) {
-        if (pcb->cwnd < pcb->ssthresh) {
-          if ((u16_t)(pcb->cwnd + pcb->mss) > pcb->cwnd) {
-            pcb->cwnd += pcb->mss;
-          }
-          LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: slow start cwnd %"U16_F"\n", pcb->cwnd));
-        } else {
-          u16_t new_cwnd = (pcb->cwnd + pcb->mss * pcb->mss / pcb->cwnd);
-          if (new_cwnd > pcb->cwnd) {
-            pcb->cwnd = new_cwnd;
-          }
-          LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: congestion avoidance cwnd %"U16_F"\n", pcb->cwnd));
-        }
-      }
-      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: ACK for %"U32_F", unacked->seqno %"U32_F":%"U32_F"\n",
-                                    ackno,
-                                    pcb->unacked != NULL?
-                                    ntohl(pcb->unacked->tcphdr->seqno): 0,
-                                    pcb->unacked != NULL?
-                                    ntohl(pcb->unacked->tcphdr->seqno) + TCP_TCPLEN(pcb->unacked): 0));
-
-      /* Remove segment from the unacknowledged list if the incoming
-         ACK acknowlegdes them. */
-      while (pcb->unacked != NULL &&
-             TCP_SEQ_LEQ(ntohl(pcb->unacked->tcphdr->seqno) +
-                         TCP_TCPLEN(pcb->unacked), ackno)) {
-        LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %"U32_F":%"U32_F" from pcb->unacked\n",
-                                      ntohl(pcb->unacked->tcphdr->seqno),
-                                      ntohl(pcb->unacked->tcphdr->seqno) +
-                                      TCP_TCPLEN(pcb->unacked)));
-
-        next = pcb->unacked;
-        pcb->unacked = pcb->unacked->next;
-
-        LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %"U16_F" ... ", (u16_t)pcb->snd_queuelen));
-        pcb->snd_queuelen -= pbuf_clen(next->p);
-        tcp_seg_free(next);
-
-        LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%"U16_F" (after freeing unacked)\n", (u16_t)pcb->snd_queuelen));
-        if (pcb->snd_queuelen != 0) {
-          LWIP_ASSERT("tcp_receive: valid queue length", pcb->unacked != NULL ||
-                      pcb->unsent != NULL);
-        }
-      }
-      pcb->polltmr = 0;
-    }
-
-    /* We go through the ->unsent list to see if any of the segments
-       on the list are acknowledged by the ACK. This may seem
-       strange since an "unsent" segment shouldn't be acked. The
-       rationale is that lwIP puts all outstanding segments on the
-       ->unsent list after a retransmission, so these segments may
-       in fact have been sent once. */
-    while (pcb->unsent != NULL &&
-           /*TCP_SEQ_LEQ(ntohl(pcb->unsent->tcphdr->seqno) + TCP_TCPLEN(pcb->unsent), ackno) &&
-             TCP_SEQ_LEQ(ackno, pcb->snd_max)*/
-           TCP_SEQ_BETWEEN(ackno, ntohl(pcb->unsent->tcphdr->seqno) + TCP_TCPLEN(pcb->unsent), pcb->snd_max)
-           ) {
-      LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %"U32_F":%"U32_F" from pcb->unsent\n",
-                                    ntohl(pcb->unsent->tcphdr->seqno), ntohl(pcb->unsent->tcphdr->seqno) +
-                                    TCP_TCPLEN(pcb->unsent)));
-
-      next = pcb->unsent;
-      pcb->unsent = pcb->unsent->next;
-      LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %"U16_F" ... ", (u16_t)pcb->snd_queuelen));
-      pcb->snd_queuelen -= pbuf_clen(next->p);
-      tcp_seg_free(next);
-      LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%"U16_F" (after freeing unsent)\n", (u16_t)pcb->snd_queuelen));
-      if (pcb->snd_queuelen != 0) {
-        LWIP_ASSERT("tcp_receive: valid queue length",
-          pcb->unacked != NULL || pcb->unsent != NULL);
-      }
-
-      if (pcb->unsent != NULL) {
-        pcb->snd_nxt = htonl(pcb->unsent->tcphdr->seqno);
-      }
-    }
-    /* End of ACK for new data processing. */
-
-    LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: pcb->rttest %"U32_F" rtseq %"U32_F" ackno %"U32_F"\n",
-                                pcb->rttest, pcb->rtseq, ackno));
-
-    /* RTT estimation calculations. This is done by checking if the
-       incoming segment acknowledges the segment we use to take a
-       round-trip time measurement. */
-    if (pcb->rttest && TCP_SEQ_LT(pcb->rtseq, ackno)) {
-      m = tcp_ticks - pcb->rttest;
-
-      LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: experienced rtt %"U16_F" ticks (%"U16_F" msec).\n",
-                                  m, m * TCP_SLOW_INTERVAL));
-
-      /* This is taken directly from VJs original code in his paper */
-      m = m - (pcb->sa >> 3);
-      pcb->sa += m;
-      if (m < 0) {
-        m = -m;
-      }
-      m = m - (pcb->sv >> 2);
-      pcb->sv += m;
-      pcb->rto = (pcb->sa >> 3) + pcb->sv;
-
-      LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: RTO %"U16_F" (%"U16_F" miliseconds)\n",
-                                  pcb->rto, pcb->rto * TCP_SLOW_INTERVAL));
-
-      pcb->rttest = 0;
-    }
-  }
-
-  /* If the incoming segment contains data, we must process it
-     further. */
-  if (tcplen > 0) {
-    /* This code basically does three things:
-
-    +) If the incoming segment contains data that is the next
-    in-sequence data, this data is passed to the application. This
-    might involve trimming the first edge of the data. The rcv_nxt
-    variable and the advertised window are adjusted.
-
-    +) If the incoming segment has data that is above the next
-    sequence number expected (->rcv_nxt), the segment is placed on
-    the ->ooseq queue. This is done by finding the appropriate
-    place in the ->ooseq queue (which is ordered by sequence
-    number) and trim the segment in both ends if needed. An
-    immediate ACK is sent to indicate that we received an
-    out-of-sequence segment.
-
-    +) Finally, we check if the first segment on the ->ooseq queue
-    now is in sequence (i.e., if rcv_nxt >= ooseq->seqno). If
-    rcv_nxt > ooseq->seqno, we must trim the first edge of the
-    segment on ->ooseq before we adjust rcv_nxt. The data in the
-    segments that are now on sequence are chained onto the
-    incoming segment so that we only need to call the application
-    once.
-    */
-
-    /* First, we check if we must trim the first edge. We have to do
-       this if the sequence number of the incoming segment is less
-       than rcv_nxt, and the sequence number plus the length of the
-       segment is larger than rcv_nxt. */
-    /*    if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)){
-          if (TCP_SEQ_LT(pcb->rcv_nxt, seqno + tcplen)) {*/
-    if(TCP_SEQ_BETWEEN(pcb->rcv_nxt, seqno+1, seqno+tcplen-1)){
-      /* Trimming the first edge is done by pushing the payload
-         pointer in the pbuf downwards. This is somewhat tricky since
-         we do not want to discard the full contents of the pbuf up to
-         the new starting point of the data since we have to keep the
-         TCP header which is present in the first pbuf in the chain.
-         
-         What is done is really quite a nasty hack: the first pbuf in
-         the pbuf chain is pointed to by inseg.p. Since we need to be
-         able to deallocate the whole pbuf, we cannot change this
-         inseg.p pointer to point to any of the later pbufs in the
-         chain. Instead, we point the ->payload pointer in the first
-         pbuf to data in one of the later pbufs. We also set the
-         inseg.data pointer to point to the right place. This way, the
-         ->p pointer will still point to the first pbuf, but the
-         ->p->payload pointer will point to data in another pbuf.
-         
-         After we are done with adjusting the pbuf pointers we must
-         adjust the ->data pointer in the seg and the segment
-         length.*/
-      
-      off = pcb->rcv_nxt - seqno;
-      p = inseg.p;
-      if (inseg.p->len < off) {
-        new_tot_len = inseg.p->tot_len - off;
-        while (p->len < off) {
-          off -= p->len;
-          /* KJM following line changed (with addition of new_tot_len var)
-             to fix bug #9076
-             inseg.p->tot_len -= p->len; */
-          p->tot_len = new_tot_len;
-          p->len = 0;
-          p = p->next;
-        }
-        pbuf_header(p, -off);
-      } else {
-        pbuf_header(inseg.p, -off);
-      }
-      /* KJM following line changed to use p->payload rather than inseg->p->payload
-         to fix bug #9076 */
-      inseg.dataptr = p->payload;
-      inseg.len -= pcb->rcv_nxt - seqno;
-      inseg.tcphdr->seqno = seqno = pcb->rcv_nxt;
-    }
-    else{
-      if(TCP_SEQ_LT(seqno, pcb->rcv_nxt)){
-        /* the whole segment is < rcv_nxt */
-        /* must be a duplicate of a packet that has already been correctly handled */
-        
-        LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: duplicate seqno %"U32_F"\n", seqno));
-        tcp_ack_now(pcb);
-      }
-    }
-
-    /* The sequence number must be within the window (above rcv_nxt
-       and below rcv_nxt + rcv_wnd) in order to be further
-       processed. */
-    /*if (TCP_SEQ_GEQ(seqno, pcb->rcv_nxt) &&
-      TCP_SEQ_LT(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {*/
-    if(TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd - 1)){
-      if (pcb->rcv_nxt == seqno) {
-        /* The incoming segment is the next in sequence. We check if
-           we have to trim the end of the segment and update rcv_nxt
-           and pass the data to the application. */
-#if TCP_QUEUE_OOSEQ
-        if (pcb->ooseq != NULL &&
-            TCP_SEQ_LEQ(pcb->ooseq->tcphdr->seqno, seqno + inseg.len)) {
-          /* We have to trim the second edge of the incoming
-             segment. */
-          inseg.len = pcb->ooseq->tcphdr->seqno - seqno;
-          pbuf_realloc(inseg.p, inseg.len);
-        }
-#endif /* TCP_QUEUE_OOSEQ */
-
-        tcplen = TCP_TCPLEN(&inseg);
-
-        /* First received FIN will be ACKed +1, on any successive (duplicate)
-         * FINs we are already in CLOSE_WAIT and have already done +1.
-         */
-        if (pcb->state != CLOSE_WAIT) {
-          pcb->rcv_nxt += tcplen;
-        }
-
-        /* Update the receiver's (our) window. */
-        if (pcb->rcv_wnd < tcplen) {
-          pcb->rcv_wnd = 0;
-        } else {
-          pcb->rcv_wnd -= tcplen;
-        }
-
-        /* If there is data in the segment, we make preparations to
-           pass this up to the application. The ->recv_data variable
-           is used for holding the pbuf that goes to the
-           application. The code for reassembling out-of-sequence data
-           chains its data on this pbuf as well.
-
-           If the segment was a FIN, we set the TF_GOT_FIN flag that will
-           be used to indicate to the application that the remote side has
-           closed its end of the connection. */
-        if (inseg.p->tot_len > 0) {
-          recv_data = inseg.p;
-          /* Since this pbuf now is the responsibility of the
-             application, we delete our reference to it so that we won't
-             (mistakingly) deallocate it. */
-          inseg.p = NULL;
-        }
-        if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) {
-          LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: received FIN.\n"));
-          recv_flags = TF_GOT_FIN;
-        }
-
-#if TCP_QUEUE_OOSEQ
-        /* We now check if we have segments on the ->ooseq queue that
-           is now in sequence. */
-        while (pcb->ooseq != NULL &&
-               pcb->ooseq->tcphdr->seqno == pcb->rcv_nxt) {
-
-          cseg = pcb->ooseq;
-          seqno = pcb->ooseq->tcphdr->seqno;
-
-          pcb->rcv_nxt += TCP_TCPLEN(cseg);
-          if (pcb->rcv_wnd < TCP_TCPLEN(cseg)) {
-            pcb->rcv_wnd = 0;
-          } else {
-            pcb->rcv_wnd -= TCP_TCPLEN(cseg);
-          }
-          if (cseg->p->tot_len > 0) {
-            /* Chain this pbuf onto the pbuf that we will pass to
-               the application. */
-            if (recv_data) {
-              pbuf_cat(recv_data, cseg->p);
-            } else {
-              recv_data = cseg->p;
-            }
-            cseg->p = NULL;
-          }
-          if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) {
-            LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: dequeued FIN.\n"));
-            recv_flags = TF_GOT_FIN;
-          }
-
-
-          pcb->ooseq = cseg->next;
-          tcp_seg_free(cseg);
-        }
-#endif /* TCP_QUEUE_OOSEQ */
-
-
-        /* Acknowledge the segment(s). */
-        tcp_ack(pcb);
-
-      } else {
-        /* We get here if the incoming segment is out-of-sequence. */
-        tcp_ack_now(pcb);
-#if TCP_QUEUE_OOSEQ
-        /* We queue the segment on the ->ooseq queue. */
-        if (pcb->ooseq == NULL) {
-          pcb->ooseq = tcp_seg_copy(&inseg);
-        } else {
-          /* If the queue is not empty, we walk through the queue and
-             try to find a place where the sequence number of the
-             incoming segment is between the sequence numbers of the
-             previous and the next segment on the ->ooseq queue. That is
-             the place where we put the incoming segment. If needed, we
-             trim the second edges of the previous and the incoming
-             segment so that it will fit into the sequence.
-
-             If the incoming segment has the same sequence number as a
-             segment on the ->ooseq queue, we discard the segment that
-             contains less data. */
-
-          prev = NULL;
-          for(next = pcb->ooseq; next != NULL; next = next->next) {
-            if (seqno == next->tcphdr->seqno) {
-              /* The sequence number of the incoming segment is the
-                 same as the sequence number of the segment on
-                 ->ooseq. We check the lengths to see which one to
-                 discard. */
-              if (inseg.len > next->len) {
-                /* The incoming segment is larger than the old
-                   segment. We replace the old segment with the new
-                   one. */
-                cseg = tcp_seg_copy(&inseg);
-                if (cseg != NULL) {
-                  cseg->next = next->next;
-                  if (prev != NULL) {
-                    prev->next = cseg;
-                  } else {
-                    pcb->ooseq = cseg;
-                  }
-                }
-                break;
-              } else {
-                /* Either the lenghts are the same or the incoming
-                   segment was smaller than the old one; in either
-                   case, we ditch the incoming segment. */
-                break;
-              }
-            } else {
-              if (prev == NULL) {
-                if (TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {
-                  /* The sequence number of the incoming segment is lower
-                     than the sequence number of the first segment on the
-                     queue. We put the incoming segment first on the
-                     queue. */
-
-                  if (TCP_SEQ_GT(seqno + inseg.len, next->tcphdr->seqno)) {
-                    /* We need to trim the incoming segment. */
-                    inseg.len = next->tcphdr->seqno - seqno;
-                    pbuf_realloc(inseg.p, inseg.len);
-                  }
-                  cseg = tcp_seg_copy(&inseg);
-                  if (cseg != NULL) {
-                    cseg->next = next;
-                    pcb->ooseq = cseg;
-                  }
-                  break;
-                }
-              } else 
-                /*if (TCP_SEQ_LT(prev->tcphdr->seqno, seqno) &&
-                  TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {*/
-                if(TCP_SEQ_BETWEEN(seqno, prev->tcphdr->seqno+1, next->tcphdr->seqno-1)){
-                /* The sequence number of the incoming segment is in
-                   between the sequence numbers of the previous and
-                   the next segment on ->ooseq. We trim and insert the
-                   incoming segment and trim the previous segment, if
-                   needed. */
-                if (TCP_SEQ_GT(seqno + inseg.len, next->tcphdr->seqno)) {
-                  /* We need to trim the incoming segment. */
-                  inseg.len = next->tcphdr->seqno - seqno;
-                  pbuf_realloc(inseg.p, inseg.len);
-                }
-
-                cseg = tcp_seg_copy(&inseg);
-                if (cseg != NULL) {
-                  cseg->next = next;
-                  prev->next = cseg;
-                  if (TCP_SEQ_GT(prev->tcphdr->seqno + prev->len, seqno)) {
-                    /* We need to trim the prev segment. */
-                    prev->len = seqno - prev->tcphdr->seqno;
-                    pbuf_realloc(prev->p, prev->len);
-                  }
-                }
-                break;
-              }
-              /* If the "next" segment is the last segment on the
-                 ooseq queue, we add the incoming segment to the end
-                 of the list. */
-              if (next->next == NULL &&
-                  TCP_SEQ_GT(seqno, next->tcphdr->seqno)) {
-                next->next = tcp_seg_copy(&inseg);
-                if (next->next != NULL) {
-                  if (TCP_SEQ_GT(next->tcphdr->seqno + next->len, seqno)) {
-                    /* We need to trim the last segment. */
-                    next->len = seqno - next->tcphdr->seqno;
-                    pbuf_realloc(next->p, next->len);
-                  }
-                }
-                break;
-              }
-            }
-            prev = next;
-          }
-        }
-#endif /* TCP_QUEUE_OOSEQ */
-
-      }
-    } else {
-      /*if (TCP_SEQ_GT(pcb->rcv_nxt, seqno) ||
-        TCP_SEQ_GEQ(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {*/
-      if(!TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd-1)){
-        tcp_ack_now(pcb);
-      }
-    }
-  } else {
-    /* Segments with length 0 is taken care of here. Segments that
-       fall out of the window are ACKed. */
-    /*if (TCP_SEQ_GT(pcb->rcv_nxt, seqno) ||
-      TCP_SEQ_GEQ(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {*/
-    if(!TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd-1)){
-      tcp_ack_now(pcb);
-    }
-  }
-}
-
-/*
- * tcp_parseopt:
- *
- * Parses the options contained in the incoming segment. (Code taken
- * from uIP with only small changes.)
- *
- */
-
-static void
-tcp_parseopt(struct tcp_pcb *pcb)
-{
-  u8_t c;
-  u8_t *opts, opt;
-  u16_t mss;
-
-  opts = (u8_t *)tcphdr + TCP_HLEN;
-
-  /* Parse the TCP MSS option, if present. */
-  if(TCPH_HDRLEN(tcphdr) > 0x5) {
-    for(c = 0; c < (TCPH_HDRLEN(tcphdr) - 5) << 2 ;) {
-      opt = opts[c];
-      if (opt == 0x00) {
-        /* End of options. */
-  break;
-      } else if (opt == 0x01) {
-        ++c;
-        /* NOP option. */
-      } else if (opt == 0x02 &&
-        opts[c + 1] == 0x04) {
-        /* An MSS option with the right option length. */
-        mss = (opts[c + 2] << 8) | opts[c + 3];
-        pcb->mss = mss > TCP_MSS? TCP_MSS: mss;
-
-        /* And we are done processing options. */
-        break;
-      } else {
-  if (opts[c + 1] == 0) {
-          /* If the length field is zero, the options are malformed
-             and we don't process them further. */
-          break;
-        }
-        /* All other options have a length field, so that we easily
-           can skip past them. */
-        c += opts[c + 1];
-      }
-    }
-  }
-}
-#endif /* LWIP_TCP */
-
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/core/tcp_out.c b/Demo/lwIP_MCF5235_GCC/lwip/src/core/tcp_out.c
deleted file mode 100644
index 62982bd14..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/core/tcp_out.c
+++ /dev/null
@@ -1,721 +0,0 @@
-/**
- * @file
- *
- * Transmission Control Protocol, outgoing traffic
- *
- * The output functions of TCP.
- *
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels 
- *
- */
-
-#include 
-
-#include "lwip/def.h"
-#include "lwip/opt.h"
-#include "lwip/mem.h"
-#include "lwip/memp.h"
-#include "lwip/sys.h"
-#include "lwip/ip_addr.h"
-#include "lwip/netif.h"
-#include "lwip/inet.h"
-#include "lwip/tcp.h"
-#include "lwip/stats.h"
-
-#if LWIP_TCP
-
-/* Forward declarations.*/
-static void tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb);
-
-err_t
-tcp_send_ctrl(struct tcp_pcb *pcb, u8_t flags)
-{
-  /* no data, no length, flags, copy=1, no optdata, no optdatalen */
-  return tcp_enqueue(pcb, NULL, 0, flags, 1, NULL, 0);
-}
-
-/**
- * Write data for sending (but does not send it immediately).
- *
- * It waits in the expectation of more data being sent soon (as
- * it can send them more efficiently by combining them together).
- * To prompt the system to send data now, call tcp_output() after
- * calling tcp_write().
- * 
- * @arg pcb Protocol control block of the TCP connection to enqueue data for. 
- * 
- * @see tcp_write()
- */
-
-err_t
-tcp_write(struct tcp_pcb *pcb, const void *arg, u16_t len, u8_t copy)
-{
-  LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_write(pcb=%p, arg=%p, len=%"U16_F", copy=%"U16_F")\n", (void *)pcb,
-    arg, len, (u16_t)copy));
-  /* connection is in valid state for data transmission? */
-  if (pcb->state == ESTABLISHED ||
-     pcb->state == CLOSE_WAIT ||
-     pcb->state == SYN_SENT ||
-     pcb->state == SYN_RCVD) {
-    if (len > 0) {
-      return tcp_enqueue(pcb, (void *)arg, len, 0, copy, NULL, 0);
-    }
-    return ERR_OK;
-  } else {
-    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | DBG_STATE | 3, ("tcp_write() called in invalid state\n"));
-    return ERR_CONN;
-  }
-}
-
-/**
- * Enqueue either data or TCP options (but not both) for tranmission
- * 
- * 
- * 
- * @arg pcb Protocol control block for the TCP connection to enqueue data for.
- * @arg arg Pointer to the data to be enqueued for sending.
- * @arg len Data length in bytes
- * @arg flags
- * @arg copy 1 if data must be copied, 0 if data is non-volatile and can be
- * referenced.
- * @arg optdata
- * @arg optlen
- */
-err_t
-tcp_enqueue(struct tcp_pcb *pcb, void *arg, u16_t len,
-  u8_t flags, u8_t copy,
-  u8_t *optdata, u8_t optlen)
-{
-  struct pbuf *p;
-  struct tcp_seg *seg, *useg, *queue;
-  u32_t left, seqno;
-  u16_t seglen;
-  void *ptr;
-  u8_t queuelen;
-
-  LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_enqueue(pcb=%p, arg=%p, len=%"U16_F", flags=%"X16_F", copy=%"U16_F")\n",
-    (void *)pcb, arg, len, (u16_t)flags, (u16_t)copy));
-  LWIP_ASSERT("tcp_enqueue: len == 0 || optlen == 0 (programmer violates API)",
-      len == 0 || optlen == 0);
-  LWIP_ASSERT("tcp_enqueue: arg == NULL || optdata == NULL (programmer violates API)",
-      arg == NULL || optdata == NULL);
-  /* fail on too much data */
-  if (len > pcb->snd_buf) {
-    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 3, ("tcp_enqueue: too much data (len=%"U16_F" > snd_buf=%"U16_F")\n", len, pcb->snd_buf));
-    return ERR_MEM;
-  }
-  left = len;
-  ptr = arg;
-
-  /* seqno will be the sequence number of the first segment enqueued
-   * by the call to this function. */
-  seqno = pcb->snd_lbb;
-
-  LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue: queuelen: %"U16_F"\n", (u16_t)pcb->snd_queuelen));
-
-  /* If total number of pbufs on the unsent/unacked queues exceeds the
-   * configured maximum, return an error */
-  queuelen = pcb->snd_queuelen;
-  if (queuelen >= TCP_SND_QUEUELEN) {
-    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 3, ("tcp_enqueue: too long queue %"U16_F" (max %"U16_F")\n", queuelen, TCP_SND_QUEUELEN));
-    TCP_STATS_INC(tcp.memerr);
-    return ERR_MEM;
-  }
-  if (queuelen != 0) {
-    LWIP_ASSERT("tcp_enqueue: pbufs on queue => at least one queue non-empty",
-      pcb->unacked != NULL || pcb->unsent != NULL);
-  } else {
-    LWIP_ASSERT("tcp_enqueue: no pbufs on queue => both queues empty",
-      pcb->unacked == NULL && pcb->unsent == NULL);
-  }
-
-  /* First, break up the data into segments and tuck them together in
-   * the local "queue" variable. */
-  useg = queue = seg = NULL;
-  seglen = 0;
-  while (queue == NULL || left > 0) {
-
-    /* The segment length should be the MSS if the data to be enqueued
-     * is larger than the MSS. */
-    seglen = left > pcb->mss? pcb->mss: left;
-
-    /* Allocate memory for tcp_seg, and fill in fields. */
-    seg = memp_malloc(MEMP_TCP_SEG);
-    if (seg == NULL) {
-      LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: could not allocate memory for tcp_seg\n"));
-      goto memerr;
-    }
-    seg->next = NULL;
-    seg->p = NULL;
-
-    /* first segment of to-be-queued data? */
-    if (queue == NULL) {
-      queue = seg;
-    }
-    /* subsequent segments of to-be-queued data */
-    else {
-      /* Attach the segment to the end of the queued segments */
-      LWIP_ASSERT("useg != NULL", useg != NULL);
-      useg->next = seg;
-    }
-    /* remember last segment of to-be-queued data for next iteration */
-    useg = seg;
-
-    /* If copy is set, memory should be allocated
-     * and data copied into pbuf, otherwise data comes from
-     * ROM or other static memory, and need not be copied. If
-     * optdata is != NULL, we have options instead of data. */
-     
-    /* options? */
-    if (optdata != NULL) {
-      if ((seg->p = pbuf_alloc(PBUF_TRANSPORT, optlen, PBUF_RAM)) == NULL) {
-        goto memerr;
-      }
-      ++queuelen;
-      seg->dataptr = seg->p->payload;
-    }
-    /* copy from volatile memory? */
-    else if (copy) {
-      if ((seg->p = pbuf_alloc(PBUF_TRANSPORT, seglen, PBUF_RAM)) == NULL) {
-        LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue : could not allocate memory for pbuf copy size %"U16_F"\n", seglen));
-        goto memerr;
-      }
-      ++queuelen;
-      if (arg != NULL) {
-        memcpy(seg->p->payload, ptr, seglen);
-      }
-      seg->dataptr = seg->p->payload;
-    }
-    /* do not copy data */
-    else {
-      /* First, allocate a pbuf for holding the data.
-       * since the referenced data is available at least until it is sent out on the
-       * link (as it has to be ACKed by the remote party) we can safely use PBUF_ROM
-       * instead of PBUF_REF here.
-       */
-      if ((p = pbuf_alloc(PBUF_TRANSPORT, seglen, PBUF_ROM)) == NULL) {
-        LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: could not allocate memory for zero-copy pbuf\n"));
-        goto memerr;
-      }
-      ++queuelen;
-      /* reference the non-volatile payload data */
-      p->payload = ptr;
-      seg->dataptr = ptr;
-
-      /* Second, allocate a pbuf for the headers. */
-      if ((seg->p = pbuf_alloc(PBUF_TRANSPORT, 0, PBUF_RAM)) == NULL) {
-        /* If allocation fails, we have to deallocate the data pbuf as
-         * well. */
-        pbuf_free(p);
-        LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: could not allocate memory for header pbuf\n"));
-        goto memerr;
-      }
-      ++queuelen;
-
-      /* Concatenate the headers and data pbufs together. */
-      pbuf_cat(seg->p/*header*/, p/*data*/);
-      p = NULL;
-    }
-
-    /* Now that there are more segments queued, we check again if the
-    length of the queue exceeds the configured maximum. */
-    if (queuelen > TCP_SND_QUEUELEN) {
-      LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: queue too long %"U16_F" (%"U16_F")\n", queuelen, TCP_SND_QUEUELEN));
-      goto memerr;
-    }
-
-    seg->len = seglen;
-
-    /* build TCP header */
-    if (pbuf_header(seg->p, TCP_HLEN)) {
-      LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: no room for TCP header in pbuf.\n"));
-      TCP_STATS_INC(tcp.err);
-      goto memerr;
-    }
-    seg->tcphdr = seg->p->payload;
-    seg->tcphdr->src = htons(pcb->local_port);
-    seg->tcphdr->dest = htons(pcb->remote_port);
-    seg->tcphdr->seqno = htonl(seqno);
-    seg->tcphdr->urgp = 0;
-    TCPH_FLAGS_SET(seg->tcphdr, flags);
-    /* don't fill in tcphdr->ackno and tcphdr->wnd until later */
-
-    /* Copy the options into the header, if they are present. */
-    if (optdata == NULL) {
-      TCPH_HDRLEN_SET(seg->tcphdr, 5);
-    }
-    else {
-      TCPH_HDRLEN_SET(seg->tcphdr, (5 + optlen / 4));
-      /* Copy options into data portion of segment.
-       Options can thus only be sent in non data carrying
-       segments such as SYN|ACK. */
-      memcpy(seg->dataptr, optdata, optlen);
-    }
-    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | DBG_TRACE, ("tcp_enqueue: queueing %"U32_F":%"U32_F" (0x%"X16_F")\n",
-      ntohl(seg->tcphdr->seqno),
-      ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg),
-      (u16_t)flags));
-
-    left -= seglen;
-    seqno += seglen;
-    ptr = (void *)((u8_t *)ptr + seglen);
-  }
-
-  /* Now that the data to be enqueued has been broken up into TCP
-  segments in the queue variable, we add them to the end of the
-  pcb->unsent queue. */
-  if (pcb->unsent == NULL) {
-    useg = NULL;
-  }
-  else {
-    for (useg = pcb->unsent; useg->next != NULL; useg = useg->next);
-  }
-  /* { useg is last segment on the unsent queue, NULL if list is empty } */
-
-  /* If there is room in the last pbuf on the unsent queue,
-  chain the first pbuf on the queue together with that. */
-  if (useg != NULL &&
-    TCP_TCPLEN(useg) != 0 &&
-    !(TCPH_FLAGS(useg->tcphdr) & (TCP_SYN | TCP_FIN)) &&
-    !(flags & (TCP_SYN | TCP_FIN)) &&
-    /* fit within max seg size */
-    useg->len + queue->len <= pcb->mss) {
-    /* Remove TCP header from first segment of our to-be-queued list */
-    pbuf_header(queue->p, -TCP_HLEN);
-    pbuf_cat(useg->p, queue->p);
-    useg->len += queue->len;
-    useg->next = queue->next;
-
-    LWIP_DEBUGF(TCP_OUTPUT_DEBUG | DBG_TRACE | DBG_STATE, ("tcp_enqueue: chaining segments, new len %"U16_F"\n", useg->len));
-    if (seg == queue) {
-      seg = NULL;
-    }
-    memp_free(MEMP_TCP_SEG, queue);
-  }
-  else {
-    /* empty list */
-    if (useg == NULL) {
-      /* initialize list with this segment */
-      pcb->unsent = queue;
-    }
-    /* enqueue segment */
-    else {
-      useg->next = queue;
-    }
-  }
-  if ((flags & TCP_SYN) || (flags & TCP_FIN)) {
-    ++len;
-  }
-  pcb->snd_lbb += len;
-
-  pcb->snd_buf -= len;
-
-  /* update number of segments on the queues */
-  pcb->snd_queuelen = queuelen;
-  LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue: %"S16_F" (after enqueued)\n", pcb->snd_queuelen));
-  if (pcb->snd_queuelen != 0) {
-    LWIP_ASSERT("tcp_enqueue: valid queue length",
-      pcb->unacked != NULL || pcb->unsent != NULL);
-  }
-
-  /* Set the PSH flag in the last segment that we enqueued, but only
-  if the segment has data (indicated by seglen > 0). */
-  if (seg != NULL && seglen > 0 && seg->tcphdr != NULL) {
-    TCPH_SET_FLAG(seg->tcphdr, TCP_PSH);
-  }
-
-  return ERR_OK;
-memerr:
-  TCP_STATS_INC(tcp.memerr);
-
-  if (queue != NULL) {
-    tcp_segs_free(queue);
-  }
-  if (pcb->snd_queuelen != 0) {
-    LWIP_ASSERT("tcp_enqueue: valid queue length", pcb->unacked != NULL ||
-      pcb->unsent != NULL);
-  }
-  LWIP_DEBUGF(TCP_QLEN_DEBUG | DBG_STATE, ("tcp_enqueue: %"S16_F" (with mem err)\n", pcb->snd_queuelen));
-  return ERR_MEM;
-}
-
-/* find out what we can send and send it */
-err_t
-tcp_output(struct tcp_pcb *pcb)
-{
-  struct pbuf *p;
-  struct tcp_hdr *tcphdr;
-  struct tcp_seg *seg, *useg;
-  u32_t wnd;
-#if TCP_CWND_DEBUG
-  s16_t i = 0;
-#endif /* TCP_CWND_DEBUG */
-
-  /* First, check if we are invoked by the TCP input processing
-     code. If so, we do not output anything. Instead, we rely on the
-     input processing code to call us when input processing is done
-     with. */
-  if (tcp_input_pcb == pcb) {
-    return ERR_OK;
-  }
-
-  wnd = LWIP_MIN(pcb->snd_wnd, pcb->cwnd);
-
-  seg = pcb->unsent;
-
-  /* useg should point to last segment on unacked queue */
-  useg = pcb->unacked;
-  if (useg != NULL) {
-    for (; useg->next != NULL; useg = useg->next);
-  }                                                                             
-   
-  /* If the TF_ACK_NOW flag is set and no data will be sent (either
-   * because the ->unsent queue is empty or because the window does
-   * not allow it), construct an empty ACK segment and send it.
-   *
-   * If data is to be sent, we will just piggyback the ACK (see below).
-   */
-  if (pcb->flags & TF_ACK_NOW &&
-     (seg == NULL ||
-      ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len > wnd)) {
-    p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM);
-    if (p == NULL) {
-      LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: (ACK) could not allocate pbuf\n"));
-      return ERR_BUF;
-    }
-    LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: sending ACK for %"U32_F"\n", pcb->rcv_nxt));
-    /* remove ACK flags from the PCB, as we send an empty ACK now */
-    pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW);
-
-    tcphdr = p->payload;
-    tcphdr->src = htons(pcb->local_port);
-    tcphdr->dest = htons(pcb->remote_port);
-    tcphdr->seqno = htonl(pcb->snd_nxt);
-    tcphdr->ackno = htonl(pcb->rcv_nxt);
-    TCPH_FLAGS_SET(tcphdr, TCP_ACK);
-    tcphdr->wnd = htons(pcb->rcv_wnd);
-    tcphdr->urgp = 0;
-    TCPH_HDRLEN_SET(tcphdr, 5);
-
-    tcphdr->chksum = 0;
-#if CHECKSUM_GEN_TCP
-    tcphdr->chksum = inet_chksum_pseudo(p, &(pcb->local_ip), &(pcb->remote_ip),
-          IP_PROTO_TCP, p->tot_len);
-#endif
-    ip_output(p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl, pcb->tos,
-        IP_PROTO_TCP);
-    pbuf_free(p);
-
-    return ERR_OK;
-  }
-
-#if TCP_OUTPUT_DEBUG
-  if (seg == NULL) {
-    LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: nothing to send (%p)\n", (void*)pcb->unsent));
-  }
-#endif /* TCP_OUTPUT_DEBUG */
-#if TCP_CWND_DEBUG
-  if (seg == NULL) {
-    LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %"U32_F", cwnd %"U16_F", wnd %"U32_F", seg == NULL, ack %"U32_F"\n",
-                            pcb->snd_wnd, pcb->cwnd, wnd,
-                            pcb->lastack));
-  } else {
-    LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %"U32_F", cwnd %"U16_F", wnd %"U32_F", effwnd %"U32_F", seq %"U32_F", ack %"U32_F"\n",
-                            pcb->snd_wnd, pcb->cwnd, wnd,
-                            ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len,
-                            ntohl(seg->tcphdr->seqno), pcb->lastack));
-  }
-#endif /* TCP_CWND_DEBUG */
-  /* data available and window allows it to be sent? */
-  while (seg != NULL &&
-  ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len <= wnd) {
-#if TCP_CWND_DEBUG
-    LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %"U32_F", cwnd %"U16_F", wnd %"U32_F", effwnd %"U32_F", seq %"U32_F", ack %"U32_F", i %"S16_F"\n",
-                            pcb->snd_wnd, pcb->cwnd, wnd,
-                            ntohl(seg->tcphdr->seqno) + seg->len -
-                            pcb->lastack,
-                            ntohl(seg->tcphdr->seqno), pcb->lastack, i));
-    ++i;
-#endif /* TCP_CWND_DEBUG */
-
-    pcb->unsent = seg->next;
-
-    if (pcb->state != SYN_SENT) {
-      TCPH_SET_FLAG(seg->tcphdr, TCP_ACK);
-      pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW);
-    }
-
-    tcp_output_segment(seg, pcb);
-    pcb->snd_nxt = ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg);
-    if (TCP_SEQ_LT(pcb->snd_max, pcb->snd_nxt)) {
-      pcb->snd_max = pcb->snd_nxt;
-    }
-    /* put segment on unacknowledged list if length > 0 */
-    if (TCP_TCPLEN(seg) > 0) {
-      seg->next = NULL;
-      /* unacked list is empty? */
-      if (pcb->unacked == NULL) {
-        pcb->unacked = seg;
-        useg = seg;
-      /* unacked list is not empty? */
-      } else {
-        /* In the case of fast retransmit, the packet should not go to the tail
-         * of the unacked queue, but rather at the head. We need to check for
-         * this case. -STJ Jul 27, 2004 */
-        if (TCP_SEQ_LT(ntohl(seg->tcphdr->seqno), ntohl(useg->tcphdr->seqno))){
-          /* add segment to head of unacked list */
-          seg->next = pcb->unacked;
-          pcb->unacked = seg;
-        } else {
-          /* add segment to tail of unacked list */
-          useg->next = seg;
-          useg = useg->next;
-        }
-      }
-    /* do not queue empty segments on the unacked list */
-    } else {
-      tcp_seg_free(seg);
-    }
-    seg = pcb->unsent;
-  }
-  return ERR_OK;
-}
-
-/**
- * Actually send a TCP segment over IP
- */
-static void
-tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb)
-{
-  u16_t len;
-  struct netif *netif;
-
-  /* The TCP header has already been constructed, but the ackno and
-   wnd fields remain. */
-  seg->tcphdr->ackno = htonl(pcb->rcv_nxt);
-
-  /* silly window avoidance */
-  if (pcb->rcv_wnd < pcb->mss) {
-    seg->tcphdr->wnd = 0;
-  } else {
-    /* advertise our receive window size in this TCP segment */
-    seg->tcphdr->wnd = htons(pcb->rcv_wnd);
-  }
-
-  /* If we don't have a local IP address, we get one by
-     calling ip_route(). */
-  if (ip_addr_isany(&(pcb->local_ip))) {
-    netif = ip_route(&(pcb->remote_ip));
-    if (netif == NULL) {
-      return;
-    }
-    ip_addr_set(&(pcb->local_ip), &(netif->ip_addr));
-  }
-
-  pcb->rtime = 0;
-
-  if (pcb->rttest == 0) {
-    pcb->rttest = tcp_ticks;
-    pcb->rtseq = ntohl(seg->tcphdr->seqno);
-
-    LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_output_segment: rtseq %"U32_F"\n", pcb->rtseq));
-  }
-  LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output_segment: %"U32_F":%"U32_F"\n",
-          htonl(seg->tcphdr->seqno), htonl(seg->tcphdr->seqno) +
-          seg->len));
-
-  len = (u16_t)((u8_t *)seg->tcphdr - (u8_t *)seg->p->payload);
-
-  seg->p->len -= len;
-  seg->p->tot_len -= len;
-
-  seg->p->payload = seg->tcphdr;
-
-  seg->tcphdr->chksum = 0;
-#if CHECKSUM_GEN_TCP
-  seg->tcphdr->chksum = inet_chksum_pseudo(seg->p,
-             &(pcb->local_ip),
-             &(pcb->remote_ip),
-             IP_PROTO_TCP, seg->p->tot_len);
-#endif
-  TCP_STATS_INC(tcp.xmit);
-
-  ip_output(seg->p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl, pcb->tos,
-      IP_PROTO_TCP);
-}
-
-void
-tcp_rst(u32_t seqno, u32_t ackno,
-  struct ip_addr *local_ip, struct ip_addr *remote_ip,
-  u16_t local_port, u16_t remote_port)
-{
-  struct pbuf *p;
-  struct tcp_hdr *tcphdr;
-  p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM);
-  if (p == NULL) {
-      LWIP_DEBUGF(TCP_DEBUG, ("tcp_rst: could not allocate memory for pbuf\n"));
-      return;
-  }
-
-  tcphdr = p->payload;
-  tcphdr->src = htons(local_port);
-  tcphdr->dest = htons(remote_port);
-  tcphdr->seqno = htonl(seqno);
-  tcphdr->ackno = htonl(ackno);
-  TCPH_FLAGS_SET(tcphdr, TCP_RST | TCP_ACK);
-  tcphdr->wnd = htons(TCP_WND);
-  tcphdr->urgp = 0;
-  TCPH_HDRLEN_SET(tcphdr, 5);
-
-  tcphdr->chksum = 0;
-#if CHECKSUM_GEN_TCP
-  tcphdr->chksum = inet_chksum_pseudo(p, local_ip, remote_ip,
-              IP_PROTO_TCP, p->tot_len);
-#endif
-  TCP_STATS_INC(tcp.xmit);
-   /* Send output with hardcoded TTL since we have no access to the pcb */
-  ip_output(p, local_ip, remote_ip, TCP_TTL, 0, IP_PROTO_TCP);
-  pbuf_free(p);
-  LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_rst: seqno %"U32_F" ackno %"U32_F".\n", seqno, ackno));
-}
-
-/* requeue all unacked segments for retransmission */
-void
-tcp_rexmit_rto(struct tcp_pcb *pcb)
-{
-  struct tcp_seg *seg;
-
-  if (pcb->unacked == NULL) {
-    return;
-  }
-
-  /* Move all unacked segments to the head of the unsent queue */
-  for (seg = pcb->unacked; seg->next != NULL; seg = seg->next);
-  /* concatenate unsent queue after unacked queue */
-  seg->next = pcb->unsent;
-  /* unsent queue is the concatenated queue (of unacked, unsent) */
-  pcb->unsent = pcb->unacked;
-  /* unacked queue is now empty */
-  pcb->unacked = NULL;
-
-  pcb->snd_nxt = ntohl(pcb->unsent->tcphdr->seqno);
-  /* increment number of retransmissions */
-  ++pcb->nrtx;
-
-  /* Don't take any RTT measurements after retransmitting. */
-  pcb->rttest = 0;
-
-  /* Do the actual retransmission */
-  tcp_output(pcb);
-}
-
-void
-tcp_rexmit(struct tcp_pcb *pcb)
-{
-  struct tcp_seg *seg;
-
-  if (pcb->unacked == NULL) {
-    return;
-  }
-
-  /* Move the first unacked segment to the unsent queue */
-  seg = pcb->unacked->next;
-  pcb->unacked->next = pcb->unsent;
-  pcb->unsent = pcb->unacked;
-  pcb->unacked = seg;
-
-  pcb->snd_nxt = ntohl(pcb->unsent->tcphdr->seqno);
-
-  ++pcb->nrtx;
-
-  /* Don't take any rtt measurements after retransmitting. */
-  pcb->rttest = 0;
-
-  /* Do the actual retransmission. */
-  tcp_output(pcb);
-
-}
-
-
-void
-tcp_keepalive(struct tcp_pcb *pcb)
-{
-   struct pbuf *p;
-   struct tcp_hdr *tcphdr;
-
-   LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: sending KEEPALIVE probe to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
-                           ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip),
-                           ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip)));
-
-   LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: tcp_ticks %"U32_F"   pcb->tmr %"U32_F"  pcb->keep_cnt %"U16_F"\n", tcp_ticks, pcb->tmr, pcb->keep_cnt));
-   
-   p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM);
-
-   if(p == NULL) {
-      LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: could not allocate memory for pbuf\n"));
-      return;
-   }
-
-   tcphdr = p->payload;
-   tcphdr->src = htons(pcb->local_port);
-   tcphdr->dest = htons(pcb->remote_port);
-   tcphdr->seqno = htonl(pcb->snd_nxt - 1);
-   tcphdr->ackno = htonl(pcb->rcv_nxt);
-   tcphdr->wnd = htons(pcb->rcv_wnd);
-   tcphdr->urgp = 0;
-   TCPH_HDRLEN_SET(tcphdr, 5);
-   
-   tcphdr->chksum = 0;
-#if CHECKSUM_GEN_TCP
-   tcphdr->chksum = inet_chksum_pseudo(p, &pcb->local_ip, &pcb->remote_ip, IP_PROTO_TCP, p->tot_len);
-#endif
-  TCP_STATS_INC(tcp.xmit);
-
-   /* Send output to IP */
-  ip_output(p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl, 0, IP_PROTO_TCP);
-
-  pbuf_free(p);
-
-  LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_keepalive: seqno %"U32_F" ackno %"U32_F".\n", pcb->snd_nxt - 1, pcb->rcv_nxt));
-}
-
-#endif /* LWIP_TCP */
-
-
-
-
-
-
-
-
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/core/udp.c b/Demo/lwIP_MCF5235_GCC/lwip/src/core/udp.c
deleted file mode 100644
index d1e0eacac..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/core/udp.c
+++ /dev/null
@@ -1,655 +0,0 @@
-/**
- * @file
- * User Datagram Protocol module
- *
- */
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels 
- *
- */
-
-
-/* udp.c
- *
- * The code for the User Datagram Protocol UDP.
- *
- */
-
-#include 
-
-#include "lwip/opt.h"
-
-#include "lwip/def.h"
-#include "lwip/memp.h"
-#include "lwip/inet.h"
-#include "lwip/ip_addr.h"
-#include "lwip/netif.h"
-#include "lwip/udp.h"
-#include "lwip/icmp.h"
-
-#include "lwip/stats.h"
-
-#include "arch/perf.h"
-#include "lwip/snmp.h"
-
-/* The list of UDP PCBs */
-#if LWIP_UDP
-/* was static, but we may want to access this from a socket layer */
-struct udp_pcb *udp_pcbs = NULL;
-
-static struct udp_pcb *pcb_cache = NULL;
-
-void
-udp_init(void)
-{
-  udp_pcbs = pcb_cache = NULL;
-}
-
-/**
- * Process an incoming UDP datagram.
- *
- * Given an incoming UDP datagram (as a chain of pbufs) this function
- * finds a corresponding UDP PCB and
- *
- * @param pbuf pbuf to be demultiplexed to a UDP PCB.
- * @param netif network interface on which the datagram was received.
- *
- */
-void
-udp_input(struct pbuf *p, struct netif *inp)
-{
-  struct udp_hdr *udphdr;
-  struct udp_pcb *pcb;
-  struct udp_pcb *uncon_pcb;
-  struct ip_hdr *iphdr;
-  u16_t src, dest;
-  u8_t local_match;
-
-  PERF_START;
-
-  UDP_STATS_INC(udp.recv);
-
-  iphdr = p->payload;
-
-  if (pbuf_header(p, -((s16_t)(UDP_HLEN + IPH_HL(iphdr) * 4)))) {
-    /* drop short packets */
-    LWIP_DEBUGF(UDP_DEBUG, ("udp_input: short UDP datagram (%"U16_F" bytes) discarded\n", p->tot_len));
-    UDP_STATS_INC(udp.lenerr);
-    UDP_STATS_INC(udp.drop);
-    snmp_inc_udpinerrors();
-    pbuf_free(p);
-    goto end;
-  }
-
-  udphdr = (struct udp_hdr *)((u8_t *)p->payload - UDP_HLEN);
-
-  LWIP_DEBUGF(UDP_DEBUG, ("udp_input: received datagram of length %"U16_F"\n", p->tot_len));
-
-  src = ntohs(udphdr->src);
-  dest = ntohs(udphdr->dest);
-
-  udp_debug_print(udphdr);
-
-  /* print the UDP source and destination */
-  LWIP_DEBUGF(UDP_DEBUG, ("udp (%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F") <-- (%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F")\n",
-    ip4_addr1(&iphdr->dest), ip4_addr2(&iphdr->dest),
-    ip4_addr3(&iphdr->dest), ip4_addr4(&iphdr->dest), ntohs(udphdr->dest),
-    ip4_addr1(&iphdr->src), ip4_addr2(&iphdr->src),
-    ip4_addr3(&iphdr->src), ip4_addr4(&iphdr->src), ntohs(udphdr->src)));
-
-  local_match = 0;
-  uncon_pcb = NULL;
-  /* Iterate through the UDP pcb list for a matching pcb */
-  for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) {
-    /* print the PCB local and remote address */
-    LWIP_DEBUGF(UDP_DEBUG, ("pcb (%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F") --- (%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F")\n",
-      ip4_addr1(&pcb->local_ip), ip4_addr2(&pcb->local_ip),
-      ip4_addr3(&pcb->local_ip), ip4_addr4(&pcb->local_ip), pcb->local_port,
-      ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip),
-      ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip), pcb->remote_port));
-
-    /* compare PCB local addr+port to UDP destination addr+port */
-    if ((pcb->local_port == dest) &&
-       (ip_addr_isany(&pcb->local_ip) ||
-        ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest)))) {
-       local_match = 1;
-       if ((uncon_pcb == NULL) && 
-           ((pcb->flags & UDP_FLAGS_CONNECTED) == 0)) {
-         /* the first unconnected matching PCB */     
-         uncon_pcb = pcb;
-       }
-    }
-    /* compare PCB remote addr+port to UDP source addr+port */
-    if ((local_match != 0) &&
-       (pcb->remote_port == src) &&
-       (ip_addr_isany(&pcb->remote_ip) ||
-       ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src)))) {
-       /* the first fully matching PCB */
-      break;
-    }
-  }
-  /* no fully matching pcb found? then look for an unconnected pcb */
-  if (pcb == NULL) {
-    pcb = uncon_pcb;
-  }
-
-  /* Check checksum if this is a match or if it was directed at us. */
-  if (pcb != NULL  || ip_addr_cmp(&inp->ip_addr, &iphdr->dest))
-    {
-    LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE, ("udp_input: calculating checksum\n"));
-    pbuf_header(p, UDP_HLEN);
-#ifdef IPv6
-    if (iphdr->nexthdr == IP_PROTO_UDPLITE) {
-#else
-    if (IPH_PROTO(iphdr) == IP_PROTO_UDPLITE) {
-#endif /* IPv4 */
-      /* Do the UDP Lite checksum */
-#if CHECKSUM_CHECK_UDP
-      if (inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src),
-         (struct ip_addr *)&(iphdr->dest),
-         IP_PROTO_UDPLITE, ntohs(udphdr->len)) != 0) {
-  LWIP_DEBUGF(UDP_DEBUG | 2, ("udp_input: UDP Lite datagram discarded due to failing checksum\n"));
-  UDP_STATS_INC(udp.chkerr);
-  UDP_STATS_INC(udp.drop);
-  snmp_inc_udpinerrors();
-  pbuf_free(p);
-  goto end;
-      }
-#endif
-    } else {
-#if CHECKSUM_CHECK_UDP
-      if (udphdr->chksum != 0) {
-  if (inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src),
-       (struct ip_addr *)&(iphdr->dest),
-        IP_PROTO_UDP, p->tot_len) != 0) {
-    LWIP_DEBUGF(UDP_DEBUG | 2, ("udp_input: UDP datagram discarded due to failing checksum\n"));
-
-    UDP_STATS_INC(udp.chkerr);
-    UDP_STATS_INC(udp.drop);
-    snmp_inc_udpinerrors();
-    pbuf_free(p);
-    goto end;
-  }
-      }
-#endif
-    }
-    pbuf_header(p, -UDP_HLEN);
-    if (pcb != NULL) {
-      snmp_inc_udpindatagrams();
-      /* callback */
-      if (pcb->recv != NULL)
-      {
-        pcb->recv(pcb->recv_arg, pcb, p, &(iphdr->src), src);
-      }
-        } else {
-      LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE, ("udp_input: not for us.\n"));
-
-      /* No match was found, send ICMP destination port unreachable unless
-      destination address was broadcast/multicast. */
-
-      if (!ip_addr_isbroadcast(&iphdr->dest, inp) &&
-          !ip_addr_ismulticast(&iphdr->dest)) {
-
-  /* adjust pbuf pointer */
-  p->payload = iphdr;
-  icmp_dest_unreach(p, ICMP_DUR_PORT);
-      }
-      UDP_STATS_INC(udp.proterr);
-      UDP_STATS_INC(udp.drop);
-    snmp_inc_udpnoports();
-      pbuf_free(p);
-    }
-  } else {
-    pbuf_free(p);
-  }
-  end:
-
-  PERF_STOP("udp_input");
-}
-
-/**
- * Send data to a specified address using UDP.
- *
- * @param pcb UDP PCB used to send the data.
- * @param pbuf chain of pbuf's to be sent.
- * @param dst_ip Destination IP address.
- * @param dst_port Destination UDP port.
- *
- * If the PCB already has a remote address association, it will
- * be restored after the data is sent.
- * 
- * @return lwIP error code.
- * - ERR_OK. Successful. No error occured.
- * - ERR_MEM. Out of memory.
- * - ERR_RTE. Could not find route to destination address.
- *
- * @see udp_disconnect() udp_send()
- */
-err_t
-udp_sendto(struct udp_pcb *pcb, struct pbuf *p,
-  struct ip_addr *dst_ip, u16_t dst_port)
-{
-  err_t err;
-  /* temporary space for current PCB remote address */
-  struct ip_addr pcb_remote_ip;
-  u16_t pcb_remote_port;
-  /* remember current remote peer address of PCB */
-  pcb_remote_ip.addr = pcb->remote_ip.addr;
-  pcb_remote_port = pcb->remote_port;
-  /* copy packet destination address to PCB remote peer address */
-  pcb->remote_ip.addr = dst_ip->addr;
-  pcb->remote_port = dst_port;
-  /* send to the packet destination address */
-  err = udp_send(pcb, p);
-  /* restore PCB remote peer address */
-  pcb->remote_ip.addr = pcb_remote_ip.addr;
-  pcb->remote_port = pcb_remote_port;
-  return err;
-}
-
-/**
- * Send data using UDP.
- *
- * @param pcb UDP PCB used to send the data.
- * @param pbuf chain of pbuf's to be sent.
- *
- * @return lwIP error code.
- * - ERR_OK. Successful. No error occured.
- * - ERR_MEM. Out of memory.
- * - ERR_RTE. Could not find route to destination address.
- *
- * @see udp_disconnect() udp_sendto()
- */
-err_t
-udp_send(struct udp_pcb *pcb, struct pbuf *p)
-{
-  struct udp_hdr *udphdr;
-  struct netif *netif;
-  struct ip_addr *src_ip;
-  err_t err;
-  struct pbuf *q; /* q will be sent down the stack */
-
-  LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 3, ("udp_send\n"));
-
-  /* if the PCB is not yet bound to a port, bind it here */
-  if (pcb->local_port == 0) {
-    LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 2, ("udp_send: not yet bound to a port, binding now\n"));
-    err = udp_bind(pcb, &pcb->local_ip, pcb->local_port);
-    if (err != ERR_OK) {
-      LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 2, ("udp_send: forced port bind failed\n"));
-      return err;
-    }
-  }
-  /* find the outgoing network interface for this packet */
-  netif = ip_route(&(pcb->remote_ip));
-  /* no outgoing network interface could be found? */
-  if (netif == NULL) {
-    LWIP_DEBUGF(UDP_DEBUG | 1, ("udp_send: No route to 0x%"X32_F"\n", pcb->remote_ip.addr));
-    UDP_STATS_INC(udp.rterr);
-    return ERR_RTE;
-  }
-
-  /* not enough space to add an UDP header to first pbuf in given p chain? */
-  if (pbuf_header(p, UDP_HLEN)) {
-    /* allocate header in a seperate new pbuf */
-    q = pbuf_alloc(PBUF_IP, UDP_HLEN, PBUF_RAM);
-    /* new header pbuf could not be allocated? */
-    if (q == NULL) {
-      LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 2, ("udp_send: could not allocate header\n"));
-      return ERR_MEM;
-    }
-    /* chain header q in front of given pbuf p */
-    pbuf_chain(q, p);
-    /* { first pbuf q points to header pbuf } */
-    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p));
-  /* adding a header within p succeeded */
-  } else {
-    /* first pbuf q equals given pbuf */
-    q = p;
-    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: added header in given pbuf %p\n", (void *)p));
-  }
-  /* { q now represents the packet to be sent } */
-  udphdr = q->payload;
-  udphdr->src = htons(pcb->local_port);
-  udphdr->dest = htons(pcb->remote_port);
-  /* in UDP, 0 checksum means 'no checksum' */
-  udphdr->chksum = 0x0000; 
-
-  /* PCB local address is IP_ANY_ADDR? */
-  if (ip_addr_isany(&pcb->local_ip)) {
-    /* use outgoing network interface IP address as source address */
-    src_ip = &(netif->ip_addr);
-  } else {
-    /* use UDP PCB local IP address as source address */
-    src_ip = &(pcb->local_ip);
-  }
-
-  LWIP_DEBUGF(UDP_DEBUG, ("udp_send: sending datagram of length %"U16_F"\n", q->tot_len));
-
-  /* UDP Lite protocol? */
-  if (pcb->flags & UDP_FLAGS_UDPLITE) {
-    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP LITE packet length %"U16_F"\n", q->tot_len));
-    /* set UDP message length in UDP header */
-    udphdr->len = htons(pcb->chksum_len);
-    /* calculate checksum */
-#if CHECKSUM_GEN_UDP
-    udphdr->chksum = inet_chksum_pseudo(q, src_ip, &(pcb->remote_ip),
-          IP_PROTO_UDP, pcb->chksum_len);
-    /* chksum zero must become 0xffff, as zero means 'no checksum' */
-    if (udphdr->chksum == 0x0000) udphdr->chksum = 0xffff;
-#else
-    udphdr->chksum = 0x0000;
-#endif
-    /* output to IP */
-    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: ip_output_if (,,,,IP_PROTO_UDPLITE,)\n"));
-    err = ip_output_if (q, src_ip, &pcb->remote_ip, pcb->ttl, pcb->tos, IP_PROTO_UDPLITE, netif);    
-  /* UDP */
-  } else {
-    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP packet length %"U16_F"\n", q->tot_len));
-    udphdr->len = htons(q->tot_len);
-    /* calculate checksum */
-#if CHECKSUM_GEN_UDP
-    if ((pcb->flags & UDP_FLAGS_NOCHKSUM) == 0) {
-      udphdr->chksum = inet_chksum_pseudo(q, src_ip, &pcb->remote_ip, IP_PROTO_UDP, q->tot_len);
-      /* chksum zero must become 0xffff, as zero means 'no checksum' */
-      if (udphdr->chksum == 0x0000) udphdr->chksum = 0xffff;
-    }
-#else
-    udphdr->chksum = 0x0000;
-#endif
-    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP checksum 0x%04"X16_F"\n", udphdr->chksum));
-    LWIP_DEBUGF(UDP_DEBUG, ("udp_send: ip_output_if (,,,,IP_PROTO_UDP,)\n"));
-    /* output to IP */
-    err = ip_output_if(q, src_ip, &pcb->remote_ip, pcb->ttl, pcb->tos, IP_PROTO_UDP, netif);    
-  }
-  /* TODO: must this be increased even if error occured? */
-  snmp_inc_udpoutdatagrams();
-
-  /* did we chain a seperate header pbuf earlier? */
-  if (q != p) {
-    /* free the header pbuf */
-    pbuf_free(q); q = NULL;
-    /* { p is still referenced by the caller, and will live on } */
-  }
-
-  UDP_STATS_INC(udp.xmit);
-  return err;
-}
-
-/**
- * Bind an UDP PCB.
- *
- * @param pcb UDP PCB to be bound with a local address ipaddr and port.
- * @param ipaddr local IP address to bind with. Use IP_ADDR_ANY to
- * bind to all local interfaces.
- * @param port local UDP port to bind with.
- *
- * @return lwIP error code.
- * - ERR_OK. Successful. No error occured.
- * - ERR_USE. The specified ipaddr and port are already bound to by
- * another UDP PCB.
- *
- * @see udp_disconnect()
- */
-err_t
-udp_bind(struct udp_pcb *pcb, struct ip_addr *ipaddr, u16_t port)
-{
-  struct udp_pcb *ipcb;
-  u8_t rebind;
-
-  LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 3, ("udp_bind(ipaddr = "));
-  ip_addr_debug_print(UDP_DEBUG, ipaddr);
-  LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 3, (", port = %"U16_F")\n", port));
-
-  rebind = 0;
-  /* Check for double bind and rebind of the same pcb */
-  for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
-    /* is this UDP PCB already on active list? */
-    if (pcb == ipcb) {
-      /* pcb may occur at most once in active list */
-      LWIP_ASSERT("rebind == 0", rebind == 0);
-      /* pcb already in list, just rebind */
-      rebind = 1;
-    }
-
-/* this code does not allow upper layer to share a UDP port for
-   listening to broadcast or multicast traffic (See SO_REUSE_ADDR and
-   SO_REUSE_PORT under *BSD). TODO: See where it fits instead, OR
-   combine with implementation of UDP PCB flags. Leon Woestenberg. */
-#ifdef LWIP_UDP_TODO
-    /* port matches that of PCB in list? */
-    else if ((ipcb->local_port == port) &&
-       /* IP address matches, or one is IP_ADDR_ANY? */
-       (ip_addr_isany(&(ipcb->local_ip)) ||
-       ip_addr_isany(ipaddr) ||
-       ip_addr_cmp(&(ipcb->local_ip), ipaddr))) {
-      /* other PCB already binds to this local IP and port */
-      LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: local port %"U16_F" already bound by another pcb\n", port));
-      return ERR_USE;
-    }
-#endif
-
-  }
-
-  ip_addr_set(&pcb->local_ip, ipaddr);
-  /* no port specified? */
-  if (port == 0) {
-#ifndef UDP_LOCAL_PORT_RANGE_START
-#define UDP_LOCAL_PORT_RANGE_START 4096
-#define UDP_LOCAL_PORT_RANGE_END   0x7fff
-#endif
-    port = UDP_LOCAL_PORT_RANGE_START;
-    ipcb = udp_pcbs;
-    while ((ipcb != NULL) && (port != UDP_LOCAL_PORT_RANGE_END)) {
-      if (ipcb->local_port == port) {
-        port++;
-        ipcb = udp_pcbs;
-      } else
-        ipcb = ipcb->next;
-    }
-    if (ipcb != NULL) {
-      /* no more ports available in local range */
-      LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: out of free UDP ports\n"));
-      return ERR_USE;
-    }
-  }
-  pcb->local_port = port;
-  /* pcb not active yet? */
-  if (rebind == 0) {
-    /* place the PCB on the active list if not already there */
-    pcb->next = udp_pcbs;
-    udp_pcbs = pcb;
-  }
-  LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | DBG_STATE, ("udp_bind: bound to %"U16_F".%"U16_F".%"U16_F".%"U16_F", port %"U16_F"\n",
-   (u16_t)(ntohl(pcb->local_ip.addr) >> 24 & 0xff),
-   (u16_t)(ntohl(pcb->local_ip.addr) >> 16 & 0xff),
-   (u16_t)(ntohl(pcb->local_ip.addr) >> 8 & 0xff),
-   (u16_t)(ntohl(pcb->local_ip.addr) & 0xff), pcb->local_port));
-  return ERR_OK;
-}
-/**
- * Connect an UDP PCB.
- *
- * This will associate the UDP PCB with the remote address.
- *
- * @param pcb UDP PCB to be connected with remote address ipaddr and port.
- * @param ipaddr remote IP address to connect with.
- * @param port remote UDP port to connect with.
- *
- * @return lwIP error code
- *
- * @see udp_disconnect()
- */
-err_t
-udp_connect(struct udp_pcb *pcb, struct ip_addr *ipaddr, u16_t port)
-{
-  struct udp_pcb *ipcb;
-
-  if (pcb->local_port == 0) {
-    err_t err = udp_bind(pcb, &pcb->local_ip, pcb->local_port);
-    if (err != ERR_OK)
-      return err;
-  }
-
-  ip_addr_set(&pcb->remote_ip, ipaddr);
-  pcb->remote_port = port;
-  pcb->flags |= UDP_FLAGS_CONNECTED;
-/** TODO: this functionality belongs in upper layers */
-#ifdef LWIP_UDP_TODO
-  /* Nail down local IP for netconn_addr()/getsockname() */
-  if (ip_addr_isany(&pcb->local_ip) && !ip_addr_isany(&pcb->remote_ip)) {
-    struct netif *netif;
-
-    if ((netif = ip_route(&(pcb->remote_ip))) == NULL) {
-      LWIP_DEBUGF(UDP_DEBUG, ("udp_connect: No route to 0x%lx\n", pcb->remote_ip.addr));
-        UDP_STATS_INC(udp.rterr);
-      return ERR_RTE;
-    }
-    /** TODO: this will bind the udp pcb locally, to the interface which
-        is used to route output packets to the remote address. However, we
-        might want to accept incoming packets on any interface! */
-    pcb->local_ip = netif->ip_addr;
-  } else if (ip_addr_isany(&pcb->remote_ip)) {
-    pcb->local_ip.addr = 0;
-  }
-#endif
-  LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | DBG_STATE, ("udp_connect: connected to %"U16_F".%"U16_F".%"U16_F".%"U16_F",port %"U16_F"\n",
-   (u16_t)(ntohl(pcb->remote_ip.addr) >> 24 & 0xff),
-   (u16_t)(ntohl(pcb->remote_ip.addr) >> 16 & 0xff),
-   (u16_t)(ntohl(pcb->remote_ip.addr) >> 8 & 0xff),
-   (u16_t)(ntohl(pcb->remote_ip.addr) & 0xff), pcb->remote_port));
-
-  /* Insert UDP PCB into the list of active UDP PCBs. */
-  for(ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
-    if (pcb == ipcb) {
-      /* already on the list, just return */
-      return ERR_OK;
-    }
-  }
-  /* PCB not yet on the list, add PCB now */
-  pcb->next = udp_pcbs;
-  udp_pcbs = pcb;
-  return ERR_OK;
-}
-
-void
-udp_disconnect(struct udp_pcb *pcb)
-{
-  /* reset remote address association */
-  ip_addr_set(&pcb->remote_ip, IP_ADDR_ANY);
-  pcb->remote_port = 0;
-  /* mark PCB as unconnected */
-  pcb->flags &= ~UDP_FLAGS_CONNECTED;
-}
-
-void
-udp_recv(struct udp_pcb *pcb,
-   void (* recv)(void *arg, struct udp_pcb *upcb, struct pbuf *p,
-           struct ip_addr *addr, u16_t port),
-   void *recv_arg)
-{
-  /* remember recv() callback and user data */
-  pcb->recv = recv;
-  pcb->recv_arg = recv_arg;
-}
-/**
- * Remove an UDP PCB.
- *
- * @param pcb UDP PCB to be removed. The PCB is removed from the list of
- * UDP PCB's and the data structure is freed from memory.
- *
- * @see udp_new()
- */
-void
-udp_remove(struct udp_pcb *pcb)
-{
-  struct udp_pcb *pcb2;
-  /* pcb to be removed is first in list? */
-  if (udp_pcbs == pcb) {
-    /* make list start at 2nd pcb */
-    udp_pcbs = udp_pcbs->next;
-  /* pcb not 1st in list */
-  } else for(pcb2 = udp_pcbs; pcb2 != NULL; pcb2 = pcb2->next) {
-    /* find pcb in udp_pcbs list */
-    if (pcb2->next != NULL && pcb2->next == pcb) {
-      /* remove pcb from list */
-      pcb2->next = pcb->next;
-    }
-  }
-  memp_free(MEMP_UDP_PCB, pcb);
-}
-/**
- * Create a UDP PCB.
- *
- * @return The UDP PCB which was created. NULL if the PCB data structure
- * could not be allocated.
- *
- * @see udp_remove()
- */
-struct udp_pcb *
-udp_new(void) {
-  struct udp_pcb *pcb;
-  pcb = memp_malloc(MEMP_UDP_PCB);
-  /* could allocate UDP PCB? */
-  if (pcb != NULL) {
-    /* initialize PCB to all zeroes */
-    memset(pcb, 0, sizeof(struct udp_pcb));
-    pcb->ttl = UDP_TTL;
-  }
-  
-  
-  return pcb;
-}
-
-#if UDP_DEBUG
-void
-udp_debug_print(struct udp_hdr *udphdr)
-{
-  LWIP_DEBUGF(UDP_DEBUG, ("UDP header:\n"));
-  LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n"));
-  LWIP_DEBUGF(UDP_DEBUG, ("|     %5"U16_F"     |     %5"U16_F"     | (src port, dest port)\n",
-         ntohs(udphdr->src), ntohs(udphdr->dest)));
-  LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n"));
-  LWIP_DEBUGF(UDP_DEBUG, ("|     %5"U16_F"     |     0x%04"X16_F"    | (len, chksum)\n",
-         ntohs(udphdr->len), ntohs(udphdr->chksum)));
-  LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n"));
-}
-#endif /* UDP_DEBUG */
-
-#endif /* LWIP_UDP */
-
-
-
-
-
-
-
-
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv4/lwip/icmp.h b/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv4/lwip/icmp.h
deleted file mode 100644
index 634405b71..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv4/lwip/icmp.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_ICMP_H__
-#define __LWIP_ICMP_H__
-
-#include "lwip/arch.h"
-
-#include "lwip/opt.h"
-#include "lwip/pbuf.h"
-
-#include "lwip/ip_addr.h"
-#include "lwip/netif.h"
-
-#define ICMP_ER 0      /* echo reply */
-#define ICMP_DUR 3     /* destination unreachable */
-#define ICMP_SQ 4      /* source quench */
-#define ICMP_RD 5      /* redirect */
-#define ICMP_ECHO 8    /* echo */
-#define ICMP_TE 11     /* time exceeded */
-#define ICMP_PP 12     /* parameter problem */
-#define ICMP_TS 13     /* timestamp */
-#define ICMP_TSR 14    /* timestamp reply */
-#define ICMP_IRQ 15    /* information request */
-#define ICMP_IR 16     /* information reply */
-
-enum icmp_dur_type {
-  ICMP_DUR_NET = 0,    /* net unreachable */
-  ICMP_DUR_HOST = 1,   /* host unreachable */
-  ICMP_DUR_PROTO = 2,  /* protocol unreachable */
-  ICMP_DUR_PORT = 3,   /* port unreachable */
-  ICMP_DUR_FRAG = 4,   /* fragmentation needed and DF set */
-  ICMP_DUR_SR = 5      /* source route failed */
-};
-
-enum icmp_te_type {
-  ICMP_TE_TTL = 0,     /* time to live exceeded in transit */
-  ICMP_TE_FRAG = 1     /* fragment reassembly time exceeded */
-};
-
-void icmp_input(struct pbuf *p, struct netif *inp);
-
-void icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t);
-void icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t);
-
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-struct icmp_echo_hdr {
-  PACK_STRUCT_FIELD(u16_t _type_code);
-  PACK_STRUCT_FIELD(u16_t chksum);
-  PACK_STRUCT_FIELD(u16_t id);
-  PACK_STRUCT_FIELD(u16_t seqno);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-
-PACK_STRUCT_BEGIN
-struct icmp_dur_hdr {
-  PACK_STRUCT_FIELD(u16_t _type_code);
-  PACK_STRUCT_FIELD(u16_t chksum);
-  PACK_STRUCT_FIELD(u32_t unused);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-
-PACK_STRUCT_BEGIN
-struct icmp_te_hdr {
-  PACK_STRUCT_FIELD(u16_t _type_code);
-  PACK_STRUCT_FIELD(u16_t chksum);
-  PACK_STRUCT_FIELD(u32_t unused);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-#define ICMPH_TYPE(hdr) (ntohs((hdr)->_type_code) >> 8)
-#define ICMPH_CODE(hdr) (ntohs((hdr)->_type_code) & 0xff)
-
-#define ICMPH_TYPE_SET(hdr, type) ((hdr)->_type_code = htons(ICMPH_CODE(hdr) | ((type) << 8)))
-#define ICMPH_CODE_SET(hdr, code) ((hdr)->_type_code = htons((code) | (ICMPH_TYPE(hdr) << 8)))
-
-#endif /* __LWIP_ICMP_H__ */
-    
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv4/lwip/inet.h b/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv4/lwip/inet.h
deleted file mode 100644
index 6d79aab7a..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv4/lwip/inet.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_INET_H__
-#define __LWIP_INET_H__
-
-#include "lwip/arch.h"
-
-#include "lwip/opt.h"
-#include "lwip/pbuf.h"
-#include "lwip/ip_addr.h"
-
-u16_t inet_chksum(void *dataptr, u16_t len);
-#if 0 /* optimized routine */
-u16_t inet_chksum4(u8_t *dataptr, u16_t len);
-#endif
-u16_t inet_chksum_pbuf(struct pbuf *p);
-u16_t inet_chksum_pseudo(struct pbuf *p,
-       struct ip_addr *src, struct ip_addr *dest,
-       u8_t proto, u16_t proto_len);
-
-u32_t inet_addr(const char *cp);
-s8_t inet_aton(const char *cp, struct in_addr *addr);
-char *inet_ntoa(struct in_addr addr); /* returns ptr to static buffer; not reentrant! */
-
-#ifdef htons
-#undef htons
-#endif /* htons */
-#ifdef htonl
-#undef htonl
-#endif /* htonl */
-#ifdef ntohs
-#undef ntohs
-#endif /* ntohs */
-#ifdef ntohl
-#undef ntohl
-#endif /* ntohl */
-
-#if BYTE_ORDER == BIG_ENDIAN
-#define htons(x) (x)
-#define ntohs(x) (x)
-#define htonl(x) (x)
-#define ntohl(x) (x)
-#else
-#ifdef LWIP_PREFIX_BYTEORDER_FUNCS
-/* workaround for naming collisions on some platforms */
-#define htons lwip_htons
-#define ntohs lwip_ntohs
-#define htonl lwip_htonl
-#define ntohl lwip_ntohl
-#endif
-u16_t htons(u16_t x);
-u16_t ntohs(u16_t x);
-u32_t htonl(u32_t x);
-u32_t ntohl(u32_t x);
-#endif
-
-#endif /* __LWIP_INET_H__ */
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv4/lwip/ip.h b/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv4/lwip/ip.h
deleted file mode 100644
index 4c15e1a0e..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv4/lwip/ip.h
+++ /dev/null
@@ -1,154 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_IP_H__
-#define __LWIP_IP_H__
-
-#include "lwip/arch.h"
-
-#include "lwip/def.h"
-#include "lwip/pbuf.h"
-#include "lwip/ip_addr.h"
-
-#include "lwip/err.h"
-
-
-void ip_init(void);
-struct netif *ip_route(struct ip_addr *dest);
-err_t ip_input(struct pbuf *p, struct netif *inp);
-err_t ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
-		u8_t ttl, u8_t tos, u8_t proto);
-err_t ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
-		   u8_t ttl, u8_t tos, u8_t proto,
-       struct netif *netif);
-
-#define IP_HLEN 20
-
-#define IP_PROTO_ICMP 1
-#define IP_PROTO_UDP 17
-#define IP_PROTO_UDPLITE 170
-#define IP_PROTO_TCP 6
-
-/* This is passed as the destination address to ip_output_if (not
-   to ip_output), meaning that an IP header already is constructed
-   in the pbuf. This is used when TCP retransmits. */
-#ifdef IP_HDRINCL
-#undef IP_HDRINCL
-#endif /* IP_HDRINCL */
-#define IP_HDRINCL  NULL
-
-
-/* This is the common part of all PCB types. It needs to be at the
-   beginning of a PCB type definition. It is located here so that
-   changes to this common part are made in one location instead of
-   having to change all PCB structs. */
-#define IP_PCB struct ip_addr local_ip; \
-  struct ip_addr remote_ip; \
-   /* Socket options */  \
-  u16_t so_options;      \
-   /* Type Of Service */ \
-  u8_t tos;              \
-  /* Time To Live */     \
-  u8_t ttl
-
-/*
- * Option flags per-socket. These are the same like SO_XXX.
- */
-#define	SOF_DEBUG	    (u16_t)0x0001U		/* turn on debugging info recording */
-#define	SOF_ACCEPTCONN	(u16_t)0x0002U		/* socket has had listen() */
-#define	SOF_REUSEADDR	(u16_t)0x0004U		/* allow local address reuse */
-#define	SOF_KEEPALIVE	(u16_t)0x0008U		/* keep connections alive */
-#define	SOF_DONTROUTE	(u16_t)0x0010U		/* just use interface addresses */
-#define	SOF_BROADCAST	(u16_t)0x0020U		/* permit sending of broadcast msgs */
-#define	SOF_USELOOPBACK	(u16_t)0x0040U		/* bypass hardware when possible */
-#define	SOF_LINGER	    (u16_t)0x0080U		/* linger on close if data present */
-#define	SOF_OOBINLINE	(u16_t)0x0100U		/* leave received OOB data in line */
-#define	SOF_REUSEPORT	(u16_t)0x0200U		/* allow local address & port reuse */
-
-
-
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-struct ip_hdr {
-  /* version / header length / type of service */
-  PACK_STRUCT_FIELD(u16_t _v_hl_tos);
-  /* total length */
-  PACK_STRUCT_FIELD(u16_t _len);
-  /* identification */
-  PACK_STRUCT_FIELD(u16_t _id);
-  /* fragment offset field */
-  PACK_STRUCT_FIELD(u16_t _offset);
-#define IP_RF 0x8000        /* reserved fragment flag */
-#define IP_DF 0x4000        /* dont fragment flag */
-#define IP_MF 0x2000        /* more fragments flag */
-#define IP_OFFMASK 0x1fff   /* mask for fragmenting bits */
-  /* time to live / protocol*/
-  PACK_STRUCT_FIELD(u16_t _ttl_proto);
-  /* checksum */
-  PACK_STRUCT_FIELD(u16_t _chksum);
-  /* source and destination IP addresses */
-  PACK_STRUCT_FIELD(struct ip_addr src);
-  PACK_STRUCT_FIELD(struct ip_addr dest); 
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-#define IPH_V(hdr)  (ntohs((hdr)->_v_hl_tos) >> 12)
-#define IPH_HL(hdr) ((ntohs((hdr)->_v_hl_tos) >> 8) & 0x0f)
-#define IPH_TOS(hdr) (ntohs((hdr)->_v_hl_tos) & 0xff)
-#define IPH_LEN(hdr) ((hdr)->_len)
-#define IPH_ID(hdr) ((hdr)->_id)
-#define IPH_OFFSET(hdr) ((hdr)->_offset)
-#define IPH_TTL(hdr) (ntohs((hdr)->_ttl_proto) >> 8)
-#define IPH_PROTO(hdr) (ntohs((hdr)->_ttl_proto) & 0xff)
-#define IPH_CHKSUM(hdr) ((hdr)->_chksum)
-
-#define IPH_VHLTOS_SET(hdr, v, hl, tos) (hdr)->_v_hl_tos = (htons(((v) << 12) | ((hl) << 8) | (tos)))
-#define IPH_LEN_SET(hdr, len) (hdr)->_len = (len)
-#define IPH_ID_SET(hdr, id) (hdr)->_id = (id)
-#define IPH_OFFSET_SET(hdr, off) (hdr)->_offset = (off)
-#define IPH_TTL_SET(hdr, ttl) (hdr)->_ttl_proto = (htons(IPH_PROTO(hdr) | ((ttl) << 8)))
-#define IPH_PROTO_SET(hdr, proto) (hdr)->_ttl_proto = (htons((proto) | (IPH_TTL(hdr) << 8)))
-#define IPH_CHKSUM_SET(hdr, chksum) (hdr)->_chksum = (chksum)
-
-#if IP_DEBUG
-void ip_debug_print(struct pbuf *p);
-#else
-#define ip_debug_print(p)
-#endif /* IP_DEBUG */
-
-#endif /* __LWIP_IP_H__ */
-
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv4/lwip/ip_addr.h b/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv4/lwip/ip_addr.h
deleted file mode 100644
index 2819b1529..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv4/lwip/ip_addr.h
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_IP_ADDR_H__
-#define __LWIP_IP_ADDR_H__
-
-#include "lwip/arch.h"
-
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-struct ip_addr {
-  PACK_STRUCT_FIELD(u32_t addr);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-struct ip_addr2 {
-  PACK_STRUCT_FIELD(u16_t addrw[2]);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-/* For compatibility with BSD code */
-struct in_addr {
-  u32_t s_addr;
-};
-
-struct netif;
-
-extern const struct ip_addr ip_addr_any;
-extern const struct ip_addr ip_addr_broadcast;
-
-/** IP_ADDR_ can be used as a fixed IP address
- *  for the wildcard and the broadcast address
- */
-#define IP_ADDR_ANY ((struct ip_addr *)&ip_addr_any)
-#define IP_ADDR_BROADCAST ((struct ip_addr *)&ip_addr_broadcast)
-
-#define INADDR_NONE    ((u32_t) 0xffffffff)  /* 255.255.255.255 */
-#define INADDR_LOOPBACK    ((u32_t) 0x7f000001)  /* 127.0.0.1 */
-
-/* Definitions of the bits in an Internet address integer.
-
-   On subnets, host and network parts are found according to
-   the subnet mask, not these masks.  */
-
-#define  IN_CLASSA(a)    ((((u32_t)(a)) & 0x80000000) == 0)
-#define  IN_CLASSA_NET    0xff000000
-#define  IN_CLASSA_NSHIFT  24
-#define  IN_CLASSA_HOST    (0xffffffff & ~IN_CLASSA_NET)
-#define  IN_CLASSA_MAX    128
-
-#define  IN_CLASSB(a)    ((((u32_t)(a)) & 0xc0000000) == 0x80000000)
-#define  IN_CLASSB_NET    0xffff0000
-#define  IN_CLASSB_NSHIFT  16
-#define  IN_CLASSB_HOST    (0xffffffff & ~IN_CLASSB_NET)
-#define  IN_CLASSB_MAX    65536
-
-#define  IN_CLASSC(a)    ((((u32_t)(a)) & 0xe0000000) == 0xc0000000)
-#define  IN_CLASSC_NET    0xffffff00
-#define  IN_CLASSC_NSHIFT  8
-#define  IN_CLASSC_HOST    (0xffffffff & ~IN_CLASSC_NET)
-
-#define IN_CLASSD(a)        (((u32_t)(a) & 0xf0000000) == 0xe0000000)
-#define IN_CLASSD_NET       0xf0000000  /* These ones aren't really */
-#define IN_CLASSD_NSHIFT    28      /* net and host fields, but */
-#define IN_CLASSD_HOST      0x0fffffff  /* routing needn't know.    */
-#define IN_MULTICAST(a)     IN_CLASSD(a)
-
-#define IN_EXPERIMENTAL(a)  (((u32_t)(a) & 0xf0000000) == 0xf0000000)
-#define IN_BADCLASS(a)      (((u32_t)(a) & 0xf0000000) == 0xf0000000)
-
-#define IN_LOOPBACKNET      127         /* official! */
-
-
-#define IP4_ADDR(ipaddr, a,b,c,d) (ipaddr)->addr = htonl(((u32_t)(a & 0xff) << 24) | ((u32_t)(b & 0xff) << 16) | \
-                                                         ((u32_t)(c & 0xff) << 8) | (u32_t)(d & 0xff))
-
-#define ip_addr_set(dest, src) (dest)->addr = \
-                               ((src) == NULL? 0:\
-                               (src)->addr)
-/**
- * Determine if two address are on the same network.
- *
- * @arg addr1 IP address 1
- * @arg addr2 IP address 2
- * @arg mask network identifier mask
- * @return !0 if the network identifiers of both address match
- */
-#define ip_addr_netcmp(addr1, addr2, mask) (((addr1)->addr & \
-                                              (mask)->addr) == \
-                                             ((addr2)->addr & \
-                                              (mask)->addr))
-#define ip_addr_cmp(addr1, addr2) ((addr1)->addr == (addr2)->addr)
-
-#define ip_addr_isany(addr1) ((addr1) == NULL || (addr1)->addr == 0)
-
-u8_t ip_addr_isbroadcast(struct ip_addr *, struct netif *);
-
-#define ip_addr_ismulticast(addr1) (((addr1)->addr & ntohl(0xf0000000)) == ntohl(0xe0000000))
-
-
-#define ip_addr_debug_print(debug, ipaddr) LWIP_DEBUGF(debug, ("%"U16_F".%"U16_F".%"U16_F".%"U16_F, \
-        ipaddr?(u16_t)(ntohl((ipaddr)->addr) >> 24) & 0xff:0, \
-        ipaddr?(u16_t)(ntohl((ipaddr)->addr) >> 16) & 0xff:0, \
-        ipaddr?(u16_t)(ntohl((ipaddr)->addr) >> 8) & 0xff:0, \
-        ipaddr?(u16_t)ntohl((ipaddr)->addr) & 0xff:0U))
-
-/* cast to unsigned int, as it is used as argument to printf functions
- * which expect integer arguments. CSi: use cc.h formatters (conversion chars)! */
-#define ip4_addr1(ipaddr) ((u16_t)(ntohl((ipaddr)->addr) >> 24) & 0xff)
-#define ip4_addr2(ipaddr) ((u16_t)(ntohl((ipaddr)->addr) >> 16) & 0xff)
-#define ip4_addr3(ipaddr) ((u16_t)(ntohl((ipaddr)->addr) >> 8) & 0xff)
-#define ip4_addr4(ipaddr) ((u16_t)(ntohl((ipaddr)->addr)) & 0xff)
-#endif /* __LWIP_IP_ADDR_H__ */
-
-
-
-
-
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv4/lwip/ip_frag.h b/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv4/lwip/ip_frag.h
deleted file mode 100644
index a982c5a63..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv4/lwip/ip_frag.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Jani Monoses 
- *
- */
-
-#ifndef __LWIP_IP_FRAG_H__
-#define __LWIP_IP_FRAG_H__
-
-#include "lwip/err.h"
-#include "lwip/pbuf.h"
-#include "lwip/netif.h"
-#include "lwip/ip_addr.h"
-
-void ip_reass_tmr(void);
-struct pbuf * ip_reass(struct pbuf *p);
-err_t ip_frag(struct pbuf *p, struct netif *netif, struct ip_addr *dest);
-
-#endif /* __LWIP_IP_FRAG_H__ */
-
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv6/lwip/icmp.h b/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv6/lwip/icmp.h
deleted file mode 100644
index 2b6adb122..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv6/lwip/icmp.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_ICMP_H__
-#define __LWIP_ICMP_H__
-
-#include "lwip/arch.h"
-
-#include "lwip/opt.h"
-#include "lwip/pbuf.h"
-
-#include "lwip/netif.h"
-
-#define ICMP6_DUR  1
-#define ICMP6_TE   3
-#define ICMP6_ECHO 128    /* echo */
-#define ICMP6_ER   129      /* echo reply */
-
-
-enum icmp_dur_type {
-  ICMP_DUR_NET = 0,    /* net unreachable */
-  ICMP_DUR_HOST = 1,   /* host unreachable */
-  ICMP_DUR_PROTO = 2,  /* protocol unreachable */
-  ICMP_DUR_PORT = 3,   /* port unreachable */
-  ICMP_DUR_FRAG = 4,   /* fragmentation needed and DF set */
-  ICMP_DUR_SR = 5      /* source route failed */
-};
-
-enum icmp_te_type {
-  ICMP_TE_TTL = 0,     /* time to live exceeded in transit */
-  ICMP_TE_FRAG = 1     /* fragment reassembly time exceeded */
-};
-
-void icmp_input(struct pbuf *p, struct netif *inp);
-
-void icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t);
-void icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t);
-
-struct icmp_echo_hdr {
-  u8_t type;
-  u8_t icode;
-  u16_t chksum;
-  u16_t id;
-  u16_t seqno;
-};
-
-struct icmp_dur_hdr {
-  u8_t type;
-  u8_t icode;
-  u16_t chksum;
-  u32_t unused;
-};
-
-struct icmp_te_hdr {
-  u8_t type;
-  u8_t icode;
-  u16_t chksum;
-  u32_t unused;
-};
-
-#endif /* __LWIP_ICMP_H__ */
-    
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv6/lwip/inet.h b/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv6/lwip/inet.h
deleted file mode 100644
index ae7834364..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv6/lwip/inet.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_INET_H__
-#define __LWIP_INET_H__
-
-#include "lwip/arch.h"
-
-#include "lwip/opt.h"
-#include "lwip/pbuf.h"
-#include "lwip/ip_addr.h"
-
-u16_t inet_chksum(void *data, u16_t len);
-u16_t inet_chksum_pbuf(struct pbuf *p);
-u16_t inet_chksum_pseudo(struct pbuf *p,
-       struct ip_addr *src, struct ip_addr *dest,
-       u8_t proto, u32_t proto_len);
-
-u32_t inet_addr(const char *cp);
-s8_t inet_aton(const char *cp, struct in_addr *addr);
-
-#ifndef _MACHINE_ENDIAN_H_
-#ifndef _NETINET_IN_H
-#ifndef _LINUX_BYTEORDER_GENERIC_H
-u16_t htons(u16_t n);
-u16_t ntohs(u16_t n);
-u32_t htonl(u32_t n);
-u32_t ntohl(u32_t n);
-#endif /* _LINUX_BYTEORDER_GENERIC_H */
-#endif /* _NETINET_IN_H */
-#endif /* _MACHINE_ENDIAN_H_ */
-
-#endif /* __LWIP_INET_H__ */
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv6/lwip/ip.h b/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv6/lwip/ip.h
deleted file mode 100644
index f46bf9a80..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv6/lwip/ip.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_IP_H__
-#define __LWIP_IP_H__
-
-#include "lwip/opt.h"
-#include "lwip/def.h"
-#include "lwip/pbuf.h"
-#include "lwip/ip_addr.h"
-
-#include "lwip/err.h"
-
-#define IP_HLEN 40
-
-#define IP_PROTO_ICMP 58
-#define IP_PROTO_UDP 17
-#define IP_PROTO_UDPLITE 170
-#define IP_PROTO_TCP 6
-
-/* This is passed as the destination address to ip_output_if (not
-   to ip_output), meaning that an IP header already is constructed
-   in the pbuf. This is used when TCP retransmits. */
-#ifdef IP_HDRINCL
-#undef IP_HDRINCL
-#endif /* IP_HDRINCL */
-#define IP_HDRINCL  NULL
-
-
-/* The IPv6 header. */
-struct ip_hdr {
-#if BYTE_ORDER == LITTLE_ENDIAN
-  u8_t tclass1:4, v:4;
-  u8_t flow1:4, tclass2:4;  
-#else
-  u8_t v:4, tclass1:4;
-  u8_t tclass2:8, flow1:4;
-#endif
-  u16_t flow2;
-  u16_t len;                /* payload length */
-  u8_t nexthdr;             /* next header */
-  u8_t hoplim;              /* hop limit (TTL) */
-  struct ip_addr src, dest;          /* source and destination IP addresses */
-};
-
-void ip_init(void);
-
-#include "lwip/netif.h"
-
-struct netif *ip_route(struct ip_addr *dest);
-
-void ip_input(struct pbuf *p, struct netif *inp);
-
-/* source and destination addresses in network byte order, please */
-err_t ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
-         u8_t ttl, u8_t proto);
-
-err_t ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest,
-      u8_t ttl, u8_t proto,
-      struct netif *netif);
-
-#if IP_DEBUG
-void ip_debug_print(struct pbuf *p);
-#endif /* IP_DEBUG */
-
-#endif /* __LWIP_IP_H__ */
-
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv6/lwip/ip_addr.h b/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv6/lwip/ip_addr.h
deleted file mode 100644
index db1f09060..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/include/ipv6/lwip/ip_addr.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_IP_ADDR_H__
-#define __LWIP_IP_ADDR_H__
-
-#include "lwip/arch.h"
-
-#define IP_ADDR_ANY 0
-
-struct ip_addr {
-  u32_t addr[4];
-};
-
-#define IP6_ADDR(ipaddr, a,b,c,d,e,f,g,h) do { (ipaddr)->addr[0] = htonl((u32_t)((a & 0xffff) << 16) | (b & 0xffff)); \
-                                               (ipaddr)->addr[1] = htonl(((c & 0xffff) << 16) | (d & 0xffff)); \
-                                               (ipaddr)->addr[2] = htonl(((e & 0xffff) << 16) | (f & 0xffff)); \
-                                               (ipaddr)->addr[3] = htonl(((g & 0xffff) << 16) | (h & 0xffff)); } while(0)
-
-u8_t ip_addr_netcmp(struct ip_addr *addr1, struct ip_addr *addr2,
-        struct ip_addr *mask);
-u8_t ip_addr_cmp(struct ip_addr *addr1, struct ip_addr *addr2);
-void ip_addr_set(struct ip_addr *dest, struct ip_addr *src);
-u8_t ip_addr_isany(struct ip_addr *addr);
-
-
-#if IP_DEBUG
-void ip_addr_debug_print(struct ip_addr *addr);
-#endif /* IP_DEBUG */
-
-#endif /* __LWIP_IP_ADDR_H__ */
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/api.h b/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/api.h
deleted file mode 100644
index 7f0ad5966..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/api.h
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_API_H__
-#define __LWIP_API_H__
-
-#include "lwip/opt.h"
-#include "lwip/pbuf.h"
-#include "lwip/sys.h"
-
-#include "lwip/ip.h"
-
-#include "lwip/raw.h"
-#include "lwip/udp.h"
-#include "lwip/tcp.h"
-
-#include "lwip/err.h"
-
-#define NETCONN_NOCOPY 0x00
-#define NETCONN_COPY   0x01
-
-enum netconn_type {
-  NETCONN_TCP,
-  NETCONN_UDP,
-  NETCONN_UDPLITE,
-  NETCONN_UDPNOCHKSUM,
-  NETCONN_RAW
-};
-
-enum netconn_state {
-  NETCONN_NONE,
-  NETCONN_WRITE,
-  NETCONN_ACCEPT,
-  NETCONN_RECV,
-  NETCONN_CONNECT,
-  NETCONN_CLOSE
-};
-
-enum netconn_evt {
-  NETCONN_EVT_RCVPLUS,
-  NETCONN_EVT_RCVMINUS,
-  NETCONN_EVT_SENDPLUS,
-  NETCONN_EVT_SENDMINUS
-};
-
-struct netbuf {
-  struct pbuf *p, *ptr;
-  struct ip_addr *fromaddr;
-  u16_t fromport;
-  err_t err;
-};
-
-struct netconn {
-  enum netconn_type type;
-  enum netconn_state state;
-  union {
-    struct tcp_pcb *tcp;
-    struct udp_pcb *udp;
-    struct raw_pcb *raw;
-  } pcb;
-  err_t err;
-  sys_mbox_t mbox;
-  sys_mbox_t recvmbox;
-  sys_mbox_t acceptmbox;
-  sys_sem_t sem;
-  int socket;
-  u16_t recv_avail;
-  void (* callback)(struct netconn *, enum netconn_evt, u16_t len);
-};
-
-/* Network buffer functions: */
-struct netbuf *   netbuf_new      (void);
-void              netbuf_delete   (struct netbuf *buf);
-void *            netbuf_alloc    (struct netbuf *buf, u16_t size);
-void              netbuf_free     (struct netbuf *buf);
-void              netbuf_ref      (struct netbuf *buf,
-           void *dataptr, u16_t size);
-void              netbuf_chain    (struct netbuf *head,
-           struct netbuf *tail);
-
-u16_t             netbuf_len      (struct netbuf *buf);
-err_t             netbuf_data     (struct netbuf *buf,
-           void **dataptr, u16_t *len);
-s8_t              netbuf_next     (struct netbuf *buf);
-void              netbuf_first    (struct netbuf *buf);
-
-void              netbuf_copy     (struct netbuf *buf,
-           void *dataptr, u16_t len);
-void              netbuf_copy_partial(struct netbuf *buf, void *dataptr, 
-              u16_t len, u16_t offset);
-struct ip_addr *  netbuf_fromaddr (struct netbuf *buf);
-u16_t             netbuf_fromport (struct netbuf *buf);
-
-/* Network connection functions: */
-struct netconn *  netconn_new     (enum netconn_type type);
-struct
-netconn *netconn_new_with_callback(enum netconn_type t,
-                                   void (*callback)(struct netconn *, enum netconn_evt, u16_t len));
-struct
-netconn *netconn_new_with_proto_and_callback(enum netconn_type t, u16_t proto,
-                                   void (*callback)(struct netconn *, enum netconn_evt, u16_t len));
-err_t             netconn_delete  (struct netconn *conn);
-enum netconn_type netconn_type    (struct netconn *conn);
-err_t             netconn_peer    (struct netconn *conn,
-           struct ip_addr *addr,
-           u16_t *port);
-err_t             netconn_addr    (struct netconn *conn,
-           struct ip_addr **addr,
-           u16_t *port);
-err_t             netconn_bind    (struct netconn *conn,
-           struct ip_addr *addr,
-           u16_t port);
-err_t             netconn_connect (struct netconn *conn,
-           struct ip_addr *addr,
-           u16_t port);
-err_t             netconn_disconnect (struct netconn *conn);
-err_t             netconn_listen  (struct netconn *conn);
-struct netconn *  netconn_accept  (struct netconn *conn);
-struct netbuf *   netconn_recv    (struct netconn *conn);
-err_t             netconn_send    (struct netconn *conn,
-           struct netbuf *buf);
-err_t             netconn_write   (struct netconn *conn,
-           void *dataptr, u16_t size,
-           u8_t copy);
-err_t             netconn_close   (struct netconn *conn);
-
-err_t             netconn_err     (struct netconn *conn);
-
-#endif /* __LWIP_API_H__ */
-
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/api_msg.h b/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/api_msg.h
deleted file mode 100644
index 3fef3dd0c..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/api_msg.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_API_MSG_H__
-#define __LWIP_API_MSG_H__
-
-#include "lwip/opt.h"
-#include "lwip/pbuf.h"
-#include "lwip/sys.h"
-
-#include "lwip/ip.h"
-
-#include "lwip/udp.h"
-#include "lwip/tcp.h"
-
-#include "lwip/api.h"
-
-enum api_msg_type {
-  API_MSG_NEWCONN,
-  API_MSG_DELCONN,
-  
-  API_MSG_BIND,
-  API_MSG_CONNECT,
-  API_MSG_DISCONNECT,
-
-  API_MSG_LISTEN,
-  API_MSG_ACCEPT,
-
-  API_MSG_SEND,
-  API_MSG_RECV,
-  API_MSG_WRITE,
-
-  API_MSG_CLOSE,
-  
-  API_MSG_MAX
-};
-
-struct api_msg_msg {
-  struct netconn *conn;
-  enum netconn_type conntype;
-  union {
-    struct pbuf *p;   
-    struct  {
-      struct ip_addr *ipaddr;
-      u16_t port;
-    } bc;
-    struct {
-      void *dataptr;
-      u16_t len;
-      u8_t copy;
-    } w;    
-    sys_mbox_t mbox;
-    u16_t len;
-  } msg;
-};
-
-struct api_msg {
-  enum api_msg_type type;
-  struct api_msg_msg msg;
-};
-
-void api_msg_input(struct api_msg *msg);
-void api_msg_post(struct api_msg *msg);
-
-#endif /* __LWIP_API_MSG_H__ */
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/arch.h b/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/arch.h
deleted file mode 100644
index e0d622a4b..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/arch.h
+++ /dev/null
@@ -1,216 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_ARCH_H__
-#define __LWIP_ARCH_H__
-
-#ifndef LITTLE_ENDIAN
-#define LITTLE_ENDIAN 1234
-#endif
-
-#ifndef BIG_ENDIAN
-#define BIG_ENDIAN 4321
-#endif
-
-#include "arch/cc.h"
-
-#ifndef PACK_STRUCT_BEGIN
-#define PACK_STRUCT_BEGIN
-#endif /* PACK_STRUCT_BEGIN */
-
-#ifndef PACK_STRUCT_END
-#define PACK_STRUCT_END
-#endif /* PACK_STRUCT_END */
-
-#ifndef PACK_STRUCT_FIELD
-#define PACK_STRUCT_FIELD(x) x
-#endif /* PACK_STRUCT_FIELD */
-
-
-
-#ifdef LWIP_PROVIDE_ERRNO
-
-#define  EPERM     1  /* Operation not permitted */
-#define  ENOENT     2  /* No such file or directory */
-#define  ESRCH     3  /* No such process */
-#define  EINTR     4  /* Interrupted system call */
-#define  EIO     5  /* I/O error */
-#define  ENXIO     6  /* No such device or address */
-#define  E2BIG     7  /* Arg list too long */
-#define  ENOEXEC     8  /* Exec format error */
-#define  EBADF     9  /* Bad file number */
-#define  ECHILD    10  /* No child processes */
-#define  EAGAIN    11  /* Try again */
-#define  ENOMEM    12  /* Out of memory */
-#define  EACCES    13  /* Permission denied */
-#define  EFAULT    14  /* Bad address */
-#define  ENOTBLK    15  /* Block device required */
-#define  EBUSY    16  /* Device or resource busy */
-#define  EEXIST    17  /* File exists */
-#define  EXDEV    18  /* Cross-device link */
-#define  ENODEV    19  /* No such device */
-#define  ENOTDIR    20  /* Not a directory */
-#define  EISDIR    21  /* Is a directory */
-#define  EINVAL    22  /* Invalid argument */
-#define  ENFILE    23  /* File table overflow */
-#define  EMFILE    24  /* Too many open files */
-#define  ENOTTY    25  /* Not a typewriter */
-#define  ETXTBSY    26  /* Text file busy */
-#define  EFBIG    27  /* File too large */
-#define  ENOSPC    28  /* No space left on device */
-#define  ESPIPE    29  /* Illegal seek */
-#define  EROFS    30  /* Read-only file system */
-#define  EMLINK    31  /* Too many links */
-#define  EPIPE    32  /* Broken pipe */
-#define  EDOM    33  /* Math argument out of domain of func */
-#define  ERANGE    34  /* Math result not representable */
-#define  EDEADLK    35  /* Resource deadlock would occur */
-#define  ENAMETOOLONG  36  /* File name too long */
-#define  ENOLCK    37  /* No record locks available */
-#define  ENOSYS    38  /* Function not implemented */
-#define  ENOTEMPTY  39  /* Directory not empty */
-#define  ELOOP    40  /* Too many symbolic links encountered */
-#define  EWOULDBLOCK  EAGAIN  /* Operation would block */
-#define  ENOMSG    42  /* No message of desired type */
-#define  EIDRM    43  /* Identifier removed */
-#define  ECHRNG    44  /* Channel number out of range */
-#define  EL2NSYNC  45  /* Level 2 not synchronized */
-#define  EL3HLT    46  /* Level 3 halted */
-#define  EL3RST    47  /* Level 3 reset */
-#define  ELNRNG    48  /* Link number out of range */
-#define  EUNATCH    49  /* Protocol driver not attached */
-#define  ENOCSI    50  /* No CSI structure available */
-#define  EL2HLT    51  /* Level 2 halted */
-#define  EBADE    52  /* Invalid exchange */
-#define  EBADR    53  /* Invalid request descriptor */
-#define  EXFULL    54  /* Exchange full */
-#define  ENOANO    55  /* No anode */
-#define  EBADRQC    56  /* Invalid request code */
-#define  EBADSLT    57  /* Invalid slot */
-
-#define  EDEADLOCK  EDEADLK
-
-#define  EBFONT    59  /* Bad font file format */
-#define  ENOSTR    60  /* Device not a stream */
-#define  ENODATA    61  /* No data available */
-#define  ETIME    62  /* Timer expired */
-#define  ENOSR    63  /* Out of streams resources */
-#define  ENONET    64  /* Machine is not on the network */
-#define  ENOPKG    65  /* Package not installed */
-#define  EREMOTE    66  /* Object is remote */
-#define  ENOLINK    67  /* Link has been severed */
-#define  EADV    68  /* Advertise error */
-#define  ESRMNT    69  /* Srmount error */
-#define  ECOMM    70  /* Communication error on send */
-#define  EPROTO    71  /* Protocol error */
-#define  EMULTIHOP  72  /* Multihop attempted */
-#define  EDOTDOT    73  /* RFS specific error */
-#define  EBADMSG    74  /* Not a data message */
-#define  EOVERFLOW  75  /* Value too large for defined data type */
-#define  ENOTUNIQ  76  /* Name not unique on network */
-#define  EBADFD    77  /* File descriptor in bad state */
-#define  EREMCHG    78  /* Remote address changed */
-#define  ELIBACC    79  /* Can not access a needed shared library */
-#define  ELIBBAD    80  /* Accessing a corrupted shared library */
-#define  ELIBSCN    81  /* .lib section in a.out corrupted */
-#define  ELIBMAX    82  /* Attempting to link in too many shared libraries */
-#define  ELIBEXEC  83  /* Cannot exec a shared library directly */
-#define  EILSEQ    84  /* Illegal byte sequence */
-#define  ERESTART  85  /* Interrupted system call should be restarted */
-#define  ESTRPIPE  86  /* Streams pipe error */
-#define  EUSERS    87  /* Too many users */
-#define  ENOTSOCK  88  /* Socket operation on non-socket */
-#define  EDESTADDRREQ  89  /* Destination address required */
-#define  EMSGSIZE  90  /* Message too long */
-#define  EPROTOTYPE  91  /* Protocol wrong type for socket */
-#define  ENOPROTOOPT  92  /* Protocol not available */
-#define  EPROTONOSUPPORT  93  /* Protocol not supported */
-#define  ESOCKTNOSUPPORT  94  /* Socket type not supported */
-#define  EOPNOTSUPP  95  /* Operation not supported on transport endpoint */
-#define  EPFNOSUPPORT  96  /* Protocol family not supported */
-#define  EAFNOSUPPORT  97  /* Address family not supported by protocol */
-#define  EADDRINUSE  98  /* Address already in use */
-#define  EADDRNOTAVAIL  99  /* Cannot assign requested address */
-#define  ENETDOWN  100  /* Network is down */
-#define  ENETUNREACH  101  /* Network is unreachable */
-#define  ENETRESET  102  /* Network dropped connection because of reset */
-#define  ECONNABORTED  103  /* Software caused connection abort */
-#define  ECONNRESET  104  /* Connection reset by peer */
-#define  ENOBUFS    105  /* No buffer space available */
-#define  EISCONN    106  /* Transport endpoint is already connected */
-#define  ENOTCONN  107  /* Transport endpoint is not connected */
-#define  ESHUTDOWN  108  /* Cannot send after transport endpoint shutdown */
-#define  ETOOMANYREFS  109  /* Too many references: cannot splice */
-#define  ETIMEDOUT  110  /* Connection timed out */
-#define  ECONNREFUSED  111  /* Connection refused */
-#define  EHOSTDOWN  112  /* Host is down */
-#define  EHOSTUNREACH  113  /* No route to host */
-#define  EALREADY  114  /* Operation already in progress */
-#define  EINPROGRESS  115  /* Operation now in progress */
-#define  ESTALE    116  /* Stale NFS file handle */
-#define  EUCLEAN    117  /* Structure needs cleaning */
-#define  ENOTNAM    118  /* Not a XENIX named type file */
-#define  ENAVAIL    119  /* No XENIX semaphores available */
-#define  EISNAM    120  /* Is a named type file */
-#define  EREMOTEIO  121  /* Remote I/O error */
-#define  EDQUOT    122  /* Quota exceeded */
-
-#define  ENOMEDIUM  123  /* No medium found */
-#define  EMEDIUMTYPE  124  /* Wrong medium type */
-
-
-#define	ENSROK		0	/* DNS server returned answer with no data */
-#define	ENSRNODATA	160	/* DNS server returned answer with no data */
-#define	ENSRFORMERR	161	/* DNS server claims query was misformatted */
-#define	ENSRSERVFAIL 162	/* DNS server returned general failure */
-#define	ENSRNOTFOUND 163	/* Domain name not found */
-#define	ENSRNOTIMP	164	/* DNS server does not implement requested operation */
-#define	ENSRREFUSED	165	/* DNS server refused query */
-#define	ENSRBADQUERY 166	/* Misformatted DNS query */
-#define	ENSRBADNAME	167	/* Misformatted domain name */
-#define	ENSRBADFAMILY 168	/* Unsupported address family */
-#define	ENSRBADRESP	169	/* Misformatted DNS reply */
-#define	ENSRCONNREFUSED	170	/* Could not contact DNS servers */
-#define	ENSRTIMEOUT	171	/* Timeout while contacting DNS servers */
-#define	ENSROF		172	/* End of file */
-#define	ENSRFILE	173	/* Error reading file */
-#define	ENSRNOMEM	174	/* Out of memory */
-#define	ENSRDESTRUCTION	175	/* Application terminated lookup */
-#define	ENSRQUERYDOMAINTOOLONG	176	/* Domain name is too long */
-#define	ENSRCNAMELOOP	177	/* Domain name is too long */
-
-#ifndef errno
-extern int errno;
-#endif
-
-#endif /* LWIP_PROVIDE_ERRNO */
-
-#endif /* __LWIP_ARCH_H__ */
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/debug.h b/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/debug.h
deleted file mode 100644
index 8f63a7b62..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/debug.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_DEBUG_H__
-#define __LWIP_DEBUG_H__
-
-#include "arch/cc.h"
-
-/** lower two bits indicate debug level
- * - 0 off
- * - 1 warning
- * - 2 serious
- * - 3 severe
- */
-
-#define DBG_LEVEL_OFF     0
-#define DBG_LEVEL_WARNING 1  /* bad checksums, dropped packets, ... */
-#define DBG_LEVEL_SERIOUS 2  /* memory allocation failures, ... */
-#define DBG_LEVEL_SEVERE  3  /* */ 
-#define DBG_MASK_LEVEL    3
-
-/** flag for LWIP_DEBUGF to enable that debug message */
-#define DBG_ON  0x80U
-/** flag for LWIP_DEBUGF to disable that debug message */
-#define DBG_OFF 0x00U
-
-/** flag for LWIP_DEBUGF indicating a tracing message (to follow program flow) */
-#define DBG_TRACE   0x40U
-/** flag for LWIP_DEBUGF indicating a state debug message (to follow module states) */
-#define DBG_STATE   0x20U
-/** flag for LWIP_DEBUGF indicating newly added code, not thoroughly tested yet */
-#define DBG_FRESH   0x10U
-/** flag for LWIP_DEBUGF to halt after printing this debug message */
-#define DBG_HALT    0x08U
-
-#ifndef LWIP_NOASSERT
-#  define LWIP_ASSERT(x,y) do { if(!(y)) LWIP_PLATFORM_ASSERT(x); } while(0)
-#else
-#  define LWIP_ASSERT(x,y) 
-#endif
-
-#ifdef LWIP_DEBUG
-/** print debug message only if debug message type is enabled...
- *  AND is of correct type AND is at least DBG_LEVEL
- */
-#  define LWIP_DEBUGF(debug,x) do { if (((debug) & DBG_ON) && ((debug) & DBG_TYPES_ON) && ((s16_t)((debug) & DBG_MASK_LEVEL) >= DBG_MIN_LEVEL)) { LWIP_PLATFORM_DIAG(x); if ((debug) & DBG_HALT) while(1); } } while(0)
-#  define LWIP_ERROR(x)   do { LWIP_PLATFORM_DIAG(x); } while(0)  
-#else /* LWIP_DEBUG */
-#  define LWIP_DEBUGF(debug,x) 
-#  define LWIP_ERROR(x)  
-#endif /* LWIP_DEBUG */
-
-#endif /* __LWIP_DEBUG_H__ */
-
-
-
-
-
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/def.h b/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/def.h
deleted file mode 100644
index eba9b8774..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/def.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_DEF_H__
-#define __LWIP_DEF_H__
-
-/* this might define NULL already */
-#include "arch/cc.h"
-
-#define LWIP_MAX(x , y)  (x) > (y) ? (x) : (y)
-#define LWIP_MIN(x , y)  (x) < (y) ? (x) : (y)
-
-#ifndef NULL
-#define NULL ((void *)0)
-#endif
-
-
-#endif /* __LWIP_DEF_H__ */
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/dhcp.h b/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/dhcp.h
deleted file mode 100644
index bfe753f26..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/dhcp.h
+++ /dev/null
@@ -1,223 +0,0 @@
-/** @file
- */
-
-#ifndef __LWIP_DHCP_H__
-#define __LWIP_DHCP_H__
-
-#include "lwip/opt.h"
-#include "lwip/netif.h"
-#include "lwip/udp.h"
-
-/** period (in seconds) of the application calling dhcp_coarse_tmr() */
-#define DHCP_COARSE_TIMER_SECS 60 
-/** period (in milliseconds) of the application calling dhcp_fine_tmr() */
-#define DHCP_FINE_TIMER_MSECS 500 
-
-struct dhcp
-{
-  /** current DHCP state machine state */
-  u8_t state;
-  /** retries of current request */
-  u8_t tries;
-  /** transaction identifier of last sent request */ 
-  u32_t xid;
-  /** our connection to the DHCP server */ 
-  struct udp_pcb *pcb;
-  /** (first) pbuf of incoming msg */
-  struct pbuf *p;
-  /** incoming msg */
-  struct dhcp_msg *msg_in;
-  /** incoming msg options */
-  struct dhcp_msg *options_in; 
-  /** ingoing msg options length */
-  u16_t options_in_len;
-
-  struct pbuf *p_out; /* pbuf of outcoming msg */
-  struct dhcp_msg *msg_out; /* outgoing msg */
-  u16_t options_out_len; /* outgoing msg options length */
-  u16_t request_timeout; /* #ticks with period DHCP_FINE_TIMER_SECS for request timeout */
-  u16_t t1_timeout;  /* #ticks with period DHCP_COARSE_TIMER_SECS for renewal time */
-  u16_t t2_timeout;  /* #ticks with period DHCP_COARSE_TIMER_SECS for rebind time */
-  struct ip_addr server_ip_addr; /* dhcp server address that offered this lease */
-  struct ip_addr offered_ip_addr;
-  struct ip_addr offered_sn_mask;
-  struct ip_addr offered_gw_addr;
-  struct ip_addr offered_bc_addr;
-#define DHCP_MAX_DNS 2
-  u32_t dns_count; /* actual number of DNS servers obtained */
-  struct ip_addr offered_dns_addr[DHCP_MAX_DNS]; /* DNS server addresses */
- 
-  u32_t offered_t0_lease; /* lease period (in seconds) */
-  u32_t offered_t1_renew; /* recommended renew time (usually 50% of lease period) */
-  u32_t offered_t2_rebind; /* recommended rebind time (usually 66% of lease period)  */
-/** Patch #1308
- *  TODO: See dhcp.c "TODO"s
- */
-#if 0
-  struct ip_addr offered_si_addr;
-  u8_t *boot_file_name;
-#endif
-};
-
-/* MUST be compiled with "pack structs" or equivalent! */
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-/** minimum set of fields of any DHCP message */
-struct dhcp_msg
-{
-  PACK_STRUCT_FIELD(u8_t op);
-  PACK_STRUCT_FIELD(u8_t htype);
-  PACK_STRUCT_FIELD(u8_t hlen);
-  PACK_STRUCT_FIELD(u8_t hops);
-  PACK_STRUCT_FIELD(u32_t xid);
-  PACK_STRUCT_FIELD(u16_t secs);
-  PACK_STRUCT_FIELD(u16_t flags);
-  PACK_STRUCT_FIELD(struct ip_addr ciaddr);
-  PACK_STRUCT_FIELD(struct ip_addr yiaddr);
-  PACK_STRUCT_FIELD(struct ip_addr siaddr);
-  PACK_STRUCT_FIELD(struct ip_addr giaddr);
-#define DHCP_CHADDR_LEN 16U
-  PACK_STRUCT_FIELD(u8_t chaddr[DHCP_CHADDR_LEN]);
-#define DHCP_SNAME_LEN 64U
-  PACK_STRUCT_FIELD(u8_t sname[DHCP_SNAME_LEN]);
-#define DHCP_FILE_LEN 128U
-  PACK_STRUCT_FIELD(u8_t file[DHCP_FILE_LEN]);
-  PACK_STRUCT_FIELD(u32_t cookie);
-#define DHCP_MIN_OPTIONS_LEN 68U
-/** make sure user does not configure this too small */
-#if ((defined(DHCP_OPTIONS_LEN)) && (DHCP_OPTIONS_LEN < DHCP_MIN_OPTIONS_LEN))
-#  undef DHCP_OPTIONS_LEN
-#endif
-/** allow this to be configured in lwipopts.h, but not too small */
-#if (!defined(DHCP_OPTIONS_LEN))
-/** set this to be sufficient for your options in outgoing DHCP msgs */
-#  define DHCP_OPTIONS_LEN DHCP_MIN_OPTIONS_LEN
-#endif
-  PACK_STRUCT_FIELD(u8_t options[DHCP_OPTIONS_LEN]);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-/** start DHCP configuration */
-err_t dhcp_start(struct netif *netif);
-/** enforce early lease renewal (not needed normally)*/
-err_t dhcp_renew(struct netif *netif);
-/** release the DHCP lease, usually called before dhcp_stop()*/
-err_t dhcp_release(struct netif *netif);
-/** stop DHCP configuration */
-void dhcp_stop(struct netif *netif);
-/** inform server of our manual IP address */
-void dhcp_inform(struct netif *netif);
-
-/** if enabled, check whether the offered IP address is not in use, using ARP */
-#if DHCP_DOES_ARP_CHECK
-void dhcp_arp_reply(struct netif *netif, struct ip_addr *addr);
-#endif
-
-/** to be called every minute */
-void dhcp_coarse_tmr(void);
-/** to be called every half second */
-void dhcp_fine_tmr(void);
- 
-/** DHCP message item offsets and length */
-#define DHCP_MSG_OFS (UDP_DATA_OFS)  
-  #define DHCP_OP_OFS (DHCP_MSG_OFS + 0)
-  #define DHCP_HTYPE_OFS (DHCP_MSG_OFS + 1)
-  #define DHCP_HLEN_OFS (DHCP_MSG_OFS + 2)
-  #define DHCP_HOPS_OFS (DHCP_MSG_OFS + 3)
-  #define DHCP_XID_OFS (DHCP_MSG_OFS + 4)
-  #define DHCP_SECS_OFS (DHCP_MSG_OFS + 8)
-  #define DHCP_FLAGS_OFS (DHCP_MSG_OFS + 10)
-  #define DHCP_CIADDR_OFS (DHCP_MSG_OFS + 12)
-  #define DHCP_YIADDR_OFS (DHCP_MSG_OFS + 16)
-  #define DHCP_SIADDR_OFS (DHCP_MSG_OFS + 20)
-  #define DHCP_GIADDR_OFS (DHCP_MSG_OFS + 24)
-  #define DHCP_CHADDR_OFS (DHCP_MSG_OFS + 28)
-  #define DHCP_SNAME_OFS (DHCP_MSG_OFS + 44)
-  #define DHCP_FILE_OFS (DHCP_MSG_OFS + 108)
-#define DHCP_MSG_LEN 236
-
-#define DHCP_COOKIE_OFS (DHCP_MSG_OFS + DHCP_MSG_LEN)
-#define DHCP_OPTIONS_OFS (DHCP_MSG_OFS + DHCP_MSG_LEN + 4)
-
-#define DHCP_CLIENT_PORT 68  
-#define DHCP_SERVER_PORT 67
-
-/** DHCP client states */
-#define DHCP_REQUESTING 1
-#define DHCP_INIT 2
-#define DHCP_REBOOTING 3
-#define DHCP_REBINDING 4
-#define DHCP_RENEWING 5
-#define DHCP_SELECTING 6
-#define DHCP_INFORMING 7
-#define DHCP_CHECKING 8
-#define DHCP_PERMANENT 9
-#define DHCP_BOUND 10
-/** not yet implemented #define DHCP_RELEASING 11 */
-#define DHCP_BACKING_OFF 12
-#define DHCP_OFF 13
- 
-#define DHCP_BOOTREQUEST 1
-#define DHCP_BOOTREPLY 2
-
-#define DHCP_DISCOVER 1
-#define DHCP_OFFER 2
-#define DHCP_REQUEST 3
-#define DHCP_DECLINE 4
-#define DHCP_ACK 5
-#define DHCP_NAK 6
-#define DHCP_RELEASE 7
-#define DHCP_INFORM 8
-
-#define DHCP_HTYPE_ETH 1
-
-#define DHCP_HLEN_ETH 6
-
-#define DHCP_BROADCAST_FLAG 15
-#define DHCP_BROADCAST_MASK (1 << DHCP_FLAG_BROADCAST)
-
-/** BootP options */
-#define DHCP_OPTION_PAD 0
-#define DHCP_OPTION_SUBNET_MASK 1 /* RFC 2132 3.3 */
-#define DHCP_OPTION_ROUTER 3
-#define DHCP_OPTION_DNS_SERVER 6 
-#define DHCP_OPTION_HOSTNAME 12
-#define DHCP_OPTION_IP_TTL 23
-#define DHCP_OPTION_MTU 26
-#define DHCP_OPTION_BROADCAST 28
-#define DHCP_OPTION_TCP_TTL 37
-#define DHCP_OPTION_END 255
-
-/** DHCP options */
-#define DHCP_OPTION_REQUESTED_IP 50 /* RFC 2132 9.1, requested IP address */
-#define DHCP_OPTION_LEASE_TIME 51 /* RFC 2132 9.2, time in seconds, in 4 bytes */
-#define DHCP_OPTION_OVERLOAD 52 /* RFC2132 9.3, use file and/or sname field for options */
-
-#define DHCP_OPTION_MESSAGE_TYPE 53 /* RFC 2132 9.6, important for DHCP */
-#define DHCP_OPTION_MESSAGE_TYPE_LEN 1
-
-
-#define DHCP_OPTION_SERVER_ID 54 /* RFC 2132 9.7, server IP address */
-#define DHCP_OPTION_PARAMETER_REQUEST_LIST 55 /* RFC 2132 9.8, requested option types */
-
-#define DHCP_OPTION_MAX_MSG_SIZE 57 /* RFC 2132 9.10, message size accepted >= 576 */
-#define DHCP_OPTION_MAX_MSG_SIZE_LEN 2
-
-#define DHCP_OPTION_T1 58 /* T1 renewal time */
-#define DHCP_OPTION_T2 59 /* T2 rebinding time */
-#define DHCP_OPTION_CLIENT_ID 61
-#define DHCP_OPTION_TFTP_SERVERNAME 66
-#define DHCP_OPTION_BOOTFILE 67
-
-/** possible combinations of overloading the file and sname fields with options */
-#define DHCP_OVERLOAD_NONE 0
-#define DHCP_OVERLOAD_FILE 1
-#define DHCP_OVERLOAD_SNAME  2
-#define DHCP_OVERLOAD_SNAME_FILE 3
-
-#endif /*__LWIP_DHCP_H__*/
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/err.h b/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/err.h
deleted file mode 100644
index c92cb26d7..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/err.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_ERR_H__
-#define __LWIP_ERR_H__
-
-#include "lwip/opt.h"
-
-#include "arch/cc.h"
-
-typedef s8_t err_t;
-
-/* Definitions for error constants. */
-
-#define ERR_OK    0      /* No error, everything OK. */
-#define ERR_MEM  -1      /* Out of memory error.     */
-#define ERR_BUF  -2      /* Buffer error.            */
-
-
-#define ERR_ABRT -3      /* Connection aborted.      */
-#define ERR_RST  -4      /* Connection reset.        */
-#define ERR_CLSD -5      /* Connection closed.       */
-#define ERR_CONN -6      /* Not connected.           */
-
-#define ERR_VAL  -7      /* Illegal value.           */
-
-#define ERR_ARG  -8      /* Illegal argument.        */
-
-#define ERR_RTE  -9      /* Routing problem.         */
-
-#define ERR_USE  -10     /* Address in use.          */
-
-#define ERR_IF   -11     /* Low-level netif error    */
-#define ERR_ISCONN -12   /* Already connected.       */
-
-
-#ifdef LWIP_DEBUG
-extern char *lwip_strerr(err_t err);
-#else
-#define lwip_strerr(x) ""
-#endif /* LWIP_DEBUG */
-#endif /* __LWIP_ERR_H__ */
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/mem.h b/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/mem.h
deleted file mode 100644
index ee6fea7d8..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/mem.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_MEM_H__
-#define __LWIP_MEM_H__
-
-#include "lwip/opt.h"
-#include "lwip/arch.h"
-
-#if MEM_SIZE > 64000l
-typedef u32_t mem_size_t;
-#else
-typedef u16_t mem_size_t;
-#endif /* MEM_SIZE > 64000 */
-
-
-void mem_init(void);
-
-void *mem_malloc(mem_size_t size);
-void mem_free(void *mem);
-void *mem_realloc(void *mem, mem_size_t size);
-void *mem_reallocm(void *mem, mem_size_t size);
-
-#ifndef MEM_ALIGN_SIZE
-#define MEM_ALIGN_SIZE(size) (((size) + MEM_ALIGNMENT - 1) & ~(MEM_ALIGNMENT-1))
-#endif
-
-#ifndef MEM_ALIGN
-#define MEM_ALIGN(addr) ((void *)(((mem_ptr_t)(addr) + MEM_ALIGNMENT - 1) & ~(mem_ptr_t)(MEM_ALIGNMENT-1)))
-#endif
-
-#endif /* __LWIP_MEM_H__ */
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/memp.h b/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/memp.h
deleted file mode 100644
index 1cd46fa3f..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/memp.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-
-#ifndef __LWIP_MEMP_H__
-#define __LWIP_MEMP_H__
-
-#include "lwip/opt.h"
-
-typedef enum {
-  MEMP_PBUF,
-  MEMP_RAW_PCB,
-  MEMP_UDP_PCB,
-  MEMP_TCP_PCB,
-  MEMP_TCP_PCB_LISTEN,
-  MEMP_TCP_SEG,
-
-  MEMP_NETBUF,
-  MEMP_NETCONN,
-  MEMP_API_MSG,
-  MEMP_TCPIP_MSG,
-
-  MEMP_SYS_TIMEOUT,
-  
-  MEMP_MAX
-} memp_t;
-
-void memp_init(void);
-
-void *memp_malloc(memp_t type);
-void *memp_realloc(memp_t fromtype, memp_t totype, void *mem);
-void memp_free(memp_t type, void *mem);
-
-#endif /* __LWIP_MEMP_H__  */
-    
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/netif.h b/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/netif.h
deleted file mode 100644
index ff50c6f9c..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/netif.h
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_NETIF_H__
-#define __LWIP_NETIF_H__
-
-#include "lwip/opt.h"
-
-#include "lwip/err.h"
-
-#include "lwip/ip_addr.h"
-
-#include "lwip/inet.h"
-#include "lwip/pbuf.h"
-#if LWIP_DHCP
-#  include "lwip/dhcp.h"
-#endif
-
-/** must be the maximum of all used hardware address lengths
-    across all types of interfaces in use */
-#define NETIF_MAX_HWADDR_LEN 6U
-
-/** TODO: define the use (where, when, whom) of netif flags */
-
-/** whether the network interface is 'up'. this is
- * a software flag used to control whether this network
- * interface is enabled and processes traffic.
- */
-#define NETIF_FLAG_UP 0x1U
-/** if set, the netif has broadcast capability */
-#define NETIF_FLAG_BROADCAST 0x2U
-/** if set, the netif is one end of a point-to-point connection */
-#define NETIF_FLAG_POINTTOPOINT 0x4U
-/** if set, the interface is configured using DHCP */
-#define NETIF_FLAG_DHCP 0x08U
-/** if set, the interface has an active link
- *  (set by the network interface driver) */
-#define NETIF_FLAG_LINK_UP 0x10U
-
-/** Generic data structure used for all lwIP network interfaces.
- *  The following fields should be filled in by the initialization
- *  function for the device driver: hwaddr_len, hwaddr[], mtu, flags */
-
-struct netif {
-  /** pointer to next in linked list */
-  struct netif *next;
-
-  /** IP address configuration in network byte order */
-  struct ip_addr ip_addr;
-  struct ip_addr netmask;
-  struct ip_addr gw;
-
-  /** This function is called by the network device driver
-   *  to pass a packet up the TCP/IP stack. */
-  err_t (* input)(struct pbuf *p, struct netif *inp);
-  /** This function is called by the IP module when it wants
-   *  to send a packet on the interface. This function typically
-   *  first resolves the hardware address, then sends the packet. */
-  err_t (* output)(struct netif *netif, struct pbuf *p,
-       struct ip_addr *ipaddr);
-  /** This function is called by the ARP module when it wants
-   *  to send a packet on the interface. This function outputs
-   *  the pbuf as-is on the link medium. */
-  err_t (* linkoutput)(struct netif *netif, struct pbuf *p);
-  /** This field can be set by the device driver and could point
-   *  to state information for the device. */
-  void *state;
-#if LWIP_DHCP
-  /** the DHCP client state information for this netif */
-  struct dhcp *dhcp;
-#endif
-  /** number of bytes used in hwaddr */
-  u8_t hwaddr_len;
-  /** link level hardware address of this interface */
-  u8_t hwaddr[NETIF_MAX_HWADDR_LEN];
-  /** maximum transfer unit (in bytes) */
-  u16_t mtu;
-  /** flags (see NETIF_FLAG_ above) */
-  u8_t flags;
-  /** link type */
-  u8_t link_type;
-  /** descriptive abbreviation */
-  char name[2];
-  /** number of this interface */
-  u8_t num;
-};
-
-/** The list of network interfaces. */
-extern struct netif *netif_list;
-/** The default network interface. */
-extern struct netif *netif_default;
-
-/* netif_init() must be called first. */
-void netif_init(void);
-
-struct netif *netif_add(struct netif *netif, struct ip_addr *ipaddr, struct ip_addr *netmask,
-      struct ip_addr *gw,
-      void *state,
-      err_t (* init)(struct netif *netif),
-      err_t (* input)(struct pbuf *p, struct netif *netif));
-
-void
-netif_set_addr(struct netif *netif,struct ip_addr *ipaddr, struct ip_addr *netmask,
-    struct ip_addr *gw);
-void netif_remove(struct netif * netif);
-
-/* Returns a network interface given its name. The name is of the form
-   "et0", where the first two letters are the "name" field in the
-   netif structure, and the digit is in the num field in the same
-   structure. */
-struct netif *netif_find(char *name);
-
-void netif_set_default(struct netif *netif);
-
-void netif_set_ipaddr(struct netif *netif, struct ip_addr *ipaddr);
-void netif_set_netmask(struct netif *netif, struct ip_addr *netmast);
-void netif_set_gw(struct netif *netif, struct ip_addr *gw);
-void netif_set_up(struct netif *netif);
-void netif_set_down(struct netif *netif);
-u8_t netif_is_up(struct netif *netif);
-
-#endif /* __LWIP_NETIF_H__ */
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/opt.h b/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/opt.h
deleted file mode 100644
index 45636cb24..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/opt.h
+++ /dev/null
@@ -1,671 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_OPT_H__
-#define __LWIP_OPT_H__
-
-/* Include user defined options first */
-#include "lwipopts.h"
-#include "lwip/debug.h"
-
-/* Define default values for unconfigured parameters. */
-
-/* Platform specific locking */
-
-/*
- * enable SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection
- * for certain critical regions during buffer allocation, deallocation and memory
- * allocation and deallocation.
- */
-#ifndef SYS_LIGHTWEIGHT_PROT
-#define SYS_LIGHTWEIGHT_PROT            0
-#endif
-
-#ifndef NO_SYS
-#define NO_SYS                          0
-#endif
-/* ---------- Memory options ---------- */
-/* MEM_ALIGNMENT: should be set to the alignment of the CPU for which
-   lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4, 2
-   byte alignment -> define MEM_ALIGNMENT to 2. */
-
-#ifndef MEM_ALIGNMENT
-#define MEM_ALIGNMENT                   1
-#endif
-
-/* MEM_SIZE: the size of the heap memory. If the application will send
-a lot of data that needs to be copied, this should be set high. */
-#ifndef MEM_SIZE
-#define MEM_SIZE                        1600
-#endif
-
-#ifndef MEMP_SANITY_CHECK
-#define MEMP_SANITY_CHECK       0
-#endif
-
-/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application
-   sends a lot of data out of ROM (or other static memory), this
-   should be set high. */
-#ifndef MEMP_NUM_PBUF
-#define MEMP_NUM_PBUF                   16
-#endif
-
-/* Number of raw connection PCBs */
-#ifndef MEMP_NUM_RAW_PCB
-#define MEMP_NUM_RAW_PCB                4
-#endif
-
-/* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One
-   per active UDP "connection". */
-#ifndef MEMP_NUM_UDP_PCB
-#define MEMP_NUM_UDP_PCB                4
-#endif
-/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP
-   connections. */
-#ifndef MEMP_NUM_TCP_PCB
-#define MEMP_NUM_TCP_PCB                5
-#endif
-/* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP
-   connections. */
-#ifndef MEMP_NUM_TCP_PCB_LISTEN
-#define MEMP_NUM_TCP_PCB_LISTEN         8
-#endif
-/* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP
-   segments. */
-#ifndef MEMP_NUM_TCP_SEG
-#define MEMP_NUM_TCP_SEG                16
-#endif
-/* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active
-   timeouts. */
-#ifndef MEMP_NUM_SYS_TIMEOUT
-#define MEMP_NUM_SYS_TIMEOUT            3
-#endif
-
-/* The following four are used only with the sequential API and can be
-   set to 0 if the application only will use the raw API. */
-/* MEMP_NUM_NETBUF: the number of struct netbufs. */
-#ifndef MEMP_NUM_NETBUF
-#define MEMP_NUM_NETBUF                 2
-#endif
-/* MEMP_NUM_NETCONN: the number of struct netconns. */
-#ifndef MEMP_NUM_NETCONN
-#define MEMP_NUM_NETCONN                4
-#endif
-/* MEMP_NUM_APIMSG: the number of struct api_msg, used for
-   communication between the TCP/IP stack and the sequential
-   programs. */
-#ifndef MEMP_NUM_API_MSG
-#define MEMP_NUM_API_MSG                8
-#endif
-/* MEMP_NUM_TCPIPMSG: the number of struct tcpip_msg, which is used
-   for sequential API communication and incoming packets. Used in
-   src/api/tcpip.c. */
-#ifndef MEMP_NUM_TCPIP_MSG
-#define MEMP_NUM_TCPIP_MSG              8
-#endif
-
-/* ---------- Pbuf options ---------- */
-/* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */
-
-#ifndef PBUF_POOL_SIZE
-#define PBUF_POOL_SIZE                  16
-#endif
-
-/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */
-
-#ifndef PBUF_POOL_BUFSIZE
-#define PBUF_POOL_BUFSIZE               128
-#endif
-
-/* PBUF_LINK_HLEN: the number of bytes that should be allocated for a
-   link level header. Defaults to 14 for Ethernet. */
-
-#ifndef PBUF_LINK_HLEN
-#define PBUF_LINK_HLEN                  14
-#endif
-
-
-
-/* ---------- ARP options ---------- */
-
-/** Number of active hardware address, IP address pairs cached */
-#ifndef ARP_TABLE_SIZE
-#define ARP_TABLE_SIZE                  10
-#endif
-
-/**
- * If enabled, outgoing packets are queued during hardware address
- * resolution.
- *
- * This feature has not stabilized yet. Single-packet queueing is
- * believed to be stable, multi-packet queueing is believed to
- * clash with the TCP segment queueing.
- * 
- * As multi-packet-queueing is currently disabled, enabling this
- * _should_ work, but we need your testing feedback on lwip-users.
- *
- */
-#ifndef ARP_QUEUEING
-#define ARP_QUEUEING                    1
-#endif
-
-/* This option is deprecated */
-#ifdef ETHARP_QUEUE_FIRST
-#error ETHARP_QUEUE_FIRST option is deprecated. Remove it from your lwipopts.h.
-#endif
-
-/* This option is removed to comply with the ARP standard */
-#ifdef ETHARP_ALWAYS_INSERT
-#error ETHARP_ALWAYS_INSERT option is deprecated. Remove it from your lwipopts.h.
-#endif
-
-/* ---------- IP options ---------- */
-/* Define IP_FORWARD to 1 if you wish to have the ability to forward
-   IP packets across network interfaces. If you are going to run lwIP
-   on a device with only one network interface, define this to 0. */
-#ifndef IP_FORWARD
-#define IP_FORWARD                      0
-#endif
-
-/* If defined to 1, IP options are allowed (but not parsed). If
-   defined to 0, all packets with IP options are dropped. */
-#ifndef IP_OPTIONS
-#define IP_OPTIONS                      1
-#endif
-
-/** IP reassembly and segmentation. Even if they both deal with IP
- *  fragments, note that these are orthogonal, one dealing with incoming
- *  packets, the other with outgoing packets
- */
-
-/** Reassemble incoming fragmented IP packets */
-#ifndef IP_REASSEMBLY
-#define IP_REASSEMBLY                   1
-#endif
-
-/** Fragment outgoing IP packets if their size exceeds MTU */
-#ifndef IP_FRAG
-#define IP_FRAG                         1
-#endif
-
-/* ---------- ICMP options ---------- */
-
-#ifndef ICMP_TTL
-#define ICMP_TTL                        255
-#endif
-
-/* ---------- RAW options ---------- */
-
-#ifndef LWIP_RAW
-#define LWIP_RAW                        1
-#endif
-
-#ifndef RAW_TTL
-#define RAW_TTL                        255
-#endif
-
-/* ---------- DHCP options ---------- */
-
-#ifndef LWIP_DHCP
-#define LWIP_DHCP                       0
-#endif
-
-/* 1 if you want to do an ARP check on the offered address
-   (recommended). */
-#ifndef DHCP_DOES_ARP_CHECK
-#define DHCP_DOES_ARP_CHECK             1
-#endif
-
-/* ---------- UDP options ---------- */
-#ifndef LWIP_UDP
-#define LWIP_UDP                        1
-#endif
-
-#ifndef UDP_TTL
-#define UDP_TTL                         255
-#endif
-
-/* ---------- TCP options ---------- */
-#ifndef LWIP_TCP
-#define LWIP_TCP                        1
-#endif
-
-#ifndef TCP_TTL
-#define TCP_TTL                         255
-#endif
-
-#ifndef TCP_WND
-#define TCP_WND                         2048
-#endif 
-
-#ifndef TCP_MAXRTX
-#define TCP_MAXRTX                      12
-#endif
-
-#ifndef TCP_SYNMAXRTX
-#define TCP_SYNMAXRTX                   6
-#endif
-
-
-/* Controls if TCP should queue segments that arrive out of
-   order. Define to 0 if your device is low on memory. */
-#ifndef TCP_QUEUE_OOSEQ
-#define TCP_QUEUE_OOSEQ                 1
-#endif
-
-/* TCP Maximum segment size. */
-#ifndef TCP_MSS
-#define TCP_MSS                         128 /* A *very* conservative default. */
-#endif
-
-/* TCP sender buffer space (bytes). */
-#ifndef TCP_SND_BUF
-#define TCP_SND_BUF                     256
-#endif
-
-/* TCP sender buffer space (pbufs). This must be at least = 2 *
-   TCP_SND_BUF/TCP_MSS for things to work. */
-#ifndef TCP_SND_QUEUELEN
-#define TCP_SND_QUEUELEN                4 * TCP_SND_BUF/TCP_MSS
-#endif
-
-
-/* Maximum number of retransmissions of data segments. */
-
-/* Maximum number of retransmissions of SYN segments. */
-
-/* TCP writable space (bytes). This must be less than or equal
-   to TCP_SND_BUF. It is the amount of space which must be
-   available in the tcp snd_buf for select to return writable */
-#ifndef TCP_SNDLOWAT
-#define TCP_SNDLOWAT                    TCP_SND_BUF/2
-#endif
-
-/* Support loop interface (127.0.0.1) */
-#ifndef LWIP_HAVE_LOOPIF
-#define LWIP_HAVE_LOOPIF                0
-#endif
-
-#ifndef LWIP_EVENT_API
-#define LWIP_EVENT_API                  0
-#define LWIP_CALLBACK_API               1
-#else 
-#define LWIP_EVENT_API                  1
-#define LWIP_CALLBACK_API               0
-#endif 
-
-#ifndef LWIP_COMPAT_SOCKETS
-#define LWIP_COMPAT_SOCKETS             1
-#endif
-
-
-#ifndef TCPIP_THREAD_PRIO
-#define TCPIP_THREAD_PRIO               1
-#endif
-
-#ifndef SLIPIF_THREAD_PRIO
-#define SLIPIF_THREAD_PRIO              1
-#endif
-
-#ifndef PPP_THREAD_PRIO
-#define PPP_THREAD_PRIO                 1
-#endif
-
-#ifndef DEFAULT_THREAD_PRIO
-#define DEFAULT_THREAD_PRIO             1
-#endif
-
-
-/* ---------- Socket Options ---------- */
-/* Enable SO_REUSEADDR and SO_REUSEPORT options */ 
-#ifdef SO_REUSE
-/* I removed the lot since this was an ugly hack. It broke the raw-API.
-   It also came with many ugly goto's, Christiaan Simons. */
-#error "SO_REUSE currently unavailable, this was a hack"
-#endif                                                                        
-
-
-/* ---------- Statistics options ---------- */
-#ifndef LWIP_STATS
-#define LWIP_STATS                      1
-#endif
-
-#if LWIP_STATS
-
-#ifndef LWIP_STATS_DISPLAY
-#define LWIP_STATS_DISPLAY 0
-#endif
-
-#ifndef LINK_STATS
-#define LINK_STATS  1
-#endif
-
-#ifndef IP_STATS
-#define IP_STATS    1
-#endif
-
-#ifndef IPFRAG_STATS
-#define IPFRAG_STATS    1
-#endif
-
-#ifndef ICMP_STATS
-#define ICMP_STATS  1
-#endif
-
-#ifndef UDP_STATS
-#define UDP_STATS   1
-#endif
-
-#ifndef TCP_STATS
-#define TCP_STATS   1
-#endif
-
-#ifndef MEM_STATS
-#define MEM_STATS   1
-#endif
-
-#ifndef MEMP_STATS
-#define MEMP_STATS  1
-#endif
-
-#ifndef PBUF_STATS
-#define PBUF_STATS  1
-#endif
-
-#ifndef SYS_STATS
-#define SYS_STATS   1
-#endif
-
-#ifndef RAW_STATS
-#define RAW_STATS   0
-#endif
-
-#else
-
-#define LINK_STATS  0
-#define IP_STATS    0
-#define IPFRAG_STATS    0
-#define ICMP_STATS  0
-#define UDP_STATS   0
-#define TCP_STATS   0
-#define MEM_STATS   0
-#define MEMP_STATS  0
-#define PBUF_STATS  0
-#define SYS_STATS   0
-#define RAW_STATS   0
-#define LWIP_STATS_DISPLAY  0
-
-#endif /* LWIP_STATS */
-
-/* ---------- PPP options ---------- */
-
-#ifndef PPP_SUPPORT
-#define PPP_SUPPORT                     0      /* Set for PPP */
-#endif
-
-#if PPP_SUPPORT 
-
-#define NUM_PPP                         1      /* Max PPP sessions. */
-
-
-
-#ifndef PAP_SUPPORT
-#define PAP_SUPPORT                     0      /* Set for PAP. */
-#endif
-
-#ifndef CHAP_SUPPORT
-#define CHAP_SUPPORT                    0      /* Set for CHAP. */
-#endif
-
-#define MSCHAP_SUPPORT                  0      /* Set for MSCHAP (NOT FUNCTIONAL!) */
-#define CBCP_SUPPORT                    0      /* Set for CBCP (NOT FUNCTIONAL!) */
-#define CCP_SUPPORT                     0      /* Set for CCP (NOT FUNCTIONAL!) */
-
-#ifndef VJ_SUPPORT
-#define VJ_SUPPORT                      0      /* Set for VJ header compression. */
-#endif
-
-#ifndef MD5_SUPPORT
-#define MD5_SUPPORT                     0      /* Set for MD5 (see also CHAP) */
-#endif
-
-
-/*
- * Timeouts.
- */
-#define FSM_DEFTIMEOUT                  6       /* Timeout time in seconds */
-#define FSM_DEFMAXTERMREQS              2       /* Maximum Terminate-Request transmissions */
-#define FSM_DEFMAXCONFREQS              10      /* Maximum Configure-Request transmissions */
-#define FSM_DEFMAXNAKLOOPS              5       /* Maximum number of nak loops */
-
-#define UPAP_DEFTIMEOUT                 6       /* Timeout (seconds) for retransmitting req */
-#define UPAP_DEFREQTIME                 30      /* Time to wait for auth-req from peer */
-
-#define CHAP_DEFTIMEOUT                 6       /* Timeout time in seconds */
-#define CHAP_DEFTRANSMITS               10      /* max # times to send challenge */
-
-
-/* Interval in seconds between keepalive echo requests, 0 to disable. */
-#if 1
-#define LCP_ECHOINTERVAL                0
-#else
-#define LCP_ECHOINTERVAL                10
-#endif
-
-/* Number of unanswered echo requests before failure. */
-#define LCP_MAXECHOFAILS                3
-
-/* Max Xmit idle time (in jiffies) before resend flag char. */
-#define PPP_MAXIDLEFLAG                 100
-
-/*
- * Packet sizes
- *
- * Note - lcp shouldn't be allowed to negotiate stuff outside these
- *    limits.  See lcp.h in the pppd directory.
- * (XXX - these constants should simply be shared by lcp.c instead
- *    of living in lcp.h)
- */
-#define PPP_MTU                         1500     /* Default MTU (size of Info field) */
-#if 0
-#define PPP_MAXMTU  65535 - (PPP_HDRLEN + PPP_FCSLEN)
-#else
-#define PPP_MAXMTU                      1500 /* Largest MTU we allow */
-#endif
-#define PPP_MINMTU                      64
-#define PPP_MRU                         1500     /* default MRU = max length of info field */
-#define PPP_MAXMRU                      1500     /* Largest MRU we allow */
-#define PPP_DEFMRU                      296             /* Try for this */
-#define PPP_MINMRU                      128             /* No MRUs below this */
-
-
-#define MAXNAMELEN                      256     /* max length of hostname or name for auth */
-#define MAXSECRETLEN                    256     /* max length of password or secret */
-
-#endif /* PPP_SUPPORT */
-
-/* checksum options - set to zero for hardware checksum support */
-
-#ifndef CHECKSUM_GEN_IP
-#define CHECKSUM_GEN_IP                 1
-#endif
- 
-#ifndef CHECKSUM_GEN_UDP
-#define CHECKSUM_GEN_UDP                1
-#endif
- 
-#ifndef CHECKSUM_GEN_TCP
-#define CHECKSUM_GEN_TCP                1
-#endif
- 
-#ifndef CHECKSUM_CHECK_IP
-#define CHECKSUM_CHECK_IP               1
-#endif
- 
-#ifndef CHECKSUM_CHECK_UDP
-#define CHECKSUM_CHECK_UDP              1
-#endif
-
-#ifndef CHECKSUM_CHECK_TCP
-#define CHECKSUM_CHECK_TCP              1
-#endif
-
-/* Debugging options all default to off */
-
-#ifndef DBG_TYPES_ON
-#define DBG_TYPES_ON                    0
-#endif
-
-#ifndef ETHARP_DEBUG
-#define ETHARP_DEBUG                    DBG_OFF
-#endif
-
-#ifndef NETIF_DEBUG
-#define NETIF_DEBUG                     DBG_OFF
-#endif
-
-#ifndef PBUF_DEBUG
-#define PBUF_DEBUG                      DBG_OFF
-#endif
-
-#ifndef API_LIB_DEBUG
-#define API_LIB_DEBUG                   DBG_OFF
-#endif
-
-#ifndef API_MSG_DEBUG
-#define API_MSG_DEBUG                   DBG_OFF
-#endif
-
-#ifndef SOCKETS_DEBUG
-#define SOCKETS_DEBUG                   DBG_OFF
-#endif
-
-#ifndef ICMP_DEBUG
-#define ICMP_DEBUG                      DBG_OFF
-#endif
-
-#ifndef INET_DEBUG
-#define INET_DEBUG                      DBG_OFF
-#endif
-
-#ifndef IP_DEBUG
-#define IP_DEBUG                        DBG_OFF
-#endif
-
-#ifndef IP_REASS_DEBUG
-#define IP_REASS_DEBUG                  DBG_OFF
-#endif
-
-#ifndef RAW_DEBUG
-#define RAW_DEBUG                       DBG_OFF
-#endif
-
-#ifndef MEM_DEBUG
-#define MEM_DEBUG                       DBG_OFF
-#endif
-
-#ifndef MEMP_DEBUG
-#define MEMP_DEBUG                      DBG_OFF
-#endif
-
-#ifndef SYS_DEBUG
-#define SYS_DEBUG                       DBG_OFF
-#endif
-
-#ifndef TCP_DEBUG
-#define TCP_DEBUG                       DBG_OFF
-#endif
-
-#ifndef TCP_INPUT_DEBUG
-#define TCP_INPUT_DEBUG                 DBG_OFF
-#endif
-
-#ifndef TCP_FR_DEBUG
-#define TCP_FR_DEBUG                    DBG_OFF
-#endif
-
-#ifndef TCP_RTO_DEBUG
-#define TCP_RTO_DEBUG                   DBG_OFF
-#endif
-
-#ifndef TCP_REXMIT_DEBUG
-#define TCP_REXMIT_DEBUG                DBG_OFF
-#endif
-
-#ifndef TCP_CWND_DEBUG
-#define TCP_CWND_DEBUG                  DBG_OFF
-#endif
-
-#ifndef TCP_WND_DEBUG
-#define TCP_WND_DEBUG                   DBG_OFF
-#endif
-
-#ifndef TCP_OUTPUT_DEBUG
-#define TCP_OUTPUT_DEBUG                DBG_OFF
-#endif
-
-#ifndef TCP_RST_DEBUG
-#define TCP_RST_DEBUG                   DBG_OFF
-#endif
-
-#ifndef TCP_QLEN_DEBUG
-#define TCP_QLEN_DEBUG                  DBG_OFF
-#endif
-
-#ifndef UDP_DEBUG
-#define UDP_DEBUG                       DBG_OFF
-#endif
-
-#ifndef TCPIP_DEBUG
-#define TCPIP_DEBUG                     DBG_OFF
-#endif
-
-#ifndef PPP_DEBUG 
-#define PPP_DEBUG                       DBG_OFF
-#endif
-
-#ifndef SLIP_DEBUG 
-#define SLIP_DEBUG                      DBG_OFF
-#endif
-
-#ifndef DHCP_DEBUG 
-#define DHCP_DEBUG                      DBG_OFF
-#endif
-
-
-#ifndef DBG_MIN_LEVEL
-#define DBG_MIN_LEVEL                   DBG_LEVEL_OFF
-#endif
-
-#endif /* __LWIP_OPT_H__ */
-
-
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/pbuf.h b/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/pbuf.h
deleted file mode 100644
index 546aa3035..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/pbuf.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-
-#ifndef __LWIP_PBUF_H__
-#define __LWIP_PBUF_H__
-
-#include "arch/cc.h"
-
-
-#define PBUF_TRANSPORT_HLEN 20
-#define PBUF_IP_HLEN        20
-
-typedef enum {
-  PBUF_TRANSPORT,
-  PBUF_IP,
-  PBUF_LINK,
-  PBUF_RAW
-} pbuf_layer;
-
-typedef enum {
-  PBUF_RAM,
-  PBUF_ROM,
-  PBUF_REF,
-  PBUF_POOL
-} pbuf_flag;
-
-/* Definitions for the pbuf flag field. These are NOT the flags that
- * are passed to pbuf_alloc(). */
-#define PBUF_FLAG_RAM   0x00U    /* Flags that pbuf data is stored in RAM */
-#define PBUF_FLAG_ROM   0x01U    /* Flags that pbuf data is stored in ROM */
-#define PBUF_FLAG_POOL  0x02U    /* Flags that the pbuf comes from the pbuf pool */
-#define PBUF_FLAG_REF   0x04U    /* Flags thet the pbuf payload refers to RAM */
-
-/** indicates this packet was broadcast on the link */
-#define PBUF_FLAG_LINK_BROADCAST 0x80U
-
-struct pbuf {
-  /** next pbuf in singly linked pbuf chain */
-  struct pbuf *next;
-
-  /** pointer to the actual data in the buffer */
-  void *payload;
-  
-  /**
-   * total length of this buffer and all next buffers in chain
-   * belonging to the same packet.
-   *
-   * For non-queue packet chains this is the invariant:
-   * p->tot_len == p->len + (p->next? p->next->tot_len: 0)
-   */
-  u16_t tot_len;
-  
-  /** length of this buffer */
-  u16_t len;  
-
-  /** flags telling the type of pbuf, see PBUF_FLAG_ */
-  u16_t flags;
-  
-  /**
-   * the reference count always equals the number of pointers
-   * that refer to this pbuf. This can be pointers from an application,
-   * the stack itself, or pbuf->next pointers from a chain.
-   */
-  u16_t ref;
-  
-};
-
-void pbuf_init(void);
-
-struct pbuf *pbuf_alloc(pbuf_layer l, u16_t size, pbuf_flag flag);
-void pbuf_realloc(struct pbuf *p, u16_t size); 
-u8_t pbuf_header(struct pbuf *p, s16_t header_size);
-void pbuf_ref(struct pbuf *p);
-void pbuf_ref_chain(struct pbuf *p);
-u8_t pbuf_free(struct pbuf *p);
-u8_t pbuf_clen(struct pbuf *p);  
-void pbuf_cat(struct pbuf *h, struct pbuf *t);
-void pbuf_chain(struct pbuf *h, struct pbuf *t);
-struct pbuf *pbuf_take(struct pbuf *f);
-struct pbuf *pbuf_dechain(struct pbuf *p);
-void pbuf_queue(struct pbuf *p, struct pbuf *n);
-struct pbuf * pbuf_dequeue(struct pbuf *p);
-
-#endif /* __LWIP_PBUF_H__ */
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/raw.h b/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/raw.h
deleted file mode 100644
index 6f7a98717..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/raw.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_RAW_H__
-#define __LWIP_RAW_H__
-
-#include "lwip/arch.h"
-
-#include "lwip/pbuf.h"
-#include "lwip/inet.h"
-#include "lwip/ip.h"
-
-struct raw_pcb {
-/* Common members of all PCB types */
-  IP_PCB;
-
-  struct raw_pcb *next;
-
-  u16_t protocol;
-
-  u8_t (* recv)(void *arg, struct raw_pcb *pcb, struct pbuf *p,
-    struct ip_addr *addr);
-  void *recv_arg;
-};
-
-/* The following functions is the application layer interface to the
-   RAW code. */
-struct raw_pcb * raw_new        (u16_t proto);
-void             raw_remove     (struct raw_pcb *pcb);
-err_t            raw_bind       (struct raw_pcb *pcb, struct ip_addr *ipaddr);
-err_t            raw_connect    (struct raw_pcb *pcb, struct ip_addr *ipaddr);
-
-void             raw_recv       (struct raw_pcb *pcb,
-                                 u8_t (* recv)(void *arg, struct raw_pcb *pcb,
-                                              struct pbuf *p,
-                                              struct ip_addr *addr),
-                                 void *recv_arg);
-err_t            raw_sendto    (struct raw_pcb *pcb, struct pbuf *p, struct ip_addr *ipaddr);
-err_t            raw_send       (struct raw_pcb *pcb, struct pbuf *p);
-
-/* The following functions are the lower layer interface to RAW. */
-u8_t              raw_input      (struct pbuf *p, struct netif *inp);
-void             raw_init       (void);
-
-
-#endif /* __LWIP_RAW_H__ */
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/sio.h b/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/sio.h
deleted file mode 100644
index 8a37aa35a..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/sio.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- */
-
-/*
- * This is the interface to the platform specific serial IO module
- * It needs to be implemented by those platforms which need SLIP or PPP
- */
-
-#include "arch/cc.h"
-
-#ifndef __sio_fd_t_defined
-typedef void * sio_fd_t;
-#endif
-
-#ifndef sio_open
-sio_fd_t sio_open(u8_t);
-#endif
-
-#ifndef sio_send
-void sio_send(u8_t, sio_fd_t);
-#endif
-
-#ifndef sio_recv
-u8_t sio_recv(sio_fd_t);
-#endif
-
-#ifndef sio_read
-u32_t sio_read(sio_fd_t, u8_t *, u32_t);
-#endif
-
-#ifndef sio_write
-u32_t sio_write(sio_fd_t, u8_t *, u32_t);
-#endif
-
-#ifndef sio_read_abort
-void sio_read_abort(sio_fd_t);
-#endif
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/snmp.h b/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/snmp.h
deleted file mode 100644
index 7d160aaa4..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/snmp.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * Copyright (c) 2001, 2002 Leon Woestenberg 
- * Copyright (c) 2001, 2002 Axon Digital Design B.V., The Netherlands.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Leon Woestenberg 
- *
- */
-#ifndef __LWIP_SNMP_H__
-#define __LWIP_SNMP_H__
-
-#include "lwip/opt.h"
-
-/* SNMP support available? */
-#if defined(LWIP_SNMP) && (LWIP_SNMP > 0)
-
-/* network interface */
-void snmp_add_ifinoctets(unsigned long value); 
-void snmp_inc_ifinucastpkts(void);
-void snmp_inc_ifinnucastpkts(void);
-void snmp_inc_ifindiscards(void);
-void snmp_add_ifoutoctets(unsigned long value);
-void snmp_inc_ifoutucastpkts(void);
-void snmp_inc_ifoutnucastpkts(void);
-void snmp_inc_ifoutdiscards(void);
-
-/* IP */
-void snmp_inc_ipinreceives(void);
-void snmp_inc_ipindelivers(void);
-void snmp_inc_ipindiscards(void);
-void snmp_inc_ipoutdiscards(void);
-void snmp_inc_ipoutrequests(void);
-void snmp_inc_ipunknownprotos(void);
-void snmp_inc_ipnoroutes(void);
-void snmp_inc_ipforwdatagrams(void);
-
-/* ICMP */
-void snmp_inc_icmpinmsgs(void);
-void snmp_inc_icmpinerrors(void);
-void snmp_inc_icmpindestunreachs(void);
-void snmp_inc_icmpintimeexcds(void);
-void snmp_inc_icmpinparmprobs(void);
-void snmp_inc_icmpinsrcquenchs(void);
-void snmp_inc_icmpinredirects(void);
-void snmp_inc_icmpinechos(void);
-void snmp_inc_icmpinechoreps(void);
-void snmp_inc_icmpintimestamps(void);
-void snmp_inc_icmpintimestampreps(void);
-void snmp_inc_icmpinaddrmasks(void);
-void snmp_inc_icmpinaddrmaskreps(void);
-void snmp_inc_icmpoutmsgs(void);
-void snmp_inc_icmpouterrors(void);
-void snmp_inc_icmpoutdestunreachs(void);
-void snmp_inc_icmpouttimeexcds(void);
-void snmp_inc_icmpoutparmprobs(void);
-void snmp_inc_icmpoutsrcquenchs(void);
-void snmp_inc_icmpoutredirects(void); 
-void snmp_inc_icmpoutechos(void);
-void snmp_inc_icmpoutechoreps(void);
-void snmp_inc_icmpouttimestamps(void);
-void snmp_inc_icmpouttimestampreps(void);
-void snmp_inc_icmpoutaddrmasks(void);
-void snmp_inc_icmpoutaddrmaskreps(void);
-
-/* TCP */
-void snmp_inc_tcpactiveopens(void);
-void snmp_inc_tcppassiveopens(void);
-void snmp_inc_tcpattemptfails(void);
-void snmp_inc_tcpestabresets(void);
-void snmp_inc_tcpcurrestab(void);
-void snmp_inc_tcpinsegs(void);
-void snmp_inc_tcpoutsegs(void);
-void snmp_inc_tcpretranssegs(void);
-void snmp_inc_tcpinerrs(void);
-void snmp_inc_tcpoutrsts(void);
-
-/* UDP */
-void snmp_inc_udpindatagrams(void);
-void snmp_inc_udpnoports(void);
-void snmp_inc_udpinerrors(void);
-void snmp_inc_udpoutdatagrams(void);
-
-/* LWIP_SNMP support not available */
-/* define everything to be empty */
-#else
-
-/* network interface */
-#define snmp_add_ifinoctets(value) 
-#define snmp_inc_ifinucastpkts()
-#define snmp_inc_ifinnucastpkts()
-#define snmp_inc_ifindiscards()
-#define snmp_add_ifoutoctets(value)
-#define snmp_inc_ifoutucastpkts()
-#define snmp_inc_ifoutnucastpkts()
-#define snmp_inc_ifoutdiscards()
-
-/* IP */
-#define snmp_inc_ipinreceives()
-#define snmp_inc_ipindelivers()
-#define snmp_inc_ipindiscards()
-#define snmp_inc_ipoutdiscards()
-#define snmp_inc_ipoutrequests()
-#define snmp_inc_ipunknownprotos()
-#define snmp_inc_ipnoroutes()
-#define snmp_inc_ipforwdatagrams()
-
-/* ICMP */
-#define snmp_inc_icmpinmsgs()
-#define snmp_inc_icmpinerrors() 
-#define snmp_inc_icmpindestunreachs() 
-#define snmp_inc_icmpintimeexcds()
-#define snmp_inc_icmpinparmprobs() 
-#define snmp_inc_icmpinsrcquenchs() 
-#define snmp_inc_icmpinredirects() 
-#define snmp_inc_icmpinechos() 
-#define snmp_inc_icmpinechoreps()
-#define snmp_inc_icmpintimestamps() 
-#define snmp_inc_icmpintimestampreps()
-#define snmp_inc_icmpinaddrmasks()
-#define snmp_inc_icmpinaddrmaskreps()
-#define snmp_inc_icmpoutmsgs()
-#define snmp_inc_icmpouterrors()
-#define snmp_inc_icmpoutdestunreachs() 
-#define snmp_inc_icmpouttimeexcds() 
-#define snmp_inc_icmpoutparmprobs()
-#define snmp_inc_icmpoutsrcquenchs()
-#define snmp_inc_icmpoutredirects() 
-#define snmp_inc_icmpoutechos() 
-#define snmp_inc_icmpoutechoreps()
-#define snmp_inc_icmpouttimestamps()
-#define snmp_inc_icmpouttimestampreps()
-#define snmp_inc_icmpoutaddrmasks()
-#define snmp_inc_icmpoutaddrmaskreps()
-/* TCP */
-#define snmp_inc_tcpactiveopens()
-#define snmp_inc_tcppassiveopens()
-#define snmp_inc_tcpattemptfails()
-#define snmp_inc_tcpestabresets()
-#define snmp_inc_tcpcurrestab()
-#define snmp_inc_tcpinsegs()
-#define snmp_inc_tcpoutsegs()
-#define snmp_inc_tcpretranssegs()
-#define snmp_inc_tcpinerrs()
-#define snmp_inc_tcpoutrsts()
-
-/* UDP */
-#define snmp_inc_udpindatagrams()
-#define snmp_inc_udpnoports()
-#define snmp_inc_udpinerrors()
-#define snmp_inc_udpoutdatagrams()
-
-#endif
-
-#endif /* __LWIP_SNMP_H__ */
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/sockets.h b/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/sockets.h
deleted file mode 100644
index d5f8ccf74..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/sockets.h
+++ /dev/null
@@ -1,271 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-
-
-#ifndef __LWIP_SOCKETS_H__
-#define __LWIP_SOCKETS_H__
-#include "lwip/ip_addr.h"
-
-struct sockaddr_in {
-  u8_t sin_len;
-  u8_t sin_family;
-  u16_t sin_port;
-  struct in_addr sin_addr;
-  char sin_zero[8];
-};
-
-struct sockaddr {
-  u8_t sa_len;
-  u8_t sa_family;
-  char sa_data[14];
-};
-
-#ifndef socklen_t
-#  define socklen_t int
-#endif
-
-
-#define SOCK_STREAM     1
-#define SOCK_DGRAM      2
-#define SOCK_RAW        3
-
-/*
- * Option flags per-socket.
- */
-#define  SO_DEBUG  0x0001    /* turn on debugging info recording */
-#define  SO_ACCEPTCONN  0x0002    /* socket has had listen() */
-#define  SO_REUSEADDR  0x0004    /* allow local address reuse */
-#define  SO_KEEPALIVE  0x0008    /* keep connections alive */
-#define  SO_DONTROUTE  0x0010    /* just use interface addresses */
-#define  SO_BROADCAST  0x0020    /* permit sending of broadcast msgs */
-#define  SO_USELOOPBACK  0x0040    /* bypass hardware when possible */
-#define  SO_LINGER  0x0080    /* linger on close if data present */
-#define  SO_OOBINLINE  0x0100    /* leave received OOB data in line */
-#define	 SO_REUSEPORT	0x0200		/* allow local address & port reuse */
-
-#define SO_DONTLINGER   (int)(~SO_LINGER)
-
-/*
- * Additional options, not kept in so_options.
- */
-#define SO_SNDBUF  0x1001    /* send buffer size */
-#define SO_RCVBUF  0x1002    /* receive buffer size */
-#define SO_SNDLOWAT  0x1003    /* send low-water mark */
-#define SO_RCVLOWAT  0x1004    /* receive low-water mark */
-#define SO_SNDTIMEO  0x1005    /* send timeout */
-#define SO_RCVTIMEO  0x1006    /* receive timeout */
-#define  SO_ERROR  0x1007    /* get error status and clear */
-#define  SO_TYPE    0x1008    /* get socket type */
-
-
-
-/*
- * Structure used for manipulating linger option.
- */
-struct linger {
-       int l_onoff;                /* option on/off */
-       int l_linger;               /* linger time */
-};
-
-/*
- * Level number for (get/set)sockopt() to apply to socket itself.
- */
-#define  SOL_SOCKET  0xfff    /* options for socket level */
-
-
-#define AF_UNSPEC       0
-#define AF_INET         2
-#define PF_INET         AF_INET
-#define PF_UNSPEC       AF_UNSPEC
-
-#define IPPROTO_IP      0
-#define IPPROTO_TCP     6
-#define IPPROTO_UDP     17
-
-#define INADDR_ANY      0
-#define INADDR_BROADCAST 0xffffffff
-
-/* Flags we can use with send and recv. */
-#define MSG_DONTWAIT    0x40            /* Nonblocking i/o for this operation only */
-
-
-/*
- * Options for level IPPROTO_IP
- */
-#define IP_TOS       1
-#define IP_TTL       2
-
-
-#define IPTOS_TOS_MASK          0x1E
-#define IPTOS_TOS(tos)          ((tos) & IPTOS_TOS_MASK)
-#define IPTOS_LOWDELAY          0x10
-#define IPTOS_THROUGHPUT        0x08
-#define IPTOS_RELIABILITY       0x04
-#define IPTOS_LOWCOST           0x02
-#define IPTOS_MINCOST           IPTOS_LOWCOST
-
-/*
- * Definitions for IP precedence (also in ip_tos) (hopefully unused)
- */
-#define IPTOS_PREC_MASK                 0xe0
-#define IPTOS_PREC(tos)                ((tos) & IPTOS_PREC_MASK)
-#define IPTOS_PREC_NETCONTROL           0xe0
-#define IPTOS_PREC_INTERNETCONTROL      0xc0
-#define IPTOS_PREC_CRITIC_ECP           0xa0
-#define IPTOS_PREC_FLASHOVERRIDE        0x80
-#define IPTOS_PREC_FLASH                0x60
-#define IPTOS_PREC_IMMEDIATE            0x40
-#define IPTOS_PREC_PRIORITY             0x20
-#define IPTOS_PREC_ROUTINE              0x00
-
-
-/*
- * Commands for ioctlsocket(),  taken from the BSD file fcntl.h.
- *
- *
- * Ioctl's have the command encoded in the lower word,
- * and the size of any in or out parameters in the upper
- * word.  The high 2 bits of the upper word are used
- * to encode the in/out status of the parameter; for now
- * we restrict parameters to at most 128 bytes.
- */
-#if !defined(FIONREAD) || !defined(FIONBIO)
-#define IOCPARM_MASK    0x7f            /* parameters must be < 128 bytes */
-#define IOC_VOID        0x20000000      /* no parameters */
-#define IOC_OUT         0x40000000      /* copy out parameters */
-#define IOC_IN          0x80000000      /* copy in parameters */
-#define IOC_INOUT       (IOC_IN|IOC_OUT)
-                                        /* 0x20000000 distinguishes new &
-                                           old ioctl's */
-#define _IO(x,y)        (IOC_VOID|((x)<<8)|(y))
-
-#define _IOR(x,y,t)     (IOC_OUT|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y))
-
-#define _IOW(x,y,t)     (IOC_IN|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y))
-#endif
-
-#ifndef FIONREAD
-#define FIONREAD    _IOR('f', 127, unsigned long) /* get # bytes to read */
-#endif
-#ifndef FIONBIO
-#define FIONBIO     _IOW('f', 126, unsigned long) /* set/clear non-blocking i/o */
-#endif
-
-/* Socket I/O Controls */
-#ifndef SIOCSHIWAT
-#define SIOCSHIWAT  _IOW('s',  0, unsigned long)  /* set high watermark */
-#define SIOCGHIWAT  _IOR('s',  1, unsigned long)  /* get high watermark */
-#define SIOCSLOWAT  _IOW('s',  2, unsigned long)  /* set low watermark */
-#define SIOCGLOWAT  _IOR('s',  3, unsigned long)  /* get low watermark */
-#define SIOCATMARK  _IOR('s',  7, unsigned long)  /* at oob mark? */
-#endif
-
-#ifndef O_NONBLOCK
-#define O_NONBLOCK    04000U
-#endif
-
-#ifndef FD_SET
-  #undef  FD_SETSIZE
-  #define FD_SETSIZE    16
-  #define FD_SET(n, p)  ((p)->fd_bits[(n)/8] |=  (1 << ((n) & 7)))
-  #define FD_CLR(n, p)  ((p)->fd_bits[(n)/8] &= ~(1 << ((n) & 7)))
-  #define FD_ISSET(n,p) ((p)->fd_bits[(n)/8] &   (1 << ((n) & 7)))
-  #define FD_ZERO(p)    memset((void*)(p),0,sizeof(*(p)))
-
-  typedef struct fd_set {
-          unsigned char fd_bits [(FD_SETSIZE+7)/8];
-        } fd_set;
-
-/* 
- * only define this in sockets.c so it does not interfere
- * with other projects namespaces where timeval is present
- */ 
-#ifndef LWIP_TIMEVAL_PRIVATE
-#define LWIP_TIMEVAL_PRIVATE 1
-#endif
-
-#if LWIP_TIMEVAL_PRIVATE
-  struct timeval {
-    long    tv_sec;         /* seconds */
-    long    tv_usec;        /* and microseconds */
-  };
-#endif
-
-#endif
-
-int lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen);
-int lwip_bind(int s, struct sockaddr *name, socklen_t namelen);
-int lwip_shutdown(int s, int how);
-int lwip_getpeername (int s, struct sockaddr *name, socklen_t *namelen);
-int lwip_getsockname (int s, struct sockaddr *name, socklen_t *namelen);
-int lwip_getsockopt (int s, int level, int optname, void *optval, socklen_t *optlen);
-int lwip_setsockopt (int s, int level, int optname, const void *optval, socklen_t optlen);
-int lwip_close(int s);
-int lwip_connect(int s, struct sockaddr *name, socklen_t namelen);
-int lwip_listen(int s, int backlog);
-int lwip_recv(int s, void *mem, int len, unsigned int flags);
-int lwip_read(int s, void *mem, int len);
-int lwip_recvfrom(int s, void *mem, int len, unsigned int flags,
-      struct sockaddr *from, socklen_t *fromlen);
-int lwip_send(int s, void *dataptr, int size, unsigned int flags);
-int lwip_sendto(int s, void *dataptr, int size, unsigned int flags,
-    struct sockaddr *to, socklen_t tolen);
-int lwip_socket(int domain, int type, int protocol);
-int lwip_write(int s, void *dataptr, int size);
-int lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset,
-                struct timeval *timeout);
-int lwip_ioctl(int s, long cmd, void *argp);
-
-#if LWIP_COMPAT_SOCKETS
-#define accept(a,b,c)         lwip_accept(a,b,c)
-#define bind(a,b,c)           lwip_bind(a,b,c)
-#define shutdown(a,b)         lwip_shutdown(a,b)
-#define close(s)              lwip_close(s)
-#define connect(a,b,c)        lwip_connect(a,b,c)
-#define getsockname(a,b,c)    lwip_getsockname(a,b,c)
-#define getpeername(a,b,c)    lwip_getpeername(a,b,c)
-#define setsockopt(a,b,c,d,e) lwip_setsockopt(a,b,c,d,e)
-#define getsockopt(a,b,c,d,e) lwip_getsockopt(a,b,c,d,e)
-#define listen(a,b)           lwip_listen(a,b)
-#define recv(a,b,c,d)         lwip_recv(a,b,c,d)
-#define read(a,b,c)           lwip_read(a,b,c)
-#define recvfrom(a,b,c,d,e,f) lwip_recvfrom(a,b,c,d,e,f)
-#define send(a,b,c,d)         lwip_send(a,b,c,d)
-#define sendto(a,b,c,d,e,f)   lwip_sendto(a,b,c,d,e,f)
-#define socket(a,b,c)         lwip_socket(a,b,c)
-#define write(a,b,c)          lwip_write(a,b,c)
-#define select(a,b,c,d,e)     lwip_select(a,b,c,d,e)
-#define ioctlsocket(a,b,c)    lwip_ioctl(a,b,c)
-#endif /* LWIP_COMPAT_SOCKETS */
-
-#endif /* __LWIP_SOCKETS_H__ */
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/stats.h b/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/stats.h
deleted file mode 100644
index 71acfd068..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/stats.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_STATS_H__
-#define __LWIP_STATS_H__
-
-#include "lwip/opt.h"
-#include "arch/cc.h"
-
-#include "lwip/mem.h"
-#include "lwip/memp.h"
-
-#if LWIP_STATS
-
-struct stats_proto {
-  u16_t xmit;    /* Transmitted packets. */
-  u16_t rexmit;  /* Retransmitted packets. */
-  u16_t recv;    /* Received packets. */
-  u16_t fw;      /* Forwarded packets. */
-  u16_t drop;    /* Dropped packets. */
-  u16_t chkerr;  /* Checksum error. */
-  u16_t lenerr;  /* Invalid length error. */
-  u16_t memerr;  /* Out of memory error. */
-  u16_t rterr;   /* Routing error. */
-  u16_t proterr; /* Protocol error. */
-  u16_t opterr;  /* Error in options. */
-  u16_t err;     /* Misc error. */
-  u16_t cachehit;
-};
-
-struct stats_mem {
-  mem_size_t avail;
-  mem_size_t used;
-  mem_size_t max;  
-  mem_size_t err;
-};
-
-struct stats_pbuf {
-  u16_t avail;
-  u16_t used;
-  u16_t max;  
-  u16_t err;
-
-  u16_t alloc_locked;
-  u16_t refresh_locked;
-};
-
-struct stats_syselem {
-  u16_t used;
-  u16_t max;
-  u16_t err;
-};
-
-struct stats_sys {
-  struct stats_syselem sem;
-  struct stats_syselem mbox;
-};
-
-struct stats_ {
-  struct stats_proto link;
-  struct stats_proto ip_frag;
-  struct stats_proto ip;
-  struct stats_proto icmp;
-  struct stats_proto udp;
-  struct stats_proto tcp;
-  struct stats_pbuf pbuf;
-  struct stats_mem mem;
-  struct stats_mem memp[MEMP_MAX];
-  struct stats_sys sys;
-};
-
-extern struct stats_ lwip_stats;
-
-
-void stats_init(void);
-
-#define STATS_INC(x) ++lwip_stats.x
-#else
-#define stats_init()
-#define STATS_INC(x)
-#endif /* LWIP_STATS */
-
-#if TCP_STATS
-#define TCP_STATS_INC(x) STATS_INC(x)
-#else
-#define TCP_STATS_INC(x)
-#endif
-
-#if UDP_STATS
-#define UDP_STATS_INC(x) STATS_INC(x)
-#else
-#define UDP_STATS_INC(x)
-#endif
-
-#if ICMP_STATS
-#define ICMP_STATS_INC(x) STATS_INC(x)
-#else
-#define ICMP_STATS_INC(x)
-#endif
-
-#if IP_STATS
-#define IP_STATS_INC(x) STATS_INC(x)
-#else
-#define IP_STATS_INC(x)
-#endif
-
-#if IPFRAG_STATS
-#define IPFRAG_STATS_INC(x) STATS_INC(x)
-#else
-#define IPFRAG_STATS_INC(x)
-#endif
-
-#if LINK_STATS
-#define LINK_STATS_INC(x) STATS_INC(x)
-#else
-#define LINK_STATS_INC(x)
-#endif
-
-/* Display of statistics */
-#if LWIP_STATS_DISPLAY
-void stats_display(void);
-#else
-#define stats_display()
-#endif
-
-#endif /* __LWIP_STATS_H__ */
-
-
-
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/sys.h b/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/sys.h
deleted file mode 100644
index 68926e954..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/sys.h
+++ /dev/null
@@ -1,183 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_SYS_H__
-#define __LWIP_SYS_H__
-
-#include "arch/cc.h"
-
-#include "lwip/opt.h"
-
-
-#if NO_SYS
-
-/* For a totally minimal and standalone system, we provide null
-   definitions of the sys_ functions. */
-typedef u8_t sys_sem_t;
-typedef u8_t sys_mbox_t;
-struct sys_timeout {u8_t dummy;};
-
-#define sys_init()
-#define sys_timeout(m,h,a)
-#define sys_untimeout(m,a)
-#define sys_sem_new(c) c
-#define sys_sem_signal(s)
-#define sys_sem_wait(s)
-#define sys_sem_free(s)
-#define sys_mbox_new() 0
-#define sys_mbox_fetch(m,d)
-#define sys_mbox_post(m,d)
-#define sys_mbox_free(m)
-
-#define sys_thread_new(t,a,p)
-
-#else /* NO_SYS */
-
-#include "arch/sys_arch.h"
-
-/** Return code for timeouts from sys_arch_mbox_fetch and sys_arch_sem_wait */
-#define SYS_ARCH_TIMEOUT 0xffffffff
-
-typedef void (* sys_timeout_handler)(void *arg);
-
-struct sys_timeout {
-  struct sys_timeout *next;
-  u32_t time;
-  sys_timeout_handler h;
-  void *arg;
-};
-
-struct sys_timeouts {
-  struct sys_timeout *next;
-};
-
-/* sys_init() must be called before anthing else. */
-void sys_init(void);
-
-/*
- * sys_timeout():
- *
- * Schedule a timeout a specified amount of milliseconds in the
- * future. When the timeout occurs, the specified timeout handler will
- * be called. The handler will be passed the "arg" argument when
- * called.
- *
- */
-void sys_timeout(u32_t msecs, sys_timeout_handler h, void *arg);
-void sys_untimeout(sys_timeout_handler h, void *arg);
-struct sys_timeouts *sys_arch_timeouts(void);
-
-/* Semaphore functions. */
-sys_sem_t sys_sem_new(u8_t count);
-void sys_sem_signal(sys_sem_t sem);
-u32_t sys_arch_sem_wait(sys_sem_t sem, u32_t timeout);
-void sys_sem_free(sys_sem_t sem);
-void sys_sem_wait(sys_sem_t sem);
-int sys_sem_wait_timeout(sys_sem_t sem, u32_t timeout);
-
-/* Time functions. */
-#ifndef sys_msleep
-void sys_msleep(u32_t ms); /* only has a (close to) 1 jiffy resolution. */
-#endif
-#ifndef sys_jiffies
-u32_t sys_jiffies(void); /* since power up. */
-#endif
-
-/* Mailbox functions. */
-sys_mbox_t sys_mbox_new(void);
-void sys_mbox_post(sys_mbox_t mbox, void *msg);
-u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout);
-void sys_mbox_free(sys_mbox_t mbox);
-void sys_mbox_fetch(sys_mbox_t mbox, void **msg);
-
-
-/* Thread functions. */
-sys_thread_t sys_thread_new(void (* thread)(void *arg), void *arg, int prio);
-
-/* The following functions are used only in Unix code, and
-   can be omitted when porting the stack. */
-/* Returns the current time in microseconds. */
-unsigned long sys_now(void);
-
-#endif /* NO_SYS */
-
-/* Critical Region Protection */
-/* These functions must be implemented in the sys_arch.c file.
-   In some implementations they can provide a more light-weight protection
-   mechanism than using semaphores. Otherwise semaphores can be used for
-   implementation */
-#ifndef SYS_ARCH_PROTECT
-/** SYS_LIGHTWEIGHT_PROT
- * define SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection
- * for certain critical regions during buffer allocation, deallocation and memory
- * allocation and deallocation.
- */
-#if SYS_LIGHTWEIGHT_PROT
-
-/** SYS_ARCH_DECL_PROTECT
- * declare a protection variable. This macro will default to defining a variable of
- * type sys_prot_t. If a particular port needs a different implementation, then
- * this macro may be defined in sys_arch.h.
- */
-#define SYS_ARCH_DECL_PROTECT(lev) sys_prot_t lev
-/** SYS_ARCH_PROTECT
- * Perform a "fast" protect. This could be implemented by
- * disabling interrupts for an embedded system or by using a semaphore or
- * mutex. The implementation should allow calling SYS_ARCH_PROTECT when
- * already protected. The old protection level is returned in the variable
- * "lev". This macro will default to calling the sys_arch_protect() function
- * which should be implemented in sys_arch.c. If a particular port needs a
- * different implementation, then this macro may be defined in sys_arch.h
- */
-#define SYS_ARCH_PROTECT(lev) lev = sys_arch_protect()
-/** SYS_ARCH_UNPROTECT
- * Perform a "fast" set of the protection level to "lev". This could be
- * implemented by setting the interrupt level to "lev" within the MACRO or by
- * using a semaphore or mutex.  This macro will default to calling the
- * sys_arch_unprotect() function which should be implemented in
- * sys_arch.c. If a particular port needs a different implementation, then
- * this macro may be defined in sys_arch.h
- */
-#define SYS_ARCH_UNPROTECT(lev) sys_arch_unprotect(lev)
-sys_prot_t sys_arch_protect(void);
-void sys_arch_unprotect(sys_prot_t pval);
-
-#else
-
-#define SYS_ARCH_DECL_PROTECT(lev)
-#define SYS_ARCH_PROTECT(lev)
-#define SYS_ARCH_UNPROTECT(lev)
-
-#endif /* SYS_LIGHTWEIGHT_PROT */
-
-#endif /* SYS_ARCH_PROTECT */
-
-#endif /* __LWIP_SYS_H__ */
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/tcp.h b/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/tcp.h
deleted file mode 100644
index 5f968c684..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/tcp.h
+++ /dev/null
@@ -1,531 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_TCP_H__
-#define __LWIP_TCP_H__
-
-#include "lwip/sys.h"
-#include "lwip/mem.h"
-
-#include "lwip/pbuf.h"
-#include "lwip/opt.h"
-#include "lwip/ip.h"
-#include "lwip/icmp.h"
-
-#include "lwip/err.h"
-
-struct tcp_pcb;
-
-/* Functions for interfacing with TCP: */
-
-/* Lower layer interface to TCP: */
-void             tcp_init    (void);  /* Must be called first to
-           initialize TCP. */
-void             tcp_tmr     (void);  /* Must be called every
-           TCP_TMR_INTERVAL
-           ms. (Typically 250 ms). */
-/* Application program's interface: */
-struct tcp_pcb * tcp_new     (void);
-struct tcp_pcb * tcp_alloc   (u8_t prio);
-
-void             tcp_arg     (struct tcp_pcb *pcb, void *arg);
-void             tcp_accept  (struct tcp_pcb *pcb,
-            err_t (* accept)(void *arg, struct tcp_pcb *newpcb,
-                 err_t err));
-void             tcp_recv    (struct tcp_pcb *pcb,
-            err_t (* recv)(void *arg, struct tcp_pcb *tpcb,
-          struct pbuf *p, err_t err));
-void             tcp_sent    (struct tcp_pcb *pcb,
-            err_t (* sent)(void *arg, struct tcp_pcb *tpcb,
-               u16_t len));
-void             tcp_poll    (struct tcp_pcb *pcb,
-            err_t (* poll)(void *arg, struct tcp_pcb *tpcb),
-            u8_t interval);
-void             tcp_err     (struct tcp_pcb *pcb,
-            void (* err)(void *arg, err_t err));
-
-#define          tcp_mss(pcb)      ((pcb)->mss)
-#define          tcp_sndbuf(pcb)   ((pcb)->snd_buf)
-
-void             tcp_recved  (struct tcp_pcb *pcb, u16_t len);
-err_t            tcp_bind    (struct tcp_pcb *pcb, struct ip_addr *ipaddr,
-            u16_t port);
-err_t            tcp_connect (struct tcp_pcb *pcb, struct ip_addr *ipaddr,
-            u16_t port, err_t (* connected)(void *arg,
-                    struct tcp_pcb *tpcb,
-                    err_t err));
-struct tcp_pcb * tcp_listen  (struct tcp_pcb *pcb);
-void             tcp_abort   (struct tcp_pcb *pcb);
-err_t            tcp_close   (struct tcp_pcb *pcb);
-err_t            tcp_write   (struct tcp_pcb *pcb, const void *dataptr, u16_t len,
-            u8_t copy);
-
-void             tcp_setprio (struct tcp_pcb *pcb, u8_t prio);
-
-#define TCP_PRIO_MIN    1
-#define TCP_PRIO_NORMAL 64
-#define TCP_PRIO_MAX    127
-
-/* It is also possible to call these two functions at the right
-   intervals (instead of calling tcp_tmr()). */
-void             tcp_slowtmr (void);
-void             tcp_fasttmr (void);
-
-
-/* Only used by IP to pass a TCP segment to TCP: */
-void             tcp_input   (struct pbuf *p, struct netif *inp);
-/* Used within the TCP code only: */
-err_t            tcp_output  (struct tcp_pcb *pcb);
-void             tcp_rexmit  (struct tcp_pcb *pcb);
-void             tcp_rexmit_rto  (struct tcp_pcb *pcb);
-
-
-
-#define TCP_SEQ_LT(a,b)     ((s32_t)((a)-(b)) < 0)
-#define TCP_SEQ_LEQ(a,b)    ((s32_t)((a)-(b)) <= 0)
-#define TCP_SEQ_GT(a,b)     ((s32_t)((a)-(b)) > 0)
-#define TCP_SEQ_GEQ(a,b)    ((s32_t)((a)-(b)) >= 0)
-/* is b<=a<=c? */
-#if 0 /* see bug #10548 */
-#define TCP_SEQ_BETWEEN(a,b,c) ((c)-(b) >= (a)-(b))
-#endif
-#define TCP_SEQ_BETWEEN(a,b,c) (TCP_SEQ_GEQ(a,b) && TCP_SEQ_LEQ(a,c))
-#define TCP_FIN 0x01U
-#define TCP_SYN 0x02U
-#define TCP_RST 0x04U
-#define TCP_PSH 0x08U
-#define TCP_ACK 0x10U
-#define TCP_URG 0x20U
-#define TCP_ECE 0x40U
-#define TCP_CWR 0x80U
-
-#define TCP_FLAGS 0x3fU
-
-/* Length of the TCP header, excluding options. */
-#define TCP_HLEN 20
-
-#ifndef TCP_TMR_INTERVAL
-#define TCP_TMR_INTERVAL       250  /* The TCP timer interval in
-                                       milliseconds. */
-#endif /* TCP_TMR_INTERVAL */
-
-#ifndef TCP_FAST_INTERVAL
-#define TCP_FAST_INTERVAL      TCP_TMR_INTERVAL /* the fine grained timeout in
-                                       milliseconds */
-#endif /* TCP_FAST_INTERVAL */
-
-#ifndef TCP_SLOW_INTERVAL
-#define TCP_SLOW_INTERVAL      (2*TCP_TMR_INTERVAL)  /* the coarse grained timeout in
-                                       milliseconds */
-#endif /* TCP_SLOW_INTERVAL */
-
-#define TCP_FIN_WAIT_TIMEOUT 20000 /* milliseconds */
-#define TCP_SYN_RCVD_TIMEOUT 20000 /* milliseconds */
-
-#define TCP_OOSEQ_TIMEOUT        6 /* x RTO */
-
-#define TCP_MSL 60000  /* The maximum segment lifetime in microseconds */
-
-/*
- * User-settable options (used with setsockopt).
- */
-#define	TCP_NODELAY	   0x01	   /* don't delay send to coalesce packets */
-#define TCP_KEEPALIVE  0x02    /* send KEEPALIVE probes when idle for pcb->keepalive miliseconds */
-
-/* Keepalive values */
-#define  TCP_KEEPDEFAULT   7200000                       /* KEEPALIVE timer in miliseconds */
-#define  TCP_KEEPINTVL     75000                         /* Time between KEEPALIVE probes in miliseconds */
-#define  TCP_KEEPCNT       9                             /* Counter for KEEPALIVE probes */
-#define  TCP_MAXIDLE       TCP_KEEPCNT * TCP_KEEPINTVL   /* Maximum KEEPALIVE probe time */
-
-
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-struct tcp_hdr {
-  PACK_STRUCT_FIELD(u16_t src);
-  PACK_STRUCT_FIELD(u16_t dest);
-  PACK_STRUCT_FIELD(u32_t seqno);
-  PACK_STRUCT_FIELD(u32_t ackno);
-  PACK_STRUCT_FIELD(u16_t _hdrlen_rsvd_flags);
-  PACK_STRUCT_FIELD(u16_t wnd);
-  PACK_STRUCT_FIELD(u16_t chksum);
-  PACK_STRUCT_FIELD(u16_t urgp);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-#define TCPH_OFFSET(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) >> 8)
-#define TCPH_HDRLEN(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) >> 12)
-#define TCPH_FLAGS(phdr)  (ntohs((phdr)->_hdrlen_rsvd_flags) & TCP_FLAGS)
-
-#define TCPH_OFFSET_SET(phdr, offset) (phdr)->_hdrlen_rsvd_flags = htons(((offset) << 8) | TCPH_FLAGS(phdr))
-#define TCPH_HDRLEN_SET(phdr, len) (phdr)->_hdrlen_rsvd_flags = htons(((len) << 12) | TCPH_FLAGS(phdr))
-#define TCPH_FLAGS_SET(phdr, flags) (phdr)->_hdrlen_rsvd_flags = htons((ntohs((phdr)->_hdrlen_rsvd_flags) & ~TCP_FLAGS) | (flags))
-#define TCPH_SET_FLAG(phdr, flags ) (phdr)->_hdrlen_rsvd_flags = htons(ntohs((phdr)->_hdrlen_rsvd_flags) | (flags))
-#define TCPH_UNSET_FLAG(phdr, flags) (phdr)->_hdrlen_rsvd_flags = htons(ntohs((phdr)->_hdrlen_rsvd_flags) | (TCPH_FLAGS(phdr) & ~(flags)) )
-
-#define TCP_TCPLEN(seg) ((seg)->len + ((TCPH_FLAGS((seg)->tcphdr) & TCP_FIN || \
-          TCPH_FLAGS((seg)->tcphdr) & TCP_SYN)? 1: 0))
-
-enum tcp_state {
-  CLOSED      = 0,
-  LISTEN      = 1,
-  SYN_SENT    = 2,
-  SYN_RCVD    = 3,
-  ESTABLISHED = 4,
-  FIN_WAIT_1  = 5,
-  FIN_WAIT_2  = 6,
-  CLOSE_WAIT  = 7,
-  CLOSING     = 8,
-  LAST_ACK    = 9,
-  TIME_WAIT   = 10
-};
-
-/* the TCP protocol control block */
-struct tcp_pcb {
-/** common PCB members */
-  IP_PCB;
-/** protocol specific PCB members */
-  struct tcp_pcb *next; /* for the linked list */
-  enum tcp_state state; /* TCP state */
-  u8_t prio;
-  void *callback_arg;
-
-  u16_t local_port;
-  u16_t remote_port;
-  
-  u8_t flags;
-#define TF_ACK_DELAY (u8_t)0x01U   /* Delayed ACK. */
-#define TF_ACK_NOW   (u8_t)0x02U   /* Immediate ACK. */
-#define TF_INFR      (u8_t)0x04U   /* In fast recovery. */
-#define TF_RESET     (u8_t)0x08U   /* Connection was reset. */
-#define TF_CLOSED    (u8_t)0x10U   /* Connection was sucessfully closed. */
-#define TF_GOT_FIN   (u8_t)0x20U   /* Connection was closed by the remote end. */
-#define TF_NODELAY   (u8_t)0x40U   /* Disable Nagle algorithm */
-
-  /* receiver variables */
-  u32_t rcv_nxt;   /* next seqno expected */
-  u16_t rcv_wnd;   /* receiver window */
-  
-  /* Timers */
-  u32_t tmr;
-  u8_t polltmr, pollinterval;
-  
-  /* Retransmission timer. */
-  u16_t rtime;
-  
-  u16_t mss;   /* maximum segment size */
-  
-  /* RTT (round trip time) estimation variables */
-  u32_t rttest; /* RTT estimate in 500ms ticks */
-  u32_t rtseq;  /* sequence number being timed */
-  s16_t sa, sv; /* @todo document this */
-
-  u16_t rto;    /* retransmission time-out */
-  u8_t nrtx;    /* number of retransmissions */
-
-  /* fast retransmit/recovery */
-  u32_t lastack; /* Highest acknowledged seqno. */
-  u8_t dupacks;
-  
-  /* congestion avoidance/control variables */
-  u16_t cwnd;  
-  u16_t ssthresh;
-
-  /* sender variables */
-  u32_t snd_nxt,       /* next seqno to be sent */
-    snd_max,       /* Highest seqno sent. */
-    snd_wnd,       /* sender window */
-    snd_wl1, snd_wl2, /* Sequence and acknowledgement numbers of last
-       window update. */
-    snd_lbb;       /* Sequence number of next byte to be buffered. */
-
-  u16_t acked;
-  
-  u16_t snd_buf;   /* Available buffer space for sending (in bytes). */
-  u8_t snd_queuelen; /* Available buffer space for sending (in tcp_segs). */
-  
-  
-  /* These are ordered by sequence number: */
-  struct tcp_seg *unsent;   /* Unsent (queued) segments. */
-  struct tcp_seg *unacked;  /* Sent but unacknowledged segments. */
-#if TCP_QUEUE_OOSEQ  
-  struct tcp_seg *ooseq;    /* Received out of sequence segments. */
-#endif /* TCP_QUEUE_OOSEQ */
-
-#if LWIP_CALLBACK_API
-  /* Function to be called when more send buffer space is available. */
-  err_t (* sent)(void *arg, struct tcp_pcb *pcb, u16_t space);
-  
-  /* Function to be called when (in-sequence) data has arrived. */
-  err_t (* recv)(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err);
-
-  /* Function to be called when a connection has been set up. */
-  err_t (* connected)(void *arg, struct tcp_pcb *pcb, err_t err);
-
-  /* Function to call when a listener has been connected. */
-  err_t (* accept)(void *arg, struct tcp_pcb *newpcb, err_t err);
-
-  /* Function which is called periodically. */
-  err_t (* poll)(void *arg, struct tcp_pcb *pcb);
-
-  /* Function to be called whenever a fatal error occurs. */
-  void (* errf)(void *arg, err_t err);
-#endif /* LWIP_CALLBACK_API */
-
-  /* idle time before KEEPALIVE is sent */
-  u32_t keepalive;
-  
-  /* KEEPALIVE counter */
-  u8_t keep_cnt;
-};
-
-struct tcp_pcb_listen {  
-/* Common members of all PCB types */
-  IP_PCB;
-
-/* Protocol specific PCB members */
-  struct tcp_pcb_listen *next;   /* for the linked list */
-  
-  /* Even if state is obviously LISTEN this is here for
-   * field compatibility with tpc_pcb to which it is cast sometimes
-   * Until a cleaner solution emerges this is here.FIXME
-   */ 
-  enum tcp_state state;   /* TCP state */
-
-  u8_t prio;
-  void *callback_arg;
-  
-  u16_t local_port; 
-
-#if LWIP_CALLBACK_API
-  /* Function to call when a listener has been connected. */
-  err_t (* accept)(void *arg, struct tcp_pcb *newpcb, err_t err);
-#endif /* LWIP_CALLBACK_API */
-};
-
-#if LWIP_EVENT_API
-
-enum lwip_event {
-  LWIP_EVENT_ACCEPT,
-  LWIP_EVENT_SENT,
-  LWIP_EVENT_RECV,
-  LWIP_EVENT_CONNECTED,
-  LWIP_EVENT_POLL,
-  LWIP_EVENT_ERR
-};
-
-err_t lwip_tcp_event(void *arg, struct tcp_pcb *pcb,
-         enum lwip_event,
-         struct pbuf *p,
-         u16_t size,
-         err_t err);
-
-#define TCP_EVENT_ACCEPT(pcb,err,ret)    ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
-                LWIP_EVENT_ACCEPT, NULL, 0, err)
-#define TCP_EVENT_SENT(pcb,space,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
-                   LWIP_EVENT_SENT, NULL, space, ERR_OK)
-#define TCP_EVENT_RECV(pcb,p,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
-                LWIP_EVENT_RECV, (p), 0, (err))
-#define TCP_EVENT_CONNECTED(pcb,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
-                LWIP_EVENT_CONNECTED, NULL, 0, (err))
-#define TCP_EVENT_POLL(pcb,ret)       ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
-                LWIP_EVENT_POLL, NULL, 0, ERR_OK)
-#define TCP_EVENT_ERR(errf,arg,err)  lwip_tcp_event((arg), NULL, \
-                LWIP_EVENT_ERR, NULL, 0, (err))
-#else /* LWIP_EVENT_API */
-#define TCP_EVENT_ACCEPT(pcb,err,ret)     \
-                        if((pcb)->accept != NULL) \
-                        (ret = (pcb)->accept((pcb)->callback_arg,(pcb),(err)))
-#define TCP_EVENT_SENT(pcb,space,ret) \
-                        if((pcb)->sent != NULL) \
-                        (ret = (pcb)->sent((pcb)->callback_arg,(pcb),(space)))
-#define TCP_EVENT_RECV(pcb,p,err,ret) \
-                        if((pcb)->recv != NULL) \
-                        { ret = (pcb)->recv((pcb)->callback_arg,(pcb),(p),(err)); } else { \
-                          if (p) pbuf_free(p); }
-#define TCP_EVENT_CONNECTED(pcb,err,ret) \
-                        if((pcb)->connected != NULL) \
-                        (ret = (pcb)->connected((pcb)->callback_arg,(pcb),(err)))
-#define TCP_EVENT_POLL(pcb,ret) \
-                        if((pcb)->poll != NULL) \
-                        (ret = (pcb)->poll((pcb)->callback_arg,(pcb)))
-#define TCP_EVENT_ERR(errf,arg,err) \
-                        if((errf) != NULL) \
-                        (errf)((arg),(err))
-#endif /* LWIP_EVENT_API */
-
-/* This structure represents a TCP segment on the unsent and unacked queues */
-struct tcp_seg {
-  struct tcp_seg *next;    /* used when putting segements on a queue */
-  struct pbuf *p;          /* buffer containing data + TCP header */
-  void *dataptr;           /* pointer to the TCP data in the pbuf */
-  u16_t len;               /* the TCP length of this segment */
-  struct tcp_hdr *tcphdr;  /* the TCP header */
-};
-
-/* Internal functions and global variables: */
-struct tcp_pcb *tcp_pcb_copy(struct tcp_pcb *pcb);
-void tcp_pcb_purge(struct tcp_pcb *pcb);
-void tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb);
-
-u8_t tcp_segs_free(struct tcp_seg *seg);
-u8_t tcp_seg_free(struct tcp_seg *seg);
-struct tcp_seg *tcp_seg_copy(struct tcp_seg *seg);
-
-#define tcp_ack(pcb)     if((pcb)->flags & TF_ACK_DELAY) { \
-                            (pcb)->flags &= ~TF_ACK_DELAY; \
-                            (pcb)->flags |= TF_ACK_NOW; \
-                            tcp_output(pcb); \
-                         } else { \
-                            (pcb)->flags |= TF_ACK_DELAY; \
-                         }
-
-#define tcp_ack_now(pcb) (pcb)->flags |= TF_ACK_NOW; \
-                         tcp_output(pcb)
-
-err_t tcp_send_ctrl(struct tcp_pcb *pcb, u8_t flags);
-err_t tcp_enqueue(struct tcp_pcb *pcb, void *dataptr, u16_t len,
-    u8_t flags, u8_t copy,
-                u8_t *optdata, u8_t optlen);
-
-void tcp_rexmit_seg(struct tcp_pcb *pcb, struct tcp_seg *seg);
-
-void tcp_rst(u32_t seqno, u32_t ackno,
-       struct ip_addr *local_ip, struct ip_addr *remote_ip,
-       u16_t local_port, u16_t remote_port);
-
-u32_t tcp_next_iss(void);
-
-void tcp_keepalive(struct tcp_pcb *pcb);
-
-extern struct tcp_pcb *tcp_input_pcb;
-extern u32_t tcp_ticks;
-
-#if TCP_DEBUG || TCP_INPUT_DEBUG || TCP_OUTPUT_DEBUG
-void tcp_debug_print(struct tcp_hdr *tcphdr);
-void tcp_debug_print_flags(u8_t flags);
-void tcp_debug_print_state(enum tcp_state s);
-void tcp_debug_print_pcbs(void);
-s16_t tcp_pcbs_sane(void);
-#else
-#  define tcp_debug_print(tcphdr)
-#  define tcp_debug_print_flags(flags)
-#  define tcp_debug_print_state(s)
-#  define tcp_debug_print_pcbs()
-#  define tcp_pcbs_sane() 1
-#endif /* TCP_DEBUG */
-
-#if NO_SYS
-#define tcp_timer_needed()
-#else
-void tcp_timer_needed(void);
-#endif
-
-/* The TCP PCB lists. */
-union tcp_listen_pcbs_t { /* List of all TCP PCBs in LISTEN state. */
-	struct tcp_pcb_listen *listen_pcbs; 
-	struct tcp_pcb *pcbs;
-};
-extern union tcp_listen_pcbs_t tcp_listen_pcbs;
-extern struct tcp_pcb *tcp_active_pcbs;  /* List of all TCP PCBs that are in a
-              state in which they accept or send
-              data. */
-extern struct tcp_pcb *tcp_tw_pcbs;      /* List of all TCP PCBs in TIME-WAIT. */
-
-extern struct tcp_pcb *tcp_tmp_pcb;      /* Only used for temporary storage. */
-
-/* Axioms about the above lists:   
-   1) Every TCP PCB that is not CLOSED is in one of the lists.
-   2) A PCB is only in one of the lists.
-   3) All PCBs in the tcp_listen_pcbs list is in LISTEN state.
-   4) All PCBs in the tcp_tw_pcbs list is in TIME-WAIT state.
-*/
-
-/* Define two macros, TCP_REG and TCP_RMV that registers a TCP PCB
-   with a PCB list or removes a PCB from a list, respectively. */
-#if 0
-#define TCP_REG(pcbs, npcb) do {\
-                            LWIP_DEBUGF(TCP_DEBUG, ("TCP_REG %p local port %d\n", npcb, npcb->local_port)); \
-                            for(tcp_tmp_pcb = *pcbs; \
-          tcp_tmp_pcb != NULL; \
-        tcp_tmp_pcb = tcp_tmp_pcb->next) { \
-                                LWIP_ASSERT("TCP_REG: already registered\n", tcp_tmp_pcb != npcb); \
-                            } \
-                            LWIP_ASSERT("TCP_REG: pcb->state != CLOSED", npcb->state != CLOSED); \
-                            npcb->next = *pcbs; \
-                            LWIP_ASSERT("TCP_REG: npcb->next != npcb", npcb->next != npcb); \
-                            *(pcbs) = npcb; \
-                            LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \
-              tcp_timer_needed(); \
-                            } while(0)
-#define TCP_RMV(pcbs, npcb) do { \
-                            LWIP_ASSERT("TCP_RMV: pcbs != NULL", *pcbs != NULL); \
-                            LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removing %p from %p\n", npcb, *pcbs)); \
-                            if(*pcbs == npcb) { \
-                               *pcbs = (*pcbs)->next; \
-                            } else for(tcp_tmp_pcb = *pcbs; tcp_tmp_pcb != NULL; tcp_tmp_pcb = tcp_tmp_pcb->next) { \
-                               if(tcp_tmp_pcb->next != NULL && tcp_tmp_pcb->next == npcb) { \
-                                  tcp_tmp_pcb->next = npcb->next; \
-                                  break; \
-                               } \
-                            } \
-                            npcb->next = NULL; \
-                            LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \
-                            LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removed %p from %p\n", npcb, *pcbs)); \
-                            } while(0)
-
-#else /* LWIP_DEBUG */
-#define TCP_REG(pcbs, npcb) do { \
-                            npcb->next = *pcbs; \
-                            *(pcbs) = npcb; \
-              tcp_timer_needed(); \
-                            } while(0)
-#define TCP_RMV(pcbs, npcb) do { \
-                            if(*(pcbs) == npcb) { \
-                               (*(pcbs)) = (*pcbs)->next; \
-                            } else for(tcp_tmp_pcb = *pcbs; tcp_tmp_pcb != NULL; tcp_tmp_pcb = tcp_tmp_pcb->next) { \
-                               if(tcp_tmp_pcb->next != NULL && tcp_tmp_pcb->next == npcb) { \
-                                  tcp_tmp_pcb->next = npcb->next; \
-                                  break; \
-                               } \
-                            } \
-                            npcb->next = NULL; \
-                            } while(0)
-#endif /* LWIP_DEBUG */
-#endif /* __LWIP_TCP_H__ */
-
-
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/tcpip.h b/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/tcpip.h
deleted file mode 100644
index 316ae4fc5..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/tcpip.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_TCPIP_H__
-#define __LWIP_TCPIP_H__
-
-#include "lwip/api_msg.h"
-#include "lwip/pbuf.h"
-
-void tcpip_init(void (* tcpip_init_done)(void *), void *arg);
-void tcpip_apimsg(struct api_msg *apimsg);
-err_t tcpip_input(struct pbuf *p, struct netif *inp);
-err_t tcpip_callback(void (*f)(void *ctx), void *ctx);
-
-void tcpip_tcp_timer_needed(void);
-
-enum tcpip_msg_type {
-  TCPIP_MSG_API,
-  TCPIP_MSG_INPUT,
-  TCPIP_MSG_CALLBACK
-};
-
-struct tcpip_msg {
-  enum tcpip_msg_type type;
-  sys_sem_t *sem;
-  union {
-    struct api_msg *apimsg;
-    struct {
-      struct pbuf *p;
-      struct netif *netif;
-    } inp;
-    struct {
-      void (*f)(void *ctx);
-      void *ctx;
-    } cb;
-  } msg;
-};
-
-
-#endif /* __LWIP_TCPIP_H__ */
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/udp.h b/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/udp.h
deleted file mode 100644
index ede04745f..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/include/lwip/udp.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __LWIP_UDP_H__
-#define __LWIP_UDP_H__
-
-#include "lwip/arch.h"
-
-#include "lwip/pbuf.h"
-#include "lwip/inet.h"
-#include "lwip/ip.h"
-
-#define UDP_HLEN 8
-
-struct udp_hdr {
-  PACK_STRUCT_FIELD(u16_t src);
-  PACK_STRUCT_FIELD(u16_t dest);  /* src/dest UDP ports */
-  PACK_STRUCT_FIELD(u16_t len);
-  PACK_STRUCT_FIELD(u16_t chksum);
-} PACK_STRUCT_STRUCT;
-
-#define UDP_FLAGS_NOCHKSUM 0x01U
-#define UDP_FLAGS_UDPLITE  0x02U
-#define UDP_FLAGS_CONNECTED  0x04U
-
-struct udp_pcb {
-/* Common members of all PCB types */
-  IP_PCB;
-
-/* Protocol specific PCB members */
-
-  struct udp_pcb *next;
-
-  u8_t flags;
-  u16_t local_port, remote_port;
-  
-  u16_t chksum_len;
-  
-  void (* recv)(void *arg, struct udp_pcb *pcb, struct pbuf *p,
-    struct ip_addr *addr, u16_t port);
-  void *recv_arg;  
-};
-
-/* The following functions is the application layer interface to the
-   UDP code. */
-struct udp_pcb * udp_new        (void);
-void             udp_remove     (struct udp_pcb *pcb);
-err_t            udp_bind       (struct udp_pcb *pcb, struct ip_addr *ipaddr,
-                 u16_t port);
-err_t            udp_connect    (struct udp_pcb *pcb, struct ip_addr *ipaddr,
-                 u16_t port);
-void             udp_disconnect    (struct udp_pcb *pcb);
-void             udp_recv       (struct udp_pcb *pcb,
-         void (* recv)(void *arg, struct udp_pcb *upcb,
-                 struct pbuf *p,
-                 struct ip_addr *addr,
-                 u16_t port),
-         void *recv_arg);
-err_t            udp_sendto     (struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *dst_ip, u16_t dst_port);
-err_t            udp_send       (struct udp_pcb *pcb, struct pbuf *p);
-
-#define          udp_flags(pcb)  ((pcb)->flags)
-#define          udp_setflags(pcb, f)  ((pcb)->flags = (f))
-
-/* The following functions are the lower layer interface to UDP. */
-void             udp_input      (struct pbuf *p, struct netif *inp);
-void             udp_init       (void);
-
-#if UDP_DEBUG
-void udp_debug_print(struct udp_hdr *udphdr);
-#else
-#define udp_debug_print(udphdr)
-#endif
-#endif /* __LWIP_UDP_H__ */
-
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/include/netif/etharp.h b/Demo/lwIP_MCF5235_GCC/lwip/src/include/netif/etharp.h
deleted file mode 100644
index 08437afe5..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/include/netif/etharp.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
- * Copyright (c) 2003-2004 Leon Woestenberg 
- * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-
-#ifndef __NETIF_ETHARP_H__
-#define __NETIF_ETHARP_H__
-
-#ifndef ETH_PAD_SIZE
-#define ETH_PAD_SIZE 0
-#endif
-
-#include "lwip/pbuf.h"
-#include "lwip/ip_addr.h"
-#include "lwip/netif.h"
-#include "lwip/ip.h"
-
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-struct eth_addr {
-  PACK_STRUCT_FIELD(u8_t addr[6]);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-struct eth_hdr {
-#if ETH_PAD_SIZE
-  PACK_STRUCT_FIELD(u8_t padding[ETH_PAD_SIZE]);
-#endif
-  PACK_STRUCT_FIELD(struct eth_addr dest);
-  PACK_STRUCT_FIELD(struct eth_addr src);
-  PACK_STRUCT_FIELD(u16_t type);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-/** the ARP message */
-struct etharp_hdr {
-  PACK_STRUCT_FIELD(struct eth_hdr ethhdr);
-  PACK_STRUCT_FIELD(u16_t hwtype);
-  PACK_STRUCT_FIELD(u16_t proto);
-  PACK_STRUCT_FIELD(u16_t _hwlen_protolen);
-  PACK_STRUCT_FIELD(u16_t opcode);
-  PACK_STRUCT_FIELD(struct eth_addr shwaddr);
-  PACK_STRUCT_FIELD(struct ip_addr2 sipaddr);
-  PACK_STRUCT_FIELD(struct eth_addr dhwaddr);
-  PACK_STRUCT_FIELD(struct ip_addr2 dipaddr);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-struct ethip_hdr {
-  PACK_STRUCT_FIELD(struct eth_hdr eth);
-  PACK_STRUCT_FIELD(struct ip_hdr ip);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-/** 5 seconds period */
-#define ARP_TMR_INTERVAL 5000
-
-#define ETHTYPE_ARP 0x0806
-#define ETHTYPE_IP  0x0800
-
-void etharp_init(void);
-void etharp_tmr(void);
-void etharp_ip_input(struct netif *netif, struct pbuf *p);
-void etharp_arp_input(struct netif *netif, struct eth_addr *ethaddr,
-         struct pbuf *p);
-err_t etharp_output(struct netif *netif, struct ip_addr *ipaddr,
-         struct pbuf *q);
-err_t etharp_query(struct netif *netif, struct ip_addr *ipaddr, struct pbuf *q);
-err_t etharp_request(struct netif *netif, struct ip_addr *ipaddr);
-
-#endif /* __NETIF_ARP_H__ */
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/include/netif/loopif.h b/Demo/lwIP_MCF5235_GCC/lwip/src/include/netif/loopif.h
deleted file mode 100644
index 97b3c6764..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/include/netif/loopif.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __NETIF_LOOPIF_H__
-#define __NETIF_LOOPIF_H__
-
-#include "lwip/netif.h"
-
-err_t loopif_init(struct netif *netif);
-
-#endif /* __NETIF_LOOPIF_H__ */
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/include/netif/slipif.h b/Demo/lwIP_MCF5235_GCC/lwip/src/include/netif/slipif.h
deleted file mode 100644
index bf70046a9..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/include/netif/slipif.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (c) 2001, Swedish Institute of Computer Science.
- * All rights reserved. 
- *
- * Redistribution and use in source and binary forms, with or without 
- * modification, are permitted provided that the following conditions 
- * are met: 
- * 1. Redistributions of source code must retain the above copyright 
- *    notice, this list of conditions and the following disclaimer. 
- * 2. Redistributions in binary form must reproduce the above copyright 
- *    notice, this list of conditions and the following disclaimer in the 
- *    documentation and/or other materials provided with the distribution. 
- * 3. Neither the name of the Institute nor the names of its contributors 
- *    may be used to endorse or promote products derived from this software 
- *    without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
- * SUCH DAMAGE. 
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#ifndef __NETIF_SLIPIF_H__
-#define __NETIF_SLIPIF_H__
-
-#include "lwip/netif.h"
-
-err_t slipif_init(struct netif * netif);
- 
-#endif 
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/FILES b/Demo/lwIP_MCF5235_GCC/lwip/src/netif/FILES
deleted file mode 100644
index 825d40715..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/FILES
+++ /dev/null
@@ -1,27 +0,0 @@
-This directory contains generic network interface device drivers that
-do not contain any hardware or architecture specific code. The files
-are:
-
-etharp.c
-          Implements the ARP (Address Resolution Protocol) over
-          Ethernet. The code in this file should be used together with
-          Ethernet device drivers. Note that this module has been
-          largely made Ethernet independent so you should be able to
-          adapt this for other link layers (such as Firewire).
-
-ethernetif.c
-          An example of how an Ethernet device driver could look. This
-          file can be used as a "skeleton" for developing new Ethernet
-          network device drivers. It uses the etharp.c ARP code.
-
-loopif.c
-          An example network interface that shows how a "loopback"
-          interface would work. This is not really intended for actual
-          use, but as a very basic example of how initialization and
-          output functions work.
-
-slipif.c
-          A generic implementation of the SLIP (Serial Line IP)
-          protocol. It requires a sio (serial I/O) module to work.
-	  
-ppp/      Point-to-Point Protocol stack
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/etharp.c b/Demo/lwIP_MCF5235_GCC/lwip/src/netif/etharp.c
deleted file mode 100644
index 7765046d4..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/etharp.c
+++ /dev/null
@@ -1,831 +0,0 @@
-/**
- * @file
- * Address Resolution Protocol module for IP over Ethernet
- *
- * Functionally, ARP is divided into two parts. The first maps an IP address
- * to a physical address when sending a packet, and the second part answers
- * requests from other machines for our physical address.
- *
- * This implementation complies with RFC 826 (Ethernet ARP). It supports
- * Gratuitious ARP from RFC3220 (IP Mobility Support for IPv4) section 4.6
- * if an interface calls etharp_query(our_netif, its_ip_addr, NULL) upon
- * address change.
- */
-
-/*
- * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
- * Copyright (c) 2003-2004 Leon Woestenberg 
- * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- */
-
-#include "lwip/opt.h"
-#include "lwip/inet.h"
-#include "netif/etharp.h"
-#include "lwip/ip.h"
-#include "lwip/stats.h"
-
-/* ARP needs to inform DHCP of any ARP replies? */
-#if (LWIP_DHCP && DHCP_DOES_ARP_CHECK)
-#  include "lwip/dhcp.h"
-#endif
-
-/** the time an ARP entry stays valid after its last update,
- * (240 * 5) seconds = 20 minutes.
- */
-#define ARP_MAXAGE 240
-/** the time an ARP entry stays pending after first request,
- * (2 * 5) seconds = 10 seconds.
- * 
- * @internal Keep this number at least 2, otherwise it might
- * run out instantly if the timeout occurs directly after a request.
- */
-#define ARP_MAXPENDING 2
-
-#define HWTYPE_ETHERNET 1
-
-/** ARP message types */
-#define ARP_REQUEST 1
-#define ARP_REPLY 2
-
-#define ARPH_HWLEN(hdr) (ntohs((hdr)->_hwlen_protolen) >> 8)
-#define ARPH_PROTOLEN(hdr) (ntohs((hdr)->_hwlen_protolen) & 0xff)
-
-#define ARPH_HWLEN_SET(hdr, len) (hdr)->_hwlen_protolen = htons(ARPH_PROTOLEN(hdr) | ((len) << 8))
-#define ARPH_PROTOLEN_SET(hdr, len) (hdr)->_hwlen_protolen = htons((len) | (ARPH_HWLEN(hdr) << 8))
-
-enum etharp_state {
-  ETHARP_STATE_EMPTY,
-  ETHARP_STATE_PENDING,
-  ETHARP_STATE_STABLE,
-  /** @internal transitional state used in etharp_tmr() for convenience*/
-  ETHARP_STATE_EXPIRED
-};
-
-struct etharp_entry {
-#if ARP_QUEUEING
-  /** 
-   * Pointer to queue of pending outgoing packets on this ARP entry.
-   */
-   struct pbuf *p;
-#endif
-  struct ip_addr ipaddr;
-  struct eth_addr ethaddr;
-  enum etharp_state state;
-  u8_t ctime;
-};
-
-static const struct eth_addr ethbroadcast = {{0xff,0xff,0xff,0xff,0xff,0xff}};
-static struct etharp_entry arp_table[ARP_TABLE_SIZE];
-
-/**
- * Try hard to create a new entry - we want the IP address to appear in
- * the cache (even if this means removing an active entry or so). */
-#define ETHARP_TRY_HARD 1
-
-static s8_t find_entry(struct ip_addr *ipaddr, u8_t flags);
-static err_t update_arp_entry(struct netif *netif, struct ip_addr *ipaddr, struct eth_addr *ethaddr, u8_t flags);
-/**
- * Initializes ARP module.
- */
-void
-etharp_init(void)
-{
-  u8_t i;
-  /* clear ARP entries */
-  for(i = 0; i < ARP_TABLE_SIZE; ++i) {
-    arp_table[i].state = ETHARP_STATE_EMPTY;
-#if ARP_QUEUEING
-    arp_table[i].p = NULL;
-#endif
-    arp_table[i].ctime = 0;
-  }
-}
-
-/**
- * Clears expired entries in the ARP table.
- *
- * This function should be called every ETHARP_TMR_INTERVAL microseconds (5 seconds),
- * in order to expire entries in the ARP table.
- */
-void
-etharp_tmr(void)
-{
-  u8_t i;
-
-  LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer\n"));
-  /* remove expired entries from the ARP table */
-  for (i = 0; i < ARP_TABLE_SIZE; ++i) {
-    arp_table[i].ctime++;
-    /* stable entry? */
-    if ((arp_table[i].state == ETHARP_STATE_STABLE) &&
-         /* entry has become old? */
-        (arp_table[i].ctime >= ARP_MAXAGE)) {
-      LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: expired stable entry %"U16_F".\n", (u16_t)i));
-      arp_table[i].state = ETHARP_STATE_EXPIRED;
-    /* pending entry? */
-    } else if (arp_table[i].state == ETHARP_STATE_PENDING) {
-      /* entry unresolved/pending for too long? */
-      if (arp_table[i].ctime >= ARP_MAXPENDING) {
-        LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: expired pending entry %"U16_F".\n", (u16_t)i));
-        arp_table[i].state = ETHARP_STATE_EXPIRED;
-#if ARP_QUEUEING
-      } else if (arp_table[i].p != NULL) {
-        /* resend an ARP query here */
-#endif
-      }
-    }
-    /* clean up entries that have just been expired */
-    if (arp_table[i].state == ETHARP_STATE_EXPIRED) {
-#if ARP_QUEUEING
-      /* and empty packet queue */
-      if (arp_table[i].p != NULL) {
-        /* remove all queued packets */
-        LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: freeing entry %"U16_F", packet queue %p.\n", (u16_t)i, (void *)(arp_table[i].p)));
-        pbuf_free(arp_table[i].p);
-        arp_table[i].p = NULL;
-      }
-#endif
-      /* recycle entry for re-use */      
-      arp_table[i].state = ETHARP_STATE_EMPTY;
-    }
-  }
-}
-
-/**
- * Search the ARP table for a matching or new entry.
- * 
- * If an IP address is given, return a pending or stable ARP entry that matches
- * the address. If no match is found, create a new entry with this address set,
- * but in state ETHARP_EMPTY. The caller must check and possibly change the
- * state of the returned entry.
- * 
- * If ipaddr is NULL, return a initialized new entry in state ETHARP_EMPTY.
- * 
- * In all cases, attempt to create new entries from an empty entry. If no
- * empty entries are available and ETHARP_TRY_HARD flag is set, recycle
- * old entries. Heuristic choose the least important entry for recycling.
- *
- * @param ipaddr IP address to find in ARP cache, or to add if not found.
- * @param flags
- * - ETHARP_TRY_HARD: Try hard to create a entry by allowing recycling of
- * active (stable or pending) entries.
- *  
- * @return The ARP entry index that matched or is created, ERR_MEM if no
- * entry is found or could be recycled.
- */
-static s8_t find_entry(struct ip_addr *ipaddr, u8_t flags)
-{
-  s8_t old_pending = ARP_TABLE_SIZE, old_stable = ARP_TABLE_SIZE;
-  s8_t empty = ARP_TABLE_SIZE;
-  u8_t i = 0, age_pending = 0, age_stable = 0;
-#if ARP_QUEUEING
-  /* oldest entry with packets on queue */
-  s8_t old_queue = ARP_TABLE_SIZE;
-  /* its age */
-  u8_t age_queue = 0;
-#endif
-
-  /**
-   * a) do a search through the cache, remember candidates
-   * b) select candidate entry
-   * c) create new entry
-   */
-
-  /* a) in a single search sweep, do all of this
-   * 1) remember the first empty entry (if any)
-   * 2) remember the oldest stable entry (if any)
-   * 3) remember the oldest pending entry without queued packets (if any)
-   * 4) remember the oldest pending entry with queued packets (if any)
-   * 5) search for a matching IP entry, either pending or stable
-   *    until 5 matches, or all entries are searched for.
-   */
-
-  for (i = 0; i < ARP_TABLE_SIZE; ++i) {
-    /* no empty entry found yet and now we do find one? */
-    if ((empty == ARP_TABLE_SIZE) && (arp_table[i].state == ETHARP_STATE_EMPTY)) {
-      LWIP_DEBUGF(ETHARP_DEBUG, ("find_entry: found empty entry %"U16_F"\n", (u16_t)i));
-      /* remember first empty entry */
-      empty = i;
-    }
-    /* pending entry? */
-    else if (arp_table[i].state == ETHARP_STATE_PENDING) {
-      /* if given, does IP address match IP address in ARP entry? */
-      if (ipaddr && ip_addr_cmp(ipaddr, &arp_table[i].ipaddr)) {
-        LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: found matching pending entry %"U16_F"\n", (u16_t)i));
-        /* found exact IP address match, simply bail out */
-        return i;
-#if ARP_QUEUEING
-      /* pending with queued packets? */
-      } else if (arp_table[i].p != NULL) {
-        if (arp_table[i].ctime >= age_queue) {
-          old_queue = i;
-          age_queue = arp_table[i].ctime;
-        }
-#endif
-      /* pending without queued packets? */
-      } else {
-        if (arp_table[i].ctime >= age_pending) {
-          old_pending = i;
-          age_pending = arp_table[i].ctime;
-        }
-      }        
-    }
-    /* stable entry? */
-    else if (arp_table[i].state == ETHARP_STATE_STABLE) {
-      /* if given, does IP address match IP address in ARP entry? */
-      if (ipaddr && ip_addr_cmp(ipaddr, &arp_table[i].ipaddr)) {
-        LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: found matching stable entry %"U16_F"\n", (u16_t)i));
-        /* found exact IP address match, simply bail out */
-        return i;
-      /* remember entry with oldest stable entry in oldest, its age in maxtime */
-      } else if (arp_table[i].ctime >= age_stable) {
-        old_stable = i;
-        age_stable = arp_table[i].ctime;
-      }
-    }
-  }
-  /* { we have no match } => try to create a new entry */
-   
-  /* no empty entry found and not allowed to recycle? */
-  if ((empty == ARP_TABLE_SIZE) && ((flags & ETHARP_TRY_HARD) == 0))
-  {
-  	return (s8_t)ERR_MEM;
-  }
-  
-  /* b) choose the least destructive entry to recycle:
-   * 1) empty entry
-   * 2) oldest stable entry
-   * 3) oldest pending entry without queued packets
-   * 4) oldest pending entry without queued packets
-   * 
-   * { ETHARP_TRY_HARD is set at this point }
-   */ 
-
-  /* 1) empty entry available? */
-  if (empty < ARP_TABLE_SIZE) {
-    i = empty;
-    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting empty entry %"U16_F"\n", (u16_t)i));
-  }
-  /* 2) found recyclable stable entry? */
-  else if (old_stable < ARP_TABLE_SIZE) {
-    /* recycle oldest stable*/
-    i = old_stable;
-    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting oldest stable entry %"U16_F"\n", (u16_t)i));
-#if ARP_QUEUEING
-    /* no queued packets should exist on stable entries */
-    LWIP_ASSERT("arp_table[i].p == NULL", arp_table[i].p == NULL);
-#endif
-  /* 3) found recyclable pending entry without queued packets? */
-  } else if (old_pending < ARP_TABLE_SIZE) {
-    /* recycle oldest pending */
-    i = old_pending;
-    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting oldest pending entry %"U16_F" (without queue)\n", (u16_t)i));
-#if ARP_QUEUEING
-  /* 4) found recyclable pending entry with queued packets? */
-  } else if (old_queue < ARP_TABLE_SIZE) {
-    /* recycle oldest pending */
-    i = old_queue;
-    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting oldest pending entry %"U16_F", freeing packet queue %p\n", (u16_t)i, (void *)(arp_table[i].p)));
-    pbuf_free(arp_table[i].p);
-    arp_table[i].p = NULL;
-#endif
-    /* no empty or recyclable entries found */
-  } else {
-    return (s8_t)ERR_MEM;
-  }
-
-  /* { empty or recyclable entry found } */
-  LWIP_ASSERT("i < ARP_TABLE_SIZE", i < ARP_TABLE_SIZE);
-
-  /* recycle entry (no-op for an already empty entry) */
-  arp_table[i].state = ETHARP_STATE_EMPTY;
-
-  /* IP address given? */
-  if (ipaddr != NULL) {
-    /* set IP address */
-    ip_addr_set(&arp_table[i].ipaddr, ipaddr);
-  }
-  arp_table[i].ctime = 0;
-  return (err_t)i;
-}
-
-/**
- * Update (or insert) a IP/MAC address pair in the ARP cache.
- *
- * If a pending entry is resolved, any queued packets will be sent
- * at this point.
- * 
- * @param ipaddr IP address of the inserted ARP entry.
- * @param ethaddr Ethernet address of the inserted ARP entry.
- * @param flags Defines behaviour:
- * - ETHARP_TRY_HARD Allows ARP to insert this as a new item. If not specified,
- * only existing ARP entries will be updated.
- *
- * @return
- * - ERR_OK Succesfully updated ARP cache.
- * - ERR_MEM If we could not add a new ARP entry when ETHARP_TRY_HARD was set.
- * - ERR_ARG Non-unicast address given, those will not appear in ARP cache.
- *
- * @see pbuf_free()
- */
-static err_t
-update_arp_entry(struct netif *netif, struct ip_addr *ipaddr, struct eth_addr *ethaddr, u8_t flags)
-{
-  s8_t i, k;
-  LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 3, ("update_arp_entry()\n"));
-  LWIP_ASSERT("netif->hwaddr_len != 0", netif->hwaddr_len != 0);
-  LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: %"U16_F".%"U16_F".%"U16_F".%"U16_F" - %02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F"\n",
-                                        ip4_addr1(ipaddr), ip4_addr2(ipaddr), ip4_addr3(ipaddr), ip4_addr4(ipaddr), 
-                                        ethaddr->addr[0], ethaddr->addr[1], ethaddr->addr[2],
-                                        ethaddr->addr[3], ethaddr->addr[4], ethaddr->addr[5]));
-  /* non-unicast address? */
-  if (ip_addr_isany(ipaddr) ||
-      ip_addr_isbroadcast(ipaddr, netif) ||
-      ip_addr_ismulticast(ipaddr)) {
-    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: will not add non-unicast IP address to ARP cache\n"));
-    return ERR_ARG;
-  }
-  /* find or create ARP entry */
-  i = find_entry(ipaddr, flags);
-  /* bail out if no entry could be found */
-  if (i < 0) return (err_t)i;
-  
-  /* mark it stable */
-  arp_table[i].state = ETHARP_STATE_STABLE;
-
-  LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: updating stable entry %"S16_F"\n", (s16_t)i));
-  /* update address */
-  for (k = 0; k < netif->hwaddr_len; ++k) {
-    arp_table[i].ethaddr.addr[k] = ethaddr->addr[k];
-  }
-  /* reset time stamp */
-  arp_table[i].ctime = 0;
-/* this is where we will send out queued packets! */
-#if ARP_QUEUEING
-  while (arp_table[i].p != NULL) {
-    /* get the first packet on the queue */
-    struct pbuf *p = arp_table[i].p;
-    /* Ethernet header */
-    struct eth_hdr *ethhdr = p->payload;
-    /* remember (and reference) remainder of queue */
-    /* note: this will also terminate the p pbuf chain */
-    arp_table[i].p = pbuf_dequeue(p);
-    /* fill-in Ethernet header */
-    for (k = 0; k < netif->hwaddr_len; ++k) {
-      ethhdr->dest.addr[k] = ethaddr->addr[k];
-      ethhdr->src.addr[k] = netif->hwaddr[k];
-    }
-    ethhdr->type = htons(ETHTYPE_IP);
-    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: sending queued IP packet %p.\n", (void *)p));
-    /* send the queued IP packet */
-    netif->linkoutput(netif, p);
-    /* free the queued IP packet */
-    pbuf_free(p);
-  }
-#endif
-  return ERR_OK;
-}
-
-/**
- * Updates the ARP table using the given IP packet.
- *
- * Uses the incoming IP packet's source address to update the
- * ARP cache for the local network. The function does not alter
- * or free the packet. This function must be called before the
- * packet p is passed to the IP layer.
- *
- * @param netif The lwIP network interface on which the IP packet pbuf arrived.
- * @param pbuf The IP packet that arrived on netif.
- *
- * @return NULL
- *
- * @see pbuf_free()
- */
-void
-etharp_ip_input(struct netif *netif, struct pbuf *p)
-{
-  struct ethip_hdr *hdr;
-  LWIP_ASSERT("netif != NULL", netif != NULL);
-  /* Only insert an entry if the source IP address of the
-     incoming IP packet comes from a host on the local network. */
-  hdr = p->payload;
-  /* source is not on the local network? */
-  if (!ip_addr_netcmp(&(hdr->ip.src), &(netif->ip_addr), &(netif->netmask))) {
-    /* do nothing */
-    return;
-  }
-
-  LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_ip_input: updating ETHARP table.\n"));
-  /* update ARP table */
-  /* @todo We could use ETHARP_TRY_HARD if we think we are going to talk
-   * back soon (for example, if the destination IP address is ours. */
-  update_arp_entry(netif, &(hdr->ip.src), &(hdr->eth.src), 0);
-}
-
-
-/**
- * Responds to ARP requests to us. Upon ARP replies to us, add entry to cache  
- * send out queued IP packets. Updates cache with snooped address pairs.
- *
- * Should be called for incoming ARP packets. The pbuf in the argument
- * is freed by this function.
- *
- * @param netif The lwIP network interface on which the ARP packet pbuf arrived.
- * @param pbuf The ARP packet that arrived on netif. Is freed by this function.
- * @param ethaddr Ethernet address of netif.
- *
- * @return NULL
- *
- * @see pbuf_free()
- */
-void
-etharp_arp_input(struct netif *netif, struct eth_addr *ethaddr, struct pbuf *p)
-{
-  struct etharp_hdr *hdr;
-  /* these are aligned properly, whereas the ARP header fields might not be */
-  struct ip_addr sipaddr, dipaddr;
-  u8_t i;
-  u8_t for_us;
-
-  LWIP_ASSERT("netif != NULL", netif != NULL);
-  
-  /* drop short ARP packets */
-  if (p->tot_len < sizeof(struct etharp_hdr)) {
-    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 1, ("etharp_arp_input: packet dropped, too short (%"S16_F"/%"S16_F")\n", p->tot_len, sizeof(struct etharp_hdr)));
-    pbuf_free(p);
-    return;
-  }
-
-  hdr = p->payload;
- 
-  /* get aligned copies of addresses */
-  *(struct ip_addr2 *)&sipaddr = hdr->sipaddr;
-  *(struct ip_addr2 *)&dipaddr = hdr->dipaddr;
-
-  /* this interface is not configured? */
-  if (netif->ip_addr.addr == 0) {
-    for_us = 0;
-  } else {
-    /* ARP packet directed to us? */
-    for_us = ip_addr_cmp(&dipaddr, &(netif->ip_addr));
-  }
-
-  /* ARP message directed to us? */
-  if (for_us) {
-    /* add IP address in ARP cache; assume requester wants to talk to us.
-     * can result in directly sending the queued packets for this host. */
-    update_arp_entry(netif, &sipaddr, &(hdr->shwaddr), ETHARP_TRY_HARD);
-  /* ARP message not directed to us? */
-  } else {
-    /* update the source IP address in the cache, if present */
-    update_arp_entry(netif, &sipaddr, &(hdr->shwaddr), 0);
-  }
-
-  /* now act on the message itself */
-  switch (htons(hdr->opcode)) {
-  /* ARP request? */
-  case ARP_REQUEST:
-    /* ARP request. If it asked for our address, we send out a
-     * reply. In any case, we time-stamp any existing ARP entry,
-     * and possiby send out an IP packet that was queued on it. */
-
-    LWIP_DEBUGF (ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: incoming ARP request\n"));
-    /* ARP request for our address? */
-    if (for_us) {
-
-      LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: replying to ARP request for our IP address\n"));
-      /* re-use pbuf to send ARP reply */
-      hdr->opcode = htons(ARP_REPLY);
-
-      hdr->dipaddr = hdr->sipaddr;
-      hdr->sipaddr = *(struct ip_addr2 *)&netif->ip_addr;
-
-      for(i = 0; i < netif->hwaddr_len; ++i) {
-        hdr->dhwaddr.addr[i] = hdr->shwaddr.addr[i];
-        hdr->shwaddr.addr[i] = ethaddr->addr[i];
-        hdr->ethhdr.dest.addr[i] = hdr->dhwaddr.addr[i];
-        hdr->ethhdr.src.addr[i] = ethaddr->addr[i];
-      }
-
-      hdr->hwtype = htons(HWTYPE_ETHERNET);
-      ARPH_HWLEN_SET(hdr, netif->hwaddr_len);
-
-      hdr->proto = htons(ETHTYPE_IP);
-      ARPH_PROTOLEN_SET(hdr, sizeof(struct ip_addr));
-
-      hdr->ethhdr.type = htons(ETHTYPE_ARP);
-      /* return ARP reply */
-      netif->linkoutput(netif, p);
-    /* we are not configured? */
-    } else if (netif->ip_addr.addr == 0) {
-      /* { for_us == 0 and netif->ip_addr.addr == 0 } */
-      LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: we are unconfigured, ARP request ignored.\n"));
-    /* request was not directed to us */
-    } else {
-      /* { for_us == 0 and netif->ip_addr.addr != 0 } */
-      LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: ARP request was not for us.\n"));
-    }
-    break;
-  case ARP_REPLY:
-    /* ARP reply. We already updated the ARP cache earlier. */
-    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: incoming ARP reply\n"));
-#if (LWIP_DHCP && DHCP_DOES_ARP_CHECK)
-    /* DHCP wants to know about ARP replies from any host with an
-     * IP address also offered to us by the DHCP server. We do not
-     * want to take a duplicate IP address on a single network.
-     * @todo How should we handle redundant (fail-over) interfaces?
-     * */
-    dhcp_arp_reply(netif, &sipaddr);
-#endif
-    break;
-  default:
-    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: ARP unknown opcode type %"S16_F"\n", htons(hdr->opcode)));
-    break;
-  }
-  /* free ARP packet */
-  pbuf_free(p);
-}
-
-/**
- * Resolve and fill-in Ethernet address header for outgoing packet.
- *
- * For IP multicast and broadcast, corresponding Ethernet addresses
- * are selected and the packet is transmitted on the link.
- *
- * For unicast addresses, the packet is submitted to etharp_query(). In
- * case the IP address is outside the local network, the IP address of
- * the gateway is used.
- *
- * @param netif The lwIP network interface which the IP packet will be sent on.
- * @param ipaddr The IP address of the packet destination.
- * @param pbuf The pbuf(s) containing the IP packet to be sent.
- *
- * @return
- * - ERR_RTE No route to destination (no gateway to external networks),
- * or the return type of either etharp_query() or netif->linkoutput().
- */
-err_t
-etharp_output(struct netif *netif, struct ip_addr *ipaddr, struct pbuf *q)
-{
-  struct eth_addr *dest, *srcaddr, mcastaddr;
-  struct eth_hdr *ethhdr;
-  u8_t i;
-
-  /* make room for Ethernet header - should not fail */
-  if (pbuf_header(q, sizeof(struct eth_hdr)) != 0) {
-    /* bail out */
-    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 2, ("etharp_output: could not allocate room for header.\n"));
-    LINK_STATS_INC(link.lenerr);
-    return ERR_BUF;
-  }
-
-  /* assume unresolved Ethernet address */
-  dest = NULL;
-  /* Determine on destination hardware address. Broadcasts and multicasts
-   * are special, other IP addresses are looked up in the ARP table. */
-
-  /* broadcast destination IP address? */
-  if (ip_addr_isbroadcast(ipaddr, netif)) {
-    /* broadcast on Ethernet also */
-    dest = (struct eth_addr *)ðbroadcast;
-  /* multicast destination IP address? */
-  } else if (ip_addr_ismulticast(ipaddr)) {
-    /* Hash IP multicast address to MAC address.*/
-    mcastaddr.addr[0] = 0x01;
-    mcastaddr.addr[1] = 0x00;
-    mcastaddr.addr[2] = 0x5e;
-    mcastaddr.addr[3] = ip4_addr2(ipaddr) & 0x7f;
-    mcastaddr.addr[4] = ip4_addr3(ipaddr);
-    mcastaddr.addr[5] = ip4_addr4(ipaddr);
-    /* destination Ethernet address is multicast */
-    dest = &mcastaddr;
-  /* unicast destination IP address? */
-  } else {
-    /* outside local network? */
-    if (!ip_addr_netcmp(ipaddr, &(netif->ip_addr), &(netif->netmask))) {
-      /* interface has default gateway? */
-      if (netif->gw.addr != 0) {
-        /* send to hardware address of default gateway IP address */
-        ipaddr = &(netif->gw);
-      /* no default gateway available */
-      } else {
-        /* no route to destination error (default gateway missing) */
-        return ERR_RTE;
-      }
-    }
-    /* queue on destination Ethernet address belonging to ipaddr */
-    return etharp_query(netif, ipaddr, q);
-  }
-
-  /* continuation for multicast/broadcast destinations */
-  /* obtain source Ethernet address of the given interface */
-  srcaddr = (struct eth_addr *)netif->hwaddr;
-  ethhdr = q->payload;
-  for (i = 0; i < netif->hwaddr_len; i++) {
-    ethhdr->dest.addr[i] = dest->addr[i];
-    ethhdr->src.addr[i] = srcaddr->addr[i];
-  }
-  ethhdr->type = htons(ETHTYPE_IP);
-  /* send packet directly on the link */
-  return netif->linkoutput(netif, q);
-}
-
-/**
- * Send an ARP request for the given IP address and/or queue a packet.
- *
- * If the IP address was not yet in the cache, a pending ARP cache entry
- * is added and an ARP request is sent for the given address. The packet
- * is queued on this entry.
- *
- * If the IP address was already pending in the cache, a new ARP request
- * is sent for the given address. The packet is queued on this entry.
- *
- * If the IP address was already stable in the cache, and a packet is
- * given, it is directly sent and no ARP request is sent out. 
- * 
- * If the IP address was already stable in the cache, and no packet is
- * given, an ARP request is sent out.
- * 
- * @param netif The lwIP network interface on which ipaddr
- * must be queried for.
- * @param ipaddr The IP address to be resolved.
- * @param q If non-NULL, a pbuf that must be delivered to the IP address.
- * q is not freed by this function.
- *
- * @return
- * - ERR_BUF Could not make room for Ethernet header.
- * - ERR_MEM Hardware address unknown, and no more ARP entries available
- *   to query for address or queue the packet.
- * - ERR_MEM Could not queue packet due to memory shortage.
- * - ERR_RTE No route to destination (no gateway to external networks).
- * - ERR_ARG Non-unicast address given, those will not appear in ARP cache.
- *
- */
-err_t etharp_query(struct netif *netif, struct ip_addr *ipaddr, struct pbuf *q)
-{
-  struct eth_addr * srcaddr = (struct eth_addr *)netif->hwaddr;
-  err_t result = ERR_MEM;
-  s8_t i; /* ARP entry index */
-  u8_t k; /* Ethernet address octet index */
-
-  /* non-unicast address? */
-  if (ip_addr_isbroadcast(ipaddr, netif) ||
-      ip_addr_ismulticast(ipaddr) ||
-      ip_addr_isany(ipaddr)) {
-    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: will not add non-unicast IP address to ARP cache\n"));
-    return ERR_ARG;
-  }
-
-  /* find entry in ARP cache, ask to create entry if queueing packet */
-  i = find_entry(ipaddr, ETHARP_TRY_HARD);
-
-  /* could not find or create entry? */
-  if (i < 0)
-  {
-    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: could not create ARP entry\n"));
-    if (q) LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: packet dropped\n"));
-    return (err_t)i;
-  }
-
-  /* mark a fresh entry as pending (we just sent a request) */
-  if (arp_table[i].state == ETHARP_STATE_EMPTY) {
-    arp_table[i].state = ETHARP_STATE_PENDING;
-  }
-
-  /* { i is either a STABLE or (new or existing) PENDING entry } */
-  LWIP_ASSERT("arp_table[i].state == PENDING or STABLE",
-  ((arp_table[i].state == ETHARP_STATE_PENDING) ||
-   (arp_table[i].state == ETHARP_STATE_STABLE)));
-
-  /* do we have a pending entry? or an implicit query request? */
-  if ((arp_table[i].state == ETHARP_STATE_PENDING) || (q == NULL)) {
-    /* try to resolve it; send out ARP request */
-    result = etharp_request(netif, ipaddr);
-  }
-  
-  /* packet given? */
-  if (q != NULL) {
-    /* stable entry? */
-    if (arp_table[i].state == ETHARP_STATE_STABLE) {
-      /* we have a valid IP->Ethernet address mapping,
-       * fill in the Ethernet header for the outgoing packet */
-      struct eth_hdr *ethhdr = q->payload;
-      for(k = 0; k < netif->hwaddr_len; k++) {
-        ethhdr->dest.addr[k] = arp_table[i].ethaddr.addr[k];
-        ethhdr->src.addr[k]  = srcaddr->addr[k];
-      }
-      ethhdr->type = htons(ETHTYPE_IP);
-      LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: sending packet %p\n", (void *)q));
-      /* send the packet */
-      result = netif->linkoutput(netif, q);
-    /* pending entry? (either just created or already pending */
-    } else if (arp_table[i].state == ETHARP_STATE_PENDING) {
-#if ARP_QUEUEING /* queue the given q packet */
-      struct pbuf *p;
-      /* copy any PBUF_REF referenced payloads into PBUF_RAM */
-      /* (the caller of lwIP assumes the referenced payload can be
-       * freed after it returns from the lwIP call that brought us here) */
-      p = pbuf_take(q);
-      /* packet could be taken over? */
-      if (p != NULL) {
-        /* queue packet ... */
-        if (arp_table[i].p == NULL) {
-        	/* ... in the empty queue */
-        	pbuf_ref(p);
-        	arp_table[i].p = p;
-#if 0 /* multi-packet-queueing disabled, see bug #11400 */
-        } else {
-        	/* ... at tail of non-empty queue */
-          pbuf_queue(arp_table[i].p, p);
-#endif
-        }
-        LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: queued packet %p on ARP entry %"S16_F"\n", (void *)q, (s16_t)i));
-        result = ERR_OK;
-      } else {
-        LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q));
-        /* { result == ERR_MEM } through initialization */
-      }
-#else /* ARP_QUEUEING == 0 */
-      /* q && state == PENDING && ARP_QUEUEING == 0 => result = ERR_MEM */
-      /* { result == ERR_MEM } through initialization */
-      LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: Ethernet destination address unknown, queueing disabled, packet %p dropped\n", (void *)q));
-#endif
-    }
-  }
-  return result;
-}
-
-err_t etharp_request(struct netif *netif, struct ip_addr *ipaddr)
-{
-  struct pbuf *p;
-  struct eth_addr * srcaddr = (struct eth_addr *)netif->hwaddr;
-  err_t result = ERR_OK;
-  u8_t k; /* ARP entry index */
-
-  /* allocate a pbuf for the outgoing ARP request packet */
-  p = pbuf_alloc(PBUF_LINK, sizeof(struct etharp_hdr), PBUF_RAM);
-  /* could allocate a pbuf for an ARP request? */
-  if (p != NULL) {
-    struct etharp_hdr *hdr = p->payload;
-    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_request: sending ARP request.\n"));
-    hdr->opcode = htons(ARP_REQUEST);
-    for (k = 0; k < netif->hwaddr_len; k++)
-    {
-      hdr->shwaddr.addr[k] = srcaddr->addr[k];
-      /* the hardware address is what we ask for, in
-       * a request it is a don't-care value, we use zeroes */
-      hdr->dhwaddr.addr[k] = 0x00;
-    }
-    hdr->dipaddr = *(struct ip_addr2 *)ipaddr;
-    hdr->sipaddr = *(struct ip_addr2 *)&netif->ip_addr;
-
-    hdr->hwtype = htons(HWTYPE_ETHERNET);
-    ARPH_HWLEN_SET(hdr, netif->hwaddr_len);
-
-    hdr->proto = htons(ETHTYPE_IP);
-    ARPH_PROTOLEN_SET(hdr, sizeof(struct ip_addr));
-    for (k = 0; k < netif->hwaddr_len; ++k)
-    {
-      /* broadcast to all network interfaces on the local network */
-      hdr->ethhdr.dest.addr[k] = 0xff;
-      hdr->ethhdr.src.addr[k] = srcaddr->addr[k];
-    }
-    hdr->ethhdr.type = htons(ETHTYPE_ARP);
-    /* send ARP query */
-    result = netif->linkoutput(netif, p);
-    /* free ARP query packet */
-    pbuf_free(p);
-    p = NULL;
-  /* could not allocate pbuf for ARP request */
-  } else {
-    result = ERR_MEM;
-    LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 2, ("etharp_request: could not allocate pbuf for ARP request.\n"));
-  }
-  return result;
-}
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ethernetif.c b/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ethernetif.c
deleted file mode 100644
index 0c14e8de5..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ethernetif.c
+++ /dev/null
@@ -1,306 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-
-/*
- * This file is a skeleton for developing Ethernet network interface
- * drivers for lwIP. Add code to the low_level functions and do a
- * search-and-replace for the word "ethernetif" to replace it with
- * something that better describes your network interface.
- */
-
-#include "lwip/opt.h"
-#include "lwip/def.h"
-#include "lwip/mem.h"
-#include "lwip/pbuf.h"
-#include "lwip/sys.h"
-#include 
-
-#include "netif/etharp.h"
-
-/* Define those to better describe your network interface. */
-#define IFNAME0 'e'
-#define IFNAME1 'n'
-
-struct ethernetif {
-  struct eth_addr *ethaddr;
-  /* Add whatever per-interface state that is needed here. */
-};
-
-static const struct eth_addr ethbroadcast = {{0xff,0xff,0xff,0xff,0xff,0xff}};
-
-/* Forward declarations. */
-static void  ethernetif_input(struct netif *netif);
-static err_t ethernetif_output(struct netif *netif, struct pbuf *p,
-             struct ip_addr *ipaddr);
-
-static void
-low_level_init(struct netif *netif)
-{
-  struct ethernetif *ethernetif = netif->state;
-  
-  /* set MAC hardware address length */
-  netif->hwaddr_len = 6;
-
-  /* set MAC hardware address */
-  netif->hwaddr[0] = ;
-  ...
-  netif->hwaddr[5] = ;
-
-  /* maximum transfer unit */
-  netif->mtu = 1500;
-  
-  /* broadcast capability */
-  netif->flags = NETIF_FLAG_BROADCAST;
- 
-  /* Do whatever else is needed to initialize interface. */  
-}
-
-/*
- * low_level_output():
- *
- * Should do the actual transmission of the packet. The packet is
- * contained in the pbuf that is passed to the function. This pbuf
- * might be chained.
- *
- */
-
-static err_t
-low_level_output(struct netif *netif, struct pbuf *p)
-{
-  struct ethernetif *ethernetif = netif->state;
-  struct pbuf *q;
-
-  initiate transfer();
-  
-#if ETH_PAD_SIZE
-  pbuf_header(p, -ETH_PAD_SIZE);			/* drop the padding word */
-#endif
-
-  for(q = p; q != NULL; q = q->next) {
-    /* Send the data from the pbuf to the interface, one pbuf at a
-       time. The size of the data in each pbuf is kept in the ->len
-       variable. */
-    send data from(q->payload, q->len);
-  }
-
-  signal that packet should be sent();
-
-#if ETH_PAD_SIZE
-  pbuf_header(p, ETH_PAD_SIZE);			/* reclaim the padding word */
-#endif
-  
-#if LINK_STATS
-  lwip_stats.link.xmit++;
-#endif /* LINK_STATS */      
-
-  return ERR_OK;
-}
-
-/*
- * low_level_input():
- *
- * Should allocate a pbuf and transfer the bytes of the incoming
- * packet from the interface into the pbuf.
- *
- */
-
-static struct pbuf *
-low_level_input(struct netif *netif)
-{
-  struct ethernetif *ethernetif = netif->state;
-  struct pbuf *p, *q;
-  u16_t len;
-
-  /* Obtain the size of the packet and put it into the "len"
-     variable. */
-  len = ;
-
-#if ETH_PAD_SIZE
-  len += ETH_PAD_SIZE;						/* allow room for Ethernet padding */
-#endif
-
-  /* We allocate a pbuf chain of pbufs from the pool. */
-  p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
-  
-  if (p != NULL) {
-
-#if ETH_PAD_SIZE
-    pbuf_header(p, -ETH_PAD_SIZE);			/* drop the padding word */
-#endif
-
-    /* We iterate over the pbuf chain until we have read the entire
-     * packet into the pbuf. */
-    for(q = p; q != NULL; q = q->next) {
-      /* Read enough bytes to fill this pbuf in the chain. The
-       * available data in the pbuf is given by the q->len
-       * variable. */
-      read data into(q->payload, q->len);
-    }
-    acknowledge that packet has been read();
-
-#if ETH_PAD_SIZE
-    pbuf_header(p, ETH_PAD_SIZE);			/* reclaim the padding word */
-#endif
-
-#if LINK_STATS
-    lwip_stats.link.recv++;
-#endif /* LINK_STATS */      
-  } else {
-    drop packet();
-#if LINK_STATS
-    lwip_stats.link.memerr++;
-    lwip_stats.link.drop++;
-#endif /* LINK_STATS */      
-  }
-
-  return p;  
-}
-
-/*
- * ethernetif_output():
- *
- * This function is called by the TCP/IP stack when an IP packet
- * should be sent. It calls the function called low_level_output() to
- * do the actual transmission of the packet.
- *
- */
-
-static err_t
-ethernetif_output(struct netif *netif, struct pbuf *p,
-      struct ip_addr *ipaddr)
-{
-  
- /* resolve hardware address, then send (or queue) packet */
-  return etharp_output(netif, ipaddr, p);
- 
-}
-
-/*
- * ethernetif_input():
- *
- * This function should be called when a packet is ready to be read
- * from the interface. It uses the function low_level_input() that
- * should handle the actual reception of bytes from the network
- * interface.
- *
- */
-
-static void
-ethernetif_input(struct netif *netif)
-{
-  struct ethernetif *ethernetif;
-  struct eth_hdr *ethhdr;
-  struct pbuf *p;
-
-  ethernetif = netif->state;
-  
-  /* move received packet into a new pbuf */
-  p = low_level_input(netif);
-  /* no packet could be read, silently ignore this */
-  if (p == NULL) return;
-  /* points to packet payload, which starts with an Ethernet header */
-  ethhdr = p->payload;
-
-#if LINK_STATS
-  lwip_stats.link.recv++;
-#endif /* LINK_STATS */
-
-  ethhdr = p->payload;
-    
-  switch (htons(ethhdr->type)) {
-  /* IP packet? */
-  case ETHTYPE_IP:
-    /* update ARP table */
-    etharp_ip_input(netif, p);
-    /* skip Ethernet header */
-    pbuf_header(p, -sizeof(struct eth_hdr));
-    /* pass to network layer */
-    netif->input(p, netif);
-    break;
-      
-    case ETHTYPE_ARP:
-      /* pass p to ARP module  */
-      etharp_arp_input(netif, ethernetif->ethaddr, p);
-      break;
-    default:
-      pbuf_free(p);
-      p = NULL;
-      break;
-  }
-}
-
-static void
-arp_timer(void *arg)
-{
-  etharp_tmr();
-  sys_timeout(ARP_TMR_INTERVAL, arp_timer, NULL);
-}
-
-/*
- * ethernetif_init():
- *
- * Should be called at the beginning of the program to set up the
- * network interface. It calls the function low_level_init() to do the
- * actual setup of the hardware.
- *
- */
-
-err_t
-ethernetif_init(struct netif *netif)
-{
-  struct ethernetif *ethernetif;
-    
-  ethernetif = mem_malloc(sizeof(struct ethernetif));
-  
-  if (ethernetif == NULL)
-  {
-  	LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_init: out of memory\n"));
-  	return ERR_MEM;
-  }
-  
-  netif->state = ethernetif;
-  netif->name[0] = IFNAME0;
-  netif->name[1] = IFNAME1;
-  netif->output = ethernetif_output;
-  netif->linkoutput = low_level_output;
-  
-  ethernetif->ethaddr = (struct eth_addr *)&(netif->hwaddr[0]);
-  
-  low_level_init(netif);
-
-  etharp_init();
-
-  sys_timeout(ARP_TMR_INTERVAL, arp_timer, NULL);
-
-  return ERR_OK;
-}
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/loopif.c b/Demo/lwIP_MCF5235_GCC/lwip/src/netif/loopif.c
deleted file mode 100644
index 0464cb8e8..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/loopif.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels 
- *
- */
-#include "lwip/opt.h"
-
-#if LWIP_HAVE_LOOPIF
-
-#include "netif/loopif.h"
-#include "lwip/mem.h"
-
-#if defined(LWIP_DEBUG) && defined(LWIP_TCPDUMP)
-#include "netif/tcpdump.h"
-#endif /* LWIP_DEBUG && LWIP_TCPDUMP */
-
-#include "lwip/tcp.h"
-#include "lwip/ip.h"
-
-static void
-loopif_input( void * arg )
-{
-	struct netif *netif = (struct netif *)( ((void **)arg)[ 0 ] );
-	struct pbuf *r = (struct pbuf *)( ((void **)arg)[ 1 ] );
-
-	mem_free( arg );
-	netif -> input( r, netif );
-}
-
-static err_t
-loopif_output(struct netif *netif, struct pbuf *p,
-       struct ip_addr *ipaddr)
-{
-  struct pbuf *q, *r;
-  u8_t *ptr;
-  void **arg;
-
-#if defined(LWIP_DEBUG) && defined(LWIP_TCPDUMP)
-  tcpdump(p);
-#endif /* LWIP_DEBUG && LWIP_TCPDUMP */
-  
-  r = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM);
-  if (r != NULL) {
-    ptr = r->payload;
-    
-    for(q = p; q != NULL; q = q->next) {
-      memcpy(ptr, q->payload, q->len);
-      ptr += q->len;
-    }
-
-    arg = mem_malloc( sizeof( void *[2]));
-	if( NULL == arg ) {
-		return ERR_MEM;
-	}
-	
-	arg[0] = netif;
-	arg[1] = r;
-	/**
-	 * workaround (patch #1779) to try to prevent bug #2595:
-	 * When connecting to "localhost" with the loopif interface,
-	 * tcp_output doesn't get the opportunity to finnish sending the
-	 * segment before tcp_process gets it, resulting in tcp_process
-	 * referencing pcb->unacked-> which still is NULL.
-	 * 
-	 * TODO: Is there still a race condition here? Leon
-	 */
-	sys_timeout( 1, loopif_input, arg );
-	
-    return ERR_OK;    
-  }
-  return ERR_MEM;
-}
-
-err_t
-loopif_init(struct netif *netif)
-{
-  netif->name[0] = 'l';
-  netif->name[1] = 'o';
-#if 0 /** TODO: I think this should be enabled, or not? Leon */
-  netif->input = loopif_input;
-#endif
-  netif->output = loopif_output;
-  return ERR_OK;
-}
-
-#endif /* LWIP_HAVE_LOOPIF */
-
-
-
-
-
-
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/auth.c b/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/auth.c
deleted file mode 100644
index 333496402..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/auth.c
+++ /dev/null
@@ -1,927 +0,0 @@
-/*****************************************************************************
-* auth.c - Network Authentication and Phase Control program file.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* Copyright (c) 1997 by Global Election Systems Inc.  All rights reserved.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY
-*
-* 03-01-01 Marc Boucher 
-*   Ported to lwIP.
-* 97-12-08 Guy Lancaster , Global Election Systems Inc.
-*   Ported from public pppd code.
-*****************************************************************************/
-/*
- * auth.c - PPP authentication and phase control.
- *
- * Copyright (c) 1993 The Australian National University.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by the Australian National University.  The name of the University
- * may not be used to endorse or promote products derived from this
- * software without specific prior written permission.
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- *
- * Copyright (c) 1989 Carnegie Mellon University.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by Carnegie Mellon University.  The name of the
- * University may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- */
-
-#include "ppp.h"
-#if PPP_SUPPORT > 0
-#include "fsm.h"
-#include "lcp.h"
-#include "pap.h"
-#include "chap.h"
-#include "auth.h"
-#include "ipcp.h"
-
-#if CBCP_SUPPORT > 0
-#include "cbcp.h"
-#endif
-
-#include "pppdebug.h"
-
-
-/*************************/
-/*** LOCAL DEFINITIONS ***/
-/*************************/
-
-/* Bits in auth_pending[] */
-#define PAP_WITHPEER    1
-#define PAP_PEER    2
-#define CHAP_WITHPEER   4
-#define CHAP_PEER   8
-
-
-                                                                    
-/************************/
-/*** LOCAL DATA TYPES ***/
-/************************/
-/* Used for storing a sequence of words.  Usually malloced. */
-struct wordlist {
-    struct wordlist *next;
-    char        word[1];
-};
-
-
-
-/***********************************/
-/*** LOCAL FUNCTION DECLARATIONS ***/
-/***********************************/
-extern char *crypt (const char *, const char *);
-
-/* Prototypes for procedures local to this file. */
-
-static void network_phase (int);
-static void check_idle (void *);
-static void connect_time_expired (void *);
-#if 0
-static int  login (char *, char *, char **, int *);
-#endif
-static void logout (void);
-static int  null_login (int);
-static int  get_pap_passwd (int, char *, char *);
-static int  have_pap_secret (void);
-static int  have_chap_secret (char *, char *, u32_t);
-static int  ip_addr_check (u32_t, struct wordlist *);
-#if 0 /* PAP_SUPPORT > 0 || CHAP_SUPPORT > 0 */
-static void set_allowed_addrs(int unit, struct wordlist *addrs);
-static void free_wordlist (struct wordlist *);
-#endif
-#if CBCP_SUPPORT > 0
-static void callback_phase (int);
-#endif
-
-
-/******************************/
-/*** PUBLIC DATA STRUCTURES ***/
-/******************************/
-
-
-/*****************************/
-/*** LOCAL DATA STRUCTURES ***/
-/*****************************/
-#if PAP_SUPPORT > 0 || CHAP_SUPPORT > 0
-/* The name by which the peer authenticated itself to us. */
-static char peer_authname[MAXNAMELEN];
-#endif
-
-/* Records which authentication operations haven't completed yet. */
-static int auth_pending[NUM_PPP];
-
-/* Set if we have successfully called login() */
-static int logged_in;
-
-/* Set if we have run the /etc/ppp/auth-up script. */
-static int did_authup;
-
-/* List of addresses which the peer may use. */
-static struct wordlist *addresses[NUM_PPP];
-
-/* Number of network protocols which we have opened. */
-static int num_np_open;
-
-/* Number of network protocols which have come up. */
-static int num_np_up;
-
-#if PAP_SUPPORT > 0 || CHAP_SUPPORT > 0
-/* Set if we got the contents of passwd[] from the pap-secrets file. */
-static int passwd_from_file;
-#endif
-
-
-
-/***********************************/
-/*** PUBLIC FUNCTION DEFINITIONS ***/
-/***********************************/
-/*
- * An Open on LCP has requested a change from Dead to Establish phase.
- * Do what's necessary to bring the physical layer up.
- */
-void link_required(int unit)
-{
-    AUTHDEBUG((LOG_INFO, "link_required: %d\n", unit));
-}
-
-/*
- * LCP has terminated the link; go to the Dead phase and take the
- * physical layer down.
- */
-void link_terminated(int unit)
-{
-    AUTHDEBUG((LOG_INFO, "link_terminated: %d\n", unit));
-    
-    if (lcp_phase[unit] == PHASE_DEAD)
-        return;
-    if (logged_in)
-        logout();
-    lcp_phase[unit] = PHASE_DEAD;
-    AUTHDEBUG((LOG_NOTICE, "Connection terminated.\n"));
-	pppMainWakeup(unit);
-}
-
-/*
- * LCP has gone down; it will either die or try to re-establish.
- */
-void link_down(int unit)
-{
-    int i;
-    struct protent *protp;
-    
-    AUTHDEBUG((LOG_INFO, "link_down: %d\n", unit));
-    if (did_authup) {
-        /* XXX Do link down processing. */
-        did_authup = 0;
-    }
-    for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) {
-        if (!protp->enabled_flag)
-            continue;
-        if (protp->protocol != PPP_LCP && protp->lowerdown != NULL)
-            (*protp->lowerdown)(unit);
-        if (protp->protocol < 0xC000 && protp->close != NULL)
-            (*protp->close)(unit, "LCP down");
-    }
-    num_np_open = 0;
-    num_np_up = 0;
-    if (lcp_phase[unit] != PHASE_DEAD)
-        lcp_phase[unit] = PHASE_TERMINATE;
-	pppMainWakeup(unit);
-}
-
-/*
- * The link is established.
- * Proceed to the Dead, Authenticate or Network phase as appropriate.
- */
-void link_established(int unit)
-{
-    int auth;
-    int i;
-    struct protent *protp;
-    lcp_options *wo = &lcp_wantoptions[unit];
-    lcp_options *go = &lcp_gotoptions[unit];
-#if PAP_SUPPORT > 0 || CHAP_SUPPORT > 0
-    lcp_options *ho = &lcp_hisoptions[unit];
-#endif
-    
-    AUTHDEBUG((LOG_INFO, "link_established: %d\n", unit));
-    /*
-     * Tell higher-level protocols that LCP is up.
-     */
-    for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i)
-        if (protp->protocol != PPP_LCP && protp->enabled_flag
-                && protp->lowerup != NULL)
-            (*protp->lowerup)(unit);
-    
-    if (ppp_settings.auth_required && !(go->neg_chap || go->neg_upap)) {
-        /*
-         * We wanted the peer to authenticate itself, and it refused:
-         * treat it as though it authenticated with PAP using a username
-         * of "" and a password of "".  If that's not OK, boot it out.
-         */
-        if (!wo->neg_upap || !null_login(unit)) {
-            AUTHDEBUG((LOG_WARNING, "peer refused to authenticate\n"));
-            lcp_close(unit, "peer refused to authenticate");
-            return;
-        }
-    }
-    
-    lcp_phase[unit] = PHASE_AUTHENTICATE;
-    auth = 0;
-#if CHAP_SUPPORT > 0
-    if (go->neg_chap) {
-        ChapAuthPeer(unit, ppp_settings.our_name, go->chap_mdtype);
-        auth |= CHAP_PEER;
-    } 
-#endif
-#if PAP_SUPPORT > 0 && CHAP_SUPPORT > 0
-    else
-#endif
-#if PAP_SUPPORT > 0
-    if (go->neg_upap) {
-        upap_authpeer(unit);
-        auth |= PAP_PEER;
-    }
-#endif
-#if CHAP_SUPPORT > 0
-    if (ho->neg_chap) {
-        ChapAuthWithPeer(unit, ppp_settings.user, ho->chap_mdtype);
-        auth |= CHAP_WITHPEER;
-    }
-#endif
-#if PAP_SUPPORT > 0 && CHAP_SUPPORT > 0
-    else
-#endif
-#if PAP_SUPPORT > 0
-    if (ho->neg_upap) {
-        if (ppp_settings.passwd[0] == 0) {
-            passwd_from_file = 1;
-            if (!get_pap_passwd(unit, ppp_settings.user, ppp_settings.passwd))
-                AUTHDEBUG((LOG_ERR, "No secret found for PAP login\n"));
-        }
-        upap_authwithpeer(unit, ppp_settings.user, ppp_settings.passwd);
-        auth |= PAP_WITHPEER;
-    }
-#endif
-    auth_pending[unit] = auth;
-    
-    if (!auth)
-        network_phase(unit);
-}
-
-
-/*
- * The peer has failed to authenticate himself using `protocol'.
- */
-void auth_peer_fail(int unit, u16_t protocol)
-{
-    AUTHDEBUG((LOG_INFO, "auth_peer_fail: %d proto=%X\n", unit, protocol));
-    /*
-     * Authentication failure: take the link down
-     */
-    lcp_close(unit, "Authentication failed");
-}
-
-
-#if PAP_SUPPORT > 0 || CHAP_SUPPORT > 0
-/*
- * The peer has been successfully authenticated using `protocol'.
- */
-void auth_peer_success(int unit, u16_t protocol, char *name, int namelen)
-{
-    int pbit;
-    
-    AUTHDEBUG((LOG_INFO, "auth_peer_success: %d proto=%X\n", unit, protocol));
-    switch (protocol) {
-    case PPP_CHAP:
-        pbit = CHAP_PEER;
-        break;
-    case PPP_PAP:
-        pbit = PAP_PEER;
-        break;
-    default:
-        AUTHDEBUG((LOG_WARNING, "auth_peer_success: unknown protocol %x\n",
-               protocol));
-        return;
-    }
-    
-    /*
-     * Save the authenticated name of the peer for later.
-     */
-    if (namelen > sizeof(peer_authname) - 1)
-        namelen = sizeof(peer_authname) - 1;
-    BCOPY(name, peer_authname, namelen);
-    peer_authname[namelen] = 0;
-    
-    /*
-     * If there is no more authentication still to be done,
-     * proceed to the network (or callback) phase.
-     */
-    if ((auth_pending[unit] &= ~pbit) == 0)
-        network_phase(unit);
-}
-
-/*
- * We have failed to authenticate ourselves to the peer using `protocol'.
- */
-void auth_withpeer_fail(int unit, u16_t protocol)
-{
-    int errCode = PPPERR_AUTHFAIL;
-    
-    AUTHDEBUG((LOG_INFO, "auth_withpeer_fail: %d proto=%X\n", unit, protocol));
-    if (passwd_from_file)
-        BZERO(ppp_settings.passwd, MAXSECRETLEN);
-    /* 
-     * XXX Warning: the unit number indicates the interface which is
-     * not necessarily the PPP connection.  It works here as long
-     * as we are only supporting PPP interfaces.
-     */
-    pppIOCtl(unit, PPPCTLS_ERRCODE, &errCode);
-
-    /*
-     * We've failed to authenticate ourselves to our peer.
-     * He'll probably take the link down, and there's not much
-     * we can do except wait for that.
-     */
-}
-
-/*
- * We have successfully authenticated ourselves with the peer using `protocol'.
- */
-void auth_withpeer_success(int unit, u16_t protocol)
-{
-    int pbit;
-    
-    AUTHDEBUG((LOG_INFO, "auth_withpeer_success: %d proto=%X\n", unit, protocol));
-    switch (protocol) {
-    case PPP_CHAP:
-        pbit = CHAP_WITHPEER;
-        break;
-    case PPP_PAP:
-        if (passwd_from_file)
-            BZERO(ppp_settings.passwd, MAXSECRETLEN);
-        pbit = PAP_WITHPEER;
-        break;
-    default:
-        AUTHDEBUG((LOG_WARNING, "auth_peer_success: unknown protocol %x\n",
-               protocol));
-        pbit = 0;
-    }
-    
-    /*
-     * If there is no more authentication still being done,
-     * proceed to the network (or callback) phase.
-     */
-    if ((auth_pending[unit] &= ~pbit) == 0)
-        network_phase(unit);
-}
-#endif
-
-
-/*
- * np_up - a network protocol has come up.
- */
-void np_up(int unit, u16_t proto)
-{
-    AUTHDEBUG((LOG_INFO, "np_up: %d proto=%X\n", unit, proto));
-    if (num_np_up == 0) {
-	AUTHDEBUG((LOG_INFO, "np_up: maxconnect=%d idle_time_limit=%d\n",ppp_settings.maxconnect,ppp_settings.idle_time_limit));
-        /*
-         * At this point we consider that the link has come up successfully.
-         */
-        if (ppp_settings.idle_time_limit > 0)
-            TIMEOUT(check_idle, NULL, ppp_settings.idle_time_limit);
-        
-        /*
-         * Set a timeout to close the connection once the maximum
-         * connect time has expired.
-         */
-        if (ppp_settings.maxconnect > 0)
-            TIMEOUT(connect_time_expired, 0, ppp_settings.maxconnect);
-    }
-    ++num_np_up;
-}
-
-/*
- * np_down - a network protocol has gone down.
- */
-void np_down(int unit, u16_t proto)
-{
-    AUTHDEBUG((LOG_INFO, "np_down: %d proto=%X\n", unit, proto));
-    if (--num_np_up == 0 && ppp_settings.idle_time_limit > 0) {
-        UNTIMEOUT(check_idle, NULL);
-    }
-}
-
-/*
- * np_finished - a network protocol has finished using the link.
- */
-void np_finished(int unit, u16_t proto)
-{
-    AUTHDEBUG((LOG_INFO, "np_finished: %d proto=%X\n", unit, proto));
-    if (--num_np_open <= 0) {
-        /* no further use for the link: shut up shop. */
-        lcp_close(0, "No network protocols running");
-    }
-}
-
-/*
- * auth_reset - called when LCP is starting negotiations to recheck
- * authentication options, i.e. whether we have appropriate secrets
- * to use for authenticating ourselves and/or the peer.
- */
-void auth_reset(int unit)
-{
-    lcp_options *go = &lcp_gotoptions[unit];
-    lcp_options *ao = &lcp_allowoptions[0];
-    ipcp_options *ipwo = &ipcp_wantoptions[0];
-    u32_t remote;
-    
-    AUTHDEBUG((LOG_INFO, "auth_reset: %d\n", unit));
-    ao->neg_upap = !ppp_settings.refuse_pap && (ppp_settings.passwd[0] != 0 || get_pap_passwd(unit, NULL, NULL));
-    ao->neg_chap = !ppp_settings.refuse_chap && ppp_settings.passwd[0] != 0 /*have_chap_secret(ppp_settings.user, ppp_settings.remote_name, (u32_t)0)*/;
-    
-    if (go->neg_upap && !have_pap_secret())
-        go->neg_upap = 0;
-    if (go->neg_chap) {
-        remote = ipwo->accept_remote? 0: ipwo->hisaddr;
-        if (!have_chap_secret(ppp_settings.remote_name, ppp_settings.our_name, remote))
-            go->neg_chap = 0;
-    }
-}
-
-
-#if PAP_SUPPORT > 0
-/*
- * check_passwd - Check the user name and passwd against the PAP secrets
- * file.  If requested, also check against the system password database,
- * and login the user if OK.
- *
- * returns:
- *  UPAP_AUTHNAK: Authentication failed.
- *  UPAP_AUTHACK: Authentication succeeded.
- * In either case, msg points to an appropriate message.
- */
-int check_passwd(
-	int unit,
-	char *auser,
-	int userlen,
-	char *apasswd,
-	int passwdlen,
-	char **msg,
-	int *msglen
-)
-{
-#if 1
-	*msg = (char *) 0;
-	return UPAP_AUTHACK;     /* XXX Assume all entries OK. */
-#else
-    int ret = 0;
-    struct wordlist *addrs = NULL;
-    char passwd[256], user[256];
-    char secret[MAXWORDLEN];
-    static u_short attempts = 0;
-    
-    /*
-     * Make copies of apasswd and auser, then null-terminate them.
-     */
-    BCOPY(apasswd, passwd, passwdlen);
-    passwd[passwdlen] = '\0';
-    BCOPY(auser, user, userlen);
-    user[userlen] = '\0';
-    *msg = (char *) 0;
-
-    /* XXX Validate user name and password. */
-    ret = UPAP_AUTHACK;     /* XXX Assume all entries OK. */
-        
-    if (ret == UPAP_AUTHNAK) {
-        if (*msg == (char *) 0)
-            *msg = "Login incorrect";
-        *msglen = strlen(*msg);
-        /*
-         * Frustrate passwd stealer programs.
-         * Allow 10 tries, but start backing off after 3 (stolen from login).
-         * On 10'th, drop the connection.
-         */
-        if (attempts++ >= 10) {
-            AUTHDEBUG((LOG_WARNING, "%d LOGIN FAILURES BY %s\n", attempts, user));
-            /*ppp_panic("Excess Bad Logins");*/
-        }
-        if (attempts > 3) {
-            sys_msleep((attempts - 3) * 5);
-        }
-        if (addrs != NULL) {
-            free_wordlist(addrs);
-        }
-    } else {
-        attempts = 0;           /* Reset count */
-        if (*msg == (char *) 0)
-            *msg = "Login ok";
-        *msglen = strlen(*msg);
-        set_allowed_addrs(unit, addrs);
-    }
-    
-    BZERO(passwd, sizeof(passwd));
-    BZERO(secret, sizeof(secret));
-    
-    return ret;
-#endif
-}
-#endif
-
-
-/*
- * auth_ip_addr - check whether the peer is authorized to use
- * a given IP address.  Returns 1 if authorized, 0 otherwise.
- */
-int auth_ip_addr(int unit, u32_t addr)
-{
-    return ip_addr_check(addr, addresses[unit]);
-}
-
-/*
- * bad_ip_adrs - return 1 if the IP address is one we don't want
- * to use, such as an address in the loopback net or a multicast address.
- * addr is in network byte order.
- */
-int bad_ip_adrs(u32_t addr)
-{
-    addr = ntohl(addr);
-    return (addr >> IN_CLASSA_NSHIFT) == IN_LOOPBACKNET
-        || IN_MULTICAST(addr) || IN_BADCLASS(addr);
-}
-
-
-#if CHAP_SUPPORT > 0
-/*
- * get_secret - open the CHAP secret file and return the secret
- * for authenticating the given client on the given server.
- * (We could be either client or server).
- */
-int get_secret(
-    int unit,
-    char *client,
-    char *server,
-    char *secret,
-    int *secret_len,
-    int save_addrs
-)
-{
-#if 1
-    int len;
-    struct wordlist *addrs;
-    
-    addrs = NULL;
-
-    if(!client || !client[0] || strcmp(client, ppp_settings.user)) {
-	return 0;
-    }
-
-    len = strlen(ppp_settings.passwd);
-    if (len > MAXSECRETLEN) {
-        AUTHDEBUG((LOG_ERR, "Secret for %s on %s is too long\n", client, server));
-        len = MAXSECRETLEN;
-    }
-    BCOPY(ppp_settings.passwd, secret, len);
-    *secret_len = len;
-    
-    return 1;
-#else
-    int ret = 0, len;
-    struct wordlist *addrs;
-    char secbuf[MAXWORDLEN];
-    
-    addrs = NULL;
-    secbuf[0] = 0;
-
-    /* XXX Find secret. */  
-    if (ret < 0)
-        return 0;
-    
-    if (save_addrs)
-        set_allowed_addrs(unit, addrs);
-    
-    len = strlen(secbuf);
-    if (len > MAXSECRETLEN) {
-        AUTHDEBUG((LOG_ERR, "Secret for %s on %s is too long\n", client, server));
-        len = MAXSECRETLEN;
-    }
-    BCOPY(secbuf, secret, len);
-    BZERO(secbuf, sizeof(secbuf));
-    *secret_len = len;
-    
-    return 1;
-#endif
-}
-#endif
-
-
-#if 0 /* UNUSED */
-/*
- * auth_check_options - called to check authentication options.
- */
-void auth_check_options(void)
-{
-    lcp_options *wo = &lcp_wantoptions[0];
-    int can_auth;
-    ipcp_options *ipwo = &ipcp_wantoptions[0];
-    u32_t remote;
-    
-    /* Default our_name to hostname, and user to our_name */
-    if (ppp_settings.our_name[0] == 0 || ppp_settings.usehostname)
-        strcpy(ppp_settings.our_name, ppp_settings.hostname);
-    if (ppp_settings.user[0] == 0)
-        strcpy(ppp_settings.user, ppp_settings.our_name);
-    
-    /* If authentication is required, ask peer for CHAP or PAP. */
-    if (ppp_settings.auth_required && !wo->neg_chap && !wo->neg_upap) {
-        wo->neg_chap = 1;
-        wo->neg_upap = 1;
-    }
-    
-    /*
-     * Check whether we have appropriate secrets to use
-     * to authenticate the peer.
-     */
-    can_auth = wo->neg_upap && have_pap_secret();
-    if (!can_auth && wo->neg_chap) {
-        remote = ipwo->accept_remote? 0: ipwo->hisaddr;
-        can_auth = have_chap_secret(ppp_settings.remote_name, ppp_settings.our_name, remote);
-    }
-    
-    if (ppp_settings.auth_required && !can_auth) {
-        ppp_panic("No auth secret");
-    }
-}
-#endif
-
-
-/**********************************/
-/*** LOCAL FUNCTION DEFINITIONS ***/
-/**********************************/
-/*
- * Proceed to the network phase.
- */
-static void network_phase(int unit)
-{
-    int i;
-    struct protent *protp;
-    lcp_options *go = &lcp_gotoptions[unit];
-    
-    /*
-     * If the peer had to authenticate, run the auth-up script now.
-     */
-    if ((go->neg_chap || go->neg_upap) && !did_authup) {
-        /* XXX Do setup for peer authentication. */
-        did_authup = 1;
-    }
-    
-#if CBCP_SUPPORT > 0
-    /*
-     * If we negotiated callback, do it now.
-     */
-    if (go->neg_cbcp) {
-        lcp_phase[unit] = PHASE_CALLBACK;
-        (*cbcp_protent.open)(unit);
-        return;
-    }
-#endif
-    
-    lcp_phase[unit] = PHASE_NETWORK;
-    for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i)
-        if (protp->protocol < 0xC000 && protp->enabled_flag
-                && protp->open != NULL) {
-            (*protp->open)(unit);
-            if (protp->protocol != PPP_CCP)
-                ++num_np_open;
-        }
-    
-    if (num_np_open == 0)
-        /* nothing to do */
-        lcp_close(0, "No network protocols running");
-}
-
-/*
- * check_idle - check whether the link has been idle for long
- * enough that we can shut it down.
- */
-static void check_idle(void *arg)
-{
-    struct ppp_idle idle;
-    u_short itime;
-    
-	(void)arg;
-    if (!get_idle_time(0, &idle))
-        return;
-    itime = LWIP_MIN(idle.xmit_idle, idle.recv_idle);
-    if (itime >= ppp_settings.idle_time_limit) {
-        /* link is idle: shut it down. */
-        AUTHDEBUG((LOG_INFO, "Terminating connection due to lack of activity.\n"));
-        lcp_close(0, "Link inactive");
-    } else {
-        TIMEOUT(check_idle, NULL, ppp_settings.idle_time_limit - itime);
-    }
-}
-
-/*
- * connect_time_expired - log a message and close the connection.
- */
-static void connect_time_expired(void *arg)
-{
-	(void)arg;
-
-    AUTHDEBUG((LOG_INFO, "Connect time expired\n"));
-    lcp_close(0, "Connect time expired");   /* Close connection */
-}
-
-#if 0
-/*
- * login - Check the user name and password against the system
- * password database, and login the user if OK.
- *
- * returns:
- *  UPAP_AUTHNAK: Login failed.
- *  UPAP_AUTHACK: Login succeeded.
- * In either case, msg points to an appropriate message.
- */
-static int login(char *user, char *passwd, char **msg, int *msglen)
-{
-    /* XXX Fail until we decide that we want to support logins. */
-    return (UPAP_AUTHNAK);
-}
-#endif
-
-/*
- * logout - Logout the user.
- */
-static void logout(void)
-{
-    logged_in = 0;
-}
-
-
-/*
- * null_login - Check if a username of "" and a password of "" are
- * acceptable, and iff so, set the list of acceptable IP addresses
- * and return 1.
- */
-static int null_login(int unit)
-{
-	(void)unit;
-    /* XXX Fail until we decide that we want to support logins. */
-    return 0;
-}
-
-
-/*
- * get_pap_passwd - get a password for authenticating ourselves with
- * our peer using PAP.  Returns 1 on success, 0 if no suitable password
- * could be found.
- */
-static int get_pap_passwd(int unit, char *user, char *passwd)
-{
-/* normally we would reject PAP if no password is provided,
-   but this causes problems with some providers (like CHT in Taiwan)
-   who incorrectly request PAP and expect a bogus/empty password, so
-   always provide a default user/passwd of "none"/"none"
-*/
-    if(user)
-    	strcpy(user,   "none");
-    if(passwd)
-    	strcpy(passwd, "none");
-
-    return 1;
-}
-
-
-/*
- * have_pap_secret - check whether we have a PAP file with any
- * secrets that we could possibly use for authenticating the peer.
- */
-static int have_pap_secret(void)
-{
-    /* XXX Fail until we set up our passwords. */
-    return 0;
-}
-
-
-/*
- * have_chap_secret - check whether we have a CHAP file with a
- * secret that we could possibly use for authenticating `client'
- * on `server'.  Either can be the null string, meaning we don't
- * know the identity yet.
- */
-static int have_chap_secret(char *client, char *server, u32_t remote)
-{
-	(void)client;
-	(void)server;
-	(void)remote;
-    /* XXX Fail until we set up our passwords. */
-    return 0;
-}
-
-
-#if 0 /* PAP_SUPPORT > 0 || CHAP_SUPPORT > 0 */
-/*
- * set_allowed_addrs() - set the list of allowed addresses.
- */
-static void set_allowed_addrs(int unit, struct wordlist *addrs)
-{
-    if (addresses[unit] != NULL)
-        free_wordlist(addresses[unit]);
-    addresses[unit] = addrs;
-
-#if 0
-    /*
-     * If there's only one authorized address we might as well
-     * ask our peer for that one right away
-     */
-    if (addrs != NULL && addrs->next == NULL) {
-        char *p = addrs->word;
-        struct ipcp_options *wo = &ipcp_wantoptions[unit];
-        u32_t a;
-        struct hostent *hp;
-        
-        if (wo->hisaddr == 0 && *p != '!' && *p != '-'
-                && strchr(p, '/') == NULL) {
-            hp = gethostbyname(p);
-            if (hp != NULL && hp->h_addrtype == AF_INET)
-                a = *(u32_t *)hp->h_addr;
-            else
-                a = inet_addr(p);
-            if (a != (u32_t) -1)
-                wo->hisaddr = a;
-        }
-    }
-#endif
-}
-#endif
-
-static int ip_addr_check(u32_t addr, struct wordlist *addrs)
-{
-    
-    /* don't allow loopback or multicast address */
-    if (bad_ip_adrs(addr))
-        return 0;
-    
-    if (addrs == NULL)
-        return !ppp_settings.auth_required;      /* no addresses authorized */
-    
-    /* XXX All other addresses allowed. */
-    return 1;
-}
-
-#if 0 /* PAP_SUPPORT > 0 || CHAP_SUPPORT */
-/*
- * free_wordlist - release memory allocated for a wordlist.
- */
-static void free_wordlist(struct wordlist *wp)
-{
-    struct wordlist *next;
-    
-    while (wp != NULL) {
-        next = wp->next;
-        free(wp);
-        wp = next;
-    }
-}
-#endif
-
-#endif /* PPP_SUPPORT */
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/auth.h b/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/auth.h
deleted file mode 100644
index d6a5de5b7..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/auth.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*****************************************************************************
-* auth.h -  PPP Authentication and phase control header file.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* portions Copyright (c) 1998 Global Election Systems Inc.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY
-*
-* 03-01-01 Marc Boucher 
-*   Ported to lwIP.
-* 97-12-04 Guy Lancaster , Global Election Systems Inc.
-*	Original derived from BSD pppd.h.
-*****************************************************************************/
-/*
- * pppd.h - PPP daemon global declarations.
- *
- * Copyright (c) 1989 Carnegie Mellon University.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by Carnegie Mellon University.  The name of the
- * University may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- *
- */
-
-#ifndef AUTH_H
-#define AUTH_H
-
-/***********************
-*** PUBLIC FUNCTIONS ***
-***********************/
-void link_required (int);		/* we are starting to use the link */
-void link_terminated (int);	/* we are finished with the link */
-void link_down (int);			/* the LCP layer has left the Opened state */
-void link_established (int);	/* the link is up; authenticate now */
-void np_up (int, u16_t);			/* a network protocol has come up */
-void np_down (int, u16_t);		/* a network protocol has gone down */
-void np_finished (int, u16_t);	/* a network protocol no longer needs link */
-void auth_peer_fail (int, u16_t);/* peer failed to authenticate itself */
-
-/* peer successfully authenticated itself */
-void auth_peer_success (int, u16_t, char *, int);
-
-/* we failed to authenticate ourselves */
-void auth_withpeer_fail (int, u16_t);
-
-/* we successfully authenticated ourselves */
-void auth_withpeer_success (int, u16_t);
-
-/* check authentication options supplied */
-void auth_check_options (void);
-void auth_reset (int);			/* check what secrets we have */
-
-/* Check peer-supplied username/password */
-int  check_passwd (int, char *, int, char *, int, char **, int *);
-
-/* get "secret" for chap */
-int  get_secret (int, char *, char *, char *, int *, int);
-
-/* check if IP address is authorized */
-int  auth_ip_addr (int, u32_t);
-
-/* check if IP address is unreasonable */
-int  bad_ip_adrs (u32_t);
-
-
-#endif /* AUTH_H */
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/chap.c b/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/chap.c
deleted file mode 100644
index 4d1dc0d24..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/chap.c
+++ /dev/null
@@ -1,872 +0,0 @@
-/*** WARNING - THIS HAS NEVER BEEN FINISHED ***/
-/*****************************************************************************
-* chap.c - Network Challenge Handshake Authentication Protocol program file.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* portions Copyright (c) 1997 by Global Election Systems Inc.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY
-*
-* 03-01-01 Marc Boucher 
-*   Ported to lwIP.
-* 97-12-04 Guy Lancaster , Global Election Systems Inc.
-*	Original based on BSD chap.c.
-*****************************************************************************/
-/*
- * chap.c - Challenge Handshake Authentication Protocol.
- *
- * Copyright (c) 1993 The Australian National University.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by the Australian National University.  The name of the University
- * may not be used to endorse or promote products derived from this
- * software without specific prior written permission.
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- *
- * Copyright (c) 1991 Gregory M. Christy.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by Gregory M. Christy.  The name of the author may not be used to
- * endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- */
-
-#include "ppp.h"
-#if PPP_SUPPORT > 0
-#include "magic.h"
-
-#if CHAP_SUPPORT > 0
-
-#include "randm.h"
-#include "auth.h"
-#include "md5.h"
-#include "chap.h"
-#include "chpms.h"
-#include "pppdebug.h"
-
-
-/*************************/
-/*** LOCAL DEFINITIONS ***/
-/*************************/
-
-
-/************************/
-/*** LOCAL DATA TYPES ***/
-/************************/
-
-
-/***********************************/
-/*** LOCAL FUNCTION DECLARATIONS ***/
-/***********************************/
-/*
- * Protocol entry points.
- */
-static void ChapInit (int);
-static void ChapLowerUp (int);
-static void ChapLowerDown (int);
-static void ChapInput (int, u_char *, int);
-static void ChapProtocolReject (int);
-static int  ChapPrintPkt (u_char *, int,
-			      void (*) (void *, char *, ...), void *);
-
-static void ChapChallengeTimeout (void *);
-static void ChapResponseTimeout (void *);
-static void ChapReceiveChallenge (chap_state *, u_char *, int, int);
-static void ChapRechallenge (void *);
-static void ChapReceiveResponse (chap_state *, u_char *, int, int);
-static void ChapReceiveSuccess(chap_state *cstate, u_char *inp, u_char id, int len);
-static void ChapReceiveFailure(chap_state *cstate, u_char *inp, u_char id, int len);
-static void ChapSendStatus (chap_state *, int);
-static void ChapSendChallenge (chap_state *);
-static void ChapSendResponse (chap_state *);
-static void ChapGenChallenge (chap_state *);
-
-
-/******************************/
-/*** PUBLIC DATA STRUCTURES ***/
-/******************************/
-chap_state chap[NUM_PPP];		/* CHAP state; one for each unit */
-
-struct protent chap_protent = {
-    PPP_CHAP,
-    ChapInit,
-    ChapInput,
-    ChapProtocolReject,
-    ChapLowerUp,
-    ChapLowerDown,
-    NULL,
-    NULL,
-#if 0
-    ChapPrintPkt,
-    NULL,
-#endif
-    1,
-    "CHAP",
-#if 0
-    NULL,
-    NULL,
-    NULL
-#endif
-};
-
-
-
-/*****************************/
-/*** LOCAL DATA STRUCTURES ***/
-/*****************************/
-static char *ChapCodenames[] = {
-	"Challenge", "Response", "Success", "Failure"
-};
-
-
-
-/***********************************/
-/*** PUBLIC FUNCTION DEFINITIONS ***/
-/***********************************/
-/*
- * ChapAuthWithPeer - Authenticate us with our peer (start client).
- *
- */
-void ChapAuthWithPeer(int unit, char *our_name, int digest)
-{
-	chap_state *cstate = &chap[unit];
-	
-	cstate->resp_name = our_name;
-	cstate->resp_type = digest;
-	
-	if (cstate->clientstate == CHAPCS_INITIAL ||
-			cstate->clientstate == CHAPCS_PENDING) {
-		/* lower layer isn't up - wait until later */
-		cstate->clientstate = CHAPCS_PENDING;
-		return;
-	}
-	
-	/*
-	 * We get here as a result of LCP coming up.
-	 * So even if CHAP was open before, we will 
-	 * have to re-authenticate ourselves.
-	 */
-	cstate->clientstate = CHAPCS_LISTEN;
-}
-
-
-/*
- * ChapAuthPeer - Authenticate our peer (start server).
- */
-void ChapAuthPeer(int unit, char *our_name, int digest)
-{
-	chap_state *cstate = &chap[unit];
-	
-	cstate->chal_name = our_name;
-	cstate->chal_type = digest;
-	
-	if (cstate->serverstate == CHAPSS_INITIAL ||
-			cstate->serverstate == CHAPSS_PENDING) {
-		/* lower layer isn't up - wait until later */
-		cstate->serverstate = CHAPSS_PENDING;
-		return;
-	}
-	
-	ChapGenChallenge(cstate);
-	ChapSendChallenge(cstate);		/* crank it up dude! */
-	cstate->serverstate = CHAPSS_INITIAL_CHAL;
-}
-
-
-
-
-/**********************************/
-/*** LOCAL FUNCTION DEFINITIONS ***/
-/**********************************/
-/*
- * ChapInit - Initialize a CHAP unit.
- */
-static void ChapInit(int unit)
-{
-	chap_state *cstate = &chap[unit];
-	
-	BZERO(cstate, sizeof(*cstate));
-	cstate->unit = unit;
-	cstate->clientstate = CHAPCS_INITIAL;
-	cstate->serverstate = CHAPSS_INITIAL;
-	cstate->timeouttime = CHAP_DEFTIMEOUT;
-	cstate->max_transmits = CHAP_DEFTRANSMITS;
-	/* random number generator is initialized in magic_init */
-}
-
-
-/*
- * ChapChallengeTimeout - Timeout expired on sending challenge.
- */
-static void ChapChallengeTimeout(void *arg)
-{
-	chap_state *cstate = (chap_state *) arg;
-	
-	/* if we aren't sending challenges, don't worry.  then again we */
-	/* probably shouldn't be here either */
-	if (cstate->serverstate != CHAPSS_INITIAL_CHAL &&
-			cstate->serverstate != CHAPSS_RECHALLENGE)
-		return;
-	
-	if (cstate->chal_transmits >= cstate->max_transmits) {
-		/* give up on peer */
-		CHAPDEBUG((LOG_ERR, "Peer failed to respond to CHAP challenge\n"));
-		cstate->serverstate = CHAPSS_BADAUTH;
-		auth_peer_fail(cstate->unit, PPP_CHAP);
-		return;
-	}
-	
-	ChapSendChallenge(cstate);		/* Re-send challenge */
-}
-
-
-/*
- * ChapResponseTimeout - Timeout expired on sending response.
- */
-static void ChapResponseTimeout(void *arg)
-{
-	chap_state *cstate = (chap_state *) arg;
-	
-	/* if we aren't sending a response, don't worry. */
-	if (cstate->clientstate != CHAPCS_RESPONSE)
-		return;
-	
-	ChapSendResponse(cstate);		/* re-send response */
-}
-
-
-/*
- * ChapRechallenge - Time to challenge the peer again.
- */
-static void ChapRechallenge(void *arg)
-{
-	chap_state *cstate = (chap_state *) arg;
-	
-	/* if we aren't sending a response, don't worry. */
-	if (cstate->serverstate != CHAPSS_OPEN)
-		return;
-	
-	ChapGenChallenge(cstate);
-	ChapSendChallenge(cstate);
-	cstate->serverstate = CHAPSS_RECHALLENGE;
-}
-
-
-/*
- * ChapLowerUp - The lower layer is up.
- *
- * Start up if we have pending requests.
- */
-static void ChapLowerUp(int unit)
-{
-	chap_state *cstate = &chap[unit];
-	
-	if (cstate->clientstate == CHAPCS_INITIAL)
-		cstate->clientstate = CHAPCS_CLOSED;
-	else if (cstate->clientstate == CHAPCS_PENDING)
-		cstate->clientstate = CHAPCS_LISTEN;
-	
-	if (cstate->serverstate == CHAPSS_INITIAL)
-		cstate->serverstate = CHAPSS_CLOSED;
-	else if (cstate->serverstate == CHAPSS_PENDING) {
-		ChapGenChallenge(cstate);
-		ChapSendChallenge(cstate);
-		cstate->serverstate = CHAPSS_INITIAL_CHAL;
-	}
-}
-
-
-/*
- * ChapLowerDown - The lower layer is down.
- *
- * Cancel all timeouts.
- */
-static void ChapLowerDown(int unit)
-{
-	chap_state *cstate = &chap[unit];
-	
-	/* Timeout(s) pending?  Cancel if so. */
-	if (cstate->serverstate == CHAPSS_INITIAL_CHAL ||
-			cstate->serverstate == CHAPSS_RECHALLENGE)
-		UNTIMEOUT(ChapChallengeTimeout, cstate);
-	else if (cstate->serverstate == CHAPSS_OPEN
-			&& cstate->chal_interval != 0)
-		UNTIMEOUT(ChapRechallenge, cstate);
-	if (cstate->clientstate == CHAPCS_RESPONSE)
-		UNTIMEOUT(ChapResponseTimeout, cstate);
-	
-	cstate->clientstate = CHAPCS_INITIAL;
-	cstate->serverstate = CHAPSS_INITIAL;
-}
-
-
-/*
- * ChapProtocolReject - Peer doesn't grok CHAP.
- */
-static void ChapProtocolReject(int unit)
-{
-	chap_state *cstate = &chap[unit];
-	
-	if (cstate->serverstate != CHAPSS_INITIAL &&
-			cstate->serverstate != CHAPSS_CLOSED)
-		auth_peer_fail(unit, PPP_CHAP);
-	if (cstate->clientstate != CHAPCS_INITIAL &&
-			cstate->clientstate != CHAPCS_CLOSED)
-		auth_withpeer_fail(unit, PPP_CHAP);
-	ChapLowerDown(unit);		/* shutdown chap */
-}
-
-
-/*
- * ChapInput - Input CHAP packet.
- */
-static void ChapInput(int unit, u_char *inpacket, int packet_len)
-{
-	chap_state *cstate = &chap[unit];
-	u_char *inp;
-	u_char code, id;
-	int len;
-	
-	/*
-	 * Parse header (code, id and length).
-	 * If packet too short, drop it.
-	 */
-	inp = inpacket;
-	if (packet_len < CHAP_HEADERLEN) {
-		CHAPDEBUG((LOG_INFO, "ChapInput: rcvd short header.\n"));
-		return;
-	}
-	GETCHAR(code, inp);
-	GETCHAR(id, inp);
-	GETSHORT(len, inp);
-	if (len < CHAP_HEADERLEN) {
-		CHAPDEBUG((LOG_INFO, "ChapInput: rcvd illegal length.\n"));
-		return;
-	}
-	if (len > packet_len) {
-		CHAPDEBUG((LOG_INFO, "ChapInput: rcvd short packet.\n"));
-		return;
-	}
-	len -= CHAP_HEADERLEN;
-	
-	/*
-	 * Action depends on code (as in fact it usually does :-).
-	 */
-	switch (code) {
-	case CHAP_CHALLENGE:
-		ChapReceiveChallenge(cstate, inp, id, len);
-		break;
-	
-	case CHAP_RESPONSE:
-		ChapReceiveResponse(cstate, inp, id, len);
-		break;
-	
-	case CHAP_FAILURE:
-		ChapReceiveFailure(cstate, inp, id, len);
-		break;
-	
-	case CHAP_SUCCESS:
-		ChapReceiveSuccess(cstate, inp, id, len);
-		break;
-	
-	default:				/* Need code reject? */
-		CHAPDEBUG((LOG_WARNING, "Unknown CHAP code (%d) received.\n", code));
-		break;
-	}
-}
-
-
-/*
- * ChapReceiveChallenge - Receive Challenge and send Response.
- */
-static void ChapReceiveChallenge(chap_state *cstate, u_char *inp, int id, int len)
-{
-	int rchallenge_len;
-	u_char *rchallenge;
-	int secret_len;
-	char secret[MAXSECRETLEN];
-	char rhostname[256];
-	MD5_CTX mdContext;
-	u_char hash[MD5_SIGNATURE_SIZE];
-	
-	CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: Rcvd id %d.\n", id));
-	if (cstate->clientstate == CHAPCS_CLOSED ||
-		cstate->clientstate == CHAPCS_PENDING) {
-		CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: in state %d\n",
-			   cstate->clientstate));
-		return;
-	}
-	
-	if (len < 2) {
-		CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: rcvd short packet.\n"));
-		return;
-	}
-	
-	GETCHAR(rchallenge_len, inp);
-	len -= sizeof (u_char) + rchallenge_len;	/* now name field length */
-	if (len < 0) {
-		CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: rcvd short packet.\n"));
-		return;
-	}
-	rchallenge = inp;
-	INCPTR(rchallenge_len, inp);
-	
-	if (len >= sizeof(rhostname))
-		len = sizeof(rhostname) - 1;
-	BCOPY(inp, rhostname, len);
-	rhostname[len] = '\000';
-	
-	CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: received name field '%s'\n",
-	       rhostname));
-	
-	/* Microsoft doesn't send their name back in the PPP packet */
-	if (ppp_settings.remote_name[0] != 0 && (ppp_settings.explicit_remote || rhostname[0] == 0)) {
-		strncpy(rhostname, ppp_settings.remote_name, sizeof(rhostname));
-		rhostname[sizeof(rhostname) - 1] = 0;
-		CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: using '%s' as remote name\n",
-			   rhostname));
-	}
-	
-	/* get secret for authenticating ourselves with the specified host */
-	if (!get_secret(cstate->unit, cstate->resp_name, rhostname,
-			    secret, &secret_len, 0)) {
-		secret_len = 0;		/* assume null secret if can't find one */
-		CHAPDEBUG((LOG_WARNING, "No CHAP secret found for authenticating us to %s\n", rhostname));
-	}
-	
-	/* cancel response send timeout if necessary */
-	if (cstate->clientstate == CHAPCS_RESPONSE)
-		UNTIMEOUT(ChapResponseTimeout, cstate);
-	
-	cstate->resp_id = id;
-	cstate->resp_transmits = 0;
-	
-	/*  generate MD based on negotiated type */
-	switch (cstate->resp_type) { 
-	
-	case CHAP_DIGEST_MD5:
-		MD5Init(&mdContext);
-		MD5Update(&mdContext, &cstate->resp_id, 1);
-		MD5Update(&mdContext, (u_char*)secret, secret_len);
-		MD5Update(&mdContext, rchallenge, rchallenge_len);
-		MD5Final(hash, &mdContext);
-		BCOPY(hash, cstate->response, MD5_SIGNATURE_SIZE);
-		cstate->resp_length = MD5_SIGNATURE_SIZE;
-		break;
-	
-#ifdef CHAPMS
-	case CHAP_MICROSOFT:
-		ChapMS(cstate, rchallenge, rchallenge_len, secret, secret_len);
-		break;
-#endif
-	
-	default:
-		CHAPDEBUG((LOG_INFO, "unknown digest type %d\n", cstate->resp_type));
-		return;
-	}
-	
-	BZERO(secret, sizeof(secret));
-	ChapSendResponse(cstate);
-}
-
-
-/*
- * ChapReceiveResponse - Receive and process response.
- */
-static void ChapReceiveResponse(chap_state *cstate, u_char *inp, int id, int len)
-{
-	u_char *remmd, remmd_len;
-	int secret_len, old_state;
-	int code;
-	char rhostname[256];
-	MD5_CTX mdContext;
-	char secret[MAXSECRETLEN];
-	u_char hash[MD5_SIGNATURE_SIZE];
-	
-	CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: Rcvd id %d.\n", id));
-	
-	if (cstate->serverstate == CHAPSS_CLOSED ||
-			cstate->serverstate == CHAPSS_PENDING) {
-		CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: in state %d\n",
-		cstate->serverstate));
-		return;
-	}
-	
-	if (id != cstate->chal_id)
-		return;			/* doesn't match ID of last challenge */
-	
-	/*
-	* If we have received a duplicate or bogus Response,
-	* we have to send the same answer (Success/Failure)
-	* as we did for the first Response we saw.
-	*/
-	if (cstate->serverstate == CHAPSS_OPEN) {
-		ChapSendStatus(cstate, CHAP_SUCCESS);
-		return;
-	}
-	if (cstate->serverstate == CHAPSS_BADAUTH) {
-		ChapSendStatus(cstate, CHAP_FAILURE);
-		return;
-	}
-	
-	if (len < 2) {
-		CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: rcvd short packet.\n"));
-		return;
-	}
-	GETCHAR(remmd_len, inp);		/* get length of MD */
-	remmd = inp;			/* get pointer to MD */
-	INCPTR(remmd_len, inp);
-	
-	len -= sizeof (u_char) + remmd_len;
-	if (len < 0) {
-		CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: rcvd short packet.\n"));
-		return;
-	}
-	
-	UNTIMEOUT(ChapChallengeTimeout, cstate);
-	
-	if (len >= sizeof(rhostname))
-		len = sizeof(rhostname) - 1;
-	BCOPY(inp, rhostname, len);
-	rhostname[len] = '\000';
-	
-	CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: received name field: %s\n",
-				rhostname));
-	
-	/*
-	* Get secret for authenticating them with us,
-	* do the hash ourselves, and compare the result.
-	*/
-	code = CHAP_FAILURE;
-	if (!get_secret(cstate->unit, rhostname, cstate->chal_name,
-	secret, &secret_len, 1)) {
-/*        CHAPDEBUG((LOG_WARNING, TL_CHAP, "No CHAP secret found for authenticating %s\n", rhostname)); */
-		CHAPDEBUG((LOG_WARNING, "No CHAP secret found for authenticating %s\n",
-		rhostname));
-	} else {
-	
-		/*  generate MD based on negotiated type */
-		switch (cstate->chal_type) { 
-		
-		case CHAP_DIGEST_MD5:		/* only MD5 is defined for now */
-			if (remmd_len != MD5_SIGNATURE_SIZE)
-				break;			/* it's not even the right length */
-			MD5Init(&mdContext);
-			MD5Update(&mdContext, &cstate->chal_id, 1);
-			MD5Update(&mdContext, (u_char*)secret, secret_len);
-			MD5Update(&mdContext, cstate->challenge, cstate->chal_len);
-			MD5Final(hash, &mdContext); 
-			
-			/* compare local and remote MDs and send the appropriate status */
-			if (memcmp (hash, remmd, MD5_SIGNATURE_SIZE) == 0)
-				code = CHAP_SUCCESS;	/* they are the same! */
-			break;
-		
-		default:
-			CHAPDEBUG((LOG_INFO, "unknown digest type %d\n", cstate->chal_type));
-		}
-	}
-	
-	BZERO(secret, sizeof(secret));
-	ChapSendStatus(cstate, code);
-	
-	if (code == CHAP_SUCCESS) {
-		old_state = cstate->serverstate;
-		cstate->serverstate = CHAPSS_OPEN;
-		if (old_state == CHAPSS_INITIAL_CHAL) {
-			auth_peer_success(cstate->unit, PPP_CHAP, rhostname, len);
-		}
-		if (cstate->chal_interval != 0)
-			TIMEOUT(ChapRechallenge, cstate, cstate->chal_interval);
-	} else {
-		CHAPDEBUG((LOG_ERR, "CHAP peer authentication failed\n"));
-		cstate->serverstate = CHAPSS_BADAUTH;
-		auth_peer_fail(cstate->unit, PPP_CHAP);
-	}
-}
-
-/*
- * ChapReceiveSuccess - Receive Success
- */
-static void ChapReceiveSuccess(chap_state *cstate, u_char *inp, u_char id, int len)
-{
-
-	CHAPDEBUG((LOG_INFO, "ChapReceiveSuccess: Rcvd id %d.\n", id));
-	
-	if (cstate->clientstate == CHAPCS_OPEN)
-		/* presumably an answer to a duplicate response */
-		return;
-	
-	if (cstate->clientstate != CHAPCS_RESPONSE) {
-		/* don't know what this is */
-		CHAPDEBUG((LOG_INFO, "ChapReceiveSuccess: in state %d\n",
-			   cstate->clientstate));
-		return;
-	}
-	
-	UNTIMEOUT(ChapResponseTimeout, cstate);
-	
-	/*
-	 * Print message.
-	 */
-	if (len > 0)
-		PRINTMSG(inp, len);
-	
-	cstate->clientstate = CHAPCS_OPEN;
-	
-	auth_withpeer_success(cstate->unit, PPP_CHAP);
-}
-
-
-/*
- * ChapReceiveFailure - Receive failure.
- */
-static void ChapReceiveFailure(chap_state *cstate, u_char *inp, u_char id, int len)
-{
-	CHAPDEBUG((LOG_INFO, "ChapReceiveFailure: Rcvd id %d.\n", id));
-	
-	if (cstate->clientstate != CHAPCS_RESPONSE) {
-		/* don't know what this is */
-		CHAPDEBUG((LOG_INFO, "ChapReceiveFailure: in state %d\n",
-			   cstate->clientstate));
-		return;
-	}
-	
-	UNTIMEOUT(ChapResponseTimeout, cstate);
-	
-	/*
-	 * Print message.
-	 */
-	if (len > 0)
-		PRINTMSG(inp, len);
-	
-	CHAPDEBUG((LOG_ERR, "CHAP authentication failed\n"));
-	auth_withpeer_fail(cstate->unit, PPP_CHAP);
-}
-
-
-/*
- * ChapSendChallenge - Send an Authenticate challenge.
- */
-static void ChapSendChallenge(chap_state *cstate)
-{
-	u_char *outp;
-	int chal_len, name_len;
-	int outlen;
-	
-	chal_len = cstate->chal_len;
-	name_len = strlen(cstate->chal_name);
-	outlen = CHAP_HEADERLEN + sizeof (u_char) + chal_len + name_len;
-	outp = outpacket_buf[cstate->unit];
-	
-	MAKEHEADER(outp, PPP_CHAP);		/* paste in a CHAP header */
-	
-	PUTCHAR(CHAP_CHALLENGE, outp);
-	PUTCHAR(cstate->chal_id, outp);
-	PUTSHORT(outlen, outp);
-	
-	PUTCHAR(chal_len, outp);		/* put length of challenge */
-	BCOPY(cstate->challenge, outp, chal_len);
-	INCPTR(chal_len, outp);
-	
-	BCOPY(cstate->chal_name, outp, name_len);	/* append hostname */
-	
-	pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN);
-	
-	CHAPDEBUG((LOG_INFO, "ChapSendChallenge: Sent id %d.\n", cstate->chal_id));
-	
-	TIMEOUT(ChapChallengeTimeout, cstate, cstate->timeouttime);
-	++cstate->chal_transmits;
-}
-
-
-/*
- * ChapSendStatus - Send a status response (ack or nak).
- */
-static void ChapSendStatus(chap_state *cstate, int code)
-{
-	u_char *outp;
-	int outlen, msglen;
-	char msg[256];
-	
-	if (code == CHAP_SUCCESS)
-		strcpy(msg, "Welcome!");
-	else
-		strcpy(msg, "I don't like you.  Go 'way.");
-	msglen = strlen(msg);
-	
-	outlen = CHAP_HEADERLEN + msglen;
-	outp = outpacket_buf[cstate->unit];
-	
-	MAKEHEADER(outp, PPP_CHAP);		/* paste in a header */
-	
-	PUTCHAR(code, outp);
-	PUTCHAR(cstate->chal_id, outp);
-	PUTSHORT(outlen, outp);
-	BCOPY(msg, outp, msglen);
-	pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN);
-	
-	CHAPDEBUG((LOG_INFO, "ChapSendStatus: Sent code %d, id %d.\n", code,
-	       cstate->chal_id));
-}
-
-/*
- * ChapGenChallenge is used to generate a pseudo-random challenge string of
- * a pseudo-random length between min_len and max_len.  The challenge
- * string and its length are stored in *cstate, and various other fields of
- * *cstate are initialized.
- */
-
-static void ChapGenChallenge(chap_state *cstate)
-{
-	int chal_len;
-	u_char *ptr = cstate->challenge;
-	int i;
-	
-	/* pick a random challenge length between MIN_CHALLENGE_LENGTH and 
-	   MAX_CHALLENGE_LENGTH */  
-	chal_len = (unsigned)
-				((((magic() >> 16) *
-			        (MAX_CHALLENGE_LENGTH - MIN_CHALLENGE_LENGTH)) >> 16)
-			     + MIN_CHALLENGE_LENGTH);
-	cstate->chal_len = chal_len;
-	cstate->chal_id = ++cstate->id;
-	cstate->chal_transmits = 0;
-	
-	/* generate a random string */
-	for (i = 0; i < chal_len; i++ )
-		*ptr++ = (char) (magic() & 0xff);
-}
-
-/*
- * ChapSendResponse - send a response packet with values as specified
- * in *cstate.
- */
-/* ARGSUSED */
-static void ChapSendResponse(chap_state *cstate)
-{
-	u_char *outp;
-	int outlen, md_len, name_len;
-	
-	md_len = cstate->resp_length;
-	name_len = strlen(cstate->resp_name);
-	outlen = CHAP_HEADERLEN + sizeof (u_char) + md_len + name_len;
-	outp = outpacket_buf[cstate->unit];
-	
-	MAKEHEADER(outp, PPP_CHAP);
-	
-	PUTCHAR(CHAP_RESPONSE, outp);	/* we are a response */
-	PUTCHAR(cstate->resp_id, outp);	/* copy id from challenge packet */
-	PUTSHORT(outlen, outp);			/* packet length */
-	
-	PUTCHAR(md_len, outp);			/* length of MD */
-	BCOPY(cstate->response, outp, md_len);		/* copy MD to buffer */
-	INCPTR(md_len, outp);
-	
-	BCOPY(cstate->resp_name, outp, name_len);	/* append our name */
-	
-	/* send the packet */
-	pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN);
-	
-	cstate->clientstate = CHAPCS_RESPONSE;
-	TIMEOUT(ChapResponseTimeout, cstate, cstate->timeouttime);
-	++cstate->resp_transmits;
-}
-
-/*
- * ChapPrintPkt - print the contents of a CHAP packet.
- */
-static int ChapPrintPkt(
-	u_char *p,
-	int plen,
-	void (*printer) (void *, char *, ...),
-	void *arg
-)
-{
-	int code, id, len;
-	int clen, nlen;
-	u_char x;
-	
-	if (plen < CHAP_HEADERLEN)
-		return 0;
-	GETCHAR(code, p);
-	GETCHAR(id, p);
-	GETSHORT(len, p);
-	if (len < CHAP_HEADERLEN || len > plen)
-		return 0;
-	
-	if (code >= 1 && code <= sizeof(ChapCodenames) / sizeof(char *))
-		printer(arg, " %s", ChapCodenames[code-1]);
-	else
-		printer(arg, " code=0x%x", code);
-	printer(arg, " id=0x%x", id);
-	len -= CHAP_HEADERLEN;
-	switch (code) {
-	case CHAP_CHALLENGE:
-	case CHAP_RESPONSE:
-		if (len < 1)
-			break;
-		clen = p[0];
-		if (len < clen + 1)
-			break;
-		++p;
-		nlen = len - clen - 1;
-		printer(arg, " <");
-		for (; clen > 0; --clen) {
-			GETCHAR(x, p);
-			printer(arg, "%.2x", x);
-		}
-		printer(arg, ">, name = %.*Z", nlen, p);
-		break;
-	case CHAP_FAILURE:
-	case CHAP_SUCCESS:
-		printer(arg, " %.*Z", len, p);
-		break;
-	default:
-		for (clen = len; clen > 0; --clen) {
-			GETCHAR(x, p);
-			printer(arg, " %.2x", x);
-		}
-	}
-	
-	return len + CHAP_HEADERLEN;
-}
-
-#endif
-
-#endif /* PPP_SUPPORT */
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/chap.h b/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/chap.h
deleted file mode 100644
index 5281fc01d..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/chap.h
+++ /dev/null
@@ -1,167 +0,0 @@
-/*****************************************************************************
-* chap.h - Network Challenge Handshake Authentication Protocol header file.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* portions Copyright (c) 1998 Global Election Systems Inc.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY
-*
-* 03-01-01 Marc Boucher 
-*   Ported to lwIP.
-* 97-12-03 Guy Lancaster , Global Election Systems Inc.
-*	Original built from BSD network code.
-******************************************************************************/
-/*
- * chap.h - Challenge Handshake Authentication Protocol definitions.
- *
- * Copyright (c) 1993 The Australian National University.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by the Australian National University.  The name of the University
- * may not be used to endorse or promote products derived from this
- * software without specific prior written permission.
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- *
- * Copyright (c) 1991 Gregory M. Christy
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by the author.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- *
- * $Id: chap.h,v 1.2 2006/08/29 18:53:47 wolti Exp $
- */
-
-#ifndef CHAP_H
-#define CHAP_H
-
-/*************************
-*** PUBLIC DEFINITIONS ***
-*************************/
-
-/* Code + ID + length */
-#define CHAP_HEADERLEN		4
-
-/*
- * CHAP codes.
- */
-
-#define CHAP_DIGEST_MD5		5	/* use MD5 algorithm */
-#define MD5_SIGNATURE_SIZE	16	/* 16 bytes in a MD5 message digest */
-#define CHAP_MICROSOFT		0x80	/* use Microsoft-compatible alg. */
-#define MS_CHAP_RESPONSE_LEN	49	/* Response length for MS-CHAP */
-
-#define CHAP_CHALLENGE		1
-#define CHAP_RESPONSE		2
-#define CHAP_SUCCESS		3
-#define CHAP_FAILURE    	4
-
-/*
- *  Challenge lengths (for challenges we send) and other limits.
- */
-#define MIN_CHALLENGE_LENGTH	32
-#define MAX_CHALLENGE_LENGTH	64
-#define MAX_RESPONSE_LENGTH	64	/* sufficient for MD5 or MS-CHAP */
-
-/*
- * Client (peer) states.
- */
-#define CHAPCS_INITIAL		0	/* Lower layer down, not opened */
-#define CHAPCS_CLOSED		1	/* Lower layer up, not opened */
-#define CHAPCS_PENDING		2	/* Auth us to peer when lower up */
-#define CHAPCS_LISTEN		3	/* Listening for a challenge */
-#define CHAPCS_RESPONSE		4	/* Sent response, waiting for status */
-#define CHAPCS_OPEN		5	/* We've received Success */
-
-/*
- * Server (authenticator) states.
- */
-#define CHAPSS_INITIAL		0	/* Lower layer down, not opened */
-#define CHAPSS_CLOSED		1	/* Lower layer up, not opened */
-#define CHAPSS_PENDING		2	/* Auth peer when lower up */
-#define CHAPSS_INITIAL_CHAL	3	/* We've sent the first challenge */
-#define CHAPSS_OPEN		4	/* We've sent a Success msg */
-#define CHAPSS_RECHALLENGE	5	/* We've sent another challenge */
-#define CHAPSS_BADAUTH		6	/* We've sent a Failure msg */
-
-/************************
-*** PUBLIC DATA TYPES ***
-************************/
-
-/*
- * Each interface is described by a chap structure.
- */
-
-typedef struct chap_state {
-    int unit;			/* Interface unit number */
-    int clientstate;		/* Client state */
-    int serverstate;		/* Server state */
-    u_char challenge[MAX_CHALLENGE_LENGTH]; /* last challenge string sent */
-    u_char chal_len;		/* challenge length */
-    u_char chal_id;		/* ID of last challenge */
-    u_char chal_type;		/* hash algorithm for challenges */
-    u_char id;			/* Current id */
-    char *chal_name;		/* Our name to use with challenge */
-    int chal_interval;		/* Time until we challenge peer again */
-    int timeouttime;		/* Timeout time in seconds */
-    int max_transmits;		/* Maximum # of challenge transmissions */
-    int chal_transmits;		/* Number of transmissions of challenge */
-    int resp_transmits;		/* Number of transmissions of response */
-    u_char response[MAX_RESPONSE_LENGTH];	/* Response to send */
-    u_char resp_length;		/* length of response */
-    u_char resp_id;		/* ID for response messages */
-    u_char resp_type;		/* hash algorithm for responses */
-    char *resp_name;		/* Our name to send with response */
-} chap_state;
-
-
-/******************
-*** PUBLIC DATA ***
-******************/
-extern chap_state chap[];
-
-extern struct protent chap_protent;
-
-
-/***********************
-*** PUBLIC FUNCTIONS ***
-***********************/
-
-void ChapAuthWithPeer (int, char *, int);
-void ChapAuthPeer (int, char *, int);
-
-#endif /* CHAP_H */
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/chpms.c b/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/chpms.c
deleted file mode 100644
index 01755ba39..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/chpms.c
+++ /dev/null
@@ -1,398 +0,0 @@
-/*** WARNING - THIS CODE HAS NOT BEEN FINISHED! ***/
-/*****************************************************************************
-* chpms.c - Network MicroSoft Challenge Handshake Authentication Protocol program file.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* Copyright (c) 1997 by Global Election Systems Inc.  All rights reserved.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY
-*
-* 03-01-01 Marc Boucher 
-*   Ported to lwIP.
-* 97-12-08 Guy Lancaster , Global Election Systems Inc.
-*	Original based on BSD chap_ms.c.
-*****************************************************************************/
-/*
- * chap_ms.c - Microsoft MS-CHAP compatible implementation.
- *
- * Copyright (c) 1995 Eric Rosenquist, Strata Software Limited.
- * http://www.strataware.com/
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by Eric Rosenquist.  The name of the author may not be used to
- * endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- */
-
-/*
- * Modifications by Lauri Pesonen / lpesonen@clinet.fi, april 1997
- *
- *   Implemented LANManager type password response to MS-CHAP challenges.
- *   Now pppd provides both NT style and LANMan style blocks, and the
- *   prefered is set by option "ms-lanman". Default is to use NT.
- *   The hash text (StdText) was taken from Win95 RASAPI32.DLL.
- *
- *   You should also use DOMAIN\\USERNAME as described in README.MSCHAP80
- */
-
-#define USE_CRYPT
-
-
-#include "ppp.h"
-
-#if MSCHAP_SUPPORT > 0
-
-#include "md4.h"
-#ifndef USE_CRYPT
-#include "des.h"
-#endif
-#include "chap.h"
-#include "chpms.h"
-#include "pppdebug.h"
-
-
-/*************************/
-/*** LOCAL DEFINITIONS ***/
-/*************************/
-
-
-/************************/
-/*** LOCAL DATA TYPES ***/
-/************************/
-typedef struct {
-    u_char LANManResp[24];
-    u_char NTResp[24];
-    u_char UseNT;		/* If 1, ignore the LANMan response field */
-} MS_ChapResponse;
-/* We use MS_CHAP_RESPONSE_LEN, rather than sizeof(MS_ChapResponse),
-   in case this struct gets padded. */
-
-
-
-/***********************************/
-/*** LOCAL FUNCTION DECLARATIONS ***/
-/***********************************/
-
-/* XXX Don't know what to do with these. */
-extern void setkey(const char *);
-extern void encrypt(char *, int);
-
-static void	DesEncrypt (u_char *, u_char *, u_char *);
-static void	MakeKey (u_char *, u_char *);
-
-#ifdef USE_CRYPT
-static void	Expand (u_char *, u_char *);
-static void	Collapse (u_char *, u_char *);
-#endif
-
-static void ChallengeResponse(
-	u_char *challenge,	/* IN   8 octets */
-	u_char *pwHash,		/* IN  16 octets */
-	u_char *response	/* OUT 24 octets */
-);
-static void ChapMS_NT(
-	char *rchallenge,
-	int rchallenge_len,
-	char *secret,
-	int secret_len,
-	MS_ChapResponse *response
-);
-static u_char Get7Bits(
-	u_char *input,
-	int startBit
-);
-
-
-/***********************************/
-/*** PUBLIC FUNCTION DEFINITIONS ***/
-/***********************************/
-void ChapMS(
-	chap_state *cstate,
-	char *rchallenge,
-	int rchallenge_len,
-	char *secret,
-	int secret_len
-)
-{
-	MS_ChapResponse	response;
-#ifdef MSLANMAN
-	extern int ms_lanman;
-#endif
-	
-#if 0
-	CHAPDEBUG((LOG_INFO, "ChapMS: secret is '%.*s'\n", secret_len, secret));
-#endif
-	BZERO(&response, sizeof(response));
-	
-	/* Calculate both always */
-	ChapMS_NT(rchallenge, rchallenge_len, secret, secret_len, &response);
-	
-#ifdef MSLANMAN
-	ChapMS_LANMan(rchallenge, rchallenge_len, secret, secret_len, &response);
-	
-	/* prefered method is set by option  */
-	response.UseNT = !ms_lanman;
-#else
-	response.UseNT = 1;
-#endif
-	
-	BCOPY(&response, cstate->response, MS_CHAP_RESPONSE_LEN);
-	cstate->resp_length = MS_CHAP_RESPONSE_LEN;
-}
-
-
-/**********************************/
-/*** LOCAL FUNCTION DEFINITIONS ***/
-/**********************************/
-static void ChallengeResponse(
-	u_char *challenge,	/* IN   8 octets */
-	u_char *pwHash,		/* IN  16 octets */
-	u_char *response	/* OUT 24 octets */
-)
-{
-	char    ZPasswordHash[21];
-	
-	BZERO(ZPasswordHash, sizeof(ZPasswordHash));
-	BCOPY(pwHash, ZPasswordHash, 16);
-	
-#if 0
-	log_packet(ZPasswordHash, sizeof(ZPasswordHash), "ChallengeResponse - ZPasswordHash", LOG_DEBUG);
-#endif
-	
-	DesEncrypt(challenge, ZPasswordHash +  0, response + 0);
-	DesEncrypt(challenge, ZPasswordHash +  7, response + 8);
-	DesEncrypt(challenge, ZPasswordHash + 14, response + 16);
-	
-#if 0
-	log_packet(response, 24, "ChallengeResponse - response", LOG_DEBUG);
-#endif
-}
-
-
-#ifdef USE_CRYPT
-static void DesEncrypt(
-	u_char *clear,	/* IN  8 octets */
-	u_char *key,	/* IN  7 octets */
-	u_char *cipher	/* OUT 8 octets */
-)
-{
-	u_char des_key[8];
-	u_char crypt_key[66];
-	u_char des_input[66];
-	
-	MakeKey(key, des_key);
-	
-	Expand(des_key, crypt_key);
-	setkey(crypt_key);
-	
-#if 0
-	CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet input : %02X%02X%02X%02X%02X%02X%02X%02X\n",
-	       clear[0], clear[1], clear[2], clear[3], clear[4], clear[5], clear[6], clear[7]));
-#endif
-	
-	Expand(clear, des_input);
-	encrypt(des_input, 0);
-	Collapse(des_input, cipher);
-	
-#if 0
-	CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet output: %02X%02X%02X%02X%02X%02X%02X%02X\n",
-	       cipher[0], cipher[1], cipher[2], cipher[3], cipher[4], cipher[5], cipher[6], cipher[7]));
-#endif
-}
-
-#else /* USE_CRYPT */
-
-static void DesEncrypt(
-	u_char *clear,	/* IN  8 octets */
-	u_char *key,	/* IN  7 octets */
-	u_char *cipher	/* OUT 8 octets */
-)
-{
-	des_cblock		des_key;
-	des_key_schedule	key_schedule;
-	
-	MakeKey(key, des_key);
-	
-	des_set_key(&des_key, key_schedule);
-	
-#if 0
-	CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet input : %02X%02X%02X%02X%02X%02X%02X%02X\n",
-	       clear[0], clear[1], clear[2], clear[3], clear[4], clear[5], clear[6], clear[7]));
-#endif
-	
-	des_ecb_encrypt((des_cblock *)clear, (des_cblock *)cipher, key_schedule, 1);
-	
-#if 0
-	CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet output: %02X%02X%02X%02X%02X%02X%02X%02X\n",
-	       cipher[0], cipher[1], cipher[2], cipher[3], cipher[4], cipher[5], cipher[6], cipher[7]));
-#endif
-}
-
-#endif /* USE_CRYPT */
-
-
-static u_char Get7Bits(
-	u_char *input,
-	int startBit
-)
-{
-	register unsigned int	word;
-	
-	word  = (unsigned)input[startBit / 8] << 8;
-	word |= (unsigned)input[startBit / 8 + 1];
-	
-	word >>= 15 - (startBit % 8 + 7);
-	
-	return word & 0xFE;
-}
-
-#ifdef USE_CRYPT
-
-/* in == 8-byte string (expanded version of the 56-bit key)
- * out == 64-byte string where each byte is either 1 or 0
- * Note that the low-order "bit" is always ignored by by setkey()
- */
-static void Expand(u_char *in, u_char *out)
-{
-	int j, c;
-	int i;
-	
-	for(i = 0; i < 64; in++){
-		c = *in;
-		for(j = 7; j >= 0; j--)
-			*out++ = (c >> j) & 01;
-		i += 8;
-	}
-}
-
-/* The inverse of Expand
- */
-static void Collapse(u_char *in, u_char *out)
-{
-	int j;
-	int i;
-	unsigned int c;
-	
-	for (i = 0; i < 64; i += 8, out++) {
-		c = 0;
-		for (j = 7; j >= 0; j--, in++)
-			c |= *in << j;
-		*out = c & 0xff;
-	}
-}
-#endif
-
-static void MakeKey(
-	u_char *key,		/* IN  56 bit DES key missing parity bits */
-	u_char *des_key		/* OUT 64 bit DES key with parity bits added */
-)
-{
-	des_key[0] = Get7Bits(key,  0);
-	des_key[1] = Get7Bits(key,  7);
-	des_key[2] = Get7Bits(key, 14);
-	des_key[3] = Get7Bits(key, 21);
-	des_key[4] = Get7Bits(key, 28);
-	des_key[5] = Get7Bits(key, 35);
-	des_key[6] = Get7Bits(key, 42);
-	des_key[7] = Get7Bits(key, 49);
-	
-#ifndef USE_CRYPT
-	des_set_odd_parity((des_cblock *)des_key);
-#endif
-	
-#if 0
-	CHAPDEBUG((LOG_INFO, "MakeKey: 56-bit input : %02X%02X%02X%02X%02X%02X%02X\n",
-	       key[0], key[1], key[2], key[3], key[4], key[5], key[6]));
-	CHAPDEBUG((LOG_INFO, "MakeKey: 64-bit output: %02X%02X%02X%02X%02X%02X%02X%02X\n",
-	       des_key[0], des_key[1], des_key[2], des_key[3], des_key[4], des_key[5], des_key[6], des_key[7]));
-#endif
-}
-
-static void ChapMS_NT(
-	char *rchallenge,
-	int rchallenge_len,
-	char *secret,
-	int secret_len,
-	MS_ChapResponse *response
-)
-{
-	int			i;
-	MDstruct	md4Context;
-	u_char		unicodePassword[MAX_NT_PASSWORD * 2];
-	static int	low_byte_first = -1;
-	
-	/* Initialize the Unicode version of the secret (== password). */
-	/* This implicitly supports 8-bit ISO8859/1 characters. */
-	BZERO(unicodePassword, sizeof(unicodePassword));
-	for (i = 0; i < secret_len; i++)
-		unicodePassword[i * 2] = (u_char)secret[i];
-	
-	MDbegin(&md4Context);
-	MDupdate(&md4Context, unicodePassword, secret_len * 2 * 8);	/* Unicode is 2 bytes/char, *8 for bit count */
-	
-	if (low_byte_first == -1)
-		low_byte_first = (htons((unsigned short int)1) != 1);
-	if (low_byte_first == 0)
-		MDreverse((u_long *)&md4Context);  /*  sfb 961105 */
-	
-	MDupdate(&md4Context, NULL, 0);	/* Tell MD4 we're done */
-	
-	ChallengeResponse(rchallenge, (char *)md4Context.buffer, response->NTResp);
-}
-
-#ifdef MSLANMAN
-static u_char *StdText = (u_char *)"KGS!@#$%"; /* key from rasapi32.dll */
-
-static ChapMS_LANMan(
-	char *rchallenge,
-	int rchallenge_len,
-	char *secret,
-	int secret_len,
-	MS_ChapResponse	*response
-)
-{
-	int			i;
-	u_char		UcasePassword[MAX_NT_PASSWORD]; /* max is actually 14 */
-	u_char		PasswordHash[16];
-	
-	/* LANMan password is case insensitive */
-	BZERO(UcasePassword, sizeof(UcasePassword));
-	for (i = 0; i < secret_len; i++)
-		UcasePassword[i] = (u_char)toupper(secret[i]);
-	DesEncrypt( StdText, UcasePassword + 0, PasswordHash + 0 );
-	DesEncrypt( StdText, UcasePassword + 7, PasswordHash + 8 );
-	ChallengeResponse(rchallenge, PasswordHash, response->LANManResp);
-}
-#endif
-
-#endif /* MSCHAP_SUPPORT */
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/chpms.h b/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/chpms.h
deleted file mode 100644
index 9973ba015..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/chpms.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*****************************************************************************
-* chpms.h - Network Microsoft Challenge Handshake Protocol header file.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* portions Copyright (c) 1998 Global Election Systems Inc.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY
-*
-* 03-01-01 Marc Boucher 
-*   Ported to lwIP.
-* 98-01-30 Guy Lancaster , Global Election Systems Inc.
-*	Original built from BSD network code.
-******************************************************************************/
-/*
- * chap.h - Challenge Handshake Authentication Protocol definitions.
- *
- * Copyright (c) 1995 Eric Rosenquist, Strata Software Limited.
- * http://www.strataware.com/
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by Eric Rosenquist.  The name of the author may not be used to
- * endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- *
- * $Id: chpms.h,v 1.2 2006/08/29 18:53:47 wolti Exp $
- */
-
-#ifndef CHPMS_H
-#define CHPMS_H
-
-#define MAX_NT_PASSWORD	256	/* Maximum number of (Unicode) chars in an NT password */
-
-void ChapMS (chap_state *, char *, int, char *, int);
-
-#endif /* CHPMS_H */
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/fsm.c b/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/fsm.c
deleted file mode 100644
index fe8b38a93..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/fsm.c
+++ /dev/null
@@ -1,838 +0,0 @@
-/*****************************************************************************
-* fsm.c - Network Control Protocol Finite State Machine program file.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* portions Copyright (c) 1997 by Global Election Systems Inc.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY
-*
-* 03-01-01 Marc Boucher 
-*   Ported to lwIP.
-* 97-12-01 Guy Lancaster , Global Election Systems Inc.
-*	Original based on BSD fsm.c.
-*****************************************************************************/
-/*
- * fsm.c - {Link, IP} Control Protocol Finite State Machine.
- *
- * Copyright (c) 1989 Carnegie Mellon University.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by Carnegie Mellon University.  The name of the
- * University may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- */
-
-
-/*
- * TODO:
- * Randomize fsm id on link/init.
- * Deal with variable outgoing MTU.
- */
-
-#include "ppp.h"
-#if PPP_SUPPORT > 0
-#include "fsm.h"
-#include "pppdebug.h"
-
-
-/*************************/
-/*** LOCAL DEFINITIONS ***/
-/*************************/
-
-
-/************************/
-/*** LOCAL DATA TYPES ***/
-/************************/
-
-
-/***********************************/
-/*** LOCAL FUNCTION DECLARATIONS ***/
-/***********************************/
-static void fsm_timeout (void *);
-static void fsm_rconfreq (fsm *, u_char, u_char *, int);
-static void fsm_rconfack (fsm *, int, u_char *, int);
-static void fsm_rconfnakrej (fsm *, int, int, u_char *, int);
-static void fsm_rtermreq (fsm *, int, u_char *, int);
-static void fsm_rtermack (fsm *);
-static void fsm_rcoderej (fsm *, u_char *, int);
-static void fsm_sconfreq (fsm *, int);
-
-#define PROTO_NAME(f)	((f)->callbacks->proto_name)
-
-
-/******************************/
-/*** PUBLIC DATA STRUCTURES ***/
-/******************************/
-
-
-/*****************************/
-/*** LOCAL DATA STRUCTURES ***/
-/*****************************/
-int peer_mru[NUM_PPP];
-
-
-/***********************************/
-/*** PUBLIC FUNCTION DEFINITIONS ***/
-/***********************************/
-
-/*
- * fsm_init - Initialize fsm.
- *
- * Initialize fsm state.
- */
-void fsm_init(fsm *f)
-{
-	f->state = INITIAL;
-	f->flags = 0;
-	f->id = 0;				/* XXX Start with random id? */
-	f->timeouttime = FSM_DEFTIMEOUT;
-	f->maxconfreqtransmits = FSM_DEFMAXCONFREQS;
-	f->maxtermtransmits = FSM_DEFMAXTERMREQS;
-	f->maxnakloops = FSM_DEFMAXNAKLOOPS;
-	f->term_reason_len = 0;
-}
-
-
-/*
- * fsm_lowerup - The lower layer is up.
- */
-void fsm_lowerup(fsm *f)
-{
-	int oldState = f->state;
-
-	switch( f->state ){
-	case INITIAL:
-		f->state = CLOSED;
-		break;
-	
-	case STARTING:
-		if( f->flags & OPT_SILENT )
-			f->state = STOPPED;
-		else {
-			/* Send an initial configure-request */
-			fsm_sconfreq(f, 0);
-			f->state = REQSENT;
-		}
-	break;
-	
-	default:
-		FSMDEBUG((LOG_INFO, "%s: Up event in state %d!\n",
-				PROTO_NAME(f), f->state));
-	}
-	
-	FSMDEBUG((LOG_INFO, "%s: lowerup state %d -> %d\n",
-			PROTO_NAME(f), oldState, f->state));
-}
-
-
-/*
- * fsm_lowerdown - The lower layer is down.
- *
- * Cancel all timeouts and inform upper layers.
- */
-void fsm_lowerdown(fsm *f)
-{
-	int oldState = f->state;
-	
-	switch( f->state ){
-	case CLOSED:
-		f->state = INITIAL;
-		break;
-	
-	case STOPPED:
-		f->state = STARTING;
-		if( f->callbacks->starting )
-			(*f->callbacks->starting)(f);
-		break;
-	
-	case CLOSING:
-		f->state = INITIAL;
-		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
-		break;
-	
-	case STOPPING:
-	case REQSENT:
-	case ACKRCVD:
-	case ACKSENT:
-		f->state = STARTING;
-		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
-		break;
-	
-	case OPENED:
-		if( f->callbacks->down )
-			(*f->callbacks->down)(f);
-		f->state = STARTING;
-		break;
-	
-	default:
-		FSMDEBUG((LOG_INFO, "%s: Down event in state %d!\n",
-				PROTO_NAME(f), f->state));
-	}
-	
-	FSMDEBUG((LOG_INFO, "%s: lowerdown state %d -> %d\n",
-			PROTO_NAME(f), oldState, f->state));
-}
-
-
-/*
- * fsm_open - Link is allowed to come up.
- */
-void fsm_open(fsm *f)
-{
-	int oldState = f->state;
-	
-	switch( f->state ){
-		case INITIAL:
-			f->state = STARTING;
-			if( f->callbacks->starting )
-				(*f->callbacks->starting)(f);
-			break;
-		
-		case CLOSED:
-		if( f->flags & OPT_SILENT )
-			f->state = STOPPED;
-		else {
-			/* Send an initial configure-request */
-			fsm_sconfreq(f, 0);
-			f->state = REQSENT;
-		}
-		break;
-	
-	case CLOSING:
-		f->state = STOPPING;
-		/* fall through */
-	case STOPPED:
-	case OPENED:
-		if( f->flags & OPT_RESTART ){
-			fsm_lowerdown(f);
-			fsm_lowerup(f);
-		}
-		break;
-	}
-	
-	FSMDEBUG((LOG_INFO, "%s: open state %d -> %d\n",
-			PROTO_NAME(f), oldState, f->state));
-}
-
-
-/*
- * fsm_close - Start closing connection.
- *
- * Cancel timeouts and either initiate close or possibly go directly to
- * the CLOSED state.
- */
-void fsm_close(fsm *f, char *reason)
-{
-	int oldState = f->state;
-	
-	f->term_reason = reason;
-	f->term_reason_len = (reason == NULL? 0: strlen(reason));
-	switch( f->state ){
-	case STARTING:
-		f->state = INITIAL;
-		break;
-	case STOPPED:
-		f->state = CLOSED;
-		break;
-	case STOPPING:
-		f->state = CLOSING;
-		break;
-	
-	case REQSENT:
-	case ACKRCVD:
-	case ACKSENT:
-	case OPENED:
-		if( f->state != OPENED )
-			UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
-		else if( f->callbacks->down )
-			(*f->callbacks->down)(f);	/* Inform upper layers we're down */
-		
-		/* Init restart counter, send Terminate-Request */
-		f->retransmits = f->maxtermtransmits;
-		fsm_sdata(f, TERMREQ, f->reqid = ++f->id,
-					(u_char *) f->term_reason, f->term_reason_len);
-		TIMEOUT(fsm_timeout, f, f->timeouttime);
-		--f->retransmits;
-		
-		f->state = CLOSING;
-		break;
-	}
-	
-	FSMDEBUG((LOG_INFO, "%s: close reason=%s state %d -> %d\n",
-			PROTO_NAME(f), reason, oldState, f->state));
-}
-
-
-/*
- * fsm_sdata - Send some data.
- *
- * Used for all packets sent to our peer by this module.
- */
-void fsm_sdata(
-	fsm *f,
-	u_char code, 
-	u_char id,
-	u_char *data,
-	int datalen
-)
-{
-	u_char *outp;
-	int outlen;
-	
-	/* Adjust length to be smaller than MTU */
-	outp = outpacket_buf[f->unit];
-	if (datalen > peer_mru[f->unit] - (int)HEADERLEN)
-		datalen = peer_mru[f->unit] - HEADERLEN;
-	if (datalen && data != outp + PPP_HDRLEN + HEADERLEN)
-		BCOPY(data, outp + PPP_HDRLEN + HEADERLEN, datalen);
-	outlen = datalen + HEADERLEN;
-	MAKEHEADER(outp, f->protocol);
-	PUTCHAR(code, outp);
-	PUTCHAR(id, outp);
-	PUTSHORT(outlen, outp);
-	pppWrite(f->unit, outpacket_buf[f->unit], outlen + PPP_HDRLEN);
-	FSMDEBUG((LOG_INFO, "fsm_sdata(%s): Sent code %d,%d,%d.\n",
-				PROTO_NAME(f), code, id, outlen));
-}
-
-
-/*
- * fsm_input - Input packet.
- */
-void fsm_input(fsm *f, u_char *inpacket, int l)
-{
-	u_char *inp = inpacket;
-	u_char code, id;
-	int len;
-	
-	/*
-	* Parse header (code, id and length).
-	* If packet too short, drop it.
-	*/
-	if (l < HEADERLEN) {
-		FSMDEBUG((LOG_WARNING, "fsm_input(%x): Rcvd short header.\n",
-					f->protocol));
-		return;
-	}
-	GETCHAR(code, inp);
-	GETCHAR(id, inp);
-	GETSHORT(len, inp);
-	if (len < HEADERLEN) {
-		FSMDEBUG((LOG_INFO, "fsm_input(%x): Rcvd illegal length.\n",
-				f->protocol));
-		return;
-	}
-	if (len > l) {
-		FSMDEBUG((LOG_INFO, "fsm_input(%x): Rcvd short packet.\n",
-				f->protocol));
-		return;
-	}
-	len -= HEADERLEN;		/* subtract header length */
-	
-	if( f->state == INITIAL || f->state == STARTING ){
-		FSMDEBUG((LOG_INFO, "fsm_input(%x): Rcvd packet in state %d.\n",
-				f->protocol, f->state));
-		return;
-	}
-	FSMDEBUG((LOG_INFO, "fsm_input(%s):%d,%d,%d\n", PROTO_NAME(f), code, id, l));
-	/*
-	 * Action depends on code.
-	 */
-	switch (code) {
-	case CONFREQ:
-		fsm_rconfreq(f, id, inp, len);
-		break;
-	
-	case CONFACK:
-		fsm_rconfack(f, id, inp, len);
-		break;
-	
-	case CONFNAK:
-	case CONFREJ:
-		fsm_rconfnakrej(f, code, id, inp, len);
-		break;
-	
-	case TERMREQ:
-		fsm_rtermreq(f, id, inp, len);
-		break;
-	
-	case TERMACK:
-		fsm_rtermack(f);
-		break;
-	
-	case CODEREJ:
-		fsm_rcoderej(f, inp, len);
-		break;
-	
-	default:
-		if( !f->callbacks->extcode
-				|| !(*f->callbacks->extcode)(f, code, id, inp, len) )
-			fsm_sdata(f, CODEREJ, ++f->id, inpacket, len + HEADERLEN);
-		break;
-	}
-}
-
-
-/*
- * fsm_protreject - Peer doesn't speak this protocol.
- *
- * Treat this as a catastrophic error (RXJ-).
- */
-void fsm_protreject(fsm *f)
-{
-	switch( f->state ){
-	case CLOSING:
-		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
-		/* fall through */
-	case CLOSED:
-		f->state = CLOSED;
-		if( f->callbacks->finished )
-			(*f->callbacks->finished)(f);
-		break;
-	
-	case STOPPING:
-	case REQSENT:
-	case ACKRCVD:
-	case ACKSENT:
-		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
-		/* fall through */
-	case STOPPED:
-		f->state = STOPPED;
-		if( f->callbacks->finished )
-			(*f->callbacks->finished)(f);
-		break;
-	
-	case OPENED:
-		if( f->callbacks->down )
-			(*f->callbacks->down)(f);
-		
-		/* Init restart counter, send Terminate-Request */
-		f->retransmits = f->maxtermtransmits;
-		fsm_sdata(f, TERMREQ, f->reqid = ++f->id,
-					(u_char *) f->term_reason, f->term_reason_len);
-		TIMEOUT(fsm_timeout, f, f->timeouttime);
-		--f->retransmits;
-		
-		f->state = STOPPING;
-		break;
-	
-	default:
-		FSMDEBUG((LOG_INFO, "%s: Protocol-reject event in state %d!\n",
-					PROTO_NAME(f), f->state));
-	}
-}
-
-
-
-
-
-/**********************************/
-/*** LOCAL FUNCTION DEFINITIONS ***/
-/**********************************/
-
-/*
- * fsm_timeout - Timeout expired.
- */
-static void fsm_timeout(void *arg)
-{
-    fsm *f = (fsm *) arg;
-
-    switch (f->state) {
-    case CLOSING:
-    case STOPPING:
-		if( f->retransmits <= 0 ){
-		    FSMDEBUG((LOG_WARNING, "%s: timeout sending Terminate-Request state=%d\n",
-					   PROTO_NAME(f), f->state));
-		    /*
-		     * We've waited for an ack long enough.  Peer probably heard us.
-		     */
-		    f->state = (f->state == CLOSING)? CLOSED: STOPPED;
-		    if( f->callbacks->finished )
-			(*f->callbacks->finished)(f);
-		} else {
-		    FSMDEBUG((LOG_WARNING, "%s: timeout resending Terminate-Requests state=%d\n",
-					   PROTO_NAME(f), f->state));
-		    /* Send Terminate-Request */
-		    fsm_sdata(f, TERMREQ, f->reqid = ++f->id,
-			      (u_char *) f->term_reason, f->term_reason_len);
-		    TIMEOUT(fsm_timeout, f, f->timeouttime);
-		    --f->retransmits;
-		}
-		break;
-
-    case REQSENT:
-    case ACKRCVD:
-    case ACKSENT:
-		if (f->retransmits <= 0) {
-		    FSMDEBUG((LOG_WARNING, "%s: timeout sending Config-Requests state=%d\n",
-			   PROTO_NAME(f), f->state));
-		    f->state = STOPPED;
-		    if( (f->flags & OPT_PASSIVE) == 0 && f->callbacks->finished )
-				(*f->callbacks->finished)(f);
-	
-		} else {
-		    FSMDEBUG((LOG_WARNING, "%s: timeout resending Config-Request state=%d\n",
-			   PROTO_NAME(f), f->state));
-		    /* Retransmit the configure-request */
-		    if (f->callbacks->retransmit)
-				(*f->callbacks->retransmit)(f);
-		    fsm_sconfreq(f, 1);		/* Re-send Configure-Request */
-		    if( f->state == ACKRCVD )
-				f->state = REQSENT;
-		}
-		break;
-
-    default:
-		FSMDEBUG((LOG_INFO, "%s: Timeout event in state %d!\n",
-				  PROTO_NAME(f), f->state));
-	    }
-}
-
-
-/*
- * fsm_rconfreq - Receive Configure-Request.
- */
-static void fsm_rconfreq(fsm *f, u_char id, u_char *inp, int len)
-{
-	int code, reject_if_disagree;
-	
-	FSMDEBUG((LOG_INFO, "fsm_rconfreq(%s): Rcvd id %d state=%d\n", 
-				PROTO_NAME(f), id, f->state));
-	switch( f->state ){
-	case CLOSED:
-		/* Go away, we're closed */
-		fsm_sdata(f, TERMACK, id, NULL, 0);
-		return;
-	case CLOSING:
-	case STOPPING:
-		return;
-	
-	case OPENED:
-		/* Go down and restart negotiation */
-		if( f->callbacks->down )
-			(*f->callbacks->down)(f);	/* Inform upper layers */
-		fsm_sconfreq(f, 0);		/* Send initial Configure-Request */
-		break;
-	
-	case STOPPED:
-		/* Negotiation started by our peer */
-		fsm_sconfreq(f, 0);		/* Send initial Configure-Request */
-		f->state = REQSENT;
-		break;
-	}
-	
-	/*
-	* Pass the requested configuration options
-	* to protocol-specific code for checking.
-	*/
-	if (f->callbacks->reqci){		/* Check CI */
-		reject_if_disagree = (f->nakloops >= f->maxnakloops);
-		code = (*f->callbacks->reqci)(f, inp, &len, reject_if_disagree);
-	} 
-	else if (len)
-		code = CONFREJ;			/* Reject all CI */
-	else
-		code = CONFACK;
-	
-	/* send the Ack, Nak or Rej to the peer */
-	fsm_sdata(f, (u_char)code, id, inp, len);
-	
-	if (code == CONFACK) {
-		if (f->state == ACKRCVD) {
-			UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
-			f->state = OPENED;
-			if (f->callbacks->up)
-				(*f->callbacks->up)(f);	/* Inform upper layers */
-		} 
-		else
-			f->state = ACKSENT;
-		f->nakloops = 0;
-	} 
-	else {
-		/* we sent CONFACK or CONFREJ */
-		if (f->state != ACKRCVD)
-			f->state = REQSENT;
-		if( code == CONFNAK )
-			++f->nakloops;
-	}
-}
-
-
-/*
- * fsm_rconfack - Receive Configure-Ack.
- */
-static void fsm_rconfack(fsm *f, int id, u_char *inp, int len)
-{
-	FSMDEBUG((LOG_INFO, "fsm_rconfack(%s): Rcvd id %d state=%d\n",
-				PROTO_NAME(f), id, f->state));
-	
-	if (id != f->reqid || f->seen_ack)		/* Expected id? */
-		return;					/* Nope, toss... */
-	if( !(f->callbacks->ackci? (*f->callbacks->ackci)(f, inp, len):
-								(len == 0)) ){
-		/* Ack is bad - ignore it */
-		FSMDEBUG((LOG_INFO, "%s: received bad Ack (length %d)\n",
-					PROTO_NAME(f), len));
-		return;
-	}
-	f->seen_ack = 1;
-	
-	switch (f->state) {
-	case CLOSED:
-	case STOPPED:
-		fsm_sdata(f, TERMACK, (u_char)id, NULL, 0);
-		break;
-	
-	case REQSENT:
-		f->state = ACKRCVD;
-		f->retransmits = f->maxconfreqtransmits;
-		break;
-	
-	case ACKRCVD:
-		/* Huh? an extra valid Ack? oh well... */
-		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
-		fsm_sconfreq(f, 0);
-		f->state = REQSENT;
-		break;
-	
-	case ACKSENT:
-		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
-		f->state = OPENED;
-		f->retransmits = f->maxconfreqtransmits;
-		if (f->callbacks->up)
-			(*f->callbacks->up)(f);	/* Inform upper layers */
-		break;
-	
-	case OPENED:
-		/* Go down and restart negotiation */
-		if (f->callbacks->down)
-			(*f->callbacks->down)(f);	/* Inform upper layers */
-		fsm_sconfreq(f, 0);		/* Send initial Configure-Request */
-		f->state = REQSENT;
-		break;
-	}
-}
-
-
-/*
- * fsm_rconfnakrej - Receive Configure-Nak or Configure-Reject.
- */
-static void fsm_rconfnakrej(fsm *f, int code, int id, u_char *inp, int len)
-{
-	int (*proc) (fsm *, u_char *, int);
-	int ret;
-	
-	FSMDEBUG((LOG_INFO, "fsm_rconfnakrej(%s): Rcvd id %d state=%d\n",
-				PROTO_NAME(f), id, f->state));
-	
-	if (id != f->reqid || f->seen_ack)	/* Expected id? */
-		return;				/* Nope, toss... */
-	proc = (code == CONFNAK)? f->callbacks->nakci: f->callbacks->rejci;
-	if (!proc || !(ret = proc(f, inp, len))) {
-		/* Nak/reject is bad - ignore it */
-		FSMDEBUG((LOG_INFO, "%s: received bad %s (length %d)\n",
-					PROTO_NAME(f), (code==CONFNAK? "Nak": "reject"), len));
-		return;
-	}
-	f->seen_ack = 1;
-	
-	switch (f->state) {
-	case CLOSED:
-	case STOPPED:
-		fsm_sdata(f, TERMACK, (u_char)id, NULL, 0);
-		break;
-	
-	case REQSENT:
-	case ACKSENT:
-		/* They didn't agree to what we wanted - try another request */
-		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
-		if (ret < 0)
-			f->state = STOPPED;		/* kludge for stopping CCP */
-		else
-			fsm_sconfreq(f, 0);		/* Send Configure-Request */
-		break;
-	
-	case ACKRCVD:
-		/* Got a Nak/reject when we had already had an Ack?? oh well... */
-		UNTIMEOUT(fsm_timeout, f);	/* Cancel timeout */
-		fsm_sconfreq(f, 0);
-		f->state = REQSENT;
-		break;
-	
-	case OPENED:
-		/* Go down and restart negotiation */
-		if (f->callbacks->down)
-			(*f->callbacks->down)(f);	/* Inform upper layers */
-		fsm_sconfreq(f, 0);		/* Send initial Configure-Request */
-		f->state = REQSENT;
-		break;
-	}
-}
-
-
-/*
- * fsm_rtermreq - Receive Terminate-Req.
- */
-static void fsm_rtermreq(fsm *f, int id, u_char *p, int len)
-{
-	FSMDEBUG((LOG_INFO, "fsm_rtermreq(%s): Rcvd id %d state=%d\n",
-				PROTO_NAME(f), id, f->state));
-	
-	switch (f->state) {
-	case ACKRCVD:
-	case ACKSENT:
-		f->state = REQSENT;		/* Start over but keep trying */
-		break;
-	
-	case OPENED:
-		if (len > 0) {
-			FSMDEBUG((LOG_INFO, "%s terminated by peer (%x)\n", PROTO_NAME(f), p));
-		} else {
-			FSMDEBUG((LOG_INFO, "%s terminated by peer\n", PROTO_NAME(f)));
-		}
-		if (f->callbacks->down)
-			(*f->callbacks->down)(f);	/* Inform upper layers */
-		f->retransmits = 0;
-		f->state = STOPPING;
-		TIMEOUT(fsm_timeout, f, f->timeouttime);
-		break;
-	}
-	
-	fsm_sdata(f, TERMACK, (u_char)id, NULL, 0);
-}
-
-
-/*
- * fsm_rtermack - Receive Terminate-Ack.
- */
-static void fsm_rtermack(fsm *f)
-{
-	FSMDEBUG((LOG_INFO, "fsm_rtermack(%s): state=%d\n", 
-				PROTO_NAME(f), f->state));
-	
-	switch (f->state) {
-	case CLOSING:
-		UNTIMEOUT(fsm_timeout, f);
-		f->state = CLOSED;
-		if( f->callbacks->finished )
-			(*f->callbacks->finished)(f);
-		break;
-	case STOPPING:
-		UNTIMEOUT(fsm_timeout, f);
-		f->state = STOPPED;
-		if( f->callbacks->finished )
-			(*f->callbacks->finished)(f);
-		break;
-	
-	case ACKRCVD:
-		f->state = REQSENT;
-		break;
-	
-	case OPENED:
-		if (f->callbacks->down)
-			(*f->callbacks->down)(f);	/* Inform upper layers */
-		fsm_sconfreq(f, 0);
-		break;
-	}
-}
-
-
-/*
- * fsm_rcoderej - Receive an Code-Reject.
- */
-static void fsm_rcoderej(fsm *f, u_char *inp, int len)
-{
-	u_char code, id;
-	
-	FSMDEBUG((LOG_INFO, "fsm_rcoderej(%s): state=%d\n", 
-				PROTO_NAME(f), f->state));
-	
-	if (len < HEADERLEN) {
-		FSMDEBUG((LOG_INFO, "fsm_rcoderej: Rcvd short Code-Reject packet!\n"));
-		return;
-	}
-	GETCHAR(code, inp);
-	GETCHAR(id, inp);
-	FSMDEBUG((LOG_WARNING, "%s: Rcvd Code-Reject for code %d, id %d\n",
-				PROTO_NAME(f), code, id));
-	
-	if( f->state == ACKRCVD )
-		f->state = REQSENT;
-}
-
-
-/*
- * fsm_sconfreq - Send a Configure-Request.
- */
-static void fsm_sconfreq(fsm *f, int retransmit)
-{
-	u_char *outp;
-	int cilen;
-	
-	if( f->state != REQSENT && f->state != ACKRCVD && f->state != ACKSENT ){
-		/* Not currently negotiating - reset options */
-		if( f->callbacks->resetci )
-			(*f->callbacks->resetci)(f);
-		f->nakloops = 0;
-		}
-	
-	if( !retransmit ){
-		/* New request - reset retransmission counter, use new ID */
-		f->retransmits = f->maxconfreqtransmits;
-		f->reqid = ++f->id;
-	}
-	
-	f->seen_ack = 0;
-	
-	/*
-	 * Make up the request packet
-	 */
-	outp = outpacket_buf[f->unit] + PPP_HDRLEN + HEADERLEN;
-	if( f->callbacks->cilen && f->callbacks->addci ){
-		cilen = (*f->callbacks->cilen)(f);
-		if( cilen > peer_mru[f->unit] - (int)HEADERLEN )
-			cilen = peer_mru[f->unit] - HEADERLEN;
-		if (f->callbacks->addci)
-			(*f->callbacks->addci)(f, outp, &cilen);
-	} else
-		cilen = 0;
-	
-	/* send the request to our peer */
-	fsm_sdata(f, CONFREQ, f->reqid, outp, cilen);
-	
-	/* start the retransmit timer */
-	--f->retransmits;
-	TIMEOUT(fsm_timeout, f, f->timeouttime);
-	
-	FSMDEBUG((LOG_INFO, "%s: sending Configure-Request, id %d\n",
-				PROTO_NAME(f), f->reqid));
-}
-
-#endif /* PPP_SUPPORT */
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/fsm.h b/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/fsm.h
deleted file mode 100644
index 6b9b7fed3..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/fsm.h
+++ /dev/null
@@ -1,187 +0,0 @@
-/*****************************************************************************
-* fsm.h - Network Control Protocol Finite State Machine header file.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* Copyright (c) 1997 Global Election Systems Inc.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY
-*
-* 03-01-01 Marc Boucher 
-*   Ported to lwIP.
-* 97-11-05 Guy Lancaster , Global Election Systems Inc.
-*	Original based on BSD code.
-*****************************************************************************/
-/*
- * fsm.h - {Link, IP} Control Protocol Finite State Machine definitions.
- *
- * Copyright (c) 1989 Carnegie Mellon University.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by Carnegie Mellon University.  The name of the
- * University may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- *
- * $Id: fsm.h,v 1.2 2006/08/29 18:53:47 wolti Exp $
- */
-
-#ifndef FSM_H
-#define FSM_H
-
-
-/*****************************************************************************
-************************* PUBLIC DEFINITIONS *********************************
-*****************************************************************************/
-/*
- * LCP Packet header = Code, id, length.
- */
-#define HEADERLEN	(sizeof (u_char) + sizeof (u_char) + sizeof (u_short))
-
-
-/*
- *  CP (LCP, IPCP, etc.) codes.
- */
-#define CONFREQ		1		/* Configuration Request */
-#define CONFACK		2		/* Configuration Ack */
-#define CONFNAK		3		/* Configuration Nak */
-#define CONFREJ		4		/* Configuration Reject */
-#define TERMREQ		5		/* Termination Request */
-#define TERMACK		6		/* Termination Ack */
-#define CODEREJ		7		/* Code Reject */
-
-/*
- * Link states.
- */
-#define INITIAL		0		/* Down, hasn't been opened */
-#define STARTING	1		/* Down, been opened */
-#define CLOSED		2		/* Up, hasn't been opened */
-#define STOPPED		3		/* Open, waiting for down event */
-#define CLOSING		4		/* Terminating the connection, not open */
-#define STOPPING	5		/* Terminating, but open */
-#define REQSENT		6		/* We've sent a Config Request */
-#define ACKRCVD		7		/* We've received a Config Ack */
-#define ACKSENT		8		/* We've sent a Config Ack */
-#define OPENED		9		/* Connection available */
-
-
-/*
- * Flags - indicate options controlling FSM operation
- */
-#define OPT_PASSIVE	1		/* Don't die if we don't get a response */
-#define OPT_RESTART	2		/* Treat 2nd OPEN as DOWN, UP */
-#define OPT_SILENT	4		/* Wait for peer to speak first */
-
-
-/*****************************************************************************
-************************* PUBLIC DATA TYPES **********************************
-*****************************************************************************/
-/*
- * Each FSM is described by an fsm structure and fsm callbacks.
- */
-typedef struct fsm {
-    int unit;				/* Interface unit number */
-    u_short protocol;		/* Data Link Layer Protocol field value */
-    int state;				/* State */
-    int flags;				/* Contains option bits */
-    u_char id;				/* Current id */
-    u_char reqid;			/* Current request id */
-    u_char seen_ack;		/* Have received valid Ack/Nak/Rej to Req */
-    int timeouttime;		/* Timeout time in milliseconds */
-    int maxconfreqtransmits;/* Maximum Configure-Request transmissions */
-    int retransmits;		/* Number of retransmissions left */
-    int maxtermtransmits;	/* Maximum Terminate-Request transmissions */
-    int nakloops;			/* Number of nak loops since last ack */
-    int maxnakloops;		/* Maximum number of nak loops tolerated */
-    struct fsm_callbacks* callbacks;/* Callback routines */
-    char* term_reason;		/* Reason for closing protocol */
-    int term_reason_len;	/* Length of term_reason */
-} fsm;
-
-
-typedef struct fsm_callbacks {
-    void (*resetci)			/* Reset our Configuration Information */
-		(fsm*);
-    int  (*cilen)			/* Length of our Configuration Information */
-		(fsm*);
-    void (*addci) 			/* Add our Configuration Information */
-		(fsm*, u_char*, int*);
-    int  (*ackci)			/* ACK our Configuration Information */
-		(fsm*, u_char*, int);
-    int  (*nakci)			/* NAK our Configuration Information */
-		(fsm*, u_char*, int);
-    int  (*rejci)			/* Reject our Configuration Information */
-		(fsm*, u_char*, int);
-    int  (*reqci)			/* Request peer's Configuration Information */
-		(fsm*, u_char*, int*, int);
-    void (*up)				/* Called when fsm reaches OPENED state */
-		(fsm*);
-    void (*down)			/* Called when fsm leaves OPENED state */
-		(fsm*);
-    void (*starting)		/* Called when we want the lower layer */
-		(fsm*);
-    void (*finished)		/* Called when we don't want the lower layer */
-		(fsm*);
-    void (*protreject)		/* Called when Protocol-Reject received */
-		(int);
-    void (*retransmit)		/* Retransmission is necessary */
-		(fsm*);
-    int  (*extcode)			/* Called when unknown code received */
-		(fsm*, int, u_char, u_char*, int);
-    char *proto_name;		/* String name for protocol (for messages) */
-} fsm_callbacks;
-
-
-/*****************************************************************************
-*********************** PUBLIC DATA STRUCTURES *******************************
-*****************************************************************************/
-/*
- * Variables
- */
-extern int peer_mru[];		/* currently negotiated peer MRU (per unit) */
-
-
-/*****************************************************************************
-************************** PUBLIC FUNCTIONS **********************************
-*****************************************************************************/
-
-/*
- * Prototypes
- */
-void fsm_init (fsm*);
-void fsm_lowerup (fsm*);
-void fsm_lowerdown (fsm*);
-void fsm_open (fsm*);
-void fsm_close (fsm*, char*);
-void fsm_input (fsm*, u_char*, int);
-void fsm_protreject (fsm*);
-void fsm_sdata (fsm*, u_char, u_char, u_char*, int);
-
-
-#endif /* FSM_H */
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/ipcp.c b/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/ipcp.c
deleted file mode 100644
index d5b251880..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/ipcp.c
+++ /dev/null
@@ -1,1377 +0,0 @@
-/*****************************************************************************
-* ipcp.c - Network PPP IP Control Protocol program file.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* portions Copyright (c) 1997 by Global Election Systems Inc.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY
-*
-* 03-01-01 Marc Boucher 
-*   Ported to lwIP.
-* 97-12-08 Guy Lancaster , Global Election Systems Inc.
-*	Original.
-*****************************************************************************/
-/*
- * ipcp.c - PPP IP Control Protocol.
- *
- * Copyright (c) 1989 Carnegie Mellon University.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by Carnegie Mellon University.  The name of the
- * University may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- */
-
-#include 
-
-#include "ppp.h"
-#if PPP_SUPPORT > 0
-#include "auth.h"
-#include "fsm.h"
-#include "vj.h"
-#include "ipcp.h"
-#include "pppdebug.h"
-
-
-/*************************/
-/*** LOCAL DEFINITIONS ***/
-/*************************/
-/* #define OLD_CI_ADDRS 1 */	/* Support deprecated address negotiation. */
-
-/*
- * Lengths of configuration options.
- */
-#define CILEN_VOID	2
-#define CILEN_COMPRESS	4	/* min length for compression protocol opt. */
-#define CILEN_VJ	6	/* length for RFC1332 Van-Jacobson opt. */
-#define CILEN_ADDR	6	/* new-style single address option */
-#define CILEN_ADDRS	10	/* old-style dual address option */
-
-
-
-/***********************************/
-/*** LOCAL FUNCTION DECLARATIONS ***/
-/***********************************/
-/*
- * Callbacks for fsm code.  (CI = Configuration Information)
- */
-static void ipcp_resetci (fsm *);	/* Reset our CI */
-static int  ipcp_cilen (fsm *);	        /* Return length of our CI */
-static void ipcp_addci (fsm *, u_char *, int *); /* Add our CI */
-static int  ipcp_ackci (fsm *, u_char *, int);	/* Peer ack'd our CI */
-static int  ipcp_nakci (fsm *, u_char *, int);	/* Peer nak'd our CI */
-static int  ipcp_rejci (fsm *, u_char *, int);	/* Peer rej'd our CI */
-static int  ipcp_reqci (fsm *, u_char *, int *, int); /* Rcv CI */
-static void ipcp_up (fsm *);		/* We're UP */
-static void ipcp_down (fsm *);		/* We're DOWN */
-#if 0
-static void ipcp_script (fsm *, char *); /* Run an up/down script */
-#endif
-static void ipcp_finished (fsm *);	/* Don't need lower layer */
-
-/*
- * Protocol entry points from main code.
- */
-static void ipcp_init (int);
-static void ipcp_open (int);
-static void ipcp_close (int, char *);
-static void ipcp_lowerup (int);
-static void ipcp_lowerdown (int);
-static void ipcp_input (int, u_char *, int);
-static void ipcp_protrej (int);
-
-static void ipcp_clear_addrs (int);
-
-#define CODENAME(x)	((x) == CONFACK ? "ACK" : \
-			 (x) == CONFNAK ? "NAK" : "REJ")
-
-
-
-/******************************/
-/*** PUBLIC DATA STRUCTURES ***/
-/******************************/
-/* global vars */
-ipcp_options ipcp_wantoptions[NUM_PPP];	/* Options that we want to request */
-ipcp_options ipcp_gotoptions[NUM_PPP];	/* Options that peer ack'd */
-ipcp_options ipcp_allowoptions[NUM_PPP];	/* Options we allow peer to request */
-ipcp_options ipcp_hisoptions[NUM_PPP];	/* Options that we ack'd */
-
-fsm ipcp_fsm[NUM_PPP];		/* IPCP fsm structure */
-
-struct protent ipcp_protent = {
-    PPP_IPCP,
-    ipcp_init,
-    ipcp_input,
-    ipcp_protrej,
-    ipcp_lowerup,
-    ipcp_lowerdown,
-    ipcp_open,
-    ipcp_close,
-#if 0
-    ipcp_printpkt,
-    NULL,
-#endif
-    1,
-    "IPCP",
-#if 0
-    ip_check_options,
-    NULL,
-    ip_active_pkt
-#endif
-};
-
-
-
-/*****************************/
-/*** LOCAL DATA STRUCTURES ***/
-/*****************************/
-/* local vars */
-static int cis_received[NUM_PPP];		/* # Conf-Reqs received */
-static int default_route_set[NUM_PPP];	/* Have set up a default route */
-
-static fsm_callbacks ipcp_callbacks = { /* IPCP callback routines */
-    ipcp_resetci,		/* Reset our Configuration Information */
-    ipcp_cilen,			/* Length of our Configuration Information */
-    ipcp_addci,			/* Add our Configuration Information */
-    ipcp_ackci,			/* ACK our Configuration Information */
-    ipcp_nakci,			/* NAK our Configuration Information */
-    ipcp_rejci,			/* Reject our Configuration Information */
-    ipcp_reqci,			/* Request peer's Configuration Information */
-    ipcp_up,			/* Called when fsm reaches OPENED state */
-    ipcp_down,			/* Called when fsm leaves OPENED state */
-    NULL,				/* Called when we want the lower layer up */
-    ipcp_finished,		/* Called when we want the lower layer down */
-    NULL,				/* Called when Protocol-Reject received */
-    NULL,				/* Retransmission is necessary */
-    NULL,				/* Called to handle protocol-specific codes */
-    "IPCP"				/* String name of protocol */
-};
-
-
-
-/**********************************/
-/*** LOCAL FUNCTION DEFINITIONS ***/
-/**********************************/
-
-/*
- * Non-standard inet_ntoa left here for compat with original ppp
- * sources. Assumes u32_t instead of struct in_addr.
- */ 
-
-char * _inet_ntoa(u32_t n)
-{
-	struct in_addr ia;
-	ia.s_addr = n;
-	return inet_ntoa(ia);
-}
-
-#define inet_ntoa _inet_ntoa
-
-/*
- * ipcp_init - Initialize IPCP.
- */
-static void ipcp_init(int unit)
-{
-	fsm *f = &ipcp_fsm[unit];
-	ipcp_options *wo = &ipcp_wantoptions[unit];
-	ipcp_options *ao = &ipcp_allowoptions[unit];
-	
-	f->unit = unit;
-	f->protocol = PPP_IPCP;
-	f->callbacks = &ipcp_callbacks;
-	fsm_init(&ipcp_fsm[unit]);
-	
-	memset(wo, 0, sizeof(*wo));
-	memset(ao, 0, sizeof(*ao));
-	
-	wo->neg_addr = 1;
-	wo->ouraddr = 0;
-#if VJ_SUPPORT > 0
-	wo->neg_vj = 1;
-#else
-	wo->neg_vj = 0;
-#endif
-	wo->vj_protocol = IPCP_VJ_COMP;
-	wo->maxslotindex = MAX_SLOTS - 1;
-	wo->cflag = 0;
-	
-	wo->default_route = 1;
-	
-	ao->neg_addr = 1;
-#if VJ_SUPPORT > 0
-	ao->neg_vj = 1;
-#else
-	ao->neg_vj = 0;
-#endif
-	ao->maxslotindex = MAX_SLOTS - 1;
-	ao->cflag = 1;
-	
-	ao->default_route = 1;
-}
-
-
-/*
- * ipcp_open - IPCP is allowed to come up.
- */
-static void ipcp_open(int unit)
-{
-	fsm_open(&ipcp_fsm[unit]);
-}
-
-
-/*
- * ipcp_close - Take IPCP down.
- */
-static void ipcp_close(int unit, char *reason)
-{
-	fsm_close(&ipcp_fsm[unit], reason);
-}
-
-
-/*
- * ipcp_lowerup - The lower layer is up.
- */
-static void ipcp_lowerup(int unit)
-{
-	fsm_lowerup(&ipcp_fsm[unit]);
-}
-
-
-/*
- * ipcp_lowerdown - The lower layer is down.
- */
-static void ipcp_lowerdown(int unit)
-{
-	fsm_lowerdown(&ipcp_fsm[unit]);
-}
-
-
-/*
- * ipcp_input - Input IPCP packet.
- */
-static void ipcp_input(int unit, u_char *p, int len)
-{
-	fsm_input(&ipcp_fsm[unit], p, len);
-}
-
-
-/*
- * ipcp_protrej - A Protocol-Reject was received for IPCP.
- *
- * Pretend the lower layer went down, so we shut up.
- */
-static void ipcp_protrej(int unit)
-{
-	fsm_lowerdown(&ipcp_fsm[unit]);
-}
-
-
-/*
- * ipcp_resetci - Reset our CI.
- */
-static void ipcp_resetci(fsm *f)
-{
-	ipcp_options *wo = &ipcp_wantoptions[f->unit];
-	
-	wo->req_addr = wo->neg_addr && ipcp_allowoptions[f->unit].neg_addr;
-	if (wo->ouraddr == 0)
-		wo->accept_local = 1;
-	if (wo->hisaddr == 0)
-		wo->accept_remote = 1;
-	/* Request DNS addresses from the peer */
-	wo->req_dns1 = ppp_settings.usepeerdns;
-	wo->req_dns2 = ppp_settings.usepeerdns;
-	ipcp_gotoptions[f->unit] = *wo;
-	cis_received[f->unit] = 0;
-}
-
-
-/*
- * ipcp_cilen - Return length of our CI.
- */
-static int ipcp_cilen(fsm *f)
-{
-	ipcp_options *go = &ipcp_gotoptions[f->unit];
-	ipcp_options *wo = &ipcp_wantoptions[f->unit];
-	ipcp_options *ho = &ipcp_hisoptions[f->unit];
-	
-#define LENCIVJ(neg, old)	(neg ? (old? CILEN_COMPRESS : CILEN_VJ) : 0)
-#define LENCIADDR(neg, old)	(neg ? (old? CILEN_ADDRS : CILEN_ADDR) : 0)
-#define LENCIDNS(neg)		(neg ? (CILEN_ADDR) : 0)
-	
-	/*
-	 * First see if we want to change our options to the old
-	 * forms because we have received old forms from the peer.
-	 */
-	if (wo->neg_addr && !go->neg_addr && !go->old_addrs) {
-		/* use the old style of address negotiation */
-		go->neg_addr = 1;
-		go->old_addrs = 1;
-	}
-	if (wo->neg_vj && !go->neg_vj && !go->old_vj) {
-		/* try an older style of VJ negotiation */
-		if (cis_received[f->unit] == 0) {
-			/* keep trying the new style until we see some CI from the peer */
-			go->neg_vj = 1;
-		} else {
-			/* use the old style only if the peer did */
-			if (ho->neg_vj && ho->old_vj) {
-				go->neg_vj = 1;
-				go->old_vj = 1;
-				go->vj_protocol = ho->vj_protocol;
-			}
-		}
-	}
-	
-	return (LENCIADDR(go->neg_addr, go->old_addrs)
-			+ LENCIVJ(go->neg_vj, go->old_vj) +
-			LENCIDNS(go->req_dns1) +
-			LENCIDNS(go->req_dns2));
-}
-
-
-/*
- * ipcp_addci - Add our desired CIs to a packet.
- */
-static void ipcp_addci(fsm *f, u_char *ucp, int *lenp)
-{
-	ipcp_options *go = &ipcp_gotoptions[f->unit];
-	int len = *lenp;
-	
-#define ADDCIVJ(opt, neg, val, old, maxslotindex, cflag) \
-	if (neg) { \
-		int vjlen = old? CILEN_COMPRESS : CILEN_VJ; \
-		if (len >= vjlen) { \
-			PUTCHAR(opt, ucp); \
-			PUTCHAR(vjlen, ucp); \
-			PUTSHORT(val, ucp); \
-			if (!old) { \
-				PUTCHAR(maxslotindex, ucp); \
-				PUTCHAR(cflag, ucp); \
-			} \
-			len -= vjlen; \
-		} else \
-			neg = 0; \
-	}
-	
-#define ADDCIADDR(opt, neg, old, val1, val2) \
-	if (neg) { \
-		int addrlen = (old? CILEN_ADDRS: CILEN_ADDR); \
-		if (len >= addrlen) { \
-			u32_t l; \
-			PUTCHAR(opt, ucp); \
-			PUTCHAR(addrlen, ucp); \
-			l = ntohl(val1); \
-			PUTLONG(l, ucp); \
-			if (old) { \
-				l = ntohl(val2); \
-				PUTLONG(l, ucp); \
-			} \
-			len -= addrlen; \
-		} else \
-			neg = 0; \
-	}
-
-#define ADDCIDNS(opt, neg, addr) \
-	if (neg) { \
-		if (len >= CILEN_ADDR) { \
-			u32_t l; \
-			PUTCHAR(opt, ucp); \
-			PUTCHAR(CILEN_ADDR, ucp); \
-			l = ntohl(addr); \
-			PUTLONG(l, ucp); \
-			len -= CILEN_ADDR; \
-		} else \
-			neg = 0; \
-	}
-	
-	ADDCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), go->neg_addr,
-			  go->old_addrs, go->ouraddr, go->hisaddr);
-	
-	ADDCIVJ(CI_COMPRESSTYPE, go->neg_vj, go->vj_protocol, go->old_vj,
-			go->maxslotindex, go->cflag);
-	
-	ADDCIDNS(CI_MS_DNS1, go->req_dns1, go->dnsaddr[0]);
-
-	ADDCIDNS(CI_MS_DNS2, go->req_dns2, go->dnsaddr[1]);
-
-	*lenp -= len;
-}
-
-
-/*
- * ipcp_ackci - Ack our CIs.
- *
- * Returns:
- *	0 - Ack was bad.
- *	1 - Ack was good.
- */
-static int ipcp_ackci(fsm *f, u_char *p, int len)
-{
-	ipcp_options *go = &ipcp_gotoptions[f->unit];
-	u_short cilen, citype, cishort;
-	u32_t cilong;
-	u_char cimaxslotindex, cicflag;
-	
-	/*
-	 * CIs must be in exactly the same order that we sent...
-	 * Check packet length and CI length at each step.
-	 * If we find any deviations, then this packet is bad.
-	 */
-	
-#define ACKCIVJ(opt, neg, val, old, maxslotindex, cflag) \
-	if (neg) { \
-		int vjlen = old? CILEN_COMPRESS : CILEN_VJ; \
-		if ((len -= vjlen) < 0) \
-			goto bad; \
-		GETCHAR(citype, p); \
-		GETCHAR(cilen, p); \
-		if (cilen != vjlen || \
-				citype != opt)  \
-			goto bad; \
-		GETSHORT(cishort, p); \
-		if (cishort != val) \
-			goto bad; \
-		if (!old) { \
-			GETCHAR(cimaxslotindex, p); \
-			if (cimaxslotindex != maxslotindex) \
-				goto bad; \
-			GETCHAR(cicflag, p); \
-			if (cicflag != cflag) \
-				goto bad; \
-		} \
-	}
-	
-#define ACKCIADDR(opt, neg, old, val1, val2) \
-	if (neg) { \
-		int addrlen = (old? CILEN_ADDRS: CILEN_ADDR); \
-		u32_t l; \
-		if ((len -= addrlen) < 0) \
-			goto bad; \
-		GETCHAR(citype, p); \
-		GETCHAR(cilen, p); \
-		if (cilen != addrlen || \
-				citype != opt) \
-			goto bad; \
-		GETLONG(l, p); \
-		cilong = htonl(l); \
-		if (val1 != cilong) \
-			goto bad; \
-		if (old) { \
-			GETLONG(l, p); \
-			cilong = htonl(l); \
-			if (val2 != cilong) \
-				goto bad; \
-		} \
-	}
-
-#define ACKCIDNS(opt, neg, addr) \
-	if (neg) { \
-		u32_t l; \
-		if ((len -= CILEN_ADDR) < 0) \
-			goto bad; \
-		GETCHAR(citype, p); \
-		GETCHAR(cilen, p); \
-		if (cilen != CILEN_ADDR || \
-				citype != opt) \
-			goto bad; \
-		GETLONG(l, p); \
-		cilong = htonl(l); \
-		if (addr != cilong) \
-			goto bad; \
-	}
-	
-	ACKCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), go->neg_addr,
-			  go->old_addrs, go->ouraddr, go->hisaddr);
-	
-	ACKCIVJ(CI_COMPRESSTYPE, go->neg_vj, go->vj_protocol, go->old_vj,
-			go->maxslotindex, go->cflag);
-	
-	ACKCIDNS(CI_MS_DNS1, go->req_dns1, go->dnsaddr[0]);
-
-	ACKCIDNS(CI_MS_DNS2, go->req_dns2, go->dnsaddr[1]);
-
-	/*
-	 * If there are any remaining CIs, then this packet is bad.
-	 */
-	if (len != 0)
-		goto bad;
-	return (1);
-	
-bad:
-	IPCPDEBUG((LOG_INFO, "ipcp_ackci: received bad Ack!\n"));
-	return (0);
-}
-
-/*
- * ipcp_nakci - Peer has sent a NAK for some of our CIs.
- * This should not modify any state if the Nak is bad
- * or if IPCP is in the OPENED state.
- *
- * Returns:
- *	0 - Nak was bad.
- *	1 - Nak was good.
- */
-static int ipcp_nakci(fsm *f, u_char *p, int len)
-{
-	ipcp_options *go = &ipcp_gotoptions[f->unit];
-	u_char cimaxslotindex, cicflag;
-	u_char citype, cilen, *next;
-	u_short cishort;
-	u32_t ciaddr1, ciaddr2, l, cidnsaddr;
-	ipcp_options no;		/* options we've seen Naks for */
-	ipcp_options try;		/* options to request next time */
-	
-	BZERO(&no, sizeof(no));
-	try = *go;
-	
-	/*
-	 * Any Nak'd CIs must be in exactly the same order that we sent.
-	 * Check packet length and CI length at each step.
-	 * If we find any deviations, then this packet is bad.
-	 */
-#define NAKCIADDR(opt, neg, old, code) \
-	if (go->neg && \
-			len >= (cilen = (old? CILEN_ADDRS: CILEN_ADDR)) && \
-			p[1] == cilen && \
-			p[0] == opt) { \
-		len -= cilen; \
-		INCPTR(2, p); \
-		GETLONG(l, p); \
-		ciaddr1 = htonl(l); \
-		if (old) { \
-			GETLONG(l, p); \
-			ciaddr2 = htonl(l); \
-			no.old_addrs = 1; \
-		} else \
-			ciaddr2 = 0; \
-		no.neg = 1; \
-		code \
-	}
-	
-#define NAKCIVJ(opt, neg, code) \
-	if (go->neg && \
-			((cilen = p[1]) == CILEN_COMPRESS || cilen == CILEN_VJ) && \
-			len >= cilen && \
-			p[0] == opt) { \
-		len -= cilen; \
-		INCPTR(2, p); \
-		GETSHORT(cishort, p); \
-		no.neg = 1; \
-		code \
-	}
-	
-#define NAKCIDNS(opt, neg, code) \
-	if (go->neg && \
-			((cilen = p[1]) == CILEN_ADDR) && \
-			len >= cilen && \
-			p[0] == opt) { \
-		len -= cilen; \
-		INCPTR(2, p); \
-		GETLONG(l, p); \
-		cidnsaddr = htonl(l); \
-		no.neg = 1; \
-		code \
-	}
-	
-	/*
-	 * Accept the peer's idea of {our,his} address, if different
-	 * from our idea, only if the accept_{local,remote} flag is set.
-	 */
-	NAKCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), neg_addr, go->old_addrs,
-	  if (go->accept_local && ciaddr1) { /* Do we know our address? */
-		  try.ouraddr = ciaddr1;
-		  IPCPDEBUG((LOG_INFO, "local IP address %s\n",
-			     inet_ntoa(ciaddr1)));
-	  }
-	  if (go->accept_remote && ciaddr2) { /* Does he know his? */
-		  try.hisaddr = ciaddr2;
-		  IPCPDEBUG((LOG_INFO, "remote IP address %s\n",
-			     inet_ntoa(ciaddr2)));
-	  }
-	);
-	
-	/*
-	 * Accept the peer's value of maxslotindex provided that it
-	 * is less than what we asked for.  Turn off slot-ID compression
-	 * if the peer wants.  Send old-style compress-type option if
-	 * the peer wants.
-	 */
-	NAKCIVJ(CI_COMPRESSTYPE, neg_vj,
-		if (cilen == CILEN_VJ) {
-			GETCHAR(cimaxslotindex, p);
-			GETCHAR(cicflag, p);
-			if (cishort == IPCP_VJ_COMP) {
-				try.old_vj = 0;
-				if (cimaxslotindex < go->maxslotindex)
-					try.maxslotindex = cimaxslotindex;
-				if (!cicflag)
-					try.cflag = 0;
-			} else {
-				try.neg_vj = 0;
-			}
-		} else {
-			if (cishort == IPCP_VJ_COMP || cishort == IPCP_VJ_COMP_OLD) {
-				try.old_vj = 1;
-				try.vj_protocol = cishort;
-			} else {
-				try.neg_vj = 0;
-			}
-		}
-	);
-	
-	NAKCIDNS(CI_MS_DNS1, req_dns1,
-			try.dnsaddr[0] = cidnsaddr;
-		  	IPCPDEBUG((LOG_INFO, "primary DNS address %s\n", inet_ntoa(cidnsaddr)));
-			);
-
-	NAKCIDNS(CI_MS_DNS2, req_dns2,
-			try.dnsaddr[1] = cidnsaddr;
-		  	IPCPDEBUG((LOG_INFO, "secondary DNS address %s\n", inet_ntoa(cidnsaddr)));
-			);
-
-	/*
-	* There may be remaining CIs, if the peer is requesting negotiation
-	* on an option that we didn't include in our request packet.
-	* If they want to negotiate about IP addresses, we comply.
-	* If they want us to ask for compression, we refuse.
-	*/
-	while (len > CILEN_VOID) {
-		GETCHAR(citype, p);
-		GETCHAR(cilen, p);
-		if( (len -= cilen) < 0 )
-			goto bad;
-		next = p + cilen - 2;
-		
-		switch (citype) {
-		case CI_COMPRESSTYPE:
-			if (go->neg_vj || no.neg_vj ||
-					(cilen != CILEN_VJ && cilen != CILEN_COMPRESS))
-				goto bad;
-			no.neg_vj = 1;
-			break;
-		case CI_ADDRS:
-			if ((go->neg_addr && go->old_addrs) || no.old_addrs
-					|| cilen != CILEN_ADDRS)
-				goto bad;
-			try.neg_addr = 1;
-			try.old_addrs = 1;
-			GETLONG(l, p);
-			ciaddr1 = htonl(l);
-			if (ciaddr1 && go->accept_local)
-				try.ouraddr = ciaddr1;
-			GETLONG(l, p);
-			ciaddr2 = htonl(l);
-			if (ciaddr2 && go->accept_remote)
-				try.hisaddr = ciaddr2;
-			no.old_addrs = 1;
-			break;
-		case CI_ADDR:
-			if (go->neg_addr || no.neg_addr || cilen != CILEN_ADDR)
-				goto bad;
-			try.old_addrs = 0;
-			GETLONG(l, p);
-			ciaddr1 = htonl(l);
-			if (ciaddr1 && go->accept_local)
-				try.ouraddr = ciaddr1;
-			if (try.ouraddr != 0)
-				try.neg_addr = 1;
-			no.neg_addr = 1;
-			break;
-		}
-		p = next;
-	}
-	
-	/* If there is still anything left, this packet is bad. */
-	if (len != 0)
-		goto bad;
-	
-	/*
-	 * OK, the Nak is good.  Now we can update state.
-	 */
-	if (f->state != OPENED)
-		*go = try;
-	
-	return 1;
-	
-bad:
-	IPCPDEBUG((LOG_INFO, "ipcp_nakci: received bad Nak!\n"));
-	return 0;
-}
-
-
-/*
- * ipcp_rejci - Reject some of our CIs.
- */
-static int ipcp_rejci(fsm *f, u_char *p, int len)
-{
-	ipcp_options *go = &ipcp_gotoptions[f->unit];
-	u_char cimaxslotindex, ciflag, cilen;
-	u_short cishort;
-	u32_t cilong;
-	ipcp_options try;		/* options to request next time */
-	
-	try = *go;
-	/*
-	 * Any Rejected CIs must be in exactly the same order that we sent.
-	 * Check packet length and CI length at each step.
-	 * If we find any deviations, then this packet is bad.
-	 */
-#define REJCIADDR(opt, neg, old, val1, val2) \
-	if (go->neg && \
-			len >= (cilen = old? CILEN_ADDRS: CILEN_ADDR) && \
-			p[1] == cilen && \
-			p[0] == opt) { \
-		u32_t l; \
-		len -= cilen; \
-		INCPTR(2, p); \
-		GETLONG(l, p); \
-		cilong = htonl(l); \
-		/* Check rejected value. */ \
-		if (cilong != val1) \
-			goto bad; \
-		if (old) { \
-			GETLONG(l, p); \
-			cilong = htonl(l); \
-			/* Check rejected value. */ \
-			if (cilong != val2) \
-				goto bad; \
-		} \
-		try.neg = 0; \
-	}
-	
-#define REJCIVJ(opt, neg, val, old, maxslot, cflag) \
-	if (go->neg && \
-			p[1] == (old? CILEN_COMPRESS : CILEN_VJ) && \
-			len >= p[1] && \
-			p[0] == opt) { \
-		len -= p[1]; \
-		INCPTR(2, p); \
-		GETSHORT(cishort, p); \
-		/* Check rejected value. */  \
-		if (cishort != val) \
-			goto bad; \
-		if (!old) { \
-			GETCHAR(cimaxslotindex, p); \
-			if (cimaxslotindex != maxslot) \
-				goto bad; \
-			GETCHAR(ciflag, p); \
-			if (ciflag != cflag) \
-				goto bad; \
-		} \
-		try.neg = 0; \
-	}
-	
-#define REJCIDNS(opt, neg, dnsaddr) \
-	if (go->neg && \
-			((cilen = p[1]) == CILEN_ADDR) && \
-			len >= cilen && \
-			p[0] == opt) { \
-		u32_t l; \
-		len -= cilen; \
-		INCPTR(2, p); \
-		GETLONG(l, p); \
-		cilong = htonl(l); \
-		/* Check rejected value. */ \
-		if (cilong != dnsaddr) \
-			goto bad; \
-		try.neg = 0; \
-	}
-
-	REJCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), neg_addr,
-			  go->old_addrs, go->ouraddr, go->hisaddr);
-	
-	REJCIVJ(CI_COMPRESSTYPE, neg_vj, go->vj_protocol, go->old_vj,
-			go->maxslotindex, go->cflag);
-	
-	REJCIDNS(CI_MS_DNS1, req_dns1, go->dnsaddr[0]);
-
-	REJCIDNS(CI_MS_DNS2, req_dns2, go->dnsaddr[1]);
-
-	/*
-	 * If there are any remaining CIs, then this packet is bad.
-	 */
-	if (len != 0)
-		goto bad;
-	/*
-	 * Now we can update state.
-	 */
-	if (f->state != OPENED)
-		*go = try;
-	return 1;
-	
-bad:
-	IPCPDEBUG((LOG_INFO, "ipcp_rejci: received bad Reject!\n"));
-	return 0;
-}
-
-
-/*
- * ipcp_reqci - Check the peer's requested CIs and send appropriate response.
- *
- * Returns: CONFACK, CONFNAK or CONFREJ and input packet modified
- * appropriately.  If reject_if_disagree is non-zero, doesn't return
- * CONFNAK; returns CONFREJ if it can't return CONFACK.
- */
-static int ipcp_reqci(
-	fsm *f,
-	u_char *inp,		/* Requested CIs */
-	int *len,			/* Length of requested CIs */
-	int reject_if_disagree
-)
-{
-	ipcp_options *wo = &ipcp_wantoptions[f->unit];
-	ipcp_options *ho = &ipcp_hisoptions[f->unit];
-	ipcp_options *ao = &ipcp_allowoptions[f->unit];
-#ifdef OLD_CI_ADDRS
-	ipcp_options *go = &ipcp_gotoptions[f->unit];
-#endif
-	u_char *cip, *next;				/* Pointer to current and next CIs */
-	u_short cilen, citype;			/* Parsed len, type */
-	u_short cishort;				/* Parsed short value */
-	u32_t tl, ciaddr1;			/* Parsed address values */
-#ifdef OLD_CI_ADDRS
-	u32_t ciaddr2;				/* Parsed address values */
-#endif
-	int rc = CONFACK;				/* Final packet return code */
-	int orc;						/* Individual option return code */
-	u_char *p;						/* Pointer to next char to parse */
-	u_char *ucp = inp;				/* Pointer to current output char */
-	int l = *len;					/* Length left */
-	u_char maxslotindex, cflag;
-	int d;
-	
-	cis_received[f->unit] = 1;
-	
-	/*
-	 * Reset all his options.
-	 */
-	BZERO(ho, sizeof(*ho));
-	
-	/*
-	 * Process all his options.
-	 */
-	next = inp;
-	while (l) {
-		orc = CONFACK;				/* Assume success */
-		cip = p = next;				/* Remember begining of CI */
-		if (l < 2 ||				/* Not enough data for CI header or */
-				p[1] < 2 ||			/*  CI length too small or */
-				p[1] > l) {			/*  CI length too big? */
-			IPCPDEBUG((LOG_INFO, "ipcp_reqci: bad CI length!\n"));
-			orc = CONFREJ;			/* Reject bad CI */
-			cilen = l;				/* Reject till end of packet */
-			l = 0;					/* Don't loop again */
-			goto endswitch;
-		}
-		GETCHAR(citype, p);			/* Parse CI type */
-		GETCHAR(cilen, p);			/* Parse CI length */
-		l -= cilen;					/* Adjust remaining length */
-		next += cilen;				/* Step to next CI */
-
-		switch (citype) {			/* Check CI type */
-#ifdef OLD_CI_ADDRS /* Need to save space... */
-		case CI_ADDRS:
-			IPCPDEBUG((LOG_INFO, "ipcp_reqci: received ADDRS\n"));
-			if (!ao->neg_addr ||
-					cilen != CILEN_ADDRS) {	/* Check CI length */
-				orc = CONFREJ;		/* Reject CI */
-				break;
-			}
-			
-			/*
-			 * If he has no address, or if we both have his address but
-			 * disagree about it, then NAK it with our idea.
-			 * In particular, if we don't know his address, but he does,
-			 * then accept it.
-			 */
-			GETLONG(tl, p);		/* Parse source address (his) */
-			ciaddr1 = htonl(tl);
-			IPCPDEBUG((LOG_INFO, "his addr %s\n", inet_ntoa(ciaddr1)));
-			if (ciaddr1 != wo->hisaddr
-					&& (ciaddr1 == 0 || !wo->accept_remote)) {
-				orc = CONFNAK;
-				if (!reject_if_disagree) {
-					DECPTR(sizeof(u32_t), p);
-					tl = ntohl(wo->hisaddr);
-					PUTLONG(tl, p);
-				}
-			} else if (ciaddr1 == 0 && wo->hisaddr == 0) {
-				/*
-				 * If neither we nor he knows his address, reject the option.
-				 */
-				orc = CONFREJ;
-				wo->req_addr = 0;	/* don't NAK with 0.0.0.0 later */
-				break;
-			}
-			
-			/*
-			 * If he doesn't know our address, or if we both have our address
-			 * but disagree about it, then NAK it with our idea.
-			 */
-			GETLONG(tl, p);		/* Parse desination address (ours) */
-			ciaddr2 = htonl(tl);
-			IPCPDEBUG((LOG_INFO, "our addr %s\n", inet_ntoa(ciaddr2)));
-			if (ciaddr2 != wo->ouraddr) {
-				if (ciaddr2 == 0 || !wo->accept_local) {
-					orc = CONFNAK;
-					if (!reject_if_disagree) {
-						DECPTR(sizeof(u32_t), p);
-						tl = ntohl(wo->ouraddr);
-						PUTLONG(tl, p);
-					}
-				} else {
-					go->ouraddr = ciaddr2;	/* accept peer's idea */
-				}
-			}
-			
-			ho->neg_addr = 1;
-			ho->old_addrs = 1;
-			ho->hisaddr = ciaddr1;
-			ho->ouraddr = ciaddr2;
-			break;
-#endif
-		
-		case CI_ADDR:
-			if (!ao->neg_addr) {
-				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Reject ADDR not allowed\n"));
-				orc = CONFREJ;				/* Reject CI */
-				break;
-			} else if (cilen != CILEN_ADDR) {	/* Check CI length */
-				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Reject ADDR bad len\n"));
-				orc = CONFREJ;				/* Reject CI */
-				break;
-			}
-			
-			/*
-			 * If he has no address, or if we both have his address but
-			 * disagree about it, then NAK it with our idea.
-			 * In particular, if we don't know his address, but he does,
-			 * then accept it.
-			 */
-			GETLONG(tl, p);	/* Parse source address (his) */
-			ciaddr1 = htonl(tl);
-			if (ciaddr1 != wo->hisaddr
-					&& (ciaddr1 == 0 || !wo->accept_remote)) {
-				orc = CONFNAK;
-				if (!reject_if_disagree) {
-					DECPTR(sizeof(u32_t), p);
-					tl = ntohl(wo->hisaddr);
-					PUTLONG(tl, p);
-				}
-				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Nak ADDR %s\n", inet_ntoa(ciaddr1)));
-			} else if (ciaddr1 == 0 && wo->hisaddr == 0) {
-				/*
-				 * Don't ACK an address of 0.0.0.0 - reject it instead.
-				 */
-				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Reject ADDR %s\n", inet_ntoa(ciaddr1)));
-				orc = CONFREJ;
-				wo->req_addr = 0;	/* don't NAK with 0.0.0.0 later */
-				break;
-			}
-			
-			ho->neg_addr = 1;
-			ho->hisaddr = ciaddr1;
-			IPCPDEBUG((LOG_INFO, "ipcp_reqci: ADDR %s\n", inet_ntoa(ciaddr1)));
-			break;
-		
-		case CI_MS_DNS1:
-		case CI_MS_DNS2:
-			/* Microsoft primary or secondary DNS request */
-			d = citype == CI_MS_DNS2;
-			
-			/* If we do not have a DNS address then we cannot send it */
-			if (ao->dnsaddr[d] == 0 ||
-					cilen != CILEN_ADDR) {	/* Check CI length */
-				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting DNS%d Request\n", d+1));
-				orc = CONFREJ;				/* Reject CI */
-				break;
-			}
-			GETLONG(tl, p);
-			if (htonl(tl) != ao->dnsaddr[d]) {
-				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Naking DNS%d Request %d\n",
-							d+1, inet_ntoa(tl)));
-				DECPTR(sizeof(u32_t), p);
-				tl = ntohl(ao->dnsaddr[d]);
-				PUTLONG(tl, p);
-				orc = CONFNAK;
-			}
-			IPCPDEBUG((LOG_INFO, "ipcp_reqci: received DNS%d Request\n", d+1));
-			break;
-		
-		case CI_MS_WINS1:
-		case CI_MS_WINS2:
-			/* Microsoft primary or secondary WINS request */
-			d = citype == CI_MS_WINS2;
-			IPCPDEBUG((LOG_INFO, "ipcp_reqci: received WINS%d Request\n", d+1));
-			
-			/* If we do not have a DNS address then we cannot send it */
-			if (ao->winsaddr[d] == 0 ||
-				cilen != CILEN_ADDR) {	/* Check CI length */
-				orc = CONFREJ;			/* Reject CI */
-				break;
-			}
-			GETLONG(tl, p);
-			if (htonl(tl) != ao->winsaddr[d]) {
-				DECPTR(sizeof(u32_t), p);
-				tl = ntohl(ao->winsaddr[d]);
-				PUTLONG(tl, p);
-				orc = CONFNAK;
-			}
-			break;
-		
-		case CI_COMPRESSTYPE:
-			if (!ao->neg_vj) {
-				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting COMPRESSTYPE not allowed\n"));
-				orc = CONFREJ;
-				break;
-			} else if (cilen != CILEN_VJ && cilen != CILEN_COMPRESS) {
-				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting COMPRESSTYPE len=%d\n", cilen));
-				orc = CONFREJ;
-				break;
-			}
-			GETSHORT(cishort, p);
-			
-			if (!(cishort == IPCP_VJ_COMP ||
-					(cishort == IPCP_VJ_COMP_OLD && cilen == CILEN_COMPRESS))) {
-				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting COMPRESSTYPE %d\n", cishort));
-				orc = CONFREJ;
-				break;
-			}
-			
-			ho->neg_vj = 1;
-			ho->vj_protocol = cishort;
-			if (cilen == CILEN_VJ) {
-				GETCHAR(maxslotindex, p);
-				if (maxslotindex > ao->maxslotindex) { 
-					IPCPDEBUG((LOG_INFO, "ipcp_reqci: Naking VJ max slot %d\n", maxslotindex));
-					orc = CONFNAK;
-					if (!reject_if_disagree){
-						DECPTR(1, p);
-						PUTCHAR(ao->maxslotindex, p);
-					}
-				}
-				GETCHAR(cflag, p);
-				if (cflag && !ao->cflag) {
-					IPCPDEBUG((LOG_INFO, "ipcp_reqci: Naking VJ cflag %d\n", cflag));
-					orc = CONFNAK;
-					if (!reject_if_disagree){
-						DECPTR(1, p);
-						PUTCHAR(wo->cflag, p);
-					}
-				}
-				ho->maxslotindex = maxslotindex;
-				ho->cflag = cflag;
-			} else {
-				ho->old_vj = 1;
-				ho->maxslotindex = MAX_SLOTS - 1;
-				ho->cflag = 1;
-			}
-			IPCPDEBUG((LOG_INFO, 
-						"ipcp_reqci: received COMPRESSTYPE p=%d old=%d maxslot=%d cflag=%d\n",
-						ho->vj_protocol, ho->old_vj, ho->maxslotindex, ho->cflag));
-			break;
-			
-		default:
-			IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting unknown CI type %d\n", citype));
-			orc = CONFREJ;
-			break;
-		}
-		
-endswitch:
-		if (orc == CONFACK &&		/* Good CI */
-				rc != CONFACK)		/*  but prior CI wasnt? */
-			continue;				/* Don't send this one */
-		
-		if (orc == CONFNAK) {		/* Nak this CI? */
-			if (reject_if_disagree) {	/* Getting fed up with sending NAKs? */
-				IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting too many naks\n"));
-				orc = CONFREJ;		/* Get tough if so */
-			} else {
-				if (rc == CONFREJ)	/* Rejecting prior CI? */
-					continue;		/* Don't send this one */
-				if (rc == CONFACK) {	/* Ack'd all prior CIs? */
-					rc = CONFNAK;	/* Not anymore... */
-					ucp = inp;		/* Backup */
-				}
-			}
-		}
-		
-		if (orc == CONFREJ &&		/* Reject this CI */
-				rc != CONFREJ) {	/*  but no prior ones? */
-			rc = CONFREJ;
-			ucp = inp;				/* Backup */
-		}
-		
-		/* Need to move CI? */
-		if (ucp != cip)
-			BCOPY(cip, ucp, cilen);	/* Move it */
-		
-		/* Update output pointer */
-		INCPTR(cilen, ucp);
-	}
-	
-	/*
-	 * If we aren't rejecting this packet, and we want to negotiate
-	 * their address, and they didn't send their address, then we
-	 * send a NAK with a CI_ADDR option appended.  We assume the
-	 * input buffer is long enough that we can append the extra
-	 * option safely.
-	 */
-	if (rc != CONFREJ && !ho->neg_addr &&
-			wo->req_addr && !reject_if_disagree) {
-		IPCPDEBUG((LOG_INFO, "ipcp_reqci: Requesting peer address\n"));
-		if (rc == CONFACK) {
-			rc = CONFNAK;
-			ucp = inp;				/* reset pointer */
-			wo->req_addr = 0;		/* don't ask again */
-		}
-		PUTCHAR(CI_ADDR, ucp);
-		PUTCHAR(CILEN_ADDR, ucp);
-		tl = ntohl(wo->hisaddr);
-		PUTLONG(tl, ucp);
-	}
-	
-	*len = (int)(ucp - inp);		/* Compute output length */
-	IPCPDEBUG((LOG_INFO, "ipcp_reqci: returning Configure-%s\n", CODENAME(rc)));
-	return (rc);			/* Return final code */
-}
-
-
-#if 0
-/*
- * ip_check_options - check that any IP-related options are OK,
- * and assign appropriate defaults.
- */
-static void ip_check_options(u_long localAddr)
-{
-	ipcp_options *wo = &ipcp_wantoptions[0];
-
-	/*
-	 * Load our default IP address but allow the remote host to give us
-	 * a new address.
-	 */
-	if (wo->ouraddr == 0 && !ppp_settings.disable_defaultip) {
-		wo->accept_local = 1;	/* don't insist on this default value */
-		wo->ouraddr = htonl(localAddr);
-	}
-}
-#endif
-
-
-/*
- * ipcp_up - IPCP has come UP.
- *
- * Configure the IP network interface appropriately and bring it up.
- */
-static void ipcp_up(fsm *f)
-{
-	u32_t mask;
-	ipcp_options *ho = &ipcp_hisoptions[f->unit];
-	ipcp_options *go = &ipcp_gotoptions[f->unit];
-	ipcp_options *wo = &ipcp_wantoptions[f->unit];
-	
-	np_up(f->unit, PPP_IP);
-	IPCPDEBUG((LOG_INFO, "ipcp: up\n"));
-	
-	/*
-	 * We must have a non-zero IP address for both ends of the link.
-	 */
-	if (!ho->neg_addr)
-		ho->hisaddr = wo->hisaddr;
-	
-	if (ho->hisaddr == 0) {
-		IPCPDEBUG((LOG_ERR, "Could not determine remote IP address\n"));
-		ipcp_close(f->unit, "Could not determine remote IP address");
-		return;
-	}
-	if (go->ouraddr == 0) {
-		IPCPDEBUG((LOG_ERR, "Could not determine local IP address\n"));
-		ipcp_close(f->unit, "Could not determine local IP address");
-		return;
-	}
-	
-	if (ppp_settings.usepeerdns && (go->dnsaddr[0] || go->dnsaddr[1])) {
-		/*pppGotDNSAddrs(go->dnsaddr[0], go->dnsaddr[1]);*/
-	}
-
-	/*
-	 * Check that the peer is allowed to use the IP address it wants.
-	 */
-	if (!auth_ip_addr(f->unit, ho->hisaddr)) {
-		IPCPDEBUG((LOG_ERR, "Peer is not authorized to use remote address %s\n",
-				inet_ntoa(ho->hisaddr)));
-		ipcp_close(f->unit, "Unauthorized remote IP address");
-		return;
-	}
-	
-	/* set tcp compression */
-	sifvjcomp(f->unit, ho->neg_vj, ho->cflag, ho->maxslotindex);
-	
-	/*
-	 * Set IP addresses and (if specified) netmask.
-	 */
-	mask = GetMask(go->ouraddr);
-	
-	if (!sifaddr(f->unit, go->ouraddr, ho->hisaddr, mask, go->dnsaddr[0], go->dnsaddr[1])) {
-		IPCPDEBUG((LOG_WARNING, "sifaddr failed\n"));
-		ipcp_close(f->unit, "Interface configuration failed");
-		return;
-	}
-	
-	/* bring the interface up for IP */
-	if (!sifup(f->unit)) {
-		IPCPDEBUG((LOG_WARNING, "sifup failed\n"));
-		ipcp_close(f->unit, "Interface configuration failed");
-		return;
-	}
-	
-	sifnpmode(f->unit, PPP_IP, NPMODE_PASS);
-	
-	/* assign a default route through the interface if required */
-	if (ipcp_wantoptions[f->unit].default_route) 
-		if (sifdefaultroute(f->unit, go->ouraddr, ho->hisaddr))
-			default_route_set[f->unit] = 1;
-	
-	IPCPDEBUG((LOG_NOTICE, "local  IP address %s\n", inet_ntoa(go->ouraddr)));
-	IPCPDEBUG((LOG_NOTICE, "remote IP address %s\n", inet_ntoa(ho->hisaddr)));
-	if (go->dnsaddr[0]) {
-		IPCPDEBUG((LOG_NOTICE, "primary   DNS address %s\n", inet_ntoa(go->dnsaddr[0])));
-	}
-	if (go->dnsaddr[1]) {
-		IPCPDEBUG((LOG_NOTICE, "secondary DNS address %s\n", inet_ntoa(go->dnsaddr[1])));
-	}
-}
-
-
-/*
- * ipcp_down - IPCP has gone DOWN.
- *
- * Take the IP network interface down, clear its addresses
- * and delete routes through it.
- */
-static void ipcp_down(fsm *f)
-{
-	IPCPDEBUG((LOG_INFO, "ipcp: down\n"));
-	np_down(f->unit, PPP_IP);
-	sifvjcomp(f->unit, 0, 0, 0);
-	
-	sifdown(f->unit);
-	ipcp_clear_addrs(f->unit);
-}
-
-
-/*
- * ipcp_clear_addrs() - clear the interface addresses, routes, etc.
- */
-static void ipcp_clear_addrs(int unit)
-{
-	u32_t ouraddr, hisaddr;
-	
-	ouraddr = ipcp_gotoptions[unit].ouraddr;
-	hisaddr = ipcp_hisoptions[unit].hisaddr;
-	if (default_route_set[unit]) {
-		cifdefaultroute(unit, ouraddr, hisaddr);
-		default_route_set[unit] = 0;
-	}
-	cifaddr(unit, ouraddr, hisaddr);
-}
-
-
-/*
- * ipcp_finished - possibly shut down the lower layers.
- */
-static void ipcp_finished(fsm *f)
-{
-	np_finished(f->unit, PPP_IP);
-}
-
-#if 0
-static int ipcp_printpkt(
-	u_char *p,
-	int plen,
-	void (*printer) (void *, char *, ...),
-	void *arg
-)
-{
-	(void)p;
-	(void)plen;
-	(void)printer;
-	(void)arg;
-	return 0;
-}
-
-/*
- * ip_active_pkt - see if this IP packet is worth bringing the link up for.
- * We don't bring the link up for IP fragments or for TCP FIN packets
- * with no data.
- */
-#define IP_HDRLEN	20	/* bytes */
-#define IP_OFFMASK	0x1fff
-#define IPPROTO_TCP	6
-#define TCP_HDRLEN	20
-#define TH_FIN		0x01
-
-/*
- * We use these macros because the IP header may be at an odd address,
- * and some compilers might use word loads to get th_off or ip_hl.
- */
-
-#define net_short(x)	(((x)[0] << 8) + (x)[1])
-#define get_iphl(x)	(((unsigned char *)(x))[0] & 0xF)
-#define get_ipoff(x)	net_short((unsigned char *)(x) + 6)
-#define get_ipproto(x)	(((unsigned char *)(x))[9])
-#define get_tcpoff(x)	(((unsigned char *)(x))[12] >> 4)
-#define get_tcpflags(x)	(((unsigned char *)(x))[13])
-
-static int ip_active_pkt(u_char *pkt, int len)
-{
-	u_char *tcp;
-	int hlen;
-	
-	len -= PPP_HDRLEN;
-	pkt += PPP_HDRLEN;
-	if (len < IP_HDRLEN)
-		return 0;
-	if ((get_ipoff(pkt) & IP_OFFMASK) != 0)
-		return 0;
-	if (get_ipproto(pkt) != IPPROTO_TCP)
-		return 1;
-	hlen = get_iphl(pkt) * 4;
-	if (len < hlen + TCP_HDRLEN)
-		return 0;
-	tcp = pkt + hlen;
-	if ((get_tcpflags(tcp) & TH_FIN) != 0 && len == hlen + get_tcpoff(tcp) * 4)
-		return 0;
-	return 1;
-}
-#endif
-
-#endif /* PPP_SUPPORT */
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/ipcp.h b/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/ipcp.h
deleted file mode 100644
index e907bdfce..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/ipcp.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/*****************************************************************************
-* ipcp.h -  PPP IP NCP: Internet Protocol Network Control Protocol header file.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* portions Copyright (c) 1997 Global Election Systems Inc.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY
-*
-* 03-01-01 Marc Boucher 
-*   Ported to lwIP.
-* 97-12-04 Guy Lancaster , Global Election Systems Inc.
-*	Original derived from BSD codes.
-*****************************************************************************/
-/*
- * ipcp.h - IP Control Protocol definitions.
- *
- * Copyright (c) 1989 Carnegie Mellon University.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by Carnegie Mellon University.  The name of the
- * University may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- *
- * $Id: ipcp.h,v 1.2 2006/08/29 18:53:47 wolti Exp $
- */
-
-#ifndef IPCP_H
-#define IPCP_H
-
-/*************************
-*** PUBLIC DEFINITIONS ***
-*************************/
-/*
- * Options.
- */
-#define CI_ADDRS	1			/* IP Addresses */
-#define CI_COMPRESSTYPE	2		/* Compression Type */
-#define	CI_ADDR		3
-
-#define CI_MS_WINS1	128			/* Primary WINS value */
-#define CI_MS_DNS1	129			/* Primary DNS value */
-#define CI_MS_WINS2	130			/* Secondary WINS value */
-#define CI_MS_DNS2	131			/* Secondary DNS value */
-
-#define IPCP_VJMODE_OLD 1		/* "old" mode (option # = 0x0037) */
-#define IPCP_VJMODE_RFC1172 2	/* "old-rfc"mode (option # = 0x002d) */
-#define IPCP_VJMODE_RFC1332 3	/* "new-rfc"mode (option # = 0x002d, */
-                                /*  maxslot and slot number compression) */
-
-#define IPCP_VJ_COMP 0x002d		/* current value for VJ compression option*/
-#define IPCP_VJ_COMP_OLD 0x0037	/* "old" (i.e, broken) value for VJ */
-								/* compression option*/ 
-
-
-/************************
-*** PUBLIC DATA TYPES ***
-************************/
-
-typedef struct ipcp_options {
-    u_int neg_addr : 1;			/* Negotiate IP Address? */
-    u_int old_addrs : 1;			/* Use old (IP-Addresses) option? */
-    u_int req_addr : 1;			/* Ask peer to send IP address? */
-    u_int default_route : 1;		/* Assign default route through interface? */
-    u_int proxy_arp : 1;			/* Make proxy ARP entry for peer? */
-    u_int neg_vj : 1;				/* Van Jacobson Compression? */
-    u_int old_vj : 1;				/* use old (short) form of VJ option? */
-    u_int accept_local : 1;		/* accept peer's value for ouraddr */
-    u_int accept_remote : 1;		/* accept peer's value for hisaddr */
-    u_int req_dns1 : 1;			/* Ask peer to send primary DNS address? */
-    u_int req_dns2 : 1;			/* Ask peer to send secondary DNS address? */
-    u_short vj_protocol;		/* protocol value to use in VJ option */
-    u_char maxslotindex;		/* VJ slots - 1. */
-    u_char cflag;				/* VJ slot compression flag. */
-    u32_t ouraddr, hisaddr;	/* Addresses in NETWORK BYTE ORDER */
-    u32_t dnsaddr[2];		/* Primary and secondary MS DNS entries */
-    u32_t winsaddr[2];		/* Primary and secondary MS WINS entries */
-} ipcp_options;
-
-
-/*****************************
-*** PUBLIC DATA STRUCTURES ***
-*****************************/
-
-extern fsm ipcp_fsm[];
-extern ipcp_options ipcp_wantoptions[];
-extern ipcp_options ipcp_gotoptions[];
-extern ipcp_options ipcp_allowoptions[];
-extern ipcp_options ipcp_hisoptions[];
-
-extern struct protent ipcp_protent;
-
-
-/***********************
-*** PUBLIC FUNCTIONS ***
-***********************/
-
-
-#endif /* IPCP_H */
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/lcp.c b/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/lcp.c
deleted file mode 100644
index 6a988d6df..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/lcp.c
+++ /dev/null
@@ -1,1991 +0,0 @@
-/*****************************************************************************
-* lcp.c - Network Link Control Protocol program file.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* portions Copyright (c) 1997 by Global Election Systems Inc.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY
-*
-* 03-01-01 Marc Boucher 
-*   Ported to lwIP.
-* 97-12-01 Guy Lancaster , Global Election Systems Inc.
-*	Original.
-*****************************************************************************/
-
-/*
- * lcp.c - PPP Link Control Protocol.
- *
- * Copyright (c) 1989 Carnegie Mellon University.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by Carnegie Mellon University.  The name of the
- * University may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- */
- 
-#include 
- 
-#include "ppp.h"
-#if PPP_SUPPORT > 0
-#include "fsm.h"
-#include "chap.h"
-#include "magic.h"
-#include "auth.h"
-#include "lcp.h"
-#include "pppdebug.h"
-
-
-/*************************/
-/*** LOCAL DEFINITIONS ***/
-/*************************/
-/*
- * Length of each type of configuration option (in octets)
- */
-#define CILEN_VOID	2
-#define CILEN_CHAR	3
-#define CILEN_SHORT	4	/* CILEN_VOID + sizeof(short) */
-#define CILEN_CHAP	5	/* CILEN_VOID + sizeof(short) + 1 */
-#define CILEN_LONG	6	/* CILEN_VOID + sizeof(long) */
-#define CILEN_LQR	8	/* CILEN_VOID + sizeof(short) + sizeof(long) */
-#define CILEN_CBCP	3
-
-
-/***********************************/
-/*** LOCAL FUNCTION DECLARATIONS ***/
-/***********************************/
-/*
- * Callbacks for fsm code.  (CI = Configuration Information)
- */
-static void lcp_resetci (fsm*);	        /* Reset our CI */
-static int  lcp_cilen (fsm*);		        /* Return length of our CI */
-static void lcp_addci (fsm*, u_char*, int*);       /* Add our CI to pkt */
-static int  lcp_ackci (fsm*, u_char*, int);/* Peer ack'd our CI */
-static int  lcp_nakci (fsm*, u_char*, int);/* Peer nak'd our CI */
-static int  lcp_rejci (fsm*, u_char*, int);/* Peer rej'd our CI */
-static int  lcp_reqci (fsm*, u_char*, int*, int);  /* Rcv peer CI */
-static void lcp_up (fsm*);		            /* We're UP */
-static void lcp_down (fsm*);	    	    /* We're DOWN */
-static void lcp_starting (fsm*);   	    /* We need lower layer up */
-static void lcp_finished (fsm*);	        /* We need lower layer down */
-static int  lcp_extcode (fsm*, int, u_char, u_char*, int);
-
-static void lcp_rprotrej (fsm*, u_char*, int);
-
-/*
- * routines to send LCP echos to peer
- */
-static void lcp_echo_lowerup (int);
-static void lcp_echo_lowerdown (int);
-static void LcpEchoTimeout (void*);
-static void lcp_received_echo_reply (fsm*, int, u_char*, int);
-static void LcpSendEchoRequest (fsm*);
-static void LcpLinkFailure (fsm*);
-static void LcpEchoCheck (fsm*);
-
-/*
- * Protocol entry points.
- * Some of these are called directly.
- */
-static void lcp_input (int, u_char *, int);
-static void lcp_protrej (int);
-
-#define CODENAME(x)	((x) == CONFACK ? "ACK" : \
-			 (x) == CONFNAK ? "NAK" : "REJ")
-
-
-/******************************/
-/*** PUBLIC DATA STRUCTURES ***/
-/******************************/
-/* global vars */
-LinkPhase lcp_phase[NUM_PPP];			/* Phase of link session (RFC 1661) */
-lcp_options lcp_wantoptions[NUM_PPP];	/* Options that we want to request */
-lcp_options lcp_gotoptions[NUM_PPP];	/* Options that peer ack'd */
-lcp_options lcp_allowoptions[NUM_PPP];	/* Options we allow peer to request */
-lcp_options lcp_hisoptions[NUM_PPP];	/* Options that we ack'd */
-ext_accm xmit_accm[NUM_PPP];			/* extended transmit ACCM */
-
-
-
-/*****************************/
-/*** LOCAL DATA STRUCTURES ***/
-/*****************************/
-static fsm lcp_fsm[NUM_PPP];			/* LCP fsm structure (global)*/
-static u_int	 lcp_echo_interval = LCP_ECHOINTERVAL; /* Interval between LCP echo-requests */
-static u_int	 lcp_echo_fails = LCP_MAXECHOFAILS; /* Tolerance to unanswered echo-requests */
-static u32_t lcp_echos_pending = 0;	/* Number of outstanding echo msgs */
-static u32_t lcp_echo_number   = 0;	/* ID number of next echo frame */
-static u32_t lcp_echo_timer_running = 0;  /* TRUE if a timer is running */
-
-static u_char nak_buffer[PPP_MRU];	/* where we construct a nak packet */
-
-static fsm_callbacks lcp_callbacks = {	/* LCP callback routines */
-    lcp_resetci,		/* Reset our Configuration Information */
-    lcp_cilen,			/* Length of our Configuration Information */
-    lcp_addci,			/* Add our Configuration Information */
-    lcp_ackci,			/* ACK our Configuration Information */
-    lcp_nakci,			/* NAK our Configuration Information */
-    lcp_rejci,			/* Reject our Configuration Information */
-    lcp_reqci,			/* Request peer's Configuration Information */
-    lcp_up,				/* Called when fsm reaches OPENED state */
-    lcp_down,			/* Called when fsm leaves OPENED state */
-    lcp_starting,		/* Called when we want the lower layer up */
-    lcp_finished,		/* Called when we want the lower layer down */
-    NULL,				/* Called when Protocol-Reject received */
-    NULL,				/* Retransmission is necessary */
-    lcp_extcode,		/* Called to handle LCP-specific codes */
-    "LCP"				/* String name of protocol */
-};
-
-struct protent lcp_protent = {
-    PPP_LCP,
-    lcp_init,
-    lcp_input,
-    lcp_protrej,
-    lcp_lowerup,
-    lcp_lowerdown,
-    lcp_open,
-    lcp_close,
-#if 0
-    lcp_printpkt,
-    NULL,
-#endif
-    1,
-    "LCP",
-#if 0
-    NULL,
-    NULL,
-    NULL
-#endif
-};
-
-int lcp_loopbackfail = DEFLOOPBACKFAIL;
-
-
-
-/***********************************/
-/*** PUBLIC FUNCTION DEFINITIONS ***/
-/***********************************/
-/*
- * lcp_init - Initialize LCP.
- */
-void lcp_init(int unit)
-{
-	fsm *f = &lcp_fsm[unit];
-	lcp_options *wo = &lcp_wantoptions[unit];
-	lcp_options *ao = &lcp_allowoptions[unit];
-	
-	f->unit = unit;
-	f->protocol = PPP_LCP;
-	f->callbacks = &lcp_callbacks;
-	
-	fsm_init(f);
-	
-	wo->passive = 0;
-	wo->silent = 0;
-	wo->restart = 0;			/* Set to 1 in kernels or multi-line
-								 * implementations */
-	wo->neg_mru = 1;
-	wo->mru = PPP_DEFMRU;
-	wo->neg_asyncmap = 1;
-	wo->asyncmap = 0x00000000l;	/* Assume don't need to escape any ctl chars. */
-	wo->neg_chap = 0;			/* Set to 1 on server */
-	wo->neg_upap = 0;			/* Set to 1 on server */
-	wo->chap_mdtype = CHAP_DIGEST_MD5;
-	wo->neg_magicnumber = 1;
-	wo->neg_pcompression = 1;
-	wo->neg_accompression = 1;
-	wo->neg_lqr = 0;			/* no LQR implementation yet */
-	wo->neg_cbcp = 0;
-	
-	ao->neg_mru = 1;
-	ao->mru = PPP_MAXMRU;
-	ao->neg_asyncmap = 1;
-	ao->asyncmap = 0x00000000l;	/* Assume don't need to escape any ctl chars. */
-	ao->neg_chap = (CHAP_SUPPORT != 0);
-	ao->chap_mdtype = CHAP_DIGEST_MD5;
-	ao->neg_upap = (PAP_SUPPORT != 0);
-	ao->neg_magicnumber = 1;
-	ao->neg_pcompression = 1;
-	ao->neg_accompression = 1;
-	ao->neg_lqr = 0;			/* no LQR implementation yet */
-	ao->neg_cbcp = (CBCP_SUPPORT != 0);
-
-	/* 
-	 * Set transmit escape for the flag and escape characters plus anything
-	 * set for the allowable options.
-	 */
-	memset(xmit_accm[unit], 0, sizeof(xmit_accm[0]));
-	xmit_accm[unit][15] = 0x60;
-	xmit_accm[unit][0] = (u_char)(ao->asyncmap & 0xFF);
-	xmit_accm[unit][1] = (u_char)((ao->asyncmap >> 8) & 0xFF);
-	xmit_accm[unit][2] = (u_char)((ao->asyncmap >> 16) & 0xFF);
-	xmit_accm[unit][3] = (u_char)((ao->asyncmap >> 24) & 0xFF);
-	LCPDEBUG((LOG_INFO, "lcp_init: xmit_accm=%X %X %X %X\n",
-				xmit_accm[unit][0],
-				xmit_accm[unit][1],
-				xmit_accm[unit][2],
-				xmit_accm[unit][3]));
-	
-	lcp_phase[unit] = PHASE_INITIALIZE;
-}
-
-
-/*
- * lcp_open - LCP is allowed to come up.
- */
-void lcp_open(int unit)
-{
-	fsm *f = &lcp_fsm[unit];
-	lcp_options *wo = &lcp_wantoptions[unit];
-	
-	f->flags = 0;
-	if (wo->passive)
-		f->flags |= OPT_PASSIVE;
-	if (wo->silent)
-		f->flags |= OPT_SILENT;
-	fsm_open(f);
-	
-	lcp_phase[unit] = PHASE_ESTABLISH; 
-}
-
-
-/*
- * lcp_close - Take LCP down.
- */
-void lcp_close(int unit, char *reason)
-{
-	fsm *f = &lcp_fsm[unit];
-	
-	if (lcp_phase[unit] != PHASE_DEAD)
-		lcp_phase[unit] = PHASE_TERMINATE;
-	if (f->state == STOPPED && f->flags & (OPT_PASSIVE|OPT_SILENT)) {
-		/*
-		 * This action is not strictly according to the FSM in RFC1548,
-		 * but it does mean that the program terminates if you do an
-		 * lcp_close() in passive/silent mode when a connection hasn't
-		 * been established.
-		 */
-		f->state = CLOSED;
-		lcp_finished(f);
-	}
-	else
-		fsm_close(&lcp_fsm[unit], reason);
-}
-
-
-/*
- * lcp_lowerup - The lower layer is up.
- */
-void lcp_lowerup(int unit)
-{
-	lcp_options *wo = &lcp_wantoptions[unit];
-	
-	/*
-	* Don't use A/C or protocol compression on transmission,
-	* but accept A/C and protocol compressed packets
-	* if we are going to ask for A/C and protocol compression.
-	*/
-	ppp_set_xaccm(unit, &xmit_accm[unit]);
-	ppp_send_config(unit, PPP_MRU, 0xffffffffl, 0, 0);
-	ppp_recv_config(unit, PPP_MRU, 0x00000000l,
-					wo->neg_pcompression, wo->neg_accompression);
-	peer_mru[unit] = PPP_MRU;
-	lcp_allowoptions[unit].asyncmap 
-		= (u_long)xmit_accm[unit][0]
-			| ((u_long)xmit_accm[unit][1] << 8)
-			| ((u_long)xmit_accm[unit][2] << 16)
-			| ((u_long)xmit_accm[unit][3] << 24);
-	LCPDEBUG((LOG_INFO, "lcp_lowerup: asyncmap=%X %X %X %X\n",
-				xmit_accm[unit][3],
-				xmit_accm[unit][2],
-				xmit_accm[unit][1],
-				xmit_accm[unit][0]));
-	
-	fsm_lowerup(&lcp_fsm[unit]);
-}
-
-
-/*
- * lcp_lowerdown - The lower layer is down.
- */
-void lcp_lowerdown(int unit)
-{
-	fsm_lowerdown(&lcp_fsm[unit]);
-}
-
-/*
- * lcp_sprotrej - Send a Protocol-Reject for some protocol.
- */
-void lcp_sprotrej(int unit, u_char *p, int len)
-{
-	/*
-	* Send back the protocol and the information field of the
-	* rejected packet.  We only get here if LCP is in the OPENED state.
-	*/
-
-	fsm_sdata(&lcp_fsm[unit], PROTREJ, ++lcp_fsm[unit].id,
-				p, len);
-}
-
-
-
-/**********************************/
-/*** LOCAL FUNCTION DEFINITIONS ***/
-/**********************************/
-/*
- * lcp_input - Input LCP packet.
- */
-static void lcp_input(int unit, u_char *p, int len)
-{
-	fsm *f = &lcp_fsm[unit];
-	
-	fsm_input(f, p, len);
-}
-
-
-/*
- * lcp_extcode - Handle a LCP-specific code.
- */
-static int lcp_extcode(fsm *f, int code, u_char id, u_char *inp, int len)
-{
-	u_char *magp;
-	
-	switch( code ){
-	case PROTREJ:
-		lcp_rprotrej(f, inp, len);
-		break;
-	
-	case ECHOREQ:
-		if (f->state != OPENED)
-			break;
-		LCPDEBUG((LOG_INFO, "lcp: Echo-Request, Rcvd id %d\n", id));
-		magp = inp;
-		PUTLONG(lcp_gotoptions[f->unit].magicnumber, magp);
-		fsm_sdata(f, ECHOREP, id, inp, len);
-		break;
-	
-	case ECHOREP:
-		lcp_received_echo_reply(f, id, inp, len);
-		break;
-	
-	case DISCREQ:
-		break;
-	
-	default:
-		return 0;
-	}
-	return 1;
-}
-
-    
-/*
- * lcp_rprotrej - Receive an Protocol-Reject.
- *
- * Figure out which protocol is rejected and inform it.
- */
-static void lcp_rprotrej(fsm *f, u_char *inp, int len)
-{
-	int i;
-	struct protent *protp;
-	u_short prot;
-	
-	if (len < sizeof (u_short)) {
-		LCPDEBUG((LOG_INFO,
-				"lcp_rprotrej: Rcvd short Protocol-Reject packet!\n"));
-		return;
-	}
-	
-	GETSHORT(prot, inp);
-	
-	LCPDEBUG((LOG_INFO,
-			"lcp_rprotrej: Rcvd Protocol-Reject packet for %x!\n",
-			prot));
-	
-	/*
-	* Protocol-Reject packets received in any state other than the LCP
-	* OPENED state SHOULD be silently discarded.
-	*/
-	if( f->state != OPENED ){
-		LCPDEBUG((LOG_INFO, "Protocol-Reject discarded: LCP in state %d\n",
-				f->state));
-		return;
-	}
-	
-	/*
-	* Upcall the proper Protocol-Reject routine.
-	*/
-	for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i)
-		if (protp->protocol == prot && protp->enabled_flag) {
-			(*protp->protrej)(f->unit);
-			return;
-		}
-	
-	LCPDEBUG((LOG_WARNING, "Protocol-Reject for unsupported protocol 0x%x\n",
-			prot));
-}
-
-
-/*
- * lcp_protrej - A Protocol-Reject was received.
- */
-static void lcp_protrej(int unit)
-{
-	(void)unit;
-	/*
-	* Can't reject LCP!
-	*/
-	LCPDEBUG((LOG_WARNING,
-			"lcp_protrej: Received Protocol-Reject for LCP!\n"));
-	fsm_protreject(&lcp_fsm[unit]);
-}
-
-
-/*
- * lcp_resetci - Reset our CI.
- */
-static void lcp_resetci(fsm *f)
-{
-	lcp_wantoptions[f->unit].magicnumber = magic();
-	lcp_wantoptions[f->unit].numloops = 0;
-	lcp_gotoptions[f->unit] = lcp_wantoptions[f->unit];
-	peer_mru[f->unit] = PPP_MRU;
-	auth_reset(f->unit);
-}
-
-
-/*
- * lcp_cilen - Return length of our CI.
- */
-static int lcp_cilen(fsm *f)
-{
-	lcp_options *go = &lcp_gotoptions[f->unit];
-
-#define LENCIVOID(neg)	((neg) ? CILEN_VOID : 0)
-#define LENCICHAP(neg)	((neg) ? CILEN_CHAP : 0)
-#define LENCISHORT(neg)	((neg) ? CILEN_SHORT : 0)
-#define LENCILONG(neg)	((neg) ? CILEN_LONG : 0)
-#define LENCILQR(neg)	((neg) ? CILEN_LQR: 0)
-#define LENCICBCP(neg)	((neg) ? CILEN_CBCP: 0)
-	/*
-	* NB: we only ask for one of CHAP and UPAP, even if we will
-	* accept either.
-	*/
-	return (LENCISHORT(go->neg_mru && go->mru != PPP_DEFMRU) +
-		LENCILONG(go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl) +
-		LENCICHAP(go->neg_chap) +
-		LENCISHORT(!go->neg_chap && go->neg_upap) +
-		LENCILQR(go->neg_lqr) +
-		LENCICBCP(go->neg_cbcp) +
-		LENCILONG(go->neg_magicnumber) +
-		LENCIVOID(go->neg_pcompression) +
-		LENCIVOID(go->neg_accompression));
-}
-
-
-/*
- * lcp_addci - Add our desired CIs to a packet.
- */
-static void lcp_addci(fsm *f, u_char *ucp, int *lenp)
-{
-	lcp_options *go = &lcp_gotoptions[f->unit];
-	u_char *start_ucp = ucp;
-	
-#define ADDCIVOID(opt, neg) \
-	if (neg) { \
-	    LCPDEBUG((LOG_INFO, "lcp_addci: opt=%d\n", opt)); \
-		PUTCHAR(opt, ucp); \
-		PUTCHAR(CILEN_VOID, ucp); \
-	}
-#define ADDCISHORT(opt, neg, val) \
-	if (neg) { \
-	    LCPDEBUG((LOG_INFO, "lcp_addci: INT opt=%d %X\n", opt, val)); \
-		PUTCHAR(opt, ucp); \
-		PUTCHAR(CILEN_SHORT, ucp); \
-		PUTSHORT(val, ucp); \
-	}
-#define ADDCICHAP(opt, neg, val, digest) \
-	if (neg) { \
-	    LCPDEBUG((LOG_INFO, "lcp_addci: CHAP opt=%d %X\n", opt, val)); \
-		PUTCHAR(opt, ucp); \
-		PUTCHAR(CILEN_CHAP, ucp); \
-		PUTSHORT(val, ucp); \
-		PUTCHAR(digest, ucp); \
-	}
-#define ADDCILONG(opt, neg, val) \
-	if (neg) { \
-	    LCPDEBUG((LOG_INFO, "lcp_addci: L opt=%d %lX\n", opt, val)); \
-		PUTCHAR(opt, ucp); \
-		PUTCHAR(CILEN_LONG, ucp); \
-		PUTLONG(val, ucp); \
-	}
-#define ADDCILQR(opt, neg, val) \
-	if (neg) { \
-	    LCPDEBUG((LOG_INFO, "lcp_addci: LQR opt=%d %lX\n", opt, val)); \
-		PUTCHAR(opt, ucp); \
-		PUTCHAR(CILEN_LQR, ucp); \
-		PUTSHORT(PPP_LQR, ucp); \
-		PUTLONG(val, ucp); \
-	}
-#define ADDCICHAR(opt, neg, val) \
-	if (neg) { \
-	    LCPDEBUG((LOG_INFO, "lcp_addci: CHAR opt=%d %X '%z'\n", opt, val, val)); \
-		PUTCHAR(opt, ucp); \
-		PUTCHAR(CILEN_CHAR, ucp); \
-		PUTCHAR(val, ucp); \
-	}
-	
-	ADDCISHORT(CI_MRU, go->neg_mru && go->mru != PPP_DEFMRU, go->mru);
-	ADDCILONG(CI_ASYNCMAP, go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl,
-			go->asyncmap);
-	ADDCICHAP(CI_AUTHTYPE, go->neg_chap, PPP_CHAP, go->chap_mdtype);
-	ADDCISHORT(CI_AUTHTYPE, !go->neg_chap && go->neg_upap, PPP_PAP);
-	ADDCILQR(CI_QUALITY, go->neg_lqr, go->lqr_period);
-	ADDCICHAR(CI_CALLBACK, go->neg_cbcp, CBCP_OPT);
-	ADDCILONG(CI_MAGICNUMBER, go->neg_magicnumber, go->magicnumber);
-	ADDCIVOID(CI_PCOMPRESSION, go->neg_pcompression);
-	ADDCIVOID(CI_ACCOMPRESSION, go->neg_accompression);
-	
-	if (ucp - start_ucp != *lenp) {
-		/* this should never happen, because peer_mtu should be 1500 */
-		LCPDEBUG((LOG_ERR, "Bug in lcp_addci: wrong length\n"));
-	}
-}
-
-
-/*
- * lcp_ackci - Ack our CIs.
- * This should not modify any state if the Ack is bad.
- *
- * Returns:
- *	0 - Ack was bad.
- *	1 - Ack was good.
- */
-static int lcp_ackci(fsm *f, u_char *p, int len)
-{
-	lcp_options *go = &lcp_gotoptions[f->unit];
-	u_char cilen, citype, cichar;
-	u_short cishort;
-	u32_t cilong;
-	
-	/*
-	* CIs must be in exactly the same order that we sent.
-	* Check packet length and CI length at each step.
-	* If we find any deviations, then this packet is bad.
-	*/
-#define ACKCIVOID(opt, neg) \
-	if (neg) { \
-		if ((len -= CILEN_VOID) < 0) \
-			goto bad; \
-		GETCHAR(citype, p); \
-		GETCHAR(cilen, p); \
-		if (cilen != CILEN_VOID || \
-				citype != opt) \
-			goto bad; \
-	}
-#define ACKCISHORT(opt, neg, val) \
-	if (neg) { \
-		if ((len -= CILEN_SHORT) < 0) \
-			goto bad; \
-		GETCHAR(citype, p); \
-		GETCHAR(cilen, p); \
-		if (cilen != CILEN_SHORT || \
-				citype != opt) \
-			goto bad; \
-		GETSHORT(cishort, p); \
-		if (cishort != val) \
-			goto bad; \
-	}
-#define ACKCICHAR(opt, neg, val) \
-	if (neg) { \
-		if ((len -= CILEN_CHAR) < 0) \
-			goto bad; \
-		GETCHAR(citype, p); \
-		GETCHAR(cilen, p); \
-		if (cilen != CILEN_CHAR || \
-				citype != opt) \
-			goto bad; \
-		GETCHAR(cichar, p); \
-		if (cichar != val) \
-			goto bad; \
-	}
-#define ACKCICHAP(opt, neg, val, digest) \
-	if (neg) { \
-		if ((len -= CILEN_CHAP) < 0) \
-			goto bad; \
-		GETCHAR(citype, p); \
-		GETCHAR(cilen, p); \
-		if (cilen != CILEN_CHAP || \
-				citype != opt) \
-			goto bad; \
-		GETSHORT(cishort, p); \
-		if (cishort != val) \
-			goto bad; \
-		GETCHAR(cichar, p); \
-		if (cichar != digest) \
-			goto bad; \
-	}
-#define ACKCILONG(opt, neg, val) \
-	if (neg) { \
-		if ((len -= CILEN_LONG) < 0) \
-			goto bad; \
-		GETCHAR(citype, p); \
-		GETCHAR(cilen, p); \
-		if (cilen != CILEN_LONG || \
-				citype != opt) \
-			goto bad; \
-		GETLONG(cilong, p); \
-		if (cilong != val) \
-			goto bad; \
-	}
-#define ACKCILQR(opt, neg, val) \
-	if (neg) { \
-		if ((len -= CILEN_LQR) < 0) \
-			goto bad; \
-		GETCHAR(citype, p); \
-		GETCHAR(cilen, p); \
-		if (cilen != CILEN_LQR || \
-				citype != opt) \
-			goto bad; \
-		GETSHORT(cishort, p); \
-		if (cishort != PPP_LQR) \
-			goto bad; \
-		GETLONG(cilong, p); \
-		if (cilong != val) \
-			goto bad; \
-	}
-	
-	ACKCISHORT(CI_MRU, go->neg_mru && go->mru != PPP_DEFMRU, go->mru);
-	ACKCILONG(CI_ASYNCMAP, go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl,
-			go->asyncmap);
-	ACKCICHAP(CI_AUTHTYPE, go->neg_chap, PPP_CHAP, go->chap_mdtype);
-	ACKCISHORT(CI_AUTHTYPE, !go->neg_chap && go->neg_upap, PPP_PAP);
-	ACKCILQR(CI_QUALITY, go->neg_lqr, go->lqr_period);
-	ACKCICHAR(CI_CALLBACK, go->neg_cbcp, CBCP_OPT);
-	ACKCILONG(CI_MAGICNUMBER, go->neg_magicnumber, go->magicnumber);
-	ACKCIVOID(CI_PCOMPRESSION, go->neg_pcompression);
-	ACKCIVOID(CI_ACCOMPRESSION, go->neg_accompression);
-	
-	/*
-	 * If there are any remaining CIs, then this packet is bad.
-	 */
-	if (len != 0)
-		goto bad;
-	LCPDEBUG((LOG_INFO, "lcp_acki: Ack\n"));
-	return (1);
-bad:
-	LCPDEBUG((LOG_WARNING, "lcp_acki: received bad Ack!\n"));
-	return (0);
-}
-
-
-/*
- * lcp_nakci - Peer has sent a NAK for some of our CIs.
- * This should not modify any state if the Nak is bad
- * or if LCP is in the OPENED state.
- *
- * Returns:
- *	0 - Nak was bad.
- *	1 - Nak was good.
- */
-static int lcp_nakci(fsm *f, u_char *p, int len)
-{
-	lcp_options *go = &lcp_gotoptions[f->unit];
-	lcp_options *wo = &lcp_wantoptions[f->unit];
-	u_char citype, cichar, *next;
-	u_short cishort;
-	u32_t cilong;
-	lcp_options no;		/* options we've seen Naks for */
-	lcp_options try;		/* options to request next time */
-	int looped_back = 0;
-	int cilen;
-	
-	BZERO(&no, sizeof(no));
-	try = *go;
-	
-	/*
-	* Any Nak'd CIs must be in exactly the same order that we sent.
-	* Check packet length and CI length at each step.
-	* If we find any deviations, then this packet is bad.
-	*/
-#define NAKCIVOID(opt, neg, code) \
-	if (go->neg && \
-			len >= CILEN_VOID && \
-			p[1] == CILEN_VOID && \
-			p[0] == opt) { \
-		len -= CILEN_VOID; \
-		INCPTR(CILEN_VOID, p); \
-		no.neg = 1; \
-		code \
-	}
-#define NAKCICHAP(opt, neg, code) \
-	if (go->neg && \
-			len >= CILEN_CHAP && \
-			p[1] == CILEN_CHAP && \
-			p[0] == opt) { \
-		len -= CILEN_CHAP; \
-		INCPTR(2, p); \
-		GETSHORT(cishort, p); \
-		GETCHAR(cichar, p); \
-		no.neg = 1; \
-		code \
-	}
-#define NAKCICHAR(opt, neg, code) \
-	if (go->neg && \
-			len >= CILEN_CHAR && \
-			p[1] == CILEN_CHAR && \
-			p[0] == opt) { \
-		len -= CILEN_CHAR; \
-		INCPTR(2, p); \
-		GETCHAR(cichar, p); \
-		no.neg = 1; \
-		code \
-	}
-#define NAKCISHORT(opt, neg, code) \
-	if (go->neg && \
-			len >= CILEN_SHORT && \
-			p[1] == CILEN_SHORT && \
-			p[0] == opt) { \
-		len -= CILEN_SHORT; \
-		INCPTR(2, p); \
-		GETSHORT(cishort, p); \
-		no.neg = 1; \
-		code \
-	}
-#define NAKCILONG(opt, neg, code) \
-	if (go->neg && \
-			len >= CILEN_LONG && \
-			p[1] == CILEN_LONG && \
-			p[0] == opt) { \
-		len -= CILEN_LONG; \
-		INCPTR(2, p); \
-		GETLONG(cilong, p); \
-		no.neg = 1; \
-		code \
-	}
-#define NAKCILQR(opt, neg, code) \
-	if (go->neg && \
-			len >= CILEN_LQR && \
-			p[1] == CILEN_LQR && \
-			p[0] == opt) { \
-		len -= CILEN_LQR; \
-		INCPTR(2, p); \
-		GETSHORT(cishort, p); \
-		GETLONG(cilong, p); \
-		no.neg = 1; \
-		code \
-	}
-	
-	/*
-	* We don't care if they want to send us smaller packets than
-	* we want.  Therefore, accept any MRU less than what we asked for,
-	* but then ignore the new value when setting the MRU in the kernel.
-	* If they send us a bigger MRU than what we asked, accept it, up to
-	* the limit of the default MRU we'd get if we didn't negotiate.
-	*/
-	if (go->neg_mru && go->mru != PPP_DEFMRU) {
-		NAKCISHORT(CI_MRU, neg_mru,
-			if (cishort <= wo->mru || cishort < PPP_DEFMRU)
-				try.mru = cishort;
-		);
-	}
-	
-	/*
-	* Add any characters they want to our (receive-side) asyncmap.
-	*/
-	if (go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl) {
-		NAKCILONG(CI_ASYNCMAP, neg_asyncmap,
-			try.asyncmap = go->asyncmap | cilong;
-		);
-	}
-	
-	/*
-	* If they've nak'd our authentication-protocol, check whether
-	* they are proposing a different protocol, or a different
-	* hash algorithm for CHAP.
-	*/
-	if ((go->neg_chap || go->neg_upap)
-			&& len >= CILEN_SHORT
-			&& p[0] == CI_AUTHTYPE && p[1] >= CILEN_SHORT && p[1] <= len) {
-		cilen = p[1];
-	len -= cilen;
-	no.neg_chap = go->neg_chap;
-	no.neg_upap = go->neg_upap;
-	INCPTR(2, p);
-	GETSHORT(cishort, p);
-	if (cishort == PPP_PAP && cilen == CILEN_SHORT) {
-		/*
-		 * If we were asking for CHAP, they obviously don't want to do it.
-		 * If we weren't asking for CHAP, then we were asking for PAP,
-		 * in which case this Nak is bad.
-		 */
-		if (!go->neg_chap)
-			goto bad;
-		try.neg_chap = 0;
-	
-	} else if (cishort == PPP_CHAP && cilen == CILEN_CHAP) {
-		GETCHAR(cichar, p);
-		if (go->neg_chap) {
-			/*
-			 * We were asking for CHAP/MD5; they must want a different
-			 * algorithm.  If they can't do MD5, we'll have to stop
-			 * asking for CHAP.
-			 */
-			if (cichar != go->chap_mdtype)
-				try.neg_chap = 0;
-		} else {
-			/*
-			 * Stop asking for PAP if we were asking for it.
-			 */
-			try.neg_upap = 0;
-		}
-	
-	} else {
-		/*
-		 * We don't recognize what they're suggesting.
-		 * Stop asking for what we were asking for.
-		 */
-		if (go->neg_chap)
-			try.neg_chap = 0;
-		else
-			try.neg_upap = 0;
-		p += cilen - CILEN_SHORT;
-	}
-	}
-	
-	/*
-	* If they can't cope with our link quality protocol, we'll have
-	* to stop asking for LQR.  We haven't got any other protocol.
-	* If they Nak the reporting period, take their value XXX ?
-	*/
-	NAKCILQR(CI_QUALITY, neg_lqr,
-		if (cishort != PPP_LQR)
-			try.neg_lqr = 0;
-		else
-			try.lqr_period = cilong;
-	);
-	
-	/*
-	* Only implementing CBCP...not the rest of the callback options
-	*/
-	NAKCICHAR(CI_CALLBACK, neg_cbcp,
-		try.neg_cbcp = 0;
-	);
-	
-	/*
-	* Check for a looped-back line.
-	*/
-	NAKCILONG(CI_MAGICNUMBER, neg_magicnumber,
-		try.magicnumber = magic();
-		looped_back = 1;
-	);
-	
-	/*
-	* Peer shouldn't send Nak for protocol compression or
-	* address/control compression requests; they should send
-	* a Reject instead.  If they send a Nak, treat it as a Reject.
-	*/
-	NAKCIVOID(CI_PCOMPRESSION, neg_pcompression,
-		try.neg_pcompression = 0;
-	);
-	NAKCIVOID(CI_ACCOMPRESSION, neg_accompression,
-		try.neg_accompression = 0;
-	);
-	
-	/*
-	* There may be remaining CIs, if the peer is requesting negotiation
-	* on an option that we didn't include in our request packet.
-	* If we see an option that we requested, or one we've already seen
-	* in this packet, then this packet is bad.
-	* If we wanted to respond by starting to negotiate on the requested
-	* option(s), we could, but we don't, because except for the
-	* authentication type and quality protocol, if we are not negotiating
-	* an option, it is because we were told not to.
-	* For the authentication type, the Nak from the peer means
-	* `let me authenticate myself with you' which is a bit pointless.
-	* For the quality protocol, the Nak means `ask me to send you quality
-	* reports', but if we didn't ask for them, we don't want them.
-	* An option we don't recognize represents the peer asking to
-	* negotiate some option we don't support, so ignore it.
-	*/
-	while (len > CILEN_VOID) {
-		GETCHAR(citype, p);
-		GETCHAR(cilen, p);
-		if (cilen < CILEN_VOID || (len -= cilen) < 0)
-			goto bad;
-		next = p + cilen - 2;
-		
-		switch (citype) {
-		case CI_MRU:
-			if ((go->neg_mru && go->mru != PPP_DEFMRU)
-					|| no.neg_mru || cilen != CILEN_SHORT)
-				goto bad;
-			GETSHORT(cishort, p);
-			if (cishort < PPP_DEFMRU)
-				try.mru = cishort;
-			break;
-		case CI_ASYNCMAP:
-			if ((go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl)
-					|| no.neg_asyncmap || cilen != CILEN_LONG)
-				goto bad;
-			break;
-		case CI_AUTHTYPE:
-			if (go->neg_chap || no.neg_chap || go->neg_upap || no.neg_upap)
-				goto bad;
-			break;
-		case CI_MAGICNUMBER:
-			if (go->neg_magicnumber || no.neg_magicnumber ||
-					cilen != CILEN_LONG)
-				goto bad;
-			break;
-		case CI_PCOMPRESSION:
-			if (go->neg_pcompression || no.neg_pcompression
-					|| cilen != CILEN_VOID)
-				goto bad;
-			break;
-		case CI_ACCOMPRESSION:
-			if (go->neg_accompression || no.neg_accompression
-					|| cilen != CILEN_VOID)
-				goto bad;
-			break;
-		case CI_QUALITY:
-			if (go->neg_lqr || no.neg_lqr || cilen != CILEN_LQR)
-				goto bad;
-			break;
-		}
-		p = next;
-	}
-	
-	/* If there is still anything left, this packet is bad. */
-	if (len != 0)
-		goto bad;
-	
-	/*
-	* OK, the Nak is good.  Now we can update state.
-	*/
-	if (f->state != OPENED) {
-		if (looped_back) {
-			if (++try.numloops >= lcp_loopbackfail) {
-				LCPDEBUG((LOG_NOTICE, "Serial line is looped back.\n"));
-				lcp_close(f->unit, "Loopback detected");
-			}
-		} 
-		else
-			try.numloops = 0;
-		*go = try;
-	}
-	
-	return 1;
-	
-bad:
-	LCPDEBUG((LOG_WARNING, "lcp_nakci: received bad Nak!\n"));
-	return 0;
-}
-
-
-/*
- * lcp_rejci - Peer has Rejected some of our CIs.
- * This should not modify any state if the Reject is bad
- * or if LCP is in the OPENED state.
- *
- * Returns:
- *	0 - Reject was bad.
- *	1 - Reject was good.
- */
-static int lcp_rejci(fsm *f, u_char *p, int len)
-{
-	lcp_options *go = &lcp_gotoptions[f->unit];
-	u_char cichar;
-	u_short cishort;
-	u32_t cilong;
-	lcp_options try;		/* options to request next time */
-	
-	try = *go;
-	
-	/*
-	* Any Rejected CIs must be in exactly the same order that we sent.
-	* Check packet length and CI length at each step.
-	* If we find any deviations, then this packet is bad.
-	*/
-#define REJCIVOID(opt, neg) \
-	if (go->neg && \
-			len >= CILEN_VOID && \
-			p[1] == CILEN_VOID && \
-			p[0] == opt) { \
-		len -= CILEN_VOID; \
-		INCPTR(CILEN_VOID, p); \
-		try.neg = 0; \
-		LCPDEBUG((LOG_INFO, "lcp_rejci: void opt %d rejected\n", opt)); \
-	}
-#define REJCISHORT(opt, neg, val) \
-	if (go->neg && \
-			len >= CILEN_SHORT && \
-			p[1] == CILEN_SHORT && \
-			p[0] == opt) { \
-		len -= CILEN_SHORT; \
-		INCPTR(2, p); \
-		GETSHORT(cishort, p); \
-		/* Check rejected value. */ \
-		if (cishort != val) \
-			goto bad; \
-		try.neg = 0; \
-		LCPDEBUG((LOG_INFO,"lcp_rejci: short opt %d rejected\n", opt)); \
-	}
-#define REJCICHAP(opt, neg, val, digest) \
-	if (go->neg && \
-			len >= CILEN_CHAP && \
-			p[1] == CILEN_CHAP && \
-			p[0] == opt) { \
-		len -= CILEN_CHAP; \
-		INCPTR(2, p); \
-		GETSHORT(cishort, p); \
-		GETCHAR(cichar, p); \
-		/* Check rejected value. */ \
-		if (cishort != val || cichar != digest) \
-			goto bad; \
-		try.neg = 0; \
-		try.neg_upap = 0; \
-		LCPDEBUG((LOG_INFO,"lcp_rejci: chap opt %d rejected\n", opt)); \
-	}
-#define REJCILONG(opt, neg, val) \
-	if (go->neg && \
-			len >= CILEN_LONG && \
-			p[1] == CILEN_LONG && \
-			p[0] == opt) { \
-		len -= CILEN_LONG; \
-		INCPTR(2, p); \
-		GETLONG(cilong, p); \
-		/* Check rejected value. */ \
-		if (cilong != val) \
-			goto bad; \
-		try.neg = 0; \
-		LCPDEBUG((LOG_INFO,"lcp_rejci: long opt %d rejected\n", opt)); \
-	}
-#define REJCILQR(opt, neg, val) \
-	if (go->neg && \
-			len >= CILEN_LQR && \
-			p[1] == CILEN_LQR && \
-			p[0] == opt) { \
-		len -= CILEN_LQR; \
-		INCPTR(2, p); \
-		GETSHORT(cishort, p); \
-		GETLONG(cilong, p); \
-		/* Check rejected value. */ \
-		if (cishort != PPP_LQR || cilong != val) \
-			goto bad; \
-		try.neg = 0; \
-		LCPDEBUG((LOG_INFO,"lcp_rejci: LQR opt %d rejected\n", opt)); \
-	}
-#define REJCICBCP(opt, neg, val) \
-	if (go->neg && \
-			len >= CILEN_CBCP && \
-			p[1] == CILEN_CBCP && \
-			p[0] == opt) { \
-		len -= CILEN_CBCP; \
-		INCPTR(2, p); \
-		GETCHAR(cichar, p); \
-		/* Check rejected value. */ \
-		if (cichar != val) \
-			goto bad; \
-		try.neg = 0; \
-		LCPDEBUG((LOG_INFO,"lcp_rejci: Callback opt %d rejected\n", opt)); \
-	}
-	
-	REJCISHORT(CI_MRU, neg_mru, go->mru);
-	REJCILONG(CI_ASYNCMAP, neg_asyncmap, go->asyncmap);
-	REJCICHAP(CI_AUTHTYPE, neg_chap, PPP_CHAP, go->chap_mdtype);
-	if (!go->neg_chap) {
-		REJCISHORT(CI_AUTHTYPE, neg_upap, PPP_PAP);
-	}
-	REJCILQR(CI_QUALITY, neg_lqr, go->lqr_period);
-	REJCICBCP(CI_CALLBACK, neg_cbcp, CBCP_OPT);
-	REJCILONG(CI_MAGICNUMBER, neg_magicnumber, go->magicnumber);
-	REJCIVOID(CI_PCOMPRESSION, neg_pcompression);
-	REJCIVOID(CI_ACCOMPRESSION, neg_accompression);
-	
-	/*
-	* If there are any remaining CIs, then this packet is bad.
-	*/
-	if (len != 0)
-		goto bad;
-	/*
-	* Now we can update state.
-	*/
-	if (f->state != OPENED)
-		*go = try;
-	return 1;
-	
-bad:
-	LCPDEBUG((LOG_WARNING, "lcp_rejci: received bad Reject!\n"));
-	return 0;
-}
-
-
-/*
- * lcp_reqci - Check the peer's requested CIs and send appropriate response.
- *
- * Returns: CONFACK, CONFNAK or CONFREJ and input packet modified
- * appropriately.  If reject_if_disagree is non-zero, doesn't return
- * CONFNAK; returns CONFREJ if it can't return CONFACK.
- */
-static int lcp_reqci(fsm *f, 
-						u_char *inp,		/* Requested CIs */
-						int *lenp,			/* Length of requested CIs */
-						int reject_if_disagree)
-{
-	lcp_options *go = &lcp_gotoptions[f->unit];
-	lcp_options *ho = &lcp_hisoptions[f->unit];
-	lcp_options *ao = &lcp_allowoptions[f->unit];
-	u_char *cip, *next;			/* Pointer to current and next CIs */
-	int cilen, citype, cichar;	/* Parsed len, type, char value */
-	u_short cishort;			/* Parsed short value */
-	u32_t cilong;			/* Parse long value */
-	int rc = CONFACK;			/* Final packet return code */
-	int orc;					/* Individual option return code */
-	u_char *p;					/* Pointer to next char to parse */
-	u_char *rejp;				/* Pointer to next char in reject frame */
-	u_char *nakp;				/* Pointer to next char in Nak frame */
-	int l = *lenp;				/* Length left */
-#if TRACELCP > 0
-	char traceBuf[80];
-	int traceNdx = 0;
-#endif
-	
-	/*
-	 * Reset all his options.
-	 */
-	BZERO(ho, sizeof(*ho));
-	
-	/*
-	 * Process all his options.
-	 */
-	next = inp;
-	nakp = nak_buffer;
-	rejp = inp;
-	while (l) {
-		orc = CONFACK;			/* Assume success */
-		cip = p = next;			/* Remember begining of CI */
-		if (l < 2 ||			/* Not enough data for CI header or */
-				p[1] < 2 ||			/*  CI length too small or */
-				p[1] > l) {			/*  CI length too big? */
-			LCPDEBUG((LOG_WARNING, "lcp_reqci: bad CI length!\n"));
-			orc = CONFREJ;		/* Reject bad CI */
-			cilen = l;			/* Reject till end of packet */
-			l = 0;			/* Don't loop again */
-			citype = 0;
-			goto endswitch;
-		}
-		GETCHAR(citype, p);		/* Parse CI type */
-		GETCHAR(cilen, p);		/* Parse CI length */
-		l -= cilen;			/* Adjust remaining length */
-		next += cilen;			/* Step to next CI */
-		
-		switch (citype) {		/* Check CI type */
-		case CI_MRU:
-			if (!ao->neg_mru) {		/* Allow option? */
-				LCPDEBUG((LOG_INFO, "lcp_reqci: Reject MRU - not allowed\n"));
-				orc = CONFREJ;		/* Reject CI */
-				break;
-			} else if (cilen != CILEN_SHORT) {	/* Check CI length */
-				LCPDEBUG((LOG_INFO, "lcp_reqci: Reject MRU - bad length\n"));
-				orc = CONFREJ;		/* Reject CI */
-				break;
-			}
-			GETSHORT(cishort, p);	/* Parse MRU */
-			
-			/*
-			 * He must be able to receive at least our minimum.
-			 * No need to check a maximum.  If he sends a large number,
-			 * we'll just ignore it.
-			 */
-			if (cishort < PPP_MINMRU) {
-				LCPDEBUG((LOG_INFO, "lcp_reqci: Nak - MRU too small\n"));
-				orc = CONFNAK;		/* Nak CI */
-				PUTCHAR(CI_MRU, nakp);
-				PUTCHAR(CILEN_SHORT, nakp);
-				PUTSHORT(PPP_MINMRU, nakp);	/* Give him a hint */
-				break;
-			}
-			ho->neg_mru = 1;		/* Remember he sent MRU */
-			ho->mru = cishort;		/* And remember value */
-#if TRACELCP > 0
-			snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " MRU %d", cishort);
-			traceNdx = strlen(traceBuf);
-#endif
-			break;
-		
-		case CI_ASYNCMAP:
-			if (!ao->neg_asyncmap) {
-				LCPDEBUG((LOG_INFO, "lcp_reqci: Reject ASYNCMAP not allowed\n"));
-				orc = CONFREJ;
-				break;
-			} else if (cilen != CILEN_LONG) {
-				LCPDEBUG((LOG_INFO, "lcp_reqci: Reject ASYNCMAP bad length\n"));
-				orc = CONFREJ;
-				break;
-			}
-			GETLONG(cilong, p);
-			
-			/*
-			 * Asyncmap must have set at least the bits
-			 * which are set in lcp_allowoptions[unit].asyncmap.
-			 */
-			if ((ao->asyncmap & ~cilong) != 0) {
-				LCPDEBUG((LOG_INFO, "lcp_reqci: Nak ASYNCMAP %lX missing %lX\n", 
-							cilong, ao->asyncmap));
-				orc = CONFNAK;
-				PUTCHAR(CI_ASYNCMAP, nakp);
-				PUTCHAR(CILEN_LONG, nakp);
-				PUTLONG(ao->asyncmap | cilong, nakp);
-				break;
-			}
-			ho->neg_asyncmap = 1;
-			ho->asyncmap = cilong;
-#if TRACELCP > 0
-			snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " ASYNCMAP=%lX", cilong);
-			traceNdx = strlen(traceBuf);
-#endif
-			break;
-		
-		case CI_AUTHTYPE:
-			if (cilen < CILEN_SHORT) {
-				LCPDEBUG((LOG_INFO, "lcp_reqci: Reject AUTHTYPE missing arg\n"));
-				orc = CONFREJ;
-				break;
-			} else if (!(ao->neg_upap || ao->neg_chap)) {
-				/*
-				 * Reject the option if we're not willing to authenticate.
-				 */
-				LCPDEBUG((LOG_INFO, "lcp_reqci: Reject AUTHTYPE not allowed\n"));
-				orc = CONFREJ;
-				break;
-			}
-			GETSHORT(cishort, p);
-			
-			/*
-			 * Authtype must be UPAP or CHAP.
-			 *
-			 * Note: if both ao->neg_upap and ao->neg_chap are set,
-			 * and the peer sends a Configure-Request with two
-			 * authenticate-protocol requests, one for CHAP and one
-			 * for UPAP, then we will reject the second request.
-			 * Whether we end up doing CHAP or UPAP depends then on
-			 * the ordering of the CIs in the peer's Configure-Request.
-			 */
-			
-			if (cishort == PPP_PAP) {
-				if (ho->neg_chap) {	/* we've already accepted CHAP */
-					LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE PAP already accepted\n"));
-					orc = CONFREJ;
-					break;
-				} else if (cilen != CILEN_SHORT) {
-					LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE PAP bad len\n"));
-					orc = CONFREJ;
-					break;
-				}
-				if (!ao->neg_upap) {	/* we don't want to do PAP */
-					LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE PAP not allowed\n"));
-					orc = CONFNAK;	/* NAK it and suggest CHAP */
-					PUTCHAR(CI_AUTHTYPE, nakp);
-					PUTCHAR(CILEN_CHAP, nakp);
-					PUTSHORT(PPP_CHAP, nakp);
-					PUTCHAR(ao->chap_mdtype, nakp);
-					break;
-				}
-				ho->neg_upap = 1;
-#if TRACELCP > 0
-				snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " PAP (%X)", cishort);
-				traceNdx = strlen(traceBuf);
-#endif
-				break;
-			}
-			if (cishort == PPP_CHAP) {
-				if (ho->neg_upap) {	/* we've already accepted PAP */
-					LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE CHAP accepted PAP\n"));
-					orc = CONFREJ;
-					break;
-				} else if (cilen != CILEN_CHAP) {
-					LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE CHAP bad len\n"));
-					orc = CONFREJ;
-					break;
-				}
-				if (!ao->neg_chap) {	/* we don't want to do CHAP */
-					LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE CHAP not allowed\n"));
-					orc = CONFNAK;	/* NAK it and suggest PAP */
-					PUTCHAR(CI_AUTHTYPE, nakp);
-					PUTCHAR(CILEN_SHORT, nakp);
-					PUTSHORT(PPP_PAP, nakp);
-					break;
-				}
-				GETCHAR(cichar, p);	/* get digest type*/
-				if (cichar != CHAP_DIGEST_MD5
-#ifdef CHAPMS
-						&& cichar != CHAP_MICROSOFT
-#endif
-				) {
-					LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE CHAP digest=%d\n", cichar));
-					orc = CONFNAK;
-					PUTCHAR(CI_AUTHTYPE, nakp);
-					PUTCHAR(CILEN_CHAP, nakp);
-					PUTSHORT(PPP_CHAP, nakp);
-					PUTCHAR(ao->chap_mdtype, nakp);
-					break;
-				}
-#if TRACELCP > 0
-				snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CHAP %X,%d", cishort, cichar);
-				traceNdx = strlen(traceBuf);
-#endif
-				ho->chap_mdtype = cichar; /* save md type */
-				ho->neg_chap = 1;
-				break;
-			}
-			
-			/*
-			 * We don't recognize the protocol they're asking for.
-			 * Nak it with something we're willing to do.
-			 * (At this point we know ao->neg_upap || ao->neg_chap.)
-			 */
-			orc = CONFNAK;
-			PUTCHAR(CI_AUTHTYPE, nakp);
-			if (ao->neg_chap) {
-				LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE %d req CHAP\n", cishort));
-				PUTCHAR(CILEN_CHAP, nakp);
-				PUTSHORT(PPP_CHAP, nakp);
-				PUTCHAR(ao->chap_mdtype, nakp);
-			} 
-			else {
-				LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE %d req PAP\n", cishort));
-				PUTCHAR(CILEN_SHORT, nakp);
-				PUTSHORT(PPP_PAP, nakp);
-			}
-			break;
-		
-		case CI_QUALITY:
-			GETSHORT(cishort, p);
-			GETLONG(cilong, p);
-#if TRACELCP > 0
-			snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " QUALITY (%x %x)", cishort, (unsigned int) cilong);
-			traceNdx = strlen(traceBuf);
-#endif
-
-			if (!ao->neg_lqr ||
-					cilen != CILEN_LQR) {
-				orc = CONFREJ;
-				break;
-			}
-			
-			/*
-			 * Check the protocol and the reporting period.
-			 * XXX When should we Nak this, and what with?
-			 */
-			if (cishort != PPP_LQR) {
-				orc = CONFNAK;
-				PUTCHAR(CI_QUALITY, nakp);
-				PUTCHAR(CILEN_LQR, nakp);
-				PUTSHORT(PPP_LQR, nakp);
-				PUTLONG(ao->lqr_period, nakp);
-				break;
-			}
-			break;
-		
-		case CI_MAGICNUMBER:
-			if (!(ao->neg_magicnumber || go->neg_magicnumber) ||
-					cilen != CILEN_LONG) {
-				orc = CONFREJ;
-				break;
-			}
-			GETLONG(cilong, p);
-#if TRACELCP > 0
-			snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " MAGICNUMBER (%lX)", cilong);
-			traceNdx = strlen(traceBuf);
-#endif
-
-			/*
-			 * He must have a different magic number.
-			 */
-			if (go->neg_magicnumber &&
-					cilong == go->magicnumber) {
-				cilong = magic();	/* Don't put magic() inside macro! */
-				orc = CONFNAK;
-				PUTCHAR(CI_MAGICNUMBER, nakp);
-				PUTCHAR(CILEN_LONG, nakp);
-				PUTLONG(cilong, nakp);
-				break;
-			}
-			ho->neg_magicnumber = 1;
-			ho->magicnumber = cilong;
-			break;
-		
-		
-		case CI_PCOMPRESSION:
-#if TRACELCP > 0
-			snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " PCOMPRESSION");
-			traceNdx = strlen(traceBuf);
-#endif
-			if (!ao->neg_pcompression ||
-					cilen != CILEN_VOID) {
-				orc = CONFREJ;
-				break;
-			}
-			ho->neg_pcompression = 1;
-			break;
-		
-		case CI_ACCOMPRESSION:
-#if TRACELCP > 0
-			snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " ACCOMPRESSION");
-			traceNdx = strlen(traceBuf);
-#endif
-			if (!ao->neg_accompression ||
-					cilen != CILEN_VOID) {
-				orc = CONFREJ;
-				break;
-			}
-			ho->neg_accompression = 1;
-			break;
-		
-		case CI_MRRU:
-#if TRACELCP > 0
-			snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CI_MRRU");
-			traceNdx = strlen(traceBuf);
-#endif
-			orc = CONFREJ;
-			break;
-		
-		case CI_SSNHF:
-#if TRACELCP > 0
-			snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CI_SSNHF");
-			traceNdx = strlen(traceBuf);
-#endif
-			orc = CONFREJ;
-			break;
-		
-		case CI_EPDISC:
-#if TRACELCP > 0
-			snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CI_EPDISC");
-			traceNdx = strlen(traceBuf);
-#endif
-			orc = CONFREJ;
-			break;
-		
-		default:
-#if TRACELCP
-			snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " unknown %d", citype);
-			traceNdx = strlen(traceBuf);
-#endif
-			orc = CONFREJ;
-			break;
-		}
-		
-	endswitch:
-#if TRACELCP
-		if (traceNdx >= 80 - 32) {
-			LCPDEBUG((LOG_INFO, "lcp_reqci: rcvd%s\n", traceBuf));
-			traceNdx = 0;
-		}
-#endif
-		if (orc == CONFACK &&		/* Good CI */
-				rc != CONFACK)		/*  but prior CI wasnt? */
-			continue;			/* Don't send this one */
-		
-		if (orc == CONFNAK) {		/* Nak this CI? */
-			if (reject_if_disagree	/* Getting fed up with sending NAKs? */
-					&& citype != CI_MAGICNUMBER) {
-				orc = CONFREJ;		/* Get tough if so */
-			} 
-			else {
-				if (rc == CONFREJ)	/* Rejecting prior CI? */
-					continue;		/* Don't send this one */
-				rc = CONFNAK;
-			}
-		}
-		if (orc == CONFREJ) {		/* Reject this CI */
-			rc = CONFREJ;
-			if (cip != rejp)		/* Need to move rejected CI? */
-				BCOPY(cip, rejp, cilen); /* Move it */
-			INCPTR(cilen, rejp);	/* Update output pointer */
-		}
-	}
-	
-	/*
-	 * If we wanted to send additional NAKs (for unsent CIs), the
-	 * code would go here.  The extra NAKs would go at *nakp.
-	 * At present there are no cases where we want to ask the
-	 * peer to negotiate an option.
-	 */
-	
-	switch (rc) {
-	case CONFACK:
-		*lenp = (int)(next - inp);
-		break;
-	case CONFNAK:
-		/*
-		 * Copy the Nak'd options from the nak_buffer to the caller's buffer.
-		 */
-		*lenp = (int)(nakp - nak_buffer);
-		BCOPY(nak_buffer, inp, *lenp);
-		break;
-	case CONFREJ:
-		*lenp = (int)(rejp - inp);
-		break;
-	}
-	
-#if TRACELCP > 0
-	if (traceNdx > 0) {
-		LCPDEBUG((LOG_INFO, "lcp_reqci: %s\n", traceBuf));
-	}
-#endif
-	LCPDEBUG((LOG_INFO, "lcp_reqci: returning CONF%s.\n", CODENAME(rc)));
-	return (rc);			/* Return final code */
-}
-
-
-/*
- * lcp_up - LCP has come UP.
- */
-static void lcp_up(fsm *f)
-{
-	lcp_options *wo = &lcp_wantoptions[f->unit];
-	lcp_options *ho = &lcp_hisoptions[f->unit];
-	lcp_options *go = &lcp_gotoptions[f->unit];
-	lcp_options *ao = &lcp_allowoptions[f->unit];
-	
-	if (!go->neg_magicnumber)
-		go->magicnumber = 0;
-	if (!ho->neg_magicnumber)
-		ho->magicnumber = 0;
-	
-	/*
-	* Set our MTU to the smaller of the MTU we wanted and
-	* the MRU our peer wanted.  If we negotiated an MRU,
-	* set our MRU to the larger of value we wanted and
-	* the value we got in the negotiation.
-	*/
-	ppp_send_config(f->unit, LWIP_MIN(ao->mru, (ho->neg_mru? ho->mru: PPP_MRU)),
-				(ho->neg_asyncmap? ho->asyncmap: 0xffffffffl),
-				ho->neg_pcompression, ho->neg_accompression);
-	/*
-	* If the asyncmap hasn't been negotiated, we really should
-	* set the receive asyncmap to ffffffff, but we set it to 0
-	* for backwards contemptibility.
-	*/
-	ppp_recv_config(f->unit, (go->neg_mru? LWIP_MAX(wo->mru, go->mru): PPP_MRU),
-				(go->neg_asyncmap? go->asyncmap: 0x00000000),
-				go->neg_pcompression, go->neg_accompression);
-	
-	if (ho->neg_mru)
-		peer_mru[f->unit] = ho->mru;
-	
-	lcp_echo_lowerup(f->unit);  /* Enable echo messages */
-	
-	link_established(f->unit);
-}
-
-
-/*
- * lcp_down - LCP has gone DOWN.
- *
- * Alert other protocols.
- */
-static void lcp_down(fsm *f)
-{
-	lcp_options *go = &lcp_gotoptions[f->unit];
-	
-	lcp_echo_lowerdown(f->unit);
-	
-	link_down(f->unit);
-	
-	ppp_send_config(f->unit, PPP_MRU, 0xffffffffl, 0, 0);
-	ppp_recv_config(f->unit, PPP_MRU,
-				(go->neg_asyncmap? go->asyncmap: 0x00000000),
-				go->neg_pcompression, go->neg_accompression);
-	peer_mru[f->unit] = PPP_MRU;
-}
-
-
-/*
- * lcp_starting - LCP needs the lower layer up.
- */
-static void lcp_starting(fsm *f)
-{
-	link_required(f->unit);
-}
-
-
-/*
- * lcp_finished - LCP has finished with the lower layer.
- */
-static void lcp_finished(fsm *f)
-{
-	link_terminated(f->unit);
-}
-
-
-#if 0
-/*
- * print_string - print a readable representation of a string using
- * printer.
- */
-static void print_string(
-    char *p,
-    int len,
-    void (*printer) (void *, char *, ...),
-    void *arg
-)
-{
-    int c;
-    
-    printer(arg, "\"");
-    for (; len > 0; --len) {
-        c = *p++;
-        if (' ' <= c && c <= '~') {
-            if (c == '\\' || c == '"')
-                printer(arg, "\\");
-            printer(arg, "%c", c);
-        } else {
-            switch (c) {
-            case '\n':
-                printer(arg, "\\n");
-                break;
-            case '\r':
-                printer(arg, "\\r");
-                break;
-            case '\t':
-                printer(arg, "\\t");
-                break;
-            default:
-                printer(arg, "\\%.3o", c);
-            }
-        }
-    }
-    printer(arg, "\"");
-}
-
-
-/*
- * lcp_printpkt - print the contents of an LCP packet.
- */
-static char *lcp_codenames[] = {
-	"ConfReq", "ConfAck", "ConfNak", "ConfRej",
-	"TermReq", "TermAck", "CodeRej", "ProtRej",
-	"EchoReq", "EchoRep", "DiscReq"
-};
-
-static int lcp_printpkt(
-	u_char *p,
-	int plen,
-	void (*printer) (void *, char *, ...),
-	void *arg
-)
-{
-	int code, id, len, olen;
-	u_char *pstart, *optend;
-	u_short cishort;
-	u32_t cilong;
-	
-	if (plen < HEADERLEN)
-		return 0;
-	pstart = p;
-	GETCHAR(code, p);
-	GETCHAR(id, p);
-	GETSHORT(len, p);
-	if (len < HEADERLEN || len > plen)
-		return 0;
-	
-	if (code >= 1 && code <= sizeof(lcp_codenames) / sizeof(char *))
-		printer(arg, " %s", lcp_codenames[code-1]);
-	else
-		printer(arg, " code=0x%x", code);
-	printer(arg, " id=0x%x", id);
-	len -= HEADERLEN;
-	switch (code) {
-	case CONFREQ:
-	case CONFACK:
-	case CONFNAK:
-	case CONFREJ:
-		/* print option list */
-		while (len >= 2) {
-			GETCHAR(code, p);
-			GETCHAR(olen, p);
-			p -= 2;
-			if (olen < 2 || olen > len) {
-				break;
-			}
-			printer(arg, " <");
-			len -= olen;
-			optend = p + olen;
-			switch (code) {
-			case CI_MRU:
-				if (olen == CILEN_SHORT) {
-					p += 2;
-					GETSHORT(cishort, p);
-					printer(arg, "mru %d", cishort);
-				}
-				break;
-			case CI_ASYNCMAP:
-				if (olen == CILEN_LONG) {
-					p += 2;
-					GETLONG(cilong, p);
-					printer(arg, "asyncmap 0x%lx", cilong);
-				}
-				break;
-			case CI_AUTHTYPE:
-				if (olen >= CILEN_SHORT) {
-					p += 2;
-					printer(arg, "auth ");
-					GETSHORT(cishort, p);
-					switch (cishort) {
-					case PPP_PAP:
-						printer(arg, "pap");
-						break;
-					case PPP_CHAP:
-						printer(arg, "chap");
-						break;
-					default:
-						printer(arg, "0x%x", cishort);
-					}
-				}
-				break;
-			case CI_QUALITY:
-				if (olen >= CILEN_SHORT) {
-					p += 2;
-					printer(arg, "quality ");
-					GETSHORT(cishort, p);
-					switch (cishort) {
-					case PPP_LQR:
-						printer(arg, "lqr");
-						break;
-					default:
-						printer(arg, "0x%x", cishort);
-					}
-				}
-				break;
-			case CI_CALLBACK:
-				if (olen >= CILEN_CHAR) {
-					p += 2;
-					printer(arg, "callback ");
-					GETSHORT(cishort, p);
-					switch (cishort) {
-					case CBCP_OPT:
-						printer(arg, "CBCP");
-						break;
-					default:
-						printer(arg, "0x%x", cishort);
-					}
-				}
-				break;
-			case CI_MAGICNUMBER:
-				if (olen == CILEN_LONG) {
-					p += 2;
-					GETLONG(cilong, p);
-					printer(arg, "magic 0x%x", cilong);
-				}
-				break;
-			case CI_PCOMPRESSION:
-				if (olen == CILEN_VOID) {
-					p += 2;
-					printer(arg, "pcomp");
-				}
-				break;
-			case CI_ACCOMPRESSION:
-				if (olen == CILEN_VOID) {
-					p += 2;
-					printer(arg, "accomp");
-				}
-				break;
-			}
-			while (p < optend) {
-				GETCHAR(code, p);
-				printer(arg, " %.2x", code);
-			}
-			printer(arg, ">");
-		}
-		break;
-	
-	case TERMACK:
-	case TERMREQ:
-		if (len > 0 && *p >= ' ' && *p < 0x7f) {
-			printer(arg, " ");
-			print_string((char*)p, len, printer, arg);
-			p += len;
-			len = 0;
-		}
-		break;
-	
-	case ECHOREQ:
-	case ECHOREP:
-	case DISCREQ:
-		if (len >= 4) {
-			GETLONG(cilong, p);
-			printer(arg, " magic=0x%x", cilong);
-			p += 4;
-			len -= 4;
-		}
-		break;
-	}
-	
-	/* print the rest of the bytes in the packet */
-	for (; len > 0; --len) {
-		GETCHAR(code, p);
-		printer(arg, " %.2x", code);
-	}
-	
-	return (int)(p - pstart);
-}
-#endif
-
-/*
- * Time to shut down the link because there is nothing out there.
- */
-
-static void LcpLinkFailure (fsm *f)
-{
-	if (f->state == OPENED) {
-		LCPDEBUG((LOG_INFO, "No response to %d echo-requests\n", lcp_echos_pending));
-		LCPDEBUG((LOG_NOTICE, "Serial link appears to be disconnected.\n"));
-		lcp_close(f->unit, "Peer not responding");
-	}
-}
-
-/*
- * Timer expired for the LCP echo requests from this process.
- */
-
-static void LcpEchoCheck (fsm *f)
-{
-	LcpSendEchoRequest (f);
-	
-	/*
-	 * Start the timer for the next interval.
-	 */
-	LWIP_ASSERT("lcp_echo_timer_running == 0", lcp_echo_timer_running == 0);
-
-	TIMEOUT (LcpEchoTimeout, f, lcp_echo_interval);
-	lcp_echo_timer_running = 1;
-}
-
-/*
- * LcpEchoTimeout - Timer expired on the LCP echo
- */
-
-static void LcpEchoTimeout (void *arg)
-{
-	if (lcp_echo_timer_running != 0) {
-		lcp_echo_timer_running = 0;
-		LcpEchoCheck ((fsm *) arg);
-	}
-}
-
-/*
- * LcpEchoReply - LCP has received a reply to the echo
- */
-static void lcp_received_echo_reply (fsm *f, int id, u_char *inp, int len)
-{
-	u32_t magic;
-	
-	(void)id;
-
-	/* Check the magic number - don't count replies from ourselves. */
-	if (len < 4) {
-		LCPDEBUG((LOG_WARNING, "lcp: received short Echo-Reply, length %d\n", len));
-		return;
-	}
-	GETLONG(magic, inp);
-	if (lcp_gotoptions[f->unit].neg_magicnumber
-			&& magic == lcp_gotoptions[f->unit].magicnumber) {
-		LCPDEBUG((LOG_WARNING, "appear to have received our own echo-reply!\n"));
-		return;
-	}
-	
-	/* Reset the number of outstanding echo frames */
-	lcp_echos_pending = 0;
-}
-
-/*
- * LcpSendEchoRequest - Send an echo request frame to the peer
- */
-
-static void LcpSendEchoRequest (fsm *f)
-{
-	u32_t lcp_magic;
-	u_char pkt[4], *pktp;
-	
-	/*
-	* Detect the failure of the peer at this point.
-	*/
-	if (lcp_echo_fails != 0) {
-		if (lcp_echos_pending++ >= lcp_echo_fails) {
-			LcpLinkFailure(f);
-			lcp_echos_pending = 0;
-		}
-	}
-	
-	/*
-	* Make and send the echo request frame.
-	*/
-	if (f->state == OPENED) {
-		lcp_magic = lcp_gotoptions[f->unit].magicnumber;
-		pktp = pkt;
-		PUTLONG(lcp_magic, pktp);
-		fsm_sdata(f, ECHOREQ, (u_char)(lcp_echo_number++ & 0xFF), pkt, (int)(pktp - pkt));
-	}
-}
-
-/*
- * lcp_echo_lowerup - Start the timer for the LCP frame
- */
-
-static void lcp_echo_lowerup (int unit)
-{
-	fsm *f = &lcp_fsm[unit];
-	
-	/* Clear the parameters for generating echo frames */
-	lcp_echos_pending      = 0;
-	lcp_echo_number        = 0;
-	lcp_echo_timer_running = 0;
-	
-	/* If a timeout interval is specified then start the timer */
-	if (lcp_echo_interval != 0)
-		LcpEchoCheck (f);
-}
-
-/*
- * lcp_echo_lowerdown - Stop the timer for the LCP frame
- */
-
-static void lcp_echo_lowerdown (int unit)
-{
-	fsm *f = &lcp_fsm[unit];
-	
-	if (lcp_echo_timer_running != 0) {
-		UNTIMEOUT (LcpEchoTimeout, f);
-		lcp_echo_timer_running = 0;
-	}
-}
-
-#endif /* PPP_SUPPORT */
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/lcp.h b/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/lcp.h
deleted file mode 100644
index 2944d8192..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/lcp.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/*****************************************************************************
-* lcp.h - Network Link Control Protocol header file.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* portions Copyright (c) 1997 Global Election Systems Inc.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY
-*
-* 03-01-01 Marc Boucher 
-*   Ported to lwIP.
-* 97-11-05 Guy Lancaster , Global Election Systems Inc.
-*	Original derived from BSD codes.
-*****************************************************************************/
-/*
- * lcp.h - Link Control Protocol definitions.
- *
- * Copyright (c) 1989 Carnegie Mellon University.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by Carnegie Mellon University.  The name of the
- * University may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- *
- * $Id: lcp.h,v 1.2 2006/08/29 18:53:47 wolti Exp $
- */
-
-#ifndef LCP_H
-#define LCP_H
-
-
-/*************************
-*** PUBLIC DEFINITIONS ***
-*************************/
-/*
- * Options.
- */
-#define CI_MRU		1	/* Maximum Receive Unit */
-#define CI_ASYNCMAP	2	/* Async Control Character Map */
-#define CI_AUTHTYPE	3	/* Authentication Type */
-#define CI_QUALITY	4	/* Quality Protocol */
-#define CI_MAGICNUMBER	5	/* Magic Number */
-#define CI_PCOMPRESSION	7	/* Protocol Field Compression */
-#define CI_ACCOMPRESSION 8	/* Address/Control Field Compression */
-#define CI_CALLBACK	13	/* callback */
-#define CI_MRRU		17	/* max reconstructed receive unit; multilink */
-#define CI_SSNHF	18	/* short sequence numbers for multilink */
-#define CI_EPDISC	19	/* endpoint discriminator */
-
-/*
- * LCP-specific packet types.
- */
-#define PROTREJ		8	/* Protocol Reject */
-#define ECHOREQ		9	/* Echo Request */
-#define ECHOREP		10	/* Echo Reply */
-#define DISCREQ		11	/* Discard Request */
-#define CBCP_OPT	6	/* Use callback control protocol */
-
-
-/************************
-*** PUBLIC DATA TYPES ***
-************************/
-
-/*
- * The state of options is described by an lcp_options structure.
- */
-typedef struct lcp_options {
-    u_int passive : 1;			/* Don't die if we don't get a response */
-    u_int silent : 1;				/* Wait for the other end to start first */
-    u_int restart : 1;			/* Restart vs. exit after close */
-    u_int neg_mru : 1;			/* Negotiate the MRU? */
-    u_int neg_asyncmap : 1;		/* Negotiate the async map? */
-    u_int neg_upap : 1;			/* Ask for UPAP authentication? */
-    u_int neg_chap : 1;			/* Ask for CHAP authentication? */
-    u_int neg_magicnumber : 1;	/* Ask for magic number? */
-    u_int neg_pcompression : 1;	/* HDLC Protocol Field Compression? */
-    u_int neg_accompression : 1;	/* HDLC Address/Control Field Compression? */
-    u_int neg_lqr : 1;			/* Negotiate use of Link Quality Reports */
-    u_int neg_cbcp : 1;			/* Negotiate use of CBCP */
-#ifdef PPP_MULTILINK
-    u_int neg_mrru : 1;			/* Negotiate multilink MRRU */
-    u_int neg_ssnhf : 1;		/* Negotiate short sequence numbers */
-    u_int neg_endpoint : 1;		/* Negotiate endpoint discriminator */
-#endif
-    u_short mru;			/* Value of MRU */
-#ifdef PPP_MULTILINK
-    u_short mrru;			/* Value of MRRU, and multilink enable */
-#endif
-    u_char chap_mdtype;			/* which MD type (hashing algorithm) */
-    u32_t asyncmap;			/* Value of async map */
-    u32_t magicnumber;
-    int numloops;				/* Number of loops during magic number neg. */
-    u32_t lqr_period;		/* Reporting period for LQR 1/100ths second */
-#ifdef PPP_MULTILINK
-    struct epdisc endpoint;	/* endpoint discriminator */
-#endif
-} lcp_options;
-
-/*
- * Values for phase from BSD pppd.h based on RFC 1661.
- */
-typedef enum {
-	PHASE_DEAD = 0,
-	PHASE_INITIALIZE,
-	PHASE_ESTABLISH,
-	PHASE_AUTHENTICATE,
-	PHASE_CALLBACK,
-	PHASE_NETWORK,
-	PHASE_TERMINATE
-} LinkPhase;
-
-
-/*****************************
-*** PUBLIC DATA STRUCTURES ***
-*****************************/
-
-extern LinkPhase lcp_phase[NUM_PPP];	/* Phase of link session (RFC 1661) */
-extern lcp_options lcp_wantoptions[];
-extern lcp_options lcp_gotoptions[];
-extern lcp_options lcp_allowoptions[];
-extern lcp_options lcp_hisoptions[];
-extern ext_accm xmit_accm[];
-
-
-/***********************
-*** PUBLIC FUNCTIONS ***
-***********************/
-
-void lcp_init (int);
-void lcp_open (int);
-void lcp_close (int, char *);
-void lcp_lowerup (int);
-void lcp_lowerdown (int);
-void lcp_sprotrej (int, u_char *, int);	/* send protocol reject */
-
-extern struct protent lcp_protent;
-
-/* Default number of times we receive our magic number from the peer
-   before deciding the link is looped-back. */
-#define DEFLOOPBACKFAIL	10
-
-#endif /* LCP_H */
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/magic.c b/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/magic.c
deleted file mode 100644
index 427401691..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/magic.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*****************************************************************************
-* magic.c - Network Random Number Generator program file.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* portions Copyright (c) 1997 by Global Election Systems Inc.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY
-*
-* 03-01-01 Marc Boucher 
-*   Ported to lwIP.
-* 97-12-04 Guy Lancaster , Global Election Systems Inc.
-*	Original based on BSD magic.c.
-*****************************************************************************/
-/*
- * magic.c - PPP Magic Number routines.
- *
- * Copyright (c) 1989 Carnegie Mellon University.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by Carnegie Mellon University.  The name of the
- * University may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- */
-
-#include "ppp.h"
-#include "randm.h"
-#include "magic.h"
-
-
-/***********************************/
-/*** PUBLIC FUNCTION DEFINITIONS ***/
-/***********************************/
-/*
- * magicInit - Initialize the magic number generator.
- *
- * Since we use another random number generator that has its own
- * initialization, we do nothing here.
- */
-void magicInit()
-{
-	return;
-}
-
-/*
- * magic - Returns the next magic number.
- */
-u32_t magic()
-{
-    return avRandom();
-}
-
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/magic.h b/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/magic.h
deleted file mode 100644
index f8a981728..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/magic.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*****************************************************************************
-* magic.h - Network Random Number Generator header file.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* portions Copyright (c) 1997 Global Election Systems Inc.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY
-*
-* 03-01-01 Marc Boucher 
-*   Ported to lwIP.
-* 97-12-04 Guy Lancaster , Global Election Systems Inc.
-*   Original derived from BSD codes.
-*****************************************************************************/
-/*
- * magic.h - PPP Magic Number definitions.
- *
- * Copyright (c) 1989 Carnegie Mellon University.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by Carnegie Mellon University.  The name of the
- * University may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- *
- * $Id: magic.h,v 1.2 2006/08/29 18:53:47 wolti Exp $
- */
-
-#ifndef MAGIC_H
-#define MAGIC_H
-
-/*****************************************************************************
-************************** PUBLIC FUNCTIONS **********************************
-*****************************************************************************/
-
-void magicInit(void);   /* Initialize the magic number generator */
-u32_t magic(void);  /* Returns the next magic number */
-
-#endif /* MAGIC_H */
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/md5.c b/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/md5.c
deleted file mode 100644
index e077cdea5..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/md5.c
+++ /dev/null
@@ -1,306 +0,0 @@
-/*
- ***********************************************************************
- ** md5.c -- the source code for MD5 routines                         **
- ** RSA Data Security, Inc. MD5 Message-Digest Algorithm              **
- ** Created: 2/17/90 RLR                                              **
- ** Revised: 1/91 SRD,AJ,BSK,JT Reference C ver., 7/10 constant corr. **
- ***********************************************************************
- */
-
-/*
- ***********************************************************************
- ** Copyright (C) 1990, RSA Data Security, Inc. All rights reserved.  **
- **                                                                   **
- ** License to copy and use this software is granted provided that    **
- ** it is identified as the "RSA Data Security, Inc. MD5 Message-     **
- ** Digest Algorithm" in all material mentioning or referencing this  **
- ** software or this function.                                        **
- **                                                                   **
- ** License is also granted to make and use derivative works          **
- ** provided that such works are identified as "derived from the RSA  **
- ** Data Security, Inc. MD5 Message-Digest Algorithm" in all          **
- ** material mentioning or referencing the derived work.              **
- **                                                                   **
- ** RSA Data Security, Inc. makes no representations concerning       **
- ** either the merchantability of this software or the suitability    **
- ** of this software for any particular purpose.  It is provided "as  **
- ** is" without express or implied warranty of any kind.              **
- **                                                                   **
- ** These notices must be retained in any copies of any part of this  **
- ** documentation and/or software.                                    **
- ***********************************************************************
- */
-
-#include "ppp.h"
-#include "md5.h"
-#include "pppdebug.h"
-
-#if CHAP_SUPPORT > 0 || MD5_SUPPORT > 0
-
-/*
- ***********************************************************************
- **  Message-digest routines:                                         **
- **  To form the message digest for a message M                       **
- **    (1) Initialize a context buffer mdContext using MD5Init        **
- **    (2) Call MD5Update on mdContext and M                          **
- **    (3) Call MD5Final on mdContext                                 **
- **  The message digest is now in mdContext->digest[0...15]           **
- ***********************************************************************
- */
-
-/* forward declaration */
-static void Transform (u32_t *buf, u32_t *in);
-
-static unsigned char PADDING[64] = {
-  0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
-};
-
-/* F, G, H and I are basic MD5 functions */
-#define F(x, y, z) (((x) & (y)) | ((~x) & (z)))
-#define G(x, y, z) (((x) & (z)) | ((y) & (~z)))
-#define H(x, y, z) ((x) ^ (y) ^ (z))
-#define I(x, y, z) ((y) ^ ((x) | (~z)))
-
-/* ROTATE_LEFT rotates x left n bits */
-#define ROTATE_LEFT(x, n) (((x) << (n)) | ((x) >> (32-(n))))
-
-/* FF, GG, HH, and II transformations for rounds 1, 2, 3, and 4 */
-/* Rotation is separate from addition to prevent recomputation */
-#define FF(a, b, c, d, x, s, ac) \
-  {(a) += F ((b), (c), (d)) + (x) + (u32_t)(ac); \
-   (a) = ROTATE_LEFT ((a), (s)); \
-   (a) += (b); \
-  }
-#define GG(a, b, c, d, x, s, ac) \
-  {(a) += G ((b), (c), (d)) + (x) + (u32_t)(ac); \
-   (a) = ROTATE_LEFT ((a), (s)); \
-   (a) += (b); \
-  }
-#define HH(a, b, c, d, x, s, ac) \
-  {(a) += H ((b), (c), (d)) + (x) + (u32_t)(ac); \
-   (a) = ROTATE_LEFT ((a), (s)); \
-   (a) += (b); \
-  }
-#define II(a, b, c, d, x, s, ac) \
-  {(a) += I ((b), (c), (d)) + (x) + (u32_t)(ac); \
-   (a) = ROTATE_LEFT ((a), (s)); \
-   (a) += (b); \
-  }
-
-#ifdef __STDC__
-#define UL(x)	x##UL
-#else
-#ifdef WIN32
-#define UL(x)	x##UL
-#else
-#define UL(x)	x
-#endif
-#endif
-
-/* The routine MD5Init initializes the message-digest context
-   mdContext. All fields are set to zero.
- */
-void MD5Init (MD5_CTX *mdContext)
-{
-  mdContext->i[0] = mdContext->i[1] = (u32_t)0;
-
-  /* Load magic initialization constants.
-   */
-  mdContext->buf[0] = (u32_t)0x67452301UL;
-  mdContext->buf[1] = (u32_t)0xefcdab89UL;
-  mdContext->buf[2] = (u32_t)0x98badcfeUL;
-  mdContext->buf[3] = (u32_t)0x10325476UL;
-}
-
-/* The routine MD5Update updates the message-digest context to
-   account for the presence of each of the characters inBuf[0..inLen-1]
-   in the message whose digest is being computed.
- */
-void MD5Update(MD5_CTX *mdContext, unsigned char *inBuf, unsigned int inLen)
-{
-  u32_t in[16];
-  int mdi;
-  unsigned int i, ii;
-
-#if 0
-  ppp_trace(LOG_INFO, "MD5Update: %u:%.*H\n", inLen, MIN(inLen, 20) * 2, inBuf);
-  ppp_trace(LOG_INFO, "MD5Update: %u:%s\n", inLen, inBuf);
-#endif
-  
-  /* compute number of bytes mod 64 */
-  mdi = (int)((mdContext->i[0] >> 3) & 0x3F);
-
-  /* update number of bits */
-  if ((mdContext->i[0] + ((u32_t)inLen << 3)) < mdContext->i[0])
-    mdContext->i[1]++;
-  mdContext->i[0] += ((u32_t)inLen << 3);
-  mdContext->i[1] += ((u32_t)inLen >> 29);
-
-  while (inLen--) {
-    /* add new character to buffer, increment mdi */
-    mdContext->in[mdi++] = *inBuf++;
-
-    /* transform if necessary */
-    if (mdi == 0x40) {
-      for (i = 0, ii = 0; i < 16; i++, ii += 4)
-        in[i] = (((u32_t)mdContext->in[ii+3]) << 24) |
-                (((u32_t)mdContext->in[ii+2]) << 16) |
-				(((u32_t)mdContext->in[ii+1]) << 8) |
-                ((u32_t)mdContext->in[ii]);
-      Transform (mdContext->buf, in);
-      mdi = 0;
-    }
-  }
-}
-
-/* The routine MD5Final terminates the message-digest computation and
-   ends with the desired message digest in mdContext->digest[0...15].
- */
-void MD5Final (unsigned char hash[], MD5_CTX *mdContext)
-{
-  u32_t in[16];
-  int mdi;
-  unsigned int i, ii;
-  unsigned int padLen;
-
-  /* save number of bits */
-  in[14] = mdContext->i[0];
-  in[15] = mdContext->i[1];
-
-  /* compute number of bytes mod 64 */
-  mdi = (int)((mdContext->i[0] >> 3) & 0x3F);
-
-  /* pad out to 56 mod 64 */
-  padLen = (mdi < 56) ? (56 - mdi) : (120 - mdi);
-  MD5Update (mdContext, PADDING, padLen);
-
-  /* append length in bits and transform */
-  for (i = 0, ii = 0; i < 14; i++, ii += 4)
-    in[i] = (((u32_t)mdContext->in[ii+3]) << 24) |
-            (((u32_t)mdContext->in[ii+2]) << 16) |
-            (((u32_t)mdContext->in[ii+1]) << 8) |
-            ((u32_t)mdContext->in[ii]);
-  Transform (mdContext->buf, in);
-
-  /* store buffer in digest */
-  for (i = 0, ii = 0; i < 4; i++, ii += 4) {
-    mdContext->digest[ii] = (unsigned char)(mdContext->buf[i] & 0xFF);
-	mdContext->digest[ii+1] =
-      (unsigned char)((mdContext->buf[i] >> 8) & 0xFF);
-    mdContext->digest[ii+2] =
-      (unsigned char)((mdContext->buf[i] >> 16) & 0xFF);
-    mdContext->digest[ii+3] =
-      (unsigned char)((mdContext->buf[i] >> 24) & 0xFF);
-  }
-  memcpy(hash, mdContext->digest, 16);
-}
-
-/* Basic MD5 step. Transforms buf based on in.
- */
-static void Transform (u32_t *buf, u32_t *in)
-{
-  u32_t a = buf[0], b = buf[1], c = buf[2], d = buf[3];
-
-  /* Round 1 */
-#define S11 7
-#define S12 12
-#define S13 17
-#define S14 22
-  FF ( a, b, c, d, in[ 0], S11, UL(3614090360)); /* 1 */
-  FF ( d, a, b, c, in[ 1], S12, UL(3905402710)); /* 2 */
-  FF ( c, d, a, b, in[ 2], S13, UL( 606105819)); /* 3 */
-  FF ( b, c, d, a, in[ 3], S14, UL(3250441966)); /* 4 */
-  FF ( a, b, c, d, in[ 4], S11, UL(4118548399)); /* 5 */
-  FF ( d, a, b, c, in[ 5], S12, UL(1200080426)); /* 6 */
-  FF ( c, d, a, b, in[ 6], S13, UL(2821735955)); /* 7 */
-  FF ( b, c, d, a, in[ 7], S14, UL(4249261313)); /* 8 */
-  FF ( a, b, c, d, in[ 8], S11, UL(1770035416)); /* 9 */
-  FF ( d, a, b, c, in[ 9], S12, UL(2336552879)); /* 10 */
-  FF ( c, d, a, b, in[10], S13, UL(4294925233)); /* 11 */
-  FF ( b, c, d, a, in[11], S14, UL(2304563134)); /* 12 */
-  FF ( a, b, c, d, in[12], S11, UL(1804603682)); /* 13 */
-  FF ( d, a, b, c, in[13], S12, UL(4254626195)); /* 14 */
-  FF ( c, d, a, b, in[14], S13, UL(2792965006)); /* 15 */
-  FF ( b, c, d, a, in[15], S14, UL(1236535329)); /* 16 */
-
-  /* Round 2 */
-#define S21 5
-#define S22 9
-#define S23 14
-#define S24 20
-  GG ( a, b, c, d, in[ 1], S21, UL(4129170786)); /* 17 */
-  GG ( d, a, b, c, in[ 6], S22, UL(3225465664)); /* 18 */
-  GG ( c, d, a, b, in[11], S23, UL( 643717713)); /* 19 */
-  GG ( b, c, d, a, in[ 0], S24, UL(3921069994)); /* 20 */
-  GG ( a, b, c, d, in[ 5], S21, UL(3593408605)); /* 21 */
-  GG ( d, a, b, c, in[10], S22, UL(  38016083)); /* 22 */
-  GG ( c, d, a, b, in[15], S23, UL(3634488961)); /* 23 */
-  GG ( b, c, d, a, in[ 4], S24, UL(3889429448)); /* 24 */
-  GG ( a, b, c, d, in[ 9], S21, UL( 568446438)); /* 25 */
-  GG ( d, a, b, c, in[14], S22, UL(3275163606)); /* 26 */
-  GG ( c, d, a, b, in[ 3], S23, UL(4107603335)); /* 27 */
-  GG ( b, c, d, a, in[ 8], S24, UL(1163531501)); /* 28 */
-  GG ( a, b, c, d, in[13], S21, UL(2850285829)); /* 29 */
-  GG ( d, a, b, c, in[ 2], S22, UL(4243563512)); /* 30 */
-  GG ( c, d, a, b, in[ 7], S23, UL(1735328473)); /* 31 */
-  GG ( b, c, d, a, in[12], S24, UL(2368359562)); /* 32 */
-
-  /* Round 3 */
-#define S31 4
-#define S32 11
-#define S33 16
-#define S34 23
-  HH ( a, b, c, d, in[ 5], S31, UL(4294588738)); /* 33 */
-  HH ( d, a, b, c, in[ 8], S32, UL(2272392833)); /* 34 */
-  HH ( c, d, a, b, in[11], S33, UL(1839030562)); /* 35 */
-  HH ( b, c, d, a, in[14], S34, UL(4259657740)); /* 36 */
-  HH ( a, b, c, d, in[ 1], S31, UL(2763975236)); /* 37 */
-  HH ( d, a, b, c, in[ 4], S32, UL(1272893353)); /* 38 */
-  HH ( c, d, a, b, in[ 7], S33, UL(4139469664)); /* 39 */
-  HH ( b, c, d, a, in[10], S34, UL(3200236656)); /* 40 */
-  HH ( a, b, c, d, in[13], S31, UL( 681279174)); /* 41 */
-  HH ( d, a, b, c, in[ 0], S32, UL(3936430074)); /* 42 */
-  HH ( c, d, a, b, in[ 3], S33, UL(3572445317)); /* 43 */
-  HH ( b, c, d, a, in[ 6], S34, UL(  76029189)); /* 44 */
-  HH ( a, b, c, d, in[ 9], S31, UL(3654602809)); /* 45 */
-  HH ( d, a, b, c, in[12], S32, UL(3873151461)); /* 46 */
-  HH ( c, d, a, b, in[15], S33, UL( 530742520)); /* 47 */
-  HH ( b, c, d, a, in[ 2], S34, UL(3299628645)); /* 48 */
-
-  /* Round 4 */
-#define S41 6
-#define S42 10
-#define S43 15
-#define S44 21
-  II ( a, b, c, d, in[ 0], S41, UL(4096336452)); /* 49 */
-  II ( d, a, b, c, in[ 7], S42, UL(1126891415)); /* 50 */
-  II ( c, d, a, b, in[14], S43, UL(2878612391)); /* 51 */
-  II ( b, c, d, a, in[ 5], S44, UL(4237533241)); /* 52 */
-  II ( a, b, c, d, in[12], S41, UL(1700485571)); /* 53 */
-  II ( d, a, b, c, in[ 3], S42, UL(2399980690)); /* 54 */
-  II ( c, d, a, b, in[10], S43, UL(4293915773)); /* 55 */
-  II ( b, c, d, a, in[ 1], S44, UL(2240044497)); /* 56 */
-  II ( a, b, c, d, in[ 8], S41, UL(1873313359)); /* 57 */
-  II ( d, a, b, c, in[15], S42, UL(4264355552)); /* 58 */
-  II ( c, d, a, b, in[ 6], S43, UL(2734768916)); /* 59 */
-  II ( b, c, d, a, in[13], S44, UL(1309151649)); /* 60 */
-  II ( a, b, c, d, in[ 4], S41, UL(4149444226)); /* 61 */
-  II ( d, a, b, c, in[11], S42, UL(3174756917)); /* 62 */
-  II ( c, d, a, b, in[ 2], S43, UL( 718787259)); /* 63 */
-  II ( b, c, d, a, in[ 9], S44, UL(3951481745)); /* 64 */
-
-  buf[0] += a;
-  buf[1] += b;
-  buf[2] += c;
-  buf[3] += d;
-}
-
-#endif
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/md5.h b/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/md5.h
deleted file mode 100644
index 0e81cdc34..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/md5.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- ***********************************************************************
- ** md5.h -- header file for implementation of MD5                    **
- ** RSA Data Security, Inc. MD5 Message-Digest Algorithm              **
- ** Created: 2/17/90 RLR                                              **
- ** Revised: 12/27/90 SRD,AJ,BSK,JT Reference C version               **
- ** Revised (for MD5): RLR 4/27/91                                    **
- **   -- G modified to have y&~z instead of y&z                       **
- **   -- FF, GG, HH modified to add in last register done             **
- **   -- Access pattern: round 2 works mod 5, round 3 works mod 3     **
- **   -- distinct additive constant for each step                     **
- **   -- round 4 added, working mod 7                                 **
- ***********************************************************************
- */
-
-/*
- ***********************************************************************
- ** Copyright (C) 1990, RSA Data Security, Inc. All rights reserved.  **
- **                                                                   **
- ** License to copy and use this software is granted provided that    **
- ** it is identified as the "RSA Data Security, Inc. MD5 Message-     **
- ** Digest Algorithm" in all material mentioning or referencing this  **
- ** software or this function.                                        **
- **                                                                   **
- ** License is also granted to make and use derivative works          **
- ** provided that such works are identified as "derived from the RSA  **
- ** Data Security, Inc. MD5 Message-Digest Algorithm" in all          **
- ** material mentioning or referencing the derived work.              **
- **                                                                   **
- ** RSA Data Security, Inc. makes no representations concerning       **
- ** either the merchantability of this software or the suitability    **
- ** of this software for any particular purpose.  It is provided "as  **
- ** is" without express or implied warranty of any kind.              **
- **                                                                   **
- ** These notices must be retained in any copies of any part of this  **
- ** documentation and/or software.                                    **
- ***********************************************************************
- */
-
-#ifndef MD5_H
-#define MD5_H
-
-/* Data structure for MD5 (Message-Digest) computation */
-typedef struct {
-  u32_t i[2];                   /* number of _bits_ handled mod 2^64 */
-  u32_t buf[4];                                    /* scratch buffer */
-  unsigned char in[64];                              /* input buffer */
-  unsigned char digest[16];     /* actual digest after MD5Final call */
-} MD5_CTX;
-
-void MD5Init (MD5_CTX *mdContext);
-void MD5Update (MD5_CTX *mdContext, unsigned char *inBuf, unsigned int inLen);
-void MD5Final (unsigned char hash[], MD5_CTX *mdContext);
-
-#endif /* MD5_H */
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/pap.c b/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/pap.c
deleted file mode 100644
index 23e438ff2..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/pap.c
+++ /dev/null
@@ -1,608 +0,0 @@
-/*****************************************************************************
-* pap.c - Network Password Authentication Protocol program file.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* portions Copyright (c) 1997 by Global Election Systems Inc.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY
-*
-* 03-01-01 Marc Boucher 
-*   Ported to lwIP.
-* 97-12-12 Guy Lancaster , Global Election Systems Inc.
-*	Original.
-*****************************************************************************/
-/*
- * upap.c - User/Password Authentication Protocol.
- *
- * Copyright (c) 1989 Carnegie Mellon University.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by Carnegie Mellon University.  The name of the
- * University may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- */
-
-#include "ppp.h"
-#include "auth.h"
-#include "pap.h"
-#include "pppdebug.h"
-
-
-#if PAP_SUPPORT > 0
-
-/***********************************/
-/*** LOCAL FUNCTION DECLARATIONS ***/
-/***********************************/
-/*
- * Protocol entry points.
- */
-static void upap_init (int);
-static void upap_lowerup (int);
-static void upap_lowerdown (int);
-static void upap_input (int, u_char *, int);
-static void upap_protrej (int);
-
-static void upap_timeout (void *);
-static void upap_reqtimeout (void *);
-static void upap_rauthreq (upap_state *, u_char *, int, int);
-static void upap_rauthack (upap_state *, u_char *, int, int);
-static void upap_rauthnak (upap_state *, u_char *, int, int);
-static void upap_sauthreq (upap_state *);
-static void upap_sresp (upap_state *, u_char, u_char, char *, int);
-
-
-
-
-/******************************/
-/*** PUBLIC DATA STRUCTURES ***/
-/******************************/
-struct protent pap_protent = {
-    PPP_PAP,
-    upap_init,
-    upap_input,
-    upap_protrej,
-    upap_lowerup,
-    upap_lowerdown,
-    NULL,
-    NULL,
-#if 0
-    upap_printpkt,
-    NULL,
-#endif
-    1,
-    "PAP",
-#if 0
-    NULL,
-    NULL,
-    NULL
-#endif
-};
-
-upap_state upap[NUM_PPP];		/* UPAP state; one for each unit */
-
-
-
-/***********************************/
-/*** PUBLIC FUNCTION DEFINITIONS ***/
-/***********************************/
-/*
- *  Set the default login name and password for the pap sessions
- */
-void upap_setloginpasswd(int unit, const char *luser, const char *lpassword)
-{
-	upap_state *u = &upap[unit];
-	
-	/* Save the username and password we're given */
-	u->us_user = luser;
-	u->us_userlen = strlen(luser);
-	u->us_passwd = lpassword;
-	u->us_passwdlen = strlen(lpassword);
-}
-
-
-/*
- * upap_authwithpeer - Authenticate us with our peer (start client).
- *
- * Set new state and send authenticate's.
- */
-void upap_authwithpeer(int unit, char *user, char *password)
-{
-	upap_state *u = &upap[unit];
-	
-	UPAPDEBUG((LOG_INFO, "upap_authwithpeer: %d user=%s password=%s s=%d\n",
-				unit, user, password, u->us_clientstate));
-	
-	upap_setloginpasswd(unit, user, password);
-
-	u->us_transmits = 0;
-	
-	/* Lower layer up yet? */
-	if (u->us_clientstate == UPAPCS_INITIAL ||
-			u->us_clientstate == UPAPCS_PENDING) {
-		u->us_clientstate = UPAPCS_PENDING;
-		return;
-	}
-	
-	upap_sauthreq(u);			/* Start protocol */
-}
-
-
-/*
- * upap_authpeer - Authenticate our peer (start server).
- *
- * Set new state.
- */
-void upap_authpeer(int unit)
-{
-	upap_state *u = &upap[unit];
-	
-	/* Lower layer up yet? */
-	if (u->us_serverstate == UPAPSS_INITIAL ||
-			u->us_serverstate == UPAPSS_PENDING) {
-		u->us_serverstate = UPAPSS_PENDING;
-		return;
-	}
-	
-	u->us_serverstate = UPAPSS_LISTEN;
-	if (u->us_reqtimeout > 0)
-		TIMEOUT(upap_reqtimeout, u, u->us_reqtimeout);
-}
-
-
-
-/**********************************/
-/*** LOCAL FUNCTION DEFINITIONS ***/
-/**********************************/
-/*
- * upap_init - Initialize a UPAP unit.
- */
-static void upap_init(int unit)
-{
-	upap_state *u = &upap[unit];
-
-	UPAPDEBUG((LOG_INFO, "upap_init: %d\n", unit));	
-	u->us_unit = unit;
-	u->us_user = NULL;
-	u->us_userlen = 0;
-	u->us_passwd = NULL;
-	u->us_passwdlen = 0;
-	u->us_clientstate = UPAPCS_INITIAL;
-	u->us_serverstate = UPAPSS_INITIAL;
-	u->us_id = 0;
-	u->us_timeouttime = UPAP_DEFTIMEOUT;
-	u->us_maxtransmits = 10;
-	u->us_reqtimeout = UPAP_DEFREQTIME;
-}
-
-/*
- * upap_timeout - Retransmission timer for sending auth-reqs expired.
- */
-static void upap_timeout(void *arg)
-{
-	upap_state *u = (upap_state *) arg;
-	
-	UPAPDEBUG((LOG_INFO, "upap_timeout: %d timeout %d expired s=%d\n", 
-				u->us_unit, u->us_timeouttime, u->us_clientstate));
-	
-	if (u->us_clientstate != UPAPCS_AUTHREQ)
-		return;
-	
-	if (u->us_transmits >= u->us_maxtransmits) {
-		/* give up in disgust */
-		UPAPDEBUG((LOG_ERR, "No response to PAP authenticate-requests\n"));
-		u->us_clientstate = UPAPCS_BADAUTH;
-		auth_withpeer_fail(u->us_unit, PPP_PAP);
-		return;
-	}
-	
-	upap_sauthreq(u);		/* Send Authenticate-Request */
-}
-
-
-/*
- * upap_reqtimeout - Give up waiting for the peer to send an auth-req.
- */
-static void upap_reqtimeout(void *arg)
-{
-	upap_state *u = (upap_state *) arg;
-	
-	if (u->us_serverstate != UPAPSS_LISTEN)
-		return;			/* huh?? */
-	
-	auth_peer_fail(u->us_unit, PPP_PAP);
-	u->us_serverstate = UPAPSS_BADAUTH;
-}
-
-
-/*
- * upap_lowerup - The lower layer is up.
- *
- * Start authenticating if pending.
- */
-static void upap_lowerup(int unit)
-{
-	upap_state *u = &upap[unit];
-	
-	UPAPDEBUG((LOG_INFO, "upap_lowerup: %d s=%d\n", unit, u->us_clientstate));
-	
-	if (u->us_clientstate == UPAPCS_INITIAL)
-		u->us_clientstate = UPAPCS_CLOSED;
-	else if (u->us_clientstate == UPAPCS_PENDING) {
-		upap_sauthreq(u);	/* send an auth-request */
-	}
-	
-	if (u->us_serverstate == UPAPSS_INITIAL)
-		u->us_serverstate = UPAPSS_CLOSED;
-	else if (u->us_serverstate == UPAPSS_PENDING) {
-		u->us_serverstate = UPAPSS_LISTEN;
-		if (u->us_reqtimeout > 0)
-			TIMEOUT(upap_reqtimeout, u, u->us_reqtimeout);
-	}
-}
-
-
-/*
- * upap_lowerdown - The lower layer is down.
- *
- * Cancel all timeouts.
- */
-static void upap_lowerdown(int unit)
-{
-	upap_state *u = &upap[unit];
-	
-	UPAPDEBUG((LOG_INFO, "upap_lowerdown: %d s=%d\n", unit, u->us_clientstate));
-	
-	if (u->us_clientstate == UPAPCS_AUTHREQ)	/* Timeout pending? */
-		UNTIMEOUT(upap_timeout, u);		/* Cancel timeout */
-	if (u->us_serverstate == UPAPSS_LISTEN && u->us_reqtimeout > 0)
-		UNTIMEOUT(upap_reqtimeout, u);
-	
-	u->us_clientstate = UPAPCS_INITIAL;
-	u->us_serverstate = UPAPSS_INITIAL;
-}
-
-
-/*
- * upap_protrej - Peer doesn't speak this protocol.
- *
- * This shouldn't happen.  In any case, pretend lower layer went down.
- */
-static void upap_protrej(int unit)
-{
-	upap_state *u = &upap[unit];
-	
-	if (u->us_clientstate == UPAPCS_AUTHREQ) {
-		UPAPDEBUG((LOG_ERR, "PAP authentication failed due to protocol-reject\n"));
-		auth_withpeer_fail(unit, PPP_PAP);
-	}
-	if (u->us_serverstate == UPAPSS_LISTEN) {
-		UPAPDEBUG((LOG_ERR, "PAP authentication of peer failed (protocol-reject)\n"));
-		auth_peer_fail(unit, PPP_PAP);
-	}
-	upap_lowerdown(unit);
-}
-
-
-/*
- * upap_input - Input UPAP packet.
- */
-static void upap_input(int unit, u_char *inpacket, int l)
-{
-	upap_state *u = &upap[unit];
-	u_char *inp;
-	u_char code, id;
-	int len;
-	
-	/*
-	 * Parse header (code, id and length).
-	 * If packet too short, drop it.
-	 */
-	inp = inpacket;
-	if (l < UPAP_HEADERLEN) {
-		UPAPDEBUG((LOG_INFO, "pap_input: rcvd short header.\n"));
-		return;
-	}
-	GETCHAR(code, inp);
-	GETCHAR(id, inp);
-	GETSHORT(len, inp);
-	if (len < UPAP_HEADERLEN) {
-		UPAPDEBUG((LOG_INFO, "pap_input: rcvd illegal length.\n"));
-		return;
-	}
-	if (len > l) {
-		UPAPDEBUG((LOG_INFO, "pap_input: rcvd short packet.\n"));
-		return;
-	}
-	len -= UPAP_HEADERLEN;
-	
-	/*
-	 * Action depends on code.
-	 */
-	switch (code) {
-	case UPAP_AUTHREQ:
-		upap_rauthreq(u, inp, id, len);
-		break;
-	
-	case UPAP_AUTHACK:
-		upap_rauthack(u, inp, id, len);
-		break;
-	
-	case UPAP_AUTHNAK:
-		upap_rauthnak(u, inp, id, len);
-		break;
-	
-	default:				/* XXX Need code reject */
-		break;
-	}
-}
-
-
-/*
- * upap_rauth - Receive Authenticate.
- */
-static void upap_rauthreq(
-	upap_state *u, 
-	u_char *inp, 
-	int id,
-	int len
-)
-{
-	u_char ruserlen, rpasswdlen;
-	char *ruser, *rpasswd;
-	int retcode;
-	char *msg;
-	int msglen;
-	
-	UPAPDEBUG((LOG_INFO, "pap_rauth: Rcvd id %d.\n", id));
-	
-	if (u->us_serverstate < UPAPSS_LISTEN)
-		return;
-	
-	/*
-	 * If we receive a duplicate authenticate-request, we are
-	 * supposed to return the same status as for the first request.
-	 */
-	if (u->us_serverstate == UPAPSS_OPEN) {
-		upap_sresp(u, UPAP_AUTHACK, id, "", 0);	/* return auth-ack */
-		return;
-	}
-	if (u->us_serverstate == UPAPSS_BADAUTH) {
-		upap_sresp(u, UPAP_AUTHNAK, id, "", 0);	/* return auth-nak */
-		return;
-	}
-	
-	/*
-	 * Parse user/passwd.
-	 */
-	if (len < sizeof (u_char)) {
-		UPAPDEBUG((LOG_INFO, "pap_rauth: rcvd short packet.\n"));
-		return;
-	}
-	GETCHAR(ruserlen, inp);
-	len -= sizeof (u_char) + ruserlen + sizeof (u_char);
-	if (len < 0) {
-		UPAPDEBUG((LOG_INFO, "pap_rauth: rcvd short packet.\n"));
-		return;
-	}
-	ruser = (char *) inp;
-	INCPTR(ruserlen, inp);
-	GETCHAR(rpasswdlen, inp);
-	if (len < rpasswdlen) {
-		UPAPDEBUG((LOG_INFO, "pap_rauth: rcvd short packet.\n"));
-		return;
-	}
-	rpasswd = (char *) inp;
-	
-	/*
-	 * Check the username and password given.
-	 */
-	retcode = check_passwd(u->us_unit, ruser, ruserlen, rpasswd,
-			   rpasswdlen, &msg, &msglen);
-	BZERO(rpasswd, rpasswdlen);
-	
-	upap_sresp(u, retcode, id, msg, msglen);
-	
-	if (retcode == UPAP_AUTHACK) {
-		u->us_serverstate = UPAPSS_OPEN;
-		auth_peer_success(u->us_unit, PPP_PAP, ruser, ruserlen);
-	} else {
-		u->us_serverstate = UPAPSS_BADAUTH;
-		auth_peer_fail(u->us_unit, PPP_PAP);
-	}
-	
-	if (u->us_reqtimeout > 0)
-		UNTIMEOUT(upap_reqtimeout, u);
-}
-
-
-/*
- * upap_rauthack - Receive Authenticate-Ack.
- */
-static void upap_rauthack(
-	upap_state *u,
-	u_char *inp,
-	int id,
-	int len
-)
-{
-	u_char msglen;
-	char *msg;
-	
-	UPAPDEBUG((LOG_INFO, "pap_rauthack: Rcvd id %d s=%d\n", id, u->us_clientstate));
-	
-	if (u->us_clientstate != UPAPCS_AUTHREQ) /* XXX */
-		return;
-	
-	/*
-	 * Parse message.
-	 */
-	if (len < sizeof (u_char)) {
-		UPAPDEBUG((LOG_INFO, "pap_rauthack: rcvd short packet.\n"));
-		return;
-	}
-	GETCHAR(msglen, inp);
-	len -= sizeof (u_char);
-	if (len < msglen) {
-		UPAPDEBUG((LOG_INFO, "pap_rauthack: rcvd short packet.\n"));
-		return;
-	}
-	msg = (char *) inp;
-	PRINTMSG(msg, msglen);
-	
-	u->us_clientstate = UPAPCS_OPEN;
-	
-	auth_withpeer_success(u->us_unit, PPP_PAP);
-}
-
-
-/*
- * upap_rauthnak - Receive Authenticate-Nakk.
- */
-static void upap_rauthnak(
-	upap_state *u,
-	u_char *inp,
-	int id,
-	int len
-)
-{
-	u_char msglen;
-	char *msg;
-	
-	UPAPDEBUG((LOG_INFO, "pap_rauthnak: Rcvd id %d s=%d\n", id, u->us_clientstate));
-	
-	if (u->us_clientstate != UPAPCS_AUTHREQ) /* XXX */
-		return;
-	
-	/*
-	 * Parse message.
-	 */
-	if (len < sizeof (u_char)) {
-		UPAPDEBUG((LOG_INFO, "pap_rauthnak: rcvd short packet.\n"));
-		return;
-	}
-	GETCHAR(msglen, inp);
-	len -= sizeof (u_char);
-	if (len < msglen) {
-		UPAPDEBUG((LOG_INFO, "pap_rauthnak: rcvd short packet.\n"));
-		return;
-	}
-	msg = (char *) inp;
-	PRINTMSG(msg, msglen);
-	
-	u->us_clientstate = UPAPCS_BADAUTH;
-	
-	UPAPDEBUG((LOG_ERR, "PAP authentication failed\n"));
-	auth_withpeer_fail(u->us_unit, PPP_PAP);
-}
-
-
-/*
- * upap_sauthreq - Send an Authenticate-Request.
- */
-static void upap_sauthreq(upap_state *u)
-{
-	u_char *outp;
-	int outlen;
-	
-	outlen = UPAP_HEADERLEN + 2 * sizeof (u_char) 
-			+ u->us_userlen + u->us_passwdlen;
-	outp = outpacket_buf[u->us_unit];
-	
-	MAKEHEADER(outp, PPP_PAP);
-	
-	PUTCHAR(UPAP_AUTHREQ, outp);
-	PUTCHAR(++u->us_id, outp);
-	PUTSHORT(outlen, outp);
-	PUTCHAR(u->us_userlen, outp);
-	BCOPY(u->us_user, outp, u->us_userlen);
-	INCPTR(u->us_userlen, outp);
-	PUTCHAR(u->us_passwdlen, outp);
-	BCOPY(u->us_passwd, outp, u->us_passwdlen);
-	
-	pppWrite(u->us_unit, outpacket_buf[u->us_unit], outlen + PPP_HDRLEN);
-	
-	UPAPDEBUG((LOG_INFO, "pap_sauth: Sent id %d\n", u->us_id));
-	
-	TIMEOUT(upap_timeout, u, u->us_timeouttime);
-	++u->us_transmits;
-	u->us_clientstate = UPAPCS_AUTHREQ;
-}
-
-
-/*
- * upap_sresp - Send a response (ack or nak).
- */
-static void upap_sresp(
-	upap_state *u,
-	u_char code, 
-	u_char id,
-	char *msg,
-	int msglen
-)
-{
-	u_char *outp;
-	int outlen;
-	
-	outlen = UPAP_HEADERLEN + sizeof (u_char) + msglen;
-	outp = outpacket_buf[u->us_unit];
-	MAKEHEADER(outp, PPP_PAP);
-	
-	PUTCHAR(code, outp);
-	PUTCHAR(id, outp);
-	PUTSHORT(outlen, outp);
-	PUTCHAR(msglen, outp);
-	BCOPY(msg, outp, msglen);
-	pppWrite(u->us_unit, outpacket_buf[u->us_unit], outlen + PPP_HDRLEN);
-	
-	UPAPDEBUG((LOG_INFO, "pap_sresp: Sent code %d, id %d s=%d\n", 
-				code, id, u->us_clientstate));
-}
-
-#if 0
-/*
- * upap_printpkt - print the contents of a PAP packet.
- */
-static int upap_printpkt(
-	u_char *p,
-	int plen,
-	void (*printer) (void *, char *, ...),
-	void *arg
-)
-{
-	(void)p;
-	(void)plen;
-	(void)printer;
-	(void)arg;
-	return 0;
-}
-#endif
-
-#endif /* PAP_SUPPORT */
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/pap.h b/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/pap.h
deleted file mode 100644
index 215c8a4f2..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/pap.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/*****************************************************************************
-* pap.h -  PPP Password Authentication Protocol header file.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* portions Copyright (c) 1997 Global Election Systems Inc.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY
-*
-* 03-01-01 Marc Boucher 
-*   Ported to lwIP.
-* 97-12-04 Guy Lancaster , Global Election Systems Inc.
-*	Original derived from BSD codes.
-*****************************************************************************/
-/*
- * upap.h - User/Password Authentication Protocol definitions.
- *
- * Copyright (c) 1989 Carnegie Mellon University.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by Carnegie Mellon University.  The name of the
- * University may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- */
-
-
-#ifndef PAP_H
-#define PAP_H
-
-/*************************
-*** PUBLIC DEFINITIONS ***
-*************************/
-/*
- * Packet header = Code, id, length.
- */
-#define UPAP_HEADERLEN	(sizeof (u_char) + sizeof (u_char) + sizeof (u_short))
-
-
-/*
- * UPAP codes.
- */
-#define UPAP_AUTHREQ	1	/* Authenticate-Request */
-#define UPAP_AUTHACK	2	/* Authenticate-Ack */
-#define UPAP_AUTHNAK	3	/* Authenticate-Nak */
-
-/*
- * Client states.
- */
-#define UPAPCS_INITIAL	0	/* Connection down */
-#define UPAPCS_CLOSED	1	/* Connection up, haven't requested auth */
-#define UPAPCS_PENDING	2	/* Connection down, have requested auth */
-#define UPAPCS_AUTHREQ	3	/* We've sent an Authenticate-Request */
-#define UPAPCS_OPEN		4	/* We've received an Ack */
-#define UPAPCS_BADAUTH	5	/* We've received a Nak */
-
-/*
- * Server states.
- */
-#define UPAPSS_INITIAL	0	/* Connection down */
-#define UPAPSS_CLOSED	1	/* Connection up, haven't requested auth */
-#define UPAPSS_PENDING	2	/* Connection down, have requested auth */
-#define UPAPSS_LISTEN	3	/* Listening for an Authenticate */
-#define UPAPSS_OPEN		4	/* We've sent an Ack */
-#define UPAPSS_BADAUTH	5	/* We've sent a Nak */
-
-
-/************************
-*** PUBLIC DATA TYPES ***
-************************/
-
-/*
- * Each interface is described by upap structure.
- */
-typedef struct upap_state {
-    int us_unit;			/* Interface unit number */
-    const char *us_user;	/* User */
-    int us_userlen;			/* User length */
-    const char *us_passwd;	/* Password */
-    int us_passwdlen;		/* Password length */
-    int us_clientstate;		/* Client state */
-    int us_serverstate;		/* Server state */
-    u_char us_id;			/* Current id */
-    int us_timeouttime;		/* Timeout (seconds) for auth-req retrans. */
-    int us_transmits;		/* Number of auth-reqs sent */
-    int us_maxtransmits;	/* Maximum number of auth-reqs to send */
-    int us_reqtimeout;		/* Time to wait for auth-req from peer */
-} upap_state;
-
-
-/***********************
-*** PUBLIC FUNCTIONS ***
-***********************/
-
-extern upap_state upap[];
-
-void upap_setloginpasswd(int unit, const char *luser, const char *lpassword);
-void upap_authwithpeer (int, char *, char *);
-void upap_authpeer (int);
-
-extern struct protent pap_protent;
-
-#endif /* PAP_H */
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/ppp.c b/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/ppp.c
deleted file mode 100644
index df402189e..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/ppp.c
+++ /dev/null
@@ -1,1623 +0,0 @@
-/*****************************************************************************
-* ppp.c - Network Point to Point Protocol program file.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* portions Copyright (c) 1997 by Global Election Systems Inc.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY
-*
-* 03-01-01 Marc Boucher 
-*   Ported to lwIP.
-* 97-11-05 Guy Lancaster , Global Election Systems Inc.
-*   Original.
-*****************************************************************************/
-
-/*
- * ppp_defs.h - PPP definitions.
- *
- * if_pppvar.h - private structures and declarations for PPP.
- *
- * Copyright (c) 1994 The Australian National University.
- * All rights reserved.
- *
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, provided that the above copyright
- * notice appears in all copies.  This software is provided without any
- * warranty, express or implied. The Australian National University
- * makes no representations about the suitability of this software for
- * any purpose.
- *
- * IN NO EVENT SHALL THE AUSTRALIAN NATIONAL UNIVERSITY BE LIABLE TO ANY
- * PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES
- * ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF
- * THE AUSTRALIAN NATIONAL UNIVERSITY HAVE BEEN ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * THE AUSTRALIAN NATIONAL UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
- * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
- * AND FITNESS FOR A PARTICULAR PURPOSE.  THE SOFTWARE PROVIDED HEREUNDER IS
- * ON AN "AS IS" BASIS, AND THE AUSTRALIAN NATIONAL UNIVERSITY HAS NO
- * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS,
- * OR MODIFICATIONS.
- */
-
-/*
- * if_ppp.h - Point-to-Point Protocol definitions.
- *
- * Copyright (c) 1989 Carnegie Mellon University.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by Carnegie Mellon University.  The name of the
- * University may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- */
- 
-#include 
- 
-#include "ppp.h"
-#if PPP_SUPPORT > 0
-#include "randm.h"
-#include "fsm.h"
-#if PAP_SUPPORT > 0
-#include "pap.h"
-#endif
-#if CHAP_SUPPORT > 0
-#include "chap.h"
-#endif
-#include "ipcp.h"
-#include "lcp.h"
-#include "magic.h"
-#include "auth.h"
-#if VJ_SUPPORT > 0
-#include "vj.h"
-#endif
-
-#include "pppdebug.h"
-
-/*************************/
-/*** LOCAL DEFINITIONS ***/
-/*************************/
-
-/*
- * The basic PPP frame.
- */
-#define PPP_ADDRESS(p)  (((u_char *)(p))[0])
-#define PPP_CONTROL(p)  (((u_char *)(p))[1])
-#define PPP_PROTOCOL(p) ((((u_char *)(p))[2] << 8) + ((u_char *)(p))[3])
-
-/* PPP packet parser states.  Current state indicates operation yet to be
- * completed. */
-typedef enum {
-    PDIDLE = 0,                 /* Idle state - waiting. */
-    PDSTART,                    /* Process start flag. */
-    PDADDRESS,                  /* Process address field. */
-    PDCONTROL,                  /* Process control field. */
-    PDPROTOCOL1,                /* Process protocol field 1. */
-    PDPROTOCOL2,                /* Process protocol field 2. */
-    PDDATA                      /* Process data byte. */
-} PPPDevStates;
-
-#define ESCAPE_P(accm, c) ((accm)[(c) >> 3] & pppACCMMask[c & 0x07])
-
-/************************/
-/*** LOCAL DATA TYPES ***/
-/************************/
-/*
- * PPP interface control block.
- */
-typedef struct PPPControl_s {
-    char openFlag;                      /* True when in use. */
-    char oldFrame;                      /* Old framing character for fd. */
-    sio_fd_t fd;                    /* File device ID of port. */
-    int  kill_link;                     /* Shut the link down. */
-    int  sig_hup;                       /* Carrier lost. */
-    int  if_up;                         /* True when the interface is up. */
-    int  errCode;                       /* Code indicating why interface is down. */
-    struct pbuf *inHead, *inTail;       /* The input packet. */
-    PPPDevStates inState;               /* The input process state. */
-    char inEscaped;                     /* Escape next character. */
-    u16_t inProtocol;                   /* The input protocol code. */
-    u16_t inFCS;                        /* Input Frame Check Sequence value. */
-    int  mtu;                           /* Peer's mru */
-    int  pcomp;                         /* Does peer accept protocol compression? */
-    int  accomp;                        /* Does peer accept addr/ctl compression? */
-    u_long lastXMit;                    /* Time of last transmission. */
-    ext_accm inACCM;                    /* Async-Ctl-Char-Map for input. */
-    ext_accm outACCM;                   /* Async-Ctl-Char-Map for output. */
-#if VJ_SUPPORT > 0
-    int  vjEnabled;                     /* Flag indicating VJ compression enabled. */
-    struct vjcompress vjComp;           /* Van Jabobsen compression header. */
-#endif
-
-    struct netif netif;
-
-    struct ppp_addrs addrs;
-
-    void (*linkStatusCB)(void *ctx, int errCode, void *arg);
-    void *linkStatusCtx;
-
-} PPPControl;
-
-
-/*
- * Ioctl definitions.
- */
-
-struct npioctl {
-    int     protocol;           /* PPP procotol, e.g. PPP_IP */
-    enum NPmode mode;
-};
-
-
-
-/***********************************/
-/*** LOCAL FUNCTION DECLARATIONS ***/
-/***********************************/
-static void pppMain(void *pd);
-static void pppDrop(PPPControl *pc);
-static void pppInProc(int pd, u_char *s, int l);
-
-
-/******************************/
-/*** PUBLIC DATA STRUCTURES ***/
-/******************************/
-u_long subnetMask;
-
-static PPPControl pppControl[NUM_PPP]; /* The PPP interface control blocks. */
-
-/*
- * PPP Data Link Layer "protocol" table.
- * One entry per supported protocol.
- * The last entry must be NULL.
- */
-struct protent *ppp_protocols[] = {
-    &lcp_protent,
-#if PAP_SUPPORT > 0
-    &pap_protent,
-#endif
-#if CHAP_SUPPORT > 0
-    &chap_protent,
-#endif
-#if CBCP_SUPPORT > 0
-    &cbcp_protent,
-#endif
-    &ipcp_protent,
-#if CCP_SUPPORT > 0
-    &ccp_protent,
-#endif
-    NULL
-};
-
-
-/*
- * Buffers for outgoing packets.  This must be accessed only from the appropriate
- * PPP task so that it doesn't need to be protected to avoid collisions.
- */
-u_char outpacket_buf[NUM_PPP][PPP_MRU+PPP_HDRLEN];  
-
-
-/*****************************/
-/*** LOCAL DATA STRUCTURES ***/
-/*****************************/
-
-/*
- * FCS lookup table as calculated by genfcstab.
- */
-static const u_short fcstab[256] = {
-    0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf,
-    0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7,
-    0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e,
-    0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876,
-    0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd,
-    0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5,
-    0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c,
-    0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974,
-    0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb,
-    0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3,
-    0x5285, 0x430c, 0x7197, 0x601e, 0x14a1, 0x0528, 0x37b3, 0x263a,
-    0xdecd, 0xcf44, 0xfddf, 0xec56, 0x98e9, 0x8960, 0xbbfb, 0xaa72,
-    0x6306, 0x728f, 0x4014, 0x519d, 0x2522, 0x34ab, 0x0630, 0x17b9,
-    0xef4e, 0xfec7, 0xcc5c, 0xddd5, 0xa96a, 0xb8e3, 0x8a78, 0x9bf1,
-    0x7387, 0x620e, 0x5095, 0x411c, 0x35a3, 0x242a, 0x16b1, 0x0738,
-    0xffcf, 0xee46, 0xdcdd, 0xcd54, 0xb9eb, 0xa862, 0x9af9, 0x8b70,
-    0x8408, 0x9581, 0xa71a, 0xb693, 0xc22c, 0xd3a5, 0xe13e, 0xf0b7,
-    0x0840, 0x19c9, 0x2b52, 0x3adb, 0x4e64, 0x5fed, 0x6d76, 0x7cff,
-    0x9489, 0x8500, 0xb79b, 0xa612, 0xd2ad, 0xc324, 0xf1bf, 0xe036,
-    0x18c1, 0x0948, 0x3bd3, 0x2a5a, 0x5ee5, 0x4f6c, 0x7df7, 0x6c7e,
-    0xa50a, 0xb483, 0x8618, 0x9791, 0xe32e, 0xf2a7, 0xc03c, 0xd1b5,
-    0x2942, 0x38cb, 0x0a50, 0x1bd9, 0x6f66, 0x7eef, 0x4c74, 0x5dfd,
-    0xb58b, 0xa402, 0x9699, 0x8710, 0xf3af, 0xe226, 0xd0bd, 0xc134,
-    0x39c3, 0x284a, 0x1ad1, 0x0b58, 0x7fe7, 0x6e6e, 0x5cf5, 0x4d7c,
-    0xc60c, 0xd785, 0xe51e, 0xf497, 0x8028, 0x91a1, 0xa33a, 0xb2b3,
-    0x4a44, 0x5bcd, 0x6956, 0x78df, 0x0c60, 0x1de9, 0x2f72, 0x3efb,
-    0xd68d, 0xc704, 0xf59f, 0xe416, 0x90a9, 0x8120, 0xb3bb, 0xa232,
-    0x5ac5, 0x4b4c, 0x79d7, 0x685e, 0x1ce1, 0x0d68, 0x3ff3, 0x2e7a,
-    0xe70e, 0xf687, 0xc41c, 0xd595, 0xa12a, 0xb0a3, 0x8238, 0x93b1,
-    0x6b46, 0x7acf, 0x4854, 0x59dd, 0x2d62, 0x3ceb, 0x0e70, 0x1ff9,
-    0xf78f, 0xe606, 0xd49d, 0xc514, 0xb1ab, 0xa022, 0x92b9, 0x8330,
-    0x7bc7, 0x6a4e, 0x58d5, 0x495c, 0x3de3, 0x2c6a, 0x1ef1, 0x0f78
-};
-
-/* PPP's Asynchronous-Control-Character-Map.  The mask array is used
- * to select the specific bit for a character. */
-static u_char pppACCMMask[] = {
-    0x01,
-    0x02,
-    0x04,
-    0x08,
-    0x10,
-    0x20,
-    0x40,
-    0x80
-};
-
-
-/***********************************/
-/*** PUBLIC FUNCTION DEFINITIONS ***/
-/***********************************/
-/* Initialize the PPP subsystem. */
-
-struct ppp_settings ppp_settings;
-
-void pppInit(void)
-{
-    struct protent *protp;
-    int i, j;
-    
-	memset(&ppp_settings, 0, sizeof(ppp_settings));
-	ppp_settings.usepeerdns = 1;
-	pppSetAuth(PPPAUTHTYPE_NONE, NULL, NULL);
-
-	magicInit();
-
-    for (i = 0; i < NUM_PPP; i++) {
-        pppControl[i].openFlag = 0;
-
-		subnetMask = htonl(0xffffff00);
-    
-        /*
-         * Initialize to the standard option set.
-         */
-        for (j = 0; (protp = ppp_protocols[j]) != NULL; ++j)
-            (*protp->init)(i);
-    }
-
-#if LINK_STATS
-    /* Clear the statistics. */
-    memset(&lwip_stats.link, 0, sizeof(lwip_stats.link));
-#endif
-}
-
-void pppSetAuth(enum pppAuthType authType, const char *user, const char *passwd)
-{
-    switch(authType) {
-	case PPPAUTHTYPE_NONE:
-	default:
-#ifdef LWIP_PPP_STRICT_PAP_REJECT
-	    ppp_settings.refuse_pap = 1;
-#else
-	    /* some providers request pap and accept an empty login/pw */
-	    ppp_settings.refuse_pap = 0;
-#endif
-	    ppp_settings.refuse_chap = 1;
-	    break;
-	case PPPAUTHTYPE_ANY:
-/* Warning: Using PPPAUTHTYPE_ANY might have security consequences.
- * RFC 1994 says:
- *
- * In practice, within or associated with each PPP server, there is a
- * database which associates "user" names with authentication
- * information ("secrets").  It is not anticipated that a particular
- * named user would be authenticated by multiple methods.  This would
- * make the user vulnerable to attacks which negotiate the least secure
- * method from among a set (such as PAP rather than CHAP).  If the same
- * secret was used, PAP would reveal the secret to be used later with
- * CHAP.
- *
- * Instead, for each user name there should be an indication of exactly
- * one method used to authenticate that user name.  If a user needs to
- * make use of different authentication methods under different
- * circumstances, then distinct user names SHOULD be employed, each of
- * which identifies exactly one authentication method.
- *
- */
-	    ppp_settings.refuse_pap = 0;
-	    ppp_settings.refuse_chap = 0;
-	    break;
-	case PPPAUTHTYPE_PAP:
-	    ppp_settings.refuse_pap = 0;
-	    ppp_settings.refuse_chap = 1;
-	    break;
-	case PPPAUTHTYPE_CHAP:
-	    ppp_settings.refuse_pap = 1;
-	    ppp_settings.refuse_chap = 0;
-	    break;
-    }
-
-    if(user) {
-	strncpy(ppp_settings.user, user, sizeof(ppp_settings.user)-1);
-	ppp_settings.user[sizeof(ppp_settings.user)-1] = '\0';
-    } else
-	ppp_settings.user[0] = '\0';
-
-    if(passwd) {
-	strncpy(ppp_settings.passwd, passwd, sizeof(ppp_settings.passwd)-1);
-	ppp_settings.passwd[sizeof(ppp_settings.passwd)-1] = '\0';
-    } else
-	ppp_settings.passwd[0] = '\0';
-}
-
-/* Open a new PPP connection using the given I/O device.
- * This initializes the PPP control block but does not
- * attempt to negotiate the LCP session.  If this port
- * connects to a modem, the modem connection must be
- * established before calling this.
- * Return a new PPP connection descriptor on success or
- * an error code (negative) on failure. */
-int pppOpen(sio_fd_t fd, void (*linkStatusCB)(void *ctx, int errCode, void *arg), void *linkStatusCtx)
-{
-    PPPControl *pc;
-    int pd;
-
-    /* Find a free PPP session descriptor. Critical region? */
-    for (pd = 0; pd < NUM_PPP && pppControl[pd].openFlag != 0; pd++);
-    if (pd >= NUM_PPP)
-        pd = PPPERR_OPEN;
-    else
-        pppControl[pd].openFlag = !0;
-
-    /* Launch a deamon thread. */
-    if (pd >= 0) {
-
-        pppControl[pd].openFlag = 1;
-
-        lcp_init(pd);
-        pc = &pppControl[pd];
-        pc->fd = fd;
-        pc->kill_link = 0;
-        pc->sig_hup = 0;
-        pc->if_up = 0;
-        pc->errCode = 0;
-        pc->inState = PDIDLE;
-        pc->inHead = NULL;
-        pc->inTail = NULL;
-        pc->inEscaped = 0;
-        pc->lastXMit = 0;
-
-#if VJ_SUPPORT > 0
-        pc->vjEnabled = 0;
-        vj_compress_init(&pc->vjComp);
-#endif
-
-        /* 
-         * Default the in and out accm so that escape and flag characters
-         * are always escaped. 
-         */
-        memset(pc->inACCM, 0, sizeof(ext_accm));
-        pc->inACCM[15] = 0x60;
-        memset(pc->outACCM, 0, sizeof(ext_accm));
-        pc->outACCM[15] = 0x60;
-
-	pc->linkStatusCB = linkStatusCB;
-	pc->linkStatusCtx = linkStatusCtx;
-
-	sys_thread_new(pppMain, (void*)pd, PPP_THREAD_PRIO);
-	if(!linkStatusCB) {
-		while(pd >= 0 && !pc->if_up) {
-			sys_msleep(500);
-			if (lcp_phase[pd] == PHASE_DEAD) {
-				pppClose(pd);
-				if (pc->errCode)
-					pd = pc->errCode;
-				else
-					pd = PPPERR_CONNECT;
-			}
-		}
-	}
-    }
-    return pd;
-}
-
-/* Close a PPP connection and release the descriptor. 
- * Any outstanding packets in the queues are dropped.
- * Return 0 on success, an error code on failure. */
-int pppClose(int pd)
-{
-    PPPControl *pc = &pppControl[pd];
-    int st = 0;
-
-    /* Disconnect */
-    pc->kill_link = !0;
-    pppMainWakeup(pd);
-    
-    if(!pc->linkStatusCB) {
-	    while(st >= 0 && lcp_phase[pd] != PHASE_DEAD) {
-		    sys_msleep(500);
-		    break;
-	    }
-    }
-    return st;
-}
-
-/* This function is called when carrier is lost on the PPP channel. */
-void pppSigHUP(int pd)
-{
-    PPPControl *pc = &pppControl[pd];
-
-    pc->sig_hup = 1;
-    pppMainWakeup(pd);
-}
-
-static void nPut(PPPControl *pc, struct pbuf *nb)
-{
-	struct pbuf *b;
-	int c;
-
-	for(b = nb; b != NULL; b = b->next) {
-	    if((c = sio_write(pc->fd, b->payload, b->len)) != b->len) {
-		PPPDEBUG((LOG_WARNING,
-			    "PPP nPut: incomplete sio_write(%d,, %u) = %d\n", pc->fd, b->len, c));
-#if LINK_STATS
-		lwip_stats.link.err++;
-#endif /* LINK_STATS */
-		pc->lastXMit = 0; /* prepend PPP_FLAG to next packet */
-		break;
-	    }
-	}
-	pbuf_free(nb);
-
-#if LINK_STATS
-	lwip_stats.link.xmit++;
-#endif /* LINK_STATS */
-}
-
-/* 
- * pppAppend - append given character to end of given pbuf.  If outACCM
- * is not NULL and the character needs to be escaped, do so.
- * If pbuf is full, append another.
- * Return the current pbuf.
- */
-static struct pbuf *pppAppend(u_char c, struct pbuf *nb, ext_accm *outACCM)
-{
-    struct pbuf *tb = nb;
-    
-    /* Make sure there is room for the character and an escape code.
-     * Sure we don't quite fill the buffer if the character doesn't
-     * get escaped but is one character worth complicating this? */
-    /* Note: We assume no packet header. */
-    if (nb && (PBUF_POOL_BUFSIZE - nb->len) < 2) {
-	tb = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL);
-	if (tb) {
-	    nb->next = tb;
-        }
-#if LINK_STATS
-	else {
-	    lwip_stats.link.memerr++;
-	}
-#endif /* LINK_STATS */
-	nb = tb;
-    }
-    if (nb) {
-	if (outACCM && ESCAPE_P(*outACCM, c)) {
-            *((u_char*)nb->payload + nb->len++) = PPP_ESCAPE;
-            *((u_char*)nb->payload + nb->len++) = c ^ PPP_TRANS;
-        }
-        else
-            *((u_char*)nb->payload + nb->len++) = c;
-    }
-        
-    return tb;
-}
-
-/* Send a packet on the given connection. */
-static err_t pppifOutput(struct netif *netif, struct pbuf *pb, struct ip_addr *ipaddr)
-{
-    int pd = (int)netif->state;
-    u_short protocol = PPP_IP;
-    PPPControl *pc = &pppControl[pd];
-    u_int fcsOut = PPP_INITFCS;
-    struct pbuf *headMB = NULL, *tailMB = NULL, *p;
-    u_char c;
-
-    (void)ipaddr;
-
-    /* Validate parameters. */
-    /* We let any protocol value go through - it can't hurt us
-     * and the peer will just drop it if it's not accepting it. */
-	if (pd < 0 || pd >= NUM_PPP || !pc->openFlag || !pb) {
-        PPPDEBUG((LOG_WARNING, "pppifOutput[%d]: bad parms prot=%d pb=%p\n",
-                    pd, protocol, pb));
-#if LINK_STATS
-		lwip_stats.link.opterr++;
-		lwip_stats.link.drop++;
-#endif
-		return ERR_ARG;
-	}
-
-    /* Check that the link is up. */
-	if (lcp_phase[pd] == PHASE_DEAD) {
-        PPPDEBUG((LOG_ERR, "pppifOutput[%d]: link not up\n", pd));
-#if LINK_STATS
-		lwip_stats.link.rterr++;
-		lwip_stats.link.drop++;
-#endif
-		return ERR_RTE;
-	}
-
-    /* Grab an output buffer. */
-	headMB = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL);
-    if (headMB == NULL) {
-        PPPDEBUG((LOG_WARNING, "pppifOutput[%d]: first alloc fail\n", pd));
-#if LINK_STATS
-		lwip_stats.link.memerr++;
-		lwip_stats.link.drop++;
-#endif /* LINK_STATS */
-        return ERR_MEM;
-    }
-        
-#if VJ_SUPPORT > 0
-    /* 
-     * Attempt Van Jacobson header compression if VJ is configured and
-     * this is an IP packet. 
-     */
-    if (protocol == PPP_IP && pc->vjEnabled) {
-        switch (vj_compress_tcp(&pc->vjComp, pb)) {
-        case TYPE_IP:
-            /* No change...
-            protocol = PPP_IP_PROTOCOL;
-             */
-            break;
-        case TYPE_COMPRESSED_TCP:
-            protocol = PPP_VJC_COMP;
-            break;
-        case TYPE_UNCOMPRESSED_TCP:
-            protocol = PPP_VJC_UNCOMP;
-            break;
-        default:
-            PPPDEBUG((LOG_WARNING, "pppifOutput[%d]: bad IP packet\n", pd));
-#if LINK_STATS
-			lwip_stats.link.proterr++;
-			lwip_stats.link.drop++;
-#endif
-        	pbuf_free(headMB);
-            return ERR_VAL;
-        }
-    }
-#endif
-        
-    tailMB = headMB;
-        
-    /* Build the PPP header. */
-    if ((sys_jiffies() - pc->lastXMit) >= PPP_MAXIDLEFLAG)
-        tailMB = pppAppend(PPP_FLAG, tailMB, NULL);
-    pc->lastXMit = sys_jiffies();
-    if (!pc->accomp) {
-        fcsOut = PPP_FCS(fcsOut, PPP_ALLSTATIONS);
-        tailMB = pppAppend(PPP_ALLSTATIONS, tailMB, &pc->outACCM);
-        fcsOut = PPP_FCS(fcsOut, PPP_UI);
-        tailMB = pppAppend(PPP_UI, tailMB, &pc->outACCM);
-    }
-    if (!pc->pcomp || protocol > 0xFF) {
-        c = (protocol >> 8) & 0xFF;
-        fcsOut = PPP_FCS(fcsOut, c);
-        tailMB = pppAppend(c, tailMB, &pc->outACCM);
-    }
-    c = protocol & 0xFF;
-    fcsOut = PPP_FCS(fcsOut, c);
-    tailMB = pppAppend(c, tailMB, &pc->outACCM);
-    
-    /* Load packet. */
-	for(p = pb; p; p = p->next) {
-    	int n;
-    	u_char *sPtr;
-
-        sPtr = (u_char*)p->payload;
-        n = p->len;
-        while (n-- > 0) {
-            c = *sPtr++;
-            
-            /* Update FCS before checking for special characters. */
-            fcsOut = PPP_FCS(fcsOut, c);
-            
-            /* Copy to output buffer escaping special characters. */
-            tailMB = pppAppend(c, tailMB, &pc->outACCM);
-        }
-    }
-
-    /* Add FCS and trailing flag. */
-    c = ~fcsOut & 0xFF;
-    tailMB = pppAppend(c, tailMB, &pc->outACCM);
-    c = (~fcsOut >> 8) & 0xFF;
-    tailMB = pppAppend(c, tailMB, &pc->outACCM);
-    tailMB = pppAppend(PPP_FLAG, tailMB, NULL);
-        
-    /* If we failed to complete the packet, throw it away. */
-    if (!tailMB) {
-        PPPDEBUG((LOG_WARNING,
-                    "pppifOutput[%d]: Alloc err - dropping proto=%d\n", 
-                    pd, protocol));
-        pbuf_free(headMB);
-#if LINK_STATS
-		lwip_stats.link.memerr++;
-		lwip_stats.link.drop++;
-#endif
-        return ERR_MEM;
-    }
-
-	/* Send it. */
-    PPPDEBUG((LOG_INFO, "pppifOutput[%d]: proto=0x%04X\n", pd, protocol));
-
-    nPut(pc, headMB);
-
-    return ERR_OK;
-}
-
-/* Get and set parameters for the given connection.
- * Return 0 on success, an error code on failure. */
-int  pppIOCtl(int pd, int cmd, void *arg)
-{
-    PPPControl *pc = &pppControl[pd];
-    int st = 0;
-
-    if (pd < 0 || pd >= NUM_PPP)
-        st = PPPERR_PARAM;
-    else {
-        switch(cmd) {
-        case PPPCTLG_UPSTATUS:      /* Get the PPP up status. */
-            if (arg) 
-                *(int *)arg = (int)(pc->if_up);
-            else
-                st = PPPERR_PARAM;
-            break;
-        case PPPCTLS_ERRCODE:       /* Set the PPP error code. */
-            if (arg) 
-                pc->errCode = *(int *)arg;
-            else
-                st = PPPERR_PARAM;
-            break;
-        case PPPCTLG_ERRCODE:       /* Get the PPP error code. */
-            if (arg) 
-                *(int *)arg = (int)(pc->errCode);
-            else
-                st = PPPERR_PARAM;
-            break;
-        case PPPCTLG_FD:
-            if (arg) 
-                *(sio_fd_t *)arg = pc->fd;
-            else
-                st = PPPERR_PARAM;
-            break;
-        default:
-            st = PPPERR_PARAM;
-            break;
-        }
-    }
-    
-    return st;
-}
-
-/*
- * Return the Maximum Transmission Unit for the given PPP connection.
- */
-u_int pppMTU(int pd)
-{
-    PPPControl *pc = &pppControl[pd];
-    u_int st;
-    
-    /* Validate parameters. */
-    if (pd < 0 || pd >= NUM_PPP || !pc->openFlag)
-        st = 0;
-    else
-        st = pc->mtu;
-        
-    return st;
-}
-
-/*
- * Write n characters to a ppp link.
- *  RETURN: >= 0 Number of characters written
- *           -1 Failed to write to device
- */
-int pppWrite(int pd, const u_char *s, int n)
-{
-    PPPControl *pc = &pppControl[pd];
-    u_char c;
-    u_int fcsOut = PPP_INITFCS;
-    struct pbuf *headMB = NULL, *tailMB;
-	headMB = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL);
-    if (headMB == NULL) {
-#if LINK_STATS
-		lwip_stats.link.memerr++;
-		lwip_stats.link.proterr++;
-#endif /* LINK_STATS */
-		return PPPERR_ALLOC;
-    }
-
-    tailMB = headMB;
-        
-    /* If the link has been idle, we'll send a fresh flag character to
-     * flush any noise. */
-    if ((sys_jiffies() - pc->lastXMit) >= PPP_MAXIDLEFLAG)
-        tailMB = pppAppend(PPP_FLAG, tailMB, NULL);
-    pc->lastXMit = sys_jiffies();
-     
-    /* Load output buffer. */
-    while (n-- > 0) {
-        c = *s++;
-        
-        /* Update FCS before checking for special characters. */
-        fcsOut = PPP_FCS(fcsOut, c);
-        
-        /* Copy to output buffer escaping special characters. */
-        tailMB = pppAppend(c, tailMB, &pc->outACCM);
-    }
-    
-    /* Add FCS and trailing flag. */
-    c = ~fcsOut & 0xFF;
-    tailMB = pppAppend(c, tailMB, &pc->outACCM);
-    c = (~fcsOut >> 8) & 0xFF;
-    tailMB = pppAppend(c, tailMB, &pc->outACCM);
-    tailMB = pppAppend(PPP_FLAG, tailMB, NULL);
-        
-    /* If we failed to complete the packet, throw it away.
-     * Otherwise send it. */
-    if (!tailMB) {
-		PPPDEBUG((LOG_WARNING,
-                "pppWrite[%d]: Alloc err - dropping pbuf len=%d\n", pd, headMB->len));
-/*                "pppWrite[%d]: Alloc err - dropping %d:%.*H", pd, headMB->len, LWIP_MIN(headMB->len * 2, 40), headMB->payload)); */
-		pbuf_free(headMB);
-#if LINK_STATS
-		lwip_stats.link.memerr++;
-		lwip_stats.link.proterr++;
-#endif /* LINK_STATS */
-		return PPPERR_ALLOC;
-	}
-
-    PPPDEBUG((LOG_INFO, "pppWrite[%d]: len=%d\n", pd, headMB->len));
-/*     "pppWrite[%d]: %d:%.*H", pd, headMB->len, LWIP_MIN(headMB->len * 2, 40), headMB->payload)); */
-    nPut(pc, headMB);
-
-    return PPPERR_NONE;
-}
-
-/*
- * ppp_send_config - configure the transmit characteristics of
- * the ppp interface.
- */
-void ppp_send_config(
-    int unit, 
-    int mtu,
-    u32_t asyncmap,
-    int pcomp, 
-    int accomp
-)
-{
-    PPPControl *pc = &pppControl[unit];
-    int i;
-    
-    pc->mtu = mtu;
-    pc->pcomp = pcomp;
-    pc->accomp = accomp;
-    
-    /* Load the ACCM bits for the 32 control codes. */
-    for (i = 0; i < 32/8; i++)
-        pc->outACCM[i] = (u_char)((asyncmap >> (8 * i)) & 0xFF);
-    PPPDEBUG((LOG_INFO, "ppp_send_config[%d]: outACCM=%X %X %X %X\n",
-                unit,
-                pc->outACCM[0], pc->outACCM[1], pc->outACCM[2], pc->outACCM[3]));
-}
-
-
-/*
- * ppp_set_xaccm - set the extended transmit ACCM for the interface.
- */
-void ppp_set_xaccm(int unit, ext_accm *accm)
-{
-    memcpy(pppControl[unit].outACCM, accm, sizeof(ext_accm));
-    PPPDEBUG((LOG_INFO, "ppp_set_xaccm[%d]: outACCM=%X %X %X %X\n",
-                unit,
-                pppControl[unit].outACCM[0],
-                pppControl[unit].outACCM[1],
-                pppControl[unit].outACCM[2],
-                pppControl[unit].outACCM[3]));
-}
-
-
-/*
- * ppp_recv_config - configure the receive-side characteristics of
- * the ppp interface.
- */
-void ppp_recv_config(
-    int unit, 
-    int mru,
-    u32_t asyncmap,
-    int pcomp, 
-    int accomp
-)
-{
-    PPPControl *pc = &pppControl[unit];
-    int i;
-    
-	(void)accomp;
-	(void)pcomp;
-	(void)mru;
-
-    /* Load the ACCM bits for the 32 control codes. */
-    for (i = 0; i < 32 / 8; i++)
-        pc->inACCM[i] = (u_char)(asyncmap >> (i * 8));
-    PPPDEBUG((LOG_INFO, "ppp_recv_config[%d]: inACCM=%X %X %X %X\n",
-                unit,
-                pc->inACCM[0], pc->inACCM[1], pc->inACCM[2], pc->inACCM[3]));
-}
-
-#if 0
-/*
- * ccp_test - ask kernel whether a given compression method
- * is acceptable for use.  Returns 1 if the method and parameters
- * are OK, 0 if the method is known but the parameters are not OK
- * (e.g. code size should be reduced), or -1 if the method is unknown.
- */
-int ccp_test(
-    int unit, 
-    int opt_len, 
-    int for_transmit,
-    u_char *opt_ptr
-)
-{
-    return 0;   /* XXX Currently no compression. */
-}
-
-/*
- * ccp_flags_set - inform kernel about the current state of CCP.
- */
-void ccp_flags_set(int unit, int isopen, int isup)
-{
-    /* XXX */
-}
-
-/*
- * ccp_fatal_error - returns 1 if decompression was disabled as a
- * result of an error detected after decompression of a packet,
- * 0 otherwise.  This is necessary because of patent nonsense.
- */
-int ccp_fatal_error(int unit)
-{
-    /* XXX */
-    return 0;
-}
-#endif
-
-/*
- * get_idle_time - return how long the link has been idle.
- */
-int get_idle_time(int u, struct ppp_idle *ip)
-{   
-    /* XXX */
-	(void)u;
-	(void)ip;
-
-    return 0;
-}
-
-
-/*
- * Return user specified netmask, modified by any mask we might determine
- * for address `addr' (in network byte order).
- * Here we scan through the system's list of interfaces, looking for
- * any non-point-to-point interfaces which might appear to be on the same
- * network as `addr'.  If we find any, we OR in their netmask to the
- * user-specified netmask.
- */
-u32_t GetMask(u32_t addr)
-{
-    u32_t mask, nmask;
-    
-    htonl(addr);
-    if (IN_CLASSA(addr))    /* determine network mask for address class */
-        nmask = IN_CLASSA_NET;
-    else if (IN_CLASSB(addr))
-        nmask = IN_CLASSB_NET;
-    else
-        nmask = IN_CLASSC_NET;
-    /* class D nets are disallowed by bad_ip_adrs */
-    mask = subnetMask | htonl(nmask);
-    
-    /* XXX
-     * Scan through the system's network interfaces.
-     * Get each netmask and OR them into our mask.
-     */
-    
-    return mask;
-}
-
-/*
- * sifvjcomp - config tcp header compression
- */
-int sifvjcomp(
-    int pd, 
-    int vjcomp, 
-    int cidcomp, 
-    int maxcid
-)
-{
-#if VJ_SUPPORT > 0
-    PPPControl *pc = &pppControl[pd];
-    
-    pc->vjEnabled = vjcomp;
-    pc->vjComp.compressSlot = cidcomp;
-    pc->vjComp.maxSlotIndex = maxcid;
-    PPPDEBUG((LOG_INFO, "sifvjcomp: VJ compress enable=%d slot=%d max slot=%d\n",
-                vjcomp, cidcomp, maxcid));
-#endif
-
-    return 0;
-}
-
-/*
- * pppifNetifInit - netif init callback
- */
-static err_t pppifNetifInit(struct netif *netif)
-{
-	netif->name[0] = 'p';
-	netif->name[1] = 'p';
-	netif->output = pppifOutput;
-	netif->mtu = pppMTU((int)netif->state);
-	return ERR_OK;
-}
-
-
-/*
- * sifup - Config the interface up and enable IP packets to pass.
- */
-int sifup(int pd)
-{
-    PPPControl *pc = &pppControl[pd];
-    int st = 1;
-    
-    if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
-        st = 0;
-        PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd));
-    } else {
-		netif_remove(&pc->netif);
-		if (netif_add(&pc->netif, &pc->addrs.our_ipaddr, &pc->addrs.netmask, &pc->addrs.his_ipaddr, (void *)pd, pppifNetifInit, ip_input)) {
-        		pc->if_up = 1;
-        		pc->errCode = PPPERR_NONE;
-
-			PPPDEBUG((LOG_DEBUG, "sifup: unit %d: linkStatusCB=%lx errCode=%d\n", pd, pc->linkStatusCB, pc->errCode));
-			if(pc->linkStatusCB)
-				pc->linkStatusCB(pc->linkStatusCtx, pc->errCode, &pc->addrs);
-		} else {
-        	st = 0;
-        	PPPDEBUG((LOG_ERR, "sifup[%d]: netif_add failed\n", pd));
-		}
-    }
-
-    return st;
-}
-
-/*
- * sifnpmode - Set the mode for handling packets for a given NP.
- */
-int sifnpmode(int u, int proto, enum NPmode mode)
-{
-	(void)u;
-	(void)proto;
-	(void)mode;
-    return 0;
-}
-
-/*
- * sifdown - Config the interface down and disable IP.
- */
-int sifdown(int pd)
-{
-    PPPControl *pc = &pppControl[pd];
-    int st = 1;
-    
-    if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
-        st = 0;
-        PPPDEBUG((LOG_WARNING, "sifdown[%d]: bad parms\n", pd));
-    } else {
-        pc->if_up = 0;
-	netif_remove(&pc->netif);
-	PPPDEBUG((LOG_DEBUG, "sifdown: unit %d: linkStatusCB=%lx errCode=%d\n", pd, pc->linkStatusCB, pc->errCode));
-	if(pc->linkStatusCB)
-		pc->linkStatusCB(pc->linkStatusCtx, PPPERR_CONNECT, NULL);
-	}
-    return st;
-}
-
-/*
- * sifaddr - Config the interface IP addresses and netmask.
- */
-int sifaddr(
-    int pd,             /* Interface unit ??? */
-    u32_t o,        /* Our IP address ??? */
-    u32_t h,        /* His IP address ??? */
-    u32_t m,        /* IP subnet mask ??? */
-    u32_t ns1,      /* Primary DNS */
-    u32_t ns2       /* Secondary DNS */
-)
-{
-    PPPControl *pc = &pppControl[pd];
-    int st = 1;
-    
-    if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
-        st = 0;
-        PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd));
-    } else {
-		memcpy(&pc->addrs.our_ipaddr, &o, sizeof(o));
-		memcpy(&pc->addrs.his_ipaddr, &h, sizeof(h));
-		memcpy(&pc->addrs.netmask, &m, sizeof(m));
-		memcpy(&pc->addrs.dns1, &ns1, sizeof(ns1));
-		memcpy(&pc->addrs.dns2, &ns2, sizeof(ns2));
-    }
-    return st;
-}
-
-/*
- * cifaddr - Clear the interface IP addresses, and delete routes
- * through the interface if possible.
- */
-int cifaddr(
-    int pd,         /* Interface unit ??? */
-    u32_t o,    /* Our IP address ??? */
-    u32_t h     /* IP broadcast address ??? */
-)
-{
-    PPPControl *pc = &pppControl[pd];
-    int st = 1;
-    
-	(void)o;
-	(void)h;
-    if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
-        st = 0;
-        PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd));
-    } else {
-		IP4_ADDR(&pc->addrs.our_ipaddr, 0,0,0,0);
-		IP4_ADDR(&pc->addrs.his_ipaddr, 0,0,0,0);
-		IP4_ADDR(&pc->addrs.netmask, 255,255,255,0);
-		IP4_ADDR(&pc->addrs.dns1, 0,0,0,0);
-		IP4_ADDR(&pc->addrs.dns2, 0,0,0,0);
-    }
-    return st;
-}
-
-/*
- * sifdefaultroute - assign a default route through the address given.
- */
-int sifdefaultroute(int pd, u32_t l, u32_t g)
-{
-    PPPControl *pc = &pppControl[pd];
-    int st = 1;
-    
-	(void)l;
-	(void)g;
-    if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
-        st = 0;
-        PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd));
-    } else {
-		netif_set_default(&pc->netif);
-    }
-
-    /* TODO: check how PPP handled the netMask, previously not set by ipSetDefault */
-
-    return st;
-}
-
-/*
- * cifdefaultroute - delete a default route through the address given.
- */
-int cifdefaultroute(int pd, u32_t l, u32_t g)
-{
-    PPPControl *pc = &pppControl[pd];
-    int st = 1;
-    
-	(void)l;
-	(void)g;
-    if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) {
-        st = 0;
-        PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd));
-    } else {
-		netif_set_default(NULL);
-    }
-
-    return st;
-}
-
-void
-pppMainWakeup(int pd)
-{
-	PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d\n", pd));
-	sio_read_abort(pppControl[pd].fd);
-}
-
-/* these callbacks are necessary because lcp_* functions
-   must be called in the same context as pppInput(),
-   namely the tcpip_thread(), essentially because
-   they manipulate timeouts which are thread-private
-*/
-
-static void
-pppStartCB(void *arg)
-{
-    int pd = (int)arg;
-
-	PPPDEBUG((LOG_DEBUG, "pppStartCB: unit %d\n", pd));
-    lcp_lowerup(pd);
-    lcp_open(pd);      /* Start protocol */
-}
-
-static void
-pppStopCB(void *arg)
-{
-    int pd = (int)arg;
-
-	PPPDEBUG((LOG_DEBUG, "pppStopCB: unit %d\n", pd));
-    lcp_close(pd, "User request");
-}
-
-static void
-pppHupCB(void *arg)
-{
-    int pd = (int)arg;
-
-	PPPDEBUG((LOG_DEBUG, "pppHupCB: unit %d\n", pd));
-    lcp_lowerdown(pd);
-    link_terminated(pd);
-}
-/**********************************/
-/*** LOCAL FUNCTION DEFINITIONS ***/
-/**********************************/
-/* The main PPP process function.  This implements the state machine according
- * to section 4 of RFC 1661: The Point-To-Point Protocol. */
-static void pppMain(void *arg)
-{
-    int pd = (int)arg;
-    struct pbuf *p;
-    PPPControl* pc;
-
-    pc = &pppControl[pd];
-
-    p = pbuf_alloc(PBUF_RAW, PPP_MRU+PPP_HDRLEN, PBUF_RAM);
-    if(!p) {
-		LWIP_ASSERT("p != NULL", p);
-		pc->errCode = PPPERR_ALLOC;
-		goto out;
-    }
-
-    /*
-     * Start the connection and handle incoming events (packet or timeout).
-     */
-	PPPDEBUG((LOG_INFO, "pppMain: unit %d: Connecting\n", pd));
-    tcpip_callback(pppStartCB, arg);
-    while (lcp_phase[pd] != PHASE_DEAD) {
-        if (pc->kill_link) {
-	    	PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d kill_link -> pppStopCB\n", pd));
-		pc->errCode = PPPERR_USER;
-		/* This will leave us at PHASE_DEAD. */
-    		tcpip_callback(pppStopCB, arg);
-		pc->kill_link = 0;
-        }
-        else if (pc->sig_hup) {
-	    	PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d sig_hup -> pppHupCB\n", pd));
-		pc->sig_hup = 0;
-    		tcpip_callback(pppHupCB, arg);
-        } else {
-		int c = sio_read(pc->fd, p->payload, p->len);
-		if(c > 0) {
-			pppInProc(pd, p->payload, c);
-		} else {
-		    PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d sio_read len=%d returned %d\n", pd, p->len, c));
-		    sys_msleep(1); /* give other tasks a chance to run */
-		}
-        }
-    }
-	PPPDEBUG((LOG_INFO, "pppMain: unit %d: PHASE_DEAD\n", pd));
-    pbuf_free(p);
-
-out:
-	PPPDEBUG((LOG_DEBUG, "pppMain: unit %d: linkStatusCB=%lx errCode=%d\n", pd, pc->linkStatusCB, pc->errCode));
-    if(pc->linkStatusCB)
-	    pc->linkStatusCB(pc->linkStatusCtx, pc->errCode ? pc->errCode : PPPERR_PROTOCOL, NULL);
-
-    pc->openFlag = 0;
-}
-
-static struct pbuf *pppSingleBuf(struct pbuf *p)
-{
-	struct pbuf *q, *b;
-	u_char *pl;
-
-	if(p->tot_len == p->len)
-		return p;
-
-	q = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM);
-	if(!q) {
-		PPPDEBUG((LOG_ERR,
-                        "pppSingleBuf: unable to alloc new buf (%d)\n", p->tot_len));
-		return p; /* live dangerously */
-	}
-
-	for(b = p, pl = q->payload; b != NULL; b = b->next) {
-		memcpy(pl, b->payload, b->len);
-		pl += b->len;
-	}
-
-	pbuf_free(p);
-
-	return q;
-}
-
-struct pppInputHeader {
-	int unit;
-	u16_t proto;
-};
-
-/*
- * Pass the processed input packet to the appropriate handler.
- * This function and all handlers run in the context of the tcpip_thread
- */
-static void pppInput(void *arg)
-{
-	struct pbuf *nb = (struct pbuf *)arg;
-    u16_t protocol;
-    int pd;
-
-	pd = ((struct pppInputHeader *)nb->payload)->unit;
-	protocol = ((struct pppInputHeader *)nb->payload)->proto;
-
-    pbuf_header(nb, -(int)sizeof(struct pppInputHeader));
-
-#if LINK_STATS
-    lwip_stats.link.recv++;
-#endif /* LINK_STATS */
-
-    /*
-     * Toss all non-LCP packets unless LCP is OPEN.
-     * Until we get past the authentication phase, toss all packets
-     * except LCP, LQR and authentication packets.
-     */
-    if((lcp_phase[pd] <= PHASE_AUTHENTICATE) && (protocol != PPP_LCP)) {
-	    if(!((protocol == PPP_LQR) || (protocol == PPP_PAP) || (protocol == PPP_CHAP)) ||
-			(lcp_phase[pd] != PHASE_AUTHENTICATE)) {
-		PPPDEBUG((LOG_INFO, "pppInput: discarding proto 0x%04X in phase %d\n", protocol, lcp_phase[pd]));
-		goto drop;
-	    }
-    }
-
-    switch(protocol) {
-    case PPP_VJC_COMP:      /* VJ compressed TCP */
-#if VJ_SUPPORT > 0
-        PPPDEBUG((LOG_INFO, "pppInput[%d]: vj_comp in pbuf len=%d\n", pd, nb->len));
-        /*
-         * Clip off the VJ header and prepend the rebuilt TCP/IP header and
-         * pass the result to IP.
-         */
-        if (vj_uncompress_tcp(&nb, &pppControl[pd].vjComp) >= 0) {
-            pppControl[pd].netif.input(nb, &pppControl[pd].netif);
-			return;
-        }
-	/* Something's wrong so drop it. */
-	PPPDEBUG((LOG_WARNING, "pppInput[%d]: Dropping VJ compressed\n", pd));
-#else
-        /* No handler for this protocol so drop the packet. */
-        PPPDEBUG((LOG_INFO, "pppInput[%d]: drop VJ Comp in %d:%s\n", pd, nb->len, nb->payload));
-#endif /* VJ_SUPPORT > 0 */
-	break;
-    case PPP_VJC_UNCOMP:    /* VJ uncompressed TCP */
-#if VJ_SUPPORT > 0
-        PPPDEBUG((LOG_INFO, "pppInput[%d]: vj_un in pbuf len=%d\n", pd, nb->len));
-        /*
-         * Process the TCP/IP header for VJ header compression and then pass
-         * the packet to IP.
-         */
-        if (vj_uncompress_uncomp(nb, &pppControl[pd].vjComp) >= 0) {
-            pppControl[pd].netif.input(nb, &pppControl[pd].netif);
-			return;
-        }
-	/* Something's wrong so drop it. */
-	PPPDEBUG((LOG_WARNING, "pppInput[%d]: Dropping VJ uncompressed\n", pd));
-#else
-        /* No handler for this protocol so drop the packet. */
-        PPPDEBUG((LOG_INFO,
-                    "pppInput[%d]: drop VJ UnComp in %d:.*H\n", 
-                    pd, nb->len, LWIP_MIN(nb->len * 2, 40), nb->payload));
-#endif /* VJ_SUPPORT > 0 */
-	break;
-    case PPP_IP:            /* Internet Protocol */
-        PPPDEBUG((LOG_INFO, "pppInput[%d]: ip in pbuf len=%d\n", pd, nb->len));
-        pppControl[pd].netif.input(nb, &pppControl[pd].netif);
-		return;
-    default:
-	{
-		struct protent *protp;
-		int i;
-
-		/*
-		 * Upcall the proper protocol input routine.
-		 */
-		for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) {
-			if (protp->protocol == protocol && protp->enabled_flag) {
-				PPPDEBUG((LOG_INFO, "pppInput[%d]: %s len=%d\n", pd, protp->name, nb->len));
-				nb = pppSingleBuf(nb);
-				(*protp->input)(pd, nb->payload, nb->len);
-				goto out;
-			}
-		}
-
-		/* No handler for this protocol so reject the packet. */
-		PPPDEBUG((LOG_INFO, "pppInput[%d]: rejecting unsupported proto 0x%04X len=%d\n", pd, protocol, nb->len));
-		pbuf_header(nb, sizeof(protocol));
-#if BYTE_ORDER == LITTLE_ENDIAN
-		protocol = htons(protocol);
-		memcpy(nb->payload, &protocol, sizeof(protocol));
-#endif
-		lcp_sprotrej(pd, nb->payload, nb->len);
-	}
-	break;
-    }
-
-drop:
-#if LINK_STATS
-    lwip_stats.link.drop++;
-#endif
-
-out:
-    pbuf_free(nb);
-    return;
-}
-
-
-/*
- * Drop the input packet.
- */
-static void pppDrop(PPPControl *pc)
-{
-    if (pc->inHead != NULL) {
-#if 0	    
-        PPPDEBUG((LOG_INFO, "pppDrop: %d:%.*H\n", pc->inHead->len, min(60, pc->inHead->len * 2), pc->inHead->payload));
-#endif	
-        PPPDEBUG((LOG_INFO, "pppDrop: pbuf len=%d\n", pc->inHead->len));
-	if (pc->inTail && (pc->inTail != pc->inHead))
-	    pbuf_free(pc->inTail);
-        pbuf_free(pc->inHead);
-        pc->inHead = NULL;
-        pc->inTail = NULL;
-    }
-#if VJ_SUPPORT > 0
-    vj_uncompress_err(&pc->vjComp);
-#endif
-
-#if LINK_STATS
-    lwip_stats.link.drop++;
-#endif /* LINK_STATS */
-}
-
-
-/*
- * Process a received octet string.
- */
-static void pppInProc(int pd, u_char *s, int l)
-{
-    PPPControl *pc = &pppControl[pd];
-    struct pbuf *nextNBuf;
-    u_char curChar;
-
-    PPPDEBUG((LOG_DEBUG, "pppInProc[%d]: got %d bytes\n", pd, l));
-    while (l-- > 0) {
-        curChar = *s++;
-        
-        /* Handle special characters. */
-        if (ESCAPE_P(pc->inACCM, curChar)) {
-            /* Check for escape sequences. */
-            /* XXX Note that this does not handle an escaped 0x5d character which
-             * would appear as an escape character.  Since this is an ASCII ']'
-             * and there is no reason that I know of to escape it, I won't complicate
-             * the code to handle this case. GLL */
-            if (curChar == PPP_ESCAPE)
-                pc->inEscaped = 1;
-            /* Check for the flag character. */
-            else if (curChar == PPP_FLAG) {
-                /* If this is just an extra flag character, ignore it. */
-                if (pc->inState <= PDADDRESS)
-                    ;
-                /* If we haven't received the packet header, drop what has come in. */
-                else if (pc->inState < PDDATA) {
-                    PPPDEBUG((LOG_WARNING,
-                                "pppInProc[%d]: Dropping incomplete packet %d\n", 
-                                pd, pc->inState));
-#if LINK_STATS
-					lwip_stats.link.lenerr++;
-#endif
-                    pppDrop(pc);
-                }
-                /* If the fcs is invalid, drop the packet. */
-                else if (pc->inFCS != PPP_GOODFCS) {
-                    PPPDEBUG((LOG_INFO,
-                                "pppInProc[%d]: Dropping bad fcs 0x%04X proto=0x%04X\n", 
-                                pd, pc->inFCS, pc->inProtocol));
-#if LINK_STATS
-					lwip_stats.link.chkerr++;
-#endif
-                    pppDrop(pc);
-                }
-                /* Otherwise it's a good packet so pass it on. */
-                else {
-                    
-                    /* Trim off the checksum. */
-		    if(pc->inTail->len >= 2) {
-			pc->inTail->len -= 2;
-
-			pc->inTail->tot_len = pc->inTail->len;
-			if (pc->inTail != pc->inHead) {
-			    pbuf_cat(pc->inHead, pc->inTail);
-			}
-		    } else {
-			pc->inTail->tot_len = pc->inTail->len;
-			if (pc->inTail != pc->inHead) {
-			    pbuf_cat(pc->inHead, pc->inTail);
-			}
-
-			pbuf_realloc(pc->inHead, pc->inHead->tot_len - 2);
-		    }
-
-                    /* Dispatch the packet thereby consuming it. */
-		    if(tcpip_callback(pppInput, pc->inHead) != ERR_OK) {
-                    	PPPDEBUG((LOG_ERR,
-				    "pppInProc[%d]: tcpip_callback() failed, dropping packet\n", pd));
-			pbuf_free(pc->inHead);
-#if LINK_STATS
-			lwip_stats.link.drop++;
-#endif
-		    }
-                    pc->inHead = NULL;
-                    pc->inTail = NULL;
-                }
-                    
-                /* Prepare for a new packet. */
-                pc->inFCS = PPP_INITFCS;
-                pc->inState = PDADDRESS;
-                pc->inEscaped = 0;
-            }
-            /* Other characters are usually control characters that may have
-             * been inserted by the physical layer so here we just drop them. */
-            else {
-                PPPDEBUG((LOG_WARNING,
-                            "pppInProc[%d]: Dropping ACCM char <%d>\n", pd, curChar));
-            }
-        }
-        /* Process other characters. */
-        else {
-            /* Unencode escaped characters. */
-            if (pc->inEscaped) {
-                pc->inEscaped = 0;
-                curChar ^= PPP_TRANS;
-            }
-            
-            /* Process character relative to current state. */
-            switch(pc->inState) {
-            case PDIDLE:                    /* Idle state - waiting. */
-                /* Drop the character if it's not 0xff
-                 * we would have processed a flag character above. */
-                if (curChar != PPP_ALLSTATIONS) {
-                	break;
-				}
-
-				/* Fall through */
-            case PDSTART:                   /* Process start flag. */
-                /* Prepare for a new packet. */
-                pc->inFCS = PPP_INITFCS;
-
-				/* Fall through */
-            case PDADDRESS:                 /* Process address field. */
-                if (curChar == PPP_ALLSTATIONS) {
-                    pc->inState = PDCONTROL;
-                    break;
-                }
-                /* Else assume compressed address and control fields so
-                 * fall through to get the protocol... */
-            case PDCONTROL:                 /* Process control field. */
-                /* If we don't get a valid control code, restart. */
-                if (curChar == PPP_UI) {
-                    pc->inState = PDPROTOCOL1;
-                	break;
-                }
-#if 0
-                else {
-                    PPPDEBUG((LOG_WARNING,
-                                "pppInProc[%d]: Invalid control <%d>\n", pd, curChar));
-                    pc->inState = PDSTART;
-                }
-#endif
-            case PDPROTOCOL1:               /* Process protocol field 1. */
-                /* If the lower bit is set, this is the end of the protocol
-                 * field. */
-                if (curChar & 1) {
-                    pc->inProtocol = curChar;
-                    pc->inState = PDDATA;
-                }
-                else {
-                    pc->inProtocol = (u_int)curChar << 8;
-                    pc->inState = PDPROTOCOL2;
-                }
-                break;
-            case PDPROTOCOL2:               /* Process protocol field 2. */
-                pc->inProtocol |= curChar;
-                pc->inState = PDDATA;
-                break;
-            case PDDATA:                    /* Process data byte. */
-                /* Make space to receive processed data. */
-                if (pc->inTail == NULL || pc->inTail->len == PBUF_POOL_BUFSIZE) {
-		    if(pc->inTail) {
-			pc->inTail->tot_len = pc->inTail->len;
-			if (pc->inTail != pc->inHead) {
-			    pbuf_cat(pc->inHead, pc->inTail);
-			}
-		    }
-                    /* If we haven't started a packet, we need a packet header. */
-                    nextNBuf = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL);
-                    if (nextNBuf == NULL) {
-                        /* No free buffers.  Drop the input packet and let the
-                         * higher layers deal with it.  Continue processing
-                         * the received pbuf chain in case a new packet starts. */
-                        PPPDEBUG((LOG_ERR, "pppInProc[%d]: NO FREE MBUFS!\n", pd));
-#if LINK_STATS
-						lwip_stats.link.memerr++;
-#endif /* LINK_STATS */
-                        pppDrop(pc);
-                        pc->inState = PDSTART;  /* Wait for flag sequence. */
-			break;
-                    }
-		    if (pc->inHead == NULL) {
-			struct pppInputHeader *pih = nextNBuf->payload;
-
-			pih->unit = pd;
-			pih->proto = pc->inProtocol;
-
-			nextNBuf->len += sizeof(*pih);
-
-			pc->inHead = nextNBuf;
-		    }
-		    pc->inTail = nextNBuf;
-                }
-                /* Load character into buffer. */
-                ((u_char*)pc->inTail->payload)[pc->inTail->len++] = curChar;
-                break;
-            }
-
-            /* update the frame check sequence number. */
-            pc->inFCS = PPP_FCS(pc->inFCS, curChar);
-        }
-    }
-	avRandomize();
-}
-
-#endif /* PPP_SUPPORT */
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/ppp.h b/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/ppp.h
deleted file mode 100644
index dbe12171e..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/ppp.h
+++ /dev/null
@@ -1,446 +0,0 @@
-/*****************************************************************************
-* ppp.h - Network Point to Point Protocol header file.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* portions Copyright (c) 1997 Global Election Systems Inc.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY
-*
-* 03-01-01 Marc Boucher 
-*   Ported to lwIP.
-* 97-11-05 Guy Lancaster , Global Election Systems Inc.
-*	Original derived from BSD codes.
-*****************************************************************************/
-
-#ifndef PPP_H
-#define PPP_H
-
-#include "lwip/opt.h"
-
-#if PPP_SUPPORT > 0
-#include "lwip/sio.h"
-#include "lwip/api.h"
-#include "lwip/sockets.h"
-#include "lwip/stats.h"
-#include "lwip/mem.h"
-#include "lwip/tcpip.h"
-#include "lwip/netif.h"
-
-/*
- * pppd.h - PPP daemon global declarations.
- *
- * Copyright (c) 1989 Carnegie Mellon University.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by Carnegie Mellon University.  The name of the
- * University may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- *
- */
-/*
- * ppp_defs.h - PPP definitions.
- *
- * Copyright (c) 1994 The Australian National University.
- * All rights reserved.
- *
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, provided that the above copyright
- * notice appears in all copies.  This software is provided without any
- * warranty, express or implied. The Australian National University
- * makes no representations about the suitability of this software for
- * any purpose.
- *
- * IN NO EVENT SHALL THE AUSTRALIAN NATIONAL UNIVERSITY BE LIABLE TO ANY
- * PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES
- * ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF
- * THE AUSTRALIAN NATIONAL UNIVERSITY HAVE BEEN ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * THE AUSTRALIAN NATIONAL UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
- * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
- * AND FITNESS FOR A PARTICULAR PURPOSE.  THE SOFTWARE PROVIDED HEREUNDER IS
- * ON AN "AS IS" BASIS, AND THE AUSTRALIAN NATIONAL UNIVERSITY HAS NO
- * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS,
- * OR MODIFICATIONS.
- */
-
-#define TIMEOUT(f, a, t)    sys_untimeout((f), (a)), sys_timeout((t)*1000, (f), (a))
-#define UNTIMEOUT(f, a)     sys_untimeout((f), (a))
-
-
-# ifndef __u_char_defined
-
-/* Type definitions for BSD code. */
-typedef unsigned long u_long;
-typedef unsigned int u_int;
-typedef unsigned short u_short;
-typedef unsigned char u_char;
-
-#endif
-
-/*
- * Constants and structures defined by the internet system,
- * Per RFC 790, September 1981, and numerous additions.
- */
-
-/*
- * The basic PPP frame.
- */
-#define PPP_HDRLEN  4       /* octets for standard ppp header */
-#define PPP_FCSLEN  2       /* octets for FCS */
-
-
-/*
- * Significant octet values.
- */
-#define PPP_ALLSTATIONS 0xff    /* All-Stations broadcast address */
-#define PPP_UI          0x03    /* Unnumbered Information */
-#define PPP_FLAG        0x7e    /* Flag Sequence */
-#define PPP_ESCAPE      0x7d    /* Asynchronous Control Escape */
-#define PPP_TRANS       0x20    /* Asynchronous transparency modifier */
-
-/*
- * Protocol field values.
- */
-#define PPP_IP          0x21    /* Internet Protocol */
-#define PPP_AT          0x29    /* AppleTalk Protocol */
-#define PPP_VJC_COMP    0x2d    /* VJ compressed TCP */
-#define PPP_VJC_UNCOMP  0x2f    /* VJ uncompressed TCP */
-#define PPP_COMP        0xfd    /* compressed packet */
-#define PPP_IPCP        0x8021  /* IP Control Protocol */
-#define PPP_ATCP        0x8029  /* AppleTalk Control Protocol */
-#define PPP_CCP         0x80fd  /* Compression Control Protocol */
-#define PPP_LCP         0xc021  /* Link Control Protocol */
-#define PPP_PAP         0xc023  /* Password Authentication Protocol */
-#define PPP_LQR         0xc025  /* Link Quality Report protocol */
-#define PPP_CHAP        0xc223  /* Cryptographic Handshake Auth. Protocol */
-#define PPP_CBCP        0xc029  /* Callback Control Protocol */
-
-/*
- * Values for FCS calculations.
- */
-#define PPP_INITFCS 0xffff  /* Initial FCS value */
-#define PPP_GOODFCS 0xf0b8  /* Good final FCS value */
-#define PPP_FCS(fcs, c) (((fcs) >> 8) ^ fcstab[((fcs) ^ (c)) & 0xff])
-
-/*
- * Extended asyncmap - allows any character to be escaped.
- */
-typedef u_char  ext_accm[32];
-
-/*
- * What to do with network protocol (NP) packets.
- */
-enum NPmode {
-    NPMODE_PASS,        /* pass the packet through */
-    NPMODE_DROP,        /* silently drop the packet */
-    NPMODE_ERROR,       /* return an error */
-    NPMODE_QUEUE        /* save it up for later. */
-};
-
-/*
- * Inline versions of get/put char/short/long.
- * Pointer is advanced; we assume that both arguments
- * are lvalues and will already be in registers.
- * cp MUST be u_char *.
- */
-#define GETCHAR(c, cp) { \
-    (c) = *(cp)++; \
-}
-#define PUTCHAR(c, cp) { \
-    *(cp)++ = (u_char) (c); \
-}
-
-
-#define GETSHORT(s, cp) { \
-    (s) = *(cp)++ << 8; \
-    (s) |= *(cp)++; \
-}
-#define PUTSHORT(s, cp) { \
-    *(cp)++ = (u_char) ((s) >> 8); \
-    *(cp)++ = (u_char) (s); \
-}
-
-#define GETLONG(l, cp) { \
-    (l) = *(cp)++ << 8; \
-    (l) |= *(cp)++; (l) <<= 8; \
-    (l) |= *(cp)++; (l) <<= 8; \
-    (l) |= *(cp)++; \
-}
-#define PUTLONG(l, cp) { \
-    *(cp)++ = (u_char) ((l) >> 24); \
-    *(cp)++ = (u_char) ((l) >> 16); \
-    *(cp)++ = (u_char) ((l) >> 8); \
-    *(cp)++ = (u_char) (l); \
-}
-
-
-#define INCPTR(n, cp)   ((cp) += (n))
-#define DECPTR(n, cp)   ((cp) -= (n))
-
-#define BCMP(s0, s1, l)     memcmp((u_char *)(s0), (u_char *)(s1), (l))
-#define BCOPY(s, d, l)      memcpy((d), (s), (l))
-#define BZERO(s, n)         memset(s, 0, n)
-#if PPP_DEBUG
-#define PRINTMSG(m, l)  { m[l] = '\0'; ppp_trace(LOG_INFO, "Remote message: %s\n", m); }
-#else
-#define PRINTMSG(m, l)
-#endif
-
-/*
- * MAKEHEADER - Add PPP Header fields to a packet.
- */
-#define MAKEHEADER(p, t) { \
-    PUTCHAR(PPP_ALLSTATIONS, p); \
-    PUTCHAR(PPP_UI, p); \
-    PUTSHORT(t, p); }
-
-/*************************
-*** PUBLIC DEFINITIONS ***
-*************************/
-
-/* Error codes. */
-#define PPPERR_NONE 0				/* No error. */
-#define PPPERR_PARAM -1				/* Invalid parameter. */
-#define PPPERR_OPEN -2				/* Unable to open PPP session. */
-#define PPPERR_DEVICE -3			/* Invalid I/O device for PPP. */
-#define PPPERR_ALLOC -4				/* Unable to allocate resources. */
-#define PPPERR_USER -5				/* User interrupt. */
-#define PPPERR_CONNECT -6			/* Connection lost. */
-#define PPPERR_AUTHFAIL -7			/* Failed authentication challenge. */
-#define PPPERR_PROTOCOL -8			/* Failed to meet protocol. */
-
-/*
- * PPP IOCTL commands.
- */
-/*
- * Get the up status - 0 for down, non-zero for up.  The argument must
- * point to an int.
- */
-#define PPPCTLG_UPSTATUS 100	/* Get the up status - 0 down else up */
-#define PPPCTLS_ERRCODE 101		/* Set the error code */
-#define PPPCTLG_ERRCODE 102		/* Get the error code */
-#define	PPPCTLG_FD		103		/* Get the fd associated with the ppp */
-
-/************************
-*** PUBLIC DATA TYPES ***
-************************/
-
-/*
- * The following struct gives the addresses of procedures to call
- * for a particular protocol.
- */
-struct protent {
-    u_short protocol;       /* PPP protocol number */
-    /* Initialization procedure */
-    void (*init) (int unit);
-    /* Process a received packet */
-    void (*input) (int unit, u_char *pkt, int len);
-    /* Process a received protocol-reject */
-    void (*protrej) (int unit);
-    /* Lower layer has come up */
-    void (*lowerup) (int unit);
-    /* Lower layer has gone down */
-    void (*lowerdown) (int unit);
-    /* Open the protocol */
-    void (*open) (int unit);
-    /* Close the protocol */
-    void (*close) (int unit, char *reason);
-#if 0
-    /* Print a packet in readable form */
-    int  (*printpkt) (u_char *pkt, int len,
-              void (*printer) (void *, char *, ...),
-              void *arg);
-    /* Process a received data packet */
-    void (*datainput) (int unit, u_char *pkt, int len);
-#endif
-    int  enabled_flag;      /* 0 iff protocol is disabled */
-    char *name;         /* Text name of protocol */
-#if 0
-    /* Check requested options, assign defaults */
-    void (*check_options) (u_long);
-    /* Configure interface for demand-dial */
-    int  (*demand_conf) (int unit);
-    /* Say whether to bring up link for this pkt */
-    int  (*active_pkt) (u_char *pkt, int len);
-#endif
-};
-
-/*
- * The following structure records the time in seconds since
- * the last NP packet was sent or received.
- */
-struct ppp_idle {
-    u_short xmit_idle;      /* seconds since last NP packet sent */
-    u_short recv_idle;      /* seconds since last NP packet received */
-};
-
-struct ppp_settings {
-
-	u_int  disable_defaultip : 1;   /* Don't use hostname for default IP addrs */
-	u_int  auth_required : 1;      /* Peer is required to authenticate */
-	u_int  explicit_remote : 1;    /* remote_name specified with remotename opt */
-	u_int  refuse_pap : 1;         /* Don't wanna auth. ourselves with PAP */
-	u_int  refuse_chap : 1;        /* Don't wanna auth. ourselves with CHAP */
-	u_int  usehostname : 1;        /* Use hostname for our_name */
-	u_int  usepeerdns : 1;         /* Ask peer for DNS adds */
-
-	u_short idle_time_limit; /* Shut down link if idle for this long */
-	int  maxconnect;         /* Maximum connect time (seconds) */
-
-	char user[MAXNAMELEN + 1];/* Username for PAP */
-	char passwd[MAXSECRETLEN + 1];           /* Password for PAP, secret for CHAP */
-	char our_name[MAXNAMELEN + 1];         /* Our name for authentication purposes */
-	char remote_name[MAXNAMELEN + 1];      /* Peer's name for authentication */
-};
-
-struct ppp_addrs {
-    struct ip_addr our_ipaddr, his_ipaddr, netmask, dns1, dns2;
-};
-
-/*****************************
-*** PUBLIC DATA STRUCTURES ***
-*****************************/
-/* Buffers for outgoing packets. */
-extern u_char outpacket_buf[NUM_PPP][PPP_MRU+PPP_HDRLEN];
-
-extern struct ppp_settings ppp_settings;
-
-extern struct protent *ppp_protocols[];/* Table of pointers to supported protocols */
-
-
-/***********************
-*** PUBLIC FUNCTIONS ***
-***********************/
-
-/* Initialize the PPP subsystem. */
-void pppInit(void);
-
-/* Warning: Using PPPAUTHTYPE_ANY might have security consequences.
- * RFC 1994 says:
- *
- * In practice, within or associated with each PPP server, there is a
- * database which associates "user" names with authentication
- * information ("secrets").  It is not anticipated that a particular
- * named user would be authenticated by multiple methods.  This would
- * make the user vulnerable to attacks which negotiate the least secure
- * method from among a set (such as PAP rather than CHAP).  If the same
- * secret was used, PAP would reveal the secret to be used later with
- * CHAP.
- *
- * Instead, for each user name there should be an indication of exactly
- * one method used to authenticate that user name.  If a user needs to
- * make use of different authentication methods under different
- * circumstances, then distinct user names SHOULD be employed, each of
- * which identifies exactly one authentication method.
- *
- */
-enum pppAuthType {
-    PPPAUTHTYPE_NONE,
-    PPPAUTHTYPE_ANY,
-    PPPAUTHTYPE_PAP,
-    PPPAUTHTYPE_CHAP
-};
-
-void pppSetAuth(enum pppAuthType authType, const char *user, const char *passwd);
-
-/*
- * Open a new PPP connection using the given I/O device.
- * This initializes the PPP control block but does not
- * attempt to negotiate the LCP session.
- * Return a new PPP connection descriptor on success or
- * an error code (negative) on failure. 
- */
-int pppOpen(sio_fd_t fd, void (*linkStatusCB)(void *ctx, int errCode, void *arg), void *linkStatusCtx);
-
-/*
- * Close a PPP connection and release the descriptor. 
- * Any outstanding packets in the queues are dropped.
- * Return 0 on success, an error code on failure. 
- */
-int pppClose(int pd);
-
-/*
- * Indicate to the PPP process that the line has disconnected.
- */
-void pppSigHUP(int pd);
-
-/*
- * Get and set parameters for the given connection.
- * Return 0 on success, an error code on failure. 
- */
-int  pppIOCtl(int pd, int cmd, void *arg);
-
-/*
- * Return the Maximum Transmission Unit for the given PPP connection.
- */
-u_int pppMTU(int pd);
-
-/*
- * Write n characters to a ppp link.
- *	RETURN: >= 0 Number of characters written
- *		 	 -1 Failed to write to device
- */
-int pppWrite(int pd, const u_char *s, int n);
-
-void pppMainWakeup(int pd);
-
-/* Configure i/f transmit parameters */
-void ppp_send_config (int, int, u32_t, int, int);
-/* Set extended transmit ACCM */
-void ppp_set_xaccm (int, ext_accm *);
-/* Configure i/f receive parameters */
-void ppp_recv_config (int, int, u32_t, int, int);
-/* Find out how long link has been idle */
-int  get_idle_time (int, struct ppp_idle *);
-
-/* Configure VJ TCP header compression */
-int  sifvjcomp (int, int, int, int);
-/* Configure i/f down (for IP) */
-int  sifup (int);		
-/* Set mode for handling packets for proto */
-int  sifnpmode (int u, int proto, enum NPmode mode);
-/* Configure i/f down (for IP) */
-int  sifdown (int);	
-/* Configure IP addresses for i/f */
-int  sifaddr (int, u32_t, u32_t, u32_t, u32_t, u32_t);
-/* Reset i/f IP addresses */
-int  cifaddr (int, u32_t, u32_t);
-/* Create default route through i/f */
-int  sifdefaultroute (int, u32_t, u32_t);
-/* Delete default route through i/f */
-int  cifdefaultroute (int, u32_t, u32_t);
-
-/* Get appropriate netmask for address */
-u32_t GetMask (u32_t); 
-
-#endif /* PPP_SUPPORT */
-
-#endif /* PPP_H */
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/pppdebug.h b/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/pppdebug.h
deleted file mode 100644
index de1478cee..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/pppdebug.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/*****************************************************************************
-* pppdebug.h - System debugging utilities.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* portions Copyright (c) 1998 Global Election Systems Inc.
-* portions Copyright (c) 2001 by Cognizant Pty Ltd.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY (please don't use tabs!)
-*
-* 03-01-01 Marc Boucher 
-*   Ported to lwIP.
-* 98-07-29 Guy Lancaster , Global Election Systems Inc.
-*	Original.
-*
-*****************************************************************************
-*/
-#ifndef PPPDEBUG_H
-#define PPPDEBUG_H
-
-/************************
-*** PUBLIC DATA TYPES ***
-************************/
-/* Trace levels. */
-typedef enum {
-	LOG_CRITICAL = 0,
-	LOG_ERR = 1,
-	LOG_NOTICE = 2,
-	LOG_WARNING = 3,
-	LOG_INFO = 5,
-	LOG_DETAIL = 6,
-	LOG_DEBUG = 7
-} LogCodes;
-
-
-/***********************
-*** PUBLIC FUNCTIONS ***
-***********************/
-/*
- *	ppp_trace - a form of printf to send tracing information to stderr
- */
-void ppp_trace(int level, const char *format,...);
-
-#if PPP_DEBUG > 0
-
-#define AUTHDEBUG(a) ppp_trace a
-#define IPCPDEBUG(a) ppp_trace a
-#define UPAPDEBUG(a) ppp_trace a
-#define LCPDEBUG(a) ppp_trace a
-#define FSMDEBUG(a) ppp_trace a
-#define CHAPDEBUG(a) ppp_trace a
-#define PPPDEBUG(a) ppp_trace a
-
-#define TRACELCP 1
-
-#else
-
-#define AUTHDEBUG(a)
-#define IPCPDEBUG(a)
-#define UPAPDEBUG(a)
-#define LCPDEBUG(a)
-#define FSMDEBUG(a)
-#define CHAPDEBUG(a)
-
-#define PPPDEBUG(a)
-
-#define TRACELCP 0
-
-#endif
-
-#endif /* PPPDEBUG_H */
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/randm.c b/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/randm.c
deleted file mode 100644
index 05eeb4410..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/randm.c
+++ /dev/null
@@ -1,242 +0,0 @@
-/*****************************************************************************
-* randm.c - Random number generator program file.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* Copyright (c) 1998 by Global Election Systems Inc.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY
-*
-* 03-01-01 Marc Boucher 
-*   Ported to lwIP.
-* 98-06-03 Guy Lancaster , Global Election Systems Inc.
-*   Extracted from avos.
-*****************************************************************************/
-
-#include "ppp.h"
-#if PPP_SUPPORT > 0
-#include "md5.h"
-#include "randm.h"
-
-#include "pppdebug.h"
-
-
-#if MD5_SUPPORT>0   /* this module depends on MD5 */
-#define RANDPOOLSZ 16   /* Bytes stored in the pool of randomness. */
-
-/*****************************/
-/*** LOCAL DATA STRUCTURES ***/
-/*****************************/
-static char randPool[RANDPOOLSZ];   /* Pool of randomness. */
-static long randCount = 0;      /* Pseudo-random incrementer */
-
-
-/***********************************/
-/*** PUBLIC FUNCTION DEFINITIONS ***/
-/***********************************/
-/*
- * Initialize the random number generator.
- *
- * Since this is to be called on power up, we don't have much
- *  system randomess to work with.  Here all we use is the
- *  real-time clock.  We'll accumulate more randomness as soon
- *  as things start happening.
- */
-void avRandomInit()
-{
-    avChurnRand(NULL, 0);
-}
-
-/*
- * Churn the randomness pool on a random event.  Call this early and often
- *  on random and semi-random system events to build randomness in time for
- *  usage.  For randomly timed events, pass a null pointer and a zero length
- *  and this will use the system timer and other sources to add randomness.
- *  If new random data is available, pass a pointer to that and it will be
- *  included.
- *
- * Ref: Applied Cryptography 2nd Ed. by Bruce Schneier p. 427
- */
-void avChurnRand(char *randData, u32_t randLen)
-{
-    MD5_CTX md5;
-
-/*  ppp_trace(LOG_INFO, "churnRand: %u@%P\n", randLen, randData); */
-    MD5Init(&md5);
-    MD5Update(&md5, (u_char *)randPool, sizeof(randPool));
-    if (randData)
-        MD5Update(&md5, (u_char *)randData, randLen);
-    else {
-        struct {
-            /* INCLUDE fields for any system sources of randomness */
-            char foobar;
-        } sysData;
-
-        /* Load sysData fields here. */
-        ;
-        MD5Update(&md5, (u_char *)&sysData, sizeof(sysData));
-    }
-    MD5Final((u_char *)randPool, &md5);
-/*  ppp_trace(LOG_INFO, "churnRand: -> 0\n"); */
-}
-
-/*
- * Use the random pool to generate random data.  This degrades to pseudo
- *  random when used faster than randomness is supplied using churnRand().
- * Note: It's important that there be sufficient randomness in randPool
- *  before this is called for otherwise the range of the result may be
- *  narrow enough to make a search feasible.
- *
- * Ref: Applied Cryptography 2nd Ed. by Bruce Schneier p. 427
- *
- * XXX Why does he not just call churnRand() for each block?  Probably
- *  so that you don't ever publish the seed which could possibly help
- *  predict future values.
- * XXX Why don't we preserve md5 between blocks and just update it with
- *  randCount each time?  Probably there is a weakness but I wish that
- *  it was documented.
- */
-void avGenRand(char *buf, u32_t bufLen)
-{
-    MD5_CTX md5;
-    u_char tmp[16];
-    u32_t n;
-
-    while (bufLen > 0) {
-        n = LWIP_MIN(bufLen, RANDPOOLSZ);
-        MD5Init(&md5);
-        MD5Update(&md5, (u_char *)randPool, sizeof(randPool));
-        MD5Update(&md5, (u_char *)&randCount, sizeof(randCount));
-        MD5Final(tmp, &md5);
-        randCount++;
-        memcpy(buf, tmp, n);
-        buf += n;
-        bufLen -= n;
-    }
-}
-
-/*
- * Return a new random number.
- */
-u32_t avRandom()
-{
-    u32_t newRand;
-
-    avGenRand((char *)&newRand, sizeof(newRand));
-
-    return newRand;
-}
-
-#else /* MD5_SUPPORT */
-
-
-/*****************************/
-/*** LOCAL DATA STRUCTURES ***/
-/*****************************/
-static int  avRandomized = 0;       /* Set when truely randomized. */
-static u32_t avRandomSeed = 0;      /* Seed used for random number generation. */
-
-
-/***********************************/
-/*** PUBLIC FUNCTION DEFINITIONS ***/
-/***********************************/
-/*
- * Initialize the random number generator.
- *
- * Here we attempt to compute a random number seed but even if
- * it isn't random, we'll randomize it later.
- *
- * The current method uses the fields from the real time clock,
- * the idle process counter, the millisecond counter, and the
- * hardware timer tick counter.  When this is invoked
- * in startup(), then the idle counter and timer values may
- * repeat after each boot and the real time clock may not be
- * operational.  Thus we call it again on the first random
- * event.
- */
-void avRandomInit()
-{
-#if 0
-    /* Get a pointer into the last 4 bytes of clockBuf. */
-    u32_t *lptr1 = (u32_t *)((char *)&clockBuf[3]);
-
-    /*
-     * Initialize our seed using the real-time clock, the idle
-     * counter, the millisecond timer, and the hardware timer
-     * tick counter.  The real-time clock and the hardware
-     * tick counter are the best sources of randomness but
-     * since the tick counter is only 16 bit (and truncated
-     * at that), the idle counter and millisecond timer
-     * (which may be small values) are added to help
-     * randomize the lower 16 bits of the seed.
-     */
-    readClk();
-    avRandomSeed += *(u32_t *)clockBuf + *lptr1 + OSIdleCtr
-             + ppp_mtime() + ((u32_t)TM1 << 16) + TM1;
-#else
-    avRandomSeed += sys_jiffies(); /* XXX */
-#endif
-        
-    /* Initialize the Borland random number generator. */
-    srand((unsigned)avRandomSeed);
-}
-
-/*
- * Randomize our random seed value.  Here we use the fact that
- * this function is called at *truely random* times by the polling
- * and network functions.  Here we only get 16 bits of new random
- * value but we use the previous value to randomize the other 16
- * bits.
- */
-void avRandomize(void)
-{
-    static u32_t last_jiffies;
-
-    if (!avRandomized) {
-        avRandomized = !0;
-        avRandomInit();
-        /* The initialization function also updates the seed. */
-    } else {
-/*        avRandomSeed += (avRandomSeed << 16) + TM1; */
-    	avRandomSeed += (sys_jiffies() - last_jiffies); /* XXX */
-    }
-    last_jiffies = sys_jiffies();
-}
-
-/*
- * Return a new random number.
- * Here we use the Borland rand() function to supply a pseudo random
- * number which we make truely random by combining it with our own
- * seed which is randomized by truely random events. 
- * Thus the numbers will be truely random unless there have been no
- * operator or network events in which case it will be pseudo random
- * seeded by the real time clock.
- */
-u32_t avRandom()
-{
-    return ((((u32_t)rand() << 16) + rand()) + avRandomSeed);
-}
-
-
-
-#endif /* MD5_SUPPORT */
-#endif /* PPP_SUPPORT */
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/randm.h b/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/randm.h
deleted file mode 100644
index baa42f0c2..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/randm.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/*****************************************************************************
-* randm.h - Random number generator header file.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* Copyright (c) 1998 Global Election Systems Inc.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY
-*
-* 03-01-01 Marc Boucher 
-*   Ported to lwIP.
-* 98-05-29 Guy Lancaster , Global Election Systems Inc.
-*	Extracted from avos.
-*****************************************************************************/
-
-#ifndef RANDM_H
-#define RANDM_H
-
-/***********************
-*** PUBLIC FUNCTIONS ***
-***********************/
-/*
- * Initialize the random number generator.
- */
-void avRandomInit(void);
-
-/*
- * Churn the randomness pool on a random event.  Call this early and often
- *	on random and semi-random system events to build randomness in time for
- *	usage.  For randomly timed events, pass a null pointer and a zero length
- *	and this will use the system timer and other sources to add randomness.
- *	If new random data is available, pass a pointer to that and it will be
- *	included.
- */
-void avChurnRand(char *randData, u32_t randLen);
-
-/*
- * Randomize our random seed value.  To be called for truely random events
- * such as user operations and network traffic.
- */
-#if MD5_SUPPORT
-#define avRandomize()	avChurnRand(NULL, 0)
-#else
-void avRandomize(void);
-#endif
-
-/*
- * Use the random pool to generate random data.  This degrades to pseudo
- *	random when used faster than randomness is supplied using churnRand().
- *	Thus it's important to make sure that the results of this are not
- *	published directly because one could predict the next result to at
- *	least some degree.  Also, it's important to get a good seed before
- *	the first use.
- */
-void avGenRand(char *buf, u32_t bufLen);
-
-/*
- * Return a new random number.
- */
-u32_t avRandom(void);
-
-
-#endif /* RANDM_H */
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/vj.c b/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/vj.c
deleted file mode 100644
index 0636ee11b..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/vj.c
+++ /dev/null
@@ -1,633 +0,0 @@
-/*
- * Routines to compress and uncompess tcp packets (for transmission
- * over low speed serial lines.
- *
- * Copyright (c) 1989 Regents of the University of California.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by the University of California, Berkeley.  The name of the
- * University may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- *
- *	Van Jacobson (van@helios.ee.lbl.gov), Dec 31, 1989:
- *	- Initial distribution.
- *
- * Modified June 1993 by Paul Mackerras, paulus@cs.anu.edu.au,
- * so that the entire packet being decompressed doesn't have
- * to be in contiguous memory (just the compressed header).
- *
- * Modified March 1998 by Guy Lancaster, glanca@gesn.com,
- * for a 16 bit processor.
- */
-
-#include 
-
-#include "ppp.h"
-#include "vj.h"
-#include "pppdebug.h"
-
-#if VJ_SUPPORT > 0
-
-#if LINK_STATS
-#define INCR(counter) ++comp->stats.counter
-#else
-#define INCR(counter)
-#endif
-
-#if defined(NO_CHAR_BITFIELDS)
-#define getip_hl(base)	((base).ip_hl_v&0xf)
-#define getth_off(base)	(((base).th_x2_off&0xf0)>>4)
-#else
-#define getip_hl(base)	((base).ip_hl)
-#define getth_off(base)	((base).th_off)
-#endif
-
-void vj_compress_init(struct vjcompress *comp)
-{
-	register u_int i;
-	register struct cstate *tstate = comp->tstate;
-	
-#if MAX_SLOTS == 0
-	memset((char *)comp, 0, sizeof(*comp));
-#endif
-	comp->maxSlotIndex = MAX_SLOTS - 1;
-	comp->compressSlot = 0;		/* Disable slot ID compression by default. */
-	for (i = MAX_SLOTS - 1; i > 0; --i) {
-		tstate[i].cs_id = i;
-		tstate[i].cs_next = &tstate[i - 1];
-	}
-	tstate[0].cs_next = &tstate[MAX_SLOTS - 1];
-	tstate[0].cs_id = 0;
-	comp->last_cs = &tstate[0];
-	comp->last_recv = 255;
-	comp->last_xmit = 255;
-	comp->flags = VJF_TOSS;
-}
-
-
-/* ENCODE encodes a number that is known to be non-zero.  ENCODEZ
- * checks for zero (since zero has to be encoded in the long, 3 byte
- * form).
- */
-#define ENCODE(n) { \
-	if ((u_short)(n) >= 256) { \
-		*cp++ = 0; \
-		cp[1] = (n); \
-		cp[0] = (n) >> 8; \
-		cp += 2; \
-	} else { \
-		*cp++ = (n); \
-	} \
-}
-#define ENCODEZ(n) { \
-	if ((u_short)(n) >= 256 || (u_short)(n) == 0) { \
-		*cp++ = 0; \
-		cp[1] = (n); \
-		cp[0] = (n) >> 8; \
-		cp += 2; \
-	} else { \
-		*cp++ = (n); \
-	} \
-}
-
-#define DECODEL(f) { \
-	if (*cp == 0) {\
-		u32_t tmp = ntohl(f) + ((cp[1] << 8) | cp[2]); \
-		(f) = htonl(tmp); \
-		cp += 3; \
-	} else { \
-		u32_t tmp = ntohl(f) + (u32_t)*cp++; \
-		(f) = htonl(tmp); \
-	} \
-}
-
-#define DECODES(f) { \
-	if (*cp == 0) {\
-		u_short tmp = ntohs(f) + (((u_short)cp[1] << 8) | cp[2]); \
-		(f) = htons(tmp); \
-		cp += 3; \
-	} else { \
-		u_short tmp = ntohs(f) + (u_short)*cp++; \
-		(f) = htons(tmp); \
-	} \
-}
-
-#define DECODEU(f) { \
-	if (*cp == 0) {\
-		(f) = htons(((u_short)cp[1] << 8) | cp[2]); \
-		cp += 3; \
-	} else { \
-		(f) = htons((u_short)*cp++); \
-	} \
-}
-
-/*
- * vj_compress_tcp - Attempt to do Van Jacobsen header compression on a
- * packet.  This assumes that nb and comp are not null and that the first
- * buffer of the chain contains a valid IP header.
- * Return the VJ type code indicating whether or not the packet was
- * compressed.
- */
-u_int vj_compress_tcp(
-	struct vjcompress *comp,
-	struct pbuf *pb
-)
-{
-	register struct ip *ip = (struct ip *)pb->payload;
-	register struct cstate *cs = comp->last_cs->cs_next;
-	register u_short hlen = getip_hl(*ip);
-	register struct tcphdr *oth;
-	register struct tcphdr *th;
-	register u_short deltaS, deltaA;
-	register u_long deltaL;
-	register u_int changes = 0;
-	u_char new_seq[16];
-	register u_char *cp = new_seq;
-
-	/*	
-	 * Check that the packet is IP proto TCP.
-	 */
-	if (ip->ip_p != IPPROTO_TCP)
-		return (TYPE_IP);
-		
-	/*
-	 * Bail if this is an IP fragment or if the TCP packet isn't
-	 * `compressible' (i.e., ACK isn't set or some other control bit is
-	 * set).  
-	 */
-	if ((ip->ip_off & htons(0x3fff)) || pb->tot_len < 40)
-		return (TYPE_IP);
-	th = (struct tcphdr *)&((long *)ip)[hlen];
-	if ((th->th_flags & (TCP_SYN|TCP_FIN|TCP_RST|TCP_ACK)) != TCP_ACK)
-		return (TYPE_IP);
-		
-	/*
-	 * Packet is compressible -- we're going to send either a
-	 * COMPRESSED_TCP or UNCOMPRESSED_TCP packet.  Either way we need
-	 * to locate (or create) the connection state.  Special case the
-	 * most recently used connection since it's most likely to be used
-	 * again & we don't have to do any reordering if it's used.
-	 */
-	INCR(vjs_packets);
-	if (ip->ip_src.s_addr != cs->cs_ip.ip_src.s_addr 
-			|| ip->ip_dst.s_addr != cs->cs_ip.ip_dst.s_addr 
-			|| *(long *)th != ((long *)&cs->cs_ip)[getip_hl(cs->cs_ip)]) {
-		/*
-		 * Wasn't the first -- search for it.
-		 *
-		 * States are kept in a circularly linked list with
-		 * last_cs pointing to the end of the list.  The
-		 * list is kept in lru order by moving a state to the
-		 * head of the list whenever it is referenced.  Since
-		 * the list is short and, empirically, the connection
-		 * we want is almost always near the front, we locate
-		 * states via linear search.  If we don't find a state
-		 * for the datagram, the oldest state is (re-)used.
-		 */
-		register struct cstate *lcs;
-		register struct cstate *lastcs = comp->last_cs;
-		
-		do {
-			lcs = cs; cs = cs->cs_next;
-			INCR(vjs_searches);
-			if (ip->ip_src.s_addr == cs->cs_ip.ip_src.s_addr
-					&& ip->ip_dst.s_addr == cs->cs_ip.ip_dst.s_addr
-					&& *(long *)th == ((long *)&cs->cs_ip)[getip_hl(cs->cs_ip)])
-				goto found;
-		} while (cs != lastcs);
-		
-		/*
-		 * Didn't find it -- re-use oldest cstate.  Send an
-		 * uncompressed packet that tells the other side what
-		 * connection number we're using for this conversation.
-		 * Note that since the state list is circular, the oldest
-		 * state points to the newest and we only need to set
-		 * last_cs to update the lru linkage.
-		 */
-		INCR(vjs_misses);
-		comp->last_cs = lcs;
-		hlen += getth_off(*th);
-		hlen <<= 2;
-		/* Check that the IP/TCP headers are contained in the first buffer. */
-		if (hlen > pb->len)
-			return (TYPE_IP);
-		goto uncompressed;
-		
-		found:
-		/*
-		 * Found it -- move to the front on the connection list.
-		 */
-		if (cs == lastcs)
-			comp->last_cs = lcs;
-		else {
-			lcs->cs_next = cs->cs_next;
-			cs->cs_next = lastcs->cs_next;
-			lastcs->cs_next = cs;
-		}
-	}
-	
-	oth = (struct tcphdr *)&((long *)&cs->cs_ip)[hlen];
-	deltaS = hlen;
-	hlen += getth_off(*th);
-	hlen <<= 2;
-	/* Check that the IP/TCP headers are contained in the first buffer. */
-	if (hlen > pb->len) {
-		PPPDEBUG((LOG_INFO, "vj_compress_tcp: header len %d spans buffers\n", 
-					hlen));
-		return (TYPE_IP);
-	}
-	
-	/*
-	 * Make sure that only what we expect to change changed. The first
-	 * line of the `if' checks the IP protocol version, header length &
-	 * type of service.  The 2nd line checks the "Don't fragment" bit.
-	 * The 3rd line checks the time-to-live and protocol (the protocol
-	 * check is unnecessary but costless).  The 4th line checks the TCP
-	 * header length.  The 5th line checks IP options, if any.  The 6th
-	 * line checks TCP options, if any.  If any of these things are
-	 * different between the previous & current datagram, we send the
-	 * current datagram `uncompressed'.
-	 */
-	if (((u_short *)ip)[0] != ((u_short *)&cs->cs_ip)[0] 
-			|| ((u_short *)ip)[3] != ((u_short *)&cs->cs_ip)[3] 
-			|| ((u_short *)ip)[4] != ((u_short *)&cs->cs_ip)[4] 
-			|| getth_off(*th) != getth_off(*oth) 
-			|| (deltaS > 5 && BCMP(ip + 1, &cs->cs_ip + 1, (deltaS - 5) << 2)) 
-			|| (getth_off(*th) > 5 && BCMP(th + 1, oth + 1, (getth_off(*th) - 5) << 2)))
-		goto uncompressed;
-	
-	/*
-	 * Figure out which of the changing fields changed.  The
-	 * receiver expects changes in the order: urgent, window,
-	 * ack, seq (the order minimizes the number of temporaries
-	 * needed in this section of code).
-	 */
-	if (th->th_flags & TCP_URG) {
-		deltaS = ntohs(th->th_urp);
-		ENCODEZ(deltaS);
-		changes |= NEW_U;
-	} else if (th->th_urp != oth->th_urp)
-		/* argh! URG not set but urp changed -- a sensible
-		 * implementation should never do this but RFC793
-		 * doesn't prohibit the change so we have to deal
-		 * with it. */
-		goto uncompressed;
-	
-	if ((deltaS = (u_short)(ntohs(th->th_win) - ntohs(oth->th_win))) != 0) {
-		ENCODE(deltaS);
-		changes |= NEW_W;
-	}
-	
-	if ((deltaL = ntohl(th->th_ack) - ntohl(oth->th_ack)) != 0) {
-		if (deltaL > 0xffff)
-			goto uncompressed;
-		deltaA = (u_short)deltaL;
-		ENCODE(deltaA);
-		changes |= NEW_A;
-	}
-	
-	if ((deltaL = ntohl(th->th_seq) - ntohl(oth->th_seq)) != 0) {
-		if (deltaL > 0xffff)
-			goto uncompressed;
-		deltaS = (u_short)deltaL;
-		ENCODE(deltaS);
-		changes |= NEW_S;
-	}
-	
-	switch(changes) {
-	
-	case 0:
-		/*
-		 * Nothing changed. If this packet contains data and the
-		 * last one didn't, this is probably a data packet following
-		 * an ack (normal on an interactive connection) and we send
-		 * it compressed.  Otherwise it's probably a retransmit,
-		 * retransmitted ack or window probe.  Send it uncompressed
-		 * in case the other side missed the compressed version.
-		 */
-		if (ip->ip_len != cs->cs_ip.ip_len &&
-			ntohs(cs->cs_ip.ip_len) == hlen)
-		break;
-	
-	/* (fall through) */
-	
-	case SPECIAL_I:
-	case SPECIAL_D:
-		/*
-		 * actual changes match one of our special case encodings --
-		 * send packet uncompressed.
-		 */
-		goto uncompressed;
-	
-	case NEW_S|NEW_A:
-		if (deltaS == deltaA && deltaS == ntohs(cs->cs_ip.ip_len) - hlen) {
-			/* special case for echoed terminal traffic */
-			changes = SPECIAL_I;
-			cp = new_seq;
-		}
-		break;
-	
-	case NEW_S:
-		if (deltaS == ntohs(cs->cs_ip.ip_len) - hlen) {
-			/* special case for data xfer */
-			changes = SPECIAL_D;
-			cp = new_seq;
-		}
-		break;
-	}
-	
-	deltaS = (u_short)(ntohs(ip->ip_id) - ntohs(cs->cs_ip.ip_id));
-	if (deltaS != 1) {
-		ENCODEZ(deltaS);
-		changes |= NEW_I;
-	}
-	if (th->th_flags & TCP_PSH)
-	changes |= TCP_PUSH_BIT;
-	/*
-	 * Grab the cksum before we overwrite it below.  Then update our
-	 * state with this packet's header.
-	 */
-	deltaA = ntohs(th->th_sum);
-	BCOPY(ip, &cs->cs_ip, hlen);
-	
-	/*
-	 * We want to use the original packet as our compressed packet.
-	 * (cp - new_seq) is the number of bytes we need for compressed
-	 * sequence numbers.  In addition we need one byte for the change
-	 * mask, one for the connection id and two for the tcp checksum.
-	 * So, (cp - new_seq) + 4 bytes of header are needed.  hlen is how
-	 * many bytes of the original packet to toss so subtract the two to
-	 * get the new packet size.
-	 */
-	deltaS = (u_short)(cp - new_seq);
-	if (!comp->compressSlot || comp->last_xmit != cs->cs_id) {
-		comp->last_xmit = cs->cs_id;
-		hlen -= deltaS + 4;
-		pbuf_header(pb, -hlen);
-		cp = (u_char *)pb->payload;
-		*cp++ = changes | NEW_C;
-		*cp++ = cs->cs_id;
-	} else {
-		hlen -= deltaS + 3;
-		pbuf_header(pb, -hlen);
-		cp = (u_char *)pb->payload;
-		*cp++ = changes;
-	}
-	*cp++ = deltaA >> 8;
-	*cp++ = deltaA;
-	BCOPY(new_seq, cp, deltaS);
-	INCR(vjs_compressed);
-	return (TYPE_COMPRESSED_TCP);
-
-	/*
-	 * Update connection state cs & send uncompressed packet (that is,
-	 * a regular ip/tcp packet but with the 'conversation id' we hope
-	 * to use on future compressed packets in the protocol field).
-	 */
-uncompressed:
-	BCOPY(ip, &cs->cs_ip, hlen);
-	ip->ip_p = cs->cs_id;
-	comp->last_xmit = cs->cs_id;
-	return (TYPE_UNCOMPRESSED_TCP);
-}
-
-/*
- * Called when we may have missed a packet.
- */
-void vj_uncompress_err(struct vjcompress *comp)
-{
-    comp->flags |= VJF_TOSS;
-	INCR(vjs_errorin);
-}
-
-/*
- * "Uncompress" a packet of type TYPE_UNCOMPRESSED_TCP.
- * Return 0 on success, -1 on failure.
- */
-int vj_uncompress_uncomp(
-	struct pbuf *nb,
-	struct vjcompress *comp
-)
-{
-	register u_int hlen;
-	register struct cstate *cs;
-	register struct ip *ip;
-	
-	ip = (struct ip *)nb->payload;
-	hlen = getip_hl(*ip) << 2;
-	if (ip->ip_p >= MAX_SLOTS
-			|| hlen + sizeof(struct tcphdr) > nb->len
-			|| (hlen += getth_off(*((struct tcphdr *)&((char *)ip)[hlen])) << 2)
-			    > nb->len
-			|| hlen > MAX_HDR) {
-		PPPDEBUG((LOG_INFO, "vj_uncompress_uncomp: bad cid=%d, hlen=%d buflen=%d\n", 
-					ip->ip_p, hlen, nb->len));
-		comp->flags |= VJF_TOSS;
-		INCR(vjs_errorin);
-		return -1;
-	}
-	cs = &comp->rstate[comp->last_recv = ip->ip_p];
-	comp->flags &=~ VJF_TOSS;
-	ip->ip_p = IPPROTO_TCP;
-	BCOPY(ip, &cs->cs_ip, hlen);
-	cs->cs_hlen = hlen;
-	INCR(vjs_uncompressedin);
-	return 0;
-}
-
-/*
- * Uncompress a packet of type TYPE_COMPRESSED_TCP.
- * The packet is composed of a buffer chain and the first buffer
- * must contain an accurate chain length.
- * The first buffer must include the entire compressed TCP/IP header. 
- * This procedure replaces the compressed header with the uncompressed
- * header and returns the length of the VJ header.
- */
-int vj_uncompress_tcp(
-	struct pbuf **nb,
-	struct vjcompress *comp
-)
-{
-	u_char *cp;
-	struct tcphdr *th;
-	struct cstate *cs;
-	u_short *bp;
-	struct pbuf *n0 = *nb;
-	u32_t tmp;
-	u_int vjlen, hlen, changes;
-	
-	INCR(vjs_compressedin);
-	cp = (u_char *)n0->payload;
-	changes = *cp++;
-	if (changes & NEW_C) {
-		/* 
-		 * Make sure the state index is in range, then grab the state.
-		 * If we have a good state index, clear the 'discard' flag. 
-		 */
-		if (*cp >= MAX_SLOTS) {
-			PPPDEBUG((LOG_INFO, "vj_uncompress_tcp: bad cid=%d\n", *cp));
-			goto bad;
-		}
-		
-		comp->flags &=~ VJF_TOSS;
-		comp->last_recv = *cp++;
-	} else {
-		/* 
-		 * this packet has an implicit state index.  If we've
-		 * had a line error since the last time we got an
-		 * explicit state index, we have to toss the packet. 
-		 */
-		if (comp->flags & VJF_TOSS) {
-			PPPDEBUG((LOG_INFO, "vj_uncompress_tcp: tossing\n"));
-			INCR(vjs_tossed);
-			return (-1);
-		}
-	}
-	cs = &comp->rstate[comp->last_recv];
-	hlen = getip_hl(cs->cs_ip) << 2;
-	th = (struct tcphdr *)&((u_char *)&cs->cs_ip)[hlen];
-	th->th_sum = htons((*cp << 8) | cp[1]);
-	cp += 2;
-	if (changes & TCP_PUSH_BIT)
-		th->th_flags |= TCP_PSH;
-	else
-		th->th_flags &=~ TCP_PSH;
-	
-	switch (changes & SPECIALS_MASK) {
-	case SPECIAL_I:
-		{
-			register u32_t i = ntohs(cs->cs_ip.ip_len) - cs->cs_hlen;
-			/* some compilers can't nest inline assembler.. */
-			tmp = ntohl(th->th_ack) + i;
-			th->th_ack = htonl(tmp);
-			tmp = ntohl(th->th_seq) + i;
-			th->th_seq = htonl(tmp);
-		}
-		break;
-	
-	case SPECIAL_D:
-		/* some compilers can't nest inline assembler.. */
-		tmp = ntohl(th->th_seq) + ntohs(cs->cs_ip.ip_len) - cs->cs_hlen;
-		th->th_seq = htonl(tmp);
-		break;
-	
-	default:
-		if (changes & NEW_U) {
-			th->th_flags |= TCP_URG;
-			DECODEU(th->th_urp);
-		} else
-			th->th_flags &=~ TCP_URG;
-		if (changes & NEW_W)
-			DECODES(th->th_win);
-		if (changes & NEW_A)
-			DECODEL(th->th_ack);
-		if (changes & NEW_S)
-			DECODEL(th->th_seq);
-		break;
-	}
-	if (changes & NEW_I) {
-		DECODES(cs->cs_ip.ip_id);
-	} else {
-		cs->cs_ip.ip_id = ntohs(cs->cs_ip.ip_id) + 1;
-		cs->cs_ip.ip_id = htons(cs->cs_ip.ip_id);
-	}
-	
-	/*
-	 * At this point, cp points to the first byte of data in the
-	 * packet.  Fill in the IP total length and update the IP
-	 * header checksum.
-	 */
-	vjlen = (u_short)(cp - (u_char*)n0->payload);
-	if (n0->len < vjlen) {
-		/* 
-		 * We must have dropped some characters (crc should detect
-		 * this but the old slip framing won't) 
-		 */
-		PPPDEBUG((LOG_INFO, "vj_uncompress_tcp: head buffer %d too short %d\n", 
-				  n0->len, vjlen));
-		goto bad;
-	}
-	
-#if BYTE_ORDER == LITTLE_ENDIAN
-	tmp = n0->tot_len - vjlen + cs->cs_hlen;
-	cs->cs_ip.ip_len = htons(tmp);
-#else
-	cs->cs_ip.ip_len = htons(n0->tot_len - vjlen + cs->cs_hlen);
-#endif
-	
-	/* recompute the ip header checksum */
-	bp = (u_short *) &cs->cs_ip;
-	cs->cs_ip.ip_sum = 0;
-	for (tmp = 0; hlen > 0; hlen -= 2)
-		tmp += *bp++;
-	tmp = (tmp & 0xffff) + (tmp >> 16);
-	tmp = (tmp & 0xffff) + (tmp >> 16);
-	cs->cs_ip.ip_sum = (u_short)(~tmp);
-	
-	/* Remove the compressed header and prepend the uncompressed header. */
-	pbuf_header(n0, -vjlen);
-
-	if(MEM_ALIGN(n0->payload) != n0->payload) {
-		struct pbuf *np, *q;
-		u8_t *bufptr;
-
-		np = pbuf_alloc(PBUF_RAW, n0->len + cs->cs_hlen, PBUF_POOL);
-		if(!np) {
-			PPPDEBUG((LOG_WARNING, "vj_uncompress_tcp: realign failed\n"));
-			*nb = NULL;
-			goto bad;
-		}
-
-		pbuf_header(np, -cs->cs_hlen);
-
-		bufptr = n0->payload;
-		for(q = np; q != NULL; q = q->next) {
-			memcpy(q->payload, bufptr, q->len);
-			bufptr += q->len;
-		}
-
-		if(n0->next) {
-			pbuf_chain(np, n0->next);
-			pbuf_dechain(n0);
-		}
-		pbuf_free(n0);
-		n0 = np;
-	}
-
-	if(pbuf_header(n0, cs->cs_hlen)) {
-		struct pbuf *np;
-
-		LWIP_ASSERT("vj_uncompress_tcp: cs->cs_hlen <= PBUF_POOL_BUFSIZE", cs->cs_hlen <= PBUF_POOL_BUFSIZE);
-		np = pbuf_alloc(PBUF_RAW, cs->cs_hlen, PBUF_POOL);
-		if(!np) {
-			PPPDEBUG((LOG_WARNING, "vj_uncompress_tcp: prepend failed\n"));
-			*nb = NULL;
-			goto bad;
-		}
-		pbuf_cat(np, n0);
-		n0 = np;
-	}
-	LWIP_ASSERT("n0->len >= cs->cs_hlen", n0->len >= cs->cs_hlen);
-	memcpy(n0->payload, &cs->cs_ip, cs->cs_hlen);
-
-	*nb = n0;
-
-	return vjlen;
-	
-bad:
-	comp->flags |= VJF_TOSS;
-	INCR(vjs_errorin);
-	return (-1);
-}
-
-#endif
-
-
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/vj.h b/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/vj.h
deleted file mode 100644
index bcad00ea4..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/vj.h
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * Definitions for tcp compression routines.
- *
- * $Id: vj.h,v 1.2 2006/08/29 18:53:47 wolti Exp $
- *
- * Copyright (c) 1989 Regents of the University of California.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by the University of California, Berkeley.  The name of the
- * University may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- *
- *	Van Jacobson (van@helios.ee.lbl.gov), Dec 31, 1989:
- *	- Initial distribution.
- */
-
-#ifndef VJ_H
-#define VJ_H
-
-#include "vjbsdhdr.h"
-
-#define MAX_SLOTS	16			/* must be > 2 and < 256 */
-#define MAX_HDR		128
-
-/*
- * Compressed packet format:
- *
- * The first octet contains the packet type (top 3 bits), TCP
- * 'push' bit, and flags that indicate which of the 4 TCP sequence
- * numbers have changed (bottom 5 bits).  The next octet is a
- * conversation number that associates a saved IP/TCP header with
- * the compressed packet.  The next two octets are the TCP checksum
- * from the original datagram.  The next 0 to 15 octets are
- * sequence number changes, one change per bit set in the header
- * (there may be no changes and there are two special cases where
- * the receiver implicitly knows what changed -- see below).
- * 
- * There are 5 numbers which can change (they are always inserted
- * in the following order): TCP urgent pointer, window,
- * acknowlegement, sequence number and IP ID.  (The urgent pointer
- * is different from the others in that its value is sent, not the
- * change in value.)  Since typical use of SLIP links is biased
- * toward small packets (see comments on MTU/MSS below), changes
- * use a variable length coding with one octet for numbers in the
- * range 1 - 255 and 3 octets (0, MSB, LSB) for numbers in the
- * range 256 - 65535 or 0.  (If the change in sequence number or
- * ack is more than 65535, an uncompressed packet is sent.)
- */
-
-/*
- * Packet types (must not conflict with IP protocol version)
- *
- * The top nibble of the first octet is the packet type.  There are
- * three possible types: IP (not proto TCP or tcp with one of the
- * control flags set); uncompressed TCP (a normal IP/TCP packet but
- * with the 8-bit protocol field replaced by an 8-bit connection id --
- * this type of packet syncs the sender & receiver); and compressed
- * TCP (described above).
- *
- * LSB of 4-bit field is TCP "PUSH" bit (a worthless anachronism) and
- * is logically part of the 4-bit "changes" field that follows.  Top
- * three bits are actual packet type.  For backward compatibility
- * and in the interest of conserving bits, numbers are chosen so the
- * IP protocol version number (4) which normally appears in this nibble
- * means "IP packet".
- */
-
-/* packet types */
-#define TYPE_IP 0x40
-#define TYPE_UNCOMPRESSED_TCP 0x70
-#define TYPE_COMPRESSED_TCP 0x80
-#define TYPE_ERROR 0x00
-
-/* Bits in first octet of compressed packet */
-#define NEW_C	0x40	/* flag bits for what changed in a packet */
-#define NEW_I	0x20
-#define NEW_S	0x08
-#define NEW_A	0x04
-#define NEW_W	0x02
-#define NEW_U	0x01
-
-/* reserved, special-case values of above */
-#define SPECIAL_I (NEW_S|NEW_W|NEW_U)		/* echoed interactive traffic */
-#define SPECIAL_D (NEW_S|NEW_A|NEW_W|NEW_U)	/* unidirectional data */
-#define SPECIALS_MASK (NEW_S|NEW_A|NEW_W|NEW_U)
-
-#define TCP_PUSH_BIT 0x10
-
-
-/*
- * "state" data for each active tcp conversation on the wire.  This is
- * basically a copy of the entire IP/TCP header from the last packet
- * we saw from the conversation together with a small identifier
- * the transmit & receive ends of the line use to locate saved header.
- */
-struct cstate {
-    struct cstate *cs_next;	/* next most recently used state (xmit only) */
-    u_short cs_hlen;		/* size of hdr (receive only) */
-    u_char cs_id;			/* connection # associated with this state */
-    u_char cs_filler;
-    union {
-		char csu_hdr[MAX_HDR];
-		struct ip csu_ip;	/* ip/tcp hdr from most recent packet */
-    } vjcs_u;
-};
-#define cs_ip vjcs_u.csu_ip
-#define cs_hdr vjcs_u.csu_hdr
-
-
-struct vjstat {
-    unsigned long vjs_packets;			/* outbound packets */
-    unsigned long vjs_compressed;		/* outbound compressed packets */
-    unsigned long vjs_searches;			/* searches for connection state */
-    unsigned long vjs_misses;			/* times couldn't find conn. state */
-    unsigned long vjs_uncompressedin;	/* inbound uncompressed packets */
-    unsigned long vjs_compressedin;		/* inbound compressed packets */
-    unsigned long vjs_errorin;			/* inbound unknown type packets */
-    unsigned long vjs_tossed;			/* inbound packets tossed because of error */
-};
-
-/*
- * all the state data for one serial line (we need one of these per line).
- */
-struct vjcompress {
-    struct cstate *last_cs;	/* most recently used tstate */
-    u_char last_recv;		/* last rcvd conn. id */
-    u_char last_xmit;		/* last sent conn. id */
-    u_short flags;
-    u_char maxSlotIndex;
-    u_char compressSlot;	/* Flag indicating OK to compress slot ID. */
-#if LINK_STATS
-    struct vjstat stats;
-#endif
-    struct cstate tstate[MAX_SLOTS];	/* xmit connection states */
-    struct cstate rstate[MAX_SLOTS];	/* receive connection states */
-};
-
-/* flag values */
-#define VJF_TOSS 1U		/* tossing rcvd frames because of input err */
-
-extern void  vj_compress_init (struct vjcompress *comp);
-extern u_int vj_compress_tcp (struct vjcompress *comp, struct pbuf *pb);
-extern void  vj_uncompress_err (struct vjcompress *comp);
-extern int vj_uncompress_uncomp(struct pbuf *nb, struct vjcompress *comp);
-extern int vj_uncompress_tcp(struct pbuf **nb, struct vjcompress *comp);
-
-#endif /* VJ_H */
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/vjbsdhdr.h b/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/vjbsdhdr.h
deleted file mode 100644
index a089352ad..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/ppp/vjbsdhdr.h
+++ /dev/null
@@ -1,76 +0,0 @@
-#ifndef VJBSDHDR_H
-#define VJBSDHDR_H
-
-#include "lwip/tcp.h"
-
-
-/*
- * Structure of an internet header, naked of options.
- *
- * We declare ip_len and ip_off to be short, rather than u_short
- * pragmatically since otherwise unsigned comparisons can result
- * against negative integers quite easily, and fail in subtle ways.
- */
-PACK_STRUCT_BEGIN
-struct ip
-{
-#if defined(NO_CHAR_BITFIELDS)
-	u_char ip_hl_v;	/* bug in GCC for mips means the bitfield stuff will sometimes break - so we use a char for both and get round it with macro's instead... */
-#else
-#if BYTE_ORDER == LITTLE_ENDIAN
-	unsigned ip_hl:4,				/* header length */
-		ip_v:4;						/* version */
-#elif BYTE_ORDER == BIG_ENDIAN 
-	unsigned ip_v:4,					/* version */
-		ip_hl:4;					/* header length */
-#else
-	COMPLAIN - NO BYTE ORDER SELECTED!
-#endif
-#endif
-	u_char	ip_tos;					/* type of service */
-	u_short	ip_len;					/* total length */
-	u_short	ip_id;					/* identification */
-	u_short	ip_off;					/* fragment offset field */
-#define	IP_DF 0x4000				/* dont fragment flag */
-#define	IP_MF 0x2000				/* more fragments flag */
-#define	IP_OFFMASK 0x1fff			/* mask for fragmenting bits */
-	u_char	ip_ttl;					/* time to live */
-	u_char	ip_p;					/* protocol */
-	u_short	ip_sum;					/* checksum */
-	struct	in_addr ip_src,ip_dst;	/* source and dest address */
-};
-PACK_STRUCT_END
-
-typedef u32_t tcp_seq;
-
-/*
- * TCP header.
- * Per RFC 793, September, 1981.
- */
-PACK_STRUCT_BEGIN
-struct tcphdr  
-{
-	u_short	th_sport;		/* source port */
-	u_short	th_dport;		/* destination port */
-	tcp_seq	th_seq;			/* sequence number */
-	tcp_seq	th_ack;			/* acknowledgement number */
-#if defined(NO_CHAR_BITFIELDS)
-	u_char th_x2_off;
-#else
-#if BYTE_ORDER == LITTLE_ENDIAN
-	unsigned	th_x2:4,		/* (unused) */
-			th_off:4;		/* data offset */
-#endif
-#if BYTE_ORDER == BIG_ENDIAN 
-	unsigned	th_off:4,		/* data offset */
-			th_x2:4;		/* (unused) */
-#endif
-#endif
-	u_char	th_flags;
-	u_short	th_win;			/* window */
-	u_short	th_sum;			/* checksum */
-	u_short	th_urp;			/* urgent pointer */
-};
-PACK_STRUCT_END
-
-#endif /* VJBSDHDR_H */
diff --git a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/slipif.c b/Demo/lwIP_MCF5235_GCC/lwip/src/netif/slipif.c
deleted file mode 100644
index dd8db208c..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwip/src/netif/slipif.c
+++ /dev/null
@@ -1,213 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved. 
- *
- * Redistribution and use in source and binary forms, with or without 
- * modification, are permitted provided that the following conditions 
- * are met: 
- * 1. Redistributions of source code must retain the above copyright 
- *    notice, this list of conditions and the following disclaimer. 
- * 2. Redistributions in binary form must reproduce the above copyright 
- *    notice, this list of conditions and the following disclaimer in the 
- *    documentation and/or other materials provided with the distribution. 
- * 3. Neither the name of the Institute nor the names of its contributors 
- *    may be used to endorse or promote products derived from this software 
- *    without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
- * SUCH DAMAGE. 
- *
- * This file is built upon the file: src/arch/rtxc/netif/sioslip.c
- *
- * Author: Magnus Ivarsson  
- */
-
-/* 
- * This is an arch independent SLIP netif. The specific serial hooks must be
- * provided by another file. They are sio_open, sio_recv and sio_send
- */
-
-#include "netif/slipif.h"
-#include "lwip/opt.h"
-#include "lwip/def.h"
-#include "lwip/pbuf.h"
-#include "lwip/sys.h"
-#include "lwip/stats.h"
-#include "lwip/sio.h"
-
-#define SLIP_END     0300
-#define SLIP_ESC     0333
-#define SLIP_ESC_END 0334
-#define SLIP_ESC_ESC 0335
-
-#define MAX_SIZE     1500
-
-/**
- * Send a pbuf doing the necessary SLIP encapsulation
- *
- * Uses the serial layer's sio_send() 
- */
-err_t
-slipif_output(struct netif *netif, struct pbuf *p, struct ip_addr *ipaddr)
-{
-  struct pbuf *q;
-  u16_t i;
-  u8_t c;
-
-  /* Send pbuf out on the serial I/O device. */
-  sio_send(SLIP_END, netif->state);
-
-  for (q = p; q != NULL; q = q->next) {
-    for (i = 0; i < q->len; i++) {
-      c = ((u8_t *)q->payload)[i];
-      switch (c) {
-      case SLIP_END:
-        sio_send(SLIP_ESC, netif->state);
-        sio_send(SLIP_ESC_END, netif->state);
-        break;
-      case SLIP_ESC:
-        sio_send(SLIP_ESC, netif->state);
-        sio_send(SLIP_ESC_ESC, netif->state);
-        break;
-      default:
-        sio_send(c, netif->state);
-        break;
-      }
-    }
-  }
-  sio_send(SLIP_END, netif->state);
-  return 0;
-}
-
-/**
- * Handle the incoming SLIP stream character by character
- *
- * Poll the serial layer by calling sio_recv()
- * 
- * @return The IP packet when SLIP_END is received 
- */
-static struct pbuf *
-slipif_input(struct netif *netif)
-{
-  u8_t c;
-  struct pbuf *p, *q;
-  u16_t recved;
-  u16_t i;
-
-  q = p = NULL;
-  recved = i = 0;
-  c = 0;
-
-  while (1) {
-    c = sio_recv(netif->state);
-    switch (c) {
-    case SLIP_END:
-      if (recved > 0) {
-        /* Received whole packet. */
-        pbuf_realloc(q, recved);
-        
-        LINK_STATS_INC(link.recv);
-        
-        LWIP_DEBUGF(SLIP_DEBUG, ("slipif: Got packet\n"));
-        return q;
-      }
-      break;
-
-    case SLIP_ESC:
-      c = sio_recv(netif->state);
-      switch (c) {
-      case SLIP_ESC_END:
-        c = SLIP_END;
-        break;
-      case SLIP_ESC_ESC:
-        c = SLIP_ESC;
-        break;
-      }
-      /* FALLTHROUGH */
-
-    default:
-      if (p == NULL) {
-        LWIP_DEBUGF(SLIP_DEBUG, ("slipif_input: alloc\n"));
-        p = pbuf_alloc(PBUF_LINK, PBUF_POOL_BUFSIZE, PBUF_POOL);
-
-        if (p == NULL) {
-          LINK_STATS_INC(link.drop);
-          LWIP_DEBUGF(SLIP_DEBUG, ("slipif_input: no new pbuf! (DROP)\n"));
-        }
-
-        if (q != NULL) {
-          pbuf_cat(q, p);
-        } else {
-          q = p;
-        }
-      }
-      if (p != NULL && recved < MAX_SIZE) {
-        ((u8_t *)p->payload)[i] = c;
-        recved++;
-        i++;
-        if (i >= p->len) {
-          i = 0;
-          if (p->next != NULL && p->next->len > 0)
-            p = p->next;
-          else
-            p = NULL;
-        }
-      }
-      break;
-    }
-
-  }
-  return NULL;
-}
-
-/**
- * The SLIP input thread.
- *
- * Feed the IP layer with incoming packets
- */
-static void
-slipif_loop(void *nf)
-{
-  struct pbuf *p;
-  struct netif *netif = (struct netif *)nf;
-
-  while (1) {
-    p = slipif_input(netif);
-    netif->input(p, netif);
-  }
-}
-
-/**
- * SLIP netif initialization
- *
- * Call the arch specific sio_open and remember
- * the opened device in the state field of the netif.
- */
-err_t
-slipif_init(struct netif *netif)
-{
-
-  LWIP_DEBUGF(SLIP_DEBUG, ("slipif_init: netif->num=%"U16_F"\n", (u16_t)netif->num));
-
-  netif->name[0] = 's';
-  netif->name[1] = 'l';
-  netif->output = slipif_output;
-  netif->mtu = 1500;
-  netif->flags = NETIF_FLAG_POINTTOPOINT;
-
-  netif->state = sio_open(netif->num);
-  if (!netif->state)
-    return ERR_IF;
-
-  sys_thread_new(slipif_loop, netif, SLIPIF_THREAD_PRIO);
-  return ERR_OK;
-}
diff --git a/Demo/lwIP_MCF5235_GCC/lwipopts.h b/Demo/lwIP_MCF5235_GCC/lwipopts.h
deleted file mode 100644
index f759ea1ce..000000000
--- a/Demo/lwIP_MCF5235_GCC/lwipopts.h
+++ /dev/null
@@ -1,182 +0,0 @@
-/*
- * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels 
- * Modifications: Christian Walter 
- */
-#ifndef __LWIPOPTS_H__
-#define __LWIPOPTS_H__
-
-/* ------------------------ Generic options ------------------------------- */
-#undef  LWIP_NOASSERT
-
-#define SYS_LIGHTWEIGHT_PROT    1
-#define TCPIP_THREAD_PRIO       3
-
-#define LWIP_DEBUG              1
-#define DBG_TYPES_ON            ( DBG_LEVEL_WARNING | DBG_LEVEL_SEVERE | DBG_LEVEL_SERIOUS )
-#define FEC_DEBUG               ( DBG_LEVEL_WARNING | DBG_ON )
-
-/* ------------------------ Memory options -------------------------------- */
-/* MEM_ALIGNMENT: should be set to the alignment of the CPU for which
-   lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4, 2
-   byte alignment -> define MEM_ALIGNMENT to 2. */
-#define MEM_ALIGNMENT           4
-
-/* MEM_SIZE: the size of the heap memory. If the application will send
-a lot of data that needs to be copied, this should be set high. */
-#define MEM_SIZE                2000
-
-/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application
-   sends a lot of data out of ROM (or other static memory), this
-   should be set high. */
-#define MEMP_NUM_PBUF           20
-/* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One
-   per active UDP "connection". */
-#define MEMP_NUM_UDP_PCB        4
-/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP
-   connections. */
-#define MEMP_NUM_TCP_PCB        10
-/* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP
-   connections. */
-#define MEMP_NUM_TCP_PCB_LISTEN 8
-/* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP
-   segments. */
-#define MEMP_NUM_TCP_SEG        8
-/* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active
-   timeouts. */
-#define MEMP_NUM_SYS_TIMEOUT    3
-
-/* The following four are used only with the sequential API and can be
-   set to 0 if the application only will use the raw API. */
-/* MEMP_NUM_NETBUF: the number of struct netbufs. */
-#define MEMP_NUM_NETBUF         4
-/* MEMP_NUM_NETCONN: the number of struct netconns. */
-#define MEMP_NUM_NETCONN        4
-/* MEMP_NUM_APIMSG: the number of struct api_msg, used for
-   communication between the TCP/IP stack and the sequential
-   programs. */
-#define MEMP_NUM_API_MSG        8
-/* MEMP_NUM_TCPIPMSG: the number of struct tcpip_msg, which is used
-   for sequential API communication and incoming packets. Used in
-   src/api/tcpip.c. */
-#define MEMP_NUM_TCPIP_MSG      8
-
-/* These two control is reclaimer functions should be compiled
-   in. Should always be turned on (1). */
-#define MEM_RECLAIM             1
-#define MEMP_RECLAIM            1
-
-/* ---------- Pbuf options ---------- */
-/* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */
-#define PBUF_POOL_SIZE          16
-
-/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */
-#define PBUF_POOL_BUFSIZE       512
-
-/* PBUF_LINK_HLEN: the number of bytes that should be allocated for a
-   link level header. */
-#define PBUF_LINK_HLEN          16
-
-/* ------------------------ TCP options ----------------------------------- */
-#define LWIP_TCP                1
-#define TCP_TTL                 255
-
-/* Controls if TCP should queue segments that arrive out of
-   order. Define to 0 if your device is low on memory. */
-#define TCP_QUEUE_OOSEQ         1
-
-/* TCP Maximum segment size. */
-#define TCP_MSS                 512
-
-/* TCP sender buffer space (bytes). */
-#define TCP_SND_BUF             512
-
-/* TCP sender buffer space (pbufs). This must be at least = 2 *
-   TCP_SND_BUF/TCP_MSS for things to work. */
-#define TCP_SND_QUEUELEN        6 * TCP_SND_BUF/TCP_MSS
-
-/* TCP receive window. */
-#define TCP_WND                 512
-
-/* Maximum number of retransmissions of data segments. */
-#define TCP_MAXRTX              12
-
-/* Maximum number of retransmissions of SYN segments. */
-#define TCP_SYNMAXRTX           4
-
-/* ------------------------ ARP options ----------------------------------- */
-#define ARP_TABLE_SIZE          10
-#define ARP_QUEUEING            1
-
-/* ------------------------ IP options ------------------------------------ */
-/* Define IP_FORWARD to 1 if you wish to have the ability to forward
-   IP packets across network interfaces. If you are going to run lwIP
-   on a device with only one network interface, define this to 0. */
-#define IP_FORWARD              1
-
-/* If defined to 1, IP options are allowed (but not parsed). If
-   defined to 0, all packets with IP options are dropped. */
-#define IP_OPTIONS              1
-
-/* ------------------------ ICMP options ---------------------------------- */
-#define ICMP_TTL                255
-
-
-/* ------------------------ DHCP options ---------------------------------- */
-/* Define LWIP_DHCP to 1 if you want DHCP configuration of
-   interfaces. DHCP is not implemented in lwIP 0.5.1, however, so
-   turning this on does currently not work. */
-#define LWIP_DHCP               0
-
-/* 1 if you want to do an ARP check on the offered address
-   (recommended). */
-#define DHCP_DOES_ARP_CHECK     1
-
-/* ------------------------ UDP options ----------------------------------- */
-#define LWIP_UDP                1
-#define UDP_TTL                 255
-
-/* ------------------------ Statistics options ---------------------------- */
-#define STATS
-
-#ifdef STATS
-#define LINK_STATS              1
-#define IP_STATS                1
-#define ICMP_STATS              1
-#define UDP_STATS               1
-#define TCP_STATS               1
-#define MEM_STATS               1
-#define MEMP_STATS              1
-#define PBUF_STATS              1
-#define SYS_STATS               1
-#endif /* STATS */
-
-#define LWIP_PROVIDE_ERRNO      1
-
-#endif /* __LWIPOPTS_H__ */
diff --git a/Demo/lwIP_MCF5235_GCC/m5235-ram.ld b/Demo/lwIP_MCF5235_GCC/m5235-ram.ld
deleted file mode 100644
index 7119d3f51..000000000
--- a/Demo/lwIP_MCF5235_GCC/m5235-ram.ld
+++ /dev/null
@@ -1,119 +0,0 @@
-STARTUP(system/crt0.o)
-INPUT(system/vector.o)
-OUTPUT_ARCH(m68k)
-SEARCH_DIR(.)
-GROUP(-lc -lgcc)
-
-__DYNAMIC  =  0;
-
-MEMORY
-{
-  sdram  (rwx) : ORIGIN = 0x00000000, LENGTH = 0x01000000
-  sram   (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000
-  ipsbar (rwx) : ORIGIN = 0x40000000, LENGTH = 0x40000000
-  flash  (rwx) : ORIGIN = 0x80000000, LENGTH = 0x00080000
-}
-
-PROVIDE (__stack = 0x2000FFFC);
-
-SECTIONS
-{
-  .sdram      : {} > sdram
-  .ipsbar     : {} > ipsbar
-  .sram (NOLOAD) : { *(.vector_ram); *(.nbuf) } > sram
-  .flash      : {} > flash
-
-  .text :
-  {
-    __text_start = . ;
-    *(.vector_rom)
-    . = ALIGN (0x100);
-    *(.text)
-    . = ALIGN (16);
-
-    *(.eh_frame)
-    . = ALIGN (16);
-
-    *(.gnu.linkonce.t.*) 
-
-    . = ALIGN(0x4);
-     __CTOR_LIST__ = .;
-    ___CTOR_LIST__ = .;
-    LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
-    *(.ctors)
-    LONG(0)
-    __CTOR_END__ = .;
-    __DTOR_LIST__ = .;
-    ___DTOR_LIST__ = .;
-    LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
-    *(.dtors)
-     LONG(0)
-    __DTOR_END__ = .;
-    *(.rodata)
-    *(.rodata.*)
-    *(.gcc_except_table) 
-
-    . = ALIGN(0x2);
-    __INIT_SECTION__ = . ;
-    LONG (0x4e560000)	/* linkw %fp,#0 */
-    *(.init)
-    SHORT (0x4e5e)	/* unlk %fp */
-    SHORT (0x4e75)	/* rts */
-
-    __FINI_SECTION__ = . ;
-    LONG (0x4e560000)	/* linkw %fp,#0 */
-    *(.fini)
-    SHORT (0x4e5e)	/* unlk %fp */
-    SHORT (0x4e75)	/* rts */
-
-    *(.lit)
-    . = ALIGN(16);
-    _etext = .;
-    etext = .;
-  } > sdram
-
-  .data :
-  {
-    copy_start = .;
-    *(.shdata)
-    *(.data)
-    *(.gnu.linkonce.d.*)
-    . = ALIGN (16);
-    _edata = .;
-    copy_end = .;
-  } > sdram
-  __data_load_start = LOADADDR(.data);
-  __data_load_end = __data_load_start + SIZEOF(.data);
-
-  .bss :
-  {
-    . = ALIGN(0x4);
-    __bss_start = . ;
-    *(.shbss)
-    *(.bss)
-    *(COMMON)
-    _end =  ALIGN (0x8);
-    __end = _end;
-  } > sdram
-
-  .stab 0 (NOLOAD) :
-  {
-    *(.stab)
-  }
-
-  .stabstr 0 (NOLOAD) :
-  {
-    *(.stabstr)
-  }
-}
-
-__IPSBAR            = ADDR(.ipsbar);
-
-__SDRAM             = ADDR(.sdram);
-__SDRAM_SIZE        = SIZEOF(.sdram);
-
-__SRAM              = ADDR(.sram);
-__SRAM_SIZE         = SIZEOF(.sram);
-
-__FLASH             = ADDR(.flash);
-__FLASH_SIZE        = SIZEOF(.flash);
diff --git a/Demo/lwIP_MCF5235_GCC/m5235-rom.ld b/Demo/lwIP_MCF5235_GCC/m5235-rom.ld
deleted file mode 100644
index 333d28e1f..000000000
--- a/Demo/lwIP_MCF5235_GCC/m5235-rom.ld
+++ /dev/null
@@ -1,121 +0,0 @@
-STARTUP(system/crt0.o)
-INPUT(system/vector.o)
-OUTPUT_ARCH(m68k)
-SEARCH_DIR(.)
-GROUP(-lc -lgcc)
-
-__DYNAMIC  =  0;
-
-MEMORY
-{
-  flash  (rwx) : ORIGIN = 0x00000000, LENGTH = 0x00200000
-  sdram  (rwx) : ORIGIN = 0x01000000, LENGTH = 0x01000000
-  sram   (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000
-  ipsbar (rwx) : ORIGIN = 0x40000000, LENGTH = 0x40000000
-}
-
-PROVIDE (__stack = 0x2000FFFC);
-
-SECTIONS
-{
-  .sdram      : {} > sdram
-  .ipsbar     : {} > ipsbar
-  .sram (NOLOAD) : { *(.vector_ram); *(.nbuf) } > sram
-  .flash      : {} > flash
-
-  .text :
-  {
-    __text_start = . ;
-    *(.vector_rom)
-    . = ALIGN (0x100);
-    *(.text)
-    . = ALIGN (16);
-
-    *(.eh_frame)
-    . = ALIGN (16);
-
-    *(.gnu.linkonce.t.*) 
-
-    . = ALIGN(0x4);
-     __CTOR_LIST__ = .;
-    ___CTOR_LIST__ = .;
-    LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
-    *(.ctors)
-    LONG(0)
-    __CTOR_END__ = .;
-    __DTOR_LIST__ = .;
-    ___DTOR_LIST__ = .;
-    LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
-    *(.dtors)
-     LONG(0)
-    __DTOR_END__ = .;
-    *(.rodata)
-    *(.rodata.*)
-    *(.gcc_except_table) 
-
-    . = ALIGN(0x2);
-    __INIT_SECTION__ = . ;
-    LONG (0x4e560000)	/* linkw %fp,#0 */
-    *(.init)
-    SHORT (0x4e5e)	/* unlk %fp */
-    SHORT (0x4e75)	/* rts */
-
-    __FINI_SECTION__ = . ;
-    LONG (0x4e560000)	/* linkw %fp,#0 */
-    *(.fini)
-    SHORT (0x4e5e)	/* unlk %fp */
-    SHORT (0x4e75)	/* rts */
-
-    *(.lit)
-    . = ALIGN(16);
-    _etext = .;
-    etext = .;
-
-  } > flash
-  . = ALIGN(2);
-
-  .data : AT (ADDR (.text) + SIZEOF (.text))
-  {
-    copy_start = .;
-    *(.shdata)
-    *(.data)
-    *(.gnu.linkonce.d.*)
-    . = ALIGN (16);
-    _edata = .;
-    copy_end = .;
-  } > sdram
-  __data_load_start = LOADADDR(.data);
-  __data_load_end = __data_load_start + SIZEOF(.data);
-
-  .bss :
-  {
-    . = ALIGN(0x4);
-    __bss_start = . ;
-    *(.shbss)
-    *(.bss)
-    *(COMMON)
-    _end =  ALIGN (0x8);
-    __end = _end;
-  } > sdram
-
-  .stab 0 (NOLOAD) :
-  {
-    *(.stab)
-  }
-
-  .stabstr 0 (NOLOAD) :
-  {
-    *(.stabstr)
-  }
-}
-
-__IPSBAR            = ADDR(.ipsbar);
-
-__SDRAM             = ADDR(.sdram);
-__SDRAM_SIZE        = SIZEOF(.sdram);
-
-__SRAM              = ADDR(.sram);
-__SRAM_SIZE         = SIZEOF(.sram);
-
-__FLASH             = ADDR(.flash);
-__FLASH_SIZE        = SIZEOF(.flash);
diff --git a/Demo/lwIP_MCF5235_GCC/m5235.gdb b/Demo/lwIP_MCF5235_GCC/m5235.gdb
deleted file mode 100644
index 545fbea31..000000000
--- a/Demo/lwIP_MCF5235_GCC/m5235.gdb
+++ /dev/null
@@ -1,134 +0,0 @@
-set $IPSBAR = 0x40000000
-
-set $DCR    = $IPSBAR + 0x000040
-set $DACR0  = $IPSBAR + 0x000048
-set $DMR0   = $IPSBAR + 0x00004C
-
-set $CSAR0  = $IPSBAR + 0x000080
-set $CSMR0  = $IPSBAR + 0x000084
-set $CSCR0  = $IPSBAR + 0x00008A
-
-set $PAR_SDRAM = $IPSBAR + 0x100046
-set $PAR_AD    = $IPSBAR + 0x100040
-
-set $WCR    = $IPSBAR + 0x140000
-
-define delay
-  set $delay = 0
-  while ($delay < 20000)
-    set $delay += 1
-  end  
-end
-
-define delay_memsync
-  set $delay = 0
-  while ($delay < 10000)
-    set $delay += 1
-  end  
-end
-
-define setup-cs
-  # 2MB FLASH on CS0 at 0x80000000
-  set *(unsigned short *)$CSAR0 = 0x00008000
-  set *(unsigned long  *)$CSMR0 = 0x001F0101
-  set *(unsigned short *)$CSCR0 = 0x00001980
-end
-
-define setup-sdram
-  # Set PAR_SDRAM to allow SDRAM signals to be enable
-  set *(unsigned char *)$PAR_SDRAM = 0x3F
-  # Set PAR_AD to allow 32-bit SDRAM if the external boot device is 16-bit
-  set *(unsigned char *)$PAR_AD = 0xE1
-
-  # SDRAM
-  set *(unsigned short *)$DCR   = 0x0446
-  set *(unsigned long *)$DACR0  = 0x00001300
-  set *(unsigned long *)$DMR0   = 0x00FC0001
-
-  # Set IP in DACR and init precharge.
-  set *(unsigned long *)$DACR0 |= 0x00000008
-  set *(0x00000000)             = 0xAA55AA55
-  delay
-
-  # Set RE in DACR
-  set *(unsigned long *)$DACR0 |= 0x00008000
-  # Issue IMRS
-  set *(unsigned long *)$DACR0 |= 0x00000040
-  set *(0x00000400)             = 0xAA55AA55
-  delay
-end
-
-define setup-other
-  # Turn Off WCR
-  set *(unsigned char *)$WCR = 0x00
-end
-
-define setup-and-load
-  bdm-reset
-
-  # Set VBR to the vector table.
-  set $vbr = 0x00000000
-  # Set internal SRAM to start at 0x20000000
-  set $rambar = 0x20000001
-
-  setup-other
-  setup-cs
-  setup-sdram
-end
-
-define debug-sramtest
-  set $srambase = 0x20000000
-  set $sramsize = 0x00010000
-  set $j = 0
-  printf "Testing SRAM : 0x%08X - 0x%08X\n", $srambase, ($srambase + $sramsize)
-  set $i = $srambase
-  while $i < ($srambase + $sramsize)
-    set *(unsigned long *)($i) = 0xAA55AA55
-    delay_memsync
-    if 0xAA55AA55 != *(unsigned long *)$i
-      printf "  0x%08X = FAIL\n", $i
-    else
-      printf "  0x%08X = OK", $i
-      if $j % 4 == 3
-        printf "\n"
-      end
-      set $j = $j + 1
-    end
-    set $i = $i + 0x400
-  end
-en
-
-define debug-ramtest
-  set $sdrambase = 0x00000000
-  set $sdramsize = 0x01000000
-  set $j = 0
-  printf "Testing SDRAM : 0x%08X - 0x%08X\n", $sdrambase, ($sdrambase + $sdramsize)
-  set $i = $sdrambase 
-  while $i < ($sdrambase + $sdramsize)
-    set *(unsigned long *)($i) = 0xAA55AA55
-    delay_memsync
-    if 0xAA55AA55 != *(unsigned long *)$i
-      printf "  0x%08X = FAIL\n", $i
-    else
-      printf "  0x%08X = OK", $i
-      if $j % 4 == 3
-        printf "\n"
-      end
-      set $j = $j + 1
-    end
-    set $i = $i + 0x10000
-  end
-  printf "\n"
-end
-
-define execute
-  set $pc = *(long *)0x00000004
-  tbreak main
-  tk gdbtk_update
-end
-
-define debug-printexception
-  printf "vector: %d", *(unsigned short *)$sp >> 2 &0x1F
-  printf "old pc: 0x%08x", *(unsigned long *)($sp + 4)
-  printf "old sr: 0x%02x", *(unsigned short *)($sp + 2)
-end
diff --git a/Demo/lwIP_MCF5235_GCC/system/crt0.S b/Demo/lwIP_MCF5235_GCC/system/crt0.S
deleted file mode 100644
index 21954bcb1..000000000
--- a/Demo/lwIP_MCF5235_GCC/system/crt0.S
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
-    FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter.
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-
-    FreeRTOS is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with FreeRTOS; if not, write to the Free Software
-    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-
-    A special exception to the GPL can be applied should you wish to distribute
-    a combined work that includes FreeRTOS, without being obliged to provide
-    the source code for any proprietary components.  See the licensing section
-    of http://www.FreeRTOS.org for full details of how and when the exception
-    can be applied.
-
-    ***************************************************************************
-    See http://www.FreeRTOS.org for documentation, latest information, license
-    and contact details.  Please ensure to read the configuration and relevant
-    port sections of the online documentation.
-    ***************************************************************************
-*/
-
-  .title "crt0.S"
-
-  .extern main
-  .extern __stack
-  .extern __bss_start
-  .extern __text_start
-  .extern init_main
-
-  .equ    MCF5XXX_RAMBAR_SPV,   0x00000200
-  .equ    MCF5XXX_RAMBAR_V,     0x00000001
-  .global start
-
-  .align  4
-debug:
-  .word   0x2C80    /* write to CSR */
-  .word   0x0010
-  .word   0x0400
-  .word   0x0000
-
-start:
-  /* disable all interrupts on startup. */
-  move.w  #0x2700, sr
-
-  /* prepare internal SRAM. */
-  move.l  #__SRAM, d0
-  ori.l   #( MCF5XXX_RAMBAR_SPV | MCF5XXX_RAMBAR_V ), d0
-  movec   d0, rambar
-
-  /* prepare stack and frame pointer. */
-  move.l  #__stack, sp
-  link    a6, #-8
-
-  /* initialize hardware. */
-  jsr     init_main
-
-  /* zero out the bss section. */
-  move.l  #__bss_start, d1
-  move.l  #_end, d0
-  cmp.l   d0, d1
-  jbeq    3f
-  move.l  d1, a0
-  sub.l   d1, d0
-  subq.l  #1, d0
-2:
-  clr.b   (a0)+
-  subq.l  #1, d0
-  jbpl    2b
-3:
-
-  /* Relocate the data section. */
-  move.l  #__data_load_start, %a0         /* .data in ROM */
-  move.l  #copy_start, %a1                /* .data in RAM */
-
-  /* Test if the two sections overlap. This is the case when we are working
-   * with the debugger and the debugger loads the .data section.
-   */
-  cmpa.l  %a0, %a1
-  beq     2f
-1:
-  /* Have we already copied everything. */
-  cmpa.l  #__data_load_end, %a0
-  beq     2f
-  move.b  (%a0)+, (%a1)+
-  bra     1b
-
-2:
-
-  /* C library */
-  move.l  #__FINI_SECTION__, -(%sp)
-  jsr     atexit
-  jsr     __INIT_SECTION__
-
-  /* call main(int argc, char *argv[] */
-  move.l  #0, -(sp)
-  move.l  #0, -(sp)
-  move.l  #0, -(sp)
-  jsr     main
-  lea     (sp, 12), %sp
-
-  /* stop on exit from main. */
-1:
-  halt
-
diff --git a/Demo/lwIP_MCF5235_GCC/system/init.c b/Demo/lwIP_MCF5235_GCC/system/init.c
deleted file mode 100644
index 74957f35e..000000000
--- a/Demo/lwIP_MCF5235_GCC/system/init.c
+++ /dev/null
@@ -1,743 +0,0 @@
-/*
-    FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter.
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-
-    FreeRTOS is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with FreeRTOS; if not, write to the Free Software
-    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-
-    A special exception to the GPL can be applied should you wish to distribute
-    a combined work that includes FreeRTOS, without being obliged to provide
-    the source code for any proprietary components.  See the licensing section
-    of http://www.FreeRTOS.org for full details of how and when the exception
-    can be applied.
-
-    ***************************************************************************
-    See http://www.FreeRTOS.org for documentation, latest information, license
-    and contact details.  Please ensure to read the configuration and relevant
-    port sections of the online documentation.
-    ***************************************************************************
-*/
-
-#include "mcf5xxx.h"
-#include "mcf523x.h"
-
-/* Function prototypes */
-void            init_main( void );
-static void     disable_interrupts( void );
-static void     disable_watchdog_timer( void );
-static void     disable_cache( void );
-static void     init_ipsbar( void );
-static void     init_basics( void );
-static void     init_clock_config( void );
-static void     init_chip_selects( void );
-static void     init_bus_config( void );
-static void     init_cache( void );
-static void     init_eport( void );
-static void     init_flexcan( void );
-static void     init_power_management( void );
-static void     init_dma_timers( void );
-static void     init_interrupt_timers( void );
-static void     init_watchdog_timers( void );
-static void     init_pin_assignments( void );
-static void     init_sdram_controller( void );
-static void     init_interrupt_controller( void );
-
-
-/*********************************************************************
-* init_main - Main entry point for initialisation code               *
-**********************************************************************/
-void
-init_main( void )
-{
-
-    /* Initialise base address of peripherals, VBR, etc */
-    init_ipsbar(  );
-    init_basics(  );
-    init_clock_config(  );
-
-    /* Disable interrupts, watchdog timer, cache */
-    disable_interrupts(  );
-    disable_watchdog_timer(  );
-    disable_cache(  );
-
-    /* Initialise individual modules */
-    init_chip_selects(  );
-    init_bus_config(  );
-    init_cache(  );
-    init_eport(  );
-    init_flexcan(  );
-    init_power_management(  );
-    init_dma_timers(  );
-    init_interrupt_timers(  );
-    init_watchdog_timers(  );
-    init_pin_assignments(  );
-    init_sdram_controller(  );
-
-    /* Initialise interrupt controller */
-    init_interrupt_controller(  );
-}
-
-/*********************************************************************
-* disable_interrupts - Disable all interrupt sources                 *
-**********************************************************************/
-static void
-disable_interrupts( void )
-{
-    vuint8         *p;
-    int             i;
-
-
-    /* Set ICR008-ICR063 to 0x0 */
-    p = ( vuint8 * ) & MCF_INTC0_ICR8;
-    for( i = 8; i <= 63; i++ )
-        *p++ = 0x0;
-
-    /* Set ICR108-ICR163 to 0x0 */
-    p = ( vuint8 * ) & MCF_INTC1_ICR8;
-    for( i = 108; i <= 163; i++ )
-        *p++ = 0x0;
-}
-
-
-/*********************************************************************
-* disable_watchdog_timer - Disable system watchdog timer             *
-**********************************************************************/
-static void
-disable_watchdog_timer( void )
-{
-
-    /* Disable Core Watchdog Timer */
-    MCF_SCM_CWCR = 0;
-}
-
-/*********************************************************************
-* disable_cache - Disable and invalidate cache                       *
-**********************************************************************/
-static void
-disable_cache( void )
-{
-    asm ( "move.l   #0x01000000, %d0" );
-    asm ( "movec    %d0, %CACR" );
-}
-
-/*********************************************************************
-* init_basics - Configuration Information & VBR                      *
-**********************************************************************/
-static void
-init_basics( void )
-{
-    int             i;
-    extern uint32   __RAMVEC[];
-    extern uint32   __ROMVEC[];
-
-    /* Transfer size not driven on SIZ[1:0] pins during external cycles
-       Processor Status (PST) and Debug Data (DDATA) functions disabled
-       Bus monitor disabled
-       Output pads configured for full strength
-     */
-    MCF_CCM_CCR = ( 0x1 << 15 ) | MCF_CCM_CCR_BME;
-
-    /* Set up RAM vectors */
-    for( i = 0; i < 256; i++ )
-
-    {
-        __RAMVEC[i] = __ROMVEC[i];
-    }
-    asm( "move.l   %0,%%d0": :"i"( __RAMVEC ) );
-    asm( "movec    %d0,%vbr" );
-}
-
-
-/*********************************************************************
-* init_clock_config - Clock Module                                   *
-**********************************************************************/
-static void
-init_clock_config( void )
-{
-    /* Clock module uses normal PLL mode with 25.0000 MHz external reference (Fref)
-       MFD = 0, RFD = 1
-       Bus clock frequency = 25.00 MHz
-       Processor clock frequency = 2 x bus clock = 50.00 MHz
-       Frequency Modulation disabled
-       Loss of clock detection disabled
-       Reset/Interrupt on loss of lock disabled
-     */
-    MCF_FMPLL_SYNCR = 0x00100000;       /* Set RFD=RFD+1 to avoid frequency overshoot */
-    while( ( MCF_FMPLL_SYNSR & 0x08 ) == 0 )    /* Wait for PLL to lock */
-        ;
-    MCF_FMPLL_SYNCR = 0x00080000;       /* Set desired RFD */
-    while( ( MCF_FMPLL_SYNSR & 0x08 ) == 0 )    /* Wait for PLL to lock */
-        ;
-}
-
-
-/*********************************************************************
-* init_ipsbar - Internal Peripheral System Base Address (IPSBAR)     *
-**********************************************************************/
-static void
-init_ipsbar( void )
-{
-    extern int  __SRAM;
-
-    /* Base address of internal peripherals (IPSBAR) = 0x40000000
-
-       Note: Processor powers up with IPS base address = 0x40000000
-       Write to IPS base + 0x00000000 to set new value
-     */
-    *( vuint32 * ) 0x40000000 = ( vuint32 ) __IPSBAR + 1;
-
-    /* Configure RAMBAR in SCM module and allow dual-ported access. */
-    MCF_SCM_RAMBAR = ( uint32 ) &__SRAM | MCF_SCM_RAMBAR_BDE;
-}
-
-/*********************************************************************
-* init_chip_selects - Chip Select Module                             *
-**********************************************************************/
-static void
-init_chip_selects( void )
-{
-    extern void __FLASH;
-    uint32 FLASH_ADDR = (uint32)&__FLASH;
-
-    /* Chip Select 0 - External Flash */
-    MCF_CS_CSAR0 = MCF_CS_CSAR_BA( FLASH_ADDR );
-    MCF_CS_CSCR0 = ( 0
-                     | MCF_CS_CSCR_IWS( 6 )
-                     | MCF_CS_CSCR_AA | MCF_CS_CSCR_PS_16 );
-    MCF_CS_CSMR0 = MCF_CS_CSMR_BAM_2M | MCF_CS_CSMR_V;
-
-    /* Chip Select 1 disabled (CSMR1[V] = 0) */
-    MCF_CS_CSAR1 = 0;
-    MCF_CS_CSMR1 = 0;
-    MCF_CS_CSCR1 = 0;
-
-    /* Chip Select 2 disabled (CSMR2[V] = 0) */
-    MCF_CS_CSAR2 = 0;
-    MCF_CS_CSMR2 = 0;
-    MCF_CS_CSCR2 = 0;
-
-    /* Chip Select 3 disabled (CSMR3[V] = 0) */
-    MCF_CS_CSAR3 = 0;
-    MCF_CS_CSMR3 = 0;
-    MCF_CS_CSCR3 = 0;
-
-    /* Chip Select 4 disabled (CSMR4[V] = 0) */
-    MCF_CS_CSAR4 = 0;
-    MCF_CS_CSMR4 = 0;
-    MCF_CS_CSCR4 = 0;
-
-    /* Chip Select 5 disabled (CSMR5[V] = 0) */
-    MCF_CS_CSAR5 = 0;
-    MCF_CS_CSMR5 = 0;
-    MCF_CS_CSCR5 = 0;
-
-    /* Chip Select 6 disabled (CSMR6[V] = 0) */
-    MCF_CS_CSAR6 = 0;
-    MCF_CS_CSMR6 = 0;
-    MCF_CS_CSCR6 = 0;
-
-    /* Chip Select 7 disabled (CSMR7[V] = 0) */
-    MCF_CS_CSAR7 = 0;
-    MCF_CS_CSMR7 = 0;
-    MCF_CS_CSCR7 = 0;
-}
-
-/*********************************************************************
-* init_bus_config - Internal Bus Arbitration                         *
-**********************************************************************/
-static void
-init_bus_config( void )
-{
-
-    /* Use round robin arbitration scheme
-       Assigned priorities (highest first):
-       Ethernet
-       DMA Controller
-       ColdFire Core
-       DMA bandwidth control disabled
-       Park on last active bus master
-     */
-    MCF_SCM_MPARK =
-        MCF_SCM_MPARK_M3_PRTY( 0x3 ) | MCF_SCM_MPARK_M2_PRTY( 0x2 ) |
-        MCF_SCM_MPARK_M1_PRTY( 0x1 );
-}
-
-/*********************************************************************
-* init_cache - Instruction/Data Cache                                *
-**********************************************************************/
-static void
-init_cache( void )
-{
-    /* Configured as split cache: 4 KByte instruction cache and 4 Kbyte data cache
-       ACR0: Don't cache accesses to 16 MB memory region at address $20000000
-       ACR1: Don't cache accesses to 1 GB memory region at address $40000000
-       CACR: Cache accesses to the rest of memory
-    */
-    asm("move.l   #0x80000000,%d0");
-    asm("movec    %d0,%CACR");
-    asm("move.l   #0x2000c040,%d0");
-    asm("movec    %d0,%ACR0");
-    asm("move.l   #0x403fc040,%d0");
-    asm("movec    %d0,%ACR1");
-
-    /* Instruction/Data cache disabled. */
-    //asm( "move.l   #0x00000000, %d0" );
-    //asm( "movec    %d0,%cacr" );
-}
-
-/*********************************************************************
-* init_eport - Edge Port Module (EPORT)                              *
-**********************************************************************/
-static void
-init_eport( void )
-{
-
-    /* Pins 1-7 configured as GPIO inputs */
-    MCF_EPORT_EPPAR = 0;
-    MCF_EPORT_EPDDR = 0;
-    MCF_EPORT_EPIER = 0;
-}
-
-/*********************************************************************
-* init_flexcan - FlexCAN Module                                      *
-**********************************************************************/
-static void
-init_flexcan( void )
-{
-
-    /* FlexCAN controller 0 disabled (CANMCR0[MDIS]=1) */
-    MCF_CAN_IMASK0 = 0;
-    MCF_CAN_RXGMASK0 = MCF_CAN_RXGMASK_MI( 0x1fffffff );
-    MCF_CAN_RX14MASK0 = MCF_CAN_RX14MASK_MI( 0x1fffffff );
-    MCF_CAN_RX15MASK0 = MCF_CAN_RX15MASK_MI( 0x1fffffff );
-    MCF_CAN_CANCTRL0 = 0;
-    MCF_CAN_CANMCR0 =
-        MCF_CAN_CANMCR_MDIS | MCF_CAN_CANMCR_FRZ | MCF_CAN_CANMCR_HALT |
-        MCF_CAN_CANMCR_SUPV | MCF_CAN_CANMCR_MAXMB( 0xf );
-
-    /* FlexCAN controller 1 disabled (CANMCR1[MDIS]=1) */
-    MCF_CAN_IMASK1 = 0;
-    MCF_CAN_RXGMASK1 = MCF_CAN_RXGMASK_MI( 0x1fffffff );
-    MCF_CAN_RX14MASK1 = MCF_CAN_RX14MASK_MI( 0x1fffffff );
-    MCF_CAN_RX15MASK1 = MCF_CAN_RX15MASK_MI( 0x1fffffff );
-    MCF_CAN_CANCTRL1 = 0;
-    MCF_CAN_CANMCR1 =
-        MCF_CAN_CANMCR_MDIS | MCF_CAN_CANMCR_FRZ | MCF_CAN_CANMCR_HALT |
-        MCF_CAN_CANMCR_SUPV | MCF_CAN_CANMCR_MAXMB( 0xf );
-}
-
-/*********************************************************************
-* init_power_management - Power Management                           *
-**********************************************************************/
-static void
-init_power_management( void )
-{
-
-    /* On executing STOP instruction, processor enters RUN mode
-       Mode is exited when an interrupt of level 1 or higher is received
-     */
-    MCF_SCM_LPICR = MCF_SCM_LPICR_ENBSTOP;
-    MCF_CCM_LPCR = 0;
-}
-
-/*********************************************************************
-* init_sdram_controller - SDRAM Controller                           *
-**********************************************************************/
-static void
-init_sdram_controller( void )
-{
-    extern void __SDRAM;
-    uint32 SDRAM_ADDR = (uint32)&__SDRAM;
-    int             i;
-
-
-    /*
-     * Check to see if the SDRAM has already been initialized
-     * by a run control tool
-     */
-    if( !( MCF_SDRAMC_DACR0 & MCF_SDRAMC_DACR0_RE ) )
-    {
-        /* Initialize DRAM Control Register: DCR */
-        MCF_SDRAMC_DCR = ( MCF_SDRAMC_DCR_RTIM( 1 ) |
-                           MCF_SDRAMC_DCR_RC( ( 15 * FSYS_2 ) >> 4 ) );
-
-        /* Initialize DACR0 */
-        MCF_SDRAMC_DACR0 = ( MCF_SDRAMC_DACR0_BA( SDRAM_ADDR >> 18UL ) |
-                             MCF_SDRAMC_DACR0_CASL( 1 ) |
-                             MCF_SDRAMC_DACR0_CBM( 3 ) |
-                             MCF_SDRAMC_DACR0_PS( 0 ) );
-
-        /* Initialize DMR0 */
-        MCF_SDRAMC_DMR0 = ( MCF_SDRAMC_DMR_BAM_16M | MCF_SDRAMC_DMR0_V );
-
-        /* Set IP (bit 3) in DACR */
-        MCF_SDRAMC_DACR0 |= MCF_SDRAMC_DACR0_IP;
-
-        /* Wait 30ns to allow banks to precharge */
-        for( i = 0; i < 5; i++ )
-        {
-            asm volatile    ( " nop" );
-        }
-        /* Write to this block to initiate precharge */
-        *( uint32 * ) ( SDRAM_ADDR ) = 0xA5A59696;
-
-        /* Set RE (bit 15) in DACR */
-        MCF_SDRAMC_DACR0 |= MCF_SDRAMC_DACR0_RE;
-
-        /* Wait for at least 8 auto refresh cycles to occur */
-        for( i = 0; i < 2000; i++ )
-        {
-            asm volatile    ( "nop" );
-        }
-        /* Finish the configuration by issuing the IMRS. */
-        MCF_SDRAMC_DACR0 |= MCF_SDRAMC_DACR0_MRS;
-
-        /* Write to the SDRAM Mode Register */
-        *( uint32 * ) ( SDRAM_ADDR + 0x400 ) = 0xA5A59696;
-    }
-}
-
-/*********************************************************************
-* init_dma_timers - DMA Timer Modules                                *
-**********************************************************************/
-static void
-init_dma_timers( void )
-{
-
-    /* DMA Timer 0 disabled (DTMR0[RST] = 0) */
-    MCF_TIMER_DTMR0 = 0;
-    MCF_TIMER_DTXMR0 = 0;
-    MCF_TIMER_DTRR0 = 0xffffffff;
-
-    /* DMA Timer 1 disabled (DTMR1[RST] = 0) */
-    MCF_TIMER_DTMR1 = 0;
-    MCF_TIMER_DTXMR1 = 0;
-    MCF_TIMER_DTRR1 = 0xffffffff;
-
-    /* DMA Timer 2 disabled (DTMR2[RST] = 0) */
-    MCF_TIMER_DTMR2 = 0;
-    MCF_TIMER_DTXMR2 = 0;
-    MCF_TIMER_DTRR2 = 0xffffffff;
-
-    /* DMA Timer 3 disabled (DTMR3[RST] = 0) */
-    MCF_TIMER_DTMR3 = 0;
-    MCF_TIMER_DTXMR3 = 0;
-    MCF_TIMER_DTRR3 = 0xffffffff;
-}
-
-/**********************************************************************
-* init_interrupt_timers - Programmable Interrupt Timer (PIT) Modules  *
-***********************************************************************/
-static void
-init_interrupt_timers( void )
-{
-
-    /* PIT0 disabled (PCSR0[EN]=0) */
-    MCF_PIT_PCSR0 = 0;
-
-    /* PIT1 disabled (PCSR1[EN]=0) */
-    MCF_PIT_PCSR1 = 0;
-
-    /* PIT2 disabled (PCSR2[EN]=0) */
-    MCF_PIT_PCSR2 = 0;
-
-    /* PIT3 disabled (PCSR3[EN]=0) */
-    MCF_PIT_PCSR3 = 0;
-}
-
-/*********************************************************************
-* init_watchdog_timers - Watchdog Timer Modules                      *
-**********************************************************************/
-static void
-init_watchdog_timers( void )
-{
-
-    /* Watchdog Timer disabled (WCR[EN]=0)
-       NOTE: WCR and WMR cannot be written again until after the
-       processor is reset.
-     */
-    MCF_WTM_WCR = MCF_WTM_WCR_WAIT | MCF_WTM_WCR_DOZE | MCF_WTM_WCR_HALTED;
-    MCF_WTM_WMR = 0xffff;
-
-    /* Core Watchdog Timer disabled (CWCR[CWE]=0) */
-    MCF_SCM_CWCR = 0;
-}
-
-/*********************************************************************
-* init_interrupt_controller - Interrupt Controller                   *
-**********************************************************************/
-static void
-init_interrupt_controller( void )
-{
-
-    /* Configured interrupt sources in order of priority...
-       Level 7:  External interrupt /IRQ7, (initially masked)
-       Level 6:  External interrupt /IRQ6, (initially masked)
-       Level 5:  External interrupt /IRQ5, (initially masked)
-       Level 4:  External interrupt /IRQ4, (initially masked)
-       Level 3:  External interrupt /IRQ3, (initially masked)
-       Level 2:  External interrupt /IRQ2, (initially masked)
-       Level 1:  External interrupt /IRQ1, (initially masked)
-     */
-    MCF_INTC0_ICR1 = 0;
-    MCF_INTC0_ICR2 = 0;
-    MCF_INTC0_ICR3 = 0;
-    MCF_INTC0_ICR4 = 0;
-    MCF_INTC0_ICR5 = 0;
-    MCF_INTC0_ICR6 = 0;
-    MCF_INTC0_ICR7 = 0;
-    MCF_INTC0_ICR8 = 0;
-    MCF_INTC0_ICR9 = 0;
-    MCF_INTC0_ICR10 = 0;
-    MCF_INTC0_ICR11 = 0;
-    MCF_INTC0_ICR12 = 0;
-    MCF_INTC0_ICR13 = 0;
-    MCF_INTC0_ICR14 = 0;
-    MCF_INTC0_ICR15 = 0;
-    MCF_INTC0_ICR17 = 0;
-    MCF_INTC0_ICR18 = 0;
-    MCF_INTC0_ICR19 = 0;
-    MCF_INTC0_ICR20 = 0;
-    MCF_INTC0_ICR21 = 0;
-    MCF_INTC0_ICR22 = 0;
-    MCF_INTC0_ICR23 = 0;
-    MCF_INTC0_ICR24 = 0;
-    MCF_INTC0_ICR25 = 0;
-    MCF_INTC0_ICR26 = 0;
-    MCF_INTC0_ICR27 = 0;
-    MCF_INTC0_ICR28 = 0;
-    MCF_INTC0_ICR29 = 0;
-    MCF_INTC0_ICR30 = 0;
-    MCF_INTC0_ICR31 = 0;
-    MCF_INTC0_ICR32 = 0;
-    MCF_INTC0_ICR33 = 0;
-    MCF_INTC0_ICR34 = 0;
-    MCF_INTC0_ICR35 = 0;
-    MCF_INTC0_ICR36 = 0;
-    MCF_INTC0_ICR37 = 0;
-    MCF_INTC0_ICR38 = 0;
-    MCF_INTC0_ICR39 = 0;
-    MCF_INTC0_ICR40 = 0;
-    MCF_INTC0_ICR41 = 0;
-    MCF_INTC0_ICR42 = 0;
-    MCF_INTC0_ICR43 = 0;
-    MCF_INTC0_ICR44 = 0;
-    MCF_INTC0_ICR45 = 0;
-    MCF_INTC0_ICR46 = 0;
-    MCF_INTC0_ICR47 = 0;
-    MCF_INTC0_ICR48 = 0;
-    MCF_INTC0_ICR49 = 0;
-    MCF_INTC0_ICR50 = 0;
-    MCF_INTC0_ICR51 = 0;
-    MCF_INTC0_ICR52 = 0;
-    MCF_INTC0_ICR53 = 0;
-    MCF_INTC0_ICR54 = 0;
-    MCF_INTC0_ICR55 = 0;
-    MCF_INTC0_ICR56 = 0;
-    MCF_INTC0_ICR57 = 0;
-    MCF_INTC0_ICR58 = 0;
-    MCF_INTC0_ICR59 = 0;
-    MCF_INTC0_ICR60 = 0;
-    MCF_INTC1_ICR8 = 0;
-    MCF_INTC1_ICR9 = 0;
-    MCF_INTC1_ICR10 = 0;
-    MCF_INTC1_ICR11 = 0;
-    MCF_INTC1_ICR12 = 0;
-    MCF_INTC1_ICR13 = 0;
-    MCF_INTC1_ICR14 = 0;
-    MCF_INTC1_ICR15 = 0;
-    MCF_INTC1_ICR16 = 0;
-    MCF_INTC1_ICR17 = 0;
-    MCF_INTC1_ICR18 = 0;
-    MCF_INTC1_ICR19 = 0;
-    MCF_INTC1_ICR20 = 0;
-    MCF_INTC1_ICR21 = 0;
-    MCF_INTC1_ICR22 = 0;
-    MCF_INTC1_ICR23 = 0;
-    MCF_INTC1_ICR24 = 0;
-    MCF_INTC1_ICR25 = 0;
-    MCF_INTC1_ICR27 = 0;
-    MCF_INTC1_ICR28 = 0;
-    MCF_INTC1_ICR29 = 0;
-    MCF_INTC1_ICR30 = 0;
-    MCF_INTC1_ICR31 = 0;
-    MCF_INTC1_ICR32 = 0;
-    MCF_INTC1_ICR33 = 0;
-    MCF_INTC1_ICR34 = 0;
-    MCF_INTC1_ICR35 = 0;
-    MCF_INTC1_ICR36 = 0;
-    MCF_INTC1_ICR37 = 0;
-    MCF_INTC1_ICR38 = 0;
-    MCF_INTC1_ICR39 = 0;
-    MCF_INTC1_ICR40 = 0;
-    MCF_INTC1_ICR41 = 0;
-    MCF_INTC1_ICR42 = 0;
-    MCF_INTC1_ICR59 = 0;
-    MCF_INTC0_IMRH = 0xffffffff;
-    MCF_INTC0_IMRL =
-        MCF_INTC0_IMRL_INT_MASK31 | MCF_INTC0_IMRL_INT_MASK30 |
-        MCF_INTC0_IMRL_INT_MASK29 | MCF_INTC0_IMRL_INT_MASK28 |
-        MCF_INTC0_IMRL_INT_MASK27 | MCF_INTC0_IMRL_INT_MASK26 |
-        MCF_INTC0_IMRL_INT_MASK25 | MCF_INTC0_IMRL_INT_MASK24 |
-        MCF_INTC0_IMRL_INT_MASK23 | MCF_INTC0_IMRL_INT_MASK22 |
-        MCF_INTC0_IMRL_INT_MASK21 | MCF_INTC0_IMRL_INT_MASK20 |
-        MCF_INTC0_IMRL_INT_MASK19 | MCF_INTC0_IMRL_INT_MASK18 |
-        MCF_INTC0_IMRL_INT_MASK17 | MCF_INTC0_IMRL_INT_MASK16 |
-        MCF_INTC0_IMRL_INT_MASK15 | MCF_INTC0_IMRL_INT_MASK14 |
-        MCF_INTC0_IMRL_INT_MASK13 | MCF_INTC0_IMRL_INT_MASK12 |
-        MCF_INTC0_IMRL_INT_MASK11 | MCF_INTC0_IMRL_INT_MASK10 |
-        MCF_INTC0_IMRL_INT_MASK9 | MCF_INTC0_IMRL_INT_MASK8 |
-        MCF_INTC0_IMRL_INT_MASK7 | MCF_INTC0_IMRL_INT_MASK6 |
-        MCF_INTC0_IMRL_INT_MASK5 | MCF_INTC0_IMRL_INT_MASK4 |
-        MCF_INTC0_IMRL_INT_MASK3 | MCF_INTC0_IMRL_INT_MASK2 |
-        MCF_INTC0_IMRL_INT_MASK1;
-    MCF_INTC1_IMRH = 0xffffffff;
-    MCF_INTC1_IMRL =
-        MCF_INTC1_IMRL_INT_MASK31 | MCF_INTC1_IMRL_INT_MASK30 |
-        MCF_INTC1_IMRL_INT_MASK29 | MCF_INTC1_IMRL_INT_MASK28 |
-        MCF_INTC1_IMRL_INT_MASK27 | MCF_INTC1_IMRL_INT_MASK26 |
-        MCF_INTC1_IMRL_INT_MASK25 | MCF_INTC1_IMRL_INT_MASK24 |
-        MCF_INTC1_IMRL_INT_MASK23 | MCF_INTC1_IMRL_INT_MASK22 |
-        MCF_INTC1_IMRL_INT_MASK21 | MCF_INTC1_IMRL_INT_MASK20 |
-        MCF_INTC1_IMRL_INT_MASK19 | MCF_INTC1_IMRL_INT_MASK18 |
-        MCF_INTC1_IMRL_INT_MASK17 | MCF_INTC1_IMRL_INT_MASK16 |
-        MCF_INTC1_IMRL_INT_MASK15 | MCF_INTC1_IMRL_INT_MASK14 |
-        MCF_INTC1_IMRL_INT_MASK13 | MCF_INTC1_IMRL_INT_MASK12 |
-        MCF_INTC1_IMRL_INT_MASK11 | MCF_INTC1_IMRL_INT_MASK10 |
-        MCF_INTC1_IMRL_INT_MASK9 | MCF_INTC1_IMRL_INT_MASK8 |
-        MCF_INTC1_IMRL_INT_MASK7 | MCF_INTC1_IMRL_INT_MASK6 |
-        MCF_INTC1_IMRL_INT_MASK5 | MCF_INTC1_IMRL_INT_MASK4 |
-        MCF_INTC1_IMRL_INT_MASK3 | MCF_INTC1_IMRL_INT_MASK2 |
-        MCF_INTC1_IMRL_INT_MASK1;
-}
-
-/*********************************************************************
-* init_pin_assignments - Pin Assignment and General Purpose I/O      *
-**********************************************************************/
-static void
-init_pin_assignments( void )
-{
-
-    /* Pin assignments for port ADDR
-       Pins are all GPIO inputs
-     */
-    MCF_GPIO_PDDR_APDDR = 0;
-    MCF_GPIO_PAR_AD = MCF_GPIO_PAR_AD_PAR_ADDR23
-        | MCF_GPIO_PAR_AD_PAR_ADDR22
-        | MCF_GPIO_PAR_AD_PAR_ADDR21 | MCF_GPIO_PAR_AD_PAR_DATAL;
-
-    /* Pin assignments for ports DATAH and DATAL
-       Pins are all GPIO inputs
-     */
-    MCF_GPIO_PDDR_DATAH = 0;
-    MCF_GPIO_PDDR_DATAL = 0;
-
-    /* Pin assignments for port BUSCTL
-       Pin /OE        : External bus output enable, /OE
-       Pin /TA        : External bus transfer acknowledge, /TA
-       Pin /TEA       : External bus transfer error acknowledge, /TEA
-       Pin R/W        : External bus read/write indication, R/W
-       Pin TSIZ1      : External bus transfer size TSIZ1 or DMA acknowledge /DACK1
-       Pin TSIZ0      : External bus transfer size TSIZ0 or DMA acknowledge /DACK0
-       Pin /TS        : External bus transfer start, /TS
-       Pin /TIP       : External bus transfer in progess, /TIP
-     */
-    MCF_GPIO_PDDR_BUSCTL = 0;
-    MCF_GPIO_PAR_BUSCTL =
-        MCF_GPIO_PAR_BUSCTL_PAR_OE | MCF_GPIO_PAR_BUSCTL_PAR_TA |
-        MCF_GPIO_PAR_BUSCTL_PAR_TEA( 0x3 ) | MCF_GPIO_PAR_BUSCTL_PAR_RWB |
-        MCF_GPIO_PAR_BUSCTL_PAR_TSIZ1 | MCF_GPIO_PAR_BUSCTL_PAR_TSIZ0 |
-        MCF_GPIO_PAR_BUSCTL_PAR_TS( 0x3 ) |
-        MCF_GPIO_PAR_BUSCTL_PAR_TIP( 0x3 );
-
-    /* Pin assignments for port BS
-       Pin /BS3       : External byte strobe /BS3
-       Pin /BS2       : External byte strobe /BS2
-       Pin /BS1       : External byte strobe /BS1
-       Pin /BS0       : External byte strobe /BS0
-     */
-    MCF_GPIO_PDDR_BS = 0;
-    MCF_GPIO_PAR_BS =
-        MCF_GPIO_PAR_BS_PAR_BS3 | MCF_GPIO_PAR_BS_PAR_BS2 |
-        MCF_GPIO_PAR_BS_PAR_BS1 | MCF_GPIO_PAR_BS_PAR_BS0;
-
-    /* Pin assignments for port CS
-       Pin /CS7       : Chip select /CS7
-       Pin /CS6       : Chip select /CS6
-       Pin /CS5       : Chip select /CS5
-       Pin /CS4       : Chip select /CS4
-       Pin /CS3       : Chip select /CS3
-       Pin /CS2       : Chip select /CS2
-       Pin /CS1       : Chip select /CS1
-     */
-    MCF_GPIO_PDDR_CS = 0;
-    MCF_GPIO_PAR_CS =
-        MCF_GPIO_PAR_CS_PAR_CS7 | MCF_GPIO_PAR_CS_PAR_CS6 |
-        MCF_GPIO_PAR_CS_PAR_CS5 | MCF_GPIO_PAR_CS_PAR_CS4 |
-        MCF_GPIO_PAR_CS_PAR_CS3 | MCF_GPIO_PAR_CS_PAR_CS2 |
-        MCF_GPIO_PAR_CS_PAR_CS1;
-
-    /* Pin assignments for port SDRAM
-       Pin /SD_WE     : SDRAM controller /SD_WE
-       Pin /SD_SCAS   : SDRAM controller /SD_SCAS
-       Pin /SD_SRAS   : SDRAM controller /SD_SRAS
-       Pin /SD_SCKE   : SDRAM controller /SD_SCKE
-       Pin /SD_CS1    : SDRAM controller /SD_CS1
-       Pin /SD_CS0    : SDRAM controller /SD_CS0
-     */
-    MCF_GPIO_PDDR_SDRAM = 0;
-    MCF_GPIO_PAR_SDRAM =
-        MCF_GPIO_PAR_SDRAM_PAR_SDWE | MCF_GPIO_PAR_SDRAM_PAR_SCAS |
-        MCF_GPIO_PAR_SDRAM_PAR_SRAS | MCF_GPIO_PAR_SDRAM_PAR_SCKE |
-        MCF_GPIO_PAR_SDRAM_PAR_SDCS1 | MCF_GPIO_PAR_SDRAM_PAR_SDCS0;
-
-    /* Pin assignments for port FECI2C
-       Pins are all GPIO inputs
-     */
-    MCF_GPIO_PDDR_FECI2C = 0;
-    MCF_GPIO_PAR_FECI2C =
-        MCF_GPIO_PAR_FECI2C_PAR_EMDC_FEC | MCF_GPIO_PAR_FECI2C_PAR_EMDIO_FEC;
-
-    /* Pin assignments for port UARTL
-       Pins are all GPIO inputs
-     */
-    MCF_GPIO_PDDR_UARTL = 0;
-    MCF_GPIO_PAR_UART = 0;
-
-    /* Pin assignments for port UARTH
-       Pin U2TXD      : GPIO input
-       Pin U2RXD      : GPIO input
-       Pin /IRQ2      : Interrupt request /IRQ2 or GPIO
-     */
-    MCF_GPIO_PDDR_UARTH = 0;
-
-    /* Pin assignments for port QSPI
-       Pins are all GPIO inputs
-     */
-    MCF_GPIO_PDDR_QSPI = 0;
-    MCF_GPIO_PAR_QSPI = 0;
-
-    /* Pin assignments for port TIMER
-       Pins are all GPIO inputs
-     */
-    MCF_GPIO_PDDR_TIMER = 0;
-    MCF_GPIO_PAR_TIMER = 0;
-
-    /* Pin assignments for port ETPU
-       Pins are all GPIO inputs
-     */
-    MCF_GPIO_PDDR_ETPU = 0;
-    MCF_GPIO_PAR_ETPU = 0;
-}
diff --git a/Demo/lwIP_MCF5235_GCC/system/mcf5xxx.S b/Demo/lwIP_MCF5235_GCC/system/mcf5xxx.S
deleted file mode 100644
index d810a2fdc..000000000
--- a/Demo/lwIP_MCF5235_GCC/system/mcf5xxx.S
+++ /dev/null
@@ -1,249 +0,0 @@
-/*
- * Lowest level routines for all ColdFire processors. Based on the
- * MCF523x examples from Freescale.
- *
- * Freescale explicitly grants the redistribution and modification
- * of these source files. The complete licensing information is
- * available in the file LICENSE_FREESCALE.TXT.
- *
- * Modifications Copyright (c) 2006 Christian Walter 
- *
- * File: $Id: mcf5xxx.S,v 1.3 2006/09/24 22:50:23 wolti Exp $
- */
-
-  .global asm_set_ipl
-  .global _asm_set_ipl
-  .global mcf5xxx_wr_cacr
-  .global _mcf5xxx_wr_cacr
-  .global mcf5xxx_wr_acr0
-  .global _mcf5xxx_wr_acr0
-  .global mcf5xxx_wr_acr1
-  .global _mcf5xxx_wr_acr1
-  .global mcf5xxx_wr_acr2
-  .global _mcf5xxx_wr_acr2
-  .global mcf5xxx_wr_acr3
-  .global _mcf5xxx_wr_acr3
-  .global mcf5xxx_wr_other_sp
-  .global _mcf5xxx_wr_other_sp
-  .global mcf5xxx_wr_other_a7
-  .global _mcf5xxx_wr_other_a7
-  .global mcf5xxx_wr_vbr
-  .global _mcf5xxx_wr_vbr
-  .global mcf5xxx_wr_macsr
-  .global _mcf5xxx_wr_macsr
-  .global mcf5xxx_wr_mask
-  .global _mcf5xxx_wr_mask
-  .global mcf5xxx_wr_acc0
-  .global _mcf5xxx_wr_acc0
-  .global mcf5xxx_wr_accext01
-  .global _mcf5xxx_wr_accext01
-  .global mcf5xxx_wr_accext23
-  .global _mcf5xxx_wr_accext23
-  .global mcf5xxx_wr_acc1
-  .global _mcf5xxx_wr_acc1
-  .global mcf5xxx_wr_acc2
-  .global _mcf5xxx_wr_acc2
-  .global mcf5xxx_wr_acc3
-  .global _mcf5xxx_wr_acc3
-  .global mcf5xxx_wr_sr
-  .global _mcf5xxx_wr_sr
-  .global mcf5xxx_wr_rambar0
-  .global _mcf5xxx_wr_rambar0
-  .global mcf5xxx_wr_rambar1
-  .global _mcf5xxx_wr_rambar1
-  .global mcf5xxx_wr_mbar
-  .global _mcf5xxx_wr_mbar
-  .global mcf5xxx_wr_mbar0
-  .global _mcf5xxx_wr_mbar0
-  .global mcf5xxx_wr_mbar1
-  .global _mcf5xxx_wr_mbar1
-
-  .text
-
-/********************************************************************/
-/*
- * This routines changes the IPL to the value passed into the routine.
- * It also returns the old IPL value back.
- * Calling convention from C:
- *   old_ipl = asm_set_ipl(new_ipl);
- * For the Diab Data C compiler, it passes return value thru D0.
- * Note that only the least significant three bits of the passed
- * value are used.
- */
-
-asm_set_ipl:
-_asm_set_ipl:
-  link  a6,#-8
-  movem.l d6-d7,(sp)
-
-  move.w  sr,d7   /* current sr  */
-
-  move.l  d7,d0   /* prepare return value  */
-  andi.l  #0x0700,d0  /* mask out IPL  */
-  lsr.l #8,d0   /* IPL   */
-
-  move.l  8(a6),d6  /* get argument  */
-  andi.l  #0x07,d6    /* least significant three bits  */
-  lsl.l #8,d6   /* move over to make mask  */
-
-  andi.l  #0x0000F8FF,d7  /* zero out current IPL  */
-  or.l  d6,d7     /* place new IPL in sr   */
-  move.w  d7,sr
-
-  movem.l (sp),d6-d7
-  lea   8(sp),sp
-  unlk  a6
-  rts
-
-/********************************************************************/
-/*
- * These routines write to the special purpose registers in the ColdFire
- * core.  Since these registers are write-only in the supervisor model,
- * no corresponding read routines exist.
- */
-
-mcf5xxx_wr_cacr:
-_mcf5xxx_wr_cacr:
-    move.l  4(sp),d0
-    .long   0x4e7b0002      /* movec d0,cacr   */
-    nop
-    rts
-
-mcf5xxx_wr_acr0:
-_mcf5xxx_wr_acr0:
-    move.l  4(sp),d0
-    .long   0x4e7b0004      /* movec d0,ACR0  */
-    nop
-    rts
-
-mcf5xxx_wr_acr1:
-_mcf5xxx_wr_acr1:
-    move.l  4(sp),d0
-    .long   0x4e7b0005      /* movec d0,ACR1  */
-    nop
-    rts
-
-mcf5xxx_wr_acr2:
-_mcf5xxx_wr_acr2:
-    move.l  4(sp),d0
-    .long   0x4e7b0006      /* movec d0,ACR2  */
-    nop
-    rts
-
-mcf5xxx_wr_acr3:
-_mcf5xxx_wr_acr3:
-    move.l  4(sp),d0
-    .long   0x4e7b0007      /* movec d0,ACR3  */
-    nop
-    rts
-
-mcf5xxx_wr_other_sp:
-_mcf5xxx_wr_other_sp:
-mcf5xxx_wr_other_a7:
-_mcf5xxx_wr_other_a7:
-  move.l  4(sp),d0
-  .long 0x4e7b0800    /* movec d0,OTHER_A7 */
-  nop
-  rts
-
-mcf5xxx_wr_vbr:
-_mcf5xxx_wr_vbr:
-  move.l  4(sp),d0
-  .long 0x4e7b0801    /* movec d0,VBR */
-  nop
-  rts
-
-mcf5xxx_wr_macsr:
-_mcf5xxx_wr_macsr:
-    move.l  4(sp),d0
-    .long   0x4e7b0804      /* movec d0,MACSR */
-    nop
-    rts
-
-mcf5xxx_wr_mask:
-_mcf5xxx_wr_mask:
-    move.l  4(sp),d0
-    .long   0x4e7b0805      /* movec d0,MASK  */
-    nop
-    rts
-
-mcf5xxx_wr_acc0:
-_mcf5xxx_wr_acc0:
-    move.l  4(sp),d0
-    .long   0x4e7b0806      /* movec d0,ACC0  */
-    nop
-    rts
-
-mcf5xxx_wr_accext01:
-_mcf5xxx_wr_accext01:
-    move.l  4(sp),d0
-    .long   0x4e7b0807      /* movec d0,ACCEXT01  */
-    nop
-    rts
-
-mcf5xxx_wr_accext23:
-_mcf5xxx_wr_accext23:
-    move.l  4(sp),d0
-    .long   0x4e7b0808      /* movec d0,ACCEXT23  */
-    nop
-    rts
-
-mcf5xxx_wr_acc1:
-_mcf5xxx_wr_acc1:
-    move.l  4(sp),d0
-    .long   0x4e7b0809      /* movec d0,ACC1  */
-    nop
-    rts
-
-mcf5xxx_wr_acc2:
-_mcf5xxx_wr_acc2:
-    move.l  4(sp),d0
-    .long   0x4e7b080A      /* movec d0,ACC2  */
-    nop
-    rts
-
-mcf5xxx_wr_acc3:
-_mcf5xxx_wr_acc3:
-    move.l  4(sp),d0
-    .long   0x4e7b080B      /* movec d0,ACC3  */
-    nop
-    rts
-
-mcf5xxx_wr_sr:
-_mcf5xxx_wr_sr:
-  move.l  4(sp),d0
-  move.w  d0,SR
-  rts
-
-mcf5xxx_wr_rambar0:
-_mcf5xxx_wr_rambar0:
-    move.l  4(sp),d0
-    .long   0x4e7b0C04      /* movec d0,RAMBAR0 */
-    nop
-    rts
-
-mcf5xxx_wr_rambar1:
-_mcf5xxx_wr_rambar1:
-    move.l  4(sp),d0
-    .long   0x4e7b0C05      /* movec d0,RAMBAR1 */
-    nop
-    rts
-
-mcf5xxx_wr_mbar:
-_mcf5xxx_wr_mbar:
-mcf5xxx_wr_mbar0:
-_mcf5xxx_wr_mbar0:
-    move.l  4(sp),d0
-    .long   0x4e7b0C0F      /* movec d0,MBAR0 */
-    nop
-    rts
-
-mcf5xxx_wr_mbar1:
-_mcf5xxx_wr_mbar1:
-    move.l  4(sp),d0
-    .long   0x4e7b0C0E      /* movec d0,MBAR1 */
-    nop
-    rts
-
-  .end
-/********************************************************************/
diff --git a/Demo/lwIP_MCF5235_GCC/system/newlib.c b/Demo/lwIP_MCF5235_GCC/system/newlib.c
deleted file mode 100644
index 82ffbb0aa..000000000
--- a/Demo/lwIP_MCF5235_GCC/system/newlib.c
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
-    FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter.
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-
-    FreeRTOS is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with FreeRTOS; if not, write to the Free Software
-    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-
-    A special exception to the GPL can be applied should you wish to distribute
-    a combined work that includes FreeRTOS, without being obliged to provide
-    the source code for any proprietary components.  See the licensing section
-    of http://www.FreeRTOS.org for full details of how and when the exception
-    can be applied.
-
-    ***************************************************************************
-    See http://www.FreeRTOS.org for documentation, latest information, license
-    and contact details.  Please ensure to read the configuration and relevant
-    port sections of the online documentation.
-    ***************************************************************************
-*/
-
-/* ------------------------ System includes ------------------------------- */
-#include 
-#include 
-#include 
-#include 
-
-/* ------------------------ FreeRTOS includes ----------------------------- */
-#include 
-#include 
-
-/* ------------------------ Prototypes ------------------------------------ */
-void vSerialPutStringNOISR( xComPortHandle pxPort,
-                            const signed portCHAR * const pcString,
-                            unsigned portSHORT usStringLength );
-
-/* ------------------------ Start implementation -------------------------- */
-void
-_exit( int status )
-{
-    asm volatile    ( "halt" );
-
-    for( ;; );
-}
-
-pid_t
-getpid( void )
-{
-    return 0;
-}
-
-int
-kill( pid_t pid, int sig )
-{
-    _exit( 0 );
-}
-
-int
-close( int fd )
-{
-    return 0;
-}
-
-int
-fstat( int fd, struct stat *buf )
-{
-    buf->st_mode = S_IFCHR;
-    buf->st_blksize = 0;
-    return 0;
-}
-
-ssize_t
-write( int fd, const void *buf, size_t nbytes )
-{
-    ssize_t res = nbytes;
-    extern xComPortHandle xSTDComPort;
-    switch ( fd )
-    {
-        case STDERR_FILENO:
-            vSerialPutStringNOISR( xSTDComPort,
-                                   ( const signed portCHAR * const )buf,
-                                   ( unsigned portSHORT )nbytes );
-            break;
-        case STDOUT_FILENO:
-            vSerialPutString( xSTDComPort,
-                              ( const signed portCHAR * const)buf,
-                              ( unsigned portSHORT )nbytes );
-            break;
-        default:
-            errno = EIO;
-            res = -1;
-            break;
-    }
-    return res;
-}
-
-int
-read( int fd, void *buf, size_t nbytes )
-{
-    switch ( fd )
-    {
-        default:
-            errno = EIO;
-            return -1;
-    }
-}
-
-int
-isatty( int fd )
-{
-    return 0;
-}
-
-off_t
-lseek( int fd, off_t offset, int whence )
-{
-    errno = EIO;
-    return ( off_t ) - 1;
-}
-
-extern char     _end[];
-char           *heap_ptr;
-
-void           *
-sbrk( ptrdiff_t nbytes )
-{
-    char           *base;
-
-    if( !heap_ptr )
-        heap_ptr = ( char * )&_end;
-    base = heap_ptr;
-    heap_ptr += nbytes;
-
-    return base;
-}
diff --git a/Demo/lwIP_MCF5235_GCC/system/serial.c b/Demo/lwIP_MCF5235_GCC/system/serial.c
deleted file mode 100644
index f1fb6a368..000000000
--- a/Demo/lwIP_MCF5235_GCC/system/serial.c
+++ /dev/null
@@ -1,298 +0,0 @@
-/*
-    FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter.
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-
-    FreeRTOS is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with FreeRTOS; if not, write to the Free Software
-    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-
-    A special exception to the GPL can be applied should you wish to distribute
-    a combined work that includes FreeRTOS, without being obliged to provide
-    the source code for any proprietary components.  See the licensing section
-    of http://www.FreeRTOS.org for full details of how and when the exception
-    can be applied.
-
-    ***************************************************************************
-    See http://www.FreeRTOS.org for documentation, latest information, license
-    and contact details.  Please ensure to read the configuration and relevant
-    port sections of the online documentation.
-    ***************************************************************************
-*/
-
-/* ------------------------ MCF523x includes ------------------------------ */
-#include "mcf5xxx.h"
-#include "mcf523x.h"
-
-/* ------------------------ FreeRTOS includes ----------------------------- */
-#include "FreeRTOS.h"
-#include "queue.h"
-#include "task.h"
-
-#include "serial.h"
-
-/* ----------------------- Defines ----------------------------------------- */
-#define BAUDRATE_VALUE(fsys, baud)      ( ( fsys )/(32UL * baud) )
-#define MCF_UART_VECTOR                 ( 64 + 13 )
-#define COM_NIFACE                      1
-#define COM_BLOCK_RETRYTIME             10
-
-/* ------------------------ Static functions ------------------------------ */
-static void     prvSerialISR( void );
-
-/* ------------------------ Static variables ------------------------------ */
-typedef struct
-{
-    portBASE_TYPE xInitialized;
-    xQueueHandle xRXChars;
-    xQueueHandle xTXChars;
-} xComPortIF_t;
-
-static xComPortIF_t xComPortIF[ COM_NIFACE ];
-
-/* ------------------------ Begin implementation -------------------------- */
-xComPortHandle
-xSerialPortInitMinimal( unsigned portLONG ulWantedBaud,
-                        unsigned portBASE_TYPE uxQueueLength )
-{
-    extern void     ( *__RAMVEC[] ) (  );
-    xComPortHandle xReturn;
-    portBASE_TYPE xOldIPL;
-
-    /* Create the queues used to hold Rx and Tx characters. */
-    xComPortIF[ 0 ].xRXChars =
-        xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE )sizeof( signed portCHAR ) );
-    xComPortIF[ 0 ].xTXChars =
-        xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE )sizeof( signed portCHAR ) );
-
-    /* If the queues were created correctly then setup the serial port hardware. */
-    if( ( xComPortIF[ 0 ].xRXChars != 0 ) && ( xComPortIF[ 0 ].xTXChars != 0 ) )
-    {
-        xOldIPL = portSET_IPL( portIPL_MAX );
-
-        /* UART 0: Reset transmitter, receiver and mode register pointer */
-        MCF_UART_UCR0 = MCF_UART_UCR_MISC( 0x3 );
-        MCF_UART_UCR0 = MCF_UART_UCR_MISC( 0x2 );
-        MCF_UART_UCR0 = MCF_UART_UCR_MISC( 0x1 );
-
-        /* Enable receive interrupts. */
-        MCF_UART_UIMR0 = MCF_UART_UIMR_RXRDY_FU;
-
-        /* 8 Databits, 1 Stopbit and no parity */
-        MCF_UART_UMR0 = MCF_UART_UMR_PM( 0x3 ) | MCF_UART_UMR_SB( 0x7 ) | MCF_UART_UMR_BC( 0x3 );
-
-        /* UART 0 Clocking */
-        MCF_UART_UCSR0 = MCF_UART_UCSR_RCS( 0xd ) | MCF_UART_UCSR_TCS( 0xd );
-        MCF_UART_UBG10 = BAUDRATE_VALUE( FSYS_2, ulWantedBaud ) >> 8U;
-        MCF_UART_UBG20 = BAUDRATE_VALUE( FSYS_2, ulWantedBaud ) & 0xFFU;
-
-        /* UART 0: Enable interrupts */
-        __RAMVEC[MCF_UART_VECTOR] = prvSerialISR;
-        MCF_INTC0_ICR13 = MCF_INTC0_ICRn_IL( 0x2 ) | MCF_INTC0_ICRn_IP( 0x1 );
-        MCF_INTC0_IMRL &= ~MCF_INTC0_IMRL_INT_MASK13;
-
-        /* UART 0 Miscellaneous */
-        MCF_UART_UACR0 = 0;
-
-        /* UART 0: Enable pins */
-        MCF_GPIO_PAR_UART = MCF_GPIO_PAR_UART_PAR_U0RXD | MCF_GPIO_PAR_UART_PAR_U0TXD;
-
-        /* Enable the UART. */
-        MCF_UART_UCR0 = MCF_UART_UCR_RXC( 0x1 ) | MCF_UART_UCR_TXC( 0x1 );
-
-        xComPortIF[ 0 ].xInitialized = TRUE;
-        xReturn = ( xComPortHandle ) &xComPortIF[ 0 ];
-
-        ( void )portSET_IPL( xOldIPL );
-    }
-    else
-    {
-        xReturn = ( xComPortHandle ) 0;
-    }
-
-    return xReturn;
-}
-
-signed          portBASE_TYPE
-xSerialGetChar( xComPortHandle pxPort, signed portCHAR * pcRxedChar,
-                portTickType xBlockTime )
-{
-    int i;
-    portBASE_TYPE xResult = pdFALSE;
-    /* Lookup the correct interface. */
-    for( i = 0; i < COM_NIFACE; i++ )
-    {
-        if( pxPort == ( xComPortHandle ) &xComPortIF[ i ] )
-        {
-            break;
-        }
-    }
-    /* This COM port is available. */
-    if( ( i != COM_NIFACE ) && xComPortIF[ i ].xInitialized )
-    {
-        /* Get the next character from the buffer.  Return false if no characters
-         * are available, or arrive before xBlockTime expires.
-         */
-        if( xQueueReceive( xComPortIF[ i ].xRXChars, pcRxedChar, xBlockTime ) )
-        {
-            xResult = pdTRUE;
-        }
-    }
-    return xResult;
-}
-
-void
-vSerialPutString( xComPortHandle pxPort, const signed portCHAR *
-                  const pcString, unsigned portSHORT usStringLength )
-{
-    int i;
-    signed portCHAR *pChNext;
-
-    /* Send each character in the string, one at a time. */
-    pChNext = ( signed portCHAR * )pcString;
-    for( i = 0; i < usStringLength; i++ )
-    {
-        /* Block until character has been transmitted. */
-        while( xSerialPutChar( pxPort, *pChNext, COM_BLOCK_RETRYTIME ) != pdTRUE ); pChNext++;
-    }
-}
-
-signed          portBASE_TYPE
-xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar,
-                portTickType xBlockTime )
-{
-    int i;
-    portBASE_TYPE xResult = pdFALSE;
-    portBASE_TYPE xOldIPL;
-    /* Lookup the correct interface. */
-    for( i = 0; i < COM_NIFACE; i++ )
-    {
-        if( pxPort == ( xComPortHandle ) &xComPortIF[ i ] )
-        {
-            break;
-        }
-    }
-    /* This COM port is available. */
-    if( ( i != COM_NIFACE ) && xComPortIF[ i ].xInitialized )
-    {
-        /* Place the character in the queue of characters to be transmitted. */
-        if( xQueueSend( xComPortIF[ i ].xTXChars, &cOutChar, xBlockTime ) == pdPASS )
-        {
-            /* Turn on the Tx interrupt so the ISR will remove the character from the
-             * queue and send it. */
-            MCF_UART_UIMR0 = MCF_UART_UIMR_TXRDY | MCF_UART_UIMR_RXRDY_FU;
-            xResult = pdTRUE;
-        }
-    }
-    return xResult;
-}
-
-signed          portBASE_TYPE
-xSerialPutCharNOISR( xComPortHandle pxPort, signed portCHAR cOutChar )
-{
-    int i;
-    portBASE_TYPE xResult = pdFALSE;
-    portBASE_TYPE xOldIPL = portSET_IPL( portIPL_MAX );
-    /* Lookup the correct interface. */
-    for( i = 0; i < COM_NIFACE; i++ )
-    {
-        if( pxPort == ( xComPortHandle ) &xComPortIF[ i ] )
-        {
-            break;
-        }
-    }
-    /* This COM port is available. Support for this only available for COM1 right now. */
-    if( ( i != COM_NIFACE ) && ( i == 0 ) )
-    {
-        /* Wait until the transmit buffer is ready. */
-        while( !( MCF_UART_USR0 & MCF_UART_USR_TXRDY ) );
-        /* Place the character in the transmit buffer. */
-        MCF_UART_UTB0 = cOutChar;
-        xResult = pdTRUE;
-    }
-    ( void )portSET_IPL( xOldIPL );
-    return xResult;
-}
-
-void
-vSerialPutStringNOISR( xComPortHandle pxPort, const signed portCHAR *
-                       const pcString, unsigned portSHORT usStringLength )
-{
-    int i;
-    signed portCHAR *pChNext;
-    portBASE_TYPE xOldIPL = portSET_IPL( portIPL_MAX );
-
-    /* Send each character in the string, one at a time. */
-    pChNext = ( signed portCHAR * )pcString;
-    for( i = 0; i < usStringLength; i++ )
-    {
-        /* Block until character has been transmitted. */
-        while( xSerialPutCharNOISR( pxPort, *pChNext ) != pdTRUE );
-        pChNext++;
-    }
-    ( void )portSET_IPL( xOldIPL );
-}
-
-void
-vSerialClose( xComPortHandle xPort )
-{
-    /* Not supported as not required by the demo application. */
-}
-
-void
-prvSerialISR( void )
-{
-    static signed portCHAR cChar;
-    static portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByRx = pdFALSE;
-
-    /* We have to remvoe the effect of the GCC. Please note that the
-     * __attribute__ ((interrupt_handler)) does not work here because we
-     * have to do the storing of the registers ourself. Another problem
-     * is the usage of a frame pointer which is unlinked on entry.
-     */
-#if _GCC_USES_FP == 1
-    asm volatile ( "unlk %fp\n\t" );
-#endif
-    /* This ISR can cause a context switch, so the first statement must be
-     * a call to the portENTER_SWITCHING_ISR() macro. This must be BEFORE any
-     * variable declarations.
-     */
-    portENTER_SWITCHING_ISR();
-
-    /* Ready to send a character from the buffer. */
-    if( MCF_UART_USR0 & MCF_UART_USR_TXRDY )
-    {
-        /* Transmit buffer is ready. Test if there are characters available. */
-        if( xQueueReceiveFromISR( xComPortIF[ 0 ].xTXChars, &cChar, &xTaskWokenByTx ) ==
-            pdTRUE )
-        {
-            /* A character was retrieved from the queue so can be sent. */
-            MCF_UART_UTB0 = cChar;
-        }
-        else
-        {
-            /* Leave only receiver enabled. */
-            MCF_UART_UIMR0 = MCF_UART_UIMR_RXRDY_FU;
-        }
-    }
-    if( MCF_UART_USR0 & MCF_UART_USR_RXRDY )
-    {
-        cChar = MCF_UART_URB0;
-        xTaskWokenByRx =
-            xQueueSendFromISR( xComPortIF[ 0].xRXChars, &cChar, xTaskWokenByRx );
-    }
-    /* Exit the ISR.  If a task was woken by either a character being
-     * or transmitted then a context switch will occur.
-     */
-    portEXIT_SWITCHING_ISR( ( xTaskWokenByTx || xTaskWokenByRx ) );
-}
diff --git a/Demo/lwIP_MCF5235_GCC/system/vector.S b/Demo/lwIP_MCF5235_GCC/system/vector.S
deleted file mode 100644
index 4c278a64c..000000000
--- a/Demo/lwIP_MCF5235_GCC/system/vector.S
+++ /dev/null
@@ -1,302 +0,0 @@
-/*
-    FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter.
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-
-    FreeRTOS is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with FreeRTOS; if not, write to the Free Software
-    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-
-    A special exception to the GPL can be applied should you wish to distribute
-    a combined work that includes FreeRTOS, without being obliged to provide
-    the source code for any proprietary components.  See the licensing section
-    of http://www.FreeRTOS.org for full details of how and when the exception
-    can be applied.
-
-    ***************************************************************************
-    See http://www.FreeRTOS.org for documentation, latest information, license
-    and contact details.  Please ensure to read the configuration and relevant
-    port sections of the online documentation.
-    ***************************************************************************
-*/
-
-  .extern __stack
-  .extern start
-  .extern fec_handler
-  .extern fec_if
-  .extern decrement_timers
-  .global __RAMVEC
-  .global __ROMVEC
-
-  .equ    MCF_PIT_PCSR0, IPSBAR + 0x150000
-  .equ    MCF_PIT_PCSR_PIF, 0x0004
-
-  .section  .vector_rom, "x"
-__ROMVEC:
-  .long   __stack               /* Reset: Initial Stack Pointer */
-  .long   start                 /* Reset: Initial Program Counter */
-  .long   VecDefault            /* Bus Error */
-  .long   VecDefault            /* Address Error */
-  .long   VecDefault            /* Illegal Instruction */
-  .long   VecDefault            /* Zero Divison */
-  .space  4                     /* reserved */
-  .space  4                     /* reserved */
-  .long   VecDefault            /* Privilege Violation */
-  .long   VecDefault            /* Trace */
-  .long   VecDefault            /* Unimplemented line-a opcode */
-  .long   VecDefault            /* Unimplemented line-b opcode */
-  .long   VecDefault            /* Non-PC breakpoint debug interrupt */
-  .long   VecDefault            /* PC breakpoint debug interrupt */
-  .long   VecDefault            /* Format Error */
-  .long   VecDefault            /* Uninitialized Interrupt */
-  .org    0x60
-  .long   IRQSpurious           /* Spurious Interrupt */
-  .long   IRQDefault            /* Level 1 Interrupt */
-  .long   IRQDefault            /* Level 2 Interrupt */
-  .long   IRQDefault            /* Level 3 Interrupt */
-  .long   IRQDefault            /* Level 4 Interrupt */
-  .long   IRQDefault            /* Level 5 Interrupt */
-  .long   IRQDefault            /* Level 6 Interrupt */
-  .long   IRQDefault            /* Level 7 Interrupt */
-  .org    0x80
-  .long   TrapDefault           /* TRAP 0 */
-  .long   TrapDefault           /* TRAP 1 */
-  .long   TrapDefault           /* TRAP 2 */
-  .long   TrapDefault           /* TRAP 3 */
-  .long   TrapDefault           /* TRAP 4 */
-  .long   TrapDefault           /* TRAP 5 */
-  .long   TrapDefault           /* TRAP 6 */
-  .long   TrapDefault           /* TRAP 7 */
-  .long   TrapDefault           /* TRAP 8 */
-  .long   TrapDefault           /* TRAP 9 */
-  .long   TrapDefault           /* TRAP 10 */
-  .long   TrapDefault           /* TRAP 11 */
-  .long   TrapDefault           /* TRAP 12 */
-  .long   TrapDefault           /* TRAP 13 */
-  .long   TrapDefault           /* TRAP 14 */
-  .long   TrapDefault           /* TRAP 15 */
-  .org    0x100
-  .long   IRQDefault            /* User-Defined Interrupt 0 */
-  .long   IRQDefault            /* User-Defined Interrupt 1 */
-  .long   IRQDefault            /* User-Defined Interrupt 2 */
-  .long   IRQDefault            /* User-Defined Interrupt 3 */
-  .long   IRQDefault            /* User-Defined Interrupt 4 */
-  .long   IRQDefault            /* User-Defined Interrupt 5 */
-  .long   IRQDefault            /* User-Defined Interrupt 6 */
-  .long   IRQDefault            /* User-Defined Interrupt 7 */
-  .long   IRQDefault            /* User-Defined Interrupt 8 */
-  .long   IRQDefault            /* User-Defined Interrupt 9 */
-  .long   IRQDefault            /* User-Defined Interrupt 10 */
-  .long   IRQDefault            /* User-Defined Interrupt 11 */
-  .long   IRQDefault            /* User-Defined Interrupt 12 */
-  .long   IRQDefault            /* User-Defined Interrupt 13 */
-  .long   IRQDefault            /* User-Defined Interrupt 14 */
-  .long   IRQDefault            /* User-Defined Interrupt 15 */
-  .long   IRQDefault            /* User-Defined Interrupt 16 */
-  .long   IRQDefault            /* User-Defined Interrupt 17 */
-  .long   IRQDefault            /* User-Defined Interrupt 18 */
-  .long   IRQDefault            /* User-Defined Interrupt 19 */
-  .long   IRQDefault            /* User-Defined Interrupt 20 */
-  .long   IRQDefault            /* User-Defined Interrupt 21 */
-  .long   IRQDefault            /* User-Defined Interrupt 22 */
-  .long   IRQDefault            /* Transmit frame interrupt */
-  .long   IRQDefault            /* Transmit buffer interrupt */
-  .long   IRQDefault            /* Transmit FIFO underrun */
-  .long   IRQDefault            /* Collision retry limit */
-  .long   IRQDefault            /* Receive frame interrupt */
-  .long   IRQDefault            /* Receive buffer interrupt */
-  .long   IRQDefault            /* MII interrupt */
-  .long   IRQDefault            /* Late collision */
-  .long   IRQDefault            /* Heartbeat error */
-  .long   IRQDefault            /* Graceful stop complete */
-  .long   IRQDefault            /* Ethernet bus error */
-  .long   IRQDefault            /* Babbling transmit error */
-  .long   IRQDefault            /* Babbling receive error */
-  .long   IRQDefault            /* Timer interrupt */
-  .long   IRQDefault            /* User-Defined Interrupt 37 */
-  .long   IRQDefault            /* User-Defined Interrupt 38 */
-  .long   IRQDefault            /* User-Defined Interrupt 39 */
-  .long   IRQDefault            /* User-Defined Interrupt 40 */
-  .long   IRQDefault            /* User-Defined Interrupt 41 */
-  .long   IRQDefault            /* User-Defined Interrupt 42 */
-  .long   IRQDefault            /* User-Defined Interrupt 43 */
-  .long   IRQDefault            /* User-Defined Interrupt 44 */
-  .long   IRQDefault            /* User-Defined Interrupt 45 */
-  .long   IRQDefault            /* User-Defined Interrupt 46 */
-  .long   IRQDefault            /* User-Defined Interrupt 47 */
-  .long   IRQDefault            /* User-Defined Interrupt 48 */
-  .long   IRQDefault            /* User-Defined Interrupt 49 */
-  .long   IRQDefault            /* User-Defined Interrupt 50 */
-  .long   IRQDefault            /* User-Defined Interrupt 51 */
-  .long   IRQDefault            /* User-Defined Interrupt 52 */
-  .long   IRQDefault            /* User-Defined Interrupt 53 */
-  .long   IRQDefault            /* User-Defined Interrupt 54 */
-  .long   IRQDefault            /* User-Defined Interrupt 55 */
-  .long   IRQDefault            /* User-Defined Interrupt 56 */
-  .long   IRQDefault            /* User-Defined Interrupt 57 */
-  .long   IRQDefault            /* User-Defined Interrupt 58 */
-  .long   IRQDefault            /* User-Defined Interrupt 59 */
-  .long   IRQDefault            /* User-Defined Interrupt 60 */
-  .long   IRQDefault            /* User-Defined Interrupt 61 */
-  .long   IRQDefault            /* User-Defined Interrupt 62 */
-  .long   IRQDefault            /* User-Defined Interrupt 63 */
-  .long   IRQDefault            /* User-Defined Interrupt 64 */
-  .long   IRQDefault            /* User-Defined Interrupt 65 */
-  .long   IRQDefault            /* User-Defined Interrupt 66 */
-  .long   IRQDefault            /* User-Defined Interrupt 67 */
-  .long   IRQDefault            /* User-Defined Interrupt 68 */
-  .long   IRQDefault            /* User-Defined Interrupt 69 */
-  .long   IRQDefault            /* User-Defined Interrupt 70 */
-  .long   IRQDefault            /* User-Defined Interrupt 71 */
-  .long   IRQDefault            /* User-Defined Interrupt 72 */
-  .long   IRQDefault            /* User-Defined Interrupt 73 */
-  .long   IRQDefault            /* User-Defined Interrupt 74 */
-  .long   IRQDefault            /* User-Defined Interrupt 75 */
-  .long   IRQDefault            /* User-Defined Interrupt 76 */
-  .long   IRQDefault            /* User-Defined Interrupt 77 */
-  .long   IRQDefault            /* User-Defined Interrupt 78 */
-  .long   IRQDefault            /* User-Defined Interrupt 79 */
-  .long   IRQDefault            /* User-Defined Interrupt 80 */
-  .long   IRQDefault            /* User-Defined Interrupt 81 */
-  .long   IRQDefault            /* User-Defined Interrupt 82 */
-  .long   IRQDefault            /* User-Defined Interrupt 83 */
-  .long   IRQDefault            /* User-Defined Interrupt 84 */
-  .long   IRQDefault            /* User-Defined Interrupt 85 */
-  .long   IRQDefault            /* User-Defined Interrupt 86 */
-  .long   IRQDefault            /* User-Defined Interrupt 87 */
-  .long   IRQDefault            /* User-Defined Interrupt 88 */
-  .long   IRQDefault            /* User-Defined Interrupt 89 */
-  .long   IRQDefault            /* User-Defined Interrupt 90 */
-  .long   IRQDefault            /* User-Defined Interrupt 91 */
-  .long   IRQDefault            /* User-Defined Interrupt 92 */
-  .long   IRQDefault            /* User-Defined Interrupt 93 */
-  .long   IRQDefault            /* User-Defined Interrupt 94 */
-  .long   IRQDefault            /* User-Defined Interrupt 95 */
-  .long   IRQDefault            /* User-Defined Interrupt 96 */
-  .long   IRQDefault            /* User-Defined Interrupt 97 */
-  .long   IRQDefault            /* User-Defined Interrupt 98 */
-  .long   IRQDefault            /* User-Defined Interrupt 99 */
-  .long   IRQDefault            /* User-Defined Interrupt 100 */
-  .long   IRQDefault            /* User-Defined Interrupt 101 */
-  .long   IRQDefault            /* User-Defined Interrupt 102 */
-  .long   IRQDefault            /* User-Defined Interrupt 103 */
-  .long   IRQDefault            /* User-Defined Interrupt 104 */
-  .long   IRQDefault            /* User-Defined Interrupt 105 */
-  .long   IRQDefault            /* User-Defined Interrupt 106 */
-  .long   IRQDefault            /* User-Defined Interrupt 107 */
-  .long   IRQDefault            /* User-Defined Interrupt 108 */
-  .long   IRQDefault            /* User-Defined Interrupt 109 */
-  .long   IRQDefault            /* User-Defined Interrupt 110 */
-  .long   IRQDefault            /* User-Defined Interrupt 111 */
-  .long   IRQDefault            /* User-Defined Interrupt 112 */
-  .long   IRQDefault            /* User-Defined Interrupt 113 */
-  .long   IRQDefault            /* User-Defined Interrupt 114 */
-  .long   IRQDefault            /* User-Defined Interrupt 115 */
-  .long   IRQDefault            /* User-Defined Interrupt 116 */
-  .long   IRQDefault            /* User-Defined Interrupt 117 */
-  .long   IRQDefault            /* User-Defined Interrupt 118 */
-  .long   IRQDefault            /* User-Defined Interrupt 119 */
-  .long   IRQDefault            /* User-Defined Interrupt 120 */
-  .long   IRQDefault            /* User-Defined Interrupt 121 */
-  .long   IRQDefault            /* User-Defined Interrupt 122 */
-  .long   IRQDefault            /* User-Defined Interrupt 123 */
-  .long   IRQDefault            /* User-Defined Interrupt 124 */
-  .long   IRQDefault            /* User-Defined Interrupt 125 */
-  .long   IRQDefault            /* User-Defined Interrupt 126 */
-  .long   IRQDefault            /* User-Defined Interrupt 127 */
-  .long   IRQDefault            /* User-Defined Interrupt 128 */
-  .long   IRQDefault            /* User-Defined Interrupt 129 */
-  .long   IRQDefault            /* User-Defined Interrupt 130 */
-  .long   IRQDefault            /* User-Defined Interrupt 131 */
-  .long   IRQDefault            /* User-Defined Interrupt 132 */
-  .long   IRQDefault            /* User-Defined Interrupt 133 */
-  .long   IRQDefault            /* User-Defined Interrupt 134 */
-  .long   IRQDefault            /* User-Defined Interrupt 135 */
-  .long   IRQDefault            /* User-Defined Interrupt 136 */
-  .long   IRQDefault            /* User-Defined Interrupt 137 */
-  .long   IRQDefault            /* User-Defined Interrupt 138 */
-  .long   IRQDefault            /* User-Defined Interrupt 139 */
-  .long   IRQDefault            /* User-Defined Interrupt 140 */
-  .long   IRQDefault            /* User-Defined Interrupt 141 */
-  .long   IRQDefault            /* User-Defined Interrupt 142 */
-  .long   IRQDefault            /* User-Defined Interrupt 143 */
-  .long   IRQDefault            /* User-Defined Interrupt 144 */
-  .long   IRQDefault            /* User-Defined Interrupt 145 */
-  .long   IRQDefault            /* User-Defined Interrupt 146 */
-  .long   IRQDefault            /* User-Defined Interrupt 147 */
-  .long   IRQDefault            /* User-Defined Interrupt 148 */
-  .long   IRQDefault            /* User-Defined Interrupt 149 */
-  .long   IRQDefault            /* User-Defined Interrupt 150 */
-  .long   IRQDefault            /* User-Defined Interrupt 151 */
-  .long   IRQDefault            /* User-Defined Interrupt 152 */
-  .long   IRQDefault            /* User-Defined Interrupt 153 */
-  .long   IRQDefault            /* User-Defined Interrupt 154 */
-  .long   IRQDefault            /* User-Defined Interrupt 155 */
-  .long   IRQDefault            /* User-Defined Interrupt 156 */
-  .long   IRQDefault            /* User-Defined Interrupt 157 */
-  .long   IRQDefault            /* User-Defined Interrupt 158 */
-  .long   IRQDefault            /* User-Defined Interrupt 159 */
-  .long   IRQDefault            /* User-Defined Interrupt 160 */
-  .long   IRQDefault            /* User-Defined Interrupt 161 */
-  .long   IRQDefault            /* User-Defined Interrupt 162 */
-  .long   IRQDefault            /* User-Defined Interrupt 163 */
-  .long   IRQDefault            /* User-Defined Interrupt 164 */
-  .long   IRQDefault            /* User-Defined Interrupt 165 */
-  .long   IRQDefault            /* User-Defined Interrupt 166 */
-  .long   IRQDefault            /* User-Defined Interrupt 167 */
-  .long   IRQDefault            /* User-Defined Interrupt 168 */
-  .long   IRQDefault            /* User-Defined Interrupt 169 */
-  .long   IRQDefault            /* User-Defined Interrupt 170 */
-  .long   IRQDefault            /* User-Defined Interrupt 171 */
-  .long   IRQDefault            /* User-Defined Interrupt 172 */
-  .long   IRQDefault            /* User-Defined Interrupt 173 */
-  .long   IRQDefault            /* User-Defined Interrupt 174 */
-  .long   IRQDefault            /* User-Defined Interrupt 175 */
-  .long   IRQDefault            /* User-Defined Interrupt 176 */
-  .long   IRQDefault            /* User-Defined Interrupt 177 */
-  .long   IRQDefault            /* User-Defined Interrupt 178 */
-  .long   IRQDefault            /* User-Defined Interrupt 179 */
-  .long   IRQDefault            /* User-Defined Interrupt 180 */
-  .long   IRQDefault            /* User-Defined Interrupt 181 */
-  .long   IRQDefault            /* User-Defined Interrupt 182 */
-  .long   IRQDefault            /* User-Defined Interrupt 183 */
-  .long   IRQDefault            /* User-Defined Interrupt 184 */
-  .long   IRQDefault            /* User-Defined Interrupt 185 */
-  .long   IRQDefault            /* User-Defined Interrupt 186 */
-  .long   IRQDefault            /* User-Defined Interrupt 187 */
-  .long   IRQDefault            /* User-Defined Interrupt 188 */
-  .long   IRQDefault            /* User-Defined Interrupt 189 */
-  .long   IRQDefault            /* User-Defined Interrupt 190 */
-  .long   IRQDefault            /* User-Defined Interrupt 191 */
-  .org    0x00000400
-
-  .section  .vector_ram
-__RAMVEC:
-  .space  0x400
-
-  .section  .text
-VecDefault:
-  halt
-  bra VecDefault
-
-IRQDefault:
-  halt
-  bra IRQDefault
-
-IRQSpurious:
-  halt
-  bra IRQSpurious
-
-TrapDefault:
-  halt
-  bra TrapDefault
diff --git a/Demo/lwIP_MCF5235_GCC/tools/indent.sh b/Demo/lwIP_MCF5235_GCC/tools/indent.sh
deleted file mode 100644
index 140fd04d7..000000000
--- a/Demo/lwIP_MCF5235_GCC/tools/indent.sh
+++ /dev/null
@@ -1,25 +0,0 @@
-#!/bin/sh
-
-indent \
-    --declaration-indentation16 \
-    --procnames-start-lines \
-    --blank-lines-after-declarations \
-    --blank-lines-after-procedures \
-    --break-before-boolean-operator \
-    --braces-after-if-line \
-    --braces-after-struct-decl-line \
-    --brace-indent0 \
-    --case-indentation0 \
-    --no-space-after-function-call-names \
-    --no-space-after-for \
-    --no-space-after-if \
-    --no-space-after-while \
-    --no-space-after-casts \
-    --space-after-parentheses \
-    --dont-format-comments \
-    --indent-level4 \
-    --honour-newlines \
-    --no-tabs \
-    --line-length100 \
-    $@
-    
diff --git a/Demo/lwIP_MCF5235_GCC/tools/mcf5235-http.png b/Demo/lwIP_MCF5235_GCC/tools/mcf5235-http.png
deleted file mode 100644
index fd5c1d5a2..000000000
Binary files a/Demo/lwIP_MCF5235_GCC/tools/mcf5235-http.png and /dev/null differ
diff --git a/Demo/lwIP_MCF5235_GCC/tools/mcf5235-icmp-frame-len1024.png b/Demo/lwIP_MCF5235_GCC/tools/mcf5235-icmp-frame-len1024.png
deleted file mode 100644
index eb3362be4..000000000
Binary files a/Demo/lwIP_MCF5235_GCC/tools/mcf5235-icmp-frame-len1024.png and /dev/null differ
diff --git a/Demo/lwIP_MCF5235_GCC/tools/mcf5235-icmp-frame-len64.png b/Demo/lwIP_MCF5235_GCC/tools/mcf5235-icmp-frame-len64.png
deleted file mode 100644
index 65347b156..000000000
Binary files a/Demo/lwIP_MCF5235_GCC/tools/mcf5235-icmp-frame-len64.png and /dev/null differ
diff --git a/Demo/lwIP_MCF5235_GCC/web.c b/Demo/lwIP_MCF5235_GCC/web.c
deleted file mode 100644
index beac59b36..000000000
--- a/Demo/lwIP_MCF5235_GCC/web.c
+++ /dev/null
@@ -1,218 +0,0 @@
-/*
-    FreeRTOS V4.1.0 - copyright (C) 2003-2006 Richard Barry.
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-
-    FreeRTOS is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with FreeRTOS; if not, write to the Free Software
-    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-
-    A special exception to the GPL can be applied should you wish to distribute
-    a combined work that includes FreeRTOS, without being obliged to provide
-    the source code for any proprietary components.  See the licensing section
-    of http://www.FreeRTOS.org for full details of how and when the exception
-    can be applied.
-
-    ***************************************************************************
-    See http://www.FreeRTOS.org for documentation, latest information, license
-    and contact details.  Please ensure to read the configuration and relevant
-    port sections of the online documentation.
-    ***************************************************************************
-*/
-
-/*
-    Implements a simplistic WEB server.  Every time a connection is made and
-    data is received a dynamic page that shows the current TCP/IP statistics
-    is generated and returned.  The connection is then closed.
-
-    This file was adapted from a FreeRTOS lwIP slip demo supplied by a third
-    party.
-*/
-
-/* ------------------------ System includes ------------------------------- */
-#include 
-#include 
-
-/* ------------------------ FreeRTOS includes ----------------------------- */
-#include "FreeRTOS.h"
-#include "task.h"
-#include "semphr.h"
-
-/* ------------------------ lwIP includes --------------------------------- */
-#include "lwip/api.h"
-#include "lwip/tcpip.h"
-#include "lwip/memp.h"
-#include "lwip/stats.h"
-#include "netif/loopif.h"
-
-/* ------------------------ Project includes ------------------------------ */
-#include "mcf5xxx.h"
-#include "mcf523x.h"
-#include "netif/fec.h"
-
-#include "web.h"
-
-/* ------------------------ Defines --------------------------------------- */
-/* The size of the buffer in which the dynamic WEB page is created. */
-#define webMAX_PAGE_SIZE        ( 2048 )
-
-/* Standard GET response. */
-#define webHTTP_OK  "HTTP/1.0 200 OK\r\nContent-type: text/html\r\n\r\n"
-
-/* The port on which we listen. */
-#define webHTTP_PORT            ( 80 )
-
-/* Delay on close error. */
-#define webSHORT_DELAY          ( 10 )
-
-/* Format of the dynamic page that is returned on each connection. */
-#define webHTML_START \
-"\
-\
-\
-\
-\r\nPage Hits = "
-
-#define webHTML_END \
-"\r\n" \
-"FreeRTOS MCF5235 port (c) 2006 by Christian Walter <wolti@sil.at>\r\n" \
-"
\r\n" \ -"\r\n" \ -"" - -/* ------------------------ Prototypes ------------------------------------ */ -static void vProcessConnection( struct netconn *pxNetCon ); - -/*------------------------------------------------------------*/ - -/* - * Process an incoming connection on port 80. - * - * This simply checks to see if the incoming data contains a GET request, and - * if so sends back a single dynamically created page. The connection is then - * closed. A more complete implementation could create a task for each - * connection. - */ -static void -vProcessConnection( struct netconn *pxNetCon ) -{ - static portCHAR cDynamicPage[webMAX_PAGE_SIZE], cPageHits[11]; - struct netbuf *pxRxBuffer; - portCHAR *pcRxString; - unsigned portSHORT usLength; - static unsigned portLONG ulPageHits = 0; - - /* We expect to immediately get data. */ - pxRxBuffer = netconn_recv( pxNetCon ); - - if( pxRxBuffer != NULL ) - { - /* Where is the data? */ - netbuf_data( pxRxBuffer, ( void * )&pcRxString, &usLength ); - - /* Is this a GET? We don't handle anything else. */ - if( !strncmp( pcRxString, "GET", 3 ) ) - { - pcRxString = cDynamicPage; - - /* Update the hit count. */ - ulPageHits++; - sprintf( cPageHits, "%lu", ulPageHits ); - - /* Write out the HTTP OK header. */ - netconn_write( pxNetCon, webHTTP_OK, ( u16_t ) strlen( webHTTP_OK ), NETCONN_COPY ); - - /* Generate the dynamic page... - - ... First the page header. */ - strcpy( cDynamicPage, webHTML_START ); - /* ... Then the hit count... */ - strcat( cDynamicPage, cPageHits ); - strcat( cDynamicPage, - "

Task          State  Priority  Stack #
************************************************
" );
-            /* ... Then the list of tasks and their status... */
-            vTaskList( ( signed portCHAR * )cDynamicPage + strlen( cDynamicPage ) );
-            /* ... Finally the page footer. */
-            strcat( cDynamicPage, webHTML_END );
-
-            /* Write out the dynamically generated page. */
-            netconn_write( pxNetCon, cDynamicPage, ( u16_t ) strlen( cDynamicPage ), NETCONN_COPY );
-        }
-
-        netbuf_delete( pxRxBuffer );
-    }
-
-    netconn_close( pxNetCon );
-}
-
-/*------------------------------------------------------------*/
-
-void
-vlwIPInit( void )
-{
-    /* Initialize lwIP and its interface layer. */
-    sys_init(  );
-    mem_init(  );
-    memp_init(  );
-    pbuf_init(  );
-    netif_init(  );
-    ip_init(  );
-    tcpip_init( NULL, NULL );
-}
-
-/*------------------------------------------------------------*/
-
-void
-vBasicWEBServer( void *pvParameters )
-{
-    struct netconn *pxHTTPListener, *pxNewConnection;
-    struct ip_addr  xIpAddr, xNetMast, xGateway;
-    static struct netif fec523x_if;
-
-    /* Parameters are not used - suppress compiler error. */
-    ( void )pvParameters;
-
-    /* Create and configure the EMAC interface. */
-    IP4_ADDR( &xIpAddr, 10, 0, 10, 2 );
-    IP4_ADDR( &xNetMast, 255, 255, 255, 0 );
-    IP4_ADDR( &xGateway, 10, 0, 10, 1 );
-    netif_add( &fec523x_if, &xIpAddr, &xNetMast, &xGateway, NULL, mcf523xfec_init, tcpip_input );
-
-    /* make it the default interface */
-    netif_set_default( &fec523x_if );
-
-    /* bring it up */
-    netif_set_up( &fec523x_if );
-
-    /* Create a new tcp connection handle */
-    pxHTTPListener = netconn_new( NETCONN_TCP );
-    netconn_bind( pxHTTPListener, NULL, webHTTP_PORT );
-    netconn_listen( pxHTTPListener );
-
-    /* Loop forever */
-    for( ;; )
-    {
-        /* Wait for connection. */
-        pxNewConnection = netconn_accept( pxHTTPListener );
-
-        if( pxNewConnection != NULL )
-        {
-            /* Service connection. */
-            vProcessConnection( pxNewConnection );
-            while( netconn_delete( pxNewConnection ) != ERR_OK )
-            {
-                vTaskDelay( webSHORT_DELAY );
-            }
-        }
-    }
-}
diff --git a/Demo/lwIP_MCF5235_GCC/web.h b/Demo/lwIP_MCF5235_GCC/web.h
deleted file mode 100644
index f903d74fa..000000000
--- a/Demo/lwIP_MCF5235_GCC/web.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
-    FreeRTOS V4.1.0 - copyright (C) 2003-2006 Richard Barry.
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-
-    FreeRTOS is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with FreeRTOS; if not, write to the Free Software
-    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-
-    A special exception to the GPL can be applied should you wish to distribute
-    a combined work that includes FreeRTOS, without being obliged to provide
-    the source code for any proprietary components.  See the licensing section
-    of http://www.FreeRTOS.org for full details of how and when the exception
-    can be applied.
-
-    ***************************************************************************
-    See http://www.FreeRTOS.org for documentation, latest information, license
-    and contact details.  Please ensure to read the configuration and relevant
-    port sections of the online documentation.
-    ***************************************************************************
-*/
-
-#ifndef BASIC_WEB_SERVER_H
-#define BASIC_WEB_SERVER_H
-
-/* The function that implements the WEB server task. */
-void            vBasicWEBServer( void *pvParameters );
-
- 
-/* Initialisation required by lwIP. */
-void            vlwIPInit( void );
-
- 
-#endif  /* 
 */
-
diff --git a/Demo/msp430_CrossWorks/FreeRTOSConfig.h b/Demo/msp430_CrossWorks/FreeRTOSConfig.h
deleted file mode 100644
index 0e05a5c14..000000000
--- a/Demo/msp430_CrossWorks/FreeRTOSConfig.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
-	FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
-
-	This file is part of the FreeRTOS.org distribution.
-
-	FreeRTOS.org is free software; you can redistribute it and/or modify
-	it under the terms of the GNU General Public License as published by
-	the Free Software Foundation; either version 2 of the License, or
-	(at your option) any later version.
-
-	FreeRTOS.org is distributed in the hope that it will be useful,
-	but WITHOUT ANY WARRANTY; without even the implied warranty of
-	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-	GNU General Public License for more details.
-
-	You should have received a copy of the GNU General Public License
-	along with FreeRTOS.org; if not, write to the Free Software
-	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-
-	A special exception to the GPL can be applied should you wish to distribute
-	a combined work that includes FreeRTOS.org, without being obliged to provide
-	the source code for any proprietary components.  See the licensing section 
-	of http://www.FreeRTOS.org for full details of how and when the exception
-	can be applied.
-
-	***************************************************************************
-	See http://www.FreeRTOS.org for documentation, latest information, license 
-	and contact details.  Please ensure to read the configuration and relevant 
-	port sections of the online documentation.
-	***************************************************************************
-*/
-
-#ifndef FREERTOS_CONFIG_H
-#define FREERTOS_CONFIG_H
-
-#include 
-
-/*-----------------------------------------------------------
- * Application specific definitions.
- *
- * These definitions should be adjusted for your particular hardware and
- * application requirements.
- *
- * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
- * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. 
- *----------------------------------------------------------*/
-
-#define configUSE_PREEMPTION		1
-#define configUSE_IDLE_HOOK			1
-#define configUSE_TICK_HOOK			0
-#define configCPU_CLOCK_HZ			( ( unsigned portLONG ) 7995392 ) /* Clock setup from main.c in the demo application. */
-#define configTICK_RATE_HZ			( ( portTickType ) 1000 )
-#define configMAX_PRIORITIES		( ( unsigned portBASE_TYPE ) 4 )
-#define configMINIMAL_STACK_SIZE	( ( unsigned portSHORT ) 50 )
-#define configTOTAL_HEAP_SIZE		( ( size_t ) ( 1800 ) )
-#define configMAX_TASK_NAME_LEN		( 8 )
-#define configUSE_TRACE_FACILITY	0
-#define configUSE_16_BIT_TICKS		1
-#define configIDLE_SHOULD_YIELD		1
-
-/* Co-routine definitions. */
-#define configUSE_CO_ROUTINES 		0
-#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
-
-/* Set the following definitions to 1 to include the API function, or zero
-to exclude the API function. */
-
-#define INCLUDE_vTaskPrioritySet		0
-#define INCLUDE_uxTaskPriorityGet		0
-#define INCLUDE_vTaskDelete				1
-#define INCLUDE_vTaskCleanUpResources	0
-#define INCLUDE_vTaskSuspend			0
-#define INCLUDE_vTaskDelayUntil			1
-#define INCLUDE_vTaskDelay				1
-
-
-#endif /* FREERTOS_CONFIG_H */
diff --git a/Demo/msp430_CrossWorks/ParTest/ParTest.c b/Demo/msp430_CrossWorks/ParTest/ParTest.c
deleted file mode 100644
index 4ea6ff63f..000000000
--- a/Demo/msp430_CrossWorks/ParTest/ParTest.c
+++ /dev/null
@@ -1,210 +0,0 @@
-/*
-	FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
-
-	This file is part of the FreeRTOS.org distribution.
-
-	FreeRTOS.org is free software; you can redistribute it and/or modify
-	it under the terms of the GNU General Public License as published by
-	the Free Software Foundation; either version 2 of the License, or
-	(at your option) any later version.
-
-	FreeRTOS.org is distributed in the hope that it will be useful,
-	but WITHOUT ANY WARRANTY; without even the implied warranty of
-	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-	GNU General Public License for more details.
-
-	You should have received a copy of the GNU General Public License
-	along with FreeRTOS.org; if not, write to the Free Software
-	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-
-	A special exception to the GPL can be applied should you wish to distribute
-	a combined work that includes FreeRTOS.org, without being obliged to provide
-	the source code for any proprietary components.  See the licensing section 
-	of http://www.FreeRTOS.org for full details of how and when the exception
-	can be applied.
-
-	***************************************************************************
-	See http://www.FreeRTOS.org for documentation, latest information, license 
-	and contact details.  Please ensure to read the configuration and relevant 
-	port sections of the online documentation.
-	***************************************************************************
-*/
-
-/*-----------------------------------------------------------
- * Characters on the LCD are used to simulate LED's.  In this case the 'ParTest'
- * is really operating on the LCD display.
- *-----------------------------------------------------------*/
-
-/*
- * This demo is configured to execute on the ES449 prototyping board from
- * SoftBaugh. The ES449 has a built in LCD display and a single built in user
- * LED.  Therefore, in place of flashing an LED, the 'flash' and 'check' tasks
- * toggle '*' characters on the LCD.  The left most '*' represents LED 0, the
- * next LED 1, etc.
- *
- * There is a single genuine on board LED referenced as LED 10.
- */
-
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Demo application includes. */
-#include "partest.h"
-
-/* Constants required to setup the LCD. */
-#define LCD_DIV_64 5
-
-/* Constants required to access the "LED's".  The LED segments are turned on
-and off to generate '*' characters. */
-#define partstNUM_LEDS			( ( unsigned portCHAR ) 6 )
-#define partstSEGMENTS_ON		( ( unsigned portCHAR ) 0x0f )
-#define partstSEGMENTS_OFF		( ( unsigned portCHAR ) 0x00 )
-
-/* The LED number of the real on board LED, rather than a simulated LED. */
-#define partstON_BOARD_LED		( ( unsigned portBASE_TYPE ) 10 )
-#define mainON_BOARD_LED_BIT	( ( unsigned portCHAR ) 0x01 )
-
-/* The LCD segments used to generate the '*' characters for LED's 0 to 5. */
-unsigned portCHAR * const ucRHSSegments[ partstNUM_LEDS ] = {	( unsigned portCHAR * )0xa4, 
-																( unsigned portCHAR * )0xa2, 
-																( unsigned portCHAR * )0xa0, 
-																( unsigned portCHAR * )0x9e,
-																( unsigned portCHAR * )0x9c,
-																( unsigned portCHAR * )0x9a };
-
-unsigned portCHAR * const ucLHSSegments[ partstNUM_LEDS ] = {	( unsigned portCHAR * )0xa3, 
-																( unsigned portCHAR * )0xa1, 
-																( unsigned portCHAR * )0x9f, 
-																( unsigned portCHAR * )0x9d,
-																( unsigned portCHAR * )0x9b,
-																( unsigned portCHAR * )0x99 };
-
-/*
- * Toggle the single genuine built in LED.
- */
-static void prvToggleOnBoardLED( void );
-
-/*-----------------------------------------------------------*/
-
-void vParTestInitialise( void )
-{
-	/* Initialise the LCD hardware. */
-
-	/* Used for the onboard LED. */
-	P1DIR = 0x01;
-
-	// Setup Basic Timer for LCD operation
-	BTCTL = (LCD_DIV_64+0x23);
-
-	// Setup port functions
-	P1SEL = 0x32;
-	P2SEL = 0x00;
-	P3SEL = 0x00;
-	P4SEL = 0xFC;
-	P5SEL = 0xFF;
-	
-	/* Initialise all segments to off. */
-	LCDM1 = partstSEGMENTS_OFF;	
-	LCDM2 = partstSEGMENTS_OFF;	
-	LCDM3 = partstSEGMENTS_OFF;	
-	LCDM4 = partstSEGMENTS_OFF;	
-	LCDM5 = partstSEGMENTS_OFF;	
-	LCDM6 = partstSEGMENTS_OFF;	
-	LCDM7 = partstSEGMENTS_OFF;	
-	LCDM8 = partstSEGMENTS_OFF;	
-	LCDM9 = partstSEGMENTS_OFF;	
-	LCDM10 = partstSEGMENTS_OFF;	
-	LCDM11 = partstSEGMENTS_OFF;	
-	LCDM12 = partstSEGMENTS_OFF;	
-	LCDM13 = partstSEGMENTS_OFF;	
-	LCDM14 = partstSEGMENTS_OFF;	
-	LCDM15 = partstSEGMENTS_OFF;	
-	LCDM16 = partstSEGMENTS_OFF;	
-	LCDM17 = partstSEGMENTS_OFF;	
-	LCDM18 = partstSEGMENTS_OFF;	
-	LCDM19 = partstSEGMENTS_OFF;	
-	LCDM20 = partstSEGMENTS_OFF;	
-
-	/* Setup LCD control. */
-	LCDCTL = (LCDSG0_7|LCD4MUX|LCDON);
-}
-/*-----------------------------------------------------------*/
-
-void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
-{
-	/* Set or clear the output [in this case show or hide the '*' character. */
-	if( uxLED < ( portBASE_TYPE ) partstNUM_LEDS )
-	{
-		vTaskSuspendAll();
-		{
-			if( xValue )
-			{
-				/* Turn on the segments required to show the '*'. */
-				*( ucRHSSegments[ uxLED ] ) = partstSEGMENTS_ON;
-				*( ucLHSSegments[ uxLED ] ) = partstSEGMENTS_ON;
-			}
-			else
-			{
-				/* Turn off all the segments. */
-				*( ucRHSSegments[ uxLED ] ) = partstSEGMENTS_OFF;
-				*( ucLHSSegments[ uxLED ] ) = partstSEGMENTS_OFF;
-			}
-		}
-		xTaskResumeAll();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
-{
-	if( uxLED < ( portBASE_TYPE ) partstNUM_LEDS )
-	{
-		vTaskSuspendAll();
-		{
-			/* If the '*' is already showing - hide it.  If it is not already
-			showing then show it. */
-			if( *( ucRHSSegments[ uxLED ] ) )
-			{
-				*( ucRHSSegments[ uxLED ] ) = partstSEGMENTS_OFF;
-				*( ucLHSSegments[ uxLED ] ) = partstSEGMENTS_OFF;
-			}
-			else
-			{
-				*( ucRHSSegments[ uxLED ] ) = partstSEGMENTS_ON;
-				*( ucLHSSegments[ uxLED ] ) = partstSEGMENTS_ON;
-			}
-		}
-		xTaskResumeAll();
-	}
-	else
-	{
-		if( uxLED == partstON_BOARD_LED )
-		{
-			/* The request related to the genuine on board LED. */
-			prvToggleOnBoardLED();
-		}
-	}	
-}
-/*-----------------------------------------------------------*/
-
-static void prvToggleOnBoardLED( void )
-{
-static unsigned portSHORT sState = pdFALSE;
-
-	/* Toggle the state of the single genuine on board LED. */
-	if( sState )	
-	{
-		P1OUT |= mainON_BOARD_LED_BIT;
-	}
-	else
-	{
-		P1OUT &= ~mainON_BOARD_LED_BIT;
-	}
-
-	sState = !sState;
-}
-/*-----------------------------------------------------------*/
-
-
diff --git a/Demo/msp430_CrossWorks/RTOSDemo.hzp b/Demo/msp430_CrossWorks/RTOSDemo.hzp
deleted file mode 100644
index 94acc5011..000000000
--- a/Demo/msp430_CrossWorks/RTOSDemo.hzp
+++ /dev/null
@@ -1,34 +0,0 @@
-
-
-  
-    
-    
-      
-      
-        
-      
-      
-      
-      
-      
-      
-    
-    
-      
-      
-      
-    
-    
-      
-      
-      
-      
-      
-      
-      
-    
-  
-  
-  
-  
-
diff --git a/Demo/msp430_CrossWorks/RTOSDemo.hzs b/Demo/msp430_CrossWorks/RTOSDemo.hzs
deleted file mode 100644
index c4dc21923..000000000
--- a/Demo/msp430_CrossWorks/RTOSDemo.hzs
+++ /dev/null
@@ -1,57 +0,0 @@
-
-
- 
- 
- 
-  
- 
- 
-  
- 
- 
-  
- 
- 
-  
- 
- 
-  
-  
-  
-  
-  
- 
- 
-  
- 
- 
-  
- 
- 
-  
- 
- 
-  
- 
- 
- 
-  
- 
- 
-  
- 
- 
-  
- 
- 
-  
- 
- 
-  
- 
- 
-  
-  
- 
- 
-
diff --git a/Demo/msp430_CrossWorks/main.c b/Demo/msp430_CrossWorks/main.c
deleted file mode 100644
index 41c7611f1..000000000
--- a/Demo/msp430_CrossWorks/main.c
+++ /dev/null
@@ -1,293 +0,0 @@
-/*
-	FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
-
-	This file is part of the FreeRTOS.org distribution.
-
-	FreeRTOS.org is free software; you can redistribute it and/or modify
-	it under the terms of the GNU General Public License as published by
-	the Free Software Foundation; either version 2 of the License, or
-	(at your option) any later version.
-
-	FreeRTOS.org is distributed in the hope that it will be useful,
-	but WITHOUT ANY WARRANTY; without even the implied warranty of
-	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-	GNU General Public License for more details.
-
-	You should have received a copy of the GNU General Public License
-	along with FreeRTOS.org; if not, write to the Free Software
-	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-
-	A special exception to the GPL can be applied should you wish to distribute
-	a combined work that includes FreeRTOS.org, without being obliged to provide
-	the source code for any proprietary components.  See the licensing section 
-	of http://www.FreeRTOS.org for full details of how and when the exception
-	can be applied.
-
-	***************************************************************************
-	See http://www.FreeRTOS.org for documentation, latest information, license 
-	and contact details.  Please ensure to read the configuration and relevant 
-	port sections of the online documentation.
-	***************************************************************************
-*/
-
-/*
- * Creates all the demo application tasks, then starts the scheduler.  The WEB
- * documentation provides more details of the demo application tasks.
- * 
- * This demo is configured to execute on the ES449 prototyping board from
- * SoftBaugh. The ES449 has a built in LCD display and a single built in user
- * LED.  Therefore, in place of flashing an LED, the 'flash' and 'check' tasks
- * toggle '*' characters on the LCD.  The left most '*' represents LED 0, the
- * next LED 1, etc.
- *
- * Main. c also creates a task called 'Check'.  This only executes every three 
- * seconds but has the highest priority so is guaranteed to get processor time.  
- * Its main function is to check that all the other tasks are still operational.  
- * Each task that does not flash an LED maintains a unique count that is 
- * incremented each time the task successfully completes its function.  Should 
- * any error occur within such a task the count is permanently halted.  The 
- * 'check' task inspects the count of each task to ensure it has changed since
- * the last time the check task executed.  If all the count variables have 
- * changed all the tasks are still executing error free, and the check task
- * toggles an LED with a three second period.  Should any task contain an error 
- * at any time the LED toggle rate will increase to 500ms.
- *
- * Please read the documentation for the MSP430 port available on
- * http://www.FreeRTOS.org.
- */
-
-/* Standard includes. */
-#include 
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Demo application includes. */
-#include "partest.h"
-#include "flash.h"
-#include "integer.h"
-#include "comtest2.h"
-#include "PollQ.h"
-
-/* Constants required for hardware setup. */
-#define mainALL_BITS_OUTPUT		( ( unsigned portCHAR ) 0xff )
-#define mainMAX_FREQUENCY		( ( unsigned portCHAR ) 121 )
-
-/* Constants that define the LED's used by the various tasks. [in this case
-the '*' characters on the LCD represent LED's] */
-#define mainCHECK_LED			( 4 )
-#define mainCOM_TEST_LED		( 10 )
-
-/* Demo task priorities. */
-#define mainCHECK_TASK_PRIORITY			( tskIDLE_PRIORITY + 3 )
-#define mainCOM_TEST_PRIORITY			( tskIDLE_PRIORITY + 2 )
-#define mainQUEUE_POLL_PRIORITY			( tskIDLE_PRIORITY + 2 )
-#define mainLED_TASK_PRIORITY			( tskIDLE_PRIORITY + 1 )
-
-/* Baud rate used by the COM test tasks. */
-#define mainCOM_TEST_BAUD_RATE			( ( unsigned portLONG ) 19200 )
-
-/* The frequency at which the 'Check' tasks executes.  See the comments at the 
-top of the page.  When the system is operating error free the 'Check' task
-toggles an LED every three seconds.  If an error is discovered in any task the
-rate is increased to 500 milliseconds.  [in this case the '*' characters on the 
-LCD represent LED's]*/
-#define mainNO_ERROR_CHECK_DELAY		( ( portTickType ) 3000 / portTICK_RATE_MS  )
-#define mainERROR_CHECK_DELAY			( ( portTickType ) 500 / portTICK_RATE_MS  )
-
-/* The constants used in the calculation. */
-#define intgCONST1				( ( portLONG ) 123 )
-#define intgCONST2				( ( portLONG ) 234567 )
-#define intgCONST3				( ( portLONG ) -3 )
-#define intgCONST4				( ( portLONG ) 7 )
-#define intgEXPECTED_ANSWER		( ( ( intgCONST1 + intgCONST2 ) * intgCONST3 ) / intgCONST4 )
-
-/* 
- * The function that implements the Check task.  See the comments at the head
- * of the page for implementation details.
- */ 
-static void vErrorChecks( void *pvParameters );
-
-/*
- * Called by the Check task.  Returns pdPASS if all the other tasks are found
- * to be operating without error - otherwise returns pdFAIL.
- */
-static portSHORT prvCheckOtherTasksAreStillRunning( void );
-
-/* 
- * Perform the hardware setup required by the ES449 in order to run the demo
- * application.
- */
-static void prvSetupHardware( void );
-
-
-portBASE_TYPE xLocalError = pdFALSE;
-
-/*-----------------------------------------------------------*/
-
-/*
- * Start the demo application tasks - then start the real time scheduler.
- */
-int main( void )
-{
-	/* Setup the hardware ready for the demo. */
-	prvSetupHardware();
-	vParTestInitialise();
-
-	/* Start the standard demo application tasks. */
-	vStartLEDFlashTasks( mainLED_TASK_PRIORITY );
-	vStartIntegerMathTasks( tskIDLE_PRIORITY );
-	vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED - 1 );
-	vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
-
-	/* Start the 'Check' task which is defined in this file. */
-	xTaskCreate( vErrorChecks, ( const signed portCHAR * const ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );	
-
-	/* Start the scheduler. */
-	vTaskStartScheduler();
-
-	/* As the scheduler has been started the demo applications tasks will be
-	executing and we should never get here! */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-static portTASK_FUNCTION( vErrorChecks, pvParameters )
-{
-portTickType xDelayPeriod = mainNO_ERROR_CHECK_DELAY;
-
-	/* Cycle for ever, delaying then checking all the other tasks are still
-	operating without error. */
-	for( ;; )
-	{
-		/* Wait until it is time to check again.  The time we wait here depends
-		on whether an error has been detected or not.  When an error is 
-		detected the time is shortened resulting in a faster LED flash rate. */
-		vTaskDelay( xDelayPeriod );
-
-		/* See if the other tasks are all ok. */
-		if( prvCheckOtherTasksAreStillRunning() != pdPASS )
-		{
-			/* An error occurred in one of the tasks so shorten the delay 
-			period - which has the effect of increasing the frequency of the
-			LED toggle. */
-			xDelayPeriod = mainERROR_CHECK_DELAY;
-		}
-
-		/* Flash! */
-		vParTestToggleLED( mainCHECK_LED );
-	}
-}
-/*-----------------------------------------------------------*/
-
-static portSHORT prvCheckOtherTasksAreStillRunning( void )
-{
-static portSHORT sNoErrorFound = pdTRUE;
-
-	/* The demo tasks maintain a count that increments every cycle of the task
-	provided that the task has never encountered an error.  This function 
-	checks the counts maintained by the tasks to ensure they are still being
-	incremented.  A count remaining at the same value between calls therefore
-	indicates that an error has been detected.  Only tasks that do not flash
-	an LED are checked. */
-
-	if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
-	{
-		sNoErrorFound = pdFALSE;
-	}
-
-	if( xAreComTestTasksStillRunning() != pdTRUE )
-	{
-		sNoErrorFound = pdFALSE;
-	}
-
-	if( xArePollingQueuesStillRunning() != pdTRUE )
-	{
-		sNoErrorFound = pdFALSE;
-	}
-
-	if( xLocalError == pdTRUE )
-	{
-		sNoErrorFound = pdFALSE;
-	}
-	
-	return sNoErrorFound;
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetupHardware( void )
-{
-	/* Stop the watchdog. */
-	WDTCTL = WDTPW + WDTHOLD;
-
-	/* Setup DCO+ for ( xtal * D * (N + 1) ) operation. */
-	FLL_CTL0 |= DCOPLUS + XCAP18PF; 
-
-	/* X2 DCO frequency, 8MHz nominal DCO */
-	SCFI0 |= FN_4;                  
-
-	/* (121+1) x 32768 x 2 = 7.99 Mhz */
-	SCFQCTL = mainMAX_FREQUENCY;
-
-	/* Setup the IO.  This is just copied from the demo supplied by SoftBaugh
-	 for the ES449 demo board. */
-	P1SEL = 0x32;
-	P2SEL = 0x00;
-	P3SEL = 0x00;
-	P4SEL = 0xFC;
-	P5SEL = 0xFF;
-}
-/*-----------------------------------------------------------*/
-
-/* The idle hook is just a copy of the standard integer maths tasks.  See
-Demo/Common/integer.c for rationale. */
-
-void vApplicationIdleHook( void ) __toplevel
-{
-/* These variables are all effectively set to constants so they are volatile to
-ensure the compiler does not just get rid of them. */
-volatile portLONG lValue;
-volatile signed portBASE_TYPE *pxTaskHasExecuted;
-
-	/* Keep performing a calculation and checking the result against a constant. */
-	for( ;; )
-	{
-		/* Perform the calculation.  This will store partial value in
-		registers, resulting in a good test of the context switch mechanism. */
-		lValue = intgCONST1;
-		lValue += intgCONST2;
-
-		/* Yield in case cooperative scheduling is being used. */
-		#if configUSE_PREEMPTION == 0
-		{
-			taskYIELD();
-		}
-		#endif
-
-		/* Finish off the calculation. */
-		lValue *= intgCONST3;
-		lValue /= intgCONST4;
-
-		/* If the calculation is found to be incorrect we stop setting the 
-		TaskHasExecuted variable so the check task can see an error has 
-		occurred. */
-		if( lValue != intgEXPECTED_ANSWER ) /*lint !e774 volatile used to prevent this being optimised out. */
-		{
-			/* Don't bother with mutual exclusion - it is only read from the
-			check task and never written. */
-			xLocalError = pdTRUE;
-		}
-		/* Yield in case cooperative scheduling is being used. */
-		#if configUSE_PREEMPTION == 0
-		{
-			taskYIELD();
-		}
-		#endif
-	}
-}
-
-
-
-
-
diff --git a/Demo/msp430_CrossWorks/serial/serial.c b/Demo/msp430_CrossWorks/serial/serial.c
deleted file mode 100644
index 95945cfe3..000000000
--- a/Demo/msp430_CrossWorks/serial/serial.c
+++ /dev/null
@@ -1,280 +0,0 @@
-/*
-	FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
-
-	This file is part of the FreeRTOS.org distribution.
-
-	FreeRTOS.org is free software; you can redistribute it and/or modify
-	it under the terms of the GNU General Public License as published by
-	the Free Software Foundation; either version 2 of the License, or
-	(at your option) any later version.
-
-	FreeRTOS.org is distributed in the hope that it will be useful,
-	but WITHOUT ANY WARRANTY; without even the implied warranty of
-	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-	GNU General Public License for more details.
-
-	You should have received a copy of the GNU General Public License
-	along with FreeRTOS.org; if not, write to the Free Software
-	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-
-	A special exception to the GPL can be applied should you wish to distribute
-	a combined work that includes FreeRTOS.org, without being obliged to provide
-	the source code for any proprietary components.  See the licensing section 
-	of http://www.FreeRTOS.org for full details of how and when the exception
-	can be applied.
-
-	***************************************************************************
-	See http://www.FreeRTOS.org for documentation, latest information, license 
-	and contact details.  Please ensure to read the configuration and relevant 
-	port sections of the online documentation.
-	***************************************************************************
-*/
-
-
-/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER.   
- * 
- * This file only supports UART 1
- */
-
-/* Standard includes. */
-#include 
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "queue.h"
-#include "task.h"
-
-/* Demo application includes. */
-#include "serial.h"
-
-/* Constants required to setup the hardware. */
-#define serTX_AND_RX			( ( unsigned portCHAR ) 0x03 )
-
-/* Misc. constants. */
-#define serNO_BLOCK				( ( portTickType ) 0 )
-
-/* Enable the UART Tx interrupt. */
-#define vInterruptOn() IFG2 |= UTXIFG1
-
-/* The queue used to hold received characters. */
-static xQueueHandle xRxedChars; 
-
-/* The queue used to hold characters waiting transmission. */
-static xQueueHandle xCharsForTx; 
-
-static volatile portSHORT sTHREEmpty;
-
-/*-----------------------------------------------------------*/
-
-xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
-{
-unsigned portLONG ulBaudRateCount;
-
-	/* Initialise the hardware. */
-
-	/* Generate the baud rate constants for the wanted baud rate. */
-	ulBaudRateCount = configCPU_CLOCK_HZ / ulWantedBaud;
-
-	portENTER_CRITICAL();
-	{
-		/* Create the queues used by the com test task. */
-		xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
-		xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
-
-		/* Reset UART. */
-		UCTL1 |= SWRST;
-
-		/* Set pin function. */
-		P4SEL |= serTX_AND_RX;
-
-		/* All other bits remain at zero for n, 8, 1 interrupt driven operation. 
-		LOOPBACK MODE!*/
-		U1CTL |= CHAR + LISTEN;
-		U1TCTL |= SSEL1;
-
-		/* Setup baud rate low byte. */
-		U1BR0 = ( unsigned portCHAR ) ( ulBaudRateCount & ( unsigned portLONG ) 0xff );
-
-		/* Setup baud rate high byte. */
-		ulBaudRateCount >>= 8UL;
-		U1BR1 = ( unsigned portCHAR ) ( ulBaudRateCount & ( unsigned portLONG ) 0xff );
-
-		/* Enable ports. */
-		ME2 |= UTXE1 + URXE1;
-
-		/* Set. */
-		UCTL1 &= ~SWRST;
-
-		/* Nothing in the buffer yet. */
-		sTHREEmpty = pdTRUE;
-
-		/* Enable interrupts. */
-		IE2 |= URXIE1 + UTXIE1;
-	}
-	portEXIT_CRITICAL();
-	
-	/* Unlike other ports, this serial code does not allow for more than one
-	com port.  We therefore don't return a pointer to a port structure and can
-	instead just return NULL. */
-	return NULL;
-}
-/*-----------------------------------------------------------*/
-
-signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )
-{
-	/* Get the next character from the buffer.  Return false if no characters
-	are available, or arrive before xBlockTime expires. */
-	if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
-	{
-		return pdTRUE;
-	}
-	else
-	{
-		return pdFALSE;
-	}
-}
-/*-----------------------------------------------------------*/
-
-signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )
-{
-signed portBASE_TYPE xReturn;
-
-	/* Transmit a character. */
-
-	portENTER_CRITICAL();
-	{
-		if( sTHREEmpty == pdTRUE )
-		{
-			/* If sTHREEmpty is true then the UART Tx ISR has indicated that 
-			there are no characters queued to be transmitted - so we can
-			write the character directly to the shift Tx register. */
-			sTHREEmpty = pdFALSE;
-			U1TXBUF = cOutChar;
-			xReturn = pdPASS;
-		}
-		else
-		{
-			/* sTHREEmpty is false, so there are still characters waiting to be
-			transmitted.  We have to queue this character so it gets 
-			transmitted	in turn. */
-
-			/* Return false if after the block time there is no room on the Tx 
-			queue.  It is ok to block inside a critical section as each task
-			maintains it's own critical section status. */
-			xReturn = xQueueSend( xCharsForTx, &cOutChar, xBlockTime );
-
-			/* Depending on queue sizing and task prioritisation:  While we 
-			were blocked waiting to post on the queue interrupts were not 
-			disabled.  It is possible that the serial ISR has emptied the 
-			Tx queue, in which case we need to start the Tx off again
-			writing directly to the Tx register. */
-			if( ( sTHREEmpty == pdTRUE ) && ( xReturn == pdPASS ) )
-			{
-				/* Get back the character we just posted. */
-				xQueueReceive( xCharsForTx, &cOutChar, serNO_BLOCK );
-				sTHREEmpty = pdFALSE;
-				U1TXBUF = cOutChar;
-			}
-		}
-	}
-	portEXIT_CRITICAL();
-
-	return pdPASS;
-}
-/*-----------------------------------------------------------*/
-
-#ifdef MSP_ROWLEY_RB_PORT
-
-/* Serial interrupt service routines for the RB port. */
-
-	/*
-	 * UART RX interrupt service routine.
-	 */
-	void vRxISR( void ) __interrupt[ UART1RX_VECTOR ]
-	{
-	signed portCHAR cChar;
-	
-		/* Get the character from the UART and post it on the queue of Rxed 
-		characters. */
-		cChar = U1RXBUF;
-	
-		if( xQueueSendFromISR( xRxedChars, &cChar, pdFALSE ) )
-		{
-			/*If the post causes a task to wake force a context switch 
-			as the woken task may have a higher priority than the task we have 
-			interrupted. */
-			taskYIELD();
-		}
-	}
-	/*-----------------------------------------------------------*/
-	
-	/*
-	 * UART Tx interrupt service routine.
-	 */
-	void vTxISR( void ) __interrupt[ UART1TX_VECTOR ]
-	{
-	signed portCHAR cChar;
-	portBASE_TYPE xTaskWoken;
-	
-		/* The previous character has been transmitted.  See if there are any
-		further characters waiting transmission. */
-	
-		if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWoken ) == pdTRUE )
-		{
-			/* There was another character queued - transmit it now. */
-			U1TXBUF = cChar;
-		}
-		else
-		{
-			/* There were no other characters to transmit. */
-			sTHREEmpty = pdTRUE;
-		}
-	}
-
-#endif
-/*-----------------------------------------------------------*/
-
-#ifdef MSP_ROWLEY_MP_PORT
-
-/* Serial port interrupts for the alternative port code. */
-
-	void ISRCom1Rx( void )
-	{
-	signed portCHAR cChar;
-	
-		/* Get the character from the UART and post it on the queue of Rxed 
-		characters. */
-		cChar = U1RXBUF;
-	
-		if( xQueueSendFromISR( xRxedChars, &cChar, pdFALSE ) )
-		{
-			/*If the post causes a task to wake force a context switch 
-			as the woken task may have a higher priority than the task we have 
-			interrupted. */
-			portEXIT_SWITCHING_ISR( pdTRUE );
-		}
-	}
-	/*-----------------------------------------------------------*/
-	
-	void ISRCom1Tx( void )
-	{
-	signed portCHAR cChar;
-	portBASE_TYPE xTaskWoken;
-	
-		/* The previous character has been transmitted.  See if there are any
-		further characters waiting transmission. */
-	
-		if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWoken ) == pdTRUE )
-		{
-			/* There was another character queued - transmit it now. */
-			U1TXBUF = cChar;
-		}
-		else
-		{
-			/* There were no other characters to transmit. */
-			sTHREEmpty = pdTRUE;
-		}
-	}
-
-#endif
-/*-----------------------------------------------------------*/
diff --git a/Demo/msp430_GCC/FreeRTOSConfig.h b/Demo/msp430_GCC/FreeRTOSConfig.h
deleted file mode 100644
index 9ec609381..000000000
--- a/Demo/msp430_GCC/FreeRTOSConfig.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
-	FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
-
-	This file is part of the FreeRTOS.org distribution.
-
-	FreeRTOS.org is free software; you can redistribute it and/or modify
-	it under the terms of the GNU General Public License as published by
-	the Free Software Foundation; either version 2 of the License, or
-	(at your option) any later version.
-
-	FreeRTOS.org is distributed in the hope that it will be useful,
-	but WITHOUT ANY WARRANTY; without even the implied warranty of
-	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-	GNU General Public License for more details.
-
-	You should have received a copy of the GNU General Public License
-	along with FreeRTOS.org; if not, write to the Free Software
-	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-
-	A special exception to the GPL can be applied should you wish to distribute
-	a combined work that includes FreeRTOS.org, without being obliged to provide
-	the source code for any proprietary components.  See the licensing section 
-	of http://www.FreeRTOS.org for full details of how and when the exception
-	can be applied.
-
-	***************************************************************************
-	See http://www.FreeRTOS.org for documentation, latest information, license 
-	and contact details.  Please ensure to read the configuration and relevant 
-	port sections of the online documentation.
-	***************************************************************************
-*/
-
-#ifndef FREERTOS_CONFIG_H
-#define FREERTOS_CONFIG_H
-
-#include 
-
-/*-----------------------------------------------------------
- * Application specific definitions.
- *
- * These definitions should be adjusted for your particular hardware and
- * application requirements.
- *
- * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
- * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. 
- *----------------------------------------------------------*/
-
-#define configUSE_PREEMPTION		1
-#define configUSE_IDLE_HOOK			0
-#define configUSE_TICK_HOOK			0
-#define configCPU_CLOCK_HZ			( ( unsigned portLONG ) 7995392 ) /* Clock setup from main.c in the demo application. */
-#define configTICK_RATE_HZ			( ( portTickType ) 1000 )
-#define configMAX_PRIORITIES		( ( unsigned portBASE_TYPE ) 4 )
-#define configMINIMAL_STACK_SIZE	( ( unsigned portSHORT ) 50 )
-#define configTOTAL_HEAP_SIZE		( ( size_t ) ( 1800 ) )
-#define configMAX_TASK_NAME_LEN		( 8 )
-#define configUSE_TRACE_FACILITY	0
-#define configUSE_16_BIT_TICKS		1
-#define configIDLE_SHOULD_YIELD		1
-
-/* Co-routine definitions. */
-#define configUSE_CO_ROUTINES 		0
-#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
-
-/* Set the following definitions to 1 to include the API function, or zero
-to exclude the API function. */
-
-#define INCLUDE_vTaskPrioritySet		0
-#define INCLUDE_uxTaskPriorityGet		0
-#define INCLUDE_vTaskDelete				1
-#define INCLUDE_vTaskCleanUpResources	0
-#define INCLUDE_vTaskSuspend			0
-#define INCLUDE_vTaskDelayUntil			1
-#define INCLUDE_vTaskDelay				1
-
-
-
-
-
-
-
-#endif /* FREERTOS_CONFIG_H */
diff --git a/Demo/msp430_GCC/ParTest/ParTest.c b/Demo/msp430_GCC/ParTest/ParTest.c
deleted file mode 100644
index c3f1171e4..000000000
--- a/Demo/msp430_GCC/ParTest/ParTest.c
+++ /dev/null
@@ -1,212 +0,0 @@
-/*
-	FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
-
-	This file is part of the FreeRTOS.org distribution.
-
-	FreeRTOS.org is free software; you can redistribute it and/or modify
-	it under the terms of the GNU General Public License as published by
-	the Free Software Foundation; either version 2 of the License, or
-	(at your option) any later version.
-
-	FreeRTOS.org is distributed in the hope that it will be useful,
-	but WITHOUT ANY WARRANTY; without even the implied warranty of
-	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-	GNU General Public License for more details.
-
-	You should have received a copy of the GNU General Public License
-	along with FreeRTOS.org; if not, write to the Free Software
-	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-
-	A special exception to the GPL can be applied should you wish to distribute
-	a combined work that includes FreeRTOS.org, without being obliged to provide
-	the source code for any proprietary components.  See the licensing section 
-	of http://www.FreeRTOS.org for full details of how and when the exception
-	can be applied.
-
-	***************************************************************************
-	See http://www.FreeRTOS.org for documentation, latest information, license 
-	and contact details.  Please ensure to read the configuration and relevant 
-	port sections of the online documentation.
-	***************************************************************************
-*/
-
-/*-----------------------------------------------------------
- * Characters on the LCD are used to simulate LED's.  In this case the 'ParTest'
- * is really operating on the LCD display.
- *-----------------------------------------------------------*/
-
-/*
- * This demo is configured to execute on the ES449 prototyping board from
- * SoftBaugh. The ES449 has a built in LCD display and a single built in user
- * LED.  Therefore, in place of flashing an LED, the 'flash' and 'check' tasks
- * toggle '*' characters on the LCD.  The left most '*' represents LED 0, the
- * next LED 1, etc.
- *
- * There is a single genuine on board LED referenced as LED 10.
- */
-
-/* Standard includes. */
-#include 
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Demo application includes. */
-#include "partest.h"
-
-/* Constants required to setup the LCD. */
-#define LCD_DIV_64 5
-
-/* Constants required to access the "LED's".  The LED segments are turned on
-and off to generate '*' characters. */
-#define partstNUM_LEDS			( ( unsigned portCHAR ) 6 )
-#define partstSEGMENTS_ON		( ( unsigned portCHAR ) 0x0f )
-#define partstSEGMENTS_OFF		( ( unsigned portCHAR ) 0x00 )
-
-/* The LED number of the real on board LED, rather than a simulated LED. */
-#define partstON_BOARD_LED		( ( unsigned portBASE_TYPE ) 10 )
-#define mainON_BOARD_LED_BIT	( ( unsigned portCHAR ) 0x01 )
-
-/* The LCD segments used to generate the '*' characters for LED's 0 to 5. */
-unsigned portCHAR * const ucRHSSegments[ partstNUM_LEDS ] = {	( unsigned portCHAR * )0xa4, 
-																( unsigned portCHAR * )0xa2, 
-																( unsigned portCHAR * )0xa0, 
-																( unsigned portCHAR * )0x9e,
-																( unsigned portCHAR * )0x9c,
-																( unsigned portCHAR * )0x9a };
-
-unsigned portCHAR * const ucLHSSegments[ partstNUM_LEDS ] = {	( unsigned portCHAR * )0xa3, 
-																( unsigned portCHAR * )0xa1, 
-																( unsigned portCHAR * )0x9f, 
-																( unsigned portCHAR * )0x9d,
-																( unsigned portCHAR * )0x9b,
-																( unsigned portCHAR * )0x99 };
-
-/*
- * Toggle the single genuine built in LED.
- */
-static void prvToggleOnBoardLED( void );
-
-/*-----------------------------------------------------------*/
-
-void vParTestInitialise( void )
-{
-	/* Initialise the LCD hardware. */
-
-	/* Used for the onboard LED. */
-	P1DIR = 0x01;
-
-	// Setup Basic Timer for LCD operation
-	BTCTL = (LCD_DIV_64+0x23);
-
-	// Setup port functions
-	P1SEL = 0x32;
-	P2SEL = 0x00;
-	P3SEL = 0x00;
-	P4SEL = 0xFC;
-	P5SEL = 0xFF;
-	
-	/* Initialise all segments to off. */
-	LCDM1 = partstSEGMENTS_OFF;	
-	LCDM2 = partstSEGMENTS_OFF;	
-	LCDM3 = partstSEGMENTS_OFF;	
-	LCDM4 = partstSEGMENTS_OFF;	
-	LCDM5 = partstSEGMENTS_OFF;	
-	LCDM6 = partstSEGMENTS_OFF;	
-	LCDM7 = partstSEGMENTS_OFF;	
-	LCDM8 = partstSEGMENTS_OFF;	
-	LCDM9 = partstSEGMENTS_OFF;	
-	LCDM10 = partstSEGMENTS_OFF;	
-	LCDM11 = partstSEGMENTS_OFF;	
-	LCDM12 = partstSEGMENTS_OFF;	
-	LCDM13 = partstSEGMENTS_OFF;	
-	LCDM14 = partstSEGMENTS_OFF;	
-	LCDM15 = partstSEGMENTS_OFF;	
-	LCDM16 = partstSEGMENTS_OFF;	
-	LCDM17 = partstSEGMENTS_OFF;	
-	LCDM18 = partstSEGMENTS_OFF;	
-	LCDM19 = partstSEGMENTS_OFF;	
-	LCDM20 = partstSEGMENTS_OFF;	
-
-	/* Setup LCD control. */
-	LCDCTL = (LCDSG0_7|LCD4MUX|LCDON);
-}
-/*-----------------------------------------------------------*/
-
-void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
-{
-	/* Set or clear the output [in this case show or hide the '*' character. */
-	if( uxLED < ( portBASE_TYPE ) partstNUM_LEDS )
-	{
-		vTaskSuspendAll();
-		{
-			if( xValue )
-			{
-				/* Turn on the segments required to show the '*'. */
-				*( ucRHSSegments[ uxLED ] ) = partstSEGMENTS_ON;
-				*( ucLHSSegments[ uxLED ] ) = partstSEGMENTS_ON;
-			}
-			else
-			{
-				/* Turn off all the segments. */
-				*( ucRHSSegments[ uxLED ] ) = partstSEGMENTS_OFF;
-				*( ucLHSSegments[ uxLED ] ) = partstSEGMENTS_OFF;
-			}
-		}
-		xTaskResumeAll();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
-{
-	if( uxLED < ( portBASE_TYPE ) partstNUM_LEDS )
-	{
-		vTaskSuspendAll();
-		{
-			/* If the '*' is already showing - hide it.  If it is not already
-			showing then show it. */
-			if( *( ucRHSSegments[ uxLED ] ) )
-			{
-				*( ucRHSSegments[ uxLED ] ) = partstSEGMENTS_OFF;
-				*( ucLHSSegments[ uxLED ] ) = partstSEGMENTS_OFF;
-			}
-			else
-			{
-				*( ucRHSSegments[ uxLED ] ) = partstSEGMENTS_ON;
-				*( ucLHSSegments[ uxLED ] ) = partstSEGMENTS_ON;
-			}
-		}
-		xTaskResumeAll();
-	}
-	else
-	{
-		if( uxLED == partstON_BOARD_LED )
-		{
-			/* The request related to the genuine on board LED. */
-			prvToggleOnBoardLED();
-		}
-	}	
-}
-/*-----------------------------------------------------------*/
-
-static void prvToggleOnBoardLED( void )
-{
-static unsigned portSHORT sState = pdFALSE;
-
-	/* Toggle the state of the single genuine on board LED. */
-	if( sState )	
-	{
-		P1OUT |= mainON_BOARD_LED_BIT;
-	}
-	else
-	{
-		P1OUT &= ~mainON_BOARD_LED_BIT;
-	}
-
-	sState = !sState;
-}
-/*-----------------------------------------------------------*/
-
-
diff --git a/Demo/msp430_GCC/gdb.ini b/Demo/msp430_GCC/gdb.ini
deleted file mode 100644
index ff3ac1401..000000000
--- a/Demo/msp430_GCC/gdb.ini
+++ /dev/null
@@ -1,8 +0,0 @@
-target remote localhost:3333
-kill
-target remote localhost:3333
-b main
-c
-
-
-
diff --git a/Demo/msp430_GCC/main.c b/Demo/msp430_GCC/main.c
deleted file mode 100644
index c6ed28775..000000000
--- a/Demo/msp430_GCC/main.c
+++ /dev/null
@@ -1,242 +0,0 @@
-/*
-	FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
-
-	This file is part of the FreeRTOS.org distribution.
-
-	FreeRTOS.org is free software; you can redistribute it and/or modify
-	it under the terms of the GNU General Public License as published by
-	the Free Software Foundation; either version 2 of the License, or
-	(at your option) any later version.
-
-	FreeRTOS.org is distributed in the hope that it will be useful,
-	but WITHOUT ANY WARRANTY; without even the implied warranty of
-	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-	GNU General Public License for more details.
-
-	You should have received a copy of the GNU General Public License
-	along with FreeRTOS.org; if not, write to the Free Software
-	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-
-	A special exception to the GPL can be applied should you wish to distribute
-	a combined work that includes FreeRTOS.org, without being obliged to provide
-	the source code for any proprietary components.  See the licensing section 
-	of http://www.FreeRTOS.org for full details of how and when the exception
-	can be applied.
-
-	***************************************************************************
-	See http://www.FreeRTOS.org for documentation, latest information, license 
-	and contact details.  Please ensure to read the configuration and relevant 
-	port sections of the online documentation.
-	***************************************************************************
-*/
-
-/*
- * Creates all the demo application tasks, then starts the scheduler.  The WEB
- * documentation provides more details of the demo application tasks.
- * 
- * This demo is configured to execute on the ES449 prototyping board from
- * SoftBaugh. The ES449 has a built in LCD display and a single built in user
- * LED.  Therefore, in place of flashing an LED, the 'flash' and 'check' tasks
- * toggle '*' characters on the LCD.  The left most '*' represents LED 0, the
- * next LED 1, etc.
- *
- * Main. c also creates a task called 'Check'.  This only executes every three 
- * seconds but has the highest priority so is guaranteed to get processor time.  
- * Its main function is to check that all the other tasks are still operational.  
- * Each task that does not flash an LED maintains a unique count that is 
- * incremented each time the task successfully completes its function.  Should 
- * any error occur within such a task the count is permanently halted.  The 
- * 'check' task inspects the count of each task to ensure it has changed since
- * the last time the check task executed.  If all the count variables have 
- * changed all the tasks are still executing error free, and the check task
- * toggles an LED with a three second period.  Should any task contain an error 
- * at any time the LED toggle rate will increase to 500ms.
- *
- * Please read the documentation for the MSP430 port available on
- * http://www.FreeRTOS.org.
- */
-
-/* Standard includes. */
-#include 
-#include 
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Demo application includes. */
-#include "partest.h"
-#include "flash.h"
-#include "integer.h"
-#include "comtest2.h"
-#include "PollQ.h"
-
-/* Constants required for hardware setup. */
-#define mainALL_BITS_OUTPUT		( ( unsigned portCHAR ) 0xff )
-#define mainMAX_FREQUENCY		( ( unsigned portCHAR ) 121 )
-
-/* Constants that define the LED's used by the various tasks. [in this case
-the '*' characters on the LCD represent LED's] */
-#define mainCHECK_LED			( 4 )
-#define mainCOM_TEST_LED		( 10 )
-
-/* Demo task priorities. */
-#define mainCHECK_TASK_PRIORITY			( tskIDLE_PRIORITY + 3 )
-#define mainCOM_TEST_PRIORITY			( tskIDLE_PRIORITY + 2 )
-#define mainQUEUE_POLL_PRIORITY			( tskIDLE_PRIORITY + 2 )
-#define mainLED_TASK_PRIORITY			( tskIDLE_PRIORITY + 1 )
-
-/* Baud rate used by the COM test tasks. */
-#define mainCOM_TEST_BAUD_RATE			( ( unsigned portLONG ) 19200 )
-
-/* The frequency at which the 'Check' tasks executes.  See the comments at the 
-top of the page.  When the system is operating error free the 'Check' task
-toggles an LED every three seconds.  If an error is discovered in any task the
-rate is increased to 500 milliseconds.  [in this case the '*' characters on the 
-LCD represent LED's]*/
-#define mainNO_ERROR_CHECK_DELAY		( ( portTickType ) 3000 / portTICK_RATE_MS  )
-#define mainERROR_CHECK_DELAY			( ( portTickType ) 500 / portTICK_RATE_MS  )
-
-/* 
- * The function that implements the Check task.  See the comments at the head
- * of the page for implementation details.
- */ 
-static void vErrorChecks( void *pvParameters );
-
-/*
- * Called by the Check task.  Returns pdPASS if all the other tasks are found
- * to be operating without error - otherwise returns pdFAIL.
- */
-static portSHORT prvCheckOtherTasksAreStillRunning( void );
-
-/* 
- * Perform the hardware setup required by the ES449 in order to run the demo
- * application.
- */
-static void prvSetupHardware( void );
-
-/*-----------------------------------------------------------*/
-
-/*
- * Start the demo application tasks - then start the real time scheduler.
- */
-int main( void )
-{
-	/* Setup the hardware ready for the demo. */
-	prvSetupHardware();
-	vParTestInitialise();
-
-	/* Start the standard demo application tasks. */
-	vStartLEDFlashTasks( mainLED_TASK_PRIORITY );
-	vStartIntegerMathTasks( tskIDLE_PRIORITY );
-	vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED - 1 );
-	vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
-
-	/* Start the 'Check' task which is defined in this file. */
-	xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );	
-
-	/* Start the scheduler. */
-	vTaskStartScheduler();
-
-	/* As the scheduler has been started the demo applications tasks will be
-	executing and we should never get here! */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-static void vErrorChecks( void *pvParameters )
-{
-static volatile unsigned portLONG ulDummyVariable = 3UL;
-portTickType xDelayPeriod = mainNO_ERROR_CHECK_DELAY;
-
-	/* Cycle for ever, delaying then checking all the other tasks are still
-	operating without error. */
-	for( ;; )
-	{
-		/* Wait until it is time to check again.  The time we wait here depends
-		on whether an error has been detected or not.  When an error is 
-		detected the time is shortened resulting in a faster LED flash rate. */
-		vTaskDelay( xDelayPeriod );
-
-		/* Perform a bit of 32bit maths to ensure the registers used by the 
-		integer tasks get some exercise outside of the integer tasks 
-		themselves. The result here is not important we are just deliberately
-		changing registers used by other tasks to ensure that their context
-		switch is operating as required. - see the demo application 
-		documentation for more info. */
-		ulDummyVariable *= 3UL;
-		
-		/* See if the other tasks are all ok. */
-		if( prvCheckOtherTasksAreStillRunning() != pdPASS )
-		{
-			/* An error occurred in one of the tasks so shorten the delay 
-			period - which has the effect of increasing the frequency of the
-			LED toggle. */
-			xDelayPeriod = mainERROR_CHECK_DELAY;
-		}
-
-		/* Flash! */
-		vParTestToggleLED( mainCHECK_LED );
-	}
-}
-/*-----------------------------------------------------------*/
-
-static portSHORT prvCheckOtherTasksAreStillRunning( void )
-{
-static portSHORT sNoErrorFound = pdTRUE;
-
-	/* The demo tasks maintain a count that increments every cycle of the task
-	provided that the task has never encountered an error.  This function 
-	checks the counts maintained by the tasks to ensure they are still being
-	incremented.  A count remaining at the same value between calls therefore
-	indicates that an error has been detected.  Only tasks that do not flash
-	an LED are checked. */
-
-	if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
-	{
-		sNoErrorFound = pdFALSE;
-	}
-
-	if( xAreComTestTasksStillRunning() != pdTRUE )
-	{
-		sNoErrorFound = pdFALSE;
-	}
-	
-	if( xArePollingQueuesStillRunning() != pdTRUE )
-	{
-		sNoErrorFound = pdFALSE;
-	}
-	
-	return sNoErrorFound;
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetupHardware( void )
-{
-	/* Stop the watchdog. */
-	WDTCTL = WDTPW + WDTHOLD;
-
-	/* Setup DCO+ for ( xtal * D * (N + 1) ) operation. */
-	FLL_CTL0 |= DCOPLUS + XCAP18PF; 
-
-	/* X2 DCO frequency, 8MHz nominal DCO */
-	SCFI0 |= FN_4;                  
-
-	/* (121+1) x 32768 x 2 = 7.99 Mhz */
-	SCFQCTL = mainMAX_FREQUENCY;
-
-	/* Setup the IO as per the SoftBaugh demo for the same target hardware. */
-	P1SEL = 0x32;
-	P2SEL = 0x00;
-	P3SEL = 0x00;
-	P4SEL = 0xFC;
-	P5SEL = 0xFF;
-}
-/*-----------------------------------------------------------*/
-
-
-
-
-
-
-
diff --git a/Demo/msp430_GCC/makefile b/Demo/msp430_GCC/makefile
deleted file mode 100644
index 45dc7143a..000000000
--- a/Demo/msp430_GCC/makefile
+++ /dev/null
@@ -1,87 +0,0 @@
-#	FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
-#
-#	This file is part of the FreeRTOS.org distribution.
-#
-#	FreeRTOS.org is free software; you can redistribute it and/or modify
-#	it under the terms of the GNU General Public License as published by
-#	the Free Software Foundation; either version 2 of the License, or
-#	(at your option) any later version.
-#
-#	FreeRTOS.org is distributed in the hope that it will be useful,
-#	but WITHOUT ANY WARRANTY; without even the implied warranty of
-#	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-#	GNU General Public License for more details.
-#
-#	You should have received a copy of the GNU General Public License
-#	along with FreeRTOS.org; if not, write to the Free Software
-#	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-#
-#	A special exception to the GPL can be applied should you wish to distribute
-#	a combined work that includes FreeRTOS.org, without being obliged to provide
-#	the source code for any proprietary components.  See the licensing section 
-#	of http://www.FreeRTOS.org for full details of how and when the exception
-#	can be applied.
-#
-#	***************************************************************************
-#	See http://www.FreeRTOS.org for documentation, latest information, license 
-#	and contact details.  Please ensure to read the configuration and relevant 
-#	port sections of the online documentation.
-#	***************************************************************************
-
-
-CC=msp430-gcc
-OBJCOPY=msp430-objcopy
-DEBUG=-g
-OPT=-Os
-WARNINGS=-Wall -Wshadow -Wpointer-arith -Wbad-function-cast -Wcast-align -Wsign-compare \
-		-Waggregate-return -Wstrict-prototypes -Wmissing-prototypes -Wmissing-declarations -Wunused
-
-CFLAGS=-mmcu=msp430x449 $(OPT) $(DEBUG) -I. -I../../Source/include -I../Common/include -DGCC_MSP430 $(WARNINGS)
-
-# Setup paths to source code
-SOURCE_PATH = ../../Source
-PORT_PATH = ../../Source/portable/GCC/MSP430F449
-DEMO_PATH = ../Common/Minimal
-
-#
-# Source files that can be built to THUMB mode.
-#
-SRC = \
-main.c \
-ParTest/ParTest.c \
-serial/serial.c \
-$(SOURCE_PATH)/tasks.c \
-$(SOURCE_PATH)/list.c \
-$(SOURCE_PATH)/queue.c \
-$(SOURCE_PATH)/portable/MemMang/heap_1.c \
-$(PORT_PATH)/port.c \
-$(DEMO_PATH)/flash.c \
-$(DEMO_PATH)/integer.c \
-$(DEMO_PATH)/comtest.c \
-$(DEMO_PATH)/PollQ.c
-
-#
-# Define all object files.
-#
-OBJ = $(SRC:.c=.o)
-
-a.out : $(OBJ) makefile
-	$(CC) $(OBJ) $(CFLAGS)
-
-$(OBJ) : %.o : %.c makefile
-	$(CC) -c $(CFLAGS) $< -o $@	
-	
-clean :
-	touch makefile
-	
-
-
-
-
-
-
-
-
-	
-
-
diff --git a/Demo/msp430_GCC/serial/serial.c b/Demo/msp430_GCC/serial/serial.c
deleted file mode 100644
index 054aa5abd..000000000
--- a/Demo/msp430_GCC/serial/serial.c
+++ /dev/null
@@ -1,234 +0,0 @@
-/*
-	FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
-
-	This file is part of the FreeRTOS.org distribution.
-
-	FreeRTOS.org is free software; you can redistribute it and/or modify
-	it under the terms of the GNU General Public License as published by
-	the Free Software Foundation; either version 2 of the License, or
-	(at your option) any later version.
-
-	FreeRTOS.org is distributed in the hope that it will be useful,
-	but WITHOUT ANY WARRANTY; without even the implied warranty of
-	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-	GNU General Public License for more details.
-
-	You should have received a copy of the GNU General Public License
-	along with FreeRTOS.org; if not, write to the Free Software
-	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-
-	A special exception to the GPL can be applied should you wish to distribute
-	a combined work that includes FreeRTOS.org, without being obliged to provide
-	the source code for any proprietary components.  See the licensing section 
-	of http://www.FreeRTOS.org for full details of how and when the exception
-	can be applied.
-
-	***************************************************************************
-	See http://www.FreeRTOS.org for documentation, latest information, license 
-	and contact details.  Please ensure to read the configuration and relevant 
-	port sections of the online documentation.
-	***************************************************************************
-*/
-
-
-/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER.   
- * 
- * This file only supports UART 1
- */
-
-/* Standard includes. */
-#include 
-#include 
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "queue.h"
-#include "task.h"
-
-/* Demo application includes. */
-#include "serial.h"
-
-/* Constants required to setup the hardware. */
-#define serTX_AND_RX			( ( unsigned portCHAR ) 0x03 )
-
-/* Misc. constants. */
-#define serNO_BLOCK				( ( portTickType ) 0 )
-
-/* Enable the UART Tx interrupt. */
-#define vInterruptOn() IFG2 |= UTXIFG1
-
-/* The queue used to hold received characters. */
-static xQueueHandle xRxedChars; 
-
-/* The queue used to hold characters waiting transmission. */
-static xQueueHandle xCharsForTx; 
-
-static volatile portSHORT sTHREEmpty;
-
-/* Interrupt service routines. */
-interrupt (UART1RX_VECTOR) vRxISR( void );
-interrupt (UART1TX_VECTOR) vTxISR( void );
-
-/*-----------------------------------------------------------*/
-
-xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
-{
-unsigned portLONG ulBaudRateCount;
-
-	/* Initialise the hardware. */
-
-	/* Generate the baud rate constants for the wanted baud rate. */
-	ulBaudRateCount = configCPU_CLOCK_HZ / ulWantedBaud;
-
-	portENTER_CRITICAL();
-	{
-		/* Create the queues used by the com test task. */
-		xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
-		xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
-
-		/* Reset UART. */
-		UCTL1 |= SWRST;
-
-		/* Set pin function. */
-		P4SEL |= serTX_AND_RX;
-
-		/* All other bits remain at zero for n, 8, 1 interrupt driven operation. 
-		LOOPBACK MODE!*/
-		U1CTL |= CHAR + LISTEN;
-		U1TCTL |= SSEL1;
-
-		/* Setup baud rate low byte. */
-		U1BR0 = ( unsigned portCHAR ) ( ulBaudRateCount & ( unsigned portLONG ) 0xff );
-
-		/* Setup baud rate high byte. */
-		ulBaudRateCount >>= 8UL;
-		U1BR1 = ( unsigned portCHAR ) ( ulBaudRateCount & ( unsigned portLONG ) 0xff );
-
-		/* Enable ports. */
-		ME2 |= UTXE1 + URXE1;
-
-		/* Set. */
-		UCTL1 &= ~SWRST;
-
-		/* Nothing in the buffer yet. */
-		sTHREEmpty = pdTRUE;
-
-		/* Enable interrupts. */
-		IE2 |= URXIE1 + UTXIE1;
-	}
-	portEXIT_CRITICAL();
-	
-	/* Unlike other ports, this serial code does not allow for more than one
-	com port.  We therefore don't return a pointer to a port structure and can
-	instead just return NULL. */
-	return NULL;
-}
-/*-----------------------------------------------------------*/
-
-signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )
-{
-	/* Get the next character from the buffer.  Return false if no characters
-	are available, or arrive before xBlockTime expires. */
-	if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
-	{
-		return pdTRUE;
-	}
-	else
-	{
-		return pdFALSE;
-	}
-}
-/*-----------------------------------------------------------*/
-
-signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )
-{
-signed portBASE_TYPE xReturn;
-
-	/* Transmit a character. */
-
-	portENTER_CRITICAL();
-	{
-		if( sTHREEmpty == pdTRUE )
-		{
-			/* If sTHREEmpty is true then the UART Tx ISR has indicated that 
-			there are no characters queued to be transmitted - so we can
-			write the character directly to the shift Tx register. */
-			sTHREEmpty = pdFALSE;
-			U1TXBUF = cOutChar;
-			xReturn = pdPASS;
-		}
-		else
-		{
-			/* sTHREEmpty is false, so there are still characters waiting to be
-			transmitted.  We have to queue this character so it gets 
-			transmitted	in turn. */
-
-			/* Return false if after the block time there is no room on the Tx 
-			queue.  It is ok to block inside a critical section as each task
-			maintains it's own critical section status. */
-			xReturn = xQueueSend( xCharsForTx, &cOutChar, xBlockTime );
-
-			/* Depending on queue sizing and task prioritisation:  While we 
-			were blocked waiting to post on the queue interrupts were not 
-			disabled.  It is possible that the serial ISR has emptied the 
-			Tx queue, in which case we need to start the Tx off again
-			writing directly to the Tx register. */
-			if( ( sTHREEmpty == pdTRUE ) && ( xReturn == pdPASS ) )
-			{
-				/* Get back the character we just posted. */
-				xQueueReceive( xCharsForTx, &cOutChar, serNO_BLOCK );
-				sTHREEmpty = pdFALSE;
-				U1TXBUF = cOutChar;
-			}
-		}
-	}
-	portEXIT_CRITICAL();
-
-	return pdPASS;
-}
-/*-----------------------------------------------------------*/
-
-/*
- * UART RX interrupt service routine.
- */
-interrupt (UART1RX_VECTOR) vRxISR( void )
-{
-signed portCHAR cChar;
-
-	/* Get the character from the UART and post it on the queue of Rxed 
-	characters. */
-	cChar = U1RXBUF;
-
-	if( xQueueSendFromISR( xRxedChars, &cChar, pdFALSE ) )
-	{
-		/*If the post causes a task to wake force a context switch 
-		as the woken task may have a higher priority than the task we have 
-		interrupted. */
-		taskYIELD();
-	}
-}
-/*-----------------------------------------------------------*/
-
-/*
- * UART Tx interrupt service routine.
- */
-interrupt (UART1TX_VECTOR) vTxISR( void )
-{
-signed portCHAR cChar;
-portBASE_TYPE xTaskWoken;
-
-	/* The previous character has been transmitted.  See if there are any
-	further characters waiting transmission. */
-
-	if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWoken ) == pdTRUE )
-	{
-		/* There was another character queued - transmit it now. */
-		U1TXBUF = cChar;
-	}
-	else
-	{
-		/* There were no other characters to transmit. */
-		sTHREEmpty = pdTRUE;
-	}
-}
-
diff --git a/Demo/readme.txt b/Demo/readme.txt
deleted file mode 100644
index 813c257cc..000000000
--- a/Demo/readme.txt
+++ /dev/null
@@ -1,16 +0,0 @@
-Each RTOS port has a demo application to demonstrate it's use.
-
-+ The Demo/Common directory contains the demo application files as described on 
-the http://www.FreeRTOS.org WEB site.  Each file creates one or more tasks.
-The files in the Demo/Common directory are used by every demo application for
-every port.
-
-+ All the other directories contain a project or makefile for the demo
-application targeted at a particular microcontroller.  
-
-
-For example, if you are interested in the ATMega323 demo application for
-the WinAVR tools then the AVR_ATMega323_WinAVR directory contains the 
-relevant makefile.  The makefile includes files from the Demo/ATMega323 
-and the Demo/Common directories.  If this is the only port you are 
-interested in then all the other directories can be ignored.
diff --git a/Demo/uIP_Demo_IAR_ARM7/EMAC/EMAClISR.s79 b/Demo/uIP_Demo_IAR_ARM7/EMAC/EMAClISR.s79
deleted file mode 100644
index 6f309cbb4..000000000
--- a/Demo/uIP_Demo_IAR_ARM7/EMAC/EMAClISR.s79
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
-	FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
-
-	This file is part of the FreeRTOS.org distribution.
-
-	FreeRTOS.org is free software; you can redistribute it and/or modify
-	it under the terms of the GNU General Public License as published by
-	the Free Software Foundation; either version 2 of the License, or
-	(at your option) any later version.
-
-	FreeRTOS.org is distributed in the hope that it will be useful,
-	but WITHOUT ANY WARRANTY; without even the implied warranty of
-	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-	GNU General Public License for more details.
-
-	You should have received a copy of the GNU General Public License
-	along with FreeRTOS.org; if not, write to the Free Software
-	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-
-	A special exception to the GPL can be applied should you wish to distribute
-	a combined work that includes FreeRTOS.org, without being obliged to provide
-	the source code for any proprietary components.  See the licensing section
-	of http://www.FreeRTOS.org for full details of how and when the exception
-	can be applied.
-
-	***************************************************************************
-	See http://www.FreeRTOS.org for documentation, latest information, license
-	and contact details.  Please ensure to read the configuration and relevant
-	port sections of the online documentation.
-	***************************************************************************
-*/
-
-		RSEG ICODE:CODE
-		CODE32
-
-		EXTERN vEMACISR
-		PUBLIC vEMACISREntry
-
-; Wrapper for the EMAC interrupt service routine.  This can cause a
-; context switch so requires an assembly wrapper.
-
-; Defines the portSAVE_CONTEXT and portRESTORE_CONTEXT macros.
-#include "ISR_Support.h"
-
-vEMACISREntry:
-
-	portSAVE_CONTEXT			; Save the context of the current task.
-
-	bl	vEMACISR				; Call the ISR routine.
-
-	portRESTORE_CONTEXT			; Restore the context of the current task -
-								; which may be different to the task that
-								; was interrupted.
-
-		END
-
diff --git a/Demo/uIP_Demo_IAR_ARM7/EMAC/SAM7_EMAC.c b/Demo/uIP_Demo_IAR_ARM7/EMAC/SAM7_EMAC.c
deleted file mode 100644
index 22ec8fe82..000000000
--- a/Demo/uIP_Demo_IAR_ARM7/EMAC/SAM7_EMAC.c
+++ /dev/null
@@ -1,703 +0,0 @@
-/*
-	FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
-
-	This file is part of the FreeRTOS.org distribution.
-
-	FreeRTOS.org is free software; you can redistribute it and/or modify
-	it under the terms of the GNU General Public License as published by
-	the Free Software Foundation; either version 2 of the License, or
-	(at your option) any later version.
-
-	FreeRTOS.org is distributed in the hope that it will be useful,
-	but WITHOUT ANY WARRANTY; without even the implied warranty of
-	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-	GNU General Public License for more details.
-
-	You should have received a copy of the GNU General Public License
-	along with FreeRTOS.org; if not, write to the Free Software
-	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-
-	A special exception to the GPL can be applied should you wish to distribute
-	a combined work that includes FreeRTOS.org, without being obliged to provide
-	the source code for any proprietary components.  See the licensing section
-	of http://www.FreeRTOS.org for full details of how and when the exception
-	can be applied.
-
-	***************************************************************************
-	See http://www.FreeRTOS.org for documentation, latest information, license
-	and contact details.  Please ensure to read the configuration and relevant
-	port sections of the online documentation.
-	***************************************************************************
-*/
-
-/*
- * Basic interrupt driven driver for the EMAC peripheral.  This driver is not
- * reentrant as with uIP the buffers are only ever accessed from a single task.
- *
- * The simple buffer management used within uIP allows the EMAC driver to also
- * be simplistic.  The driver contained within the lwIP demo is more
- * comprehensive.
- */
-
-
-/*
-Changes from V3.2.2
-
-	+ Corrected the byte order when writing the MAC address to the MAC.
-	+ Support added for MII interfaces.  Previously only RMII was supported.
-
-Changes from V3.2.3
-
-	+ The MII interface is now the default.
-	+ Modified the initialisation sequence slightly to allow auto init more
-	  time to complete.
-
-Changes from V3.2.4
-
-	+ Also read the EMAC_RSR register in the EMAC ISR as a work around the 
-	  the EMAC bug that can reset the RX bit in EMAC_ISR register before the
-	  bit has been read.
-
-Changes from V4.0.4
-
-	+ Corrected the Rx frame length mask when obtaining the length from the
-	  rx descriptor.
-
-*/
-
-/* Standard includes. */
-#include 
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "semphr.h"
-#include "task.h"
-
-/* uIP includes. */
-#include "uip.h"
-
-/* Hardware specific includes. */
-#include "Emac.h"
-#include "mii.h"
-
-
-/* USE_RMII_INTERFACE must be defined as 1 to use an RMII interface, or 0
-to use an MII interface. */
-#define USE_RMII_INTERFACE 0
-
-/* The buffer addresses written into the descriptors must be aligned so the
-last few bits are zero.  These bits have special meaning for the EMAC
-peripheral and cannot be used as part of the address. */
-#define emacADDRESS_MASK			( ( unsigned portLONG ) 0xFFFFFFFC )
-
-/* Bit used within the address stored in the descriptor to mark the last
-descriptor in the array. */
-#define emacRX_WRAP_BIT				( ( unsigned portLONG ) 0x02 )
-
-/* Bit used within the Tx descriptor status to indicate whether the
-descriptor is under the control of the EMAC or the software. */
-#define emacTX_BUF_USED				( ( unsigned portLONG ) 0x80000000 )
-
-/* A short delay is used to wait for a buffer to become available, should
-one not be immediately available when trying to transmit a frame. */
-#define emacBUFFER_WAIT_DELAY		( 2 )
-#define emacMAX_WAIT_CYCLES			( configTICK_RATE_HZ / 40 )
-
-/* Misc defines. */
-#define emacINTERRUPT_LEVEL			( 5 )
-#define emacNO_DELAY				( 0 )
-#define emacTOTAL_FRAME_HEADER_SIZE	( 54 )
-#define emacPHY_INIT_DELAY			( 5000 / portTICK_RATE_MS )
-#define emacRESET_KEY				( ( unsigned portLONG ) 0xA5000000 )
-#define emacRESET_LENGTH			( ( unsigned portLONG ) ( 0x01 << 8 ) )
-
-/* The Atmel header file only defines the TX frame length mask. */
-#define emacRX_LENGTH_FRAME			( 0xfff )
-
-/*-----------------------------------------------------------*/
-
-/*
- * Prototype for the EMAC interrupt asm wrapper.
- */
-extern void vEMACISREntry( void );
-
-/*
- * Prototype for the EMAC interrupt function - called by the asm wrapper.
- */
-__arm void vEMACISR( void );
-
-/*
- * Initialise both the Tx and Rx descriptors used by the EMAC.
- */
-static void prvSetupDescriptors(void);
-
-/*
- * Write our MAC address into the EMAC.  The MAC address is set as one of the
- * uip options.
- */
-static void prvSetupMACAddress( void );
-
-/*
- * Configure the EMAC and AIC for EMAC interrupts.
- */
-static void prvSetupEMACInterrupt( void );
-
-/*
- * Some initialisation functions taken from the Atmel EMAC sample code.
- */
-static void vReadPHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG *pulValue );
-#if USE_RMII_INTERFACE != 1
-	static void vWritePHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG ulValue);
-#endif
-static portBASE_TYPE xGetLinkSpeed( void );
-static portBASE_TYPE prvProbePHY( void );
-
-/*-----------------------------------------------------------*/
-
-/* Buffer written to by the EMAC DMA.  Must be aligned as described by the
-comment above the emacADDRESS_MASK definition. */
-#pragma data_alignment=8
-static volatile portCHAR pcRxBuffer[ NB_RX_BUFFERS * ETH_RX_BUFFER_SIZE ];
-
-/* Buffer read by the EMAC DMA.  Must be aligned as described by he comment
-above the emacADDRESS_MASK definition. */
-#pragma data_alignment=8
-static portCHAR pcTxBuffer[ NB_TX_BUFFERS * ETH_TX_BUFFER_SIZE ];
-
-/* Descriptors used to communicate between the program and the EMAC peripheral.
-These descriptors hold the locations and state of the Rx and Tx buffers. */
-static volatile AT91S_TxTdDescriptor xTxDescriptors[ NB_TX_BUFFERS ];
-static volatile AT91S_RxTdDescriptor xRxDescriptors[ NB_RX_BUFFERS ];
-
-/* The IP and Ethernet addresses are read from the uIP setup. */
-const portCHAR cMACAddress[ 6 ] = { UIP_ETHADDR0, UIP_ETHADDR1, UIP_ETHADDR2, UIP_ETHADDR3, UIP_ETHADDR4, UIP_ETHADDR5 };
-const unsigned char ucIPAddress[ 4 ]  = { UIP_IPADDR0, UIP_IPADDR1, UIP_IPADDR2, UIP_IPADDR3 };
-
-/* The semaphore used by the EMAC ISR to wake the EMAC task. */
-static xSemaphoreHandle xSemaphore = NULL;
-
-/*-----------------------------------------------------------*/
-
-xSemaphoreHandle xEMACInit( void )
-{
-	/* Code supplied by Atmel (modified) --------------------*/
-
-	/* disable pull up on RXDV => PHY normal mode (not in test mode),
-	PHY has internal pull down. */
-	AT91C_BASE_PIOB->PIO_PPUDR = 1 << 15;
-
-	#if USE_RMII_INTERFACE != 1
-	  	/* PHY has internal pull down : set MII mode. */
-	  	AT91C_BASE_PIOB->PIO_PPUDR= 1 << 16;
-	#endif
-
-	/* clear PB18 <=> PHY powerdown. */
-	AT91F_PIO_CfgOutput( AT91C_BASE_PIOB, 1 << 18 ) ;
-	AT91F_PIO_ClearOutput( AT91C_BASE_PIOB,  1 << 18) ;
-
-	/* After PHY power up, hardware reset. */
-	AT91C_BASE_RSTC->RSTC_RMR = emacRESET_KEY | emacRESET_LENGTH;
-	AT91C_BASE_RSTC->RSTC_RCR = emacRESET_KEY | AT91C_RSTC_EXTRST;
-	
-	/* Wait for hardware reset end. */
-	while( !( AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL ) )
-	{
-		__asm( "NOP" );
-	}
-	__asm( "NOP" );
-  	
-	/* EMAC IO init for EMAC-PHY com. Remove EF100 config. */
-	AT91F_EMAC_CfgPIO();
-
-	/* Enable com between EMAC PHY.
-
-	Enable management port. */
-	AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;	
-
-	/* MDC = MCK/32. */
-	AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;	
-
-	/* Wait for PHY auto init end (rather crude delay!). */
-	vTaskDelay( emacPHY_INIT_DELAY );
-
-	/* PHY configuration. */
-	#if USE_RMII_INTERFACE != 1
-	{
-		unsigned portLONG ulControl;
-
-		/* PHY has internal pull down : disable MII isolate. */
-		vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
-		vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
-		ulControl &= ~BMCR_ISOLATE;
-		vWritePHY( AT91C_PHY_ADDR, MII_BMCR, ulControl );
-	}
-	#endif
-
-	/* Disable management port again. */
-	AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
-
-	#if USE_RMII_INTERFACE != 1
-		/* Enable EMAC in MII mode, enable clock ERXCK and ETXCK. */
-		AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN ;
-	#else
-		/* Enable EMAC in RMII mode, enable RMII clock (50MHz from oscillator
-		on ERFCK). */
-		AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_RMII | AT91C_EMAC_CLKEN ;
-	#endif
-
-	/* End of code supplied by Atmel ------------------------*/
-
-	/* Setup the buffers and descriptors. */
-	prvSetupDescriptors();
-	
-	/* Load our MAC address into the EMAC. */
-	prvSetupMACAddress();
-
-	/* Try to connect. */
-	if( prvProbePHY() )
-	{
-		/* Enable the interrupt! */
-		prvSetupEMACInterrupt();
-	}
-
-	return xSemaphore;
-}
-/*-----------------------------------------------------------*/
-
-portLONG lEMACSend( void )
-{
-static unsigned portBASE_TYPE uxTxBufferIndex = 0;
-portBASE_TYPE xWaitCycles = 0;
-portLONG lReturn = pdPASS;
-portCHAR *pcBuffer;
-
-	/* Is a buffer available? */
-	while( !( xTxDescriptors[ uxTxBufferIndex ].U_Status.status & AT91C_TRANSMIT_OK ) )
-	{
-		/* There is no room to write the Tx data to the Tx buffer.  Wait a
-		short while, then try again. */
-		xWaitCycles++;
-		if( xWaitCycles > emacMAX_WAIT_CYCLES )
-		{
-			/* Give up. */
-			lReturn = pdFAIL;
-			break;
-		}
-		else
-		{
-			vTaskDelay( emacBUFFER_WAIT_DELAY );
-		}
-	}
-
-	/* lReturn will only be pdPASS if a buffer is available. */
-	if( lReturn == pdPASS )
-	{
-		/* Copy the headers into the Tx buffer.  These will be in the uIP buffer. */
-		pcBuffer = ( portCHAR * ) xTxDescriptors[ uxTxBufferIndex ].addr;
-		memcpy( ( void * ) pcBuffer, ( void * ) uip_buf, emacTOTAL_FRAME_HEADER_SIZE );
-
-		/* If there is room, also copy in the application data if any. */
-		if( ( uip_len > emacTOTAL_FRAME_HEADER_SIZE ) && ( uip_len <= ( ETH_TX_BUFFER_SIZE - emacTOTAL_FRAME_HEADER_SIZE ) ) )
-		{
-			memcpy( ( void * ) &( pcBuffer[ emacTOTAL_FRAME_HEADER_SIZE ] ), ( void * ) uip_appdata, ( uip_len - emacTOTAL_FRAME_HEADER_SIZE ) );
-		}
-
-		/* Send. */	
-		portENTER_CRITICAL();
-		{
-			if( uxTxBufferIndex >= ( NB_TX_BUFFERS - 1 ) )
-			{
-				/* Fill out the necessary in the descriptor to get the data sent. */
-				xTxDescriptors[ uxTxBufferIndex ].U_Status.status = 	( uip_len & ( unsigned portLONG ) AT91C_LENGTH_FRAME )
-																		| AT91C_LAST_BUFFER
-																		| AT91C_TRANSMIT_WRAP;
-				uxTxBufferIndex = 0;
-			}
-			else
-			{
-				/* Fill out the necessary in the descriptor to get the data sent. */
-				xTxDescriptors[ uxTxBufferIndex ].U_Status.status = 	( uip_len & ( unsigned portLONG ) AT91C_LENGTH_FRAME )
-																		| AT91C_LAST_BUFFER;
-				uxTxBufferIndex++;
-			}
-	
-			AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART;
-		}
-		portEXIT_CRITICAL();
-	}
-
-	return lReturn;
-}
-/*-----------------------------------------------------------*/
-
-unsigned portLONG ulEMACPoll( void )
-{
-static unsigned portBASE_TYPE ulNextRxBuffer = 0;
-unsigned portLONG ulSectionLength = 0, ulLengthSoFar = 0, ulEOF = pdFALSE;
-portCHAR *pcSource;
-
-	/* Skip any fragments. */
-	while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !( xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_SOF ) )
-	{
-		/* Mark the buffer as free again. */
-		xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );		
-		ulNextRxBuffer++;
-		if( ulNextRxBuffer >= NB_RX_BUFFERS )
-		{
-			ulNextRxBuffer = 0;
-		}
-	}
-
-	/* Is there a packet ready? */
-
-	while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !ulSectionLength )
-	{
-		pcSource = ( portCHAR * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );
-		ulSectionLength = xRxDescriptors[ ulNextRxBuffer ].U_Status.status & emacRX_LENGTH_FRAME;
-
-		if( ulSectionLength == 0 )
-		{
-			/* The frame is longer than the buffer pointed to by this
-			descriptor so copy the entire buffer to uIP - then move onto
-			the next descriptor to get the rest of the frame. */
-			if( ( ulLengthSoFar + ETH_RX_BUFFER_SIZE ) <= UIP_BUFSIZE )
-			{
-				memcpy( &( uip_buf[ ulLengthSoFar ] ), pcSource, ETH_RX_BUFFER_SIZE );
-				ulLengthSoFar += ETH_RX_BUFFER_SIZE;
-			}			
-		}
-		else
-		{
-			/* This is the last section of the frame.  Copy the section to
-			uIP. */
-			if( ulSectionLength < UIP_BUFSIZE )
-			{
-				/* The section length holds the length of the entire frame.
-				ulLengthSoFar holds the length of the frame sections already
-				copied to uIP, so the length of the final section is
-				ulSectionLength - ulLengthSoFar; */
-				if( ulSectionLength > ulLengthSoFar )
-				{
-					memcpy( &( uip_buf[ ulLengthSoFar ] ), pcSource, ( ulSectionLength - ulLengthSoFar ) );
-				}
-			}			
-
-			/* Is this the last buffer for the frame?  If not why? */
-			ulEOF = xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_EOF;
-		}
-
-		/* Mark the buffer as free again. */
-		xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
-
-		/* Increment to the next buffer, wrapping if necessary. */
-		ulNextRxBuffer++;
-		if( ulNextRxBuffer >= NB_RX_BUFFERS )
-		{
-			ulNextRxBuffer = 0;
-		}
-	}
-
-	/* If we obtained data but for some reason did not find the end of the
-	frame then discard the data as it must contain an error. */
-	if( !ulEOF )
-	{
-		ulSectionLength = 0;
-	}
-
-	return ulSectionLength;
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetupDescriptors(void)
-{
-unsigned portBASE_TYPE xIndex;
-unsigned portLONG ulAddress;
-
-	/* Initialise xRxDescriptors descriptor. */
-	for( xIndex = 0; xIndex < NB_RX_BUFFERS; ++xIndex )
-	{
-		/* Calculate the address of the nth buffer within the array. */
-		ulAddress = ( unsigned portLONG )( pcRxBuffer + ( xIndex * ETH_RX_BUFFER_SIZE ) );
-
-		/* Write the buffer address into the descriptor.  The DMA will place
-		the data at this address when this descriptor is being used.  Mask off
-		the bottom bits of the address as these have special meaning. */
-		xRxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
-	}	
-
-	/* The last buffer has the wrap bit set so the EMAC knows to wrap back
-	to the first buffer. */
-	xRxDescriptors[ NB_RX_BUFFERS - 1 ].addr |= emacRX_WRAP_BIT;
-
-	/* Initialise xTxDescriptors. */
-	for( xIndex = 0; xIndex < NB_TX_BUFFERS; ++xIndex )
-	{
-		/* Calculate the address of the nth buffer within the array. */
-		ulAddress = ( unsigned portLONG )( pcTxBuffer + ( xIndex * ETH_TX_BUFFER_SIZE ) );
-
-		/* Write the buffer address into the descriptor.  The DMA will read
-		data from here when the descriptor is being used. */
-		xTxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
-		xTxDescriptors[ xIndex ].U_Status.status = AT91C_TRANSMIT_OK;
-	}	
-
-	/* The last buffer has the wrap bit set so the EMAC knows to wrap back
-	to the first buffer. */
-	xTxDescriptors[ NB_TX_BUFFERS - 1 ].U_Status.status = AT91C_TRANSMIT_WRAP | AT91C_TRANSMIT_OK;
-
-	/* Tell the EMAC where to find the descriptors. */
-	AT91C_BASE_EMAC->EMAC_RBQP = ( unsigned portLONG ) xRxDescriptors;
-	AT91C_BASE_EMAC->EMAC_TBQP = ( unsigned portLONG ) xTxDescriptors;
-	
-	/* Clear all the bits in the receive status register. */
-	AT91C_BASE_EMAC->EMAC_RSR = ( AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA );
-
-	/* Enable the copy of data into the buffers, ignore broadcasts,
-	and don't copy FCS. */
-	AT91C_BASE_EMAC->EMAC_NCFGR |= ( AT91C_EMAC_CAF | AT91C_EMAC_NBC | AT91C_EMAC_DRFCS);
-
-	/* Enable Rx and Tx, plus the stats register. */
-	AT91C_BASE_EMAC->EMAC_NCR |= ( AT91C_EMAC_TE | AT91C_EMAC_RE | AT91C_EMAC_WESTAT );
-}	
-/*-----------------------------------------------------------*/
-
-static void prvSetupMACAddress( void )
-{
-	/* Must be written SA1L then SA1H. */
-	AT91C_BASE_EMAC->EMAC_SA1L =	( ( unsigned portLONG ) cMACAddress[ 3 ] << 24 ) |
-									( ( unsigned portLONG ) cMACAddress[ 2 ] << 16 ) |
-									( ( unsigned portLONG ) cMACAddress[ 1 ] << 8  ) |
-									cMACAddress[ 0 ];
-
-	AT91C_BASE_EMAC->EMAC_SA1H =	( ( unsigned portLONG ) cMACAddress[ 5 ] << 8 ) |
-									cMACAddress[ 4 ];
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetupEMACInterrupt( void )
-{
-	/* Create the semaphore used to trigger the EMAC task. */
-	vSemaphoreCreateBinary( xSemaphore );
-	if( xSemaphore )
-	{
-		/* We start by 'taking' the semaphore so the ISR can 'give' it when the
-		first interrupt occurs. */
-		xSemaphoreTake( xSemaphore, emacNO_DELAY );
-		portENTER_CRITICAL();
-		{
-			/* We want to interrupt on Rx events. */
-			AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP;
-
-			/* Enable the interrupts in the AIC. */
-			AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_EMAC, emacINTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, ( void (*)( void ) ) vEMACISREntry );
-			AT91F_AIC_EnableIt( AT91C_BASE_AIC, AT91C_ID_EMAC );
-		}
-		portEXIT_CRITICAL();
-	}
-}
-/*-----------------------------------------------------------*/
-
-__arm void vEMACISR( void )
-{
-volatile unsigned portLONG ulIntStatus, ulRxStatus;
-portBASE_TYPE xSwitchRequired = pdFALSE;
-
-	ulIntStatus = AT91C_BASE_EMAC->EMAC_ISR;
-	ulRxStatus = AT91C_BASE_EMAC->EMAC_RSR;
-
-	if( ( ulIntStatus & AT91C_EMAC_RCOMP ) || ( ulRxStatus & AT91C_EMAC_REC ) )
-	{
-		/* A frame has been received, signal the uIP task so it can process
-		the Rx descriptors. */
-		xSwitchRequired = xSemaphoreGiveFromISR( xSemaphore, pdFALSE );
-		AT91C_BASE_EMAC->EMAC_RSR = AT91C_EMAC_REC;
-	}
-
-	/* If a task was woken by either a character being received or a character
-	being transmitted then we may need to switch to another task. */
-	portEND_SWITCHING_ISR( xSwitchRequired );
-
-	/* Clear the interrupt. */
-	AT91C_BASE_AIC->AIC_EOICR = 0;
-}
-/*-----------------------------------------------------------*/
-
-
-
-/*
- * The following functions are initialisation functions taken from the Atmel
- * EMAC sample code.
- */
-
-static portBASE_TYPE prvProbePHY( void )
-{
-unsigned portLONG ulPHYId1, ulPHYId2, ulStatus;
-portBASE_TYPE xReturn = pdPASS;
-	
-	/* Code supplied by Atmel (reformatted) -----------------*/
-
-	/* Enable management port */
-	AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;	
-	AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;
-
-	/* Read the PHY ID. */
-	vReadPHY( AT91C_PHY_ADDR, MII_PHYSID1, &ulPHYId1 );
-	vReadPHY( AT91C_PHY_ADDR, MII_PHYSID2, &ulPHYId2 );
-
-	/* AMD AM79C875:
-			PHY_ID1 = 0x0022
-			PHY_ID2 = 0x5541
-			Bits 3:0 Revision Number Four bit manufacturer’s revision number.
-				0001 stands for Rev. A, etc.
-	*/
-	if( ( ( ulPHYId1 << 16 ) | ( ulPHYId2 & 0xfff0 ) ) != MII_DM9161_ID )
-	{
-		/* Did not expect this ID. */
-		xReturn = pdFAIL;
-	}
-	else
-	{
-		ulStatus = xGetLinkSpeed();
-
-		if( ulStatus != pdPASS )
-		{
-			xReturn = pdFAIL;
-		}
-	}
-
-	/* Disable management port */
-	AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;	
-
-	/* End of code supplied by Atmel ------------------------*/
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-static void vReadPHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG *pulValue )
-{
-	/* Code supplied by Atmel (reformatted) ----------------------*/
-
-	AT91C_BASE_EMAC->EMAC_MAN = 	(AT91C_EMAC_SOF & (0x01<<30))
-									| (2 << 16) | (2 << 28)
-									| ((ucPHYAddress & 0x1f) << 23)
-									| (ucAddress << 18);
-
-	/* Wait until IDLE bit in Network Status register is cleared. */
-	while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
-	{
-		__asm( "NOP" );
-	}
-
-	*pulValue = ( AT91C_BASE_EMAC->EMAC_MAN & 0x0000ffff );	
-
-	/* End of code supplied by Atmel ------------------------*/
-}
-/*-----------------------------------------------------------*/
-
-#if USE_RMII_INTERFACE != 1
-static void vWritePHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG ulValue )
-{
-	/* Code supplied by Atmel (reformatted) ----------------------*/
-
-	AT91C_BASE_EMAC->EMAC_MAN = (( AT91C_EMAC_SOF & (0x01<<30))
-								| (2 << 16) | (1 << 28)
-								| ((ucPHYAddress & 0x1f) << 23)
-								| (ucAddress << 18))
-								| (ulValue & 0xffff);
-
-	/* Wait until IDLE bit in Network Status register is cleared */
-	while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
-	{
-		__asm( "NOP" );
-	};
-
-	/* End of code supplied by Atmel ------------------------*/
-}
-#endif
-/*-----------------------------------------------------------*/
-
-static portBASE_TYPE xGetLinkSpeed( void )
-{
-	unsigned portLONG ulBMSR, ulBMCR, ulLPA, ulMACCfg, ulSpeed, ulDuplex;
-
-	/* Code supplied by Atmel (reformatted) -----------------*/
-
-	/* Link status is latched, so read twice to get current value */
-	vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
-	vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
-
-	if( !( ulBMSR & BMSR_LSTATUS ) )
-	{	
-		/* No Link. */
-		return pdFAIL;
-	}
-
-	vReadPHY(AT91C_PHY_ADDR, MII_BMCR, &ulBMCR);
-	if (ulBMCR & BMCR_ANENABLE)
-	{				
-		/* AutoNegotiation is enabled. */
-		if (!(ulBMSR & BMSR_ANEGCOMPLETE))
-		{
-			/* Auto-negotiation in progress. */
-			return pdFAIL;				
-		}		
-
-		vReadPHY(AT91C_PHY_ADDR, MII_LPA, &ulLPA);
-		if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_100HALF ) )
-		{
-			ulSpeed = SPEED_100;
-		}
-		else
-		{
-			ulSpeed = SPEED_10;
-		}
-
-		if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_10FULL ) )
-		{
-			ulDuplex = DUPLEX_FULL;
-		}
-		else
-		{
-			ulDuplex = DUPLEX_HALF;
-		}
-	}
-	else
-	{
-		ulSpeed = ( ulBMCR & BMCR_SPEED100 ) ? SPEED_100 : SPEED_10;
-		ulDuplex = ( ulBMCR & BMCR_FULLDPLX ) ? DUPLEX_FULL : DUPLEX_HALF;
-	}
-
-	/* Update the MAC */
-	ulMACCfg = AT91C_BASE_EMAC->EMAC_NCFGR & ~( AT91C_EMAC_SPD | AT91C_EMAC_FD );
-	if( ulSpeed == SPEED_100 )
-	{
-		if( ulDuplex == DUPLEX_FULL )
-		{
-			/* 100 Full Duplex */
-			AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD | AT91C_EMAC_FD;
-		}
-		else
-		{					
-			/* 100 Half Duplex */
-			AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD;
-		}
-	}
-	else
-	{
-		if (ulDuplex == DUPLEX_FULL)
-		{
-			/* 10 Full Duplex */
-			AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_FD;
-		}
-		else
-		{
-			/* 10 Half Duplex */
-			AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg;
-		}
-	}
-
-	/* End of code supplied by Atmel ------------------------*/
-
-	return pdPASS;
-}
diff --git a/Demo/uIP_Demo_IAR_ARM7/EMAC/SAM7_EMAC.h b/Demo/uIP_Demo_IAR_ARM7/EMAC/SAM7_EMAC.h
deleted file mode 100644
index 36d6a05bc..000000000
--- a/Demo/uIP_Demo_IAR_ARM7/EMAC/SAM7_EMAC.h
+++ /dev/null
@@ -1,24 +0,0 @@
-#ifndef SAM_7_EMAC_H
-#define SAM_7_EMAC_H
-
-
-/*
- * Initialise the EMAC driver.  If successful a semaphore is returned that
- * is used by the EMAC ISR to indicate that Rx packets have been received.
- * If the initialisation fails then NULL is returned.
- */
-xSemaphoreHandle xEMACInit( void );
-
-/*
- * Send the current uIP buffer.  This copies the uIP buffer to one of the
- * EMAC Tx buffers, then indicates to the EMAC that the buffer is ready.
- */
-portLONG lEMACSend( void );
-
-/*
- * Called in response to an EMAC Rx interrupt.  Copies the received frame
- * into the uIP buffer.
- */
-unsigned portLONG ulEMACPoll( void );
-
-#endif
diff --git a/Demo/uIP_Demo_IAR_ARM7/Flash_Debug/Obj/rtosdemo.pbd b/Demo/uIP_Demo_IAR_ARM7/Flash_Debug/Obj/rtosdemo.pbd
deleted file mode 100644
index 23f684657..000000000
--- a/Demo/uIP_Demo_IAR_ARM7/Flash_Debug/Obj/rtosdemo.pbd
+++ /dev/null
@@ -1,26 +0,0 @@
-This is an internal working file generated by the Source Browser.
-09:28 06s
-C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\BlockQ.pbi
-C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\Cstartup_SAM7.pbi
-C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\ParTest.pbi
-C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\PollQ.pbi
-C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\SAM7_EMAC.pbi
-C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\cgi.pbi
-C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\death.pbi
-C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\dynamic.pbi
-C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\flash.pbi
-C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\flop.pbi
-C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\fs.pbi
-C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\heap_2.pbi
-C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\httpd.pbi
-C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\integer.pbi
-C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\list.pbi
-C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\main.pbi
-C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\port.pbi
-C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\queue.pbi
-C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\semtest.pbi
-C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\tasks.pbi
-C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\uIP_Task.pbi
-C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\uip.pbi
-C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\uip_arch.pbi
-C:\E\Dev\FreeRTOS\Releases\Code\V4.0.0\Demo\uIP_Demo_IAR_ARM7\Flash_Debug\Obj\uip_arp.pbi
diff --git a/Demo/uIP_Demo_IAR_ARM7/FreeRTOSConfig.h b/Demo/uIP_Demo_IAR_ARM7/FreeRTOSConfig.h
deleted file mode 100644
index 524207720..000000000
--- a/Demo/uIP_Demo_IAR_ARM7/FreeRTOSConfig.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
-	FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
-
-	This file is part of the FreeRTOS.org distribution.
-
-	FreeRTOS.org is free software; you can redistribute it and/or modify
-	it under the terms of the GNU General Public License as published by
-	the Free Software Foundation; either version 2 of the License, or
-	(at your option) any later version.
-
-	FreeRTOS.org is distributed in the hope that it will be useful,
-	but WITHOUT ANY WARRANTY; without even the implied warranty of
-	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-	GNU General Public License for more details.
-
-	You should have received a copy of the GNU General Public License
-	along with FreeRTOS.org; if not, write to the Free Software
-	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-
-	A special exception to the GPL can be applied should you wish to distribute
-	a combined work that includes FreeRTOS.org, without being obliged to provide
-	the source code for any proprietary components.  See the licensing section
-	of http://www.FreeRTOS.org for full details of how and when the exception
-	can be applied.
-
-	***************************************************************************
-	See http://www.FreeRTOS.org for documentation, latest information, license
-	and contact details.  Please ensure to read the configuration and relevant
-	port sections of the online documentation.
-	***************************************************************************
-*/
-
-#ifndef FREERTOS_CONFIG_H
-#define FREERTOS_CONFIG_H
-
-#include 
-#include "Board.h"
-
-/*-----------------------------------------------------------
- * Application specific definitions.
- *
- * These definitions should be adjusted for your particular hardware and
- * application requirements.
- *
- * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
- * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
- *----------------------------------------------------------*/
-
-#define configUSE_PREEMPTION		1
-#define configUSE_IDLE_HOOK			0
-#define configUSE_TICK_HOOK			0
-#define configCPU_CLOCK_HZ			( ( unsigned portLONG ) 47923200 )
-#define configTICK_RATE_HZ			( ( portTickType ) 1000 )
-#define configMAX_PRIORITIES		( ( unsigned portBASE_TYPE ) 5 )
-#define configMINIMAL_STACK_SIZE	( ( unsigned portSHORT ) 100 )
-#define configTOTAL_HEAP_SIZE		( ( size_t ) 22000 )
-#define configMAX_TASK_NAME_LEN		( 16 )
-#define configUSE_TRACE_FACILITY	1
-#define configUSE_16_BIT_TICKS		0
-#define configIDLE_SHOULD_YIELD		0
-
-/* Co-routine definitions. */
-#define configUSE_CO_ROUTINES 		0
-#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
-
-/* Set the following definitions to 1 to include the API function, or zero
-to exclude the API function. */
-
-#define INCLUDE_vTaskPrioritySet		1
-#define INCLUDE_uxTaskPriorityGet		1
-#define INCLUDE_vTaskDelete				1
-#define INCLUDE_vTaskCleanUpResources	0
-#define INCLUDE_vTaskSuspend			1
-#define INCLUDE_vTaskDelayUntil			1
-#define INCLUDE_vTaskDelay				1
-
-
-#endif /* FREERTOS_CONFIG_H */
diff --git a/Demo/uIP_Demo_IAR_ARM7/ParTest/ParTest.c b/Demo/uIP_Demo_IAR_ARM7/ParTest/ParTest.c
deleted file mode 100644
index 56884c91f..000000000
--- a/Demo/uIP_Demo_IAR_ARM7/ParTest/ParTest.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
-	FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
-
-	This file is part of the FreeRTOS.org distribution.
-
-	FreeRTOS.org is free software; you can redistribute it and/or modify
-	it under the terms of the GNU General Public License as published by
-	the Free Software Foundation; either version 2 of the License, or
-	(at your option) any later version.
-
-	FreeRTOS.org is distributed in the hope that it will be useful,
-	but WITHOUT ANY WARRANTY; without even the implied warranty of
-	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-	GNU General Public License for more details.
-
-	You should have received a copy of the GNU General Public License
-	along with FreeRTOS.org; if not, write to the Free Software
-	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-
-	A special exception to the GPL can be applied should you wish to distribute
-	a combined work that includes FreeRTOS.org, without being obliged to provide
-	the source code for any proprietary components.  See the licensing section
-	of http://www.FreeRTOS.org for full details of how and when the exception
-	can be applied.
-
-	***************************************************************************
-	See http://www.FreeRTOS.org for documentation, latest information, license
-	and contact details.  Please ensure to read the configuration and relevant
-	port sections of the online documentation.
-	***************************************************************************
-*/
-
-#include "FreeRTOS.h"
-#include "partest.h"
-#include "board.h"
-
-/*-----------------------------------------------------------
- * Simple parallel port IO routines for the LED's.  LED's can be set, cleared
- * or toggled.
- *-----------------------------------------------------------*/
-const unsigned portLONG ulLED_MASK[ NB_LED ]= { LED1, LED2, LED3, LED4 };
-
-void vParTestInitialise( void )
-{	
-	/* Start with all LED's off. */
-	AT91F_PIO_SetOutput( AT91C_BASE_PIOB, LED_MASK );	
-}
-/*-----------------------------------------------------------*/
-
-void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
-{
-	if( uxLED < ( portBASE_TYPE ) NB_LED )
-	{
-		if( xValue )
-		{
-			AT91F_PIO_SetOutput( AT91C_BASE_PIOB, ulLED_MASK[ uxLED ] );
-		}
-		else
-		{
-			AT91F_PIO_ClearOutput( AT91C_BASE_PIOB, ulLED_MASK[ uxLED ]);
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
-{
-	if( uxLED < ( portBASE_TYPE ) NB_LED )
-	{
-		if( AT91F_PIO_GetInput( AT91C_BASE_PIOB ) & ulLED_MASK[ uxLED ] )
-		{
-			AT91F_PIO_ClearOutput( AT91C_BASE_PIOB, ulLED_MASK[ uxLED ]);
-		}
-		else
-		{
-			AT91F_PIO_SetOutput( AT91C_BASE_PIOB, ulLED_MASK[ uxLED ] );					
-		}
-	}
-}
-
-
diff --git a/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Board.h b/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Board.h
deleted file mode 100644
index 0313bfdc6..000000000
--- a/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Board.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*----------------------------------------------------------------------------
-*         ATMEL Microcontroller Software Support  -  ROUSSET  -
-*----------------------------------------------------------------------------
-* The software is delivered "AS IS" without warranty or condition of any
-* kind, either express, implied or statutory. This includes without
-* limitation any warranty or condition with respect to merchantability or
-* fitness for any particular purpose, or against the infringements of
-* intellectual property rights of others.
-*----------------------------------------------------------------------------
-* File Name           : Board.h
-* Object              : AT91SAM7X Evaluation Board Features Definition File.
-*
-* Creation            : JG   20/Jun/2005
-*----------------------------------------------------------------------------
-*/
-#ifndef Board_h
-#define Board_h
-
-#include 
-#define __inline inline
-#include 
-
-#define true	-1
-#define false	0
-
-/*-------------------------------*/
-/* SAM7Board Memories Definition */
-/*-------------------------------*/
-// The AT91SAM7X128 embeds a 32-Kbyte SRAM bank, and 128K-Byte Flash
-
-#define  FLASH_PAGE_NB		256
-#define  FLASH_PAGE_SIZE	128
-
-/*-----------------*/
-/* Leds Definition */
-/*-----------------*/
-#define LED1            (1<<19)	// PB19
-#define LED2            (1<<20)	// PB20
-#define LED3            (1<<21)	// PB21
-#define LED4            (1<<22)	// PB22
-#define NB_LED			4
-
-#define LED_MASK        (LED1|LED2|LED3|LED4)
-
-/*-------------------------*/
-/* Push Buttons Definition */
-/*-------------------------*/
-
-#define SW1_MASK        (1<<21)	// PA21
-#define SW2_MASK        (1<<22)	// PA22
-#define SW3_MASK        (1<<23)	// PA23
-#define SW4_MASK        (1<<24)	// PA24
-#define SW_MASK         (SW1_MASK|SW2_MASK|SW3_MASK|SW4_MASK)
-
-
-#define SW1 	(1<<21)	// PA21
-#define SW2 	(1<<22)	// PA22
-#define SW3 	(1<<23)	// PA23
-#define SW4 	(1<<24)	// PA24
-
-/*--------------*/
-/* Master Clock */
-/*--------------*/
-
-#define EXT_OC          18432000   // Exetrnal ocilator MAINCK
-#define MCK             47923200   // MCK (PLLRC div by 2)
-#define MCKKHz          (MCK/1000) //
-
-#endif /* Board_h */
diff --git a/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Cstartup.s79 b/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Cstartup.s79
deleted file mode 100644
index b875618fc..000000000
--- a/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Cstartup.s79
+++ /dev/null
@@ -1,223 +0,0 @@
-;------------------------------------------------------------------------------
-;-         ATMEL Microcontroller Software Support  -  ROUSSET  -
-;------------------------------------------------------------------------------
-; The software is delivered "AS IS" without warranty or condition of any
-; kind, either express, implied or statutory. This includes without
-; limitation any warranty or condition with respect to merchantability or
-; fitness for any particular purpose, or against the infringements of
-; intellectual property rights of others.
-;-----------------------------------------------------------------------------
-;- File source          : Cstartup.s79
-;- Object               : Generic CStartup for IAR No Use REMAP
-;- Compilation flag     : None
-;-
-;- 1.0 15/Jun/04 JPP    : Creation
-;------------------------------------------------------------------------------
-
-#include "AT91SAM7X256_inc.h"
-
-;------------------------------------------------------------------------------
-;- Area Definition
-;------------------------------------------------------------------------------
-
-;---------------------------------------------------------------
-; ?RESET
-; Reset Vector.
-; Normally, segment INTVEC is linked at address 0.
-; For debugging purposes, INTVEC may be placed at other
-; addresses.
-; A debugger that honors the entry point will start the
-; program in a normal way even if INTVEC is not at address 0.
-;-------------------------------------------------------------
-
-		PROGRAM	?RESET
-		RSEG	INTRAMSTART_REMAP
-		RSEG	INTRAMEND_REMAP
-
-		EXTERN	vPortYieldProcessor
-
-		RSEG	ICODE:CODE:ROOT(2)
-		CODE32	; Always ARM mode after reset	
-		org	0	
-reset		
-;------------------------------------------------------------------------------
-;- Exception vectors
-;--------------------
-;- These vectors can be read at address 0 or at RAM address
-;- They ABSOLUTELY requires to be in relative addresssing mode in order to
-;- guarantee a valid jump. For the moment, all are just looping.
-;- If an exception occurs before remap, this would result in an infinite loop.
-;- To ensure if a exeption occurs before start application to infinite loop.
-;------------------------------------------------------------------------------
-
-                B           InitReset           ; 0x00 Reset handler
-undefvec:
-                B           undefvec            ; 0x04 Undefined Instruction
-swivec:
-                B           vPortYieldProcessor ; 0x08 Software Interrupt
-pabtvec:
-                B           pabtvec             ; 0x0C Prefetch Abort
-dabtvec:
-                B           dabtvec             ; 0x10 Data Abort
-rsvdvec:
-                B           rsvdvec             ; 0x14 reserved
-irqvec:
-				LDR			PC, [PC, #-0xF20]	; Jump directly to the address given by the AIC
-
-fiqvec:               							; 0x1c FIQ
-
-;------------------------------------------------------------------------------
-;- Function             : FIQ_Handler_Entry
-;- Treatments           : FIQ Controller Interrupt Handler.
-;- Called Functions     : AIC_FVR[interrupt]
-;------------------------------------------------------------------------------
-
-FIQ_Handler_Entry:
-
-;- Switch in SVC/User Mode to allow User Stack access for C code
-; because the FIQ is not yet acknowledged
-
-;- Save and r0 in FIQ_Register
-            mov         r9,r0
-		    ldr         r0 , [r8, #AIC_FVR]
-            msr         CPSR_c,#I_BIT | F_BIT | ARM_MODE_SVC
-
-;- Save scratch/used registers and LR in User Stack
-            stmfd       sp!, { r1-r3, r12, lr}
-
-;- Branch to the routine pointed by the AIC_FVR
-            mov         r14, pc
-            bx          r0
-
-;- Restore scratch/used registers and LR from User Stack
-            ldmia       sp!, { r1-r3, r12, lr}
-
-;- Leave Interrupts disabled and switch back in FIQ mode
-            msr         CPSR_c, #I_BIT | F_BIT | ARM_MODE_FIQ
-
-;- Restore the R0 ARM_MODE_SVC register
-            mov         r0,r9
-
-;- Restore the Program Counter using the LR_fiq directly in the PC
-            subs        pc,lr,#4
-
-InitReset:
-;------------------------------------------------------------------------------
-;- Low level Init (PMC, AIC, ? ....) by C function AT91F_LowLevelInit
-;------------------------------------------------------------------------------
-            	EXTERN   AT91F_LowLevelInit
-
-#define  __iramend 	SFB(INTRAMEND_REMAP)
-
-;- minumum C initialization
-;- call  AT91F_LowLevelInit( void)
-
-            ldr     r13,=__iramend            ; temporary stack in internal RAM
-;--Call Low level init function in ABSOLUTE through the Interworking
-		    ldr	    r0,=AT91F_LowLevelInit
-       	    mov     lr, pc
-		    bx	    r0
-;------------------------------------------------------------------------------
-;- Stack Sizes Definition
-;------------------------
-;- Interrupt Stack requires 2 words x 8 priority level x 4 bytes when using
-;- the vectoring. This assume that the IRQ management.
-;- The Interrupt Stack must be adjusted depending on the interrupt handlers.
-;- Fast Interrupt not requires stack If in your application it required you must
-;- be definehere.
-;- The System stack size is not defined and is limited by the free internal
-;- SRAM.
-;------------------------------------------------------------------------------
-
-;------------------------------------------------------------------------------
-;- Top of Stack Definition
-;-------------------------
-;- Interrupt and Supervisor Stack are located at the top of internal memory in
-;- order to speed the exception handling context saving and restoring.
-;- ARM_MODE_SVC (Application, C) Stack is located at the top of the external memory.
-;------------------------------------------------------------------------------
-
-IRQ_STACK_SIZE          EQU     300
-
-ARM_MODE_FIQ            EQU     0x11
-ARM_MODE_IRQ            EQU     0x12
-ARM_MODE_SVC            EQU     0x13
-
-I_BIT                   EQU     0x80
-F_BIT                   EQU     0x40
-
-;------------------------------------------------------------------------------
-;- Setup the stack for each mode
-;-------------------------------
-                ldr     r0, =__iramend
-
-;- Set up Fast Interrupt Mode and set FIQ Mode Stack
-                msr     CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT
-;- Init the FIQ register
-            	ldr     r8, =AT91C_BASE_AIC
-
-;- Set up Interrupt Mode and set IRQ Mode Stack
-                msr     CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT
-                mov     r13, r0                     ; Init stack IRQ
-                sub     r0, r0, #IRQ_STACK_SIZE
-
-;- Enable interrupt & Set up Supervisor Mode and set Supervisor Mode Stack
-                msr     CPSR_c, #ARM_MODE_SVC
-                mov     r13, r0
-
-
-;---------------------------------------------------------------
-; ?CSTARTUP
-;---------------------------------------------------------------
-		EXTERN	__segment_init
-		EXTERN	main
-; Initialize segments.
-; __segment_init is assumed to use
-; instruction set and to be reachable by BL from the ICODE segment
-; (it is safest to link them in segment ICODE).
-		ldr	r0,=__segment_init
-                mov     lr, pc
-		bx	r0
-
-		PUBLIC	__main
-?jump_to_main:
-		ldr	lr,=?call_exit
-		ldr	r0,=main
-__main:
-		bx	r0
-
-;------------------------------------------------------------------------------
-;- Loop for ever
-;---------------
-;- End of application. Normally, never occur.
-;- Could jump on Software Reset ( B 0x0 ).
-;------------------------------------------------------------------------------
-?call_exit:
-End
-            b       End
-
-
-
-;---------------------------------------------------------------
-; ?EXEPTION_VECTOR
-; This module is only linked if needed for closing files.
-;---------------------------------------------------------------
-		PUBLIC	AT91F_Default_FIQ_handler
-		PUBLIC	AT91F_Default_IRQ_handler
-		PUBLIC	AT91F_Spurious_handler
-
-		CODE32	; Always ARM mode after exeption	
-
-AT91F_Default_FIQ_handler
-            b     AT91F_Default_FIQ_handler
-
-AT91F_Default_IRQ_handler
-            b     AT91F_Default_IRQ_handler
-
-AT91F_Spurious_handler
-            b     AT91F_Spurious_handler
-
-	ENDMOD
-
-	END
-
diff --git a/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Cstartup_SAM7.c b/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Cstartup_SAM7.c
deleted file mode 100644
index a7d50f692..000000000
--- a/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Cstartup_SAM7.c
+++ /dev/null
@@ -1,94 +0,0 @@
-//*----------------------------------------------------------------------------
-//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
-//*----------------------------------------------------------------------------
-//* The software is delivered "AS IS" without warranty or condition of any
-//* kind, either express, implied or statutory. This includes without
-//* limitation any warranty or condition with respect to merchantability or
-//* fitness for any particular purpose, or against the infringements of
-//* intellectual property rights of others.
-//*----------------------------------------------------------------------------
-//* File Name           : Cstartup_SAM7.c
-//* Object              : Low level initializations written in C for IAR
-//*                       tools
-//* 1.0   08/Sep/04 JPP	: Creation
-//* 1.10  10/Sep/04 JPP : Update AT91C_CKGR_PLLCOUNT filed
-//*----------------------------------------------------------------------------
-
-
-// Include the board file description
-#include "Board.h"
-//#include "init.h"
-#include 
-
-// The following functions must be write in ARM mode this function called directly
-// by exception vector
-extern void AT91F_Spurious_handler(void);
-extern void AT91F_Default_IRQ_handler(void);
-extern void AT91F_Default_FIQ_handler(void);
-
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_LowLevelInit
-//* \brief This function performs very low level HW initialization
-//*        this function can be use a Stack, depending the compilation
-//*        optimization mode
-//*----------------------------------------------------------------------------
-void AT91F_LowLevelInit( void);
-void AT91F_LowLevelInit( void ) @ "ICODE"
-{
- int            i;
- AT91PS_PMC     pPMC = AT91C_BASE_PMC;
-
-    //* Set Flash Waite sate
-	//  Single Cycle Access at Up to 30 MHz, or 40
-	//  if MCK = 47923200 I have 50 Cycle for 1 useconde ( flied MC_FMR->FMCN
-	    AT91C_BASE_MC->MC_FMR = ((AT91C_MC_FMCN)&(75 <<16)) | AT91C_MC_FWS_1FWS ;
-
-    //* Watchdog Disable
-        AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS;
-
-		
-	// If we are running off a j-link then the PLL will have already been setup.
-	if( !( pPMC->PMC_MCKR & AT91C_PMC_CSS_PLL_CLK ) )
-	{
-		//* Set MCK at 47 923 200
-    	// 1 Enabling the Main Oscillator:
-        // SCK = 1/32768 = 30.51 uSeconde
-    	// Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms
-       	pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | AT91C_CKGR_MOSCEN ));
-        // Wait the startup time
-        while(!(pPMC->PMC_SR & AT91C_PMC_MOSCS));
-		// 2 Checking the Main Oscillator Frequency (Optional)
-		// 3 Setting PLL and divider:
-		// - div by 5 Fin = 3,6864 =(18,432 / 5)
-		// - Mul 25+1: Fout =	95,8464 =(3,6864 *26)
-		// for 96 MHz the erroe is 0.16%
-		//eld out NOT USED = 0 Fi
-       	pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 5) |
-                         (AT91C_CKGR_PLLCOUNT & (28<<8)) |
-                         (AT91C_CKGR_MUL & (25<<16)));
-
-        // Wait the startup time
-        while(!(pPMC->PMC_SR & AT91C_PMC_LOCK));
-		// 4. Selection of Master Clock and Processor Clock
-        // select the PLL clock divided by 2
-
-       	pPMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2 ;
-        while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
-
-	
-        pPMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK ;
-        while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
-	}		
-		
-	// Set up the default interrupts handler vectors
-	AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler ;
-	for (i=1;i < 31; i++)
-	{
-	    AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler ;
-	}
-	AT91C_BASE_AIC->AIC_SPU  = (int) AT91F_Spurious_handler ;
-}
-
-
-
diff --git a/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Emac.h b/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Emac.h
deleted file mode 100644
index 7551a3648..000000000
--- a/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Emac.h
+++ /dev/null
@@ -1,195 +0,0 @@
-//*----------------------------------------------------------------------------
-//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
-//*----------------------------------------------------------------------------
-//* The software is delivered "AS IS" without warranty or condition of any
-//* kind, either express, implied or statutory. This includes without
-//* limitation any warranty or condition with respect to merchantability or
-//* fitness for any particular purpose, or against the infringements of
-//* intellectual property rights of others.
-//*----------------------------------------------------------------------------
-//* File Name           : Emac.h
-//* Object              : Emac header file
-//* Creation            : Hi   11/18/2002
-//*
-//*----------------------------------------------------------------------------
-#ifndef AT91C_EMAC_H
-#define AT91C_EMAC_H
-
-
-//* Allows to display all IP header in the main.c
-//* If not defined, only ICMP packets are displayed
-#define AT91C_DISPLAY_ALL_IPHEADER		0
-
-#define NB_RX_BUFFERS			25			//* Number of receive buffers
-#define ETH_RX_BUFFER_SIZE		128         //*
-
-#define NB_TX_BUFFERS			2		//* Number of Transmit buffers
-#define ETH_TX_BUFFER_SIZE		UIP_BUFSIZE       //*
-
-#define AT91C_NO_IPPACKET		0
-#define AT91C_IPPACKET	        1
-
-#define ARP_REQUEST				0x0001
-#define ARP_REPLY				0x0002
-#define PROT_ARP				0x0806
-#define PROT_IP					0x0800
-#define PROT_ICMP				0x01
-#define ICMP_ECHO_REQUEST		0x08
-#define ICMP_ECHO_REPLY			0x00
-
-#define AT91C_EMAC_CLKEN 0x2
-#define SWAP16(x)	(((x & 0xff) << 8) | (x >> 8))
-
-#if 0
-//* Transfer descriptor structure
-typedef struct _AT91S_TdDescriptor {
-	unsigned int addr;
-	unsigned int status;
-}AT91S_TdDescriptor, *AT91PS_TdDescriptor;
-#endif
-
-//* Receive Transfer descriptor structure
-typedef struct  _AT91S_RxTdDescriptor {
-	unsigned int addr;
-	union
-	{
-		unsigned int status;
-		struct {
-			unsigned int Length:11;
-			unsigned int Res0:1;
-			unsigned int Rxbuf_off:2;
-			unsigned int StartOfFrame:1;
-			unsigned int EndOfFrame:1;
-			unsigned int Cfi:1;
-			unsigned int VlanPriority:3;
-			unsigned int PriorityTag:1;
-			unsigned int VlanTag:1;
-			unsigned int TypeID:1;
-			unsigned int Sa4Match:1;
-			unsigned int Sa3Match:1;
-			unsigned int Sa2Match:1;
-			unsigned int Sa1Match:1;
-			unsigned int Res1:1;
-			unsigned int ExternalAdd:1;
-			unsigned int UniCast:1;
-			unsigned int MultiCast:1;
-			unsigned int BroadCast:1;
-		}S_Status;		
-	}U_Status;
-}AT91S_RxTdDescriptor, *AT91PS_RxTdDescriptor;
-
-
-//* Transmit Transfer descriptor structure
-typedef struct _AT91S_TxTdDescriptor {
-	unsigned int addr;
-	union
-	{
-		unsigned int status;
-		struct {
-			unsigned int Length:11;
-			unsigned int Res0:4;
-			unsigned int LastBuff:1;
-			unsigned int NoCrc:1;
-			unsigned int Res1:10;
-			unsigned int BufExhausted:1;
-			unsigned int TransmitUnderrun:1;
-			unsigned int TransmitError:1;
-			unsigned int Wrap:1;
-			unsigned int BuffUsed:1;
-		}S_Status;		
-	}U_Status;
-}AT91S_TxTdDescriptor, *AT91PS_TxTdDescriptor;
-
-#define AT91C_OWNERSHIP_BIT		0x00000001
-
-/* Receive status defintion */
-#define AT91C_BROADCAST_ADDR	((unsigned int) (1 << 31))	//* Broadcat address detected
-#define AT91C_MULTICAST_HASH 	((unsigned int) (1 << 30))	//* MultiCast hash match
-#define AT91C_UNICAST_HASH 	    ((unsigned int) (1 << 29))	//* UniCast hash match
-#define AT91C_EXTERNAL_ADDR	    ((unsigned int) (1 << 28))	//* External Address match
-#define AT91C_SA1_ADDR	    	((unsigned int) (1 << 26))	//* Specific address 1 match
-#define AT91C_SA2_ADDR	    	((unsigned int) (1 << 25))	//* Specific address 2 match
-#define AT91C_SA3_ADDR	    	((unsigned int) (1 << 24))	//* Specific address 3 match
-#define AT91C_SA4_ADDR	    	((unsigned int) (1 << 23))	//* Specific address 4 match
-#define AT91C_TYPE_ID	    	((unsigned int) (1 << 22))	//* Type ID match
-#define AT91C_VLAN_TAG	    	((unsigned int) (1 << 21))	//* VLAN tag detected
-#define AT91C_PRIORITY_TAG    	((unsigned int) (1 << 20))	//* PRIORITY tag detected
-#define AT91C_VLAN_PRIORITY    	((unsigned int) (7 << 17))  //* PRIORITY Mask
-#define AT91C_CFI_IND        	((unsigned int) (1 << 16))  //* CFI indicator
-#define AT91C_EOF           	((unsigned int) (1 << 15))  //* EOF
-#define AT91C_SOF           	((unsigned int) (1 << 14))  //* SOF
-#define AT91C_RBF_OFFSET     	((unsigned int) (3 << 12))  //* Receive Buffer Offset Mask
-#define AT91C_LENGTH_FRAME     	((unsigned int) 0x07FF)     //* Length of frame
-
-/* Transmit Status definition */
-#define AT91C_TRANSMIT_OK		((unsigned int) (1 << 31))	//*
-#define AT91C_TRANSMIT_WRAP		((unsigned int) (1 << 30))	//* Wrap bit: mark the last descriptor
-#define AT91C_TRANSMIT_ERR		((unsigned int) (1 << 29))	//* RLE:transmit error
-#define AT91C_TRANSMIT_UND		((unsigned int) (1 << 28))	//* Transmit Underrun
-#define AT91C_BUF_EX     		((unsigned int) (1 << 27))	//* Buffers exhausted in mid frame
-#define AT91C_TRANSMIT_NO_CRC	((unsigned int) (1 << 16))	//* No CRC will be appended to the current frame
-#define AT91C_LAST_BUFFER    	((unsigned int) (1 << 15))	//*
-
-#define ARP_ETHER	 		1		/* Ethernet  hardware address	*/
-#define ARPOP_REQUEST    	1		/* Request  to resolve  address	*/
-#define ARPOP_REPLY	    	2		/* Response to previous request	*/
-#define RARPOP_REQUEST   	3		/* Request  to resolve  address	*/
-#define RARPOP_REPLY	    4		/* Response to previous request */
-
-
-typedef struct _AT91S_EthHdr
-{
-	unsigned char		et_dest[6];	/* Destination node		*/
-	unsigned char		et_src[6];	/* Source node			*/
-	unsigned short		et_protlen;	/* Protocol or length		*/
-} AT91S_EthHdr, *AT91PS_EthHdr;
-
-typedef struct _AT91S_ArpHdr
-{
-	unsigned short		ar_hrd;		/* Format of hardware address	*/
-	unsigned short		ar_pro;		/* Format of protocol address	*/
-	unsigned char		ar_hln;		/* Length of hardware address	*/
-	unsigned char		ar_pln;		/* Length of protocol address	*/
-	unsigned short		ar_op;		/* Operation			*/
-	unsigned char		ar_sha[6];	/* Sender hardware address	*/
-	unsigned char		ar_spa[4];	/* Sender protocol address	*/
-	unsigned char		ar_tha[6];	/* Target hardware address	*/
-	unsigned char		ar_tpa[4];	/* Target protocol address	*/
-} AT91S_ArpHdr, *AT91PS_ArpHdr;
-
-//* IP Header structure
-typedef struct _AT91S_IPheader {
-	unsigned char	ip_hl_v;	/* header length and version	*/
-	unsigned char	ip_tos;		/* type of service		*/
-	unsigned short	ip_len;		/* total length			*/
-	unsigned short	ip_id;		/* identification		*/
-	unsigned short	ip_off;		/* fragment offset field	*/
-	unsigned char	ip_ttl;		/* time to live			*/
-	unsigned char	ip_p;		/* protocol			*/
-	unsigned short	ip_sum;		/* checksum			*/
-	unsigned char	ip_src[4];	/* Source IP address		*/
-	unsigned char	ip_dst[4];	/* Destination IP address	*/
-	unsigned short	udp_src;	/* UDP source port		*/
-	unsigned short	udp_dst;	/* UDP destination port		*/
-	unsigned short	udp_len;	/* Length of UDP packet		*/
-	unsigned short	udp_xsum;	/* Checksum			*/
-} AT91S_IPheader, *AT91PS_IPheader;
-
-//* ICMP echo header structure
-typedef struct _AT91S_IcmpEchoHdr {
-    unsigned char   type;       /* type of message */
-    unsigned char   code;       /* type subcode */
-    unsigned short  cksum;      /* ones complement cksum of struct */
-    unsigned short  id;         /* identifier */
-    unsigned short  seq;        /* sequence number */
-}AT91S_IcmpEchoHdr, *AT91PS_IcmpEchoHdr;
-
-
-typedef struct _AT91S_EthPack
-{
-	AT91S_EthHdr	EthHdr;
-	AT91S_ArpHdr	ArpHdr;
-} AT91S_EthPack, *AT91PS_EthPack;
-
-
-#endif //* AT91C_EMAC_H
diff --git a/Demo/uIP_Demo_IAR_ARM7/SrcIAR/dbgu.c b/Demo/uIP_Demo_IAR_ARM7/SrcIAR/dbgu.c
deleted file mode 100644
index cee31b1d5..000000000
--- a/Demo/uIP_Demo_IAR_ARM7/SrcIAR/dbgu.c
+++ /dev/null
@@ -1,95 +0,0 @@
-//*----------------------------------------------------------------------------
-//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
-//*----------------------------------------------------------------------------
-//* The software is delivered "AS IS" without warranty or condition of any
-//* kind, either express, implied or statutory. This includes without
-//* limitation any warranty or condition with respect to merchantability or
-//* fitness for any particular purpose, or against the infringements of
-//* intellectual property rights of others.
-//*----------------------------------------------------------------------------
-//* File Name           : dbgu.c
-//* Object              : DBGU routines written in C
-//* Creation            : JG   16/Aug/2004
-//*----------------------------------------------------------------------------
-
-// Include Standard files
-#include "Board.h"
-
-//*--------------------------1--------------------------------------------------
-//* \fn    AT91F_DBGU_Printk
-//* \brief This function is used to send a string through the DBGU channel (Very low level debugging)
-//*----------------------------------------------------------------------------
-void AT91F_DBGU_Printk(	char *buffer)
-{
-    AT91PS_DBGU pDbgu = AT91C_BASE_DBGU ; 
-    unsigned int temp;
-    
-    while(*buffer != '\0') 
-    {
-        temp=0;
-        
-	while (temp==0)
-	{
-	  if ( (pDbgu->DBGU_CSR & 0x0200) == 0)
-	    temp=0;
-	  else
-	    temp=1;
-	}
-
-        pDbgu->DBGU_THR = *buffer;
-        buffer++;
-    }
-}
-
-
-void Init_DBGU_CLK(void)
-{
-  AT91F_PMC_EnablePeriphClock(AT91C_BASE_PMC, ((unsigned int) 1 << AT91C_ID_SYS));
-}
-
-void Init_DBGU_BGR(unsigned short baud)
-{
-  AT91PS_DBGU pDbgu = AT91C_BASE_DBGU ; 
-  
-  pDbgu->DBGU_BRGR = (unsigned short)baud;
-}
-
-void DBGU_TX_Enable(void)
-{
-  AT91PS_DBGU pDbgu = AT91C_BASE_DBGU ; 
-  
-  pDbgu->DBGU_CR = 0x00000040;
-}
-
-void DBGU_RX_Enable(void)
-{
-  AT91PS_DBGU pDbgu = AT91C_BASE_DBGU ; 
-  
-  pDbgu->DBGU_CR = 0x00000010;
-}
-
-void DBGU_RX_TX_RST_DIS(void)
-{
-  AT91PS_DBGU pDbgu = AT91C_BASE_DBGU ; 
-  pDbgu->DBGU_CR = 0x000000AC;
-}
-
-void DBGU_Parity_Cfg(unsigned int par)
-{
-  AT91PS_DBGU pDbgu = AT91C_BASE_DBGU ; 
-  
-  pDbgu->DBGU_MR = par << 9;
-}
-
-
-void Init_DBGU(void)
-{ 
-  AT91F_DBGU_CfgPIO();
-  DBGU_RX_TX_RST_DIS();
-  Init_DBGU_BGR(26);  //26 <=> 115kBd
-  DBGU_Parity_Cfg(4);
-  DBGU_TX_Enable();   
-  DBGU_RX_Enable();
-}
-
-
diff --git a/Demo/uIP_Demo_IAR_ARM7/SrcIAR/dbgu.h b/Demo/uIP_Demo_IAR_ARM7/SrcIAR/dbgu.h
deleted file mode 100644
index 58f50a046..000000000
--- a/Demo/uIP_Demo_IAR_ARM7/SrcIAR/dbgu.h
+++ /dev/null
@@ -1,22 +0,0 @@
-//*----------------------------------------------------------------------------
-//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
-//*----------------------------------------------------------------------------
-//* The software is delivered "AS IS" without warranty or condition of any
-//* kind, either express, implied or statutory. This includes without
-//* limitation any warranty or condition with respect to merchantability or
-//* fitness for any particular purpose, or against the infringements of
-//* intellectual property rights of others.
-//*----------------------------------------------------------------------------
-//* File Name           : dbgu.c
-//* Object              : DBGU routines written in C
-//* Creation            : JG   16/Aug/2004
-//*----------------------------------------------------------------------------
-
-// Include Standard files
-extern void APPLI_DBGU(void);   
-extern void D1_TEST_REGISTER_RESET_VALUES(void);
-extern void D2_CHIP_ID_VALUES(void);
-
-
-
-
diff --git a/Demo/uIP_Demo_IAR_ARM7/SrcIAR/init.c b/Demo/uIP_Demo_IAR_ARM7/SrcIAR/init.c
deleted file mode 100644
index cbb1ee48e..000000000
--- a/Demo/uIP_Demo_IAR_ARM7/SrcIAR/init.c
+++ /dev/null
@@ -1,31 +0,0 @@
-//*----------------------------------------------------------------------------
-//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
-//*----------------------------------------------------------------------------
-//* The software is delivered "AS IS" without warranty or condition of any
-//* kind, either express, implied or statutory. This includes without
-//* limitation any warranty or condition with respect to merchantability or
-//* fitness for any particular purpose, or against the infringements of
-//* intellectual property rights of others.
-//*----------------------------------------------------------------------------
-//* File Name           : init.c
-//* Object              : Low level initialisations written in C
-//* Creation            : ODi   06/26/2002
-//*
-//*----------------------------------------------------------------------------
-#include "board.h"
-//#include "init.h"
-#include 
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_Printk
-//* \brief This function is used to send a string through the DBGU channel (Very low level debugging)
-//*----------------------------------------------------------------------------
-void AT91F_DBGU_Printk(
-	char *buffer) // \arg pointer to a string ending by \0
-{
-	while(*buffer != '\0') {
-		while (!AT91F_US_TxReady((AT91PS_USART)AT91C_BASE_DBGU));
-		AT91F_US_PutChar((AT91PS_USART)AT91C_BASE_DBGU, *buffer++);
-	}
-}
-
diff --git a/Demo/uIP_Demo_IAR_ARM7/SrcIAR/ioat91sam7x128.h b/Demo/uIP_Demo_IAR_ARM7/SrcIAR/ioat91sam7x128.h
deleted file mode 100644
index df9caccb5..000000000
--- a/Demo/uIP_Demo_IAR_ARM7/SrcIAR/ioat91sam7x128.h
+++ /dev/null
@@ -1,4700 +0,0 @@
-// - ----------------------------------------------------------------------------
-// -          ATMEL Microcontroller Software Support  -  ROUSSET  -
-// - ----------------------------------------------------------------------------
-// -  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-// -  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-// -  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-// -  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-// -  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// -  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-// -  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-// -  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-// -  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-// -  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// - ----------------------------------------------------------------------------
-// - File Name           : AT91SAM7X128.h
-// - Object              : AT91SAM7X128 definitions
-// - Generated           : AT91 SW Application Group  05/20/2005 (16:22:23)
-// - 
-// - CVS Reference       : /AT91SAM7X128.pl/1.14/Tue May 10 12:12:05 2005//
-// - CVS Reference       : /SYS_SAM7X.pl/1.3/Tue Feb  1 17:01:43 2005//
-// - CVS Reference       : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
-// - CVS Reference       : /PMC_SAM7X.pl/1.4/Tue Feb  8 13:58:10 2005//
-// - CVS Reference       : /RSTC_SAM7X.pl/1.1/Tue Feb  1 16:16:26 2005//
-// - CVS Reference       : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
-// - CVS Reference       : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
-// - CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
-// - CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:18:28 2005//
-// - CVS Reference       : /RTTC_6081A.pl/1.2/Tue Nov  9 14:43:58 2004//
-// - CVS Reference       : /PITC_6079A.pl/1.2/Tue Nov  9 14:43:56 2004//
-// - CVS Reference       : /WDTC_6080A.pl/1.3/Tue Nov  9 14:44:00 2004//
-// - CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:05:48 2005//
-// - CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 08:48:54 2005//
-// - CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
-// - CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
-// - CVS Reference       : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
-// - CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
-// - CVS Reference       : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
-// - CVS Reference       : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
-// - CVS Reference       : /CAN_6019B.pl/1.1/Tue Mar  8 12:42:22 2005//
-// - CVS Reference       : /EMACB_6119A.pl/1.5/Thu Feb  3 15:52:04 2005//
-// - CVS Reference       : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
-// - CVS Reference       : /AES_6149A.pl/1.10/Mon Feb  7 09:44:25 2005//
-// - CVS Reference       : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
-// - ----------------------------------------------------------------------------
-
-#ifndef AT91SAM7X128_H
-#define AT91SAM7X128_H
-
-#ifdef __IAR_SYSTEMS_ICC__
-
-typedef volatile unsigned int AT91_REG;// Hardware register definition
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR System Peripherals
-// *****************************************************************************
-typedef struct _AT91S_SYS {
-	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
-	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
-	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
-	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
-	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
-	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
-	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
-	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
-	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
-	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
-	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
-	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
-	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
-	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
-	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
-	AT91_REG	 Reserved2[45]; 	// 
-	AT91_REG	 DBGU_CR; 	// Control Register
-	AT91_REG	 DBGU_MR; 	// Mode Register
-	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
-	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
-	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
-	AT91_REG	 DBGU_CSR; 	// Channel Status Register
-	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
-	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
-	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 Reserved3[7]; 	// 
-	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
-	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
-	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
-	AT91_REG	 Reserved4[45]; 	// 
-	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
-	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
-	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
-	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
-	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
-	AT91_REG	 Reserved5[54]; 	// 
-	AT91_REG	 PIOA_PER; 	// PIO Enable Register
-	AT91_REG	 PIOA_PDR; 	// PIO Disable Register
-	AT91_REG	 PIOA_PSR; 	// PIO Status Register
-	AT91_REG	 Reserved6[1]; 	// 
-	AT91_REG	 PIOA_OER; 	// Output Enable Register
-	AT91_REG	 PIOA_ODR; 	// Output Disable Registerr
-	AT91_REG	 PIOA_OSR; 	// Output Status Register
-	AT91_REG	 Reserved7[1]; 	// 
-	AT91_REG	 PIOA_IFER; 	// Input Filter Enable Register
-	AT91_REG	 PIOA_IFDR; 	// Input Filter Disable Register
-	AT91_REG	 PIOA_IFSR; 	// Input Filter Status Register
-	AT91_REG	 Reserved8[1]; 	// 
-	AT91_REG	 PIOA_SODR; 	// Set Output Data Register
-	AT91_REG	 PIOA_CODR; 	// Clear Output Data Register
-	AT91_REG	 PIOA_ODSR; 	// Output Data Status Register
-	AT91_REG	 PIOA_PDSR; 	// Pin Data Status Register
-	AT91_REG	 PIOA_IER; 	// Interrupt Enable Register
-	AT91_REG	 PIOA_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PIOA_IMR; 	// Interrupt Mask Register
-	AT91_REG	 PIOA_ISR; 	// Interrupt Status Register
-	AT91_REG	 PIOA_MDER; 	// Multi-driver Enable Register
-	AT91_REG	 PIOA_MDDR; 	// Multi-driver Disable Register
-	AT91_REG	 PIOA_MDSR; 	// Multi-driver Status Register
-	AT91_REG	 Reserved9[1]; 	// 
-	AT91_REG	 PIOA_PPUDR; 	// Pull-up Disable Register
-	AT91_REG	 PIOA_PPUER; 	// Pull-up Enable Register
-	AT91_REG	 PIOA_PPUSR; 	// Pull-up Status Register
-	AT91_REG	 Reserved10[1]; 	// 
-	AT91_REG	 PIOA_ASR; 	// Select A Register
-	AT91_REG	 PIOA_BSR; 	// Select B Register
-	AT91_REG	 PIOA_ABSR; 	// AB Select Status Register
-	AT91_REG	 Reserved11[9]; 	// 
-	AT91_REG	 PIOA_OWER; 	// Output Write Enable Register
-	AT91_REG	 PIOA_OWDR; 	// Output Write Disable Register
-	AT91_REG	 PIOA_OWSR; 	// Output Write Status Register
-	AT91_REG	 Reserved12[85]; 	// 
-	AT91_REG	 PIOB_PER; 	// PIO Enable Register
-	AT91_REG	 PIOB_PDR; 	// PIO Disable Register
-	AT91_REG	 PIOB_PSR; 	// PIO Status Register
-	AT91_REG	 Reserved13[1]; 	// 
-	AT91_REG	 PIOB_OER; 	// Output Enable Register
-	AT91_REG	 PIOB_ODR; 	// Output Disable Registerr
-	AT91_REG	 PIOB_OSR; 	// Output Status Register
-	AT91_REG	 Reserved14[1]; 	// 
-	AT91_REG	 PIOB_IFER; 	// Input Filter Enable Register
-	AT91_REG	 PIOB_IFDR; 	// Input Filter Disable Register
-	AT91_REG	 PIOB_IFSR; 	// Input Filter Status Register
-	AT91_REG	 Reserved15[1]; 	// 
-	AT91_REG	 PIOB_SODR; 	// Set Output Data Register
-	AT91_REG	 PIOB_CODR; 	// Clear Output Data Register
-	AT91_REG	 PIOB_ODSR; 	// Output Data Status Register
-	AT91_REG	 PIOB_PDSR; 	// Pin Data Status Register
-	AT91_REG	 PIOB_IER; 	// Interrupt Enable Register
-	AT91_REG	 PIOB_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PIOB_IMR; 	// Interrupt Mask Register
-	AT91_REG	 PIOB_ISR; 	// Interrupt Status Register
-	AT91_REG	 PIOB_MDER; 	// Multi-driver Enable Register
-	AT91_REG	 PIOB_MDDR; 	// Multi-driver Disable Register
-	AT91_REG	 PIOB_MDSR; 	// Multi-driver Status Register
-	AT91_REG	 Reserved16[1]; 	// 
-	AT91_REG	 PIOB_PPUDR; 	// Pull-up Disable Register
-	AT91_REG	 PIOB_PPUER; 	// Pull-up Enable Register
-	AT91_REG	 PIOB_PPUSR; 	// Pull-up Status Register
-	AT91_REG	 Reserved17[1]; 	// 
-	AT91_REG	 PIOB_ASR; 	// Select A Register
-	AT91_REG	 PIOB_BSR; 	// Select B Register
-	AT91_REG	 PIOB_ABSR; 	// AB Select Status Register
-	AT91_REG	 Reserved18[9]; 	// 
-	AT91_REG	 PIOB_OWER; 	// Output Write Enable Register
-	AT91_REG	 PIOB_OWDR; 	// Output Write Disable Register
-	AT91_REG	 PIOB_OWSR; 	// Output Write Status Register
-	AT91_REG	 Reserved19[341]; 	// 
-	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
-	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
-	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
-	AT91_REG	 Reserved20[1]; 	// 
-	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
-	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
-	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
-	AT91_REG	 Reserved21[1]; 	// 
-	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
-	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 Reserved22[1]; 	// 
-	AT91_REG	 PMC_PLLR; 	// PLL Register
-	AT91_REG	 PMC_MCKR; 	// Master Clock Register
-	AT91_REG	 Reserved23[3]; 	// 
-	AT91_REG	 PMC_PCKR[4]; 	// Programmable Clock Register
-	AT91_REG	 Reserved24[4]; 	// 
-	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
-	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PMC_SR; 	// Status Register
-	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved25[36]; 	// 
-	AT91_REG	 RSTC_RCR; 	// Reset Control Register
-	AT91_REG	 RSTC_RSR; 	// Reset Status Register
-	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
-	AT91_REG	 Reserved26[5]; 	// 
-	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
-	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
-	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
-	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
-	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
-	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
-	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
-	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
-	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
-	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
-	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
-	AT91_REG	 Reserved27[5]; 	// 
-	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
-} AT91S_SYS, *AT91PS_SYS;
-
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
-// *****************************************************************************
-typedef struct _AT91S_AIC {
-	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
-	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
-	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
-	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
-	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
-	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
-	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
-	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
-	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
-	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
-	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
-	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
-	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
-	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
-	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
-} AT91S_AIC, *AT91PS_AIC;
-
-// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
-#define AT91C_AIC_PRIOR       ((unsigned int) 0x7 <<  0) // (AIC) Priority Level
-#define 	AT91C_AIC_PRIOR_LOWEST               ((unsigned int) 0x0) // (AIC) Lowest priority level
-#define 	AT91C_AIC_PRIOR_HIGHEST              ((unsigned int) 0x7) // (AIC) Highest priority level
-#define AT91C_AIC_SRCTYPE     ((unsigned int) 0x3 <<  5) // (AIC) Interrupt Source Type
-#define 	AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       ((unsigned int) 0x0 <<  5) // (AIC) Internal Sources Code Label High-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        ((unsigned int) 0x0 <<  5) // (AIC) External Sources Code Label Low-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) Internal Sources Code Label Positive Edge triggered
-#define 	AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) External Sources Code Label Negative Edge triggered
-#define 	AT91C_AIC_SRCTYPE_HIGH_LEVEL           ((unsigned int) 0x2 <<  5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_POSITIVE_EDGE        ((unsigned int) 0x3 <<  5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
-// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
-#define AT91C_AIC_NFIQ        ((unsigned int) 0x1 <<  0) // (AIC) NFIQ Status
-#define AT91C_AIC_NIRQ        ((unsigned int) 0x1 <<  1) // (AIC) NIRQ Status
-// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
-#define AT91C_AIC_DCR_PROT    ((unsigned int) 0x1 <<  0) // (AIC) Protection Mode
-#define AT91C_AIC_DCR_GMSK    ((unsigned int) 0x1 <<  1) // (AIC) General Mask
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
-// *****************************************************************************
-typedef struct _AT91S_PDC {
-	AT91_REG	 PDC_RPR; 	// Receive Pointer Register
-	AT91_REG	 PDC_RCR; 	// Receive Counter Register
-	AT91_REG	 PDC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 PDC_TCR; 	// Transmit Counter Register
-	AT91_REG	 PDC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 PDC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 PDC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 PDC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 PDC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 PDC_PTSR; 	// PDC Transfer Status Register
-} AT91S_PDC, *AT91PS_PDC;
-
-// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
-#define AT91C_PDC_RXTEN       ((unsigned int) 0x1 <<  0) // (PDC) Receiver Transfer Enable
-#define AT91C_PDC_RXTDIS      ((unsigned int) 0x1 <<  1) // (PDC) Receiver Transfer Disable
-#define AT91C_PDC_TXTEN       ((unsigned int) 0x1 <<  8) // (PDC) Transmitter Transfer Enable
-#define AT91C_PDC_TXTDIS      ((unsigned int) 0x1 <<  9) // (PDC) Transmitter Transfer Disable
-// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Debug Unit
-// *****************************************************************************
-typedef struct _AT91S_DBGU {
-	AT91_REG	 DBGU_CR; 	// Control Register
-	AT91_REG	 DBGU_MR; 	// Mode Register
-	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
-	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
-	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
-	AT91_REG	 DBGU_CSR; 	// Channel Status Register
-	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
-	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
-	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 Reserved0[7]; 	// 
-	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
-	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
-	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
-	AT91_REG	 Reserved1[45]; 	// 
-	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
-	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
-	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
-	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
-	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
-} AT91S_DBGU, *AT91PS_DBGU;
-
-// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
-#define AT91C_US_RSTRX        ((unsigned int) 0x1 <<  2) // (DBGU) Reset Receiver
-#define AT91C_US_RSTTX        ((unsigned int) 0x1 <<  3) // (DBGU) Reset Transmitter
-#define AT91C_US_RXEN         ((unsigned int) 0x1 <<  4) // (DBGU) Receiver Enable
-#define AT91C_US_RXDIS        ((unsigned int) 0x1 <<  5) // (DBGU) Receiver Disable
-#define AT91C_US_TXEN         ((unsigned int) 0x1 <<  6) // (DBGU) Transmitter Enable
-#define AT91C_US_TXDIS        ((unsigned int) 0x1 <<  7) // (DBGU) Transmitter Disable
-#define AT91C_US_RSTSTA       ((unsigned int) 0x1 <<  8) // (DBGU) Reset Status Bits
-// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
-#define AT91C_US_PAR          ((unsigned int) 0x7 <<  9) // (DBGU) Parity type
-#define 	AT91C_US_PAR_EVEN                 ((unsigned int) 0x0 <<  9) // (DBGU) Even Parity
-#define 	AT91C_US_PAR_ODD                  ((unsigned int) 0x1 <<  9) // (DBGU) Odd Parity
-#define 	AT91C_US_PAR_SPACE                ((unsigned int) 0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
-#define 	AT91C_US_PAR_MARK                 ((unsigned int) 0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
-#define 	AT91C_US_PAR_NONE                 ((unsigned int) 0x4 <<  9) // (DBGU) No Parity
-#define 	AT91C_US_PAR_MULTI_DROP           ((unsigned int) 0x6 <<  9) // (DBGU) Multi-drop mode
-#define AT91C_US_CHMODE       ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
-#define 	AT91C_US_CHMODE_NORMAL               ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-#define 	AT91C_US_CHMODE_AUTO                 ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-#define 	AT91C_US_CHMODE_LOCAL                ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-#define 	AT91C_US_CHMODE_REMOTE               ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
-#define AT91C_US_RXRDY        ((unsigned int) 0x1 <<  0) // (DBGU) RXRDY Interrupt
-#define AT91C_US_TXRDY        ((unsigned int) 0x1 <<  1) // (DBGU) TXRDY Interrupt
-#define AT91C_US_ENDRX        ((unsigned int) 0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
-#define AT91C_US_ENDTX        ((unsigned int) 0x1 <<  4) // (DBGU) End of Transmit Interrupt
-#define AT91C_US_OVRE         ((unsigned int) 0x1 <<  5) // (DBGU) Overrun Interrupt
-#define AT91C_US_FRAME        ((unsigned int) 0x1 <<  6) // (DBGU) Framing Error Interrupt
-#define AT91C_US_PARE         ((unsigned int) 0x1 <<  7) // (DBGU) Parity Error Interrupt
-#define AT91C_US_TXEMPTY      ((unsigned int) 0x1 <<  9) // (DBGU) TXEMPTY Interrupt
-#define AT91C_US_TXBUFE       ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
-#define AT91C_US_RXBUFF       ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
-#define AT91C_US_COMM_TX      ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
-#define AT91C_US_COMM_RX      ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
-// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
-// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
-// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
-// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
-#define AT91C_US_FORCE_NTRST  ((unsigned int) 0x1 <<  0) // (DBGU) Force NTRST in JTAG
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
-// *****************************************************************************
-typedef struct _AT91S_PIO {
-	AT91_REG	 PIO_PER; 	// PIO Enable Register
-	AT91_REG	 PIO_PDR; 	// PIO Disable Register
-	AT91_REG	 PIO_PSR; 	// PIO Status Register
-	AT91_REG	 Reserved0[1]; 	// 
-	AT91_REG	 PIO_OER; 	// Output Enable Register
-	AT91_REG	 PIO_ODR; 	// Output Disable Registerr
-	AT91_REG	 PIO_OSR; 	// Output Status Register
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 PIO_IFER; 	// Input Filter Enable Register
-	AT91_REG	 PIO_IFDR; 	// Input Filter Disable Register
-	AT91_REG	 PIO_IFSR; 	// Input Filter Status Register
-	AT91_REG	 Reserved2[1]; 	// 
-	AT91_REG	 PIO_SODR; 	// Set Output Data Register
-	AT91_REG	 PIO_CODR; 	// Clear Output Data Register
-	AT91_REG	 PIO_ODSR; 	// Output Data Status Register
-	AT91_REG	 PIO_PDSR; 	// Pin Data Status Register
-	AT91_REG	 PIO_IER; 	// Interrupt Enable Register
-	AT91_REG	 PIO_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PIO_IMR; 	// Interrupt Mask Register
-	AT91_REG	 PIO_ISR; 	// Interrupt Status Register
-	AT91_REG	 PIO_MDER; 	// Multi-driver Enable Register
-	AT91_REG	 PIO_MDDR; 	// Multi-driver Disable Register
-	AT91_REG	 PIO_MDSR; 	// Multi-driver Status Register
-	AT91_REG	 Reserved3[1]; 	// 
-	AT91_REG	 PIO_PPUDR; 	// Pull-up Disable Register
-	AT91_REG	 PIO_PPUER; 	// Pull-up Enable Register
-	AT91_REG	 PIO_PPUSR; 	// Pull-up Status Register
-	AT91_REG	 Reserved4[1]; 	// 
-	AT91_REG	 PIO_ASR; 	// Select A Register
-	AT91_REG	 PIO_BSR; 	// Select B Register
-	AT91_REG	 PIO_ABSR; 	// AB Select Status Register
-	AT91_REG	 Reserved5[9]; 	// 
-	AT91_REG	 PIO_OWER; 	// Output Write Enable Register
-	AT91_REG	 PIO_OWDR; 	// Output Write Disable Register
-	AT91_REG	 PIO_OWSR; 	// Output Write Status Register
-} AT91S_PIO, *AT91PS_PIO;
-
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
-// *****************************************************************************
-typedef struct _AT91S_CKGR {
-	AT91_REG	 CKGR_MOR; 	// Main Oscillator Register
-	AT91_REG	 CKGR_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 Reserved0[1]; 	// 
-	AT91_REG	 CKGR_PLLR; 	// PLL Register
-} AT91S_CKGR, *AT91PS_CKGR;
-
-// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
-#define AT91C_CKGR_MOSCEN     ((unsigned int) 0x1 <<  0) // (CKGR) Main Oscillator Enable
-#define AT91C_CKGR_OSCBYPASS  ((unsigned int) 0x1 <<  1) // (CKGR) Main Oscillator Bypass
-#define AT91C_CKGR_OSCOUNT    ((unsigned int) 0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
-// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
-#define AT91C_CKGR_MAINF      ((unsigned int) 0xFFFF <<  0) // (CKGR) Main Clock Frequency
-#define AT91C_CKGR_MAINRDY    ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
-// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 
-#define AT91C_CKGR_DIV        ((unsigned int) 0xFF <<  0) // (CKGR) Divider Selected
-#define 	AT91C_CKGR_DIV_0                    ((unsigned int) 0x0) // (CKGR) Divider output is 0
-#define 	AT91C_CKGR_DIV_BYPASS               ((unsigned int) 0x1) // (CKGR) Divider is bypassed
-#define AT91C_CKGR_PLLCOUNT   ((unsigned int) 0x3F <<  8) // (CKGR) PLL Counter
-#define AT91C_CKGR_OUT        ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
-#define 	AT91C_CKGR_OUT_0                    ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_1                    ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_2                    ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_3                    ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_MUL        ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
-#define AT91C_CKGR_USBDIV     ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
-#define 	AT91C_CKGR_USBDIV_0                    ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
-#define 	AT91C_CKGR_USBDIV_1                    ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
-#define 	AT91C_CKGR_USBDIV_2                    ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Power Management Controler
-// *****************************************************************************
-typedef struct _AT91S_PMC {
-	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
-	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
-	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
-	AT91_REG	 Reserved0[1]; 	// 
-	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
-	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
-	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
-	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 Reserved2[1]; 	// 
-	AT91_REG	 PMC_PLLR; 	// PLL Register
-	AT91_REG	 PMC_MCKR; 	// Master Clock Register
-	AT91_REG	 Reserved3[3]; 	// 
-	AT91_REG	 PMC_PCKR[4]; 	// Programmable Clock Register
-	AT91_REG	 Reserved4[4]; 	// 
-	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
-	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PMC_SR; 	// Status Register
-	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
-} AT91S_PMC, *AT91PS_PMC;
-
-// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
-#define AT91C_PMC_PCK         ((unsigned int) 0x1 <<  0) // (PMC) Processor Clock
-#define AT91C_PMC_UDP         ((unsigned int) 0x1 <<  7) // (PMC) USB Device Port Clock
-#define AT91C_PMC_PCK0        ((unsigned int) 0x1 <<  8) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK1        ((unsigned int) 0x1 <<  9) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK2        ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK3        ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
-// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
-// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
-// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
-// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
-// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 
-// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
-#define AT91C_PMC_CSS         ((unsigned int) 0x3 <<  0) // (PMC) Programmable Clock Selection
-#define 	AT91C_PMC_CSS_SLOW_CLK             ((unsigned int) 0x0) // (PMC) Slow Clock is selected
-#define 	AT91C_PMC_CSS_MAIN_CLK             ((unsigned int) 0x1) // (PMC) Main Clock is selected
-#define 	AT91C_PMC_CSS_PLL_CLK              ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
-#define AT91C_PMC_PRES        ((unsigned int) 0x7 <<  2) // (PMC) Programmable Clock Prescaler
-#define 	AT91C_PMC_PRES_CLK                  ((unsigned int) 0x0 <<  2) // (PMC) Selected clock
-#define 	AT91C_PMC_PRES_CLK_2                ((unsigned int) 0x1 <<  2) // (PMC) Selected clock divided by 2
-#define 	AT91C_PMC_PRES_CLK_4                ((unsigned int) 0x2 <<  2) // (PMC) Selected clock divided by 4
-#define 	AT91C_PMC_PRES_CLK_8                ((unsigned int) 0x3 <<  2) // (PMC) Selected clock divided by 8
-#define 	AT91C_PMC_PRES_CLK_16               ((unsigned int) 0x4 <<  2) // (PMC) Selected clock divided by 16
-#define 	AT91C_PMC_PRES_CLK_32               ((unsigned int) 0x5 <<  2) // (PMC) Selected clock divided by 32
-#define 	AT91C_PMC_PRES_CLK_64               ((unsigned int) 0x6 <<  2) // (PMC) Selected clock divided by 64
-// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
-// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
-#define AT91C_PMC_MOSCS       ((unsigned int) 0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
-#define AT91C_PMC_LOCK        ((unsigned int) 0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
-#define AT91C_PMC_MCKRDY      ((unsigned int) 0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK0RDY     ((unsigned int) 0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK1RDY     ((unsigned int) 0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK2RDY     ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK3RDY     ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
-// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
-// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
-// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_RSTC {
-	AT91_REG	 RSTC_RCR; 	// Reset Control Register
-	AT91_REG	 RSTC_RSR; 	// Reset Status Register
-	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
-} AT91S_RSTC, *AT91PS_RSTC;
-
-// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
-#define AT91C_RSTC_PROCRST    ((unsigned int) 0x1 <<  0) // (RSTC) Processor Reset
-#define AT91C_RSTC_PERRST     ((unsigned int) 0x1 <<  2) // (RSTC) Peripheral Reset
-#define AT91C_RSTC_EXTRST     ((unsigned int) 0x1 <<  3) // (RSTC) External Reset
-#define AT91C_RSTC_KEY        ((unsigned int) 0xFF << 24) // (RSTC) Password
-// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
-#define AT91C_RSTC_URSTS      ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Status
-#define AT91C_RSTC_BODSTS     ((unsigned int) 0x1 <<  1) // (RSTC) Brownout Detection Status
-#define AT91C_RSTC_RSTTYP     ((unsigned int) 0x7 <<  8) // (RSTC) Reset Type
-#define 	AT91C_RSTC_RSTTYP_POWERUP              ((unsigned int) 0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
-#define 	AT91C_RSTC_RSTTYP_WAKEUP               ((unsigned int) 0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.
-#define 	AT91C_RSTC_RSTTYP_WATCHDOG             ((unsigned int) 0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
-#define 	AT91C_RSTC_RSTTYP_SOFTWARE             ((unsigned int) 0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
-#define 	AT91C_RSTC_RSTTYP_USER                 ((unsigned int) 0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
-#define 	AT91C_RSTC_RSTTYP_BROWNOUT             ((unsigned int) 0x5 <<  8) // (RSTC) Brownout Reset occured.
-#define AT91C_RSTC_NRSTL      ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
-#define AT91C_RSTC_SRCMP      ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
-// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
-#define AT91C_RSTC_URSTEN     ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Enable
-#define AT91C_RSTC_URSTIEN    ((unsigned int) 0x1 <<  4) // (RSTC) User Reset Interrupt Enable
-#define AT91C_RSTC_ERSTL      ((unsigned int) 0xF <<  8) // (RSTC) User Reset Enable
-#define AT91C_RSTC_BODIEN     ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_RTTC {
-	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
-	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
-	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
-	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
-} AT91S_RTTC, *AT91PS_RTTC;
-
-// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
-#define AT91C_RTTC_RTPRES     ((unsigned int) 0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
-#define AT91C_RTTC_ALMIEN     ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
-#define AT91C_RTTC_RTTINCIEN  ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
-#define AT91C_RTTC_RTTRST     ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
-// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
-#define AT91C_RTTC_ALMV       ((unsigned int) 0x0 <<  0) // (RTTC) Alarm Value
-// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
-#define AT91C_RTTC_CRTV       ((unsigned int) 0x0 <<  0) // (RTTC) Current Real-time Value
-// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
-#define AT91C_RTTC_ALMS       ((unsigned int) 0x1 <<  0) // (RTTC) Real-time Alarm Status
-#define AT91C_RTTC_RTTINC     ((unsigned int) 0x1 <<  1) // (RTTC) Real-time Timer Increment
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_PITC {
-	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
-	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
-	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
-	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
-} AT91S_PITC, *AT91PS_PITC;
-
-// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
-#define AT91C_PITC_PIV        ((unsigned int) 0xFFFFF <<  0) // (PITC) Periodic Interval Value
-#define AT91C_PITC_PITEN      ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
-#define AT91C_PITC_PITIEN     ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
-// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
-#define AT91C_PITC_PITS       ((unsigned int) 0x1 <<  0) // (PITC) Periodic Interval Timer Status
-// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
-#define AT91C_PITC_CPIV       ((unsigned int) 0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
-#define AT91C_PITC_PICNT      ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
-// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_WDTC {
-	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
-	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
-	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
-} AT91S_WDTC, *AT91PS_WDTC;
-
-// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
-#define AT91C_WDTC_WDRSTT     ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Restart
-#define AT91C_WDTC_KEY        ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password
-// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
-#define AT91C_WDTC_WDV        ((unsigned int) 0xFFF <<  0) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDFIEN     ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
-#define AT91C_WDTC_WDRSTEN    ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
-#define AT91C_WDTC_WDRPROC    ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDDIS      ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
-#define AT91C_WDTC_WDD        ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
-#define AT91C_WDTC_WDDBGHLT   ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
-#define AT91C_WDTC_WDIDLEHLT  ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
-// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
-#define AT91C_WDTC_WDUNF      ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Underflow
-#define AT91C_WDTC_WDERR      ((unsigned int) 0x1 <<  1) // (WDTC) Watchdog Error
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_VREG {
-	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
-} AT91S_VREG, *AT91PS_VREG;
-
-// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- 
-#define AT91C_VREG_PSTDBY     ((unsigned int) 0x1 <<  0) // (VREG) Voltage Regulator Power Standby Mode
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_MC {
-	AT91_REG	 MC_RCR; 	// MC Remap Control Register
-	AT91_REG	 MC_ASR; 	// MC Abort Status Register
-	AT91_REG	 MC_AASR; 	// MC Abort Address Status Register
-	AT91_REG	 Reserved0[21]; 	// 
-	AT91_REG	 MC_FMR; 	// MC Flash Mode Register
-	AT91_REG	 MC_FCR; 	// MC Flash Command Register
-	AT91_REG	 MC_FSR; 	// MC Flash Status Register
-} AT91S_MC, *AT91PS_MC;
-
-// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
-#define AT91C_MC_RCB          ((unsigned int) 0x1 <<  0) // (MC) Remap Command Bit
-// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
-#define AT91C_MC_UNDADD       ((unsigned int) 0x1 <<  0) // (MC) Undefined Addess Abort Status
-#define AT91C_MC_MISADD       ((unsigned int) 0x1 <<  1) // (MC) Misaligned Addess Abort Status
-#define AT91C_MC_ABTSZ        ((unsigned int) 0x3 <<  8) // (MC) Abort Size Status
-#define 	AT91C_MC_ABTSZ_BYTE                 ((unsigned int) 0x0 <<  8) // (MC) Byte
-#define 	AT91C_MC_ABTSZ_HWORD                ((unsigned int) 0x1 <<  8) // (MC) Half-word
-#define 	AT91C_MC_ABTSZ_WORD                 ((unsigned int) 0x2 <<  8) // (MC) Word
-#define AT91C_MC_ABTTYP       ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
-#define 	AT91C_MC_ABTTYP_DATAR                ((unsigned int) 0x0 << 10) // (MC) Data Read
-#define 	AT91C_MC_ABTTYP_DATAW                ((unsigned int) 0x1 << 10) // (MC) Data Write
-#define 	AT91C_MC_ABTTYP_FETCH                ((unsigned int) 0x2 << 10) // (MC) Code Fetch
-#define AT91C_MC_MST0         ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
-#define AT91C_MC_MST1         ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
-#define AT91C_MC_SVMST0       ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
-#define AT91C_MC_SVMST1       ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
-// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- 
-#define AT91C_MC_FRDY         ((unsigned int) 0x1 <<  0) // (MC) Flash Ready
-#define AT91C_MC_LOCKE        ((unsigned int) 0x1 <<  2) // (MC) Lock Error
-#define AT91C_MC_PROGE        ((unsigned int) 0x1 <<  3) // (MC) Programming Error
-#define AT91C_MC_NEBP         ((unsigned int) 0x1 <<  7) // (MC) No Erase Before Programming
-#define AT91C_MC_FWS          ((unsigned int) 0x3 <<  8) // (MC) Flash Wait State
-#define 	AT91C_MC_FWS_0FWS                 ((unsigned int) 0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations
-#define 	AT91C_MC_FWS_1FWS                 ((unsigned int) 0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations
-#define 	AT91C_MC_FWS_2FWS                 ((unsigned int) 0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations
-#define 	AT91C_MC_FWS_3FWS                 ((unsigned int) 0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations
-#define AT91C_MC_FMCN         ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
-// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- 
-#define AT91C_MC_FCMD         ((unsigned int) 0xF <<  0) // (MC) Flash Command
-#define 	AT91C_MC_FCMD_START_PROG           ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
-#define 	AT91C_MC_FCMD_LOCK                 ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define 	AT91C_MC_FCMD_PROG_AND_LOCK        ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
-#define 	AT91C_MC_FCMD_UNLOCK               ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define 	AT91C_MC_FCMD_ERASE_ALL            ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
-#define 	AT91C_MC_FCMD_SET_GP_NVM           ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
-#define 	AT91C_MC_FCMD_CLR_GP_NVM           ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
-#define 	AT91C_MC_FCMD_SET_SECURITY         ((unsigned int) 0xF) // (MC) Set Security Bit.
-#define AT91C_MC_PAGEN        ((unsigned int) 0x3FF <<  8) // (MC) Page Number
-#define AT91C_MC_KEY          ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
-// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- 
-#define AT91C_MC_SECURITY     ((unsigned int) 0x1 <<  4) // (MC) Security Bit Status
-#define AT91C_MC_GPNVM0       ((unsigned int) 0x1 <<  8) // (MC) Sector 0 Lock Status
-#define AT91C_MC_GPNVM1       ((unsigned int) 0x1 <<  9) // (MC) Sector 1 Lock Status
-#define AT91C_MC_GPNVM2       ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
-#define AT91C_MC_GPNVM3       ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
-#define AT91C_MC_GPNVM4       ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
-#define AT91C_MC_GPNVM5       ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
-#define AT91C_MC_GPNVM6       ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
-#define AT91C_MC_GPNVM7       ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS0       ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
-#define AT91C_MC_LOCKS1       ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
-#define AT91C_MC_LOCKS2       ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
-#define AT91C_MC_LOCKS3       ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
-#define AT91C_MC_LOCKS4       ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
-#define AT91C_MC_LOCKS5       ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
-#define AT91C_MC_LOCKS6       ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
-#define AT91C_MC_LOCKS7       ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS8       ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
-#define AT91C_MC_LOCKS9       ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
-#define AT91C_MC_LOCKS10      ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
-#define AT91C_MC_LOCKS11      ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
-#define AT91C_MC_LOCKS12      ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
-#define AT91C_MC_LOCKS13      ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
-#define AT91C_MC_LOCKS14      ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
-#define AT91C_MC_LOCKS15      ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
-// *****************************************************************************
-typedef struct _AT91S_SPI {
-	AT91_REG	 SPI_CR; 	// Control Register
-	AT91_REG	 SPI_MR; 	// Mode Register
-	AT91_REG	 SPI_RDR; 	// Receive Data Register
-	AT91_REG	 SPI_TDR; 	// Transmit Data Register
-	AT91_REG	 SPI_SR; 	// Status Register
-	AT91_REG	 SPI_IER; 	// Interrupt Enable Register
-	AT91_REG	 SPI_IDR; 	// Interrupt Disable Register
-	AT91_REG	 SPI_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved0[4]; 	// 
-	AT91_REG	 SPI_CSR[4]; 	// Chip Select Register
-	AT91_REG	 Reserved1[48]; 	// 
-	AT91_REG	 SPI_RPR; 	// Receive Pointer Register
-	AT91_REG	 SPI_RCR; 	// Receive Counter Register
-	AT91_REG	 SPI_TPR; 	// Transmit Pointer Register
-	AT91_REG	 SPI_TCR; 	// Transmit Counter Register
-	AT91_REG	 SPI_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 SPI_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 SPI_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 SPI_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 SPI_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 SPI_PTSR; 	// PDC Transfer Status Register
-} AT91S_SPI, *AT91PS_SPI;
-
-// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
-#define AT91C_SPI_SPIEN       ((unsigned int) 0x1 <<  0) // (SPI) SPI Enable
-#define AT91C_SPI_SPIDIS      ((unsigned int) 0x1 <<  1) // (SPI) SPI Disable
-#define AT91C_SPI_SWRST       ((unsigned int) 0x1 <<  7) // (SPI) SPI Software reset
-#define AT91C_SPI_LASTXFER    ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
-// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
-#define AT91C_SPI_MSTR        ((unsigned int) 0x1 <<  0) // (SPI) Master/Slave Mode
-#define AT91C_SPI_PS          ((unsigned int) 0x1 <<  1) // (SPI) Peripheral Select
-#define 	AT91C_SPI_PS_FIXED                ((unsigned int) 0x0 <<  1) // (SPI) Fixed Peripheral Select
-#define 	AT91C_SPI_PS_VARIABLE             ((unsigned int) 0x1 <<  1) // (SPI) Variable Peripheral Select
-#define AT91C_SPI_PCSDEC      ((unsigned int) 0x1 <<  2) // (SPI) Chip Select Decode
-#define AT91C_SPI_FDIV        ((unsigned int) 0x1 <<  3) // (SPI) Clock Selection
-#define AT91C_SPI_MODFDIS     ((unsigned int) 0x1 <<  4) // (SPI) Mode Fault Detection
-#define AT91C_SPI_LLB         ((unsigned int) 0x1 <<  7) // (SPI) Clock Selection
-#define AT91C_SPI_PCS         ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
-#define AT91C_SPI_DLYBCS      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
-// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
-#define AT91C_SPI_RD          ((unsigned int) 0xFFFF <<  0) // (SPI) Receive Data
-#define AT91C_SPI_RPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
-#define AT91C_SPI_TD          ((unsigned int) 0xFFFF <<  0) // (SPI) Transmit Data
-#define AT91C_SPI_TPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
-#define AT91C_SPI_RDRF        ((unsigned int) 0x1 <<  0) // (SPI) Receive Data Register Full
-#define AT91C_SPI_TDRE        ((unsigned int) 0x1 <<  1) // (SPI) Transmit Data Register Empty
-#define AT91C_SPI_MODF        ((unsigned int) 0x1 <<  2) // (SPI) Mode Fault Error
-#define AT91C_SPI_OVRES       ((unsigned int) 0x1 <<  3) // (SPI) Overrun Error Status
-#define AT91C_SPI_ENDRX       ((unsigned int) 0x1 <<  4) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_ENDTX       ((unsigned int) 0x1 <<  5) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_RXBUFF      ((unsigned int) 0x1 <<  6) // (SPI) RXBUFF Interrupt
-#define AT91C_SPI_TXBUFE      ((unsigned int) 0x1 <<  7) // (SPI) TXBUFE Interrupt
-#define AT91C_SPI_NSSR        ((unsigned int) 0x1 <<  8) // (SPI) NSSR Interrupt
-#define AT91C_SPI_TXEMPTY     ((unsigned int) 0x1 <<  9) // (SPI) TXEMPTY Interrupt
-#define AT91C_SPI_SPIENS      ((unsigned int) 0x1 << 16) // (SPI) Enable Status
-// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
-// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
-// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
-// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
-#define AT91C_SPI_CPOL        ((unsigned int) 0x1 <<  0) // (SPI) Clock Polarity
-#define AT91C_SPI_NCPHA       ((unsigned int) 0x1 <<  1) // (SPI) Clock Phase
-#define AT91C_SPI_CSAAT       ((unsigned int) 0x1 <<  3) // (SPI) Chip Select Active After Transfer
-#define AT91C_SPI_BITS        ((unsigned int) 0xF <<  4) // (SPI) Bits Per Transfer
-#define 	AT91C_SPI_BITS_8                    ((unsigned int) 0x0 <<  4) // (SPI) 8 Bits Per transfer
-#define 	AT91C_SPI_BITS_9                    ((unsigned int) 0x1 <<  4) // (SPI) 9 Bits Per transfer
-#define 	AT91C_SPI_BITS_10                   ((unsigned int) 0x2 <<  4) // (SPI) 10 Bits Per transfer
-#define 	AT91C_SPI_BITS_11                   ((unsigned int) 0x3 <<  4) // (SPI) 11 Bits Per transfer
-#define 	AT91C_SPI_BITS_12                   ((unsigned int) 0x4 <<  4) // (SPI) 12 Bits Per transfer
-#define 	AT91C_SPI_BITS_13                   ((unsigned int) 0x5 <<  4) // (SPI) 13 Bits Per transfer
-#define 	AT91C_SPI_BITS_14                   ((unsigned int) 0x6 <<  4) // (SPI) 14 Bits Per transfer
-#define 	AT91C_SPI_BITS_15                   ((unsigned int) 0x7 <<  4) // (SPI) 15 Bits Per transfer
-#define 	AT91C_SPI_BITS_16                   ((unsigned int) 0x8 <<  4) // (SPI) 16 Bits Per transfer
-#define AT91C_SPI_SCBR        ((unsigned int) 0xFF <<  8) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBS       ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK
-#define AT91C_SPI_DLYBCT      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Usart
-// *****************************************************************************
-typedef struct _AT91S_USART {
-	AT91_REG	 US_CR; 	// Control Register
-	AT91_REG	 US_MR; 	// Mode Register
-	AT91_REG	 US_IER; 	// Interrupt Enable Register
-	AT91_REG	 US_IDR; 	// Interrupt Disable Register
-	AT91_REG	 US_IMR; 	// Interrupt Mask Register
-	AT91_REG	 US_CSR; 	// Channel Status Register
-	AT91_REG	 US_RHR; 	// Receiver Holding Register
-	AT91_REG	 US_THR; 	// Transmitter Holding Register
-	AT91_REG	 US_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 US_RTOR; 	// Receiver Time-out Register
-	AT91_REG	 US_TTGR; 	// Transmitter Time-guard Register
-	AT91_REG	 Reserved0[5]; 	// 
-	AT91_REG	 US_FIDI; 	// FI_DI_Ratio Register
-	AT91_REG	 US_NER; 	// Nb Errors Register
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 US_IF; 	// IRDA_FILTER Register
-	AT91_REG	 Reserved2[44]; 	// 
-	AT91_REG	 US_RPR; 	// Receive Pointer Register
-	AT91_REG	 US_RCR; 	// Receive Counter Register
-	AT91_REG	 US_TPR; 	// Transmit Pointer Register
-	AT91_REG	 US_TCR; 	// Transmit Counter Register
-	AT91_REG	 US_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 US_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 US_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 US_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 US_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 US_PTSR; 	// PDC Transfer Status Register
-} AT91S_USART, *AT91PS_USART;
-
-// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
-#define AT91C_US_STTBRK       ((unsigned int) 0x1 <<  9) // (USART) Start Break
-#define AT91C_US_STPBRK       ((unsigned int) 0x1 << 10) // (USART) Stop Break
-#define AT91C_US_STTTO        ((unsigned int) 0x1 << 11) // (USART) Start Time-out
-#define AT91C_US_SENDA        ((unsigned int) 0x1 << 12) // (USART) Send Address
-#define AT91C_US_RSTIT        ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
-#define AT91C_US_RSTNACK      ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
-#define AT91C_US_RETTO        ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
-#define AT91C_US_DTREN        ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
-#define AT91C_US_DTRDIS       ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
-#define AT91C_US_RTSEN        ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
-#define AT91C_US_RTSDIS       ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
-// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
-#define AT91C_US_USMODE       ((unsigned int) 0xF <<  0) // (USART) Usart mode
-#define 	AT91C_US_USMODE_NORMAL               ((unsigned int) 0x0) // (USART) Normal
-#define 	AT91C_US_USMODE_RS485                ((unsigned int) 0x1) // (USART) RS485
-#define 	AT91C_US_USMODE_HWHSH                ((unsigned int) 0x2) // (USART) Hardware Handshaking
-#define 	AT91C_US_USMODE_MODEM                ((unsigned int) 0x3) // (USART) Modem
-#define 	AT91C_US_USMODE_ISO7816_0            ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
-#define 	AT91C_US_USMODE_ISO7816_1            ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
-#define 	AT91C_US_USMODE_IRDA                 ((unsigned int) 0x8) // (USART) IrDA
-#define 	AT91C_US_USMODE_SWHSH                ((unsigned int) 0xC) // (USART) Software Handshaking
-#define AT91C_US_CLKS         ((unsigned int) 0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define 	AT91C_US_CLKS_CLOCK                ((unsigned int) 0x0 <<  4) // (USART) Clock
-#define 	AT91C_US_CLKS_FDIV1                ((unsigned int) 0x1 <<  4) // (USART) fdiv1
-#define 	AT91C_US_CLKS_SLOW                 ((unsigned int) 0x2 <<  4) // (USART) slow_clock (ARM)
-#define 	AT91C_US_CLKS_EXT                  ((unsigned int) 0x3 <<  4) // (USART) External (SCK)
-#define AT91C_US_CHRL         ((unsigned int) 0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define 	AT91C_US_CHRL_5_BITS               ((unsigned int) 0x0 <<  6) // (USART) Character Length: 5 bits
-#define 	AT91C_US_CHRL_6_BITS               ((unsigned int) 0x1 <<  6) // (USART) Character Length: 6 bits
-#define 	AT91C_US_CHRL_7_BITS               ((unsigned int) 0x2 <<  6) // (USART) Character Length: 7 bits
-#define 	AT91C_US_CHRL_8_BITS               ((unsigned int) 0x3 <<  6) // (USART) Character Length: 8 bits
-#define AT91C_US_SYNC         ((unsigned int) 0x1 <<  8) // (USART) Synchronous Mode Select
-#define AT91C_US_NBSTOP       ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
-#define 	AT91C_US_NBSTOP_1_BIT                ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
-#define 	AT91C_US_NBSTOP_15_BIT               ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-#define 	AT91C_US_NBSTOP_2_BIT                ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
-#define AT91C_US_MSBF         ((unsigned int) 0x1 << 16) // (USART) Bit Order
-#define AT91C_US_MODE9        ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
-#define AT91C_US_CKLO         ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
-#define AT91C_US_OVER         ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
-#define AT91C_US_INACK        ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
-#define AT91C_US_DSNACK       ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
-#define AT91C_US_MAX_ITER     ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
-#define AT91C_US_FILTER       ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
-// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
-#define AT91C_US_RXBRK        ((unsigned int) 0x1 <<  2) // (USART) Break Received/End of Break
-#define AT91C_US_TIMEOUT      ((unsigned int) 0x1 <<  8) // (USART) Receiver Time-out
-#define AT91C_US_ITERATION    ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
-#define AT91C_US_NACK         ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
-#define AT91C_US_RIIC         ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
-#define AT91C_US_DSRIC        ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
-#define AT91C_US_DCDIC        ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
-#define AT91C_US_CTSIC        ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
-// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
-// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
-// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
-#define AT91C_US_RI           ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
-#define AT91C_US_DSR          ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
-#define AT91C_US_DCD          ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
-#define AT91C_US_CTS          ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_SSC {
-	AT91_REG	 SSC_CR; 	// Control Register
-	AT91_REG	 SSC_CMR; 	// Clock Mode Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 SSC_RCMR; 	// Receive Clock ModeRegister
-	AT91_REG	 SSC_RFMR; 	// Receive Frame Mode Register
-	AT91_REG	 SSC_TCMR; 	// Transmit Clock Mode Register
-	AT91_REG	 SSC_TFMR; 	// Transmit Frame Mode Register
-	AT91_REG	 SSC_RHR; 	// Receive Holding Register
-	AT91_REG	 SSC_THR; 	// Transmit Holding Register
-	AT91_REG	 Reserved1[2]; 	// 
-	AT91_REG	 SSC_RSHR; 	// Receive Sync Holding Register
-	AT91_REG	 SSC_TSHR; 	// Transmit Sync Holding Register
-	AT91_REG	 Reserved2[2]; 	// 
-	AT91_REG	 SSC_SR; 	// Status Register
-	AT91_REG	 SSC_IER; 	// Interrupt Enable Register
-	AT91_REG	 SSC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 SSC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved3[44]; 	// 
-	AT91_REG	 SSC_RPR; 	// Receive Pointer Register
-	AT91_REG	 SSC_RCR; 	// Receive Counter Register
-	AT91_REG	 SSC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 SSC_TCR; 	// Transmit Counter Register
-	AT91_REG	 SSC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 SSC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 SSC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 SSC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 SSC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 SSC_PTSR; 	// PDC Transfer Status Register
-} AT91S_SSC, *AT91PS_SSC;
-
-// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
-#define AT91C_SSC_RXEN        ((unsigned int) 0x1 <<  0) // (SSC) Receive Enable
-#define AT91C_SSC_RXDIS       ((unsigned int) 0x1 <<  1) // (SSC) Receive Disable
-#define AT91C_SSC_TXEN        ((unsigned int) 0x1 <<  8) // (SSC) Transmit Enable
-#define AT91C_SSC_TXDIS       ((unsigned int) 0x1 <<  9) // (SSC) Transmit Disable
-#define AT91C_SSC_SWRST       ((unsigned int) 0x1 << 15) // (SSC) Software Reset
-// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
-#define AT91C_SSC_CKS         ((unsigned int) 0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
-#define 	AT91C_SSC_CKS_DIV                  ((unsigned int) 0x0) // (SSC) Divided Clock
-#define 	AT91C_SSC_CKS_TK                   ((unsigned int) 0x1) // (SSC) TK Clock signal
-#define 	AT91C_SSC_CKS_RK                   ((unsigned int) 0x2) // (SSC) RK pin
-#define AT91C_SSC_CKO         ((unsigned int) 0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
-#define 	AT91C_SSC_CKO_NONE                 ((unsigned int) 0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-#define 	AT91C_SSC_CKO_CONTINOUS            ((unsigned int) 0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
-#define 	AT91C_SSC_CKO_DATA_TX              ((unsigned int) 0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-#define AT91C_SSC_CKI         ((unsigned int) 0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
-#define AT91C_SSC_START       ((unsigned int) 0xF <<  8) // (SSC) Receive/Transmit Start Selection
-#define 	AT91C_SSC_START_CONTINOUS            ((unsigned int) 0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-#define 	AT91C_SSC_START_TX                   ((unsigned int) 0x1 <<  8) // (SSC) Transmit/Receive start
-#define 	AT91C_SSC_START_LOW_RF               ((unsigned int) 0x2 <<  8) // (SSC) Detection of a low level on RF input
-#define 	AT91C_SSC_START_HIGH_RF              ((unsigned int) 0x3 <<  8) // (SSC) Detection of a high level on RF input
-#define 	AT91C_SSC_START_FALL_RF              ((unsigned int) 0x4 <<  8) // (SSC) Detection of a falling edge on RF input
-#define 	AT91C_SSC_START_RISE_RF              ((unsigned int) 0x5 <<  8) // (SSC) Detection of a rising edge on RF input
-#define 	AT91C_SSC_START_LEVEL_RF             ((unsigned int) 0x6 <<  8) // (SSC) Detection of any level change on RF input
-#define 	AT91C_SSC_START_EDGE_RF              ((unsigned int) 0x7 <<  8) // (SSC) Detection of any edge on RF input
-#define 	AT91C_SSC_START_0                    ((unsigned int) 0x8 <<  8) // (SSC) Compare 0
-#define AT91C_SSC_STTDLY      ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
-#define AT91C_SSC_PERIOD      ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
-// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
-#define AT91C_SSC_DATLEN      ((unsigned int) 0x1F <<  0) // (SSC) Data Length
-#define AT91C_SSC_LOOP        ((unsigned int) 0x1 <<  5) // (SSC) Loop Mode
-#define AT91C_SSC_MSBF        ((unsigned int) 0x1 <<  7) // (SSC) Most Significant Bit First
-#define AT91C_SSC_DATNB       ((unsigned int) 0xF <<  8) // (SSC) Data Number per Frame
-#define AT91C_SSC_FSLEN       ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
-#define AT91C_SSC_FSOS        ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
-#define 	AT91C_SSC_FSOS_NONE                 ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-#define 	AT91C_SSC_FSOS_NEGATIVE             ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-#define 	AT91C_SSC_FSOS_POSITIVE             ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-#define 	AT91C_SSC_FSOS_LOW                  ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-#define 	AT91C_SSC_FSOS_HIGH                 ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-#define 	AT91C_SSC_FSOS_TOGGLE               ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-#define AT91C_SSC_FSEDGE      ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
-// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
-// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
-#define AT91C_SSC_DATDEF      ((unsigned int) 0x1 <<  5) // (SSC) Data Default Value
-#define AT91C_SSC_FSDEN       ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
-// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
-#define AT91C_SSC_TXRDY       ((unsigned int) 0x1 <<  0) // (SSC) Transmit Ready
-#define AT91C_SSC_TXEMPTY     ((unsigned int) 0x1 <<  1) // (SSC) Transmit Empty
-#define AT91C_SSC_ENDTX       ((unsigned int) 0x1 <<  2) // (SSC) End Of Transmission
-#define AT91C_SSC_TXBUFE      ((unsigned int) 0x1 <<  3) // (SSC) Transmit Buffer Empty
-#define AT91C_SSC_RXRDY       ((unsigned int) 0x1 <<  4) // (SSC) Receive Ready
-#define AT91C_SSC_OVRUN       ((unsigned int) 0x1 <<  5) // (SSC) Receive Overrun
-#define AT91C_SSC_ENDRX       ((unsigned int) 0x1 <<  6) // (SSC) End of Reception
-#define AT91C_SSC_RXBUFF      ((unsigned int) 0x1 <<  7) // (SSC) Receive Buffer Full
-#define AT91C_SSC_TXSYN       ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
-#define AT91C_SSC_RXSYN       ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
-#define AT91C_SSC_TXENA       ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
-#define AT91C_SSC_RXENA       ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
-// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
-// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
-// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Two-wire Interface
-// *****************************************************************************
-typedef struct _AT91S_TWI {
-	AT91_REG	 TWI_CR; 	// Control Register
-	AT91_REG	 TWI_MMR; 	// Master Mode Register
-	AT91_REG	 Reserved0[1]; 	// 
-	AT91_REG	 TWI_IADR; 	// Internal Address Register
-	AT91_REG	 TWI_CWGR; 	// Clock Waveform Generator Register
-	AT91_REG	 Reserved1[3]; 	// 
-	AT91_REG	 TWI_SR; 	// Status Register
-	AT91_REG	 TWI_IER; 	// Interrupt Enable Register
-	AT91_REG	 TWI_IDR; 	// Interrupt Disable Register
-	AT91_REG	 TWI_IMR; 	// Interrupt Mask Register
-	AT91_REG	 TWI_RHR; 	// Receive Holding Register
-	AT91_REG	 TWI_THR; 	// Transmit Holding Register
-} AT91S_TWI, *AT91PS_TWI;
-
-// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
-#define AT91C_TWI_START       ((unsigned int) 0x1 <<  0) // (TWI) Send a START Condition
-#define AT91C_TWI_STOP        ((unsigned int) 0x1 <<  1) // (TWI) Send a STOP Condition
-#define AT91C_TWI_MSEN        ((unsigned int) 0x1 <<  2) // (TWI) TWI Master Transfer Enabled
-#define AT91C_TWI_MSDIS       ((unsigned int) 0x1 <<  3) // (TWI) TWI Master Transfer Disabled
-#define AT91C_TWI_SWRST       ((unsigned int) 0x1 <<  7) // (TWI) Software Reset
-// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
-#define AT91C_TWI_IADRSZ      ((unsigned int) 0x3 <<  8) // (TWI) Internal Device Address Size
-#define 	AT91C_TWI_IADRSZ_NO                   ((unsigned int) 0x0 <<  8) // (TWI) No internal device address
-#define 	AT91C_TWI_IADRSZ_1_BYTE               ((unsigned int) 0x1 <<  8) // (TWI) One-byte internal device address
-#define 	AT91C_TWI_IADRSZ_2_BYTE               ((unsigned int) 0x2 <<  8) // (TWI) Two-byte internal device address
-#define 	AT91C_TWI_IADRSZ_3_BYTE               ((unsigned int) 0x3 <<  8) // (TWI) Three-byte internal device address
-#define AT91C_TWI_MREAD       ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
-#define AT91C_TWI_DADR        ((unsigned int) 0x7F << 16) // (TWI) Device Address
-// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
-#define AT91C_TWI_CLDIV       ((unsigned int) 0xFF <<  0) // (TWI) Clock Low Divider
-#define AT91C_TWI_CHDIV       ((unsigned int) 0xFF <<  8) // (TWI) Clock High Divider
-#define AT91C_TWI_CKDIV       ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
-// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
-#define AT91C_TWI_TXCOMP      ((unsigned int) 0x1 <<  0) // (TWI) Transmission Completed
-#define AT91C_TWI_RXRDY       ((unsigned int) 0x1 <<  1) // (TWI) Receive holding register ReaDY
-#define AT91C_TWI_TXRDY       ((unsigned int) 0x1 <<  2) // (TWI) Transmit holding register ReaDY
-#define AT91C_TWI_OVRE        ((unsigned int) 0x1 <<  6) // (TWI) Overrun Error
-#define AT91C_TWI_UNRE        ((unsigned int) 0x1 <<  7) // (TWI) Underrun Error
-#define AT91C_TWI_NACK        ((unsigned int) 0x1 <<  8) // (TWI) Not Acknowledged
-// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
-// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
-// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
-// *****************************************************************************
-typedef struct _AT91S_PWMC_CH {
-	AT91_REG	 PWMC_CMR; 	// Channel Mode Register
-	AT91_REG	 PWMC_CDTYR; 	// Channel Duty Cycle Register
-	AT91_REG	 PWMC_CPRDR; 	// Channel Period Register
-	AT91_REG	 PWMC_CCNTR; 	// Channel Counter Register
-	AT91_REG	 PWMC_CUPDR; 	// Channel Update Register
-	AT91_REG	 PWMC_Reserved[3]; 	// Reserved
-} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
-
-// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- 
-#define AT91C_PWMC_CPRE       ((unsigned int) 0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
-#define 	AT91C_PWMC_CPRE_MCK                  ((unsigned int) 0x0) // (PWMC_CH) 
-#define 	AT91C_PWMC_CPRE_MCKA                 ((unsigned int) 0xB) // (PWMC_CH) 
-#define 	AT91C_PWMC_CPRE_MCKB                 ((unsigned int) 0xC) // (PWMC_CH) 
-#define AT91C_PWMC_CALG       ((unsigned int) 0x1 <<  8) // (PWMC_CH) Channel Alignment
-#define AT91C_PWMC_CPOL       ((unsigned int) 0x1 <<  9) // (PWMC_CH) Channel Polarity
-#define AT91C_PWMC_CPD        ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
-// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- 
-#define AT91C_PWMC_CDTY       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
-// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- 
-#define AT91C_PWMC_CPRD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Period
-// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- 
-#define AT91C_PWMC_CCNT       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Counter
-// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- 
-#define AT91C_PWMC_CUPD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Update
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_PWMC {
-	AT91_REG	 PWMC_MR; 	// PWMC Mode Register
-	AT91_REG	 PWMC_ENA; 	// PWMC Enable Register
-	AT91_REG	 PWMC_DIS; 	// PWMC Disable Register
-	AT91_REG	 PWMC_SR; 	// PWMC Status Register
-	AT91_REG	 PWMC_IER; 	// PWMC Interrupt Enable Register
-	AT91_REG	 PWMC_IDR; 	// PWMC Interrupt Disable Register
-	AT91_REG	 PWMC_IMR; 	// PWMC Interrupt Mask Register
-	AT91_REG	 PWMC_ISR; 	// PWMC Interrupt Status Register
-	AT91_REG	 Reserved0[55]; 	// 
-	AT91_REG	 PWMC_VR; 	// PWMC Version Register
-	AT91_REG	 Reserved1[64]; 	// 
-	AT91S_PWMC_CH	 PWMC_CH[4]; 	// PWMC Channel
-} AT91S_PWMC, *AT91PS_PWMC;
-
-// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- 
-#define AT91C_PWMC_DIVA       ((unsigned int) 0xFF <<  0) // (PWMC) CLKA divide factor.
-#define AT91C_PWMC_PREA       ((unsigned int) 0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
-#define 	AT91C_PWMC_PREA_MCK                  ((unsigned int) 0x0 <<  8) // (PWMC) 
-#define AT91C_PWMC_DIVB       ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
-#define AT91C_PWMC_PREB       ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
-#define 	AT91C_PWMC_PREB_MCK                  ((unsigned int) 0x0 << 24) // (PWMC) 
-// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- 
-#define AT91C_PWMC_CHID0      ((unsigned int) 0x1 <<  0) // (PWMC) Channel ID 0
-#define AT91C_PWMC_CHID1      ((unsigned int) 0x1 <<  1) // (PWMC) Channel ID 1
-#define AT91C_PWMC_CHID2      ((unsigned int) 0x1 <<  2) // (PWMC) Channel ID 2
-#define AT91C_PWMC_CHID3      ((unsigned int) 0x1 <<  3) // (PWMC) Channel ID 3
-// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- 
-// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- 
-// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- 
-// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- 
-// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- 
-// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR USB Device Interface
-// *****************************************************************************
-typedef struct _AT91S_UDP {
-	AT91_REG	 UDP_NUM; 	// Frame Number Register
-	AT91_REG	 UDP_GLBSTATE; 	// Global State Register
-	AT91_REG	 UDP_FADDR; 	// Function Address Register
-	AT91_REG	 Reserved0[1]; 	// 
-	AT91_REG	 UDP_IER; 	// Interrupt Enable Register
-	AT91_REG	 UDP_IDR; 	// Interrupt Disable Register
-	AT91_REG	 UDP_IMR; 	// Interrupt Mask Register
-	AT91_REG	 UDP_ISR; 	// Interrupt Status Register
-	AT91_REG	 UDP_ICR; 	// Interrupt Clear Register
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 UDP_RSTEP; 	// Reset Endpoint Register
-	AT91_REG	 Reserved2[1]; 	// 
-	AT91_REG	 UDP_CSR[6]; 	// Endpoint Control and Status Register
-	AT91_REG	 Reserved3[2]; 	// 
-	AT91_REG	 UDP_FDR[6]; 	// Endpoint FIFO Data Register
-	AT91_REG	 Reserved4[3]; 	// 
-	AT91_REG	 UDP_TXVC; 	// Transceiver Control Register
-} AT91S_UDP, *AT91PS_UDP;
-
-// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
-#define AT91C_UDP_FRM_NUM     ((unsigned int) 0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
-#define AT91C_UDP_FRM_ERR     ((unsigned int) 0x1 << 16) // (UDP) Frame Error
-#define AT91C_UDP_FRM_OK      ((unsigned int) 0x1 << 17) // (UDP) Frame OK
-// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
-#define AT91C_UDP_FADDEN      ((unsigned int) 0x1 <<  0) // (UDP) Function Address Enable
-#define AT91C_UDP_CONFG       ((unsigned int) 0x1 <<  1) // (UDP) Configured
-#define AT91C_UDP_ESR         ((unsigned int) 0x1 <<  2) // (UDP) Enable Send Resume
-#define AT91C_UDP_RSMINPR     ((unsigned int) 0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
-#define AT91C_UDP_RMWUPE      ((unsigned int) 0x1 <<  4) // (UDP) Remote Wake Up Enable
-// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
-#define AT91C_UDP_FADD        ((unsigned int) 0xFF <<  0) // (UDP) Function Address Value
-#define AT91C_UDP_FEN         ((unsigned int) 0x1 <<  8) // (UDP) Function Enable
-// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
-#define AT91C_UDP_EPINT0      ((unsigned int) 0x1 <<  0) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT1      ((unsigned int) 0x1 <<  1) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT2      ((unsigned int) 0x1 <<  2) // (UDP) Endpoint 2 Interrupt
-#define AT91C_UDP_EPINT3      ((unsigned int) 0x1 <<  3) // (UDP) Endpoint 3 Interrupt
-#define AT91C_UDP_EPINT4      ((unsigned int) 0x1 <<  4) // (UDP) Endpoint 4 Interrupt
-#define AT91C_UDP_EPINT5      ((unsigned int) 0x1 <<  5) // (UDP) Endpoint 5 Interrupt
-#define AT91C_UDP_RXSUSP      ((unsigned int) 0x1 <<  8) // (UDP) USB Suspend Interrupt
-#define AT91C_UDP_RXRSM       ((unsigned int) 0x1 <<  9) // (UDP) USB Resume Interrupt
-#define AT91C_UDP_EXTRSM      ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
-#define AT91C_UDP_SOFINT      ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
-#define AT91C_UDP_WAKEUP      ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
-// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
-// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
-// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
-#define AT91C_UDP_ENDBUSRES   ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
-// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
-// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
-#define AT91C_UDP_EP0         ((unsigned int) 0x1 <<  0) // (UDP) Reset Endpoint 0
-#define AT91C_UDP_EP1         ((unsigned int) 0x1 <<  1) // (UDP) Reset Endpoint 1
-#define AT91C_UDP_EP2         ((unsigned int) 0x1 <<  2) // (UDP) Reset Endpoint 2
-#define AT91C_UDP_EP3         ((unsigned int) 0x1 <<  3) // (UDP) Reset Endpoint 3
-#define AT91C_UDP_EP4         ((unsigned int) 0x1 <<  4) // (UDP) Reset Endpoint 4
-#define AT91C_UDP_EP5         ((unsigned int) 0x1 <<  5) // (UDP) Reset Endpoint 5
-// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
-#define AT91C_UDP_TXCOMP      ((unsigned int) 0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
-#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 <<  1) // (UDP) Receive Data Bank 0
-#define AT91C_UDP_RXSETUP     ((unsigned int) 0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
-#define AT91C_UDP_ISOERROR    ((unsigned int) 0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
-#define AT91C_UDP_TXPKTRDY    ((unsigned int) 0x1 <<  4) // (UDP) Transmit Packet Ready
-#define AT91C_UDP_FORCESTALL  ((unsigned int) 0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-#define AT91C_UDP_DIR         ((unsigned int) 0x1 <<  7) // (UDP) Transfer Direction
-#define AT91C_UDP_EPTYPE      ((unsigned int) 0x7 <<  8) // (UDP) Endpoint type
-#define 	AT91C_UDP_EPTYPE_CTRL                 ((unsigned int) 0x0 <<  8) // (UDP) Control
-#define 	AT91C_UDP_EPTYPE_ISO_OUT              ((unsigned int) 0x1 <<  8) // (UDP) Isochronous OUT
-#define 	AT91C_UDP_EPTYPE_BULK_OUT             ((unsigned int) 0x2 <<  8) // (UDP) Bulk OUT
-#define 	AT91C_UDP_EPTYPE_INT_OUT              ((unsigned int) 0x3 <<  8) // (UDP) Interrupt OUT
-#define 	AT91C_UDP_EPTYPE_ISO_IN               ((unsigned int) 0x5 <<  8) // (UDP) Isochronous IN
-#define 	AT91C_UDP_EPTYPE_BULK_IN              ((unsigned int) 0x6 <<  8) // (UDP) Bulk IN
-#define 	AT91C_UDP_EPTYPE_INT_IN               ((unsigned int) 0x7 <<  8) // (UDP) Interrupt IN
-#define AT91C_UDP_DTGLE       ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
-#define AT91C_UDP_EPEDS       ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
-#define AT91C_UDP_RXBYTECNT   ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
-// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- 
-#define AT91C_UDP_TXVDIS      ((unsigned int) 0x1 <<  8) // (UDP) 
-#define AT91C_UDP_PUON        ((unsigned int) 0x1 <<  9) // (UDP) Pull-up ON
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
-// *****************************************************************************
-typedef struct _AT91S_TC {
-	AT91_REG	 TC_CCR; 	// Channel Control Register
-	AT91_REG	 TC_CMR; 	// Channel Mode Register (Capture Mode / Waveform Mode)
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 TC_CV; 	// Counter Value
-	AT91_REG	 TC_RA; 	// Register A
-	AT91_REG	 TC_RB; 	// Register B
-	AT91_REG	 TC_RC; 	// Register C
-	AT91_REG	 TC_SR; 	// Status Register
-	AT91_REG	 TC_IER; 	// Interrupt Enable Register
-	AT91_REG	 TC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 TC_IMR; 	// Interrupt Mask Register
-} AT91S_TC, *AT91PS_TC;
-
-// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
-#define AT91C_TC_CLKEN        ((unsigned int) 0x1 <<  0) // (TC) Counter Clock Enable Command
-#define AT91C_TC_CLKDIS       ((unsigned int) 0x1 <<  1) // (TC) Counter Clock Disable Command
-#define AT91C_TC_SWTRG        ((unsigned int) 0x1 <<  2) // (TC) Software Trigger Command
-// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
-#define AT91C_TC_CLKS         ((unsigned int) 0x7 <<  0) // (TC) Clock Selection
-#define 	AT91C_TC_CLKS_TIMER_DIV1_CLOCK     ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV2_CLOCK     ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV3_CLOCK     ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV4_CLOCK     ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV5_CLOCK     ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
-#define 	AT91C_TC_CLKS_XC0                  ((unsigned int) 0x5) // (TC) Clock selected: XC0
-#define 	AT91C_TC_CLKS_XC1                  ((unsigned int) 0x6) // (TC) Clock selected: XC1
-#define 	AT91C_TC_CLKS_XC2                  ((unsigned int) 0x7) // (TC) Clock selected: XC2
-#define AT91C_TC_CLKI         ((unsigned int) 0x1 <<  3) // (TC) Clock Invert
-#define AT91C_TC_BURST        ((unsigned int) 0x3 <<  4) // (TC) Burst Signal Selection
-#define 	AT91C_TC_BURST_NONE                 ((unsigned int) 0x0 <<  4) // (TC) The clock is not gated by an external signal
-#define 	AT91C_TC_BURST_XC0                  ((unsigned int) 0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
-#define 	AT91C_TC_BURST_XC1                  ((unsigned int) 0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
-#define 	AT91C_TC_BURST_XC2                  ((unsigned int) 0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
-#define AT91C_TC_CPCSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
-#define AT91C_TC_LDBSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
-#define AT91C_TC_CPCDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
-#define AT91C_TC_LDBDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
-#define AT91C_TC_ETRGEDG      ((unsigned int) 0x3 <<  8) // (TC) External Trigger Edge Selection
-#define 	AT91C_TC_ETRGEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
-#define 	AT91C_TC_ETRGEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
-#define 	AT91C_TC_ETRGEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
-#define 	AT91C_TC_ETRGEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVTEDG      ((unsigned int) 0x3 <<  8) // (TC) External Event Edge Selection
-#define 	AT91C_TC_EEVTEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
-#define 	AT91C_TC_EEVTEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
-#define 	AT91C_TC_EEVTEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
-#define 	AT91C_TC_EEVTEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVT         ((unsigned int) 0x3 << 10) // (TC) External Event  Selection
-#define 	AT91C_TC_EEVT_TIOB                 ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
-#define 	AT91C_TC_EEVT_XC0                  ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
-#define 	AT91C_TC_EEVT_XC1                  ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
-#define 	AT91C_TC_EEVT_XC2                  ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
-#define AT91C_TC_ABETRG       ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
-#define AT91C_TC_ENETRG       ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
-#define AT91C_TC_WAVESEL      ((unsigned int) 0x3 << 13) // (TC) Waveform  Selection
-#define 	AT91C_TC_WAVESEL_UP                   ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UPDOWN               ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UP_AUTO              ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
-#define AT91C_TC_CPCTRG       ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
-#define AT91C_TC_WAVE         ((unsigned int) 0x1 << 15) // (TC) 
-#define AT91C_TC_ACPA         ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
-#define 	AT91C_TC_ACPA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Effect: none
-#define 	AT91C_TC_ACPA_SET                  ((unsigned int) 0x1 << 16) // (TC) Effect: set
-#define 	AT91C_TC_ACPA_CLEAR                ((unsigned int) 0x2 << 16) // (TC) Effect: clear
-#define 	AT91C_TC_ACPA_TOGGLE               ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
-#define AT91C_TC_LDRA         ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
-#define 	AT91C_TC_LDRA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Edge: None
-#define 	AT91C_TC_LDRA_RISING               ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
-#define 	AT91C_TC_LDRA_FALLING              ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
-#define 	AT91C_TC_LDRA_BOTH                 ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_ACPC         ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
-#define 	AT91C_TC_ACPC_NONE                 ((unsigned int) 0x0 << 18) // (TC) Effect: none
-#define 	AT91C_TC_ACPC_SET                  ((unsigned int) 0x1 << 18) // (TC) Effect: set
-#define 	AT91C_TC_ACPC_CLEAR                ((unsigned int) 0x2 << 18) // (TC) Effect: clear
-#define 	AT91C_TC_ACPC_TOGGLE               ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
-#define AT91C_TC_LDRB         ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
-#define 	AT91C_TC_LDRB_NONE                 ((unsigned int) 0x0 << 18) // (TC) Edge: None
-#define 	AT91C_TC_LDRB_RISING               ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
-#define 	AT91C_TC_LDRB_FALLING              ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
-#define 	AT91C_TC_LDRB_BOTH                 ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_AEEVT        ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
-#define 	AT91C_TC_AEEVT_NONE                 ((unsigned int) 0x0 << 20) // (TC) Effect: none
-#define 	AT91C_TC_AEEVT_SET                  ((unsigned int) 0x1 << 20) // (TC) Effect: set
-#define 	AT91C_TC_AEEVT_CLEAR                ((unsigned int) 0x2 << 20) // (TC) Effect: clear
-#define 	AT91C_TC_AEEVT_TOGGLE               ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
-#define AT91C_TC_ASWTRG       ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
-#define 	AT91C_TC_ASWTRG_NONE                 ((unsigned int) 0x0 << 22) // (TC) Effect: none
-#define 	AT91C_TC_ASWTRG_SET                  ((unsigned int) 0x1 << 22) // (TC) Effect: set
-#define 	AT91C_TC_ASWTRG_CLEAR                ((unsigned int) 0x2 << 22) // (TC) Effect: clear
-#define 	AT91C_TC_ASWTRG_TOGGLE               ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
-#define AT91C_TC_BCPB         ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
-#define 	AT91C_TC_BCPB_NONE                 ((unsigned int) 0x0 << 24) // (TC) Effect: none
-#define 	AT91C_TC_BCPB_SET                  ((unsigned int) 0x1 << 24) // (TC) Effect: set
-#define 	AT91C_TC_BCPB_CLEAR                ((unsigned int) 0x2 << 24) // (TC) Effect: clear
-#define 	AT91C_TC_BCPB_TOGGLE               ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
-#define AT91C_TC_BCPC         ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
-#define 	AT91C_TC_BCPC_NONE                 ((unsigned int) 0x0 << 26) // (TC) Effect: none
-#define 	AT91C_TC_BCPC_SET                  ((unsigned int) 0x1 << 26) // (TC) Effect: set
-#define 	AT91C_TC_BCPC_CLEAR                ((unsigned int) 0x2 << 26) // (TC) Effect: clear
-#define 	AT91C_TC_BCPC_TOGGLE               ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
-#define AT91C_TC_BEEVT        ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
-#define 	AT91C_TC_BEEVT_NONE                 ((unsigned int) 0x0 << 28) // (TC) Effect: none
-#define 	AT91C_TC_BEEVT_SET                  ((unsigned int) 0x1 << 28) // (TC) Effect: set
-#define 	AT91C_TC_BEEVT_CLEAR                ((unsigned int) 0x2 << 28) // (TC) Effect: clear
-#define 	AT91C_TC_BEEVT_TOGGLE               ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
-#define AT91C_TC_BSWTRG       ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
-#define 	AT91C_TC_BSWTRG_NONE                 ((unsigned int) 0x0 << 30) // (TC) Effect: none
-#define 	AT91C_TC_BSWTRG_SET                  ((unsigned int) 0x1 << 30) // (TC) Effect: set
-#define 	AT91C_TC_BSWTRG_CLEAR                ((unsigned int) 0x2 << 30) // (TC) Effect: clear
-#define 	AT91C_TC_BSWTRG_TOGGLE               ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
-// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
-#define AT91C_TC_COVFS        ((unsigned int) 0x1 <<  0) // (TC) Counter Overflow
-#define AT91C_TC_LOVRS        ((unsigned int) 0x1 <<  1) // (TC) Load Overrun
-#define AT91C_TC_CPAS         ((unsigned int) 0x1 <<  2) // (TC) RA Compare
-#define AT91C_TC_CPBS         ((unsigned int) 0x1 <<  3) // (TC) RB Compare
-#define AT91C_TC_CPCS         ((unsigned int) 0x1 <<  4) // (TC) RC Compare
-#define AT91C_TC_LDRAS        ((unsigned int) 0x1 <<  5) // (TC) RA Loading
-#define AT91C_TC_LDRBS        ((unsigned int) 0x1 <<  6) // (TC) RB Loading
-#define AT91C_TC_ETRGS        ((unsigned int) 0x1 <<  7) // (TC) External Trigger
-#define AT91C_TC_CLKSTA       ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
-#define AT91C_TC_MTIOA        ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
-#define AT91C_TC_MTIOB        ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
-// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
-// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
-// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
-// *****************************************************************************
-typedef struct _AT91S_TCB {
-	AT91S_TC	 TCB_TC0; 	// TC Channel 0
-	AT91_REG	 Reserved0[4]; 	// 
-	AT91S_TC	 TCB_TC1; 	// TC Channel 1
-	AT91_REG	 Reserved1[4]; 	// 
-	AT91S_TC	 TCB_TC2; 	// TC Channel 2
-	AT91_REG	 Reserved2[4]; 	// 
-	AT91_REG	 TCB_BCR; 	// TC Block Control Register
-	AT91_REG	 TCB_BMR; 	// TC Block Mode Register
-} AT91S_TCB, *AT91PS_TCB;
-
-// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
-#define AT91C_TCB_SYNC        ((unsigned int) 0x1 <<  0) // (TCB) Synchro Command
-// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
-#define AT91C_TCB_TC0XC0S     ((unsigned int) 0x3 <<  0) // (TCB) External Clock Signal 0 Selection
-#define 	AT91C_TCB_TC0XC0S_TCLK0                ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
-#define 	AT91C_TCB_TC0XC0S_NONE                 ((unsigned int) 0x1) // (TCB) None signal connected to XC0
-#define 	AT91C_TCB_TC0XC0S_TIOA1                ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
-#define 	AT91C_TCB_TC0XC0S_TIOA2                ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
-#define AT91C_TCB_TC1XC1S     ((unsigned int) 0x3 <<  2) // (TCB) External Clock Signal 1 Selection
-#define 	AT91C_TCB_TC1XC1S_TCLK1                ((unsigned int) 0x0 <<  2) // (TCB) TCLK1 connected to XC1
-#define 	AT91C_TCB_TC1XC1S_NONE                 ((unsigned int) 0x1 <<  2) // (TCB) None signal connected to XC1
-#define 	AT91C_TCB_TC1XC1S_TIOA0                ((unsigned int) 0x2 <<  2) // (TCB) TIOA0 connected to XC1
-#define 	AT91C_TCB_TC1XC1S_TIOA2                ((unsigned int) 0x3 <<  2) // (TCB) TIOA2 connected to XC1
-#define AT91C_TCB_TC2XC2S     ((unsigned int) 0x3 <<  4) // (TCB) External Clock Signal 2 Selection
-#define 	AT91C_TCB_TC2XC2S_TCLK2                ((unsigned int) 0x0 <<  4) // (TCB) TCLK2 connected to XC2
-#define 	AT91C_TCB_TC2XC2S_NONE                 ((unsigned int) 0x1 <<  4) // (TCB) None signal connected to XC2
-#define 	AT91C_TCB_TC2XC2S_TIOA0                ((unsigned int) 0x2 <<  4) // (TCB) TIOA0 connected to XC2
-#define 	AT91C_TCB_TC2XC2S_TIOA1                ((unsigned int) 0x3 <<  4) // (TCB) TIOA2 connected to XC2
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface
-// *****************************************************************************
-typedef struct _AT91S_CAN_MB {
-	AT91_REG	 CAN_MB_MMR; 	// MailBox Mode Register
-	AT91_REG	 CAN_MB_MAM; 	// MailBox Acceptance Mask Register
-	AT91_REG	 CAN_MB_MID; 	// MailBox ID Register
-	AT91_REG	 CAN_MB_MFID; 	// MailBox Family ID Register
-	AT91_REG	 CAN_MB_MSR; 	// MailBox Status Register
-	AT91_REG	 CAN_MB_MDL; 	// MailBox Data Low Register
-	AT91_REG	 CAN_MB_MDH; 	// MailBox Data High Register
-	AT91_REG	 CAN_MB_MCR; 	// MailBox Control Register
-} AT91S_CAN_MB, *AT91PS_CAN_MB;
-
-// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- 
-#define AT91C_CAN_MTIMEMARK   ((unsigned int) 0xFFFF <<  0) // (CAN_MB) Mailbox Timemark
-#define AT91C_CAN_PRIOR       ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority
-#define AT91C_CAN_MOT         ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type
-#define 	AT91C_CAN_MOT_DIS                  ((unsigned int) 0x0 << 24) // (CAN_MB) 
-#define 	AT91C_CAN_MOT_RX                   ((unsigned int) 0x1 << 24) // (CAN_MB) 
-#define 	AT91C_CAN_MOT_RXOVERWRITE          ((unsigned int) 0x2 << 24) // (CAN_MB) 
-#define 	AT91C_CAN_MOT_TX                   ((unsigned int) 0x3 << 24) // (CAN_MB) 
-#define 	AT91C_CAN_MOT_CONSUMER             ((unsigned int) 0x4 << 24) // (CAN_MB) 
-#define 	AT91C_CAN_MOT_PRODUCER             ((unsigned int) 0x5 << 24) // (CAN_MB) 
-// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- 
-#define AT91C_CAN_MIDvB       ((unsigned int) 0x3FFFF <<  0) // (CAN_MB) Complementary bits for identifier in extended mode
-#define AT91C_CAN_MIDvA       ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
-#define AT91C_CAN_MIDE        ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version
-// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- 
-// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- 
-// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- 
-#define AT91C_CAN_MTIMESTAMP  ((unsigned int) 0xFFFF <<  0) // (CAN_MB) Timer Value
-#define AT91C_CAN_MDLC        ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code
-#define AT91C_CAN_MRTR        ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
-#define AT91C_CAN_MABT        ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort
-#define AT91C_CAN_MRDY        ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready
-#define AT91C_CAN_MMI         ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored
-// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- 
-// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- 
-// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- 
-#define AT91C_CAN_MACR        ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox
-#define AT91C_CAN_MTCR        ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Control Area Network Interface
-// *****************************************************************************
-typedef struct _AT91S_CAN {
-	AT91_REG	 CAN_MR; 	// Mode Register
-	AT91_REG	 CAN_IER; 	// Interrupt Enable Register
-	AT91_REG	 CAN_IDR; 	// Interrupt Disable Register
-	AT91_REG	 CAN_IMR; 	// Interrupt Mask Register
-	AT91_REG	 CAN_SR; 	// Status Register
-	AT91_REG	 CAN_BR; 	// Baudrate Register
-	AT91_REG	 CAN_TIM; 	// Timer Register
-	AT91_REG	 CAN_TIMESTP; 	// Time Stamp Register
-	AT91_REG	 CAN_ECR; 	// Error Counter Register
-	AT91_REG	 CAN_TCR; 	// Transfer Command Register
-	AT91_REG	 CAN_ACR; 	// Abort Command Register
-	AT91_REG	 Reserved0[52]; 	// 
-	AT91_REG	 CAN_VR; 	// Version Register
-	AT91_REG	 Reserved1[64]; 	// 
-	AT91S_CAN_MB	 CAN_MB0; 	// CAN Mailbox 0
-	AT91S_CAN_MB	 CAN_MB1; 	// CAN Mailbox 1
-	AT91S_CAN_MB	 CAN_MB2; 	// CAN Mailbox 2
-	AT91S_CAN_MB	 CAN_MB3; 	// CAN Mailbox 3
-	AT91S_CAN_MB	 CAN_MB4; 	// CAN Mailbox 4
-	AT91S_CAN_MB	 CAN_MB5; 	// CAN Mailbox 5
-	AT91S_CAN_MB	 CAN_MB6; 	// CAN Mailbox 6
-	AT91S_CAN_MB	 CAN_MB7; 	// CAN Mailbox 7
-	AT91S_CAN_MB	 CAN_MB8; 	// CAN Mailbox 8
-	AT91S_CAN_MB	 CAN_MB9; 	// CAN Mailbox 9
-	AT91S_CAN_MB	 CAN_MB10; 	// CAN Mailbox 10
-	AT91S_CAN_MB	 CAN_MB11; 	// CAN Mailbox 11
-	AT91S_CAN_MB	 CAN_MB12; 	// CAN Mailbox 12
-	AT91S_CAN_MB	 CAN_MB13; 	// CAN Mailbox 13
-	AT91S_CAN_MB	 CAN_MB14; 	// CAN Mailbox 14
-	AT91S_CAN_MB	 CAN_MB15; 	// CAN Mailbox 15
-} AT91S_CAN, *AT91PS_CAN;
-
-// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- 
-#define AT91C_CAN_CANEN       ((unsigned int) 0x1 <<  0) // (CAN) CAN Controller Enable
-#define AT91C_CAN_LPM         ((unsigned int) 0x1 <<  1) // (CAN) Disable/Enable Low Power Mode
-#define AT91C_CAN_ABM         ((unsigned int) 0x1 <<  2) // (CAN) Disable/Enable Autobaud/Listen Mode
-#define AT91C_CAN_OVL         ((unsigned int) 0x1 <<  3) // (CAN) Disable/Enable Overload Frame
-#define AT91C_CAN_TEOF        ((unsigned int) 0x1 <<  4) // (CAN) Time Stamp messages at each end of Frame
-#define AT91C_CAN_TTM         ((unsigned int) 0x1 <<  5) // (CAN) Disable/Enable Time Trigger Mode
-#define AT91C_CAN_TIMFRZ      ((unsigned int) 0x1 <<  6) // (CAN) Enable Timer Freeze
-#define AT91C_CAN_DRPT        ((unsigned int) 0x1 <<  7) // (CAN) Disable Repeat
-// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- 
-#define AT91C_CAN_MB0         ((unsigned int) 0x1 <<  0) // (CAN) Mailbox 0 Flag
-#define AT91C_CAN_MB1         ((unsigned int) 0x1 <<  1) // (CAN) Mailbox 1 Flag
-#define AT91C_CAN_MB2         ((unsigned int) 0x1 <<  2) // (CAN) Mailbox 2 Flag
-#define AT91C_CAN_MB3         ((unsigned int) 0x1 <<  3) // (CAN) Mailbox 3 Flag
-#define AT91C_CAN_MB4         ((unsigned int) 0x1 <<  4) // (CAN) Mailbox 4 Flag
-#define AT91C_CAN_MB5         ((unsigned int) 0x1 <<  5) // (CAN) Mailbox 5 Flag
-#define AT91C_CAN_MB6         ((unsigned int) 0x1 <<  6) // (CAN) Mailbox 6 Flag
-#define AT91C_CAN_MB7         ((unsigned int) 0x1 <<  7) // (CAN) Mailbox 7 Flag
-#define AT91C_CAN_MB8         ((unsigned int) 0x1 <<  8) // (CAN) Mailbox 8 Flag
-#define AT91C_CAN_MB9         ((unsigned int) 0x1 <<  9) // (CAN) Mailbox 9 Flag
-#define AT91C_CAN_MB10        ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag
-#define AT91C_CAN_MB11        ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag
-#define AT91C_CAN_MB12        ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag
-#define AT91C_CAN_MB13        ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag
-#define AT91C_CAN_MB14        ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag
-#define AT91C_CAN_MB15        ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag
-#define AT91C_CAN_ERRA        ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag
-#define AT91C_CAN_WARN        ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag
-#define AT91C_CAN_ERRP        ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag
-#define AT91C_CAN_BOFF        ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag
-#define AT91C_CAN_SLEEP       ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag
-#define AT91C_CAN_WAKEUP      ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag
-#define AT91C_CAN_TOVF        ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag
-#define AT91C_CAN_TSTP        ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag
-#define AT91C_CAN_CERR        ((unsigned int) 0x1 << 24) // (CAN) CRC Error
-#define AT91C_CAN_SERR        ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error
-#define AT91C_CAN_AERR        ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error
-#define AT91C_CAN_FERR        ((unsigned int) 0x1 << 27) // (CAN) Form Error
-#define AT91C_CAN_BERR        ((unsigned int) 0x1 << 28) // (CAN) Bit Error
-// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- 
-// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- 
-// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- 
-#define AT91C_CAN_RBSY        ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy
-#define AT91C_CAN_TBSY        ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy
-#define AT91C_CAN_OVLY        ((unsigned int) 0x1 << 31) // (CAN) Overload Busy
-// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- 
-#define AT91C_CAN_PHASE2      ((unsigned int) 0x7 <<  0) // (CAN) Phase 2 segment
-#define AT91C_CAN_PHASE1      ((unsigned int) 0x7 <<  4) // (CAN) Phase 1 segment
-#define AT91C_CAN_PROPAG      ((unsigned int) 0x7 <<  8) // (CAN) Programmation time segment
-#define AT91C_CAN_SYNC        ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment
-#define AT91C_CAN_BRP         ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler
-#define AT91C_CAN_SMP         ((unsigned int) 0x1 << 24) // (CAN) Sampling mode
-// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- 
-#define AT91C_CAN_TIMER       ((unsigned int) 0xFFFF <<  0) // (CAN) Timer field
-// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- 
-// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- 
-#define AT91C_CAN_REC         ((unsigned int) 0xFF <<  0) // (CAN) Receive Error Counter
-#define AT91C_CAN_TEC         ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter
-// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- 
-#define AT91C_CAN_TIMRST      ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field
-// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
-// *****************************************************************************
-typedef struct _AT91S_EMAC {
-	AT91_REG	 EMAC_NCR; 	// Network Control Register
-	AT91_REG	 EMAC_NCFGR; 	// Network Configuration Register
-	AT91_REG	 EMAC_NSR; 	// Network Status Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 EMAC_TSR; 	// Transmit Status Register
-	AT91_REG	 EMAC_RBQP; 	// Receive Buffer Queue Pointer
-	AT91_REG	 EMAC_TBQP; 	// Transmit Buffer Queue Pointer
-	AT91_REG	 EMAC_RSR; 	// Receive Status Register
-	AT91_REG	 EMAC_ISR; 	// Interrupt Status Register
-	AT91_REG	 EMAC_IER; 	// Interrupt Enable Register
-	AT91_REG	 EMAC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 EMAC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 EMAC_MAN; 	// PHY Maintenance Register
-	AT91_REG	 EMAC_PTR; 	// Pause Time Register
-	AT91_REG	 EMAC_PFR; 	// Pause Frames received Register
-	AT91_REG	 EMAC_FTO; 	// Frames Transmitted OK Register
-	AT91_REG	 EMAC_SCF; 	// Single Collision Frame Register
-	AT91_REG	 EMAC_MCF; 	// Multiple Collision Frame Register
-	AT91_REG	 EMAC_FRO; 	// Frames Received OK Register
-	AT91_REG	 EMAC_FCSE; 	// Frame Check Sequence Error Register
-	AT91_REG	 EMAC_ALE; 	// Alignment Error Register
-	AT91_REG	 EMAC_DTF; 	// Deferred Transmission Frame Register
-	AT91_REG	 EMAC_LCOL; 	// Late Collision Register
-	AT91_REG	 EMAC_ECOL; 	// Excessive Collision Register
-	AT91_REG	 EMAC_TUND; 	// Transmit Underrun Error Register
-	AT91_REG	 EMAC_CSE; 	// Carrier Sense Error Register
-	AT91_REG	 EMAC_RRE; 	// Receive Ressource Error Register
-	AT91_REG	 EMAC_ROV; 	// Receive Overrun Errors Register
-	AT91_REG	 EMAC_RSE; 	// Receive Symbol Errors Register
-	AT91_REG	 EMAC_ELE; 	// Excessive Length Errors Register
-	AT91_REG	 EMAC_RJA; 	// Receive Jabbers Register
-	AT91_REG	 EMAC_USF; 	// Undersize Frames Register
-	AT91_REG	 EMAC_STE; 	// SQE Test Error Register
-	AT91_REG	 EMAC_RLE; 	// Receive Length Field Mismatch Register
-	AT91_REG	 EMAC_TPF; 	// Transmitted Pause Frames Register
-	AT91_REG	 EMAC_HRB; 	// Hash Address Bottom[31:0]
-	AT91_REG	 EMAC_HRT; 	// Hash Address Top[63:32]
-	AT91_REG	 EMAC_SA1L; 	// Specific Address 1 Bottom, First 4 bytes
-	AT91_REG	 EMAC_SA1H; 	// Specific Address 1 Top, Last 2 bytes
-	AT91_REG	 EMAC_SA2L; 	// Specific Address 2 Bottom, First 4 bytes
-	AT91_REG	 EMAC_SA2H; 	// Specific Address 2 Top, Last 2 bytes
-	AT91_REG	 EMAC_SA3L; 	// Specific Address 3 Bottom, First 4 bytes
-	AT91_REG	 EMAC_SA3H; 	// Specific Address 3 Top, Last 2 bytes
-	AT91_REG	 EMAC_SA4L; 	// Specific Address 4 Bottom, First 4 bytes
-	AT91_REG	 EMAC_SA4H; 	// Specific Address 4 Top, Last 2 bytes
-	AT91_REG	 EMAC_TID; 	// Type ID Checking Register
-	AT91_REG	 EMAC_TPQ; 	// Transmit Pause Quantum Register
-	AT91_REG	 EMAC_USRIO; 	// USER Input/Output Register
-	AT91_REG	 EMAC_WOL; 	// Wake On LAN Register
-	AT91_REG	 Reserved1[13]; 	// 
-	AT91_REG	 EMAC_REV; 	// Revision Register
-} AT91S_EMAC, *AT91PS_EMAC;
-
-// -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- 
-#define AT91C_EMAC_LB         ((unsigned int) 0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
-#define AT91C_EMAC_LLB        ((unsigned int) 0x1 <<  1) // (EMAC) Loopback local. 
-#define AT91C_EMAC_RE         ((unsigned int) 0x1 <<  2) // (EMAC) Receive enable. 
-#define AT91C_EMAC_TE         ((unsigned int) 0x1 <<  3) // (EMAC) Transmit enable. 
-#define AT91C_EMAC_MPE        ((unsigned int) 0x1 <<  4) // (EMAC) Management port enable. 
-#define AT91C_EMAC_CLRSTAT    ((unsigned int) 0x1 <<  5) // (EMAC) Clear statistics registers. 
-#define AT91C_EMAC_INCSTAT    ((unsigned int) 0x1 <<  6) // (EMAC) Increment statistics registers. 
-#define AT91C_EMAC_WESTAT     ((unsigned int) 0x1 <<  7) // (EMAC) Write enable for statistics registers. 
-#define AT91C_EMAC_BP         ((unsigned int) 0x1 <<  8) // (EMAC) Back pressure. 
-#define AT91C_EMAC_TSTART     ((unsigned int) 0x1 <<  9) // (EMAC) Start Transmission. 
-#define AT91C_EMAC_THALT      ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. 
-#define AT91C_EMAC_TPFR       ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame 
-#define AT91C_EMAC_TZQ        ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame
-// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- 
-#define AT91C_EMAC_SPD        ((unsigned int) 0x1 <<  0) // (EMAC) Speed. 
-#define AT91C_EMAC_FD         ((unsigned int) 0x1 <<  1) // (EMAC) Full duplex. 
-#define AT91C_EMAC_JFRAME     ((unsigned int) 0x1 <<  3) // (EMAC) Jumbo Frames. 
-#define AT91C_EMAC_CAF        ((unsigned int) 0x1 <<  4) // (EMAC) Copy all frames. 
-#define AT91C_EMAC_NBC        ((unsigned int) 0x1 <<  5) // (EMAC) No broadcast. 
-#define AT91C_EMAC_MTI        ((unsigned int) 0x1 <<  6) // (EMAC) Multicast hash event enable
-#define AT91C_EMAC_UNI        ((unsigned int) 0x1 <<  7) // (EMAC) Unicast hash enable. 
-#define AT91C_EMAC_BIG        ((unsigned int) 0x1 <<  8) // (EMAC) Receive 1522 bytes. 
-#define AT91C_EMAC_EAE        ((unsigned int) 0x1 <<  9) // (EMAC) External address match enable. 
-#define AT91C_EMAC_CLK        ((unsigned int) 0x3 << 10) // (EMAC) 
-#define 	AT91C_EMAC_CLK_HCLK_8               ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8
-#define 	AT91C_EMAC_CLK_HCLK_16              ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16
-#define 	AT91C_EMAC_CLK_HCLK_32              ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32
-#define 	AT91C_EMAC_CLK_HCLK_64              ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64
-#define AT91C_EMAC_RTY        ((unsigned int) 0x1 << 12) // (EMAC) 
-#define AT91C_EMAC_PAE        ((unsigned int) 0x1 << 13) // (EMAC) 
-#define AT91C_EMAC_RBOF       ((unsigned int) 0x3 << 14) // (EMAC) 
-#define 	AT91C_EMAC_RBOF_OFFSET_0             ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer
-#define 	AT91C_EMAC_RBOF_OFFSET_1             ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer
-#define 	AT91C_EMAC_RBOF_OFFSET_2             ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
-#define 	AT91C_EMAC_RBOF_OFFSET_3             ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
-#define AT91C_EMAC_RLCE       ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable
-#define AT91C_EMAC_DRFCS      ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS
-#define AT91C_EMAC_EFRHD      ((unsigned int) 0x1 << 18) // (EMAC) 
-#define AT91C_EMAC_IRXFCS     ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS
-// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- 
-#define AT91C_EMAC_LINKR      ((unsigned int) 0x1 <<  0) // (EMAC) 
-#define AT91C_EMAC_MDIO       ((unsigned int) 0x1 <<  1) // (EMAC) 
-#define AT91C_EMAC_IDLE       ((unsigned int) 0x1 <<  2) // (EMAC) 
-// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- 
-#define AT91C_EMAC_UBR        ((unsigned int) 0x1 <<  0) // (EMAC) 
-#define AT91C_EMAC_COL        ((unsigned int) 0x1 <<  1) // (EMAC) 
-#define AT91C_EMAC_RLES       ((unsigned int) 0x1 <<  2) // (EMAC) 
-#define AT91C_EMAC_TGO        ((unsigned int) 0x1 <<  3) // (EMAC) Transmit Go
-#define AT91C_EMAC_BEX        ((unsigned int) 0x1 <<  4) // (EMAC) Buffers exhausted mid frame
-#define AT91C_EMAC_COMP       ((unsigned int) 0x1 <<  5) // (EMAC) 
-#define AT91C_EMAC_UND        ((unsigned int) 0x1 <<  6) // (EMAC) 
-// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- 
-#define AT91C_EMAC_BNA        ((unsigned int) 0x1 <<  0) // (EMAC) 
-#define AT91C_EMAC_REC        ((unsigned int) 0x1 <<  1) // (EMAC) 
-#define AT91C_EMAC_OVR        ((unsigned int) 0x1 <<  2) // (EMAC) 
-// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- 
-#define AT91C_EMAC_MFD        ((unsigned int) 0x1 <<  0) // (EMAC) 
-#define AT91C_EMAC_RCOMP      ((unsigned int) 0x1 <<  1) // (EMAC) 
-#define AT91C_EMAC_RXUBR      ((unsigned int) 0x1 <<  2) // (EMAC) 
-#define AT91C_EMAC_TXUBR      ((unsigned int) 0x1 <<  3) // (EMAC) 
-#define AT91C_EMAC_TUNDR      ((unsigned int) 0x1 <<  4) // (EMAC) 
-#define AT91C_EMAC_RLEX       ((unsigned int) 0x1 <<  5) // (EMAC) 
-#define AT91C_EMAC_TXERR      ((unsigned int) 0x1 <<  6) // (EMAC) 
-#define AT91C_EMAC_TCOMP      ((unsigned int) 0x1 <<  7) // (EMAC) 
-#define AT91C_EMAC_LINK       ((unsigned int) 0x1 <<  9) // (EMAC) 
-#define AT91C_EMAC_ROVR       ((unsigned int) 0x1 << 10) // (EMAC) 
-#define AT91C_EMAC_HRESP      ((unsigned int) 0x1 << 11) // (EMAC) 
-#define AT91C_EMAC_PFRE       ((unsigned int) 0x1 << 12) // (EMAC) 
-#define AT91C_EMAC_PTZ        ((unsigned int) 0x1 << 13) // (EMAC) 
-// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- 
-// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- 
-// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- 
-// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- 
-#define AT91C_EMAC_DATA       ((unsigned int) 0xFFFF <<  0) // (EMAC) 
-#define AT91C_EMAC_CODE       ((unsigned int) 0x3 << 16) // (EMAC) 
-#define AT91C_EMAC_REGA       ((unsigned int) 0x1F << 18) // (EMAC) 
-#define AT91C_EMAC_PHYA       ((unsigned int) 0x1F << 23) // (EMAC) 
-#define AT91C_EMAC_RW         ((unsigned int) 0x3 << 28) // (EMAC) 
-#define AT91C_EMAC_SOF        ((unsigned int) 0x3 << 30) // (EMAC) 
-// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- 
-#define AT91C_EMAC_RMII       ((unsigned int) 0x1 <<  0) // (EMAC) Reduce MII
-// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- 
-#define AT91C_EMAC_IP         ((unsigned int) 0xFFFF <<  0) // (EMAC) ARP request IP address
-#define AT91C_EMAC_MAG        ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable
-#define AT91C_EMAC_ARP        ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable
-#define AT91C_EMAC_SA1        ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable
-// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- 
-#define AT91C_EMAC_REVREF     ((unsigned int) 0xFFFF <<  0) // (EMAC) 
-#define AT91C_EMAC_PARTREF    ((unsigned int) 0xFFFF << 16) // (EMAC) 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
-// *****************************************************************************
-typedef struct _AT91S_ADC {
-	AT91_REG	 ADC_CR; 	// ADC Control Register
-	AT91_REG	 ADC_MR; 	// ADC Mode Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 ADC_CHER; 	// ADC Channel Enable Register
-	AT91_REG	 ADC_CHDR; 	// ADC Channel Disable Register
-	AT91_REG	 ADC_CHSR; 	// ADC Channel Status Register
-	AT91_REG	 ADC_SR; 	// ADC Status Register
-	AT91_REG	 ADC_LCDR; 	// ADC Last Converted Data Register
-	AT91_REG	 ADC_IER; 	// ADC Interrupt Enable Register
-	AT91_REG	 ADC_IDR; 	// ADC Interrupt Disable Register
-	AT91_REG	 ADC_IMR; 	// ADC Interrupt Mask Register
-	AT91_REG	 ADC_CDR0; 	// ADC Channel Data Register 0
-	AT91_REG	 ADC_CDR1; 	// ADC Channel Data Register 1
-	AT91_REG	 ADC_CDR2; 	// ADC Channel Data Register 2
-	AT91_REG	 ADC_CDR3; 	// ADC Channel Data Register 3
-	AT91_REG	 ADC_CDR4; 	// ADC Channel Data Register 4
-	AT91_REG	 ADC_CDR5; 	// ADC Channel Data Register 5
-	AT91_REG	 ADC_CDR6; 	// ADC Channel Data Register 6
-	AT91_REG	 ADC_CDR7; 	// ADC Channel Data Register 7
-	AT91_REG	 Reserved1[44]; 	// 
-	AT91_REG	 ADC_RPR; 	// Receive Pointer Register
-	AT91_REG	 ADC_RCR; 	// Receive Counter Register
-	AT91_REG	 ADC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 ADC_TCR; 	// Transmit Counter Register
-	AT91_REG	 ADC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 ADC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 ADC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 ADC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 ADC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 ADC_PTSR; 	// PDC Transfer Status Register
-} AT91S_ADC, *AT91PS_ADC;
-
-// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
-#define AT91C_ADC_SWRST       ((unsigned int) 0x1 <<  0) // (ADC) Software Reset
-#define AT91C_ADC_START       ((unsigned int) 0x1 <<  1) // (ADC) Start Conversion
-// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 
-#define AT91C_ADC_TRGEN       ((unsigned int) 0x1 <<  0) // (ADC) Trigger Enable
-#define 	AT91C_ADC_TRGEN_DIS                  ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
-#define 	AT91C_ADC_TRGEN_EN                   ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
-#define AT91C_ADC_TRGSEL      ((unsigned int) 0x7 <<  1) // (ADC) Trigger Selection
-#define 	AT91C_ADC_TRGSEL_TIOA0                ((unsigned int) 0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
-#define 	AT91C_ADC_TRGSEL_TIOA1                ((unsigned int) 0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
-#define 	AT91C_ADC_TRGSEL_TIOA2                ((unsigned int) 0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
-#define 	AT91C_ADC_TRGSEL_TIOA3                ((unsigned int) 0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
-#define 	AT91C_ADC_TRGSEL_TIOA4                ((unsigned int) 0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
-#define 	AT91C_ADC_TRGSEL_TIOA5                ((unsigned int) 0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
-#define 	AT91C_ADC_TRGSEL_EXT                  ((unsigned int) 0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
-#define AT91C_ADC_LOWRES      ((unsigned int) 0x1 <<  4) // (ADC) Resolution.
-#define 	AT91C_ADC_LOWRES_10_BIT               ((unsigned int) 0x0 <<  4) // (ADC) 10-bit resolution
-#define 	AT91C_ADC_LOWRES_8_BIT                ((unsigned int) 0x1 <<  4) // (ADC) 8-bit resolution
-#define AT91C_ADC_SLEEP       ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
-#define 	AT91C_ADC_SLEEP_NORMAL_MODE          ((unsigned int) 0x0 <<  5) // (ADC) Normal Mode
-#define 	AT91C_ADC_SLEEP_MODE                 ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
-#define AT91C_ADC_PRESCAL     ((unsigned int) 0x3F <<  8) // (ADC) Prescaler rate selection
-#define AT91C_ADC_STARTUP     ((unsigned int) 0x1F << 16) // (ADC) Startup Time
-#define AT91C_ADC_SHTIM       ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
-// -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 
-#define AT91C_ADC_CH0         ((unsigned int) 0x1 <<  0) // (ADC) Channel 0
-#define AT91C_ADC_CH1         ((unsigned int) 0x1 <<  1) // (ADC) Channel 1
-#define AT91C_ADC_CH2         ((unsigned int) 0x1 <<  2) // (ADC) Channel 2
-#define AT91C_ADC_CH3         ((unsigned int) 0x1 <<  3) // (ADC) Channel 3
-#define AT91C_ADC_CH4         ((unsigned int) 0x1 <<  4) // (ADC) Channel 4
-#define AT91C_ADC_CH5         ((unsigned int) 0x1 <<  5) // (ADC) Channel 5
-#define AT91C_ADC_CH6         ((unsigned int) 0x1 <<  6) // (ADC) Channel 6
-#define AT91C_ADC_CH7         ((unsigned int) 0x1 <<  7) // (ADC) Channel 7
-// -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 
-// -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 
-// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 
-#define AT91C_ADC_EOC0        ((unsigned int) 0x1 <<  0) // (ADC) End of Conversion
-#define AT91C_ADC_EOC1        ((unsigned int) 0x1 <<  1) // (ADC) End of Conversion
-#define AT91C_ADC_EOC2        ((unsigned int) 0x1 <<  2) // (ADC) End of Conversion
-#define AT91C_ADC_EOC3        ((unsigned int) 0x1 <<  3) // (ADC) End of Conversion
-#define AT91C_ADC_EOC4        ((unsigned int) 0x1 <<  4) // (ADC) End of Conversion
-#define AT91C_ADC_EOC5        ((unsigned int) 0x1 <<  5) // (ADC) End of Conversion
-#define AT91C_ADC_EOC6        ((unsigned int) 0x1 <<  6) // (ADC) End of Conversion
-#define AT91C_ADC_EOC7        ((unsigned int) 0x1 <<  7) // (ADC) End of Conversion
-#define AT91C_ADC_OVRE0       ((unsigned int) 0x1 <<  8) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE1       ((unsigned int) 0x1 <<  9) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE2       ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE3       ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE4       ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE5       ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE6       ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE7       ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
-#define AT91C_ADC_DRDY        ((unsigned int) 0x1 << 16) // (ADC) Data Ready
-#define AT91C_ADC_GOVRE       ((unsigned int) 0x1 << 17) // (ADC) General Overrun
-#define AT91C_ADC_ENDRX       ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
-#define AT91C_ADC_RXBUFF      ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
-// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 
-#define AT91C_ADC_LDATA       ((unsigned int) 0x3FF <<  0) // (ADC) Last Data Converted
-// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 
-// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 
-// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 
-// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 
-#define AT91C_ADC_DATA        ((unsigned int) 0x3FF <<  0) // (ADC) Converted Data
-// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 
-// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 
-// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 
-// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 
-// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 
-// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 
-// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard
-// *****************************************************************************
-typedef struct _AT91S_AES {
-	AT91_REG	 AES_CR; 	// Control Register
-	AT91_REG	 AES_MR; 	// Mode Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 AES_IER; 	// Interrupt Enable Register
-	AT91_REG	 AES_IDR; 	// Interrupt Disable Register
-	AT91_REG	 AES_IMR; 	// Interrupt Mask Register
-	AT91_REG	 AES_ISR; 	// Interrupt Status Register
-	AT91_REG	 AES_KEYWxR[4]; 	// Key Word x Register
-	AT91_REG	 Reserved1[4]; 	// 
-	AT91_REG	 AES_IDATAxR[4]; 	// Input Data x Register
-	AT91_REG	 AES_ODATAxR[4]; 	// Output Data x Register
-	AT91_REG	 AES_IVxR[4]; 	// Initialization Vector x Register
-	AT91_REG	 Reserved2[35]; 	// 
-	AT91_REG	 AES_VR; 	// AES Version Register
-	AT91_REG	 AES_RPR; 	// Receive Pointer Register
-	AT91_REG	 AES_RCR; 	// Receive Counter Register
-	AT91_REG	 AES_TPR; 	// Transmit Pointer Register
-	AT91_REG	 AES_TCR; 	// Transmit Counter Register
-	AT91_REG	 AES_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 AES_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 AES_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 AES_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 AES_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 AES_PTSR; 	// PDC Transfer Status Register
-} AT91S_AES, *AT91PS_AES;
-
-// -------- AES_CR : (AES Offset: 0x0) Control Register -------- 
-#define AT91C_AES_START       ((unsigned int) 0x1 <<  0) // (AES) Starts Processing
-#define AT91C_AES_SWRST       ((unsigned int) 0x1 <<  8) // (AES) Software Reset
-#define AT91C_AES_LOADSEED    ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading
-// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- 
-#define AT91C_AES_CIPHER      ((unsigned int) 0x1 <<  0) // (AES) Processing Mode
-#define AT91C_AES_PROCDLY     ((unsigned int) 0xF <<  4) // (AES) Processing Delay
-#define AT91C_AES_SMOD        ((unsigned int) 0x3 <<  8) // (AES) Start Mode
-#define 	AT91C_AES_SMOD_MANUAL               ((unsigned int) 0x0 <<  8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
-#define 	AT91C_AES_SMOD_AUTO                 ((unsigned int) 0x1 <<  8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
-#define 	AT91C_AES_SMOD_PDC                  ((unsigned int) 0x2 <<  8) // (AES) PDC Mode (cf datasheet).
-#define AT91C_AES_OPMOD       ((unsigned int) 0x7 << 12) // (AES) Operation Mode
-#define 	AT91C_AES_OPMOD_ECB                  ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode.
-#define 	AT91C_AES_OPMOD_CBC                  ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
-#define 	AT91C_AES_OPMOD_OFB                  ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode.
-#define 	AT91C_AES_OPMOD_CFB                  ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode.
-#define 	AT91C_AES_OPMOD_CTR                  ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode.
-#define AT91C_AES_LOD         ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode
-#define AT91C_AES_CFBS        ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size
-#define 	AT91C_AES_CFBS_128_BIT              ((unsigned int) 0x0 << 16) // (AES) 128-bit.
-#define 	AT91C_AES_CFBS_64_BIT               ((unsigned int) 0x1 << 16) // (AES) 64-bit.
-#define 	AT91C_AES_CFBS_32_BIT               ((unsigned int) 0x2 << 16) // (AES) 32-bit.
-#define 	AT91C_AES_CFBS_16_BIT               ((unsigned int) 0x3 << 16) // (AES) 16-bit.
-#define 	AT91C_AES_CFBS_8_BIT                ((unsigned int) 0x4 << 16) // (AES) 8-bit.
-#define AT91C_AES_CKEY        ((unsigned int) 0xF << 20) // (AES) Countermeasure Key
-#define AT91C_AES_CTYPE       ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type
-#define 	AT91C_AES_CTYPE_TYPE1_EN             ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled.
-#define 	AT91C_AES_CTYPE_TYPE2_EN             ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled.
-#define 	AT91C_AES_CTYPE_TYPE3_EN             ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled.
-#define 	AT91C_AES_CTYPE_TYPE4_EN             ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled.
-#define 	AT91C_AES_CTYPE_TYPE5_EN             ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled.
-// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- 
-#define AT91C_AES_DATRDY      ((unsigned int) 0x1 <<  0) // (AES) DATRDY
-#define AT91C_AES_ENDRX       ((unsigned int) 0x1 <<  1) // (AES) PDC Read Buffer End
-#define AT91C_AES_ENDTX       ((unsigned int) 0x1 <<  2) // (AES) PDC Write Buffer End
-#define AT91C_AES_RXBUFF      ((unsigned int) 0x1 <<  3) // (AES) PDC Read Buffer Full
-#define AT91C_AES_TXBUFE      ((unsigned int) 0x1 <<  4) // (AES) PDC Write Buffer Empty
-#define AT91C_AES_URAD        ((unsigned int) 0x1 <<  8) // (AES) Unspecified Register Access Detection
-// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- 
-// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- 
-// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- 
-#define AT91C_AES_URAT        ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status
-#define 	AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
-#define 	AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing.
-#define 	AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing.
-#define 	AT91C_AES_URAT_OUT_DAT_READ_SUBKEY  ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation.
-#define 	AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation.
-#define 	AT91C_AES_URAT_WO_REG_READ          ((unsigned int) 0x5 << 12) // (AES) Write-only register read access.
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard
-// *****************************************************************************
-typedef struct _AT91S_TDES {
-	AT91_REG	 TDES_CR; 	// Control Register
-	AT91_REG	 TDES_MR; 	// Mode Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 TDES_IER; 	// Interrupt Enable Register
-	AT91_REG	 TDES_IDR; 	// Interrupt Disable Register
-	AT91_REG	 TDES_IMR; 	// Interrupt Mask Register
-	AT91_REG	 TDES_ISR; 	// Interrupt Status Register
-	AT91_REG	 TDES_KEY1WxR[2]; 	// Key 1 Word x Register
-	AT91_REG	 TDES_KEY2WxR[2]; 	// Key 2 Word x Register
-	AT91_REG	 TDES_KEY3WxR[2]; 	// Key 3 Word x Register
-	AT91_REG	 Reserved1[2]; 	// 
-	AT91_REG	 TDES_IDATAxR[2]; 	// Input Data x Register
-	AT91_REG	 Reserved2[2]; 	// 
-	AT91_REG	 TDES_ODATAxR[2]; 	// Output Data x Register
-	AT91_REG	 Reserved3[2]; 	// 
-	AT91_REG	 TDES_IVxR[2]; 	// Initialization Vector x Register
-	AT91_REG	 Reserved4[37]; 	// 
-	AT91_REG	 TDES_VR; 	// TDES Version Register
-	AT91_REG	 TDES_RPR; 	// Receive Pointer Register
-	AT91_REG	 TDES_RCR; 	// Receive Counter Register
-	AT91_REG	 TDES_TPR; 	// Transmit Pointer Register
-	AT91_REG	 TDES_TCR; 	// Transmit Counter Register
-	AT91_REG	 TDES_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 TDES_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 TDES_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 TDES_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 TDES_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 TDES_PTSR; 	// PDC Transfer Status Register
-} AT91S_TDES, *AT91PS_TDES;
-
-// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- 
-#define AT91C_TDES_START      ((unsigned int) 0x1 <<  0) // (TDES) Starts Processing
-#define AT91C_TDES_SWRST      ((unsigned int) 0x1 <<  8) // (TDES) Software Reset
-// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- 
-#define AT91C_TDES_CIPHER     ((unsigned int) 0x1 <<  0) // (TDES) Processing Mode
-#define AT91C_TDES_TDESMOD    ((unsigned int) 0x1 <<  1) // (TDES) Single or Triple DES Mode
-#define AT91C_TDES_KEYMOD     ((unsigned int) 0x1 <<  4) // (TDES) Key Mode
-#define AT91C_TDES_SMOD       ((unsigned int) 0x3 <<  8) // (TDES) Start Mode
-#define 	AT91C_TDES_SMOD_MANUAL               ((unsigned int) 0x0 <<  8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
-#define 	AT91C_TDES_SMOD_AUTO                 ((unsigned int) 0x1 <<  8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
-#define 	AT91C_TDES_SMOD_PDC                  ((unsigned int) 0x2 <<  8) // (TDES) PDC Mode (cf datasheet).
-#define AT91C_TDES_OPMOD      ((unsigned int) 0x3 << 12) // (TDES) Operation Mode
-#define 	AT91C_TDES_OPMOD_ECB                  ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
-#define 	AT91C_TDES_OPMOD_CBC                  ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
-#define 	AT91C_TDES_OPMOD_OFB                  ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode.
-#define 	AT91C_TDES_OPMOD_CFB                  ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode.
-#define AT91C_TDES_LOD        ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode
-#define AT91C_TDES_CFBS       ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size
-#define 	AT91C_TDES_CFBS_64_BIT               ((unsigned int) 0x0 << 16) // (TDES) 64-bit.
-#define 	AT91C_TDES_CFBS_32_BIT               ((unsigned int) 0x1 << 16) // (TDES) 32-bit.
-#define 	AT91C_TDES_CFBS_16_BIT               ((unsigned int) 0x2 << 16) // (TDES) 16-bit.
-#define 	AT91C_TDES_CFBS_8_BIT                ((unsigned int) 0x3 << 16) // (TDES) 8-bit.
-// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- 
-#define AT91C_TDES_DATRDY     ((unsigned int) 0x1 <<  0) // (TDES) DATRDY
-#define AT91C_TDES_ENDRX      ((unsigned int) 0x1 <<  1) // (TDES) PDC Read Buffer End
-#define AT91C_TDES_ENDTX      ((unsigned int) 0x1 <<  2) // (TDES) PDC Write Buffer End
-#define AT91C_TDES_RXBUFF     ((unsigned int) 0x1 <<  3) // (TDES) PDC Read Buffer Full
-#define AT91C_TDES_TXBUFE     ((unsigned int) 0x1 <<  4) // (TDES) PDC Write Buffer Empty
-#define AT91C_TDES_URAD       ((unsigned int) 0x1 <<  8) // (TDES) Unspecified Register Access Detection
-// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- 
-// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- 
-// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- 
-#define AT91C_TDES_URAT       ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status
-#define 	AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
-#define 	AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing.
-#define 	AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing.
-#define 	AT91C_TDES_URAT_WO_REG_READ          ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access.
-
-// *****************************************************************************
-//               REGISTER ADDRESS DEFINITION FOR AT91SAM7X128
-// *****************************************************************************
-// ========== Register definition for SYS peripheral ========== 
-// ========== Register definition for AIC peripheral ========== 
-#define AT91C_AIC_IVR   ((AT91_REG *) 	0xFFFFF100) // (AIC) IRQ Vector Register
-#define AT91C_AIC_SMR   ((AT91_REG *) 	0xFFFFF000) // (AIC) Source Mode Register
-#define AT91C_AIC_FVR   ((AT91_REG *) 	0xFFFFF104) // (AIC) FIQ Vector Register
-#define AT91C_AIC_DCR   ((AT91_REG *) 	0xFFFFF138) // (AIC) Debug Control Register (Protect)
-#define AT91C_AIC_EOICR ((AT91_REG *) 	0xFFFFF130) // (AIC) End of Interrupt Command Register
-#define AT91C_AIC_SVR   ((AT91_REG *) 	0xFFFFF080) // (AIC) Source Vector Register
-#define AT91C_AIC_FFSR  ((AT91_REG *) 	0xFFFFF148) // (AIC) Fast Forcing Status Register
-#define AT91C_AIC_ICCR  ((AT91_REG *) 	0xFFFFF128) // (AIC) Interrupt Clear Command Register
-#define AT91C_AIC_ISR   ((AT91_REG *) 	0xFFFFF108) // (AIC) Interrupt Status Register
-#define AT91C_AIC_IMR   ((AT91_REG *) 	0xFFFFF110) // (AIC) Interrupt Mask Register
-#define AT91C_AIC_IPR   ((AT91_REG *) 	0xFFFFF10C) // (AIC) Interrupt Pending Register
-#define AT91C_AIC_FFER  ((AT91_REG *) 	0xFFFFF140) // (AIC) Fast Forcing Enable Register
-#define AT91C_AIC_IECR  ((AT91_REG *) 	0xFFFFF120) // (AIC) Interrupt Enable Command Register
-#define AT91C_AIC_ISCR  ((AT91_REG *) 	0xFFFFF12C) // (AIC) Interrupt Set Command Register
-#define AT91C_AIC_FFDR  ((AT91_REG *) 	0xFFFFF144) // (AIC) Fast Forcing Disable Register
-#define AT91C_AIC_CISR  ((AT91_REG *) 	0xFFFFF114) // (AIC) Core Interrupt Status Register
-#define AT91C_AIC_IDCR  ((AT91_REG *) 	0xFFFFF124) // (AIC) Interrupt Disable Command Register
-#define AT91C_AIC_SPU   ((AT91_REG *) 	0xFFFFF134) // (AIC) Spurious Vector Register
-// ========== Register definition for PDC_DBGU peripheral ========== 
-#define AT91C_DBGU_TCR  ((AT91_REG *) 	0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
-#define AT91C_DBGU_RNPR ((AT91_REG *) 	0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
-#define AT91C_DBGU_TNPR ((AT91_REG *) 	0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
-#define AT91C_DBGU_TPR  ((AT91_REG *) 	0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
-#define AT91C_DBGU_RPR  ((AT91_REG *) 	0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
-#define AT91C_DBGU_RCR  ((AT91_REG *) 	0xFFFFF304) // (PDC_DBGU) Receive Counter Register
-#define AT91C_DBGU_RNCR ((AT91_REG *) 	0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
-#define AT91C_DBGU_PTCR ((AT91_REG *) 	0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
-#define AT91C_DBGU_PTSR ((AT91_REG *) 	0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
-#define AT91C_DBGU_TNCR ((AT91_REG *) 	0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
-// ========== Register definition for DBGU peripheral ========== 
-#define AT91C_DBGU_EXID ((AT91_REG *) 	0xFFFFF244) // (DBGU) Chip ID Extension Register
-#define AT91C_DBGU_BRGR ((AT91_REG *) 	0xFFFFF220) // (DBGU) Baud Rate Generator Register
-#define AT91C_DBGU_IDR  ((AT91_REG *) 	0xFFFFF20C) // (DBGU) Interrupt Disable Register
-#define AT91C_DBGU_CSR  ((AT91_REG *) 	0xFFFFF214) // (DBGU) Channel Status Register
-#define AT91C_DBGU_CIDR ((AT91_REG *) 	0xFFFFF240) // (DBGU) Chip ID Register
-#define AT91C_DBGU_MR   ((AT91_REG *) 	0xFFFFF204) // (DBGU) Mode Register
-#define AT91C_DBGU_IMR  ((AT91_REG *) 	0xFFFFF210) // (DBGU) Interrupt Mask Register
-#define AT91C_DBGU_CR   ((AT91_REG *) 	0xFFFFF200) // (DBGU) Control Register
-#define AT91C_DBGU_FNTR ((AT91_REG *) 	0xFFFFF248) // (DBGU) Force NTRST Register
-#define AT91C_DBGU_THR  ((AT91_REG *) 	0xFFFFF21C) // (DBGU) Transmitter Holding Register
-#define AT91C_DBGU_RHR  ((AT91_REG *) 	0xFFFFF218) // (DBGU) Receiver Holding Register
-#define AT91C_DBGU_IER  ((AT91_REG *) 	0xFFFFF208) // (DBGU) Interrupt Enable Register
-// ========== Register definition for PIOA peripheral ========== 
-#define AT91C_PIOA_ODR  ((AT91_REG *) 	0xFFFFF414) // (PIOA) Output Disable Registerr
-#define AT91C_PIOA_SODR ((AT91_REG *) 	0xFFFFF430) // (PIOA) Set Output Data Register
-#define AT91C_PIOA_ISR  ((AT91_REG *) 	0xFFFFF44C) // (PIOA) Interrupt Status Register
-#define AT91C_PIOA_ABSR ((AT91_REG *) 	0xFFFFF478) // (PIOA) AB Select Status Register
-#define AT91C_PIOA_IER  ((AT91_REG *) 	0xFFFFF440) // (PIOA) Interrupt Enable Register
-#define AT91C_PIOA_PPUDR ((AT91_REG *) 	0xFFFFF460) // (PIOA) Pull-up Disable Register
-#define AT91C_PIOA_IMR  ((AT91_REG *) 	0xFFFFF448) // (PIOA) Interrupt Mask Register
-#define AT91C_PIOA_PER  ((AT91_REG *) 	0xFFFFF400) // (PIOA) PIO Enable Register
-#define AT91C_PIOA_IFDR ((AT91_REG *) 	0xFFFFF424) // (PIOA) Input Filter Disable Register
-#define AT91C_PIOA_OWDR ((AT91_REG *) 	0xFFFFF4A4) // (PIOA) Output Write Disable Register
-#define AT91C_PIOA_MDSR ((AT91_REG *) 	0xFFFFF458) // (PIOA) Multi-driver Status Register
-#define AT91C_PIOA_IDR  ((AT91_REG *) 	0xFFFFF444) // (PIOA) Interrupt Disable Register
-#define AT91C_PIOA_ODSR ((AT91_REG *) 	0xFFFFF438) // (PIOA) Output Data Status Register
-#define AT91C_PIOA_PPUSR ((AT91_REG *) 	0xFFFFF468) // (PIOA) Pull-up Status Register
-#define AT91C_PIOA_OWSR ((AT91_REG *) 	0xFFFFF4A8) // (PIOA) Output Write Status Register
-#define AT91C_PIOA_BSR  ((AT91_REG *) 	0xFFFFF474) // (PIOA) Select B Register
-#define AT91C_PIOA_OWER ((AT91_REG *) 	0xFFFFF4A0) // (PIOA) Output Write Enable Register
-#define AT91C_PIOA_IFER ((AT91_REG *) 	0xFFFFF420) // (PIOA) Input Filter Enable Register
-#define AT91C_PIOA_PDSR ((AT91_REG *) 	0xFFFFF43C) // (PIOA) Pin Data Status Register
-#define AT91C_PIOA_PPUER ((AT91_REG *) 	0xFFFFF464) // (PIOA) Pull-up Enable Register
-#define AT91C_PIOA_OSR  ((AT91_REG *) 	0xFFFFF418) // (PIOA) Output Status Register
-#define AT91C_PIOA_ASR  ((AT91_REG *) 	0xFFFFF470) // (PIOA) Select A Register
-#define AT91C_PIOA_MDDR ((AT91_REG *) 	0xFFFFF454) // (PIOA) Multi-driver Disable Register
-#define AT91C_PIOA_CODR ((AT91_REG *) 	0xFFFFF434) // (PIOA) Clear Output Data Register
-#define AT91C_PIOA_MDER ((AT91_REG *) 	0xFFFFF450) // (PIOA) Multi-driver Enable Register
-#define AT91C_PIOA_PDR  ((AT91_REG *) 	0xFFFFF404) // (PIOA) PIO Disable Register
-#define AT91C_PIOA_IFSR ((AT91_REG *) 	0xFFFFF428) // (PIOA) Input Filter Status Register
-#define AT91C_PIOA_OER  ((AT91_REG *) 	0xFFFFF410) // (PIOA) Output Enable Register
-#define AT91C_PIOA_PSR  ((AT91_REG *) 	0xFFFFF408) // (PIOA) PIO Status Register
-// ========== Register definition for PIOB peripheral ========== 
-#define AT91C_PIOB_OWDR ((AT91_REG *) 	0xFFFFF6A4) // (PIOB) Output Write Disable Register
-#define AT91C_PIOB_MDER ((AT91_REG *) 	0xFFFFF650) // (PIOB) Multi-driver Enable Register
-#define AT91C_PIOB_PPUSR ((AT91_REG *) 	0xFFFFF668) // (PIOB) Pull-up Status Register
-#define AT91C_PIOB_IMR  ((AT91_REG *) 	0xFFFFF648) // (PIOB) Interrupt Mask Register
-#define AT91C_PIOB_ASR  ((AT91_REG *) 	0xFFFFF670) // (PIOB) Select A Register
-#define AT91C_PIOB_PPUDR ((AT91_REG *) 	0xFFFFF660) // (PIOB) Pull-up Disable Register
-#define AT91C_PIOB_PSR  ((AT91_REG *) 	0xFFFFF608) // (PIOB) PIO Status Register
-#define AT91C_PIOB_IER  ((AT91_REG *) 	0xFFFFF640) // (PIOB) Interrupt Enable Register
-#define AT91C_PIOB_CODR ((AT91_REG *) 	0xFFFFF634) // (PIOB) Clear Output Data Register
-#define AT91C_PIOB_OWER ((AT91_REG *) 	0xFFFFF6A0) // (PIOB) Output Write Enable Register
-#define AT91C_PIOB_ABSR ((AT91_REG *) 	0xFFFFF678) // (PIOB) AB Select Status Register
-#define AT91C_PIOB_IFDR ((AT91_REG *) 	0xFFFFF624) // (PIOB) Input Filter Disable Register
-#define AT91C_PIOB_PDSR ((AT91_REG *) 	0xFFFFF63C) // (PIOB) Pin Data Status Register
-#define AT91C_PIOB_IDR  ((AT91_REG *) 	0xFFFFF644) // (PIOB) Interrupt Disable Register
-#define AT91C_PIOB_OWSR ((AT91_REG *) 	0xFFFFF6A8) // (PIOB) Output Write Status Register
-#define AT91C_PIOB_PDR  ((AT91_REG *) 	0xFFFFF604) // (PIOB) PIO Disable Register
-#define AT91C_PIOB_ODR  ((AT91_REG *) 	0xFFFFF614) // (PIOB) Output Disable Registerr
-#define AT91C_PIOB_IFSR ((AT91_REG *) 	0xFFFFF628) // (PIOB) Input Filter Status Register
-#define AT91C_PIOB_PPUER ((AT91_REG *) 	0xFFFFF664) // (PIOB) Pull-up Enable Register
-#define AT91C_PIOB_SODR ((AT91_REG *) 	0xFFFFF630) // (PIOB) Set Output Data Register
-#define AT91C_PIOB_ISR  ((AT91_REG *) 	0xFFFFF64C) // (PIOB) Interrupt Status Register
-#define AT91C_PIOB_ODSR ((AT91_REG *) 	0xFFFFF638) // (PIOB) Output Data Status Register
-#define AT91C_PIOB_OSR  ((AT91_REG *) 	0xFFFFF618) // (PIOB) Output Status Register
-#define AT91C_PIOB_MDSR ((AT91_REG *) 	0xFFFFF658) // (PIOB) Multi-driver Status Register
-#define AT91C_PIOB_IFER ((AT91_REG *) 	0xFFFFF620) // (PIOB) Input Filter Enable Register
-#define AT91C_PIOB_BSR  ((AT91_REG *) 	0xFFFFF674) // (PIOB) Select B Register
-#define AT91C_PIOB_MDDR ((AT91_REG *) 	0xFFFFF654) // (PIOB) Multi-driver Disable Register
-#define AT91C_PIOB_OER  ((AT91_REG *) 	0xFFFFF610) // (PIOB) Output Enable Register
-#define AT91C_PIOB_PER  ((AT91_REG *) 	0xFFFFF600) // (PIOB) PIO Enable Register
-// ========== Register definition for CKGR peripheral ========== 
-#define AT91C_CKGR_MOR  ((AT91_REG *) 	0xFFFFFC20) // (CKGR) Main Oscillator Register
-#define AT91C_CKGR_PLLR ((AT91_REG *) 	0xFFFFFC2C) // (CKGR) PLL Register
-#define AT91C_CKGR_MCFR ((AT91_REG *) 	0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
-// ========== Register definition for PMC peripheral ========== 
-#define AT91C_PMC_IDR   ((AT91_REG *) 	0xFFFFFC64) // (PMC) Interrupt Disable Register
-#define AT91C_PMC_MOR   ((AT91_REG *) 	0xFFFFFC20) // (PMC) Main Oscillator Register
-#define AT91C_PMC_PLLR  ((AT91_REG *) 	0xFFFFFC2C) // (PMC) PLL Register
-#define AT91C_PMC_PCER  ((AT91_REG *) 	0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
-#define AT91C_PMC_PCKR  ((AT91_REG *) 	0xFFFFFC40) // (PMC) Programmable Clock Register
-#define AT91C_PMC_MCKR  ((AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register
-#define AT91C_PMC_SCDR  ((AT91_REG *) 	0xFFFFFC04) // (PMC) System Clock Disable Register
-#define AT91C_PMC_PCDR  ((AT91_REG *) 	0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
-#define AT91C_PMC_SCSR  ((AT91_REG *) 	0xFFFFFC08) // (PMC) System Clock Status Register
-#define AT91C_PMC_PCSR  ((AT91_REG *) 	0xFFFFFC18) // (PMC) Peripheral Clock Status Register
-#define AT91C_PMC_MCFR  ((AT91_REG *) 	0xFFFFFC24) // (PMC) Main Clock  Frequency Register
-#define AT91C_PMC_SCER  ((AT91_REG *) 	0xFFFFFC00) // (PMC) System Clock Enable Register
-#define AT91C_PMC_IMR   ((AT91_REG *) 	0xFFFFFC6C) // (PMC) Interrupt Mask Register
-#define AT91C_PMC_IER   ((AT91_REG *) 	0xFFFFFC60) // (PMC) Interrupt Enable Register
-#define AT91C_PMC_SR    ((AT91_REG *) 	0xFFFFFC68) // (PMC) Status Register
-// ========== Register definition for RSTC peripheral ========== 
-#define AT91C_RSTC_RCR  ((AT91_REG *) 	0xFFFFFD00) // (RSTC) Reset Control Register
-#define AT91C_RSTC_RMR  ((AT91_REG *) 	0xFFFFFD08) // (RSTC) Reset Mode Register
-#define AT91C_RSTC_RSR  ((AT91_REG *) 	0xFFFFFD04) // (RSTC) Reset Status Register
-// ========== Register definition for RTTC peripheral ========== 
-#define AT91C_RTTC_RTSR ((AT91_REG *) 	0xFFFFFD2C) // (RTTC) Real-time Status Register
-#define AT91C_RTTC_RTMR ((AT91_REG *) 	0xFFFFFD20) // (RTTC) Real-time Mode Register
-#define AT91C_RTTC_RTVR ((AT91_REG *) 	0xFFFFFD28) // (RTTC) Real-time Value Register
-#define AT91C_RTTC_RTAR ((AT91_REG *) 	0xFFFFFD24) // (RTTC) Real-time Alarm Register
-// ========== Register definition for PITC peripheral ========== 
-#define AT91C_PITC_PIVR ((AT91_REG *) 	0xFFFFFD38) // (PITC) Period Interval Value Register
-#define AT91C_PITC_PISR ((AT91_REG *) 	0xFFFFFD34) // (PITC) Period Interval Status Register
-#define AT91C_PITC_PIIR ((AT91_REG *) 	0xFFFFFD3C) // (PITC) Period Interval Image Register
-#define AT91C_PITC_PIMR ((AT91_REG *) 	0xFFFFFD30) // (PITC) Period Interval Mode Register
-// ========== Register definition for WDTC peripheral ========== 
-#define AT91C_WDTC_WDCR ((AT91_REG *) 	0xFFFFFD40) // (WDTC) Watchdog Control Register
-#define AT91C_WDTC_WDSR ((AT91_REG *) 	0xFFFFFD48) // (WDTC) Watchdog Status Register
-#define AT91C_WDTC_WDMR ((AT91_REG *) 	0xFFFFFD44) // (WDTC) Watchdog Mode Register
-// ========== Register definition for VREG peripheral ========== 
-#define AT91C_VREG_MR   ((AT91_REG *) 	0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
-// ========== Register definition for MC peripheral ========== 
-#define AT91C_MC_ASR    ((AT91_REG *) 	0xFFFFFF04) // (MC) MC Abort Status Register
-#define AT91C_MC_RCR    ((AT91_REG *) 	0xFFFFFF00) // (MC) MC Remap Control Register
-#define AT91C_MC_FCR    ((AT91_REG *) 	0xFFFFFF64) // (MC) MC Flash Command Register
-#define AT91C_MC_AASR   ((AT91_REG *) 	0xFFFFFF08) // (MC) MC Abort Address Status Register
-#define AT91C_MC_FSR    ((AT91_REG *) 	0xFFFFFF68) // (MC) MC Flash Status Register
-#define AT91C_MC_FMR    ((AT91_REG *) 	0xFFFFFF60) // (MC) MC Flash Mode Register
-// ========== Register definition for PDC_SPI1 peripheral ========== 
-#define AT91C_SPI1_PTCR ((AT91_REG *) 	0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
-#define AT91C_SPI1_RPR  ((AT91_REG *) 	0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
-#define AT91C_SPI1_TNCR ((AT91_REG *) 	0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
-#define AT91C_SPI1_TPR  ((AT91_REG *) 	0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
-#define AT91C_SPI1_TNPR ((AT91_REG *) 	0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
-#define AT91C_SPI1_TCR  ((AT91_REG *) 	0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
-#define AT91C_SPI1_RCR  ((AT91_REG *) 	0xFFFE4104) // (PDC_SPI1) Receive Counter Register
-#define AT91C_SPI1_RNPR ((AT91_REG *) 	0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
-#define AT91C_SPI1_RNCR ((AT91_REG *) 	0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
-#define AT91C_SPI1_PTSR ((AT91_REG *) 	0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
-// ========== Register definition for SPI1 peripheral ========== 
-#define AT91C_SPI1_IMR  ((AT91_REG *) 	0xFFFE401C) // (SPI1) Interrupt Mask Register
-#define AT91C_SPI1_IER  ((AT91_REG *) 	0xFFFE4014) // (SPI1) Interrupt Enable Register
-#define AT91C_SPI1_MR   ((AT91_REG *) 	0xFFFE4004) // (SPI1) Mode Register
-#define AT91C_SPI1_RDR  ((AT91_REG *) 	0xFFFE4008) // (SPI1) Receive Data Register
-#define AT91C_SPI1_IDR  ((AT91_REG *) 	0xFFFE4018) // (SPI1) Interrupt Disable Register
-#define AT91C_SPI1_SR   ((AT91_REG *) 	0xFFFE4010) // (SPI1) Status Register
-#define AT91C_SPI1_TDR  ((AT91_REG *) 	0xFFFE400C) // (SPI1) Transmit Data Register
-#define AT91C_SPI1_CR   ((AT91_REG *) 	0xFFFE4000) // (SPI1) Control Register
-#define AT91C_SPI1_CSR  ((AT91_REG *) 	0xFFFE4030) // (SPI1) Chip Select Register
-// ========== Register definition for PDC_SPI0 peripheral ========== 
-#define AT91C_SPI0_PTCR ((AT91_REG *) 	0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
-#define AT91C_SPI0_TPR  ((AT91_REG *) 	0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
-#define AT91C_SPI0_TCR  ((AT91_REG *) 	0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
-#define AT91C_SPI0_RCR  ((AT91_REG *) 	0xFFFE0104) // (PDC_SPI0) Receive Counter Register
-#define AT91C_SPI0_PTSR ((AT91_REG *) 	0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
-#define AT91C_SPI0_RNPR ((AT91_REG *) 	0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
-#define AT91C_SPI0_RPR  ((AT91_REG *) 	0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
-#define AT91C_SPI0_TNCR ((AT91_REG *) 	0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
-#define AT91C_SPI0_RNCR ((AT91_REG *) 	0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
-#define AT91C_SPI0_TNPR ((AT91_REG *) 	0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
-// ========== Register definition for SPI0 peripheral ========== 
-#define AT91C_SPI0_IER  ((AT91_REG *) 	0xFFFE0014) // (SPI0) Interrupt Enable Register
-#define AT91C_SPI0_SR   ((AT91_REG *) 	0xFFFE0010) // (SPI0) Status Register
-#define AT91C_SPI0_IDR  ((AT91_REG *) 	0xFFFE0018) // (SPI0) Interrupt Disable Register
-#define AT91C_SPI0_CR   ((AT91_REG *) 	0xFFFE0000) // (SPI0) Control Register
-#define AT91C_SPI0_MR   ((AT91_REG *) 	0xFFFE0004) // (SPI0) Mode Register
-#define AT91C_SPI0_IMR  ((AT91_REG *) 	0xFFFE001C) // (SPI0) Interrupt Mask Register
-#define AT91C_SPI0_TDR  ((AT91_REG *) 	0xFFFE000C) // (SPI0) Transmit Data Register
-#define AT91C_SPI0_RDR  ((AT91_REG *) 	0xFFFE0008) // (SPI0) Receive Data Register
-#define AT91C_SPI0_CSR  ((AT91_REG *) 	0xFFFE0030) // (SPI0) Chip Select Register
-// ========== Register definition for PDC_US1 peripheral ========== 
-#define AT91C_US1_RNCR  ((AT91_REG *) 	0xFFFC4114) // (PDC_US1) Receive Next Counter Register
-#define AT91C_US1_PTCR  ((AT91_REG *) 	0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
-#define AT91C_US1_TCR   ((AT91_REG *) 	0xFFFC410C) // (PDC_US1) Transmit Counter Register
-#define AT91C_US1_PTSR  ((AT91_REG *) 	0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
-#define AT91C_US1_TNPR  ((AT91_REG *) 	0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
-#define AT91C_US1_RCR   ((AT91_REG *) 	0xFFFC4104) // (PDC_US1) Receive Counter Register
-#define AT91C_US1_RNPR  ((AT91_REG *) 	0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
-#define AT91C_US1_RPR   ((AT91_REG *) 	0xFFFC4100) // (PDC_US1) Receive Pointer Register
-#define AT91C_US1_TNCR  ((AT91_REG *) 	0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
-#define AT91C_US1_TPR   ((AT91_REG *) 	0xFFFC4108) // (PDC_US1) Transmit Pointer Register
-// ========== Register definition for US1 peripheral ========== 
-#define AT91C_US1_IF    ((AT91_REG *) 	0xFFFC404C) // (US1) IRDA_FILTER Register
-#define AT91C_US1_NER   ((AT91_REG *) 	0xFFFC4044) // (US1) Nb Errors Register
-#define AT91C_US1_RTOR  ((AT91_REG *) 	0xFFFC4024) // (US1) Receiver Time-out Register
-#define AT91C_US1_CSR   ((AT91_REG *) 	0xFFFC4014) // (US1) Channel Status Register
-#define AT91C_US1_IDR   ((AT91_REG *) 	0xFFFC400C) // (US1) Interrupt Disable Register
-#define AT91C_US1_IER   ((AT91_REG *) 	0xFFFC4008) // (US1) Interrupt Enable Register
-#define AT91C_US1_THR   ((AT91_REG *) 	0xFFFC401C) // (US1) Transmitter Holding Register
-#define AT91C_US1_TTGR  ((AT91_REG *) 	0xFFFC4028) // (US1) Transmitter Time-guard Register
-#define AT91C_US1_RHR   ((AT91_REG *) 	0xFFFC4018) // (US1) Receiver Holding Register
-#define AT91C_US1_BRGR  ((AT91_REG *) 	0xFFFC4020) // (US1) Baud Rate Generator Register
-#define AT91C_US1_IMR   ((AT91_REG *) 	0xFFFC4010) // (US1) Interrupt Mask Register
-#define AT91C_US1_FIDI  ((AT91_REG *) 	0xFFFC4040) // (US1) FI_DI_Ratio Register
-#define AT91C_US1_CR    ((AT91_REG *) 	0xFFFC4000) // (US1) Control Register
-#define AT91C_US1_MR    ((AT91_REG *) 	0xFFFC4004) // (US1) Mode Register
-// ========== Register definition for PDC_US0 peripheral ========== 
-#define AT91C_US0_TNPR  ((AT91_REG *) 	0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
-#define AT91C_US0_RNPR  ((AT91_REG *) 	0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
-#define AT91C_US0_TCR   ((AT91_REG *) 	0xFFFC010C) // (PDC_US0) Transmit Counter Register
-#define AT91C_US0_PTCR  ((AT91_REG *) 	0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
-#define AT91C_US0_PTSR  ((AT91_REG *) 	0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
-#define AT91C_US0_TNCR  ((AT91_REG *) 	0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
-#define AT91C_US0_TPR   ((AT91_REG *) 	0xFFFC0108) // (PDC_US0) Transmit Pointer Register
-#define AT91C_US0_RCR   ((AT91_REG *) 	0xFFFC0104) // (PDC_US0) Receive Counter Register
-#define AT91C_US0_RPR   ((AT91_REG *) 	0xFFFC0100) // (PDC_US0) Receive Pointer Register
-#define AT91C_US0_RNCR  ((AT91_REG *) 	0xFFFC0114) // (PDC_US0) Receive Next Counter Register
-// ========== Register definition for US0 peripheral ========== 
-#define AT91C_US0_BRGR  ((AT91_REG *) 	0xFFFC0020) // (US0) Baud Rate Generator Register
-#define AT91C_US0_NER   ((AT91_REG *) 	0xFFFC0044) // (US0) Nb Errors Register
-#define AT91C_US0_CR    ((AT91_REG *) 	0xFFFC0000) // (US0) Control Register
-#define AT91C_US0_IMR   ((AT91_REG *) 	0xFFFC0010) // (US0) Interrupt Mask Register
-#define AT91C_US0_FIDI  ((AT91_REG *) 	0xFFFC0040) // (US0) FI_DI_Ratio Register
-#define AT91C_US0_TTGR  ((AT91_REG *) 	0xFFFC0028) // (US0) Transmitter Time-guard Register
-#define AT91C_US0_MR    ((AT91_REG *) 	0xFFFC0004) // (US0) Mode Register
-#define AT91C_US0_RTOR  ((AT91_REG *) 	0xFFFC0024) // (US0) Receiver Time-out Register
-#define AT91C_US0_CSR   ((AT91_REG *) 	0xFFFC0014) // (US0) Channel Status Register
-#define AT91C_US0_RHR   ((AT91_REG *) 	0xFFFC0018) // (US0) Receiver Holding Register
-#define AT91C_US0_IDR   ((AT91_REG *) 	0xFFFC000C) // (US0) Interrupt Disable Register
-#define AT91C_US0_THR   ((AT91_REG *) 	0xFFFC001C) // (US0) Transmitter Holding Register
-#define AT91C_US0_IF    ((AT91_REG *) 	0xFFFC004C) // (US0) IRDA_FILTER Register
-#define AT91C_US0_IER   ((AT91_REG *) 	0xFFFC0008) // (US0) Interrupt Enable Register
-// ========== Register definition for PDC_SSC peripheral ========== 
-#define AT91C_SSC_TNCR  ((AT91_REG *) 	0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
-#define AT91C_SSC_RPR   ((AT91_REG *) 	0xFFFD4100) // (PDC_SSC) Receive Pointer Register
-#define AT91C_SSC_RNCR  ((AT91_REG *) 	0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
-#define AT91C_SSC_TPR   ((AT91_REG *) 	0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
-#define AT91C_SSC_PTCR  ((AT91_REG *) 	0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
-#define AT91C_SSC_TCR   ((AT91_REG *) 	0xFFFD410C) // (PDC_SSC) Transmit Counter Register
-#define AT91C_SSC_RCR   ((AT91_REG *) 	0xFFFD4104) // (PDC_SSC) Receive Counter Register
-#define AT91C_SSC_RNPR  ((AT91_REG *) 	0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
-#define AT91C_SSC_TNPR  ((AT91_REG *) 	0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
-#define AT91C_SSC_PTSR  ((AT91_REG *) 	0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
-// ========== Register definition for SSC peripheral ========== 
-#define AT91C_SSC_RHR   ((AT91_REG *) 	0xFFFD4020) // (SSC) Receive Holding Register
-#define AT91C_SSC_RSHR  ((AT91_REG *) 	0xFFFD4030) // (SSC) Receive Sync Holding Register
-#define AT91C_SSC_TFMR  ((AT91_REG *) 	0xFFFD401C) // (SSC) Transmit Frame Mode Register
-#define AT91C_SSC_IDR   ((AT91_REG *) 	0xFFFD4048) // (SSC) Interrupt Disable Register
-#define AT91C_SSC_THR   ((AT91_REG *) 	0xFFFD4024) // (SSC) Transmit Holding Register
-#define AT91C_SSC_RCMR  ((AT91_REG *) 	0xFFFD4010) // (SSC) Receive Clock ModeRegister
-#define AT91C_SSC_IER   ((AT91_REG *) 	0xFFFD4044) // (SSC) Interrupt Enable Register
-#define AT91C_SSC_TSHR  ((AT91_REG *) 	0xFFFD4034) // (SSC) Transmit Sync Holding Register
-#define AT91C_SSC_SR    ((AT91_REG *) 	0xFFFD4040) // (SSC) Status Register
-#define AT91C_SSC_CMR   ((AT91_REG *) 	0xFFFD4004) // (SSC) Clock Mode Register
-#define AT91C_SSC_TCMR  ((AT91_REG *) 	0xFFFD4018) // (SSC) Transmit Clock Mode Register
-#define AT91C_SSC_CR    ((AT91_REG *) 	0xFFFD4000) // (SSC) Control Register
-#define AT91C_SSC_IMR   ((AT91_REG *) 	0xFFFD404C) // (SSC) Interrupt Mask Register
-#define AT91C_SSC_RFMR  ((AT91_REG *) 	0xFFFD4014) // (SSC) Receive Frame Mode Register
-// ========== Register definition for TWI peripheral ========== 
-#define AT91C_TWI_IER   ((AT91_REG *) 	0xFFFB8024) // (TWI) Interrupt Enable Register
-#define AT91C_TWI_CR    ((AT91_REG *) 	0xFFFB8000) // (TWI) Control Register
-#define AT91C_TWI_SR    ((AT91_REG *) 	0xFFFB8020) // (TWI) Status Register
-#define AT91C_TWI_IMR   ((AT91_REG *) 	0xFFFB802C) // (TWI) Interrupt Mask Register
-#define AT91C_TWI_THR   ((AT91_REG *) 	0xFFFB8034) // (TWI) Transmit Holding Register
-#define AT91C_TWI_IDR   ((AT91_REG *) 	0xFFFB8028) // (TWI) Interrupt Disable Register
-#define AT91C_TWI_IADR  ((AT91_REG *) 	0xFFFB800C) // (TWI) Internal Address Register
-#define AT91C_TWI_MMR   ((AT91_REG *) 	0xFFFB8004) // (TWI) Master Mode Register
-#define AT91C_TWI_CWGR  ((AT91_REG *) 	0xFFFB8010) // (TWI) Clock Waveform Generator Register
-#define AT91C_TWI_RHR   ((AT91_REG *) 	0xFFFB8030) // (TWI) Receive Holding Register
-// ========== Register definition for PWMC_CH3 peripheral ========== 
-#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 	0xFFFCC270) // (PWMC_CH3) Channel Update Register
-#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 	0xFFFCC274) // (PWMC_CH3) Reserved
-#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 	0xFFFCC268) // (PWMC_CH3) Channel Period Register
-#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 	0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
-#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 	0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
-#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 	0xFFFCC260) // (PWMC_CH3) Channel Mode Register
-// ========== Register definition for PWMC_CH2 peripheral ========== 
-#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 	0xFFFCC254) // (PWMC_CH2) Reserved
-#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 	0xFFFCC240) // (PWMC_CH2) Channel Mode Register
-#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 	0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
-#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 	0xFFFCC248) // (PWMC_CH2) Channel Period Register
-#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 	0xFFFCC250) // (PWMC_CH2) Channel Update Register
-#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 	0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH1 peripheral ========== 
-#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 	0xFFFCC234) // (PWMC_CH1) Reserved
-#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 	0xFFFCC230) // (PWMC_CH1) Channel Update Register
-#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 	0xFFFCC228) // (PWMC_CH1) Channel Period Register
-#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 	0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
-#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 	0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
-#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 	0xFFFCC220) // (PWMC_CH1) Channel Mode Register
-// ========== Register definition for PWMC_CH0 peripheral ========== 
-#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 	0xFFFCC214) // (PWMC_CH0) Reserved
-#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 	0xFFFCC208) // (PWMC_CH0) Channel Period Register
-#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 	0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
-#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 	0xFFFCC200) // (PWMC_CH0) Channel Mode Register
-#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 	0xFFFCC210) // (PWMC_CH0) Channel Update Register
-#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 	0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
-// ========== Register definition for PWMC peripheral ========== 
-#define AT91C_PWMC_IDR  ((AT91_REG *) 	0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
-#define AT91C_PWMC_DIS  ((AT91_REG *) 	0xFFFCC008) // (PWMC) PWMC Disable Register
-#define AT91C_PWMC_IER  ((AT91_REG *) 	0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
-#define AT91C_PWMC_VR   ((AT91_REG *) 	0xFFFCC0FC) // (PWMC) PWMC Version Register
-#define AT91C_PWMC_ISR  ((AT91_REG *) 	0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
-#define AT91C_PWMC_SR   ((AT91_REG *) 	0xFFFCC00C) // (PWMC) PWMC Status Register
-#define AT91C_PWMC_IMR  ((AT91_REG *) 	0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
-#define AT91C_PWMC_MR   ((AT91_REG *) 	0xFFFCC000) // (PWMC) PWMC Mode Register
-#define AT91C_PWMC_ENA  ((AT91_REG *) 	0xFFFCC004) // (PWMC) PWMC Enable Register
-// ========== Register definition for UDP peripheral ========== 
-#define AT91C_UDP_IMR   ((AT91_REG *) 	0xFFFB0018) // (UDP) Interrupt Mask Register
-#define AT91C_UDP_FADDR ((AT91_REG *) 	0xFFFB0008) // (UDP) Function Address Register
-#define AT91C_UDP_NUM   ((AT91_REG *) 	0xFFFB0000) // (UDP) Frame Number Register
-#define AT91C_UDP_FDR   ((AT91_REG *) 	0xFFFB0050) // (UDP) Endpoint FIFO Data Register
-#define AT91C_UDP_ISR   ((AT91_REG *) 	0xFFFB001C) // (UDP) Interrupt Status Register
-#define AT91C_UDP_CSR   ((AT91_REG *) 	0xFFFB0030) // (UDP) Endpoint Control and Status Register
-#define AT91C_UDP_IDR   ((AT91_REG *) 	0xFFFB0014) // (UDP) Interrupt Disable Register
-#define AT91C_UDP_ICR   ((AT91_REG *) 	0xFFFB0020) // (UDP) Interrupt Clear Register
-#define AT91C_UDP_RSTEP ((AT91_REG *) 	0xFFFB0028) // (UDP) Reset Endpoint Register
-#define AT91C_UDP_TXVC  ((AT91_REG *) 	0xFFFB0074) // (UDP) Transceiver Control Register
-#define AT91C_UDP_GLBSTATE ((AT91_REG *) 	0xFFFB0004) // (UDP) Global State Register
-#define AT91C_UDP_IER   ((AT91_REG *) 	0xFFFB0010) // (UDP) Interrupt Enable Register
-// ========== Register definition for TC0 peripheral ========== 
-#define AT91C_TC0_SR    ((AT91_REG *) 	0xFFFA0020) // (TC0) Status Register
-#define AT91C_TC0_RC    ((AT91_REG *) 	0xFFFA001C) // (TC0) Register C
-#define AT91C_TC0_RB    ((AT91_REG *) 	0xFFFA0018) // (TC0) Register B
-#define AT91C_TC0_CCR   ((AT91_REG *) 	0xFFFA0000) // (TC0) Channel Control Register
-#define AT91C_TC0_CMR   ((AT91_REG *) 	0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC0_IER   ((AT91_REG *) 	0xFFFA0024) // (TC0) Interrupt Enable Register
-#define AT91C_TC0_RA    ((AT91_REG *) 	0xFFFA0014) // (TC0) Register A
-#define AT91C_TC0_IDR   ((AT91_REG *) 	0xFFFA0028) // (TC0) Interrupt Disable Register
-#define AT91C_TC0_CV    ((AT91_REG *) 	0xFFFA0010) // (TC0) Counter Value
-#define AT91C_TC0_IMR   ((AT91_REG *) 	0xFFFA002C) // (TC0) Interrupt Mask Register
-// ========== Register definition for TC1 peripheral ========== 
-#define AT91C_TC1_RB    ((AT91_REG *) 	0xFFFA0058) // (TC1) Register B
-#define AT91C_TC1_CCR   ((AT91_REG *) 	0xFFFA0040) // (TC1) Channel Control Register
-#define AT91C_TC1_IER   ((AT91_REG *) 	0xFFFA0064) // (TC1) Interrupt Enable Register
-#define AT91C_TC1_IDR   ((AT91_REG *) 	0xFFFA0068) // (TC1) Interrupt Disable Register
-#define AT91C_TC1_SR    ((AT91_REG *) 	0xFFFA0060) // (TC1) Status Register
-#define AT91C_TC1_CMR   ((AT91_REG *) 	0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC1_RA    ((AT91_REG *) 	0xFFFA0054) // (TC1) Register A
-#define AT91C_TC1_RC    ((AT91_REG *) 	0xFFFA005C) // (TC1) Register C
-#define AT91C_TC1_IMR   ((AT91_REG *) 	0xFFFA006C) // (TC1) Interrupt Mask Register
-#define AT91C_TC1_CV    ((AT91_REG *) 	0xFFFA0050) // (TC1) Counter Value
-// ========== Register definition for TC2 peripheral ========== 
-#define AT91C_TC2_CMR   ((AT91_REG *) 	0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC2_CCR   ((AT91_REG *) 	0xFFFA0080) // (TC2) Channel Control Register
-#define AT91C_TC2_CV    ((AT91_REG *) 	0xFFFA0090) // (TC2) Counter Value
-#define AT91C_TC2_RA    ((AT91_REG *) 	0xFFFA0094) // (TC2) Register A
-#define AT91C_TC2_RB    ((AT91_REG *) 	0xFFFA0098) // (TC2) Register B
-#define AT91C_TC2_IDR   ((AT91_REG *) 	0xFFFA00A8) // (TC2) Interrupt Disable Register
-#define AT91C_TC2_IMR   ((AT91_REG *) 	0xFFFA00AC) // (TC2) Interrupt Mask Register
-#define AT91C_TC2_RC    ((AT91_REG *) 	0xFFFA009C) // (TC2) Register C
-#define AT91C_TC2_IER   ((AT91_REG *) 	0xFFFA00A4) // (TC2) Interrupt Enable Register
-#define AT91C_TC2_SR    ((AT91_REG *) 	0xFFFA00A0) // (TC2) Status Register
-// ========== Register definition for TCB peripheral ========== 
-#define AT91C_TCB_BMR   ((AT91_REG *) 	0xFFFA00C4) // (TCB) TC Block Mode Register
-#define AT91C_TCB_BCR   ((AT91_REG *) 	0xFFFA00C0) // (TCB) TC Block Control Register
-// ========== Register definition for CAN_MB0 peripheral ========== 
-#define AT91C_CAN_MB0_MDL ((AT91_REG *) 	0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
-#define AT91C_CAN_MB0_MAM ((AT91_REG *) 	0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB0_MCR ((AT91_REG *) 	0xFFFD021C) // (CAN_MB0) MailBox Control Register
-#define AT91C_CAN_MB0_MID ((AT91_REG *) 	0xFFFD0208) // (CAN_MB0) MailBox ID Register
-#define AT91C_CAN_MB0_MSR ((AT91_REG *) 	0xFFFD0210) // (CAN_MB0) MailBox Status Register
-#define AT91C_CAN_MB0_MFID ((AT91_REG *) 	0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
-#define AT91C_CAN_MB0_MDH ((AT91_REG *) 	0xFFFD0218) // (CAN_MB0) MailBox Data High Register
-#define AT91C_CAN_MB0_MMR ((AT91_REG *) 	0xFFFD0200) // (CAN_MB0) MailBox Mode Register
-// ========== Register definition for CAN_MB1 peripheral ========== 
-#define AT91C_CAN_MB1_MDL ((AT91_REG *) 	0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
-#define AT91C_CAN_MB1_MID ((AT91_REG *) 	0xFFFD0228) // (CAN_MB1) MailBox ID Register
-#define AT91C_CAN_MB1_MMR ((AT91_REG *) 	0xFFFD0220) // (CAN_MB1) MailBox Mode Register
-#define AT91C_CAN_MB1_MSR ((AT91_REG *) 	0xFFFD0230) // (CAN_MB1) MailBox Status Register
-#define AT91C_CAN_MB1_MAM ((AT91_REG *) 	0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB1_MDH ((AT91_REG *) 	0xFFFD0238) // (CAN_MB1) MailBox Data High Register
-#define AT91C_CAN_MB1_MCR ((AT91_REG *) 	0xFFFD023C) // (CAN_MB1) MailBox Control Register
-#define AT91C_CAN_MB1_MFID ((AT91_REG *) 	0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
-// ========== Register definition for CAN_MB2 peripheral ========== 
-#define AT91C_CAN_MB2_MCR ((AT91_REG *) 	0xFFFD025C) // (CAN_MB2) MailBox Control Register
-#define AT91C_CAN_MB2_MDH ((AT91_REG *) 	0xFFFD0258) // (CAN_MB2) MailBox Data High Register
-#define AT91C_CAN_MB2_MID ((AT91_REG *) 	0xFFFD0248) // (CAN_MB2) MailBox ID Register
-#define AT91C_CAN_MB2_MDL ((AT91_REG *) 	0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
-#define AT91C_CAN_MB2_MMR ((AT91_REG *) 	0xFFFD0240) // (CAN_MB2) MailBox Mode Register
-#define AT91C_CAN_MB2_MAM ((AT91_REG *) 	0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB2_MFID ((AT91_REG *) 	0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
-#define AT91C_CAN_MB2_MSR ((AT91_REG *) 	0xFFFD0250) // (CAN_MB2) MailBox Status Register
-// ========== Register definition for CAN_MB3 peripheral ========== 
-#define AT91C_CAN_MB3_MFID ((AT91_REG *) 	0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
-#define AT91C_CAN_MB3_MAM ((AT91_REG *) 	0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB3_MID ((AT91_REG *) 	0xFFFD0268) // (CAN_MB3) MailBox ID Register
-#define AT91C_CAN_MB3_MCR ((AT91_REG *) 	0xFFFD027C) // (CAN_MB3) MailBox Control Register
-#define AT91C_CAN_MB3_MMR ((AT91_REG *) 	0xFFFD0260) // (CAN_MB3) MailBox Mode Register
-#define AT91C_CAN_MB3_MSR ((AT91_REG *) 	0xFFFD0270) // (CAN_MB3) MailBox Status Register
-#define AT91C_CAN_MB3_MDL ((AT91_REG *) 	0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
-#define AT91C_CAN_MB3_MDH ((AT91_REG *) 	0xFFFD0278) // (CAN_MB3) MailBox Data High Register
-// ========== Register definition for CAN_MB4 peripheral ========== 
-#define AT91C_CAN_MB4_MID ((AT91_REG *) 	0xFFFD0288) // (CAN_MB4) MailBox ID Register
-#define AT91C_CAN_MB4_MMR ((AT91_REG *) 	0xFFFD0280) // (CAN_MB4) MailBox Mode Register
-#define AT91C_CAN_MB4_MDH ((AT91_REG *) 	0xFFFD0298) // (CAN_MB4) MailBox Data High Register
-#define AT91C_CAN_MB4_MFID ((AT91_REG *) 	0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
-#define AT91C_CAN_MB4_MSR ((AT91_REG *) 	0xFFFD0290) // (CAN_MB4) MailBox Status Register
-#define AT91C_CAN_MB4_MCR ((AT91_REG *) 	0xFFFD029C) // (CAN_MB4) MailBox Control Register
-#define AT91C_CAN_MB4_MDL ((AT91_REG *) 	0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
-#define AT91C_CAN_MB4_MAM ((AT91_REG *) 	0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
-// ========== Register definition for CAN_MB5 peripheral ========== 
-#define AT91C_CAN_MB5_MSR ((AT91_REG *) 	0xFFFD02B0) // (CAN_MB5) MailBox Status Register
-#define AT91C_CAN_MB5_MCR ((AT91_REG *) 	0xFFFD02BC) // (CAN_MB5) MailBox Control Register
-#define AT91C_CAN_MB5_MFID ((AT91_REG *) 	0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
-#define AT91C_CAN_MB5_MDH ((AT91_REG *) 	0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
-#define AT91C_CAN_MB5_MID ((AT91_REG *) 	0xFFFD02A8) // (CAN_MB5) MailBox ID Register
-#define AT91C_CAN_MB5_MMR ((AT91_REG *) 	0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
-#define AT91C_CAN_MB5_MDL ((AT91_REG *) 	0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
-#define AT91C_CAN_MB5_MAM ((AT91_REG *) 	0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
-// ========== Register definition for CAN_MB6 peripheral ========== 
-#define AT91C_CAN_MB6_MFID ((AT91_REG *) 	0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
-#define AT91C_CAN_MB6_MID ((AT91_REG *) 	0xFFFD02C8) // (CAN_MB6) MailBox ID Register
-#define AT91C_CAN_MB6_MAM ((AT91_REG *) 	0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB6_MSR ((AT91_REG *) 	0xFFFD02D0) // (CAN_MB6) MailBox Status Register
-#define AT91C_CAN_MB6_MDL ((AT91_REG *) 	0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
-#define AT91C_CAN_MB6_MCR ((AT91_REG *) 	0xFFFD02DC) // (CAN_MB6) MailBox Control Register
-#define AT91C_CAN_MB6_MDH ((AT91_REG *) 	0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
-#define AT91C_CAN_MB6_MMR ((AT91_REG *) 	0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
-// ========== Register definition for CAN_MB7 peripheral ========== 
-#define AT91C_CAN_MB7_MCR ((AT91_REG *) 	0xFFFD02FC) // (CAN_MB7) MailBox Control Register
-#define AT91C_CAN_MB7_MDH ((AT91_REG *) 	0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
-#define AT91C_CAN_MB7_MFID ((AT91_REG *) 	0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
-#define AT91C_CAN_MB7_MDL ((AT91_REG *) 	0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
-#define AT91C_CAN_MB7_MID ((AT91_REG *) 	0xFFFD02E8) // (CAN_MB7) MailBox ID Register
-#define AT91C_CAN_MB7_MMR ((AT91_REG *) 	0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
-#define AT91C_CAN_MB7_MAM ((AT91_REG *) 	0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB7_MSR ((AT91_REG *) 	0xFFFD02F0) // (CAN_MB7) MailBox Status Register
-// ========== Register definition for CAN peripheral ========== 
-#define AT91C_CAN_TCR   ((AT91_REG *) 	0xFFFD0024) // (CAN) Transfer Command Register
-#define AT91C_CAN_IMR   ((AT91_REG *) 	0xFFFD000C) // (CAN) Interrupt Mask Register
-#define AT91C_CAN_IER   ((AT91_REG *) 	0xFFFD0004) // (CAN) Interrupt Enable Register
-#define AT91C_CAN_ECR   ((AT91_REG *) 	0xFFFD0020) // (CAN) Error Counter Register
-#define AT91C_CAN_TIMESTP ((AT91_REG *) 	0xFFFD001C) // (CAN) Time Stamp Register
-#define AT91C_CAN_MR    ((AT91_REG *) 	0xFFFD0000) // (CAN) Mode Register
-#define AT91C_CAN_IDR   ((AT91_REG *) 	0xFFFD0008) // (CAN) Interrupt Disable Register
-#define AT91C_CAN_ACR   ((AT91_REG *) 	0xFFFD0028) // (CAN) Abort Command Register
-#define AT91C_CAN_TIM   ((AT91_REG *) 	0xFFFD0018) // (CAN) Timer Register
-#define AT91C_CAN_SR    ((AT91_REG *) 	0xFFFD0010) // (CAN) Status Register
-#define AT91C_CAN_BR    ((AT91_REG *) 	0xFFFD0014) // (CAN) Baudrate Register
-#define AT91C_CAN_VR    ((AT91_REG *) 	0xFFFD00FC) // (CAN) Version Register
-// ========== Register definition for EMAC peripheral ========== 
-#define AT91C_EMAC_ISR  ((AT91_REG *) 	0xFFFDC024) // (EMAC) Interrupt Status Register
-#define AT91C_EMAC_SA4H ((AT91_REG *) 	0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
-#define AT91C_EMAC_SA1L ((AT91_REG *) 	0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
-#define AT91C_EMAC_ELE  ((AT91_REG *) 	0xFFFDC078) // (EMAC) Excessive Length Errors Register
-#define AT91C_EMAC_LCOL ((AT91_REG *) 	0xFFFDC05C) // (EMAC) Late Collision Register
-#define AT91C_EMAC_RLE  ((AT91_REG *) 	0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
-#define AT91C_EMAC_WOL  ((AT91_REG *) 	0xFFFDC0C4) // (EMAC) Wake On LAN Register
-#define AT91C_EMAC_DTF  ((AT91_REG *) 	0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
-#define AT91C_EMAC_TUND ((AT91_REG *) 	0xFFFDC064) // (EMAC) Transmit Underrun Error Register
-#define AT91C_EMAC_NCR  ((AT91_REG *) 	0xFFFDC000) // (EMAC) Network Control Register
-#define AT91C_EMAC_SA4L ((AT91_REG *) 	0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
-#define AT91C_EMAC_RSR  ((AT91_REG *) 	0xFFFDC020) // (EMAC) Receive Status Register
-#define AT91C_EMAC_SA3L ((AT91_REG *) 	0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
-#define AT91C_EMAC_TSR  ((AT91_REG *) 	0xFFFDC014) // (EMAC) Transmit Status Register
-#define AT91C_EMAC_IDR  ((AT91_REG *) 	0xFFFDC02C) // (EMAC) Interrupt Disable Register
-#define AT91C_EMAC_RSE  ((AT91_REG *) 	0xFFFDC074) // (EMAC) Receive Symbol Errors Register
-#define AT91C_EMAC_ECOL ((AT91_REG *) 	0xFFFDC060) // (EMAC) Excessive Collision Register
-#define AT91C_EMAC_TID  ((AT91_REG *) 	0xFFFDC0B8) // (EMAC) Type ID Checking Register
-#define AT91C_EMAC_HRB  ((AT91_REG *) 	0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
-#define AT91C_EMAC_TBQP ((AT91_REG *) 	0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
-#define AT91C_EMAC_USRIO ((AT91_REG *) 	0xFFFDC0C0) // (EMAC) USER Input/Output Register
-#define AT91C_EMAC_PTR  ((AT91_REG *) 	0xFFFDC038) // (EMAC) Pause Time Register
-#define AT91C_EMAC_SA2H ((AT91_REG *) 	0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
-#define AT91C_EMAC_ROV  ((AT91_REG *) 	0xFFFDC070) // (EMAC) Receive Overrun Errors Register
-#define AT91C_EMAC_ALE  ((AT91_REG *) 	0xFFFDC054) // (EMAC) Alignment Error Register
-#define AT91C_EMAC_RJA  ((AT91_REG *) 	0xFFFDC07C) // (EMAC) Receive Jabbers Register
-#define AT91C_EMAC_RBQP ((AT91_REG *) 	0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
-#define AT91C_EMAC_TPF  ((AT91_REG *) 	0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
-#define AT91C_EMAC_NCFGR ((AT91_REG *) 	0xFFFDC004) // (EMAC) Network Configuration Register
-#define AT91C_EMAC_HRT  ((AT91_REG *) 	0xFFFDC094) // (EMAC) Hash Address Top[63:32]
-#define AT91C_EMAC_USF  ((AT91_REG *) 	0xFFFDC080) // (EMAC) Undersize Frames Register
-#define AT91C_EMAC_FCSE ((AT91_REG *) 	0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
-#define AT91C_EMAC_TPQ  ((AT91_REG *) 	0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
-#define AT91C_EMAC_MAN  ((AT91_REG *) 	0xFFFDC034) // (EMAC) PHY Maintenance Register
-#define AT91C_EMAC_FTO  ((AT91_REG *) 	0xFFFDC040) // (EMAC) Frames Transmitted OK Register
-#define AT91C_EMAC_REV  ((AT91_REG *) 	0xFFFDC0FC) // (EMAC) Revision Register
-#define AT91C_EMAC_IMR  ((AT91_REG *) 	0xFFFDC030) // (EMAC) Interrupt Mask Register
-#define AT91C_EMAC_SCF  ((AT91_REG *) 	0xFFFDC044) // (EMAC) Single Collision Frame Register
-#define AT91C_EMAC_PFR  ((AT91_REG *) 	0xFFFDC03C) // (EMAC) Pause Frames received Register
-#define AT91C_EMAC_MCF  ((AT91_REG *) 	0xFFFDC048) // (EMAC) Multiple Collision Frame Register
-#define AT91C_EMAC_NSR  ((AT91_REG *) 	0xFFFDC008) // (EMAC) Network Status Register
-#define AT91C_EMAC_SA2L ((AT91_REG *) 	0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
-#define AT91C_EMAC_FRO  ((AT91_REG *) 	0xFFFDC04C) // (EMAC) Frames Received OK Register
-#define AT91C_EMAC_IER  ((AT91_REG *) 	0xFFFDC028) // (EMAC) Interrupt Enable Register
-#define AT91C_EMAC_SA1H ((AT91_REG *) 	0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
-#define AT91C_EMAC_CSE  ((AT91_REG *) 	0xFFFDC068) // (EMAC) Carrier Sense Error Register
-#define AT91C_EMAC_SA3H ((AT91_REG *) 	0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
-#define AT91C_EMAC_RRE  ((AT91_REG *) 	0xFFFDC06C) // (EMAC) Receive Ressource Error Register
-#define AT91C_EMAC_STE  ((AT91_REG *) 	0xFFFDC084) // (EMAC) SQE Test Error Register
-// ========== Register definition for PDC_ADC peripheral ========== 
-#define AT91C_ADC_PTSR  ((AT91_REG *) 	0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
-#define AT91C_ADC_PTCR  ((AT91_REG *) 	0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
-#define AT91C_ADC_TNPR  ((AT91_REG *) 	0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
-#define AT91C_ADC_TNCR  ((AT91_REG *) 	0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
-#define AT91C_ADC_RNPR  ((AT91_REG *) 	0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
-#define AT91C_ADC_RNCR  ((AT91_REG *) 	0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
-#define AT91C_ADC_RPR   ((AT91_REG *) 	0xFFFD8100) // (PDC_ADC) Receive Pointer Register
-#define AT91C_ADC_TCR   ((AT91_REG *) 	0xFFFD810C) // (PDC_ADC) Transmit Counter Register
-#define AT91C_ADC_TPR   ((AT91_REG *) 	0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
-#define AT91C_ADC_RCR   ((AT91_REG *) 	0xFFFD8104) // (PDC_ADC) Receive Counter Register
-// ========== Register definition for ADC peripheral ========== 
-#define AT91C_ADC_CDR2  ((AT91_REG *) 	0xFFFD8038) // (ADC) ADC Channel Data Register 2
-#define AT91C_ADC_CDR3  ((AT91_REG *) 	0xFFFD803C) // (ADC) ADC Channel Data Register 3
-#define AT91C_ADC_CDR0  ((AT91_REG *) 	0xFFFD8030) // (ADC) ADC Channel Data Register 0
-#define AT91C_ADC_CDR5  ((AT91_REG *) 	0xFFFD8044) // (ADC) ADC Channel Data Register 5
-#define AT91C_ADC_CHDR  ((AT91_REG *) 	0xFFFD8014) // (ADC) ADC Channel Disable Register
-#define AT91C_ADC_SR    ((AT91_REG *) 	0xFFFD801C) // (ADC) ADC Status Register
-#define AT91C_ADC_CDR4  ((AT91_REG *) 	0xFFFD8040) // (ADC) ADC Channel Data Register 4
-#define AT91C_ADC_CDR1  ((AT91_REG *) 	0xFFFD8034) // (ADC) ADC Channel Data Register 1
-#define AT91C_ADC_LCDR  ((AT91_REG *) 	0xFFFD8020) // (ADC) ADC Last Converted Data Register
-#define AT91C_ADC_IDR   ((AT91_REG *) 	0xFFFD8028) // (ADC) ADC Interrupt Disable Register
-#define AT91C_ADC_CR    ((AT91_REG *) 	0xFFFD8000) // (ADC) ADC Control Register
-#define AT91C_ADC_CDR7  ((AT91_REG *) 	0xFFFD804C) // (ADC) ADC Channel Data Register 7
-#define AT91C_ADC_CDR6  ((AT91_REG *) 	0xFFFD8048) // (ADC) ADC Channel Data Register 6
-#define AT91C_ADC_IER   ((AT91_REG *) 	0xFFFD8024) // (ADC) ADC Interrupt Enable Register
-#define AT91C_ADC_CHER  ((AT91_REG *) 	0xFFFD8010) // (ADC) ADC Channel Enable Register
-#define AT91C_ADC_CHSR  ((AT91_REG *) 	0xFFFD8018) // (ADC) ADC Channel Status Register
-#define AT91C_ADC_MR    ((AT91_REG *) 	0xFFFD8004) // (ADC) ADC Mode Register
-#define AT91C_ADC_IMR   ((AT91_REG *) 	0xFFFD802C) // (ADC) ADC Interrupt Mask Register
-// ========== Register definition for PDC_AES peripheral ========== 
-#define AT91C_AES_TPR   ((AT91_REG *) 	0xFFFA4108) // (PDC_AES) Transmit Pointer Register
-#define AT91C_AES_PTCR  ((AT91_REG *) 	0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
-#define AT91C_AES_RNPR  ((AT91_REG *) 	0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
-#define AT91C_AES_TNCR  ((AT91_REG *) 	0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
-#define AT91C_AES_TCR   ((AT91_REG *) 	0xFFFA410C) // (PDC_AES) Transmit Counter Register
-#define AT91C_AES_RCR   ((AT91_REG *) 	0xFFFA4104) // (PDC_AES) Receive Counter Register
-#define AT91C_AES_RNCR  ((AT91_REG *) 	0xFFFA4114) // (PDC_AES) Receive Next Counter Register
-#define AT91C_AES_TNPR  ((AT91_REG *) 	0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
-#define AT91C_AES_RPR   ((AT91_REG *) 	0xFFFA4100) // (PDC_AES) Receive Pointer Register
-#define AT91C_AES_PTSR  ((AT91_REG *) 	0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
-// ========== Register definition for AES peripheral ========== 
-#define AT91C_AES_IVxR  ((AT91_REG *) 	0xFFFA4060) // (AES) Initialization Vector x Register
-#define AT91C_AES_MR    ((AT91_REG *) 	0xFFFA4004) // (AES) Mode Register
-#define AT91C_AES_VR    ((AT91_REG *) 	0xFFFA40FC) // (AES) AES Version Register
-#define AT91C_AES_ODATAxR ((AT91_REG *) 	0xFFFA4050) // (AES) Output Data x Register
-#define AT91C_AES_IDATAxR ((AT91_REG *) 	0xFFFA4040) // (AES) Input Data x Register
-#define AT91C_AES_CR    ((AT91_REG *) 	0xFFFA4000) // (AES) Control Register
-#define AT91C_AES_IDR   ((AT91_REG *) 	0xFFFA4014) // (AES) Interrupt Disable Register
-#define AT91C_AES_IMR   ((AT91_REG *) 	0xFFFA4018) // (AES) Interrupt Mask Register
-#define AT91C_AES_IER   ((AT91_REG *) 	0xFFFA4010) // (AES) Interrupt Enable Register
-#define AT91C_AES_KEYWxR ((AT91_REG *) 	0xFFFA4020) // (AES) Key Word x Register
-#define AT91C_AES_ISR   ((AT91_REG *) 	0xFFFA401C) // (AES) Interrupt Status Register
-// ========== Register definition for PDC_TDES peripheral ========== 
-#define AT91C_TDES_RNCR ((AT91_REG *) 	0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
-#define AT91C_TDES_TCR  ((AT91_REG *) 	0xFFFA810C) // (PDC_TDES) Transmit Counter Register
-#define AT91C_TDES_RCR  ((AT91_REG *) 	0xFFFA8104) // (PDC_TDES) Receive Counter Register
-#define AT91C_TDES_TNPR ((AT91_REG *) 	0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
-#define AT91C_TDES_RNPR ((AT91_REG *) 	0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
-#define AT91C_TDES_RPR  ((AT91_REG *) 	0xFFFA8100) // (PDC_TDES) Receive Pointer Register
-#define AT91C_TDES_TNCR ((AT91_REG *) 	0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
-#define AT91C_TDES_TPR  ((AT91_REG *) 	0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
-#define AT91C_TDES_PTSR ((AT91_REG *) 	0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
-#define AT91C_TDES_PTCR ((AT91_REG *) 	0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
-// ========== Register definition for TDES peripheral ========== 
-#define AT91C_TDES_KEY2WxR ((AT91_REG *) 	0xFFFA8028) // (TDES) Key 2 Word x Register
-#define AT91C_TDES_KEY3WxR ((AT91_REG *) 	0xFFFA8030) // (TDES) Key 3 Word x Register
-#define AT91C_TDES_IDR  ((AT91_REG *) 	0xFFFA8014) // (TDES) Interrupt Disable Register
-#define AT91C_TDES_VR   ((AT91_REG *) 	0xFFFA80FC) // (TDES) TDES Version Register
-#define AT91C_TDES_IVxR ((AT91_REG *) 	0xFFFA8060) // (TDES) Initialization Vector x Register
-#define AT91C_TDES_ODATAxR ((AT91_REG *) 	0xFFFA8050) // (TDES) Output Data x Register
-#define AT91C_TDES_IMR  ((AT91_REG *) 	0xFFFA8018) // (TDES) Interrupt Mask Register
-#define AT91C_TDES_MR   ((AT91_REG *) 	0xFFFA8004) // (TDES) Mode Register
-#define AT91C_TDES_CR   ((AT91_REG *) 	0xFFFA8000) // (TDES) Control Register
-#define AT91C_TDES_IER  ((AT91_REG *) 	0xFFFA8010) // (TDES) Interrupt Enable Register
-#define AT91C_TDES_ISR  ((AT91_REG *) 	0xFFFA801C) // (TDES) Interrupt Status Register
-#define AT91C_TDES_IDATAxR ((AT91_REG *) 	0xFFFA8040) // (TDES) Input Data x Register
-#define AT91C_TDES_KEY1WxR ((AT91_REG *) 	0xFFFA8020) // (TDES) Key 1 Word x Register
-
-// *****************************************************************************
-//               PIO DEFINITIONS FOR AT91SAM7X128
-// *****************************************************************************
-#define AT91C_PIO_PA0        ((unsigned int) 1 <<  0) // Pin Controlled by PA0
-#define AT91C_PA0_RXD0     ((unsigned int) AT91C_PIO_PA0) //  USART 0 Receive Data
-#define AT91C_PIO_PA1        ((unsigned int) 1 <<  1) // Pin Controlled by PA1
-#define AT91C_PA1_TXD0     ((unsigned int) AT91C_PIO_PA1) //  USART 0 Transmit Data
-#define AT91C_PIO_PA10       ((unsigned int) 1 << 10) // Pin Controlled by PA10
-#define AT91C_PA10_TWD      ((unsigned int) AT91C_PIO_PA10) //  TWI Two-wire Serial Data
-#define AT91C_PIO_PA11       ((unsigned int) 1 << 11) // Pin Controlled by PA11
-#define AT91C_PA11_TWCK     ((unsigned int) AT91C_PIO_PA11) //  TWI Two-wire Serial Clock
-#define AT91C_PIO_PA12       ((unsigned int) 1 << 12) // Pin Controlled by PA12
-#define AT91C_PA12_NPCS00   ((unsigned int) AT91C_PIO_PA12) //  SPI 0 Peripheral Chip Select 0
-#define AT91C_PIO_PA13       ((unsigned int) 1 << 13) // Pin Controlled by PA13
-#define AT91C_PA13_NPCS01   ((unsigned int) AT91C_PIO_PA13) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PA13_PCK1     ((unsigned int) AT91C_PIO_PA13) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PA14       ((unsigned int) 1 << 14) // Pin Controlled by PA14
-#define AT91C_PA14_NPCS02   ((unsigned int) AT91C_PIO_PA14) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PA14_IRQ1     ((unsigned int) AT91C_PIO_PA14) //  External Interrupt 1
-#define AT91C_PIO_PA15       ((unsigned int) 1 << 15) // Pin Controlled by PA15
-#define AT91C_PA15_NPCS03   ((unsigned int) AT91C_PIO_PA15) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PA15_TCLK2    ((unsigned int) AT91C_PIO_PA15) //  Timer Counter 2 external clock input
-#define AT91C_PIO_PA16       ((unsigned int) 1 << 16) // Pin Controlled by PA16
-#define AT91C_PA16_MISO0    ((unsigned int) AT91C_PIO_PA16) //  SPI 0 Master In Slave
-#define AT91C_PIO_PA17       ((unsigned int) 1 << 17) // Pin Controlled by PA17
-#define AT91C_PA17_MOSI0    ((unsigned int) AT91C_PIO_PA17) //  SPI 0 Master Out Slave
-#define AT91C_PIO_PA18       ((unsigned int) 1 << 18) // Pin Controlled by PA18
-#define AT91C_PA18_SPCK0    ((unsigned int) AT91C_PIO_PA18) //  SPI 0 Serial Clock
-#define AT91C_PIO_PA19       ((unsigned int) 1 << 19) // Pin Controlled by PA19
-#define AT91C_PA19_CANRX    ((unsigned int) AT91C_PIO_PA19) //  CAN Receive
-#define AT91C_PIO_PA2        ((unsigned int) 1 <<  2) // Pin Controlled by PA2
-#define AT91C_PA2_SCK0     ((unsigned int) AT91C_PIO_PA2) //  USART 0 Serial Clock
-#define AT91C_PA2_NPCS11   ((unsigned int) AT91C_PIO_PA2) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA20       ((unsigned int) 1 << 20) // Pin Controlled by PA20
-#define AT91C_PA20_CANTX    ((unsigned int) AT91C_PIO_PA20) //  CAN Transmit
-#define AT91C_PIO_PA21       ((unsigned int) 1 << 21) // Pin Controlled by PA21
-#define AT91C_PA21_TF       ((unsigned int) AT91C_PIO_PA21) //  SSC Transmit Frame Sync
-#define AT91C_PA21_NPCS10   ((unsigned int) AT91C_PIO_PA21) //  SPI 1 Peripheral Chip Select 0
-#define AT91C_PIO_PA22       ((unsigned int) 1 << 22) // Pin Controlled by PA22
-#define AT91C_PA22_TK       ((unsigned int) AT91C_PIO_PA22) //  SSC Transmit Clock
-#define AT91C_PA22_SPCK1    ((unsigned int) AT91C_PIO_PA22) //  SPI 1 Serial Clock
-#define AT91C_PIO_PA23       ((unsigned int) 1 << 23) // Pin Controlled by PA23
-#define AT91C_PA23_TD       ((unsigned int) AT91C_PIO_PA23) //  SSC Transmit data
-#define AT91C_PA23_MOSI1    ((unsigned int) AT91C_PIO_PA23) //  SPI 1 Master Out Slave
-#define AT91C_PIO_PA24       ((unsigned int) 1 << 24) // Pin Controlled by PA24
-#define AT91C_PA24_RD       ((unsigned int) AT91C_PIO_PA24) //  SSC Receive Data
-#define AT91C_PA24_MISO1    ((unsigned int) AT91C_PIO_PA24) //  SPI 1 Master In Slave
-#define AT91C_PIO_PA25       ((unsigned int) 1 << 25) // Pin Controlled by PA25
-#define AT91C_PA25_RK       ((unsigned int) AT91C_PIO_PA25) //  SSC Receive Clock
-#define AT91C_PA25_NPCS11   ((unsigned int) AT91C_PIO_PA25) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA26       ((unsigned int) 1 << 26) // Pin Controlled by PA26
-#define AT91C_PA26_RF       ((unsigned int) AT91C_PIO_PA26) //  SSC Receive Frame Sync
-#define AT91C_PA26_NPCS12   ((unsigned int) AT91C_PIO_PA26) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA27       ((unsigned int) 1 << 27) // Pin Controlled by PA27
-#define AT91C_PA27_DRXD     ((unsigned int) AT91C_PIO_PA27) //  DBGU Debug Receive Data
-#define AT91C_PA27_PCK3     ((unsigned int) AT91C_PIO_PA27) //  PMC Programmable Clock Output 3
-#define AT91C_PIO_PA28       ((unsigned int) 1 << 28) // Pin Controlled by PA28
-#define AT91C_PA28_DTXD     ((unsigned int) AT91C_PIO_PA28) //  DBGU Debug Transmit Data
-#define AT91C_PIO_PA29       ((unsigned int) 1 << 29) // Pin Controlled by PA29
-#define AT91C_PA29_FIQ      ((unsigned int) AT91C_PIO_PA29) //  AIC Fast Interrupt Input
-#define AT91C_PA29_NPCS13   ((unsigned int) AT91C_PIO_PA29) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA3        ((unsigned int) 1 <<  3) // Pin Controlled by PA3
-#define AT91C_PA3_RTS0     ((unsigned int) AT91C_PIO_PA3) //  USART 0 Ready To Send
-#define AT91C_PA3_NPCS12   ((unsigned int) AT91C_PIO_PA3) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA30       ((unsigned int) 1 << 30) // Pin Controlled by PA30
-#define AT91C_PA30_IRQ0     ((unsigned int) AT91C_PIO_PA30) //  External Interrupt 0
-#define AT91C_PA30_PCK2     ((unsigned int) AT91C_PIO_PA30) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PA4        ((unsigned int) 1 <<  4) // Pin Controlled by PA4
-#define AT91C_PA4_CTS0     ((unsigned int) AT91C_PIO_PA4) //  USART 0 Clear To Send
-#define AT91C_PA4_NPCS13   ((unsigned int) AT91C_PIO_PA4) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA5        ((unsigned int) 1 <<  5) // Pin Controlled by PA5
-#define AT91C_PA5_RXD1     ((unsigned int) AT91C_PIO_PA5) //  USART 1 Receive Data
-#define AT91C_PIO_PA6        ((unsigned int) 1 <<  6) // Pin Controlled by PA6
-#define AT91C_PA6_TXD1     ((unsigned int) AT91C_PIO_PA6) //  USART 1 Transmit Data
-#define AT91C_PIO_PA7        ((unsigned int) 1 <<  7) // Pin Controlled by PA7
-#define AT91C_PA7_SCK1     ((unsigned int) AT91C_PIO_PA7) //  USART 1 Serial Clock
-#define AT91C_PA7_NPCS01   ((unsigned int) AT91C_PIO_PA7) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PA8        ((unsigned int) 1 <<  8) // Pin Controlled by PA8
-#define AT91C_PA8_RTS1     ((unsigned int) AT91C_PIO_PA8) //  USART 1 Ready To Send
-#define AT91C_PA8_NPCS02   ((unsigned int) AT91C_PIO_PA8) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PA9        ((unsigned int) 1 <<  9) // Pin Controlled by PA9
-#define AT91C_PA9_CTS1     ((unsigned int) AT91C_PIO_PA9) //  USART 1 Clear To Send
-#define AT91C_PA9_NPCS03   ((unsigned int) AT91C_PIO_PA9) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB0        ((unsigned int) 1 <<  0) // Pin Controlled by PB0
-#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) //  Ethernet MAC Transmit Clock/Reference Clock
-#define AT91C_PB0_PCK0     ((unsigned int) AT91C_PIO_PB0) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PB1        ((unsigned int) 1 <<  1) // Pin Controlled by PB1
-#define AT91C_PB1_ETXEN    ((unsigned int) AT91C_PIO_PB1) //  Ethernet MAC Transmit Enable
-#define AT91C_PIO_PB10       ((unsigned int) 1 << 10) // Pin Controlled by PB10
-#define AT91C_PB10_ETX2     ((unsigned int) AT91C_PIO_PB10) //  Ethernet MAC Transmit Data 2
-#define AT91C_PB10_NPCS11   ((unsigned int) AT91C_PIO_PB10) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PB11       ((unsigned int) 1 << 11) // Pin Controlled by PB11
-#define AT91C_PB11_ETX3     ((unsigned int) AT91C_PIO_PB11) //  Ethernet MAC Transmit Data 3
-#define AT91C_PB11_NPCS12   ((unsigned int) AT91C_PIO_PB11) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PB12       ((unsigned int) 1 << 12) // Pin Controlled by PB12
-#define AT91C_PB12_ETXER    ((unsigned int) AT91C_PIO_PB12) //  Ethernet MAC Transmikt Coding Error
-#define AT91C_PB12_TCLK0    ((unsigned int) AT91C_PIO_PB12) //  Timer Counter 0 external clock input
-#define AT91C_PIO_PB13       ((unsigned int) 1 << 13) // Pin Controlled by PB13
-#define AT91C_PB13_ERX2     ((unsigned int) AT91C_PIO_PB13) //  Ethernet MAC Receive Data 2
-#define AT91C_PB13_NPCS01   ((unsigned int) AT91C_PIO_PB13) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PB14       ((unsigned int) 1 << 14) // Pin Controlled by PB14
-#define AT91C_PB14_ERX3     ((unsigned int) AT91C_PIO_PB14) //  Ethernet MAC Receive Data 3
-#define AT91C_PB14_NPCS02   ((unsigned int) AT91C_PIO_PB14) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PB15       ((unsigned int) 1 << 15) // Pin Controlled by PB15
-#define AT91C_PB15_ERXDV    ((unsigned int) AT91C_PIO_PB15) //  Ethernet MAC Receive Data Valid
-#define AT91C_PIO_PB16       ((unsigned int) 1 << 16) // Pin Controlled by PB16
-#define AT91C_PB16_ECOL     ((unsigned int) AT91C_PIO_PB16) //  Ethernet MAC Collision Detected
-#define AT91C_PB16_NPCS13   ((unsigned int) AT91C_PIO_PB16) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PB17       ((unsigned int) 1 << 17) // Pin Controlled by PB17
-#define AT91C_PB17_ERXCK    ((unsigned int) AT91C_PIO_PB17) //  Ethernet MAC Receive Clock
-#define AT91C_PB17_NPCS03   ((unsigned int) AT91C_PIO_PB17) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB18       ((unsigned int) 1 << 18) // Pin Controlled by PB18
-#define AT91C_PB18_EF100    ((unsigned int) AT91C_PIO_PB18) //  Ethernet MAC Force 100 Mbits/sec
-#define AT91C_PB18_ADTRG    ((unsigned int) AT91C_PIO_PB18) //  ADC External Trigger
-#define AT91C_PIO_PB19       ((unsigned int) 1 << 19) // Pin Controlled by PB19
-#define AT91C_PB19_PWM0     ((unsigned int) AT91C_PIO_PB19) //  PWM Channel 0
-#define AT91C_PB19_TCLK1    ((unsigned int) AT91C_PIO_PB19) //  Timer Counter 1 external clock input
-#define AT91C_PIO_PB2        ((unsigned int) 1 <<  2) // Pin Controlled by PB2
-#define AT91C_PB2_ETX0     ((unsigned int) AT91C_PIO_PB2) //  Ethernet MAC Transmit Data 0
-#define AT91C_PIO_PB20       ((unsigned int) 1 << 20) // Pin Controlled by PB20
-#define AT91C_PB20_PWM1     ((unsigned int) AT91C_PIO_PB20) //  PWM Channel 1
-#define AT91C_PB20_PCK0     ((unsigned int) AT91C_PIO_PB20) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PB21       ((unsigned int) 1 << 21) // Pin Controlled by PB21
-#define AT91C_PB21_PWM2     ((unsigned int) AT91C_PIO_PB21) //  PWM Channel 2
-#define AT91C_PB21_PCK1     ((unsigned int) AT91C_PIO_PB21) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PB22       ((unsigned int) 1 << 22) // Pin Controlled by PB22
-#define AT91C_PB22_PWM3     ((unsigned int) AT91C_PIO_PB22) //  PWM Channel 3
-#define AT91C_PB22_PCK2     ((unsigned int) AT91C_PIO_PB22) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PB23       ((unsigned int) 1 << 23) // Pin Controlled by PB23
-#define AT91C_PB23_TIOA0    ((unsigned int) AT91C_PIO_PB23) //  Timer Counter 0 Multipurpose Timer I/O Pin A
-#define AT91C_PB23_DCD1     ((unsigned int) AT91C_PIO_PB23) //  USART 1 Data Carrier Detect
-#define AT91C_PIO_PB24       ((unsigned int) 1 << 24) // Pin Controlled by PB24
-#define AT91C_PB24_TIOB0    ((unsigned int) AT91C_PIO_PB24) //  Timer Counter 0 Multipurpose Timer I/O Pin B
-#define AT91C_PB24_DSR1     ((unsigned int) AT91C_PIO_PB24) //  USART 1 Data Set ready
-#define AT91C_PIO_PB25       ((unsigned int) 1 << 25) // Pin Controlled by PB25
-#define AT91C_PB25_TIOA1    ((unsigned int) AT91C_PIO_PB25) //  Timer Counter 1 Multipurpose Timer I/O Pin A
-#define AT91C_PB25_DTR1     ((unsigned int) AT91C_PIO_PB25) //  USART 1 Data Terminal ready
-#define AT91C_PIO_PB26       ((unsigned int) 1 << 26) // Pin Controlled by PB26
-#define AT91C_PB26_TIOB1    ((unsigned int) AT91C_PIO_PB26) //  Timer Counter 1 Multipurpose Timer I/O Pin B
-#define AT91C_PB26_RI1      ((unsigned int) AT91C_PIO_PB26) //  USART 1 Ring Indicator
-#define AT91C_PIO_PB27       ((unsigned int) 1 << 27) // Pin Controlled by PB27
-#define AT91C_PB27_TIOA2    ((unsigned int) AT91C_PIO_PB27) //  Timer Counter 2 Multipurpose Timer I/O Pin A
-#define AT91C_PB27_PWM0     ((unsigned int) AT91C_PIO_PB27) //  PWM Channel 0
-#define AT91C_PIO_PB28       ((unsigned int) 1 << 28) // Pin Controlled by PB28
-#define AT91C_PB28_TIOB2    ((unsigned int) AT91C_PIO_PB28) //  Timer Counter 2 Multipurpose Timer I/O Pin B
-#define AT91C_PB28_PWM1     ((unsigned int) AT91C_PIO_PB28) //  PWM Channel 1
-#define AT91C_PIO_PB29       ((unsigned int) 1 << 29) // Pin Controlled by PB29
-#define AT91C_PB29_PCK1     ((unsigned int) AT91C_PIO_PB29) //  PMC Programmable Clock Output 1
-#define AT91C_PB29_PWM2     ((unsigned int) AT91C_PIO_PB29) //  PWM Channel 2
-#define AT91C_PIO_PB3        ((unsigned int) 1 <<  3) // Pin Controlled by PB3
-#define AT91C_PB3_ETX1     ((unsigned int) AT91C_PIO_PB3) //  Ethernet MAC Transmit Data 1
-#define AT91C_PIO_PB30       ((unsigned int) 1 << 30) // Pin Controlled by PB30
-#define AT91C_PB30_PCK2     ((unsigned int) AT91C_PIO_PB30) //  PMC Programmable Clock Output 2
-#define AT91C_PB30_PWM3     ((unsigned int) AT91C_PIO_PB30) //  PWM Channel 3
-#define AT91C_PIO_PB4        ((unsigned int) 1 <<  4) // Pin Controlled by PB4
-#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
-#define AT91C_PIO_PB5        ((unsigned int) 1 <<  5) // Pin Controlled by PB5
-#define AT91C_PB5_ERX0     ((unsigned int) AT91C_PIO_PB5) //  Ethernet MAC Receive Data 0
-#define AT91C_PIO_PB6        ((unsigned int) 1 <<  6) // Pin Controlled by PB6
-#define AT91C_PB6_ERX1     ((unsigned int) AT91C_PIO_PB6) //  Ethernet MAC Receive Data 1
-#define AT91C_PIO_PB7        ((unsigned int) 1 <<  7) // Pin Controlled by PB7
-#define AT91C_PB7_ERXER    ((unsigned int) AT91C_PIO_PB7) //  Ethernet MAC Receive Error
-#define AT91C_PIO_PB8        ((unsigned int) 1 <<  8) // Pin Controlled by PB8
-#define AT91C_PB8_EMDC     ((unsigned int) AT91C_PIO_PB8) //  Ethernet MAC Management Data Clock
-#define AT91C_PIO_PB9        ((unsigned int) 1 <<  9) // Pin Controlled by PB9
-#define AT91C_PB9_EMDIO    ((unsigned int) AT91C_PIO_PB9) //  Ethernet MAC Management Data Input/Output
-
-// *****************************************************************************
-//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128
-// *****************************************************************************
-#define AT91C_ID_FIQ    ((unsigned int)  0) // Advanced Interrupt Controller (FIQ)
-#define AT91C_ID_SYS    ((unsigned int)  1) // System Peripheral
-#define AT91C_ID_PIOA   ((unsigned int)  2) // Parallel IO Controller A
-#define AT91C_ID_PIOB   ((unsigned int)  3) // Parallel IO Controller B
-#define AT91C_ID_SPI0   ((unsigned int)  4) // Serial Peripheral Interface 0
-#define AT91C_ID_SPI1   ((unsigned int)  5) // Serial Peripheral Interface 1
-#define AT91C_ID_US0    ((unsigned int)  6) // USART 0
-#define AT91C_ID_US1    ((unsigned int)  7) // USART 1
-#define AT91C_ID_SSC    ((unsigned int)  8) // Serial Synchronous Controller
-#define AT91C_ID_TWI    ((unsigned int)  9) // Two-Wire Interface
-#define AT91C_ID_PWMC   ((unsigned int) 10) // PWM Controller
-#define AT91C_ID_UDP    ((unsigned int) 11) // USB Device Port
-#define AT91C_ID_TC0    ((unsigned int) 12) // Timer Counter 0
-#define AT91C_ID_TC1    ((unsigned int) 13) // Timer Counter 1
-#define AT91C_ID_TC2    ((unsigned int) 14) // Timer Counter 2
-#define AT91C_ID_CAN    ((unsigned int) 15) // Control Area Network Controller
-#define AT91C_ID_EMAC   ((unsigned int) 16) // Ethernet MAC
-#define AT91C_ID_ADC    ((unsigned int) 17) // Analog-to-Digital Converter
-#define AT91C_ID_AES    ((unsigned int) 18) // Advanced Encryption Standard 128-bit
-#define AT91C_ID_TDES   ((unsigned int) 19) // Triple Data Encryption Standard
-#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
-#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
-#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
-#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
-#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
-#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
-#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
-#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
-#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
-#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
-#define AT91C_ID_IRQ0   ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
-#define AT91C_ID_IRQ1   ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
-
-// *****************************************************************************
-//               BASE ADDRESS DEFINITIONS FOR AT91SAM7X128
-// *****************************************************************************
-#define AT91C_BASE_SYS       ((AT91PS_SYS) 	0xFFFFF000) // (SYS) Base Address
-#define AT91C_BASE_AIC       ((AT91PS_AIC) 	0xFFFFF000) // (AIC) Base Address
-#define AT91C_BASE_PDC_DBGU  ((AT91PS_PDC) 	0xFFFFF300) // (PDC_DBGU) Base Address
-#define AT91C_BASE_DBGU      ((AT91PS_DBGU) 	0xFFFFF200) // (DBGU) Base Address
-#define AT91C_BASE_PIOA      ((AT91PS_PIO) 	0xFFFFF400) // (PIOA) Base Address
-#define AT91C_BASE_PIOB      ((AT91PS_PIO) 	0xFFFFF600) // (PIOB) Base Address
-#define AT91C_BASE_CKGR      ((AT91PS_CKGR) 	0xFFFFFC20) // (CKGR) Base Address
-#define AT91C_BASE_PMC       ((AT91PS_PMC) 	0xFFFFFC00) // (PMC) Base Address
-#define AT91C_BASE_RSTC      ((AT91PS_RSTC) 	0xFFFFFD00) // (RSTC) Base Address
-#define AT91C_BASE_RTTC      ((AT91PS_RTTC) 	0xFFFFFD20) // (RTTC) Base Address
-#define AT91C_BASE_PITC      ((AT91PS_PITC) 	0xFFFFFD30) // (PITC) Base Address
-#define AT91C_BASE_WDTC      ((AT91PS_WDTC) 	0xFFFFFD40) // (WDTC) Base Address
-#define AT91C_BASE_VREG      ((AT91PS_VREG) 	0xFFFFFD60) // (VREG) Base Address
-#define AT91C_BASE_MC        ((AT91PS_MC) 	0xFFFFFF00) // (MC) Base Address
-#define AT91C_BASE_PDC_SPI1  ((AT91PS_PDC) 	0xFFFE4100) // (PDC_SPI1) Base Address
-#define AT91C_BASE_SPI1      ((AT91PS_SPI) 	0xFFFE4000) // (SPI1) Base Address
-#define AT91C_BASE_PDC_SPI0  ((AT91PS_PDC) 	0xFFFE0100) // (PDC_SPI0) Base Address
-#define AT91C_BASE_SPI0      ((AT91PS_SPI) 	0xFFFE0000) // (SPI0) Base Address
-#define AT91C_BASE_PDC_US1   ((AT91PS_PDC) 	0xFFFC4100) // (PDC_US1) Base Address
-#define AT91C_BASE_US1       ((AT91PS_USART) 	0xFFFC4000) // (US1) Base Address
-#define AT91C_BASE_PDC_US0   ((AT91PS_PDC) 	0xFFFC0100) // (PDC_US0) Base Address
-#define AT91C_BASE_US0       ((AT91PS_USART) 	0xFFFC0000) // (US0) Base Address
-#define AT91C_BASE_PDC_SSC   ((AT91PS_PDC) 	0xFFFD4100) // (PDC_SSC) Base Address
-#define AT91C_BASE_SSC       ((AT91PS_SSC) 	0xFFFD4000) // (SSC) Base Address
-#define AT91C_BASE_TWI       ((AT91PS_TWI) 	0xFFFB8000) // (TWI) Base Address
-#define AT91C_BASE_PWMC_CH3  ((AT91PS_PWMC_CH) 	0xFFFCC260) // (PWMC_CH3) Base Address
-#define AT91C_BASE_PWMC_CH2  ((AT91PS_PWMC_CH) 	0xFFFCC240) // (PWMC_CH2) Base Address
-#define AT91C_BASE_PWMC_CH1  ((AT91PS_PWMC_CH) 	0xFFFCC220) // (PWMC_CH1) Base Address
-#define AT91C_BASE_PWMC_CH0  ((AT91PS_PWMC_CH) 	0xFFFCC200) // (PWMC_CH0) Base Address
-#define AT91C_BASE_PWMC      ((AT91PS_PWMC) 	0xFFFCC000) // (PWMC) Base Address
-#define AT91C_BASE_UDP       ((AT91PS_UDP) 	0xFFFB0000) // (UDP) Base Address
-#define AT91C_BASE_TC0       ((AT91PS_TC) 	0xFFFA0000) // (TC0) Base Address
-#define AT91C_BASE_TC1       ((AT91PS_TC) 	0xFFFA0040) // (TC1) Base Address
-#define AT91C_BASE_TC2       ((AT91PS_TC) 	0xFFFA0080) // (TC2) Base Address
-#define AT91C_BASE_TCB       ((AT91PS_TCB) 	0xFFFA0000) // (TCB) Base Address
-#define AT91C_BASE_CAN_MB0   ((AT91PS_CAN_MB) 	0xFFFD0200) // (CAN_MB0) Base Address
-#define AT91C_BASE_CAN_MB1   ((AT91PS_CAN_MB) 	0xFFFD0220) // (CAN_MB1) Base Address
-#define AT91C_BASE_CAN_MB2   ((AT91PS_CAN_MB) 	0xFFFD0240) // (CAN_MB2) Base Address
-#define AT91C_BASE_CAN_MB3   ((AT91PS_CAN_MB) 	0xFFFD0260) // (CAN_MB3) Base Address
-#define AT91C_BASE_CAN_MB4   ((AT91PS_CAN_MB) 	0xFFFD0280) // (CAN_MB4) Base Address
-#define AT91C_BASE_CAN_MB5   ((AT91PS_CAN_MB) 	0xFFFD02A0) // (CAN_MB5) Base Address
-#define AT91C_BASE_CAN_MB6   ((AT91PS_CAN_MB) 	0xFFFD02C0) // (CAN_MB6) Base Address
-#define AT91C_BASE_CAN_MB7   ((AT91PS_CAN_MB) 	0xFFFD02E0) // (CAN_MB7) Base Address
-#define AT91C_BASE_CAN       ((AT91PS_CAN) 	0xFFFD0000) // (CAN) Base Address
-#define AT91C_BASE_EMAC      ((AT91PS_EMAC) 	0xFFFDC000) // (EMAC) Base Address
-#define AT91C_BASE_PDC_ADC   ((AT91PS_PDC) 	0xFFFD8100) // (PDC_ADC) Base Address
-#define AT91C_BASE_ADC       ((AT91PS_ADC) 	0xFFFD8000) // (ADC) Base Address
-#define AT91C_BASE_PDC_AES   ((AT91PS_PDC) 	0xFFFA4100) // (PDC_AES) Base Address
-#define AT91C_BASE_AES       ((AT91PS_AES) 	0xFFFA4000) // (AES) Base Address
-#define AT91C_BASE_PDC_TDES  ((AT91PS_PDC) 	0xFFFA8100) // (PDC_TDES) Base Address
-#define AT91C_BASE_TDES      ((AT91PS_TDES) 	0xFFFA8000) // (TDES) Base Address
-
-// *****************************************************************************
-//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128
-// *****************************************************************************
-#define AT91C_ISRAM	 ((char *) 	0x00200000) // Internal SRAM base address
-#define AT91C_ISRAM_SIZE	 ((unsigned int) 0x00008000) // Internal SRAM size in byte (32 Kbyte)
-#define AT91C_IFLASH	 ((char *) 	0x00100000) // Internal ROM base address
-#define AT91C_IFLASH_SIZE	 ((unsigned int) 0x00020000) // Internal ROM size in byte (128 Kbyte)
-#endif /* __IAR_SYSTEMS_ICC__ */
-
-#ifdef __IAR_SYSTEMS_ASM__
-
-// - Hardware register definition
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR System Peripherals
-// - *****************************************************************************
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
-// - *****************************************************************************
-// - -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
-AT91C_AIC_PRIOR           EQU (0x7 <<  0) ;- (AIC) Priority Level
-AT91C_AIC_PRIOR_LOWEST    EQU (0x0) ;- (AIC) Lowest priority level
-AT91C_AIC_PRIOR_HIGHEST   EQU (0x7) ;- (AIC) Highest priority level
-AT91C_AIC_SRCTYPE         EQU (0x3 <<  5) ;- (AIC) Interrupt Source Type
-AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL EQU (0x0 <<  5) ;- (AIC) Internal Sources Code Label High-level Sensitive
-AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL EQU (0x0 <<  5) ;- (AIC) External Sources Code Label Low-level Sensitive
-AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE EQU (0x1 <<  5) ;- (AIC) Internal Sources Code Label Positive Edge triggered
-AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE EQU (0x1 <<  5) ;- (AIC) External Sources Code Label Negative Edge triggered
-AT91C_AIC_SRCTYPE_HIGH_LEVEL EQU (0x2 <<  5) ;- (AIC) Internal Or External Sources Code Label High-level Sensitive
-AT91C_AIC_SRCTYPE_POSITIVE_EDGE EQU (0x3 <<  5) ;- (AIC) Internal Or External Sources Code Label Positive Edge triggered
-// - -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
-AT91C_AIC_NFIQ            EQU (0x1 <<  0) ;- (AIC) NFIQ Status
-AT91C_AIC_NIRQ            EQU (0x1 <<  1) ;- (AIC) NIRQ Status
-// - -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
-AT91C_AIC_DCR_PROT        EQU (0x1 <<  0) ;- (AIC) Protection Mode
-AT91C_AIC_DCR_GMSK        EQU (0x1 <<  1) ;- (AIC) General Mask
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
-// - *****************************************************************************
-// - -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
-AT91C_PDC_RXTEN           EQU (0x1 <<  0) ;- (PDC) Receiver Transfer Enable
-AT91C_PDC_RXTDIS          EQU (0x1 <<  1) ;- (PDC) Receiver Transfer Disable
-AT91C_PDC_TXTEN           EQU (0x1 <<  8) ;- (PDC) Transmitter Transfer Enable
-AT91C_PDC_TXTDIS          EQU (0x1 <<  9) ;- (PDC) Transmitter Transfer Disable
-// - -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Debug Unit
-// - *****************************************************************************
-// - -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
-AT91C_US_RSTRX            EQU (0x1 <<  2) ;- (DBGU) Reset Receiver
-AT91C_US_RSTTX            EQU (0x1 <<  3) ;- (DBGU) Reset Transmitter
-AT91C_US_RXEN             EQU (0x1 <<  4) ;- (DBGU) Receiver Enable
-AT91C_US_RXDIS            EQU (0x1 <<  5) ;- (DBGU) Receiver Disable
-AT91C_US_TXEN             EQU (0x1 <<  6) ;- (DBGU) Transmitter Enable
-AT91C_US_TXDIS            EQU (0x1 <<  7) ;- (DBGU) Transmitter Disable
-AT91C_US_RSTSTA           EQU (0x1 <<  8) ;- (DBGU) Reset Status Bits
-// - -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
-AT91C_US_PAR              EQU (0x7 <<  9) ;- (DBGU) Parity type
-AT91C_US_PAR_EVEN         EQU (0x0 <<  9) ;- (DBGU) Even Parity
-AT91C_US_PAR_ODD          EQU (0x1 <<  9) ;- (DBGU) Odd Parity
-AT91C_US_PAR_SPACE        EQU (0x2 <<  9) ;- (DBGU) Parity forced to 0 (Space)
-AT91C_US_PAR_MARK         EQU (0x3 <<  9) ;- (DBGU) Parity forced to 1 (Mark)
-AT91C_US_PAR_NONE         EQU (0x4 <<  9) ;- (DBGU) No Parity
-AT91C_US_PAR_MULTI_DROP   EQU (0x6 <<  9) ;- (DBGU) Multi-drop mode
-AT91C_US_CHMODE           EQU (0x3 << 14) ;- (DBGU) Channel Mode
-AT91C_US_CHMODE_NORMAL    EQU (0x0 << 14) ;- (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-AT91C_US_CHMODE_AUTO      EQU (0x1 << 14) ;- (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-AT91C_US_CHMODE_LOCAL     EQU (0x2 << 14) ;- (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-AT91C_US_CHMODE_REMOTE    EQU (0x3 << 14) ;- (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-// - -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
-AT91C_US_RXRDY            EQU (0x1 <<  0) ;- (DBGU) RXRDY Interrupt
-AT91C_US_TXRDY            EQU (0x1 <<  1) ;- (DBGU) TXRDY Interrupt
-AT91C_US_ENDRX            EQU (0x1 <<  3) ;- (DBGU) End of Receive Transfer Interrupt
-AT91C_US_ENDTX            EQU (0x1 <<  4) ;- (DBGU) End of Transmit Interrupt
-AT91C_US_OVRE             EQU (0x1 <<  5) ;- (DBGU) Overrun Interrupt
-AT91C_US_FRAME            EQU (0x1 <<  6) ;- (DBGU) Framing Error Interrupt
-AT91C_US_PARE             EQU (0x1 <<  7) ;- (DBGU) Parity Error Interrupt
-AT91C_US_TXEMPTY          EQU (0x1 <<  9) ;- (DBGU) TXEMPTY Interrupt
-AT91C_US_TXBUFE           EQU (0x1 << 11) ;- (DBGU) TXBUFE Interrupt
-AT91C_US_RXBUFF           EQU (0x1 << 12) ;- (DBGU) RXBUFF Interrupt
-AT91C_US_COMM_TX          EQU (0x1 << 30) ;- (DBGU) COMM_TX Interrupt
-AT91C_US_COMM_RX          EQU (0x1 << 31) ;- (DBGU) COMM_RX Interrupt
-// - -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
-// - -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
-// - -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
-// - -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
-AT91C_US_FORCE_NTRST      EQU (0x1 <<  0) ;- (DBGU) Force NTRST in JTAG
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
-// - *****************************************************************************
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Clock Generator Controler
-// - *****************************************************************************
-// - -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
-AT91C_CKGR_MOSCEN         EQU (0x1 <<  0) ;- (CKGR) Main Oscillator Enable
-AT91C_CKGR_OSCBYPASS      EQU (0x1 <<  1) ;- (CKGR) Main Oscillator Bypass
-AT91C_CKGR_OSCOUNT        EQU (0xFF <<  8) ;- (CKGR) Main Oscillator Start-up Time
-// - -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
-AT91C_CKGR_MAINF          EQU (0xFFFF <<  0) ;- (CKGR) Main Clock Frequency
-AT91C_CKGR_MAINRDY        EQU (0x1 << 16) ;- (CKGR) Main Clock Ready
-// - -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 
-AT91C_CKGR_DIV            EQU (0xFF <<  0) ;- (CKGR) Divider Selected
-AT91C_CKGR_DIV_0          EQU (0x0) ;- (CKGR) Divider output is 0
-AT91C_CKGR_DIV_BYPASS     EQU (0x1) ;- (CKGR) Divider is bypassed
-AT91C_CKGR_PLLCOUNT       EQU (0x3F <<  8) ;- (CKGR) PLL Counter
-AT91C_CKGR_OUT            EQU (0x3 << 14) ;- (CKGR) PLL Output Frequency Range
-AT91C_CKGR_OUT_0          EQU (0x0 << 14) ;- (CKGR) Please refer to the PLL datasheet
-AT91C_CKGR_OUT_1          EQU (0x1 << 14) ;- (CKGR) Please refer to the PLL datasheet
-AT91C_CKGR_OUT_2          EQU (0x2 << 14) ;- (CKGR) Please refer to the PLL datasheet
-AT91C_CKGR_OUT_3          EQU (0x3 << 14) ;- (CKGR) Please refer to the PLL datasheet
-AT91C_CKGR_MUL            EQU (0x7FF << 16) ;- (CKGR) PLL Multiplier
-AT91C_CKGR_USBDIV         EQU (0x3 << 28) ;- (CKGR) Divider for USB Clocks
-AT91C_CKGR_USBDIV_0       EQU (0x0 << 28) ;- (CKGR) Divider output is PLL clock output
-AT91C_CKGR_USBDIV_1       EQU (0x1 << 28) ;- (CKGR) Divider output is PLL clock output divided by 2
-AT91C_CKGR_USBDIV_2       EQU (0x2 << 28) ;- (CKGR) Divider output is PLL clock output divided by 4
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Power Management Controler
-// - *****************************************************************************
-// - -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
-AT91C_PMC_PCK             EQU (0x1 <<  0) ;- (PMC) Processor Clock
-AT91C_PMC_UDP             EQU (0x1 <<  7) ;- (PMC) USB Device Port Clock
-AT91C_PMC_PCK0            EQU (0x1 <<  8) ;- (PMC) Programmable Clock Output
-AT91C_PMC_PCK1            EQU (0x1 <<  9) ;- (PMC) Programmable Clock Output
-AT91C_PMC_PCK2            EQU (0x1 << 10) ;- (PMC) Programmable Clock Output
-AT91C_PMC_PCK3            EQU (0x1 << 11) ;- (PMC) Programmable Clock Output
-// - -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
-// - -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
-// - -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
-// - -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
-// - -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 
-// - -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
-AT91C_PMC_CSS             EQU (0x3 <<  0) ;- (PMC) Programmable Clock Selection
-AT91C_PMC_CSS_SLOW_CLK    EQU (0x0) ;- (PMC) Slow Clock is selected
-AT91C_PMC_CSS_MAIN_CLK    EQU (0x1) ;- (PMC) Main Clock is selected
-AT91C_PMC_CSS_PLL_CLK     EQU (0x3) ;- (PMC) Clock from PLL is selected
-AT91C_PMC_PRES            EQU (0x7 <<  2) ;- (PMC) Programmable Clock Prescaler
-AT91C_PMC_PRES_CLK        EQU (0x0 <<  2) ;- (PMC) Selected clock
-AT91C_PMC_PRES_CLK_2      EQU (0x1 <<  2) ;- (PMC) Selected clock divided by 2
-AT91C_PMC_PRES_CLK_4      EQU (0x2 <<  2) ;- (PMC) Selected clock divided by 4
-AT91C_PMC_PRES_CLK_8      EQU (0x3 <<  2) ;- (PMC) Selected clock divided by 8
-AT91C_PMC_PRES_CLK_16     EQU (0x4 <<  2) ;- (PMC) Selected clock divided by 16
-AT91C_PMC_PRES_CLK_32     EQU (0x5 <<  2) ;- (PMC) Selected clock divided by 32
-AT91C_PMC_PRES_CLK_64     EQU (0x6 <<  2) ;- (PMC) Selected clock divided by 64
-// - -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
-// - -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
-AT91C_PMC_MOSCS           EQU (0x1 <<  0) ;- (PMC) MOSC Status/Enable/Disable/Mask
-AT91C_PMC_LOCK            EQU (0x1 <<  2) ;- (PMC) PLL Status/Enable/Disable/Mask
-AT91C_PMC_MCKRDY          EQU (0x1 <<  3) ;- (PMC) MCK_RDY Status/Enable/Disable/Mask
-AT91C_PMC_PCK0RDY         EQU (0x1 <<  8) ;- (PMC) PCK0_RDY Status/Enable/Disable/Mask
-AT91C_PMC_PCK1RDY         EQU (0x1 <<  9) ;- (PMC) PCK1_RDY Status/Enable/Disable/Mask
-AT91C_PMC_PCK2RDY         EQU (0x1 << 10) ;- (PMC) PCK2_RDY Status/Enable/Disable/Mask
-AT91C_PMC_PCK3RDY         EQU (0x1 << 11) ;- (PMC) PCK3_RDY Status/Enable/Disable/Mask
-// - -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
-// - -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
-// - -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Reset Controller Interface
-// - *****************************************************************************
-// - -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
-AT91C_RSTC_PROCRST        EQU (0x1 <<  0) ;- (RSTC) Processor Reset
-AT91C_RSTC_PERRST         EQU (0x1 <<  2) ;- (RSTC) Peripheral Reset
-AT91C_RSTC_EXTRST         EQU (0x1 <<  3) ;- (RSTC) External Reset
-AT91C_RSTC_KEY            EQU (0xFF << 24) ;- (RSTC) Password
-// - -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
-AT91C_RSTC_URSTS          EQU (0x1 <<  0) ;- (RSTC) User Reset Status
-AT91C_RSTC_BODSTS         EQU (0x1 <<  1) ;- (RSTC) Brownout Detection Status
-AT91C_RSTC_RSTTYP         EQU (0x7 <<  8) ;- (RSTC) Reset Type
-AT91C_RSTC_RSTTYP_POWERUP EQU (0x0 <<  8) ;- (RSTC) Power-up Reset. VDDCORE rising.
-AT91C_RSTC_RSTTYP_WAKEUP  EQU (0x1 <<  8) ;- (RSTC) WakeUp Reset. VDDCORE rising.
-AT91C_RSTC_RSTTYP_WATCHDOG EQU (0x2 <<  8) ;- (RSTC) Watchdog Reset. Watchdog overflow occured.
-AT91C_RSTC_RSTTYP_SOFTWARE EQU (0x3 <<  8) ;- (RSTC) Software Reset. Processor reset required by the software.
-AT91C_RSTC_RSTTYP_USER    EQU (0x4 <<  8) ;- (RSTC) User Reset. NRST pin detected low.
-AT91C_RSTC_RSTTYP_BROWNOUT EQU (0x5 <<  8) ;- (RSTC) Brownout Reset occured.
-AT91C_RSTC_NRSTL          EQU (0x1 << 16) ;- (RSTC) NRST pin level
-AT91C_RSTC_SRCMP          EQU (0x1 << 17) ;- (RSTC) Software Reset Command in Progress.
-// - -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
-AT91C_RSTC_URSTEN         EQU (0x1 <<  0) ;- (RSTC) User Reset Enable
-AT91C_RSTC_URSTIEN        EQU (0x1 <<  4) ;- (RSTC) User Reset Interrupt Enable
-AT91C_RSTC_ERSTL          EQU (0xF <<  8) ;- (RSTC) User Reset Enable
-AT91C_RSTC_BODIEN         EQU (0x1 << 16) ;- (RSTC) Brownout Detection Interrupt Enable
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
-// - *****************************************************************************
-// - -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
-AT91C_RTTC_RTPRES         EQU (0xFFFF <<  0) ;- (RTTC) Real-time Timer Prescaler Value
-AT91C_RTTC_ALMIEN         EQU (0x1 << 16) ;- (RTTC) Alarm Interrupt Enable
-AT91C_RTTC_RTTINCIEN      EQU (0x1 << 17) ;- (RTTC) Real Time Timer Increment Interrupt Enable
-AT91C_RTTC_RTTRST         EQU (0x1 << 18) ;- (RTTC) Real Time Timer Restart
-// - -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
-AT91C_RTTC_ALMV           EQU (0x0 <<  0) ;- (RTTC) Alarm Value
-// - -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
-AT91C_RTTC_CRTV           EQU (0x0 <<  0) ;- (RTTC) Current Real-time Value
-// - -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
-AT91C_RTTC_ALMS           EQU (0x1 <<  0) ;- (RTTC) Real-time Alarm Status
-AT91C_RTTC_RTTINC         EQU (0x1 <<  1) ;- (RTTC) Real-time Timer Increment
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
-// - *****************************************************************************
-// - -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
-AT91C_PITC_PIV            EQU (0xFFFFF <<  0) ;- (PITC) Periodic Interval Value
-AT91C_PITC_PITEN          EQU (0x1 << 24) ;- (PITC) Periodic Interval Timer Enabled
-AT91C_PITC_PITIEN         EQU (0x1 << 25) ;- (PITC) Periodic Interval Timer Interrupt Enable
-// - -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
-AT91C_PITC_PITS           EQU (0x1 <<  0) ;- (PITC) Periodic Interval Timer Status
-// - -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
-AT91C_PITC_CPIV           EQU (0xFFFFF <<  0) ;- (PITC) Current Periodic Interval Value
-AT91C_PITC_PICNT          EQU (0xFFF << 20) ;- (PITC) Periodic Interval Counter
-// - -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
-// - *****************************************************************************
-// - -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
-AT91C_WDTC_WDRSTT         EQU (0x1 <<  0) ;- (WDTC) Watchdog Restart
-AT91C_WDTC_KEY            EQU (0xFF << 24) ;- (WDTC) Watchdog KEY Password
-// - -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
-AT91C_WDTC_WDV            EQU (0xFFF <<  0) ;- (WDTC) Watchdog Timer Restart
-AT91C_WDTC_WDFIEN         EQU (0x1 << 12) ;- (WDTC) Watchdog Fault Interrupt Enable
-AT91C_WDTC_WDRSTEN        EQU (0x1 << 13) ;- (WDTC) Watchdog Reset Enable
-AT91C_WDTC_WDRPROC        EQU (0x1 << 14) ;- (WDTC) Watchdog Timer Restart
-AT91C_WDTC_WDDIS          EQU (0x1 << 15) ;- (WDTC) Watchdog Disable
-AT91C_WDTC_WDD            EQU (0xFFF << 16) ;- (WDTC) Watchdog Delta Value
-AT91C_WDTC_WDDBGHLT       EQU (0x1 << 28) ;- (WDTC) Watchdog Debug Halt
-AT91C_WDTC_WDIDLEHLT      EQU (0x1 << 29) ;- (WDTC) Watchdog Idle Halt
-// - -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
-AT91C_WDTC_WDUNF          EQU (0x1 <<  0) ;- (WDTC) Watchdog Underflow
-AT91C_WDTC_WDERR          EQU (0x1 <<  1) ;- (WDTC) Watchdog Error
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
-// - *****************************************************************************
-// - -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- 
-AT91C_VREG_PSTDBY         EQU (0x1 <<  0) ;- (VREG) Voltage Regulator Power Standby Mode
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Memory Controller Interface
-// - *****************************************************************************
-// - -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
-AT91C_MC_RCB              EQU (0x1 <<  0) ;- (MC) Remap Command Bit
-// - -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
-AT91C_MC_UNDADD           EQU (0x1 <<  0) ;- (MC) Undefined Addess Abort Status
-AT91C_MC_MISADD           EQU (0x1 <<  1) ;- (MC) Misaligned Addess Abort Status
-AT91C_MC_ABTSZ            EQU (0x3 <<  8) ;- (MC) Abort Size Status
-AT91C_MC_ABTSZ_BYTE       EQU (0x0 <<  8) ;- (MC) Byte
-AT91C_MC_ABTSZ_HWORD      EQU (0x1 <<  8) ;- (MC) Half-word
-AT91C_MC_ABTSZ_WORD       EQU (0x2 <<  8) ;- (MC) Word
-AT91C_MC_ABTTYP           EQU (0x3 << 10) ;- (MC) Abort Type Status
-AT91C_MC_ABTTYP_DATAR     EQU (0x0 << 10) ;- (MC) Data Read
-AT91C_MC_ABTTYP_DATAW     EQU (0x1 << 10) ;- (MC) Data Write
-AT91C_MC_ABTTYP_FETCH     EQU (0x2 << 10) ;- (MC) Code Fetch
-AT91C_MC_MST0             EQU (0x1 << 16) ;- (MC) Master 0 Abort Source
-AT91C_MC_MST1             EQU (0x1 << 17) ;- (MC) Master 1 Abort Source
-AT91C_MC_SVMST0           EQU (0x1 << 24) ;- (MC) Saved Master 0 Abort Source
-AT91C_MC_SVMST1           EQU (0x1 << 25) ;- (MC) Saved Master 1 Abort Source
-// - -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- 
-AT91C_MC_FRDY             EQU (0x1 <<  0) ;- (MC) Flash Ready
-AT91C_MC_LOCKE            EQU (0x1 <<  2) ;- (MC) Lock Error
-AT91C_MC_PROGE            EQU (0x1 <<  3) ;- (MC) Programming Error
-AT91C_MC_NEBP             EQU (0x1 <<  7) ;- (MC) No Erase Before Programming
-AT91C_MC_FWS              EQU (0x3 <<  8) ;- (MC) Flash Wait State
-AT91C_MC_FWS_0FWS         EQU (0x0 <<  8) ;- (MC) 1 cycle for Read, 2 for Write operations
-AT91C_MC_FWS_1FWS         EQU (0x1 <<  8) ;- (MC) 2 cycles for Read, 3 for Write operations
-AT91C_MC_FWS_2FWS         EQU (0x2 <<  8) ;- (MC) 3 cycles for Read, 4 for Write operations
-AT91C_MC_FWS_3FWS         EQU (0x3 <<  8) ;- (MC) 4 cycles for Read, 4 for Write operations
-AT91C_MC_FMCN             EQU (0xFF << 16) ;- (MC) Flash Microsecond Cycle Number
-// - -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- 
-AT91C_MC_FCMD             EQU (0xF <<  0) ;- (MC) Flash Command
-AT91C_MC_FCMD_START_PROG  EQU (0x1) ;- (MC) Starts the programming of th epage specified by PAGEN.
-AT91C_MC_FCMD_LOCK        EQU (0x2) ;- (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-AT91C_MC_FCMD_PROG_AND_LOCK EQU (0x3) ;- (MC) The lock sequence automatically happens after the programming sequence is completed.
-AT91C_MC_FCMD_UNLOCK      EQU (0x4) ;- (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-AT91C_MC_FCMD_ERASE_ALL   EQU (0x8) ;- (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
-AT91C_MC_FCMD_SET_GP_NVM  EQU (0xB) ;- (MC) Set General Purpose NVM bits.
-AT91C_MC_FCMD_CLR_GP_NVM  EQU (0xD) ;- (MC) Clear General Purpose NVM bits.
-AT91C_MC_FCMD_SET_SECURITY EQU (0xF) ;- (MC) Set Security Bit.
-AT91C_MC_PAGEN            EQU (0x3FF <<  8) ;- (MC) Page Number
-AT91C_MC_KEY              EQU (0xFF << 24) ;- (MC) Writing Protect Key
-// - -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- 
-AT91C_MC_SECURITY         EQU (0x1 <<  4) ;- (MC) Security Bit Status
-AT91C_MC_GPNVM0           EQU (0x1 <<  8) ;- (MC) Sector 0 Lock Status
-AT91C_MC_GPNVM1           EQU (0x1 <<  9) ;- (MC) Sector 1 Lock Status
-AT91C_MC_GPNVM2           EQU (0x1 << 10) ;- (MC) Sector 2 Lock Status
-AT91C_MC_GPNVM3           EQU (0x1 << 11) ;- (MC) Sector 3 Lock Status
-AT91C_MC_GPNVM4           EQU (0x1 << 12) ;- (MC) Sector 4 Lock Status
-AT91C_MC_GPNVM5           EQU (0x1 << 13) ;- (MC) Sector 5 Lock Status
-AT91C_MC_GPNVM6           EQU (0x1 << 14) ;- (MC) Sector 6 Lock Status
-AT91C_MC_GPNVM7           EQU (0x1 << 15) ;- (MC) Sector 7 Lock Status
-AT91C_MC_LOCKS0           EQU (0x1 << 16) ;- (MC) Sector 0 Lock Status
-AT91C_MC_LOCKS1           EQU (0x1 << 17) ;- (MC) Sector 1 Lock Status
-AT91C_MC_LOCKS2           EQU (0x1 << 18) ;- (MC) Sector 2 Lock Status
-AT91C_MC_LOCKS3           EQU (0x1 << 19) ;- (MC) Sector 3 Lock Status
-AT91C_MC_LOCKS4           EQU (0x1 << 20) ;- (MC) Sector 4 Lock Status
-AT91C_MC_LOCKS5           EQU (0x1 << 21) ;- (MC) Sector 5 Lock Status
-AT91C_MC_LOCKS6           EQU (0x1 << 22) ;- (MC) Sector 6 Lock Status
-AT91C_MC_LOCKS7           EQU (0x1 << 23) ;- (MC) Sector 7 Lock Status
-AT91C_MC_LOCKS8           EQU (0x1 << 24) ;- (MC) Sector 8 Lock Status
-AT91C_MC_LOCKS9           EQU (0x1 << 25) ;- (MC) Sector 9 Lock Status
-AT91C_MC_LOCKS10          EQU (0x1 << 26) ;- (MC) Sector 10 Lock Status
-AT91C_MC_LOCKS11          EQU (0x1 << 27) ;- (MC) Sector 11 Lock Status
-AT91C_MC_LOCKS12          EQU (0x1 << 28) ;- (MC) Sector 12 Lock Status
-AT91C_MC_LOCKS13          EQU (0x1 << 29) ;- (MC) Sector 13 Lock Status
-AT91C_MC_LOCKS14          EQU (0x1 << 30) ;- (MC) Sector 14 Lock Status
-AT91C_MC_LOCKS15          EQU (0x1 << 31) ;- (MC) Sector 15 Lock Status
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
-// - *****************************************************************************
-// - -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
-AT91C_SPI_SPIEN           EQU (0x1 <<  0) ;- (SPI) SPI Enable
-AT91C_SPI_SPIDIS          EQU (0x1 <<  1) ;- (SPI) SPI Disable
-AT91C_SPI_SWRST           EQU (0x1 <<  7) ;- (SPI) SPI Software reset
-AT91C_SPI_LASTXFER        EQU (0x1 << 24) ;- (SPI) SPI Last Transfer
-// - -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
-AT91C_SPI_MSTR            EQU (0x1 <<  0) ;- (SPI) Master/Slave Mode
-AT91C_SPI_PS              EQU (0x1 <<  1) ;- (SPI) Peripheral Select
-AT91C_SPI_PS_FIXED        EQU (0x0 <<  1) ;- (SPI) Fixed Peripheral Select
-AT91C_SPI_PS_VARIABLE     EQU (0x1 <<  1) ;- (SPI) Variable Peripheral Select
-AT91C_SPI_PCSDEC          EQU (0x1 <<  2) ;- (SPI) Chip Select Decode
-AT91C_SPI_FDIV            EQU (0x1 <<  3) ;- (SPI) Clock Selection
-AT91C_SPI_MODFDIS         EQU (0x1 <<  4) ;- (SPI) Mode Fault Detection
-AT91C_SPI_LLB             EQU (0x1 <<  7) ;- (SPI) Clock Selection
-AT91C_SPI_PCS             EQU (0xF << 16) ;- (SPI) Peripheral Chip Select
-AT91C_SPI_DLYBCS          EQU (0xFF << 24) ;- (SPI) Delay Between Chip Selects
-// - -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
-AT91C_SPI_RD              EQU (0xFFFF <<  0) ;- (SPI) Receive Data
-AT91C_SPI_RPCS            EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status
-// - -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
-AT91C_SPI_TD              EQU (0xFFFF <<  0) ;- (SPI) Transmit Data
-AT91C_SPI_TPCS            EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status
-// - -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
-AT91C_SPI_RDRF            EQU (0x1 <<  0) ;- (SPI) Receive Data Register Full
-AT91C_SPI_TDRE            EQU (0x1 <<  1) ;- (SPI) Transmit Data Register Empty
-AT91C_SPI_MODF            EQU (0x1 <<  2) ;- (SPI) Mode Fault Error
-AT91C_SPI_OVRES           EQU (0x1 <<  3) ;- (SPI) Overrun Error Status
-AT91C_SPI_ENDRX           EQU (0x1 <<  4) ;- (SPI) End of Receiver Transfer
-AT91C_SPI_ENDTX           EQU (0x1 <<  5) ;- (SPI) End of Receiver Transfer
-AT91C_SPI_RXBUFF          EQU (0x1 <<  6) ;- (SPI) RXBUFF Interrupt
-AT91C_SPI_TXBUFE          EQU (0x1 <<  7) ;- (SPI) TXBUFE Interrupt
-AT91C_SPI_NSSR            EQU (0x1 <<  8) ;- (SPI) NSSR Interrupt
-AT91C_SPI_TXEMPTY         EQU (0x1 <<  9) ;- (SPI) TXEMPTY Interrupt
-AT91C_SPI_SPIENS          EQU (0x1 << 16) ;- (SPI) Enable Status
-// - -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
-// - -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
-// - -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
-// - -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
-AT91C_SPI_CPOL            EQU (0x1 <<  0) ;- (SPI) Clock Polarity
-AT91C_SPI_NCPHA           EQU (0x1 <<  1) ;- (SPI) Clock Phase
-AT91C_SPI_CSAAT           EQU (0x1 <<  3) ;- (SPI) Chip Select Active After Transfer
-AT91C_SPI_BITS            EQU (0xF <<  4) ;- (SPI) Bits Per Transfer
-AT91C_SPI_BITS_8          EQU (0x0 <<  4) ;- (SPI) 8 Bits Per transfer
-AT91C_SPI_BITS_9          EQU (0x1 <<  4) ;- (SPI) 9 Bits Per transfer
-AT91C_SPI_BITS_10         EQU (0x2 <<  4) ;- (SPI) 10 Bits Per transfer
-AT91C_SPI_BITS_11         EQU (0x3 <<  4) ;- (SPI) 11 Bits Per transfer
-AT91C_SPI_BITS_12         EQU (0x4 <<  4) ;- (SPI) 12 Bits Per transfer
-AT91C_SPI_BITS_13         EQU (0x5 <<  4) ;- (SPI) 13 Bits Per transfer
-AT91C_SPI_BITS_14         EQU (0x6 <<  4) ;- (SPI) 14 Bits Per transfer
-AT91C_SPI_BITS_15         EQU (0x7 <<  4) ;- (SPI) 15 Bits Per transfer
-AT91C_SPI_BITS_16         EQU (0x8 <<  4) ;- (SPI) 16 Bits Per transfer
-AT91C_SPI_SCBR            EQU (0xFF <<  8) ;- (SPI) Serial Clock Baud Rate
-AT91C_SPI_DLYBS           EQU (0xFF << 16) ;- (SPI) Delay Before SPCK
-AT91C_SPI_DLYBCT          EQU (0xFF << 24) ;- (SPI) Delay Between Consecutive Transfers
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Usart
-// - *****************************************************************************
-// - -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
-AT91C_US_STTBRK           EQU (0x1 <<  9) ;- (USART) Start Break
-AT91C_US_STPBRK           EQU (0x1 << 10) ;- (USART) Stop Break
-AT91C_US_STTTO            EQU (0x1 << 11) ;- (USART) Start Time-out
-AT91C_US_SENDA            EQU (0x1 << 12) ;- (USART) Send Address
-AT91C_US_RSTIT            EQU (0x1 << 13) ;- (USART) Reset Iterations
-AT91C_US_RSTNACK          EQU (0x1 << 14) ;- (USART) Reset Non Acknowledge
-AT91C_US_RETTO            EQU (0x1 << 15) ;- (USART) Rearm Time-out
-AT91C_US_DTREN            EQU (0x1 << 16) ;- (USART) Data Terminal ready Enable
-AT91C_US_DTRDIS           EQU (0x1 << 17) ;- (USART) Data Terminal ready Disable
-AT91C_US_RTSEN            EQU (0x1 << 18) ;- (USART) Request to Send enable
-AT91C_US_RTSDIS           EQU (0x1 << 19) ;- (USART) Request to Send Disable
-// - -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
-AT91C_US_USMODE           EQU (0xF <<  0) ;- (USART) Usart mode
-AT91C_US_USMODE_NORMAL    EQU (0x0) ;- (USART) Normal
-AT91C_US_USMODE_RS485     EQU (0x1) ;- (USART) RS485
-AT91C_US_USMODE_HWHSH     EQU (0x2) ;- (USART) Hardware Handshaking
-AT91C_US_USMODE_MODEM     EQU (0x3) ;- (USART) Modem
-AT91C_US_USMODE_ISO7816_0 EQU (0x4) ;- (USART) ISO7816 protocol: T = 0
-AT91C_US_USMODE_ISO7816_1 EQU (0x6) ;- (USART) ISO7816 protocol: T = 1
-AT91C_US_USMODE_IRDA      EQU (0x8) ;- (USART) IrDA
-AT91C_US_USMODE_SWHSH     EQU (0xC) ;- (USART) Software Handshaking
-AT91C_US_CLKS             EQU (0x3 <<  4) ;- (USART) Clock Selection (Baud Rate generator Input Clock
-AT91C_US_CLKS_CLOCK       EQU (0x0 <<  4) ;- (USART) Clock
-AT91C_US_CLKS_FDIV1       EQU (0x1 <<  4) ;- (USART) fdiv1
-AT91C_US_CLKS_SLOW        EQU (0x2 <<  4) ;- (USART) slow_clock (ARM)
-AT91C_US_CLKS_EXT         EQU (0x3 <<  4) ;- (USART) External (SCK)
-AT91C_US_CHRL             EQU (0x3 <<  6) ;- (USART) Clock Selection (Baud Rate generator Input Clock
-AT91C_US_CHRL_5_BITS      EQU (0x0 <<  6) ;- (USART) Character Length: 5 bits
-AT91C_US_CHRL_6_BITS      EQU (0x1 <<  6) ;- (USART) Character Length: 6 bits
-AT91C_US_CHRL_7_BITS      EQU (0x2 <<  6) ;- (USART) Character Length: 7 bits
-AT91C_US_CHRL_8_BITS      EQU (0x3 <<  6) ;- (USART) Character Length: 8 bits
-AT91C_US_SYNC             EQU (0x1 <<  8) ;- (USART) Synchronous Mode Select
-AT91C_US_NBSTOP           EQU (0x3 << 12) ;- (USART) Number of Stop bits
-AT91C_US_NBSTOP_1_BIT     EQU (0x0 << 12) ;- (USART) 1 stop bit
-AT91C_US_NBSTOP_15_BIT    EQU (0x1 << 12) ;- (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-AT91C_US_NBSTOP_2_BIT     EQU (0x2 << 12) ;- (USART) 2 stop bits
-AT91C_US_MSBF             EQU (0x1 << 16) ;- (USART) Bit Order
-AT91C_US_MODE9            EQU (0x1 << 17) ;- (USART) 9-bit Character length
-AT91C_US_CKLO             EQU (0x1 << 18) ;- (USART) Clock Output Select
-AT91C_US_OVER             EQU (0x1 << 19) ;- (USART) Over Sampling Mode
-AT91C_US_INACK            EQU (0x1 << 20) ;- (USART) Inhibit Non Acknowledge
-AT91C_US_DSNACK           EQU (0x1 << 21) ;- (USART) Disable Successive NACK
-AT91C_US_MAX_ITER         EQU (0x1 << 24) ;- (USART) Number of Repetitions
-AT91C_US_FILTER           EQU (0x1 << 28) ;- (USART) Receive Line Filter
-// - -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
-AT91C_US_RXBRK            EQU (0x1 <<  2) ;- (USART) Break Received/End of Break
-AT91C_US_TIMEOUT          EQU (0x1 <<  8) ;- (USART) Receiver Time-out
-AT91C_US_ITERATION        EQU (0x1 << 10) ;- (USART) Max number of Repetitions Reached
-AT91C_US_NACK             EQU (0x1 << 13) ;- (USART) Non Acknowledge
-AT91C_US_RIIC             EQU (0x1 << 16) ;- (USART) Ring INdicator Input Change Flag
-AT91C_US_DSRIC            EQU (0x1 << 17) ;- (USART) Data Set Ready Input Change Flag
-AT91C_US_DCDIC            EQU (0x1 << 18) ;- (USART) Data Carrier Flag
-AT91C_US_CTSIC            EQU (0x1 << 19) ;- (USART) Clear To Send Input Change Flag
-// - -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
-// - -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
-// - -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
-AT91C_US_RI               EQU (0x1 << 20) ;- (USART) Image of RI Input
-AT91C_US_DSR              EQU (0x1 << 21) ;- (USART) Image of DSR Input
-AT91C_US_DCD              EQU (0x1 << 22) ;- (USART) Image of DCD Input
-AT91C_US_CTS              EQU (0x1 << 23) ;- (USART) Image of CTS Input
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
-// - *****************************************************************************
-// - -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
-AT91C_SSC_RXEN            EQU (0x1 <<  0) ;- (SSC) Receive Enable
-AT91C_SSC_RXDIS           EQU (0x1 <<  1) ;- (SSC) Receive Disable
-AT91C_SSC_TXEN            EQU (0x1 <<  8) ;- (SSC) Transmit Enable
-AT91C_SSC_TXDIS           EQU (0x1 <<  9) ;- (SSC) Transmit Disable
-AT91C_SSC_SWRST           EQU (0x1 << 15) ;- (SSC) Software Reset
-// - -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
-AT91C_SSC_CKS             EQU (0x3 <<  0) ;- (SSC) Receive/Transmit Clock Selection
-AT91C_SSC_CKS_DIV         EQU (0x0) ;- (SSC) Divided Clock
-AT91C_SSC_CKS_TK          EQU (0x1) ;- (SSC) TK Clock signal
-AT91C_SSC_CKS_RK          EQU (0x2) ;- (SSC) RK pin
-AT91C_SSC_CKO             EQU (0x7 <<  2) ;- (SSC) Receive/Transmit Clock Output Mode Selection
-AT91C_SSC_CKO_NONE        EQU (0x0 <<  2) ;- (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-AT91C_SSC_CKO_CONTINOUS   EQU (0x1 <<  2) ;- (SSC) Continuous Receive/Transmit Clock RK pin: Output
-AT91C_SSC_CKO_DATA_TX     EQU (0x2 <<  2) ;- (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-AT91C_SSC_CKI             EQU (0x1 <<  5) ;- (SSC) Receive/Transmit Clock Inversion
-AT91C_SSC_START           EQU (0xF <<  8) ;- (SSC) Receive/Transmit Start Selection
-AT91C_SSC_START_CONTINOUS EQU (0x0 <<  8) ;- (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-AT91C_SSC_START_TX        EQU (0x1 <<  8) ;- (SSC) Transmit/Receive start
-AT91C_SSC_START_LOW_RF    EQU (0x2 <<  8) ;- (SSC) Detection of a low level on RF input
-AT91C_SSC_START_HIGH_RF   EQU (0x3 <<  8) ;- (SSC) Detection of a high level on RF input
-AT91C_SSC_START_FALL_RF   EQU (0x4 <<  8) ;- (SSC) Detection of a falling edge on RF input
-AT91C_SSC_START_RISE_RF   EQU (0x5 <<  8) ;- (SSC) Detection of a rising edge on RF input
-AT91C_SSC_START_LEVEL_RF  EQU (0x6 <<  8) ;- (SSC) Detection of any level change on RF input
-AT91C_SSC_START_EDGE_RF   EQU (0x7 <<  8) ;- (SSC) Detection of any edge on RF input
-AT91C_SSC_START_0         EQU (0x8 <<  8) ;- (SSC) Compare 0
-AT91C_SSC_STTDLY          EQU (0xFF << 16) ;- (SSC) Receive/Transmit Start Delay
-AT91C_SSC_PERIOD          EQU (0xFF << 24) ;- (SSC) Receive/Transmit Period Divider Selection
-// - -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
-AT91C_SSC_DATLEN          EQU (0x1F <<  0) ;- (SSC) Data Length
-AT91C_SSC_LOOP            EQU (0x1 <<  5) ;- (SSC) Loop Mode
-AT91C_SSC_MSBF            EQU (0x1 <<  7) ;- (SSC) Most Significant Bit First
-AT91C_SSC_DATNB           EQU (0xF <<  8) ;- (SSC) Data Number per Frame
-AT91C_SSC_FSLEN           EQU (0xF << 16) ;- (SSC) Receive/Transmit Frame Sync length
-AT91C_SSC_FSOS            EQU (0x7 << 20) ;- (SSC) Receive/Transmit Frame Sync Output Selection
-AT91C_SSC_FSOS_NONE       EQU (0x0 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-AT91C_SSC_FSOS_NEGATIVE   EQU (0x1 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-AT91C_SSC_FSOS_POSITIVE   EQU (0x2 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-AT91C_SSC_FSOS_LOW        EQU (0x3 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-AT91C_SSC_FSOS_HIGH       EQU (0x4 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-AT91C_SSC_FSOS_TOGGLE     EQU (0x5 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-AT91C_SSC_FSEDGE          EQU (0x1 << 24) ;- (SSC) Frame Sync Edge Detection
-// - -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
-// - -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
-AT91C_SSC_DATDEF          EQU (0x1 <<  5) ;- (SSC) Data Default Value
-AT91C_SSC_FSDEN           EQU (0x1 << 23) ;- (SSC) Frame Sync Data Enable
-// - -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
-AT91C_SSC_TXRDY           EQU (0x1 <<  0) ;- (SSC) Transmit Ready
-AT91C_SSC_TXEMPTY         EQU (0x1 <<  1) ;- (SSC) Transmit Empty
-AT91C_SSC_ENDTX           EQU (0x1 <<  2) ;- (SSC) End Of Transmission
-AT91C_SSC_TXBUFE          EQU (0x1 <<  3) ;- (SSC) Transmit Buffer Empty
-AT91C_SSC_RXRDY           EQU (0x1 <<  4) ;- (SSC) Receive Ready
-AT91C_SSC_OVRUN           EQU (0x1 <<  5) ;- (SSC) Receive Overrun
-AT91C_SSC_ENDRX           EQU (0x1 <<  6) ;- (SSC) End of Reception
-AT91C_SSC_RXBUFF          EQU (0x1 <<  7) ;- (SSC) Receive Buffer Full
-AT91C_SSC_TXSYN           EQU (0x1 << 10) ;- (SSC) Transmit Sync
-AT91C_SSC_RXSYN           EQU (0x1 << 11) ;- (SSC) Receive Sync
-AT91C_SSC_TXENA           EQU (0x1 << 16) ;- (SSC) Transmit Enable
-AT91C_SSC_RXENA           EQU (0x1 << 17) ;- (SSC) Receive Enable
-// - -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
-// - -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
-// - -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Two-wire Interface
-// - *****************************************************************************
-// - -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
-AT91C_TWI_START           EQU (0x1 <<  0) ;- (TWI) Send a START Condition
-AT91C_TWI_STOP            EQU (0x1 <<  1) ;- (TWI) Send a STOP Condition
-AT91C_TWI_MSEN            EQU (0x1 <<  2) ;- (TWI) TWI Master Transfer Enabled
-AT91C_TWI_MSDIS           EQU (0x1 <<  3) ;- (TWI) TWI Master Transfer Disabled
-AT91C_TWI_SWRST           EQU (0x1 <<  7) ;- (TWI) Software Reset
-// - -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
-AT91C_TWI_IADRSZ          EQU (0x3 <<  8) ;- (TWI) Internal Device Address Size
-AT91C_TWI_IADRSZ_NO       EQU (0x0 <<  8) ;- (TWI) No internal device address
-AT91C_TWI_IADRSZ_1_BYTE   EQU (0x1 <<  8) ;- (TWI) One-byte internal device address
-AT91C_TWI_IADRSZ_2_BYTE   EQU (0x2 <<  8) ;- (TWI) Two-byte internal device address
-AT91C_TWI_IADRSZ_3_BYTE   EQU (0x3 <<  8) ;- (TWI) Three-byte internal device address
-AT91C_TWI_MREAD           EQU (0x1 << 12) ;- (TWI) Master Read Direction
-AT91C_TWI_DADR            EQU (0x7F << 16) ;- (TWI) Device Address
-// - -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
-AT91C_TWI_CLDIV           EQU (0xFF <<  0) ;- (TWI) Clock Low Divider
-AT91C_TWI_CHDIV           EQU (0xFF <<  8) ;- (TWI) Clock High Divider
-AT91C_TWI_CKDIV           EQU (0x7 << 16) ;- (TWI) Clock Divider
-// - -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
-AT91C_TWI_TXCOMP          EQU (0x1 <<  0) ;- (TWI) Transmission Completed
-AT91C_TWI_RXRDY           EQU (0x1 <<  1) ;- (TWI) Receive holding register ReaDY
-AT91C_TWI_TXRDY           EQU (0x1 <<  2) ;- (TWI) Transmit holding register ReaDY
-AT91C_TWI_OVRE            EQU (0x1 <<  6) ;- (TWI) Overrun Error
-AT91C_TWI_UNRE            EQU (0x1 <<  7) ;- (TWI) Underrun Error
-AT91C_TWI_NACK            EQU (0x1 <<  8) ;- (TWI) Not Acknowledged
-// - -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
-// - -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
-// - -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
-// - *****************************************************************************
-// - -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- 
-AT91C_PWMC_CPRE           EQU (0xF <<  0) ;- (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
-AT91C_PWMC_CPRE_MCK       EQU (0x0) ;- (PWMC_CH) 
-AT91C_PWMC_CPRE_MCKA      EQU (0xB) ;- (PWMC_CH) 
-AT91C_PWMC_CPRE_MCKB      EQU (0xC) ;- (PWMC_CH) 
-AT91C_PWMC_CALG           EQU (0x1 <<  8) ;- (PWMC_CH) Channel Alignment
-AT91C_PWMC_CPOL           EQU (0x1 <<  9) ;- (PWMC_CH) Channel Polarity
-AT91C_PWMC_CPD            EQU (0x1 << 10) ;- (PWMC_CH) Channel Update Period
-// - -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- 
-AT91C_PWMC_CDTY           EQU (0x0 <<  0) ;- (PWMC_CH) Channel Duty Cycle
-// - -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- 
-AT91C_PWMC_CPRD           EQU (0x0 <<  0) ;- (PWMC_CH) Channel Period
-// - -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- 
-AT91C_PWMC_CCNT           EQU (0x0 <<  0) ;- (PWMC_CH) Channel Counter
-// - -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- 
-AT91C_PWMC_CUPD           EQU (0x0 <<  0) ;- (PWMC_CH) Channel Update
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
-// - *****************************************************************************
-// - -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- 
-AT91C_PWMC_DIVA           EQU (0xFF <<  0) ;- (PWMC) CLKA divide factor.
-AT91C_PWMC_PREA           EQU (0xF <<  8) ;- (PWMC) Divider Input Clock Prescaler A
-AT91C_PWMC_PREA_MCK       EQU (0x0 <<  8) ;- (PWMC) 
-AT91C_PWMC_DIVB           EQU (0xFF << 16) ;- (PWMC) CLKB divide factor.
-AT91C_PWMC_PREB           EQU (0xF << 24) ;- (PWMC) Divider Input Clock Prescaler B
-AT91C_PWMC_PREB_MCK       EQU (0x0 << 24) ;- (PWMC) 
-// - -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- 
-AT91C_PWMC_CHID0          EQU (0x1 <<  0) ;- (PWMC) Channel ID 0
-AT91C_PWMC_CHID1          EQU (0x1 <<  1) ;- (PWMC) Channel ID 1
-AT91C_PWMC_CHID2          EQU (0x1 <<  2) ;- (PWMC) Channel ID 2
-AT91C_PWMC_CHID3          EQU (0x1 <<  3) ;- (PWMC) Channel ID 3
-// - -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- 
-// - -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- 
-// - -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- 
-// - -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- 
-// - -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- 
-// - -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- 
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR USB Device Interface
-// - *****************************************************************************
-// - -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
-AT91C_UDP_FRM_NUM         EQU (0x7FF <<  0) ;- (UDP) Frame Number as Defined in the Packet Field Formats
-AT91C_UDP_FRM_ERR         EQU (0x1 << 16) ;- (UDP) Frame Error
-AT91C_UDP_FRM_OK          EQU (0x1 << 17) ;- (UDP) Frame OK
-// - -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
-AT91C_UDP_FADDEN          EQU (0x1 <<  0) ;- (UDP) Function Address Enable
-AT91C_UDP_CONFG           EQU (0x1 <<  1) ;- (UDP) Configured
-AT91C_UDP_ESR             EQU (0x1 <<  2) ;- (UDP) Enable Send Resume
-AT91C_UDP_RSMINPR         EQU (0x1 <<  3) ;- (UDP) A Resume Has Been Sent to the Host
-AT91C_UDP_RMWUPE          EQU (0x1 <<  4) ;- (UDP) Remote Wake Up Enable
-// - -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
-AT91C_UDP_FADD            EQU (0xFF <<  0) ;- (UDP) Function Address Value
-AT91C_UDP_FEN             EQU (0x1 <<  8) ;- (UDP) Function Enable
-// - -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
-AT91C_UDP_EPINT0          EQU (0x1 <<  0) ;- (UDP) Endpoint 0 Interrupt
-AT91C_UDP_EPINT1          EQU (0x1 <<  1) ;- (UDP) Endpoint 0 Interrupt
-AT91C_UDP_EPINT2          EQU (0x1 <<  2) ;- (UDP) Endpoint 2 Interrupt
-AT91C_UDP_EPINT3          EQU (0x1 <<  3) ;- (UDP) Endpoint 3 Interrupt
-AT91C_UDP_EPINT4          EQU (0x1 <<  4) ;- (UDP) Endpoint 4 Interrupt
-AT91C_UDP_EPINT5          EQU (0x1 <<  5) ;- (UDP) Endpoint 5 Interrupt
-AT91C_UDP_RXSUSP          EQU (0x1 <<  8) ;- (UDP) USB Suspend Interrupt
-AT91C_UDP_RXRSM           EQU (0x1 <<  9) ;- (UDP) USB Resume Interrupt
-AT91C_UDP_EXTRSM          EQU (0x1 << 10) ;- (UDP) USB External Resume Interrupt
-AT91C_UDP_SOFINT          EQU (0x1 << 11) ;- (UDP) USB Start Of frame Interrupt
-AT91C_UDP_WAKEUP          EQU (0x1 << 13) ;- (UDP) USB Resume Interrupt
-// - -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
-// - -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
-// - -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
-AT91C_UDP_ENDBUSRES       EQU (0x1 << 12) ;- (UDP) USB End Of Bus Reset Interrupt
-// - -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
-// - -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
-AT91C_UDP_EP0             EQU (0x1 <<  0) ;- (UDP) Reset Endpoint 0
-AT91C_UDP_EP1             EQU (0x1 <<  1) ;- (UDP) Reset Endpoint 1
-AT91C_UDP_EP2             EQU (0x1 <<  2) ;- (UDP) Reset Endpoint 2
-AT91C_UDP_EP3             EQU (0x1 <<  3) ;- (UDP) Reset Endpoint 3
-AT91C_UDP_EP4             EQU (0x1 <<  4) ;- (UDP) Reset Endpoint 4
-AT91C_UDP_EP5             EQU (0x1 <<  5) ;- (UDP) Reset Endpoint 5
-// - -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
-AT91C_UDP_TXCOMP          EQU (0x1 <<  0) ;- (UDP) Generates an IN packet with data previously written in the DPR
-AT91C_UDP_RX_DATA_BK0     EQU (0x1 <<  1) ;- (UDP) Receive Data Bank 0
-AT91C_UDP_RXSETUP         EQU (0x1 <<  2) ;- (UDP) Sends STALL to the Host (Control endpoints)
-AT91C_UDP_ISOERROR        EQU (0x1 <<  3) ;- (UDP) Isochronous error (Isochronous endpoints)
-AT91C_UDP_TXPKTRDY        EQU (0x1 <<  4) ;- (UDP) Transmit Packet Ready
-AT91C_UDP_FORCESTALL      EQU (0x1 <<  5) ;- (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-AT91C_UDP_RX_DATA_BK1     EQU (0x1 <<  6) ;- (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-AT91C_UDP_DIR             EQU (0x1 <<  7) ;- (UDP) Transfer Direction
-AT91C_UDP_EPTYPE          EQU (0x7 <<  8) ;- (UDP) Endpoint type
-AT91C_UDP_EPTYPE_CTRL     EQU (0x0 <<  8) ;- (UDP) Control
-AT91C_UDP_EPTYPE_ISO_OUT  EQU (0x1 <<  8) ;- (UDP) Isochronous OUT
-AT91C_UDP_EPTYPE_BULK_OUT EQU (0x2 <<  8) ;- (UDP) Bulk OUT
-AT91C_UDP_EPTYPE_INT_OUT  EQU (0x3 <<  8) ;- (UDP) Interrupt OUT
-AT91C_UDP_EPTYPE_ISO_IN   EQU (0x5 <<  8) ;- (UDP) Isochronous IN
-AT91C_UDP_EPTYPE_BULK_IN  EQU (0x6 <<  8) ;- (UDP) Bulk IN
-AT91C_UDP_EPTYPE_INT_IN   EQU (0x7 <<  8) ;- (UDP) Interrupt IN
-AT91C_UDP_DTGLE           EQU (0x1 << 11) ;- (UDP) Data Toggle
-AT91C_UDP_EPEDS           EQU (0x1 << 15) ;- (UDP) Endpoint Enable Disable
-AT91C_UDP_RXBYTECNT       EQU (0x7FF << 16) ;- (UDP) Number Of Bytes Available in the FIFO
-// - -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- 
-AT91C_UDP_TXVDIS          EQU (0x1 <<  8) ;- (UDP) 
-AT91C_UDP_PUON            EQU (0x1 <<  9) ;- (UDP) Pull-up ON
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
-// - *****************************************************************************
-// - -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
-AT91C_TC_CLKEN            EQU (0x1 <<  0) ;- (TC) Counter Clock Enable Command
-AT91C_TC_CLKDIS           EQU (0x1 <<  1) ;- (TC) Counter Clock Disable Command
-AT91C_TC_SWTRG            EQU (0x1 <<  2) ;- (TC) Software Trigger Command
-// - -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
-AT91C_TC_CLKS             EQU (0x7 <<  0) ;- (TC) Clock Selection
-AT91C_TC_CLKS_TIMER_DIV1_CLOCK EQU (0x0) ;- (TC) Clock selected: TIMER_DIV1_CLOCK
-AT91C_TC_CLKS_TIMER_DIV2_CLOCK EQU (0x1) ;- (TC) Clock selected: TIMER_DIV2_CLOCK
-AT91C_TC_CLKS_TIMER_DIV3_CLOCK EQU (0x2) ;- (TC) Clock selected: TIMER_DIV3_CLOCK
-AT91C_TC_CLKS_TIMER_DIV4_CLOCK EQU (0x3) ;- (TC) Clock selected: TIMER_DIV4_CLOCK
-AT91C_TC_CLKS_TIMER_DIV5_CLOCK EQU (0x4) ;- (TC) Clock selected: TIMER_DIV5_CLOCK
-AT91C_TC_CLKS_XC0         EQU (0x5) ;- (TC) Clock selected: XC0
-AT91C_TC_CLKS_XC1         EQU (0x6) ;- (TC) Clock selected: XC1
-AT91C_TC_CLKS_XC2         EQU (0x7) ;- (TC) Clock selected: XC2
-AT91C_TC_CLKI             EQU (0x1 <<  3) ;- (TC) Clock Invert
-AT91C_TC_BURST            EQU (0x3 <<  4) ;- (TC) Burst Signal Selection
-AT91C_TC_BURST_NONE       EQU (0x0 <<  4) ;- (TC) The clock is not gated by an external signal
-AT91C_TC_BURST_XC0        EQU (0x1 <<  4) ;- (TC) XC0 is ANDed with the selected clock
-AT91C_TC_BURST_XC1        EQU (0x2 <<  4) ;- (TC) XC1 is ANDed with the selected clock
-AT91C_TC_BURST_XC2        EQU (0x3 <<  4) ;- (TC) XC2 is ANDed with the selected clock
-AT91C_TC_CPCSTOP          EQU (0x1 <<  6) ;- (TC) Counter Clock Stopped with RC Compare
-AT91C_TC_LDBSTOP          EQU (0x1 <<  6) ;- (TC) Counter Clock Stopped with RB Loading
-AT91C_TC_CPCDIS           EQU (0x1 <<  7) ;- (TC) Counter Clock Disable with RC Compare
-AT91C_TC_LDBDIS           EQU (0x1 <<  7) ;- (TC) Counter Clock Disabled with RB Loading
-AT91C_TC_ETRGEDG          EQU (0x3 <<  8) ;- (TC) External Trigger Edge Selection
-AT91C_TC_ETRGEDG_NONE     EQU (0x0 <<  8) ;- (TC) Edge: None
-AT91C_TC_ETRGEDG_RISING   EQU (0x1 <<  8) ;- (TC) Edge: rising edge
-AT91C_TC_ETRGEDG_FALLING  EQU (0x2 <<  8) ;- (TC) Edge: falling edge
-AT91C_TC_ETRGEDG_BOTH     EQU (0x3 <<  8) ;- (TC) Edge: each edge
-AT91C_TC_EEVTEDG          EQU (0x3 <<  8) ;- (TC) External Event Edge Selection
-AT91C_TC_EEVTEDG_NONE     EQU (0x0 <<  8) ;- (TC) Edge: None
-AT91C_TC_EEVTEDG_RISING   EQU (0x1 <<  8) ;- (TC) Edge: rising edge
-AT91C_TC_EEVTEDG_FALLING  EQU (0x2 <<  8) ;- (TC) Edge: falling edge
-AT91C_TC_EEVTEDG_BOTH     EQU (0x3 <<  8) ;- (TC) Edge: each edge
-AT91C_TC_EEVT             EQU (0x3 << 10) ;- (TC) External Event  Selection
-AT91C_TC_EEVT_TIOB        EQU (0x0 << 10) ;- (TC) Signal selected as external event: TIOB TIOB direction: input
-AT91C_TC_EEVT_XC0         EQU (0x1 << 10) ;- (TC) Signal selected as external event: XC0 TIOB direction: output
-AT91C_TC_EEVT_XC1         EQU (0x2 << 10) ;- (TC) Signal selected as external event: XC1 TIOB direction: output
-AT91C_TC_EEVT_XC2         EQU (0x3 << 10) ;- (TC) Signal selected as external event: XC2 TIOB direction: output
-AT91C_TC_ABETRG           EQU (0x1 << 10) ;- (TC) TIOA or TIOB External Trigger Selection
-AT91C_TC_ENETRG           EQU (0x1 << 12) ;- (TC) External Event Trigger enable
-AT91C_TC_WAVESEL          EQU (0x3 << 13) ;- (TC) Waveform  Selection
-AT91C_TC_WAVESEL_UP       EQU (0x0 << 13) ;- (TC) UP mode without atomatic trigger on RC Compare
-AT91C_TC_WAVESEL_UPDOWN   EQU (0x1 << 13) ;- (TC) UPDOWN mode without automatic trigger on RC Compare
-AT91C_TC_WAVESEL_UP_AUTO  EQU (0x2 << 13) ;- (TC) UP mode with automatic trigger on RC Compare
-AT91C_TC_WAVESEL_UPDOWN_AUTO EQU (0x3 << 13) ;- (TC) UPDOWN mode with automatic trigger on RC Compare
-AT91C_TC_CPCTRG           EQU (0x1 << 14) ;- (TC) RC Compare Trigger Enable
-AT91C_TC_WAVE             EQU (0x1 << 15) ;- (TC) 
-AT91C_TC_ACPA             EQU (0x3 << 16) ;- (TC) RA Compare Effect on TIOA
-AT91C_TC_ACPA_NONE        EQU (0x0 << 16) ;- (TC) Effect: none
-AT91C_TC_ACPA_SET         EQU (0x1 << 16) ;- (TC) Effect: set
-AT91C_TC_ACPA_CLEAR       EQU (0x2 << 16) ;- (TC) Effect: clear
-AT91C_TC_ACPA_TOGGLE      EQU (0x3 << 16) ;- (TC) Effect: toggle
-AT91C_TC_LDRA             EQU (0x3 << 16) ;- (TC) RA Loading Selection
-AT91C_TC_LDRA_NONE        EQU (0x0 << 16) ;- (TC) Edge: None
-AT91C_TC_LDRA_RISING      EQU (0x1 << 16) ;- (TC) Edge: rising edge of TIOA
-AT91C_TC_LDRA_FALLING     EQU (0x2 << 16) ;- (TC) Edge: falling edge of TIOA
-AT91C_TC_LDRA_BOTH        EQU (0x3 << 16) ;- (TC) Edge: each edge of TIOA
-AT91C_TC_ACPC             EQU (0x3 << 18) ;- (TC) RC Compare Effect on TIOA
-AT91C_TC_ACPC_NONE        EQU (0x0 << 18) ;- (TC) Effect: none
-AT91C_TC_ACPC_SET         EQU (0x1 << 18) ;- (TC) Effect: set
-AT91C_TC_ACPC_CLEAR       EQU (0x2 << 18) ;- (TC) Effect: clear
-AT91C_TC_ACPC_TOGGLE      EQU (0x3 << 18) ;- (TC) Effect: toggle
-AT91C_TC_LDRB             EQU (0x3 << 18) ;- (TC) RB Loading Selection
-AT91C_TC_LDRB_NONE        EQU (0x0 << 18) ;- (TC) Edge: None
-AT91C_TC_LDRB_RISING      EQU (0x1 << 18) ;- (TC) Edge: rising edge of TIOA
-AT91C_TC_LDRB_FALLING     EQU (0x2 << 18) ;- (TC) Edge: falling edge of TIOA
-AT91C_TC_LDRB_BOTH        EQU (0x3 << 18) ;- (TC) Edge: each edge of TIOA
-AT91C_TC_AEEVT            EQU (0x3 << 20) ;- (TC) External Event Effect on TIOA
-AT91C_TC_AEEVT_NONE       EQU (0x0 << 20) ;- (TC) Effect: none
-AT91C_TC_AEEVT_SET        EQU (0x1 << 20) ;- (TC) Effect: set
-AT91C_TC_AEEVT_CLEAR      EQU (0x2 << 20) ;- (TC) Effect: clear
-AT91C_TC_AEEVT_TOGGLE     EQU (0x3 << 20) ;- (TC) Effect: toggle
-AT91C_TC_ASWTRG           EQU (0x3 << 22) ;- (TC) Software Trigger Effect on TIOA
-AT91C_TC_ASWTRG_NONE      EQU (0x0 << 22) ;- (TC) Effect: none
-AT91C_TC_ASWTRG_SET       EQU (0x1 << 22) ;- (TC) Effect: set
-AT91C_TC_ASWTRG_CLEAR     EQU (0x2 << 22) ;- (TC) Effect: clear
-AT91C_TC_ASWTRG_TOGGLE    EQU (0x3 << 22) ;- (TC) Effect: toggle
-AT91C_TC_BCPB             EQU (0x3 << 24) ;- (TC) RB Compare Effect on TIOB
-AT91C_TC_BCPB_NONE        EQU (0x0 << 24) ;- (TC) Effect: none
-AT91C_TC_BCPB_SET         EQU (0x1 << 24) ;- (TC) Effect: set
-AT91C_TC_BCPB_CLEAR       EQU (0x2 << 24) ;- (TC) Effect: clear
-AT91C_TC_BCPB_TOGGLE      EQU (0x3 << 24) ;- (TC) Effect: toggle
-AT91C_TC_BCPC             EQU (0x3 << 26) ;- (TC) RC Compare Effect on TIOB
-AT91C_TC_BCPC_NONE        EQU (0x0 << 26) ;- (TC) Effect: none
-AT91C_TC_BCPC_SET         EQU (0x1 << 26) ;- (TC) Effect: set
-AT91C_TC_BCPC_CLEAR       EQU (0x2 << 26) ;- (TC) Effect: clear
-AT91C_TC_BCPC_TOGGLE      EQU (0x3 << 26) ;- (TC) Effect: toggle
-AT91C_TC_BEEVT            EQU (0x3 << 28) ;- (TC) External Event Effect on TIOB
-AT91C_TC_BEEVT_NONE       EQU (0x0 << 28) ;- (TC) Effect: none
-AT91C_TC_BEEVT_SET        EQU (0x1 << 28) ;- (TC) Effect: set
-AT91C_TC_BEEVT_CLEAR      EQU (0x2 << 28) ;- (TC) Effect: clear
-AT91C_TC_BEEVT_TOGGLE     EQU (0x3 << 28) ;- (TC) Effect: toggle
-AT91C_TC_BSWTRG           EQU (0x3 << 30) ;- (TC) Software Trigger Effect on TIOB
-AT91C_TC_BSWTRG_NONE      EQU (0x0 << 30) ;- (TC) Effect: none
-AT91C_TC_BSWTRG_SET       EQU (0x1 << 30) ;- (TC) Effect: set
-AT91C_TC_BSWTRG_CLEAR     EQU (0x2 << 30) ;- (TC) Effect: clear
-AT91C_TC_BSWTRG_TOGGLE    EQU (0x3 << 30) ;- (TC) Effect: toggle
-// - -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
-AT91C_TC_COVFS            EQU (0x1 <<  0) ;- (TC) Counter Overflow
-AT91C_TC_LOVRS            EQU (0x1 <<  1) ;- (TC) Load Overrun
-AT91C_TC_CPAS             EQU (0x1 <<  2) ;- (TC) RA Compare
-AT91C_TC_CPBS             EQU (0x1 <<  3) ;- (TC) RB Compare
-AT91C_TC_CPCS             EQU (0x1 <<  4) ;- (TC) RC Compare
-AT91C_TC_LDRAS            EQU (0x1 <<  5) ;- (TC) RA Loading
-AT91C_TC_LDRBS            EQU (0x1 <<  6) ;- (TC) RB Loading
-AT91C_TC_ETRGS            EQU (0x1 <<  7) ;- (TC) External Trigger
-AT91C_TC_CLKSTA           EQU (0x1 << 16) ;- (TC) Clock Enabling
-AT91C_TC_MTIOA            EQU (0x1 << 17) ;- (TC) TIOA Mirror
-AT91C_TC_MTIOB            EQU (0x1 << 18) ;- (TC) TIOA Mirror
-// - -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
-// - -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
-// - -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Timer Counter Interface
-// - *****************************************************************************
-// - -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
-AT91C_TCB_SYNC            EQU (0x1 <<  0) ;- (TCB) Synchro Command
-// - -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
-AT91C_TCB_TC0XC0S         EQU (0x3 <<  0) ;- (TCB) External Clock Signal 0 Selection
-AT91C_TCB_TC0XC0S_TCLK0   EQU (0x0) ;- (TCB) TCLK0 connected to XC0
-AT91C_TCB_TC0XC0S_NONE    EQU (0x1) ;- (TCB) None signal connected to XC0
-AT91C_TCB_TC0XC0S_TIOA1   EQU (0x2) ;- (TCB) TIOA1 connected to XC0
-AT91C_TCB_TC0XC0S_TIOA2   EQU (0x3) ;- (TCB) TIOA2 connected to XC0
-AT91C_TCB_TC1XC1S         EQU (0x3 <<  2) ;- (TCB) External Clock Signal 1 Selection
-AT91C_TCB_TC1XC1S_TCLK1   EQU (0x0 <<  2) ;- (TCB) TCLK1 connected to XC1
-AT91C_TCB_TC1XC1S_NONE    EQU (0x1 <<  2) ;- (TCB) None signal connected to XC1
-AT91C_TCB_TC1XC1S_TIOA0   EQU (0x2 <<  2) ;- (TCB) TIOA0 connected to XC1
-AT91C_TCB_TC1XC1S_TIOA2   EQU (0x3 <<  2) ;- (TCB) TIOA2 connected to XC1
-AT91C_TCB_TC2XC2S         EQU (0x3 <<  4) ;- (TCB) External Clock Signal 2 Selection
-AT91C_TCB_TC2XC2S_TCLK2   EQU (0x0 <<  4) ;- (TCB) TCLK2 connected to XC2
-AT91C_TCB_TC2XC2S_NONE    EQU (0x1 <<  4) ;- (TCB) None signal connected to XC2
-AT91C_TCB_TC2XC2S_TIOA0   EQU (0x2 <<  4) ;- (TCB) TIOA0 connected to XC2
-AT91C_TCB_TC2XC2S_TIOA1   EQU (0x3 <<  4) ;- (TCB) TIOA2 connected to XC2
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface
-// - *****************************************************************************
-// - -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- 
-AT91C_CAN_MTIMEMARK       EQU (0xFFFF <<  0) ;- (CAN_MB) Mailbox Timemark
-AT91C_CAN_PRIOR           EQU (0xF << 16) ;- (CAN_MB) Mailbox Priority
-AT91C_CAN_MOT             EQU (0x7 << 24) ;- (CAN_MB) Mailbox Object Type
-AT91C_CAN_MOT_DIS         EQU (0x0 << 24) ;- (CAN_MB) 
-AT91C_CAN_MOT_RX          EQU (0x1 << 24) ;- (CAN_MB) 
-AT91C_CAN_MOT_RXOVERWRITE EQU (0x2 << 24) ;- (CAN_MB) 
-AT91C_CAN_MOT_TX          EQU (0x3 << 24) ;- (CAN_MB) 
-AT91C_CAN_MOT_CONSUMER    EQU (0x4 << 24) ;- (CAN_MB) 
-AT91C_CAN_MOT_PRODUCER    EQU (0x5 << 24) ;- (CAN_MB) 
-// - -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- 
-AT91C_CAN_MIDvB           EQU (0x3FFFF <<  0) ;- (CAN_MB) Complementary bits for identifier in extended mode
-AT91C_CAN_MIDvA           EQU (0x7FF << 18) ;- (CAN_MB) Identifier for standard frame mode
-AT91C_CAN_MIDE            EQU (0x1 << 29) ;- (CAN_MB) Identifier Version
-// - -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- 
-// - -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- 
-// - -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- 
-AT91C_CAN_MTIMESTAMP      EQU (0xFFFF <<  0) ;- (CAN_MB) Timer Value
-AT91C_CAN_MDLC            EQU (0xF << 16) ;- (CAN_MB) Mailbox Data Length Code
-AT91C_CAN_MRTR            EQU (0x1 << 20) ;- (CAN_MB) Mailbox Remote Transmission Request
-AT91C_CAN_MABT            EQU (0x1 << 22) ;- (CAN_MB) Mailbox Message Abort
-AT91C_CAN_MRDY            EQU (0x1 << 23) ;- (CAN_MB) Mailbox Ready
-AT91C_CAN_MMI             EQU (0x1 << 24) ;- (CAN_MB) Mailbox Message Ignored
-// - -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- 
-// - -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- 
-// - -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- 
-AT91C_CAN_MACR            EQU (0x1 << 22) ;- (CAN_MB) Abort Request for Mailbox
-AT91C_CAN_MTCR            EQU (0x1 << 23) ;- (CAN_MB) Mailbox Transfer Command
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Control Area Network Interface
-// - *****************************************************************************
-// - -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- 
-AT91C_CAN_CANEN           EQU (0x1 <<  0) ;- (CAN) CAN Controller Enable
-AT91C_CAN_LPM             EQU (0x1 <<  1) ;- (CAN) Disable/Enable Low Power Mode
-AT91C_CAN_ABM             EQU (0x1 <<  2) ;- (CAN) Disable/Enable Autobaud/Listen Mode
-AT91C_CAN_OVL             EQU (0x1 <<  3) ;- (CAN) Disable/Enable Overload Frame
-AT91C_CAN_TEOF            EQU (0x1 <<  4) ;- (CAN) Time Stamp messages at each end of Frame
-AT91C_CAN_TTM             EQU (0x1 <<  5) ;- (CAN) Disable/Enable Time Trigger Mode
-AT91C_CAN_TIMFRZ          EQU (0x1 <<  6) ;- (CAN) Enable Timer Freeze
-AT91C_CAN_DRPT            EQU (0x1 <<  7) ;- (CAN) Disable Repeat
-// - -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- 
-AT91C_CAN_MB0             EQU (0x1 <<  0) ;- (CAN) Mailbox 0 Flag
-AT91C_CAN_MB1             EQU (0x1 <<  1) ;- (CAN) Mailbox 1 Flag
-AT91C_CAN_MB2             EQU (0x1 <<  2) ;- (CAN) Mailbox 2 Flag
-AT91C_CAN_MB3             EQU (0x1 <<  3) ;- (CAN) Mailbox 3 Flag
-AT91C_CAN_MB4             EQU (0x1 <<  4) ;- (CAN) Mailbox 4 Flag
-AT91C_CAN_MB5             EQU (0x1 <<  5) ;- (CAN) Mailbox 5 Flag
-AT91C_CAN_MB6             EQU (0x1 <<  6) ;- (CAN) Mailbox 6 Flag
-AT91C_CAN_MB7             EQU (0x1 <<  7) ;- (CAN) Mailbox 7 Flag
-AT91C_CAN_MB8             EQU (0x1 <<  8) ;- (CAN) Mailbox 8 Flag
-AT91C_CAN_MB9             EQU (0x1 <<  9) ;- (CAN) Mailbox 9 Flag
-AT91C_CAN_MB10            EQU (0x1 << 10) ;- (CAN) Mailbox 10 Flag
-AT91C_CAN_MB11            EQU (0x1 << 11) ;- (CAN) Mailbox 11 Flag
-AT91C_CAN_MB12            EQU (0x1 << 12) ;- (CAN) Mailbox 12 Flag
-AT91C_CAN_MB13            EQU (0x1 << 13) ;- (CAN) Mailbox 13 Flag
-AT91C_CAN_MB14            EQU (0x1 << 14) ;- (CAN) Mailbox 14 Flag
-AT91C_CAN_MB15            EQU (0x1 << 15) ;- (CAN) Mailbox 15 Flag
-AT91C_CAN_ERRA            EQU (0x1 << 16) ;- (CAN) Error Active Mode Flag
-AT91C_CAN_WARN            EQU (0x1 << 17) ;- (CAN) Warning Limit Flag
-AT91C_CAN_ERRP            EQU (0x1 << 18) ;- (CAN) Error Passive Mode Flag
-AT91C_CAN_BOFF            EQU (0x1 << 19) ;- (CAN) Bus Off Mode Flag
-AT91C_CAN_SLEEP           EQU (0x1 << 20) ;- (CAN) Sleep Flag
-AT91C_CAN_WAKEUP          EQU (0x1 << 21) ;- (CAN) Wakeup Flag
-AT91C_CAN_TOVF            EQU (0x1 << 22) ;- (CAN) Timer Overflow Flag
-AT91C_CAN_TSTP            EQU (0x1 << 23) ;- (CAN) Timestamp Flag
-AT91C_CAN_CERR            EQU (0x1 << 24) ;- (CAN) CRC Error
-AT91C_CAN_SERR            EQU (0x1 << 25) ;- (CAN) Stuffing Error
-AT91C_CAN_AERR            EQU (0x1 << 26) ;- (CAN) Acknowledgment Error
-AT91C_CAN_FERR            EQU (0x1 << 27) ;- (CAN) Form Error
-AT91C_CAN_BERR            EQU (0x1 << 28) ;- (CAN) Bit Error
-// - -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- 
-// - -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- 
-// - -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- 
-AT91C_CAN_RBSY            EQU (0x1 << 29) ;- (CAN) Receiver Busy
-AT91C_CAN_TBSY            EQU (0x1 << 30) ;- (CAN) Transmitter Busy
-AT91C_CAN_OVLY            EQU (0x1 << 31) ;- (CAN) Overload Busy
-// - -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- 
-AT91C_CAN_PHASE2          EQU (0x7 <<  0) ;- (CAN) Phase 2 segment
-AT91C_CAN_PHASE1          EQU (0x7 <<  4) ;- (CAN) Phase 1 segment
-AT91C_CAN_PROPAG          EQU (0x7 <<  8) ;- (CAN) Programmation time segment
-AT91C_CAN_SYNC            EQU (0x3 << 12) ;- (CAN) Re-synchronization jump width segment
-AT91C_CAN_BRP             EQU (0x7F << 16) ;- (CAN) Baudrate Prescaler
-AT91C_CAN_SMP             EQU (0x1 << 24) ;- (CAN) Sampling mode
-// - -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- 
-AT91C_CAN_TIMER           EQU (0xFFFF <<  0) ;- (CAN) Timer field
-// - -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- 
-// - -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- 
-AT91C_CAN_REC             EQU (0xFF <<  0) ;- (CAN) Receive Error Counter
-AT91C_CAN_TEC             EQU (0xFF << 16) ;- (CAN) Transmit Error Counter
-// - -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- 
-AT91C_CAN_TIMRST          EQU (0x1 << 31) ;- (CAN) Timer Reset Field
-// - -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- 
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
-// - *****************************************************************************
-// - -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- 
-AT91C_EMAC_LB             EQU (0x1 <<  0) ;- (EMAC) Loopback. Optional. When set, loopback signal is at high level.
-AT91C_EMAC_LLB            EQU (0x1 <<  1) ;- (EMAC) Loopback local. 
-AT91C_EMAC_RE             EQU (0x1 <<  2) ;- (EMAC) Receive enable. 
-AT91C_EMAC_TE             EQU (0x1 <<  3) ;- (EMAC) Transmit enable. 
-AT91C_EMAC_MPE            EQU (0x1 <<  4) ;- (EMAC) Management port enable. 
-AT91C_EMAC_CLRSTAT        EQU (0x1 <<  5) ;- (EMAC) Clear statistics registers. 
-AT91C_EMAC_INCSTAT        EQU (0x1 <<  6) ;- (EMAC) Increment statistics registers. 
-AT91C_EMAC_WESTAT         EQU (0x1 <<  7) ;- (EMAC) Write enable for statistics registers. 
-AT91C_EMAC_BP             EQU (0x1 <<  8) ;- (EMAC) Back pressure. 
-AT91C_EMAC_TSTART         EQU (0x1 <<  9) ;- (EMAC) Start Transmission. 
-AT91C_EMAC_THALT          EQU (0x1 << 10) ;- (EMAC) Transmission Halt. 
-AT91C_EMAC_TPFR           EQU (0x1 << 11) ;- (EMAC) Transmit pause frame 
-AT91C_EMAC_TZQ            EQU (0x1 << 12) ;- (EMAC) Transmit zero quantum pause frame
-// - -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- 
-AT91C_EMAC_SPD            EQU (0x1 <<  0) ;- (EMAC) Speed. 
-AT91C_EMAC_FD             EQU (0x1 <<  1) ;- (EMAC) Full duplex. 
-AT91C_EMAC_JFRAME         EQU (0x1 <<  3) ;- (EMAC) Jumbo Frames. 
-AT91C_EMAC_CAF            EQU (0x1 <<  4) ;- (EMAC) Copy all frames. 
-AT91C_EMAC_NBC            EQU (0x1 <<  5) ;- (EMAC) No broadcast. 
-AT91C_EMAC_MTI            EQU (0x1 <<  6) ;- (EMAC) Multicast hash event enable
-AT91C_EMAC_UNI            EQU (0x1 <<  7) ;- (EMAC) Unicast hash enable. 
-AT91C_EMAC_BIG            EQU (0x1 <<  8) ;- (EMAC) Receive 1522 bytes. 
-AT91C_EMAC_EAE            EQU (0x1 <<  9) ;- (EMAC) External address match enable. 
-AT91C_EMAC_CLK            EQU (0x3 << 10) ;- (EMAC) 
-AT91C_EMAC_CLK_HCLK_8     EQU (0x0 << 10) ;- (EMAC) HCLK divided by 8
-AT91C_EMAC_CLK_HCLK_16    EQU (0x1 << 10) ;- (EMAC) HCLK divided by 16
-AT91C_EMAC_CLK_HCLK_32    EQU (0x2 << 10) ;- (EMAC) HCLK divided by 32
-AT91C_EMAC_CLK_HCLK_64    EQU (0x3 << 10) ;- (EMAC) HCLK divided by 64
-AT91C_EMAC_RTY            EQU (0x1 << 12) ;- (EMAC) 
-AT91C_EMAC_PAE            EQU (0x1 << 13) ;- (EMAC) 
-AT91C_EMAC_RBOF           EQU (0x3 << 14) ;- (EMAC) 
-AT91C_EMAC_RBOF_OFFSET_0  EQU (0x0 << 14) ;- (EMAC) no offset from start of receive buffer
-AT91C_EMAC_RBOF_OFFSET_1  EQU (0x1 << 14) ;- (EMAC) one byte offset from start of receive buffer
-AT91C_EMAC_RBOF_OFFSET_2  EQU (0x2 << 14) ;- (EMAC) two bytes offset from start of receive buffer
-AT91C_EMAC_RBOF_OFFSET_3  EQU (0x3 << 14) ;- (EMAC) three bytes offset from start of receive buffer
-AT91C_EMAC_RLCE           EQU (0x1 << 16) ;- (EMAC) Receive Length field Checking Enable
-AT91C_EMAC_DRFCS          EQU (0x1 << 17) ;- (EMAC) Discard Receive FCS
-AT91C_EMAC_EFRHD          EQU (0x1 << 18) ;- (EMAC) 
-AT91C_EMAC_IRXFCS         EQU (0x1 << 19) ;- (EMAC) Ignore RX FCS
-// - -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- 
-AT91C_EMAC_LINKR          EQU (0x1 <<  0) ;- (EMAC) 
-AT91C_EMAC_MDIO           EQU (0x1 <<  1) ;- (EMAC) 
-AT91C_EMAC_IDLE           EQU (0x1 <<  2) ;- (EMAC) 
-// - -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- 
-AT91C_EMAC_UBR            EQU (0x1 <<  0) ;- (EMAC) 
-AT91C_EMAC_COL            EQU (0x1 <<  1) ;- (EMAC) 
-AT91C_EMAC_RLES           EQU (0x1 <<  2) ;- (EMAC) 
-AT91C_EMAC_TGO            EQU (0x1 <<  3) ;- (EMAC) Transmit Go
-AT91C_EMAC_BEX            EQU (0x1 <<  4) ;- (EMAC) Buffers exhausted mid frame
-AT91C_EMAC_COMP           EQU (0x1 <<  5) ;- (EMAC) 
-AT91C_EMAC_UND            EQU (0x1 <<  6) ;- (EMAC) 
-// - -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- 
-AT91C_EMAC_BNA            EQU (0x1 <<  0) ;- (EMAC) 
-AT91C_EMAC_REC            EQU (0x1 <<  1) ;- (EMAC) 
-AT91C_EMAC_OVR            EQU (0x1 <<  2) ;- (EMAC) 
-// - -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- 
-AT91C_EMAC_MFD            EQU (0x1 <<  0) ;- (EMAC) 
-AT91C_EMAC_RCOMP          EQU (0x1 <<  1) ;- (EMAC) 
-AT91C_EMAC_RXUBR          EQU (0x1 <<  2) ;- (EMAC) 
-AT91C_EMAC_TXUBR          EQU (0x1 <<  3) ;- (EMAC) 
-AT91C_EMAC_TUNDR          EQU (0x1 <<  4) ;- (EMAC) 
-AT91C_EMAC_RLEX           EQU (0x1 <<  5) ;- (EMAC) 
-AT91C_EMAC_TXERR          EQU (0x1 <<  6) ;- (EMAC) 
-AT91C_EMAC_TCOMP          EQU (0x1 <<  7) ;- (EMAC) 
-AT91C_EMAC_LINK           EQU (0x1 <<  9) ;- (EMAC) 
-AT91C_EMAC_ROVR           EQU (0x1 << 10) ;- (EMAC) 
-AT91C_EMAC_HRESP          EQU (0x1 << 11) ;- (EMAC) 
-AT91C_EMAC_PFRE           EQU (0x1 << 12) ;- (EMAC) 
-AT91C_EMAC_PTZ            EQU (0x1 << 13) ;- (EMAC) 
-// - -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- 
-// - -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- 
-// - -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- 
-// - -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- 
-AT91C_EMAC_DATA           EQU (0xFFFF <<  0) ;- (EMAC) 
-AT91C_EMAC_CODE           EQU (0x3 << 16) ;- (EMAC) 
-AT91C_EMAC_REGA           EQU (0x1F << 18) ;- (EMAC) 
-AT91C_EMAC_PHYA           EQU (0x1F << 23) ;- (EMAC) 
-AT91C_EMAC_RW             EQU (0x3 << 28) ;- (EMAC) 
-AT91C_EMAC_SOF            EQU (0x3 << 30) ;- (EMAC) 
-// - -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- 
-AT91C_EMAC_RMII           EQU (0x1 <<  0) ;- (EMAC) Reduce MII
-// - -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- 
-AT91C_EMAC_IP             EQU (0xFFFF <<  0) ;- (EMAC) ARP request IP address
-AT91C_EMAC_MAG            EQU (0x1 << 16) ;- (EMAC) Magic packet event enable
-AT91C_EMAC_ARP            EQU (0x1 << 17) ;- (EMAC) ARP request event enable
-AT91C_EMAC_SA1            EQU (0x1 << 18) ;- (EMAC) Specific address register 1 event enable
-// - -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- 
-AT91C_EMAC_REVREF         EQU (0xFFFF <<  0) ;- (EMAC) 
-AT91C_EMAC_PARTREF        EQU (0xFFFF << 16) ;- (EMAC) 
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
-// - *****************************************************************************
-// - -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
-AT91C_ADC_SWRST           EQU (0x1 <<  0) ;- (ADC) Software Reset
-AT91C_ADC_START           EQU (0x1 <<  1) ;- (ADC) Start Conversion
-// - -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 
-AT91C_ADC_TRGEN           EQU (0x1 <<  0) ;- (ADC) Trigger Enable
-AT91C_ADC_TRGEN_DIS       EQU (0x0) ;- (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
-AT91C_ADC_TRGEN_EN        EQU (0x1) ;- (ADC) Hardware trigger selected by TRGSEL field is enabled.
-AT91C_ADC_TRGSEL          EQU (0x7 <<  1) ;- (ADC) Trigger Selection
-AT91C_ADC_TRGSEL_TIOA0    EQU (0x0 <<  1) ;- (ADC) Selected TRGSEL = TIAO0
-AT91C_ADC_TRGSEL_TIOA1    EQU (0x1 <<  1) ;- (ADC) Selected TRGSEL = TIAO1
-AT91C_ADC_TRGSEL_TIOA2    EQU (0x2 <<  1) ;- (ADC) Selected TRGSEL = TIAO2
-AT91C_ADC_TRGSEL_TIOA3    EQU (0x3 <<  1) ;- (ADC) Selected TRGSEL = TIAO3
-AT91C_ADC_TRGSEL_TIOA4    EQU (0x4 <<  1) ;- (ADC) Selected TRGSEL = TIAO4
-AT91C_ADC_TRGSEL_TIOA5    EQU (0x5 <<  1) ;- (ADC) Selected TRGSEL = TIAO5
-AT91C_ADC_TRGSEL_EXT      EQU (0x6 <<  1) ;- (ADC) Selected TRGSEL = External Trigger
-AT91C_ADC_LOWRES          EQU (0x1 <<  4) ;- (ADC) Resolution.
-AT91C_ADC_LOWRES_10_BIT   EQU (0x0 <<  4) ;- (ADC) 10-bit resolution
-AT91C_ADC_LOWRES_8_BIT    EQU (0x1 <<  4) ;- (ADC) 8-bit resolution
-AT91C_ADC_SLEEP           EQU (0x1 <<  5) ;- (ADC) Sleep Mode
-AT91C_ADC_SLEEP_NORMAL_MODE EQU (0x0 <<  5) ;- (ADC) Normal Mode
-AT91C_ADC_SLEEP_MODE      EQU (0x1 <<  5) ;- (ADC) Sleep Mode
-AT91C_ADC_PRESCAL         EQU (0x3F <<  8) ;- (ADC) Prescaler rate selection
-AT91C_ADC_STARTUP         EQU (0x1F << 16) ;- (ADC) Startup Time
-AT91C_ADC_SHTIM           EQU (0xF << 24) ;- (ADC) Sample & Hold Time
-// - -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 
-AT91C_ADC_CH0             EQU (0x1 <<  0) ;- (ADC) Channel 0
-AT91C_ADC_CH1             EQU (0x1 <<  1) ;- (ADC) Channel 1
-AT91C_ADC_CH2             EQU (0x1 <<  2) ;- (ADC) Channel 2
-AT91C_ADC_CH3             EQU (0x1 <<  3) ;- (ADC) Channel 3
-AT91C_ADC_CH4             EQU (0x1 <<  4) ;- (ADC) Channel 4
-AT91C_ADC_CH5             EQU (0x1 <<  5) ;- (ADC) Channel 5
-AT91C_ADC_CH6             EQU (0x1 <<  6) ;- (ADC) Channel 6
-AT91C_ADC_CH7             EQU (0x1 <<  7) ;- (ADC) Channel 7
-// - -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 
-// - -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 
-// - -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 
-AT91C_ADC_EOC0            EQU (0x1 <<  0) ;- (ADC) End of Conversion
-AT91C_ADC_EOC1            EQU (0x1 <<  1) ;- (ADC) End of Conversion
-AT91C_ADC_EOC2            EQU (0x1 <<  2) ;- (ADC) End of Conversion
-AT91C_ADC_EOC3            EQU (0x1 <<  3) ;- (ADC) End of Conversion
-AT91C_ADC_EOC4            EQU (0x1 <<  4) ;- (ADC) End of Conversion
-AT91C_ADC_EOC5            EQU (0x1 <<  5) ;- (ADC) End of Conversion
-AT91C_ADC_EOC6            EQU (0x1 <<  6) ;- (ADC) End of Conversion
-AT91C_ADC_EOC7            EQU (0x1 <<  7) ;- (ADC) End of Conversion
-AT91C_ADC_OVRE0           EQU (0x1 <<  8) ;- (ADC) Overrun Error
-AT91C_ADC_OVRE1           EQU (0x1 <<  9) ;- (ADC) Overrun Error
-AT91C_ADC_OVRE2           EQU (0x1 << 10) ;- (ADC) Overrun Error
-AT91C_ADC_OVRE3           EQU (0x1 << 11) ;- (ADC) Overrun Error
-AT91C_ADC_OVRE4           EQU (0x1 << 12) ;- (ADC) Overrun Error
-AT91C_ADC_OVRE5           EQU (0x1 << 13) ;- (ADC) Overrun Error
-AT91C_ADC_OVRE6           EQU (0x1 << 14) ;- (ADC) Overrun Error
-AT91C_ADC_OVRE7           EQU (0x1 << 15) ;- (ADC) Overrun Error
-AT91C_ADC_DRDY            EQU (0x1 << 16) ;- (ADC) Data Ready
-AT91C_ADC_GOVRE           EQU (0x1 << 17) ;- (ADC) General Overrun
-AT91C_ADC_ENDRX           EQU (0x1 << 18) ;- (ADC) End of Receiver Transfer
-AT91C_ADC_RXBUFF          EQU (0x1 << 19) ;- (ADC) RXBUFF Interrupt
-// - -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 
-AT91C_ADC_LDATA           EQU (0x3FF <<  0) ;- (ADC) Last Data Converted
-// - -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 
-// - -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 
-// - -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 
-// - -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 
-AT91C_ADC_DATA            EQU (0x3FF <<  0) ;- (ADC) Converted Data
-// - -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 
-// - -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 
-// - -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 
-// - -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 
-// - -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 
-// - -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 
-// - -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard
-// - *****************************************************************************
-// - -------- AES_CR : (AES Offset: 0x0) Control Register -------- 
-AT91C_AES_START           EQU (0x1 <<  0) ;- (AES) Starts Processing
-AT91C_AES_SWRST           EQU (0x1 <<  8) ;- (AES) Software Reset
-AT91C_AES_LOADSEED        EQU (0x1 << 16) ;- (AES) Random Number Generator Seed Loading
-// - -------- AES_MR : (AES Offset: 0x4) Mode Register -------- 
-AT91C_AES_CIPHER          EQU (0x1 <<  0) ;- (AES) Processing Mode
-AT91C_AES_PROCDLY         EQU (0xF <<  4) ;- (AES) Processing Delay
-AT91C_AES_SMOD            EQU (0x3 <<  8) ;- (AES) Start Mode
-AT91C_AES_SMOD_MANUAL     EQU (0x0 <<  8) ;- (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
-AT91C_AES_SMOD_AUTO       EQU (0x1 <<  8) ;- (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
-AT91C_AES_SMOD_PDC        EQU (0x2 <<  8) ;- (AES) PDC Mode (cf datasheet).
-AT91C_AES_OPMOD           EQU (0x7 << 12) ;- (AES) Operation Mode
-AT91C_AES_OPMOD_ECB       EQU (0x0 << 12) ;- (AES) ECB Electronic CodeBook mode.
-AT91C_AES_OPMOD_CBC       EQU (0x1 << 12) ;- (AES) CBC Cipher Block Chaining mode.
-AT91C_AES_OPMOD_OFB       EQU (0x2 << 12) ;- (AES) OFB Output Feedback mode.
-AT91C_AES_OPMOD_CFB       EQU (0x3 << 12) ;- (AES) CFB Cipher Feedback mode.
-AT91C_AES_OPMOD_CTR       EQU (0x4 << 12) ;- (AES) CTR Counter mode.
-AT91C_AES_LOD             EQU (0x1 << 15) ;- (AES) Last Output Data Mode
-AT91C_AES_CFBS            EQU (0x7 << 16) ;- (AES) Cipher Feedback Data Size
-AT91C_AES_CFBS_128_BIT    EQU (0x0 << 16) ;- (AES) 128-bit.
-AT91C_AES_CFBS_64_BIT     EQU (0x1 << 16) ;- (AES) 64-bit.
-AT91C_AES_CFBS_32_BIT     EQU (0x2 << 16) ;- (AES) 32-bit.
-AT91C_AES_CFBS_16_BIT     EQU (0x3 << 16) ;- (AES) 16-bit.
-AT91C_AES_CFBS_8_BIT      EQU (0x4 << 16) ;- (AES) 8-bit.
-AT91C_AES_CKEY            EQU (0xF << 20) ;- (AES) Countermeasure Key
-AT91C_AES_CTYPE           EQU (0x1F << 24) ;- (AES) Countermeasure Type
-AT91C_AES_CTYPE_TYPE1_EN  EQU (0x1 << 24) ;- (AES) Countermeasure type 1 is enabled.
-AT91C_AES_CTYPE_TYPE2_EN  EQU (0x2 << 24) ;- (AES) Countermeasure type 2 is enabled.
-AT91C_AES_CTYPE_TYPE3_EN  EQU (0x4 << 24) ;- (AES) Countermeasure type 3 is enabled.
-AT91C_AES_CTYPE_TYPE4_EN  EQU (0x8 << 24) ;- (AES) Countermeasure type 4 is enabled.
-AT91C_AES_CTYPE_TYPE5_EN  EQU (0x10 << 24) ;- (AES) Countermeasure type 5 is enabled.
-// - -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- 
-AT91C_AES_DATRDY          EQU (0x1 <<  0) ;- (AES) DATRDY
-AT91C_AES_ENDRX           EQU (0x1 <<  1) ;- (AES) PDC Read Buffer End
-AT91C_AES_ENDTX           EQU (0x1 <<  2) ;- (AES) PDC Write Buffer End
-AT91C_AES_RXBUFF          EQU (0x1 <<  3) ;- (AES) PDC Read Buffer Full
-AT91C_AES_TXBUFE          EQU (0x1 <<  4) ;- (AES) PDC Write Buffer Empty
-AT91C_AES_URAD            EQU (0x1 <<  8) ;- (AES) Unspecified Register Access Detection
-// - -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- 
-// - -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- 
-// - -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- 
-AT91C_AES_URAT            EQU (0x7 << 12) ;- (AES) Unspecified Register Access Type Status
-AT91C_AES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (AES) Input data register written during the data processing in PDC mode.
-AT91C_AES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (AES) Output data register read during the data processing.
-AT91C_AES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (AES) Mode register written during the data processing.
-AT91C_AES_URAT_OUT_DAT_READ_SUBKEY EQU (0x3 << 12) ;- (AES) Output data register read during the sub-keys generation.
-AT91C_AES_URAT_MODEREG_WRITE_SUBKEY EQU (0x4 << 12) ;- (AES) Mode register written during the sub-keys generation.
-AT91C_AES_URAT_WO_REG_READ EQU (0x5 << 12) ;- (AES) Write-only register read access.
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard
-// - *****************************************************************************
-// - -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- 
-AT91C_TDES_START          EQU (0x1 <<  0) ;- (TDES) Starts Processing
-AT91C_TDES_SWRST          EQU (0x1 <<  8) ;- (TDES) Software Reset
-// - -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- 
-AT91C_TDES_CIPHER         EQU (0x1 <<  0) ;- (TDES) Processing Mode
-AT91C_TDES_TDESMOD        EQU (0x1 <<  1) ;- (TDES) Single or Triple DES Mode
-AT91C_TDES_KEYMOD         EQU (0x1 <<  4) ;- (TDES) Key Mode
-AT91C_TDES_SMOD           EQU (0x3 <<  8) ;- (TDES) Start Mode
-AT91C_TDES_SMOD_MANUAL    EQU (0x0 <<  8) ;- (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
-AT91C_TDES_SMOD_AUTO      EQU (0x1 <<  8) ;- (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
-AT91C_TDES_SMOD_PDC       EQU (0x2 <<  8) ;- (TDES) PDC Mode (cf datasheet).
-AT91C_TDES_OPMOD          EQU (0x3 << 12) ;- (TDES) Operation Mode
-AT91C_TDES_OPMOD_ECB      EQU (0x0 << 12) ;- (TDES) ECB Electronic CodeBook mode.
-AT91C_TDES_OPMOD_CBC      EQU (0x1 << 12) ;- (TDES) CBC Cipher Block Chaining mode.
-AT91C_TDES_OPMOD_OFB      EQU (0x2 << 12) ;- (TDES) OFB Output Feedback mode.
-AT91C_TDES_OPMOD_CFB      EQU (0x3 << 12) ;- (TDES) CFB Cipher Feedback mode.
-AT91C_TDES_LOD            EQU (0x1 << 15) ;- (TDES) Last Output Data Mode
-AT91C_TDES_CFBS           EQU (0x3 << 16) ;- (TDES) Cipher Feedback Data Size
-AT91C_TDES_CFBS_64_BIT    EQU (0x0 << 16) ;- (TDES) 64-bit.
-AT91C_TDES_CFBS_32_BIT    EQU (0x1 << 16) ;- (TDES) 32-bit.
-AT91C_TDES_CFBS_16_BIT    EQU (0x2 << 16) ;- (TDES) 16-bit.
-AT91C_TDES_CFBS_8_BIT     EQU (0x3 << 16) ;- (TDES) 8-bit.
-// - -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- 
-AT91C_TDES_DATRDY         EQU (0x1 <<  0) ;- (TDES) DATRDY
-AT91C_TDES_ENDRX          EQU (0x1 <<  1) ;- (TDES) PDC Read Buffer End
-AT91C_TDES_ENDTX          EQU (0x1 <<  2) ;- (TDES) PDC Write Buffer End
-AT91C_TDES_RXBUFF         EQU (0x1 <<  3) ;- (TDES) PDC Read Buffer Full
-AT91C_TDES_TXBUFE         EQU (0x1 <<  4) ;- (TDES) PDC Write Buffer Empty
-AT91C_TDES_URAD           EQU (0x1 <<  8) ;- (TDES) Unspecified Register Access Detection
-// - -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- 
-// - -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- 
-// - -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- 
-AT91C_TDES_URAT           EQU (0x3 << 12) ;- (TDES) Unspecified Register Access Type Status
-AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (TDES) Input data register written during the data processing in PDC mode.
-AT91C_TDES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (TDES) Output data register read during the data processing.
-AT91C_TDES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (TDES) Mode register written during the data processing.
-AT91C_TDES_URAT_WO_REG_READ EQU (0x3 << 12) ;- (TDES) Write-only register read access.
-
-// - *****************************************************************************
-// -               REGISTER ADDRESS DEFINITION FOR AT91SAM7X128
-// - *****************************************************************************
-// - ========== Register definition for SYS peripheral ========== 
-// - ========== Register definition for AIC peripheral ========== 
-AT91C_AIC_IVR             EQU (0xFFFFF100) ;- (AIC) IRQ Vector Register
-AT91C_AIC_SMR             EQU (0xFFFFF000) ;- (AIC) Source Mode Register
-AT91C_AIC_FVR             EQU (0xFFFFF104) ;- (AIC) FIQ Vector Register
-AT91C_AIC_DCR             EQU (0xFFFFF138) ;- (AIC) Debug Control Register (Protect)
-AT91C_AIC_EOICR           EQU (0xFFFFF130) ;- (AIC) End of Interrupt Command Register
-AT91C_AIC_SVR             EQU (0xFFFFF080) ;- (AIC) Source Vector Register
-AT91C_AIC_FFSR            EQU (0xFFFFF148) ;- (AIC) Fast Forcing Status Register
-AT91C_AIC_ICCR            EQU (0xFFFFF128) ;- (AIC) Interrupt Clear Command Register
-AT91C_AIC_ISR             EQU (0xFFFFF108) ;- (AIC) Interrupt Status Register
-AT91C_AIC_IMR             EQU (0xFFFFF110) ;- (AIC) Interrupt Mask Register
-AT91C_AIC_IPR             EQU (0xFFFFF10C) ;- (AIC) Interrupt Pending Register
-AT91C_AIC_FFER            EQU (0xFFFFF140) ;- (AIC) Fast Forcing Enable Register
-AT91C_AIC_IECR            EQU (0xFFFFF120) ;- (AIC) Interrupt Enable Command Register
-AT91C_AIC_ISCR            EQU (0xFFFFF12C) ;- (AIC) Interrupt Set Command Register
-AT91C_AIC_FFDR            EQU (0xFFFFF144) ;- (AIC) Fast Forcing Disable Register
-AT91C_AIC_CISR            EQU (0xFFFFF114) ;- (AIC) Core Interrupt Status Register
-AT91C_AIC_IDCR            EQU (0xFFFFF124) ;- (AIC) Interrupt Disable Command Register
-AT91C_AIC_SPU             EQU (0xFFFFF134) ;- (AIC) Spurious Vector Register
-// - ========== Register definition for PDC_DBGU peripheral ========== 
-AT91C_DBGU_TCR            EQU (0xFFFFF30C) ;- (PDC_DBGU) Transmit Counter Register
-AT91C_DBGU_RNPR           EQU (0xFFFFF310) ;- (PDC_DBGU) Receive Next Pointer Register
-AT91C_DBGU_TNPR           EQU (0xFFFFF318) ;- (PDC_DBGU) Transmit Next Pointer Register
-AT91C_DBGU_TPR            EQU (0xFFFFF308) ;- (PDC_DBGU) Transmit Pointer Register
-AT91C_DBGU_RPR            EQU (0xFFFFF300) ;- (PDC_DBGU) Receive Pointer Register
-AT91C_DBGU_RCR            EQU (0xFFFFF304) ;- (PDC_DBGU) Receive Counter Register
-AT91C_DBGU_RNCR           EQU (0xFFFFF314) ;- (PDC_DBGU) Receive Next Counter Register
-AT91C_DBGU_PTCR           EQU (0xFFFFF320) ;- (PDC_DBGU) PDC Transfer Control Register
-AT91C_DBGU_PTSR           EQU (0xFFFFF324) ;- (PDC_DBGU) PDC Transfer Status Register
-AT91C_DBGU_TNCR           EQU (0xFFFFF31C) ;- (PDC_DBGU) Transmit Next Counter Register
-// - ========== Register definition for DBGU peripheral ========== 
-AT91C_DBGU_EXID           EQU (0xFFFFF244) ;- (DBGU) Chip ID Extension Register
-AT91C_DBGU_BRGR           EQU (0xFFFFF220) ;- (DBGU) Baud Rate Generator Register
-AT91C_DBGU_IDR            EQU (0xFFFFF20C) ;- (DBGU) Interrupt Disable Register
-AT91C_DBGU_CSR            EQU (0xFFFFF214) ;- (DBGU) Channel Status Register
-AT91C_DBGU_CIDR           EQU (0xFFFFF240) ;- (DBGU) Chip ID Register
-AT91C_DBGU_MR             EQU (0xFFFFF204) ;- (DBGU) Mode Register
-AT91C_DBGU_IMR            EQU (0xFFFFF210) ;- (DBGU) Interrupt Mask Register
-AT91C_DBGU_CR             EQU (0xFFFFF200) ;- (DBGU) Control Register
-AT91C_DBGU_FNTR           EQU (0xFFFFF248) ;- (DBGU) Force NTRST Register
-AT91C_DBGU_THR            EQU (0xFFFFF21C) ;- (DBGU) Transmitter Holding Register
-AT91C_DBGU_RHR            EQU (0xFFFFF218) ;- (DBGU) Receiver Holding Register
-AT91C_DBGU_IER            EQU (0xFFFFF208) ;- (DBGU) Interrupt Enable Register
-// - ========== Register definition for PIOA peripheral ========== 
-AT91C_PIOA_ODR            EQU (0xFFFFF414) ;- (PIOA) Output Disable Registerr
-AT91C_PIOA_SODR           EQU (0xFFFFF430) ;- (PIOA) Set Output Data Register
-AT91C_PIOA_ISR            EQU (0xFFFFF44C) ;- (PIOA) Interrupt Status Register
-AT91C_PIOA_ABSR           EQU (0xFFFFF478) ;- (PIOA) AB Select Status Register
-AT91C_PIOA_IER            EQU (0xFFFFF440) ;- (PIOA) Interrupt Enable Register
-AT91C_PIOA_PPUDR          EQU (0xFFFFF460) ;- (PIOA) Pull-up Disable Register
-AT91C_PIOA_IMR            EQU (0xFFFFF448) ;- (PIOA) Interrupt Mask Register
-AT91C_PIOA_PER            EQU (0xFFFFF400) ;- (PIOA) PIO Enable Register
-AT91C_PIOA_IFDR           EQU (0xFFFFF424) ;- (PIOA) Input Filter Disable Register
-AT91C_PIOA_OWDR           EQU (0xFFFFF4A4) ;- (PIOA) Output Write Disable Register
-AT91C_PIOA_MDSR           EQU (0xFFFFF458) ;- (PIOA) Multi-driver Status Register
-AT91C_PIOA_IDR            EQU (0xFFFFF444) ;- (PIOA) Interrupt Disable Register
-AT91C_PIOA_ODSR           EQU (0xFFFFF438) ;- (PIOA) Output Data Status Register
-AT91C_PIOA_PPUSR          EQU (0xFFFFF468) ;- (PIOA) Pull-up Status Register
-AT91C_PIOA_OWSR           EQU (0xFFFFF4A8) ;- (PIOA) Output Write Status Register
-AT91C_PIOA_BSR            EQU (0xFFFFF474) ;- (PIOA) Select B Register
-AT91C_PIOA_OWER           EQU (0xFFFFF4A0) ;- (PIOA) Output Write Enable Register
-AT91C_PIOA_IFER           EQU (0xFFFFF420) ;- (PIOA) Input Filter Enable Register
-AT91C_PIOA_PDSR           EQU (0xFFFFF43C) ;- (PIOA) Pin Data Status Register
-AT91C_PIOA_PPUER          EQU (0xFFFFF464) ;- (PIOA) Pull-up Enable Register
-AT91C_PIOA_OSR            EQU (0xFFFFF418) ;- (PIOA) Output Status Register
-AT91C_PIOA_ASR            EQU (0xFFFFF470) ;- (PIOA) Select A Register
-AT91C_PIOA_MDDR           EQU (0xFFFFF454) ;- (PIOA) Multi-driver Disable Register
-AT91C_PIOA_CODR           EQU (0xFFFFF434) ;- (PIOA) Clear Output Data Register
-AT91C_PIOA_MDER           EQU (0xFFFFF450) ;- (PIOA) Multi-driver Enable Register
-AT91C_PIOA_PDR            EQU (0xFFFFF404) ;- (PIOA) PIO Disable Register
-AT91C_PIOA_IFSR           EQU (0xFFFFF428) ;- (PIOA) Input Filter Status Register
-AT91C_PIOA_OER            EQU (0xFFFFF410) ;- (PIOA) Output Enable Register
-AT91C_PIOA_PSR            EQU (0xFFFFF408) ;- (PIOA) PIO Status Register
-// - ========== Register definition for PIOB peripheral ========== 
-AT91C_PIOB_OWDR           EQU (0xFFFFF6A4) ;- (PIOB) Output Write Disable Register
-AT91C_PIOB_MDER           EQU (0xFFFFF650) ;- (PIOB) Multi-driver Enable Register
-AT91C_PIOB_PPUSR          EQU (0xFFFFF668) ;- (PIOB) Pull-up Status Register
-AT91C_PIOB_IMR            EQU (0xFFFFF648) ;- (PIOB) Interrupt Mask Register
-AT91C_PIOB_ASR            EQU (0xFFFFF670) ;- (PIOB) Select A Register
-AT91C_PIOB_PPUDR          EQU (0xFFFFF660) ;- (PIOB) Pull-up Disable Register
-AT91C_PIOB_PSR            EQU (0xFFFFF608) ;- (PIOB) PIO Status Register
-AT91C_PIOB_IER            EQU (0xFFFFF640) ;- (PIOB) Interrupt Enable Register
-AT91C_PIOB_CODR           EQU (0xFFFFF634) ;- (PIOB) Clear Output Data Register
-AT91C_PIOB_OWER           EQU (0xFFFFF6A0) ;- (PIOB) Output Write Enable Register
-AT91C_PIOB_ABSR           EQU (0xFFFFF678) ;- (PIOB) AB Select Status Register
-AT91C_PIOB_IFDR           EQU (0xFFFFF624) ;- (PIOB) Input Filter Disable Register
-AT91C_PIOB_PDSR           EQU (0xFFFFF63C) ;- (PIOB) Pin Data Status Register
-AT91C_PIOB_IDR            EQU (0xFFFFF644) ;- (PIOB) Interrupt Disable Register
-AT91C_PIOB_OWSR           EQU (0xFFFFF6A8) ;- (PIOB) Output Write Status Register
-AT91C_PIOB_PDR            EQU (0xFFFFF604) ;- (PIOB) PIO Disable Register
-AT91C_PIOB_ODR            EQU (0xFFFFF614) ;- (PIOB) Output Disable Registerr
-AT91C_PIOB_IFSR           EQU (0xFFFFF628) ;- (PIOB) Input Filter Status Register
-AT91C_PIOB_PPUER          EQU (0xFFFFF664) ;- (PIOB) Pull-up Enable Register
-AT91C_PIOB_SODR           EQU (0xFFFFF630) ;- (PIOB) Set Output Data Register
-AT91C_PIOB_ISR            EQU (0xFFFFF64C) ;- (PIOB) Interrupt Status Register
-AT91C_PIOB_ODSR           EQU (0xFFFFF638) ;- (PIOB) Output Data Status Register
-AT91C_PIOB_OSR            EQU (0xFFFFF618) ;- (PIOB) Output Status Register
-AT91C_PIOB_MDSR           EQU (0xFFFFF658) ;- (PIOB) Multi-driver Status Register
-AT91C_PIOB_IFER           EQU (0xFFFFF620) ;- (PIOB) Input Filter Enable Register
-AT91C_PIOB_BSR            EQU (0xFFFFF674) ;- (PIOB) Select B Register
-AT91C_PIOB_MDDR           EQU (0xFFFFF654) ;- (PIOB) Multi-driver Disable Register
-AT91C_PIOB_OER            EQU (0xFFFFF610) ;- (PIOB) Output Enable Register
-AT91C_PIOB_PER            EQU (0xFFFFF600) ;- (PIOB) PIO Enable Register
-// - ========== Register definition for CKGR peripheral ========== 
-AT91C_CKGR_MOR            EQU (0xFFFFFC20) ;- (CKGR) Main Oscillator Register
-AT91C_CKGR_PLLR           EQU (0xFFFFFC2C) ;- (CKGR) PLL Register
-AT91C_CKGR_MCFR           EQU (0xFFFFFC24) ;- (CKGR) Main Clock  Frequency Register
-// - ========== Register definition for PMC peripheral ========== 
-AT91C_PMC_IDR             EQU (0xFFFFFC64) ;- (PMC) Interrupt Disable Register
-AT91C_PMC_MOR             EQU (0xFFFFFC20) ;- (PMC) Main Oscillator Register
-AT91C_PMC_PLLR            EQU (0xFFFFFC2C) ;- (PMC) PLL Register
-AT91C_PMC_PCER            EQU (0xFFFFFC10) ;- (PMC) Peripheral Clock Enable Register
-AT91C_PMC_PCKR            EQU (0xFFFFFC40) ;- (PMC) Programmable Clock Register
-AT91C_PMC_MCKR            EQU (0xFFFFFC30) ;- (PMC) Master Clock Register
-AT91C_PMC_SCDR            EQU (0xFFFFFC04) ;- (PMC) System Clock Disable Register
-AT91C_PMC_PCDR            EQU (0xFFFFFC14) ;- (PMC) Peripheral Clock Disable Register
-AT91C_PMC_SCSR            EQU (0xFFFFFC08) ;- (PMC) System Clock Status Register
-AT91C_PMC_PCSR            EQU (0xFFFFFC18) ;- (PMC) Peripheral Clock Status Register
-AT91C_PMC_MCFR            EQU (0xFFFFFC24) ;- (PMC) Main Clock  Frequency Register
-AT91C_PMC_SCER            EQU (0xFFFFFC00) ;- (PMC) System Clock Enable Register
-AT91C_PMC_IMR             EQU (0xFFFFFC6C) ;- (PMC) Interrupt Mask Register
-AT91C_PMC_IER             EQU (0xFFFFFC60) ;- (PMC) Interrupt Enable Register
-AT91C_PMC_SR              EQU (0xFFFFFC68) ;- (PMC) Status Register
-// - ========== Register definition for RSTC peripheral ========== 
-AT91C_RSTC_RCR            EQU (0xFFFFFD00) ;- (RSTC) Reset Control Register
-AT91C_RSTC_RMR            EQU (0xFFFFFD08) ;- (RSTC) Reset Mode Register
-AT91C_RSTC_RSR            EQU (0xFFFFFD04) ;- (RSTC) Reset Status Register
-// - ========== Register definition for RTTC peripheral ========== 
-AT91C_RTTC_RTSR           EQU (0xFFFFFD2C) ;- (RTTC) Real-time Status Register
-AT91C_RTTC_RTMR           EQU (0xFFFFFD20) ;- (RTTC) Real-time Mode Register
-AT91C_RTTC_RTVR           EQU (0xFFFFFD28) ;- (RTTC) Real-time Value Register
-AT91C_RTTC_RTAR           EQU (0xFFFFFD24) ;- (RTTC) Real-time Alarm Register
-// - ========== Register definition for PITC peripheral ========== 
-AT91C_PITC_PIVR           EQU (0xFFFFFD38) ;- (PITC) Period Interval Value Register
-AT91C_PITC_PISR           EQU (0xFFFFFD34) ;- (PITC) Period Interval Status Register
-AT91C_PITC_PIIR           EQU (0xFFFFFD3C) ;- (PITC) Period Interval Image Register
-AT91C_PITC_PIMR           EQU (0xFFFFFD30) ;- (PITC) Period Interval Mode Register
-// - ========== Register definition for WDTC peripheral ========== 
-AT91C_WDTC_WDCR           EQU (0xFFFFFD40) ;- (WDTC) Watchdog Control Register
-AT91C_WDTC_WDSR           EQU (0xFFFFFD48) ;- (WDTC) Watchdog Status Register
-AT91C_WDTC_WDMR           EQU (0xFFFFFD44) ;- (WDTC) Watchdog Mode Register
-// - ========== Register definition for VREG peripheral ========== 
-AT91C_VREG_MR             EQU (0xFFFFFD60) ;- (VREG) Voltage Regulator Mode Register
-// - ========== Register definition for MC peripheral ========== 
-AT91C_MC_ASR              EQU (0xFFFFFF04) ;- (MC) MC Abort Status Register
-AT91C_MC_RCR              EQU (0xFFFFFF00) ;- (MC) MC Remap Control Register
-AT91C_MC_FCR              EQU (0xFFFFFF64) ;- (MC) MC Flash Command Register
-AT91C_MC_AASR             EQU (0xFFFFFF08) ;- (MC) MC Abort Address Status Register
-AT91C_MC_FSR              EQU (0xFFFFFF68) ;- (MC) MC Flash Status Register
-AT91C_MC_FMR              EQU (0xFFFFFF60) ;- (MC) MC Flash Mode Register
-// - ========== Register definition for PDC_SPI1 peripheral ========== 
-AT91C_SPI1_PTCR           EQU (0xFFFE4120) ;- (PDC_SPI1) PDC Transfer Control Register
-AT91C_SPI1_RPR            EQU (0xFFFE4100) ;- (PDC_SPI1) Receive Pointer Register
-AT91C_SPI1_TNCR           EQU (0xFFFE411C) ;- (PDC_SPI1) Transmit Next Counter Register
-AT91C_SPI1_TPR            EQU (0xFFFE4108) ;- (PDC_SPI1) Transmit Pointer Register
-AT91C_SPI1_TNPR           EQU (0xFFFE4118) ;- (PDC_SPI1) Transmit Next Pointer Register
-AT91C_SPI1_TCR            EQU (0xFFFE410C) ;- (PDC_SPI1) Transmit Counter Register
-AT91C_SPI1_RCR            EQU (0xFFFE4104) ;- (PDC_SPI1) Receive Counter Register
-AT91C_SPI1_RNPR           EQU (0xFFFE4110) ;- (PDC_SPI1) Receive Next Pointer Register
-AT91C_SPI1_RNCR           EQU (0xFFFE4114) ;- (PDC_SPI1) Receive Next Counter Register
-AT91C_SPI1_PTSR           EQU (0xFFFE4124) ;- (PDC_SPI1) PDC Transfer Status Register
-// - ========== Register definition for SPI1 peripheral ========== 
-AT91C_SPI1_IMR            EQU (0xFFFE401C) ;- (SPI1) Interrupt Mask Register
-AT91C_SPI1_IER            EQU (0xFFFE4014) ;- (SPI1) Interrupt Enable Register
-AT91C_SPI1_MR             EQU (0xFFFE4004) ;- (SPI1) Mode Register
-AT91C_SPI1_RDR            EQU (0xFFFE4008) ;- (SPI1) Receive Data Register
-AT91C_SPI1_IDR            EQU (0xFFFE4018) ;- (SPI1) Interrupt Disable Register
-AT91C_SPI1_SR             EQU (0xFFFE4010) ;- (SPI1) Status Register
-AT91C_SPI1_TDR            EQU (0xFFFE400C) ;- (SPI1) Transmit Data Register
-AT91C_SPI1_CR             EQU (0xFFFE4000) ;- (SPI1) Control Register
-AT91C_SPI1_CSR            EQU (0xFFFE4030) ;- (SPI1) Chip Select Register
-// - ========== Register definition for PDC_SPI0 peripheral ========== 
-AT91C_SPI0_PTCR           EQU (0xFFFE0120) ;- (PDC_SPI0) PDC Transfer Control Register
-AT91C_SPI0_TPR            EQU (0xFFFE0108) ;- (PDC_SPI0) Transmit Pointer Register
-AT91C_SPI0_TCR            EQU (0xFFFE010C) ;- (PDC_SPI0) Transmit Counter Register
-AT91C_SPI0_RCR            EQU (0xFFFE0104) ;- (PDC_SPI0) Receive Counter Register
-AT91C_SPI0_PTSR           EQU (0xFFFE0124) ;- (PDC_SPI0) PDC Transfer Status Register
-AT91C_SPI0_RNPR           EQU (0xFFFE0110) ;- (PDC_SPI0) Receive Next Pointer Register
-AT91C_SPI0_RPR            EQU (0xFFFE0100) ;- (PDC_SPI0) Receive Pointer Register
-AT91C_SPI0_TNCR           EQU (0xFFFE011C) ;- (PDC_SPI0) Transmit Next Counter Register
-AT91C_SPI0_RNCR           EQU (0xFFFE0114) ;- (PDC_SPI0) Receive Next Counter Register
-AT91C_SPI0_TNPR           EQU (0xFFFE0118) ;- (PDC_SPI0) Transmit Next Pointer Register
-// - ========== Register definition for SPI0 peripheral ========== 
-AT91C_SPI0_IER            EQU (0xFFFE0014) ;- (SPI0) Interrupt Enable Register
-AT91C_SPI0_SR             EQU (0xFFFE0010) ;- (SPI0) Status Register
-AT91C_SPI0_IDR            EQU (0xFFFE0018) ;- (SPI0) Interrupt Disable Register
-AT91C_SPI0_CR             EQU (0xFFFE0000) ;- (SPI0) Control Register
-AT91C_SPI0_MR             EQU (0xFFFE0004) ;- (SPI0) Mode Register
-AT91C_SPI0_IMR            EQU (0xFFFE001C) ;- (SPI0) Interrupt Mask Register
-AT91C_SPI0_TDR            EQU (0xFFFE000C) ;- (SPI0) Transmit Data Register
-AT91C_SPI0_RDR            EQU (0xFFFE0008) ;- (SPI0) Receive Data Register
-AT91C_SPI0_CSR            EQU (0xFFFE0030) ;- (SPI0) Chip Select Register
-// - ========== Register definition for PDC_US1 peripheral ========== 
-AT91C_US1_RNCR            EQU (0xFFFC4114) ;- (PDC_US1) Receive Next Counter Register
-AT91C_US1_PTCR            EQU (0xFFFC4120) ;- (PDC_US1) PDC Transfer Control Register
-AT91C_US1_TCR             EQU (0xFFFC410C) ;- (PDC_US1) Transmit Counter Register
-AT91C_US1_PTSR            EQU (0xFFFC4124) ;- (PDC_US1) PDC Transfer Status Register
-AT91C_US1_TNPR            EQU (0xFFFC4118) ;- (PDC_US1) Transmit Next Pointer Register
-AT91C_US1_RCR             EQU (0xFFFC4104) ;- (PDC_US1) Receive Counter Register
-AT91C_US1_RNPR            EQU (0xFFFC4110) ;- (PDC_US1) Receive Next Pointer Register
-AT91C_US1_RPR             EQU (0xFFFC4100) ;- (PDC_US1) Receive Pointer Register
-AT91C_US1_TNCR            EQU (0xFFFC411C) ;- (PDC_US1) Transmit Next Counter Register
-AT91C_US1_TPR             EQU (0xFFFC4108) ;- (PDC_US1) Transmit Pointer Register
-// - ========== Register definition for US1 peripheral ========== 
-AT91C_US1_IF              EQU (0xFFFC404C) ;- (US1) IRDA_FILTER Register
-AT91C_US1_NER             EQU (0xFFFC4044) ;- (US1) Nb Errors Register
-AT91C_US1_RTOR            EQU (0xFFFC4024) ;- (US1) Receiver Time-out Register
-AT91C_US1_CSR             EQU (0xFFFC4014) ;- (US1) Channel Status Register
-AT91C_US1_IDR             EQU (0xFFFC400C) ;- (US1) Interrupt Disable Register
-AT91C_US1_IER             EQU (0xFFFC4008) ;- (US1) Interrupt Enable Register
-AT91C_US1_THR             EQU (0xFFFC401C) ;- (US1) Transmitter Holding Register
-AT91C_US1_TTGR            EQU (0xFFFC4028) ;- (US1) Transmitter Time-guard Register
-AT91C_US1_RHR             EQU (0xFFFC4018) ;- (US1) Receiver Holding Register
-AT91C_US1_BRGR            EQU (0xFFFC4020) ;- (US1) Baud Rate Generator Register
-AT91C_US1_IMR             EQU (0xFFFC4010) ;- (US1) Interrupt Mask Register
-AT91C_US1_FIDI            EQU (0xFFFC4040) ;- (US1) FI_DI_Ratio Register
-AT91C_US1_CR              EQU (0xFFFC4000) ;- (US1) Control Register
-AT91C_US1_MR              EQU (0xFFFC4004) ;- (US1) Mode Register
-// - ========== Register definition for PDC_US0 peripheral ========== 
-AT91C_US0_TNPR            EQU (0xFFFC0118) ;- (PDC_US0) Transmit Next Pointer Register
-AT91C_US0_RNPR            EQU (0xFFFC0110) ;- (PDC_US0) Receive Next Pointer Register
-AT91C_US0_TCR             EQU (0xFFFC010C) ;- (PDC_US0) Transmit Counter Register
-AT91C_US0_PTCR            EQU (0xFFFC0120) ;- (PDC_US0) PDC Transfer Control Register
-AT91C_US0_PTSR            EQU (0xFFFC0124) ;- (PDC_US0) PDC Transfer Status Register
-AT91C_US0_TNCR            EQU (0xFFFC011C) ;- (PDC_US0) Transmit Next Counter Register
-AT91C_US0_TPR             EQU (0xFFFC0108) ;- (PDC_US0) Transmit Pointer Register
-AT91C_US0_RCR             EQU (0xFFFC0104) ;- (PDC_US0) Receive Counter Register
-AT91C_US0_RPR             EQU (0xFFFC0100) ;- (PDC_US0) Receive Pointer Register
-AT91C_US0_RNCR            EQU (0xFFFC0114) ;- (PDC_US0) Receive Next Counter Register
-// - ========== Register definition for US0 peripheral ========== 
-AT91C_US0_BRGR            EQU (0xFFFC0020) ;- (US0) Baud Rate Generator Register
-AT91C_US0_NER             EQU (0xFFFC0044) ;- (US0) Nb Errors Register
-AT91C_US0_CR              EQU (0xFFFC0000) ;- (US0) Control Register
-AT91C_US0_IMR             EQU (0xFFFC0010) ;- (US0) Interrupt Mask Register
-AT91C_US0_FIDI            EQU (0xFFFC0040) ;- (US0) FI_DI_Ratio Register
-AT91C_US0_TTGR            EQU (0xFFFC0028) ;- (US0) Transmitter Time-guard Register
-AT91C_US0_MR              EQU (0xFFFC0004) ;- (US0) Mode Register
-AT91C_US0_RTOR            EQU (0xFFFC0024) ;- (US0) Receiver Time-out Register
-AT91C_US0_CSR             EQU (0xFFFC0014) ;- (US0) Channel Status Register
-AT91C_US0_RHR             EQU (0xFFFC0018) ;- (US0) Receiver Holding Register
-AT91C_US0_IDR             EQU (0xFFFC000C) ;- (US0) Interrupt Disable Register
-AT91C_US0_THR             EQU (0xFFFC001C) ;- (US0) Transmitter Holding Register
-AT91C_US0_IF              EQU (0xFFFC004C) ;- (US0) IRDA_FILTER Register
-AT91C_US0_IER             EQU (0xFFFC0008) ;- (US0) Interrupt Enable Register
-// - ========== Register definition for PDC_SSC peripheral ========== 
-AT91C_SSC_TNCR            EQU (0xFFFD411C) ;- (PDC_SSC) Transmit Next Counter Register
-AT91C_SSC_RPR             EQU (0xFFFD4100) ;- (PDC_SSC) Receive Pointer Register
-AT91C_SSC_RNCR            EQU (0xFFFD4114) ;- (PDC_SSC) Receive Next Counter Register
-AT91C_SSC_TPR             EQU (0xFFFD4108) ;- (PDC_SSC) Transmit Pointer Register
-AT91C_SSC_PTCR            EQU (0xFFFD4120) ;- (PDC_SSC) PDC Transfer Control Register
-AT91C_SSC_TCR             EQU (0xFFFD410C) ;- (PDC_SSC) Transmit Counter Register
-AT91C_SSC_RCR             EQU (0xFFFD4104) ;- (PDC_SSC) Receive Counter Register
-AT91C_SSC_RNPR            EQU (0xFFFD4110) ;- (PDC_SSC) Receive Next Pointer Register
-AT91C_SSC_TNPR            EQU (0xFFFD4118) ;- (PDC_SSC) Transmit Next Pointer Register
-AT91C_SSC_PTSR            EQU (0xFFFD4124) ;- (PDC_SSC) PDC Transfer Status Register
-// - ========== Register definition for SSC peripheral ========== 
-AT91C_SSC_RHR             EQU (0xFFFD4020) ;- (SSC) Receive Holding Register
-AT91C_SSC_RSHR            EQU (0xFFFD4030) ;- (SSC) Receive Sync Holding Register
-AT91C_SSC_TFMR            EQU (0xFFFD401C) ;- (SSC) Transmit Frame Mode Register
-AT91C_SSC_IDR             EQU (0xFFFD4048) ;- (SSC) Interrupt Disable Register
-AT91C_SSC_THR             EQU (0xFFFD4024) ;- (SSC) Transmit Holding Register
-AT91C_SSC_RCMR            EQU (0xFFFD4010) ;- (SSC) Receive Clock ModeRegister
-AT91C_SSC_IER             EQU (0xFFFD4044) ;- (SSC) Interrupt Enable Register
-AT91C_SSC_TSHR            EQU (0xFFFD4034) ;- (SSC) Transmit Sync Holding Register
-AT91C_SSC_SR              EQU (0xFFFD4040) ;- (SSC) Status Register
-AT91C_SSC_CMR             EQU (0xFFFD4004) ;- (SSC) Clock Mode Register
-AT91C_SSC_TCMR            EQU (0xFFFD4018) ;- (SSC) Transmit Clock Mode Register
-AT91C_SSC_CR              EQU (0xFFFD4000) ;- (SSC) Control Register
-AT91C_SSC_IMR             EQU (0xFFFD404C) ;- (SSC) Interrupt Mask Register
-AT91C_SSC_RFMR            EQU (0xFFFD4014) ;- (SSC) Receive Frame Mode Register
-// - ========== Register definition for TWI peripheral ========== 
-AT91C_TWI_IER             EQU (0xFFFB8024) ;- (TWI) Interrupt Enable Register
-AT91C_TWI_CR              EQU (0xFFFB8000) ;- (TWI) Control Register
-AT91C_TWI_SR              EQU (0xFFFB8020) ;- (TWI) Status Register
-AT91C_TWI_IMR             EQU (0xFFFB802C) ;- (TWI) Interrupt Mask Register
-AT91C_TWI_THR             EQU (0xFFFB8034) ;- (TWI) Transmit Holding Register
-AT91C_TWI_IDR             EQU (0xFFFB8028) ;- (TWI) Interrupt Disable Register
-AT91C_TWI_IADR            EQU (0xFFFB800C) ;- (TWI) Internal Address Register
-AT91C_TWI_MMR             EQU (0xFFFB8004) ;- (TWI) Master Mode Register
-AT91C_TWI_CWGR            EQU (0xFFFB8010) ;- (TWI) Clock Waveform Generator Register
-AT91C_TWI_RHR             EQU (0xFFFB8030) ;- (TWI) Receive Holding Register
-// - ========== Register definition for PWMC_CH3 peripheral ========== 
-AT91C_PWMC_CH3_CUPDR      EQU (0xFFFCC270) ;- (PWMC_CH3) Channel Update Register
-AT91C_PWMC_CH3_Reserved   EQU (0xFFFCC274) ;- (PWMC_CH3) Reserved
-AT91C_PWMC_CH3_CPRDR      EQU (0xFFFCC268) ;- (PWMC_CH3) Channel Period Register
-AT91C_PWMC_CH3_CDTYR      EQU (0xFFFCC264) ;- (PWMC_CH3) Channel Duty Cycle Register
-AT91C_PWMC_CH3_CCNTR      EQU (0xFFFCC26C) ;- (PWMC_CH3) Channel Counter Register
-AT91C_PWMC_CH3_CMR        EQU (0xFFFCC260) ;- (PWMC_CH3) Channel Mode Register
-// - ========== Register definition for PWMC_CH2 peripheral ========== 
-AT91C_PWMC_CH2_Reserved   EQU (0xFFFCC254) ;- (PWMC_CH2) Reserved
-AT91C_PWMC_CH2_CMR        EQU (0xFFFCC240) ;- (PWMC_CH2) Channel Mode Register
-AT91C_PWMC_CH2_CCNTR      EQU (0xFFFCC24C) ;- (PWMC_CH2) Channel Counter Register
-AT91C_PWMC_CH2_CPRDR      EQU (0xFFFCC248) ;- (PWMC_CH2) Channel Period Register
-AT91C_PWMC_CH2_CUPDR      EQU (0xFFFCC250) ;- (PWMC_CH2) Channel Update Register
-AT91C_PWMC_CH2_CDTYR      EQU (0xFFFCC244) ;- (PWMC_CH2) Channel Duty Cycle Register
-// - ========== Register definition for PWMC_CH1 peripheral ========== 
-AT91C_PWMC_CH1_Reserved   EQU (0xFFFCC234) ;- (PWMC_CH1) Reserved
-AT91C_PWMC_CH1_CUPDR      EQU (0xFFFCC230) ;- (PWMC_CH1) Channel Update Register
-AT91C_PWMC_CH1_CPRDR      EQU (0xFFFCC228) ;- (PWMC_CH1) Channel Period Register
-AT91C_PWMC_CH1_CCNTR      EQU (0xFFFCC22C) ;- (PWMC_CH1) Channel Counter Register
-AT91C_PWMC_CH1_CDTYR      EQU (0xFFFCC224) ;- (PWMC_CH1) Channel Duty Cycle Register
-AT91C_PWMC_CH1_CMR        EQU (0xFFFCC220) ;- (PWMC_CH1) Channel Mode Register
-// - ========== Register definition for PWMC_CH0 peripheral ========== 
-AT91C_PWMC_CH0_Reserved   EQU (0xFFFCC214) ;- (PWMC_CH0) Reserved
-AT91C_PWMC_CH0_CPRDR      EQU (0xFFFCC208) ;- (PWMC_CH0) Channel Period Register
-AT91C_PWMC_CH0_CDTYR      EQU (0xFFFCC204) ;- (PWMC_CH0) Channel Duty Cycle Register
-AT91C_PWMC_CH0_CMR        EQU (0xFFFCC200) ;- (PWMC_CH0) Channel Mode Register
-AT91C_PWMC_CH0_CUPDR      EQU (0xFFFCC210) ;- (PWMC_CH0) Channel Update Register
-AT91C_PWMC_CH0_CCNTR      EQU (0xFFFCC20C) ;- (PWMC_CH0) Channel Counter Register
-// - ========== Register definition for PWMC peripheral ========== 
-AT91C_PWMC_IDR            EQU (0xFFFCC014) ;- (PWMC) PWMC Interrupt Disable Register
-AT91C_PWMC_DIS            EQU (0xFFFCC008) ;- (PWMC) PWMC Disable Register
-AT91C_PWMC_IER            EQU (0xFFFCC010) ;- (PWMC) PWMC Interrupt Enable Register
-AT91C_PWMC_VR             EQU (0xFFFCC0FC) ;- (PWMC) PWMC Version Register
-AT91C_PWMC_ISR            EQU (0xFFFCC01C) ;- (PWMC) PWMC Interrupt Status Register
-AT91C_PWMC_SR             EQU (0xFFFCC00C) ;- (PWMC) PWMC Status Register
-AT91C_PWMC_IMR            EQU (0xFFFCC018) ;- (PWMC) PWMC Interrupt Mask Register
-AT91C_PWMC_MR             EQU (0xFFFCC000) ;- (PWMC) PWMC Mode Register
-AT91C_PWMC_ENA            EQU (0xFFFCC004) ;- (PWMC) PWMC Enable Register
-// - ========== Register definition for UDP peripheral ========== 
-AT91C_UDP_IMR             EQU (0xFFFB0018) ;- (UDP) Interrupt Mask Register
-AT91C_UDP_FADDR           EQU (0xFFFB0008) ;- (UDP) Function Address Register
-AT91C_UDP_NUM             EQU (0xFFFB0000) ;- (UDP) Frame Number Register
-AT91C_UDP_FDR             EQU (0xFFFB0050) ;- (UDP) Endpoint FIFO Data Register
-AT91C_UDP_ISR             EQU (0xFFFB001C) ;- (UDP) Interrupt Status Register
-AT91C_UDP_CSR             EQU (0xFFFB0030) ;- (UDP) Endpoint Control and Status Register
-AT91C_UDP_IDR             EQU (0xFFFB0014) ;- (UDP) Interrupt Disable Register
-AT91C_UDP_ICR             EQU (0xFFFB0020) ;- (UDP) Interrupt Clear Register
-AT91C_UDP_RSTEP           EQU (0xFFFB0028) ;- (UDP) Reset Endpoint Register
-AT91C_UDP_TXVC            EQU (0xFFFB0074) ;- (UDP) Transceiver Control Register
-AT91C_UDP_GLBSTATE        EQU (0xFFFB0004) ;- (UDP) Global State Register
-AT91C_UDP_IER             EQU (0xFFFB0010) ;- (UDP) Interrupt Enable Register
-// - ========== Register definition for TC0 peripheral ========== 
-AT91C_TC0_SR              EQU (0xFFFA0020) ;- (TC0) Status Register
-AT91C_TC0_RC              EQU (0xFFFA001C) ;- (TC0) Register C
-AT91C_TC0_RB              EQU (0xFFFA0018) ;- (TC0) Register B
-AT91C_TC0_CCR             EQU (0xFFFA0000) ;- (TC0) Channel Control Register
-AT91C_TC0_CMR             EQU (0xFFFA0004) ;- (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
-AT91C_TC0_IER             EQU (0xFFFA0024) ;- (TC0) Interrupt Enable Register
-AT91C_TC0_RA              EQU (0xFFFA0014) ;- (TC0) Register A
-AT91C_TC0_IDR             EQU (0xFFFA0028) ;- (TC0) Interrupt Disable Register
-AT91C_TC0_CV              EQU (0xFFFA0010) ;- (TC0) Counter Value
-AT91C_TC0_IMR             EQU (0xFFFA002C) ;- (TC0) Interrupt Mask Register
-// - ========== Register definition for TC1 peripheral ========== 
-AT91C_TC1_RB              EQU (0xFFFA0058) ;- (TC1) Register B
-AT91C_TC1_CCR             EQU (0xFFFA0040) ;- (TC1) Channel Control Register
-AT91C_TC1_IER             EQU (0xFFFA0064) ;- (TC1) Interrupt Enable Register
-AT91C_TC1_IDR             EQU (0xFFFA0068) ;- (TC1) Interrupt Disable Register
-AT91C_TC1_SR              EQU (0xFFFA0060) ;- (TC1) Status Register
-AT91C_TC1_CMR             EQU (0xFFFA0044) ;- (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
-AT91C_TC1_RA              EQU (0xFFFA0054) ;- (TC1) Register A
-AT91C_TC1_RC              EQU (0xFFFA005C) ;- (TC1) Register C
-AT91C_TC1_IMR             EQU (0xFFFA006C) ;- (TC1) Interrupt Mask Register
-AT91C_TC1_CV              EQU (0xFFFA0050) ;- (TC1) Counter Value
-// - ========== Register definition for TC2 peripheral ========== 
-AT91C_TC2_CMR             EQU (0xFFFA0084) ;- (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
-AT91C_TC2_CCR             EQU (0xFFFA0080) ;- (TC2) Channel Control Register
-AT91C_TC2_CV              EQU (0xFFFA0090) ;- (TC2) Counter Value
-AT91C_TC2_RA              EQU (0xFFFA0094) ;- (TC2) Register A
-AT91C_TC2_RB              EQU (0xFFFA0098) ;- (TC2) Register B
-AT91C_TC2_IDR             EQU (0xFFFA00A8) ;- (TC2) Interrupt Disable Register
-AT91C_TC2_IMR             EQU (0xFFFA00AC) ;- (TC2) Interrupt Mask Register
-AT91C_TC2_RC              EQU (0xFFFA009C) ;- (TC2) Register C
-AT91C_TC2_IER             EQU (0xFFFA00A4) ;- (TC2) Interrupt Enable Register
-AT91C_TC2_SR              EQU (0xFFFA00A0) ;- (TC2) Status Register
-// - ========== Register definition for TCB peripheral ========== 
-AT91C_TCB_BMR             EQU (0xFFFA00C4) ;- (TCB) TC Block Mode Register
-AT91C_TCB_BCR             EQU (0xFFFA00C0) ;- (TCB) TC Block Control Register
-// - ========== Register definition for CAN_MB0 peripheral ========== 
-AT91C_CAN_MB0_MDL         EQU (0xFFFD0214) ;- (CAN_MB0) MailBox Data Low Register
-AT91C_CAN_MB0_MAM         EQU (0xFFFD0204) ;- (CAN_MB0) MailBox Acceptance Mask Register
-AT91C_CAN_MB0_MCR         EQU (0xFFFD021C) ;- (CAN_MB0) MailBox Control Register
-AT91C_CAN_MB0_MID         EQU (0xFFFD0208) ;- (CAN_MB0) MailBox ID Register
-AT91C_CAN_MB0_MSR         EQU (0xFFFD0210) ;- (CAN_MB0) MailBox Status Register
-AT91C_CAN_MB0_MFID        EQU (0xFFFD020C) ;- (CAN_MB0) MailBox Family ID Register
-AT91C_CAN_MB0_MDH         EQU (0xFFFD0218) ;- (CAN_MB0) MailBox Data High Register
-AT91C_CAN_MB0_MMR         EQU (0xFFFD0200) ;- (CAN_MB0) MailBox Mode Register
-// - ========== Register definition for CAN_MB1 peripheral ========== 
-AT91C_CAN_MB1_MDL         EQU (0xFFFD0234) ;- (CAN_MB1) MailBox Data Low Register
-AT91C_CAN_MB1_MID         EQU (0xFFFD0228) ;- (CAN_MB1) MailBox ID Register
-AT91C_CAN_MB1_MMR         EQU (0xFFFD0220) ;- (CAN_MB1) MailBox Mode Register
-AT91C_CAN_MB1_MSR         EQU (0xFFFD0230) ;- (CAN_MB1) MailBox Status Register
-AT91C_CAN_MB1_MAM         EQU (0xFFFD0224) ;- (CAN_MB1) MailBox Acceptance Mask Register
-AT91C_CAN_MB1_MDH         EQU (0xFFFD0238) ;- (CAN_MB1) MailBox Data High Register
-AT91C_CAN_MB1_MCR         EQU (0xFFFD023C) ;- (CAN_MB1) MailBox Control Register
-AT91C_CAN_MB1_MFID        EQU (0xFFFD022C) ;- (CAN_MB1) MailBox Family ID Register
-// - ========== Register definition for CAN_MB2 peripheral ========== 
-AT91C_CAN_MB2_MCR         EQU (0xFFFD025C) ;- (CAN_MB2) MailBox Control Register
-AT91C_CAN_MB2_MDH         EQU (0xFFFD0258) ;- (CAN_MB2) MailBox Data High Register
-AT91C_CAN_MB2_MID         EQU (0xFFFD0248) ;- (CAN_MB2) MailBox ID Register
-AT91C_CAN_MB2_MDL         EQU (0xFFFD0254) ;- (CAN_MB2) MailBox Data Low Register
-AT91C_CAN_MB2_MMR         EQU (0xFFFD0240) ;- (CAN_MB2) MailBox Mode Register
-AT91C_CAN_MB2_MAM         EQU (0xFFFD0244) ;- (CAN_MB2) MailBox Acceptance Mask Register
-AT91C_CAN_MB2_MFID        EQU (0xFFFD024C) ;- (CAN_MB2) MailBox Family ID Register
-AT91C_CAN_MB2_MSR         EQU (0xFFFD0250) ;- (CAN_MB2) MailBox Status Register
-// - ========== Register definition for CAN_MB3 peripheral ========== 
-AT91C_CAN_MB3_MFID        EQU (0xFFFD026C) ;- (CAN_MB3) MailBox Family ID Register
-AT91C_CAN_MB3_MAM         EQU (0xFFFD0264) ;- (CAN_MB3) MailBox Acceptance Mask Register
-AT91C_CAN_MB3_MID         EQU (0xFFFD0268) ;- (CAN_MB3) MailBox ID Register
-AT91C_CAN_MB3_MCR         EQU (0xFFFD027C) ;- (CAN_MB3) MailBox Control Register
-AT91C_CAN_MB3_MMR         EQU (0xFFFD0260) ;- (CAN_MB3) MailBox Mode Register
-AT91C_CAN_MB3_MSR         EQU (0xFFFD0270) ;- (CAN_MB3) MailBox Status Register
-AT91C_CAN_MB3_MDL         EQU (0xFFFD0274) ;- (CAN_MB3) MailBox Data Low Register
-AT91C_CAN_MB3_MDH         EQU (0xFFFD0278) ;- (CAN_MB3) MailBox Data High Register
-// - ========== Register definition for CAN_MB4 peripheral ========== 
-AT91C_CAN_MB4_MID         EQU (0xFFFD0288) ;- (CAN_MB4) MailBox ID Register
-AT91C_CAN_MB4_MMR         EQU (0xFFFD0280) ;- (CAN_MB4) MailBox Mode Register
-AT91C_CAN_MB4_MDH         EQU (0xFFFD0298) ;- (CAN_MB4) MailBox Data High Register
-AT91C_CAN_MB4_MFID        EQU (0xFFFD028C) ;- (CAN_MB4) MailBox Family ID Register
-AT91C_CAN_MB4_MSR         EQU (0xFFFD0290) ;- (CAN_MB4) MailBox Status Register
-AT91C_CAN_MB4_MCR         EQU (0xFFFD029C) ;- (CAN_MB4) MailBox Control Register
-AT91C_CAN_MB4_MDL         EQU (0xFFFD0294) ;- (CAN_MB4) MailBox Data Low Register
-AT91C_CAN_MB4_MAM         EQU (0xFFFD0284) ;- (CAN_MB4) MailBox Acceptance Mask Register
-// - ========== Register definition for CAN_MB5 peripheral ========== 
-AT91C_CAN_MB5_MSR         EQU (0xFFFD02B0) ;- (CAN_MB5) MailBox Status Register
-AT91C_CAN_MB5_MCR         EQU (0xFFFD02BC) ;- (CAN_MB5) MailBox Control Register
-AT91C_CAN_MB5_MFID        EQU (0xFFFD02AC) ;- (CAN_MB5) MailBox Family ID Register
-AT91C_CAN_MB5_MDH         EQU (0xFFFD02B8) ;- (CAN_MB5) MailBox Data High Register
-AT91C_CAN_MB5_MID         EQU (0xFFFD02A8) ;- (CAN_MB5) MailBox ID Register
-AT91C_CAN_MB5_MMR         EQU (0xFFFD02A0) ;- (CAN_MB5) MailBox Mode Register
-AT91C_CAN_MB5_MDL         EQU (0xFFFD02B4) ;- (CAN_MB5) MailBox Data Low Register
-AT91C_CAN_MB5_MAM         EQU (0xFFFD02A4) ;- (CAN_MB5) MailBox Acceptance Mask Register
-// - ========== Register definition for CAN_MB6 peripheral ========== 
-AT91C_CAN_MB6_MFID        EQU (0xFFFD02CC) ;- (CAN_MB6) MailBox Family ID Register
-AT91C_CAN_MB6_MID         EQU (0xFFFD02C8) ;- (CAN_MB6) MailBox ID Register
-AT91C_CAN_MB6_MAM         EQU (0xFFFD02C4) ;- (CAN_MB6) MailBox Acceptance Mask Register
-AT91C_CAN_MB6_MSR         EQU (0xFFFD02D0) ;- (CAN_MB6) MailBox Status Register
-AT91C_CAN_MB6_MDL         EQU (0xFFFD02D4) ;- (CAN_MB6) MailBox Data Low Register
-AT91C_CAN_MB6_MCR         EQU (0xFFFD02DC) ;- (CAN_MB6) MailBox Control Register
-AT91C_CAN_MB6_MDH         EQU (0xFFFD02D8) ;- (CAN_MB6) MailBox Data High Register
-AT91C_CAN_MB6_MMR         EQU (0xFFFD02C0) ;- (CAN_MB6) MailBox Mode Register
-// - ========== Register definition for CAN_MB7 peripheral ========== 
-AT91C_CAN_MB7_MCR         EQU (0xFFFD02FC) ;- (CAN_MB7) MailBox Control Register
-AT91C_CAN_MB7_MDH         EQU (0xFFFD02F8) ;- (CAN_MB7) MailBox Data High Register
-AT91C_CAN_MB7_MFID        EQU (0xFFFD02EC) ;- (CAN_MB7) MailBox Family ID Register
-AT91C_CAN_MB7_MDL         EQU (0xFFFD02F4) ;- (CAN_MB7) MailBox Data Low Register
-AT91C_CAN_MB7_MID         EQU (0xFFFD02E8) ;- (CAN_MB7) MailBox ID Register
-AT91C_CAN_MB7_MMR         EQU (0xFFFD02E0) ;- (CAN_MB7) MailBox Mode Register
-AT91C_CAN_MB7_MAM         EQU (0xFFFD02E4) ;- (CAN_MB7) MailBox Acceptance Mask Register
-AT91C_CAN_MB7_MSR         EQU (0xFFFD02F0) ;- (CAN_MB7) MailBox Status Register
-// - ========== Register definition for CAN peripheral ========== 
-AT91C_CAN_TCR             EQU (0xFFFD0024) ;- (CAN) Transfer Command Register
-AT91C_CAN_IMR             EQU (0xFFFD000C) ;- (CAN) Interrupt Mask Register
-AT91C_CAN_IER             EQU (0xFFFD0004) ;- (CAN) Interrupt Enable Register
-AT91C_CAN_ECR             EQU (0xFFFD0020) ;- (CAN) Error Counter Register
-AT91C_CAN_TIMESTP         EQU (0xFFFD001C) ;- (CAN) Time Stamp Register
-AT91C_CAN_MR              EQU (0xFFFD0000) ;- (CAN) Mode Register
-AT91C_CAN_IDR             EQU (0xFFFD0008) ;- (CAN) Interrupt Disable Register
-AT91C_CAN_ACR             EQU (0xFFFD0028) ;- (CAN) Abort Command Register
-AT91C_CAN_TIM             EQU (0xFFFD0018) ;- (CAN) Timer Register
-AT91C_CAN_SR              EQU (0xFFFD0010) ;- (CAN) Status Register
-AT91C_CAN_BR              EQU (0xFFFD0014) ;- (CAN) Baudrate Register
-AT91C_CAN_VR              EQU (0xFFFD00FC) ;- (CAN) Version Register
-// - ========== Register definition for EMAC peripheral ========== 
-AT91C_EMAC_ISR            EQU (0xFFFDC024) ;- (EMAC) Interrupt Status Register
-AT91C_EMAC_SA4H           EQU (0xFFFDC0B4) ;- (EMAC) Specific Address 4 Top, Last 2 bytes
-AT91C_EMAC_SA1L           EQU (0xFFFDC098) ;- (EMAC) Specific Address 1 Bottom, First 4 bytes
-AT91C_EMAC_ELE            EQU (0xFFFDC078) ;- (EMAC) Excessive Length Errors Register
-AT91C_EMAC_LCOL           EQU (0xFFFDC05C) ;- (EMAC) Late Collision Register
-AT91C_EMAC_RLE            EQU (0xFFFDC088) ;- (EMAC) Receive Length Field Mismatch Register
-AT91C_EMAC_WOL            EQU (0xFFFDC0C4) ;- (EMAC) Wake On LAN Register
-AT91C_EMAC_DTF            EQU (0xFFFDC058) ;- (EMAC) Deferred Transmission Frame Register
-AT91C_EMAC_TUND           EQU (0xFFFDC064) ;- (EMAC) Transmit Underrun Error Register
-AT91C_EMAC_NCR            EQU (0xFFFDC000) ;- (EMAC) Network Control Register
-AT91C_EMAC_SA4L           EQU (0xFFFDC0B0) ;- (EMAC) Specific Address 4 Bottom, First 4 bytes
-AT91C_EMAC_RSR            EQU (0xFFFDC020) ;- (EMAC) Receive Status Register
-AT91C_EMAC_SA3L           EQU (0xFFFDC0A8) ;- (EMAC) Specific Address 3 Bottom, First 4 bytes
-AT91C_EMAC_TSR            EQU (0xFFFDC014) ;- (EMAC) Transmit Status Register
-AT91C_EMAC_IDR            EQU (0xFFFDC02C) ;- (EMAC) Interrupt Disable Register
-AT91C_EMAC_RSE            EQU (0xFFFDC074) ;- (EMAC) Receive Symbol Errors Register
-AT91C_EMAC_ECOL           EQU (0xFFFDC060) ;- (EMAC) Excessive Collision Register
-AT91C_EMAC_TID            EQU (0xFFFDC0B8) ;- (EMAC) Type ID Checking Register
-AT91C_EMAC_HRB            EQU (0xFFFDC090) ;- (EMAC) Hash Address Bottom[31:0]
-AT91C_EMAC_TBQP           EQU (0xFFFDC01C) ;- (EMAC) Transmit Buffer Queue Pointer
-AT91C_EMAC_USRIO          EQU (0xFFFDC0C0) ;- (EMAC) USER Input/Output Register
-AT91C_EMAC_PTR            EQU (0xFFFDC038) ;- (EMAC) Pause Time Register
-AT91C_EMAC_SA2H           EQU (0xFFFDC0A4) ;- (EMAC) Specific Address 2 Top, Last 2 bytes
-AT91C_EMAC_ROV            EQU (0xFFFDC070) ;- (EMAC) Receive Overrun Errors Register
-AT91C_EMAC_ALE            EQU (0xFFFDC054) ;- (EMAC) Alignment Error Register
-AT91C_EMAC_RJA            EQU (0xFFFDC07C) ;- (EMAC) Receive Jabbers Register
-AT91C_EMAC_RBQP           EQU (0xFFFDC018) ;- (EMAC) Receive Buffer Queue Pointer
-AT91C_EMAC_TPF            EQU (0xFFFDC08C) ;- (EMAC) Transmitted Pause Frames Register
-AT91C_EMAC_NCFGR          EQU (0xFFFDC004) ;- (EMAC) Network Configuration Register
-AT91C_EMAC_HRT            EQU (0xFFFDC094) ;- (EMAC) Hash Address Top[63:32]
-AT91C_EMAC_USF            EQU (0xFFFDC080) ;- (EMAC) Undersize Frames Register
-AT91C_EMAC_FCSE           EQU (0xFFFDC050) ;- (EMAC) Frame Check Sequence Error Register
-AT91C_EMAC_TPQ            EQU (0xFFFDC0BC) ;- (EMAC) Transmit Pause Quantum Register
-AT91C_EMAC_MAN            EQU (0xFFFDC034) ;- (EMAC) PHY Maintenance Register
-AT91C_EMAC_FTO            EQU (0xFFFDC040) ;- (EMAC) Frames Transmitted OK Register
-AT91C_EMAC_REV            EQU (0xFFFDC0FC) ;- (EMAC) Revision Register
-AT91C_EMAC_IMR            EQU (0xFFFDC030) ;- (EMAC) Interrupt Mask Register
-AT91C_EMAC_SCF            EQU (0xFFFDC044) ;- (EMAC) Single Collision Frame Register
-AT91C_EMAC_PFR            EQU (0xFFFDC03C) ;- (EMAC) Pause Frames received Register
-AT91C_EMAC_MCF            EQU (0xFFFDC048) ;- (EMAC) Multiple Collision Frame Register
-AT91C_EMAC_NSR            EQU (0xFFFDC008) ;- (EMAC) Network Status Register
-AT91C_EMAC_SA2L           EQU (0xFFFDC0A0) ;- (EMAC) Specific Address 2 Bottom, First 4 bytes
-AT91C_EMAC_FRO            EQU (0xFFFDC04C) ;- (EMAC) Frames Received OK Register
-AT91C_EMAC_IER            EQU (0xFFFDC028) ;- (EMAC) Interrupt Enable Register
-AT91C_EMAC_SA1H           EQU (0xFFFDC09C) ;- (EMAC) Specific Address 1 Top, Last 2 bytes
-AT91C_EMAC_CSE            EQU (0xFFFDC068) ;- (EMAC) Carrier Sense Error Register
-AT91C_EMAC_SA3H           EQU (0xFFFDC0AC) ;- (EMAC) Specific Address 3 Top, Last 2 bytes
-AT91C_EMAC_RRE            EQU (0xFFFDC06C) ;- (EMAC) Receive Ressource Error Register
-AT91C_EMAC_STE            EQU (0xFFFDC084) ;- (EMAC) SQE Test Error Register
-// - ========== Register definition for PDC_ADC peripheral ========== 
-AT91C_ADC_PTSR            EQU (0xFFFD8124) ;- (PDC_ADC) PDC Transfer Status Register
-AT91C_ADC_PTCR            EQU (0xFFFD8120) ;- (PDC_ADC) PDC Transfer Control Register
-AT91C_ADC_TNPR            EQU (0xFFFD8118) ;- (PDC_ADC) Transmit Next Pointer Register
-AT91C_ADC_TNCR            EQU (0xFFFD811C) ;- (PDC_ADC) Transmit Next Counter Register
-AT91C_ADC_RNPR            EQU (0xFFFD8110) ;- (PDC_ADC) Receive Next Pointer Register
-AT91C_ADC_RNCR            EQU (0xFFFD8114) ;- (PDC_ADC) Receive Next Counter Register
-AT91C_ADC_RPR             EQU (0xFFFD8100) ;- (PDC_ADC) Receive Pointer Register
-AT91C_ADC_TCR             EQU (0xFFFD810C) ;- (PDC_ADC) Transmit Counter Register
-AT91C_ADC_TPR             EQU (0xFFFD8108) ;- (PDC_ADC) Transmit Pointer Register
-AT91C_ADC_RCR             EQU (0xFFFD8104) ;- (PDC_ADC) Receive Counter Register
-// - ========== Register definition for ADC peripheral ========== 
-AT91C_ADC_CDR2            EQU (0xFFFD8038) ;- (ADC) ADC Channel Data Register 2
-AT91C_ADC_CDR3            EQU (0xFFFD803C) ;- (ADC) ADC Channel Data Register 3
-AT91C_ADC_CDR0            EQU (0xFFFD8030) ;- (ADC) ADC Channel Data Register 0
-AT91C_ADC_CDR5            EQU (0xFFFD8044) ;- (ADC) ADC Channel Data Register 5
-AT91C_ADC_CHDR            EQU (0xFFFD8014) ;- (ADC) ADC Channel Disable Register
-AT91C_ADC_SR              EQU (0xFFFD801C) ;- (ADC) ADC Status Register
-AT91C_ADC_CDR4            EQU (0xFFFD8040) ;- (ADC) ADC Channel Data Register 4
-AT91C_ADC_CDR1            EQU (0xFFFD8034) ;- (ADC) ADC Channel Data Register 1
-AT91C_ADC_LCDR            EQU (0xFFFD8020) ;- (ADC) ADC Last Converted Data Register
-AT91C_ADC_IDR             EQU (0xFFFD8028) ;- (ADC) ADC Interrupt Disable Register
-AT91C_ADC_CR              EQU (0xFFFD8000) ;- (ADC) ADC Control Register
-AT91C_ADC_CDR7            EQU (0xFFFD804C) ;- (ADC) ADC Channel Data Register 7
-AT91C_ADC_CDR6            EQU (0xFFFD8048) ;- (ADC) ADC Channel Data Register 6
-AT91C_ADC_IER             EQU (0xFFFD8024) ;- (ADC) ADC Interrupt Enable Register
-AT91C_ADC_CHER            EQU (0xFFFD8010) ;- (ADC) ADC Channel Enable Register
-AT91C_ADC_CHSR            EQU (0xFFFD8018) ;- (ADC) ADC Channel Status Register
-AT91C_ADC_MR              EQU (0xFFFD8004) ;- (ADC) ADC Mode Register
-AT91C_ADC_IMR             EQU (0xFFFD802C) ;- (ADC) ADC Interrupt Mask Register
-// - ========== Register definition for PDC_AES peripheral ========== 
-AT91C_AES_TPR             EQU (0xFFFA4108) ;- (PDC_AES) Transmit Pointer Register
-AT91C_AES_PTCR            EQU (0xFFFA4120) ;- (PDC_AES) PDC Transfer Control Register
-AT91C_AES_RNPR            EQU (0xFFFA4110) ;- (PDC_AES) Receive Next Pointer Register
-AT91C_AES_TNCR            EQU (0xFFFA411C) ;- (PDC_AES) Transmit Next Counter Register
-AT91C_AES_TCR             EQU (0xFFFA410C) ;- (PDC_AES) Transmit Counter Register
-AT91C_AES_RCR             EQU (0xFFFA4104) ;- (PDC_AES) Receive Counter Register
-AT91C_AES_RNCR            EQU (0xFFFA4114) ;- (PDC_AES) Receive Next Counter Register
-AT91C_AES_TNPR            EQU (0xFFFA4118) ;- (PDC_AES) Transmit Next Pointer Register
-AT91C_AES_RPR             EQU (0xFFFA4100) ;- (PDC_AES) Receive Pointer Register
-AT91C_AES_PTSR            EQU (0xFFFA4124) ;- (PDC_AES) PDC Transfer Status Register
-// - ========== Register definition for AES peripheral ========== 
-AT91C_AES_IVxR            EQU (0xFFFA4060) ;- (AES) Initialization Vector x Register
-AT91C_AES_MR              EQU (0xFFFA4004) ;- (AES) Mode Register
-AT91C_AES_VR              EQU (0xFFFA40FC) ;- (AES) AES Version Register
-AT91C_AES_ODATAxR         EQU (0xFFFA4050) ;- (AES) Output Data x Register
-AT91C_AES_IDATAxR         EQU (0xFFFA4040) ;- (AES) Input Data x Register
-AT91C_AES_CR              EQU (0xFFFA4000) ;- (AES) Control Register
-AT91C_AES_IDR             EQU (0xFFFA4014) ;- (AES) Interrupt Disable Register
-AT91C_AES_IMR             EQU (0xFFFA4018) ;- (AES) Interrupt Mask Register
-AT91C_AES_IER             EQU (0xFFFA4010) ;- (AES) Interrupt Enable Register
-AT91C_AES_KEYWxR          EQU (0xFFFA4020) ;- (AES) Key Word x Register
-AT91C_AES_ISR             EQU (0xFFFA401C) ;- (AES) Interrupt Status Register
-// - ========== Register definition for PDC_TDES peripheral ========== 
-AT91C_TDES_RNCR           EQU (0xFFFA8114) ;- (PDC_TDES) Receive Next Counter Register
-AT91C_TDES_TCR            EQU (0xFFFA810C) ;- (PDC_TDES) Transmit Counter Register
-AT91C_TDES_RCR            EQU (0xFFFA8104) ;- (PDC_TDES) Receive Counter Register
-AT91C_TDES_TNPR           EQU (0xFFFA8118) ;- (PDC_TDES) Transmit Next Pointer Register
-AT91C_TDES_RNPR           EQU (0xFFFA8110) ;- (PDC_TDES) Receive Next Pointer Register
-AT91C_TDES_RPR            EQU (0xFFFA8100) ;- (PDC_TDES) Receive Pointer Register
-AT91C_TDES_TNCR           EQU (0xFFFA811C) ;- (PDC_TDES) Transmit Next Counter Register
-AT91C_TDES_TPR            EQU (0xFFFA8108) ;- (PDC_TDES) Transmit Pointer Register
-AT91C_TDES_PTSR           EQU (0xFFFA8124) ;- (PDC_TDES) PDC Transfer Status Register
-AT91C_TDES_PTCR           EQU (0xFFFA8120) ;- (PDC_TDES) PDC Transfer Control Register
-// - ========== Register definition for TDES peripheral ========== 
-AT91C_TDES_KEY2WxR        EQU (0xFFFA8028) ;- (TDES) Key 2 Word x Register
-AT91C_TDES_KEY3WxR        EQU (0xFFFA8030) ;- (TDES) Key 3 Word x Register
-AT91C_TDES_IDR            EQU (0xFFFA8014) ;- (TDES) Interrupt Disable Register
-AT91C_TDES_VR             EQU (0xFFFA80FC) ;- (TDES) TDES Version Register
-AT91C_TDES_IVxR           EQU (0xFFFA8060) ;- (TDES) Initialization Vector x Register
-AT91C_TDES_ODATAxR        EQU (0xFFFA8050) ;- (TDES) Output Data x Register
-AT91C_TDES_IMR            EQU (0xFFFA8018) ;- (TDES) Interrupt Mask Register
-AT91C_TDES_MR             EQU (0xFFFA8004) ;- (TDES) Mode Register
-AT91C_TDES_CR             EQU (0xFFFA8000) ;- (TDES) Control Register
-AT91C_TDES_IER            EQU (0xFFFA8010) ;- (TDES) Interrupt Enable Register
-AT91C_TDES_ISR            EQU (0xFFFA801C) ;- (TDES) Interrupt Status Register
-AT91C_TDES_IDATAxR        EQU (0xFFFA8040) ;- (TDES) Input Data x Register
-AT91C_TDES_KEY1WxR        EQU (0xFFFA8020) ;- (TDES) Key 1 Word x Register
-
-// - *****************************************************************************
-// -               PIO DEFINITIONS FOR AT91SAM7X128
-// - *****************************************************************************
-AT91C_PIO_PA0             EQU (1 <<  0) ;- Pin Controlled by PA0
-AT91C_PA0_RXD0            EQU (AT91C_PIO_PA0) ;-  USART 0 Receive Data
-AT91C_PIO_PA1             EQU (1 <<  1) ;- Pin Controlled by PA1
-AT91C_PA1_TXD0            EQU (AT91C_PIO_PA1) ;-  USART 0 Transmit Data
-AT91C_PIO_PA10            EQU (1 << 10) ;- Pin Controlled by PA10
-AT91C_PA10_TWD            EQU (AT91C_PIO_PA10) ;-  TWI Two-wire Serial Data
-AT91C_PIO_PA11            EQU (1 << 11) ;- Pin Controlled by PA11
-AT91C_PA11_TWCK           EQU (AT91C_PIO_PA11) ;-  TWI Two-wire Serial Clock
-AT91C_PIO_PA12            EQU (1 << 12) ;- Pin Controlled by PA12
-AT91C_PA12_NPCS00         EQU (AT91C_PIO_PA12) ;-  SPI 0 Peripheral Chip Select 0
-AT91C_PIO_PA13            EQU (1 << 13) ;- Pin Controlled by PA13
-AT91C_PA13_NPCS01         EQU (AT91C_PIO_PA13) ;-  SPI 0 Peripheral Chip Select 1
-AT91C_PA13_PCK1           EQU (AT91C_PIO_PA13) ;-  PMC Programmable Clock Output 1
-AT91C_PIO_PA14            EQU (1 << 14) ;- Pin Controlled by PA14
-AT91C_PA14_NPCS02         EQU (AT91C_PIO_PA14) ;-  SPI 0 Peripheral Chip Select 2
-AT91C_PA14_IRQ1           EQU (AT91C_PIO_PA14) ;-  External Interrupt 1
-AT91C_PIO_PA15            EQU (1 << 15) ;- Pin Controlled by PA15
-AT91C_PA15_NPCS03         EQU (AT91C_PIO_PA15) ;-  SPI 0 Peripheral Chip Select 3
-AT91C_PA15_TCLK2          EQU (AT91C_PIO_PA15) ;-  Timer Counter 2 external clock input
-AT91C_PIO_PA16            EQU (1 << 16) ;- Pin Controlled by PA16
-AT91C_PA16_MISO0          EQU (AT91C_PIO_PA16) ;-  SPI 0 Master In Slave
-AT91C_PIO_PA17            EQU (1 << 17) ;- Pin Controlled by PA17
-AT91C_PA17_MOSI0          EQU (AT91C_PIO_PA17) ;-  SPI 0 Master Out Slave
-AT91C_PIO_PA18            EQU (1 << 18) ;- Pin Controlled by PA18
-AT91C_PA18_SPCK0          EQU (AT91C_PIO_PA18) ;-  SPI 0 Serial Clock
-AT91C_PIO_PA19            EQU (1 << 19) ;- Pin Controlled by PA19
-AT91C_PA19_CANRX          EQU (AT91C_PIO_PA19) ;-  CAN Receive
-AT91C_PIO_PA2             EQU (1 <<  2) ;- Pin Controlled by PA2
-AT91C_PA2_SCK0            EQU (AT91C_PIO_PA2) ;-  USART 0 Serial Clock
-AT91C_PA2_NPCS11          EQU (AT91C_PIO_PA2) ;-  SPI 1 Peripheral Chip Select 1
-AT91C_PIO_PA20            EQU (1 << 20) ;- Pin Controlled by PA20
-AT91C_PA20_CANTX          EQU (AT91C_PIO_PA20) ;-  CAN Transmit
-AT91C_PIO_PA21            EQU (1 << 21) ;- Pin Controlled by PA21
-AT91C_PA21_TF             EQU (AT91C_PIO_PA21) ;-  SSC Transmit Frame Sync
-AT91C_PA21_NPCS10         EQU (AT91C_PIO_PA21) ;-  SPI 1 Peripheral Chip Select 0
-AT91C_PIO_PA22            EQU (1 << 22) ;- Pin Controlled by PA22
-AT91C_PA22_TK             EQU (AT91C_PIO_PA22) ;-  SSC Transmit Clock
-AT91C_PA22_SPCK1          EQU (AT91C_PIO_PA22) ;-  SPI 1 Serial Clock
-AT91C_PIO_PA23            EQU (1 << 23) ;- Pin Controlled by PA23
-AT91C_PA23_TD             EQU (AT91C_PIO_PA23) ;-  SSC Transmit data
-AT91C_PA23_MOSI1          EQU (AT91C_PIO_PA23) ;-  SPI 1 Master Out Slave
-AT91C_PIO_PA24            EQU (1 << 24) ;- Pin Controlled by PA24
-AT91C_PA24_RD             EQU (AT91C_PIO_PA24) ;-  SSC Receive Data
-AT91C_PA24_MISO1          EQU (AT91C_PIO_PA24) ;-  SPI 1 Master In Slave
-AT91C_PIO_PA25            EQU (1 << 25) ;- Pin Controlled by PA25
-AT91C_PA25_RK             EQU (AT91C_PIO_PA25) ;-  SSC Receive Clock
-AT91C_PA25_NPCS11         EQU (AT91C_PIO_PA25) ;-  SPI 1 Peripheral Chip Select 1
-AT91C_PIO_PA26            EQU (1 << 26) ;- Pin Controlled by PA26
-AT91C_PA26_RF             EQU (AT91C_PIO_PA26) ;-  SSC Receive Frame Sync
-AT91C_PA26_NPCS12         EQU (AT91C_PIO_PA26) ;-  SPI 1 Peripheral Chip Select 2
-AT91C_PIO_PA27            EQU (1 << 27) ;- Pin Controlled by PA27
-AT91C_PA27_DRXD           EQU (AT91C_PIO_PA27) ;-  DBGU Debug Receive Data
-AT91C_PA27_PCK3           EQU (AT91C_PIO_PA27) ;-  PMC Programmable Clock Output 3
-AT91C_PIO_PA28            EQU (1 << 28) ;- Pin Controlled by PA28
-AT91C_PA28_DTXD           EQU (AT91C_PIO_PA28) ;-  DBGU Debug Transmit Data
-AT91C_PIO_PA29            EQU (1 << 29) ;- Pin Controlled by PA29
-AT91C_PA29_FIQ            EQU (AT91C_PIO_PA29) ;-  AIC Fast Interrupt Input
-AT91C_PA29_NPCS13         EQU (AT91C_PIO_PA29) ;-  SPI 1 Peripheral Chip Select 3
-AT91C_PIO_PA3             EQU (1 <<  3) ;- Pin Controlled by PA3
-AT91C_PA3_RTS0            EQU (AT91C_PIO_PA3) ;-  USART 0 Ready To Send
-AT91C_PA3_NPCS12          EQU (AT91C_PIO_PA3) ;-  SPI 1 Peripheral Chip Select 2
-AT91C_PIO_PA30            EQU (1 << 30) ;- Pin Controlled by PA30
-AT91C_PA30_IRQ0           EQU (AT91C_PIO_PA30) ;-  External Interrupt 0
-AT91C_PA30_PCK2           EQU (AT91C_PIO_PA30) ;-  PMC Programmable Clock Output 2
-AT91C_PIO_PA4             EQU (1 <<  4) ;- Pin Controlled by PA4
-AT91C_PA4_CTS0            EQU (AT91C_PIO_PA4) ;-  USART 0 Clear To Send
-AT91C_PA4_NPCS13          EQU (AT91C_PIO_PA4) ;-  SPI 1 Peripheral Chip Select 3
-AT91C_PIO_PA5             EQU (1 <<  5) ;- Pin Controlled by PA5
-AT91C_PA5_RXD1            EQU (AT91C_PIO_PA5) ;-  USART 1 Receive Data
-AT91C_PIO_PA6             EQU (1 <<  6) ;- Pin Controlled by PA6
-AT91C_PA6_TXD1            EQU (AT91C_PIO_PA6) ;-  USART 1 Transmit Data
-AT91C_PIO_PA7             EQU (1 <<  7) ;- Pin Controlled by PA7
-AT91C_PA7_SCK1            EQU (AT91C_PIO_PA7) ;-  USART 1 Serial Clock
-AT91C_PA7_NPCS01          EQU (AT91C_PIO_PA7) ;-  SPI 0 Peripheral Chip Select 1
-AT91C_PIO_PA8             EQU (1 <<  8) ;- Pin Controlled by PA8
-AT91C_PA8_RTS1            EQU (AT91C_PIO_PA8) ;-  USART 1 Ready To Send
-AT91C_PA8_NPCS02          EQU (AT91C_PIO_PA8) ;-  SPI 0 Peripheral Chip Select 2
-AT91C_PIO_PA9             EQU (1 <<  9) ;- Pin Controlled by PA9
-AT91C_PA9_CTS1            EQU (AT91C_PIO_PA9) ;-  USART 1 Clear To Send
-AT91C_PA9_NPCS03          EQU (AT91C_PIO_PA9) ;-  SPI 0 Peripheral Chip Select 3
-AT91C_PIO_PB0             EQU (1 <<  0) ;- Pin Controlled by PB0
-AT91C_PB0_ETXCK_EREFCK    EQU (AT91C_PIO_PB0) ;-  Ethernet MAC Transmit Clock/Reference Clock
-AT91C_PB0_PCK0            EQU (AT91C_PIO_PB0) ;-  PMC Programmable Clock Output 0
-AT91C_PIO_PB1             EQU (1 <<  1) ;- Pin Controlled by PB1
-AT91C_PB1_ETXEN           EQU (AT91C_PIO_PB1) ;-  Ethernet MAC Transmit Enable
-AT91C_PIO_PB10            EQU (1 << 10) ;- Pin Controlled by PB10
-AT91C_PB10_ETX2           EQU (AT91C_PIO_PB10) ;-  Ethernet MAC Transmit Data 2
-AT91C_PB10_NPCS11         EQU (AT91C_PIO_PB10) ;-  SPI 1 Peripheral Chip Select 1
-AT91C_PIO_PB11            EQU (1 << 11) ;- Pin Controlled by PB11
-AT91C_PB11_ETX3           EQU (AT91C_PIO_PB11) ;-  Ethernet MAC Transmit Data 3
-AT91C_PB11_NPCS12         EQU (AT91C_PIO_PB11) ;-  SPI 1 Peripheral Chip Select 2
-AT91C_PIO_PB12            EQU (1 << 12) ;- Pin Controlled by PB12
-AT91C_PB12_ETXER          EQU (AT91C_PIO_PB12) ;-  Ethernet MAC Transmikt Coding Error
-AT91C_PB12_TCLK0          EQU (AT91C_PIO_PB12) ;-  Timer Counter 0 external clock input
-AT91C_PIO_PB13            EQU (1 << 13) ;- Pin Controlled by PB13
-AT91C_PB13_ERX2           EQU (AT91C_PIO_PB13) ;-  Ethernet MAC Receive Data 2
-AT91C_PB13_NPCS01         EQU (AT91C_PIO_PB13) ;-  SPI 0 Peripheral Chip Select 1
-AT91C_PIO_PB14            EQU (1 << 14) ;- Pin Controlled by PB14
-AT91C_PB14_ERX3           EQU (AT91C_PIO_PB14) ;-  Ethernet MAC Receive Data 3
-AT91C_PB14_NPCS02         EQU (AT91C_PIO_PB14) ;-  SPI 0 Peripheral Chip Select 2
-AT91C_PIO_PB15            EQU (1 << 15) ;- Pin Controlled by PB15
-AT91C_PB15_ERXDV          EQU (AT91C_PIO_PB15) ;-  Ethernet MAC Receive Data Valid
-AT91C_PIO_PB16            EQU (1 << 16) ;- Pin Controlled by PB16
-AT91C_PB16_ECOL           EQU (AT91C_PIO_PB16) ;-  Ethernet MAC Collision Detected
-AT91C_PB16_NPCS13         EQU (AT91C_PIO_PB16) ;-  SPI 1 Peripheral Chip Select 3
-AT91C_PIO_PB17            EQU (1 << 17) ;- Pin Controlled by PB17
-AT91C_PB17_ERXCK          EQU (AT91C_PIO_PB17) ;-  Ethernet MAC Receive Clock
-AT91C_PB17_NPCS03         EQU (AT91C_PIO_PB17) ;-  SPI 0 Peripheral Chip Select 3
-AT91C_PIO_PB18            EQU (1 << 18) ;- Pin Controlled by PB18
-AT91C_PB18_EF100          EQU (AT91C_PIO_PB18) ;-  Ethernet MAC Force 100 Mbits/sec
-AT91C_PB18_ADTRG          EQU (AT91C_PIO_PB18) ;-  ADC External Trigger
-AT91C_PIO_PB19            EQU (1 << 19) ;- Pin Controlled by PB19
-AT91C_PB19_PWM0           EQU (AT91C_PIO_PB19) ;-  PWM Channel 0
-AT91C_PB19_TCLK1          EQU (AT91C_PIO_PB19) ;-  Timer Counter 1 external clock input
-AT91C_PIO_PB2             EQU (1 <<  2) ;- Pin Controlled by PB2
-AT91C_PB2_ETX0            EQU (AT91C_PIO_PB2) ;-  Ethernet MAC Transmit Data 0
-AT91C_PIO_PB20            EQU (1 << 20) ;- Pin Controlled by PB20
-AT91C_PB20_PWM1           EQU (AT91C_PIO_PB20) ;-  PWM Channel 1
-AT91C_PB20_PCK0           EQU (AT91C_PIO_PB20) ;-  PMC Programmable Clock Output 0
-AT91C_PIO_PB21            EQU (1 << 21) ;- Pin Controlled by PB21
-AT91C_PB21_PWM2           EQU (AT91C_PIO_PB21) ;-  PWM Channel 2
-AT91C_PB21_PCK1           EQU (AT91C_PIO_PB21) ;-  PMC Programmable Clock Output 1
-AT91C_PIO_PB22            EQU (1 << 22) ;- Pin Controlled by PB22
-AT91C_PB22_PWM3           EQU (AT91C_PIO_PB22) ;-  PWM Channel 3
-AT91C_PB22_PCK2           EQU (AT91C_PIO_PB22) ;-  PMC Programmable Clock Output 2
-AT91C_PIO_PB23            EQU (1 << 23) ;- Pin Controlled by PB23
-AT91C_PB23_TIOA0          EQU (AT91C_PIO_PB23) ;-  Timer Counter 0 Multipurpose Timer I/O Pin A
-AT91C_PB23_DCD1           EQU (AT91C_PIO_PB23) ;-  USART 1 Data Carrier Detect
-AT91C_PIO_PB24            EQU (1 << 24) ;- Pin Controlled by PB24
-AT91C_PB24_TIOB0          EQU (AT91C_PIO_PB24) ;-  Timer Counter 0 Multipurpose Timer I/O Pin B
-AT91C_PB24_DSR1           EQU (AT91C_PIO_PB24) ;-  USART 1 Data Set ready
-AT91C_PIO_PB25            EQU (1 << 25) ;- Pin Controlled by PB25
-AT91C_PB25_TIOA1          EQU (AT91C_PIO_PB25) ;-  Timer Counter 1 Multipurpose Timer I/O Pin A
-AT91C_PB25_DTR1           EQU (AT91C_PIO_PB25) ;-  USART 1 Data Terminal ready
-AT91C_PIO_PB26            EQU (1 << 26) ;- Pin Controlled by PB26
-AT91C_PB26_TIOB1          EQU (AT91C_PIO_PB26) ;-  Timer Counter 1 Multipurpose Timer I/O Pin B
-AT91C_PB26_RI1            EQU (AT91C_PIO_PB26) ;-  USART 1 Ring Indicator
-AT91C_PIO_PB27            EQU (1 << 27) ;- Pin Controlled by PB27
-AT91C_PB27_TIOA2          EQU (AT91C_PIO_PB27) ;-  Timer Counter 2 Multipurpose Timer I/O Pin A
-AT91C_PB27_PWM0           EQU (AT91C_PIO_PB27) ;-  PWM Channel 0
-AT91C_PIO_PB28            EQU (1 << 28) ;- Pin Controlled by PB28
-AT91C_PB28_TIOB2          EQU (AT91C_PIO_PB28) ;-  Timer Counter 2 Multipurpose Timer I/O Pin B
-AT91C_PB28_PWM1           EQU (AT91C_PIO_PB28) ;-  PWM Channel 1
-AT91C_PIO_PB29            EQU (1 << 29) ;- Pin Controlled by PB29
-AT91C_PB29_PCK1           EQU (AT91C_PIO_PB29) ;-  PMC Programmable Clock Output 1
-AT91C_PB29_PWM2           EQU (AT91C_PIO_PB29) ;-  PWM Channel 2
-AT91C_PIO_PB3             EQU (1 <<  3) ;- Pin Controlled by PB3
-AT91C_PB3_ETX1            EQU (AT91C_PIO_PB3) ;-  Ethernet MAC Transmit Data 1
-AT91C_PIO_PB30            EQU (1 << 30) ;- Pin Controlled by PB30
-AT91C_PB30_PCK2           EQU (AT91C_PIO_PB30) ;-  PMC Programmable Clock Output 2
-AT91C_PB30_PWM3           EQU (AT91C_PIO_PB30) ;-  PWM Channel 3
-AT91C_PIO_PB4             EQU (1 <<  4) ;- Pin Controlled by PB4
-AT91C_PB4_ECRS_ECRSDV     EQU (AT91C_PIO_PB4) ;-  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
-AT91C_PIO_PB5             EQU (1 <<  5) ;- Pin Controlled by PB5
-AT91C_PB5_ERX0            EQU (AT91C_PIO_PB5) ;-  Ethernet MAC Receive Data 0
-AT91C_PIO_PB6             EQU (1 <<  6) ;- Pin Controlled by PB6
-AT91C_PB6_ERX1            EQU (AT91C_PIO_PB6) ;-  Ethernet MAC Receive Data 1
-AT91C_PIO_PB7             EQU (1 <<  7) ;- Pin Controlled by PB7
-AT91C_PB7_ERXER           EQU (AT91C_PIO_PB7) ;-  Ethernet MAC Receive Error
-AT91C_PIO_PB8             EQU (1 <<  8) ;- Pin Controlled by PB8
-AT91C_PB8_EMDC            EQU (AT91C_PIO_PB8) ;-  Ethernet MAC Management Data Clock
-AT91C_PIO_PB9             EQU (1 <<  9) ;- Pin Controlled by PB9
-AT91C_PB9_EMDIO           EQU (AT91C_PIO_PB9) ;-  Ethernet MAC Management Data Input/Output
-
-// - *****************************************************************************
-// -               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128
-// - *****************************************************************************
-AT91C_ID_FIQ              EQU ( 0) ;- Advanced Interrupt Controller (FIQ)
-AT91C_ID_SYS              EQU ( 1) ;- System Peripheral
-AT91C_ID_PIOA             EQU ( 2) ;- Parallel IO Controller A
-AT91C_ID_PIOB             EQU ( 3) ;- Parallel IO Controller B
-AT91C_ID_SPI0             EQU ( 4) ;- Serial Peripheral Interface 0
-AT91C_ID_SPI1             EQU ( 5) ;- Serial Peripheral Interface 1
-AT91C_ID_US0              EQU ( 6) ;- USART 0
-AT91C_ID_US1              EQU ( 7) ;- USART 1
-AT91C_ID_SSC              EQU ( 8) ;- Serial Synchronous Controller
-AT91C_ID_TWI              EQU ( 9) ;- Two-Wire Interface
-AT91C_ID_PWMC             EQU (10) ;- PWM Controller
-AT91C_ID_UDP              EQU (11) ;- USB Device Port
-AT91C_ID_TC0              EQU (12) ;- Timer Counter 0
-AT91C_ID_TC1              EQU (13) ;- Timer Counter 1
-AT91C_ID_TC2              EQU (14) ;- Timer Counter 2
-AT91C_ID_CAN              EQU (15) ;- Control Area Network Controller
-AT91C_ID_EMAC             EQU (16) ;- Ethernet MAC
-AT91C_ID_ADC              EQU (17) ;- Analog-to-Digital Converter
-AT91C_ID_AES              EQU (18) ;- Advanced Encryption Standard 128-bit
-AT91C_ID_TDES             EQU (19) ;- Triple Data Encryption Standard
-AT91C_ID_20_Reserved      EQU (20) ;- Reserved
-AT91C_ID_21_Reserved      EQU (21) ;- Reserved
-AT91C_ID_22_Reserved      EQU (22) ;- Reserved
-AT91C_ID_23_Reserved      EQU (23) ;- Reserved
-AT91C_ID_24_Reserved      EQU (24) ;- Reserved
-AT91C_ID_25_Reserved      EQU (25) ;- Reserved
-AT91C_ID_26_Reserved      EQU (26) ;- Reserved
-AT91C_ID_27_Reserved      EQU (27) ;- Reserved
-AT91C_ID_28_Reserved      EQU (28) ;- Reserved
-AT91C_ID_29_Reserved      EQU (29) ;- Reserved
-AT91C_ID_IRQ0             EQU (30) ;- Advanced Interrupt Controller (IRQ0)
-AT91C_ID_IRQ1             EQU (31) ;- Advanced Interrupt Controller (IRQ1)
-
-// - *****************************************************************************
-// -               BASE ADDRESS DEFINITIONS FOR AT91SAM7X128
-// - *****************************************************************************
-AT91C_BASE_SYS            EQU (0xFFFFF000) ;- (SYS) Base Address
-AT91C_BASE_AIC            EQU (0xFFFFF000) ;- (AIC) Base Address
-AT91C_BASE_PDC_DBGU       EQU (0xFFFFF300) ;- (PDC_DBGU) Base Address
-AT91C_BASE_DBGU           EQU (0xFFFFF200) ;- (DBGU) Base Address
-AT91C_BASE_PIOA           EQU (0xFFFFF400) ;- (PIOA) Base Address
-AT91C_BASE_PIOB           EQU (0xFFFFF600) ;- (PIOB) Base Address
-AT91C_BASE_CKGR           EQU (0xFFFFFC20) ;- (CKGR) Base Address
-AT91C_BASE_PMC            EQU (0xFFFFFC00) ;- (PMC) Base Address
-AT91C_BASE_RSTC           EQU (0xFFFFFD00) ;- (RSTC) Base Address
-AT91C_BASE_RTTC           EQU (0xFFFFFD20) ;- (RTTC) Base Address
-AT91C_BASE_PITC           EQU (0xFFFFFD30) ;- (PITC) Base Address
-AT91C_BASE_WDTC           EQU (0xFFFFFD40) ;- (WDTC) Base Address
-AT91C_BASE_VREG           EQU (0xFFFFFD60) ;- (VREG) Base Address
-AT91C_BASE_MC             EQU (0xFFFFFF00) ;- (MC) Base Address
-AT91C_BASE_PDC_SPI1       EQU (0xFFFE4100) ;- (PDC_SPI1) Base Address
-AT91C_BASE_SPI1           EQU (0xFFFE4000) ;- (SPI1) Base Address
-AT91C_BASE_PDC_SPI0       EQU (0xFFFE0100) ;- (PDC_SPI0) Base Address
-AT91C_BASE_SPI0           EQU (0xFFFE0000) ;- (SPI0) Base Address
-AT91C_BASE_PDC_US1        EQU (0xFFFC4100) ;- (PDC_US1) Base Address
-AT91C_BASE_US1            EQU (0xFFFC4000) ;- (US1) Base Address
-AT91C_BASE_PDC_US0        EQU (0xFFFC0100) ;- (PDC_US0) Base Address
-AT91C_BASE_US0            EQU (0xFFFC0000) ;- (US0) Base Address
-AT91C_BASE_PDC_SSC        EQU (0xFFFD4100) ;- (PDC_SSC) Base Address
-AT91C_BASE_SSC            EQU (0xFFFD4000) ;- (SSC) Base Address
-AT91C_BASE_TWI            EQU (0xFFFB8000) ;- (TWI) Base Address
-AT91C_BASE_PWMC_CH3       EQU (0xFFFCC260) ;- (PWMC_CH3) Base Address
-AT91C_BASE_PWMC_CH2       EQU (0xFFFCC240) ;- (PWMC_CH2) Base Address
-AT91C_BASE_PWMC_CH1       EQU (0xFFFCC220) ;- (PWMC_CH1) Base Address
-AT91C_BASE_PWMC_CH0       EQU (0xFFFCC200) ;- (PWMC_CH0) Base Address
-AT91C_BASE_PWMC           EQU (0xFFFCC000) ;- (PWMC) Base Address
-AT91C_BASE_UDP            EQU (0xFFFB0000) ;- (UDP) Base Address
-AT91C_BASE_TC0            EQU (0xFFFA0000) ;- (TC0) Base Address
-AT91C_BASE_TC1            EQU (0xFFFA0040) ;- (TC1) Base Address
-AT91C_BASE_TC2            EQU (0xFFFA0080) ;- (TC2) Base Address
-AT91C_BASE_TCB            EQU (0xFFFA0000) ;- (TCB) Base Address
-AT91C_BASE_CAN_MB0        EQU (0xFFFD0200) ;- (CAN_MB0) Base Address
-AT91C_BASE_CAN_MB1        EQU (0xFFFD0220) ;- (CAN_MB1) Base Address
-AT91C_BASE_CAN_MB2        EQU (0xFFFD0240) ;- (CAN_MB2) Base Address
-AT91C_BASE_CAN_MB3        EQU (0xFFFD0260) ;- (CAN_MB3) Base Address
-AT91C_BASE_CAN_MB4        EQU (0xFFFD0280) ;- (CAN_MB4) Base Address
-AT91C_BASE_CAN_MB5        EQU (0xFFFD02A0) ;- (CAN_MB5) Base Address
-AT91C_BASE_CAN_MB6        EQU (0xFFFD02C0) ;- (CAN_MB6) Base Address
-AT91C_BASE_CAN_MB7        EQU (0xFFFD02E0) ;- (CAN_MB7) Base Address
-AT91C_BASE_CAN            EQU (0xFFFD0000) ;- (CAN) Base Address
-AT91C_BASE_EMAC           EQU (0xFFFDC000) ;- (EMAC) Base Address
-AT91C_BASE_PDC_ADC        EQU (0xFFFD8100) ;- (PDC_ADC) Base Address
-AT91C_BASE_ADC            EQU (0xFFFD8000) ;- (ADC) Base Address
-AT91C_BASE_PDC_AES        EQU (0xFFFA4100) ;- (PDC_AES) Base Address
-AT91C_BASE_AES            EQU (0xFFFA4000) ;- (AES) Base Address
-AT91C_BASE_PDC_TDES       EQU (0xFFFA8100) ;- (PDC_TDES) Base Address
-AT91C_BASE_TDES           EQU (0xFFFA8000) ;- (TDES) Base Address
-
-// - *****************************************************************************
-// -               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128
-// - *****************************************************************************
-AT91C_ISRAM               EQU (0x00200000) ;- Internal SRAM base address
-AT91C_ISRAM_SIZE          EQU (0x00008000) ;- Internal SRAM size in byte (32 Kbyte)
-AT91C_IFLASH              EQU (0x00100000) ;- Internal ROM base address
-AT91C_IFLASH_SIZE         EQU (0x00020000) ;- Internal ROM size in byte (128 Kbyte)
-#endif /* __IAR_SYSTEMS_ASM__ */
-
-
-#endif /* AT91SAM7X128_H */
diff --git a/Demo/uIP_Demo_IAR_ARM7/SrcIAR/ioat91sam7x256.h b/Demo/uIP_Demo_IAR_ARM7/SrcIAR/ioat91sam7x256.h
deleted file mode 100644
index 742f25c6c..000000000
--- a/Demo/uIP_Demo_IAR_ARM7/SrcIAR/ioat91sam7x256.h
+++ /dev/null
@@ -1,4700 +0,0 @@
-// - ----------------------------------------------------------------------------
-// -          ATMEL Microcontroller Software Support  -  ROUSSET  -
-// - ----------------------------------------------------------------------------
-// -  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-// -  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-// -  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-// -  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-// -  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// -  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-// -  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-// -  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-// -  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-// -  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// - ----------------------------------------------------------------------------
-// - File Name           : AT91SAM7X256.h
-// - Object              : AT91SAM7X256 definitions
-// - Generated           : AT91 SW Application Group  05/20/2005 (16:22:29)
-// - 
-// - CVS Reference       : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005//
-// - CVS Reference       : /SYS_SAM7X.pl/1.3/Tue Feb  1 17:01:43 2005//
-// - CVS Reference       : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
-// - CVS Reference       : /PMC_SAM7X.pl/1.4/Tue Feb  8 13:58:10 2005//
-// - CVS Reference       : /RSTC_SAM7X.pl/1.1/Tue Feb  1 16:16:26 2005//
-// - CVS Reference       : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
-// - CVS Reference       : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
-// - CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
-// - CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:18:28 2005//
-// - CVS Reference       : /RTTC_6081A.pl/1.2/Tue Nov  9 14:43:58 2004//
-// - CVS Reference       : /PITC_6079A.pl/1.2/Tue Nov  9 14:43:56 2004//
-// - CVS Reference       : /WDTC_6080A.pl/1.3/Tue Nov  9 14:44:00 2004//
-// - CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:05:48 2005//
-// - CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 08:48:54 2005//
-// - CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
-// - CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
-// - CVS Reference       : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
-// - CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
-// - CVS Reference       : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
-// - CVS Reference       : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
-// - CVS Reference       : /CAN_6019B.pl/1.1/Tue Mar  8 12:42:22 2005//
-// - CVS Reference       : /EMACB_6119A.pl/1.5/Thu Feb  3 15:52:04 2005//
-// - CVS Reference       : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
-// - CVS Reference       : /AES_6149A.pl/1.10/Mon Feb  7 09:44:25 2005//
-// - CVS Reference       : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
-// - ----------------------------------------------------------------------------
-
-#ifndef AT91SAM7X256_H
-#define AT91SAM7X256_H
-
-#ifdef __IAR_SYSTEMS_ICC__
-
-typedef volatile unsigned int AT91_REG;// Hardware register definition
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR System Peripherals
-// *****************************************************************************
-typedef struct _AT91S_SYS {
-	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
-	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
-	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
-	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
-	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
-	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
-	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
-	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
-	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
-	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
-	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
-	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
-	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
-	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
-	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
-	AT91_REG	 Reserved2[45]; 	// 
-	AT91_REG	 DBGU_CR; 	// Control Register
-	AT91_REG	 DBGU_MR; 	// Mode Register
-	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
-	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
-	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
-	AT91_REG	 DBGU_CSR; 	// Channel Status Register
-	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
-	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
-	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 Reserved3[7]; 	// 
-	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
-	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
-	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
-	AT91_REG	 Reserved4[45]; 	// 
-	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
-	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
-	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
-	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
-	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
-	AT91_REG	 Reserved5[54]; 	// 
-	AT91_REG	 PIOA_PER; 	// PIO Enable Register
-	AT91_REG	 PIOA_PDR; 	// PIO Disable Register
-	AT91_REG	 PIOA_PSR; 	// PIO Status Register
-	AT91_REG	 Reserved6[1]; 	// 
-	AT91_REG	 PIOA_OER; 	// Output Enable Register
-	AT91_REG	 PIOA_ODR; 	// Output Disable Registerr
-	AT91_REG	 PIOA_OSR; 	// Output Status Register
-	AT91_REG	 Reserved7[1]; 	// 
-	AT91_REG	 PIOA_IFER; 	// Input Filter Enable Register
-	AT91_REG	 PIOA_IFDR; 	// Input Filter Disable Register
-	AT91_REG	 PIOA_IFSR; 	// Input Filter Status Register
-	AT91_REG	 Reserved8[1]; 	// 
-	AT91_REG	 PIOA_SODR; 	// Set Output Data Register
-	AT91_REG	 PIOA_CODR; 	// Clear Output Data Register
-	AT91_REG	 PIOA_ODSR; 	// Output Data Status Register
-	AT91_REG	 PIOA_PDSR; 	// Pin Data Status Register
-	AT91_REG	 PIOA_IER; 	// Interrupt Enable Register
-	AT91_REG	 PIOA_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PIOA_IMR; 	// Interrupt Mask Register
-	AT91_REG	 PIOA_ISR; 	// Interrupt Status Register
-	AT91_REG	 PIOA_MDER; 	// Multi-driver Enable Register
-	AT91_REG	 PIOA_MDDR; 	// Multi-driver Disable Register
-	AT91_REG	 PIOA_MDSR; 	// Multi-driver Status Register
-	AT91_REG	 Reserved9[1]; 	// 
-	AT91_REG	 PIOA_PPUDR; 	// Pull-up Disable Register
-	AT91_REG	 PIOA_PPUER; 	// Pull-up Enable Register
-	AT91_REG	 PIOA_PPUSR; 	// Pull-up Status Register
-	AT91_REG	 Reserved10[1]; 	// 
-	AT91_REG	 PIOA_ASR; 	// Select A Register
-	AT91_REG	 PIOA_BSR; 	// Select B Register
-	AT91_REG	 PIOA_ABSR; 	// AB Select Status Register
-	AT91_REG	 Reserved11[9]; 	// 
-	AT91_REG	 PIOA_OWER; 	// Output Write Enable Register
-	AT91_REG	 PIOA_OWDR; 	// Output Write Disable Register
-	AT91_REG	 PIOA_OWSR; 	// Output Write Status Register
-	AT91_REG	 Reserved12[85]; 	// 
-	AT91_REG	 PIOB_PER; 	// PIO Enable Register
-	AT91_REG	 PIOB_PDR; 	// PIO Disable Register
-	AT91_REG	 PIOB_PSR; 	// PIO Status Register
-	AT91_REG	 Reserved13[1]; 	// 
-	AT91_REG	 PIOB_OER; 	// Output Enable Register
-	AT91_REG	 PIOB_ODR; 	// Output Disable Registerr
-	AT91_REG	 PIOB_OSR; 	// Output Status Register
-	AT91_REG	 Reserved14[1]; 	// 
-	AT91_REG	 PIOB_IFER; 	// Input Filter Enable Register
-	AT91_REG	 PIOB_IFDR; 	// Input Filter Disable Register
-	AT91_REG	 PIOB_IFSR; 	// Input Filter Status Register
-	AT91_REG	 Reserved15[1]; 	// 
-	AT91_REG	 PIOB_SODR; 	// Set Output Data Register
-	AT91_REG	 PIOB_CODR; 	// Clear Output Data Register
-	AT91_REG	 PIOB_ODSR; 	// Output Data Status Register
-	AT91_REG	 PIOB_PDSR; 	// Pin Data Status Register
-	AT91_REG	 PIOB_IER; 	// Interrupt Enable Register
-	AT91_REG	 PIOB_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PIOB_IMR; 	// Interrupt Mask Register
-	AT91_REG	 PIOB_ISR; 	// Interrupt Status Register
-	AT91_REG	 PIOB_MDER; 	// Multi-driver Enable Register
-	AT91_REG	 PIOB_MDDR; 	// Multi-driver Disable Register
-	AT91_REG	 PIOB_MDSR; 	// Multi-driver Status Register
-	AT91_REG	 Reserved16[1]; 	// 
-	AT91_REG	 PIOB_PPUDR; 	// Pull-up Disable Register
-	AT91_REG	 PIOB_PPUER; 	// Pull-up Enable Register
-	AT91_REG	 PIOB_PPUSR; 	// Pull-up Status Register
-	AT91_REG	 Reserved17[1]; 	// 
-	AT91_REG	 PIOB_ASR; 	// Select A Register
-	AT91_REG	 PIOB_BSR; 	// Select B Register
-	AT91_REG	 PIOB_ABSR; 	// AB Select Status Register
-	AT91_REG	 Reserved18[9]; 	// 
-	AT91_REG	 PIOB_OWER; 	// Output Write Enable Register
-	AT91_REG	 PIOB_OWDR; 	// Output Write Disable Register
-	AT91_REG	 PIOB_OWSR; 	// Output Write Status Register
-	AT91_REG	 Reserved19[341]; 	// 
-	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
-	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
-	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
-	AT91_REG	 Reserved20[1]; 	// 
-	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
-	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
-	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
-	AT91_REG	 Reserved21[1]; 	// 
-	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
-	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 Reserved22[1]; 	// 
-	AT91_REG	 PMC_PLLR; 	// PLL Register
-	AT91_REG	 PMC_MCKR; 	// Master Clock Register
-	AT91_REG	 Reserved23[3]; 	// 
-	AT91_REG	 PMC_PCKR[4]; 	// Programmable Clock Register
-	AT91_REG	 Reserved24[4]; 	// 
-	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
-	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PMC_SR; 	// Status Register
-	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved25[36]; 	// 
-	AT91_REG	 RSTC_RCR; 	// Reset Control Register
-	AT91_REG	 RSTC_RSR; 	// Reset Status Register
-	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
-	AT91_REG	 Reserved26[5]; 	// 
-	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
-	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
-	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
-	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
-	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
-	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
-	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
-	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
-	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
-	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
-	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
-	AT91_REG	 Reserved27[5]; 	// 
-	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
-} AT91S_SYS, *AT91PS_SYS;
-
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
-// *****************************************************************************
-typedef struct _AT91S_AIC {
-	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
-	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
-	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
-	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
-	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
-	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
-	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
-	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
-	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
-	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
-	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
-	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
-	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
-	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
-	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
-} AT91S_AIC, *AT91PS_AIC;
-
-// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
-#define AT91C_AIC_PRIOR       ((unsigned int) 0x7 <<  0) // (AIC) Priority Level
-#define 	AT91C_AIC_PRIOR_LOWEST               ((unsigned int) 0x0) // (AIC) Lowest priority level
-#define 	AT91C_AIC_PRIOR_HIGHEST              ((unsigned int) 0x7) // (AIC) Highest priority level
-#define AT91C_AIC_SRCTYPE     ((unsigned int) 0x3 <<  5) // (AIC) Interrupt Source Type
-#define 	AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       ((unsigned int) 0x0 <<  5) // (AIC) Internal Sources Code Label High-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        ((unsigned int) 0x0 <<  5) // (AIC) External Sources Code Label Low-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) Internal Sources Code Label Positive Edge triggered
-#define 	AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) External Sources Code Label Negative Edge triggered
-#define 	AT91C_AIC_SRCTYPE_HIGH_LEVEL           ((unsigned int) 0x2 <<  5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_POSITIVE_EDGE        ((unsigned int) 0x3 <<  5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
-// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
-#define AT91C_AIC_NFIQ        ((unsigned int) 0x1 <<  0) // (AIC) NFIQ Status
-#define AT91C_AIC_NIRQ        ((unsigned int) 0x1 <<  1) // (AIC) NIRQ Status
-// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
-#define AT91C_AIC_DCR_PROT    ((unsigned int) 0x1 <<  0) // (AIC) Protection Mode
-#define AT91C_AIC_DCR_GMSK    ((unsigned int) 0x1 <<  1) // (AIC) General Mask
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
-// *****************************************************************************
-typedef struct _AT91S_PDC {
-	AT91_REG	 PDC_RPR; 	// Receive Pointer Register
-	AT91_REG	 PDC_RCR; 	// Receive Counter Register
-	AT91_REG	 PDC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 PDC_TCR; 	// Transmit Counter Register
-	AT91_REG	 PDC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 PDC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 PDC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 PDC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 PDC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 PDC_PTSR; 	// PDC Transfer Status Register
-} AT91S_PDC, *AT91PS_PDC;
-
-// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
-#define AT91C_PDC_RXTEN       ((unsigned int) 0x1 <<  0) // (PDC) Receiver Transfer Enable
-#define AT91C_PDC_RXTDIS      ((unsigned int) 0x1 <<  1) // (PDC) Receiver Transfer Disable
-#define AT91C_PDC_TXTEN       ((unsigned int) 0x1 <<  8) // (PDC) Transmitter Transfer Enable
-#define AT91C_PDC_TXTDIS      ((unsigned int) 0x1 <<  9) // (PDC) Transmitter Transfer Disable
-// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Debug Unit
-// *****************************************************************************
-typedef struct _AT91S_DBGU {
-	AT91_REG	 DBGU_CR; 	// Control Register
-	AT91_REG	 DBGU_MR; 	// Mode Register
-	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
-	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
-	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
-	AT91_REG	 DBGU_CSR; 	// Channel Status Register
-	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
-	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
-	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 Reserved0[7]; 	// 
-	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
-	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
-	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
-	AT91_REG	 Reserved1[45]; 	// 
-	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
-	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
-	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
-	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
-	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
-} AT91S_DBGU, *AT91PS_DBGU;
-
-// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
-#define AT91C_US_RSTRX        ((unsigned int) 0x1 <<  2) // (DBGU) Reset Receiver
-#define AT91C_US_RSTTX        ((unsigned int) 0x1 <<  3) // (DBGU) Reset Transmitter
-#define AT91C_US_RXEN         ((unsigned int) 0x1 <<  4) // (DBGU) Receiver Enable
-#define AT91C_US_RXDIS        ((unsigned int) 0x1 <<  5) // (DBGU) Receiver Disable
-#define AT91C_US_TXEN         ((unsigned int) 0x1 <<  6) // (DBGU) Transmitter Enable
-#define AT91C_US_TXDIS        ((unsigned int) 0x1 <<  7) // (DBGU) Transmitter Disable
-#define AT91C_US_RSTSTA       ((unsigned int) 0x1 <<  8) // (DBGU) Reset Status Bits
-// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
-#define AT91C_US_PAR          ((unsigned int) 0x7 <<  9) // (DBGU) Parity type
-#define 	AT91C_US_PAR_EVEN                 ((unsigned int) 0x0 <<  9) // (DBGU) Even Parity
-#define 	AT91C_US_PAR_ODD                  ((unsigned int) 0x1 <<  9) // (DBGU) Odd Parity
-#define 	AT91C_US_PAR_SPACE                ((unsigned int) 0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
-#define 	AT91C_US_PAR_MARK                 ((unsigned int) 0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
-#define 	AT91C_US_PAR_NONE                 ((unsigned int) 0x4 <<  9) // (DBGU) No Parity
-#define 	AT91C_US_PAR_MULTI_DROP           ((unsigned int) 0x6 <<  9) // (DBGU) Multi-drop mode
-#define AT91C_US_CHMODE       ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
-#define 	AT91C_US_CHMODE_NORMAL               ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-#define 	AT91C_US_CHMODE_AUTO                 ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-#define 	AT91C_US_CHMODE_LOCAL                ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-#define 	AT91C_US_CHMODE_REMOTE               ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
-#define AT91C_US_RXRDY        ((unsigned int) 0x1 <<  0) // (DBGU) RXRDY Interrupt
-#define AT91C_US_TXRDY        ((unsigned int) 0x1 <<  1) // (DBGU) TXRDY Interrupt
-#define AT91C_US_ENDRX        ((unsigned int) 0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
-#define AT91C_US_ENDTX        ((unsigned int) 0x1 <<  4) // (DBGU) End of Transmit Interrupt
-#define AT91C_US_OVRE         ((unsigned int) 0x1 <<  5) // (DBGU) Overrun Interrupt
-#define AT91C_US_FRAME        ((unsigned int) 0x1 <<  6) // (DBGU) Framing Error Interrupt
-#define AT91C_US_PARE         ((unsigned int) 0x1 <<  7) // (DBGU) Parity Error Interrupt
-#define AT91C_US_TXEMPTY      ((unsigned int) 0x1 <<  9) // (DBGU) TXEMPTY Interrupt
-#define AT91C_US_TXBUFE       ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
-#define AT91C_US_RXBUFF       ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
-#define AT91C_US_COMM_TX      ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
-#define AT91C_US_COMM_RX      ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
-// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
-// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
-// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
-// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
-#define AT91C_US_FORCE_NTRST  ((unsigned int) 0x1 <<  0) // (DBGU) Force NTRST in JTAG
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
-// *****************************************************************************
-typedef struct _AT91S_PIO {
-	AT91_REG	 PIO_PER; 	// PIO Enable Register
-	AT91_REG	 PIO_PDR; 	// PIO Disable Register
-	AT91_REG	 PIO_PSR; 	// PIO Status Register
-	AT91_REG	 Reserved0[1]; 	// 
-	AT91_REG	 PIO_OER; 	// Output Enable Register
-	AT91_REG	 PIO_ODR; 	// Output Disable Registerr
-	AT91_REG	 PIO_OSR; 	// Output Status Register
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 PIO_IFER; 	// Input Filter Enable Register
-	AT91_REG	 PIO_IFDR; 	// Input Filter Disable Register
-	AT91_REG	 PIO_IFSR; 	// Input Filter Status Register
-	AT91_REG	 Reserved2[1]; 	// 
-	AT91_REG	 PIO_SODR; 	// Set Output Data Register
-	AT91_REG	 PIO_CODR; 	// Clear Output Data Register
-	AT91_REG	 PIO_ODSR; 	// Output Data Status Register
-	AT91_REG	 PIO_PDSR; 	// Pin Data Status Register
-	AT91_REG	 PIO_IER; 	// Interrupt Enable Register
-	AT91_REG	 PIO_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PIO_IMR; 	// Interrupt Mask Register
-	AT91_REG	 PIO_ISR; 	// Interrupt Status Register
-	AT91_REG	 PIO_MDER; 	// Multi-driver Enable Register
-	AT91_REG	 PIO_MDDR; 	// Multi-driver Disable Register
-	AT91_REG	 PIO_MDSR; 	// Multi-driver Status Register
-	AT91_REG	 Reserved3[1]; 	// 
-	AT91_REG	 PIO_PPUDR; 	// Pull-up Disable Register
-	AT91_REG	 PIO_PPUER; 	// Pull-up Enable Register
-	AT91_REG	 PIO_PPUSR; 	// Pull-up Status Register
-	AT91_REG	 Reserved4[1]; 	// 
-	AT91_REG	 PIO_ASR; 	// Select A Register
-	AT91_REG	 PIO_BSR; 	// Select B Register
-	AT91_REG	 PIO_ABSR; 	// AB Select Status Register
-	AT91_REG	 Reserved5[9]; 	// 
-	AT91_REG	 PIO_OWER; 	// Output Write Enable Register
-	AT91_REG	 PIO_OWDR; 	// Output Write Disable Register
-	AT91_REG	 PIO_OWSR; 	// Output Write Status Register
-} AT91S_PIO, *AT91PS_PIO;
-
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
-// *****************************************************************************
-typedef struct _AT91S_CKGR {
-	AT91_REG	 CKGR_MOR; 	// Main Oscillator Register
-	AT91_REG	 CKGR_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 Reserved0[1]; 	// 
-	AT91_REG	 CKGR_PLLR; 	// PLL Register
-} AT91S_CKGR, *AT91PS_CKGR;
-
-// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
-#define AT91C_CKGR_MOSCEN     ((unsigned int) 0x1 <<  0) // (CKGR) Main Oscillator Enable
-#define AT91C_CKGR_OSCBYPASS  ((unsigned int) 0x1 <<  1) // (CKGR) Main Oscillator Bypass
-#define AT91C_CKGR_OSCOUNT    ((unsigned int) 0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
-// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
-#define AT91C_CKGR_MAINF      ((unsigned int) 0xFFFF <<  0) // (CKGR) Main Clock Frequency
-#define AT91C_CKGR_MAINRDY    ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
-// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 
-#define AT91C_CKGR_DIV        ((unsigned int) 0xFF <<  0) // (CKGR) Divider Selected
-#define 	AT91C_CKGR_DIV_0                    ((unsigned int) 0x0) // (CKGR) Divider output is 0
-#define 	AT91C_CKGR_DIV_BYPASS               ((unsigned int) 0x1) // (CKGR) Divider is bypassed
-#define AT91C_CKGR_PLLCOUNT   ((unsigned int) 0x3F <<  8) // (CKGR) PLL Counter
-#define AT91C_CKGR_OUT        ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
-#define 	AT91C_CKGR_OUT_0                    ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_1                    ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_2                    ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_3                    ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_MUL        ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
-#define AT91C_CKGR_USBDIV     ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
-#define 	AT91C_CKGR_USBDIV_0                    ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
-#define 	AT91C_CKGR_USBDIV_1                    ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
-#define 	AT91C_CKGR_USBDIV_2                    ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Power Management Controler
-// *****************************************************************************
-typedef struct _AT91S_PMC {
-	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
-	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
-	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
-	AT91_REG	 Reserved0[1]; 	// 
-	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
-	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
-	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
-	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 Reserved2[1]; 	// 
-	AT91_REG	 PMC_PLLR; 	// PLL Register
-	AT91_REG	 PMC_MCKR; 	// Master Clock Register
-	AT91_REG	 Reserved3[3]; 	// 
-	AT91_REG	 PMC_PCKR[4]; 	// Programmable Clock Register
-	AT91_REG	 Reserved4[4]; 	// 
-	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
-	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PMC_SR; 	// Status Register
-	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
-} AT91S_PMC, *AT91PS_PMC;
-
-// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
-#define AT91C_PMC_PCK         ((unsigned int) 0x1 <<  0) // (PMC) Processor Clock
-#define AT91C_PMC_UDP         ((unsigned int) 0x1 <<  7) // (PMC) USB Device Port Clock
-#define AT91C_PMC_PCK0        ((unsigned int) 0x1 <<  8) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK1        ((unsigned int) 0x1 <<  9) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK2        ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK3        ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
-// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
-// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
-// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
-// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
-// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 
-// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
-#define AT91C_PMC_CSS         ((unsigned int) 0x3 <<  0) // (PMC) Programmable Clock Selection
-#define 	AT91C_PMC_CSS_SLOW_CLK             ((unsigned int) 0x0) // (PMC) Slow Clock is selected
-#define 	AT91C_PMC_CSS_MAIN_CLK             ((unsigned int) 0x1) // (PMC) Main Clock is selected
-#define 	AT91C_PMC_CSS_PLL_CLK              ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
-#define AT91C_PMC_PRES        ((unsigned int) 0x7 <<  2) // (PMC) Programmable Clock Prescaler
-#define 	AT91C_PMC_PRES_CLK                  ((unsigned int) 0x0 <<  2) // (PMC) Selected clock
-#define 	AT91C_PMC_PRES_CLK_2                ((unsigned int) 0x1 <<  2) // (PMC) Selected clock divided by 2
-#define 	AT91C_PMC_PRES_CLK_4                ((unsigned int) 0x2 <<  2) // (PMC) Selected clock divided by 4
-#define 	AT91C_PMC_PRES_CLK_8                ((unsigned int) 0x3 <<  2) // (PMC) Selected clock divided by 8
-#define 	AT91C_PMC_PRES_CLK_16               ((unsigned int) 0x4 <<  2) // (PMC) Selected clock divided by 16
-#define 	AT91C_PMC_PRES_CLK_32               ((unsigned int) 0x5 <<  2) // (PMC) Selected clock divided by 32
-#define 	AT91C_PMC_PRES_CLK_64               ((unsigned int) 0x6 <<  2) // (PMC) Selected clock divided by 64
-// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
-// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
-#define AT91C_PMC_MOSCS       ((unsigned int) 0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
-#define AT91C_PMC_LOCK        ((unsigned int) 0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
-#define AT91C_PMC_MCKRDY      ((unsigned int) 0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK0RDY     ((unsigned int) 0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK1RDY     ((unsigned int) 0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK2RDY     ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK3RDY     ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
-// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
-// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
-// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_RSTC {
-	AT91_REG	 RSTC_RCR; 	// Reset Control Register
-	AT91_REG	 RSTC_RSR; 	// Reset Status Register
-	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
-} AT91S_RSTC, *AT91PS_RSTC;
-
-// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
-#define AT91C_RSTC_PROCRST    ((unsigned int) 0x1 <<  0) // (RSTC) Processor Reset
-#define AT91C_RSTC_PERRST     ((unsigned int) 0x1 <<  2) // (RSTC) Peripheral Reset
-#define AT91C_RSTC_EXTRST     ((unsigned int) 0x1 <<  3) // (RSTC) External Reset
-#define AT91C_RSTC_KEY        ((unsigned int) 0xFF << 24) // (RSTC) Password
-// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
-#define AT91C_RSTC_URSTS      ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Status
-#define AT91C_RSTC_BODSTS     ((unsigned int) 0x1 <<  1) // (RSTC) Brownout Detection Status
-#define AT91C_RSTC_RSTTYP     ((unsigned int) 0x7 <<  8) // (RSTC) Reset Type
-#define 	AT91C_RSTC_RSTTYP_POWERUP              ((unsigned int) 0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
-#define 	AT91C_RSTC_RSTTYP_WAKEUP               ((unsigned int) 0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.
-#define 	AT91C_RSTC_RSTTYP_WATCHDOG             ((unsigned int) 0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
-#define 	AT91C_RSTC_RSTTYP_SOFTWARE             ((unsigned int) 0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
-#define 	AT91C_RSTC_RSTTYP_USER                 ((unsigned int) 0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
-#define 	AT91C_RSTC_RSTTYP_BROWNOUT             ((unsigned int) 0x5 <<  8) // (RSTC) Brownout Reset occured.
-#define AT91C_RSTC_NRSTL      ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
-#define AT91C_RSTC_SRCMP      ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
-// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
-#define AT91C_RSTC_URSTEN     ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Enable
-#define AT91C_RSTC_URSTIEN    ((unsigned int) 0x1 <<  4) // (RSTC) User Reset Interrupt Enable
-#define AT91C_RSTC_ERSTL      ((unsigned int) 0xF <<  8) // (RSTC) User Reset Enable
-#define AT91C_RSTC_BODIEN     ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_RTTC {
-	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
-	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
-	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
-	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
-} AT91S_RTTC, *AT91PS_RTTC;
-
-// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
-#define AT91C_RTTC_RTPRES     ((unsigned int) 0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
-#define AT91C_RTTC_ALMIEN     ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
-#define AT91C_RTTC_RTTINCIEN  ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
-#define AT91C_RTTC_RTTRST     ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
-// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
-#define AT91C_RTTC_ALMV       ((unsigned int) 0x0 <<  0) // (RTTC) Alarm Value
-// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
-#define AT91C_RTTC_CRTV       ((unsigned int) 0x0 <<  0) // (RTTC) Current Real-time Value
-// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
-#define AT91C_RTTC_ALMS       ((unsigned int) 0x1 <<  0) // (RTTC) Real-time Alarm Status
-#define AT91C_RTTC_RTTINC     ((unsigned int) 0x1 <<  1) // (RTTC) Real-time Timer Increment
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_PITC {
-	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
-	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
-	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
-	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
-} AT91S_PITC, *AT91PS_PITC;
-
-// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
-#define AT91C_PITC_PIV        ((unsigned int) 0xFFFFF <<  0) // (PITC) Periodic Interval Value
-#define AT91C_PITC_PITEN      ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
-#define AT91C_PITC_PITIEN     ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
-// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
-#define AT91C_PITC_PITS       ((unsigned int) 0x1 <<  0) // (PITC) Periodic Interval Timer Status
-// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
-#define AT91C_PITC_CPIV       ((unsigned int) 0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
-#define AT91C_PITC_PICNT      ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
-// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_WDTC {
-	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
-	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
-	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
-} AT91S_WDTC, *AT91PS_WDTC;
-
-// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
-#define AT91C_WDTC_WDRSTT     ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Restart
-#define AT91C_WDTC_KEY        ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password
-// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
-#define AT91C_WDTC_WDV        ((unsigned int) 0xFFF <<  0) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDFIEN     ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
-#define AT91C_WDTC_WDRSTEN    ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
-#define AT91C_WDTC_WDRPROC    ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDDIS      ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
-#define AT91C_WDTC_WDD        ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
-#define AT91C_WDTC_WDDBGHLT   ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
-#define AT91C_WDTC_WDIDLEHLT  ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
-// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
-#define AT91C_WDTC_WDUNF      ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Underflow
-#define AT91C_WDTC_WDERR      ((unsigned int) 0x1 <<  1) // (WDTC) Watchdog Error
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_VREG {
-	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
-} AT91S_VREG, *AT91PS_VREG;
-
-// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- 
-#define AT91C_VREG_PSTDBY     ((unsigned int) 0x1 <<  0) // (VREG) Voltage Regulator Power Standby Mode
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_MC {
-	AT91_REG	 MC_RCR; 	// MC Remap Control Register
-	AT91_REG	 MC_ASR; 	// MC Abort Status Register
-	AT91_REG	 MC_AASR; 	// MC Abort Address Status Register
-	AT91_REG	 Reserved0[21]; 	// 
-	AT91_REG	 MC_FMR; 	// MC Flash Mode Register
-	AT91_REG	 MC_FCR; 	// MC Flash Command Register
-	AT91_REG	 MC_FSR; 	// MC Flash Status Register
-} AT91S_MC, *AT91PS_MC;
-
-// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
-#define AT91C_MC_RCB          ((unsigned int) 0x1 <<  0) // (MC) Remap Command Bit
-// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
-#define AT91C_MC_UNDADD       ((unsigned int) 0x1 <<  0) // (MC) Undefined Addess Abort Status
-#define AT91C_MC_MISADD       ((unsigned int) 0x1 <<  1) // (MC) Misaligned Addess Abort Status
-#define AT91C_MC_ABTSZ        ((unsigned int) 0x3 <<  8) // (MC) Abort Size Status
-#define 	AT91C_MC_ABTSZ_BYTE                 ((unsigned int) 0x0 <<  8) // (MC) Byte
-#define 	AT91C_MC_ABTSZ_HWORD                ((unsigned int) 0x1 <<  8) // (MC) Half-word
-#define 	AT91C_MC_ABTSZ_WORD                 ((unsigned int) 0x2 <<  8) // (MC) Word
-#define AT91C_MC_ABTTYP       ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
-#define 	AT91C_MC_ABTTYP_DATAR                ((unsigned int) 0x0 << 10) // (MC) Data Read
-#define 	AT91C_MC_ABTTYP_DATAW                ((unsigned int) 0x1 << 10) // (MC) Data Write
-#define 	AT91C_MC_ABTTYP_FETCH                ((unsigned int) 0x2 << 10) // (MC) Code Fetch
-#define AT91C_MC_MST0         ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
-#define AT91C_MC_MST1         ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
-#define AT91C_MC_SVMST0       ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
-#define AT91C_MC_SVMST1       ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
-// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- 
-#define AT91C_MC_FRDY         ((unsigned int) 0x1 <<  0) // (MC) Flash Ready
-#define AT91C_MC_LOCKE        ((unsigned int) 0x1 <<  2) // (MC) Lock Error
-#define AT91C_MC_PROGE        ((unsigned int) 0x1 <<  3) // (MC) Programming Error
-#define AT91C_MC_NEBP         ((unsigned int) 0x1 <<  7) // (MC) No Erase Before Programming
-#define AT91C_MC_FWS          ((unsigned int) 0x3 <<  8) // (MC) Flash Wait State
-#define 	AT91C_MC_FWS_0FWS                 ((unsigned int) 0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations
-#define 	AT91C_MC_FWS_1FWS                 ((unsigned int) 0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations
-#define 	AT91C_MC_FWS_2FWS                 ((unsigned int) 0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations
-#define 	AT91C_MC_FWS_3FWS                 ((unsigned int) 0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations
-#define AT91C_MC_FMCN         ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
-// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- 
-#define AT91C_MC_FCMD         ((unsigned int) 0xF <<  0) // (MC) Flash Command
-#define 	AT91C_MC_FCMD_START_PROG           ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
-#define 	AT91C_MC_FCMD_LOCK                 ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define 	AT91C_MC_FCMD_PROG_AND_LOCK        ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
-#define 	AT91C_MC_FCMD_UNLOCK               ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define 	AT91C_MC_FCMD_ERASE_ALL            ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
-#define 	AT91C_MC_FCMD_SET_GP_NVM           ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
-#define 	AT91C_MC_FCMD_CLR_GP_NVM           ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
-#define 	AT91C_MC_FCMD_SET_SECURITY         ((unsigned int) 0xF) // (MC) Set Security Bit.
-#define AT91C_MC_PAGEN        ((unsigned int) 0x3FF <<  8) // (MC) Page Number
-#define AT91C_MC_KEY          ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
-// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- 
-#define AT91C_MC_SECURITY     ((unsigned int) 0x1 <<  4) // (MC) Security Bit Status
-#define AT91C_MC_GPNVM0       ((unsigned int) 0x1 <<  8) // (MC) Sector 0 Lock Status
-#define AT91C_MC_GPNVM1       ((unsigned int) 0x1 <<  9) // (MC) Sector 1 Lock Status
-#define AT91C_MC_GPNVM2       ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
-#define AT91C_MC_GPNVM3       ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
-#define AT91C_MC_GPNVM4       ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
-#define AT91C_MC_GPNVM5       ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
-#define AT91C_MC_GPNVM6       ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
-#define AT91C_MC_GPNVM7       ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS0       ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
-#define AT91C_MC_LOCKS1       ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
-#define AT91C_MC_LOCKS2       ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
-#define AT91C_MC_LOCKS3       ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
-#define AT91C_MC_LOCKS4       ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
-#define AT91C_MC_LOCKS5       ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
-#define AT91C_MC_LOCKS6       ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
-#define AT91C_MC_LOCKS7       ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS8       ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
-#define AT91C_MC_LOCKS9       ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
-#define AT91C_MC_LOCKS10      ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
-#define AT91C_MC_LOCKS11      ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
-#define AT91C_MC_LOCKS12      ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
-#define AT91C_MC_LOCKS13      ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
-#define AT91C_MC_LOCKS14      ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
-#define AT91C_MC_LOCKS15      ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
-// *****************************************************************************
-typedef struct _AT91S_SPI {
-	AT91_REG	 SPI_CR; 	// Control Register
-	AT91_REG	 SPI_MR; 	// Mode Register
-	AT91_REG	 SPI_RDR; 	// Receive Data Register
-	AT91_REG	 SPI_TDR; 	// Transmit Data Register
-	AT91_REG	 SPI_SR; 	// Status Register
-	AT91_REG	 SPI_IER; 	// Interrupt Enable Register
-	AT91_REG	 SPI_IDR; 	// Interrupt Disable Register
-	AT91_REG	 SPI_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved0[4]; 	// 
-	AT91_REG	 SPI_CSR[4]; 	// Chip Select Register
-	AT91_REG	 Reserved1[48]; 	// 
-	AT91_REG	 SPI_RPR; 	// Receive Pointer Register
-	AT91_REG	 SPI_RCR; 	// Receive Counter Register
-	AT91_REG	 SPI_TPR; 	// Transmit Pointer Register
-	AT91_REG	 SPI_TCR; 	// Transmit Counter Register
-	AT91_REG	 SPI_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 SPI_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 SPI_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 SPI_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 SPI_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 SPI_PTSR; 	// PDC Transfer Status Register
-} AT91S_SPI, *AT91PS_SPI;
-
-// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
-#define AT91C_SPI_SPIEN       ((unsigned int) 0x1 <<  0) // (SPI) SPI Enable
-#define AT91C_SPI_SPIDIS      ((unsigned int) 0x1 <<  1) // (SPI) SPI Disable
-#define AT91C_SPI_SWRST       ((unsigned int) 0x1 <<  7) // (SPI) SPI Software reset
-#define AT91C_SPI_LASTXFER    ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
-// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
-#define AT91C_SPI_MSTR        ((unsigned int) 0x1 <<  0) // (SPI) Master/Slave Mode
-#define AT91C_SPI_PS          ((unsigned int) 0x1 <<  1) // (SPI) Peripheral Select
-#define 	AT91C_SPI_PS_FIXED                ((unsigned int) 0x0 <<  1) // (SPI) Fixed Peripheral Select
-#define 	AT91C_SPI_PS_VARIABLE             ((unsigned int) 0x1 <<  1) // (SPI) Variable Peripheral Select
-#define AT91C_SPI_PCSDEC      ((unsigned int) 0x1 <<  2) // (SPI) Chip Select Decode
-#define AT91C_SPI_FDIV        ((unsigned int) 0x1 <<  3) // (SPI) Clock Selection
-#define AT91C_SPI_MODFDIS     ((unsigned int) 0x1 <<  4) // (SPI) Mode Fault Detection
-#define AT91C_SPI_LLB         ((unsigned int) 0x1 <<  7) // (SPI) Clock Selection
-#define AT91C_SPI_PCS         ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
-#define AT91C_SPI_DLYBCS      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
-// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
-#define AT91C_SPI_RD          ((unsigned int) 0xFFFF <<  0) // (SPI) Receive Data
-#define AT91C_SPI_RPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
-#define AT91C_SPI_TD          ((unsigned int) 0xFFFF <<  0) // (SPI) Transmit Data
-#define AT91C_SPI_TPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
-#define AT91C_SPI_RDRF        ((unsigned int) 0x1 <<  0) // (SPI) Receive Data Register Full
-#define AT91C_SPI_TDRE        ((unsigned int) 0x1 <<  1) // (SPI) Transmit Data Register Empty
-#define AT91C_SPI_MODF        ((unsigned int) 0x1 <<  2) // (SPI) Mode Fault Error
-#define AT91C_SPI_OVRES       ((unsigned int) 0x1 <<  3) // (SPI) Overrun Error Status
-#define AT91C_SPI_ENDRX       ((unsigned int) 0x1 <<  4) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_ENDTX       ((unsigned int) 0x1 <<  5) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_RXBUFF      ((unsigned int) 0x1 <<  6) // (SPI) RXBUFF Interrupt
-#define AT91C_SPI_TXBUFE      ((unsigned int) 0x1 <<  7) // (SPI) TXBUFE Interrupt
-#define AT91C_SPI_NSSR        ((unsigned int) 0x1 <<  8) // (SPI) NSSR Interrupt
-#define AT91C_SPI_TXEMPTY     ((unsigned int) 0x1 <<  9) // (SPI) TXEMPTY Interrupt
-#define AT91C_SPI_SPIENS      ((unsigned int) 0x1 << 16) // (SPI) Enable Status
-// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
-// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
-// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
-// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
-#define AT91C_SPI_CPOL        ((unsigned int) 0x1 <<  0) // (SPI) Clock Polarity
-#define AT91C_SPI_NCPHA       ((unsigned int) 0x1 <<  1) // (SPI) Clock Phase
-#define AT91C_SPI_CSAAT       ((unsigned int) 0x1 <<  3) // (SPI) Chip Select Active After Transfer
-#define AT91C_SPI_BITS        ((unsigned int) 0xF <<  4) // (SPI) Bits Per Transfer
-#define 	AT91C_SPI_BITS_8                    ((unsigned int) 0x0 <<  4) // (SPI) 8 Bits Per transfer
-#define 	AT91C_SPI_BITS_9                    ((unsigned int) 0x1 <<  4) // (SPI) 9 Bits Per transfer
-#define 	AT91C_SPI_BITS_10                   ((unsigned int) 0x2 <<  4) // (SPI) 10 Bits Per transfer
-#define 	AT91C_SPI_BITS_11                   ((unsigned int) 0x3 <<  4) // (SPI) 11 Bits Per transfer
-#define 	AT91C_SPI_BITS_12                   ((unsigned int) 0x4 <<  4) // (SPI) 12 Bits Per transfer
-#define 	AT91C_SPI_BITS_13                   ((unsigned int) 0x5 <<  4) // (SPI) 13 Bits Per transfer
-#define 	AT91C_SPI_BITS_14                   ((unsigned int) 0x6 <<  4) // (SPI) 14 Bits Per transfer
-#define 	AT91C_SPI_BITS_15                   ((unsigned int) 0x7 <<  4) // (SPI) 15 Bits Per transfer
-#define 	AT91C_SPI_BITS_16                   ((unsigned int) 0x8 <<  4) // (SPI) 16 Bits Per transfer
-#define AT91C_SPI_SCBR        ((unsigned int) 0xFF <<  8) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBS       ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK
-#define AT91C_SPI_DLYBCT      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Usart
-// *****************************************************************************
-typedef struct _AT91S_USART {
-	AT91_REG	 US_CR; 	// Control Register
-	AT91_REG	 US_MR; 	// Mode Register
-	AT91_REG	 US_IER; 	// Interrupt Enable Register
-	AT91_REG	 US_IDR; 	// Interrupt Disable Register
-	AT91_REG	 US_IMR; 	// Interrupt Mask Register
-	AT91_REG	 US_CSR; 	// Channel Status Register
-	AT91_REG	 US_RHR; 	// Receiver Holding Register
-	AT91_REG	 US_THR; 	// Transmitter Holding Register
-	AT91_REG	 US_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 US_RTOR; 	// Receiver Time-out Register
-	AT91_REG	 US_TTGR; 	// Transmitter Time-guard Register
-	AT91_REG	 Reserved0[5]; 	// 
-	AT91_REG	 US_FIDI; 	// FI_DI_Ratio Register
-	AT91_REG	 US_NER; 	// Nb Errors Register
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 US_IF; 	// IRDA_FILTER Register
-	AT91_REG	 Reserved2[44]; 	// 
-	AT91_REG	 US_RPR; 	// Receive Pointer Register
-	AT91_REG	 US_RCR; 	// Receive Counter Register
-	AT91_REG	 US_TPR; 	// Transmit Pointer Register
-	AT91_REG	 US_TCR; 	// Transmit Counter Register
-	AT91_REG	 US_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 US_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 US_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 US_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 US_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 US_PTSR; 	// PDC Transfer Status Register
-} AT91S_USART, *AT91PS_USART;
-
-// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
-#define AT91C_US_STTBRK       ((unsigned int) 0x1 <<  9) // (USART) Start Break
-#define AT91C_US_STPBRK       ((unsigned int) 0x1 << 10) // (USART) Stop Break
-#define AT91C_US_STTTO        ((unsigned int) 0x1 << 11) // (USART) Start Time-out
-#define AT91C_US_SENDA        ((unsigned int) 0x1 << 12) // (USART) Send Address
-#define AT91C_US_RSTIT        ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
-#define AT91C_US_RSTNACK      ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
-#define AT91C_US_RETTO        ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
-#define AT91C_US_DTREN        ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
-#define AT91C_US_DTRDIS       ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
-#define AT91C_US_RTSEN        ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
-#define AT91C_US_RTSDIS       ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
-// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
-#define AT91C_US_USMODE       ((unsigned int) 0xF <<  0) // (USART) Usart mode
-#define 	AT91C_US_USMODE_NORMAL               ((unsigned int) 0x0) // (USART) Normal
-#define 	AT91C_US_USMODE_RS485                ((unsigned int) 0x1) // (USART) RS485
-#define 	AT91C_US_USMODE_HWHSH                ((unsigned int) 0x2) // (USART) Hardware Handshaking
-#define 	AT91C_US_USMODE_MODEM                ((unsigned int) 0x3) // (USART) Modem
-#define 	AT91C_US_USMODE_ISO7816_0            ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
-#define 	AT91C_US_USMODE_ISO7816_1            ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
-#define 	AT91C_US_USMODE_IRDA                 ((unsigned int) 0x8) // (USART) IrDA
-#define 	AT91C_US_USMODE_SWHSH                ((unsigned int) 0xC) // (USART) Software Handshaking
-#define AT91C_US_CLKS         ((unsigned int) 0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define 	AT91C_US_CLKS_CLOCK                ((unsigned int) 0x0 <<  4) // (USART) Clock
-#define 	AT91C_US_CLKS_FDIV1                ((unsigned int) 0x1 <<  4) // (USART) fdiv1
-#define 	AT91C_US_CLKS_SLOW                 ((unsigned int) 0x2 <<  4) // (USART) slow_clock (ARM)
-#define 	AT91C_US_CLKS_EXT                  ((unsigned int) 0x3 <<  4) // (USART) External (SCK)
-#define AT91C_US_CHRL         ((unsigned int) 0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define 	AT91C_US_CHRL_5_BITS               ((unsigned int) 0x0 <<  6) // (USART) Character Length: 5 bits
-#define 	AT91C_US_CHRL_6_BITS               ((unsigned int) 0x1 <<  6) // (USART) Character Length: 6 bits
-#define 	AT91C_US_CHRL_7_BITS               ((unsigned int) 0x2 <<  6) // (USART) Character Length: 7 bits
-#define 	AT91C_US_CHRL_8_BITS               ((unsigned int) 0x3 <<  6) // (USART) Character Length: 8 bits
-#define AT91C_US_SYNC         ((unsigned int) 0x1 <<  8) // (USART) Synchronous Mode Select
-#define AT91C_US_NBSTOP       ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
-#define 	AT91C_US_NBSTOP_1_BIT                ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
-#define 	AT91C_US_NBSTOP_15_BIT               ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-#define 	AT91C_US_NBSTOP_2_BIT                ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
-#define AT91C_US_MSBF         ((unsigned int) 0x1 << 16) // (USART) Bit Order
-#define AT91C_US_MODE9        ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
-#define AT91C_US_CKLO         ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
-#define AT91C_US_OVER         ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
-#define AT91C_US_INACK        ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
-#define AT91C_US_DSNACK       ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
-#define AT91C_US_MAX_ITER     ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
-#define AT91C_US_FILTER       ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
-// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
-#define AT91C_US_RXBRK        ((unsigned int) 0x1 <<  2) // (USART) Break Received/End of Break
-#define AT91C_US_TIMEOUT      ((unsigned int) 0x1 <<  8) // (USART) Receiver Time-out
-#define AT91C_US_ITERATION    ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
-#define AT91C_US_NACK         ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
-#define AT91C_US_RIIC         ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
-#define AT91C_US_DSRIC        ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
-#define AT91C_US_DCDIC        ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
-#define AT91C_US_CTSIC        ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
-// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
-// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
-// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
-#define AT91C_US_RI           ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
-#define AT91C_US_DSR          ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
-#define AT91C_US_DCD          ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
-#define AT91C_US_CTS          ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_SSC {
-	AT91_REG	 SSC_CR; 	// Control Register
-	AT91_REG	 SSC_CMR; 	// Clock Mode Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 SSC_RCMR; 	// Receive Clock ModeRegister
-	AT91_REG	 SSC_RFMR; 	// Receive Frame Mode Register
-	AT91_REG	 SSC_TCMR; 	// Transmit Clock Mode Register
-	AT91_REG	 SSC_TFMR; 	// Transmit Frame Mode Register
-	AT91_REG	 SSC_RHR; 	// Receive Holding Register
-	AT91_REG	 SSC_THR; 	// Transmit Holding Register
-	AT91_REG	 Reserved1[2]; 	// 
-	AT91_REG	 SSC_RSHR; 	// Receive Sync Holding Register
-	AT91_REG	 SSC_TSHR; 	// Transmit Sync Holding Register
-	AT91_REG	 Reserved2[2]; 	// 
-	AT91_REG	 SSC_SR; 	// Status Register
-	AT91_REG	 SSC_IER; 	// Interrupt Enable Register
-	AT91_REG	 SSC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 SSC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved3[44]; 	// 
-	AT91_REG	 SSC_RPR; 	// Receive Pointer Register
-	AT91_REG	 SSC_RCR; 	// Receive Counter Register
-	AT91_REG	 SSC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 SSC_TCR; 	// Transmit Counter Register
-	AT91_REG	 SSC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 SSC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 SSC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 SSC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 SSC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 SSC_PTSR; 	// PDC Transfer Status Register
-} AT91S_SSC, *AT91PS_SSC;
-
-// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
-#define AT91C_SSC_RXEN        ((unsigned int) 0x1 <<  0) // (SSC) Receive Enable
-#define AT91C_SSC_RXDIS       ((unsigned int) 0x1 <<  1) // (SSC) Receive Disable
-#define AT91C_SSC_TXEN        ((unsigned int) 0x1 <<  8) // (SSC) Transmit Enable
-#define AT91C_SSC_TXDIS       ((unsigned int) 0x1 <<  9) // (SSC) Transmit Disable
-#define AT91C_SSC_SWRST       ((unsigned int) 0x1 << 15) // (SSC) Software Reset
-// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
-#define AT91C_SSC_CKS         ((unsigned int) 0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
-#define 	AT91C_SSC_CKS_DIV                  ((unsigned int) 0x0) // (SSC) Divided Clock
-#define 	AT91C_SSC_CKS_TK                   ((unsigned int) 0x1) // (SSC) TK Clock signal
-#define 	AT91C_SSC_CKS_RK                   ((unsigned int) 0x2) // (SSC) RK pin
-#define AT91C_SSC_CKO         ((unsigned int) 0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
-#define 	AT91C_SSC_CKO_NONE                 ((unsigned int) 0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-#define 	AT91C_SSC_CKO_CONTINOUS            ((unsigned int) 0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
-#define 	AT91C_SSC_CKO_DATA_TX              ((unsigned int) 0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-#define AT91C_SSC_CKI         ((unsigned int) 0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
-#define AT91C_SSC_START       ((unsigned int) 0xF <<  8) // (SSC) Receive/Transmit Start Selection
-#define 	AT91C_SSC_START_CONTINOUS            ((unsigned int) 0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-#define 	AT91C_SSC_START_TX                   ((unsigned int) 0x1 <<  8) // (SSC) Transmit/Receive start
-#define 	AT91C_SSC_START_LOW_RF               ((unsigned int) 0x2 <<  8) // (SSC) Detection of a low level on RF input
-#define 	AT91C_SSC_START_HIGH_RF              ((unsigned int) 0x3 <<  8) // (SSC) Detection of a high level on RF input
-#define 	AT91C_SSC_START_FALL_RF              ((unsigned int) 0x4 <<  8) // (SSC) Detection of a falling edge on RF input
-#define 	AT91C_SSC_START_RISE_RF              ((unsigned int) 0x5 <<  8) // (SSC) Detection of a rising edge on RF input
-#define 	AT91C_SSC_START_LEVEL_RF             ((unsigned int) 0x6 <<  8) // (SSC) Detection of any level change on RF input
-#define 	AT91C_SSC_START_EDGE_RF              ((unsigned int) 0x7 <<  8) // (SSC) Detection of any edge on RF input
-#define 	AT91C_SSC_START_0                    ((unsigned int) 0x8 <<  8) // (SSC) Compare 0
-#define AT91C_SSC_STTDLY      ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
-#define AT91C_SSC_PERIOD      ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
-// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
-#define AT91C_SSC_DATLEN      ((unsigned int) 0x1F <<  0) // (SSC) Data Length
-#define AT91C_SSC_LOOP        ((unsigned int) 0x1 <<  5) // (SSC) Loop Mode
-#define AT91C_SSC_MSBF        ((unsigned int) 0x1 <<  7) // (SSC) Most Significant Bit First
-#define AT91C_SSC_DATNB       ((unsigned int) 0xF <<  8) // (SSC) Data Number per Frame
-#define AT91C_SSC_FSLEN       ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
-#define AT91C_SSC_FSOS        ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
-#define 	AT91C_SSC_FSOS_NONE                 ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-#define 	AT91C_SSC_FSOS_NEGATIVE             ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-#define 	AT91C_SSC_FSOS_POSITIVE             ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-#define 	AT91C_SSC_FSOS_LOW                  ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-#define 	AT91C_SSC_FSOS_HIGH                 ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-#define 	AT91C_SSC_FSOS_TOGGLE               ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-#define AT91C_SSC_FSEDGE      ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
-// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
-// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
-#define AT91C_SSC_DATDEF      ((unsigned int) 0x1 <<  5) // (SSC) Data Default Value
-#define AT91C_SSC_FSDEN       ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
-// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
-#define AT91C_SSC_TXRDY       ((unsigned int) 0x1 <<  0) // (SSC) Transmit Ready
-#define AT91C_SSC_TXEMPTY     ((unsigned int) 0x1 <<  1) // (SSC) Transmit Empty
-#define AT91C_SSC_ENDTX       ((unsigned int) 0x1 <<  2) // (SSC) End Of Transmission
-#define AT91C_SSC_TXBUFE      ((unsigned int) 0x1 <<  3) // (SSC) Transmit Buffer Empty
-#define AT91C_SSC_RXRDY       ((unsigned int) 0x1 <<  4) // (SSC) Receive Ready
-#define AT91C_SSC_OVRUN       ((unsigned int) 0x1 <<  5) // (SSC) Receive Overrun
-#define AT91C_SSC_ENDRX       ((unsigned int) 0x1 <<  6) // (SSC) End of Reception
-#define AT91C_SSC_RXBUFF      ((unsigned int) 0x1 <<  7) // (SSC) Receive Buffer Full
-#define AT91C_SSC_TXSYN       ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
-#define AT91C_SSC_RXSYN       ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
-#define AT91C_SSC_TXENA       ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
-#define AT91C_SSC_RXENA       ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
-// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
-// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
-// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Two-wire Interface
-// *****************************************************************************
-typedef struct _AT91S_TWI {
-	AT91_REG	 TWI_CR; 	// Control Register
-	AT91_REG	 TWI_MMR; 	// Master Mode Register
-	AT91_REG	 Reserved0[1]; 	// 
-	AT91_REG	 TWI_IADR; 	// Internal Address Register
-	AT91_REG	 TWI_CWGR; 	// Clock Waveform Generator Register
-	AT91_REG	 Reserved1[3]; 	// 
-	AT91_REG	 TWI_SR; 	// Status Register
-	AT91_REG	 TWI_IER; 	// Interrupt Enable Register
-	AT91_REG	 TWI_IDR; 	// Interrupt Disable Register
-	AT91_REG	 TWI_IMR; 	// Interrupt Mask Register
-	AT91_REG	 TWI_RHR; 	// Receive Holding Register
-	AT91_REG	 TWI_THR; 	// Transmit Holding Register
-} AT91S_TWI, *AT91PS_TWI;
-
-// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
-#define AT91C_TWI_START       ((unsigned int) 0x1 <<  0) // (TWI) Send a START Condition
-#define AT91C_TWI_STOP        ((unsigned int) 0x1 <<  1) // (TWI) Send a STOP Condition
-#define AT91C_TWI_MSEN        ((unsigned int) 0x1 <<  2) // (TWI) TWI Master Transfer Enabled
-#define AT91C_TWI_MSDIS       ((unsigned int) 0x1 <<  3) // (TWI) TWI Master Transfer Disabled
-#define AT91C_TWI_SWRST       ((unsigned int) 0x1 <<  7) // (TWI) Software Reset
-// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
-#define AT91C_TWI_IADRSZ      ((unsigned int) 0x3 <<  8) // (TWI) Internal Device Address Size
-#define 	AT91C_TWI_IADRSZ_NO                   ((unsigned int) 0x0 <<  8) // (TWI) No internal device address
-#define 	AT91C_TWI_IADRSZ_1_BYTE               ((unsigned int) 0x1 <<  8) // (TWI) One-byte internal device address
-#define 	AT91C_TWI_IADRSZ_2_BYTE               ((unsigned int) 0x2 <<  8) // (TWI) Two-byte internal device address
-#define 	AT91C_TWI_IADRSZ_3_BYTE               ((unsigned int) 0x3 <<  8) // (TWI) Three-byte internal device address
-#define AT91C_TWI_MREAD       ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
-#define AT91C_TWI_DADR        ((unsigned int) 0x7F << 16) // (TWI) Device Address
-// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
-#define AT91C_TWI_CLDIV       ((unsigned int) 0xFF <<  0) // (TWI) Clock Low Divider
-#define AT91C_TWI_CHDIV       ((unsigned int) 0xFF <<  8) // (TWI) Clock High Divider
-#define AT91C_TWI_CKDIV       ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
-// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
-#define AT91C_TWI_TXCOMP      ((unsigned int) 0x1 <<  0) // (TWI) Transmission Completed
-#define AT91C_TWI_RXRDY       ((unsigned int) 0x1 <<  1) // (TWI) Receive holding register ReaDY
-#define AT91C_TWI_TXRDY       ((unsigned int) 0x1 <<  2) // (TWI) Transmit holding register ReaDY
-#define AT91C_TWI_OVRE        ((unsigned int) 0x1 <<  6) // (TWI) Overrun Error
-#define AT91C_TWI_UNRE        ((unsigned int) 0x1 <<  7) // (TWI) Underrun Error
-#define AT91C_TWI_NACK        ((unsigned int) 0x1 <<  8) // (TWI) Not Acknowledged
-// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
-// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
-// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
-// *****************************************************************************
-typedef struct _AT91S_PWMC_CH {
-	AT91_REG	 PWMC_CMR; 	// Channel Mode Register
-	AT91_REG	 PWMC_CDTYR; 	// Channel Duty Cycle Register
-	AT91_REG	 PWMC_CPRDR; 	// Channel Period Register
-	AT91_REG	 PWMC_CCNTR; 	// Channel Counter Register
-	AT91_REG	 PWMC_CUPDR; 	// Channel Update Register
-	AT91_REG	 PWMC_Reserved[3]; 	// Reserved
-} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
-
-// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- 
-#define AT91C_PWMC_CPRE       ((unsigned int) 0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
-#define 	AT91C_PWMC_CPRE_MCK                  ((unsigned int) 0x0) // (PWMC_CH) 
-#define 	AT91C_PWMC_CPRE_MCKA                 ((unsigned int) 0xB) // (PWMC_CH) 
-#define 	AT91C_PWMC_CPRE_MCKB                 ((unsigned int) 0xC) // (PWMC_CH) 
-#define AT91C_PWMC_CALG       ((unsigned int) 0x1 <<  8) // (PWMC_CH) Channel Alignment
-#define AT91C_PWMC_CPOL       ((unsigned int) 0x1 <<  9) // (PWMC_CH) Channel Polarity
-#define AT91C_PWMC_CPD        ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
-// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- 
-#define AT91C_PWMC_CDTY       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
-// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- 
-#define AT91C_PWMC_CPRD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Period
-// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- 
-#define AT91C_PWMC_CCNT       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Counter
-// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- 
-#define AT91C_PWMC_CUPD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Update
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_PWMC {
-	AT91_REG	 PWMC_MR; 	// PWMC Mode Register
-	AT91_REG	 PWMC_ENA; 	// PWMC Enable Register
-	AT91_REG	 PWMC_DIS; 	// PWMC Disable Register
-	AT91_REG	 PWMC_SR; 	// PWMC Status Register
-	AT91_REG	 PWMC_IER; 	// PWMC Interrupt Enable Register
-	AT91_REG	 PWMC_IDR; 	// PWMC Interrupt Disable Register
-	AT91_REG	 PWMC_IMR; 	// PWMC Interrupt Mask Register
-	AT91_REG	 PWMC_ISR; 	// PWMC Interrupt Status Register
-	AT91_REG	 Reserved0[55]; 	// 
-	AT91_REG	 PWMC_VR; 	// PWMC Version Register
-	AT91_REG	 Reserved1[64]; 	// 
-	AT91S_PWMC_CH	 PWMC_CH[4]; 	// PWMC Channel
-} AT91S_PWMC, *AT91PS_PWMC;
-
-// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- 
-#define AT91C_PWMC_DIVA       ((unsigned int) 0xFF <<  0) // (PWMC) CLKA divide factor.
-#define AT91C_PWMC_PREA       ((unsigned int) 0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
-#define 	AT91C_PWMC_PREA_MCK                  ((unsigned int) 0x0 <<  8) // (PWMC) 
-#define AT91C_PWMC_DIVB       ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
-#define AT91C_PWMC_PREB       ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
-#define 	AT91C_PWMC_PREB_MCK                  ((unsigned int) 0x0 << 24) // (PWMC) 
-// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- 
-#define AT91C_PWMC_CHID0      ((unsigned int) 0x1 <<  0) // (PWMC) Channel ID 0
-#define AT91C_PWMC_CHID1      ((unsigned int) 0x1 <<  1) // (PWMC) Channel ID 1
-#define AT91C_PWMC_CHID2      ((unsigned int) 0x1 <<  2) // (PWMC) Channel ID 2
-#define AT91C_PWMC_CHID3      ((unsigned int) 0x1 <<  3) // (PWMC) Channel ID 3
-// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- 
-// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- 
-// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- 
-// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- 
-// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- 
-// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR USB Device Interface
-// *****************************************************************************
-typedef struct _AT91S_UDP {
-	AT91_REG	 UDP_NUM; 	// Frame Number Register
-	AT91_REG	 UDP_GLBSTATE; 	// Global State Register
-	AT91_REG	 UDP_FADDR; 	// Function Address Register
-	AT91_REG	 Reserved0[1]; 	// 
-	AT91_REG	 UDP_IER; 	// Interrupt Enable Register
-	AT91_REG	 UDP_IDR; 	// Interrupt Disable Register
-	AT91_REG	 UDP_IMR; 	// Interrupt Mask Register
-	AT91_REG	 UDP_ISR; 	// Interrupt Status Register
-	AT91_REG	 UDP_ICR; 	// Interrupt Clear Register
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 UDP_RSTEP; 	// Reset Endpoint Register
-	AT91_REG	 Reserved2[1]; 	// 
-	AT91_REG	 UDP_CSR[6]; 	// Endpoint Control and Status Register
-	AT91_REG	 Reserved3[2]; 	// 
-	AT91_REG	 UDP_FDR[6]; 	// Endpoint FIFO Data Register
-	AT91_REG	 Reserved4[3]; 	// 
-	AT91_REG	 UDP_TXVC; 	// Transceiver Control Register
-} AT91S_UDP, *AT91PS_UDP;
-
-// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
-#define AT91C_UDP_FRM_NUM     ((unsigned int) 0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
-#define AT91C_UDP_FRM_ERR     ((unsigned int) 0x1 << 16) // (UDP) Frame Error
-#define AT91C_UDP_FRM_OK      ((unsigned int) 0x1 << 17) // (UDP) Frame OK
-// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
-#define AT91C_UDP_FADDEN      ((unsigned int) 0x1 <<  0) // (UDP) Function Address Enable
-#define AT91C_UDP_CONFG       ((unsigned int) 0x1 <<  1) // (UDP) Configured
-#define AT91C_UDP_ESR         ((unsigned int) 0x1 <<  2) // (UDP) Enable Send Resume
-#define AT91C_UDP_RSMINPR     ((unsigned int) 0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
-#define AT91C_UDP_RMWUPE      ((unsigned int) 0x1 <<  4) // (UDP) Remote Wake Up Enable
-// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
-#define AT91C_UDP_FADD        ((unsigned int) 0xFF <<  0) // (UDP) Function Address Value
-#define AT91C_UDP_FEN         ((unsigned int) 0x1 <<  8) // (UDP) Function Enable
-// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
-#define AT91C_UDP_EPINT0      ((unsigned int) 0x1 <<  0) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT1      ((unsigned int) 0x1 <<  1) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT2      ((unsigned int) 0x1 <<  2) // (UDP) Endpoint 2 Interrupt
-#define AT91C_UDP_EPINT3      ((unsigned int) 0x1 <<  3) // (UDP) Endpoint 3 Interrupt
-#define AT91C_UDP_EPINT4      ((unsigned int) 0x1 <<  4) // (UDP) Endpoint 4 Interrupt
-#define AT91C_UDP_EPINT5      ((unsigned int) 0x1 <<  5) // (UDP) Endpoint 5 Interrupt
-#define AT91C_UDP_RXSUSP      ((unsigned int) 0x1 <<  8) // (UDP) USB Suspend Interrupt
-#define AT91C_UDP_RXRSM       ((unsigned int) 0x1 <<  9) // (UDP) USB Resume Interrupt
-#define AT91C_UDP_EXTRSM      ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
-#define AT91C_UDP_SOFINT      ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
-#define AT91C_UDP_WAKEUP      ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
-// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
-// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
-// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
-#define AT91C_UDP_ENDBUSRES   ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
-// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
-// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
-#define AT91C_UDP_EP0         ((unsigned int) 0x1 <<  0) // (UDP) Reset Endpoint 0
-#define AT91C_UDP_EP1         ((unsigned int) 0x1 <<  1) // (UDP) Reset Endpoint 1
-#define AT91C_UDP_EP2         ((unsigned int) 0x1 <<  2) // (UDP) Reset Endpoint 2
-#define AT91C_UDP_EP3         ((unsigned int) 0x1 <<  3) // (UDP) Reset Endpoint 3
-#define AT91C_UDP_EP4         ((unsigned int) 0x1 <<  4) // (UDP) Reset Endpoint 4
-#define AT91C_UDP_EP5         ((unsigned int) 0x1 <<  5) // (UDP) Reset Endpoint 5
-// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
-#define AT91C_UDP_TXCOMP      ((unsigned int) 0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
-#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 <<  1) // (UDP) Receive Data Bank 0
-#define AT91C_UDP_RXSETUP     ((unsigned int) 0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
-#define AT91C_UDP_ISOERROR    ((unsigned int) 0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
-#define AT91C_UDP_TXPKTRDY    ((unsigned int) 0x1 <<  4) // (UDP) Transmit Packet Ready
-#define AT91C_UDP_FORCESTALL  ((unsigned int) 0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-#define AT91C_UDP_DIR         ((unsigned int) 0x1 <<  7) // (UDP) Transfer Direction
-#define AT91C_UDP_EPTYPE      ((unsigned int) 0x7 <<  8) // (UDP) Endpoint type
-#define 	AT91C_UDP_EPTYPE_CTRL                 ((unsigned int) 0x0 <<  8) // (UDP) Control
-#define 	AT91C_UDP_EPTYPE_ISO_OUT              ((unsigned int) 0x1 <<  8) // (UDP) Isochronous OUT
-#define 	AT91C_UDP_EPTYPE_BULK_OUT             ((unsigned int) 0x2 <<  8) // (UDP) Bulk OUT
-#define 	AT91C_UDP_EPTYPE_INT_OUT              ((unsigned int) 0x3 <<  8) // (UDP) Interrupt OUT
-#define 	AT91C_UDP_EPTYPE_ISO_IN               ((unsigned int) 0x5 <<  8) // (UDP) Isochronous IN
-#define 	AT91C_UDP_EPTYPE_BULK_IN              ((unsigned int) 0x6 <<  8) // (UDP) Bulk IN
-#define 	AT91C_UDP_EPTYPE_INT_IN               ((unsigned int) 0x7 <<  8) // (UDP) Interrupt IN
-#define AT91C_UDP_DTGLE       ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
-#define AT91C_UDP_EPEDS       ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
-#define AT91C_UDP_RXBYTECNT   ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
-// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- 
-#define AT91C_UDP_TXVDIS      ((unsigned int) 0x1 <<  8) // (UDP) 
-#define AT91C_UDP_PUON        ((unsigned int) 0x1 <<  9) // (UDP) Pull-up ON
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
-// *****************************************************************************
-typedef struct _AT91S_TC {
-	AT91_REG	 TC_CCR; 	// Channel Control Register
-	AT91_REG	 TC_CMR; 	// Channel Mode Register (Capture Mode / Waveform Mode)
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 TC_CV; 	// Counter Value
-	AT91_REG	 TC_RA; 	// Register A
-	AT91_REG	 TC_RB; 	// Register B
-	AT91_REG	 TC_RC; 	// Register C
-	AT91_REG	 TC_SR; 	// Status Register
-	AT91_REG	 TC_IER; 	// Interrupt Enable Register
-	AT91_REG	 TC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 TC_IMR; 	// Interrupt Mask Register
-} AT91S_TC, *AT91PS_TC;
-
-// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
-#define AT91C_TC_CLKEN        ((unsigned int) 0x1 <<  0) // (TC) Counter Clock Enable Command
-#define AT91C_TC_CLKDIS       ((unsigned int) 0x1 <<  1) // (TC) Counter Clock Disable Command
-#define AT91C_TC_SWTRG        ((unsigned int) 0x1 <<  2) // (TC) Software Trigger Command
-// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
-#define AT91C_TC_CLKS         ((unsigned int) 0x7 <<  0) // (TC) Clock Selection
-#define 	AT91C_TC_CLKS_TIMER_DIV1_CLOCK     ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV2_CLOCK     ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV3_CLOCK     ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV4_CLOCK     ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV5_CLOCK     ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
-#define 	AT91C_TC_CLKS_XC0                  ((unsigned int) 0x5) // (TC) Clock selected: XC0
-#define 	AT91C_TC_CLKS_XC1                  ((unsigned int) 0x6) // (TC) Clock selected: XC1
-#define 	AT91C_TC_CLKS_XC2                  ((unsigned int) 0x7) // (TC) Clock selected: XC2
-#define AT91C_TC_CLKI         ((unsigned int) 0x1 <<  3) // (TC) Clock Invert
-#define AT91C_TC_BURST        ((unsigned int) 0x3 <<  4) // (TC) Burst Signal Selection
-#define 	AT91C_TC_BURST_NONE                 ((unsigned int) 0x0 <<  4) // (TC) The clock is not gated by an external signal
-#define 	AT91C_TC_BURST_XC0                  ((unsigned int) 0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
-#define 	AT91C_TC_BURST_XC1                  ((unsigned int) 0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
-#define 	AT91C_TC_BURST_XC2                  ((unsigned int) 0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
-#define AT91C_TC_CPCSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
-#define AT91C_TC_LDBSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
-#define AT91C_TC_CPCDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
-#define AT91C_TC_LDBDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
-#define AT91C_TC_ETRGEDG      ((unsigned int) 0x3 <<  8) // (TC) External Trigger Edge Selection
-#define 	AT91C_TC_ETRGEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
-#define 	AT91C_TC_ETRGEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
-#define 	AT91C_TC_ETRGEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
-#define 	AT91C_TC_ETRGEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVTEDG      ((unsigned int) 0x3 <<  8) // (TC) External Event Edge Selection
-#define 	AT91C_TC_EEVTEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
-#define 	AT91C_TC_EEVTEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
-#define 	AT91C_TC_EEVTEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
-#define 	AT91C_TC_EEVTEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVT         ((unsigned int) 0x3 << 10) // (TC) External Event  Selection
-#define 	AT91C_TC_EEVT_TIOB                 ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
-#define 	AT91C_TC_EEVT_XC0                  ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
-#define 	AT91C_TC_EEVT_XC1                  ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
-#define 	AT91C_TC_EEVT_XC2                  ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
-#define AT91C_TC_ABETRG       ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
-#define AT91C_TC_ENETRG       ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
-#define AT91C_TC_WAVESEL      ((unsigned int) 0x3 << 13) // (TC) Waveform  Selection
-#define 	AT91C_TC_WAVESEL_UP                   ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UPDOWN               ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UP_AUTO              ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
-#define AT91C_TC_CPCTRG       ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
-#define AT91C_TC_WAVE         ((unsigned int) 0x1 << 15) // (TC) 
-#define AT91C_TC_ACPA         ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
-#define 	AT91C_TC_ACPA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Effect: none
-#define 	AT91C_TC_ACPA_SET                  ((unsigned int) 0x1 << 16) // (TC) Effect: set
-#define 	AT91C_TC_ACPA_CLEAR                ((unsigned int) 0x2 << 16) // (TC) Effect: clear
-#define 	AT91C_TC_ACPA_TOGGLE               ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
-#define AT91C_TC_LDRA         ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
-#define 	AT91C_TC_LDRA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Edge: None
-#define 	AT91C_TC_LDRA_RISING               ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
-#define 	AT91C_TC_LDRA_FALLING              ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
-#define 	AT91C_TC_LDRA_BOTH                 ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_ACPC         ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
-#define 	AT91C_TC_ACPC_NONE                 ((unsigned int) 0x0 << 18) // (TC) Effect: none
-#define 	AT91C_TC_ACPC_SET                  ((unsigned int) 0x1 << 18) // (TC) Effect: set
-#define 	AT91C_TC_ACPC_CLEAR                ((unsigned int) 0x2 << 18) // (TC) Effect: clear
-#define 	AT91C_TC_ACPC_TOGGLE               ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
-#define AT91C_TC_LDRB         ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
-#define 	AT91C_TC_LDRB_NONE                 ((unsigned int) 0x0 << 18) // (TC) Edge: None
-#define 	AT91C_TC_LDRB_RISING               ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
-#define 	AT91C_TC_LDRB_FALLING              ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
-#define 	AT91C_TC_LDRB_BOTH                 ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_AEEVT        ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
-#define 	AT91C_TC_AEEVT_NONE                 ((unsigned int) 0x0 << 20) // (TC) Effect: none
-#define 	AT91C_TC_AEEVT_SET                  ((unsigned int) 0x1 << 20) // (TC) Effect: set
-#define 	AT91C_TC_AEEVT_CLEAR                ((unsigned int) 0x2 << 20) // (TC) Effect: clear
-#define 	AT91C_TC_AEEVT_TOGGLE               ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
-#define AT91C_TC_ASWTRG       ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
-#define 	AT91C_TC_ASWTRG_NONE                 ((unsigned int) 0x0 << 22) // (TC) Effect: none
-#define 	AT91C_TC_ASWTRG_SET                  ((unsigned int) 0x1 << 22) // (TC) Effect: set
-#define 	AT91C_TC_ASWTRG_CLEAR                ((unsigned int) 0x2 << 22) // (TC) Effect: clear
-#define 	AT91C_TC_ASWTRG_TOGGLE               ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
-#define AT91C_TC_BCPB         ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
-#define 	AT91C_TC_BCPB_NONE                 ((unsigned int) 0x0 << 24) // (TC) Effect: none
-#define 	AT91C_TC_BCPB_SET                  ((unsigned int) 0x1 << 24) // (TC) Effect: set
-#define 	AT91C_TC_BCPB_CLEAR                ((unsigned int) 0x2 << 24) // (TC) Effect: clear
-#define 	AT91C_TC_BCPB_TOGGLE               ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
-#define AT91C_TC_BCPC         ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
-#define 	AT91C_TC_BCPC_NONE                 ((unsigned int) 0x0 << 26) // (TC) Effect: none
-#define 	AT91C_TC_BCPC_SET                  ((unsigned int) 0x1 << 26) // (TC) Effect: set
-#define 	AT91C_TC_BCPC_CLEAR                ((unsigned int) 0x2 << 26) // (TC) Effect: clear
-#define 	AT91C_TC_BCPC_TOGGLE               ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
-#define AT91C_TC_BEEVT        ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
-#define 	AT91C_TC_BEEVT_NONE                 ((unsigned int) 0x0 << 28) // (TC) Effect: none
-#define 	AT91C_TC_BEEVT_SET                  ((unsigned int) 0x1 << 28) // (TC) Effect: set
-#define 	AT91C_TC_BEEVT_CLEAR                ((unsigned int) 0x2 << 28) // (TC) Effect: clear
-#define 	AT91C_TC_BEEVT_TOGGLE               ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
-#define AT91C_TC_BSWTRG       ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
-#define 	AT91C_TC_BSWTRG_NONE                 ((unsigned int) 0x0 << 30) // (TC) Effect: none
-#define 	AT91C_TC_BSWTRG_SET                  ((unsigned int) 0x1 << 30) // (TC) Effect: set
-#define 	AT91C_TC_BSWTRG_CLEAR                ((unsigned int) 0x2 << 30) // (TC) Effect: clear
-#define 	AT91C_TC_BSWTRG_TOGGLE               ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
-// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
-#define AT91C_TC_COVFS        ((unsigned int) 0x1 <<  0) // (TC) Counter Overflow
-#define AT91C_TC_LOVRS        ((unsigned int) 0x1 <<  1) // (TC) Load Overrun
-#define AT91C_TC_CPAS         ((unsigned int) 0x1 <<  2) // (TC) RA Compare
-#define AT91C_TC_CPBS         ((unsigned int) 0x1 <<  3) // (TC) RB Compare
-#define AT91C_TC_CPCS         ((unsigned int) 0x1 <<  4) // (TC) RC Compare
-#define AT91C_TC_LDRAS        ((unsigned int) 0x1 <<  5) // (TC) RA Loading
-#define AT91C_TC_LDRBS        ((unsigned int) 0x1 <<  6) // (TC) RB Loading
-#define AT91C_TC_ETRGS        ((unsigned int) 0x1 <<  7) // (TC) External Trigger
-#define AT91C_TC_CLKSTA       ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
-#define AT91C_TC_MTIOA        ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
-#define AT91C_TC_MTIOB        ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
-// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
-// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
-// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
-// *****************************************************************************
-typedef struct _AT91S_TCB {
-	AT91S_TC	 TCB_TC0; 	// TC Channel 0
-	AT91_REG	 Reserved0[4]; 	// 
-	AT91S_TC	 TCB_TC1; 	// TC Channel 1
-	AT91_REG	 Reserved1[4]; 	// 
-	AT91S_TC	 TCB_TC2; 	// TC Channel 2
-	AT91_REG	 Reserved2[4]; 	// 
-	AT91_REG	 TCB_BCR; 	// TC Block Control Register
-	AT91_REG	 TCB_BMR; 	// TC Block Mode Register
-} AT91S_TCB, *AT91PS_TCB;
-
-// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
-#define AT91C_TCB_SYNC        ((unsigned int) 0x1 <<  0) // (TCB) Synchro Command
-// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
-#define AT91C_TCB_TC0XC0S     ((unsigned int) 0x3 <<  0) // (TCB) External Clock Signal 0 Selection
-#define 	AT91C_TCB_TC0XC0S_TCLK0                ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
-#define 	AT91C_TCB_TC0XC0S_NONE                 ((unsigned int) 0x1) // (TCB) None signal connected to XC0
-#define 	AT91C_TCB_TC0XC0S_TIOA1                ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
-#define 	AT91C_TCB_TC0XC0S_TIOA2                ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
-#define AT91C_TCB_TC1XC1S     ((unsigned int) 0x3 <<  2) // (TCB) External Clock Signal 1 Selection
-#define 	AT91C_TCB_TC1XC1S_TCLK1                ((unsigned int) 0x0 <<  2) // (TCB) TCLK1 connected to XC1
-#define 	AT91C_TCB_TC1XC1S_NONE                 ((unsigned int) 0x1 <<  2) // (TCB) None signal connected to XC1
-#define 	AT91C_TCB_TC1XC1S_TIOA0                ((unsigned int) 0x2 <<  2) // (TCB) TIOA0 connected to XC1
-#define 	AT91C_TCB_TC1XC1S_TIOA2                ((unsigned int) 0x3 <<  2) // (TCB) TIOA2 connected to XC1
-#define AT91C_TCB_TC2XC2S     ((unsigned int) 0x3 <<  4) // (TCB) External Clock Signal 2 Selection
-#define 	AT91C_TCB_TC2XC2S_TCLK2                ((unsigned int) 0x0 <<  4) // (TCB) TCLK2 connected to XC2
-#define 	AT91C_TCB_TC2XC2S_NONE                 ((unsigned int) 0x1 <<  4) // (TCB) None signal connected to XC2
-#define 	AT91C_TCB_TC2XC2S_TIOA0                ((unsigned int) 0x2 <<  4) // (TCB) TIOA0 connected to XC2
-#define 	AT91C_TCB_TC2XC2S_TIOA1                ((unsigned int) 0x3 <<  4) // (TCB) TIOA2 connected to XC2
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface
-// *****************************************************************************
-typedef struct _AT91S_CAN_MB {
-	AT91_REG	 CAN_MB_MMR; 	// MailBox Mode Register
-	AT91_REG	 CAN_MB_MAM; 	// MailBox Acceptance Mask Register
-	AT91_REG	 CAN_MB_MID; 	// MailBox ID Register
-	AT91_REG	 CAN_MB_MFID; 	// MailBox Family ID Register
-	AT91_REG	 CAN_MB_MSR; 	// MailBox Status Register
-	AT91_REG	 CAN_MB_MDL; 	// MailBox Data Low Register
-	AT91_REG	 CAN_MB_MDH; 	// MailBox Data High Register
-	AT91_REG	 CAN_MB_MCR; 	// MailBox Control Register
-} AT91S_CAN_MB, *AT91PS_CAN_MB;
-
-// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- 
-#define AT91C_CAN_MTIMEMARK   ((unsigned int) 0xFFFF <<  0) // (CAN_MB) Mailbox Timemark
-#define AT91C_CAN_PRIOR       ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority
-#define AT91C_CAN_MOT         ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type
-#define 	AT91C_CAN_MOT_DIS                  ((unsigned int) 0x0 << 24) // (CAN_MB) 
-#define 	AT91C_CAN_MOT_RX                   ((unsigned int) 0x1 << 24) // (CAN_MB) 
-#define 	AT91C_CAN_MOT_RXOVERWRITE          ((unsigned int) 0x2 << 24) // (CAN_MB) 
-#define 	AT91C_CAN_MOT_TX                   ((unsigned int) 0x3 << 24) // (CAN_MB) 
-#define 	AT91C_CAN_MOT_CONSUMER             ((unsigned int) 0x4 << 24) // (CAN_MB) 
-#define 	AT91C_CAN_MOT_PRODUCER             ((unsigned int) 0x5 << 24) // (CAN_MB) 
-// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- 
-#define AT91C_CAN_MIDvB       ((unsigned int) 0x3FFFF <<  0) // (CAN_MB) Complementary bits for identifier in extended mode
-#define AT91C_CAN_MIDvA       ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
-#define AT91C_CAN_MIDE        ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version
-// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- 
-// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- 
-// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- 
-#define AT91C_CAN_MTIMESTAMP  ((unsigned int) 0xFFFF <<  0) // (CAN_MB) Timer Value
-#define AT91C_CAN_MDLC        ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code
-#define AT91C_CAN_MRTR        ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
-#define AT91C_CAN_MABT        ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort
-#define AT91C_CAN_MRDY        ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready
-#define AT91C_CAN_MMI         ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored
-// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- 
-// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- 
-// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- 
-#define AT91C_CAN_MACR        ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox
-#define AT91C_CAN_MTCR        ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Control Area Network Interface
-// *****************************************************************************
-typedef struct _AT91S_CAN {
-	AT91_REG	 CAN_MR; 	// Mode Register
-	AT91_REG	 CAN_IER; 	// Interrupt Enable Register
-	AT91_REG	 CAN_IDR; 	// Interrupt Disable Register
-	AT91_REG	 CAN_IMR; 	// Interrupt Mask Register
-	AT91_REG	 CAN_SR; 	// Status Register
-	AT91_REG	 CAN_BR; 	// Baudrate Register
-	AT91_REG	 CAN_TIM; 	// Timer Register
-	AT91_REG	 CAN_TIMESTP; 	// Time Stamp Register
-	AT91_REG	 CAN_ECR; 	// Error Counter Register
-	AT91_REG	 CAN_TCR; 	// Transfer Command Register
-	AT91_REG	 CAN_ACR; 	// Abort Command Register
-	AT91_REG	 Reserved0[52]; 	// 
-	AT91_REG	 CAN_VR; 	// Version Register
-	AT91_REG	 Reserved1[64]; 	// 
-	AT91S_CAN_MB	 CAN_MB0; 	// CAN Mailbox 0
-	AT91S_CAN_MB	 CAN_MB1; 	// CAN Mailbox 1
-	AT91S_CAN_MB	 CAN_MB2; 	// CAN Mailbox 2
-	AT91S_CAN_MB	 CAN_MB3; 	// CAN Mailbox 3
-	AT91S_CAN_MB	 CAN_MB4; 	// CAN Mailbox 4
-	AT91S_CAN_MB	 CAN_MB5; 	// CAN Mailbox 5
-	AT91S_CAN_MB	 CAN_MB6; 	// CAN Mailbox 6
-	AT91S_CAN_MB	 CAN_MB7; 	// CAN Mailbox 7
-	AT91S_CAN_MB	 CAN_MB8; 	// CAN Mailbox 8
-	AT91S_CAN_MB	 CAN_MB9; 	// CAN Mailbox 9
-	AT91S_CAN_MB	 CAN_MB10; 	// CAN Mailbox 10
-	AT91S_CAN_MB	 CAN_MB11; 	// CAN Mailbox 11
-	AT91S_CAN_MB	 CAN_MB12; 	// CAN Mailbox 12
-	AT91S_CAN_MB	 CAN_MB13; 	// CAN Mailbox 13
-	AT91S_CAN_MB	 CAN_MB14; 	// CAN Mailbox 14
-	AT91S_CAN_MB	 CAN_MB15; 	// CAN Mailbox 15
-} AT91S_CAN, *AT91PS_CAN;
-
-// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- 
-#define AT91C_CAN_CANEN       ((unsigned int) 0x1 <<  0) // (CAN) CAN Controller Enable
-#define AT91C_CAN_LPM         ((unsigned int) 0x1 <<  1) // (CAN) Disable/Enable Low Power Mode
-#define AT91C_CAN_ABM         ((unsigned int) 0x1 <<  2) // (CAN) Disable/Enable Autobaud/Listen Mode
-#define AT91C_CAN_OVL         ((unsigned int) 0x1 <<  3) // (CAN) Disable/Enable Overload Frame
-#define AT91C_CAN_TEOF        ((unsigned int) 0x1 <<  4) // (CAN) Time Stamp messages at each end of Frame
-#define AT91C_CAN_TTM         ((unsigned int) 0x1 <<  5) // (CAN) Disable/Enable Time Trigger Mode
-#define AT91C_CAN_TIMFRZ      ((unsigned int) 0x1 <<  6) // (CAN) Enable Timer Freeze
-#define AT91C_CAN_DRPT        ((unsigned int) 0x1 <<  7) // (CAN) Disable Repeat
-// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- 
-#define AT91C_CAN_MB0         ((unsigned int) 0x1 <<  0) // (CAN) Mailbox 0 Flag
-#define AT91C_CAN_MB1         ((unsigned int) 0x1 <<  1) // (CAN) Mailbox 1 Flag
-#define AT91C_CAN_MB2         ((unsigned int) 0x1 <<  2) // (CAN) Mailbox 2 Flag
-#define AT91C_CAN_MB3         ((unsigned int) 0x1 <<  3) // (CAN) Mailbox 3 Flag
-#define AT91C_CAN_MB4         ((unsigned int) 0x1 <<  4) // (CAN) Mailbox 4 Flag
-#define AT91C_CAN_MB5         ((unsigned int) 0x1 <<  5) // (CAN) Mailbox 5 Flag
-#define AT91C_CAN_MB6         ((unsigned int) 0x1 <<  6) // (CAN) Mailbox 6 Flag
-#define AT91C_CAN_MB7         ((unsigned int) 0x1 <<  7) // (CAN) Mailbox 7 Flag
-#define AT91C_CAN_MB8         ((unsigned int) 0x1 <<  8) // (CAN) Mailbox 8 Flag
-#define AT91C_CAN_MB9         ((unsigned int) 0x1 <<  9) // (CAN) Mailbox 9 Flag
-#define AT91C_CAN_MB10        ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag
-#define AT91C_CAN_MB11        ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag
-#define AT91C_CAN_MB12        ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag
-#define AT91C_CAN_MB13        ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag
-#define AT91C_CAN_MB14        ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag
-#define AT91C_CAN_MB15        ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag
-#define AT91C_CAN_ERRA        ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag
-#define AT91C_CAN_WARN        ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag
-#define AT91C_CAN_ERRP        ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag
-#define AT91C_CAN_BOFF        ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag
-#define AT91C_CAN_SLEEP       ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag
-#define AT91C_CAN_WAKEUP      ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag
-#define AT91C_CAN_TOVF        ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag
-#define AT91C_CAN_TSTP        ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag
-#define AT91C_CAN_CERR        ((unsigned int) 0x1 << 24) // (CAN) CRC Error
-#define AT91C_CAN_SERR        ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error
-#define AT91C_CAN_AERR        ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error
-#define AT91C_CAN_FERR        ((unsigned int) 0x1 << 27) // (CAN) Form Error
-#define AT91C_CAN_BERR        ((unsigned int) 0x1 << 28) // (CAN) Bit Error
-// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- 
-// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- 
-// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- 
-#define AT91C_CAN_RBSY        ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy
-#define AT91C_CAN_TBSY        ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy
-#define AT91C_CAN_OVLY        ((unsigned int) 0x1 << 31) // (CAN) Overload Busy
-// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- 
-#define AT91C_CAN_PHASE2      ((unsigned int) 0x7 <<  0) // (CAN) Phase 2 segment
-#define AT91C_CAN_PHASE1      ((unsigned int) 0x7 <<  4) // (CAN) Phase 1 segment
-#define AT91C_CAN_PROPAG      ((unsigned int) 0x7 <<  8) // (CAN) Programmation time segment
-#define AT91C_CAN_SYNC        ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment
-#define AT91C_CAN_BRP         ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler
-#define AT91C_CAN_SMP         ((unsigned int) 0x1 << 24) // (CAN) Sampling mode
-// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- 
-#define AT91C_CAN_TIMER       ((unsigned int) 0xFFFF <<  0) // (CAN) Timer field
-// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- 
-// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- 
-#define AT91C_CAN_REC         ((unsigned int) 0xFF <<  0) // (CAN) Receive Error Counter
-#define AT91C_CAN_TEC         ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter
-// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- 
-#define AT91C_CAN_TIMRST      ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field
-// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
-// *****************************************************************************
-typedef struct _AT91S_EMAC {
-	AT91_REG	 EMAC_NCR; 	// Network Control Register
-	AT91_REG	 EMAC_NCFGR; 	// Network Configuration Register
-	AT91_REG	 EMAC_NSR; 	// Network Status Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 EMAC_TSR; 	// Transmit Status Register
-	AT91_REG	 EMAC_RBQP; 	// Receive Buffer Queue Pointer
-	AT91_REG	 EMAC_TBQP; 	// Transmit Buffer Queue Pointer
-	AT91_REG	 EMAC_RSR; 	// Receive Status Register
-	AT91_REG	 EMAC_ISR; 	// Interrupt Status Register
-	AT91_REG	 EMAC_IER; 	// Interrupt Enable Register
-	AT91_REG	 EMAC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 EMAC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 EMAC_MAN; 	// PHY Maintenance Register
-	AT91_REG	 EMAC_PTR; 	// Pause Time Register
-	AT91_REG	 EMAC_PFR; 	// Pause Frames received Register
-	AT91_REG	 EMAC_FTO; 	// Frames Transmitted OK Register
-	AT91_REG	 EMAC_SCF; 	// Single Collision Frame Register
-	AT91_REG	 EMAC_MCF; 	// Multiple Collision Frame Register
-	AT91_REG	 EMAC_FRO; 	// Frames Received OK Register
-	AT91_REG	 EMAC_FCSE; 	// Frame Check Sequence Error Register
-	AT91_REG	 EMAC_ALE; 	// Alignment Error Register
-	AT91_REG	 EMAC_DTF; 	// Deferred Transmission Frame Register
-	AT91_REG	 EMAC_LCOL; 	// Late Collision Register
-	AT91_REG	 EMAC_ECOL; 	// Excessive Collision Register
-	AT91_REG	 EMAC_TUND; 	// Transmit Underrun Error Register
-	AT91_REG	 EMAC_CSE; 	// Carrier Sense Error Register
-	AT91_REG	 EMAC_RRE; 	// Receive Ressource Error Register
-	AT91_REG	 EMAC_ROV; 	// Receive Overrun Errors Register
-	AT91_REG	 EMAC_RSE; 	// Receive Symbol Errors Register
-	AT91_REG	 EMAC_ELE; 	// Excessive Length Errors Register
-	AT91_REG	 EMAC_RJA; 	// Receive Jabbers Register
-	AT91_REG	 EMAC_USF; 	// Undersize Frames Register
-	AT91_REG	 EMAC_STE; 	// SQE Test Error Register
-	AT91_REG	 EMAC_RLE; 	// Receive Length Field Mismatch Register
-	AT91_REG	 EMAC_TPF; 	// Transmitted Pause Frames Register
-	AT91_REG	 EMAC_HRB; 	// Hash Address Bottom[31:0]
-	AT91_REG	 EMAC_HRT; 	// Hash Address Top[63:32]
-	AT91_REG	 EMAC_SA1L; 	// Specific Address 1 Bottom, First 4 bytes
-	AT91_REG	 EMAC_SA1H; 	// Specific Address 1 Top, Last 2 bytes
-	AT91_REG	 EMAC_SA2L; 	// Specific Address 2 Bottom, First 4 bytes
-	AT91_REG	 EMAC_SA2H; 	// Specific Address 2 Top, Last 2 bytes
-	AT91_REG	 EMAC_SA3L; 	// Specific Address 3 Bottom, First 4 bytes
-	AT91_REG	 EMAC_SA3H; 	// Specific Address 3 Top, Last 2 bytes
-	AT91_REG	 EMAC_SA4L; 	// Specific Address 4 Bottom, First 4 bytes
-	AT91_REG	 EMAC_SA4H; 	// Specific Address 4 Top, Last 2 bytes
-	AT91_REG	 EMAC_TID; 	// Type ID Checking Register
-	AT91_REG	 EMAC_TPQ; 	// Transmit Pause Quantum Register
-	AT91_REG	 EMAC_USRIO; 	// USER Input/Output Register
-	AT91_REG	 EMAC_WOL; 	// Wake On LAN Register
-	AT91_REG	 Reserved1[13]; 	// 
-	AT91_REG	 EMAC_REV; 	// Revision Register
-} AT91S_EMAC, *AT91PS_EMAC;
-
-// -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- 
-#define AT91C_EMAC_LB         ((unsigned int) 0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
-#define AT91C_EMAC_LLB        ((unsigned int) 0x1 <<  1) // (EMAC) Loopback local. 
-#define AT91C_EMAC_RE         ((unsigned int) 0x1 <<  2) // (EMAC) Receive enable. 
-#define AT91C_EMAC_TE         ((unsigned int) 0x1 <<  3) // (EMAC) Transmit enable. 
-#define AT91C_EMAC_MPE        ((unsigned int) 0x1 <<  4) // (EMAC) Management port enable. 
-#define AT91C_EMAC_CLRSTAT    ((unsigned int) 0x1 <<  5) // (EMAC) Clear statistics registers. 
-#define AT91C_EMAC_INCSTAT    ((unsigned int) 0x1 <<  6) // (EMAC) Increment statistics registers. 
-#define AT91C_EMAC_WESTAT     ((unsigned int) 0x1 <<  7) // (EMAC) Write enable for statistics registers. 
-#define AT91C_EMAC_BP         ((unsigned int) 0x1 <<  8) // (EMAC) Back pressure. 
-#define AT91C_EMAC_TSTART     ((unsigned int) 0x1 <<  9) // (EMAC) Start Transmission. 
-#define AT91C_EMAC_THALT      ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. 
-#define AT91C_EMAC_TPFR       ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame 
-#define AT91C_EMAC_TZQ        ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame
-// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- 
-#define AT91C_EMAC_SPD        ((unsigned int) 0x1 <<  0) // (EMAC) Speed. 
-#define AT91C_EMAC_FD         ((unsigned int) 0x1 <<  1) // (EMAC) Full duplex. 
-#define AT91C_EMAC_JFRAME     ((unsigned int) 0x1 <<  3) // (EMAC) Jumbo Frames. 
-#define AT91C_EMAC_CAF        ((unsigned int) 0x1 <<  4) // (EMAC) Copy all frames. 
-#define AT91C_EMAC_NBC        ((unsigned int) 0x1 <<  5) // (EMAC) No broadcast. 
-#define AT91C_EMAC_MTI        ((unsigned int) 0x1 <<  6) // (EMAC) Multicast hash event enable
-#define AT91C_EMAC_UNI        ((unsigned int) 0x1 <<  7) // (EMAC) Unicast hash enable. 
-#define AT91C_EMAC_BIG        ((unsigned int) 0x1 <<  8) // (EMAC) Receive 1522 bytes. 
-#define AT91C_EMAC_EAE        ((unsigned int) 0x1 <<  9) // (EMAC) External address match enable. 
-#define AT91C_EMAC_CLK        ((unsigned int) 0x3 << 10) // (EMAC) 
-#define 	AT91C_EMAC_CLK_HCLK_8               ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8
-#define 	AT91C_EMAC_CLK_HCLK_16              ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16
-#define 	AT91C_EMAC_CLK_HCLK_32              ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32
-#define 	AT91C_EMAC_CLK_HCLK_64              ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64
-#define AT91C_EMAC_RTY        ((unsigned int) 0x1 << 12) // (EMAC) 
-#define AT91C_EMAC_PAE        ((unsigned int) 0x1 << 13) // (EMAC) 
-#define AT91C_EMAC_RBOF       ((unsigned int) 0x3 << 14) // (EMAC) 
-#define 	AT91C_EMAC_RBOF_OFFSET_0             ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer
-#define 	AT91C_EMAC_RBOF_OFFSET_1             ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer
-#define 	AT91C_EMAC_RBOF_OFFSET_2             ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
-#define 	AT91C_EMAC_RBOF_OFFSET_3             ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
-#define AT91C_EMAC_RLCE       ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable
-#define AT91C_EMAC_DRFCS      ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS
-#define AT91C_EMAC_EFRHD      ((unsigned int) 0x1 << 18) // (EMAC) 
-#define AT91C_EMAC_IRXFCS     ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS
-// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- 
-#define AT91C_EMAC_LINKR      ((unsigned int) 0x1 <<  0) // (EMAC) 
-#define AT91C_EMAC_MDIO       ((unsigned int) 0x1 <<  1) // (EMAC) 
-#define AT91C_EMAC_IDLE       ((unsigned int) 0x1 <<  2) // (EMAC) 
-// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- 
-#define AT91C_EMAC_UBR        ((unsigned int) 0x1 <<  0) // (EMAC) 
-#define AT91C_EMAC_COL        ((unsigned int) 0x1 <<  1) // (EMAC) 
-#define AT91C_EMAC_RLES       ((unsigned int) 0x1 <<  2) // (EMAC) 
-#define AT91C_EMAC_TGO        ((unsigned int) 0x1 <<  3) // (EMAC) Transmit Go
-#define AT91C_EMAC_BEX        ((unsigned int) 0x1 <<  4) // (EMAC) Buffers exhausted mid frame
-#define AT91C_EMAC_COMP       ((unsigned int) 0x1 <<  5) // (EMAC) 
-#define AT91C_EMAC_UND        ((unsigned int) 0x1 <<  6) // (EMAC) 
-// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- 
-#define AT91C_EMAC_BNA        ((unsigned int) 0x1 <<  0) // (EMAC) 
-#define AT91C_EMAC_REC        ((unsigned int) 0x1 <<  1) // (EMAC) 
-#define AT91C_EMAC_OVR        ((unsigned int) 0x1 <<  2) // (EMAC) 
-// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- 
-#define AT91C_EMAC_MFD        ((unsigned int) 0x1 <<  0) // (EMAC) 
-#define AT91C_EMAC_RCOMP      ((unsigned int) 0x1 <<  1) // (EMAC) 
-#define AT91C_EMAC_RXUBR      ((unsigned int) 0x1 <<  2) // (EMAC) 
-#define AT91C_EMAC_TXUBR      ((unsigned int) 0x1 <<  3) // (EMAC) 
-#define AT91C_EMAC_TUNDR      ((unsigned int) 0x1 <<  4) // (EMAC) 
-#define AT91C_EMAC_RLEX       ((unsigned int) 0x1 <<  5) // (EMAC) 
-#define AT91C_EMAC_TXERR      ((unsigned int) 0x1 <<  6) // (EMAC) 
-#define AT91C_EMAC_TCOMP      ((unsigned int) 0x1 <<  7) // (EMAC) 
-#define AT91C_EMAC_LINK       ((unsigned int) 0x1 <<  9) // (EMAC) 
-#define AT91C_EMAC_ROVR       ((unsigned int) 0x1 << 10) // (EMAC) 
-#define AT91C_EMAC_HRESP      ((unsigned int) 0x1 << 11) // (EMAC) 
-#define AT91C_EMAC_PFRE       ((unsigned int) 0x1 << 12) // (EMAC) 
-#define AT91C_EMAC_PTZ        ((unsigned int) 0x1 << 13) // (EMAC) 
-// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- 
-// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- 
-// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- 
-// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- 
-#define AT91C_EMAC_DATA       ((unsigned int) 0xFFFF <<  0) // (EMAC) 
-#define AT91C_EMAC_CODE       ((unsigned int) 0x3 << 16) // (EMAC) 
-#define AT91C_EMAC_REGA       ((unsigned int) 0x1F << 18) // (EMAC) 
-#define AT91C_EMAC_PHYA       ((unsigned int) 0x1F << 23) // (EMAC) 
-#define AT91C_EMAC_RW         ((unsigned int) 0x3 << 28) // (EMAC) 
-#define AT91C_EMAC_SOF        ((unsigned int) 0x3 << 30) // (EMAC) 
-// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- 
-#define AT91C_EMAC_RMII       ((unsigned int) 0x1 <<  0) // (EMAC) Reduce MII
-// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- 
-#define AT91C_EMAC_IP         ((unsigned int) 0xFFFF <<  0) // (EMAC) ARP request IP address
-#define AT91C_EMAC_MAG        ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable
-#define AT91C_EMAC_ARP        ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable
-#define AT91C_EMAC_SA1        ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable
-// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- 
-#define AT91C_EMAC_REVREF     ((unsigned int) 0xFFFF <<  0) // (EMAC) 
-#define AT91C_EMAC_PARTREF    ((unsigned int) 0xFFFF << 16) // (EMAC) 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
-// *****************************************************************************
-typedef struct _AT91S_ADC {
-	AT91_REG	 ADC_CR; 	// ADC Control Register
-	AT91_REG	 ADC_MR; 	// ADC Mode Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 ADC_CHER; 	// ADC Channel Enable Register
-	AT91_REG	 ADC_CHDR; 	// ADC Channel Disable Register
-	AT91_REG	 ADC_CHSR; 	// ADC Channel Status Register
-	AT91_REG	 ADC_SR; 	// ADC Status Register
-	AT91_REG	 ADC_LCDR; 	// ADC Last Converted Data Register
-	AT91_REG	 ADC_IER; 	// ADC Interrupt Enable Register
-	AT91_REG	 ADC_IDR; 	// ADC Interrupt Disable Register
-	AT91_REG	 ADC_IMR; 	// ADC Interrupt Mask Register
-	AT91_REG	 ADC_CDR0; 	// ADC Channel Data Register 0
-	AT91_REG	 ADC_CDR1; 	// ADC Channel Data Register 1
-	AT91_REG	 ADC_CDR2; 	// ADC Channel Data Register 2
-	AT91_REG	 ADC_CDR3; 	// ADC Channel Data Register 3
-	AT91_REG	 ADC_CDR4; 	// ADC Channel Data Register 4
-	AT91_REG	 ADC_CDR5; 	// ADC Channel Data Register 5
-	AT91_REG	 ADC_CDR6; 	// ADC Channel Data Register 6
-	AT91_REG	 ADC_CDR7; 	// ADC Channel Data Register 7
-	AT91_REG	 Reserved1[44]; 	// 
-	AT91_REG	 ADC_RPR; 	// Receive Pointer Register
-	AT91_REG	 ADC_RCR; 	// Receive Counter Register
-	AT91_REG	 ADC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 ADC_TCR; 	// Transmit Counter Register
-	AT91_REG	 ADC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 ADC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 ADC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 ADC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 ADC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 ADC_PTSR; 	// PDC Transfer Status Register
-} AT91S_ADC, *AT91PS_ADC;
-
-// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
-#define AT91C_ADC_SWRST       ((unsigned int) 0x1 <<  0) // (ADC) Software Reset
-#define AT91C_ADC_START       ((unsigned int) 0x1 <<  1) // (ADC) Start Conversion
-// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 
-#define AT91C_ADC_TRGEN       ((unsigned int) 0x1 <<  0) // (ADC) Trigger Enable
-#define 	AT91C_ADC_TRGEN_DIS                  ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
-#define 	AT91C_ADC_TRGEN_EN                   ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
-#define AT91C_ADC_TRGSEL      ((unsigned int) 0x7 <<  1) // (ADC) Trigger Selection
-#define 	AT91C_ADC_TRGSEL_TIOA0                ((unsigned int) 0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
-#define 	AT91C_ADC_TRGSEL_TIOA1                ((unsigned int) 0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
-#define 	AT91C_ADC_TRGSEL_TIOA2                ((unsigned int) 0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
-#define 	AT91C_ADC_TRGSEL_TIOA3                ((unsigned int) 0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
-#define 	AT91C_ADC_TRGSEL_TIOA4                ((unsigned int) 0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
-#define 	AT91C_ADC_TRGSEL_TIOA5                ((unsigned int) 0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
-#define 	AT91C_ADC_TRGSEL_EXT                  ((unsigned int) 0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
-#define AT91C_ADC_LOWRES      ((unsigned int) 0x1 <<  4) // (ADC) Resolution.
-#define 	AT91C_ADC_LOWRES_10_BIT               ((unsigned int) 0x0 <<  4) // (ADC) 10-bit resolution
-#define 	AT91C_ADC_LOWRES_8_BIT                ((unsigned int) 0x1 <<  4) // (ADC) 8-bit resolution
-#define AT91C_ADC_SLEEP       ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
-#define 	AT91C_ADC_SLEEP_NORMAL_MODE          ((unsigned int) 0x0 <<  5) // (ADC) Normal Mode
-#define 	AT91C_ADC_SLEEP_MODE                 ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
-#define AT91C_ADC_PRESCAL     ((unsigned int) 0x3F <<  8) // (ADC) Prescaler rate selection
-#define AT91C_ADC_STARTUP     ((unsigned int) 0x1F << 16) // (ADC) Startup Time
-#define AT91C_ADC_SHTIM       ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
-// -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 
-#define AT91C_ADC_CH0         ((unsigned int) 0x1 <<  0) // (ADC) Channel 0
-#define AT91C_ADC_CH1         ((unsigned int) 0x1 <<  1) // (ADC) Channel 1
-#define AT91C_ADC_CH2         ((unsigned int) 0x1 <<  2) // (ADC) Channel 2
-#define AT91C_ADC_CH3         ((unsigned int) 0x1 <<  3) // (ADC) Channel 3
-#define AT91C_ADC_CH4         ((unsigned int) 0x1 <<  4) // (ADC) Channel 4
-#define AT91C_ADC_CH5         ((unsigned int) 0x1 <<  5) // (ADC) Channel 5
-#define AT91C_ADC_CH6         ((unsigned int) 0x1 <<  6) // (ADC) Channel 6
-#define AT91C_ADC_CH7         ((unsigned int) 0x1 <<  7) // (ADC) Channel 7
-// -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 
-// -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 
-// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 
-#define AT91C_ADC_EOC0        ((unsigned int) 0x1 <<  0) // (ADC) End of Conversion
-#define AT91C_ADC_EOC1        ((unsigned int) 0x1 <<  1) // (ADC) End of Conversion
-#define AT91C_ADC_EOC2        ((unsigned int) 0x1 <<  2) // (ADC) End of Conversion
-#define AT91C_ADC_EOC3        ((unsigned int) 0x1 <<  3) // (ADC) End of Conversion
-#define AT91C_ADC_EOC4        ((unsigned int) 0x1 <<  4) // (ADC) End of Conversion
-#define AT91C_ADC_EOC5        ((unsigned int) 0x1 <<  5) // (ADC) End of Conversion
-#define AT91C_ADC_EOC6        ((unsigned int) 0x1 <<  6) // (ADC) End of Conversion
-#define AT91C_ADC_EOC7        ((unsigned int) 0x1 <<  7) // (ADC) End of Conversion
-#define AT91C_ADC_OVRE0       ((unsigned int) 0x1 <<  8) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE1       ((unsigned int) 0x1 <<  9) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE2       ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE3       ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE4       ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE5       ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE6       ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE7       ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
-#define AT91C_ADC_DRDY        ((unsigned int) 0x1 << 16) // (ADC) Data Ready
-#define AT91C_ADC_GOVRE       ((unsigned int) 0x1 << 17) // (ADC) General Overrun
-#define AT91C_ADC_ENDRX       ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
-#define AT91C_ADC_RXBUFF      ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
-// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 
-#define AT91C_ADC_LDATA       ((unsigned int) 0x3FF <<  0) // (ADC) Last Data Converted
-// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 
-// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 
-// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 
-// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 
-#define AT91C_ADC_DATA        ((unsigned int) 0x3FF <<  0) // (ADC) Converted Data
-// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 
-// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 
-// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 
-// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 
-// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 
-// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 
-// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard
-// *****************************************************************************
-typedef struct _AT91S_AES {
-	AT91_REG	 AES_CR; 	// Control Register
-	AT91_REG	 AES_MR; 	// Mode Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 AES_IER; 	// Interrupt Enable Register
-	AT91_REG	 AES_IDR; 	// Interrupt Disable Register
-	AT91_REG	 AES_IMR; 	// Interrupt Mask Register
-	AT91_REG	 AES_ISR; 	// Interrupt Status Register
-	AT91_REG	 AES_KEYWxR[4]; 	// Key Word x Register
-	AT91_REG	 Reserved1[4]; 	// 
-	AT91_REG	 AES_IDATAxR[4]; 	// Input Data x Register
-	AT91_REG	 AES_ODATAxR[4]; 	// Output Data x Register
-	AT91_REG	 AES_IVxR[4]; 	// Initialization Vector x Register
-	AT91_REG	 Reserved2[35]; 	// 
-	AT91_REG	 AES_VR; 	// AES Version Register
-	AT91_REG	 AES_RPR; 	// Receive Pointer Register
-	AT91_REG	 AES_RCR; 	// Receive Counter Register
-	AT91_REG	 AES_TPR; 	// Transmit Pointer Register
-	AT91_REG	 AES_TCR; 	// Transmit Counter Register
-	AT91_REG	 AES_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 AES_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 AES_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 AES_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 AES_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 AES_PTSR; 	// PDC Transfer Status Register
-} AT91S_AES, *AT91PS_AES;
-
-// -------- AES_CR : (AES Offset: 0x0) Control Register -------- 
-#define AT91C_AES_START       ((unsigned int) 0x1 <<  0) // (AES) Starts Processing
-#define AT91C_AES_SWRST       ((unsigned int) 0x1 <<  8) // (AES) Software Reset
-#define AT91C_AES_LOADSEED    ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading
-// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- 
-#define AT91C_AES_CIPHER      ((unsigned int) 0x1 <<  0) // (AES) Processing Mode
-#define AT91C_AES_PROCDLY     ((unsigned int) 0xF <<  4) // (AES) Processing Delay
-#define AT91C_AES_SMOD        ((unsigned int) 0x3 <<  8) // (AES) Start Mode
-#define 	AT91C_AES_SMOD_MANUAL               ((unsigned int) 0x0 <<  8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
-#define 	AT91C_AES_SMOD_AUTO                 ((unsigned int) 0x1 <<  8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
-#define 	AT91C_AES_SMOD_PDC                  ((unsigned int) 0x2 <<  8) // (AES) PDC Mode (cf datasheet).
-#define AT91C_AES_OPMOD       ((unsigned int) 0x7 << 12) // (AES) Operation Mode
-#define 	AT91C_AES_OPMOD_ECB                  ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode.
-#define 	AT91C_AES_OPMOD_CBC                  ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
-#define 	AT91C_AES_OPMOD_OFB                  ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode.
-#define 	AT91C_AES_OPMOD_CFB                  ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode.
-#define 	AT91C_AES_OPMOD_CTR                  ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode.
-#define AT91C_AES_LOD         ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode
-#define AT91C_AES_CFBS        ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size
-#define 	AT91C_AES_CFBS_128_BIT              ((unsigned int) 0x0 << 16) // (AES) 128-bit.
-#define 	AT91C_AES_CFBS_64_BIT               ((unsigned int) 0x1 << 16) // (AES) 64-bit.
-#define 	AT91C_AES_CFBS_32_BIT               ((unsigned int) 0x2 << 16) // (AES) 32-bit.
-#define 	AT91C_AES_CFBS_16_BIT               ((unsigned int) 0x3 << 16) // (AES) 16-bit.
-#define 	AT91C_AES_CFBS_8_BIT                ((unsigned int) 0x4 << 16) // (AES) 8-bit.
-#define AT91C_AES_CKEY        ((unsigned int) 0xF << 20) // (AES) Countermeasure Key
-#define AT91C_AES_CTYPE       ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type
-#define 	AT91C_AES_CTYPE_TYPE1_EN             ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled.
-#define 	AT91C_AES_CTYPE_TYPE2_EN             ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled.
-#define 	AT91C_AES_CTYPE_TYPE3_EN             ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled.
-#define 	AT91C_AES_CTYPE_TYPE4_EN             ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled.
-#define 	AT91C_AES_CTYPE_TYPE5_EN             ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled.
-// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- 
-#define AT91C_AES_DATRDY      ((unsigned int) 0x1 <<  0) // (AES) DATRDY
-#define AT91C_AES_ENDRX       ((unsigned int) 0x1 <<  1) // (AES) PDC Read Buffer End
-#define AT91C_AES_ENDTX       ((unsigned int) 0x1 <<  2) // (AES) PDC Write Buffer End
-#define AT91C_AES_RXBUFF      ((unsigned int) 0x1 <<  3) // (AES) PDC Read Buffer Full
-#define AT91C_AES_TXBUFE      ((unsigned int) 0x1 <<  4) // (AES) PDC Write Buffer Empty
-#define AT91C_AES_URAD        ((unsigned int) 0x1 <<  8) // (AES) Unspecified Register Access Detection
-// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- 
-// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- 
-// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- 
-#define AT91C_AES_URAT        ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status
-#define 	AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
-#define 	AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing.
-#define 	AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing.
-#define 	AT91C_AES_URAT_OUT_DAT_READ_SUBKEY  ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation.
-#define 	AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation.
-#define 	AT91C_AES_URAT_WO_REG_READ          ((unsigned int) 0x5 << 12) // (AES) Write-only register read access.
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard
-// *****************************************************************************
-typedef struct _AT91S_TDES {
-	AT91_REG	 TDES_CR; 	// Control Register
-	AT91_REG	 TDES_MR; 	// Mode Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 TDES_IER; 	// Interrupt Enable Register
-	AT91_REG	 TDES_IDR; 	// Interrupt Disable Register
-	AT91_REG	 TDES_IMR; 	// Interrupt Mask Register
-	AT91_REG	 TDES_ISR; 	// Interrupt Status Register
-	AT91_REG	 TDES_KEY1WxR[2]; 	// Key 1 Word x Register
-	AT91_REG	 TDES_KEY2WxR[2]; 	// Key 2 Word x Register
-	AT91_REG	 TDES_KEY3WxR[2]; 	// Key 3 Word x Register
-	AT91_REG	 Reserved1[2]; 	// 
-	AT91_REG	 TDES_IDATAxR[2]; 	// Input Data x Register
-	AT91_REG	 Reserved2[2]; 	// 
-	AT91_REG	 TDES_ODATAxR[2]; 	// Output Data x Register
-	AT91_REG	 Reserved3[2]; 	// 
-	AT91_REG	 TDES_IVxR[2]; 	// Initialization Vector x Register
-	AT91_REG	 Reserved4[37]; 	// 
-	AT91_REG	 TDES_VR; 	// TDES Version Register
-	AT91_REG	 TDES_RPR; 	// Receive Pointer Register
-	AT91_REG	 TDES_RCR; 	// Receive Counter Register
-	AT91_REG	 TDES_TPR; 	// Transmit Pointer Register
-	AT91_REG	 TDES_TCR; 	// Transmit Counter Register
-	AT91_REG	 TDES_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 TDES_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 TDES_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 TDES_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 TDES_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 TDES_PTSR; 	// PDC Transfer Status Register
-} AT91S_TDES, *AT91PS_TDES;
-
-// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- 
-#define AT91C_TDES_START      ((unsigned int) 0x1 <<  0) // (TDES) Starts Processing
-#define AT91C_TDES_SWRST      ((unsigned int) 0x1 <<  8) // (TDES) Software Reset
-// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- 
-#define AT91C_TDES_CIPHER     ((unsigned int) 0x1 <<  0) // (TDES) Processing Mode
-#define AT91C_TDES_TDESMOD    ((unsigned int) 0x1 <<  1) // (TDES) Single or Triple DES Mode
-#define AT91C_TDES_KEYMOD     ((unsigned int) 0x1 <<  4) // (TDES) Key Mode
-#define AT91C_TDES_SMOD       ((unsigned int) 0x3 <<  8) // (TDES) Start Mode
-#define 	AT91C_TDES_SMOD_MANUAL               ((unsigned int) 0x0 <<  8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
-#define 	AT91C_TDES_SMOD_AUTO                 ((unsigned int) 0x1 <<  8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
-#define 	AT91C_TDES_SMOD_PDC                  ((unsigned int) 0x2 <<  8) // (TDES) PDC Mode (cf datasheet).
-#define AT91C_TDES_OPMOD      ((unsigned int) 0x3 << 12) // (TDES) Operation Mode
-#define 	AT91C_TDES_OPMOD_ECB                  ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
-#define 	AT91C_TDES_OPMOD_CBC                  ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
-#define 	AT91C_TDES_OPMOD_OFB                  ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode.
-#define 	AT91C_TDES_OPMOD_CFB                  ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode.
-#define AT91C_TDES_LOD        ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode
-#define AT91C_TDES_CFBS       ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size
-#define 	AT91C_TDES_CFBS_64_BIT               ((unsigned int) 0x0 << 16) // (TDES) 64-bit.
-#define 	AT91C_TDES_CFBS_32_BIT               ((unsigned int) 0x1 << 16) // (TDES) 32-bit.
-#define 	AT91C_TDES_CFBS_16_BIT               ((unsigned int) 0x2 << 16) // (TDES) 16-bit.
-#define 	AT91C_TDES_CFBS_8_BIT                ((unsigned int) 0x3 << 16) // (TDES) 8-bit.
-// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- 
-#define AT91C_TDES_DATRDY     ((unsigned int) 0x1 <<  0) // (TDES) DATRDY
-#define AT91C_TDES_ENDRX      ((unsigned int) 0x1 <<  1) // (TDES) PDC Read Buffer End
-#define AT91C_TDES_ENDTX      ((unsigned int) 0x1 <<  2) // (TDES) PDC Write Buffer End
-#define AT91C_TDES_RXBUFF     ((unsigned int) 0x1 <<  3) // (TDES) PDC Read Buffer Full
-#define AT91C_TDES_TXBUFE     ((unsigned int) 0x1 <<  4) // (TDES) PDC Write Buffer Empty
-#define AT91C_TDES_URAD       ((unsigned int) 0x1 <<  8) // (TDES) Unspecified Register Access Detection
-// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- 
-// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- 
-// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- 
-#define AT91C_TDES_URAT       ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status
-#define 	AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
-#define 	AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing.
-#define 	AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing.
-#define 	AT91C_TDES_URAT_WO_REG_READ          ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access.
-
-// *****************************************************************************
-//               REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
-// *****************************************************************************
-// ========== Register definition for SYS peripheral ========== 
-// ========== Register definition for AIC peripheral ========== 
-#define AT91C_AIC_IVR   ((AT91_REG *) 	0xFFFFF100) // (AIC) IRQ Vector Register
-#define AT91C_AIC_SMR   ((AT91_REG *) 	0xFFFFF000) // (AIC) Source Mode Register
-#define AT91C_AIC_FVR   ((AT91_REG *) 	0xFFFFF104) // (AIC) FIQ Vector Register
-#define AT91C_AIC_DCR   ((AT91_REG *) 	0xFFFFF138) // (AIC) Debug Control Register (Protect)
-#define AT91C_AIC_EOICR ((AT91_REG *) 	0xFFFFF130) // (AIC) End of Interrupt Command Register
-#define AT91C_AIC_SVR   ((AT91_REG *) 	0xFFFFF080) // (AIC) Source Vector Register
-#define AT91C_AIC_FFSR  ((AT91_REG *) 	0xFFFFF148) // (AIC) Fast Forcing Status Register
-#define AT91C_AIC_ICCR  ((AT91_REG *) 	0xFFFFF128) // (AIC) Interrupt Clear Command Register
-#define AT91C_AIC_ISR   ((AT91_REG *) 	0xFFFFF108) // (AIC) Interrupt Status Register
-#define AT91C_AIC_IMR   ((AT91_REG *) 	0xFFFFF110) // (AIC) Interrupt Mask Register
-#define AT91C_AIC_IPR   ((AT91_REG *) 	0xFFFFF10C) // (AIC) Interrupt Pending Register
-#define AT91C_AIC_FFER  ((AT91_REG *) 	0xFFFFF140) // (AIC) Fast Forcing Enable Register
-#define AT91C_AIC_IECR  ((AT91_REG *) 	0xFFFFF120) // (AIC) Interrupt Enable Command Register
-#define AT91C_AIC_ISCR  ((AT91_REG *) 	0xFFFFF12C) // (AIC) Interrupt Set Command Register
-#define AT91C_AIC_FFDR  ((AT91_REG *) 	0xFFFFF144) // (AIC) Fast Forcing Disable Register
-#define AT91C_AIC_CISR  ((AT91_REG *) 	0xFFFFF114) // (AIC) Core Interrupt Status Register
-#define AT91C_AIC_IDCR  ((AT91_REG *) 	0xFFFFF124) // (AIC) Interrupt Disable Command Register
-#define AT91C_AIC_SPU   ((AT91_REG *) 	0xFFFFF134) // (AIC) Spurious Vector Register
-// ========== Register definition for PDC_DBGU peripheral ========== 
-#define AT91C_DBGU_TCR  ((AT91_REG *) 	0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
-#define AT91C_DBGU_RNPR ((AT91_REG *) 	0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
-#define AT91C_DBGU_TNPR ((AT91_REG *) 	0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
-#define AT91C_DBGU_TPR  ((AT91_REG *) 	0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
-#define AT91C_DBGU_RPR  ((AT91_REG *) 	0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
-#define AT91C_DBGU_RCR  ((AT91_REG *) 	0xFFFFF304) // (PDC_DBGU) Receive Counter Register
-#define AT91C_DBGU_RNCR ((AT91_REG *) 	0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
-#define AT91C_DBGU_PTCR ((AT91_REG *) 	0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
-#define AT91C_DBGU_PTSR ((AT91_REG *) 	0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
-#define AT91C_DBGU_TNCR ((AT91_REG *) 	0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
-// ========== Register definition for DBGU peripheral ========== 
-#define AT91C_DBGU_EXID ((AT91_REG *) 	0xFFFFF244) // (DBGU) Chip ID Extension Register
-#define AT91C_DBGU_BRGR ((AT91_REG *) 	0xFFFFF220) // (DBGU) Baud Rate Generator Register
-#define AT91C_DBGU_IDR  ((AT91_REG *) 	0xFFFFF20C) // (DBGU) Interrupt Disable Register
-#define AT91C_DBGU_CSR  ((AT91_REG *) 	0xFFFFF214) // (DBGU) Channel Status Register
-#define AT91C_DBGU_CIDR ((AT91_REG *) 	0xFFFFF240) // (DBGU) Chip ID Register
-#define AT91C_DBGU_MR   ((AT91_REG *) 	0xFFFFF204) // (DBGU) Mode Register
-#define AT91C_DBGU_IMR  ((AT91_REG *) 	0xFFFFF210) // (DBGU) Interrupt Mask Register
-#define AT91C_DBGU_CR   ((AT91_REG *) 	0xFFFFF200) // (DBGU) Control Register
-#define AT91C_DBGU_FNTR ((AT91_REG *) 	0xFFFFF248) // (DBGU) Force NTRST Register
-#define AT91C_DBGU_THR  ((AT91_REG *) 	0xFFFFF21C) // (DBGU) Transmitter Holding Register
-#define AT91C_DBGU_RHR  ((AT91_REG *) 	0xFFFFF218) // (DBGU) Receiver Holding Register
-#define AT91C_DBGU_IER  ((AT91_REG *) 	0xFFFFF208) // (DBGU) Interrupt Enable Register
-// ========== Register definition for PIOA peripheral ========== 
-#define AT91C_PIOA_ODR  ((AT91_REG *) 	0xFFFFF414) // (PIOA) Output Disable Registerr
-#define AT91C_PIOA_SODR ((AT91_REG *) 	0xFFFFF430) // (PIOA) Set Output Data Register
-#define AT91C_PIOA_ISR  ((AT91_REG *) 	0xFFFFF44C) // (PIOA) Interrupt Status Register
-#define AT91C_PIOA_ABSR ((AT91_REG *) 	0xFFFFF478) // (PIOA) AB Select Status Register
-#define AT91C_PIOA_IER  ((AT91_REG *) 	0xFFFFF440) // (PIOA) Interrupt Enable Register
-#define AT91C_PIOA_PPUDR ((AT91_REG *) 	0xFFFFF460) // (PIOA) Pull-up Disable Register
-#define AT91C_PIOA_IMR  ((AT91_REG *) 	0xFFFFF448) // (PIOA) Interrupt Mask Register
-#define AT91C_PIOA_PER  ((AT91_REG *) 	0xFFFFF400) // (PIOA) PIO Enable Register
-#define AT91C_PIOA_IFDR ((AT91_REG *) 	0xFFFFF424) // (PIOA) Input Filter Disable Register
-#define AT91C_PIOA_OWDR ((AT91_REG *) 	0xFFFFF4A4) // (PIOA) Output Write Disable Register
-#define AT91C_PIOA_MDSR ((AT91_REG *) 	0xFFFFF458) // (PIOA) Multi-driver Status Register
-#define AT91C_PIOA_IDR  ((AT91_REG *) 	0xFFFFF444) // (PIOA) Interrupt Disable Register
-#define AT91C_PIOA_ODSR ((AT91_REG *) 	0xFFFFF438) // (PIOA) Output Data Status Register
-#define AT91C_PIOA_PPUSR ((AT91_REG *) 	0xFFFFF468) // (PIOA) Pull-up Status Register
-#define AT91C_PIOA_OWSR ((AT91_REG *) 	0xFFFFF4A8) // (PIOA) Output Write Status Register
-#define AT91C_PIOA_BSR  ((AT91_REG *) 	0xFFFFF474) // (PIOA) Select B Register
-#define AT91C_PIOA_OWER ((AT91_REG *) 	0xFFFFF4A0) // (PIOA) Output Write Enable Register
-#define AT91C_PIOA_IFER ((AT91_REG *) 	0xFFFFF420) // (PIOA) Input Filter Enable Register
-#define AT91C_PIOA_PDSR ((AT91_REG *) 	0xFFFFF43C) // (PIOA) Pin Data Status Register
-#define AT91C_PIOA_PPUER ((AT91_REG *) 	0xFFFFF464) // (PIOA) Pull-up Enable Register
-#define AT91C_PIOA_OSR  ((AT91_REG *) 	0xFFFFF418) // (PIOA) Output Status Register
-#define AT91C_PIOA_ASR  ((AT91_REG *) 	0xFFFFF470) // (PIOA) Select A Register
-#define AT91C_PIOA_MDDR ((AT91_REG *) 	0xFFFFF454) // (PIOA) Multi-driver Disable Register
-#define AT91C_PIOA_CODR ((AT91_REG *) 	0xFFFFF434) // (PIOA) Clear Output Data Register
-#define AT91C_PIOA_MDER ((AT91_REG *) 	0xFFFFF450) // (PIOA) Multi-driver Enable Register
-#define AT91C_PIOA_PDR  ((AT91_REG *) 	0xFFFFF404) // (PIOA) PIO Disable Register
-#define AT91C_PIOA_IFSR ((AT91_REG *) 	0xFFFFF428) // (PIOA) Input Filter Status Register
-#define AT91C_PIOA_OER  ((AT91_REG *) 	0xFFFFF410) // (PIOA) Output Enable Register
-#define AT91C_PIOA_PSR  ((AT91_REG *) 	0xFFFFF408) // (PIOA) PIO Status Register
-// ========== Register definition for PIOB peripheral ========== 
-#define AT91C_PIOB_OWDR ((AT91_REG *) 	0xFFFFF6A4) // (PIOB) Output Write Disable Register
-#define AT91C_PIOB_MDER ((AT91_REG *) 	0xFFFFF650) // (PIOB) Multi-driver Enable Register
-#define AT91C_PIOB_PPUSR ((AT91_REG *) 	0xFFFFF668) // (PIOB) Pull-up Status Register
-#define AT91C_PIOB_IMR  ((AT91_REG *) 	0xFFFFF648) // (PIOB) Interrupt Mask Register
-#define AT91C_PIOB_ASR  ((AT91_REG *) 	0xFFFFF670) // (PIOB) Select A Register
-#define AT91C_PIOB_PPUDR ((AT91_REG *) 	0xFFFFF660) // (PIOB) Pull-up Disable Register
-#define AT91C_PIOB_PSR  ((AT91_REG *) 	0xFFFFF608) // (PIOB) PIO Status Register
-#define AT91C_PIOB_IER  ((AT91_REG *) 	0xFFFFF640) // (PIOB) Interrupt Enable Register
-#define AT91C_PIOB_CODR ((AT91_REG *) 	0xFFFFF634) // (PIOB) Clear Output Data Register
-#define AT91C_PIOB_OWER ((AT91_REG *) 	0xFFFFF6A0) // (PIOB) Output Write Enable Register
-#define AT91C_PIOB_ABSR ((AT91_REG *) 	0xFFFFF678) // (PIOB) AB Select Status Register
-#define AT91C_PIOB_IFDR ((AT91_REG *) 	0xFFFFF624) // (PIOB) Input Filter Disable Register
-#define AT91C_PIOB_PDSR ((AT91_REG *) 	0xFFFFF63C) // (PIOB) Pin Data Status Register
-#define AT91C_PIOB_IDR  ((AT91_REG *) 	0xFFFFF644) // (PIOB) Interrupt Disable Register
-#define AT91C_PIOB_OWSR ((AT91_REG *) 	0xFFFFF6A8) // (PIOB) Output Write Status Register
-#define AT91C_PIOB_PDR  ((AT91_REG *) 	0xFFFFF604) // (PIOB) PIO Disable Register
-#define AT91C_PIOB_ODR  ((AT91_REG *) 	0xFFFFF614) // (PIOB) Output Disable Registerr
-#define AT91C_PIOB_IFSR ((AT91_REG *) 	0xFFFFF628) // (PIOB) Input Filter Status Register
-#define AT91C_PIOB_PPUER ((AT91_REG *) 	0xFFFFF664) // (PIOB) Pull-up Enable Register
-#define AT91C_PIOB_SODR ((AT91_REG *) 	0xFFFFF630) // (PIOB) Set Output Data Register
-#define AT91C_PIOB_ISR  ((AT91_REG *) 	0xFFFFF64C) // (PIOB) Interrupt Status Register
-#define AT91C_PIOB_ODSR ((AT91_REG *) 	0xFFFFF638) // (PIOB) Output Data Status Register
-#define AT91C_PIOB_OSR  ((AT91_REG *) 	0xFFFFF618) // (PIOB) Output Status Register
-#define AT91C_PIOB_MDSR ((AT91_REG *) 	0xFFFFF658) // (PIOB) Multi-driver Status Register
-#define AT91C_PIOB_IFER ((AT91_REG *) 	0xFFFFF620) // (PIOB) Input Filter Enable Register
-#define AT91C_PIOB_BSR  ((AT91_REG *) 	0xFFFFF674) // (PIOB) Select B Register
-#define AT91C_PIOB_MDDR ((AT91_REG *) 	0xFFFFF654) // (PIOB) Multi-driver Disable Register
-#define AT91C_PIOB_OER  ((AT91_REG *) 	0xFFFFF610) // (PIOB) Output Enable Register
-#define AT91C_PIOB_PER  ((AT91_REG *) 	0xFFFFF600) // (PIOB) PIO Enable Register
-// ========== Register definition for CKGR peripheral ========== 
-#define AT91C_CKGR_MOR  ((AT91_REG *) 	0xFFFFFC20) // (CKGR) Main Oscillator Register
-#define AT91C_CKGR_PLLR ((AT91_REG *) 	0xFFFFFC2C) // (CKGR) PLL Register
-#define AT91C_CKGR_MCFR ((AT91_REG *) 	0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
-// ========== Register definition for PMC peripheral ========== 
-#define AT91C_PMC_IDR   ((AT91_REG *) 	0xFFFFFC64) // (PMC) Interrupt Disable Register
-#define AT91C_PMC_MOR   ((AT91_REG *) 	0xFFFFFC20) // (PMC) Main Oscillator Register
-#define AT91C_PMC_PLLR  ((AT91_REG *) 	0xFFFFFC2C) // (PMC) PLL Register
-#define AT91C_PMC_PCER  ((AT91_REG *) 	0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
-#define AT91C_PMC_PCKR  ((AT91_REG *) 	0xFFFFFC40) // (PMC) Programmable Clock Register
-#define AT91C_PMC_MCKR  ((AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register
-#define AT91C_PMC_SCDR  ((AT91_REG *) 	0xFFFFFC04) // (PMC) System Clock Disable Register
-#define AT91C_PMC_PCDR  ((AT91_REG *) 	0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
-#define AT91C_PMC_SCSR  ((AT91_REG *) 	0xFFFFFC08) // (PMC) System Clock Status Register
-#define AT91C_PMC_PCSR  ((AT91_REG *) 	0xFFFFFC18) // (PMC) Peripheral Clock Status Register
-#define AT91C_PMC_MCFR  ((AT91_REG *) 	0xFFFFFC24) // (PMC) Main Clock  Frequency Register
-#define AT91C_PMC_SCER  ((AT91_REG *) 	0xFFFFFC00) // (PMC) System Clock Enable Register
-#define AT91C_PMC_IMR   ((AT91_REG *) 	0xFFFFFC6C) // (PMC) Interrupt Mask Register
-#define AT91C_PMC_IER   ((AT91_REG *) 	0xFFFFFC60) // (PMC) Interrupt Enable Register
-#define AT91C_PMC_SR    ((AT91_REG *) 	0xFFFFFC68) // (PMC) Status Register
-// ========== Register definition for RSTC peripheral ========== 
-#define AT91C_RSTC_RCR  ((AT91_REG *) 	0xFFFFFD00) // (RSTC) Reset Control Register
-#define AT91C_RSTC_RMR  ((AT91_REG *) 	0xFFFFFD08) // (RSTC) Reset Mode Register
-#define AT91C_RSTC_RSR  ((AT91_REG *) 	0xFFFFFD04) // (RSTC) Reset Status Register
-// ========== Register definition for RTTC peripheral ========== 
-#define AT91C_RTTC_RTSR ((AT91_REG *) 	0xFFFFFD2C) // (RTTC) Real-time Status Register
-#define AT91C_RTTC_RTMR ((AT91_REG *) 	0xFFFFFD20) // (RTTC) Real-time Mode Register
-#define AT91C_RTTC_RTVR ((AT91_REG *) 	0xFFFFFD28) // (RTTC) Real-time Value Register
-#define AT91C_RTTC_RTAR ((AT91_REG *) 	0xFFFFFD24) // (RTTC) Real-time Alarm Register
-// ========== Register definition for PITC peripheral ========== 
-#define AT91C_PITC_PIVR ((AT91_REG *) 	0xFFFFFD38) // (PITC) Period Interval Value Register
-#define AT91C_PITC_PISR ((AT91_REG *) 	0xFFFFFD34) // (PITC) Period Interval Status Register
-#define AT91C_PITC_PIIR ((AT91_REG *) 	0xFFFFFD3C) // (PITC) Period Interval Image Register
-#define AT91C_PITC_PIMR ((AT91_REG *) 	0xFFFFFD30) // (PITC) Period Interval Mode Register
-// ========== Register definition for WDTC peripheral ========== 
-#define AT91C_WDTC_WDCR ((AT91_REG *) 	0xFFFFFD40) // (WDTC) Watchdog Control Register
-#define AT91C_WDTC_WDSR ((AT91_REG *) 	0xFFFFFD48) // (WDTC) Watchdog Status Register
-#define AT91C_WDTC_WDMR ((AT91_REG *) 	0xFFFFFD44) // (WDTC) Watchdog Mode Register
-// ========== Register definition for VREG peripheral ========== 
-#define AT91C_VREG_MR   ((AT91_REG *) 	0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
-// ========== Register definition for MC peripheral ========== 
-#define AT91C_MC_ASR    ((AT91_REG *) 	0xFFFFFF04) // (MC) MC Abort Status Register
-#define AT91C_MC_RCR    ((AT91_REG *) 	0xFFFFFF00) // (MC) MC Remap Control Register
-#define AT91C_MC_FCR    ((AT91_REG *) 	0xFFFFFF64) // (MC) MC Flash Command Register
-#define AT91C_MC_AASR   ((AT91_REG *) 	0xFFFFFF08) // (MC) MC Abort Address Status Register
-#define AT91C_MC_FSR    ((AT91_REG *) 	0xFFFFFF68) // (MC) MC Flash Status Register
-#define AT91C_MC_FMR    ((AT91_REG *) 	0xFFFFFF60) // (MC) MC Flash Mode Register
-// ========== Register definition for PDC_SPI1 peripheral ========== 
-#define AT91C_SPI1_PTCR ((AT91_REG *) 	0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
-#define AT91C_SPI1_RPR  ((AT91_REG *) 	0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
-#define AT91C_SPI1_TNCR ((AT91_REG *) 	0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
-#define AT91C_SPI1_TPR  ((AT91_REG *) 	0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
-#define AT91C_SPI1_TNPR ((AT91_REG *) 	0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
-#define AT91C_SPI1_TCR  ((AT91_REG *) 	0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
-#define AT91C_SPI1_RCR  ((AT91_REG *) 	0xFFFE4104) // (PDC_SPI1) Receive Counter Register
-#define AT91C_SPI1_RNPR ((AT91_REG *) 	0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
-#define AT91C_SPI1_RNCR ((AT91_REG *) 	0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
-#define AT91C_SPI1_PTSR ((AT91_REG *) 	0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
-// ========== Register definition for SPI1 peripheral ========== 
-#define AT91C_SPI1_IMR  ((AT91_REG *) 	0xFFFE401C) // (SPI1) Interrupt Mask Register
-#define AT91C_SPI1_IER  ((AT91_REG *) 	0xFFFE4014) // (SPI1) Interrupt Enable Register
-#define AT91C_SPI1_MR   ((AT91_REG *) 	0xFFFE4004) // (SPI1) Mode Register
-#define AT91C_SPI1_RDR  ((AT91_REG *) 	0xFFFE4008) // (SPI1) Receive Data Register
-#define AT91C_SPI1_IDR  ((AT91_REG *) 	0xFFFE4018) // (SPI1) Interrupt Disable Register
-#define AT91C_SPI1_SR   ((AT91_REG *) 	0xFFFE4010) // (SPI1) Status Register
-#define AT91C_SPI1_TDR  ((AT91_REG *) 	0xFFFE400C) // (SPI1) Transmit Data Register
-#define AT91C_SPI1_CR   ((AT91_REG *) 	0xFFFE4000) // (SPI1) Control Register
-#define AT91C_SPI1_CSR  ((AT91_REG *) 	0xFFFE4030) // (SPI1) Chip Select Register
-// ========== Register definition for PDC_SPI0 peripheral ========== 
-#define AT91C_SPI0_PTCR ((AT91_REG *) 	0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
-#define AT91C_SPI0_TPR  ((AT91_REG *) 	0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
-#define AT91C_SPI0_TCR  ((AT91_REG *) 	0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
-#define AT91C_SPI0_RCR  ((AT91_REG *) 	0xFFFE0104) // (PDC_SPI0) Receive Counter Register
-#define AT91C_SPI0_PTSR ((AT91_REG *) 	0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
-#define AT91C_SPI0_RNPR ((AT91_REG *) 	0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
-#define AT91C_SPI0_RPR  ((AT91_REG *) 	0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
-#define AT91C_SPI0_TNCR ((AT91_REG *) 	0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
-#define AT91C_SPI0_RNCR ((AT91_REG *) 	0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
-#define AT91C_SPI0_TNPR ((AT91_REG *) 	0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
-// ========== Register definition for SPI0 peripheral ========== 
-#define AT91C_SPI0_IER  ((AT91_REG *) 	0xFFFE0014) // (SPI0) Interrupt Enable Register
-#define AT91C_SPI0_SR   ((AT91_REG *) 	0xFFFE0010) // (SPI0) Status Register
-#define AT91C_SPI0_IDR  ((AT91_REG *) 	0xFFFE0018) // (SPI0) Interrupt Disable Register
-#define AT91C_SPI0_CR   ((AT91_REG *) 	0xFFFE0000) // (SPI0) Control Register
-#define AT91C_SPI0_MR   ((AT91_REG *) 	0xFFFE0004) // (SPI0) Mode Register
-#define AT91C_SPI0_IMR  ((AT91_REG *) 	0xFFFE001C) // (SPI0) Interrupt Mask Register
-#define AT91C_SPI0_TDR  ((AT91_REG *) 	0xFFFE000C) // (SPI0) Transmit Data Register
-#define AT91C_SPI0_RDR  ((AT91_REG *) 	0xFFFE0008) // (SPI0) Receive Data Register
-#define AT91C_SPI0_CSR  ((AT91_REG *) 	0xFFFE0030) // (SPI0) Chip Select Register
-// ========== Register definition for PDC_US1 peripheral ========== 
-#define AT91C_US1_RNCR  ((AT91_REG *) 	0xFFFC4114) // (PDC_US1) Receive Next Counter Register
-#define AT91C_US1_PTCR  ((AT91_REG *) 	0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
-#define AT91C_US1_TCR   ((AT91_REG *) 	0xFFFC410C) // (PDC_US1) Transmit Counter Register
-#define AT91C_US1_PTSR  ((AT91_REG *) 	0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
-#define AT91C_US1_TNPR  ((AT91_REG *) 	0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
-#define AT91C_US1_RCR   ((AT91_REG *) 	0xFFFC4104) // (PDC_US1) Receive Counter Register
-#define AT91C_US1_RNPR  ((AT91_REG *) 	0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
-#define AT91C_US1_RPR   ((AT91_REG *) 	0xFFFC4100) // (PDC_US1) Receive Pointer Register
-#define AT91C_US1_TNCR  ((AT91_REG *) 	0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
-#define AT91C_US1_TPR   ((AT91_REG *) 	0xFFFC4108) // (PDC_US1) Transmit Pointer Register
-// ========== Register definition for US1 peripheral ========== 
-#define AT91C_US1_IF    ((AT91_REG *) 	0xFFFC404C) // (US1) IRDA_FILTER Register
-#define AT91C_US1_NER   ((AT91_REG *) 	0xFFFC4044) // (US1) Nb Errors Register
-#define AT91C_US1_RTOR  ((AT91_REG *) 	0xFFFC4024) // (US1) Receiver Time-out Register
-#define AT91C_US1_CSR   ((AT91_REG *) 	0xFFFC4014) // (US1) Channel Status Register
-#define AT91C_US1_IDR   ((AT91_REG *) 	0xFFFC400C) // (US1) Interrupt Disable Register
-#define AT91C_US1_IER   ((AT91_REG *) 	0xFFFC4008) // (US1) Interrupt Enable Register
-#define AT91C_US1_THR   ((AT91_REG *) 	0xFFFC401C) // (US1) Transmitter Holding Register
-#define AT91C_US1_TTGR  ((AT91_REG *) 	0xFFFC4028) // (US1) Transmitter Time-guard Register
-#define AT91C_US1_RHR   ((AT91_REG *) 	0xFFFC4018) // (US1) Receiver Holding Register
-#define AT91C_US1_BRGR  ((AT91_REG *) 	0xFFFC4020) // (US1) Baud Rate Generator Register
-#define AT91C_US1_IMR   ((AT91_REG *) 	0xFFFC4010) // (US1) Interrupt Mask Register
-#define AT91C_US1_FIDI  ((AT91_REG *) 	0xFFFC4040) // (US1) FI_DI_Ratio Register
-#define AT91C_US1_CR    ((AT91_REG *) 	0xFFFC4000) // (US1) Control Register
-#define AT91C_US1_MR    ((AT91_REG *) 	0xFFFC4004) // (US1) Mode Register
-// ========== Register definition for PDC_US0 peripheral ========== 
-#define AT91C_US0_TNPR  ((AT91_REG *) 	0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
-#define AT91C_US0_RNPR  ((AT91_REG *) 	0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
-#define AT91C_US0_TCR   ((AT91_REG *) 	0xFFFC010C) // (PDC_US0) Transmit Counter Register
-#define AT91C_US0_PTCR  ((AT91_REG *) 	0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
-#define AT91C_US0_PTSR  ((AT91_REG *) 	0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
-#define AT91C_US0_TNCR  ((AT91_REG *) 	0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
-#define AT91C_US0_TPR   ((AT91_REG *) 	0xFFFC0108) // (PDC_US0) Transmit Pointer Register
-#define AT91C_US0_RCR   ((AT91_REG *) 	0xFFFC0104) // (PDC_US0) Receive Counter Register
-#define AT91C_US0_RPR   ((AT91_REG *) 	0xFFFC0100) // (PDC_US0) Receive Pointer Register
-#define AT91C_US0_RNCR  ((AT91_REG *) 	0xFFFC0114) // (PDC_US0) Receive Next Counter Register
-// ========== Register definition for US0 peripheral ========== 
-#define AT91C_US0_BRGR  ((AT91_REG *) 	0xFFFC0020) // (US0) Baud Rate Generator Register
-#define AT91C_US0_NER   ((AT91_REG *) 	0xFFFC0044) // (US0) Nb Errors Register
-#define AT91C_US0_CR    ((AT91_REG *) 	0xFFFC0000) // (US0) Control Register
-#define AT91C_US0_IMR   ((AT91_REG *) 	0xFFFC0010) // (US0) Interrupt Mask Register
-#define AT91C_US0_FIDI  ((AT91_REG *) 	0xFFFC0040) // (US0) FI_DI_Ratio Register
-#define AT91C_US0_TTGR  ((AT91_REG *) 	0xFFFC0028) // (US0) Transmitter Time-guard Register
-#define AT91C_US0_MR    ((AT91_REG *) 	0xFFFC0004) // (US0) Mode Register
-#define AT91C_US0_RTOR  ((AT91_REG *) 	0xFFFC0024) // (US0) Receiver Time-out Register
-#define AT91C_US0_CSR   ((AT91_REG *) 	0xFFFC0014) // (US0) Channel Status Register
-#define AT91C_US0_RHR   ((AT91_REG *) 	0xFFFC0018) // (US0) Receiver Holding Register
-#define AT91C_US0_IDR   ((AT91_REG *) 	0xFFFC000C) // (US0) Interrupt Disable Register
-#define AT91C_US0_THR   ((AT91_REG *) 	0xFFFC001C) // (US0) Transmitter Holding Register
-#define AT91C_US0_IF    ((AT91_REG *) 	0xFFFC004C) // (US0) IRDA_FILTER Register
-#define AT91C_US0_IER   ((AT91_REG *) 	0xFFFC0008) // (US0) Interrupt Enable Register
-// ========== Register definition for PDC_SSC peripheral ========== 
-#define AT91C_SSC_TNCR  ((AT91_REG *) 	0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
-#define AT91C_SSC_RPR   ((AT91_REG *) 	0xFFFD4100) // (PDC_SSC) Receive Pointer Register
-#define AT91C_SSC_RNCR  ((AT91_REG *) 	0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
-#define AT91C_SSC_TPR   ((AT91_REG *) 	0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
-#define AT91C_SSC_PTCR  ((AT91_REG *) 	0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
-#define AT91C_SSC_TCR   ((AT91_REG *) 	0xFFFD410C) // (PDC_SSC) Transmit Counter Register
-#define AT91C_SSC_RCR   ((AT91_REG *) 	0xFFFD4104) // (PDC_SSC) Receive Counter Register
-#define AT91C_SSC_RNPR  ((AT91_REG *) 	0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
-#define AT91C_SSC_TNPR  ((AT91_REG *) 	0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
-#define AT91C_SSC_PTSR  ((AT91_REG *) 	0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
-// ========== Register definition for SSC peripheral ========== 
-#define AT91C_SSC_RHR   ((AT91_REG *) 	0xFFFD4020) // (SSC) Receive Holding Register
-#define AT91C_SSC_RSHR  ((AT91_REG *) 	0xFFFD4030) // (SSC) Receive Sync Holding Register
-#define AT91C_SSC_TFMR  ((AT91_REG *) 	0xFFFD401C) // (SSC) Transmit Frame Mode Register
-#define AT91C_SSC_IDR   ((AT91_REG *) 	0xFFFD4048) // (SSC) Interrupt Disable Register
-#define AT91C_SSC_THR   ((AT91_REG *) 	0xFFFD4024) // (SSC) Transmit Holding Register
-#define AT91C_SSC_RCMR  ((AT91_REG *) 	0xFFFD4010) // (SSC) Receive Clock ModeRegister
-#define AT91C_SSC_IER   ((AT91_REG *) 	0xFFFD4044) // (SSC) Interrupt Enable Register
-#define AT91C_SSC_TSHR  ((AT91_REG *) 	0xFFFD4034) // (SSC) Transmit Sync Holding Register
-#define AT91C_SSC_SR    ((AT91_REG *) 	0xFFFD4040) // (SSC) Status Register
-#define AT91C_SSC_CMR   ((AT91_REG *) 	0xFFFD4004) // (SSC) Clock Mode Register
-#define AT91C_SSC_TCMR  ((AT91_REG *) 	0xFFFD4018) // (SSC) Transmit Clock Mode Register
-#define AT91C_SSC_CR    ((AT91_REG *) 	0xFFFD4000) // (SSC) Control Register
-#define AT91C_SSC_IMR   ((AT91_REG *) 	0xFFFD404C) // (SSC) Interrupt Mask Register
-#define AT91C_SSC_RFMR  ((AT91_REG *) 	0xFFFD4014) // (SSC) Receive Frame Mode Register
-// ========== Register definition for TWI peripheral ========== 
-#define AT91C_TWI_IER   ((AT91_REG *) 	0xFFFB8024) // (TWI) Interrupt Enable Register
-#define AT91C_TWI_CR    ((AT91_REG *) 	0xFFFB8000) // (TWI) Control Register
-#define AT91C_TWI_SR    ((AT91_REG *) 	0xFFFB8020) // (TWI) Status Register
-#define AT91C_TWI_IMR   ((AT91_REG *) 	0xFFFB802C) // (TWI) Interrupt Mask Register
-#define AT91C_TWI_THR   ((AT91_REG *) 	0xFFFB8034) // (TWI) Transmit Holding Register
-#define AT91C_TWI_IDR   ((AT91_REG *) 	0xFFFB8028) // (TWI) Interrupt Disable Register
-#define AT91C_TWI_IADR  ((AT91_REG *) 	0xFFFB800C) // (TWI) Internal Address Register
-#define AT91C_TWI_MMR   ((AT91_REG *) 	0xFFFB8004) // (TWI) Master Mode Register
-#define AT91C_TWI_CWGR  ((AT91_REG *) 	0xFFFB8010) // (TWI) Clock Waveform Generator Register
-#define AT91C_TWI_RHR   ((AT91_REG *) 	0xFFFB8030) // (TWI) Receive Holding Register
-// ========== Register definition for PWMC_CH3 peripheral ========== 
-#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 	0xFFFCC270) // (PWMC_CH3) Channel Update Register
-#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 	0xFFFCC274) // (PWMC_CH3) Reserved
-#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 	0xFFFCC268) // (PWMC_CH3) Channel Period Register
-#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 	0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
-#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 	0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
-#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 	0xFFFCC260) // (PWMC_CH3) Channel Mode Register
-// ========== Register definition for PWMC_CH2 peripheral ========== 
-#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 	0xFFFCC254) // (PWMC_CH2) Reserved
-#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 	0xFFFCC240) // (PWMC_CH2) Channel Mode Register
-#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 	0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
-#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 	0xFFFCC248) // (PWMC_CH2) Channel Period Register
-#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 	0xFFFCC250) // (PWMC_CH2) Channel Update Register
-#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 	0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH1 peripheral ========== 
-#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 	0xFFFCC234) // (PWMC_CH1) Reserved
-#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 	0xFFFCC230) // (PWMC_CH1) Channel Update Register
-#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 	0xFFFCC228) // (PWMC_CH1) Channel Period Register
-#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 	0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
-#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 	0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
-#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 	0xFFFCC220) // (PWMC_CH1) Channel Mode Register
-// ========== Register definition for PWMC_CH0 peripheral ========== 
-#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 	0xFFFCC214) // (PWMC_CH0) Reserved
-#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 	0xFFFCC208) // (PWMC_CH0) Channel Period Register
-#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 	0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
-#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 	0xFFFCC200) // (PWMC_CH0) Channel Mode Register
-#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 	0xFFFCC210) // (PWMC_CH0) Channel Update Register
-#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 	0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
-// ========== Register definition for PWMC peripheral ========== 
-#define AT91C_PWMC_IDR  ((AT91_REG *) 	0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
-#define AT91C_PWMC_DIS  ((AT91_REG *) 	0xFFFCC008) // (PWMC) PWMC Disable Register
-#define AT91C_PWMC_IER  ((AT91_REG *) 	0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
-#define AT91C_PWMC_VR   ((AT91_REG *) 	0xFFFCC0FC) // (PWMC) PWMC Version Register
-#define AT91C_PWMC_ISR  ((AT91_REG *) 	0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
-#define AT91C_PWMC_SR   ((AT91_REG *) 	0xFFFCC00C) // (PWMC) PWMC Status Register
-#define AT91C_PWMC_IMR  ((AT91_REG *) 	0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
-#define AT91C_PWMC_MR   ((AT91_REG *) 	0xFFFCC000) // (PWMC) PWMC Mode Register
-#define AT91C_PWMC_ENA  ((AT91_REG *) 	0xFFFCC004) // (PWMC) PWMC Enable Register
-// ========== Register definition for UDP peripheral ========== 
-#define AT91C_UDP_IMR   ((AT91_REG *) 	0xFFFB0018) // (UDP) Interrupt Mask Register
-#define AT91C_UDP_FADDR ((AT91_REG *) 	0xFFFB0008) // (UDP) Function Address Register
-#define AT91C_UDP_NUM   ((AT91_REG *) 	0xFFFB0000) // (UDP) Frame Number Register
-#define AT91C_UDP_FDR   ((AT91_REG *) 	0xFFFB0050) // (UDP) Endpoint FIFO Data Register
-#define AT91C_UDP_ISR   ((AT91_REG *) 	0xFFFB001C) // (UDP) Interrupt Status Register
-#define AT91C_UDP_CSR   ((AT91_REG *) 	0xFFFB0030) // (UDP) Endpoint Control and Status Register
-#define AT91C_UDP_IDR   ((AT91_REG *) 	0xFFFB0014) // (UDP) Interrupt Disable Register
-#define AT91C_UDP_ICR   ((AT91_REG *) 	0xFFFB0020) // (UDP) Interrupt Clear Register
-#define AT91C_UDP_RSTEP ((AT91_REG *) 	0xFFFB0028) // (UDP) Reset Endpoint Register
-#define AT91C_UDP_TXVC  ((AT91_REG *) 	0xFFFB0074) // (UDP) Transceiver Control Register
-#define AT91C_UDP_GLBSTATE ((AT91_REG *) 	0xFFFB0004) // (UDP) Global State Register
-#define AT91C_UDP_IER   ((AT91_REG *) 	0xFFFB0010) // (UDP) Interrupt Enable Register
-// ========== Register definition for TC0 peripheral ========== 
-#define AT91C_TC0_SR    ((AT91_REG *) 	0xFFFA0020) // (TC0) Status Register
-#define AT91C_TC0_RC    ((AT91_REG *) 	0xFFFA001C) // (TC0) Register C
-#define AT91C_TC0_RB    ((AT91_REG *) 	0xFFFA0018) // (TC0) Register B
-#define AT91C_TC0_CCR   ((AT91_REG *) 	0xFFFA0000) // (TC0) Channel Control Register
-#define AT91C_TC0_CMR   ((AT91_REG *) 	0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC0_IER   ((AT91_REG *) 	0xFFFA0024) // (TC0) Interrupt Enable Register
-#define AT91C_TC0_RA    ((AT91_REG *) 	0xFFFA0014) // (TC0) Register A
-#define AT91C_TC0_IDR   ((AT91_REG *) 	0xFFFA0028) // (TC0) Interrupt Disable Register
-#define AT91C_TC0_CV    ((AT91_REG *) 	0xFFFA0010) // (TC0) Counter Value
-#define AT91C_TC0_IMR   ((AT91_REG *) 	0xFFFA002C) // (TC0) Interrupt Mask Register
-// ========== Register definition for TC1 peripheral ========== 
-#define AT91C_TC1_RB    ((AT91_REG *) 	0xFFFA0058) // (TC1) Register B
-#define AT91C_TC1_CCR   ((AT91_REG *) 	0xFFFA0040) // (TC1) Channel Control Register
-#define AT91C_TC1_IER   ((AT91_REG *) 	0xFFFA0064) // (TC1) Interrupt Enable Register
-#define AT91C_TC1_IDR   ((AT91_REG *) 	0xFFFA0068) // (TC1) Interrupt Disable Register
-#define AT91C_TC1_SR    ((AT91_REG *) 	0xFFFA0060) // (TC1) Status Register
-#define AT91C_TC1_CMR   ((AT91_REG *) 	0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC1_RA    ((AT91_REG *) 	0xFFFA0054) // (TC1) Register A
-#define AT91C_TC1_RC    ((AT91_REG *) 	0xFFFA005C) // (TC1) Register C
-#define AT91C_TC1_IMR   ((AT91_REG *) 	0xFFFA006C) // (TC1) Interrupt Mask Register
-#define AT91C_TC1_CV    ((AT91_REG *) 	0xFFFA0050) // (TC1) Counter Value
-// ========== Register definition for TC2 peripheral ========== 
-#define AT91C_TC2_CMR   ((AT91_REG *) 	0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC2_CCR   ((AT91_REG *) 	0xFFFA0080) // (TC2) Channel Control Register
-#define AT91C_TC2_CV    ((AT91_REG *) 	0xFFFA0090) // (TC2) Counter Value
-#define AT91C_TC2_RA    ((AT91_REG *) 	0xFFFA0094) // (TC2) Register A
-#define AT91C_TC2_RB    ((AT91_REG *) 	0xFFFA0098) // (TC2) Register B
-#define AT91C_TC2_IDR   ((AT91_REG *) 	0xFFFA00A8) // (TC2) Interrupt Disable Register
-#define AT91C_TC2_IMR   ((AT91_REG *) 	0xFFFA00AC) // (TC2) Interrupt Mask Register
-#define AT91C_TC2_RC    ((AT91_REG *) 	0xFFFA009C) // (TC2) Register C
-#define AT91C_TC2_IER   ((AT91_REG *) 	0xFFFA00A4) // (TC2) Interrupt Enable Register
-#define AT91C_TC2_SR    ((AT91_REG *) 	0xFFFA00A0) // (TC2) Status Register
-// ========== Register definition for TCB peripheral ========== 
-#define AT91C_TCB_BMR   ((AT91_REG *) 	0xFFFA00C4) // (TCB) TC Block Mode Register
-#define AT91C_TCB_BCR   ((AT91_REG *) 	0xFFFA00C0) // (TCB) TC Block Control Register
-// ========== Register definition for CAN_MB0 peripheral ========== 
-#define AT91C_CAN_MB0_MDL ((AT91_REG *) 	0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
-#define AT91C_CAN_MB0_MAM ((AT91_REG *) 	0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB0_MCR ((AT91_REG *) 	0xFFFD021C) // (CAN_MB0) MailBox Control Register
-#define AT91C_CAN_MB0_MID ((AT91_REG *) 	0xFFFD0208) // (CAN_MB0) MailBox ID Register
-#define AT91C_CAN_MB0_MSR ((AT91_REG *) 	0xFFFD0210) // (CAN_MB0) MailBox Status Register
-#define AT91C_CAN_MB0_MFID ((AT91_REG *) 	0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
-#define AT91C_CAN_MB0_MDH ((AT91_REG *) 	0xFFFD0218) // (CAN_MB0) MailBox Data High Register
-#define AT91C_CAN_MB0_MMR ((AT91_REG *) 	0xFFFD0200) // (CAN_MB0) MailBox Mode Register
-// ========== Register definition for CAN_MB1 peripheral ========== 
-#define AT91C_CAN_MB1_MDL ((AT91_REG *) 	0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
-#define AT91C_CAN_MB1_MID ((AT91_REG *) 	0xFFFD0228) // (CAN_MB1) MailBox ID Register
-#define AT91C_CAN_MB1_MMR ((AT91_REG *) 	0xFFFD0220) // (CAN_MB1) MailBox Mode Register
-#define AT91C_CAN_MB1_MSR ((AT91_REG *) 	0xFFFD0230) // (CAN_MB1) MailBox Status Register
-#define AT91C_CAN_MB1_MAM ((AT91_REG *) 	0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB1_MDH ((AT91_REG *) 	0xFFFD0238) // (CAN_MB1) MailBox Data High Register
-#define AT91C_CAN_MB1_MCR ((AT91_REG *) 	0xFFFD023C) // (CAN_MB1) MailBox Control Register
-#define AT91C_CAN_MB1_MFID ((AT91_REG *) 	0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
-// ========== Register definition for CAN_MB2 peripheral ========== 
-#define AT91C_CAN_MB2_MCR ((AT91_REG *) 	0xFFFD025C) // (CAN_MB2) MailBox Control Register
-#define AT91C_CAN_MB2_MDH ((AT91_REG *) 	0xFFFD0258) // (CAN_MB2) MailBox Data High Register
-#define AT91C_CAN_MB2_MID ((AT91_REG *) 	0xFFFD0248) // (CAN_MB2) MailBox ID Register
-#define AT91C_CAN_MB2_MDL ((AT91_REG *) 	0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
-#define AT91C_CAN_MB2_MMR ((AT91_REG *) 	0xFFFD0240) // (CAN_MB2) MailBox Mode Register
-#define AT91C_CAN_MB2_MAM ((AT91_REG *) 	0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB2_MFID ((AT91_REG *) 	0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
-#define AT91C_CAN_MB2_MSR ((AT91_REG *) 	0xFFFD0250) // (CAN_MB2) MailBox Status Register
-// ========== Register definition for CAN_MB3 peripheral ========== 
-#define AT91C_CAN_MB3_MFID ((AT91_REG *) 	0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
-#define AT91C_CAN_MB3_MAM ((AT91_REG *) 	0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB3_MID ((AT91_REG *) 	0xFFFD0268) // (CAN_MB3) MailBox ID Register
-#define AT91C_CAN_MB3_MCR ((AT91_REG *) 	0xFFFD027C) // (CAN_MB3) MailBox Control Register
-#define AT91C_CAN_MB3_MMR ((AT91_REG *) 	0xFFFD0260) // (CAN_MB3) MailBox Mode Register
-#define AT91C_CAN_MB3_MSR ((AT91_REG *) 	0xFFFD0270) // (CAN_MB3) MailBox Status Register
-#define AT91C_CAN_MB3_MDL ((AT91_REG *) 	0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
-#define AT91C_CAN_MB3_MDH ((AT91_REG *) 	0xFFFD0278) // (CAN_MB3) MailBox Data High Register
-// ========== Register definition for CAN_MB4 peripheral ========== 
-#define AT91C_CAN_MB4_MID ((AT91_REG *) 	0xFFFD0288) // (CAN_MB4) MailBox ID Register
-#define AT91C_CAN_MB4_MMR ((AT91_REG *) 	0xFFFD0280) // (CAN_MB4) MailBox Mode Register
-#define AT91C_CAN_MB4_MDH ((AT91_REG *) 	0xFFFD0298) // (CAN_MB4) MailBox Data High Register
-#define AT91C_CAN_MB4_MFID ((AT91_REG *) 	0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
-#define AT91C_CAN_MB4_MSR ((AT91_REG *) 	0xFFFD0290) // (CAN_MB4) MailBox Status Register
-#define AT91C_CAN_MB4_MCR ((AT91_REG *) 	0xFFFD029C) // (CAN_MB4) MailBox Control Register
-#define AT91C_CAN_MB4_MDL ((AT91_REG *) 	0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
-#define AT91C_CAN_MB4_MAM ((AT91_REG *) 	0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
-// ========== Register definition for CAN_MB5 peripheral ========== 
-#define AT91C_CAN_MB5_MSR ((AT91_REG *) 	0xFFFD02B0) // (CAN_MB5) MailBox Status Register
-#define AT91C_CAN_MB5_MCR ((AT91_REG *) 	0xFFFD02BC) // (CAN_MB5) MailBox Control Register
-#define AT91C_CAN_MB5_MFID ((AT91_REG *) 	0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
-#define AT91C_CAN_MB5_MDH ((AT91_REG *) 	0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
-#define AT91C_CAN_MB5_MID ((AT91_REG *) 	0xFFFD02A8) // (CAN_MB5) MailBox ID Register
-#define AT91C_CAN_MB5_MMR ((AT91_REG *) 	0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
-#define AT91C_CAN_MB5_MDL ((AT91_REG *) 	0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
-#define AT91C_CAN_MB5_MAM ((AT91_REG *) 	0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
-// ========== Register definition for CAN_MB6 peripheral ========== 
-#define AT91C_CAN_MB6_MFID ((AT91_REG *) 	0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
-#define AT91C_CAN_MB6_MID ((AT91_REG *) 	0xFFFD02C8) // (CAN_MB6) MailBox ID Register
-#define AT91C_CAN_MB6_MAM ((AT91_REG *) 	0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB6_MSR ((AT91_REG *) 	0xFFFD02D0) // (CAN_MB6) MailBox Status Register
-#define AT91C_CAN_MB6_MDL ((AT91_REG *) 	0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
-#define AT91C_CAN_MB6_MCR ((AT91_REG *) 	0xFFFD02DC) // (CAN_MB6) MailBox Control Register
-#define AT91C_CAN_MB6_MDH ((AT91_REG *) 	0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
-#define AT91C_CAN_MB6_MMR ((AT91_REG *) 	0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
-// ========== Register definition for CAN_MB7 peripheral ========== 
-#define AT91C_CAN_MB7_MCR ((AT91_REG *) 	0xFFFD02FC) // (CAN_MB7) MailBox Control Register
-#define AT91C_CAN_MB7_MDH ((AT91_REG *) 	0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
-#define AT91C_CAN_MB7_MFID ((AT91_REG *) 	0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
-#define AT91C_CAN_MB7_MDL ((AT91_REG *) 	0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
-#define AT91C_CAN_MB7_MID ((AT91_REG *) 	0xFFFD02E8) // (CAN_MB7) MailBox ID Register
-#define AT91C_CAN_MB7_MMR ((AT91_REG *) 	0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
-#define AT91C_CAN_MB7_MAM ((AT91_REG *) 	0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB7_MSR ((AT91_REG *) 	0xFFFD02F0) // (CAN_MB7) MailBox Status Register
-// ========== Register definition for CAN peripheral ========== 
-#define AT91C_CAN_TCR   ((AT91_REG *) 	0xFFFD0024) // (CAN) Transfer Command Register
-#define AT91C_CAN_IMR   ((AT91_REG *) 	0xFFFD000C) // (CAN) Interrupt Mask Register
-#define AT91C_CAN_IER   ((AT91_REG *) 	0xFFFD0004) // (CAN) Interrupt Enable Register
-#define AT91C_CAN_ECR   ((AT91_REG *) 	0xFFFD0020) // (CAN) Error Counter Register
-#define AT91C_CAN_TIMESTP ((AT91_REG *) 	0xFFFD001C) // (CAN) Time Stamp Register
-#define AT91C_CAN_MR    ((AT91_REG *) 	0xFFFD0000) // (CAN) Mode Register
-#define AT91C_CAN_IDR   ((AT91_REG *) 	0xFFFD0008) // (CAN) Interrupt Disable Register
-#define AT91C_CAN_ACR   ((AT91_REG *) 	0xFFFD0028) // (CAN) Abort Command Register
-#define AT91C_CAN_TIM   ((AT91_REG *) 	0xFFFD0018) // (CAN) Timer Register
-#define AT91C_CAN_SR    ((AT91_REG *) 	0xFFFD0010) // (CAN) Status Register
-#define AT91C_CAN_BR    ((AT91_REG *) 	0xFFFD0014) // (CAN) Baudrate Register
-#define AT91C_CAN_VR    ((AT91_REG *) 	0xFFFD00FC) // (CAN) Version Register
-// ========== Register definition for EMAC peripheral ========== 
-#define AT91C_EMAC_ISR  ((AT91_REG *) 	0xFFFDC024) // (EMAC) Interrupt Status Register
-#define AT91C_EMAC_SA4H ((AT91_REG *) 	0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
-#define AT91C_EMAC_SA1L ((AT91_REG *) 	0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
-#define AT91C_EMAC_ELE  ((AT91_REG *) 	0xFFFDC078) // (EMAC) Excessive Length Errors Register
-#define AT91C_EMAC_LCOL ((AT91_REG *) 	0xFFFDC05C) // (EMAC) Late Collision Register
-#define AT91C_EMAC_RLE  ((AT91_REG *) 	0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
-#define AT91C_EMAC_WOL  ((AT91_REG *) 	0xFFFDC0C4) // (EMAC) Wake On LAN Register
-#define AT91C_EMAC_DTF  ((AT91_REG *) 	0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
-#define AT91C_EMAC_TUND ((AT91_REG *) 	0xFFFDC064) // (EMAC) Transmit Underrun Error Register
-#define AT91C_EMAC_NCR  ((AT91_REG *) 	0xFFFDC000) // (EMAC) Network Control Register
-#define AT91C_EMAC_SA4L ((AT91_REG *) 	0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
-#define AT91C_EMAC_RSR  ((AT91_REG *) 	0xFFFDC020) // (EMAC) Receive Status Register
-#define AT91C_EMAC_SA3L ((AT91_REG *) 	0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
-#define AT91C_EMAC_TSR  ((AT91_REG *) 	0xFFFDC014) // (EMAC) Transmit Status Register
-#define AT91C_EMAC_IDR  ((AT91_REG *) 	0xFFFDC02C) // (EMAC) Interrupt Disable Register
-#define AT91C_EMAC_RSE  ((AT91_REG *) 	0xFFFDC074) // (EMAC) Receive Symbol Errors Register
-#define AT91C_EMAC_ECOL ((AT91_REG *) 	0xFFFDC060) // (EMAC) Excessive Collision Register
-#define AT91C_EMAC_TID  ((AT91_REG *) 	0xFFFDC0B8) // (EMAC) Type ID Checking Register
-#define AT91C_EMAC_HRB  ((AT91_REG *) 	0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
-#define AT91C_EMAC_TBQP ((AT91_REG *) 	0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
-#define AT91C_EMAC_USRIO ((AT91_REG *) 	0xFFFDC0C0) // (EMAC) USER Input/Output Register
-#define AT91C_EMAC_PTR  ((AT91_REG *) 	0xFFFDC038) // (EMAC) Pause Time Register
-#define AT91C_EMAC_SA2H ((AT91_REG *) 	0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
-#define AT91C_EMAC_ROV  ((AT91_REG *) 	0xFFFDC070) // (EMAC) Receive Overrun Errors Register
-#define AT91C_EMAC_ALE  ((AT91_REG *) 	0xFFFDC054) // (EMAC) Alignment Error Register
-#define AT91C_EMAC_RJA  ((AT91_REG *) 	0xFFFDC07C) // (EMAC) Receive Jabbers Register
-#define AT91C_EMAC_RBQP ((AT91_REG *) 	0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
-#define AT91C_EMAC_TPF  ((AT91_REG *) 	0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
-#define AT91C_EMAC_NCFGR ((AT91_REG *) 	0xFFFDC004) // (EMAC) Network Configuration Register
-#define AT91C_EMAC_HRT  ((AT91_REG *) 	0xFFFDC094) // (EMAC) Hash Address Top[63:32]
-#define AT91C_EMAC_USF  ((AT91_REG *) 	0xFFFDC080) // (EMAC) Undersize Frames Register
-#define AT91C_EMAC_FCSE ((AT91_REG *) 	0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
-#define AT91C_EMAC_TPQ  ((AT91_REG *) 	0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
-#define AT91C_EMAC_MAN  ((AT91_REG *) 	0xFFFDC034) // (EMAC) PHY Maintenance Register
-#define AT91C_EMAC_FTO  ((AT91_REG *) 	0xFFFDC040) // (EMAC) Frames Transmitted OK Register
-#define AT91C_EMAC_REV  ((AT91_REG *) 	0xFFFDC0FC) // (EMAC) Revision Register
-#define AT91C_EMAC_IMR  ((AT91_REG *) 	0xFFFDC030) // (EMAC) Interrupt Mask Register
-#define AT91C_EMAC_SCF  ((AT91_REG *) 	0xFFFDC044) // (EMAC) Single Collision Frame Register
-#define AT91C_EMAC_PFR  ((AT91_REG *) 	0xFFFDC03C) // (EMAC) Pause Frames received Register
-#define AT91C_EMAC_MCF  ((AT91_REG *) 	0xFFFDC048) // (EMAC) Multiple Collision Frame Register
-#define AT91C_EMAC_NSR  ((AT91_REG *) 	0xFFFDC008) // (EMAC) Network Status Register
-#define AT91C_EMAC_SA2L ((AT91_REG *) 	0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
-#define AT91C_EMAC_FRO  ((AT91_REG *) 	0xFFFDC04C) // (EMAC) Frames Received OK Register
-#define AT91C_EMAC_IER  ((AT91_REG *) 	0xFFFDC028) // (EMAC) Interrupt Enable Register
-#define AT91C_EMAC_SA1H ((AT91_REG *) 	0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
-#define AT91C_EMAC_CSE  ((AT91_REG *) 	0xFFFDC068) // (EMAC) Carrier Sense Error Register
-#define AT91C_EMAC_SA3H ((AT91_REG *) 	0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
-#define AT91C_EMAC_RRE  ((AT91_REG *) 	0xFFFDC06C) // (EMAC) Receive Ressource Error Register
-#define AT91C_EMAC_STE  ((AT91_REG *) 	0xFFFDC084) // (EMAC) SQE Test Error Register
-// ========== Register definition for PDC_ADC peripheral ========== 
-#define AT91C_ADC_PTSR  ((AT91_REG *) 	0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
-#define AT91C_ADC_PTCR  ((AT91_REG *) 	0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
-#define AT91C_ADC_TNPR  ((AT91_REG *) 	0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
-#define AT91C_ADC_TNCR  ((AT91_REG *) 	0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
-#define AT91C_ADC_RNPR  ((AT91_REG *) 	0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
-#define AT91C_ADC_RNCR  ((AT91_REG *) 	0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
-#define AT91C_ADC_RPR   ((AT91_REG *) 	0xFFFD8100) // (PDC_ADC) Receive Pointer Register
-#define AT91C_ADC_TCR   ((AT91_REG *) 	0xFFFD810C) // (PDC_ADC) Transmit Counter Register
-#define AT91C_ADC_TPR   ((AT91_REG *) 	0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
-#define AT91C_ADC_RCR   ((AT91_REG *) 	0xFFFD8104) // (PDC_ADC) Receive Counter Register
-// ========== Register definition for ADC peripheral ========== 
-#define AT91C_ADC_CDR2  ((AT91_REG *) 	0xFFFD8038) // (ADC) ADC Channel Data Register 2
-#define AT91C_ADC_CDR3  ((AT91_REG *) 	0xFFFD803C) // (ADC) ADC Channel Data Register 3
-#define AT91C_ADC_CDR0  ((AT91_REG *) 	0xFFFD8030) // (ADC) ADC Channel Data Register 0
-#define AT91C_ADC_CDR5  ((AT91_REG *) 	0xFFFD8044) // (ADC) ADC Channel Data Register 5
-#define AT91C_ADC_CHDR  ((AT91_REG *) 	0xFFFD8014) // (ADC) ADC Channel Disable Register
-#define AT91C_ADC_SR    ((AT91_REG *) 	0xFFFD801C) // (ADC) ADC Status Register
-#define AT91C_ADC_CDR4  ((AT91_REG *) 	0xFFFD8040) // (ADC) ADC Channel Data Register 4
-#define AT91C_ADC_CDR1  ((AT91_REG *) 	0xFFFD8034) // (ADC) ADC Channel Data Register 1
-#define AT91C_ADC_LCDR  ((AT91_REG *) 	0xFFFD8020) // (ADC) ADC Last Converted Data Register
-#define AT91C_ADC_IDR   ((AT91_REG *) 	0xFFFD8028) // (ADC) ADC Interrupt Disable Register
-#define AT91C_ADC_CR    ((AT91_REG *) 	0xFFFD8000) // (ADC) ADC Control Register
-#define AT91C_ADC_CDR7  ((AT91_REG *) 	0xFFFD804C) // (ADC) ADC Channel Data Register 7
-#define AT91C_ADC_CDR6  ((AT91_REG *) 	0xFFFD8048) // (ADC) ADC Channel Data Register 6
-#define AT91C_ADC_IER   ((AT91_REG *) 	0xFFFD8024) // (ADC) ADC Interrupt Enable Register
-#define AT91C_ADC_CHER  ((AT91_REG *) 	0xFFFD8010) // (ADC) ADC Channel Enable Register
-#define AT91C_ADC_CHSR  ((AT91_REG *) 	0xFFFD8018) // (ADC) ADC Channel Status Register
-#define AT91C_ADC_MR    ((AT91_REG *) 	0xFFFD8004) // (ADC) ADC Mode Register
-#define AT91C_ADC_IMR   ((AT91_REG *) 	0xFFFD802C) // (ADC) ADC Interrupt Mask Register
-// ========== Register definition for PDC_AES peripheral ========== 
-#define AT91C_AES_TPR   ((AT91_REG *) 	0xFFFA4108) // (PDC_AES) Transmit Pointer Register
-#define AT91C_AES_PTCR  ((AT91_REG *) 	0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
-#define AT91C_AES_RNPR  ((AT91_REG *) 	0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
-#define AT91C_AES_TNCR  ((AT91_REG *) 	0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
-#define AT91C_AES_TCR   ((AT91_REG *) 	0xFFFA410C) // (PDC_AES) Transmit Counter Register
-#define AT91C_AES_RCR   ((AT91_REG *) 	0xFFFA4104) // (PDC_AES) Receive Counter Register
-#define AT91C_AES_RNCR  ((AT91_REG *) 	0xFFFA4114) // (PDC_AES) Receive Next Counter Register
-#define AT91C_AES_TNPR  ((AT91_REG *) 	0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
-#define AT91C_AES_RPR   ((AT91_REG *) 	0xFFFA4100) // (PDC_AES) Receive Pointer Register
-#define AT91C_AES_PTSR  ((AT91_REG *) 	0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
-// ========== Register definition for AES peripheral ========== 
-#define AT91C_AES_IVxR  ((AT91_REG *) 	0xFFFA4060) // (AES) Initialization Vector x Register
-#define AT91C_AES_MR    ((AT91_REG *) 	0xFFFA4004) // (AES) Mode Register
-#define AT91C_AES_VR    ((AT91_REG *) 	0xFFFA40FC) // (AES) AES Version Register
-#define AT91C_AES_ODATAxR ((AT91_REG *) 	0xFFFA4050) // (AES) Output Data x Register
-#define AT91C_AES_IDATAxR ((AT91_REG *) 	0xFFFA4040) // (AES) Input Data x Register
-#define AT91C_AES_CR    ((AT91_REG *) 	0xFFFA4000) // (AES) Control Register
-#define AT91C_AES_IDR   ((AT91_REG *) 	0xFFFA4014) // (AES) Interrupt Disable Register
-#define AT91C_AES_IMR   ((AT91_REG *) 	0xFFFA4018) // (AES) Interrupt Mask Register
-#define AT91C_AES_IER   ((AT91_REG *) 	0xFFFA4010) // (AES) Interrupt Enable Register
-#define AT91C_AES_KEYWxR ((AT91_REG *) 	0xFFFA4020) // (AES) Key Word x Register
-#define AT91C_AES_ISR   ((AT91_REG *) 	0xFFFA401C) // (AES) Interrupt Status Register
-// ========== Register definition for PDC_TDES peripheral ========== 
-#define AT91C_TDES_RNCR ((AT91_REG *) 	0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
-#define AT91C_TDES_TCR  ((AT91_REG *) 	0xFFFA810C) // (PDC_TDES) Transmit Counter Register
-#define AT91C_TDES_RCR  ((AT91_REG *) 	0xFFFA8104) // (PDC_TDES) Receive Counter Register
-#define AT91C_TDES_TNPR ((AT91_REG *) 	0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
-#define AT91C_TDES_RNPR ((AT91_REG *) 	0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
-#define AT91C_TDES_RPR  ((AT91_REG *) 	0xFFFA8100) // (PDC_TDES) Receive Pointer Register
-#define AT91C_TDES_TNCR ((AT91_REG *) 	0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
-#define AT91C_TDES_TPR  ((AT91_REG *) 	0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
-#define AT91C_TDES_PTSR ((AT91_REG *) 	0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
-#define AT91C_TDES_PTCR ((AT91_REG *) 	0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
-// ========== Register definition for TDES peripheral ========== 
-#define AT91C_TDES_KEY2WxR ((AT91_REG *) 	0xFFFA8028) // (TDES) Key 2 Word x Register
-#define AT91C_TDES_KEY3WxR ((AT91_REG *) 	0xFFFA8030) // (TDES) Key 3 Word x Register
-#define AT91C_TDES_IDR  ((AT91_REG *) 	0xFFFA8014) // (TDES) Interrupt Disable Register
-#define AT91C_TDES_VR   ((AT91_REG *) 	0xFFFA80FC) // (TDES) TDES Version Register
-#define AT91C_TDES_IVxR ((AT91_REG *) 	0xFFFA8060) // (TDES) Initialization Vector x Register
-#define AT91C_TDES_ODATAxR ((AT91_REG *) 	0xFFFA8050) // (TDES) Output Data x Register
-#define AT91C_TDES_IMR  ((AT91_REG *) 	0xFFFA8018) // (TDES) Interrupt Mask Register
-#define AT91C_TDES_MR   ((AT91_REG *) 	0xFFFA8004) // (TDES) Mode Register
-#define AT91C_TDES_CR   ((AT91_REG *) 	0xFFFA8000) // (TDES) Control Register
-#define AT91C_TDES_IER  ((AT91_REG *) 	0xFFFA8010) // (TDES) Interrupt Enable Register
-#define AT91C_TDES_ISR  ((AT91_REG *) 	0xFFFA801C) // (TDES) Interrupt Status Register
-#define AT91C_TDES_IDATAxR ((AT91_REG *) 	0xFFFA8040) // (TDES) Input Data x Register
-#define AT91C_TDES_KEY1WxR ((AT91_REG *) 	0xFFFA8020) // (TDES) Key 1 Word x Register
-
-// *****************************************************************************
-//               PIO DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_PIO_PA0        ((unsigned int) 1 <<  0) // Pin Controlled by PA0
-#define AT91C_PA0_RXD0     ((unsigned int) AT91C_PIO_PA0) //  USART 0 Receive Data
-#define AT91C_PIO_PA1        ((unsigned int) 1 <<  1) // Pin Controlled by PA1
-#define AT91C_PA1_TXD0     ((unsigned int) AT91C_PIO_PA1) //  USART 0 Transmit Data
-#define AT91C_PIO_PA10       ((unsigned int) 1 << 10) // Pin Controlled by PA10
-#define AT91C_PA10_TWD      ((unsigned int) AT91C_PIO_PA10) //  TWI Two-wire Serial Data
-#define AT91C_PIO_PA11       ((unsigned int) 1 << 11) // Pin Controlled by PA11
-#define AT91C_PA11_TWCK     ((unsigned int) AT91C_PIO_PA11) //  TWI Two-wire Serial Clock
-#define AT91C_PIO_PA12       ((unsigned int) 1 << 12) // Pin Controlled by PA12
-#define AT91C_PA12_NPCS00   ((unsigned int) AT91C_PIO_PA12) //  SPI 0 Peripheral Chip Select 0
-#define AT91C_PIO_PA13       ((unsigned int) 1 << 13) // Pin Controlled by PA13
-#define AT91C_PA13_NPCS01   ((unsigned int) AT91C_PIO_PA13) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PA13_PCK1     ((unsigned int) AT91C_PIO_PA13) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PA14       ((unsigned int) 1 << 14) // Pin Controlled by PA14
-#define AT91C_PA14_NPCS02   ((unsigned int) AT91C_PIO_PA14) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PA14_IRQ1     ((unsigned int) AT91C_PIO_PA14) //  External Interrupt 1
-#define AT91C_PIO_PA15       ((unsigned int) 1 << 15) // Pin Controlled by PA15
-#define AT91C_PA15_NPCS03   ((unsigned int) AT91C_PIO_PA15) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PA15_TCLK2    ((unsigned int) AT91C_PIO_PA15) //  Timer Counter 2 external clock input
-#define AT91C_PIO_PA16       ((unsigned int) 1 << 16) // Pin Controlled by PA16
-#define AT91C_PA16_MISO0    ((unsigned int) AT91C_PIO_PA16) //  SPI 0 Master In Slave
-#define AT91C_PIO_PA17       ((unsigned int) 1 << 17) // Pin Controlled by PA17
-#define AT91C_PA17_MOSI0    ((unsigned int) AT91C_PIO_PA17) //  SPI 0 Master Out Slave
-#define AT91C_PIO_PA18       ((unsigned int) 1 << 18) // Pin Controlled by PA18
-#define AT91C_PA18_SPCK0    ((unsigned int) AT91C_PIO_PA18) //  SPI 0 Serial Clock
-#define AT91C_PIO_PA19       ((unsigned int) 1 << 19) // Pin Controlled by PA19
-#define AT91C_PA19_CANRX    ((unsigned int) AT91C_PIO_PA19) //  CAN Receive
-#define AT91C_PIO_PA2        ((unsigned int) 1 <<  2) // Pin Controlled by PA2
-#define AT91C_PA2_SCK0     ((unsigned int) AT91C_PIO_PA2) //  USART 0 Serial Clock
-#define AT91C_PA2_NPCS11   ((unsigned int) AT91C_PIO_PA2) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA20       ((unsigned int) 1 << 20) // Pin Controlled by PA20
-#define AT91C_PA20_CANTX    ((unsigned int) AT91C_PIO_PA20) //  CAN Transmit
-#define AT91C_PIO_PA21       ((unsigned int) 1 << 21) // Pin Controlled by PA21
-#define AT91C_PA21_TF       ((unsigned int) AT91C_PIO_PA21) //  SSC Transmit Frame Sync
-#define AT91C_PA21_NPCS10   ((unsigned int) AT91C_PIO_PA21) //  SPI 1 Peripheral Chip Select 0
-#define AT91C_PIO_PA22       ((unsigned int) 1 << 22) // Pin Controlled by PA22
-#define AT91C_PA22_TK       ((unsigned int) AT91C_PIO_PA22) //  SSC Transmit Clock
-#define AT91C_PA22_SPCK1    ((unsigned int) AT91C_PIO_PA22) //  SPI 1 Serial Clock
-#define AT91C_PIO_PA23       ((unsigned int) 1 << 23) // Pin Controlled by PA23
-#define AT91C_PA23_TD       ((unsigned int) AT91C_PIO_PA23) //  SSC Transmit data
-#define AT91C_PA23_MOSI1    ((unsigned int) AT91C_PIO_PA23) //  SPI 1 Master Out Slave
-#define AT91C_PIO_PA24       ((unsigned int) 1 << 24) // Pin Controlled by PA24
-#define AT91C_PA24_RD       ((unsigned int) AT91C_PIO_PA24) //  SSC Receive Data
-#define AT91C_PA24_MISO1    ((unsigned int) AT91C_PIO_PA24) //  SPI 1 Master In Slave
-#define AT91C_PIO_PA25       ((unsigned int) 1 << 25) // Pin Controlled by PA25
-#define AT91C_PA25_RK       ((unsigned int) AT91C_PIO_PA25) //  SSC Receive Clock
-#define AT91C_PA25_NPCS11   ((unsigned int) AT91C_PIO_PA25) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA26       ((unsigned int) 1 << 26) // Pin Controlled by PA26
-#define AT91C_PA26_RF       ((unsigned int) AT91C_PIO_PA26) //  SSC Receive Frame Sync
-#define AT91C_PA26_NPCS12   ((unsigned int) AT91C_PIO_PA26) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA27       ((unsigned int) 1 << 27) // Pin Controlled by PA27
-#define AT91C_PA27_DRXD     ((unsigned int) AT91C_PIO_PA27) //  DBGU Debug Receive Data
-#define AT91C_PA27_PCK3     ((unsigned int) AT91C_PIO_PA27) //  PMC Programmable Clock Output 3
-#define AT91C_PIO_PA28       ((unsigned int) 1 << 28) // Pin Controlled by PA28
-#define AT91C_PA28_DTXD     ((unsigned int) AT91C_PIO_PA28) //  DBGU Debug Transmit Data
-#define AT91C_PIO_PA29       ((unsigned int) 1 << 29) // Pin Controlled by PA29
-#define AT91C_PA29_FIQ      ((unsigned int) AT91C_PIO_PA29) //  AIC Fast Interrupt Input
-#define AT91C_PA29_NPCS13   ((unsigned int) AT91C_PIO_PA29) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA3        ((unsigned int) 1 <<  3) // Pin Controlled by PA3
-#define AT91C_PA3_RTS0     ((unsigned int) AT91C_PIO_PA3) //  USART 0 Ready To Send
-#define AT91C_PA3_NPCS12   ((unsigned int) AT91C_PIO_PA3) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA30       ((unsigned int) 1 << 30) // Pin Controlled by PA30
-#define AT91C_PA30_IRQ0     ((unsigned int) AT91C_PIO_PA30) //  External Interrupt 0
-#define AT91C_PA30_PCK2     ((unsigned int) AT91C_PIO_PA30) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PA4        ((unsigned int) 1 <<  4) // Pin Controlled by PA4
-#define AT91C_PA4_CTS0     ((unsigned int) AT91C_PIO_PA4) //  USART 0 Clear To Send
-#define AT91C_PA4_NPCS13   ((unsigned int) AT91C_PIO_PA4) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA5        ((unsigned int) 1 <<  5) // Pin Controlled by PA5
-#define AT91C_PA5_RXD1     ((unsigned int) AT91C_PIO_PA5) //  USART 1 Receive Data
-#define AT91C_PIO_PA6        ((unsigned int) 1 <<  6) // Pin Controlled by PA6
-#define AT91C_PA6_TXD1     ((unsigned int) AT91C_PIO_PA6) //  USART 1 Transmit Data
-#define AT91C_PIO_PA7        ((unsigned int) 1 <<  7) // Pin Controlled by PA7
-#define AT91C_PA7_SCK1     ((unsigned int) AT91C_PIO_PA7) //  USART 1 Serial Clock
-#define AT91C_PA7_NPCS01   ((unsigned int) AT91C_PIO_PA7) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PA8        ((unsigned int) 1 <<  8) // Pin Controlled by PA8
-#define AT91C_PA8_RTS1     ((unsigned int) AT91C_PIO_PA8) //  USART 1 Ready To Send
-#define AT91C_PA8_NPCS02   ((unsigned int) AT91C_PIO_PA8) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PA9        ((unsigned int) 1 <<  9) // Pin Controlled by PA9
-#define AT91C_PA9_CTS1     ((unsigned int) AT91C_PIO_PA9) //  USART 1 Clear To Send
-#define AT91C_PA9_NPCS03   ((unsigned int) AT91C_PIO_PA9) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB0        ((unsigned int) 1 <<  0) // Pin Controlled by PB0
-#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) //  Ethernet MAC Transmit Clock/Reference Clock
-#define AT91C_PB0_PCK0     ((unsigned int) AT91C_PIO_PB0) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PB1        ((unsigned int) 1 <<  1) // Pin Controlled by PB1
-#define AT91C_PB1_ETXEN    ((unsigned int) AT91C_PIO_PB1) //  Ethernet MAC Transmit Enable
-#define AT91C_PIO_PB10       ((unsigned int) 1 << 10) // Pin Controlled by PB10
-#define AT91C_PB10_ETX2     ((unsigned int) AT91C_PIO_PB10) //  Ethernet MAC Transmit Data 2
-#define AT91C_PB10_NPCS11   ((unsigned int) AT91C_PIO_PB10) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PB11       ((unsigned int) 1 << 11) // Pin Controlled by PB11
-#define AT91C_PB11_ETX3     ((unsigned int) AT91C_PIO_PB11) //  Ethernet MAC Transmit Data 3
-#define AT91C_PB11_NPCS12   ((unsigned int) AT91C_PIO_PB11) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PB12       ((unsigned int) 1 << 12) // Pin Controlled by PB12
-#define AT91C_PB12_ETXER    ((unsigned int) AT91C_PIO_PB12) //  Ethernet MAC Transmikt Coding Error
-#define AT91C_PB12_TCLK0    ((unsigned int) AT91C_PIO_PB12) //  Timer Counter 0 external clock input
-#define AT91C_PIO_PB13       ((unsigned int) 1 << 13) // Pin Controlled by PB13
-#define AT91C_PB13_ERX2     ((unsigned int) AT91C_PIO_PB13) //  Ethernet MAC Receive Data 2
-#define AT91C_PB13_NPCS01   ((unsigned int) AT91C_PIO_PB13) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PB14       ((unsigned int) 1 << 14) // Pin Controlled by PB14
-#define AT91C_PB14_ERX3     ((unsigned int) AT91C_PIO_PB14) //  Ethernet MAC Receive Data 3
-#define AT91C_PB14_NPCS02   ((unsigned int) AT91C_PIO_PB14) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PB15       ((unsigned int) 1 << 15) // Pin Controlled by PB15
-#define AT91C_PB15_ERXDV    ((unsigned int) AT91C_PIO_PB15) //  Ethernet MAC Receive Data Valid
-#define AT91C_PIO_PB16       ((unsigned int) 1 << 16) // Pin Controlled by PB16
-#define AT91C_PB16_ECOL     ((unsigned int) AT91C_PIO_PB16) //  Ethernet MAC Collision Detected
-#define AT91C_PB16_NPCS13   ((unsigned int) AT91C_PIO_PB16) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PB17       ((unsigned int) 1 << 17) // Pin Controlled by PB17
-#define AT91C_PB17_ERXCK    ((unsigned int) AT91C_PIO_PB17) //  Ethernet MAC Receive Clock
-#define AT91C_PB17_NPCS03   ((unsigned int) AT91C_PIO_PB17) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB18       ((unsigned int) 1 << 18) // Pin Controlled by PB18
-#define AT91C_PB18_EF100    ((unsigned int) AT91C_PIO_PB18) //  Ethernet MAC Force 100 Mbits/sec
-#define AT91C_PB18_ADTRG    ((unsigned int) AT91C_PIO_PB18) //  ADC External Trigger
-#define AT91C_PIO_PB19       ((unsigned int) 1 << 19) // Pin Controlled by PB19
-#define AT91C_PB19_PWM0     ((unsigned int) AT91C_PIO_PB19) //  PWM Channel 0
-#define AT91C_PB19_TCLK1    ((unsigned int) AT91C_PIO_PB19) //  Timer Counter 1 external clock input
-#define AT91C_PIO_PB2        ((unsigned int) 1 <<  2) // Pin Controlled by PB2
-#define AT91C_PB2_ETX0     ((unsigned int) AT91C_PIO_PB2) //  Ethernet MAC Transmit Data 0
-#define AT91C_PIO_PB20       ((unsigned int) 1 << 20) // Pin Controlled by PB20
-#define AT91C_PB20_PWM1     ((unsigned int) AT91C_PIO_PB20) //  PWM Channel 1
-#define AT91C_PB20_PCK0     ((unsigned int) AT91C_PIO_PB20) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PB21       ((unsigned int) 1 << 21) // Pin Controlled by PB21
-#define AT91C_PB21_PWM2     ((unsigned int) AT91C_PIO_PB21) //  PWM Channel 2
-#define AT91C_PB21_PCK1     ((unsigned int) AT91C_PIO_PB21) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PB22       ((unsigned int) 1 << 22) // Pin Controlled by PB22
-#define AT91C_PB22_PWM3     ((unsigned int) AT91C_PIO_PB22) //  PWM Channel 3
-#define AT91C_PB22_PCK2     ((unsigned int) AT91C_PIO_PB22) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PB23       ((unsigned int) 1 << 23) // Pin Controlled by PB23
-#define AT91C_PB23_TIOA0    ((unsigned int) AT91C_PIO_PB23) //  Timer Counter 0 Multipurpose Timer I/O Pin A
-#define AT91C_PB23_DCD1     ((unsigned int) AT91C_PIO_PB23) //  USART 1 Data Carrier Detect
-#define AT91C_PIO_PB24       ((unsigned int) 1 << 24) // Pin Controlled by PB24
-#define AT91C_PB24_TIOB0    ((unsigned int) AT91C_PIO_PB24) //  Timer Counter 0 Multipurpose Timer I/O Pin B
-#define AT91C_PB24_DSR1     ((unsigned int) AT91C_PIO_PB24) //  USART 1 Data Set ready
-#define AT91C_PIO_PB25       ((unsigned int) 1 << 25) // Pin Controlled by PB25
-#define AT91C_PB25_TIOA1    ((unsigned int) AT91C_PIO_PB25) //  Timer Counter 1 Multipurpose Timer I/O Pin A
-#define AT91C_PB25_DTR1     ((unsigned int) AT91C_PIO_PB25) //  USART 1 Data Terminal ready
-#define AT91C_PIO_PB26       ((unsigned int) 1 << 26) // Pin Controlled by PB26
-#define AT91C_PB26_TIOB1    ((unsigned int) AT91C_PIO_PB26) //  Timer Counter 1 Multipurpose Timer I/O Pin B
-#define AT91C_PB26_RI1      ((unsigned int) AT91C_PIO_PB26) //  USART 1 Ring Indicator
-#define AT91C_PIO_PB27       ((unsigned int) 1 << 27) // Pin Controlled by PB27
-#define AT91C_PB27_TIOA2    ((unsigned int) AT91C_PIO_PB27) //  Timer Counter 2 Multipurpose Timer I/O Pin A
-#define AT91C_PB27_PWM0     ((unsigned int) AT91C_PIO_PB27) //  PWM Channel 0
-#define AT91C_PIO_PB28       ((unsigned int) 1 << 28) // Pin Controlled by PB28
-#define AT91C_PB28_TIOB2    ((unsigned int) AT91C_PIO_PB28) //  Timer Counter 2 Multipurpose Timer I/O Pin B
-#define AT91C_PB28_PWM1     ((unsigned int) AT91C_PIO_PB28) //  PWM Channel 1
-#define AT91C_PIO_PB29       ((unsigned int) 1 << 29) // Pin Controlled by PB29
-#define AT91C_PB29_PCK1     ((unsigned int) AT91C_PIO_PB29) //  PMC Programmable Clock Output 1
-#define AT91C_PB29_PWM2     ((unsigned int) AT91C_PIO_PB29) //  PWM Channel 2
-#define AT91C_PIO_PB3        ((unsigned int) 1 <<  3) // Pin Controlled by PB3
-#define AT91C_PB3_ETX1     ((unsigned int) AT91C_PIO_PB3) //  Ethernet MAC Transmit Data 1
-#define AT91C_PIO_PB30       ((unsigned int) 1 << 30) // Pin Controlled by PB30
-#define AT91C_PB30_PCK2     ((unsigned int) AT91C_PIO_PB30) //  PMC Programmable Clock Output 2
-#define AT91C_PB30_PWM3     ((unsigned int) AT91C_PIO_PB30) //  PWM Channel 3
-#define AT91C_PIO_PB4        ((unsigned int) 1 <<  4) // Pin Controlled by PB4
-#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
-#define AT91C_PIO_PB5        ((unsigned int) 1 <<  5) // Pin Controlled by PB5
-#define AT91C_PB5_ERX0     ((unsigned int) AT91C_PIO_PB5) //  Ethernet MAC Receive Data 0
-#define AT91C_PIO_PB6        ((unsigned int) 1 <<  6) // Pin Controlled by PB6
-#define AT91C_PB6_ERX1     ((unsigned int) AT91C_PIO_PB6) //  Ethernet MAC Receive Data 1
-#define AT91C_PIO_PB7        ((unsigned int) 1 <<  7) // Pin Controlled by PB7
-#define AT91C_PB7_ERXER    ((unsigned int) AT91C_PIO_PB7) //  Ethernet MAC Receive Error
-#define AT91C_PIO_PB8        ((unsigned int) 1 <<  8) // Pin Controlled by PB8
-#define AT91C_PB8_EMDC     ((unsigned int) AT91C_PIO_PB8) //  Ethernet MAC Management Data Clock
-#define AT91C_PIO_PB9        ((unsigned int) 1 <<  9) // Pin Controlled by PB9
-#define AT91C_PB9_EMDIO    ((unsigned int) AT91C_PIO_PB9) //  Ethernet MAC Management Data Input/Output
-
-// *****************************************************************************
-//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_ID_FIQ    ((unsigned int)  0) // Advanced Interrupt Controller (FIQ)
-#define AT91C_ID_SYS    ((unsigned int)  1) // System Peripheral
-#define AT91C_ID_PIOA   ((unsigned int)  2) // Parallel IO Controller A
-#define AT91C_ID_PIOB   ((unsigned int)  3) // Parallel IO Controller B
-#define AT91C_ID_SPI0   ((unsigned int)  4) // Serial Peripheral Interface 0
-#define AT91C_ID_SPI1   ((unsigned int)  5) // Serial Peripheral Interface 1
-#define AT91C_ID_US0    ((unsigned int)  6) // USART 0
-#define AT91C_ID_US1    ((unsigned int)  7) // USART 1
-#define AT91C_ID_SSC    ((unsigned int)  8) // Serial Synchronous Controller
-#define AT91C_ID_TWI    ((unsigned int)  9) // Two-Wire Interface
-#define AT91C_ID_PWMC   ((unsigned int) 10) // PWM Controller
-#define AT91C_ID_UDP    ((unsigned int) 11) // USB Device Port
-#define AT91C_ID_TC0    ((unsigned int) 12) // Timer Counter 0
-#define AT91C_ID_TC1    ((unsigned int) 13) // Timer Counter 1
-#define AT91C_ID_TC2    ((unsigned int) 14) // Timer Counter 2
-#define AT91C_ID_CAN    ((unsigned int) 15) // Control Area Network Controller
-#define AT91C_ID_EMAC   ((unsigned int) 16) // Ethernet MAC
-#define AT91C_ID_ADC    ((unsigned int) 17) // Analog-to-Digital Converter
-#define AT91C_ID_AES    ((unsigned int) 18) // Advanced Encryption Standard 128-bit
-#define AT91C_ID_TDES   ((unsigned int) 19) // Triple Data Encryption Standard
-#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
-#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
-#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
-#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
-#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
-#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
-#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
-#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
-#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
-#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
-#define AT91C_ID_IRQ0   ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
-#define AT91C_ID_IRQ1   ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
-
-// *****************************************************************************
-//               BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_BASE_SYS       ((AT91PS_SYS) 	0xFFFFF000) // (SYS) Base Address
-#define AT91C_BASE_AIC       ((AT91PS_AIC) 	0xFFFFF000) // (AIC) Base Address
-#define AT91C_BASE_PDC_DBGU  ((AT91PS_PDC) 	0xFFFFF300) // (PDC_DBGU) Base Address
-#define AT91C_BASE_DBGU      ((AT91PS_DBGU) 	0xFFFFF200) // (DBGU) Base Address
-#define AT91C_BASE_PIOA      ((AT91PS_PIO) 	0xFFFFF400) // (PIOA) Base Address
-#define AT91C_BASE_PIOB      ((AT91PS_PIO) 	0xFFFFF600) // (PIOB) Base Address
-#define AT91C_BASE_CKGR      ((AT91PS_CKGR) 	0xFFFFFC20) // (CKGR) Base Address
-#define AT91C_BASE_PMC       ((AT91PS_PMC) 	0xFFFFFC00) // (PMC) Base Address
-#define AT91C_BASE_RSTC      ((AT91PS_RSTC) 	0xFFFFFD00) // (RSTC) Base Address
-#define AT91C_BASE_RTTC      ((AT91PS_RTTC) 	0xFFFFFD20) // (RTTC) Base Address
-#define AT91C_BASE_PITC      ((AT91PS_PITC) 	0xFFFFFD30) // (PITC) Base Address
-#define AT91C_BASE_WDTC      ((AT91PS_WDTC) 	0xFFFFFD40) // (WDTC) Base Address
-#define AT91C_BASE_VREG      ((AT91PS_VREG) 	0xFFFFFD60) // (VREG) Base Address
-#define AT91C_BASE_MC        ((AT91PS_MC) 	0xFFFFFF00) // (MC) Base Address
-#define AT91C_BASE_PDC_SPI1  ((AT91PS_PDC) 	0xFFFE4100) // (PDC_SPI1) Base Address
-#define AT91C_BASE_SPI1      ((AT91PS_SPI) 	0xFFFE4000) // (SPI1) Base Address
-#define AT91C_BASE_PDC_SPI0  ((AT91PS_PDC) 	0xFFFE0100) // (PDC_SPI0) Base Address
-#define AT91C_BASE_SPI0      ((AT91PS_SPI) 	0xFFFE0000) // (SPI0) Base Address
-#define AT91C_BASE_PDC_US1   ((AT91PS_PDC) 	0xFFFC4100) // (PDC_US1) Base Address
-#define AT91C_BASE_US1       ((AT91PS_USART) 	0xFFFC4000) // (US1) Base Address
-#define AT91C_BASE_PDC_US0   ((AT91PS_PDC) 	0xFFFC0100) // (PDC_US0) Base Address
-#define AT91C_BASE_US0       ((AT91PS_USART) 	0xFFFC0000) // (US0) Base Address
-#define AT91C_BASE_PDC_SSC   ((AT91PS_PDC) 	0xFFFD4100) // (PDC_SSC) Base Address
-#define AT91C_BASE_SSC       ((AT91PS_SSC) 	0xFFFD4000) // (SSC) Base Address
-#define AT91C_BASE_TWI       ((AT91PS_TWI) 	0xFFFB8000) // (TWI) Base Address
-#define AT91C_BASE_PWMC_CH3  ((AT91PS_PWMC_CH) 	0xFFFCC260) // (PWMC_CH3) Base Address
-#define AT91C_BASE_PWMC_CH2  ((AT91PS_PWMC_CH) 	0xFFFCC240) // (PWMC_CH2) Base Address
-#define AT91C_BASE_PWMC_CH1  ((AT91PS_PWMC_CH) 	0xFFFCC220) // (PWMC_CH1) Base Address
-#define AT91C_BASE_PWMC_CH0  ((AT91PS_PWMC_CH) 	0xFFFCC200) // (PWMC_CH0) Base Address
-#define AT91C_BASE_PWMC      ((AT91PS_PWMC) 	0xFFFCC000) // (PWMC) Base Address
-#define AT91C_BASE_UDP       ((AT91PS_UDP) 	0xFFFB0000) // (UDP) Base Address
-#define AT91C_BASE_TC0       ((AT91PS_TC) 	0xFFFA0000) // (TC0) Base Address
-#define AT91C_BASE_TC1       ((AT91PS_TC) 	0xFFFA0040) // (TC1) Base Address
-#define AT91C_BASE_TC2       ((AT91PS_TC) 	0xFFFA0080) // (TC2) Base Address
-#define AT91C_BASE_TCB       ((AT91PS_TCB) 	0xFFFA0000) // (TCB) Base Address
-#define AT91C_BASE_CAN_MB0   ((AT91PS_CAN_MB) 	0xFFFD0200) // (CAN_MB0) Base Address
-#define AT91C_BASE_CAN_MB1   ((AT91PS_CAN_MB) 	0xFFFD0220) // (CAN_MB1) Base Address
-#define AT91C_BASE_CAN_MB2   ((AT91PS_CAN_MB) 	0xFFFD0240) // (CAN_MB2) Base Address
-#define AT91C_BASE_CAN_MB3   ((AT91PS_CAN_MB) 	0xFFFD0260) // (CAN_MB3) Base Address
-#define AT91C_BASE_CAN_MB4   ((AT91PS_CAN_MB) 	0xFFFD0280) // (CAN_MB4) Base Address
-#define AT91C_BASE_CAN_MB5   ((AT91PS_CAN_MB) 	0xFFFD02A0) // (CAN_MB5) Base Address
-#define AT91C_BASE_CAN_MB6   ((AT91PS_CAN_MB) 	0xFFFD02C0) // (CAN_MB6) Base Address
-#define AT91C_BASE_CAN_MB7   ((AT91PS_CAN_MB) 	0xFFFD02E0) // (CAN_MB7) Base Address
-#define AT91C_BASE_CAN       ((AT91PS_CAN) 	0xFFFD0000) // (CAN) Base Address
-#define AT91C_BASE_EMAC      ((AT91PS_EMAC) 	0xFFFDC000) // (EMAC) Base Address
-#define AT91C_BASE_PDC_ADC   ((AT91PS_PDC) 	0xFFFD8100) // (PDC_ADC) Base Address
-#define AT91C_BASE_ADC       ((AT91PS_ADC) 	0xFFFD8000) // (ADC) Base Address
-#define AT91C_BASE_PDC_AES   ((AT91PS_PDC) 	0xFFFA4100) // (PDC_AES) Base Address
-#define AT91C_BASE_AES       ((AT91PS_AES) 	0xFFFA4000) // (AES) Base Address
-#define AT91C_BASE_PDC_TDES  ((AT91PS_PDC) 	0xFFFA8100) // (PDC_TDES) Base Address
-#define AT91C_BASE_TDES      ((AT91PS_TDES) 	0xFFFA8000) // (TDES) Base Address
-
-// *****************************************************************************
-//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_ISRAM	 ((char *) 	0x00200000) // Internal SRAM base address
-#define AT91C_ISRAM_SIZE	 ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte)
-#define AT91C_IFLASH	 ((char *) 	0x00100000) // Internal ROM base address
-#define AT91C_IFLASH_SIZE	 ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte)
-#endif /* __IAR_SYSTEMS_ICC__ */
-
-#ifdef __IAR_SYSTEMS_ASM__
-
-// - Hardware register definition
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR System Peripherals
-// - *****************************************************************************
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
-// - *****************************************************************************
-// - -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
-AT91C_AIC_PRIOR           EQU (0x7 <<  0) ;- (AIC) Priority Level
-AT91C_AIC_PRIOR_LOWEST    EQU (0x0) ;- (AIC) Lowest priority level
-AT91C_AIC_PRIOR_HIGHEST   EQU (0x7) ;- (AIC) Highest priority level
-AT91C_AIC_SRCTYPE         EQU (0x3 <<  5) ;- (AIC) Interrupt Source Type
-AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL EQU (0x0 <<  5) ;- (AIC) Internal Sources Code Label High-level Sensitive
-AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL EQU (0x0 <<  5) ;- (AIC) External Sources Code Label Low-level Sensitive
-AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE EQU (0x1 <<  5) ;- (AIC) Internal Sources Code Label Positive Edge triggered
-AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE EQU (0x1 <<  5) ;- (AIC) External Sources Code Label Negative Edge triggered
-AT91C_AIC_SRCTYPE_HIGH_LEVEL EQU (0x2 <<  5) ;- (AIC) Internal Or External Sources Code Label High-level Sensitive
-AT91C_AIC_SRCTYPE_POSITIVE_EDGE EQU (0x3 <<  5) ;- (AIC) Internal Or External Sources Code Label Positive Edge triggered
-// - -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
-AT91C_AIC_NFIQ            EQU (0x1 <<  0) ;- (AIC) NFIQ Status
-AT91C_AIC_NIRQ            EQU (0x1 <<  1) ;- (AIC) NIRQ Status
-// - -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
-AT91C_AIC_DCR_PROT        EQU (0x1 <<  0) ;- (AIC) Protection Mode
-AT91C_AIC_DCR_GMSK        EQU (0x1 <<  1) ;- (AIC) General Mask
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
-// - *****************************************************************************
-// - -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
-AT91C_PDC_RXTEN           EQU (0x1 <<  0) ;- (PDC) Receiver Transfer Enable
-AT91C_PDC_RXTDIS          EQU (0x1 <<  1) ;- (PDC) Receiver Transfer Disable
-AT91C_PDC_TXTEN           EQU (0x1 <<  8) ;- (PDC) Transmitter Transfer Enable
-AT91C_PDC_TXTDIS          EQU (0x1 <<  9) ;- (PDC) Transmitter Transfer Disable
-// - -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Debug Unit
-// - *****************************************************************************
-// - -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
-AT91C_US_RSTRX            EQU (0x1 <<  2) ;- (DBGU) Reset Receiver
-AT91C_US_RSTTX            EQU (0x1 <<  3) ;- (DBGU) Reset Transmitter
-AT91C_US_RXEN             EQU (0x1 <<  4) ;- (DBGU) Receiver Enable
-AT91C_US_RXDIS            EQU (0x1 <<  5) ;- (DBGU) Receiver Disable
-AT91C_US_TXEN             EQU (0x1 <<  6) ;- (DBGU) Transmitter Enable
-AT91C_US_TXDIS            EQU (0x1 <<  7) ;- (DBGU) Transmitter Disable
-AT91C_US_RSTSTA           EQU (0x1 <<  8) ;- (DBGU) Reset Status Bits
-// - -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
-AT91C_US_PAR              EQU (0x7 <<  9) ;- (DBGU) Parity type
-AT91C_US_PAR_EVEN         EQU (0x0 <<  9) ;- (DBGU) Even Parity
-AT91C_US_PAR_ODD          EQU (0x1 <<  9) ;- (DBGU) Odd Parity
-AT91C_US_PAR_SPACE        EQU (0x2 <<  9) ;- (DBGU) Parity forced to 0 (Space)
-AT91C_US_PAR_MARK         EQU (0x3 <<  9) ;- (DBGU) Parity forced to 1 (Mark)
-AT91C_US_PAR_NONE         EQU (0x4 <<  9) ;- (DBGU) No Parity
-AT91C_US_PAR_MULTI_DROP   EQU (0x6 <<  9) ;- (DBGU) Multi-drop mode
-AT91C_US_CHMODE           EQU (0x3 << 14) ;- (DBGU) Channel Mode
-AT91C_US_CHMODE_NORMAL    EQU (0x0 << 14) ;- (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-AT91C_US_CHMODE_AUTO      EQU (0x1 << 14) ;- (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-AT91C_US_CHMODE_LOCAL     EQU (0x2 << 14) ;- (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-AT91C_US_CHMODE_REMOTE    EQU (0x3 << 14) ;- (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-// - -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
-AT91C_US_RXRDY            EQU (0x1 <<  0) ;- (DBGU) RXRDY Interrupt
-AT91C_US_TXRDY            EQU (0x1 <<  1) ;- (DBGU) TXRDY Interrupt
-AT91C_US_ENDRX            EQU (0x1 <<  3) ;- (DBGU) End of Receive Transfer Interrupt
-AT91C_US_ENDTX            EQU (0x1 <<  4) ;- (DBGU) End of Transmit Interrupt
-AT91C_US_OVRE             EQU (0x1 <<  5) ;- (DBGU) Overrun Interrupt
-AT91C_US_FRAME            EQU (0x1 <<  6) ;- (DBGU) Framing Error Interrupt
-AT91C_US_PARE             EQU (0x1 <<  7) ;- (DBGU) Parity Error Interrupt
-AT91C_US_TXEMPTY          EQU (0x1 <<  9) ;- (DBGU) TXEMPTY Interrupt
-AT91C_US_TXBUFE           EQU (0x1 << 11) ;- (DBGU) TXBUFE Interrupt
-AT91C_US_RXBUFF           EQU (0x1 << 12) ;- (DBGU) RXBUFF Interrupt
-AT91C_US_COMM_TX          EQU (0x1 << 30) ;- (DBGU) COMM_TX Interrupt
-AT91C_US_COMM_RX          EQU (0x1 << 31) ;- (DBGU) COMM_RX Interrupt
-// - -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
-// - -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
-// - -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
-// - -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
-AT91C_US_FORCE_NTRST      EQU (0x1 <<  0) ;- (DBGU) Force NTRST in JTAG
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
-// - *****************************************************************************
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Clock Generator Controler
-// - *****************************************************************************
-// - -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
-AT91C_CKGR_MOSCEN         EQU (0x1 <<  0) ;- (CKGR) Main Oscillator Enable
-AT91C_CKGR_OSCBYPASS      EQU (0x1 <<  1) ;- (CKGR) Main Oscillator Bypass
-AT91C_CKGR_OSCOUNT        EQU (0xFF <<  8) ;- (CKGR) Main Oscillator Start-up Time
-// - -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
-AT91C_CKGR_MAINF          EQU (0xFFFF <<  0) ;- (CKGR) Main Clock Frequency
-AT91C_CKGR_MAINRDY        EQU (0x1 << 16) ;- (CKGR) Main Clock Ready
-// - -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 
-AT91C_CKGR_DIV            EQU (0xFF <<  0) ;- (CKGR) Divider Selected
-AT91C_CKGR_DIV_0          EQU (0x0) ;- (CKGR) Divider output is 0
-AT91C_CKGR_DIV_BYPASS     EQU (0x1) ;- (CKGR) Divider is bypassed
-AT91C_CKGR_PLLCOUNT       EQU (0x3F <<  8) ;- (CKGR) PLL Counter
-AT91C_CKGR_OUT            EQU (0x3 << 14) ;- (CKGR) PLL Output Frequency Range
-AT91C_CKGR_OUT_0          EQU (0x0 << 14) ;- (CKGR) Please refer to the PLL datasheet
-AT91C_CKGR_OUT_1          EQU (0x1 << 14) ;- (CKGR) Please refer to the PLL datasheet
-AT91C_CKGR_OUT_2          EQU (0x2 << 14) ;- (CKGR) Please refer to the PLL datasheet
-AT91C_CKGR_OUT_3          EQU (0x3 << 14) ;- (CKGR) Please refer to the PLL datasheet
-AT91C_CKGR_MUL            EQU (0x7FF << 16) ;- (CKGR) PLL Multiplier
-AT91C_CKGR_USBDIV         EQU (0x3 << 28) ;- (CKGR) Divider for USB Clocks
-AT91C_CKGR_USBDIV_0       EQU (0x0 << 28) ;- (CKGR) Divider output is PLL clock output
-AT91C_CKGR_USBDIV_1       EQU (0x1 << 28) ;- (CKGR) Divider output is PLL clock output divided by 2
-AT91C_CKGR_USBDIV_2       EQU (0x2 << 28) ;- (CKGR) Divider output is PLL clock output divided by 4
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Power Management Controler
-// - *****************************************************************************
-// - -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
-AT91C_PMC_PCK             EQU (0x1 <<  0) ;- (PMC) Processor Clock
-AT91C_PMC_UDP             EQU (0x1 <<  7) ;- (PMC) USB Device Port Clock
-AT91C_PMC_PCK0            EQU (0x1 <<  8) ;- (PMC) Programmable Clock Output
-AT91C_PMC_PCK1            EQU (0x1 <<  9) ;- (PMC) Programmable Clock Output
-AT91C_PMC_PCK2            EQU (0x1 << 10) ;- (PMC) Programmable Clock Output
-AT91C_PMC_PCK3            EQU (0x1 << 11) ;- (PMC) Programmable Clock Output
-// - -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
-// - -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
-// - -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
-// - -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
-// - -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 
-// - -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
-AT91C_PMC_CSS             EQU (0x3 <<  0) ;- (PMC) Programmable Clock Selection
-AT91C_PMC_CSS_SLOW_CLK    EQU (0x0) ;- (PMC) Slow Clock is selected
-AT91C_PMC_CSS_MAIN_CLK    EQU (0x1) ;- (PMC) Main Clock is selected
-AT91C_PMC_CSS_PLL_CLK     EQU (0x3) ;- (PMC) Clock from PLL is selected
-AT91C_PMC_PRES            EQU (0x7 <<  2) ;- (PMC) Programmable Clock Prescaler
-AT91C_PMC_PRES_CLK        EQU (0x0 <<  2) ;- (PMC) Selected clock
-AT91C_PMC_PRES_CLK_2      EQU (0x1 <<  2) ;- (PMC) Selected clock divided by 2
-AT91C_PMC_PRES_CLK_4      EQU (0x2 <<  2) ;- (PMC) Selected clock divided by 4
-AT91C_PMC_PRES_CLK_8      EQU (0x3 <<  2) ;- (PMC) Selected clock divided by 8
-AT91C_PMC_PRES_CLK_16     EQU (0x4 <<  2) ;- (PMC) Selected clock divided by 16
-AT91C_PMC_PRES_CLK_32     EQU (0x5 <<  2) ;- (PMC) Selected clock divided by 32
-AT91C_PMC_PRES_CLK_64     EQU (0x6 <<  2) ;- (PMC) Selected clock divided by 64
-// - -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
-// - -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
-AT91C_PMC_MOSCS           EQU (0x1 <<  0) ;- (PMC) MOSC Status/Enable/Disable/Mask
-AT91C_PMC_LOCK            EQU (0x1 <<  2) ;- (PMC) PLL Status/Enable/Disable/Mask
-AT91C_PMC_MCKRDY          EQU (0x1 <<  3) ;- (PMC) MCK_RDY Status/Enable/Disable/Mask
-AT91C_PMC_PCK0RDY         EQU (0x1 <<  8) ;- (PMC) PCK0_RDY Status/Enable/Disable/Mask
-AT91C_PMC_PCK1RDY         EQU (0x1 <<  9) ;- (PMC) PCK1_RDY Status/Enable/Disable/Mask
-AT91C_PMC_PCK2RDY         EQU (0x1 << 10) ;- (PMC) PCK2_RDY Status/Enable/Disable/Mask
-AT91C_PMC_PCK3RDY         EQU (0x1 << 11) ;- (PMC) PCK3_RDY Status/Enable/Disable/Mask
-// - -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
-// - -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
-// - -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Reset Controller Interface
-// - *****************************************************************************
-// - -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
-AT91C_RSTC_PROCRST        EQU (0x1 <<  0) ;- (RSTC) Processor Reset
-AT91C_RSTC_PERRST         EQU (0x1 <<  2) ;- (RSTC) Peripheral Reset
-AT91C_RSTC_EXTRST         EQU (0x1 <<  3) ;- (RSTC) External Reset
-AT91C_RSTC_KEY            EQU (0xFF << 24) ;- (RSTC) Password
-// - -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
-AT91C_RSTC_URSTS          EQU (0x1 <<  0) ;- (RSTC) User Reset Status
-AT91C_RSTC_BODSTS         EQU (0x1 <<  1) ;- (RSTC) Brownout Detection Status
-AT91C_RSTC_RSTTYP         EQU (0x7 <<  8) ;- (RSTC) Reset Type
-AT91C_RSTC_RSTTYP_POWERUP EQU (0x0 <<  8) ;- (RSTC) Power-up Reset. VDDCORE rising.
-AT91C_RSTC_RSTTYP_WAKEUP  EQU (0x1 <<  8) ;- (RSTC) WakeUp Reset. VDDCORE rising.
-AT91C_RSTC_RSTTYP_WATCHDOG EQU (0x2 <<  8) ;- (RSTC) Watchdog Reset. Watchdog overflow occured.
-AT91C_RSTC_RSTTYP_SOFTWARE EQU (0x3 <<  8) ;- (RSTC) Software Reset. Processor reset required by the software.
-AT91C_RSTC_RSTTYP_USER    EQU (0x4 <<  8) ;- (RSTC) User Reset. NRST pin detected low.
-AT91C_RSTC_RSTTYP_BROWNOUT EQU (0x5 <<  8) ;- (RSTC) Brownout Reset occured.
-AT91C_RSTC_NRSTL          EQU (0x1 << 16) ;- (RSTC) NRST pin level
-AT91C_RSTC_SRCMP          EQU (0x1 << 17) ;- (RSTC) Software Reset Command in Progress.
-// - -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
-AT91C_RSTC_URSTEN         EQU (0x1 <<  0) ;- (RSTC) User Reset Enable
-AT91C_RSTC_URSTIEN        EQU (0x1 <<  4) ;- (RSTC) User Reset Interrupt Enable
-AT91C_RSTC_ERSTL          EQU (0xF <<  8) ;- (RSTC) User Reset Enable
-AT91C_RSTC_BODIEN         EQU (0x1 << 16) ;- (RSTC) Brownout Detection Interrupt Enable
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
-// - *****************************************************************************
-// - -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
-AT91C_RTTC_RTPRES         EQU (0xFFFF <<  0) ;- (RTTC) Real-time Timer Prescaler Value
-AT91C_RTTC_ALMIEN         EQU (0x1 << 16) ;- (RTTC) Alarm Interrupt Enable
-AT91C_RTTC_RTTINCIEN      EQU (0x1 << 17) ;- (RTTC) Real Time Timer Increment Interrupt Enable
-AT91C_RTTC_RTTRST         EQU (0x1 << 18) ;- (RTTC) Real Time Timer Restart
-// - -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
-AT91C_RTTC_ALMV           EQU (0x0 <<  0) ;- (RTTC) Alarm Value
-// - -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
-AT91C_RTTC_CRTV           EQU (0x0 <<  0) ;- (RTTC) Current Real-time Value
-// - -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
-AT91C_RTTC_ALMS           EQU (0x1 <<  0) ;- (RTTC) Real-time Alarm Status
-AT91C_RTTC_RTTINC         EQU (0x1 <<  1) ;- (RTTC) Real-time Timer Increment
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
-// - *****************************************************************************
-// - -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
-AT91C_PITC_PIV            EQU (0xFFFFF <<  0) ;- (PITC) Periodic Interval Value
-AT91C_PITC_PITEN          EQU (0x1 << 24) ;- (PITC) Periodic Interval Timer Enabled
-AT91C_PITC_PITIEN         EQU (0x1 << 25) ;- (PITC) Periodic Interval Timer Interrupt Enable
-// - -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
-AT91C_PITC_PITS           EQU (0x1 <<  0) ;- (PITC) Periodic Interval Timer Status
-// - -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
-AT91C_PITC_CPIV           EQU (0xFFFFF <<  0) ;- (PITC) Current Periodic Interval Value
-AT91C_PITC_PICNT          EQU (0xFFF << 20) ;- (PITC) Periodic Interval Counter
-// - -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
-// - *****************************************************************************
-// - -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
-AT91C_WDTC_WDRSTT         EQU (0x1 <<  0) ;- (WDTC) Watchdog Restart
-AT91C_WDTC_KEY            EQU (0xFF << 24) ;- (WDTC) Watchdog KEY Password
-// - -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
-AT91C_WDTC_WDV            EQU (0xFFF <<  0) ;- (WDTC) Watchdog Timer Restart
-AT91C_WDTC_WDFIEN         EQU (0x1 << 12) ;- (WDTC) Watchdog Fault Interrupt Enable
-AT91C_WDTC_WDRSTEN        EQU (0x1 << 13) ;- (WDTC) Watchdog Reset Enable
-AT91C_WDTC_WDRPROC        EQU (0x1 << 14) ;- (WDTC) Watchdog Timer Restart
-AT91C_WDTC_WDDIS          EQU (0x1 << 15) ;- (WDTC) Watchdog Disable
-AT91C_WDTC_WDD            EQU (0xFFF << 16) ;- (WDTC) Watchdog Delta Value
-AT91C_WDTC_WDDBGHLT       EQU (0x1 << 28) ;- (WDTC) Watchdog Debug Halt
-AT91C_WDTC_WDIDLEHLT      EQU (0x1 << 29) ;- (WDTC) Watchdog Idle Halt
-// - -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
-AT91C_WDTC_WDUNF          EQU (0x1 <<  0) ;- (WDTC) Watchdog Underflow
-AT91C_WDTC_WDERR          EQU (0x1 <<  1) ;- (WDTC) Watchdog Error
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
-// - *****************************************************************************
-// - -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- 
-AT91C_VREG_PSTDBY         EQU (0x1 <<  0) ;- (VREG) Voltage Regulator Power Standby Mode
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Memory Controller Interface
-// - *****************************************************************************
-// - -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
-AT91C_MC_RCB              EQU (0x1 <<  0) ;- (MC) Remap Command Bit
-// - -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
-AT91C_MC_UNDADD           EQU (0x1 <<  0) ;- (MC) Undefined Addess Abort Status
-AT91C_MC_MISADD           EQU (0x1 <<  1) ;- (MC) Misaligned Addess Abort Status
-AT91C_MC_ABTSZ            EQU (0x3 <<  8) ;- (MC) Abort Size Status
-AT91C_MC_ABTSZ_BYTE       EQU (0x0 <<  8) ;- (MC) Byte
-AT91C_MC_ABTSZ_HWORD      EQU (0x1 <<  8) ;- (MC) Half-word
-AT91C_MC_ABTSZ_WORD       EQU (0x2 <<  8) ;- (MC) Word
-AT91C_MC_ABTTYP           EQU (0x3 << 10) ;- (MC) Abort Type Status
-AT91C_MC_ABTTYP_DATAR     EQU (0x0 << 10) ;- (MC) Data Read
-AT91C_MC_ABTTYP_DATAW     EQU (0x1 << 10) ;- (MC) Data Write
-AT91C_MC_ABTTYP_FETCH     EQU (0x2 << 10) ;- (MC) Code Fetch
-AT91C_MC_MST0             EQU (0x1 << 16) ;- (MC) Master 0 Abort Source
-AT91C_MC_MST1             EQU (0x1 << 17) ;- (MC) Master 1 Abort Source
-AT91C_MC_SVMST0           EQU (0x1 << 24) ;- (MC) Saved Master 0 Abort Source
-AT91C_MC_SVMST1           EQU (0x1 << 25) ;- (MC) Saved Master 1 Abort Source
-// - -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- 
-AT91C_MC_FRDY             EQU (0x1 <<  0) ;- (MC) Flash Ready
-AT91C_MC_LOCKE            EQU (0x1 <<  2) ;- (MC) Lock Error
-AT91C_MC_PROGE            EQU (0x1 <<  3) ;- (MC) Programming Error
-AT91C_MC_NEBP             EQU (0x1 <<  7) ;- (MC) No Erase Before Programming
-AT91C_MC_FWS              EQU (0x3 <<  8) ;- (MC) Flash Wait State
-AT91C_MC_FWS_0FWS         EQU (0x0 <<  8) ;- (MC) 1 cycle for Read, 2 for Write operations
-AT91C_MC_FWS_1FWS         EQU (0x1 <<  8) ;- (MC) 2 cycles for Read, 3 for Write operations
-AT91C_MC_FWS_2FWS         EQU (0x2 <<  8) ;- (MC) 3 cycles for Read, 4 for Write operations
-AT91C_MC_FWS_3FWS         EQU (0x3 <<  8) ;- (MC) 4 cycles for Read, 4 for Write operations
-AT91C_MC_FMCN             EQU (0xFF << 16) ;- (MC) Flash Microsecond Cycle Number
-// - -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- 
-AT91C_MC_FCMD             EQU (0xF <<  0) ;- (MC) Flash Command
-AT91C_MC_FCMD_START_PROG  EQU (0x1) ;- (MC) Starts the programming of th epage specified by PAGEN.
-AT91C_MC_FCMD_LOCK        EQU (0x2) ;- (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-AT91C_MC_FCMD_PROG_AND_LOCK EQU (0x3) ;- (MC) The lock sequence automatically happens after the programming sequence is completed.
-AT91C_MC_FCMD_UNLOCK      EQU (0x4) ;- (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-AT91C_MC_FCMD_ERASE_ALL   EQU (0x8) ;- (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
-AT91C_MC_FCMD_SET_GP_NVM  EQU (0xB) ;- (MC) Set General Purpose NVM bits.
-AT91C_MC_FCMD_CLR_GP_NVM  EQU (0xD) ;- (MC) Clear General Purpose NVM bits.
-AT91C_MC_FCMD_SET_SECURITY EQU (0xF) ;- (MC) Set Security Bit.
-AT91C_MC_PAGEN            EQU (0x3FF <<  8) ;- (MC) Page Number
-AT91C_MC_KEY              EQU (0xFF << 24) ;- (MC) Writing Protect Key
-// - -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- 
-AT91C_MC_SECURITY         EQU (0x1 <<  4) ;- (MC) Security Bit Status
-AT91C_MC_GPNVM0           EQU (0x1 <<  8) ;- (MC) Sector 0 Lock Status
-AT91C_MC_GPNVM1           EQU (0x1 <<  9) ;- (MC) Sector 1 Lock Status
-AT91C_MC_GPNVM2           EQU (0x1 << 10) ;- (MC) Sector 2 Lock Status
-AT91C_MC_GPNVM3           EQU (0x1 << 11) ;- (MC) Sector 3 Lock Status
-AT91C_MC_GPNVM4           EQU (0x1 << 12) ;- (MC) Sector 4 Lock Status
-AT91C_MC_GPNVM5           EQU (0x1 << 13) ;- (MC) Sector 5 Lock Status
-AT91C_MC_GPNVM6           EQU (0x1 << 14) ;- (MC) Sector 6 Lock Status
-AT91C_MC_GPNVM7           EQU (0x1 << 15) ;- (MC) Sector 7 Lock Status
-AT91C_MC_LOCKS0           EQU (0x1 << 16) ;- (MC) Sector 0 Lock Status
-AT91C_MC_LOCKS1           EQU (0x1 << 17) ;- (MC) Sector 1 Lock Status
-AT91C_MC_LOCKS2           EQU (0x1 << 18) ;- (MC) Sector 2 Lock Status
-AT91C_MC_LOCKS3           EQU (0x1 << 19) ;- (MC) Sector 3 Lock Status
-AT91C_MC_LOCKS4           EQU (0x1 << 20) ;- (MC) Sector 4 Lock Status
-AT91C_MC_LOCKS5           EQU (0x1 << 21) ;- (MC) Sector 5 Lock Status
-AT91C_MC_LOCKS6           EQU (0x1 << 22) ;- (MC) Sector 6 Lock Status
-AT91C_MC_LOCKS7           EQU (0x1 << 23) ;- (MC) Sector 7 Lock Status
-AT91C_MC_LOCKS8           EQU (0x1 << 24) ;- (MC) Sector 8 Lock Status
-AT91C_MC_LOCKS9           EQU (0x1 << 25) ;- (MC) Sector 9 Lock Status
-AT91C_MC_LOCKS10          EQU (0x1 << 26) ;- (MC) Sector 10 Lock Status
-AT91C_MC_LOCKS11          EQU (0x1 << 27) ;- (MC) Sector 11 Lock Status
-AT91C_MC_LOCKS12          EQU (0x1 << 28) ;- (MC) Sector 12 Lock Status
-AT91C_MC_LOCKS13          EQU (0x1 << 29) ;- (MC) Sector 13 Lock Status
-AT91C_MC_LOCKS14          EQU (0x1 << 30) ;- (MC) Sector 14 Lock Status
-AT91C_MC_LOCKS15          EQU (0x1 << 31) ;- (MC) Sector 15 Lock Status
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
-// - *****************************************************************************
-// - -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
-AT91C_SPI_SPIEN           EQU (0x1 <<  0) ;- (SPI) SPI Enable
-AT91C_SPI_SPIDIS          EQU (0x1 <<  1) ;- (SPI) SPI Disable
-AT91C_SPI_SWRST           EQU (0x1 <<  7) ;- (SPI) SPI Software reset
-AT91C_SPI_LASTXFER        EQU (0x1 << 24) ;- (SPI) SPI Last Transfer
-// - -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
-AT91C_SPI_MSTR            EQU (0x1 <<  0) ;- (SPI) Master/Slave Mode
-AT91C_SPI_PS              EQU (0x1 <<  1) ;- (SPI) Peripheral Select
-AT91C_SPI_PS_FIXED        EQU (0x0 <<  1) ;- (SPI) Fixed Peripheral Select
-AT91C_SPI_PS_VARIABLE     EQU (0x1 <<  1) ;- (SPI) Variable Peripheral Select
-AT91C_SPI_PCSDEC          EQU (0x1 <<  2) ;- (SPI) Chip Select Decode
-AT91C_SPI_FDIV            EQU (0x1 <<  3) ;- (SPI) Clock Selection
-AT91C_SPI_MODFDIS         EQU (0x1 <<  4) ;- (SPI) Mode Fault Detection
-AT91C_SPI_LLB             EQU (0x1 <<  7) ;- (SPI) Clock Selection
-AT91C_SPI_PCS             EQU (0xF << 16) ;- (SPI) Peripheral Chip Select
-AT91C_SPI_DLYBCS          EQU (0xFF << 24) ;- (SPI) Delay Between Chip Selects
-// - -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
-AT91C_SPI_RD              EQU (0xFFFF <<  0) ;- (SPI) Receive Data
-AT91C_SPI_RPCS            EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status
-// - -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
-AT91C_SPI_TD              EQU (0xFFFF <<  0) ;- (SPI) Transmit Data
-AT91C_SPI_TPCS            EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status
-// - -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
-AT91C_SPI_RDRF            EQU (0x1 <<  0) ;- (SPI) Receive Data Register Full
-AT91C_SPI_TDRE            EQU (0x1 <<  1) ;- (SPI) Transmit Data Register Empty
-AT91C_SPI_MODF            EQU (0x1 <<  2) ;- (SPI) Mode Fault Error
-AT91C_SPI_OVRES           EQU (0x1 <<  3) ;- (SPI) Overrun Error Status
-AT91C_SPI_ENDRX           EQU (0x1 <<  4) ;- (SPI) End of Receiver Transfer
-AT91C_SPI_ENDTX           EQU (0x1 <<  5) ;- (SPI) End of Receiver Transfer
-AT91C_SPI_RXBUFF          EQU (0x1 <<  6) ;- (SPI) RXBUFF Interrupt
-AT91C_SPI_TXBUFE          EQU (0x1 <<  7) ;- (SPI) TXBUFE Interrupt
-AT91C_SPI_NSSR            EQU (0x1 <<  8) ;- (SPI) NSSR Interrupt
-AT91C_SPI_TXEMPTY         EQU (0x1 <<  9) ;- (SPI) TXEMPTY Interrupt
-AT91C_SPI_SPIENS          EQU (0x1 << 16) ;- (SPI) Enable Status
-// - -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
-// - -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
-// - -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
-// - -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
-AT91C_SPI_CPOL            EQU (0x1 <<  0) ;- (SPI) Clock Polarity
-AT91C_SPI_NCPHA           EQU (0x1 <<  1) ;- (SPI) Clock Phase
-AT91C_SPI_CSAAT           EQU (0x1 <<  3) ;- (SPI) Chip Select Active After Transfer
-AT91C_SPI_BITS            EQU (0xF <<  4) ;- (SPI) Bits Per Transfer
-AT91C_SPI_BITS_8          EQU (0x0 <<  4) ;- (SPI) 8 Bits Per transfer
-AT91C_SPI_BITS_9          EQU (0x1 <<  4) ;- (SPI) 9 Bits Per transfer
-AT91C_SPI_BITS_10         EQU (0x2 <<  4) ;- (SPI) 10 Bits Per transfer
-AT91C_SPI_BITS_11         EQU (0x3 <<  4) ;- (SPI) 11 Bits Per transfer
-AT91C_SPI_BITS_12         EQU (0x4 <<  4) ;- (SPI) 12 Bits Per transfer
-AT91C_SPI_BITS_13         EQU (0x5 <<  4) ;- (SPI) 13 Bits Per transfer
-AT91C_SPI_BITS_14         EQU (0x6 <<  4) ;- (SPI) 14 Bits Per transfer
-AT91C_SPI_BITS_15         EQU (0x7 <<  4) ;- (SPI) 15 Bits Per transfer
-AT91C_SPI_BITS_16         EQU (0x8 <<  4) ;- (SPI) 16 Bits Per transfer
-AT91C_SPI_SCBR            EQU (0xFF <<  8) ;- (SPI) Serial Clock Baud Rate
-AT91C_SPI_DLYBS           EQU (0xFF << 16) ;- (SPI) Delay Before SPCK
-AT91C_SPI_DLYBCT          EQU (0xFF << 24) ;- (SPI) Delay Between Consecutive Transfers
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Usart
-// - *****************************************************************************
-// - -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
-AT91C_US_STTBRK           EQU (0x1 <<  9) ;- (USART) Start Break
-AT91C_US_STPBRK           EQU (0x1 << 10) ;- (USART) Stop Break
-AT91C_US_STTTO            EQU (0x1 << 11) ;- (USART) Start Time-out
-AT91C_US_SENDA            EQU (0x1 << 12) ;- (USART) Send Address
-AT91C_US_RSTIT            EQU (0x1 << 13) ;- (USART) Reset Iterations
-AT91C_US_RSTNACK          EQU (0x1 << 14) ;- (USART) Reset Non Acknowledge
-AT91C_US_RETTO            EQU (0x1 << 15) ;- (USART) Rearm Time-out
-AT91C_US_DTREN            EQU (0x1 << 16) ;- (USART) Data Terminal ready Enable
-AT91C_US_DTRDIS           EQU (0x1 << 17) ;- (USART) Data Terminal ready Disable
-AT91C_US_RTSEN            EQU (0x1 << 18) ;- (USART) Request to Send enable
-AT91C_US_RTSDIS           EQU (0x1 << 19) ;- (USART) Request to Send Disable
-// - -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
-AT91C_US_USMODE           EQU (0xF <<  0) ;- (USART) Usart mode
-AT91C_US_USMODE_NORMAL    EQU (0x0) ;- (USART) Normal
-AT91C_US_USMODE_RS485     EQU (0x1) ;- (USART) RS485
-AT91C_US_USMODE_HWHSH     EQU (0x2) ;- (USART) Hardware Handshaking
-AT91C_US_USMODE_MODEM     EQU (0x3) ;- (USART) Modem
-AT91C_US_USMODE_ISO7816_0 EQU (0x4) ;- (USART) ISO7816 protocol: T = 0
-AT91C_US_USMODE_ISO7816_1 EQU (0x6) ;- (USART) ISO7816 protocol: T = 1
-AT91C_US_USMODE_IRDA      EQU (0x8) ;- (USART) IrDA
-AT91C_US_USMODE_SWHSH     EQU (0xC) ;- (USART) Software Handshaking
-AT91C_US_CLKS             EQU (0x3 <<  4) ;- (USART) Clock Selection (Baud Rate generator Input Clock
-AT91C_US_CLKS_CLOCK       EQU (0x0 <<  4) ;- (USART) Clock
-AT91C_US_CLKS_FDIV1       EQU (0x1 <<  4) ;- (USART) fdiv1
-AT91C_US_CLKS_SLOW        EQU (0x2 <<  4) ;- (USART) slow_clock (ARM)
-AT91C_US_CLKS_EXT         EQU (0x3 <<  4) ;- (USART) External (SCK)
-AT91C_US_CHRL             EQU (0x3 <<  6) ;- (USART) Clock Selection (Baud Rate generator Input Clock
-AT91C_US_CHRL_5_BITS      EQU (0x0 <<  6) ;- (USART) Character Length: 5 bits
-AT91C_US_CHRL_6_BITS      EQU (0x1 <<  6) ;- (USART) Character Length: 6 bits
-AT91C_US_CHRL_7_BITS      EQU (0x2 <<  6) ;- (USART) Character Length: 7 bits
-AT91C_US_CHRL_8_BITS      EQU (0x3 <<  6) ;- (USART) Character Length: 8 bits
-AT91C_US_SYNC             EQU (0x1 <<  8) ;- (USART) Synchronous Mode Select
-AT91C_US_NBSTOP           EQU (0x3 << 12) ;- (USART) Number of Stop bits
-AT91C_US_NBSTOP_1_BIT     EQU (0x0 << 12) ;- (USART) 1 stop bit
-AT91C_US_NBSTOP_15_BIT    EQU (0x1 << 12) ;- (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-AT91C_US_NBSTOP_2_BIT     EQU (0x2 << 12) ;- (USART) 2 stop bits
-AT91C_US_MSBF             EQU (0x1 << 16) ;- (USART) Bit Order
-AT91C_US_MODE9            EQU (0x1 << 17) ;- (USART) 9-bit Character length
-AT91C_US_CKLO             EQU (0x1 << 18) ;- (USART) Clock Output Select
-AT91C_US_OVER             EQU (0x1 << 19) ;- (USART) Over Sampling Mode
-AT91C_US_INACK            EQU (0x1 << 20) ;- (USART) Inhibit Non Acknowledge
-AT91C_US_DSNACK           EQU (0x1 << 21) ;- (USART) Disable Successive NACK
-AT91C_US_MAX_ITER         EQU (0x1 << 24) ;- (USART) Number of Repetitions
-AT91C_US_FILTER           EQU (0x1 << 28) ;- (USART) Receive Line Filter
-// - -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
-AT91C_US_RXBRK            EQU (0x1 <<  2) ;- (USART) Break Received/End of Break
-AT91C_US_TIMEOUT          EQU (0x1 <<  8) ;- (USART) Receiver Time-out
-AT91C_US_ITERATION        EQU (0x1 << 10) ;- (USART) Max number of Repetitions Reached
-AT91C_US_NACK             EQU (0x1 << 13) ;- (USART) Non Acknowledge
-AT91C_US_RIIC             EQU (0x1 << 16) ;- (USART) Ring INdicator Input Change Flag
-AT91C_US_DSRIC            EQU (0x1 << 17) ;- (USART) Data Set Ready Input Change Flag
-AT91C_US_DCDIC            EQU (0x1 << 18) ;- (USART) Data Carrier Flag
-AT91C_US_CTSIC            EQU (0x1 << 19) ;- (USART) Clear To Send Input Change Flag
-// - -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
-// - -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
-// - -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
-AT91C_US_RI               EQU (0x1 << 20) ;- (USART) Image of RI Input
-AT91C_US_DSR              EQU (0x1 << 21) ;- (USART) Image of DSR Input
-AT91C_US_DCD              EQU (0x1 << 22) ;- (USART) Image of DCD Input
-AT91C_US_CTS              EQU (0x1 << 23) ;- (USART) Image of CTS Input
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
-// - *****************************************************************************
-// - -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
-AT91C_SSC_RXEN            EQU (0x1 <<  0) ;- (SSC) Receive Enable
-AT91C_SSC_RXDIS           EQU (0x1 <<  1) ;- (SSC) Receive Disable
-AT91C_SSC_TXEN            EQU (0x1 <<  8) ;- (SSC) Transmit Enable
-AT91C_SSC_TXDIS           EQU (0x1 <<  9) ;- (SSC) Transmit Disable
-AT91C_SSC_SWRST           EQU (0x1 << 15) ;- (SSC) Software Reset
-// - -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
-AT91C_SSC_CKS             EQU (0x3 <<  0) ;- (SSC) Receive/Transmit Clock Selection
-AT91C_SSC_CKS_DIV         EQU (0x0) ;- (SSC) Divided Clock
-AT91C_SSC_CKS_TK          EQU (0x1) ;- (SSC) TK Clock signal
-AT91C_SSC_CKS_RK          EQU (0x2) ;- (SSC) RK pin
-AT91C_SSC_CKO             EQU (0x7 <<  2) ;- (SSC) Receive/Transmit Clock Output Mode Selection
-AT91C_SSC_CKO_NONE        EQU (0x0 <<  2) ;- (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-AT91C_SSC_CKO_CONTINOUS   EQU (0x1 <<  2) ;- (SSC) Continuous Receive/Transmit Clock RK pin: Output
-AT91C_SSC_CKO_DATA_TX     EQU (0x2 <<  2) ;- (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-AT91C_SSC_CKI             EQU (0x1 <<  5) ;- (SSC) Receive/Transmit Clock Inversion
-AT91C_SSC_START           EQU (0xF <<  8) ;- (SSC) Receive/Transmit Start Selection
-AT91C_SSC_START_CONTINOUS EQU (0x0 <<  8) ;- (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-AT91C_SSC_START_TX        EQU (0x1 <<  8) ;- (SSC) Transmit/Receive start
-AT91C_SSC_START_LOW_RF    EQU (0x2 <<  8) ;- (SSC) Detection of a low level on RF input
-AT91C_SSC_START_HIGH_RF   EQU (0x3 <<  8) ;- (SSC) Detection of a high level on RF input
-AT91C_SSC_START_FALL_RF   EQU (0x4 <<  8) ;- (SSC) Detection of a falling edge on RF input
-AT91C_SSC_START_RISE_RF   EQU (0x5 <<  8) ;- (SSC) Detection of a rising edge on RF input
-AT91C_SSC_START_LEVEL_RF  EQU (0x6 <<  8) ;- (SSC) Detection of any level change on RF input
-AT91C_SSC_START_EDGE_RF   EQU (0x7 <<  8) ;- (SSC) Detection of any edge on RF input
-AT91C_SSC_START_0         EQU (0x8 <<  8) ;- (SSC) Compare 0
-AT91C_SSC_STTDLY          EQU (0xFF << 16) ;- (SSC) Receive/Transmit Start Delay
-AT91C_SSC_PERIOD          EQU (0xFF << 24) ;- (SSC) Receive/Transmit Period Divider Selection
-// - -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
-AT91C_SSC_DATLEN          EQU (0x1F <<  0) ;- (SSC) Data Length
-AT91C_SSC_LOOP            EQU (0x1 <<  5) ;- (SSC) Loop Mode
-AT91C_SSC_MSBF            EQU (0x1 <<  7) ;- (SSC) Most Significant Bit First
-AT91C_SSC_DATNB           EQU (0xF <<  8) ;- (SSC) Data Number per Frame
-AT91C_SSC_FSLEN           EQU (0xF << 16) ;- (SSC) Receive/Transmit Frame Sync length
-AT91C_SSC_FSOS            EQU (0x7 << 20) ;- (SSC) Receive/Transmit Frame Sync Output Selection
-AT91C_SSC_FSOS_NONE       EQU (0x0 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-AT91C_SSC_FSOS_NEGATIVE   EQU (0x1 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-AT91C_SSC_FSOS_POSITIVE   EQU (0x2 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-AT91C_SSC_FSOS_LOW        EQU (0x3 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-AT91C_SSC_FSOS_HIGH       EQU (0x4 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-AT91C_SSC_FSOS_TOGGLE     EQU (0x5 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-AT91C_SSC_FSEDGE          EQU (0x1 << 24) ;- (SSC) Frame Sync Edge Detection
-// - -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
-// - -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
-AT91C_SSC_DATDEF          EQU (0x1 <<  5) ;- (SSC) Data Default Value
-AT91C_SSC_FSDEN           EQU (0x1 << 23) ;- (SSC) Frame Sync Data Enable
-// - -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
-AT91C_SSC_TXRDY           EQU (0x1 <<  0) ;- (SSC) Transmit Ready
-AT91C_SSC_TXEMPTY         EQU (0x1 <<  1) ;- (SSC) Transmit Empty
-AT91C_SSC_ENDTX           EQU (0x1 <<  2) ;- (SSC) End Of Transmission
-AT91C_SSC_TXBUFE          EQU (0x1 <<  3) ;- (SSC) Transmit Buffer Empty
-AT91C_SSC_RXRDY           EQU (0x1 <<  4) ;- (SSC) Receive Ready
-AT91C_SSC_OVRUN           EQU (0x1 <<  5) ;- (SSC) Receive Overrun
-AT91C_SSC_ENDRX           EQU (0x1 <<  6) ;- (SSC) End of Reception
-AT91C_SSC_RXBUFF          EQU (0x1 <<  7) ;- (SSC) Receive Buffer Full
-AT91C_SSC_TXSYN           EQU (0x1 << 10) ;- (SSC) Transmit Sync
-AT91C_SSC_RXSYN           EQU (0x1 << 11) ;- (SSC) Receive Sync
-AT91C_SSC_TXENA           EQU (0x1 << 16) ;- (SSC) Transmit Enable
-AT91C_SSC_RXENA           EQU (0x1 << 17) ;- (SSC) Receive Enable
-// - -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
-// - -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
-// - -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Two-wire Interface
-// - *****************************************************************************
-// - -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
-AT91C_TWI_START           EQU (0x1 <<  0) ;- (TWI) Send a START Condition
-AT91C_TWI_STOP            EQU (0x1 <<  1) ;- (TWI) Send a STOP Condition
-AT91C_TWI_MSEN            EQU (0x1 <<  2) ;- (TWI) TWI Master Transfer Enabled
-AT91C_TWI_MSDIS           EQU (0x1 <<  3) ;- (TWI) TWI Master Transfer Disabled
-AT91C_TWI_SWRST           EQU (0x1 <<  7) ;- (TWI) Software Reset
-// - -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
-AT91C_TWI_IADRSZ          EQU (0x3 <<  8) ;- (TWI) Internal Device Address Size
-AT91C_TWI_IADRSZ_NO       EQU (0x0 <<  8) ;- (TWI) No internal device address
-AT91C_TWI_IADRSZ_1_BYTE   EQU (0x1 <<  8) ;- (TWI) One-byte internal device address
-AT91C_TWI_IADRSZ_2_BYTE   EQU (0x2 <<  8) ;- (TWI) Two-byte internal device address
-AT91C_TWI_IADRSZ_3_BYTE   EQU (0x3 <<  8) ;- (TWI) Three-byte internal device address
-AT91C_TWI_MREAD           EQU (0x1 << 12) ;- (TWI) Master Read Direction
-AT91C_TWI_DADR            EQU (0x7F << 16) ;- (TWI) Device Address
-// - -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
-AT91C_TWI_CLDIV           EQU (0xFF <<  0) ;- (TWI) Clock Low Divider
-AT91C_TWI_CHDIV           EQU (0xFF <<  8) ;- (TWI) Clock High Divider
-AT91C_TWI_CKDIV           EQU (0x7 << 16) ;- (TWI) Clock Divider
-// - -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
-AT91C_TWI_TXCOMP          EQU (0x1 <<  0) ;- (TWI) Transmission Completed
-AT91C_TWI_RXRDY           EQU (0x1 <<  1) ;- (TWI) Receive holding register ReaDY
-AT91C_TWI_TXRDY           EQU (0x1 <<  2) ;- (TWI) Transmit holding register ReaDY
-AT91C_TWI_OVRE            EQU (0x1 <<  6) ;- (TWI) Overrun Error
-AT91C_TWI_UNRE            EQU (0x1 <<  7) ;- (TWI) Underrun Error
-AT91C_TWI_NACK            EQU (0x1 <<  8) ;- (TWI) Not Acknowledged
-// - -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
-// - -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
-// - -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
-// - *****************************************************************************
-// - -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- 
-AT91C_PWMC_CPRE           EQU (0xF <<  0) ;- (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
-AT91C_PWMC_CPRE_MCK       EQU (0x0) ;- (PWMC_CH) 
-AT91C_PWMC_CPRE_MCKA      EQU (0xB) ;- (PWMC_CH) 
-AT91C_PWMC_CPRE_MCKB      EQU (0xC) ;- (PWMC_CH) 
-AT91C_PWMC_CALG           EQU (0x1 <<  8) ;- (PWMC_CH) Channel Alignment
-AT91C_PWMC_CPOL           EQU (0x1 <<  9) ;- (PWMC_CH) Channel Polarity
-AT91C_PWMC_CPD            EQU (0x1 << 10) ;- (PWMC_CH) Channel Update Period
-// - -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- 
-AT91C_PWMC_CDTY           EQU (0x0 <<  0) ;- (PWMC_CH) Channel Duty Cycle
-// - -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- 
-AT91C_PWMC_CPRD           EQU (0x0 <<  0) ;- (PWMC_CH) Channel Period
-// - -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- 
-AT91C_PWMC_CCNT           EQU (0x0 <<  0) ;- (PWMC_CH) Channel Counter
-// - -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- 
-AT91C_PWMC_CUPD           EQU (0x0 <<  0) ;- (PWMC_CH) Channel Update
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
-// - *****************************************************************************
-// - -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- 
-AT91C_PWMC_DIVA           EQU (0xFF <<  0) ;- (PWMC) CLKA divide factor.
-AT91C_PWMC_PREA           EQU (0xF <<  8) ;- (PWMC) Divider Input Clock Prescaler A
-AT91C_PWMC_PREA_MCK       EQU (0x0 <<  8) ;- (PWMC) 
-AT91C_PWMC_DIVB           EQU (0xFF << 16) ;- (PWMC) CLKB divide factor.
-AT91C_PWMC_PREB           EQU (0xF << 24) ;- (PWMC) Divider Input Clock Prescaler B
-AT91C_PWMC_PREB_MCK       EQU (0x0 << 24) ;- (PWMC) 
-// - -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- 
-AT91C_PWMC_CHID0          EQU (0x1 <<  0) ;- (PWMC) Channel ID 0
-AT91C_PWMC_CHID1          EQU (0x1 <<  1) ;- (PWMC) Channel ID 1
-AT91C_PWMC_CHID2          EQU (0x1 <<  2) ;- (PWMC) Channel ID 2
-AT91C_PWMC_CHID3          EQU (0x1 <<  3) ;- (PWMC) Channel ID 3
-// - -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- 
-// - -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- 
-// - -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- 
-// - -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- 
-// - -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- 
-// - -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- 
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR USB Device Interface
-// - *****************************************************************************
-// - -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
-AT91C_UDP_FRM_NUM         EQU (0x7FF <<  0) ;- (UDP) Frame Number as Defined in the Packet Field Formats
-AT91C_UDP_FRM_ERR         EQU (0x1 << 16) ;- (UDP) Frame Error
-AT91C_UDP_FRM_OK          EQU (0x1 << 17) ;- (UDP) Frame OK
-// - -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
-AT91C_UDP_FADDEN          EQU (0x1 <<  0) ;- (UDP) Function Address Enable
-AT91C_UDP_CONFG           EQU (0x1 <<  1) ;- (UDP) Configured
-AT91C_UDP_ESR             EQU (0x1 <<  2) ;- (UDP) Enable Send Resume
-AT91C_UDP_RSMINPR         EQU (0x1 <<  3) ;- (UDP) A Resume Has Been Sent to the Host
-AT91C_UDP_RMWUPE          EQU (0x1 <<  4) ;- (UDP) Remote Wake Up Enable
-// - -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
-AT91C_UDP_FADD            EQU (0xFF <<  0) ;- (UDP) Function Address Value
-AT91C_UDP_FEN             EQU (0x1 <<  8) ;- (UDP) Function Enable
-// - -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
-AT91C_UDP_EPINT0          EQU (0x1 <<  0) ;- (UDP) Endpoint 0 Interrupt
-AT91C_UDP_EPINT1          EQU (0x1 <<  1) ;- (UDP) Endpoint 0 Interrupt
-AT91C_UDP_EPINT2          EQU (0x1 <<  2) ;- (UDP) Endpoint 2 Interrupt
-AT91C_UDP_EPINT3          EQU (0x1 <<  3) ;- (UDP) Endpoint 3 Interrupt
-AT91C_UDP_EPINT4          EQU (0x1 <<  4) ;- (UDP) Endpoint 4 Interrupt
-AT91C_UDP_EPINT5          EQU (0x1 <<  5) ;- (UDP) Endpoint 5 Interrupt
-AT91C_UDP_RXSUSP          EQU (0x1 <<  8) ;- (UDP) USB Suspend Interrupt
-AT91C_UDP_RXRSM           EQU (0x1 <<  9) ;- (UDP) USB Resume Interrupt
-AT91C_UDP_EXTRSM          EQU (0x1 << 10) ;- (UDP) USB External Resume Interrupt
-AT91C_UDP_SOFINT          EQU (0x1 << 11) ;- (UDP) USB Start Of frame Interrupt
-AT91C_UDP_WAKEUP          EQU (0x1 << 13) ;- (UDP) USB Resume Interrupt
-// - -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
-// - -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
-// - -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
-AT91C_UDP_ENDBUSRES       EQU (0x1 << 12) ;- (UDP) USB End Of Bus Reset Interrupt
-// - -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
-// - -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
-AT91C_UDP_EP0             EQU (0x1 <<  0) ;- (UDP) Reset Endpoint 0
-AT91C_UDP_EP1             EQU (0x1 <<  1) ;- (UDP) Reset Endpoint 1
-AT91C_UDP_EP2             EQU (0x1 <<  2) ;- (UDP) Reset Endpoint 2
-AT91C_UDP_EP3             EQU (0x1 <<  3) ;- (UDP) Reset Endpoint 3
-AT91C_UDP_EP4             EQU (0x1 <<  4) ;- (UDP) Reset Endpoint 4
-AT91C_UDP_EP5             EQU (0x1 <<  5) ;- (UDP) Reset Endpoint 5
-// - -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
-AT91C_UDP_TXCOMP          EQU (0x1 <<  0) ;- (UDP) Generates an IN packet with data previously written in the DPR
-AT91C_UDP_RX_DATA_BK0     EQU (0x1 <<  1) ;- (UDP) Receive Data Bank 0
-AT91C_UDP_RXSETUP         EQU (0x1 <<  2) ;- (UDP) Sends STALL to the Host (Control endpoints)
-AT91C_UDP_ISOERROR        EQU (0x1 <<  3) ;- (UDP) Isochronous error (Isochronous endpoints)
-AT91C_UDP_TXPKTRDY        EQU (0x1 <<  4) ;- (UDP) Transmit Packet Ready
-AT91C_UDP_FORCESTALL      EQU (0x1 <<  5) ;- (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-AT91C_UDP_RX_DATA_BK1     EQU (0x1 <<  6) ;- (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-AT91C_UDP_DIR             EQU (0x1 <<  7) ;- (UDP) Transfer Direction
-AT91C_UDP_EPTYPE          EQU (0x7 <<  8) ;- (UDP) Endpoint type
-AT91C_UDP_EPTYPE_CTRL     EQU (0x0 <<  8) ;- (UDP) Control
-AT91C_UDP_EPTYPE_ISO_OUT  EQU (0x1 <<  8) ;- (UDP) Isochronous OUT
-AT91C_UDP_EPTYPE_BULK_OUT EQU (0x2 <<  8) ;- (UDP) Bulk OUT
-AT91C_UDP_EPTYPE_INT_OUT  EQU (0x3 <<  8) ;- (UDP) Interrupt OUT
-AT91C_UDP_EPTYPE_ISO_IN   EQU (0x5 <<  8) ;- (UDP) Isochronous IN
-AT91C_UDP_EPTYPE_BULK_IN  EQU (0x6 <<  8) ;- (UDP) Bulk IN
-AT91C_UDP_EPTYPE_INT_IN   EQU (0x7 <<  8) ;- (UDP) Interrupt IN
-AT91C_UDP_DTGLE           EQU (0x1 << 11) ;- (UDP) Data Toggle
-AT91C_UDP_EPEDS           EQU (0x1 << 15) ;- (UDP) Endpoint Enable Disable
-AT91C_UDP_RXBYTECNT       EQU (0x7FF << 16) ;- (UDP) Number Of Bytes Available in the FIFO
-// - -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- 
-AT91C_UDP_TXVDIS          EQU (0x1 <<  8) ;- (UDP) 
-AT91C_UDP_PUON            EQU (0x1 <<  9) ;- (UDP) Pull-up ON
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
-// - *****************************************************************************
-// - -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
-AT91C_TC_CLKEN            EQU (0x1 <<  0) ;- (TC) Counter Clock Enable Command
-AT91C_TC_CLKDIS           EQU (0x1 <<  1) ;- (TC) Counter Clock Disable Command
-AT91C_TC_SWTRG            EQU (0x1 <<  2) ;- (TC) Software Trigger Command
-// - -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
-AT91C_TC_CLKS             EQU (0x7 <<  0) ;- (TC) Clock Selection
-AT91C_TC_CLKS_TIMER_DIV1_CLOCK EQU (0x0) ;- (TC) Clock selected: TIMER_DIV1_CLOCK
-AT91C_TC_CLKS_TIMER_DIV2_CLOCK EQU (0x1) ;- (TC) Clock selected: TIMER_DIV2_CLOCK
-AT91C_TC_CLKS_TIMER_DIV3_CLOCK EQU (0x2) ;- (TC) Clock selected: TIMER_DIV3_CLOCK
-AT91C_TC_CLKS_TIMER_DIV4_CLOCK EQU (0x3) ;- (TC) Clock selected: TIMER_DIV4_CLOCK
-AT91C_TC_CLKS_TIMER_DIV5_CLOCK EQU (0x4) ;- (TC) Clock selected: TIMER_DIV5_CLOCK
-AT91C_TC_CLKS_XC0         EQU (0x5) ;- (TC) Clock selected: XC0
-AT91C_TC_CLKS_XC1         EQU (0x6) ;- (TC) Clock selected: XC1
-AT91C_TC_CLKS_XC2         EQU (0x7) ;- (TC) Clock selected: XC2
-AT91C_TC_CLKI             EQU (0x1 <<  3) ;- (TC) Clock Invert
-AT91C_TC_BURST            EQU (0x3 <<  4) ;- (TC) Burst Signal Selection
-AT91C_TC_BURST_NONE       EQU (0x0 <<  4) ;- (TC) The clock is not gated by an external signal
-AT91C_TC_BURST_XC0        EQU (0x1 <<  4) ;- (TC) XC0 is ANDed with the selected clock
-AT91C_TC_BURST_XC1        EQU (0x2 <<  4) ;- (TC) XC1 is ANDed with the selected clock
-AT91C_TC_BURST_XC2        EQU (0x3 <<  4) ;- (TC) XC2 is ANDed with the selected clock
-AT91C_TC_CPCSTOP          EQU (0x1 <<  6) ;- (TC) Counter Clock Stopped with RC Compare
-AT91C_TC_LDBSTOP          EQU (0x1 <<  6) ;- (TC) Counter Clock Stopped with RB Loading
-AT91C_TC_CPCDIS           EQU (0x1 <<  7) ;- (TC) Counter Clock Disable with RC Compare
-AT91C_TC_LDBDIS           EQU (0x1 <<  7) ;- (TC) Counter Clock Disabled with RB Loading
-AT91C_TC_ETRGEDG          EQU (0x3 <<  8) ;- (TC) External Trigger Edge Selection
-AT91C_TC_ETRGEDG_NONE     EQU (0x0 <<  8) ;- (TC) Edge: None
-AT91C_TC_ETRGEDG_RISING   EQU (0x1 <<  8) ;- (TC) Edge: rising edge
-AT91C_TC_ETRGEDG_FALLING  EQU (0x2 <<  8) ;- (TC) Edge: falling edge
-AT91C_TC_ETRGEDG_BOTH     EQU (0x3 <<  8) ;- (TC) Edge: each edge
-AT91C_TC_EEVTEDG          EQU (0x3 <<  8) ;- (TC) External Event Edge Selection
-AT91C_TC_EEVTEDG_NONE     EQU (0x0 <<  8) ;- (TC) Edge: None
-AT91C_TC_EEVTEDG_RISING   EQU (0x1 <<  8) ;- (TC) Edge: rising edge
-AT91C_TC_EEVTEDG_FALLING  EQU (0x2 <<  8) ;- (TC) Edge: falling edge
-AT91C_TC_EEVTEDG_BOTH     EQU (0x3 <<  8) ;- (TC) Edge: each edge
-AT91C_TC_EEVT             EQU (0x3 << 10) ;- (TC) External Event  Selection
-AT91C_TC_EEVT_TIOB        EQU (0x0 << 10) ;- (TC) Signal selected as external event: TIOB TIOB direction: input
-AT91C_TC_EEVT_XC0         EQU (0x1 << 10) ;- (TC) Signal selected as external event: XC0 TIOB direction: output
-AT91C_TC_EEVT_XC1         EQU (0x2 << 10) ;- (TC) Signal selected as external event: XC1 TIOB direction: output
-AT91C_TC_EEVT_XC2         EQU (0x3 << 10) ;- (TC) Signal selected as external event: XC2 TIOB direction: output
-AT91C_TC_ABETRG           EQU (0x1 << 10) ;- (TC) TIOA or TIOB External Trigger Selection
-AT91C_TC_ENETRG           EQU (0x1 << 12) ;- (TC) External Event Trigger enable
-AT91C_TC_WAVESEL          EQU (0x3 << 13) ;- (TC) Waveform  Selection
-AT91C_TC_WAVESEL_UP       EQU (0x0 << 13) ;- (TC) UP mode without atomatic trigger on RC Compare
-AT91C_TC_WAVESEL_UPDOWN   EQU (0x1 << 13) ;- (TC) UPDOWN mode without automatic trigger on RC Compare
-AT91C_TC_WAVESEL_UP_AUTO  EQU (0x2 << 13) ;- (TC) UP mode with automatic trigger on RC Compare
-AT91C_TC_WAVESEL_UPDOWN_AUTO EQU (0x3 << 13) ;- (TC) UPDOWN mode with automatic trigger on RC Compare
-AT91C_TC_CPCTRG           EQU (0x1 << 14) ;- (TC) RC Compare Trigger Enable
-AT91C_TC_WAVE             EQU (0x1 << 15) ;- (TC) 
-AT91C_TC_ACPA             EQU (0x3 << 16) ;- (TC) RA Compare Effect on TIOA
-AT91C_TC_ACPA_NONE        EQU (0x0 << 16) ;- (TC) Effect: none
-AT91C_TC_ACPA_SET         EQU (0x1 << 16) ;- (TC) Effect: set
-AT91C_TC_ACPA_CLEAR       EQU (0x2 << 16) ;- (TC) Effect: clear
-AT91C_TC_ACPA_TOGGLE      EQU (0x3 << 16) ;- (TC) Effect: toggle
-AT91C_TC_LDRA             EQU (0x3 << 16) ;- (TC) RA Loading Selection
-AT91C_TC_LDRA_NONE        EQU (0x0 << 16) ;- (TC) Edge: None
-AT91C_TC_LDRA_RISING      EQU (0x1 << 16) ;- (TC) Edge: rising edge of TIOA
-AT91C_TC_LDRA_FALLING     EQU (0x2 << 16) ;- (TC) Edge: falling edge of TIOA
-AT91C_TC_LDRA_BOTH        EQU (0x3 << 16) ;- (TC) Edge: each edge of TIOA
-AT91C_TC_ACPC             EQU (0x3 << 18) ;- (TC) RC Compare Effect on TIOA
-AT91C_TC_ACPC_NONE        EQU (0x0 << 18) ;- (TC) Effect: none
-AT91C_TC_ACPC_SET         EQU (0x1 << 18) ;- (TC) Effect: set
-AT91C_TC_ACPC_CLEAR       EQU (0x2 << 18) ;- (TC) Effect: clear
-AT91C_TC_ACPC_TOGGLE      EQU (0x3 << 18) ;- (TC) Effect: toggle
-AT91C_TC_LDRB             EQU (0x3 << 18) ;- (TC) RB Loading Selection
-AT91C_TC_LDRB_NONE        EQU (0x0 << 18) ;- (TC) Edge: None
-AT91C_TC_LDRB_RISING      EQU (0x1 << 18) ;- (TC) Edge: rising edge of TIOA
-AT91C_TC_LDRB_FALLING     EQU (0x2 << 18) ;- (TC) Edge: falling edge of TIOA
-AT91C_TC_LDRB_BOTH        EQU (0x3 << 18) ;- (TC) Edge: each edge of TIOA
-AT91C_TC_AEEVT            EQU (0x3 << 20) ;- (TC) External Event Effect on TIOA
-AT91C_TC_AEEVT_NONE       EQU (0x0 << 20) ;- (TC) Effect: none
-AT91C_TC_AEEVT_SET        EQU (0x1 << 20) ;- (TC) Effect: set
-AT91C_TC_AEEVT_CLEAR      EQU (0x2 << 20) ;- (TC) Effect: clear
-AT91C_TC_AEEVT_TOGGLE     EQU (0x3 << 20) ;- (TC) Effect: toggle
-AT91C_TC_ASWTRG           EQU (0x3 << 22) ;- (TC) Software Trigger Effect on TIOA
-AT91C_TC_ASWTRG_NONE      EQU (0x0 << 22) ;- (TC) Effect: none
-AT91C_TC_ASWTRG_SET       EQU (0x1 << 22) ;- (TC) Effect: set
-AT91C_TC_ASWTRG_CLEAR     EQU (0x2 << 22) ;- (TC) Effect: clear
-AT91C_TC_ASWTRG_TOGGLE    EQU (0x3 << 22) ;- (TC) Effect: toggle
-AT91C_TC_BCPB             EQU (0x3 << 24) ;- (TC) RB Compare Effect on TIOB
-AT91C_TC_BCPB_NONE        EQU (0x0 << 24) ;- (TC) Effect: none
-AT91C_TC_BCPB_SET         EQU (0x1 << 24) ;- (TC) Effect: set
-AT91C_TC_BCPB_CLEAR       EQU (0x2 << 24) ;- (TC) Effect: clear
-AT91C_TC_BCPB_TOGGLE      EQU (0x3 << 24) ;- (TC) Effect: toggle
-AT91C_TC_BCPC             EQU (0x3 << 26) ;- (TC) RC Compare Effect on TIOB
-AT91C_TC_BCPC_NONE        EQU (0x0 << 26) ;- (TC) Effect: none
-AT91C_TC_BCPC_SET         EQU (0x1 << 26) ;- (TC) Effect: set
-AT91C_TC_BCPC_CLEAR       EQU (0x2 << 26) ;- (TC) Effect: clear
-AT91C_TC_BCPC_TOGGLE      EQU (0x3 << 26) ;- (TC) Effect: toggle
-AT91C_TC_BEEVT            EQU (0x3 << 28) ;- (TC) External Event Effect on TIOB
-AT91C_TC_BEEVT_NONE       EQU (0x0 << 28) ;- (TC) Effect: none
-AT91C_TC_BEEVT_SET        EQU (0x1 << 28) ;- (TC) Effect: set
-AT91C_TC_BEEVT_CLEAR      EQU (0x2 << 28) ;- (TC) Effect: clear
-AT91C_TC_BEEVT_TOGGLE     EQU (0x3 << 28) ;- (TC) Effect: toggle
-AT91C_TC_BSWTRG           EQU (0x3 << 30) ;- (TC) Software Trigger Effect on TIOB
-AT91C_TC_BSWTRG_NONE      EQU (0x0 << 30) ;- (TC) Effect: none
-AT91C_TC_BSWTRG_SET       EQU (0x1 << 30) ;- (TC) Effect: set
-AT91C_TC_BSWTRG_CLEAR     EQU (0x2 << 30) ;- (TC) Effect: clear
-AT91C_TC_BSWTRG_TOGGLE    EQU (0x3 << 30) ;- (TC) Effect: toggle
-// - -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
-AT91C_TC_COVFS            EQU (0x1 <<  0) ;- (TC) Counter Overflow
-AT91C_TC_LOVRS            EQU (0x1 <<  1) ;- (TC) Load Overrun
-AT91C_TC_CPAS             EQU (0x1 <<  2) ;- (TC) RA Compare
-AT91C_TC_CPBS             EQU (0x1 <<  3) ;- (TC) RB Compare
-AT91C_TC_CPCS             EQU (0x1 <<  4) ;- (TC) RC Compare
-AT91C_TC_LDRAS            EQU (0x1 <<  5) ;- (TC) RA Loading
-AT91C_TC_LDRBS            EQU (0x1 <<  6) ;- (TC) RB Loading
-AT91C_TC_ETRGS            EQU (0x1 <<  7) ;- (TC) External Trigger
-AT91C_TC_CLKSTA           EQU (0x1 << 16) ;- (TC) Clock Enabling
-AT91C_TC_MTIOA            EQU (0x1 << 17) ;- (TC) TIOA Mirror
-AT91C_TC_MTIOB            EQU (0x1 << 18) ;- (TC) TIOA Mirror
-// - -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
-// - -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
-// - -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Timer Counter Interface
-// - *****************************************************************************
-// - -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
-AT91C_TCB_SYNC            EQU (0x1 <<  0) ;- (TCB) Synchro Command
-// - -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
-AT91C_TCB_TC0XC0S         EQU (0x3 <<  0) ;- (TCB) External Clock Signal 0 Selection
-AT91C_TCB_TC0XC0S_TCLK0   EQU (0x0) ;- (TCB) TCLK0 connected to XC0
-AT91C_TCB_TC0XC0S_NONE    EQU (0x1) ;- (TCB) None signal connected to XC0
-AT91C_TCB_TC0XC0S_TIOA1   EQU (0x2) ;- (TCB) TIOA1 connected to XC0
-AT91C_TCB_TC0XC0S_TIOA2   EQU (0x3) ;- (TCB) TIOA2 connected to XC0
-AT91C_TCB_TC1XC1S         EQU (0x3 <<  2) ;- (TCB) External Clock Signal 1 Selection
-AT91C_TCB_TC1XC1S_TCLK1   EQU (0x0 <<  2) ;- (TCB) TCLK1 connected to XC1
-AT91C_TCB_TC1XC1S_NONE    EQU (0x1 <<  2) ;- (TCB) None signal connected to XC1
-AT91C_TCB_TC1XC1S_TIOA0   EQU (0x2 <<  2) ;- (TCB) TIOA0 connected to XC1
-AT91C_TCB_TC1XC1S_TIOA2   EQU (0x3 <<  2) ;- (TCB) TIOA2 connected to XC1
-AT91C_TCB_TC2XC2S         EQU (0x3 <<  4) ;- (TCB) External Clock Signal 2 Selection
-AT91C_TCB_TC2XC2S_TCLK2   EQU (0x0 <<  4) ;- (TCB) TCLK2 connected to XC2
-AT91C_TCB_TC2XC2S_NONE    EQU (0x1 <<  4) ;- (TCB) None signal connected to XC2
-AT91C_TCB_TC2XC2S_TIOA0   EQU (0x2 <<  4) ;- (TCB) TIOA0 connected to XC2
-AT91C_TCB_TC2XC2S_TIOA1   EQU (0x3 <<  4) ;- (TCB) TIOA2 connected to XC2
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface
-// - *****************************************************************************
-// - -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- 
-AT91C_CAN_MTIMEMARK       EQU (0xFFFF <<  0) ;- (CAN_MB) Mailbox Timemark
-AT91C_CAN_PRIOR           EQU (0xF << 16) ;- (CAN_MB) Mailbox Priority
-AT91C_CAN_MOT             EQU (0x7 << 24) ;- (CAN_MB) Mailbox Object Type
-AT91C_CAN_MOT_DIS         EQU (0x0 << 24) ;- (CAN_MB) 
-AT91C_CAN_MOT_RX          EQU (0x1 << 24) ;- (CAN_MB) 
-AT91C_CAN_MOT_RXOVERWRITE EQU (0x2 << 24) ;- (CAN_MB) 
-AT91C_CAN_MOT_TX          EQU (0x3 << 24) ;- (CAN_MB) 
-AT91C_CAN_MOT_CONSUMER    EQU (0x4 << 24) ;- (CAN_MB) 
-AT91C_CAN_MOT_PRODUCER    EQU (0x5 << 24) ;- (CAN_MB) 
-// - -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- 
-AT91C_CAN_MIDvB           EQU (0x3FFFF <<  0) ;- (CAN_MB) Complementary bits for identifier in extended mode
-AT91C_CAN_MIDvA           EQU (0x7FF << 18) ;- (CAN_MB) Identifier for standard frame mode
-AT91C_CAN_MIDE            EQU (0x1 << 29) ;- (CAN_MB) Identifier Version
-// - -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- 
-// - -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- 
-// - -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- 
-AT91C_CAN_MTIMESTAMP      EQU (0xFFFF <<  0) ;- (CAN_MB) Timer Value
-AT91C_CAN_MDLC            EQU (0xF << 16) ;- (CAN_MB) Mailbox Data Length Code
-AT91C_CAN_MRTR            EQU (0x1 << 20) ;- (CAN_MB) Mailbox Remote Transmission Request
-AT91C_CAN_MABT            EQU (0x1 << 22) ;- (CAN_MB) Mailbox Message Abort
-AT91C_CAN_MRDY            EQU (0x1 << 23) ;- (CAN_MB) Mailbox Ready
-AT91C_CAN_MMI             EQU (0x1 << 24) ;- (CAN_MB) Mailbox Message Ignored
-// - -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- 
-// - -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- 
-// - -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- 
-AT91C_CAN_MACR            EQU (0x1 << 22) ;- (CAN_MB) Abort Request for Mailbox
-AT91C_CAN_MTCR            EQU (0x1 << 23) ;- (CAN_MB) Mailbox Transfer Command
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Control Area Network Interface
-// - *****************************************************************************
-// - -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- 
-AT91C_CAN_CANEN           EQU (0x1 <<  0) ;- (CAN) CAN Controller Enable
-AT91C_CAN_LPM             EQU (0x1 <<  1) ;- (CAN) Disable/Enable Low Power Mode
-AT91C_CAN_ABM             EQU (0x1 <<  2) ;- (CAN) Disable/Enable Autobaud/Listen Mode
-AT91C_CAN_OVL             EQU (0x1 <<  3) ;- (CAN) Disable/Enable Overload Frame
-AT91C_CAN_TEOF            EQU (0x1 <<  4) ;- (CAN) Time Stamp messages at each end of Frame
-AT91C_CAN_TTM             EQU (0x1 <<  5) ;- (CAN) Disable/Enable Time Trigger Mode
-AT91C_CAN_TIMFRZ          EQU (0x1 <<  6) ;- (CAN) Enable Timer Freeze
-AT91C_CAN_DRPT            EQU (0x1 <<  7) ;- (CAN) Disable Repeat
-// - -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- 
-AT91C_CAN_MB0             EQU (0x1 <<  0) ;- (CAN) Mailbox 0 Flag
-AT91C_CAN_MB1             EQU (0x1 <<  1) ;- (CAN) Mailbox 1 Flag
-AT91C_CAN_MB2             EQU (0x1 <<  2) ;- (CAN) Mailbox 2 Flag
-AT91C_CAN_MB3             EQU (0x1 <<  3) ;- (CAN) Mailbox 3 Flag
-AT91C_CAN_MB4             EQU (0x1 <<  4) ;- (CAN) Mailbox 4 Flag
-AT91C_CAN_MB5             EQU (0x1 <<  5) ;- (CAN) Mailbox 5 Flag
-AT91C_CAN_MB6             EQU (0x1 <<  6) ;- (CAN) Mailbox 6 Flag
-AT91C_CAN_MB7             EQU (0x1 <<  7) ;- (CAN) Mailbox 7 Flag
-AT91C_CAN_MB8             EQU (0x1 <<  8) ;- (CAN) Mailbox 8 Flag
-AT91C_CAN_MB9             EQU (0x1 <<  9) ;- (CAN) Mailbox 9 Flag
-AT91C_CAN_MB10            EQU (0x1 << 10) ;- (CAN) Mailbox 10 Flag
-AT91C_CAN_MB11            EQU (0x1 << 11) ;- (CAN) Mailbox 11 Flag
-AT91C_CAN_MB12            EQU (0x1 << 12) ;- (CAN) Mailbox 12 Flag
-AT91C_CAN_MB13            EQU (0x1 << 13) ;- (CAN) Mailbox 13 Flag
-AT91C_CAN_MB14            EQU (0x1 << 14) ;- (CAN) Mailbox 14 Flag
-AT91C_CAN_MB15            EQU (0x1 << 15) ;- (CAN) Mailbox 15 Flag
-AT91C_CAN_ERRA            EQU (0x1 << 16) ;- (CAN) Error Active Mode Flag
-AT91C_CAN_WARN            EQU (0x1 << 17) ;- (CAN) Warning Limit Flag
-AT91C_CAN_ERRP            EQU (0x1 << 18) ;- (CAN) Error Passive Mode Flag
-AT91C_CAN_BOFF            EQU (0x1 << 19) ;- (CAN) Bus Off Mode Flag
-AT91C_CAN_SLEEP           EQU (0x1 << 20) ;- (CAN) Sleep Flag
-AT91C_CAN_WAKEUP          EQU (0x1 << 21) ;- (CAN) Wakeup Flag
-AT91C_CAN_TOVF            EQU (0x1 << 22) ;- (CAN) Timer Overflow Flag
-AT91C_CAN_TSTP            EQU (0x1 << 23) ;- (CAN) Timestamp Flag
-AT91C_CAN_CERR            EQU (0x1 << 24) ;- (CAN) CRC Error
-AT91C_CAN_SERR            EQU (0x1 << 25) ;- (CAN) Stuffing Error
-AT91C_CAN_AERR            EQU (0x1 << 26) ;- (CAN) Acknowledgment Error
-AT91C_CAN_FERR            EQU (0x1 << 27) ;- (CAN) Form Error
-AT91C_CAN_BERR            EQU (0x1 << 28) ;- (CAN) Bit Error
-// - -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- 
-// - -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- 
-// - -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- 
-AT91C_CAN_RBSY            EQU (0x1 << 29) ;- (CAN) Receiver Busy
-AT91C_CAN_TBSY            EQU (0x1 << 30) ;- (CAN) Transmitter Busy
-AT91C_CAN_OVLY            EQU (0x1 << 31) ;- (CAN) Overload Busy
-// - -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- 
-AT91C_CAN_PHASE2          EQU (0x7 <<  0) ;- (CAN) Phase 2 segment
-AT91C_CAN_PHASE1          EQU (0x7 <<  4) ;- (CAN) Phase 1 segment
-AT91C_CAN_PROPAG          EQU (0x7 <<  8) ;- (CAN) Programmation time segment
-AT91C_CAN_SYNC            EQU (0x3 << 12) ;- (CAN) Re-synchronization jump width segment
-AT91C_CAN_BRP             EQU (0x7F << 16) ;- (CAN) Baudrate Prescaler
-AT91C_CAN_SMP             EQU (0x1 << 24) ;- (CAN) Sampling mode
-// - -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- 
-AT91C_CAN_TIMER           EQU (0xFFFF <<  0) ;- (CAN) Timer field
-// - -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- 
-// - -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- 
-AT91C_CAN_REC             EQU (0xFF <<  0) ;- (CAN) Receive Error Counter
-AT91C_CAN_TEC             EQU (0xFF << 16) ;- (CAN) Transmit Error Counter
-// - -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- 
-AT91C_CAN_TIMRST          EQU (0x1 << 31) ;- (CAN) Timer Reset Field
-// - -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- 
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
-// - *****************************************************************************
-// - -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- 
-AT91C_EMAC_LB             EQU (0x1 <<  0) ;- (EMAC) Loopback. Optional. When set, loopback signal is at high level.
-AT91C_EMAC_LLB            EQU (0x1 <<  1) ;- (EMAC) Loopback local. 
-AT91C_EMAC_RE             EQU (0x1 <<  2) ;- (EMAC) Receive enable. 
-AT91C_EMAC_TE             EQU (0x1 <<  3) ;- (EMAC) Transmit enable. 
-AT91C_EMAC_MPE            EQU (0x1 <<  4) ;- (EMAC) Management port enable. 
-AT91C_EMAC_CLRSTAT        EQU (0x1 <<  5) ;- (EMAC) Clear statistics registers. 
-AT91C_EMAC_INCSTAT        EQU (0x1 <<  6) ;- (EMAC) Increment statistics registers. 
-AT91C_EMAC_WESTAT         EQU (0x1 <<  7) ;- (EMAC) Write enable for statistics registers. 
-AT91C_EMAC_BP             EQU (0x1 <<  8) ;- (EMAC) Back pressure. 
-AT91C_EMAC_TSTART         EQU (0x1 <<  9) ;- (EMAC) Start Transmission. 
-AT91C_EMAC_THALT          EQU (0x1 << 10) ;- (EMAC) Transmission Halt. 
-AT91C_EMAC_TPFR           EQU (0x1 << 11) ;- (EMAC) Transmit pause frame 
-AT91C_EMAC_TZQ            EQU (0x1 << 12) ;- (EMAC) Transmit zero quantum pause frame
-// - -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- 
-AT91C_EMAC_SPD            EQU (0x1 <<  0) ;- (EMAC) Speed. 
-AT91C_EMAC_FD             EQU (0x1 <<  1) ;- (EMAC) Full duplex. 
-AT91C_EMAC_JFRAME         EQU (0x1 <<  3) ;- (EMAC) Jumbo Frames. 
-AT91C_EMAC_CAF            EQU (0x1 <<  4) ;- (EMAC) Copy all frames. 
-AT91C_EMAC_NBC            EQU (0x1 <<  5) ;- (EMAC) No broadcast. 
-AT91C_EMAC_MTI            EQU (0x1 <<  6) ;- (EMAC) Multicast hash event enable
-AT91C_EMAC_UNI            EQU (0x1 <<  7) ;- (EMAC) Unicast hash enable. 
-AT91C_EMAC_BIG            EQU (0x1 <<  8) ;- (EMAC) Receive 1522 bytes. 
-AT91C_EMAC_EAE            EQU (0x1 <<  9) ;- (EMAC) External address match enable. 
-AT91C_EMAC_CLK            EQU (0x3 << 10) ;- (EMAC) 
-AT91C_EMAC_CLK_HCLK_8     EQU (0x0 << 10) ;- (EMAC) HCLK divided by 8
-AT91C_EMAC_CLK_HCLK_16    EQU (0x1 << 10) ;- (EMAC) HCLK divided by 16
-AT91C_EMAC_CLK_HCLK_32    EQU (0x2 << 10) ;- (EMAC) HCLK divided by 32
-AT91C_EMAC_CLK_HCLK_64    EQU (0x3 << 10) ;- (EMAC) HCLK divided by 64
-AT91C_EMAC_RTY            EQU (0x1 << 12) ;- (EMAC) 
-AT91C_EMAC_PAE            EQU (0x1 << 13) ;- (EMAC) 
-AT91C_EMAC_RBOF           EQU (0x3 << 14) ;- (EMAC) 
-AT91C_EMAC_RBOF_OFFSET_0  EQU (0x0 << 14) ;- (EMAC) no offset from start of receive buffer
-AT91C_EMAC_RBOF_OFFSET_1  EQU (0x1 << 14) ;- (EMAC) one byte offset from start of receive buffer
-AT91C_EMAC_RBOF_OFFSET_2  EQU (0x2 << 14) ;- (EMAC) two bytes offset from start of receive buffer
-AT91C_EMAC_RBOF_OFFSET_3  EQU (0x3 << 14) ;- (EMAC) three bytes offset from start of receive buffer
-AT91C_EMAC_RLCE           EQU (0x1 << 16) ;- (EMAC) Receive Length field Checking Enable
-AT91C_EMAC_DRFCS          EQU (0x1 << 17) ;- (EMAC) Discard Receive FCS
-AT91C_EMAC_EFRHD          EQU (0x1 << 18) ;- (EMAC) 
-AT91C_EMAC_IRXFCS         EQU (0x1 << 19) ;- (EMAC) Ignore RX FCS
-// - -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- 
-AT91C_EMAC_LINKR          EQU (0x1 <<  0) ;- (EMAC) 
-AT91C_EMAC_MDIO           EQU (0x1 <<  1) ;- (EMAC) 
-AT91C_EMAC_IDLE           EQU (0x1 <<  2) ;- (EMAC) 
-// - -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- 
-AT91C_EMAC_UBR            EQU (0x1 <<  0) ;- (EMAC) 
-AT91C_EMAC_COL            EQU (0x1 <<  1) ;- (EMAC) 
-AT91C_EMAC_RLES           EQU (0x1 <<  2) ;- (EMAC) 
-AT91C_EMAC_TGO            EQU (0x1 <<  3) ;- (EMAC) Transmit Go
-AT91C_EMAC_BEX            EQU (0x1 <<  4) ;- (EMAC) Buffers exhausted mid frame
-AT91C_EMAC_COMP           EQU (0x1 <<  5) ;- (EMAC) 
-AT91C_EMAC_UND            EQU (0x1 <<  6) ;- (EMAC) 
-// - -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- 
-AT91C_EMAC_BNA            EQU (0x1 <<  0) ;- (EMAC) 
-AT91C_EMAC_REC            EQU (0x1 <<  1) ;- (EMAC) 
-AT91C_EMAC_OVR            EQU (0x1 <<  2) ;- (EMAC) 
-// - -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- 
-AT91C_EMAC_MFD            EQU (0x1 <<  0) ;- (EMAC) 
-AT91C_EMAC_RCOMP          EQU (0x1 <<  1) ;- (EMAC) 
-AT91C_EMAC_RXUBR          EQU (0x1 <<  2) ;- (EMAC) 
-AT91C_EMAC_TXUBR          EQU (0x1 <<  3) ;- (EMAC) 
-AT91C_EMAC_TUNDR          EQU (0x1 <<  4) ;- (EMAC) 
-AT91C_EMAC_RLEX           EQU (0x1 <<  5) ;- (EMAC) 
-AT91C_EMAC_TXERR          EQU (0x1 <<  6) ;- (EMAC) 
-AT91C_EMAC_TCOMP          EQU (0x1 <<  7) ;- (EMAC) 
-AT91C_EMAC_LINK           EQU (0x1 <<  9) ;- (EMAC) 
-AT91C_EMAC_ROVR           EQU (0x1 << 10) ;- (EMAC) 
-AT91C_EMAC_HRESP          EQU (0x1 << 11) ;- (EMAC) 
-AT91C_EMAC_PFRE           EQU (0x1 << 12) ;- (EMAC) 
-AT91C_EMAC_PTZ            EQU (0x1 << 13) ;- (EMAC) 
-// - -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- 
-// - -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- 
-// - -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- 
-// - -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- 
-AT91C_EMAC_DATA           EQU (0xFFFF <<  0) ;- (EMAC) 
-AT91C_EMAC_CODE           EQU (0x3 << 16) ;- (EMAC) 
-AT91C_EMAC_REGA           EQU (0x1F << 18) ;- (EMAC) 
-AT91C_EMAC_PHYA           EQU (0x1F << 23) ;- (EMAC) 
-AT91C_EMAC_RW             EQU (0x3 << 28) ;- (EMAC) 
-AT91C_EMAC_SOF            EQU (0x3 << 30) ;- (EMAC) 
-// - -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- 
-AT91C_EMAC_RMII           EQU (0x1 <<  0) ;- (EMAC) Reduce MII
-// - -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- 
-AT91C_EMAC_IP             EQU (0xFFFF <<  0) ;- (EMAC) ARP request IP address
-AT91C_EMAC_MAG            EQU (0x1 << 16) ;- (EMAC) Magic packet event enable
-AT91C_EMAC_ARP            EQU (0x1 << 17) ;- (EMAC) ARP request event enable
-AT91C_EMAC_SA1            EQU (0x1 << 18) ;- (EMAC) Specific address register 1 event enable
-// - -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- 
-AT91C_EMAC_REVREF         EQU (0xFFFF <<  0) ;- (EMAC) 
-AT91C_EMAC_PARTREF        EQU (0xFFFF << 16) ;- (EMAC) 
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
-// - *****************************************************************************
-// - -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
-AT91C_ADC_SWRST           EQU (0x1 <<  0) ;- (ADC) Software Reset
-AT91C_ADC_START           EQU (0x1 <<  1) ;- (ADC) Start Conversion
-// - -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 
-AT91C_ADC_TRGEN           EQU (0x1 <<  0) ;- (ADC) Trigger Enable
-AT91C_ADC_TRGEN_DIS       EQU (0x0) ;- (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
-AT91C_ADC_TRGEN_EN        EQU (0x1) ;- (ADC) Hardware trigger selected by TRGSEL field is enabled.
-AT91C_ADC_TRGSEL          EQU (0x7 <<  1) ;- (ADC) Trigger Selection
-AT91C_ADC_TRGSEL_TIOA0    EQU (0x0 <<  1) ;- (ADC) Selected TRGSEL = TIAO0
-AT91C_ADC_TRGSEL_TIOA1    EQU (0x1 <<  1) ;- (ADC) Selected TRGSEL = TIAO1
-AT91C_ADC_TRGSEL_TIOA2    EQU (0x2 <<  1) ;- (ADC) Selected TRGSEL = TIAO2
-AT91C_ADC_TRGSEL_TIOA3    EQU (0x3 <<  1) ;- (ADC) Selected TRGSEL = TIAO3
-AT91C_ADC_TRGSEL_TIOA4    EQU (0x4 <<  1) ;- (ADC) Selected TRGSEL = TIAO4
-AT91C_ADC_TRGSEL_TIOA5    EQU (0x5 <<  1) ;- (ADC) Selected TRGSEL = TIAO5
-AT91C_ADC_TRGSEL_EXT      EQU (0x6 <<  1) ;- (ADC) Selected TRGSEL = External Trigger
-AT91C_ADC_LOWRES          EQU (0x1 <<  4) ;- (ADC) Resolution.
-AT91C_ADC_LOWRES_10_BIT   EQU (0x0 <<  4) ;- (ADC) 10-bit resolution
-AT91C_ADC_LOWRES_8_BIT    EQU (0x1 <<  4) ;- (ADC) 8-bit resolution
-AT91C_ADC_SLEEP           EQU (0x1 <<  5) ;- (ADC) Sleep Mode
-AT91C_ADC_SLEEP_NORMAL_MODE EQU (0x0 <<  5) ;- (ADC) Normal Mode
-AT91C_ADC_SLEEP_MODE      EQU (0x1 <<  5) ;- (ADC) Sleep Mode
-AT91C_ADC_PRESCAL         EQU (0x3F <<  8) ;- (ADC) Prescaler rate selection
-AT91C_ADC_STARTUP         EQU (0x1F << 16) ;- (ADC) Startup Time
-AT91C_ADC_SHTIM           EQU (0xF << 24) ;- (ADC) Sample & Hold Time
-// - -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 
-AT91C_ADC_CH0             EQU (0x1 <<  0) ;- (ADC) Channel 0
-AT91C_ADC_CH1             EQU (0x1 <<  1) ;- (ADC) Channel 1
-AT91C_ADC_CH2             EQU (0x1 <<  2) ;- (ADC) Channel 2
-AT91C_ADC_CH3             EQU (0x1 <<  3) ;- (ADC) Channel 3
-AT91C_ADC_CH4             EQU (0x1 <<  4) ;- (ADC) Channel 4
-AT91C_ADC_CH5             EQU (0x1 <<  5) ;- (ADC) Channel 5
-AT91C_ADC_CH6             EQU (0x1 <<  6) ;- (ADC) Channel 6
-AT91C_ADC_CH7             EQU (0x1 <<  7) ;- (ADC) Channel 7
-// - -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 
-// - -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 
-// - -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 
-AT91C_ADC_EOC0            EQU (0x1 <<  0) ;- (ADC) End of Conversion
-AT91C_ADC_EOC1            EQU (0x1 <<  1) ;- (ADC) End of Conversion
-AT91C_ADC_EOC2            EQU (0x1 <<  2) ;- (ADC) End of Conversion
-AT91C_ADC_EOC3            EQU (0x1 <<  3) ;- (ADC) End of Conversion
-AT91C_ADC_EOC4            EQU (0x1 <<  4) ;- (ADC) End of Conversion
-AT91C_ADC_EOC5            EQU (0x1 <<  5) ;- (ADC) End of Conversion
-AT91C_ADC_EOC6            EQU (0x1 <<  6) ;- (ADC) End of Conversion
-AT91C_ADC_EOC7            EQU (0x1 <<  7) ;- (ADC) End of Conversion
-AT91C_ADC_OVRE0           EQU (0x1 <<  8) ;- (ADC) Overrun Error
-AT91C_ADC_OVRE1           EQU (0x1 <<  9) ;- (ADC) Overrun Error
-AT91C_ADC_OVRE2           EQU (0x1 << 10) ;- (ADC) Overrun Error
-AT91C_ADC_OVRE3           EQU (0x1 << 11) ;- (ADC) Overrun Error
-AT91C_ADC_OVRE4           EQU (0x1 << 12) ;- (ADC) Overrun Error
-AT91C_ADC_OVRE5           EQU (0x1 << 13) ;- (ADC) Overrun Error
-AT91C_ADC_OVRE6           EQU (0x1 << 14) ;- (ADC) Overrun Error
-AT91C_ADC_OVRE7           EQU (0x1 << 15) ;- (ADC) Overrun Error
-AT91C_ADC_DRDY            EQU (0x1 << 16) ;- (ADC) Data Ready
-AT91C_ADC_GOVRE           EQU (0x1 << 17) ;- (ADC) General Overrun
-AT91C_ADC_ENDRX           EQU (0x1 << 18) ;- (ADC) End of Receiver Transfer
-AT91C_ADC_RXBUFF          EQU (0x1 << 19) ;- (ADC) RXBUFF Interrupt
-// - -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 
-AT91C_ADC_LDATA           EQU (0x3FF <<  0) ;- (ADC) Last Data Converted
-// - -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 
-// - -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 
-// - -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 
-// - -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 
-AT91C_ADC_DATA            EQU (0x3FF <<  0) ;- (ADC) Converted Data
-// - -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 
-// - -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 
-// - -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 
-// - -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 
-// - -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 
-// - -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 
-// - -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard
-// - *****************************************************************************
-// - -------- AES_CR : (AES Offset: 0x0) Control Register -------- 
-AT91C_AES_START           EQU (0x1 <<  0) ;- (AES) Starts Processing
-AT91C_AES_SWRST           EQU (0x1 <<  8) ;- (AES) Software Reset
-AT91C_AES_LOADSEED        EQU (0x1 << 16) ;- (AES) Random Number Generator Seed Loading
-// - -------- AES_MR : (AES Offset: 0x4) Mode Register -------- 
-AT91C_AES_CIPHER          EQU (0x1 <<  0) ;- (AES) Processing Mode
-AT91C_AES_PROCDLY         EQU (0xF <<  4) ;- (AES) Processing Delay
-AT91C_AES_SMOD            EQU (0x3 <<  8) ;- (AES) Start Mode
-AT91C_AES_SMOD_MANUAL     EQU (0x0 <<  8) ;- (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
-AT91C_AES_SMOD_AUTO       EQU (0x1 <<  8) ;- (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
-AT91C_AES_SMOD_PDC        EQU (0x2 <<  8) ;- (AES) PDC Mode (cf datasheet).
-AT91C_AES_OPMOD           EQU (0x7 << 12) ;- (AES) Operation Mode
-AT91C_AES_OPMOD_ECB       EQU (0x0 << 12) ;- (AES) ECB Electronic CodeBook mode.
-AT91C_AES_OPMOD_CBC       EQU (0x1 << 12) ;- (AES) CBC Cipher Block Chaining mode.
-AT91C_AES_OPMOD_OFB       EQU (0x2 << 12) ;- (AES) OFB Output Feedback mode.
-AT91C_AES_OPMOD_CFB       EQU (0x3 << 12) ;- (AES) CFB Cipher Feedback mode.
-AT91C_AES_OPMOD_CTR       EQU (0x4 << 12) ;- (AES) CTR Counter mode.
-AT91C_AES_LOD             EQU (0x1 << 15) ;- (AES) Last Output Data Mode
-AT91C_AES_CFBS            EQU (0x7 << 16) ;- (AES) Cipher Feedback Data Size
-AT91C_AES_CFBS_128_BIT    EQU (0x0 << 16) ;- (AES) 128-bit.
-AT91C_AES_CFBS_64_BIT     EQU (0x1 << 16) ;- (AES) 64-bit.
-AT91C_AES_CFBS_32_BIT     EQU (0x2 << 16) ;- (AES) 32-bit.
-AT91C_AES_CFBS_16_BIT     EQU (0x3 << 16) ;- (AES) 16-bit.
-AT91C_AES_CFBS_8_BIT      EQU (0x4 << 16) ;- (AES) 8-bit.
-AT91C_AES_CKEY            EQU (0xF << 20) ;- (AES) Countermeasure Key
-AT91C_AES_CTYPE           EQU (0x1F << 24) ;- (AES) Countermeasure Type
-AT91C_AES_CTYPE_TYPE1_EN  EQU (0x1 << 24) ;- (AES) Countermeasure type 1 is enabled.
-AT91C_AES_CTYPE_TYPE2_EN  EQU (0x2 << 24) ;- (AES) Countermeasure type 2 is enabled.
-AT91C_AES_CTYPE_TYPE3_EN  EQU (0x4 << 24) ;- (AES) Countermeasure type 3 is enabled.
-AT91C_AES_CTYPE_TYPE4_EN  EQU (0x8 << 24) ;- (AES) Countermeasure type 4 is enabled.
-AT91C_AES_CTYPE_TYPE5_EN  EQU (0x10 << 24) ;- (AES) Countermeasure type 5 is enabled.
-// - -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- 
-AT91C_AES_DATRDY          EQU (0x1 <<  0) ;- (AES) DATRDY
-AT91C_AES_ENDRX           EQU (0x1 <<  1) ;- (AES) PDC Read Buffer End
-AT91C_AES_ENDTX           EQU (0x1 <<  2) ;- (AES) PDC Write Buffer End
-AT91C_AES_RXBUFF          EQU (0x1 <<  3) ;- (AES) PDC Read Buffer Full
-AT91C_AES_TXBUFE          EQU (0x1 <<  4) ;- (AES) PDC Write Buffer Empty
-AT91C_AES_URAD            EQU (0x1 <<  8) ;- (AES) Unspecified Register Access Detection
-// - -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- 
-// - -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- 
-// - -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- 
-AT91C_AES_URAT            EQU (0x7 << 12) ;- (AES) Unspecified Register Access Type Status
-AT91C_AES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (AES) Input data register written during the data processing in PDC mode.
-AT91C_AES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (AES) Output data register read during the data processing.
-AT91C_AES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (AES) Mode register written during the data processing.
-AT91C_AES_URAT_OUT_DAT_READ_SUBKEY EQU (0x3 << 12) ;- (AES) Output data register read during the sub-keys generation.
-AT91C_AES_URAT_MODEREG_WRITE_SUBKEY EQU (0x4 << 12) ;- (AES) Mode register written during the sub-keys generation.
-AT91C_AES_URAT_WO_REG_READ EQU (0x5 << 12) ;- (AES) Write-only register read access.
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard
-// - *****************************************************************************
-// - -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- 
-AT91C_TDES_START          EQU (0x1 <<  0) ;- (TDES) Starts Processing
-AT91C_TDES_SWRST          EQU (0x1 <<  8) ;- (TDES) Software Reset
-// - -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- 
-AT91C_TDES_CIPHER         EQU (0x1 <<  0) ;- (TDES) Processing Mode
-AT91C_TDES_TDESMOD        EQU (0x1 <<  1) ;- (TDES) Single or Triple DES Mode
-AT91C_TDES_KEYMOD         EQU (0x1 <<  4) ;- (TDES) Key Mode
-AT91C_TDES_SMOD           EQU (0x3 <<  8) ;- (TDES) Start Mode
-AT91C_TDES_SMOD_MANUAL    EQU (0x0 <<  8) ;- (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
-AT91C_TDES_SMOD_AUTO      EQU (0x1 <<  8) ;- (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
-AT91C_TDES_SMOD_PDC       EQU (0x2 <<  8) ;- (TDES) PDC Mode (cf datasheet).
-AT91C_TDES_OPMOD          EQU (0x3 << 12) ;- (TDES) Operation Mode
-AT91C_TDES_OPMOD_ECB      EQU (0x0 << 12) ;- (TDES) ECB Electronic CodeBook mode.
-AT91C_TDES_OPMOD_CBC      EQU (0x1 << 12) ;- (TDES) CBC Cipher Block Chaining mode.
-AT91C_TDES_OPMOD_OFB      EQU (0x2 << 12) ;- (TDES) OFB Output Feedback mode.
-AT91C_TDES_OPMOD_CFB      EQU (0x3 << 12) ;- (TDES) CFB Cipher Feedback mode.
-AT91C_TDES_LOD            EQU (0x1 << 15) ;- (TDES) Last Output Data Mode
-AT91C_TDES_CFBS           EQU (0x3 << 16) ;- (TDES) Cipher Feedback Data Size
-AT91C_TDES_CFBS_64_BIT    EQU (0x0 << 16) ;- (TDES) 64-bit.
-AT91C_TDES_CFBS_32_BIT    EQU (0x1 << 16) ;- (TDES) 32-bit.
-AT91C_TDES_CFBS_16_BIT    EQU (0x2 << 16) ;- (TDES) 16-bit.
-AT91C_TDES_CFBS_8_BIT     EQU (0x3 << 16) ;- (TDES) 8-bit.
-// - -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- 
-AT91C_TDES_DATRDY         EQU (0x1 <<  0) ;- (TDES) DATRDY
-AT91C_TDES_ENDRX          EQU (0x1 <<  1) ;- (TDES) PDC Read Buffer End
-AT91C_TDES_ENDTX          EQU (0x1 <<  2) ;- (TDES) PDC Write Buffer End
-AT91C_TDES_RXBUFF         EQU (0x1 <<  3) ;- (TDES) PDC Read Buffer Full
-AT91C_TDES_TXBUFE         EQU (0x1 <<  4) ;- (TDES) PDC Write Buffer Empty
-AT91C_TDES_URAD           EQU (0x1 <<  8) ;- (TDES) Unspecified Register Access Detection
-// - -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- 
-// - -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- 
-// - -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- 
-AT91C_TDES_URAT           EQU (0x3 << 12) ;- (TDES) Unspecified Register Access Type Status
-AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (TDES) Input data register written during the data processing in PDC mode.
-AT91C_TDES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (TDES) Output data register read during the data processing.
-AT91C_TDES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (TDES) Mode register written during the data processing.
-AT91C_TDES_URAT_WO_REG_READ EQU (0x3 << 12) ;- (TDES) Write-only register read access.
-
-// - *****************************************************************************
-// -               REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
-// - *****************************************************************************
-// - ========== Register definition for SYS peripheral ========== 
-// - ========== Register definition for AIC peripheral ========== 
-AT91C_AIC_IVR             EQU (0xFFFFF100) ;- (AIC) IRQ Vector Register
-AT91C_AIC_SMR             EQU (0xFFFFF000) ;- (AIC) Source Mode Register
-AT91C_AIC_FVR             EQU (0xFFFFF104) ;- (AIC) FIQ Vector Register
-AT91C_AIC_DCR             EQU (0xFFFFF138) ;- (AIC) Debug Control Register (Protect)
-AT91C_AIC_EOICR           EQU (0xFFFFF130) ;- (AIC) End of Interrupt Command Register
-AT91C_AIC_SVR             EQU (0xFFFFF080) ;- (AIC) Source Vector Register
-AT91C_AIC_FFSR            EQU (0xFFFFF148) ;- (AIC) Fast Forcing Status Register
-AT91C_AIC_ICCR            EQU (0xFFFFF128) ;- (AIC) Interrupt Clear Command Register
-AT91C_AIC_ISR             EQU (0xFFFFF108) ;- (AIC) Interrupt Status Register
-AT91C_AIC_IMR             EQU (0xFFFFF110) ;- (AIC) Interrupt Mask Register
-AT91C_AIC_IPR             EQU (0xFFFFF10C) ;- (AIC) Interrupt Pending Register
-AT91C_AIC_FFER            EQU (0xFFFFF140) ;- (AIC) Fast Forcing Enable Register
-AT91C_AIC_IECR            EQU (0xFFFFF120) ;- (AIC) Interrupt Enable Command Register
-AT91C_AIC_ISCR            EQU (0xFFFFF12C) ;- (AIC) Interrupt Set Command Register
-AT91C_AIC_FFDR            EQU (0xFFFFF144) ;- (AIC) Fast Forcing Disable Register
-AT91C_AIC_CISR            EQU (0xFFFFF114) ;- (AIC) Core Interrupt Status Register
-AT91C_AIC_IDCR            EQU (0xFFFFF124) ;- (AIC) Interrupt Disable Command Register
-AT91C_AIC_SPU             EQU (0xFFFFF134) ;- (AIC) Spurious Vector Register
-// - ========== Register definition for PDC_DBGU peripheral ========== 
-AT91C_DBGU_TCR            EQU (0xFFFFF30C) ;- (PDC_DBGU) Transmit Counter Register
-AT91C_DBGU_RNPR           EQU (0xFFFFF310) ;- (PDC_DBGU) Receive Next Pointer Register
-AT91C_DBGU_TNPR           EQU (0xFFFFF318) ;- (PDC_DBGU) Transmit Next Pointer Register
-AT91C_DBGU_TPR            EQU (0xFFFFF308) ;- (PDC_DBGU) Transmit Pointer Register
-AT91C_DBGU_RPR            EQU (0xFFFFF300) ;- (PDC_DBGU) Receive Pointer Register
-AT91C_DBGU_RCR            EQU (0xFFFFF304) ;- (PDC_DBGU) Receive Counter Register
-AT91C_DBGU_RNCR           EQU (0xFFFFF314) ;- (PDC_DBGU) Receive Next Counter Register
-AT91C_DBGU_PTCR           EQU (0xFFFFF320) ;- (PDC_DBGU) PDC Transfer Control Register
-AT91C_DBGU_PTSR           EQU (0xFFFFF324) ;- (PDC_DBGU) PDC Transfer Status Register
-AT91C_DBGU_TNCR           EQU (0xFFFFF31C) ;- (PDC_DBGU) Transmit Next Counter Register
-// - ========== Register definition for DBGU peripheral ========== 
-AT91C_DBGU_EXID           EQU (0xFFFFF244) ;- (DBGU) Chip ID Extension Register
-AT91C_DBGU_BRGR           EQU (0xFFFFF220) ;- (DBGU) Baud Rate Generator Register
-AT91C_DBGU_IDR            EQU (0xFFFFF20C) ;- (DBGU) Interrupt Disable Register
-AT91C_DBGU_CSR            EQU (0xFFFFF214) ;- (DBGU) Channel Status Register
-AT91C_DBGU_CIDR           EQU (0xFFFFF240) ;- (DBGU) Chip ID Register
-AT91C_DBGU_MR             EQU (0xFFFFF204) ;- (DBGU) Mode Register
-AT91C_DBGU_IMR            EQU (0xFFFFF210) ;- (DBGU) Interrupt Mask Register
-AT91C_DBGU_CR             EQU (0xFFFFF200) ;- (DBGU) Control Register
-AT91C_DBGU_FNTR           EQU (0xFFFFF248) ;- (DBGU) Force NTRST Register
-AT91C_DBGU_THR            EQU (0xFFFFF21C) ;- (DBGU) Transmitter Holding Register
-AT91C_DBGU_RHR            EQU (0xFFFFF218) ;- (DBGU) Receiver Holding Register
-AT91C_DBGU_IER            EQU (0xFFFFF208) ;- (DBGU) Interrupt Enable Register
-// - ========== Register definition for PIOA peripheral ========== 
-AT91C_PIOA_ODR            EQU (0xFFFFF414) ;- (PIOA) Output Disable Registerr
-AT91C_PIOA_SODR           EQU (0xFFFFF430) ;- (PIOA) Set Output Data Register
-AT91C_PIOA_ISR            EQU (0xFFFFF44C) ;- (PIOA) Interrupt Status Register
-AT91C_PIOA_ABSR           EQU (0xFFFFF478) ;- (PIOA) AB Select Status Register
-AT91C_PIOA_IER            EQU (0xFFFFF440) ;- (PIOA) Interrupt Enable Register
-AT91C_PIOA_PPUDR          EQU (0xFFFFF460) ;- (PIOA) Pull-up Disable Register
-AT91C_PIOA_IMR            EQU (0xFFFFF448) ;- (PIOA) Interrupt Mask Register
-AT91C_PIOA_PER            EQU (0xFFFFF400) ;- (PIOA) PIO Enable Register
-AT91C_PIOA_IFDR           EQU (0xFFFFF424) ;- (PIOA) Input Filter Disable Register
-AT91C_PIOA_OWDR           EQU (0xFFFFF4A4) ;- (PIOA) Output Write Disable Register
-AT91C_PIOA_MDSR           EQU (0xFFFFF458) ;- (PIOA) Multi-driver Status Register
-AT91C_PIOA_IDR            EQU (0xFFFFF444) ;- (PIOA) Interrupt Disable Register
-AT91C_PIOA_ODSR           EQU (0xFFFFF438) ;- (PIOA) Output Data Status Register
-AT91C_PIOA_PPUSR          EQU (0xFFFFF468) ;- (PIOA) Pull-up Status Register
-AT91C_PIOA_OWSR           EQU (0xFFFFF4A8) ;- (PIOA) Output Write Status Register
-AT91C_PIOA_BSR            EQU (0xFFFFF474) ;- (PIOA) Select B Register
-AT91C_PIOA_OWER           EQU (0xFFFFF4A0) ;- (PIOA) Output Write Enable Register
-AT91C_PIOA_IFER           EQU (0xFFFFF420) ;- (PIOA) Input Filter Enable Register
-AT91C_PIOA_PDSR           EQU (0xFFFFF43C) ;- (PIOA) Pin Data Status Register
-AT91C_PIOA_PPUER          EQU (0xFFFFF464) ;- (PIOA) Pull-up Enable Register
-AT91C_PIOA_OSR            EQU (0xFFFFF418) ;- (PIOA) Output Status Register
-AT91C_PIOA_ASR            EQU (0xFFFFF470) ;- (PIOA) Select A Register
-AT91C_PIOA_MDDR           EQU (0xFFFFF454) ;- (PIOA) Multi-driver Disable Register
-AT91C_PIOA_CODR           EQU (0xFFFFF434) ;- (PIOA) Clear Output Data Register
-AT91C_PIOA_MDER           EQU (0xFFFFF450) ;- (PIOA) Multi-driver Enable Register
-AT91C_PIOA_PDR            EQU (0xFFFFF404) ;- (PIOA) PIO Disable Register
-AT91C_PIOA_IFSR           EQU (0xFFFFF428) ;- (PIOA) Input Filter Status Register
-AT91C_PIOA_OER            EQU (0xFFFFF410) ;- (PIOA) Output Enable Register
-AT91C_PIOA_PSR            EQU (0xFFFFF408) ;- (PIOA) PIO Status Register
-// - ========== Register definition for PIOB peripheral ========== 
-AT91C_PIOB_OWDR           EQU (0xFFFFF6A4) ;- (PIOB) Output Write Disable Register
-AT91C_PIOB_MDER           EQU (0xFFFFF650) ;- (PIOB) Multi-driver Enable Register
-AT91C_PIOB_PPUSR          EQU (0xFFFFF668) ;- (PIOB) Pull-up Status Register
-AT91C_PIOB_IMR            EQU (0xFFFFF648) ;- (PIOB) Interrupt Mask Register
-AT91C_PIOB_ASR            EQU (0xFFFFF670) ;- (PIOB) Select A Register
-AT91C_PIOB_PPUDR          EQU (0xFFFFF660) ;- (PIOB) Pull-up Disable Register
-AT91C_PIOB_PSR            EQU (0xFFFFF608) ;- (PIOB) PIO Status Register
-AT91C_PIOB_IER            EQU (0xFFFFF640) ;- (PIOB) Interrupt Enable Register
-AT91C_PIOB_CODR           EQU (0xFFFFF634) ;- (PIOB) Clear Output Data Register
-AT91C_PIOB_OWER           EQU (0xFFFFF6A0) ;- (PIOB) Output Write Enable Register
-AT91C_PIOB_ABSR           EQU (0xFFFFF678) ;- (PIOB) AB Select Status Register
-AT91C_PIOB_IFDR           EQU (0xFFFFF624) ;- (PIOB) Input Filter Disable Register
-AT91C_PIOB_PDSR           EQU (0xFFFFF63C) ;- (PIOB) Pin Data Status Register
-AT91C_PIOB_IDR            EQU (0xFFFFF644) ;- (PIOB) Interrupt Disable Register
-AT91C_PIOB_OWSR           EQU (0xFFFFF6A8) ;- (PIOB) Output Write Status Register
-AT91C_PIOB_PDR            EQU (0xFFFFF604) ;- (PIOB) PIO Disable Register
-AT91C_PIOB_ODR            EQU (0xFFFFF614) ;- (PIOB) Output Disable Registerr
-AT91C_PIOB_IFSR           EQU (0xFFFFF628) ;- (PIOB) Input Filter Status Register
-AT91C_PIOB_PPUER          EQU (0xFFFFF664) ;- (PIOB) Pull-up Enable Register
-AT91C_PIOB_SODR           EQU (0xFFFFF630) ;- (PIOB) Set Output Data Register
-AT91C_PIOB_ISR            EQU (0xFFFFF64C) ;- (PIOB) Interrupt Status Register
-AT91C_PIOB_ODSR           EQU (0xFFFFF638) ;- (PIOB) Output Data Status Register
-AT91C_PIOB_OSR            EQU (0xFFFFF618) ;- (PIOB) Output Status Register
-AT91C_PIOB_MDSR           EQU (0xFFFFF658) ;- (PIOB) Multi-driver Status Register
-AT91C_PIOB_IFER           EQU (0xFFFFF620) ;- (PIOB) Input Filter Enable Register
-AT91C_PIOB_BSR            EQU (0xFFFFF674) ;- (PIOB) Select B Register
-AT91C_PIOB_MDDR           EQU (0xFFFFF654) ;- (PIOB) Multi-driver Disable Register
-AT91C_PIOB_OER            EQU (0xFFFFF610) ;- (PIOB) Output Enable Register
-AT91C_PIOB_PER            EQU (0xFFFFF600) ;- (PIOB) PIO Enable Register
-// - ========== Register definition for CKGR peripheral ========== 
-AT91C_CKGR_MOR            EQU (0xFFFFFC20) ;- (CKGR) Main Oscillator Register
-AT91C_CKGR_PLLR           EQU (0xFFFFFC2C) ;- (CKGR) PLL Register
-AT91C_CKGR_MCFR           EQU (0xFFFFFC24) ;- (CKGR) Main Clock  Frequency Register
-// - ========== Register definition for PMC peripheral ========== 
-AT91C_PMC_IDR             EQU (0xFFFFFC64) ;- (PMC) Interrupt Disable Register
-AT91C_PMC_MOR             EQU (0xFFFFFC20) ;- (PMC) Main Oscillator Register
-AT91C_PMC_PLLR            EQU (0xFFFFFC2C) ;- (PMC) PLL Register
-AT91C_PMC_PCER            EQU (0xFFFFFC10) ;- (PMC) Peripheral Clock Enable Register
-AT91C_PMC_PCKR            EQU (0xFFFFFC40) ;- (PMC) Programmable Clock Register
-AT91C_PMC_MCKR            EQU (0xFFFFFC30) ;- (PMC) Master Clock Register
-AT91C_PMC_SCDR            EQU (0xFFFFFC04) ;- (PMC) System Clock Disable Register
-AT91C_PMC_PCDR            EQU (0xFFFFFC14) ;- (PMC) Peripheral Clock Disable Register
-AT91C_PMC_SCSR            EQU (0xFFFFFC08) ;- (PMC) System Clock Status Register
-AT91C_PMC_PCSR            EQU (0xFFFFFC18) ;- (PMC) Peripheral Clock Status Register
-AT91C_PMC_MCFR            EQU (0xFFFFFC24) ;- (PMC) Main Clock  Frequency Register
-AT91C_PMC_SCER            EQU (0xFFFFFC00) ;- (PMC) System Clock Enable Register
-AT91C_PMC_IMR             EQU (0xFFFFFC6C) ;- (PMC) Interrupt Mask Register
-AT91C_PMC_IER             EQU (0xFFFFFC60) ;- (PMC) Interrupt Enable Register
-AT91C_PMC_SR              EQU (0xFFFFFC68) ;- (PMC) Status Register
-// - ========== Register definition for RSTC peripheral ========== 
-AT91C_RSTC_RCR            EQU (0xFFFFFD00) ;- (RSTC) Reset Control Register
-AT91C_RSTC_RMR            EQU (0xFFFFFD08) ;- (RSTC) Reset Mode Register
-AT91C_RSTC_RSR            EQU (0xFFFFFD04) ;- (RSTC) Reset Status Register
-// - ========== Register definition for RTTC peripheral ========== 
-AT91C_RTTC_RTSR           EQU (0xFFFFFD2C) ;- (RTTC) Real-time Status Register
-AT91C_RTTC_RTMR           EQU (0xFFFFFD20) ;- (RTTC) Real-time Mode Register
-AT91C_RTTC_RTVR           EQU (0xFFFFFD28) ;- (RTTC) Real-time Value Register
-AT91C_RTTC_RTAR           EQU (0xFFFFFD24) ;- (RTTC) Real-time Alarm Register
-// - ========== Register definition for PITC peripheral ========== 
-AT91C_PITC_PIVR           EQU (0xFFFFFD38) ;- (PITC) Period Interval Value Register
-AT91C_PITC_PISR           EQU (0xFFFFFD34) ;- (PITC) Period Interval Status Register
-AT91C_PITC_PIIR           EQU (0xFFFFFD3C) ;- (PITC) Period Interval Image Register
-AT91C_PITC_PIMR           EQU (0xFFFFFD30) ;- (PITC) Period Interval Mode Register
-// - ========== Register definition for WDTC peripheral ========== 
-AT91C_WDTC_WDCR           EQU (0xFFFFFD40) ;- (WDTC) Watchdog Control Register
-AT91C_WDTC_WDSR           EQU (0xFFFFFD48) ;- (WDTC) Watchdog Status Register
-AT91C_WDTC_WDMR           EQU (0xFFFFFD44) ;- (WDTC) Watchdog Mode Register
-// - ========== Register definition for VREG peripheral ========== 
-AT91C_VREG_MR             EQU (0xFFFFFD60) ;- (VREG) Voltage Regulator Mode Register
-// - ========== Register definition for MC peripheral ========== 
-AT91C_MC_ASR              EQU (0xFFFFFF04) ;- (MC) MC Abort Status Register
-AT91C_MC_RCR              EQU (0xFFFFFF00) ;- (MC) MC Remap Control Register
-AT91C_MC_FCR              EQU (0xFFFFFF64) ;- (MC) MC Flash Command Register
-AT91C_MC_AASR             EQU (0xFFFFFF08) ;- (MC) MC Abort Address Status Register
-AT91C_MC_FSR              EQU (0xFFFFFF68) ;- (MC) MC Flash Status Register
-AT91C_MC_FMR              EQU (0xFFFFFF60) ;- (MC) MC Flash Mode Register
-// - ========== Register definition for PDC_SPI1 peripheral ========== 
-AT91C_SPI1_PTCR           EQU (0xFFFE4120) ;- (PDC_SPI1) PDC Transfer Control Register
-AT91C_SPI1_RPR            EQU (0xFFFE4100) ;- (PDC_SPI1) Receive Pointer Register
-AT91C_SPI1_TNCR           EQU (0xFFFE411C) ;- (PDC_SPI1) Transmit Next Counter Register
-AT91C_SPI1_TPR            EQU (0xFFFE4108) ;- (PDC_SPI1) Transmit Pointer Register
-AT91C_SPI1_TNPR           EQU (0xFFFE4118) ;- (PDC_SPI1) Transmit Next Pointer Register
-AT91C_SPI1_TCR            EQU (0xFFFE410C) ;- (PDC_SPI1) Transmit Counter Register
-AT91C_SPI1_RCR            EQU (0xFFFE4104) ;- (PDC_SPI1) Receive Counter Register
-AT91C_SPI1_RNPR           EQU (0xFFFE4110) ;- (PDC_SPI1) Receive Next Pointer Register
-AT91C_SPI1_RNCR           EQU (0xFFFE4114) ;- (PDC_SPI1) Receive Next Counter Register
-AT91C_SPI1_PTSR           EQU (0xFFFE4124) ;- (PDC_SPI1) PDC Transfer Status Register
-// - ========== Register definition for SPI1 peripheral ========== 
-AT91C_SPI1_IMR            EQU (0xFFFE401C) ;- (SPI1) Interrupt Mask Register
-AT91C_SPI1_IER            EQU (0xFFFE4014) ;- (SPI1) Interrupt Enable Register
-AT91C_SPI1_MR             EQU (0xFFFE4004) ;- (SPI1) Mode Register
-AT91C_SPI1_RDR            EQU (0xFFFE4008) ;- (SPI1) Receive Data Register
-AT91C_SPI1_IDR            EQU (0xFFFE4018) ;- (SPI1) Interrupt Disable Register
-AT91C_SPI1_SR             EQU (0xFFFE4010) ;- (SPI1) Status Register
-AT91C_SPI1_TDR            EQU (0xFFFE400C) ;- (SPI1) Transmit Data Register
-AT91C_SPI1_CR             EQU (0xFFFE4000) ;- (SPI1) Control Register
-AT91C_SPI1_CSR            EQU (0xFFFE4030) ;- (SPI1) Chip Select Register
-// - ========== Register definition for PDC_SPI0 peripheral ========== 
-AT91C_SPI0_PTCR           EQU (0xFFFE0120) ;- (PDC_SPI0) PDC Transfer Control Register
-AT91C_SPI0_TPR            EQU (0xFFFE0108) ;- (PDC_SPI0) Transmit Pointer Register
-AT91C_SPI0_TCR            EQU (0xFFFE010C) ;- (PDC_SPI0) Transmit Counter Register
-AT91C_SPI0_RCR            EQU (0xFFFE0104) ;- (PDC_SPI0) Receive Counter Register
-AT91C_SPI0_PTSR           EQU (0xFFFE0124) ;- (PDC_SPI0) PDC Transfer Status Register
-AT91C_SPI0_RNPR           EQU (0xFFFE0110) ;- (PDC_SPI0) Receive Next Pointer Register
-AT91C_SPI0_RPR            EQU (0xFFFE0100) ;- (PDC_SPI0) Receive Pointer Register
-AT91C_SPI0_TNCR           EQU (0xFFFE011C) ;- (PDC_SPI0) Transmit Next Counter Register
-AT91C_SPI0_RNCR           EQU (0xFFFE0114) ;- (PDC_SPI0) Receive Next Counter Register
-AT91C_SPI0_TNPR           EQU (0xFFFE0118) ;- (PDC_SPI0) Transmit Next Pointer Register
-// - ========== Register definition for SPI0 peripheral ========== 
-AT91C_SPI0_IER            EQU (0xFFFE0014) ;- (SPI0) Interrupt Enable Register
-AT91C_SPI0_SR             EQU (0xFFFE0010) ;- (SPI0) Status Register
-AT91C_SPI0_IDR            EQU (0xFFFE0018) ;- (SPI0) Interrupt Disable Register
-AT91C_SPI0_CR             EQU (0xFFFE0000) ;- (SPI0) Control Register
-AT91C_SPI0_MR             EQU (0xFFFE0004) ;- (SPI0) Mode Register
-AT91C_SPI0_IMR            EQU (0xFFFE001C) ;- (SPI0) Interrupt Mask Register
-AT91C_SPI0_TDR            EQU (0xFFFE000C) ;- (SPI0) Transmit Data Register
-AT91C_SPI0_RDR            EQU (0xFFFE0008) ;- (SPI0) Receive Data Register
-AT91C_SPI0_CSR            EQU (0xFFFE0030) ;- (SPI0) Chip Select Register
-// - ========== Register definition for PDC_US1 peripheral ========== 
-AT91C_US1_RNCR            EQU (0xFFFC4114) ;- (PDC_US1) Receive Next Counter Register
-AT91C_US1_PTCR            EQU (0xFFFC4120) ;- (PDC_US1) PDC Transfer Control Register
-AT91C_US1_TCR             EQU (0xFFFC410C) ;- (PDC_US1) Transmit Counter Register
-AT91C_US1_PTSR            EQU (0xFFFC4124) ;- (PDC_US1) PDC Transfer Status Register
-AT91C_US1_TNPR            EQU (0xFFFC4118) ;- (PDC_US1) Transmit Next Pointer Register
-AT91C_US1_RCR             EQU (0xFFFC4104) ;- (PDC_US1) Receive Counter Register
-AT91C_US1_RNPR            EQU (0xFFFC4110) ;- (PDC_US1) Receive Next Pointer Register
-AT91C_US1_RPR             EQU (0xFFFC4100) ;- (PDC_US1) Receive Pointer Register
-AT91C_US1_TNCR            EQU (0xFFFC411C) ;- (PDC_US1) Transmit Next Counter Register
-AT91C_US1_TPR             EQU (0xFFFC4108) ;- (PDC_US1) Transmit Pointer Register
-// - ========== Register definition for US1 peripheral ========== 
-AT91C_US1_IF              EQU (0xFFFC404C) ;- (US1) IRDA_FILTER Register
-AT91C_US1_NER             EQU (0xFFFC4044) ;- (US1) Nb Errors Register
-AT91C_US1_RTOR            EQU (0xFFFC4024) ;- (US1) Receiver Time-out Register
-AT91C_US1_CSR             EQU (0xFFFC4014) ;- (US1) Channel Status Register
-AT91C_US1_IDR             EQU (0xFFFC400C) ;- (US1) Interrupt Disable Register
-AT91C_US1_IER             EQU (0xFFFC4008) ;- (US1) Interrupt Enable Register
-AT91C_US1_THR             EQU (0xFFFC401C) ;- (US1) Transmitter Holding Register
-AT91C_US1_TTGR            EQU (0xFFFC4028) ;- (US1) Transmitter Time-guard Register
-AT91C_US1_RHR             EQU (0xFFFC4018) ;- (US1) Receiver Holding Register
-AT91C_US1_BRGR            EQU (0xFFFC4020) ;- (US1) Baud Rate Generator Register
-AT91C_US1_IMR             EQU (0xFFFC4010) ;- (US1) Interrupt Mask Register
-AT91C_US1_FIDI            EQU (0xFFFC4040) ;- (US1) FI_DI_Ratio Register
-AT91C_US1_CR              EQU (0xFFFC4000) ;- (US1) Control Register
-AT91C_US1_MR              EQU (0xFFFC4004) ;- (US1) Mode Register
-// - ========== Register definition for PDC_US0 peripheral ========== 
-AT91C_US0_TNPR            EQU (0xFFFC0118) ;- (PDC_US0) Transmit Next Pointer Register
-AT91C_US0_RNPR            EQU (0xFFFC0110) ;- (PDC_US0) Receive Next Pointer Register
-AT91C_US0_TCR             EQU (0xFFFC010C) ;- (PDC_US0) Transmit Counter Register
-AT91C_US0_PTCR            EQU (0xFFFC0120) ;- (PDC_US0) PDC Transfer Control Register
-AT91C_US0_PTSR            EQU (0xFFFC0124) ;- (PDC_US0) PDC Transfer Status Register
-AT91C_US0_TNCR            EQU (0xFFFC011C) ;- (PDC_US0) Transmit Next Counter Register
-AT91C_US0_TPR             EQU (0xFFFC0108) ;- (PDC_US0) Transmit Pointer Register
-AT91C_US0_RCR             EQU (0xFFFC0104) ;- (PDC_US0) Receive Counter Register
-AT91C_US0_RPR             EQU (0xFFFC0100) ;- (PDC_US0) Receive Pointer Register
-AT91C_US0_RNCR            EQU (0xFFFC0114) ;- (PDC_US0) Receive Next Counter Register
-// - ========== Register definition for US0 peripheral ========== 
-AT91C_US0_BRGR            EQU (0xFFFC0020) ;- (US0) Baud Rate Generator Register
-AT91C_US0_NER             EQU (0xFFFC0044) ;- (US0) Nb Errors Register
-AT91C_US0_CR              EQU (0xFFFC0000) ;- (US0) Control Register
-AT91C_US0_IMR             EQU (0xFFFC0010) ;- (US0) Interrupt Mask Register
-AT91C_US0_FIDI            EQU (0xFFFC0040) ;- (US0) FI_DI_Ratio Register
-AT91C_US0_TTGR            EQU (0xFFFC0028) ;- (US0) Transmitter Time-guard Register
-AT91C_US0_MR              EQU (0xFFFC0004) ;- (US0) Mode Register
-AT91C_US0_RTOR            EQU (0xFFFC0024) ;- (US0) Receiver Time-out Register
-AT91C_US0_CSR             EQU (0xFFFC0014) ;- (US0) Channel Status Register
-AT91C_US0_RHR             EQU (0xFFFC0018) ;- (US0) Receiver Holding Register
-AT91C_US0_IDR             EQU (0xFFFC000C) ;- (US0) Interrupt Disable Register
-AT91C_US0_THR             EQU (0xFFFC001C) ;- (US0) Transmitter Holding Register
-AT91C_US0_IF              EQU (0xFFFC004C) ;- (US0) IRDA_FILTER Register
-AT91C_US0_IER             EQU (0xFFFC0008) ;- (US0) Interrupt Enable Register
-// - ========== Register definition for PDC_SSC peripheral ========== 
-AT91C_SSC_TNCR            EQU (0xFFFD411C) ;- (PDC_SSC) Transmit Next Counter Register
-AT91C_SSC_RPR             EQU (0xFFFD4100) ;- (PDC_SSC) Receive Pointer Register
-AT91C_SSC_RNCR            EQU (0xFFFD4114) ;- (PDC_SSC) Receive Next Counter Register
-AT91C_SSC_TPR             EQU (0xFFFD4108) ;- (PDC_SSC) Transmit Pointer Register
-AT91C_SSC_PTCR            EQU (0xFFFD4120) ;- (PDC_SSC) PDC Transfer Control Register
-AT91C_SSC_TCR             EQU (0xFFFD410C) ;- (PDC_SSC) Transmit Counter Register
-AT91C_SSC_RCR             EQU (0xFFFD4104) ;- (PDC_SSC) Receive Counter Register
-AT91C_SSC_RNPR            EQU (0xFFFD4110) ;- (PDC_SSC) Receive Next Pointer Register
-AT91C_SSC_TNPR            EQU (0xFFFD4118) ;- (PDC_SSC) Transmit Next Pointer Register
-AT91C_SSC_PTSR            EQU (0xFFFD4124) ;- (PDC_SSC) PDC Transfer Status Register
-// - ========== Register definition for SSC peripheral ========== 
-AT91C_SSC_RHR             EQU (0xFFFD4020) ;- (SSC) Receive Holding Register
-AT91C_SSC_RSHR            EQU (0xFFFD4030) ;- (SSC) Receive Sync Holding Register
-AT91C_SSC_TFMR            EQU (0xFFFD401C) ;- (SSC) Transmit Frame Mode Register
-AT91C_SSC_IDR             EQU (0xFFFD4048) ;- (SSC) Interrupt Disable Register
-AT91C_SSC_THR             EQU (0xFFFD4024) ;- (SSC) Transmit Holding Register
-AT91C_SSC_RCMR            EQU (0xFFFD4010) ;- (SSC) Receive Clock ModeRegister
-AT91C_SSC_IER             EQU (0xFFFD4044) ;- (SSC) Interrupt Enable Register
-AT91C_SSC_TSHR            EQU (0xFFFD4034) ;- (SSC) Transmit Sync Holding Register
-AT91C_SSC_SR              EQU (0xFFFD4040) ;- (SSC) Status Register
-AT91C_SSC_CMR             EQU (0xFFFD4004) ;- (SSC) Clock Mode Register
-AT91C_SSC_TCMR            EQU (0xFFFD4018) ;- (SSC) Transmit Clock Mode Register
-AT91C_SSC_CR              EQU (0xFFFD4000) ;- (SSC) Control Register
-AT91C_SSC_IMR             EQU (0xFFFD404C) ;- (SSC) Interrupt Mask Register
-AT91C_SSC_RFMR            EQU (0xFFFD4014) ;- (SSC) Receive Frame Mode Register
-// - ========== Register definition for TWI peripheral ========== 
-AT91C_TWI_IER             EQU (0xFFFB8024) ;- (TWI) Interrupt Enable Register
-AT91C_TWI_CR              EQU (0xFFFB8000) ;- (TWI) Control Register
-AT91C_TWI_SR              EQU (0xFFFB8020) ;- (TWI) Status Register
-AT91C_TWI_IMR             EQU (0xFFFB802C) ;- (TWI) Interrupt Mask Register
-AT91C_TWI_THR             EQU (0xFFFB8034) ;- (TWI) Transmit Holding Register
-AT91C_TWI_IDR             EQU (0xFFFB8028) ;- (TWI) Interrupt Disable Register
-AT91C_TWI_IADR            EQU (0xFFFB800C) ;- (TWI) Internal Address Register
-AT91C_TWI_MMR             EQU (0xFFFB8004) ;- (TWI) Master Mode Register
-AT91C_TWI_CWGR            EQU (0xFFFB8010) ;- (TWI) Clock Waveform Generator Register
-AT91C_TWI_RHR             EQU (0xFFFB8030) ;- (TWI) Receive Holding Register
-// - ========== Register definition for PWMC_CH3 peripheral ========== 
-AT91C_PWMC_CH3_CUPDR      EQU (0xFFFCC270) ;- (PWMC_CH3) Channel Update Register
-AT91C_PWMC_CH3_Reserved   EQU (0xFFFCC274) ;- (PWMC_CH3) Reserved
-AT91C_PWMC_CH3_CPRDR      EQU (0xFFFCC268) ;- (PWMC_CH3) Channel Period Register
-AT91C_PWMC_CH3_CDTYR      EQU (0xFFFCC264) ;- (PWMC_CH3) Channel Duty Cycle Register
-AT91C_PWMC_CH3_CCNTR      EQU (0xFFFCC26C) ;- (PWMC_CH3) Channel Counter Register
-AT91C_PWMC_CH3_CMR        EQU (0xFFFCC260) ;- (PWMC_CH3) Channel Mode Register
-// - ========== Register definition for PWMC_CH2 peripheral ========== 
-AT91C_PWMC_CH2_Reserved   EQU (0xFFFCC254) ;- (PWMC_CH2) Reserved
-AT91C_PWMC_CH2_CMR        EQU (0xFFFCC240) ;- (PWMC_CH2) Channel Mode Register
-AT91C_PWMC_CH2_CCNTR      EQU (0xFFFCC24C) ;- (PWMC_CH2) Channel Counter Register
-AT91C_PWMC_CH2_CPRDR      EQU (0xFFFCC248) ;- (PWMC_CH2) Channel Period Register
-AT91C_PWMC_CH2_CUPDR      EQU (0xFFFCC250) ;- (PWMC_CH2) Channel Update Register
-AT91C_PWMC_CH2_CDTYR      EQU (0xFFFCC244) ;- (PWMC_CH2) Channel Duty Cycle Register
-// - ========== Register definition for PWMC_CH1 peripheral ========== 
-AT91C_PWMC_CH1_Reserved   EQU (0xFFFCC234) ;- (PWMC_CH1) Reserved
-AT91C_PWMC_CH1_CUPDR      EQU (0xFFFCC230) ;- (PWMC_CH1) Channel Update Register
-AT91C_PWMC_CH1_CPRDR      EQU (0xFFFCC228) ;- (PWMC_CH1) Channel Period Register
-AT91C_PWMC_CH1_CCNTR      EQU (0xFFFCC22C) ;- (PWMC_CH1) Channel Counter Register
-AT91C_PWMC_CH1_CDTYR      EQU (0xFFFCC224) ;- (PWMC_CH1) Channel Duty Cycle Register
-AT91C_PWMC_CH1_CMR        EQU (0xFFFCC220) ;- (PWMC_CH1) Channel Mode Register
-// - ========== Register definition for PWMC_CH0 peripheral ========== 
-AT91C_PWMC_CH0_Reserved   EQU (0xFFFCC214) ;- (PWMC_CH0) Reserved
-AT91C_PWMC_CH0_CPRDR      EQU (0xFFFCC208) ;- (PWMC_CH0) Channel Period Register
-AT91C_PWMC_CH0_CDTYR      EQU (0xFFFCC204) ;- (PWMC_CH0) Channel Duty Cycle Register
-AT91C_PWMC_CH0_CMR        EQU (0xFFFCC200) ;- (PWMC_CH0) Channel Mode Register
-AT91C_PWMC_CH0_CUPDR      EQU (0xFFFCC210) ;- (PWMC_CH0) Channel Update Register
-AT91C_PWMC_CH0_CCNTR      EQU (0xFFFCC20C) ;- (PWMC_CH0) Channel Counter Register
-// - ========== Register definition for PWMC peripheral ========== 
-AT91C_PWMC_IDR            EQU (0xFFFCC014) ;- (PWMC) PWMC Interrupt Disable Register
-AT91C_PWMC_DIS            EQU (0xFFFCC008) ;- (PWMC) PWMC Disable Register
-AT91C_PWMC_IER            EQU (0xFFFCC010) ;- (PWMC) PWMC Interrupt Enable Register
-AT91C_PWMC_VR             EQU (0xFFFCC0FC) ;- (PWMC) PWMC Version Register
-AT91C_PWMC_ISR            EQU (0xFFFCC01C) ;- (PWMC) PWMC Interrupt Status Register
-AT91C_PWMC_SR             EQU (0xFFFCC00C) ;- (PWMC) PWMC Status Register
-AT91C_PWMC_IMR            EQU (0xFFFCC018) ;- (PWMC) PWMC Interrupt Mask Register
-AT91C_PWMC_MR             EQU (0xFFFCC000) ;- (PWMC) PWMC Mode Register
-AT91C_PWMC_ENA            EQU (0xFFFCC004) ;- (PWMC) PWMC Enable Register
-// - ========== Register definition for UDP peripheral ========== 
-AT91C_UDP_IMR             EQU (0xFFFB0018) ;- (UDP) Interrupt Mask Register
-AT91C_UDP_FADDR           EQU (0xFFFB0008) ;- (UDP) Function Address Register
-AT91C_UDP_NUM             EQU (0xFFFB0000) ;- (UDP) Frame Number Register
-AT91C_UDP_FDR             EQU (0xFFFB0050) ;- (UDP) Endpoint FIFO Data Register
-AT91C_UDP_ISR             EQU (0xFFFB001C) ;- (UDP) Interrupt Status Register
-AT91C_UDP_CSR             EQU (0xFFFB0030) ;- (UDP) Endpoint Control and Status Register
-AT91C_UDP_IDR             EQU (0xFFFB0014) ;- (UDP) Interrupt Disable Register
-AT91C_UDP_ICR             EQU (0xFFFB0020) ;- (UDP) Interrupt Clear Register
-AT91C_UDP_RSTEP           EQU (0xFFFB0028) ;- (UDP) Reset Endpoint Register
-AT91C_UDP_TXVC            EQU (0xFFFB0074) ;- (UDP) Transceiver Control Register
-AT91C_UDP_GLBSTATE        EQU (0xFFFB0004) ;- (UDP) Global State Register
-AT91C_UDP_IER             EQU (0xFFFB0010) ;- (UDP) Interrupt Enable Register
-// - ========== Register definition for TC0 peripheral ========== 
-AT91C_TC0_SR              EQU (0xFFFA0020) ;- (TC0) Status Register
-AT91C_TC0_RC              EQU (0xFFFA001C) ;- (TC0) Register C
-AT91C_TC0_RB              EQU (0xFFFA0018) ;- (TC0) Register B
-AT91C_TC0_CCR             EQU (0xFFFA0000) ;- (TC0) Channel Control Register
-AT91C_TC0_CMR             EQU (0xFFFA0004) ;- (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
-AT91C_TC0_IER             EQU (0xFFFA0024) ;- (TC0) Interrupt Enable Register
-AT91C_TC0_RA              EQU (0xFFFA0014) ;- (TC0) Register A
-AT91C_TC0_IDR             EQU (0xFFFA0028) ;- (TC0) Interrupt Disable Register
-AT91C_TC0_CV              EQU (0xFFFA0010) ;- (TC0) Counter Value
-AT91C_TC0_IMR             EQU (0xFFFA002C) ;- (TC0) Interrupt Mask Register
-// - ========== Register definition for TC1 peripheral ========== 
-AT91C_TC1_RB              EQU (0xFFFA0058) ;- (TC1) Register B
-AT91C_TC1_CCR             EQU (0xFFFA0040) ;- (TC1) Channel Control Register
-AT91C_TC1_IER             EQU (0xFFFA0064) ;- (TC1) Interrupt Enable Register
-AT91C_TC1_IDR             EQU (0xFFFA0068) ;- (TC1) Interrupt Disable Register
-AT91C_TC1_SR              EQU (0xFFFA0060) ;- (TC1) Status Register
-AT91C_TC1_CMR             EQU (0xFFFA0044) ;- (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
-AT91C_TC1_RA              EQU (0xFFFA0054) ;- (TC1) Register A
-AT91C_TC1_RC              EQU (0xFFFA005C) ;- (TC1) Register C
-AT91C_TC1_IMR             EQU (0xFFFA006C) ;- (TC1) Interrupt Mask Register
-AT91C_TC1_CV              EQU (0xFFFA0050) ;- (TC1) Counter Value
-// - ========== Register definition for TC2 peripheral ========== 
-AT91C_TC2_CMR             EQU (0xFFFA0084) ;- (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
-AT91C_TC2_CCR             EQU (0xFFFA0080) ;- (TC2) Channel Control Register
-AT91C_TC2_CV              EQU (0xFFFA0090) ;- (TC2) Counter Value
-AT91C_TC2_RA              EQU (0xFFFA0094) ;- (TC2) Register A
-AT91C_TC2_RB              EQU (0xFFFA0098) ;- (TC2) Register B
-AT91C_TC2_IDR             EQU (0xFFFA00A8) ;- (TC2) Interrupt Disable Register
-AT91C_TC2_IMR             EQU (0xFFFA00AC) ;- (TC2) Interrupt Mask Register
-AT91C_TC2_RC              EQU (0xFFFA009C) ;- (TC2) Register C
-AT91C_TC2_IER             EQU (0xFFFA00A4) ;- (TC2) Interrupt Enable Register
-AT91C_TC2_SR              EQU (0xFFFA00A0) ;- (TC2) Status Register
-// - ========== Register definition for TCB peripheral ========== 
-AT91C_TCB_BMR             EQU (0xFFFA00C4) ;- (TCB) TC Block Mode Register
-AT91C_TCB_BCR             EQU (0xFFFA00C0) ;- (TCB) TC Block Control Register
-// - ========== Register definition for CAN_MB0 peripheral ========== 
-AT91C_CAN_MB0_MDL         EQU (0xFFFD0214) ;- (CAN_MB0) MailBox Data Low Register
-AT91C_CAN_MB0_MAM         EQU (0xFFFD0204) ;- (CAN_MB0) MailBox Acceptance Mask Register
-AT91C_CAN_MB0_MCR         EQU (0xFFFD021C) ;- (CAN_MB0) MailBox Control Register
-AT91C_CAN_MB0_MID         EQU (0xFFFD0208) ;- (CAN_MB0) MailBox ID Register
-AT91C_CAN_MB0_MSR         EQU (0xFFFD0210) ;- (CAN_MB0) MailBox Status Register
-AT91C_CAN_MB0_MFID        EQU (0xFFFD020C) ;- (CAN_MB0) MailBox Family ID Register
-AT91C_CAN_MB0_MDH         EQU (0xFFFD0218) ;- (CAN_MB0) MailBox Data High Register
-AT91C_CAN_MB0_MMR         EQU (0xFFFD0200) ;- (CAN_MB0) MailBox Mode Register
-// - ========== Register definition for CAN_MB1 peripheral ========== 
-AT91C_CAN_MB1_MDL         EQU (0xFFFD0234) ;- (CAN_MB1) MailBox Data Low Register
-AT91C_CAN_MB1_MID         EQU (0xFFFD0228) ;- (CAN_MB1) MailBox ID Register
-AT91C_CAN_MB1_MMR         EQU (0xFFFD0220) ;- (CAN_MB1) MailBox Mode Register
-AT91C_CAN_MB1_MSR         EQU (0xFFFD0230) ;- (CAN_MB1) MailBox Status Register
-AT91C_CAN_MB1_MAM         EQU (0xFFFD0224) ;- (CAN_MB1) MailBox Acceptance Mask Register
-AT91C_CAN_MB1_MDH         EQU (0xFFFD0238) ;- (CAN_MB1) MailBox Data High Register
-AT91C_CAN_MB1_MCR         EQU (0xFFFD023C) ;- (CAN_MB1) MailBox Control Register
-AT91C_CAN_MB1_MFID        EQU (0xFFFD022C) ;- (CAN_MB1) MailBox Family ID Register
-// - ========== Register definition for CAN_MB2 peripheral ========== 
-AT91C_CAN_MB2_MCR         EQU (0xFFFD025C) ;- (CAN_MB2) MailBox Control Register
-AT91C_CAN_MB2_MDH         EQU (0xFFFD0258) ;- (CAN_MB2) MailBox Data High Register
-AT91C_CAN_MB2_MID         EQU (0xFFFD0248) ;- (CAN_MB2) MailBox ID Register
-AT91C_CAN_MB2_MDL         EQU (0xFFFD0254) ;- (CAN_MB2) MailBox Data Low Register
-AT91C_CAN_MB2_MMR         EQU (0xFFFD0240) ;- (CAN_MB2) MailBox Mode Register
-AT91C_CAN_MB2_MAM         EQU (0xFFFD0244) ;- (CAN_MB2) MailBox Acceptance Mask Register
-AT91C_CAN_MB2_MFID        EQU (0xFFFD024C) ;- (CAN_MB2) MailBox Family ID Register
-AT91C_CAN_MB2_MSR         EQU (0xFFFD0250) ;- (CAN_MB2) MailBox Status Register
-// - ========== Register definition for CAN_MB3 peripheral ========== 
-AT91C_CAN_MB3_MFID        EQU (0xFFFD026C) ;- (CAN_MB3) MailBox Family ID Register
-AT91C_CAN_MB3_MAM         EQU (0xFFFD0264) ;- (CAN_MB3) MailBox Acceptance Mask Register
-AT91C_CAN_MB3_MID         EQU (0xFFFD0268) ;- (CAN_MB3) MailBox ID Register
-AT91C_CAN_MB3_MCR         EQU (0xFFFD027C) ;- (CAN_MB3) MailBox Control Register
-AT91C_CAN_MB3_MMR         EQU (0xFFFD0260) ;- (CAN_MB3) MailBox Mode Register
-AT91C_CAN_MB3_MSR         EQU (0xFFFD0270) ;- (CAN_MB3) MailBox Status Register
-AT91C_CAN_MB3_MDL         EQU (0xFFFD0274) ;- (CAN_MB3) MailBox Data Low Register
-AT91C_CAN_MB3_MDH         EQU (0xFFFD0278) ;- (CAN_MB3) MailBox Data High Register
-// - ========== Register definition for CAN_MB4 peripheral ========== 
-AT91C_CAN_MB4_MID         EQU (0xFFFD0288) ;- (CAN_MB4) MailBox ID Register
-AT91C_CAN_MB4_MMR         EQU (0xFFFD0280) ;- (CAN_MB4) MailBox Mode Register
-AT91C_CAN_MB4_MDH         EQU (0xFFFD0298) ;- (CAN_MB4) MailBox Data High Register
-AT91C_CAN_MB4_MFID        EQU (0xFFFD028C) ;- (CAN_MB4) MailBox Family ID Register
-AT91C_CAN_MB4_MSR         EQU (0xFFFD0290) ;- (CAN_MB4) MailBox Status Register
-AT91C_CAN_MB4_MCR         EQU (0xFFFD029C) ;- (CAN_MB4) MailBox Control Register
-AT91C_CAN_MB4_MDL         EQU (0xFFFD0294) ;- (CAN_MB4) MailBox Data Low Register
-AT91C_CAN_MB4_MAM         EQU (0xFFFD0284) ;- (CAN_MB4) MailBox Acceptance Mask Register
-// - ========== Register definition for CAN_MB5 peripheral ========== 
-AT91C_CAN_MB5_MSR         EQU (0xFFFD02B0) ;- (CAN_MB5) MailBox Status Register
-AT91C_CAN_MB5_MCR         EQU (0xFFFD02BC) ;- (CAN_MB5) MailBox Control Register
-AT91C_CAN_MB5_MFID        EQU (0xFFFD02AC) ;- (CAN_MB5) MailBox Family ID Register
-AT91C_CAN_MB5_MDH         EQU (0xFFFD02B8) ;- (CAN_MB5) MailBox Data High Register
-AT91C_CAN_MB5_MID         EQU (0xFFFD02A8) ;- (CAN_MB5) MailBox ID Register
-AT91C_CAN_MB5_MMR         EQU (0xFFFD02A0) ;- (CAN_MB5) MailBox Mode Register
-AT91C_CAN_MB5_MDL         EQU (0xFFFD02B4) ;- (CAN_MB5) MailBox Data Low Register
-AT91C_CAN_MB5_MAM         EQU (0xFFFD02A4) ;- (CAN_MB5) MailBox Acceptance Mask Register
-// - ========== Register definition for CAN_MB6 peripheral ========== 
-AT91C_CAN_MB6_MFID        EQU (0xFFFD02CC) ;- (CAN_MB6) MailBox Family ID Register
-AT91C_CAN_MB6_MID         EQU (0xFFFD02C8) ;- (CAN_MB6) MailBox ID Register
-AT91C_CAN_MB6_MAM         EQU (0xFFFD02C4) ;- (CAN_MB6) MailBox Acceptance Mask Register
-AT91C_CAN_MB6_MSR         EQU (0xFFFD02D0) ;- (CAN_MB6) MailBox Status Register
-AT91C_CAN_MB6_MDL         EQU (0xFFFD02D4) ;- (CAN_MB6) MailBox Data Low Register
-AT91C_CAN_MB6_MCR         EQU (0xFFFD02DC) ;- (CAN_MB6) MailBox Control Register
-AT91C_CAN_MB6_MDH         EQU (0xFFFD02D8) ;- (CAN_MB6) MailBox Data High Register
-AT91C_CAN_MB6_MMR         EQU (0xFFFD02C0) ;- (CAN_MB6) MailBox Mode Register
-// - ========== Register definition for CAN_MB7 peripheral ========== 
-AT91C_CAN_MB7_MCR         EQU (0xFFFD02FC) ;- (CAN_MB7) MailBox Control Register
-AT91C_CAN_MB7_MDH         EQU (0xFFFD02F8) ;- (CAN_MB7) MailBox Data High Register
-AT91C_CAN_MB7_MFID        EQU (0xFFFD02EC) ;- (CAN_MB7) MailBox Family ID Register
-AT91C_CAN_MB7_MDL         EQU (0xFFFD02F4) ;- (CAN_MB7) MailBox Data Low Register
-AT91C_CAN_MB7_MID         EQU (0xFFFD02E8) ;- (CAN_MB7) MailBox ID Register
-AT91C_CAN_MB7_MMR         EQU (0xFFFD02E0) ;- (CAN_MB7) MailBox Mode Register
-AT91C_CAN_MB7_MAM         EQU (0xFFFD02E4) ;- (CAN_MB7) MailBox Acceptance Mask Register
-AT91C_CAN_MB7_MSR         EQU (0xFFFD02F0) ;- (CAN_MB7) MailBox Status Register
-// - ========== Register definition for CAN peripheral ========== 
-AT91C_CAN_TCR             EQU (0xFFFD0024) ;- (CAN) Transfer Command Register
-AT91C_CAN_IMR             EQU (0xFFFD000C) ;- (CAN) Interrupt Mask Register
-AT91C_CAN_IER             EQU (0xFFFD0004) ;- (CAN) Interrupt Enable Register
-AT91C_CAN_ECR             EQU (0xFFFD0020) ;- (CAN) Error Counter Register
-AT91C_CAN_TIMESTP         EQU (0xFFFD001C) ;- (CAN) Time Stamp Register
-AT91C_CAN_MR              EQU (0xFFFD0000) ;- (CAN) Mode Register
-AT91C_CAN_IDR             EQU (0xFFFD0008) ;- (CAN) Interrupt Disable Register
-AT91C_CAN_ACR             EQU (0xFFFD0028) ;- (CAN) Abort Command Register
-AT91C_CAN_TIM             EQU (0xFFFD0018) ;- (CAN) Timer Register
-AT91C_CAN_SR              EQU (0xFFFD0010) ;- (CAN) Status Register
-AT91C_CAN_BR              EQU (0xFFFD0014) ;- (CAN) Baudrate Register
-AT91C_CAN_VR              EQU (0xFFFD00FC) ;- (CAN) Version Register
-// - ========== Register definition for EMAC peripheral ========== 
-AT91C_EMAC_ISR            EQU (0xFFFDC024) ;- (EMAC) Interrupt Status Register
-AT91C_EMAC_SA4H           EQU (0xFFFDC0B4) ;- (EMAC) Specific Address 4 Top, Last 2 bytes
-AT91C_EMAC_SA1L           EQU (0xFFFDC098) ;- (EMAC) Specific Address 1 Bottom, First 4 bytes
-AT91C_EMAC_ELE            EQU (0xFFFDC078) ;- (EMAC) Excessive Length Errors Register
-AT91C_EMAC_LCOL           EQU (0xFFFDC05C) ;- (EMAC) Late Collision Register
-AT91C_EMAC_RLE            EQU (0xFFFDC088) ;- (EMAC) Receive Length Field Mismatch Register
-AT91C_EMAC_WOL            EQU (0xFFFDC0C4) ;- (EMAC) Wake On LAN Register
-AT91C_EMAC_DTF            EQU (0xFFFDC058) ;- (EMAC) Deferred Transmission Frame Register
-AT91C_EMAC_TUND           EQU (0xFFFDC064) ;- (EMAC) Transmit Underrun Error Register
-AT91C_EMAC_NCR            EQU (0xFFFDC000) ;- (EMAC) Network Control Register
-AT91C_EMAC_SA4L           EQU (0xFFFDC0B0) ;- (EMAC) Specific Address 4 Bottom, First 4 bytes
-AT91C_EMAC_RSR            EQU (0xFFFDC020) ;- (EMAC) Receive Status Register
-AT91C_EMAC_SA3L           EQU (0xFFFDC0A8) ;- (EMAC) Specific Address 3 Bottom, First 4 bytes
-AT91C_EMAC_TSR            EQU (0xFFFDC014) ;- (EMAC) Transmit Status Register
-AT91C_EMAC_IDR            EQU (0xFFFDC02C) ;- (EMAC) Interrupt Disable Register
-AT91C_EMAC_RSE            EQU (0xFFFDC074) ;- (EMAC) Receive Symbol Errors Register
-AT91C_EMAC_ECOL           EQU (0xFFFDC060) ;- (EMAC) Excessive Collision Register
-AT91C_EMAC_TID            EQU (0xFFFDC0B8) ;- (EMAC) Type ID Checking Register
-AT91C_EMAC_HRB            EQU (0xFFFDC090) ;- (EMAC) Hash Address Bottom[31:0]
-AT91C_EMAC_TBQP           EQU (0xFFFDC01C) ;- (EMAC) Transmit Buffer Queue Pointer
-AT91C_EMAC_USRIO          EQU (0xFFFDC0C0) ;- (EMAC) USER Input/Output Register
-AT91C_EMAC_PTR            EQU (0xFFFDC038) ;- (EMAC) Pause Time Register
-AT91C_EMAC_SA2H           EQU (0xFFFDC0A4) ;- (EMAC) Specific Address 2 Top, Last 2 bytes
-AT91C_EMAC_ROV            EQU (0xFFFDC070) ;- (EMAC) Receive Overrun Errors Register
-AT91C_EMAC_ALE            EQU (0xFFFDC054) ;- (EMAC) Alignment Error Register
-AT91C_EMAC_RJA            EQU (0xFFFDC07C) ;- (EMAC) Receive Jabbers Register
-AT91C_EMAC_RBQP           EQU (0xFFFDC018) ;- (EMAC) Receive Buffer Queue Pointer
-AT91C_EMAC_TPF            EQU (0xFFFDC08C) ;- (EMAC) Transmitted Pause Frames Register
-AT91C_EMAC_NCFGR          EQU (0xFFFDC004) ;- (EMAC) Network Configuration Register
-AT91C_EMAC_HRT            EQU (0xFFFDC094) ;- (EMAC) Hash Address Top[63:32]
-AT91C_EMAC_USF            EQU (0xFFFDC080) ;- (EMAC) Undersize Frames Register
-AT91C_EMAC_FCSE           EQU (0xFFFDC050) ;- (EMAC) Frame Check Sequence Error Register
-AT91C_EMAC_TPQ            EQU (0xFFFDC0BC) ;- (EMAC) Transmit Pause Quantum Register
-AT91C_EMAC_MAN            EQU (0xFFFDC034) ;- (EMAC) PHY Maintenance Register
-AT91C_EMAC_FTO            EQU (0xFFFDC040) ;- (EMAC) Frames Transmitted OK Register
-AT91C_EMAC_REV            EQU (0xFFFDC0FC) ;- (EMAC) Revision Register
-AT91C_EMAC_IMR            EQU (0xFFFDC030) ;- (EMAC) Interrupt Mask Register
-AT91C_EMAC_SCF            EQU (0xFFFDC044) ;- (EMAC) Single Collision Frame Register
-AT91C_EMAC_PFR            EQU (0xFFFDC03C) ;- (EMAC) Pause Frames received Register
-AT91C_EMAC_MCF            EQU (0xFFFDC048) ;- (EMAC) Multiple Collision Frame Register
-AT91C_EMAC_NSR            EQU (0xFFFDC008) ;- (EMAC) Network Status Register
-AT91C_EMAC_SA2L           EQU (0xFFFDC0A0) ;- (EMAC) Specific Address 2 Bottom, First 4 bytes
-AT91C_EMAC_FRO            EQU (0xFFFDC04C) ;- (EMAC) Frames Received OK Register
-AT91C_EMAC_IER            EQU (0xFFFDC028) ;- (EMAC) Interrupt Enable Register
-AT91C_EMAC_SA1H           EQU (0xFFFDC09C) ;- (EMAC) Specific Address 1 Top, Last 2 bytes
-AT91C_EMAC_CSE            EQU (0xFFFDC068) ;- (EMAC) Carrier Sense Error Register
-AT91C_EMAC_SA3H           EQU (0xFFFDC0AC) ;- (EMAC) Specific Address 3 Top, Last 2 bytes
-AT91C_EMAC_RRE            EQU (0xFFFDC06C) ;- (EMAC) Receive Ressource Error Register
-AT91C_EMAC_STE            EQU (0xFFFDC084) ;- (EMAC) SQE Test Error Register
-// - ========== Register definition for PDC_ADC peripheral ========== 
-AT91C_ADC_PTSR            EQU (0xFFFD8124) ;- (PDC_ADC) PDC Transfer Status Register
-AT91C_ADC_PTCR            EQU (0xFFFD8120) ;- (PDC_ADC) PDC Transfer Control Register
-AT91C_ADC_TNPR            EQU (0xFFFD8118) ;- (PDC_ADC) Transmit Next Pointer Register
-AT91C_ADC_TNCR            EQU (0xFFFD811C) ;- (PDC_ADC) Transmit Next Counter Register
-AT91C_ADC_RNPR            EQU (0xFFFD8110) ;- (PDC_ADC) Receive Next Pointer Register
-AT91C_ADC_RNCR            EQU (0xFFFD8114) ;- (PDC_ADC) Receive Next Counter Register
-AT91C_ADC_RPR             EQU (0xFFFD8100) ;- (PDC_ADC) Receive Pointer Register
-AT91C_ADC_TCR             EQU (0xFFFD810C) ;- (PDC_ADC) Transmit Counter Register
-AT91C_ADC_TPR             EQU (0xFFFD8108) ;- (PDC_ADC) Transmit Pointer Register
-AT91C_ADC_RCR             EQU (0xFFFD8104) ;- (PDC_ADC) Receive Counter Register
-// - ========== Register definition for ADC peripheral ========== 
-AT91C_ADC_CDR2            EQU (0xFFFD8038) ;- (ADC) ADC Channel Data Register 2
-AT91C_ADC_CDR3            EQU (0xFFFD803C) ;- (ADC) ADC Channel Data Register 3
-AT91C_ADC_CDR0            EQU (0xFFFD8030) ;- (ADC) ADC Channel Data Register 0
-AT91C_ADC_CDR5            EQU (0xFFFD8044) ;- (ADC) ADC Channel Data Register 5
-AT91C_ADC_CHDR            EQU (0xFFFD8014) ;- (ADC) ADC Channel Disable Register
-AT91C_ADC_SR              EQU (0xFFFD801C) ;- (ADC) ADC Status Register
-AT91C_ADC_CDR4            EQU (0xFFFD8040) ;- (ADC) ADC Channel Data Register 4
-AT91C_ADC_CDR1            EQU (0xFFFD8034) ;- (ADC) ADC Channel Data Register 1
-AT91C_ADC_LCDR            EQU (0xFFFD8020) ;- (ADC) ADC Last Converted Data Register
-AT91C_ADC_IDR             EQU (0xFFFD8028) ;- (ADC) ADC Interrupt Disable Register
-AT91C_ADC_CR              EQU (0xFFFD8000) ;- (ADC) ADC Control Register
-AT91C_ADC_CDR7            EQU (0xFFFD804C) ;- (ADC) ADC Channel Data Register 7
-AT91C_ADC_CDR6            EQU (0xFFFD8048) ;- (ADC) ADC Channel Data Register 6
-AT91C_ADC_IER             EQU (0xFFFD8024) ;- (ADC) ADC Interrupt Enable Register
-AT91C_ADC_CHER            EQU (0xFFFD8010) ;- (ADC) ADC Channel Enable Register
-AT91C_ADC_CHSR            EQU (0xFFFD8018) ;- (ADC) ADC Channel Status Register
-AT91C_ADC_MR              EQU (0xFFFD8004) ;- (ADC) ADC Mode Register
-AT91C_ADC_IMR             EQU (0xFFFD802C) ;- (ADC) ADC Interrupt Mask Register
-// - ========== Register definition for PDC_AES peripheral ========== 
-AT91C_AES_TPR             EQU (0xFFFA4108) ;- (PDC_AES) Transmit Pointer Register
-AT91C_AES_PTCR            EQU (0xFFFA4120) ;- (PDC_AES) PDC Transfer Control Register
-AT91C_AES_RNPR            EQU (0xFFFA4110) ;- (PDC_AES) Receive Next Pointer Register
-AT91C_AES_TNCR            EQU (0xFFFA411C) ;- (PDC_AES) Transmit Next Counter Register
-AT91C_AES_TCR             EQU (0xFFFA410C) ;- (PDC_AES) Transmit Counter Register
-AT91C_AES_RCR             EQU (0xFFFA4104) ;- (PDC_AES) Receive Counter Register
-AT91C_AES_RNCR            EQU (0xFFFA4114) ;- (PDC_AES) Receive Next Counter Register
-AT91C_AES_TNPR            EQU (0xFFFA4118) ;- (PDC_AES) Transmit Next Pointer Register
-AT91C_AES_RPR             EQU (0xFFFA4100) ;- (PDC_AES) Receive Pointer Register
-AT91C_AES_PTSR            EQU (0xFFFA4124) ;- (PDC_AES) PDC Transfer Status Register
-// - ========== Register definition for AES peripheral ========== 
-AT91C_AES_IVxR            EQU (0xFFFA4060) ;- (AES) Initialization Vector x Register
-AT91C_AES_MR              EQU (0xFFFA4004) ;- (AES) Mode Register
-AT91C_AES_VR              EQU (0xFFFA40FC) ;- (AES) AES Version Register
-AT91C_AES_ODATAxR         EQU (0xFFFA4050) ;- (AES) Output Data x Register
-AT91C_AES_IDATAxR         EQU (0xFFFA4040) ;- (AES) Input Data x Register
-AT91C_AES_CR              EQU (0xFFFA4000) ;- (AES) Control Register
-AT91C_AES_IDR             EQU (0xFFFA4014) ;- (AES) Interrupt Disable Register
-AT91C_AES_IMR             EQU (0xFFFA4018) ;- (AES) Interrupt Mask Register
-AT91C_AES_IER             EQU (0xFFFA4010) ;- (AES) Interrupt Enable Register
-AT91C_AES_KEYWxR          EQU (0xFFFA4020) ;- (AES) Key Word x Register
-AT91C_AES_ISR             EQU (0xFFFA401C) ;- (AES) Interrupt Status Register
-// - ========== Register definition for PDC_TDES peripheral ========== 
-AT91C_TDES_RNCR           EQU (0xFFFA8114) ;- (PDC_TDES) Receive Next Counter Register
-AT91C_TDES_TCR            EQU (0xFFFA810C) ;- (PDC_TDES) Transmit Counter Register
-AT91C_TDES_RCR            EQU (0xFFFA8104) ;- (PDC_TDES) Receive Counter Register
-AT91C_TDES_TNPR           EQU (0xFFFA8118) ;- (PDC_TDES) Transmit Next Pointer Register
-AT91C_TDES_RNPR           EQU (0xFFFA8110) ;- (PDC_TDES) Receive Next Pointer Register
-AT91C_TDES_RPR            EQU (0xFFFA8100) ;- (PDC_TDES) Receive Pointer Register
-AT91C_TDES_TNCR           EQU (0xFFFA811C) ;- (PDC_TDES) Transmit Next Counter Register
-AT91C_TDES_TPR            EQU (0xFFFA8108) ;- (PDC_TDES) Transmit Pointer Register
-AT91C_TDES_PTSR           EQU (0xFFFA8124) ;- (PDC_TDES) PDC Transfer Status Register
-AT91C_TDES_PTCR           EQU (0xFFFA8120) ;- (PDC_TDES) PDC Transfer Control Register
-// - ========== Register definition for TDES peripheral ========== 
-AT91C_TDES_KEY2WxR        EQU (0xFFFA8028) ;- (TDES) Key 2 Word x Register
-AT91C_TDES_KEY3WxR        EQU (0xFFFA8030) ;- (TDES) Key 3 Word x Register
-AT91C_TDES_IDR            EQU (0xFFFA8014) ;- (TDES) Interrupt Disable Register
-AT91C_TDES_VR             EQU (0xFFFA80FC) ;- (TDES) TDES Version Register
-AT91C_TDES_IVxR           EQU (0xFFFA8060) ;- (TDES) Initialization Vector x Register
-AT91C_TDES_ODATAxR        EQU (0xFFFA8050) ;- (TDES) Output Data x Register
-AT91C_TDES_IMR            EQU (0xFFFA8018) ;- (TDES) Interrupt Mask Register
-AT91C_TDES_MR             EQU (0xFFFA8004) ;- (TDES) Mode Register
-AT91C_TDES_CR             EQU (0xFFFA8000) ;- (TDES) Control Register
-AT91C_TDES_IER            EQU (0xFFFA8010) ;- (TDES) Interrupt Enable Register
-AT91C_TDES_ISR            EQU (0xFFFA801C) ;- (TDES) Interrupt Status Register
-AT91C_TDES_IDATAxR        EQU (0xFFFA8040) ;- (TDES) Input Data x Register
-AT91C_TDES_KEY1WxR        EQU (0xFFFA8020) ;- (TDES) Key 1 Word x Register
-
-// - *****************************************************************************
-// -               PIO DEFINITIONS FOR AT91SAM7X256
-// - *****************************************************************************
-AT91C_PIO_PA0             EQU (1 <<  0) ;- Pin Controlled by PA0
-AT91C_PA0_RXD0            EQU (AT91C_PIO_PA0) ;-  USART 0 Receive Data
-AT91C_PIO_PA1             EQU (1 <<  1) ;- Pin Controlled by PA1
-AT91C_PA1_TXD0            EQU (AT91C_PIO_PA1) ;-  USART 0 Transmit Data
-AT91C_PIO_PA10            EQU (1 << 10) ;- Pin Controlled by PA10
-AT91C_PA10_TWD            EQU (AT91C_PIO_PA10) ;-  TWI Two-wire Serial Data
-AT91C_PIO_PA11            EQU (1 << 11) ;- Pin Controlled by PA11
-AT91C_PA11_TWCK           EQU (AT91C_PIO_PA11) ;-  TWI Two-wire Serial Clock
-AT91C_PIO_PA12            EQU (1 << 12) ;- Pin Controlled by PA12
-AT91C_PA12_NPCS00         EQU (AT91C_PIO_PA12) ;-  SPI 0 Peripheral Chip Select 0
-AT91C_PIO_PA13            EQU (1 << 13) ;- Pin Controlled by PA13
-AT91C_PA13_NPCS01         EQU (AT91C_PIO_PA13) ;-  SPI 0 Peripheral Chip Select 1
-AT91C_PA13_PCK1           EQU (AT91C_PIO_PA13) ;-  PMC Programmable Clock Output 1
-AT91C_PIO_PA14            EQU (1 << 14) ;- Pin Controlled by PA14
-AT91C_PA14_NPCS02         EQU (AT91C_PIO_PA14) ;-  SPI 0 Peripheral Chip Select 2
-AT91C_PA14_IRQ1           EQU (AT91C_PIO_PA14) ;-  External Interrupt 1
-AT91C_PIO_PA15            EQU (1 << 15) ;- Pin Controlled by PA15
-AT91C_PA15_NPCS03         EQU (AT91C_PIO_PA15) ;-  SPI 0 Peripheral Chip Select 3
-AT91C_PA15_TCLK2          EQU (AT91C_PIO_PA15) ;-  Timer Counter 2 external clock input
-AT91C_PIO_PA16            EQU (1 << 16) ;- Pin Controlled by PA16
-AT91C_PA16_MISO0          EQU (AT91C_PIO_PA16) ;-  SPI 0 Master In Slave
-AT91C_PIO_PA17            EQU (1 << 17) ;- Pin Controlled by PA17
-AT91C_PA17_MOSI0          EQU (AT91C_PIO_PA17) ;-  SPI 0 Master Out Slave
-AT91C_PIO_PA18            EQU (1 << 18) ;- Pin Controlled by PA18
-AT91C_PA18_SPCK0          EQU (AT91C_PIO_PA18) ;-  SPI 0 Serial Clock
-AT91C_PIO_PA19            EQU (1 << 19) ;- Pin Controlled by PA19
-AT91C_PA19_CANRX          EQU (AT91C_PIO_PA19) ;-  CAN Receive
-AT91C_PIO_PA2             EQU (1 <<  2) ;- Pin Controlled by PA2
-AT91C_PA2_SCK0            EQU (AT91C_PIO_PA2) ;-  USART 0 Serial Clock
-AT91C_PA2_NPCS11          EQU (AT91C_PIO_PA2) ;-  SPI 1 Peripheral Chip Select 1
-AT91C_PIO_PA20            EQU (1 << 20) ;- Pin Controlled by PA20
-AT91C_PA20_CANTX          EQU (AT91C_PIO_PA20) ;-  CAN Transmit
-AT91C_PIO_PA21            EQU (1 << 21) ;- Pin Controlled by PA21
-AT91C_PA21_TF             EQU (AT91C_PIO_PA21) ;-  SSC Transmit Frame Sync
-AT91C_PA21_NPCS10         EQU (AT91C_PIO_PA21) ;-  SPI 1 Peripheral Chip Select 0
-AT91C_PIO_PA22            EQU (1 << 22) ;- Pin Controlled by PA22
-AT91C_PA22_TK             EQU (AT91C_PIO_PA22) ;-  SSC Transmit Clock
-AT91C_PA22_SPCK1          EQU (AT91C_PIO_PA22) ;-  SPI 1 Serial Clock
-AT91C_PIO_PA23            EQU (1 << 23) ;- Pin Controlled by PA23
-AT91C_PA23_TD             EQU (AT91C_PIO_PA23) ;-  SSC Transmit data
-AT91C_PA23_MOSI1          EQU (AT91C_PIO_PA23) ;-  SPI 1 Master Out Slave
-AT91C_PIO_PA24            EQU (1 << 24) ;- Pin Controlled by PA24
-AT91C_PA24_RD             EQU (AT91C_PIO_PA24) ;-  SSC Receive Data
-AT91C_PA24_MISO1          EQU (AT91C_PIO_PA24) ;-  SPI 1 Master In Slave
-AT91C_PIO_PA25            EQU (1 << 25) ;- Pin Controlled by PA25
-AT91C_PA25_RK             EQU (AT91C_PIO_PA25) ;-  SSC Receive Clock
-AT91C_PA25_NPCS11         EQU (AT91C_PIO_PA25) ;-  SPI 1 Peripheral Chip Select 1
-AT91C_PIO_PA26            EQU (1 << 26) ;- Pin Controlled by PA26
-AT91C_PA26_RF             EQU (AT91C_PIO_PA26) ;-  SSC Receive Frame Sync
-AT91C_PA26_NPCS12         EQU (AT91C_PIO_PA26) ;-  SPI 1 Peripheral Chip Select 2
-AT91C_PIO_PA27            EQU (1 << 27) ;- Pin Controlled by PA27
-AT91C_PA27_DRXD           EQU (AT91C_PIO_PA27) ;-  DBGU Debug Receive Data
-AT91C_PA27_PCK3           EQU (AT91C_PIO_PA27) ;-  PMC Programmable Clock Output 3
-AT91C_PIO_PA28            EQU (1 << 28) ;- Pin Controlled by PA28
-AT91C_PA28_DTXD           EQU (AT91C_PIO_PA28) ;-  DBGU Debug Transmit Data
-AT91C_PIO_PA29            EQU (1 << 29) ;- Pin Controlled by PA29
-AT91C_PA29_FIQ            EQU (AT91C_PIO_PA29) ;-  AIC Fast Interrupt Input
-AT91C_PA29_NPCS13         EQU (AT91C_PIO_PA29) ;-  SPI 1 Peripheral Chip Select 3
-AT91C_PIO_PA3             EQU (1 <<  3) ;- Pin Controlled by PA3
-AT91C_PA3_RTS0            EQU (AT91C_PIO_PA3) ;-  USART 0 Ready To Send
-AT91C_PA3_NPCS12          EQU (AT91C_PIO_PA3) ;-  SPI 1 Peripheral Chip Select 2
-AT91C_PIO_PA30            EQU (1 << 30) ;- Pin Controlled by PA30
-AT91C_PA30_IRQ0           EQU (AT91C_PIO_PA30) ;-  External Interrupt 0
-AT91C_PA30_PCK2           EQU (AT91C_PIO_PA30) ;-  PMC Programmable Clock Output 2
-AT91C_PIO_PA4             EQU (1 <<  4) ;- Pin Controlled by PA4
-AT91C_PA4_CTS0            EQU (AT91C_PIO_PA4) ;-  USART 0 Clear To Send
-AT91C_PA4_NPCS13          EQU (AT91C_PIO_PA4) ;-  SPI 1 Peripheral Chip Select 3
-AT91C_PIO_PA5             EQU (1 <<  5) ;- Pin Controlled by PA5
-AT91C_PA5_RXD1            EQU (AT91C_PIO_PA5) ;-  USART 1 Receive Data
-AT91C_PIO_PA6             EQU (1 <<  6) ;- Pin Controlled by PA6
-AT91C_PA6_TXD1            EQU (AT91C_PIO_PA6) ;-  USART 1 Transmit Data
-AT91C_PIO_PA7             EQU (1 <<  7) ;- Pin Controlled by PA7
-AT91C_PA7_SCK1            EQU (AT91C_PIO_PA7) ;-  USART 1 Serial Clock
-AT91C_PA7_NPCS01          EQU (AT91C_PIO_PA7) ;-  SPI 0 Peripheral Chip Select 1
-AT91C_PIO_PA8             EQU (1 <<  8) ;- Pin Controlled by PA8
-AT91C_PA8_RTS1            EQU (AT91C_PIO_PA8) ;-  USART 1 Ready To Send
-AT91C_PA8_NPCS02          EQU (AT91C_PIO_PA8) ;-  SPI 0 Peripheral Chip Select 2
-AT91C_PIO_PA9             EQU (1 <<  9) ;- Pin Controlled by PA9
-AT91C_PA9_CTS1            EQU (AT91C_PIO_PA9) ;-  USART 1 Clear To Send
-AT91C_PA9_NPCS03          EQU (AT91C_PIO_PA9) ;-  SPI 0 Peripheral Chip Select 3
-AT91C_PIO_PB0             EQU (1 <<  0) ;- Pin Controlled by PB0
-AT91C_PB0_ETXCK_EREFCK    EQU (AT91C_PIO_PB0) ;-  Ethernet MAC Transmit Clock/Reference Clock
-AT91C_PB0_PCK0            EQU (AT91C_PIO_PB0) ;-  PMC Programmable Clock Output 0
-AT91C_PIO_PB1             EQU (1 <<  1) ;- Pin Controlled by PB1
-AT91C_PB1_ETXEN           EQU (AT91C_PIO_PB1) ;-  Ethernet MAC Transmit Enable
-AT91C_PIO_PB10            EQU (1 << 10) ;- Pin Controlled by PB10
-AT91C_PB10_ETX2           EQU (AT91C_PIO_PB10) ;-  Ethernet MAC Transmit Data 2
-AT91C_PB10_NPCS11         EQU (AT91C_PIO_PB10) ;-  SPI 1 Peripheral Chip Select 1
-AT91C_PIO_PB11            EQU (1 << 11) ;- Pin Controlled by PB11
-AT91C_PB11_ETX3           EQU (AT91C_PIO_PB11) ;-  Ethernet MAC Transmit Data 3
-AT91C_PB11_NPCS12         EQU (AT91C_PIO_PB11) ;-  SPI 1 Peripheral Chip Select 2
-AT91C_PIO_PB12            EQU (1 << 12) ;- Pin Controlled by PB12
-AT91C_PB12_ETXER          EQU (AT91C_PIO_PB12) ;-  Ethernet MAC Transmikt Coding Error
-AT91C_PB12_TCLK0          EQU (AT91C_PIO_PB12) ;-  Timer Counter 0 external clock input
-AT91C_PIO_PB13            EQU (1 << 13) ;- Pin Controlled by PB13
-AT91C_PB13_ERX2           EQU (AT91C_PIO_PB13) ;-  Ethernet MAC Receive Data 2
-AT91C_PB13_NPCS01         EQU (AT91C_PIO_PB13) ;-  SPI 0 Peripheral Chip Select 1
-AT91C_PIO_PB14            EQU (1 << 14) ;- Pin Controlled by PB14
-AT91C_PB14_ERX3           EQU (AT91C_PIO_PB14) ;-  Ethernet MAC Receive Data 3
-AT91C_PB14_NPCS02         EQU (AT91C_PIO_PB14) ;-  SPI 0 Peripheral Chip Select 2
-AT91C_PIO_PB15            EQU (1 << 15) ;- Pin Controlled by PB15
-AT91C_PB15_ERXDV          EQU (AT91C_PIO_PB15) ;-  Ethernet MAC Receive Data Valid
-AT91C_PIO_PB16            EQU (1 << 16) ;- Pin Controlled by PB16
-AT91C_PB16_ECOL           EQU (AT91C_PIO_PB16) ;-  Ethernet MAC Collision Detected
-AT91C_PB16_NPCS13         EQU (AT91C_PIO_PB16) ;-  SPI 1 Peripheral Chip Select 3
-AT91C_PIO_PB17            EQU (1 << 17) ;- Pin Controlled by PB17
-AT91C_PB17_ERXCK          EQU (AT91C_PIO_PB17) ;-  Ethernet MAC Receive Clock
-AT91C_PB17_NPCS03         EQU (AT91C_PIO_PB17) ;-  SPI 0 Peripheral Chip Select 3
-AT91C_PIO_PB18            EQU (1 << 18) ;- Pin Controlled by PB18
-AT91C_PB18_EF100          EQU (AT91C_PIO_PB18) ;-  Ethernet MAC Force 100 Mbits/sec
-AT91C_PB18_ADTRG          EQU (AT91C_PIO_PB18) ;-  ADC External Trigger
-AT91C_PIO_PB19            EQU (1 << 19) ;- Pin Controlled by PB19
-AT91C_PB19_PWM0           EQU (AT91C_PIO_PB19) ;-  PWM Channel 0
-AT91C_PB19_TCLK1          EQU (AT91C_PIO_PB19) ;-  Timer Counter 1 external clock input
-AT91C_PIO_PB2             EQU (1 <<  2) ;- Pin Controlled by PB2
-AT91C_PB2_ETX0            EQU (AT91C_PIO_PB2) ;-  Ethernet MAC Transmit Data 0
-AT91C_PIO_PB20            EQU (1 << 20) ;- Pin Controlled by PB20
-AT91C_PB20_PWM1           EQU (AT91C_PIO_PB20) ;-  PWM Channel 1
-AT91C_PB20_PCK0           EQU (AT91C_PIO_PB20) ;-  PMC Programmable Clock Output 0
-AT91C_PIO_PB21            EQU (1 << 21) ;- Pin Controlled by PB21
-AT91C_PB21_PWM2           EQU (AT91C_PIO_PB21) ;-  PWM Channel 2
-AT91C_PB21_PCK1           EQU (AT91C_PIO_PB21) ;-  PMC Programmable Clock Output 1
-AT91C_PIO_PB22            EQU (1 << 22) ;- Pin Controlled by PB22
-AT91C_PB22_PWM3           EQU (AT91C_PIO_PB22) ;-  PWM Channel 3
-AT91C_PB22_PCK2           EQU (AT91C_PIO_PB22) ;-  PMC Programmable Clock Output 2
-AT91C_PIO_PB23            EQU (1 << 23) ;- Pin Controlled by PB23
-AT91C_PB23_TIOA0          EQU (AT91C_PIO_PB23) ;-  Timer Counter 0 Multipurpose Timer I/O Pin A
-AT91C_PB23_DCD1           EQU (AT91C_PIO_PB23) ;-  USART 1 Data Carrier Detect
-AT91C_PIO_PB24            EQU (1 << 24) ;- Pin Controlled by PB24
-AT91C_PB24_TIOB0          EQU (AT91C_PIO_PB24) ;-  Timer Counter 0 Multipurpose Timer I/O Pin B
-AT91C_PB24_DSR1           EQU (AT91C_PIO_PB24) ;-  USART 1 Data Set ready
-AT91C_PIO_PB25            EQU (1 << 25) ;- Pin Controlled by PB25
-AT91C_PB25_TIOA1          EQU (AT91C_PIO_PB25) ;-  Timer Counter 1 Multipurpose Timer I/O Pin A
-AT91C_PB25_DTR1           EQU (AT91C_PIO_PB25) ;-  USART 1 Data Terminal ready
-AT91C_PIO_PB26            EQU (1 << 26) ;- Pin Controlled by PB26
-AT91C_PB26_TIOB1          EQU (AT91C_PIO_PB26) ;-  Timer Counter 1 Multipurpose Timer I/O Pin B
-AT91C_PB26_RI1            EQU (AT91C_PIO_PB26) ;-  USART 1 Ring Indicator
-AT91C_PIO_PB27            EQU (1 << 27) ;- Pin Controlled by PB27
-AT91C_PB27_TIOA2          EQU (AT91C_PIO_PB27) ;-  Timer Counter 2 Multipurpose Timer I/O Pin A
-AT91C_PB27_PWM0           EQU (AT91C_PIO_PB27) ;-  PWM Channel 0
-AT91C_PIO_PB28            EQU (1 << 28) ;- Pin Controlled by PB28
-AT91C_PB28_TIOB2          EQU (AT91C_PIO_PB28) ;-  Timer Counter 2 Multipurpose Timer I/O Pin B
-AT91C_PB28_PWM1           EQU (AT91C_PIO_PB28) ;-  PWM Channel 1
-AT91C_PIO_PB29            EQU (1 << 29) ;- Pin Controlled by PB29
-AT91C_PB29_PCK1           EQU (AT91C_PIO_PB29) ;-  PMC Programmable Clock Output 1
-AT91C_PB29_PWM2           EQU (AT91C_PIO_PB29) ;-  PWM Channel 2
-AT91C_PIO_PB3             EQU (1 <<  3) ;- Pin Controlled by PB3
-AT91C_PB3_ETX1            EQU (AT91C_PIO_PB3) ;-  Ethernet MAC Transmit Data 1
-AT91C_PIO_PB30            EQU (1 << 30) ;- Pin Controlled by PB30
-AT91C_PB30_PCK2           EQU (AT91C_PIO_PB30) ;-  PMC Programmable Clock Output 2
-AT91C_PB30_PWM3           EQU (AT91C_PIO_PB30) ;-  PWM Channel 3
-AT91C_PIO_PB4             EQU (1 <<  4) ;- Pin Controlled by PB4
-AT91C_PB4_ECRS_ECRSDV     EQU (AT91C_PIO_PB4) ;-  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
-AT91C_PIO_PB5             EQU (1 <<  5) ;- Pin Controlled by PB5
-AT91C_PB5_ERX0            EQU (AT91C_PIO_PB5) ;-  Ethernet MAC Receive Data 0
-AT91C_PIO_PB6             EQU (1 <<  6) ;- Pin Controlled by PB6
-AT91C_PB6_ERX1            EQU (AT91C_PIO_PB6) ;-  Ethernet MAC Receive Data 1
-AT91C_PIO_PB7             EQU (1 <<  7) ;- Pin Controlled by PB7
-AT91C_PB7_ERXER           EQU (AT91C_PIO_PB7) ;-  Ethernet MAC Receive Error
-AT91C_PIO_PB8             EQU (1 <<  8) ;- Pin Controlled by PB8
-AT91C_PB8_EMDC            EQU (AT91C_PIO_PB8) ;-  Ethernet MAC Management Data Clock
-AT91C_PIO_PB9             EQU (1 <<  9) ;- Pin Controlled by PB9
-AT91C_PB9_EMDIO           EQU (AT91C_PIO_PB9) ;-  Ethernet MAC Management Data Input/Output
-
-// - *****************************************************************************
-// -               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
-// - *****************************************************************************
-AT91C_ID_FIQ              EQU ( 0) ;- Advanced Interrupt Controller (FIQ)
-AT91C_ID_SYS              EQU ( 1) ;- System Peripheral
-AT91C_ID_PIOA             EQU ( 2) ;- Parallel IO Controller A
-AT91C_ID_PIOB             EQU ( 3) ;- Parallel IO Controller B
-AT91C_ID_SPI0             EQU ( 4) ;- Serial Peripheral Interface 0
-AT91C_ID_SPI1             EQU ( 5) ;- Serial Peripheral Interface 1
-AT91C_ID_US0              EQU ( 6) ;- USART 0
-AT91C_ID_US1              EQU ( 7) ;- USART 1
-AT91C_ID_SSC              EQU ( 8) ;- Serial Synchronous Controller
-AT91C_ID_TWI              EQU ( 9) ;- Two-Wire Interface
-AT91C_ID_PWMC             EQU (10) ;- PWM Controller
-AT91C_ID_UDP              EQU (11) ;- USB Device Port
-AT91C_ID_TC0              EQU (12) ;- Timer Counter 0
-AT91C_ID_TC1              EQU (13) ;- Timer Counter 1
-AT91C_ID_TC2              EQU (14) ;- Timer Counter 2
-AT91C_ID_CAN              EQU (15) ;- Control Area Network Controller
-AT91C_ID_EMAC             EQU (16) ;- Ethernet MAC
-AT91C_ID_ADC              EQU (17) ;- Analog-to-Digital Converter
-AT91C_ID_AES              EQU (18) ;- Advanced Encryption Standard 128-bit
-AT91C_ID_TDES             EQU (19) ;- Triple Data Encryption Standard
-AT91C_ID_20_Reserved      EQU (20) ;- Reserved
-AT91C_ID_21_Reserved      EQU (21) ;- Reserved
-AT91C_ID_22_Reserved      EQU (22) ;- Reserved
-AT91C_ID_23_Reserved      EQU (23) ;- Reserved
-AT91C_ID_24_Reserved      EQU (24) ;- Reserved
-AT91C_ID_25_Reserved      EQU (25) ;- Reserved
-AT91C_ID_26_Reserved      EQU (26) ;- Reserved
-AT91C_ID_27_Reserved      EQU (27) ;- Reserved
-AT91C_ID_28_Reserved      EQU (28) ;- Reserved
-AT91C_ID_29_Reserved      EQU (29) ;- Reserved
-AT91C_ID_IRQ0             EQU (30) ;- Advanced Interrupt Controller (IRQ0)
-AT91C_ID_IRQ1             EQU (31) ;- Advanced Interrupt Controller (IRQ1)
-
-// - *****************************************************************************
-// -               BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
-// - *****************************************************************************
-AT91C_BASE_SYS            EQU (0xFFFFF000) ;- (SYS) Base Address
-AT91C_BASE_AIC            EQU (0xFFFFF000) ;- (AIC) Base Address
-AT91C_BASE_PDC_DBGU       EQU (0xFFFFF300) ;- (PDC_DBGU) Base Address
-AT91C_BASE_DBGU           EQU (0xFFFFF200) ;- (DBGU) Base Address
-AT91C_BASE_PIOA           EQU (0xFFFFF400) ;- (PIOA) Base Address
-AT91C_BASE_PIOB           EQU (0xFFFFF600) ;- (PIOB) Base Address
-AT91C_BASE_CKGR           EQU (0xFFFFFC20) ;- (CKGR) Base Address
-AT91C_BASE_PMC            EQU (0xFFFFFC00) ;- (PMC) Base Address
-AT91C_BASE_RSTC           EQU (0xFFFFFD00) ;- (RSTC) Base Address
-AT91C_BASE_RTTC           EQU (0xFFFFFD20) ;- (RTTC) Base Address
-AT91C_BASE_PITC           EQU (0xFFFFFD30) ;- (PITC) Base Address
-AT91C_BASE_WDTC           EQU (0xFFFFFD40) ;- (WDTC) Base Address
-AT91C_BASE_VREG           EQU (0xFFFFFD60) ;- (VREG) Base Address
-AT91C_BASE_MC             EQU (0xFFFFFF00) ;- (MC) Base Address
-AT91C_BASE_PDC_SPI1       EQU (0xFFFE4100) ;- (PDC_SPI1) Base Address
-AT91C_BASE_SPI1           EQU (0xFFFE4000) ;- (SPI1) Base Address
-AT91C_BASE_PDC_SPI0       EQU (0xFFFE0100) ;- (PDC_SPI0) Base Address
-AT91C_BASE_SPI0           EQU (0xFFFE0000) ;- (SPI0) Base Address
-AT91C_BASE_PDC_US1        EQU (0xFFFC4100) ;- (PDC_US1) Base Address
-AT91C_BASE_US1            EQU (0xFFFC4000) ;- (US1) Base Address
-AT91C_BASE_PDC_US0        EQU (0xFFFC0100) ;- (PDC_US0) Base Address
-AT91C_BASE_US0            EQU (0xFFFC0000) ;- (US0) Base Address
-AT91C_BASE_PDC_SSC        EQU (0xFFFD4100) ;- (PDC_SSC) Base Address
-AT91C_BASE_SSC            EQU (0xFFFD4000) ;- (SSC) Base Address
-AT91C_BASE_TWI            EQU (0xFFFB8000) ;- (TWI) Base Address
-AT91C_BASE_PWMC_CH3       EQU (0xFFFCC260) ;- (PWMC_CH3) Base Address
-AT91C_BASE_PWMC_CH2       EQU (0xFFFCC240) ;- (PWMC_CH2) Base Address
-AT91C_BASE_PWMC_CH1       EQU (0xFFFCC220) ;- (PWMC_CH1) Base Address
-AT91C_BASE_PWMC_CH0       EQU (0xFFFCC200) ;- (PWMC_CH0) Base Address
-AT91C_BASE_PWMC           EQU (0xFFFCC000) ;- (PWMC) Base Address
-AT91C_BASE_UDP            EQU (0xFFFB0000) ;- (UDP) Base Address
-AT91C_BASE_TC0            EQU (0xFFFA0000) ;- (TC0) Base Address
-AT91C_BASE_TC1            EQU (0xFFFA0040) ;- (TC1) Base Address
-AT91C_BASE_TC2            EQU (0xFFFA0080) ;- (TC2) Base Address
-AT91C_BASE_TCB            EQU (0xFFFA0000) ;- (TCB) Base Address
-AT91C_BASE_CAN_MB0        EQU (0xFFFD0200) ;- (CAN_MB0) Base Address
-AT91C_BASE_CAN_MB1        EQU (0xFFFD0220) ;- (CAN_MB1) Base Address
-AT91C_BASE_CAN_MB2        EQU (0xFFFD0240) ;- (CAN_MB2) Base Address
-AT91C_BASE_CAN_MB3        EQU (0xFFFD0260) ;- (CAN_MB3) Base Address
-AT91C_BASE_CAN_MB4        EQU (0xFFFD0280) ;- (CAN_MB4) Base Address
-AT91C_BASE_CAN_MB5        EQU (0xFFFD02A0) ;- (CAN_MB5) Base Address
-AT91C_BASE_CAN_MB6        EQU (0xFFFD02C0) ;- (CAN_MB6) Base Address
-AT91C_BASE_CAN_MB7        EQU (0xFFFD02E0) ;- (CAN_MB7) Base Address
-AT91C_BASE_CAN            EQU (0xFFFD0000) ;- (CAN) Base Address
-AT91C_BASE_EMAC           EQU (0xFFFDC000) ;- (EMAC) Base Address
-AT91C_BASE_PDC_ADC        EQU (0xFFFD8100) ;- (PDC_ADC) Base Address
-AT91C_BASE_ADC            EQU (0xFFFD8000) ;- (ADC) Base Address
-AT91C_BASE_PDC_AES        EQU (0xFFFA4100) ;- (PDC_AES) Base Address
-AT91C_BASE_AES            EQU (0xFFFA4000) ;- (AES) Base Address
-AT91C_BASE_PDC_TDES       EQU (0xFFFA8100) ;- (PDC_TDES) Base Address
-AT91C_BASE_TDES           EQU (0xFFFA8000) ;- (TDES) Base Address
-
-// - *****************************************************************************
-// -               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
-// - *****************************************************************************
-AT91C_ISRAM               EQU (0x00200000) ;- Internal SRAM base address
-AT91C_ISRAM_SIZE          EQU (0x00010000) ;- Internal SRAM size in byte (64 Kbyte)
-AT91C_IFLASH              EQU (0x00100000) ;- Internal ROM base address
-AT91C_IFLASH_SIZE         EQU (0x00040000) ;- Internal ROM size in byte (256 Kbyte)
-#endif /* __IAR_SYSTEMS_ASM__ */
-
-
-#endif /* AT91SAM7X256_H */
diff --git a/Demo/uIP_Demo_IAR_ARM7/SrcIAR/mii.h b/Demo/uIP_Demo_IAR_ARM7/SrcIAR/mii.h
deleted file mode 100644
index 29b2f53d5..000000000
--- a/Demo/uIP_Demo_IAR_ARM7/SrcIAR/mii.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/* Generic MII registers. */
-
-#define MII_BMCR            0x00        /* Basic mode control register */
-#define MII_BMSR            0x01        /* Basic mode status register  */
-#define MII_PHYSID1         0x02        /* PHYS ID 1                   */
-#define MII_PHYSID2         0x03        /* PHYS ID 2                   */
-#define MII_ADVERTISE       0x04        /* Advertisement control reg   */
-#define MII_LPA             0x05        /* Link partner ability reg    */
-#define MII_EXPANSION       0x06        /* Expansion register          */
-#define MII_DCOUNTER        0x12        /* Disconnect counter          */
-#define MII_FCSCOUNTER      0x13        /* False carrier counter       */
-#define MII_NWAYTEST        0x14        /* N-way auto-neg test reg     */
-#define MII_RERRCOUNTER     0x15        /* Receive error counter       */
-#define MII_SREVISION       0x16        /* Silicon revision            */
-#define MII_RESV1           0x17        /* Reserved...                 */
-#define MII_LBRERROR        0x18        /* Lpback, rx, bypass error    */
-#define MII_PHYADDR         0x19        /* PHY address                 */
-#define MII_RESV2           0x1a        /* Reserved...                 */
-#define MII_TPISTATUS       0x1b        /* TPI status for 10mbps       */
-#define MII_NCONFIG         0x1c        /* Network interface config    */
-
-/* Basic mode control register. */
-#define BMCR_RESV               0x007f  /* Unused...                   */
-#define BMCR_CTST               0x0080  /* Collision test              */
-#define BMCR_FULLDPLX           0x0100  /* Full duplex                 */
-#define BMCR_ANRESTART          0x0200  /* Auto negotiation restart    */
-#define BMCR_ISOLATE            0x0400  /* Disconnect DP83840 from MII */
-#define BMCR_PDOWN              0x0800  /* Powerdown the DP83840       */
-#define BMCR_ANENABLE           0x1000  /* Enable auto negotiation     */
-#define BMCR_SPEED100           0x2000  /* Select 100Mbps              */
-#define BMCR_LOOPBACK           0x4000  /* TXD loopback bits           */
-#define BMCR_RESET              0x8000  /* Reset the DP83840           */
-
-/* Basic mode status register. */
-#define BMSR_ERCAP              0x0001  /* Ext-reg capability          */
-#define BMSR_JCD                0x0002  /* Jabber detected             */
-#define BMSR_LSTATUS            0x0004  /* Link status                 */
-#define BMSR_ANEGCAPABLE        0x0008  /* Able to do auto-negotiation */
-#define BMSR_RFAULT             0x0010  /* Remote fault detected       */
-#define BMSR_ANEGCOMPLETE       0x0020  /* Auto-negotiation complete   */
-#define BMSR_RESV               0x07c0  /* Unused...                   */
-#define BMSR_10HALF             0x0800  /* Can do 10mbps, half-duplex  */
-#define BMSR_10FULL             0x1000  /* Can do 10mbps, full-duplex  */
-#define BMSR_100HALF            0x2000  /* Can do 100mbps, half-duplex */
-#define BMSR_100FULL            0x4000  /* Can do 100mbps, full-duplex */
-#define BMSR_100BASE4           0x8000  /* Can do 100mbps, 4k packets  */
-
-/* Advertisement control register. */
-#define ADVERTISE_SLCT          0x001f  /* Selector bits               */
-#define ADVERTISE_CSMA          0x0001  /* Only selector supported     */
-#define ADVERTISE_10HALF        0x0020  /* Try for 10mbps half-duplex  */
-#define ADVERTISE_10FULL        0x0040  /* Try for 10mbps full-duplex  */
-#define ADVERTISE_100HALF       0x0080  /* Try for 100mbps half-duplex */
-#define ADVERTISE_100FULL       0x0100  /* Try for 100mbps full-duplex */
-#define ADVERTISE_100BASE4      0x0200  /* Try for 100mbps 4k packets  */
-#define ADVERTISE_RESV          0x1c00  /* Unused...                   */
-#define ADVERTISE_RFAULT        0x2000  /* Say we can detect faults    */
-#define ADVERTISE_LPACK         0x4000  /* Ack link partners response  */
-#define ADVERTISE_NPAGE         0x8000  /* Next page bit               */
-
-#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
-			ADVERTISE_CSMA)
-#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
-                       ADVERTISE_100HALF | ADVERTISE_100FULL)
-
-/* Link partner ability register. */
-#define LPA_SLCT                0x001f  /* Same as advertise selector  */
-#define LPA_10HALF              0x0020  /* Can do 10mbps half-duplex   */
-#define LPA_10FULL              0x0040  /* Can do 10mbps full-duplex   */
-#define LPA_100HALF             0x0080  /* Can do 100mbps half-duplex  */
-#define LPA_100FULL             0x0100  /* Can do 100mbps full-duplex  */
-#define LPA_100BASE4            0x0200  /* Can do 100mbps 4k packets   */
-#define LPA_RESV                0x1c00  /* Unused...                   */
-#define LPA_RFAULT              0x2000  /* Link partner faulted        */
-#define LPA_LPACK               0x4000  /* Link partner acked us       */
-#define LPA_NPAGE               0x8000  /* Next page bit               */
-
-#define LPA_DUPLEX		(LPA_10FULL | LPA_100FULL)
-#define LPA_100			(LPA_100FULL | LPA_100HALF | LPA_100BASE4)
-
-/* Expansion register for auto-negotiation. */
-#define EXPANSION_NWAY          0x0001  /* Can do N-way auto-nego      */
-#define EXPANSION_LCWP          0x0002  /* Got new RX page code word   */
-#define EXPANSION_ENABLENPAGE   0x0004  /* This enables npage words    */
-#define EXPANSION_NPCAPABLE     0x0008  /* Link partner supports npage */
-#define EXPANSION_MFAULTS       0x0010  /* Multiple faults detected    */
-#define EXPANSION_RESV          0xffe0  /* Unused...                   */
-
-/* N-way test register. */
-#define NWAYTEST_RESV1          0x00ff  /* Unused...                   */
-#define NWAYTEST_LOOPBACK       0x0100  /* Enable loopback for N-way   */
-#define NWAYTEST_RESV2          0xfe00  /* Unused...                   */
-
-#define SPEED_10				10
-#define SPEED_100				100
-
-/* Duplex, half or full. */
-#define DUPLEX_HALF				0x00
-#define DUPLEX_FULL				0x01
-
-/* PHY ID */
-#define MII_DM9161_ID     0x0181b8a0
-#define MII_AM79C875_ID   0x00225540	/* 0x00225541 */
-
-#define AT91C_PHY_ADDR	31
diff --git a/Demo/uIP_Demo_IAR_ARM7/main.c b/Demo/uIP_Demo_IAR_ARM7/main.c
deleted file mode 100644
index 6aa5bfdbd..000000000
--- a/Demo/uIP_Demo_IAR_ARM7/main.c
+++ /dev/null
@@ -1,252 +0,0 @@
-/*
-	FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
-
-	This file is part of the FreeRTOS.org distribution.
-
-	FreeRTOS.org is free software; you can redistribute it and/or modify
-	it under the terms of the GNU General Public License as published by
-	the Free Software Foundation; either version 2 of the License, or
-	(at your option) any later version.
-
-	FreeRTOS.org is distributed in the hope that it will be useful,
-	but WITHOUT ANY WARRANTY; without even the implied warranty of
-	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-	GNU General Public License for more details.
-
-	You should have received a copy of the GNU General Public License
-	along with FreeRTOS.org; if not, write to the Free Software
-	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-
-	A special exception to the GPL can be applied should you wish to distribute
-	a combined work that includes FreeRTOS.org, without being obliged to provide
-	the source code for any proprietary components.  See the licensing section
-	of http://www.FreeRTOS.org for full details of how and when the exception
-	can be applied.
-
-	***************************************************************************
-	See http://www.FreeRTOS.org for documentation, latest information, license
-	and contact details.  Please ensure to read the configuration and relevant
-	port sections of the online documentation.
-	***************************************************************************
-*/
-
-/*
- * Creates all the application tasks, then starts the scheduler.
- *
- * A task is also created called "uIP".  This executes the uIP stack and small
- * WEB server sample.  All the other tasks are from the set of standard
- * demo tasks.  The WEB documentation provides more details of the standard
- * demo application tasks.
- *
- * Main.c also creates a task called "Check".  This only executes every three
- * seconds but has the highest priority so is guaranteed to get processor time.
- * Its main function is to check the status of all the other demo application
- * tasks.  LED mainCHECK_LED is toggled every three seconds by the check task
- * should no error conditions be detected in any of the standard demo tasks.
- * The toggle rate increasing to 500ms indicates that at least one error has
- * been detected.
- */
-
-
-/* Standard includes. */
-#include 
-#include 
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Demo application includes. */
-#include "partest.h"
-#include "PollQ.h"
-#include "dynamic.h"
-#include "semtest.h"
-#include "flash.h"
-#include "integer.h"
-#include "flop.h"
-#include "BlockQ.h"
-#include "death.h"
-#include "uip_task.h"
-
-/*-----------------------------------------------------------*/
-
-/* Priorities/stacks for the demo application tasks. */
-#define mainQUEUE_POLL_PRIORITY		( tskIDLE_PRIORITY + 1 )
-#define mainCHECK_TASK_PRIORITY		( tskIDLE_PRIORITY + 3 )
-#define mainSEM_TEST_PRIORITY		( tskIDLE_PRIORITY + 1 )
-#define mainUIP_PRIORITY			( tskIDLE_PRIORITY + 3 )
-#define mainFLASH_PRIORITY			( tskIDLE_PRIORITY + 2 )
-#define mainBLOCK_Q_PRIORITY		( tskIDLE_PRIORITY + 1 )
-#define mainDEATH_PRIORITY			( tskIDLE_PRIORITY + 2 )
-#define mainUIP_TASK_STACK_SIZE		( 250 )
-
-/* The rate at which the on board LED will toggle when there is/is not an
-error. */
-#define mainNO_ERROR_FLASH_PERIOD	( ( portTickType ) 3000 / portTICK_RATE_MS  )
-#define mainERROR_FLASH_PERIOD		( ( portTickType ) 500 / portTICK_RATE_MS  )
-
-/* The LED used by the check task to indicate the system status. */
-#define mainCHECK_LED 				( 3 )
-/*-----------------------------------------------------------*/
-
-/*
- * Checks that all the demo application tasks are still executing without error
- * - as described at the top of the file.
- */
-static portLONG prvCheckOtherTasksAreStillRunning( void );
-
-/*
- * The task that executes at the highest priority and calls
- * prvCheckOtherTasksAreStillRunning().  See the description at the top
- * of the file.
- */
-static void vErrorChecks( void *pvParameters );
-
-/*
- * Configure the processor for use with the Atmel demo board.  This is very
- * minimal as most of the setup is performed in the startup code.
- */
-static void prvSetupHardware( void );
-
-/*-----------------------------------------------------------*/
-
-/*
- * Starts all the other tasks, then starts the scheduler.
- */
-int main( void )
-{
-	/* Configure the processor. */
-	prvSetupHardware();
-
-	/* Setup the port used to flash the LED's. */
-	vParTestInitialise();
-
-	/* Start the task that handles the TCP/IP and WEB server functionality. */
-    xTaskCreate( vuIP_TASK, "uIP", mainUIP_TASK_STACK_SIZE, NULL, mainUIP_PRIORITY, NULL );
-	
-	/* Start the demo/test application tasks.  These are created in addition
-	to the TCP/IP task for demonstration and test purposes. */
-	vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
-	vStartDynamicPriorityTasks();
-	vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
-	vStartLEDFlashTasks( mainFLASH_PRIORITY );
-	vStartIntegerMathTasks( tskIDLE_PRIORITY );
-	vStartMathTasks( tskIDLE_PRIORITY );
-	vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
-
-	/* Start the check task - which is defined in this file. */	
-    xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
-
-	/* Must be last to get created. */
-	vCreateSuicidalTasks( mainDEATH_PRIORITY );
-
-	/* Now all the tasks have been started - start the scheduler. */
-	vTaskStartScheduler();
-
-	/* Should never reach here because the tasks should now be executing! */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetupHardware( void )
-{
-	/* When using the JTAG debugger the hardware is not always initialised to
-	the correct default state.  This line just ensures that this does not
-	cause all interrupts to be masked at the start. */
-	AT91C_BASE_AIC->AIC_EOICR = 0;
-	
-	/* Most setup is performed by the low level init function called from the
-	startup asm file.
-
-	Configure the PIO Lines corresponding to LED1 to LED4 to be outputs as
-	well as the UART Tx line. */
-	AT91F_PIO_CfgOutput( AT91C_BASE_PIOB, LED_MASK );
-
-	/* Enable the peripheral clock. */
-	AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, 1 << AT91C_ID_PIOA );
-	AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, 1 << AT91C_ID_PIOB ) ;
-	AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, 1 << AT91C_ID_EMAC ) ;
-}
-/*-----------------------------------------------------------*/
-
-static void vErrorChecks( void *pvParameters )
-{
-portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD;
-portTickType xLastWakeTime;
-
-	/* Initialise xLastWakeTime to ensure the first call to vTaskDelayUntil()
-	functions correctly. */
-	xLastWakeTime = xTaskGetTickCount();
-
-	/* Cycle for ever, delaying then checking all the other tasks are still
-	operating without error.  If an error is detected then the delay period
-	is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so
-	the Check LED flash rate will increase. */
-	for( ;; )
-	{
-		/* Delay until it is time to execute again.  The delay period is
-		shorter following an error. */
-		vTaskDelayUntil( &xLastWakeTime, xDelayPeriod );
-	
-		/* Check all the standard demo application tasks are executing without
-		error.  */
-		if( prvCheckOtherTasksAreStillRunning() != pdPASS )
-		{
-			/* An error has been detected in one of the tasks - flash faster. */
-			xDelayPeriod = mainERROR_FLASH_PERIOD;
-		}
-
-		vParTestToggleLED( mainCHECK_LED );
-	}
-}
-/*-----------------------------------------------------------*/
-
-static portLONG prvCheckOtherTasksAreStillRunning( void )
-{
-portLONG lReturn = ( portLONG ) pdPASS;
-
-
-	/* Check all the demo tasks (other than the flash tasks) to ensure
-	that they are all still running, and that none of them have detected
-	an error. */
-
-	if( xArePollingQueuesStillRunning() != pdTRUE )
-	{
-		lReturn = ( portLONG ) pdFAIL;
-	}
-
-	if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
-	{
-		lReturn = ( portLONG ) pdFAIL;
-	}
-
-	if( xAreSemaphoreTasksStillRunning() != pdTRUE )
-	{
-		lReturn = ( portLONG ) pdFAIL;
-	}
-
-	if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
-	{
-		lReturn = ( portLONG ) pdFAIL;
-	}
-
-	if( xAreMathsTaskStillRunning() != pdTRUE )
-	{
-		lReturn = ( portLONG ) pdFAIL;
-	}
-
-	if( xAreBlockingQueuesStillRunning() != pdTRUE )
-	{
-		lReturn = ( portLONG ) pdFAIL;
-	}
-
-	if( xIsCreateTaskStillRunning() != pdTRUE )
-	{
-		lReturn = ( portLONG ) pdFAIL;
-	}
-
-	return lReturn;
-}
-
-
-
diff --git a/Demo/uIP_Demo_IAR_ARM7/resource/SAM7.mac b/Demo/uIP_Demo_IAR_ARM7/resource/SAM7.mac
deleted file mode 100644
index 277ca1f94..000000000
--- a/Demo/uIP_Demo_IAR_ARM7/resource/SAM7.mac
+++ /dev/null
@@ -1,194 +0,0 @@
-// ---------------------------------------------------------
-//		 Microcontroller Software Support  -  ROUSSET  -
-// ---------------------------------------------------------
-// The software is delivered "AS IS" without warranty or 
-// condition of any  kind, either express, implied or 
-// statutory. This includes without limitation any warranty 
-// or condition with respect to merchantability or fitness 
-// for any particular purpose, or against the infringements of
-// intellectual property rights of others.
-// ---------------------------------------------------------
-//  File: SAM7.mac
-//
-//  1.0 08/Mar/04 JPP    : Creation
-//  1.1 23/Mar/05 JPP    : Change Variable name
-//
-//  $Revision: 1.5 $
-//
-// ---------------------------------------------------------
-
-__var __mac_i;
-__var __mac_pt;
-
-execUserReset()
-{
-   AIC();
-//*  Watchdog Disable
-   Watchdog();
-}
-
-execUserPreload()
-{
-//*  Set the RAM memory at 0x0020 0000 for code AT 0 flash area 
-     CheckRemap();
-//*  Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R
-    __mac_i =__readMemory32(0xFFFFF240,"Memory");
-    __message " ---------------------------------------- Chip ID   0x",__mac_i:%X;  
-    __mac_i =__readMemory32(0xFFFFF244,"Memory");
-    __message " ---------------------------------------- Extention 0x",__mac_i:%X;  
-//* Get the chip status
-
-//* Init AIC
-   AIC();
-//*  Watchdog Disable
-   Watchdog();
-
-}
-
-
-//-----------------------------------------------------------------------------
-// Watchdog
-//-------------------------------
-// Normally, the Watchdog is enable at the reset for load it's preferable to
-// Disable.
-//-----------------------------------------------------------------------------
-Watchdog()
-{
-//* Watchdog Disable
-//      AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS;
-   __writeMemory32(0x00008000,0xFFFFFD44,"Memory");
-   __message "------------------------------- Watchdog Disable ----------------------------------------";  
-}
-
-
-//-----------------------------------------------------------------------------
-// Check Remap
-//-------------
-//-----------------------------------------------------------------------------
-CheckRemap()
-{
-//* Read the value at 0x0
-    __mac_i =__readMemory32(0x00000000,"Memory");
-    __mac_i =__mac_i+1;
-    __writeMemory32(__mac_i,0x00,"Memory");
-    __mac_pt =__readMemory32(0x00000000,"Memory");
-    
- if (__mac_i == __mac_pt)  
- {
-   __message "------------------------------- The Remap is done ----------------------------------------";  
-//*   Toggel RESET The remap
-    __writeMemory32(0x00000001,0xFFFFFF00,"Memory");
-   
- } else {  
-   __message "------------------------------- The Remap is NOT -----------------------------------------";  
- }
-
-}
-
-
-execUserSetup()
-{
- ini();
-     __message "-------------------------------Set PC ----------------------------------------";  
-     __writeMemory32(0x00000000,0xB4,"Register");
-}
-
-//-----------------------------------------------------------------------------
-// Reset the Interrupt Controller
-//-------------------------------
-// Normally, the code is executed only if a reset has been actually performed.
-// So, the AIC initialization resumes at setting up the default vectors.
-//-----------------------------------------------------------------------------
-AIC()
-{
-// Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF;
-    __writeMemory32(0xffffffff,0xFFFFF124,"Memory");
-    __writeMemory32(0xffffffff,0xFFFFF128,"Memory");
-// disable peripheral clock  Peripheral Clock Disable Register
-    __writeMemory32(0xffffffff,0xFFFFFC14,"Memory");
-
-// #define AT91C_TC0_SR    ((AT91_REG *) 	0xFFFA0020) // (TC0) Status Register
-// #define AT91C_TC1_SR    ((AT91_REG *) 	0xFFFA0060) // (TC1) Status Register
-// #define AT91C_TC2_SR    ((AT91_REG *) 	0xFFFA00A0) // (TC2) Status Register
-    __readMemory32(0xFFFA0020,"Memory");
-    __readMemory32(0xFFFA0060,"Memory");
-    __readMemory32(0xFFFA00A0,"Memory");
-
-    for (__mac_i=0;__mac_i < 8; __mac_i++)
-    {
-      // AT91C_BASE_AIC->AIC_EOICR
-      __mac_pt  =  __readMemory32(0xFFFFF130,"Memory");
-    
-    }
-   __message "------------------------------- AIC 2 INIT ---------------------------------------------";  
-}
-
-ini()
-{
-__writeMemory32(0x0,0x00,"Register");
-__writeMemory32(0x0,0x04,"Register");
-__writeMemory32(0x0,0x08,"Register");
-__writeMemory32(0x0,0x0C,"Register");
-__writeMemory32(0x0,0x10,"Register");
-__writeMemory32(0x0,0x14,"Register");
-__writeMemory32(0x0,0x18,"Register");
-__writeMemory32(0x0,0x1C,"Register");
-__writeMemory32(0x0,0x20,"Register");
-__writeMemory32(0x0,0x24,"Register");
-__writeMemory32(0x0,0x28,"Register");
-__writeMemory32(0x0,0x2C,"Register");
-__writeMemory32(0x0,0x30,"Register");
-__writeMemory32(0x0,0x34,"Register");
-__writeMemory32(0x0,0x38,"Register");
-
-// Set CPSR
-__writeMemory32(0x0D3,0x98,"Register");
-
-
-}
-
-RG()
-{
-
-__mac_i =__readMemory32(0x00,"Register");   __message "R00 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x04,"Register");   __message "R01 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x08,"Register");   __message "R02 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x0C,"Register");   __message "R03 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x10,"Register");   __message "R04 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x14,"Register");   __message "R05 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x18,"Register");   __message "R06 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x1C,"Register");   __message "R07 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x20,"Register");   __message "R08 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x24,"Register");   __message "R09 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x28,"Register");   __message "R10 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x2C,"Register");   __message "R11 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x30,"Register");   __message "R12 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x34,"Register");   __message "R13 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x38,"Register");   __message "R14 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x3C,"Register");   __message "R13 SVC 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x40,"Register");   __message "R14 SVC 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x44,"Register");   __message "R13 ABT 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x48,"Register");   __message "R14 ABT 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x4C,"Register");   __message "R13 UND 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x50,"Register");   __message "R14 UND 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x54,"Register");   __message "R13 IRQ 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x58,"Register");   __message "R14 IRQ 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x5C,"Register");   __message "R08 FIQ 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x60,"Register");   __message "R09 FIQ 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x64,"Register");   __message "R10 FIQ 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x68,"Register");   __message "R11 FIQ 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x6C,"Register");   __message "R12 FIQ 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x70,"Register");   __message "R13 FIQ 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x74,"Register");   __message "R14 FIQ0x",__mac_i:%X; 
-__mac_i =__readMemory32(0x98,"Register");   __message "CPSR     ",__mac_i:%X; 
-__mac_i =__readMemory32(0x94,"Register");   __message "SPSR     ",__mac_i:%X; 
-__mac_i =__readMemory32(0x9C,"Register");   __message "SPSR ABT ",__mac_i:%X; 
-__mac_i =__readMemory32(0xA0,"Register");   __message "SPSR ABT ",__mac_i:%X; 
-__mac_i =__readMemory32(0xA4,"Register");   __message "SPSR UND ",__mac_i:%X; 
-__mac_i =__readMemory32(0xA8,"Register");   __message "SPSR IRQ ",__mac_i:%X; 
-__mac_i =__readMemory32(0xAC,"Register");   __message "SPSR FIQ ",__mac_i:%X; 
-
-__mac_i =__readMemory32(0xB4,"Register");   __message "PC 0x",__mac_i:%X;  
-
-}
-
diff --git a/Demo/uIP_Demo_IAR_ARM7/resource/SAM7_RAM.mac b/Demo/uIP_Demo_IAR_ARM7/resource/SAM7_RAM.mac
deleted file mode 100644
index 63228c346..000000000
--- a/Demo/uIP_Demo_IAR_ARM7/resource/SAM7_RAM.mac
+++ /dev/null
@@ -1,227 +0,0 @@
-// ---------------------------------------------------------
-//   ATMEL Microcontroller Software Support  -  ROUSSET  -
-// ---------------------------------------------------------
-// The software is delivered "AS IS" without warranty or 
-// condition of any  kind, either express, implied or 
-// statutory. This includes without limitation any warranty 
-// or condition with respect to merchantability or fitness 
-// for any particular purpose, or against the infringements of
-// intellectual property rights of others.
-// ---------------------------------------------------------
-//  File: SAM7_RAM.mac
-//
-//  1.0 08/Mar/05 JPP    : Creation
-//  1.1 23/Mar/05 JPP    : Change Variable name
-//
-//  $Revision: 1.6 $
-//
-// ---------------------------------------------------------
-
-__var __mac_i;
-__var __mac_pt;
-__var __mac_mem;
-execUserReset()
-{
-     CheckNoRemap();
-     ini();
-     AIC();
-     __message "-------------------------------Set PC Reset ----------------------------------";  
-     __writeMemory32(0x00000000,0xB4,"Register");
-}
-
-execUserPreload()
-{
-//*  __message "-------------------------------Set CPSR  ----------------------------------";  
-     __writeMemory32(0xD3,0x98,"Register"); 
-    __writeMemory32(0xffffffff,0xFFFFFC14,"Memory");
-     PllSetting();
- //* Init AIC
-     AIC();
-
-//*  Set the RAM memory at 0x0020 0000 for code AT 0 flash area 
-     CheckNoRemap();
-//*  Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R
-    __mac_i=__readMemory32(0xFFFFF240,"Memory");
-    __message " ---------------------------------------- Chip ID   0x",__mac_i:%X;  
-    __mac_i=__readMemory32(0xFFFFF244,"Memory");
-    __message " ---------------------------------------- Extention 0x",__mac_i:%X;  
-    __mac_i=__readMemory32(0xFFFFFF6C,"Memory");
-    __message " ---------------------------------------- Flash Version 0x",__mac_i:%X;  
-
-//*  Watchdog Disable
-    Watchdog();
-//*    RG();
-}
-//-----------------------------------------------------------------------------
-// PllSetting
-//-------------------------------
-// Set PLL
-//-----------------------------------------------------------------------------
-PllSetting()
-{
-// -1- Enabling the Main Oscillator:
-//*#define AT91C_PMC_MOR   ((AT91_REG *) 	0xFFFFFC20) // (PMC) Main Oscillator Register
-//*#define AT91C_PMC_PLLR  ((AT91_REG *) 	0xFFFFFC2C) // (PMC) PLL Register
-//*#define AT91C_PMC_MCKR  ((AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register
-
-//*pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) |    //0x0000 0600
-//                          AT91C_CKGR_MOSCEN ));          //0x0000 0001 
-__writeMemory32(0x00000601,0xFFFFFC20,"Memory");
-
-// -2- Wait
-// -3- Setting PLL and divider:
-// - div by 5 Fin = 3,6864 =(18,432 / 5)
-// - Mul 25+1: Fout =	95,8464 =(3,6864 *26)
-// for 96 MHz the erroe is 0.16%
-// Field out NOT USED = 0
-// PLLCOUNT pll startup time esrtimate at : 0.844 ms
-// PLLCOUNT 28 = 0.000844 /(1/32768)
-//       pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x05) |       //0x0000 0005
-//                         (AT91C_CKGR_PLLCOUNT & (28<<8)) //0x0000 1C00
-//                         (AT91C_CKGR_MUL & (25<<16)));   //0x0019 0000 
-__writeMemory32(0x00191C05,0xFFFFFC2C,"Memory");
-// -2- Wait
-// -5- Selection of Master Clock and Processor Clock
-// select the PLL clock divided by 2
-//	    pPMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK |     //0x0000 0003
-//                           AT91C_PMC_PRES_CLK_2 ;      //0x0000 0004
-__writeMemory32(0x00000007,0xFFFFFC30,"Memory");        
-       
-
-   __message "------------------------------- PLL  Enable ----------------------------------------";  
-}
-
-//-----------------------------------------------------------------------------
-// Watchdog
-//-------------------------------
-// Normally, the Watchdog is enable at the reset for load it's preferable to
-// Disable.
-//-----------------------------------------------------------------------------
-Watchdog()
-{
-//* Watchdog Disable
-//      AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS;
-   __writeMemory32(0x00008000,0xFFFFFD44,"Memory");
-   __message "------------------------------- Watchdog Disable ----------------------------------------";  
-}
-
-CheckNoRemap()
-{
-//* Read the value at 0x0
-    __mac_i =__readMemory32(0x00000000,"Memory");
-    __mac_mem = __mac_i;
-    __mac_i=__mac_i+1;
-    __writeMemory32(__mac_i,0x00,"Memory");
-    __mac_pt=__readMemory32(0x00000000,"Memory");
-    
- if (__mac_i == __mac_pt)  
- {
-   __message "------------------------------- The Remap is done ----------------------------------------";  
-   __writeMemory32( __mac_mem,0x00000000,"Memory");
-  
- } else {  
-   __message "------------------------------- The Remap is NOT -----------------------------------------";  
-//*   Toggel RESET The remap
-    __writeMemory32(0x00000001,0xFFFFFF00,"Memory");
- }
-
-}
-
-//-----------------------------------------------------------------------------
-// Reset the Interrupt Controller
-//-------------------------------
-// Normally, the code is executed only if a reset has been actually performed.
-// So, the AIC initialization resumes at setting up the default vectors.
-//-----------------------------------------------------------------------------
-AIC()
-{
-// Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF;
-    __writeMemory32(0xffffffff,0xFFFFF124,"Memory");
-    __writeMemory32(0xffffffff,0xFFFFF128,"Memory");
-// disable peripheral clock  Peripheral Clock Disable Register
-    __writeMemory32(0xffffffff,0xFFFFFC14,"Memory");
-
-// #define AT91C_TC0_SR    ((AT91_REG *) 	0xFFFA0020) // (TC0) Status Register
-// #define AT91C_TC1_SR    ((AT91_REG *) 	0xFFFA0060) // (TC1) Status Register
-// #define AT91C_TC2_SR    ((AT91_REG *) 	0xFFFA00A0) // (TC2) Status Register
-    __readMemory32(0xFFFA0020,"Memory");
-    __readMemory32(0xFFFA0060,"Memory");
-    __readMemory32(0xFFFA00A0,"Memory");
-    for (__mac_i=0;__mac_i < 8; __mac_i++)
-    {
-      // AT91C_BASE_AIC->AIC_EOICR
-      __mac_pt  =  __readMemory32(0xFFFFF130,"Memory");
-    
-    }
-   __message "------------------------------- AIC 2 INIT ---------------------------------------------";  
-}
-
-ini()
-{
-__writeMemory32(0x0,0x00,"Register");
-__writeMemory32(0x0,0x04,"Register");
-__writeMemory32(0x0,0x08,"Register");
-__writeMemory32(0x0,0x0C,"Register");
-__writeMemory32(0x0,0x10,"Register");
-__writeMemory32(0x0,0x14,"Register");
-__writeMemory32(0x0,0x18,"Register");
-__writeMemory32(0x0,0x1C,"Register");
-__writeMemory32(0x0,0x20,"Register");
-__writeMemory32(0x0,0x24,"Register");
-__writeMemory32(0x0,0x28,"Register");
-__writeMemory32(0x0,0x2C,"Register");
-__writeMemory32(0x0,0x30,"Register");
-__writeMemory32(0x0,0x34,"Register");
-__writeMemory32(0x0,0x38,"Register");
-
-// Set CPSR
-__writeMemory32(0x0D3,0x98,"Register");
-
-
-}
-
-RG()
-{
-
-__mac_i =__readMemory32(0x00,"Register");   __message "R00 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x04,"Register");   __message "R01 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x08,"Register");   __message "R02 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x0C,"Register");   __message "R03 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x10,"Register");   __message "R04 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x14,"Register");   __message "R05 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x18,"Register");   __message "R06 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x1C,"Register");   __message "R07 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x20,"Register");   __message "R08 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x24,"Register");   __message "R09 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x28,"Register");   __message "R10 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x2C,"Register");   __message "R11 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x30,"Register");   __message "R12 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x34,"Register");   __message "R13 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x38,"Register");   __message "R14 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x3C,"Register");   __message "R13 SVC 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x40,"Register");   __message "R14 SVC 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x44,"Register");   __message "R13 ABT 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x48,"Register");   __message "R14 ABT 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x4C,"Register");   __message "R13 UND 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x50,"Register");   __message "R14 UND 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x54,"Register");   __message "R13 IRQ 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x58,"Register");   __message "R14 IRQ 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x5C,"Register");   __message "R08 FIQ 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x60,"Register");   __message "R09 FIQ 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x64,"Register");   __message "R10 FIQ 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x68,"Register");   __message "R11 FIQ 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x6C,"Register");   __message "R12 FIQ 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x70,"Register");   __message "R13 FIQ 0x",__mac_i:%X;  
-__mac_i =__readMemory32(0x74,"Register");   __message "R14 FIQ0x",__mac_i:%X; 
-__mac_i =__readMemory32(0x98,"Register");   __message "CPSR     ",__mac_i:%X; 
-__mac_i =__readMemory32(0x94,"Register");   __message "SPSR     ",__mac_i:%X; 
-__mac_i =__readMemory32(0x9C,"Register");   __message "SPSR ABT ",__mac_i:%X; 
-__mac_i =__readMemory32(0xA0,"Register");   __message "SPSR ABT ",__mac_i:%X; 
-__mac_i =__readMemory32(0xA4,"Register");   __message "SPSR UND ",__mac_i:%X; 
-__mac_i =__readMemory32(0xA8,"Register");   __message "SPSR IRQ ",__mac_i:%X; 
-__mac_i =__readMemory32(0xAC,"Register");   __message "SPSR FIQ ",__mac_i:%X; 
-
-__mac_i =__readMemory32(0xB4,"Register");   __message "PC 0x",__mac_i:%X;  
-
-}
-
diff --git a/Demo/uIP_Demo_IAR_ARM7/resource/at91SAM7X256_NoRemap.xcl b/Demo/uIP_Demo_IAR_ARM7/resource/at91SAM7X256_NoRemap.xcl
deleted file mode 100644
index 95fa2e1de..000000000
--- a/Demo/uIP_Demo_IAR_ARM7/resource/at91SAM7X256_NoRemap.xcl
+++ /dev/null
@@ -1,135 +0,0 @@
-// ---------------------------------------------------------
-//   ATMEL Microcontroller Software Support  -  ROUSSET  -
-// ---------------------------------------------------------
-// The software is delivered "AS IS" without warranty or 
-// condition of any  kind, either express, implied or 
-// statutory. This includes without limitation any warranty 
-// or condition with respect to merchantability or fitness 
-// for any particular purpose, or against the infringements of
-// intellectual property rights of others.
-// ---------------------------------------------------------
-//  File: at91SAM7x256_NoRemap.xlc
-//
-//
-//  $Revision: 1.1.1.1 $
-//
-// ---------------------------------------------------------
-
-//*************************************************************************
-// XLINK command file template for EWARM/ICCARM
-//
-// Usage:  xlink  -f lnkarm  
-//                -s   
-//
-// $Revision: 1.1.1.1 $
-//*************************************************************************
-
-//************************************************
-// Inform the linker about the CPU family used.
-// AT91SAM7S64 Memory mapping
-// No remap
-//  ROMSTART
-//  Start address 0x0000 0000 
-//  Size  256 Kbo 0x0004 0000 
-//  RAMSTART
-//  Start address 0x0020 0000 
-//  Size  64Kbo   0x0001 0000 
-// Remap done
-//  RAMSTART
-//  Start address 0x0000 0000 
-//  Size  64Kbo   0x0001 0000 
-//  ROMSTART
-//  Start address 0x0010 0000 
-//  Size  256Kbo  0x0004 0000 
-
-//************************************************
--carm
-
-//*************************************************************************
-// Internal Ram segments mapped AFTER REMAP 64K.
-//*************************************************************************
-// Use these addresses for the .
--Z(CONST)INTRAMSTART_REMAP=00200000
--Z(CONST)INTRAMEND_REMAP=0020FFFF
-
-//*************************************************************************
-// Read-only segments mapped to Flash 256K.
-//*************************************************************************
--DROMSTART=00000000
--DROMEND=0003FFFF
-//*************************************************************************
-// Read/write segments mapped to RAM.
-//*************************************************************************
--DRAMSTART=00200000
--DRAMEND=00200FFFF
-
-//************************************************
-// Address range for reset and exception
-// vectors (INTVEC).
-// The vector area is 32 bytes, 
-// an additional 32 bytes is allocated for the
-// constant table used by ldr PC in cstartup.s79.
-//************************************************
--Z(CODE)INTVEC=00-3F
-
-//************************************************
-// Startup code and exception routines (ICODE).
-//************************************************
--Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND
--Z(CODE)SWITAB=ROMSTART-ROMEND
-
-//************************************************
-// Code segments may be placed anywhere.
-//************************************************
--Z(CODE)CODE=ROMSTART-ROMEND
-
-//************************************************
-// Various constants and initializers.
-//************************************************
--Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND
--Z(CONST)CHECKSUM=ROMSTART-ROMEND
-
-
-//************************************************
-// Data segments.
-//************************************************
--Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND
-
-//************************************************
-// __ramfunc code copied to and executed from RAM.
-//************************************************
--Z(DATA)CODE_I=RAMSTART-RAMEND
-
-//************************************************
-// ICCARM produces code for __ramfunc functions in
-// CODE_I segments. The -Q XLINK command line
-// option redirects XLINK to emit the code in the
-// debug information associated with the CODE_I
-// segment, where the code will execute.
-//************************************************
-
-//*************************************************************************
-// Stack and heap segments.
-//*************************************************************************
-//-D_CSTACK_SIZE=(400*4)
-//-D_IRQ_STACK_SIZE=(2*8*4)
-
-//-Z(DATA)CSTACK+_CSTACK_SIZE=RAMSTART-RAMEND
-//-Z(DATA)IRQ_STACK+_IRQ_STACK_SIZE=RAMSTART-RAMEND
-
-//*************************************************************************
-// ELF/DWARF support.
-//
-// Uncomment the line "-Felf" below to generate ELF/DWARF output.
-// Available format specifiers are:
-//
-//   "-yn": Suppress DWARF debug output
-//   "-yp": Multiple ELF program sections
-//   "-yas": Format suitable for debuggers from ARM Ltd (also sets -p flag)
-//
-// "-Felf" and the format specifiers can also be supplied directly as
-// command line options, or selected from the Xlink Output tab in the
-// IAR Embedded Workbench.
-//*************************************************************************
-
-// -Felf
diff --git a/Demo/uIP_Demo_IAR_ARM7/rtosdemo.dep b/Demo/uIP_Demo_IAR_ARM7/rtosdemo.dep
deleted file mode 100644
index 04b6ad8ff..000000000
--- a/Demo/uIP_Demo_IAR_ARM7/rtosdemo.dep
+++ /dev/null
@@ -1,1590 +0,0 @@
-
-
-
-  2
-  
-    Flash Debug
-    
-      $PROJ_DIR$\uip\uipopt.h
-      $PROJ_DIR$\uip\fsdata.h
-      $TOOLKIT_DIR$\inc\intrinsic.h
-      $PROJ_DIR$\Flash_Debug\Obj\uip_arp.r79
-      $PROJ_DIR$\Flash_Debug\Obj\queue.r79
-      $PROJ_DIR$\Flash_Debug\Obj\ParTest.r79
-      $PROJ_DIR$\Flash_Debug\Obj\list.r79
-      $PROJ_DIR$\Flash_Debug\Obj\PollQ.r79
-      $PROJ_DIR$\..\..\Source\portable\IAR\AtmelSAM7S64\lib_AT91SAM7X256.h
-      $PROJ_DIR$\uip\uip.c
-      $PROJ_DIR$\..\..\Source\tasks.c
-      $PROJ_DIR$\..\..\Source\include\semphr.h
-      $PROJ_DIR$\uip\cgi.c
-      $PROJ_DIR$\uip\fs.c
-      $PROJ_DIR$\uip\httpd.c
-      $PROJ_DIR$\Flash_Debug\Obj\death.r79
-      $PROJ_DIR$\SrcIAR\Board.h
-      $PROJ_DIR$\..\Common\include\BlockQ.h
-      $PROJ_DIR$\..\..\Source\include\portable.h
-      $PROJ_DIR$\SrcIAR\Cstartup_SAM7.c
-      $PROJ_DIR$\SrcIAR\Cstartup.s79
-      $PROJ_DIR$\uip\uip_arp.c
-      $PROJ_DIR$\uip\uip_arch.c
-      $PROJ_DIR$\..\..\Source\portable\IAR\AtmelSAM7S64\ISR_Support.h
-      $PROJ_DIR$\Flash_Debug\Obj\BlockQ.r79
-      $PROJ_DIR$\Flash_Debug\Obj\heap_2.r79
-      $PROJ_DIR$\SrcIAR\Emac.h
-      $PROJ_DIR$\Flash_Debug\Obj\httpd.r79
-      $PROJ_DIR$\..\..\Source\portable\IAR\AtmelSAM7S64\AT91SAM7X256_inc.h
-      $PROJ_DIR$\EMAC\SAM7_EMAC.h
-      $PROJ_DIR$\Flash_Debug\Obj\main.pbi
-      $PROJ_DIR$\..\..\Source\portable\IAR\AtmelSAM7S64\AT91SAM7X256.h
-      $PROJ_DIR$\Flash_Debug\Obj\integer.r79
-      $PROJ_DIR$\Flash_Debug\Obj\portasm.r79
-      $PROJ_DIR$\uip\httpd.h
-      $PROJ_DIR$\Flash_Debug\Obj\SAM7_EMAC.r79
-      $PROJ_DIR$\Flash_Debug\Obj\dynamic.r79
-      $PROJ_DIR$\resource\at91SAM7X256_NoRemap.xcl
-      $PROJ_DIR$\..\Common\Minimal\death.c
-      $PROJ_DIR$\Flash_Debug\Obj\BlockQ.pbi
-      $TOOLKIT_DIR$\inc\DLib_Threads.h
-      $PROJ_DIR$\Flash_Debug\Obj\cgi.r79
-      $PROJ_DIR$\Flash_Debug\Obj\integer.pbi
-      $PROJ_DIR$\Flash_Debug\Exe\rtosdemo.sim
-      $PROJ_DIR$\Flash_Debug\Obj\Cstartup_SAM7.r79
-      $PROJ_DIR$\..\Common\include\death.h
-      $TOOLKIT_DIR$\inc\stddef.h
-      $PROJ_DIR$\Flash_Debug\Obj\main.r79
-      $PROJ_DIR$\Flash_Debug\Obj\port.r79
-      $PROJ_DIR$\Flash_Debug\Obj\flop.r79
-      $PROJ_DIR$\Flash_Debug\Obj\Cstartup.r79
-      $PROJ_DIR$\..\..\Source\include\croutine.h
-      $PROJ_DIR$\Flash_Debug\Obj\queue.pbi
-      $PROJ_DIR$\Flash_Debug\Obj\Cstartup_SAM7.pbi
-      $PROJ_DIR$\..\..\Source\portable\IAR\AtmelSAM7S64\AT91SAM7S64_inc.h
-      $PROJ_DIR$\Flash_Debug\Obj\flash.r79
-      $PROJ_DIR$\..\Common\include\integer.h
-      $PROJ_DIR$\Flash_Debug\Obj\semtest.r79
-      $TOOLKIT_DIR$\inc\string.h
-      $PROJ_DIR$\uip\tapdev.h
-      $PROJ_DIR$\Flash_Debug\Obj\list.pbi
-      $PROJ_DIR$\..\Common\include\semtest.h
-      $PROJ_DIR$\uip\uip_arp.h
-      $PROJ_DIR$\uip\fs.h
-      $PROJ_DIR$\..\Common\include\partest.h
-      $PROJ_DIR$\..\..\Source\include\list.h
-      $TOOLKIT_DIR$\inc\stdlib.h
-      $PROJ_DIR$\Flash_Debug\Obj\fs.r79
-      $PROJ_DIR$\..\..\Source\include\task.h
-      $TOOLKIT_DIR$\inc\xencoding_limits.h
-      $PROJ_DIR$\..\Common\include\PollQ.h
-      $PROJ_DIR$\..\..\Source\portable\IAR\AtmelSAM7S64\portmacro.h
-      $PROJ_DIR$\Flash_Debug\Exe\rtosdemo.d79
-      $PROJ_DIR$\Flash_Debug\Obj\dynamic.pbi
-      $TOOLKIT_DIR$\lib\dl4tptinl8n.h
-      $PROJ_DIR$\..\Common\Minimal\semtest.c
-      $PROJ_DIR$\uip\fsdata.c
-      $PROJ_DIR$\Flash_Debug\Obj\fs.pbi
-      $PROJ_DIR$\Flash_Debug\List\rtosdemo.map
-      $PROJ_DIR$\Flash_Debug\Obj\uIP_Task.r79
-      $PROJ_DIR$\Flash_Debug\Obj\EMAClISR.r79
-      $PROJ_DIR$\Flash_Debug\Obj\semtest.pbi
-      $PROJ_DIR$\uip\uip.h
-      $PROJ_DIR$\ParTest\ParTest.c
-      $TOOLKIT_DIR$\inc\stdio.h
-      $PROJ_DIR$\Flash_Debug\Obj\death.pbi
-      $PROJ_DIR$\uIP_Task.c
-      $PROJ_DIR$\..\Common\Minimal\PollQ.c
-      $PROJ_DIR$\EMAC\SAM7_EMAC.c
-      $PROJ_DIR$\..\Common\include\flop.h
-      $PROJ_DIR$\..\Common\include\flash.h
-      $PROJ_DIR$\uip\cgi.h
-      $PROJ_DIR$\..\..\Source\include\FreeRTOS.h
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deleted file mode 100644
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diff --git a/Demo/uIP_Demo_IAR_ARM7/uIP_Task.c b/Demo/uIP_Demo_IAR_ARM7/uIP_Task.c
deleted file mode 100644
index 24f0bc3ee..000000000
--- a/Demo/uIP_Demo_IAR_ARM7/uIP_Task.c
+++ /dev/null
@@ -1,207 +0,0 @@
-/*
- * Modified from an original work that is Copyright (c) 2001-2003, Adam Dunkels.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote
- *    products derived from this software without specific prior
- *    written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
- * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
- * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * This file is part of the uIP TCP/IP stack.
- *
- * $Id: main.c,v 1.10.2.4 2003/10/21 21:27:51 adam Exp $
- *
- */
-
-/* Standard includes. */
-#include 
-#include 
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "semphr.h"
-#include "task.h"
-
-/* Demo app includes. */
-#include "SAM7_EMAC.h"
-
-/* uIP includes. */
-#undef HTONS
-#include "uip.h"
-#include "uip_arp.h"
-#include "tapdev.h"
-#include "httpd.h"
-
-/* The start of the uIP buffer, which will contain the frame headers. */
-#define pucUIP_Buffer ( ( struct uip_eth_hdr * ) &uip_buf[ 0 ] )
-
-/* uIP update frequencies. */
-#define RT_CLOCK_SECOND		( configTICK_RATE_HZ  )
-#define uipARP_FREQUENCY	( 20 )
-#define uipMAX_BLOCK_TIME	( RT_CLOCK_SECOND / 4 )
-
-/*-----------------------------------------------------------*/
-
-void vuIP_TASK( void *pvParameters )
-{
-/* The semaphore used by the EMAC ISR to indicate that an Rx frame is ready
-for processing. */
-xSemaphoreHandle xSemaphore = NULL;
-portBASE_TYPE xARPTimer;
-unsigned portBASE_TYPE uxPriority;
-static volatile portTickType xStartTime, xCurrentTime;
-
-	/* Initialize the uIP TCP/IP stack. */
-	uip_init();
-	uip_arp_init();
-	
-	/* Initialize the HTTP server. */
-	httpd_init();
-
-	/* Initialise the local timers. */
-	xStartTime = xTaskGetTickCount();
-	xARPTimer = 0;
-
-	/* Initialise the EMAC.  A semaphore will be returned when this is
-	successful. This routine contains code that polls status bits.  If the
-	Ethernet cable is not plugged in then this can take a considerable time.
-	To prevent this starving lower priority tasks of processing time we
-	lower our priority prior to the call, then raise it back again once the
-	initialisation is complete. */
-	uxPriority = uxTaskPriorityGet( NULL );
-	vTaskPrioritySet( NULL, tskIDLE_PRIORITY );
-	while( xSemaphore == NULL )
-	{
-		xSemaphore = xEMACInit();
-	}
-	vTaskPrioritySet( NULL, uxPriority );
-
-	for( ;; )
-	{
-		/* Let the network device driver read an entire IP packet
-		into the uip_buf. If it returns > 0, there is a packet in the
-		uip_buf buffer. */
-		uip_len = ulEMACPoll();
-
-		/* Was a packet placed in the uIP buffer? */
-		if( uip_len > 0 )
-		{
-			/* A packet is present in the uIP buffer. We call the
-			appropriate ARP functions depending on what kind of packet we
-			have received. If the packet is an IP packet, we should call
-			uip_input() as well. */
-			if( pucUIP_Buffer->type == htons( UIP_ETHTYPE_IP ) )
-			{
-				uip_arp_ipin();
-				uip_input();
-
-				/* If the above function invocation resulted in data that
-				should be sent out on the network, the global variable
-				uip_len is set to a value > 0. */
-				if( uip_len > 0 )
-				{
-					uip_arp_out();
-					lEMACSend();
-				}
-			}
-			else if( pucUIP_Buffer->type == htons( UIP_ETHTYPE_ARP ) )
-			{
-				uip_arp_arpin();
-
-				/* If the above function invocation resulted in data that
-				should be sent out on the network, the global variable
-				uip_len is set to a value > 0. */	
-				if( uip_len > 0 )
-				{	
-					lEMACSend();
-				}
-			}
-		}
-		else
-		{
-			/* The poll function returned 0, so no packet was
-			received. Instead we check if it is time that we do the
-			periodic processing. */
-			xCurrentTime = xTaskGetTickCount();
-
-			if( ( xCurrentTime - xStartTime ) >= RT_CLOCK_SECOND )
-			{
-				portBASE_TYPE i;
-
-				/* Reset the timer. */
-				xStartTime = xCurrentTime;
-
-				/* Periodic check of all connections. */
-				for( i = 0; i < UIP_CONNS; i++ )
-				{
-					uip_periodic( i );
-
-					/* If the above function invocation resulted in data that
-					should be sent out on the network, the global variable
-					uip_len is set to a value > 0. */					
-					if( uip_len > 0 )
-					{
-						uip_arp_out();
-						lEMACSend();
-					}
-				}
-
-				#if UIP_UDP
-					for( i = 0; i < UIP_UDP_CONNS; i++ )
-					{
-						uip_udp_periodic( i );
-
-						/* If the above function invocation resulted in data that
-						should be sent out on the network, the global variable
-						uip_len is set to a value > 0. */
-						if( uip_len > 0 )
-						{
-							uip_arp_out();
-							tapdev_send();
-						}
-					}
-				#endif /* UIP_UDP */
-
-				/* Periodically call the ARP timer function. */
-				if( ++xARPTimer == uipARP_FREQUENCY )
-				{	
-					uip_arp_timer();
-					xARPTimer = 0;
-				}
-			}
-			else
-			{				
-				/* We did not receive a packet, and there was no periodic
-				processing to perform.  Block for a fixed period.  If a packet
-				is received during this period we will be woken by the ISR
-				giving us the Semaphore. */
-				xSemaphoreTake( xSemaphore, uipMAX_BLOCK_TIME );
-			}
-		}
-	}
-}
-/*-----------------------------------------------------------------------------------*/
-
-
-
-
-
diff --git a/Demo/uIP_Demo_IAR_ARM7/uIP_Task.h b/Demo/uIP_Demo_IAR_ARM7/uIP_Task.h
deleted file mode 100644
index aae424ba0..000000000
--- a/Demo/uIP_Demo_IAR_ARM7/uIP_Task.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef UIP_TASK_H
-#define UIP_TASK_H
-
-/* The task that handles all uIP data. */
-void vuIP_TASK( void *pvParameters );
-
-#endif
-
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/Makefile b/Demo/uIP_Demo_IAR_ARM7/uip/Makefile
deleted file mode 100644
index 61d3a06aa..000000000
--- a/Demo/uIP_Demo_IAR_ARM7/uip/Makefile
+++ /dev/null
@@ -1,74 +0,0 @@
-# Copyright (c) 2001, Adam Dunkels.
-# All rights reserved. 
-#
-# Redistribution and use in source and binary forms, with or without 
-# modification, are permitted provided that the following conditions 
-# are met: 
-# 1. Redistributions of source code must retain the above copyright 
-#    notice, this list of conditions and the following disclaimer. 
-# 2. Redistributions in binary form must reproduce the above copyright 
-#    notice, this list of conditions and the following disclaimer in the 
-#    documentation and/or other materials provided with the distribution. 
-# 3. All advertising materials mentioning features or use of this software
-#    must display the following acknowledgement:
-#      This product includes software developed by Adam Dunkels.
-# 4. The name of the author may not be used to endorse or promote
-#    products derived from this software without specific prior
-#    written permission.  
-#
-# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
-# OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-# ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
-# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
-#
-# This file is part of the uIP TCP/IP stack.
-#
-# $Id: Makefile,v 1.8.2.2 2003/10/04 22:54:17 adam Exp $
-#
-
-CC=gcc
-CFLAGS=-Wall -g -I../uip -I. -I../apps/httpd -I../apps/resolv -I../apps/webclient -I../apps/smtp  -I../apps/telnet -fpack-struct
-
-%.o:
-	$(CC) $(CFLAGS) -c $(<:.o=.c)
-
-
-uip: uip.o uip_arch.o tapdev.o httpd.o main.o fs.o uip_arp.o cgi.o 
-
-tapdev.o: tapdev.c uipopt.h
-main.o: main.c ../uip/uip.h uipopt.h ../apps/httpd/httpd.h \
- tapdev.h
-uip_arch.o: uip_arch.c ../uip/uip_arch.h ../uip/uip.h uipopt.h \
- ../apps/httpd/httpd.h 
-uip.o: ../uip/uip.c ../uip/uip.h uipopt.h ../apps/httpd/httpd.h 
-
-uip_arp.o: ../uip/uip_arp.c ../uip/uip_arp.h ../uip/uip.h uipopt.h \
- ../apps/httpd/httpd.h
-	$(CC) -o uip_arp.o $(CFLAGS) -fpack-struct -c ../uip/uip_arp.c
-
-
-cgi.o: ../apps/httpd/cgi.c ../uip/uip.h uipopt.h ../apps/smtp/smtp.h \
- ../apps/httpd/cgi.h ../apps/httpd/httpd.h ../apps/httpd/fs.h
-fs.o: ../apps/httpd/fs.c ../uip/uip.h uipopt.h ../apps/smtp/smtp.h \
- ../apps/httpd/httpd.h ../apps/httpd/fs.h ../apps/httpd/fsdata.h \
- ../apps/httpd/fsdata.c
-fsdata.o: ../apps/httpd/fsdata.c
-httpd.o: ../apps/httpd/httpd.c ../uip/uip.h uipopt.h \
- ../apps/smtp/smtp.h ../apps/httpd/httpd.h ../apps/httpd/fs.h \
- ../apps/httpd/fsdata.h ../apps/httpd/cgi.h
-
-clean:
-	rm -f *.o *~ *core uip
-
-
-
-
-
-
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/cgi.c b/Demo/uIP_Demo_IAR_ARM7/uip/cgi.c
deleted file mode 100644
index 748cc1b5d..000000000
--- a/Demo/uIP_Demo_IAR_ARM7/uip/cgi.c
+++ /dev/null
@@ -1,225 +0,0 @@
-/**
- * \addtogroup httpd
- * @{
- */
-
-/**
- * \file
- * HTTP server script language C functions file.
- * \author Adam Dunkels 
- *
- * This file contains functions that are called by the web server
- * scripts. The functions takes one argument, and the return value is
- * interpreted as follows. A zero means that the function did not
- * complete and should be invoked for the next packet as well. A
- * non-zero value indicates that the function has completed and that
- * the web server should move along to the next script line.
- *
- */
-
-/*
- * Copyright (c) 2001, Adam Dunkels.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote
- *    products derived from this software without specific prior
- *    written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
- * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
- * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * This file is part of the uIP TCP/IP stack.
- *
- * $Id: cgi.c,v 1.23.2.4 2003/10/07 13:22:27 adam Exp $
- *
- */
-
-#include "uip.h"
-#include "cgi.h"
-#include "httpd.h"
-#include "fs.h"
-
-#include 
-#include 
-
-static u8_t print_stats(u8_t next);
-static u8_t file_stats(u8_t next);
-static u8_t tcp_stats(u8_t next);
-static u8_t rtos_stats(u8_t next);
-
-cgifunction cgitab[] = {
-  print_stats,   /* CGI function "a" */
-  file_stats,    /* CGI function "b" */
-  tcp_stats,      /* CGI function "c" */
-  rtos_stats	/* CGI function "d" */
-};
-
-static const char closed[] =   /*  "CLOSED",*/
-{0x43, 0x4c, 0x4f, 0x53, 0x45, 0x44, 0};
-static const char syn_rcvd[] = /*  "SYN-RCVD",*/
-{0x53, 0x59, 0x4e, 0x2d, 0x52, 0x43, 0x56,
- 0x44,  0};
-static const char syn_sent[] = /*  "SYN-SENT",*/
-{0x53, 0x59, 0x4e, 0x2d, 0x53, 0x45, 0x4e,
- 0x54,  0};
-static const char established[] = /*  "ESTABLISHED",*/
-{0x45, 0x53, 0x54, 0x41, 0x42, 0x4c, 0x49, 0x53, 0x48,
- 0x45, 0x44, 0};
-static const char fin_wait_1[] = /*  "FIN-WAIT-1",*/
-{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49,
- 0x54, 0x2d, 0x31, 0};
-static const char fin_wait_2[] = /*  "FIN-WAIT-2",*/
-{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49,
- 0x54, 0x2d, 0x32, 0};
-static const char closing[] = /*  "CLOSING",*/
-{0x43, 0x4c, 0x4f, 0x53, 0x49,
- 0x4e, 0x47, 0};
-static const char time_wait[] = /*  "TIME-WAIT,"*/
-{0x54, 0x49, 0x4d, 0x45, 0x2d, 0x57, 0x41,
- 0x49, 0x54, 0};
-static const char last_ack[] = /*  "LAST-ACK"*/
-{0x4c, 0x41, 0x53, 0x54, 0x2d, 0x41, 0x43,
- 0x4b, 0};
-
-static const char *states[] = {
-  closed,
-  syn_rcvd,
-  syn_sent,
-  established,
-  fin_wait_1,
-  fin_wait_2,
-  closing,
-  time_wait,
-  last_ack};
-
-
-/*-----------------------------------------------------------------------------------*/
-/* print_stats:
- *
- * Prints out a part of the uIP statistics. The statistics data is
- * written into the uip_appdata buffer. It overwrites any incoming
- * packet.
- */
-static u8_t
-print_stats(u8_t next)
-{
-#if UIP_STATISTICS
-  u16_t i, j;
-  u8_t *buf;
-  u16_t *databytes;
-
-  if(next) {
-    /* If our last data has been acknowledged, we move on the next
-       chunk of statistics. */
-    hs->count = hs->count + 4;
-    if(hs->count >= sizeof(struct uip_stats)/sizeof(u16_t)) {
-      /* We have printed out all statistics, so we return 1 to
-	 indicate that we are done. */
-      return 1;
-    }
-  }
-
-  /* Write part of the statistics into the uip_appdata buffer. */
-  databytes = (u16_t *)&uip_stat + hs->count;
-  buf       = (u8_t *)uip_appdata;
-
-  j = 4 + 1;
-  i = hs->count;
-  while (i < sizeof(struct uip_stats)/sizeof(u16_t) && --j > 0) {
-    sprintf((char *)buf, "%5u\r\n", *databytes);
-    ++databytes;
-    buf += 6;
-    ++i;
-  }
-
-  /* Send the data. */
-  uip_send(uip_appdata, buf - uip_appdata);
-
-  return 0;
-#else
-  return 1;
-#endif /* UIP_STATISTICS */
-}
-/*-----------------------------------------------------------------------------------*/
-static u8_t
-file_stats(u8_t next)
-{
-  /* We use sprintf() to print the number of file accesses to a
-     particular file (given as an argument to the function in the
-     script). We then use uip_send() to actually send the data. */
-  if(next) {
-    return 1;
-  }
-  uip_send(uip_appdata, sprintf((char *)uip_appdata, "%5u", fs_count(&hs->script[4])));
-  return 0;
-}
-/*-----------------------------------------------------------------------------------*/
-static u8_t
-tcp_stats(u8_t next)
-{
-  struct uip_conn *conn;
-
-  if(next) {
-    /* If the previously sent data has been acknowledged, we move
-       forward one connection. */
-    if(++hs->count == UIP_CONNS) {
-      /* If all connections has been printed out, we are done and
-	 return 1. */
-      return 1;
-    }
-  }
-
-  conn = &uip_conns[hs->count];
-  if((conn->tcpstateflags & TS_MASK) == CLOSED) {
-    uip_send(uip_appdata, sprintf((char *)uip_appdata,
-				  "
\r\n", - conn->nrtx, - conn->timer, - (uip_outstanding(conn))? '*':' ', - (uip_stopped(conn))? '!':' ')); - } else { - uip_send(uip_appdata, sprintf((char *)uip_appdata, - "\r\n", - htons(conn->ripaddr[0]) >> 8, - htons(conn->ripaddr[0]) & 0xff, - htons(conn->ripaddr[1]) >> 8, - htons(conn->ripaddr[1]) & 0xff, - htons(conn->rport), - states[conn->tcpstateflags & TS_MASK], - conn->nrtx, - conn->timer, - (uip_outstanding(conn))? '*':' ', - (uip_stopped(conn))? '!':' ')); - } - return 0; -} -/*-----------------------------------------------------------------------------------*/ - -static u8_t -rtos_stats(u8_t next) -{ -static char cTraceBuffer[ 1024 ]; -extern void ( vTaskList )( char * ); - - vTaskList( cTraceBuffer ); - uip_send( ( void * ) cTraceBuffer, strlen( cTraceBuffer ) ); - - return 1; -} diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/cgi.h b/Demo/uIP_Demo_IAR_ARM7/uip/cgi.h deleted file mode 100644 index d85389b52..000000000 --- a/Demo/uIP_Demo_IAR_ARM7/uip/cgi.h +++ /dev/null @@ -1,57 +0,0 @@ -/** - * \addtogroup httpd - * @{ - */ - -/** - * \file - * HTTP script language header file. - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2001, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: cgi.h,v 1.3.2.4 2003/10/07 13:22:27 adam Exp $ - * - */ - -#ifndef __CGI_H__ -#define __CGI_H__ - -typedef u8_t (* cgifunction)(u8_t next); - -/** - * A table containing pointers to C functions that can be called from - * a web server script. - */ -extern cgifunction cgitab[]; - -#endif /* __CGI_H__ */ diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/crt0.asm b/Demo/uIP_Demo_IAR_ARM7/uip/crt0.asm deleted file mode 100644 index ef91f42a8..000000000 --- a/Demo/uIP_Demo_IAR_ARM7/uip/crt0.asm +++ /dev/null @@ -1,66 +0,0 @@ -// Rowley C Compiler, runtime support. -// -// Copyright (c) 2001, 2002, 2003 Rowley Associates Limited. -// -// This file may be distributed under the terms of the License Agreement -// provided with this software. -// -// THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE -// WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. - -; Create sections - .data - .bss - -; Go to code section. - .code - -; Executed upon reset -__reset proc - -; Turn off watchdog. You can enable it in main() if required. - mov.w #0x5a80, &0x120 - -; Set up stack. - mov.w #RAM_Start_Address+RAM_Size, sp - -; Copy from initialised data section to data section. - mov.w #SFB(IDATA0), r15 - mov.w #data_init_begin, r14 - mov.w #data_init_end-data_init_begin, r13 - call #_memcpy - -; Zero the bss. Ensure the stack is not allocated in the bss! - mov.w #SFB(UDATA0), r15 - mov.w #0, r14 - mov.w #SFE(UDATA0)-SFB(UDATA0), r13 - call #_memset - -; Call user entry point void main(void). - call #_main - -; If main() returns, kick off again. - jmp __reset - endproc - -; Heap data structures; removed by the linker if the heap isn't used. - .break - .data - align WORD -___heap_start__:: - DW 0 - DW heap_size - DS heap_size-4 - -; Reset vector - .vectors - .keep - org 0x1e - dw __reset - -; Initialise the IDATA0 section by duplicating the contents into the -; CONST section and copying them on startup. - .const -data_init_begin: - .init "IDATA0" -data_init_end: diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/fs.c b/Demo/uIP_Demo_IAR_ARM7/uip/fs.c deleted file mode 100644 index a66eb8dc3..000000000 --- a/Demo/uIP_Demo_IAR_ARM7/uip/fs.c +++ /dev/null @@ -1,156 +0,0 @@ -/** - * \addtogroup httpd - * @{ - */ - -/** - * \file - * HTTP server read-only file system code. - * \author Adam Dunkels - * - * A simple read-only filesystem. - */ - -/* - * Copyright (c) 2001, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - * $Id: fs.c,v 1.7.2.3 2003/10/07 13:22:27 adam Exp $ - */ - -#include "uip.h" -#include "httpd.h" -#include "fs.h" -#include "fsdata.h" - -#define NULL (void *)0 -#include "fsdata.c" - -#ifdef FS_STATISTICS -#if FS_STATISTICS == 1 -static u16_t count[FS_NUMFILES]; -#endif /* FS_STATISTICS */ -#endif /* FS_STATISTICS */ - -/*-----------------------------------------------------------------------------------*/ -static u8_t -fs_strcmp(const char *str1, const char *str2) -{ - u8_t i; - i = 0; - loop: - - if(str2[i] == 0 || - str1[i] == '\r' || - str1[i] == '\n') { - return 0; - } - - if(str1[i] != str2[i]) { - return 1; - } - - - ++i; - goto loop; -} -/*-----------------------------------------------------------------------------------*/ -int -fs_open(const char *name, struct fs_file *file) -{ -#ifdef FS_STATISTICS -#if FS_STATISTICS == 1 - u16_t i = 0; -#endif /* FS_STATISTICS */ -#endif /* FS_STATISTICS */ - struct fsdata_file_noconst *f; - - for(f = (struct fsdata_file_noconst *)FS_ROOT; - f != NULL; - f = (struct fsdata_file_noconst *)f->next) { - - if(fs_strcmp(name, f->name) == 0) { - file->data = f->data; - file->len = f->len; -#ifdef FS_STATISTICS -#if FS_STATISTICS == 1 - ++count[i]; -#endif /* FS_STATISTICS */ -#endif /* FS_STATISTICS */ - - return 1; - } -#ifdef FS_STATISTICS -#if FS_STATISTICS == 1 - ++i; -#endif /* FS_STATISTICS */ -#endif /* FS_STATISTICS */ - - } - return 0; -} -/*-----------------------------------------------------------------------------------*/ -void -fs_init(void) -{ -#ifdef FS_STATISTICS -#if FS_STATISTICS == 1 - u16_t i; - for(i = 0; i < FS_NUMFILES; i++) { - count[i] = 0; - } -#endif /* FS_STATISTICS */ -#endif /* FS_STATISTICS */ -} -/*-----------------------------------------------------------------------------------*/ -#ifdef FS_STATISTICS -#if FS_STATISTICS == 1 -u16_t fs_count -(char *name) -{ - struct fsdata_file_noconst *f; - u16_t i; - - i = 0; - for(f = (struct fsdata_file_noconst *)FS_ROOT; - f != NULL; - f = (struct fsdata_file_noconst *)f->next) { - - if(fs_strcmp(name, f->name) == 0) { - return count[i]; - } - ++i; - } - return 0; -} -#endif /* FS_STATISTICS */ -#endif /* FS_STATISTICS */ -/*-----------------------------------------------------------------------------------*/ diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/fs.h b/Demo/uIP_Demo_IAR_ARM7/uip/fs.h deleted file mode 100644 index 65551ba41..000000000 --- a/Demo/uIP_Demo_IAR_ARM7/uip/fs.h +++ /dev/null @@ -1,80 +0,0 @@ -/** - * \addtogroup httpd - * @{ - */ - -/** - * \file - * HTTP server read-only file system header file. - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2001, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - * $Id: fs.h,v 1.6.2.3 2003/10/07 13:22:27 adam Exp $ - */ -#ifndef __FS_H__ -#define __FS_H__ - -#include "uip.h" - -/** - * An open file in the read-only file system. - */ -struct fs_file { - char *data; /**< The actual file data. */ - int len; /**< The length of the file data. */ -}; - -/** - * Open a file in the read-only file system. - * - * \param name The name of the file. - * - * \param file The file pointer, which must be allocated by caller and - * will be filled in by the function. - */ -int fs_open(const char *name, struct fs_file *file); - -#ifdef FS_STATISTICS -#if FS_STATISTICS == 1 -u16_t fs_count(char *name); -#endif /* FS_STATISTICS */ -#endif /* FS_STATISTICS */ - -/** - * Initialize the read-only file system. - */ -void fs_init(void); - -#endif /* __FS_H__ */ diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/fs/404.html b/Demo/uIP_Demo_IAR_ARM7/uip/fs/404.html deleted file mode 100644 index 8d6beec83..000000000 --- a/Demo/uIP_Demo_IAR_ARM7/uip/fs/404.html +++ /dev/null @@ -1 +0,0 @@ -

404 - file not found

\ No newline at end of file diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/files b/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/files deleted file mode 100644 index 58c45f30f..000000000 --- a/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/files +++ /dev/null @@ -1,26 +0,0 @@ -# This script shows the access statistics for different files on the -# web server. -# -# First, we include the HTML header. -i /files_header.html -# Print out the name of the file, and call the function that prints -# the access statistics of that file. -t -# Include the HTML footer. -i /files_footer.plain -# End of script. -. \ No newline at end of file diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/rtos b/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/rtos deleted file mode 100644 index 7772ea420..000000000 --- a/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/rtos +++ /dev/null @@ -1,6 +0,0 @@ -t uIP Open Source Embedded TCP/IP Stack On FreeRTOS KernelFreeRTOS Homepage

AT91SAM7X Embedded WEB Server Demo
Using uIP and the FreeRTOS real time kernel

These pages are being served by an Atmel AT91SAM7X256 microcontroller, using Adam Dunkels open source uIP TCP/IP stack.

The uIP stack is executing from a single task under control of the FreeRTOS real time kernel. The table below shows the statistics for all the tasks in the demo applicaiton.

Task          State  Priority  Stack	#
************************************************

-c d
-t
-. - - diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/stats b/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/stats deleted file mode 100644 index 2c71c90dc..000000000 --- a/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/stats +++ /dev/null @@ -1,4 +0,0 @@ -i /stats_header.html -c a -i /stats_footer.plain -. diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/tcp b/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/tcp deleted file mode 100644 index 14efd3700..000000000 --- a/Demo/uIP_Demo_IAR_ARM7/uip/fs/cgi/tcp +++ /dev/null @@ -1,4 +0,0 @@ -i /tcp_header.html -c c -i /tcp_footer.plain -. \ No newline at end of file diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/fs/control.html b/Demo/uIP_Demo_IAR_ARM7/uip/fs/control.html deleted file mode 100644 index 0d9352ce7..000000000 --- a/Demo/uIP_Demo_IAR_ARM7/uip/fs/control.html +++ /dev/null @@ -1,20 +0,0 @@ - - -AT91SAM7X Embedded WEB Server using uIP and FreeRTOS - - - - -Tasks | -Connections | -Files | -Statistics
-
- - - - - - - - diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/fs/files_footer.plain b/Demo/uIP_Demo_IAR_ARM7/uip/fs/files_footer.plain deleted file mode 100644 index 0b6dceb4f..000000000 --- a/Demo/uIP_Demo_IAR_ARM7/uip/fs/files_footer.plain +++ /dev/null @@ -1,3 +0,0 @@ -
LocalRemoteStateRetransmissionsTimerFlags
--%u%u%c %c
%u.%u.%u.%u:%u%s%u%u%c %c
/index.html -c b /index.html -t
/control.html -c b /control.html -t
/img/logo.png -c b /img/logo.png -t
/404.html -c b /404.html -t
/cgi/files -c b /cgi/files -t
/cgi/stats -c b /cgi/stats -t
/cgi/tcp -c b /cgi/tcp -t
- - diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/fs/files_header.html b/Demo/uIP_Demo_IAR_ARM7/uip/fs/files_header.html deleted file mode 100644 index 20cf1c961..000000000 --- a/Demo/uIP_Demo_IAR_ARM7/uip/fs/files_header.html +++ /dev/null @@ -1,4 +0,0 @@ - - -
- diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/fs/img/logo.png b/Demo/uIP_Demo_IAR_ARM7/uip/fs/img/logo.png deleted file mode 100644 index ef572dd38..000000000 Binary files a/Demo/uIP_Demo_IAR_ARM7/uip/fs/img/logo.png and /dev/null differ diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/fs/index.html b/Demo/uIP_Demo_IAR_ARM7/uip/fs/index.html deleted file mode 100644 index 626ff3780..000000000 --- a/Demo/uIP_Demo_IAR_ARM7/uip/fs/index.html +++ /dev/null @@ -1,15 +0,0 @@ - - - - - - - - - - -<body> -Your browser must support frames -</body> - - \ No newline at end of file diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/fs/stats_footer.plain b/Demo/uIP_Demo_IAR_ARM7/uip/fs/stats_footer.plain deleted file mode 100644 index 0b6dceb4f..000000000 --- a/Demo/uIP_Demo_IAR_ARM7/uip/fs/stats_footer.plain +++ /dev/null @@ -1,3 +0,0 @@ -
- - diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/fs/stats_header.html b/Demo/uIP_Demo_IAR_ARM7/uip/fs/stats_header.html deleted file mode 100644 index e819c3449..000000000 --- a/Demo/uIP_Demo_IAR_ARM7/uip/fs/stats_header.html +++ /dev/null @@ -1,30 +0,0 @@ - - -
- -
-
-IP           Packets dropped
-             Packets received
-             Packets sent
-IP errors    IP version/header length
-             IP length, high byte
-             IP length, low byte
-             IP fragments
-             Header checksum
-             Wrong protocol
-ICMP	     Packets dropped
-             Packets received
-             Packets sent
-             Type errors
-TCP          Packets dropped
-             Packets received
-             Packets sent
-             Checksum errors
-             Data packets without ACKs
-             Resets
-             Retransmissions
-	     No connection avaliable
-	     Connection attempts to closed ports
-
-
\ No newline at end of file
diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/fs/tcp_footer.plain b/Demo/uIP_Demo_IAR_ARM7/uip/fs/tcp_footer.plain
deleted file mode 100644
index 442c17a58..000000000
--- a/Demo/uIP_Demo_IAR_ARM7/uip/fs/tcp_footer.plain
+++ /dev/null
@@ -1,5 +0,0 @@
-
-
-
- - \ No newline at end of file diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/fs/tcp_header.html b/Demo/uIP_Demo_IAR_ARM7/uip/fs/tcp_header.html deleted file mode 100644 index 47bdf302c..000000000 --- a/Demo/uIP_Demo_IAR_ARM7/uip/fs/tcp_header.html +++ /dev/null @@ -1,6 +0,0 @@ - - -
- - - diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/fsdata.c b/Demo/uIP_Demo_IAR_ARM7/uip/fsdata.c deleted file mode 100644 index 6a3c5140a..000000000 --- a/Demo/uIP_Demo_IAR_ARM7/uip/fsdata.c +++ /dev/null @@ -1,968 +0,0 @@ -static const char data_404_html[] = { - /* /404.html */ - 0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0, - 0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x34, - 0x30, 0x34, 0x20, 0x46, 0x69, 0x6c, 0x65, 0x20, 0x6e, 0x6f, - 0x74, 0x20, 0x66, 0x6f, 0x75, 0x6e, 0x64, 0xd, 0xa, 0x53, - 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, - 0x2f, 0x30, 0x2e, 0x39, 0x20, 0x28, 0x68, 0x74, 0x74, 0x70, - 0x3a, 0x2f, 0x2f, 0x64, 0x75, 0x6e, 0x6b, 0x65, 0x6c, 0x73, - 0x2e, 0x63, 0x6f, 0x6d, 0x2f, 0x61, 0x64, 0x61, 0x6d, 0x2f, - 0x75, 0x69, 0x70, 0x2f, 0x29, 0xd, 0xa, 0x43, 0x6f, 0x6e, - 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, - 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, - 0xd, 0xa, 0xd, 0xa, 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, - 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10}}; - -const struct fsdata_file file_control_html[] = {{file_404_html, data_control_html, data_control_html + 14, sizeof(data_control_html) - 14}}; - -const struct fsdata_file file_files_footer_plain[] = {{file_control_html, data_files_footer_plain, data_files_footer_plain + 20, sizeof(data_files_footer_plain) - 20}}; - -const struct fsdata_file file_files_header_html[] = {{file_files_footer_plain, data_files_header_html, data_files_header_html + 19, sizeof(data_files_header_html) - 19}}; - -const struct fsdata_file file_stats_footer_plain[] = {{file_files_header_html, data_stats_footer_plain, data_stats_footer_plain + 20, sizeof(data_stats_footer_plain) - 20}}; - -const struct fsdata_file file_stats_header_html[] = {{file_stats_footer_plain, data_stats_header_html, data_stats_header_html + 19, sizeof(data_stats_header_html) - 19}}; - -const struct fsdata_file file_tcp_footer_plain[] = {{file_stats_header_html, data_tcp_footer_plain, data_tcp_footer_plain + 18, sizeof(data_tcp_footer_plain) - 18}}; - -const struct fsdata_file file_tcp_header_html[] = {{file_tcp_footer_plain, data_tcp_header_html, data_tcp_header_html + 17, sizeof(data_tcp_header_html) - 17}}; - -const struct fsdata_file file_img_logo_png[] = {{file_tcp_header_html, data_img_logo_png, data_img_logo_png + 14, sizeof(data_img_logo_png) - 14}}; - -const struct fsdata_file file_cgi_files[] = {{file_img_logo_png, data_cgi_files, data_cgi_files + 11, sizeof(data_cgi_files) - 11}}; - -const struct fsdata_file file_cgi_stats[] = {{file_cgi_files, data_cgi_stats, data_cgi_stats + 11, sizeof(data_cgi_stats) - 11}}; - -const struct fsdata_file file_cgi_tcp[] = {{file_cgi_stats, data_cgi_tcp, data_cgi_tcp + 9, sizeof(data_cgi_tcp) - 9}}; - -const struct fsdata_file file_cgi_rtos[] = {{file_cgi_tcp, data_cgi_rtos, data_cgi_rtos + 10, sizeof(data_cgi_rtos) - 10}}; - -const struct fsdata_file file_index_html[] = {{file_cgi_rtos, data_index_html, data_index_html + 12, sizeof(data_index_html) - 12}}; - -#define FS_ROOT file_index_html - -#define FS_NUMFILES 14 diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/fsdata.h b/Demo/uIP_Demo_IAR_ARM7/uip/fsdata.h deleted file mode 100644 index 94086c4df..000000000 --- a/Demo/uIP_Demo_IAR_ARM7/uip/fsdata.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2001, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - * $Id: fsdata.h,v 1.4.2.1 2003/10/04 22:54:06 adam Exp $ - */ -#ifndef __FSDATA_H__ -#define __FSDATA_H__ - -#include "uipopt.h" - -struct fsdata_file { - const struct fsdata_file *next; - const char *name; - const char *data; - const int len; -#ifdef FS_STATISTICS -#if FS_STATISTICS == 1 - u16_t count; -#endif /* FS_STATISTICS */ -#endif /* FS_STATISTICS */ -}; - -struct fsdata_file_noconst { - struct fsdata_file *next; - char *name; - char *data; - int len; -#ifdef FS_STATISTICS -#if FS_STATISTICS == 1 - u16_t count; -#endif /* FS_STATISTICS */ -#endif /* FS_STATISTICS */ -}; - -#endif /* __FSDATA_H__ */ diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/httpd.c b/Demo/uIP_Demo_IAR_ARM7/uip/httpd.c deleted file mode 100644 index 108fa26e8..000000000 --- a/Demo/uIP_Demo_IAR_ARM7/uip/httpd.c +++ /dev/null @@ -1,372 +0,0 @@ -/** - * \addtogroup exampleapps - * @{ - */ - -/** - * \defgroup httpd Web server - * @{ - * - * The uIP web server is a very simplistic implementation of an HTTP - * server. It can serve web pages and files from a read-only ROM - * filesystem, and provides a very small scripting language. - * - * The script language is very simple and works as follows. Each - * script line starts with a command character, either "i", "t", "c", - * "#" or ".". The "i" command tells the script interpreter to - * "include" a file from the virtual file system and output it to the - * web browser. The "t" command should be followed by a line of text - * that is to be output to the browser. The "c" command is used to - * call one of the C functions from the httpd-cgi.c file. A line that - * starts with a "#" is ignored (i.e., the "#" denotes a comment), and - * the "." denotes the last script line. - * - * The script that produces the file statistics page looks somewhat - * like this: - * - \code -i /header.html -t

File statistics


RemoteStateRetransmissionsTimerFlags
-t
/index.html -c a /index.html -t
/cgi/files -c a /cgi/files -t
/cgi/tcp -c a /cgi/tcp -t
/404.html -c a /404.html -t
-i /footer.plain -. - \endcode - * - */ - - -/** - * \file - * HTTP server. - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2001, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: httpd.c,v 1.28.2.6 2003/10/07 13:22:27 adam Exp $ - * - */ - - -#include "uip.h" -#include "httpd.h" -#include "fs.h" -#include "fsdata.h" -#include "cgi.h" - -#define NULL (void *)0 - -/* The HTTP server states: */ -#define HTTP_NOGET 0 -#define HTTP_FILE 1 -#define HTTP_TEXT 2 -#define HTTP_FUNC 3 -#define HTTP_END 4 - -#ifdef DEBUG -#include -#define PRINT(x) -#define PRINTLN(x) -#else /* DEBUG */ -#define PRINT(x) -#define PRINTLN(x) -#endif /* DEBUG */ - -struct httpd_state *hs; - -extern const struct fsdata_file file_index_html; -extern const struct fsdata_file file_404_html; - -static void next_scriptline(void); -static void next_scriptstate(void); - -#define ISO_G 0x47 -#define ISO_E 0x45 -#define ISO_T 0x54 -#define ISO_slash 0x2f -#define ISO_c 0x63 -#define ISO_g 0x67 -#define ISO_i 0x69 -#define ISO_space 0x20 -#define ISO_nl 0x0a -#define ISO_cr 0x0d -#define ISO_a 0x61 -#define ISO_t 0x74 -#define ISO_hash 0x23 -#define ISO_period 0x2e - -#define httpPORT 80 - -/*-----------------------------------------------------------------------------------*/ -/** - * Initialize the web server. - * - * Starts to listen for incoming connection requests on TCP port 80. - */ -/*-----------------------------------------------------------------------------------*/ -void -httpd_init(void) -{ - fs_init(); - - /* Listen to port 80. */ - uip_listen(HTONS(httpPORT)); -} -/*-----------------------------------------------------------------------------------*/ -void -httpd_appcall(void) -{ - struct fs_file fsfile; - - u8_t i; - - switch(uip_conn->lport) { - /* This is the web server: */ - case HTONS(httpPORT): - /* Pick out the application state from the uip_conn structure. */ - hs = (struct httpd_state *)(uip_conn->appstate); - - /* We use the uip_ test functions to deduce why we were - called. If uip_connected() is non-zero, we were called - because a remote host has connected to us. If - uip_newdata() is non-zero, we were called because the - remote host has sent us new data, and if uip_acked() is - non-zero, the remote host has acknowledged the data we - previously sent to it. */ - if(uip_connected()) { - /* Since we have just been connected with the remote host, we - reset the state for this connection. The ->count variable - contains the amount of data that is yet to be sent to the - remote host, and the ->state is set to HTTP_NOGET to signal - that we haven't received any HTTP GET request for this - connection yet. */ - - hs->state = HTTP_NOGET; - hs->count = 0; - return; - - } else if(uip_poll()) { - /* If we are polled ten times, we abort the connection. This is - because we don't want connections lingering indefinately in - the system. */ - if(hs->count++ >= 10) { - uip_abort(); - } - return; - } else if(uip_newdata() && hs->state == HTTP_NOGET) { - /* This is the first data we receive, and it should contain a - GET. */ - - /* Check for GET. */ - if(uip_appdata[0] != ISO_G || - uip_appdata[1] != ISO_E || - uip_appdata[2] != ISO_T || - uip_appdata[3] != ISO_space) { - /* If it isn't a GET, we abort the connection. */ - uip_abort(); - return; - } - - /* Find the file we are looking for. */ - for(i = 4; i < 40; ++i) { - if(uip_appdata[i] == ISO_space || - uip_appdata[i] == ISO_cr || - uip_appdata[i] == ISO_nl) { - uip_appdata[i] = 0; - break; - } - } - - PRINT("request for file "); - PRINTLN(&uip_appdata[4]); - - /* Check for a request for "/". */ - if(uip_appdata[4] == ISO_slash && - uip_appdata[5] == 0) { - fs_open(file_index_html.name, &fsfile); - } else { - if(!fs_open((const char *)&uip_appdata[4], &fsfile)) { - PRINTLN("couldn't open file"); - fs_open(file_404_html.name, &fsfile); - } - } - - - if(uip_appdata[4] == ISO_slash && - uip_appdata[5] == ISO_c && - uip_appdata[6] == ISO_g && - uip_appdata[7] == ISO_i && - uip_appdata[8] == ISO_slash) { - /* If the request is for a file that starts with "/cgi/", we - prepare for invoking a script. */ - hs->script = fsfile.data; - next_scriptstate(); - } else { - hs->script = NULL; - /* The web server is now no longer in the HTTP_NOGET state, but - in the HTTP_FILE state since is has now got the GET from - the client and will start transmitting the file. */ - hs->state = HTTP_FILE; - - /* Point the file pointers in the connection state to point to - the first byte of the file. */ - hs->dataptr = fsfile.data; - hs->count = fsfile.len; - } - } - - - if(hs->state != HTTP_FUNC) { - /* Check if the client (remote end) has acknowledged any data that - we've previously sent. If so, we move the file pointer further - into the file and send back more data. If we are out of data to - send, we close the connection. */ - if(uip_acked()) { - if(hs->count >= uip_conn->len) { - hs->count -= uip_conn->len; - hs->dataptr += uip_conn->len; - } else { - hs->count = 0; - } - - if(hs->count == 0) { - if(hs->script != NULL) { - next_scriptline(); - next_scriptstate(); - } else { - uip_close(); - } - } - } - } else { - /* Call the CGI function. */ - if(cgitab[hs->script[2] - ISO_a](uip_acked())) { - /* If the function returns non-zero, we jump to the next line - in the script. */ - next_scriptline(); - next_scriptstate(); - } - } - - if(hs->state != HTTP_FUNC && !uip_poll()) { - /* Send a piece of data, but not more than the MSS of the - connection. */ - uip_send(( void * ) hs->dataptr, hs->count); - } - - /* Finally, return to uIP. Our outgoing packet will soon be on its - way... */ - return; - - default: - /* Should never happen. */ - uip_abort(); - break; - } -} -/*-----------------------------------------------------------------------------------*/ -/* next_scriptline(): - * - * Reads the script until it finds a newline. */ -static void -next_scriptline(void) -{ - /* Loop until we find a newline character. */ - do { - ++(hs->script); - } while(hs->script[0] != ISO_nl); - - /* Eat up the newline as well. */ - ++(hs->script); -} -/*-----------------------------------------------------------------------------------*/ -/* next_sciptstate: - * - * Reads one line of script and decides what to do next. - */ -static void -next_scriptstate(void) -{ - struct fs_file fsfile; - long i; - - again: - switch(hs->script[0]) { - case ISO_t: - /* Send a text string. */ - hs->state = HTTP_TEXT; - hs->dataptr = &hs->script[2]; - - /* Calculate length of string. */ - for(i = 0; hs->dataptr[i] != ISO_nl; ++i); - hs->count = i; - break; - case ISO_c: - /* Call a function. */ - hs->state = HTTP_FUNC; - hs->dataptr = NULL; - hs->count = 0; - cgitab[hs->script[2] - ISO_a](0); - break; - case ISO_i: - /* Include a file. */ - hs->state = HTTP_FILE; - if(!fs_open(&hs->script[2], &fsfile)) { - uip_abort(); - } - hs->dataptr = fsfile.data; - hs->count = fsfile.len; - break; - case ISO_hash: - /* Comment line. */ - next_scriptline(); - goto again; - case ISO_period: - /* End of script. */ - hs->state = HTTP_END; - uip_close(); - break; - default: - uip_abort(); - break; - } -} -/*-----------------------------------------------------------------------------------*/ -/** @} */ -/** @} */ diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/httpd.c_ b/Demo/uIP_Demo_IAR_ARM7/uip/httpd.c_ deleted file mode 100644 index fda240826..000000000 --- a/Demo/uIP_Demo_IAR_ARM7/uip/httpd.c_ +++ /dev/null @@ -1,380 +0,0 @@ -/*$T httpd.c GC 1.138 07/23/05 13:10:49 */ - -/* - * \addtogroup exampleapps @{ Ł - * \defgroup httpd Web server @{ The uIP web server is a very simplistic - * implementation of an HTTP server. It can serve web pages and files from a - * read-only ROM filesystem, and provides a very small scripting language. The - * script language is very simple and works as follows. Each script line starts - * with a command character, either "i", "t", "c", "#" or ".". The "i" command - * tells the script interpreter to "include" a file from the virtual file system - * and output it to the web browser. The "t" command should be followed by a line - * of text that is to be output to the browser. The "c" command is used to call - * one of the C functions from the httpd-cgi.c file. A line that starts with a "#" - * is ignored (i.e., the "#" denotes a comment), and the "." denotes the last - * script line. The script that produces the file statistics page looks somewhat - * like this: \code i /header.html t

File statistics


t
/index.html c a - * /index.html t
/cgi/files c - * a /cgi/files t
/cgi/tcp c a - * /cgi/tcp t
/404.html c a - * /404.html t
i /footer.plain . \endcode Ł - * \file HTTP server. \author Adam Dunkels Ł - * Copyright (c) 2001, Adam Dunkels. All rights reserved. Redistribution and use - * in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: 1. Redistributions of source - * code must retain the above copyright notice, this list of conditions and the - * following disclaimer. 2. Redistributions in binary form must reproduce the - * above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. 3. The - * name of the author may not be used to endorse or promote products derived from - * this software without specific prior written permission. THIS SOFTWARE IS - * PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * This file is part of the uIP TCP/IP stack. $Id: httpd.c,v 1.28.2.6 2003/10/07 - * 13:22:27 adam Exp $ - */ -#include "uip.h" -#include "httpd.h" -#include "fs.h" -#include "fsdata.h" -#include "cgi.h" - -#define NULL ( void * ) 0 - -/* The HTTP server states: */ -#define HTTP_NOGET 0 -#define HTTP_FILE 1 -#define HTTP_TEXT 2 -#define HTTP_FUNC 3 -#define HTTP_END 4 - -#ifdef DEBUG -#include -#define PRINT( x ) -#define PRINTLN( x ) -#else /* DEBUG */ -#define PRINT( x ) -#define PRINTLN( x ) -#endif /* DEBUG */ - -struct httpd_state *hs; - -extern const struct fsdata_file file_index_html; -extern const struct fsdata_file file_404_html; - -static void next_scriptline( void ); -static void next_scriptstate( void ); - -#define ISO_G 0x47 -#define ISO_E 0x45 -#define ISO_T 0x54 -#define ISO_slash 0x2f -#define ISO_c 0x63 -#define ISO_g 0x67 -#define ISO_i 0x69 -#define ISO_space 0x20 -#define ISO_nl 0x0a -#define ISO_cr 0x0d -#define ISO_a 0x61 -#define ISO_t 0x74 -#define ISO_hash 0x23 -#define ISO_period 0x2e - -#define httpPORT 80 - -/* - ======================================================================================================================= - Initialize the web server. Starts to listen for incoming connection requests on TCP port 80. - ======================================================================================================================= - */ -void httpd_init( void ) -{ - fs_init(); - - /* Listen to port 80. */ - uip_listen( HTONS( httpPORT ) ); -} - -/* - ======================================================================================================================= - ======================================================================================================================= - */ -void httpd_appcall( void ) -{ - /*~~~~~~~~~~~~~~~~~~~*/ - struct fs_file fsfile; - u8_t i; - /*~~~~~~~~~~~~~~~~~~~*/ - - switch( uip_conn->lport ) - { - /* This is the web server: */ - case HTONS( httpPORT ): - /* Pick out the application state from the uip_conn structure. */ - hs = ( struct httpd_state * ) ( uip_conn->appstate ); - - /* - * We use the uip_ test functions to deduce why we were called. If uip_connected() - * is non-zero, we were called because a remote host has connected to us. If - * uip_newdata() is non-zero, we were called because the remote host has sent us - * new data, and if uip_acked() is non-zero, the remote host has acknowledged the - * data we previously sent to it. - */ - if( uip_connected() ) - { - /* - * Since we have just been connected with the remote host, we reset the state for - * this connection. The ->count variable contains the amount of data that is yet - * to be sent to the remote host, and the ->state is set to HTTP_NOGET to signal - * that we haven't received any HTTP GET request for this connection yet. - */ - hs->state = HTTP_NOGET; - hs->count = 0; - return; - } - else if( uip_poll() ) - { - /* - * If we are polled ten times, we abort the connection. This is because we don't - * want connections lingering indefinately in the system. - */ - if( hs->count++ >= 10 ) - { - uip_abort(); - } - - return; - } - else if( uip_newdata() && hs->state == HTTP_NOGET ) - { - /* - * This is the first data we receive, and it should contain a GET. Ł - * Check for GET. - */ - if - ( - uip_appdata[0] != ISO_G - || uip_appdata[1] != ISO_E - || uip_appdata[2] != ISO_T - || uip_appdata[3] != ISO_space - ) - { - /* If it isn't a GET, we abort the connection. */ - uip_abort(); - return; - } - - /* Find the file we are looking for. */ - for( i = 4; i < 40; ++i ) - { - if( uip_appdata[i] == ISO_space || uip_appdata[i] == ISO_cr || uip_appdata[i] == ISO_nl ) - { - uip_appdata[i] = 0; - break; - } - } - - PRINT( "request for file " ); - PRINTLN( &uip_appdata[4] ); - - /* Check for a request for "/". */ - if( uip_appdata[4] == ISO_slash && uip_appdata[5] == 0 ) - { - fs_open( file_index_html.name, &fsfile ); - } - else - { - if( !fs_open( ( const char * ) &uip_appdata[4], &fsfile ) ) - { - PRINTLN( "couldn't open file" ); - fs_open( file_404_html.name, &fsfile ); - } - } - - if - ( - uip_appdata[4] == ISO_slash - && uip_appdata[5] == ISO_c - && uip_appdata[6] == ISO_g - && uip_appdata[7] == ISO_i - && uip_appdata[8] == ISO_slash - ) - { - /* - * If the request is for a file that starts with "/cgi/", we prepare for invoking - * a script. - */ - hs->script = fsfile.data; - next_scriptstate(); - } - else - { - hs->script = NULL; - - /* - * The web server is now no longer in the HTTP_NOGET state, but in the HTTP_FILE - * state since is has now got the GET from the client and will start transmitting - * the file. - */ - hs->state = HTTP_FILE; - - /* - * Point the file pointers in the connection state to point to the first byte of - * the file. - */ - hs->dataptr = fsfile.data; - hs->count = fsfile.len; - } - } - - if( hs->state != HTTP_FUNC ) - { - /* - * Check if the client (remote end) has acknowledged any data that we've - * previously sent. If so, we move the file pointer further into the file and send - * back more data. If we are out of data to send, we close the connection. - */ - if( uip_acked() ) - { - if( hs->count >= uip_conn->len ) - { - hs->count -= uip_conn->len; - hs->dataptr += uip_conn->len; - } - else - { - hs->count = 0; - } - - if( hs->count == 0 ) - { - if( hs->script != NULL ) - { - next_scriptline(); - next_scriptstate(); - } - else - { - uip_close(); - } - } - } - } - else - { - /* Call the CGI function. */ - if( cgitab[hs->script[2] - ISO_a](uip_acked()) ) - { - /* If the function returns non-zero, we jump to the next line in the script. */ - next_scriptline(); - next_scriptstate(); - } - } - - if( hs->state != HTTP_FUNC && !uip_poll() ) - { - /* Send a piece of data, but not more than the MSS of the connection. */ - uip_send( ( void * ) hs->dataptr, hs->count ); - } - - /* Finally, return to uIP. Our outgoing packet will soon be on its way... */ - return; - - default: - /* Should never happen. */ - uip_abort(); - break; - } -} - -/* - ======================================================================================================================= - next_scriptline(): Reads the script until it finds a newline. - ======================================================================================================================= - */ -static void next_scriptline( void ) -{ - /* Loop until we find a newline character. */ - do - { - ++( hs->script ); - } while( hs->script[0] != ISO_nl ); - - /* Eat up the newline as well. */ - ++( hs->script ); -} - -/* - ======================================================================================================================= - next_sciptstate: Reads one line of script and decides what to do next. - ======================================================================================================================= - */ -static void next_scriptstate( void ) -{ - /*~~~~~~~~~~~~~~~~~~~*/ - struct fs_file fsfile; - u8_t i; - /*~~~~~~~~~~~~~~~~~~~*/ - -again: - switch( hs->script[0] ) - { - case ISO_t: - /* Send a text string. */ - hs->state = HTTP_TEXT; - hs->dataptr = &hs->script[2]; - - /* Calculate length of string. */ - for( i = 0; hs->dataptr[i] != ISO_nl; ++i ); - hs->count = i; - break; - - case ISO_c: - /* Call a function. */ - hs->state = HTTP_FUNC; - hs->dataptr = NULL; - hs->count = 0; - cgitab[hs->script[2] - ISO_a]( 0 ); - break; - - case ISO_i: - /* Include a file. */ - hs->state = HTTP_FILE; - if( !fs_open( &hs->script[2], &fsfile ) ) - { - uip_abort(); - } - - hs->dataptr = fsfile.data; - hs->count = fsfile.len; - break; - - case ISO_hash: - /* Comment line. */ - next_scriptline(); - goto again; - - case ISO_period: - /* End of script. */ - hs->state = HTTP_END; - uip_close(); - break; - - default: - uip_abort(); - break; - } -} - -/* - * @} Ł - * @} - */ diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/httpd.h b/Demo/uIP_Demo_IAR_ARM7/uip/httpd.h deleted file mode 100644 index 34d6bb35f..000000000 --- a/Demo/uIP_Demo_IAR_ARM7/uip/httpd.h +++ /dev/null @@ -1,77 +0,0 @@ -/** - * \addtogroup httpd - * @{ - */ - -/** - * \file - * HTTP server header file. - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2001, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: httpd.h,v 1.4.2.3 2003/10/06 22:56:44 adam Exp $ - * - */ - -#ifndef __HTTPD_H__ -#define __HTTPD_H__ - -void httpd_init(void); -void httpd_appcall(void); - -/* UIP_APPCALL: the name of the application function. This function - must return void and take no arguments (i.e., C type "void - appfunc(void)"). */ -#ifndef UIP_APPCALL -#define UIP_APPCALL httpd_appcall -#endif - -struct httpd_state { - u8_t state; - u16_t count; - char *dataptr; - char *script; -}; - - -/* UIP_APPSTATE_SIZE: The size of the application-specific state - stored in the uip_conn structure. */ -#ifndef UIP_APPSTATE_SIZE -#define UIP_APPSTATE_SIZE (sizeof(struct httpd_state)) -#endif - -#define FS_STATISTICS 1 - -extern struct httpd_state *hs; - -#endif /* __HTTPD_H__ */ diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/main_led b/Demo/uIP_Demo_IAR_ARM7/uip/main_led deleted file mode 100644 index 8fe01ea6d..000000000 --- a/Demo/uIP_Demo_IAR_ARM7/uip/main_led +++ /dev/null @@ -1,67 +0,0 @@ -// Copyright (c) 2001-2004 Rowley Associates Limited. -// -// This file may be distributed under the terms of the License Agreement -// provided with this software. -// -// THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE -// WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. -// -//////////////////////////////////////////////////////////////////////////////// -// -// Olimex LPC-P1 LED Example -// -// Description -// ----------- -// This example demonstrates writing to the programmable peripheral interface. -// -//////////////////////////////////////////////////////////////////////////////// - -#include - -#define LED_RED (1<<8) -#define LED_GREEN (1<<10) -#define LED_YELLOW (1<<11) - -#define LED1 LED_YELLOW - -static void -ledInit() -{ - IODIR |= LED1; - IOSET = LED1; -} - -static void -ledOn(void) -{ - IOCLR = LED1; -} - -static void -ledOff(void) -{ - IOSET = LED1; -} - -void -delay(int d) -{ - for(; d; --d); -} - -int -main(void) -{ - MAMCR = 2; - ledInit(); - while (1) - { - ledOn(); - delay(100000); - ledOff(); - delay(100000); - } - return 0; -} - - diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/makefsdata b/Demo/uIP_Demo_IAR_ARM7/uip/makefsdata deleted file mode 100644 index f5f75f174..000000000 --- a/Demo/uIP_Demo_IAR_ARM7/uip/makefsdata +++ /dev/null @@ -1,93 +0,0 @@ -#!/usr/bin/perl - -open(OUTPUT, "> fsdata.c"); - -chdir("fs"); -open(FILES, "find . -type f |"); - -while($file = ) { - - # Do not include files in CVS directories nor backup files. - if($file =~ /(CVS|~)/) { - next; - } - - chop($file); - - open(HEADER, "> /tmp/header") || die $!; - if($file =~ /404.html/) { - print(HEADER "HTTP/1.0 404 File not found\r\n"); - } else { - print(HEADER "HTTP/1.0 200 OK\r\n"); - } - print(HEADER "Server: uIP/0.9 (http://dunkels.com/adam/uip/)\r\n"); - if($file =~ /\.html$/) { - print(HEADER "Content-type: text/html\r\n"); - } elsif($file =~ /\.gif$/) { - print(HEADER "Content-type: image/gif\r\n"); - } elsif($file =~ /\.png$/) { - print(HEADER "Content-type: image/png\r\n"); - } elsif($file =~ /\.jpg$/) { - print(HEADER "Content-type: image/jpeg\r\n"); - } else { - print(HEADER "Content-type: text/plain\r\n"); - } - print(HEADER "\r\n"); - close(HEADER); - - unless($file =~ /\.plain$/ || $file =~ /cgi/) { - system("cat /tmp/header $file > /tmp/file"); - } else { - system("cp $file /tmp/file"); - } - - open(FILE, "/tmp/file"); - unlink("/tmp/file"); - unlink("/tmp/header"); - - $file =~ s/\.//; - $fvar = $file; - $fvar =~ s-/-_-g; - $fvar =~ s-\.-_-g; - print(OUTPUT "static const char data".$fvar."[] = {\n"); - print(OUTPUT "\t/* $file */\n\t"); - for($j = 0; $j < length($file); $j++) { - printf(OUTPUT "%#02x, ", unpack("C", substr($file, $j, 1))); - } - printf(OUTPUT "0,\n"); - - - $i = 0; - while(read(FILE, $data, 1)) { - if($i == 0) { - print(OUTPUT "\t"); - } - printf(OUTPUT "%#02x, ", unpack("C", $data)); - $i++; - if($i == 10) { - print(OUTPUT "\n"); - $i = 0; - } - } - print(OUTPUT "};\n\n"); - close(FILE); - push(@fvars, $fvar); - push(@files, $file); -} - -for($i = 0; $i < @fvars; $i++) { - $file = $files[$i]; - $fvar = $fvars[$i]; - - if($i == 0) { - $prevfile = "NULL"; - } else { - $prevfile = "file" . $fvars[$i - 1]; - } - print(OUTPUT "const struct fsdata_file file".$fvar."[] = {{$prevfile, data$fvar, "); - print(OUTPUT "data$fvar + ". (length($file) + 1) .", "); - print(OUTPUT "sizeof(data$fvar) - ". (length($file) + 1) ."}};\n\n"); -} - -print(OUTPUT "#define FS_ROOT file$fvars[$i - 1]\n\n"); -print(OUTPUT "#define FS_NUMFILES $i"); diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/memb.c b/Demo/uIP_Demo_IAR_ARM7/uip/memb.c deleted file mode 100644 index 56e663446..000000000 --- a/Demo/uIP_Demo_IAR_ARM7/uip/memb.c +++ /dev/null @@ -1,152 +0,0 @@ -/** - * \addtogroup exampleapps - * @{ - */ - -/** - * \file - * Memory block allocation routines. - * \author Adam Dunkels - * - * The memory block allocation routines provide a simple yet powerful - * set of functions for managing a set of memory blocks of fixed - * size. A set of memory blocks is statically declared with the - * MEMB() macro. Memory blocks are allocated from the declared - * memory by the memb_alloc() function, and are deallocated with the - * memb_free() function. - * - * \note Because of namespace clashes only one MEMB() can be - * declared per C module, and the name scope of a MEMB() memory - * block is local to each C module. - * - * The following example shows how to declare and use a memory block - * called "cmem" which has 8 chunks of memory with each memory chunk - * being 20 bytes large. - * - \code - MEMB(cmem, 20, 8); - - int main(int argc, char *argv[]) { - char *ptr; - - memb_init(&cmem); - - ptr = memb_alloc(&cmem); - - if(ptr != NULL) { - do_something(ptr); - } else { - printf("Could not allocate memory.\n"); - } - - if(memb_free(ptr) == 0) { - printf("Deallocation succeeded.\n"); - } - } - \endcode - * - */ - -#include - -#include "memb.h" - -/*------------------------------------------------------------------------------*/ -/** - * Initialize a memory block that was declared with MEMB(). - * - * \param m A memory block previosly declared with MEMB(). - */ -/*------------------------------------------------------------------------------*/ -void -memb_init(struct memb_blocks *m) -{ - memset(m->mem, (m->size + 1) * m->num, 0); -} -/*------------------------------------------------------------------------------*/ -/** - * Allocate a memory block from a block of memory declared with MEMB(). - * - * \param m A memory block previosly declared with MEMB(). - */ -/*------------------------------------------------------------------------------*/ -char * -memb_alloc(struct memb_blocks *m) -{ - int i; - char *ptr; - - ptr = m->mem; - for(i = 0; i < m->num; ++i) { - if(*ptr == 0) { - /* If this block was unused, we increase the reference count to - indicate that it now is used and return a pointer to the - first byte following the reference counter. */ - ++*ptr; - return ptr + 1; - } - ptr += m->size + 1; - } - - /* No free block was found, so we return NULL to indicate failure to - allocate block. */ - return NULL; -} -/*------------------------------------------------------------------------------*/ -/** - * Deallocate a memory block from a memory block previously declared - * with MEMB(). - * - * \param m m A memory block previosly declared with MEMB(). - * - * \param ptr A pointer to the memory block that is to be deallocated. - * - * \return The new reference count for the memory block (should be 0 - * if successfully deallocated) or -1 if the pointer "ptr" did not - * point to a legal memory block. - */ -/*------------------------------------------------------------------------------*/ -char -memb_free(struct memb_blocks *m, char *ptr) -{ - int i; - char *ptr2; - - /* Walk through the list of blocks and try to find the block to - which the pointer "ptr" points to. */ - ptr2 = m->mem; - for(i = 0; i < m->num; ++i) { - - if(ptr2 == ptr - 1) { - /* We've found to block to which "ptr" points so we decrease the - reference count and return the new value of it. */ - return --*ptr2; - } - ptr2 += m->size + 1; - } - return -1; -} -/*------------------------------------------------------------------------------*/ -/** - * Increase the reference count for a memory chunk. - * - * \note No sanity checks are currently made. - * - * \param m m A memory block previosly declared with MEMB(). - * - * \param ptr A pointer to the memory chunk for which the reference - * count should be increased. - * - * \return The new reference count. - */ -/*------------------------------------------------------------------------------*/ -char -memb_ref(struct memb_blocks *m, char *ptr) -{ - return ++*(ptr - 1); -} -/*------------------------------------------------------------------------------*/ - - - - diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/memb.h b/Demo/uIP_Demo_IAR_ARM7/uip/memb.h deleted file mode 100644 index 505846f4d..000000000 --- a/Demo/uIP_Demo_IAR_ARM7/uip/memb.h +++ /dev/null @@ -1,43 +0,0 @@ -/** - * \addtogroup exampleapps - * @{ - */ - -/** - * \file - * Memory block allocation routines. - * \author Adam Dunkels - * - */ - -#ifndef __MEMB_H__ -#define __MEMB_H__ - -/** - * Declare a memory block. - * - * \param name The name of the memory block (later used with - * memb_init(), memb_alloc() and memb_free()). - * - * \param size The size of each memory chunk, in bytes. - * - * \param num The total number of memory chunks in the block. - * - */ -#define MEMB(name, size, num) \ - static char memb_mem[(size + 1) * num]; \ - static struct memb_blocks name = {size, num, memb_mem} - -struct memb_blocks { - unsigned short size; - unsigned short num; - char *mem; -}; - -void memb_init(struct memb_blocks *m); -char *memb_alloc(struct memb_blocks *m); -char memb_ref(struct memb_blocks *m, char *ptr); -char memb_free(struct memb_blocks *m, char *ptr); - - -#endif /* __MEMB_H__ */ diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/setarp.bat b/Demo/uIP_Demo_IAR_ARM7/uip/setarp.bat deleted file mode 100644 index 7f5babb3f..000000000 --- a/Demo/uIP_Demo_IAR_ARM7/uip/setarp.bat +++ /dev/null @@ -1 +0,0 @@ -arp -s 172.25.218.210 00-bd-3b-33-05-72 diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/slipdev.c b/Demo/uIP_Demo_IAR_ARM7/uip/slipdev.c deleted file mode 100644 index fc968c82e..000000000 --- a/Demo/uIP_Demo_IAR_ARM7/uip/slipdev.c +++ /dev/null @@ -1,202 +0,0 @@ -/** - * \addtogroup uip - * @{ - */ - -/** - * \defgroup slip Serial Line IP (SLIP) protocol - * @{ - * - * The SLIP protocol is a very simple way to transmit IP packets over - * a serial line. It does not provide any framing or error control, - * and is therefore not very widely used today. - * - * This SLIP implementation requires two functions for accessing the - * serial device: slipdev_char_poll() and slipdev_char_put(). These - * must be implemented specifically for the system on which the SLIP - * protocol is to be run. - */ - -/** - * \file - * SLIP protocol implementation - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2001, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: slipdev.c,v 1.1.2.3 2003/10/07 13:23:01 adam Exp $ - * - */ - -/* - * This is a generic implementation of the SLIP protocol over an RS232 - * (serial) device. - * - * Huge thanks to Ullrich von Bassewitz of cc65 fame for - * and endless supply of bugfixes, insightsful comments and - * suggestions, and improvements to this code! - */ - -#include "uip.h" - -#define SLIP_END 0300 -#define SLIP_ESC 0333 -#define SLIP_ESC_END 0334 -#define SLIP_ESC_ESC 0335 - -static u8_t slip_buf[UIP_BUFSIZE]; - -static u16_t len, tmplen; -static u8_t lastc; - -/*-----------------------------------------------------------------------------------*/ -/** - * Send the packet in the uip_buf and uip_appdata buffers using the - * SLIP protocol. - * - * The first 40 bytes of the packet (the IP and TCP headers) are read - * from the uip_buf buffer, and the following bytes (the application - * data) are read from the uip_appdata buffer. - * - */ -/*-----------------------------------------------------------------------------------*/ -void -slipdev_send(void) -{ - u16_t i; - u8_t *ptr; - u8_t c; - - slipdev_char_put(SLIP_END); - - ptr = uip_buf; - for(i = 0; i < uip_len; ++i) { - if(i == 40) { - ptr = (u8_t *)uip_appdata; - } - c = *ptr++; - switch(c) { - case SLIP_END: - slipdev_char_put(SLIP_ESC); - slipdev_char_put(SLIP_ESC_END); - break; - case SLIP_ESC: - slipdev_char_put(SLIP_ESC); - slipdev_char_put(SLIP_ESC_ESC); - break; - default: - slipdev_char_put(c); - break; - } - } - slipdev_char_put(SLIP_END); -} -/*-----------------------------------------------------------------------------------*/ -/** - * Poll the SLIP device for an available packet. - * - * This function will poll the SLIP device to see if a packet is - * available. It uses a buffer in which all avaliable bytes from the - * RS232 interface are read into. When a full packet has been read - * into the buffer, the packet is copied into the uip_buf buffer and - * the length of the packet is returned. - * - * \return The length of the packet placed in the uip_buf buffer, or - * zero if no packet is available. - */ -/*-----------------------------------------------------------------------------------*/ -u16_t -slipdev_poll(void) -{ - u8_t c; - - while(slipdev_char_poll(c)) { - switch(c) { - case SLIP_ESC: - lastc = c; - break; - - case SLIP_END: - lastc = c; - /* End marker found, we copy our input buffer to the uip_buf - buffer and return the size of the packet we copied. */ - memcpy(uip_buf, slip_buf, len); - tmplen = len; - len = 0; - return tmplen; - - default: - if(lastc == SLIP_ESC) { - lastc = c; - /* Previous read byte was an escape byte, so this byte will be - interpreted differently from others. */ - switch(c) { - case SLIP_ESC_END: - c = SLIP_END; - break; - case SLIP_ESC_ESC: - c = SLIP_ESC; - break; - } - } else { - lastc = c; - } - - slip_buf[len] = c; - ++len; - - if(len > UIP_BUFSIZE) { - len = 0; - } - - break; - } - } - return 0; -} -/*-----------------------------------------------------------------------------------*/ -/** - * Initialize the SLIP module. - * - * This function does not initialize the underlying RS232 device, but - * only the SLIP part. - */ -/*-----------------------------------------------------------------------------------*/ -void -slipdev_init(void) -{ - lastc = len = 0; -} -/*-----------------------------------------------------------------------------------*/ - -/** @} */ -/** @} */ diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/slipdev.h b/Demo/uIP_Demo_IAR_ARM7/uip/slipdev.h deleted file mode 100644 index 3fbfe2d2d..000000000 --- a/Demo/uIP_Demo_IAR_ARM7/uip/slipdev.h +++ /dev/null @@ -1,88 +0,0 @@ -/** - * \addtogroup slip - * @{ - */ - -/** - * \file - * SLIP header file. - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2001, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: slipdev.h,v 1.1.2.3 2003/10/06 22:42:51 adam Exp $ - * - */ - -#ifndef __SLIPDEV_H__ -#define __SLIPDEV_H__ - -#include "uip.h" - -/** - * Put a character on the serial device. - * - * This function is used by the SLIP implementation to put a character - * on the serial device. It must be implemented specifically for the - * system on which the SLIP implementation is to be run. - * - * \param c The character to be put on the serial device. - */ -void slipdev_char_put(u8_t c); - -/** - * Poll the serial device for a character. - * - * This function is used by the SLIP implementation to poll the serial - * device for a character. It must be implemented specifically for the - * system on which the SLIP implementation is to be run. - * - * The function should return immediately regardless if a character is - * available or not. If a character is available it should be placed - * at the memory location pointed to by the pointer supplied by the - * arguement c. - * - * \param c A pointer to a byte that is filled in by the function with - * the received character, if available. - * - * \retval 0 If no character is available. - * \retval Non-zero If a character is available. - */ -u8_t slipdev_char_poll(u8_t *c); - -void slipdev_init(void); -void slipdev_send(void); -u16_t slipdev_poll(void); - -#endif /* __SLIPDEV_H__ */ - -/** @} */ diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/tapdev.c b/Demo/uIP_Demo_IAR_ARM7/uip/tapdev.c deleted file mode 100644 index 0d23fc4d9..000000000 --- a/Demo/uIP_Demo_IAR_ARM7/uip/tapdev.c +++ /dev/null @@ -1,171 +0,0 @@ -/* - * Copyright (c) 2001, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * Author: Adam Dunkels - * - * $Id: tapdev.c,v 1.7.2.1 2003/10/07 13:23:19 adam Exp $ - */ - - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef linux -#include -#include -#include -#define DEVTAP "/dev/net/tun" -#else /* linux */ -#define DEVTAP "/dev/tap0" -#endif /* linux */ - -#include "uip.h" - -static int fd; - -static unsigned long lasttime; -static struct timezone tz; - -/*-----------------------------------------------------------------------------------*/ -void -tapdev_init(void) -{ - char buf[1024]; - - fd = open(DEVTAP, O_RDWR); - if(fd == -1) { - perror("tapdev: tapdev_init: open"); - exit(1); - } - -#ifdef linux - { - struct ifreq ifr; - memset(&ifr, 0, sizeof(ifr)); - ifr.ifr_flags = IFF_TAP|IFF_NO_PI; - if (ioctl(fd, TUNSETIFF, (void *) &ifr) < 0) { - perror(buf); - exit(1); - } - } -#endif /* Linux */ - - snprintf(buf, sizeof(buf), "ifconfig tap0 inet %d.%d.%d.%d", - UIP_DRIPADDR0, UIP_DRIPADDR1, UIP_DRIPADDR2, UIP_DRIPADDR3); - system(buf); - - lasttime = 0; -} -/*-----------------------------------------------------------------------------------*/ -unsigned int -tapdev_read(void) -{ - fd_set fdset; - struct timeval tv, now; - int ret; - - if(lasttime >= 500000) { - lasttime = 0; - return 0; - } - - tv.tv_sec = 0; - tv.tv_usec = 500000 - lasttime; - - - FD_ZERO(&fdset); - FD_SET(fd, &fdset); - - gettimeofday(&now, &tz); - ret = select(fd + 1, &fdset, NULL, NULL, &tv); - if(ret == 0) { - lasttime = 0; - return 0; - } - ret = read(fd, uip_buf, UIP_BUFSIZE); - if(ret == -1) { - perror("tap_dev: tapdev_read: read"); - } - gettimeofday(&tv, &tz); - lasttime += (tv.tv_sec - now.tv_sec) * 1000000 + (tv.tv_usec - now.tv_usec); - - return ret; -} -/*-----------------------------------------------------------------------------------*/ -void -tapdev_send(void) -{ - int ret; - struct iovec iov[2]; - -#ifdef linux - { - char tmpbuf[UIP_BUFSIZE]; - int i; - - for(i = 0; i < 40 + UIP_LLH_LEN; i++) { - tmpbuf[i] = uip_buf[i]; - } - - for(; i < uip_len; i++) { - tmpbuf[i] = uip_appdata[i - 40 - UIP_LLH_LEN]; - } - - ret = write(fd, tmpbuf, uip_len); - } -#else - - if(uip_len < 40 + UIP_LLH_LEN) { - ret = write(fd, uip_buf, uip_len + UIP_LLH_LEN); - } else { - iov[0].iov_base = uip_buf; - iov[0].iov_len = 40 + UIP_LLH_LEN; - iov[1].iov_base = (char *)uip_appdata; - iov[1].iov_len = uip_len - (40 + UIP_LLH_LEN); - - ret = writev(fd, iov, 2); - } -#endif - if(ret == -1) { - perror("tap_dev: tapdev_send: writev"); - exit(1); - } -} -/*-----------------------------------------------------------------------------------*/ diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/tapdev.h b/Demo/uIP_Demo_IAR_ARM7/uip/tapdev.h deleted file mode 100644 index 66f1a4a71..000000000 --- a/Demo/uIP_Demo_IAR_ARM7/uip/tapdev.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (c) 2001, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: tapdev.h,v 1.1.2.1 2003/10/04 22:54:17 adam Exp $ - * - */ - -#ifndef __TAPDEV_H__ -#define __TAPDEV_H__ - -void tapdev_init(void); -unsigned int tapdev_read(void); -void tapdev_send(void); - -#endif /* __TAPDEV_H__ */ diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/telnetd-shell.c b/Demo/uIP_Demo_IAR_ARM7/uip/telnetd-shell.c deleted file mode 100644 index 7dff714ca..000000000 --- a/Demo/uIP_Demo_IAR_ARM7/uip/telnetd-shell.c +++ /dev/null @@ -1,181 +0,0 @@ -/** - * \addtogroup telnetd - * @{ - */ - -/** - * \file - * An example telnet server shell - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2003, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the Contiki desktop OS. - * - * $Id: telnetd-shell.c,v 1.1.2.1 2003/10/06 22:56:22 adam Exp $ - * - */ - -#include "uip.h" -#include "telnetd.h" -#include - -struct ptentry { - char c; - void (* pfunc)(struct telnetd_state *s, char *str); -}; - -/*-----------------------------------------------------------------------------------*/ -static void -parse(struct telnetd_state *s, register char *str, struct ptentry *t) -{ - register struct ptentry *p; - char *sstr; - - sstr = str; - - /* Loop over the parse table entries in t in order to find one that - matches the first character in str. */ - for(p = t; p->c != 0; ++p) { - if(*str == p->c) { - /* Skip rest of the characters up to the first space. */ - while(*str != ' ') { - ++str; - } - - /* Skip all spaces.*/ - while(*str == ' ') { - ++str; - } - - /* Call parse table entry function and return. */ - p->pfunc(s, str); - return; - } - } - - /* Did not find matching entry in parse table. We just call the - default handler supplied by the caller and return. */ - p->pfunc(s, str); -} -/*-----------------------------------------------------------------------------------*/ -static void -exitt(struct telnetd_state *s, char *str) -{ - telnetd_close(s); -} -/*-----------------------------------------------------------------------------------*/ -static void -inttostr(register char *str, unsigned int i) -{ - str[0] = '0' + i / 100; - if(str[0] == '0') { - str[0] = ' '; - } - str[1] = '0' + (i / 10) % 10; - if(str[1] == '0') { - str[1] = ' '; - } - str[2] = '0' + i % 10; - str[3] = ' '; - str[4] = 0; -} -/*-----------------------------------------------------------------------------------*/ -static void -stats(struct telnetd_state *s, char *strr) -{ - char str[10]; - - inttostr(str, uip_stat.ip.recv); - telnetd_output(s, "IP packets received ", str); - inttostr(str, uip_stat.ip.sent); - telnetd_output(s, "IP packets sent ", str); - inttostr(str, uip_stat.ip.drop); - telnetd_output(s, "IP packets dropped ", str); - - inttostr(str, uip_stat.icmp.recv); - telnetd_output(s, "ICMP packets received ", str); - inttostr(str, uip_stat.icmp.sent); - telnetd_output(s, "ICMP packets sent ", str); - inttostr(str, uip_stat.icmp.drop); - telnetd_output(s, "ICMP packets dropped ", str); - - inttostr(str, uip_stat.tcp.recv); - telnetd_output(s, "TCP packets received ", str); - inttostr(str, uip_stat.tcp.sent); - telnetd_output(s, "TCP packets sent ", str); - inttostr(str, uip_stat.tcp.drop); - telnetd_output(s, "TCP packets dropped ", str); - inttostr(str, uip_stat.tcp.rexmit); - telnetd_output(s, "TCP packets retransmitted ", str); - inttostr(str, uip_stat.tcp.synrst); - telnetd_output(s, "TCP connection attempts ", str); -} -/*-----------------------------------------------------------------------------------*/ -static void -help(struct telnetd_state *s, char *str) -{ - telnetd_output(s, "Available commands:", ""); - telnetd_output(s, "stats - show uIP statistics", ""); - telnetd_output(s, "exit - exit shell", ""); - telnetd_output(s, "? - show this help", ""); -} -/*-----------------------------------------------------------------------------------*/ -static void -none(struct telnetd_state *s, char *str) -{ - if(strlen(str) > 0) { - telnetd_output(s, "Unknown command", ""); - } -} -/*-----------------------------------------------------------------------------------*/ -static struct ptentry configparsetab[] = - {{'s', stats}, - {'e', exitt}, - {'?', help}, - - /* Default action */ - {0, none}}; -/*-----------------------------------------------------------------------------------*/ -void -telnetd_connected(struct telnetd_state *s) -{ - telnetd_output(s, "uIP command shell", ""); - telnetd_output(s, "Type '?' for help", ""); - telnetd_prompt(s, "uIP-0.9> "); -} -/*-----------------------------------------------------------------------------------*/ -void -telnetd_input(struct telnetd_state *s, char *cmd) -{ - parse(s, cmd, configparsetab); - telnetd_prompt(s, "uIP-0.9> "); -} -/*-----------------------------------------------------------------------------------*/ diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/telnetd.c b/Demo/uIP_Demo_IAR_ARM7/uip/telnetd.c deleted file mode 100644 index dba522271..000000000 --- a/Demo/uIP_Demo_IAR_ARM7/uip/telnetd.c +++ /dev/null @@ -1,392 +0,0 @@ -/** - * \addtogroup exampleapps - * @{ - */ - -/** - * \defgroup telnetd Telnet server - * @{ - * - * The uIP telnet server provides a command based interface to uIP. It - * allows using the "telnet" application to access uIP, and implements - * the required telnet option negotiation. - * - * The code is structured in a way which makes it possible to add - * commands without having to rewrite the main telnet code. The main - * telnet code calls two callback functions, telnetd_connected() and - * telnetd_input(), when a telnet connection has been established and - * when a line of text arrives on a telnet connection. These two - * functions can be implemented in a way which suits the particular - * application or environment in which the uIP system is intended to - * be run. - * - * The uIP distribution contains an example telnet shell - * implementation that provides a basic set of commands. - */ - -/** - * \file - * Implementation of the Telnet server. - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2003, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: telnetd.c,v 1.1.2.2 2003/10/07 13:47:50 adam Exp $ - * - */ - -#include "uip.h" -#include "memb.h" -#include "telnetd.h" -#include - -#define ISO_nl 0x0a -#define ISO_cr 0x0d - -MEMB(linemem, TELNETD_LINELEN, TELNETD_NUMLINES); - -static u8_t i; - -#define STATE_NORMAL 0 -#define STATE_IAC 1 -#define STATE_WILL 2 -#define STATE_WONT 3 -#define STATE_DO 4 -#define STATE_DONT 5 -#define STATE_CLOSE 6 - -#define TELNET_IAC 255 -#define TELNET_WILL 251 -#define TELNET_WONT 252 -#define TELNET_DO 253 -#define TELNET_DONT 254 -/*-----------------------------------------------------------------------------------*/ -static char * -alloc_line(void) -{ - return memb_alloc(&linemem); -} -/*-----------------------------------------------------------------------------------*/ -static void -dealloc_line(char *line) -{ - memb_free(&linemem, line); -} -/*-----------------------------------------------------------------------------------*/ -static void -sendline(struct telnetd_state *s, char *line) -{ - static unsigned int i; - for(i = 0; i < TELNETD_NUMLINES; ++i) { - if(s->lines[i] == NULL) { - s->lines[i] = line; - break; - } - } - if(i == TELNETD_NUMLINES) { - dealloc_line(line); - } -} -/*-----------------------------------------------------------------------------------*/ -/** - * Close a telnet session. - * - * This function can be called from a telnet command in order to close - * the connection. - * - * \param s The connection which is to be closed. - * - */ -/*-----------------------------------------------------------------------------------*/ -void -telnetd_close(struct telnetd_state *s) -{ - s->state = STATE_CLOSE; -} -/*-----------------------------------------------------------------------------------*/ -/** - * Print a prompt on a telnet connection. - * - * This function can be called by the telnet command shell in order to - * print out a command prompt. - * - * \param s A telnet connection. - * - * \param str The command prompt. - * - */ -/*-----------------------------------------------------------------------------------*/ -void -telnetd_prompt(struct telnetd_state *s, char *str) -{ - char *line; - line = alloc_line(); - if(line != NULL) { - strncpy(line, str, TELNETD_LINELEN); - sendline(s, line); - } -} -/*-----------------------------------------------------------------------------------*/ -/** - * Print out a string on a telnet connection. - * - * This function can be called from a telnet command parser in order - * to print out a string of text on the connection. The two strings - * given as arguments to the function will be concatenated, a carrige - * return and a new line character will be added, and the line is - * sent. - * - * \param s The telnet connection. - * - * \param str1 The first string. - * - * \param str2 The second string. - * - */ -/*-----------------------------------------------------------------------------------*/ -void -telnetd_output(struct telnetd_state *s, char *str1, char *str2) -{ - static unsigned len; - char *line; - - line = alloc_line(); - if(line != NULL) { - len = strlen(str1); - strncpy(line, str1, TELNETD_LINELEN); - if(len < TELNETD_LINELEN) { - strncpy(line + len, str2, TELNETD_LINELEN - len); - } - len = strlen(line); - if(len < TELNETD_LINELEN - 2) { - line[len] = ISO_cr; - line[len+1] = ISO_nl; - line[len+2] = 0; - } - sendline(s, line); - } -} -/*-----------------------------------------------------------------------------------*/ -/** - * Initialize the telnet server. - * - * This function will perform the necessary initializations and start - * listening on TCP port 23. - */ -/*-----------------------------------------------------------------------------------*/ -void -telnetd_init(void) -{ - memb_init(&linemem); - uip_listen(HTONS(23)); -} -/*-----------------------------------------------------------------------------------*/ -static void -acked(struct telnetd_state *s) -{ - dealloc_line(s->lines[0]); - for(i = 1; i < TELNETD_NUMLINES; ++i) { - s->lines[i - 1] = s->lines[i]; - } -} -/*-----------------------------------------------------------------------------------*/ -static void -senddata(struct telnetd_state *s) -{ - if(s->lines[0] != NULL) { - uip_send(s->lines[0], strlen(s->lines[0])); - } -} -/*-----------------------------------------------------------------------------------*/ -static void -getchar(struct telnetd_state *s, u8_t c) -{ - if(c == ISO_cr) { - return; - } - - s->buf[(int)s->bufptr] = c; - if(s->buf[(int)s->bufptr] == ISO_nl || - s->bufptr == sizeof(s->buf) - 1) { - if(s->bufptr > 0) { - s->buf[(int)s->bufptr] = 0; - } - telnetd_input(s, s->buf); - s->bufptr = 0; - } else { - ++s->bufptr; - } -} -/*-----------------------------------------------------------------------------------*/ -static void -sendopt(struct telnetd_state *s, u8_t option, u8_t value) -{ - char *line; - line = alloc_line(); - if(line != NULL) { - line[0] = TELNET_IAC; - line[1] = option; - line[2] = value; - line[3] = 0; - sendline(s, line); - } -} -/*-----------------------------------------------------------------------------------*/ -static void -newdata(struct telnetd_state *s) -{ - u16_t len; - u8_t c; - - - len = uip_datalen(); - - while(len > 0 && s->bufptr < sizeof(s->buf)) { - c = *uip_appdata; - ++uip_appdata; - --len; - switch(s->state) { - case STATE_IAC: - if(c == TELNET_IAC) { - getchar(s, c); - s->state = STATE_NORMAL; - } else { - switch(c) { - case TELNET_WILL: - s->state = STATE_WILL; - break; - case TELNET_WONT: - s->state = STATE_WONT; - break; - case TELNET_DO: - s->state = STATE_DO; - break; - case TELNET_DONT: - s->state = STATE_DONT; - break; - default: - s->state = STATE_NORMAL; - break; - } - } - break; - case STATE_WILL: - /* Reply with a DONT */ - sendopt(s, TELNET_DONT, c); - s->state = STATE_NORMAL; - break; - - case STATE_WONT: - /* Reply with a DONT */ - sendopt(s, TELNET_DONT, c); - s->state = STATE_NORMAL; - break; - case STATE_DO: - /* Reply with a WONT */ - sendopt(s, TELNET_WONT, c); - s->state = STATE_NORMAL; - break; - case STATE_DONT: - /* Reply with a WONT */ - sendopt(s, TELNET_WONT, c); - s->state = STATE_NORMAL; - break; - case STATE_NORMAL: - if(c == TELNET_IAC) { - s->state = STATE_IAC; - } else { - getchar(s, c); - } - break; - } - - - } - -} -/*-----------------------------------------------------------------------------------*/ -void -telnetd_app(void) -{ - struct telnetd_state *s; - - s = (struct telnetd_state *)uip_conn->appstate; - - if(uip_connected()) { - - for(i = 0; i < TELNETD_NUMLINES; ++i) { - s->lines[i] = NULL; - } - s->bufptr = 0; - s->state = STATE_NORMAL; - - telnetd_connected(s); - senddata(s); - return; - } - - if(s->state == STATE_CLOSE) { - s->state = STATE_NORMAL; - uip_close(); - return; - } - - if(uip_closed()) { - telnetd_output(s, "Connection closed", ""); - } - - - if(uip_aborted()) { - telnetd_output(s, "Connection reset", ""); - } - - if(uip_timedout()) { - telnetd_output(s, "Connection timed out", ""); - } - - if(uip_acked()) { - acked(s); - } - - if(uip_newdata()) { - newdata(s); - } - - if(uip_rexmit() || - uip_newdata() || - uip_acked()) { - senddata(s); - } else if(uip_poll()) { - senddata(s); - } -} -/*-----------------------------------------------------------------------------------*/ diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/telnetd.h b/Demo/uIP_Demo_IAR_ARM7/uip/telnetd.h deleted file mode 100644 index 254e44ff1..000000000 --- a/Demo/uIP_Demo_IAR_ARM7/uip/telnetd.h +++ /dev/null @@ -1,114 +0,0 @@ -/** - * \addtogroup telnetd - * @{ - */ - -/** - * \file - * Header file for the telnet server. - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2002, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: telnetd.h,v 1.1.2.2 2003/10/07 13:22:27 adam Exp $ - * - */ -#ifndef __TELNETD_H__ -#define __TELNETD_H__ - -#include "uip.h" - -/** - * The maximum length of a telnet line. - * - * \hideinitializer - */ -#define TELNETD_LINELEN 36 - -/** - * The number of output lines being buffered for all telnet - * connections. - * - * \hideinitializer - */ -#define TELNETD_NUMLINES 2 - -/** - * A telnet connection structure. - */ -struct telnetd_state { - char *lines[TELNETD_NUMLINES]; - char buf[TELNETD_LINELEN]; - char bufptr; - u8_t state; -}; - - -/** - * Callback function that is called when a telnet connection has been - * established. - * - * \param s The telnet connection. - */ -void telnetd_connected(struct telnetd_state *s); - -/** - * Callback function that is called when a line of text has arrived on - * a telnet connection. - * - * \param s The telnet connection. - * - * \param cmd The line of text. - */ -void telnetd_input(struct telnetd_state *s, char *cmd); - - -void telnetd_close(struct telnetd_state *s); -void telnetd_output(struct telnetd_state *s, char *s1, char *s2); -void telnetd_prompt(struct telnetd_state *s, char *str); - -void telnetd_app(void); - -#ifndef UIP_APPCALL -#define UIP_APPCALL telnetd_app -#endif - -#ifndef UIP_APPSTATE_SIZE -#define UIP_APPSTATE_SIZE (sizeof(struct telnetd_state)) -#endif - -void telnetd_init(void); - - -#endif /* __TELNET_H__ */ - -/** @} */ diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/uip.c b/Demo/uIP_Demo_IAR_ARM7/uip/uip.c deleted file mode 100644 index 37f64facc..000000000 --- a/Demo/uIP_Demo_IAR_ARM7/uip/uip.c +++ /dev/null @@ -1,1514 +0,0 @@ -/** - * \addtogroup uip - * @{ - */ - -/** - * \file - * The uIP TCP/IP stack code. - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2001-2003, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: uip.c,v 1.62.2.10 2003/10/07 13:23:01 adam Exp $ - * - */ - -/* -This is a small implementation of the IP and TCP protocols (as well as -some basic ICMP stuff). The implementation couples the IP, TCP and the -application layers very tightly. To keep the size of the compiled code -down, this code also features heavy usage of the goto statement. - -The principle is that we have a small buffer, called the uip_buf, in -which the device driver puts an incoming packet. The TCP/IP stack -parses the headers in the packet, and calls upon the application. If -the remote host has sent data to the application, this data is present -in the uip_buf and the application read the data from there. It is up -to the application to put this data into a byte stream if needed. The -application will not be fed with data that is out of sequence. - -If the application whishes to send data to the peer, it should put its -data into the uip_buf, 40 bytes from the start of the buffer. The -TCP/IP stack will calculate the checksums, and fill in the necessary -header fields and finally send the packet back to the peer. -*/ - -#include "uip.h" -#include "uipopt.h" -#include "uip_arch.h" - -/*-----------------------------------------------------------------------------------*/ -/* Variable definitions. */ - - -/* The IP address of this host. If it is defined to be fixed (by setting UIP_FIXEDADDR to 1 in uipopt.h), the address is set here. Otherwise, the address */ -#if UIP_FIXEDADDR > 0 -const u16_t uip_hostaddr[2] = - {HTONS((UIP_IPADDR0 << 8) | UIP_IPADDR1), - HTONS((UIP_IPADDR2 << 8) | UIP_IPADDR3)}; -const u16_t uip_arp_draddr[2] = - {HTONS((UIP_DRIPADDR0 << 8) | UIP_DRIPADDR1), - HTONS((UIP_DRIPADDR2 << 8) | UIP_DRIPADDR3)}; -const u16_t uip_arp_netmask[2] = - {HTONS((UIP_NETMASK0 << 8) | UIP_NETMASK1), - HTONS((UIP_NETMASK2 << 8) | UIP_NETMASK3)}; -#else -u16_t uip_hostaddr[2]; -u16_t uip_arp_draddr[2], uip_arp_netmask[2]; -#endif /* UIP_FIXEDADDR */ - -u8_t uip_buf[UIP_BUFSIZE+2]; /* The packet buffer that contains - incoming packets. */ -volatile u8_t *uip_appdata; /* The uip_appdata pointer points to - application data. */ -volatile u8_t *uip_sappdata; /* The uip_appdata pointer points to the - application data which is to be sent. */ -#if UIP_URGDATA > 0 -volatile u8_t *uip_urgdata; /* The uip_urgdata pointer points to - urgent data (out-of-band data), if - present. */ -volatile u8_t uip_urglen, uip_surglen; -#endif /* UIP_URGDATA > 0 */ - -volatile u16_t uip_len, uip_slen; - /* The uip_len is either 8 or 16 bits, - depending on the maximum packet - size. */ - -volatile u8_t uip_flags; /* The uip_flags variable is used for - communication between the TCP/IP stack - and the application program. */ -struct uip_conn *uip_conn; /* uip_conn always points to the current - connection. */ - -struct uip_conn uip_conns[UIP_CONNS]; - /* The uip_conns array holds all TCP - connections. */ -u16_t uip_listenports[UIP_LISTENPORTS]; - /* The uip_listenports list all currently - listning ports. */ -#if UIP_UDP -struct uip_udp_conn *uip_udp_conn; -struct uip_udp_conn uip_udp_conns[UIP_UDP_CONNS]; -#endif /* UIP_UDP */ - - -static u16_t ipid; /* Ths ipid variable is an increasing - number that is used for the IP ID - field. */ - -static u8_t iss[4]; /* The iss variable is used for the TCP - initial sequence number. */ - -#if UIP_ACTIVE_OPEN -static u16_t lastport; /* Keeps track of the last port used for - a new connection. */ -#endif /* UIP_ACTIVE_OPEN */ - -/* Temporary variables. */ -volatile u8_t uip_acc32[4]; -static u8_t c, opt; -static u16_t tmp16; - -/* Structures and definitions. */ -#define TCP_FIN 0x01 -#define TCP_SYN 0x02 -#define TCP_RST 0x04 -#define TCP_PSH 0x08 -#define TCP_ACK 0x10 -#define TCP_URG 0x20 -#define TCP_CTL 0x3f - -#define ICMP_ECHO_REPLY 0 -#define ICMP_ECHO 8 - -/* Macros. */ -#define BUF ((uip_tcpip_hdr *)&uip_buf[UIP_LLH_LEN]) -#define FBUF ((uip_tcpip_hdr *)&uip_reassbuf[0]) -#define ICMPBUF ((uip_icmpip_hdr *)&uip_buf[UIP_LLH_LEN]) -#define UDPBUF ((uip_udpip_hdr *)&uip_buf[UIP_LLH_LEN]) - -#if UIP_STATISTICS == 1 -struct uip_stats uip_stat; -#define UIP_STAT(s) s -#else -#define UIP_STAT(s) -#endif /* UIP_STATISTICS == 1 */ - -#if UIP_LOGGING == 1 -#include -void uip_log(char *msg); -#define UIP_LOG(m) uip_log(m) -#else -#define UIP_LOG(m) -#endif /* UIP_LOGGING == 1 */ - -/*-----------------------------------------------------------------------------------*/ -void -uip_init(void) -{ - for(c = 0; c < UIP_LISTENPORTS; ++c) { - uip_listenports[c] = 0; - } - for(c = 0; c < UIP_CONNS; ++c) { - uip_conns[c].tcpstateflags = CLOSED; - } -#if UIP_ACTIVE_OPEN - lastport = 1024; -#endif /* UIP_ACTIVE_OPEN */ - -#if UIP_UDP - for(c = 0; c < UIP_UDP_CONNS; ++c) { - uip_udp_conns[c].lport = 0; - } -#endif /* UIP_UDP */ - - - /* IPv4 initialization. */ -#if UIP_FIXEDADDR == 0 - uip_hostaddr[0] = uip_hostaddr[1] = 0; -#endif /* UIP_FIXEDADDR */ - -} -/*-----------------------------------------------------------------------------------*/ -#if UIP_ACTIVE_OPEN -struct uip_conn * -uip_connect(u16_t *ripaddr, u16_t rport) -{ - register struct uip_conn *conn, *cconn; - - /* Find an unused local port. */ - again: - ++lastport; - - if(lastport >= 32000) { - lastport = 4096; - } - - /* Check if this port is already in use, and if so try to find - another one. */ - for(c = 0; c < UIP_CONNS; ++c) { - conn = &uip_conns[c]; - if(conn->tcpstateflags != CLOSED && - conn->lport == htons(lastport)) { - goto again; - } - } - - - conn = 0; - for(c = 0; c < UIP_CONNS; ++c) { - cconn = &uip_conns[c]; - if(cconn->tcpstateflags == CLOSED) { - conn = cconn; - break; - } - if(cconn->tcpstateflags == TIME_WAIT) { - if(conn == 0 || - cconn->timer > uip_conn->timer) { - conn = cconn; - } - } - } - - if(conn == 0) { - return 0; - } - - conn->tcpstateflags = SYN_SENT; - - conn->snd_nxt[0] = iss[0]; - conn->snd_nxt[1] = iss[1]; - conn->snd_nxt[2] = iss[2]; - conn->snd_nxt[3] = iss[3]; - - conn->initialmss = conn->mss = UIP_TCP_MSS; - - conn->len = 1; /* TCP length of the SYN is one. */ - conn->nrtx = 0; - conn->timer = 1; /* Send the SYN next time around. */ - conn->rto = UIP_RTO; - conn->sa = 0; - conn->sv = 16; - conn->lport = htons(lastport); - conn->rport = rport; - conn->ripaddr[0] = ripaddr[0]; - conn->ripaddr[1] = ripaddr[1]; - - return conn; -} -#endif /* UIP_ACTIVE_OPEN */ -/*-----------------------------------------------------------------------------------*/ -#if UIP_UDP -struct uip_udp_conn * -uip_udp_new(u16_t *ripaddr, u16_t rport) -{ - register struct uip_udp_conn *conn; - - /* Find an unused local port. */ - again: - ++lastport; - - if(lastport >= 32000) { - lastport = 4096; - } - - for(c = 0; c < UIP_UDP_CONNS; ++c) { - if(uip_udp_conns[c].lport == lastport) { - goto again; - } - } - - - conn = 0; - for(c = 0; c < UIP_UDP_CONNS; ++c) { - if(uip_udp_conns[c].lport == 0) { - conn = &uip_udp_conns[c]; - break; - } - } - - if(conn == 0) { - return 0; - } - - conn->lport = HTONS(lastport); - conn->rport = HTONS(rport); - conn->ripaddr[0] = ripaddr[0]; - conn->ripaddr[1] = ripaddr[1]; - - return conn; -} -#endif /* UIP_UDP */ -/*-----------------------------------------------------------------------------------*/ -void -uip_unlisten(u16_t port) -{ - for(c = 0; c < UIP_LISTENPORTS; ++c) { - if(uip_listenports[c] == port) { - uip_listenports[c] = 0; - return; - } - } -} -/*-----------------------------------------------------------------------------------*/ -void -uip_listen(u16_t port) -{ - for(c = 0; c < UIP_LISTENPORTS; ++c) { - if(uip_listenports[c] == 0) { - uip_listenports[c] = port; - return; - } - } -} -/*-----------------------------------------------------------------------------------*/ -/* XXX: IP fragment reassembly: not well-tested. */ - -#if UIP_REASSEMBLY -#define UIP_REASS_BUFSIZE (UIP_BUFSIZE - UIP_LLH_LEN) -static u8_t uip_reassbuf[UIP_REASS_BUFSIZE]; -static u8_t uip_reassbitmap[UIP_REASS_BUFSIZE / (8 * 8)]; -static const u8_t bitmap_bits[8] = {0xff, 0x7f, 0x3f, 0x1f, - 0x0f, 0x07, 0x03, 0x01}; -static u16_t uip_reasslen; -static u8_t uip_reassflags; -#define UIP_REASS_FLAG_LASTFRAG 0x01 -static u8_t uip_reasstmr; - -#define IP_HLEN 20 -#define IP_MF 0x20 - -static u8_t -uip_reass(void) -{ - u16_t offset, len; - u16_t i; - - /* If ip_reasstmr is zero, no packet is present in the buffer, so we - write the IP header of the fragment into the reassembly - buffer. The timer is updated with the maximum age. */ - if(uip_reasstmr == 0) { - memcpy(uip_reassbuf, &BUF->vhl, IP_HLEN); - uip_reasstmr = UIP_REASS_MAXAGE; - uip_reassflags = 0; - /* Clear the bitmap. */ - memset(uip_reassbitmap, sizeof(uip_reassbitmap), 0); - } - - /* Check if the incoming fragment matches the one currently present - in the reasembly buffer. If so, we proceed with copying the - fragment into the buffer. */ - if(BUF->srcipaddr[0] == FBUF->srcipaddr[0] && - BUF->srcipaddr[1] == FBUF->srcipaddr[1] && - BUF->destipaddr[0] == FBUF->destipaddr[0] && - BUF->destipaddr[1] == FBUF->destipaddr[1] && - BUF->ipid[0] == FBUF->ipid[0] && - BUF->ipid[1] == FBUF->ipid[1]) { - - len = (BUF->len[0] << 8) + BUF->len[1] - (BUF->vhl & 0x0f) * 4; - offset = (((BUF->ipoffset[0] & 0x3f) << 8) + BUF->ipoffset[1]) * 8; - - /* If the offset or the offset + fragment length overflows the - reassembly buffer, we discard the entire packet. */ - if(offset > UIP_REASS_BUFSIZE || - offset + len > UIP_REASS_BUFSIZE) { - uip_reasstmr = 0; - goto nullreturn; - } - - /* Copy the fragment into the reassembly buffer, at the right - offset. */ - memcpy(&uip_reassbuf[IP_HLEN + offset], - (char *)BUF + (int)((BUF->vhl & 0x0f) * 4), - len); - - /* Update the bitmap. */ - if(offset / (8 * 8) == (offset + len) / (8 * 8)) { - /* If the two endpoints are in the same byte, we only update - that byte. */ - - uip_reassbitmap[offset / (8 * 8)] |= - bitmap_bits[(offset / 8 ) & 7] & - ~bitmap_bits[((offset + len) / 8 ) & 7]; - } else { - /* If the two endpoints are in different bytes, we update the - bytes in the endpoints and fill the stuff inbetween with - 0xff. */ - uip_reassbitmap[offset / (8 * 8)] |= - bitmap_bits[(offset / 8 ) & 7]; - for(i = 1 + offset / (8 * 8); i < (offset + len) / (8 * 8); ++i) { - uip_reassbitmap[i] = 0xff; - } - uip_reassbitmap[(offset + len) / (8 * 8)] |= - ~bitmap_bits[((offset + len) / 8 ) & 7]; - } - - /* If this fragment has the More Fragments flag set to zero, we - know that this is the last fragment, so we can calculate the - size of the entire packet. We also set the - IP_REASS_FLAG_LASTFRAG flag to indicate that we have received - the final fragment. */ - - if((BUF->ipoffset[0] & IP_MF) == 0) { - uip_reassflags |= UIP_REASS_FLAG_LASTFRAG; - uip_reasslen = offset + len; - } - - /* Finally, we check if we have a full packet in the buffer. We do - this by checking if we have the last fragment and if all bits - in the bitmap are set. */ - if(uip_reassflags & UIP_REASS_FLAG_LASTFRAG) { - /* Check all bytes up to and including all but the last byte in - the bitmap. */ - for(i = 0; i < uip_reasslen / (8 * 8) - 1; ++i) { - if(uip_reassbitmap[i] != 0xff) { - goto nullreturn; - } - } - /* Check the last byte in the bitmap. It should contain just the - right amount of bits. */ - if(uip_reassbitmap[uip_reasslen / (8 * 8)] != - (u8_t)~bitmap_bits[uip_reasslen / 8 & 7]) { - goto nullreturn; - } - - /* If we have come this far, we have a full packet in the - buffer, so we allocate a pbuf and copy the packet into it. We - also reset the timer. */ - uip_reasstmr = 0; - memcpy(BUF, FBUF, uip_reasslen); - - /* Pretend to be a "normal" (i.e., not fragmented) IP packet - from now on. */ - BUF->ipoffset[0] = BUF->ipoffset[1] = 0; - BUF->len[0] = uip_reasslen >> 8; - BUF->len[1] = uip_reasslen & 0xff; - BUF->ipchksum = 0; - BUF->ipchksum = ~(uip_ipchksum()); - - return uip_reasslen; - } - } - - nullreturn: - return 0; -} -#endif /* UIP_REASSEMBL */ -/*-----------------------------------------------------------------------------------*/ -static void -uip_add_rcv_nxt(u16_t n) -{ - uip_add32(uip_conn->rcv_nxt, n); - uip_conn->rcv_nxt[0] = uip_acc32[0]; - uip_conn->rcv_nxt[1] = uip_acc32[1]; - uip_conn->rcv_nxt[2] = uip_acc32[2]; - uip_conn->rcv_nxt[3] = uip_acc32[3]; -} -/*-----------------------------------------------------------------------------------*/ -void -uip_process(u8_t flag) -{ - register struct uip_conn *uip_connr = uip_conn; - - uip_appdata = &uip_buf[40 + UIP_LLH_LEN]; - - - /* Check if we were invoked because of the perodic timer fireing. */ - if(flag == UIP_TIMER) { -#if UIP_REASSEMBLY - if(uip_reasstmr != 0) { - --uip_reasstmr; - } -#endif /* UIP_REASSEMBLY */ - /* Increase the initial sequence number. */ - if(++iss[3] == 0) { - if(++iss[2] == 0) { - if(++iss[1] == 0) { - ++iss[0]; - } - } - } - uip_len = 0; - if(uip_connr->tcpstateflags == TIME_WAIT || - uip_connr->tcpstateflags == FIN_WAIT_2) { - ++(uip_connr->timer); - if(uip_connr->timer == UIP_TIME_WAIT_TIMEOUT) { - uip_connr->tcpstateflags = CLOSED; - } - } else if(uip_connr->tcpstateflags != CLOSED) { - /* If the connection has outstanding data, we increase the - connection's timer and see if it has reached the RTO value - in which case we retransmit. */ - if(uip_outstanding(uip_connr)) { - if(uip_connr->timer-- == 0) { - if(uip_connr->nrtx == UIP_MAXRTX || - ((uip_connr->tcpstateflags == SYN_SENT || - uip_connr->tcpstateflags == SYN_RCVD) && - uip_connr->nrtx == UIP_MAXSYNRTX)) { - uip_connr->tcpstateflags = CLOSED; - - /* We call UIP_APPCALL() with uip_flags set to - UIP_TIMEDOUT to inform the application that the - connection has timed out. */ - uip_flags = UIP_TIMEDOUT; - UIP_APPCALL(); - - /* We also send a reset packet to the remote host. */ - BUF->flags = TCP_RST | TCP_ACK; - goto tcp_send_nodata; - } - - /* Exponential backoff. */ - uip_connr->timer = UIP_RTO << (uip_connr->nrtx > 4? - 4: - uip_connr->nrtx); - ++(uip_connr->nrtx); - - /* Ok, so we need to retransmit. We do this differently - depending on which state we are in. In ESTABLISHED, we - call upon the application so that it may prepare the - data for the retransmit. In SYN_RCVD, we resend the - SYNACK that we sent earlier and in LAST_ACK we have to - retransmit our FINACK. */ - UIP_STAT(++uip_stat.tcp.rexmit); - switch(uip_connr->tcpstateflags & TS_MASK) { - case SYN_RCVD: - /* In the SYN_RCVD state, we should retransmit our - SYNACK. */ - goto tcp_send_synack; - -#if UIP_ACTIVE_OPEN - case SYN_SENT: - /* In the SYN_SENT state, we retransmit out SYN. */ - BUF->flags = 0; - goto tcp_send_syn; -#endif /* UIP_ACTIVE_OPEN */ - - case ESTABLISHED: - /* In the ESTABLISHED state, we call upon the application - to do the actual retransmit after which we jump into - the code for sending out the packet (the apprexmit - label). */ - uip_len = 0; - uip_slen = 0; - uip_flags = UIP_REXMIT; - UIP_APPCALL(); - goto apprexmit; - - case FIN_WAIT_1: - case CLOSING: - case LAST_ACK: - /* In all these states we should retransmit a FINACK. */ - goto tcp_send_finack; - - } - } - } else if((uip_connr->tcpstateflags & TS_MASK) == ESTABLISHED) { - /* If there was no need for a retransmission, we poll the - application for new data. */ - uip_len = 0; - uip_slen = 0; - uip_flags = UIP_POLL; - UIP_APPCALL(); - goto appsend; - } - } - goto drop; - } -#if UIP_UDP - if(flag == UIP_UDP_TIMER) { - if(uip_udp_conn->lport != 0) { - uip_appdata = &uip_buf[UIP_LLH_LEN + 28]; - uip_len = uip_slen = 0; - uip_flags = UIP_POLL; - UIP_UDP_APPCALL(); - goto udp_send; - } else { - goto drop; - } - } -#endif - - /* This is where the input processing starts. */ - UIP_STAT(++uip_stat.ip.recv); - - - /* Start of IPv4 input header processing code. */ - - /* Check validity of the IP header. */ - if(BUF->vhl != 0x45) { /* IP version and header length. */ - UIP_STAT(++uip_stat.ip.drop); - UIP_STAT(++uip_stat.ip.vhlerr); - UIP_LOG("ip: invalid version or header length."); - goto drop; - } - - /* Check the size of the packet. If the size reported to us in - uip_len doesn't match the size reported in the IP header, there - has been a transmission error and we drop the packet. */ - - if(BUF->len[0] != (uip_len >> 8)) { /* IP length, high byte. */ - uip_len = (uip_len & 0xff) | (BUF->len[0] << 8); - } - if(BUF->len[1] != (uip_len & 0xff)) { /* IP length, low byte. */ - uip_len = (uip_len & 0xff00) | BUF->len[1]; - } - - /* Check the fragment flag. */ - if((BUF->ipoffset[0] & 0x3f) != 0 || - BUF->ipoffset[1] != 0) { -#if UIP_REASSEMBLY - uip_len = uip_reass(); - if(uip_len == 0) { - goto drop; - } -#else - UIP_STAT(++uip_stat.ip.drop); - UIP_STAT(++uip_stat.ip.fragerr); - UIP_LOG("ip: fragment dropped."); - goto drop; -#endif /* UIP_REASSEMBLY */ - } - - /* If we are configured to use ping IP address configuration and - hasn't been assigned an IP address yet, we accept all ICMP - packets. */ -#if UIP_PINGADDRCONF - if((uip_hostaddr[0] | uip_hostaddr[1]) == 0) { - if(BUF->proto == UIP_PROTO_ICMP) { - UIP_LOG("ip: possible ping config packet received."); - goto icmp_input; - } else { - UIP_LOG("ip: packet dropped since no address assigned."); - goto drop; - } - } -#endif /* UIP_PINGADDRCONF */ - - /* Check if the packet is destined for our IP address. */ - if(BUF->destipaddr[0] != uip_hostaddr[0]) { - UIP_STAT(++uip_stat.ip.drop); - UIP_LOG("ip: packet not for us."); - goto drop; - } - if(BUF->destipaddr[1] != uip_hostaddr[1]) { - UIP_STAT(++uip_stat.ip.drop); - UIP_LOG("ip: packet not for us."); - goto drop; - } - -#if 0 - // IP checksum is wrong through Netgear DSL router - if (uip_ipchksum() != 0xffff) { /* Compute and check the IP header - checksum. */ - UIP_STAT(++uip_stat.ip.drop); - UIP_STAT(++uip_stat.ip.chkerr); - UIP_LOG("ip: bad checksum."); - goto drop; - } -#endif - - if(BUF->proto == UIP_PROTO_TCP) /* Check for TCP packet. If so, jump - to the tcp_input label. */ - goto tcp_input; - -#if UIP_UDP - if(BUF->proto == UIP_PROTO_UDP) - goto udp_input; -#endif /* UIP_UDP */ - - if(BUF->proto != UIP_PROTO_ICMP) { /* We only allow ICMP packets from - here. */ - UIP_STAT(++uip_stat.ip.drop); - UIP_STAT(++uip_stat.ip.protoerr); - UIP_LOG("ip: neither tcp nor icmp."); - goto drop; - } - -#if UIP_PINGADDRCONF - icmp_input: -#endif - UIP_STAT(++uip_stat.icmp.recv); - - /* ICMP echo (i.e., ping) processing. This is simple, we only change - the ICMP type from ECHO to ECHO_REPLY and adjust the ICMP - checksum before we return the packet. */ - if(ICMPBUF->type != ICMP_ECHO) { - UIP_STAT(++uip_stat.icmp.drop); - UIP_STAT(++uip_stat.icmp.typeerr); - UIP_LOG("icmp: not icmp echo."); - goto drop; - } - - /* If we are configured to use ping IP address assignment, we use - the destination IP address of this ping packet and assign it to - ourself. */ -#if UIP_PINGADDRCONF - if((uip_hostaddr[0] | uip_hostaddr[1]) == 0) { - uip_hostaddr[0] = BUF->destipaddr[0]; - uip_hostaddr[1] = BUF->destipaddr[1]; - } -#endif /* UIP_PINGADDRCONF */ - - ICMPBUF->type = ICMP_ECHO_REPLY; - - if(ICMPBUF->icmpchksum >= HTONS(0xffff - (ICMP_ECHO << 8))) { - ICMPBUF->icmpchksum += HTONS(ICMP_ECHO << 8) + 1; - } else { - ICMPBUF->icmpchksum += HTONS(ICMP_ECHO << 8); - } - - /* Swap IP addresses. */ - tmp16 = BUF->destipaddr[0]; - BUF->destipaddr[0] = BUF->srcipaddr[0]; - BUF->srcipaddr[0] = tmp16; - tmp16 = BUF->destipaddr[1]; - BUF->destipaddr[1] = BUF->srcipaddr[1]; - BUF->srcipaddr[1] = tmp16; - - UIP_STAT(++uip_stat.icmp.sent); - goto send; - - /* End of IPv4 input header processing code. */ - - -#if UIP_UDP - /* UDP input processing. */ - udp_input: - /* UDP processing is really just a hack. We don't do anything to the - UDP/IP headers, but let the UDP application do all the hard - work. If the application sets uip_slen, it has a packet to - send. */ -#if UIP_UDP_CHECKSUMS - if(uip_udpchksum() != 0xffff) { - UIP_STAT(++uip_stat.udp.drop); - UIP_STAT(++uip_stat.udp.chkerr); - UIP_LOG("udp: bad checksum."); - goto drop; - } -#endif /* UIP_UDP_CHECKSUMS */ - - /* Demultiplex this UDP packet between the UDP "connections". */ - for(uip_udp_conn = &uip_udp_conns[0]; - uip_udp_conn < &uip_udp_conns[UIP_UDP_CONNS]; - ++uip_udp_conn) { - if(uip_udp_conn->lport != 0 && - UDPBUF->destport == uip_udp_conn->lport && - (uip_udp_conn->rport == 0 || - UDPBUF->srcport == uip_udp_conn->rport) && - BUF->srcipaddr[0] == uip_udp_conn->ripaddr[0] && - BUF->srcipaddr[1] == uip_udp_conn->ripaddr[1]) { - goto udp_found; - } - } - goto drop; - - udp_found: - uip_len = uip_len - 28; - uip_appdata = &uip_buf[UIP_LLH_LEN + 28]; - uip_flags = UIP_NEWDATA; - uip_slen = 0; - UIP_UDP_APPCALL(); - udp_send: - if(uip_slen == 0) { - goto drop; - } - uip_len = uip_slen + 28; - - BUF->len[0] = (uip_len >> 8); - BUF->len[1] = (uip_len & 0xff); - - BUF->proto = UIP_PROTO_UDP; - - UDPBUF->udplen = HTONS(uip_slen + 8); - UDPBUF->udpchksum = 0; -#if UIP_UDP_CHECKSUMS - /* Calculate UDP checksum. */ - UDPBUF->udpchksum = ~(uip_udpchksum()); - if(UDPBUF->udpchksum == 0) { - UDPBUF->udpchksum = 0xffff; - } -#endif /* UIP_UDP_CHECKSUMS */ - - BUF->srcport = uip_udp_conn->lport; - BUF->destport = uip_udp_conn->rport; - - BUF->srcipaddr[0] = uip_hostaddr[0]; - BUF->srcipaddr[1] = uip_hostaddr[1]; - BUF->destipaddr[0] = uip_udp_conn->ripaddr[0]; - BUF->destipaddr[1] = uip_udp_conn->ripaddr[1]; - - uip_appdata = &uip_buf[UIP_LLH_LEN + 40]; - goto ip_send_nolen; -#endif /* UIP_UDP */ - - /* TCP input processing. */ - tcp_input: - UIP_STAT(++uip_stat.tcp.recv); - - /* Start of TCP input header processing code. */ - -#if 1 // FIXME - if(uip_tcpchksum() != 0xffff) { /* Compute and check the TCP - checksum. */ - UIP_STAT(++uip_stat.tcp.drop); - UIP_STAT(++uip_stat.tcp.chkerr); - UIP_LOG("tcp: bad checksum."); - goto drop; - } -#endif - - /* Demultiplex this segment. */ - /* First check any active connections. */ - for(uip_connr = &uip_conns[0]; uip_connr < &uip_conns[UIP_CONNS]; ++uip_connr) { - if(uip_connr->tcpstateflags != CLOSED && - BUF->destport == uip_connr->lport && - BUF->srcport == uip_connr->rport && - BUF->srcipaddr[0] == uip_connr->ripaddr[0] && - BUF->srcipaddr[1] == uip_connr->ripaddr[1]) { - goto found; - } - } - - /* If we didn't find and active connection that expected the packet, - either this packet is an old duplicate, or this is a SYN packet - destined for a connection in LISTEN. If the SYN flag isn't set, - it is an old packet and we send a RST. */ - if((BUF->flags & TCP_CTL) != TCP_SYN) - goto reset; - - tmp16 = BUF->destport; - /* Next, check listening connections. */ - for(c = 0; c < UIP_LISTENPORTS; ++c) { - if(tmp16 == uip_listenports[c]) - goto found_listen; - } - - /* No matching connection found, so we send a RST packet. */ - UIP_STAT(++uip_stat.tcp.synrst); - reset: - - /* We do not send resets in response to resets. */ - if(BUF->flags & TCP_RST) - goto drop; - - UIP_STAT(++uip_stat.tcp.rst); - - BUF->flags = TCP_RST | TCP_ACK; - uip_len = 40; - BUF->tcpoffset = 5 << 4; - - /* Flip the seqno and ackno fields in the TCP header. */ - c = BUF->seqno[3]; - BUF->seqno[3] = BUF->ackno[3]; - BUF->ackno[3] = c; - - c = BUF->seqno[2]; - BUF->seqno[2] = BUF->ackno[2]; - BUF->ackno[2] = c; - - c = BUF->seqno[1]; - BUF->seqno[1] = BUF->ackno[1]; - BUF->ackno[1] = c; - - c = BUF->seqno[0]; - BUF->seqno[0] = BUF->ackno[0]; - BUF->ackno[0] = c; - - /* We also have to increase the sequence number we are - acknowledging. If the least significant byte overflowed, we need - to propagate the carry to the other bytes as well. */ - if(++BUF->ackno[3] == 0) { - if(++BUF->ackno[2] == 0) { - if(++BUF->ackno[1] == 0) { - ++BUF->ackno[0]; - } - } - } - - /* Swap port numbers. */ - tmp16 = BUF->srcport; - BUF->srcport = BUF->destport; - BUF->destport = tmp16; - - /* Swap IP addresses. */ - tmp16 = BUF->destipaddr[0]; - BUF->destipaddr[0] = BUF->srcipaddr[0]; - BUF->srcipaddr[0] = tmp16; - tmp16 = BUF->destipaddr[1]; - BUF->destipaddr[1] = BUF->srcipaddr[1]; - BUF->srcipaddr[1] = tmp16; - - - /* And send out the RST packet! */ - goto tcp_send_noconn; - - /* This label will be jumped to if we matched the incoming packet - with a connection in LISTEN. In that case, we should create a new - connection and send a SYNACK in return. */ - found_listen: - /* First we check if there are any connections avaliable. Unused - connections are kept in the same table as used connections, but - unused ones have the tcpstate set to CLOSED. Also, connections in - TIME_WAIT are kept track of and we'll use the oldest one if no - CLOSED connections are found. Thanks to Eddie C. Dost for a very - nice algorithm for the TIME_WAIT search. */ - uip_connr = 0; - for(c = 0; c < UIP_CONNS; ++c) { - if(uip_conns[c].tcpstateflags == CLOSED) { - uip_connr = &uip_conns[c]; - break; - } - if(uip_conns[c].tcpstateflags == TIME_WAIT) { - if(uip_connr == 0 || - uip_conns[c].timer > uip_connr->timer) { - uip_connr = &uip_conns[c]; - } - } - } - - if(uip_connr == 0) { - /* All connections are used already, we drop packet and hope that - the remote end will retransmit the packet at a time when we - have more spare connections. */ - UIP_STAT(++uip_stat.tcp.syndrop); - UIP_LOG("tcp: found no unused connections."); - goto drop; - } - uip_conn = uip_connr; - - /* Fill in the necessary fields for the new connection. */ - uip_connr->rto = uip_connr->timer = UIP_RTO; - uip_connr->sa = 0; - uip_connr->sv = 4; - uip_connr->nrtx = 0; - uip_connr->lport = BUF->destport; - uip_connr->rport = BUF->srcport; - uip_connr->ripaddr[0] = BUF->srcipaddr[0]; - uip_connr->ripaddr[1] = BUF->srcipaddr[1]; - uip_connr->tcpstateflags = SYN_RCVD; - - uip_connr->snd_nxt[0] = iss[0]; - uip_connr->snd_nxt[1] = iss[1]; - uip_connr->snd_nxt[2] = iss[2]; - uip_connr->snd_nxt[3] = iss[3]; - uip_connr->len = 1; - - /* rcv_nxt should be the seqno from the incoming packet + 1. */ - uip_connr->rcv_nxt[3] = BUF->seqno[3]; - uip_connr->rcv_nxt[2] = BUF->seqno[2]; - uip_connr->rcv_nxt[1] = BUF->seqno[1]; - uip_connr->rcv_nxt[0] = BUF->seqno[0]; - uip_add_rcv_nxt(1); - - /* Parse the TCP MSS option, if present. */ - if((BUF->tcpoffset & 0xf0) > 0x50) { - for(c = 0; c < ((BUF->tcpoffset >> 4) - 5) << 2 ;) { - opt = uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + c]; - if(opt == 0x00) { - /* End of options. */ - break; - } else if(opt == 0x01) { - ++c; - /* NOP option. */ - } else if(opt == 0x02 && - uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0x04) { - /* An MSS option with the right option length. */ - tmp16 = ((u16_t)uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 2 + c] << 8) | - (u16_t)uip_buf[40 + UIP_LLH_LEN + 3 + c]; - uip_connr->initialmss = uip_connr->mss = - tmp16 > UIP_TCP_MSS? UIP_TCP_MSS: tmp16; - - /* And we are done processing options. */ - break; - } else { - /* All other options have a length field, so that we easily - can skip past them. */ - if(uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0) { - /* If the length field is zero, the options are malformed - and we don't process them further. */ - break; - } - c += uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c]; - } - } - } - - /* Our response will be a SYNACK. */ -#if UIP_ACTIVE_OPEN - tcp_send_synack: - BUF->flags = TCP_ACK; - - tcp_send_syn: - BUF->flags |= TCP_SYN; -#else /* UIP_ACTIVE_OPEN */ - tcp_send_synack: - BUF->flags = TCP_SYN | TCP_ACK; -#endif /* UIP_ACTIVE_OPEN */ - - /* We send out the TCP Maximum Segment Size option with our - SYNACK. */ - BUF->optdata[0] = 2; - BUF->optdata[1] = 4; - BUF->optdata[2] = (UIP_TCP_MSS) / 256; - BUF->optdata[3] = (UIP_TCP_MSS) & 255; - uip_len = 44; - BUF->tcpoffset = 6 << 4; - goto tcp_send; - - /* This label will be jumped to if we found an active connection. */ - found: - uip_conn = uip_connr; - uip_flags = 0; - - /* We do a very naive form of TCP reset processing; we just accept - any RST and kill our connection. We should in fact check if the - sequence number of this reset is wihtin our advertised window - before we accept the reset. */ - if(BUF->flags & TCP_RST) { - uip_connr->tcpstateflags = CLOSED; - UIP_LOG("tcp: got reset, aborting connection."); - uip_flags = UIP_ABORT; - UIP_APPCALL(); - goto drop; - } - /* Calculated the length of the data, if the application has sent - any data to us. */ - c = (BUF->tcpoffset >> 4) << 2; - /* uip_len will contain the length of the actual TCP data. This is - calculated by subtracing the length of the TCP header (in - c) and the length of the IP header (20 bytes). */ - uip_len = uip_len - c - 20; - - /* First, check if the sequence number of the incoming packet is - what we're expecting next. If not, we send out an ACK with the - correct numbers in. */ - if(uip_len > 0 && - (BUF->seqno[0] != uip_connr->rcv_nxt[0] || - BUF->seqno[1] != uip_connr->rcv_nxt[1] || - BUF->seqno[2] != uip_connr->rcv_nxt[2] || - BUF->seqno[3] != uip_connr->rcv_nxt[3])) { - goto tcp_send_ack; - } - - /* Next, check if the incoming segment acknowledges any outstanding - data. If so, we update the sequence number, reset the length of - the outstanding data, calculate RTT estimations, and reset the - retransmission timer. */ - if((BUF->flags & TCP_ACK) && uip_outstanding(uip_connr)) { - uip_add32(uip_connr->snd_nxt, uip_connr->len); - if(BUF->ackno[0] == uip_acc32[0] && - BUF->ackno[1] == uip_acc32[1] && - BUF->ackno[2] == uip_acc32[2] && - BUF->ackno[3] == uip_acc32[3]) { - /* Update sequence number. */ - uip_connr->snd_nxt[0] = uip_acc32[0]; - uip_connr->snd_nxt[1] = uip_acc32[1]; - uip_connr->snd_nxt[2] = uip_acc32[2]; - uip_connr->snd_nxt[3] = uip_acc32[3]; - - - /* Do RTT estimation, unless we have done retransmissions. */ - if(uip_connr->nrtx == 0) { - signed char m; - m = uip_connr->rto - uip_connr->timer; - /* This is taken directly from VJs original code in his paper */ - m = m - (uip_connr->sa >> 3); - uip_connr->sa += m; - if(m < 0) { - m = -m; - } - m = m - (uip_connr->sv >> 2); - uip_connr->sv += m; - uip_connr->rto = (uip_connr->sa >> 3) + uip_connr->sv; - - } - /* Set the acknowledged flag. */ - uip_flags = UIP_ACKDATA; - /* Reset the retransmission timer. */ - uip_connr->timer = uip_connr->rto; - } - - } - - /* Do different things depending on in what state the connection is. */ - switch(uip_connr->tcpstateflags & TS_MASK) { - /* CLOSED and LISTEN are not handled here. CLOSE_WAIT is not - implemented, since we force the application to close when the - peer sends a FIN (hence the application goes directly from - ESTABLISHED to LAST_ACK). */ - case SYN_RCVD: - /* In SYN_RCVD we have sent out a SYNACK in response to a SYN, and - we are waiting for an ACK that acknowledges the data we sent - out the last time. Therefore, we want to have the UIP_ACKDATA - flag set. If so, we enter the ESTABLISHED state. */ - if(uip_flags & UIP_ACKDATA) { - uip_connr->tcpstateflags = ESTABLISHED; - uip_flags = UIP_CONNECTED; - uip_connr->len = 0; - if(uip_len > 0) { - uip_flags |= UIP_NEWDATA; - uip_add_rcv_nxt(uip_len); - } - uip_slen = 0; - UIP_APPCALL(); - goto appsend; - } - goto drop; -#if UIP_ACTIVE_OPEN - case SYN_SENT: - /* In SYN_SENT, we wait for a SYNACK that is sent in response to - our SYN. The rcv_nxt is set to sequence number in the SYNACK - plus one, and we send an ACK. We move into the ESTABLISHED - state. */ - if((uip_flags & UIP_ACKDATA) && - BUF->flags == (TCP_SYN | TCP_ACK)) { - - /* Parse the TCP MSS option, if present. */ - if((BUF->tcpoffset & 0xf0) > 0x50) { - for(c = 0; c < ((BUF->tcpoffset >> 4) - 5) << 2 ;) { - opt = uip_buf[40 + UIP_LLH_LEN + c]; - if(opt == 0x00) { - /* End of options. */ - break; - } else if(opt == 0x01) { - ++c; - /* NOP option. */ - } else if(opt == 0x02 && - uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0x04) { - /* An MSS option with the right option length. */ - tmp16 = (uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 2 + c] << 8) | - uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 3 + c]; - uip_connr->initialmss = - uip_connr->mss = tmp16 > UIP_TCP_MSS? UIP_TCP_MSS: tmp16; - - /* And we are done processing options. */ - break; - } else { - /* All other options have a length field, so that we easily - can skip past them. */ - if(uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0) { - /* If the length field is zero, the options are malformed - and we don't process them further. */ - break; - } - c += uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c]; - } - } - } - uip_connr->tcpstateflags = ESTABLISHED; - uip_connr->rcv_nxt[0] = BUF->seqno[0]; - uip_connr->rcv_nxt[1] = BUF->seqno[1]; - uip_connr->rcv_nxt[2] = BUF->seqno[2]; - uip_connr->rcv_nxt[3] = BUF->seqno[3]; - uip_add_rcv_nxt(1); - uip_flags = UIP_CONNECTED | UIP_NEWDATA; - uip_connr->len = 0; - uip_len = 0; - uip_slen = 0; - UIP_APPCALL(); - goto appsend; - } - goto reset; -#endif /* UIP_ACTIVE_OPEN */ - - case ESTABLISHED: - /* In the ESTABLISHED state, we call upon the application to feed - data into the uip_buf. If the UIP_ACKDATA flag is set, the - application should put new data into the buffer, otherwise we are - retransmitting an old segment, and the application should put that - data into the buffer. - - If the incoming packet is a FIN, we should close the connection on - this side as well, and we send out a FIN and enter the LAST_ACK - state. We require that there is no outstanding data; otherwise the - sequence numbers will be screwed up. */ - - if(BUF->flags & TCP_FIN) { - if(uip_outstanding(uip_connr)) { - goto drop; - } - uip_add_rcv_nxt(1 + uip_len); - uip_flags = UIP_CLOSE; - if(uip_len > 0) { - uip_flags |= UIP_NEWDATA; - } - UIP_APPCALL(); - uip_connr->len = 1; - uip_connr->tcpstateflags = LAST_ACK; - uip_connr->nrtx = 0; - tcp_send_finack: - BUF->flags = TCP_FIN | TCP_ACK; - goto tcp_send_nodata; - } - - /* Check the URG flag. If this is set, the segment carries urgent - data that we must pass to the application. */ - if(BUF->flags & TCP_URG) { -#if UIP_URGDATA > 0 - uip_urglen = (BUF->urgp[0] << 8) | BUF->urgp[1]; - if(uip_urglen > uip_len) { - /* There is more urgent data in the next segment to come. */ - uip_urglen = uip_len; - } - uip_add_rcv_nxt(uip_urglen); - uip_len -= uip_urglen; - uip_urgdata = uip_appdata; - uip_appdata += uip_urglen; - } else { - uip_urglen = 0; -#endif /* UIP_URGDATA > 0 */ - uip_appdata += (BUF->urgp[0] << 8) | BUF->urgp[1]; - uip_len -= (BUF->urgp[0] << 8) | BUF->urgp[1]; - } - - - /* If uip_len > 0 we have TCP data in the packet, and we flag this - by setting the UIP_NEWDATA flag and update the sequence number - we acknowledge. If the application has stopped the dataflow - using uip_stop(), we must not accept any data packets from the - remote host. */ - if(uip_len > 0 && !(uip_connr->tcpstateflags & UIP_STOPPED)) { - uip_flags |= UIP_NEWDATA; - uip_add_rcv_nxt(uip_len); - } - - /* Check if the available buffer space advertised by the other end - is smaller than the initial MSS for this connection. If so, we - set the current MSS to the window size to ensure that the - application does not send more data than the other end can - handle. - - If the remote host advertises a zero window, we set the MSS to - the initial MSS so that the application will send an entire MSS - of data. This data will not be acknowledged by the receiver, - and the application will retransmit it. This is called the - "persistent timer" and uses the retransmission mechanim. - */ - tmp16 = ((u16_t)BUF->wnd[0] << 8) + (u16_t)BUF->wnd[1]; - if(tmp16 > uip_connr->initialmss || - tmp16 == 0) { - tmp16 = uip_connr->initialmss; - } - uip_connr->mss = tmp16; - - /* If this packet constitutes an ACK for outstanding data (flagged - by the UIP_ACKDATA flag, we should call the application since it - might want to send more data. If the incoming packet had data - from the peer (as flagged by the UIP_NEWDATA flag), the - application must also be notified. - - When the application is called, the global variable uip_len - contains the length of the incoming data. The application can - access the incoming data through the global pointer - uip_appdata, which usually points 40 bytes into the uip_buf - array. - - If the application wishes to send any data, this data should be - put into the uip_appdata and the length of the data should be - put into uip_len. If the application don't have any data to - send, uip_len must be set to 0. */ - if(uip_flags & (UIP_NEWDATA | UIP_ACKDATA)) { - uip_slen = 0; - UIP_APPCALL(); - - appsend: - - if(uip_flags & UIP_ABORT) { - uip_slen = 0; - uip_connr->tcpstateflags = CLOSED; - BUF->flags = TCP_RST | TCP_ACK; - goto tcp_send_nodata; - } - - if(uip_flags & UIP_CLOSE) { - uip_slen = 0; - uip_connr->len = 1; - uip_connr->tcpstateflags = FIN_WAIT_1; - uip_connr->nrtx = 0; - BUF->flags = TCP_FIN | TCP_ACK; - goto tcp_send_nodata; - } - - /* If uip_slen > 0, the application has data to be sent. */ - if(uip_slen > 0) { - - /* If the connection has acknowledged data, the contents of - the ->len variable should be discarded. */ - if((uip_flags & UIP_ACKDATA) != 0) { - uip_connr->len = 0; - } - - /* If the ->len variable is non-zero the connection has - already data in transit and cannot send anymore right - now. */ - if(uip_connr->len == 0) { - - /* The application cannot send more than what is allowed by - the mss (the minumum of the MSS and the available - window). */ - if(uip_slen > uip_connr->mss) { - uip_slen = uip_connr->mss; - } - - /* Remember how much data we send out now so that we know - when everything has been acknowledged. */ - uip_connr->len = uip_slen; - } else { - - /* If the application already had unacknowledged data, we - make sure that the application does not send (i.e., - retransmit) out more than it previously sent out. */ - uip_slen = uip_connr->len; - } - } else { - uip_connr->len = 0; - } - uip_connr->nrtx = 0; - apprexmit: - uip_appdata = uip_sappdata; - - /* If the application has data to be sent, or if the incoming - packet had new data in it, we must send out a packet. */ - if(uip_slen > 0 && uip_connr->len > 0) { - /* Add the length of the IP and TCP headers. */ - uip_len = uip_connr->len + UIP_TCPIP_HLEN; - /* We always set the ACK flag in response packets. */ - BUF->flags = TCP_ACK | TCP_PSH; - /* Send the packet. */ - goto tcp_send_noopts; - } - /* If there is no data to send, just send out a pure ACK if - there is newdata. */ - if(uip_flags & UIP_NEWDATA) { - uip_len = UIP_TCPIP_HLEN; - BUF->flags = TCP_ACK; - goto tcp_send_noopts; - } - } - goto drop; - case LAST_ACK: - /* We can close this connection if the peer has acknowledged our - FIN. This is indicated by the UIP_ACKDATA flag. */ - if(uip_flags & UIP_ACKDATA) { - uip_connr->tcpstateflags = CLOSED; - uip_flags = UIP_CLOSE; - UIP_APPCALL(); - } - break; - - case FIN_WAIT_1: - /* The application has closed the connection, but the remote host - hasn't closed its end yet. Thus we do nothing but wait for a - FIN from the other side. */ - if(uip_len > 0) { - uip_add_rcv_nxt(uip_len); - } - if(BUF->flags & TCP_FIN) { - if(uip_flags & UIP_ACKDATA) { - uip_connr->tcpstateflags = TIME_WAIT; - uip_connr->timer = 0; - uip_connr->len = 0; - } else { - uip_connr->tcpstateflags = CLOSING; - } - uip_add_rcv_nxt(1); - uip_flags = UIP_CLOSE; - UIP_APPCALL(); - goto tcp_send_ack; - } else if(uip_flags & UIP_ACKDATA) { - uip_connr->tcpstateflags = FIN_WAIT_2; - uip_connr->len = 0; - goto drop; - } - if(uip_len > 0) { - goto tcp_send_ack; - } - goto drop; - - case FIN_WAIT_2: - if(uip_len > 0) { - uip_add_rcv_nxt(uip_len); - } - if(BUF->flags & TCP_FIN) { - uip_connr->tcpstateflags = TIME_WAIT; - uip_connr->timer = 0; - uip_add_rcv_nxt(1); - uip_flags = UIP_CLOSE; - UIP_APPCALL(); - goto tcp_send_ack; - } - if(uip_len > 0) { - goto tcp_send_ack; - } - goto drop; - - case TIME_WAIT: - goto tcp_send_ack; - - case CLOSING: - if(uip_flags & UIP_ACKDATA) { - uip_connr->tcpstateflags = TIME_WAIT; - uip_connr->timer = 0; - } - } - goto drop; - - - /* We jump here when we are ready to send the packet, and just want - to set the appropriate TCP sequence numbers in the TCP header. */ - tcp_send_ack: - BUF->flags = TCP_ACK; - tcp_send_nodata: - uip_len = 40; - tcp_send_noopts: - BUF->tcpoffset = 5 << 4; - tcp_send: - /* We're done with the input processing. We are now ready to send a - reply. Our job is to fill in all the fields of the TCP and IP - headers before calculating the checksum and finally send the - packet. */ - BUF->ackno[0] = uip_connr->rcv_nxt[0]; - BUF->ackno[1] = uip_connr->rcv_nxt[1]; - BUF->ackno[2] = uip_connr->rcv_nxt[2]; - BUF->ackno[3] = uip_connr->rcv_nxt[3]; - - BUF->seqno[0] = uip_connr->snd_nxt[0]; - BUF->seqno[1] = uip_connr->snd_nxt[1]; - BUF->seqno[2] = uip_connr->snd_nxt[2]; - BUF->seqno[3] = uip_connr->snd_nxt[3]; - - BUF->proto = UIP_PROTO_TCP; - - BUF->srcport = uip_connr->lport; - BUF->destport = uip_connr->rport; - - BUF->srcipaddr[0] = uip_hostaddr[0]; - BUF->srcipaddr[1] = uip_hostaddr[1]; - BUF->destipaddr[0] = uip_connr->ripaddr[0]; - BUF->destipaddr[1] = uip_connr->ripaddr[1]; - - - if(uip_connr->tcpstateflags & UIP_STOPPED) { - /* If the connection has issued uip_stop(), we advertise a zero - window so that the remote host will stop sending data. */ - BUF->wnd[0] = BUF->wnd[1] = 0; - } else { - BUF->wnd[0] = ((UIP_RECEIVE_WINDOW) >> 8); - BUF->wnd[1] = ((UIP_RECEIVE_WINDOW) & 0xff); - } - - tcp_send_noconn: - - BUF->len[0] = (uip_len >> 8); - BUF->len[1] = (uip_len & 0xff); - - /* Calculate TCP checksum. */ - BUF->tcpchksum = 0; - BUF->tcpchksum = ~(uip_tcpchksum()); - - -#if UIP_UDP - ip_send_nolen: -#endif - - BUF->vhl = 0x45; - BUF->tos = 0; - BUF->ipoffset[0] = BUF->ipoffset[1] = 0; - BUF->ttl = UIP_TTL; - ++ipid; - BUF->ipid[0] = ipid >> 8; - BUF->ipid[1] = ipid & 0xff; - - /* Calculate IP checksum. */ - BUF->ipchksum = 0; - BUF->ipchksum = ~(uip_ipchksum()); - - UIP_STAT(++uip_stat.tcp.sent); - send: - UIP_STAT(++uip_stat.ip.sent); - /* Return and let the caller do the actual transmission. */ - return; - drop: - uip_len = 0; - return; -} -/*-----------------------------------------------------------------------------------*/ -u16_t -htons(u16_t val) -{ - return HTONS(val); -} -/*-----------------------------------------------------------------------------------*/ -/** @} */ diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/uip.h b/Demo/uIP_Demo_IAR_ARM7/uip/uip.h deleted file mode 100644 index 0ff1b2a79..000000000 --- a/Demo/uIP_Demo_IAR_ARM7/uip/uip.h +++ /dev/null @@ -1,1060 +0,0 @@ -/** - * \addtogroup uip - * @{ - */ - -/** - * \file - * Header file for the uIP TCP/IP stack. - * \author Adam Dunkels - * - * The uIP TCP/IP stack header file contains definitions for a number - * of C macros that are used by uIP programs as well as internal uIP - * structures, TCP/IP header structures and function declarations. - * - */ - - -/* - * Copyright (c) 2001-2003, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: uip.h,v 1.36.2.7 2003/10/07 13:47:51 adam Exp $ - * - */ - -#ifndef __UIP_H__ -#define __UIP_H__ - -#include "uipopt.h" - -/*-----------------------------------------------------------------------------------*/ -/* First, the functions that should be called from the - * system. Initialization, the periodic timer and incoming packets are - * handled by the following three functions. - */ - -/** - * \defgroup uipconffunc uIP configuration functions - * @{ - * - * The uIP configuration functions are used for setting run-time - * parameters in uIP such as IP addresses. - */ - -/** - * Set the IP address of this host. - * - * The IP address is represented as a 4-byte array where the first - * octet of the IP address is put in the first member of the 4-byte - * array. - * - * \param addr A pointer to a 4-byte representation of the IP address. - * - * \hideinitializer - */ -#define uip_sethostaddr(addr) do { uip_hostaddr[0] = addr[0]; \ - uip_hostaddr[1] = addr[1]; } while(0) - -/** - * Get the IP address of this host. - * - * The IP address is represented as a 4-byte array where the first - * octet of the IP address is put in the first member of the 4-byte - * array. - * - * \param addr A pointer to a 4-byte array that will be filled in with - * the currently configured IP address. - * - * \hideinitializer - */ -#define uip_gethostaddr(addr) do { addr[0] = uip_hostaddr[0]; \ - addr[1] = uip_hostaddr[1]; } while(0) - -/** @} */ - -/** - * \defgroup uipinit uIP initialization functions - * @{ - * - * The uIP initialization functions are used for booting uIP. - */ - -/** - * uIP initialization function. - * - * This function should be called at boot up to initilize the uIP - * TCP/IP stack. - */ -void uip_init(void); - -/** @} */ - -/** - * \defgroup uipdevfunc uIP device driver functions - * @{ - * - * These functions are used by a network device driver for interacting - * with uIP. - */ - -/** - * Process an incoming packet. - * - * This function should be called when the device driver has received - * a packet from the network. The packet from the device driver must - * be present in the uip_buf buffer, and the length of the packet - * should be placed in the uip_len variable. - * - * When the function returns, there may be an outbound packet placed - * in the uip_buf packet buffer. If so, the uip_len variable is set to - * the length of the packet. If no packet is to be sent out, the - * uip_len variable is set to 0. - * - * The usual way of calling the function is presented by the source - * code below. - \code - uip_len = devicedriver_poll(); - if(uip_len > 0) { - uip_input(); - if(uip_len > 0) { - devicedriver_send(); - } - } - \endcode - * - * \note If you are writing a uIP device driver that needs ARP - * (Address Resolution Protocol), e.g., when running uIP over - * Ethernet, you will need to call the uIP ARP code before calling - * this function: - \code - #define BUF ((struct uip_eth_hdr *)&uip_buf[0]) - uip_len = ethernet_devicedrver_poll(); - if(uip_len > 0) { - if(BUF->type == HTONS(UIP_ETHTYPE_IP)) { - uip_arp_ipin(); - uip_input(); - if(uip_len > 0) { - uip_arp_out(); - ethernet_devicedriver_send(); - } - } else if(BUF->type == HTONS(UIP_ETHTYPE_ARP)) { - uip_arp_arpin(); - if(uip_len > 0) { - ethernet_devicedriver_send(); - } - } - \endcode - * - * \hideinitializer - */ -#define uip_input() uip_process(UIP_DATA) - -/** - * Periodic processing for a connection identified by its number. - * - * This function does the necessary periodic processing (timers, - * polling) for a uIP TCP conneciton, and should be called when the - * periodic uIP timer goes off. It should be called for every - * connection, regardless of whether they are open of closed. - * - * When the function returns, it may have an outbound packet waiting - * for service in the uIP packet buffer, and if so the uip_len - * variable is set to a value larger than zero. The device driver - * should be called to send out the packet. - * - * The ususal way of calling the function is through a for() loop like - * this: - \code - for(i = 0; i < UIP_CONNS; ++i) { - uip_periodic(i); - if(uip_len > 0) { - devicedriver_send(); - } - } - \endcode - * - * \note If you are writing a uIP device driver that needs ARP - * (Address Resolution Protocol), e.g., when running uIP over - * Ethernet, you will need to call the uip_arp_out() function before - * calling the device driver: - \code - for(i = 0; i < UIP_CONNS; ++i) { - uip_periodic(i); - if(uip_len > 0) { - uip_arp_out(); - ethernet_devicedriver_send(); - } - } - \endcode - * - * \param conn The number of the connection which is to be periodically polled. - * - * \hideinitializer - */ -#define uip_periodic(conn) do { uip_conn = &uip_conns[conn]; \ - uip_process(UIP_TIMER); } while (0) - -/** - * Periodic processing for a connection identified by a pointer to its structure. - * - * Same as uip_periodic() but takes a pointer to the actual uip_conn - * struct instead of an integer as its argument. This function can be - * used to force periodic processing of a specific connection. - * - * \param conn A pointer to the uip_conn struct for the connection to - * be processed. - * - * \hideinitializer - */ -#define uip_periodic_conn(conn) do { uip_conn = conn; \ - uip_process(UIP_TIMER); } while (0) - -#if UIP_UDP -/** - * Periodic processing for a UDP connection identified by its number. - * - * This function is essentially the same as uip_prerioic(), but for - * UDP connections. It is called in a similar fashion as the - * uip_periodic() function: - \code - for(i = 0; i < UIP_UDP_CONNS; i++) { - uip_udp_periodic(i); - if(uip_len > 0) { - devicedriver_send(); - } - } - \endcode - * - * \note As for the uip_periodic() function, special care has to be - * taken when using uIP together with ARP and Ethernet: - \code - for(i = 0; i < UIP_UDP_CONNS; i++) { - uip_udp_periodic(i); - if(uip_len > 0) { - uip_arp_out(); - ethernet_devicedriver_send(); - } - } - \endcode - * - * \param conn The number of the UDP connection to be processed. - * - * \hideinitializer - */ -#define uip_udp_periodic(conn) do { uip_udp_conn = &uip_udp_conns[conn]; \ - uip_process(UIP_UDP_TIMER); } while (0) - -/** - * Periodic processing for a UDP connection identified by a pointer to - * its structure. - * - * Same as uip_udp_periodic() but takes a pointer to the actual - * uip_conn struct instead of an integer as its argument. This - * function can be used to force periodic processing of a specific - * connection. - * - * \param conn A pointer to the uip_udp_conn struct for the connection - * to be processed. - * - * \hideinitializer - */ -#define uip_udp_periodic_conn(conn) do { uip_udp_conn = conn; \ - uip_process(UIP_UDP_TIMER); } while (0) - - -#endif /* UIP_UDP */ - -/** - * The uIP packet buffer. - * - * The uip_buf array is used to hold incoming and outgoing - * packets. The device driver should place incoming data into this - * buffer. When sending data, the device driver should read the link - * level headers and the TCP/IP headers from this buffer. The size of - * the link level headers is configured by the UIP_LLH_LEN define. - * - * \note The application data need not be placed in this buffer, so - * the device driver must read it from the place pointed to by the - * uip_appdata pointer as illustrated by the following example: - \code - void - devicedriver_send(void) - { - hwsend(&uip_buf[0], UIP_LLH_LEN); - hwsend(&uip_buf[UIP_LLH_LEN], 40); - hwsend(uip_appdata, uip_len - 40 - UIP_LLH_LEN); - } - \endcode - */ -extern u8_t uip_buf[UIP_BUFSIZE+2]; /*_RB_ __attribute__ ((aligned (4)));*/ - -/** @} */ - -/*-----------------------------------------------------------------------------------*/ -/* Functions that are used by the uIP application program. Opening and - * closing connections, sending and receiving data, etc. is all - * handled by the functions below. -*/ -/** - * \defgroup uipappfunc uIP application functions - * @{ - * - * Functions used by an application running of top of uIP. - */ - -/** - * Start listening to the specified port. - * - * \note Since this function expects the port number in network byte - * order, a conversion using HTONS() or htons() is necessary. - * - \code - uip_listen(HTONS(80)); - \endcode - * - * \param port A 16-bit port number in network byte order. - */ -void uip_listen(u16_t port); - -/** - * Stop listening to the specified port. - * - * \note Since this function expects the port number in network byte - * order, a conversion using HTONS() or htons() is necessary. - * - \code - uip_unlisten(HTONS(80)); - \endcode - * - * \param port A 16-bit port number in network byte order. - */ -void uip_unlisten(u16_t port); - -/** - * Connect to a remote host using TCP. - * - * This function is used to start a new connection to the specified - * port on the specied host. It allocates a new connection identifier, - * sets the connection to the SYN_SENT state and sets the - * retransmission timer to 0. This will cause a TCP SYN segment to be - * sent out the next time this connection is periodically processed, - * which usually is done within 0.5 seconds after the call to - * uip_connect(). - * - * \note This function is avaliable only if support for active open - * has been configured by defining UIP_ACTIVE_OPEN to 1 in uipopt.h. - * - * \note Since this function requires the port number to be in network - * byte order, a convertion using HTONS() or htons() is necessary. - * - \code - u16_t ipaddr[2]; - - uip_ipaddr(ipaddr, 192,168,1,2); - uip_connect(ipaddr, HTONS(80)); - \endcode - * - * \param ripaddr A pointer to a 4-byte array representing the IP - * address of the remote hot. - * - * \param port A 16-bit port number in network byte order. - * - * \return A pointer to the uIP connection identifier for the new connection, - * or NULL if no connection could be allocated. - * - */ -struct uip_conn *uip_connect(u16_t *ripaddr, u16_t port); - - - -/** - * \internal - * - * Check if a connection has outstanding (i.e., unacknowledged) data. - * - * \param conn A pointer to the uip_conn structure for the connection. - * - * \hideinitializer - */ -#define uip_outstanding(conn) ((conn)->len) - -/** - * Send data on the current connection. - * - * This function is used to send out a single segment of TCP - * data. Only applications that have been invoked by uIP for event - * processing can send data. - * - * The amount of data that actually is sent out after a call to this - * funcion is determined by the maximum amount of data TCP allows. uIP - * will automatically crop the data so that only the appropriate - * amount of data is sent. The function uip_mss() can be used to query - * uIP for the amount of data that actually will be sent. - * - * \note This function does not guarantee that the sent data will - * arrive at the destination. If the data is lost in the network, the - * application will be invoked with the uip_rexmit() event being - * set. The application will then have to resend the data using this - * function. - * - * \param data A pointer to the data which is to be sent. - * - * \param len The maximum amount of data bytes to be sent. - * - * \hideinitializer - */ -#define uip_send(data, len) do { uip_sappdata = (data); uip_slen = (len);} while(0) - -/** - * The length of any incoming data that is currently avaliable (if avaliable) - * in the uip_appdata buffer. - * - * The test function uip_data() must first be used to check if there - * is any data available at all. - * - * \hideinitializer - */ -#define uip_datalen() uip_len - -/** - * The length of any out-of-band data (urgent data) that has arrived - * on the connection. - * - * \note The configuration parameter UIP_URGDATA must be set for this - * function to be enabled. - * - * \hideinitializer - */ -#define uip_urgdatalen() uip_urglen - -/** - * Close the current connection. - * - * This function will close the current connection in a nice way. - * - * \hideinitializer - */ -#define uip_close() (uip_flags = UIP_CLOSE) - -/** - * Abort the current connection. - * - * This function will abort (reset) the current connection, and is - * usually used when an error has occured that prevents using the - * uip_close() function. - * - * \hideinitializer - */ -#define uip_abort() (uip_flags = UIP_ABORT) - -/** - * Tell the sending host to stop sending data. - * - * This function will close our receiver's window so that we stop - * receiving data for the current connection. - * - * \hideinitializer - */ -#define uip_stop() (uip_conn->tcpstateflags |= UIP_STOPPED) - -/** - * Find out if the current connection has been previously stopped with - * uip_stop(). - * - * \hideinitializer - */ -#define uip_stopped(conn) ((conn)->tcpstateflags & UIP_STOPPED) - -/** - * Restart the current connection, if is has previously been stopped - * with uip_stop(). - * - * This function will open the receiver's window again so that we - * start receiving data for the current connection. - * - * \hideinitializer - */ -#define uip_restart() do { uip_flags |= UIP_NEWDATA; \ - uip_conn->tcpstateflags &= ~UIP_STOPPED; \ - } while(0) - - -/* uIP tests that can be made to determine in what state the current - connection is, and what the application function should do. */ - -/** - * Is new incoming data available? - * - * Will reduce to non-zero if there is new data for the application - * present at the uip_appdata pointer. The size of the data is - * avaliable through the uip_len variable. - * - * \hideinitializer - */ -#define uip_newdata() (uip_flags & UIP_NEWDATA) - -/** - * Has previously sent data been acknowledged? - * - * Will reduce to non-zero if the previously sent data has been - * acknowledged by the remote host. This means that the application - * can send new data. - * - * \hideinitializer - */ -#define uip_acked() (uip_flags & UIP_ACKDATA) - -/** - * Has the connection just been connected? - * - * Reduces to non-zero if the current connection has been connected to - * a remote host. This will happen both if the connection has been - * actively opened (with uip_connect()) or passively opened (with - * uip_listen()). - * - * \hideinitializer - */ -#define uip_connected() (uip_flags & UIP_CONNECTED) - -/** - * Has the connection been closed by the other end? - * - * Is non-zero if the connection has been closed by the remote - * host. The application may then do the necessary clean-ups. - * - * \hideinitializer - */ -#define uip_closed() (uip_flags & UIP_CLOSE) - -/** - * Has the connection been aborted by the other end? - * - * Non-zero if the current connection has been aborted (reset) by the - * remote host. - * - * \hideinitializer - */ -#define uip_aborted() (uip_flags & UIP_ABORT) - -/** - * Has the connection timed out? - * - * Non-zero if the current connection has been aborted due to too many - * retransmissions. - * - * \hideinitializer - */ -#define uip_timedout() (uip_flags & UIP_TIMEDOUT) - -/** - * Do we need to retransmit previously data? - * - * Reduces to non-zero if the previously sent data has been lost in - * the network, and the application should retransmit it. The - * application should send the exact same data as it did the last - * time, using the uip_send() function. - * - * \hideinitializer - */ -#define uip_rexmit() (uip_flags & UIP_REXMIT) - -/** - * Is the connection being polled by uIP? - * - * Is non-zero if the reason the application is invoked is that the - * current connection has been idle for a while and should be - * polled. - * - * The polling event can be used for sending data without having to - * wait for the remote host to send data. - * - * \hideinitializer - */ -#define uip_poll() (uip_flags & UIP_POLL) - -/** - * Get the initial maxium segment size (MSS) of the current - * connection. - * - * \hideinitializer - */ -#define uip_initialmss() (uip_conn->initialmss) - -/** - * Get the current maxium segment size that can be sent on the current - * connection. - * - * The current maxiumum segment size that can be sent on the - * connection is computed from the receiver's window and the MSS of - * the connection (which also is available by calling - * uip_initialmss()). - * - * \hideinitializer - */ -#define uip_mss() (uip_conn->mss) - -/** - * Set up a new UDP connection. - * - * \param ripaddr A pointer to a 4-byte structure representing the IP - * address of the remote host. - * - * \param rport The remote port number in network byte order. - * - * \return The uip_udp_conn structure for the new connection or NULL - * if no connection could be allocated. - */ -struct uip_udp_conn *uip_udp_new(u16_t *ripaddr, u16_t rport); - -/** - * Removed a UDP connection. - * - * \param conn A pointer to the uip_udp_conn structure for the connection. - * - * \hideinitializer - */ -#define uip_udp_remove(conn) (conn)->lport = 0 - -/** - * Send a UDP datagram of length len on the current connection. - * - * This function can only be called in response to a UDP event (poll - * or newdata). The data must be present in the uip_buf buffer, at the - * place pointed to by the uip_appdata pointer. - * - * \param len The length of the data in the uip_buf buffer. - * - * \hideinitializer - */ -#define uip_udp_send(len) uip_slen = (len) - -/** @} */ - -/* uIP convenience and converting functions. */ - -/** - * \defgroup uipconvfunc uIP conversion functions - * @{ - * - * These functions can be used for converting between different data - * formats used by uIP. - */ - -/** - * Pack an IP address into a 4-byte array which is used by uIP to - * represent IP addresses. - * - * Example: - \code - u16_t ipaddr[2]; - - uip_ipaddr(&ipaddr, 192,168,1,2); - \endcode - * - * \param addr A pointer to a 4-byte array that will be filled in with - * the IP addres. - * \param addr0 The first octet of the IP address. - * \param addr1 The second octet of the IP address. - * \param addr2 The third octet of the IP address. - * \param addr3 The forth octet of the IP address. - * - * \hideinitializer - */ -#define uip_ipaddr(addr, addr0,addr1,addr2,addr3) do { \ - (addr)[0] = HTONS(((addr0) << 8) | (addr1)); \ - (addr)[1] = HTONS(((addr2) << 8) | (addr3)); \ - } while(0) - -/** - * Convert 16-bit quantity from host byte order to network byte order. - * - * This macro is primarily used for converting constants from host - * byte order to network byte order. For converting variables to - * network byte order, use the htons() function instead. - * - * \hideinitializer - */ -#ifndef HTONS -# if BYTE_ORDER == BIG_ENDIAN -# define HTONS(n) (n) -# else /* BYTE_ORDER == BIG_ENDIAN */ -# define HTONS(n) ((((u16_t)((n) & 0xff)) << 8) | (((n) & 0xff00) >> 8)) -# endif /* BYTE_ORDER == BIG_ENDIAN */ -#endif /* HTONS */ - -/** - * Convert 16-bit quantity from host byte order to network byte order. - * - * This function is primarily used for converting variables from host - * byte order to network byte order. For converting constants to - * network byte order, use the HTONS() macro instead. - */ -#ifndef htons -u16_t htons(u16_t val); -#endif /* htons */ - -/** @} */ - -/** - * Pointer to the application data in the packet buffer. - * - * This pointer points to the application data when the application is - * called. If the application wishes to send data, the application may - * use this space to write the data into before calling uip_send(). - */ -extern volatile u8_t *uip_appdata; -extern volatile u8_t *uip_sappdata; - -#if UIP_URGDATA > 0 -/* u8_t *uip_urgdata: - * - * This pointer points to any urgent data that has been received. Only - * present if compiled with support for urgent data (UIP_URGDATA). - */ -extern volatile u8_t *uip_urgdata; -#endif /* UIP_URGDATA > 0 */ - - -/* u[8|16]_t uip_len: - * - * When the application is called, uip_len contains the length of any - * new data that has been received from the remote host. The - * application should set this variable to the size of any data that - * the application wishes to send. When the network device driver - * output function is called, uip_len should contain the length of the - * outgoing packet. - */ -extern volatile u16_t uip_len, uip_slen; - -#if UIP_URGDATA > 0 -extern volatile u8_t uip_urglen, uip_surglen; -#endif /* UIP_URGDATA > 0 */ - - -/** - * Representation of a uIP TCP connection. - * - * The uip_conn structure is used for identifying a connection. All - * but one field in the structure are to be considered read-only by an - * application. The only exception is the appstate field whos purpose - * is to let the application store application-specific state (e.g., - * file pointers) for the connection. The size of this field is - * configured in the "uipopt.h" header file. - */ -struct uip_conn { - u16_t ripaddr[2]; /**< The IP address of the remote host. */ - - u16_t lport; /**< The local TCP port, in network byte order. */ - u16_t rport; /**< The local remote TCP port, in network byte - order. */ - - u8_t rcv_nxt[4]; /**< The sequence number that we expect to - receive next. */ - u8_t snd_nxt[4]; /**< The sequence number that was last sent by - us. */ - u16_t len; /**< Length of the data that was previously sent. */ - u16_t mss; /**< Current maximum segment size for the - connection. */ - u16_t initialmss; /**< Initial maximum segment size for the - connection. */ - u8_t sa; /**< Retransmission time-out calculation state - variable. */ - u8_t sv; /**< Retransmission time-out calculation state - variable. */ - u8_t rto; /**< Retransmission time-out. */ - u8_t tcpstateflags; /**< TCP state and flags. */ - u8_t timer; /**< The retransmission timer. */ - u8_t nrtx; /**< The number of retransmissions for the last - segment sent. */ - - /** The application state. */ - u8_t appstate[UIP_APPSTATE_SIZE]; -}; - - -/* Pointer to the current connection. */ -extern struct uip_conn *uip_conn; -/* The array containing all uIP connections. */ -extern struct uip_conn uip_conns[UIP_CONNS]; -/** - * \addtogroup uiparch - * @{ - */ - -/** - * 4-byte array used for the 32-bit sequence number calculations. - */ -extern volatile u8_t uip_acc32[4]; - -/** @} */ - - -#if UIP_UDP -/** - * Representation of a uIP UDP connection. - */ -struct uip_udp_conn { - u16_t ripaddr[2]; /**< The IP address of the remote peer. */ - u16_t lport; /**< The local port number in network byte order. */ - u16_t rport; /**< The remote port number in network byte order. */ -}; - -extern struct uip_udp_conn *uip_udp_conn; -extern struct uip_udp_conn uip_udp_conns[UIP_UDP_CONNS]; -#endif /* UIP_UDP */ - -/** - * The structure holding the TCP/IP statistics that are gathered if - * UIP_STATISTICS is set to 1. - * - */ -struct uip_stats { - struct { - uip_stats_t drop; /**< Number of dropped packets at the IP - layer. */ - uip_stats_t recv; /**< Number of received packets at the IP - layer. */ - uip_stats_t sent; /**< Number of sent packets at the IP - layer. */ - uip_stats_t vhlerr; /**< Number of packets dropped due to wrong - IP version or header length. */ - uip_stats_t hblenerr; /**< Number of packets dropped due to wrong - IP length, high byte. */ - uip_stats_t lblenerr; /**< Number of packets dropped due to wrong - IP length, low byte. */ - uip_stats_t fragerr; /**< Number of packets dropped since they - were IP fragments. */ - uip_stats_t chkerr; /**< Number of packets dropped due to IP - checksum errors. */ - uip_stats_t protoerr; /**< Number of packets dropped since they - were neither ICMP, UDP nor TCP. */ - } ip; /**< IP statistics. */ - struct { - uip_stats_t drop; /**< Number of dropped ICMP packets. */ - uip_stats_t recv; /**< Number of received ICMP packets. */ - uip_stats_t sent; /**< Number of sent ICMP packets. */ - uip_stats_t typeerr; /**< Number of ICMP packets with a wrong - type. */ - } icmp; /**< ICMP statistics. */ - struct { - uip_stats_t drop; /**< Number of dropped TCP segments. */ - uip_stats_t recv; /**< Number of recived TCP segments. */ - uip_stats_t sent; /**< Number of sent TCP segments. */ - uip_stats_t chkerr; /**< Number of TCP segments with a bad - checksum. */ - uip_stats_t ackerr; /**< Number of TCP segments with a bad ACK - number. */ - uip_stats_t rst; /**< Number of recevied TCP RST (reset) segments. */ - uip_stats_t rexmit; /**< Number of retransmitted TCP segments. */ - uip_stats_t syndrop; /**< Number of dropped SYNs due to too few - connections was avaliable. */ - uip_stats_t synrst; /**< Number of SYNs for closed ports, - triggering a RST. */ - } tcp; /**< TCP statistics. */ -}; - -/** - * The uIP TCP/IP statistics. - * - * This is the variable in which the uIP TCP/IP statistics are gathered. - */ -extern struct uip_stats uip_stat; - - -/*-----------------------------------------------------------------------------------*/ -/* All the stuff below this point is internal to uIP and should not be - * used directly by an application or by a device driver. - */ -/*-----------------------------------------------------------------------------------*/ -/* u8_t uip_flags: - * - * When the application is called, uip_flags will contain the flags - * that are defined in this file. Please read below for more - * infomation. - */ -extern volatile u8_t uip_flags; - -/* The following flags may be set in the global variable uip_flags - before calling the application callback. The UIP_ACKDATA and - UIP_NEWDATA flags may both be set at the same time, whereas the - others are mutualy exclusive. Note that these flags should *NOT* be - accessed directly, but through the uIP functions/macros. */ - -#define UIP_ACKDATA 1 /* Signifies that the outstanding data was - acked and the application should send - out new data instead of retransmitting - the last data. */ -#define UIP_NEWDATA 2 /* Flags the fact that the peer has sent - us new data. */ -#define UIP_REXMIT 4 /* Tells the application to retransmit the - data that was last sent. */ -#define UIP_POLL 8 /* Used for polling the application, to - check if the application has data that - it wants to send. */ -#define UIP_CLOSE 16 /* The remote host has closed the - connection, thus the connection has - gone away. Or the application signals - that it wants to close the - connection. */ -#define UIP_ABORT 32 /* The remote host has aborted the - connection, thus the connection has - gone away. Or the application signals - that it wants to abort the - connection. */ -#define UIP_CONNECTED 64 /* We have got a connection from a remote - host and have set up a new connection - for it, or an active connection has - been successfully established. */ - -#define UIP_TIMEDOUT 128 /* The connection has been aborted due to - too many retransmissions. */ - - -/* uip_process(flag): - * - * The actual uIP function which does all the work. - */ -void uip_process(u8_t flag); - -/* The following flags are passed as an argument to the uip_process() - function. They are used to distinguish between the two cases where - uip_process() is called. It can be called either because we have - incoming data that should be processed, or because the periodic - timer has fired. */ - -#define UIP_DATA 1 /* Tells uIP that there is incoming data in - the uip_buf buffer. The length of the - data is stored in the global variable - uip_len. */ -#define UIP_TIMER 2 /* Tells uIP that the periodic timer has - fired. */ -#if UIP_UDP -#define UIP_UDP_TIMER 3 -#endif /* UIP_UDP */ - -/* The TCP states used in the uip_conn->tcpstateflags. */ -#define CLOSED 0 -#define SYN_RCVD 1 -#define SYN_SENT 2 -#define ESTABLISHED 3 -#define FIN_WAIT_1 4 -#define FIN_WAIT_2 5 -#define CLOSING 6 -#define TIME_WAIT 7 -#define LAST_ACK 8 -#define TS_MASK 15 - -#define UIP_STOPPED 16 - -#define UIP_TCPIP_HLEN 40 - -/* The TCP and IP headers. */ -typedef struct { - /* IP header. */ - u8_t vhl, - tos, - len[2], - ipid[2], - ipoffset[2], - ttl, - proto; - u16_t ipchksum; - u16_t srcipaddr[2], - destipaddr[2]; - - /* TCP header. */ - u16_t srcport, - destport; - u8_t seqno[4], - ackno[4], - tcpoffset, - flags, - wnd[2]; - u16_t tcpchksum; - u8_t urgp[2]; - u8_t optdata[4]; -} uip_tcpip_hdr; - -/* The ICMP and IP headers. */ -typedef struct { - /* IP header. */ - u8_t vhl, - tos, - len[2], - ipid[2], - ipoffset[2], - ttl, - proto; - u16_t ipchksum; - u16_t srcipaddr[2], - destipaddr[2]; - /* ICMP (echo) header. */ - u8_t type, icode; - u16_t icmpchksum; - u16_t id, seqno; -} uip_icmpip_hdr; - - -/* The UDP and IP headers. */ -typedef struct { - /* IP header. */ - u8_t vhl, - tos, - len[2], - ipid[2], - ipoffset[2], - ttl, - proto; - u16_t ipchksum; - u16_t srcipaddr[2], - destipaddr[2]; - - /* UDP header. */ - u16_t srcport, - destport; - u16_t udplen; - u16_t udpchksum; -} uip_udpip_hdr; - -#define UIP_PROTO_ICMP 1 -#define UIP_PROTO_TCP 6 -#define UIP_PROTO_UDP 17 - -#if UIP_FIXEDADDR -extern const u16_t uip_hostaddr[2]; -#else /* UIP_FIXEDADDR */ -extern u16_t uip_hostaddr[2]; -#endif /* UIP_FIXEDADDR */ - -#endif /* __UIP_H__ */ - - -/** @} */ - diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/uip_arch.c b/Demo/uIP_Demo_IAR_ARM7/uip/uip_arch.c deleted file mode 100644 index 9dad18cc5..000000000 --- a/Demo/uIP_Demo_IAR_ARM7/uip/uip_arch.c +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Copyright (c) 2001, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: uip_arch.c,v 1.2.2.1 2003/10/04 22:54:17 adam Exp $ - * - */ - - -#include "uip.h" -#include "uip_arch.h" - -#define BUF ((uip_tcpip_hdr *)&uip_buf[UIP_LLH_LEN]) -#define IP_PROTO_TCP 6 - -/*-----------------------------------------------------------------------------------*/ -void -uip_add32(u8_t *op32, u16_t op16) -{ - - uip_acc32[3] = op32[3] + (op16 & 0xff); - uip_acc32[2] = op32[2] + (op16 >> 8); - uip_acc32[1] = op32[1]; - uip_acc32[0] = op32[0]; - - if(uip_acc32[2] < (op16 >> 8)) { - ++uip_acc32[1]; - if(uip_acc32[1] == 0) { - ++uip_acc32[0]; - } - } - - - if(uip_acc32[3] < (op16 & 0xff)) { - ++uip_acc32[2]; - if(uip_acc32[2] == 0) { - ++uip_acc32[1]; - if(uip_acc32[1] == 0) { - ++uip_acc32[0]; - } - } - } -} -/*-----------------------------------------------------------------------------------*/ -u16_t -uip_chksum(u16_t *sdata, u16_t len) -{ - u16_t acc; - - for (acc = 0; len > 1; len -= 2) { - u16_t u = ((unsigned char *)sdata)[0] + (((unsigned char *)sdata)[1] << 8); - if ((acc += u) < u) { - /* Overflow, so we add the carry to acc (i.e., increase by - one). */ - ++acc; - } - ++sdata; - } - - /* add up any odd byte */ - if(len == 1) { - acc += htons(((u16_t)(*(u8_t *)sdata)) << 8); - if(acc < htons(((u16_t)(*(u8_t *)sdata)) << 8)) { - ++acc; - } - } - - return acc; -} -/*-----------------------------------------------------------------------------------*/ -u16_t -uip_ipchksum(void) -{ - return uip_chksum((u16_t *)&uip_buf[UIP_LLH_LEN], 20); -} -/*-----------------------------------------------------------------------------------*/ -u16_t -uip_tcpchksum(void) -{ - u16_t hsum, sum; - - - /* Compute the checksum of the TCP header. */ - hsum = uip_chksum((u16_t *)&uip_buf[20 + UIP_LLH_LEN], 20); - - /* Compute the checksum of the data in the TCP packet and add it to - the TCP header checksum. */ - sum = uip_chksum((u16_t *)uip_appdata, - (u16_t)(((((u16_t)(BUF->len[0]) << 8) + BUF->len[1]) - 40))); - - if((sum += hsum) < hsum) { - ++sum; - } - - if((sum += BUF->srcipaddr[0]) < BUF->srcipaddr[0]) { - ++sum; - } - if((sum += BUF->srcipaddr[1]) < BUF->srcipaddr[1]) { - ++sum; - } - if((sum += BUF->destipaddr[0]) < BUF->destipaddr[0]) { - ++sum; - } - if((sum += BUF->destipaddr[1]) < BUF->destipaddr[1]) { - ++sum; - } - if((sum += (u16_t)htons((u16_t)IP_PROTO_TCP)) < (u16_t)htons((u16_t)IP_PROTO_TCP)) { - ++sum; - } - - hsum = (u16_t)htons((((u16_t)(BUF->len[0]) << 8) + BUF->len[1]) - 20); - - if((sum += hsum) < hsum) { - ++sum; - } - - return sum; -} -/*-----------------------------------------------------------------------------------*/ diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/uip_arch.h b/Demo/uIP_Demo_IAR_ARM7/uip/uip_arch.h deleted file mode 100644 index b2d133f2e..000000000 --- a/Demo/uIP_Demo_IAR_ARM7/uip/uip_arch.h +++ /dev/null @@ -1,130 +0,0 @@ -/** - * \defgroup uiparch Architecture specific uIP functions - * @{ - * - * The functions in the architecture specific module implement the IP - * check sum and 32-bit additions. - * - * The IP checksum calculation is the most computationally expensive - * operation in the TCP/IP stack and it therefore pays off to - * implement this in efficient assembler. The purpose of the uip-arch - * module is to let the checksum functions to be implemented in - * architecture specific assembler. - * - */ - -/** - * \file - * Declarations of architecture specific functions. - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2001, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: uip_arch.h,v 1.1.2.2 2003/10/06 15:10:22 adam Exp $ - * - */ - -#ifndef __UIP_ARCH_H__ -#define __UIP_ARCH_H__ - -#include "uip.h" - -/** - * Carry out a 32-bit addition. - * - * Because not all architectures for which uIP is intended has native - * 32-bit arithmetic, uIP uses an external C function for doing the - * required 32-bit additions in the TCP protocol processing. This - * function should add the two arguments and place the result in the - * global variable uip_acc32. - * - * \note The 32-bit integer pointed to by the op32 parameter and the - * result in the uip_acc32 variable are in network byte order (big - * endian). - * - * \param op32 A pointer to a 4-byte array representing a 32-bit - * integer in network byte order (big endian). - * - * \param op16 A 16-bit integer in host byte order. - */ -void uip_add32(u8_t *op32, u16_t op16); - -/** - * Calculate the Internet checksum over a buffer. - * - * The Internet checksum is the one's complement of the one's - * complement sum of all 16-bit words in the buffer. - * - * See RFC1071. - * - * \note This function is not called in the current version of uIP, - * but future versions might make use of it. - * - * \param buf A pointer to the buffer over which the checksum is to be - * computed. - * - * \param len The length of the buffer over which the checksum is to - * be computed. - * - * \return The Internet checksum of the buffer. - */ -u16_t uip_chksum(u16_t *buf, u16_t len); - -/** - * Calculate the IP header checksum of the packet header in uip_buf. - * - * The IP header checksum is the Internet checksum of the 20 bytes of - * the IP header. - * - * \return The IP header checksum of the IP header in the uip_buf - * buffer. - */ -u16_t uip_ipchksum(void); - -/** - * Calculate the TCP checksum of the packet in uip_buf and uip_appdata. - * - * The TCP checksum is the Internet checksum of data contents of the - * TCP segment, and a pseudo-header as defined in RFC793. - * - * \note The uip_appdata pointer that points to the packet data may - * point anywhere in memory, so it is not possible to simply calculate - * the Internet checksum of the contents of the uip_buf buffer. - * - * \return The TCP checksum of the TCP segment in uip_buf and pointed - * to by uip_appdata. - */ -u16_t uip_tcpchksum(void); - -/** @} */ - -#endif /* __UIP_ARCH_H__ */ diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/uip_arp.c b/Demo/uIP_Demo_IAR_ARM7/uip/uip_arp.c deleted file mode 100644 index db8d72d8c..000000000 --- a/Demo/uIP_Demo_IAR_ARM7/uip/uip_arp.c +++ /dev/null @@ -1,429 +0,0 @@ -/** - * \addtogroup uip - * @{ - */ - -/** - * \defgroup uiparp uIP Address Resolution Protocol - * @{ - * - * The Address Resolution Protocol ARP is used for mapping between IP - * addresses and link level addresses such as the Ethernet MAC - * addresses. ARP uses broadcast queries to ask for the link level - * address of a known IP address and the host which is configured with - * the IP address for which the query was meant, will respond with its - * link level address. - * - * \note This ARP implementation only supports Ethernet. - */ - -/** - * \file - * Implementation of the ARP Address Resolution Protocol. - * \author Adam Dunkels - * - */ - -/* - * Copyright (c) 2001-2003, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: uip_arp.c,v 1.7.2.3 2003/10/06 22:42:30 adam Exp $ - * - */ - - -#include "uip_arp.h" - -#include - -struct arp_hdr { - struct uip_eth_hdr ethhdr; - u16_t hwtype; - u16_t protocol; - u8_t hwlen; - u8_t protolen; - u16_t opcode; - struct uip_eth_addr shwaddr; - u16_t sipaddr[2]; - struct uip_eth_addr dhwaddr; - u16_t dipaddr[2]; -}; - -struct ethip_hdr { - struct uip_eth_hdr ethhdr; - /* IP header. */ - u8_t vhl, - tos, - len[2], - ipid[2], - ipoffset[2], - ttl, - proto; - u16_t ipchksum; - u16_t srcipaddr[2], - destipaddr[2]; -}; - -#define ARP_REQUEST 1 -#define ARP_REPLY 2 - -#define ARP_HWTYPE_ETH 1 - -struct arp_entry { - u16_t ipaddr[2]; - struct uip_eth_addr ethaddr; - u8_t time; -}; - -struct uip_eth_addr uip_ethaddr = {{UIP_ETHADDR0, - UIP_ETHADDR1, - UIP_ETHADDR2, - UIP_ETHADDR3, - UIP_ETHADDR4, - UIP_ETHADDR5}}; - -static struct arp_entry arp_table[UIP_ARPTAB_SIZE]; -static u16_t ipaddr[2]; -static u8_t i, c; - -static u8_t arptime; -static u8_t tmpage; - -#define BUF ((struct arp_hdr *)&uip_buf[0]) -#define IPBUF ((struct ethip_hdr *)&uip_buf[0]) -/*-----------------------------------------------------------------------------------*/ -/** - * Initialize the ARP module. - * - */ -/*-----------------------------------------------------------------------------------*/ -void -uip_arp_init(void) -{ - for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { - memset(arp_table[i].ipaddr, 0, 4); - } -} -/*-----------------------------------------------------------------------------------*/ -/** - * Periodic ARP processing function. - * - * This function performs periodic timer processing in the ARP module - * and should be called at regular intervals. The recommended interval - * is 10 seconds between the calls. - * - */ -/*-----------------------------------------------------------------------------------*/ -void -uip_arp_timer(void) -{ - struct arp_entry *tabptr; - - ++arptime; - for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { - tabptr = &arp_table[i]; - if((tabptr->ipaddr[0] | tabptr->ipaddr[1]) != 0 && - arptime - tabptr->time >= UIP_ARP_MAXAGE) { - memset(tabptr->ipaddr, 0, 4); - } - } - -} -/*-----------------------------------------------------------------------------------*/ -static void -uip_arp_update(u16_t *ipaddr, struct uip_eth_addr *ethaddr) -{ - register struct arp_entry *tabptr; - /* Walk through the ARP mapping table and try to find an entry to - update. If none is found, the IP -> MAC address mapping is - inserted in the ARP table. */ - for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { - - tabptr = &arp_table[i]; - /* Only check those entries that are actually in use. */ - if(tabptr->ipaddr[0] != 0 && - tabptr->ipaddr[1] != 0) { - - /* Check if the source IP address of the incoming packet matches - the IP address in this ARP table entry. */ - if(ipaddr[0] == tabptr->ipaddr[0] && - ipaddr[1] == tabptr->ipaddr[1]) { - - /* An old entry found, update this and return. */ - memcpy(tabptr->ethaddr.addr, ethaddr->addr, 6); - tabptr->time = arptime; - - return; - } - } - } - - /* If we get here, no existing ARP table entry was found, so we - create one. */ - - /* First, we try to find an unused entry in the ARP table. */ - for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { - tabptr = &arp_table[i]; - if(tabptr->ipaddr[0] == 0 && - tabptr->ipaddr[1] == 0) { - break; - } - } - - /* If no unused entry is found, we try to find the oldest entry and - throw it away. */ - if(i == UIP_ARPTAB_SIZE) { - tmpage = 0; - c = 0; - for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { - tabptr = &arp_table[i]; - if(arptime - tabptr->time > tmpage) { - tmpage = arptime - tabptr->time; - c = i; - } - } - i = c; - } - - /* Now, i is the ARP table entry which we will fill with the new - information. */ - memcpy(tabptr->ipaddr, ipaddr, 4); - memcpy(tabptr->ethaddr.addr, ethaddr->addr, 6); - tabptr->time = arptime; -} -/*-----------------------------------------------------------------------------------*/ -/** - * ARP processing for incoming IP packets - * - * This function should be called by the device driver when an IP - * packet has been received. The function will check if the address is - * in the ARP cache, and if so the ARP cache entry will be - * refreshed. If no ARP cache entry was found, a new one is created. - * - * This function expects an IP packet with a prepended Ethernet header - * in the uip_buf[] buffer, and the length of the packet in the global - * variable uip_len. - */ -/*-----------------------------------------------------------------------------------*/ -void -uip_arp_ipin(void) -{ - uip_len -= sizeof(struct uip_eth_hdr); - - /* Only insert/update an entry if the source IP address of the - incoming IP packet comes from a host on the local network. */ - if((IPBUF->srcipaddr[0] & uip_arp_netmask[0]) != - (uip_hostaddr[0] & uip_arp_netmask[0])) { - return; - } - if((IPBUF->srcipaddr[1] & uip_arp_netmask[1]) != - (uip_hostaddr[1] & uip_arp_netmask[1])) { - return; - } - uip_arp_update(IPBUF->srcipaddr, &(IPBUF->ethhdr.src)); - - return; -} -/*-----------------------------------------------------------------------------------*/ -/** - * ARP processing for incoming ARP packets. - * - * This function should be called by the device driver when an ARP - * packet has been received. The function will act differently - * depending on the ARP packet type: if it is a reply for a request - * that we previously sent out, the ARP cache will be filled in with - * the values from the ARP reply. If the incoming ARP packet is an ARP - * request for our IP address, an ARP reply packet is created and put - * into the uip_buf[] buffer. - * - * When the function returns, the value of the global variable uip_len - * indicates whether the device driver should send out a packet or - * not. If uip_len is zero, no packet should be sent. If uip_len is - * non-zero, it contains the length of the outbound packet that is - * present in the uip_buf[] buffer. - * - * This function expects an ARP packet with a prepended Ethernet - * header in the uip_buf[] buffer, and the length of the packet in the - * global variable uip_len. - */ -/*-----------------------------------------------------------------------------------*/ -typedef struct arp_hdr aht; - -void -uip_arp_arpin(void) -{ - int ul; - - if(uip_len < sizeof(struct arp_hdr)) { - uip_len = 0; - return; - } - - uip_len = 0; - - switch(BUF->opcode) { - case HTONS(ARP_REQUEST): - /* ARP request. If it asked for our address, we send out a - reply. */ - if(BUF->dipaddr[0] == uip_hostaddr[0] && - BUF->dipaddr[1] == uip_hostaddr[1]) { - /* The reply opcode is 2. */ - BUF->opcode = HTONS(2); - - memcpy(BUF->dhwaddr.addr, BUF->shwaddr.addr, 6); - memcpy(BUF->shwaddr.addr, uip_ethaddr.addr, 6); - memcpy(BUF->ethhdr.src.addr, uip_ethaddr.addr, 6); - memcpy(BUF->ethhdr.dest.addr, BUF->dhwaddr.addr, 6); - - BUF->dipaddr[0] = BUF->sipaddr[0]; - BUF->dipaddr[1] = BUF->sipaddr[1]; - BUF->sipaddr[0] = uip_hostaddr[0]; - BUF->sipaddr[1] = uip_hostaddr[1]; - - ul = BUF->hwlen; - BUF->ethhdr.type = HTONS(UIP_ETHTYPE_ARP); - uip_len = sizeof(struct arp_hdr); - } - break; - case HTONS(ARP_REPLY): - /* ARP reply. We insert or update the ARP table if it was meant - for us. */ - if(BUF->dipaddr[0] == uip_hostaddr[0] && - BUF->dipaddr[1] == uip_hostaddr[1]) { - - uip_arp_update(BUF->sipaddr, &BUF->shwaddr); - } - break; - } - - ( void ) ul; - - return; -} -/*-----------------------------------------------------------------------------------*/ -/** - * Prepend Ethernet header to an outbound IP packet and see if we need - * to send out an ARP request. - * - * This function should be called before sending out an IP packet. The - * function checks the destination IP address of the IP packet to see - * what Ethernet MAC address that should be used as a destination MAC - * address on the Ethernet. - * - * If the destination IP address is in the local network (determined - * by logical ANDing of netmask and our IP address), the function - * checks the ARP cache to see if an entry for the destination IP - * address is found. If so, an Ethernet header is prepended and the - * function returns. If no ARP cache entry is found for the - * destination IP address, the packet in the uip_buf[] is replaced by - * an ARP request packet for the IP address. The IP packet is dropped - * and it is assumed that they higher level protocols (e.g., TCP) - * eventually will retransmit the dropped packet. - * - * If the destination IP address is not on the local network, the IP - * address of the default router is used instead. - * - * When the function returns, a packet is present in the uip_buf[] - * buffer, and the length of the packet is in the global variable - * uip_len. - */ -/*-----------------------------------------------------------------------------------*/ -void -uip_arp_out(void) -{ - struct arp_entry *tabptr; - /* Find the destination IP address in the ARP table and construct - the Ethernet header. If the destination IP addres isn't on the - local network, we use the default router's IP address instead. - - If not ARP table entry is found, we overwrite the original IP - packet with an ARP request for the IP address. */ - - /* Check if the destination address is on the local network. */ - if((IPBUF->destipaddr[0] & uip_arp_netmask[0]) != - (uip_hostaddr[0] & uip_arp_netmask[0]) || - (IPBUF->destipaddr[1] & uip_arp_netmask[1]) != - (uip_hostaddr[1] & uip_arp_netmask[1])) { - /* Destination address was not on the local network, so we need to - use the default router's IP address instead of the destination - address when determining the MAC address. */ - ipaddr[0] = uip_arp_draddr[0]; - ipaddr[1] = uip_arp_draddr[1]; - } else { - /* Else, we use the destination IP address. */ - ipaddr[0] = IPBUF->destipaddr[0]; - ipaddr[1] = IPBUF->destipaddr[1]; - } - - for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { - tabptr = &arp_table[i]; - if(ipaddr[0] == tabptr->ipaddr[0] && - ipaddr[1] == tabptr->ipaddr[1]) - break; - } - - if(i == UIP_ARPTAB_SIZE) { - /* The destination address was not in our ARP table, so we - overwrite the IP packet with an ARP request. */ - - memset(BUF->ethhdr.dest.addr, 0xff, 6); - memset(BUF->dhwaddr.addr, 0x00, 6); - memcpy(BUF->ethhdr.src.addr, uip_ethaddr.addr, 6); - memcpy(BUF->shwaddr.addr, uip_ethaddr.addr, 6); - - BUF->dipaddr[0] = ipaddr[0]; - BUF->dipaddr[1] = ipaddr[1]; - BUF->sipaddr[0] = uip_hostaddr[0]; - BUF->sipaddr[1] = uip_hostaddr[1]; - BUF->opcode = HTONS(ARP_REQUEST); /* ARP request. */ - BUF->hwtype = HTONS(ARP_HWTYPE_ETH); - BUF->protocol = HTONS(UIP_ETHTYPE_IP); - BUF->hwlen = 6; - BUF->protolen = 4; - BUF->ethhdr.type = HTONS(UIP_ETHTYPE_ARP); - - uip_appdata = &uip_buf[40 + UIP_LLH_LEN]; - - uip_len = sizeof(struct arp_hdr); - return; - } - - /* Build an ethernet header. */ - memcpy(IPBUF->ethhdr.dest.addr, tabptr->ethaddr.addr, 6); - memcpy(IPBUF->ethhdr.src.addr, uip_ethaddr.addr, 6); - - IPBUF->ethhdr.type = HTONS(UIP_ETHTYPE_IP); - - uip_len += sizeof(struct uip_eth_hdr); -} -/*-----------------------------------------------------------------------------------*/ - -/** @} */ -/** @} */ diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/uip_arp.h b/Demo/uIP_Demo_IAR_ARM7/uip/uip_arp.h deleted file mode 100644 index fadad57bb..000000000 --- a/Demo/uIP_Demo_IAR_ARM7/uip/uip_arp.h +++ /dev/null @@ -1,201 +0,0 @@ -/** - * \addtogroup uip - * @{ - */ - -/** - * \addtogroup uiparp - * @{ - */ - -/** - * \file - * Macros and definitions for the ARP module. - * \author Adam Dunkels - */ - - -/* - * Copyright (c) 2001-2003, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: uip_arp.h,v 1.3.2.2 2003/10/06 15:10:22 adam Exp $ - * - */ - -#ifndef __UIP_ARP_H__ -#define __UIP_ARP_H__ - -#include "uip.h" - - -/** - * Representation of a 48-bit Ethernet address. - */ -struct uip_eth_addr { - u8_t addr[6]; -} /*_RB_ __attribute__ ((packed, aligned (1))) */; - -extern struct uip_eth_addr uip_ethaddr; - -/** - * The Ethernet header. - */ -struct uip_eth_hdr { - struct uip_eth_addr dest; - struct uip_eth_addr src; - u16_t type; -} /*_RB_ __attribute__ ((packed)) */; - -#define UIP_ETHTYPE_ARP 0x0806 -#define UIP_ETHTYPE_IP 0x0800 -#define UIP_ETHTYPE_IP6 0x86dd - - -/* The uip_arp_init() function must be called before any of the other - ARP functions. */ -void uip_arp_init(void); - -/* The uip_arp_ipin() function should be called whenever an IP packet - arrives from the Ethernet. This function refreshes the ARP table or - inserts a new mapping if none exists. The function assumes that an - IP packet with an Ethernet header is present in the uip_buf buffer - and that the length of the packet is in the uip_len variable. */ -void uip_arp_ipin(void); - -/* The uip_arp_arpin() should be called when an ARP packet is received - by the Ethernet driver. This function also assumes that the - Ethernet frame is present in the uip_buf buffer. When the - uip_arp_arpin() function returns, the contents of the uip_buf - buffer should be sent out on the Ethernet if the uip_len variable - is > 0. */ -void uip_arp_arpin(void); - -/* The uip_arp_out() function should be called when an IP packet - should be sent out on the Ethernet. This function creates an - Ethernet header before the IP header in the uip_buf buffer. The - Ethernet header will have the correct Ethernet MAC destination - address filled in if an ARP table entry for the destination IP - address (or the IP address of the default router) is present. If no - such table entry is found, the IP packet is overwritten with an ARP - request and we rely on TCP to retransmit the packet that was - overwritten. In any case, the uip_len variable holds the length of - the Ethernet frame that should be transmitted. */ -void uip_arp_out(void); - -/* The uip_arp_timer() function should be called every ten seconds. It - is responsible for flushing old entries in the ARP table. */ -void uip_arp_timer(void); - -/** @} */ - -/** - * \addtogroup uipconffunc - * @{ - */ - -/** - * Set the default router's IP address. - * - * \param addr A pointer to a 4-byte array containing the IP address - * of the default router. - * - * \hideinitializer - */ -#define uip_setdraddr(addr) do { uip_arp_draddr[0] = addr[0]; \ - uip_arp_draddr[1] = addr[1]; } while(0) - -/** - * Set the netmask. - * - * \param addr A pointer to a 4-byte array containing the IP address - * of the netmask. - * - * \hideinitializer - */ -#define uip_setnetmask(addr) do { uip_arp_netmask[0] = addr[0]; \ - uip_arp_netmask[1] = addr[1]; } while(0) - - -/** - * Get the default router's IP address. - * - * \param addr A pointer to a 4-byte array that will be filled in with - * the IP address of the default router. - * - * \hideinitializer - */ -#define uip_getdraddr(addr) do { addr[0] = uip_arp_draddr[0]; \ - addr[1] = uip_arp_draddr[1]; } while(0) - -/** - * Get the netmask. - * - * \param addr A pointer to a 4-byte array that will be filled in with - * the value of the netmask. - * - * \hideinitializer - */ -#define uip_getnetmask(addr) do { addr[0] = uip_arp_netmask[0]; \ - addr[1] = uip_arp_netmask[1]; } while(0) - - -/** - * Specifiy the Ethernet MAC address. - * - * The ARP code needs to know the MAC address of the Ethernet card in - * order to be able to respond to ARP queries and to generate working - * Ethernet headers. - * - * \note This macro only specifies the Ethernet MAC address to the ARP - * code. It cannot be used to change the MAC address of the Ethernet - * card. - * - * \param eaddr A pointer to a struct uip_eth_addr containing the - * Ethernet MAC address of the Ethernet card. - * - * \hideinitializer - */ -#define uip_setethaddr(eaddr) do {uip_ethaddr.addr[0] = eaddr.addr[0]; \ - uip_ethaddr.addr[1] = eaddr.addr[1];\ - uip_ethaddr.addr[2] = eaddr.addr[2];\ - uip_ethaddr.addr[3] = eaddr.addr[3];\ - uip_ethaddr.addr[4] = eaddr.addr[4];\ - uip_ethaddr.addr[5] = eaddr.addr[5];} while(0) - -/** @} */ - -/** - * \internal Internal variables that are set using the macros - * uip_setdraddr and uip_setnetmask. - */ -extern u16_t uip_arp_draddr[2], uip_arp_netmask[2]; -#endif /* __UIP_ARP_H__ */ - - diff --git a/Demo/uIP_Demo_IAR_ARM7/uip/uipopt.h b/Demo/uIP_Demo_IAR_ARM7/uip/uipopt.h deleted file mode 100644 index 3701f6294..000000000 --- a/Demo/uIP_Demo_IAR_ARM7/uip/uipopt.h +++ /dev/null @@ -1,560 +0,0 @@ -/** - * \defgroup uipopt Configuration options for uIP - * @{ - * - * uIP is configured using the per-project configuration file - * "uipopt.h". This file contains all compile-time options for uIP and - * should be tweaked to match each specific project. The uIP - * distribution contains a documented example "uipopt.h" that can be - * copied and modified for each project. - */ - -/** - * \file - * Configuration options for uIP. - * \author Adam Dunkels - * - * This file is used for tweaking various configuration options for - * uIP. You should make a copy of this file into one of your project's - * directories instead of editing this example "uipopt.h" file that - * comes with the uIP distribution. - */ - -/* - * Copyright (c) 2001-2003, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: uipopt.h,v 1.16.2.5 2003/10/07 13:22:51 adam Exp $ - * - */ - -#ifndef __UIPOPT_H__ -#define __UIPOPT_H__ - -/*------------------------------------------------------------------------------*/ -/** - * \defgroup uipopttypedef uIP type definitions - * @{ - */ - -/** - * The 8-bit unsigned data type. - * - * This may have to be tweaked for your particular compiler. "unsigned - * char" works for most compilers. - */ -typedef unsigned char u8_t; - -/** - * The 16-bit unsigned data type. - * - * This may have to be tweaked for your particular compiler. "unsigned - * short" works for most compilers. - */ -typedef unsigned short u16_t; - -/** - * The statistics data type. - * - * This datatype determines how high the statistics counters are able - * to count. - */ -typedef unsigned short uip_stats_t; - -/** @} */ - -/*------------------------------------------------------------------------------*/ - -/** - * \defgroup uipoptstaticconf Static configuration options - * @{ - * - * These configuration options can be used for setting the IP address - * settings statically, but only if UIP_FIXEDADDR is set to 1. The - * configuration options for a specific node includes IP address, - * netmask and default router as well as the Ethernet address. The - * netmask, default router and Ethernet address are appliciable only - * if uIP should be run over Ethernet. - * - * All of these should be changed to suit your project. -*/ - -/** - * Determines if uIP should use a fixed IP address or not. - * - * If uIP should use a fixed IP address, the settings are set in the - * uipopt.h file. If not, the macros uip_sethostaddr(), - * uip_setdraddr() and uip_setnetmask() should be used instead. - * - * \hideinitializer - */ -#define UIP_FIXEDADDR 1 - -/** - * Ping IP address asignment. - * - * uIP uses a "ping" packets for setting its own IP address if this - * option is set. If so, uIP will start with an empty IP address and - * the destination IP address of the first incoming "ping" (ICMP echo) - * packet will be used for setting the hosts IP address. - * - * \note This works only if UIP_FIXEDADDR is 0. - * - * \hideinitializer - */ -#define UIP_PINGADDRCONF 0 - - -#define UIP_IPADDR0 172U /**< The first octet of the IP address of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_IPADDR1 25U /**< The second octet of the IP address of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_IPADDR2 218U /**< The third octet of the IP address of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_IPADDR3 204U /**< The fourth octet of the IP address of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ - -#define UIP_NETMASK0 255 /**< The first octet of the netmask of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_NETMASK1 255 /**< The second octet of the netmask of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_NETMASK2 0 /**< The third octet of the netmask of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_NETMASK3 0 /**< The fourth octet of the netmask of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ - -#define UIP_DRIPADDR0 172 /**< The first octet of the IP address of - the default router, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_DRIPADDR1 25 /**< The second octet of the IP address of - the default router, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_DRIPADDR2 218 /**< The third octet of the IP address of - the default router, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_DRIPADDR3 3 /**< The fourth octet of the IP address of - the default router, if UIP_FIXEDADDR is - 1. \hideinitializer */ - - - -/** - * Specifies if the uIP ARP module should be compiled with a fixed - * Ethernet MAC address or not. - * - * If this configuration option is 0, the macro uip_setethaddr() can - * be used to specify the Ethernet address at run-time. - * - * \hideinitializer - */ -#define UIP_FIXEDETHADDR 0 - -#define UIP_ETHADDR0 0x00 /**< The first octet of the Ethernet - address if UIP_FIXEDETHADDR is - 1. \hideinitializer */ -#define UIP_ETHADDR1 0xbd /**< The second octet of the Ethernet - address if UIP_FIXEDETHADDR is - 1. \hideinitializer */ -#define UIP_ETHADDR2 0x3b /**< The third octet of the Ethernet - address if UIP_FIXEDETHADDR is - 1. \hideinitializer */ -#define UIP_ETHADDR3 0x33 /**< The fourth octet of the Ethernet - address if UIP_FIXEDETHADDR is - 1. \hideinitializer */ -#define UIP_ETHADDR4 0x06 /**< The fifth octet of the Ethernet - address if UIP_FIXEDETHADDR is - 1. \hideinitializer */ -#define UIP_ETHADDR5 0x65 /**< The sixth octet of the Ethernet - address if UIP_FIXEDETHADDR is - 1. \hideinitializer */ - -/** @} */ -/*------------------------------------------------------------------------------*/ -/** - * \defgroup uipoptip IP configuration options - * @{ - * - */ -/** - * The IP TTL (time to live) of IP packets sent by uIP. - * - * This should normally not be changed. - */ -#define UIP_TTL 255 - -/** - * Turn on support for IP packet reassembly. - * - * uIP supports reassembly of fragmented IP packets. This features - * requires an additonal amount of RAM to hold the reassembly buffer - * and the reassembly code size is approximately 700 bytes. The - * reassembly buffer is of the same size as the uip_buf buffer - * (configured by UIP_BUFSIZE). - * - * \note IP packet reassembly is not heavily tested. - * - * \hideinitializer - */ -#define UIP_REASSEMBLY 0 - -/** - * The maximum time an IP fragment should wait in the reassembly - * buffer before it is dropped. - * - */ -#define UIP_REASS_MAXAGE 40 - -/** @} */ - -/*------------------------------------------------------------------------------*/ -/** - * \defgroup uipoptudp UDP configuration options - * @{ - * - * \note The UDP support in uIP is still not entirely complete; there - * is no support for sending or receiving broadcast or multicast - * packets, but it works well enough to support a number of vital - * applications such as DNS queries, though - */ - -/** - * Toggles wether UDP support should be compiled in or not. - * - * \hideinitializer - */ -#define UIP_UDP 0 - -/** - * Toggles if UDP checksums should be used or not. - * - * \note Support for UDP checksums is currently not included in uIP, - * so this option has no function. - * - * \hideinitializer - */ -#define UIP_UDP_CHECKSUMS 0 - -/** - * The maximum amount of concurrent UDP connections. - * - * \hideinitializer - */ -#define UIP_UDP_CONNS 2 - -/** - * The name of the function that should be called when UDP datagrams arrive. - * - * \hideinitializer - */ -#define UIP_UDP_APPCALL udp_appcall - -/** @} */ -/*------------------------------------------------------------------------------*/ -/** - * \defgroup uipopttcp TCP configuration options - * @{ - */ - -/** - * Determines if support for opening connections from uIP should be - * compiled in. - * - * If the applications that are running on top of uIP for this project - * do not need to open outgoing TCP connections, this configration - * option can be turned off to reduce the code size of uIP. - * - * \hideinitializer - */ -#define UIP_ACTIVE_OPEN 0 - -/** - * The maximum number of simultaneously open TCP connections. - * - * Since the TCP connections are statically allocated, turning this - * configuration knob down results in less RAM used. Each TCP - * connection requires approximatly 30 bytes of memory. - * - * \hideinitializer - */ -#define UIP_CONNS 25 - -/** - * The maximum number of simultaneously listening TCP ports. - * - * Each listening TCP port requires 2 bytes of memory. - * - * \hideinitializer - */ -#define UIP_LISTENPORTS 10 - -/** - * The size of the advertised receiver's window. - * - * Should be set low (i.e., to the size of the uip_buf buffer) is the - * application is slow to process incoming data, or high (32768 bytes) - * if the application processes data quickly. - * - * \hideinitializer - */ -#define UIP_RECEIVE_WINDOW 32768 - -/** - * Determines if support for TCP urgent data notification should be - * compiled in. - * - * Urgent data (out-of-band data) is a rarely used TCP feature that - * very seldom would be required. - * - * \hideinitializer - */ -#define UIP_URGDATA 1 - -/** - * The initial retransmission timeout counted in timer pulses. - * - * This should not be changed. - */ -#define UIP_RTO 3 - -/** - * The maximum number of times a segment should be retransmitted - * before the connection should be aborted. - * - * This should not be changed. - */ -#define UIP_MAXRTX 8 - -/** - * The maximum number of times a SYN segment should be retransmitted - * before a connection request should be deemed to have been - * unsuccessful. - * - * This should not need to be changed. - */ -#define UIP_MAXSYNRTX 3 - -/** - * The TCP maximum segment size. - * - * This is should not be to set to more than UIP_BUFSIZE - UIP_LLH_LEN - 40. - */ -#define UIP_TCP_MSS (UIP_BUFSIZE - UIP_LLH_LEN - 40) - -/** - * How long a connection should stay in the TIME_WAIT state. - * - * This configiration option has no real implication, and it should be - * left untouched. - */ -#define UIP_TIME_WAIT_TIMEOUT 120 - - -/** @} */ -/*------------------------------------------------------------------------------*/ -/** - * \defgroup uipoptarp ARP configuration options - * @{ - */ - -/** - * The size of the ARP table. - * - * This option should be set to a larger value if this uIP node will - * have many connections from the local network. - * - * \hideinitializer - */ -#define UIP_ARPTAB_SIZE 8 - -/** - * The maxium age of ARP table entries measured in 10ths of seconds. - * - * An UIP_ARP_MAXAGE of 120 corresponds to 20 minutes (BSD - * default). - */ -#define UIP_ARP_MAXAGE 120 - -/** @} */ - -/*------------------------------------------------------------------------------*/ - -/** - * \defgroup uipoptgeneral General configuration options - * @{ - */ - -/** - * The size of the uIP packet buffer. - * - * The uIP packet buffer should not be smaller than 60 bytes, and does - * not need to be larger than 1500 bytes. Lower size results in lower - * TCP throughput, larger size results in higher TCP throughput. - * - * \hideinitializer - */ -#define UIP_BUFSIZE 2048 - - -/** - * Determines if statistics support should be compiled in. - * - * The statistics is useful for debugging and to show the user. - * - * \hideinitializer - */ -#define UIP_STATISTICS 1 - -/** - * Determines if logging of certain events should be compiled in. - * - * This is useful mostly for debugging. The function uip_log() - * must be implemented to suit the architecture of the project, if - * logging is turned on. - * - * \hideinitializer - */ -#define UIP_LOGGING 0 - -/** - * Print out a uIP log message. - * - * This function must be implemented by the module that uses uIP, and - * is called by uIP whenever a log message is generated. - */ -void uip_log(char *msg); - -/** - * The link level header length. - * - * This is the offset into the uip_buf where the IP header can be - * found. For Ethernet, this should be set to 14. For SLIP, this - * should be set to 0. - * - * \hideinitializer - */ -#define UIP_LLH_LEN 14 - - -/** @} */ -/*------------------------------------------------------------------------------*/ -/** - * \defgroup uipoptcpu CPU architecture configuration - * @{ - * - * The CPU architecture configuration is where the endianess of the - * CPU on which uIP is to be run is specified. Most CPUs today are - * little endian, and the most notable exception are the Motorolas - * which are big endian. The BYTE_ORDER macro should be changed to - * reflect the CPU architecture on which uIP is to be run. - */ -#ifndef LITTLE_ENDIAN -#define LITTLE_ENDIAN 3412 -#endif /* LITTLE_ENDIAN */ -#ifndef BIG_ENDIAN -#define BIG_ENDIAN 1234 -#endif /* BIGE_ENDIAN */ - -/** - * The byte order of the CPU architecture on which uIP is to be run. - * - * This option can be either BIG_ENDIAN (Motorola byte order) or - * LITTLE_ENDIAN (Intel byte order). - * - * \hideinitializer - */ -#ifndef BYTE_ORDER -#define BYTE_ORDER LITTLE_ENDIAN -#endif /* BYTE_ORDER */ - -/** @} */ -/*------------------------------------------------------------------------------*/ - -/** - * \defgroup uipoptapp Appication specific configurations - * @{ - * - * An uIP application is implemented using a single application - * function that is called by uIP whenever a TCP/IP event occurs. The - * name of this function must be registered with uIP at compile time - * using the UIP_APPCALL definition. - * - * uIP applications can store the application state within the - * uip_conn structure by specifying the size of the application - * structure with the UIP_APPSTATE_SIZE macro. - * - * The file containing the definitions must be included in the - * uipopt.h file. - * - * The following example illustrates how this can look. - \code - -void httpd_appcall(void); -#define UIP_APPCALL httpd_appcall - -struct httpd_state { - u8_t state; - u16_t count; - char *dataptr; - char *script; -}; -#define UIP_APPSTATE_SIZE (sizeof(struct httpd_state)) - \endcode - */ - -/** - * \var #define UIP_APPCALL - * - * The name of the application function that uIP should call in - * response to TCP/IP events. - * - */ - -/** - * \var #define UIP_APPSTATE_SIZE - * - * The size of the application state that is to be stored in the - * uip_conn structure. - */ -/** @} */ - -/* Include the header file for the application program that should be - used. If you don't use the example web server, you should change - this. */ -#include "httpd.h" - - -#endif /* __UIPOPT_H__ */ diff --git a/Demo/uIP_Demo_Rowley_ARM7/FreeRTOSConfig.h b/Demo/uIP_Demo_Rowley_ARM7/FreeRTOSConfig.h deleted file mode 100644 index e74f16dc6..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/FreeRTOSConfig.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -#include -#define vPortYieldProcessor swi_handler - - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 58982400 ) /* =14.7456MHz xtal multiplied by 4 using the PLL. */ -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 10 * 1024 ) ) -#define configMAX_TASK_NAME_LEN ( 16 ) -#define configUSE_TRACE_FACILITY 1 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 1 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/uIP_Demo_Rowley_ARM7/Philips_LPC210X_Startup.s b/Demo/uIP_Demo_Rowley_ARM7/Philips_LPC210X_Startup.s deleted file mode 100644 index 47debb720..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/Philips_LPC210X_Startup.s +++ /dev/null @@ -1,213 +0,0 @@ -/***************************************************************************** - * Copyright (c) 2001, 2002 Rowley Associates Limited. * - * * - * This file may be distributed under the terms of the License Agreement * - * provided with this software. * - * * - * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE * - * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * - *****************************************************************************/ - -/***************************************************************************** - * Preprocessor Definitions - * ------------------------ - * - * VECTORED_IRQ_INTERRUPTS - * - * Enable vectored IRQ interrupts. If defined, the PC register will be loaded - * with the contents of the VICVectAddr register on an IRQ exception. - * - * USE_PLL - * - * If defined, connect PLL as processor clock source. If undefined, the - * oscillator clock will be used. - * - * PLLCFG_VAL - * - * Override the default PLL configuration (multiplier = 5, divider = 2) - * by defining PLLCFG_VAL. - * - * USE_MAM - * - * If defined then the memory accelerator module (MAM) will be enabled. - * - * MAMCR_VAL & MAMTIM_VAL - * - * Override the default MAM configuration (fully enabled, 3 fetch cycles) - * by defining MAMCR_VAL and MAMTIM_VAL. - * - * VPBDIV_VAL - * - * If defined then this value will be used to configure the VPB divider. - * - * SRAM_EXCEPTIONS - * - * If defined, enable copying and re-mapping of interrupt vectors from User - * FLASH to SRAM. If undefined, interrupt vectors will be mapped in User - * FLASH. - * - *****************************************************************************/ - -#ifndef PLLCFG_VAL -#define PLLCFG_VAL 0x24 -#endif - -#ifndef MAMCR_VAL -#define MAMCR_VAL 2 -#endif - -#ifndef MAMTIM_VAL -#define MAMTIM_VAL 3 -#endif - -#define MAMCR_OFFS 0x000 -#define MAMTIM_OFFS 0x004 - -#define PLLCON_OFFS 0x080 -#define PLLCFG_OFFS 0x084 -#define PLLSTAT_OFFS 0x088 -#define PLLFEED_OFFS 0x08C - -#define VPBDIV_OFFS 0x100 - - .section .vectors, "ax" - .code 32 - .align 0 - -/***************************************************************************** - * Exception Vectors * - *****************************************************************************/ -_vectors: - ldr pc, [pc, #reset_handler_address - . - 8] /* reset */ - ldr pc, [pc, #undef_handler_address - . - 8] /* undefined instruction */ - ldr pc, [pc, #swi_handler_address - . - 8] /* swi handler */ - ldr pc, [pc, #pabort_handler_address - . - 8] /* abort prefetch */ - ldr pc, [pc, #dabort_handler_address - . - 8] /* abort data */ -#ifdef VECTORED_IRQ_INTERRUPTS - .word 0xB9205F84 /* boot loader checksum */ - ldr pc, [pc, #-0xFF0] /* irq handler */ -#else - .word 0xB8A06F60 /* boot loader checksum */ - ldr pc, [pc, #irq_handler_address - . - 8] /* irq handler */ -#endif - ldr pc, [pc, #fiq_handler_address - . - 8] /* fiq handler */ - -reset_handler_address: - .word reset_handler -undef_handler_address: - .word undef_handler -swi_handler_address: - .word swi_handler -pabort_handler_address: - .word pabort_handler -dabort_handler_address: - .word dabort_handler -irq_handler_address: - .word irq_handler -fiq_handler_address: - .word fiq_handler - - .section .init, "ax" - .code 32 - .align 0 - -/****************************************************************************** - * * - * Default exception handlers * - * * - ******************************************************************************/ - -reset_handler: -#if defined(USE_PLL) || defined(USE_MAM) || defined(VPBDIV_VAL) - ldr r0, =0xE01FC000 -#endif -#if defined(USE_PLL) - /* Configure PLL Multiplier/Divider */ - ldr r1, =PLLCFG_VAL - str r1, [r0, #PLLCFG_OFFS] - /* Enable PLL */ - mov r1, #0x1 - str r1, [r0, #PLLCON_OFFS] - mov r1, #0xAA - str r1, [r0, #PLLFEED_OFFS] - mov r1, #0x55 - str r1, [r0, #PLLFEED_OFFS] - /* Wait for PLL to lock */ -pll_lock_loop: - ldr r1, [r0, #PLLSTAT_OFFS] - tst r1, #0x400 - beq pll_lock_loop - /* PLL Locked, connect PLL as clock source */ - mov r1, #0x3 - str r1, [r0, #PLLCON_OFFS] - mov r1, #0xAA - str r1, [r0, #PLLFEED_OFFS] - mov r1, #0x55 - str r1, [r0, #PLLFEED_OFFS] -#endif - -#if defined(USE_MAM) - mov r1, #0 - str r1, [r0, #MAMCR_OFFS] - ldr r1, =MAMTIM_VAL - str r1, [r0, #MAMTIM_OFFS] - ldr r1, =MAMCR_VAL - str r1, [r0, #MAMCR_OFFS] -#endif - -#if defined(VPBDIV_VAL) - ldr r1, =VPBDIV_VAL - str r1, [r0, #VPBDIV_OFFS] -#endif - -#if defined(SRAM_EXCEPTIONS) - /* Copy exception vectors into SRAM */ - mov r8, #0x40000000 - ldr r9, =_vectors - ldmia r9!, {r0-r7} - stmia r8!, {r0-r7} - ldmia r9!, {r0-r6} - stmia r8!, {r0-r6} - - /* Re-map interrupt vectors from SRAM */ - ldr r0, MEMMAP - mov r1, #2 /* User RAM Mode. Interrupt vectors are re-mapped from SRAM */ - str r1, [r0] -#endif /* SRAM_EXCEPTIONS */ - - b _start - -#ifdef SRAM_EXCEPTIONS -MEMMAP: - .word 0xE01FC040 -#endif - -/****************************************************************************** - * * - * Default exception handlers * - * These are declared weak symbols so they can be redefined in user code. * - * * - ******************************************************************************/ - -undef_handler: - b undef_handler - -swi_handler: - b swi_handler - -pabort_handler: - b pabort_handler - -dabort_handler: - b dabort_handler - -irq_handler: - b irq_handler - -fiq_handler: - b fiq_handler - - .weak undef_handler, swi_handler, pabort_handler, dabort_handler, irq_handler, fiq_handler - - - diff --git a/Demo/uIP_Demo_Rowley_ARM7/flash_placement.xml b/Demo/uIP_Demo_Rowley_ARM7/flash_placement.xml deleted file mode 100644 index 449adf2e4..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/flash_placement.xml +++ /dev/null @@ -1,29 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Demo/uIP_Demo_Rowley_ARM7/lpc210x.h b/Demo/uIP_Demo_Rowley_ARM7/lpc210x.h deleted file mode 100644 index 3f1e3042d..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/lpc210x.h +++ /dev/null @@ -1,321 +0,0 @@ -#ifndef lpc210x_h -#define lpc210x_h -/******************************************************************************* -lpc210x.h - Register defs for Philips LPC210X: LPC2104, LPC2105 and LPC2106 - - -THE SOFTWARE IS DELIVERED "AS IS" WITHOUT WARRANTY OR CONDITION OF ANY KIND, -EITHER EXPRESS, IMPLIED OR STATUTORY. THIS INCLUDES WITHOUT LIMITATION ANY -WARRANTY OR CONDITION WITH RESPECT TO MERCHANTABILITY OR FITNESS FOR ANY -PARTICULAR PURPOSE, OR AGAINST THE INFRINGEMENTS OF INTELLECTUAL PROPERTY RIGHTS -OF OTHERS. - -This file may be freely used for commercial and non-commercial applications, -including being redistributed with any tools. - -If you find a problem with the file, please report it so that it can be fixed. - -Created by Sten Larsson (sten_larsson at yahoo com) - -Edited by Richard Barry. -*******************************************************************************/ - -#define REG8 (volatile unsigned char*) -#define REG16 (volatile unsigned short*) -#define REG32 (volatile unsigned int*) - - -/*############################################################################## -## MISC -##############################################################################*/ - - /* Constants for data to put in IRQ/FIQ Exception Vectors */ -#define VECTDATA_IRQ 0xE51FFFF0 /* LDR PC,[PC,#-0xFF0] */ -#define VECTDATA_FIQ /* __TODO */ - - -/*############################################################################## -## VECTORED INTERRUPT CONTROLLER -##############################################################################*/ - -#define VICIRQStatus (*(REG32 (0xFFFFF000))) -#define VICFIQStatus (*(REG32 (0xFFFFF004))) -#define VICRawIntr (*(REG32 (0xFFFFF008))) -#define VICIntSelect (*(REG32 (0xFFFFF00C))) -#define VICIntEnable (*(REG32 (0xFFFFF010))) -#define VICIntEnClear (*(REG32 (0xFFFFF014))) -#define VICSoftInt (*(REG32 (0xFFFFF018))) -#define VICSoftIntClear (*(REG32 (0xFFFFF01C))) -#define VICProtection (*(REG32 (0xFFFFF020))) -#define VICVectAddr (*(REG32 (0xFFFFF030))) -#define VICDefVectAddr (*(REG32 (0xFFFFF034))) - -#define VICVectAddr0 (*(REG32 (0xFFFFF100))) -#define VICVectAddr1 (*(REG32 (0xFFFFF104))) -#define VICVectAddr2 (*(REG32 (0xFFFFF108))) -#define VICVectAddr3 (*(REG32 (0xFFFFF10C))) -#define VICVectAddr4 (*(REG32 (0xFFFFF110))) -#define VICVectAddr5 (*(REG32 (0xFFFFF114))) -#define VICVectAddr6 (*(REG32 (0xFFFFF118))) -#define VICVectAddr7 (*(REG32 (0xFFFFF11C))) -#define VICVectAddr8 (*(REG32 (0xFFFFF120))) -#define VICVectAddr9 (*(REG32 (0xFFFFF124))) -#define VICVectAddr10 (*(REG32 (0xFFFFF128))) -#define VICVectAddr11 (*(REG32 (0xFFFFF12C))) -#define VICVectAddr12 (*(REG32 (0xFFFFF130))) -#define VICVectAddr13 (*(REG32 (0xFFFFF134))) -#define VICVectAddr14 (*(REG32 (0xFFFFF138))) -#define VICVectAddr15 (*(REG32 (0xFFFFF13C))) - -#define VICVectCntl0 (*(REG32 (0xFFFFF200))) -#define VICVectCntl1 (*(REG32 (0xFFFFF204))) -#define VICVectCntl2 (*(REG32 (0xFFFFF208))) -#define VICVectCntl3 (*(REG32 (0xFFFFF20C))) -#define VICVectCntl4 (*(REG32 (0xFFFFF210))) -#define VICVectCntl5 (*(REG32 (0xFFFFF214))) -#define VICVectCntl6 (*(REG32 (0xFFFFF218))) -#define VICVectCntl7 (*(REG32 (0xFFFFF21C))) -#define VICVectCntl8 (*(REG32 (0xFFFFF220))) -#define VICVectCntl9 (*(REG32 (0xFFFFF224))) -#define VICVectCntl10 (*(REG32 (0xFFFFF228))) -#define VICVectCntl11 (*(REG32 (0xFFFFF22C))) -#define VICVectCntl12 (*(REG32 (0xFFFFF230))) -#define VICVectCntl13 (*(REG32 (0xFFFFF234))) -#define VICVectCntl14 (*(REG32 (0xFFFFF238))) -#define VICVectCntl15 (*(REG32 (0xFFFFF23C))) - -#define VICITCR (*(REG32 (0xFFFFF300))) -#define VICITIP1 (*(REG32 (0xFFFFF304))) -#define VICITIP2 (*(REG32 (0xFFFFF308))) -#define VICITOP1 (*(REG32 (0xFFFFF30C))) -#define VICITOP2 (*(REG32 (0xFFFFF310))) -#define VICPeriphID0 (*(REG32 (0xFFFFFFE0))) -#define VICPeriphID1 (*(REG32 (0xFFFFFFE4))) -#define VICPeriphID2 (*(REG32 (0xFFFFFFE8))) -#define VICPeriphID3 (*(REG32 (0xFFFFFFEC))) - -#define VICIntEnClr VICIntEnClear -#define VICSoftIntClr VICSoftIntClear - - -/*############################################################################## -## PCB - Pin Connect Block -##############################################################################*/ - -#define PCB_PINSEL0 (*(REG32 (0xE002C000))) -#define PCB_PINSEL1 (*(REG32 (0xE002C004))) - - -/*############################################################################## -## GPIO - General Purpose I/O -##############################################################################*/ - -#define GPIO_IOPIN (*(REG32 (0xE0028000))) /* ALTERNATE NAME GPIO = GPIO0 */ -#define GPIO_IOSET (*(REG32 (0xE0028004))) -#define GPIO_IODIR (*(REG32 (0xE0028008))) -#define GPIO_IOCLR (*(REG32 (0xE002800C))) - -#define GPIO0_IOPIN (*(REG32 (0xE0028000))) /* ALTERNATE NAME GPIO = GPIO0 */ -#define GPIO0_IOSET (*(REG32 (0xE0028004))) -#define GPIO0_IODIR (*(REG32 (0xE0028008))) -#define GPIO0_IOCLR (*(REG32 (0xE002800C))) - - -/*############################################################################## -## UART0 / UART1 -##############################################################################*/ - -/* ---- UART 0 --------------------------------------------- */ -#define UART0_RBR (*(REG32 (0xE000C000))) -#define UART0_THR (*(REG32 (0xE000C000))) -#define UART0_IER (*(REG32 (0xE000C004))) -#define UART0_IIR (*(REG32 (0xE000C008))) -#define UART0_FCR (*(REG32 (0xE000C008))) -#define UART0_LCR (*(REG32 (0xE000C00C))) -#define UART0_LSR (*(REG32 (0xE000C014))) -#define UART0_SCR (*(REG32 (0xE000C01C))) -#define UART0_DLL (*(REG32 (0xE000C000))) -#define UART0_DLM (*(REG32 (0xE000C004))) - -/* ---- UART 1 --------------------------------------------- */ -#define UART1_RBR (*(REG32 (0xE0010000))) -#define UART1_THR (*(REG32 (0xE0010000))) -#define UART1_IER (*(REG32 (0xE0010004))) -#define UART1_IIR (*(REG32 (0xE0010008))) -#define UART1_FCR (*(REG32 (0xE0010008))) -#define UART1_LCR (*(REG32 (0xE001000C))) -#define UART1_LSR (*(REG32 (0xE0010014))) -#define UART1_SCR (*(REG32 (0xE001001C))) -#define UART1_DLL (*(REG32 (0xE0010000))) -#define UART1_DLM (*(REG32 (0xE0010004))) -#define UART1_MCR (*(REG32 (0xE0010010))) -#define UART1_MSR (*(REG32 (0xE0010018))) - - -/*############################################################################## -## I2C -##############################################################################*/ - -#define I2C_I2CONSET (*(REG32 (0xE001C000))) -#define I2C_I2STAT (*(REG32 (0xE001C004))) -#define I2C_I2DAT (*(REG32 (0xE001C008))) -#define I2C_I2ADR (*(REG32 (0xE001C00C))) -#define I2C_I2SCLH (*(REG32 (0xE001C010))) -#define I2C_I2SCLL (*(REG32 (0xE001C014))) -#define I2C_I2CONCLR (*(REG32 (0xE001C018))) - - -/*############################################################################## -## SPI - Serial Peripheral Interface -##############################################################################*/ - -#define SPI_SPCR (*(REG32 (0xE0020000))) -#define SPI_SPSR (*(REG32 (0xE0020004))) -#define SPI_SPDR (*(REG32 (0xE0020008))) -#define SPI_SPCCR (*(REG32 (0xE002000C))) -#define SPI_SPTCR (*(REG32 (0xE0020010))) -#define SPI_SPTSR (*(REG32 (0xE0020014))) -#define SPI_SPTOR (*(REG32 (0xE0020018))) -#define SPI_SPINT (*(REG32 (0xE002001C))) - - -/*############################################################################## -## Timer 0 and Timer 1 -##############################################################################*/ - -/* ---- Timer 0 -------------------------------------------- */ -#define T0_IR (*(REG32 (0xE0004000))) -#define T0_TCR (*(REG32 (0xE0004004))) -#define T0_TC (*(REG32 (0xE0004008))) -#define T0_PR (*(REG32 (0xE000400C))) -#define T0_PC (*(REG32 (0xE0004010))) -#define T0_MCR (*(REG32 (0xE0004014))) -#define T0_MR0 (*(REG32 (0xE0004018))) -#define T0_MR1 (*(REG32 (0xE000401C))) -#define T0_MR2 (*(REG32 (0xE0004020))) -#define T0_MR3 (*(REG32 (0xE0004024))) -#define T0_CCR (*(REG32 (0xE0004028))) -#define T0_CR0 (*(REG32 (0xE000402C))) -#define T0_CR1 (*(REG32 (0xE0004030))) -#define T0_CR2 (*(REG32 (0xE0004034))) -#define T0_CR3 (*(REG32 (0xE0004038))) -#define T0_EMR (*(REG32 (0xE000403C))) - -/* ---- Timer 1 -------------------------------------------- */ -#define T1_IR (*(REG32 (0xE0008000))) -#define T1_TCR (*(REG32 (0xE0008004))) -#define T1_TC (*(REG32 (0xE0008008))) -#define T1_PR (*(REG32 (0xE000800C))) -#define T1_PC (*(REG32 (0xE0008010))) -#define T1_MCR (*(REG32 (0xE0008014))) -#define T1_MR0 (*(REG32 (0xE0008018))) -#define T1_MR1 (*(REG32 (0xE000801C))) -#define T1_MR2 (*(REG32 (0xE0008020))) -#define T1_MR3 (*(REG32 (0xE0008024))) -#define T1_CCR (*(REG32 (0xE0008028))) -#define T1_CR0 (*(REG32 (0xE000802C))) -#define T1_CR1 (*(REG32 (0xE0008030))) -#define T1_CR2 (*(REG32 (0xE0008034))) -#define T1_CR3 (*(REG32 (0xE0008038))) -#define T1_EMR (*(REG32 (0xE000803C))) - - -/*############################################################################## -## PWM -##############################################################################*/ - -#define PWM_IR (*(REG32 (0xE0014000))) -#define PWM_TCR (*(REG32 (0xE0014004))) -#define PWM_TC (*(REG32 (0xE0014008))) -#define PWM_PR (*(REG32 (0xE001400C))) -#define PWM_PC (*(REG32 (0xE0014010))) -#define PWM_MCR (*(REG32 (0xE0014014))) -#define PWM_MR0 (*(REG32 (0xE0014018))) -#define PWM_MR1 (*(REG32 (0xE001401C))) -#define PWM_MR2 (*(REG32 (0xE0014020))) -#define PWM_MR3 (*(REG32 (0xE0014024))) -#define PWM_MR4 (*(REG32 (0xE0014040))) -#define PWM_MR5 (*(REG32 (0xE0014044))) -#define PWM_MR6 (*(REG32 (0xE0014048))) -#define PWM_EMR (*(REG32 (0xE001403C))) -#define PWM_PCR (*(REG32 (0xE001404C))) -#define PWM_LER (*(REG32 (0xE0014050))) -#define PWM_CCR (*(REG32 (0xE0014028))) -#define PWM_CR0 (*(REG32 (0xE001402C))) -#define PWM_CR1 (*(REG32 (0xE0014030))) -#define PWM_CR2 (*(REG32 (0xE0014034))) -#define PWM_CR3 (*(REG32 (0xE0014038))) - -/*############################################################################## -## RTC -##############################################################################*/ - -/* ---- RTC: Miscellaneous Register Group ------------------ */ -#define RTC_ILR (*(REG32 (0xE0024000))) -#define RTC_CTC (*(REG32 (0xE0024004))) -#define RTC_CCR (*(REG32 (0xE0024008))) -#define RTC_CIIR (*(REG32 (0xE002400C))) -#define RTC_AMR (*(REG32 (0xE0024010))) -#define RTC_CTIME0 (*(REG32 (0xE0024014))) -#define RTC_CTIME1 (*(REG32 (0xE0024018))) -#define RTC_CTIME2 (*(REG32 (0xE002401C))) - -/* ---- RTC: Timer Control Group --------------------------- */ -#define RTC_SEC (*(REG32 (0xE0024020))) -#define RTC_MIN (*(REG32 (0xE0024024))) -#define RTC_HOUR (*(REG32 (0xE0024028))) -#define RTC_DOM (*(REG32 (0xE002402C))) -#define RTC_DOW (*(REG32 (0xE0024030))) -#define RTC_DOY (*(REG32 (0xE0024034))) -#define RTC_MONTH (*(REG32 (0xE0024038))) -#define RTC_YEAR (*(REG32 (0xE002403C))) - -/* ---- RTC: Alarm Control Group --------------------------- */ -#define RTC_ALSEC (*(REG32 (0xE0024060))) -#define RTC_ALMIN (*(REG32 (0xE0024064))) -#define RTC_ALHOUR (*(REG32 (0xE0024068))) -#define RTC_ALDOM (*(REG32 (0xE002406C))) -#define RTC_ALDOW (*(REG32 (0xE0024070))) -#define RTC_ALDOY (*(REG32 (0xE0024074))) -#define RTC_ALMON (*(REG32 (0xE0024078))) -#define RTC_ALYEAR (*(REG32 (0xE002407C))) - -/* ---- RTC: Reference Clock Divider Group ----------------- */ -#define RTC_PREINT (*(REG32 (0xE0024080))) -#define RTC_PREFRAC (*(REG32 (0xE0024084))) - - -/*############################################################################## -## WD - Watchdog -##############################################################################*/ - -#define WD_WDMOD (*(REG32 (0xE0000000))) -#define WD_WDTC (*(REG32 (0xE0000004))) -#define WD_WDFEED (*(REG32 (0xE0000008))) -#define WD_WDTV (*(REG32 (0xE000000C))) - - -/*############################################################################## -## System Control Block -##############################################################################*/ - -#define SCB_EXTINT (*(REG32 (0xE01FC140))) -#define SCB_EXTWAKE (*(REG32 (0xE01FC144))) -#define SCB_MEMMAP (*(REG32 (0xE01FC040))) -#define SCB_PLLCON (*(REG32 (0xE01FC080))) -#define SCB_PLLCFG (*(REG32 (0xE01FC084))) -#define SCB_PLLSTAT (*(REG32 (0xE01FC088))) -#define SCB_PLLFEED (*(REG32 (0xE01FC08C))) -#define SCB_PCON (*(REG32 (0xE01FC0C0))) -#define SCB_PCONP (*(REG32 (0xE01FC0C4))) -#define SCB_VPBDIV (*(REG32 (0xE01FC100))) - -/*############################################################################## -## Memory Accelerator Module (MAM) -##############################################################################*/ - -#define MAM_TIM (*(REG32 (0xE01FC004))) -#define MAM_CR (*(REG32 (0xE01FC000))) - -#endif /* lpc210x_h */ - diff --git a/Demo/uIP_Demo_Rowley_ARM7/main.c b/Demo/uIP_Demo_Rowley_ARM7/main.c deleted file mode 100644 index b0221d707..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/main.c +++ /dev/null @@ -1,284 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. - The processor MUST be in supervisor mode when vTaskStartScheduler is - called. The demo applications included in the FreeRTOS.org download switch - to supervisor mode prior to main being called. If you are not using one of - these demo application projects then ensure Supervisor mode is used. -*/ - - -/* - * Creates all the application tasks, then starts the scheduler. - * - * A task is created called "uIP". This executes the uIP stack and small - * WEB server sample. All the other tasks are from the set of standard - * demo tasks. The WEB documentation provides more details of the standard - * demo application tasks. - * - * Main.c also creates a task called "Check". This only executes every three - * seconds but has the highest priority so is guaranteed to get processor time. - * Its main function is to check that all the other tasks are still operational. - * Each standard demo task maintains a unique count that is incremented each - * time the task successfully completes its function. Should any error occur - * within such a task the count is permanently halted. The check task inspects - * the count of each task to ensure it has changed since the last time the - * check task executed. If all the count variables have changed all the tasks - * are still executing error free, and the check task toggles the yellow LED. - * Should any task contain an error at any time the LED toggle rate will change - * from 3 seconds to 500ms. - * - */ - - -/* Standard includes. */ -#include -#include - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Demo application includes. */ -#include "PollQ.h" -#include "dynamic.h" -#include "semtest.h" - -/*-----------------------------------------------------------*/ - -/* Constants to setup the PLL. */ -#define mainPLL_MUL_4 ( ( unsigned portCHAR ) 0x0003 ) -#define mainPLL_DIV_1 ( ( unsigned portCHAR ) 0x0000 ) -#define mainPLL_ENABLE ( ( unsigned portCHAR ) 0x0001 ) -#define mainPLL_CONNECT ( ( unsigned portCHAR ) 0x0003 ) -#define mainPLL_FEED_BYTE1 ( ( unsigned portCHAR ) 0xaa ) -#define mainPLL_FEED_BYTE2 ( ( unsigned portCHAR ) 0x55 ) -#define mainPLL_LOCK ( ( unsigned portLONG ) 0x0400 ) - -/* Constants to setup the MAM. */ -#define mainMAM_TIM_3 ( ( unsigned portCHAR ) 0x03 ) -#define mainMAM_MODE_FULL ( ( unsigned portCHAR ) 0x02 ) - -/* Constants to setup the peripheral bus. */ -#define mainBUS_CLK_FULL ( ( unsigned portCHAR ) 0x01 ) - -/* Priorities/stacks for the demo application tasks. */ -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) -#define mainUIP_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define mainUIP_TASK_STACK_SIZE ( 150 ) - -/* The rate at which the on board LED will toggle when there is/is not an -error. */ -#define mainNO_ERROR_FLASH_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS ) -#define mainERROR_FLASH_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS ) -#define mainON_BOARD_LED_BIT ( ( unsigned portLONG ) 0x80 ) -#define mainYELLOW_LED ( 1 << 11 ) - -/*-----------------------------------------------------------*/ - -/* - * This is the uIP task which is defined within the uip.c file. This has not - * been placed into a header file in order to minimise the changes to the uip - * code. - */ -extern void ( vuIP_TASK ) ( void *pvParameters ); - -/* - * The Yellow LED is under the control of the Check task. All the other LED's - * are under the control of the uIP task. - */ -void prvToggleOnBoardLED( void ); - -/* - * Checks that all the demo application tasks are still executing without error - * - as described at the top of the file. - */ -static portLONG prvCheckOtherTasksAreStillRunning( void ); - -/* - * The task that executes at the highest priority and calls - * prvCheckOtherTasksAreStillRunning(). See the description at the top - * of the file. - */ -static void vErrorChecks( void *pvParameters ); - -/* - * Configure the processor for use with the Olimex demo board. This includes - * setup for the I/O, system clock, and access timings. - */ -static void prvSetupHardware( void ); - -/*-----------------------------------------------------------*/ - -/* - * Starts all the other tasks, then starts the scheduler. - */ -int main( void ) -{ - /* Configure the processor. */ - prvSetupHardware(); - - /* Start the task that handles the TCP/IP functionality. */ - xTaskCreate( vuIP_TASK, "uIP", mainUIP_TASK_STACK_SIZE, NULL, mainUIP_PRIORITY, NULL ); - - /* Start the demo/test application tasks. These are created in addition - to the TCP/IP task for demonstration and test purposes. */ - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartDynamicPriorityTasks(); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - - /* Start the check task - which is defined in this file. */ - xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - - /* Now all the tasks have been started - start the scheduler. - - NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. - The processor MUST be in supervisor mode when vTaskStartScheduler is - called. The demo applications included in the FreeRTOS.org download switch - to supervisor mode prior to main being called. If you are not using one of - these demo application projects then ensure Supervisor mode is used here. */ - vTaskStartScheduler(); - - /* Should never reach here! */ - return 0; -} -/*-----------------------------------------------------------*/ - -static void vErrorChecks( void *pvParameters ) -{ -portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD; - - /* Cycle for ever, delaying then checking all the other tasks are still - operating without error. If an error is detected then the delay period - is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so - the on board LED flash rate will increase. */ - for( ;; ) - { - /* Delay until it is time to execute again. */ - vTaskDelay( xDelayPeriod ); - - /* Check all the standard demo application tasks are executing without - error. */ - if( prvCheckOtherTasksAreStillRunning() != pdPASS ) - { - /* An error has been detected in one of the tasks - flash faster. */ - xDelayPeriod = mainERROR_FLASH_PERIOD; - } - - prvToggleOnBoardLED(); - } -} -/*-----------------------------------------------------------*/ - -static void prvSetupHardware( void ) -{ - #ifdef RUN_FROM_RAM - /* Remap the interrupt vectors to RAM if we are are running from RAM. */ - SCB_MEMMAP = 2; - #endif - - /* Setup the PLL to multiply the XTAL input by 4. */ - SCB_PLLCFG = ( mainPLL_MUL_4 | mainPLL_DIV_1 ); - - /* Activate the PLL by turning it on then feeding the correct sequence of - bytes. */ - SCB_PLLCON = mainPLL_ENABLE; - SCB_PLLFEED = mainPLL_FEED_BYTE1; - SCB_PLLFEED = mainPLL_FEED_BYTE2; - - /* Wait for the PLL to lock... */ - while( !( SCB_PLLSTAT & mainPLL_LOCK ) ); - - /* ...before connecting it using the feed sequence again. */ - SCB_PLLCON = mainPLL_CONNECT; - SCB_PLLFEED = mainPLL_FEED_BYTE1; - SCB_PLLFEED = mainPLL_FEED_BYTE2; - - /* Setup and turn on the MAM. Three cycle access is used due to the fast - PLL used. It is possible faster overall performance could be obtained by - tuning the MAM and PLL settings. */ - MAM_TIM = mainMAM_TIM_3; - MAM_CR = mainMAM_MODE_FULL; - - /* Setup the peripheral bus to be the same as the PLL output. */ - SCB_VPBDIV = mainBUS_CLK_FULL; -} -/*-----------------------------------------------------------*/ - -void prvToggleOnBoardLED( void ) -{ -unsigned portLONG ulState; - - ulState = GPIO0_IOPIN; - if( ulState & mainYELLOW_LED ) - { - GPIO_IOCLR = mainYELLOW_LED; - } - else - { - GPIO_IOSET = mainYELLOW_LED; - } -} -/*-----------------------------------------------------------*/ - -static portLONG prvCheckOtherTasksAreStillRunning( void ) -{ -portLONG lReturn = ( portLONG ) pdPASS; - - /* Check all the demo tasks (other than the flash tasks) to ensure - that they are all still running, and that none of them have detected - an error. */ - - if( xArePollingQueuesStillRunning() != pdTRUE ) - { - lReturn = ( portLONG ) pdFAIL; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - lReturn = ( portLONG ) pdFAIL; - } - - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - lReturn = ( portLONG ) pdFAIL; - } - - return lReturn; -} - - - diff --git a/Demo/uIP_Demo_Rowley_ARM7/rtosdemo.hzp b/Demo/uIP_Demo_Rowley_ARM7/rtosdemo.hzp deleted file mode 100644 index e5d235ed2..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/rtosdemo.hzp +++ /dev/null @@ -1,56 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Demo/uIP_Demo_Rowley_ARM7/rtosdemo.hzs b/Demo/uIP_Demo_Rowley_ARM7/rtosdemo.hzs deleted file mode 100644 index 61e9d913b..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/rtosdemo.hzs +++ /dev/null @@ -1,76 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/Makefile b/Demo/uIP_Demo_Rowley_ARM7/uip/Makefile deleted file mode 100644 index 61d3a06aa..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/uip/Makefile +++ /dev/null @@ -1,74 +0,0 @@ -# Copyright (c) 2001, Adam Dunkels. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# 3. All advertising materials mentioning features or use of this software -# must display the following acknowledgement: -# This product includes software developed by Adam Dunkels. -# 4. The name of the author may not be used to endorse or promote -# products derived from this software without specific prior -# written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS -# OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY -# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# This file is part of the uIP TCP/IP stack. -# -# $Id: Makefile,v 1.8.2.2 2003/10/04 22:54:17 adam Exp $ -# - -CC=gcc -CFLAGS=-Wall -g -I../uip -I. -I../apps/httpd -I../apps/resolv -I../apps/webclient -I../apps/smtp -I../apps/telnet -fpack-struct - -%.o: - $(CC) $(CFLAGS) -c $(<:.o=.c) - - -uip: uip.o uip_arch.o tapdev.o httpd.o main.o fs.o uip_arp.o cgi.o - -tapdev.o: tapdev.c uipopt.h -main.o: main.c ../uip/uip.h uipopt.h ../apps/httpd/httpd.h \ - tapdev.h -uip_arch.o: uip_arch.c ../uip/uip_arch.h ../uip/uip.h uipopt.h \ - ../apps/httpd/httpd.h -uip.o: ../uip/uip.c ../uip/uip.h uipopt.h ../apps/httpd/httpd.h - -uip_arp.o: ../uip/uip_arp.c ../uip/uip_arp.h ../uip/uip.h uipopt.h \ - ../apps/httpd/httpd.h - $(CC) -o uip_arp.o $(CFLAGS) -fpack-struct -c ../uip/uip_arp.c - - -cgi.o: ../apps/httpd/cgi.c ../uip/uip.h uipopt.h ../apps/smtp/smtp.h \ - ../apps/httpd/cgi.h ../apps/httpd/httpd.h ../apps/httpd/fs.h -fs.o: ../apps/httpd/fs.c ../uip/uip.h uipopt.h ../apps/smtp/smtp.h \ - ../apps/httpd/httpd.h ../apps/httpd/fs.h ../apps/httpd/fsdata.h \ - ../apps/httpd/fsdata.c -fsdata.o: ../apps/httpd/fsdata.c -httpd.o: ../apps/httpd/httpd.c ../uip/uip.h uipopt.h \ - ../apps/smtp/smtp.h ../apps/httpd/httpd.h ../apps/httpd/fs.h \ - ../apps/httpd/fsdata.h ../apps/httpd/cgi.h - -clean: - rm -f *.o *~ *core uip - - - - - - diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/cgi.c b/Demo/uIP_Demo_Rowley_ARM7/uip/cgi.c deleted file mode 100644 index 06574a156..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/uip/cgi.c +++ /dev/null @@ -1,211 +0,0 @@ -/** - * \addtogroup httpd - * @{ - */ - -/** - * \file - * HTTP server script language C functions file. - * \author Adam Dunkels - * - * This file contains functions that are called by the web server - * scripts. The functions takes one argument, and the return value is - * interpreted as follows. A zero means that the function did not - * complete and should be invoked for the next packet as well. A - * non-zero value indicates that the function has completed and that - * the web server should move along to the next script line. - * - */ - -/* - * Copyright (c) 2001, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: cgi.c,v 1.23.2.4 2003/10/07 13:22:27 adam Exp $ - * - */ - -#include "uip.h" -#include "cgi.h" -#include "httpd.h" -#include "fs.h" - -#include -#include - -static u8_t print_stats(u8_t next); -static u8_t file_stats(u8_t next); -static u8_t tcp_stats(u8_t next); - -cgifunction cgitab[] = { - print_stats, /* CGI function "a" */ - file_stats, /* CGI function "b" */ - tcp_stats /* CGI function "c" */ -}; - -static const char closed[] = /* "CLOSED",*/ -{0x43, 0x4c, 0x4f, 0x53, 0x45, 0x44, 0}; -static const char syn_rcvd[] = /* "SYN-RCVD",*/ -{0x53, 0x59, 0x4e, 0x2d, 0x52, 0x43, 0x56, - 0x44, 0}; -static const char syn_sent[] = /* "SYN-SENT",*/ -{0x53, 0x59, 0x4e, 0x2d, 0x53, 0x45, 0x4e, - 0x54, 0}; -static const char established[] = /* "ESTABLISHED",*/ -{0x45, 0x53, 0x54, 0x41, 0x42, 0x4c, 0x49, 0x53, 0x48, - 0x45, 0x44, 0}; -static const char fin_wait_1[] = /* "FIN-WAIT-1",*/ -{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, - 0x54, 0x2d, 0x31, 0}; -static const char fin_wait_2[] = /* "FIN-WAIT-2",*/ -{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49, - 0x54, 0x2d, 0x32, 0}; -static const char closing[] = /* "CLOSING",*/ -{0x43, 0x4c, 0x4f, 0x53, 0x49, - 0x4e, 0x47, 0}; -static const char time_wait[] = /* "TIME-WAIT,"*/ -{0x54, 0x49, 0x4d, 0x45, 0x2d, 0x57, 0x41, - 0x49, 0x54, 0}; -static const char last_ack[] = /* "LAST-ACK"*/ -{0x4c, 0x41, 0x53, 0x54, 0x2d, 0x41, 0x43, - 0x4b, 0}; - -static const char *states[] = { - closed, - syn_rcvd, - syn_sent, - established, - fin_wait_1, - fin_wait_2, - closing, - time_wait, - last_ack}; - - -/*-----------------------------------------------------------------------------------*/ -/* print_stats: - * - * Prints out a part of the uIP statistics. The statistics data is - * written into the uip_appdata buffer. It overwrites any incoming - * packet. - */ -static u8_t -print_stats(u8_t next) -{ -#if UIP_STATISTICS - u16_t i, j; - u8_t *buf; - u16_t *databytes; - - if(next) { - /* If our last data has been acknowledged, we move on the next - chunk of statistics. */ - hs->count = hs->count + 4; - if(hs->count >= sizeof(struct uip_stats)/sizeof(u16_t)) { - /* We have printed out all statistics, so we return 1 to - indicate that we are done. */ - return 1; - } - } - - /* Write part of the statistics into the uip_appdata buffer. */ - databytes = (u16_t *)&uip_stat + hs->count; - buf = (u8_t *)uip_appdata; - - j = 4 + 1; - i = hs->count; - while (i < sizeof(struct uip_stats)/sizeof(u16_t) && --j > 0) { - sprintf((char *)buf, "%5u\r\n", *databytes); - ++databytes; - buf += 6; - ++i; - } - - /* Send the data. */ - uip_send(uip_appdata, buf - uip_appdata); - - return 0; -#else - return 1; -#endif /* UIP_STATISTICS */ -} -/*-----------------------------------------------------------------------------------*/ -static u8_t -file_stats(u8_t next) -{ - /* We use sprintf() to print the number of file accesses to a - particular file (given as an argument to the function in the - script). We then use uip_send() to actually send the data. */ - if(next) { - return 1; - } - uip_send(uip_appdata, sprintf((char *)uip_appdata, "%5u", fs_count(&hs->script[4]))); - return 0; -} -/*-----------------------------------------------------------------------------------*/ -static u8_t -tcp_stats(u8_t next) -{ - struct uip_conn *conn; - - if(next) { - /* If the previously sent data has been acknowledged, we move - forward one connection. */ - if(++hs->count == UIP_CONNS) { - /* If all connections has been printed out, we are done and - return 1. */ - return 1; - } - } - - conn = &uip_conns[hs->count]; - if((conn->tcpstateflags & TS_MASK) == CLOSED) { - uip_send(uip_appdata, sprintf((char *)uip_appdata, - "--%u%u%c %c\r\n", - conn->nrtx, - conn->timer, - (uip_outstanding(conn))? '*':' ', - (uip_stopped(conn))? '!':' ')); - } else { - uip_send(uip_appdata, sprintf((char *)uip_appdata, - "%u.%u.%u.%u:%u%s%u%u%c %c\r\n", - htons(conn->ripaddr[0]) >> 8, - htons(conn->ripaddr[0]) & 0xff, - htons(conn->ripaddr[1]) >> 8, - htons(conn->ripaddr[1]) & 0xff, - htons(conn->rport), - states[conn->tcpstateflags & TS_MASK], - conn->nrtx, - conn->timer, - (uip_outstanding(conn))? '*':' ', - (uip_stopped(conn))? '!':' ')); - } - return 0; -} -/*-----------------------------------------------------------------------------------*/ diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/cgi.h b/Demo/uIP_Demo_Rowley_ARM7/uip/cgi.h deleted file mode 100644 index d85389b52..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/uip/cgi.h +++ /dev/null @@ -1,57 +0,0 @@ -/** - * \addtogroup httpd - * @{ - */ - -/** - * \file - * HTTP script language header file. - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2001, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: cgi.h,v 1.3.2.4 2003/10/07 13:22:27 adam Exp $ - * - */ - -#ifndef __CGI_H__ -#define __CGI_H__ - -typedef u8_t (* cgifunction)(u8_t next); - -/** - * A table containing pointers to C functions that can be called from - * a web server script. - */ -extern cgifunction cgitab[]; - -#endif /* __CGI_H__ */ diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/crt0.asm b/Demo/uIP_Demo_Rowley_ARM7/uip/crt0.asm deleted file mode 100644 index ef91f42a8..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/uip/crt0.asm +++ /dev/null @@ -1,66 +0,0 @@ -// Rowley C Compiler, runtime support. -// -// Copyright (c) 2001, 2002, 2003 Rowley Associates Limited. -// -// This file may be distributed under the terms of the License Agreement -// provided with this software. -// -// THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE -// WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. - -; Create sections - .data - .bss - -; Go to code section. - .code - -; Executed upon reset -__reset proc - -; Turn off watchdog. You can enable it in main() if required. - mov.w #0x5a80, &0x120 - -; Set up stack. - mov.w #RAM_Start_Address+RAM_Size, sp - -; Copy from initialised data section to data section. - mov.w #SFB(IDATA0), r15 - mov.w #data_init_begin, r14 - mov.w #data_init_end-data_init_begin, r13 - call #_memcpy - -; Zero the bss. Ensure the stack is not allocated in the bss! - mov.w #SFB(UDATA0), r15 - mov.w #0, r14 - mov.w #SFE(UDATA0)-SFB(UDATA0), r13 - call #_memset - -; Call user entry point void main(void). - call #_main - -; If main() returns, kick off again. - jmp __reset - endproc - -; Heap data structures; removed by the linker if the heap isn't used. - .break - .data - align WORD -___heap_start__:: - DW 0 - DW heap_size - DS heap_size-4 - -; Reset vector - .vectors - .keep - org 0x1e - dw __reset - -; Initialise the IDATA0 section by duplicating the contents into the -; CONST section and copying them on startup. - .const -data_init_begin: - .init "IDATA0" -data_init_end: diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/cs8900a.c b/Demo/uIP_Demo_Rowley_ARM7/uip/cs8900a.c deleted file mode 100644 index 331463a78..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/uip/cs8900a.c +++ /dev/null @@ -1,546 +0,0 @@ -// cs8900a.c: device driver for the CS8900a chip in 8-bit mode. - -#include - -#include "cs8900a.h" -#include "uip.h" -#include "uip_arp.h" - -#define IOR (1<<12) // CS8900's ISA-bus interface pins -#define IOW (1<<13) - -// definitions for Crystal CS8900 ethernet-controller -// based on linux-header by Russel Nelson - -#define PP_ChipID 0x0000 // offset 0h -> Corp-ID - - // offset 2h -> Model/Product Number -#define LED_RED (1<<8) -#define LED_GREEN (1<<10) -#define LED_YELLOW (1<<11) - -#define PP_ISAIOB 0x0020 // IO base address -#define PP_CS8900_ISAINT 0x0022 // ISA interrupt select -#define PP_CS8900_ISADMA 0x0024 // ISA Rec DMA channel -#define PP_ISASOF 0x0026 // ISA DMA offset -#define PP_DmaFrameCnt 0x0028 // ISA DMA Frame count -#define PP_DmaByteCnt 0x002A // ISA DMA Byte count -#define PP_CS8900_ISAMemB 0x002C // Memory base -#define PP_ISABootBase 0x0030 // Boot Prom base -#define PP_ISABootMask 0x0034 // Boot Prom Mask - -// EEPROM data and command registers -#define PP_EECMD 0x0040 // NVR Interface Command register -#define PP_EEData 0x0042 // NVR Interface Data Register - -// Configuration and control registers -#define PP_RxCFG 0x0102 // Rx Bus config -#define PP_RxCTL 0x0104 // Receive Control Register -#define PP_TxCFG 0x0106 // Transmit Config Register -#define PP_TxCMD 0x0108 // Transmit Command Register -#define PP_BufCFG 0x010A // Bus configuration Register -#define PP_LineCTL 0x0112 // Line Config Register -#define PP_SelfCTL 0x0114 // Self Command Register -#define PP_BusCTL 0x0116 // ISA bus control Register -#define PP_TestCTL 0x0118 // Test Register - -// Status and Event Registers -#define PP_ISQ 0x0120 // Interrupt Status -#define PP_RxEvent 0x0124 // Rx Event Register -#define PP_TxEvent 0x0128 // Tx Event Register -#define PP_BufEvent 0x012C // Bus Event Register -#define PP_RxMiss 0x0130 // Receive Miss Count -#define PP_TxCol 0x0132 // Transmit Collision Count -#define PP_LineST 0x0134 // Line State Register -#define PP_SelfST 0x0136 // Self State register -#define PP_BusST 0x0138 // Bus Status -#define PP_TDR 0x013C // Time Domain Reflectometry - -// Initiate Transmit Registers -#define PP_TxCommand 0x0144 // Tx Command -#define PP_TxLength 0x0146 // Tx Length - -// Adress Filter Registers -#define PP_LAF 0x0150 // Hash Table -#define PP_IA 0x0158 // Physical Address Register - -// Frame Location -#define PP_RxStatus 0x0400 // Receive start of frame -#define PP_RxLength 0x0402 // Receive Length of frame -#define PP_RxFrame 0x0404 // Receive frame pointer -#define PP_TxFrame 0x0A00 // Transmit frame pointer - -// Primary I/O Base Address. If no I/O base is supplied by the user, then this -// can be used as the default I/O base to access the PacketPage Area. -#define DEFAULTIOBASE 0x0300 - -// PP_RxCFG - Receive Configuration and Interrupt Mask bit definition - Read/write -#define SKIP_1 0x0040 -#define RX_STREAM_ENBL 0x0080 -#define RX_OK_ENBL 0x0100 -#define RX_DMA_ONLY 0x0200 -#define AUTO_RX_DMA 0x0400 -#define BUFFER_CRC 0x0800 -#define RX_CRC_ERROR_ENBL 0x1000 -#define RX_RUNT_ENBL 0x2000 -#define RX_EXTRA_DATA_ENBL 0x4000 - -// PP_RxCTL - Receive Control bit definition - Read/write -#define RX_IA_HASH_ACCEPT 0x0040 -#define RX_PROM_ACCEPT 0x0080 -#define RX_OK_ACCEPT 0x0100 -#define RX_MULTCAST_ACCEPT 0x0200 -#define RX_IA_ACCEPT 0x0400 -#define RX_BROADCAST_ACCEPT 0x0800 -#define RX_BAD_CRC_ACCEPT 0x1000 -#define RX_RUNT_ACCEPT 0x2000 -#define RX_EXTRA_DATA_ACCEPT 0x4000 - -// PP_TxCFG - Transmit Configuration Interrupt Mask bit definition - Read/write -#define TX_LOST_CRS_ENBL 0x0040 -#define TX_SQE_ERROR_ENBL 0x0080 -#define TX_OK_ENBL 0x0100 -#define TX_LATE_COL_ENBL 0x0200 -#define TX_JBR_ENBL 0x0400 -#define TX_ANY_COL_ENBL 0x0800 -#define TX_16_COL_ENBL 0x8000 - -// PP_TxCMD - Transmit Command bit definition - Read-only and -// PP_TxCommand - Write-only -#define TX_START_5_BYTES 0x0000 -#define TX_START_381_BYTES 0x0040 -#define TX_START_1021_BYTES 0x0080 -#define TX_START_ALL_BYTES 0x00C0 -#define TX_FORCE 0x0100 -#define TX_ONE_COL 0x0200 -#define TX_NO_CRC 0x1000 -#define TX_RUNT 0x2000 - -// PP_BufCFG - Buffer Configuration Interrupt Mask bit definition - Read/write -#define GENERATE_SW_INTERRUPT 0x0040 -#define RX_DMA_ENBL 0x0080 -#define READY_FOR_TX_ENBL 0x0100 -#define TX_UNDERRUN_ENBL 0x0200 -#define RX_MISS_ENBL 0x0400 -#define RX_128_BYTE_ENBL 0x0800 -#define TX_COL_COUNT_OVRFLOW_ENBL 0x1000 -#define RX_MISS_COUNT_OVRFLOW_ENBL 0x2000 -#define RX_DEST_MATCH_ENBL 0x8000 - -// PP_LineCTL - Line Control bit definition - Read/write -#define SERIAL_RX_ON 0x0040 -#define SERIAL_TX_ON 0x0080 -#define AUI_ONLY 0x0100 -#define AUTO_AUI_10BASET 0x0200 -#define MODIFIED_BACKOFF 0x0800 -#define NO_AUTO_POLARITY 0x1000 -#define TWO_PART_DEFDIS 0x2000 -#define LOW_RX_SQUELCH 0x4000 - -// PP_SelfCTL - Software Self Control bit definition - Read/write -#define POWER_ON_RESET 0x0040 -#define SW_STOP 0x0100 -#define SLEEP_ON 0x0200 -#define AUTO_WAKEUP 0x0400 -#define HCB0_ENBL 0x1000 -#define HCB1_ENBL 0x2000 -#define HCB0 0x4000 -#define HCB1 0x8000 - -// PP_BusCTL - ISA Bus Control bit definition - Read/write -#define RESET_RX_DMA 0x0040 -#define MEMORY_ON 0x0400 -#define DMA_BURST_MODE 0x0800 -#define IO_CHANNEL_READY_ON 0x1000 -#define RX_DMA_SIZE_64K 0x2000 -#define ENABLE_IRQ 0x8000 - -// PP_TestCTL - Test Control bit definition - Read/write -#define LINK_OFF 0x0080 -#define ENDEC_LOOPBACK 0x0200 -#define AUI_LOOPBACK 0x0400 -#define BACKOFF_OFF 0x0800 -#define FDX_8900 0x4000 - -// PP_RxEvent - Receive Event Bit definition - Read-only -#define RX_IA_HASHED 0x0040 -#define RX_DRIBBLE 0x0080 -#define RX_OK 0x0100 -#define RX_HASHED 0x0200 -#define RX_IA 0x0400 -#define RX_BROADCAST 0x0800 -#define RX_CRC_ERROR 0x1000 -#define RX_RUNT 0x2000 -#define RX_EXTRA_DATA 0x4000 -#define HASH_INDEX_MASK 0xFC00 // Hash-Table Index Mask (6 Bit) - -// PP_TxEvent - Transmit Event Bit definition - Read-only -#define TX_LOST_CRS 0x0040 -#define TX_SQE_ERROR 0x0080 -#define TX_OK 0x0100 -#define TX_LATE_COL 0x0200 -#define TX_JBR 0x0400 -#define TX_16_COL 0x8000 -#define TX_COL_COUNT_MASK 0x7800 - -// PP_BufEvent - Buffer Event Bit definition - Read-only -#define SW_INTERRUPT 0x0040 -#define RX_DMA 0x0080 -#define READY_FOR_TX 0x0100 -#define TX_UNDERRUN 0x0200 -#define RX_MISS 0x0400 -#define RX_128_BYTE 0x0800 -#define TX_COL_OVRFLW 0x1000 -#define RX_MISS_OVRFLW 0x2000 -#define RX_DEST_MATCH 0x8000 - -// PP_LineST - Ethernet Line Status bit definition - Read-only -#define LINK_OK 0x0080 -#define AUI_ON 0x0100 -#define TENBASET_ON 0x0200 -#define POLARITY_OK 0x1000 -#define CRS_OK 0x4000 - -// PP_SelfST - Chip Software Status bit definition -#define ACTIVE_33V 0x0040 -#define INIT_DONE 0x0080 -#define SI_BUSY 0x0100 -#define EEPROM_PRESENT 0x0200 -#define EEPROM_OK 0x0400 -#define EL_PRESENT 0x0800 -#define EE_SIZE_64 0x1000 - -// PP_BusST - ISA Bus Status bit definition -#define TX_BID_ERROR 0x0080 -#define READY_FOR_TX_NOW 0x0100 - -// The following block defines the ISQ event types -#define ISQ_RX_EVENT 0x0004 -#define ISQ_TX_EVENT 0x0008 -#define ISQ_BUFFER_EVENT 0x000C -#define ISQ_RX_MISS_EVENT 0x0010 -#define ISQ_TX_COL_EVENT 0x0012 - -#define ISQ_EVENT_MASK 0x003F // ISQ mask to find out type of event - -// Ports for I/O-Mode -#define RX_FRAME_PORT 0x0000 -#define TX_FRAME_PORT 0x0000 -#define TX_CMD_PORT 0x0004 -#define TX_LEN_PORT 0x0006 -#define ISQ_PORT 0x0008 -#define ADD_PORT 0x000A -#define DATA_PORT 0x000C - -#define AUTOINCREMENT 0x8000 // Bit mask to set Bit-15 for autoincrement - -// EEProm Commands -#define EEPROM_WRITE_EN 0x00F0 -#define EEPROM_WRITE_DIS 0x0000 -#define EEPROM_WRITE_CMD 0x0100 -#define EEPROM_READ_CMD 0x0200 - -// Receive Header of each packet in receive area of memory for DMA-Mode -#define RBUF_EVENT_LOW 0x0000 // Low byte of RxEvent -#define RBUF_EVENT_HIGH 0x0001 // High byte of RxEvent -#define RBUF_LEN_LOW 0x0002 // Length of received data - low byte -#define RBUF_LEN_HI 0x0003 // Length of received data - high byte -#define RBUF_HEAD_LEN 0x0004 // Length of this header - -// typedefs -typedef struct { // struct to store CS8900's - unsigned int Addr; // init-sequence - unsigned int Data; -} TInitSeq; - -unsigned short ticks; - -static void skip_frame(void); - -const TInitSeq InitSeq[] = -{ - PP_IA, UIP_ETHADDR0 + (UIP_ETHADDR1 << 8), // set our MAC as Individual Address - PP_IA + 2, UIP_ETHADDR2 + (UIP_ETHADDR3 << 8), - PP_IA + 4, UIP_ETHADDR4 + (UIP_ETHADDR5 << 8), - PP_LineCTL, SERIAL_RX_ON | SERIAL_TX_ON, // configure the Physical Interface - PP_RxCTL, RX_OK_ACCEPT | RX_IA_ACCEPT | RX_BROADCAST_ACCEPT -}; - -// Writes a word in little-endian byte order to a specified port-address -void -cs8900a_write(unsigned addr, unsigned int data) -{ - GPIO_IODIR |= 0xff << 16; // Data port to output - - GPIO_IOCLR = 0xf << 4; // Put address on bus - GPIO_IOSET = addr << 4; - - GPIO_IOCLR = 0xff << 16; // Write low order byte to data bus - GPIO_IOSET = data << 16; - - asm volatile ( "NOP" ); - GPIO_IOCLR = IOW; // Toggle IOW-signal - asm volatile ( "NOP" ); - GPIO_IOSET = IOW; - asm volatile ( "NOP" ); - - GPIO_IOCLR = 0xf << 4; - GPIO_IOSET = ((addr | 1) << 4); // And put next address on bus - - GPIO_IOCLR = 0xff << 16; // Write high order byte to data bus - GPIO_IOSET = data >> 8 << 16; - - asm volatile ( "NOP" ); - GPIO_IOCLR = IOW; // Toggle IOW-signal - asm volatile ( "NOP" ); - GPIO_IOSET = IOW; - asm volatile ( "NOP" ); -} - -// Reads a word in little-endian byte order from a specified port-address -unsigned -cs8900a_read(unsigned addr) -{ - unsigned int value; - - GPIO_IODIR &= ~(0xff << 16); // Data port to input - - GPIO_IOCLR = 0xf << 4; // Put address on bus - GPIO_IOSET = addr << 4; - - asm volatile ( "NOP" ); - GPIO_IOCLR = IOR; // IOR-signal low - asm volatile ( "NOP" ); - value = (GPIO_IOPIN >> 16) & 0xff; // get low order byte from data bus - GPIO_IOSET = IOR; - - GPIO_IOSET = 1 << 4; // IOR high and put next address on bus - - asm volatile ( "NOP" ); - GPIO_IOCLR = IOR; // IOR-signal low - asm volatile ( "NOP" ); - value |= ((GPIO_IOPIN >> 8) & 0xff00); // get high order byte from data bus - GPIO_IOSET = IOR; // IOR-signal low - - return value; -} - -// Reads a word in little-endian byte order from a specified port-address -unsigned -cs8900a_read_addr_high_first(unsigned addr) -{ - unsigned int value; - - GPIO_IODIR &= ~(0xff << 16); // Data port to input - - GPIO_IOCLR = 0xf << 4; // Put address on bus - GPIO_IOSET = (addr+1) << 4; - - asm volatile ( "NOP" ); - GPIO_IOCLR = IOR; // IOR-signal low - asm volatile ( "NOP" ); - value = ((GPIO_IOPIN >> 8) & 0xff00); // get high order byte from data bus - GPIO_IOSET = IOR; // IOR-signal high - - GPIO_IOCLR = 1 << 4; // Put low address on bus - - asm volatile ( "NOP" ); - GPIO_IOCLR = IOR; // IOR-signal low - asm volatile ( "NOP" ); - value |= (GPIO_IOPIN >> 16) & 0xff; // get low order byte from data bus - GPIO_IOSET = IOR; - - return value; -} - -void -cs8900a_init(void) -{ - int i; - - // Reset outputs, control lines high - GPIO_IOSET = IOR | IOW; - - // No LEDs on. - GPIO_IOSET = LED_RED | LED_YELLOW | LED_GREEN; - - // Port 3 as output (all pins but RS232) - GPIO_IODIR = ~0U; // everything to output. - - // Reset outputs - GPIO_IOCLR = 0xff << 16; // clear data outputs - - // Reset the CS8900A - cs8900a_write(ADD_PORT, PP_SelfCTL); - cs8900a_write(DATA_PORT, POWER_ON_RESET); - - // Wait until chip-reset is done - cs8900a_write(ADD_PORT, PP_SelfST); - while ((cs8900a_read(DATA_PORT) & INIT_DONE) == 0) - ; - - // Configure the CS8900A - for (i = 0; i < sizeof InitSeq / sizeof (TInitSeq); ++i) - { - cs8900a_write(ADD_PORT, InitSeq[i].Addr); - cs8900a_write(DATA_PORT, InitSeq[i].Data); - } -} - -void -cs8900a_send(void) -{ - unsigned u; - - GPIO_IOCLR = LED_RED; // Light RED LED when frame starting - - // Transmit command - cs8900a_write(TX_CMD_PORT, TX_START_ALL_BYTES); - cs8900a_write(TX_LEN_PORT, uip_len); - - // Maximum number of retries - u = 8; - for (;;) - { - // Check for avaliable buffer space - cs8900a_write(ADD_PORT, PP_BusST); - if (cs8900a_read(DATA_PORT) & READY_FOR_TX_NOW) - break; - if (u -- == 0) - { - GPIO_IOSET = LED_RED; // Extinguish RED LED on end of frame - return; - } - - // No space avaliable, skip a received frame and try again - skip_frame(); - } - - GPIO_IODIR |= 0xff << 16; // Data port to output - - // Send 40+14=54 bytes of header - for (u = 0; u < 54; u += 2) - { - GPIO_IOCLR = 0xf << 4; // Put address on bus - GPIO_IOSET = TX_FRAME_PORT << 4; - - GPIO_IOCLR = 0xff << 16; // Write low order byte to data bus - GPIO_IOSET = uip_buf[u] << 16; // write low order byte to data bus - - asm volatile ( "NOP" ); - GPIO_IOCLR = IOW; // Toggle IOW-signal - asm volatile ( "NOP" ); - GPIO_IOSET = IOW; - - GPIO_IOCLR = 0xf << 4; // Put address on bus - GPIO_IOSET = (TX_FRAME_PORT | 1) << 4; // and put next address on bus - - GPIO_IOCLR = 0xff << 16; // Write low order byte to data bus - GPIO_IOSET = uip_buf[u+1] << 16; // write low order byte to data bus - - asm volatile ( "NOP" ); - GPIO_IOCLR = IOW; // Toggle IOW-signal - asm volatile ( "NOP" ); - GPIO_IOSET = IOW; - } - - if (uip_len <= 54) - { - GPIO_IOSET = LED_RED; // Extinguish RED LED on end of frame - return; - } - - // Send remainder of packet, the application data - uip_len -= 54; - for (u = 0; u < uip_len; u += 2) - { - - GPIO_IOCLR = 0xf << 4; // Put address on bus - GPIO_IOSET = TX_FRAME_PORT << 4; - - GPIO_IOCLR = 0xff << 16; // Write low order byte to data bus - GPIO_IOSET = uip_appdata[u] << 16; // write low order byte to data bus - - asm volatile ( "NOP" ); - GPIO_IOCLR = IOW; // Toggle IOW-signal - asm volatile ( "NOP" ); - GPIO_IOSET = IOW; - - GPIO_IOCLR = 0xf << 4; // Put address on bus - GPIO_IOSET = (TX_FRAME_PORT | 1) << 4; // and put next address on bus - - GPIO_IOCLR = 0xff << 16; // Write low order byte to data bus - GPIO_IOSET = uip_appdata[u+1] << 16; // write low order byte to data bus - - asm volatile ( "NOP" ); - GPIO_IOCLR = IOW; // Toggle IOW-signal - asm volatile ( "NOP" ); - GPIO_IOSET = IOW; - } - - GPIO_IOSET = LED_RED; // Extinguish RED LED on end of frame -} - -static void -skip_frame(void) -{ - // No space avaliable, skip a received frame and try again - cs8900a_write(ADD_PORT, PP_RxCFG); - cs8900a_write(DATA_PORT, cs8900a_read(DATA_PORT) | SKIP_1); -} - -u8_t -cs8900a_poll(void) -{ - u16_t len, u; - - // Check receiver event register to see if there are any valid frames avaliable - cs8900a_write(ADD_PORT, PP_RxEvent); - if ((cs8900a_read(DATA_PORT) & 0xd00) == 0) - return 0; - - GPIO_IOCLR = LED_GREEN; // Light GREED LED when frame coming in. - - // Read receiver status and discard it. - cs8900a_read_addr_high_first(RX_FRAME_PORT); - - // Read frame length - len = cs8900a_read_addr_high_first(RX_FRAME_PORT); - - // If the frame is too big to handle, throw it away - if (len > UIP_BUFSIZE) - { - skip_frame(); - return 0; - } - - // Data port to input - GPIO_IODIR &= ~(0xff << 16); - - GPIO_IOCLR = 0xf << 4; // put address on bus - GPIO_IOSET = RX_FRAME_PORT << 4; - - // Read bytes into uip_buf - u = 0; - while (u < len) - { - GPIO_IOCLR = 1 << 4; // put address on bus - - GPIO_IOCLR = IOR; // IOR-signal low - uip_buf[u] = GPIO_IOPIN >> 16; // get high order byte from data bus - asm volatile ( "NOP" ); - GPIO_IOSET = IOR; // IOR-signal high - - GPIO_IOSET = 1 << 4; // put address on bus - - GPIO_IOCLR = IOR; // IOR-signal low - asm volatile ( "NOP" ); - uip_buf[u+1] = GPIO_IOPIN >> 16; // get high order byte from data bus - GPIO_IOSET = IOR; // IOR-signal high - u += 2; - } - - GPIO_IOSET = LED_GREEN; // Extinguish GREED LED when frame finished. - return len; -} - diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/cs8900a.h b/Demo/uIP_Demo_Rowley_ARM7/uip/cs8900a.h deleted file mode 100644 index 2d4b56fe0..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/uip/cs8900a.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef __CS8900A_H__ -#define __CS8900A_H__ - -#include "uip_arch.h" - -void cs8900a_init(void); -void cs8900a_send(void); -u8_t cs8900a_poll(void); - -#endif /* __CS8900A_H__ */ diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/fs.c b/Demo/uIP_Demo_Rowley_ARM7/uip/fs.c deleted file mode 100644 index 7e15200b2..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/uip/fs.c +++ /dev/null @@ -1,155 +0,0 @@ -/** - * \addtogroup httpd - * @{ - */ - -/** - * \file - * HTTP server read-only file system code. - * \author Adam Dunkels - * - * A simple read-only filesystem. - */ - -/* - * Copyright (c) 2001, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - * $Id: fs.c,v 1.7.2.3 2003/10/07 13:22:27 adam Exp $ - */ - -#include "uip.h" -#include "httpd.h" -#include "fs.h" -#include "fsdata.h" - -#define NULL (void *)0 -#include "fsdata.c" - -#ifdef FS_STATISTICS -#if FS_STATISTICS == 1 -static u16_t count[FS_NUMFILES]; -#endif /* FS_STATISTICS */ -#endif /* FS_STATISTICS */ - -/*-----------------------------------------------------------------------------------*/ -static u8_t -fs_strcmp(const char *str1, const char *str2) -{ - u8_t i; - i = 0; - loop: - - if(str2[i] == 0 || - str1[i] == '\r' || - str1[i] == '\n') { - return 0; - } - - if(str1[i] != str2[i]) { - return 1; - } - - - ++i; - goto loop; -} -/*-----------------------------------------------------------------------------------*/ -int -fs_open(const char *name, struct fs_file *file) -{ -#ifdef FS_STATISTICS -#if FS_STATISTICS == 1 - u16_t i = 0; -#endif /* FS_STATISTICS */ -#endif /* FS_STATISTICS */ - struct fsdata_file_noconst *f; - - for(f = (struct fsdata_file_noconst *)FS_ROOT; - f != NULL; - f = (struct fsdata_file_noconst *)f->next) { - - if(fs_strcmp(name, f->name) == 0) { - file->data = f->data; - file->len = f->len; -#ifdef FS_STATISTICS -#if FS_STATISTICS == 1 - ++count[i]; -#endif /* FS_STATISTICS */ -#endif /* FS_STATISTICS */ - return 1; - } -#ifdef FS_STATISTICS -#if FS_STATISTICS == 1 - ++i; -#endif /* FS_STATISTICS */ -#endif /* FS_STATISTICS */ - - } - return 0; -} -/*-----------------------------------------------------------------------------------*/ -void -fs_init(void) -{ -#ifdef FS_STATISTICS -#if FS_STATISTICS == 1 - u16_t i; - for(i = 0; i < FS_NUMFILES; i++) { - count[i] = 0; - } -#endif /* FS_STATISTICS */ -#endif /* FS_STATISTICS */ -} -/*-----------------------------------------------------------------------------------*/ -#ifdef FS_STATISTICS -#if FS_STATISTICS == 1 -u16_t fs_count -(char *name) -{ - struct fsdata_file_noconst *f; - u16_t i; - - i = 0; - for(f = (struct fsdata_file_noconst *)FS_ROOT; - f != NULL; - f = (struct fsdata_file_noconst *)f->next) { - - if(fs_strcmp(name, f->name) == 0) { - return count[i]; - } - ++i; - } - return 0; -} -#endif /* FS_STATISTICS */ -#endif /* FS_STATISTICS */ -/*-----------------------------------------------------------------------------------*/ diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/fs.h b/Demo/uIP_Demo_Rowley_ARM7/uip/fs.h deleted file mode 100644 index 65551ba41..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/uip/fs.h +++ /dev/null @@ -1,80 +0,0 @@ -/** - * \addtogroup httpd - * @{ - */ - -/** - * \file - * HTTP server read-only file system header file. - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2001, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - * $Id: fs.h,v 1.6.2.3 2003/10/07 13:22:27 adam Exp $ - */ -#ifndef __FS_H__ -#define __FS_H__ - -#include "uip.h" - -/** - * An open file in the read-only file system. - */ -struct fs_file { - char *data; /**< The actual file data. */ - int len; /**< The length of the file data. */ -}; - -/** - * Open a file in the read-only file system. - * - * \param name The name of the file. - * - * \param file The file pointer, which must be allocated by caller and - * will be filled in by the function. - */ -int fs_open(const char *name, struct fs_file *file); - -#ifdef FS_STATISTICS -#if FS_STATISTICS == 1 -u16_t fs_count(char *name); -#endif /* FS_STATISTICS */ -#endif /* FS_STATISTICS */ - -/** - * Initialize the read-only file system. - */ -void fs_init(void); - -#endif /* __FS_H__ */ diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/fs/404.html b/Demo/uIP_Demo_Rowley_ARM7/uip/fs/404.html deleted file mode 100644 index 8d6beec83..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/uip/fs/404.html +++ /dev/null @@ -1 +0,0 @@ -

404 - file not found

\ No newline at end of file diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/fs/about.html b/Demo/uIP_Demo_Rowley_ARM7/uip/fs/about.html deleted file mode 100644 index 4c886897b..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/uip/fs/about.html +++ /dev/null @@ -1,18 +0,0 @@ - - -
-
-

Welcome

-

-These web pages are served by the small web server running on top of -the uIP TCP/IP -stack. -

-

-Click on the links above to see some status information about the web -server and the TCP/IP stack. -

-
-
- - \ No newline at end of file diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/fs/cgi/files b/Demo/uIP_Demo_Rowley_ARM7/uip/fs/cgi/files deleted file mode 100644 index 64e0b5005..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/uip/fs/cgi/files +++ /dev/null @@ -1,28 +0,0 @@ -# This script shows the access statistics for different files on the -# web server. -# -# First, we include the HTML header. -i /files_header.html -# Print out the name of the file, and call the function that prints -# the access statistics of that file. -t /index.html -c b /index.html -t /about.html -c b /about.html -t /control.html -c b /control.html -t /img/bg.png -c b /img/bg.png -t /404.html -c b /404.html -t /cgi/files -c b /cgi/files -t /cgi/stats -c b /cgi/stats -t /cgi/tcp -c b /cgi/tcp -t -# Include the HTML footer. -i /files_footer.plain -# End of script. -. \ No newline at end of file diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/fs/cgi/stats b/Demo/uIP_Demo_Rowley_ARM7/uip/fs/cgi/stats deleted file mode 100644 index 2c71c90dc..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/uip/fs/cgi/stats +++ /dev/null @@ -1,4 +0,0 @@ -i /stats_header.html -c a -i /stats_footer.plain -. diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/fs/cgi/tcp b/Demo/uIP_Demo_Rowley_ARM7/uip/fs/cgi/tcp deleted file mode 100644 index 14efd3700..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/uip/fs/cgi/tcp +++ /dev/null @@ -1,4 +0,0 @@ -i /tcp_header.html -c c -i /tcp_footer.plain -. \ No newline at end of file diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/fs/control.html b/Demo/uIP_Demo_Rowley_ARM7/uip/fs/control.html deleted file mode 100644 index ce28dbe7d..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/uip/fs/control.html +++ /dev/null @@ -1,14 +0,0 @@ - - -
-
-

uIP web server test pages

-[ About | -Connections | -Files | -Statistics ] -
-
- - \ No newline at end of file diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/fs/files_footer.plain b/Demo/uIP_Demo_Rowley_ARM7/uip/fs/files_footer.plain deleted file mode 100644 index 0b6dceb4f..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/uip/fs/files_footer.plain +++ /dev/null @@ -1,3 +0,0 @@ - - - diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/fs/files_header.html b/Demo/uIP_Demo_Rowley_ARM7/uip/fs/files_header.html deleted file mode 100644 index 25d86501e..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/uip/fs/files_header.html +++ /dev/null @@ -1,4 +0,0 @@ - - -
- diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/fs/img/bg.png b/Demo/uIP_Demo_Rowley_ARM7/uip/fs/img/bg.png deleted file mode 100644 index 18533b369..000000000 Binary files a/Demo/uIP_Demo_Rowley_ARM7/uip/fs/img/bg.png and /dev/null differ diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/fs/index.html b/Demo/uIP_Demo_Rowley_ARM7/uip/fs/index.html deleted file mode 100644 index 3429ef3af..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/uip/fs/index.html +++ /dev/null @@ -1,14 +0,0 @@ - -uIP web server test page - - - - - - - -<body> -Your browser must support frames -</body> - - \ No newline at end of file diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/fs/stats_footer.plain b/Demo/uIP_Demo_Rowley_ARM7/uip/fs/stats_footer.plain deleted file mode 100644 index 0b6dceb4f..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/uip/fs/stats_footer.plain +++ /dev/null @@ -1,3 +0,0 @@ -
- - diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/fs/stats_header.html b/Demo/uIP_Demo_Rowley_ARM7/uip/fs/stats_header.html deleted file mode 100644 index 4efaddf5b..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/uip/fs/stats_header.html +++ /dev/null @@ -1,30 +0,0 @@ - - -
- -
-
-IP           Packets dropped
-             Packets received
-             Packets sent
-IP errors    IP version/header length
-             IP length, high byte
-             IP length, low byte
-             IP fragments
-             Header checksum
-             Wrong protocol
-ICMP	     Packets dropped
-             Packets received
-             Packets sent
-             Type errors
-TCP          Packets dropped
-             Packets received
-             Packets sent
-             Checksum errors
-             Data packets without ACKs
-             Resets
-             Retransmissions
-	     No connection avaliable
-	     Connection attempts to closed ports
-
-
\ No newline at end of file
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/fs/tcp_footer.plain b/Demo/uIP_Demo_Rowley_ARM7/uip/fs/tcp_footer.plain
deleted file mode 100644
index 442c17a58..000000000
--- a/Demo/uIP_Demo_Rowley_ARM7/uip/fs/tcp_footer.plain
+++ /dev/null
@@ -1,5 +0,0 @@
-
-
-
- - \ No newline at end of file diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/fs/tcp_header.html b/Demo/uIP_Demo_Rowley_ARM7/uip/fs/tcp_header.html deleted file mode 100644 index 1a5057167..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/uip/fs/tcp_header.html +++ /dev/null @@ -1,6 +0,0 @@ - - -
- - - diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/fsdata.c b/Demo/uIP_Demo_Rowley_ARM7/uip/fsdata.c deleted file mode 100644 index ff855e7dc..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/uip/fsdata.c +++ /dev/null @@ -1,619 +0,0 @@ -static const char data_cgi_files[] = { - /* /cgi/files */ - 0x2f, 0x63, 0x67, 0x69, 0x2f, 0x66, 0x69, 0x6c, 0x65, 0x73, 0, - 0x23, 0x20, 0x54, 0x68, 0x69, 0x73, 0x20, 0x73, 0x63, 0x72, - 0x69, 0x70, 0x74, 0x20, 0x73, 0x68, 0x6f, 0x77, 0x73, 0x20, - 0x74, 0x68, 0x65, 0x20, 0x61, 0x63, 0x63, 0x65, 0x73, 0x73, - 0x20, 0x73, 0x74, 0x61, 0x74, 0x69, 0x73, 0x74, 0x69, 0x63, - 0x73, 0x20, 0x66, 0x6f, 0x72, 0x20, 0x64, 0x69, 0x66, 0x66, - 0x65, 0x72, 0x65, 0x6e, 0x74, 0x20, 0x66, 0x69, 0x6c, 0x65, - 0x73, 0x20, 0x6f, 0x6e, 0x20, 0x74, 0x68, 0x65, 0xa, 0x23, - 0x20, 0x77, 0x65, 0x62, 0x20, 0x73, 0x65, 0x72, 0x76, 0x65, - 0x72, 0x2e, 0xa, 0x23, 0xa, 0x23, 0x20, 0x46, 0x69, 0x72, - 0x73, 0x74, 0x2c, 0x20, 0x77, 0x65, 0x20, 0x69, 0x6e, 0x63, - 0x6c, 0x75, 0x64, 0x65, 0x20, 0x74, 0x68, 0x65, 0x20, 0x48, - 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11}}; - -const struct fsdata_file file_cgi_stats[] = {{file_cgi_files, data_cgi_stats, data_cgi_stats + 11, sizeof(data_cgi_stats) - 11}}; - -const struct fsdata_file file_cgi_tcp[] = {{file_cgi_stats, data_cgi_tcp, data_cgi_tcp + 9, sizeof(data_cgi_tcp) - 9}}; - -const struct fsdata_file file_img_bg_png[] = {{file_cgi_tcp, data_img_bg_png, data_img_bg_png + 12, sizeof(data_img_bg_png) - 12}}; - -const struct fsdata_file file_about_html[] = {{file_img_bg_png, data_about_html, data_about_html + 12, sizeof(data_about_html) - 12}}; - -const struct fsdata_file file_control_html[] = {{file_about_html, data_control_html, data_control_html + 14, sizeof(data_control_html) - 14}}; - -const struct fsdata_file file_404_html[] = {{file_control_html, data_404_html, data_404_html + 10, sizeof(data_404_html) - 10}}; - -const struct fsdata_file file_files_footer_plain[] = {{file_404_html, data_files_footer_plain, data_files_footer_plain + 20, sizeof(data_files_footer_plain) - 20}}; - -const struct fsdata_file file_files_header_html[] = {{file_files_footer_plain, data_files_header_html, data_files_header_html + 19, sizeof(data_files_header_html) - 19}}; - -const struct fsdata_file file_index_html[] = {{file_files_header_html, data_index_html, data_index_html + 12, sizeof(data_index_html) - 12}}; - -const struct fsdata_file file_stats_footer_plain[] = {{file_index_html, data_stats_footer_plain, data_stats_footer_plain + 20, sizeof(data_stats_footer_plain) - 20}}; - -const struct fsdata_file file_stats_header_html[] = {{file_stats_footer_plain, data_stats_header_html, data_stats_header_html + 19, sizeof(data_stats_header_html) - 19}}; - -const struct fsdata_file file_tcp_footer_plain[] = {{file_stats_header_html, data_tcp_footer_plain, data_tcp_footer_plain + 18, sizeof(data_tcp_footer_plain) - 18}}; - -const struct fsdata_file file_tcp_header_html[] = {{file_tcp_footer_plain, data_tcp_header_html, data_tcp_header_html + 17, sizeof(data_tcp_header_html) - 17}}; - -#define FS_ROOT file_tcp_header_html - -#define FS_NUMFILES 14 diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/fsdata.h b/Demo/uIP_Demo_Rowley_ARM7/uip/fsdata.h deleted file mode 100644 index 94086c4df..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/uip/fsdata.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2001, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - * $Id: fsdata.h,v 1.4.2.1 2003/10/04 22:54:06 adam Exp $ - */ -#ifndef __FSDATA_H__ -#define __FSDATA_H__ - -#include "uipopt.h" - -struct fsdata_file { - const struct fsdata_file *next; - const char *name; - const char *data; - const int len; -#ifdef FS_STATISTICS -#if FS_STATISTICS == 1 - u16_t count; -#endif /* FS_STATISTICS */ -#endif /* FS_STATISTICS */ -}; - -struct fsdata_file_noconst { - struct fsdata_file *next; - char *name; - char *data; - int len; -#ifdef FS_STATISTICS -#if FS_STATISTICS == 1 - u16_t count; -#endif /* FS_STATISTICS */ -#endif /* FS_STATISTICS */ -}; - -#endif /* __FSDATA_H__ */ diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/httpd.c b/Demo/uIP_Demo_Rowley_ARM7/uip/httpd.c deleted file mode 100644 index 9d2c6e599..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/uip/httpd.c +++ /dev/null @@ -1,373 +0,0 @@ -/** - * \addtogroup exampleapps - * @{ - */ - -/** - * \defgroup httpd Web server - * @{ - * - * The uIP web server is a very simplistic implementation of an HTTP - * server. It can serve web pages and files from a read-only ROM - * filesystem, and provides a very small scripting language. - * - * The script language is very simple and works as follows. Each - * script line starts with a command character, either "i", "t", "c", - * "#" or ".". The "i" command tells the script interpreter to - * "include" a file from the virtual file system and output it to the - * web browser. The "t" command should be followed by a line of text - * that is to be output to the browser. The "c" command is used to - * call one of the C functions from the httpd-cgi.c file. A line that - * starts with a "#" is ignored (i.e., the "#" denotes a comment), and - * the "." denotes the last script line. - * - * The script that produces the file statistics page looks somewhat - * like this: - * - \code -i /header.html -t

File statistics


RemoteStateRetransmissionsTimerFlags
-t
/index.html -c a /index.html -t
/cgi/files -c a /cgi/files -t
/cgi/tcp -c a /cgi/tcp -t
/404.html -c a /404.html -t
-i /footer.plain -. - \endcode - * - */ - - -/** - * \file - * HTTP server. - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2001, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: httpd.c,v 1.28.2.6 2003/10/07 13:22:27 adam Exp $ - * - */ - - -#include "uip.h" -#include "httpd.h" -#include "fs.h" -#include "fsdata.h" -#include "cgi.h" - -#define NULL (void *)0 - -/* The HTTP server states: */ -#define HTTP_NOGET 0 -#define HTTP_FILE 1 -#define HTTP_TEXT 2 -#define HTTP_FUNC 3 -#define HTTP_END 4 - -#ifdef DEBUG -#include -#define PRINT(x) -#define PRINTLN(x) -#else /* DEBUG */ -#define PRINT(x) -#define PRINTLN(x) -#endif /* DEBUG */ - -struct httpd_state *hs; - -extern const struct fsdata_file file_index_html; -extern const struct fsdata_file file_404_html; - -static void next_scriptline(void); -static void next_scriptstate(void); - -#define ISO_G 0x47 -#define ISO_E 0x45 -#define ISO_T 0x54 -#define ISO_slash 0x2f -#define ISO_c 0x63 -#define ISO_g 0x67 -#define ISO_i 0x69 -#define ISO_space 0x20 -#define ISO_nl 0x0a -#define ISO_cr 0x0d -#define ISO_a 0x61 -#define ISO_t 0x74 -#define ISO_hash 0x23 -#define ISO_period 0x2e - -#define httpPORT 80 - -/*-----------------------------------------------------------------------------------*/ -/** - * Initialize the web server. - * - * Starts to listen for incoming connection requests on TCP port 80. - */ -/*-----------------------------------------------------------------------------------*/ -void -httpd_init(void) -{ - fs_init(); - - /* Listen to port 80. */ - uip_listen(HTONS(httpPORT)); -} -/*-----------------------------------------------------------------------------------*/ -void -httpd_appcall(void) -{ - struct fs_file fsfile; - - u8_t i; - - switch(uip_conn->lport) { - /* This is the web server: */ - case HTONS(httpPORT): - /* Pick out the application state from the uip_conn structure. */ - hs = (struct httpd_state *)(uip_conn->appstate); - - /* We use the uip_ test functions to deduce why we were - called. If uip_connected() is non-zero, we were called - because a remote host has connected to us. If - uip_newdata() is non-zero, we were called because the - remote host has sent us new data, and if uip_acked() is - non-zero, the remote host has acknowledged the data we - previously sent to it. */ - if(uip_connected()) { - /* Since we have just been connected with the remote host, we - reset the state for this connection. The ->count variable - contains the amount of data that is yet to be sent to the - remote host, and the ->state is set to HTTP_NOGET to signal - that we haven't received any HTTP GET request for this - connection yet. */ - - hs->state = HTTP_NOGET; - hs->count = 0; - return; - - } else if(uip_poll()) { - /* If we are polled ten times, we abort the connection. This is - because we don't want connections lingering indefinately in - the system. */ - if(hs->count++ >= 10) { - uip_abort(); - } - return; - } else if(uip_newdata() && hs->state == HTTP_NOGET) { - /* This is the first data we receive, and it should contain a - GET. */ - - /* Check for GET. */ - if(uip_appdata[0] != ISO_G || - uip_appdata[1] != ISO_E || - uip_appdata[2] != ISO_T || - uip_appdata[3] != ISO_space) { - /* If it isn't a GET, we abort the connection. */ - uip_abort(); - return; - } - - /* Find the file we are looking for. */ - for(i = 4; i < 40; ++i) { - if(uip_appdata[i] == ISO_space || - uip_appdata[i] == ISO_cr || - uip_appdata[i] == ISO_nl) { - uip_appdata[i] = 0; - break; - } - } - - PRINT("request for file "); - PRINTLN(&uip_appdata[4]); - - /* Check for a request for "/". */ - if(uip_appdata[4] == ISO_slash && - uip_appdata[5] == 0) { - fs_open(file_index_html.name, &fsfile); - } else { - if(!fs_open((const char *)&uip_appdata[4], &fsfile)) { - PRINTLN("couldn't open file"); - fs_open(file_404_html.name, &fsfile); - } - } - - - if(uip_appdata[4] == ISO_slash && - uip_appdata[5] == ISO_c && - uip_appdata[6] == ISO_g && - uip_appdata[7] == ISO_i && - uip_appdata[8] == ISO_slash) { - /* If the request is for a file that starts with "/cgi/", we - prepare for invoking a script. */ - hs->script = fsfile.data; - next_scriptstate(); - } else { - hs->script = NULL; - /* The web server is now no longer in the HTTP_NOGET state, but - in the HTTP_FILE state since is has now got the GET from - the client and will start transmitting the file. */ - hs->state = HTTP_FILE; - - /* Point the file pointers in the connection state to point to - the first byte of the file. */ - hs->dataptr = fsfile.data; - hs->count = fsfile.len; - } - } - - - if(hs->state != HTTP_FUNC) { - /* Check if the client (remote end) has acknowledged any data that - we've previously sent. If so, we move the file pointer further - into the file and send back more data. If we are out of data to - send, we close the connection. */ - if(uip_acked()) { - if(hs->count >= uip_conn->len) { - hs->count -= uip_conn->len; - hs->dataptr += uip_conn->len; - } else { - hs->count = 0; - } - - if(hs->count == 0) { - if(hs->script != NULL) { - next_scriptline(); - next_scriptstate(); - } else { - uip_close(); - } - } - } - } else { - /* Call the CGI function. */ - if(cgitab[hs->script[2] - ISO_a](uip_acked())) { - /* If the function returns non-zero, we jump to the next line - in the script. */ - next_scriptline(); - next_scriptstate(); - } - } - - if(hs->state != HTTP_FUNC && !uip_poll()) { - /* Send a piece of data, but not more than the MSS of the - connection. */ - uip_send(hs->dataptr, hs->count); - } - - /* Finally, return to uIP. Our outgoing packet will soon be on its - way... */ - return; - - default: - /* Should never happen. */ - uip_abort(); - break; - } -} -/*-----------------------------------------------------------------------------------*/ -/* next_scriptline(): - * - * Reads the script until it finds a newline. */ -static void -next_scriptline(void) -{ - /* Loop until we find a newline character. */ - do { - ++(hs->script); - } while(hs->script[0] != ISO_nl); - - /* Eat up the newline as well. */ - ++(hs->script); -} -/*-----------------------------------------------------------------------------------*/ -/* next_sciptstate: - * - * Reads one line of script and decides what to do next. - */ -static void -next_scriptstate(void) -{ - struct fs_file fsfile; - u8_t i; - - again: - switch(hs->script[0]) { - case ISO_t: - /* Send a text string. */ - hs->state = HTTP_TEXT; - hs->dataptr = &hs->script[2]; - - /* Calculate length of string. */ - for(i = 0; hs->dataptr[i] != ISO_nl; ++i); - hs->count = i; - break; - case ISO_c: - /* Call a function. */ - hs->state = HTTP_FUNC; - hs->dataptr = NULL; - hs->count = 0; - cgitab[hs->script[2] - ISO_a](0); - break; - case ISO_i: - /* Include a file. */ - hs->state = HTTP_FILE; - if(!fs_open(&hs->script[2], &fsfile)) { - uip_abort(); - } - hs->dataptr = fsfile.data; - hs->count = fsfile.len; - break; - case ISO_hash: - /* Comment line. */ - next_scriptline(); - goto again; - break; - case ISO_period: - /* End of script. */ - hs->state = HTTP_END; - uip_close(); - break; - default: - uip_abort(); - break; - } -} -/*-----------------------------------------------------------------------------------*/ -/** @} */ -/** @} */ diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/httpd.h b/Demo/uIP_Demo_Rowley_ARM7/uip/httpd.h deleted file mode 100644 index 34d6bb35f..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/uip/httpd.h +++ /dev/null @@ -1,77 +0,0 @@ -/** - * \addtogroup httpd - * @{ - */ - -/** - * \file - * HTTP server header file. - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2001, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: httpd.h,v 1.4.2.3 2003/10/06 22:56:44 adam Exp $ - * - */ - -#ifndef __HTTPD_H__ -#define __HTTPD_H__ - -void httpd_init(void); -void httpd_appcall(void); - -/* UIP_APPCALL: the name of the application function. This function - must return void and take no arguments (i.e., C type "void - appfunc(void)"). */ -#ifndef UIP_APPCALL -#define UIP_APPCALL httpd_appcall -#endif - -struct httpd_state { - u8_t state; - u16_t count; - char *dataptr; - char *script; -}; - - -/* UIP_APPSTATE_SIZE: The size of the application-specific state - stored in the uip_conn structure. */ -#ifndef UIP_APPSTATE_SIZE -#define UIP_APPSTATE_SIZE (sizeof(struct httpd_state)) -#endif - -#define FS_STATISTICS 1 - -extern struct httpd_state *hs; - -#endif /* __HTTPD_H__ */ diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/main_led b/Demo/uIP_Demo_Rowley_ARM7/uip/main_led deleted file mode 100644 index 8fe01ea6d..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/uip/main_led +++ /dev/null @@ -1,67 +0,0 @@ -// Copyright (c) 2001-2004 Rowley Associates Limited. -// -// This file may be distributed under the terms of the License Agreement -// provided with this software. -// -// THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE -// WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. -// -//////////////////////////////////////////////////////////////////////////////// -// -// Olimex LPC-P1 LED Example -// -// Description -// ----------- -// This example demonstrates writing to the programmable peripheral interface. -// -//////////////////////////////////////////////////////////////////////////////// - -#include - -#define LED_RED (1<<8) -#define LED_GREEN (1<<10) -#define LED_YELLOW (1<<11) - -#define LED1 LED_YELLOW - -static void -ledInit() -{ - IODIR |= LED1; - IOSET = LED1; -} - -static void -ledOn(void) -{ - IOCLR = LED1; -} - -static void -ledOff(void) -{ - IOSET = LED1; -} - -void -delay(int d) -{ - for(; d; --d); -} - -int -main(void) -{ - MAMCR = 2; - ledInit(); - while (1) - { - ledOn(); - delay(100000); - ledOff(); - delay(100000); - } - return 0; -} - - diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/makefsdata b/Demo/uIP_Demo_Rowley_ARM7/uip/makefsdata deleted file mode 100644 index f5f75f174..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/uip/makefsdata +++ /dev/null @@ -1,93 +0,0 @@ -#!/usr/bin/perl - -open(OUTPUT, "> fsdata.c"); - -chdir("fs"); -open(FILES, "find . -type f |"); - -while($file = ) { - - # Do not include files in CVS directories nor backup files. - if($file =~ /(CVS|~)/) { - next; - } - - chop($file); - - open(HEADER, "> /tmp/header") || die $!; - if($file =~ /404.html/) { - print(HEADER "HTTP/1.0 404 File not found\r\n"); - } else { - print(HEADER "HTTP/1.0 200 OK\r\n"); - } - print(HEADER "Server: uIP/0.9 (http://dunkels.com/adam/uip/)\r\n"); - if($file =~ /\.html$/) { - print(HEADER "Content-type: text/html\r\n"); - } elsif($file =~ /\.gif$/) { - print(HEADER "Content-type: image/gif\r\n"); - } elsif($file =~ /\.png$/) { - print(HEADER "Content-type: image/png\r\n"); - } elsif($file =~ /\.jpg$/) { - print(HEADER "Content-type: image/jpeg\r\n"); - } else { - print(HEADER "Content-type: text/plain\r\n"); - } - print(HEADER "\r\n"); - close(HEADER); - - unless($file =~ /\.plain$/ || $file =~ /cgi/) { - system("cat /tmp/header $file > /tmp/file"); - } else { - system("cp $file /tmp/file"); - } - - open(FILE, "/tmp/file"); - unlink("/tmp/file"); - unlink("/tmp/header"); - - $file =~ s/\.//; - $fvar = $file; - $fvar =~ s-/-_-g; - $fvar =~ s-\.-_-g; - print(OUTPUT "static const char data".$fvar."[] = {\n"); - print(OUTPUT "\t/* $file */\n\t"); - for($j = 0; $j < length($file); $j++) { - printf(OUTPUT "%#02x, ", unpack("C", substr($file, $j, 1))); - } - printf(OUTPUT "0,\n"); - - - $i = 0; - while(read(FILE, $data, 1)) { - if($i == 0) { - print(OUTPUT "\t"); - } - printf(OUTPUT "%#02x, ", unpack("C", $data)); - $i++; - if($i == 10) { - print(OUTPUT "\n"); - $i = 0; - } - } - print(OUTPUT "};\n\n"); - close(FILE); - push(@fvars, $fvar); - push(@files, $file); -} - -for($i = 0; $i < @fvars; $i++) { - $file = $files[$i]; - $fvar = $fvars[$i]; - - if($i == 0) { - $prevfile = "NULL"; - } else { - $prevfile = "file" . $fvars[$i - 1]; - } - print(OUTPUT "const struct fsdata_file file".$fvar."[] = {{$prevfile, data$fvar, "); - print(OUTPUT "data$fvar + ". (length($file) + 1) .", "); - print(OUTPUT "sizeof(data$fvar) - ". (length($file) + 1) ."}};\n\n"); -} - -print(OUTPUT "#define FS_ROOT file$fvars[$i - 1]\n\n"); -print(OUTPUT "#define FS_NUMFILES $i"); diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/memb.c b/Demo/uIP_Demo_Rowley_ARM7/uip/memb.c deleted file mode 100644 index 56e663446..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/uip/memb.c +++ /dev/null @@ -1,152 +0,0 @@ -/** - * \addtogroup exampleapps - * @{ - */ - -/** - * \file - * Memory block allocation routines. - * \author Adam Dunkels - * - * The memory block allocation routines provide a simple yet powerful - * set of functions for managing a set of memory blocks of fixed - * size. A set of memory blocks is statically declared with the - * MEMB() macro. Memory blocks are allocated from the declared - * memory by the memb_alloc() function, and are deallocated with the - * memb_free() function. - * - * \note Because of namespace clashes only one MEMB() can be - * declared per C module, and the name scope of a MEMB() memory - * block is local to each C module. - * - * The following example shows how to declare and use a memory block - * called "cmem" which has 8 chunks of memory with each memory chunk - * being 20 bytes large. - * - \code - MEMB(cmem, 20, 8); - - int main(int argc, char *argv[]) { - char *ptr; - - memb_init(&cmem); - - ptr = memb_alloc(&cmem); - - if(ptr != NULL) { - do_something(ptr); - } else { - printf("Could not allocate memory.\n"); - } - - if(memb_free(ptr) == 0) { - printf("Deallocation succeeded.\n"); - } - } - \endcode - * - */ - -#include - -#include "memb.h" - -/*------------------------------------------------------------------------------*/ -/** - * Initialize a memory block that was declared with MEMB(). - * - * \param m A memory block previosly declared with MEMB(). - */ -/*------------------------------------------------------------------------------*/ -void -memb_init(struct memb_blocks *m) -{ - memset(m->mem, (m->size + 1) * m->num, 0); -} -/*------------------------------------------------------------------------------*/ -/** - * Allocate a memory block from a block of memory declared with MEMB(). - * - * \param m A memory block previosly declared with MEMB(). - */ -/*------------------------------------------------------------------------------*/ -char * -memb_alloc(struct memb_blocks *m) -{ - int i; - char *ptr; - - ptr = m->mem; - for(i = 0; i < m->num; ++i) { - if(*ptr == 0) { - /* If this block was unused, we increase the reference count to - indicate that it now is used and return a pointer to the - first byte following the reference counter. */ - ++*ptr; - return ptr + 1; - } - ptr += m->size + 1; - } - - /* No free block was found, so we return NULL to indicate failure to - allocate block. */ - return NULL; -} -/*------------------------------------------------------------------------------*/ -/** - * Deallocate a memory block from a memory block previously declared - * with MEMB(). - * - * \param m m A memory block previosly declared with MEMB(). - * - * \param ptr A pointer to the memory block that is to be deallocated. - * - * \return The new reference count for the memory block (should be 0 - * if successfully deallocated) or -1 if the pointer "ptr" did not - * point to a legal memory block. - */ -/*------------------------------------------------------------------------------*/ -char -memb_free(struct memb_blocks *m, char *ptr) -{ - int i; - char *ptr2; - - /* Walk through the list of blocks and try to find the block to - which the pointer "ptr" points to. */ - ptr2 = m->mem; - for(i = 0; i < m->num; ++i) { - - if(ptr2 == ptr - 1) { - /* We've found to block to which "ptr" points so we decrease the - reference count and return the new value of it. */ - return --*ptr2; - } - ptr2 += m->size + 1; - } - return -1; -} -/*------------------------------------------------------------------------------*/ -/** - * Increase the reference count for a memory chunk. - * - * \note No sanity checks are currently made. - * - * \param m m A memory block previosly declared with MEMB(). - * - * \param ptr A pointer to the memory chunk for which the reference - * count should be increased. - * - * \return The new reference count. - */ -/*------------------------------------------------------------------------------*/ -char -memb_ref(struct memb_blocks *m, char *ptr) -{ - return ++*(ptr - 1); -} -/*------------------------------------------------------------------------------*/ - - - - diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/memb.h b/Demo/uIP_Demo_Rowley_ARM7/uip/memb.h deleted file mode 100644 index 505846f4d..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/uip/memb.h +++ /dev/null @@ -1,43 +0,0 @@ -/** - * \addtogroup exampleapps - * @{ - */ - -/** - * \file - * Memory block allocation routines. - * \author Adam Dunkels - * - */ - -#ifndef __MEMB_H__ -#define __MEMB_H__ - -/** - * Declare a memory block. - * - * \param name The name of the memory block (later used with - * memb_init(), memb_alloc() and memb_free()). - * - * \param size The size of each memory chunk, in bytes. - * - * \param num The total number of memory chunks in the block. - * - */ -#define MEMB(name, size, num) \ - static char memb_mem[(size + 1) * num]; \ - static struct memb_blocks name = {size, num, memb_mem} - -struct memb_blocks { - unsigned short size; - unsigned short num; - char *mem; -}; - -void memb_init(struct memb_blocks *m); -char *memb_alloc(struct memb_blocks *m); -char memb_ref(struct memb_blocks *m, char *ptr); -char memb_free(struct memb_blocks *m, char *ptr); - - -#endif /* __MEMB_H__ */ diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/slipdev.c b/Demo/uIP_Demo_Rowley_ARM7/uip/slipdev.c deleted file mode 100644 index fc968c82e..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/uip/slipdev.c +++ /dev/null @@ -1,202 +0,0 @@ -/** - * \addtogroup uip - * @{ - */ - -/** - * \defgroup slip Serial Line IP (SLIP) protocol - * @{ - * - * The SLIP protocol is a very simple way to transmit IP packets over - * a serial line. It does not provide any framing or error control, - * and is therefore not very widely used today. - * - * This SLIP implementation requires two functions for accessing the - * serial device: slipdev_char_poll() and slipdev_char_put(). These - * must be implemented specifically for the system on which the SLIP - * protocol is to be run. - */ - -/** - * \file - * SLIP protocol implementation - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2001, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: slipdev.c,v 1.1.2.3 2003/10/07 13:23:01 adam Exp $ - * - */ - -/* - * This is a generic implementation of the SLIP protocol over an RS232 - * (serial) device. - * - * Huge thanks to Ullrich von Bassewitz of cc65 fame for - * and endless supply of bugfixes, insightsful comments and - * suggestions, and improvements to this code! - */ - -#include "uip.h" - -#define SLIP_END 0300 -#define SLIP_ESC 0333 -#define SLIP_ESC_END 0334 -#define SLIP_ESC_ESC 0335 - -static u8_t slip_buf[UIP_BUFSIZE]; - -static u16_t len, tmplen; -static u8_t lastc; - -/*-----------------------------------------------------------------------------------*/ -/** - * Send the packet in the uip_buf and uip_appdata buffers using the - * SLIP protocol. - * - * The first 40 bytes of the packet (the IP and TCP headers) are read - * from the uip_buf buffer, and the following bytes (the application - * data) are read from the uip_appdata buffer. - * - */ -/*-----------------------------------------------------------------------------------*/ -void -slipdev_send(void) -{ - u16_t i; - u8_t *ptr; - u8_t c; - - slipdev_char_put(SLIP_END); - - ptr = uip_buf; - for(i = 0; i < uip_len; ++i) { - if(i == 40) { - ptr = (u8_t *)uip_appdata; - } - c = *ptr++; - switch(c) { - case SLIP_END: - slipdev_char_put(SLIP_ESC); - slipdev_char_put(SLIP_ESC_END); - break; - case SLIP_ESC: - slipdev_char_put(SLIP_ESC); - slipdev_char_put(SLIP_ESC_ESC); - break; - default: - slipdev_char_put(c); - break; - } - } - slipdev_char_put(SLIP_END); -} -/*-----------------------------------------------------------------------------------*/ -/** - * Poll the SLIP device for an available packet. - * - * This function will poll the SLIP device to see if a packet is - * available. It uses a buffer in which all avaliable bytes from the - * RS232 interface are read into. When a full packet has been read - * into the buffer, the packet is copied into the uip_buf buffer and - * the length of the packet is returned. - * - * \return The length of the packet placed in the uip_buf buffer, or - * zero if no packet is available. - */ -/*-----------------------------------------------------------------------------------*/ -u16_t -slipdev_poll(void) -{ - u8_t c; - - while(slipdev_char_poll(c)) { - switch(c) { - case SLIP_ESC: - lastc = c; - break; - - case SLIP_END: - lastc = c; - /* End marker found, we copy our input buffer to the uip_buf - buffer and return the size of the packet we copied. */ - memcpy(uip_buf, slip_buf, len); - tmplen = len; - len = 0; - return tmplen; - - default: - if(lastc == SLIP_ESC) { - lastc = c; - /* Previous read byte was an escape byte, so this byte will be - interpreted differently from others. */ - switch(c) { - case SLIP_ESC_END: - c = SLIP_END; - break; - case SLIP_ESC_ESC: - c = SLIP_ESC; - break; - } - } else { - lastc = c; - } - - slip_buf[len] = c; - ++len; - - if(len > UIP_BUFSIZE) { - len = 0; - } - - break; - } - } - return 0; -} -/*-----------------------------------------------------------------------------------*/ -/** - * Initialize the SLIP module. - * - * This function does not initialize the underlying RS232 device, but - * only the SLIP part. - */ -/*-----------------------------------------------------------------------------------*/ -void -slipdev_init(void) -{ - lastc = len = 0; -} -/*-----------------------------------------------------------------------------------*/ - -/** @} */ -/** @} */ diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/slipdev.h b/Demo/uIP_Demo_Rowley_ARM7/uip/slipdev.h deleted file mode 100644 index 3fbfe2d2d..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/uip/slipdev.h +++ /dev/null @@ -1,88 +0,0 @@ -/** - * \addtogroup slip - * @{ - */ - -/** - * \file - * SLIP header file. - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2001, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: slipdev.h,v 1.1.2.3 2003/10/06 22:42:51 adam Exp $ - * - */ - -#ifndef __SLIPDEV_H__ -#define __SLIPDEV_H__ - -#include "uip.h" - -/** - * Put a character on the serial device. - * - * This function is used by the SLIP implementation to put a character - * on the serial device. It must be implemented specifically for the - * system on which the SLIP implementation is to be run. - * - * \param c The character to be put on the serial device. - */ -void slipdev_char_put(u8_t c); - -/** - * Poll the serial device for a character. - * - * This function is used by the SLIP implementation to poll the serial - * device for a character. It must be implemented specifically for the - * system on which the SLIP implementation is to be run. - * - * The function should return immediately regardless if a character is - * available or not. If a character is available it should be placed - * at the memory location pointed to by the pointer supplied by the - * arguement c. - * - * \param c A pointer to a byte that is filled in by the function with - * the received character, if available. - * - * \retval 0 If no character is available. - * \retval Non-zero If a character is available. - */ -u8_t slipdev_char_poll(u8_t *c); - -void slipdev_init(void); -void slipdev_send(void); -u16_t slipdev_poll(void); - -#endif /* __SLIPDEV_H__ */ - -/** @} */ diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/tapdev.c b/Demo/uIP_Demo_Rowley_ARM7/uip/tapdev.c deleted file mode 100644 index 0d23fc4d9..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/uip/tapdev.c +++ /dev/null @@ -1,171 +0,0 @@ -/* - * Copyright (c) 2001, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * Author: Adam Dunkels - * - * $Id: tapdev.c,v 1.7.2.1 2003/10/07 13:23:19 adam Exp $ - */ - - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef linux -#include -#include -#include -#define DEVTAP "/dev/net/tun" -#else /* linux */ -#define DEVTAP "/dev/tap0" -#endif /* linux */ - -#include "uip.h" - -static int fd; - -static unsigned long lasttime; -static struct timezone tz; - -/*-----------------------------------------------------------------------------------*/ -void -tapdev_init(void) -{ - char buf[1024]; - - fd = open(DEVTAP, O_RDWR); - if(fd == -1) { - perror("tapdev: tapdev_init: open"); - exit(1); - } - -#ifdef linux - { - struct ifreq ifr; - memset(&ifr, 0, sizeof(ifr)); - ifr.ifr_flags = IFF_TAP|IFF_NO_PI; - if (ioctl(fd, TUNSETIFF, (void *) &ifr) < 0) { - perror(buf); - exit(1); - } - } -#endif /* Linux */ - - snprintf(buf, sizeof(buf), "ifconfig tap0 inet %d.%d.%d.%d", - UIP_DRIPADDR0, UIP_DRIPADDR1, UIP_DRIPADDR2, UIP_DRIPADDR3); - system(buf); - - lasttime = 0; -} -/*-----------------------------------------------------------------------------------*/ -unsigned int -tapdev_read(void) -{ - fd_set fdset; - struct timeval tv, now; - int ret; - - if(lasttime >= 500000) { - lasttime = 0; - return 0; - } - - tv.tv_sec = 0; - tv.tv_usec = 500000 - lasttime; - - - FD_ZERO(&fdset); - FD_SET(fd, &fdset); - - gettimeofday(&now, &tz); - ret = select(fd + 1, &fdset, NULL, NULL, &tv); - if(ret == 0) { - lasttime = 0; - return 0; - } - ret = read(fd, uip_buf, UIP_BUFSIZE); - if(ret == -1) { - perror("tap_dev: tapdev_read: read"); - } - gettimeofday(&tv, &tz); - lasttime += (tv.tv_sec - now.tv_sec) * 1000000 + (tv.tv_usec - now.tv_usec); - - return ret; -} -/*-----------------------------------------------------------------------------------*/ -void -tapdev_send(void) -{ - int ret; - struct iovec iov[2]; - -#ifdef linux - { - char tmpbuf[UIP_BUFSIZE]; - int i; - - for(i = 0; i < 40 + UIP_LLH_LEN; i++) { - tmpbuf[i] = uip_buf[i]; - } - - for(; i < uip_len; i++) { - tmpbuf[i] = uip_appdata[i - 40 - UIP_LLH_LEN]; - } - - ret = write(fd, tmpbuf, uip_len); - } -#else - - if(uip_len < 40 + UIP_LLH_LEN) { - ret = write(fd, uip_buf, uip_len + UIP_LLH_LEN); - } else { - iov[0].iov_base = uip_buf; - iov[0].iov_len = 40 + UIP_LLH_LEN; - iov[1].iov_base = (char *)uip_appdata; - iov[1].iov_len = uip_len - (40 + UIP_LLH_LEN); - - ret = writev(fd, iov, 2); - } -#endif - if(ret == -1) { - perror("tap_dev: tapdev_send: writev"); - exit(1); - } -} -/*-----------------------------------------------------------------------------------*/ diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/tapdev.h b/Demo/uIP_Demo_Rowley_ARM7/uip/tapdev.h deleted file mode 100644 index 66f1a4a71..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/uip/tapdev.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (c) 2001, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: tapdev.h,v 1.1.2.1 2003/10/04 22:54:17 adam Exp $ - * - */ - -#ifndef __TAPDEV_H__ -#define __TAPDEV_H__ - -void tapdev_init(void); -unsigned int tapdev_read(void); -void tapdev_send(void); - -#endif /* __TAPDEV_H__ */ diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/telnetd-shell.c b/Demo/uIP_Demo_Rowley_ARM7/uip/telnetd-shell.c deleted file mode 100644 index 7dff714ca..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/uip/telnetd-shell.c +++ /dev/null @@ -1,181 +0,0 @@ -/** - * \addtogroup telnetd - * @{ - */ - -/** - * \file - * An example telnet server shell - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2003, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the Contiki desktop OS. - * - * $Id: telnetd-shell.c,v 1.1.2.1 2003/10/06 22:56:22 adam Exp $ - * - */ - -#include "uip.h" -#include "telnetd.h" -#include - -struct ptentry { - char c; - void (* pfunc)(struct telnetd_state *s, char *str); -}; - -/*-----------------------------------------------------------------------------------*/ -static void -parse(struct telnetd_state *s, register char *str, struct ptentry *t) -{ - register struct ptentry *p; - char *sstr; - - sstr = str; - - /* Loop over the parse table entries in t in order to find one that - matches the first character in str. */ - for(p = t; p->c != 0; ++p) { - if(*str == p->c) { - /* Skip rest of the characters up to the first space. */ - while(*str != ' ') { - ++str; - } - - /* Skip all spaces.*/ - while(*str == ' ') { - ++str; - } - - /* Call parse table entry function and return. */ - p->pfunc(s, str); - return; - } - } - - /* Did not find matching entry in parse table. We just call the - default handler supplied by the caller and return. */ - p->pfunc(s, str); -} -/*-----------------------------------------------------------------------------------*/ -static void -exitt(struct telnetd_state *s, char *str) -{ - telnetd_close(s); -} -/*-----------------------------------------------------------------------------------*/ -static void -inttostr(register char *str, unsigned int i) -{ - str[0] = '0' + i / 100; - if(str[0] == '0') { - str[0] = ' '; - } - str[1] = '0' + (i / 10) % 10; - if(str[1] == '0') { - str[1] = ' '; - } - str[2] = '0' + i % 10; - str[3] = ' '; - str[4] = 0; -} -/*-----------------------------------------------------------------------------------*/ -static void -stats(struct telnetd_state *s, char *strr) -{ - char str[10]; - - inttostr(str, uip_stat.ip.recv); - telnetd_output(s, "IP packets received ", str); - inttostr(str, uip_stat.ip.sent); - telnetd_output(s, "IP packets sent ", str); - inttostr(str, uip_stat.ip.drop); - telnetd_output(s, "IP packets dropped ", str); - - inttostr(str, uip_stat.icmp.recv); - telnetd_output(s, "ICMP packets received ", str); - inttostr(str, uip_stat.icmp.sent); - telnetd_output(s, "ICMP packets sent ", str); - inttostr(str, uip_stat.icmp.drop); - telnetd_output(s, "ICMP packets dropped ", str); - - inttostr(str, uip_stat.tcp.recv); - telnetd_output(s, "TCP packets received ", str); - inttostr(str, uip_stat.tcp.sent); - telnetd_output(s, "TCP packets sent ", str); - inttostr(str, uip_stat.tcp.drop); - telnetd_output(s, "TCP packets dropped ", str); - inttostr(str, uip_stat.tcp.rexmit); - telnetd_output(s, "TCP packets retransmitted ", str); - inttostr(str, uip_stat.tcp.synrst); - telnetd_output(s, "TCP connection attempts ", str); -} -/*-----------------------------------------------------------------------------------*/ -static void -help(struct telnetd_state *s, char *str) -{ - telnetd_output(s, "Available commands:", ""); - telnetd_output(s, "stats - show uIP statistics", ""); - telnetd_output(s, "exit - exit shell", ""); - telnetd_output(s, "? - show this help", ""); -} -/*-----------------------------------------------------------------------------------*/ -static void -none(struct telnetd_state *s, char *str) -{ - if(strlen(str) > 0) { - telnetd_output(s, "Unknown command", ""); - } -} -/*-----------------------------------------------------------------------------------*/ -static struct ptentry configparsetab[] = - {{'s', stats}, - {'e', exitt}, - {'?', help}, - - /* Default action */ - {0, none}}; -/*-----------------------------------------------------------------------------------*/ -void -telnetd_connected(struct telnetd_state *s) -{ - telnetd_output(s, "uIP command shell", ""); - telnetd_output(s, "Type '?' for help", ""); - telnetd_prompt(s, "uIP-0.9> "); -} -/*-----------------------------------------------------------------------------------*/ -void -telnetd_input(struct telnetd_state *s, char *cmd) -{ - parse(s, cmd, configparsetab); - telnetd_prompt(s, "uIP-0.9> "); -} -/*-----------------------------------------------------------------------------------*/ diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/telnetd.c b/Demo/uIP_Demo_Rowley_ARM7/uip/telnetd.c deleted file mode 100644 index dba522271..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/uip/telnetd.c +++ /dev/null @@ -1,392 +0,0 @@ -/** - * \addtogroup exampleapps - * @{ - */ - -/** - * \defgroup telnetd Telnet server - * @{ - * - * The uIP telnet server provides a command based interface to uIP. It - * allows using the "telnet" application to access uIP, and implements - * the required telnet option negotiation. - * - * The code is structured in a way which makes it possible to add - * commands without having to rewrite the main telnet code. The main - * telnet code calls two callback functions, telnetd_connected() and - * telnetd_input(), when a telnet connection has been established and - * when a line of text arrives on a telnet connection. These two - * functions can be implemented in a way which suits the particular - * application or environment in which the uIP system is intended to - * be run. - * - * The uIP distribution contains an example telnet shell - * implementation that provides a basic set of commands. - */ - -/** - * \file - * Implementation of the Telnet server. - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2003, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: telnetd.c,v 1.1.2.2 2003/10/07 13:47:50 adam Exp $ - * - */ - -#include "uip.h" -#include "memb.h" -#include "telnetd.h" -#include - -#define ISO_nl 0x0a -#define ISO_cr 0x0d - -MEMB(linemem, TELNETD_LINELEN, TELNETD_NUMLINES); - -static u8_t i; - -#define STATE_NORMAL 0 -#define STATE_IAC 1 -#define STATE_WILL 2 -#define STATE_WONT 3 -#define STATE_DO 4 -#define STATE_DONT 5 -#define STATE_CLOSE 6 - -#define TELNET_IAC 255 -#define TELNET_WILL 251 -#define TELNET_WONT 252 -#define TELNET_DO 253 -#define TELNET_DONT 254 -/*-----------------------------------------------------------------------------------*/ -static char * -alloc_line(void) -{ - return memb_alloc(&linemem); -} -/*-----------------------------------------------------------------------------------*/ -static void -dealloc_line(char *line) -{ - memb_free(&linemem, line); -} -/*-----------------------------------------------------------------------------------*/ -static void -sendline(struct telnetd_state *s, char *line) -{ - static unsigned int i; - for(i = 0; i < TELNETD_NUMLINES; ++i) { - if(s->lines[i] == NULL) { - s->lines[i] = line; - break; - } - } - if(i == TELNETD_NUMLINES) { - dealloc_line(line); - } -} -/*-----------------------------------------------------------------------------------*/ -/** - * Close a telnet session. - * - * This function can be called from a telnet command in order to close - * the connection. - * - * \param s The connection which is to be closed. - * - */ -/*-----------------------------------------------------------------------------------*/ -void -telnetd_close(struct telnetd_state *s) -{ - s->state = STATE_CLOSE; -} -/*-----------------------------------------------------------------------------------*/ -/** - * Print a prompt on a telnet connection. - * - * This function can be called by the telnet command shell in order to - * print out a command prompt. - * - * \param s A telnet connection. - * - * \param str The command prompt. - * - */ -/*-----------------------------------------------------------------------------------*/ -void -telnetd_prompt(struct telnetd_state *s, char *str) -{ - char *line; - line = alloc_line(); - if(line != NULL) { - strncpy(line, str, TELNETD_LINELEN); - sendline(s, line); - } -} -/*-----------------------------------------------------------------------------------*/ -/** - * Print out a string on a telnet connection. - * - * This function can be called from a telnet command parser in order - * to print out a string of text on the connection. The two strings - * given as arguments to the function will be concatenated, a carrige - * return and a new line character will be added, and the line is - * sent. - * - * \param s The telnet connection. - * - * \param str1 The first string. - * - * \param str2 The second string. - * - */ -/*-----------------------------------------------------------------------------------*/ -void -telnetd_output(struct telnetd_state *s, char *str1, char *str2) -{ - static unsigned len; - char *line; - - line = alloc_line(); - if(line != NULL) { - len = strlen(str1); - strncpy(line, str1, TELNETD_LINELEN); - if(len < TELNETD_LINELEN) { - strncpy(line + len, str2, TELNETD_LINELEN - len); - } - len = strlen(line); - if(len < TELNETD_LINELEN - 2) { - line[len] = ISO_cr; - line[len+1] = ISO_nl; - line[len+2] = 0; - } - sendline(s, line); - } -} -/*-----------------------------------------------------------------------------------*/ -/** - * Initialize the telnet server. - * - * This function will perform the necessary initializations and start - * listening on TCP port 23. - */ -/*-----------------------------------------------------------------------------------*/ -void -telnetd_init(void) -{ - memb_init(&linemem); - uip_listen(HTONS(23)); -} -/*-----------------------------------------------------------------------------------*/ -static void -acked(struct telnetd_state *s) -{ - dealloc_line(s->lines[0]); - for(i = 1; i < TELNETD_NUMLINES; ++i) { - s->lines[i - 1] = s->lines[i]; - } -} -/*-----------------------------------------------------------------------------------*/ -static void -senddata(struct telnetd_state *s) -{ - if(s->lines[0] != NULL) { - uip_send(s->lines[0], strlen(s->lines[0])); - } -} -/*-----------------------------------------------------------------------------------*/ -static void -getchar(struct telnetd_state *s, u8_t c) -{ - if(c == ISO_cr) { - return; - } - - s->buf[(int)s->bufptr] = c; - if(s->buf[(int)s->bufptr] == ISO_nl || - s->bufptr == sizeof(s->buf) - 1) { - if(s->bufptr > 0) { - s->buf[(int)s->bufptr] = 0; - } - telnetd_input(s, s->buf); - s->bufptr = 0; - } else { - ++s->bufptr; - } -} -/*-----------------------------------------------------------------------------------*/ -static void -sendopt(struct telnetd_state *s, u8_t option, u8_t value) -{ - char *line; - line = alloc_line(); - if(line != NULL) { - line[0] = TELNET_IAC; - line[1] = option; - line[2] = value; - line[3] = 0; - sendline(s, line); - } -} -/*-----------------------------------------------------------------------------------*/ -static void -newdata(struct telnetd_state *s) -{ - u16_t len; - u8_t c; - - - len = uip_datalen(); - - while(len > 0 && s->bufptr < sizeof(s->buf)) { - c = *uip_appdata; - ++uip_appdata; - --len; - switch(s->state) { - case STATE_IAC: - if(c == TELNET_IAC) { - getchar(s, c); - s->state = STATE_NORMAL; - } else { - switch(c) { - case TELNET_WILL: - s->state = STATE_WILL; - break; - case TELNET_WONT: - s->state = STATE_WONT; - break; - case TELNET_DO: - s->state = STATE_DO; - break; - case TELNET_DONT: - s->state = STATE_DONT; - break; - default: - s->state = STATE_NORMAL; - break; - } - } - break; - case STATE_WILL: - /* Reply with a DONT */ - sendopt(s, TELNET_DONT, c); - s->state = STATE_NORMAL; - break; - - case STATE_WONT: - /* Reply with a DONT */ - sendopt(s, TELNET_DONT, c); - s->state = STATE_NORMAL; - break; - case STATE_DO: - /* Reply with a WONT */ - sendopt(s, TELNET_WONT, c); - s->state = STATE_NORMAL; - break; - case STATE_DONT: - /* Reply with a WONT */ - sendopt(s, TELNET_WONT, c); - s->state = STATE_NORMAL; - break; - case STATE_NORMAL: - if(c == TELNET_IAC) { - s->state = STATE_IAC; - } else { - getchar(s, c); - } - break; - } - - - } - -} -/*-----------------------------------------------------------------------------------*/ -void -telnetd_app(void) -{ - struct telnetd_state *s; - - s = (struct telnetd_state *)uip_conn->appstate; - - if(uip_connected()) { - - for(i = 0; i < TELNETD_NUMLINES; ++i) { - s->lines[i] = NULL; - } - s->bufptr = 0; - s->state = STATE_NORMAL; - - telnetd_connected(s); - senddata(s); - return; - } - - if(s->state == STATE_CLOSE) { - s->state = STATE_NORMAL; - uip_close(); - return; - } - - if(uip_closed()) { - telnetd_output(s, "Connection closed", ""); - } - - - if(uip_aborted()) { - telnetd_output(s, "Connection reset", ""); - } - - if(uip_timedout()) { - telnetd_output(s, "Connection timed out", ""); - } - - if(uip_acked()) { - acked(s); - } - - if(uip_newdata()) { - newdata(s); - } - - if(uip_rexmit() || - uip_newdata() || - uip_acked()) { - senddata(s); - } else if(uip_poll()) { - senddata(s); - } -} -/*-----------------------------------------------------------------------------------*/ diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/telnetd.h b/Demo/uIP_Demo_Rowley_ARM7/uip/telnetd.h deleted file mode 100644 index 254e44ff1..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/uip/telnetd.h +++ /dev/null @@ -1,114 +0,0 @@ -/** - * \addtogroup telnetd - * @{ - */ - -/** - * \file - * Header file for the telnet server. - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2002, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: telnetd.h,v 1.1.2.2 2003/10/07 13:22:27 adam Exp $ - * - */ -#ifndef __TELNETD_H__ -#define __TELNETD_H__ - -#include "uip.h" - -/** - * The maximum length of a telnet line. - * - * \hideinitializer - */ -#define TELNETD_LINELEN 36 - -/** - * The number of output lines being buffered for all telnet - * connections. - * - * \hideinitializer - */ -#define TELNETD_NUMLINES 2 - -/** - * A telnet connection structure. - */ -struct telnetd_state { - char *lines[TELNETD_NUMLINES]; - char buf[TELNETD_LINELEN]; - char bufptr; - u8_t state; -}; - - -/** - * Callback function that is called when a telnet connection has been - * established. - * - * \param s The telnet connection. - */ -void telnetd_connected(struct telnetd_state *s); - -/** - * Callback function that is called when a line of text has arrived on - * a telnet connection. - * - * \param s The telnet connection. - * - * \param cmd The line of text. - */ -void telnetd_input(struct telnetd_state *s, char *cmd); - - -void telnetd_close(struct telnetd_state *s); -void telnetd_output(struct telnetd_state *s, char *s1, char *s2); -void telnetd_prompt(struct telnetd_state *s, char *str); - -void telnetd_app(void); - -#ifndef UIP_APPCALL -#define UIP_APPCALL telnetd_app -#endif - -#ifndef UIP_APPSTATE_SIZE -#define UIP_APPSTATE_SIZE (sizeof(struct telnetd_state)) -#endif - -void telnetd_init(void); - - -#endif /* __TELNET_H__ */ - -/** @} */ diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/uIP_Task.c b/Demo/uIP_Demo_Rowley_ARM7/uip/uIP_Task.c deleted file mode 100644 index 85d2f469e..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/uip/uIP_Task.c +++ /dev/null @@ -1,201 +0,0 @@ -/* - * Copyright (c) 2001-2003, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: main.c,v 1.10.2.4 2003/10/21 21:27:51 adam Exp $ - * - */ - - -#include /* For system(). */ -#include /* For printf(). */ - -#include "FreeRTOS.h" -#include "task.h" - -#undef HTONS - -#include "cs8900a.h" -#include "uip.h" -#include "uip_arp.h" -#include "tapdev.h" -#include "httpd.h" - -static const struct uip_eth_addr ethaddr = {{0x00,0x00,0xe2,0x58,0xb6,0x6b}}; - -#define BUF ((struct uip_eth_hdr *)&uip_buf[0]) -#define uipSHORT_DELAY ( ( portTickType ) 2 / portTICK_RATE_MS ) - -#ifndef NULL -#define NULL (void *)0 -#endif /* NULL */ - -static volatile portTickType start, current; - -#define RT_CLOCK_SECOND ( configTICK_RATE_HZ / 2 ) - -/*-----------------------------------------------------------------------------------*/ -/** - * \internal - * A real-time clock. - * - * This example main() function uses polling of a real-time clock in - * order to know when the periodic processing should be - * performed. This is implemented using this function - rt_ticks(). In - * this example unix implementation, it simply calls the unix function - * gettimeofday() which returns the current wall clock time. - * - * For a micro-controller, a simple way to implement this function is - * by having a counter that is incremented by a timer interrupt and - * read by this function. - * - * The macro RT_CLOCK_SECOND should be defined as the approximate - * number of ticks that are elapsed during one second. - */ -#define rt_ticks xTaskGetTickCount - -/*-----------------------------------------------------------------------------------*/ -void vuIP_TASK( void *pvParameters ) -{ -u8_t i, arptimer; -u16_t addr[2]; -int z = 3; - - /* Initialize the uIP TCP/IP stack. */ - uip_init(); - uip_arp_init(); - - /* Initialize the device driver. */ - cs8900a_init(); - - /* Initialize the HTTP server. */ - httpd_init(); - - start = rt_ticks(); - arptimer = 0; - - while(1) - { - /* Let the network device driver read an entire IP packet - into the uip_buf. If it returns > 0, there is a packet in the - uip_buf buffer. */ - uip_len = cs8900a_poll(); - - if(uip_len > 0) - { - /* A packet is present in the packet buffer. We call the - appropriate ARP functions depending on what kind of packet we - have received. If the packet is an IP packet, we should call - uip_input() as well. */ - if(BUF->type == htons(UIP_ETHTYPE_IP)) - { - uip_arp_ipin(); - uip_input(); - /* If the above function invocation resulted in data that - should be sent out on the network, the global variable - uip_len is set to a value > 0. */ - if(uip_len > 0) - { - uip_arp_out(); - cs8900a_send(); - } - } - else if(BUF->type == htons(UIP_ETHTYPE_ARP)) - { - uip_arp_arpin(); - /* If the above function invocation resulted in data that - should be sent out on the network, the global variable - uip_len is set to a value > 0. */ - if(uip_len > 0) - { - cs8900a_send(); - } - } - } - else - { - /* The poll function returned 0, so no packet was - received. Instead we check if there is time that we do the - periodic processing. */ - current = rt_ticks(); - - if((u16_t)(current - start) >= (u16_t)RT_CLOCK_SECOND / 2) - { - start = current; - - for(i = 0; i < UIP_CONNS; i++) - { - uip_periodic(i); - - /* If the above function invocation resulted in data that - should be sent out on the network, the global variable - uip_len is set to a value > 0. */ - - if(uip_len > 0) - { - uip_arp_out(); - cs8900a_send(); - } - } - - #if UIP_UDP - for(i = 0; i < UIP_UDP_CONNS; i++) - { - uip_udp_periodic(i); - - /* If the above function invocation resulted in data that - should be sent out on the network, the global variable - uip_len is set to a value > 0. */ - - if(uip_len > 0) - { - uip_arp_out(); - tapdev_send(); - } - } - #endif /* UIP_UDP */ - - /* Call the ARP timer function every 10 seconds. */ - if(++arptimer == 20) - { - uip_arp_timer(); - arptimer = 0; - } - } - else - { - vTaskDelay( uipSHORT_DELAY ); - } } - } -} -/*-----------------------------------------------------------------------------------*/ - - - - diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/uip.c b/Demo/uIP_Demo_Rowley_ARM7/uip/uip.c deleted file mode 100644 index 3ef7e8d6c..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/uip/uip.c +++ /dev/null @@ -1,1509 +0,0 @@ -/** - * \addtogroup uip - * @{ - */ - -/** - * \file - * The uIP TCP/IP stack code. - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2001-2003, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: uip.c,v 1.62.2.10 2003/10/07 13:23:01 adam Exp $ - * - */ - -/* -This is a small implementation of the IP and TCP protocols (as well as -some basic ICMP stuff). The implementation couples the IP, TCP and the -application layers very tightly. To keep the size of the compiled code -down, this code also features heavy usage of the goto statement. - -The principle is that we have a small buffer, called the uip_buf, in -which the device driver puts an incoming packet. The TCP/IP stack -parses the headers in the packet, and calls upon the application. If -the remote host has sent data to the application, this data is present -in the uip_buf and the application read the data from there. It is up -to the application to put this data into a byte stream if needed. The -application will not be fed with data that is out of sequence. - -If the application whishes to send data to the peer, it should put its -data into the uip_buf, 40 bytes from the start of the buffer. The -TCP/IP stack will calculate the checksums, and fill in the necessary -header fields and finally send the packet back to the peer. -*/ - -#include "uip.h" -#include "uipopt.h" -#include "uip_arch.h" - -/*-----------------------------------------------------------------------------------*/ -/* Variable definitions. */ - - -/* The IP address of this host. If it is defined to be fixed (by setting UIP_FIXEDADDR to 1 in uipopt.h), the address is set here. Otherwise, the address */ -#if UIP_FIXEDADDR > 0 -const u16_t uip_hostaddr[2] = - {HTONS((UIP_IPADDR0 << 8) | UIP_IPADDR1), - HTONS((UIP_IPADDR2 << 8) | UIP_IPADDR3)}; -const u16_t uip_arp_draddr[2] = - {HTONS((UIP_DRIPADDR0 << 8) | UIP_DRIPADDR1), - HTONS((UIP_DRIPADDR2 << 8) | UIP_DRIPADDR3)}; -const u16_t uip_arp_netmask[2] = - {HTONS((UIP_NETMASK0 << 8) | UIP_NETMASK1), - HTONS((UIP_NETMASK2 << 8) | UIP_NETMASK3)}; -#else -u16_t uip_hostaddr[2]; -u16_t uip_arp_draddr[2], uip_arp_netmask[2]; -#endif /* UIP_FIXEDADDR */ - -u8_t uip_buf[UIP_BUFSIZE+2]; /* The packet buffer that contains - incoming packets. */ -volatile u8_t *uip_appdata; /* The uip_appdata pointer points to - application data. */ -volatile u8_t *uip_sappdata; /* The uip_appdata pointer points to the - application data which is to be sent. */ -#if UIP_URGDATA > 0 -volatile u8_t *uip_urgdata; /* The uip_urgdata pointer points to - urgent data (out-of-band data), if - present. */ -volatile u8_t uip_urglen, uip_surglen; -#endif /* UIP_URGDATA > 0 */ - -volatile u16_t uip_len, uip_slen; - /* The uip_len is either 8 or 16 bits, - depending on the maximum packet - size. */ - -volatile u8_t uip_flags; /* The uip_flags variable is used for - communication between the TCP/IP stack - and the application program. */ -struct uip_conn *uip_conn; /* uip_conn always points to the current - connection. */ - -struct uip_conn uip_conns[UIP_CONNS]; - /* The uip_conns array holds all TCP - connections. */ -u16_t uip_listenports[UIP_LISTENPORTS]; - /* The uip_listenports list all currently - listning ports. */ -#if UIP_UDP -struct uip_udp_conn *uip_udp_conn; -struct uip_udp_conn uip_udp_conns[UIP_UDP_CONNS]; -#endif /* UIP_UDP */ - - -static u16_t ipid; /* Ths ipid variable is an increasing - number that is used for the IP ID - field. */ - -static u8_t iss[4]; /* The iss variable is used for the TCP - initial sequence number. */ - -#if UIP_ACTIVE_OPEN -static u16_t lastport; /* Keeps track of the last port used for - a new connection. */ -#endif /* UIP_ACTIVE_OPEN */ - -/* Temporary variables. */ -volatile u8_t uip_acc32[4]; -static u8_t c, opt; -static u16_t tmp16; - -/* Structures and definitions. */ -#define TCP_FIN 0x01 -#define TCP_SYN 0x02 -#define TCP_RST 0x04 -#define TCP_PSH 0x08 -#define TCP_ACK 0x10 -#define TCP_URG 0x20 -#define TCP_CTL 0x3f - -#define ICMP_ECHO_REPLY 0 -#define ICMP_ECHO 8 - -/* Macros. */ -#define BUF ((uip_tcpip_hdr *)&uip_buf[UIP_LLH_LEN]) -#define FBUF ((uip_tcpip_hdr *)&uip_reassbuf[0]) -#define ICMPBUF ((uip_icmpip_hdr *)&uip_buf[UIP_LLH_LEN]) -#define UDPBUF ((uip_udpip_hdr *)&uip_buf[UIP_LLH_LEN]) - -#if UIP_STATISTICS == 1 -struct uip_stats uip_stat; -#define UIP_STAT(s) s -#else -#define UIP_STAT(s) -#endif /* UIP_STATISTICS == 1 */ - -#if UIP_LOGGING == 1 -#include -void uip_log(char *msg); -#define UIP_LOG(m) uip_log(m) -#else -#define UIP_LOG(m) -#endif /* UIP_LOGGING == 1 */ - -/*-----------------------------------------------------------------------------------*/ -void -uip_init(void) -{ - for(c = 0; c < UIP_LISTENPORTS; ++c) { - uip_listenports[c] = 0; - } - for(c = 0; c < UIP_CONNS; ++c) { - uip_conns[c].tcpstateflags = CLOSED; - } -#if UIP_ACTIVE_OPEN - lastport = 1024; -#endif /* UIP_ACTIVE_OPEN */ - -#if UIP_UDP - for(c = 0; c < UIP_UDP_CONNS; ++c) { - uip_udp_conns[c].lport = 0; - } -#endif /* UIP_UDP */ - - - /* IPv4 initialization. */ -#if UIP_FIXEDADDR == 0 - uip_hostaddr[0] = uip_hostaddr[1] = 0; -#endif /* UIP_FIXEDADDR */ - -} -/*-----------------------------------------------------------------------------------*/ -#if UIP_ACTIVE_OPEN -struct uip_conn * -uip_connect(u16_t *ripaddr, u16_t rport) -{ - register struct uip_conn *conn, *cconn; - - /* Find an unused local port. */ - again: - ++lastport; - - if(lastport >= 32000) { - lastport = 4096; - } - - /* Check if this port is already in use, and if so try to find - another one. */ - for(c = 0; c < UIP_CONNS; ++c) { - conn = &uip_conns[c]; - if(conn->tcpstateflags != CLOSED && - conn->lport == htons(lastport)) { - goto again; - } - } - - - conn = 0; - for(c = 0; c < UIP_CONNS; ++c) { - cconn = &uip_conns[c]; - if(cconn->tcpstateflags == CLOSED) { - conn = cconn; - break; - } - if(cconn->tcpstateflags == TIME_WAIT) { - if(conn == 0 || - cconn->timer > uip_conn->timer) { - conn = cconn; - } - } - } - - if(conn == 0) { - return 0; - } - - conn->tcpstateflags = SYN_SENT; - - conn->snd_nxt[0] = iss[0]; - conn->snd_nxt[1] = iss[1]; - conn->snd_nxt[2] = iss[2]; - conn->snd_nxt[3] = iss[3]; - - conn->initialmss = conn->mss = UIP_TCP_MSS; - - conn->len = 1; /* TCP length of the SYN is one. */ - conn->nrtx = 0; - conn->timer = 1; /* Send the SYN next time around. */ - conn->rto = UIP_RTO; - conn->sa = 0; - conn->sv = 16; - conn->lport = htons(lastport); - conn->rport = rport; - conn->ripaddr[0] = ripaddr[0]; - conn->ripaddr[1] = ripaddr[1]; - - return conn; -} -#endif /* UIP_ACTIVE_OPEN */ -/*-----------------------------------------------------------------------------------*/ -#if UIP_UDP -struct uip_udp_conn * -uip_udp_new(u16_t *ripaddr, u16_t rport) -{ - register struct uip_udp_conn *conn; - - /* Find an unused local port. */ - again: - ++lastport; - - if(lastport >= 32000) { - lastport = 4096; - } - - for(c = 0; c < UIP_UDP_CONNS; ++c) { - if(uip_udp_conns[c].lport == lastport) { - goto again; - } - } - - - conn = 0; - for(c = 0; c < UIP_UDP_CONNS; ++c) { - if(uip_udp_conns[c].lport == 0) { - conn = &uip_udp_conns[c]; - break; - } - } - - if(conn == 0) { - return 0; - } - - conn->lport = HTONS(lastport); - conn->rport = HTONS(rport); - conn->ripaddr[0] = ripaddr[0]; - conn->ripaddr[1] = ripaddr[1]; - - return conn; -} -#endif /* UIP_UDP */ -/*-----------------------------------------------------------------------------------*/ -void -uip_unlisten(u16_t port) -{ - for(c = 0; c < UIP_LISTENPORTS; ++c) { - if(uip_listenports[c] == port) { - uip_listenports[c] = 0; - return; - } - } -} -/*-----------------------------------------------------------------------------------*/ -void -uip_listen(u16_t port) -{ - for(c = 0; c < UIP_LISTENPORTS; ++c) { - if(uip_listenports[c] == 0) { - uip_listenports[c] = port; - return; - } - } -} -/*-----------------------------------------------------------------------------------*/ -/* XXX: IP fragment reassembly: not well-tested. */ - -#if UIP_REASSEMBLY -#define UIP_REASS_BUFSIZE (UIP_BUFSIZE - UIP_LLH_LEN) -static u8_t uip_reassbuf[UIP_REASS_BUFSIZE]; -static u8_t uip_reassbitmap[UIP_REASS_BUFSIZE / (8 * 8)]; -static const u8_t bitmap_bits[8] = {0xff, 0x7f, 0x3f, 0x1f, - 0x0f, 0x07, 0x03, 0x01}; -static u16_t uip_reasslen; -static u8_t uip_reassflags; -#define UIP_REASS_FLAG_LASTFRAG 0x01 -static u8_t uip_reasstmr; - -#define IP_HLEN 20 -#define IP_MF 0x20 - -static u8_t -uip_reass(void) -{ - u16_t offset, len; - u16_t i; - - /* If ip_reasstmr is zero, no packet is present in the buffer, so we - write the IP header of the fragment into the reassembly - buffer. The timer is updated with the maximum age. */ - if(uip_reasstmr == 0) { - memcpy(uip_reassbuf, &BUF->vhl, IP_HLEN); - uip_reasstmr = UIP_REASS_MAXAGE; - uip_reassflags = 0; - /* Clear the bitmap. */ - memset(uip_reassbitmap, sizeof(uip_reassbitmap), 0); - } - - /* Check if the incoming fragment matches the one currently present - in the reasembly buffer. If so, we proceed with copying the - fragment into the buffer. */ - if(BUF->srcipaddr[0] == FBUF->srcipaddr[0] && - BUF->srcipaddr[1] == FBUF->srcipaddr[1] && - BUF->destipaddr[0] == FBUF->destipaddr[0] && - BUF->destipaddr[1] == FBUF->destipaddr[1] && - BUF->ipid[0] == FBUF->ipid[0] && - BUF->ipid[1] == FBUF->ipid[1]) { - - len = (BUF->len[0] << 8) + BUF->len[1] - (BUF->vhl & 0x0f) * 4; - offset = (((BUF->ipoffset[0] & 0x3f) << 8) + BUF->ipoffset[1]) * 8; - - /* If the offset or the offset + fragment length overflows the - reassembly buffer, we discard the entire packet. */ - if(offset > UIP_REASS_BUFSIZE || - offset + len > UIP_REASS_BUFSIZE) { - uip_reasstmr = 0; - goto nullreturn; - } - - /* Copy the fragment into the reassembly buffer, at the right - offset. */ - memcpy(&uip_reassbuf[IP_HLEN + offset], - (char *)BUF + (int)((BUF->vhl & 0x0f) * 4), - len); - - /* Update the bitmap. */ - if(offset / (8 * 8) == (offset + len) / (8 * 8)) { - /* If the two endpoints are in the same byte, we only update - that byte. */ - - uip_reassbitmap[offset / (8 * 8)] |= - bitmap_bits[(offset / 8 ) & 7] & - ~bitmap_bits[((offset + len) / 8 ) & 7]; - } else { - /* If the two endpoints are in different bytes, we update the - bytes in the endpoints and fill the stuff inbetween with - 0xff. */ - uip_reassbitmap[offset / (8 * 8)] |= - bitmap_bits[(offset / 8 ) & 7]; - for(i = 1 + offset / (8 * 8); i < (offset + len) / (8 * 8); ++i) { - uip_reassbitmap[i] = 0xff; - } - uip_reassbitmap[(offset + len) / (8 * 8)] |= - ~bitmap_bits[((offset + len) / 8 ) & 7]; - } - - /* If this fragment has the More Fragments flag set to zero, we - know that this is the last fragment, so we can calculate the - size of the entire packet. We also set the - IP_REASS_FLAG_LASTFRAG flag to indicate that we have received - the final fragment. */ - - if((BUF->ipoffset[0] & IP_MF) == 0) { - uip_reassflags |= UIP_REASS_FLAG_LASTFRAG; - uip_reasslen = offset + len; - } - - /* Finally, we check if we have a full packet in the buffer. We do - this by checking if we have the last fragment and if all bits - in the bitmap are set. */ - if(uip_reassflags & UIP_REASS_FLAG_LASTFRAG) { - /* Check all bytes up to and including all but the last byte in - the bitmap. */ - for(i = 0; i < uip_reasslen / (8 * 8) - 1; ++i) { - if(uip_reassbitmap[i] != 0xff) { - goto nullreturn; - } - } - /* Check the last byte in the bitmap. It should contain just the - right amount of bits. */ - if(uip_reassbitmap[uip_reasslen / (8 * 8)] != - (u8_t)~bitmap_bits[uip_reasslen / 8 & 7]) { - goto nullreturn; - } - - /* If we have come this far, we have a full packet in the - buffer, so we allocate a pbuf and copy the packet into it. We - also reset the timer. */ - uip_reasstmr = 0; - memcpy(BUF, FBUF, uip_reasslen); - - /* Pretend to be a "normal" (i.e., not fragmented) IP packet - from now on. */ - BUF->ipoffset[0] = BUF->ipoffset[1] = 0; - BUF->len[0] = uip_reasslen >> 8; - BUF->len[1] = uip_reasslen & 0xff; - BUF->ipchksum = 0; - BUF->ipchksum = ~(uip_ipchksum()); - - return uip_reasslen; - } - } - - nullreturn: - return 0; -} -#endif /* UIP_REASSEMBL */ -/*-----------------------------------------------------------------------------------*/ -static void -uip_add_rcv_nxt(u16_t n) -{ - uip_add32(uip_conn->rcv_nxt, n); - uip_conn->rcv_nxt[0] = uip_acc32[0]; - uip_conn->rcv_nxt[1] = uip_acc32[1]; - uip_conn->rcv_nxt[2] = uip_acc32[2]; - uip_conn->rcv_nxt[3] = uip_acc32[3]; -} -/*-----------------------------------------------------------------------------------*/ -void -uip_process(u8_t flag) -{ - register struct uip_conn *uip_connr = uip_conn; - - uip_appdata = &uip_buf[40 + UIP_LLH_LEN]; - - - /* Check if we were invoked because of the perodic timer fireing. */ - if(flag == UIP_TIMER) { -#if UIP_REASSEMBLY - if(uip_reasstmr != 0) { - --uip_reasstmr; - } -#endif /* UIP_REASSEMBLY */ - /* Increase the initial sequence number. */ - if(++iss[3] == 0) { - if(++iss[2] == 0) { - if(++iss[1] == 0) { - ++iss[0]; - } - } - } - uip_len = 0; - if(uip_connr->tcpstateflags == TIME_WAIT || - uip_connr->tcpstateflags == FIN_WAIT_2) { - ++(uip_connr->timer); - if(uip_connr->timer == UIP_TIME_WAIT_TIMEOUT) { - uip_connr->tcpstateflags = CLOSED; - } - } else if(uip_connr->tcpstateflags != CLOSED) { - /* If the connection has outstanding data, we increase the - connection's timer and see if it has reached the RTO value - in which case we retransmit. */ - if(uip_outstanding(uip_connr)) { - if(uip_connr->timer-- == 0) { - if(uip_connr->nrtx == UIP_MAXRTX || - ((uip_connr->tcpstateflags == SYN_SENT || - uip_connr->tcpstateflags == SYN_RCVD) && - uip_connr->nrtx == UIP_MAXSYNRTX)) { - uip_connr->tcpstateflags = CLOSED; - - /* We call UIP_APPCALL() with uip_flags set to - UIP_TIMEDOUT to inform the application that the - connection has timed out. */ - uip_flags = UIP_TIMEDOUT; - UIP_APPCALL(); - - /* We also send a reset packet to the remote host. */ - BUF->flags = TCP_RST | TCP_ACK; - goto tcp_send_nodata; - } - - /* Exponential backoff. */ - uip_connr->timer = UIP_RTO << (uip_connr->nrtx > 4? - 4: - uip_connr->nrtx); - ++(uip_connr->nrtx); - - /* Ok, so we need to retransmit. We do this differently - depending on which state we are in. In ESTABLISHED, we - call upon the application so that it may prepare the - data for the retransmit. In SYN_RCVD, we resend the - SYNACK that we sent earlier and in LAST_ACK we have to - retransmit our FINACK. */ - UIP_STAT(++uip_stat.tcp.rexmit); - switch(uip_connr->tcpstateflags & TS_MASK) { - case SYN_RCVD: - /* In the SYN_RCVD state, we should retransmit our - SYNACK. */ - goto tcp_send_synack; - -#if UIP_ACTIVE_OPEN - case SYN_SENT: - /* In the SYN_SENT state, we retransmit out SYN. */ - BUF->flags = 0; - goto tcp_send_syn; -#endif /* UIP_ACTIVE_OPEN */ - - case ESTABLISHED: - /* In the ESTABLISHED state, we call upon the application - to do the actual retransmit after which we jump into - the code for sending out the packet (the apprexmit - label). */ - uip_len = 0; - uip_slen = 0; - uip_flags = UIP_REXMIT; - UIP_APPCALL(); - goto apprexmit; - - case FIN_WAIT_1: - case CLOSING: - case LAST_ACK: - /* In all these states we should retransmit a FINACK. */ - goto tcp_send_finack; - - } - } - } else if((uip_connr->tcpstateflags & TS_MASK) == ESTABLISHED) { - /* If there was no need for a retransmission, we poll the - application for new data. */ - uip_len = 0; - uip_slen = 0; - uip_flags = UIP_POLL; - UIP_APPCALL(); - goto appsend; - } - } - goto drop; - } -#if UIP_UDP - if(flag == UIP_UDP_TIMER) { - if(uip_udp_conn->lport != 0) { - uip_appdata = &uip_buf[UIP_LLH_LEN + 28]; - uip_len = uip_slen = 0; - uip_flags = UIP_POLL; - UIP_UDP_APPCALL(); - goto udp_send; - } else { - goto drop; - } - } -#endif - - /* This is where the input processing starts. */ - UIP_STAT(++uip_stat.ip.recv); - - - /* Start of IPv4 input header processing code. */ - - /* Check validity of the IP header. */ - if(BUF->vhl != 0x45) { /* IP version and header length. */ - UIP_STAT(++uip_stat.ip.drop); - UIP_STAT(++uip_stat.ip.vhlerr); - UIP_LOG("ip: invalid version or header length."); - goto drop; - } - - /* Check the size of the packet. If the size reported to us in - uip_len doesn't match the size reported in the IP header, there - has been a transmission error and we drop the packet. */ - - if(BUF->len[0] != (uip_len >> 8)) { /* IP length, high byte. */ - uip_len = (uip_len & 0xff) | (BUF->len[0] << 8); - } - if(BUF->len[1] != (uip_len & 0xff)) { /* IP length, low byte. */ - uip_len = (uip_len & 0xff00) | BUF->len[1]; - } - - /* Check the fragment flag. */ - if((BUF->ipoffset[0] & 0x3f) != 0 || - BUF->ipoffset[1] != 0) { -#if UIP_REASSEMBLY - uip_len = uip_reass(); - if(uip_len == 0) { - goto drop; - } -#else - UIP_STAT(++uip_stat.ip.drop); - UIP_STAT(++uip_stat.ip.fragerr); - UIP_LOG("ip: fragment dropped."); - goto drop; -#endif /* UIP_REASSEMBLY */ - } - - /* If we are configured to use ping IP address configuration and - hasn't been assigned an IP address yet, we accept all ICMP - packets. */ -#if UIP_PINGADDRCONF - if((uip_hostaddr[0] | uip_hostaddr[1]) == 0) { - if(BUF->proto == UIP_PROTO_ICMP) { - UIP_LOG("ip: possible ping config packet received."); - goto icmp_input; - } else { - UIP_LOG("ip: packet dropped since no address assigned."); - goto drop; - } - } -#endif /* UIP_PINGADDRCONF */ - - /* Check if the packet is destined for our IP address. */ - if(BUF->destipaddr[0] != uip_hostaddr[0]) { - UIP_STAT(++uip_stat.ip.drop); - UIP_LOG("ip: packet not for us."); - goto drop; - } - if(BUF->destipaddr[1] != uip_hostaddr[1]) { - UIP_STAT(++uip_stat.ip.drop); - UIP_LOG("ip: packet not for us."); - goto drop; - } - -#if 0 - // IP checksum is wrong through Netgear DSL router - if (uip_ipchksum() != 0xffff) { /* Compute and check the IP header - checksum. */ - UIP_STAT(++uip_stat.ip.drop); - UIP_STAT(++uip_stat.ip.chkerr); - UIP_LOG("ip: bad checksum."); - goto drop; - } -#endif - - if(BUF->proto == UIP_PROTO_TCP) /* Check for TCP packet. If so, jump - to the tcp_input label. */ - goto tcp_input; - -#if UIP_UDP - if(BUF->proto == UIP_PROTO_UDP) - goto udp_input; -#endif /* UIP_UDP */ - - if(BUF->proto != UIP_PROTO_ICMP) { /* We only allow ICMP packets from - here. */ - UIP_STAT(++uip_stat.ip.drop); - UIP_STAT(++uip_stat.ip.protoerr); - UIP_LOG("ip: neither tcp nor icmp."); - goto drop; - } - - icmp_input: - UIP_STAT(++uip_stat.icmp.recv); - - /* ICMP echo (i.e., ping) processing. This is simple, we only change - the ICMP type from ECHO to ECHO_REPLY and adjust the ICMP - checksum before we return the packet. */ - if(ICMPBUF->type != ICMP_ECHO) { - UIP_STAT(++uip_stat.icmp.drop); - UIP_STAT(++uip_stat.icmp.typeerr); - UIP_LOG("icmp: not icmp echo."); - goto drop; - } - - /* If we are configured to use ping IP address assignment, we use - the destination IP address of this ping packet and assign it to - ourself. */ -#if UIP_PINGADDRCONF - if((uip_hostaddr[0] | uip_hostaddr[1]) == 0) { - uip_hostaddr[0] = BUF->destipaddr[0]; - uip_hostaddr[1] = BUF->destipaddr[1]; - } -#endif /* UIP_PINGADDRCONF */ - - ICMPBUF->type = ICMP_ECHO_REPLY; - - if(ICMPBUF->icmpchksum >= HTONS(0xffff - (ICMP_ECHO << 8))) { - ICMPBUF->icmpchksum += HTONS(ICMP_ECHO << 8) + 1; - } else { - ICMPBUF->icmpchksum += HTONS(ICMP_ECHO << 8); - } - - /* Swap IP addresses. */ - tmp16 = BUF->destipaddr[0]; - BUF->destipaddr[0] = BUF->srcipaddr[0]; - BUF->srcipaddr[0] = tmp16; - tmp16 = BUF->destipaddr[1]; - BUF->destipaddr[1] = BUF->srcipaddr[1]; - BUF->srcipaddr[1] = tmp16; - - UIP_STAT(++uip_stat.icmp.sent); - goto send; - - /* End of IPv4 input header processing code. */ - - -#if UIP_UDP - /* UDP input processing. */ - udp_input: - /* UDP processing is really just a hack. We don't do anything to the - UDP/IP headers, but let the UDP application do all the hard - work. If the application sets uip_slen, it has a packet to - send. */ -#if UIP_UDP_CHECKSUMS - if(uip_udpchksum() != 0xffff) { - UIP_STAT(++uip_stat.udp.drop); - UIP_STAT(++uip_stat.udp.chkerr); - UIP_LOG("udp: bad checksum."); - goto drop; - } -#endif /* UIP_UDP_CHECKSUMS */ - - /* Demultiplex this UDP packet between the UDP "connections". */ - for(uip_udp_conn = &uip_udp_conns[0]; - uip_udp_conn < &uip_udp_conns[UIP_UDP_CONNS]; - ++uip_udp_conn) { - if(uip_udp_conn->lport != 0 && - UDPBUF->destport == uip_udp_conn->lport && - (uip_udp_conn->rport == 0 || - UDPBUF->srcport == uip_udp_conn->rport) && - BUF->srcipaddr[0] == uip_udp_conn->ripaddr[0] && - BUF->srcipaddr[1] == uip_udp_conn->ripaddr[1]) { - goto udp_found; - } - } - goto drop; - - udp_found: - uip_len = uip_len - 28; - uip_appdata = &uip_buf[UIP_LLH_LEN + 28]; - uip_flags = UIP_NEWDATA; - uip_slen = 0; - UIP_UDP_APPCALL(); - udp_send: - if(uip_slen == 0) { - goto drop; - } - uip_len = uip_slen + 28; - - BUF->len[0] = (uip_len >> 8); - BUF->len[1] = (uip_len & 0xff); - - BUF->proto = UIP_PROTO_UDP; - - UDPBUF->udplen = HTONS(uip_slen + 8); - UDPBUF->udpchksum = 0; -#if UIP_UDP_CHECKSUMS - /* Calculate UDP checksum. */ - UDPBUF->udpchksum = ~(uip_udpchksum()); - if(UDPBUF->udpchksum == 0) { - UDPBUF->udpchksum = 0xffff; - } -#endif /* UIP_UDP_CHECKSUMS */ - - BUF->srcport = uip_udp_conn->lport; - BUF->destport = uip_udp_conn->rport; - - BUF->srcipaddr[0] = uip_hostaddr[0]; - BUF->srcipaddr[1] = uip_hostaddr[1]; - BUF->destipaddr[0] = uip_udp_conn->ripaddr[0]; - BUF->destipaddr[1] = uip_udp_conn->ripaddr[1]; - - uip_appdata = &uip_buf[UIP_LLH_LEN + 40]; - goto ip_send_nolen; -#endif /* UIP_UDP */ - - /* TCP input processing. */ - tcp_input: - UIP_STAT(++uip_stat.tcp.recv); - - /* Start of TCP input header processing code. */ - -#if 1 // FIXME - if(uip_tcpchksum() != 0xffff) { /* Compute and check the TCP - checksum. */ - UIP_STAT(++uip_stat.tcp.drop); - UIP_STAT(++uip_stat.tcp.chkerr); - UIP_LOG("tcp: bad checksum."); - goto drop; - } -#endif - - /* Demultiplex this segment. */ - /* First check any active connections. */ - for(uip_connr = &uip_conns[0]; uip_connr < &uip_conns[UIP_CONNS]; ++uip_connr) { - if(uip_connr->tcpstateflags != CLOSED && - BUF->destport == uip_connr->lport && - BUF->srcport == uip_connr->rport && - BUF->srcipaddr[0] == uip_connr->ripaddr[0] && - BUF->srcipaddr[1] == uip_connr->ripaddr[1]) { - goto found; - } - } - - /* If we didn't find and active connection that expected the packet, - either this packet is an old duplicate, or this is a SYN packet - destined for a connection in LISTEN. If the SYN flag isn't set, - it is an old packet and we send a RST. */ - if((BUF->flags & TCP_CTL) != TCP_SYN) - goto reset; - - tmp16 = BUF->destport; - /* Next, check listening connections. */ - for(c = 0; c < UIP_LISTENPORTS; ++c) { - if(tmp16 == uip_listenports[c]) - goto found_listen; - } - - /* No matching connection found, so we send a RST packet. */ - UIP_STAT(++uip_stat.tcp.synrst); - reset: - - /* We do not send resets in response to resets. */ - if(BUF->flags & TCP_RST) - goto drop; - - UIP_STAT(++uip_stat.tcp.rst); - - BUF->flags = TCP_RST | TCP_ACK; - uip_len = 40; - BUF->tcpoffset = 5 << 4; - - /* Flip the seqno and ackno fields in the TCP header. */ - c = BUF->seqno[3]; - BUF->seqno[3] = BUF->ackno[3]; - BUF->ackno[3] = c; - - c = BUF->seqno[2]; - BUF->seqno[2] = BUF->ackno[2]; - BUF->ackno[2] = c; - - c = BUF->seqno[1]; - BUF->seqno[1] = BUF->ackno[1]; - BUF->ackno[1] = c; - - c = BUF->seqno[0]; - BUF->seqno[0] = BUF->ackno[0]; - BUF->ackno[0] = c; - - /* We also have to increase the sequence number we are - acknowledging. If the least significant byte overflowed, we need - to propagate the carry to the other bytes as well. */ - if(++BUF->ackno[3] == 0) { - if(++BUF->ackno[2] == 0) { - if(++BUF->ackno[1] == 0) { - ++BUF->ackno[0]; - } - } - } - - /* Swap port numbers. */ - tmp16 = BUF->srcport; - BUF->srcport = BUF->destport; - BUF->destport = tmp16; - - /* Swap IP addresses. */ - tmp16 = BUF->destipaddr[0]; - BUF->destipaddr[0] = BUF->srcipaddr[0]; - BUF->srcipaddr[0] = tmp16; - tmp16 = BUF->destipaddr[1]; - BUF->destipaddr[1] = BUF->srcipaddr[1]; - BUF->srcipaddr[1] = tmp16; - - - /* And send out the RST packet! */ - goto tcp_send_noconn; - - /* This label will be jumped to if we matched the incoming packet - with a connection in LISTEN. In that case, we should create a new - connection and send a SYNACK in return. */ - found_listen: - /* First we check if there are any connections avaliable. Unused - connections are kept in the same table as used connections, but - unused ones have the tcpstate set to CLOSED. Also, connections in - TIME_WAIT are kept track of and we'll use the oldest one if no - CLOSED connections are found. Thanks to Eddie C. Dost for a very - nice algorithm for the TIME_WAIT search. */ - uip_connr = 0; - for(c = 0; c < UIP_CONNS; ++c) { - if(uip_conns[c].tcpstateflags == CLOSED) { - uip_connr = &uip_conns[c]; - break; - } - if(uip_conns[c].tcpstateflags == TIME_WAIT) { - if(uip_connr == 0 || - uip_conns[c].timer > uip_connr->timer) { - uip_connr = &uip_conns[c]; - } - } - } - - if(uip_connr == 0) { - /* All connections are used already, we drop packet and hope that - the remote end will retransmit the packet at a time when we - have more spare connections. */ - UIP_STAT(++uip_stat.tcp.syndrop); - UIP_LOG("tcp: found no unused connections."); - goto drop; - } - uip_conn = uip_connr; - - /* Fill in the necessary fields for the new connection. */ - uip_connr->rto = uip_connr->timer = UIP_RTO; - uip_connr->sa = 0; - uip_connr->sv = 4; - uip_connr->nrtx = 0; - uip_connr->lport = BUF->destport; - uip_connr->rport = BUF->srcport; - uip_connr->ripaddr[0] = BUF->srcipaddr[0]; - uip_connr->ripaddr[1] = BUF->srcipaddr[1]; - uip_connr->tcpstateflags = SYN_RCVD; - - uip_connr->snd_nxt[0] = iss[0]; - uip_connr->snd_nxt[1] = iss[1]; - uip_connr->snd_nxt[2] = iss[2]; - uip_connr->snd_nxt[3] = iss[3]; - uip_connr->len = 1; - - /* rcv_nxt should be the seqno from the incoming packet + 1. */ - uip_connr->rcv_nxt[3] = BUF->seqno[3]; - uip_connr->rcv_nxt[2] = BUF->seqno[2]; - uip_connr->rcv_nxt[1] = BUF->seqno[1]; - uip_connr->rcv_nxt[0] = BUF->seqno[0]; - uip_add_rcv_nxt(1); - - /* Parse the TCP MSS option, if present. */ - if((BUF->tcpoffset & 0xf0) > 0x50) { - for(c = 0; c < ((BUF->tcpoffset >> 4) - 5) << 2 ;) { - opt = uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + c]; - if(opt == 0x00) { - /* End of options. */ - break; - } else if(opt == 0x01) { - ++c; - /* NOP option. */ - } else if(opt == 0x02 && - uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0x04) { - /* An MSS option with the right option length. */ - tmp16 = ((u16_t)uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 2 + c] << 8) | - (u16_t)uip_buf[40 + UIP_LLH_LEN + 3 + c]; - uip_connr->initialmss = uip_connr->mss = - tmp16 > UIP_TCP_MSS? UIP_TCP_MSS: tmp16; - - /* And we are done processing options. */ - break; - } else { - /* All other options have a length field, so that we easily - can skip past them. */ - if(uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0) { - /* If the length field is zero, the options are malformed - and we don't process them further. */ - break; - } - c += uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c]; - } - } - } - - /* Our response will be a SYNACK. */ -#if UIP_ACTIVE_OPEN - tcp_send_synack: - BUF->flags = TCP_ACK; - - tcp_send_syn: - BUF->flags |= TCP_SYN; -#else /* UIP_ACTIVE_OPEN */ - tcp_send_synack: - BUF->flags = TCP_SYN | TCP_ACK; -#endif /* UIP_ACTIVE_OPEN */ - - /* We send out the TCP Maximum Segment Size option with our - SYNACK. */ - BUF->optdata[0] = 2; - BUF->optdata[1] = 4; - BUF->optdata[2] = (UIP_TCP_MSS) / 256; - BUF->optdata[3] = (UIP_TCP_MSS) & 255; - uip_len = 44; - BUF->tcpoffset = 6 << 4; - goto tcp_send; - - /* This label will be jumped to if we found an active connection. */ - found: - uip_conn = uip_connr; - uip_flags = 0; - - /* We do a very naive form of TCP reset processing; we just accept - any RST and kill our connection. We should in fact check if the - sequence number of this reset is wihtin our advertised window - before we accept the reset. */ - if(BUF->flags & TCP_RST) { - uip_connr->tcpstateflags = CLOSED; - UIP_LOG("tcp: got reset, aborting connection."); - uip_flags = UIP_ABORT; - UIP_APPCALL(); - goto drop; - } - /* Calculated the length of the data, if the application has sent - any data to us. */ - c = (BUF->tcpoffset >> 4) << 2; - /* uip_len will contain the length of the actual TCP data. This is - calculated by subtracing the length of the TCP header (in - c) and the length of the IP header (20 bytes). */ - uip_len = uip_len - c - 20; - - /* First, check if the sequence number of the incoming packet is - what we're expecting next. If not, we send out an ACK with the - correct numbers in. */ - if(uip_len > 0 && - (BUF->seqno[0] != uip_connr->rcv_nxt[0] || - BUF->seqno[1] != uip_connr->rcv_nxt[1] || - BUF->seqno[2] != uip_connr->rcv_nxt[2] || - BUF->seqno[3] != uip_connr->rcv_nxt[3])) { - goto tcp_send_ack; - } - - /* Next, check if the incoming segment acknowledges any outstanding - data. If so, we update the sequence number, reset the length of - the outstanding data, calculate RTT estimations, and reset the - retransmission timer. */ - if((BUF->flags & TCP_ACK) && uip_outstanding(uip_connr)) { - uip_add32(uip_connr->snd_nxt, uip_connr->len); - if(BUF->ackno[0] == uip_acc32[0] && - BUF->ackno[1] == uip_acc32[1] && - BUF->ackno[2] == uip_acc32[2] && - BUF->ackno[3] == uip_acc32[3]) { - /* Update sequence number. */ - uip_connr->snd_nxt[0] = uip_acc32[0]; - uip_connr->snd_nxt[1] = uip_acc32[1]; - uip_connr->snd_nxt[2] = uip_acc32[2]; - uip_connr->snd_nxt[3] = uip_acc32[3]; - - - /* Do RTT estimation, unless we have done retransmissions. */ - if(uip_connr->nrtx == 0) { - signed char m; - m = uip_connr->rto - uip_connr->timer; - /* This is taken directly from VJs original code in his paper */ - m = m - (uip_connr->sa >> 3); - uip_connr->sa += m; - if(m < 0) { - m = -m; - } - m = m - (uip_connr->sv >> 2); - uip_connr->sv += m; - uip_connr->rto = (uip_connr->sa >> 3) + uip_connr->sv; - - } - /* Set the acknowledged flag. */ - uip_flags = UIP_ACKDATA; - /* Reset the retransmission timer. */ - uip_connr->timer = uip_connr->rto; - } - - } - - /* Do different things depending on in what state the connection is. */ - switch(uip_connr->tcpstateflags & TS_MASK) { - /* CLOSED and LISTEN are not handled here. CLOSE_WAIT is not - implemented, since we force the application to close when the - peer sends a FIN (hence the application goes directly from - ESTABLISHED to LAST_ACK). */ - case SYN_RCVD: - /* In SYN_RCVD we have sent out a SYNACK in response to a SYN, and - we are waiting for an ACK that acknowledges the data we sent - out the last time. Therefore, we want to have the UIP_ACKDATA - flag set. If so, we enter the ESTABLISHED state. */ - if(uip_flags & UIP_ACKDATA) { - uip_connr->tcpstateflags = ESTABLISHED; - uip_flags = UIP_CONNECTED; - uip_connr->len = 0; - if(uip_len > 0) { - uip_flags |= UIP_NEWDATA; - uip_add_rcv_nxt(uip_len); - } - uip_slen = 0; - UIP_APPCALL(); - goto appsend; - } - goto drop; -#if UIP_ACTIVE_OPEN - case SYN_SENT: - /* In SYN_SENT, we wait for a SYNACK that is sent in response to - our SYN. The rcv_nxt is set to sequence number in the SYNACK - plus one, and we send an ACK. We move into the ESTABLISHED - state. */ - if((uip_flags & UIP_ACKDATA) && - BUF->flags == (TCP_SYN | TCP_ACK)) { - - /* Parse the TCP MSS option, if present. */ - if((BUF->tcpoffset & 0xf0) > 0x50) { - for(c = 0; c < ((BUF->tcpoffset >> 4) - 5) << 2 ;) { - opt = uip_buf[40 + UIP_LLH_LEN + c]; - if(opt == 0x00) { - /* End of options. */ - break; - } else if(opt == 0x01) { - ++c; - /* NOP option. */ - } else if(opt == 0x02 && - uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0x04) { - /* An MSS option with the right option length. */ - tmp16 = (uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 2 + c] << 8) | - uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 3 + c]; - uip_connr->initialmss = - uip_connr->mss = tmp16 > UIP_TCP_MSS? UIP_TCP_MSS: tmp16; - - /* And we are done processing options. */ - break; - } else { - /* All other options have a length field, so that we easily - can skip past them. */ - if(uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0) { - /* If the length field is zero, the options are malformed - and we don't process them further. */ - break; - } - c += uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c]; - } - } - } - uip_connr->tcpstateflags = ESTABLISHED; - uip_connr->rcv_nxt[0] = BUF->seqno[0]; - uip_connr->rcv_nxt[1] = BUF->seqno[1]; - uip_connr->rcv_nxt[2] = BUF->seqno[2]; - uip_connr->rcv_nxt[3] = BUF->seqno[3]; - uip_add_rcv_nxt(1); - uip_flags = UIP_CONNECTED | UIP_NEWDATA; - uip_connr->len = 0; - uip_len = 0; - uip_slen = 0; - UIP_APPCALL(); - goto appsend; - } - goto reset; -#endif /* UIP_ACTIVE_OPEN */ - - case ESTABLISHED: - /* In the ESTABLISHED state, we call upon the application to feed - data into the uip_buf. If the UIP_ACKDATA flag is set, the - application should put new data into the buffer, otherwise we are - retransmitting an old segment, and the application should put that - data into the buffer. - - If the incoming packet is a FIN, we should close the connection on - this side as well, and we send out a FIN and enter the LAST_ACK - state. We require that there is no outstanding data; otherwise the - sequence numbers will be screwed up. */ - - if(BUF->flags & TCP_FIN) { - if(uip_outstanding(uip_connr)) { - goto drop; - } - uip_add_rcv_nxt(1 + uip_len); - uip_flags = UIP_CLOSE; - if(uip_len > 0) { - uip_flags |= UIP_NEWDATA; - } - UIP_APPCALL(); - uip_connr->len = 1; - uip_connr->tcpstateflags = LAST_ACK; - uip_connr->nrtx = 0; - tcp_send_finack: - BUF->flags = TCP_FIN | TCP_ACK; - goto tcp_send_nodata; - } - - /* Check the URG flag. If this is set, the segment carries urgent - data that we must pass to the application. */ - if(BUF->flags & TCP_URG) { -#if UIP_URGDATA > 0 - uip_urglen = (BUF->urgp[0] << 8) | BUF->urgp[1]; - if(uip_urglen > uip_len) { - /* There is more urgent data in the next segment to come. */ - uip_urglen = uip_len; - } - uip_add_rcv_nxt(uip_urglen); - uip_len -= uip_urglen; - uip_urgdata = uip_appdata; - uip_appdata += uip_urglen; - } else { - uip_urglen = 0; -#endif /* UIP_URGDATA > 0 */ - uip_appdata += (BUF->urgp[0] << 8) | BUF->urgp[1]; - uip_len -= (BUF->urgp[0] << 8) | BUF->urgp[1]; - } - - - /* If uip_len > 0 we have TCP data in the packet, and we flag this - by setting the UIP_NEWDATA flag and update the sequence number - we acknowledge. If the application has stopped the dataflow - using uip_stop(), we must not accept any data packets from the - remote host. */ - if(uip_len > 0 && !(uip_connr->tcpstateflags & UIP_STOPPED)) { - uip_flags |= UIP_NEWDATA; - uip_add_rcv_nxt(uip_len); - } - - /* Check if the available buffer space advertised by the other end - is smaller than the initial MSS for this connection. If so, we - set the current MSS to the window size to ensure that the - application does not send more data than the other end can - handle. - - If the remote host advertises a zero window, we set the MSS to - the initial MSS so that the application will send an entire MSS - of data. This data will not be acknowledged by the receiver, - and the application will retransmit it. This is called the - "persistent timer" and uses the retransmission mechanim. - */ - tmp16 = ((u16_t)BUF->wnd[0] << 8) + (u16_t)BUF->wnd[1]; - if(tmp16 > uip_connr->initialmss || - tmp16 == 0) { - tmp16 = uip_connr->initialmss; - } - uip_connr->mss = tmp16; - - /* If this packet constitutes an ACK for outstanding data (flagged - by the UIP_ACKDATA flag, we should call the application since it - might want to send more data. If the incoming packet had data - from the peer (as flagged by the UIP_NEWDATA flag), the - application must also be notified. - - When the application is called, the global variable uip_len - contains the length of the incoming data. The application can - access the incoming data through the global pointer - uip_appdata, which usually points 40 bytes into the uip_buf - array. - - If the application wishes to send any data, this data should be - put into the uip_appdata and the length of the data should be - put into uip_len. If the application don't have any data to - send, uip_len must be set to 0. */ - if(uip_flags & (UIP_NEWDATA | UIP_ACKDATA)) { - uip_slen = 0; - UIP_APPCALL(); - - appsend: - - if(uip_flags & UIP_ABORT) { - uip_slen = 0; - uip_connr->tcpstateflags = CLOSED; - BUF->flags = TCP_RST | TCP_ACK; - goto tcp_send_nodata; - } - - if(uip_flags & UIP_CLOSE) { - uip_slen = 0; - uip_connr->len = 1; - uip_connr->tcpstateflags = FIN_WAIT_1; - uip_connr->nrtx = 0; - BUF->flags = TCP_FIN | TCP_ACK; - goto tcp_send_nodata; - } - - /* If uip_slen > 0, the application has data to be sent. */ - if(uip_slen > 0) { - - /* If the connection has acknowledged data, the contents of - the ->len variable should be discarded. */ - if((uip_flags & UIP_ACKDATA) != 0) { - uip_connr->len = 0; - } - - /* If the ->len variable is non-zero the connection has - already data in transit and cannot send anymore right - now. */ - if(uip_connr->len == 0) { - - /* The application cannot send more than what is allowed by - the mss (the minumum of the MSS and the available - window). */ - if(uip_slen > uip_connr->mss) { - uip_slen = uip_connr->mss; - } - - /* Remember how much data we send out now so that we know - when everything has been acknowledged. */ - uip_connr->len = uip_slen; - } else { - - /* If the application already had unacknowledged data, we - make sure that the application does not send (i.e., - retransmit) out more than it previously sent out. */ - uip_slen = uip_connr->len; - } - } else { - uip_connr->len = 0; - } - uip_connr->nrtx = 0; - apprexmit: - uip_appdata = uip_sappdata; - - /* If the application has data to be sent, or if the incoming - packet had new data in it, we must send out a packet. */ - if(uip_slen > 0 && uip_connr->len > 0) { - /* Add the length of the IP and TCP headers. */ - uip_len = uip_connr->len + UIP_TCPIP_HLEN; - /* We always set the ACK flag in response packets. */ - BUF->flags = TCP_ACK | TCP_PSH; - /* Send the packet. */ - goto tcp_send_noopts; - } - /* If there is no data to send, just send out a pure ACK if - there is newdata. */ - if(uip_flags & UIP_NEWDATA) { - uip_len = UIP_TCPIP_HLEN; - BUF->flags = TCP_ACK; - goto tcp_send_noopts; - } - } - goto drop; - case LAST_ACK: - /* We can close this connection if the peer has acknowledged our - FIN. This is indicated by the UIP_ACKDATA flag. */ - if(uip_flags & UIP_ACKDATA) { - uip_connr->tcpstateflags = CLOSED; - uip_flags = UIP_CLOSE; - UIP_APPCALL(); - } - break; - - case FIN_WAIT_1: - /* The application has closed the connection, but the remote host - hasn't closed its end yet. Thus we do nothing but wait for a - FIN from the other side. */ - if(uip_len > 0) { - uip_add_rcv_nxt(uip_len); - } - if(BUF->flags & TCP_FIN) { - if(uip_flags & UIP_ACKDATA) { - uip_connr->tcpstateflags = TIME_WAIT; - uip_connr->timer = 0; - uip_connr->len = 0; - } else { - uip_connr->tcpstateflags = CLOSING; - } - uip_add_rcv_nxt(1); - uip_flags = UIP_CLOSE; - UIP_APPCALL(); - goto tcp_send_ack; - } else if(uip_flags & UIP_ACKDATA) { - uip_connr->tcpstateflags = FIN_WAIT_2; - uip_connr->len = 0; - goto drop; - } - if(uip_len > 0) { - goto tcp_send_ack; - } - goto drop; - - case FIN_WAIT_2: - if(uip_len > 0) { - uip_add_rcv_nxt(uip_len); - } - if(BUF->flags & TCP_FIN) { - uip_connr->tcpstateflags = TIME_WAIT; - uip_connr->timer = 0; - uip_add_rcv_nxt(1); - uip_flags = UIP_CLOSE; - UIP_APPCALL(); - goto tcp_send_ack; - } - if(uip_len > 0) { - goto tcp_send_ack; - } - goto drop; - - case TIME_WAIT: - goto tcp_send_ack; - - case CLOSING: - if(uip_flags & UIP_ACKDATA) { - uip_connr->tcpstateflags = TIME_WAIT; - uip_connr->timer = 0; - } - } - goto drop; - - - /* We jump here when we are ready to send the packet, and just want - to set the appropriate TCP sequence numbers in the TCP header. */ - tcp_send_ack: - BUF->flags = TCP_ACK; - tcp_send_nodata: - uip_len = 40; - tcp_send_noopts: - BUF->tcpoffset = 5 << 4; - tcp_send: - /* We're done with the input processing. We are now ready to send a - reply. Our job is to fill in all the fields of the TCP and IP - headers before calculating the checksum and finally send the - packet. */ - BUF->ackno[0] = uip_connr->rcv_nxt[0]; - BUF->ackno[1] = uip_connr->rcv_nxt[1]; - BUF->ackno[2] = uip_connr->rcv_nxt[2]; - BUF->ackno[3] = uip_connr->rcv_nxt[3]; - - BUF->seqno[0] = uip_connr->snd_nxt[0]; - BUF->seqno[1] = uip_connr->snd_nxt[1]; - BUF->seqno[2] = uip_connr->snd_nxt[2]; - BUF->seqno[3] = uip_connr->snd_nxt[3]; - - BUF->proto = UIP_PROTO_TCP; - - BUF->srcport = uip_connr->lport; - BUF->destport = uip_connr->rport; - - BUF->srcipaddr[0] = uip_hostaddr[0]; - BUF->srcipaddr[1] = uip_hostaddr[1]; - BUF->destipaddr[0] = uip_connr->ripaddr[0]; - BUF->destipaddr[1] = uip_connr->ripaddr[1]; - - - if(uip_connr->tcpstateflags & UIP_STOPPED) { - /* If the connection has issued uip_stop(), we advertise a zero - window so that the remote host will stop sending data. */ - BUF->wnd[0] = BUF->wnd[1] = 0; - } else { - BUF->wnd[0] = ((UIP_RECEIVE_WINDOW) >> 8); - BUF->wnd[1] = ((UIP_RECEIVE_WINDOW) & 0xff); - } - - tcp_send_noconn: - - BUF->len[0] = (uip_len >> 8); - BUF->len[1] = (uip_len & 0xff); - - /* Calculate TCP checksum. */ - BUF->tcpchksum = 0; - BUF->tcpchksum = ~(uip_tcpchksum()); - - ip_send_nolen: - - BUF->vhl = 0x45; - BUF->tos = 0; - BUF->ipoffset[0] = BUF->ipoffset[1] = 0; - BUF->ttl = UIP_TTL; - ++ipid; - BUF->ipid[0] = ipid >> 8; - BUF->ipid[1] = ipid & 0xff; - - /* Calculate IP checksum. */ - BUF->ipchksum = 0; - BUF->ipchksum = ~(uip_ipchksum()); - - UIP_STAT(++uip_stat.tcp.sent); - send: - UIP_STAT(++uip_stat.ip.sent); - /* Return and let the caller do the actual transmission. */ - return; - drop: - uip_len = 0; - return; -} -/*-----------------------------------------------------------------------------------*/ -u16_t -htons(u16_t val) -{ - return HTONS(val); -} -/*-----------------------------------------------------------------------------------*/ -/** @} */ diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/uip.h b/Demo/uIP_Demo_Rowley_ARM7/uip/uip.h deleted file mode 100644 index f6367a261..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/uip/uip.h +++ /dev/null @@ -1,1060 +0,0 @@ -/** - * \addtogroup uip - * @{ - */ - -/** - * \file - * Header file for the uIP TCP/IP stack. - * \author Adam Dunkels - * - * The uIP TCP/IP stack header file contains definitions for a number - * of C macros that are used by uIP programs as well as internal uIP - * structures, TCP/IP header structures and function declarations. - * - */ - - -/* - * Copyright (c) 2001-2003, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: uip.h,v 1.36.2.7 2003/10/07 13:47:51 adam Exp $ - * - */ - -#ifndef __UIP_H__ -#define __UIP_H__ - -#include "uipopt.h" - -/*-----------------------------------------------------------------------------------*/ -/* First, the functions that should be called from the - * system. Initialization, the periodic timer and incoming packets are - * handled by the following three functions. - */ - -/** - * \defgroup uipconffunc uIP configuration functions - * @{ - * - * The uIP configuration functions are used for setting run-time - * parameters in uIP such as IP addresses. - */ - -/** - * Set the IP address of this host. - * - * The IP address is represented as a 4-byte array where the first - * octet of the IP address is put in the first member of the 4-byte - * array. - * - * \param addr A pointer to a 4-byte representation of the IP address. - * - * \hideinitializer - */ -#define uip_sethostaddr(addr) do { uip_hostaddr[0] = addr[0]; \ - uip_hostaddr[1] = addr[1]; } while(0) - -/** - * Get the IP address of this host. - * - * The IP address is represented as a 4-byte array where the first - * octet of the IP address is put in the first member of the 4-byte - * array. - * - * \param addr A pointer to a 4-byte array that will be filled in with - * the currently configured IP address. - * - * \hideinitializer - */ -#define uip_gethostaddr(addr) do { addr[0] = uip_hostaddr[0]; \ - addr[1] = uip_hostaddr[1]; } while(0) - -/** @} */ - -/** - * \defgroup uipinit uIP initialization functions - * @{ - * - * The uIP initialization functions are used for booting uIP. - */ - -/** - * uIP initialization function. - * - * This function should be called at boot up to initilize the uIP - * TCP/IP stack. - */ -void uip_init(void); - -/** @} */ - -/** - * \defgroup uipdevfunc uIP device driver functions - * @{ - * - * These functions are used by a network device driver for interacting - * with uIP. - */ - -/** - * Process an incoming packet. - * - * This function should be called when the device driver has received - * a packet from the network. The packet from the device driver must - * be present in the uip_buf buffer, and the length of the packet - * should be placed in the uip_len variable. - * - * When the function returns, there may be an outbound packet placed - * in the uip_buf packet buffer. If so, the uip_len variable is set to - * the length of the packet. If no packet is to be sent out, the - * uip_len variable is set to 0. - * - * The usual way of calling the function is presented by the source - * code below. - \code - uip_len = devicedriver_poll(); - if(uip_len > 0) { - uip_input(); - if(uip_len > 0) { - devicedriver_send(); - } - } - \endcode - * - * \note If you are writing a uIP device driver that needs ARP - * (Address Resolution Protocol), e.g., when running uIP over - * Ethernet, you will need to call the uIP ARP code before calling - * this function: - \code - #define BUF ((struct uip_eth_hdr *)&uip_buf[0]) - uip_len = ethernet_devicedrver_poll(); - if(uip_len > 0) { - if(BUF->type == HTONS(UIP_ETHTYPE_IP)) { - uip_arp_ipin(); - uip_input(); - if(uip_len > 0) { - uip_arp_out(); - ethernet_devicedriver_send(); - } - } else if(BUF->type == HTONS(UIP_ETHTYPE_ARP)) { - uip_arp_arpin(); - if(uip_len > 0) { - ethernet_devicedriver_send(); - } - } - \endcode - * - * \hideinitializer - */ -#define uip_input() uip_process(UIP_DATA) - -/** - * Periodic processing for a connection identified by its number. - * - * This function does the necessary periodic processing (timers, - * polling) for a uIP TCP conneciton, and should be called when the - * periodic uIP timer goes off. It should be called for every - * connection, regardless of whether they are open of closed. - * - * When the function returns, it may have an outbound packet waiting - * for service in the uIP packet buffer, and if so the uip_len - * variable is set to a value larger than zero. The device driver - * should be called to send out the packet. - * - * The ususal way of calling the function is through a for() loop like - * this: - \code - for(i = 0; i < UIP_CONNS; ++i) { - uip_periodic(i); - if(uip_len > 0) { - devicedriver_send(); - } - } - \endcode - * - * \note If you are writing a uIP device driver that needs ARP - * (Address Resolution Protocol), e.g., when running uIP over - * Ethernet, you will need to call the uip_arp_out() function before - * calling the device driver: - \code - for(i = 0; i < UIP_CONNS; ++i) { - uip_periodic(i); - if(uip_len > 0) { - uip_arp_out(); - ethernet_devicedriver_send(); - } - } - \endcode - * - * \param conn The number of the connection which is to be periodically polled. - * - * \hideinitializer - */ -#define uip_periodic(conn) do { uip_conn = &uip_conns[conn]; \ - uip_process(UIP_TIMER); } while (0) - -/** - * Periodic processing for a connection identified by a pointer to its structure. - * - * Same as uip_periodic() but takes a pointer to the actual uip_conn - * struct instead of an integer as its argument. This function can be - * used to force periodic processing of a specific connection. - * - * \param conn A pointer to the uip_conn struct for the connection to - * be processed. - * - * \hideinitializer - */ -#define uip_periodic_conn(conn) do { uip_conn = conn; \ - uip_process(UIP_TIMER); } while (0) - -#if UIP_UDP -/** - * Periodic processing for a UDP connection identified by its number. - * - * This function is essentially the same as uip_prerioic(), but for - * UDP connections. It is called in a similar fashion as the - * uip_periodic() function: - \code - for(i = 0; i < UIP_UDP_CONNS; i++) { - uip_udp_periodic(i); - if(uip_len > 0) { - devicedriver_send(); - } - } - \endcode - * - * \note As for the uip_periodic() function, special care has to be - * taken when using uIP together with ARP and Ethernet: - \code - for(i = 0; i < UIP_UDP_CONNS; i++) { - uip_udp_periodic(i); - if(uip_len > 0) { - uip_arp_out(); - ethernet_devicedriver_send(); - } - } - \endcode - * - * \param conn The number of the UDP connection to be processed. - * - * \hideinitializer - */ -#define uip_udp_periodic(conn) do { uip_udp_conn = &uip_udp_conns[conn]; \ - uip_process(UIP_UDP_TIMER); } while (0) - -/** - * Periodic processing for a UDP connection identified by a pointer to - * its structure. - * - * Same as uip_udp_periodic() but takes a pointer to the actual - * uip_conn struct instead of an integer as its argument. This - * function can be used to force periodic processing of a specific - * connection. - * - * \param conn A pointer to the uip_udp_conn struct for the connection - * to be processed. - * - * \hideinitializer - */ -#define uip_udp_periodic_conn(conn) do { uip_udp_conn = conn; \ - uip_process(UIP_UDP_TIMER); } while (0) - - -#endif /* UIP_UDP */ - -/** - * The uIP packet buffer. - * - * The uip_buf array is used to hold incoming and outgoing - * packets. The device driver should place incoming data into this - * buffer. When sending data, the device driver should read the link - * level headers and the TCP/IP headers from this buffer. The size of - * the link level headers is configured by the UIP_LLH_LEN define. - * - * \note The application data need not be placed in this buffer, so - * the device driver must read it from the place pointed to by the - * uip_appdata pointer as illustrated by the following example: - \code - void - devicedriver_send(void) - { - hwsend(&uip_buf[0], UIP_LLH_LEN); - hwsend(&uip_buf[UIP_LLH_LEN], 40); - hwsend(uip_appdata, uip_len - 40 - UIP_LLH_LEN); - } - \endcode - */ -extern u8_t uip_buf[UIP_BUFSIZE+2] __attribute__ ((aligned (4))); - -/** @} */ - -/*-----------------------------------------------------------------------------------*/ -/* Functions that are used by the uIP application program. Opening and - * closing connections, sending and receiving data, etc. is all - * handled by the functions below. -*/ -/** - * \defgroup uipappfunc uIP application functions - * @{ - * - * Functions used by an application running of top of uIP. - */ - -/** - * Start listening to the specified port. - * - * \note Since this function expects the port number in network byte - * order, a conversion using HTONS() or htons() is necessary. - * - \code - uip_listen(HTONS(80)); - \endcode - * - * \param port A 16-bit port number in network byte order. - */ -void uip_listen(u16_t port); - -/** - * Stop listening to the specified port. - * - * \note Since this function expects the port number in network byte - * order, a conversion using HTONS() or htons() is necessary. - * - \code - uip_unlisten(HTONS(80)); - \endcode - * - * \param port A 16-bit port number in network byte order. - */ -void uip_unlisten(u16_t port); - -/** - * Connect to a remote host using TCP. - * - * This function is used to start a new connection to the specified - * port on the specied host. It allocates a new connection identifier, - * sets the connection to the SYN_SENT state and sets the - * retransmission timer to 0. This will cause a TCP SYN segment to be - * sent out the next time this connection is periodically processed, - * which usually is done within 0.5 seconds after the call to - * uip_connect(). - * - * \note This function is avaliable only if support for active open - * has been configured by defining UIP_ACTIVE_OPEN to 1 in uipopt.h. - * - * \note Since this function requires the port number to be in network - * byte order, a convertion using HTONS() or htons() is necessary. - * - \code - u16_t ipaddr[2]; - - uip_ipaddr(ipaddr, 192,168,1,2); - uip_connect(ipaddr, HTONS(80)); - \endcode - * - * \param ripaddr A pointer to a 4-byte array representing the IP - * address of the remote hot. - * - * \param port A 16-bit port number in network byte order. - * - * \return A pointer to the uIP connection identifier for the new connection, - * or NULL if no connection could be allocated. - * - */ -struct uip_conn *uip_connect(u16_t *ripaddr, u16_t port); - - - -/** - * \internal - * - * Check if a connection has outstanding (i.e., unacknowledged) data. - * - * \param conn A pointer to the uip_conn structure for the connection. - * - * \hideinitializer - */ -#define uip_outstanding(conn) ((conn)->len) - -/** - * Send data on the current connection. - * - * This function is used to send out a single segment of TCP - * data. Only applications that have been invoked by uIP for event - * processing can send data. - * - * The amount of data that actually is sent out after a call to this - * funcion is determined by the maximum amount of data TCP allows. uIP - * will automatically crop the data so that only the appropriate - * amount of data is sent. The function uip_mss() can be used to query - * uIP for the amount of data that actually will be sent. - * - * \note This function does not guarantee that the sent data will - * arrive at the destination. If the data is lost in the network, the - * application will be invoked with the uip_rexmit() event being - * set. The application will then have to resend the data using this - * function. - * - * \param data A pointer to the data which is to be sent. - * - * \param len The maximum amount of data bytes to be sent. - * - * \hideinitializer - */ -#define uip_send(data, len) do { uip_sappdata = (data); uip_slen = (len);} while(0) - -/** - * The length of any incoming data that is currently avaliable (if avaliable) - * in the uip_appdata buffer. - * - * The test function uip_data() must first be used to check if there - * is any data available at all. - * - * \hideinitializer - */ -#define uip_datalen() uip_len - -/** - * The length of any out-of-band data (urgent data) that has arrived - * on the connection. - * - * \note The configuration parameter UIP_URGDATA must be set for this - * function to be enabled. - * - * \hideinitializer - */ -#define uip_urgdatalen() uip_urglen - -/** - * Close the current connection. - * - * This function will close the current connection in a nice way. - * - * \hideinitializer - */ -#define uip_close() (uip_flags = UIP_CLOSE) - -/** - * Abort the current connection. - * - * This function will abort (reset) the current connection, and is - * usually used when an error has occured that prevents using the - * uip_close() function. - * - * \hideinitializer - */ -#define uip_abort() (uip_flags = UIP_ABORT) - -/** - * Tell the sending host to stop sending data. - * - * This function will close our receiver's window so that we stop - * receiving data for the current connection. - * - * \hideinitializer - */ -#define uip_stop() (uip_conn->tcpstateflags |= UIP_STOPPED) - -/** - * Find out if the current connection has been previously stopped with - * uip_stop(). - * - * \hideinitializer - */ -#define uip_stopped(conn) ((conn)->tcpstateflags & UIP_STOPPED) - -/** - * Restart the current connection, if is has previously been stopped - * with uip_stop(). - * - * This function will open the receiver's window again so that we - * start receiving data for the current connection. - * - * \hideinitializer - */ -#define uip_restart() do { uip_flags |= UIP_NEWDATA; \ - uip_conn->tcpstateflags &= ~UIP_STOPPED; \ - } while(0) - - -/* uIP tests that can be made to determine in what state the current - connection is, and what the application function should do. */ - -/** - * Is new incoming data available? - * - * Will reduce to non-zero if there is new data for the application - * present at the uip_appdata pointer. The size of the data is - * avaliable through the uip_len variable. - * - * \hideinitializer - */ -#define uip_newdata() (uip_flags & UIP_NEWDATA) - -/** - * Has previously sent data been acknowledged? - * - * Will reduce to non-zero if the previously sent data has been - * acknowledged by the remote host. This means that the application - * can send new data. - * - * \hideinitializer - */ -#define uip_acked() (uip_flags & UIP_ACKDATA) - -/** - * Has the connection just been connected? - * - * Reduces to non-zero if the current connection has been connected to - * a remote host. This will happen both if the connection has been - * actively opened (with uip_connect()) or passively opened (with - * uip_listen()). - * - * \hideinitializer - */ -#define uip_connected() (uip_flags & UIP_CONNECTED) - -/** - * Has the connection been closed by the other end? - * - * Is non-zero if the connection has been closed by the remote - * host. The application may then do the necessary clean-ups. - * - * \hideinitializer - */ -#define uip_closed() (uip_flags & UIP_CLOSE) - -/** - * Has the connection been aborted by the other end? - * - * Non-zero if the current connection has been aborted (reset) by the - * remote host. - * - * \hideinitializer - */ -#define uip_aborted() (uip_flags & UIP_ABORT) - -/** - * Has the connection timed out? - * - * Non-zero if the current connection has been aborted due to too many - * retransmissions. - * - * \hideinitializer - */ -#define uip_timedout() (uip_flags & UIP_TIMEDOUT) - -/** - * Do we need to retransmit previously data? - * - * Reduces to non-zero if the previously sent data has been lost in - * the network, and the application should retransmit it. The - * application should send the exact same data as it did the last - * time, using the uip_send() function. - * - * \hideinitializer - */ -#define uip_rexmit() (uip_flags & UIP_REXMIT) - -/** - * Is the connection being polled by uIP? - * - * Is non-zero if the reason the application is invoked is that the - * current connection has been idle for a while and should be - * polled. - * - * The polling event can be used for sending data without having to - * wait for the remote host to send data. - * - * \hideinitializer - */ -#define uip_poll() (uip_flags & UIP_POLL) - -/** - * Get the initial maxium segment size (MSS) of the current - * connection. - * - * \hideinitializer - */ -#define uip_initialmss() (uip_conn->initialmss) - -/** - * Get the current maxium segment size that can be sent on the current - * connection. - * - * The current maxiumum segment size that can be sent on the - * connection is computed from the receiver's window and the MSS of - * the connection (which also is available by calling - * uip_initialmss()). - * - * \hideinitializer - */ -#define uip_mss() (uip_conn->mss) - -/** - * Set up a new UDP connection. - * - * \param ripaddr A pointer to a 4-byte structure representing the IP - * address of the remote host. - * - * \param rport The remote port number in network byte order. - * - * \return The uip_udp_conn structure for the new connection or NULL - * if no connection could be allocated. - */ -struct uip_udp_conn *uip_udp_new(u16_t *ripaddr, u16_t rport); - -/** - * Removed a UDP connection. - * - * \param conn A pointer to the uip_udp_conn structure for the connection. - * - * \hideinitializer - */ -#define uip_udp_remove(conn) (conn)->lport = 0 - -/** - * Send a UDP datagram of length len on the current connection. - * - * This function can only be called in response to a UDP event (poll - * or newdata). The data must be present in the uip_buf buffer, at the - * place pointed to by the uip_appdata pointer. - * - * \param len The length of the data in the uip_buf buffer. - * - * \hideinitializer - */ -#define uip_udp_send(len) uip_slen = (len) - -/** @} */ - -/* uIP convenience and converting functions. */ - -/** - * \defgroup uipconvfunc uIP conversion functions - * @{ - * - * These functions can be used for converting between different data - * formats used by uIP. - */ - -/** - * Pack an IP address into a 4-byte array which is used by uIP to - * represent IP addresses. - * - * Example: - \code - u16_t ipaddr[2]; - - uip_ipaddr(&ipaddr, 192,168,1,2); - \endcode - * - * \param addr A pointer to a 4-byte array that will be filled in with - * the IP addres. - * \param addr0 The first octet of the IP address. - * \param addr1 The second octet of the IP address. - * \param addr2 The third octet of the IP address. - * \param addr3 The forth octet of the IP address. - * - * \hideinitializer - */ -#define uip_ipaddr(addr, addr0,addr1,addr2,addr3) do { \ - (addr)[0] = HTONS(((addr0) << 8) | (addr1)); \ - (addr)[1] = HTONS(((addr2) << 8) | (addr3)); \ - } while(0) - -/** - * Convert 16-bit quantity from host byte order to network byte order. - * - * This macro is primarily used for converting constants from host - * byte order to network byte order. For converting variables to - * network byte order, use the htons() function instead. - * - * \hideinitializer - */ -#ifndef HTONS -# if BYTE_ORDER == BIG_ENDIAN -# define HTONS(n) (n) -# else /* BYTE_ORDER == BIG_ENDIAN */ -# define HTONS(n) ((((u16_t)((n) & 0xff)) << 8) | (((n) & 0xff00) >> 8)) -# endif /* BYTE_ORDER == BIG_ENDIAN */ -#endif /* HTONS */ - -/** - * Convert 16-bit quantity from host byte order to network byte order. - * - * This function is primarily used for converting variables from host - * byte order to network byte order. For converting constants to - * network byte order, use the HTONS() macro instead. - */ -#ifndef htons -u16_t htons(u16_t val); -#endif /* htons */ - -/** @} */ - -/** - * Pointer to the application data in the packet buffer. - * - * This pointer points to the application data when the application is - * called. If the application wishes to send data, the application may - * use this space to write the data into before calling uip_send(). - */ -extern volatile u8_t *uip_appdata; -extern volatile u8_t *uip_sappdata; - -#if UIP_URGDATA > 0 -/* u8_t *uip_urgdata: - * - * This pointer points to any urgent data that has been received. Only - * present if compiled with support for urgent data (UIP_URGDATA). - */ -extern volatile u8_t *uip_urgdata; -#endif /* UIP_URGDATA > 0 */ - - -/* u[8|16]_t uip_len: - * - * When the application is called, uip_len contains the length of any - * new data that has been received from the remote host. The - * application should set this variable to the size of any data that - * the application wishes to send. When the network device driver - * output function is called, uip_len should contain the length of the - * outgoing packet. - */ -extern volatile u16_t uip_len, uip_slen; - -#if UIP_URGDATA > 0 -extern volatile u8_t uip_urglen, uip_surglen; -#endif /* UIP_URGDATA > 0 */ - - -/** - * Representation of a uIP TCP connection. - * - * The uip_conn structure is used for identifying a connection. All - * but one field in the structure are to be considered read-only by an - * application. The only exception is the appstate field whos purpose - * is to let the application store application-specific state (e.g., - * file pointers) for the connection. The size of this field is - * configured in the "uipopt.h" header file. - */ -struct uip_conn { - u16_t ripaddr[2]; /**< The IP address of the remote host. */ - - u16_t lport; /**< The local TCP port, in network byte order. */ - u16_t rport; /**< The local remote TCP port, in network byte - order. */ - - u8_t rcv_nxt[4]; /**< The sequence number that we expect to - receive next. */ - u8_t snd_nxt[4]; /**< The sequence number that was last sent by - us. */ - u16_t len; /**< Length of the data that was previously sent. */ - u16_t mss; /**< Current maximum segment size for the - connection. */ - u16_t initialmss; /**< Initial maximum segment size for the - connection. */ - u8_t sa; /**< Retransmission time-out calculation state - variable. */ - u8_t sv; /**< Retransmission time-out calculation state - variable. */ - u8_t rto; /**< Retransmission time-out. */ - u8_t tcpstateflags; /**< TCP state and flags. */ - u8_t timer; /**< The retransmission timer. */ - u8_t nrtx; /**< The number of retransmissions for the last - segment sent. */ - - /** The application state. */ - u8_t appstate[UIP_APPSTATE_SIZE]; -}; - - -/* Pointer to the current connection. */ -extern struct uip_conn *uip_conn; -/* The array containing all uIP connections. */ -extern struct uip_conn uip_conns[UIP_CONNS]; -/** - * \addtogroup uiparch - * @{ - */ - -/** - * 4-byte array used for the 32-bit sequence number calculations. - */ -extern volatile u8_t uip_acc32[4]; - -/** @} */ - - -#if UIP_UDP -/** - * Representation of a uIP UDP connection. - */ -struct uip_udp_conn { - u16_t ripaddr[2]; /**< The IP address of the remote peer. */ - u16_t lport; /**< The local port number in network byte order. */ - u16_t rport; /**< The remote port number in network byte order. */ -}; - -extern struct uip_udp_conn *uip_udp_conn; -extern struct uip_udp_conn uip_udp_conns[UIP_UDP_CONNS]; -#endif /* UIP_UDP */ - -/** - * The structure holding the TCP/IP statistics that are gathered if - * UIP_STATISTICS is set to 1. - * - */ -struct uip_stats { - struct { - uip_stats_t drop; /**< Number of dropped packets at the IP - layer. */ - uip_stats_t recv; /**< Number of received packets at the IP - layer. */ - uip_stats_t sent; /**< Number of sent packets at the IP - layer. */ - uip_stats_t vhlerr; /**< Number of packets dropped due to wrong - IP version or header length. */ - uip_stats_t hblenerr; /**< Number of packets dropped due to wrong - IP length, high byte. */ - uip_stats_t lblenerr; /**< Number of packets dropped due to wrong - IP length, low byte. */ - uip_stats_t fragerr; /**< Number of packets dropped since they - were IP fragments. */ - uip_stats_t chkerr; /**< Number of packets dropped due to IP - checksum errors. */ - uip_stats_t protoerr; /**< Number of packets dropped since they - were neither ICMP, UDP nor TCP. */ - } ip; /**< IP statistics. */ - struct { - uip_stats_t drop; /**< Number of dropped ICMP packets. */ - uip_stats_t recv; /**< Number of received ICMP packets. */ - uip_stats_t sent; /**< Number of sent ICMP packets. */ - uip_stats_t typeerr; /**< Number of ICMP packets with a wrong - type. */ - } icmp; /**< ICMP statistics. */ - struct { - uip_stats_t drop; /**< Number of dropped TCP segments. */ - uip_stats_t recv; /**< Number of recived TCP segments. */ - uip_stats_t sent; /**< Number of sent TCP segments. */ - uip_stats_t chkerr; /**< Number of TCP segments with a bad - checksum. */ - uip_stats_t ackerr; /**< Number of TCP segments with a bad ACK - number. */ - uip_stats_t rst; /**< Number of recevied TCP RST (reset) segments. */ - uip_stats_t rexmit; /**< Number of retransmitted TCP segments. */ - uip_stats_t syndrop; /**< Number of dropped SYNs due to too few - connections was avaliable. */ - uip_stats_t synrst; /**< Number of SYNs for closed ports, - triggering a RST. */ - } tcp; /**< TCP statistics. */ -}; - -/** - * The uIP TCP/IP statistics. - * - * This is the variable in which the uIP TCP/IP statistics are gathered. - */ -extern struct uip_stats uip_stat; - - -/*-----------------------------------------------------------------------------------*/ -/* All the stuff below this point is internal to uIP and should not be - * used directly by an application or by a device driver. - */ -/*-----------------------------------------------------------------------------------*/ -/* u8_t uip_flags: - * - * When the application is called, uip_flags will contain the flags - * that are defined in this file. Please read below for more - * infomation. - */ -extern volatile u8_t uip_flags; - -/* The following flags may be set in the global variable uip_flags - before calling the application callback. The UIP_ACKDATA and - UIP_NEWDATA flags may both be set at the same time, whereas the - others are mutualy exclusive. Note that these flags should *NOT* be - accessed directly, but through the uIP functions/macros. */ - -#define UIP_ACKDATA 1 /* Signifies that the outstanding data was - acked and the application should send - out new data instead of retransmitting - the last data. */ -#define UIP_NEWDATA 2 /* Flags the fact that the peer has sent - us new data. */ -#define UIP_REXMIT 4 /* Tells the application to retransmit the - data that was last sent. */ -#define UIP_POLL 8 /* Used for polling the application, to - check if the application has data that - it wants to send. */ -#define UIP_CLOSE 16 /* The remote host has closed the - connection, thus the connection has - gone away. Or the application signals - that it wants to close the - connection. */ -#define UIP_ABORT 32 /* The remote host has aborted the - connection, thus the connection has - gone away. Or the application signals - that it wants to abort the - connection. */ -#define UIP_CONNECTED 64 /* We have got a connection from a remote - host and have set up a new connection - for it, or an active connection has - been successfully established. */ - -#define UIP_TIMEDOUT 128 /* The connection has been aborted due to - too many retransmissions. */ - - -/* uip_process(flag): - * - * The actual uIP function which does all the work. - */ -void uip_process(u8_t flag); - -/* The following flags are passed as an argument to the uip_process() - function. They are used to distinguish between the two cases where - uip_process() is called. It can be called either because we have - incoming data that should be processed, or because the periodic - timer has fired. */ - -#define UIP_DATA 1 /* Tells uIP that there is incoming data in - the uip_buf buffer. The length of the - data is stored in the global variable - uip_len. */ -#define UIP_TIMER 2 /* Tells uIP that the periodic timer has - fired. */ -#if UIP_UDP -#define UIP_UDP_TIMER 3 -#endif /* UIP_UDP */ - -/* The TCP states used in the uip_conn->tcpstateflags. */ -#define CLOSED 0 -#define SYN_RCVD 1 -#define SYN_SENT 2 -#define ESTABLISHED 3 -#define FIN_WAIT_1 4 -#define FIN_WAIT_2 5 -#define CLOSING 6 -#define TIME_WAIT 7 -#define LAST_ACK 8 -#define TS_MASK 15 - -#define UIP_STOPPED 16 - -#define UIP_TCPIP_HLEN 40 - -/* The TCP and IP headers. */ -typedef struct { - /* IP header. */ - u8_t vhl, - tos, - len[2], - ipid[2], - ipoffset[2], - ttl, - proto; - u16_t ipchksum; - u16_t srcipaddr[2], - destipaddr[2]; - - /* TCP header. */ - u16_t srcport, - destport; - u8_t seqno[4], - ackno[4], - tcpoffset, - flags, - wnd[2]; - u16_t tcpchksum; - u8_t urgp[2]; - u8_t optdata[4]; -} uip_tcpip_hdr; - -/* The ICMP and IP headers. */ -typedef struct { - /* IP header. */ - u8_t vhl, - tos, - len[2], - ipid[2], - ipoffset[2], - ttl, - proto; - u16_t ipchksum; - u16_t srcipaddr[2], - destipaddr[2]; - /* ICMP (echo) header. */ - u8_t type, icode; - u16_t icmpchksum; - u16_t id, seqno; -} uip_icmpip_hdr; - - -/* The UDP and IP headers. */ -typedef struct { - /* IP header. */ - u8_t vhl, - tos, - len[2], - ipid[2], - ipoffset[2], - ttl, - proto; - u16_t ipchksum; - u16_t srcipaddr[2], - destipaddr[2]; - - /* UDP header. */ - u16_t srcport, - destport; - u16_t udplen; - u16_t udpchksum; -} uip_udpip_hdr; - -#define UIP_PROTO_ICMP 1 -#define UIP_PROTO_TCP 6 -#define UIP_PROTO_UDP 17 - -#if UIP_FIXEDADDR -extern const u16_t uip_hostaddr[2]; -#else /* UIP_FIXEDADDR */ -extern u16_t uip_hostaddr[2]; -#endif /* UIP_FIXEDADDR */ - -#endif /* __UIP_H__ */ - - -/** @} */ - diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arch.c b/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arch.c deleted file mode 100644 index 4cd08c3c7..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arch.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - * Copyright (c) 2001, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: uip_arch.c,v 1.2.2.1 2003/10/04 22:54:17 adam Exp $ - * - */ - - -#include "uip.h" -#include "uip_arch.h" -#include <__cross_studio_io.h> - -#define BUF ((uip_tcpip_hdr *)&uip_buf[UIP_LLH_LEN]) -#define IP_PROTO_TCP 6 - -/*-----------------------------------------------------------------------------------*/ -void -uip_add32(u8_t *op32, u16_t op16) -{ - - uip_acc32[3] = op32[3] + (op16 & 0xff); - uip_acc32[2] = op32[2] + (op16 >> 8); - uip_acc32[1] = op32[1]; - uip_acc32[0] = op32[0]; - - if(uip_acc32[2] < (op16 >> 8)) { - ++uip_acc32[1]; - if(uip_acc32[1] == 0) { - ++uip_acc32[0]; - } - } - - - if(uip_acc32[3] < (op16 & 0xff)) { - ++uip_acc32[2]; - if(uip_acc32[2] == 0) { - ++uip_acc32[1]; - if(uip_acc32[1] == 0) { - ++uip_acc32[0]; - } - } - } -} -/*-----------------------------------------------------------------------------------*/ -u16_t -uip_chksum(u16_t *sdata, u16_t len) -{ - u16_t acc; - - for (acc = 0; len > 1; len -= 2) { - u16_t u = ((unsigned char *)sdata)[0] + (((unsigned char *)sdata)[1] << 8); - if ((acc += u) < u) { - /* Overflow, so we add the carry to acc (i.e., increase by - one). */ - ++acc; - } - ++sdata; - } - - /* add up any odd byte */ - if(len == 1) { - acc += htons(((u16_t)(*(u8_t *)sdata)) << 8); - if(acc < htons(((u16_t)(*(u8_t *)sdata)) << 8)) { - ++acc; - } - } - - return acc; -} -/*-----------------------------------------------------------------------------------*/ -u16_t -uip_ipchksum(void) -{ - return uip_chksum((u16_t *)&uip_buf[UIP_LLH_LEN], 20); -} -/*-----------------------------------------------------------------------------------*/ -u16_t -uip_tcpchksum(void) -{ - u16_t hsum, sum; - - - /* Compute the checksum of the TCP header. */ - hsum = uip_chksum((u16_t *)&uip_buf[20 + UIP_LLH_LEN], 20); - - /* Compute the checksum of the data in the TCP packet and add it to - the TCP header checksum. */ - sum = uip_chksum((u16_t *)uip_appdata, - (u16_t)(((((u16_t)(BUF->len[0]) << 8) + BUF->len[1]) - 40))); - - if((sum += hsum) < hsum) { - ++sum; - } - - if((sum += BUF->srcipaddr[0]) < BUF->srcipaddr[0]) { - ++sum; - } - if((sum += BUF->srcipaddr[1]) < BUF->srcipaddr[1]) { - ++sum; - } - if((sum += BUF->destipaddr[0]) < BUF->destipaddr[0]) { - ++sum; - } - if((sum += BUF->destipaddr[1]) < BUF->destipaddr[1]) { - ++sum; - } - if((sum += (u16_t)htons((u16_t)IP_PROTO_TCP)) < (u16_t)htons((u16_t)IP_PROTO_TCP)) { - ++sum; - } - - hsum = (u16_t)htons((((u16_t)(BUF->len[0]) << 8) + BUF->len[1]) - 20); - - if((sum += hsum) < hsum) { - ++sum; - } - - return sum; -} -/*-----------------------------------------------------------------------------------*/ diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arch.h b/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arch.h deleted file mode 100644 index b2d133f2e..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arch.h +++ /dev/null @@ -1,130 +0,0 @@ -/** - * \defgroup uiparch Architecture specific uIP functions - * @{ - * - * The functions in the architecture specific module implement the IP - * check sum and 32-bit additions. - * - * The IP checksum calculation is the most computationally expensive - * operation in the TCP/IP stack and it therefore pays off to - * implement this in efficient assembler. The purpose of the uip-arch - * module is to let the checksum functions to be implemented in - * architecture specific assembler. - * - */ - -/** - * \file - * Declarations of architecture specific functions. - * \author Adam Dunkels - */ - -/* - * Copyright (c) 2001, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: uip_arch.h,v 1.1.2.2 2003/10/06 15:10:22 adam Exp $ - * - */ - -#ifndef __UIP_ARCH_H__ -#define __UIP_ARCH_H__ - -#include "uip.h" - -/** - * Carry out a 32-bit addition. - * - * Because not all architectures for which uIP is intended has native - * 32-bit arithmetic, uIP uses an external C function for doing the - * required 32-bit additions in the TCP protocol processing. This - * function should add the two arguments and place the result in the - * global variable uip_acc32. - * - * \note The 32-bit integer pointed to by the op32 parameter and the - * result in the uip_acc32 variable are in network byte order (big - * endian). - * - * \param op32 A pointer to a 4-byte array representing a 32-bit - * integer in network byte order (big endian). - * - * \param op16 A 16-bit integer in host byte order. - */ -void uip_add32(u8_t *op32, u16_t op16); - -/** - * Calculate the Internet checksum over a buffer. - * - * The Internet checksum is the one's complement of the one's - * complement sum of all 16-bit words in the buffer. - * - * See RFC1071. - * - * \note This function is not called in the current version of uIP, - * but future versions might make use of it. - * - * \param buf A pointer to the buffer over which the checksum is to be - * computed. - * - * \param len The length of the buffer over which the checksum is to - * be computed. - * - * \return The Internet checksum of the buffer. - */ -u16_t uip_chksum(u16_t *buf, u16_t len); - -/** - * Calculate the IP header checksum of the packet header in uip_buf. - * - * The IP header checksum is the Internet checksum of the 20 bytes of - * the IP header. - * - * \return The IP header checksum of the IP header in the uip_buf - * buffer. - */ -u16_t uip_ipchksum(void); - -/** - * Calculate the TCP checksum of the packet in uip_buf and uip_appdata. - * - * The TCP checksum is the Internet checksum of data contents of the - * TCP segment, and a pseudo-header as defined in RFC793. - * - * \note The uip_appdata pointer that points to the packet data may - * point anywhere in memory, so it is not possible to simply calculate - * the Internet checksum of the contents of the uip_buf buffer. - * - * \return The TCP checksum of the TCP segment in uip_buf and pointed - * to by uip_appdata. - */ -u16_t uip_tcpchksum(void); - -/** @} */ - -#endif /* __UIP_ARCH_H__ */ diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arp.c b/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arp.c deleted file mode 100644 index f2804df95..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arp.c +++ /dev/null @@ -1,427 +0,0 @@ -/** - * \addtogroup uip - * @{ - */ - -/** - * \defgroup uiparp uIP Address Resolution Protocol - * @{ - * - * The Address Resolution Protocol ARP is used for mapping between IP - * addresses and link level addresses such as the Ethernet MAC - * addresses. ARP uses broadcast queries to ask for the link level - * address of a known IP address and the host which is configured with - * the IP address for which the query was meant, will respond with its - * link level address. - * - * \note This ARP implementation only supports Ethernet. - */ - -/** - * \file - * Implementation of the ARP Address Resolution Protocol. - * \author Adam Dunkels - * - */ - -/* - * Copyright (c) 2001-2003, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: uip_arp.c,v 1.7.2.3 2003/10/06 22:42:30 adam Exp $ - * - */ - - -#include "uip_arp.h" - -#include - -struct arp_hdr { - struct uip_eth_hdr ethhdr; - u16_t hwtype; - u16_t protocol; - u8_t hwlen; - u8_t protolen; - u16_t opcode; - struct uip_eth_addr shwaddr; - u16_t sipaddr[2]; - struct uip_eth_addr dhwaddr; - u16_t dipaddr[2]; -}; - -struct ethip_hdr { - struct uip_eth_hdr ethhdr; - /* IP header. */ - u8_t vhl, - tos, - len[2], - ipid[2], - ipoffset[2], - ttl, - proto; - u16_t ipchksum; - u16_t srcipaddr[2], - destipaddr[2]; -}; - -#define ARP_REQUEST 1 -#define ARP_REPLY 2 - -#define ARP_HWTYPE_ETH 1 - -struct arp_entry { - u16_t ipaddr[2]; - struct uip_eth_addr ethaddr; - u8_t time; -}; - -struct uip_eth_addr uip_ethaddr = {{UIP_ETHADDR0, - UIP_ETHADDR1, - UIP_ETHADDR2, - UIP_ETHADDR3, - UIP_ETHADDR4, - UIP_ETHADDR5}}; - -static struct arp_entry arp_table[UIP_ARPTAB_SIZE]; -static u16_t ipaddr[2]; -static u8_t i, c; - -static u8_t arptime; -static u8_t tmpage; - -#define BUF ((struct arp_hdr *)&uip_buf[0]) -#define IPBUF ((struct ethip_hdr *)&uip_buf[0]) -/*-----------------------------------------------------------------------------------*/ -/** - * Initialize the ARP module. - * - */ -/*-----------------------------------------------------------------------------------*/ -void -uip_arp_init(void) -{ - for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { - memset(arp_table[i].ipaddr, 0, 4); - } -} -/*-----------------------------------------------------------------------------------*/ -/** - * Periodic ARP processing function. - * - * This function performs periodic timer processing in the ARP module - * and should be called at regular intervals. The recommended interval - * is 10 seconds between the calls. - * - */ -/*-----------------------------------------------------------------------------------*/ -void -uip_arp_timer(void) -{ - struct arp_entry *tabptr; - - ++arptime; - for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { - tabptr = &arp_table[i]; - if((tabptr->ipaddr[0] | tabptr->ipaddr[1]) != 0 && - arptime - tabptr->time >= UIP_ARP_MAXAGE) { - memset(tabptr->ipaddr, 0, 4); - } - } - -} -/*-----------------------------------------------------------------------------------*/ -static void -uip_arp_update(u16_t *ipaddr, struct uip_eth_addr *ethaddr) -{ - register struct arp_entry *tabptr; - /* Walk through the ARP mapping table and try to find an entry to - update. If none is found, the IP -> MAC address mapping is - inserted in the ARP table. */ - for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { - - tabptr = &arp_table[i]; - /* Only check those entries that are actually in use. */ - if(tabptr->ipaddr[0] != 0 && - tabptr->ipaddr[1] != 0) { - - /* Check if the source IP address of the incoming packet matches - the IP address in this ARP table entry. */ - if(ipaddr[0] == tabptr->ipaddr[0] && - ipaddr[1] == tabptr->ipaddr[1]) { - - /* An old entry found, update this and return. */ - memcpy(tabptr->ethaddr.addr, ethaddr->addr, 6); - tabptr->time = arptime; - - return; - } - } - } - - /* If we get here, no existing ARP table entry was found, so we - create one. */ - - /* First, we try to find an unused entry in the ARP table. */ - for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { - tabptr = &arp_table[i]; - if(tabptr->ipaddr[0] == 0 && - tabptr->ipaddr[1] == 0) { - break; - } - } - - /* If no unused entry is found, we try to find the oldest entry and - throw it away. */ - if(i == UIP_ARPTAB_SIZE) { - tmpage = 0; - c = 0; - for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { - tabptr = &arp_table[i]; - if(arptime - tabptr->time > tmpage) { - tmpage = arptime - tabptr->time; - c = i; - } - } - i = c; - } - - /* Now, i is the ARP table entry which we will fill with the new - information. */ - memcpy(tabptr->ipaddr, ipaddr, 4); - memcpy(tabptr->ethaddr.addr, ethaddr->addr, 6); - tabptr->time = arptime; -} -/*-----------------------------------------------------------------------------------*/ -/** - * ARP processing for incoming IP packets - * - * This function should be called by the device driver when an IP - * packet has been received. The function will check if the address is - * in the ARP cache, and if so the ARP cache entry will be - * refreshed. If no ARP cache entry was found, a new one is created. - * - * This function expects an IP packet with a prepended Ethernet header - * in the uip_buf[] buffer, and the length of the packet in the global - * variable uip_len. - */ -/*-----------------------------------------------------------------------------------*/ -void -uip_arp_ipin(void) -{ - uip_len -= sizeof(struct uip_eth_hdr); - - /* Only insert/update an entry if the source IP address of the - incoming IP packet comes from a host on the local network. */ - if((IPBUF->srcipaddr[0] & uip_arp_netmask[0]) != - (uip_hostaddr[0] & uip_arp_netmask[0])) { - return; - } - if((IPBUF->srcipaddr[1] & uip_arp_netmask[1]) != - (uip_hostaddr[1] & uip_arp_netmask[1])) { - return; - } - uip_arp_update(IPBUF->srcipaddr, &(IPBUF->ethhdr.src)); - - return; -} -/*-----------------------------------------------------------------------------------*/ -/** - * ARP processing for incoming ARP packets. - * - * This function should be called by the device driver when an ARP - * packet has been received. The function will act differently - * depending on the ARP packet type: if it is a reply for a request - * that we previously sent out, the ARP cache will be filled in with - * the values from the ARP reply. If the incoming ARP packet is an ARP - * request for our IP address, an ARP reply packet is created and put - * into the uip_buf[] buffer. - * - * When the function returns, the value of the global variable uip_len - * indicates whether the device driver should send out a packet or - * not. If uip_len is zero, no packet should be sent. If uip_len is - * non-zero, it contains the length of the outbound packet that is - * present in the uip_buf[] buffer. - * - * This function expects an ARP packet with a prepended Ethernet - * header in the uip_buf[] buffer, and the length of the packet in the - * global variable uip_len. - */ -/*-----------------------------------------------------------------------------------*/ -typedef struct arp_hdr aht; - -void -uip_arp_arpin(void) -{ - int ul; - - if(uip_len < sizeof(struct arp_hdr)) { - uip_len = 0; - return; - } - - uip_len = 0; - - switch(BUF->opcode) { - case HTONS(ARP_REQUEST): - /* ARP request. If it asked for our address, we send out a - reply. */ - if(BUF->dipaddr[0] == uip_hostaddr[0] && - BUF->dipaddr[1] == uip_hostaddr[1]) { - /* The reply opcode is 2. */ - BUF->opcode = HTONS(2); - - memcpy(BUF->dhwaddr.addr, BUF->shwaddr.addr, 6); - memcpy(BUF->shwaddr.addr, uip_ethaddr.addr, 6); - memcpy(BUF->ethhdr.src.addr, uip_ethaddr.addr, 6); - memcpy(BUF->ethhdr.dest.addr, BUF->dhwaddr.addr, 6); - - BUF->dipaddr[0] = BUF->sipaddr[0]; - BUF->dipaddr[1] = BUF->sipaddr[1]; - BUF->sipaddr[0] = uip_hostaddr[0]; - BUF->sipaddr[1] = uip_hostaddr[1]; - - ul = BUF->hwlen; - BUF->ethhdr.type = HTONS(UIP_ETHTYPE_ARP); - uip_len = sizeof(struct arp_hdr); - } - break; - case HTONS(ARP_REPLY): - /* ARP reply. We insert or update the ARP table if it was meant - for us. */ - if(BUF->dipaddr[0] == uip_hostaddr[0] && - BUF->dipaddr[1] == uip_hostaddr[1]) { - - uip_arp_update(BUF->sipaddr, &BUF->shwaddr); - } - break; - } - - return; -} -/*-----------------------------------------------------------------------------------*/ -/** - * Prepend Ethernet header to an outbound IP packet and see if we need - * to send out an ARP request. - * - * This function should be called before sending out an IP packet. The - * function checks the destination IP address of the IP packet to see - * what Ethernet MAC address that should be used as a destination MAC - * address on the Ethernet. - * - * If the destination IP address is in the local network (determined - * by logical ANDing of netmask and our IP address), the function - * checks the ARP cache to see if an entry for the destination IP - * address is found. If so, an Ethernet header is prepended and the - * function returns. If no ARP cache entry is found for the - * destination IP address, the packet in the uip_buf[] is replaced by - * an ARP request packet for the IP address. The IP packet is dropped - * and it is assumed that they higher level protocols (e.g., TCP) - * eventually will retransmit the dropped packet. - * - * If the destination IP address is not on the local network, the IP - * address of the default router is used instead. - * - * When the function returns, a packet is present in the uip_buf[] - * buffer, and the length of the packet is in the global variable - * uip_len. - */ -/*-----------------------------------------------------------------------------------*/ -void -uip_arp_out(void) -{ - struct arp_entry *tabptr; - /* Find the destination IP address in the ARP table and construct - the Ethernet header. If the destination IP addres isn't on the - local network, we use the default router's IP address instead. - - If not ARP table entry is found, we overwrite the original IP - packet with an ARP request for the IP address. */ - - /* Check if the destination address is on the local network. */ - if((IPBUF->destipaddr[0] & uip_arp_netmask[0]) != - (uip_hostaddr[0] & uip_arp_netmask[0]) || - (IPBUF->destipaddr[1] & uip_arp_netmask[1]) != - (uip_hostaddr[1] & uip_arp_netmask[1])) { - /* Destination address was not on the local network, so we need to - use the default router's IP address instead of the destination - address when determining the MAC address. */ - ipaddr[0] = uip_arp_draddr[0]; - ipaddr[1] = uip_arp_draddr[1]; - } else { - /* Else, we use the destination IP address. */ - ipaddr[0] = IPBUF->destipaddr[0]; - ipaddr[1] = IPBUF->destipaddr[1]; - } - - for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { - tabptr = &arp_table[i]; - if(ipaddr[0] == tabptr->ipaddr[0] && - ipaddr[1] == tabptr->ipaddr[1]) - break; - } - - if(i == UIP_ARPTAB_SIZE) { - /* The destination address was not in our ARP table, so we - overwrite the IP packet with an ARP request. */ - - memset(BUF->ethhdr.dest.addr, 0xff, 6); - memset(BUF->dhwaddr.addr, 0x00, 6); - memcpy(BUF->ethhdr.src.addr, uip_ethaddr.addr, 6); - memcpy(BUF->shwaddr.addr, uip_ethaddr.addr, 6); - - BUF->dipaddr[0] = ipaddr[0]; - BUF->dipaddr[1] = ipaddr[1]; - BUF->sipaddr[0] = uip_hostaddr[0]; - BUF->sipaddr[1] = uip_hostaddr[1]; - BUF->opcode = HTONS(ARP_REQUEST); /* ARP request. */ - BUF->hwtype = HTONS(ARP_HWTYPE_ETH); - BUF->protocol = HTONS(UIP_ETHTYPE_IP); - BUF->hwlen = 6; - BUF->protolen = 4; - BUF->ethhdr.type = HTONS(UIP_ETHTYPE_ARP); - - uip_appdata = &uip_buf[40 + UIP_LLH_LEN]; - - uip_len = sizeof(struct arp_hdr); - return; - } - - /* Build an ethernet header. */ - memcpy(IPBUF->ethhdr.dest.addr, tabptr->ethaddr.addr, 6); - memcpy(IPBUF->ethhdr.src.addr, uip_ethaddr.addr, 6); - - IPBUF->ethhdr.type = HTONS(UIP_ETHTYPE_IP); - - uip_len += sizeof(struct uip_eth_hdr); -} -/*-----------------------------------------------------------------------------------*/ - -/** @} */ -/** @} */ diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arp.h b/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arp.h deleted file mode 100644 index bf9049888..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/uip/uip_arp.h +++ /dev/null @@ -1,201 +0,0 @@ -/** - * \addtogroup uip - * @{ - */ - -/** - * \addtogroup uiparp - * @{ - */ - -/** - * \file - * Macros and definitions for the ARP module. - * \author Adam Dunkels - */ - - -/* - * Copyright (c) 2001-2003, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: uip_arp.h,v 1.3.2.2 2003/10/06 15:10:22 adam Exp $ - * - */ - -#ifndef __UIP_ARP_H__ -#define __UIP_ARP_H__ - -#include "uip.h" - - -/** - * Representation of a 48-bit Ethernet address. - */ -struct uip_eth_addr { - u8_t addr[6]; -} __attribute__ ((packed, aligned (1))); - -extern struct uip_eth_addr uip_ethaddr; - -/** - * The Ethernet header. - */ -struct uip_eth_hdr { - struct uip_eth_addr dest; - struct uip_eth_addr src; - u16_t type; -} __attribute__ ((packed)); - -#define UIP_ETHTYPE_ARP 0x0806 -#define UIP_ETHTYPE_IP 0x0800 -#define UIP_ETHTYPE_IP6 0x86dd - - -/* The uip_arp_init() function must be called before any of the other - ARP functions. */ -void uip_arp_init(void); - -/* The uip_arp_ipin() function should be called whenever an IP packet - arrives from the Ethernet. This function refreshes the ARP table or - inserts a new mapping if none exists. The function assumes that an - IP packet with an Ethernet header is present in the uip_buf buffer - and that the length of the packet is in the uip_len variable. */ -void uip_arp_ipin(void); - -/* The uip_arp_arpin() should be called when an ARP packet is received - by the Ethernet driver. This function also assumes that the - Ethernet frame is present in the uip_buf buffer. When the - uip_arp_arpin() function returns, the contents of the uip_buf - buffer should be sent out on the Ethernet if the uip_len variable - is > 0. */ -void uip_arp_arpin(void); - -/* The uip_arp_out() function should be called when an IP packet - should be sent out on the Ethernet. This function creates an - Ethernet header before the IP header in the uip_buf buffer. The - Ethernet header will have the correct Ethernet MAC destination - address filled in if an ARP table entry for the destination IP - address (or the IP address of the default router) is present. If no - such table entry is found, the IP packet is overwritten with an ARP - request and we rely on TCP to retransmit the packet that was - overwritten. In any case, the uip_len variable holds the length of - the Ethernet frame that should be transmitted. */ -void uip_arp_out(void); - -/* The uip_arp_timer() function should be called every ten seconds. It - is responsible for flushing old entries in the ARP table. */ -void uip_arp_timer(void); - -/** @} */ - -/** - * \addtogroup uipconffunc - * @{ - */ - -/** - * Set the default router's IP address. - * - * \param addr A pointer to a 4-byte array containing the IP address - * of the default router. - * - * \hideinitializer - */ -#define uip_setdraddr(addr) do { uip_arp_draddr[0] = addr[0]; \ - uip_arp_draddr[1] = addr[1]; } while(0) - -/** - * Set the netmask. - * - * \param addr A pointer to a 4-byte array containing the IP address - * of the netmask. - * - * \hideinitializer - */ -#define uip_setnetmask(addr) do { uip_arp_netmask[0] = addr[0]; \ - uip_arp_netmask[1] = addr[1]; } while(0) - - -/** - * Get the default router's IP address. - * - * \param addr A pointer to a 4-byte array that will be filled in with - * the IP address of the default router. - * - * \hideinitializer - */ -#define uip_getdraddr(addr) do { addr[0] = uip_arp_draddr[0]; \ - addr[1] = uip_arp_draddr[1]; } while(0) - -/** - * Get the netmask. - * - * \param addr A pointer to a 4-byte array that will be filled in with - * the value of the netmask. - * - * \hideinitializer - */ -#define uip_getnetmask(addr) do { addr[0] = uip_arp_netmask[0]; \ - addr[1] = uip_arp_netmask[1]; } while(0) - - -/** - * Specifiy the Ethernet MAC address. - * - * The ARP code needs to know the MAC address of the Ethernet card in - * order to be able to respond to ARP queries and to generate working - * Ethernet headers. - * - * \note This macro only specifies the Ethernet MAC address to the ARP - * code. It cannot be used to change the MAC address of the Ethernet - * card. - * - * \param eaddr A pointer to a struct uip_eth_addr containing the - * Ethernet MAC address of the Ethernet card. - * - * \hideinitializer - */ -#define uip_setethaddr(eaddr) do {uip_ethaddr.addr[0] = eaddr.addr[0]; \ - uip_ethaddr.addr[1] = eaddr.addr[1];\ - uip_ethaddr.addr[2] = eaddr.addr[2];\ - uip_ethaddr.addr[3] = eaddr.addr[3];\ - uip_ethaddr.addr[4] = eaddr.addr[4];\ - uip_ethaddr.addr[5] = eaddr.addr[5];} while(0) - -/** @} */ - -/** - * \internal Internal variables that are set using the macros - * uip_setdraddr and uip_setnetmask. - */ -extern u16_t uip_arp_draddr[2], uip_arp_netmask[2]; -#endif /* __UIP_ARP_H__ */ - - diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/uipopt.h b/Demo/uIP_Demo_Rowley_ARM7/uip/uipopt.h deleted file mode 100644 index 9d274d534..000000000 --- a/Demo/uIP_Demo_Rowley_ARM7/uip/uipopt.h +++ /dev/null @@ -1,602 +0,0 @@ -/** - * \defgroup uipopt Configuration options for uIP - * @{ - * - * uIP is configured using the per-project configuration file - * "uipopt.h". This file contains all compile-time options for uIP and - * should be tweaked to match each specific project. The uIP - * distribution contains a documented example "uipopt.h" that can be - * copied and modified for each project. - */ - -/** - * \file - * Configuration options for uIP. - * \author Adam Dunkels - * - * This file is used for tweaking various configuration options for - * uIP. You should make a copy of this file into one of your project's - * directories instead of editing this example "uipopt.h" file that - * comes with the uIP distribution. - */ - -/* - * Copyright (c) 2001-2003, Adam Dunkels. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS - * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE - * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack. - * - * $Id: uipopt.h,v 1.16.2.5 2003/10/07 13:22:51 adam Exp $ - * - */ - -#ifndef __UIPOPT_H__ -#define __UIPOPT_H__ - -/*------------------------------------------------------------------------------*/ -/** - * \defgroup uipopttypedef uIP type definitions - * @{ - */ - -/** - * The 8-bit unsigned data type. - * - * This may have to be tweaked for your particular compiler. "unsigned - * char" works for most compilers. - */ -typedef unsigned char u8_t; - -/** - * The 16-bit unsigned data type. - * - * This may have to be tweaked for your particular compiler. "unsigned - * short" works for most compilers. - */ -typedef unsigned short u16_t; - -/** - * The statistics data type. - * - * This datatype determines how high the statistics counters are able - * to count. - */ -typedef unsigned short uip_stats_t; - -/** @} */ - -/*------------------------------------------------------------------------------*/ - -/** - * \defgroup uipoptstaticconf Static configuration options - * @{ - * - * These configuration options can be used for setting the IP address - * settings statically, but only if UIP_FIXEDADDR is set to 1. The - * configuration options for a specific node includes IP address, - * netmask and default router as well as the Ethernet address. The - * netmask, default router and Ethernet address are appliciable only - * if uIP should be run over Ethernet. - * - * All of these should be changed to suit your project. -*/ - -/** - * Determines if uIP should use a fixed IP address or not. - * - * If uIP should use a fixed IP address, the settings are set in the - * uipopt.h file. If not, the macros uip_sethostaddr(), - * uip_setdraddr() and uip_setnetmask() should be used instead. - * - * \hideinitializer - */ -#define UIP_FIXEDADDR 1 - -/** - * Ping IP address asignment. - * - * uIP uses a "ping" packets for setting its own IP address if this - * option is set. If so, uIP will start with an empty IP address and - * the destination IP address of the first incoming "ping" (ICMP echo) - * packet will be used for setting the hosts IP address. - * - * \note This works only if UIP_FIXEDADDR is 0. - * - * \hideinitializer - */ -#define UIP_PINGADDRCONF 0 - -#if 0 -#define UIP_IPADDR0 172U /**< The first octet of the IP address of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_IPADDR1 25U /**< The second octet of the IP address of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_IPADDR2 218U /**< The third octet of the IP address of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_IPADDR3 202U /**< The fourth octet of the IP address of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ - -#define UIP_NETMASK0 255 /**< The first octet of the netmask of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_NETMASK1 255 /**< The second octet of the netmask of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_NETMASK2 255 /**< The third octet of the netmask of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_NETMASK3 0 /**< The fourth octet of the netmask of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ - - -#define UIP_DRIPADDR0 192 /**< The first octet of the IP address of - the default router, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_DRIPADDR1 168 /**< The second octet of the IP address of - the default router, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_DRIPADDR2 0 /**< The third octet of the IP address of - the default router, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_DRIPADDR3 1 /**< The fourth octet of the IP address of - the default router, if UIP_FIXEDADDR is - 1. \hideinitializer */ - -#else - -#define UIP_IPADDR0 172U /**< The first octet of the IP address of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_IPADDR1 25U /**< The second octet of the IP address of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_IPADDR2 218U /**< The third octet of the IP address of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_IPADDR3 202U /**< The fourth octet of the IP address of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ - -#define UIP_NETMASK0 255 /**< The first octet of the netmask of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_NETMASK1 255 /**< The second octet of the netmask of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_NETMASK2 255 /**< The third octet of the netmask of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_NETMASK3 0 /**< The fourth octet of the netmask of - this uIP node, if UIP_FIXEDADDR is - 1. \hideinitializer */ - -#define UIP_DRIPADDR0 172 /**< The first octet of the IP address of - the default router, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_DRIPADDR1 25 /**< The second octet of the IP address of - the default router, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_DRIPADDR2 218 /**< The third octet of the IP address of - the default router, if UIP_FIXEDADDR is - 1. \hideinitializer */ -#define UIP_DRIPADDR3 3 /**< The fourth octet of the IP address of - the default router, if UIP_FIXEDADDR is - 1. \hideinitializer */ - -#endif - -/** - * Specifies if the uIP ARP module should be compiled with a fixed - * Ethernet MAC address or not. - * - * If this configuration option is 0, the macro uip_setethaddr() can - * be used to specify the Ethernet address at run-time. - * - * \hideinitializer - */ -#define UIP_FIXEDETHADDR 0 - -#define UIP_ETHADDR0 0x00 /**< The first octet of the Ethernet - address if UIP_FIXEDETHADDR is - 1. \hideinitializer */ -#define UIP_ETHADDR1 0xbd /**< The second octet of the Ethernet - address if UIP_FIXEDETHADDR is - 1. \hideinitializer */ -#define UIP_ETHADDR2 0x3b /**< The third octet of the Ethernet - address if UIP_FIXEDETHADDR is - 1. \hideinitializer */ -#define UIP_ETHADDR3 0x33 /**< The fourth octet of the Ethernet - address if UIP_FIXEDETHADDR is - 1. \hideinitializer */ -#define UIP_ETHADDR4 0x05 /**< The fifth octet of the Ethernet - address if UIP_FIXEDETHADDR is - 1. \hideinitializer */ -#define UIP_ETHADDR5 0x71 /**< The sixth octet of the Ethernet - address if UIP_FIXEDETHADDR is - 1. \hideinitializer */ - -/** @} */ -/*------------------------------------------------------------------------------*/ -/** - * \defgroup uipoptip IP configuration options - * @{ - * - */ -/** - * The IP TTL (time to live) of IP packets sent by uIP. - * - * This should normally not be changed. - */ -#define UIP_TTL 255 - -/** - * Turn on support for IP packet reassembly. - * - * uIP supports reassembly of fragmented IP packets. This features - * requires an additonal amount of RAM to hold the reassembly buffer - * and the reassembly code size is approximately 700 bytes. The - * reassembly buffer is of the same size as the uip_buf buffer - * (configured by UIP_BUFSIZE). - * - * \note IP packet reassembly is not heavily tested. - * - * \hideinitializer - */ -#define UIP_REASSEMBLY 0 - -/** - * The maximum time an IP fragment should wait in the reassembly - * buffer before it is dropped. - * - */ -#define UIP_REASS_MAXAGE 40 - -/** @} */ - -/*------------------------------------------------------------------------------*/ -/** - * \defgroup uipoptudp UDP configuration options - * @{ - * - * \note The UDP support in uIP is still not entirely complete; there - * is no support for sending or receiving broadcast or multicast - * packets, but it works well enough to support a number of vital - * applications such as DNS queries, though - */ - -/** - * Toggles wether UDP support should be compiled in or not. - * - * \hideinitializer - */ -#define UIP_UDP 0 - -/** - * Toggles if UDP checksums should be used or not. - * - * \note Support for UDP checksums is currently not included in uIP, - * so this option has no function. - * - * \hideinitializer - */ -#define UIP_UDP_CHECKSUMS 0 - -/** - * The maximum amount of concurrent UDP connections. - * - * \hideinitializer - */ -#define UIP_UDP_CONNS 2 - -/** - * The name of the function that should be called when UDP datagrams arrive. - * - * \hideinitializer - */ -#define UIP_UDP_APPCALL udp_appcall - -/** @} */ -/*------------------------------------------------------------------------------*/ -/** - * \defgroup uipopttcp TCP configuration options - * @{ - */ - -/** - * Determines if support for opening connections from uIP should be - * compiled in. - * - * If the applications that are running on top of uIP for this project - * do not need to open outgoing TCP connections, this configration - * option can be turned off to reduce the code size of uIP. - * - * \hideinitializer - */ -#define UIP_ACTIVE_OPEN 1 - -/** - * The maximum number of simultaneously open TCP connections. - * - * Since the TCP connections are statically allocated, turning this - * configuration knob down results in less RAM used. Each TCP - * connection requires approximatly 30 bytes of memory. - * - * \hideinitializer - */ -#define UIP_CONNS 20 - -/** - * The maximum number of simultaneously listening TCP ports. - * - * Each listening TCP port requires 2 bytes of memory. - * - * \hideinitializer - */ -#define UIP_LISTENPORTS 10 - -/** - * The size of the advertised receiver's window. - * - * Should be set low (i.e., to the size of the uip_buf buffer) is the - * application is slow to process incoming data, or high (32768 bytes) - * if the application processes data quickly. - * - * \hideinitializer - */ -#define UIP_RECEIVE_WINDOW 32768 - -/** - * Determines if support for TCP urgent data notification should be - * compiled in. - * - * Urgent data (out-of-band data) is a rarely used TCP feature that - * very seldom would be required. - * - * \hideinitializer - */ -#define UIP_URGDATA 1 - -/** - * The initial retransmission timeout counted in timer pulses. - * - * This should not be changed. - */ -#define UIP_RTO 3 - -/** - * The maximum number of times a segment should be retransmitted - * before the connection should be aborted. - * - * This should not be changed. - */ -#define UIP_MAXRTX 8 - -/** - * The maximum number of times a SYN segment should be retransmitted - * before a connection request should be deemed to have been - * unsuccessful. - * - * This should not need to be changed. - */ -#define UIP_MAXSYNRTX 3 - -/** - * The TCP maximum segment size. - * - * This is should not be to set to more than UIP_BUFSIZE - UIP_LLH_LEN - 40. - */ -#define UIP_TCP_MSS (UIP_BUFSIZE - UIP_LLH_LEN - 40) - -/** - * How long a connection should stay in the TIME_WAIT state. - * - * This configiration option has no real implication, and it should be - * left untouched. - */ -#define UIP_TIME_WAIT_TIMEOUT 120 - - -/** @} */ -/*------------------------------------------------------------------------------*/ -/** - * \defgroup uipoptarp ARP configuration options - * @{ - */ - -/** - * The size of the ARP table. - * - * This option should be set to a larger value if this uIP node will - * have many connections from the local network. - * - * \hideinitializer - */ -#define UIP_ARPTAB_SIZE 8 - -/** - * The maxium age of ARP table entries measured in 10ths of seconds. - * - * An UIP_ARP_MAXAGE of 120 corresponds to 20 minutes (BSD - * default). - */ -#define UIP_ARP_MAXAGE 120 - -/** @} */ - -/*------------------------------------------------------------------------------*/ - -/** - * \defgroup uipoptgeneral General configuration options - * @{ - */ - -/** - * The size of the uIP packet buffer. - * - * The uIP packet buffer should not be smaller than 60 bytes, and does - * not need to be larger than 1500 bytes. Lower size results in lower - * TCP throughput, larger size results in higher TCP throughput. - * - * \hideinitializer - */ -#define UIP_BUFSIZE 2048 - - -/** - * Determines if statistics support should be compiled in. - * - * The statistics is useful for debugging and to show the user. - * - * \hideinitializer - */ -#define UIP_STATISTICS 1 - -/** - * Determines if logging of certain events should be compiled in. - * - * This is useful mostly for debugging. The function uip_log() - * must be implemented to suit the architecture of the project, if - * logging is turned on. - * - * \hideinitializer - */ -#define UIP_LOGGING 0 - -/** - * Print out a uIP log message. - * - * This function must be implemented by the module that uses uIP, and - * is called by uIP whenever a log message is generated. - */ -void uip_log(char *msg); - -/** - * The link level header length. - * - * This is the offset into the uip_buf where the IP header can be - * found. For Ethernet, this should be set to 14. For SLIP, this - * should be set to 0. - * - * \hideinitializer - */ -#define UIP_LLH_LEN 14 - - -/** @} */ -/*------------------------------------------------------------------------------*/ -/** - * \defgroup uipoptcpu CPU architecture configuration - * @{ - * - * The CPU architecture configuration is where the endianess of the - * CPU on which uIP is to be run is specified. Most CPUs today are - * little endian, and the most notable exception are the Motorolas - * which are big endian. The BYTE_ORDER macro should be changed to - * reflect the CPU architecture on which uIP is to be run. - */ -#ifndef LITTLE_ENDIAN -#define LITTLE_ENDIAN 3412 -#endif /* LITTLE_ENDIAN */ -#ifndef BIG_ENDIAN -#define BIG_ENDIAN 1234 -#endif /* BIGE_ENDIAN */ - -/** - * The byte order of the CPU architecture on which uIP is to be run. - * - * This option can be either BIG_ENDIAN (Motorola byte order) or - * LITTLE_ENDIAN (Intel byte order). - * - * \hideinitializer - */ -#ifndef BYTE_ORDER -#define BYTE_ORDER LITTLE_ENDIAN -#endif /* BYTE_ORDER */ - -/** @} */ -/*------------------------------------------------------------------------------*/ - -/** - * \defgroup uipoptapp Appication specific configurations - * @{ - * - * An uIP application is implemented using a single application - * function that is called by uIP whenever a TCP/IP event occurs. The - * name of this function must be registered with uIP at compile time - * using the UIP_APPCALL definition. - * - * uIP applications can store the application state within the - * uip_conn structure by specifying the size of the application - * structure with the UIP_APPSTATE_SIZE macro. - * - * The file containing the definitions must be included in the - * uipopt.h file. - * - * The following example illustrates how this can look. - \code - -void httpd_appcall(void); -#define UIP_APPCALL httpd_appcall - -struct httpd_state { - u8_t state; - u16_t count; - char *dataptr; - char *script; -}; -#define UIP_APPSTATE_SIZE (sizeof(struct httpd_state)) - \endcode - */ - -/** - * \var #define UIP_APPCALL - * - * The name of the application function that uIP should call in - * response to TCP/IP events. - * - */ - -/** - * \var #define UIP_APPSTATE_SIZE - * - * The size of the application state that is to be stored in the - * uip_conn structure. - */ -/** @} */ - -/* Include the header file for the application program that should be - used. If you don't use the example web server, you should change - this. */ -#include "httpd.h" - - -#endif /* __UIPOPT_H__ */ diff --git a/GitHub-FreeRTOS-Kernel-Home.url b/GitHub-FreeRTOS-Kernel-Home.url new file mode 100644 index 000000000..87d25ce02 --- /dev/null +++ b/GitHub-FreeRTOS-Kernel-Home.url @@ -0,0 +1,7 @@ +[{000214A0-0000-0000-C000-000000000046}] +Prop3=19,2 +[InternetShortcut] +URL=https://github.com/FreeRTOS/FreeRTOS-Kernel +IconIndex=0 +IDList= +HotKey=0 diff --git a/History.txt b/History.txt new file mode 100644 index 000000000..7df76e16f --- /dev/null +++ b/History.txt @@ -0,0 +1,3494 @@ +Documentation and download available at https://www.FreeRTOS.org/ + +Changes between FreeRTOS V11.1.0 and FreeRTOS V11.2.0 released March 04, 2025 + + + Add CC-RH port for Renesas F1Kx devices. We thank @TrongNguyenR for their + contribution. + + Add Pointer Authentication (PAC) and Branch Target Identification (BTI) + support to the ARMv8-M ports. We thank @AhmedIsmail02 for their + contribution. + + Add Floating Point Unit (FPU) support to the ARM_AARCH64 port. We thank + @StefanBalt for their contribution. + + Add FPU Safe Application IRQ Handler suport to the ARM_AARCH64_SRE port. + We thank @GhMarwen for their contribution. + + Add Privileged eXecute Never MPU attribute support to the ARMv8-M ports. + We thank @AhmedIsmail02 for their contribution. + + Update XMOS xcore.ai port to be compatible with FreeRTOS Kernel version + 11. We thank @ACascarino for their contribution. + + ARM_CRx_No_GIC port updates: + - Remove inline assembly and move assembly code to separate portASM.S + file. + - Add support for Floating Point Unit (FPU). + - Add support to allow the application writer to handle SVC calls raised + from the application code. + - Add support for vApplicationFPUSafeIRQHandler. + + POSIX port updates: + - Set PTHREAD_MUTEX_ROBUST attribute on the mutex to prevent application + hangs when a thread dies while holding a mutex. + - Avoid calling pthread_sigmask on non-FreeROS threads when + vPortEndScheduler is called from a non-FreeRTOS thread. We thank + @johnboiles for their contribution. + - Remove unnecessary call to pthread_attr_setstacksize. We thank + @hollinsky for their contribution. + - Add an assert to catch if vPortYield is called from a non-FreeRTOS + thread. We thank @johnboiles for their contribution. + - Fix Posix port compilation on FreeBSD. We thank @tymmej for their + contribution. + + Update the Xtensa port and move it to the Partner-Supported-Ports + repository. We thank @ianstcdns for their contribution. + + Add vPortGenerateSimulatedInterruptFromWindowsThread API in the MSVC-MingW + port to enable native windows thread to synchronize with FreeRTOS task + through simulated interrupt. + + Update Windows port to use Waitable Timer instead of Sleep to improve tick + accuracy. We thank @bknicholls and @leegeth for their contribution. + + Update the value of queueQUEUE_TYPE_SET to a unique value (5) to allow + tracers to differentiate between queues and queue sets. We thank @schilkp + for their contribution. + + Add traceSTARTING_SCHEDULER tracing hook to enable tracers to run code on + startup. We thank @schilkp for their contribution. + + Define vApplicationGetTimerTaskMemory only when configUSE_TIMERS is set to + 1. We thank @HazardyKnusperkeks for their contribution. + + Reset xNextTaskUnblockTime in task notify FromISR APIs to allow the core + to enter sleep mode at the earliest possible time when using tickless + idle. + + Optimize xTaskIncrementTick for SMP by removing xYieldRequiredForCore. We + thank @cymizer for their contribution. + + Update the SMP scheduler to re-select a core to yield when the core + affinity of a ready task is changed. + + Update xEventGroupSetBits to read the event bits value to be returned to + the caller while the scheduler is suspended. This fixes dereference after + the event group is deleted by higher priority task. We thank @skotopes for + their contribution. + + Optimize certain getter APIs by removing unnecessary calls to + task{ENTER|EXIT}_CRITICAL() when the data access is atomic. We thank + @GuilhermeGiacomoSimoes for their contribution. + + Optimize xTaskNotifyWait and ulTaskNotifyTake APIs to suspend the + scheduler only if the task is not already notified, and the caller is + willing to wait for the notification. We thank @jefftenney for + their contribution. + + Fix error checking of prvCreateIdleTasks. We thank @kakkoko for their + contribution. + + Update SMP lock macros and critical nesting macros to pass core ID as an + argument. This reduces the number of accesses to a peripheral register to + query core ID. We thank @felixvanoost for their contribution. + + Add stack pointer bounds check when configCHECK_FOR_STACK_OVERFLOW is set + to 2 to improve reliability of stack overflow detection. We thank + @jiladahe1997 for their contribution. + + Update run-time stats to include time elapsed since the last context + switch for the currently running task. + + Add xQueueCreateSetStatic API for static creation of Queue Sets. We thank + @kzorer for their contribution. + + Update the traceMALLOC() macro to pass the actual size of the allocated + block for secure_heap, heap_2, heap_4 and heap_5. We thank @DazzlingOkami + for their contribution. + + Update heap_1 to use heapADD_WILL_OVERFLOW macro to improve readability. + We thank @wdfk-prog for their contribution. + + Add pointer protection to the pxNextFreeBlock member of the allocated + block's metadata in heap_4 and heap_5 when configENABLE_HEAP_PROTECTOR is + set to 1. We thank @Saiiijchan for their contribution. + + Allow the application writer to override pointer validation for heap_5 + when configENABLE_HEAP_PROTECTOR is used. We thank @Saiiijchan for their + contribution. + + Add xPortResetHeapMinimumEverFreeHeapSize to heap_4.c and heap_5.c. + We thank @TomasGalbickaNXP for their contribution. + + Add NULL check in the event_create function in the POSIX port. We thank + @laroche for their contribution. + + Use _GNU_SOURCE macro instead of __USE_GNU in the Posix port. We thank + @maxiaogood for their contribution. + + Use the new __ARM_FP macro instead of the deprectred __VFP_FP__ macro in + GCC/ARM_CM7, GCC/ARM_CM4_MPU, and GCC/ARM_CM4F ports. We thank @haydenridd + for their contribution. + + Add portMEMORY_BARRIER definition to the Xtensa port. We thank @superroc + for their contribution. + + Move the hardware include msp430.h to port.c from portmacro.h. We thank + @mayl for their contribution. + + Update ARM assembly syntax for Cortex-M ports. We thank @laroche for their + contribution. + + Update the Windows port to records a pending yield in + vPortCloseRunningThread to ensure that the next tick interrupt schedules + the next task regardless of the value of configUSE_PREEMPTION. + + Fix the context switch issue in the RL78 port. We thank @KeitaKashima for + their contribution. + + Fix compilation issue in ARM CM0 port when using Keil MDK. We thank + @TomasGalbickaNXP for their contribution. + + Fix IA32 port compilation when configUSE_COMMON_INTERRUPT_ENTRY_POINT is + set to 0. We thank @Ryzee119 for their contribution. + + Store configMTIMECMP_BASE_ADDRESS in a 64-bit integer for the RISC-V port. + We thank @vishwamartur for their contribution. + + Fix nested interrupt handling and optimize FPU related context switching + for the F1Kx port. We thank @TrongNguyenR for their contribution. + + Update the RP2040 port to add support for Raspberry Pi Pico SDK 2.0.0. + We thank @kilograham for their contribution. + + Fix the return value of portYIELD_FROM_ISR macro for the MSVC-MingW port. + We thank @wwhheerree for their contribution. + + Optimize vApplicationFPUSafeIRQHandler for the Coretex-A9 port by + removing the unnecessarily preserved callee saved registers. We thank + @Saiiijchan for their contribution. + + Fix the context array size for MPU ports to ensure the saved context + location falls within the reserved context area rather than overlapping + with the next MPU_SETTINGS structure member. + + Update CMake files for RP2040 port to fetch the port from the + Community-Supported-Ports repo. We thank @kilograham for their + contribution. + + Fix CMake file for the GCC ARM_CM0 port to include MPU files. We thank + @0mhu for their contribution. + + Add an example of human readable table generated by vTaskListTasks() in + the function documentation. We thank @wwhheerree for their contribution. + +Changes between FreeRTOS V11.0.1 and FreeRTOS V11.1.0 released April 22, 2024 + + + Add ARMv7-R port with Memory Protection Unit (MPU) support. + + Add Memory Protection Unit (MPU) support to the Cortex-M0 port. + + Add stream batching buffer. A stream batching buffer differs from a stream + buffer when a task reads from a non-empty buffer: + - The task reading from a non-empty stream buffer returns immediately + regardless of the amount of data in the buffer. + - The task reading from a non-empty steam batching buffer blocks until the + amount of data in the buffer exceeds the trigger level or the block time + expires. + We thank @cperkulator for their contribution. + + Add the ability to change task notification index for stream buffers. We + thank @glemco for their contribution. + + Add xStreamBufferResetFromISR and xMessageBufferResetFromISR APIs to reset + stream buffer and message buffer from an Interrupt Service Routine (ISR). + We thank @HagaiMoshe for their contribution. + + Update all the FreeRTOS APIs to use configSTACK_DEPTH_TYPE for stack type. + We thank @feilipu for their contribution. + + Update vTaskEndScheduler to delete the timer and idle tasks, + once the scheduler is stopped. + + Make xTaskGetCurrentTaskHandleForCore() available to the single core + scheduler. We thank @Dazza0 for their contribution. + + Update uxTaskGetSystemState to not use the pxIndex member of the List_t + structure while iterating ready tasks list. The reason is that pxIndex + member must only used to select next ready task to run. We thank + @gemarcano for their inputs. + + Add a config option to the FreeRTOS SMP Kernel to set the default core + affinity mask for tasks created without an affinity mask. We thank @go2sh + for their contribution. + + Add configUSE_EVENT_GROUPS and configUSE_STREAM_BUFFERS configuration + constants to control the inclusion of event group and stream buffer + functionalities. + + Code changes to comply with MISRA C 2012. + + Add 64-bit support to the FreeRTOS Windows Simulator port. We thank @watsk + and @josesimoes for their contributions. + + Add support for 64-bit Microblaze processor to the MicroblazeV9 port. We + thank @mubinsyed for their contribution. + + Add support for MSP430 Embedded Application Binary Interface (EABI) to + the MSP430F449 port to make it work with both MSP430 GCC and MSPGCC + compilers. We thank @Forty-Bot for their contribution. + + Update xPortIsAuthorizedToAccessBuffer() on FreeRTOS ports with MPU + support to grant an unprivileged task access to all the memory before the + scheduler is started. + + Update the POSIX port to pass the FreeRTOS task name to pthread for + readable output in debuggers. We thank @Mixaill for their contribution. + + Update the POSIX port to ignore the user specified stack memory and only + pass the stack size to the pthread API to avoid errors caused when stack size + is smaller than the minimum. We thank @cmorgnaBE for their + contribution. + + Update the POSIX port to use a timer thread for tick interrupts instead of + POSIX timers to address issues with signal handling in non-FreeRTOS + pthreads. We thank @cmorgnaBE for their contribution. + + Update ARM_TFM port to support TF-Mv2.0.0 release of trusted-firmware-m. + We thanks @urutva for their contribution. + + Remove redundant constant pools in ARMv8 ports. We thank @urutva for their + contribution. + + Add APIs to reset the internal state of kernel modules. These APIs are + primarily intended to be used in the testing frameworks that restart the + scheduler. + + Use kernel provided implementations of vApplicationGetIdleTaskMemory() and + vApplicationGetTimerTaskMemory() in the RP2040 port. We thank @dpslwk for + their contribution. + + Fix atomic enter/exit critical section macro definitions in atomic.h for + ports that support nested interrupts. We thank @sebunger for their + contribution. + + Fix compiler warnings in the MSP430F449 port when compiled with the + MSP430 GCC compiler. We thank @Forty-Bot for their contribution. + + Update the scheduler suspension usage in ulTaskGenericNotifyTake and + xTaskGenericNotifyWait() to enhance code readability. We thank @Dazza0 for + their contribution. + + Add support for latest version of MPU wrappers( mpu_wrappers_v2) in CMake. + We thank @IsaacDynamo for their contribution. + + Update CMake support to create only one static library containing both the + kernel common code and the kernel port code. We thank @barnatahmed for + their contribution. + +Changes between FreeRTOS V11.0.0 and FreeRTOS V11.0.1 released December 21, 2023 + + + Updated the SBOM file. + +Changes between FreeRTOS V10.6.2 and FreeRTOS V11.0.0 released December 18, 2023 + + + SMP merged into the mainline: While FreeRTOS introduced Asymmetric + Multiprocessing (AMP) support in 2017, FreeRTOS Version 11.0.0 is the + first to merge Symmetric Multiprocessing (SMP) support into the mainline + release. SMP enables one instance of the FreeRTOS Kernel to schedule tasks + across multiple identical processor cores. We thank Mike Bruno and Jerry + McCarthy of XMOS and, Darian Liang, Sudeep Mohanty and Zim Kalinowski of + Espressif Systems for their contributions. + + Switch MISRA compliance checking from PC Lint to Coverity, and update from + MISRA C:2004 to MISRA C:2012. + + Add a template FreeRTOSConfig.h, inclusive of an abbreviated explanation of + each configuration item. Application writers can use this template as a + starting point to create the FreeRTOSConfig.h file for their application. + + Add a template FreeRTOS port which can be used as a starting point for + developing a new FreeRTOS port. + + Add bounds checking and obfuscation to internal heap block pointers in + heap_4.c and heap_5.c to help catch pointer corruptions. The application can + enable these checks by setting configENABLE_HEAP_PROTECTOR to 1 in their + FreeRTOSConfig.h. We thank @oliverlavery for their contribution. + + Update vTaskList and vTaskGetRunTimeStats APIs to replace the use of sprintf + with snprintf. + + Add trace macros to ports that enable tracing the interaction of ISRs with + scheduler events. We thank @conara for their contribution. + + Add trace macros that enable tracing of entering and exiting all APIs. We + thank @Techcore123 for their contribution. + + Add uxTaskBasePriorityGet and uxTaskBasePriorityGetFromISR APIs to get the + base priority of a task. The base priority of a task is the priority that + was last assigned to the task - which due to priority inheritance, may not + be the current priority of the task. + + Add pdTICKS_TO_MS macro to convert time in FreeRTOS ticks to time in + milliseconds. We thank @Dazza0 for their contribution. + + Add default implementations of vApplicationGetIdleTaskMemory and + vApplicationGetTimerTaskMemory. The application can enable these default + implementations by setting configKERNEL_PROVIDED_STATIC_MEMORY to 1 in their + FreeRTOSConfig.h. We thank @mdnr-g for their contribution. + + Update vTaskGetInfo to include start and end of the stack whenever both + values are available. We thank @vinceburns for their contribution. + + Prevent tasks waiting for a notification from being resumed by calls to + vTaskResume or vTaskResumeFromISR. We thank @Moral-Hao for their + contribution. + + Add asserts to validate that the application has correctly installed + FreeRTOS handlers for PendSV and SVCall interrupts on Cortex-M devices. + We thank @jefftenney for their contribution. + + Rename ARM_CA53_64_BIT and ARM_CA53_64_BIT_SRE ports to Arm_AARCH64 and + Arm_AARCH64_SRE respectively as these ports are applicable to all AArch64 + architecture. We thank @urutva for their contribution. + + Add CMake support to allow the application writer to select the RISC-V + chip extension. We thank @JoeBenczarski for their contribution. + + Add CMake support to allow the application writer to build an application + with static allocation only. We thank @conara for their contribution. + + Make taskYIELD available to unprivileged tasks for ARMv8-M ports. + + Update Cortex-M23 ports to not use PSPLIM_NS. We thank @urutva for their + contribution. + + Update the SysTick setup code for ARMv8-M ports to first configure the clock + source and then enable SysTick. This is needed to address a bug in QEMU + versions older than 7.0.0, which causes an emulation error if SysTick is + enabled without first selecting a valid clock source. We thank @jefftenney + for their contribution. + + Add the port-optimized task selection algorithm optionally available for + ARMv7-M ports to the ARMv8-M ports. We thank @jefftenney for their + contribution. + + Improve the speed of pvPortMalloc in heap_4.c and heap_5.c by removing + unnecessary steps while splitting a large memory block into two. We thank + @Moral-Hao for their contribution. + + Shorten the critical section in pvPortMalloc in heap_2.c, heap_4.c and + heap_5.c by moving the size calculation out of the critical section. We thank + @Moral-Hao for their contribution. + + Update xTaskNotifyWait and ulTaskNotifyTake to remove the non-deterministic + operation of traversing a linked link from a critical section. We thank + @karver8 for their contribution. + + Fix stack end and stack size computation in POSIX port to meet the stack + alignment requirements on MacOS. We thank @tegimeki for their contribution. + + Update the vTaskPrioritySet implementation to use the new priority when the + task has inherited priority from a mutex it is holding, and the new priority + is bigger than the inherited priority. We thank @Moral-Hao for their + contribution. + + Add stack alignment adjustment if stack grows upwards. We thank @ivq for + their contribution. + + Fix pxTopOfStack calculation in configINIT_TLS_BLOCK when picolib C is + selected as the C library implementation to ensure that + pxPortInitialiseStack does not overwrite the data in the TLS block portion + of the stack. We thank @bebebib-rs for their contribution. + + Fix vPortEndScheduler() for the MSVC port so that the function + prvProcessSimulatedInterrupts is not stuck in an infinite loop when the + scheduler is stopped. We thank @Ju1He1 for their contribution. + + Add the Pull Request (PR) Process explaining the stages a PR goes through. + +Changes between FreeRTOS V10.6.1 and FreeRTOS V10.6.2 released November 29, 2023 + + + Add the following improvements to the new MPU wrapper (mpu_wrappers_v2.c) + introduced in version 10.6.0: + - Introduce Access Control List (ACL) feature to allow the application + writer to control an unprivileged task’s access to kernel objects. + - Update the system call entry mechanism to only require one Supervisor + Call (SVC) instruction. + - Wrap parameters for system calls with more than four parameters in a + struct to avoid special handling during system call entry. + - Fix 2 possible integer overflows. + - Convert some asserts to run time parameter checks. + +Changes between FreeRTOS V10.6.0 and FreeRTOS V10.6.1 released August 17, 2023 + + + Add runtime parameter checks to functions in mpu_wrappers_v2.c file. + The same checks are already performed in API implementations using + asserts. + We thank the following people for their inputs in these changes: + - Lan Luo, Zixia Liu of School of Computer Science and Technology, + Anhui University of Technology, China. + - Xinwen Fu of Department of Computer Science, University of + Massachusetts Lowell, USA. + - Xinhui Shao, Yumeng Wei, Huaiyu Yan, Zhen Ling of School of + Computer Science and Engineering, Southeast University, China. + +Changes between FreeRTOS V10.5.1 and FreeRTOS 10.6.0 released July 13, 2023 + + + Add a new MPU wrapper that places additional restrictions on unprivileged + tasks. The following is the list of changes introduced with the new MPU + wrapper: + + 1. Opaque and indirectly verifiable integers for kernel object handles: + All the kernel object handles (for example, queue handles) are now + opaque integers. Previously object handles were raw pointers. + 2. Save the task context in Task Control Block (TCB): When a task is + swapped out by the scheduler, the task's context is now saved in its + TCB. Previously the task's context was saved on its stack. + 3. Execute system calls on a separate privileged only stack: FreeRTOS + system calls, which execute with elevated privilege, now use a + separate privileged only stack. Previously system calls used the + calling task's stack. The application writer can control the size of + the system call stack using new configSYSTEM_CALL_STACK_SIZE config + macro. + 4. Memory bounds checks: FreeRTOS system calls which accept a pointer + and de-reference it, now verify that the calling task has required + permissions to access the memory location referenced by the pointer. + 5. System calls restrictions: The following system calls are no longer + available to unprivileged tasks: + - vQueueDelete + - xQueueCreateMutex + - xQueueCreateMutexStatic + - xQueueCreateCountingSemaphore + - xQueueCreateCountingSemaphoreStatic + - xQueueGenericCreate + - xQueueGenericCreateStatic + - xQueueCreateSet + - xQueueRemoveFromSet + - xQueueGenericReset + - xTaskCreate + - xTaskCreateStatic + - vTaskDelete + - vTaskPrioritySet + - vTaskSuspendAll + - xTaskResumeAll + - xTaskGetHandle + - xTaskCallApplicationTaskHook + - vTaskList + - vTaskGetRunTimeStats + - xTaskCatchUpTicks + - xEventGroupCreate + - xEventGroupCreateStatic + - vEventGroupDelete + - xStreamBufferGenericCreate + - xStreamBufferGenericCreateStatic + - vStreamBufferDelete + - xStreamBufferReset + Also, an unprivileged task can no longer use vTaskSuspend to suspend + any task other than itself. + + We thank the following people for their inputs in these enhancements: + - David Reiss of Meta Platforms, Inc. + - Lan Luo, Xinhui Shao, Yumeng Wei, Zixia Liu, Huaiyu Yan and Zhen Ling + of School of Computer Science and Engineering, Southeast University, + China. + - Xinwen Fu of Department of Computer Science, University of + Massachusetts Lowell, USA. + - Yueqi Chen, Zicheng Wang, Minghao Lin, Jiahe Wang of University of + Colorado Boulder, USA. + + Add Cortex-M35P port. Contributed by @urutva. + + Add embedded extension (RV32E) support to the IAR RISC-V port. + + Add ulTaskGetRunTimeCounter and ulTaskGetRunTimePercent APIs. Contributed by + @chrisnc. + + Add APIs to get the application supplied buffers from statically + created kernel objects. The following new APIs are added: + - xTaskGetStaticBuffers + - xQueueGetStaticBuffers + - xQueueGenericGetStaticBuffers + - xSemaphoreGetStaticBuffer + - xEventGroupGetStaticBuffer + - xStreamBufferGetStaticBuffers + - xMessageBufferGetStaticBuffers + These APIs enable the application writer to obtain static buffers from + the kernel object and free/reuse them at the time of deletion. Earlier + the application writer had to maintain the association of static buffers + and the kernel object in the application. Contributed by @Dazza0. + + Add Thread Local Storage (TLS) support using picolibc function. Contributed + by @keith-packard. + + Add configTICK_TYPE_WIDTH_IN_BITS to configure TickType_t data type. As a result, + the number of bits in an event group also increases with big data type. Contributed + by @Hadatko. + + Update eTaskGetState and uxTaskGetSystemState to return eReady for pending ready + tasks. Contributed by @Dazza0. + + Update heap_4 and heap_5 to add padding only if the resulting block is not + already aligned. + + Fix the scheduler logic in a couple of places to not preempt a task when an + equal priority task becomes ready. + + Add macros used in FreeRTOS-Plus libraries. Contributed by @Holden. + + Fix clang compiler warnings. Contributed by @phelter. + + Add assertions to ARMv8-M ports to detect when FreeRTOS APIs are called from + interrupts with priority higher than the configMAX_SYSCALL_INTERRUPT_PRIORITY. + Contributed by @urutva. + + Add xPortIsInsideInterrupt API to ARM_CM0 ports. + + Fix build warning in MSP430X port when large data model is used. + + Add the ability to use Cortex-R5 port on the parts without FPU. + + Fix build warning in heap implementations on PIC24/dsPIC. + + Update interrupt priority asserts for Cortex-M ports so that these do not fire + on QEMU which does not implement PRIO bits. + + Update ARMv7-M ports to ensure that kernel interrupts run at the lowest priority. + configKERNEL_INTERRUPT_PRIORITY is now obsolete for ARMv7-M ports and brings + these ports inline with the newer ARMv8-M ports. Contributed by @chrisnc. + + Fix build issue in POSIX GCC port on Windows Subsystem for Linux (WSL). Contributed + by @jacky309. + + Add portMEMORY_BARRIER to Microblaze port. Contributed by @bbain. + + Add portPOINTER_SIZE_TYPE definition for ATmega port. Contributed by @jputcu. + + Multiple improvements in the CMake support. Contributed by @phelte and @cookpate. + +Changes between FreeRTOS V10.5.0 and FreeRTOS V10.5.1 released November 16 2022 + + Updated the kernel version in manifest and SBOM + +Changes between FreeRTOS V10.4.6 and FreeRTOS V10.5.0 released September 16 2022 + + + ARMv7-M and ARMv8-M MPU ports: It was possible for a third party that + already independently gained the ability to execute injected code to + read from or write to arbitrary addresses by passing a negative argument + as the xIndex parameter to pvTaskGetThreadLocalStoragePointer() or + vTaskSetThreadLocalStoragePointer respectively. A check has been added to + ensure that passing a negative argument as the xIndex parameter does not + cause arbitrary read or write. + We thank Certibit Consulting, LLC for reporting this issue. + + ARMv7-M and ARMv8-M MPU ports: It was possible for an unprivileged task + to invoke any function with privilege by passing it as a parameter to + MPU_xTaskCreate, MPU_xTaskCreateStatic, MPU_xTimerCreate, + MPU_xTimerCreateStatic, or MPU_xTimerPendFunctionCall. MPU_xTaskCreate + and MPU_xTaskCreateStatic have been updated to only allow creation of + unprivileged tasks. MPU_xTimerCreate, MPU_xTimerCreateStatic and + MPU_xTimerPendFunctionCall APIs have been removed. + We thank Huazhong University of Science and Technology for reporting + this issue. + + ARMv7-M and ARMv8-M MPU ports: It was possible for a third party that + already independently gained the ability to execute injected code to + achieve further privilege escalation by branching directly inside a + FreeRTOS MPU API wrapper function with a manually crafted stack frame. + The local stack variable `xRunningPrivileged` has been removed so that + a manually crafted stack frame cannot be used for privilege escalation + by branching directly inside a FreeRTOS MPU API wrapper. + We thank Certibit Consulting, LLC, Huazhong University of Science and + Technology and the SecLab team at Northeastern University for reporting + this issue. + + ARMv7-M MPU ports: It was possible to configure overlapping memory + protection unit (MPU) regions such that an unprivileged task could access + privileged data. The kernel now uses highest numbered MPU regions for + kernel protections to prevent such MPU configurations. + We thank the SecLab team at Northeastern University for reporting this + issue. + + Add support for ARM Cortex-M55. + + Add support for ARM Cortex-M85. Contributed by @gbrtth. + + Add vectored mode interrupt support to the RISC-V port. + + Add support for RV32E extension (Embedded Profile) in RISC-V GCC port. + Contributed by @Limoto. + + Heap improvements: + - Add a check to heap_2 to track if a memory block is allocated to + the application or not. The MSB of the size field is used for this + purpose. The same check already exists in heap_4 and heap_5. This + check prevents double free errors. + - Add a new flag configHEAP_CLEAR_MEMORY_ON_FREE to heap_2, heap_4 + and heap_5. If the flag is set in FreeRTOSConfig.h then memory freed using + vPortFree() is automatically cleared to zero. + - Add a new API pvPortCalloc to heap_2, heap_4 and heap_5 which has the same + signature as the standard library calloc function. + - Update the pointer types to portPOINTER_SIZE_TYPE. Contributed by + @Octaviarius. + + Add the ability to override send and receive completed callbacks for each + instance of a stream buffer or message buffer. Earlier there could be + one send and one receive callback for all instances of stream and message + buffers. Having separate callbacks per instance allows different message + and stream buffers to be used differently - for example, some for inter core + communication and others for same core communication. + The feature can be controlled by setting the configuration option + configUSE_SB_COMPLETED_CALLBACK in FreeRTOSConfig.h. When the option is set to 1, + APIs xStreamBufferCreateWithCallback() or xStreamBufferCreateStaticWithCallback() + (and likewise APIs for message buffer) can be used to create a stream buffer + or message buffer instance with application provided callback overrides. When + the option is set to 0, then the default callbacks as defined by + sbSEND_COMPLETED() and sbRECEIVE_COMPLETED() macros are invoked. To maintain + backwards compatibility, configUSE_SB_COMPLETED_CALLBACK defaults to 0. The + functionality is currently not supported for MPU enabled ports. + + Generalize the FreeRTOS's Thread Local Storage (TLS) support so that it + is not tied to newlib and can be used with other c-runtime libraries also. + The default behavior for newlib support is kept same for backward + compatibility. + + Add support to build and link FreeRTOS using CMake build system. Contributed + by @yhsb2k. + + Add support to generate Software Bill of Materials (SBOM) for every release. + + Add support for 16 MPU regions to the GCC Cortex-M33 ports. + + Add ARM Cortex-M7 r0p0/r0p1 Errata 837070 workaround to ARM CM4 MPU ports. + The application writer needs to define configENABLE_ERRATA_837070_WORKAROUND + when using CM4 MPU ports on a Cortex-M7 r0p0/r0p1 core. + + Add configSYSTICK_CLOCK_HZ to Cortex-M0 ports. This is needed to support + the case when the SysTick timer is not clocked from the same source as the CPU. + + Add hardware stack protection support to MicroBlazeV9 port. This ensures that + the CPU immediately raises Stack Protection Violation exception as soon as any + task violates its stack limits. Contributed by @uecasm. + + Introduce the configUSE_MINI_LIST_ITEM configuration option. When this + option is set to 1, ListItem_t and MiniLitItem_t remain separate types. + However, when configUSE_MINI_LIST_ITEM == 0, MiniLitItem_t and ListItem_t + are both typedefs of the same struct xLIST_ITEM. This addresses some issues + observed when strict-aliasing and link time optimization are enabled. + To maintain backwards compatibility, configUSE_MINI_LIST_ITEM defaults to 1. + + Simplify prvInitialiseNewTask to memset newly allocated TCB structures + to zero, and remove code that set individual structure members to zero. + + Add prototype for prvPortYieldFromISR to the POSIX port so that it builds + without any warning with -Wmissing-prototypes compiler option. + + Add top of stack and end of stack to the task info report obtained using + vTaskGetInfo(). Contributed by @shreyasbharath. + + Add a cap to the cRxLock and cTxLock members of the queue data structure. + These locks count the number items received and sent to the queue while + the queue was locked. These are later used to unblock tasks waiting on + the queue when the queue is unlocked. This PR caps the values of the + cRxLock and cTxLock to the number of tasks in the system because we cannot + unblock more tasks than there are in the system. Note that the same assert + could still be triggered is the application creates more than 127 tasks. + + Changed uxAutoReload parameter in timer functions to xAutoReload. The + type is now BaseType_t. This matches the type of pdTRUE and pdFALSE. + The new function xTimerGetAutoReload() provides the auto-reload state as + a BaseType_t. The legacy function uxTimerGetAutoReload is retained with the + original UBaseType_t return value. + + Fix support for user implementations of tickless idle that call + vTaskStepTick() with xExpectedIdleTime ticks to step. The new code + ensures xTickCount reaches xNextTaskUnblockTime inside xTaskIncrementTick() + instead of inside vTaskStepTick(). This fixes the typical case where a task + wakes up one tick late and a rare case assertion failure when xTickCount\ + rolls over. Contributed by @jefftenney. + + Fix deadlock in event groups when pvPortMalloc and vPortFree functions + are protected with a mutex. Contributed by @clemenskresser. + + Fix a warning in tasks.c when compiled with -Wduplicated-branches + GCC option. Contributed by @pierrenoel-bouteville-act. + + Fix compilation error in tasks.c when configSUPPORT_DYNAMIC_ALLOCATION + is set to zero. Contributed by @rdpoor. + + Fix prvWriteMessageToBuffer() function in stream_buffer.c so that it correctly + copies length on big endian platforms too. + + Remove the need for INCLUDE_vTaskSuspend to be set to 1 + when configUSE_TICKLESS_IDLE is enabled. Contributed by @pramithkv. + + Update the RL78 IAR port to the latest version of IAR which uses the + industry standard ELF format as opposed to earlier UBROF object format. + Contributed by @felipe-iar. + + Add tick type is atomic flag when tick count is 16-bit to PIC24 port. This + allows the PIC24 family of 16 bit processors to read the tick count without + a critical section when the tick count is also 16 bits. + + Fix offset-out-of-range errors for GCC CM3/CM4 mpu ports when + Link Time Optimization is enabled. Contributed by @niniemann. + + Remove #error when RISC-V port is compiled on a 64-bit RISC-V platform. + Contributed by @cmdrf. + + Fix ullPortInterruptNesting alignment in Cortex-A53 port so that it is + 8-byte aligned. This fixes the unaligned access exception. Contributed + by @Atomar25. + + Fix Interrupt Handler Register Function and Exception Process in NiosII + Port. Contributed by @ghost. + + Change FreeRTOS IRQ Handler for Cortex-A53 SRE port to store and restore + interrupt acknowledge register. This ensures that the SRE port behavior + matches the Memory Mapped IO port. Contributed by @sviaunxp. + + Update the uncrustify config file to match the version of the uncrustify + used in the CI Action. Also, pin the version of uncrustify in CI. Contributed + by @swaldhoer. + +Changes between FreeRTOS V10.4.5 and FreeRTOS V10.4.6 released November 12 2021 + + + ARMv7-M and ARMv8-M MPU ports – prevent non-kernel code from calling the + internal functions xPortRaisePrivilege and vPortResetPrivilege by changing + them to macros. + + Introduce a new config configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS which + enables developers to prevent critical sections from unprivileged tasks. + It defaults to 1 for backward compatibility. Application should set it to + 0 to disable critical sections from unprivileged tasks. + +Changes between FreeRTOS V10.4.4 and FreeRTOS V10.4.5 released September 10 2021 + + See https://www.FreeRTOS.org/FreeRTOS-V10.4.5.html + + + Introduce configRUN_TIME_COUNTER_TYPE which enables developers to define + the type used to hold run time statistic counters. Defaults to uint32_t + for backward compatibility. #define configRUN_TIME_COUNTER_TYPE to a type + (for example, uint64_t) in FreeRTOSConfig.h to override the default. + + Introduce ulTaskGetIdleRunTimePercent() to complement the pre-existing + ulTaskGetIdleRunTimeCounter(). Whereas the pre-existing function returns + the raw run time counter value, the new function returns the percentage of + the entire run time consumed by the idle task. Note the amount of idle + time is only a good measure of the slack time in a system if there are no + other tasks executing at the idle priority, tickless idle is not used, and + configIDLE_SHOULD_YIELD is set to 0. + + ARMv8-M secure-side port: Tasks that call secure functions from the + non-secure side of an ARMv8-M MCU (ARM Cortex-M23 and Cortex-M33) have two + contexts - one on the non-secure side and one on the secure-side. Previous + versions of the FreeRTOS ARMv8-M secure-side ports allocated the structures + that reference secure-side contexts at run time. Now the structures are + allocated statically at compile time. The change necessitates the + introduction of the secureconfigMAX_SECURE_CONTEXTS configuration constant, + which sets the number of statically allocated secure contexts. + secureconfigMAX_SECURE_CONTEXTS defaults to 8 if left undefined. + Applications that only use FreeRTOS code on the non-secure side, such as + those running third-party code on the secure side, are not affected by + this change. + +Changes between FreeRTOS V10.4.3 and FreeRTOS V10.4.4 released May 28 2021 + + Minor performance improvements to xTaskIncrementTick() achieved by providing + macro versions of uxListRemove() and vListInsertEnd(). + + Minor refactor of timers.c that obsoletes the need for the + tmrCOMMAND_START_DONT_TRACE macro and removes the need for timers.c to + post to its own event queue. A consequence of this change is that auto- + reload timers that miss their intended next execution time will execute + again immediately rather than executing again the next time the command + queue is processed. (thanks Jeff Tenney). + + Fix a race condition in the message buffer implementation. The + underlying cause was that length and data bytes are written and read as + two distinct operations, which both modify the size of the buffer. If a + context switch occurs after adding or removing the length bytes, but + before adding or removing the data bytes, then another task may observe + the message buffer in an invalid state. + + The xTaskCreate() and xTaskCreateStatic() functions accept a task priority + as an input parameter. The priority has always been silently capped to + (configMAX_PRIORITIES - 1) should it be set to a value above that priority. + Now values above that priority will also trigger a configASSERT() failure. + + Replace configASSERT( pcQueueName ) in vQueueAddToRegistry with a NULL + pointer check. + + Introduce the configSTACK_ALLOCATION_FROM_SEPARATE_HEAP configuration + constant that enables the stack allocated to tasks to come from a heap other + than the heap used by other memory allocations. This enables stacks to be + placed within special regions, such as fast tightly coupled memory. + + If there is an attempt to add the same queue or semaphore handle to the + queue registry more than once then prior versions would create two separate + entries. Now if this is done the first entry is overwritten rather than + duplicated. + + Update the ESP32 port and TF-M (Trusted Firmware M)code to the latest from + their respective repositories. + + Correct a build error in the POSIX port. + + Additional minor formatting updates, including replacing tabs with spaces + in more files. + + Other minor updates include adding additional configASSERT() checks and + correcting and improving code comments. + + Go look at the smp branch to see the progress towards the Symmetric + Multiprocessing Kernel. https://github.com/FreeRTOS/FreeRTOS-Kernel/tree/smp + +Changes between FreeRTOS V10.4.2 and FreeRTOS V10.4.3 released December 14 2020 + + V10.4.3 is included in the 202012.00 LTS release. Learn more at https:/freertos.org/lts-libraries.html + + See https://www.FreeRTOS.org/FreeRTOS-V10.4.x.html + + + Changes to improve robustness and consistency for buffer allocation in + the heap, queue and stream buffer. + + The following functions can no longer be called from unprivileged code. + - xTaskCreateRestricted + - xTaskCreateRestrictedStatic + - vTaskAllocateMPURegions + + +Changes between FreeRTOS V10.4.1 and FreeRTOS V10.4.2 released November 10 2020 + + See https://www.FreeRTOS.org/FreeRTOS-V10.4.x.html + + + Fix an issue in the ARMv8-M ports that caused BASEPRI to be masked + between the first task starting to execute and that task making + a FreeRTOS API call. + + Introduced xTaskDelayUntil(), which is functionally equivalent to + vTaskDelayUntil(), with the addition of returning a value to + indicating whether or not the function placed the calling task into + the Blocked state or not. + + Update WolfSSL to 4.5.0 and add the FIPS ready demo. + + Add support for ESP IDF 4.2 to ThirdParty Xtensa port. + + Re-introduce uxTopUsedPriority to support OpenOCD debugging. + + Convert most dependent libraries in FreeRTOS/FreeRTOS to submodules. + + Various general maintenance and improvements to MISRA compliance. + + +Changes between FreeRTOS V10.4.0 and FreeRTOS V10.4.1 released September 17 2020 + + See https://www.FreeRTOS.org/FreeRTOS-V10.4.x.html + + + Fixed an incorrectly named parameter that prevented the + ulTaskNotifyTakeIndexed macro compiling, and the name space clash in the + test code that prevented this error causing test failures. + + +Changes between FreeRTOS V10.3.1 and FreeRTOS V10.4.0 released September 10 2020 + + See https://www.FreeRTOS.org/FreeRTOS-V10.4.x.html + + Major enhancements: + + + Task notifications: Prior to FreeRTOS V10.4.0 each created task had a + single direct to task notification. From FreeRTOS V10.4.0 each task has + an array of notifications. The direct to task notification API has been + extended with API functions postfixed with "Indexed" to enable the API to + operate on a task notification at any array index. See + https://www.freertos.org/RTOS-task-notifications.html for more information. + + Kernel ports that support memory protection units (MPUs): The ARMv7-M and + ARMv8-M MPU ports now support a privilege access only heap. The ARMv7-M + MPU ports now support devices that have 16 MPU regions, have the ability + to override default memory attributes for privileged code and data + regions, and have the ability to place the FreeRTOS kernel code outside of + the Flash memory. The ARMv8-M MPU ports now support tickless idle mode. + See https://www.freertos.org/FreeRTOS-MPU-memory-protection-unit.html + for more information. + + Additional noteworthy updates: + + + Code formatting is now automated to facilitate the increase in + collaborative development in Git. The auto-formated code is not identical + to the original formatting conventions. Most notably spaces are now used + in place of tabs. + + The prototypes for callback functions (those that start with "Application", + such as vApplicationStackOverflowHook()) are now in the FreeRTOS header + files, removing the need for application writers to add prototypes into + the C files in which they define the functions. + + New Renesas RXv3 port layer. + + Updates to the Synopsys ARC code, including support for EM and HS cores, + and updated BSP. + + Added new POSIX port layer that allows FreeRTOS to run on Linux hosts in + the same way the Windows port layer enables FreeRTOS to run on Windows + hosts. + + Many other minor optimisations and enhancements. For full details + see https://github.com/FreeRTOS/FreeRTOS-Kernel/commits/main + + +Changes between FreeRTOS V10.3.0 and FreeRTOS V10.3.1 released February 18 2020 + + See https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html + + + ./FreeRTOS-Labs directory was removed from this file. The libraries it + contained are now available as a separate download. + +Changes between FreeRTOS V10.2.1 and FreeRTOS V10.3.0 released February 7 2020 + + See https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html + + New and updated kernel ports: + + + Added RISC-V port for the IAR compiler. + + Update the Windows simulator port to use a synchronous object to prevent + a user reported error whereby a task continues to run for a short time + after being moved to the Blocked state. Note we were not able to + replicate the reported issue and it likely depends on your CPU model. + + Correct alignment of stack top in RISC-V port when + configISR_STACK_SIZE_WORDS is defined to a non zero value, which causes + the interrupt stack to be statically allocated. + + The RISC-V machine timer compare register can now be for any HART, whereas + previously it was always assumed FreeRTOS was running on HART 0. + + Update the sequence used to update the 64-bit machine timer + compare register on 32-bit cores to match that suggested in RISC-V + documentation. + + Added tickless low power modes into the ARM, IAR and GCC Cortex-M0 compiler + ports. + + Updated the behaviour of the ARMv7-M MPU (Memory Protection Unit) ports to + match that of the ARMv8-M ports whereby privilege escalations can only + originate from within the kernel's own memory segment. Added + configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY configuration constant. + + Update existing MPU ports to correctly disable the MPU before it is + updated. + + Added contributed port and demo application for a T-Head (formally C-SKY) + microcontroller. + + New API functions: + + + Added the vPortGetHeapStats() API function which returns information on + the heap_4 and heap_5 state. + + Added xTaskCatchUpTicks(), which corrects the tick count value after the + application code has held interrupts disabled for an extended period. + + Added xTaskNotifyValueClear() API function. + + Added uxTimerGetReloadMode() API function. + + Other miscellaneous changes: + + Change type of uxPendedTicks from UBaseType_t to TickType_t to ensure it + has the same type as variables with which it is compared to, and therefore + also renamed the variable xPendingTicks. + + Update Keil projects that use the MPU so memory regions come from linker + script (scatter file) variables instead of being hard coded. + + Added LPC51U68 Cortex-M0+ demos for GCC (MCUXpresso), Keil and IAR + compilers. + + Added CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube demo. + + Added LPC54018 MPU demo. + + Rename xTaskGetIdleRunTimeCounter() to ulTaskGetIdleRunTimeCounter(). + + +Changes between FreeRTOS V10.2.1 and FreeRTOS V10.2.0 released May 13 2019: + + + Added ARM Cortex-M23 port layer to complement the pre-existing ARM + Cortex-M33 port layer. + + The RISC-V port now automatically switches between 32-bit and 64-bit + cores. + + Introduced the portMEMORY_BARRIER macro to prevent instruction re-ordering + when GCC link time optimisation is used. + + Introduced the portDONT_DISCARD macro to the ARMv8-M ports to try and + prevent the secure side builds from removing symbols required by the + non secure side build. + + Introduced the portARCH_NAME to provide additional data to select semi- + automated build environments. + + Cortex-M33 and Cortex-M23 ports now correctly disable the MPU before + updating the MPU registers. + + + Added Nuvoton NuMaker-PFM-M2351 ARM Cortex-M23 demo. + + Added LPC55S69 ARM Cortex-M33 demo. + + Added an STM32 dual core AMP stress test demo. + + +Changes between FreeRTOS V10.1.1 and FreeRTOS V10.2.0 released February 25 2019: + + + Added GCC RISC-V MCU port with three separate demo applications. + + Included pre-existing ARM Cortex-M33 (ARMv8-M) GCC/ARMclang and IAR ports + with Keil simulator demo. + + Update the method used to detect if a timer is active. Previously the + timer was deemed to be inactive if it was not referenced from a list. + However, when a timer is updated it is temporarily removed from, then + re-added to a list, so now the timer's active status is stored separately. + + Add vTimerSetReloadMode(), xTaskGetIdleRunTimeCounter(), and + xTaskGetApplicationTaskTagFromISR() API functions. + + Updated third party Xtensa port so it is MIT licensed. + + Added configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H to the Renesas + compiler RX600v2 port to enable switching between platform.h and + iodefine.h includes within that port's port.c file. + + Removed the 'FromISR' functions from the MPU ports as ISRs run privileged + anyway. + + Added uxTaskGetStackHighWaterMark2() function to enable the return type to + be changed without breaking backward compatibility. + uxTaskGetStackHighWaterMark() returns a UBaseType_t as always, + uxTaskGetStackHighWaterMark2() returns configSTACK_DEPTH_TYPE to allow the + user to determine the return type. + + Fixed issues in memory protected ports related to different combinations + of static memory only and dynamic memory only builds. As a result the + definition of tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE became more + complex and was moved to FreeRTOS.h with a table explaining its definition. + + Added a 'get task tag from ISR' function. + + Change the method used to determine if a timer is active or not from just + seeing if it is referenced from the active timer list to storing its + active state explicitly. The change prevents the timer reporting that it + is inactive while it is being moved from one list to another. + + The pcName parameter passed into the task create functions can be NULL, + previously a name had to be provided. + + When using tickless idle, prvResetNextTaskUnblockTime() is now only called + in xTaskRemoveFromEventList() if the scheduler is not suspended. + + Introduced portHAS_STACK_OVERFLOW_CHECKING, which should be set to 1 for + FreeRTOS ports that run on architectures that have stack limit registers. + + +Changes between FreeRTOS V10.1.0 and FreeRTOS V10.1.1 released 7 September 2018 + + + Reverted a few structure name changes that broke several kernel aware + debugger plug-ins. + + Updated to the latest trace recorder code. + + Fixed some formatting in the FreeRTOS+TCP TCP/IP stack code. + + Reverted moving some variables from file to function scope as doing so + broke debug scenarios that require the static qualifier to be removed. + +Changes between FreeRTOS V10.0.1 and FreeRTOS V10.1.0 released 22 August 2018 + + FreeRTOS Kernel Changes: + + + Update lint checked MISRA compliance to use the latest MISRA standard, was + previously using the original MISRA standard. + + Updated all object handles (TaskHandle_t, QueueHandle_t, etc.) to be + unique types instead of void pointers, improving type safety. (this was + attempted some years back but had to be backed out due to bugs in some + debuggers). Note this required the pvContainer member of a ListItem_t + struct to be renamed - set configENABLE_BACKWARD_COMPATIBILITY to 1 if + this causes an issue. + + Added configUSE_POSIX_ERRNO to enable per task POSIX style errno + functionality in a more user friendly way - previously the generic thread + local storage feature was used for this purpose. + + Added Xtensa port and demo application for the XCC compiler. + + Changed the implementation of vPortEndScheduler() for the Win32 port to + simply call exit( 0 ). + + Bug fix in vPortEnableInterrupt() for the GCC Microblaze port to protect + the read modify write access to an internal Microblaze register. + + Fix minor niggles when the MPU is used with regards to prototype + differences, static struct size differences, etc. + + The usStackHighWaterMark member of the TaskStatus_t structure now has type + configSTACK_DEPTH_TYPE in place of uint16_t - that change should have been + made when the configSTACK_DEPTH_TYPE type (which gets around the previous + 16-bit limit on stack size specifications) was introduced. + + Added the xMessageBufferNextLengthBytes() API function and likewise stream + buffer equivalent. + + Introduce configMESSAGE_BUFFER_LENGTH_TYPE to allow the number of bytes + used to hold the length of a message in the message buffer to be reduced. + configMESSAGE_BUFFER_LENGTH_TYPE default to size_t, but if, for example, + messages can never be more than 255 bytes it could be set to uint8_t, + saving 3 bytes each time a message is written into the message buffer + (assuming sizeof( size_t ) is 4). + + Updated the StaticTimer_t structure to ensure it matches the size of the + Timer_t structure when the size of TaskFunction_t does not equal the size + of void *. + + Update various Xilinx demos to use 2018.1 version of the SDK tools. + + Various updates to demo tasks to maintain test coverage. + + FreeRTOS+UDP was removed in FreeRTOS V10.1.0 as it was replaced by + FreeRTOS+TCP, which was brought into the main download in FreeRTOS + V10.0.0. FreeRTOS+TCP can be configured as a UDP only stack, and + FreeRTOS+UDP does not contain the patches applied to FreeRTOS+TCP. + + FreeRTOS+TCP Changes: + + + Multiple security improvements and fixes in packet parsing routines, DNS + caching, and TCP sequence number and ID generation. + + Disable NBNS and LLMNR by default. + + Add TCP hang protection by default. + + We thank Ori Karliner of Zimperium zLabs Team for reporting these issues. + + +Changes between FreeRTOS V10.0.0 and FreeRTOS V10.0.1, released December 20 2017 + + + Fix position of "#if defined( __cplusplus )" in stream_buffer.h. + + Correct declarations of MPU_xQueuePeek() and MPU_xQueueSemaphoreTake() in + mpu_prototypes.h. + + Correct formatting in vTaskList() helper function when it prints the state + of the currently executing task. + + Introduce #error if stream_buffer.c is built without + configUSE_TASK_NOTIFICATIONS set to 1. + + Update FreeRTOS+TCP to V2.0.0 + - Improve the formatting of text that displays the available netword + interfaces when FreeRTOS+TCP is used on Windows with WinPCap. + - Introduce ipconfigSOCKET_HAS_USER_WAKE_CALLBACK option to enable a user + definable callback to execute when data arrives on a socket. + +Changes between FreeRTOS V9.0.1 and FreeRTOS V10.0.0: + + The FreeRTOS kernel is now MIT licensed: https://www.FreeRTOS.org/license + + New Features and components: + + + Stream Buffers - see https://www.FreeRTOS.org/RTOS-stream-buffer-example.html + + Message Buffers - see https://www.FreeRTOS.org//RTOS-message-buffer-example.html + + Move FreeRTOS+TCP into the main repository, along with the basic Win32 + TCP demo FreeRTOS_Plus_TCP_Minimal_Windows_Simulator. + + New ports or demos: + + + Added demo for TI SimpleLink CC3220 MCU. + + Added MPU and non MPU projects for Microchip CEC and MEC 17xx and 51xx + MCUs. + + Added CORTEX_MPU_Static_Simulator_Keil_GCC demo to test static allocation + in the MPU port. + + Fixes or enhancements: + + + Cortex-M ports push additional register prior to calling + vTaskSwitchContext to ensure 8-byte alignment is maintained. Only + important if a user defined tick hook function performs an operation that + requires 8-byte alignment. + + Optimisations to the implementation of the standard tickless idle mode on + Cortex-M devices. + + Improvements to the Win32 port including using higher priority threads. + + Ensure interrupt stack alignment on PIC32 ports. + + Updated GCC TriCore port to build with later compiler versions. + + Update mpu_wrappers.c to support static allocation. + + The uxNumberOfItems member of List_t is now volatile - solving an issue + when the IAR compiler was used with maximum optimization. + + Introduced configRECORD_STACK_HIGH_ADDRESS. When set to 1 the stack start + address is saved into each task's TCB (assuming stack grows down). + + Introduced configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H to allow user defined + functionality, and user defined initialisation, to be added to FreeRTOS's + tasks.c source file. When configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H is + set to 1 a user provided header file called freertos_task_c_additions.h + will be included at the bottom of tasks.c. Functions defined in that + header file can call freertos_tasks_c_additions_init(), which in turn + calls a macro called FREERTOS_TASKS_C_ADDITIONS_INIT(), if it is defined. + FREERTOS_TASKS_C_ADDITIONS_INIT() can be defined in FreeRTOSConfig.h. + + Introduced configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( x ) which can be + defined by a user in FreeRTOSConfig.h. The macro is called before + assessing whether to enter tickless idle mode or not. If the macro sets + x to zero then tickless idle mode will not be entered. This allows users + to abort tickless idle mode entry before the tickless idle function is + even called - previously it was only possible to abort from within the + tickless idle function itself. + + Added configPRINTF(), which can be defined by users to allow all libraries + to use the same print formatter. + + Introduced configMAX() and configMIN() macros which default to standard + max( x, y ) and min( x, y ) macro behaviour, but can be overridden if the + application writer defines the same macros in FreeRTOSConfig.h. + + Corrected the definition of StaticTask_t in the case where + INCLUDE_xTaskAbortDelay is set to 1. + + Introduced configTIMER_SERVICE_TASK_NAME and configIDLE_TASK_NAME, both of + which can be defined to strings in FreeRTOSConfig.h to change the default + names of the timer service and idle tasks respectively. + + Only fill the stack of a newly created task with a known value if stack + checking, or high water mark checking/viewing, is in use - removing the + dependency on memset() in other cases. + + Introduced xTaskCreateRestrictedStatic() so static allocation can be used + with the MPU. + + Ensure suspended tasks cannot be unsuspended by a received task + notification. + + Fix race condition in vTaskSetTimeOutState(). + + Updated trace recorder files to the latest version. + +Changes since FreeRTOS V9.0.0: + + + Priority dis-inheritance behaviour has been enhanced in the case where a + task that attempted to take a mutex that was held by a lower priority task + timed out before it was able to obtain the mutex (causing the task that + holds the mutex to have its priority raised, then lowered again, in + accordance with the priority inheritance protocol). + + Split the overloaded xQueueGenericReceive() function into three separate + dedicated functions. + + Allow the default human readable text names given to the Idle and Timer + tasks to be overridden by defining the configIDLE_TASK_NAME and + configTIMER_SERVICE_TASK_NAME definitions respectively in FreeRTOSConfig.h. + + Introduced configINITIAL_TICK_COUNT to allow the tick count to take a + value of than than 0 when the system boots. This can be useful for + testing purposes - although setting configUSE_16_BIT_TICKS to 1 can also + be used to test frequent tick overflows. + + Ensure the Cortex-M SysTick count is cleared to zero before starting the + first task. + + Add configASSERT() into ARM Cortex-M ports to check the number of priority + bit settings. + + Clear the 'control' register before starting ARM Cortex-M4F ports in case + the FPU is used before the scheduler is started. This just saves a few + bytes on the main stack as it prevents space being left for a later save + of FPU registers. + + Added xSemaphoreGetMutexHolderFromISR(). + + Corrected use of portNVIC_PENDSVSET to portNVIC_PENDSVSET_BIT in MPU ports. + + Introduced configSTACK_DEPTH_TYPE to allow users to change the type used + to specify the stack size when using xTaskCreate(). For historic reasons, + when FreeRTOS was only used on small MCUs, the type was set to uint16_t, + but that can be too restrictive when FreeRTOS is used on larger + processors. configSTACK_DEPTH_TYPE defaults to uint16_t. + xTaskCreateStatic(), being a newer function, used a uint32_t. + + Increase the priority of the Windows threads used by the Win32 port. As + all the threads run on the same core, and the threads run with very high + priority, there is a risk that the host will become unresponsive, so also + prevent the Windows port executing on single core hosts. + +Changes between FreeRTOS V9.0.0 and FreeRTOS V9.0.0rc2 released May 25 2016: + + See https://www.FreeRTOS.org/FreeRTOS-V9.html + + RTOS kernel updates: + + + The prototype of the new xTaskCreateStatic() API function was modified to + remove a parameter and improve compatibility with other new + "CreateStatic()" API functions. The stack size parameter in + xTaskCreateStatic() is now uint32_t, which changes the prototype of the + callback functions. See the following URL: + https://www.FreeRTOS.org/xTaskCreateStatic.html + + GCC ARM Cortex-A port: Introduced the configUSE_TASK_FPU_SUPPORT + constant. When configUSE_TASK_FPU_SUPPORT is set to 2 every task is + automatically given a floating point (FPU) context. + + GCC ARM Cortex-A port: It is now possible to automatically save and + restore all floating point (FPU) registers on entry to each potentially + nested interrupt by defining vApplicationFPUSafeIRQHandler() instead of + vApplicationIRQHandler(). + + All ARM Cortex-M3/4F/7 ports: Clear the least significant bit of the task + entry address placed onto the stack of a task when the task is created for + strict compliance with the ARM Cortex-M3/4/7 architecture documentation + (no noticeable effect unless using the QMEU emulator). + + Added GCC and Keil ARM Cortex-M4F MPU ports - previously the MPU was only + supported on ARM Cortex-M3. + + ARM Cortex-M3/4F MPU ports: Update to fully support the FreeRTOS V9.0.0 + API (other than static object creation) and added the + FreeRTOS/Demo/CORTEX_MPU_Simulator_Keil_GCC demo application to + demonstrate how to use the updated MPU port. + + All ARM Cortex-M3/4F/7 ports: Add additional barrier instructions to the + default low power tickless implementation. + + All ARM Cortex-M0 ports: Prevent an item being left on the stack of the + first task that executes. + + Win32 ports: Reduce the amount of stack used and change the way Windows + threads are deleted to increase the maximum execution time. + + Add an ARM Cortex-M4F port for the MikroC compiler. Ensure to read the + documentation page for this port before use. + + MPS430X IAR port: Update to be compatible with the latest EW430 tools + release. + + IAR32 GCC port: Correct vPortExitCritical() when + configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY. + + For consistency vTaskGetTaskInfo() now has the alias vTaskGetInfo(), + xTaskGetTaskHandle() now has the alias xTaskGetHandle() and + pcQueueGetQueueName() now has an alias pcQueueGetName(). + + Fix various errors in comments and compiler warnings. + + Demo application updates: + + + Update Atmel Studio projects to use Atmel Studio 7. + + Update Xilinx SDK projects to use the 2016.1 version of the SDK. + + Remove dependency on legacy IO libraries from the PIC32 demos. + + Move the Xilinx UltraScale Cortex-R5 demo into the main distribution. + + Update the MSP432 libraries to the latest version. + + Add Microchip CEC1302 (ARM Cortex-M4F) demos for GCC, Keil and MikroC + compilers. + + Move the Atmel SAMA5D2 demo into the main distribution. + +Changes between FreeRTOS V9.0.0rc1 and FreeRTOS V9.0.0rc2 (release candidate 2) +released March 30 2016: + + NOTE - See https://www.FreeRTOS.org/FreeRTOS-V9.html for details + + + The functions that create RTOS objects using static memory allocation have + been simplified and will not revert to using dynamic allocation if a + buffer is passed into a function as NULL. + + Introduced the configSUPPORT_DYNAMIC_ALLOCATION configuration constant to + allow a FreeRTOS application to be built without a heap even being being + defined. The Win32 example located in the + /FreeRTOS/demo/WIN32-MSVC-Static-Allocation-Only directory is provided as + a reference for projects that do not include a FreeRTOS heap. + + Minor run-time optimisations. + + Two new low power tickless implementations that target Silicon Labs EFM32 + microcontrollers. + + Addition of the xTimerGetPeriod() and xTimerGetExpireTime() API functions. + +Changes between FreeRTOS V8.2.3 and FreeRTOS V9.0.0rc1 (release candidate 1) +released February 19 2016: + + RTOS Kernel Updates: + + + Major new feature - tasks, semaphores, queues, timers and event groups can + now be created using statically allocated memory, so without any calls to + pvPortMalloc(). + + Major new features - Added the xTaskAbortDelay() API function which allows + one task to force another task to immediately leave the Blocked state, + even if the event the blocked task is waiting for has not occurred, or the + blocked task's timeout has not expired. + + Updates necessary to allow FreeRTOS to run on 64-bit architectures. + + Added vApplicationDaemonTaskStartupHook() which executes when the RTOS + daemon task (which used to be called the timer service task) starts + running. This is useful if the application includes initialisation code + that would benefit from executing after the scheduler has been started. + + Added the xTaskGetTaskHandle() API function, which obtains a task handle + from the task's name. xTaskGetTaskHandle() uses multiple string compare + operations, so it is recommended that it is called only once per task. + The handle returned by xTaskGetTaskHandle() can then be stored locally for + later re-use. + + Added the pcQueueGetQueueName() API function, which obtains the name of + a queue from the queue's handle. + + Tickless idling (for low power applications) can now also be used when + configUSE_PREEMPTION is 0. + + If one task deletes another task, then the stack and TCB of the deleted + task is now freed immediately. If a task deletes itself, then the stack + and TCB of the deleted task are freed by the Idle task as before. + + If a task notification is used to unblock a task from an ISR, but the + xHigherPriorityTaskWoken parameter is not used, then pend a context switch + that will then occur during the next tick interrupt. + + Heap_1.c and Heap_2.c now use the configAPPLICATION_ALLOCATED_HEAP + settings, which previously was only used by heap_4.c. + configAPPLICATION_ALLOCATED_HEAP allows the application writer to declare + the array that will be used as the FreeRTOS heap, and in-so-doing, place + the heap at a specific memory location. + + TaskStatus_t structures are used to obtain details of a task. + TaskStatus_t now includes the bae address of the task's stack. + + Added the vTaskGetTaskInfo() API function, which returns a TaskStatus_t + structure that contains information about a single task. Previously this + information could only be obtained for all the tasks at once, as an array + of TaskStatus_t structures. + + Added the uxSemaphoreGetCount() API function. + + Replicate previous Cortex-M4F and Cortex-M7 optimisations in some + Cortex-M3 port layers. + + Demo Application Updates: + + Further demo applications will be added prior to the final FreeRTOS V9 + release. + + + Updated SAM4L Atmel Studio project to use Atmel Studio 7. + + Added ARM Cortex-A53 64-bit port. + + Added a port and demo for the ARM Cortex-A53 64-bit cores on the Xilinx + Ultrascale MPSoC. + + Added Cortex-M7 SAME70 GCC demo. + + Added EFM32 Giant and Wonder Gecko demos. + + +Changes between V8.2.2 and V8.2.3 released October 16, 2015 + + RTOS kernel updates: + + + Fix bug identified in a modification made in V8.2.2 to the software timer + code that allows tickless low power applications to sleep indefinitely + when software timers are used. + + Simplify and improve efficiency of stack overflow checking. + + Add xTaskNotifyStateClear() API function. + + New IAR and GCC Cortex-R ports for microprocessors that do not use an ARM + generic interrupt controller (GIC). + + New PIC32MEC14xx port. + + Add support for PIC32MZ EF parts (with floating point) into the PIC32MZ + port. + + Zynq7000 port layer now declares the functions that setup and clear the + tick interrupt as weak symbols so they can be overridden by the + application, and uses a global XScuGic object so the same object can be + used by the application code. + + Introduced configUSE_TASK_FPU_SUPPORT, although the PIC32MZ EF port is + currently the only port that uses it. + + Updates to RL78 and 78K0 IAR port layers to improve support for + combinations of memory models. + + Minor updates to heap_5.c to remove compiler warnings generated by some + compilers. + + License simplifications. See /FreeRTOS/License/license.txt in the + official distribution. + + FreeRTOS+ updates: + + + Update directory names to use WolfSSL instead of CyaSSL, inline with + WolfSSL's re-branding. + + Update to latest WolfSSL code. + + Update to latest FreeRTOS+Trace recorder code. + + Add in the FreeRTOS+Trace recorder library required for streaming trace. + + Demo application changes: + + + Add demo applications for Renesas RZ/T (Cortex-R), PIC32MZ EF (PIC32 with + floating point hardware), PIC32MEC14xx, RX71M, RX113 and RX231. + + General tidy up of spelling and compiler warnings. + + +Changes between V8.2.1 and V8.2.2 released August 12, 2015 + + RTOS kernel updates: + + + Added Intel IA32/x86 32-bit port. + + General maintenance. + + PRIVILEGED_FUNCTION and PRIVILEGED_DATA macros, which are used in memory + protected systems, have been added to the newer event group and software + timer functions. + + Add the errno definitions used by FreeRTOS+ components into projdefs.h. + + Remove the restriction that prevented tick-less idle implementations + waiting indefinitely when software timers were used in the same + application. + + Introduce xTaskNotifyAndQueryFromISR() as the interrupt safe version of + xTaskNotifyAndQuery(). + + Add additional NOPs to the MSP430X port layers to ensure strict compliance + with the hardware documentation. + + Microblaze port: Added option for port optimised task selection. + + Microblaze port: Previously tasks inherited the exception enable state + at the time the task was created. Now all tasks are created with + exceptions enabled if the Microblaze design supports exceptions. + + Windows port: Add additional safe guards to ensure the correct start up + sequence and thread switching timing. + + Windows port: Improve the implementation of the port optimised task + selection assembly code. + + Update heap_4 and heap_5 to allow use on 64-bit processors. + + Simplify the code that creates a queue. + + General improved tick-less idle behaviour. + + Ensure none of the variables in the common kernel files are initialised to + anything other than zero. + + Correct calculation of xHeapStructSize in heap_4 and heap_5. + + Demo application updates: + + + Added demo project for the new IA32/x86 port that targets the Galileo + hardware. + + Added MSP430FR5969 demos (previously provided as a separate download). + + Added FreeRTOS BSP repository for automatic creation of FreeRTOS + applications in the Xilinx SDK. + + Added Atmel Studio / GCC project for the SAMV71 (ARM Cortex-M7) + + Update Xilinx SDK projects to use version 2015.2 of the SDK. + + Remove Microblaze demos that were using obsolete tools. + + Add MSP43FR5969 IAR and CCS demos. + + FreeRTOS+ Updates: + + + Updated FreeRTOS+Trace recorder library, which requires an update to the + FreeRTOS+Trace application. + + Added Reliance Edge source code and demo application. Reliance edge is + a fail safe transactional file system ideal for applications that require + file storage, and especially when high reliability is essential. + + Introduce configAPPLICATION_PROVIDES_cOutputBuffer to allow FreeRTOS+CLI + users to place the output buffer at a fixed memory address. + + Improve the NetworkInterface.c file provided for the Windows port of + FreeRTOS+UDP. + +Changes between V8.2.0 and V8.2.1 released 24th March 2015. + + RTOS kernel updates: + + + Added user definable and flexible thread local storage facility. + + Added vTimerSetTimerID() API function to complement the pvTimerGetTimerID() + function to allow the timer's ID to be used as timer local storage. + + Fixed a potential issue related to the use of queue sets from an ISR. + + Some updates to the Xilinx Microblaze GCC port. + + Added ARM Cortex-M4F port for Texas Instruments Code Composer Studio. + + Added ARM Cortex-M7 r0p1 port layer for IAR, GCC and Keil which contains a + minor errata work around. All other ARM Cortex-M7 core revisions should + use the ARM Cortex-M4F port. + + Exclude the whole of croutine.c if configUSE_CO_ROUTINES is set to 0. + + Change some data types from uint32_t to size_t in preparation for 64-bit + Windows port. + + Update the PIC32 port to remove deprecation warnings output by the latest + XC32 compilers. + + Fix bug when xQueueOverwrite() and xQueueOverwrite() from ISR are used to + overwrite items in two queues that are part of the same set. + + Demo application updates: + + + Added demo application for TI's ARM Cortex-M4F based MSP432 + microcontroller using IAR, Keil and CCS compilers. + + Added demo application for STM32F ARM Cortex-M7 based microcontroller + using IAR and Keil. + + Added demo application for Atmel SAMV71 ARM Cortex-M7 based + microcontroller using IAR and Keil. + + Added Microblaze demo that uses the 2014.4 version of the Xilinx SDK and + runs on the KC705 evaluation board (Kintex FPGA). + +Changes between V8.1.2 and V8.2.0 released 16th January 2015 + + Changes between release candidate 1 and the official release are restricted + to maintenance only. + + Significant RTOS kernel updates: + + + MAJOR NEW FEATURE! Task notifications. Please see the following URL for + details: https://www.FreeRTOS.org/RTOS-task-notifications.html + + NEW HEADER FILE REQUIRED! Obsolete definitions have been separated into + a new header file called FreeRTOS/Source/include/deprecated_definitions.h. + This header file must be present to build. Note some of the obsolete + definitions are still used by very old demo application projects. + + Other RTOS kernel updates: + + + Made xSemaphoreGiveFromISR() a function rather than a macro that calls + xQueueGenericSendFromISR(). This allows for major performance + enhancements at the expense of some additional code size if both functions + are used in the same application. NOTE: In most uses cases such use of + a semaphore can now be replaced with a task notification which is smaller + and faster still. + + The TCB is now always allocated such that the task's stack grows away from + the TCB (improves debugging of stack overflows as the overflow will not + overwrite the task's name). + + GCC, IAR and Keil Cortex-M4F ports now use more inlining (performance + enhancements at the cost of a little additional code space). + + Queues are now allocated with a single call to pvPortMalloc() which + allocates both the queue structure and the queue storage area. + + Introduced a new critical section macro for reading the tick count that + defines away to nothing in cases where the width of the tick allows the + tick count to be read atomically (performance benefits - especially when + optimisation is on). + + Introduced configAPPLICATION_ALLOCATED_HEAP in heap_4.c to allow the + application writer to provide their own heap array - and in so doing + control the location of the heap. + + Introduced configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES which, when set, will + include known values in both list and list item structures. The values + are intended to assist debugging. If the values get overwritten then it + is likely application code has written over RAM used by the kernel. + + configASSERT()s in all Cortex-M ports used to test the lowest 5 bits of + the interrupt control register to detect taskENTER_CRITICAL() being called + from an interrupt. This has been changed to test all 8 bits. + + Introduced uxTaskPriorityGetFromISR(). + + Microblze V8 port now tests XPAR_MICROBLAZE_0_USE_FPU for inequality to 0 + rather than equality to 1, and 2 and 3 are also valid values. + + Cortex-A5 GIC-less port no longer passes the address of the interrupting + peripheral into the interrupt handler. + + Fix an issue in FreeRTOS-MPU where an attempt was made to free the stack + belonging to a task when the task was deleted, even when the stack was + allocated statically. + + Utility (helper) functions that format task statistic information into + human readable tables now pad task names with spaces to ensure columns + line up correctly even where task name lengths vary greatly. + + Update FreeRTOS+Trace recorder library to version 2.7.0. + + Demo application updates: + + + Added two new standard demo task sets: IntSemTest and TaskNotify. + + Added port and demo application for Atmel SAMA5D4 Cortex-A5 MPU. + + Added demo application for Altera Cyclone V Cortex-A9 MPU. + + Updated Zynq demo to use version 2014.4 of Xilinx's SDK and added in + demo tasks for new RTOS features. + + Updated Atmel SAM4E and SAM4S demos to include a lot of additional test + and demo tasks. + + Fixed a corner case issue in Atmel SAM4L low power tickless + implementation, and added button interrupt handling. + + Make the interrupt queue tests more tolerant to heave CPU loads. + + Updated MSVC FreeRTOS simulator demo to include the latest standard test + and demo tasks. + + Updated MingW/Eclipse FreeRTOS simulator demo to match the FreeRTOS MSVC + simulator demo. + + Updated all demos that use FreeRTOS+Trace to work with the latest trace + recorder code. + + +Changes between V8.1.1 and V8.1.2 released September 2nd 2014 + + Move the defaulting of configUSE_PORT_OPTIMISED_TASK_SELECTION into the + individual port layers where necessary so it does not affect ports that do + not support the definition. + +Changes between V8.1.0 and V8.1.1 released August 29th 2014 + + By popular requests - a minor patch to V8.1.0 to re-instate the ability to + give a mutex type semaphore (with priority inheritance) from an interrupt + handler. + +Changes between V8.0.1 and V8.1.0 released August 26th 2014 + + FreeRTOS scheduler, kernel, demo and test updates: + + + Improved the priority inheritance algorithms to assist integration with + off the shelf middleware that may hold multiple mutexes simultaneously. + + Introduce heap_5.c, which is similar to heap_4.c but allows the heap to + span multiple non-contiguous memory regions. + + Updated all Cortex-A9 ports to help trap a couple of common usage errors - + the first being when a task incorrectly attempts to exit its implementing + function and the second being when a non interrupt safe API function is + called from an interrupt. + + Update all Cortex-A9 ports to remove obsolete mode switches prior to + restoring a task context. + + configUSE_PORT_OPTIMISED_TASK_SELECTION now defaults to 1 instead of 0. + + Update all Cortex-M3/4F ports to trap a non interrupt safe API function + being called from an interrupt handler. + + Simplify the alignment checks in heap_4.c. + + Update the MSVC Windows simulator demo to use heap_5.c in place of + heap_4.c to ensure end users have an example to refer to. + + Updated standard demo test code to test the new priority inheritance + algorithms. + + Updated the standard demo tasks to make use of stdint and the FreeRTOS + specific typedefs that were introduced in FreeRTOS V8.0.0. + + Introduce the pdMS_TO_TICKS() macro as a more user friendly and intuitive + alternative to pdTICKS_PER_MS - both of which can be used to convert a + time specified in milliseconds to a time specified in RTOS ticks. + + Fix a bug in the Tasking compiler's Cortex-M port that resulted in an + incorrect value being written to the basepri register. This only effects + users of the Tasking compiler. + + Update the Zynq demo to use version 2014.2 of the SDK and add in an lwIP + example that demonstrates lwIP being used with both its raw and sockets + interfaces. + + Updated the CCS Cortex-R4 port to enable it to be built with the latest + CCS compiler. + + New ports and demo applications: + + + Two Renesas RX64M ports (RXv2 core) and demos introduced, one for the GCC + compiler and one for the Renesas compiler. Both demos use e2 studio. + + Generic IAR Cortex-A5 port (without any reliance on a GIC) introduced. + The new port is demonstrated on an Atmel SAMA5D3 XPlained board. + + FreeRTOS+ component updates: + + + Update CyaSSL to the latest version. + + Updated the FreeRTOS+ components supplied directly by Real Time Engineers + Ltd. to make use of stdint and the FreeRTOS specific typedefs that were + introduced in FreeRTOS V8.0.0. + + Rework and simplify the FreeRTOS+FAT SL RAM disk driver. + + Miscellaneous updates and maintenance: + + + Update the IAR and DS-5/ARM RZ demos to target the official RZ RSK + hardware in place of the previously targeted Renesas internal (not + publicly available) hardware. + + Various other maintenance tasks. + + +Changes between V8.0.0 and V8.0.1 released 2nd May 2014 + + + Minor fixes to the event group functionality that was released in V8.0.0. + The 'clear bits from ISR' functionality is now implemented using a + deferred interrupt callback instead of a function, and the 'wait bits' and + 'task sync' functions now correctly clear internal control bits before + returning a value in every possible path through the respective functions. + + Ensure the updating of internal control data is protected by a critical + section after a task is deleted or suspended. + + Minor fixes to FreeRTOS+FAT SL - namely seeking beyond the end of a file + when the offset was not a multiple of the sector size. + + Ensure Cortex-A9 system registers are only ever accessed as 32-bit values, + even when only the lest significant byte of the register is implemented. + + Other updates: + + + Updated the XMC4200 IAR project so it links with version 7.x of the IAR + tools. + + Add RL78L1C demo. + + Add pcTimerGetName() API function. + + Call _reclaim_reent() when a task is deleted if configUSE_NEWLIB_REENTRANT + is defined. + +Changes between V7.6.0 and V8.0.0 released 19th Feb 2014 + + https://www.FreeRTOS.org/upgrading-to-FreeRTOS-V8.html + + FreeRTOS V8.x.x is a drop-in compatible replacement for FreeRTOS V7.x.x, + although a change to the type used to reference character strings may result + in application code generating a few (easily clearable) compiler warnings + after the upgrade, and an updated typedef naming convention means use of the + old typedef names is now discouraged. + See https://www.FreeRTOS.org/upgrading-to-FreeRTOS-V8.html for full + information. + + New features and functionality: + + + Event groups - see https://www.FreeRTOS.org/FreeRTOS-Event-Groups.html + + Centralised deferred interrupt processing - see + https://www.FreeRTOS.org/xTimerPendFunctionCallFromISR.html + + Other updates: + + + Previously, when a task left the Blocked state, a context switch was + performed if the priority of the unblocked task was greater than or equal + to the priority of the Running task. Now a context switch is only + performed if the priority of the unblocked task is greater than the + priority of the Running task. + + New low power tickless demonstration project that targets the ST STM32L + microcontroller - see + https://www.FreeRTOS.org/STM32L-discovery-low-power-tickless-RTOS-demo.html + + Add xPortGetMinimumEverFreeHeapSize() to heap_4.c. + + Small change to the tickless low power implementation on the SAM4L to + ensure the alarm value (compare match value) cannot be set to zero when a + tickless period is exited due to an interrupt originating from a source + other than the RTOS tick. + + Update the GCC/Eclipse Win32 simulator demo to make better use of Eclipse + resource filters and match the functionality of the MSVC equivalent. + + xTaskIsTaskSuspended() is no longer a public function. Use + eTaskGetState() in its place. + + Improved trace macros, including tracing of heap usage. + + Remove one level of indirection when accepting interrupts on the PIC32MZ. + + Add Cortex-A9 GCC port layer. + + Add Xilinx Zynq demo application. + + +Changes between V7.5.3 and V7.6.0 released 18th November 2013 + + V7.6.0 changes some behaviour when the co-operative scheduler is used (when + configUSE_PREEMPTION is set to 0). It is important to note that the + behaviour of the pre-emptive scheduler is unchanged - the following + description only applies when configUSE_PREEMPTION is set to 0: + + WHEN configUSE_PREEMPTION IS SET TO 0 (which is in a small minority of + cases) a context switch will now only occur when a task places itself into + the Blocked state, or explicitly calls taskYIELD(). This differs from + previous versions, where a context switch would also occur when implicitly + moving a higher priority task out of the Blocked state. For example, + previously, WHEN PREEMPTION WAS TURNED OFF, if task A unblocks task B by + writing to a queue, then the scheduler would switch to the higher priority + task. Now, WHEN PREEMPTION IS TURNED OFF, if task A unblocks task B by + writing to a queue, task B will not start running until task A enters the + Blocked state or task A calls taskYIELD(). [If configUSE_PREEMPTION is not + set to 0, so the normal pre-emptive scheduler is being used, then task B + will start running immediately that it is moved out of the Blocked state]. + + Other changes: + + + Added a port layer and a demo project for the new PIC32MZ architecture. + + Update the PIC32MX port layer to re-introduce some ehb instructions that + were previously removed, add the ability to catch interrupt stack + overflows (previously only task stack overflows were trapped), and also + add the ability to catch an application task incorrectly attempting to + return from its implementing function. + + Make dramatic improvements to the performance of the Win32 simulator port + layer. + + Ensure tasks that are blocked indefinitely report their state as Blocked + instead of Suspended. + + Slight improvement to the Cortex-M4F port layers where previously one + register was inadvertently being saved twice. + + Introduce the xSemaphoreCreateBinary() API function to ensure consistency + in the semantics of how each semaphore type is created. It is no longer + recommended to use vSemaphoreCreateBinary() (the version prefixed with a + 'v'), although it will remain in the code for backward compatibility. + + Update the Cortex-M0 port layers to allow the scheduler to be started + without using the SVC handler. + + Added a build configuration to the PIC32MX MPLAB X demo project that + targets the PIC32 USB II starter kit. Previously all the build + configurations required the Explorer 16 hardware. + + Some of the standard demo tasks have been updated to ensure they execute + correctly with the updated co-operative scheduling behaviour. + + Added comprehensive demo for the Atmel SAM4E, including use of + FreeRTOS+UDP, FreeRTOS+FAT SL and FreeRTOS+CLI. + + FreeRTOS+ Changes: + + + Minor maintenance on FreeRTOS+UDP. + +Changes between V7.5.2 and V7.5.3 released October 14 2013 + + Kernel changes: + + + Prior to V7.5.x yields requested from the tick hook would occur in the + same tick interrupt - revert to that original behaviour. + + New API function uxQueueSpacesAvailable(). + + Introduced the prvTaskExitError() function to Cortex-M0, Cortex-M3/4 + and Cortex-M4F ports. prvTaskExitError() is used to trap tasks that + attempt to return from their implementing functions (tasks should call + vTaskDelete( NULL ); if they want to exit). + + The Cortex-M0 version of portSET_INTERRUPT_MASK_FROM_ISR and + portCLEAR_INTERRUPT_MASK_FROM_ISR are now fully nestable. + + Improved behaviour and robustness of the default Cortex-M tickless idle + behaviour. + + Add workaround for silicon errata PMU_CM001 in Infineon XMC4000 devices to + all Cortex-M4F ports. + + Add Cortex-M0 port for Keil. + + Updated Cortus port. + + Ensure _impure_ptr is initialised before the scheduler is started. + Previously it was not set until the first context switch. + + FreeRTOS+ changes: + + + Update FreeRTOS+UDP to V1.0.1 - including direct integration of the + FreeRTOS+Nabto task, improvements to the DHCP behaviour, and a correction + to the test that prevents the network event hook being called on the first + network down event. The FreeRTOS+UDP change history is maintained + separately. + + Correct the __NVIC_PRIO_BITS setting in the LPC18xx.h header files + provided in the NXP CMSIS library, then update the interrupts used by the + LPC18xx demos accordingly. + + Replace double quotes (") with single quotes (') in FreeRTOS+CLI help + strings to ensure the strings can be used with the JSON descriptions used + in the FreeRTOS+Nabto demos. + + Demo and miscellaneous changes: + + + Added demo for the Atmel SAMD20 Cortex-M0+. The demo includes + FreeRTOS+CLI + + Added a demo for the Infineon Cortex-M0 that can be built with the IAR + Keil and GCC tools. + + Updated the Infineon XMC4000 demos for IAR, Keil, GCC and Tasking tools, + with additional build configurations to directly support the XMC4200 and + XMC4400 devices, in addition to the previously supported XMC4500. + + Updated the demo application. + + Added additional trace macros traceMALLOC and traceFREE to track heap + usage. + +Changes between V7.5.0 and V7.5.2 released July 24 2013 + + V7.5.2 makes the new Cortex-M vPortCheckInterruptPriority() function + compatible with the STM32 standard peripheral driver library, and adds + an extra critical section to the default low power tickless mode + implementation. Only users of the STM32 peripheral library or the default + tickless implementation need update from version 7.5.0. + +Changes between V7.4.2 and V7.5.0 released July 19 2013 + + V7.5.0 is a major upgrade that includes multiple scheduling and efficiency + improvements, and some new API functions. + + Compatibility information for FreeRTOS users: + FreeRTOS V7.5.0 is backward compatible with FreeRTOS V7.4.0 with one + exception; the vTaskList() and vTaskGetRunTimeStats() functions are now + considered legacy, having been replaced by the single uxTaskGetSystemState() + function. configUSE_STATS_FORMATTING_FUNCTIONS must be set to 1 in + FreeRTOSConfig.h for vTaskList() and vTaskGetRunTimeStats() to be + available. + + Compatibility information for FreeRTOS port writers: + vTaskIncrementTick() is now called xTaskIncrementTick() (because it now + returns a value). + + Headline changes: + + + Multiple scheduling and efficiency improvements. + + Core kernel files now pass PC-Lint V8 static checking without outputting + any warnings (information on the test conditions will follow). + + New API functions: + + + uxTaskGetSystemState() https://www.FreeRTOS.org/uxTaskGetSystemState.html + + xQueueOverwrite() https://www.FreeRTOS.org/xQueueOverwrite.html + + xQueueOverwriteFromISR() + + xQueuePeekFromISR() + + The following ports and demos, which were previously available separately, + are now incorporated into the main FreeRTOS zip file download: + + + ARM Cortex-A9 IAR + + ARM Cortex-A9 ARM compiler + + Renesas RZ + + Microsemi SmartFusion2 + + New FreeRTOSConfig.h settings + https://freertos.org/a00110.html + + + configUSE_TIME_SLICING + + configUSE_NEWLIB_REENTRANT + + configUSE_STATS_FORMATTING_FUNCTIONS + + configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS + + Other changes: + + + (MPU port only) The configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS + options provides a mechanism that allows application writers to execute + certain functions in privileged mode even when a task is running in user + mode. + + Ports that support interrupt nesting now include a configASSERT() that + will trigger if an interrupt safe FreeRTOS function is called from an + interrupt that has a priority designated as above the maximum system/API + call interrupt priority. + + The included FreeRTOS+Trace recorder code has been updated to the latest + version, and the demo applications that use the trace recorder code have + been updated accordingly. + + The FreeRTOS Windows Simulator (MSVC version only) has been updated to + include a new basic 'blinky' build option in addition to the original + comprehensive build option. + + Improve RAM usage efficiency of heap_4.c and heap_2.c. + + Prevent heap_4.c from attempting to free memory blocks that were not + allocated by heap_4.c, or have already been freed. + + As FreeRTOS now comes with FreeRTOS+FAT SL (donated by HCC) the Chan FATfs + files have been removed from FreeRTOS/Demo/Common. + + Fix build error when R4 port is build in co-operative mode. + + Multiple port and demo application maintenance activities. + +Changes between V7.4.1 and V7.4.2 released May 1 2013 + + NOTE: There are no changes in the FreeRTOS kernel between V7.4.1 and V7.4.2 + + + Added FreeRTOS+FAT SL source code and demo project. The demo project + runs in the FreeRTOS Windows simulator for easy and hardware independent + experimentation and evaluation. See https://www.FreeRTOS.org/fat_sl + +Changes between V7.4.0 and V7.4.1 released April 18 2013 + + + To ensure strict conformance with the spec and ensure compatibility with + future chips data and instruction barrier instructions have been added to + the yield macros of Cortex-M and Cortex-R port layers. For efficiency + the Cortex-M port layer "yield" and "yield" from ISR are now implemented + separately as the barrier instructions are not required in the ISR case. + + Added FreeRTOS+UDP into main download. + + Reorganised the FreeRTOS+ directory so it now matches the FreeRTOS + directory with Source and Demo subdirectories. + + Implemented the Berkeley sockets select() function in FreeRTOS+UDP. + + Changed (unsigned) casting in calls to standard library functions with + (size_t) casting. + + Added the Atmel SAM4L and Renesas RX100 demos that demonstrates the + tickless (tick suppression) low power FreeRTOS features. + + Add a new RL78 IAR demo that targets numerous new RL78 chips and + evaluation boards. + + Adjusted stack alignment on RX200 ports to ensure an assert was not + falsely triggered when configASSERT() is defined. + + Updated the Cortex_M4F_Infineon_XMC4500_IAR demo to build with the latest + version of EWARM. + + Corrected header comments in the het.c and het.h files (RM48/TMS570 demo). + + +Changes between V7.3.0 and V7.4.0 released February 20 2013 + + + New feature: Queue sets. See: + https://www.FreeRTOS.org/Pend-on-multiple-rtos-objects.html + + Overhauled the default tickless idle mode implementation provided with the + ARM Cortex-M3 port layers. + + Enhanced tickless support in the core kernel code with the introduction of + the configEXPECTED_IDLE_TIME_BEFORE_SLEEP macro and the + eTaskConfirmSleepModeStatus() function. + + Added the QueueSet.c common demo/test file. Several demo applications + have been updated to use the new demo/test tasks. + + Removed reliance on the PLIB libraries from the MPLAB PIC32 port layer and + demo applications. + + Added the FreeRTOS+Trace recorder code to the MSVC Win32 demo. + + Renamed eTaskStateGet() to eTaskGetState() for consistency, and added a + pre-processor macro for backward compatibility with the previous name. + + Updated functions implemented in the core queue.c source file to allow + queue.h to be included from the .c file directly (this prevents compiler + warnings that were generated by some compilers). + + Updated the CCS Cortex-R4 port layer to replace the CLZ assembler function + with the CLZ compiler intrinsic that is provided by the latest versions of + the CCS ARM compiler. + + Updated all heap_x.c implementations to replace the structure that was + used to ensure the start of the heap was aligned with a more portable + direct C code implementation. + + Added support for PIC24 devices that include EDS. + + Minor optimisations to the PIC32 port layer. + + Minor changes to tasks.c that allow the state viewer plug-ins to display + additional information. + + Bug fix: Update prvProcessReceivedCommands() in timers.c to remove an + issue that could occur if the priority of the timer daemon task was set + below the priority of tasks that used timer services. + + Update the FreeRTOS+Trace recorder code to the latest version. + +Changes between V7.2.0 and V7.3.0 released October 31 2012 + + + Added ability to override the default scheduler task selection mechanism + with implementations that make use of architecture specific instructions. + + Added ability to suppress tick interrupts during idle time, and in so + doing, provide the ability to make use of architecture specific low power + functionality. + + Added the portSUPPRESS_TICKS_AND_SLEEP() macro and vTaskStepTick() helper + function. + + Added the configSYSTICK_CLOCK_HZ configuration constant. + + Reworked the Cortex-M3 and Cortex-M4F port layers for GCC, Keil and IAR to + directly support basic power saving functionality. + + Added hooks to allow basic power saving to be augmented in the application + by making use of chip specific functionality. + + Minor change to allow mutex type semaphores to be used from interrupts + (which would not be a normal usage model for a mutex). + + Change the behaviour of the interrupt safe interrupt mask save and restore + macros in the Cortex-M ports. The save macro now returns the previous + mask value. The restore macro now uses the previous mask value. These + changes are not necessary for the kernel's own implementation, and are + made purely because the macros were being used by application writers. + + Added eTaskStateGet() API function. + + Added port specific optimisations to the PIC32 port layer, and updated the + PIC32 demo applications to make use of this new feature. + + Added port specific optimisations to the Win32 simulator port. + + Added new ports and demo applications for the TI Hercules RM48 and TMS570 + safety microcontrollers. + + Added SAM3 demos targeting the ATSAM3S-EK2 and ATSAM3X-EK evaluation + boards. + + Updated the PIC32 MPLAB X project to manually set the compiler include + paths instead of using the IDE entry box following reports that the + include paths were somehow being deleted. + + Improved character handling in FreeRTOS+CLI. + +Changes between V7.1.1 and V7.2.0 released 14 August 2012 + + FreeRTOS V7.2.0 is backward compatible with FreeRTOS V7.1.2. + + + Added a FreeRTOS+ sub-directory. The directory contains some FreeRTOS+ + source code, and example projects that use the FreeRTOS Win32 simulator. + + Added a new example heap allocation implementation (heap_4.c) that + includes memory block coalescence. + + Added a demo that targets the Atmel SAM4S Cortex-M4 based microcontroller. + The demo is preconfigured to build using the free Atmel Studio 6 IDE and + GCC compiler. + + Added xSemaphoreTakeFromISR() implementation. + + The last parameter in ISR safe FreeRTOS queue and semaphore functions + (xHigherPriorityTaskWoken) is now optional and can be set to NULL if it + is not required. + + Update the IAR and MSP430X ports to clear all lower power mode bits before + exiting the tick interrupt [bug fix]. + + Allow xQueueReset() to be used, even when the queues event lists are not + empty. + + Added a vQueueDelete() handler for the FreeRTOS MPU port (this was + previously missing). + + Updated the vPortSVCHandler() functions in the FreeRTOS MPU port layer to + ensure it compiles with the latest ARM GCC compilers from Linaro. + + Updated the prvReadGP() function in the NIOS II port to ensure the compiler + can choose any register for the functions parameter (required at high + compiler optimisation levels). + + Add #error macros into the Keil and IAR Cortex-M ports to ensure they + cannot be built if the user has set configMAX_SYSCALL_INTERRUPT_PRIORITY + to 0. + + Added comments in the FreeRTOSConfig.h files associated with Cortex-M3 and + Cortex-M4 demos stating that the configMAX_SYSCALL_INTERRUPT_PRIORITY + parameter must not be set to 0. + + Introduce new INCLUDE_xQueueGetMutexHolder configuration constant + (defaulted to 0). + + Added two new list handling macros - for internal use only in upcoming new + products. + + Removed all mention of the legacy vTaskStartTrace and ulTaskEndTrace + macros. FreeRTOS+Trace supersedes the legacy trace. + + Added a configASSERT() into the vPortFree() function in heap_1.c as it is + invalid for the function to be called. + + Made the xRxLock and xTxLock members of the queue structure volatile. + This is probably not necessary, and is included as a precautionary + measure. + + Modify the assert() that checks to see if the priority passed into an + xTaskCreate() function is within valid bounds to permit the assert to be + used in the FreeRTOS MPU port. + + The software timer service (daemon) task is now created in a way that + to ensure compatibility with FreeRTOS MPU. + +Changes between V7.1.0 and V7.1.1 released May 1 2012 + + New ports: + + The following ports are brand new: + + Cortex-M3 Tasking + + The following ports have been available as separate downloads for a number + of months, but are now included in the main FreeRTOS download. + + Cortex-M0 IAR + + Cortex-M0 GCC + + Cortex-M4F GCC (with full floating point support) + + + New demos: + + The following demos are brand new: + + Renesas RX63N RDK (Renesas compiler) + + The following demos have been available as separate downloads for a number + of months, but are now included in the main FreeRTOS download. + + NXP LPC1114 GCC/LPCXpresso + + ST STM32F0518 IAR + + Infineon XMC4500 GCC/Atollic + + Infineon XMC4500 IAR + + Infineon XMC4500 Keil + + Infineon XMC4500 Tasking + + + Kernel miscellaneous / maintenance: + + + Introduced the portSETUP_TCB() macro to remove the requirement for the + Windows simulator to use the traceTASK_CREATE() macro, leaving the trace + macro available for use by FreeRTOS+Trace (https://www.FreeRTOS.org/trace). + + Added a new trace macro, traceMOVE_TASK_TO_READY_STATE(), to allow future + FreeRTOS+Trace versions to provide even more information to users. + + Updated the FreeRTOS MPU port to be correct for changes that were + introduced in FreeRTOS V7.1.0. + + Introduced the xQueueReset() API function. + + Introduced the xSemaphoreGetMutexHolder() API function. + + Tidy up various port implementations to add the static key word where + appropriate, and remove obsolete code. + + Slight change to the initial stack frame given to the RX600 ports to allow + them to be used in the Eclipse based E2Studio IDE without confusing GDB. + + Correct the alignment given to the initial stack of Cortex-M4F tasks. + + Added a NOP following each DINT instruction on MSP430 devices for strict + conformance with the instructions on using DINT. + + Changed the implementation of thread deletes in the Win32 port to prevent + the port making use of the traceTASK_DELETE() trace macros - leaving this + macro free for use by FreeRTOS+Trace. + + Made some benign changes to the RX600 Renesas compiler port layer to + ensure the code can be built to a library without essential code being + removed by the linker. + + Reverted the change in the name of the uxTaskNumber variable made in + V7.1.0 as it broke the IAR plug-in. + + + Demo miscellaneous / maintenance: + + + The command interpreter has now been formally released as FreeRTOS+CLI, + and been moved out of the main FreeRTOS download, to instead be available + from the FreeRTOS+ Ecosystem site https://www.FreeRTOS.org/plus. + + flash_timer.c/h has been added to the list of standard demo tasks. This + performs the same functionality as the flash.c tasks, but using software + timers in place of tasks. + + Upgraded the PIC32 demo as follows: Changes to how the library functions + are called necessitated by the new compiler version, addition of MPLAB X + project with PIC32MX360, PIC32MX460 and PIC32MX795 configurations, + addition of simply blinky demo, updated FreeRTOSConfig.h to include more + parameters, addition of hook function stubs. + + The MSP430X IAR and CCS demos have been updated to ensure the power + settings are correct for the configured CPU frequency. + + Rowley CrossWorks projects have been updated to correct the "multiple + definition of ..." warnings introduced when the toolchain was updated. + + Updated various FreeRTOSConfig.h header files associated with projects + that build with Eclipse to include a #error statement informing the user + that the CreateProjectDirectoryStructure.bat batch file needs to be + executed before the projects can be opened. + + Renamed directories that included "CCS4" in their name to remove the '4' + and instead just be "CCS". This is because the demo was updated and + tested to also work with later Code Composer Studio versions. + + Updated the TCP/IP periodic timer frequency in numerous uIP demos to be + 50ms instead of 500ms. + +Changes between V7.0.2 and V7.1.0 released December 13 2011 + + New ports: + + + Cortex-M4F IAR port. + + Cortex-M4F Keil/RVDS port. + + TriCore GCC port. + + New demos: + + + NXP LPC4350 using the Keil MDK, and demonstrated on a Hitex development + board. + + ST STM32F407 using the IAR Embedded Workbench for ARM, and demonstrated on + the IAR STM32F407ZG-SK starter kit. + + Infineon TriCore TC1782, using the GCC compiler, demonstrated on the + TriBoard TC1782 evaluation board. + + Renesas RX630, using the Renesas compiler and HEW, demonstrated on an + RX630 RSK (Renesas Starter Kit). + + Miscellaneous / maintenance: + + + Removed all calls to printf() from the K60/IAR Kinetis demo so the project + can execute stand alone - without being connected to the debugger. + + Completed the command interpreter framework. Command handlers now receive + the entire command string, giving them direct access to parameters. + Utility functions are provided to check the number of parameters, and + return parameter sub-strings. + + The previously documented fix for the bug in xTaskResumeFromISR() that + effected (only) ports supporting interrupt nesting has now been + incorporated into the main release. + + The portALIGNMENT_ASSERT_pxCurrentTCB() definition has been added to allow + specific ports to skip the second stack alignment check when a task is + created. This is because the second check is not appropriate for some + ports - including the new TriCore port where the checked pointer does not + actually point to a stack. + + The portCLEAN_UP_TCB() macro has been added to allow port specific clean + up when a task is deleted - again this is required by the TriCore port. + + Various other minor changes to ensure warning free builds on a growing + number of microcontroller and toolchain platforms. This includes a + (benign) correction to the prototype of the + vApplicationStackOverflowHook() definition found in lots of recent demos. + + Trace system: + + + The legacy trace mechanism has been completely removed - it has been + obsolete for the years since the trace macros were introduced. The + configuration constant configUSE_TRACE_FACILITY is now used to optionally + include additional queue and task information. The additional information + is intended to make the trace mechanism more generic, and allow the trace + output to provide more information. When configUSE_TRACE_FACILITY is set + to 1: + - the queue structure includes an additional member to hold the queue + type, which can be base, mutex, counting semaphore, binary semaphore + or recursive mutex. + - the queue structure includes an additional member to hold a queue + number. A trace tool can set and query the queue number for its own + purposes. The kernel does not use the queue number itself. + - the TCB structure includes an additional member to hold a task number + number. A trace tool can set and query the task number for its own + purposes. The kernel does not use the task number itself. + + Queues and all types of semaphores are now automatically allocated their + type as they are created. + + Added two new trace macros - traceTASK_PRIORITY_INHERIT() and + traskTASK_PRIORITY_DISINHERIT(). + + Updated the traceQUEUE_CREATE_FAILED() macro to take a parameter that + indicates the type of queue, mutex, or semaphore that failed to be + created. + + The position from which traceCREATE_MUTEX() is called has been moved from + after the call to xQueueGenericSend() [within the same function] to before + the call. This ensures the trace events occur in the correct order. + + The value passed into tracePRIORITY_SET() has been corrected for the case + where vTaskPrioritySet() is called with a null parameter. + +Changes between V7.0.1 and V7.0.2 released September 20 2011 + + New ports: + + + The official FreeRTOS Renesas RX200 port and demo application have been + incorporated into the main FreeRTOS zip file download. + + The official FreeRTOS Renesas RL78 port and demo application have been + incorporated into the main FreeRTOS zip file download. + + The official FreeRTOS Freescale Kinetis K60 tower demo application has + been incorporated into the main FreeRTOS zip file download. This includes + an embedded web server example. + + A new Microblaze V8 port layer has been created to replace the older, now + deprecated, port layer. The V8 port supports V8.x of the Microblaze IP, + including exceptions, caches, and the floating point unit. A new + Microblaze demo has also been added to demonstrate the new Microblaze V8 + port layer. The demo application was created using V13.1 of the Xilinx + EDK, and includes a basic embedded web server that uses lwIP V1.4.0. + + The official FreeRTOS Fujitsu FM3 MB9A310 demo application has been + incorporated into the main FreeRTOS zip file download. Projects are + provided for both the IAR and Keil toolchains. + + + API additions: + + + xTaskGetIdleTaskHandle() has been added. + + xTaskGetTimerDaemonTaskHandle() has been added. + + pcTaskGetTaskName() has been added. + + vSemaphoreDelete() macro has been added to make it obvious how to delete + a semaphore. In previous versions vQueueDelete() had to be used. + + vTaskCleanUpResources() has been removed. It has been obsolete for a + while. + + portPOINTER_SIZE_TYPE has been introduced to prevent compiler warnings + being generated when the size of a pointer does not match the size of + the stack type. This will (has already) be used in new ports, but will + not be retrofitted to existing ports until the existing port itself is + updated. + + Other updates and news: + + + The core files have all been modified to tighten the coding standard even + further. These are style, not functional changes. + + All ARM7 port layers have been slightly modified to prevent erroneous + assert() failures when tasks are created and configASSERT() is defined. + + All ARM IAR projects have been updated to build with the latest V6.2.x + versions of the IAR Embedded Workbench for ARM tools (EWARM). This was + necessary due to a change in the way EWARM uses the CMSIS libraries. + + The PIC32 port layer has been updated in preparation for V2 of the C32 + compiler. + + The old Virtex-4 Microblaze demo has been marked as deprecated. Please + use the brand new Spartan-6 port and demo in its place. + + The bones of a new generic command interpreter is located in + FreeRTOS/Demo/Common/Utils/CommandInterpreter.c. This is still a work in + progress, and not documented. It is however already in use. It will be + documented in full when the projects that are already using it are + completed. + + A couple of new standard demos have been included. First, a version of + flop.c called sp_flop.c. This is similar to flop.c, but uses single + precision floats in place of double precision doubles. This allows the + for testing ports to processors that have only single precision floating + point units, and revert to using emulated calculations whenever a double + is used. Second, comtest_strings.c has been included to allow the test + of UART drivers when an entire string is transmitted at once. The + previous comtest.c only used single character transmission and reception. + + lwIP V1.4.0 is now included in the FreeRTOS/Demo/Common directory, and + used by a couple of new demos. + +Changes between V7.0.0 and V7.0.1 released May 13 2011 + + + Added a Fujitsu FM3 demo application for both the IAR and Keil tool + chains. + + Added a SmartFusion demo application for all of the IAR, Keil and + SoftConsole (GCC/Eclipse) tool chains. + + Updated the RX600 port and demo applications to take into account the + different semantics required when using the latest (V1.0.2.0) version of + the Renesas compiler. + + Modified the RX600 Ethernet driver slightly to make it more robust under + heavy load, and updated the uIP handling task to make use of the FreeRTOS + software timers. + + Slightly changed the PIC32 port layer to move an ehb instruction in line + with the recommendations of the MIPS core manual, and ensure 8 byte stack + alignment is truly always obtained. + + Changed the behaviour when tasks are suspended before the scheduler has + been started. Before, there needed to be at least one task that was not + in the suspended state. This is no longer the case. + +Changes between V6.1.1 and V7.0.0 released April 8 2011 + + FreeRTOS V7.0.0 is backward compatible with FreeRTOS V6.x.x + + Main changes: + + + Introduced a new software timer implementation. + + Introduced a new common demo application file to exercise the new timer + implementation. + + Updated the Win32/MSVC simulator project to include the new software timer + demo tasks and software timer tick hook test. Much simpler software timer + demonstrations are included in the demo projects for both of the new ports + (MSP430X with CCS4 and STM32 with TrueStudio). + + Various enhancements to the kernel implementation in tasks.c. These are + transparent to users and do not effect the pre-existing API. + + Added calls to configASSERT() within the kernel code. configASSERT() is + functionally equivalent to the standard C assert() macro, but does not + rely on the compiler providing assert.h. + + Other changes: + + + Updated the MSP430X IAR port and demo project to include support for the + medium memory model. + + Added a demo project for the MSP430X that targets the MSP430X Discovery + board and uses the Code Composer Studio 4 tools. This demo includes use + of the new software timer implementation. + + Added an STM32F100RB demo project that targets the STM32 Discovery Board + and uses the TrueStudio Eclipse based IDE from Atollic. + + Removed some compiler warnings from the PSoC demo application. + + Updated the PIC32 port layer to ensure the + configMAX_SYSCALL_INTERRUPT_PRIORITY constant works as expected no matter + what its value is (within the valid range set by the microcontroller + kernel). + + Updated the PIC24, dsPIC and PIC32 projects so they work with the latest + MPLAB compiler versions from Microchip. + + Various cosmetic changes to prepare for a standards compliance statement + that will be published after the software release. + + +Changes between V6.1.0 and V6.1.1 released January 14 2011 + + + Added two new Windows simulator ports. One uses the free Microsoft Visual + Studio 2010 express edition, and the other the free MingW/Eclipse + environment. Demo projects are provided for both. + + Added three demo projects for the PSoC 5 (CYAC5588). These are for the + GCC, Keil, and RVDS build tools, and all use the PSoC Creator IDE. + + Added a demo for the low power STM32L152 microcontroller using the IAR + Embedded Workbench. + + Added a new port for the MSP430X core using the IAR Embedded Workbench. + + Updated all the RX62N demo projects that target the Renesas Demonstration + Kit (RDK) to take into account the reversed LED wiring on later hardware + revisions, and the new J-Link debug interface DLL. + + Updated all the RX62N demo projects so the IO page served by the example + embedded web server works with all web browsers. + + Updated the Red Suite projects to work with the up coming Red Suite + release, and to use a more recent version of the CMSIS libraries. + + Added the traceTAKE_MUTEX_RECURSIVE_FAILED() trace macro. + + Removed the (pointless) parameter from the traceTASK_CREATE_FAILED() + trace macro. + + Introduced the portALT_GET_RUN_TIME_COUNTER_VALUE() macro to compliment + the already existing portGET_RUN_TIME_COUNTER_VALUE(). This allows for + more flexibility in how the time base for the run time statistics feature + can be implemented. + + Added a "cpsie i" instruction before the "svc 0" instruction used to start + the scheduler in each of the Cortex M3 ports. This is to ensure that + interrupts are globally enabled prior to the "svc 0" instruction being + executed in cases where interrupts are left disabled by the C start up + code. + + Slight optimisation in the run time stats calculation. + +Changes between V6.0.5 and V6.1.0 released October 6 2010 + + + Added xTaskGetTickCountFromISR() function. + + Modified vTaskSuspend() to allow tasks that have just been created to be + immediately suspended even when the kernel has not been started. This + allows them to effectively start in the Suspended state - a feature that + has been asked for on numerous occasions to assist with initialisation + procedures. + + Added ports for the Renesas RX62N using IAR, GCC and Renesas tool suites. + + Added a STM32F103 demo application that uses the Rowley tools. + + Under specific conditions xFreeBytesRemaining within heap_2.c could end up + with an incorrect value. This has been fixed. + + xTaskCreateGeneric() has a parameter that can be used to pass the handle + of the task just created out to the calling task. The assignment to this + parameter has been moved to ensure it is assigned prior to the newly + created having any possibility of executing. This takes into account the + case where the assignment is made to a global variable that is accessed by + the newly created task. + + Fixed some build time compiler warnings in various FreeTCPIP (based on + uIP) files. + + Fixed some build time compiler warnings in Demo/Common/Minimal/IntQueue.c. + +Changes between V6.0.4 and V6.0.5 released May 17 2010 + + + Added port and demo application for the Cortus APS3 processor. + +Changes between V6.0.3 and V6.0.4 released March 14 2010 + + + All the contributed files that were located in the Demo/Unsupported_Demos + directory have been removed. These files are instead now available in the + new Community Contributions section of the FreeRTOS website. See + https://www.FreeRTOS.org/RTOS-contributed-ports.html + + The project file located in the Demo/CORTEX_STM32F107_GCC_Rowley directory + has been upgraded to use V2.x of the Rowley Crossworks STM32 support + package. + + An initial Energy Micro EFM32 demo has been included. This will be + updated over the coming months to make better use of the low power modes + the EFM32 provides. + +Changes between V6.0.2 and V6.0.3 released February 26 2010 + + + SuperH SH7216 (SH2A-FPU) port and demo application added. + + Slight modification made to the default implementation of + pvPortMallocAligned() and vPortFreeAligned() macros so by default they + just call pvPortMalloc() and vPortFree(). The macros are only needed to + be defined when a memory protection unit (MPU) is being used - and then + only depending on other configuration settings. + +Changes between V6.0.1 and V6.0.2 released January 9th 2010 + + + Changed all GCC ARM 7 ports to use 0 as the SWI instruction parameter. + Previously the parameter was blank and therefore only an implicit 0 but + newer GCC releases do not permit this. + + Updated IAR SAM7S and SAM7X ports to work with IAR V5.40. + + Changed the stack alignment requirement for PIC32 from 4 bytes to 8 bytes. + + Updated prvListTaskWithinSingleList() is it works on processors where the + stack grows up from low memory. + + Corrected some comments. + + Updated the startup file for the RVDS LPC21xx demo. + +Changes between V6.0.0 and V6.0.1 released November 15th 2009 + + + Altered pxPortInitialiseStack() for all Cortex-M3 ports to ensure the + stack pointer is where the compiler expects it to be when a task first + starts executing. + + The following minor changes only effect the Cortex-M3 MPU port: + + + portRESET_PRIVILEGE() assembly macro updated to include a clobber list. + + Added prototypes for all the privileged function wrappers to ensure no + compile time warnings are generated no matter what the warning level + setting. + + Corrected the name of portSVC_prvRaisePrivilege to + portSVC_RAISE_PRIVILEGE. + + Added conditional compilation into xTaskGenericCreate() to prevent some + compilers issuing warnings when portPRIVILEGE_BIT is defined as zero. + + +Changes between V5.4.2 and V6.0.0 released October 16th 2009 + + FreeRTOS V6 is backward compatible with FreeRTOS V5.x. + + Main changes: + + + FreeRTOS V6 is the first version to include memory protection unit (MPU) + support. Two ports now exist for the Cortex M3, the standard FreeRTOS + which does not include MPU support, and FreeRTOS-MPU which does. + + xTaskCreateRestricted() and vTaskAllocateMPURegions() API functions added + in support of FreeRTOS-MPU. + + Wording for the GPL exception has been (hopefully) clarified. Also the + license.txt file included in the download has been fixed (the previous + version contained some corruption). + + Other changes: + + + New API function xPortGetFreeHeapSize() added to heap_1.c and heap_2.c. + + ARM7 GCC demo interrupt service routines wrappers have been modified to + call the C portion using an __asm statement. This prevents the function + call being inlined at higher optimisation levels. + + ARM7 ports now automatically set the THUMB bit if necessary when + setting up the initial stack of a task - removing the need for + THUMB_INTERWORK to be defined. This also allows THUMB mode and ARM mode + tasks to be mixed more easily. + + All ARM7/9 ports now have portBYTE_ALIGNMENT set to 8 by default. + + Various demo application project files have been updated to be up to date + with the latest IDE versions. + + The linker scripts used with command line GCC demos have been updated to + include an eh_frame section to allow their use with the latest Yagarto + release. Likewise the demo makefiles have been updated to include + command line options to reduce or eliminate the eh_frame section all + together. + + The definition of portBYTE_ALIGNMENT_MASK has been moved out of the + various memory allocation files and into the common portable.h header + file. + + Removed unnecessary use of portLONG, portSHORT and portCHAR. + + Added LM3Sxxxx demo for Rowley CrossWorks. + + Posix simulator has been upgraded - see the corresponding WEB page on the + FreeRTOS.org site. + + +Changes between V5.4.1 and V5.4.2 released August 9th 2009 + + + Added a new port and demo app for the Altera Nios2 soft core. + + Added LPC1768 demo for IAR. + + Added a USB CDC demo to all LPC1768 demos (Code Red, CrossWorks and IAR). + + Changed clock frequency of LPC1768 demos to 99MHz. + +Changes between V5.4.0 and V5.4.1 released July 25th 2009 + + + New hook function added. vApplicationMallocFailedHook() is (optionally) + called if pvPortMalloc() returns NULL. + + Additional casting added to xTaskCheckForTimeOut(). This prevents + problems that can arise should configUSE_16_BIT_TICKS be set to 1 on a + 32 bit architecture (which would probably be a mistake, anyway). + + Corrected the parameter passed to NVIC_SetPriority() to set the MAC + interrupt priority in both LPC1768 demos. + + Decreased the default setting of configMINIMAL_STACK_SIZE in the PIC32 + demo application to ensure the heap space was not completely consumed + before the scheduler was started. + +Changes between V5.3.1 and V5.4.0 released July 13th 2009 + + + Added Virtex5 / PPC440 port and demos. + + Replaced the LPC1766 Red Suite demo with an LPC1768 Red Suite demo. The + original demo was configured to use engineering samples of the CPU. The + new demo has an improved Ethernet driver. + + Added LPC1768 Rowley demo with zero copy Ethernet driver. + + Reworked byte alignment code to ensure 8 byte alignment works correctly. + + Set configUSE_16_BIT_TICKS to 0 in the PPC405 demo projects. + + Changed the initial stack setup for the PPC405 to ensure the small data + area pointers are setup correctly. + +Changes between V5.3.0 and V5.3.1 released June 21st 2009 + + + Added ColdFire V1 MCF51CN128 port and WEB server demo. + + Added STM32 Connectivity Line STM32107 Cortex M3 WEB server demo. + + Changed the Cortex M3 port.c asm statements to __asm so it can be + compiled using Rowley CrossWorks V2 in its default configuration. + + Updated the Posix/Linux simulator contributed port. + +Changes between V5.2.0 and V5.3.0 released June 1st 2009 + + Main changes: + + + Added new (optional) feature that gathers statistics on the amount of CPU + time used by each task. + + Added a new demo application for the Atmel AT91SAM3U Cortex-M3 based + microcontroller. + + Added a new demo application for the NXP LPC1766 Cortex-M3 based + microcontroller. + + Added a contributed port/demo that allows FreeRTOS to be 'simulated' in a + Linux environment. + + Minor changes: + + Updated the Stellaris uIP WEB server demos to include the new run time + statistics gathering feature - and include a served WEB page that + presents the information in a tabular format. + + Added in the lwIP port layer for the Coldfire MCF52259. + + Updated the CrossWorks LPC2368 WEB server to include an image in the + served content. + + Changed some of the timing in the initialisation of the LPC2368 MAC to + permit its use on all part revisions. + + Minor modifications to the core uIP code to remove some compiler warnings. + + Added xTaskGetApplicationTaskTag() function and updated the OpenWatcom + demo to make use of the new function. + + Added contributed demos for AVR32 AP7000, STM32 Primer 2 and STM32 using + Rowley Crossworks. + + Heap_1.c and Heap_2.c used to define structures for the purpose of data + alignment. These have been converted to unions to save a few bytes of + RAM that would otherwise be wasted. + + Remove the call to strncpy() used to copy the task name into the TCB when + the maximum task name is configured to be 1 byte long. + +Changes between V5.1.2 and V5.2.0 released March 14th 2009 + + + Optimised the queue send and receive functions (also used by semaphores). + + Replaced the standard critical sections used to protect BIOS calls in the + PC port to instead use scheduler locks. This is because the BIOS calls + always return with interrupts enabled. + + Corrected unclosed comments in boot.s. + +Changes between V5.1.1 and V5.1.2 released February 9th 2009 + + + Added NEC V850ES port and demo. + + Added NEC 78K0R port and demo. + + Added MCF52259 port and demo. + + Added the AT91SAM9XE port and demo. + + Updated the MCF52233 FEC driver to work around a silicon bug that + prevents the part auto negotiating some network parameters. + + Minor modifications to the MCF52233 makefile to permit it to be used + on Linux hosts. + + Updated the STM32 primer files to allow them to be built with the latest + version of the RIDE tools. + + Updated the threads.js Java script used for kernel aware debugging in + the Rowley CrossWorks IDE. + + +Changes between V5.1.0 and V5.1.1 released November 20, 2008 + + + Added Coldfire MCF52233 WEB server demo using GCC and Eclipse. + + Added IAR MSP430 port and demo. + + Corrected several compiler time issues that had crept in as tool versions + change. + + Included FreeRTOS-uIP - a faster uIP. This is not yet complete. + +Changes between V5.0.4 and V5.1.0 released October 24, 2008 + + + Added a new port and demo application for the ColdFire V2 core using the + CodeWarrior development tools. + + Replaced the ARM7 demo that used the old (and now no longer supported) + Keil compiler with a new port that uses the new Keil/RVDS combo. + + Stack overflow checking now works for stacks that grow up from low + memory (PIC24 and dsPIC). + + BUG FIX - set the PIC32 definition of portSTACK_GROWTH to the correct + value of -1. + + MSP430 port layers have been updated to permit tasks to place the + microcontroller into power down modes 1 to 3. The demo applications have + likewise been updated to demonstrate the new feature. + + Replaced the two separate MSP430/Rowley port layers with a single and more + flexible version. + + Added more contributed ports, including ports for NEC and SAM9 + microcontrollers. + + Changed the linker script used in the LPC2368 Eclipse demo. + +Changes between V5.0.3 and V5.0.4 released September 22, 2008 + + + Completely re-written port for ColdFire GCC. + + Bug fix: All Cortex M3 ports have a minor change to the code that sets + the pending interrupt. + + Some header files require that FreeRTOS.h be included prior to their + inclusion. #error message have been added to all such header file + informing users to the cause of the compilation error should the headers + not be included in the correct order. + +Changes between V5.0.2 and V5.0.3 released July 31, 2008 + + Changes relating to the Cortex M3: + + + Added configMAX_SYSCALL_INTERRUPT_PRIORITY usage to all the Cortex M3 + ports and demos. See the port documentation pages on the FreeRTOS.org + WEB site for full usage information. + + Improved efficiency of Cortex M3 port even further. + + Ensure the Cortex M3 port works no matter where the vector table is + located. + + Added the IntQTimer demo/test tasks to a demo project for each CM3 port + (Keil, GCC and IAR) to test the new configMAX_SYSCALL_INTERRUPT_PRIORITY + functionality. + + Added the mainINCLUDE_WEB_SERVER definition to the LM3SXXXX IAR and Keil + projects to allow the WEB server to be conditionally excluded from the + build and therefore allow use of the KickStart (code size limited) + compiler version. + + Other changes: + + + Moved the PIC24 and dsPIC versions of vPortYield() from the C file to + an assembly file to allow use with all MPLAB compiler versions. This also + allows the omit-frame-pointer optimisation to be turned off. + +Changes between V5.0.0 and V5.0.2 released May 30, 2008 + + + Updated the PIC32 port to allow queue API calls to be used from + interrupts above the kernel interrupt priority, and to allow full + interrupt nesting. Task stack usages has also been reduced. + + Added a new PowerPC port that demonstrates how the trace macros can be + used to allow the use of a floating point co-processor. The + traceTASK_SWITCHED_OUT() and traceTASK_SWITCHED_INT() macros are used to + save and restore the floating point context respectively for those tasks + that actually use floating point operations. + + BUG FIX: The first PPC405 port contained a bug in that it did not leave + adequate space above the stack for the backchain to be saved when a task + started to execute for the first time. + + Updated queue.c to add in the means to allow interrupt nesting and for + queue API functions to be called from interrupts that have a priority + above the kernel priority. This is only supported on PIC32 ports thus + far. + + Fixed the compiler warnings that were generated when the latest version + of WinAVR was used. + + Remove all inline usage of 'inline' from the core kernel code. + + Added the queue registry feature. The queue registry is provided as a + means for kernel aware debuggers to locate queue definitions. It has no + purpose unless you are using a kernel aware debugger. The queue registry + will only be used when configQUEUE_REGISTRY_SIZE is greater than zero. + + Added the ST Cortex-M3 drivers into the Demo/Common/Drivers directory to + prevent them from having to be included in multiple demos. + + Added a Keil STM32 demo application. + + Changed the blocktim.c test files as it is no longer legitimate for all + ports to call queue API functions from within a critical section. + + Added the IntQueue.c test file to test the calling of queue API functions + from different interrupt priority levels, and test interrupt nesting. + +Changes between V5.0.0 and V5.0.1 + + + V5.0.1 was a customer specific release. + +Changes between V4.8.0 and V5.0.0 released April 15, 2008 + + *** VERY IMPORTANT INFORMATION ON UPGRADING TO FREERTOS.ORG V5.0.0 *** + + The parameters to the functions xQueueSendFromISR(), xQueueSendToFrontFromISR(), + xQueueSendToBackFromISR() and xSemaphoreGiveFromISR() have changed. You must + update all calls to these functions to use the new calling convention! Your + compiler might not issue any type mismatch warnings! + + + Other changes: + + + Support added for the new Luminary Micro LM3S3768 and LM3S3748 Cortex-M3 + microcontrollers. + + New task hook feature added. + + PowerPC demo updated to use version 10.1 of the Xilinx EDK. + + Efficiency gains within the PIC32 port layer. + +Changes between V4.7.2 and V4.8.0 released March 26 2008 + + + Added a Virtex4 PowerPC 405 port and demo application. + + Added optional stack overflow checking and new + uxTaskGetStackHighWaterMark() function. + + Added new xQueueIsQueueEmptyFromISR(), xQueueIsQueueFullFromISR() and + uxQueueMessagesWaitingFromISR() API functions. + + Efficiency improvements to the Cortex-M3 port layer. NOTE: This + requires that an SVC handler be installed in the application. + + Efficiency improvements to the queue send and receive functions. + + Added new trace macros. These are application definable to provide + a flexible trace facility. + + Implemented the configKERNEL_INTERRUPT_PRIORITY within the Keil Cortex + M3 port layer (bringing it up to the same standard as the IAR and GCC + versions). + + Ports that used the arm-stellaris-eabi-gcc tools have been converted to + use the arm-non-eabi-gcc tools. + +Changes between V4.7.1 and V4.7.2 released February 21, 2008 + + + Added Fujitsu MB91460 port and demo. + + Added Fujitsu MB96340 port and demo. + + Tidied up the capitalisation of include files to facilitate builds on + Linux hosts. + + Removed some redundant casting that was generating warnings - but was + included to remove warnings on other compilers. + +Changes between V4.7.0 and V4.7.1 released February 3, 2008 + + + Updated all IAR ARM projects to use V5.11 of the IAR Embedded Workbench + for ARM. + + Introduced recursive semaphore feature. + + Updated LPC2368 demos to take into account silicon bugs in old chip + revisions. + + Updated STR9 uIP port to manually set the net mask and gateway addresses. + + Updating demos to allow more to run with the co-operative scheduler. + + Fixed co-operative scheduler behaviour upon the occurrence of a tick + interrupt while the scheduler was suspended. + + Updated documentation contained within semphr.h. + + ARM7 GCC ports no longer use the IRQ attribute. + +Changes between V4.6.1 and V4.7.0 released December 6, 2007 + + + Introduced the counting semaphore macros and demo source files. The + Open Watcom PC project has been updated to include the new demo. See + the online documentation for more information. + + Introduced the 'alternative' queue handling API and demo source files. + The Open Watcom PC project has been updated to include the new demo + source files. See the online documentation for more information. + + Added AT91SAM7X Eclipse demo project. + + Added the STM32 primer demo project for the GCC compiler and Ride IDE. + + Removed the .lock files that were mistakenly included in the V4.6.1 + eclipse workspaces. + +Changes between V4.6.0 and V4.6.1 released November 5 2007 + + + Added support for the MIPS M4K based PIC32. + + Added 'extern "C"' to all the header files to facilitate use with C++. + +Changes between V4.5.0 and V4.6.0 released October 28 2007 + + + Changed the method used to force a context switch within an ISR for the + ARM7/9 GCC ports only. The portENTER_SWITCHING_ISR() and + portEXIT_SWITCHING_ISR() macros are no longer supported. This is to + ensure correct behaviour no matter which GCC version is used, with or + without the -fomit-frame-pointer option, and at all optimisation levels. + + Corrected the prototype for xQueueGenericSend() within queue.h. + +Changes between V4.4.0 and V4.5.0 released September 17 2007 + + + Added the xQueueSendToFront(), xQueueSendToBack() and xQueuePeek() + functionality. These should now be used in preference to the old + xQueueSend() function - which is maintained for backward compatibility. + + Added Mutex functionality. The behaviour of mutexes is subtly different + to the already existing binary semaphores as mutexes automatically + include a priority inheritance mechanism. + + Added the GenQTest.c and QPeek.c to test and demonstrate the behaviour + of the new functionality. + + Updated the LM3Sxxxx and PC ports to include the new GenQTest.c and + QPeek.c files. + + Updated the GCC port for the Cortex M3 to include the + configKERNEL_INTERRUPT_PRIORITY functionality. This was previously only + included in the IAR port. + + Optimised the GCC and IAR port layer code - specifically the context + switch code. + + Consolidated the LM3Sxxxx EK demos for all development tools into a + single project that automatically detects which version of the EK the + application is executing on. + + Added Eclipse support for LM3Sxxxx evaluation kits. + + Added Eclipse support for the Keil LPC2368 evaluation kit. + + Added the Demo/Drivers directory to hold code that is common to multiple + demo application projects. + + Included some minor bug fixes in the uIP 1.0 code. + + Added an lwIP demo for the STR9 - thanks ST for assistance. + + Updated the AVR32 port to ensure correct behaviour with full compiler + optimisation. + + Included binaries for OpenOCD FTDI and parallel port interfaces. + +Changes between V4.4.0 and V4.3.1 released July 31, 2007 + + + Added AVR32 UC3B demo application. + + Updated AVR32 UC3A port and demo applications. + + Added IAR lwIP demo for AVR32 UC3A. + + Updated listGET_OWNER_OF_NEXT_ENTRY() to assist compiler optimisation + (thanks Niu Yong for making the suggestion). + + Added xTaskGetSchedulerState() API function. + + BUG FIX: Corrected behaviour when tasks that are blocked indefinitely + have their block time adjusted (within xQueueSend() and xQueueReceive()), + and are the subject of a call the vTaskResume() when they are not + actually in the Suspended state (thanks Dan Searles for reporting the + issues). + + +Changes between V4.3.0 and V4.3.1 released June 11, 2007 + + + Added STMicroelectronics STM32 Cortex-M3 demo application. + + Updated ustdlib.c for the GCC LM3S6965 demo. + +Changes between V4.2.1 and V4.3.0 released June 5, 2007 + + + Introduced configKERNEL_INTERRUPT_PRIORITY to the IAR Cortex-M3, PIC24 + and dsPIC ports. See the LM3S6965 and PIC24 demo application + documentation pages for more information. + + Updated the PIC24 and dsPIC demos to build with V3.0 of the PIC30 GCC + tools, and changed the demo applications. + + Added demos for the new Ethernet and CAN enabled Luminary Micro Stellaris + microcontrollers. + + Corrected bug in uIP the demos that prevented frames of approximately 1480 + bytes and over from being transmitted. + + Included the LPC2368/uIP/Rowley demo into the main FreeRTOS.org + download. + + Update to WizC PIC18 port to permit its use with version 14 of the + compiler. Thanks Marcel! + +Changes between V4.2.1 and V4.2.0 released April 2, 2007 + + + Added AVR32 AT32UC3A ports for GCC and IAR. + + Added -fomit-frame-pointer option to lwIP SAM7X demo makefile. + + Moved location of call to LCD_Init() in STR9 demo to ensure it is only + called after the scheduler has been started. + +Changes between V4.1.3 and V4.2.0 released February 8, 2007 + + + Changes to both task.c and queue.c as a result of testing performed on + the SafeRTOS code base. + + Added Cortex-M3 LM3S811 demos for GCC and IAR tools. + +Changes between V4.1.2 and V4.1.3 released November 19, 2006 + + + Added STR750 ARM7 port using the Raisonance RIDE/GCC tools. + + Added -fomit-frame-pointer option to Rowley ARM7 demos as work around + to GCC bug at some optimisation levels. + + Altered the way the heap is defined in the LM3S811 Keil demo to prevent + the RAM usage from counting toward the code size limit calculation. + + CO-ROUTINE BUG FIX: Removed the call to prvIsQueueEmpty from within + xQueueCRReceive as it exited with interrupts enabled. Thanks Paul Katz. + + Tasks that block on events with a timeout of portMAX_DELAY are now + blocked indefinitely if configINCLUDE_vTaskSuspend is defined. + Previously portMAX_DELAY was just the longest block time possible. This + is still the case if configINCLUDE_vTaskSuspend is not defined. + + Minor changes to some demo application files. + +Changes between V4.1.1 and V4.1.2 released October 21, 2006 + + + Added 16bit PIC ports and demos. + + Added STR750 port and demo. + + +Changes between V4.1.0 and V4.1.1 released September 24, 2006 + + + Added the Luminary Micro Stellaris LM3S811 demo application. + +Changes between V4.0.5 and V4.1.0 released August 28, 2006 + + + Prior to V4.1.0, under certain documented circumstances, it was possible + for xQueueSend() and xQueueReceive() to return without having completed + and without their block time expiring. The block time effectively + stated a maximum block time, and the return value of the function needed + to be checked to determine the reason for returning. This is no longer + the case as the functions will only return once the block time has + expired or they are able to complete their operation. It is therefore no + longer necessary to wrap calls within loops. + + Changed the critical section handling in the IAR AVR port to correct the + behaviour when used with later compiler versions. + + Added the LPC2138 CrossWorks demo into the zip file. Previously this was + only available as a separate download. + + Modified the AVR demo applications to demonstrate the use of co-routines. + +Changes between V4.0.4 and V4.0.5 released August 13, 2006 + + + Introduced API function xTaskResumeFromISR(). Same functionality as + xTaskResume(), but can be called from within an interrupt service routine. + + Optimised vListInsert() in the case when the wake time is the maximum + tick count value. + + Bug fix: The 'value' of the event list item is updated when the priority + of a task is changed. Previously only the priority of the TCB itself was + changed. + + vTaskPrioritySet() and vTaskResume() no longer use the event list item. + This has not been necessary since V4.0.1 when the xMissedYield handling + was added. + + Lowered the PCLK setting on the ARM9 STR9 demo from 96MHz to 48MHz. + + When ending the scheduler - do not try to attempt a context switch when + deleting the current task. + + SAM7X EMAC drivers: Corrected the Rx frame length mask when obtaining + the length from the rx descriptor. + + +Changes between V4.0.3 and V4.0.4 released June 22, 2006 + + + Added a port and demo application for the STR9 ARM9 based processors from + ST. + + Slight optimisation to the vTaskPrioritySet() function. + + Included the latest uIP version (1.0) in the demo/common/ethernet + directory. + +Changes between V4.0.2 and V4.0.3 released June 7, 2006 + + + Added a port and demo application for the Cortex-M3 target using the IAR + development tools. + + The ARM Cortex-m3 Rowley projects have been updated to use V1.6 of the + CrossStudio tools. + + The heap size defined for the lwIP Rowley demo has been reduced so that + the project will link correctly when using the command line GCC tools + also. The makefile has also been modified to allow debugging. + + The lwIP Rowley demo not includes a 'kernel aware' debug window. + + The uIP Rowley project has been updated to build with V1.6 of CrossWorks. + + The second set of tasks in the blockQ demo were created the wrong way + around (inconsistent to the description in the file). This has been + corrected. + +Changes between V4.0.1 and V4.0.2 released May 28, 2006 + + + Port and demo application added for the Tern Ethernet Engine controller. + + Port and demo application added for MC9S12 using GCC, thanks to + Jefferson "imajeff" Smith. + + The function vTaskList() now suspends the scheduler rather than disabling + interrupts during the creation of the task list. + + Allow a task to delete itself by passing in its own handle. Previously + this could only be done by passing in NULL. + + Corrected the value passed to the WDG_PeriodValueConfig() library + function in the STR71x demo. + + The tick hook function is now called only within a tick isr. Previously + it was also called when the tick function was called during the scheduler + unlocking process. + + The EMAC driver in the SAM7X lwIP demo has been made more robust as per + the thread: https://sourceforge.net/forum/message.php?msg_id=3714405 + + In the PC ports: Add function prvSetTickFrequencyDefault() to set the + DOS tick back to its proper value when the scheduler exits. Thanks + Raynald! + + In the Borland x86 ports there was a mistake in the portFIRST_CONTEXT + macro where the BP register was not popped from the stack correctly. The + BP value would never get used so this did not cause a problem, but it has + been corrected all the same. + + +Changes between V4.0.0 and V4.0.1 released April 7 2006 + + + Improved the ARM CORTEX M3 ports so they now only have to service + pendSV interrupts. + + Added a Luminary Micro port and demo for use with Rowley CrossWorks. + + Added the xMissedYield handling to tasks.c. + +Changes between V3.2.4 and V4.0.0 + + Major changes: + + + Added new RTOS port for Luminary Micros ARM CORTEX M3 microcontrollers. + + Added new co-routine functionality. + + Other kernel changes: + + + An optional tick hook call is now included in the tick function. + + Introduced the xMiniListItem structure and removed the list pxHead + member in order to reduce RAM usage. + + Added the following definitions to the FreeRTOSConfig.h file included + with every port: + configUSE_TICK_HOOK + configUSE_CO_ROUTINES + configMAX_CO_ROUTINE_PRIORITIES + + The volatile qualification has been changed on the list members to allow + the task.c code to be tidied up a bit. + + The scheduler can now be started even if no tasks have been created! + This is to allow co-routines to run when there are no tasks. + + A task being woken by an event will now preempt the currently running task + even if its priority is only equal to the currently running task. + + Port and demo application changes: + + + Updated the WinAVR demo to compile with the latest version of WinAVR + with no warnings generated. + + Changed the WinAVR makefile to make chars signed - needed for the + co-routine code if BaseType_t is set to char. + + Added new demo application file crflash.c. This demonstrates co-routine + functionality including passing data between co-routines. + + Added new demo application file crhook.c. This demonstrates co-routine + and tick hook functionality including passing data between and ISR and + a co-routine. + + Some NOP's were missing following stmdb{}^ instructions in various ARM7 + ports. These have been added. + + Updated the Open Watcom PC demo project to include the crflash and crhook + demo co-routines as an example of their use. + + Updated the H8S demo to compile with the latest version of GCC. + + Updated the SAM7X EMAC drivers to take into account the hardware errata + regarding lost packets. + + Changed the default MAC address used by some WEB server demos as the + original addresses used was not liked by some routers. + + Modified the SAM7X/IAR startup code slightly to prevent it hanging on + some systems when the code is executed using a j-link debugger. The + j-link macro file configures the PLL before the code executes so + attempting to configure it again in the startup code was causing a + problem for some user. Now a check is performed first to see if the + PLL is already set up. + + GCC port now contain all assembler code in a single asm block rather than + individual blocks as before. + + GCC LPC2000 code now explicitly uses R0 rather than letting the assembler + choose the register to use as a temporary register during the context + switch. + + Added portNOP() macro. + + The compare match load value on LPC2000 ports now has 1 added to correct + the value used. + + The minimal stack depth has been increased slightly on the WIZC PIC18 + port. + +Changes between V3.2.3 and V3.2.4 + + + Modified the GCC ARM7 port layer to allow use with GCC V4.0.0 and above. + Many thanks to Glen Biagioni for the provided update. + + Added a new Microblaze port and demo application. + + Modified the SAM7X EMAC demo to default to use the MII interface rather + than the RMII interface. + + Modified the startup sequence of the SAM7X demo slightly to allow the + EMAC longer to auto negotiate. + +Changes between V3.2.2 and V3.2.3 + + + Added MII interface support to the SAM7X EMAC peripheral driver. + Previously versions worked with the RMII interface only. + + Added command line GCC support to the SAM7X lwIP demo. Previously the + project could only be built using the CrossWorks IDE. Modifications to + this end include the addition of a standard makefile and linker script to + the download, and some adjustments to the stacks allocated to each task. + + Changed the page returned by the lwIP WEB server demo to display the + task status table rather than the TCP/IP statistics. + + Corrected the capitalisation of some header file includes and makefile + dependencies to facilitate use on Linux host computers. + + The various LPC2000 ports had a mistake in the timer setup where the + prescale value was written to T0_PC instead of T0_PR. This would have + no effect unless a prescale value was actually required. This has been + corrected. + +Changes between V3.2.1 and V3.2.2 - Released 23 September, 2005 + + + Added an IAR port for the Philips LPC2129 + + The Atmel ARM7 IAR demo project files are now saved in the IAR Embedded + Workbench V4.30a format. + + Updated the J-Link macro file included with the SAM7X uIP demo project + to allow the demo board to be reset over the J-Link. + +Changes between V3.2.0 and V3.2.1 - Released 1 September, 2005 + + + Added lwIP demo for AT91SAM7X using Rowley tools. + + Added uIP demo for AT91SAM7X using IAR tools. + + Added function xTaskGetCurrentTaskHandle(). + + Renamed events.h to mevents.h to prevent it conflicting with the events.h + generated automatically by the HCS12 processor expert utility. events.h + is only used by the PC demo application. + + Both PIC18 ports now initialise the TBLPTRU to 0 as this is the value + expected by the compiler, and the compilers do not write to this + register. + + The HCS12 banked model demo now creates the 'suicide' tasks immediately + prior to starting the scheduler. These tasks should be the last tasks to + get started in order for the test to function correctly. + +Changes between V3.1.1 and V3.2.0 - Released 29 June, 2005 + + V3.2.0 introduces two new MSP430 ports and corrects a minor kernel + issues. Thanks to Ares.qi for his input. + + + Added two MSP430 ports that use the Rowley CrossWorks development tools. + One port just mirrors the existing GCC port. The other port was provided + by Milos Prokic. Thanks! + + V3.2.0 corrects the behavior when vTaskPrioritySet() or vTaskResume() + are called while the scheduler is locked (by a call to + vTaskSuspendAll()). When this is done the subject task now starts to + execute immediately when the scheduler is unlocked if it has the highest + priority that is ready to run. Previously there was a possibility that + the task would not run until the next RTOS tick or call to portYIELD(). + + Another similar small correction ensures that in the case where more than + one task is blocked on a semaphore or queue, the task with the highest + priority is guaranteed to be unblocked first. + + Added a couple of more test tasks to the PC demo which cover the points + above. + +Changes between V3.1.0 and V3.1.1 - Released 21st June, 2005 + + This release updates the HCS12 port. The common kernel code + remains unchanged. + + + Updated the HCS12 port to support banking and introduced a demo + application for the MC9S12DP256. The new demo application is + located in the Demo/HCS12_CodeWarrior_banked directory. + + The name of the directory containing the MC9S12F32 demo application + has been changed to Demo/HCS12_CodeWarrior_small (as in 'small' + memory model). + + MC9S12F32 demo updated slightly to use the PLL. The CPU speed for the + demo application is now 24MHz. Previously it was 8MHz. + + The demo application file Demo/Common/Minimal/death.c has a slight + alteration to prevent it using floating point variables. + + +Changes between V3.0.0 and V3.1.0 - Released 11th June, 2005 + + + Added new ports for ST Microsystems STR71x, and Freescale HCS12 + microcontrollers. Currently the HCS12 port is limited to the small + memory model. Large memory models will be supported in the next + release. + + PIC18 wizC port updated. Thanks to Marcel van Lieshout for his + continuing contribution. + + The accuracy of the AVR port timer setup has been improved. Thanks to + Thomas Krutmann for this contribution. + + Added a new conditional compilation macro configIDLE_SHOULD_YIELD. + See the WEB documentation for details. + + Updated the CrossWorks uIP demo to build with V1.4 of CrossWorks. + + Slight modification to the SAM7 release build configuration to correct + an include path definition. + + Updated the MPLAB PIC18 documentation to provide extra details on linker + file configuration. + +Changes between V3.0.0 and V2.6.1 - Released 23rd April, 2005 + + V3.0.0 includes many enhancements, so this history list is broken into + subsections as follows: + + API changes + New ports + Directory name changes + Kernel and miscellaneous changes changes + + - API changes + + + Each port now defines BaseType_t as the data type that is most + efficient for that architecture. The type BaseType_t is used + extensively in API calls necessitating the following changes to the + FreeRTOS API function prototypes. + + See the "New for V3.0.0" section of the FreeRTOS online + documentation for full details of API changes. + + - New ports + + + The AT91FR40008 ARM7 port contributed by John Feller is now included + in the download (thanks John!). + + The PIC18 port for the wizC/fedC compiler contributed by Marcel van + Lieshout is now included in the download (thanks Marcel!). + + The IAR port for the AVR microcontroller has been upgraded to V3.0.0 + and is now a supported port. + + - Directory name changes + + For consistency, and to allow integration of the new ports, the + following directory names have been changed. + + + The source/portable/GCC/ARM7 directory has been renamed + source/portable/GCC/ARM7_LPC2000 so it is compatible with the naming + of other GCC ARM7 ports. + + The Demo/PIC directory has been renamed Demo/PIC18_MPLAB to + accommodate the wizC/fedC PIC port. + + The demo applications for the two AVR ports no longer share the same + directory. The WinAVR demo is in the Demo/AVR_ATMega323_WinAVR + directory and the IAR port in the Demo/AVR_ATMega323_IAR directory. + + + - Kernel and miscellaneous changes changes + + See the "New for V3.0.0" section of the FreeRTOS online + documentation for more information. + + + Previously 'portmacro.h' contained some user editable definitions + relating to the user application, and some fixed definitions relating + specifically to the port being used. The application specific + definitions have been removed from 'portmacro.h' and placed inside a + new header file called 'FreeRTOSConfig.h'. 'portmacro.h' should now + never be modified by the user. A 'FreeRTOSConfig.h' is now included + in each of FreeRTOS/Demo subdirectories - as it's settings relate to + the demo application rather than being specific to the port. + + Introduced configUSE_IDLE_HOOK in idle task. + + The idle task will yield when another idle priority task is ready to + run. Previously the idle task would run to the end of its time slice + regardless. + + The idle task is now created when the scheduler is started. This + requires less stack than the previous scheme where it was created upon + creation of the first application task. + + The function usPortCheckFreeStackSpace() has been renamed + usTaskCheckFreeStackSpace() and moved from the portable layer to + tasks.c. + + Corrected spelling of portMINMAL_STACK_SIZE to portMINIMAL_STACK_SIZE. + + The portheap.c file included with the AVR port has been deleted. The + AVR demo now uses the standard heap1 sample memory allocator. + + The GCC AVR port is now build using the standard make utility. The + batch files used previously have been deleted. This means a recent + version of WinAVR is required in order to create a binary suitable for + source level debugging. + + vTaskStartScheduler() no longer takes the configUSE_PREEMPTION + constant as a parameter. Instead the constant is used directly within + tasks.c and no parameter is required. + + The header file 'FreeRTOS.h' has been created and is used to include + 'projdefs.h', 'FreeRTOSConfig.h' and 'portable.h' in the necessary + order. FreeRTOS.h can now be included in place of these other + headers. + + The header file 'errors.h' has been deleted. The definitions it + contained are now located within 'projdefs.h'. + + pvPortMalloc() now takes a size_t parameter as per the ANSI malloc(). + Previously an unsigned short was used. + + When resuming the scheduler a yield is performed if either a tick has + been missed, or a task is moved from the pending ready list into a + ready list. Previously a yield was not performed on this second + condition. + + In heap1.c an overflow check has been added to ensure the next free + byte variable does not wrap around. + + Introduced the portTASK_FUNCTION() and portTASK_FUNCTION_PROTO() + macros. + + The MPLAB PIC port now saved the TABLAT register in interrupt service + routines. + +Changes between V2.6.0 and V2.6.1 - Released Feb 22, 2005 + + This version adds support for the H8 processor. + + Other changes: + + + tskMAX_TASK_NAME_LEN removed from the task.h header and added to each + individual portmacro.h file as portMAX_TASK_NAME_LEN. This allows RAM + limited ports to allocate fewer characters to the task name. + + AVR port - Replaced the inb() and outb() functions with direct memory + access. This allows the port to be built with the 20050414 build of + WinAVR. + + GCC LPC2106 port - removed the 'static' from the definition of + vNonPreemptiveTick() to allow the demo to link when using the cooperative + scheduler. + + GCC LPC2106 port - Corrected the optimisation options in the batch files + ROM_THUMB.bat, RAM_THUMB.bat, ROM_ARM.bat and RAM_ARM.bat. The lower case + -o is replaced by an uppercase -O. + + Tasks.c - The strcpy call has been removed when copying across the task + name into the TCB. + + Updated the trace visualisation to always be 4 byte aligned so it can be + used on ARM architectures. + + There are now two tracecon executables (that convert the trace file binary + into an ASCII file). One for big endian targets and one for little endian + targets. + + Added ucTasksDeleted variable to prevent vTaskSuspendAll() being called + too often in the idle task. + + SAM7 USB driver - Replaced the duplicated RX_DATA_BK0 in the interrupt + mask with the RX_DATA_BK1. + + +Changes between V2.5.5 and V2.6.0 - Released January 16, 2005 + + + Added the API function vTaskDelayUntil(). The demo app file + Demo/Common/Minimal/flash.c has been updated to demonstrate its use. + + Added INCLUDE_vTaskDelay conditional compilation. + + Changed the name of the Demo/ARM7_AtmelSAM7S64_IAR directory to + Demo/ARM7_AT91SAM7S64_IAR for consistency. + + Modified the AT91SAM7S USB driver to allow descriptors that have + a length that is an exact multiple of the FIFO to be transmitted. + +Changes between V2.5.4 and V2.5.5 - Released January 3, 2005 + + This version adds support for the Atmel SAM7 ARM7 microcontrollers + along with the IAR development tools. + + Other changes: + + + Renamed the Demo/ARM7 directory to Demo/ARM7_LPC2106_GCC. + + Renamed the Demo/ARM7_Keil directory to Demo/ARM7_LPC2129_Keil. + + Modified the Philips ARM7 serial interrupt service routines to only + process one interrupt per call. This seems to enable the ISR to + operate more quickly. + + Removed the 'far' keyword from the Open Watcom portable layer source + files. This allows their use with V1.3 of Open Watcom. + + Minor modifications to the SDCC build files to allow their use under + Linux. Thanks to Frieder Ferlemann for this contribution. + + Small change to sTaskCreate() to allow a context switch even when + pxCreatedTask is NULL. Thanks to Kamil for this contribution. + + inline keyword removed from vTaskSwitchContext() and VTaskIncrementTick() + definitions. + +Changes between V2.5.3 and V2.5.4 - Released Dec 1, 2004 + + This is an important maintenance release. + + The function cTaskResumeAll() has been modified so it can be used safely + prior to the kernel being initialised. This was an issue as + cTaskResumeAll() is called from pvPortMalloc(). Thanks to Daniel Braun + for highlighting this issue. + +Changes between V2.5.2 and V2.5.3 - Released Nov 2, 2004 + + The critical section handling functions have been changed for the GCC ARM7 + port. Some optimisation levels use the stack differently to others. This + means the interrupt flags cannot always be stored on the stack and are + instead now stored in a variable, which is then saved as part of the + tasks context. This allows the GCC ARM7 port to be used at all + optimisation levels - including -Os. + + Other minor changes: + + + MSP430 definition of usCriticalNesting now uses the volatile qualifier. + This is probably not required but added just in case. + +Changes between V2.5.1 and V2.5.2 - Released Oct 26, 2004 + + + Added the Keil ARM7 port. + + Slight modification to comtest.c to make the delay periods more random. + This creates a better test condition. + +Changes between V2.5.0 and V2.5.1 - Released Oct 9, 2004 + + + Added the MSP430 port. + + Extra comments added to the GCC ARM7 port.c and portISR.c files. + + The memory pool allocated within heap_1.c has been placed within a + structure to ensure correct memory alignment on 32bit systems. + + Within the GCC ARM7 serial drivers an extra check is made to ensure + the post to the queue was successful if then attempting immediately + retrieve the posted character. + + Changed the name of the constant portTICKS_PER_MS to portTICK_PERIOD_MS + as the old name was misleading. + + +Changes between V2.4.2 and V2.5.0 - Released Aug 12, 2004 + + The RTOS source code download now includes three separate memory allocation + schemes - so you can choose the most appropriate for your application. + These are found in the Source/Portable/MemMang directory. The demo + application projects have also been updated to demonstrate the new schemes. + See the "Memory Management" page of the API documentation for more details. + + + Added heap_1.c, heap_2.c and heap_3.c in the Source/Portable/MemMang + directory. + + Replaced the portheap.c files for each demo application with one of the + new memory allocation files. + + Updated the portmacro.h file for each demo application to include the + constants required for the new memory allocators: portTOTAL_HEAP_SIZE and + portBYTE_ALIGNMENT. + + Added a new test to the ARM7 demo application that tests the operation + of the heap_2 memory allocator. + + +Changes between V2.4.1 and V2.4.2 - Released July 14, 2004 + + + The ARM7 port now supports THUMB mode. + + Modification to the ARM7 demo application serial port driver. + +Changes between V2.4.0 and V2.4.1 - Released July 2, 2004 + + + Rationalised the ARM7 port version of portEXIT_CRITICAL() - + improvements provided by Bill Knight. + + Made demo serial driver more complete and robust. + + +Changes between V2.4.0 and V2.3.1 - Released June 30, 2004 + + + Added the first ARM7 port - thanks to Bill Knight for the assistance + provided. + + Added extra files to the Demo/Common/Minimal directory. These are + equivalent to their Demo/Common/Full counterparts but with the + calls to the functions defined in print.c removed. + + Added TABLAT to the list of registers saved as part of a PIC18 context. + +Changes between V2.3.0 and V2.3.1 - Released June 25, 2004 + + + Changed the way the vector table is defined to be more portable. + + Corrected the definitions of SPH and SPL in portmacro.s90. + The previous definitions prevented V2.3.0 operating if the iom323.h + header file was included in portmacro.s90. + +Changes between V2.2.0 and V2.3.0 - Released June 19, 2004 + + + Added an AVR port that uses the IAR compiler. + + Explicit use of 'signed' qualifier on plain char types. + + Modified the Open Watcom project files to use 'signed' as the + default char type. + + Changed odd calculation of initial pxTopOfStack value when + portSTACK_GROWTH < 0. + + Added inline qualifier to context switch functions within task.c. + Ports that do not support the (non ANSI) inline keyword have the + inline #define'd away in their respective portmacro.h files. + +Changes between V2.1.1 and V2.2.0 - Released May 18, 2004 + + + Added Cygnal 8051 port. + + PCLATU and PCLATH are now saved as part of the PIC18 context. This + allows function pointers to be used within tasks. Thanks to Javier + Espeche for the enhancement. + + Minor changes to demo application files to reduce stack usage. + + Minor changes to prevent compiler warnings when compiling the new port. + +Changes between V2.1.0 and V2.1.1 - Released March 12, 2004 + + + Bug fix - pxCurrentTCB is now initialised before the call to + prvInitialiseTaskLists(). Previously pxCurrentTCB could be accessed + while null during the initialisation sequence. Thanks to Giuseppe + Franco for the correction. + +Changes between V2.0.0 and V2.1.0 - Released Feb 29, 2004 + + V2.1.0 has significant reworks that greatly reduce the amount of time + the kernel has interrupts disabled. The first section of modifications + listed here must be taken into account by users. The second section + are related to the kernel implementation and as such are transparent. + + Section1 : + + + The typedef TickType_t has been introduced. All delay times should + now use a variable of type TickType_t in place of the unsigned long's + used previously. API function prototypes have been updated + appropriately. + + The configuration macro USE_16_BIT_TICKS has been introduced. If set + to 1 TickType_t is defined as an unsigned short. If set to 0 + TickType_t is defined as an unsigned long. See the configuration + section of the API documentation for more details. + + The configuration macro INCLUDE_vTaskSuspendAll is now obsolete. + + vTaskResumeAll() has been renamed cTaskResumeAll() as it now returns a + value (see the API documentation). + + ulTaskGetTickCount() has been renamed xTaskGetTickCount() as the type + it returns now depends on the USE_16_BIT_TICKS definition. + + cQueueReceive() must now >never< be used from within an ISR. Use the new + cQueueReceiveFromISR() function instead. + + Section 2: + + + A mechanism has been introduced that allows a queue to be accessed by + a task and ISR simultaneously. + + A "pending ready" queue has been introduced that enables interrupts to + be processed when the scheduler is suspended. + + The list implementation has been improved to provide faster item + removal. + + The scheduler now makes use of the scheduler suspend mechanism in places + where previously interrupts were disabled. + +Changes between V1.2.6 and V2.0.0 - Released Jan 31, 2004 + + + Introduced new API functions: + vTaskPriorityGet () + vTaskPrioritySet () + vTaskSuspend () + vTaskResume () + vTaskSuspendAll () + vTaskResumeAll () + + Added conditional compilation options that allow the components of the + kernel that are unused by an application to be excluded from the build. + See the Configuration section on the WEB site for more information (on + the API pages). The macros have been added to each portmacro.h file ( + sometimes called prtmacro.h). + + Rearranged tasks.c. + + Added demo application file dynamic.c. + + Updated the PC demo application to make use of dynamic.c. + + Updated the documentation contained in the kernel header files. + + Creating a task now causes a context switch if the task being created + has a higher priority than the calling task - assuming the kernel is + running. + + vTaskDelete() now only causes a context switch if the calling task is + the task being deleted. + +Changes between V1.2.5 and V1.2.6 - Released December 31, 2003 + + Barring the change to the interrupt vector (PIC port) these are minor + enhancements. + + + The interrupt vector used for the PIC master ISR has been changed from + 0x18 to 0x08 - where it should have always been. The incorrect address + still works but probably executes a number of NOP's before getting to the + ISR. + + Changed the baud rate used by the AVR demo application to 38400. This + has an error percentage of less than one percent with an 8MHz clock. + + Raised the priority of the Rx task in demo\full\comtest.c. This only + affects the Flashlite and PC ports. This was done to prevent the Rx + buffer becoming full. + + Reverted the Flashlite COM port driver back so it does not use the DMA. + The DMA appears to miss characters under stress. The Borland Flashlite + port was also calculating a register value incorrectly resulting in the + wrong DMA source address being used. The same code worked fine when + compiling with Open Watcom. Other minor enhancements were made to the + interrupt handling. + + Modified the PIC serial Rx ISR to check for and clear overrun errors. + Overrun errors seem to prevent any further characters being received. + + The PIC demo projects now have some optimisation switched on. + + +Changes between V1.2.4 and V1.2.5 + + Small fix made to the PIC specific port.c file described below. + + + Introduced portGLOBAL_INTERRUPT_FLAG definition to test the global + interrupt flag setting. Using the two bits defined within + portINITAL_INTERRUPT_STATE was causing the w register to get clobbered + before the test was performed. + +Changes between V1.2.3 and V1.2.4 + + V1.2.4 contains a release version of the PIC18 port. + An optional exception has been included with the GPL. See the licensing + section of www.FreeRTOS.org for details. + + + The function xPortInitMinimal() has been renamed to + xSerialPortInitMinimal() and the function xPortInit() has been renamed + to xSerialPortInit(). + + The function sSerialPutChar() has been renamed cSerialPutChar() and + the function return type changed to portCHAR. + + The integer and flop tasks now include calls to tskYIELD(), allowing + them to be used with the cooperative scheduler. + + All the demo applications now use the integer and comtest tasks when the + cooperative scheduler is being used. Previously they were only used with + the preemptive scheduler. + + Minor changes made to operation of minimal versions of comtest.c and + integer.c. + + The ATMega port definition of portCPU_CLOSK_HZ definition changed to + 8MHz base 10, previously it base 16. + + + +Changes between V1.2.2a and V1.2.3 + + The only change of any significance is to the license, which has changed + from the Open Software License to the GNU GPL. + + The zip file also contains a pre-release version of the PIC18 port. This + has not yet completed testing and as such does not constitute part of the + V1.2.3 release. It is still however covered by the GNU GPL. + + There are minor source code changes to accommodate the PIC C compiler. + These mainly involve more explicit casting. + + + sTaskCreate() has been modified slightly to make use of the + portSTACK_GROWTH macro. This is required for the PIC port where the + stack grows in the opposite direction to the other existing ports. + + prvCheckTasksWaitingTermination() has been modified slightly to bring + the decrementing of usCurrentNumberOfTasks within the critical section, + where it should have been since the creation of an eight bit port. + +Changes between V1.2.2 and V1.2.2a + + The makefile and buildcoff.bat files included with the AVR demo application + have been modified for use with the September 2003 build of WinAVR. No + source files have changed. + +Changes between V1.2.1 and V1.2.2 + + There are only minor changes here to allow the PC and Flashlite 186 ports + to use the Borland V4.52 compiler, as supplied with the Flashlite 186 + development kit. + + + Introduced a BCC directory under source\portable. This contains all the + files specific to the Borland compiler port. + + Corrected the macro naming of portMS_PER_TICK to portTICKS_PER_MS. + + Modified comtest.c to increase the rate at which the string is + transmitted and received on the serial port. The Flashlite 186 demo + app baud rate has also been increased. + + The values of the constants used in both integer.c files have been + increased to force the Borland compiler to use 32 bit values. The + Borland optimiser placed the previous values in 16 bit registers, and in + So doing invalidated the test. + +Changes between V1.2.0 and V1.2.1 + + This version includes some minor changes to the list implementation aimed + at improving the context switch time - with is now approximately 10% faster. + Changes include the removal of some null pointer assignment checks. These + were redundant where the scheduler uses the list functions, but means any + user application choosing to use the same list functions must now check + that no NULL pointers are passed as a parameter. + + The Flashlite 186 serial port driver has also been modified to use a DMA + channel for transmissions. The serial driver is fully functional but still + under development. Flashlite users may prefer to use V1.2.0 for now. + + Details: + + + Changed the baud rate for the ATMega323 serial test from 19200 to 57600. + + Use vSerialPutString() instead of single character puts in + Demo\Full\Comtest.c. This allows the use of the flashlite DMA serial + driver. Also the check variable only stops incrementing after two + consecutive failures. + + semtest.c creates four tasks, two of which operate at the idle priority. + The tasks that operate at the idle priority now use a lower expected + count than those running at a higher priority. This prevents the low + priority tasks from signalling an error because they have not been + scheduled enough time for each of them to count the shared variable to + the higher original value. + + The flashlite 186 serial driver now uses a DMA channel for transmissions. + + Removed the volatile modifier from the list function parameters. This was + only ever included to prevent compiler warnings. Now warnings are + removed by casting parameters where the calls are made. + + prvListGetOwnerOfNextEntry() and prvListGetOwnerOfHeadEntry() have been + removed from list.c and added as macros in list.h. + + usNumberOfItems has been added to the list structure. This removes the + need for a pointer comparison when checking if a list is empty, and so + is slightly faster. + + Removed the NULL check in vListRemove(). This makes the call faster but + necessitates any application code utilising the list implementation to + ensure NULL pointers are not passed. + + Renamed portTICKS_PER_MS definition to portMS_PER_TICK (milli seconds + per tick). This is what it always should have been. + +Changes between V1.01 and V1.2.0 + + The majority of these changes were made to accommodate the 8bit AVR port. + The scheduler workings have not changed, but some of the data types used + have been made more friendly to an eight bit environment. + + Details: + + + Changed the version numbering format. + + Added AVR port. + + Split the directory demo\common into demo\common\minimal and + demo\common\full. The files in the full directory are for systems with + a display (currently PC and Flashlite 186 demo's). The files in the + minimal directory are for systems with limited RAM and no display + (currently MegaAVR). + + Minor changes to demo application function prototypes to make more use + of 8bit data types. + + Within the scheduler itself the following functions have slightly + modified declarations to make use of 8bit data types where possible: + xQueueCreate(), + sQueueReceive(), + sQUeueReceive(), + usQueueMessageWaiting(), + sQueueSendFromISR(), + sSemaphoreTake(), + sSemaphoreGive(), + sSemaphoreGiveFromISR(), + sTaskCreate(), + sTaskMoveFromEventList(). + + Where the return type has changed the function name has also changed in + accordance with the naming convention. For example + usQueueMessageWaiting() has become ucQueueMessageWaiting(). + + The definition tskMAX_PRIORITIES has been moved from task.h to + portmacro.h and renamed portMAX_PRIORITIES. This allows different + ports to allocate a different maximum number of priorities. + + By default the trace facility is off, previously USE_TRACE_FACILITY + was defined. + + comtest.c now uses a pseudo random delay between sends. This allows for + better testing as the interrupts do not arrive at regular intervals. + + Minor change to the Flashlite serial port driver. The driver is written + to demonstrate the scheduler and is not written to be efficient. + + + +Changes between V1.00 and V1.01 + + These changes improve the ports. The scheduler itself has not changed. + + Improved context switch mechanism used when performing a context + switch from an ISR (both the tick ISR and the serial comms ISR's within + the demo application). The new mechanism is faster and uses less stack. + + The assembler file portasm.asm has been replaced by a header file + portasm.h. This includes a few assembler macro definitions. + + All saving and restoring of registers onto/off of the stack is now handled + by the compiler. This means the initial stack setup for a task has to + mimic the stack used by the compiler, which is different for debug and + release builds. + + Slightly changed the operation of the demo application, details below. + + Details: + + + portSWITCH_CONTEXT() replaced by vPortFirstContext(). + + pxPortInitialiseStack() modified to replicate the stack used by the + compiler. + + portasm.asm file removed. + + portasm.h introduced. This contains macro definitions for + portSWITCH_CONTEXT() and portFIRST_CONTEXT(). + + Context switch from ISR now uses the compiler generated interrupt + mechanism. This is done simply by calling portSWITCH_CONTEXT and leaving + the save/restore to compiler generated code. + + Calls to taskYIELD() during ISR's have been replaced by calling the + simpler and faster portSWITCH_CONTEXT(). + + The Flashlite 186 port now uses 186 instruction set (used to use 80x86 + instructions only). + + The blocking queue tasks within the demo application did not operate + quite as described. This has been corrected. + + The priority of the comtest Rx task within the demo application has been + lowered. Received characters are now processed (read from the queue) at + the idle priority, allowing low priority tasks to run evenly at times of + a high communications overhead. + + Prevent the call to kbhit() in main.c for debug builds as the debugger + seems to have problems stepping over the call. This if for the PC port + only. diff --git a/LICENSE.md b/LICENSE.md new file mode 100644 index 000000000..9cf106272 --- /dev/null +++ b/LICENSE.md @@ -0,0 +1,19 @@ +MIT License + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. diff --git a/License/license.txt b/License/license.txt deleted file mode 100644 index 1787b6ad1..000000000 --- a/License/license.txt +++ /dev/null @@ -1,399 +0,0 @@ -The FreeRTOS.org source code is licensed by the modified GNU General Public -License (GPL) text provided below. The FreeRTOS download also includes -demo application source code, some of which is provided by third parties -AND IS LICENSED SEPARATELY FROM FREERTOS.ORG. - -For the avoidance of any doubt refer to the comment included at the top -of each source and header file for license and copyright information. - -This is a list of files for which Richard Barry is not the copyright owner -and are NOT COVERED BY THE GPL. - - -1) Various header files provided by silicon manufacturers and tool vendors - that define processor specific memory addresses and utility macros. - Permission has been granted by the various copyright holders for these - files to be included in the FreeRTOS download. Users must ensure license - conditions are adhered to for any use other than compilation of the - FreeRTOS demo application. - -2) The uIP TCP/IP stack the copyright of which is held by Adam Dunkels. - Users must ensure the open source license conditions stated at the top - of each uIP source file is understood and adhered to. - -3) The lwIP TCP/IP stack the copyright of which is held by the Swedish - Institute of Computer Science. Users must ensure the open source license - conditions stated at the top of each lwIP source file is understood and - adhered to. - -4) All files contained within the FreeRTOS\Demo\CORTEX_LM3S102_GCC\hw_include - and FreeRTOS\Demo\CORTEX_LM3S316_IAR\hw_include directories. The - copyright of these files is owned by Luminary Micro. Permission has been - granted by Luminary Micro for these files to be included in the FreeRTOS - download. Users must ensure the license conditions stated in the EULA.txt - file located in the same directories is understood and adhered at all - times for all files in those directories. - -5) The files contained within FreeRTOS\Demo\WizNET_DEMO_TERN_186\tern_code, - which are slightly modified versions of code provided by and copyright to - Tern Inc. - -Errors and omissions should be reported to Richard Barry, contact details for -whom can be obtained from http://www.FreeRTOS.org. - - - - - -The GPL license text follows. - -An exception to this license exists that can be applied should you -wish to use FreeRTOS in a work that includes commercial or -proprietary code without being obliged to provide source code for the -proprietary components. See the licensing section of -http://www.FreeRTOS.org for full details. --------------------------------------------------------------------- - - - - GNU GENERAL PUBLIC LICENSE - Version 2, June 1991 - - Copyright (C) 1989, 1991 Free Software Foundation, Inc. - 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - Everyone is permitted to copy and distribute verbatim copies - of this license document, but changing it is not allowed. - - Preamble - - The licenses for most software are designed to take away your -freedom to share and change it. By contrast, the GNU General Public -License is intended to guarantee your freedom to share and change free -software--to make sure the software is free for all its users. This -General Public License applies to most of the Free Software -Foundation's software and to any other program whose authors commit to -using it. (Some other Free Software Foundation software is covered by -the GNU Library General Public License instead.) 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It is safest -to attach them to the start of each source file to most effectively -convey the exclusion of warranty; and each file should have at least -the "copyright" line and a pointer to where the full notice is found. - - - Copyright (C) - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - -Also add information on how to contact you by electronic and paper mail. - -If the program is interactive, make it output a short notice like this -when it starts in an interactive mode: - - Gnomovision version 69, Copyright (C) year name of author - Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. - This is free software, and you are welcome to redistribute it - under certain conditions; type `show c' for details. - -The hypothetical commands `show w' and `show c' should show the appropriate -parts of the General Public License. Of course, the commands you use may -be called something other than `show w' and `show c'; they could even be -mouse-clicks or menu items--whatever suits your program. - -You should also get your employer (if you work as a programmer) or your -school, if any, to sign a "copyright disclaimer" for the program, if -necessary. Here is a sample; alter the names: - - Yoyodyne, Inc., hereby disclaims all copyright interest in the program - `Gnomovision' (which makes passes at compilers) written by James Hacker. - - , 1 April 1989 - Ty Coon, President of Vice - -This General Public License does not permit incorporating your program into -proprietary programs. If your program is a subroutine library, you may -consider it more useful to permit linking proprietary applications with the -library. If this is what you want to do, use the GNU Library General -Public License instead of this License. - diff --git a/MISRA.md b/MISRA.md new file mode 100644 index 000000000..87ff4cbcd --- /dev/null +++ b/MISRA.md @@ -0,0 +1,145 @@ +# MISRA Compliance + +FreeRTOS-Kernel conforms to [MISRA C:2012](https://www.misra.org.uk/misra-c) +guidelines, with the deviations listed below. Compliance is checked with +Coverity static analysis version 2023.6.1. Since the FreeRTOS kernel is +designed for small-embedded devices, it needs to have a very small memory +footprint and has to be efficient. To achieve that and to increase the +performance, it deviates from some MISRA rules. The specific deviations, +suppressed inline, are listed below. + +Additionally, [MISRA configuration file](examples/coverity/coverity_misra.config) +contains project wide deviations. + +### Suppressed with Coverity Comments +To find the violation references in the source files run grep on the source code +with ( Assuming rule 8.4 violation; with justification in point 1 ): +``` +grep 'MISRA Ref 8.4.1' . -rI +``` + +#### Dir 4.7 +MISRA C:2012 Dir 4.7: If a function returns error information, then that error +information shall be tested. + +_Ref 4.7.1_ + - `taskENTER_CRITICAL_FROM_ISR` returns the interrupt mask and not any error + information. Therefore, there is no need test the return value. + +#### Rule 8.4 + +MISRA C:2012 Rule 8.4: A compatible declaration shall be visible when an +object or function with external linkage is defined. + +_Ref 8.4.1_ + - pxCurrentTCB(s) is defined with external linkage but it is only referenced + from the assembly code in the port files. Therefore, adding a declaration in + header file is not useful as the assembly code will still need to declare it + separately. + +_Ref 8.4.2_ + - xQueueRegistry is defined with external linkage because it is accessed by the + kernel unit tests. It is not meant to be directly accessed by the application + and therefore, not declared in a header file. + +#### Rule 8.6 + +MISRA C:2012 Rule 8.6: An identifier with external linkage shall have exactly +one external definition. + +_Ref 8.6.1_ + - This rule prohibits an identifier with external linkage to have multiple + definitions or no definition. FreeRTOS hook functions are implemented in + the application and therefore, have no definition in the Kernel code. + +#### Rule 11.1 +MISRA C:2012 Rule 11.1: Conversions shall not be performed between a pointer to +function and any other type. + +_Ref 11.1.1_ + - The pointer to function is casted into void to avoid unused parameter + compiler warning when Stream Buffer's Tx and Rx Completed callback feature is + not used. + +#### Rule 11.3 + +MISRA C:2012 Rule 11.3: A cast shall not be performed between a pointer to +object type and a pointer to a different object type. + +_Ref 11.3.1_ + - This rule prohibits casting a pointer to object into a pointer to a + different object because it may result in an incorrectly aligned pointer, + leading to undefined behavior. Even if the casting produces a correctly + aligned pointer, the behavior may be still undefined if the pointer is + used to access an object. FreeRTOS deliberately creates external aliases + for all the kernel object types (StaticEventGroup_t, StaticQueue_t, + StaticStreamBuffer_t, StaticTimer_t and StaticTask_t) for data hiding + purposes. The internal object types and the corresponding external + aliases are guaranteed to have the same size and alignment which is + checked using configASSERT. + + +#### Rule 11.5 + +MISRA C:2012 Rule 11.5: A conversion should not be performed from pointer to +void into pointer to object. +This rule prohibits conversion of a pointer to void into a pointer to +object because it may result in an incorrectly aligned pointer leading +to undefined behavior. + +_Ref 11.5.1_ + - The memory blocks returned by pvPortMalloc() are guaranteed to meet the + architecture alignment requirements specified by portBYTE_ALIGNMENT. + The casting of the pointer to void returned by pvPortMalloc() is, + therefore, safe because it is guaranteed to be aligned. + +_Ref 11.5.2_ + - The conversion from a pointer to void into a pointer to EventGroup_t is + safe because it is a pointer to EventGroup_t, which is returned to the + application at the time of event group creation for data hiding + purposes. + +_Ref 11.5.3_ + - The conversion from a pointer to void in list macros for list item owner + is safe because the type of the pointer stored and retrieved is the + same. + +_Ref 11.5.4_ + - The conversion from a pointer to void into a pointer to EventGroup_t is + safe because it is a pointer to EventGroup_t, which is passed as a + parameter to the xTimerPendFunctionCallFromISR API when the callback is + pended. + +_Ref 11.5.5_ + - The conversion from a pointer to void into a pointer to uint8_t is safe + because data storage buffers are implemented as uint8_t arrays for the + ease of sizing, alignment and access. + +#### Rule 14.3 + +MISRA C-2012 Rule 14.3: Controlling expressions shall not be invariant. + +_Ref 14.3_ + - The `configMAX_TASK_NAME_LEN` , `taskRESERVED_TASK_NAME_LENGTH` and `SIZE_MAX` + are evaluated to constants at compile time and may vary based on the build + configuration. + +#### Rule 18.1 + +MISRA C-2012 Rule 18.1: A pointer resulting from arithmetic on a pointer operand +shall address an element of the same array as that pointer operand. + +_Ref 18.1_ + - Array access remains within bounds since either the null terminator in + the IDLE task name will break the loop, or the loop will break normally + if the array size is smaller than the IDLE task name length. + +#### Rule 21.6 + +MISRA C-2012 Rule 21.6: The Standard Library input/output functions shall not +be used. + +_Ref 21.6.1_ + - The Standard Library function snprintf is used in vTaskListTasks and + vTaskGetRunTimeStatistics APIs, both of which are utility functions only and + are not considered part of core kernel implementation. diff --git a/Quick_Start_Guide.url b/Quick_Start_Guide.url new file mode 100644 index 000000000..ebefebd61 --- /dev/null +++ b/Quick_Start_Guide.url @@ -0,0 +1,5 @@ +[InternetShortcut] +URL=https://www.FreeRTOS.org/FreeRTOS-quick-start-guide.html +IDList= +[{000214A0-0000-0000-C000-000000000046}] +Prop3=19,2 diff --git a/README.md b/README.md new file mode 100644 index 000000000..b4e87ce3b --- /dev/null +++ b/README.md @@ -0,0 +1,192 @@ +[![CMock Unit Tests](https://github.com/FreeRTOS/FreeRTOS-Kernel/actions/workflows/unit-tests.yml/badge.svg?branch=main&event=push)](https://github.com/FreeRTOS/FreeRTOS-Kernel/actions/workflows/unit-tests.yml?query=branch%3Amain+event%3Apush+workflow%3A%22CMock+Unit+Tests%22++) +[![codecov](https://app.codecov.io/gh/FreeRTOS/FreeRTOS-Kernel/badge.svg?branch=main)](https://codecov.io/gh/FreeRTOS/FreeRTOS-Kernel) + +## Getting started + +This repository contains FreeRTOS kernel source/header files and kernel +ports only. This repository is referenced as a submodule in +[FreeRTOS/FreeRTOS](https://github.com/FreeRTOS/FreeRTOS) +repository, which contains pre-configured demo application projects under +```FreeRTOS/Demo``` directory. + +The easiest way to use FreeRTOS is to start with one of the pre-configured demo +application projects. That way you will have the correct FreeRTOS source files +included, and the correct include paths configured. Once a demo application is +building and executing you can remove the demo application files, and start to +add in your own application source files. See the +[FreeRTOS Kernel Quick Start Guide](https://www.freertos.org/Documentation/01-FreeRTOS-quick-start/01-Beginners-guide/02-Quick-start-guide) +for detailed instructions and other useful links. + +Additionally, for FreeRTOS kernel feature information refer to the +[Developer Documentation](https://www.freertos.org/Documentation/02-Kernel/02-Kernel-features/00-Developer-docs), +and [API Reference](https://www.freertos.org/Documentation/02-Kernel/04-API-references/01-Task-creation/00-TaskHandle). + +Also for contributing and creating a Pull Request please refer to +[the instructions here](.github/CONTRIBUTING.md#contributing-via-pull-request). + +**FreeRTOS-Kernel V11.1.0 +[source code](https://github.com/FreeRTOS/FreeRTOS-Kernel/tree/V11.1.0) is part +of the +[FreeRTOS 202406.00 LTS](https://github.com/FreeRTOS/FreeRTOS-LTS/tree/202406-LTS) +release.** + +### Getting help + +If you have any questions or need assistance troubleshooting your FreeRTOS project, +we have an active community that can help on the +[FreeRTOS Community Support Forum](https://forums.freertos.org). + +## To consume FreeRTOS-Kernel + +### Consume with CMake + +If using CMake, it is recommended to use this repository using FetchContent. +Add the following into your project's main or a subdirectory's `CMakeLists.txt`: + +- Define the source and version/tag you want to use: + +```cmake +FetchContent_Declare( freertos_kernel + GIT_REPOSITORY https://github.com/FreeRTOS/FreeRTOS-Kernel.git + GIT_TAG main #Note: Best practice to use specific git-hash or tagged version +) +``` + +In case you prefer to add it as a git submodule, do: + +```bash +git submodule add https://github.com/FreeRTOS/FreeRTOS-Kernel.git +git submodule update --init +``` + +- Add a freertos_config library (typically an INTERFACE library) The following assumes the directory structure: + - `include/FreeRTOSConfig.h` + +```cmake +add_library(freertos_config INTERFACE) + +target_include_directories(freertos_config SYSTEM +INTERFACE + include +) + +target_compile_definitions(freertos_config + INTERFACE + projCOVERAGE_TEST=0 +) +``` + +In case you installed FreeRTOS-Kernel as a submodule, you will have to add it as a subdirectory: + +```cmake +add_subdirectory(${FREERTOS_PATH}) +``` + +- Configure the FreeRTOS-Kernel and make it available + - this particular example supports a native and cross-compiled build option. + +```cmake +set( FREERTOS_HEAP "4" CACHE STRING "" FORCE) +# Select the native compile PORT +set( FREERTOS_PORT "GCC_POSIX" CACHE STRING "" FORCE) +# Select the cross-compile PORT +if (CMAKE_CROSSCOMPILING) + set(FREERTOS_PORT "GCC_ARM_CA9" CACHE STRING "" FORCE) +endif() + +FetchContent_MakeAvailable(freertos_kernel) +``` + +- In case of cross compilation, you should also add the following to `freertos_config`: + +```cmake +target_compile_definitions(freertos_config INTERFACE ${definitions}) +target_compile_options(freertos_config INTERFACE ${options}) +``` + +### Consuming stand-alone - Cloning this repository + +To clone using HTTPS: + +``` +git clone https://github.com/FreeRTOS/FreeRTOS-Kernel.git +``` + +Using SSH: + +``` +git clone git@github.com:FreeRTOS/FreeRTOS-Kernel.git +``` + +## Repository structure + +- The root of this repository contains the three files that are common to +every port - list.c, queue.c and tasks.c. The kernel is contained within these +three files. croutine.c implements the optional co-routine functionality - which +is normally only used on very memory limited systems. + +- The ```./portable``` directory contains the files that are specific to a particular microcontroller and/or compiler. +See the readme file in the ```./portable``` directory for more information. + +- The ```./include``` directory contains the real time kernel header files. + +- The ```./template_configuration``` directory contains a sample `FreeRTOSConfig.h` to help jumpstart a new project. +See the [FreeRTOSConfig.h](examples/template_configuration/FreeRTOSConfig.h) file for instructions. + +### Code Formatting + +FreeRTOS files are formatted using the +"[uncrustify](https://github.com/uncrustify/uncrustify)" tool. +The configuration file used by uncrustify can be found in the +[FreeRTOS/CI-CD-GitHub-Actions's](https://github.com/FreeRTOS/CI-CD-Github-Actions) +[uncrustify.cfg](https://github.com/FreeRTOS/CI-CD-Github-Actions/tree/main/formatting) +file. + +### Line Endings + +File checked into the FreeRTOS-Kernel repository use unix-style LF line endings +for the best compatibility with git. + +For optimal compatibility with Microsoft Windows tools, it is best to enable +the git autocrlf feature. You can enable this setting for the current +repository using the following command: + +``` +git config core.autocrlf true +``` + +### Git History Optimizations + +Some commits in this repository perform large refactors which touch many lines +and lead to unwanted behavior when using the `git blame` command. You can +configure git to ignore the list of large refactor commits in this repository +with the following command: + +``` +git config blame.ignoreRevsFile .git-blame-ignore-revs +``` + +### Spelling and Formatting + +We recommend using [Visual Studio Code](https://code.visualstudio.com), +commonly referred to as VSCode, when working on the FreeRTOS-Kernel. +The FreeRTOS-Kernel also uses [cSpell](https://cspell.org/) as part of its +spelling check. The config file for which can be found at [cspell.config.yaml](cspell.config.yaml) +There is additionally a +[cSpell plugin for VSCode](https://marketplace.visualstudio.com/items?itemName=streetsidesoftware.code-spell-checker) +that can be used as well. +*[.cSpellWords.txt](.github/.cSpellWords.txt)* contains words that are not +traditionally found in an English dictionary. It is used by the spellchecker +to verify the various jargon, variable names, and other odd words used in the +FreeRTOS code base are correct. If your pull request fails to pass the spelling +and you believe this is a mistake, then add the word to +*[.cSpellWords.txt](.github/.cSpellWords.txt)*. When adding a word please +then sort the list, which can be done by running the bash command: +`sort -u .cSpellWords.txt -o .cSpellWords.txt` +Note that only the FreeRTOS-Kernel Source Files, [include](include), +[portable/MemMang](portable/MemMang), and [portable/Common](portable/Common) +files are checked for proper spelling, and formatting at this time. + +## Third Party Tools +Visit [this link](.github/third_party_tools.md) for detailed information about +third-party tools with FreeRTOS support. diff --git a/Source/croutine.c b/Source/croutine.c deleted file mode 100644 index b559c304a..000000000 --- a/Source/croutine.c +++ /dev/null @@ -1,342 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#include "FreeRTOS.h" -#include "task.h" -#include "croutine.h" - -/* Lists for ready and blocked co-routines. --------------------*/ -static xList pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ]; /*< Prioritised ready co-routines. */ -static xList xDelayedCoRoutineList1; /*< Delayed co-routines. */ -static xList xDelayedCoRoutineList2; /*< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */ -static xList * pxDelayedCoRoutineList; /*< Points to the delayed co-routine list currently being used. */ -static xList * pxOverflowDelayedCoRoutineList; /*< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */ -static xList xPendingReadyList; /*< Holds co-routines that have been readied by an external event. They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */ - -/* Other file private variables. --------------------------------*/ -corCRCB * pxCurrentCoRoutine = NULL; -static unsigned portBASE_TYPE uxTopCoRoutineReadyPriority = 0; -static portTickType xCoRoutineTickCount = 0; - -/* The initial state of the co-routine when it is created. */ -#define corINITIAL_STATE ( 0 ) - -/* - * Place the co-routine represented by pxCRCB into the appropriate ready queue - * for the priority. It is inserted at the end of the list. - * - * This macro accesses the co-routine ready lists and therefore must not be - * used from within an ISR. - */ -#define prvAddCoRoutineToReadyQueue( pxCRCB ) \ -{ \ - if( pxCRCB->uxPriority > uxTopCoRoutineReadyPriority ) \ - { \ - uxTopCoRoutineReadyPriority = pxCRCB->uxPriority; \ - } \ - vListInsertEnd( ( xList * ) &( pxReadyCoRoutineLists[ pxCRCB->uxPriority ] ), &( pxCRCB->xGenericListItem ) ); \ -} - -/* - * Utility to ready all the lists used by the scheduler. This is called - * automatically upon the creation of the first co-routine. - */ -static void prvInitialiseCoRoutineLists( void ); - -/* - * Co-routines that are readied by an interrupt cannot be placed directly into - * the ready lists (there is no mutual exclusion). Instead they are placed in - * in the pending ready list in order that they can later be moved to the ready - * list by the co-routine scheduler. - */ -static inline void prvCheckPendingReadyList( void ); - -/* - * Macro that looks at the list of co-routines that are currently delayed to - * see if any require waking. - * - * Co-routines are stored in the queue in the order of their wake time - - * meaning once one co-routine has been found whose timer has not expired - * we need not look any further down the list. - */ -static inline void prvCheckDelayedList( void ); - -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, unsigned portBASE_TYPE uxPriority, unsigned portBASE_TYPE uxIndex ) -{ -signed portBASE_TYPE xReturn; -corCRCB *pxCoRoutine; - - /* Allocate the memory that will store the co-routine control block. */ - pxCoRoutine = ( corCRCB * ) pvPortMalloc( sizeof( corCRCB ) ); - if( pxCoRoutine ) - { - /* If pxCurrentCoRoutine is NULL then this is the first co-routine to - be created and the co-routine data structures need initialising. */ - if( pxCurrentCoRoutine == NULL ) - { - pxCurrentCoRoutine = pxCoRoutine; - prvInitialiseCoRoutineLists(); - } - - /* Check the priority is within limits. */ - if( uxPriority >= configMAX_CO_ROUTINE_PRIORITIES ) - { - uxPriority = configMAX_CO_ROUTINE_PRIORITIES - 1; - } - - /* Fill out the co-routine control block from the function parameters. */ - pxCoRoutine->uxState = corINITIAL_STATE; - pxCoRoutine->uxPriority = uxPriority; - pxCoRoutine->uxIndex = uxIndex; - pxCoRoutine->pxCoRoutineFunction = pxCoRoutineCode; - - /* Initialise all the other co-routine control block parameters. */ - vListInitialiseItem( &( pxCoRoutine->xGenericListItem ) ); - vListInitialiseItem( &( pxCoRoutine->xEventListItem ) ); - - /* Set the co-routine control block as a link back from the xListItem. - This is so we can get back to the containing CRCB from a generic item - in a list. */ - listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xGenericListItem ), pxCoRoutine ); - listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xEventListItem ), pxCoRoutine ); - - /* Event lists are always in priority order. */ - listSET_LIST_ITEM_VALUE( &( pxCoRoutine->xEventListItem ), configMAX_PRIORITIES - ( portTickType ) uxPriority ); - - /* Now the co-routine has been initialised it can be added to the ready - list at the correct priority. */ - prvAddCoRoutineToReadyQueue( pxCoRoutine ); - - xReturn = pdPASS; - } - else - { - xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -void vCoRoutineAddToDelayedList( portTickType xTicksToDelay, xList *pxEventList ) -{ -portTickType xTimeToWake; - - /* Calculate the time to wake - this may overflow but this is - not a problem. */ - xTimeToWake = xCoRoutineTickCount + xTicksToDelay; - - /* We must remove ourselves from the ready list before adding - ourselves to the blocked list as the same list item is used for - both lists. */ - vListRemove( ( xListItem * ) &( pxCurrentCoRoutine->xGenericListItem ) ); - - /* The list item will be inserted in wake time order. */ - listSET_LIST_ITEM_VALUE( &( pxCurrentCoRoutine->xGenericListItem ), xTimeToWake ); - - if( xTimeToWake < xCoRoutineTickCount ) - { - /* Wake time has overflowed. Place this item in the - overflow list. */ - vListInsert( ( xList * ) pxOverflowDelayedCoRoutineList, ( xListItem * ) &( pxCurrentCoRoutine->xGenericListItem ) ); - } - else - { - /* The wake time has not overflowed, so we can use the - current block list. */ - vListInsert( ( xList * ) pxDelayedCoRoutineList, ( xListItem * ) &( pxCurrentCoRoutine->xGenericListItem ) ); - } - - if( pxEventList ) - { - /* Also add the co-routine to an event list. If this is done then the - function must be called with interrupts disabled. */ - vListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) ); - } -} -/*-----------------------------------------------------------*/ - -static inline void prvCheckPendingReadyList( void ) -{ - /* Are there any co-routines waiting to get moved to the ready list? These - are co-routines that have been readied by an ISR. The ISR cannot access - the ready lists itself. */ - while( !listLIST_IS_EMPTY( &xPendingReadyList ) ) - { - corCRCB *pxUnblockedCRCB; - - /* The pending ready list can be accessed by an ISR. */ - portDISABLE_INTERRUPTS(); - { - pxUnblockedCRCB = ( corCRCB * ) listGET_OWNER_OF_HEAD_ENTRY( (&xPendingReadyList) ); - vListRemove( &( pxUnblockedCRCB->xEventListItem ) ); - } - portENABLE_INTERRUPTS(); - - vListRemove( &( pxUnblockedCRCB->xGenericListItem ) ); - prvAddCoRoutineToReadyQueue( pxUnblockedCRCB ); - } -} -/*-----------------------------------------------------------*/ - -static inline void prvCheckDelayedList( void ) -{ -static portTickType xLastTickCount, xPassedTicks; -corCRCB *pxCRCB; - - xPassedTicks = xTaskGetTickCount() - xLastTickCount; - while( xPassedTicks ) - { - xCoRoutineTickCount++; - xPassedTicks--; - - /* If the tick count has overflowed we need to swap the ready lists. */ - if( xCoRoutineTickCount == 0 ) - { - xList * pxTemp; - - /* Tick count has overflowed so we need to swap the delay lists. If there are - any items in pxDelayedCoRoutineList here then there is an error! */ - pxTemp = pxDelayedCoRoutineList; - pxDelayedCoRoutineList = pxOverflowDelayedCoRoutineList; - pxOverflowDelayedCoRoutineList = pxTemp; - } - - /* See if this tick has made a timeout expire. */ - while( ( pxCRCB = ( corCRCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedCoRoutineList ) ) != NULL ) - { - if( xCoRoutineTickCount < listGET_LIST_ITEM_VALUE( &( pxCRCB->xGenericListItem ) ) ) - { - /* Timeout not yet expired. */ - break; - } - - portDISABLE_INTERRUPTS(); - { - /* The event could have occurred just before this critical - section. If this is the case then the generic list item will - have been moved to the pending ready list and the following - line is still valid. Also the pvContainer parameter will have - been set to NULL so the following lines are also valid. */ - vListRemove( &( pxCRCB->xGenericListItem ) ); - - /* Is the co-routine waiting on an event also? */ - if( pxCRCB->xEventListItem.pvContainer ) - { - vListRemove( &( pxCRCB->xEventListItem ) ); - } - } - portENABLE_INTERRUPTS(); - - prvAddCoRoutineToReadyQueue( pxCRCB ); - } - } - - xLastTickCount = xCoRoutineTickCount; -} -/*-----------------------------------------------------------*/ - -void vCoRoutineSchedule( void ) -{ - /* See if any co-routines readied by events need moving to the ready lists. */ - prvCheckPendingReadyList(); - - /* See if any delayed co-routines have timed out. */ - prvCheckDelayedList(); - - /* Find the highest priority queue that contains ready co-routines. */ - while( listLIST_IS_EMPTY( &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ) ) - { - if( uxTopCoRoutineReadyPriority == 0 ) - { - /* No more co-routines to check. */ - return; - } - --uxTopCoRoutineReadyPriority; - } - - /* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the co-routines - of the same priority get an equal share of the processor time. */ - listGET_OWNER_OF_NEXT_ENTRY( pxCurrentCoRoutine, &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ); - - /* Call the co-routine. */ - ( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex ); - - return; -} -/*-----------------------------------------------------------*/ - -static void prvInitialiseCoRoutineLists( void ) -{ -unsigned portBASE_TYPE uxPriority; - - for( uxPriority = 0; uxPriority < configMAX_CO_ROUTINE_PRIORITIES; uxPriority++ ) - { - vListInitialise( ( xList * ) &( pxReadyCoRoutineLists[ uxPriority ] ) ); - } - - vListInitialise( ( xList * ) &xDelayedCoRoutineList1 ); - vListInitialise( ( xList * ) &xDelayedCoRoutineList2 ); - vListInitialise( ( xList * ) &xPendingReadyList ); - - /* Start with pxDelayedCoRoutineList using list1 and the - pxOverflowDelayedCoRoutineList using list2. */ - pxDelayedCoRoutineList = &xDelayedCoRoutineList1; - pxOverflowDelayedCoRoutineList = &xDelayedCoRoutineList2; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xCoRoutineRemoveFromEventList( const xList *pxEventList ) -{ -corCRCB *pxUnblockedCRCB; -signed portBASE_TYPE xReturn; - - /* This function is called from within an interrupt. It can only access - event lists and the pending ready list. */ - pxUnblockedCRCB = ( corCRCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); - vListRemove( &( pxUnblockedCRCB->xEventListItem ) ); - vListInsertEnd( ( xList * ) &( xPendingReadyList ), &( pxUnblockedCRCB->xEventListItem ) ); - - if( pxUnblockedCRCB->uxPriority >= pxCurrentCoRoutine->uxPriority ) - { - xReturn = pdTRUE; - } - else - { - xReturn = pdFALSE; - } - - return xReturn; -} - diff --git a/Source/include/FreeRTOS.h b/Source/include/FreeRTOS.h deleted file mode 100644 index 63bd13055..000000000 --- a/Source/include/FreeRTOS.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef INC_FREERTOS_H -#define INC_FREERTOS_H - - -/* - * Include the generic headers required for the FreeRTOS port being used. - */ -#include - -/* Basic FreeRTOS definitions. */ -#include "projdefs.h" - -/* Application specific configuration options. */ -#include "FreeRTOSConfig.h" - -/* Definitions specific to the port being used. */ -#include "portable.h" - - - - - - - -/* - * Check all the required application specific macros have been defined. - * These macros are application specific and (as downloaded) are defined - * within FreeRTOSConfig.h. - */ - -#ifndef configUSE_PREEMPTION - #error Missing definition: configUSE_PREEMPTION should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef configUSE_IDLE_HOOK - #error Missing definition: configUSE_IDLE_HOOK should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef configUSE_TICK_HOOK - #error Missing definition: configUSE_TICK_HOOK should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef configUSE_CO_ROUTINES - #error Missing definition: configUSE_CO_ROUTINES should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskPrioritySet - #error Missing definition: INCLUDE_vTaskPrioritySet should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_uxTaskPriorityGet - #error Missing definition: INCLUDE_uxTaskPriorityGet should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskDelete - #error Missing definition: INCLUDE_vTaskDelete should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskCleanUpResources - #error Missing definition: INCLUDE_vTaskCleanUpResources should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskSuspend - #error Missing definition: INCLUDE_vTaskSuspend should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskDelayUntil - #error Missing definition: INCLUDE_vTaskDelayUntil should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskDelay - #error Missing definition: INCLUDE_vTaskDelay should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef configUSE_16_BIT_TICKS - #error Missing definition: configUSE_16_BIT_TICKS should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#endif diff --git a/Source/include/croutine.h b/Source/include/croutine.h deleted file mode 100644 index 383ecf3b8..000000000 --- a/Source/include/croutine.h +++ /dev/null @@ -1,713 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ -#ifndef CO_ROUTINE_H -#define CO_ROUTINE_H - -#include "list.h" - -/* Used to hide the implementation of the co-routine control block. The -control block structure however has to be included in the header due to -the macro implementation of the co-routine functionality. */ -typedef void * xCoRoutineHandle; - -/* Defines the prototype to which co-routine functions must conform. */ -typedef void (*crCOROUTINE_CODE)( xCoRoutineHandle, unsigned portBASE_TYPE ); - -typedef struct corCoRoutineControlBlock -{ - crCOROUTINE_CODE pxCoRoutineFunction; - xListItem xGenericListItem; /*< List item used to place the CRCB in ready and blocked queues. */ - xListItem xEventListItem; /*< List item used to place the CRCB in event lists. */ - unsigned portBASE_TYPE uxPriority; /*< The priority of the co-routine in relation to other co-routines. */ - unsigned portBASE_TYPE uxIndex; /*< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */ - unsigned portSHORT uxState; /*< Used internally by the co-routine implementation. */ -} corCRCB; /* Co-routine control block. Note must be identical in size down to uxPriority with tskTCB. */ - -/** - * croutine. h - *
- portBASE_TYPE xCoRoutineCreate(
-                                 crCOROUTINE_CODE pxCoRoutineCode,
-                                 unsigned portBASE_TYPE uxPriority,
-                                 unsigned portBASE_TYPE uxIndex
-                               );
- * - * Create a new co-routine and add it to the list of co-routines that are - * ready to run. - * - * @param pxCoRoutineCode Pointer to the co-routine function. Co-routine - * functions require special syntax - see the co-routine section of the WEB - * documentation for more information. - * - * @param uxPriority The priority with respect to other co-routines at which - * the co-routine will run. - * - * @param uxIndex Used to distinguish between different co-routines that - * execute the same function. See the example below and the co-routine section - * of the WEB documentation for further information. - * - * @return pdPASS if the co-routine was successfully created and added to a ready - * list, otherwise an error code defined with ProjDefs.h. - * - * Example usage: - 
- // Co-routine to be created.
- void vFlashCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- // This may not be necessary for const variables.
- static const char cLedToFlash[ 2 ] = { 5, 6 };
- static const portTickType xTimeToDelay[ 2 ] = { 200, 400 };
-
-     // Must start every co-routine with a call to crSTART();
-     crSTART( xHandle );
-
-     for( ;; )
-     {
-         // This co-routine just delays for a fixed period, then toggles
-         // an LED.  Two co-routines are created using this function, so
-         // the uxIndex parameter is used to tell the co-routine which
-         // LED to flash and how long to delay.  This assumes xQueue has
-         // already been created.
-         vParTestToggleLED( cLedToFlash[ uxIndex ] );
-         crDELAY( xHandle, uxFlashRates[ uxIndex ] );
-     }
-
-     // Must end every co-routine with a call to crEND();
-     crEND();
- }
-
- // Function that creates two co-routines.
- void vOtherFunction( void )
- {
- unsigned char ucParameterToPass;
- xTaskHandle xHandle;
-		
-     // Create two co-routines at priority 0.  The first is given index 0
-     // so (from the code above) toggles LED 5 every 200 ticks.  The second
-     // is given index 1 so toggles LED 6 every 400 ticks.
-     for( uxIndex = 0; uxIndex < 2; uxIndex++ )
-     {
-         xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex );
-     }
- }
-
- * \defgroup xCoRoutineCreate xCoRoutineCreate - * \ingroup Tasks - */ -signed portBASE_TYPE xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, unsigned portBASE_TYPE uxPriority, unsigned portBASE_TYPE uxIndex ); - - -/** - * croutine. h - *
- void vCoRoutineSchedule( void );
- * - * Run a co-routine. - * - * vCoRoutineSchedule() executes the highest priority co-routine that is able - * to run. The co-routine will execute until it either blocks, yields or is - * preempted by a task. Co-routines execute cooperatively so one - * co-routine cannot be preempted by another, but can be preempted by a task. - * - * If an application comprises of both tasks and co-routines then - * vCoRoutineSchedule should be called from the idle task (in an idle task - * hook). - * - * Example usage: - 
- // This idle task hook will schedule a co-routine each time it is called.
- // The rest of the idle task will execute between co-routine calls.
- void vApplicationIdleHook( void )
- {
-	vCoRoutineSchedule();
- }
-
- // Alternatively, if you do not require any other part of the idle task to
- // execute, the idle task hook can call vCoRoutineScheduler() within an
- // infinite loop.
- void vApplicationIdleHook( void )
- {
-    for( ;; )
-    {
-        vCoRoutineSchedule();
-    }
- }
-
- * \defgroup vCoRoutineSchedule vCoRoutineSchedule - * \ingroup Tasks - */ -void vCoRoutineSchedule( void ); - -/** - * croutine. h - * 
- crSTART( xCoRoutineHandle xHandle );
- * - * This macro MUST always be called at the start of a co-routine function. - * - * Example usage: - 
- // Co-routine to be created.
- void vACoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- static portLONG ulAVariable;
-
-     // Must start every co-routine with a call to crSTART();
-     crSTART( xHandle );
-
-     for( ;; )
-     {
-          // Co-routine functionality goes here.
-     }
-
-     // Must end every co-routine with a call to crEND();
-     crEND();
- }
- * \defgroup crSTART crSTART - * \ingroup Tasks - */ -#define crSTART( pxCRCB ) switch( ( ( corCRCB * )pxCRCB )->uxState ) { case 0: - -/** - * croutine. h - * 
- crEND();
- * - * This macro MUST always be called at the end of a co-routine function. - * - * Example usage: - 
- // Co-routine to be created.
- void vACoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- static portLONG ulAVariable;
-
-     // Must start every co-routine with a call to crSTART();
-     crSTART( xHandle );
-
-     for( ;; )
-     {
-          // Co-routine functionality goes here.
-     }
-
-     // Must end every co-routine with a call to crEND();
-     crEND();
- }
- * \defgroup crSTART crSTART - * \ingroup Tasks - */ -#define crEND() } - -/* - * These macros are intended for internal use by the co-routine implementation - * only. The macros should not be used directly by application writers. - */ -#define crSET_STATE0( xHandle ) ( ( corCRCB * )xHandle)->uxState = (__LINE__ * 2); return; case (__LINE__ * 2): -#define crSET_STATE1( xHandle ) ( ( corCRCB * )xHandle)->uxState = ((__LINE__ * 2)+1); return; case ((__LINE__ * 2)+1): - -/** - * croutine. h - *
- crDELAY( xCoRoutineHandle xHandle, portTickType xTicksToDelay );
- * - * Delay a co-routine for a fixed period of time. - * - * crDELAY can only be called from the co-routine function itself - not - * from within a function called by the co-routine function. This is because - * co-routines do not maintain their own stack. - * - * @param xHandle The handle of the co-routine to delay. This is the xHandle - * parameter of the co-routine function. - * - * @param xTickToDelay The number of ticks that the co-routine should delay - * for. The actual amount of time this equates to is defined by - * configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant portTICK_RATE_MS - * can be used to convert ticks to milliseconds. - * - * Example usage: - 
- // Co-routine to be created.
- void vACoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- // This may not be necessary for const variables.
- // We are to delay for 200ms.
- static const xTickType xDelayTime = 200 / portTICK_RATE_MS;
-
-     // Must start every co-routine with a call to crSTART();
-     crSTART( xHandle );
-
-     for( ;; )
-     {
-        // Delay for 200ms.
-        crDELAY( xHandle, xDelayTime );
-
-        // Do something here.
-     }
-
-     // Must end every co-routine with a call to crEND();
-     crEND();
- }
- * \defgroup crDELAY crDELAY - * \ingroup Tasks - */ -#define crDELAY( xHandle, xTicksToDelay ) \ - if( xTicksToDelay > 0 ) \ - { \ - vCoRoutineAddToDelayedList( xTicksToDelay, NULL ); \ - } \ - crSET_STATE0( xHandle ); - -/** - * 
- crQUEUE_SEND(
-                  xCoRoutineHandle xHandle,
-                  xQueueHandle pxQueue,
-                  void *pvItemToQueue,
-                  portTickType xTicksToWait,
-                  portBASE_TYPE *pxResult
-             )
- * - * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine - * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. - * - * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas - * xQueueSend() and xQueueReceive() can only be used from tasks. - * - * crQUEUE_SEND can only be called from the co-routine function itself - not - * from within a function called by the co-routine function. This is because - * co-routines do not maintain their own stack. - * - * See the co-routine section of the WEB documentation for information on - * passing data between tasks and co-routines and between ISR's and - * co-routines. - * - * @param xHandle The handle of the calling co-routine. This is the xHandle - * parameter of the co-routine function. - * - * @param pxQueue The handle of the queue on which the data will be posted. - * The handle is obtained as the return value when the queue is created using - * the xQueueCreate() API function. - * - * @param pvItemToQueue A pointer to the data being posted onto the queue. - * The number of bytes of each queued item is specified when the queue is - * created. This number of bytes is copied from pvItemToQueue into the queue - * itself. - * - * @param xTickToDelay The number of ticks that the co-routine should block - * to wait for space to become available on the queue, should space not be - * available immediately. The actual amount of time this equates to is defined - * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant - * portTICK_RATE_MS can be used to convert ticks to milliseconds (see example - * below). - * - * @param pxResult The variable pointed to by pxResult will be set to pdPASS if - * data was successfully posted onto the queue, otherwise it will be set to an - * error defined within ProjDefs.h. - * - * Example usage: - 
- // Co-routine function that blocks for a fixed period then posts a number onto
- // a queue.
- static void prvCoRoutineFlashTask( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- static portBASE_TYPE xNumberToPost = 0;
- static portBASE_TYPE xResult;
-
-    // Co-routines must begin with a call to crSTART().
-    crSTART( xHandle );
-
-    for( ;; )
-    {
-        // This assumes the queue has already been created.
-        crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult );
-
-        if( xResult != pdPASS )
-        {
-            // The message was not posted!
-        }
-
-        // Increment the number to be posted onto the queue.
-        xNumberToPost++;
-
-        // Delay for 100 ticks.
-        crDELAY( xHandle, 100 );
-    }
-
-    // Co-routines must end with a call to crEND().
-    crEND();
- }
- * \defgroup crQUEUE_SEND crQUEUE_SEND - * \ingroup Tasks - */ -#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult ) \ -{ \ - *pxResult = xQueueCRSend( pxQueue, pvItemToQueue, xTicksToWait ); \ - if( *pxResult == errQUEUE_BLOCKED ) \ - { \ - crSET_STATE0( xHandle ); \ - *pxResult = xQueueCRSend( pxQueue, pvItemToQueue, 0 ); \ - } \ - if( *pxResult == errQUEUE_YIELD ) \ - { \ - crSET_STATE1( xHandle ); \ - *pxResult = pdPASS; \ - } \ -} - -/** - * croutine. h - * 
-  crQUEUE_RECEIVE(
-                     xCoRoutineHandle xHandle,
-                     xQueueHandle pxQueue,
-                     void *pvBuffer,
-                     portTickType xTicksToWait,
-                     portBASE_TYPE *pxResult
-                 )
- * - * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine - * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. - * - * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas - * xQueueSend() and xQueueReceive() can only be used from tasks. - * - * crQUEUE_RECEIVE can only be called from the co-routine function itself - not - * from within a function called by the co-routine function. This is because - * co-routines do not maintain their own stack. - * - * See the co-routine section of the WEB documentation for information on - * passing data between tasks and co-routines and between ISR's and - * co-routines. - * - * @param xHandle The handle of the calling co-routine. This is the xHandle - * parameter of the co-routine function. - * - * @param pxQueue The handle of the queue from which the data will be received. - * The handle is obtained as the return value when the queue is created using - * the xQueueCreate() API function. - * - * @param pvBuffer The buffer into which the received item is to be copied. - * The number of bytes of each queued item is specified when the queue is - * created. This number of bytes is copied into pvBuffer. - * - * @param xTickToDelay The number of ticks that the co-routine should block - * to wait for data to become available from the queue, should data not be - * available immediately. The actual amount of time this equates to is defined - * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant - * portTICK_RATE_MS can be used to convert ticks to milliseconds (see the - * crQUEUE_SEND example). - * - * @param pxResult The variable pointed to by pxResult will be set to pdPASS if - * data was successfully retrieved from the queue, otherwise it will be set to - * an error code as defined within ProjDefs.h. - * - * Example usage: - 
- // A co-routine receives the number of an LED to flash from a queue.  It
- // blocks on the queue until the number is received.
- static void prvCoRoutineFlashWorkTask( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- static portBASE_TYPE xResult;
- static unsigned portBASE_TYPE uxLEDToFlash;
-
-    // All co-routines must start with a call to crSTART().
-    crSTART( xHandle );
-
-    for( ;; )
-    {
-        // Wait for data to become available on the queue.
-        crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
-
-        if( xResult == pdPASS )
-        {
-            // We received the LED to flash - flash it!
-            vParTestToggleLED( uxLEDToFlash );
-        }
-    }
-
-    crEND();
- }
- * \defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE - * \ingroup Tasks - */ -#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult ) \ -{ \ - *pxResult = xQueueCRReceive( pxQueue, pvBuffer, xTicksToWait ); \ - if( *pxResult == errQUEUE_BLOCKED ) \ - { \ - crSET_STATE0( xHandle ); \ - *pxResult = xQueueCRReceive( pxQueue, pvBuffer, 0 ); \ - } \ - if( *pxResult == errQUEUE_YIELD ) \ - { \ - crSET_STATE1( xHandle ); \ - *pxResult = pdPASS; \ - } \ -} - -/** - * croutine. h - * 
-  crQUEUE_SEND_FROM_ISR(
-                            xQueueHandle pxQueue,
-                            void *pvItemToQueue,
-                            portBASE_TYPE xCoRoutinePreviouslyWoken
-                       )
- * - * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the - * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() - * functions used by tasks. - * - * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to - * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and - * xQueueReceiveFromISR() can only be used to pass data between a task and and - * ISR. - * - * crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue - * that is being used from within a co-routine. - * - * See the co-routine section of the WEB documentation for information on - * passing data between tasks and co-routines and between ISR's and - * co-routines. - * - * @param xQueue The handle to the queue on which the item is to be posted. - * - * @param pvItemToQueue A pointer to the item that is to be placed on the - * queue. The size of the items the queue will hold was defined when the - * queue was created, so this many bytes will be copied from pvItemToQueue - * into the queue storage area. - * - * @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto - * the same queue multiple times from a single interrupt. The first call - * should always pass in pdFALSE. Subsequent calls should pass in - * the value returned from the previous call. - * - * @return pdTRUE if a co-routine was woken by posting onto the queue. This is - * used by the ISR to determine if a context switch may be required following - * the ISR. - * - * Example usage: - 
- // A co-routine that blocks on a queue waiting for characters to be received.
- static void vReceivingCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
- {
- portCHAR cRxedChar;
- portBASE_TYPE xResult;
-
-     // All co-routines must start with a call to crSTART().
-     crSTART( xHandle );
-
-     for( ;; )
-     {
-         // Wait for data to become available on the queue.  This assumes the
-         // queue xCommsRxQueue has already been created!
-         crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
-
-         // Was a character received?
-         if( xResult == pdPASS )
-         {
-             // Process the character here.
-         }
-     }
-
-     // All co-routines must end with a call to crEND().
-     crEND();
- }
-
- // An ISR that uses a queue to send characters received on a serial port to
- // a co-routine.
- void vUART_ISR( void )
- {
- portCHAR cRxedChar;
- portBASE_TYPE xCRWokenByPost = pdFALSE;
-
-     // We loop around reading characters until there are none left in the UART.
-     while( UART_RX_REG_NOT_EMPTY() )
-     {
-         // Obtain the character from the UART.
-         cRxedChar = UART_RX_REG;
-
-         // Post the character onto a queue.  xCRWokenByPost will be pdFALSE
-         // the first time around the loop.  If the post causes a co-routine
-         // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE.
-         // In this manner we can ensure that if more than one co-routine is
-         // blocked on the queue only one is woken by this ISR no matter how
-         // many characters are posted to the queue.
-         xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost );
-     }
- }
- * \defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR - * \ingroup Tasks - */ -#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) xQueueCRSendFromISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) - - -/** - * croutine. h - * 
-  crQUEUE_SEND_FROM_ISR(
-                            xQueueHandle pxQueue,
-                            void *pvBuffer,
-                            portBASE_TYPE * pxCoRoutineWoken
-                       )
- * - * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the - * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() - * functions used by tasks. - * - * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to - * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and - * xQueueReceiveFromISR() can only be used to pass data between a task and and - * ISR. - * - * crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data - * from a queue that is being used from within a co-routine (a co-routine - * posted to the queue). - * - * See the co-routine section of the WEB documentation for information on - * passing data between tasks and co-routines and between ISR's and - * co-routines. - * - * @param xQueue The handle to the queue on which the item is to be posted. - * - * @param pvBuffer A pointer to a buffer into which the received item will be - * placed. The size of the items the queue will hold was defined when the - * queue was created, so this many bytes will be copied from the queue into - * pvBuffer. - * - * @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become - * available on the queue. If crQUEUE_RECEIVE_FROM_ISR causes such a - * co-routine to unblock *pxCoRoutineWoken will get set to pdTRUE, otherwise - * *pxCoRoutineWoken will remain unchanged. - * - * @return pdTRUE an item was successfully received from the queue, otherwise - * pdFALSE. - * - * Example usage: - 
- // A co-routine that posts a character to a queue then blocks for a fixed
- // period.  The character is incremented each time.
- static void vSendingCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
- {
- // cChar holds its value while this co-routine is blocked and must therefore
- // be declared static.
- static portCHAR cCharToTx = 'a';
- portBASE_TYPE xResult;
-
-     // All co-routines must start with a call to crSTART().
-     crSTART( xHandle );
-
-     for( ;; )
-     {
-         // Send the next character to the queue.
-         crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult );
-
-         if( xResult == pdPASS )
-         {
-             // The character was successfully posted to the queue.
-         }
-		 else
-		 {
-			// Could not post the character to the queue.
-		 }
-
-         // Enable the UART Tx interrupt to cause an interrupt in this
-		 // hypothetical UART.  The interrupt will obtain the character
-		 // from the queue and send it.
-		 ENABLE_RX_INTERRUPT();
-
-		 // Increment to the next character then block for a fixed period.
-		 // cCharToTx will maintain its value across the delay as it is
-		 // declared static.
-		 cCharToTx++;
-		 if( cCharToTx > 'x' )
-		 {
-			cCharToTx = 'a';
-		 }
-		 crDELAY( 100 );
-     }
-
-     // All co-routines must end with a call to crEND().
-     crEND();
- }
-
- // An ISR that uses a queue to receive characters to send on a UART.
- void vUART_ISR( void )
- {
- portCHAR cCharToTx;
- portBASE_TYPE xCRWokenByPost = pdFALSE;
-
-     while( UART_TX_REG_EMPTY() )
-     {
-         // Are there any characters in the queue waiting to be sent?
-		 // xCRWokenByPost will automatically be set to pdTRUE if a co-routine
-		 // is woken by the post - ensuring that only a single co-routine is
-		 // woken no matter how many times we go around this loop.
-         if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) )
-		 {
-			 SEND_CHARACTER( cCharToTx );
-		 }
-     }
- }
- * \defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR - * \ingroup Tasks - */ -#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) xQueueCRReceiveFromISR( pxQueue, pvBuffer, pxCoRoutineWoken ) - -/* - * This function is intended for internal use by the co-routine macros only. - * The macro nature of the co-routine implementation requires that the - * prototype appears here. The function should not be used by application - * writers. - * - * Removes the current co-routine from its ready list and places it in the - * appropriate delayed list. - */ -void vCoRoutineAddToDelayedList( portTickType xTicksToDelay, xList *pxEventList ); - -/* - * This function is intended for internal use by the queue implementation only. - * The function should not be used by application writers. - * - * Removes the highest priority co-routine from the event list and places it in - * the pending ready list. - */ -signed portBASE_TYPE xCoRoutineRemoveFromEventList( const xList *pxEventList ); - - -#endif /* CO_ROUTINE_H */ diff --git a/Source/include/list.h b/Source/include/list.h deleted file mode 100644 index 243fdb7a8..000000000 --- a/Source/include/list.h +++ /dev/null @@ -1,270 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * This is the list implementation used by the scheduler. While it is tailored - * heavily for the schedulers needs, it is also available for use by - * application code. - * - * xLists can only store pointers to xListItems. Each xListItem contains a - * numeric value (xItemValue). Most of the time the lists are sorted in - * descending item value order. - * - * Lists are created already containing one list item. The value of this - * item is the maximum possible that can be stored, it is therefore always at - * the end of the list and acts as a marker. The list member pxHead always - * points to this marker - even though it is at the tail of the list. This - * is because the tail contains a wrap back pointer to the true head of - * the list. - * - * In addition to it's value, each list item contains a pointer to the next - * item in the list (pxNext), a pointer to the list it is in (pxContainer) - * and a pointer to back to the object that contains it. These later two - * pointers are included for efficiency of list manipulation. There is - * effectively a two way link between the object containing the list item and - * the list item itself. - * - * - * \page ListIntroduction List Implementation - * \ingroup FreeRTOSIntro - */ - - -#ifndef LIST_H -#define LIST_H - -/* - * Definition of the only type of object that a list can contain. - */ -struct xLIST_ITEM -{ - portTickType xItemValue; /*< The value being listed. In most cases this is used to sort the list in descending order. */ - volatile struct xLIST_ITEM * pxNext; /*< Pointer to the next xListItem in the list. */ - volatile struct xLIST_ITEM * pxPrevious;/*< Pointer to the previous xListItem in the list. */ - void * pvOwner; /*< Pointer to the object (normally a TCB) that contains the list item. There is therefore a two way link between the object containing the list item and the list item itself. */ - void * pvContainer; /*< Pointer to the list in which this list item is placed (if any). */ -}; -typedef struct xLIST_ITEM xListItem; /* For some reason lint wants this as two separate definitions. */ - -struct xMINI_LIST_ITEM -{ - portTickType xItemValue; - volatile struct xLIST_ITEM *pxNext; - volatile struct xLIST_ITEM *pxPrevious; -}; -typedef struct xMINI_LIST_ITEM xMiniListItem; - -/* - * Definition of the type of queue used by the scheduler. - */ -typedef struct xLIST -{ - volatile unsigned portBASE_TYPE uxNumberOfItems; - volatile xListItem * pxIndex; /*< Used to walk through the list. Points to the last item returned by a call to pvListGetOwnerOfNextEntry (). */ - volatile xMiniListItem xListEnd; /*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */ -} xList; - -/* - * Access macro to set the owner of a list item. The owner of a list item - * is the object (usually a TCB) that contains the list item. - * - * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER - * \ingroup LinkedList - */ -#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner ) ( pxListItem )->pvOwner = ( void * ) pxOwner - -/* - * Access macro to set the value of the list item. In most cases the value is - * used to sort the list in descending order. - * - * \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE - * \ingroup LinkedList - */ -#define listSET_LIST_ITEM_VALUE( pxListItem, xValue ) ( pxListItem )->xItemValue = xValue - -/* - * Access macro the retrieve the value of the list item. The value can - * represent anything - for example a the priority of a task, or the time at - * which a task should be unblocked. - * - * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE - * \ingroup LinkedList - */ -#define listGET_LIST_ITEM_VALUE( pxListItem ) ( ( pxListItem )->xItemValue ) - -/* - * Access macro to determine if a list contains any items. The macro will - * only have the value true if the list is empty. - * - * \page listLIST_IS_EMPTY listLIST_IS_EMPTY - * \ingroup LinkedList - */ -#define listLIST_IS_EMPTY( pxList ) ( ( pxList )->uxNumberOfItems == ( unsigned portBASE_TYPE ) 0 ) - -/* - * Access macro to return the number of items in the list. - */ -#define listCURRENT_LIST_LENGTH( pxList ) ( ( pxList )->uxNumberOfItems ) - -/* - * Access function to obtain the owner of the next entry in a list. - * - * The list member pxIndex is used to walk through a list. Calling - * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list - * and returns that entries pxOwner parameter. Using multiple calls to this - * function it is therefore possible to move through every item contained in - * a list. - * - * The pxOwner parameter of a list item is a pointer to the object that owns - * the list item. In the scheduler this is normally a task control block. - * The pxOwner parameter effectively creates a two way link between the list - * item and its owner. - * - * @param pxList The list from which the next item owner is to be returned. - * - * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY - * \ingroup LinkedList - */ -#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList ) \ - /* Increment the index to the next item and return the item, ensuring */ \ - /* we don't return the marker used at the end of the list. */ \ - ( pxList )->pxIndex = ( pxList )->pxIndex->pxNext; \ - if( ( pxList )->pxIndex == ( xListItem * ) &( ( pxList )->xListEnd ) ) \ - { \ - ( pxList )->pxIndex = ( pxList )->pxIndex->pxNext; \ - } \ - pxTCB = ( pxList )->pxIndex->pvOwner - - -/* - * Access function to obtain the owner of the first entry in a list. Lists - * are normally sorted in ascending item value order. - * - * This function returns the pxOwner member of the first item in the list. - * The pxOwner parameter of a list item is a pointer to the object that owns - * the list item. In the scheduler this is normally a task control block. - * The pxOwner parameter effectively creates a two way link between the list - * item and its owner. - * - * @param pxList The list from which the owner of the head item is to be - * returned. - * - * \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY - * \ingroup LinkedList - */ -#define listGET_OWNER_OF_HEAD_ENTRY( pxList ) ( ( pxList->uxNumberOfItems != ( unsigned portBASE_TYPE ) 0 ) ? ( (&( pxList->xListEnd ))->pxNext->pvOwner ) : ( NULL ) ) - -/* - * Check to see if a list item is within a list. The list item maintains a - * "container" pointer that points to the list it is in. All this macro does - * is check to see if the container and the list match. - * - * @param pxList The list we want to know if the list item is within. - * @param pxListItem The list item we want to know if is in the list. - * @return pdTRUE is the list item is in the list, otherwise pdFALSE. - * pointer against - */ -#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( pxListItem )->pvContainer == ( void * ) pxList ) - -/* - * Must be called before a list is used! This initialises all the members - * of the list structure and inserts the xListEnd item into the list as a - * marker to the back of the list. - * - * @param pxList Pointer to the list being initialised. - * - * \page vListInitialise vListInitialise - * \ingroup LinkedList - */ -void vListInitialise( xList *pxList ); - -/* - * Must be called before a list item is used. This sets the list container to - * null so the item does not think that it is already contained in a list. - * - * @param pxItem Pointer to the list item being initialised. - * - * \page vListInitialiseItem vListInitialiseItem - * \ingroup LinkedList - */ -void vListInitialiseItem( xListItem *pxItem ); - -/* - * Insert a list item into a list. The item will be inserted into the list in - * a position determined by its item value (descending item value order). - * - * @param pxList The list into which the item is to be inserted. - * - * @param pxNewListItem The item to that is to be placed in the list. - * - * \page vListInsert vListInsert - * \ingroup LinkedList - */ -void vListInsert( xList *pxList, xListItem *pxNewListItem ); - -/* - * Insert a list item into a list. The item will be inserted in a position - * such that it will be the last item within the list returned by multiple - * calls to listGET_OWNER_OF_NEXT_ENTRY. - * - * The list member pvIndex is used to walk through a list. Calling - * listGET_OWNER_OF_NEXT_ENTRY increments pvIndex to the next item in the list. - * Placing an item in a list using vListInsertEnd effectively places the item - * in the list position pointed to by pvIndex. This means that every other - * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before - * the pvIndex parameter again points to the item being inserted. - * - * @param pxList The list into which the item is to be inserted. - * - * @param pxNewListItem The list item to be inserted into the list. - * - * \page vListInsertEnd vListInsertEnd - * \ingroup LinkedList - */ -void vListInsertEnd( xList *pxList, xListItem *pxNewListItem ); - -/* - * Remove an item from a list. The list item has a pointer to the list that - * it is in, so only the list item need be passed into the function. - * - * @param vListRemove The item to be removed. The item will remove itself from - * the list pointed to by it's pxContainer parameter. - * - * \page vListRemove vListRemove - * \ingroup LinkedList - */ -void vListRemove( xListItem *pxItemToRemove ); - - - -#endif - diff --git a/Source/include/portable.h b/Source/include/portable.h deleted file mode 100644 index 3d18ce7b5..000000000 --- a/Source/include/portable.h +++ /dev/null @@ -1,208 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http:www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http:www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/*----------------------------------------------------------- - * Portable layer API. Each function must be defined for each port. - *----------------------------------------------------------*/ - -#ifndef PORTABLE_H -#define PORTABLE_H - -/* Include the macro file relevant to the port being used. */ - -#ifdef OPEN_WATCOM_INDUSTRIAL_PC_PORT - #include "..\..\source\portable\owatcom\16bitdos\pc\portmacro.h" - typedef void ( __interrupt __far *pxISR )(); -#endif - -#ifdef OPEN_WATCOM_FLASH_LITE_186_PORT - #include "..\..\source\portable\owatcom\16bitdos\flsh186\portmacro.h" - typedef void ( __interrupt __far *pxISR )(); -#endif - -#ifdef GCC_MEGA_AVR - #include "../portable/GCC/ATMega323/portmacro.h" -#endif - -#ifdef IAR_MEGA_AVR - #include "../portable/IAR/ATMega323/portmacro.h" -#endif - -#ifdef MPLAB_PIC24_PORT - #include "..\..\Source\portable\MPLAB\PIC24_dsPIC\portmacro.h" -#endif - -#ifdef MPLAB_DSPIC_PORT - #include "..\..\Source\portable\MPLAB\PIC24_dsPIC\portmacro.h" -#endif - -#ifdef MPLAB_PIC18F_PORT - #include "..\..\source\portable\MPLAB\PIC18F\portmacro.h" -#endif - -#ifdef _FEDPICC - #include "libFreeRTOS/Include/portmacro.h" -#endif - -#ifdef SDCC_CYGNAL - #include "../../Source/portable/SDCC/Cygnal/portmacro.h" -#endif - -#ifdef GCC_ARM7 - #include "../../Source/portable/GCC/ARM7_LPC2000/portmacro.h" -#endif - -#ifdef GCC_MSP430 - #include "../../Source/portable/GCC/MSP430F449/portmacro.h" -#endif - -#ifdef ROWLEY_MSP430 - #include "../../Source/portable/Rowley/MSP430F449/portmacro.h" -#endif - -#ifdef KEIL_ARM7 - #include "..\..\Source\portable\Keil\ARM7\portmacro.h" -#endif - -#ifdef SAM7_GCC - #include "../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h" -#endif - -#ifdef SAM7_IAR - #include "..\..\Source\portable\IAR\AtmelSAM7S64\portmacro.h" -#endif - -#ifdef LPC2000_IAR - #include "..\..\Source\portable\IAR\LPC2000\portmacro.h" -#endif - -#ifdef STR71X_IAR - #include "..\..\Source\portable\IAR\STR71x\portmacro.h" -#endif - -#ifdef STR75X_IAR - #include "..\..\Source\portable\IAR\STR75x\portmacro.h" -#endif - -#ifdef STR75X_GCC - #include "..\..\Source\portable\GCC\STR75x\portmacro.h" -#endif - -#ifdef STR91X_IAR - #include "..\..\Source\portable\IAR\STR91x\portmacro.h" -#endif - -#ifdef GCC_H8S - #include "../../Source/portable/GCC/H8S2329/portmacro.h" -#endif - -#ifdef GCC_AT91FR40008 - #include "../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h" -#endif - -#ifdef RVDS_ARMCM3_LM3S102 - #include "../../Source/portable/RVDS/ARM_CM3/portmacro.h" -#endif - -#ifdef GCC_ARMCM3_LM3S102 - #include "../../Source/portable/GCC/ARM_CM3/portmacro.h" -#endif - -#ifdef IAR_ARMCM3_LM - #include "../../Source/portable/IAR/ARM_CM3/portmacro.h" -#endif - -#ifdef HCS12_CODE_WARRIOR - #include "../../Source/portable/CodeWarrior/HCS12/portmacro.h" -#endif - -#ifdef MICROBLAZE_GCC - #include "../../Source/portable/GCC/MicroBlaze/portmacro.h" -#endif - -#ifdef TERN_EE - #include "..\..\Source\portable\Paradigm\Tern_EE\small\portmacro.h" -#endif - -#ifdef GCC_HCS12 - #include "../../Source/portable/GCC/HCS12/portmacro.h" -#endif - -#ifdef GCC_MCF5235 - #include "../../Source/portable/GCC/MCF5235/portmacro.h" -#endif - -#ifdef BCC_INDUSTRIAL_PC_PORT - /* A short file name has to be used in place of the normal - FreeRTOSConfig.h when using the Borland compiler. */ - #include "frconfig.h" - #include "..\portable\BCC\16BitDOS\PC\prtmacro.h" - typedef void ( __interrupt __far *pxISR )(); -#endif - -#ifdef BCC_FLASH_LITE_186_PORT - /* A short file name has to be used in place of the normal - FreeRTOSConfig.h when using the Borland compiler. */ - #include "frconfig.h" - #include "..\portable\BCC\16BitDOS\flsh186\prtmacro.h" - typedef void ( __interrupt __far *pxISR )(); -#endif -/* - * Setup the stack of a new task so it is ready to be placed under the - * scheduler control. The registers have to be placed on the stack in - * the order that the port expects to find them. - */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ); - -/* - * Map to the memory management routines required for the port. - */ -void *pvPortMalloc( size_t xSize ); -void vPortFree( void *pv ); -void vPortInitialiseBlocks( void ); - -/* - * Setup the hardware ready for the scheduler to take control. This generally - * sets up a tick interrupt and sets timers for the correct tick frequency. - */ -portBASE_TYPE xPortStartScheduler( void ); - -/* - * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so - * the hardware is left in its original condition after the scheduler stops - * executing. - */ -void vPortEndScheduler( void ); - - -#endif /* PORTABLE_H */ - diff --git a/Source/include/projdefs.h b/Source/include/projdefs.h deleted file mode 100644 index 070af1c6d..000000000 --- a/Source/include/projdefs.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef PROJDEFS_H -#define PROJDEFS_H - -/* Defines to prototype to which task functions must conform. */ -typedef void (*pdTASK_CODE)( void * ); - -#define pdTRUE ( 1 ) -#define pdFALSE ( 0 ) - -#define pdPASS ( 1 ) -#define pdFAIL ( 0 ) -#define errQUEUE_EMPTY ( 0 ) -#define errQUEUE_FULL ( 0 ) - -/* Error definitions. */ -#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ( -1 ) -#define errNO_TASK_TO_RUN ( -2 ) -#define errQUEUE_BLOCKED ( -4 ) -#define errQUEUE_YIELD ( -5 ) - -#endif /* PROJDEFS_H */ - - - diff --git a/Source/include/queue.h b/Source/include/queue.h deleted file mode 100644 index 35056ab3c..000000000 --- a/Source/include/queue.h +++ /dev/null @@ -1,471 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef QUEUE_H -#define QUEUE_H - -typedef void * xQueueHandle; - -/** - * queue. h - * 
- xQueueHandle xQueueCreate( 
-                              unsigned portBASE_TYPE uxQueueLength, 
-                              unsigned portBASE_TYPE uxItemSize 
-                          );
- *
- * - * Creates a new queue instance. This allocates the storage required by the - * new queue and returns a handle for the queue. - * - * @param uxQueueLength The maximum number of items that the queue can contain. - * - * @param uxItemSize The number of bytes each item in the queue will require. - * Items are queued by copy, not by reference, so this is the number of bytes - * that will be copied for each posted item. Each item on the queue must be - * the same size. - * - * @return If the queue is successfully create then a handle to the newly - * created queue is returned. If the queue cannot be created then 0 is - * returned. - * - * Example usage: - 
- struct AMessage
- {
-    portCHAR ucMessageID;
-    portCHAR ucData[ 20 ];
- };
-
- void vATask( void *pvParameters )
- {
- xQueueHandle xQueue1, xQueue2;
-
-    // Create a queue capable of containing 10 unsigned long values.
-    xQueue1 = xQueueCreate( 10, sizeof( unsigned portLONG ) );
-    if( xQueue1 == 0 )
-    {
-        // Queue was not created and must not be used.
-    }
-
-    // Create a queue capable of containing 10 pointers to AMessage structures.
-    // These should be passed by pointer as they contain a lot of data.
-    xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
-    if( xQueue2 == 0 )
-    {
-        // Queue was not created and must not be used.
-    }
-
-    // ... Rest of task code.
- }
-
- * \defgroup xQueueCreate xQueueCreate - * \ingroup QueueManagement - */ -xQueueHandle xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize ); - -/** - * queue. h - * 
- portBASE_TYPE xQueueSend( 
-                             xQueueHandle xQueue, 
-                             const void * pvItemToQueue, 
-                             portTickType xTicksToWait 
-                         );
- *
- * - * Post an item on a queue. The item is queued by copy, not by reference. - * This function must not be called from an interrupt service routine. - * See xQueueSendFromISR () for an alternative which may be used in an ISR. - * - * @param xQueue The handle to the queue on which the item is to be posted. - * - * @param pvItemToQueue A pointer to the item that is to be placed on the - * queue. The size of the items the queue will hold was defined when the - * queue was created, so this many bytes will be copied from pvItemToQueue - * into the queue storage area. - * - * @param xTicksToWait The maximum amount of time the task should block - * waiting for space to become available on the queue, should it already - * be full. The call will return immediately if this is set to 0. The - * time is defined in tick periods so the constant portTICK_RATE_MS - * should be used to convert to real time if this is required. - * - * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL. - * - * Example usage: - 
- struct AMessage
- {
-    portCHAR ucMessageID;
-    portCHAR ucData[ 20 ];
- } xMessage;
-
- unsigned portLONG ulVar = 10UL;
-
- void vATask( void *pvParameters )
- {
- xQueueHandle xQueue1, xQueue2;
- struct AMessage *pxMessage;
-
-    // Create a queue capable of containing 10 unsigned long values.
-    xQueue1 = xQueueCreate( 10, sizeof( unsigned portLONG ) );
-
-    // Create a queue capable of containing 10 pointers to AMessage structures.
-    // These should be passed by pointer as they contain a lot of data.
-    xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
-
-    // ...
-
-    if( xQueue1 != 0 )
-    {
-        // Send an unsigned long.  Wait for 10 ticks for space to become 
-        // available if necessary.
-        if( xQueueSend( xQueue1, ( void * ) &ulVar, ( portTickType ) 10 ) != pdPASS )
-        {
-            // Failed to post the message, even after 10 ticks.
-        }
-    }
-
-    if( xQueue2 != 0 )
-    {
-        // Send a pointer to a struct AMessage object.  Don't block if the
-        // queue is already full.
-        pxMessage = & xMessage;
-        xQueueSend( xQueue2, ( void * ) &pxMessage, ( portTickType ) 0 );
-    }
-
-	// ... Rest of task code.
- }
-
- * \defgroup xQueueSend xQueueSend - * \ingroup QueueManagement - */ -signed portBASE_TYPE xQueueSend( xQueueHandle xQueue, const void * pvItemToQueue, portTickType xTicksToWait ); - -/** - * queue. h - * 
- portBASE_TYPE xQueueReceive( 
-                                xQueueHandle xQueue, 
-                                void *pvBuffer, 
-                                portTickType xTicksToWait 
-                            );
- * - * Receive an item from a queue. The item is received by copy so a buffer of - * adequate size must be provided. The number of bytes copied into the buffer - * was defined when the queue was created. - * - * This function must not be used in an interrupt service routine. See - * xQueueReceiveFromISR for an alternative that can. - * - * @param pxQueue The handle to the queue from which the item is to be - * received. - * - * @param pvBuffer Pointer to the buffer into which the received item will - * be copied. - * - * @param xTicksToWait The maximum amount of time the task should block - * waiting for an item to receive should the queue be empty at the time - * of the call. The time is defined in tick periods so the constant - * portTICK_RATE_MS should be used to convert to real time if this is required. - * - * @return pdTRUE if an item was successfully received from the queue, - * otherwise pdFALSE. - * - * Example usage: - 
- struct AMessage
- {
-    portCHAR ucMessageID;
-    portCHAR ucData[ 20 ];
- } xMessage;
-
- xQueueHandle xQueue;
- 
- // Task to create a queue and post a value.
- void vATask( void *pvParameters )
- {
- struct AMessage *pxMessage;
-
-    // Create a queue capable of containing 10 pointers to AMessage structures.
-    // These should be passed by pointer as they contain a lot of data.
-    xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
-    if( xQueue == 0 )
-    {
-        // Failed to create the queue.
-    }
-
-    // ...
-
-    // Send a pointer to a struct AMessage object.  Don't block if the
-    // queue is already full.
-    pxMessage = & xMessage;
-    xQueueSend( xQueue, ( void * ) &pxMessage, ( portTickType ) 0 );
-
-	// ... Rest of task code.
- }
-
- // Task to receive from the queue.
- void vADifferentTask( void *pvParameters )
- {
- struct AMessage *pxRxedMessage;
-
-    if( xQueue != 0 )
-    {
-        // Receive a message on the created queue.  Block for 10 ticks if a
-        // message is not immediately available.
-        if( xQueueReceive( xQueue, &( pxRxedMessage ), ( portTickType ) 10 ) )
-        {
-            // pcRxedMessage now points to the struct AMessage variable posted
-            // by vATask.
-        }
-    }
-
-	// ... Rest of task code.
- }
-
- * \defgroup xQueueReceive xQueueReceive - * \ingroup QueueManagement - */ -signed portBASE_TYPE xQueueReceive( xQueueHandle xQueue, void *pvBuffer, portTickType xTicksToWait ); - -/** - * queue. h - * 
unsigned portBASE_TYPE uxQueueMessagesWaiting( xQueueHandle xQueue );
- * - * Return the number of messages stored in a queue. - * - * @param xQueue A handle to the queue being queried. - * - * @return The number of messages available in the queue. - * - * \page uxQueueMessagesWaiting uxQueueMessagesWaiting - * \ingroup QueueManagement - */ -unsigned portBASE_TYPE uxQueueMessagesWaiting( xQueueHandle xQueue ); - -/** - * queue. h - * 
void vQueueDelete( xQueueHandle xQueue );
- * - * Delete a queue - freeing all the memory allocated for storing of items - * placed on the queue. - * - * @param xQueue A handle to the queue to be deleted. - * - * \page vQueueDelete vQueueDelete - * \ingroup QueueManagement - */ -void vQueueDelete( xQueueHandle xQueue ); - -/** - * queue. h - * 
- portBASE_TYPE xQueueSendFromISR( 
-                                    xQueueHandle pxQueue, 
-                                    const void *pvItemToQueue, 
-                                    portBASE_TYPE xTaskPreviouslyWoken 
-                                );
-
- * - * Post an item on a queue. It is safe to use this function from within an - * interrupt service routine. - * - * Items are queued by copy not reference so it is preferable to only - * queue small items, especially when called from an ISR. In most cases - * it would be preferable to store a pointer to the item being queued. - * - * @param xQueue The handle to the queue on which the item is to be posted. - * - * @param pvItemToQueue A pointer to the item that is to be placed on the - * queue. The size of the items the queue will hold was defined when the - * queue was created, so this many bytes will be copied from pvItemToQueue - * into the queue storage area. - * - * @param cTaskPreviouslyWoken This is included so an ISR can post onto - * the same queue multiple times from a single interrupt. The first call - * should always pass in pdFALSE. Subsequent calls should pass in - * the value returned from the previous call. See the file serial .c in the - * PC port for a good example of this mechanism. - * - * @return pdTRUE if a task was woken by posting onto the queue. This is - * used by the ISR to determine if a context switch may be required following - * the ISR. - * - * Example usage for buffered IO (where the ISR can obtain more than one value - * per call): - 
- void vBufferISR( void )
- {
- portCHAR cIn;
- portBASE_TYPE xTaskWokenByPost;
-
-    // We have not woken a task at the start of the ISR.
-    cTaskWokenByPost = pdFALSE;
-
-    // Loop until the buffer is empty.
-    do
-    {
-        // Obtain a byte from the buffer.
-        cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );						
-
-        // Post the byte.  The first time round the loop cTaskWokenByPost
-        // will be pdFALSE.  If the queue send causes a task to wake we do
-        // not want the task to run until we have finished the ISR, so
-        // xQueueSendFromISR does not cause a context switch.  Also we 
-        // don't want subsequent posts to wake any other tasks, so we store
-        // the return value back into cTaskWokenByPost so xQueueSendFromISR
-        // knows not to wake any task the next iteration of the loop.
-        xTaskWokenByPost = xQueueSendFromISR( xRxQueue, &cIn, cTaskWokenByPost );
-
-    } while( portINPUT_BYTE( BUFFER_COUNT ) );
-
-    // Now the buffer is empty we can switch context if necessary.
-    if( cTaskWokenByPost )
-    {
-        taskYIELD ();
-    }
- }
-
- * - * \defgroup xQueueSendFromISR xQueueSendFromISR - * \ingroup QueueManagement - */ -signed portBASE_TYPE xQueueSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xTaskPreviouslyWoken ); - -/** - * queue. h - * 
- portBASE_TYPE xQueueReceiveFromISR( 
-                                       xQueueHandle pxQueue, 
-                                       void *pvBuffer, 
-                                       portBASE_TYPE *pxTaskWoken 
-                                   ); 
- *
- * - * Receive an item from a queue. It is safe to use this function from within an - * interrupt service routine. - * - * @param pxQueue The handle to the queue from which the item is to be - * received. - * - * @param pvBuffer Pointer to the buffer into which the received item will - * be copied. - * - * @param pxTaskWoken A task may be blocked waiting for space to become - * available on the queue. If xQueueReceiveFromISR causes such a task to - * unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will - * remain unchanged. - * - * @return pdTRUE if an item was successfully received from the queue, - * otherwise pdFALSE. - * - * Example usage: - 
- 
- xQueueHandle xQueue;
- 
- // Function to create a queue and post some values.
- void vAFunction( void *pvParameters )
- {
- portCHAR cValueToPost;
- const portTickType xBlockTime = ( portTickType )0xff;
-
-    // Create a queue capable of containing 10 characters.
-    xQueue = xQueueCreate( 10, sizeof( portCHAR ) );
-    if( xQueue == 0 )
-    {
-        // Failed to create the queue.
-    }
-
-    // ...
-
-    // Post some characters that will be used within an ISR.  If the queue
-    // is full then this task will block for xBlockTime ticks.
-    cValueToPost = 'a';
-    xQueueSend( xQueue, ( void * ) &cValueToPost, xBlockTime );
-    cValueToPost = 'b';
-    xQueueSend( xQueue, ( void * ) &cValueToPost, xBlockTime );
-
-    // ... keep posting characters ... this task may block when the queue
-    // becomes full.
-
-    cValueToPost = 'c';
-    xQueueSend( xQueue, ( void * ) &cValueToPost, xBlockTime );
- }
-
- // ISR that outputs all the characters received on the queue. 
- void vISR_Routine( void )
- {
- portBASE_TYPE xTaskWokenByReceive = pdFALSE;
- portCHAR cRxedChar;
-
-    while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) )
-    {
-        // A character was received.  Output the character now.
-        vOutputCharacter( cRxedChar );
-
-        // If removing the character from the queue woke the task that was 
-        // posting onto the queue cTaskWokenByReceive will have been set to
-        // pdTRUE.  No matter how many times this loop iterates only one
-        // task will be woken.
-    }
-
-    if( cTaskWokenByPost != ( portCHAR ) pdFALSE;
-    {
-        taskYIELD ();
-    }
- }
-
- * \defgroup xQueueReceiveFromISR xQueueReceiveFromISR - * \ingroup QueueManagement - */ -signed portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken ); - - -/* - * The functions defined above are for passing data to and from tasks. The - * functions below are the equivalents for passing data to and from - * co-rtoutines. - * - * These functions are called from the co-routine macro implementation and - * should not be called directly from application code. Instead use the macro - * wrappers defined within croutine.h. - */ -signed portBASE_TYPE xQueueCRSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xCoRoutinePreviouslyWoken ); -signed portBASE_TYPE xQueueCRReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken ); -signed portBASE_TYPE xQueueCRSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait ); -signed portBASE_TYPE xQueueCRReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait ); - -#endif - diff --git a/Source/include/semphr.h b/Source/include/semphr.h deleted file mode 100644 index 9d410ae81..000000000 --- a/Source/include/semphr.h +++ /dev/null @@ -1,289 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#include "queue.h" - -#ifndef SEMAPHORE_H -#define SEMAPHORE_H - -typedef xQueueHandle xSemaphoreHandle; - -#define semBINARY_SEMAPHORE_QUEUE_LENGTH ( ( unsigned portCHAR ) 1 ) -#define semSEMAPHORE_QUEUE_ITEM_LENGTH ( ( unsigned portCHAR ) 0 ) -#define semGIVE_BLOCK_TIME ( ( portTickType ) 0 ) - - -/** - * semphr. h - * 
vSemaphoreCreateBinary( xSemaphoreHandle xSemaphore )
- * - * Macro that implements a semaphore by using the existing queue mechanism. - * The queue length is 1 as this is a binary semaphore. The data size is 0 - * as we don't want to actually store any data - we just want to know if the - * queue is empty or full. - * - * @param xSemaphore Handle to the created semaphore. Should be of type xSemaphoreHandle. - * - * Example usage: - 
- xSemaphoreHandle xSemaphore;
-
- void vATask( void * pvParameters )
- {
-    // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().
-    // This is a macro so pass the variable in directly.
-    vSemaphoreCreateBinary( xSemaphore );
-
-    if( xSemaphore != NULL )
-    {
-        // The semaphore was created successfully.
-        // The semaphore can now be used.  
-    }
- }
-
- * \defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary - * \ingroup Semaphores - */ -#define vSemaphoreCreateBinary( xSemaphore ) { \ - xSemaphore = xQueueCreate( ( unsigned portCHAR ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH ); \ - if( xSemaphore != NULL ) \ - { \ - xSemaphoreGive( xSemaphore ); \ - } \ - } - -/** - * semphr. h - * xSemaphoreTake( - * xSemaphoreHandle xSemaphore, - * portTickType xBlockTime - * ) - * - * Macro to obtain a semaphore. The semaphore must of been created using - * vSemaphoreCreateBinary (). - * - * @param xSemaphore A handle to the semaphore being obtained. This is the - * handle returned by vSemaphoreCreateBinary (); - * - * @param xBlockTime The time in ticks to wait for the semaphore to become - * available. The macro portTICK_RATE_MS can be used to convert this to a - * real time. A block time of zero can be used to poll the semaphore. - * - * @return pdTRUE if the semaphore was obtained. pdFALSE if xBlockTime - * expired without the semaphore becoming available. - * - * Example usage: - 
- xSemaphoreHandle xSemaphore = NULL;
-
- // A task that creates a semaphore.
- void vATask( void * pvParameters )
- {
-    // Create the semaphore to guard a shared resource.
-    vSemaphoreCreateBinary( xSemaphore );
- }
-
- // A task that uses the semaphore.
- void vAnotherTask( void * pvParameters )
- {
-    // ... Do other things.
-
-    if( xSemaphore != NULL )
-    {
-        // See if we can obtain the semaphore.  If the semaphore is not available
-        // wait 10 ticks to see if it becomes free.	
-        if( xSemaphoreTake( xSemaphore, ( portTickType ) 10 ) == pdTRUE )
-        {
-            // We were able to obtain the semaphore and can now access the
-            // shared resource.
-
-            // ...
-
-            // We have finished accessing the shared resource.  Release the 
-            // semaphore.
-            xSemaphoreGive( xSemaphore );
-        }
-        else
-        {
-            // We could not obtain the semaphore and can therefore not access
-            // the shared resource safely.
-        }
-    }
- }
-
- * \defgroup xSemaphoreTake xSemaphoreTake - * \ingroup Semaphores - */ -#define xSemaphoreTake( xSemaphore, xBlockTime ) xQueueReceive( ( xQueueHandle ) xSemaphore, NULL, xBlockTime ) - -/** - * semphr. h - * 
xSemaphoreGive( xSemaphoreHandle xSemaphore )
- * - * Macro to release a semaphore. The semaphore must of been created using - * vSemaphoreCreateBinary (), and obtained using sSemaphoreTake (). - * - * This must not be used from an ISR. See xSemaphoreGiveFromISR () for - * an alternative which can be used from an ISR. - * - * @param xSemaphore A handle to the semaphore being released. This is the - * handle returned by vSemaphoreCreateBinary (); - * - * @return pdTRUE if the semaphore was released. pdFALSE if an error occurred. - * Semaphores are implemented using queues. An error can occur if there is - * no space on the queue to post a message - indicating that the - * semaphore was not first obtained correctly. - * - * Example usage: - 
- xSemaphoreHandle xSemaphore = NULL;
-
- void vATask( void * pvParameters )
- {
-    // Create the semaphore to guard a shared resource.
-    vSemaphoreCreateBinary( xSemaphore );
-
-    if( xSemaphore != NULL )
-    {
-        if( xSemaphoreGive( xSemaphore ) != pdTRUE )
-        {
-            // We would expect this call to fail because we cannot give
-            // a semaphore without first "taking" it!
-        }
-
-        // Obtain the semaphore - don't block if the semaphore is not
-        // immediately available.
-        if( xSemaphoreTake( xSemaphore, ( portTickType ) 0 ) )
-        {
-            // We now have the semaphore and can access the shared resource.
-
-            // ...
-
-            // We have finished accessing the shared resource so can free the
-            // semaphore.
-            if( xSemaphoreGive( xSemaphore ) != pdTRUE )
-            {
-                // We would not expect this call to fail because we must have
-                // obtained the semaphore to get here.
-            }
-        }
-    }
- }
-
- * \defgroup xSemaphoreGive xSemaphoreGive - * \ingroup Semaphores - */ -#define xSemaphoreGive( xSemaphore ) xQueueSend( ( xQueueHandle ) xSemaphore, NULL, semGIVE_BLOCK_TIME ) - -/** - * semphr. h - * 
- xSemaphoreGiveFromISR( 
-                          xSemaphoreHandle xSemaphore, 
-                          portSHORT sTaskPreviouslyWoken 
-                      )
- * - * Macro to release a semaphore. The semaphore must of been created using - * vSemaphoreCreateBinary (), and obtained using xSemaphoreTake (). - * - * This macro can be used from an ISR. - * - * @param xSemaphore A handle to the semaphore being released. This is the - * handle returned by vSemaphoreCreateBinary (); - * - * @param sTaskPreviouslyWoken This is included so an ISR can make multiple calls - * to xSemaphoreGiveFromISR () from a single interrupt. The first call - * should always pass in pdFALSE. Subsequent calls should pass in - * the value returned from the previous call. See the file serial .c in the - * PC port for a good example of using xSemaphoreGiveFromISR (). - * - * @return pdTRUE if a task was woken by releasing the semaphore. This is - * used by the ISR to determine if a context switch may be required following - * the ISR. - * - * Example usage: - 
- #define LONG_TIME 0xffff
- #define TICKS_TO_WAIT	10
- xSemaphoreHandle xSemaphore = NULL;
-
- // Repetitive task.
- void vATask( void * pvParameters )
- {
-    for( ;; )
-    {
-        // We want this task to run every 10 ticks or a timer.  The semaphore 
-        // was created before this task was started
-
-        // Block waiting for the semaphore to become available.
-        if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE )
-        {
-            // It is time to execute.
-
-            // ...
-
-            // We have finished our task.  Return to the top of the loop where
-            // we will block on the semaphore until it is time to execute 
-            // again.
-        }
-    }
- }
-
- // Timer ISR
- void vTimerISR( void * pvParameters )
- {
- static unsigned portCHAR ucLocalTickCount = 0;
-
-    // A timer tick has occurred.
-
-    // ... Do other time functions.
-
-    // Is it time for vATask () to run?
-    ucLocalTickCount++;
-    if( ucLocalTickCount >= TICKS_TO_WAIT )
-    {
-        // Unblock the task by releasing the semaphore.
-        xSemaphoreGive( xSemaphore );
-
-        // Reset the count so we release the semaphore again in 10 ticks time.
-        ucLocalTickCount = 0;
-    }
- }
-
- * \defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR - * \ingroup Semaphores - */ -#define xSemaphoreGiveFromISR( xSemaphore, xTaskPreviouslyWoken ) xQueueSendFromISR( ( xQueueHandle ) xSemaphore, NULL, xTaskPreviouslyWoken ) - - -#endif - diff --git a/Source/include/task.h b/Source/include/task.h deleted file mode 100644 index 0d3eb86c1..000000000 --- a/Source/include/task.h +++ /dev/null @@ -1,951 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef TASK_H -#define TASK_H - -#include "portable.h" -#include "list.h" - -/*----------------------------------------------------------- - * MACROS AND DEFINITIONS - *----------------------------------------------------------*/ - -#define tskKERNEL_VERSION_NUMBER "V4.2.0" - -/** - * task. h - * - * Type by which tasks are referenced. For example, a call to xTaskCreate - * returns (via a pointer parameter) an xTaskHandle variable that can then - * be used as a parameter to vTaskDelete to delete the task. - * - * \page xTaskHandle xTaskHandle - * \ingroup Tasks - */ -typedef void * xTaskHandle; - -/* - * Used internally only. - */ -typedef struct xTIME_OUT -{ - portBASE_TYPE xOverflowCount; - portTickType xTimeOnEntering; -} xTimeOutType; - -/* - * Defines the priority used by the idle task. This must not be modified. - * - * \ingroup TaskUtils - */ -#define tskIDLE_PRIORITY ( ( unsigned portBASE_TYPE ) 0 ) - -/** - * task. h - * - * Macro for forcing a context switch. - * - * \page taskYIELD taskYIELD - * \ingroup SchedulerControl - */ -#define taskYIELD() portYIELD() - -/** - * task. h - * - * Macro to mark the start of a critical code region. Preemptive context - * switches cannot occur when in a critical region. - * - * NOTE: This may alter the stack (depending on the portable implementation) - * so must be used with care! - * - * \page taskENTER_CRITICAL taskENTER_CRITICAL - * \ingroup SchedulerControl - */ -#define taskENTER_CRITICAL() portENTER_CRITICAL() - -/** - * task. h - * - * Macro to mark the end of a critical code region. Preemptive context - * switches cannot occur when in a critical region. - * - * NOTE: This may alter the stack (depending on the portable implementation) - * so must be used with care! - * - * \page taskEXIT_CRITICAL taskEXIT_CRITICAL - * \ingroup SchedulerControl - */ -#define taskEXIT_CRITICAL() portEXIT_CRITICAL() - -/** - * task. h - * - * Macro to disable all maskable interrupts. - * - * \page taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS - * \ingroup SchedulerControl - */ -#define taskDISABLE_INTERRUPTS() portDISABLE_INTERRUPTS() - -/** - * task. h - * - * Macro to enable microcontroller interrupts. - * - * \page taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS - * \ingroup SchedulerControl - */ -#define taskENABLE_INTERRUPTS() portENABLE_INTERRUPTS() - - -/*----------------------------------------------------------- - * TASK CREATION API - *----------------------------------------------------------*/ - -/** - * task. h - *
- portBASE_TYPE xTaskCreate(
-                              pdTASK_CODE pvTaskCode,
-                              const portCHAR * const pcName,
-                              unsigned portSHORT usStackDepth,
-                              void *pvParameters,
-                              unsigned portBASE_TYPE uxPriority,
-                              xTaskHandle *pvCreatedTask
-                          );
- * - * Create a new task and add it to the list of tasks that are ready to run. - * - * @param pvTaskCode Pointer to the task entry function. Tasks - * must be implemented to never return (i.e. continuous loop). - * - * @param pcName A descriptive name for the task. This is mainly used to - * facilitate debugging. Max length defined by tskMAX_TASK_NAME_LEN - default - * is 16. - * - * @param usStackDepth The size of the task stack specified as the number of - * variables the stack can hold - not the number of bytes. For example, if - * the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes - * will be allocated for stack storage. - * - * @param pvParameters Pointer that will be used as the parameter for the task - * being created. - * - * @param uxPriority The priority at which the task should run. - * - * @param pvCreatedTask Used to pass back a handle by which the created task - * can be referenced. - * - * @return pdPASS if the task was successfully created and added to a ready - * list, otherwise an error code defined in the file errors. h - * - * Example usage: - 
- // Task to be created.
- void vTaskCode( void * pvParameters )
- {
-     for( ;; )
-     {
-         // Task code goes here.
-     }
- }
-
- // Function that creates a task.
- void vOtherFunction( void )
- {
- unsigned char ucParameterToPass;
- xTaskHandle xHandle;
-		
-     // Create the task, storing the handle.
-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle );
-		
-     // Use the handle to delete the task.
-     vTaskDelete( xHandle );
- }
-
- * \defgroup xTaskCreate xTaskCreate - * \ingroup Tasks - */ -signed portBASE_TYPE xTaskCreate( pdTASK_CODE pvTaskCode, const signed portCHAR * const pcName, unsigned portSHORT usStackDepth, void *pvParameters, unsigned portBASE_TYPE uxPriority, xTaskHandle *pvCreatedTask ); - -/** - * task. h - * 
void vTaskDelete( xTaskHandle pxTask );
- * - * INCLUDE_vTaskDelete must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Remove a task from the RTOS real time kernels management. The task being - * deleted will be removed from all ready, blocked, suspended and event lists. - * - * NOTE: The idle task is responsible for freeing the kernel allocated - * memory from tasks that have been deleted. It is therefore important that - * the idle task is not starved of microcontroller processing time if your - * application makes any calls to vTaskDelete (). Memory allocated by the - * task code is not automatically freed, and should be freed before the task - * is deleted. - * - * See the demo application file death.c for sample code that utilises - * vTaskDelete (). - * - * @param pxTask The handle of the task to be deleted. Passing NULL will - * cause the calling task to be deleted. - * - * Example usage: - 
- void vOtherFunction( void )
- {
- xTaskHandle xHandle;
-		
-     // Create the task, storing the handle.
-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
-		
-     // Use the handle to delete the task.
-     vTaskDelete( xHandle );
- }
-
- * \defgroup vTaskDelete vTaskDelete - * \ingroup Tasks - */ -void vTaskDelete( xTaskHandle pxTask ); - - -/*----------------------------------------------------------- - * TASK CONTROL API - *----------------------------------------------------------*/ - -/** - * task. h - * 
void vTaskDelay( portTickType xTicksToDelay );
- * - * Delay a task for a given number of ticks. The actual time that the - * task remains blocked depends on the tick rate. The constant - * portTICK_RATE_MS can be used to calculate real time from the tick - * rate - with the resolution of one tick period. - * - * INCLUDE_vTaskDelay must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * @param xTicksToDelay The amount of time, in tick periods, that - * the calling task should block. - * - * Example usage: - 
- // Wait 10 ticks before performing an action.
- // NOTE:
- // This is for demonstration only and would be better achieved
- // using vTaskDelayUntil ().
- void vTaskFunction( void * pvParameters )
- {
- portTickType xDelay, xNextTime;
-
-     // Calc the time at which we want to perform the action
-     // next.
-     xNextTime = xTaskGetTickCount () + ( portTickType ) 10;
-
-     for( ;; )
-     {
-         xDelay = xNextTime - xTaskGetTickCount ();
-         xNextTime += ( portTickType ) 10;
-
-         // Guard against overflow
-         if( xDelay <= ( portTickType ) 10 )
-         {
-             vTaskDelay( xDelay );
-         }
-
-         // Perform action here.
-     }
- }
-
- * \defgroup vTaskDelay vTaskDelay - * \ingroup TaskCtrl - */ -void vTaskDelay( portTickType xTicksToDelay ); - -/** - * task. h - * 
void vTaskDelayUntil( portTickType *pxPreviousWakeTime, portTickType xTimeIncrement );
- * - * INCLUDE_vTaskDelayUntil must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Delay a task until a specified time. This function can be used by cyclical - * tasks to ensure a constant execution frequency. - * - * This function differs from vTaskDelay () in one important aspect: vTaskDelay () will - * cause a task to block for the specified number of ticks from the time vTaskDelay () is - * called. It is therefore difficult to use vTaskDelay () by itself to generate a fixed - * execution frequency as the time between a task starting to execute and that task - * calling vTaskDelay () may not be fixed [the task may take a different path though the - * code between calls, or may get interrupted or preempted a different number of times - * each time it executes]. - * - * Whereas vTaskDelay () specifies a wake time relative to the time at which the function - * is called, vTaskDelayUntil () specifies the absolute (exact) time at which it wishes to - * unblock. - * - * The constant portTICK_RATE_MS can be used to calculate real time from the tick - * rate - with the resolution of one tick period. - * - * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the - * task was last unblocked. The variable must be initialised with the current time - * prior to its first use (see the example below). Following this the variable is - * automatically updated within vTaskDelayUntil (). - * - * @param xTimeIncrement The cycle time period. The task will be unblocked at - * time *pxPreviousWakeTime + xTimeIncrement. Calling vTaskDelayUntil with the - * same xTimeIncrement parameter value will cause the task to execute with - * a fixed interface period. - * - * Example usage: - 
- // Perform an action every 10 ticks.
- void vTaskFunction( void * pvParameters )
- {
- portTickType xLastWakeTime;
- const portTickType xFrequency = 10;
-
-     // Initialise the xLastWakeTime variable with the current time.
-     xLastWakeTime = xTaskGetTickCount ();
-     for( ;; )
-     {
-         // Wait for the next cycle.
-         vTaskDelayUntil( &xLastWakeTime, xFrequency );
-
-         // Perform action here.
-     }
- }
-
- * \defgroup vTaskDelayUntil vTaskDelayUntil - * \ingroup TaskCtrl - */ -void vTaskDelayUntil( portTickType *pxPreviousWakeTime, portTickType xTimeIncrement ); - -/** - * task. h - * 
unsigned portBASE_TYPE uxTaskPriorityGet( xTaskHandle pxTask );
- * - * INCLUDE_xTaskPriorityGet must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Obtain the priority of any task. - * - * @param pxTask Handle of the task to be queried. Passing a NULL - * handle results in the priority of the calling task being returned. - * - * @return The priority of pxTask. - * - * Example usage: - 
- void vAFunction( void )
- {
- xTaskHandle xHandle;
-		
-     // Create a task, storing the handle.
-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
-		
-     // ...
-
-     // Use the handle to obtain the priority of the created task.
-     // It was created with tskIDLE_PRIORITY, but may have changed
-     // it itself.
-     if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY )
-     {
-         // The task has changed it's priority.
-     }
-
-     // ...
-
-     // Is our priority higher than the created task?
-     if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) )
-     {
-         // Our priority (obtained using NULL handle) is higher.
-     }
- }
-
- * \defgroup uxTaskPriorityGet uxTaskPriorityGet - * \ingroup TaskCtrl - */ -unsigned portBASE_TYPE uxTaskPriorityGet( xTaskHandle pxTask ); - -/** - * task. h - * 
void vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority );
- * - * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Set the priority of any task. - * - * A context switch will occur before the function returns if the priority - * being set is higher than the currently executing task. - * - * @param pxTask Handle to the task for which the priority is being set. - * Passing a NULL handle results in the priority of the calling task being set. - * - * @param uxNewPriority The priority to which the task will be set. - * - * Example usage: - 
- void vAFunction( void )
- {
- xTaskHandle xHandle;
-		
-     // Create a task, storing the handle.
-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
-
-     // ...
-
-     // Use the handle to raise the priority of the created task.
-     vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 );
-
-     // ...
-
-     // Use a NULL handle to raise our priority to the same value.
-     vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 );
- }
-
- * \defgroup vTaskPrioritySet vTaskPrioritySet - * \ingroup TaskCtrl - */ -void vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority ); - -/** - * task. h - * 
void vTaskSuspend( xTaskHandle pxTaskToSuspend );
- * - * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Suspend any task. When suspended a task will never get any microcontroller - * processing time, no matter what its priority. - * - * Calls to vTaskSuspend are not accumulative - - * i.e. calling vTaskSuspend () twice on the same task still only requires one - * call to vTaskResume () to ready the suspended task. - * - * @param pxTaskToSuspend Handle to the task being suspended. Passing a NULL - * handle will cause the calling task to be suspended. - * - * Example usage: - 
- void vAFunction( void )
- {
- xTaskHandle xHandle;
-		
-     // Create a task, storing the handle.
-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
-		
-     // ...
-
-     // Use the handle to suspend the created task.
-     vTaskSuspend( xHandle );
-
-     // ...
-		
-     // The created task will not run during this period, unless
-     // another task calls vTaskResume( xHandle ).
-		
-     //...
-		
-
-     // Suspend ourselves.
-     vTaskSuspend( NULL );
-
-     // We cannot get here unless another task calls vTaskResume
-     // with our handle as the parameter.
- }
-
- * \defgroup vTaskSuspend vTaskSuspend - * \ingroup TaskCtrl - */ -void vTaskSuspend( xTaskHandle pxTaskToSuspend ); - -/** - * task. h - * 
void vTaskResume( xTaskHandle pxTaskToResume );
- * - * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Resumes a suspended task. - * - * A task that has been suspended by one of more calls to vTaskSuspend () - * will be made available for running again by a single call to - * vTaskResume (). - * - * @param pxTaskToResume Handle to the task being readied. - * - * Example usage: - 
- void vAFunction( void )
- {
- xTaskHandle xHandle;
-		
-     // Create a task, storing the handle.
-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
-		
-     // ...
-
-     // Use the handle to suspend the created task.
-     vTaskSuspend( xHandle );
-
-     // ...
-	
-     // The created task will not run during this period, unless
-     // another task calls vTaskResume( xHandle ).
-		
-     //...
-		
-
-     // Resume the suspended task ourselves.
-     vTaskResume( xHandle );
-
-     // The created task will once again get microcontroller processing
-     // time in accordance with it priority within the system.
- }
-
- * \defgroup vTaskResume vTaskResume - * \ingroup TaskCtrl - */ -void vTaskResume( xTaskHandle pxTaskToResume ); - -/** - * task. h - * 
void xTaskResumeFromISR( xTaskHandle pxTaskToResume );
- * - * INCLUDE_xTaskResumeFromISR must be defined as 1 for this function to be - * available. See the configuration section for more information. - * - * An implementation of vTaskResume() that can be called from within an ISR. - * - * A task that has been suspended by one of more calls to vTaskSuspend () - * will be made available for running again by a single call to - * xTaskResumeFromISR (). - * - * @param pxTaskToResume Handle to the task being readied. - * - * \defgroup vTaskResumeFromISR vTaskResumeFromISR - * \ingroup TaskCtrl - */ -portBASE_TYPE xTaskResumeFromISR( xTaskHandle pxTaskToResume ); - -/*----------------------------------------------------------- - * SCHEDULER CONTROL - *----------------------------------------------------------*/ - -/** - * task. h - * 
void vTaskStartScheduler( void );
- * - * Starts the real time kernel tick processing. After calling the kernel - * has control over which tasks are executed and when. This function - * does not return until an executing task calls vTaskEndScheduler (). - * - * At least one task should be created via a call to xTaskCreate () - * before calling vTaskStartScheduler (). The idle task is created - * automatically when the first application task is created. - * - * See the demo application file main.c for an example of creating - * tasks and starting the kernel. - * - * Example usage: - 
- void vAFunction( void )
- {
-     // Create at least one task before starting the kernel.
-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
-
-     // Start the real time kernel with preemption.
-     vTaskStartScheduler ();
-
-     // Will not get here unless a task calls vTaskEndScheduler ()
- }
-
- * - * \defgroup vTaskStartScheduler vTaskStartScheduler - * \ingroup SchedulerControl - */ -void vTaskStartScheduler( void ); - -/** - * task. h - * 
void vTaskEndScheduler( void );
- * - * Stops the real time kernel tick. All created tasks will be automatically - * deleted and multitasking (either preemptive or cooperative) will - * stop. Execution then resumes from the point where vTaskStartScheduler () - * was called, as if vTaskStartScheduler () had just returned. - * - * See the demo application file main. c in the demo/PC directory for an - * example that uses vTaskEndScheduler (). - * - * vTaskEndScheduler () requires an exit function to be defined within the - * portable layer (see vPortEndScheduler () in port. c for the PC port). This - * performs hardware specific operations such as stopping the kernel tick. - * - * vTaskEndScheduler () will cause all of the resources allocated by the - * kernel to be freed - but will not free resources allocated by application - * tasks. - * - * Example usage: - 
- void vTaskCode( void * pvParameters )
- {
-     for( ;; )
-     {
-         // Task code goes here.
-
-         // At some point we want to end the real time kernel processing
-         // so call ...
-         vTaskEndScheduler ();
-     }
- }
-
- void vAFunction( void )
- {
-     // Create at least one task before starting the kernel.
-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
-
-     // Start the real time kernel with preemption.
-     vTaskStartScheduler ();
-
-     // Will only get here when the vTaskCode () task has called
-     // vTaskEndScheduler ().  When we get here we are back to single task
-     // execution.
- }
-
- * - * \defgroup vTaskEndScheduler vTaskEndScheduler - * \ingroup SchedulerControl - */ -void vTaskEndScheduler( void ); - -/** - * task. h - * 
void vTaskSuspendAll( void );
- * - * Suspends all real time kernel activity while keeping interrupts (including the - * kernel tick) enabled. - * - * After calling vTaskSuspendAll () the calling task will continue to execute - * without risk of being swapped out until a call to xTaskResumeAll () has been - * made. - * - * Example usage: - 
- void vTask1( void * pvParameters )
- {
-     for( ;; )
-     {
-         // Task code goes here.
-
-         // ...
-
-         // At some point the task wants to perform a long operation during
-         // which it does not want to get swapped out.  It cannot use
-         // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
-         // operation may cause interrupts to be missed - including the
-         // ticks.
-
-         // Prevent the real time kernel swapping out the task.
-         vTaskSuspendAll ();
-
-         // Perform the operation here.  There is no need to use critical
-         // sections as we have all the microcontroller processing time.
-         // During this time interrupts will still operate and the kernel
-         // tick count will be maintained.
-
-         // ...
-
-         // The operation is complete.  Restart the kernel.
-         xTaskResumeAll ();
-     }
- }
-
- * \defgroup vTaskSuspendAll vTaskSuspendAll - * \ingroup SchedulerControl - */ -void vTaskSuspendAll( void ); - -/** - * task. h - * 
portCHAR xTaskResumeAll( void );
- * - * Resumes real time kernel activity following a call to vTaskSuspendAll (). - * After a call to vTaskSuspendAll () the kernel will take control of which - * task is executing at any time. - * - * @return If resuming the scheduler caused a context switch then pdTRUE is - * returned, otherwise pdFALSE is returned. - * - * Example usage: - 
- void vTask1( void * pvParameters )
- {
-     for( ;; )
-     {
-         // Task code goes here.
-
-         // ...
-
-         // At some point the task wants to perform a long operation during
-         // which it does not want to get swapped out.  It cannot use
-         // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
-         // operation may cause interrupts to be missed - including the
-         // ticks.
-
-         // Prevent the real time kernel swapping out the task.
-         vTaskSuspendAll ();
-
-         // Perform the operation here.  There is no need to use critical
-         // sections as we have all the microcontroller processing time.
-         // During this time interrupts will still operate and the real
-         // time kernel tick count will be maintained.
-
-         // ...
-
-         // The operation is complete.  Restart the kernel.  We want to force
-         // a context switch - but there is no point if resuming the scheduler
-         // caused a context switch already.
-         if( !xTaskResumeAll () )
-         {
-              taskYIELD ();
-         }
-     }
- }
-
- * \defgroup xTaskResumeAll xTaskResumeAll - * \ingroup SchedulerControl - */ -signed portBASE_TYPE xTaskResumeAll( void ); - - -/*----------------------------------------------------------- - * TASK UTILITIES - *----------------------------------------------------------*/ - -/** - * task. h - * 
volatile portTickType xTaskGetTickCount( void );
- * - * @return The count of ticks since vTaskStartScheduler was called. - * - * \page xTaskGetTickCount xTaskGetTickCount - * \ingroup TaskUtils - */ -portTickType xTaskGetTickCount( void ); - -/** - * task. h - * 
unsigned portSHORT uxTaskGetNumberOfTasks( void );
- * - * @return The number of tasks that the real time kernel is currently managing. - * This includes all ready, blocked and suspended tasks. A task that - * has been deleted but not yet freed by the idle task will also be - * included in the count. - * - * \page uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks - * \ingroup TaskUtils - */ -unsigned portBASE_TYPE uxTaskGetNumberOfTasks( void ); - -/** - * task. h - * 
void vTaskList( portCHAR *pcWriteBuffer );
- * - * configUSE_TRACE_FACILITY, INCLUDE_vTaskDelete and INCLUDE_vTaskSuspend - * must all be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * NOTE: This function will disable interrupts for its duration. It is - * not intended for normal application runtime use but as a debug aid. - * - * Lists all the current tasks, along with their current state and stack - * usage high water mark. - * - * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or - * suspended ('S'). - * - * @param pcWriteBuffer A buffer into which the above mentioned details - * will be written, in ascii form. This buffer is assumed to be large - * enough to contain the generated report. Approximately 40 bytes per - * task should be sufficient. - * - * \page vTaskList vTaskList - * \ingroup TaskUtils - */ -void vTaskList( signed portCHAR *pcWriteBuffer ); - -/** - * task. h - * 
void vTaskStartTrace( portCHAR * pcBuffer, unsigned portBASE_TYPE uxBufferSize );
- * - * Starts a real time kernel activity trace. The trace logs the identity of - * which task is running when. - * - * The trace file is stored in binary format. A separate DOS utility called - * convtrce.exe is used to convert this into a tab delimited text file which - * can be viewed and plotted in a spread sheet. - * - * @param pcBuffer The buffer into which the trace will be written. - * - * @param ulBufferSize The size of pcBuffer in bytes. The trace will continue - * until either the buffer in full, or ulTaskEndTrace () is called. - * - * \page vTaskStartTrace vTaskStartTrace - * \ingroup TaskUtils - */ -void vTaskStartTrace( signed portCHAR * pcBuffer, unsigned portLONG ulBufferSize ); - -/** - * task. h - * 
unsigned portLONG ulTaskEndTrace( void );
- * - * Stops a kernel activity trace. See vTaskStartTrace (). - * - * @return The number of bytes that have been written into the trace buffer. - * - * \page usTaskEndTrace usTaskEndTrace - * \ingroup TaskUtils - */ -unsigned portLONG ulTaskEndTrace( void ); - - -/*----------------------------------------------------------- - * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES - *----------------------------------------------------------*/ - -/* - * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY - * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS - * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. - * - * Called from the real time kernel tick (either preemptive or cooperative), - * this increments the tick count and checks if any tasks that are blocked - * for a finite period required removing from a blocked list and placing on - * a ready list. - */ -inline void vTaskIncrementTick( void ); - -/* - * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN - * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. - * - * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED. - * - * Removes the calling task from the ready list and places it both - * on the list of tasks waiting for a particular event, and the - * list of delayed tasks. The task will be removed from both lists - * and replaced on the ready list should either the event occur (and - * there be no higher priority tasks waiting on the same event) or - * the delay period expires. - * - * @param pxEventList The list containing tasks that are blocked waiting - * for the event to occur. - * - * @param xTicksToWait The maximum amount of time that the task should wait - * for the event to occur. This is specified in kernel ticks,the constant - * portTICK_RATE_MS can be used to convert kernel ticks into a real time - * period. - */ -void vTaskPlaceOnEventList( xList *pxEventList, portTickType xTicksToWait ); - -/* - * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN - * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. - * - * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED. - * - * Removes a task from both the specified event list and the list of blocked - * tasks, and places it on a ready queue. - * - * xTaskRemoveFromEventList () will be called if either an event occurs to - * unblock a task, or the block timeout period expires. - * - * @return pdTRUE if the task being removed has a higher priority than the task - * making the call, otherwise pdFALSE. - */ -signed portBASE_TYPE xTaskRemoveFromEventList( const xList *pxEventList ); - -/* - * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN - * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. - * - * INCLUDE_vTaskCleanUpResources and INCLUDE_vTaskSuspend must be defined as 1 - * for this function to be available. - * See the configuration section for more information. - * - * Empties the ready and delayed queues of task control blocks, freeing the - * memory allocated for the task control block and task stacks as it goes. - */ -void vTaskCleanUpResources( void ); - -/* - * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY - * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS - * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. - * - * Sets the pointer to the current TCB to the TCB of the highest priority task - * that is ready to run. - */ -inline void vTaskSwitchContext( void ); - -/* - * Return the handle of the calling task. - */ -xTaskHandle xTaskGetCurrentTaskHandle( void ); - -/* - * Capture the current time status for future reference. - */ -void vTaskSetTimeOutState( xTimeOutType *pxTimeOut ); - -/* - * Compare the time status now with that previously captured to see if the - * timeout has expired. - */ -portBASE_TYPE xTaskCheckForTimeOut( xTimeOutType *pxTimeOut, portTickType *pxTicksToWait ); - -/* - * Shortcut used by the queue implementation to prevent unnecessary call to - * taskYIELD(); - */ -void vTaskMissedYield( void ); - -#endif /* TASK_H */ - - - diff --git a/Source/list.c b/Source/list.c deleted file mode 100644 index d28adc989..000000000 --- a/Source/list.c +++ /dev/null @@ -1,201 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V1.2.0 - - + Removed the volatile modifier from the function parameters. This was - only ever included to prevent compiler warnings. Now warnings are - removed by casting parameters where the calls are made. - - + prvListGetOwnerOfNextEntry() and prvListGetOwnerOfHeadEntry() have been - removed from the c file and added as macros to the h file. - - + uxNumberOfItems has been added to the list structure. This removes the - need for a pointer comparison when checking if a list is empty, and so - is slightly faster. - - + Removed the NULL check in vListRemove(). This makes the call faster but - necessitates any application code utilising the list implementation to - ensure NULL pointers are not passed. - -Changes from V2.0.0 - - + Double linked the lists to allow faster removal item removal. - -Changes from V2.6.1 - - + Make use of the new portBASE_TYPE definition where ever appropriate. - -Changes from V3.0.0 - - + API changes as described on the FreeRTOS.org WEB site. - -Changes from V3.2.4 - - + Removed the pxHead member of the xList structure. This always pointed - to the same place so has been removed to free a few bytes of RAM. - - + Introduced the xMiniListItem structure that does not include the - xListItem members that are not required by the xListEnd member of a list. - Again this was done to reduce RAM usage. - - + Changed the volatile definitions of some structure members to clean up - the code where the list structures are used. - -Changes from V4.0.4 - - + Optimised vListInsert() in the case when the wake time is the maximum - tick count value. -*/ - -#include -#include "FreeRTOS.h" -#include "list.h" - -/*----------------------------------------------------------- - * PUBLIC LIST API documented in list.h - *----------------------------------------------------------*/ - -void vListInitialise( xList *pxList ) -{ - /* The list structure contains a list item which is used to mark the - end of the list. To initialise the list the list end is inserted - as the only list entry. */ - pxList->pxIndex = ( xListItem * ) &( pxList->xListEnd ); - - /* The list end value is the highest possible value in the list to - ensure it remains at the end of the list. */ - pxList->xListEnd.xItemValue = portMAX_DELAY; - - /* The list end next and previous pointers point to itself so we know - when the list is empty. */ - pxList->xListEnd.pxNext = ( xListItem * ) &( pxList->xListEnd ); - pxList->xListEnd.pxPrevious = ( xListItem * ) &( pxList->xListEnd ); - - pxList->uxNumberOfItems = 0; -} -/*-----------------------------------------------------------*/ - -void vListInitialiseItem( xListItem *pxItem ) -{ - /* Make sure the list item is not recorded as being on a list. */ - pxItem->pvContainer = NULL; -} -/*-----------------------------------------------------------*/ - -void vListInsertEnd( xList *pxList, xListItem *pxNewListItem ) -{ -volatile xListItem * pxIndex; - - /* Insert a new list item into pxList, but rather than sort the list, - makes the new list item the last item to be removed by a call to - pvListGetOwnerOfNextEntry. This means it has to be the item pointed to by - the pxIndex member. */ - pxIndex = pxList->pxIndex; - - pxNewListItem->pxNext = pxIndex->pxNext; - pxNewListItem->pxPrevious = pxList->pxIndex; - pxIndex->pxNext->pxPrevious = ( volatile xListItem * ) pxNewListItem; - pxIndex->pxNext = ( volatile xListItem * ) pxNewListItem; - pxList->pxIndex = ( volatile xListItem * ) pxNewListItem; - - /* Remember which list the item is in. */ - pxNewListItem->pvContainer = ( void * ) pxList; - - ( pxList->uxNumberOfItems )++; -} -/*-----------------------------------------------------------*/ - -void vListInsert( xList *pxList, xListItem *pxNewListItem ) -{ -volatile xListItem *pxIterator; -portTickType xValueOfInsertion; - - /* Insert the new list item into the list, sorted in ulListItem order. */ - xValueOfInsertion = pxNewListItem->xItemValue; - - /* If the list already contains a list item with the same item value then - the new list item should be placed after it. This ensures that TCB's which - are stored in ready lists (all of which have the same ulListItem value) - get an equal share of the CPU. However, if the xItemValue is the same as - the back marker the iteration loop below will not end. This means we need - to guard against this by checking the value first and modifying the - algorithm slightly if necessary. */ - if( xValueOfInsertion == portMAX_DELAY ) - { - pxIterator = pxList->xListEnd.pxPrevious; - } - else - { - for( pxIterator = ( xListItem * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) - { - /* There is nothing to do here, we are just iterating to the - wanted insertion position. */ - } - } - - pxNewListItem->pxNext = pxIterator->pxNext; - pxNewListItem->pxNext->pxPrevious = ( volatile xListItem * ) pxNewListItem; - pxNewListItem->pxPrevious = pxIterator; - pxIterator->pxNext = ( volatile xListItem * ) pxNewListItem; - - /* Remember which list the item is in. This allows fast removal of the - item later. */ - pxNewListItem->pvContainer = ( void * ) pxList; - - ( pxList->uxNumberOfItems )++; -} -/*-----------------------------------------------------------*/ - -void vListRemove( xListItem *pxItemToRemove ) -{ -xList * pxList; - - pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious; - pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext; - - /* The list item knows which list it is in. Obtain the list from the list - item. */ - pxList = ( xList * ) pxItemToRemove->pvContainer; - - /* Make sure the index is left pointing to a valid item. */ - if( pxList->pxIndex == pxItemToRemove ) - { - pxList->pxIndex = pxItemToRemove->pxPrevious; - } - - pxItemToRemove->pvContainer = NULL; - ( pxList->uxNumberOfItems )--; -} -/*-----------------------------------------------------------*/ - diff --git a/Source/portable/BCC/16BitDOS/Flsh186/port.c b/Source/portable/BCC/16BitDOS/Flsh186/port.c deleted file mode 100644 index 16cdce3b6..000000000 --- a/Source/portable/BCC/16BitDOS/Flsh186/port.c +++ /dev/null @@ -1,253 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V1.00: - - + Call to taskYIELD() from within tick ISR has been replaced by the more - efficient portSWITCH_CONTEXT(). - + ISR function definitions renamed to include the prv prefix. - -Changes from V2.6.1 - - + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION - macro to be consistent with the later ports. -*/ - -/*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the Flashlite 186 - * port. - *----------------------------------------------------------*/ - -#include -#include -#include - -#include "FreeRTOS.h" -#include "task.h" -#include "portasm.h" - -/*lint -e950 Non ANSI reserved words okay in this file only. */ - -#define portTIMER_EOI_TYPE ( 8 ) -#define portRESET_PIC() portOUTPUT_WORD( ( unsigned portSHORT ) 0xff22, portTIMER_EOI_TYPE ) -#define portTIMER_INT_NUMBER 0x12 - -#define portTIMER_1_CONTROL_REGISTER ( ( unsigned portSHORT ) 0xff5e ) -#define portTIMER_0_CONTROL_REGISTER ( ( unsigned portSHORT ) 0xff56 ) -#define portTIMER_INTERRUPT_ENABLE ( ( unsigned portSHORT ) 0x2000 ) - -/* Setup the hardware to generate the required tick frequency. */ -static void prvSetTickFrequency( unsigned portLONG ulTickRateHz ); - -/* Set the hardware back to the state as per before the scheduler started. */ -static void prvExitFunction( void ); - -/* The ISR used depends on whether the preemptive or cooperative scheduler -is being used. */ -#if( configUSE_PREEMPTION == 1 ) - /* Tick service routine used by the scheduler when preemptive scheduling is - being used. */ - static void __interrupt __far prvPreemptiveTick( void ); -#else - /* Tick service routine used by the scheduler when cooperative scheduling is - being used. */ - static void __interrupt __far prvNonPreemptiveTick( void ); -#endif - -/* Trap routine used by taskYIELD() to manually cause a context switch. */ -static void __interrupt __far prvYieldProcessor( void ); - -/*lint -e956 File scopes necessary here. */ - -/* Set true when the vectors are set so the scheduler will service the tick. */ -static portBASE_TYPE xSchedulerRunning = pdFALSE; - -/* Points to the original routine installed on the vector we use for manual -context switches. This is then used to restore the original routine during -prvExitFunction(). */ -static void ( __interrupt __far *pxOldSwitchISR )(); - -/* Used to restore the original DOS context when the scheduler is ended. */ -static jmp_buf xJumpBuf; - -/*lint +e956 */ - -/*-----------------------------------------------------------*/ -portBASE_TYPE xPortStartScheduler( void ) -{ - /* This is called with interrupts already disabled. */ - - /* Remember what was on the interrupts we are going to use - so we can put them back later if required. */ - pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER ); - - /* Put our manual switch (yield) function on a known - vector. */ - _dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor ); - - #if( configUSE_PREEMPTION == 1 ) - { - /* Put our tick switch function on the timer interrupt. */ - _dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick ); - } - #else - { - /* We want the timer interrupt to just increment the tick count. */ - _dos_setvect( portTIMER_INT_NUMBER, prvNonPreemptiveTick ); - } - #endif - - prvSetTickFrequency( configTICK_RATE_HZ ); - - /* Clean up function if we want to return to DOS. */ - if( setjmp( xJumpBuf ) != 0 ) - { - prvExitFunction(); - xSchedulerRunning = pdFALSE; - } - else - { - xSchedulerRunning = pdTRUE; - - /* Kick off the scheduler by setting up the context of the first task. */ - portFIRST_CONTEXT(); - } - - return xSchedulerRunning; -} -/*-----------------------------------------------------------*/ - -/* The ISR used depends on whether the preemptive or cooperative scheduler -is being used. */ -#if( configUSE_PREEMPTION == 1 ) - static void __interrupt __far prvPreemptiveTick( void ) - { - /* Get the scheduler to update the task states following the tick. */ - vTaskIncrementTick(); - - /* Switch in the context of the next task to be run. */ - portSWITCH_CONTEXT(); - - /* Reset the PIC ready for the next time. */ - portRESET_PIC(); - } -#else - static void __interrupt __far prvNonPreemptiveTick( void ) - { - /* Same as preemptive tick, but the cooperative scheduler is being used - so we don't have to switch in the context of the next task. */ - vTaskIncrementTick(); - portRESET_PIC(); - } -#endif -/*-----------------------------------------------------------*/ - -static void __interrupt __far prvYieldProcessor( void ) -{ - /* Switch in the context of the next task to be run. */ - portSWITCH_CONTEXT(); -} -/*-----------------------------------------------------------*/ - -void vPortEndScheduler( void ) -{ - /* Jump back to the processor state prior to starting the - scheduler. This means we are not going to be using a - task stack frame so the task can be deleted. */ - longjmp( xJumpBuf, 1 ); -} -/*-----------------------------------------------------------*/ - -static void prvExitFunction( void ) -{ -const unsigned portSHORT usTimerDisable = 0x0000; -unsigned portSHORT usTimer0Control; - - /* Interrupts should be disabled here anyway - but no - harm in making sure. */ - portDISABLE_INTERRUPTS(); - if( xSchedulerRunning == pdTRUE ) - { - /* Put back the switch interrupt routines that was in place - before the scheduler started. */ - _dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR ); - } - - /* Disable the timer used for the tick to ensure the scheduler is - not called before restoring interrupts. There was previously nothing - on this timer so there is no old ISR to restore. */ - portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerDisable ); - - /* Restart the DOS tick. */ - usTimer0Control = portINPUT_WORD( portTIMER_0_CONTROL_REGISTER ); - usTimer0Control |= portTIMER_INTERRUPT_ENABLE; - portOUTPUT_WORD( portTIMER_0_CONTROL_REGISTER, usTimer0Control ); - - - portENABLE_INTERRUPTS(); - - /* This will free up all the memory used by the scheduler. - exiting back to dos with INT21 AH=4CH will do this anyway so - it is not necessary to call this. */ - vTaskCleanUpResources(); -} -/*-----------------------------------------------------------*/ - -static void prvSetTickFrequency( unsigned portLONG ulTickRateHz ) -{ -const unsigned portSHORT usMaxCountRegister = 0xff5a; -const unsigned portSHORT usTimerPriorityRegister = 0xff32; -const unsigned portSHORT usTimerEnable = 0xC000; -const unsigned portSHORT usRetrigger = 0x0001; -const unsigned portSHORT usTimerHighPriority = 0x0000; -unsigned portSHORT usTimer0Control; - -/* ( CPU frequency / 4 ) / clock 2 max count [inpw( 0xff62 ) = 7] */ - -const unsigned portLONG ulClockFrequency = ( unsigned portLONG ) 0x7f31a0UL; - -unsigned portLONG ulTimerCount = ulClockFrequency / ulTickRateHz; - - portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerEnable | portTIMER_INTERRUPT_ENABLE | usRetrigger ); - portOUTPUT_WORD( usMaxCountRegister, ( unsigned portSHORT ) ulTimerCount ); - portOUTPUT_WORD( usTimerPriorityRegister, usTimerHighPriority ); - - /* Stop the DOS tick - don't do this if you want to maintain a TOD clock. */ - usTimer0Control = portINPUT_WORD( portTIMER_0_CONTROL_REGISTER ); - usTimer0Control &= ~portTIMER_INTERRUPT_ENABLE; - portOUTPUT_WORD( portTIMER_0_CONTROL_REGISTER, usTimer0Control ); -} - - -/*lint +e950 */ - diff --git a/Source/portable/BCC/16BitDOS/Flsh186/prtmacro.h b/Source/portable/BCC/16BitDOS/Flsh186/prtmacro.h deleted file mode 100644 index bf1b5ca89..000000000 --- a/Source/portable/BCC/16BitDOS/Flsh186/prtmacro.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -/*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the - * given hardware and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - -/* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE long -#define portLONG long -#define portSHORT int -#define portSTACK_TYPE unsigned portSHORT -#define portBASE_TYPE portSHORT - -#if( configUSE_16_BIT_TICKS == 1 ) - typedef unsigned portSHORT portTickType; - #define portMAX_DELAY ( portTickType ) 0xffff -#else - typedef unsigned portLONG portTickType; - #define portMAX_DELAY ( portTickType ) 0xffffffff -#endif -/*-----------------------------------------------------------*/ - -/* Critical section handling. */ -#define portENTER_CRITICAL() __asm{ pushf } \ - __asm{ cli } \ - -#define portEXIT_CRITICAL() __asm{ popf } - -#define portDISABLE_INTERRUPTS() __asm{ cli } - -#define portENABLE_INTERRUPTS() __asm{ sti } -/*-----------------------------------------------------------*/ - -/* Hardware specifics. */ -#define portNOP() __asm{ nop } -#define portSTACK_GROWTH ( -1 ) -#define portSWITCH_INT_NUMBER 0x80 -#define portYIELD() __asm{ int portSWITCH_INT_NUMBER } -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 2 -#define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */ -/*-----------------------------------------------------------*/ - -/* Compiler specifics. */ -#define portINPUT_BYTE( xAddr ) inp( xAddr ) -#define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue ) -#define portINPUT_WORD( xAddr ) inpw( xAddr ) -#define portOUTPUT_WORD( xAddr, usValue ) outpw( xAddr, usValue ) -#define inline -/*-----------------------------------------------------------*/ - -/* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters ) -#define portTASK_FUNCTION( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters ) - -#endif /* PORTMACRO_H */ - diff --git a/Source/portable/BCC/16BitDOS/PC/port.c b/Source/portable/BCC/16BitDOS/PC/port.c deleted file mode 100644 index d3f540b14..000000000 --- a/Source/portable/BCC/16BitDOS/PC/port.c +++ /dev/null @@ -1,297 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V2.6.1 - - + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION - macro to be consistent with the later ports. - -Changes from V4.0.1 - - + Add function prvSetTickFrequencyDefault() to set the DOS tick back to - its proper value when the scheduler exits. -*/ - -#include -#include -#include - -#include "FreeRTOS.h" -#include "task.h" -#include "portasm.h" - -/*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the industrial - * PC port. - *----------------------------------------------------------*/ - -/*lint -e950 Non ANSI reserved words okay in this file only. */ - -#define portTIMER_INT_NUMBER 0x08 - -/* Setup hardware for required tick interrupt rate. */ -static void prvSetTickFrequency( unsigned portLONG ulTickRateHz ); - -/* Restore hardware to as it was prior to starting the scheduler. */ -static void prvExitFunction( void ); - -/* Either chain to the DOS tick (which itself clears the PIC) or clear the PIC -directly. We chain to the DOS tick as close as possible to the standard DOS -tick rate. */ -static void prvPortResetPIC( void ); - -/* The ISR used depends on whether the preemptive or cooperative -scheduler is being used. */ -#if( configUSE_PREEMPTION == 1 ) - /* Tick service routine used by the scheduler when preemptive scheduling is - being used. */ - static void __interrupt __far prvPreemptiveTick( void ); -#else - /* Tick service routine used by the scheduler when cooperative scheduling is - being used. */ - static void __interrupt __far prvNonPreemptiveTick( void ); -#endif - -/* Trap routine used by taskYIELD() to manually cause a context switch. */ -static void __interrupt __far prvYieldProcessor( void ); - -/* Set the tick frequency back so the floppy drive works correctly when the -scheduler exits. */ -static void prvSetTickFrequencyDefault( void ); - -/*lint -e956 File scopes necessary here. */ - -/* Used to signal when to chain to the DOS tick, and when to just clear the PIC ourselves. */ -static portSHORT sDOSTickCounter; - -/* Set true when the vectors are set so the scheduler will service the tick. */ -static portBASE_TYPE xSchedulerRunning = pdFALSE; - -/* Points to the original routine installed on the vector we use for manual context switches. This is then used to restore the original routine during prvExitFunction(). */ -static void ( __interrupt __far *pxOldSwitchISR )(); - -/* Points to the original routine installed on the vector we use to chain to the DOS tick. This is then used to restore the original routine during prvExitFunction(). */ -static void ( __interrupt __far *pxOldSwitchISRPlus1 )(); - -/* Used to restore the original DOS context when the scheduler is ended. */ -static jmp_buf xJumpBuf; - -/*lint +e956 */ - -/*-----------------------------------------------------------*/ -portBASE_TYPE xPortStartScheduler( void ) -{ -pxISR pxOriginalTickISR; - - /* This is called with interrupts already disabled. */ - - /* Remember what was on the interrupts we are going to use - so we can put them back later if required. */ - pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER ); - pxOriginalTickISR = _dos_getvect( portTIMER_INT_NUMBER ); - pxOldSwitchISRPlus1 = _dos_getvect( portSWITCH_INT_NUMBER + 1 ); - - prvSetTickFrequency( configTICK_RATE_HZ ); - - /* Put our manual switch (yield) function on a known - vector. */ - _dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor ); - - /* Put the old tick on a different interrupt number so we can - call it when we want. */ - _dos_setvect( portSWITCH_INT_NUMBER + 1, pxOriginalTickISR ); - - /* The ISR used depends on whether the preemptive or cooperative - scheduler is being used. */ - #if( configUSE_PREEMPTION == 1 ) - { - /* Put our tick switch function on the timer interrupt. */ - _dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick ); - } - #else - { - /* We want the timer interrupt to just increment the tick count. */ - _dos_setvect( portTIMER_INT_NUMBER, prvNonPreemptiveTick ); - } - #endif - - /* Setup a counter that is used to call the DOS interrupt as close - to it's original frequency as can be achieved given our chosen tick - frequency. */ - sDOSTickCounter = portTICKS_PER_DOS_TICK; - - /* Clean up function if we want to return to DOS. */ - if( setjmp( xJumpBuf ) != 0 ) - { - prvExitFunction(); - xSchedulerRunning = pdFALSE; - } - else - { - xSchedulerRunning = pdTRUE; - - /* Kick off the scheduler by setting up the context of the first task. */ - portFIRST_CONTEXT(); - } - - return xSchedulerRunning; -} -/*-----------------------------------------------------------*/ - -/* The ISR used depends on whether the preemptive or cooperative -scheduler is being used. */ -#if( configUSE_PREEMPTION == 1 ) - static void __interrupt __far prvPreemptiveTick( void ) - { - /* Get the scheduler to update the task states following the tick. */ - vTaskIncrementTick(); - - /* Switch in the context of the next task to be run. */ - portSWITCH_CONTEXT(); - - /* Reset the PIC ready for the next time. */ - prvPortResetPIC(); - } -#else - static void __interrupt __far prvNonPreemptiveTick( void ) - { - /* Same as preemptive tick, but the cooperative scheduler is being used - so we don't have to switch in the context of the next task. */ - vTaskIncrementTick(); - prvPortResetPIC(); - } -#endif -/*-----------------------------------------------------------*/ - -static void __interrupt __far prvYieldProcessor( void ) -{ - /* Switch in the context of the next task to be run. */ - portSWITCH_CONTEXT(); -} -/*-----------------------------------------------------------*/ - -static void prvPortResetPIC( void ) -{ - /* We are going to call the DOS tick interrupt at as close a - frequency to the normal DOS tick as possible. */ - - /* WE SHOULD NOT DO THIS IF YIELD WAS CALLED. */ - --sDOSTickCounter; - if( sDOSTickCounter <= 0 ) - { - sDOSTickCounter = ( portSHORT ) portTICKS_PER_DOS_TICK; - __asm{ int portSWITCH_INT_NUMBER + 1 }; - } - else - { - /* Reset the PIC as the DOS tick is not being called to - do it. */ - __asm - { - mov al, 20H - out 20H, al - }; - } -} -/*-----------------------------------------------------------*/ - -void vPortEndScheduler( void ) -{ - /* Jump back to the processor state prior to starting the - scheduler. This means we are not going to be using a - task stack frame so the task can be deleted. */ - longjmp( xJumpBuf, 1 ); -} -/*-----------------------------------------------------------*/ - -static void prvExitFunction( void ) -{ -void ( __interrupt __far *pxOriginalTickISR )(); - - /* Interrupts should be disabled here anyway - but no - harm in making sure. */ - portDISABLE_INTERRUPTS(); - if( xSchedulerRunning == pdTRUE ) - { - /* Set the DOS tick back onto the timer ticker. */ - pxOriginalTickISR = _dos_getvect( portSWITCH_INT_NUMBER + 1 ); - _dos_setvect( portTIMER_INT_NUMBER, pxOriginalTickISR ); - prvSetTickFrequencyDefault(); - - /* Put back the switch interrupt routines that was in place - before the scheduler started. */ - _dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR ); - _dos_setvect( portSWITCH_INT_NUMBER + 1, pxOldSwitchISRPlus1 ); - } - /* The tick timer is back how DOS wants it. We can re-enable - interrupts without the scheduler being called. */ - portENABLE_INTERRUPTS(); - - /* This will free up all the memory used by the scheduler. - exiting back to dos with INT21 AH=4CH will do this anyway so - it is not necessary to call this. */ - vTaskCleanUpResources(); -} -/*-----------------------------------------------------------*/ - -static void prvSetTickFrequency( unsigned portLONG ulTickRateHz ) -{ -const unsigned portSHORT usPIT_MODE = ( unsigned portSHORT ) 0x43; -const unsigned portSHORT usPIT0 = ( unsigned portSHORT ) 0x40; -const unsigned portLONG ulPIT_CONST = ( unsigned portLONG ) 1193180UL; -const unsigned portSHORT us8254_CTR0_MODE3 = ( unsigned portSHORT ) 0x36; -unsigned portLONG ulOutput; - - /* Setup the 8245 to tick at the wanted frequency. */ - portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 ); - ulOutput = ulPIT_CONST / ulTickRateHz; - portOUTPUT_BYTE( usPIT0, ( unsigned portSHORT )( ulOutput & ( unsigned portLONG ) 0xff ) ); - ulOutput >>= 8; - portOUTPUT_BYTE( usPIT0, ( unsigned portSHORT ) ( ulOutput & ( unsigned portLONG ) 0xff ) ); -} -/*-----------------------------------------------------------*/ - -static void prvSetTickFrequencyDefault( void ) -{ -const unsigned portSHORT usPIT_MODE = ( unsigned portSHORT ) 0x43; -const unsigned portSHORT usPIT0 = ( unsigned portSHORT ) 0x40; -const unsigned portSHORT us8254_CTR0_MODE3 = ( unsigned portSHORT ) 0x36; - - portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 ); - portOUTPUT_BYTE( usPIT0,0 ); - portOUTPUT_BYTE( usPIT0,0 ); -} - - -/*lint +e950 */ - diff --git a/Source/portable/BCC/16BitDOS/PC/prtmacro.h b/Source/portable/BCC/16BitDOS/PC/prtmacro.h deleted file mode 100644 index 6355cc5a7..000000000 --- a/Source/portable/BCC/16BitDOS/PC/prtmacro.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -/*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the - * given hardware and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - -/* Type definitions. */ -#define portCHAR char -#define portFLOAT long -#define portDOUBLE long -#define portLONG long -#define portSHORT int -#define portSTACK_TYPE unsigned portSHORT -#define portBASE_TYPE portSHORT - -#if( configUSE_16_BIT_TICKS == 1 ) - typedef unsigned portSHORT portTickType; - #define portMAX_DELAY ( portTickType ) 0xffff -#else - typedef unsigned portLONG portTickType; - #define portMAX_DELAY ( portTickType ) 0xffffffff -#endif -/*-----------------------------------------------------------*/ - -/* Critical section management. */ -#define portENTER_CRITICAL() __asm{ pushf } \ - __asm{ cli } \ - -#define portEXIT_CRITICAL() __asm{ popf } - -#define portDISABLE_INTERRUPTS() __asm{ cli } - -#define portENABLE_INTERRUPTS() __asm{ sti } -/*-----------------------------------------------------------*/ - -/* Hardware specifics. */ -#define portNOP() __asm{ nop } -#define portSTACK_GROWTH ( -1 ) -#define portSWITCH_INT_NUMBER 0x80 -#define portYIELD() __asm{ int portSWITCH_INT_NUMBER } -#define portDOS_TICK_RATE ( 18.20648 ) -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) -#define portTICKS_PER_DOS_TICK ( ( unsigned portSHORT ) ( ( ( portDOUBLE ) configTICK_RATE_HZ / portDOS_TICK_RATE ) + 0.5 ) ) -#define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */ -/*-----------------------------------------------------------*/ - -/* Compiler specifics. */ -#define portINPUT_BYTE( xAddr ) inp( xAddr ) -#define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue ) -#define inline -/*-----------------------------------------------------------*/ - -/* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters ) -#define portTASK_FUNCTION( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters ) - -#endif /* PORTMACRO_H */ - diff --git a/Source/portable/BCC/16BitDOS/common/portasm.h b/Source/portable/BCC/16BitDOS/common/portasm.h deleted file mode 100644 index f4e389977..000000000 --- a/Source/portable/BCC/16BitDOS/common/portasm.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef PORT_ASM_H -#define PORT_ASM_H - -typedef void tskTCB; -extern volatile tskTCB * volatile pxCurrentTCB; -extern void vTaskSwitchContext( void ); - -/* - * Saves the stack pointer for one task into its TCB, calls - * vTaskSwitchContext() to update the TCB being used, then restores the stack - * from the new TCB read to run the task. - */ -void portSWITCH_CONTEXT( void ); - -/* - * Load the stack pointer from the TCB of the task which is going to be first - * to execute. Then force an IRET so the registers and IP are popped off the - * stack. - */ -void portFIRST_CONTEXT( void ); - -/* There are slightly different versions depending on whether you are building -to include debugger information. If debugger information is used then there -are a couple of extra bytes left of the ISR stack (presumably for use by the -debugger). The true stack pointer is then stored in the bp register. We add -2 to the stack pointer to remove the extra bytes before we restore our context. */ - -#define portSWITCH_CONTEXT() \ - asm { mov ax, seg pxCurrentTCB } \ - asm { mov ds, ax } \ - asm { les bx, pxCurrentTCB } /* Save the stack pointer into the TCB. */ \ - asm { mov es:0x2[ bx ], ss } \ - asm { mov es:[ bx ], sp } \ - asm { call far ptr vTaskSwitchContext } /* Perform the switch. */ \ - asm { mov ax, seg pxCurrentTCB } /* Restore the stack pointer from the TCB. */ \ - asm { mov ds, ax } \ - asm { les bx, dword ptr pxCurrentTCB } \ - asm { mov ss, es:[ bx + 2 ] } \ - asm { mov sp, es:[ bx ] } - -#define portFIRST_CONTEXT() \ - __asm { mov ax, seg pxCurrentTCB } \ - __asm { mov ds, ax } \ - __asm { les bx, dword ptr pxCurrentTCB } \ - __asm { mov ss, es:[ bx + 2 ] } \ - __asm { mov sp, es:[ bx ] } \ - __asm { pop bp } \ - __asm { pop di } \ - __asm { pop si } \ - __asm { pop ds } \ - __asm { pop es } \ - __asm { pop dx } \ - __asm { pop cx } \ - __asm { pop bx } \ - __asm { pop ax } \ - __asm { iret } - - -#endif - diff --git a/Source/portable/BCC/16BitDOS/common/portcomn.c b/Source/portable/BCC/16BitDOS/common/portcomn.c deleted file mode 100644 index 294b8816c..000000000 --- a/Source/portable/BCC/16BitDOS/common/portcomn.c +++ /dev/null @@ -1,125 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V1.00: - - + pxPortInitialiseStack() now initialises the stack of new tasks to the - same format used by the compiler. This allows the compiler generated - interrupt mechanism to be used for context switches. - -Changes from V2.6.1 - - + Move usPortCheckFreeStackSpace() to tasks.c. -*/ - - -#include -#include -#include "FreeRTOS.h" - -/*-----------------------------------------------------------*/ - -/* See header file for description. */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) -{ -portSTACK_TYPE DS_Reg = 0; - - /* Place a few bytes of known values on the bottom of the stack. - This is just useful for debugging. */ - - *pxTopOfStack = 0x1111; - pxTopOfStack--; - *pxTopOfStack = 0x2222; - pxTopOfStack--; - *pxTopOfStack = 0x3333; - pxTopOfStack--; - *pxTopOfStack = 0x4444; - pxTopOfStack--; - *pxTopOfStack = 0x5555; - pxTopOfStack--; - - - /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */ - - /* We are going to start the scheduler using a return from interrupt - instruction to load the program counter, so first there would be the - function call with parameters preamble. */ - - *pxTopOfStack = FP_SEG( pvParameters ); - pxTopOfStack--; - *pxTopOfStack = FP_OFF( pvParameters ); - pxTopOfStack--; - *pxTopOfStack = FP_SEG( pxCode ); - pxTopOfStack--; - *pxTopOfStack = FP_OFF( pxCode ); - pxTopOfStack--; - - /* Next the status register and interrupt return address. */ - *pxTopOfStack = portINITIAL_SW; - pxTopOfStack--; - *pxTopOfStack = FP_SEG( pxCode ); - pxTopOfStack--; - *pxTopOfStack = FP_OFF( pxCode ); - pxTopOfStack--; - - /* The remaining registers would be pushed on the stack by our context - switch function. These are loaded with values simply to make debugging - easier. */ - *pxTopOfStack = ( portSTACK_TYPE ) 0xAAAA; /* AX */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xBBBB; /* BX */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xCCCC; /* CX */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xDDDD; /* DX */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xEEEE; /* ES */ - pxTopOfStack--; - - /* We need the true data segment. */ - __asm{ MOV DS_Reg, DS }; - - *pxTopOfStack = DS_Reg; /* DS */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x0123; /* SI */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xDDDD; /* DI */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xBBBB; /* BP */ - - /*lint +e950 +e611 +e923 */ - - return pxTopOfStack; -} -/*-----------------------------------------------------------*/ - diff --git a/Source/portable/CodeWarrior/HCS12/port.c b/Source/portable/CodeWarrior/HCS12/port.c deleted file mode 100644 index f4992dd9f..000000000 --- a/Source/portable/CodeWarrior/HCS12/port.c +++ /dev/null @@ -1,243 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - - -/*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the HCS12 port. - *----------------------------------------------------------*/ - - -/* - * Configure a timer to generate the RTOS tick at the frequency specified - * within FreeRTOSConfig.h. - */ -static void prvSetupTimerInterrupt( void ); - -/* Interrupt service routines have to be in non-banked memory - as does the -scheduler startup function. */ -#pragma CODE_SEG __NEAR_SEG NON_BANKED - - /* Manual context switch function. This is the SWI ISR. */ - void interrupt vPortYield( void ); - - /* Tick context switch function. This is the timer ISR. */ - void interrupt vPortTickInterrupt( void ); - - /* Simply called by xPortStartScheduler(). xPortStartScheduler() does not - start the scheduler directly because the header file containing the - xPortStartScheduler() prototype is part of the common kernel code, and - therefore cannot use the CODE_SEG pragma. */ - static portBASE_TYPE xBankedStartScheduler( void ); - -#pragma CODE_SEG DEFAULT - -/* Calls to portENTER_CRITICAL() can be nested. When they are nested the -critical section should not be left (i.e. interrupts should not be re-enabled) -until the nesting depth reaches 0. This variable simply tracks the nesting -depth. Each task maintains it's own critical nesting depth variable so -uxCriticalNesting is saved and restored from the task stack during a context -switch. */ -volatile unsigned portBASE_TYPE uxCriticalNesting = 0xff; - -/*-----------------------------------------------------------*/ - -/* - * See header file for description. - */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) -{ - /* - Place a few bytes of known values on the bottom of the stack. - This can be uncommented to provide useful stack markers when debugging. - - *pxTopOfStack = ( portSTACK_TYPE ) 0x11; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x22; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x33; - pxTopOfStack--; - */ - - - - /* Setup the initial stack of the task. The stack is set exactly as - expected by the portRESTORE_CONTEXT() macro. In this case the stack as - expected by the HCS12 RTI instruction. */ - - - /* The address of the task function is placed in the stack byte at a time. */ - *pxTopOfStack = ( portSTACK_TYPE ) *( ((portSTACK_TYPE *) (&pxCode) ) + 1 ); - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) *( ((portSTACK_TYPE *) (&pxCode) ) + 0 ); - pxTopOfStack--; - - /* Next are all the registers that form part of the task context. */ - - /* Y register */ - *pxTopOfStack = ( portSTACK_TYPE ) 0xff; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xee; - pxTopOfStack--; - - /* X register */ - *pxTopOfStack = ( portSTACK_TYPE ) 0xdd; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xcc; - pxTopOfStack--; - - /* A register contains parameter high byte. */ - *pxTopOfStack = ( portSTACK_TYPE ) *( ((portSTACK_TYPE *) (&pvParameters) ) + 0 ); - pxTopOfStack--; - - /* B register contains parameter low byte. */ - *pxTopOfStack = ( portSTACK_TYPE ) *( ((portSTACK_TYPE *) (&pvParameters) ) + 1 ); - pxTopOfStack--; - - /* CCR: Note that when the task starts interrupts will be enabled since - "I" bit of CCR is cleared */ - *pxTopOfStack = ( portSTACK_TYPE ) 0x00; - pxTopOfStack--; - - #ifdef BANKED_MODEL - /* The page of the task. */ - *pxTopOfStack = ( portSTACK_TYPE ) ( ( int ) pxCode ); - pxTopOfStack--; - #endif - - /* Finally the critical nesting depth is initialised with 0 (not within - a critical section). */ - *pxTopOfStack = ( portSTACK_TYPE ) 0x00; - - return pxTopOfStack; -} -/*-----------------------------------------------------------*/ - -void vPortEndScheduler( void ) -{ - /* It is unlikely that the HCS12 port will get stopped. */ -} -/*-----------------------------------------------------------*/ - -static void prvSetupTimerInterrupt( void ) -{ - TickTimer_SetFreqHz( configTICK_RATE_HZ ); - TickTimer_Enable(); -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xPortStartScheduler( void ) -{ - /* xPortStartScheduler() does not start the scheduler directly because - the header file containing the xPortStartScheduler() prototype is part - of the common kernel code, and therefore cannot use the CODE_SEG pragma. - Instead it simply calls the locally defined xBankedStartScheduler() - - which does use the CODE_SEG pragma. */ - - return xBankedStartScheduler(); -} -/*-----------------------------------------------------------*/ - -#pragma CODE_SEG __NEAR_SEG NON_BANKED - -static portBASE_TYPE xBankedStartScheduler( void ) -{ - /* Configure the timer that will generate the RTOS tick. Interrupts are - disabled when this function is called. */ - prvSetupTimerInterrupt(); - - /* Restore the context of the first task. */ - portRESTORE_CONTEXT(); - - /* Simulate the end of an interrupt to start the scheduler off. */ - __asm( "rti" ); - - /* Should not get here! */ - return pdFALSE; -} -/*-----------------------------------------------------------*/ - -/* - * Context switch functions. These are both interrupt service routines. - */ - -/* - * Manual context switch forced by calling portYIELD(). This is the SWI - * handler. - */ -void interrupt vPortYield( void ) -{ - portSAVE_CONTEXT(); - vTaskSwitchContext(); - portRESTORE_CONTEXT(); -} -/*-----------------------------------------------------------*/ - -/* - * RTOS tick interrupt service routine. If the cooperative scheduler is - * being used then this simply increments the tick count. If the - * preemptive scheduler is being used a context switch can occur. - */ -void interrupt vPortTickInterrupt( void ) -{ - #if configUSE_PREEMPTION == 1 - { - /* A context switch might happen so save the context. */ - portSAVE_CONTEXT(); - - /* Increment the tick ... */ - vTaskIncrementTick(); - - /* ... then see if the new tick value has necessitated a - context switch. */ - vTaskSwitchContext(); - - TFLG1 = 1; - - /* Restore the context of a task - which may be a different task - to that interrupted. */ - portRESTORE_CONTEXT(); - } - #else - { - vTaskIncrementTick(); - TFLG1 = 1; - } - #endif -} - -#pragma CODE_SEG DEFAULT - - diff --git a/Source/portable/CodeWarrior/HCS12/portmacro.h b/Source/portable/CodeWarrior/HCS12/portmacro.h deleted file mode 100644 index 34ac8272e..000000000 --- a/Source/portable/CodeWarrior/HCS12/portmacro.h +++ /dev/null @@ -1,205 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -/*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the - * given hardware and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - -/* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE unsigned portCHAR -#define portBASE_TYPE char - -#if( configUSE_16_BIT_TICKS == 1 ) - typedef unsigned portSHORT portTickType; - #define portMAX_DELAY ( portTickType ) 0xffff -#else - typedef unsigned portLONG portTickType; - #define portMAX_DELAY ( portTickType ) 0xffffffff -#endif -/*-----------------------------------------------------------*/ - -/* Hardware specifics. */ -#define portBYTE_ALIGNMENT 1 -#define portSTACK_GROWTH ( -1 ) -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) -#define portYIELD() __asm( "swi" ); -#define portNOP() __asm( "nop" ); -/*-----------------------------------------------------------*/ - -/* Critical section handling. */ -#define portENABLE_INTERRUPTS() __asm( "cli" ) -#define portDISABLE_INTERRUPTS() __asm( "sei" ) - -/* - * Disable interrupts before incrementing the count of critical section nesting. - * The nesting count is maintained so we know when interrupts should be - * re-enabled. Once interrupts are disabled the nesting count can be accessed - * directly. Each task maintains its own nesting count. - */ -#define portENTER_CRITICAL() \ -{ \ - extern volatile unsigned portBASE_TYPE uxCriticalNesting; \ - \ - portDISABLE_INTERRUPTS(); \ - uxCriticalNesting++; \ -} - -/* - * Interrupts are disabled so we can access the nesting count directly. If the - * nesting is found to be 0 (no nesting) then we are leaving the critical - * section and interrupts can be re-enabled. - */ -#define portEXIT_CRITICAL() \ -{ \ - extern volatile unsigned portBASE_TYPE uxCriticalNesting; \ - \ - uxCriticalNesting--; \ - if( uxCriticalNesting == 0 ) \ - { \ - portENABLE_INTERRUPTS(); \ - } \ -} -/*-----------------------------------------------------------*/ - -/* Task utilities. */ - -/* - * These macros are very simple as the processor automatically saves and - * restores its registers as interrupts are entered and exited. In - * addition to the (automatically stacked) registers we also stack the - * critical nesting count. Each task maintains its own critical nesting - * count as it is legitimate for a task to yield from within a critical - * section. If the banked memory model is being used then the PPAGE - * register is also stored as part of the tasks context. - */ - -#ifdef BANKED_MODEL - /* - * Load the stack pointer for the task, then pull the critical nesting - * count and PPAGE register from the stack. The remains of the - * context are restored by the RTI instruction. - */ - #define portRESTORE_CONTEXT() \ - { \ - extern volatile void * pxCurrentTCB; \ - extern volatile unsigned portBASE_TYPE uxCriticalNesting; \ - \ - __asm( "ldx pxCurrentTCB" ); \ - __asm( "lds 0, x" ); \ - __asm( "pula" ); \ - __asm( "staa uxCriticalNesting" ); \ - __asm( "pula" ); \ - __asm( "staa 0x30" ); /* 0x30 = PPAGE */ \ - } - - /* - * By the time this macro is called the processor has already stacked the - * registers. Simply stack the nesting count and PPAGE value, then save - * the task stack pointer. - */ - #define portSAVE_CONTEXT() \ - { \ - extern volatile void * pxCurrentTCB; \ - extern volatile unsigned portBASE_TYPE uxCriticalNesting; \ - \ - __asm( "ldaa 0x30" ); /* 0x30 = PPAGE */ \ - __asm( "psha" ); \ - __asm( "ldaa uxCriticalNesting" ); \ - __asm( "psha" ); \ - __asm( "ldx pxCurrentTCB" ); \ - __asm( "sts 0, x" ); \ - } -#else - - /* - * These macros are as per the BANKED versions above, but without saving - * and restoring the PPAGE register. - */ - - #define portRESTORE_CONTEXT() \ - { \ - extern volatile void * pxCurrentTCB; \ - extern volatile unsigned portBASE_TYPE uxCriticalNesting; \ - \ - __asm( "ldx pxCurrentTCB" ); \ - __asm( "lds 0, x" ); \ - __asm( "pula" ); \ - __asm( "staa uxCriticalNesting" ); \ - } - - #define portSAVE_CONTEXT() \ - { \ - extern volatile void * pxCurrentTCB; \ - extern volatile unsigned portBASE_TYPE uxCriticalNesting; \ - \ - __asm( "ldaa uxCriticalNesting" ); \ - __asm( "psha" ); \ - __asm( "ldx pxCurrentTCB" ); \ - __asm( "sts 0, x" ); \ - } -#endif - -/* - * Utility macro to call macros above in correct order in order to perform a - * task switch from within a standard ISR. This macro can only be used if - * the ISR does not use any local (stack) variables. If the ISR uses stack - * variables portYIELD() should be used in it's place. - */ -#define portTASK_SWITCH_FROM_ISR() \ - portSAVE_CONTEXT(); \ - vTaskSwitchContext(); \ - portRESTORE_CONTEXT(); - - -/* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) - -#define inline - -#endif /* PORTMACRO_H */ - diff --git a/Source/portable/GCC/ARM7_AT91FR40008/port.c b/Source/portable/GCC/ARM7_AT91FR40008/port.c deleted file mode 100644 index afbad22e1..000000000 --- a/Source/portable/GCC/ARM7_AT91FR40008/port.c +++ /dev/null @@ -1,239 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the Atmel AT91R40008 - * port. - * - * Components that can be compiled to either ARM or THUMB mode are - * contained in this file. The ISR routines, which can only be compiled - * to ARM mode are contained in portISR.c. - *----------------------------------------------------------*/ - -/* Standard includes. */ -#include - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Hardware specific definitions. */ -#include "AT91R40008.h" -#include "pio.h" -#include "aic.h" -#include "tc.h" - -/* Constants required to setup the task context. */ -#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ -#define portTHUMB_MODE_BIT ( ( portSTACK_TYPE ) 0x20 ) -#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 ) -#define portNO_CRITICAL_SECTION_NESTING ( ( portSTACK_TYPE ) 0 ) -#define portTICK_PRIORITY_6 ( 6 ) -/*-----------------------------------------------------------*/ - -/* Setup the timer to generate the tick interrupts. */ -static void prvSetupTimerInterrupt( void ); - -/* - * The scheduler can only be started from ARM mode, so - * vPortISRStartFirstSTask() is defined in portISR.c. - */ -extern void vPortISRStartFirstTask( void ); - -/*-----------------------------------------------------------*/ - -/* - * Initialise the stack of a task to look exactly as if a call to - * portSAVE_CONTEXT had been called. - * - * See header file for description. - */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) -{ -portSTACK_TYPE *pxOriginalTOS; - - pxOriginalTOS = pxTopOfStack; - - /* Setup the initial stack of the task. The stack is set exactly as - expected by the portRESTORE_CONTEXT() macro. */ - - /* First on the stack is the return address - which in this case is the - start of the task. The offset is added to make the return address appear - as it would within an IRQ ISR. */ - *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; - pxTopOfStack--; - - *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */ - pxTopOfStack--; - - /* When the task starts is will expect to find the function parameter in - R0. */ - *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ - pxTopOfStack--; - - /* The last thing onto the stack is the status register, which is set for - system mode, with interrupts enabled. */ - *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR; - - #ifdef THUMB_INTERWORK - { - /* We want the task to start in thumb mode. */ - *pxTopOfStack |= portTHUMB_MODE_BIT; - } - #endif - - pxTopOfStack--; - - /* Some optimisation levels use the stack differently to others. This - means the interrupt flags cannot always be stored on the stack and will - instead be stored in a variable, which is then saved as part of the - tasks context. */ - *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING; - - return pxTopOfStack; -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xPortStartScheduler( void ) -{ - /* Start the timer that generates the tick ISR. Interrupts are disabled - here already. */ - prvSetupTimerInterrupt(); - - /* Start the first task. */ - vPortISRStartFirstTask(); - - /* Should not get here! */ - return 0; -} -/*-----------------------------------------------------------*/ - -void vPortEndScheduler( void ) -{ - /* It is unlikely that the ARM port will require this function as there - is nothing to return to. */ -} -/*-----------------------------------------------------------*/ - -/* - * Setup the tick timer to generate the tick interrupts at the required frequency. - */ -static void prvSetupTimerInterrupt( void ) -{ -volatile unsigned portLONG ulDummy; - - /* Enable clock to the tick timer... */ - AT91C_BASE_PS->PS_PCER = portTIMER_CLK_ENABLE_BIT; - - /* Stop the tick timer... */ - portTIMER_REG_BASE_PTR->TC_CCR = TC_CLKDIS; - - /* Start with tick timer interrupts disabled... */ - portTIMER_REG_BASE_PTR->TC_IDR = 0xFFFFFFFF; - - /* Clear any pending tick timer interrupts... */ - ulDummy = portTIMER_REG_BASE_PTR->TC_SR; - - /* Store interrupt handler function address in tick timer vector register... - The ISR installed depends on whether the preemptive or cooperative - scheduler is being used. */ - #if configUSE_PREEMPTION == 1 - { - extern void ( vPreemptiveTick )( void ); - AT91C_BASE_AIC->AIC_SVR[portTIMER_AIC_CHANNEL] = ( unsigned portLONG ) vPreemptiveTick; - } - #else // else use cooperative scheduler - { - extern void ( vNonPreemptiveTick )( void ); - AT91C_BASE_AIC->AIC_SVR[portTIMER_AIC_CHANNEL] = ( unsigned portLONG ) vNonPreemptiveTick; - } - #endif - - /* Tick timer interrupt level-sensitive, priority 6... */ - AT91C_BASE_AIC->AIC_SMR[ portTIMER_AIC_CHANNEL ] = AIC_SRCTYPE_INT_LEVEL_SENSITIVE | portTICK_PRIORITY_6; - - /* Enable the tick timer interrupt... - - First at timer level */ - portTIMER_REG_BASE_PTR->TC_IER = TC_CPCS; - - /* Then at the AIC level. */ - AT91C_BASE_AIC->AIC_IECR = (1 << portTIMER_AIC_CHANNEL); - - /* Calculate timer compare value to achieve the desired tick rate... */ - if( (configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 2) ) <= 0xFFFF ) - { - /* The tick rate is fast enough for us to use the faster timer input - clock (main clock / 2). */ - portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK2 | TC_BURST_NONE | TC_CPCTRG; - portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 2); - } - else - { - /* We must use a slower timer input clock (main clock / 8) because the - tick rate is too slow for the faster input clock. */ - portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK8 | TC_BURST_NONE | TC_CPCTRG; - portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 8); - } - - /* Start tick timer... */ - portTIMER_REG_BASE_PTR->TC_CCR = TC_SWTRG | TC_CLKEN; -} -/*-----------------------------------------------------------*/ - diff --git a/Source/portable/GCC/ARM7_AT91FR40008/portISR.c b/Source/portable/GCC/ARM7_AT91FR40008/portISR.c deleted file mode 100644 index 23941cb17..000000000 --- a/Source/portable/GCC/ARM7_AT91FR40008/portISR.c +++ /dev/null @@ -1,236 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/*----------------------------------------------------------- - * Components that can be compiled to either ARM or THUMB mode are - * contained in port.c The ISR routines, which can only be compiled - * to ARM mode, are contained in this file. - *----------------------------------------------------------*/ - -/* - Changes from V3.2.4 - - + The assembler statements are now included in a single asm block rather - than each line having its own asm block. -*/ - - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Constants required to handle interrupts. */ -#define portCLEAR_AIC_INTERRUPT ( ( unsigned portLONG ) 0 ) - -/* Constants required to handle critical sections. */ -#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 ) -volatile unsigned portLONG ulCriticalNesting = 9999UL; - -/*-----------------------------------------------------------*/ - -/* ISR to handle manual context switches (from a call to taskYIELD()). */ -void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked)); - -/* - * The scheduler can only be started from ARM mode, hence the inclusion of this - * function here. - */ -void vPortISRStartFirstTask( void ); -/*-----------------------------------------------------------*/ - -void vPortISRStartFirstTask( void ) -{ - /* Simply start the scheduler. This is included here as it can only be - called from ARM mode. */ - portRESTORE_CONTEXT(); -} -/*-----------------------------------------------------------*/ - -/* - * Called by portYIELD() or taskYIELD() to manually force a context switch. - * - * When a context switch is performed from the task level the saved task - * context is made to look as if it occurred from within the tick ISR. This - * way the same restore context function can be used when restoring the context - * saved from the ISR or that saved from a call to vPortYieldProcessor. - */ -void vPortYieldProcessor( void ) -{ - /* Within an IRQ ISR the link register has an offset from the true return - address, but an SWI ISR does not. Add the offset manually so the same - ISR return code can be used in both cases. */ - asm volatile ( "ADD LR, LR, #4" ); - - /* Perform the context switch. First save the context of the current task. */ - portSAVE_CONTEXT(); - - /* Find the highest priority task that is ready to run. */ - vTaskSwitchContext(); - - /* Restore the context of the new task. */ - portRESTORE_CONTEXT(); -} -/*-----------------------------------------------------------*/ - -/* - * The ISR used for the scheduler tick depends on whether the cooperative or - * the preemptive scheduler is being used. - */ - -#if configUSE_PREEMPTION == 0 - - /* The cooperative scheduler requires a normal IRQ service routine to - simply increment the system tick. */ - void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ"))); - void vNonPreemptiveTick( void ) - { - static volatile unsigned portLONG ulDummy; - - /* Clear tick timer interrupt indication. */ - ulDummy = portTIMER_REG_BASE_PTR->TC_SR; - - vTaskIncrementTick(); - - /* Acknowledge the interrupt at AIC level... */ - AT91C_BASE_AIC->AIC_EOICR = portCLEAR_AIC_INTERRUPT; - } - -#else /* else preemption is turned on */ - - /* The preemptive scheduler is defined as "naked" as the full context is - saved on entry as part of the context switch. */ - void vPreemptiveTick( void ) __attribute__((naked)); - void vPreemptiveTick( void ) - { - /* Save the context of the interrupted task. */ - portSAVE_CONTEXT(); - - /* WARNING - Do not use local (stack) variables here. Use globals - if you must! */ - static volatile unsigned portLONG ulDummy; - - /* Clear tick timer interrupt indication. */ - ulDummy = portTIMER_REG_BASE_PTR->TC_SR; - - /* Increment the RTOS tick count, then look for the highest priority - task that is ready to run. */ - vTaskIncrementTick(); - vTaskSwitchContext(); - - /* Acknowledge the interrupt at AIC level... */ - AT91C_BASE_AIC->AIC_EOICR = portCLEAR_AIC_INTERRUPT; - - /* Restore the context of the new task. */ - portRESTORE_CONTEXT(); - } - -#endif -/*-----------------------------------------------------------*/ - -/* - * The interrupt management utilities can only be called from ARM mode. When - * THUMB_INTERWORK is defined the utilities are defined as functions here to - * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then - * the utilities are defined as macros in portmacro.h - as per other ports. - */ -#ifdef THUMB_INTERWORK - - void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); - void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); - - void vPortDisableInterruptsFromThumb( void ) - { - asm volatile ( - "STMDB SP!, {R0} \n\t" /* Push R0. */ - "MRS R0, CPSR \n\t" /* Get CPSR. */ - "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ - "LDMIA SP!, {R0} \n\t" /* Pop R0. */ - "BX R14" ); /* Return back to thumb. */ - } - - void vPortEnableInterruptsFromThumb( void ) - { - asm volatile ( - "STMDB SP!, {R0} \n\t" /* Push R0. */ - "MRS R0, CPSR \n\t" /* Get CPSR. */ - "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ - "LDMIA SP!, {R0} \n\t" /* Pop R0. */ - "BX R14" ); /* Return back to thumb. */ - } - -#endif /* THUMB_INTERWORK */ - -/* The code generated by the GCC compiler uses the stack in different ways at -different optimisation levels. The interrupt flags can therefore not always -be saved to the stack. Instead the critical section nesting level is stored -in a variable, which is then saved as part of the stack context. */ -void vPortEnterCritical( void ) -{ - /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ - asm volatile ( - "STMDB SP!, {R0} \n\t" /* Push R0. */ - "MRS R0, CPSR \n\t" /* Get CPSR. */ - "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ - "LDMIA SP!, {R0}" ); /* Pop R0. */ - - /* Now interrupts are disabled ulCriticalNesting can be accessed - directly. Increment ulCriticalNesting to keep a count of how many times - portENTER_CRITICAL() has been called. */ - ulCriticalNesting++; -} - -void vPortExitCritical( void ) -{ - if( ulCriticalNesting > portNO_CRITICAL_NESTING ) - { - /* Decrement the nesting count as we are leaving a critical section. */ - ulCriticalNesting--; - - /* If the nesting level has reached zero then interrupts should be - re-enabled. */ - if( ulCriticalNesting == portNO_CRITICAL_NESTING ) - { - /* Enable interrupts as per portEXIT_CRITICAL(). */ - asm volatile ( - "STMDB SP!, {R0} \n\t" /* Push R0. */ - "MRS R0, CPSR \n\t" /* Get CPSR. */ - "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ - "LDMIA SP!, {R0}" ); /* Pop R0. */ - } - } -} - diff --git a/Source/portable/GCC/ARM7_AT91FR40008/portmacro.h b/Source/portable/GCC/ARM7_AT91FR40008/portmacro.h deleted file mode 100644 index 9e85cad15..000000000 --- a/Source/portable/GCC/ARM7_AT91FR40008/portmacro.h +++ /dev/null @@ -1,269 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - Changes from V3.2.3 - - + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1. - - Changes from V3.2.4 - - + Removed the use of the %0 parameter within the assembler macros and - replaced them with hard coded registers. This will ensure the - assembler does not select the link register as the temp register as - was occasionally happening previously. - - + The assembler statements are now included in a single asm block rather - than each line having its own asm block. -*/ - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -/*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the - * given hardware and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - -/* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE unsigned portLONG -#define portBASE_TYPE long - -#if( configUSE_16_BIT_TICKS == 1 ) - typedef unsigned portSHORT portTickType; - #define portMAX_DELAY ( portTickType ) 0xffff -#else - typedef unsigned portLONG portTickType; - #define portMAX_DELAY ( portTickType ) 0xffffffff -#endif -/*-----------------------------------------------------------*/ - -/* Hardware specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 4 -#define portYIELD() asm volatile ( "SWI" ); -#define portNOP() asm volatile ( "NOP" ); - -/* - * These define the timer to use for generating the tick interrupt. - * They are put in this file so they can be shared between "port.c" - * and "portisr.c". - */ -#define portTIMER_REG_BASE_PTR AT91C_BASE_TC0 -#define portTIMER_CLK_ENABLE_BIT AT91C_PS_TC0 -#define portTIMER_AIC_CHANNEL ( ( unsigned portLONG ) 4 ) -/*-----------------------------------------------------------*/ - -/* Task utilities. */ - -/* - * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR - * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but - * are included here for efficiency. An attempt to call one from - * THUMB mode code will result in a compile time error. - */ - -#define portRESTORE_CONTEXT() \ -{ \ -extern volatile void * volatile pxCurrentTCB; \ -extern volatile unsigned portLONG ulCriticalNesting; \ - \ - /* Set the LR to the task stack. */ \ - asm volatile ( \ - "LDR R0, =pxCurrentTCB \n\t" \ - "LDR R0, [R0] \n\t" \ - "LDR LR, [R0] \n\t" \ - \ - /* The critical nesting depth is the first item on the stack. */ \ - /* Load it into the ulCriticalNesting variable. */ \ - "LDR R0, =ulCriticalNesting \n\t" \ - "LDMFD LR!, {R1} \n\t" \ - "STR R1, [R0] \n\t" \ - \ - /* Get the SPSR from the stack. */ \ - "LDMFD LR!, {R0} \n\t" \ - "MSR SPSR, R0 \n\t" \ - \ - /* Restore all system mode registers for the task. */ \ - "LDMFD LR, {R0-R14}^ \n\t" \ - "NOP \n\t" \ - \ - /* Restore the return address. */ \ - "LDR LR, [LR, #+60] \n\t" \ - \ - /* And return - correcting the offset in the LR to obtain the */ \ - /* correct address. */ \ - "SUBS PC, LR, #4 \n\t" \ - ); \ - ( void ) ulCriticalNesting; \ - ( void ) pxCurrentTCB; \ -} -/*-----------------------------------------------------------*/ - -#define portSAVE_CONTEXT() \ -{ \ -extern volatile void * volatile pxCurrentTCB; \ -extern volatile unsigned portLONG ulCriticalNesting; \ - \ - /* Push R0 as we are going to use the register. */ \ - asm volatile ( \ - "STMDB SP!, {R0} \n\t" \ - \ - /* Set R0 to point to the task stack pointer. */ \ - "STMDB SP,{SP}^ \n\t" \ - "NOP \n\t" \ - "SUB SP, SP, #4 \n\t" \ - "LDMIA SP!,{R0} \n\t" \ - \ - /* Push the return address onto the stack. */ \ - "STMDB R0!, {LR} \n\t" \ - \ - /* Now we have saved LR we can use it instead of R0. */ \ - "MOV LR, R0 \n\t" \ - \ - /* Pop R0 so we can save it onto the system mode stack. */ \ - "LDMIA SP!, {R0} \n\t" \ - \ - /* Push all the system mode registers onto the task stack. */ \ - "STMDB LR,{R0-LR}^ \n\t" \ - "NOP \n\t" \ - "SUB LR, LR, #60 \n\t" \ - \ - /* Push the SPSR onto the task stack. */ \ - "MRS R0, SPSR \n\t" \ - "STMDB LR!, {R0} \n\t" \ - \ - "LDR R0, =ulCriticalNesting \n\t" \ - "LDR R0, [R0] \n\t" \ - "STMDB LR!, {R0} \n\t" \ - \ - /* Store the new top of stack for the task. */ \ - "LDR R0, =pxCurrentTCB \n\t" \ - "LDR R0, [R0] \n\t" \ - "STR LR, [R0] \n\t" \ - ); \ - ( void ) ulCriticalNesting; \ - ( void ) pxCurrentTCB; \ -} - -/*----------------------------------------------------------- - * ISR entry and exit macros. These are only required if a task switch - * is required from the ISR. - *----------------------------------------------------------*/ - -#define portENTER_SWITCHING_ISR() \ - /* Save the context of the interrupted task. */ \ - portSAVE_CONTEXT(); \ - \ - /* We don't know the stack requirements for the ISR, so the frame */\ - /* pointer will be set to the top of the task stack, and the stack*/\ - /* pointer left where it is. The IRQ stack will get used for any */\ - /* functions calls made by this ISR. */ \ - asm volatile ( "SUB R11, LR, #4" ); \ - { - -#define portEXIT_SWITCHING_ISR( SwitchRequired ) \ - /* If a switch is required then we just need to call */ \ - /* vTaskSwitchContext() as the context has already been */ \ - /* saved. */ \ - if( SwitchRequired ) \ - { \ - vTaskSwitchContext(); \ - } \ - } \ - /* Restore the context of which ever task is now the highest */ \ - /* priority that is ready to run. */ \ - portRESTORE_CONTEXT(); -/*-----------------------------------------------------------*/ - -/* Critical section handling. */ - -/* - * The interrupt management utilities can only be called from ARM mode. When - * THUMB_INTERWORK is defined the utilities are defined as functions in - * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not - * defined then the utilities are defined as macros here - as per other ports. - */ - -#ifdef THUMB_INTERWORK - - extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); - extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); - - #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb() - #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb() - -#else - - #define portDISABLE_INTERRUPTS() \ - asm volatile ( \ - "STMDB SP!, {R0} \n\t" /* Push R0. */ \ - "MRS R0, CPSR \n\t" /* Get CPSR. */ \ - "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ - "LDMIA SP!, {R0} " ) /* Pop R0. */ - - #define portENABLE_INTERRUPTS() \ - asm volatile ( \ - "STMDB SP!, {R0} \n\t" /* Push R0. */ \ - "MRS R0, CPSR \n\t" /* Get CPSR. */ \ - "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ - "LDMIA SP!, {R0} " ) /* Pop R0. */ - -#endif /* THUMB_INTERWORK */ - -extern void vPortEnterCritical( void ); -extern void vPortExitCritical( void ); - -#define portENTER_CRITICAL() vPortEnterCritical(); -#define portEXIT_CRITICAL() vPortExitCritical(); - -/*-----------------------------------------------------------*/ - -/* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) - -#endif /* PORTMACRO_H */ - diff --git a/Source/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h b/Source/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h deleted file mode 100644 index a14279e0b..000000000 --- a/Source/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h +++ /dev/null @@ -1,2731 +0,0 @@ -// ---------------------------------------------------------------------------- -// ATMEL Microcontroller Software Support - ROUSSET - -// ---------------------------------------------------------------------------- -// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// ---------------------------------------------------------------------------- -// File Name : AT91SAM7X256.h -// Object : AT91SAM7X256 definitions -// Generated : AT91 SW Application Group 05/20/2005 (16:22:29) -// -// CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005// -// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// -// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// -// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// -// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// -// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// -// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// -// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// -// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// -// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// -// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// -// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// -// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// -// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// -// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// -// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// -// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// -// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// -// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// -// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// -// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// -// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// -// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// -// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// -// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// -// ---------------------------------------------------------------------------- - -#ifndef AT91SAM7X256_H -#define AT91SAM7X256_H - -typedef volatile unsigned int AT91_REG;// Hardware register definition - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Peripherals -// ***************************************************************************** -typedef struct _AT91S_SYS { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register - AT91_REG Reserved2[45]; // - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved3[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved4[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register - AT91_REG Reserved5[54]; // - AT91_REG PIOA_PER; // PIO Enable Register - AT91_REG PIOA_PDR; // PIO Disable Register - AT91_REG PIOA_PSR; // PIO Status Register - AT91_REG Reserved6[1]; // - AT91_REG PIOA_OER; // Output Enable Register - AT91_REG PIOA_ODR; // Output Disable Registerr - AT91_REG PIOA_OSR; // Output Status Register - AT91_REG Reserved7[1]; // - AT91_REG PIOA_IFER; // Input Filter Enable Register - AT91_REG PIOA_IFDR; // Input Filter Disable Register - AT91_REG PIOA_IFSR; // Input Filter Status Register - AT91_REG Reserved8[1]; // - AT91_REG PIOA_SODR; // Set Output Data Register - AT91_REG PIOA_CODR; // Clear Output Data Register - AT91_REG PIOA_ODSR; // Output Data Status Register - AT91_REG PIOA_PDSR; // Pin Data Status Register - AT91_REG PIOA_IER; // Interrupt Enable Register - AT91_REG PIOA_IDR; // Interrupt Disable Register - AT91_REG PIOA_IMR; // Interrupt Mask Register - AT91_REG PIOA_ISR; // Interrupt Status Register - AT91_REG PIOA_MDER; // Multi-driver Enable Register - AT91_REG PIOA_MDDR; // Multi-driver Disable Register - AT91_REG PIOA_MDSR; // Multi-driver Status Register - AT91_REG Reserved9[1]; // - AT91_REG PIOA_PPUDR; // Pull-up Disable Register - AT91_REG PIOA_PPUER; // Pull-up Enable Register - AT91_REG PIOA_PPUSR; // Pull-up Status Register - AT91_REG Reserved10[1]; // - AT91_REG PIOA_ASR; // Select A Register - AT91_REG PIOA_BSR; // Select B Register - AT91_REG PIOA_ABSR; // AB Select Status Register - AT91_REG Reserved11[9]; // - AT91_REG PIOA_OWER; // Output Write Enable Register - AT91_REG PIOA_OWDR; // Output Write Disable Register - AT91_REG PIOA_OWSR; // Output Write Status Register - AT91_REG Reserved12[85]; // - AT91_REG PIOB_PER; // PIO Enable Register - AT91_REG PIOB_PDR; // PIO Disable Register - AT91_REG PIOB_PSR; // PIO Status Register - AT91_REG Reserved13[1]; // - AT91_REG PIOB_OER; // Output Enable Register - AT91_REG PIOB_ODR; // Output Disable Registerr - AT91_REG PIOB_OSR; // Output Status Register - AT91_REG Reserved14[1]; // - AT91_REG PIOB_IFER; // Input Filter Enable Register - AT91_REG PIOB_IFDR; // Input Filter Disable Register - AT91_REG PIOB_IFSR; // Input Filter Status Register - AT91_REG Reserved15[1]; // - AT91_REG PIOB_SODR; // Set Output Data Register - AT91_REG PIOB_CODR; // Clear Output Data Register - AT91_REG PIOB_ODSR; // Output Data Status Register - AT91_REG PIOB_PDSR; // Pin Data Status Register - AT91_REG PIOB_IER; // Interrupt Enable Register - AT91_REG PIOB_IDR; // Interrupt Disable Register - AT91_REG PIOB_IMR; // Interrupt Mask Register - AT91_REG PIOB_ISR; // Interrupt Status Register - AT91_REG PIOB_MDER; // Multi-driver Enable Register - AT91_REG PIOB_MDDR; // Multi-driver Disable Register - AT91_REG PIOB_MDSR; // Multi-driver Status Register - AT91_REG Reserved16[1]; // - AT91_REG PIOB_PPUDR; // Pull-up Disable Register - AT91_REG PIOB_PPUER; // Pull-up Enable Register - AT91_REG PIOB_PPUSR; // Pull-up Status Register - AT91_REG Reserved17[1]; // - AT91_REG PIOB_ASR; // Select A Register - AT91_REG PIOB_BSR; // Select B Register - AT91_REG PIOB_ABSR; // AB Select Status Register - AT91_REG Reserved18[9]; // - AT91_REG PIOB_OWER; // Output Write Enable Register - AT91_REG PIOB_OWDR; // Output Write Disable Register - AT91_REG PIOB_OWSR; // Output Write Status Register - AT91_REG Reserved19[341]; // - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved20[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved21[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved22[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved23[3]; // - AT91_REG PMC_PCKR[4]; // Programmable Clock Register - AT91_REG Reserved24[4]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register - AT91_REG Reserved25[36]; // - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register - AT91_REG Reserved26[5]; // - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register - AT91_REG Reserved27[5]; // - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_SYS, *AT91PS_SYS; - - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// ***************************************************************************** -typedef struct _AT91S_AIC { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register -} AT91S_AIC, *AT91PS_AIC; - -// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level -#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level -#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level -#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type -#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive -#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered -#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered -#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered -// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status -#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status -// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode -#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Peripheral DMA Controller -// ***************************************************************************** -typedef struct _AT91S_PDC { - AT91_REG PDC_RPR; // Receive Pointer Register - AT91_REG PDC_RCR; // Receive Counter Register - AT91_REG PDC_TPR; // Transmit Pointer Register - AT91_REG PDC_TCR; // Transmit Counter Register - AT91_REG PDC_RNPR; // Receive Next Pointer Register - AT91_REG PDC_RNCR; // Receive Next Counter Register - AT91_REG PDC_TNPR; // Transmit Next Pointer Register - AT91_REG PDC_TNCR; // Transmit Next Counter Register - AT91_REG PDC_PTCR; // PDC Transfer Control Register - AT91_REG PDC_PTSR; // PDC Transfer Status Register -} AT91S_PDC, *AT91PS_PDC; - -// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable -#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable -#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable -#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable -// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Debug Unit -// ***************************************************************************** -typedef struct _AT91S_DBGU { - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved0[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved1[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register -} AT91S_DBGU, *AT91PS_DBGU; - -// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver -#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter -#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable -#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable -#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable -#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable -#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits -// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type -#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity -#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity -#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space) -#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark) -#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity -#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode -#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode -#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt -#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt -#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt -#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt -#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt -#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt -#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt -#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt -#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt -#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt -#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt -#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt -// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// ***************************************************************************** -typedef struct _AT91S_PIO { - AT91_REG PIO_PER; // PIO Enable Register - AT91_REG PIO_PDR; // PIO Disable Register - AT91_REG PIO_PSR; // PIO Status Register - AT91_REG Reserved0[1]; // - AT91_REG PIO_OER; // Output Enable Register - AT91_REG PIO_ODR; // Output Disable Registerr - AT91_REG PIO_OSR; // Output Status Register - AT91_REG Reserved1[1]; // - AT91_REG PIO_IFER; // Input Filter Enable Register - AT91_REG PIO_IFDR; // Input Filter Disable Register - AT91_REG PIO_IFSR; // Input Filter Status Register - AT91_REG Reserved2[1]; // - AT91_REG PIO_SODR; // Set Output Data Register - AT91_REG PIO_CODR; // Clear Output Data Register - AT91_REG PIO_ODSR; // Output Data Status Register - AT91_REG PIO_PDSR; // Pin Data Status Register - AT91_REG PIO_IER; // Interrupt Enable Register - AT91_REG PIO_IDR; // Interrupt Disable Register - AT91_REG PIO_IMR; // Interrupt Mask Register - AT91_REG PIO_ISR; // Interrupt Status Register - AT91_REG PIO_MDER; // Multi-driver Enable Register - AT91_REG PIO_MDDR; // Multi-driver Disable Register - AT91_REG PIO_MDSR; // Multi-driver Status Register - AT91_REG Reserved3[1]; // - AT91_REG PIO_PPUDR; // Pull-up Disable Register - AT91_REG PIO_PPUER; // Pull-up Enable Register - AT91_REG PIO_PPUSR; // Pull-up Status Register - AT91_REG Reserved4[1]; // - AT91_REG PIO_ASR; // Select A Register - AT91_REG PIO_BSR; // Select B Register - AT91_REG PIO_ABSR; // AB Select Status Register - AT91_REG Reserved5[9]; // - AT91_REG PIO_OWER; // Output Write Enable Register - AT91_REG PIO_OWDR; // Output Write Disable Register - AT91_REG PIO_OWSR; // Output Write Status Register -} AT91S_PIO, *AT91PS_PIO; - - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Clock Generator Controler -// ***************************************************************************** -typedef struct _AT91S_CKGR { - AT91_REG CKGR_MOR; // Main Oscillator Register - AT91_REG CKGR_MCFR; // Main Clock Frequency Register - AT91_REG Reserved0[1]; // - AT91_REG CKGR_PLLR; // PLL Register -} AT91S_CKGR, *AT91PS_CKGR; - -// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable -#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass -#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time -// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency -#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready -// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- -#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter -#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range -#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier -#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks -#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output -#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 -#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Power Management Controler -// ***************************************************************************** -typedef struct _AT91S_PMC { - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved0[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved1[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved2[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved3[3]; // - AT91_REG PMC_PCKR[4]; // Programmable Clock Register - AT91_REG Reserved4[4]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register -} AT91S_PMC, *AT91PS_PMC; - -// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock -#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock -#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output -// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- -// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- -// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- -// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection -#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected -#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected -#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected -#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler -#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock -#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 -#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 -#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 -#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 -#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 -#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 -// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask -#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask -#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask -// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Reset Controller Interface -// ***************************************************************************** -typedef struct _AT91S_RSTC { - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register -} AT91S_RSTC, *AT91PS_RSTC; - -// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- -#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset -#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset -#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset -#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password -// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- -#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status -#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status -#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type -#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. -#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. -#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low. -#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured. -#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level -#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress. -// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- -#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable -#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable -#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable -#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_RTTC { - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register -} AT91S_RTTC, *AT91PS_RTTC; - -// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- -#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value -#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable -#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable -#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart -// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- -#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value -// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- -#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value -// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- -#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status -#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_PITC { - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register -} AT91S_PITC, *AT91PS_PITC; - -// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- -#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value -#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled -#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable -// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- -#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status -// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- -#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value -#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter -// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_WDTC { - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register -} AT91S_WDTC, *AT91PS_WDTC; - -// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- -#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart -#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password -// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- -#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable -#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable -#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable -#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value -#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt -#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt -// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- -#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow -#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface -// ***************************************************************************** -typedef struct _AT91S_VREG { - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_VREG, *AT91PS_VREG; - -// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- -#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Memory Controller Interface -// ***************************************************************************** -typedef struct _AT91S_MC { - AT91_REG MC_RCR; // MC Remap Control Register - AT91_REG MC_ASR; // MC Abort Status Register - AT91_REG MC_AASR; // MC Abort Address Status Register - AT91_REG Reserved0[21]; // - AT91_REG MC_FMR; // MC Flash Mode Register - AT91_REG MC_FCR; // MC Flash Command Register - AT91_REG MC_FSR; // MC Flash Status Register -} AT91S_MC, *AT91PS_MC; - -// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit -// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status -#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status -#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status -#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte -#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word -#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word -#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status -#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read -#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write -#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch -#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source -#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source -#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source -#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source -// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- -#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready -#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error -#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error -#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming -#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State -#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations -#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations -#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations -#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations -#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number -// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- -#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command -#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN. -#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. -#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. -#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits. -#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits. -#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit. -#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number -#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key -// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- -#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status -#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status -#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status -#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status -#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status -#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status -#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status -#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status -#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status -#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status -#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status -#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status -#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status -#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status -#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status -#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status -#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status -#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status -#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status -#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status -#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status -#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status -#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Serial Parallel Interface -// ***************************************************************************** -typedef struct _AT91S_SPI { - AT91_REG SPI_CR; // Control Register - AT91_REG SPI_MR; // Mode Register - AT91_REG SPI_RDR; // Receive Data Register - AT91_REG SPI_TDR; // Transmit Data Register - AT91_REG SPI_SR; // Status Register - AT91_REG SPI_IER; // Interrupt Enable Register - AT91_REG SPI_IDR; // Interrupt Disable Register - AT91_REG SPI_IMR; // Interrupt Mask Register - AT91_REG Reserved0[4]; // - AT91_REG SPI_CSR[4]; // Chip Select Register - AT91_REG Reserved1[48]; // - AT91_REG SPI_RPR; // Receive Pointer Register - AT91_REG SPI_RCR; // Receive Counter Register - AT91_REG SPI_TPR; // Transmit Pointer Register - AT91_REG SPI_TCR; // Transmit Counter Register - AT91_REG SPI_RNPR; // Receive Next Pointer Register - AT91_REG SPI_RNCR; // Receive Next Counter Register - AT91_REG SPI_TNPR; // Transmit Next Pointer Register - AT91_REG SPI_TNCR; // Transmit Next Counter Register - AT91_REG SPI_PTCR; // PDC Transfer Control Register - AT91_REG SPI_PTSR; // PDC Transfer Status Register -} AT91S_SPI, *AT91PS_SPI; - -// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable -#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable -#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset -#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer -// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode -#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select -#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select -#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select -#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode -#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection -#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection -#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection -#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select -#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects -// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data -#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data -#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full -#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty -#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error -#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status -#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer -#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer -#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt -#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt -#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt -#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt -#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status -// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity -#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase -#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer -#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer -#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer -#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer -#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer -#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer -#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer -#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer -#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer -#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer -#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer -#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK -#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Usart -// ***************************************************************************** -typedef struct _AT91S_USART { - AT91_REG US_CR; // Control Register - AT91_REG US_MR; // Mode Register - AT91_REG US_IER; // Interrupt Enable Register - AT91_REG US_IDR; // Interrupt Disable Register - AT91_REG US_IMR; // Interrupt Mask Register - AT91_REG US_CSR; // Channel Status Register - AT91_REG US_RHR; // Receiver Holding Register - AT91_REG US_THR; // Transmitter Holding Register - AT91_REG US_BRGR; // Baud Rate Generator Register - AT91_REG US_RTOR; // Receiver Time-out Register - AT91_REG US_TTGR; // Transmitter Time-guard Register - AT91_REG Reserved0[5]; // - AT91_REG US_FIDI; // FI_DI_Ratio Register - AT91_REG US_NER; // Nb Errors Register - AT91_REG Reserved1[1]; // - AT91_REG US_IF; // IRDA_FILTER Register - AT91_REG Reserved2[44]; // - AT91_REG US_RPR; // Receive Pointer Register - AT91_REG US_RCR; // Receive Counter Register - AT91_REG US_TPR; // Transmit Pointer Register - AT91_REG US_TCR; // Transmit Counter Register - AT91_REG US_RNPR; // Receive Next Pointer Register - AT91_REG US_RNCR; // Receive Next Counter Register - AT91_REG US_TNPR; // Transmit Next Pointer Register - AT91_REG US_TNCR; // Transmit Next Counter Register - AT91_REG US_PTCR; // PDC Transfer Control Register - AT91_REG US_PTSR; // PDC Transfer Status Register -} AT91S_USART, *AT91PS_USART; - -// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break -#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break -#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out -#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address -#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations -#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge -#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out -#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable -#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable -#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable -#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable -// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode -#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal -#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 -#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking -#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem -#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0 -#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1 -#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA -#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking -#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock -#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 -#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) -#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) -#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits -#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits -#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits -#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits -#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select -#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits -#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit -#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits -#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order -#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length -#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select -#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode -#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge -#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK -#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions -#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter -// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break -#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out -#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached -#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge -#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag -#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag -#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag -#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag -// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input -#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input -#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input -#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// ***************************************************************************** -typedef struct _AT91S_SSC { - AT91_REG SSC_CR; // Control Register - AT91_REG SSC_CMR; // Clock Mode Register - AT91_REG Reserved0[2]; // - AT91_REG SSC_RCMR; // Receive Clock ModeRegister - AT91_REG SSC_RFMR; // Receive Frame Mode Register - AT91_REG SSC_TCMR; // Transmit Clock Mode Register - AT91_REG SSC_TFMR; // Transmit Frame Mode Register - AT91_REG SSC_RHR; // Receive Holding Register - AT91_REG SSC_THR; // Transmit Holding Register - AT91_REG Reserved1[2]; // - AT91_REG SSC_RSHR; // Receive Sync Holding Register - AT91_REG SSC_TSHR; // Transmit Sync Holding Register - AT91_REG Reserved2[2]; // - AT91_REG SSC_SR; // Status Register - AT91_REG SSC_IER; // Interrupt Enable Register - AT91_REG SSC_IDR; // Interrupt Disable Register - AT91_REG SSC_IMR; // Interrupt Mask Register - AT91_REG Reserved3[44]; // - AT91_REG SSC_RPR; // Receive Pointer Register - AT91_REG SSC_RCR; // Receive Counter Register - AT91_REG SSC_TPR; // Transmit Pointer Register - AT91_REG SSC_TCR; // Transmit Counter Register - AT91_REG SSC_RNPR; // Receive Next Pointer Register - AT91_REG SSC_RNCR; // Receive Next Counter Register - AT91_REG SSC_TNPR; // Transmit Next Pointer Register - AT91_REG SSC_TNCR; // Transmit Next Counter Register - AT91_REG SSC_PTCR; // PDC Transfer Control Register - AT91_REG SSC_PTSR; // PDC Transfer Status Register -} AT91S_SSC, *AT91PS_SSC; - -// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable -#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable -#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable -#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable -#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset -// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection -#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock -#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal -#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin -#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection -#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output -#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion -#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection -#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start -#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input -#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input -#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input -#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input -#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input -#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input -#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0 -#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay -#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection -// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length -#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode -#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First -#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame -#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length -#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection -#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection -// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value -#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable -// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready -#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty -#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission -#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty -#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready -#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun -#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception -#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full -#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync -#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync -#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable -#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable -// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Two-wire Interface -// ***************************************************************************** -typedef struct _AT91S_TWI { - AT91_REG TWI_CR; // Control Register - AT91_REG TWI_MMR; // Master Mode Register - AT91_REG Reserved0[1]; // - AT91_REG TWI_IADR; // Internal Address Register - AT91_REG TWI_CWGR; // Clock Waveform Generator Register - AT91_REG Reserved1[3]; // - AT91_REG TWI_SR; // Status Register - AT91_REG TWI_IER; // Interrupt Enable Register - AT91_REG TWI_IDR; // Interrupt Disable Register - AT91_REG TWI_IMR; // Interrupt Mask Register - AT91_REG TWI_RHR; // Receive Holding Register - AT91_REG TWI_THR; // Transmit Holding Register -} AT91S_TWI, *AT91PS_TWI; - -// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition -#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition -#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled -#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled -#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset -// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size -#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address -#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address -#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address -#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address -#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction -#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address -// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider -#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider -#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider -// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed -#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY -#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY -#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error -#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error -#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged -// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR PWMC Channel Interface -// ***************************************************************************** -typedef struct _AT91S_PWMC_CH { - AT91_REG PWMC_CMR; // Channel Mode Register - AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register - AT91_REG PWMC_CPRDR; // Channel Period Register - AT91_REG PWMC_CCNTR; // Channel Counter Register - AT91_REG PWMC_CUPDR; // Channel Update Register - AT91_REG PWMC_Reserved[3]; // Reserved -} AT91S_PWMC_CH, *AT91PS_PWMC_CH; - -// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- -#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx -#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) -#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment -#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity -#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period -// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- -#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle -// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- -#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period -// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- -#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter -// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- -#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface -// ***************************************************************************** -typedef struct _AT91S_PWMC { - AT91_REG PWMC_MR; // PWMC Mode Register - AT91_REG PWMC_ENA; // PWMC Enable Register - AT91_REG PWMC_DIS; // PWMC Disable Register - AT91_REG PWMC_SR; // PWMC Status Register - AT91_REG PWMC_IER; // PWMC Interrupt Enable Register - AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register - AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register - AT91_REG PWMC_ISR; // PWMC Interrupt Status Register - AT91_REG Reserved0[55]; // - AT91_REG PWMC_VR; // PWMC Version Register - AT91_REG Reserved1[64]; // - AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel -} AT91S_PWMC, *AT91PS_PWMC; - -// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- -#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor. -#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A -#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) -#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor. -#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B -#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) -// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- -#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0 -#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1 -#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2 -#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3 -// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- -// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- -// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- -// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- -// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- -// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Device Interface -// ***************************************************************************** -typedef struct _AT91S_UDP { - AT91_REG UDP_NUM; // Frame Number Register - AT91_REG UDP_GLBSTATE; // Global State Register - AT91_REG UDP_FADDR; // Function Address Register - AT91_REG Reserved0[1]; // - AT91_REG UDP_IER; // Interrupt Enable Register - AT91_REG UDP_IDR; // Interrupt Disable Register - AT91_REG UDP_IMR; // Interrupt Mask Register - AT91_REG UDP_ISR; // Interrupt Status Register - AT91_REG UDP_ICR; // Interrupt Clear Register - AT91_REG Reserved1[1]; // - AT91_REG UDP_RSTEP; // Reset Endpoint Register - AT91_REG Reserved2[1]; // - AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register - AT91_REG Reserved3[2]; // - AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register - AT91_REG Reserved4[3]; // - AT91_REG UDP_TXVC; // Transceiver Control Register -} AT91S_UDP, *AT91PS_UDP; - -// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats -#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error -#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK -// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable -#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured -#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume -#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host -#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable -// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value -#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable -// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt -#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt -#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt -#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt -#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt -#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt -#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt -#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt -#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt -// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt -// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 -#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 -#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 -#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3 -#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4 -#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5 -// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR -#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 -#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) -#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) -#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready -#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction -#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type -#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control -#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT -#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT -#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT -#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN -#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN -#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN -#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle -#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable -#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO -// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- -#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP) -#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// ***************************************************************************** -typedef struct _AT91S_TC { - AT91_REG TC_CCR; // Channel Control Register - AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) - AT91_REG Reserved0[2]; // - AT91_REG TC_CV; // Counter Value - AT91_REG TC_RA; // Register A - AT91_REG TC_RB; // Register B - AT91_REG TC_RC; // Register C - AT91_REG TC_SR; // Status Register - AT91_REG TC_IER; // Interrupt Enable Register - AT91_REG TC_IDR; // Interrupt Disable Register - AT91_REG TC_IMR; // Interrupt Mask Register -} AT91S_TC, *AT91PS_TC; - -// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command -#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command -#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command -// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection -#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK -#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0 -#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1 -#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2 -#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert -#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection -#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal -#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock -#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock -#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock -#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare -#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading -#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare -#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading -#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection -#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None -#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection -#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None -#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection -#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input -#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output -#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output -#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output -#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection -#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable -#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection -#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare -#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable -#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) -#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA -#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none -#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set -#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear -#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle -#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection -#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None -#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA -#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA -#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none -#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set -#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear -#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle -#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection -#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None -#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA -#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA -#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none -#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set -#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear -#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle -#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA -#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none -#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set -#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear -#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle -#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB -#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none -#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set -#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear -#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle -#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB -#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none -#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set -#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear -#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle -#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB -#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none -#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set -#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear -#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle -#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB -#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none -#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set -#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear -#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle -// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow -#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun -#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare -#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare -#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare -#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading -#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading -#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger -#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling -#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror -#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror -// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Interface -// ***************************************************************************** -typedef struct _AT91S_TCB { - AT91S_TC TCB_TC0; // TC Channel 0 - AT91_REG Reserved0[4]; // - AT91S_TC TCB_TC1; // TC Channel 1 - AT91_REG Reserved1[4]; // - AT91S_TC TCB_TC2; // TC Channel 2 - AT91_REG Reserved2[4]; // - AT91_REG TCB_BCR; // TC Block Control Register - AT91_REG TCB_BMR; // TC Block Mode Register -} AT91S_TCB, *AT91PS_TCB; - -// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command -// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection -#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 -#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 -#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection -#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 -#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 -#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection -#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 -#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface -// ***************************************************************************** -typedef struct _AT91S_CAN_MB { - AT91_REG CAN_MB_MMR; // MailBox Mode Register - AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register - AT91_REG CAN_MB_MID; // MailBox ID Register - AT91_REG CAN_MB_MFID; // MailBox Family ID Register - AT91_REG CAN_MB_MSR; // MailBox Status Register - AT91_REG CAN_MB_MDL; // MailBox Data Low Register - AT91_REG CAN_MB_MDH; // MailBox Data High Register - AT91_REG CAN_MB_MCR; // MailBox Control Register -} AT91S_CAN_MB, *AT91PS_CAN_MB; - -// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- -#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark -#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority -#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type -#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB) -// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- -#define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode -#define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode -#define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version -// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- -// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- -// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- -#define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value -#define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code -#define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request -#define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort -#define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready -#define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored -// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- -// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- -// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- -#define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox -#define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network Interface -// ***************************************************************************** -typedef struct _AT91S_CAN { - AT91_REG CAN_MR; // Mode Register - AT91_REG CAN_IER; // Interrupt Enable Register - AT91_REG CAN_IDR; // Interrupt Disable Register - AT91_REG CAN_IMR; // Interrupt Mask Register - AT91_REG CAN_SR; // Status Register - AT91_REG CAN_BR; // Baudrate Register - AT91_REG CAN_TIM; // Timer Register - AT91_REG CAN_TIMESTP; // Time Stamp Register - AT91_REG CAN_ECR; // Error Counter Register - AT91_REG CAN_TCR; // Transfer Command Register - AT91_REG CAN_ACR; // Abort Command Register - AT91_REG Reserved0[52]; // - AT91_REG CAN_VR; // Version Register - AT91_REG Reserved1[64]; // - AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0 - AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1 - AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2 - AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3 - AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4 - AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5 - AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6 - AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7 - AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8 - AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9 - AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10 - AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11 - AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12 - AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13 - AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14 - AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15 -} AT91S_CAN, *AT91PS_CAN; - -// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- -#define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable -#define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode -#define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode -#define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame -#define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame -#define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode -#define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze -#define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat -// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- -#define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag -#define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag -#define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag -#define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag -#define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag -#define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag -#define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag -#define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag -#define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag -#define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag -#define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag -#define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag -#define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag -#define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag -#define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag -#define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag -#define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag -#define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag -#define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag -#define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag -#define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag -#define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag -#define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag -#define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag -#define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error -#define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error -#define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error -#define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error -#define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error -// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- -// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- -// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- -#define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy -#define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy -#define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy -// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- -#define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment -#define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment -#define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment -#define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment -#define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler -#define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode -// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- -#define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field -// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- -// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- -#define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter -#define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter -// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- -#define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field -// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 -// ***************************************************************************** -typedef struct _AT91S_EMAC { - AT91_REG EMAC_NCR; // Network Control Register - AT91_REG EMAC_NCFGR; // Network Configuration Register - AT91_REG EMAC_NSR; // Network Status Register - AT91_REG Reserved0[2]; // - AT91_REG EMAC_TSR; // Transmit Status Register - AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer - AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer - AT91_REG EMAC_RSR; // Receive Status Register - AT91_REG EMAC_ISR; // Interrupt Status Register - AT91_REG EMAC_IER; // Interrupt Enable Register - AT91_REG EMAC_IDR; // Interrupt Disable Register - AT91_REG EMAC_IMR; // Interrupt Mask Register - AT91_REG EMAC_MAN; // PHY Maintenance Register - AT91_REG EMAC_PTR; // Pause Time Register - AT91_REG EMAC_PFR; // Pause Frames received Register - AT91_REG EMAC_FTO; // Frames Transmitted OK Register - AT91_REG EMAC_SCF; // Single Collision Frame Register - AT91_REG EMAC_MCF; // Multiple Collision Frame Register - AT91_REG EMAC_FRO; // Frames Received OK Register - AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register - AT91_REG EMAC_ALE; // Alignment Error Register - AT91_REG EMAC_DTF; // Deferred Transmission Frame Register - AT91_REG EMAC_LCOL; // Late Collision Register - AT91_REG EMAC_ECOL; // Excessive Collision Register - AT91_REG EMAC_TUND; // Transmit Underrun Error Register - AT91_REG EMAC_CSE; // Carrier Sense Error Register - AT91_REG EMAC_RRE; // Receive Ressource Error Register - AT91_REG EMAC_ROV; // Receive Overrun Errors Register - AT91_REG EMAC_RSE; // Receive Symbol Errors Register - AT91_REG EMAC_ELE; // Excessive Length Errors Register - AT91_REG EMAC_RJA; // Receive Jabbers Register - AT91_REG EMAC_USF; // Undersize Frames Register - AT91_REG EMAC_STE; // SQE Test Error Register - AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register - AT91_REG EMAC_TPF; // Transmitted Pause Frames Register - AT91_REG EMAC_HRB; // Hash Address Bottom[31:0] - AT91_REG EMAC_HRT; // Hash Address Top[63:32] - AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes - AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes - AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes - AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes - AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes - AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes - AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes - AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes - AT91_REG EMAC_TID; // Type ID Checking Register - AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register - AT91_REG EMAC_USRIO; // USER Input/Output Register - AT91_REG EMAC_WOL; // Wake On LAN Register - AT91_REG Reserved1[13]; // - AT91_REG EMAC_REV; // Revision Register -} AT91S_EMAC, *AT91PS_EMAC; - -// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- -#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. -#define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local. -#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable. -#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable. -#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable. -#define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers. -#define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers. -#define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers. -#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure. -#define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission. -#define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. -#define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame -#define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame -// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- -#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed. -#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex. -#define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames. -#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames. -#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast. -#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable -#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable. -#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes. -#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable. -#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC) -#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8 -#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16 -#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32 -#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64 -#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC) -#define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC) -#define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC) -#define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer -#define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable -#define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS -#define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC) -#define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS -// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- -#define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC) -// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- -#define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC) -#define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go -#define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame -#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC) -#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC) -// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- -#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC) -// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- -#define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC) -#define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC) -#define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC) -#define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC) -#define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC) -#define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC) -#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC) -#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC) -#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC) -#define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC) -#define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC) -// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- -// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- -// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- -// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- -#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC) -#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC) -#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC) -#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC) -#define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC) -// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- -#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII -// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- -#define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address -#define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable -#define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable -#define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable -// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- -#define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC) - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Analog to Digital Convertor -// ***************************************************************************** -typedef struct _AT91S_ADC { - AT91_REG ADC_CR; // ADC Control Register - AT91_REG ADC_MR; // ADC Mode Register - AT91_REG Reserved0[2]; // - AT91_REG ADC_CHER; // ADC Channel Enable Register - AT91_REG ADC_CHDR; // ADC Channel Disable Register - AT91_REG ADC_CHSR; // ADC Channel Status Register - AT91_REG ADC_SR; // ADC Status Register - AT91_REG ADC_LCDR; // ADC Last Converted Data Register - AT91_REG ADC_IER; // ADC Interrupt Enable Register - AT91_REG ADC_IDR; // ADC Interrupt Disable Register - AT91_REG ADC_IMR; // ADC Interrupt Mask Register - AT91_REG ADC_CDR0; // ADC Channel Data Register 0 - AT91_REG ADC_CDR1; // ADC Channel Data Register 1 - AT91_REG ADC_CDR2; // ADC Channel Data Register 2 - AT91_REG ADC_CDR3; // ADC Channel Data Register 3 - AT91_REG ADC_CDR4; // ADC Channel Data Register 4 - AT91_REG ADC_CDR5; // ADC Channel Data Register 5 - AT91_REG ADC_CDR6; // ADC Channel Data Register 6 - AT91_REG ADC_CDR7; // ADC Channel Data Register 7 - AT91_REG Reserved1[44]; // - AT91_REG ADC_RPR; // Receive Pointer Register - AT91_REG ADC_RCR; // Receive Counter Register - AT91_REG ADC_TPR; // Transmit Pointer Register - AT91_REG ADC_TCR; // Transmit Counter Register - AT91_REG ADC_RNPR; // Receive Next Pointer Register - AT91_REG ADC_RNCR; // Receive Next Counter Register - AT91_REG ADC_TNPR; // Transmit Next Pointer Register - AT91_REG ADC_TNCR; // Transmit Next Counter Register - AT91_REG ADC_PTCR; // PDC Transfer Control Register - AT91_REG ADC_PTSR; // PDC Transfer Status Register -} AT91S_ADC, *AT91PS_ADC; - -// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- -#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset -#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion -// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- -#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable -#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software -#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. -#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection -#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 -#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 -#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 -#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 -#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 -#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 -#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger -#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution. -#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution -#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution -#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode -#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection -#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time -#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time -// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- -#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0 -#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1 -#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2 -#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3 -#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4 -#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5 -#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6 -#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7 -// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- -// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- -// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- -#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion -#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion -#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion -#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion -#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion -#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion -#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion -#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion -#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error -#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error -#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error -#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error -#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error -#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error -#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error -#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error -#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready -#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun -#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer -#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt -// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- -#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted -// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- -// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- -// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- -// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- -#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data -// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- -// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- -// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- -// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- -// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- -// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- -// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Encryption Standard -// ***************************************************************************** -typedef struct _AT91S_AES { - AT91_REG AES_CR; // Control Register - AT91_REG AES_MR; // Mode Register - AT91_REG Reserved0[2]; // - AT91_REG AES_IER; // Interrupt Enable Register - AT91_REG AES_IDR; // Interrupt Disable Register - AT91_REG AES_IMR; // Interrupt Mask Register - AT91_REG AES_ISR; // Interrupt Status Register - AT91_REG AES_KEYWxR[4]; // Key Word x Register - AT91_REG Reserved1[4]; // - AT91_REG AES_IDATAxR[4]; // Input Data x Register - AT91_REG AES_ODATAxR[4]; // Output Data x Register - AT91_REG AES_IVxR[4]; // Initialization Vector x Register - AT91_REG Reserved2[35]; // - AT91_REG AES_VR; // AES Version Register - AT91_REG AES_RPR; // Receive Pointer Register - AT91_REG AES_RCR; // Receive Counter Register - AT91_REG AES_TPR; // Transmit Pointer Register - AT91_REG AES_TCR; // Transmit Counter Register - AT91_REG AES_RNPR; // Receive Next Pointer Register - AT91_REG AES_RNCR; // Receive Next Counter Register - AT91_REG AES_TNPR; // Transmit Next Pointer Register - AT91_REG AES_TNCR; // Transmit Next Counter Register - AT91_REG AES_PTCR; // PDC Transfer Control Register - AT91_REG AES_PTSR; // PDC Transfer Status Register -} AT91S_AES, *AT91PS_AES; - -// -------- AES_CR : (AES Offset: 0x0) Control Register -------- -#define AT91C_AES_START ((unsigned int) 0x1 << 0) // (AES) Starts Processing -#define AT91C_AES_SWRST ((unsigned int) 0x1 << 8) // (AES) Software Reset -#define AT91C_AES_LOADSEED ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading -// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- -#define AT91C_AES_CIPHER ((unsigned int) 0x1 << 0) // (AES) Processing Mode -#define AT91C_AES_PROCDLY ((unsigned int) 0xF << 4) // (AES) Processing Delay -#define AT91C_AES_SMOD ((unsigned int) 0x3 << 8) // (AES) Start Mode -#define AT91C_AES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. -#define AT91C_AES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). -#define AT91C_AES_SMOD_PDC ((unsigned int) 0x2 << 8) // (AES) PDC Mode (cf datasheet). -#define AT91C_AES_OPMOD ((unsigned int) 0x7 << 12) // (AES) Operation Mode -#define AT91C_AES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode. -#define AT91C_AES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode. -#define AT91C_AES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode. -#define AT91C_AES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode. -#define AT91C_AES_OPMOD_CTR ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode. -#define AT91C_AES_LOD ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode -#define AT91C_AES_CFBS ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size -#define AT91C_AES_CFBS_128_BIT ((unsigned int) 0x0 << 16) // (AES) 128-bit. -#define AT91C_AES_CFBS_64_BIT ((unsigned int) 0x1 << 16) // (AES) 64-bit. -#define AT91C_AES_CFBS_32_BIT ((unsigned int) 0x2 << 16) // (AES) 32-bit. -#define AT91C_AES_CFBS_16_BIT ((unsigned int) 0x3 << 16) // (AES) 16-bit. -#define AT91C_AES_CFBS_8_BIT ((unsigned int) 0x4 << 16) // (AES) 8-bit. -#define AT91C_AES_CKEY ((unsigned int) 0xF << 20) // (AES) Countermeasure Key -#define AT91C_AES_CTYPE ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type -#define AT91C_AES_CTYPE_TYPE1_EN ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled. -#define AT91C_AES_CTYPE_TYPE2_EN ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled. -#define AT91C_AES_CTYPE_TYPE3_EN ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled. -#define AT91C_AES_CTYPE_TYPE4_EN ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled. -#define AT91C_AES_CTYPE_TYPE5_EN ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled. -// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- -#define AT91C_AES_DATRDY ((unsigned int) 0x1 << 0) // (AES) DATRDY -#define AT91C_AES_ENDRX ((unsigned int) 0x1 << 1) // (AES) PDC Read Buffer End -#define AT91C_AES_ENDTX ((unsigned int) 0x1 << 2) // (AES) PDC Write Buffer End -#define AT91C_AES_RXBUFF ((unsigned int) 0x1 << 3) // (AES) PDC Read Buffer Full -#define AT91C_AES_TXBUFE ((unsigned int) 0x1 << 4) // (AES) PDC Write Buffer Empty -#define AT91C_AES_URAD ((unsigned int) 0x1 << 8) // (AES) Unspecified Register Access Detection -// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- -// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- -// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- -#define AT91C_AES_URAT ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status -#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode. -#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing. -#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing. -#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation. -#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation. -#define AT91C_AES_URAT_WO_REG_READ ((unsigned int) 0x5 << 12) // (AES) Write-only register read access. - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard -// ***************************************************************************** -typedef struct _AT91S_TDES { - AT91_REG TDES_CR; // Control Register - AT91_REG TDES_MR; // Mode Register - AT91_REG Reserved0[2]; // - AT91_REG TDES_IER; // Interrupt Enable Register - AT91_REG TDES_IDR; // Interrupt Disable Register - AT91_REG TDES_IMR; // Interrupt Mask Register - AT91_REG TDES_ISR; // Interrupt Status Register - AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register - AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register - AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register - AT91_REG Reserved1[2]; // - AT91_REG TDES_IDATAxR[2]; // Input Data x Register - AT91_REG Reserved2[2]; // - AT91_REG TDES_ODATAxR[2]; // Output Data x Register - AT91_REG Reserved3[2]; // - AT91_REG TDES_IVxR[2]; // Initialization Vector x Register - AT91_REG Reserved4[37]; // - AT91_REG TDES_VR; // TDES Version Register - AT91_REG TDES_RPR; // Receive Pointer Register - AT91_REG TDES_RCR; // Receive Counter Register - AT91_REG TDES_TPR; // Transmit Pointer Register - AT91_REG TDES_TCR; // Transmit Counter Register - AT91_REG TDES_RNPR; // Receive Next Pointer Register - AT91_REG TDES_RNCR; // Receive Next Counter Register - AT91_REG TDES_TNPR; // Transmit Next Pointer Register - AT91_REG TDES_TNCR; // Transmit Next Counter Register - AT91_REG TDES_PTCR; // PDC Transfer Control Register - AT91_REG TDES_PTSR; // PDC Transfer Status Register -} AT91S_TDES, *AT91PS_TDES; - -// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- -#define AT91C_TDES_START ((unsigned int) 0x1 << 0) // (TDES) Starts Processing -#define AT91C_TDES_SWRST ((unsigned int) 0x1 << 8) // (TDES) Software Reset -// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- -#define AT91C_TDES_CIPHER ((unsigned int) 0x1 << 0) // (TDES) Processing Mode -#define AT91C_TDES_TDESMOD ((unsigned int) 0x1 << 1) // (TDES) Single or Triple DES Mode -#define AT91C_TDES_KEYMOD ((unsigned int) 0x1 << 4) // (TDES) Key Mode -#define AT91C_TDES_SMOD ((unsigned int) 0x3 << 8) // (TDES) Start Mode -#define AT91C_TDES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. -#define AT91C_TDES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). -#define AT91C_TDES_SMOD_PDC ((unsigned int) 0x2 << 8) // (TDES) PDC Mode (cf datasheet). -#define AT91C_TDES_OPMOD ((unsigned int) 0x3 << 12) // (TDES) Operation Mode -#define AT91C_TDES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode. -#define AT91C_TDES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode. -#define AT91C_TDES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode. -#define AT91C_TDES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode. -#define AT91C_TDES_LOD ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode -#define AT91C_TDES_CFBS ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size -#define AT91C_TDES_CFBS_64_BIT ((unsigned int) 0x0 << 16) // (TDES) 64-bit. -#define AT91C_TDES_CFBS_32_BIT ((unsigned int) 0x1 << 16) // (TDES) 32-bit. -#define AT91C_TDES_CFBS_16_BIT ((unsigned int) 0x2 << 16) // (TDES) 16-bit. -#define AT91C_TDES_CFBS_8_BIT ((unsigned int) 0x3 << 16) // (TDES) 8-bit. -// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- -#define AT91C_TDES_DATRDY ((unsigned int) 0x1 << 0) // (TDES) DATRDY -#define AT91C_TDES_ENDRX ((unsigned int) 0x1 << 1) // (TDES) PDC Read Buffer End -#define AT91C_TDES_ENDTX ((unsigned int) 0x1 << 2) // (TDES) PDC Write Buffer End -#define AT91C_TDES_RXBUFF ((unsigned int) 0x1 << 3) // (TDES) PDC Read Buffer Full -#define AT91C_TDES_TXBUFE ((unsigned int) 0x1 << 4) // (TDES) PDC Write Buffer Empty -#define AT91C_TDES_URAD ((unsigned int) 0x1 << 8) // (TDES) Unspecified Register Access Detection -// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- -// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- -// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- -#define AT91C_TDES_URAT ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status -#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode. -#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing. -#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing. -#define AT91C_TDES_URAT_WO_REG_READ ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access. - -// ***************************************************************************** -// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 -// ***************************************************************************** -// ========== Register definition for SYS peripheral ========== -// ========== Register definition for AIC peripheral ========== -#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register -#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register -#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register -#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) -#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register -#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register -#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register -#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register -#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register -#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register -#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register -#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register -#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register -#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register -#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register -#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register -#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register -#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register -// ========== Register definition for PDC_DBGU peripheral ========== -#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register -#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register -#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register -#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register -#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register -#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register -#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register -#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register -#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register -#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register -// ========== Register definition for DBGU peripheral ========== -#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register -#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register -#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register -#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register -#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register -#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register -#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register -#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register -#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register -#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register -#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register -#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register -// ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register -#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register -#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register -#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register -#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register -#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register -#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register -#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register -#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register -#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register -#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register -#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register -#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register -// ========== Register definition for PIOB peripheral ========== -#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register -#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register -#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register -#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register -#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register -#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register -#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register -#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register -#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register -#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register -#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register -#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register -#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register -#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register -#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register -#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register -#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr -#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register -#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register -#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register -#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register -#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register -#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register -#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register -#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register -#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register -#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register -#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register -#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register -// ========== Register definition for CKGR peripheral ========== -#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register -#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register -#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register -// ========== Register definition for PMC peripheral ========== -#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register -#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register -#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register -#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register -#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register -#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register -#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register -#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register -#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register -#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register -#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register -#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register -#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register -#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register -#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register -// ========== Register definition for RSTC peripheral ========== -#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register -#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register -#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register -// ========== Register definition for RTTC peripheral ========== -#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register -#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register -#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register -#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register -// ========== Register definition for PITC peripheral ========== -#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register -#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register -#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register -#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register -// ========== Register definition for WDTC peripheral ========== -#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register -#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register -#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register -// ========== Register definition for VREG peripheral ========== -#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register -// ========== Register definition for MC peripheral ========== -#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register -#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register -#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register -#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register -#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register -#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register -// ========== Register definition for PDC_SPI1 peripheral ========== -#define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register -#define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register -#define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register -#define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register -#define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register -#define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register -#define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register -#define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register -#define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register -#define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register -// ========== Register definition for SPI1 peripheral ========== -#define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register -#define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register -#define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register -#define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register -#define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register -#define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register -#define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register -#define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register -#define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register -// ========== Register definition for PDC_SPI0 peripheral ========== -#define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register -#define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register -#define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register -#define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register -#define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register -#define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register -#define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register -#define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register -#define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register -#define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register -// ========== Register definition for SPI0 peripheral ========== -#define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register -#define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register -#define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register -#define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register -#define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register -#define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register -#define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register -#define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register -#define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register -// ========== Register definition for PDC_US1 peripheral ========== -#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register -#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register -#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register -#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register -#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register -#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register -#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register -#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register -#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register -#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register -// ========== Register definition for US1 peripheral ========== -#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register -#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register -#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register -#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register -#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register -#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register -#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register -#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register -#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register -#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register -#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register -#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register -#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register -#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register -// ========== Register definition for PDC_US0 peripheral ========== -#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register -#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register -#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register -#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register -#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register -#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register -#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register -#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register -#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register -#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register -// ========== Register definition for US0 peripheral ========== -#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register -#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register -#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register -#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register -#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register -#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register -#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register -#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register -#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register -#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register -#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register -#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register -#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register -#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register -// ========== Register definition for PDC_SSC peripheral ========== -#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register -#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register -#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register -#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register -#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register -#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register -#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register -#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register -#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register -#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register -// ========== Register definition for SSC peripheral ========== -#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register -#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register -#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register -#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register -#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register -#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister -#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register -#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register -#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register -#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register -#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register -#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register -#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register -#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register -// ========== Register definition for TWI peripheral ========== -#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register -#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register -#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register -#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register -#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register -#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register -#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register -#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register -#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register -#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register -// ========== Register definition for PWMC_CH3 peripheral ========== -#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register -#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved -#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register -#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register -#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register -#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register -// ========== Register definition for PWMC_CH2 peripheral ========== -#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved -#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register -#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register -#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register -#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register -#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH1 peripheral ========== -#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved -#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register -#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register -#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register -#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register -#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register -// ========== Register definition for PWMC_CH0 peripheral ========== -#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved -#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register -#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register -#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register -#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register -#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register -// ========== Register definition for PWMC peripheral ========== -#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register -#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register -#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register -#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register -#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register -#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register -#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register -#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register -#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register -// ========== Register definition for UDP peripheral ========== -#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register -#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register -#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register -#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register -#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register -#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register -#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register -#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register -#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register -#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register -#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register -#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register -// ========== Register definition for TC0 peripheral ========== -#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register -#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C -#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B -#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register -#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register -#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A -#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register -#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value -#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register -// ========== Register definition for TC1 peripheral ========== -#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B -#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register -#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register -#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register -#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register -#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A -#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C -#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register -#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value -// ========== Register definition for TC2 peripheral ========== -#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register -#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value -#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A -#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B -#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register -#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register -#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C -#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register -#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register -// ========== Register definition for TCB peripheral ========== -#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register -#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register -// ========== Register definition for CAN_MB0 peripheral ========== -#define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register -#define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register -#define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register -#define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register -#define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register -#define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register -#define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register -#define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register -// ========== Register definition for CAN_MB1 peripheral ========== -#define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register -#define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register -#define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register -#define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register -#define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register -#define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register -#define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register -#define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register -// ========== Register definition for CAN_MB2 peripheral ========== -#define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register -#define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register -#define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register -#define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register -#define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register -#define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register -#define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register -#define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register -// ========== Register definition for CAN_MB3 peripheral ========== -#define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register -#define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register -#define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register -#define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register -#define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register -#define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register -#define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register -#define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register -// ========== Register definition for CAN_MB4 peripheral ========== -#define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register -#define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register -#define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register -#define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register -#define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register -#define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register -#define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register -#define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register -// ========== Register definition for CAN_MB5 peripheral ========== -#define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register -#define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register -#define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register -#define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register -#define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register -#define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register -#define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register -#define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register -// ========== Register definition for CAN_MB6 peripheral ========== -#define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register -#define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register -#define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register -#define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register -#define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register -#define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register -#define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register -#define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register -// ========== Register definition for CAN_MB7 peripheral ========== -#define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register -#define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register -#define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register -#define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register -#define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register -#define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register -#define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register -#define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register -// ========== Register definition for CAN peripheral ========== -#define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register -#define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register -#define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register -#define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register -#define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register -#define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register -#define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register -#define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register -#define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register -#define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register -#define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register -#define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register -// ========== Register definition for EMAC peripheral ========== -#define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register -#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes -#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes -#define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register -#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register -#define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register -#define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register -#define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register -#define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register -#define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register -#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes -#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register -#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes -#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register -#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register -#define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register -#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register -#define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register -#define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] -#define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer -#define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register -#define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register -#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes -#define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register -#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register -#define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register -#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer -#define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register -#define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register -#define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32] -#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register -#define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register -#define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register -#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register -#define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register -#define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register -#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register -#define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register -#define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register -#define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register -#define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register -#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes -#define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register -#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register -#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes -#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register -#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes -#define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register -#define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register -// ========== Register definition for PDC_ADC peripheral ========== -#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register -#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register -#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register -#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register -#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register -#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register -#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register -#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register -#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register -#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register -// ========== Register definition for ADC peripheral ========== -#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 -#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 -#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 -#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 -#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register -#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register -#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 -#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 -#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register -#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register -#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register -#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 -#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 -#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register -#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register -#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register -#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register -#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register -// ========== Register definition for PDC_AES peripheral ========== -#define AT91C_AES_TPR ((AT91_REG *) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register -#define AT91C_AES_PTCR ((AT91_REG *) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register -#define AT91C_AES_RNPR ((AT91_REG *) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register -#define AT91C_AES_TNCR ((AT91_REG *) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register -#define AT91C_AES_TCR ((AT91_REG *) 0xFFFA410C) // (PDC_AES) Transmit Counter Register -#define AT91C_AES_RCR ((AT91_REG *) 0xFFFA4104) // (PDC_AES) Receive Counter Register -#define AT91C_AES_RNCR ((AT91_REG *) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register -#define AT91C_AES_TNPR ((AT91_REG *) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register -#define AT91C_AES_RPR ((AT91_REG *) 0xFFFA4100) // (PDC_AES) Receive Pointer Register -#define AT91C_AES_PTSR ((AT91_REG *) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register -// ========== Register definition for AES peripheral ========== -#define AT91C_AES_IVxR ((AT91_REG *) 0xFFFA4060) // (AES) Initialization Vector x Register -#define AT91C_AES_MR ((AT91_REG *) 0xFFFA4004) // (AES) Mode Register -#define AT91C_AES_VR ((AT91_REG *) 0xFFFA40FC) // (AES) AES Version Register -#define AT91C_AES_ODATAxR ((AT91_REG *) 0xFFFA4050) // (AES) Output Data x Register -#define AT91C_AES_IDATAxR ((AT91_REG *) 0xFFFA4040) // (AES) Input Data x Register -#define AT91C_AES_CR ((AT91_REG *) 0xFFFA4000) // (AES) Control Register -#define AT91C_AES_IDR ((AT91_REG *) 0xFFFA4014) // (AES) Interrupt Disable Register -#define AT91C_AES_IMR ((AT91_REG *) 0xFFFA4018) // (AES) Interrupt Mask Register -#define AT91C_AES_IER ((AT91_REG *) 0xFFFA4010) // (AES) Interrupt Enable Register -#define AT91C_AES_KEYWxR ((AT91_REG *) 0xFFFA4020) // (AES) Key Word x Register -#define AT91C_AES_ISR ((AT91_REG *) 0xFFFA401C) // (AES) Interrupt Status Register -// ========== Register definition for PDC_TDES peripheral ========== -#define AT91C_TDES_RNCR ((AT91_REG *) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register -#define AT91C_TDES_TCR ((AT91_REG *) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register -#define AT91C_TDES_RCR ((AT91_REG *) 0xFFFA8104) // (PDC_TDES) Receive Counter Register -#define AT91C_TDES_TNPR ((AT91_REG *) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register -#define AT91C_TDES_RNPR ((AT91_REG *) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register -#define AT91C_TDES_RPR ((AT91_REG *) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register -#define AT91C_TDES_TNCR ((AT91_REG *) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register -#define AT91C_TDES_TPR ((AT91_REG *) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register -#define AT91C_TDES_PTSR ((AT91_REG *) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register -#define AT91C_TDES_PTCR ((AT91_REG *) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register -// ========== Register definition for TDES peripheral ========== -#define AT91C_TDES_KEY2WxR ((AT91_REG *) 0xFFFA8028) // (TDES) Key 2 Word x Register -#define AT91C_TDES_KEY3WxR ((AT91_REG *) 0xFFFA8030) // (TDES) Key 3 Word x Register -#define AT91C_TDES_IDR ((AT91_REG *) 0xFFFA8014) // (TDES) Interrupt Disable Register -#define AT91C_TDES_VR ((AT91_REG *) 0xFFFA80FC) // (TDES) TDES Version Register -#define AT91C_TDES_IVxR ((AT91_REG *) 0xFFFA8060) // (TDES) Initialization Vector x Register -#define AT91C_TDES_ODATAxR ((AT91_REG *) 0xFFFA8050) // (TDES) Output Data x Register -#define AT91C_TDES_IMR ((AT91_REG *) 0xFFFA8018) // (TDES) Interrupt Mask Register -#define AT91C_TDES_MR ((AT91_REG *) 0xFFFA8004) // (TDES) Mode Register -#define AT91C_TDES_CR ((AT91_REG *) 0xFFFA8000) // (TDES) Control Register -#define AT91C_TDES_IER ((AT91_REG *) 0xFFFA8010) // (TDES) Interrupt Enable Register -#define AT91C_TDES_ISR ((AT91_REG *) 0xFFFA801C) // (TDES) Interrupt Status Register -#define AT91C_TDES_IDATAxR ((AT91_REG *) 0xFFFA8040) // (TDES) Input Data x Register -#define AT91C_TDES_KEY1WxR ((AT91_REG *) 0xFFFA8020) // (TDES) Key 1 Word x Register - -// ***************************************************************************** -// PIO DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 -#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data -#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 -#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data -#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 -#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data -#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 -#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock -#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 -#define AT91C_PA12_NPCS00 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 -#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 -#define AT91C_PA13_NPCS01 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 -#define AT91C_PA14_NPCS02 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1 -#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 -#define AT91C_PA15_NPCS03 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input -#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 -#define AT91C_PA16_MISO0 ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave -#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 -#define AT91C_PA17_MOSI0 ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave -#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 -#define AT91C_PA18_SPCK0 ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock -#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 -#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive -#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 -#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock -#define AT91C_PA2_NPCS11 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 -#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit -#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 -#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync -#define AT91C_PA21_NPCS10 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 -#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 -#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock -#define AT91C_PA22_SPCK1 ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock -#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 -#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data -#define AT91C_PA23_MOSI1 ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave -#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 -#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data -#define AT91C_PA24_MISO1 ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave -#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 -#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock -#define AT91C_PA25_NPCS11 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 -#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync -#define AT91C_PA26_NPCS12 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 -#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data -#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3 -#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 -#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data -#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 -#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input -#define AT91C_PA29_NPCS13 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 -#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send -#define AT91C_PA3_NPCS12 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 -#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0 -#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 -#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send -#define AT91C_PA4_NPCS13 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 -#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data -#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 -#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data -#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 -#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock -#define AT91C_PA7_NPCS01 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 -#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send -#define AT91C_PA8_NPCS02 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 -#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send -#define AT91C_PA9_NPCS03 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0 -#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock -#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1 -#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable -#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10 -#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 -#define AT91C_PB10_NPCS11 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11 -#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 -#define AT91C_PB11_NPCS12 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12 -#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error -#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input -#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13 -#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 -#define AT91C_PB13_NPCS01 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14 -#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 -#define AT91C_PB14_NPCS02 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15 -#define AT91C_PB15_ERXDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid -#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16 -#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected -#define AT91C_PB16_NPCS13 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17 -#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock -#define AT91C_PB17_NPCS03 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18 -#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec -#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger -#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19 -#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0 -#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input -#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2 -#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 -#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20 -#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1 -#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21 -#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2 -#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22 -#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3 -#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23 -#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A -#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect -#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24 -#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B -#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready -#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25 -#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A -#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready -#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26 -#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B -#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator -#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27 -#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A -#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0 -#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28 -#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B -#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1 -#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29 -#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1 -#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2 -#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3 -#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 -#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30 -#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2 -#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3 -#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4 -#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid -#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5 -#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 -#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6 -#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 -#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7 -#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error -#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8 -#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock -#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9 -#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output - -// ***************************************************************************** -// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) -#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral -#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A -#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B -#define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0 -#define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1 -#define AT91C_ID_US0 ((unsigned int) 6) // USART 0 -#define AT91C_ID_US1 ((unsigned int) 7) // USART 1 -#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller -#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface -#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller -#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port -#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0 -#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1 -#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2 -#define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller -#define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC -#define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter -#define AT91C_ID_AES ((unsigned int) 18) // Advanced Encryption Standard 128-bit -#define AT91C_ID_TDES ((unsigned int) 19) // Triple Data Encryption Standard -#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved -#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved -#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved -#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved -#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved -#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved -#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved -#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved -#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved -#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved -#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0) -#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1) - -// ***************************************************************************** -// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address -#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address -#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address -#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address -#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address -#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address -#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address -#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address -#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address -#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address -#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address -#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address -#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address -#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address -#define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address -#define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address -#define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address -#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address -#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address -#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address -#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address -#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address -#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address -#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address -#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address -#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address -#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address -#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address -#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address -#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address -#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address -#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address -#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address -#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address -#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address -#define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address -#define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address -#define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address -#define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address -#define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address -#define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address -#define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address -#define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address -#define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address -#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address -#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address -#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address -#define AT91C_BASE_PDC_AES ((AT91PS_PDC) 0xFFFA4100) // (PDC_AES) Base Address -#define AT91C_BASE_AES ((AT91PS_AES) 0xFFFA4000) // (AES) Base Address -#define AT91C_BASE_PDC_TDES ((AT91PS_PDC) 0xFFFA8100) // (PDC_TDES) Base Address -#define AT91C_BASE_TDES ((AT91PS_TDES) 0xFFFA8000) // (TDES) Base Address - -// ***************************************************************************** -// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address -#define AT91C_ISRAM_SIZE ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte) -#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address -#define AT91C_IFLASH_SIZE ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte) - -#define AT91F_AIC_ConfigureIt( irq_id, priority, src_type, newHandler ) \ -{ \ - unsigned int mask ; \ - \ - mask = 0x1 << irq_id; \ - /* Disable the interrupt on the interrupt controller */ \ - AT91C_BASE_AIC->AIC_IDCR = mask ; \ - /* Save the interrupt handler routine pointer and the interrupt priority */ \ - AT91C_BASE_AIC->AIC_SVR[irq_id] = (unsigned int) newHandler ; \ - /* Store the Source Mode Register */ \ - AT91C_BASE_AIC->AIC_SMR[irq_id] = src_type | priority ; \ - /* Clear the interrupt on the interrupt controller */ \ - AT91C_BASE_AIC->AIC_ICCR = mask ; \ -} - - -#endif diff --git a/Source/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h b/Source/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h deleted file mode 100644 index 8ea721e28..000000000 --- a/Source/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h +++ /dev/null @@ -1,4698 +0,0 @@ -// - ---------------------------------------------------------------------------- -// - ATMEL Microcontroller Software Support - ROUSSET - -// - ---------------------------------------------------------------------------- -// - DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -// - IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -// - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -// - DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -// - INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// - LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -// - OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// - LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// - NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -// - EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// - ---------------------------------------------------------------------------- -// - File Name : AT91SAM7X256.h -// - Object : AT91SAM7X256 definitions -// - Generated : AT91 SW Application Group 05/20/2005 (16:22:29) -// - -// - CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005// -// - CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// -// - CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// -// - CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// -// - CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// -// - CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// -// - CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// -// - CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// -// - CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// -// - CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// -// - CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// -// - CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// -// - CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// -// - CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// -// - CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// -// - CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// -// - CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// -// - CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// -// - CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// -// - CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// -// - CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// -// - CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// -// - CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// -// - CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// -// - CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// -// - ---------------------------------------------------------------------------- - -#ifndef AT91SAM7X256_H -#define AT91SAM7X256_H - -typedef volatile unsigned int AT91_REG;// Hardware register definition - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Peripherals -// ***************************************************************************** -typedef struct _AT91S_SYS { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register - AT91_REG Reserved2[45]; // - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved3[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved4[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register - AT91_REG Reserved5[54]; // - AT91_REG PIOA_PER; // PIO Enable Register - AT91_REG PIOA_PDR; // PIO Disable Register - AT91_REG PIOA_PSR; // PIO Status Register - AT91_REG Reserved6[1]; // - AT91_REG PIOA_OER; // Output Enable Register - AT91_REG PIOA_ODR; // Output Disable Registerr - AT91_REG PIOA_OSR; // Output Status Register - AT91_REG Reserved7[1]; // - AT91_REG PIOA_IFER; // Input Filter Enable Register - AT91_REG PIOA_IFDR; // Input Filter Disable Register - AT91_REG PIOA_IFSR; // Input Filter Status Register - AT91_REG Reserved8[1]; // - AT91_REG PIOA_SODR; // Set Output Data Register - AT91_REG PIOA_CODR; // Clear Output Data Register - AT91_REG PIOA_ODSR; // Output Data Status Register - AT91_REG PIOA_PDSR; // Pin Data Status Register - AT91_REG PIOA_IER; // Interrupt Enable Register - AT91_REG PIOA_IDR; // Interrupt Disable Register - AT91_REG PIOA_IMR; // Interrupt Mask Register - AT91_REG PIOA_ISR; // Interrupt Status Register - AT91_REG PIOA_MDER; // Multi-driver Enable Register - AT91_REG PIOA_MDDR; // Multi-driver Disable Register - AT91_REG PIOA_MDSR; // Multi-driver Status Register - AT91_REG Reserved9[1]; // - AT91_REG PIOA_PPUDR; // Pull-up Disable Register - AT91_REG PIOA_PPUER; // Pull-up Enable Register - AT91_REG PIOA_PPUSR; // Pull-up Status Register - AT91_REG Reserved10[1]; // - AT91_REG PIOA_ASR; // Select A Register - AT91_REG PIOA_BSR; // Select B Register - AT91_REG PIOA_ABSR; // AB Select Status Register - AT91_REG Reserved11[9]; // - AT91_REG PIOA_OWER; // Output Write Enable Register - AT91_REG PIOA_OWDR; // Output Write Disable Register - AT91_REG PIOA_OWSR; // Output Write Status Register - AT91_REG Reserved12[85]; // - AT91_REG PIOB_PER; // PIO Enable Register - AT91_REG PIOB_PDR; // PIO Disable Register - AT91_REG PIOB_PSR; // PIO Status Register - AT91_REG Reserved13[1]; // - AT91_REG PIOB_OER; // Output Enable Register - AT91_REG PIOB_ODR; // Output Disable Registerr - AT91_REG PIOB_OSR; // Output Status Register - AT91_REG Reserved14[1]; // - AT91_REG PIOB_IFER; // Input Filter Enable Register - AT91_REG PIOB_IFDR; // Input Filter Disable Register - AT91_REG PIOB_IFSR; // Input Filter Status Register - AT91_REG Reserved15[1]; // - AT91_REG PIOB_SODR; // Set Output Data Register - AT91_REG PIOB_CODR; // Clear Output Data Register - AT91_REG PIOB_ODSR; // Output Data Status Register - AT91_REG PIOB_PDSR; // Pin Data Status Register - AT91_REG PIOB_IER; // Interrupt Enable Register - AT91_REG PIOB_IDR; // Interrupt Disable Register - AT91_REG PIOB_IMR; // Interrupt Mask Register - AT91_REG PIOB_ISR; // Interrupt Status Register - AT91_REG PIOB_MDER; // Multi-driver Enable Register - AT91_REG PIOB_MDDR; // Multi-driver Disable Register - AT91_REG PIOB_MDSR; // Multi-driver Status Register - AT91_REG Reserved16[1]; // - AT91_REG PIOB_PPUDR; // Pull-up Disable Register - AT91_REG PIOB_PPUER; // Pull-up Enable Register - AT91_REG PIOB_PPUSR; // Pull-up Status Register - AT91_REG Reserved17[1]; // - AT91_REG PIOB_ASR; // Select A Register - AT91_REG PIOB_BSR; // Select B Register - AT91_REG PIOB_ABSR; // AB Select Status Register - AT91_REG Reserved18[9]; // - AT91_REG PIOB_OWER; // Output Write Enable Register - AT91_REG PIOB_OWDR; // Output Write Disable Register - AT91_REG PIOB_OWSR; // Output Write Status Register - AT91_REG Reserved19[341]; // - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved20[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved21[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved22[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved23[3]; // - AT91_REG PMC_PCKR[4]; // Programmable Clock Register - AT91_REG Reserved24[4]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register - AT91_REG Reserved25[36]; // - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register - AT91_REG Reserved26[5]; // - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register - AT91_REG Reserved27[5]; // - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_SYS, *AT91PS_SYS; - - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// ***************************************************************************** -typedef struct _AT91S_AIC { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register -} AT91S_AIC, *AT91PS_AIC; - -// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level -#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level -#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level -#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type -#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive -#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered -#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered -#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered -// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status -#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status -// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode -#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Peripheral DMA Controller -// ***************************************************************************** -typedef struct _AT91S_PDC { - AT91_REG PDC_RPR; // Receive Pointer Register - AT91_REG PDC_RCR; // Receive Counter Register - AT91_REG PDC_TPR; // Transmit Pointer Register - AT91_REG PDC_TCR; // Transmit Counter Register - AT91_REG PDC_RNPR; // Receive Next Pointer Register - AT91_REG PDC_RNCR; // Receive Next Counter Register - AT91_REG PDC_TNPR; // Transmit Next Pointer Register - AT91_REG PDC_TNCR; // Transmit Next Counter Register - AT91_REG PDC_PTCR; // PDC Transfer Control Register - AT91_REG PDC_PTSR; // PDC Transfer Status Register -} AT91S_PDC, *AT91PS_PDC; - -// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable -#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable -#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable -#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable -// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Debug Unit -// ***************************************************************************** -typedef struct _AT91S_DBGU { - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved0[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved1[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register -} AT91S_DBGU, *AT91PS_DBGU; - -// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver -#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter -#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable -#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable -#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable -#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable -#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits -// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type -#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity -#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity -#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space) -#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark) -#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity -#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode -#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode -#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt -#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt -#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt -#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt -#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt -#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt -#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt -#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt -#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt -#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt -#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt -#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt -// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// ***************************************************************************** -typedef struct _AT91S_PIO { - AT91_REG PIO_PER; // PIO Enable Register - AT91_REG PIO_PDR; // PIO Disable Register - AT91_REG PIO_PSR; // PIO Status Register - AT91_REG Reserved0[1]; // - AT91_REG PIO_OER; // Output Enable Register - AT91_REG PIO_ODR; // Output Disable Registerr - AT91_REG PIO_OSR; // Output Status Register - AT91_REG Reserved1[1]; // - AT91_REG PIO_IFER; // Input Filter Enable Register - AT91_REG PIO_IFDR; // Input Filter Disable Register - AT91_REG PIO_IFSR; // Input Filter Status Register - AT91_REG Reserved2[1]; // - AT91_REG PIO_SODR; // Set Output Data Register - AT91_REG PIO_CODR; // Clear Output Data Register - AT91_REG PIO_ODSR; // Output Data Status Register - AT91_REG PIO_PDSR; // Pin Data Status Register - AT91_REG PIO_IER; // Interrupt Enable Register - AT91_REG PIO_IDR; // Interrupt Disable Register - AT91_REG PIO_IMR; // Interrupt Mask Register - AT91_REG PIO_ISR; // Interrupt Status Register - AT91_REG PIO_MDER; // Multi-driver Enable Register - AT91_REG PIO_MDDR; // Multi-driver Disable Register - AT91_REG PIO_MDSR; // Multi-driver Status Register - AT91_REG Reserved3[1]; // - AT91_REG PIO_PPUDR; // Pull-up Disable Register - AT91_REG PIO_PPUER; // Pull-up Enable Register - AT91_REG PIO_PPUSR; // Pull-up Status Register - AT91_REG Reserved4[1]; // - AT91_REG PIO_ASR; // Select A Register - AT91_REG PIO_BSR; // Select B Register - AT91_REG PIO_ABSR; // AB Select Status Register - AT91_REG Reserved5[9]; // - AT91_REG PIO_OWER; // Output Write Enable Register - AT91_REG PIO_OWDR; // Output Write Disable Register - AT91_REG PIO_OWSR; // Output Write Status Register -} AT91S_PIO, *AT91PS_PIO; - - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Clock Generator Controler -// ***************************************************************************** -typedef struct _AT91S_CKGR { - AT91_REG CKGR_MOR; // Main Oscillator Register - AT91_REG CKGR_MCFR; // Main Clock Frequency Register - AT91_REG Reserved0[1]; // - AT91_REG CKGR_PLLR; // PLL Register -} AT91S_CKGR, *AT91PS_CKGR; - -// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable -#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass -#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time -// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency -#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready -// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- -#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter -#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range -#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier -#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks -#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output -#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 -#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Power Management Controler -// ***************************************************************************** -typedef struct _AT91S_PMC { - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved0[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved1[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved2[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved3[3]; // - AT91_REG PMC_PCKR[4]; // Programmable Clock Register - AT91_REG Reserved4[4]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register -} AT91S_PMC, *AT91PS_PMC; - -// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock -#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock -#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output -// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- -// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- -// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- -// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection -#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected -#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected -#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected -#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler -#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock -#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 -#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 -#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 -#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 -#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 -#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 -// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask -#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask -#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask -// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Reset Controller Interface -// ***************************************************************************** -typedef struct _AT91S_RSTC { - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register -} AT91S_RSTC, *AT91PS_RSTC; - -// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- -#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset -#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset -#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset -#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password -// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- -#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status -#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status -#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type -#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. -#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. -#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low. -#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured. -#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level -#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress. -// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- -#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable -#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable -#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable -#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_RTTC { - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register -} AT91S_RTTC, *AT91PS_RTTC; - -// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- -#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value -#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable -#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable -#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart -// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- -#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value -// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- -#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value -// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- -#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status -#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_PITC { - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register -} AT91S_PITC, *AT91PS_PITC; - -// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- -#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value -#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled -#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable -// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- -#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status -// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- -#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value -#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter -// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_WDTC { - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register -} AT91S_WDTC, *AT91PS_WDTC; - -// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- -#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart -#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password -// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- -#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable -#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable -#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable -#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value -#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt -#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt -// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- -#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow -#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface -// ***************************************************************************** -typedef struct _AT91S_VREG { - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_VREG, *AT91PS_VREG; - -// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- -#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Memory Controller Interface -// ***************************************************************************** -typedef struct _AT91S_MC { - AT91_REG MC_RCR; // MC Remap Control Register - AT91_REG MC_ASR; // MC Abort Status Register - AT91_REG MC_AASR; // MC Abort Address Status Register - AT91_REG Reserved0[21]; // - AT91_REG MC_FMR; // MC Flash Mode Register - AT91_REG MC_FCR; // MC Flash Command Register - AT91_REG MC_FSR; // MC Flash Status Register -} AT91S_MC, *AT91PS_MC; - -// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit -// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status -#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status -#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status -#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte -#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word -#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word -#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status -#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read -#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write -#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch -#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source -#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source -#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source -#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source -// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- -#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready -#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error -#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error -#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming -#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State -#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations -#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations -#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations -#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations -#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number -// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- -#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command -#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN. -#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. -#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. -#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits. -#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits. -#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit. -#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number -#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key -// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- -#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status -#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status -#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status -#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status -#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status -#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status -#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status -#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status -#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status -#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status -#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status -#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status -#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status -#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status -#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status -#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status -#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status -#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status -#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status -#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status -#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status -#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status -#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Serial Parallel Interface -// ***************************************************************************** -typedef struct _AT91S_SPI { - AT91_REG SPI_CR; // Control Register - AT91_REG SPI_MR; // Mode Register - AT91_REG SPI_RDR; // Receive Data Register - AT91_REG SPI_TDR; // Transmit Data Register - AT91_REG SPI_SR; // Status Register - AT91_REG SPI_IER; // Interrupt Enable Register - AT91_REG SPI_IDR; // Interrupt Disable Register - AT91_REG SPI_IMR; // Interrupt Mask Register - AT91_REG Reserved0[4]; // - AT91_REG SPI_CSR[4]; // Chip Select Register - AT91_REG Reserved1[48]; // - AT91_REG SPI_RPR; // Receive Pointer Register - AT91_REG SPI_RCR; // Receive Counter Register - AT91_REG SPI_TPR; // Transmit Pointer Register - AT91_REG SPI_TCR; // Transmit Counter Register - AT91_REG SPI_RNPR; // Receive Next Pointer Register - AT91_REG SPI_RNCR; // Receive Next Counter Register - AT91_REG SPI_TNPR; // Transmit Next Pointer Register - AT91_REG SPI_TNCR; // Transmit Next Counter Register - AT91_REG SPI_PTCR; // PDC Transfer Control Register - AT91_REG SPI_PTSR; // PDC Transfer Status Register -} AT91S_SPI, *AT91PS_SPI; - -// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable -#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable -#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset -#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer -// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode -#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select -#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select -#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select -#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode -#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection -#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection -#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection -#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select -#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects -// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data -#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data -#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full -#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty -#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error -#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status -#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer -#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer -#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt -#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt -#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt -#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt -#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status -// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity -#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase -#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer -#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer -#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer -#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer -#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer -#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer -#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer -#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer -#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer -#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer -#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer -#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK -#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Usart -// ***************************************************************************** -typedef struct _AT91S_USART { - AT91_REG US_CR; // Control Register - AT91_REG US_MR; // Mode Register - AT91_REG US_IER; // Interrupt Enable Register - AT91_REG US_IDR; // Interrupt Disable Register - AT91_REG US_IMR; // Interrupt Mask Register - AT91_REG US_CSR; // Channel Status Register - AT91_REG US_RHR; // Receiver Holding Register - AT91_REG US_THR; // Transmitter Holding Register - AT91_REG US_BRGR; // Baud Rate Generator Register - AT91_REG US_RTOR; // Receiver Time-out Register - AT91_REG US_TTGR; // Transmitter Time-guard Register - AT91_REG Reserved0[5]; // - AT91_REG US_FIDI; // FI_DI_Ratio Register - AT91_REG US_NER; // Nb Errors Register - AT91_REG Reserved1[1]; // - AT91_REG US_IF; // IRDA_FILTER Register - AT91_REG Reserved2[44]; // - AT91_REG US_RPR; // Receive Pointer Register - AT91_REG US_RCR; // Receive Counter Register - AT91_REG US_TPR; // Transmit Pointer Register - AT91_REG US_TCR; // Transmit Counter Register - AT91_REG US_RNPR; // Receive Next Pointer Register - AT91_REG US_RNCR; // Receive Next Counter Register - AT91_REG US_TNPR; // Transmit Next Pointer Register - AT91_REG US_TNCR; // Transmit Next Counter Register - AT91_REG US_PTCR; // PDC Transfer Control Register - AT91_REG US_PTSR; // PDC Transfer Status Register -} AT91S_USART, *AT91PS_USART; - -// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break -#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break -#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out -#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address -#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations -#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge -#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out -#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable -#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable -#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable -#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable -// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode -#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal -#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 -#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking -#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem -#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0 -#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1 -#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA -#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking -#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock -#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 -#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) -#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) -#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits -#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits -#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits -#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits -#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select -#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits -#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit -#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits -#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order -#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length -#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select -#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode -#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge -#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK -#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions -#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter -// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break -#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out -#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached -#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge -#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag -#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag -#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag -#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag -// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input -#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input -#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input -#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// ***************************************************************************** -typedef struct _AT91S_SSC { - AT91_REG SSC_CR; // Control Register - AT91_REG SSC_CMR; // Clock Mode Register - AT91_REG Reserved0[2]; // - AT91_REG SSC_RCMR; // Receive Clock ModeRegister - AT91_REG SSC_RFMR; // Receive Frame Mode Register - AT91_REG SSC_TCMR; // Transmit Clock Mode Register - AT91_REG SSC_TFMR; // Transmit Frame Mode Register - AT91_REG SSC_RHR; // Receive Holding Register - AT91_REG SSC_THR; // Transmit Holding Register - AT91_REG Reserved1[2]; // - AT91_REG SSC_RSHR; // Receive Sync Holding Register - AT91_REG SSC_TSHR; // Transmit Sync Holding Register - AT91_REG Reserved2[2]; // - AT91_REG SSC_SR; // Status Register - AT91_REG SSC_IER; // Interrupt Enable Register - AT91_REG SSC_IDR; // Interrupt Disable Register - AT91_REG SSC_IMR; // Interrupt Mask Register - AT91_REG Reserved3[44]; // - AT91_REG SSC_RPR; // Receive Pointer Register - AT91_REG SSC_RCR; // Receive Counter Register - AT91_REG SSC_TPR; // Transmit Pointer Register - AT91_REG SSC_TCR; // Transmit Counter Register - AT91_REG SSC_RNPR; // Receive Next Pointer Register - AT91_REG SSC_RNCR; // Receive Next Counter Register - AT91_REG SSC_TNPR; // Transmit Next Pointer Register - AT91_REG SSC_TNCR; // Transmit Next Counter Register - AT91_REG SSC_PTCR; // PDC Transfer Control Register - AT91_REG SSC_PTSR; // PDC Transfer Status Register -} AT91S_SSC, *AT91PS_SSC; - -// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable -#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable -#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable -#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable -#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset -// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection -#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock -#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal -#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin -#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection -#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output -#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion -#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection -#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start -#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input -#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input -#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input -#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input -#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input -#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input -#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0 -#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay -#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection -// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length -#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode -#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First -#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame -#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length -#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection -#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection -// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value -#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable -// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready -#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty -#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission -#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty -#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready -#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun -#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception -#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full -#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync -#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync -#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable -#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable -// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Two-wire Interface -// ***************************************************************************** -typedef struct _AT91S_TWI { - AT91_REG TWI_CR; // Control Register - AT91_REG TWI_MMR; // Master Mode Register - AT91_REG Reserved0[1]; // - AT91_REG TWI_IADR; // Internal Address Register - AT91_REG TWI_CWGR; // Clock Waveform Generator Register - AT91_REG Reserved1[3]; // - AT91_REG TWI_SR; // Status Register - AT91_REG TWI_IER; // Interrupt Enable Register - AT91_REG TWI_IDR; // Interrupt Disable Register - AT91_REG TWI_IMR; // Interrupt Mask Register - AT91_REG TWI_RHR; // Receive Holding Register - AT91_REG TWI_THR; // Transmit Holding Register -} AT91S_TWI, *AT91PS_TWI; - -// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition -#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition -#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled -#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled -#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset -// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size -#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address -#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address -#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address -#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address -#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction -#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address -// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider -#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider -#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider -// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed -#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY -#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY -#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error -#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error -#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged -// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR PWMC Channel Interface -// ***************************************************************************** -typedef struct _AT91S_PWMC_CH { - AT91_REG PWMC_CMR; // Channel Mode Register - AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register - AT91_REG PWMC_CPRDR; // Channel Period Register - AT91_REG PWMC_CCNTR; // Channel Counter Register - AT91_REG PWMC_CUPDR; // Channel Update Register - AT91_REG PWMC_Reserved[3]; // Reserved -} AT91S_PWMC_CH, *AT91PS_PWMC_CH; - -// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- -#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx -#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) -#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment -#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity -#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period -// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- -#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle -// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- -#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period -// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- -#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter -// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- -#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface -// ***************************************************************************** -typedef struct _AT91S_PWMC { - AT91_REG PWMC_MR; // PWMC Mode Register - AT91_REG PWMC_ENA; // PWMC Enable Register - AT91_REG PWMC_DIS; // PWMC Disable Register - AT91_REG PWMC_SR; // PWMC Status Register - AT91_REG PWMC_IER; // PWMC Interrupt Enable Register - AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register - AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register - AT91_REG PWMC_ISR; // PWMC Interrupt Status Register - AT91_REG Reserved0[55]; // - AT91_REG PWMC_VR; // PWMC Version Register - AT91_REG Reserved1[64]; // - AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel -} AT91S_PWMC, *AT91PS_PWMC; - -// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- -#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor. -#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A -#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) -#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor. -#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B -#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) -// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- -#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0 -#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1 -#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2 -#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3 -// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- -// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- -// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- -// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- -// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- -// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Device Interface -// ***************************************************************************** -typedef struct _AT91S_UDP { - AT91_REG UDP_NUM; // Frame Number Register - AT91_REG UDP_GLBSTATE; // Global State Register - AT91_REG UDP_FADDR; // Function Address Register - AT91_REG Reserved0[1]; // - AT91_REG UDP_IER; // Interrupt Enable Register - AT91_REG UDP_IDR; // Interrupt Disable Register - AT91_REG UDP_IMR; // Interrupt Mask Register - AT91_REG UDP_ISR; // Interrupt Status Register - AT91_REG UDP_ICR; // Interrupt Clear Register - AT91_REG Reserved1[1]; // - AT91_REG UDP_RSTEP; // Reset Endpoint Register - AT91_REG Reserved2[1]; // - AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register - AT91_REG Reserved3[2]; // - AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register - AT91_REG Reserved4[3]; // - AT91_REG UDP_TXVC; // Transceiver Control Register -} AT91S_UDP, *AT91PS_UDP; - -// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats -#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error -#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK -// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable -#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured -#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume -#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host -#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable -// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value -#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable -// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt -#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt -#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt -#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt -#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt -#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt -#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt -#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt -#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt -// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt -// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 -#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 -#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 -#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3 -#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4 -#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5 -// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR -#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 -#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) -#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) -#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready -#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction -#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type -#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control -#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT -#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT -#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT -#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN -#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN -#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN -#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle -#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable -#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO -// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- -#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP) -#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// ***************************************************************************** -typedef struct _AT91S_TC { - AT91_REG TC_CCR; // Channel Control Register - AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) - AT91_REG Reserved0[2]; // - AT91_REG TC_CV; // Counter Value - AT91_REG TC_RA; // Register A - AT91_REG TC_RB; // Register B - AT91_REG TC_RC; // Register C - AT91_REG TC_SR; // Status Register - AT91_REG TC_IER; // Interrupt Enable Register - AT91_REG TC_IDR; // Interrupt Disable Register - AT91_REG TC_IMR; // Interrupt Mask Register -} AT91S_TC, *AT91PS_TC; - -// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command -#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command -#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command -// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection -#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK -#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0 -#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1 -#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2 -#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert -#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection -#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal -#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock -#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock -#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock -#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare -#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading -#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare -#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading -#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection -#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None -#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection -#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None -#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection -#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input -#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output -#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output -#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output -#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection -#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable -#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection -#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare -#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable -#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) -#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA -#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none -#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set -#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear -#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle -#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection -#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None -#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA -#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA -#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none -#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set -#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear -#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle -#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection -#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None -#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA -#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA -#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none -#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set -#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear -#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle -#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA -#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none -#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set -#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear -#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle -#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB -#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none -#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set -#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear -#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle -#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB -#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none -#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set -#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear -#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle -#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB -#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none -#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set -#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear -#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle -#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB -#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none -#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set -#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear -#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle -// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow -#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun -#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare -#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare -#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare -#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading -#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading -#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger -#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling -#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror -#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror -// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Interface -// ***************************************************************************** -typedef struct _AT91S_TCB { - AT91S_TC TCB_TC0; // TC Channel 0 - AT91_REG Reserved0[4]; // - AT91S_TC TCB_TC1; // TC Channel 1 - AT91_REG Reserved1[4]; // - AT91S_TC TCB_TC2; // TC Channel 2 - AT91_REG Reserved2[4]; // - AT91_REG TCB_BCR; // TC Block Control Register - AT91_REG TCB_BMR; // TC Block Mode Register -} AT91S_TCB, *AT91PS_TCB; - -// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command -// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection -#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 -#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 -#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection -#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 -#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 -#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection -#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 -#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface -// ***************************************************************************** -typedef struct _AT91S_CAN_MB { - AT91_REG CAN_MB_MMR; // MailBox Mode Register - AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register - AT91_REG CAN_MB_MID; // MailBox ID Register - AT91_REG CAN_MB_MFID; // MailBox Family ID Register - AT91_REG CAN_MB_MSR; // MailBox Status Register - AT91_REG CAN_MB_MDL; // MailBox Data Low Register - AT91_REG CAN_MB_MDH; // MailBox Data High Register - AT91_REG CAN_MB_MCR; // MailBox Control Register -} AT91S_CAN_MB, *AT91PS_CAN_MB; - -// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- -#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark -#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority -#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type -#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB) -// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- -#define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode -#define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode -#define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version -// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- -// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- -// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- -#define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value -#define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code -#define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request -#define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort -#define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready -#define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored -// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- -// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- -// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- -#define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox -#define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network Interface -// ***************************************************************************** -typedef struct _AT91S_CAN { - AT91_REG CAN_MR; // Mode Register - AT91_REG CAN_IER; // Interrupt Enable Register - AT91_REG CAN_IDR; // Interrupt Disable Register - AT91_REG CAN_IMR; // Interrupt Mask Register - AT91_REG CAN_SR; // Status Register - AT91_REG CAN_BR; // Baudrate Register - AT91_REG CAN_TIM; // Timer Register - AT91_REG CAN_TIMESTP; // Time Stamp Register - AT91_REG CAN_ECR; // Error Counter Register - AT91_REG CAN_TCR; // Transfer Command Register - AT91_REG CAN_ACR; // Abort Command Register - AT91_REG Reserved0[52]; // - AT91_REG CAN_VR; // Version Register - AT91_REG Reserved1[64]; // - AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0 - AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1 - AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2 - AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3 - AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4 - AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5 - AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6 - AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7 - AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8 - AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9 - AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10 - AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11 - AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12 - AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13 - AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14 - AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15 -} AT91S_CAN, *AT91PS_CAN; - -// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- -#define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable -#define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode -#define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode -#define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame -#define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame -#define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode -#define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze -#define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat -// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- -#define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag -#define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag -#define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag -#define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag -#define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag -#define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag -#define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag -#define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag -#define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag -#define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag -#define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag -#define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag -#define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag -#define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag -#define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag -#define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag -#define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag -#define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag -#define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag -#define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag -#define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag -#define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag -#define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag -#define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag -#define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error -#define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error -#define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error -#define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error -#define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error -// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- -// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- -// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- -#define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy -#define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy -#define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy -// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- -#define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment -#define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment -#define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment -#define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment -#define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler -#define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode -// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- -#define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field -// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- -// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- -#define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter -#define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter -// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- -#define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field -// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 -// ***************************************************************************** -typedef struct _AT91S_EMAC { - AT91_REG EMAC_NCR; // Network Control Register - AT91_REG EMAC_NCFGR; // Network Configuration Register - AT91_REG EMAC_NSR; // Network Status Register - AT91_REG Reserved0[2]; // - AT91_REG EMAC_TSR; // Transmit Status Register - AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer - AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer - AT91_REG EMAC_RSR; // Receive Status Register - AT91_REG EMAC_ISR; // Interrupt Status Register - AT91_REG EMAC_IER; // Interrupt Enable Register - AT91_REG EMAC_IDR; // Interrupt Disable Register - AT91_REG EMAC_IMR; // Interrupt Mask Register - AT91_REG EMAC_MAN; // PHY Maintenance Register - AT91_REG EMAC_PTR; // Pause Time Register - AT91_REG EMAC_PFR; // Pause Frames received Register - AT91_REG EMAC_FTO; // Frames Transmitted OK Register - AT91_REG EMAC_SCF; // Single Collision Frame Register - AT91_REG EMAC_MCF; // Multiple Collision Frame Register - AT91_REG EMAC_FRO; // Frames Received OK Register - AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register - AT91_REG EMAC_ALE; // Alignment Error Register - AT91_REG EMAC_DTF; // Deferred Transmission Frame Register - AT91_REG EMAC_LCOL; // Late Collision Register - AT91_REG EMAC_ECOL; // Excessive Collision Register - AT91_REG EMAC_TUND; // Transmit Underrun Error Register - AT91_REG EMAC_CSE; // Carrier Sense Error Register - AT91_REG EMAC_RRE; // Receive Ressource Error Register - AT91_REG EMAC_ROV; // Receive Overrun Errors Register - AT91_REG EMAC_RSE; // Receive Symbol Errors Register - AT91_REG EMAC_ELE; // Excessive Length Errors Register - AT91_REG EMAC_RJA; // Receive Jabbers Register - AT91_REG EMAC_USF; // Undersize Frames Register - AT91_REG EMAC_STE; // SQE Test Error Register - AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register - AT91_REG EMAC_TPF; // Transmitted Pause Frames Register - AT91_REG EMAC_HRB; // Hash Address Bottom[31:0] - AT91_REG EMAC_HRT; // Hash Address Top[63:32] - AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes - AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes - AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes - AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes - AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes - AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes - AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes - AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes - AT91_REG EMAC_TID; // Type ID Checking Register - AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register - AT91_REG EMAC_USRIO; // USER Input/Output Register - AT91_REG EMAC_WOL; // Wake On LAN Register - AT91_REG Reserved1[13]; // - AT91_REG EMAC_REV; // Revision Register -} AT91S_EMAC, *AT91PS_EMAC; - -// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- -#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. -#define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local. -#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable. -#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable. -#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable. -#define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers. -#define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers. -#define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers. -#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure. -#define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission. -#define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. -#define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame -#define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame -// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- -#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed. -#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex. -#define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames. -#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames. -#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast. -#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable -#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable. -#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes. -#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable. -#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC) -#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8 -#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16 -#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32 -#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64 -#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC) -#define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC) -#define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC) -#define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer -#define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable -#define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS -#define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC) -#define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS -// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- -#define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC) -// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- -#define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC) -#define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go -#define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame -#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC) -#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC) -// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- -#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC) -// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- -#define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC) -#define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC) -#define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC) -#define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC) -#define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC) -#define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC) -#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC) -#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC) -#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC) -#define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC) -#define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC) -// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- -// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- -// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- -// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- -#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC) -#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC) -#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC) -#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC) -#define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC) -// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- -#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII -// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- -#define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address -#define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable -#define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable -#define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable -// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- -#define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC) - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Analog to Digital Convertor -// ***************************************************************************** -typedef struct _AT91S_ADC { - AT91_REG ADC_CR; // ADC Control Register - AT91_REG ADC_MR; // ADC Mode Register - AT91_REG Reserved0[2]; // - AT91_REG ADC_CHER; // ADC Channel Enable Register - AT91_REG ADC_CHDR; // ADC Channel Disable Register - AT91_REG ADC_CHSR; // ADC Channel Status Register - AT91_REG ADC_SR; // ADC Status Register - AT91_REG ADC_LCDR; // ADC Last Converted Data Register - AT91_REG ADC_IER; // ADC Interrupt Enable Register - AT91_REG ADC_IDR; // ADC Interrupt Disable Register - AT91_REG ADC_IMR; // ADC Interrupt Mask Register - AT91_REG ADC_CDR0; // ADC Channel Data Register 0 - AT91_REG ADC_CDR1; // ADC Channel Data Register 1 - AT91_REG ADC_CDR2; // ADC Channel Data Register 2 - AT91_REG ADC_CDR3; // ADC Channel Data Register 3 - AT91_REG ADC_CDR4; // ADC Channel Data Register 4 - AT91_REG ADC_CDR5; // ADC Channel Data Register 5 - AT91_REG ADC_CDR6; // ADC Channel Data Register 6 - AT91_REG ADC_CDR7; // ADC Channel Data Register 7 - AT91_REG Reserved1[44]; // - AT91_REG ADC_RPR; // Receive Pointer Register - AT91_REG ADC_RCR; // Receive Counter Register - AT91_REG ADC_TPR; // Transmit Pointer Register - AT91_REG ADC_TCR; // Transmit Counter Register - AT91_REG ADC_RNPR; // Receive Next Pointer Register - AT91_REG ADC_RNCR; // Receive Next Counter Register - AT91_REG ADC_TNPR; // Transmit Next Pointer Register - AT91_REG ADC_TNCR; // Transmit Next Counter Register - AT91_REG ADC_PTCR; // PDC Transfer Control Register - AT91_REG ADC_PTSR; // PDC Transfer Status Register -} AT91S_ADC, *AT91PS_ADC; - -// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- -#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset -#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion -// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- -#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable -#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software -#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. -#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection -#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 -#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 -#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 -#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 -#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 -#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 -#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger -#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution. -#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution -#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution -#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode -#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection -#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time -#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time -// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- -#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0 -#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1 -#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2 -#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3 -#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4 -#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5 -#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6 -#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7 -// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- -// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- -// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- -#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion -#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion -#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion -#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion -#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion -#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion -#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion -#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion -#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error -#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error -#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error -#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error -#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error -#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error -#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error -#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error -#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready -#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun -#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer -#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt -// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- -#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted -// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- -// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- -// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- -// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- -#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data -// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- -// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- -// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- -// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- -// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- -// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- -// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Encryption Standard -// ***************************************************************************** -typedef struct _AT91S_AES { - AT91_REG AES_CR; // Control Register - AT91_REG AES_MR; // Mode Register - AT91_REG Reserved0[2]; // - AT91_REG AES_IER; // Interrupt Enable Register - AT91_REG AES_IDR; // Interrupt Disable Register - AT91_REG AES_IMR; // Interrupt Mask Register - AT91_REG AES_ISR; // Interrupt Status Register - AT91_REG AES_KEYWxR[4]; // Key Word x Register - AT91_REG Reserved1[4]; // - AT91_REG AES_IDATAxR[4]; // Input Data x Register - AT91_REG AES_ODATAxR[4]; // Output Data x Register - AT91_REG AES_IVxR[4]; // Initialization Vector x Register - AT91_REG Reserved2[35]; // - AT91_REG AES_VR; // AES Version Register - AT91_REG AES_RPR; // Receive Pointer Register - AT91_REG AES_RCR; // Receive Counter Register - AT91_REG AES_TPR; // Transmit Pointer Register - AT91_REG AES_TCR; // Transmit Counter Register - AT91_REG AES_RNPR; // Receive Next Pointer Register - AT91_REG AES_RNCR; // Receive Next Counter Register - AT91_REG AES_TNPR; // Transmit Next Pointer Register - AT91_REG AES_TNCR; // Transmit Next Counter Register - AT91_REG AES_PTCR; // PDC Transfer Control Register - AT91_REG AES_PTSR; // PDC Transfer Status Register -} AT91S_AES, *AT91PS_AES; - -// -------- AES_CR : (AES Offset: 0x0) Control Register -------- -#define AT91C_AES_START ((unsigned int) 0x1 << 0) // (AES) Starts Processing -#define AT91C_AES_SWRST ((unsigned int) 0x1 << 8) // (AES) Software Reset -#define AT91C_AES_LOADSEED ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading -// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- -#define AT91C_AES_CIPHER ((unsigned int) 0x1 << 0) // (AES) Processing Mode -#define AT91C_AES_PROCDLY ((unsigned int) 0xF << 4) // (AES) Processing Delay -#define AT91C_AES_SMOD ((unsigned int) 0x3 << 8) // (AES) Start Mode -#define AT91C_AES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. -#define AT91C_AES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). -#define AT91C_AES_SMOD_PDC ((unsigned int) 0x2 << 8) // (AES) PDC Mode (cf datasheet). -#define AT91C_AES_OPMOD ((unsigned int) 0x7 << 12) // (AES) Operation Mode -#define AT91C_AES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode. -#define AT91C_AES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode. -#define AT91C_AES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode. -#define AT91C_AES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode. -#define AT91C_AES_OPMOD_CTR ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode. -#define AT91C_AES_LOD ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode -#define AT91C_AES_CFBS ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size -#define AT91C_AES_CFBS_128_BIT ((unsigned int) 0x0 << 16) // (AES) 128-bit. -#define AT91C_AES_CFBS_64_BIT ((unsigned int) 0x1 << 16) // (AES) 64-bit. -#define AT91C_AES_CFBS_32_BIT ((unsigned int) 0x2 << 16) // (AES) 32-bit. -#define AT91C_AES_CFBS_16_BIT ((unsigned int) 0x3 << 16) // (AES) 16-bit. -#define AT91C_AES_CFBS_8_BIT ((unsigned int) 0x4 << 16) // (AES) 8-bit. -#define AT91C_AES_CKEY ((unsigned int) 0xF << 20) // (AES) Countermeasure Key -#define AT91C_AES_CTYPE ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type -#define AT91C_AES_CTYPE_TYPE1_EN ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled. -#define AT91C_AES_CTYPE_TYPE2_EN ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled. -#define AT91C_AES_CTYPE_TYPE3_EN ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled. -#define AT91C_AES_CTYPE_TYPE4_EN ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled. -#define AT91C_AES_CTYPE_TYPE5_EN ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled. -// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- -#define AT91C_AES_DATRDY ((unsigned int) 0x1 << 0) // (AES) DATRDY -#define AT91C_AES_ENDRX ((unsigned int) 0x1 << 1) // (AES) PDC Read Buffer End -#define AT91C_AES_ENDTX ((unsigned int) 0x1 << 2) // (AES) PDC Write Buffer End -#define AT91C_AES_RXBUFF ((unsigned int) 0x1 << 3) // (AES) PDC Read Buffer Full -#define AT91C_AES_TXBUFE ((unsigned int) 0x1 << 4) // (AES) PDC Write Buffer Empty -#define AT91C_AES_URAD ((unsigned int) 0x1 << 8) // (AES) Unspecified Register Access Detection -// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- -// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- -// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- -#define AT91C_AES_URAT ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status -#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode. -#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing. -#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing. -#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation. -#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation. -#define AT91C_AES_URAT_WO_REG_READ ((unsigned int) 0x5 << 12) // (AES) Write-only register read access. - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard -// ***************************************************************************** -typedef struct _AT91S_TDES { - AT91_REG TDES_CR; // Control Register - AT91_REG TDES_MR; // Mode Register - AT91_REG Reserved0[2]; // - AT91_REG TDES_IER; // Interrupt Enable Register - AT91_REG TDES_IDR; // Interrupt Disable Register - AT91_REG TDES_IMR; // Interrupt Mask Register - AT91_REG TDES_ISR; // Interrupt Status Register - AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register - AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register - AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register - AT91_REG Reserved1[2]; // - AT91_REG TDES_IDATAxR[2]; // Input Data x Register - AT91_REG Reserved2[2]; // - AT91_REG TDES_ODATAxR[2]; // Output Data x Register - AT91_REG Reserved3[2]; // - AT91_REG TDES_IVxR[2]; // Initialization Vector x Register - AT91_REG Reserved4[37]; // - AT91_REG TDES_VR; // TDES Version Register - AT91_REG TDES_RPR; // Receive Pointer Register - AT91_REG TDES_RCR; // Receive Counter Register - AT91_REG TDES_TPR; // Transmit Pointer Register - AT91_REG TDES_TCR; // Transmit Counter Register - AT91_REG TDES_RNPR; // Receive Next Pointer Register - AT91_REG TDES_RNCR; // Receive Next Counter Register - AT91_REG TDES_TNPR; // Transmit Next Pointer Register - AT91_REG TDES_TNCR; // Transmit Next Counter Register - AT91_REG TDES_PTCR; // PDC Transfer Control Register - AT91_REG TDES_PTSR; // PDC Transfer Status Register -} AT91S_TDES, *AT91PS_TDES; - -// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- -#define AT91C_TDES_START ((unsigned int) 0x1 << 0) // (TDES) Starts Processing -#define AT91C_TDES_SWRST ((unsigned int) 0x1 << 8) // (TDES) Software Reset -// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- -#define AT91C_TDES_CIPHER ((unsigned int) 0x1 << 0) // (TDES) Processing Mode -#define AT91C_TDES_TDESMOD ((unsigned int) 0x1 << 1) // (TDES) Single or Triple DES Mode -#define AT91C_TDES_KEYMOD ((unsigned int) 0x1 << 4) // (TDES) Key Mode -#define AT91C_TDES_SMOD ((unsigned int) 0x3 << 8) // (TDES) Start Mode -#define AT91C_TDES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. -#define AT91C_TDES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). -#define AT91C_TDES_SMOD_PDC ((unsigned int) 0x2 << 8) // (TDES) PDC Mode (cf datasheet). -#define AT91C_TDES_OPMOD ((unsigned int) 0x3 << 12) // (TDES) Operation Mode -#define AT91C_TDES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode. -#define AT91C_TDES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode. -#define AT91C_TDES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode. -#define AT91C_TDES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode. -#define AT91C_TDES_LOD ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode -#define AT91C_TDES_CFBS ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size -#define AT91C_TDES_CFBS_64_BIT ((unsigned int) 0x0 << 16) // (TDES) 64-bit. -#define AT91C_TDES_CFBS_32_BIT ((unsigned int) 0x1 << 16) // (TDES) 32-bit. -#define AT91C_TDES_CFBS_16_BIT ((unsigned int) 0x2 << 16) // (TDES) 16-bit. -#define AT91C_TDES_CFBS_8_BIT ((unsigned int) 0x3 << 16) // (TDES) 8-bit. -// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- -#define AT91C_TDES_DATRDY ((unsigned int) 0x1 << 0) // (TDES) DATRDY -#define AT91C_TDES_ENDRX ((unsigned int) 0x1 << 1) // (TDES) PDC Read Buffer End -#define AT91C_TDES_ENDTX ((unsigned int) 0x1 << 2) // (TDES) PDC Write Buffer End -#define AT91C_TDES_RXBUFF ((unsigned int) 0x1 << 3) // (TDES) PDC Read Buffer Full -#define AT91C_TDES_TXBUFE ((unsigned int) 0x1 << 4) // (TDES) PDC Write Buffer Empty -#define AT91C_TDES_URAD ((unsigned int) 0x1 << 8) // (TDES) Unspecified Register Access Detection -// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- -// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- -// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- -#define AT91C_TDES_URAT ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status -#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode. -#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing. -#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing. -#define AT91C_TDES_URAT_WO_REG_READ ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access. - -// ***************************************************************************** -// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 -// ***************************************************************************** -// ========== Register definition for SYS peripheral ========== -// ========== Register definition for AIC peripheral ========== -#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register -#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register -#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register -#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) -#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register -#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register -#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register -#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register -#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register -#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register -#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register -#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register -#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register -#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register -#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register -#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register -#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register -#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register -// ========== Register definition for PDC_DBGU peripheral ========== -#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register -#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register -#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register -#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register -#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register -#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register -#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register -#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register -#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register -#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register -// ========== Register definition for DBGU peripheral ========== -#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register -#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register -#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register -#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register -#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register -#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register -#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register -#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register -#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register -#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register -#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register -#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register -// ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register -#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register -#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register -#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register -#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register -#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register -#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register -#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register -#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register -#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register -#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register -#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register -#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register -// ========== Register definition for PIOB peripheral ========== -#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register -#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register -#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register -#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register -#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register -#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register -#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register -#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register -#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register -#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register -#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register -#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register -#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register -#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register -#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register -#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register -#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr -#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register -#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register -#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register -#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register -#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register -#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register -#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register -#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register -#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register -#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register -#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register -#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register -// ========== Register definition for CKGR peripheral ========== -#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register -#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register -#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register -// ========== Register definition for PMC peripheral ========== -#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register -#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register -#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register -#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register -#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register -#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register -#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register -#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register -#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register -#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register -#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register -#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register -#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register -#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register -#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register -// ========== Register definition for RSTC peripheral ========== -#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register -#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register -#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register -// ========== Register definition for RTTC peripheral ========== -#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register -#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register -#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register -#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register -// ========== Register definition for PITC peripheral ========== -#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register -#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register -#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register -#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register -// ========== Register definition for WDTC peripheral ========== -#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register -#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register -#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register -// ========== Register definition for VREG peripheral ========== -#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register -// ========== Register definition for MC peripheral ========== -#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register -#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register -#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register -#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register -#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register -#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register -// ========== Register definition for PDC_SPI1 peripheral ========== -#define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register -#define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register -#define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register -#define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register -#define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register -#define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register -#define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register -#define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register -#define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register -#define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register -// ========== Register definition for SPI1 peripheral ========== -#define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register -#define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register -#define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register -#define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register -#define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register -#define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register -#define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register -#define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register -#define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register -// ========== Register definition for PDC_SPI0 peripheral ========== -#define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register -#define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register -#define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register -#define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register -#define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register -#define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register -#define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register -#define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register -#define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register -#define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register -// ========== Register definition for SPI0 peripheral ========== -#define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register -#define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register -#define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register -#define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register -#define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register -#define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register -#define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register -#define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register -#define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register -// ========== Register definition for PDC_US1 peripheral ========== -#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register -#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register -#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register -#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register -#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register -#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register -#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register -#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register -#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register -#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register -// ========== Register definition for US1 peripheral ========== -#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register -#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register -#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register -#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register -#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register -#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register -#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register -#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register -#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register -#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register -#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register -#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register -#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register -#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register -// ========== Register definition for PDC_US0 peripheral ========== -#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register -#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register -#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register -#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register -#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register -#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register -#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register -#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register -#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register -#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register -// ========== Register definition for US0 peripheral ========== -#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register -#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register -#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register -#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register -#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register -#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register -#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register -#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register -#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register -#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register -#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register -#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register -#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register -#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register -// ========== Register definition for PDC_SSC peripheral ========== -#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register -#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register -#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register -#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register -#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register -#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register -#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register -#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register -#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register -#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register -// ========== Register definition for SSC peripheral ========== -#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register -#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register -#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register -#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register -#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register -#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister -#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register -#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register -#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register -#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register -#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register -#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register -#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register -#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register -// ========== Register definition for TWI peripheral ========== -#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register -#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register -#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register -#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register -#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register -#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register -#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register -#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register -#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register -#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register -// ========== Register definition for PWMC_CH3 peripheral ========== -#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register -#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved -#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register -#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register -#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register -#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register -// ========== Register definition for PWMC_CH2 peripheral ========== -#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved -#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register -#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register -#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register -#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register -#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH1 peripheral ========== -#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved -#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register -#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register -#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register -#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register -#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register -// ========== Register definition for PWMC_CH0 peripheral ========== -#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved -#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register -#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register -#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register -#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register -#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register -// ========== Register definition for PWMC peripheral ========== -#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register -#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register -#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register -#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register -#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register -#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register -#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register -#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register -#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register -// ========== Register definition for UDP peripheral ========== -#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register -#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register -#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register -#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register -#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register -#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register -#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register -#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register -#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register -#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register -#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register -#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register -// ========== Register definition for TC0 peripheral ========== -#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register -#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C -#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B -#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register -#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register -#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A -#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register -#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value -#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register -// ========== Register definition for TC1 peripheral ========== -#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B -#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register -#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register -#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register -#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register -#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A -#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C -#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register -#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value -// ========== Register definition for TC2 peripheral ========== -#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register -#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value -#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A -#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B -#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register -#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register -#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C -#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register -#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register -// ========== Register definition for TCB peripheral ========== -#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register -#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register -// ========== Register definition for CAN_MB0 peripheral ========== -#define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register -#define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register -#define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register -#define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register -#define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register -#define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register -#define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register -#define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register -// ========== Register definition for CAN_MB1 peripheral ========== -#define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register -#define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register -#define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register -#define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register -#define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register -#define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register -#define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register -#define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register -// ========== Register definition for CAN_MB2 peripheral ========== -#define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register -#define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register -#define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register -#define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register -#define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register -#define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register -#define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register -#define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register -// ========== Register definition for CAN_MB3 peripheral ========== -#define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register -#define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register -#define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register -#define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register -#define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register -#define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register -#define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register -#define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register -// ========== Register definition for CAN_MB4 peripheral ========== -#define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register -#define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register -#define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register -#define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register -#define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register -#define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register -#define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register -#define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register -// ========== Register definition for CAN_MB5 peripheral ========== -#define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register -#define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register -#define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register -#define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register -#define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register -#define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register -#define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register -#define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register -// ========== Register definition for CAN_MB6 peripheral ========== -#define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register -#define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register -#define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register -#define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register -#define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register -#define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register -#define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register -#define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register -// ========== Register definition for CAN_MB7 peripheral ========== -#define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register -#define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register -#define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register -#define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register -#define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register -#define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register -#define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register -#define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register -// ========== Register definition for CAN peripheral ========== -#define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register -#define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register -#define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register -#define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register -#define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register -#define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register -#define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register -#define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register -#define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register -#define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register -#define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register -#define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register -// ========== Register definition for EMAC peripheral ========== -#define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register -#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes -#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes -#define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register -#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register -#define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register -#define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register -#define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register -#define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register -#define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register -#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes -#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register -#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes -#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register -#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register -#define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register -#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register -#define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register -#define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] -#define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer -#define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register -#define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register -#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes -#define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register -#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register -#define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register -#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer -#define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register -#define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register -#define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32] -#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register -#define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register -#define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register -#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register -#define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register -#define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register -#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register -#define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register -#define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register -#define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register -#define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register -#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes -#define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register -#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register -#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes -#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register -#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes -#define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register -#define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register -// ========== Register definition for PDC_ADC peripheral ========== -#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register -#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register -#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register -#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register -#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register -#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register -#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register -#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register -#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register -#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register -// ========== Register definition for ADC peripheral ========== -#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 -#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 -#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 -#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 -#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register -#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register -#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 -#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 -#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register -#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register -#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register -#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 -#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 -#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register -#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register -#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register -#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register -#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register -// ========== Register definition for PDC_AES peripheral ========== -#define AT91C_AES_TPR ((AT91_REG *) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register -#define AT91C_AES_PTCR ((AT91_REG *) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register -#define AT91C_AES_RNPR ((AT91_REG *) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register -#define AT91C_AES_TNCR ((AT91_REG *) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register -#define AT91C_AES_TCR ((AT91_REG *) 0xFFFA410C) // (PDC_AES) Transmit Counter Register -#define AT91C_AES_RCR ((AT91_REG *) 0xFFFA4104) // (PDC_AES) Receive Counter Register -#define AT91C_AES_RNCR ((AT91_REG *) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register -#define AT91C_AES_TNPR ((AT91_REG *) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register -#define AT91C_AES_RPR ((AT91_REG *) 0xFFFA4100) // (PDC_AES) Receive Pointer Register -#define AT91C_AES_PTSR ((AT91_REG *) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register -// ========== Register definition for AES peripheral ========== -#define AT91C_AES_IVxR ((AT91_REG *) 0xFFFA4060) // (AES) Initialization Vector x Register -#define AT91C_AES_MR ((AT91_REG *) 0xFFFA4004) // (AES) Mode Register -#define AT91C_AES_VR ((AT91_REG *) 0xFFFA40FC) // (AES) AES Version Register -#define AT91C_AES_ODATAxR ((AT91_REG *) 0xFFFA4050) // (AES) Output Data x Register -#define AT91C_AES_IDATAxR ((AT91_REG *) 0xFFFA4040) // (AES) Input Data x Register -#define AT91C_AES_CR ((AT91_REG *) 0xFFFA4000) // (AES) Control Register -#define AT91C_AES_IDR ((AT91_REG *) 0xFFFA4014) // (AES) Interrupt Disable Register -#define AT91C_AES_IMR ((AT91_REG *) 0xFFFA4018) // (AES) Interrupt Mask Register -#define AT91C_AES_IER ((AT91_REG *) 0xFFFA4010) // (AES) Interrupt Enable Register -#define AT91C_AES_KEYWxR ((AT91_REG *) 0xFFFA4020) // (AES) Key Word x Register -#define AT91C_AES_ISR ((AT91_REG *) 0xFFFA401C) // (AES) Interrupt Status Register -// ========== Register definition for PDC_TDES peripheral ========== -#define AT91C_TDES_RNCR ((AT91_REG *) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register -#define AT91C_TDES_TCR ((AT91_REG *) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register -#define AT91C_TDES_RCR ((AT91_REG *) 0xFFFA8104) // (PDC_TDES) Receive Counter Register -#define AT91C_TDES_TNPR ((AT91_REG *) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register -#define AT91C_TDES_RNPR ((AT91_REG *) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register -#define AT91C_TDES_RPR ((AT91_REG *) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register -#define AT91C_TDES_TNCR ((AT91_REG *) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register -#define AT91C_TDES_TPR ((AT91_REG *) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register -#define AT91C_TDES_PTSR ((AT91_REG *) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register -#define AT91C_TDES_PTCR ((AT91_REG *) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register -// ========== Register definition for TDES peripheral ========== -#define AT91C_TDES_KEY2WxR ((AT91_REG *) 0xFFFA8028) // (TDES) Key 2 Word x Register -#define AT91C_TDES_KEY3WxR ((AT91_REG *) 0xFFFA8030) // (TDES) Key 3 Word x Register -#define AT91C_TDES_IDR ((AT91_REG *) 0xFFFA8014) // (TDES) Interrupt Disable Register -#define AT91C_TDES_VR ((AT91_REG *) 0xFFFA80FC) // (TDES) TDES Version Register -#define AT91C_TDES_IVxR ((AT91_REG *) 0xFFFA8060) // (TDES) Initialization Vector x Register -#define AT91C_TDES_ODATAxR ((AT91_REG *) 0xFFFA8050) // (TDES) Output Data x Register -#define AT91C_TDES_IMR ((AT91_REG *) 0xFFFA8018) // (TDES) Interrupt Mask Register -#define AT91C_TDES_MR ((AT91_REG *) 0xFFFA8004) // (TDES) Mode Register -#define AT91C_TDES_CR ((AT91_REG *) 0xFFFA8000) // (TDES) Control Register -#define AT91C_TDES_IER ((AT91_REG *) 0xFFFA8010) // (TDES) Interrupt Enable Register -#define AT91C_TDES_ISR ((AT91_REG *) 0xFFFA801C) // (TDES) Interrupt Status Register -#define AT91C_TDES_IDATAxR ((AT91_REG *) 0xFFFA8040) // (TDES) Input Data x Register -#define AT91C_TDES_KEY1WxR ((AT91_REG *) 0xFFFA8020) // (TDES) Key 1 Word x Register - -// ***************************************************************************** -// PIO DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 -#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data -#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 -#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data -#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 -#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data -#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 -#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock -#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 -#define AT91C_PA12_NPCS00 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 -#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 -#define AT91C_PA13_NPCS01 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 -#define AT91C_PA14_NPCS02 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1 -#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 -#define AT91C_PA15_NPCS03 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input -#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 -#define AT91C_PA16_MISO0 ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave -#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 -#define AT91C_PA17_MOSI0 ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave -#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 -#define AT91C_PA18_SPCK0 ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock -#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 -#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive -#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 -#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock -#define AT91C_PA2_NPCS11 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 -#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit -#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 -#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync -#define AT91C_PA21_NPCS10 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 -#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 -#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock -#define AT91C_PA22_SPCK1 ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock -#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 -#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data -#define AT91C_PA23_MOSI1 ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave -#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 -#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data -#define AT91C_PA24_MISO1 ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave -#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 -#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock -#define AT91C_PA25_NPCS11 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 -#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync -#define AT91C_PA26_NPCS12 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 -#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data -#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3 -#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 -#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data -#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 -#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input -#define AT91C_PA29_NPCS13 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 -#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send -#define AT91C_PA3_NPCS12 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 -#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0 -#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 -#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send -#define AT91C_PA4_NPCS13 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 -#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data -#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 -#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data -#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 -#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock -#define AT91C_PA7_NPCS01 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 -#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send -#define AT91C_PA8_NPCS02 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 -#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send -#define AT91C_PA9_NPCS03 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0 -#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock -#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1 -#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable -#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10 -#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 -#define AT91C_PB10_NPCS11 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11 -#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 -#define AT91C_PB11_NPCS12 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12 -#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error -#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input -#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13 -#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 -#define AT91C_PB13_NPCS01 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14 -#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 -#define AT91C_PB14_NPCS02 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15 -#define AT91C_PB15_ERXDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid -#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16 -#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected -#define AT91C_PB16_NPCS13 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17 -#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock -#define AT91C_PB17_NPCS03 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18 -#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec -#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger -#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19 -#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0 -#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input -#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2 -#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 -#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20 -#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1 -#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21 -#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2 -#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22 -#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3 -#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23 -#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A -#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect -#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24 -#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B -#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready -#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25 -#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A -#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready -#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26 -#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B -#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator -#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27 -#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A -#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0 -#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28 -#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B -#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1 -#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29 -#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1 -#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2 -#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3 -#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 -#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30 -#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2 -#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3 -#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4 -#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid -#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5 -#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 -#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6 -#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 -#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7 -#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error -#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8 -#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock -#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9 -#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output - -// ***************************************************************************** -// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) -#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral -#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A -#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B -#define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0 -#define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1 -#define AT91C_ID_US0 ((unsigned int) 6) // USART 0 -#define AT91C_ID_US1 ((unsigned int) 7) // USART 1 -#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller -#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface -#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller -#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port -#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0 -#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1 -#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2 -#define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller -#define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC -#define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter -#define AT91C_ID_AES ((unsigned int) 18) // Advanced Encryption Standard 128-bit -#define AT91C_ID_TDES ((unsigned int) 19) // Triple Data Encryption Standard -#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved -#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved -#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved -#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved -#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved -#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved -#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved -#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved -#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved -#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved -#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0) -#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1) - -// ***************************************************************************** -// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address -#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address -#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address -#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address -#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address -#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address -#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address -#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address -#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address -#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address -#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address -#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address -#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address -#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address -#define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address -#define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address -#define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address -#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address -#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address -#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address -#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address -#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address -#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address -#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address -#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address -#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address -#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address -#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address -#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address -#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address -#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address -#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address -#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address -#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address -#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address -#define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address -#define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address -#define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address -#define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address -#define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address -#define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address -#define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address -#define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address -#define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address -#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address -#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address -#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address -#define AT91C_BASE_PDC_AES ((AT91PS_PDC) 0xFFFA4100) // (PDC_AES) Base Address -#define AT91C_BASE_AES ((AT91PS_AES) 0xFFFA4000) // (AES) Base Address -#define AT91C_BASE_PDC_TDES ((AT91PS_PDC) 0xFFFA8100) // (PDC_TDES) Base Address -#define AT91C_BASE_TDES ((AT91PS_TDES) 0xFFFA8000) // (TDES) Base Address - -// ***************************************************************************** -// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address -#define AT91C_ISRAM_SIZE ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte) -#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address -#define AT91C_IFLASH_SIZE ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte) - - - -// - Hardware register definition - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR System Peripherals -// - ***************************************************************************** - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// - ***************************************************************************** -// - -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -#if 0 /*_RB_*/ -AT91C_AIC_PRIOR EQU (0x7 << 0) ;- (AIC) Priority Level -AT91C_AIC_PRIOR_LOWEST EQU (0x0) ;- (AIC) Lowest priority level -AT91C_AIC_PRIOR_HIGHEST EQU (0x7) ;- (AIC) Highest priority level -AT91C_AIC_SRCTYPE EQU (0x3 << 5) ;- (AIC) Interrupt Source Type -AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL EQU (0x0 << 5) ;- (AIC) Internal Sources Code Label High-level Sensitive -AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL EQU (0x0 << 5) ;- (AIC) External Sources Code Label Low-level Sensitive -AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE EQU (0x1 << 5) ;- (AIC) Internal Sources Code Label Positive Edge triggered -AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE EQU (0x1 << 5) ;- (AIC) External Sources Code Label Negative Edge triggered -AT91C_AIC_SRCTYPE_HIGH_LEVEL EQU (0x2 << 5) ;- (AIC) Internal Or External Sources Code Label High-level Sensitive -AT91C_AIC_SRCTYPE_POSITIVE_EDGE EQU (0x3 << 5) ;- (AIC) Internal Or External Sources Code Label Positive Edge triggered -// - -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -AT91C_AIC_NFIQ EQU (0x1 << 0) ;- (AIC) NFIQ Status -AT91C_AIC_NIRQ EQU (0x1 << 1) ;- (AIC) NIRQ Status -// - -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -AT91C_AIC_DCR_PROT EQU (0x1 << 0) ;- (AIC) Protection Mode -AT91C_AIC_DCR_GMSK EQU (0x1 << 1) ;- (AIC) General Mask -#endif -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Peripheral DMA Controller -// - ***************************************************************************** -// - -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -AT91C_PDC_RXTEN EQU (0x1 << 0) ;- (PDC) Receiver Transfer Enable -AT91C_PDC_RXTDIS EQU (0x1 << 1) ;- (PDC) Receiver Transfer Disable -AT91C_PDC_TXTEN EQU (0x1 << 8) ;- (PDC) Transmitter Transfer Enable -AT91C_PDC_TXTDIS EQU (0x1 << 9) ;- (PDC) Transmitter Transfer Disable -// - -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Debug Unit -// - ***************************************************************************** -// - -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -AT91C_US_RSTRX EQU (0x1 << 2) ;- (DBGU) Reset Receiver -AT91C_US_RSTTX EQU (0x1 << 3) ;- (DBGU) Reset Transmitter -AT91C_US_RXEN EQU (0x1 << 4) ;- (DBGU) Receiver Enable -AT91C_US_RXDIS EQU (0x1 << 5) ;- (DBGU) Receiver Disable -AT91C_US_TXEN EQU (0x1 << 6) ;- (DBGU) Transmitter Enable -AT91C_US_TXDIS EQU (0x1 << 7) ;- (DBGU) Transmitter Disable -AT91C_US_RSTSTA EQU (0x1 << 8) ;- (DBGU) Reset Status Bits -// - -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -AT91C_US_PAR EQU (0x7 << 9) ;- (DBGU) Parity type -AT91C_US_PAR_EVEN EQU (0x0 << 9) ;- (DBGU) Even Parity -AT91C_US_PAR_ODD EQU (0x1 << 9) ;- (DBGU) Odd Parity -AT91C_US_PAR_SPACE EQU (0x2 << 9) ;- (DBGU) Parity forced to 0 (Space) -AT91C_US_PAR_MARK EQU (0x3 << 9) ;- (DBGU) Parity forced to 1 (Mark) -AT91C_US_PAR_NONE EQU (0x4 << 9) ;- (DBGU) No Parity -AT91C_US_PAR_MULTI_DROP EQU (0x6 << 9) ;- (DBGU) Multi-drop mode -AT91C_US_CHMODE EQU (0x3 << 14) ;- (DBGU) Channel Mode -AT91C_US_CHMODE_NORMAL EQU (0x0 << 14) ;- (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -AT91C_US_CHMODE_AUTO EQU (0x1 << 14) ;- (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -AT91C_US_CHMODE_LOCAL EQU (0x2 << 14) ;- (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -AT91C_US_CHMODE_REMOTE EQU (0x3 << 14) ;- (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// - -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -AT91C_US_RXRDY EQU (0x1 << 0) ;- (DBGU) RXRDY Interrupt -AT91C_US_TXRDY EQU (0x1 << 1) ;- (DBGU) TXRDY Interrupt -AT91C_US_ENDRX EQU (0x1 << 3) ;- (DBGU) End of Receive Transfer Interrupt -AT91C_US_ENDTX EQU (0x1 << 4) ;- (DBGU) End of Transmit Interrupt -AT91C_US_OVRE EQU (0x1 << 5) ;- (DBGU) Overrun Interrupt -AT91C_US_FRAME EQU (0x1 << 6) ;- (DBGU) Framing Error Interrupt -AT91C_US_PARE EQU (0x1 << 7) ;- (DBGU) Parity Error Interrupt -AT91C_US_TXEMPTY EQU (0x1 << 9) ;- (DBGU) TXEMPTY Interrupt -AT91C_US_TXBUFE EQU (0x1 << 11) ;- (DBGU) TXBUFE Interrupt -AT91C_US_RXBUFF EQU (0x1 << 12) ;- (DBGU) RXBUFF Interrupt -AT91C_US_COMM_TX EQU (0x1 << 30) ;- (DBGU) COMM_TX Interrupt -AT91C_US_COMM_RX EQU (0x1 << 31) ;- (DBGU) COMM_RX Interrupt -// - -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// - -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// - -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// - -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -AT91C_US_FORCE_NTRST EQU (0x1 << 0) ;- (DBGU) Force NTRST in JTAG - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// - ***************************************************************************** - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Clock Generator Controler -// - ***************************************************************************** -// - -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -AT91C_CKGR_MOSCEN EQU (0x1 << 0) ;- (CKGR) Main Oscillator Enable -AT91C_CKGR_OSCBYPASS EQU (0x1 << 1) ;- (CKGR) Main Oscillator Bypass -AT91C_CKGR_OSCOUNT EQU (0xFF << 8) ;- (CKGR) Main Oscillator Start-up Time -// - -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -AT91C_CKGR_MAINF EQU (0xFFFF << 0) ;- (CKGR) Main Clock Frequency -AT91C_CKGR_MAINRDY EQU (0x1 << 16) ;- (CKGR) Main Clock Ready -// - -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- -AT91C_CKGR_DIV EQU (0xFF << 0) ;- (CKGR) Divider Selected -AT91C_CKGR_DIV_0 EQU (0x0) ;- (CKGR) Divider output is 0 -AT91C_CKGR_DIV_BYPASS EQU (0x1) ;- (CKGR) Divider is bypassed -AT91C_CKGR_PLLCOUNT EQU (0x3F << 8) ;- (CKGR) PLL Counter -AT91C_CKGR_OUT EQU (0x3 << 14) ;- (CKGR) PLL Output Frequency Range -AT91C_CKGR_OUT_0 EQU (0x0 << 14) ;- (CKGR) Please refer to the PLL datasheet -AT91C_CKGR_OUT_1 EQU (0x1 << 14) ;- (CKGR) Please refer to the PLL datasheet -AT91C_CKGR_OUT_2 EQU (0x2 << 14) ;- (CKGR) Please refer to the PLL datasheet -AT91C_CKGR_OUT_3 EQU (0x3 << 14) ;- (CKGR) Please refer to the PLL datasheet -AT91C_CKGR_MUL EQU (0x7FF << 16) ;- (CKGR) PLL Multiplier -AT91C_CKGR_USBDIV EQU (0x3 << 28) ;- (CKGR) Divider for USB Clocks -AT91C_CKGR_USBDIV_0 EQU (0x0 << 28) ;- (CKGR) Divider output is PLL clock output -AT91C_CKGR_USBDIV_1 EQU (0x1 << 28) ;- (CKGR) Divider output is PLL clock output divided by 2 -AT91C_CKGR_USBDIV_2 EQU (0x2 << 28) ;- (CKGR) Divider output is PLL clock output divided by 4 - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Power Management Controler -// - ***************************************************************************** -// - -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -AT91C_PMC_PCK EQU (0x1 << 0) ;- (PMC) Processor Clock -AT91C_PMC_UDP EQU (0x1 << 7) ;- (PMC) USB Device Port Clock -AT91C_PMC_PCK0 EQU (0x1 << 8) ;- (PMC) Programmable Clock Output -AT91C_PMC_PCK1 EQU (0x1 << 9) ;- (PMC) Programmable Clock Output -AT91C_PMC_PCK2 EQU (0x1 << 10) ;- (PMC) Programmable Clock Output -AT91C_PMC_PCK3 EQU (0x1 << 11) ;- (PMC) Programmable Clock Output -// - -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// - -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// - -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- -// - -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- -// - -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- -// - -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -AT91C_PMC_CSS EQU (0x3 << 0) ;- (PMC) Programmable Clock Selection -AT91C_PMC_CSS_SLOW_CLK EQU (0x0) ;- (PMC) Slow Clock is selected -AT91C_PMC_CSS_MAIN_CLK EQU (0x1) ;- (PMC) Main Clock is selected -AT91C_PMC_CSS_PLL_CLK EQU (0x3) ;- (PMC) Clock from PLL is selected -AT91C_PMC_PRES EQU (0x7 << 2) ;- (PMC) Programmable Clock Prescaler -AT91C_PMC_PRES_CLK EQU (0x0 << 2) ;- (PMC) Selected clock -AT91C_PMC_PRES_CLK_2 EQU (0x1 << 2) ;- (PMC) Selected clock divided by 2 -AT91C_PMC_PRES_CLK_4 EQU (0x2 << 2) ;- (PMC) Selected clock divided by 4 -AT91C_PMC_PRES_CLK_8 EQU (0x3 << 2) ;- (PMC) Selected clock divided by 8 -AT91C_PMC_PRES_CLK_16 EQU (0x4 << 2) ;- (PMC) Selected clock divided by 16 -AT91C_PMC_PRES_CLK_32 EQU (0x5 << 2) ;- (PMC) Selected clock divided by 32 -AT91C_PMC_PRES_CLK_64 EQU (0x6 << 2) ;- (PMC) Selected clock divided by 64 -// - -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// - -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -AT91C_PMC_MOSCS EQU (0x1 << 0) ;- (PMC) MOSC Status/Enable/Disable/Mask -AT91C_PMC_LOCK EQU (0x1 << 2) ;- (PMC) PLL Status/Enable/Disable/Mask -AT91C_PMC_MCKRDY EQU (0x1 << 3) ;- (PMC) MCK_RDY Status/Enable/Disable/Mask -AT91C_PMC_PCK0RDY EQU (0x1 << 8) ;- (PMC) PCK0_RDY Status/Enable/Disable/Mask -AT91C_PMC_PCK1RDY EQU (0x1 << 9) ;- (PMC) PCK1_RDY Status/Enable/Disable/Mask -AT91C_PMC_PCK2RDY EQU (0x1 << 10) ;- (PMC) PCK2_RDY Status/Enable/Disable/Mask -AT91C_PMC_PCK3RDY EQU (0x1 << 11) ;- (PMC) PCK3_RDY Status/Enable/Disable/Mask -// - -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// - -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// - -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Reset Controller Interface -// - ***************************************************************************** -// - -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- -AT91C_RSTC_PROCRST EQU (0x1 << 0) ;- (RSTC) Processor Reset -AT91C_RSTC_PERRST EQU (0x1 << 2) ;- (RSTC) Peripheral Reset -AT91C_RSTC_EXTRST EQU (0x1 << 3) ;- (RSTC) External Reset -AT91C_RSTC_KEY EQU (0xFF << 24) ;- (RSTC) Password -// - -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- -AT91C_RSTC_URSTS EQU (0x1 << 0) ;- (RSTC) User Reset Status -AT91C_RSTC_BODSTS EQU (0x1 << 1) ;- (RSTC) Brownout Detection Status -AT91C_RSTC_RSTTYP EQU (0x7 << 8) ;- (RSTC) Reset Type -AT91C_RSTC_RSTTYP_POWERUP EQU (0x0 << 8) ;- (RSTC) Power-up Reset. VDDCORE rising. -AT91C_RSTC_RSTTYP_WAKEUP EQU (0x1 << 8) ;- (RSTC) WakeUp Reset. VDDCORE rising. -AT91C_RSTC_RSTTYP_WATCHDOG EQU (0x2 << 8) ;- (RSTC) Watchdog Reset. Watchdog overflow occured. -AT91C_RSTC_RSTTYP_SOFTWARE EQU (0x3 << 8) ;- (RSTC) Software Reset. Processor reset required by the software. -AT91C_RSTC_RSTTYP_USER EQU (0x4 << 8) ;- (RSTC) User Reset. NRST pin detected low. -AT91C_RSTC_RSTTYP_BROWNOUT EQU (0x5 << 8) ;- (RSTC) Brownout Reset occured. -AT91C_RSTC_NRSTL EQU (0x1 << 16) ;- (RSTC) NRST pin level -AT91C_RSTC_SRCMP EQU (0x1 << 17) ;- (RSTC) Software Reset Command in Progress. -// - -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- -AT91C_RSTC_URSTEN EQU (0x1 << 0) ;- (RSTC) User Reset Enable -AT91C_RSTC_URSTIEN EQU (0x1 << 4) ;- (RSTC) User Reset Interrupt Enable -AT91C_RSTC_ERSTL EQU (0xF << 8) ;- (RSTC) User Reset Enable -AT91C_RSTC_BODIEN EQU (0x1 << 16) ;- (RSTC) Brownout Detection Interrupt Enable - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface -// - ***************************************************************************** -// - -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- -AT91C_RTTC_RTPRES EQU (0xFFFF << 0) ;- (RTTC) Real-time Timer Prescaler Value -AT91C_RTTC_ALMIEN EQU (0x1 << 16) ;- (RTTC) Alarm Interrupt Enable -AT91C_RTTC_RTTINCIEN EQU (0x1 << 17) ;- (RTTC) Real Time Timer Increment Interrupt Enable -AT91C_RTTC_RTTRST EQU (0x1 << 18) ;- (RTTC) Real Time Timer Restart -// - -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- -AT91C_RTTC_ALMV EQU (0x0 << 0) ;- (RTTC) Alarm Value -// - -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- -AT91C_RTTC_CRTV EQU (0x0 << 0) ;- (RTTC) Current Real-time Value -// - -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- -AT91C_RTTC_ALMS EQU (0x1 << 0) ;- (RTTC) Real-time Alarm Status -AT91C_RTTC_RTTINC EQU (0x1 << 1) ;- (RTTC) Real-time Timer Increment - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface -// - ***************************************************************************** -// - -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- -AT91C_PITC_PIV EQU (0xFFFFF << 0) ;- (PITC) Periodic Interval Value -AT91C_PITC_PITEN EQU (0x1 << 24) ;- (PITC) Periodic Interval Timer Enabled -AT91C_PITC_PITIEN EQU (0x1 << 25) ;- (PITC) Periodic Interval Timer Interrupt Enable -// - -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- -AT91C_PITC_PITS EQU (0x1 << 0) ;- (PITC) Periodic Interval Timer Status -// - -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- -AT91C_PITC_CPIV EQU (0xFFFFF << 0) ;- (PITC) Current Periodic Interval Value -AT91C_PITC_PICNT EQU (0xFFF << 20) ;- (PITC) Periodic Interval Counter -// - -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface -// - ***************************************************************************** -// - -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- -AT91C_WDTC_WDRSTT EQU (0x1 << 0) ;- (WDTC) Watchdog Restart -AT91C_WDTC_KEY EQU (0xFF << 24) ;- (WDTC) Watchdog KEY Password -// - -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- -AT91C_WDTC_WDV EQU (0xFFF << 0) ;- (WDTC) Watchdog Timer Restart -AT91C_WDTC_WDFIEN EQU (0x1 << 12) ;- (WDTC) Watchdog Fault Interrupt Enable -AT91C_WDTC_WDRSTEN EQU (0x1 << 13) ;- (WDTC) Watchdog Reset Enable -AT91C_WDTC_WDRPROC EQU (0x1 << 14) ;- (WDTC) Watchdog Timer Restart -AT91C_WDTC_WDDIS EQU (0x1 << 15) ;- (WDTC) Watchdog Disable -AT91C_WDTC_WDD EQU (0xFFF << 16) ;- (WDTC) Watchdog Delta Value -AT91C_WDTC_WDDBGHLT EQU (0x1 << 28) ;- (WDTC) Watchdog Debug Halt -AT91C_WDTC_WDIDLEHLT EQU (0x1 << 29) ;- (WDTC) Watchdog Idle Halt -// - -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- -AT91C_WDTC_WDUNF EQU (0x1 << 0) ;- (WDTC) Watchdog Underflow -AT91C_WDTC_WDERR EQU (0x1 << 1) ;- (WDTC) Watchdog Error - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface -// - ***************************************************************************** -// - -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- -AT91C_VREG_PSTDBY EQU (0x1 << 0) ;- (VREG) Voltage Regulator Power Standby Mode - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Memory Controller Interface -// - ***************************************************************************** -// - -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -AT91C_MC_RCB EQU (0x1 << 0) ;- (MC) Remap Command Bit -// - -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -AT91C_MC_UNDADD EQU (0x1 << 0) ;- (MC) Undefined Addess Abort Status -AT91C_MC_MISADD EQU (0x1 << 1) ;- (MC) Misaligned Addess Abort Status -AT91C_MC_ABTSZ EQU (0x3 << 8) ;- (MC) Abort Size Status -AT91C_MC_ABTSZ_BYTE EQU (0x0 << 8) ;- (MC) Byte -AT91C_MC_ABTSZ_HWORD EQU (0x1 << 8) ;- (MC) Half-word -AT91C_MC_ABTSZ_WORD EQU (0x2 << 8) ;- (MC) Word -AT91C_MC_ABTTYP EQU (0x3 << 10) ;- (MC) Abort Type Status -AT91C_MC_ABTTYP_DATAR EQU (0x0 << 10) ;- (MC) Data Read -AT91C_MC_ABTTYP_DATAW EQU (0x1 << 10) ;- (MC) Data Write -AT91C_MC_ABTTYP_FETCH EQU (0x2 << 10) ;- (MC) Code Fetch -AT91C_MC_MST0 EQU (0x1 << 16) ;- (MC) Master 0 Abort Source -AT91C_MC_MST1 EQU (0x1 << 17) ;- (MC) Master 1 Abort Source -AT91C_MC_SVMST0 EQU (0x1 << 24) ;- (MC) Saved Master 0 Abort Source -AT91C_MC_SVMST1 EQU (0x1 << 25) ;- (MC) Saved Master 1 Abort Source -// - -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- -AT91C_MC_FRDY EQU (0x1 << 0) ;- (MC) Flash Ready -AT91C_MC_LOCKE EQU (0x1 << 2) ;- (MC) Lock Error -AT91C_MC_PROGE EQU (0x1 << 3) ;- (MC) Programming Error -AT91C_MC_NEBP EQU (0x1 << 7) ;- (MC) No Erase Before Programming -AT91C_MC_FWS EQU (0x3 << 8) ;- (MC) Flash Wait State -AT91C_MC_FWS_0FWS EQU (0x0 << 8) ;- (MC) 1 cycle for Read, 2 for Write operations -AT91C_MC_FWS_1FWS EQU (0x1 << 8) ;- (MC) 2 cycles for Read, 3 for Write operations -AT91C_MC_FWS_2FWS EQU (0x2 << 8) ;- (MC) 3 cycles for Read, 4 for Write operations -AT91C_MC_FWS_3FWS EQU (0x3 << 8) ;- (MC) 4 cycles for Read, 4 for Write operations -AT91C_MC_FMCN EQU (0xFF << 16) ;- (MC) Flash Microsecond Cycle Number -// - -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- -AT91C_MC_FCMD EQU (0xF << 0) ;- (MC) Flash Command -AT91C_MC_FCMD_START_PROG EQU (0x1) ;- (MC) Starts the programming of th epage specified by PAGEN. -AT91C_MC_FCMD_LOCK EQU (0x2) ;- (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -AT91C_MC_FCMD_PROG_AND_LOCK EQU (0x3) ;- (MC) The lock sequence automatically happens after the programming sequence is completed. -AT91C_MC_FCMD_UNLOCK EQU (0x4) ;- (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -AT91C_MC_FCMD_ERASE_ALL EQU (0x8) ;- (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. -AT91C_MC_FCMD_SET_GP_NVM EQU (0xB) ;- (MC) Set General Purpose NVM bits. -AT91C_MC_FCMD_CLR_GP_NVM EQU (0xD) ;- (MC) Clear General Purpose NVM bits. -AT91C_MC_FCMD_SET_SECURITY EQU (0xF) ;- (MC) Set Security Bit. -AT91C_MC_PAGEN EQU (0x3FF << 8) ;- (MC) Page Number -AT91C_MC_KEY EQU (0xFF << 24) ;- (MC) Writing Protect Key -// - -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- -AT91C_MC_SECURITY EQU (0x1 << 4) ;- (MC) Security Bit Status -AT91C_MC_GPNVM0 EQU (0x1 << 8) ;- (MC) Sector 0 Lock Status -AT91C_MC_GPNVM1 EQU (0x1 << 9) ;- (MC) Sector 1 Lock Status -AT91C_MC_GPNVM2 EQU (0x1 << 10) ;- (MC) Sector 2 Lock Status -AT91C_MC_GPNVM3 EQU (0x1 << 11) ;- (MC) Sector 3 Lock Status -AT91C_MC_GPNVM4 EQU (0x1 << 12) ;- (MC) Sector 4 Lock Status -AT91C_MC_GPNVM5 EQU (0x1 << 13) ;- (MC) Sector 5 Lock Status -AT91C_MC_GPNVM6 EQU (0x1 << 14) ;- (MC) Sector 6 Lock Status -AT91C_MC_GPNVM7 EQU (0x1 << 15) ;- (MC) Sector 7 Lock Status -AT91C_MC_LOCKS0 EQU (0x1 << 16) ;- (MC) Sector 0 Lock Status -AT91C_MC_LOCKS1 EQU (0x1 << 17) ;- (MC) Sector 1 Lock Status -AT91C_MC_LOCKS2 EQU (0x1 << 18) ;- (MC) Sector 2 Lock Status -AT91C_MC_LOCKS3 EQU (0x1 << 19) ;- (MC) Sector 3 Lock Status -AT91C_MC_LOCKS4 EQU (0x1 << 20) ;- (MC) Sector 4 Lock Status -AT91C_MC_LOCKS5 EQU (0x1 << 21) ;- (MC) Sector 5 Lock Status -AT91C_MC_LOCKS6 EQU (0x1 << 22) ;- (MC) Sector 6 Lock Status -AT91C_MC_LOCKS7 EQU (0x1 << 23) ;- (MC) Sector 7 Lock Status -AT91C_MC_LOCKS8 EQU (0x1 << 24) ;- (MC) Sector 8 Lock Status -AT91C_MC_LOCKS9 EQU (0x1 << 25) ;- (MC) Sector 9 Lock Status -AT91C_MC_LOCKS10 EQU (0x1 << 26) ;- (MC) Sector 10 Lock Status -AT91C_MC_LOCKS11 EQU (0x1 << 27) ;- (MC) Sector 11 Lock Status -AT91C_MC_LOCKS12 EQU (0x1 << 28) ;- (MC) Sector 12 Lock Status -AT91C_MC_LOCKS13 EQU (0x1 << 29) ;- (MC) Sector 13 Lock Status -AT91C_MC_LOCKS14 EQU (0x1 << 30) ;- (MC) Sector 14 Lock Status -AT91C_MC_LOCKS15 EQU (0x1 << 31) ;- (MC) Sector 15 Lock Status - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Serial Parallel Interface -// - ***************************************************************************** -// - -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -AT91C_SPI_SPIEN EQU (0x1 << 0) ;- (SPI) SPI Enable -AT91C_SPI_SPIDIS EQU (0x1 << 1) ;- (SPI) SPI Disable -AT91C_SPI_SWRST EQU (0x1 << 7) ;- (SPI) SPI Software reset -AT91C_SPI_LASTXFER EQU (0x1 << 24) ;- (SPI) SPI Last Transfer -// - -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -AT91C_SPI_MSTR EQU (0x1 << 0) ;- (SPI) Master/Slave Mode -AT91C_SPI_PS EQU (0x1 << 1) ;- (SPI) Peripheral Select -AT91C_SPI_PS_FIXED EQU (0x0 << 1) ;- (SPI) Fixed Peripheral Select -AT91C_SPI_PS_VARIABLE EQU (0x1 << 1) ;- (SPI) Variable Peripheral Select -AT91C_SPI_PCSDEC EQU (0x1 << 2) ;- (SPI) Chip Select Decode -AT91C_SPI_FDIV EQU (0x1 << 3) ;- (SPI) Clock Selection -AT91C_SPI_MODFDIS EQU (0x1 << 4) ;- (SPI) Mode Fault Detection -AT91C_SPI_LLB EQU (0x1 << 7) ;- (SPI) Clock Selection -AT91C_SPI_PCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select -AT91C_SPI_DLYBCS EQU (0xFF << 24) ;- (SPI) Delay Between Chip Selects -// - -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -AT91C_SPI_RD EQU (0xFFFF << 0) ;- (SPI) Receive Data -AT91C_SPI_RPCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status -// - -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -AT91C_SPI_TD EQU (0xFFFF << 0) ;- (SPI) Transmit Data -AT91C_SPI_TPCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status -// - -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -AT91C_SPI_RDRF EQU (0x1 << 0) ;- (SPI) Receive Data Register Full -AT91C_SPI_TDRE EQU (0x1 << 1) ;- (SPI) Transmit Data Register Empty -AT91C_SPI_MODF EQU (0x1 << 2) ;- (SPI) Mode Fault Error -AT91C_SPI_OVRES EQU (0x1 << 3) ;- (SPI) Overrun Error Status -AT91C_SPI_ENDRX EQU (0x1 << 4) ;- (SPI) End of Receiver Transfer -AT91C_SPI_ENDTX EQU (0x1 << 5) ;- (SPI) End of Receiver Transfer -AT91C_SPI_RXBUFF EQU (0x1 << 6) ;- (SPI) RXBUFF Interrupt -AT91C_SPI_TXBUFE EQU (0x1 << 7) ;- (SPI) TXBUFE Interrupt -AT91C_SPI_NSSR EQU (0x1 << 8) ;- (SPI) NSSR Interrupt -AT91C_SPI_TXEMPTY EQU (0x1 << 9) ;- (SPI) TXEMPTY Interrupt -AT91C_SPI_SPIENS EQU (0x1 << 16) ;- (SPI) Enable Status -// - -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// - -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// - -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// - -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -AT91C_SPI_CPOL EQU (0x1 << 0) ;- (SPI) Clock Polarity -AT91C_SPI_NCPHA EQU (0x1 << 1) ;- (SPI) Clock Phase -AT91C_SPI_CSAAT EQU (0x1 << 3) ;- (SPI) Chip Select Active After Transfer -AT91C_SPI_BITS EQU (0xF << 4) ;- (SPI) Bits Per Transfer -AT91C_SPI_BITS_8 EQU (0x0 << 4) ;- (SPI) 8 Bits Per transfer -AT91C_SPI_BITS_9 EQU (0x1 << 4) ;- (SPI) 9 Bits Per transfer -AT91C_SPI_BITS_10 EQU (0x2 << 4) ;- (SPI) 10 Bits Per transfer -AT91C_SPI_BITS_11 EQU (0x3 << 4) ;- (SPI) 11 Bits Per transfer -AT91C_SPI_BITS_12 EQU (0x4 << 4) ;- (SPI) 12 Bits Per transfer -AT91C_SPI_BITS_13 EQU (0x5 << 4) ;- (SPI) 13 Bits Per transfer -AT91C_SPI_BITS_14 EQU (0x6 << 4) ;- (SPI) 14 Bits Per transfer -AT91C_SPI_BITS_15 EQU (0x7 << 4) ;- (SPI) 15 Bits Per transfer -AT91C_SPI_BITS_16 EQU (0x8 << 4) ;- (SPI) 16 Bits Per transfer -AT91C_SPI_SCBR EQU (0xFF << 8) ;- (SPI) Serial Clock Baud Rate -AT91C_SPI_DLYBS EQU (0xFF << 16) ;- (SPI) Delay Before SPCK -AT91C_SPI_DLYBCT EQU (0xFF << 24) ;- (SPI) Delay Between Consecutive Transfers - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Usart -// - ***************************************************************************** -// - -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -AT91C_US_STTBRK EQU (0x1 << 9) ;- (USART) Start Break -AT91C_US_STPBRK EQU (0x1 << 10) ;- (USART) Stop Break -AT91C_US_STTTO EQU (0x1 << 11) ;- (USART) Start Time-out -AT91C_US_SENDA EQU (0x1 << 12) ;- (USART) Send Address -AT91C_US_RSTIT EQU (0x1 << 13) ;- (USART) Reset Iterations -AT91C_US_RSTNACK EQU (0x1 << 14) ;- (USART) Reset Non Acknowledge -AT91C_US_RETTO EQU (0x1 << 15) ;- (USART) Rearm Time-out -AT91C_US_DTREN EQU (0x1 << 16) ;- (USART) Data Terminal ready Enable -AT91C_US_DTRDIS EQU (0x1 << 17) ;- (USART) Data Terminal ready Disable -AT91C_US_RTSEN EQU (0x1 << 18) ;- (USART) Request to Send enable -AT91C_US_RTSDIS EQU (0x1 << 19) ;- (USART) Request to Send Disable -// - -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -AT91C_US_USMODE EQU (0xF << 0) ;- (USART) Usart mode -AT91C_US_USMODE_NORMAL EQU (0x0) ;- (USART) Normal -AT91C_US_USMODE_RS485 EQU (0x1) ;- (USART) RS485 -AT91C_US_USMODE_HWHSH EQU (0x2) ;- (USART) Hardware Handshaking -AT91C_US_USMODE_MODEM EQU (0x3) ;- (USART) Modem -AT91C_US_USMODE_ISO7816_0 EQU (0x4) ;- (USART) ISO7816 protocol: T = 0 -AT91C_US_USMODE_ISO7816_1 EQU (0x6) ;- (USART) ISO7816 protocol: T = 1 -AT91C_US_USMODE_IRDA EQU (0x8) ;- (USART) IrDA -AT91C_US_USMODE_SWHSH EQU (0xC) ;- (USART) Software Handshaking -AT91C_US_CLKS EQU (0x3 << 4) ;- (USART) Clock Selection (Baud Rate generator Input Clock -AT91C_US_CLKS_CLOCK EQU (0x0 << 4) ;- (USART) Clock -AT91C_US_CLKS_FDIV1 EQU (0x1 << 4) ;- (USART) fdiv1 -AT91C_US_CLKS_SLOW EQU (0x2 << 4) ;- (USART) slow_clock (ARM) -AT91C_US_CLKS_EXT EQU (0x3 << 4) ;- (USART) External (SCK) -AT91C_US_CHRL EQU (0x3 << 6) ;- (USART) Clock Selection (Baud Rate generator Input Clock -AT91C_US_CHRL_5_BITS EQU (0x0 << 6) ;- (USART) Character Length: 5 bits -AT91C_US_CHRL_6_BITS EQU (0x1 << 6) ;- (USART) Character Length: 6 bits -AT91C_US_CHRL_7_BITS EQU (0x2 << 6) ;- (USART) Character Length: 7 bits -AT91C_US_CHRL_8_BITS EQU (0x3 << 6) ;- (USART) Character Length: 8 bits -AT91C_US_SYNC EQU (0x1 << 8) ;- (USART) Synchronous Mode Select -AT91C_US_NBSTOP EQU (0x3 << 12) ;- (USART) Number of Stop bits -AT91C_US_NBSTOP_1_BIT EQU (0x0 << 12) ;- (USART) 1 stop bit -AT91C_US_NBSTOP_15_BIT EQU (0x1 << 12) ;- (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -AT91C_US_NBSTOP_2_BIT EQU (0x2 << 12) ;- (USART) 2 stop bits -AT91C_US_MSBF EQU (0x1 << 16) ;- (USART) Bit Order -AT91C_US_MODE9 EQU (0x1 << 17) ;- (USART) 9-bit Character length -AT91C_US_CKLO EQU (0x1 << 18) ;- (USART) Clock Output Select -AT91C_US_OVER EQU (0x1 << 19) ;- (USART) Over Sampling Mode -AT91C_US_INACK EQU (0x1 << 20) ;- (USART) Inhibit Non Acknowledge -AT91C_US_DSNACK EQU (0x1 << 21) ;- (USART) Disable Successive NACK -AT91C_US_MAX_ITER EQU (0x1 << 24) ;- (USART) Number of Repetitions -AT91C_US_FILTER EQU (0x1 << 28) ;- (USART) Receive Line Filter -// - -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -AT91C_US_RXBRK EQU (0x1 << 2) ;- (USART) Break Received/End of Break -AT91C_US_TIMEOUT EQU (0x1 << 8) ;- (USART) Receiver Time-out -AT91C_US_ITERATION EQU (0x1 << 10) ;- (USART) Max number of Repetitions Reached -AT91C_US_NACK EQU (0x1 << 13) ;- (USART) Non Acknowledge -AT91C_US_RIIC EQU (0x1 << 16) ;- (USART) Ring INdicator Input Change Flag -AT91C_US_DSRIC EQU (0x1 << 17) ;- (USART) Data Set Ready Input Change Flag -AT91C_US_DCDIC EQU (0x1 << 18) ;- (USART) Data Carrier Flag -AT91C_US_CTSIC EQU (0x1 << 19) ;- (USART) Clear To Send Input Change Flag -// - -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// - -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// - -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -AT91C_US_RI EQU (0x1 << 20) ;- (USART) Image of RI Input -AT91C_US_DSR EQU (0x1 << 21) ;- (USART) Image of DSR Input -AT91C_US_DCD EQU (0x1 << 22) ;- (USART) Image of DCD Input -AT91C_US_CTS EQU (0x1 << 23) ;- (USART) Image of CTS Input - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// - ***************************************************************************** -// - -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -AT91C_SSC_RXEN EQU (0x1 << 0) ;- (SSC) Receive Enable -AT91C_SSC_RXDIS EQU (0x1 << 1) ;- (SSC) Receive Disable -AT91C_SSC_TXEN EQU (0x1 << 8) ;- (SSC) Transmit Enable -AT91C_SSC_TXDIS EQU (0x1 << 9) ;- (SSC) Transmit Disable -AT91C_SSC_SWRST EQU (0x1 << 15) ;- (SSC) Software Reset -// - -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -AT91C_SSC_CKS EQU (0x3 << 0) ;- (SSC) Receive/Transmit Clock Selection -AT91C_SSC_CKS_DIV EQU (0x0) ;- (SSC) Divided Clock -AT91C_SSC_CKS_TK EQU (0x1) ;- (SSC) TK Clock signal -AT91C_SSC_CKS_RK EQU (0x2) ;- (SSC) RK pin -AT91C_SSC_CKO EQU (0x7 << 2) ;- (SSC) Receive/Transmit Clock Output Mode Selection -AT91C_SSC_CKO_NONE EQU (0x0 << 2) ;- (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -AT91C_SSC_CKO_CONTINOUS EQU (0x1 << 2) ;- (SSC) Continuous Receive/Transmit Clock RK pin: Output -AT91C_SSC_CKO_DATA_TX EQU (0x2 << 2) ;- (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -AT91C_SSC_CKI EQU (0x1 << 5) ;- (SSC) Receive/Transmit Clock Inversion -AT91C_SSC_START EQU (0xF << 8) ;- (SSC) Receive/Transmit Start Selection -AT91C_SSC_START_CONTINOUS EQU (0x0 << 8) ;- (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -AT91C_SSC_START_TX EQU (0x1 << 8) ;- (SSC) Transmit/Receive start -AT91C_SSC_START_LOW_RF EQU (0x2 << 8) ;- (SSC) Detection of a low level on RF input -AT91C_SSC_START_HIGH_RF EQU (0x3 << 8) ;- (SSC) Detection of a high level on RF input -AT91C_SSC_START_FALL_RF EQU (0x4 << 8) ;- (SSC) Detection of a falling edge on RF input -AT91C_SSC_START_RISE_RF EQU (0x5 << 8) ;- (SSC) Detection of a rising edge on RF input -AT91C_SSC_START_LEVEL_RF EQU (0x6 << 8) ;- (SSC) Detection of any level change on RF input -AT91C_SSC_START_EDGE_RF EQU (0x7 << 8) ;- (SSC) Detection of any edge on RF input -AT91C_SSC_START_0 EQU (0x8 << 8) ;- (SSC) Compare 0 -AT91C_SSC_STTDLY EQU (0xFF << 16) ;- (SSC) Receive/Transmit Start Delay -AT91C_SSC_PERIOD EQU (0xFF << 24) ;- (SSC) Receive/Transmit Period Divider Selection -// - -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -AT91C_SSC_DATLEN EQU (0x1F << 0) ;- (SSC) Data Length -AT91C_SSC_LOOP EQU (0x1 << 5) ;- (SSC) Loop Mode -AT91C_SSC_MSBF EQU (0x1 << 7) ;- (SSC) Most Significant Bit First -AT91C_SSC_DATNB EQU (0xF << 8) ;- (SSC) Data Number per Frame -AT91C_SSC_FSLEN EQU (0xF << 16) ;- (SSC) Receive/Transmit Frame Sync length -AT91C_SSC_FSOS EQU (0x7 << 20) ;- (SSC) Receive/Transmit Frame Sync Output Selection -AT91C_SSC_FSOS_NONE EQU (0x0 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -AT91C_SSC_FSOS_NEGATIVE EQU (0x1 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -AT91C_SSC_FSOS_POSITIVE EQU (0x2 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -AT91C_SSC_FSOS_LOW EQU (0x3 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -AT91C_SSC_FSOS_HIGH EQU (0x4 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -AT91C_SSC_FSOS_TOGGLE EQU (0x5 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -AT91C_SSC_FSEDGE EQU (0x1 << 24) ;- (SSC) Frame Sync Edge Detection -// - -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// - -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -AT91C_SSC_DATDEF EQU (0x1 << 5) ;- (SSC) Data Default Value -AT91C_SSC_FSDEN EQU (0x1 << 23) ;- (SSC) Frame Sync Data Enable -// - -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -AT91C_SSC_TXRDY EQU (0x1 << 0) ;- (SSC) Transmit Ready -AT91C_SSC_TXEMPTY EQU (0x1 << 1) ;- (SSC) Transmit Empty -AT91C_SSC_ENDTX EQU (0x1 << 2) ;- (SSC) End Of Transmission -AT91C_SSC_TXBUFE EQU (0x1 << 3) ;- (SSC) Transmit Buffer Empty -AT91C_SSC_RXRDY EQU (0x1 << 4) ;- (SSC) Receive Ready -AT91C_SSC_OVRUN EQU (0x1 << 5) ;- (SSC) Receive Overrun -AT91C_SSC_ENDRX EQU (0x1 << 6) ;- (SSC) End of Reception -AT91C_SSC_RXBUFF EQU (0x1 << 7) ;- (SSC) Receive Buffer Full -AT91C_SSC_TXSYN EQU (0x1 << 10) ;- (SSC) Transmit Sync -AT91C_SSC_RXSYN EQU (0x1 << 11) ;- (SSC) Receive Sync -AT91C_SSC_TXENA EQU (0x1 << 16) ;- (SSC) Transmit Enable -AT91C_SSC_RXENA EQU (0x1 << 17) ;- (SSC) Receive Enable -// - -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// - -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// - -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Two-wire Interface -// - ***************************************************************************** -// - -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -AT91C_TWI_START EQU (0x1 << 0) ;- (TWI) Send a START Condition -AT91C_TWI_STOP EQU (0x1 << 1) ;- (TWI) Send a STOP Condition -AT91C_TWI_MSEN EQU (0x1 << 2) ;- (TWI) TWI Master Transfer Enabled -AT91C_TWI_MSDIS EQU (0x1 << 3) ;- (TWI) TWI Master Transfer Disabled -AT91C_TWI_SWRST EQU (0x1 << 7) ;- (TWI) Software Reset -// - -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -AT91C_TWI_IADRSZ EQU (0x3 << 8) ;- (TWI) Internal Device Address Size -AT91C_TWI_IADRSZ_NO EQU (0x0 << 8) ;- (TWI) No internal device address -AT91C_TWI_IADRSZ_1_BYTE EQU (0x1 << 8) ;- (TWI) One-byte internal device address -AT91C_TWI_IADRSZ_2_BYTE EQU (0x2 << 8) ;- (TWI) Two-byte internal device address -AT91C_TWI_IADRSZ_3_BYTE EQU (0x3 << 8) ;- (TWI) Three-byte internal device address -AT91C_TWI_MREAD EQU (0x1 << 12) ;- (TWI) Master Read Direction -AT91C_TWI_DADR EQU (0x7F << 16) ;- (TWI) Device Address -// - -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -AT91C_TWI_CLDIV EQU (0xFF << 0) ;- (TWI) Clock Low Divider -AT91C_TWI_CHDIV EQU (0xFF << 8) ;- (TWI) Clock High Divider -AT91C_TWI_CKDIV EQU (0x7 << 16) ;- (TWI) Clock Divider -// - -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -AT91C_TWI_TXCOMP EQU (0x1 << 0) ;- (TWI) Transmission Completed -AT91C_TWI_RXRDY EQU (0x1 << 1) ;- (TWI) Receive holding register ReaDY -AT91C_TWI_TXRDY EQU (0x1 << 2) ;- (TWI) Transmit holding register ReaDY -AT91C_TWI_OVRE EQU (0x1 << 6) ;- (TWI) Overrun Error -AT91C_TWI_UNRE EQU (0x1 << 7) ;- (TWI) Underrun Error -AT91C_TWI_NACK EQU (0x1 << 8) ;- (TWI) Not Acknowledged -// - -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// - -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// - -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR PWMC Channel Interface -// - ***************************************************************************** -// - -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- -AT91C_PWMC_CPRE EQU (0xF << 0) ;- (PWMC_CH) Channel Pre-scaler : PWMC_CLKx -AT91C_PWMC_CPRE_MCK EQU (0x0) ;- (PWMC_CH) -AT91C_PWMC_CPRE_MCKA EQU (0xB) ;- (PWMC_CH) -AT91C_PWMC_CPRE_MCKB EQU (0xC) ;- (PWMC_CH) -AT91C_PWMC_CALG EQU (0x1 << 8) ;- (PWMC_CH) Channel Alignment -AT91C_PWMC_CPOL EQU (0x1 << 9) ;- (PWMC_CH) Channel Polarity -AT91C_PWMC_CPD EQU (0x1 << 10) ;- (PWMC_CH) Channel Update Period -// - -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- -AT91C_PWMC_CDTY EQU (0x0 << 0) ;- (PWMC_CH) Channel Duty Cycle -// - -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- -AT91C_PWMC_CPRD EQU (0x0 << 0) ;- (PWMC_CH) Channel Period -// - -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- -AT91C_PWMC_CCNT EQU (0x0 << 0) ;- (PWMC_CH) Channel Counter -// - -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- -AT91C_PWMC_CUPD EQU (0x0 << 0) ;- (PWMC_CH) Channel Update - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface -// - ***************************************************************************** -// - -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- -AT91C_PWMC_DIVA EQU (0xFF << 0) ;- (PWMC) CLKA divide factor. -AT91C_PWMC_PREA EQU (0xF << 8) ;- (PWMC) Divider Input Clock Prescaler A -AT91C_PWMC_PREA_MCK EQU (0x0 << 8) ;- (PWMC) -AT91C_PWMC_DIVB EQU (0xFF << 16) ;- (PWMC) CLKB divide factor. -AT91C_PWMC_PREB EQU (0xF << 24) ;- (PWMC) Divider Input Clock Prescaler B -AT91C_PWMC_PREB_MCK EQU (0x0 << 24) ;- (PWMC) -// - -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- -AT91C_PWMC_CHID0 EQU (0x1 << 0) ;- (PWMC) Channel ID 0 -AT91C_PWMC_CHID1 EQU (0x1 << 1) ;- (PWMC) Channel ID 1 -AT91C_PWMC_CHID2 EQU (0x1 << 2) ;- (PWMC) Channel ID 2 -AT91C_PWMC_CHID3 EQU (0x1 << 3) ;- (PWMC) Channel ID 3 -// - -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- -// - -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- -// - -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- -// - -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- -// - -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- -// - -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR USB Device Interface -// - ***************************************************************************** -// - -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -AT91C_UDP_FRM_NUM EQU (0x7FF << 0) ;- (UDP) Frame Number as Defined in the Packet Field Formats -AT91C_UDP_FRM_ERR EQU (0x1 << 16) ;- (UDP) Frame Error -AT91C_UDP_FRM_OK EQU (0x1 << 17) ;- (UDP) Frame OK -// - -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -AT91C_UDP_FADDEN EQU (0x1 << 0) ;- (UDP) Function Address Enable -AT91C_UDP_CONFG EQU (0x1 << 1) ;- (UDP) Configured -AT91C_UDP_ESR EQU (0x1 << 2) ;- (UDP) Enable Send Resume -AT91C_UDP_RSMINPR EQU (0x1 << 3) ;- (UDP) A Resume Has Been Sent to the Host -AT91C_UDP_RMWUPE EQU (0x1 << 4) ;- (UDP) Remote Wake Up Enable -// - -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -AT91C_UDP_FADD EQU (0xFF << 0) ;- (UDP) Function Address Value -AT91C_UDP_FEN EQU (0x1 << 8) ;- (UDP) Function Enable -// - -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -AT91C_UDP_EPINT0 EQU (0x1 << 0) ;- (UDP) Endpoint 0 Interrupt -AT91C_UDP_EPINT1 EQU (0x1 << 1) ;- (UDP) Endpoint 0 Interrupt -AT91C_UDP_EPINT2 EQU (0x1 << 2) ;- (UDP) Endpoint 2 Interrupt -AT91C_UDP_EPINT3 EQU (0x1 << 3) ;- (UDP) Endpoint 3 Interrupt -AT91C_UDP_EPINT4 EQU (0x1 << 4) ;- (UDP) Endpoint 4 Interrupt -AT91C_UDP_EPINT5 EQU (0x1 << 5) ;- (UDP) Endpoint 5 Interrupt -AT91C_UDP_RXSUSP EQU (0x1 << 8) ;- (UDP) USB Suspend Interrupt -AT91C_UDP_RXRSM EQU (0x1 << 9) ;- (UDP) USB Resume Interrupt -AT91C_UDP_EXTRSM EQU (0x1 << 10) ;- (UDP) USB External Resume Interrupt -AT91C_UDP_SOFINT EQU (0x1 << 11) ;- (UDP) USB Start Of frame Interrupt -AT91C_UDP_WAKEUP EQU (0x1 << 13) ;- (UDP) USB Resume Interrupt -// - -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// - -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// - -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -AT91C_UDP_ENDBUSRES EQU (0x1 << 12) ;- (UDP) USB End Of Bus Reset Interrupt -// - -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// - -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -AT91C_UDP_EP0 EQU (0x1 << 0) ;- (UDP) Reset Endpoint 0 -AT91C_UDP_EP1 EQU (0x1 << 1) ;- (UDP) Reset Endpoint 1 -AT91C_UDP_EP2 EQU (0x1 << 2) ;- (UDP) Reset Endpoint 2 -AT91C_UDP_EP3 EQU (0x1 << 3) ;- (UDP) Reset Endpoint 3 -AT91C_UDP_EP4 EQU (0x1 << 4) ;- (UDP) Reset Endpoint 4 -AT91C_UDP_EP5 EQU (0x1 << 5) ;- (UDP) Reset Endpoint 5 -// - -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -AT91C_UDP_TXCOMP EQU (0x1 << 0) ;- (UDP) Generates an IN packet with data previously written in the DPR -AT91C_UDP_RX_DATA_BK0 EQU (0x1 << 1) ;- (UDP) Receive Data Bank 0 -AT91C_UDP_RXSETUP EQU (0x1 << 2) ;- (UDP) Sends STALL to the Host (Control endpoints) -AT91C_UDP_ISOERROR EQU (0x1 << 3) ;- (UDP) Isochronous error (Isochronous endpoints) -AT91C_UDP_TXPKTRDY EQU (0x1 << 4) ;- (UDP) Transmit Packet Ready -AT91C_UDP_FORCESTALL EQU (0x1 << 5) ;- (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -AT91C_UDP_RX_DATA_BK1 EQU (0x1 << 6) ;- (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -AT91C_UDP_DIR EQU (0x1 << 7) ;- (UDP) Transfer Direction -AT91C_UDP_EPTYPE EQU (0x7 << 8) ;- (UDP) Endpoint type -AT91C_UDP_EPTYPE_CTRL EQU (0x0 << 8) ;- (UDP) Control -AT91C_UDP_EPTYPE_ISO_OUT EQU (0x1 << 8) ;- (UDP) Isochronous OUT -AT91C_UDP_EPTYPE_BULK_OUT EQU (0x2 << 8) ;- (UDP) Bulk OUT -AT91C_UDP_EPTYPE_INT_OUT EQU (0x3 << 8) ;- (UDP) Interrupt OUT -AT91C_UDP_EPTYPE_ISO_IN EQU (0x5 << 8) ;- (UDP) Isochronous IN -AT91C_UDP_EPTYPE_BULK_IN EQU (0x6 << 8) ;- (UDP) Bulk IN -AT91C_UDP_EPTYPE_INT_IN EQU (0x7 << 8) ;- (UDP) Interrupt IN -AT91C_UDP_DTGLE EQU (0x1 << 11) ;- (UDP) Data Toggle -AT91C_UDP_EPEDS EQU (0x1 << 15) ;- (UDP) Endpoint Enable Disable -AT91C_UDP_RXBYTECNT EQU (0x7FF << 16) ;- (UDP) Number Of Bytes Available in the FIFO -// - -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- -AT91C_UDP_TXVDIS EQU (0x1 << 8) ;- (UDP) -AT91C_UDP_PUON EQU (0x1 << 9) ;- (UDP) Pull-up ON - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// - ***************************************************************************** -// - -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -AT91C_TC_CLKEN EQU (0x1 << 0) ;- (TC) Counter Clock Enable Command -AT91C_TC_CLKDIS EQU (0x1 << 1) ;- (TC) Counter Clock Disable Command -AT91C_TC_SWTRG EQU (0x1 << 2) ;- (TC) Software Trigger Command -// - -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -AT91C_TC_CLKS EQU (0x7 << 0) ;- (TC) Clock Selection -AT91C_TC_CLKS_TIMER_DIV1_CLOCK EQU (0x0) ;- (TC) Clock selected: TIMER_DIV1_CLOCK -AT91C_TC_CLKS_TIMER_DIV2_CLOCK EQU (0x1) ;- (TC) Clock selected: TIMER_DIV2_CLOCK -AT91C_TC_CLKS_TIMER_DIV3_CLOCK EQU (0x2) ;- (TC) Clock selected: TIMER_DIV3_CLOCK -AT91C_TC_CLKS_TIMER_DIV4_CLOCK EQU (0x3) ;- (TC) Clock selected: TIMER_DIV4_CLOCK -AT91C_TC_CLKS_TIMER_DIV5_CLOCK EQU (0x4) ;- (TC) Clock selected: TIMER_DIV5_CLOCK -AT91C_TC_CLKS_XC0 EQU (0x5) ;- (TC) Clock selected: XC0 -AT91C_TC_CLKS_XC1 EQU (0x6) ;- (TC) Clock selected: XC1 -AT91C_TC_CLKS_XC2 EQU (0x7) ;- (TC) Clock selected: XC2 -AT91C_TC_CLKI EQU (0x1 << 3) ;- (TC) Clock Invert -AT91C_TC_BURST EQU (0x3 << 4) ;- (TC) Burst Signal Selection -AT91C_TC_BURST_NONE EQU (0x0 << 4) ;- (TC) The clock is not gated by an external signal -AT91C_TC_BURST_XC0 EQU (0x1 << 4) ;- (TC) XC0 is ANDed with the selected clock -AT91C_TC_BURST_XC1 EQU (0x2 << 4) ;- (TC) XC1 is ANDed with the selected clock -AT91C_TC_BURST_XC2 EQU (0x3 << 4) ;- (TC) XC2 is ANDed with the selected clock -AT91C_TC_CPCSTOP EQU (0x1 << 6) ;- (TC) Counter Clock Stopped with RC Compare -AT91C_TC_LDBSTOP EQU (0x1 << 6) ;- (TC) Counter Clock Stopped with RB Loading -AT91C_TC_CPCDIS EQU (0x1 << 7) ;- (TC) Counter Clock Disable with RC Compare -AT91C_TC_LDBDIS EQU (0x1 << 7) ;- (TC) Counter Clock Disabled with RB Loading -AT91C_TC_ETRGEDG EQU (0x3 << 8) ;- (TC) External Trigger Edge Selection -AT91C_TC_ETRGEDG_NONE EQU (0x0 << 8) ;- (TC) Edge: None -AT91C_TC_ETRGEDG_RISING EQU (0x1 << 8) ;- (TC) Edge: rising edge -AT91C_TC_ETRGEDG_FALLING EQU (0x2 << 8) ;- (TC) Edge: falling edge -AT91C_TC_ETRGEDG_BOTH EQU (0x3 << 8) ;- (TC) Edge: each edge -AT91C_TC_EEVTEDG EQU (0x3 << 8) ;- (TC) External Event Edge Selection -AT91C_TC_EEVTEDG_NONE EQU (0x0 << 8) ;- (TC) Edge: None -AT91C_TC_EEVTEDG_RISING EQU (0x1 << 8) ;- (TC) Edge: rising edge -AT91C_TC_EEVTEDG_FALLING EQU (0x2 << 8) ;- (TC) Edge: falling edge -AT91C_TC_EEVTEDG_BOTH EQU (0x3 << 8) ;- (TC) Edge: each edge -AT91C_TC_EEVT EQU (0x3 << 10) ;- (TC) External Event Selection -AT91C_TC_EEVT_TIOB EQU (0x0 << 10) ;- (TC) Signal selected as external event: TIOB TIOB direction: input -AT91C_TC_EEVT_XC0 EQU (0x1 << 10) ;- (TC) Signal selected as external event: XC0 TIOB direction: output -AT91C_TC_EEVT_XC1 EQU (0x2 << 10) ;- (TC) Signal selected as external event: XC1 TIOB direction: output -AT91C_TC_EEVT_XC2 EQU (0x3 << 10) ;- (TC) Signal selected as external event: XC2 TIOB direction: output -AT91C_TC_ABETRG EQU (0x1 << 10) ;- (TC) TIOA or TIOB External Trigger Selection -AT91C_TC_ENETRG EQU (0x1 << 12) ;- (TC) External Event Trigger enable -AT91C_TC_WAVESEL EQU (0x3 << 13) ;- (TC) Waveform Selection -AT91C_TC_WAVESEL_UP EQU (0x0 << 13) ;- (TC) UP mode without atomatic trigger on RC Compare -AT91C_TC_WAVESEL_UPDOWN EQU (0x1 << 13) ;- (TC) UPDOWN mode without automatic trigger on RC Compare -AT91C_TC_WAVESEL_UP_AUTO EQU (0x2 << 13) ;- (TC) UP mode with automatic trigger on RC Compare -AT91C_TC_WAVESEL_UPDOWN_AUTO EQU (0x3 << 13) ;- (TC) UPDOWN mode with automatic trigger on RC Compare -AT91C_TC_CPCTRG EQU (0x1 << 14) ;- (TC) RC Compare Trigger Enable -AT91C_TC_WAVE EQU (0x1 << 15) ;- (TC) -AT91C_TC_ACPA EQU (0x3 << 16) ;- (TC) RA Compare Effect on TIOA -AT91C_TC_ACPA_NONE EQU (0x0 << 16) ;- (TC) Effect: none -AT91C_TC_ACPA_SET EQU (0x1 << 16) ;- (TC) Effect: set -AT91C_TC_ACPA_CLEAR EQU (0x2 << 16) ;- (TC) Effect: clear -AT91C_TC_ACPA_TOGGLE EQU (0x3 << 16) ;- (TC) Effect: toggle -AT91C_TC_LDRA EQU (0x3 << 16) ;- (TC) RA Loading Selection -AT91C_TC_LDRA_NONE EQU (0x0 << 16) ;- (TC) Edge: None -AT91C_TC_LDRA_RISING EQU (0x1 << 16) ;- (TC) Edge: rising edge of TIOA -AT91C_TC_LDRA_FALLING EQU (0x2 << 16) ;- (TC) Edge: falling edge of TIOA -AT91C_TC_LDRA_BOTH EQU (0x3 << 16) ;- (TC) Edge: each edge of TIOA -AT91C_TC_ACPC EQU (0x3 << 18) ;- (TC) RC Compare Effect on TIOA -AT91C_TC_ACPC_NONE EQU (0x0 << 18) ;- (TC) Effect: none -AT91C_TC_ACPC_SET EQU (0x1 << 18) ;- (TC) Effect: set -AT91C_TC_ACPC_CLEAR EQU (0x2 << 18) ;- (TC) Effect: clear -AT91C_TC_ACPC_TOGGLE EQU (0x3 << 18) ;- (TC) Effect: toggle -AT91C_TC_LDRB EQU (0x3 << 18) ;- (TC) RB Loading Selection -AT91C_TC_LDRB_NONE EQU (0x0 << 18) ;- (TC) Edge: None -AT91C_TC_LDRB_RISING EQU (0x1 << 18) ;- (TC) Edge: rising edge of TIOA -AT91C_TC_LDRB_FALLING EQU (0x2 << 18) ;- (TC) Edge: falling edge of TIOA -AT91C_TC_LDRB_BOTH EQU (0x3 << 18) ;- (TC) Edge: each edge of TIOA -AT91C_TC_AEEVT EQU (0x3 << 20) ;- (TC) External Event Effect on TIOA -AT91C_TC_AEEVT_NONE EQU (0x0 << 20) ;- (TC) Effect: none -AT91C_TC_AEEVT_SET EQU (0x1 << 20) ;- (TC) Effect: set -AT91C_TC_AEEVT_CLEAR EQU (0x2 << 20) ;- (TC) Effect: clear -AT91C_TC_AEEVT_TOGGLE EQU (0x3 << 20) ;- (TC) Effect: toggle -AT91C_TC_ASWTRG EQU (0x3 << 22) ;- (TC) Software Trigger Effect on TIOA -AT91C_TC_ASWTRG_NONE EQU (0x0 << 22) ;- (TC) Effect: none -AT91C_TC_ASWTRG_SET EQU (0x1 << 22) ;- (TC) Effect: set -AT91C_TC_ASWTRG_CLEAR EQU (0x2 << 22) ;- (TC) Effect: clear -AT91C_TC_ASWTRG_TOGGLE EQU (0x3 << 22) ;- (TC) Effect: toggle -AT91C_TC_BCPB EQU (0x3 << 24) ;- (TC) RB Compare Effect on TIOB -AT91C_TC_BCPB_NONE EQU (0x0 << 24) ;- (TC) Effect: none -AT91C_TC_BCPB_SET EQU (0x1 << 24) ;- (TC) Effect: set -AT91C_TC_BCPB_CLEAR EQU (0x2 << 24) ;- (TC) Effect: clear -AT91C_TC_BCPB_TOGGLE EQU (0x3 << 24) ;- (TC) Effect: toggle -AT91C_TC_BCPC EQU (0x3 << 26) ;- (TC) RC Compare Effect on TIOB -AT91C_TC_BCPC_NONE EQU (0x0 << 26) ;- (TC) Effect: none -AT91C_TC_BCPC_SET EQU (0x1 << 26) ;- (TC) Effect: set -AT91C_TC_BCPC_CLEAR EQU (0x2 << 26) ;- (TC) Effect: clear -AT91C_TC_BCPC_TOGGLE EQU (0x3 << 26) ;- (TC) Effect: toggle -AT91C_TC_BEEVT EQU (0x3 << 28) ;- (TC) External Event Effect on TIOB -AT91C_TC_BEEVT_NONE EQU (0x0 << 28) ;- (TC) Effect: none -AT91C_TC_BEEVT_SET EQU (0x1 << 28) ;- (TC) Effect: set -AT91C_TC_BEEVT_CLEAR EQU (0x2 << 28) ;- (TC) Effect: clear -AT91C_TC_BEEVT_TOGGLE EQU (0x3 << 28) ;- (TC) Effect: toggle -AT91C_TC_BSWTRG EQU (0x3 << 30) ;- (TC) Software Trigger Effect on TIOB -AT91C_TC_BSWTRG_NONE EQU (0x0 << 30) ;- (TC) Effect: none -AT91C_TC_BSWTRG_SET EQU (0x1 << 30) ;- (TC) Effect: set -AT91C_TC_BSWTRG_CLEAR EQU (0x2 << 30) ;- (TC) Effect: clear -AT91C_TC_BSWTRG_TOGGLE EQU (0x3 << 30) ;- (TC) Effect: toggle -// - -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -AT91C_TC_COVFS EQU (0x1 << 0) ;- (TC) Counter Overflow -AT91C_TC_LOVRS EQU (0x1 << 1) ;- (TC) Load Overrun -AT91C_TC_CPAS EQU (0x1 << 2) ;- (TC) RA Compare -AT91C_TC_CPBS EQU (0x1 << 3) ;- (TC) RB Compare -AT91C_TC_CPCS EQU (0x1 << 4) ;- (TC) RC Compare -AT91C_TC_LDRAS EQU (0x1 << 5) ;- (TC) RA Loading -AT91C_TC_LDRBS EQU (0x1 << 6) ;- (TC) RB Loading -AT91C_TC_ETRGS EQU (0x1 << 7) ;- (TC) External Trigger -AT91C_TC_CLKSTA EQU (0x1 << 16) ;- (TC) Clock Enabling -AT91C_TC_MTIOA EQU (0x1 << 17) ;- (TC) TIOA Mirror -AT91C_TC_MTIOB EQU (0x1 << 18) ;- (TC) TIOA Mirror -// - -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// - -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// - -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Timer Counter Interface -// - ***************************************************************************** -// - -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -AT91C_TCB_SYNC EQU (0x1 << 0) ;- (TCB) Synchro Command -// - -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -AT91C_TCB_TC0XC0S EQU (0x3 << 0) ;- (TCB) External Clock Signal 0 Selection -AT91C_TCB_TC0XC0S_TCLK0 EQU (0x0) ;- (TCB) TCLK0 connected to XC0 -AT91C_TCB_TC0XC0S_NONE EQU (0x1) ;- (TCB) None signal connected to XC0 -AT91C_TCB_TC0XC0S_TIOA1 EQU (0x2) ;- (TCB) TIOA1 connected to XC0 -AT91C_TCB_TC0XC0S_TIOA2 EQU (0x3) ;- (TCB) TIOA2 connected to XC0 -AT91C_TCB_TC1XC1S EQU (0x3 << 2) ;- (TCB) External Clock Signal 1 Selection -AT91C_TCB_TC1XC1S_TCLK1 EQU (0x0 << 2) ;- (TCB) TCLK1 connected to XC1 -AT91C_TCB_TC1XC1S_NONE EQU (0x1 << 2) ;- (TCB) None signal connected to XC1 -AT91C_TCB_TC1XC1S_TIOA0 EQU (0x2 << 2) ;- (TCB) TIOA0 connected to XC1 -AT91C_TCB_TC1XC1S_TIOA2 EQU (0x3 << 2) ;- (TCB) TIOA2 connected to XC1 -AT91C_TCB_TC2XC2S EQU (0x3 << 4) ;- (TCB) External Clock Signal 2 Selection -AT91C_TCB_TC2XC2S_TCLK2 EQU (0x0 << 4) ;- (TCB) TCLK2 connected to XC2 -AT91C_TCB_TC2XC2S_NONE EQU (0x1 << 4) ;- (TCB) None signal connected to XC2 -AT91C_TCB_TC2XC2S_TIOA0 EQU (0x2 << 4) ;- (TCB) TIOA0 connected to XC2 -AT91C_TCB_TC2XC2S_TIOA1 EQU (0x3 << 4) ;- (TCB) TIOA2 connected to XC2 - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface -// - ***************************************************************************** -// - -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- -AT91C_CAN_MTIMEMARK EQU (0xFFFF << 0) ;- (CAN_MB) Mailbox Timemark -AT91C_CAN_PRIOR EQU (0xF << 16) ;- (CAN_MB) Mailbox Priority -AT91C_CAN_MOT EQU (0x7 << 24) ;- (CAN_MB) Mailbox Object Type -AT91C_CAN_MOT_DIS EQU (0x0 << 24) ;- (CAN_MB) -AT91C_CAN_MOT_RX EQU (0x1 << 24) ;- (CAN_MB) -AT91C_CAN_MOT_RXOVERWRITE EQU (0x2 << 24) ;- (CAN_MB) -AT91C_CAN_MOT_TX EQU (0x3 << 24) ;- (CAN_MB) -AT91C_CAN_MOT_CONSUMER EQU (0x4 << 24) ;- (CAN_MB) -AT91C_CAN_MOT_PRODUCER EQU (0x5 << 24) ;- (CAN_MB) -// - -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- -AT91C_CAN_MIDvB EQU (0x3FFFF << 0) ;- (CAN_MB) Complementary bits for identifier in extended mode -AT91C_CAN_MIDvA EQU (0x7FF << 18) ;- (CAN_MB) Identifier for standard frame mode -AT91C_CAN_MIDE EQU (0x1 << 29) ;- (CAN_MB) Identifier Version -// - -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- -// - -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- -// - -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- -AT91C_CAN_MTIMESTAMP EQU (0xFFFF << 0) ;- (CAN_MB) Timer Value -AT91C_CAN_MDLC EQU (0xF << 16) ;- (CAN_MB) Mailbox Data Length Code -AT91C_CAN_MRTR EQU (0x1 << 20) ;- (CAN_MB) Mailbox Remote Transmission Request -AT91C_CAN_MABT EQU (0x1 << 22) ;- (CAN_MB) Mailbox Message Abort -AT91C_CAN_MRDY EQU (0x1 << 23) ;- (CAN_MB) Mailbox Ready -AT91C_CAN_MMI EQU (0x1 << 24) ;- (CAN_MB) Mailbox Message Ignored -// - -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- -// - -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- -// - -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- -AT91C_CAN_MACR EQU (0x1 << 22) ;- (CAN_MB) Abort Request for Mailbox -AT91C_CAN_MTCR EQU (0x1 << 23) ;- (CAN_MB) Mailbox Transfer Command - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Control Area Network Interface -// - ***************************************************************************** -// - -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- -AT91C_CAN_CANEN EQU (0x1 << 0) ;- (CAN) CAN Controller Enable -AT91C_CAN_LPM EQU (0x1 << 1) ;- (CAN) Disable/Enable Low Power Mode -AT91C_CAN_ABM EQU (0x1 << 2) ;- (CAN) Disable/Enable Autobaud/Listen Mode -AT91C_CAN_OVL EQU (0x1 << 3) ;- (CAN) Disable/Enable Overload Frame -AT91C_CAN_TEOF EQU (0x1 << 4) ;- (CAN) Time Stamp messages at each end of Frame -AT91C_CAN_TTM EQU (0x1 << 5) ;- (CAN) Disable/Enable Time Trigger Mode -AT91C_CAN_TIMFRZ EQU (0x1 << 6) ;- (CAN) Enable Timer Freeze -AT91C_CAN_DRPT EQU (0x1 << 7) ;- (CAN) Disable Repeat -// - -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- -AT91C_CAN_MB0 EQU (0x1 << 0) ;- (CAN) Mailbox 0 Flag -AT91C_CAN_MB1 EQU (0x1 << 1) ;- (CAN) Mailbox 1 Flag -AT91C_CAN_MB2 EQU (0x1 << 2) ;- (CAN) Mailbox 2 Flag -AT91C_CAN_MB3 EQU (0x1 << 3) ;- (CAN) Mailbox 3 Flag -AT91C_CAN_MB4 EQU (0x1 << 4) ;- (CAN) Mailbox 4 Flag -AT91C_CAN_MB5 EQU (0x1 << 5) ;- (CAN) Mailbox 5 Flag -AT91C_CAN_MB6 EQU (0x1 << 6) ;- (CAN) Mailbox 6 Flag -AT91C_CAN_MB7 EQU (0x1 << 7) ;- (CAN) Mailbox 7 Flag -AT91C_CAN_MB8 EQU (0x1 << 8) ;- (CAN) Mailbox 8 Flag -AT91C_CAN_MB9 EQU (0x1 << 9) ;- (CAN) Mailbox 9 Flag -AT91C_CAN_MB10 EQU (0x1 << 10) ;- (CAN) Mailbox 10 Flag -AT91C_CAN_MB11 EQU (0x1 << 11) ;- (CAN) Mailbox 11 Flag -AT91C_CAN_MB12 EQU (0x1 << 12) ;- (CAN) Mailbox 12 Flag -AT91C_CAN_MB13 EQU (0x1 << 13) ;- (CAN) Mailbox 13 Flag -AT91C_CAN_MB14 EQU (0x1 << 14) ;- (CAN) Mailbox 14 Flag -AT91C_CAN_MB15 EQU (0x1 << 15) ;- (CAN) Mailbox 15 Flag -AT91C_CAN_ERRA EQU (0x1 << 16) ;- (CAN) Error Active Mode Flag -AT91C_CAN_WARN EQU (0x1 << 17) ;- (CAN) Warning Limit Flag -AT91C_CAN_ERRP EQU (0x1 << 18) ;- (CAN) Error Passive Mode Flag -AT91C_CAN_BOFF EQU (0x1 << 19) ;- (CAN) Bus Off Mode Flag -AT91C_CAN_SLEEP EQU (0x1 << 20) ;- (CAN) Sleep Flag -AT91C_CAN_WAKEUP EQU (0x1 << 21) ;- (CAN) Wakeup Flag -AT91C_CAN_TOVF EQU (0x1 << 22) ;- (CAN) Timer Overflow Flag -AT91C_CAN_TSTP EQU (0x1 << 23) ;- (CAN) Timestamp Flag -AT91C_CAN_CERR EQU (0x1 << 24) ;- (CAN) CRC Error -AT91C_CAN_SERR EQU (0x1 << 25) ;- (CAN) Stuffing Error -AT91C_CAN_AERR EQU (0x1 << 26) ;- (CAN) Acknowledgment Error -AT91C_CAN_FERR EQU (0x1 << 27) ;- (CAN) Form Error -AT91C_CAN_BERR EQU (0x1 << 28) ;- (CAN) Bit Error -// - -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- -// - -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- -// - -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- -AT91C_CAN_RBSY EQU (0x1 << 29) ;- (CAN) Receiver Busy -AT91C_CAN_TBSY EQU (0x1 << 30) ;- (CAN) Transmitter Busy -AT91C_CAN_OVLY EQU (0x1 << 31) ;- (CAN) Overload Busy -// - -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- -AT91C_CAN_PHASE2 EQU (0x7 << 0) ;- (CAN) Phase 2 segment -AT91C_CAN_PHASE1 EQU (0x7 << 4) ;- (CAN) Phase 1 segment -AT91C_CAN_PROPAG EQU (0x7 << 8) ;- (CAN) Programmation time segment -AT91C_CAN_SYNC EQU (0x3 << 12) ;- (CAN) Re-synchronization jump width segment -AT91C_CAN_BRP EQU (0x7F << 16) ;- (CAN) Baudrate Prescaler -AT91C_CAN_SMP EQU (0x1 << 24) ;- (CAN) Sampling mode -// - -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- -AT91C_CAN_TIMER EQU (0xFFFF << 0) ;- (CAN) Timer field -// - -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- -// - -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- -AT91C_CAN_REC EQU (0xFF << 0) ;- (CAN) Receive Error Counter -AT91C_CAN_TEC EQU (0xFF << 16) ;- (CAN) Transmit Error Counter -// - -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- -AT91C_CAN_TIMRST EQU (0x1 << 31) ;- (CAN) Timer Reset Field -// - -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 -// - ***************************************************************************** -// - -------- EMAC_NCR : (EMAC Offset: 0x0) -------- -AT91C_EMAC_LB EQU (0x1 << 0) ;- (EMAC) Loopback. Optional. When set, loopback signal is at high level. -AT91C_EMAC_LLB EQU (0x1 << 1) ;- (EMAC) Loopback local. -AT91C_EMAC_RE EQU (0x1 << 2) ;- (EMAC) Receive enable. -AT91C_EMAC_TE EQU (0x1 << 3) ;- (EMAC) Transmit enable. -AT91C_EMAC_MPE EQU (0x1 << 4) ;- (EMAC) Management port enable. -AT91C_EMAC_CLRSTAT EQU (0x1 << 5) ;- (EMAC) Clear statistics registers. -AT91C_EMAC_INCSTAT EQU (0x1 << 6) ;- (EMAC) Increment statistics registers. -AT91C_EMAC_WESTAT EQU (0x1 << 7) ;- (EMAC) Write enable for statistics registers. -AT91C_EMAC_BP EQU (0x1 << 8) ;- (EMAC) Back pressure. -AT91C_EMAC_TSTART EQU (0x1 << 9) ;- (EMAC) Start Transmission. -AT91C_EMAC_THALT EQU (0x1 << 10) ;- (EMAC) Transmission Halt. -AT91C_EMAC_TPFR EQU (0x1 << 11) ;- (EMAC) Transmit pause frame -AT91C_EMAC_TZQ EQU (0x1 << 12) ;- (EMAC) Transmit zero quantum pause frame -// - -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- -AT91C_EMAC_SPD EQU (0x1 << 0) ;- (EMAC) Speed. -AT91C_EMAC_FD EQU (0x1 << 1) ;- (EMAC) Full duplex. -AT91C_EMAC_JFRAME EQU (0x1 << 3) ;- (EMAC) Jumbo Frames. -AT91C_EMAC_CAF EQU (0x1 << 4) ;- (EMAC) Copy all frames. -AT91C_EMAC_NBC EQU (0x1 << 5) ;- (EMAC) No broadcast. -AT91C_EMAC_MTI EQU (0x1 << 6) ;- (EMAC) Multicast hash event enable -AT91C_EMAC_UNI EQU (0x1 << 7) ;- (EMAC) Unicast hash enable. -AT91C_EMAC_BIG EQU (0x1 << 8) ;- (EMAC) Receive 1522 bytes. -AT91C_EMAC_EAE EQU (0x1 << 9) ;- (EMAC) External address match enable. -AT91C_EMAC_CLK EQU (0x3 << 10) ;- (EMAC) -AT91C_EMAC_CLK_HCLK_8 EQU (0x0 << 10) ;- (EMAC) HCLK divided by 8 -AT91C_EMAC_CLK_HCLK_16 EQU (0x1 << 10) ;- (EMAC) HCLK divided by 16 -AT91C_EMAC_CLK_HCLK_32 EQU (0x2 << 10) ;- (EMAC) HCLK divided by 32 -AT91C_EMAC_CLK_HCLK_64 EQU (0x3 << 10) ;- (EMAC) HCLK divided by 64 -AT91C_EMAC_RTY EQU (0x1 << 12) ;- (EMAC) -AT91C_EMAC_PAE EQU (0x1 << 13) ;- (EMAC) -AT91C_EMAC_RBOF EQU (0x3 << 14) ;- (EMAC) -AT91C_EMAC_RBOF_OFFSET_0 EQU (0x0 << 14) ;- (EMAC) no offset from start of receive buffer -AT91C_EMAC_RBOF_OFFSET_1 EQU (0x1 << 14) ;- (EMAC) one byte offset from start of receive buffer -AT91C_EMAC_RBOF_OFFSET_2 EQU (0x2 << 14) ;- (EMAC) two bytes offset from start of receive buffer -AT91C_EMAC_RBOF_OFFSET_3 EQU (0x3 << 14) ;- (EMAC) three bytes offset from start of receive buffer -AT91C_EMAC_RLCE EQU (0x1 << 16) ;- (EMAC) Receive Length field Checking Enable -AT91C_EMAC_DRFCS EQU (0x1 << 17) ;- (EMAC) Discard Receive FCS -AT91C_EMAC_EFRHD EQU (0x1 << 18) ;- (EMAC) -AT91C_EMAC_IRXFCS EQU (0x1 << 19) ;- (EMAC) Ignore RX FCS -// - -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- -AT91C_EMAC_LINKR EQU (0x1 << 0) ;- (EMAC) -AT91C_EMAC_MDIO EQU (0x1 << 1) ;- (EMAC) -AT91C_EMAC_IDLE EQU (0x1 << 2) ;- (EMAC) -// - -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- -AT91C_EMAC_UBR EQU (0x1 << 0) ;- (EMAC) -AT91C_EMAC_COL EQU (0x1 << 1) ;- (EMAC) -AT91C_EMAC_RLES EQU (0x1 << 2) ;- (EMAC) -AT91C_EMAC_TGO EQU (0x1 << 3) ;- (EMAC) Transmit Go -AT91C_EMAC_BEX EQU (0x1 << 4) ;- (EMAC) Buffers exhausted mid frame -AT91C_EMAC_COMP EQU (0x1 << 5) ;- (EMAC) -AT91C_EMAC_UND EQU (0x1 << 6) ;- (EMAC) -// - -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- -AT91C_EMAC_BNA EQU (0x1 << 0) ;- (EMAC) -AT91C_EMAC_REC EQU (0x1 << 1) ;- (EMAC) -AT91C_EMAC_OVR EQU (0x1 << 2) ;- (EMAC) -// - -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- -AT91C_EMAC_MFD EQU (0x1 << 0) ;- (EMAC) -AT91C_EMAC_RCOMP EQU (0x1 << 1) ;- (EMAC) -AT91C_EMAC_RXUBR EQU (0x1 << 2) ;- (EMAC) -AT91C_EMAC_TXUBR EQU (0x1 << 3) ;- (EMAC) -AT91C_EMAC_TUNDR EQU (0x1 << 4) ;- (EMAC) -AT91C_EMAC_RLEX EQU (0x1 << 5) ;- (EMAC) -AT91C_EMAC_TXERR EQU (0x1 << 6) ;- (EMAC) -AT91C_EMAC_TCOMP EQU (0x1 << 7) ;- (EMAC) -AT91C_EMAC_LINK EQU (0x1 << 9) ;- (EMAC) -AT91C_EMAC_ROVR EQU (0x1 << 10) ;- (EMAC) -AT91C_EMAC_HRESP EQU (0x1 << 11) ;- (EMAC) -AT91C_EMAC_PFRE EQU (0x1 << 12) ;- (EMAC) -AT91C_EMAC_PTZ EQU (0x1 << 13) ;- (EMAC) -// - -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- -// - -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- -// - -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- -// - -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- -AT91C_EMAC_DATA EQU (0xFFFF << 0) ;- (EMAC) -AT91C_EMAC_CODE EQU (0x3 << 16) ;- (EMAC) -AT91C_EMAC_REGA EQU (0x1F << 18) ;- (EMAC) -AT91C_EMAC_PHYA EQU (0x1F << 23) ;- (EMAC) -AT91C_EMAC_RW EQU (0x3 << 28) ;- (EMAC) -AT91C_EMAC_SOF EQU (0x3 << 30) ;- (EMAC) -// - -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- -AT91C_EMAC_RMII EQU (0x1 << 0) ;- (EMAC) Reduce MII -// - -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- -AT91C_EMAC_IP EQU (0xFFFF << 0) ;- (EMAC) ARP request IP address -AT91C_EMAC_MAG EQU (0x1 << 16) ;- (EMAC) Magic packet event enable -AT91C_EMAC_ARP EQU (0x1 << 17) ;- (EMAC) ARP request event enable -AT91C_EMAC_SA1 EQU (0x1 << 18) ;- (EMAC) Specific address register 1 event enable -// - -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- -AT91C_EMAC_REVREF EQU (0xFFFF << 0) ;- (EMAC) -AT91C_EMAC_PARTREF EQU (0xFFFF << 16) ;- (EMAC) - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Analog to Digital Convertor -// - ***************************************************************************** -// - -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- -AT91C_ADC_SWRST EQU (0x1 << 0) ;- (ADC) Software Reset -AT91C_ADC_START EQU (0x1 << 1) ;- (ADC) Start Conversion -// - -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- -AT91C_ADC_TRGEN EQU (0x1 << 0) ;- (ADC) Trigger Enable -AT91C_ADC_TRGEN_DIS EQU (0x0) ;- (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software -AT91C_ADC_TRGEN_EN EQU (0x1) ;- (ADC) Hardware trigger selected by TRGSEL field is enabled. -AT91C_ADC_TRGSEL EQU (0x7 << 1) ;- (ADC) Trigger Selection -AT91C_ADC_TRGSEL_TIOA0 EQU (0x0 << 1) ;- (ADC) Selected TRGSEL = TIAO0 -AT91C_ADC_TRGSEL_TIOA1 EQU (0x1 << 1) ;- (ADC) Selected TRGSEL = TIAO1 -AT91C_ADC_TRGSEL_TIOA2 EQU (0x2 << 1) ;- (ADC) Selected TRGSEL = TIAO2 -AT91C_ADC_TRGSEL_TIOA3 EQU (0x3 << 1) ;- (ADC) Selected TRGSEL = TIAO3 -AT91C_ADC_TRGSEL_TIOA4 EQU (0x4 << 1) ;- (ADC) Selected TRGSEL = TIAO4 -AT91C_ADC_TRGSEL_TIOA5 EQU (0x5 << 1) ;- (ADC) Selected TRGSEL = TIAO5 -AT91C_ADC_TRGSEL_EXT EQU (0x6 << 1) ;- (ADC) Selected TRGSEL = External Trigger -AT91C_ADC_LOWRES EQU (0x1 << 4) ;- (ADC) Resolution. -AT91C_ADC_LOWRES_10_BIT EQU (0x0 << 4) ;- (ADC) 10-bit resolution -AT91C_ADC_LOWRES_8_BIT EQU (0x1 << 4) ;- (ADC) 8-bit resolution -AT91C_ADC_SLEEP EQU (0x1 << 5) ;- (ADC) Sleep Mode -AT91C_ADC_SLEEP_NORMAL_MODE EQU (0x0 << 5) ;- (ADC) Normal Mode -AT91C_ADC_SLEEP_MODE EQU (0x1 << 5) ;- (ADC) Sleep Mode -AT91C_ADC_PRESCAL EQU (0x3F << 8) ;- (ADC) Prescaler rate selection -AT91C_ADC_STARTUP EQU (0x1F << 16) ;- (ADC) Startup Time -AT91C_ADC_SHTIM EQU (0xF << 24) ;- (ADC) Sample & Hold Time -// - -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- -AT91C_ADC_CH0 EQU (0x1 << 0) ;- (ADC) Channel 0 -AT91C_ADC_CH1 EQU (0x1 << 1) ;- (ADC) Channel 1 -AT91C_ADC_CH2 EQU (0x1 << 2) ;- (ADC) Channel 2 -AT91C_ADC_CH3 EQU (0x1 << 3) ;- (ADC) Channel 3 -AT91C_ADC_CH4 EQU (0x1 << 4) ;- (ADC) Channel 4 -AT91C_ADC_CH5 EQU (0x1 << 5) ;- (ADC) Channel 5 -AT91C_ADC_CH6 EQU (0x1 << 6) ;- (ADC) Channel 6 -AT91C_ADC_CH7 EQU (0x1 << 7) ;- (ADC) Channel 7 -// - -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- -// - -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- -// - -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- -AT91C_ADC_EOC0 EQU (0x1 << 0) ;- (ADC) End of Conversion -AT91C_ADC_EOC1 EQU (0x1 << 1) ;- (ADC) End of Conversion -AT91C_ADC_EOC2 EQU (0x1 << 2) ;- (ADC) End of Conversion -AT91C_ADC_EOC3 EQU (0x1 << 3) ;- (ADC) End of Conversion -AT91C_ADC_EOC4 EQU (0x1 << 4) ;- (ADC) End of Conversion -AT91C_ADC_EOC5 EQU (0x1 << 5) ;- (ADC) End of Conversion -AT91C_ADC_EOC6 EQU (0x1 << 6) ;- (ADC) End of Conversion -AT91C_ADC_EOC7 EQU (0x1 << 7) ;- (ADC) End of Conversion -AT91C_ADC_OVRE0 EQU (0x1 << 8) ;- (ADC) Overrun Error -AT91C_ADC_OVRE1 EQU (0x1 << 9) ;- (ADC) Overrun Error -AT91C_ADC_OVRE2 EQU (0x1 << 10) ;- (ADC) Overrun Error -AT91C_ADC_OVRE3 EQU (0x1 << 11) ;- (ADC) Overrun Error -AT91C_ADC_OVRE4 EQU (0x1 << 12) ;- (ADC) Overrun Error -AT91C_ADC_OVRE5 EQU (0x1 << 13) ;- (ADC) Overrun Error -AT91C_ADC_OVRE6 EQU (0x1 << 14) ;- (ADC) Overrun Error -AT91C_ADC_OVRE7 EQU (0x1 << 15) ;- (ADC) Overrun Error -AT91C_ADC_DRDY EQU (0x1 << 16) ;- (ADC) Data Ready -AT91C_ADC_GOVRE EQU (0x1 << 17) ;- (ADC) General Overrun -AT91C_ADC_ENDRX EQU (0x1 << 18) ;- (ADC) End of Receiver Transfer -AT91C_ADC_RXBUFF EQU (0x1 << 19) ;- (ADC) RXBUFF Interrupt -// - -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- -AT91C_ADC_LDATA EQU (0x3FF << 0) ;- (ADC) Last Data Converted -// - -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- -// - -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- -// - -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- -// - -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- -AT91C_ADC_DATA EQU (0x3FF << 0) ;- (ADC) Converted Data -// - -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- -// - -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- -// - -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- -// - -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- -// - -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- -// - -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- -// - -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Advanced Encryption Standard -// - ***************************************************************************** -// - -------- AES_CR : (AES Offset: 0x0) Control Register -------- -AT91C_AES_START EQU (0x1 << 0) ;- (AES) Starts Processing -AT91C_AES_SWRST EQU (0x1 << 8) ;- (AES) Software Reset -AT91C_AES_LOADSEED EQU (0x1 << 16) ;- (AES) Random Number Generator Seed Loading -// - -------- AES_MR : (AES Offset: 0x4) Mode Register -------- -AT91C_AES_CIPHER EQU (0x1 << 0) ;- (AES) Processing Mode -AT91C_AES_PROCDLY EQU (0xF << 4) ;- (AES) Processing Delay -AT91C_AES_SMOD EQU (0x3 << 8) ;- (AES) Start Mode -AT91C_AES_SMOD_MANUAL EQU (0x0 << 8) ;- (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. -AT91C_AES_SMOD_AUTO EQU (0x1 << 8) ;- (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). -AT91C_AES_SMOD_PDC EQU (0x2 << 8) ;- (AES) PDC Mode (cf datasheet). -AT91C_AES_OPMOD EQU (0x7 << 12) ;- (AES) Operation Mode -AT91C_AES_OPMOD_ECB EQU (0x0 << 12) ;- (AES) ECB Electronic CodeBook mode. -AT91C_AES_OPMOD_CBC EQU (0x1 << 12) ;- (AES) CBC Cipher Block Chaining mode. -AT91C_AES_OPMOD_OFB EQU (0x2 << 12) ;- (AES) OFB Output Feedback mode. -AT91C_AES_OPMOD_CFB EQU (0x3 << 12) ;- (AES) CFB Cipher Feedback mode. -AT91C_AES_OPMOD_CTR EQU (0x4 << 12) ;- (AES) CTR Counter mode. -AT91C_AES_LOD EQU (0x1 << 15) ;- (AES) Last Output Data Mode -AT91C_AES_CFBS EQU (0x7 << 16) ;- (AES) Cipher Feedback Data Size -AT91C_AES_CFBS_128_BIT EQU (0x0 << 16) ;- (AES) 128-bit. -AT91C_AES_CFBS_64_BIT EQU (0x1 << 16) ;- (AES) 64-bit. -AT91C_AES_CFBS_32_BIT EQU (0x2 << 16) ;- (AES) 32-bit. -AT91C_AES_CFBS_16_BIT EQU (0x3 << 16) ;- (AES) 16-bit. -AT91C_AES_CFBS_8_BIT EQU (0x4 << 16) ;- (AES) 8-bit. -AT91C_AES_CKEY EQU (0xF << 20) ;- (AES) Countermeasure Key -AT91C_AES_CTYPE EQU (0x1F << 24) ;- (AES) Countermeasure Type -AT91C_AES_CTYPE_TYPE1_EN EQU (0x1 << 24) ;- (AES) Countermeasure type 1 is enabled. -AT91C_AES_CTYPE_TYPE2_EN EQU (0x2 << 24) ;- (AES) Countermeasure type 2 is enabled. -AT91C_AES_CTYPE_TYPE3_EN EQU (0x4 << 24) ;- (AES) Countermeasure type 3 is enabled. -AT91C_AES_CTYPE_TYPE4_EN EQU (0x8 << 24) ;- (AES) Countermeasure type 4 is enabled. -AT91C_AES_CTYPE_TYPE5_EN EQU (0x10 << 24) ;- (AES) Countermeasure type 5 is enabled. -// - -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- -AT91C_AES_DATRDY EQU (0x1 << 0) ;- (AES) DATRDY -AT91C_AES_ENDRX EQU (0x1 << 1) ;- (AES) PDC Read Buffer End -AT91C_AES_ENDTX EQU (0x1 << 2) ;- (AES) PDC Write Buffer End -AT91C_AES_RXBUFF EQU (0x1 << 3) ;- (AES) PDC Read Buffer Full -AT91C_AES_TXBUFE EQU (0x1 << 4) ;- (AES) PDC Write Buffer Empty -AT91C_AES_URAD EQU (0x1 << 8) ;- (AES) Unspecified Register Access Detection -// - -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- -// - -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- -// - -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- -AT91C_AES_URAT EQU (0x7 << 12) ;- (AES) Unspecified Register Access Type Status -AT91C_AES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (AES) Input data register written during the data processing in PDC mode. -AT91C_AES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (AES) Output data register read during the data processing. -AT91C_AES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (AES) Mode register written during the data processing. -AT91C_AES_URAT_OUT_DAT_READ_SUBKEY EQU (0x3 << 12) ;- (AES) Output data register read during the sub-keys generation. -AT91C_AES_URAT_MODEREG_WRITE_SUBKEY EQU (0x4 << 12) ;- (AES) Mode register written during the sub-keys generation. -AT91C_AES_URAT_WO_REG_READ EQU (0x5 << 12) ;- (AES) Write-only register read access. - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Triple Data Encryption Standard -// - ***************************************************************************** -// - -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- -AT91C_TDES_START EQU (0x1 << 0) ;- (TDES) Starts Processing -AT91C_TDES_SWRST EQU (0x1 << 8) ;- (TDES) Software Reset -// - -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- -AT91C_TDES_CIPHER EQU (0x1 << 0) ;- (TDES) Processing Mode -AT91C_TDES_TDESMOD EQU (0x1 << 1) ;- (TDES) Single or Triple DES Mode -AT91C_TDES_KEYMOD EQU (0x1 << 4) ;- (TDES) Key Mode -AT91C_TDES_SMOD EQU (0x3 << 8) ;- (TDES) Start Mode -AT91C_TDES_SMOD_MANUAL EQU (0x0 << 8) ;- (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. -AT91C_TDES_SMOD_AUTO EQU (0x1 << 8) ;- (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). -AT91C_TDES_SMOD_PDC EQU (0x2 << 8) ;- (TDES) PDC Mode (cf datasheet). -AT91C_TDES_OPMOD EQU (0x3 << 12) ;- (TDES) Operation Mode -AT91C_TDES_OPMOD_ECB EQU (0x0 << 12) ;- (TDES) ECB Electronic CodeBook mode. -AT91C_TDES_OPMOD_CBC EQU (0x1 << 12) ;- (TDES) CBC Cipher Block Chaining mode. -AT91C_TDES_OPMOD_OFB EQU (0x2 << 12) ;- (TDES) OFB Output Feedback mode. -AT91C_TDES_OPMOD_CFB EQU (0x3 << 12) ;- (TDES) CFB Cipher Feedback mode. -AT91C_TDES_LOD EQU (0x1 << 15) ;- (TDES) Last Output Data Mode -AT91C_TDES_CFBS EQU (0x3 << 16) ;- (TDES) Cipher Feedback Data Size -AT91C_TDES_CFBS_64_BIT EQU (0x0 << 16) ;- (TDES) 64-bit. -AT91C_TDES_CFBS_32_BIT EQU (0x1 << 16) ;- (TDES) 32-bit. -AT91C_TDES_CFBS_16_BIT EQU (0x2 << 16) ;- (TDES) 16-bit. -AT91C_TDES_CFBS_8_BIT EQU (0x3 << 16) ;- (TDES) 8-bit. -// - -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- -AT91C_TDES_DATRDY EQU (0x1 << 0) ;- (TDES) DATRDY -AT91C_TDES_ENDRX EQU (0x1 << 1) ;- (TDES) PDC Read Buffer End -AT91C_TDES_ENDTX EQU (0x1 << 2) ;- (TDES) PDC Write Buffer End -AT91C_TDES_RXBUFF EQU (0x1 << 3) ;- (TDES) PDC Read Buffer Full -AT91C_TDES_TXBUFE EQU (0x1 << 4) ;- (TDES) PDC Write Buffer Empty -AT91C_TDES_URAD EQU (0x1 << 8) ;- (TDES) Unspecified Register Access Detection -// - -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- -// - -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- -// - -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- -AT91C_TDES_URAT EQU (0x3 << 12) ;- (TDES) Unspecified Register Access Type Status -AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (TDES) Input data register written during the data processing in PDC mode. -AT91C_TDES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (TDES) Output data register read during the data processing. -AT91C_TDES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (TDES) Mode register written during the data processing. -AT91C_TDES_URAT_WO_REG_READ EQU (0x3 << 12) ;- (TDES) Write-only register read access. - -// - ***************************************************************************** -// - REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 -// - ***************************************************************************** -// - ========== Register definition for SYS peripheral ========== -// - ========== Register definition for AIC peripheral ========== -AT91C_AIC_IVR EQU (0xFFFFF100) ;- (AIC) IRQ Vector Register -AT91C_AIC_SMR EQU (0xFFFFF000) ;- (AIC) Source Mode Register -AT91C_AIC_FVR EQU (0xFFFFF104) ;- (AIC) FIQ Vector Register -AT91C_AIC_DCR EQU (0xFFFFF138) ;- (AIC) Debug Control Register (Protect) -AT91C_AIC_EOICR EQU (0xFFFFF130) ;- (AIC) End of Interrupt Command Register -AT91C_AIC_SVR EQU (0xFFFFF080) ;- (AIC) Source Vector Register -AT91C_AIC_FFSR EQU (0xFFFFF148) ;- (AIC) Fast Forcing Status Register -AT91C_AIC_ICCR EQU (0xFFFFF128) ;- (AIC) Interrupt Clear Command Register -AT91C_AIC_ISR EQU (0xFFFFF108) ;- (AIC) Interrupt Status Register -AT91C_AIC_IMR EQU (0xFFFFF110) ;- (AIC) Interrupt Mask Register -AT91C_AIC_IPR EQU (0xFFFFF10C) ;- (AIC) Interrupt Pending Register -AT91C_AIC_FFER EQU (0xFFFFF140) ;- (AIC) Fast Forcing Enable Register -AT91C_AIC_IECR EQU (0xFFFFF120) ;- (AIC) Interrupt Enable Command Register -AT91C_AIC_ISCR EQU (0xFFFFF12C) ;- (AIC) Interrupt Set Command Register -AT91C_AIC_FFDR EQU (0xFFFFF144) ;- (AIC) Fast Forcing Disable Register -AT91C_AIC_CISR EQU (0xFFFFF114) ;- (AIC) Core Interrupt Status Register -AT91C_AIC_IDCR EQU (0xFFFFF124) ;- (AIC) Interrupt Disable Command Register -AT91C_AIC_SPU EQU (0xFFFFF134) ;- (AIC) Spurious Vector Register -// - ========== Register definition for PDC_DBGU peripheral ========== -AT91C_DBGU_TCR EQU (0xFFFFF30C) ;- (PDC_DBGU) Transmit Counter Register -AT91C_DBGU_RNPR EQU (0xFFFFF310) ;- (PDC_DBGU) Receive Next Pointer Register -AT91C_DBGU_TNPR EQU (0xFFFFF318) ;- (PDC_DBGU) Transmit Next Pointer Register -AT91C_DBGU_TPR EQU (0xFFFFF308) ;- (PDC_DBGU) Transmit Pointer Register -AT91C_DBGU_RPR EQU (0xFFFFF300) ;- (PDC_DBGU) Receive Pointer Register -AT91C_DBGU_RCR EQU (0xFFFFF304) ;- (PDC_DBGU) Receive Counter Register -AT91C_DBGU_RNCR EQU (0xFFFFF314) ;- (PDC_DBGU) Receive Next Counter Register -AT91C_DBGU_PTCR EQU (0xFFFFF320) ;- (PDC_DBGU) PDC Transfer Control Register -AT91C_DBGU_PTSR EQU (0xFFFFF324) ;- (PDC_DBGU) PDC Transfer Status Register -AT91C_DBGU_TNCR EQU (0xFFFFF31C) ;- (PDC_DBGU) Transmit Next Counter Register -// - ========== Register definition for DBGU peripheral ========== -AT91C_DBGU_EXID EQU (0xFFFFF244) ;- (DBGU) Chip ID Extension Register -AT91C_DBGU_BRGR EQU (0xFFFFF220) ;- (DBGU) Baud Rate Generator Register -AT91C_DBGU_IDR EQU (0xFFFFF20C) ;- (DBGU) Interrupt Disable Register -AT91C_DBGU_CSR EQU (0xFFFFF214) ;- (DBGU) Channel Status Register -AT91C_DBGU_CIDR EQU (0xFFFFF240) ;- (DBGU) Chip ID Register -AT91C_DBGU_MR EQU (0xFFFFF204) ;- (DBGU) Mode Register -AT91C_DBGU_IMR EQU (0xFFFFF210) ;- (DBGU) Interrupt Mask Register -AT91C_DBGU_CR EQU (0xFFFFF200) ;- (DBGU) Control Register -AT91C_DBGU_FNTR EQU (0xFFFFF248) ;- (DBGU) Force NTRST Register -AT91C_DBGU_THR EQU (0xFFFFF21C) ;- (DBGU) Transmitter Holding Register -AT91C_DBGU_RHR EQU (0xFFFFF218) ;- (DBGU) Receiver Holding Register -AT91C_DBGU_IER EQU (0xFFFFF208) ;- (DBGU) Interrupt Enable Register -// - ========== Register definition for PIOA peripheral ========== -AT91C_PIOA_ODR EQU (0xFFFFF414) ;- (PIOA) Output Disable Registerr -AT91C_PIOA_SODR EQU (0xFFFFF430) ;- (PIOA) Set Output Data Register -AT91C_PIOA_ISR EQU (0xFFFFF44C) ;- (PIOA) Interrupt Status Register -AT91C_PIOA_ABSR EQU (0xFFFFF478) ;- (PIOA) AB Select Status Register -AT91C_PIOA_IER EQU (0xFFFFF440) ;- (PIOA) Interrupt Enable Register -AT91C_PIOA_PPUDR EQU (0xFFFFF460) ;- (PIOA) Pull-up Disable Register -AT91C_PIOA_IMR EQU (0xFFFFF448) ;- (PIOA) Interrupt Mask Register -AT91C_PIOA_PER EQU (0xFFFFF400) ;- (PIOA) PIO Enable Register -AT91C_PIOA_IFDR EQU (0xFFFFF424) ;- (PIOA) Input Filter Disable Register -AT91C_PIOA_OWDR EQU (0xFFFFF4A4) ;- (PIOA) Output Write Disable Register -AT91C_PIOA_MDSR EQU (0xFFFFF458) ;- (PIOA) Multi-driver Status Register -AT91C_PIOA_IDR EQU (0xFFFFF444) ;- (PIOA) Interrupt Disable Register -AT91C_PIOA_ODSR EQU (0xFFFFF438) ;- (PIOA) Output Data Status Register -AT91C_PIOA_PPUSR EQU (0xFFFFF468) ;- (PIOA) Pull-up Status Register -AT91C_PIOA_OWSR EQU (0xFFFFF4A8) ;- (PIOA) Output Write Status Register -AT91C_PIOA_BSR EQU (0xFFFFF474) ;- (PIOA) Select B Register -AT91C_PIOA_OWER EQU (0xFFFFF4A0) ;- (PIOA) Output Write Enable Register -AT91C_PIOA_IFER EQU (0xFFFFF420) ;- (PIOA) Input Filter Enable Register -AT91C_PIOA_PDSR EQU (0xFFFFF43C) ;- (PIOA) Pin Data Status Register -AT91C_PIOA_PPUER EQU (0xFFFFF464) ;- (PIOA) Pull-up Enable Register -AT91C_PIOA_OSR EQU (0xFFFFF418) ;- (PIOA) Output Status Register -AT91C_PIOA_ASR EQU (0xFFFFF470) ;- (PIOA) Select A Register -AT91C_PIOA_MDDR EQU (0xFFFFF454) ;- (PIOA) Multi-driver Disable Register -AT91C_PIOA_CODR EQU (0xFFFFF434) ;- (PIOA) Clear Output Data Register -AT91C_PIOA_MDER EQU (0xFFFFF450) ;- (PIOA) Multi-driver Enable Register -AT91C_PIOA_PDR EQU (0xFFFFF404) ;- (PIOA) PIO Disable Register -AT91C_PIOA_IFSR EQU (0xFFFFF428) ;- (PIOA) Input Filter Status Register -AT91C_PIOA_OER EQU (0xFFFFF410) ;- (PIOA) Output Enable Register -AT91C_PIOA_PSR EQU (0xFFFFF408) ;- (PIOA) PIO Status Register -// - ========== Register definition for PIOB peripheral ========== -AT91C_PIOB_OWDR EQU (0xFFFFF6A4) ;- (PIOB) Output Write Disable Register -AT91C_PIOB_MDER EQU (0xFFFFF650) ;- (PIOB) Multi-driver Enable Register -AT91C_PIOB_PPUSR EQU (0xFFFFF668) ;- (PIOB) Pull-up Status Register -AT91C_PIOB_IMR EQU (0xFFFFF648) ;- (PIOB) Interrupt Mask Register -AT91C_PIOB_ASR EQU (0xFFFFF670) ;- (PIOB) Select A Register -AT91C_PIOB_PPUDR EQU (0xFFFFF660) ;- (PIOB) Pull-up Disable Register -AT91C_PIOB_PSR EQU (0xFFFFF608) ;- (PIOB) PIO Status Register -AT91C_PIOB_IER EQU (0xFFFFF640) ;- (PIOB) Interrupt Enable Register -AT91C_PIOB_CODR EQU (0xFFFFF634) ;- (PIOB) Clear Output Data Register -AT91C_PIOB_OWER EQU (0xFFFFF6A0) ;- (PIOB) Output Write Enable Register -AT91C_PIOB_ABSR EQU (0xFFFFF678) ;- (PIOB) AB Select Status Register -AT91C_PIOB_IFDR EQU (0xFFFFF624) ;- (PIOB) Input Filter Disable Register -AT91C_PIOB_PDSR EQU (0xFFFFF63C) ;- (PIOB) Pin Data Status Register -AT91C_PIOB_IDR EQU (0xFFFFF644) ;- (PIOB) Interrupt Disable Register -AT91C_PIOB_OWSR EQU (0xFFFFF6A8) ;- (PIOB) Output Write Status Register -AT91C_PIOB_PDR EQU (0xFFFFF604) ;- (PIOB) PIO Disable Register -AT91C_PIOB_ODR EQU (0xFFFFF614) ;- (PIOB) Output Disable Registerr -AT91C_PIOB_IFSR EQU (0xFFFFF628) ;- (PIOB) Input Filter Status Register -AT91C_PIOB_PPUER EQU (0xFFFFF664) ;- (PIOB) Pull-up Enable Register -AT91C_PIOB_SODR EQU (0xFFFFF630) ;- (PIOB) Set Output Data Register -AT91C_PIOB_ISR EQU (0xFFFFF64C) ;- (PIOB) Interrupt Status Register -AT91C_PIOB_ODSR EQU (0xFFFFF638) ;- (PIOB) Output Data Status Register -AT91C_PIOB_OSR EQU (0xFFFFF618) ;- (PIOB) Output Status Register -AT91C_PIOB_MDSR EQU (0xFFFFF658) ;- (PIOB) Multi-driver Status Register -AT91C_PIOB_IFER EQU (0xFFFFF620) ;- (PIOB) Input Filter Enable Register -AT91C_PIOB_BSR EQU (0xFFFFF674) ;- (PIOB) Select B Register -AT91C_PIOB_MDDR EQU (0xFFFFF654) ;- (PIOB) Multi-driver Disable Register -AT91C_PIOB_OER EQU (0xFFFFF610) ;- (PIOB) Output Enable Register -AT91C_PIOB_PER EQU (0xFFFFF600) ;- (PIOB) PIO Enable Register -// - ========== Register definition for CKGR peripheral ========== -AT91C_CKGR_MOR EQU (0xFFFFFC20) ;- (CKGR) Main Oscillator Register -AT91C_CKGR_PLLR EQU (0xFFFFFC2C) ;- (CKGR) PLL Register -AT91C_CKGR_MCFR EQU (0xFFFFFC24) ;- (CKGR) Main Clock Frequency Register -// - ========== Register definition for PMC peripheral ========== -AT91C_PMC_IDR EQU (0xFFFFFC64) ;- (PMC) Interrupt Disable Register -AT91C_PMC_MOR EQU (0xFFFFFC20) ;- (PMC) Main Oscillator Register -AT91C_PMC_PLLR EQU (0xFFFFFC2C) ;- (PMC) PLL Register -AT91C_PMC_PCER EQU (0xFFFFFC10) ;- (PMC) Peripheral Clock Enable Register -AT91C_PMC_PCKR EQU (0xFFFFFC40) ;- (PMC) Programmable Clock Register -AT91C_PMC_MCKR EQU (0xFFFFFC30) ;- (PMC) Master Clock Register -AT91C_PMC_SCDR EQU (0xFFFFFC04) ;- (PMC) System Clock Disable Register -AT91C_PMC_PCDR EQU (0xFFFFFC14) ;- (PMC) Peripheral Clock Disable Register -AT91C_PMC_SCSR EQU (0xFFFFFC08) ;- (PMC) System Clock Status Register -AT91C_PMC_PCSR EQU (0xFFFFFC18) ;- (PMC) Peripheral Clock Status Register -AT91C_PMC_MCFR EQU (0xFFFFFC24) ;- (PMC) Main Clock Frequency Register -AT91C_PMC_SCER EQU (0xFFFFFC00) ;- (PMC) System Clock Enable Register -AT91C_PMC_IMR EQU (0xFFFFFC6C) ;- (PMC) Interrupt Mask Register -AT91C_PMC_IER EQU (0xFFFFFC60) ;- (PMC) Interrupt Enable Register -AT91C_PMC_SR EQU (0xFFFFFC68) ;- (PMC) Status Register -// - ========== Register definition for RSTC peripheral ========== -AT91C_RSTC_RCR EQU (0xFFFFFD00) ;- (RSTC) Reset Control Register -AT91C_RSTC_RMR EQU (0xFFFFFD08) ;- (RSTC) Reset Mode Register -AT91C_RSTC_RSR EQU (0xFFFFFD04) ;- (RSTC) Reset Status Register -// - ========== Register definition for RTTC peripheral ========== -AT91C_RTTC_RTSR EQU (0xFFFFFD2C) ;- (RTTC) Real-time Status Register -AT91C_RTTC_RTMR EQU (0xFFFFFD20) ;- (RTTC) Real-time Mode Register -AT91C_RTTC_RTVR EQU (0xFFFFFD28) ;- (RTTC) Real-time Value Register -AT91C_RTTC_RTAR EQU (0xFFFFFD24) ;- (RTTC) Real-time Alarm Register -// - ========== Register definition for PITC peripheral ========== -AT91C_PITC_PIVR EQU (0xFFFFFD38) ;- (PITC) Period Interval Value Register -AT91C_PITC_PISR EQU (0xFFFFFD34) ;- (PITC) Period Interval Status Register -AT91C_PITC_PIIR EQU (0xFFFFFD3C) ;- (PITC) Period Interval Image Register -AT91C_PITC_PIMR EQU (0xFFFFFD30) ;- (PITC) Period Interval Mode Register -// - ========== Register definition for WDTC peripheral ========== -AT91C_WDTC_WDCR EQU (0xFFFFFD40) ;- (WDTC) Watchdog Control Register -AT91C_WDTC_WDSR EQU (0xFFFFFD48) ;- (WDTC) Watchdog Status Register -AT91C_WDTC_WDMR EQU (0xFFFFFD44) ;- (WDTC) Watchdog Mode Register -// - ========== Register definition for VREG peripheral ========== -AT91C_VREG_MR EQU (0xFFFFFD60) ;- (VREG) Voltage Regulator Mode Register -// - ========== Register definition for MC peripheral ========== -AT91C_MC_ASR EQU (0xFFFFFF04) ;- (MC) MC Abort Status Register -AT91C_MC_RCR EQU (0xFFFFFF00) ;- (MC) MC Remap Control Register -AT91C_MC_FCR EQU (0xFFFFFF64) ;- (MC) MC Flash Command Register -AT91C_MC_AASR EQU (0xFFFFFF08) ;- (MC) MC Abort Address Status Register -AT91C_MC_FSR EQU (0xFFFFFF68) ;- (MC) MC Flash Status Register -AT91C_MC_FMR EQU (0xFFFFFF60) ;- (MC) MC Flash Mode Register -// - ========== Register definition for PDC_SPI1 peripheral ========== -AT91C_SPI1_PTCR EQU (0xFFFE4120) ;- (PDC_SPI1) PDC Transfer Control Register -AT91C_SPI1_RPR EQU (0xFFFE4100) ;- (PDC_SPI1) Receive Pointer Register -AT91C_SPI1_TNCR EQU (0xFFFE411C) ;- (PDC_SPI1) Transmit Next Counter Register -AT91C_SPI1_TPR EQU (0xFFFE4108) ;- (PDC_SPI1) Transmit Pointer Register -AT91C_SPI1_TNPR EQU (0xFFFE4118) ;- (PDC_SPI1) Transmit Next Pointer Register -AT91C_SPI1_TCR EQU (0xFFFE410C) ;- (PDC_SPI1) Transmit Counter Register -AT91C_SPI1_RCR EQU (0xFFFE4104) ;- (PDC_SPI1) Receive Counter Register -AT91C_SPI1_RNPR EQU (0xFFFE4110) ;- (PDC_SPI1) Receive Next Pointer Register -AT91C_SPI1_RNCR EQU (0xFFFE4114) ;- (PDC_SPI1) Receive Next Counter Register -AT91C_SPI1_PTSR EQU (0xFFFE4124) ;- (PDC_SPI1) PDC Transfer Status Register -// - ========== Register definition for SPI1 peripheral ========== -AT91C_SPI1_IMR EQU (0xFFFE401C) ;- (SPI1) Interrupt Mask Register -AT91C_SPI1_IER EQU (0xFFFE4014) ;- (SPI1) Interrupt Enable Register -AT91C_SPI1_MR EQU (0xFFFE4004) ;- (SPI1) Mode Register -AT91C_SPI1_RDR EQU (0xFFFE4008) ;- (SPI1) Receive Data Register -AT91C_SPI1_IDR EQU (0xFFFE4018) ;- (SPI1) Interrupt Disable Register -AT91C_SPI1_SR EQU (0xFFFE4010) ;- (SPI1) Status Register -AT91C_SPI1_TDR EQU (0xFFFE400C) ;- (SPI1) Transmit Data Register -AT91C_SPI1_CR EQU (0xFFFE4000) ;- (SPI1) Control Register -AT91C_SPI1_CSR EQU (0xFFFE4030) ;- (SPI1) Chip Select Register -// - ========== Register definition for PDC_SPI0 peripheral ========== -AT91C_SPI0_PTCR EQU (0xFFFE0120) ;- (PDC_SPI0) PDC Transfer Control Register -AT91C_SPI0_TPR EQU (0xFFFE0108) ;- (PDC_SPI0) Transmit Pointer Register -AT91C_SPI0_TCR EQU (0xFFFE010C) ;- (PDC_SPI0) Transmit Counter Register -AT91C_SPI0_RCR EQU (0xFFFE0104) ;- (PDC_SPI0) Receive Counter Register -AT91C_SPI0_PTSR EQU (0xFFFE0124) ;- (PDC_SPI0) PDC Transfer Status Register -AT91C_SPI0_RNPR EQU (0xFFFE0110) ;- (PDC_SPI0) Receive Next Pointer Register -AT91C_SPI0_RPR EQU (0xFFFE0100) ;- (PDC_SPI0) Receive Pointer Register -AT91C_SPI0_TNCR EQU (0xFFFE011C) ;- (PDC_SPI0) Transmit Next Counter Register -AT91C_SPI0_RNCR EQU (0xFFFE0114) ;- (PDC_SPI0) Receive Next Counter Register -AT91C_SPI0_TNPR EQU (0xFFFE0118) ;- (PDC_SPI0) Transmit Next Pointer Register -// - ========== Register definition for SPI0 peripheral ========== -AT91C_SPI0_IER EQU (0xFFFE0014) ;- (SPI0) Interrupt Enable Register -AT91C_SPI0_SR EQU (0xFFFE0010) ;- (SPI0) Status Register -AT91C_SPI0_IDR EQU (0xFFFE0018) ;- (SPI0) Interrupt Disable Register -AT91C_SPI0_CR EQU (0xFFFE0000) ;- (SPI0) Control Register -AT91C_SPI0_MR EQU (0xFFFE0004) ;- (SPI0) Mode Register -AT91C_SPI0_IMR EQU (0xFFFE001C) ;- (SPI0) Interrupt Mask Register -AT91C_SPI0_TDR EQU (0xFFFE000C) ;- (SPI0) Transmit Data Register -AT91C_SPI0_RDR EQU (0xFFFE0008) ;- (SPI0) Receive Data Register -AT91C_SPI0_CSR EQU (0xFFFE0030) ;- (SPI0) Chip Select Register -// - ========== Register definition for PDC_US1 peripheral ========== -AT91C_US1_RNCR EQU (0xFFFC4114) ;- (PDC_US1) Receive Next Counter Register -AT91C_US1_PTCR EQU (0xFFFC4120) ;- (PDC_US1) PDC Transfer Control Register -AT91C_US1_TCR EQU (0xFFFC410C) ;- (PDC_US1) Transmit Counter Register -AT91C_US1_PTSR EQU (0xFFFC4124) ;- (PDC_US1) PDC Transfer Status Register -AT91C_US1_TNPR EQU (0xFFFC4118) ;- (PDC_US1) Transmit Next Pointer Register -AT91C_US1_RCR EQU (0xFFFC4104) ;- (PDC_US1) Receive Counter Register -AT91C_US1_RNPR EQU (0xFFFC4110) ;- (PDC_US1) Receive Next Pointer Register -AT91C_US1_RPR EQU (0xFFFC4100) ;- (PDC_US1) Receive Pointer Register -AT91C_US1_TNCR EQU (0xFFFC411C) ;- (PDC_US1) Transmit Next Counter Register -AT91C_US1_TPR EQU (0xFFFC4108) ;- (PDC_US1) Transmit Pointer Register -// - ========== Register definition for US1 peripheral ========== -AT91C_US1_IF EQU (0xFFFC404C) ;- (US1) IRDA_FILTER Register -AT91C_US1_NER EQU (0xFFFC4044) ;- (US1) Nb Errors Register -AT91C_US1_RTOR EQU (0xFFFC4024) ;- (US1) Receiver Time-out Register -AT91C_US1_CSR EQU (0xFFFC4014) ;- (US1) Channel Status Register -AT91C_US1_IDR EQU (0xFFFC400C) ;- (US1) Interrupt Disable Register -AT91C_US1_IER EQU (0xFFFC4008) ;- (US1) Interrupt Enable Register -AT91C_US1_THR EQU (0xFFFC401C) ;- (US1) Transmitter Holding Register -AT91C_US1_TTGR EQU (0xFFFC4028) ;- (US1) Transmitter Time-guard Register -AT91C_US1_RHR EQU (0xFFFC4018) ;- (US1) Receiver Holding Register -AT91C_US1_BRGR EQU (0xFFFC4020) ;- (US1) Baud Rate Generator Register -AT91C_US1_IMR EQU (0xFFFC4010) ;- (US1) Interrupt Mask Register -AT91C_US1_FIDI EQU (0xFFFC4040) ;- (US1) FI_DI_Ratio Register -AT91C_US1_CR EQU (0xFFFC4000) ;- (US1) Control Register -AT91C_US1_MR EQU (0xFFFC4004) ;- (US1) Mode Register -// - ========== Register definition for PDC_US0 peripheral ========== -AT91C_US0_TNPR EQU (0xFFFC0118) ;- (PDC_US0) Transmit Next Pointer Register -AT91C_US0_RNPR EQU (0xFFFC0110) ;- (PDC_US0) Receive Next Pointer Register -AT91C_US0_TCR EQU (0xFFFC010C) ;- (PDC_US0) Transmit Counter Register -AT91C_US0_PTCR EQU (0xFFFC0120) ;- (PDC_US0) PDC Transfer Control Register -AT91C_US0_PTSR EQU (0xFFFC0124) ;- (PDC_US0) PDC Transfer Status Register -AT91C_US0_TNCR EQU (0xFFFC011C) ;- (PDC_US0) Transmit Next Counter Register -AT91C_US0_TPR EQU (0xFFFC0108) ;- (PDC_US0) Transmit Pointer Register -AT91C_US0_RCR EQU (0xFFFC0104) ;- (PDC_US0) Receive Counter Register -AT91C_US0_RPR EQU (0xFFFC0100) ;- (PDC_US0) Receive Pointer Register -AT91C_US0_RNCR EQU (0xFFFC0114) ;- (PDC_US0) Receive Next Counter Register -// - ========== Register definition for US0 peripheral ========== -AT91C_US0_BRGR EQU (0xFFFC0020) ;- (US0) Baud Rate Generator Register -AT91C_US0_NER EQU (0xFFFC0044) ;- (US0) Nb Errors Register -AT91C_US0_CR EQU (0xFFFC0000) ;- (US0) Control Register -AT91C_US0_IMR EQU (0xFFFC0010) ;- (US0) Interrupt Mask Register -AT91C_US0_FIDI EQU (0xFFFC0040) ;- (US0) FI_DI_Ratio Register -AT91C_US0_TTGR EQU (0xFFFC0028) ;- (US0) Transmitter Time-guard Register -AT91C_US0_MR EQU (0xFFFC0004) ;- (US0) Mode Register -AT91C_US0_RTOR EQU (0xFFFC0024) ;- (US0) Receiver Time-out Register -AT91C_US0_CSR EQU (0xFFFC0014) ;- (US0) Channel Status Register -AT91C_US0_RHR EQU (0xFFFC0018) ;- (US0) Receiver Holding Register -AT91C_US0_IDR EQU (0xFFFC000C) ;- (US0) Interrupt Disable Register -AT91C_US0_THR EQU (0xFFFC001C) ;- (US0) Transmitter Holding Register -AT91C_US0_IF EQU (0xFFFC004C) ;- (US0) IRDA_FILTER Register -AT91C_US0_IER EQU (0xFFFC0008) ;- (US0) Interrupt Enable Register -// - ========== Register definition for PDC_SSC peripheral ========== -AT91C_SSC_TNCR EQU (0xFFFD411C) ;- (PDC_SSC) Transmit Next Counter Register -AT91C_SSC_RPR EQU (0xFFFD4100) ;- (PDC_SSC) Receive Pointer Register -AT91C_SSC_RNCR EQU (0xFFFD4114) ;- (PDC_SSC) Receive Next Counter Register -AT91C_SSC_TPR EQU (0xFFFD4108) ;- (PDC_SSC) Transmit Pointer Register -AT91C_SSC_PTCR EQU (0xFFFD4120) ;- (PDC_SSC) PDC Transfer Control Register -AT91C_SSC_TCR EQU (0xFFFD410C) ;- (PDC_SSC) Transmit Counter Register -AT91C_SSC_RCR EQU (0xFFFD4104) ;- (PDC_SSC) Receive Counter Register -AT91C_SSC_RNPR EQU (0xFFFD4110) ;- (PDC_SSC) Receive Next Pointer Register -AT91C_SSC_TNPR EQU (0xFFFD4118) ;- (PDC_SSC) Transmit Next Pointer Register -AT91C_SSC_PTSR EQU (0xFFFD4124) ;- (PDC_SSC) PDC Transfer Status Register -// - ========== Register definition for SSC peripheral ========== -AT91C_SSC_RHR EQU (0xFFFD4020) ;- (SSC) Receive Holding Register -AT91C_SSC_RSHR EQU (0xFFFD4030) ;- (SSC) Receive Sync Holding Register -AT91C_SSC_TFMR EQU (0xFFFD401C) ;- (SSC) Transmit Frame Mode Register -AT91C_SSC_IDR EQU (0xFFFD4048) ;- (SSC) Interrupt Disable Register -AT91C_SSC_THR EQU (0xFFFD4024) ;- (SSC) Transmit Holding Register -AT91C_SSC_RCMR EQU (0xFFFD4010) ;- (SSC) Receive Clock ModeRegister -AT91C_SSC_IER EQU (0xFFFD4044) ;- (SSC) Interrupt Enable Register -AT91C_SSC_TSHR EQU (0xFFFD4034) ;- (SSC) Transmit Sync Holding Register -AT91C_SSC_SR EQU (0xFFFD4040) ;- (SSC) Status Register -AT91C_SSC_CMR EQU (0xFFFD4004) ;- (SSC) Clock Mode Register -AT91C_SSC_TCMR EQU (0xFFFD4018) ;- (SSC) Transmit Clock Mode Register -AT91C_SSC_CR EQU (0xFFFD4000) ;- (SSC) Control Register -AT91C_SSC_IMR EQU (0xFFFD404C) ;- (SSC) Interrupt Mask Register -AT91C_SSC_RFMR EQU (0xFFFD4014) ;- (SSC) Receive Frame Mode Register -// - ========== Register definition for TWI peripheral ========== -AT91C_TWI_IER EQU (0xFFFB8024) ;- (TWI) Interrupt Enable Register -AT91C_TWI_CR EQU (0xFFFB8000) ;- (TWI) Control Register -AT91C_TWI_SR EQU (0xFFFB8020) ;- (TWI) Status Register -AT91C_TWI_IMR EQU (0xFFFB802C) ;- (TWI) Interrupt Mask Register -AT91C_TWI_THR EQU (0xFFFB8034) ;- (TWI) Transmit Holding Register -AT91C_TWI_IDR EQU (0xFFFB8028) ;- (TWI) Interrupt Disable Register -AT91C_TWI_IADR EQU (0xFFFB800C) ;- (TWI) Internal Address Register -AT91C_TWI_MMR EQU (0xFFFB8004) ;- (TWI) Master Mode Register -AT91C_TWI_CWGR EQU (0xFFFB8010) ;- (TWI) Clock Waveform Generator Register -AT91C_TWI_RHR EQU (0xFFFB8030) ;- (TWI) Receive Holding Register -// - ========== Register definition for PWMC_CH3 peripheral ========== -AT91C_PWMC_CH3_CUPDR EQU (0xFFFCC270) ;- (PWMC_CH3) Channel Update Register -AT91C_PWMC_CH3_Reserved EQU (0xFFFCC274) ;- (PWMC_CH3) Reserved -AT91C_PWMC_CH3_CPRDR EQU (0xFFFCC268) ;- (PWMC_CH3) Channel Period Register -AT91C_PWMC_CH3_CDTYR EQU (0xFFFCC264) ;- (PWMC_CH3) Channel Duty Cycle Register -AT91C_PWMC_CH3_CCNTR EQU (0xFFFCC26C) ;- (PWMC_CH3) Channel Counter Register -AT91C_PWMC_CH3_CMR EQU (0xFFFCC260) ;- (PWMC_CH3) Channel Mode Register -// - ========== Register definition for PWMC_CH2 peripheral ========== -AT91C_PWMC_CH2_Reserved EQU (0xFFFCC254) ;- (PWMC_CH2) Reserved -AT91C_PWMC_CH2_CMR EQU (0xFFFCC240) ;- (PWMC_CH2) Channel Mode Register -AT91C_PWMC_CH2_CCNTR EQU (0xFFFCC24C) ;- (PWMC_CH2) Channel Counter Register -AT91C_PWMC_CH2_CPRDR EQU (0xFFFCC248) ;- (PWMC_CH2) Channel Period Register -AT91C_PWMC_CH2_CUPDR EQU (0xFFFCC250) ;- (PWMC_CH2) Channel Update Register -AT91C_PWMC_CH2_CDTYR EQU (0xFFFCC244) ;- (PWMC_CH2) Channel Duty Cycle Register -// - ========== Register definition for PWMC_CH1 peripheral ========== -AT91C_PWMC_CH1_Reserved EQU (0xFFFCC234) ;- (PWMC_CH1) Reserved -AT91C_PWMC_CH1_CUPDR EQU (0xFFFCC230) ;- (PWMC_CH1) Channel Update Register -AT91C_PWMC_CH1_CPRDR EQU (0xFFFCC228) ;- (PWMC_CH1) Channel Period Register -AT91C_PWMC_CH1_CCNTR EQU (0xFFFCC22C) ;- (PWMC_CH1) Channel Counter Register -AT91C_PWMC_CH1_CDTYR EQU (0xFFFCC224) ;- (PWMC_CH1) Channel Duty Cycle Register -AT91C_PWMC_CH1_CMR EQU (0xFFFCC220) ;- (PWMC_CH1) Channel Mode Register -// - ========== Register definition for PWMC_CH0 peripheral ========== -AT91C_PWMC_CH0_Reserved EQU (0xFFFCC214) ;- (PWMC_CH0) Reserved -AT91C_PWMC_CH0_CPRDR EQU (0xFFFCC208) ;- (PWMC_CH0) Channel Period Register -AT91C_PWMC_CH0_CDTYR EQU (0xFFFCC204) ;- (PWMC_CH0) Channel Duty Cycle Register -AT91C_PWMC_CH0_CMR EQU (0xFFFCC200) ;- (PWMC_CH0) Channel Mode Register -AT91C_PWMC_CH0_CUPDR EQU (0xFFFCC210) ;- (PWMC_CH0) Channel Update Register -AT91C_PWMC_CH0_CCNTR EQU (0xFFFCC20C) ;- (PWMC_CH0) Channel Counter Register -// - ========== Register definition for PWMC peripheral ========== -AT91C_PWMC_IDR EQU (0xFFFCC014) ;- (PWMC) PWMC Interrupt Disable Register -AT91C_PWMC_DIS EQU (0xFFFCC008) ;- (PWMC) PWMC Disable Register -AT91C_PWMC_IER EQU (0xFFFCC010) ;- (PWMC) PWMC Interrupt Enable Register -AT91C_PWMC_VR EQU (0xFFFCC0FC) ;- (PWMC) PWMC Version Register -AT91C_PWMC_ISR EQU (0xFFFCC01C) ;- (PWMC) PWMC Interrupt Status Register -AT91C_PWMC_SR EQU (0xFFFCC00C) ;- (PWMC) PWMC Status Register -AT91C_PWMC_IMR EQU (0xFFFCC018) ;- (PWMC) PWMC Interrupt Mask Register -AT91C_PWMC_MR EQU (0xFFFCC000) ;- (PWMC) PWMC Mode Register -AT91C_PWMC_ENA EQU (0xFFFCC004) ;- (PWMC) PWMC Enable Register -// - ========== Register definition for UDP peripheral ========== -AT91C_UDP_IMR EQU (0xFFFB0018) ;- (UDP) Interrupt Mask Register -AT91C_UDP_FADDR EQU (0xFFFB0008) ;- (UDP) Function Address Register -AT91C_UDP_NUM EQU (0xFFFB0000) ;- (UDP) Frame Number Register -AT91C_UDP_FDR EQU (0xFFFB0050) ;- (UDP) Endpoint FIFO Data Register -AT91C_UDP_ISR EQU (0xFFFB001C) ;- (UDP) Interrupt Status Register -AT91C_UDP_CSR EQU (0xFFFB0030) ;- (UDP) Endpoint Control and Status Register -AT91C_UDP_IDR EQU (0xFFFB0014) ;- (UDP) Interrupt Disable Register -AT91C_UDP_ICR EQU (0xFFFB0020) ;- (UDP) Interrupt Clear Register -AT91C_UDP_RSTEP EQU (0xFFFB0028) ;- (UDP) Reset Endpoint Register -AT91C_UDP_TXVC EQU (0xFFFB0074) ;- (UDP) Transceiver Control Register -AT91C_UDP_GLBSTATE EQU (0xFFFB0004) ;- (UDP) Global State Register -AT91C_UDP_IER EQU (0xFFFB0010) ;- (UDP) Interrupt Enable Register -// - ========== Register definition for TC0 peripheral ========== -AT91C_TC0_SR EQU (0xFFFA0020) ;- (TC0) Status Register -AT91C_TC0_RC EQU (0xFFFA001C) ;- (TC0) Register C -AT91C_TC0_RB EQU (0xFFFA0018) ;- (TC0) Register B -AT91C_TC0_CCR EQU (0xFFFA0000) ;- (TC0) Channel Control Register -AT91C_TC0_CMR EQU (0xFFFA0004) ;- (TC0) Channel Mode Register (Capture Mode / Waveform Mode) -AT91C_TC0_IER EQU (0xFFFA0024) ;- (TC0) Interrupt Enable Register -AT91C_TC0_RA EQU (0xFFFA0014) ;- (TC0) Register A -AT91C_TC0_IDR EQU (0xFFFA0028) ;- (TC0) Interrupt Disable Register -AT91C_TC0_CV EQU (0xFFFA0010) ;- (TC0) Counter Value -AT91C_TC0_IMR EQU (0xFFFA002C) ;- (TC0) Interrupt Mask Register -// - ========== Register definition for TC1 peripheral ========== -AT91C_TC1_RB EQU (0xFFFA0058) ;- (TC1) Register B -AT91C_TC1_CCR EQU (0xFFFA0040) ;- (TC1) Channel Control Register -AT91C_TC1_IER EQU (0xFFFA0064) ;- (TC1) Interrupt Enable Register -AT91C_TC1_IDR EQU (0xFFFA0068) ;- (TC1) Interrupt Disable Register -AT91C_TC1_SR EQU (0xFFFA0060) ;- (TC1) Status Register -AT91C_TC1_CMR EQU (0xFFFA0044) ;- (TC1) Channel Mode Register (Capture Mode / Waveform Mode) -AT91C_TC1_RA EQU (0xFFFA0054) ;- (TC1) Register A -AT91C_TC1_RC EQU (0xFFFA005C) ;- (TC1) Register C -AT91C_TC1_IMR EQU (0xFFFA006C) ;- (TC1) Interrupt Mask Register -AT91C_TC1_CV EQU (0xFFFA0050) ;- (TC1) Counter Value -// - ========== Register definition for TC2 peripheral ========== -AT91C_TC2_CMR EQU (0xFFFA0084) ;- (TC2) Channel Mode Register (Capture Mode / Waveform Mode) -AT91C_TC2_CCR EQU (0xFFFA0080) ;- (TC2) Channel Control Register -AT91C_TC2_CV EQU (0xFFFA0090) ;- (TC2) Counter Value -AT91C_TC2_RA EQU (0xFFFA0094) ;- (TC2) Register A -AT91C_TC2_RB EQU (0xFFFA0098) ;- (TC2) Register B -AT91C_TC2_IDR EQU (0xFFFA00A8) ;- (TC2) Interrupt Disable Register -AT91C_TC2_IMR EQU (0xFFFA00AC) ;- (TC2) Interrupt Mask Register -AT91C_TC2_RC EQU (0xFFFA009C) ;- (TC2) Register C -AT91C_TC2_IER EQU (0xFFFA00A4) ;- (TC2) Interrupt Enable Register -AT91C_TC2_SR EQU (0xFFFA00A0) ;- (TC2) Status Register -// - ========== Register definition for TCB peripheral ========== -AT91C_TCB_BMR EQU (0xFFFA00C4) ;- (TCB) TC Block Mode Register -AT91C_TCB_BCR EQU (0xFFFA00C0) ;- (TCB) TC Block Control Register -// - ========== Register definition for CAN_MB0 peripheral ========== -AT91C_CAN_MB0_MDL EQU (0xFFFD0214) ;- (CAN_MB0) MailBox Data Low Register -AT91C_CAN_MB0_MAM EQU (0xFFFD0204) ;- (CAN_MB0) MailBox Acceptance Mask Register -AT91C_CAN_MB0_MCR EQU (0xFFFD021C) ;- (CAN_MB0) MailBox Control Register -AT91C_CAN_MB0_MID EQU (0xFFFD0208) ;- (CAN_MB0) MailBox ID Register -AT91C_CAN_MB0_MSR EQU (0xFFFD0210) ;- (CAN_MB0) MailBox Status Register -AT91C_CAN_MB0_MFID EQU (0xFFFD020C) ;- (CAN_MB0) MailBox Family ID Register -AT91C_CAN_MB0_MDH EQU (0xFFFD0218) ;- (CAN_MB0) MailBox Data High Register -AT91C_CAN_MB0_MMR EQU (0xFFFD0200) ;- (CAN_MB0) MailBox Mode Register -// - ========== Register definition for CAN_MB1 peripheral ========== -AT91C_CAN_MB1_MDL EQU (0xFFFD0234) ;- (CAN_MB1) MailBox Data Low Register -AT91C_CAN_MB1_MID EQU (0xFFFD0228) ;- (CAN_MB1) MailBox ID Register -AT91C_CAN_MB1_MMR EQU (0xFFFD0220) ;- (CAN_MB1) MailBox Mode Register -AT91C_CAN_MB1_MSR EQU (0xFFFD0230) ;- (CAN_MB1) MailBox Status Register -AT91C_CAN_MB1_MAM EQU (0xFFFD0224) ;- (CAN_MB1) MailBox Acceptance Mask Register -AT91C_CAN_MB1_MDH EQU (0xFFFD0238) ;- (CAN_MB1) MailBox Data High Register -AT91C_CAN_MB1_MCR EQU (0xFFFD023C) ;- (CAN_MB1) MailBox Control Register -AT91C_CAN_MB1_MFID EQU (0xFFFD022C) ;- (CAN_MB1) MailBox Family ID Register -// - ========== Register definition for CAN_MB2 peripheral ========== -AT91C_CAN_MB2_MCR EQU (0xFFFD025C) ;- (CAN_MB2) MailBox Control Register -AT91C_CAN_MB2_MDH EQU (0xFFFD0258) ;- (CAN_MB2) MailBox Data High Register -AT91C_CAN_MB2_MID EQU (0xFFFD0248) ;- (CAN_MB2) MailBox ID Register -AT91C_CAN_MB2_MDL EQU (0xFFFD0254) ;- (CAN_MB2) MailBox Data Low Register -AT91C_CAN_MB2_MMR EQU (0xFFFD0240) ;- (CAN_MB2) MailBox Mode Register -AT91C_CAN_MB2_MAM EQU (0xFFFD0244) ;- (CAN_MB2) MailBox Acceptance Mask Register -AT91C_CAN_MB2_MFID EQU (0xFFFD024C) ;- (CAN_MB2) MailBox Family ID Register -AT91C_CAN_MB2_MSR EQU (0xFFFD0250) ;- (CAN_MB2) MailBox Status Register -// - ========== Register definition for CAN_MB3 peripheral ========== -AT91C_CAN_MB3_MFID EQU (0xFFFD026C) ;- (CAN_MB3) MailBox Family ID Register -AT91C_CAN_MB3_MAM EQU (0xFFFD0264) ;- (CAN_MB3) MailBox Acceptance Mask Register -AT91C_CAN_MB3_MID EQU (0xFFFD0268) ;- (CAN_MB3) MailBox ID Register -AT91C_CAN_MB3_MCR EQU (0xFFFD027C) ;- (CAN_MB3) MailBox Control Register -AT91C_CAN_MB3_MMR EQU (0xFFFD0260) ;- (CAN_MB3) MailBox Mode Register -AT91C_CAN_MB3_MSR EQU (0xFFFD0270) ;- (CAN_MB3) MailBox Status Register -AT91C_CAN_MB3_MDL EQU (0xFFFD0274) ;- (CAN_MB3) MailBox Data Low Register -AT91C_CAN_MB3_MDH EQU (0xFFFD0278) ;- (CAN_MB3) MailBox Data High Register -// - ========== Register definition for CAN_MB4 peripheral ========== -AT91C_CAN_MB4_MID EQU (0xFFFD0288) ;- (CAN_MB4) MailBox ID Register -AT91C_CAN_MB4_MMR EQU (0xFFFD0280) ;- (CAN_MB4) MailBox Mode Register -AT91C_CAN_MB4_MDH EQU (0xFFFD0298) ;- (CAN_MB4) MailBox Data High Register -AT91C_CAN_MB4_MFID EQU (0xFFFD028C) ;- (CAN_MB4) MailBox Family ID Register -AT91C_CAN_MB4_MSR EQU (0xFFFD0290) ;- (CAN_MB4) MailBox Status Register -AT91C_CAN_MB4_MCR EQU (0xFFFD029C) ;- (CAN_MB4) MailBox Control Register -AT91C_CAN_MB4_MDL EQU (0xFFFD0294) ;- (CAN_MB4) MailBox Data Low Register -AT91C_CAN_MB4_MAM EQU (0xFFFD0284) ;- (CAN_MB4) MailBox Acceptance Mask Register -// - ========== Register definition for CAN_MB5 peripheral ========== -AT91C_CAN_MB5_MSR EQU (0xFFFD02B0) ;- (CAN_MB5) MailBox Status Register -AT91C_CAN_MB5_MCR EQU (0xFFFD02BC) ;- (CAN_MB5) MailBox Control Register -AT91C_CAN_MB5_MFID EQU (0xFFFD02AC) ;- (CAN_MB5) MailBox Family ID Register -AT91C_CAN_MB5_MDH EQU (0xFFFD02B8) ;- (CAN_MB5) MailBox Data High Register -AT91C_CAN_MB5_MID EQU (0xFFFD02A8) ;- (CAN_MB5) MailBox ID Register -AT91C_CAN_MB5_MMR EQU (0xFFFD02A0) ;- (CAN_MB5) MailBox Mode Register -AT91C_CAN_MB5_MDL EQU (0xFFFD02B4) ;- (CAN_MB5) MailBox Data Low Register -AT91C_CAN_MB5_MAM EQU (0xFFFD02A4) ;- (CAN_MB5) MailBox Acceptance Mask Register -// - ========== Register definition for CAN_MB6 peripheral ========== -AT91C_CAN_MB6_MFID EQU (0xFFFD02CC) ;- (CAN_MB6) MailBox Family ID Register -AT91C_CAN_MB6_MID EQU (0xFFFD02C8) ;- (CAN_MB6) MailBox ID Register -AT91C_CAN_MB6_MAM EQU (0xFFFD02C4) ;- (CAN_MB6) MailBox Acceptance Mask Register -AT91C_CAN_MB6_MSR EQU (0xFFFD02D0) ;- (CAN_MB6) MailBox Status Register -AT91C_CAN_MB6_MDL EQU (0xFFFD02D4) ;- (CAN_MB6) MailBox Data Low Register -AT91C_CAN_MB6_MCR EQU (0xFFFD02DC) ;- (CAN_MB6) MailBox Control Register -AT91C_CAN_MB6_MDH EQU (0xFFFD02D8) ;- (CAN_MB6) MailBox Data High Register -AT91C_CAN_MB6_MMR EQU (0xFFFD02C0) ;- (CAN_MB6) MailBox Mode Register -// - ========== Register definition for CAN_MB7 peripheral ========== -AT91C_CAN_MB7_MCR EQU (0xFFFD02FC) ;- (CAN_MB7) MailBox Control Register -AT91C_CAN_MB7_MDH EQU (0xFFFD02F8) ;- (CAN_MB7) MailBox Data High Register -AT91C_CAN_MB7_MFID EQU (0xFFFD02EC) ;- (CAN_MB7) MailBox Family ID Register -AT91C_CAN_MB7_MDL EQU (0xFFFD02F4) ;- (CAN_MB7) MailBox Data Low Register -AT91C_CAN_MB7_MID EQU (0xFFFD02E8) ;- (CAN_MB7) MailBox ID Register -AT91C_CAN_MB7_MMR EQU (0xFFFD02E0) ;- (CAN_MB7) MailBox Mode Register -AT91C_CAN_MB7_MAM EQU (0xFFFD02E4) ;- (CAN_MB7) MailBox Acceptance Mask Register -AT91C_CAN_MB7_MSR EQU (0xFFFD02F0) ;- (CAN_MB7) MailBox Status Register -// - ========== Register definition for CAN peripheral ========== -AT91C_CAN_TCR EQU (0xFFFD0024) ;- (CAN) Transfer Command Register -AT91C_CAN_IMR EQU (0xFFFD000C) ;- (CAN) Interrupt Mask Register -AT91C_CAN_IER EQU (0xFFFD0004) ;- (CAN) Interrupt Enable Register -AT91C_CAN_ECR EQU (0xFFFD0020) ;- (CAN) Error Counter Register -AT91C_CAN_TIMESTP EQU (0xFFFD001C) ;- (CAN) Time Stamp Register -AT91C_CAN_MR EQU (0xFFFD0000) ;- (CAN) Mode Register -AT91C_CAN_IDR EQU (0xFFFD0008) ;- (CAN) Interrupt Disable Register -AT91C_CAN_ACR EQU (0xFFFD0028) ;- (CAN) Abort Command Register -AT91C_CAN_TIM EQU (0xFFFD0018) ;- (CAN) Timer Register -AT91C_CAN_SR EQU (0xFFFD0010) ;- (CAN) Status Register -AT91C_CAN_BR EQU (0xFFFD0014) ;- (CAN) Baudrate Register -AT91C_CAN_VR EQU (0xFFFD00FC) ;- (CAN) Version Register -// - ========== Register definition for EMAC peripheral ========== -AT91C_EMAC_ISR EQU (0xFFFDC024) ;- (EMAC) Interrupt Status Register -AT91C_EMAC_SA4H EQU (0xFFFDC0B4) ;- (EMAC) Specific Address 4 Top, Last 2 bytes -AT91C_EMAC_SA1L EQU (0xFFFDC098) ;- (EMAC) Specific Address 1 Bottom, First 4 bytes -AT91C_EMAC_ELE EQU (0xFFFDC078) ;- (EMAC) Excessive Length Errors Register -AT91C_EMAC_LCOL EQU (0xFFFDC05C) ;- (EMAC) Late Collision Register -AT91C_EMAC_RLE EQU (0xFFFDC088) ;- (EMAC) Receive Length Field Mismatch Register -AT91C_EMAC_WOL EQU (0xFFFDC0C4) ;- (EMAC) Wake On LAN Register -AT91C_EMAC_DTF EQU (0xFFFDC058) ;- (EMAC) Deferred Transmission Frame Register -AT91C_EMAC_TUND EQU (0xFFFDC064) ;- (EMAC) Transmit Underrun Error Register -AT91C_EMAC_NCR EQU (0xFFFDC000) ;- (EMAC) Network Control Register -AT91C_EMAC_SA4L EQU (0xFFFDC0B0) ;- (EMAC) Specific Address 4 Bottom, First 4 bytes -AT91C_EMAC_RSR EQU (0xFFFDC020) ;- (EMAC) Receive Status Register -AT91C_EMAC_SA3L EQU (0xFFFDC0A8) ;- (EMAC) Specific Address 3 Bottom, First 4 bytes -AT91C_EMAC_TSR EQU (0xFFFDC014) ;- (EMAC) Transmit Status Register -AT91C_EMAC_IDR EQU (0xFFFDC02C) ;- (EMAC) Interrupt Disable Register -AT91C_EMAC_RSE EQU (0xFFFDC074) ;- (EMAC) Receive Symbol Errors Register -AT91C_EMAC_ECOL EQU (0xFFFDC060) ;- (EMAC) Excessive Collision Register -AT91C_EMAC_TID EQU (0xFFFDC0B8) ;- (EMAC) Type ID Checking Register -AT91C_EMAC_HRB EQU (0xFFFDC090) ;- (EMAC) Hash Address Bottom[31:0] -AT91C_EMAC_TBQP EQU (0xFFFDC01C) ;- (EMAC) Transmit Buffer Queue Pointer -AT91C_EMAC_USRIO EQU (0xFFFDC0C0) ;- (EMAC) USER Input/Output Register -AT91C_EMAC_PTR EQU (0xFFFDC038) ;- (EMAC) Pause Time Register -AT91C_EMAC_SA2H EQU (0xFFFDC0A4) ;- (EMAC) Specific Address 2 Top, Last 2 bytes -AT91C_EMAC_ROV EQU (0xFFFDC070) ;- (EMAC) Receive Overrun Errors Register -AT91C_EMAC_ALE EQU (0xFFFDC054) ;- (EMAC) Alignment Error Register -AT91C_EMAC_RJA EQU (0xFFFDC07C) ;- (EMAC) Receive Jabbers Register -AT91C_EMAC_RBQP EQU (0xFFFDC018) ;- (EMAC) Receive Buffer Queue Pointer -AT91C_EMAC_TPF EQU (0xFFFDC08C) ;- (EMAC) Transmitted Pause Frames Register -AT91C_EMAC_NCFGR EQU (0xFFFDC004) ;- (EMAC) Network Configuration Register -AT91C_EMAC_HRT EQU (0xFFFDC094) ;- (EMAC) Hash Address Top[63:32] -AT91C_EMAC_USF EQU (0xFFFDC080) ;- (EMAC) Undersize Frames Register -AT91C_EMAC_FCSE EQU (0xFFFDC050) ;- (EMAC) Frame Check Sequence Error Register -AT91C_EMAC_TPQ EQU (0xFFFDC0BC) ;- (EMAC) Transmit Pause Quantum Register -AT91C_EMAC_MAN EQU (0xFFFDC034) ;- (EMAC) PHY Maintenance Register -AT91C_EMAC_FTO EQU (0xFFFDC040) ;- (EMAC) Frames Transmitted OK Register -AT91C_EMAC_REV EQU (0xFFFDC0FC) ;- (EMAC) Revision Register -AT91C_EMAC_IMR EQU (0xFFFDC030) ;- (EMAC) Interrupt Mask Register -AT91C_EMAC_SCF EQU (0xFFFDC044) ;- (EMAC) Single Collision Frame Register -AT91C_EMAC_PFR EQU (0xFFFDC03C) ;- (EMAC) Pause Frames received Register -AT91C_EMAC_MCF EQU (0xFFFDC048) ;- (EMAC) Multiple Collision Frame Register -AT91C_EMAC_NSR EQU (0xFFFDC008) ;- (EMAC) Network Status Register -AT91C_EMAC_SA2L EQU (0xFFFDC0A0) ;- (EMAC) Specific Address 2 Bottom, First 4 bytes -AT91C_EMAC_FRO EQU (0xFFFDC04C) ;- (EMAC) Frames Received OK Register -AT91C_EMAC_IER EQU (0xFFFDC028) ;- (EMAC) Interrupt Enable Register -AT91C_EMAC_SA1H EQU (0xFFFDC09C) ;- (EMAC) Specific Address 1 Top, Last 2 bytes -AT91C_EMAC_CSE EQU (0xFFFDC068) ;- (EMAC) Carrier Sense Error Register -AT91C_EMAC_SA3H EQU (0xFFFDC0AC) ;- (EMAC) Specific Address 3 Top, Last 2 bytes -AT91C_EMAC_RRE EQU (0xFFFDC06C) ;- (EMAC) Receive Ressource Error Register -AT91C_EMAC_STE EQU (0xFFFDC084) ;- (EMAC) SQE Test Error Register -// - ========== Register definition for PDC_ADC peripheral ========== -AT91C_ADC_PTSR EQU (0xFFFD8124) ;- (PDC_ADC) PDC Transfer Status Register -AT91C_ADC_PTCR EQU (0xFFFD8120) ;- (PDC_ADC) PDC Transfer Control Register -AT91C_ADC_TNPR EQU (0xFFFD8118) ;- (PDC_ADC) Transmit Next Pointer Register -AT91C_ADC_TNCR EQU (0xFFFD811C) ;- (PDC_ADC) Transmit Next Counter Register -AT91C_ADC_RNPR EQU (0xFFFD8110) ;- (PDC_ADC) Receive Next Pointer Register -AT91C_ADC_RNCR EQU (0xFFFD8114) ;- (PDC_ADC) Receive Next Counter Register -AT91C_ADC_RPR EQU (0xFFFD8100) ;- (PDC_ADC) Receive Pointer Register -AT91C_ADC_TCR EQU (0xFFFD810C) ;- (PDC_ADC) Transmit Counter Register -AT91C_ADC_TPR EQU (0xFFFD8108) ;- (PDC_ADC) Transmit Pointer Register -AT91C_ADC_RCR EQU (0xFFFD8104) ;- (PDC_ADC) Receive Counter Register -// - ========== Register definition for ADC peripheral ========== -AT91C_ADC_CDR2 EQU (0xFFFD8038) ;- (ADC) ADC Channel Data Register 2 -AT91C_ADC_CDR3 EQU (0xFFFD803C) ;- (ADC) ADC Channel Data Register 3 -AT91C_ADC_CDR0 EQU (0xFFFD8030) ;- (ADC) ADC Channel Data Register 0 -AT91C_ADC_CDR5 EQU (0xFFFD8044) ;- (ADC) ADC Channel Data Register 5 -AT91C_ADC_CHDR EQU (0xFFFD8014) ;- (ADC) ADC Channel Disable Register -AT91C_ADC_SR EQU (0xFFFD801C) ;- (ADC) ADC Status Register -AT91C_ADC_CDR4 EQU (0xFFFD8040) ;- (ADC) ADC Channel Data Register 4 -AT91C_ADC_CDR1 EQU (0xFFFD8034) ;- (ADC) ADC Channel Data Register 1 -AT91C_ADC_LCDR EQU (0xFFFD8020) ;- (ADC) ADC Last Converted Data Register -AT91C_ADC_IDR EQU (0xFFFD8028) ;- (ADC) ADC Interrupt Disable Register -AT91C_ADC_CR EQU (0xFFFD8000) ;- (ADC) ADC Control Register -AT91C_ADC_CDR7 EQU (0xFFFD804C) ;- (ADC) ADC Channel Data Register 7 -AT91C_ADC_CDR6 EQU (0xFFFD8048) ;- (ADC) ADC Channel Data Register 6 -AT91C_ADC_IER EQU (0xFFFD8024) ;- (ADC) ADC Interrupt Enable Register -AT91C_ADC_CHER EQU (0xFFFD8010) ;- (ADC) ADC Channel Enable Register -AT91C_ADC_CHSR EQU (0xFFFD8018) ;- (ADC) ADC Channel Status Register -AT91C_ADC_MR EQU (0xFFFD8004) ;- (ADC) ADC Mode Register -AT91C_ADC_IMR EQU (0xFFFD802C) ;- (ADC) ADC Interrupt Mask Register -// - ========== Register definition for PDC_AES peripheral ========== -AT91C_AES_TPR EQU (0xFFFA4108) ;- (PDC_AES) Transmit Pointer Register -AT91C_AES_PTCR EQU (0xFFFA4120) ;- (PDC_AES) PDC Transfer Control Register -AT91C_AES_RNPR EQU (0xFFFA4110) ;- (PDC_AES) Receive Next Pointer Register -AT91C_AES_TNCR EQU (0xFFFA411C) ;- (PDC_AES) Transmit Next Counter Register -AT91C_AES_TCR EQU (0xFFFA410C) ;- (PDC_AES) Transmit Counter Register -AT91C_AES_RCR EQU (0xFFFA4104) ;- (PDC_AES) Receive Counter Register -AT91C_AES_RNCR EQU (0xFFFA4114) ;- (PDC_AES) Receive Next Counter Register -AT91C_AES_TNPR EQU (0xFFFA4118) ;- (PDC_AES) Transmit Next Pointer Register -AT91C_AES_RPR EQU (0xFFFA4100) ;- (PDC_AES) Receive Pointer Register -AT91C_AES_PTSR EQU (0xFFFA4124) ;- (PDC_AES) PDC Transfer Status Register -// - ========== Register definition for AES peripheral ========== -AT91C_AES_IVxR EQU (0xFFFA4060) ;- (AES) Initialization Vector x Register -AT91C_AES_MR EQU (0xFFFA4004) ;- (AES) Mode Register -AT91C_AES_VR EQU (0xFFFA40FC) ;- (AES) AES Version Register -AT91C_AES_ODATAxR EQU (0xFFFA4050) ;- (AES) Output Data x Register -AT91C_AES_IDATAxR EQU (0xFFFA4040) ;- (AES) Input Data x Register -AT91C_AES_CR EQU (0xFFFA4000) ;- (AES) Control Register -AT91C_AES_IDR EQU (0xFFFA4014) ;- (AES) Interrupt Disable Register -AT91C_AES_IMR EQU (0xFFFA4018) ;- (AES) Interrupt Mask Register -AT91C_AES_IER EQU (0xFFFA4010) ;- (AES) Interrupt Enable Register -AT91C_AES_KEYWxR EQU (0xFFFA4020) ;- (AES) Key Word x Register -AT91C_AES_ISR EQU (0xFFFA401C) ;- (AES) Interrupt Status Register -// - ========== Register definition for PDC_TDES peripheral ========== -AT91C_TDES_RNCR EQU (0xFFFA8114) ;- (PDC_TDES) Receive Next Counter Register -AT91C_TDES_TCR EQU (0xFFFA810C) ;- (PDC_TDES) Transmit Counter Register -AT91C_TDES_RCR EQU (0xFFFA8104) ;- (PDC_TDES) Receive Counter Register -AT91C_TDES_TNPR EQU (0xFFFA8118) ;- (PDC_TDES) Transmit Next Pointer Register -AT91C_TDES_RNPR EQU (0xFFFA8110) ;- (PDC_TDES) Receive Next Pointer Register -AT91C_TDES_RPR EQU (0xFFFA8100) ;- (PDC_TDES) Receive Pointer Register -AT91C_TDES_TNCR EQU (0xFFFA811C) ;- (PDC_TDES) Transmit Next Counter Register -AT91C_TDES_TPR EQU (0xFFFA8108) ;- (PDC_TDES) Transmit Pointer Register -AT91C_TDES_PTSR EQU (0xFFFA8124) ;- (PDC_TDES) PDC Transfer Status Register -AT91C_TDES_PTCR EQU (0xFFFA8120) ;- (PDC_TDES) PDC Transfer Control Register -// - ========== Register definition for TDES peripheral ========== -AT91C_TDES_KEY2WxR EQU (0xFFFA8028) ;- (TDES) Key 2 Word x Register -AT91C_TDES_KEY3WxR EQU (0xFFFA8030) ;- (TDES) Key 3 Word x Register -AT91C_TDES_IDR EQU (0xFFFA8014) ;- (TDES) Interrupt Disable Register -AT91C_TDES_VR EQU (0xFFFA80FC) ;- (TDES) TDES Version Register -AT91C_TDES_IVxR EQU (0xFFFA8060) ;- (TDES) Initialization Vector x Register -AT91C_TDES_ODATAxR EQU (0xFFFA8050) ;- (TDES) Output Data x Register -AT91C_TDES_IMR EQU (0xFFFA8018) ;- (TDES) Interrupt Mask Register -AT91C_TDES_MR EQU (0xFFFA8004) ;- (TDES) Mode Register -AT91C_TDES_CR EQU (0xFFFA8000) ;- (TDES) Control Register -AT91C_TDES_IER EQU (0xFFFA8010) ;- (TDES) Interrupt Enable Register -AT91C_TDES_ISR EQU (0xFFFA801C) ;- (TDES) Interrupt Status Register -AT91C_TDES_IDATAxR EQU (0xFFFA8040) ;- (TDES) Input Data x Register -AT91C_TDES_KEY1WxR EQU (0xFFFA8020) ;- (TDES) Key 1 Word x Register - -// - ***************************************************************************** -// - PIO DEFINITIONS FOR AT91SAM7X256 -// - ***************************************************************************** -AT91C_PIO_PA0 EQU (1 << 0) ;- Pin Controlled by PA0 -AT91C_PA0_RXD0 EQU (AT91C_PIO_PA0) ;- USART 0 Receive Data -AT91C_PIO_PA1 EQU (1 << 1) ;- Pin Controlled by PA1 -AT91C_PA1_TXD0 EQU (AT91C_PIO_PA1) ;- USART 0 Transmit Data -AT91C_PIO_PA10 EQU (1 << 10) ;- Pin Controlled by PA10 -AT91C_PA10_TWD EQU (AT91C_PIO_PA10) ;- TWI Two-wire Serial Data -AT91C_PIO_PA11 EQU (1 << 11) ;- Pin Controlled by PA11 -AT91C_PA11_TWCK EQU (AT91C_PIO_PA11) ;- TWI Two-wire Serial Clock -AT91C_PIO_PA12 EQU (1 << 12) ;- Pin Controlled by PA12 -AT91C_PA12_NPCS00 EQU (AT91C_PIO_PA12) ;- SPI 0 Peripheral Chip Select 0 -AT91C_PIO_PA13 EQU (1 << 13) ;- Pin Controlled by PA13 -AT91C_PA13_NPCS01 EQU (AT91C_PIO_PA13) ;- SPI 0 Peripheral Chip Select 1 -AT91C_PA13_PCK1 EQU (AT91C_PIO_PA13) ;- PMC Programmable Clock Output 1 -AT91C_PIO_PA14 EQU (1 << 14) ;- Pin Controlled by PA14 -AT91C_PA14_NPCS02 EQU (AT91C_PIO_PA14) ;- SPI 0 Peripheral Chip Select 2 -AT91C_PA14_IRQ1 EQU (AT91C_PIO_PA14) ;- External Interrupt 1 -AT91C_PIO_PA15 EQU (1 << 15) ;- Pin Controlled by PA15 -AT91C_PA15_NPCS03 EQU (AT91C_PIO_PA15) ;- SPI 0 Peripheral Chip Select 3 -AT91C_PA15_TCLK2 EQU (AT91C_PIO_PA15) ;- Timer Counter 2 external clock input -AT91C_PIO_PA16 EQU (1 << 16) ;- Pin Controlled by PA16 -AT91C_PA16_MISO0 EQU (AT91C_PIO_PA16) ;- SPI 0 Master In Slave -AT91C_PIO_PA17 EQU (1 << 17) ;- Pin Controlled by PA17 -AT91C_PA17_MOSI0 EQU (AT91C_PIO_PA17) ;- SPI 0 Master Out Slave -AT91C_PIO_PA18 EQU (1 << 18) ;- Pin Controlled by PA18 -AT91C_PA18_SPCK0 EQU (AT91C_PIO_PA18) ;- SPI 0 Serial Clock -AT91C_PIO_PA19 EQU (1 << 19) ;- Pin Controlled by PA19 -AT91C_PA19_CANRX EQU (AT91C_PIO_PA19) ;- CAN Receive -AT91C_PIO_PA2 EQU (1 << 2) ;- Pin Controlled by PA2 -AT91C_PA2_SCK0 EQU (AT91C_PIO_PA2) ;- USART 0 Serial Clock -AT91C_PA2_NPCS11 EQU (AT91C_PIO_PA2) ;- SPI 1 Peripheral Chip Select 1 -AT91C_PIO_PA20 EQU (1 << 20) ;- Pin Controlled by PA20 -AT91C_PA20_CANTX EQU (AT91C_PIO_PA20) ;- CAN Transmit -AT91C_PIO_PA21 EQU (1 << 21) ;- Pin Controlled by PA21 -AT91C_PA21_TF EQU (AT91C_PIO_PA21) ;- SSC Transmit Frame Sync -AT91C_PA21_NPCS10 EQU (AT91C_PIO_PA21) ;- SPI 1 Peripheral Chip Select 0 -AT91C_PIO_PA22 EQU (1 << 22) ;- Pin Controlled by PA22 -AT91C_PA22_TK EQU (AT91C_PIO_PA22) ;- SSC Transmit Clock -AT91C_PA22_SPCK1 EQU (AT91C_PIO_PA22) ;- SPI 1 Serial Clock -AT91C_PIO_PA23 EQU (1 << 23) ;- Pin Controlled by PA23 -AT91C_PA23_TD EQU (AT91C_PIO_PA23) ;- SSC Transmit data -AT91C_PA23_MOSI1 EQU (AT91C_PIO_PA23) ;- SPI 1 Master Out Slave -AT91C_PIO_PA24 EQU (1 << 24) ;- Pin Controlled by PA24 -AT91C_PA24_RD EQU (AT91C_PIO_PA24) ;- SSC Receive Data -AT91C_PA24_MISO1 EQU (AT91C_PIO_PA24) ;- SPI 1 Master In Slave -AT91C_PIO_PA25 EQU (1 << 25) ;- Pin Controlled by PA25 -AT91C_PA25_RK EQU (AT91C_PIO_PA25) ;- SSC Receive Clock -AT91C_PA25_NPCS11 EQU (AT91C_PIO_PA25) ;- SPI 1 Peripheral Chip Select 1 -AT91C_PIO_PA26 EQU (1 << 26) ;- Pin Controlled by PA26 -AT91C_PA26_RF EQU (AT91C_PIO_PA26) ;- SSC Receive Frame Sync -AT91C_PA26_NPCS12 EQU (AT91C_PIO_PA26) ;- SPI 1 Peripheral Chip Select 2 -AT91C_PIO_PA27 EQU (1 << 27) ;- Pin Controlled by PA27 -AT91C_PA27_DRXD EQU (AT91C_PIO_PA27) ;- DBGU Debug Receive Data -AT91C_PA27_PCK3 EQU (AT91C_PIO_PA27) ;- PMC Programmable Clock Output 3 -AT91C_PIO_PA28 EQU (1 << 28) ;- Pin Controlled by PA28 -AT91C_PA28_DTXD EQU (AT91C_PIO_PA28) ;- DBGU Debug Transmit Data -AT91C_PIO_PA29 EQU (1 << 29) ;- Pin Controlled by PA29 -AT91C_PA29_FIQ EQU (AT91C_PIO_PA29) ;- AIC Fast Interrupt Input -AT91C_PA29_NPCS13 EQU (AT91C_PIO_PA29) ;- SPI 1 Peripheral Chip Select 3 -AT91C_PIO_PA3 EQU (1 << 3) ;- Pin Controlled by PA3 -AT91C_PA3_RTS0 EQU (AT91C_PIO_PA3) ;- USART 0 Ready To Send -AT91C_PA3_NPCS12 EQU (AT91C_PIO_PA3) ;- SPI 1 Peripheral Chip Select 2 -AT91C_PIO_PA30 EQU (1 << 30) ;- Pin Controlled by PA30 -AT91C_PA30_IRQ0 EQU (AT91C_PIO_PA30) ;- External Interrupt 0 -AT91C_PA30_PCK2 EQU (AT91C_PIO_PA30) ;- PMC Programmable Clock Output 2 -AT91C_PIO_PA4 EQU (1 << 4) ;- Pin Controlled by PA4 -AT91C_PA4_CTS0 EQU (AT91C_PIO_PA4) ;- USART 0 Clear To Send -AT91C_PA4_NPCS13 EQU (AT91C_PIO_PA4) ;- SPI 1 Peripheral Chip Select 3 -AT91C_PIO_PA5 EQU (1 << 5) ;- Pin Controlled by PA5 -AT91C_PA5_RXD1 EQU (AT91C_PIO_PA5) ;- USART 1 Receive Data -AT91C_PIO_PA6 EQU (1 << 6) ;- Pin Controlled by PA6 -AT91C_PA6_TXD1 EQU (AT91C_PIO_PA6) ;- USART 1 Transmit Data -AT91C_PIO_PA7 EQU (1 << 7) ;- Pin Controlled by PA7 -AT91C_PA7_SCK1 EQU (AT91C_PIO_PA7) ;- USART 1 Serial Clock -AT91C_PA7_NPCS01 EQU (AT91C_PIO_PA7) ;- SPI 0 Peripheral Chip Select 1 -AT91C_PIO_PA8 EQU (1 << 8) ;- Pin Controlled by PA8 -AT91C_PA8_RTS1 EQU (AT91C_PIO_PA8) ;- USART 1 Ready To Send -AT91C_PA8_NPCS02 EQU (AT91C_PIO_PA8) ;- SPI 0 Peripheral Chip Select 2 -AT91C_PIO_PA9 EQU (1 << 9) ;- Pin Controlled by PA9 -AT91C_PA9_CTS1 EQU (AT91C_PIO_PA9) ;- USART 1 Clear To Send -AT91C_PA9_NPCS03 EQU (AT91C_PIO_PA9) ;- SPI 0 Peripheral Chip Select 3 -AT91C_PIO_PB0 EQU (1 << 0) ;- Pin Controlled by PB0 -AT91C_PB0_ETXCK_EREFCK EQU (AT91C_PIO_PB0) ;- Ethernet MAC Transmit Clock/Reference Clock -AT91C_PB0_PCK0 EQU (AT91C_PIO_PB0) ;- PMC Programmable Clock Output 0 -AT91C_PIO_PB1 EQU (1 << 1) ;- Pin Controlled by PB1 -AT91C_PB1_ETXEN EQU (AT91C_PIO_PB1) ;- Ethernet MAC Transmit Enable -AT91C_PIO_PB10 EQU (1 << 10) ;- Pin Controlled by PB10 -AT91C_PB10_ETX2 EQU (AT91C_PIO_PB10) ;- Ethernet MAC Transmit Data 2 -AT91C_PB10_NPCS11 EQU (AT91C_PIO_PB10) ;- SPI 1 Peripheral Chip Select 1 -AT91C_PIO_PB11 EQU (1 << 11) ;- Pin Controlled by PB11 -AT91C_PB11_ETX3 EQU (AT91C_PIO_PB11) ;- Ethernet MAC Transmit Data 3 -AT91C_PB11_NPCS12 EQU (AT91C_PIO_PB11) ;- SPI 1 Peripheral Chip Select 2 -AT91C_PIO_PB12 EQU (1 << 12) ;- Pin Controlled by PB12 -AT91C_PB12_ETXER EQU (AT91C_PIO_PB12) ;- Ethernet MAC Transmikt Coding Error -AT91C_PB12_TCLK0 EQU (AT91C_PIO_PB12) ;- Timer Counter 0 external clock input -AT91C_PIO_PB13 EQU (1 << 13) ;- Pin Controlled by PB13 -AT91C_PB13_ERX2 EQU (AT91C_PIO_PB13) ;- Ethernet MAC Receive Data 2 -AT91C_PB13_NPCS01 EQU (AT91C_PIO_PB13) ;- SPI 0 Peripheral Chip Select 1 -AT91C_PIO_PB14 EQU (1 << 14) ;- Pin Controlled by PB14 -AT91C_PB14_ERX3 EQU (AT91C_PIO_PB14) ;- Ethernet MAC Receive Data 3 -AT91C_PB14_NPCS02 EQU (AT91C_PIO_PB14) ;- SPI 0 Peripheral Chip Select 2 -AT91C_PIO_PB15 EQU (1 << 15) ;- Pin Controlled by PB15 -AT91C_PB15_ERXDV EQU (AT91C_PIO_PB15) ;- Ethernet MAC Receive Data Valid -AT91C_PIO_PB16 EQU (1 << 16) ;- Pin Controlled by PB16 -AT91C_PB16_ECOL EQU (AT91C_PIO_PB16) ;- Ethernet MAC Collision Detected -AT91C_PB16_NPCS13 EQU (AT91C_PIO_PB16) ;- SPI 1 Peripheral Chip Select 3 -AT91C_PIO_PB17 EQU (1 << 17) ;- Pin Controlled by PB17 -AT91C_PB17_ERXCK EQU (AT91C_PIO_PB17) ;- Ethernet MAC Receive Clock -AT91C_PB17_NPCS03 EQU (AT91C_PIO_PB17) ;- SPI 0 Peripheral Chip Select 3 -AT91C_PIO_PB18 EQU (1 << 18) ;- Pin Controlled by PB18 -AT91C_PB18_EF100 EQU (AT91C_PIO_PB18) ;- Ethernet MAC Force 100 Mbits/sec -AT91C_PB18_ADTRG EQU (AT91C_PIO_PB18) ;- ADC External Trigger -AT91C_PIO_PB19 EQU (1 << 19) ;- Pin Controlled by PB19 -AT91C_PB19_PWM0 EQU (AT91C_PIO_PB19) ;- PWM Channel 0 -AT91C_PB19_TCLK1 EQU (AT91C_PIO_PB19) ;- Timer Counter 1 external clock input -AT91C_PIO_PB2 EQU (1 << 2) ;- Pin Controlled by PB2 -AT91C_PB2_ETX0 EQU (AT91C_PIO_PB2) ;- Ethernet MAC Transmit Data 0 -AT91C_PIO_PB20 EQU (1 << 20) ;- Pin Controlled by PB20 -AT91C_PB20_PWM1 EQU (AT91C_PIO_PB20) ;- PWM Channel 1 -AT91C_PB20_PCK0 EQU (AT91C_PIO_PB20) ;- PMC Programmable Clock Output 0 -AT91C_PIO_PB21 EQU (1 << 21) ;- Pin Controlled by PB21 -AT91C_PB21_PWM2 EQU (AT91C_PIO_PB21) ;- PWM Channel 2 -AT91C_PB21_PCK1 EQU (AT91C_PIO_PB21) ;- PMC Programmable Clock Output 1 -AT91C_PIO_PB22 EQU (1 << 22) ;- Pin Controlled by PB22 -AT91C_PB22_PWM3 EQU (AT91C_PIO_PB22) ;- PWM Channel 3 -AT91C_PB22_PCK2 EQU (AT91C_PIO_PB22) ;- PMC Programmable Clock Output 2 -AT91C_PIO_PB23 EQU (1 << 23) ;- Pin Controlled by PB23 -AT91C_PB23_TIOA0 EQU (AT91C_PIO_PB23) ;- Timer Counter 0 Multipurpose Timer I/O Pin A -AT91C_PB23_DCD1 EQU (AT91C_PIO_PB23) ;- USART 1 Data Carrier Detect -AT91C_PIO_PB24 EQU (1 << 24) ;- Pin Controlled by PB24 -AT91C_PB24_TIOB0 EQU (AT91C_PIO_PB24) ;- Timer Counter 0 Multipurpose Timer I/O Pin B -AT91C_PB24_DSR1 EQU (AT91C_PIO_PB24) ;- USART 1 Data Set ready -AT91C_PIO_PB25 EQU (1 << 25) ;- Pin Controlled by PB25 -AT91C_PB25_TIOA1 EQU (AT91C_PIO_PB25) ;- Timer Counter 1 Multipurpose Timer I/O Pin A -AT91C_PB25_DTR1 EQU (AT91C_PIO_PB25) ;- USART 1 Data Terminal ready -AT91C_PIO_PB26 EQU (1 << 26) ;- Pin Controlled by PB26 -AT91C_PB26_TIOB1 EQU (AT91C_PIO_PB26) ;- Timer Counter 1 Multipurpose Timer I/O Pin B -AT91C_PB26_RI1 EQU (AT91C_PIO_PB26) ;- USART 1 Ring Indicator -AT91C_PIO_PB27 EQU (1 << 27) ;- Pin Controlled by PB27 -AT91C_PB27_TIOA2 EQU (AT91C_PIO_PB27) ;- Timer Counter 2 Multipurpose Timer I/O Pin A -AT91C_PB27_PWM0 EQU (AT91C_PIO_PB27) ;- PWM Channel 0 -AT91C_PIO_PB28 EQU (1 << 28) ;- Pin Controlled by PB28 -AT91C_PB28_TIOB2 EQU (AT91C_PIO_PB28) ;- Timer Counter 2 Multipurpose Timer I/O Pin B -AT91C_PB28_PWM1 EQU (AT91C_PIO_PB28) ;- PWM Channel 1 -AT91C_PIO_PB29 EQU (1 << 29) ;- Pin Controlled by PB29 -AT91C_PB29_PCK1 EQU (AT91C_PIO_PB29) ;- PMC Programmable Clock Output 1 -AT91C_PB29_PWM2 EQU (AT91C_PIO_PB29) ;- PWM Channel 2 -AT91C_PIO_PB3 EQU (1 << 3) ;- Pin Controlled by PB3 -AT91C_PB3_ETX1 EQU (AT91C_PIO_PB3) ;- Ethernet MAC Transmit Data 1 -AT91C_PIO_PB30 EQU (1 << 30) ;- Pin Controlled by PB30 -AT91C_PB30_PCK2 EQU (AT91C_PIO_PB30) ;- PMC Programmable Clock Output 2 -AT91C_PB30_PWM3 EQU (AT91C_PIO_PB30) ;- PWM Channel 3 -AT91C_PIO_PB4 EQU (1 << 4) ;- Pin Controlled by PB4 -AT91C_PB4_ECRS_ECRSDV EQU (AT91C_PIO_PB4) ;- Ethernet MAC Carrier Sense/Carrier Sense and Data Valid -AT91C_PIO_PB5 EQU (1 << 5) ;- Pin Controlled by PB5 -AT91C_PB5_ERX0 EQU (AT91C_PIO_PB5) ;- Ethernet MAC Receive Data 0 -AT91C_PIO_PB6 EQU (1 << 6) ;- Pin Controlled by PB6 -AT91C_PB6_ERX1 EQU (AT91C_PIO_PB6) ;- Ethernet MAC Receive Data 1 -AT91C_PIO_PB7 EQU (1 << 7) ;- Pin Controlled by PB7 -AT91C_PB7_ERXER EQU (AT91C_PIO_PB7) ;- Ethernet MAC Receive Error -AT91C_PIO_PB8 EQU (1 << 8) ;- Pin Controlled by PB8 -AT91C_PB8_EMDC EQU (AT91C_PIO_PB8) ;- Ethernet MAC Management Data Clock -AT91C_PIO_PB9 EQU (1 << 9) ;- Pin Controlled by PB9 -AT91C_PB9_EMDIO EQU (AT91C_PIO_PB9) ;- Ethernet MAC Management Data Input/Output - -// - ***************************************************************************** -// - PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 -// - ***************************************************************************** -AT91C_ID_FIQ EQU ( 0) ;- Advanced Interrupt Controller (FIQ) -AT91C_ID_SYS EQU ( 1) ;- System Peripheral -AT91C_ID_PIOA EQU ( 2) ;- Parallel IO Controller A -AT91C_ID_PIOB EQU ( 3) ;- Parallel IO Controller B -AT91C_ID_SPI0 EQU ( 4) ;- Serial Peripheral Interface 0 -AT91C_ID_SPI1 EQU ( 5) ;- Serial Peripheral Interface 1 -AT91C_ID_US0 EQU ( 6) ;- USART 0 -AT91C_ID_US1 EQU ( 7) ;- USART 1 -AT91C_ID_SSC EQU ( 8) ;- Serial Synchronous Controller -AT91C_ID_TWI EQU ( 9) ;- Two-Wire Interface -AT91C_ID_PWMC EQU (10) ;- PWM Controller -AT91C_ID_UDP EQU (11) ;- USB Device Port -AT91C_ID_TC0 EQU (12) ;- Timer Counter 0 -AT91C_ID_TC1 EQU (13) ;- Timer Counter 1 -AT91C_ID_TC2 EQU (14) ;- Timer Counter 2 -AT91C_ID_CAN EQU (15) ;- Control Area Network Controller -AT91C_ID_EMAC EQU (16) ;- Ethernet MAC -AT91C_ID_ADC EQU (17) ;- Analog-to-Digital Converter -AT91C_ID_AES EQU (18) ;- Advanced Encryption Standard 128-bit -AT91C_ID_TDES EQU (19) ;- Triple Data Encryption Standard -AT91C_ID_20_Reserved EQU (20) ;- Reserved -AT91C_ID_21_Reserved EQU (21) ;- Reserved -AT91C_ID_22_Reserved EQU (22) ;- Reserved -AT91C_ID_23_Reserved EQU (23) ;- Reserved -AT91C_ID_24_Reserved EQU (24) ;- Reserved -AT91C_ID_25_Reserved EQU (25) ;- Reserved -AT91C_ID_26_Reserved EQU (26) ;- Reserved -AT91C_ID_27_Reserved EQU (27) ;- Reserved -AT91C_ID_28_Reserved EQU (28) ;- Reserved -AT91C_ID_29_Reserved EQU (29) ;- Reserved -AT91C_ID_IRQ0 EQU (30) ;- Advanced Interrupt Controller (IRQ0) -AT91C_ID_IRQ1 EQU (31) ;- Advanced Interrupt Controller (IRQ1) - -// - ***************************************************************************** -// - BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 -// - ***************************************************************************** -AT91C_BASE_SYS EQU (0xFFFFF000) ;- (SYS) Base Address -AT91C_BASE_AIC EQU (0xFFFFF000) ;- (AIC) Base Address -AT91C_BASE_PDC_DBGU EQU (0xFFFFF300) ;- (PDC_DBGU) Base Address -AT91C_BASE_DBGU EQU (0xFFFFF200) ;- (DBGU) Base Address -AT91C_BASE_PIOA EQU (0xFFFFF400) ;- (PIOA) Base Address -AT91C_BASE_PIOB EQU (0xFFFFF600) ;- (PIOB) Base Address -AT91C_BASE_CKGR EQU (0xFFFFFC20) ;- (CKGR) Base Address -AT91C_BASE_PMC EQU (0xFFFFFC00) ;- (PMC) Base Address -AT91C_BASE_RSTC EQU (0xFFFFFD00) ;- (RSTC) Base Address -AT91C_BASE_RTTC EQU (0xFFFFFD20) ;- (RTTC) Base Address -AT91C_BASE_PITC EQU (0xFFFFFD30) ;- (PITC) Base Address -AT91C_BASE_WDTC EQU (0xFFFFFD40) ;- (WDTC) Base Address -AT91C_BASE_VREG EQU (0xFFFFFD60) ;- (VREG) Base Address -AT91C_BASE_MC EQU (0xFFFFFF00) ;- (MC) Base Address -AT91C_BASE_PDC_SPI1 EQU (0xFFFE4100) ;- (PDC_SPI1) Base Address -AT91C_BASE_SPI1 EQU (0xFFFE4000) ;- (SPI1) Base Address -AT91C_BASE_PDC_SPI0 EQU (0xFFFE0100) ;- (PDC_SPI0) Base Address -AT91C_BASE_SPI0 EQU (0xFFFE0000) ;- (SPI0) Base Address -AT91C_BASE_PDC_US1 EQU (0xFFFC4100) ;- (PDC_US1) Base Address -AT91C_BASE_US1 EQU (0xFFFC4000) ;- (US1) Base Address -AT91C_BASE_PDC_US0 EQU (0xFFFC0100) ;- (PDC_US0) Base Address -AT91C_BASE_US0 EQU (0xFFFC0000) ;- (US0) Base Address -AT91C_BASE_PDC_SSC EQU (0xFFFD4100) ;- (PDC_SSC) Base Address -AT91C_BASE_SSC EQU (0xFFFD4000) ;- (SSC) Base Address -AT91C_BASE_TWI EQU (0xFFFB8000) ;- (TWI) Base Address -AT91C_BASE_PWMC_CH3 EQU (0xFFFCC260) ;- (PWMC_CH3) Base Address -AT91C_BASE_PWMC_CH2 EQU (0xFFFCC240) ;- (PWMC_CH2) Base Address -AT91C_BASE_PWMC_CH1 EQU (0xFFFCC220) ;- (PWMC_CH1) Base Address -AT91C_BASE_PWMC_CH0 EQU (0xFFFCC200) ;- (PWMC_CH0) Base Address -AT91C_BASE_PWMC EQU (0xFFFCC000) ;- (PWMC) Base Address -AT91C_BASE_UDP EQU (0xFFFB0000) ;- (UDP) Base Address -AT91C_BASE_TC0 EQU (0xFFFA0000) ;- (TC0) Base Address -AT91C_BASE_TC1 EQU (0xFFFA0040) ;- (TC1) Base Address -AT91C_BASE_TC2 EQU (0xFFFA0080) ;- (TC2) Base Address -AT91C_BASE_TCB EQU (0xFFFA0000) ;- (TCB) Base Address -AT91C_BASE_CAN_MB0 EQU (0xFFFD0200) ;- (CAN_MB0) Base Address -AT91C_BASE_CAN_MB1 EQU (0xFFFD0220) ;- (CAN_MB1) Base Address -AT91C_BASE_CAN_MB2 EQU (0xFFFD0240) ;- (CAN_MB2) Base Address -AT91C_BASE_CAN_MB3 EQU (0xFFFD0260) ;- (CAN_MB3) Base Address -AT91C_BASE_CAN_MB4 EQU (0xFFFD0280) ;- (CAN_MB4) Base Address -AT91C_BASE_CAN_MB5 EQU (0xFFFD02A0) ;- (CAN_MB5) Base Address -AT91C_BASE_CAN_MB6 EQU (0xFFFD02C0) ;- (CAN_MB6) Base Address -AT91C_BASE_CAN_MB7 EQU (0xFFFD02E0) ;- (CAN_MB7) Base Address -AT91C_BASE_CAN EQU (0xFFFD0000) ;- (CAN) Base Address -AT91C_BASE_EMAC EQU (0xFFFDC000) ;- (EMAC) Base Address -AT91C_BASE_PDC_ADC EQU (0xFFFD8100) ;- (PDC_ADC) Base Address -AT91C_BASE_ADC EQU (0xFFFD8000) ;- (ADC) Base Address -AT91C_BASE_PDC_AES EQU (0xFFFA4100) ;- (PDC_AES) Base Address -AT91C_BASE_AES EQU (0xFFFA4000) ;- (AES) Base Address -AT91C_BASE_PDC_TDES EQU (0xFFFA8100) ;- (PDC_TDES) Base Address -AT91C_BASE_TDES EQU (0xFFFA8000) ;- (TDES) Base Address - -// - ***************************************************************************** -// - MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 -// - ***************************************************************************** -AT91C_ISRAM EQU (0x00200000) ;- Internal SRAM base address -AT91C_ISRAM_SIZE EQU (0x00010000) ;- Internal SRAM size in byte (64 Kbyte) -AT91C_IFLASH EQU (0x00100000) ;- Internal ROM base address -AT91C_IFLASH_SIZE EQU (0x00040000) ;- Internal ROM size in byte (256 Kbyte) - - - -#endif /* AT91SAM7X256_H */ diff --git a/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c b/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c deleted file mode 100644 index 9cbd823c6..000000000 --- a/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c +++ /dev/null @@ -1,51 +0,0 @@ -//* ---------------------------------------------------------------------------- -//* ATMEL Microcontroller Software Support - ROUSSET - -//* ---------------------------------------------------------------------------- -//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -//* ---------------------------------------------------------------------------- -//* File Name : lib_AT91SAM7X256.h -//* Object : AT91SAM7X256 inlined functions -//* Generated : AT91 SW Application Group 05/20/2005 (16:22:29) -//* -//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// -//* CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005// -//* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005// -//* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004// -//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// -//* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004// -//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// -//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003// -//* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004// -//* CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005// -//* CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005// -//* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// -//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// -//* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004// -//* CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005// -//* CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005// -//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// -//* CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004// -//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// -//* CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003// -//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// -//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002// -//* ---------------------------------------------------------------------------- - - -#include "AT91SAM7X256.h" - - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_ConfigureIt -//* \brief Interrupt Handler Initialization -//*---------------------------------------------------------------------------- - diff --git a/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h b/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h deleted file mode 100644 index e66b4e1e1..000000000 --- a/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h +++ /dev/null @@ -1,4558 +0,0 @@ -//* ---------------------------------------------------------------------------- -//* ATMEL Microcontroller Software Support - ROUSSET - -//* ---------------------------------------------------------------------------- -//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -//* ---------------------------------------------------------------------------- -//* File Name : lib_AT91SAM7X256.h -//* Object : AT91SAM7X256 inlined functions -//* Generated : AT91 SW Application Group 05/20/2005 (16:22:29) -//* -//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// -//* CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005// -//* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005// -//* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004// -//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// -//* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004// -//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// -//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003// -//* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004// -//* CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005// -//* CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005// -//* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// -//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// -//* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004// -//* CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005// -//* CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005// -//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// -//* CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004// -//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// -//* CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003// -//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// -//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002// -//* ---------------------------------------------------------------------------- - -#ifndef lib_AT91SAM7X256_H -#define lib_AT91SAM7X256_H - -/* ***************************************************************************** - SOFTWARE API FOR AIC - ***************************************************************************** */ -#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20] - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_ConfigureIt -//* \brief Interrupt Handler Initialization -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AIC_ConfigureIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id, // \arg interrupt number to initialize - unsigned int priority, // \arg priority to give to the interrupt - unsigned int src_type, // \arg activation and sense of activation - void (*newHandler) (void) ) // \arg address of the interrupt handler -{ - unsigned int oldHandler; - unsigned int mask ; - - oldHandler = pAic->AIC_SVR[irq_id]; - - mask = 0x1 << irq_id ; - //* Disable the interrupt on the interrupt controller - pAic->AIC_IDCR = mask ; - //* Save the interrupt handler routine pointer and the interrupt priority - pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ; - //* Store the Source Mode Register - pAic->AIC_SMR[irq_id] = src_type | priority ; - //* Clear the interrupt on the interrupt controller - pAic->AIC_ICCR = mask ; - - return oldHandler; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_EnableIt -//* \brief Enable corresponding IT number -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_EnableIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id ) // \arg interrupt number to initialize -{ - //* Enable the interrupt on the interrupt controller - pAic->AIC_IECR = 0x1 << irq_id ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_DisableIt -//* \brief Disable corresponding IT number -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_DisableIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id ) // \arg interrupt number to initialize -{ - unsigned int mask = 0x1 << irq_id; - //* Disable the interrupt on the interrupt controller - pAic->AIC_IDCR = mask ; - //* Clear the interrupt on the Interrupt Controller ( if one is pending ) - pAic->AIC_ICCR = mask ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_ClearIt -//* \brief Clear corresponding IT number -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_ClearIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg interrupt number to initialize -{ - //* Clear the interrupt on the Interrupt Controller ( if one is pending ) - pAic->AIC_ICCR = (0x1 << irq_id); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_AcknowledgeIt -//* \brief Acknowledge corresponding IT number -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_AcknowledgeIt ( - AT91PS_AIC pAic) // \arg pointer to the AIC registers -{ - pAic->AIC_EOICR = pAic->AIC_EOICR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_SetExceptionVector -//* \brief Configure vector handler -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AIC_SetExceptionVector ( - unsigned int *pVector, // \arg pointer to the AIC registers - void (*Handler) () ) // \arg Interrupt Handler -{ - unsigned int oldVector = *pVector; - - if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE) - *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE; - else - *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000; - - return oldVector; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_Trig -//* \brief Trig an IT -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_Trig ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg interrupt number -{ - pAic->AIC_ISCR = (0x1 << irq_id) ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_IsActive -//* \brief Test if an IT is active -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AIC_IsActive ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg Interrupt Number -{ - return (pAic->AIC_ISR & (0x1 << irq_id)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_IsPending -//* \brief Test if an IT is pending -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AIC_IsPending ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg Interrupt Number -{ - return (pAic->AIC_IPR & (0x1 << irq_id)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_Open -//* \brief Set exception vectors and AIC registers to default values -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_Open( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - void (*IrqHandler) (), // \arg Default IRQ vector exception - void (*FiqHandler) (), // \arg Default FIQ vector exception - void (*DefaultHandler) (), // \arg Default Handler set in ISR - void (*SpuriousHandler) (), // \arg Default Spurious Handler - unsigned int protectMode) // \arg Debug Control Register -{ - int i; - - // Disable all interrupts and set IVR to the default handler - for (i = 0; i < 32; ++i) { - AT91F_AIC_DisableIt(pAic, i); - AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler); - } - - // Set the IRQ exception vector - AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler); - // Set the Fast Interrupt exception vector - AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler); - - pAic->AIC_SPU = (unsigned int) SpuriousHandler; - pAic->AIC_DCR = protectMode; -} -/* ***************************************************************************** - SOFTWARE API FOR PDC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetNextRx -//* \brief Set the next receive transfer descriptor -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_SetNextRx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be received - unsigned int bytes) // \arg number of bytes to be received -{ - pPDC->PDC_RNPR = (unsigned int) address; - pPDC->PDC_RNCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetNextTx -//* \brief Set the next transmit transfer descriptor -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_SetNextTx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be transmitted - unsigned int bytes) // \arg number of bytes to be transmitted -{ - pPDC->PDC_TNPR = (unsigned int) address; - pPDC->PDC_TNCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetRx -//* \brief Set the receive transfer descriptor -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_SetRx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be received - unsigned int bytes) // \arg number of bytes to be received -{ - pPDC->PDC_RPR = (unsigned int) address; - pPDC->PDC_RCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetTx -//* \brief Set the transmit transfer descriptor -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_SetTx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be transmitted - unsigned int bytes) // \arg number of bytes to be transmitted -{ - pPDC->PDC_TPR = (unsigned int) address; - pPDC->PDC_TCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_EnableTx -//* \brief Enable transmit -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_EnableTx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_TXTEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_EnableRx -//* \brief Enable receive -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_EnableRx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_RXTEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_DisableTx -//* \brief Disable transmit -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_DisableTx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_DisableRx -//* \brief Disable receive -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_DisableRx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsTxEmpty -//* \brief Test if the current transfer descriptor has been sent -//*---------------------------------------------------------------------------- -__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_TCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsNextTxEmpty -//* \brief Test if the next transfer descriptor has been moved to the current td -//*---------------------------------------------------------------------------- -__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_TNCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsRxEmpty -//* \brief Test if the current transfer descriptor has been filled -//*---------------------------------------------------------------------------- -__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_RCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsNextRxEmpty -//* \brief Test if the next transfer descriptor has been moved to the current td -//*---------------------------------------------------------------------------- -__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_RNCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_Open -//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_Open ( - AT91PS_PDC pPDC) // \arg pointer to a PDC controller -{ - //* Disable the RX and TX PDC transfer requests - AT91F_PDC_DisableRx(pPDC); - AT91F_PDC_DisableTx(pPDC); - - //* Reset all Counter register Next buffer first - AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); - AT91F_PDC_SetTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetRx(pPDC, (char *) 0, 0); - - //* Enable the RX and TX PDC transfer requests - AT91F_PDC_EnableRx(pPDC); - AT91F_PDC_EnableTx(pPDC); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_Close -//* \brief Close PDC: disable TX and RX reset transfer descriptors -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_Close ( - AT91PS_PDC pPDC) // \arg pointer to a PDC controller -{ - //* Disable the RX and TX PDC transfer requests - AT91F_PDC_DisableRx(pPDC); - AT91F_PDC_DisableTx(pPDC); - - //* Reset all Counter register Next buffer first - AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); - AT91F_PDC_SetTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetRx(pPDC, (char *) 0, 0); - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SendFrame -//* \brief Close PDC: disable TX and RX reset transfer descriptors -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PDC_SendFrame( - AT91PS_PDC pPDC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - if (AT91F_PDC_IsTxEmpty(pPDC)) { - //* Buffer and next buffer can be initialized - AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer); - AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer); - return 2; - } - else if (AT91F_PDC_IsNextTxEmpty(pPDC)) { - //* Only one buffer can be initialized - AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer); - return 1; - } - else { - //* All buffer are in use... - return 0; - } -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_ReceiveFrame -//* \brief Close PDC: disable TX and RX reset transfer descriptors -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PDC_ReceiveFrame ( - AT91PS_PDC pPDC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - if (AT91F_PDC_IsRxEmpty(pPDC)) { - //* Buffer and next buffer can be initialized - AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer); - AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer); - return 2; - } - else if (AT91F_PDC_IsNextRxEmpty(pPDC)) { - //* Only one buffer can be initialized - AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer); - return 1; - } - else { - //* All buffer are in use... - return 0; - } -} -/* ***************************************************************************** - SOFTWARE API FOR DBGU - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_InterruptEnable -//* \brief Enable DBGU Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_DBGU_InterruptEnable( - AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller - unsigned int flag) // \arg dbgu interrupt to be enabled -{ - pDbgu->DBGU_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_InterruptDisable -//* \brief Disable DBGU Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_DBGU_InterruptDisable( - AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller - unsigned int flag) // \arg dbgu interrupt to be disabled -{ - pDbgu->DBGU_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_GetInterruptMaskStatus -//* \brief Return DBGU Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status - AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller -{ - return pDbgu->DBGU_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_IsInterruptMasked -//* \brief Test if DBGU Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_DBGU_IsInterruptMasked( - AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR PIO - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgPeriph -//* \brief Enable pins to be drived by peripheral -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgPeriph( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int periphAEnable, // \arg PERIPH A to enable - unsigned int periphBEnable) // \arg PERIPH B to enable - -{ - pPio->PIO_ASR = periphAEnable; - pPio->PIO_BSR = periphBEnable; - pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgOutput -//* \brief Enable PIO in output mode -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int pioEnable) // \arg PIO to be enabled -{ - pPio->PIO_PER = pioEnable; // Set in PIO mode - pPio->PIO_OER = pioEnable; // Configure in Output -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgInput -//* \brief Enable PIO in input mode -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgInput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int inputEnable) // \arg PIO to be enabled -{ - // Disable output - pPio->PIO_ODR = inputEnable; - pPio->PIO_PER = inputEnable; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgOpendrain -//* \brief Configure PIO in open drain -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgOpendrain( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int multiDrvEnable) // \arg pio to be configured in open drain -{ - // Configure the multi-drive option - pPio->PIO_MDDR = ~multiDrvEnable; - pPio->PIO_MDER = multiDrvEnable; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgPullup -//* \brief Enable pullup on PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgPullup( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int pullupEnable) // \arg enable pullup on PIO -{ - // Connect or not Pullup - pPio->PIO_PPUDR = ~pullupEnable; - pPio->PIO_PPUER = pullupEnable; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgDirectDrive -//* \brief Enable direct drive on PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgDirectDrive( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int directDrive) // \arg PIO to be configured with direct drive - -{ - // Configure the Direct Drive - pPio->PIO_OWDR = ~directDrive; - pPio->PIO_OWER = directDrive; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgInputFilter -//* \brief Enable input filter on input PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgInputFilter( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int inputFilter) // \arg PIO to be configured with input filter - -{ - // Configure the Direct Drive - pPio->PIO_IFDR = ~inputFilter; - pPio->PIO_IFER = inputFilter; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInput -//* \brief Return PIO input value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetInput( // \return PIO input - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_PDSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInputSet -//* \brief Test if PIO is input flag is active -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsInputSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInput(pPio) & flag); -} - - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_SetOutput -//* \brief Set to 1 output PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_SetOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg output to be set -{ - pPio->PIO_SODR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_ClearOutput -//* \brief Set to 0 output PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_ClearOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg output to be cleared -{ - pPio->PIO_CODR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_ForceOutput -//* \brief Force output when Direct drive option is enabled -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_ForceOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg output to be forced -{ - pPio->PIO_ODSR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_Enable -//* \brief Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_Enable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be enabled -{ - pPio->PIO_PER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_Disable -//* \brief Disable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_Disable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be disabled -{ - pPio->PIO_PDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetStatus -//* \brief Return PIO Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_PSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsSet -//* \brief Test if PIO is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputEnable -//* \brief Output Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_OutputEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output to be enabled -{ - pPio->PIO_OER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputDisable -//* \brief Output Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_OutputDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output to be disabled -{ - pPio->PIO_ODR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetOutputStatus -//* \brief Return PIO Output Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_OSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsOuputSet -//* \brief Test if PIO Output is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsOutputSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetOutputStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InputFilterEnable -//* \brief Input Filter Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_InputFilterEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio input filter to be enabled -{ - pPio->PIO_IFER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InputFilterDisable -//* \brief Input Filter Disable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_InputFilterDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio input filter to be disabled -{ - pPio->PIO_IFDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInputFilterStatus -//* \brief Return PIO Input Filter Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_IFSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInputFilterSet -//* \brief Test if PIO Input filter is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsInputFilterSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInputFilterStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetOutputDataStatus -//* \brief Return PIO Output Data Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_ODSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InterruptEnable -//* \brief Enable PIO Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_InterruptEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio interrupt to be enabled -{ - pPio->PIO_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InterruptDisable -//* \brief Disable PIO Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_InterruptDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio interrupt to be disabled -{ - pPio->PIO_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInterruptMaskStatus -//* \brief Return PIO Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInterruptStatus -//* \brief Return PIO Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_ISR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInterruptMasked -//* \brief Test if PIO Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsInterruptMasked( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInterruptSet -//* \brief Test if PIO Interrupt is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsInterruptSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInterruptStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_MultiDriverEnable -//* \brief Multi Driver Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_MultiDriverEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be enabled -{ - pPio->PIO_MDER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_MultiDriverDisable -//* \brief Multi Driver Disable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_MultiDriverDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be disabled -{ - pPio->PIO_MDDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetMultiDriverStatus -//* \brief Return PIO Multi Driver Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_MDSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsMultiDriverSet -//* \brief Test if PIO MultiDriver is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsMultiDriverSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_A_RegisterSelection -//* \brief PIO A Register Selection -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_A_RegisterSelection( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio A register selection -{ - pPio->PIO_ASR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_B_RegisterSelection -//* \brief PIO B Register Selection -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_B_RegisterSelection( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio B register selection -{ - pPio->PIO_BSR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_Get_AB_RegisterStatus -//* \brief Return PIO Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_ABSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsAB_RegisterSet -//* \brief Test if PIO AB Register is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsAB_RegisterSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputWriteEnable -//* \brief Output Write Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_OutputWriteEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output write to be enabled -{ - pPio->PIO_OWER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputWriteDisable -//* \brief Output Write Disable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_OutputWriteDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output write to be disabled -{ - pPio->PIO_OWDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetOutputWriteStatus -//* \brief Return PIO Output Write Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_OWSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsOutputWriteSet -//* \brief Test if PIO OutputWrite is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsOutputWriteSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetCfgPullup -//* \brief Return PIO Configuration Pullup -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_PPUSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsOutputDataStatusSet -//* \brief Test if PIO Output Data Status is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsOutputDataStatusSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetOutputDataStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsCfgPullupStatusSet -//* \brief Test if PIO Configuration Pullup Status is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsCfgPullupStatusSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (~AT91F_PIO_GetCfgPullup(pPio) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR PMC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgSysClkEnableReg -//* \brief Configure the System Clock Enable Register of the PMC controller -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_CfgSysClkEnableReg ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int mode) -{ - //* Write to the SCER register - pPMC->PMC_SCER = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgSysClkDisableReg -//* \brief Configure the System Clock Disable Register of the PMC controller -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_CfgSysClkDisableReg ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int mode) -{ - //* Write to the SCDR register - pPMC->PMC_SCDR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetSysClkStatusReg -//* \brief Return the System Clock Status Register of the PMC controller -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetSysClkStatusReg ( - AT91PS_PMC pPMC // pointer to a CAN controller - ) -{ - return pPMC->PMC_SCSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_EnablePeriphClock -//* \brief Enable peripheral clock -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_EnablePeriphClock ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int periphIds) // \arg IDs of peripherals to enable -{ - pPMC->PMC_PCER = periphIds; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_DisablePeriphClock -//* \brief Disable peripheral clock -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_DisablePeriphClock ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int periphIds) // \arg IDs of peripherals to enable -{ - pPMC->PMC_PCDR = periphIds; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetPeriphClock -//* \brief Get peripheral clock status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetPeriphClock ( - AT91PS_PMC pPMC) // \arg pointer to PMC controller -{ - return pPMC->PMC_PCSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_CfgMainOscillatorReg -//* \brief Cfg the main oscillator -//*---------------------------------------------------------------------------- -__inline void AT91F_CKGR_CfgMainOscillatorReg ( - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int mode) -{ - pCKGR->CKGR_MOR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_GetMainOscillatorReg -//* \brief Cfg the main oscillator -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CKGR_GetMainOscillatorReg ( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller -{ - return pCKGR->CKGR_MOR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_EnableMainOscillator -//* \brief Enable the main oscillator -//*---------------------------------------------------------------------------- -__inline void AT91F_CKGR_EnableMainOscillator( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller -{ - pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_DisableMainOscillator -//* \brief Disable the main oscillator -//*---------------------------------------------------------------------------- -__inline void AT91F_CKGR_DisableMainOscillator ( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller -{ - pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_CfgMainOscStartUpTime -//* \brief Cfg MOR Register according to the main osc startup time -//*---------------------------------------------------------------------------- -__inline void AT91F_CKGR_CfgMainOscStartUpTime ( - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int startup_time, // \arg main osc startup time in microsecond (us) - unsigned int slowClock) // \arg slowClock in Hz -{ - pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT; - pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_GetMainClockFreqReg -//* \brief Cfg the main oscillator -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CKGR_GetMainClockFreqReg ( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller -{ - return pCKGR->CKGR_MCFR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_GetMainClock -//* \brief Return Main clock in Hz -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CKGR_GetMainClock ( - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int slowClock) // \arg slowClock in Hz -{ - return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgMCKReg -//* \brief Cfg Master Clock Register -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_CfgMCKReg ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int mode) -{ - pPMC->PMC_MCKR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetMCKReg -//* \brief Return Master Clock Register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetMCKReg( - AT91PS_PMC pPMC) // \arg pointer to PMC controller -{ - return pPMC->PMC_MCKR; -} - -//*------------------------------------------------------------------------------ -//* \fn AT91F_PMC_GetMasterClock -//* \brief Return master clock in Hz which correponds to processor clock for ARM7 -//*------------------------------------------------------------------------------ -__inline unsigned int AT91F_PMC_GetMasterClock ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int slowClock) // \arg slowClock in Hz -{ - unsigned int reg = pPMC->PMC_MCKR; - unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2)); - unsigned int pllDivider, pllMultiplier; - - switch (reg & AT91C_PMC_CSS) { - case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected - return slowClock / prescaler; - case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected - return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler; - case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected - reg = pCKGR->CKGR_PLLR; - pllDivider = (reg & AT91C_CKGR_DIV); - pllMultiplier = ((reg & AT91C_CKGR_MUL) >> 16) + 1; - return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler; - } - return 0; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_EnablePCK -//* \brief Enable peripheral clock -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_EnablePCK ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int pck, // \arg Peripheral clock identifier 0 .. 7 - unsigned int mode) -{ - pPMC->PMC_PCKR[pck] = mode; - pPMC->PMC_SCER = (1 << pck) << 8; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_DisablePCK -//* \brief Enable peripheral clock -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_DisablePCK ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int pck) // \arg Peripheral clock identifier 0 .. 7 -{ - pPMC->PMC_SCDR = (1 << pck) << 8; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_EnableIt -//* \brief Enable PMC interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_EnableIt ( - AT91PS_PMC pPMC, // pointer to a PMC controller - unsigned int flag) // IT to be enabled -{ - //* Write to the IER register - pPMC->PMC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_DisableIt -//* \brief Disable PMC interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_DisableIt ( - AT91PS_PMC pPMC, // pointer to a PMC controller - unsigned int flag) // IT to be disabled -{ - //* Write to the IDR register - pPMC->PMC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetStatus -//* \brief Return PMC Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status - AT91PS_PMC pPMC) // pointer to a PMC controller -{ - return pPMC->PMC_SR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetInterruptMaskStatus -//* \brief Return PMC Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status - AT91PS_PMC pPMC) // pointer to a PMC controller -{ - return pPMC->PMC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_IsInterruptMasked -//* \brief Test if PMC Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_IsInterruptMasked( - AT91PS_PMC pPMC, // \arg pointer to a PMC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_IsStatusSet -//* \brief Test if PMC Status is Set -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_IsStatusSet( - AT91PS_PMC pPMC, // \arg pointer to a PMC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PMC_GetStatus(pPMC) & flag); -}/* ***************************************************************************** - SOFTWARE API FOR RSTC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTSoftReset -//* \brief Start Software Reset -//*---------------------------------------------------------------------------- -__inline void AT91F_RSTSoftReset( - AT91PS_RSTC pRSTC, - unsigned int reset) -{ - pRSTC->RSTC_RCR = (0xA5000000 | reset); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTSetMode -//* \brief Set Reset Mode -//*---------------------------------------------------------------------------- -__inline void AT91F_RSTSetMode( - AT91PS_RSTC pRSTC, - unsigned int mode) -{ - pRSTC->RSTC_RMR = (0xA5000000 | mode); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTGetMode -//* \brief Get Reset Mode -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_RSTGetMode( - AT91PS_RSTC pRSTC) -{ - return (pRSTC->RSTC_RMR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTGetStatus -//* \brief Get Reset Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_RSTGetStatus( - AT91PS_RSTC pRSTC) -{ - return (pRSTC->RSTC_RSR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTIsSoftRstActive -//* \brief Return !=0 if software reset is still not completed -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_RSTIsSoftRstActive( - AT91PS_RSTC pRSTC) -{ - return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP); -} -/* ***************************************************************************** - SOFTWARE API FOR RTTC - ***************************************************************************** */ -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_SetRTT_TimeBase() -//* \brief Set the RTT prescaler according to the TimeBase in ms -//*-------------------------------------------------------------------------------------- -__inline unsigned int AT91F_RTTSetTimeBase( - AT91PS_RTTC pRTTC, - unsigned int ms) -{ - if (ms > 2000) - return 1; // AT91C_TIME_OUT_OF_RANGE - pRTTC->RTTC_RTMR &= ~0xFFFF; - pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF); - return 0; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTTSetPrescaler() -//* \brief Set the new prescaler value -//*-------------------------------------------------------------------------------------- -__inline unsigned int AT91F_RTTSetPrescaler( - AT91PS_RTTC pRTTC, - unsigned int rtpres) -{ - pRTTC->RTTC_RTMR &= ~0xFFFF; - pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF); - return (pRTTC->RTTC_RTMR); -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTTRestart() -//* \brief Restart the RTT prescaler -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTRestart( - AT91PS_RTTC pRTTC) -{ - pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST; -} - - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_SetAlarmINT() -//* \brief Enable RTT Alarm Interrupt -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTSetAlarmINT( - AT91PS_RTTC pRTTC) -{ - pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_ClearAlarmINT() -//* \brief Disable RTT Alarm Interrupt -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTClearAlarmINT( - AT91PS_RTTC pRTTC) -{ - pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_SetRttIncINT() -//* \brief Enable RTT INC Interrupt -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTSetRttIncINT( - AT91PS_RTTC pRTTC) -{ - pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_ClearRttIncINT() -//* \brief Disable RTT INC Interrupt -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTClearRttIncINT( - AT91PS_RTTC pRTTC) -{ - pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_SetAlarmValue() -//* \brief Set RTT Alarm Value -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTSetAlarmValue( - AT91PS_RTTC pRTTC, unsigned int alarm) -{ - pRTTC->RTTC_RTAR = alarm; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_GetAlarmValue() -//* \brief Get RTT Alarm Value -//*-------------------------------------------------------------------------------------- -__inline unsigned int AT91F_RTTGetAlarmValue( - AT91PS_RTTC pRTTC) -{ - return(pRTTC->RTTC_RTAR); -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTTGetStatus() -//* \brief Read the RTT status -//*-------------------------------------------------------------------------------------- -__inline unsigned int AT91F_RTTGetStatus( - AT91PS_RTTC pRTTC) -{ - return(pRTTC->RTTC_RTSR); -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_ReadValue() -//* \brief Read the RTT value -//*-------------------------------------------------------------------------------------- -__inline unsigned int AT91F_RTTReadValue( - AT91PS_RTTC pRTTC) -{ - register volatile unsigned int val1,val2; - do - { - val1 = pRTTC->RTTC_RTVR; - val2 = pRTTC->RTTC_RTVR; - } - while(val1 != val2); - return(val1); -} -/* ***************************************************************************** - SOFTWARE API FOR PITC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITInit -//* \brief System timer init : period in µsecond, system clock freq in MHz -//*---------------------------------------------------------------------------- -__inline void AT91F_PITInit( - AT91PS_PITC pPITC, - unsigned int period, - unsigned int pit_frequency) -{ - pPITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0; // +8 to avoid %10 and /10 - pPITC->PITC_PIMR |= AT91C_PITC_PITEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITSetPIV -//* \brief Set the PIT Periodic Interval Value -//*---------------------------------------------------------------------------- -__inline void AT91F_PITSetPIV( - AT91PS_PITC pPITC, - unsigned int piv) -{ - pPITC->PITC_PIMR = piv | (pPITC->PITC_PIMR & (AT91C_PITC_PITEN | AT91C_PITC_PITIEN)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITEnableInt -//* \brief Enable PIT periodic interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PITEnableInt( - AT91PS_PITC pPITC) -{ - pPITC->PITC_PIMR |= AT91C_PITC_PITIEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITDisableInt -//* \brief Disable PIT periodic interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PITDisableInt( - AT91PS_PITC pPITC) -{ - pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITGetMode -//* \brief Read PIT mode register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PITGetMode( - AT91PS_PITC pPITC) -{ - return(pPITC->PITC_PIMR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITGetStatus -//* \brief Read PIT status register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PITGetStatus( - AT91PS_PITC pPITC) -{ - return(pPITC->PITC_PISR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITGetPIIR -//* \brief Read PIT CPIV and PICNT without ressetting the counters -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PITGetPIIR( - AT91PS_PITC pPITC) -{ - return(pPITC->PITC_PIIR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITGetPIVR -//* \brief Read System timer CPIV and PICNT without ressetting the counters -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PITGetPIVR( - AT91PS_PITC pPITC) -{ - return(pPITC->PITC_PIVR); -} -/* ***************************************************************************** - SOFTWARE API FOR WDTC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_WDTSetMode -//* \brief Set Watchdog Mode Register -//*---------------------------------------------------------------------------- -__inline void AT91F_WDTSetMode( - AT91PS_WDTC pWDTC, - unsigned int Mode) -{ - pWDTC->WDTC_WDMR = Mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_WDTRestart -//* \brief Restart Watchdog -//*---------------------------------------------------------------------------- -__inline void AT91F_WDTRestart( - AT91PS_WDTC pWDTC) -{ - pWDTC->WDTC_WDCR = 0xA5000001; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_WDTSGettatus -//* \brief Get Watchdog Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_WDTSGettatus( - AT91PS_WDTC pWDTC) -{ - return(pWDTC->WDTC_WDSR & 0x3); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_WDTGetPeriod -//* \brief Translate ms into Watchdog Compatible value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_WDTGetPeriod(unsigned int ms) -{ - if ((ms < 4) || (ms > 16000)) - return 0; - return((ms << 8) / 1000); -} -/* ***************************************************************************** - SOFTWARE API FOR VREG - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_VREG_Enable_LowPowerMode -//* \brief Enable VREG Low Power Mode -//*---------------------------------------------------------------------------- -__inline void AT91F_VREG_Enable_LowPowerMode( - AT91PS_VREG pVREG) -{ - pVREG->VREG_MR |= AT91C_VREG_PSTDBY; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_VREG_Disable_LowPowerMode -//* \brief Disable VREG Low Power Mode -//*---------------------------------------------------------------------------- -__inline void AT91F_VREG_Disable_LowPowerMode( - AT91PS_VREG pVREG) -{ - pVREG->VREG_MR &= ~AT91C_VREG_PSTDBY; -}/* ***************************************************************************** - SOFTWARE API FOR MC - ***************************************************************************** */ - -#define AT91C_MC_CORRECT_KEY ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_Remap -//* \brief Make Remap -//*---------------------------------------------------------------------------- -__inline void AT91F_MC_Remap (void) // -{ - AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC; - - pMC->MC_RCR = AT91C_MC_RCB; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_CfgModeReg -//* \brief Configure the EFC Mode Register of the MC controller -//*---------------------------------------------------------------------------- -__inline void AT91F_MC_EFC_CfgModeReg ( - AT91PS_MC pMC, // pointer to a MC controller - unsigned int mode) // mode register -{ - // Write to the FMR register - pMC->MC_FMR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_GetModeReg -//* \brief Return MC EFC Mode Regsiter -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MC_EFC_GetModeReg( - AT91PS_MC pMC) // pointer to a MC controller -{ - return pMC->MC_FMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_ComputeFMCN -//* \brief Return MC EFC Mode Regsiter -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MC_EFC_ComputeFMCN( - int master_clock) // master clock in Hz -{ - return (master_clock/1000000 +2); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_PerformCmd -//* \brief Perform EFC Command -//*---------------------------------------------------------------------------- -__inline void AT91F_MC_EFC_PerformCmd ( - AT91PS_MC pMC, // pointer to a MC controller - unsigned int transfer_cmd) -{ - pMC->MC_FCR = transfer_cmd; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_GetStatus -//* \brief Return MC EFC Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MC_EFC_GetStatus( - AT91PS_MC pMC) // pointer to a MC controller -{ - return pMC->MC_FSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_IsInterruptMasked -//* \brief Test if EFC MC Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MC_EFC_IsInterruptMasked( - AT91PS_MC pMC, // \arg pointer to a MC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_MC_EFC_GetModeReg(pMC) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_IsInterruptSet -//* \brief Test if EFC MC Interrupt is Set -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MC_EFC_IsInterruptSet( - AT91PS_MC pMC, // \arg pointer to a MC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_MC_EFC_GetStatus(pMC) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR SPI - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Open -//* \brief Open a SPI Port -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SPI_Open ( - const unsigned int null) // \arg -{ - /* NOT DEFINED AT THIS MOMENT */ - return ( 0 ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_CfgCs -//* \brief Configure SPI chip select register -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_CfgCs ( - AT91PS_SPI pSPI, // pointer to a SPI controller - int cs, // SPI cs number (0 to 3) - int val) // chip select register -{ - //* Write to the CSR register - *(pSPI->SPI_CSR + cs) = val; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_EnableIt -//* \brief Enable SPI interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_EnableIt ( - AT91PS_SPI pSPI, // pointer to a SPI controller - unsigned int flag) // IT to be enabled -{ - //* Write to the IER register - pSPI->SPI_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_DisableIt -//* \brief Disable SPI interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_DisableIt ( - AT91PS_SPI pSPI, // pointer to a SPI controller - unsigned int flag) // IT to be disabled -{ - //* Write to the IDR register - pSPI->SPI_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Reset -//* \brief Reset the SPI controller -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_Reset ( - AT91PS_SPI pSPI // pointer to a SPI controller - ) -{ - //* Write to the CR register - pSPI->SPI_CR = AT91C_SPI_SWRST; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Enable -//* \brief Enable the SPI controller -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_Enable ( - AT91PS_SPI pSPI // pointer to a SPI controller - ) -{ - //* Write to the CR register - pSPI->SPI_CR = AT91C_SPI_SPIEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Disable -//* \brief Disable the SPI controller -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_Disable ( - AT91PS_SPI pSPI // pointer to a SPI controller - ) -{ - //* Write to the CR register - pSPI->SPI_CR = AT91C_SPI_SPIDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_CfgMode -//* \brief Enable the SPI controller -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_CfgMode ( - AT91PS_SPI pSPI, // pointer to a SPI controller - int mode) // mode register -{ - //* Write to the MR register - pSPI->SPI_MR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_CfgPCS -//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_CfgPCS ( - AT91PS_SPI pSPI, // pointer to a SPI controller - char PCS_Device) // PCS of the Device -{ - //* Write to the MR register - pSPI->SPI_MR &= 0xFFF0FFFF; - pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_ReceiveFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SPI_ReceiveFrame ( - AT91PS_SPI pSPI, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_ReceiveFrame( - (AT91PS_PDC) &(pSPI->SPI_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_SendFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SPI_SendFrame( - AT91PS_SPI pSPI, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_SendFrame( - (AT91PS_PDC) &(pSPI->SPI_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Close -//* \brief Close SPI: disable IT disable transfert, close PDC -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_Close ( - AT91PS_SPI pSPI) // \arg pointer to a SPI controller -{ - //* Reset all the Chip Select register - pSPI->SPI_CSR[0] = 0 ; - pSPI->SPI_CSR[1] = 0 ; - pSPI->SPI_CSR[2] = 0 ; - pSPI->SPI_CSR[3] = 0 ; - - //* Reset the SPI mode - pSPI->SPI_MR = 0 ; - - //* Disable all interrupts - pSPI->SPI_IDR = 0xFFFFFFFF ; - - //* Abort the Peripheral Data Transfers - AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR)); - - //* Disable receiver and transmitter and stop any activity immediately - pSPI->SPI_CR = AT91C_SPI_SPIDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_PutChar -//* \brief Send a character,does not check if ready to send -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_PutChar ( - AT91PS_SPI pSPI, - unsigned int character, - unsigned int cs_number ) -{ - unsigned int value_for_cs; - value_for_cs = (~(1 << cs_number)) & 0xF; //Place a zero among a 4 ONEs number - pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_GetChar -//* \brief Receive a character,does not check if a character is available -//*---------------------------------------------------------------------------- -__inline int AT91F_SPI_GetChar ( - const AT91PS_SPI pSPI) -{ - return((pSPI->SPI_RDR) & 0xFFFF); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_GetInterruptMaskStatus -//* \brief Return SPI Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status - AT91PS_SPI pSpi) // \arg pointer to a SPI controller -{ - return pSpi->SPI_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_IsInterruptMasked -//* \brief Test if SPI Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_SPI_IsInterruptMasked( - AT91PS_SPI pSpi, // \arg pointer to a SPI controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR USART - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Baudrate -//* \brief Calculate the baudrate -//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity -#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_NONE + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CLKS_CLOCK ) - -//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity -#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_NONE + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CLKS_EXT ) - -//* Standard Synchronous Mode : 8 bits , 1 stop , no parity -#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \ - AT91C_US_USMODE_NORMAL + \ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_NONE + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CLKS_CLOCK ) - -//* SCK used Label -#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT) - -//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity -#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \ - AT91C_US_CLKS_CLOCK +\ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_EVEN + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CKLO +\ - AT91C_US_OVER) - -//* Standard IRDA mode -#define AT91C_US_ASYNC_IRDA_MODE ( AT91C_US_USMODE_IRDA + \ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_NONE + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CLKS_CLOCK ) - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Baudrate -//* \brief Caluculate baud_value according to the main clock and the baud rate -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_US_Baudrate ( - const unsigned int main_clock, // \arg peripheral clock - const unsigned int baud_rate) // \arg UART baudrate -{ - unsigned int baud_value = ((main_clock*10)/(baud_rate * 16)); - if ((baud_value % 10) >= 5) - baud_value = (baud_value / 10) + 1; - else - baud_value /= 10; - return baud_value; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_SetBaudrate -//* \brief Set the baudrate according to the CPU clock -//*---------------------------------------------------------------------------- -__inline void AT91F_US_SetBaudrate ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int mainClock, // \arg peripheral clock - unsigned int speed) // \arg UART baudrate -{ - //* Define the baud rate divisor register - pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_SetTimeguard -//* \brief Set USART timeguard -//*---------------------------------------------------------------------------- -__inline void AT91F_US_SetTimeguard ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int timeguard) // \arg timeguard value -{ - //* Write the Timeguard Register - pUSART->US_TTGR = timeguard ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_EnableIt -//* \brief Enable USART IT -//*---------------------------------------------------------------------------- -__inline void AT91F_US_EnableIt ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int flag) // \arg IT to be enabled -{ - //* Write to the IER register - pUSART->US_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_DisableIt -//* \brief Disable USART IT -//*---------------------------------------------------------------------------- -__inline void AT91F_US_DisableIt ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int flag) // \arg IT to be disabled -{ - //* Write to the IER register - pUSART->US_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Configure -//* \brief Configure USART -//*---------------------------------------------------------------------------- -__inline void AT91F_US_Configure ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int mainClock, // \arg peripheral clock - unsigned int mode , // \arg mode Register to be programmed - unsigned int baudRate , // \arg baudrate to be programmed - unsigned int timeguard ) // \arg timeguard to be programmed -{ - //* Disable interrupts - pUSART->US_IDR = (unsigned int) -1; - - //* Reset receiver and transmitter - pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ; - - //* Define the baud rate divisor register - AT91F_US_SetBaudrate(pUSART, mainClock, baudRate); - - //* Write the Timeguard Register - AT91F_US_SetTimeguard(pUSART, timeguard); - - //* Clear Transmit and Receive Counters - AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR)); - - //* Define the USART mode - pUSART->US_MR = mode ; - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_EnableRx -//* \brief Enable receiving characters -//*---------------------------------------------------------------------------- -__inline void AT91F_US_EnableRx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Enable receiver - pUSART->US_CR = AT91C_US_RXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_EnableTx -//* \brief Enable sending characters -//*---------------------------------------------------------------------------- -__inline void AT91F_US_EnableTx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Enable transmitter - pUSART->US_CR = AT91C_US_TXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_ResetRx -//* \brief Reset Receiver and re-enable it -//*---------------------------------------------------------------------------- -__inline void AT91F_US_ResetRx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Reset receiver - pUSART->US_CR = AT91C_US_RSTRX; - //* Re-Enable receiver - pUSART->US_CR = AT91C_US_RXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_ResetTx -//* \brief Reset Transmitter and re-enable it -//*---------------------------------------------------------------------------- -__inline void AT91F_US_ResetTx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Reset transmitter - pUSART->US_CR = AT91C_US_RSTTX; - //* Enable transmitter - pUSART->US_CR = AT91C_US_TXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_DisableRx -//* \brief Disable Receiver -//*---------------------------------------------------------------------------- -__inline void AT91F_US_DisableRx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Disable receiver - pUSART->US_CR = AT91C_US_RXDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_DisableTx -//* \brief Disable Transmitter -//*---------------------------------------------------------------------------- -__inline void AT91F_US_DisableTx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Disable transmitter - pUSART->US_CR = AT91C_US_TXDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Close -//* \brief Close USART: disable IT disable receiver and transmitter, close PDC -//*---------------------------------------------------------------------------- -__inline void AT91F_US_Close ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Reset the baud rate divisor register - pUSART->US_BRGR = 0 ; - - //* Reset the USART mode - pUSART->US_MR = 0 ; - - //* Reset the Timeguard Register - pUSART->US_TTGR = 0; - - //* Disable all interrupts - pUSART->US_IDR = 0xFFFFFFFF ; - - //* Abort the Peripheral Data Transfers - AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR)); - - //* Disable receiver and transmitter and stop any activity immediately - pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_TxReady -//* \brief Return 1 if a character can be written in US_THR -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_US_TxReady ( - AT91PS_USART pUSART ) // \arg pointer to a USART controller -{ - return (pUSART->US_CSR & AT91C_US_TXRDY); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_RxReady -//* \brief Return 1 if a character can be read in US_RHR -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_US_RxReady ( - AT91PS_USART pUSART ) // \arg pointer to a USART controller -{ - return (pUSART->US_CSR & AT91C_US_RXRDY); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Error -//* \brief Return the error flag -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_US_Error ( - AT91PS_USART pUSART ) // \arg pointer to a USART controller -{ - return (pUSART->US_CSR & - (AT91C_US_OVRE | // Overrun error - AT91C_US_FRAME | // Framing error - AT91C_US_PARE)); // Parity error -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_PutChar -//* \brief Send a character,does not check if ready to send -//*---------------------------------------------------------------------------- -__inline void AT91F_US_PutChar ( - AT91PS_USART pUSART, - int character ) -{ - pUSART->US_THR = (character & 0x1FF); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_GetChar -//* \brief Receive a character,does not check if a character is available -//*---------------------------------------------------------------------------- -__inline int AT91F_US_GetChar ( - const AT91PS_USART pUSART) -{ - return((pUSART->US_RHR) & 0x1FF); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_SendFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_US_SendFrame( - AT91PS_USART pUSART, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_SendFrame( - (AT91PS_PDC) &(pUSART->US_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_ReceiveFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_US_ReceiveFrame ( - AT91PS_USART pUSART, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_ReceiveFrame( - (AT91PS_PDC) &(pUSART->US_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_SetIrdaFilter -//* \brief Set the value of IrDa filter tregister -//*---------------------------------------------------------------------------- -__inline void AT91F_US_SetIrdaFilter ( - AT91PS_USART pUSART, - unsigned char value -) -{ - pUSART->US_IF = value; -} - -/* ***************************************************************************** - SOFTWARE API FOR SSC - ***************************************************************************** */ -//* Define the standard I2S mode configuration - -//* Configuration to set in the SSC Transmit Clock Mode Register -//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits -//* nb_slot_by_frame : number of channels -#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ - AT91C_SSC_CKS_DIV +\ - AT91C_SSC_CKO_CONTINOUS +\ - AT91C_SSC_CKG_NONE +\ - AT91C_SSC_START_FALL_RF +\ - AT91C_SSC_STTOUT +\ - ((1<<16) & AT91C_SSC_STTDLY) +\ - ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24)) - - -//* Configuration to set in the SSC Transmit Frame Mode Register -//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits -//* nb_slot_by_frame : number of channels -#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ - (nb_bit_by_slot-1) +\ - AT91C_SSC_MSBF +\ - (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\ - (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\ - AT91C_SSC_FSOS_NEGATIVE) - - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_SetBaudrate -//* \brief Set the baudrate according to the CPU clock -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_SetBaudrate ( - AT91PS_SSC pSSC, // \arg pointer to a SSC controller - unsigned int mainClock, // \arg peripheral clock - unsigned int speed) // \arg SSC baudrate -{ - unsigned int baud_value; - //* Define the baud rate divisor register - if (speed == 0) - baud_value = 0; - else - { - baud_value = (unsigned int) (mainClock * 10)/(2*speed); - if ((baud_value % 10) >= 5) - baud_value = (baud_value / 10) + 1; - else - baud_value /= 10; - } - - pSSC->SSC_CMR = baud_value; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_Configure -//* \brief Configure SSC -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_Configure ( - AT91PS_SSC pSSC, // \arg pointer to a SSC controller - unsigned int syst_clock, // \arg System Clock Frequency - unsigned int baud_rate, // \arg Expected Baud Rate Frequency - unsigned int clock_rx, // \arg Receiver Clock Parameters - unsigned int mode_rx, // \arg mode Register to be programmed - unsigned int clock_tx, // \arg Transmitter Clock Parameters - unsigned int mode_tx) // \arg mode Register to be programmed -{ - //* Disable interrupts - pSSC->SSC_IDR = (unsigned int) -1; - - //* Reset receiver and transmitter - pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ; - - //* Define the Clock Mode Register - AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate); - - //* Write the Receive Clock Mode Register - pSSC->SSC_RCMR = clock_rx; - - //* Write the Transmit Clock Mode Register - pSSC->SSC_TCMR = clock_tx; - - //* Write the Receive Frame Mode Register - pSSC->SSC_RFMR = mode_rx; - - //* Write the Transmit Frame Mode Register - pSSC->SSC_TFMR = mode_tx; - - //* Clear Transmit and Receive Counters - AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR)); - - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_EnableRx -//* \brief Enable receiving datas -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_EnableRx ( - AT91PS_SSC pSSC) // \arg pointer to a SSC controller -{ - //* Enable receiver - pSSC->SSC_CR = AT91C_SSC_RXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_DisableRx -//* \brief Disable receiving datas -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_DisableRx ( - AT91PS_SSC pSSC) // \arg pointer to a SSC controller -{ - //* Disable receiver - pSSC->SSC_CR = AT91C_SSC_RXDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_EnableTx -//* \brief Enable sending datas -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_EnableTx ( - AT91PS_SSC pSSC) // \arg pointer to a SSC controller -{ - //* Enable transmitter - pSSC->SSC_CR = AT91C_SSC_TXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_DisableTx -//* \brief Disable sending datas -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_DisableTx ( - AT91PS_SSC pSSC) // \arg pointer to a SSC controller -{ - //* Disable transmitter - pSSC->SSC_CR = AT91C_SSC_TXDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_EnableIt -//* \brief Enable SSC IT -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_EnableIt ( - AT91PS_SSC pSSC, // \arg pointer to a SSC controller - unsigned int flag) // \arg IT to be enabled -{ - //* Write to the IER register - pSSC->SSC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_DisableIt -//* \brief Disable SSC IT -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_DisableIt ( - AT91PS_SSC pSSC, // \arg pointer to a SSC controller - unsigned int flag) // \arg IT to be disabled -{ - //* Write to the IDR register - pSSC->SSC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_ReceiveFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SSC_ReceiveFrame ( - AT91PS_SSC pSSC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_ReceiveFrame( - (AT91PS_PDC) &(pSSC->SSC_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_SendFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SSC_SendFrame( - AT91PS_SSC pSSC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_SendFrame( - (AT91PS_PDC) &(pSSC->SSC_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_GetInterruptMaskStatus -//* \brief Return SSC Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status - AT91PS_SSC pSsc) // \arg pointer to a SSC controller -{ - return pSsc->SSC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_IsInterruptMasked -//* \brief Test if SSC Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_SSC_IsInterruptMasked( - AT91PS_SSC pSsc, // \arg pointer to a SSC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR TWI - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_EnableIt -//* \brief Enable TWI IT -//*---------------------------------------------------------------------------- -__inline void AT91F_TWI_EnableIt ( - AT91PS_TWI pTWI, // \arg pointer to a TWI controller - unsigned int flag) // \arg IT to be enabled -{ - //* Write to the IER register - pTWI->TWI_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_DisableIt -//* \brief Disable TWI IT -//*---------------------------------------------------------------------------- -__inline void AT91F_TWI_DisableIt ( - AT91PS_TWI pTWI, // \arg pointer to a TWI controller - unsigned int flag) // \arg IT to be disabled -{ - //* Write to the IDR register - pTWI->TWI_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_Configure -//* \brief Configure TWI in master mode -//*---------------------------------------------------------------------------- -__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI ) // \arg pointer to a TWI controller -{ - //* Disable interrupts - pTWI->TWI_IDR = (unsigned int) -1; - - //* Reset peripheral - pTWI->TWI_CR = AT91C_TWI_SWRST; - - //* Set Master mode - pTWI->TWI_CR = AT91C_TWI_MSEN; - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_GetInterruptMaskStatus -//* \brief Return TWI Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status - AT91PS_TWI pTwi) // \arg pointer to a TWI controller -{ - return pTwi->TWI_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_IsInterruptMasked -//* \brief Test if TWI Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_TWI_IsInterruptMasked( - AT91PS_TWI pTwi, // \arg pointer to a TWI controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR PWMC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_GetStatus -//* \brief Return PWM Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status - AT91PS_PWMC pPWM) // pointer to a PWM controller -{ - return pPWM->PWMC_SR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_InterruptEnable -//* \brief Enable PWM Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_InterruptEnable( - AT91PS_PWMC pPwm, // \arg pointer to a PWM controller - unsigned int flag) // \arg PWM interrupt to be enabled -{ - pPwm->PWMC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_InterruptDisable -//* \brief Disable PWM Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_InterruptDisable( - AT91PS_PWMC pPwm, // \arg pointer to a PWM controller - unsigned int flag) // \arg PWM interrupt to be disabled -{ - pPwm->PWMC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_GetInterruptMaskStatus -//* \brief Return PWM Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status - AT91PS_PWMC pPwm) // \arg pointer to a PWM controller -{ - return pPwm->PWMC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_IsInterruptMasked -//* \brief Test if PWM Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PWMC_IsInterruptMasked( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_IsStatusSet -//* \brief Test if PWM Interrupt is Set -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PWMC_IsStatusSet( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PWMC_GetStatus(pPWM) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_CfgChannel -//* \brief Test if PWM Interrupt is Set -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CfgChannel( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int channelId, // \arg PWM channel ID - unsigned int mode, // \arg PWM mode - unsigned int period, // \arg PWM period - unsigned int duty) // \arg PWM duty cycle -{ - pPWM->PWMC_CH[channelId].PWMC_CMR = mode; - pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty; - pPWM->PWMC_CH[channelId].PWMC_CPRDR = period; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_StartChannel -//* \brief Enable channel -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_StartChannel( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int flag) // \arg Channels IDs to be enabled -{ - pPWM->PWMC_ENA = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_StopChannel -//* \brief Disable channel -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_StopChannel( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int flag) // \arg Channels IDs to be enabled -{ - pPWM->PWMC_DIS = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_UpdateChannel -//* \brief Update Period or Duty Cycle -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_UpdateChannel( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int channelId, // \arg PWM channel ID - unsigned int update) // \arg Channels IDs to be enabled -{ - pPWM->PWMC_CH[channelId].PWMC_CUPDR = update; -} - -/* ***************************************************************************** - SOFTWARE API FOR UDP - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EnableIt -//* \brief Enable UDP IT -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EnableIt ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg IT to be enabled -{ - //* Write to the IER register - pUDP->UDP_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_DisableIt -//* \brief Disable UDP IT -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_DisableIt ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg IT to be disabled -{ - //* Write to the IDR register - pUDP->UDP_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_SetAddress -//* \brief Set UDP functional address -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_SetAddress ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char address) // \arg new UDP address -{ - pUDP->UDP_FADDR = (AT91C_UDP_FEN | address); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EnableEp -//* \brief Enable Endpoint -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EnableEp ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - pUDP->UDP_CSR[endpoint] |= AT91C_UDP_EPEDS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_DisableEp -//* \brief Enable Endpoint -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_DisableEp ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - pUDP->UDP_CSR[endpoint] &= ~AT91C_UDP_EPEDS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_SetState -//* \brief Set UDP Device state -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_SetState ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg new UDP address -{ - pUDP->UDP_GLBSTATE &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG); - pUDP->UDP_GLBSTATE |= flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_GetState -//* \brief return UDP Device state -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state - AT91PS_UDP pUDP) // \arg pointer to a UDP controller -{ - return (pUDP->UDP_GLBSTATE & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_ResetEp -//* \brief Reset UDP endpoint -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_ResetEp ( // \return the UDP device state - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg Endpoints to be reset -{ - pUDP->UDP_RSTEP = flag; - pUDP->UDP_RSTEP = 0; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpStall -//* \brief Endpoint will STALL requests -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EpStall( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpWrite -//* \brief Write value in the DPR -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EpWrite( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint, // \arg endpoint number - unsigned char value) // \arg value to be written in the DPR -{ - pUDP->UDP_FDR[endpoint] = value; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpRead -//* \brief Return value from the DPR -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_UDP_EpRead( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - return pUDP->UDP_FDR[endpoint]; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpEndOfWr -//* \brief Notify the UDP that values in DPR are ready to be sent -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EpEndOfWr( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpClear -//* \brief Clear flag in the endpoint CSR register -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EpClear( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint, // \arg endpoint number - unsigned int flag) // \arg flag to be cleared -{ - pUDP->UDP_CSR[endpoint] &= ~(flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpSet -//* \brief Set flag in the endpoint CSR register -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EpSet( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint, // \arg endpoint number - unsigned int flag) // \arg flag to be cleared -{ - pUDP->UDP_CSR[endpoint] |= flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpStatus -//* \brief Return the endpoint CSR register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_UDP_EpStatus( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - return pUDP->UDP_CSR[endpoint]; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_GetInterruptMaskStatus -//* \brief Return UDP Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status - AT91PS_UDP pUdp) // \arg pointer to a UDP controller -{ - return pUdp->UDP_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_IsInterruptMasked -//* \brief Test if UDP Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_UDP_IsInterruptMasked( - AT91PS_UDP pUdp, // \arg pointer to a UDP controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR TC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC_InterruptEnable -//* \brief Enable TC Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_TC_InterruptEnable( - AT91PS_TC pTc, // \arg pointer to a TC controller - unsigned int flag) // \arg TC interrupt to be enabled -{ - pTc->TC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC_InterruptDisable -//* \brief Disable TC Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_TC_InterruptDisable( - AT91PS_TC pTc, // \arg pointer to a TC controller - unsigned int flag) // \arg TC interrupt to be disabled -{ - pTc->TC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC_GetInterruptMaskStatus -//* \brief Return TC Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status - AT91PS_TC pTc) // \arg pointer to a TC controller -{ - return pTc->TC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC_IsInterruptMasked -//* \brief Test if TC Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_TC_IsInterruptMasked( - AT91PS_TC pTc, // \arg pointer to a TC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR CAN - ***************************************************************************** */ -#define STANDARD_FORMAT 0 -#define EXTENDED_FORMAT 1 - -//*---------------------------------------------------------------------------- -//* \fn AT91F_InitMailboxRegisters() -//* \brief Configure the corresponding mailbox -//*---------------------------------------------------------------------------- -__inline void AT91F_InitMailboxRegisters(AT91PS_CAN_MB CAN_Mailbox, - int mode_reg, - int acceptance_mask_reg, - int id_reg, - int data_low_reg, - int data_high_reg, - int control_reg) -{ - CAN_Mailbox->CAN_MB_MCR = 0x0; - CAN_Mailbox->CAN_MB_MMR = mode_reg; - CAN_Mailbox->CAN_MB_MAM = acceptance_mask_reg; - CAN_Mailbox->CAN_MB_MID = id_reg; - CAN_Mailbox->CAN_MB_MDL = data_low_reg; - CAN_Mailbox->CAN_MB_MDH = data_high_reg; - CAN_Mailbox->CAN_MB_MCR = control_reg; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_EnableCAN() -//* \brief -//*---------------------------------------------------------------------------- -__inline void AT91F_EnableCAN( - AT91PS_CAN pCAN) // pointer to a CAN controller -{ - pCAN->CAN_MR |= AT91C_CAN_CANEN; - - // Wait for WAKEUP flag raising <=> 11-recessive-bit were scanned by the transceiver - while( (pCAN->CAN_SR & AT91C_CAN_WAKEUP) != AT91C_CAN_WAKEUP ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DisableCAN() -//* \brief -//*---------------------------------------------------------------------------- -__inline void AT91F_DisableCAN( - AT91PS_CAN pCAN) // pointer to a CAN controller -{ - pCAN->CAN_MR &= ~AT91C_CAN_CANEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_EnableIt -//* \brief Enable CAN interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_EnableIt ( - AT91PS_CAN pCAN, // pointer to a CAN controller - unsigned int flag) // IT to be enabled -{ - //* Write to the IER register - pCAN->CAN_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_DisableIt -//* \brief Disable CAN interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_DisableIt ( - AT91PS_CAN pCAN, // pointer to a CAN controller - unsigned int flag) // IT to be disabled -{ - //* Write to the IDR register - pCAN->CAN_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetStatus -//* \brief Return CAN Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetStatus( // \return CAN Interrupt Status - AT91PS_CAN pCAN) // pointer to a CAN controller -{ - return pCAN->CAN_SR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetInterruptMaskStatus -//* \brief Return CAN Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetInterruptMaskStatus( // \return CAN Interrupt Mask Status - AT91PS_CAN pCAN) // pointer to a CAN controller -{ - return pCAN->CAN_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_IsInterruptMasked -//* \brief Test if CAN Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_IsInterruptMasked( - AT91PS_CAN pCAN, // \arg pointer to a CAN controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_CAN_GetInterruptMaskStatus(pCAN) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_IsStatusSet -//* \brief Test if CAN Interrupt is Set -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_IsStatusSet( - AT91PS_CAN pCAN, // \arg pointer to a CAN controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_CAN_GetStatus(pCAN) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgModeReg -//* \brief Configure the Mode Register of the CAN controller -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgModeReg ( - AT91PS_CAN pCAN, // pointer to a CAN controller - unsigned int mode) // mode register -{ - //* Write to the MR register - pCAN->CAN_MR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetModeReg -//* \brief Return the Mode Register of the CAN controller value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetModeReg ( - AT91PS_CAN pCAN // pointer to a CAN controller - ) -{ - return pCAN->CAN_MR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgBaudrateReg -//* \brief Configure the Baudrate of the CAN controller for the network -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgBaudrateReg ( - AT91PS_CAN pCAN, // pointer to a CAN controller - unsigned int baudrate_cfg) -{ - //* Write to the BR register - pCAN->CAN_BR = baudrate_cfg; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetBaudrate -//* \brief Return the Baudrate of the CAN controller for the network value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetBaudrate ( - AT91PS_CAN pCAN // pointer to a CAN controller - ) -{ - return pCAN->CAN_BR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetInternalCounter -//* \brief Return CAN Timer Regsiter Value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetInternalCounter ( - AT91PS_CAN pCAN // pointer to a CAN controller - ) -{ - return pCAN->CAN_TIM; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetTimestamp -//* \brief Return CAN Timestamp Register Value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetTimestamp ( - AT91PS_CAN pCAN // pointer to a CAN controller - ) -{ - return pCAN->CAN_TIMESTP; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetErrorCounter -//* \brief Return CAN Error Counter Register Value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetErrorCounter ( - AT91PS_CAN pCAN // pointer to a CAN controller - ) -{ - return pCAN->CAN_ECR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_InitTransferRequest -//* \brief Request for a transfer on the corresponding mailboxes -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_InitTransferRequest ( - AT91PS_CAN pCAN, // pointer to a CAN controller - unsigned int transfer_cmd) -{ - pCAN->CAN_TCR = transfer_cmd; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_InitAbortRequest -//* \brief Abort the corresponding mailboxes -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_InitAbortRequest ( - AT91PS_CAN pCAN, // pointer to a CAN controller - unsigned int abort_cmd) -{ - pCAN->CAN_ACR = abort_cmd; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgMessageModeReg -//* \brief Program the Message Mode Register -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgMessageModeReg ( - AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox - unsigned int mode) -{ - CAN_Mailbox->CAN_MB_MMR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetMessageModeReg -//* \brief Return the Message Mode Register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetMessageModeReg ( - AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox -{ - return CAN_Mailbox->CAN_MB_MMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgMessageIDReg -//* \brief Program the Message ID Register -//* \brief Version == 0 for Standard messsage, Version == 1 for Extended -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgMessageIDReg ( - AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox - unsigned int id, - unsigned char version) -{ - if(version==0) // IDvA Standard Format - CAN_Mailbox->CAN_MB_MID = id<<18; - else // IDvB Extended Format - CAN_Mailbox->CAN_MB_MID = id | (1<<29); // set MIDE bit -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetMessageIDReg -//* \brief Return the Message ID Register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetMessageIDReg ( - AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox -{ - return CAN_Mailbox->CAN_MB_MID; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgMessageAcceptanceMaskReg -//* \brief Program the Message Acceptance Mask Register -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgMessageAcceptanceMaskReg ( - AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox - unsigned int mask) -{ - CAN_Mailbox->CAN_MB_MAM = mask; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetMessageAcceptanceMaskReg -//* \brief Return the Message Acceptance Mask Register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetMessageAcceptanceMaskReg ( - AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox -{ - return CAN_Mailbox->CAN_MB_MAM; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetFamilyID -//* \brief Return the Message ID Register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetFamilyID ( - AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox -{ - return CAN_Mailbox->CAN_MB_MFID; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgMessageCtrl -//* \brief Request and config for a transfer on the corresponding mailbox -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgMessageCtrlReg ( - AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox - unsigned int message_ctrl_cmd) -{ - CAN_Mailbox->CAN_MB_MCR = message_ctrl_cmd; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetMessageStatus -//* \brief Return CAN Mailbox Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetMessageStatus ( - AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox -{ - return CAN_Mailbox->CAN_MB_MSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgMessageDataLow -//* \brief Program data low value -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgMessageDataLow ( - AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox - unsigned int data) -{ - CAN_Mailbox->CAN_MB_MDL = data; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetMessageDataLow -//* \brief Return data low value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetMessageDataLow ( - AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox -{ - return CAN_Mailbox->CAN_MB_MDL; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgMessageDataHigh -//* \brief Program data high value -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgMessageDataHigh ( - AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox - unsigned int data) -{ - CAN_Mailbox->CAN_MB_MDH = data; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetMessageDataHigh -//* \brief Return data high value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetMessageDataHigh ( - AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox -{ - return CAN_Mailbox->CAN_MB_MDH; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_Open -//* \brief Open a CAN Port -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_Open ( - const unsigned int null) // \arg -{ - /* NOT DEFINED AT THIS MOMENT */ - return ( 0 ); -} -/* ***************************************************************************** - SOFTWARE API FOR ADC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_EnableIt -//* \brief Enable ADC interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_EnableIt ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int flag) // IT to be enabled -{ - //* Write to the IER register - pADC->ADC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_DisableIt -//* \brief Disable ADC interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_DisableIt ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int flag) // IT to be disabled -{ - //* Write to the IDR register - pADC->ADC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetStatus -//* \brief Return ADC Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status - AT91PS_ADC pADC) // pointer to a ADC controller -{ - return pADC->ADC_SR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetInterruptMaskStatus -//* \brief Return ADC Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status - AT91PS_ADC pADC) // pointer to a ADC controller -{ - return pADC->ADC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_IsInterruptMasked -//* \brief Test if ADC Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_IsInterruptMasked( - AT91PS_ADC pADC, // \arg pointer to a ADC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_IsStatusSet -//* \brief Test if ADC Status is Set -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_IsStatusSet( - AT91PS_ADC pADC, // \arg pointer to a ADC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_ADC_GetStatus(pADC) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_CfgModeReg -//* \brief Configure the Mode Register of the ADC controller -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_CfgModeReg ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int mode) // mode register -{ - //* Write to the MR register - pADC->ADC_MR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetModeReg -//* \brief Return the Mode Register of the ADC controller value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetModeReg ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_MR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_CfgTimings -//* \brief Configure the different necessary timings of the ADC controller -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_CfgTimings ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int mck_clock, // in MHz - unsigned int adc_clock, // in MHz - unsigned int startup_time, // in us - unsigned int sample_and_hold_time) // in ns -{ - unsigned int prescal,startup,shtim; - - prescal = mck_clock/(2*adc_clock) - 1; - startup = adc_clock*startup_time/8 - 1; - shtim = adc_clock*sample_and_hold_time/1000 - 1; - - //* Write to the MR register - pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_EnableChannel -//* \brief Return ADC Timer Register Value -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_EnableChannel ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int channel) // mode register -{ - //* Write to the CHER register - pADC->ADC_CHER = channel; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_DisableChannel -//* \brief Return ADC Timer Register Value -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_DisableChannel ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int channel) // mode register -{ - //* Write to the CHDR register - pADC->ADC_CHDR = channel; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetChannelStatus -//* \brief Return ADC Timer Register Value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetChannelStatus ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CHSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_StartConversion -//* \brief Software request for a analog to digital conversion -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_StartConversion ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - pADC->ADC_CR = AT91C_ADC_START; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_SoftReset -//* \brief Software reset -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_SoftReset ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - pADC->ADC_CR = AT91C_ADC_SWRST; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetLastConvertedData -//* \brief Return the Last Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetLastConvertedData ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_LCDR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH0 -//* \brief Return the Channel 0 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH0 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR0; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH1 -//* \brief Return the Channel 1 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH1 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR1; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH2 -//* \brief Return the Channel 2 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH2 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR2; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH3 -//* \brief Return the Channel 3 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH3 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR3; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH4 -//* \brief Return the Channel 4 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH4 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR4; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH5 -//* \brief Return the Channel 5 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH5 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR5; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH6 -//* \brief Return the Channel 6 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH6 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR6; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH7 -//* \brief Return the Channel 7 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH7 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR7; -} - -/* ***************************************************************************** - SOFTWARE API FOR AES - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_EnableIt -//* \brief Enable AES interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_AES_EnableIt ( - AT91PS_AES pAES, // pointer to a AES controller - unsigned int flag) // IT to be enabled -{ - //* Write to the IER register - pAES->AES_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_DisableIt -//* \brief Disable AES interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_AES_DisableIt ( - AT91PS_AES pAES, // pointer to a AES controller - unsigned int flag) // IT to be disabled -{ - //* Write to the IDR register - pAES->AES_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_GetStatus -//* \brief Return AES Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AES_GetStatus( // \return AES Interrupt Status - AT91PS_AES pAES) // pointer to a AES controller -{ - return pAES->AES_ISR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_GetInterruptMaskStatus -//* \brief Return AES Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AES_GetInterruptMaskStatus( // \return AES Interrupt Mask Status - AT91PS_AES pAES) // pointer to a AES controller -{ - return pAES->AES_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_IsInterruptMasked -//* \brief Test if AES Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AES_IsInterruptMasked( - AT91PS_AES pAES, // \arg pointer to a AES controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_AES_GetInterruptMaskStatus(pAES) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_IsStatusSet -//* \brief Test if AES Status is Set -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AES_IsStatusSet( - AT91PS_AES pAES, // \arg pointer to a AES controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_AES_GetStatus(pAES) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_CfgModeReg -//* \brief Configure the Mode Register of the AES controller -//*---------------------------------------------------------------------------- -__inline void AT91F_AES_CfgModeReg ( - AT91PS_AES pAES, // pointer to a AES controller - unsigned int mode) // mode register -{ - //* Write to the MR register - pAES->AES_MR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_GetModeReg -//* \brief Return the Mode Register of the AES controller value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AES_GetModeReg ( - AT91PS_AES pAES // pointer to a AES controller - ) -{ - return pAES->AES_MR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_StartProcessing -//* \brief Start Encryption or Decryption -//*---------------------------------------------------------------------------- -__inline void AT91F_AES_StartProcessing ( - AT91PS_AES pAES // pointer to a AES controller - ) -{ - pAES->AES_CR = AT91C_AES_START; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_SoftReset -//* \brief Reset AES -//*---------------------------------------------------------------------------- -__inline void AT91F_AES_SoftReset ( - AT91PS_AES pAES // pointer to a AES controller - ) -{ - pAES->AES_CR = AT91C_AES_SWRST; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_LoadNewSeed -//* \brief Load New Seed in the random number generator -//*---------------------------------------------------------------------------- -__inline void AT91F_AES_LoadNewSeed ( - AT91PS_AES pAES // pointer to a AES controller - ) -{ - pAES->AES_CR = AT91C_AES_LOADSEED; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_SetCryptoKey -//* \brief Set Cryptographic Key x -//*---------------------------------------------------------------------------- -__inline void AT91F_AES_SetCryptoKey ( - AT91PS_AES pAES, // pointer to a AES controller - unsigned char index, - unsigned int keyword - ) -{ - pAES->AES_KEYWxR[index] = keyword; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_InputData -//* \brief Set Input Data x -//*---------------------------------------------------------------------------- -__inline void AT91F_AES_InputData ( - AT91PS_AES pAES, // pointer to a AES controller - unsigned char index, - unsigned int indata - ) -{ - pAES->AES_IDATAxR[index] = indata; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_GetOutputData -//* \brief Get Output Data x -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AES_GetOutputData ( - AT91PS_AES pAES, // pointer to a AES controller - unsigned char index - ) -{ - return pAES->AES_ODATAxR[index]; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_SetInitializationVector -//* \brief Set Initialization Vector (or Counter) x -//*---------------------------------------------------------------------------- -__inline void AT91F_AES_SetInitializationVector ( - AT91PS_AES pAES, // pointer to a AES controller - unsigned char index, - unsigned int initvector - ) -{ - pAES->AES_IVxR[index] = initvector; -} - -/* ***************************************************************************** - SOFTWARE API FOR TDES - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_EnableIt -//* \brief Enable TDES interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_TDES_EnableIt ( - AT91PS_TDES pTDES, // pointer to a TDES controller - unsigned int flag) // IT to be enabled -{ - //* Write to the IER register - pTDES->TDES_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_DisableIt -//* \brief Disable TDES interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_TDES_DisableIt ( - AT91PS_TDES pTDES, // pointer to a TDES controller - unsigned int flag) // IT to be disabled -{ - //* Write to the IDR register - pTDES->TDES_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_GetStatus -//* \brief Return TDES Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_TDES_GetStatus( // \return TDES Interrupt Status - AT91PS_TDES pTDES) // pointer to a TDES controller -{ - return pTDES->TDES_ISR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_GetInterruptMaskStatus -//* \brief Return TDES Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_TDES_GetInterruptMaskStatus( // \return TDES Interrupt Mask Status - AT91PS_TDES pTDES) // pointer to a TDES controller -{ - return pTDES->TDES_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_IsInterruptMasked -//* \brief Test if TDES Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_TDES_IsInterruptMasked( - AT91PS_TDES pTDES, // \arg pointer to a TDES controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_TDES_GetInterruptMaskStatus(pTDES) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_IsStatusSet -//* \brief Test if TDES Status is Set -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_TDES_IsStatusSet( - AT91PS_TDES pTDES, // \arg pointer to a TDES controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_TDES_GetStatus(pTDES) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_CfgModeReg -//* \brief Configure the Mode Register of the TDES controller -//*---------------------------------------------------------------------------- -__inline void AT91F_TDES_CfgModeReg ( - AT91PS_TDES pTDES, // pointer to a TDES controller - unsigned int mode) // mode register -{ - //* Write to the MR register - pTDES->TDES_MR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_GetModeReg -//* \brief Return the Mode Register of the TDES controller value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_TDES_GetModeReg ( - AT91PS_TDES pTDES // pointer to a TDES controller - ) -{ - return pTDES->TDES_MR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_StartProcessing -//* \brief Start Encryption or Decryption -//*---------------------------------------------------------------------------- -__inline void AT91F_TDES_StartProcessing ( - AT91PS_TDES pTDES // pointer to a TDES controller - ) -{ - pTDES->TDES_CR = AT91C_TDES_START; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_SoftReset -//* \brief Reset TDES -//*---------------------------------------------------------------------------- -__inline void AT91F_TDES_SoftReset ( - AT91PS_TDES pTDES // pointer to a TDES controller - ) -{ - pTDES->TDES_CR = AT91C_TDES_SWRST; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_SetCryptoKey1 -//* \brief Set Cryptographic Key 1 Word x -//*---------------------------------------------------------------------------- -__inline void AT91F_TDES_SetCryptoKey1 ( - AT91PS_TDES pTDES, // pointer to a TDES controller - unsigned char index, - unsigned int keyword - ) -{ - pTDES->TDES_KEY1WxR[index] = keyword; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_SetCryptoKey2 -//* \brief Set Cryptographic Key 2 Word x -//*---------------------------------------------------------------------------- -__inline void AT91F_TDES_SetCryptoKey2 ( - AT91PS_TDES pTDES, // pointer to a TDES controller - unsigned char index, - unsigned int keyword - ) -{ - pTDES->TDES_KEY2WxR[index] = keyword; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_SetCryptoKey3 -//* \brief Set Cryptographic Key 3 Word x -//*---------------------------------------------------------------------------- -__inline void AT91F_TDES_SetCryptoKey3 ( - AT91PS_TDES pTDES, // pointer to a TDES controller - unsigned char index, - unsigned int keyword - ) -{ - pTDES->TDES_KEY3WxR[index] = keyword; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_InputData -//* \brief Set Input Data x -//*---------------------------------------------------------------------------- -__inline void AT91F_TDES_InputData ( - AT91PS_TDES pTDES, // pointer to a TDES controller - unsigned char index, - unsigned int indata - ) -{ - pTDES->TDES_IDATAxR[index] = indata; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_GetOutputData -//* \brief Get Output Data x -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_TDES_GetOutputData ( - AT91PS_TDES pTDES, // pointer to a TDES controller - unsigned char index - ) -{ - return pTDES->TDES_ODATAxR[index]; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_SetInitializationVector -//* \brief Set Initialization Vector x -//*---------------------------------------------------------------------------- -__inline void AT91F_TDES_SetInitializationVector ( - AT91PS_TDES pTDES, // pointer to a TDES controller - unsigned char index, - unsigned int initvector - ) -{ - pTDES->TDES_IVxR[index] = initvector; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_CfgPMC -//* \brief Enable Peripheral clock in PMC for DBGU -//*---------------------------------------------------------------------------- -__inline void AT91F_DBGU_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_CfgPIO -//* \brief Configure PIO controllers to drive DBGU signals -//*---------------------------------------------------------------------------- -__inline void AT91F_DBGU_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA27_DRXD ) | - ((unsigned int) AT91C_PA28_DTXD ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgPMC -//* \brief Enable Peripheral clock in PMC for PMC -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgPIO -//* \brief Configure PIO controllers to drive PMC signals -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB30_PCK2 ) | - ((unsigned int) AT91C_PB29_PCK1 ), // Peripheral A - ((unsigned int) AT91C_PB20_PCK0 ) | - ((unsigned int) AT91C_PB0_PCK0 ) | - ((unsigned int) AT91C_PB22_PCK2 ) | - ((unsigned int) AT91C_PB21_PCK1 )); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PA30_PCK2 ) | - ((unsigned int) AT91C_PA13_PCK1 ) | - ((unsigned int) AT91C_PA27_PCK3 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_VREG_CfgPMC -//* \brief Enable Peripheral clock in PMC for VREG -//*---------------------------------------------------------------------------- -__inline void AT91F_VREG_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTC_CfgPMC -//* \brief Enable Peripheral clock in PMC for RSTC -//*---------------------------------------------------------------------------- -__inline void AT91F_RSTC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_CfgPMC -//* \brief Enable Peripheral clock in PMC for SSC -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SSC)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_CfgPIO -//* \brief Configure PIO controllers to drive SSC signals -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA25_RK ) | - ((unsigned int) AT91C_PA22_TK ) | - ((unsigned int) AT91C_PA21_TF ) | - ((unsigned int) AT91C_PA24_RD ) | - ((unsigned int) AT91C_PA26_RF ) | - ((unsigned int) AT91C_PA23_TD ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_WDTC_CfgPMC -//* \brief Enable Peripheral clock in PMC for WDTC -//*---------------------------------------------------------------------------- -__inline void AT91F_WDTC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US1_CfgPMC -//* \brief Enable Peripheral clock in PMC for US1 -//*---------------------------------------------------------------------------- -__inline void AT91F_US1_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_US1)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US1_CfgPIO -//* \brief Configure PIO controllers to drive US1 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_US1_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PB26_RI1 ) | - ((unsigned int) AT91C_PB24_DSR1 ) | - ((unsigned int) AT91C_PB23_DCD1 ) | - ((unsigned int) AT91C_PB25_DTR1 )); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA7_SCK1 ) | - ((unsigned int) AT91C_PA8_RTS1 ) | - ((unsigned int) AT91C_PA6_TXD1 ) | - ((unsigned int) AT91C_PA5_RXD1 ) | - ((unsigned int) AT91C_PA9_CTS1 ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US0_CfgPMC -//* \brief Enable Peripheral clock in PMC for US0 -//*---------------------------------------------------------------------------- -__inline void AT91F_US0_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_US0)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US0_CfgPIO -//* \brief Configure PIO controllers to drive US0 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_US0_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA0_RXD0 ) | - ((unsigned int) AT91C_PA4_CTS0 ) | - ((unsigned int) AT91C_PA3_RTS0 ) | - ((unsigned int) AT91C_PA2_SCK0 ) | - ((unsigned int) AT91C_PA1_TXD0 ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI1_CfgPMC -//* \brief Enable Peripheral clock in PMC for SPI1 -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI1_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SPI1)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI1_CfgPIO -//* \brief Configure PIO controllers to drive SPI1 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI1_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PB16_NPCS13 ) | - ((unsigned int) AT91C_PB10_NPCS11 ) | - ((unsigned int) AT91C_PB11_NPCS12 )); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PA4_NPCS13 ) | - ((unsigned int) AT91C_PA29_NPCS13 ) | - ((unsigned int) AT91C_PA21_NPCS10 ) | - ((unsigned int) AT91C_PA22_SPCK1 ) | - ((unsigned int) AT91C_PA25_NPCS11 ) | - ((unsigned int) AT91C_PA2_NPCS11 ) | - ((unsigned int) AT91C_PA24_MISO1 ) | - ((unsigned int) AT91C_PA3_NPCS12 ) | - ((unsigned int) AT91C_PA26_NPCS12 ) | - ((unsigned int) AT91C_PA23_MOSI1 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI0_CfgPMC -//* \brief Enable Peripheral clock in PMC for SPI0 -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI0_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SPI0)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI0_CfgPIO -//* \brief Configure PIO controllers to drive SPI0 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI0_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PB13_NPCS01 ) | - ((unsigned int) AT91C_PB17_NPCS03 ) | - ((unsigned int) AT91C_PB14_NPCS02 )); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA16_MISO0 ) | - ((unsigned int) AT91C_PA13_NPCS01 ) | - ((unsigned int) AT91C_PA15_NPCS03 ) | - ((unsigned int) AT91C_PA17_MOSI0 ) | - ((unsigned int) AT91C_PA18_SPCK0 ) | - ((unsigned int) AT91C_PA14_NPCS02 ) | - ((unsigned int) AT91C_PA12_NPCS00 ), // Peripheral A - ((unsigned int) AT91C_PA7_NPCS01 ) | - ((unsigned int) AT91C_PA9_NPCS03 ) | - ((unsigned int) AT91C_PA8_NPCS02 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITC_CfgPMC -//* \brief Enable Peripheral clock in PMC for PITC -//*---------------------------------------------------------------------------- -__inline void AT91F_PITC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_CfgPMC -//* \brief Enable Peripheral clock in PMC for AIC -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_FIQ) | - ((unsigned int) 1 << AT91C_ID_IRQ0) | - ((unsigned int) 1 << AT91C_ID_IRQ1)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_CfgPIO -//* \brief Configure PIO controllers to drive AIC signals -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA30_IRQ0 ) | - ((unsigned int) AT91C_PA29_FIQ ), // Peripheral A - ((unsigned int) AT91C_PA14_IRQ1 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_CfgPMC -//* \brief Enable Peripheral clock in PMC for AES -//*---------------------------------------------------------------------------- -__inline void AT91F_AES_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_AES)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_CfgPMC -//* \brief Enable Peripheral clock in PMC for TWI -//*---------------------------------------------------------------------------- -__inline void AT91F_TWI_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TWI)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_CfgPIO -//* \brief Configure PIO controllers to drive TWI signals -//*---------------------------------------------------------------------------- -__inline void AT91F_TWI_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA11_TWCK ) | - ((unsigned int) AT91C_PA10_TWD ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_CfgPMC -//* \brief Enable Peripheral clock in PMC for ADC -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_ADC)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_CfgPIO -//* \brief Configure PIO controllers to drive ADC signals -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PB18_ADTRG )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CH3_CfgPIO -//* \brief Configure PIO controllers to drive PWMC_CH3 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CH3_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB22_PWM3 ), // Peripheral A - ((unsigned int) AT91C_PB30_PWM3 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CH2_CfgPIO -//* \brief Configure PIO controllers to drive PWMC_CH2 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CH2_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB21_PWM2 ), // Peripheral A - ((unsigned int) AT91C_PB29_PWM2 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CH1_CfgPIO -//* \brief Configure PIO controllers to drive PWMC_CH1 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CH1_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB20_PWM1 ), // Peripheral A - ((unsigned int) AT91C_PB28_PWM1 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CH0_CfgPIO -//* \brief Configure PIO controllers to drive PWMC_CH0 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CH0_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB19_PWM0 ), // Peripheral A - ((unsigned int) AT91C_PB27_PWM0 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RTTC_CfgPMC -//* \brief Enable Peripheral clock in PMC for RTTC -//*---------------------------------------------------------------------------- -__inline void AT91F_RTTC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_CfgPMC -//* \brief Enable Peripheral clock in PMC for UDP -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_UDP)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_CfgPMC -//* \brief Enable Peripheral clock in PMC for TDES -//*---------------------------------------------------------------------------- -__inline void AT91F_TDES_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TDES)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_EMAC_CfgPMC -//* \brief Enable Peripheral clock in PMC for EMAC -//*---------------------------------------------------------------------------- -__inline void AT91F_EMAC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_EMAC)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_EMAC_CfgPIO -//* \brief Configure PIO controllers to drive EMAC signals -//*---------------------------------------------------------------------------- -__inline void AT91F_EMAC_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB2_ETX0 ) | - ((unsigned int) AT91C_PB12_ETXER ) | - ((unsigned int) AT91C_PB16_ECOL ) | - ((unsigned int) AT91C_PB11_ETX3 ) | - ((unsigned int) AT91C_PB6_ERX1 ) | - ((unsigned int) AT91C_PB15_ERXDV ) | - ((unsigned int) AT91C_PB13_ERX2 ) | - ((unsigned int) AT91C_PB3_ETX1 ) | - ((unsigned int) AT91C_PB8_EMDC ) | - ((unsigned int) AT91C_PB5_ERX0 ) | - //((unsigned int) AT91C_PB18_EF100 ) | - ((unsigned int) AT91C_PB14_ERX3 ) | - ((unsigned int) AT91C_PB4_ECRS_ECRSDV) | - ((unsigned int) AT91C_PB1_ETXEN ) | - ((unsigned int) AT91C_PB10_ETX2 ) | - ((unsigned int) AT91C_PB0_ETXCK_EREFCK) | - ((unsigned int) AT91C_PB9_EMDIO ) | - ((unsigned int) AT91C_PB7_ERXER ) | - ((unsigned int) AT91C_PB17_ERXCK ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC0_CfgPMC -//* \brief Enable Peripheral clock in PMC for TC0 -//*---------------------------------------------------------------------------- -__inline void AT91F_TC0_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TC0)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC0_CfgPIO -//* \brief Configure PIO controllers to drive TC0 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_TC0_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB23_TIOA0 ) | - ((unsigned int) AT91C_PB24_TIOB0 ), // Peripheral A - ((unsigned int) AT91C_PB12_TCLK0 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC1_CfgPMC -//* \brief Enable Peripheral clock in PMC for TC1 -//*---------------------------------------------------------------------------- -__inline void AT91F_TC1_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TC1)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC1_CfgPIO -//* \brief Configure PIO controllers to drive TC1 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_TC1_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB25_TIOA1 ) | - ((unsigned int) AT91C_PB26_TIOB1 ), // Peripheral A - ((unsigned int) AT91C_PB19_TCLK1 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC2_CfgPMC -//* \brief Enable Peripheral clock in PMC for TC2 -//*---------------------------------------------------------------------------- -__inline void AT91F_TC2_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TC2)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC2_CfgPIO -//* \brief Configure PIO controllers to drive TC2 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_TC2_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB28_TIOB2 ) | - ((unsigned int) AT91C_PB27_TIOA2 ), // Peripheral A - 0); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PA15_TCLK2 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_CfgPMC -//* \brief Enable Peripheral clock in PMC for MC -//*---------------------------------------------------------------------------- -__inline void AT91F_MC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIOA_CfgPMC -//* \brief Enable Peripheral clock in PMC for PIOA -//*---------------------------------------------------------------------------- -__inline void AT91F_PIOA_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_PIOA)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIOB_CfgPMC -//* \brief Enable Peripheral clock in PMC for PIOB -//*---------------------------------------------------------------------------- -__inline void AT91F_PIOB_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_PIOB)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgPMC -//* \brief Enable Peripheral clock in PMC for CAN -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_CAN)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgPIO -//* \brief Configure PIO controllers to drive CAN signals -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA20_CANTX ) | - ((unsigned int) AT91C_PA19_CANRX ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CfgPMC -//* \brief Enable Peripheral clock in PMC for PWMC -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_PWMC)); -} - -#endif // lib_AT91SAM7X256_H diff --git a/Source/portable/GCC/ARM7_AT91SAM7S/port.c b/Source/portable/GCC/ARM7_AT91SAM7S/port.c deleted file mode 100644 index 8af844803..000000000 --- a/Source/portable/GCC/ARM7_AT91SAM7S/port.c +++ /dev/null @@ -1,222 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the ARM7 port. - * - * Components that can be compiled to either ARM or THUMB mode are - * contained in this file. The ISR routines, which can only be compiled - * to ARM mode are contained in portISR.c. - *----------------------------------------------------------*/ - -/* - Changes from V2.5.2 - - + ulCriticalNesting is now saved as part of the task context, as is - therefore added to the initial task stack during pxPortInitialiseStack. -*/ - - -/* Standard includes. */ -#include - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Processor constants. */ -#include "AT91SAM7X256.h" - -/* Constants required to setup the task context. */ -#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ -#define portTHUMB_MODE_BIT ( ( portSTACK_TYPE ) 0x20 ) -#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 ) -#define portNO_CRITICAL_SECTION_NESTING ( ( portSTACK_TYPE ) 0 ) - -/* Constants required to setup the tick ISR. */ -#define portENABLE_TIMER ( ( unsigned portCHAR ) 0x01 ) -#define portPRESCALE_VALUE 0x00 -#define portINTERRUPT_ON_MATCH ( ( unsigned portLONG ) 0x01 ) -#define portRESET_COUNT_ON_MATCH ( ( unsigned portLONG ) 0x02 ) - -/* Constants required to setup the PIT. */ -#define portPIT_CLOCK_DIVISOR ( ( unsigned portLONG ) 16 ) -#define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_RATE_MS ) - -#define portINT_LEVEL_SENSITIVE 0 -#define portPIT_ENABLE ( ( unsigned portSHORT ) 0x1 << 24 ) -#define portPIT_INT_ENABLE ( ( unsigned portSHORT ) 0x1 << 25 ) -/*-----------------------------------------------------------*/ - -/* Setup the timer to generate the tick interrupts. */ -static void prvSetupTimerInterrupt( void ); - -/* - * The scheduler can only be started from ARM mode, so - * vPortISRStartFirstSTask() is defined in portISR.c. - */ -extern void vPortISRStartFirstTask( void ); - -/*-----------------------------------------------------------*/ - -/* - * Initialise the stack of a task to look exactly as if a call to - * portSAVE_CONTEXT had been called. - * - * See header file for description. - */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) -{ -portSTACK_TYPE *pxOriginalTOS; - - pxOriginalTOS = pxTopOfStack; - - /* Setup the initial stack of the task. The stack is set exactly as - expected by the portRESTORE_CONTEXT() macro. */ - - /* First on the stack is the return address - which in this case is the - start of the task. The offset is added to make the return address appear - as it would within an IRQ ISR. */ - *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; - pxTopOfStack--; - - *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */ - pxTopOfStack--; - - /* When the task starts is will expect to find the function parameter in - R0. */ - *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ - pxTopOfStack--; - - /* The last thing onto the stack is the status register, which is set for - system mode, with interrupts enabled. */ - *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR; - - #ifdef THUMB_INTERWORK - { - /* We want the task to start in thumb mode. */ - *pxTopOfStack |= portTHUMB_MODE_BIT; - } - #endif - - pxTopOfStack--; - - /* Some optimisation levels use the stack differently to others. This - means the interrupt flags cannot always be stored on the stack and will - instead be stored in a variable, which is then saved as part of the - tasks context. */ - *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING; - - return pxTopOfStack; -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xPortStartScheduler( void ) -{ - /* Start the timer that generates the tick ISR. Interrupts are disabled - here already. */ - prvSetupTimerInterrupt(); - - /* Start the first task. */ - vPortISRStartFirstTask(); - - /* Should not get here! */ - return 0; -} -/*-----------------------------------------------------------*/ - -void vPortEndScheduler( void ) -{ - /* It is unlikely that the ARM port will require this function as there - is nothing to return to. */ -} -/*-----------------------------------------------------------*/ - -/* - * Setup the timer 0 to generate the tick interrupts at the required frequency. - */ -static void prvSetupTimerInterrupt( void ) -{ -AT91PS_PITC pxPIT = AT91C_BASE_PITC; - - /* Setup the AIC for PIT interrupts. The interrupt routine chosen depends - on whether the preemptive or cooperative scheduler is being used. */ - #if configUSE_PREEMPTION == 0 - - extern void ( vNonPreemptiveTick ) ( void ); - AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vNonPreemptiveTick ); - - #else - - extern void ( vPreemptiveTick )( void ); - AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPreemptiveTick ); - - #endif - - /* Configure the PIT period. */ - pxPIT->PITC_PIMR = portPIT_ENABLE | portPIT_INT_ENABLE | portPIT_COUNTER_VALUE; - - /* Enable the interrupt. Global interrupts are disables at this point so - this is safe. */ - AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_SYS; -} -/*-----------------------------------------------------------*/ - - - diff --git a/Source/portable/GCC/ARM7_AT91SAM7S/portISR.c b/Source/portable/GCC/ARM7_AT91SAM7S/portISR.c deleted file mode 100644 index 6a2537c09..000000000 --- a/Source/portable/GCC/ARM7_AT91SAM7S/portISR.c +++ /dev/null @@ -1,231 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/*----------------------------------------------------------- - * Components that can be compiled to either ARM or THUMB mode are - * contained in port.c The ISR routines, which can only be compiled - * to ARM mode, are contained in this file. - *----------------------------------------------------------*/ - -/* - Changes from V3.2.4 - - + The assembler statements are now included in a single asm block rather - than each line having its own asm block. -*/ - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -#include "AT91SAM7X256.h" - -/* Constants required to handle interrupts. */ -#define portTIMER_MATCH_ISR_BIT ( ( unsigned portCHAR ) 0x01 ) -#define portCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 ) - -/* Constants required to handle critical sections. */ -#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 ) -volatile unsigned portLONG ulCriticalNesting = 9999UL; - -/*-----------------------------------------------------------*/ - -/* ISR to handle manual context switches (from a call to taskYIELD()). */ -void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked)); - -/* - * The scheduler can only be started from ARM mode, hence the inclusion of this - * function here. - */ -void vPortISRStartFirstTask( void ); -/*-----------------------------------------------------------*/ - -void vPortISRStartFirstTask( void ) -{ - /* Simply start the scheduler. This is included here as it can only be - called from ARM mode. */ - portRESTORE_CONTEXT(); -} -/*-----------------------------------------------------------*/ - -/* - * Called by portYIELD() or taskYIELD() to manually force a context switch. - * - * When a context switch is performed from the task level the saved task - * context is made to look as if it occurred from within the tick ISR. This - * way the same restore context function can be used when restoring the context - * saved from the ISR or that saved from a call to vPortYieldProcessor. - */ -void vPortYieldProcessor( void ) -{ - /* Within an IRQ ISR the link register has an offset from the true return - address, but an SWI ISR does not. Add the offset manually so the same - ISR return code can be used in both cases. */ - asm volatile ( "ADD LR, LR, #4" ); - - /* Perform the context switch. First save the context of the current task. */ - portSAVE_CONTEXT(); - - /* Find the highest priority task that is ready to run. */ - vTaskSwitchContext(); - - /* Restore the context of the new task. */ - portRESTORE_CONTEXT(); -} -/*-----------------------------------------------------------*/ - -/* - * The ISR used for the scheduler tick depends on whether the cooperative or - * the preemptive scheduler is being used. - */ - -#if configUSE_PREEMPTION == 0 - - /* The cooperative scheduler requires a normal IRQ service routine to - simply increment the system tick. */ - void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ"))); - void vNonPreemptiveTick( void ) - { - unsigned portLONG ulDummy; - - /* Increment the tick count - which may wake some tasks but as the - preemptive scheduler is not being used any woken task is not given - processor time no matter what its priority. */ - vTaskIncrementTick(); - - /* Clear the PIT interrupt. */ - ulDummy = AT91C_BASE_PITC->PITC_PIVR; - - /* End the interrupt in the AIC. */ - AT91C_BASE_AIC->AIC_EOICR = ulDummy; - } - -#else - - /* The preemptive scheduler is defined as "naked" as the full context is - saved on entry as part of the context switch. */ - void vPreemptiveTick( void ) __attribute__((naked)); - void vPreemptiveTick( void ) - { - /* Save the context of the current task. */ - portSAVE_CONTEXT(); - - /* Increment the tick count - this may wake a task. */ - vTaskIncrementTick(); - - /* Find the highest priority task that is ready to run. */ - vTaskSwitchContext(); - - /* End the interrupt in the AIC. */ - AT91C_BASE_AIC->AIC_EOICR = AT91C_BASE_PITC->PITC_PIVR;; - - portRESTORE_CONTEXT(); - } - -#endif -/*-----------------------------------------------------------*/ - -/* - * The interrupt management utilities can only be called from ARM mode. When - * THUMB_INTERWORK is defined the utilities are defined as functions here to - * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then - * the utilities are defined as macros in portmacro.h - as per other ports. - */ -void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); -void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); - -void vPortDisableInterruptsFromThumb( void ) -{ - asm volatile ( - "STMDB SP!, {R0} \n\t" /* Push R0. */ - "MRS R0, CPSR \n\t" /* Get CPSR. */ - "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ - "LDMIA SP!, {R0} \n\t" /* Pop R0. */ - "BX R14" ); /* Return back to thumb. */ -} - -void vPortEnableInterruptsFromThumb( void ) -{ - asm volatile ( - "STMDB SP!, {R0} \n\t" /* Push R0. */ - "MRS R0, CPSR \n\t" /* Get CPSR. */ - "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ - "LDMIA SP!, {R0} \n\t" /* Pop R0. */ - "BX R14" ); /* Return back to thumb. */ -} - - -/* The code generated by the GCC compiler uses the stack in different ways at -different optimisation levels. The interrupt flags can therefore not always -be saved to the stack. Instead the critical section nesting level is stored -in a variable, which is then saved as part of the stack context. */ -void vPortEnterCritical( void ) -{ - /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ - asm volatile ( - "STMDB SP!, {R0} \n\t" /* Push R0. */ - "MRS R0, CPSR \n\t" /* Get CPSR. */ - "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ - "LDMIA SP!, {R0}" ); /* Pop R0. */ - - /* Now interrupts are disabled ulCriticalNesting can be accessed - directly. Increment ulCriticalNesting to keep a count of how many times - portENTER_CRITICAL() has been called. */ - ulCriticalNesting++; -} - -void vPortExitCritical( void ) -{ - if( ulCriticalNesting > portNO_CRITICAL_NESTING ) - { - /* Decrement the nesting count as we are leaving a critical section. */ - ulCriticalNesting--; - - /* If the nesting level has reached zero then interrupts should be - re-enabled. */ - if( ulCriticalNesting == portNO_CRITICAL_NESTING ) - { - /* Enable interrupts as per portEXIT_CRITICAL(). */ - asm volatile ( - "STMDB SP!, {R0} \n\t" /* Push R0. */ - "MRS R0, CPSR \n\t" /* Get CPSR. */ - "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ - "LDMIA SP!, {R0}" ); /* Pop R0. */ - } - } -} - diff --git a/Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h b/Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h deleted file mode 100644 index 9d17e02c6..000000000 --- a/Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h +++ /dev/null @@ -1,264 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - Changes from V3.2.3 - - + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1. - - Changes from V3.2.4 - - + Removed the use of the %0 parameter within the assembler macros and - replaced them with hard coded registers. This will ensure the - assembler does not select the link register as the temp register as - was occasionally happening previously. - - + The assembler statements are now included in a single asm block rather - than each line having its own asm block. -*/ - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -/*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the - * given hardware and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - -/* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE unsigned portLONG -#define portBASE_TYPE portLONG - -#if( configUSE_16_BIT_TICKS == 1 ) - typedef unsigned portSHORT portTickType; - #define portMAX_DELAY ( portTickType ) 0xffff -#else - typedef unsigned portLONG portTickType; - #define portMAX_DELAY ( portTickType ) 0xffffffff -#endif -/*-----------------------------------------------------------*/ - -/* Architecture specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 4 -#define portNOP() asm volatile ( "NOP" ); -/*-----------------------------------------------------------*/ - - -/* Scheduler utilities. */ - -/* - * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR - * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but - * are included here for efficiency. An attempt to call one from - * THUMB mode code will result in a compile time error. - */ - -#define portRESTORE_CONTEXT() \ -{ \ -extern volatile void * volatile pxCurrentTCB; \ -extern volatile unsigned portLONG ulCriticalNesting; \ - \ - /* Set the LR to the task stack. */ \ - asm volatile ( \ - "LDR R0, =pxCurrentTCB \n\t" \ - "LDR R0, [R0] \n\t" \ - "LDR LR, [R0] \n\t" \ - \ - /* The critical nesting depth is the first item on the stack. */ \ - /* Load it into the ulCriticalNesting variable. */ \ - "LDR R0, =ulCriticalNesting \n\t" \ - "LDMFD LR!, {R1} \n\t" \ - "STR R1, [R0] \n\t" \ - \ - /* Get the SPSR from the stack. */ \ - "LDMFD LR!, {R0} \n\t" \ - "MSR SPSR, R0 \n\t" \ - \ - /* Restore all system mode registers for the task. */ \ - "LDMFD LR, {R0-R14}^ \n\t" \ - "NOP \n\t" \ - \ - /* Restore the return address. */ \ - "LDR LR, [LR, #+60] \n\t" \ - \ - /* And return - correcting the offset in the LR to obtain the */ \ - /* correct address. */ \ - "SUBS PC, LR, #4 \n\t" \ - ); \ - ( void ) ulCriticalNesting; \ - ( void ) pxCurrentTCB; \ -} -/*-----------------------------------------------------------*/ - -#define portSAVE_CONTEXT() \ -{ \ -extern volatile void * volatile pxCurrentTCB; \ -extern volatile unsigned portLONG ulCriticalNesting; \ - \ - /* Push R0 as we are going to use the register. */ \ - asm volatile ( \ - "STMDB SP!, {R0} \n\t" \ - \ - /* Set R0 to point to the task stack pointer. */ \ - "STMDB SP,{SP}^ \n\t" \ - "NOP \n\t" \ - "SUB SP, SP, #4 \n\t" \ - "LDMIA SP!,{R0} \n\t" \ - \ - /* Push the return address onto the stack. */ \ - "STMDB R0!, {LR} \n\t" \ - \ - /* Now we have saved LR we can use it instead of R0. */ \ - "MOV LR, R0 \n\t" \ - \ - /* Pop R0 so we can save it onto the system mode stack. */ \ - "LDMIA SP!, {R0} \n\t" \ - \ - /* Push all the system mode registers onto the task stack. */ \ - "STMDB LR,{R0-LR}^ \n\t" \ - "NOP \n\t" \ - "SUB LR, LR, #60 \n\t" \ - \ - /* Push the SPSR onto the task stack. */ \ - "MRS R0, SPSR \n\t" \ - "STMDB LR!, {R0} \n\t" \ - \ - "LDR R0, =ulCriticalNesting \n\t" \ - "LDR R0, [R0] \n\t" \ - "STMDB LR!, {R0} \n\t" \ - \ - /* Store the new top of stack for the task. */ \ - "LDR R0, =pxCurrentTCB \n\t" \ - "LDR R0, [R0] \n\t" \ - "STR LR, [R0] \n\t" \ - ); \ - ( void ) ulCriticalNesting; \ - ( void ) pxCurrentTCB; \ -} - - -/*----------------------------------------------------------- - * ISR entry and exit macros. These are only required if a task switch - * is required from the ISR. - *----------------------------------------------------------*/ - - -#define portENTER_SWITCHING_ISR() \ - /* Save the context of the interrupted task. */ \ - portSAVE_CONTEXT(); \ - \ - /* We don't know the stack requirements for the ISR, so the frame */\ - /* pointer will be set to the top of the task stack, and the stack*/\ - /* pointer left where it is. The IRQ stack will get used for any */\ - /* functions calls made by this ISR. */ \ - asm volatile ( "SUB R11, LR, #4" ); \ - { - -#define portEXIT_SWITCHING_ISR( SwitchRequired ) \ - /* If a switch is required then we just need to call */ \ - /* vTaskSwitchContext() as the context has already been */ \ - /* saved. */ \ - if( SwitchRequired ) \ - { \ - vTaskSwitchContext(); \ - } \ - } \ - /* Restore the context of which ever task is now the highest */ \ - /* priority that is ready to run. */ \ - portRESTORE_CONTEXT(); - -#define portYIELD() asm volatile ( "SWI" ); -/*-----------------------------------------------------------*/ - - -/* Critical section management. */ - -/* - * The interrupt management utilities can only be called from ARM mode. When - * THUMB_INTERWORK is defined the utilities are defined as functions in - * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not - * defined then the utilities are defined as macros here - as per other ports. - */ - -#ifdef THUMB_INTERWORK - - extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); - extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); - - #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb() - #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb() - -#else - - #define portDISABLE_INTERRUPTS() \ - asm volatile ( \ - "STMDB SP!, {R0} \n\t" /* Push R0. */ \ - "MRS R0, CPSR \n\t" /* Get CPSR. */ \ - "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ - "LDMIA SP!, {R0} " ) /* Pop R0. */ - - #define portENABLE_INTERRUPTS() \ - asm volatile ( \ - "STMDB SP!, {R0} \n\t" /* Push R0. */ \ - "MRS R0, CPSR \n\t" /* Get CPSR. */ \ - "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ - "LDMIA SP!, {R0} " ) /* Pop R0. */ - -#endif /* THUMB_INTERWORK */ - -extern void vPortEnterCritical( void ); -extern void vPortExitCritical( void ); - -#define portENTER_CRITICAL() vPortEnterCritical(); -#define portEXIT_CRITICAL() vPortExitCritical(); -/*-----------------------------------------------------------*/ - -/* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) - -#endif /* PORTMACRO_H */ - diff --git a/Source/portable/GCC/ARM7_LPC2000/port.c b/Source/portable/GCC/ARM7_LPC2000/port.c deleted file mode 100644 index ad12bbba3..000000000 --- a/Source/portable/GCC/ARM7_LPC2000/port.c +++ /dev/null @@ -1,245 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the ARM7 port. - * - * Components that can be compiled to either ARM or THUMB mode are - * contained in this file. The ISR routines, which can only be compiled - * to ARM mode are contained in portISR.c. - *----------------------------------------------------------*/ - -/* - Changes from V2.5.2 - - + ulCriticalNesting is now saved as part of the task context, as is - therefore added to the initial task stack during pxPortInitialiseStack. - - Changes from V3.2.2 - - + Bug fix - The prescale value for the timer setup is now written to T0_PR - instead of T0_PC. This bug would have had no effect unless a prescale - value was actually used. -*/ - - -/* Standard includes. */ -#include - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Constants required to setup the task context. */ -#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ -#define portTHUMB_MODE_BIT ( ( portSTACK_TYPE ) 0x20 ) -#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 ) -#define portNO_CRITICAL_SECTION_NESTING ( ( portSTACK_TYPE ) 0 ) - -/* Constants required to setup the tick ISR. */ -#define portENABLE_TIMER ( ( unsigned portCHAR ) 0x01 ) -#define portPRESCALE_VALUE 0x00 -#define portINTERRUPT_ON_MATCH ( ( unsigned portLONG ) 0x01 ) -#define portRESET_COUNT_ON_MATCH ( ( unsigned portLONG ) 0x02 ) - -/* Constants required to setup the VIC for the tick ISR. */ -#define portTIMER_VIC_CHANNEL ( ( unsigned portLONG ) 0x0004 ) -#define portTIMER_VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x0010 ) -#define portTIMER_VIC_ENABLE ( ( unsigned portLONG ) 0x0020 ) - -/*-----------------------------------------------------------*/ - -/* Setup the timer to generate the tick interrupts. */ -static void prvSetupTimerInterrupt( void ); - -/* - * The scheduler can only be started from ARM mode, so - * vPortISRStartFirstSTask() is defined in portISR.c. - */ -extern void vPortISRStartFirstTask( void ); - -/*-----------------------------------------------------------*/ - -/* - * Initialise the stack of a task to look exactly as if a call to - * portSAVE_CONTEXT had been called. - * - * See header file for description. - */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) -{ -portSTACK_TYPE *pxOriginalTOS; - - pxOriginalTOS = pxTopOfStack; - - /* Setup the initial stack of the task. The stack is set exactly as - expected by the portRESTORE_CONTEXT() macro. */ - - /* First on the stack is the return address - which in this case is the - start of the task. The offset is added to make the return address appear - as it would within an IRQ ISR. */ - *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; - pxTopOfStack--; - - *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */ - pxTopOfStack--; - - /* When the task starts is will expect to find the function parameter in - R0. */ - *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ - pxTopOfStack--; - - /* The last thing onto the stack is the status register, which is set for - system mode, with interrupts enabled. */ - *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR; - - #ifdef THUMB_INTERWORK - { - /* We want the task to start in thumb mode. */ - *pxTopOfStack |= portTHUMB_MODE_BIT; - } - #endif - - pxTopOfStack--; - - /* Some optimisation levels use the stack differently to others. This - means the interrupt flags cannot always be stored on the stack and will - instead be stored in a variable, which is then saved as part of the - tasks context. */ - *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING; - - return pxTopOfStack; -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xPortStartScheduler( void ) -{ - /* Start the timer that generates the tick ISR. Interrupts are disabled - here already. */ - prvSetupTimerInterrupt(); - - /* Start the first task. */ - vPortISRStartFirstTask(); - - /* Should not get here! */ - return 0; -} -/*-----------------------------------------------------------*/ - -void vPortEndScheduler( void ) -{ - /* It is unlikely that the ARM port will require this function as there - is nothing to return to. */ -} -/*-----------------------------------------------------------*/ - -/* - * Setup the timer 0 to generate the tick interrupts at the required frequency. - */ -static void prvSetupTimerInterrupt( void ) -{ -unsigned portLONG ulCompareMatch; - - /* A 1ms tick does not require the use of the timer prescale. This is - defaulted to zero but can be used if necessary. */ - T0_PR = portPRESCALE_VALUE; - - /* Calculate the match value required for our wanted tick rate. */ - ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ; - - /* Protect against divide by zero. Using an if() statement still results - in a warning - hence the #if. */ - #if portPRESCALE_VALUE != 0 - { - ulCompareMatch /= ( portPRESCALE_VALUE + 1 ); - } - #endif - T0_MR0 = ulCompareMatch; - - /* Generate tick with timer 0 compare match. */ - T0_MCR = portRESET_COUNT_ON_MATCH | portINTERRUPT_ON_MATCH; - - /* Setup the VIC for the timer. */ - VICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT ); - VICIntEnable |= portTIMER_VIC_CHANNEL_BIT; - - /* The ISR installed depends on whether the preemptive or cooperative - scheduler is being used. */ - #if configUSE_PREEMPTION == 1 - { - extern void ( vPreemptiveTick )( void ); - VICVectAddr0 = ( portLONG ) vPreemptiveTick; - } - #else - { - extern void ( vNonPreemptiveTick )( void ); - VICVectAddr0 = ( portLONG ) vNonPreemptiveTick; - } - #endif - - VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE; - - /* Start the timer - interrupts are disabled when this function is called - so it is okay to do this here. */ - T0_TCR = portENABLE_TIMER; -} -/*-----------------------------------------------------------*/ - - - diff --git a/Source/portable/GCC/ARM7_LPC2000/portISR.c b/Source/portable/GCC/ARM7_LPC2000/portISR.c deleted file mode 100644 index 7551d2ca8..000000000 --- a/Source/portable/GCC/ARM7_LPC2000/portISR.c +++ /dev/null @@ -1,235 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/*----------------------------------------------------------- - * Components that can be compiled to either ARM or THUMB mode are - * contained in port.c The ISR routines, which can only be compiled - * to ARM mode, are contained in this file. - *----------------------------------------------------------*/ - -/* - Changes from V2.5.2 - - + The critical section management functions have been changed. These no - longer modify the stack and are safe to use at all optimisation levels. - The functions are now also the same for both ARM and THUMB modes. - - Changes from V2.6.0 - - + Removed the 'static' from the definition of vNonPreemptiveTick() to - allow the demo to link when using the cooperative scheduler. - - Changes from V3.2.4 - - + The assembler statements are now included in a single asm block rather - than each line having its own asm block. -*/ - - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Constants required to handle interrupts. */ -#define portTIMER_MATCH_ISR_BIT ( ( unsigned portCHAR ) 0x01 ) -#define portCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 ) - -/* Constants required to handle critical sections. */ -#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 ) -volatile unsigned portLONG ulCriticalNesting = 9999UL; - -/*-----------------------------------------------------------*/ - -/* ISR to handle manual context switches (from a call to taskYIELD()). */ -void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked)); - -/* - * The scheduler can only be started from ARM mode, hence the inclusion of this - * function here. - */ -void vPortISRStartFirstTask( void ); -/*-----------------------------------------------------------*/ - -void vPortISRStartFirstTask( void ) -{ - /* Simply start the scheduler. This is included here as it can only be - called from ARM mode. */ - portRESTORE_CONTEXT(); -} -/*-----------------------------------------------------------*/ - -/* - * Called by portYIELD() or taskYIELD() to manually force a context switch. - * - * When a context switch is performed from the task level the saved task - * context is made to look as if it occurred from within the tick ISR. This - * way the same restore context function can be used when restoring the context - * saved from the ISR or that saved from a call to vPortYieldProcessor. - */ -void vPortYieldProcessor( void ) -{ - /* Within an IRQ ISR the link register has an offset from the true return - address, but an SWI ISR does not. Add the offset manually so the same - ISR return code can be used in both cases. */ - asm volatile ( "ADD LR, LR, #4" ); - - /* Perform the context switch. First save the context of the current task. */ - portSAVE_CONTEXT(); - - /* Find the highest priority task that is ready to run. */ - vTaskSwitchContext(); - - /* Restore the context of the new task. */ - portRESTORE_CONTEXT(); -} -/*-----------------------------------------------------------*/ - -/* - * The ISR used for the scheduler tick depends on whether the cooperative or - * the preemptive scheduler is being used. - */ - -#if configUSE_PREEMPTION == 0 - - /* The cooperative scheduler requires a normal IRQ service routine to - simply increment the system tick. */ - void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ"))); - void vNonPreemptiveTick( void ) - { - vTaskIncrementTick(); - T0_IR = portTIMER_MATCH_ISR_BIT; - VICVectAddr = portCLEAR_VIC_INTERRUPT; - } - -#else - - /* The preemptive scheduler is defined as "naked" as the full context is - saved on entry as part of the context switch. */ - void vPreemptiveTick( void ) __attribute__((naked)); - void vPreemptiveTick( void ) - { - /* Save the context of the interrupted task. */ - portSAVE_CONTEXT(); - - /* Increment the RTOS tick count, then look for the highest priority - task that is ready to run. */ - vTaskIncrementTick(); - vTaskSwitchContext(); - - /* Ready for the next interrupt. */ - T0_IR = portTIMER_MATCH_ISR_BIT; - VICVectAddr = portCLEAR_VIC_INTERRUPT; - - /* Restore the context of the new task. */ - portRESTORE_CONTEXT(); - } - -#endif -/*-----------------------------------------------------------*/ - -/* - * The interrupt management utilities can only be called from ARM mode. When - * THUMB_INTERWORK is defined the utilities are defined as functions here to - * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then - * the utilities are defined as macros in portmacro.h - as per other ports. - */ -#ifdef THUMB_INTERWORK - - void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); - void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); - - void vPortDisableInterruptsFromThumb( void ) - { - asm volatile ( - "STMDB SP!, {R0} \n\t" /* Push R0. */ - "MRS R0, CPSR \n\t" /* Get CPSR. */ - "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ - "LDMIA SP!, {R0} \n\t" /* Pop R0. */ - "BX R14" ); /* Return back to thumb. */ - } - - void vPortEnableInterruptsFromThumb( void ) - { - asm volatile ( - "STMDB SP!, {R0} \n\t" /* Push R0. */ - "MRS R0, CPSR \n\t" /* Get CPSR. */ - "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ - "LDMIA SP!, {R0} \n\t" /* Pop R0. */ - "BX R14" ); /* Return back to thumb. */ - } - -#endif /* THUMB_INTERWORK */ - -/* The code generated by the GCC compiler uses the stack in different ways at -different optimisation levels. The interrupt flags can therefore not always -be saved to the stack. Instead the critical section nesting level is stored -in a variable, which is then saved as part of the stack context. */ -void vPortEnterCritical( void ) -{ - /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ - asm volatile ( - "STMDB SP!, {R0} \n\t" /* Push R0. */ - "MRS R0, CPSR \n\t" /* Get CPSR. */ - "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ - "LDMIA SP!, {R0}" ); /* Pop R0. */ - - /* Now interrupts are disabled ulCriticalNesting can be accessed - directly. Increment ulCriticalNesting to keep a count of how many times - portENTER_CRITICAL() has been called. */ - ulCriticalNesting++; -} - -void vPortExitCritical( void ) -{ - if( ulCriticalNesting > portNO_CRITICAL_NESTING ) - { - /* Decrement the nesting count as we are leaving a critical section. */ - ulCriticalNesting--; - - /* If the nesting level has reached zero then interrupts should be - re-enabled. */ - if( ulCriticalNesting == portNO_CRITICAL_NESTING ) - { - /* Enable interrupts as per portEXIT_CRITICAL(). */ - asm volatile ( - "STMDB SP!, {R0} \n\t" /* Push R0. */ - "MRS R0, CPSR \n\t" /* Get CPSR. */ - "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ - "LDMIA SP!, {R0}" ); /* Pop R0. */ - } - } -} diff --git a/Source/portable/GCC/ARM7_LPC2000/portmacro.h b/Source/portable/GCC/ARM7_LPC2000/portmacro.h deleted file mode 100644 index 9d17e02c6..000000000 --- a/Source/portable/GCC/ARM7_LPC2000/portmacro.h +++ /dev/null @@ -1,264 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - Changes from V3.2.3 - - + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1. - - Changes from V3.2.4 - - + Removed the use of the %0 parameter within the assembler macros and - replaced them with hard coded registers. This will ensure the - assembler does not select the link register as the temp register as - was occasionally happening previously. - - + The assembler statements are now included in a single asm block rather - than each line having its own asm block. -*/ - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -/*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the - * given hardware and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - -/* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE unsigned portLONG -#define portBASE_TYPE portLONG - -#if( configUSE_16_BIT_TICKS == 1 ) - typedef unsigned portSHORT portTickType; - #define portMAX_DELAY ( portTickType ) 0xffff -#else - typedef unsigned portLONG portTickType; - #define portMAX_DELAY ( portTickType ) 0xffffffff -#endif -/*-----------------------------------------------------------*/ - -/* Architecture specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 4 -#define portNOP() asm volatile ( "NOP" ); -/*-----------------------------------------------------------*/ - - -/* Scheduler utilities. */ - -/* - * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR - * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but - * are included here for efficiency. An attempt to call one from - * THUMB mode code will result in a compile time error. - */ - -#define portRESTORE_CONTEXT() \ -{ \ -extern volatile void * volatile pxCurrentTCB; \ -extern volatile unsigned portLONG ulCriticalNesting; \ - \ - /* Set the LR to the task stack. */ \ - asm volatile ( \ - "LDR R0, =pxCurrentTCB \n\t" \ - "LDR R0, [R0] \n\t" \ - "LDR LR, [R0] \n\t" \ - \ - /* The critical nesting depth is the first item on the stack. */ \ - /* Load it into the ulCriticalNesting variable. */ \ - "LDR R0, =ulCriticalNesting \n\t" \ - "LDMFD LR!, {R1} \n\t" \ - "STR R1, [R0] \n\t" \ - \ - /* Get the SPSR from the stack. */ \ - "LDMFD LR!, {R0} \n\t" \ - "MSR SPSR, R0 \n\t" \ - \ - /* Restore all system mode registers for the task. */ \ - "LDMFD LR, {R0-R14}^ \n\t" \ - "NOP \n\t" \ - \ - /* Restore the return address. */ \ - "LDR LR, [LR, #+60] \n\t" \ - \ - /* And return - correcting the offset in the LR to obtain the */ \ - /* correct address. */ \ - "SUBS PC, LR, #4 \n\t" \ - ); \ - ( void ) ulCriticalNesting; \ - ( void ) pxCurrentTCB; \ -} -/*-----------------------------------------------------------*/ - -#define portSAVE_CONTEXT() \ -{ \ -extern volatile void * volatile pxCurrentTCB; \ -extern volatile unsigned portLONG ulCriticalNesting; \ - \ - /* Push R0 as we are going to use the register. */ \ - asm volatile ( \ - "STMDB SP!, {R0} \n\t" \ - \ - /* Set R0 to point to the task stack pointer. */ \ - "STMDB SP,{SP}^ \n\t" \ - "NOP \n\t" \ - "SUB SP, SP, #4 \n\t" \ - "LDMIA SP!,{R0} \n\t" \ - \ - /* Push the return address onto the stack. */ \ - "STMDB R0!, {LR} \n\t" \ - \ - /* Now we have saved LR we can use it instead of R0. */ \ - "MOV LR, R0 \n\t" \ - \ - /* Pop R0 so we can save it onto the system mode stack. */ \ - "LDMIA SP!, {R0} \n\t" \ - \ - /* Push all the system mode registers onto the task stack. */ \ - "STMDB LR,{R0-LR}^ \n\t" \ - "NOP \n\t" \ - "SUB LR, LR, #60 \n\t" \ - \ - /* Push the SPSR onto the task stack. */ \ - "MRS R0, SPSR \n\t" \ - "STMDB LR!, {R0} \n\t" \ - \ - "LDR R0, =ulCriticalNesting \n\t" \ - "LDR R0, [R0] \n\t" \ - "STMDB LR!, {R0} \n\t" \ - \ - /* Store the new top of stack for the task. */ \ - "LDR R0, =pxCurrentTCB \n\t" \ - "LDR R0, [R0] \n\t" \ - "STR LR, [R0] \n\t" \ - ); \ - ( void ) ulCriticalNesting; \ - ( void ) pxCurrentTCB; \ -} - - -/*----------------------------------------------------------- - * ISR entry and exit macros. These are only required if a task switch - * is required from the ISR. - *----------------------------------------------------------*/ - - -#define portENTER_SWITCHING_ISR() \ - /* Save the context of the interrupted task. */ \ - portSAVE_CONTEXT(); \ - \ - /* We don't know the stack requirements for the ISR, so the frame */\ - /* pointer will be set to the top of the task stack, and the stack*/\ - /* pointer left where it is. The IRQ stack will get used for any */\ - /* functions calls made by this ISR. */ \ - asm volatile ( "SUB R11, LR, #4" ); \ - { - -#define portEXIT_SWITCHING_ISR( SwitchRequired ) \ - /* If a switch is required then we just need to call */ \ - /* vTaskSwitchContext() as the context has already been */ \ - /* saved. */ \ - if( SwitchRequired ) \ - { \ - vTaskSwitchContext(); \ - } \ - } \ - /* Restore the context of which ever task is now the highest */ \ - /* priority that is ready to run. */ \ - portRESTORE_CONTEXT(); - -#define portYIELD() asm volatile ( "SWI" ); -/*-----------------------------------------------------------*/ - - -/* Critical section management. */ - -/* - * The interrupt management utilities can only be called from ARM mode. When - * THUMB_INTERWORK is defined the utilities are defined as functions in - * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not - * defined then the utilities are defined as macros here - as per other ports. - */ - -#ifdef THUMB_INTERWORK - - extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); - extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); - - #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb() - #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb() - -#else - - #define portDISABLE_INTERRUPTS() \ - asm volatile ( \ - "STMDB SP!, {R0} \n\t" /* Push R0. */ \ - "MRS R0, CPSR \n\t" /* Get CPSR. */ \ - "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ - "LDMIA SP!, {R0} " ) /* Pop R0. */ - - #define portENABLE_INTERRUPTS() \ - asm volatile ( \ - "STMDB SP!, {R0} \n\t" /* Push R0. */ \ - "MRS R0, CPSR \n\t" /* Get CPSR. */ \ - "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ - "LDMIA SP!, {R0} " ) /* Pop R0. */ - -#endif /* THUMB_INTERWORK */ - -extern void vPortEnterCritical( void ); -extern void vPortExitCritical( void ); - -#define portENTER_CRITICAL() vPortEnterCritical(); -#define portEXIT_CRITICAL() vPortExitCritical(); -/*-----------------------------------------------------------*/ - -/* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) - -#endif /* PORTMACRO_H */ - diff --git a/Source/portable/GCC/ARM_CM3/port.c b/Source/portable/GCC/ARM_CM3/port.c deleted file mode 100644 index ad8d148eb..000000000 --- a/Source/portable/GCC/ARM_CM3/port.c +++ /dev/null @@ -1,299 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - Changes between V4.0.0 and V4.0.1 - - + Reduced the code used to setup the initial stack frame. - + The kernel no longer has to install or handle the fault interrupt. -*/ - - -/*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the ARM CM3 port. - *----------------------------------------------------------*/ - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Constants required to manipulate the NVIC. */ -#define portNVIC_SYSTICK_CTRL ( ( volatile unsigned portLONG *) 0xe000e010 ) -#define portNVIC_SYSTICK_LOAD ( ( volatile unsigned portLONG *) 0xe000e014 ) -#define portNVIC_INT_CTRL ( ( volatile unsigned portLONG *) 0xe000ed04 ) -#define portNVIC_SYSPRI2 ( ( volatile unsigned portLONG *) 0xe000ed20 ) -#define portNVIC_SYSPRI1 ( ( volatile unsigned portLONG *) 0xe000ed1c ) -#define portNVIC_SYSTICK_CLK 0x00000004 -#define portNVIC_SYSTICK_INT 0x00000002 -#define portNVIC_SYSTICK_ENABLE 0x00000001 -#define portNVIC_PENDSVSET 0x10000000 -#define portNVIC_PENDSV_PRI 0x00ff0000 -#define portNVIC_SVCALL_PRI 0xff000000 -#define portNVIC_SYSTICK_PRI 0xff000000 - -/* Constants required to set up the initial stack. */ -#define portINITIAL_XPSR ( 0x01000000 ) - -/* Each task maintains its own interrupt status in the critical nesting -variable. */ -unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa; - -/* - * Setup the timer to generate the tick interrupts. - */ -static void prvSetupTimerInterrupt( void ); - -/* - * Exception handlers. - */ -void xPortPendSVHandler( void ) __attribute__ (( naked )); -void xPortSysTickHandler( void ) __attribute__ (( naked )); - -/* - * Set the MSP/PSP to a known value. - */ -void prvSetMSP( unsigned long ulValue ) __attribute__ (( naked )); -void prvSetPSP( unsigned long ulValue ) __attribute__ (( naked )); - -/*-----------------------------------------------------------*/ - -/* - * See header file for description. - */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) -{ - /* Simulate the stack frame as it would be created by a context switch - interrupt. */ - *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* PC */ - pxTopOfStack--; - *pxTopOfStack = 0xfffffffd; /* LR */ - pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ - *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ - pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ - *pxTopOfStack = 0x00000000; /* uxCriticalNesting. */ - - return pxTopOfStack; -} -/*-----------------------------------------------------------*/ - -void prvSetPSP( unsigned long ulValue ) -{ - asm volatile( "msr psp, r0" ); - asm volatile( "bx lr" ); -} -/*-----------------------------------------------------------*/ - -void prvSetMSP( unsigned long ulValue ) -{ - asm volatile( "msr msp, r0" ); - asm volatile( "bx lr" ); -} -/*-----------------------------------------------------------*/ - -/* - * See header file for description. - */ -portBASE_TYPE xPortStartScheduler( void ) -{ - /* Make PendSV, CallSV and SysTick the lowest priority interrupts. */ - *(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI; - *(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI; - - /* Start the timer that generates the tick ISR. Interrupts are disabled - here already. */ - prvSetupTimerInterrupt(); - - /* Start the first task. */ - prvSetPSP( 0 ); - prvSetMSP( *((unsigned portLONG *) 0 ) ); - *(portNVIC_INT_CTRL) |= portNVIC_PENDSVSET; - - /* Enable interrupts */ - portENABLE_INTERRUPTS(); - - /* Should not get here! */ - return 0; -} -/*-----------------------------------------------------------*/ - -void vPortEndScheduler( void ) -{ - /* It is unlikely that the CM3 port will require this function as there - is nothing to return to. */ -} -/*-----------------------------------------------------------*/ - -void vPortYieldFromISR( void ) -{ - /* Set a PendSV to request a context switch. */ - *(portNVIC_INT_CTRL) |= portNVIC_PENDSVSET; - - /* This function is also called in response to a Yield(), so we want - the yield to occur immediately. */ - portENABLE_INTERRUPTS(); -} -/*-----------------------------------------------------------*/ - -void vPortEnterCritical( void ) -{ - portDISABLE_INTERRUPTS(); - uxCriticalNesting++; -} -/*-----------------------------------------------------------*/ - -void vPortExitCritical( void ) -{ - uxCriticalNesting--; - if( uxCriticalNesting == 0 ) - { - portENABLE_INTERRUPTS(); - } -} -/*-----------------------------------------------------------*/ - -void xPortPendSVHandler( void ) -{ - /* Start first task if the stack has not yet been setup. */ - __asm volatile - ( - " mrs r0, psp \n" - " cbz r0, no_save \n" - " \n" /* Save the context into the TCB. */ - " sub r0, #0x20 \n" - " stm r0, {r4-r11} \n" - " nop \n" - " sub r0, #0x04 \n" - " ldr r1, uxCriticalNestingConst \n" - " ldr r1, [r1] \n" - " stm r0, {r1} \n" - " ldr r1, pxCurrentTCBConst \n" - " ldr r1, [r1] \n" - " str r0, [r1] \n" - " \n" - "no_save:\n" - " ldr r0, vTaskSwitchContextConst \n" /* Find the task to execute. */ - " push {r14} \n" - " cpsid i \n" - " blx r0 \n" - " cpsie i \n" - " pop {r14} \n" - " \n" /* Restore the context. */ - " ldr r1, pxCurrentTCBConst \n" - " ldr r1, [r1] \n" - " ldr r0, [r1] \n" - " ldm r0, {r1, r4-r11} \n" - " nop \n" - " ldr r2, uxCriticalNestingConst \n" - " str r1, [r2] \n" - " add r0, #0x24 \n" - " msr psp, r0 \n" - " orr r14, #0xd \n" - " \n" /* Exit with interrupts in the state required by the task. */ - " cbnz r1, sv_disable_interrupts \n" - " bx r14 \n" - " \n" - "sv_disable_interrupts: \n" - " cpsid i \n" - " bx r14 \n" - " \n" - " .align 2 \n" - "vTaskSwitchContextConst: .word vTaskSwitchContext \n" - "pxCurrentTCBConst: .word pxCurrentTCB \n" - "uxCriticalNestingConst: .word uxCriticalNesting \n" - ); -} -/*-----------------------------------------------------------*/ - -void xPortSysTickHandler( void ) -{ - extern void vTaskIncrementTick( void ); - extern void vPortYieldFromISR( void ); - - /* Call the scheduler tick function. */ - __asm volatile - ( - " ldr r0, vTaskIncrementTickConst \n" - " push {r14} \n" - " cpsid i \n" - " blx r0 \n" - " cpsie i \n" - " pop {r14}" - ); - - /* If using preemption, also force a context switch. */ - #if configUSE_PREEMPTION == 1 - __asm volatile - ( - " push {r14} \n" - " ldr r0, vPortYieldFromISRConst2 \n" - " blx r0 \n" - " pop {r14}" - ); - #endif - - /* Exit with interrupts in the correct state. */ - __asm volatile - ( - " ldr r2, uxCriticalNestingConst2 \n" - " ldr r2, [r2] \n" - " cbnz r2, tick_disable_interrupts \n" - " bx r14" - ); - - __asm volatile - ( - "tick_disable_interrupts: \n" - " cpsid i \n" - " bx r14 \n" - " \n" - " .align 2 \n" - "vPortYieldFromISRConst2: .word vPortYieldFromISR\n" - "vTaskIncrementTickConst: .word vTaskIncrementTick\n" - "uxCriticalNestingConst2: .word uxCriticalNesting" - ); -} -/*-----------------------------------------------------------*/ - -/* - * Setup the systick timer to generate the tick interrupts at the required - * frequency. - */ -void prvSetupTimerInterrupt( void ) -{ - /* Configure SysTick to interrupt at the requested rate. */ - *(portNVIC_SYSTICK_LOAD) = configCPU_CLOCK_HZ / configTICK_RATE_HZ; - *(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE; -} - - diff --git a/Source/portable/GCC/ARM_CM3/portmacro.h b/Source/portable/GCC/ARM_CM3/portmacro.h deleted file mode 100644 index e90f604ee..000000000 --- a/Source/portable/GCC/ARM_CM3/portmacro.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -/*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the - * given hardware and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - -/* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE unsigned portLONG -#define portBASE_TYPE long - -#if( configUSE_16_BIT_TICKS == 1 ) - typedef unsigned portSHORT portTickType; - #define portMAX_DELAY ( portTickType ) 0xffff -#else - typedef unsigned portLONG portTickType; - #define portMAX_DELAY ( portTickType ) 0xffffffff -#endif -/*-----------------------------------------------------------*/ - -/* Architecture specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 4 -/*-----------------------------------------------------------*/ - - -/* Scheduler utilities. */ -extern void vPortYieldFromISR( void ); - -#define portYIELD() vPortYieldFromISR() - -#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vPortYieldFromISR() -/*-----------------------------------------------------------*/ - - -/* Critical section management. */ - -extern void vPortEnableInterrupts( void ); -extern void vPortEnterCritical( void ); -extern void vPortExitCritical( void ); - -#define portDISABLE_INTERRUPTS() __asm volatile( "cpsid i" ) -#define portENABLE_INTERRUPTS() __asm volatile( "cpsie i" ) -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() -/*-----------------------------------------------------------*/ - -/* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) - -#define inline -#define portNOP() - -#endif /* PORTMACRO_H */ - diff --git a/Source/portable/GCC/ATMega323/port.c b/Source/portable/GCC/ATMega323/port.c deleted file mode 100644 index 7d0caab22..000000000 --- a/Source/portable/GCC/ATMega323/port.c +++ /dev/null @@ -1,432 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - -Changes from V2.6.0 - - + AVR port - Replaced the inb() and outb() functions with direct memory - access. This allows the port to be built with the 20050414 build of - WinAVR. -*/ - -#include -#include - -#include "FreeRTOS.h" -#include "task.h" - -/*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the AVR port. - *----------------------------------------------------------*/ - -/* Start tasks with interrupts enables. */ -#define portFLAGS_INT_ENABLED ( ( portSTACK_TYPE ) 0x80 ) - -/* Hardware constants for timer 1. */ -#define portCLEAR_COUNTER_ON_MATCH ( ( unsigned portCHAR ) 0x08 ) -#define portPRESCALE_64 ( ( unsigned portCHAR ) 0x03 ) -#define portCLOCK_PRESCALER ( ( unsigned portLONG ) 64 ) -#define portCOMPARE_MATCH_A_INTERRUPT_ENABLE ( ( unsigned portCHAR ) 0x10 ) - -/*-----------------------------------------------------------*/ - -/* We require the address of the pxCurrentTCB variable, but don't want to know -any details of its type. */ -typedef void tskTCB; -extern volatile tskTCB * volatile pxCurrentTCB; - -/*-----------------------------------------------------------*/ - -/* - * Macro to save all the general purpose registers, the save the stack pointer - * into the TCB. - * - * The first thing we do is save the flags then disable interrupts. This is to - * guard our stack against having a context switch interrupt after we have already - * pushed the registers onto the stack - causing the 32 registers to be on the - * stack twice. - * - * r1 is set to zero as the compiler expects it to be thus, however some - * of the math routines make use of R1. - * - * The interrupts will have been disabled during the call to portSAVE_CONTEXT() - * so we need not worry about reading/writing to the stack pointer. - */ - -#define portSAVE_CONTEXT() \ - asm volatile ( "push r0 \n\t" \ - "in r0, __SREG__ \n\t" \ - "cli \n\t" \ - "push r0 \n\t" \ - "push r1 \n\t" \ - "clr r1 \n\t" \ - "push r2 \n\t" \ - "push r3 \n\t" \ - "push r4 \n\t" \ - "push r5 \n\t" \ - "push r6 \n\t" \ - "push r7 \n\t" \ - "push r8 \n\t" \ - "push r9 \n\t" \ - "push r10 \n\t" \ - "push r11 \n\t" \ - "push r12 \n\t" \ - "push r13 \n\t" \ - "push r14 \n\t" \ - "push r15 \n\t" \ - "push r16 \n\t" \ - "push r17 \n\t" \ - "push r18 \n\t" \ - "push r19 \n\t" \ - "push r20 \n\t" \ - "push r21 \n\t" \ - "push r22 \n\t" \ - "push r23 \n\t" \ - "push r24 \n\t" \ - "push r25 \n\t" \ - "push r26 \n\t" \ - "push r27 \n\t" \ - "push r28 \n\t" \ - "push r29 \n\t" \ - "push r30 \n\t" \ - "push r31 \n\t" \ - "lds r26, pxCurrentTCB \n\t" \ - "lds r27, pxCurrentTCB + 1 \n\t" \ - "in r0, 0x3d \n\t" \ - "st x+, r0 \n\t" \ - "in r0, 0x3e \n\t" \ - "st x+, r0 \n\t" \ - ); - -/* - * Opposite to portSAVE_CONTEXT(). Interrupts will have been disabled during - * the context save so we can write to the stack pointer. - */ - -#define portRESTORE_CONTEXT() \ - asm volatile ( "lds r26, pxCurrentTCB \n\t" \ - "lds r27, pxCurrentTCB + 1 \n\t" \ - "ld r28, x+ \n\t" \ - "out __SP_L__, r28 \n\t" \ - "ld r29, x+ \n\t" \ - "out __SP_H__, r29 \n\t" \ - "pop r31 \n\t" \ - "pop r30 \n\t" \ - "pop r29 \n\t" \ - "pop r28 \n\t" \ - "pop r27 \n\t" \ - "pop r26 \n\t" \ - "pop r25 \n\t" \ - "pop r24 \n\t" \ - "pop r23 \n\t" \ - "pop r22 \n\t" \ - "pop r21 \n\t" \ - "pop r20 \n\t" \ - "pop r19 \n\t" \ - "pop r18 \n\t" \ - "pop r17 \n\t" \ - "pop r16 \n\t" \ - "pop r15 \n\t" \ - "pop r14 \n\t" \ - "pop r13 \n\t" \ - "pop r12 \n\t" \ - "pop r11 \n\t" \ - "pop r10 \n\t" \ - "pop r9 \n\t" \ - "pop r8 \n\t" \ - "pop r7 \n\t" \ - "pop r6 \n\t" \ - "pop r5 \n\t" \ - "pop r4 \n\t" \ - "pop r3 \n\t" \ - "pop r2 \n\t" \ - "pop r1 \n\t" \ - "pop r0 \n\t" \ - "out __SREG__, r0 \n\t" \ - "pop r0 \n\t" \ - ); - -/*-----------------------------------------------------------*/ - -/* - * Perform hardware setup to enable ticks from timer 1, compare match A. - */ -static void prvSetupTimerInterrupt( void ); -/*-----------------------------------------------------------*/ - -/* - * See header file for description. - */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) -{ -unsigned portSHORT usAddress; - - /* Place a few bytes of known values on the bottom of the stack. - This is just useful for debugging. */ - - *pxTopOfStack = 0x11; - pxTopOfStack--; - *pxTopOfStack = 0x22; - pxTopOfStack--; - *pxTopOfStack = 0x33; - pxTopOfStack--; - - /* Simulate how the stack would look after a call to vPortYield() generated by - the compiler. */ - - /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */ - - /* The start of the task code will be popped off the stack last, so place - it on first. */ - usAddress = ( unsigned portSHORT ) pxCode; - *pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned portSHORT ) 0x00ff ); - pxTopOfStack--; - - usAddress >>= 8; - *pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned portSHORT ) 0x00ff ); - pxTopOfStack--; - - /* Next simulate the stack as if after a call to portSAVE_CONTEXT(). - portSAVE_CONTEXT places the flags on the stack immediately after r0 - to ensure the interrupts get disabled as soon as possible, and so ensuring - the stack use is minimal should a context switch interrupt occur. */ - *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* R0 */ - pxTopOfStack--; - *pxTopOfStack = portFLAGS_INT_ENABLED; - pxTopOfStack--; - - - /* Now the remaining registers. The compiler expects R1 to be 0. */ - *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* R1 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x02; /* R2 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x03; /* R3 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x04; /* R4 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x05; /* R5 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x06; /* R6 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x07; /* R7 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x08; /* R8 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x09; /* R9 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x10; /* R10 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x11; /* R11 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x12; /* R12 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x13; /* R13 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x14; /* R14 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x15; /* R15 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x16; /* R16 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x17; /* R17 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x18; /* R18 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x19; /* R19 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x20; /* R20 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x21; /* R21 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x22; /* R22 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x23; /* R23 */ - pxTopOfStack--; - - /* Place the parameter on the stack in the expected location. */ - usAddress = ( unsigned portSHORT ) pvParameters; - *pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned portSHORT ) 0x00ff ); - pxTopOfStack--; - - usAddress >>= 8; - *pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned portSHORT ) 0x00ff ); - pxTopOfStack--; - - *pxTopOfStack = ( portSTACK_TYPE ) 0x26; /* R26 X */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x27; /* R27 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x28; /* R28 Y */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x29; /* R29 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x30; /* R30 Z */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x031; /* R31 */ - pxTopOfStack--; - - /*lint +e950 +e611 +e923 */ - - return pxTopOfStack; -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xPortStartScheduler( void ) -{ - /* In this port we ignore the parameter and use the configUSE_PREEMPTION - definition instead. */ - - /* Setup the hardware to generate the tick. */ - prvSetupTimerInterrupt(); - - /* Restore the context of the first task that is going to run. */ - portRESTORE_CONTEXT(); - - /* Simulate a function call end as generated by the compiler. We will now - jump to the start of the task the context of which we have just restored. */ - asm volatile ( "ret" ); - - /* Should not get here. */ - return pdTRUE; -} -/*-----------------------------------------------------------*/ - -void vPortEndScheduler( void ) -{ - /* It is unlikely that the AVR port will get stopped. If required simply - disable the tick interrupt here. */ -} -/*-----------------------------------------------------------*/ - -/* - * Manual context switch. The first thing we do is save the registers so we - * can use a naked attribute. - */ -void vPortYield( void ) __attribute__ ( ( naked ) ); -void vPortYield( void ) -{ - portSAVE_CONTEXT(); - vTaskSwitchContext(); - portRESTORE_CONTEXT(); - - asm volatile ( "ret" ); -} -/*-----------------------------------------------------------*/ - -/* - * Context switch function used by the tick. This must be identical to - * vPortYield() from the call to vTaskSwitchContext() onwards. The only - * difference from vPortYield() is the tick count is incremented as the - * call comes from the tick ISR. - */ -void vPortYieldFromTick( void ) __attribute__ ( ( naked ) ); -void vPortYieldFromTick( void ) -{ - portSAVE_CONTEXT(); - vTaskIncrementTick(); - vTaskSwitchContext(); - portRESTORE_CONTEXT(); - - asm volatile ( "ret" ); -} -/*-----------------------------------------------------------*/ - -/* - * Setup timer 1 compare match A to generate a tick interrupt. - */ -static void prvSetupTimerInterrupt( void ) -{ -unsigned portLONG ulCompareMatch; -unsigned portCHAR ucHighByte, ucLowByte; - - /* Using 16bit timer 1 to generate the tick. Correct fuses must be - selected for the configCPU_CLOCK_HZ clock. */ - - ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ; - - /* We only have 16 bits so have to scale to get our required tick rate. */ - ulCompareMatch /= portCLOCK_PRESCALER; - - /* Adjust for correct value. */ - ulCompareMatch -= ( unsigned portLONG ) 1; - - /* Setup compare match value for compare match A. Interrupts are disabled - before this is called so we need not worry here. */ - ucLowByte = ( unsigned portCHAR ) ( ulCompareMatch & ( unsigned portLONG ) 0xff ); - ulCompareMatch >>= 8; - ucHighByte = ( unsigned portCHAR ) ( ulCompareMatch & ( unsigned portLONG ) 0xff ); - OCR1AH = ucHighByte; - OCR1AL = ucLowByte; - - /* Setup clock source and compare match behaviour. */ - ucLowByte = portCLEAR_COUNTER_ON_MATCH | portPRESCALE_64; - TCCR1B = ucLowByte; - - /* Enable the interrupt - this is okay as interrupt are currently globally - disabled. */ - ucLowByte = TIMSK; - ucLowByte |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE; - TIMSK = ucLowByte; -} -/*-----------------------------------------------------------*/ - -#if configUSE_PREEMPTION == 1 - - /* - * Tick ISR for preemptive scheduler. We can use a naked attribute as - * the context is saved at the start of vPortYieldFromTick(). The tick - * count is incremented after the context is saved. - */ - void SIG_OUTPUT_COMPARE1A( void ) __attribute__ ( ( signal, naked ) ); - void SIG_OUTPUT_COMPARE1A( void ) - { - vPortYieldFromTick(); - asm volatile ( "reti" ); - } -#else - - /* - * Tick ISR for the cooperative scheduler. All this does is increment the - * tick count. We don't need to switch context, this can only be done by - * manual calls to taskYIELD(); - */ - void SIG_OUTPUT_COMPARE1A( void ) __attribute__ ( ( signal ) ); - void SIG_OUTPUT_COMPARE1A( void ) - { - vTaskIncrementTick(); - } -#endif - - - diff --git a/Source/portable/GCC/ATMega323/portmacro.h b/Source/portable/GCC/ATMega323/portmacro.h deleted file mode 100644 index 9d0355320..000000000 --- a/Source/portable/GCC/ATMega323/portmacro.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V1.2.3 - - + portCPU_CLOSK_HZ definition changed to 8MHz base 10, previously it - base 16. -*/ - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -/*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the - * given hardware and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - -/* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT int -#define portSTACK_TYPE unsigned portCHAR -#define portBASE_TYPE char - -#if( configUSE_16_BIT_TICKS == 1 ) - typedef unsigned portSHORT portTickType; - #define portMAX_DELAY ( portTickType ) 0xffff -#else - typedef unsigned portLONG portTickType; - #define portMAX_DELAY ( portTickType ) 0xffffffff -#endif -/*-----------------------------------------------------------*/ - -/* Critical section management. */ -#define portENTER_CRITICAL() asm volatile ( "in __tmp_reg__, __SREG__" :: ); \ - asm volatile ( "cli" :: ); \ - asm volatile ( "push __tmp_reg__" :: ) - -#define portEXIT_CRITICAL() asm volatile ( "pop __tmp_reg__" :: ); \ - asm volatile ( "out __SREG__, __tmp_reg__" :: ) - -#define portDISABLE_INTERRUPTS() asm volatile ( "cli" :: ); -#define portENABLE_INTERRUPTS() asm volatile ( "sei" :: ); -/*-----------------------------------------------------------*/ - -/* Architecture specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 1 -#define portNOP() asm volatile ( "nop" ); -/*-----------------------------------------------------------*/ - -/* Kernel utilities. */ -extern void vPortYield( void ) __attribute__ ( ( naked ) ); -#define portYIELD() vPortYield() -/*-----------------------------------------------------------*/ - -/* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) - -#endif /* PORTMACRO_H */ - diff --git a/Source/portable/GCC/H8S2329/port.c b/Source/portable/GCC/H8S2329/port.c deleted file mode 100644 index 31301a210..000000000 --- a/Source/portable/GCC/H8S2329/port.c +++ /dev/null @@ -1,306 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - - -/*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the H8S port. - *----------------------------------------------------------*/ - - -/*-----------------------------------------------------------*/ - -/* When the task starts interrupts should be enabled. */ -#define portINITIAL_CCR ( ( portSTACK_TYPE ) 0x00 ) - -/* Hardware specific constants used to generate the RTOS tick from the TPU. */ -#define portCLEAR_ON_TGRA_COMPARE_MATCH ( ( unsigned portCHAR ) 0x20 ) -#define portCLOCK_DIV_64 ( ( unsigned portCHAR ) 0x03 ) -#define portCLOCK_DIV ( ( unsigned portLONG ) 64 ) -#define portTGRA_INTERRUPT_ENABLE ( ( unsigned portCHAR ) 0x01 ) -#define portTIMER_CHANNEL ( ( unsigned portCHAR ) 0x02 ) -#define portMSTP13 ( ( unsigned portSHORT ) 0x2000 ) - -/* - * Setup TPU channel one for the RTOS tick at the requested frequency. - */ -static void prvSetupTimerInterrupt( void ); - -/* - * The ISR used by portYIELD(). This is installed as a trap handler. - */ -void vPortYield( void ) __attribute__ ( ( saveall, interrupt_handler ) ); - -/*-----------------------------------------------------------*/ - -/* - * See header file for description. - */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) -{ -unsigned portLONG ulValue; - - /* This requires an even address. */ - ulValue = ( unsigned portLONG ) pxTopOfStack; - if( ulValue & 1UL ) - { - pxTopOfStack = pxTopOfStack - 1; - } - - /* Place a few bytes of known values on the bottom of the stack. - This is just useful for debugging. */ - pxTopOfStack--; - *pxTopOfStack = 0xaa; - pxTopOfStack--; - *pxTopOfStack = 0xbb; - pxTopOfStack--; - *pxTopOfStack = 0xcc; - pxTopOfStack--; - *pxTopOfStack = 0xdd; - - /* The initial stack mimics an interrupt stack. First there is the program - counter (24 bits). */ - ulValue = ( unsigned portLONG ) pxCode; - - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) ( ulValue & 0xff ); - pxTopOfStack--; - ulValue >>= 8UL; - *pxTopOfStack = ( portSTACK_TYPE ) ( ulValue & 0xff ); - pxTopOfStack--; - ulValue >>= 8UL; - *pxTopOfStack = ( portSTACK_TYPE ) ( ulValue & 0xff ); - - /* Followed by the CCR. */ - pxTopOfStack--; - *pxTopOfStack = portINITIAL_CCR; - - /* Next all the general purpose registers - with the parameters being passed - in ER0. The parameter order must match that used by the compiler when the - "saveall" function attribute is used. */ - - /* ER6 */ - pxTopOfStack--; - *pxTopOfStack = 0x66; - pxTopOfStack--; - *pxTopOfStack = 0x66; - pxTopOfStack--; - *pxTopOfStack = 0x66; - pxTopOfStack--; - *pxTopOfStack = 0x66; - - /* ER0 */ - ulValue = ( unsigned portLONG ) pvParameters; - - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) ( ulValue & 0xff ); - pxTopOfStack--; - ulValue >>= 8UL; - *pxTopOfStack = ( portSTACK_TYPE ) ( ulValue & 0xff ); - pxTopOfStack--; - ulValue >>= 8UL; - *pxTopOfStack = ( portSTACK_TYPE ) ( ulValue & 0xff ); - pxTopOfStack--; - ulValue >>= 8UL; - *pxTopOfStack = ( portSTACK_TYPE ) ( ulValue & 0xff ); - - /* ER1 */ - pxTopOfStack--; - *pxTopOfStack = 0x11; - pxTopOfStack--; - *pxTopOfStack = 0x11; - pxTopOfStack--; - *pxTopOfStack = 0x11; - pxTopOfStack--; - *pxTopOfStack = 0x11; - - /* ER2 */ - pxTopOfStack--; - *pxTopOfStack = 0x22; - pxTopOfStack--; - *pxTopOfStack = 0x22; - pxTopOfStack--; - *pxTopOfStack = 0x22; - pxTopOfStack--; - *pxTopOfStack = 0x22; - - /* ER3 */ - pxTopOfStack--; - *pxTopOfStack = 0x33; - pxTopOfStack--; - *pxTopOfStack = 0x33; - pxTopOfStack--; - *pxTopOfStack = 0x33; - pxTopOfStack--; - *pxTopOfStack = 0x33; - - /* ER4 */ - pxTopOfStack--; - *pxTopOfStack = 0x44; - pxTopOfStack--; - *pxTopOfStack = 0x44; - pxTopOfStack--; - *pxTopOfStack = 0x44; - pxTopOfStack--; - *pxTopOfStack = 0x44; - - /* ER5 */ - pxTopOfStack--; - *pxTopOfStack = 0x55; - pxTopOfStack--; - *pxTopOfStack = 0x55; - pxTopOfStack--; - *pxTopOfStack = 0x55; - pxTopOfStack--; - *pxTopOfStack = 0x55; - - return pxTopOfStack; -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xPortStartScheduler( void ) -{ -extern void * pxCurrentTCB; - - /* Setup the hardware to generate the tick. */ - prvSetupTimerInterrupt(); - - /* Restore the context of the first task that is going to run. This - mirrors the function epilogue code generated by the compiler when the - "saveall" function attribute is used. */ - asm volatile ( - "MOV.L @_pxCurrentTCB, ER6 \n\t" - "MOV.L @ER6, ER7 \n\t" - "LDM.L @SP+, (ER4-ER5) \n\t" - "LDM.L @SP+, (ER0-ER3) \n\t" - "MOV.L @ER7+, ER6 \n\t" - "RTE \n\t" - ); - - ( void ) pxCurrentTCB; - - /* Should not get here. */ - return pdTRUE; -} -/*-----------------------------------------------------------*/ - -void vPortEndScheduler( void ) -{ - /* It is unlikely that the h8 port will get stopped. */ -} -/*-----------------------------------------------------------*/ - -/* - * Manual context switch. This is a trap handler. The "saveall" function - * attribute is used so the context is saved by the compiler prologue. All - * we have to do is save the stack pointer. - */ -void vPortYield( void ) -{ - portSAVE_STACK_POINTER(); - vTaskSwitchContext(); - portRESTORE_STACK_POINTER(); -} -/*-----------------------------------------------------------*/ - -/* - * The interrupt handler installed for the RTOS tick depends on whether the - * preemptive or cooperative scheduler is being used. - */ -#if( configUSE_PREEMPTION == 1 ) - - /* - * The preemptive scheduler is used so the ISR calls vTaskSwitchContext(). - * The function prologue saves the context so all we have to do is save - * the stack pointer. - */ - void vTickISR( void ) __attribute__ ( ( saveall, interrupt_handler ) ); - void vTickISR( void ) - { - portSAVE_STACK_POINTER(); - - vTaskIncrementTick(); - vTaskSwitchContext(); - - /* Clear the interrupt. */ - TSR1 &= ~0x01; - - portRESTORE_STACK_POINTER(); - } - -#else - - /* - * The cooperative scheduler is being used so all we have to do is - * periodically increment the tick. This can just be a normal ISR and - * the "saveall" attribute is not required. - */ - void vTickISR( void ) __attribute__ ( ( interrupt_handler ) ); - void vTickISR( void ) - { - vTaskIncrementTick(); - - /* Clear the interrupt. */ - TSR1 &= ~0x01; - } - -#endif -/*-----------------------------------------------------------*/ - -/* - * Setup timer 1 compare match to generate a tick interrupt. - */ -static void prvSetupTimerInterrupt( void ) -{ -const unsigned portLONG ulCompareMatch = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) / portCLOCK_DIV; - - /* Turn the module on. */ - MSTPCR &= ~portMSTP13; - - /* Configure timer 1. */ - TCR1 = portCLEAR_ON_TGRA_COMPARE_MATCH | portCLOCK_DIV_64; - - /* Configure the compare match value for a tick of configTICK_RATE_HZ. */ - TGR1A = ulCompareMatch; - - /* Start the timer and enable the interrupt - we can do this here as - interrupts are globally disabled when this function is called. */ - TIER1 |= portTGRA_INTERRUPT_ENABLE; - TSTR |= portTIMER_CHANNEL; -} -/*-----------------------------------------------------------*/ - - - diff --git a/Source/portable/GCC/H8S2329/portmacro.h b/Source/portable/GCC/H8S2329/portmacro.h deleted file mode 100644 index 3d7dc4322..000000000 --- a/Source/portable/GCC/H8S2329/portmacro.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -/*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the - * given hardware and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - -/* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE unsigned portCHAR -#define portBASE_TYPE char - -#if( configUSE_16_BIT_TICKS == 1 ) - typedef unsigned portSHORT portTickType; - #define portMAX_DELAY ( portTickType ) 0xffff -#else - typedef unsigned portLONG portTickType; - #define portMAX_DELAY ( portTickType ) 0xffffffff -#endif -/*-----------------------------------------------------------*/ - -/* Hardware specifics. */ -#define portBYTE_ALIGNMENT 2 -#define portSTACK_GROWTH ( -1 ) -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) -#define portYIELD() asm volatile( "TRAPA #0" ) -#define portNOP() asm volatile( "NOP" ) -/*-----------------------------------------------------------*/ - -/* Critical section handling. */ -#define portENABLE_INTERRUPTS() asm volatile( "ANDC #0x7F, CCR" ); -#define portDISABLE_INTERRUPTS() asm volatile( "ORC #0x80, CCR" ); - -/* Push the CCR then disable interrupts. */ -#define portENTER_CRITICAL() asm volatile( "STC CCR, @-ER7" ); \ - portDISABLE_INTERRUPTS(); - -/* Pop the CCR to set the interrupt masking back to its previous state. */ -#define portEXIT_CRITICAL() asm volatile( "LDC @ER7+, CCR" ); -/*-----------------------------------------------------------*/ - -/* Task utilities. */ - -/* Context switch macros. These macros are very simple as the context -is saved simply by selecting the saveall attribute of the context switch -interrupt service routines. These macros save and restore the stack -pointer to the TCB. */ - -#define portSAVE_STACK_POINTER() \ -extern void* pxCurrentTCB; \ - \ - asm volatile( \ - "MOV.L @_pxCurrentTCB, ER5 \n\t" \ - "MOV.L ER7, @ER5 \n\t" \ - ); \ - ( void ) pxCurrentTCB; - - -#define portRESTORE_STACK_POINTER() \ -extern void* pxCurrentTCB; \ - \ - asm volatile( \ - "MOV.L @_pxCurrentTCB, ER5 \n\t" \ - "MOV.L @ER5, ER7 \n\t" \ - ); \ - ( void ) pxCurrentTCB; - -/*-----------------------------------------------------------*/ - -/* Macros to allow a context switch from within an application ISR. */ - -#define portENTER_SWITCHING_ISR() portSAVE_STACK_POINTER(); { - -#define portEXIT_SWITCHING_ISR( x ) \ - if( x ) \ - { \ - extern void vTaskSwitchContext( void ); \ - vTaskSwitchContext(); \ - } \ - } portRESTORE_STACK_POINTER(); -/*-----------------------------------------------------------*/ - -/* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) - -#endif /* PORTMACRO_H */ - diff --git a/Source/portable/GCC/HCS12/port.c b/Source/portable/GCC/HCS12/port.c deleted file mode 100644 index a4b687ed8..000000000 --- a/Source/portable/GCC/HCS12/port.c +++ /dev/null @@ -1,242 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* GCC/HCS12 port by Jefferson L Smith, 2005 */ - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Port includes */ -#include - -/*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the HCS12 port. - *----------------------------------------------------------*/ - - -/* - * Configure a timer to generate the RTOS tick at the frequency specified - * within FreeRTOSConfig.h. - */ -static void prvSetupTimerInterrupt( void ); - -/* NOTE: Interrupt service routines must be in non-banked memory - as does the -scheduler startup function. */ -#define ATTR_NEAR __attribute__((near)) - -/* Manual context switch function. This is the SWI ISR. */ -// __attribute__((interrupt)) -void ATTR_NEAR vPortYield( void ); - -/* Tick context switch function. This is the timer ISR. */ -// __attribute__((interrupt)) -void ATTR_NEAR vPortTickInterrupt( void ); - -/* Function in non-banked memory which actually switches to first task. */ -portBASE_TYPE ATTR_NEAR xStartSchedulerNear( void ); - -/* Calls to portENTER_CRITICAL() can be nested. When they are nested the -critical section should not be left (i.e. interrupts should not be re-enabled) -until the nesting depth reaches 0. This variable simply tracks the nesting -depth. Each task maintains it's own critical nesting depth variable so -uxCriticalNesting is saved and restored from the task stack during a context -switch. */ -volatile unsigned portBASE_TYPE uxCriticalNesting = 0x80; // un-initialized - -/*-----------------------------------------------------------*/ - -/* - * See header file for description. - */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) -{ - - - /* Setup the initial stack of the task. The stack is set exactly as - expected by the portRESTORE_CONTEXT() macro. In this case the stack as - expected by the HCS12 RTI instruction. */ - - - /* The address of the task function is placed in the stack byte at a time. */ - *pxTopOfStack = ( portSTACK_TYPE ) *( ((portSTACK_TYPE *) (&pxCode) ) + 1 ); - *--pxTopOfStack = ( portSTACK_TYPE ) *( ((portSTACK_TYPE *) (&pxCode) ) + 0 ); - - /* Next are all the registers that form part of the task context. */ - - /* Y register */ - *--pxTopOfStack = ( portSTACK_TYPE ) 0xff; - *--pxTopOfStack = ( portSTACK_TYPE ) 0xee; - - /* X register */ - *--pxTopOfStack = ( portSTACK_TYPE ) 0xdd; - *--pxTopOfStack = ( portSTACK_TYPE ) 0xcc; - - /* A register contains parameter high byte. */ - *--pxTopOfStack = ( portSTACK_TYPE ) *( ((portSTACK_TYPE *) (&pvParameters) ) + 0 ); - - /* B register contains parameter low byte. */ - *--pxTopOfStack = ( portSTACK_TYPE ) *( ((portSTACK_TYPE *) (&pvParameters) ) + 1 ); - - /* CCR: Note that when the task starts interrupts will be enabled since - "I" bit of CCR is cleared */ - *--pxTopOfStack = ( portSTACK_TYPE ) 0x80; // keeps Stop disabled (MCU default) - - /* tmp softregs used by GCC. Values right now don't matter. */ - __asm("\n\ - movw _.frame, 2,-%0 \n\ - movw _.tmp, 2,-%0 \n\ - movw _.z, 2,-%0 \n\ - movw _.xy, 2,-%0 \n\ - ;movw _.d2, 2,-%0 \n\ - ;movw _.d1, 2,-%0 \n\ - ": "=A"(pxTopOfStack) : "0"(pxTopOfStack) ); - - #ifdef BANKED_MODEL - /* The page of the task. */ - *--pxTopOfStack = 0x30; // can only directly start in PPAGE 0x30 - #endif - - /* The critical nesting depth is initialised with 0 (meaning not in - a critical section). */ - *--pxTopOfStack = ( portSTACK_TYPE ) 0x00; - - - return pxTopOfStack; -} -/*-----------------------------------------------------------*/ - -void vPortEndScheduler( void ) -{ - /* It is unlikely that the HCS12 port will get stopped. */ -} -/*-----------------------------------------------------------*/ - -static void prvSetupTimerInterrupt( void ) -{ - /* Enable hardware RTI timer */ - /* Ignores configTICK_RATE_HZ */ - RTICTL = 0x50; // 16 MHz xtal: 976.56 Hz, 1024mS - CRGINT |= 0x80; // RTIE -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xPortStartScheduler( void ) -{ - /* xPortStartScheduler() does not start the scheduler directly because - the header file containing the xPortStartScheduler() prototype is part - of the common kernel code, and therefore cannot use the CODE_SEG pragma. - Instead it simply calls the locally defined xNearStartScheduler() - - which does use the CODE_SEG pragma. */ - - short register d; - __asm ("jmp xStartSchedulerNear ; will never return": "=d"(d)); - return d; -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xStartSchedulerNear( void ) -{ - /* Configure the timer that will generate the RTOS tick. Interrupts are - disabled when this function is called. */ - prvSetupTimerInterrupt(); - - /* Restore the context of the first task. */ - portRESTORE_CONTEXT(); - - portISR_TAIL(); - - /* Should not get here! */ - return pdFALSE; -} -/*-----------------------------------------------------------*/ - -/* - * Context switch functions. These are interrupt service routines. - */ - -/* - * Manual context switch forced by calling portYIELD(). This is the SWI - * handler. - */ -void vPortYield( void ) -{ - portISR_HEAD(); - /* NOTE: This is the trap routine (swi) although not defined as a trap. - It will fill the stack the same way as an ISR in order to mix preemtion - and cooperative yield. */ - - portSAVE_CONTEXT(); - vTaskSwitchContext(); - portRESTORE_CONTEXT(); - - portISR_TAIL(); -} -/*-----------------------------------------------------------*/ - -/* - * RTOS tick interrupt service routine. If the cooperative scheduler is - * being used then this simply increments the tick count. If the - * preemptive scheduler is being used a context switch can occur. - */ -void vPortTickInterrupt( void ) -{ - portISR_HEAD(); - - /* Clear tick timer flag */ - CRGFLG = 0x80; - - #if configUSE_PREEMPTION == 1 - { - /* A context switch might happen so save the context. */ - portSAVE_CONTEXT(); - - /* Increment the tick ... */ - vTaskIncrementTick(); - - /* ... then see if the new tick value has necessitated a - context switch. */ - vTaskSwitchContext(); - - /* Restore the context of a task - which may be a different task - to that interrupted. */ - portRESTORE_CONTEXT(); - } - #else - { - vTaskIncrementTick(); - } - #endif - - portISR_TAIL(); -} - diff --git a/Source/portable/GCC/HCS12/portmacro.h b/Source/portable/GCC/HCS12/portmacro.h deleted file mode 100644 index ca6355872..000000000 --- a/Source/portable/GCC/HCS12/portmacro.h +++ /dev/null @@ -1,239 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -/*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the - * given hardware and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - -/* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE unsigned portCHAR -#define portBASE_TYPE char - -#if( configUSE_16_BIT_TICKS == 1 ) - typedef unsigned portSHORT portTickType; - #define portMAX_DELAY ( portTickType ) 0xffff -#else - typedef unsigned portLONG portTickType; - #define portMAX_DELAY ( portTickType ) 0xffffffff -#endif -/*-----------------------------------------------------------*/ - -/* Hardware specifics. */ -#define portBYTE_ALIGNMENT 1 -#define portSTACK_GROWTH ( -1 ) -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) -#define portYIELD() __asm( "swi" ); -/*-----------------------------------------------------------*/ - -/* Critical section handling. */ -#define portENABLE_INTERRUPTS() __asm( "cli" ) -#define portDISABLE_INTERRUPTS() __asm( "sei" ) - -/* - * Disable interrupts before incrementing the count of critical section nesting. - * The nesting count is maintained so we know when interrupts should be - * re-enabled. Once interrupts are disabled the nesting count can be accessed - * directly. Each task maintains its own nesting count. - */ -#define portENTER_CRITICAL() \ -{ \ - extern volatile unsigned portBASE_TYPE uxCriticalNesting; \ - \ - portDISABLE_INTERRUPTS(); \ - uxCriticalNesting++; \ -} - -/* - * Interrupts are disabled so we can access the nesting count directly. If the - * nesting is found to be 0 (no nesting) then we are leaving the critical - * section and interrupts can be re-enabled. - */ -#define portEXIT_CRITICAL() \ -{ \ - extern volatile unsigned portBASE_TYPE uxCriticalNesting; \ - \ - uxCriticalNesting--; \ - if( uxCriticalNesting == 0 ) \ - { \ - portENABLE_INTERRUPTS(); \ - } \ -} -/*-----------------------------------------------------------*/ - -/* Task utilities. */ - -/* - * These macros are very simple as the processor automatically saves and - * restores its registers as interrupts are entered and exited. In - * addition to the (automatically stacked) registers we also stack the - * critical nesting count. Each task maintains its own critical nesting - * count as it is legitimate for a task to yield from within a critical - * section. If the banked memory model is being used then the PPAGE - * register is also stored as part of the tasks context. - */ - -#ifdef BANKED_MODEL - /* - * Load the stack pointer for the task, then pull the critical nesting - * count and PPAGE register from the stack. The remains of the - * context are restored by the RTI instruction. - */ - #define portRESTORE_CONTEXT() \ - { \ - __asm( " \n\ - .globl pxCurrentTCB ; void * \n\ - .globl uxCriticalNesting ; char \n\ - \n\ - ldx pxCurrentTCB \n\ - lds 0,x ; Stack \n\ - \n\ - movb 1,sp+,uxCriticalNesting \n\ - movb 1,sp+,0x30 ; PPAGE \n\ - " ); \ - } - - /* - * By the time this macro is called the processor has already stacked the - * registers. Simply stack the nesting count and PPAGE value, then save - * the task stack pointer. - */ - #define portSAVE_CONTEXT() \ - { \ - __asm( " \n\ - .globl pxCurrentTCB ; void * \n\ - .globl uxCriticalNesting ; char \n\ - \n\ - movb 0x30, 1,-sp ; PPAGE \n\ - movb uxCriticalNesting, 1,-sp \n\ - \n\ - ldx pxCurrentTCB \n\ - sts 0,x ; Stack \n\ - " ); \ - } -#else - - /* - * These macros are as per the BANKED versions above, but without saving - * and restoring the PPAGE register. - */ - - #define portRESTORE_CONTEXT() \ - { \ - __asm( " \n\ - .globl pxCurrentTCB ; void * \n\ - .globl uxCriticalNesting ; char \n\ - \n\ - ldx pxCurrentTCB \n\ - lds 0,x ; Stack \n\ - \n\ - movb 1,sp+,uxCriticalNesting \n\ - " ); \ - } - - #define portSAVE_CONTEXT() \ - { \ - __asm( " \n\ - .globl pxCurrentTCB ; void * \n\ - .globl uxCriticalNesting ; char \n\ - \n\ - movb uxCriticalNesting, 1,-sp \n\ - \n\ - ldx pxCurrentTCB \n\ - sts 0,x ; Stack \n\ - " ); \ - } -#endif - -/* - * Utility macros to save/restore correct software registers for GCC. This is - * useful when GCC does not generate appropriate ISR head/tail code. - */ -#define portISR_HEAD() \ -{ \ - __asm(" \n\ - movw _.frame, 2,-sp \n\ - movw _.tmp, 2,-sp \n\ - movw _.z, 2,-sp \n\ - movw _.xy, 2,-sp \n\ - ;movw _.d2, 2,-sp \n\ - ;movw _.d1, 2,-sp \n\ - "); \ -} - -#define portISR_TAIL() \ -{ \ - __asm(" \n\ - movw 2,sp+, _.xy \n\ - movw 2,sp+, _.z \n\ - movw 2,sp+, _.tmp \n\ - movw 2,sp+, _.frame \n\ - ;movw 2,sp+, _.d1 \n\ - ;movw 2,sp+, _.d2 \n\ - rti \n\ - "); \ -} - -/* - * Utility macro to call macros above in correct order in order to perform a - * task switch from within a standard ISR. This macro can only be used if - * the ISR does not use any local (stack) variables. If the ISR uses stack - * variables portYIELD() should be used in it's place. - */ - -#define portTASK_SWITCH_FROM_ISR() \ - portSAVE_CONTEXT(); \ - vTaskSwitchContext(); \ - portRESTORE_CONTEXT(); - - -/* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) - - -#endif /* PORTMACRO_H */ - diff --git a/Source/portable/GCC/MCF5235/port.c b/Source/portable/GCC/MCF5235/port.c deleted file mode 100644 index 58ae34033..000000000 --- a/Source/portable/GCC/MCF5235/port.c +++ /dev/null @@ -1,263 +0,0 @@ -/* - FreeRTOS V4.1.1 - Copyright (C) 2003-2006 Richard Barry. - MCF5235 Port - Copyright (C) 2006 Christian Walter. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#include - -#include "FreeRTOS.h" -#include "FreeRTOSConfig.h" -#include "task.h" - -/* ------------------------ Types ----------------------------------------- */ -typedef volatile unsigned long vuint32; -typedef volatile unsigned short vuint16; -typedef volatile unsigned char vuint8; - -/* ------------------------ Defines --------------------------------------- */ -#define portVECTOR_TABLE __RAMVEC -#define portVECTOR_SYSCALL ( 32 + portTRAP_YIELD ) -#define portVECTOR_TIMER ( 64 + 36 ) - -#define MCF_PIT_PRESCALER 512UL -#define MCF_PIT_TIMER_TICKS ( FSYS_2 / MCF_PIT_PRESCALER ) -#define MCF_PIT_MODULUS_REGISTER(freq) ( MCF_PIT_TIMER_TICKS / ( freq ) - 1UL) - -#define MCF_PIT_PMR0 ( *( vuint16 * )( void * )( &__IPSBAR[ 0x150002 ] ) ) -#define MCF_PIT_PCSR0 ( *( vuint16 * )( void * )( &__IPSBAR[ 0x150000 ] ) ) -#define MCF_PIT_PCSR_PRE(x) ( ( ( x ) & 0x000F ) << 8 ) -#define MCF_PIT_PCSR_EN ( 0x0001 ) -#define MCF_PIT_PCSR_RLD ( 0x0002 ) -#define MCF_PIT_PCSR_PIF ( 0x0004 ) -#define MCF_PIT_PCSR_PIE ( 0x0008 ) -#define MCF_PIT_PCSR_OVW ( 0x0010 ) -#define MCF_INTC0_ICR36 ( *( vuint8 * )( void * )( &__IPSBAR[ 0x000C64 ] ) ) -#define MCF_INTC0_IMRH ( *( vuint32 * )( void * )( &__IPSBAR[ 0x000C08 ] ) ) -#define MCF_INTC0_IMRH_INT_MASK36 ( 0x00000010 ) -#define MCF_INTC0_IMRH_MASKALL ( 0x00000001 ) -#define MCF_INTC0_ICRn_IP(x) ( ( ( x ) & 0x07 ) << 0 ) -#define MCF_INTC0_ICRn_IL(x) ( ( ( x ) & 0x07 ) << 3 ) - -#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 ) -#define portINITIAL_CRITICAL_NESTING ( ( unsigned portLONG ) 10 ) - -/* ------------------------ Static variables ------------------------------ */ -volatile unsigned portLONG ulCriticalNesting = portINITIAL_CRITICAL_NESTING; - -/* ------------------------ Static functions ------------------------------ */ -#if configUSE_PREEMPTION == 0 -static void prvPortPreemptiveTick ( void ) __attribute__ ((interrupt_handler)); -#else -static void prvPortPreemptiveTick ( void ); -#endif - -/* ------------------------ Start implementation -------------------------- */ - -portSTACK_TYPE * -pxPortInitialiseStack( portSTACK_TYPE * pxTopOfStack, pdTASK_CODE pxCode, - void *pvParameters ) -{ - /* Place the parameter on the stack in the expected location. */ - *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; - pxTopOfStack--; - - /* Place dummy return address on stack. Tasks should never terminate so - * we can set this to anything. */ - *pxTopOfStack = ( portSTACK_TYPE ) 0; - pxTopOfStack--; - - /* Create a Motorola Coldfire exception stack frame. First comes the return - * address. */ - *pxTopOfStack = ( portSTACK_TYPE ) pxCode; - pxTopOfStack--; - - /* Format, fault-status, vector number for exception stack frame. Task - * run in supervisor mode. */ - *pxTopOfStack = 0x40002000UL | ( portVECTOR_SYSCALL + 32 ) << 18; - pxTopOfStack--; - - /* Set the initial critical section nesting counter to zero. This value - * is used to restore the value of ulCriticalNesting. */ - *pxTopOfStack = 0; - *pxTopOfStack--; - - *pxTopOfStack = ( portSTACK_TYPE ) 0xA6; /* A6 / FP */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xA5; /* A5 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xA4; /* A4 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xA3; /* A3 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xA2; /* A2 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xA1; /* A1 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xA0; /* A0 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xD7; /* D7 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xD6; /* D6 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xD5; /* D5 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xD4; /* D4 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xD3; /* D3 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xD2; /* D2 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xD1; /* D1 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xD0; /* D0 */ - - return pxTopOfStack; -} - -/* - * Called by portYIELD() or taskYIELD() to manually force a context switch. - */ -static void -prvPortYield( void ) -{ - asm volatile ( "move.w #0x2700, %sr\n\t" ); -#if _GCC_USES_FP == 1 - asm volatile ( "unlk %fp\n\t" ); -#endif - /* Perform the context switch. First save the context of the current task. */ - portSAVE_CONTEXT( ); - - /* Find the highest priority task that is ready to run. */ - vTaskSwitchContext( ); - - /* Restore the context of the new task. */ - portRESTORE_CONTEXT( ); -} - -#if configUSE_PREEMPTION == 0 -/* - * The ISR used for the scheduler tick depends on whether the cooperative or - * the preemptive scheduler is being used. - */ -static void -prvPortPreemptiveTick ( void ) -{ - /* The cooperative scheduler requires a normal IRQ service routine to - * simply increment the system tick. - */ - - vTaskIncrementTick( ); - MCF_PIT_PCSR0 |= MCF_PIT_PCSR_PIF; -} - -#else - -static void -prvPortPreemptiveTick( void ) -{ - asm volatile ( "move.w #0x2700, %sr\n\t" ); -#if _GCC_USES_FP == 1 - asm volatile ( "unlk %fp\n\t" ); -#endif - portSAVE_CONTEXT( ); - MCF_PIT_PCSR0 |= MCF_PIT_PCSR_PIF; - vTaskIncrementTick( ); - vTaskSwitchContext( ); - portRESTORE_CONTEXT( ); -} -#endif - -void -vPortEnterCritical() -{ - /* FIXME: We should store the old IPL here - How are we supposed to do - * this. - */ - ( void )portSET_IPL( portIPL_MAX ); - - /* Now interrupts are disabled ulCriticalNesting can be accessed - * directly. Increment ulCriticalNesting to keep a count of how many times - * portENTER_CRITICAL() has been called. */ - ulCriticalNesting++; -} - -void -vPortExitCritical() -{ - if( ulCriticalNesting > portNO_CRITICAL_NESTING ) - { - /* Decrement the nesting count as we are leaving a critical section. */ - ulCriticalNesting--; - - /* If the nesting level has reached zero then interrupts should be - re-enabled. */ - if( ulCriticalNesting == portNO_CRITICAL_NESTING ) - { - ( void )portSET_IPL( 0 ); - } - } -} - -portBASE_TYPE -xPortStartScheduler( void ) -{ - extern void ( *portVECTOR_TABLE[ ] ) ( ); - - /* Add entry in vector table for yield system call. */ - portVECTOR_TABLE[ portVECTOR_SYSCALL ] = prvPortYield; - /* Add entry in vector table for periodic timer. */ - portVECTOR_TABLE[ portVECTOR_TIMER ] = prvPortPreemptiveTick; - - /* Configure the timer for the system clock. */ - if ( configTICK_RATE_HZ > 0) - { - /* Configure prescaler */ - MCF_PIT_PCSR0 = MCF_PIT_PCSR_PRE( 0x9 ) | MCF_PIT_PCSR_RLD | MCF_PIT_PCSR_OVW; - /* Initialize the periodic timer interrupt. */ - MCF_PIT_PMR0 = MCF_PIT_MODULUS_REGISTER( configTICK_RATE_HZ ); - /* Configure interrupt priority and level and unmask interrupt. */ - MCF_INTC0_ICR36 = MCF_INTC0_ICRn_IL( 0x1 ) | MCF_INTC0_ICRn_IP( 0x1 ); - MCF_INTC0_IMRH &= ~( MCF_INTC0_IMRH_INT_MASK36 | MCF_INTC0_IMRH_MASKALL ); - /* Enable interrupts */ - MCF_PIT_PCSR0 |= MCF_PIT_PCSR_PIE | MCF_PIT_PCSR_EN | MCF_PIT_PCSR_PIF; - } - - /* Restore the context of the first task that is going to run. */ - portRESTORE_CONTEXT( ); - - /* Should not get here. */ - return pdTRUE; -} - -void -vPortEndScheduler( void ) -{ -} diff --git a/Source/portable/GCC/MCF5235/portmacro.h b/Source/portable/GCC/MCF5235/portmacro.h deleted file mode 100644 index b6966948b..000000000 --- a/Source/portable/GCC/MCF5235/portmacro.h +++ /dev/null @@ -1,148 +0,0 @@ -/* - FreeRTOS V4.1.1 - Copyright (C) 2003-2006 Richard Barry. - MCF5235 Port - Copyright (C) 2006 Christian Walter. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -/* ------------------------ Data types for Coldfire ----------------------- */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE unsigned int -#define portBASE_TYPE int - -#if( USE_16_BIT_TICKS == 1 ) - typedef unsigned portSHORT portTickType; - #define portMAX_DELAY ( portTickType ) 0xffff -#else - typedef unsigned portLONG portTickType; - #define portMAX_DELAY ( portTickType ) 0xffffffff -#endif - -/* ------------------------ Architecture specifics ------------------------ */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 4 - -#define portTRAP_YIELD 0 /* Trap 0 */ -#define portIPL_MAX 7 /* Only NMI interrupt 7 allowed. */ - -/* ------------------------ FreeRTOS macros for port ---------------------- */ - -/* - * This function must be called when the current state of the active task - * should be stored. It must be called immediately after exception - * processing from the CPU, i.e. there exists a Coldfire exception frame at - * the current position in the stack. The function reserves space on - * the stack for the CPU registers and other task dependent values (e.g - * ulCriticalNesting) and updates the top of the stack in the TCB. - */ -#define portSAVE_CONTEXT() \ - asm volatile ( /* reserve space for task state. */ \ - "lea.l (-64, %sp), %sp\n\t" \ - /* push data register %d0-%d7/%a0-%a6 on stack. */ \ - "movem.l %d0-%d7/%a0-%a6, (%sp)\n\t" \ - /* push ulCriticalNesting counter on stack. */ \ - "lea.l (60, %sp), %a0\n\t" \ - "move.l ulCriticalNesting, (%a0)\n\t" \ - /* set the new top of the stack in the TCB. */ \ - "move.l pxCurrentTCB, %a0\n\t" \ - "move.l %sp, (%a0)"); - -/*. - * This function restores the current active and continues its execution. - * It loads the current TCB and restores the processor registers, the - * task dependent values (e.g ulCriticalNesting). Finally execution - * is continued by executing an rte instruction. - */ -#define portRESTORE_CONTEXT() \ - asm volatile ( "move.l pxCurrentTCB, %sp\n\t" \ - "move.l (%sp), %sp\n\t" \ - /* stack pointer now points to the saved registers. */ \ - "movem.l (%sp), %d0-%d7/%a0-%a6\n\t" \ - /* restore ulCriticalNesting counter from stack. */ \ - "lea.l (%sp, 60), %sp\n\t" \ - "move.l (%sp)+, ulCriticalNesting\n\t" \ - /* stack pointer now points to exception frame. */ \ - "rte\n\t" ); - -#define portENTER_CRITICAL() \ - vPortEnterCritical(); - -#define portEXIT_CRITICAL() \ - vPortExitCritical(); - -#define portSET_IPL( xIPL ) \ - asm_set_ipl( xIPL ) - -#define portDISABLE_INTERRUPTS() \ - do { ( void )portSET_IPL( portIPL_MAX ); } while( 0 ) -#define portENABLE_INTERRUPTS() \ - do { ( void )portSET_IPL( 0 ); } while( 0 ) - -#define portYIELD() \ - asm volatile ( " trap %0\n\t" : : "i"(portTRAP_YIELD) ) - -#define portNOP() \ - asm volatile ( "nop\n\t" ) - -#define portENTER_SWITCHING_ISR() \ - asm volatile ( "move.w #0x2700, %sr" ); \ - /* Save the context of the interrupted task. */ \ - portSAVE_CONTEXT( ); \ - { - -#define portEXIT_SWITCHING_ISR( SwitchRequired ) \ - /* If a switch is required we call vTaskSwitchContext(). */ \ - if( SwitchRequired ) \ - { \ - vTaskSwitchContext( ); \ - } \ - } \ - portRESTORE_CONTEXT( ); - -/* ------------------------ Function prototypes --------------------------- */ -void vPortEnterCritical( void ); -void vPortExitCritical( void ); -int asm_set_ipl( unsigned long int uiNewIPL ); - -/* ------------------------ Compiler specifics ---------------------------- */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) \ - void vFunction( void *pvParameters ) - -#define portTASK_FUNCTION( vFunction, pvParameters ) \ - void vFunction( void *pvParameters ) -#endif - diff --git a/Source/portable/GCC/MSP430F449/port.c b/Source/portable/GCC/MSP430F449/port.c deleted file mode 100644 index d2d7aeacc..000000000 --- a/Source/portable/GCC/MSP430F449/port.c +++ /dev/null @@ -1,327 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - Changes from V2.5.2 - - + usCriticalNesting now has a volatile qualifier. -*/ - -/* Standard includes. */ -#include -#include - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the MSP430 port. - *----------------------------------------------------------*/ - -/* Constants required for hardware setup. The tick ISR runs off the ACLK, -not the MCLK. */ -#define portACLK_FREQUENCY_HZ ( ( portTickType ) 32768 ) -#define portINITIAL_CRITICAL_NESTING ( ( unsigned portSHORT ) 10 ) -#define portFLAGS_INT_ENABLED ( ( portSTACK_TYPE ) 0x08 ) - -/* We require the address of the pxCurrentTCB variable, but don't want to know -any details of its type. */ -typedef void tskTCB; -extern volatile tskTCB * volatile pxCurrentTCB; - -/* Most ports implement critical sections by placing the interrupt flags on -the stack before disabling interrupts. Exiting the critical section is then -simply a case of popping the flags from the stack. As mspgcc does not use -a frame pointer this cannot be done as modifying the stack will clobber all -the stack variables. Instead each task maintains a count of the critical -section nesting depth. Each time a critical section is entered the count is -incremented. Each time a critical section is left the count is decremented - -with interrupts only being re-enabled if the count is zero. - -usCriticalNesting will get set to zero when the scheduler starts, but must -not be initialised to zero as this will cause problems during the startup -sequence. */ -volatile unsigned portSHORT usCriticalNesting = portINITIAL_CRITICAL_NESTING; -/*-----------------------------------------------------------*/ - -/* - * Macro to save a task context to the task stack. This simply pushes all the - * general purpose msp430 registers onto the stack, followed by the - * usCriticalNesting value used by the task. Finally the resultant stack - * pointer value is saved into the task control block so it can be retrieved - * the next time the task executes. - */ -#define portSAVE_CONTEXT() \ - asm volatile ( "push r4 \n\t" \ - "push r5 \n\t" \ - "push r6 \n\t" \ - "push r7 \n\t" \ - "push r8 \n\t" \ - "push r9 \n\t" \ - "push r10 \n\t" \ - "push r11 \n\t" \ - "push r12 \n\t" \ - "push r13 \n\t" \ - "push r14 \n\t" \ - "push r15 \n\t" \ - "mov.w usCriticalNesting, r14 \n\t" \ - "push r14 \n\t" \ - "mov.w pxCurrentTCB, r12 \n\t" \ - "mov.w r1, @r12 \n\t" \ - ); - -/* - * Macro to restore a task context from the task stack. This is effectively - * the reverse of portSAVE_CONTEXT(). First the stack pointer value is - * loaded from the task control block. Next the value for usCriticalNesting - * used by the task is retrieved from the stack - followed by the value of all - * the general purpose msp430 registers. - */ -#define portRESTORE_CONTEXT() \ - asm volatile ( "mov.w pxCurrentTCB, r12 \n\t" \ - "mov.w @r12, r1 \n\t" \ - "pop r15 \n\t" \ - "mov.w r15, usCriticalNesting \n\t" \ - "pop r15 \n\t" \ - "pop r14 \n\t" \ - "pop r13 \n\t" \ - "pop r12 \n\t" \ - "pop r11 \n\t" \ - "pop r10 \n\t" \ - "pop r9 \n\t" \ - "pop r8 \n\t" \ - "pop r7 \n\t" \ - "pop r6 \n\t" \ - "pop r5 \n\t" \ - "pop r4 \n\t" \ - "reti \n\t" \ - ); -/*-----------------------------------------------------------*/ - -/* - * Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but - * could have alternatively used the watchdog timer or timer 1. - */ -static void prvSetupTimerInterrupt( void ); -/*-----------------------------------------------------------*/ - -/* - * Initialise the stack of a task to look exactly as if a call to - * portSAVE_CONTEXT had been called. - * - * See the header file portable.h. - */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) -{ - /* - Place a few bytes of known values on the bottom of the stack. - This is just useful for debugging and can be included if required. - - *pxTopOfStack = ( portSTACK_TYPE ) 0x1111; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x2222; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x3333; - pxTopOfStack--; - */ - - /* The msp430 automatically pushes the PC then SR onto the stack before - executing an ISR. We want the stack to look just as if this has happened - so place a pointer to the start of the task on the stack first - followed - by the flags we want the task to use when it starts up. */ - *pxTopOfStack = ( portSTACK_TYPE ) pxCode; - pxTopOfStack--; - *pxTopOfStack = portFLAGS_INT_ENABLED; - pxTopOfStack--; - - /* Next the general purpose registers. */ - *pxTopOfStack = ( portSTACK_TYPE ) 0x4444; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x5555; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x6666; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x7777; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x8888; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x9999; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaa; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xbbbb; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xcccc; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xdddd; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xeeee; - pxTopOfStack--; - - /* When the task starts is will expect to find the function parameter in - R15. */ - *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; - pxTopOfStack--; - - /* The code generated by the mspgcc compiler does not maintain separate - stack and frame pointers. The portENTER_CRITICAL macro cannot therefore - use the stack as per other ports. Instead a variable is used to keep - track of the critical section nesting. This variable has to be stored - as part of the task context and is initially set to zero. */ - *pxTopOfStack = ( portSTACK_TYPE ) portNO_CRITICAL_SECTION_NESTING; - - /* Return a pointer to the top of the stack we have generated so this can - be stored in the task control block for the task. */ - return pxTopOfStack; -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xPortStartScheduler( void ) -{ - /* Setup the hardware to generate the tick. Interrupts are disabled when - this function is called. */ - prvSetupTimerInterrupt(); - - /* Restore the context of the first task that is going to run. */ - portRESTORE_CONTEXT(); - - /* Should not get here as the tasks are now running! */ - return pdTRUE; -} -/*-----------------------------------------------------------*/ - -void vPortEndScheduler( void ) -{ - /* It is unlikely that the MSP430 port will get stopped. If required simply - disable the tick interrupt here. */ -} -/*-----------------------------------------------------------*/ - -/* - * Manual context switch called by portYIELD or taskYIELD. - * - * The first thing we do is save the registers so we can use a naked attribute. - */ -void vPortYield( void ) __attribute__ ( ( naked ) ); -void vPortYield( void ) -{ - /* We want the stack of the task being saved to look exactly as if the task - was saved during a pre-emptive RTOS tick ISR. Before calling an ISR the - msp430 places the status register onto the stack. As this is a function - call and not an ISR we have to do this manually. */ - asm volatile ( "push r2" ); - _DINT(); - - /* Save the context of the current task. */ - portSAVE_CONTEXT(); - - /* Switch to the highest priority task that is ready to run. */ - vTaskSwitchContext(); - - /* Restore the context of the new task. */ - portRESTORE_CONTEXT(); -} -/*-----------------------------------------------------------*/ - -/* - * Hardware initialisation to generate the RTOS tick. This uses timer 0 - * but could alternatively use the watchdog timer or timer 1. - */ -static void prvSetupTimerInterrupt( void ) -{ - /* Ensure the timer is stopped. */ - TACTL = 0; - - /* Run the timer of the ACLK. */ - TACTL = TASSEL_1; - - /* Clear everything to start with. */ - TACTL |= TACLR; - - /* Set the compare match value according to the tick rate we want. */ - TACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ; - - /* Enable the interrupts. */ - TACCTL0 = CCIE; - - /* Start up clean. */ - TACTL |= TACLR; - - /* Up mode. */ - TACTL |= MC_1; -} -/*-----------------------------------------------------------*/ - -/* - * The interrupt service routine used depends on whether the pre-emptive - * scheduler is being used or not. - */ - -#if configUSE_PREEMPTION == 1 - - /* - * Tick ISR for preemptive scheduler. We can use a naked attribute as - * the context is saved at the start of vPortYieldFromTick(). The tick - * count is incremented after the context is saved. - */ - interrupt (TIMERA0_VECTOR) prvTickISR( void ) __attribute__ ( ( naked ) ); - interrupt (TIMERA0_VECTOR) prvTickISR( void ) - { - /* Save the context of the interrupted task. */ - portSAVE_CONTEXT(); - - /* Increment the tick count then switch to the highest priority task - that is ready to run. */ - vTaskIncrementTick(); - vTaskSwitchContext(); - - /* Restore the context of the new task. */ - portRESTORE_CONTEXT(); - } - -#else - - /* - * Tick ISR for the cooperative scheduler. All this does is increment the - * tick count. We don't need to switch context, this can only be done by - * manual calls to taskYIELD(); - */ - interrupt (TIMERA0_VECTOR) prvTickISR( void ); - interrupt (TIMERA0_VECTOR) prvTickISR( void ) - { - vTaskIncrementTick(); - } -#endif - - - diff --git a/Source/portable/GCC/MSP430F449/portmacro.h b/Source/portable/GCC/MSP430F449/portmacro.h deleted file mode 100644 index 62eee0b57..000000000 --- a/Source/portable/GCC/MSP430F449/portmacro.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -/*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the - * given hardware and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - -/* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT int -#define portSTACK_TYPE unsigned portSHORT -#define portBASE_TYPE portSHORT - -#if( configUSE_16_BIT_TICKS == 1 ) - typedef unsigned portSHORT portTickType; - #define portMAX_DELAY ( portTickType ) 0xffff -#else - typedef unsigned portLONG portTickType; - #define portMAX_DELAY ( portTickType ) 0xffffffff -#endif -/*-----------------------------------------------------------*/ - -/* Interrupt control macros. */ -#define portDISABLE_INTERRUPTS() asm volatile ( "DINT" ) -#define portENABLE_INTERRUPTS() asm volatile ( "EINT" ) -/*-----------------------------------------------------------*/ - -/* Critical section control macros. */ -#define portNO_CRITICAL_SECTION_NESTING ( ( unsigned portSHORT ) 0 ) - -#define portENTER_CRITICAL() \ -{ \ -extern volatile unsigned portSHORT usCriticalNesting; \ - \ - portDISABLE_INTERRUPTS(); \ - \ - /* Now interrupts are disabled ulCriticalNesting can be accessed */ \ - /* directly. Increment ulCriticalNesting to keep a count of how many */ \ - /* times portENTER_CRITICAL() has been called. */ \ - usCriticalNesting++; \ -} - -#define portEXIT_CRITICAL() \ -{ \ -extern volatile unsigned portSHORT usCriticalNesting; \ - \ - if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ - { \ - /* Decrement the nesting count as we are leaving a critical section. */ \ - usCriticalNesting--; \ - \ - /* If the nesting level has reached zero then interrupts should be */ \ - /* re-enabled. */ \ - if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ - { \ - portENABLE_INTERRUPTS(); \ - } \ - } \ -} -/*-----------------------------------------------------------*/ - -/* Task utilities. */ -extern void vPortYield( void ) __attribute__ ( ( naked ) ); -#define portYIELD() vPortYield() -#define portNOP() asm volatile ( "NOP" ) -/*-----------------------------------------------------------*/ - -/* Hardwware specifics. */ -#define portBYTE_ALIGNMENT 2 -#define portSTACK_GROWTH ( -1 ) -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) -/*-----------------------------------------------------------*/ - -/* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) - -#endif /* PORTMACRO_H */ - diff --git a/Source/portable/GCC/MicroBlaze/port.c b/Source/portable/GCC/MicroBlaze/port.c deleted file mode 100644 index a9ee8c756..000000000 --- a/Source/portable/GCC/MicroBlaze/port.c +++ /dev/null @@ -1,337 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the MicroBlaze port. - *----------------------------------------------------------*/ - - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Standard includes. */ -#include - -/* Hardware includes. */ -#include -#include -#include - -/* Tasks are started with interrupts enabled. */ -#define portINITIAL_MSR_STATE ( ( portSTACK_TYPE ) 0x02 ) - -/* Tasks are started with a critical section nesting of 0 - however prior -to the scheduler being commenced we don't want the critical nesting level -to reach zero, so it is initialised to a high value. */ -#define portINITIAL_NESTING_VALUE ( 0xff ) - -/* Our hardware setup only uses one counter. */ -#define portCOUNTER_0 0 - -/* The stack used by the ISR is filled with a known value to assist in -debugging. */ -#define portISR_STACK_FILL_VALUE 0x55555555 - -/* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task -maintains it's own count, so this variable is saved as part of the task -context. */ -volatile unsigned portBASE_TYPE uxCriticalNesting = portINITIAL_NESTING_VALUE; - -/* To limit the amount of stack required by each task, this port uses a -separate stack for interrupts. */ -unsigned portLONG *pulISRStack; - -/*-----------------------------------------------------------*/ - -/* - * Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but - * could have alternatively used the watchdog timer or timer 1. - */ -static void prvSetupTimerInterrupt( void ); -/*-----------------------------------------------------------*/ - -/* - * Initialise the stack of a task to look exactly as if a call to - * portSAVE_CONTEXT had been made. - * - * See the header file portable.h. - */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) -{ -extern void *_SDA2_BASE_, *_SDA_BASE_; -const unsigned portLONG ulR2 = ( unsigned portLONG ) &_SDA2_BASE_; -const unsigned portLONG ulR13 = ( unsigned portLONG ) &_SDA_BASE_; - - /* Place a few bytes of known values on the bottom of the stack. - This is essential for the Microblaze port and these lines must - not be omitted. The parameter value will overwrite the - 0x22222222 value during the function prologue. */ - *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x22222222; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x33333333; - pxTopOfStack--; - - /* First stack an initial value for the critical section nesting. This - is initialised to zero as tasks are started with interrupts enabled. */ - *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* R0. */ - - /* Place an initial value for all the general purpose registers. */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) ulR2; /* R2 - small data area. */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x03; /* R3. */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x04; /* R4. */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) pvParameters;/* R5 contains the function call parameters. */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x06; /* R6. */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x07; /* R7. */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x08; /* R8. */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x09; /* R9. */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x0a; /* R10. */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x0b; /* R11. */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x0c; /* R12. */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) ulR13; /* R13 - small data read write area. */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* R14. */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x0f; /* R15. */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x10; /* R16. */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x11; /* R17. */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x12; /* R18. */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x13; /* R19. */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x14; /* R20. */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x15; /* R21. */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x16; /* R22. */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x17; /* R23. */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x18; /* R24. */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x19; /* R25. */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x1a; /* R26. */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x1b; /* R27. */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x1c; /* R28. */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x1d; /* R29. */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x1e; /* R30. */ - pxTopOfStack--; - - /* The MSR is stacked between R30 and R31. */ - *pxTopOfStack = portINITIAL_MSR_STATE; - pxTopOfStack--; - - *pxTopOfStack = ( portSTACK_TYPE ) 0x1f; /* R31. */ - pxTopOfStack--; - - /* Return a pointer to the top of the stack we have generated so this can - be stored in the task control block for the task. */ - return pxTopOfStack; -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xPortStartScheduler( void ) -{ -extern void ( __FreeRTOS_interrupt_Handler )( void ); -extern void ( vStartFirstTask )( void ); - - - /* Setup the FreeRTOS interrupt handler. Code copied from crt0.s. */ - asm volatile ( "la r6, r0, __FreeRTOS_interrupt_handler \n\t" \ - "sw r6, r1, r0 \n\t" \ - "lhu r7, r1, r0 \n\t" \ - "shi r7, r0, 0x12 \n\t" \ - "shi r6, r0, 0x16 " ); - - /* Setup the hardware to generate the tick. Interrupts are disabled when - this function is called. */ - prvSetupTimerInterrupt(); - - /* Allocate the stack to be used by the interrupt handler. */ - pulISRStack = ( unsigned portLONG * ) pvPortMalloc( configMINIMAL_STACK_SIZE * sizeof( portSTACK_TYPE ) ); - - /* Restore the context of the first task that is going to run. */ - if( pulISRStack != NULL ) - { - /* Fill the ISR stack with a known value to facilitate debugging. */ - memset( pulISRStack, portISR_STACK_FILL_VALUE, configMINIMAL_STACK_SIZE * sizeof( portSTACK_TYPE ) ); - pulISRStack += ( configMINIMAL_STACK_SIZE - 1 ); - - /* Kick off the first task. */ - vStartFirstTask(); - } - - /* Should not get here as the tasks are now running! */ - return pdFALSE; -} -/*-----------------------------------------------------------*/ - -void vPortEndScheduler( void ) -{ - /* Not implemented. */ -} -/*-----------------------------------------------------------*/ - -/* - * Manual context switch called by portYIELD or taskYIELD. - */ -void vPortYield( void ) -{ -extern void VPortYieldASM( void ); - - /* Perform the context switch in a critical section to assure it is - not interrupted by the tick ISR. It is not a problem to do this as - each task maintains it's own interrupt status. */ - portENTER_CRITICAL(); - /* Jump directly to the yield function to ensure there is no - compiler generated prologue code. */ - asm volatile ( "bralid r14, VPortYieldASM \n\t" \ - "or r0, r0, r0 \n\t" ); - portEXIT_CRITICAL(); -} -/*-----------------------------------------------------------*/ - -/* - * Hardware initialisation to generate the RTOS tick. - */ -static void prvSetupTimerInterrupt( void ) -{ -XTmrCtr xTimer; -const unsigned portLONG ulCounterValue = configCPU_CLOCK_HZ / configTICK_RATE_HZ; -unsigned portBASE_TYPE uxMask; - - /* The OPB timer1 is used to generate the tick. Use the provided library - functions to enable the timer and set the tick frequency. */ - XTmrCtr_mDisable( XPAR_OPB_TIMER_1_BASEADDR, XPAR_OPB_TIMER_1_DEVICE_ID ); - XTmrCtr_Initialize( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID ); - XTmrCtr_mSetLoadReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCounterValue ); - XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_LOAD_MASK | XTC_CSR_INT_OCCURED_MASK ); - - /* Set the timer interrupt enable bit while maintaining the other bit - states. */ - uxMask = XIntc_In32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ) ); - uxMask |= XPAR_OPB_TIMER_1_INTERRUPT_MASK; - XIntc_Out32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ), ( uxMask ) ); - - XTmrCtr_Start( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID ); - XTmrCtr_mSetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK | XTC_CSR_INT_OCCURED_MASK ); - XIntc_mAckIntr( XPAR_INTC_SINGLE_BASEADDR, 1 ); -} -/*-----------------------------------------------------------*/ - -/* - * The interrupt handler placed in the interrupt vector when the scheduler is - * started. The task context has already been saved when this is called. - * This handler determines the interrupt source and calls the relevant - * peripheral handler. - */ -void vTaskISRHandler( void ) -{ -static unsigned portLONG ulPending; - - /* Which interrupts are pending? */ - ulPending = XIntc_In32( ( XPAR_INTC_SINGLE_BASEADDR + XIN_IVR_OFFSET ) ); - - if( ulPending < XPAR_INTC_MAX_NUM_INTR_INPUTS ) - { - static XIntc_VectorTableEntry *pxTablePtr; - static XIntc_Config *pxConfig; - static unsigned portLONG ulInterruptMask; - - ulInterruptMask = ( unsigned portLONG ) 1 << ulPending; - - /* Get the configuration data using the device ID */ - pxConfig = &XIntc_ConfigTable[ ( unsigned portLONG ) XPAR_INTC_SINGLE_DEVICE_ID ]; - - pxTablePtr = &( pxConfig->HandlerTable[ ulPending ] ); - if( pxConfig->AckBeforeService & ( ulInterruptMask ) ) - { - XIntc_mAckIntr( pxConfig->BaseAddress, ulInterruptMask ); - pxTablePtr->Handler( pxTablePtr->CallBackRef ); - } - else - { - pxTablePtr->Handler( pxTablePtr->CallBackRef ); - XIntc_mAckIntr( pxConfig->BaseAddress, ulInterruptMask ); - } - } -} -/*-----------------------------------------------------------*/ - -/* - * Handler for the timer interrupt. - */ -void vTickISR( void *pvBaseAddress ) -{ -unsigned portLONG ulCSR; - - /* Increment the RTOS tick - this might cause a task to unblock. */ - vTaskIncrementTick(); - - /* Clear the timer interrupt */ - ulCSR = XTmrCtr_mGetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, 0); - XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCSR ); - - /* If we are using the preemptive scheduler then we also need to determine - if this tick should cause a context switch. */ - #if configUSE_PREEMPTION == 1 - vTaskSwitchContext(); - #endif -} -/*-----------------------------------------------------------*/ - - - - - diff --git a/Source/portable/GCC/MicroBlaze/portasm.s b/Source/portable/GCC/MicroBlaze/portasm.s deleted file mode 100644 index b818daa9e..000000000 --- a/Source/portable/GCC/MicroBlaze/portasm.s +++ /dev/null @@ -1,171 +0,0 @@ - .extern pxCurrentTCB - .extern vTaskISRHandler - .extern vTaskSwitchContext - .extern uxCriticalNesting - .extern pulISRStack - - .global __FreeRTOS_interrupt_handler - .global VPortYieldASM - .global vStartFirstTask - - -.macro portSAVE_CONTEXT - /* Make room for the context on the stack. */ - addik r1, r1, -132 - /* Save r31 so it can then be used. */ - swi r31, r1, 4 - /* Copy the msr into r31 - this is stacked later. */ - mfs r31, rmsr - /* Stack general registers. */ - swi r30, r1, 12 - swi r29, r1, 16 - swi r28, r1, 20 - swi r27, r1, 24 - swi r26, r1, 28 - swi r25, r1, 32 - swi r24, r1, 36 - swi r23, r1, 40 - swi r22, r1, 44 - swi r21, r1, 48 - swi r20, r1, 52 - swi r19, r1, 56 - swi r18, r1, 60 - swi r17, r1, 64 - swi r16, r1, 68 - swi r15, r1, 72 - swi r13, r1, 80 - swi r12, r1, 84 - swi r11, r1, 88 - swi r10, r1, 92 - swi r9, r1, 96 - swi r8, r1, 100 - swi r7, r1, 104 - swi r6, r1, 108 - swi r5, r1, 112 - swi r4, r1, 116 - swi r3, r1, 120 - swi r2, r1, 124 - /* Stack the critical section nesting value. */ - lwi r3, r0, uxCriticalNesting - swi r3, r1, 128 - /* Save the top of stack value to the TCB. */ - lwi r3, r0, pxCurrentTCB - sw r1, r0, r3 - - .endm - -.macro portRESTORE_CONTEXT - /* Load the top of stack value from the TCB. */ - lwi r3, r0, pxCurrentTCB - lw r1, r0, r3 - /* Restore the general registers. */ - lwi r31, r1, 4 - lwi r30, r1, 12 - lwi r29, r1, 16 - lwi r28, r1, 20 - lwi r27, r1, 24 - lwi r26, r1, 28 - lwi r25, r1, 32 - lwi r24, r1, 36 - lwi r23, r1, 40 - lwi r22, r1, 44 - lwi r21, r1, 48 - lwi r20, r1, 52 - lwi r19, r1, 56 - lwi r18, r1, 60 - lwi r17, r1, 64 - lwi r16, r1, 68 - lwi r15, r1, 72 - lwi r14, r1, 76 - lwi r13, r1, 80 - lwi r12, r1, 84 - lwi r11, r1, 88 - lwi r10, r1, 92 - lwi r9, r1, 96 - lwi r8, r1, 100 - lwi r7, r1, 104 - lwi r6, r1, 108 - lwi r5, r1, 112 - lwi r4, r1, 116 - lwi r2, r1, 124 - - /* Load the critical nesting value. */ - lwi r3, r1, 128 - swi r3, r0, uxCriticalNesting - - /* Obtain the MSR value from the stack. */ - lwi r3, r1, 8 - - /* Are interrupts enabled in the MSR? If so return using an return from - interrupt instruction to ensure interrupts are enabled only once the task - is running again. */ - andi r3, r3, 2 - beqid r3, 36 - or r0, r0, r0 - - /* Reload the rmsr from the stack, clear the enable interrupt bit in the - value before saving back to rmsr register, then return enabling interrupts - as we return. */ - lwi r3, r1, 8 - andi r3, r3, ~2 - mts rmsr, r3 - lwi r3, r1, 120 - addik r1, r1, 132 - rtid r14, 0 - or r0, r0, r0 - - /* Reload the rmsr from the stack, place it in the rmsr register, and - return without enabling interrupts. */ - lwi r3, r1, 8 - mts rmsr, r3 - lwi r3, r1, 120 - addik r1, r1, 132 - rtsd r14, 0 - or r0, r0, r0 - - .endm - - .text - .align 2 - - -__FreeRTOS_interrupt_handler: - portSAVE_CONTEXT - /* Entered via an interrupt so interrupts must be enabled in msr. */ - ori r31, r31, 2 - /* Stack msr. */ - swi r31, r1, 8 - /* Stack the return address. As we entered via an interrupt we do - not need to modify the return address prior to stacking. */ - swi r14, r1, 76 - /* Now switch to use the ISR stack. */ - lwi r3, r0, pulISRStack - add r1, r3, r0 - bralid r15, vTaskISRHandler - or r0, r0, r0 - portRESTORE_CONTEXT - - -VPortYieldASM: - portSAVE_CONTEXT - /* Stack msr. */ - swi r31, r1, 8 - /* Modify the return address so we return to the instruction after the - exception. */ - addi r14, r14, 8 - swi r14, r1, 76 - /* Now switch to use the ISR stack. */ - lwi r3, r0, pulISRStack - add r1, r3, r0 - bralid r15, vTaskSwitchContext - or r0, r0, r0 - portRESTORE_CONTEXT - -vStartFirstTask: - portRESTORE_CONTEXT - - - - - - diff --git a/Source/portable/GCC/MicroBlaze/portmacro.h b/Source/portable/GCC/MicroBlaze/portmacro.h deleted file mode 100644 index 1b43d3f07..000000000 --- a/Source/portable/GCC/MicroBlaze/portmacro.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -/*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the - * given hardware and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - -/* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE unsigned portLONG -#define portBASE_TYPE portLONG - -#if( configUSE_16_BIT_TICKS == 1 ) - typedef unsigned portSHORT portTickType; - #define portMAX_DELAY ( portTickType ) 0xffff -#else - typedef unsigned portLONG portTickType; - #define portMAX_DELAY ( portTickType ) 0xffffffff -#endif -/*-----------------------------------------------------------*/ - -/* Interrupt control macros. */ -void microblaze_disable_interrupts( void ); -void microblaze_enable_interrupts( void ); -#define portDISABLE_INTERRUPTS() microblaze_disable_interrupts() -#define portENABLE_INTERRUPTS() microblaze_enable_interrupts() -/*-----------------------------------------------------------*/ - -/* Critical section macros. */ -void vPortEnterCritical( void ); -void vPortExitCritical( void ); -#define portENTER_CRITICAL() { \ - extern unsigned portBASE_TYPE uxCriticalNesting; \ - microblaze_disable_interrupts(); \ - uxCriticalNesting++; \ - } - -#define portEXIT_CRITICAL() { \ - extern unsigned portBASE_TYPE uxCriticalNesting; \ - /* Interrupts are disabled, so we can */ \ - /* access the variable directly. */ \ - uxCriticalNesting--; \ - if( uxCriticalNesting == 0 ) \ - { \ - /* The nesting has unwound and we \ - can enable interrupts again. */ \ - portENABLE_INTERRUPTS(); \ - } \ - } - -/*-----------------------------------------------------------*/ - -/* Task utilities. */ -void vPortYield( void ); -#define portYIELD() vPortYield() - -void vTaskSwitchContext(); -#define portYIELD_FROM_ISR() vTaskSwitchContext() -/*-----------------------------------------------------------*/ - -/* Hardware specifics. */ -#define portBYTE_ALIGNMENT 4 -#define portSTACK_GROWTH ( -1 ) -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) -#define portNOP() asm volatile ( "NOP" ) -/*-----------------------------------------------------------*/ - -/* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) - -#endif /* PORTMACRO_H */ - diff --git a/Source/portable/GCC/STR75x/port.c b/Source/portable/GCC/STR75x/port.c deleted file mode 100644 index b1ab235a1..000000000 --- a/Source/portable/GCC/STR75x/port.c +++ /dev/null @@ -1,198 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the ST STR75x ARM7 - * port. - *----------------------------------------------------------*/ - -/* Library includes. */ -#include "75x_tb.h" -#include "75x_eic.h" - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Constants required to setup the initial stack. */ -#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ -#define portTHUMB_MODE_BIT ( ( portSTACK_TYPE ) 0x20 ) -#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 ) - -/* Constants required to handle critical sections. */ -#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 ) - -/* Prescale used on the timer clock when calculating the tick period. */ -#define portPRESCALE 20 - - -/*-----------------------------------------------------------*/ - -/* Setup the TB to generate the tick interrupts. */ -static void prvSetupTimerInterrupt( void ); - -/*-----------------------------------------------------------*/ - -/* - * Initialise the stack of a task to look exactly as if a call to - * portSAVE_CONTEXT had been called. - * - * See header file for description. - */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) -{ -portSTACK_TYPE *pxOriginalTOS; - - pxOriginalTOS = pxTopOfStack; - - /* Setup the initial stack of the task. The stack is set exactly as - expected by the portRESTORE_CONTEXT() macro. */ - - /* First on the stack is the return address - which in this case is the - start of the task. The offset is added to make the return address appear - as it would within an IRQ ISR. */ - *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; - pxTopOfStack--; - - *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */ - pxTopOfStack--; - - /* When the task starts is will expect to find the function parameter in - R0. */ - *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ - pxTopOfStack--; - - /* The status register is set for system mode, with interrupts enabled. */ - *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR; - - #ifdef THUMB_INTERWORK - { - /* We want the task to start in thumb mode. */ - *pxTopOfStack |= portTHUMB_MODE_BIT; - } - #endif - - pxTopOfStack--; - - /* Interrupt flags cannot always be stored on the stack and will - instead be stored in a variable, which is then saved as part of the - tasks context. */ - *pxTopOfStack = portNO_CRITICAL_NESTING; - - return pxTopOfStack; -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xPortStartScheduler( void ) -{ -extern void vPortISRStartFirstTask( void ); - - /* Start the timer that generates the tick ISR. Interrupts are disabled - here already. */ - prvSetupTimerInterrupt(); - - /* Start the first task. */ - vPortISRStartFirstTask(); - - /* Should not get here! */ - return 0; -} -/*-----------------------------------------------------------*/ - -void vPortEndScheduler( void ) -{ - /* It is unlikely that the ARM port will require this function as there - is nothing to return to. */ -} -/*-----------------------------------------------------------*/ - -static void prvSetupTimerInterrupt( void ) -{ -EIC_IRQInitTypeDef EIC_IRQInitStructure; -TB_InitTypeDef TB_InitStructure; - - /* Setup the EIC for the TB. */ - EIC_IRQInitStructure.EIC_IRQChannelCmd = ENABLE; - EIC_IRQInitStructure.EIC_IRQChannel = TB_IRQChannel; - EIC_IRQInitStructure.EIC_IRQChannelPriority = 1; - EIC_IRQInit(&EIC_IRQInitStructure); - - /* Setup the TB for the generation of the tick interrupt. */ - TB_InitStructure.TB_Mode = TB_Mode_Timing; - TB_InitStructure.TB_CounterMode = TB_CounterMode_Down; - TB_InitStructure.TB_Prescaler = portPRESCALE; - TB_InitStructure.TB_AutoReload = ( ( configCPU_CLOCK_HZ / ( portPRESCALE + 1 ) ) / configTICK_RATE_HZ ) + 1; - TB_Init(&TB_InitStructure); - - /* Enable TB Update interrupt */ - TB_ITConfig(TB_IT_Update, ENABLE); - - /* Clear TB Update interrupt pending bit */ - TB_ClearITPendingBit(TB_IT_Update); - - /* Enable TB */ - TB_Cmd(ENABLE); -} -/*-----------------------------------------------------------*/ - - - - - - - diff --git a/Source/portable/GCC/STR75x/portISR.c b/Source/portable/GCC/STR75x/portISR.c deleted file mode 100644 index dc581f9ca..000000000 --- a/Source/portable/GCC/STR75x/portISR.c +++ /dev/null @@ -1,188 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/*----------------------------------------------------------- - * Components that can be compiled to either ARM or THUMB mode are - * contained in port.c The ISR routines, which can only be compiled - * to ARM mode, are contained in this file. - *----------------------------------------------------------*/ - -/* -*/ - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Constants required to handle critical sections. */ -#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 ) - -volatile unsigned portLONG ulCriticalNesting = 9999UL; - -/*-----------------------------------------------------------*/ - -/* - * The scheduler can only be started from ARM mode, hence the inclusion of this - * function here. - */ -void vPortISRStartFirstTask( void ); -/*-----------------------------------------------------------*/ - -void vPortISRStartFirstTask( void ) -{ - /* Simply start the scheduler. This is included here as it can only be - called from ARM mode. */ - asm volatile ( \ - "LDR R0, =pxCurrentTCB \n\t" \ - "LDR R0, [R0] \n\t" \ - "LDR LR, [R0] \n\t" \ - \ - /* The critical nesting depth is the first item on the stack. */ \ - /* Load it into the ulCriticalNesting variable. */ \ - "LDR R0, =ulCriticalNesting \n\t" \ - "LDMFD LR!, {R1} \n\t" \ - "STR R1, [R0] \n\t" \ - \ - /* Get the SPSR from the stack. */ \ - "LDMFD LR!, {R0} \n\t" \ - "MSR SPSR, R0 \n\t" \ - \ - /* Restore all system mode registers for the task. */ \ - "LDMFD LR, {R0-R14}^ \n\t" \ - "NOP \n\t" \ - \ - /* Restore the return address. */ \ - "LDR LR, [LR, #+60] \n\t" \ - \ - /* And return - correcting the offset in the LR to obtain the */ \ - /* correct address. */ \ - "SUBS PC, LR, #4 \n\t" \ - ); -} -/*-----------------------------------------------------------*/ - -void vPortTickISR( void ) -{ - /* Increment the RTOS tick count, then look for the highest priority - task that is ready to run. */ - vTaskIncrementTick(); - - #if configUSE_PREEMPTION == 1 - vTaskSwitchContext(); - #endif - - /* Ready for the next interrupt. */ - TB_ClearITPendingBit( TB_IT_Update ); -} - -/*-----------------------------------------------------------*/ - -/* - * The interrupt management utilities can only be called from ARM mode. When - * THUMB_INTERWORK is defined the utilities are defined as functions here to - * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then - * the utilities are defined as macros in portmacro.h - as per other ports. - */ -#ifdef THUMB_INTERWORK - - void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); - void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); - - void vPortDisableInterruptsFromThumb( void ) - { - asm volatile ( - "STMDB SP!, {R0} \n\t" /* Push R0. */ - "MRS R0, CPSR \n\t" /* Get CPSR. */ - "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ - "LDMIA SP!, {R0} \n\t" /* Pop R0. */ - "BX R14" ); /* Return back to thumb. */ - } - - void vPortEnableInterruptsFromThumb( void ) - { - asm volatile ( - "STMDB SP!, {R0} \n\t" /* Push R0. */ - "MRS R0, CPSR \n\t" /* Get CPSR. */ - "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ - "LDMIA SP!, {R0} \n\t" /* Pop R0. */ - "BX R14" ); /* Return back to thumb. */ - } - -#endif /* THUMB_INTERWORK */ -/*-----------------------------------------------------------*/ - -void vPortEnterCritical( void ) -{ - /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ - asm volatile ( - "STMDB SP!, {R0} \n\t" /* Push R0. */ - "MRS R0, CPSR \n\t" /* Get CPSR. */ - "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ - "LDMIA SP!, {R0}" ); /* Pop R0. */ - - /* Now interrupts are disabled ulCriticalNesting can be accessed - directly. Increment ulCriticalNesting to keep a count of how many times - portENTER_CRITICAL() has been called. */ - ulCriticalNesting++; -} -/*-----------------------------------------------------------*/ - -void vPortExitCritical( void ) -{ - if( ulCriticalNesting > portNO_CRITICAL_NESTING ) - { - /* Decrement the nesting count as we are leaving a critical section. */ - ulCriticalNesting--; - - /* If the nesting level has reached zero then interrupts should be - re-enabled. */ - if( ulCriticalNesting == portNO_CRITICAL_NESTING ) - { - /* Enable interrupts as per portEXIT_CRITICAL(). */ - asm volatile ( - "STMDB SP!, {R0} \n\t" /* Push R0. */ - "MRS R0, CPSR \n\t" /* Get CPSR. */ - "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ - "LDMIA SP!, {R0}" ); /* Pop R0. */ - } - } -} - - - - - diff --git a/Source/portable/GCC/STR75x/portmacro.h b/Source/portable/GCC/STR75x/portmacro.h deleted file mode 100644 index fb3979aa4..000000000 --- a/Source/portable/GCC/STR75x/portmacro.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -/*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the - * given hardware and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - -/* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE unsigned portLONG -#define portBASE_TYPE portLONG - -#if( configUSE_16_BIT_TICKS == 1 ) - typedef unsigned portSHORT portTickType; - #define portMAX_DELAY ( portTickType ) 0xffff -#else - typedef unsigned portLONG portTickType; - #define portMAX_DELAY ( portTickType ) 0xffffffff -#endif -/*-----------------------------------------------------------*/ - -/* Hardware specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 4 -#define portYIELD() asm volatile ( "SWI 0" ) -#define portNOP() asm volatile ( "NOP" ) -/*-----------------------------------------------------------*/ - -/* Critical section handling. */ -/* - * The interrupt management utilities can only be called from ARM mode. When - * THUMB_INTERWORK is defined the utilities are defined as functions in - * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not - * defined then the utilities are defined as macros here - as per other ports. - */ - -#ifdef THUMB_INTERWORK - - extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); - extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); - - #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb() - #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb() - -#else - - #define portDISABLE_INTERRUPTS() \ - asm volatile ( \ - "STMDB SP!, {R0} \n\t" /* Push R0. */ \ - "MRS R0, CPSR \n\t" /* Get CPSR. */ \ - "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ - "LDMIA SP!, {R0} " ) /* Pop R0. */ - - #define portENABLE_INTERRUPTS() \ - asm volatile ( \ - "STMDB SP!, {R0} \n\t" /* Push R0. */ \ - "MRS R0, CPSR \n\t" /* Get CPSR. */ \ - "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \ - "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ - "LDMIA SP!, {R0} " ) /* Pop R0. */ - -#endif /* THUMB_INTERWORK */ - -extern void vPortEnterCritical( void ); -extern void vPortExitCritical( void ); - -#define portENTER_CRITICAL() vPortEnterCritical(); -#define portEXIT_CRITICAL() vPortExitCritical(); -/*-----------------------------------------------------------*/ - -/* Task utilities. */ -#define portEND_SWITCHING_ISR( xSwitchRequired ) \ -{ \ -extern void vTaskSwitchContext( void ); \ - \ - if( xSwitchRequired ) \ - { \ - vTaskSwitchContext(); \ - } \ -} -/*-----------------------------------------------------------*/ - -/* Compiler specifics */ -#define inline - -/* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) - -#endif /* PORTMACRO_H */ - - diff --git a/Source/portable/IAR/ARM_CM3/port.c b/Source/portable/IAR/ARM_CM3/port.c deleted file mode 100644 index 3b272ac0f..000000000 --- a/Source/portable/IAR/ARM_CM3/port.c +++ /dev/null @@ -1,170 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the ARM CM3 port. - *----------------------------------------------------------*/ - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Constants required to manipulate the NVIC. */ -#define portNVIC_SYSTICK_CTRL ( ( volatile unsigned portLONG *) 0xe000e010 ) -#define portNVIC_SYSTICK_LOAD ( ( volatile unsigned portLONG *) 0xe000e014 ) -#define portNVIC_INT_CTRL ( ( volatile unsigned portLONG *) 0xe000ed04 ) -#define portNVIC_SYSPRI2 ( ( volatile unsigned portLONG *) 0xe000ed20 ) -#define portNVIC_SYSPRI1 ( ( volatile unsigned portLONG *) 0xe000ed1c ) -#define portNVIC_SYSTICK_CLK 0x00000004 -#define portNVIC_SYSTICK_INT 0x00000002 -#define portNVIC_SYSTICK_ENABLE 0x00000001 -#define portNVIC_PENDSVSET 0x10000000 -#define portNVIC_PENDSV_PRI 0x00ff0000 -#define portNVIC_SVCALL_PRI 0xff000000 -#define portNVIC_SYSTICK_PRI 0xff000000 - -/* Constants required to set up the initial stack. */ -#define portINITIAL_XPSR ( 0x01000000 ) - -/* Each task maintains its own interrupt status in the critical nesting -variable. */ -unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa; - -/* - * Setup the timer to generate the tick interrupts. - */ -static void prvSetupTimerInterrupt( void ); - -/* - * Set the MSP/PSP to a known value. - */ -extern void vSetMSP( unsigned long ulValue ); -extern void vSetPSP( unsigned long ulValue ); - -/*-----------------------------------------------------------*/ - -/* - * See header file for description. - */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) -{ - /* Simulate the stack frame as it would be created by a context switch - interrupt. */ - *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* PC */ - pxTopOfStack--; - *pxTopOfStack = 0xfffffffd; /* LR */ - pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ - *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ - pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ - *pxTopOfStack = 0x00000000; /* uxCriticalNesting. */ - - return pxTopOfStack; -} -/*-----------------------------------------------------------*/ - -/* - * See header file for description. - */ -portBASE_TYPE xPortStartScheduler( void ) -{ - /* Make PendSV, CallSV and SysTick the lowest priority interrupts. */ - *(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI; - *(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI; - - /* Start the timer that generates the tick ISR. Interrupts are disabled - here already. */ - prvSetupTimerInterrupt(); - - /* Start the first task. */ - vSetPSP( 0 ); - vSetMSP( *((unsigned portLONG *) 0 ) ); - *(portNVIC_INT_CTRL) |= portNVIC_PENDSVSET; - - /* Enable interrupts */ - portENABLE_INTERRUPTS(); - - /* Should not get here! */ - return 0; -} -/*-----------------------------------------------------------*/ - -void vPortEndScheduler( void ) -{ - /* It is unlikely that the CM3 port will require this function as there - is nothing to return to. */ -} -/*-----------------------------------------------------------*/ - -void vPortYieldFromISR( void ) -{ - /* Set a PendSV to request a context switch. */ - *(portNVIC_INT_CTRL) |= portNVIC_PENDSVSET; - - /* This function is also called in response to a Yield(), so we want - the yield to occur immediately. */ - portENABLE_INTERRUPTS(); -} -/*-----------------------------------------------------------*/ - -void vPortEnterCritical( void ) -{ - portDISABLE_INTERRUPTS(); - uxCriticalNesting++; -} -/*-----------------------------------------------------------*/ - -void vPortExitCritical( void ) -{ - uxCriticalNesting--; - if( uxCriticalNesting == 0 ) - { - portENABLE_INTERRUPTS(); - } -} -/*-----------------------------------------------------------*/ - - -/* - * Setup the systick timer to generate the tick interrupts at the required - * frequency. - */ -void prvSetupTimerInterrupt( void ) -{ - /* Configure SysTick to interrupt at the requested rate. */ - *(portNVIC_SYSTICK_LOAD) = configCPU_CLOCK_HZ / configTICK_RATE_HZ; - *(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE; -} - - diff --git a/Source/portable/IAR/ARM_CM3/portasm.s b/Source/portable/IAR/ARM_CM3/portasm.s deleted file mode 100644 index fb212e958..000000000 --- a/Source/portable/IAR/ARM_CM3/portasm.s +++ /dev/null @@ -1,129 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ -#include - - RSEG ICODE:CODE - - EXTERN vPortYieldFromISR - EXTERN vTaskSwitchContext - EXTERN vTaskIncrementTick - EXTERN uxCriticalNesting - EXTERN pxCurrentTCB - - PUBLIC vSetPSP - PUBLIC vSetMSP - PUBLIC xPortPendSVHandler - PUBLIC xPortSysTickHandler - - -vSetPSP: - msr psp, r0 - bx lr -/*-----------------------------------------------------------*/ - -vSetMSP - msr msp, r0 - bx lr -/*-----------------------------------------------------------*/ - -xPortPendSVHandler: - mrs r0, psp - cbz r0, no_save - /* Save the context into the TCB. */ - sub r0, r0, #0x20 - stm r0, {r4-r11} - nop - sub r0, r0, #0x04 - ldr r1, =uxCriticalNesting - ldr r1, [r1] - str R1, [r0, #0x00] - ldr r1, =pxCurrentTCB - ldr r1, [r1] - str r0, [r1] -no_save: - ldr r0, =vTaskSwitchContext - push {r14} - cpsid i - blx r0 - cpsie i - pop {r14} - - /* Restore the context. */ - ldr r1, =pxCurrentTCB - ldr r1, [r1] - ldr r0, [r1] - ldm r0, {r1, r4-r11} - nop - ldr r2, =uxCriticalNesting - str r1, [r2] - add r0, r0, #0x24 - msr psp, r0 - orr r14, r14, #0xd - /* Exit with interrupts in the state required by the task. */ - cbnz r1, sv_disable_interrupts - bx r14 - -sv_disable_interrupts: - cpsid i - bx r14 - -/*-----------------------------------------------------------*/ - -xPortSysTickHandler: - /* Call the scheduler tick function. */ - ldr r0, =vTaskIncrementTick - push {r14} - cpsid i - blx r0 - cpsie i - pop {r14} - - /* If using preemption, also force a context switch. */ - #if configUSE_PREEMPTION == 1 - push {r14} - ldr r0, =vPortYieldFromISR - blx r0 - pop {r14} - #endif - - /* Exit with interrupts in the correct state. */ - ldr r2, =uxCriticalNesting - ldr r2, [r2] - cbnz r2, tick_disable_interrupts - bx r14 - -tick_disable_interrupts: - cpsid i - bx r14 - - END -/*-----------------------------------------------------------*/ diff --git a/Source/portable/IAR/ARM_CM3/portmacro.h b/Source/portable/IAR/ARM_CM3/portmacro.h deleted file mode 100644 index b508ad9b6..000000000 --- a/Source/portable/IAR/ARM_CM3/portmacro.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -/*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the - * given hardware and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - -/* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE unsigned portLONG -#define portBASE_TYPE long - -#if( configUSE_16_BIT_TICKS == 1 ) - typedef unsigned portSHORT portTickType; - #define portMAX_DELAY ( portTickType ) 0xffff -#else - typedef unsigned portLONG portTickType; - #define portMAX_DELAY ( portTickType ) 0xffffffff -#endif -/*-----------------------------------------------------------*/ - -/* Architecture specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 4 -/*-----------------------------------------------------------*/ - - -/* Scheduler utilities. */ -extern void vPortYieldFromISR( void ); - -#define portYIELD() vPortYieldFromISR() - -#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vPortYieldFromISR() -/*-----------------------------------------------------------*/ - - -/* Critical section management. */ - -extern void vPortEnableInterrupts( void ); -extern void vPortEnterCritical( void ); -extern void vPortExitCritical( void ); - -#define portDISABLE_INTERRUPTS() __asm ( "cpsid i" ) -#define portENABLE_INTERRUPTS() __asm ( "cpsie i" ) -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() -/*-----------------------------------------------------------*/ - -/* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) - -#define inline -#define portNOP() - -#endif /* PORTMACRO_H */ - diff --git a/Source/portable/IAR/ATMega323/port.c b/Source/portable/IAR/ATMega323/port.c deleted file mode 100644 index 9b423d5a5..000000000 --- a/Source/portable/IAR/ATMega323/port.c +++ /dev/null @@ -1,345 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#include - -#include "FreeRTOS.h" -#include "task.h" - -/*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the AVR/IAR port. - *----------------------------------------------------------*/ - -/* Start tasks with interrupts enables. */ -#define portFLAGS_INT_ENABLED ( ( portSTACK_TYPE ) 0x80 ) - -/* Hardware constants for timer 1. */ -#define portCLEAR_COUNTER_ON_MATCH ( ( unsigned portCHAR ) 0x08 ) -#define portPRESCALE_64 ( ( unsigned portCHAR ) 0x03 ) -#define portCLOCK_PRESCALER ( ( unsigned portLONG ) 64 ) -#define portCOMPARE_MATCH_A_INTERRUPT_ENABLE ( ( unsigned portCHAR ) 0x10 ) - -/* The number of bytes used on the hardware stack by the task start address. */ -#define portBYTES_USED_BY_RETURN_ADDRESS ( 2 ) -/*-----------------------------------------------------------*/ - -/* Stores the critical section nesting. This must not be initialised to 0. -It will be initialised when a task starts. */ -#define portNO_CRITICAL_NESTING ( ( unsigned portBASE_TYPE ) 0 ) -unsigned portBASE_TYPE uxCriticalNesting = 0x50; - - -/* - * Perform hardware setup to enable ticks from timer 1, compare match A. - */ -static void prvSetupTimerInterrupt( void ); - -/* - * The IAR compiler does not have full support for inline assembler, so - * these are defined in the portmacro assembler file. - */ -extern void vPortYieldFromTick( void ); -extern void vPortStart( void ); - -/*-----------------------------------------------------------*/ - -/* - * See header file for description. - */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) -{ -unsigned portSHORT usAddress; -portSTACK_TYPE *pxTopOfHardwareStack; - - /* Place a few bytes of known values on the bottom of the stack. - This is just useful for debugging. */ - - *pxTopOfStack = 0x11; - pxTopOfStack--; - *pxTopOfStack = 0x22; - pxTopOfStack--; - *pxTopOfStack = 0x33; - pxTopOfStack--; - - /* Remember where the top of the hardware stack is - this is required - below. */ - pxTopOfHardwareStack = pxTopOfStack; - - - /* Simulate how the stack would look after a call to vPortYield(). */ - - /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */ - - - - /* The IAR compiler requires two stacks per task. First there is the - hardware call stack which uses the AVR stack pointer. Second there is the - software stack (local variables, parameter passing, etc.) which uses the - AVR Y register. - - This function places both stacks within the memory block passed in as the - first parameter. The hardware stack is placed at the bottom of the memory - block. A gap is then left for the hardware stack to grow. Next the software - stack is placed. The amount of space between the software and hardware - stacks is defined by configCALL_STACK_SIZE. - - - - The first part of the stack is the hardware stack. Place the start - address of the task on the hardware stack. */ - usAddress = ( unsigned portSHORT ) pxCode; - *pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned portSHORT ) 0x00ff ); - pxTopOfStack--; - - usAddress >>= 8; - *pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned portSHORT ) 0x00ff ); - pxTopOfStack--; - - - /* Leave enough space for the hardware stack before starting the software - stack. The '- 2' is because we have already used two spaces for the - address of the start of the task. */ - pxTopOfStack -= ( configCALL_STACK_SIZE - 2 ); - - - - /* Next simulate the stack as if after a call to portSAVE_CONTEXT(). - portSAVE_CONTEXT places the flags on the stack immediately after r0 - to ensure the interrupts get disabled as soon as possible, and so ensuring - the stack use is minimal should a context switch interrupt occur. */ - *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* R0 */ - pxTopOfStack--; - *pxTopOfStack = portFLAGS_INT_ENABLED; - pxTopOfStack--; - - /* Next place the address of the hardware stack. This is required so - the AVR stack pointer can be restored to point to the hardware stack. */ - pxTopOfHardwareStack -= portBYTES_USED_BY_RETURN_ADDRESS; - usAddress = ( unsigned portSHORT ) pxTopOfHardwareStack; - - /* SPL */ - *pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned portSHORT ) 0x00ff ); - pxTopOfStack--; - - /* SPH */ - usAddress >>= 8; - *pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned portSHORT ) 0x00ff ); - pxTopOfStack--; - - - - - /* Now the remaining registers. */ - *pxTopOfStack = ( portSTACK_TYPE ) 0x01; /* R1 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x02; /* R2 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x03; /* R3 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x04; /* R4 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x05; /* R5 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x06; /* R6 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x07; /* R7 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x08; /* R8 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x09; /* R9 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x10; /* R10 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x11; /* R11 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x12; /* R12 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x13; /* R13 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x14; /* R14 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x15; /* R15 */ - pxTopOfStack--; - - /* Place the parameter on the stack in the expected location. */ - usAddress = ( unsigned portSHORT ) pvParameters; - *pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned portSHORT ) 0x00ff ); - pxTopOfStack--; - - usAddress >>= 8; - *pxTopOfStack = ( portSTACK_TYPE ) ( usAddress & ( unsigned portSHORT ) 0x00ff ); - pxTopOfStack--; - - *pxTopOfStack = ( portSTACK_TYPE ) 0x18; /* R18 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x19; /* R19 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x20; /* R20 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x21; /* R21 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x22; /* R22 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x23; /* R23 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x24; /* R24 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x25; /* R25 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x26; /* R26 X */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x27; /* R27 */ - pxTopOfStack--; - - /* The Y register is not stored as it is used as the software stack and - gets saved into the task control block. */ - - *pxTopOfStack = ( portSTACK_TYPE ) 0x30; /* R30 Z */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x031; /* R31 */ - - pxTopOfStack--; - *pxTopOfStack = portNO_CRITICAL_NESTING; /* Critical nesting is zero when the task starts. */ - - /*lint +e950 +e611 +e923 */ - - return pxTopOfStack; -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xPortStartScheduler( void ) -{ - /* Setup the hardware to generate the tick. */ - prvSetupTimerInterrupt(); - - /* Restore the context of the first task that is going to run. - Normally we would just call portRESTORE_CONTEXT() here, but as the IAR - compiler does not fully support inline assembler we have to make a call.*/ - vPortStart(); - - - /* Should not get here! */ - return pdTRUE; -} -/*-----------------------------------------------------------*/ - -void vPortEndScheduler( void ) -{ - /* It is unlikely that the AVR port will get stopped. If required simply - disable the tick interrupt here. */ -} -/*-----------------------------------------------------------*/ - -/* - * Setup timer 1 compare match A to generate a tick interrupt. - */ -static void prvSetupTimerInterrupt( void ) -{ -unsigned portLONG ulCompareMatch; -unsigned portCHAR ucHighByte, ucLowByte; - - /* Using 16bit timer 1 to generate the tick. Correct fuses must be - selected for the configCPU_CLOCK_HZ clock. */ - - ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ; - - /* We only have 16 bits so have to scale to get our required tick rate. */ - ulCompareMatch /= portCLOCK_PRESCALER; - - /* Adjust for correct value. */ - ulCompareMatch -= ( unsigned portLONG ) 1; - - /* Setup compare match value for compare match A. Interrupts are disabled - before this is called so we need not worry here. */ - ucLowByte = ( unsigned portCHAR ) ( ulCompareMatch & ( unsigned portLONG ) 0xff ); - ulCompareMatch >>= 8; - ucHighByte = ( unsigned portCHAR ) ( ulCompareMatch & ( unsigned portLONG ) 0xff ); - OCR1AH = ucHighByte; - OCR1AL = ucLowByte; - - /* Setup clock source and compare match behaviour. */ - ucLowByte = portCLEAR_COUNTER_ON_MATCH | portPRESCALE_64; - TCCR1B = ucLowByte; - - /* Enable the interrupt - this is okay as interrupt are currently globally - disabled. */ - TIMSK |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE; -} -/*-----------------------------------------------------------*/ - -#if configUSE_PREEMPTION == 1 - - /* - * Tick ISR for preemptive scheduler. We can use a __task attribute as - * the context is saved at the start of vPortYieldFromTick(). The tick - * count is incremented after the context is saved. - */ - __task void SIG_OUTPUT_COMPARE1A( void ) - { - vPortYieldFromTick(); - asm( "reti" ); - } - -#else - - /* - * Tick ISR for the cooperative scheduler. All this does is increment the - * tick count. We don't need to switch context, this can only be done by - * manual calls to taskYIELD(); - * - * THE INTERRUPT VECTOR IS POPULATED IN portmacro.s90. DO NOT INSTALL - * IT HERE USING THE USUAL PRAGMA. - */ - __interrupt void SIG_OUTPUT_COMPARE1A( void ) - { - vTaskIncrementTick(); - } -#endif -/*-----------------------------------------------------------*/ - -void vPortEnterCritical( void ) -{ - portDISABLE_INTERRUPTS(); - uxCriticalNesting++; -} -/*-----------------------------------------------------------*/ - -void vPortExitCritical( void ) -{ - uxCriticalNesting--; - if( uxCriticalNesting == portNO_CRITICAL_NESTING ) - { - portENABLE_INTERRUPTS(); - } -} - - diff --git a/Source/portable/IAR/ATMega323/portmacro.h b/Source/portable/IAR/ATMega323/portmacro.h deleted file mode 100644 index 89a29a596..000000000 --- a/Source/portable/IAR/ATMega323/portmacro.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V1.2.3 - - + portCPU_CLOSK_HZ definition changed to 8MHz base 10, previously it - base 16. -*/ - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -/*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the - * given hardware and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - -/* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT int -#define portSTACK_TYPE unsigned portCHAR -#define portBASE_TYPE portCHAR - -#if( configUSE_16_BIT_TICKS == 1 ) - typedef unsigned portSHORT portTickType; - #define portMAX_DELAY ( portTickType ) 0xffff -#else - typedef unsigned portLONG portTickType; - #define portMAX_DELAY ( portTickType ) 0xffffffff -#endif - -/*-----------------------------------------------------------*/ - -/* Critical section management. */ -extern void vPortEnterCritical( void ); -extern void vPortExitCritical( void ); -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() - -#define portDISABLE_INTERRUPTS() asm( "cli" ) -#define portENABLE_INTERRUPTS() asm( "sei" ) -/*-----------------------------------------------------------*/ - -/* Architecture specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 1 -#define portNOP() asm( "nop" ) -/*-----------------------------------------------------------*/ - -/* Kernel utilities. */ -void vPortYield( void ); -#define portYIELD() vPortYield() - -#ifdef IAR_MEGA_AVR - #define outb( PORT, VALUE ) PORT = VALUE -#endif -/*-----------------------------------------------------------*/ - -/* Compiler specifics. */ -#define inline -/*-----------------------------------------------------------*/ - -/* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) - -#endif /* PORTMACRO_H */ - - diff --git a/Source/portable/IAR/ATMega323/portmacro.s90 b/Source/portable/IAR/ATMega323/portmacro.s90 deleted file mode 100644 index bce1756ec..000000000 --- a/Source/portable/IAR/ATMega323/portmacro.s90 +++ /dev/null @@ -1,245 +0,0 @@ -; FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. -; -; This file is part of the FreeRTOS.org distribution. -; -; FreeRTOS.org is free software; you can redistribute it and/or modify -; it under the terms of the GNU General Public License as published by -; the Free Software Foundation; either version 2 of the License, or -; (at your option) any later version. -; -; FreeRTOS.org is distributed in the hope that it will be useful, -; but WITHOUT ANY WARRANTY; without even the implied warranty of -; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; GNU General Public License for more details. -; -; You should have received a copy of the GNU General Public License -; along with FreeRTOS.org; if not, write to the Free Software -; Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -; -; A special exception to the GPL can be applied should you wish to distribute -; a combined work that includes FreeRTOS.org, without being obliged to provide -; the source code for any proprietary components. See the licensing section -; of http://www.FreeRTOS.org for full details of how and when the exception -; can be applied. -; -; *************************************************************************** -; See http://www.FreeRTOS.org for documentation, latest information, license -; and contact details. Please ensure to read the configuration and relevant -; port sections of the online documentation. -; *************************************************************************** - -#include - -; Declare all extern symbols here - including any ISRs that are referenced in -; the vector table. - -; ISR functions -; ------------- -EXTERN SIG_OUTPUT_COMPARE1A -EXTERN SIG_UART_RECV -EXTERN SIG_UART_DATA - - -; Functions used by scheduler -; --------------------------- -EXTERN vTaskSwitchContext -EXTERN pxCurrentTCB -EXTERN vTaskIncrementTick -EXTERN uxCriticalNesting - -; Functions implemented in this file -; ---------------------------------- -PUBLIC vPortYield -PUBLIC vPortYieldFromTick -PUBLIC vPortStart - - -; Interrupt vector table. -; ----------------------- -; -; For simplicity the RTOS tick interrupt routine uses the __task keyword. -; As the IAR compiler does not permit a function to be declared using both -; __task and __interrupt, the use of __task necessitates that the interrupt -; vector table be setup manually. -; -; To write an ISR, implement the ISR function using the __interrupt keyword -; but do not install the interrupt using the "#pragma vector=ABC" method. -; Instead manually place the name of the ISR in the vector table using an -; ORG and jmp instruction as demonstrated below. -; You will also have to add an EXTERN statement at the top of the file. - - ASEG - - - ORG TIMER1_COMPA_vect ; Vector address - jmp SIG_OUTPUT_COMPARE1A ; ISR - - ORG USART_RXC_vect ; Vector address - jmp SIG_UART_RECV ; ISR - - ORG USART_UDRE_vect ; Vector address - jmp SIG_UART_DATA ; ISR - - - RSEG CODE - - - -; Saving and Restoring a Task Context and Task Switching -; ------------------------------------------------------ -; -; The IAR compiler does not fully support inline assembler, so saving and -; restoring a task context has to be written in an asm file. -; -; vPortYield() and vPortYieldFromTick() are usually written in C. Doing -; so in this case would required calls to be made to portSAVE_CONTEXT() and -; portRESTORE_CONTEXT(). This is dis-advantageous as the context switch -; function would require two extra jump and return instructions over the -; WinAVR equivalent. -; -; To avoid this I have opted to implement both vPortYield() and -; vPortYieldFromTick() in this assembly file. For convenience -; portSAVE_CONTEXT and portRESTORE_CONTEXT are implemented as macros. - -portSAVE_CONTEXT MACRO - st -y, r0 ; First save the r0 register - we need to use this. - in r0, SREG ; Obtain the SREG value so we can disable interrupts... - cli ; ... as soon as possible. - st -y, r0 ; Store the SREG as it was before we disabled interrupts. - - in r0, SPL ; Next store the hardware stack pointer. The IAR... - st -y, r0 ; ... compiler uses the hardware stack as a call stack ... - in r0, SPH ; ... only. - st -y, r0 - - st -y, r1 ; Now store the rest of the registers. Dont store the ... - st -y, r2 ; ... the Y register here as it is used as the software - st -y, r3 ; stack pointer and will get saved into the TCB. - st -y, r4 - st -y, r5 - st -y, r6 - st -y, r7 - st -y, r8 - st -y, r9 - st -y, r10 - st -y, r11 - st -y, r12 - st -y, r13 - st -y, r14 - st -y, r15 - st -y, r16 - st -y, r17 - st -y, r18 - st -y, r19 - st -y, r20 - st -y, r21 - st -y, r22 - st -y, r23 - st -y, r24 - st -y, r25 - st -y, r26 - st -y, r27 - st -y, r30 - st -y, r31 - lds r0, uxCriticalNesting - st -y, r0 ; Store the critical nesting counter. - - lds r26, pxCurrentTCB ; Finally save the software stack pointer (Y ... - lds r27, pxCurrentTCB + 1 ; ... register) into the TCB. - st x+, r28 - st x+, r29 - - ENDM - - -portRESTORE_CONTEXT MACRO - lds r26, pxCurrentTCB - lds r27, pxCurrentTCB + 1 ; Restore the software stack pointer from ... - ld r28, x+ ; the TCB into the software stack pointer (... - ld r29, x+ ; ... the Y register). - - ld r0, y+ - sts uxCriticalNesting, r0 - ld r31, y+ ; Restore the registers down to R0. The Y - ld r30, y+ ; register is missing from this list as it - ld r27, y+ ; has already been restored. - ld r26, y+ - ld r25, y+ - ld r24, y+ - ld r23, y+ - ld r22, y+ - ld r21, y+ - ld r20, y+ - ld r19, y+ - ld r18, y+ - ld r17, y+ - ld r16, y+ - ld r15, y+ - ld r14, y+ - ld r13, y+ - ld r12, y+ - ld r11, y+ - ld r10, y+ - ld r9, y+ - ld r8, y+ - ld r7, y+ - ld r6, y+ - ld r5, y+ - ld r4, y+ - ld r3, y+ - ld r2, y+ - ld r1, y+ - - ld r0, y+ ; The next thing on the stack is the ... - out SPH, r0 ; ... hardware stack pointer. - ld r0, y+ - out SPL, r0 - - ld r0, y+ ; Next there is the SREG register. - out SREG, r0 - - ld r0, y+ ; Finally we have finished with r0, so restore r0. - - ENDM - - - -; vPortYield() and vPortYieldFromTick() -; ------------------------------------- -; -; Manual and preemptive context switch functions respectively. -; The IAR compiler does not fully support inline assembler, -; so these are implemented here rather than the more usually -; place of within port.c. - -vPortYield: - portSAVE_CONTEXT ; Save the context of the current task. - call vTaskSwitchContext ; Call the scheduler. - portRESTORE_CONTEXT ; Restore the context of whichever task the ... - ret ; ... scheduler decided should run. - -vPortYieldFromTick: - portSAVE_CONTEXT ; Save the context of the current task. - call vTaskIncrementTick ; Call the timer tick function. - call vTaskSwitchContext ; Call the scheduler. - portRESTORE_CONTEXT ; Restore the context of whichever task the ... - ret ; ... scheduler decided should run. - -; vPortStart() -; ------------ -; -; Again due to the lack of inline assembler, this is required -; to get access to the portRESTORE_CONTEXT macro. - -vPortStart: - portRESTORE_CONTEXT - ret - - -; Just a filler for unused interrupt vectors. -vNoISR: - reti - - - END - diff --git a/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h b/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h deleted file mode 100644 index 8f9ddb43a..000000000 --- a/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h +++ /dev/null @@ -1,1914 +0,0 @@ -// ---------------------------------------------------------------------------- -// ATMEL Microcontroller Software Support - ROUSSET - -// ---------------------------------------------------------------------------- -// The software is delivered "AS IS" without warranty or condition of any -// kind, either express, implied or statutory. This includes without -// limitation any warranty or condition with respect to merchantability or -// fitness for any particular purpose, or against the infringements of -// intellectual property rights of others. -// ---------------------------------------------------------------------------- -// File Name : AT91SAM7S64.h -// Object : AT91SAM7S64 definitions -// Generated : AT91 SW Application Group 07/16/2004 (07:43:08) -// -// CVS Reference : /AT91SAM7S64.pl/1.12/Mon Jul 12 13:02:30 2004// -// CVS Reference : /SYSC_SAM7Sxx.pl/1.5/Mon Jul 12 16:22:12 2004// -// CVS Reference : /MC_SAM02.pl/1.3/Wed Mar 10 08:37:04 2004// -// CVS Reference : /UDP_1765B.pl/1.3/Fri Aug 2 14:45:38 2002// -// CVS Reference : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// -// CVS Reference : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004// -// CVS Reference : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// -// CVS Reference : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003// -// CVS Reference : /US_1739C.pl/1.2/Mon Jul 12 17:26:24 2004// -// CVS Reference : /SPI2.pl/1.2/Fri Oct 17 08:13:40 2003// -// CVS Reference : /SSC_1762A.pl/1.2/Fri Nov 8 13:26:40 2002// -// CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// -// CVS Reference : /TWI_1761B.pl/1.4/Fri Feb 7 10:30:08 2003// -// CVS Reference : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:24 2002// -// CVS Reference : /ADC_SAM.pl/1.7/Fri Oct 17 08:12:38 2003// -// CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// -// ---------------------------------------------------------------------------- - -#ifndef AT91SAM7S64_H -#define AT91SAM7S64_H - -typedef volatile unsigned int AT91_REG;// Hardware register definition - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Peripherals -// ***************************************************************************** -typedef struct _AT91S_SYSC { - AT91_REG SYSC_AIC_SMR[32]; // Source Mode Register - AT91_REG SYSC_AIC_SVR[32]; // Source Vector Register - AT91_REG SYSC_AIC_IVR; // IRQ Vector Register - AT91_REG SYSC_AIC_FVR; // FIQ Vector Register - AT91_REG SYSC_AIC_ISR; // Interrupt Status Register - AT91_REG SYSC_AIC_IPR; // Interrupt Pending Register - AT91_REG SYSC_AIC_IMR; // Interrupt Mask Register - AT91_REG SYSC_AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG SYSC_AIC_IECR; // Interrupt Enable Command Register - AT91_REG SYSC_AIC_IDCR; // Interrupt Disable Command Register - AT91_REG SYSC_AIC_ICCR; // Interrupt Clear Command Register - AT91_REG SYSC_AIC_ISCR; // Interrupt Set Command Register - AT91_REG SYSC_AIC_EOICR; // End of Interrupt Command Register - AT91_REG SYSC_AIC_SPU; // Spurious Vector Register - AT91_REG SYSC_AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG SYSC_AIC_FFER; // Fast Forcing Enable Register - AT91_REG SYSC_AIC_FFDR; // Fast Forcing Disable Register - AT91_REG SYSC_AIC_FFSR; // Fast Forcing Status Register - AT91_REG Reserved2[45]; // - AT91_REG SYSC_DBGU_CR; // Control Register - AT91_REG SYSC_DBGU_MR; // Mode Register - AT91_REG SYSC_DBGU_IER; // Interrupt Enable Register - AT91_REG SYSC_DBGU_IDR; // Interrupt Disable Register - AT91_REG SYSC_DBGU_IMR; // Interrupt Mask Register - AT91_REG SYSC_DBGU_CSR; // Channel Status Register - AT91_REG SYSC_DBGU_RHR; // Receiver Holding Register - AT91_REG SYSC_DBGU_THR; // Transmitter Holding Register - AT91_REG SYSC_DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved3[7]; // - AT91_REG SYSC_DBGU_C1R; // Chip ID1 Register - AT91_REG SYSC_DBGU_C2R; // Chip ID2 Register - AT91_REG SYSC_DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved4[45]; // - AT91_REG SYSC_DBGU_RPR; // Receive Pointer Register - AT91_REG SYSC_DBGU_RCR; // Receive Counter Register - AT91_REG SYSC_DBGU_TPR; // Transmit Pointer Register - AT91_REG SYSC_DBGU_TCR; // Transmit Counter Register - AT91_REG SYSC_DBGU_RNPR; // Receive Next Pointer Register - AT91_REG SYSC_DBGU_RNCR; // Receive Next Counter Register - AT91_REG SYSC_DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG SYSC_DBGU_TNCR; // Transmit Next Counter Register - AT91_REG SYSC_DBGU_PTCR; // PDC Transfer Control Register - AT91_REG SYSC_DBGU_PTSR; // PDC Transfer Status Register - AT91_REG Reserved5[54]; // - AT91_REG SYSC_PIOA_PER; // PIO Enable Register - AT91_REG SYSC_PIOA_PDR; // PIO Disable Register - AT91_REG SYSC_PIOA_PSR; // PIO Status Register - AT91_REG Reserved6[1]; // - AT91_REG SYSC_PIOA_OER; // Output Enable Register - AT91_REG SYSC_PIOA_ODR; // Output Disable Registerr - AT91_REG SYSC_PIOA_OSR; // Output Status Register - AT91_REG Reserved7[1]; // - AT91_REG SYSC_PIOA_IFER; // Input Filter Enable Register - AT91_REG SYSC_PIOA_IFDR; // Input Filter Disable Register - AT91_REG SYSC_PIOA_IFSR; // Input Filter Status Register - AT91_REG Reserved8[1]; // - AT91_REG SYSC_PIOA_SODR; // Set Output Data Register - AT91_REG SYSC_PIOA_CODR; // Clear Output Data Register - AT91_REG SYSC_PIOA_ODSR; // Output Data Status Register - AT91_REG SYSC_PIOA_PDSR; // Pin Data Status Register - AT91_REG SYSC_PIOA_IER; // Interrupt Enable Register - AT91_REG SYSC_PIOA_IDR; // Interrupt Disable Register - AT91_REG SYSC_PIOA_IMR; // Interrupt Mask Register - AT91_REG SYSC_PIOA_ISR; // Interrupt Status Register - AT91_REG SYSC_PIOA_MDER; // Multi-driver Enable Register - AT91_REG SYSC_PIOA_MDDR; // Multi-driver Disable Register - AT91_REG SYSC_PIOA_MDSR; // Multi-driver Status Register - AT91_REG Reserved9[1]; // - AT91_REG SYSC_PIOA_PPUDR; // Pull-up Disable Register - AT91_REG SYSC_PIOA_PPUER; // Pull-up Enable Register - AT91_REG SYSC_PIOA_PPUSR; // Pad Pull-up Status Register - AT91_REG Reserved10[1]; // - AT91_REG SYSC_PIOA_ASR; // Select A Register - AT91_REG SYSC_PIOA_BSR; // Select B Register - AT91_REG SYSC_PIOA_ABSR; // AB Select Status Register - AT91_REG Reserved11[9]; // - AT91_REG SYSC_PIOA_OWER; // Output Write Enable Register - AT91_REG SYSC_PIOA_OWDR; // Output Write Disable Register - AT91_REG SYSC_PIOA_OWSR; // Output Write Status Register - AT91_REG Reserved12[469]; // - AT91_REG SYSC_PMC_SCER; // System Clock Enable Register - AT91_REG SYSC_PMC_SCDR; // System Clock Disable Register - AT91_REG SYSC_PMC_SCSR; // System Clock Status Register - AT91_REG Reserved13[1]; // - AT91_REG SYSC_PMC_PCER; // Peripheral Clock Enable Register - AT91_REG SYSC_PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG SYSC_PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved14[1]; // - AT91_REG SYSC_PMC_MOR; // Main Oscillator Register - AT91_REG SYSC_PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved15[1]; // - AT91_REG SYSC_PMC_PLLR; // PLL Register - AT91_REG SYSC_PMC_MCKR; // Master Clock Register - AT91_REG Reserved16[3]; // - AT91_REG SYSC_PMC_PCKR[8]; // Programmable Clock Register - AT91_REG SYSC_PMC_IER; // Interrupt Enable Register - AT91_REG SYSC_PMC_IDR; // Interrupt Disable Register - AT91_REG SYSC_PMC_SR; // Status Register - AT91_REG SYSC_PMC_IMR; // Interrupt Mask Register - AT91_REG Reserved17[36]; // - AT91_REG SYSC_RSTC_RCR; // Reset Control Register - AT91_REG SYSC_RSTC_RSR; // Reset Status Register - AT91_REG SYSC_RSTC_RMR; // Reset Mode Register - AT91_REG Reserved18[5]; // - AT91_REG SYSC_RTTC_RTMR; // Real-time Mode Register - AT91_REG SYSC_RTTC_RTAR; // Real-time Alarm Register - AT91_REG SYSC_RTTC_RTVR; // Real-time Value Register - AT91_REG SYSC_RTTC_RTSR; // Real-time Status Register - AT91_REG SYSC_PITC_PIMR; // Period Interval Mode Register - AT91_REG SYSC_PITC_PISR; // Period Interval Status Register - AT91_REG SYSC_PITC_PIVR; // Period Interval Value Register - AT91_REG SYSC_PITC_PIIR; // Period Interval Image Register - AT91_REG SYSC_WDTC_WDCR; // Watchdog Control Register - AT91_REG SYSC_WDTC_WDMR; // Watchdog Mode Register - AT91_REG SYSC_WDTC_WDSR; // Watchdog Status Register - AT91_REG Reserved19[5]; // - AT91_REG SYSC_SYSC_VRPM; // Voltage Regulator Power Mode Register -} AT91S_SYSC, *AT91PS_SYSC; - -// -------- VRPM : (SYSC Offset: 0xd60) Voltage Regulator Power Mode Register -------- -#define AT91C_SYSC_PSTDBY ((unsigned int) 0x1 << 0) // (SYSC) Voltage Regulator Power Mode - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// ***************************************************************************** -typedef struct _AT91S_AIC { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register -} AT91S_AIC, *AT91PS_AIC; - -// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level -#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level -#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level -#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type -#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive -#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered -#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered -// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status -#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status -// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode -#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Debug Unit -// ***************************************************************************** -typedef struct _AT91S_DBGU { - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved0[7]; // - AT91_REG DBGU_C1R; // Chip ID1 Register - AT91_REG DBGU_C2R; // Chip ID2 Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved1[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register -} AT91S_DBGU, *AT91PS_DBGU; - -// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver -#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter -#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable -#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable -#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable -#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable -// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type -#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity -#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity -#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space) -#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark) -#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity -#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode -#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode -#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt -#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt -#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt -#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt -#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt -#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt -#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt -#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt -#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt -#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt -#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt -#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt -// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Peripheral Data Controller -// ***************************************************************************** -typedef struct _AT91S_PDC { - AT91_REG PDC_RPR; // Receive Pointer Register - AT91_REG PDC_RCR; // Receive Counter Register - AT91_REG PDC_TPR; // Transmit Pointer Register - AT91_REG PDC_TCR; // Transmit Counter Register - AT91_REG PDC_RNPR; // Receive Next Pointer Register - AT91_REG PDC_RNCR; // Receive Next Counter Register - AT91_REG PDC_TNPR; // Transmit Next Pointer Register - AT91_REG PDC_TNCR; // Transmit Next Counter Register - AT91_REG PDC_PTCR; // PDC Transfer Control Register - AT91_REG PDC_PTSR; // PDC Transfer Status Register -} AT91S_PDC, *AT91PS_PDC; - -// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable -#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable -#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable -#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable -// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// ***************************************************************************** -typedef struct _AT91S_PIO { - AT91_REG PIO_PER; // PIO Enable Register - AT91_REG PIO_PDR; // PIO Disable Register - AT91_REG PIO_PSR; // PIO Status Register - AT91_REG Reserved0[1]; // - AT91_REG PIO_OER; // Output Enable Register - AT91_REG PIO_ODR; // Output Disable Registerr - AT91_REG PIO_OSR; // Output Status Register - AT91_REG Reserved1[1]; // - AT91_REG PIO_IFER; // Input Filter Enable Register - AT91_REG PIO_IFDR; // Input Filter Disable Register - AT91_REG PIO_IFSR; // Input Filter Status Register - AT91_REG Reserved2[1]; // - AT91_REG PIO_SODR; // Set Output Data Register - AT91_REG PIO_CODR; // Clear Output Data Register - AT91_REG PIO_ODSR; // Output Data Status Register - AT91_REG PIO_PDSR; // Pin Data Status Register - AT91_REG PIO_IER; // Interrupt Enable Register - AT91_REG PIO_IDR; // Interrupt Disable Register - AT91_REG PIO_IMR; // Interrupt Mask Register - AT91_REG PIO_ISR; // Interrupt Status Register - AT91_REG PIO_MDER; // Multi-driver Enable Register - AT91_REG PIO_MDDR; // Multi-driver Disable Register - AT91_REG PIO_MDSR; // Multi-driver Status Register - AT91_REG Reserved3[1]; // - AT91_REG PIO_PPUDR; // Pull-up Disable Register - AT91_REG PIO_PPUER; // Pull-up Enable Register - AT91_REG PIO_PPUSR; // Pad Pull-up Status Register - AT91_REG Reserved4[1]; // - AT91_REG PIO_ASR; // Select A Register - AT91_REG PIO_BSR; // Select B Register - AT91_REG PIO_ABSR; // AB Select Status Register - AT91_REG Reserved5[9]; // - AT91_REG PIO_OWER; // Output Write Enable Register - AT91_REG PIO_OWDR; // Output Write Disable Register - AT91_REG PIO_OWSR; // Output Write Status Register -} AT91S_PIO, *AT91PS_PIO; - - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Clock Generator Controler -// ***************************************************************************** -typedef struct _AT91S_CKGR { - AT91_REG CKGR_MOR; // Main Oscillator Register - AT91_REG CKGR_MCFR; // Main Clock Frequency Register - AT91_REG Reserved0[1]; // - AT91_REG CKGR_PLLR; // PLL Register -} AT91S_CKGR, *AT91PS_CKGR; - -// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable -#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass -#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time -// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency -#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready -// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- -#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter -#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range -#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier -#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks -#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output -#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 -#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Power Management Controler -// ***************************************************************************** -typedef struct _AT91S_PMC { - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved0[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved1[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved2[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved3[3]; // - AT91_REG PMC_PCKR[8]; // Programmable Clock Register - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register -} AT91S_PMC, *AT91PS_PMC; - -// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock -#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock -#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output -// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- -// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- -// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- -// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection -#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected -#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected -#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected -#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler -#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock -#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 -#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 -#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 -#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 -#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 -#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 -// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask -#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask -#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask -// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Reset Controller Interface -// ***************************************************************************** -typedef struct _AT91S_RSTC { - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register -} AT91S_RSTC, *AT91PS_RSTC; - -// -------- SYSC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- -#define AT91C_SYSC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset -#define AT91C_SYSC_ICERST ((unsigned int) 0x1 << 1) // (RSTC) ICE Interface Reset -#define AT91C_SYSC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset -#define AT91C_SYSC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset -#define AT91C_SYSC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password -// -------- SYSC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- -#define AT91C_SYSC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status -#define AT91C_SYSC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brown-out Detection Status -#define AT91C_SYSC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type -#define AT91C_SYSC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. -#define AT91C_SYSC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. -#define AT91C_SYSC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. -#define AT91C_SYSC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low. -#define AT91C_SYSC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brown-out Reset. -#define AT91C_SYSC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level -#define AT91C_SYSC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress. -// -------- SYSC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- -#define AT91C_SYSC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable -#define AT91C_SYSC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable -#define AT91C_SYSC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable -#define AT91C_SYSC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brown-out Detection Interrupt Enable - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_RTTC { - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register -} AT91S_RTTC, *AT91PS_RTTC; - -// -------- SYSC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- -#define AT91C_SYSC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value -#define AT91C_SYSC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable -#define AT91C_SYSC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable -#define AT91C_SYSC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart -// -------- SYSC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- -#define AT91C_SYSC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value -// -------- SYSC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- -#define AT91C_SYSC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value -// -------- SYSC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- -#define AT91C_SYSC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status -#define AT91C_SYSC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_PITC { - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register -} AT91S_PITC, *AT91PS_PITC; - -// -------- SYSC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- -#define AT91C_SYSC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value -#define AT91C_SYSC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled -#define AT91C_SYSC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable -// -------- SYSC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- -#define AT91C_SYSC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status -// -------- SYSC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- -#define AT91C_SYSC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value -#define AT91C_SYSC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter -// -------- SYSC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_WDTC { - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register -} AT91S_WDTC, *AT91PS_WDTC; - -// -------- SYSC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- -#define AT91C_SYSC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart -// -------- SYSC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- -#define AT91C_SYSC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart -#define AT91C_SYSC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable -#define AT91C_SYSC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable -#define AT91C_SYSC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart -#define AT91C_SYSC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable -#define AT91C_SYSC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value -#define AT91C_SYSC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt -#define AT91C_SYSC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt -// -------- SYSC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- -#define AT91C_SYSC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow -#define AT91C_SYSC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Memory Controller Interface -// ***************************************************************************** -typedef struct _AT91S_MC { - AT91_REG MC_RCR; // MC Remap Control Register - AT91_REG MC_ASR; // MC Abort Status Register - AT91_REG MC_AASR; // MC Abort Address Status Register - AT91_REG Reserved0[21]; // - AT91_REG MC_FMR; // MC Flash Mode Register - AT91_REG MC_FCR; // MC Flash Command Register - AT91_REG MC_FSR; // MC Flash Status Register -} AT91S_MC, *AT91PS_MC; - -// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit -// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status -#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status -#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status -#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte -#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word -#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word -#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status -#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read -#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write -#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch -#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source -#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source -#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source -#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source -// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- -#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready -#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error -#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error -#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming -#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State -#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations -#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations -#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations -#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations -#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number -// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- -#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command -#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN. -#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. -#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. -#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits. -#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits. -#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit. -#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number -#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key -// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- -#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status -#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status -#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status -#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status -#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status -#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status -#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status -#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status -#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status -#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status -#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status -#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status -#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status -#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status -#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status -#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status -#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status -#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status -#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status -#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status -#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status -#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status -#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Serial Parallel Interface -// ***************************************************************************** -typedef struct _AT91S_SPI { - AT91_REG SPI_CR; // Control Register - AT91_REG SPI_MR; // Mode Register - AT91_REG SPI_RDR; // Receive Data Register - AT91_REG SPI_TDR; // Transmit Data Register - AT91_REG SPI_SR; // Status Register - AT91_REG SPI_IER; // Interrupt Enable Register - AT91_REG SPI_IDR; // Interrupt Disable Register - AT91_REG SPI_IMR; // Interrupt Mask Register - AT91_REG Reserved0[4]; // - AT91_REG SPI_CSR[4]; // Chip Select Register - AT91_REG Reserved1[48]; // - AT91_REG SPI_RPR; // Receive Pointer Register - AT91_REG SPI_RCR; // Receive Counter Register - AT91_REG SPI_TPR; // Transmit Pointer Register - AT91_REG SPI_TCR; // Transmit Counter Register - AT91_REG SPI_RNPR; // Receive Next Pointer Register - AT91_REG SPI_RNCR; // Receive Next Counter Register - AT91_REG SPI_TNPR; // Transmit Next Pointer Register - AT91_REG SPI_TNCR; // Transmit Next Counter Register - AT91_REG SPI_PTCR; // PDC Transfer Control Register - AT91_REG SPI_PTSR; // PDC Transfer Status Register -} AT91S_SPI, *AT91PS_SPI; - -// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable -#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable -#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset -#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer -// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode -#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select -#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select -#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select -#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode -#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection -#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection -#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection -#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select -#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects -// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data -#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data -#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full -#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty -#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error -#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status -#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer -#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer -#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt -#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt -#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt -#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt -#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status -// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity -#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase -#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 2) // (SPI) Chip Select Active After Transfer -#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer -#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer -#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer -#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer -#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer -#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer -#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer -#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer -#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer -#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer -#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Analog to Digital Convertor -// ***************************************************************************** -typedef struct _AT91S_ADC { - AT91_REG ADC_CR; // ADC Control Register - AT91_REG ADC_MR; // ADC Mode Register - AT91_REG Reserved0[2]; // - AT91_REG ADC_CHER; // ADC Channel Enable Register - AT91_REG ADC_CHDR; // ADC Channel Disable Register - AT91_REG ADC_CHSR; // ADC Channel Status Register - AT91_REG ADC_SR; // ADC Status Register - AT91_REG ADC_LCDR; // ADC Last Converted Data Register - AT91_REG ADC_IER; // ADC Interrupt Enable Register - AT91_REG ADC_IDR; // ADC Interrupt Disable Register - AT91_REG ADC_IMR; // ADC Interrupt Mask Register - AT91_REG ADC_CDR0; // ADC Channel Data Register 0 - AT91_REG ADC_CDR1; // ADC Channel Data Register 1 - AT91_REG ADC_CDR2; // ADC Channel Data Register 2 - AT91_REG ADC_CDR3; // ADC Channel Data Register 3 - AT91_REG ADC_CDR4; // ADC Channel Data Register 4 - AT91_REG ADC_CDR5; // ADC Channel Data Register 5 - AT91_REG ADC_CDR6; // ADC Channel Data Register 6 - AT91_REG ADC_CDR7; // ADC Channel Data Register 7 - AT91_REG Reserved1[44]; // - AT91_REG ADC_RPR; // Receive Pointer Register - AT91_REG ADC_RCR; // Receive Counter Register - AT91_REG ADC_TPR; // Transmit Pointer Register - AT91_REG ADC_TCR; // Transmit Counter Register - AT91_REG ADC_RNPR; // Receive Next Pointer Register - AT91_REG ADC_RNCR; // Receive Next Counter Register - AT91_REG ADC_TNPR; // Transmit Next Pointer Register - AT91_REG ADC_TNCR; // Transmit Next Counter Register - AT91_REG ADC_PTCR; // PDC Transfer Control Register - AT91_REG ADC_PTSR; // PDC Transfer Status Register -} AT91S_ADC, *AT91PS_ADC; - -// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- -#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset -#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion -// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- -#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable -#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software -#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. -#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection -#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 -#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 -#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 -#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 -#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 -#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 -#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger -#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution. -#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution -#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution -#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode -#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection -#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time -#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time -// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- -#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0 -#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1 -#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2 -#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3 -#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4 -#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5 -#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6 -#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7 -// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- -// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- -// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- -#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion -#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion -#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion -#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion -#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion -#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion -#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion -#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion -#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error -#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error -#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error -#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error -#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error -#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error -#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error -#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error -#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready -#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun -#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer -#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt -// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- -#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted -// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- -// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- -// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- -// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- -#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data -// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- -// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- -// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- -// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- -// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- -// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- -// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// ***************************************************************************** -typedef struct _AT91S_SSC { - AT91_REG SSC_CR; // Control Register - AT91_REG SSC_CMR; // Clock Mode Register - AT91_REG Reserved0[2]; // - AT91_REG SSC_RCMR; // Receive Clock ModeRegister - AT91_REG SSC_RFMR; // Receive Frame Mode Register - AT91_REG SSC_TCMR; // Transmit Clock Mode Register - AT91_REG SSC_TFMR; // Transmit Frame Mode Register - AT91_REG SSC_RHR; // Receive Holding Register - AT91_REG SSC_THR; // Transmit Holding Register - AT91_REG Reserved1[2]; // - AT91_REG SSC_RSHR; // Receive Sync Holding Register - AT91_REG SSC_TSHR; // Transmit Sync Holding Register - AT91_REG SSC_RC0R; // Receive Compare 0 Register - AT91_REG SSC_RC1R; // Receive Compare 1 Register - AT91_REG SSC_SR; // Status Register - AT91_REG SSC_IER; // Interrupt Enable Register - AT91_REG SSC_IDR; // Interrupt Disable Register - AT91_REG SSC_IMR; // Interrupt Mask Register - AT91_REG Reserved2[44]; // - AT91_REG SSC_RPR; // Receive Pointer Register - AT91_REG SSC_RCR; // Receive Counter Register - AT91_REG SSC_TPR; // Transmit Pointer Register - AT91_REG SSC_TCR; // Transmit Counter Register - AT91_REG SSC_RNPR; // Receive Next Pointer Register - AT91_REG SSC_RNCR; // Receive Next Counter Register - AT91_REG SSC_TNPR; // Transmit Next Pointer Register - AT91_REG SSC_TNCR; // Transmit Next Counter Register - AT91_REG SSC_PTCR; // PDC Transfer Control Register - AT91_REG SSC_PTSR; // PDC Transfer Status Register -} AT91S_SSC, *AT91PS_SSC; - -// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable -#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable -#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable -#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable -#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset -// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection -#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock -#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal -#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin -#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection -#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output -#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion -#define AT91C_SSC_CKG ((unsigned int) 0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection -#define AT91C_SSC_CKG_NONE ((unsigned int) 0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock -#define AT91C_SSC_CKG_LOW ((unsigned int) 0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low -#define AT91C_SSC_CKG_HIGH ((unsigned int) 0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High -#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection -#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start -#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input -#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input -#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input -#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input -#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input -#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input -#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0 -#define AT91C_SSC_STOP ((unsigned int) 0x1 << 12) // (SSC) Receive Stop Selection -#define AT91C_SSC_STTOUT ((unsigned int) 0x1 << 15) // (SSC) Receive/Transmit Start Output Selection -#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay -#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection -// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length -#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode -#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First -#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame -#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length -#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection -#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection -// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value -#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable -// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready -#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty -#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission -#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty -#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready -#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun -#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception -#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full -#define AT91C_SSC_CP0 ((unsigned int) 0x1 << 8) // (SSC) Compare 0 -#define AT91C_SSC_CP1 ((unsigned int) 0x1 << 9) // (SSC) Compare 1 -#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync -#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync -#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable -#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable -// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Usart -// ***************************************************************************** -typedef struct _AT91S_USART { - AT91_REG US_CR; // Control Register - AT91_REG US_MR; // Mode Register - AT91_REG US_IER; // Interrupt Enable Register - AT91_REG US_IDR; // Interrupt Disable Register - AT91_REG US_IMR; // Interrupt Mask Register - AT91_REG US_CSR; // Channel Status Register - AT91_REG US_RHR; // Receiver Holding Register - AT91_REG US_THR; // Transmitter Holding Register - AT91_REG US_BRGR; // Baud Rate Generator Register - AT91_REG US_RTOR; // Receiver Time-out Register - AT91_REG US_TTGR; // Transmitter Time-guard Register - AT91_REG Reserved0[5]; // - AT91_REG US_FIDI; // FI_DI_Ratio Register - AT91_REG US_NER; // Nb Errors Register - AT91_REG US_XXR; // XON_XOFF Register - AT91_REG US_IF; // IRDA_FILTER Register - AT91_REG Reserved1[44]; // - AT91_REG US_RPR; // Receive Pointer Register - AT91_REG US_RCR; // Receive Counter Register - AT91_REG US_TPR; // Transmit Pointer Register - AT91_REG US_TCR; // Transmit Counter Register - AT91_REG US_RNPR; // Receive Next Pointer Register - AT91_REG US_RNCR; // Receive Next Counter Register - AT91_REG US_TNPR; // Transmit Next Pointer Register - AT91_REG US_TNCR; // Transmit Next Counter Register - AT91_REG US_PTCR; // PDC Transfer Control Register - AT91_REG US_PTSR; // PDC Transfer Status Register -} AT91S_USART, *AT91PS_USART; - -// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (USART) Reset Status Bits -#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break -#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break -#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out -#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address -#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations -#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge -#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out -#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable -#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable -#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable -#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable -// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode -#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal -#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 -#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking -#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem -#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0 -#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1 -#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA -#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking -#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock -#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 -#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) -#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) -#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits -#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits -#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits -#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits -#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select -#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits -#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit -#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits -#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order -#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length -#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select -#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode -#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge -#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK -#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions -#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter -// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break -#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out -#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached -#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge -#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag -#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag -#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag -#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag -// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input -#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input -#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input -#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Two-wire Interface -// ***************************************************************************** -typedef struct _AT91S_TWI { - AT91_REG TWI_CR; // Control Register - AT91_REG TWI_MMR; // Master Mode Register - AT91_REG TWI_SMR; // Slave Mode Register - AT91_REG TWI_IADR; // Internal Address Register - AT91_REG TWI_CWGR; // Clock Waveform Generator Register - AT91_REG Reserved0[3]; // - AT91_REG TWI_SR; // Status Register - AT91_REG TWI_IER; // Interrupt Enable Register - AT91_REG TWI_IDR; // Interrupt Disable Register - AT91_REG TWI_IMR; // Interrupt Mask Register - AT91_REG TWI_RHR; // Receive Holding Register - AT91_REG TWI_THR; // Transmit Holding Register -} AT91S_TWI, *AT91PS_TWI; - -// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition -#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition -#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled -#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled -#define AT91C_TWI_SVEN ((unsigned int) 0x1 << 4) // (TWI) TWI Slave Transfer Enabled -#define AT91C_TWI_SVDIS ((unsigned int) 0x1 << 5) // (TWI) TWI Slave Transfer Disabled -#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset -// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size -#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address -#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address -#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address -#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address -#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction -#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address -// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- -#define AT91C_TWI_SADR ((unsigned int) 0x7F << 16) // (TWI) Slave Device Address -// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider -#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider -#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider -// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed -#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY -#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY -#define AT91C_TWI_SVREAD ((unsigned int) 0x1 << 3) // (TWI) Slave Read -#define AT91C_TWI_SVACC ((unsigned int) 0x1 << 4) // (TWI) Slave Access -#define AT91C_TWI_GCACC ((unsigned int) 0x1 << 5) // (TWI) General Call Access -#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error -#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error -#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged -#define AT91C_TWI_ARBLST ((unsigned int) 0x1 << 9) // (TWI) Arbitration Lost -// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// ***************************************************************************** -typedef struct _AT91S_TC { - AT91_REG TC_CCR; // Channel Control Register - AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) - AT91_REG Reserved0[2]; // - AT91_REG TC_CV; // Counter Value - AT91_REG TC_RA; // Register A - AT91_REG TC_RB; // Register B - AT91_REG TC_RC; // Register C - AT91_REG TC_SR; // Status Register - AT91_REG TC_IER; // Interrupt Enable Register - AT91_REG TC_IDR; // Interrupt Disable Register - AT91_REG TC_IMR; // Interrupt Mask Register -} AT91S_TC, *AT91PS_TC; - -// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command -#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command -#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command -// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection -#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK -#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0 -#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1 -#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2 -#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert -#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection -#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal -#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock -#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock -#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock -#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare -#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading -#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading -#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare -#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection -#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None -#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection -#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None -#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection -#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection -#define AT91C_TC_EEVT_NONE ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input -#define AT91C_TC_EEVT_RISING ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output -#define AT91C_TC_EEVT_FALLING ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output -#define AT91C_TC_EEVT_BOTH ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output -#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable -#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection -#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare -#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable -#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) -#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection -#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None -#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA -#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA -#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none -#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set -#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear -#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle -#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection -#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None -#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA -#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA -#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none -#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set -#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear -#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle -#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA -#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none -#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set -#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear -#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle -#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA -#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none -#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set -#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear -#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle -#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB -#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none -#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set -#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear -#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle -#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB -#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none -#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set -#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear -#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle -#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB -#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none -#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set -#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear -#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle -#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB -#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none -#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set -#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear -#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle -// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow -#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun -#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare -#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare -#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare -#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading -#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading -#define AT91C_TC_ETRCS ((unsigned int) 0x1 << 7) // (TC) External Trigger -#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 16) // (TC) Clock Enabling -#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror -#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror -// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Interface -// ***************************************************************************** -typedef struct _AT91S_TCB { - AT91S_TC TCB_TC0; // TC Channel 0 - AT91_REG Reserved0[4]; // - AT91S_TC TCB_TC1; // TC Channel 1 - AT91_REG Reserved1[4]; // - AT91S_TC TCB_TC2; // TC Channel 2 - AT91_REG Reserved2[4]; // - AT91_REG TCB_BCR; // TC Block Control Register - AT91_REG TCB_BMR; // TC Block Mode Register -} AT91S_TCB, *AT91PS_TCB; - -// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command -// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -#define AT91C_TCB_TC0XC0S ((unsigned int) 0x1 << 0) // (TCB) External Clock Signal 0 Selection -#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 -#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 -#define AT91C_TCB_TC1XC1S ((unsigned int) 0x1 << 2) // (TCB) External Clock Signal 1 Selection -#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 -#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 -#define AT91C_TCB_TC2XC2S ((unsigned int) 0x1 << 4) // (TCB) External Clock Signal 2 Selection -#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 -#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA2 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR PWMC Channel Interface -// ***************************************************************************** -typedef struct _AT91S_PWMC_CH { - AT91_REG PWMC_CMR; // Channel Mode Register - AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register - AT91_REG PWMC_CPRDR; // Channel Period Register - AT91_REG PWMC_CCNTR; // Channel Counter Register - AT91_REG PWMC_CUPDR; // Channel Update Register - AT91_REG PWMC_Reserved[3]; // Reserved -} AT91S_PWMC_CH, *AT91PS_PWMC_CH; - -// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- -#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx -#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) -#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment -#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity -#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period -// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- -#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle -// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- -#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period -// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- -#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter -// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- -#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface -// ***************************************************************************** -typedef struct _AT91S_PWMC { - AT91_REG PWMC_MR; // PWMC Mode Register - AT91_REG PWMC_ENA; // PWMC Enable Register - AT91_REG PWMC_DIS; // PWMC Disable Register - AT91_REG PWMC_SR; // PWMC Status Register - AT91_REG PWMC_IER; // PWMC Interrupt Enable Register - AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register - AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register - AT91_REG PWMC_ISR; // PWMC Interrupt Status Register - AT91_REG Reserved0[55]; // - AT91_REG PWMC_VR; // PWMC Version Register - AT91_REG Reserved1[64]; // - AT91S_PWMC_CH PWMC_CH[32]; // PWMC Channel 0 -} AT91S_PWMC, *AT91PS_PWMC; - -// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- -#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor. -#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A -#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) -#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor. -#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B -#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) -// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- -#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0 -#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1 -#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2 -#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3 -#define AT91C_PWMC_CHID4 ((unsigned int) 0x1 << 4) // (PWMC) Channel ID 4 -#define AT91C_PWMC_CHID5 ((unsigned int) 0x1 << 5) // (PWMC) Channel ID 5 -#define AT91C_PWMC_CHID6 ((unsigned int) 0x1 << 6) // (PWMC) Channel ID 6 -#define AT91C_PWMC_CHID7 ((unsigned int) 0x1 << 7) // (PWMC) Channel ID 7 -// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- -// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- -// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- -// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- -// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- -// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Device Interface -// ***************************************************************************** -typedef struct _AT91S_UDP { - AT91_REG UDP_NUM; // Frame Number Register - AT91_REG UDP_GLBSTATE; // Global State Register - AT91_REG UDP_FADDR; // Function Address Register - AT91_REG Reserved0[1]; // - AT91_REG UDP_IER; // Interrupt Enable Register - AT91_REG UDP_IDR; // Interrupt Disable Register - AT91_REG UDP_IMR; // Interrupt Mask Register - AT91_REG UDP_ISR; // Interrupt Status Register - AT91_REG UDP_ICR; // Interrupt Clear Register - AT91_REG Reserved1[1]; // - AT91_REG UDP_RSTEP; // Reset Endpoint Register - AT91_REG Reserved2[1]; // - AT91_REG UDP_CSR[8]; // Endpoint Control and Status Register - AT91_REG UDP_FDR[8]; // Endpoint FIFO Data Register -} AT91S_UDP, *AT91PS_UDP; - -// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats -#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error -#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK -// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable -#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured -#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 2) // (UDP) Remote Wake Up Enable -#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host -// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value -#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable -// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt -#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt -#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt -#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt -#define AT91C_UDP_EPINT6 ((unsigned int) 0x1 << 6) // (UDP) Endpoint 6 Interrupt -#define AT91C_UDP_EPINT7 ((unsigned int) 0x1 << 7) // (UDP) Endpoint 7 Interrupt -#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt -#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt -#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt -#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt -#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt -// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt -// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 -#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 -#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 -#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3 -#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4 -#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5 -#define AT91C_UDP_EP6 ((unsigned int) 0x1 << 6) // (UDP) Reset Endpoint 6 -#define AT91C_UDP_EP7 ((unsigned int) 0x1 << 7) // (UDP) Reset Endpoint 7 -// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR -#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 -#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) -#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) -#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready -#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction -#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type -#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control -#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT -#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT -#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT -#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN -#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN -#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN -#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle -#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable -#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO - -// ***************************************************************************** -// REGISTER ADDRESS DEFINITION FOR AT91SAM7S64 -// ***************************************************************************** -// ========== Register definition for SYSC peripheral ========== -#define AT91C_SYSC_SYSC_VRPM ((AT91_REG *) 0xFFFFFD60) // (SYSC) Voltage Regulator Power Mode Register -// ========== Register definition for AIC peripheral ========== -#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register -#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register -#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register -#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register -#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register -#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) -#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register -#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register -#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register -#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register -#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register -#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register -#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register -#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register -#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register -#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register -#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register -#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register -// ========== Register definition for DBGU peripheral ========== -#define AT91C_DBGU_C2R ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID2 Register -#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register -#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register -#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register -#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register -#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register -#define AT91C_DBGU_C1R ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID1 Register -#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register -#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register -#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register -#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register -#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register -// ========== Register definition for PDC_DBGU peripheral ========== -#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register -#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register -#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register -#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register -#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register -#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register -#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register -#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register -#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register -#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register -// ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register -#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register -#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register -#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register -#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register -#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register -#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register -#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pad Pull-up Status Register -#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register -#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register -#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register -#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register -#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register -// ========== Register definition for CKGR peripheral ========== -#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register -#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register -#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register -// ========== Register definition for PMC peripheral ========== -#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register -#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register -#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register -#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register -#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register -#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register -#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register -#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register -#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register -#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register -#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register -#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register -#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register -#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register -#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register -// ========== Register definition for RSTC peripheral ========== -#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register -#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register -#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register -// ========== Register definition for RTTC peripheral ========== -#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register -#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register -#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register -#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register -// ========== Register definition for PITC peripheral ========== -#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register -#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register -#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register -#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register -// ========== Register definition for WDTC peripheral ========== -#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register -#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register -#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register -// ========== Register definition for MC peripheral ========== -#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register -#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register -#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register -#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register -#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register -#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register -// ========== Register definition for PDC_SPI peripheral ========== -#define AT91C_SPI_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register -#define AT91C_SPI_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register -#define AT91C_SPI_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register -#define AT91C_SPI_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register -#define AT91C_SPI_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register -#define AT91C_SPI_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register -#define AT91C_SPI_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register -#define AT91C_SPI_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register -#define AT91C_SPI_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register -#define AT91C_SPI_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register -// ========== Register definition for SPI peripheral ========== -#define AT91C_SPI_CSR ((AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register -#define AT91C_SPI_IDR ((AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register -#define AT91C_SPI_SR ((AT91_REG *) 0xFFFE0010) // (SPI) Status Register -#define AT91C_SPI_RDR ((AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register -#define AT91C_SPI_CR ((AT91_REG *) 0xFFFE0000) // (SPI) Control Register -#define AT91C_SPI_IMR ((AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register -#define AT91C_SPI_IER ((AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register -#define AT91C_SPI_TDR ((AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register -#define AT91C_SPI_MR ((AT91_REG *) 0xFFFE0004) // (SPI) Mode Register -// ========== Register definition for PDC_ADC peripheral ========== -#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register -#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register -#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register -#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register -#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register -#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register -#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register -#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register -#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register -#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register -// ========== Register definition for ADC peripheral ========== -#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register -#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 -#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 -#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 -#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 -#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 -#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 -#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 -#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register -#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 -#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register -#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register -#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register -#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register -#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register -#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register -#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register -#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register -// ========== Register definition for PDC_SSC peripheral ========== -#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register -#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register -#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register -#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register -#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register -#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register -#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register -#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register -#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register -#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register -// ========== Register definition for SSC peripheral ========== -#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register -#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register -#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register -#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register -#define AT91C_SSC_RC0R ((AT91_REG *) 0xFFFD4038) // (SSC) Receive Compare 0 Register -#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register -#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register -#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register -#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister -#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register -#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register -#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register -#define AT91C_SSC_RC1R ((AT91_REG *) 0xFFFD403C) // (SSC) Receive Compare 1 Register -#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register -#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register -#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register -// ========== Register definition for PDC_US1 peripheral ========== -#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register -#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register -#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register -#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register -#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register -#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register -#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register -#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register -#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register -#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register -// ========== Register definition for US1 peripheral ========== -#define AT91C_US1_XXR ((AT91_REG *) 0xFFFC4048) // (US1) XON_XOFF Register -#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register -#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register -#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register -#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register -#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register -#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register -#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register -#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register -#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register -#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register -#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register -#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register -#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register -#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register -// ========== Register definition for PDC_US0 peripheral ========== -#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register -#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register -#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register -#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register -#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register -#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register -#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register -#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register -#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register -#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register -// ========== Register definition for US0 peripheral ========== -#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register -#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register -#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register -#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register -#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register -#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register -#define AT91C_US0_XXR ((AT91_REG *) 0xFFFC0048) // (US0) XON_XOFF Register -#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register -#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register -#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register -#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register -#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register -#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register -#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register -#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register -// ========== Register definition for TWI peripheral ========== -#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register -#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register -#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register -#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register -#define AT91C_TWI_SMR ((AT91_REG *) 0xFFFB8008) // (TWI) Slave Mode Register -#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register -#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register -#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register -#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register -#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register -#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register -// ========== Register definition for TC2 peripheral ========== -#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register -#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register -#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C -#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A -#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register -#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register -#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B -#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value -#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register -// ========== Register definition for TC1 peripheral ========== -#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register -#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register -#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C -#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A -#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register -#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register -#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B -#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value -#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register -// ========== Register definition for TC0 peripheral ========== -#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register -#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register -#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C -#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A -#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register -#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register -#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B -#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value -#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register -// ========== Register definition for TCB peripheral ========== -#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register -#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register -// ========== Register definition for PWMC_CH3 peripheral ========== -#define AT91C_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register -#define AT91C_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register -#define AT91C_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register -#define AT91C_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved -#define AT91C_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register -#define AT91C_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH2 peripheral ========== -#define AT91C_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register -#define AT91C_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register -#define AT91C_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register -#define AT91C_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved -#define AT91C_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register -#define AT91C_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH1 peripheral ========== -#define AT91C_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register -#define AT91C_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register -#define AT91C_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register -#define AT91C_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved -#define AT91C_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register -#define AT91C_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH0 peripheral ========== -#define AT91C_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register -#define AT91C_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register -#define AT91C_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register -#define AT91C_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved -#define AT91C_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register -#define AT91C_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register -// ========== Register definition for PWMC peripheral ========== -#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register -#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register -#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register -#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register -#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register -#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register -#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register -#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register -#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register -// ========== Register definition for UDP peripheral ========== -#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register -#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register -#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register -#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register -#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register -#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register -#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register -#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register -#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register -#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register -#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register - -// ***************************************************************************** -// PIO DEFINITIONS FOR AT91SAM7S64 -// ***************************************************************************** -#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 -#define AT91C_PA0_PWM0 ((unsigned int) AT91C_PIO_PA0) // PWM Channel 0 -#define AT91C_PA0_TIOA0 ((unsigned int) AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 -#define AT91C_PA1_PWM1 ((unsigned int) AT91C_PIO_PA1) // PWM Channel 1 -#define AT91C_PA1_TIOB0 ((unsigned int) AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 -#define AT91C_PA10_DTXD ((unsigned int) AT91C_PIO_PA10) // DBGU Debug Transmit Data -#define AT91C_PA10_NPCS2 ((unsigned int) AT91C_PIO_PA10) // SPI Peripheral Chip Select 2 -#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 -#define AT91C_PA11_NPCS0 ((unsigned int) AT91C_PIO_PA11) // SPI Peripheral Chip Select 0 -#define AT91C_PA11_PWM0 ((unsigned int) AT91C_PIO_PA11) // PWM Channel 0 -#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 -#define AT91C_PA12_MISO ((unsigned int) AT91C_PIO_PA12) // SPI Master In Slave -#define AT91C_PA12_PWM1 ((unsigned int) AT91C_PIO_PA12) // PWM Channel 1 -#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 -#define AT91C_PA13_MOSI ((unsigned int) AT91C_PIO_PA13) // SPI Master Out Slave -#define AT91C_PA13_PWM2 ((unsigned int) AT91C_PIO_PA13) // PWM Channel 2 -#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 -#define AT91C_PA14_SPCK ((unsigned int) AT91C_PIO_PA14) // SPI Serial Clock -#define AT91C_PA14_PWM3 ((unsigned int) AT91C_PIO_PA14) // PWM Channel 3 -#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 -#define AT91C_PA15_TF ((unsigned int) AT91C_PIO_PA15) // SSC Transmit Frame Sync -#define AT91C_PA15_TIOA1 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 -#define AT91C_PA16_TK ((unsigned int) AT91C_PIO_PA16) // SSC Transmit Clock -#define AT91C_PA16_TIOB1 ((unsigned int) AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 -#define AT91C_PA17_TD ((unsigned int) AT91C_PIO_PA17) // SSC Transmit data -#define AT91C_PA17_PCK1 ((unsigned int) AT91C_PIO_PA17) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 -#define AT91C_PA18_RD ((unsigned int) AT91C_PIO_PA18) // SSC Receive Data -#define AT91C_PA18_PCK2 ((unsigned int) AT91C_PIO_PA18) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 -#define AT91C_PA19_RK ((unsigned int) AT91C_PIO_PA19) // SSC Receive Clock -#define AT91C_PA19_FIQ ((unsigned int) AT91C_PIO_PA19) // AIC Fast Interrupt Input -#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 -#define AT91C_PA2_PWM2 ((unsigned int) AT91C_PIO_PA2) // PWM Channel 2 -#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock -#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 -#define AT91C_PA20_RF ((unsigned int) AT91C_PIO_PA20) // SSC Receive Frame Sync -#define AT91C_PA20_IRQ0 ((unsigned int) AT91C_PIO_PA20) // External Interrupt 0 -#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 -#define AT91C_PA21_RXD1 ((unsigned int) AT91C_PIO_PA21) // USART 1 Receive Data -#define AT91C_PA21_PCK1 ((unsigned int) AT91C_PIO_PA21) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 -#define AT91C_PA22_TXD1 ((unsigned int) AT91C_PIO_PA22) // USART 1 Transmit Data -#define AT91C_PA22_NPCS3 ((unsigned int) AT91C_PIO_PA22) // SPI Peripheral Chip Select 3 -#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 -#define AT91C_PA23_SCK1 ((unsigned int) AT91C_PIO_PA23) // USART 1 Serial Clock -#define AT91C_PA23_PWM0 ((unsigned int) AT91C_PIO_PA23) // PWM Channel 0 -#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 -#define AT91C_PA24_RTS1 ((unsigned int) AT91C_PIO_PA24) // USART 1 Ready To Send -#define AT91C_PA24_PWM1 ((unsigned int) AT91C_PIO_PA24) // PWM Channel 1 -#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 -#define AT91C_PA25_CTS1 ((unsigned int) AT91C_PIO_PA25) // USART 1 Clear To Send -#define AT91C_PA25_PWM2 ((unsigned int) AT91C_PIO_PA25) // PWM Channel 2 -#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 -#define AT91C_PA26_DCD1 ((unsigned int) AT91C_PIO_PA26) // USART 1 Data Carrier Detect -#define AT91C_PA26_TIOA2 ((unsigned int) AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 -#define AT91C_PA27_DTR1 ((unsigned int) AT91C_PIO_PA27) // USART 1 Data Terminal ready -#define AT91C_PA27_TIOB2 ((unsigned int) AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 -#define AT91C_PA28_DSR1 ((unsigned int) AT91C_PIO_PA28) // USART 1 Data Set ready -#define AT91C_PA28_TCLK1 ((unsigned int) AT91C_PIO_PA28) // Timer Counter 1 external clock input -#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 -#define AT91C_PA29_RI1 ((unsigned int) AT91C_PIO_PA29) // USART 1 Ring Indicator -#define AT91C_PA29_TCLK2 ((unsigned int) AT91C_PIO_PA29) // Timer Counter 2 external clock input -#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 -#define AT91C_PA3_TWD ((unsigned int) AT91C_PIO_PA3) // TWI Two-wire Serial Data -#define AT91C_PA3_NPCS3 ((unsigned int) AT91C_PIO_PA3) // SPI Peripheral Chip Select 3 -#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 -#define AT91C_PA30_IRQ1 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 1 -#define AT91C_PA30_NPCS2 ((unsigned int) AT91C_PIO_PA30) // SPI Peripheral Chip Select 2 -#define AT91C_PIO_PA31 ((unsigned int) 1 << 31) // Pin Controlled by PA31 -#define AT91C_PA31_NPCS1 ((unsigned int) AT91C_PIO_PA31) // SPI Peripheral Chip Select 1 -#define AT91C_PA31_PCK2 ((unsigned int) AT91C_PIO_PA31) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 -#define AT91C_PA4_TWCK ((unsigned int) AT91C_PIO_PA4) // TWI Two-wire Serial Clock -#define AT91C_PA4_TCLK0 ((unsigned int) AT91C_PIO_PA4) // Timer Counter 0 external clock input -#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 -#define AT91C_PA5_RXD0 ((unsigned int) AT91C_PIO_PA5) // USART 0 Receive Data -#define AT91C_PA5_NPCS3 ((unsigned int) AT91C_PIO_PA5) // SPI Peripheral Chip Select 3 -#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 -#define AT91C_PA6_TXD0 ((unsigned int) AT91C_PIO_PA6) // USART 0 Transmit Data -#define AT91C_PA6_PCK0 ((unsigned int) AT91C_PIO_PA6) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 -#define AT91C_PA7_RTS0 ((unsigned int) AT91C_PIO_PA7) // USART 0 Ready To Send -#define AT91C_PA7_PWM3 ((unsigned int) AT91C_PIO_PA7) // PWM Channel 3 -#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 -#define AT91C_PA8_CTS0 ((unsigned int) AT91C_PIO_PA8) // USART 0 Clear To Send -#define AT91C_PA8_ADTRG ((unsigned int) AT91C_PIO_PA8) // ADC External Trigger -#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 -#define AT91C_PA9_DRXD ((unsigned int) AT91C_PIO_PA9) // DBGU Debug Receive Data -#define AT91C_PA9_NPCS1 ((unsigned int) AT91C_PIO_PA9) // SPI Peripheral Chip Select 1 - -// ***************************************************************************** -// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64 -// ***************************************************************************** -#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) -#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral -#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller -#define AT91C_ID_3_Reserved ((unsigned int) 3) // Reserved -#define AT91C_ID_ADC ((unsigned int) 4) // Analog-to-Digital Converter -#define AT91C_ID_SPI ((unsigned int) 5) // Serial Peripheral Interface -#define AT91C_ID_US0 ((unsigned int) 6) // USART 0 -#define AT91C_ID_US1 ((unsigned int) 7) // USART 1 -#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller -#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface -#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller -#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port -#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0 -#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1 -#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2 -#define AT91C_ID_15_Reserved ((unsigned int) 15) // Reserved -#define AT91C_ID_16_Reserved ((unsigned int) 16) // Reserved -#define AT91C_ID_17_Reserved ((unsigned int) 17) // Reserved -#define AT91C_ID_18_Reserved ((unsigned int) 18) // Reserved -#define AT91C_ID_19_Reserved ((unsigned int) 19) // Reserved -#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved -#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved -#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved -#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved -#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved -#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved -#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved -#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved -#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved -#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved -#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0) -#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1) - -// ***************************************************************************** -// BASE ADDRESS DEFINITIONS FOR AT91SAM7S64 -// ***************************************************************************** -#define AT91C_BASE_SYSC ((AT91PS_SYSC) 0xFFFFF000) // (SYSC) Base Address -#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address -#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address -#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address -#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address -#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address -#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address -#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address -#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address -#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address -#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address -#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address -#define AT91C_BASE_PDC_SPI ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address -#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address -#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address -#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address -#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address -#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address -#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address -#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address -#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address -#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address -#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address -#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address -#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address -#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address -#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address -#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address -#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address -#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address -#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address -#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address -#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address - -// ***************************************************************************** -// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64 -// ***************************************************************************** -#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address -#define AT91C_ISRAM_SIZE ((unsigned int) 0x00004000) // Internal SRAM size in byte (16 Kbyte) -#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address -#define AT91C_IFLASH_SIZE ((unsigned int) 0x00010000) // Internal ROM size in byte (64 Kbyte) - -#endif diff --git a/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h b/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h deleted file mode 100644 index 7d2657a20..000000000 --- a/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h +++ /dev/null @@ -1,1812 +0,0 @@ -// ---------------------------------------------------------------------------- -// ATMEL Microcontroller Software Support - ROUSSET - -// ---------------------------------------------------------------------------- -// The software is delivered "AS IS" without warranty or condition of any -// kind, either express, implied or statutory. This includes without -// limitation any warranty or condition with respect to merchantability or -// fitness for any particular purpose, or against the infringements of -// intellectual property rights of others. -// ---------------------------------------------------------------------------- -// File Name : AT91SAM7S64.h -// Object : AT91SAM7S64 definitions -// Generated : AT91 SW Application Group 07/16/2004 (07:43:09) -// -// CVS Reference : /AT91SAM7S64.pl/1.12/Mon Jul 12 13:02:30 2004// -// CVS Reference : /SYSC_SAM7Sxx.pl/1.5/Mon Jul 12 16:22:12 2004// -// CVS Reference : /MC_SAM02.pl/1.3/Wed Mar 10 08:37:04 2004// -// CVS Reference : /UDP_1765B.pl/1.3/Fri Aug 2 14:45:38 2002// -// CVS Reference : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// -// CVS Reference : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004// -// CVS Reference : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// -// CVS Reference : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003// -// CVS Reference : /US_1739C.pl/1.2/Mon Jul 12 17:26:24 2004// -// CVS Reference : /SPI2.pl/1.2/Fri Oct 17 08:13:40 2003// -// CVS Reference : /SSC_1762A.pl/1.2/Fri Nov 8 13:26:40 2002// -// CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// -// CVS Reference : /TWI_1761B.pl/1.4/Fri Feb 7 10:30:08 2003// -// CVS Reference : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:24 2002// -// CVS Reference : /ADC_SAM.pl/1.7/Fri Oct 17 08:12:38 2003// -// CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// -// ---------------------------------------------------------------------------- - -// Hardware register definition - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Peripherals -// ***************************************************************************** -// *** Register offset in AT91S_SYSC structure *** -#define SYSC_AIC_SMR ( 0) // Source Mode Register -#define SYSC_AIC_SVR (128) // Source Vector Register -#define SYSC_AIC_IVR (256) // IRQ Vector Register -#define SYSC_AIC_FVR (260) // FIQ Vector Register -#define SYSC_AIC_ISR (264) // Interrupt Status Register -#define SYSC_AIC_IPR (268) // Interrupt Pending Register -#define SYSC_AIC_IMR (272) // Interrupt Mask Register -#define SYSC_AIC_CISR (276) // Core Interrupt Status Register -#define SYSC_AIC_IECR (288) // Interrupt Enable Command Register -#define SYSC_AIC_IDCR (292) // Interrupt Disable Command Register -#define SYSC_AIC_ICCR (296) // Interrupt Clear Command Register -#define SYSC_AIC_ISCR (300) // Interrupt Set Command Register -#define SYSC_AIC_EOICR (304) // End of Interrupt Command Register -#define SYSC_AIC_SPU (308) // Spurious Vector Register -#define SYSC_AIC_DCR (312) // Debug Control Register (Protect) -#define SYSC_AIC_FFER (320) // Fast Forcing Enable Register -#define SYSC_AIC_FFDR (324) // Fast Forcing Disable Register -#define SYSC_AIC_FFSR (328) // Fast Forcing Status Register -#define SYSC_DBGU_CR (512) // Control Register -#define SYSC_DBGU_MR (516) // Mode Register -#define SYSC_DBGU_IER (520) // Interrupt Enable Register -#define SYSC_DBGU_IDR (524) // Interrupt Disable Register -#define SYSC_DBGU_IMR (528) // Interrupt Mask Register -#define SYSC_DBGU_CSR (532) // Channel Status Register -#define SYSC_DBGU_RHR (536) // Receiver Holding Register -#define SYSC_DBGU_THR (540) // Transmitter Holding Register -#define SYSC_DBGU_BRGR (544) // Baud Rate Generator Register -#define SYSC_DBGU_C1R (576) // Chip ID1 Register -#define SYSC_DBGU_C2R (580) // Chip ID2 Register -#define SYSC_DBGU_FNTR (584) // Force NTRST Register -#define SYSC_DBGU_RPR (768) // Receive Pointer Register -#define SYSC_DBGU_RCR (772) // Receive Counter Register -#define SYSC_DBGU_TPR (776) // Transmit Pointer Register -#define SYSC_DBGU_TCR (780) // Transmit Counter Register -#define SYSC_DBGU_RNPR (784) // Receive Next Pointer Register -#define SYSC_DBGU_RNCR (788) // Receive Next Counter Register -#define SYSC_DBGU_TNPR (792) // Transmit Next Pointer Register -#define SYSC_DBGU_TNCR (796) // Transmit Next Counter Register -#define SYSC_DBGU_PTCR (800) // PDC Transfer Control Register -#define SYSC_DBGU_PTSR (804) // PDC Transfer Status Register -#define SYSC_PIOA_PER (1024) // PIO Enable Register -#define SYSC_PIOA_PDR (1028) // PIO Disable Register -#define SYSC_PIOA_PSR (1032) // PIO Status Register -#define SYSC_PIOA_OER (1040) // Output Enable Register -#define SYSC_PIOA_ODR (1044) // Output Disable Registerr -#define SYSC_PIOA_OSR (1048) // Output Status Register -#define SYSC_PIOA_IFER (1056) // Input Filter Enable Register -#define SYSC_PIOA_IFDR (1060) // Input Filter Disable Register -#define SYSC_PIOA_IFSR (1064) // Input Filter Status Register -#define SYSC_PIOA_SODR (1072) // Set Output Data Register -#define SYSC_PIOA_CODR (1076) // Clear Output Data Register -#define SYSC_PIOA_ODSR (1080) // Output Data Status Register -#define SYSC_PIOA_PDSR (1084) // Pin Data Status Register -#define SYSC_PIOA_IER (1088) // Interrupt Enable Register -#define SYSC_PIOA_IDR (1092) // Interrupt Disable Register -#define SYSC_PIOA_IMR (1096) // Interrupt Mask Register -#define SYSC_PIOA_ISR (1100) // Interrupt Status Register -#define SYSC_PIOA_MDER (1104) // Multi-driver Enable Register -#define SYSC_PIOA_MDDR (1108) // Multi-driver Disable Register -#define SYSC_PIOA_MDSR (1112) // Multi-driver Status Register -#define SYSC_PIOA_PPUDR (1120) // Pull-up Disable Register -#define SYSC_PIOA_PPUER (1124) // Pull-up Enable Register -#define SYSC_PIOA_PPUSR (1128) // Pad Pull-up Status Register -#define SYSC_PIOA_ASR (1136) // Select A Register -#define SYSC_PIOA_BSR (1140) // Select B Register -#define SYSC_PIOA_ABSR (1144) // AB Select Status Register -#define SYSC_PIOA_OWER (1184) // Output Write Enable Register -#define SYSC_PIOA_OWDR (1188) // Output Write Disable Register -#define SYSC_PIOA_OWSR (1192) // Output Write Status Register -#define SYSC_PMC_SCER (3072) // System Clock Enable Register -#define SYSC_PMC_SCDR (3076) // System Clock Disable Register -#define SYSC_PMC_SCSR (3080) // System Clock Status Register -#define SYSC_PMC_PCER (3088) // Peripheral Clock Enable Register -#define SYSC_PMC_PCDR (3092) // Peripheral Clock Disable Register -#define SYSC_PMC_PCSR (3096) // Peripheral Clock Status Register -#define SYSC_PMC_MOR (3104) // Main Oscillator Register -#define SYSC_PMC_MCFR (3108) // Main Clock Frequency Register -#define SYSC_PMC_PLLR (3116) // PLL Register -#define SYSC_PMC_MCKR (3120) // Master Clock Register -#define SYSC_PMC_PCKR (3136) // Programmable Clock Register -#define SYSC_PMC_IER (3168) // Interrupt Enable Register -#define SYSC_PMC_IDR (3172) // Interrupt Disable Register -#define SYSC_PMC_SR (3176) // Status Register -#define SYSC_PMC_IMR (3180) // Interrupt Mask Register -#define SYSC_RSTC_RCR (3328) // Reset Control Register -#define SYSC_RSTC_RSR (3332) // Reset Status Register -#define SYSC_RSTC_RMR (3336) // Reset Mode Register -#define SYSC_RTTC_RTMR (3360) // Real-time Mode Register -#define SYSC_RTTC_RTAR (3364) // Real-time Alarm Register -#define SYSC_RTTC_RTVR (3368) // Real-time Value Register -#define SYSC_RTTC_RTSR (3372) // Real-time Status Register -#define SYSC_PITC_PIMR (3376) // Period Interval Mode Register -#define SYSC_PITC_PISR (3380) // Period Interval Status Register -#define SYSC_PITC_PIVR (3384) // Period Interval Value Register -#define SYSC_PITC_PIIR (3388) // Period Interval Image Register -#define SYSC_WDTC_WDCR (3392) // Watchdog Control Register -#define SYSC_WDTC_WDMR (3396) // Watchdog Mode Register -#define SYSC_WDTC_WDSR (3400) // Watchdog Status Register -#define SYSC_SYSC_VRPM (3424) // Voltage Regulator Power Mode Register -// -------- VRPM : (SYSC Offset: 0xd60) Voltage Regulator Power Mode Register -------- -#define AT91C_SYSC_PSTDBY (0x1 << 0) // (SYSC) Voltage Regulator Power Mode - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// ***************************************************************************** -// *** Register offset in AT91S_AIC structure *** -#define AIC_SMR ( 0) // Source Mode Register -#define AIC_SVR (128) // Source Vector Register -#define AIC_IVR (256) // IRQ Vector Register -#define AIC_FVR (260) // FIQ Vector Register -#define AIC_ISR (264) // Interrupt Status Register -#define AIC_IPR (268) // Interrupt Pending Register -#define AIC_IMR (272) // Interrupt Mask Register -#define AIC_CISR (276) // Core Interrupt Status Register -#define AIC_IECR (288) // Interrupt Enable Command Register -#define AIC_IDCR (292) // Interrupt Disable Command Register -#define AIC_ICCR (296) // Interrupt Clear Command Register -#define AIC_ISCR (300) // Interrupt Set Command Register -#define AIC_EOICR (304) // End of Interrupt Command Register -#define AIC_SPU (308) // Spurious Vector Register -#define AIC_DCR (312) // Debug Control Register (Protect) -#define AIC_FFER (320) // Fast Forcing Enable Register -#define AIC_FFDR (324) // Fast Forcing Disable Register -#define AIC_FFSR (328) // Fast Forcing Status Register -// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level -#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level -#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level -#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type -#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE (0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive -#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED (0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered -#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL (0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE (0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered -// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status -#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status -// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode -#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Debug Unit -// ***************************************************************************** -// *** Register offset in AT91S_DBGU structure *** -#define DBGU_CR ( 0) // Control Register -#define DBGU_MR ( 4) // Mode Register -#define DBGU_IER ( 8) // Interrupt Enable Register -#define DBGU_IDR (12) // Interrupt Disable Register -#define DBGU_IMR (16) // Interrupt Mask Register -#define DBGU_CSR (20) // Channel Status Register -#define DBGU_RHR (24) // Receiver Holding Register -#define DBGU_THR (28) // Transmitter Holding Register -#define DBGU_BRGR (32) // Baud Rate Generator Register -#define DBGU_C1R (64) // Chip ID1 Register -#define DBGU_C2R (68) // Chip ID2 Register -#define DBGU_FNTR (72) // Force NTRST Register -#define DBGU_RPR (256) // Receive Pointer Register -#define DBGU_RCR (260) // Receive Counter Register -#define DBGU_TPR (264) // Transmit Pointer Register -#define DBGU_TCR (268) // Transmit Counter Register -#define DBGU_RNPR (272) // Receive Next Pointer Register -#define DBGU_RNCR (276) // Receive Next Counter Register -#define DBGU_TNPR (280) // Transmit Next Pointer Register -#define DBGU_TNCR (284) // Transmit Next Counter Register -#define DBGU_PTCR (288) // PDC Transfer Control Register -#define DBGU_PTSR (292) // PDC Transfer Status Register -// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver -#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter -#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable -#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable -#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable -#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable -// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type -#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity -#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity -#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) -#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) -#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity -#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode -#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode -#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt -#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt -#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt -#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt -#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt -#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt -#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt -#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt -#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt -#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt -#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt -#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt -// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Peripheral Data Controller -// ***************************************************************************** -// *** Register offset in AT91S_PDC structure *** -#define PDC_RPR ( 0) // Receive Pointer Register -#define PDC_RCR ( 4) // Receive Counter Register -#define PDC_TPR ( 8) // Transmit Pointer Register -#define PDC_TCR (12) // Transmit Counter Register -#define PDC_RNPR (16) // Receive Next Pointer Register -#define PDC_RNCR (20) // Receive Next Counter Register -#define PDC_TNPR (24) // Transmit Next Pointer Register -#define PDC_TNCR (28) // Transmit Next Counter Register -#define PDC_PTCR (32) // PDC Transfer Control Register -#define PDC_PTSR (36) // PDC Transfer Status Register -// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable -#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable -#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable -#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable -// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// ***************************************************************************** -// *** Register offset in AT91S_PIO structure *** -#define PIO_PER ( 0) // PIO Enable Register -#define PIO_PDR ( 4) // PIO Disable Register -#define PIO_PSR ( 8) // PIO Status Register -#define PIO_OER (16) // Output Enable Register -#define PIO_ODR (20) // Output Disable Registerr -#define PIO_OSR (24) // Output Status Register -#define PIO_IFER (32) // Input Filter Enable Register -#define PIO_IFDR (36) // Input Filter Disable Register -#define PIO_IFSR (40) // Input Filter Status Register -#define PIO_SODR (48) // Set Output Data Register -#define PIO_CODR (52) // Clear Output Data Register -#define PIO_ODSR (56) // Output Data Status Register -#define PIO_PDSR (60) // Pin Data Status Register -#define PIO_IER (64) // Interrupt Enable Register -#define PIO_IDR (68) // Interrupt Disable Register -#define PIO_IMR (72) // Interrupt Mask Register -#define PIO_ISR (76) // Interrupt Status Register -#define PIO_MDER (80) // Multi-driver Enable Register -#define PIO_MDDR (84) // Multi-driver Disable Register -#define PIO_MDSR (88) // Multi-driver Status Register -#define PIO_PPUDR (96) // Pull-up Disable Register -#define PIO_PPUER (100) // Pull-up Enable Register -#define PIO_PPUSR (104) // Pad Pull-up Status Register -#define PIO_ASR (112) // Select A Register -#define PIO_BSR (116) // Select B Register -#define PIO_ABSR (120) // AB Select Status Register -#define PIO_OWER (160) // Output Write Enable Register -#define PIO_OWDR (164) // Output Write Disable Register -#define PIO_OWSR (168) // Output Write Status Register - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Clock Generator Controler -// ***************************************************************************** -// *** Register offset in AT91S_CKGR structure *** -#define CKGR_MOR ( 0) // Main Oscillator Register -#define CKGR_MCFR ( 4) // Main Clock Frequency Register -#define CKGR_PLLR (12) // PLL Register -// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable -#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass -#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time -// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency -#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready -// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- -#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter -#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range -#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier -#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks -#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output -#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 -#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Power Management Controler -// ***************************************************************************** -// *** Register offset in AT91S_PMC structure *** -#define PMC_SCER ( 0) // System Clock Enable Register -#define PMC_SCDR ( 4) // System Clock Disable Register -#define PMC_SCSR ( 8) // System Clock Status Register -#define PMC_PCER (16) // Peripheral Clock Enable Register -#define PMC_PCDR (20) // Peripheral Clock Disable Register -#define PMC_PCSR (24) // Peripheral Clock Status Register -#define PMC_MOR (32) // Main Oscillator Register -#define PMC_MCFR (36) // Main Clock Frequency Register -#define PMC_PLLR (44) // PLL Register -#define PMC_MCKR (48) // Master Clock Register -#define PMC_PCKR (64) // Programmable Clock Register -#define PMC_IER (96) // Interrupt Enable Register -#define PMC_IDR (100) // Interrupt Disable Register -#define PMC_SR (104) // Status Register -#define PMC_IMR (108) // Interrupt Mask Register -// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock -#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock -#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output -// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- -// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- -// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- -// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection -#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected -#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected -#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected -#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler -#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock -#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 -#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 -#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 -#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 -#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 -#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 -// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask -#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask -#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask -// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Reset Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_RSTC structure *** -#define RSTC_RCR ( 0) // Reset Control Register -#define RSTC_RSR ( 4) // Reset Status Register -#define RSTC_RMR ( 8) // Reset Mode Register -// -------- SYSC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- -#define AT91C_SYSC_PROCRST (0x1 << 0) // (RSTC) Processor Reset -#define AT91C_SYSC_ICERST (0x1 << 1) // (RSTC) ICE Interface Reset -#define AT91C_SYSC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset -#define AT91C_SYSC_EXTRST (0x1 << 3) // (RSTC) External Reset -#define AT91C_SYSC_KEY (0xFF << 24) // (RSTC) Password -// -------- SYSC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- -#define AT91C_SYSC_URSTS (0x1 << 0) // (RSTC) User Reset Status -#define AT91C_SYSC_BODSTS (0x1 << 1) // (RSTC) Brown-out Detection Status -#define AT91C_SYSC_RSTTYP (0x7 << 8) // (RSTC) Reset Type -#define AT91C_SYSC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. -#define AT91C_SYSC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. -#define AT91C_SYSC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. -#define AT91C_SYSC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. -#define AT91C_SYSC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brown-out Reset. -#define AT91C_SYSC_NRSTL (0x1 << 16) // (RSTC) NRST pin level -#define AT91C_SYSC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. -// -------- SYSC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- -#define AT91C_SYSC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable -#define AT91C_SYSC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable -#define AT91C_SYSC_ERSTL (0xF << 8) // (RSTC) User Reset Enable -#define AT91C_SYSC_BODIEN (0x1 << 16) // (RSTC) Brown-out Detection Interrupt Enable - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_RTTC structure *** -#define RTTC_RTMR ( 0) // Real-time Mode Register -#define RTTC_RTAR ( 4) // Real-time Alarm Register -#define RTTC_RTVR ( 8) // Real-time Value Register -#define RTTC_RTSR (12) // Real-time Status Register -// -------- SYSC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- -#define AT91C_SYSC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value -#define AT91C_SYSC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable -#define AT91C_SYSC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable -#define AT91C_SYSC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart -// -------- SYSC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- -#define AT91C_SYSC_ALMV (0x0 << 0) // (RTTC) Alarm Value -// -------- SYSC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- -#define AT91C_SYSC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value -// -------- SYSC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- -#define AT91C_SYSC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status -#define AT91C_SYSC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_PITC structure *** -#define PITC_PIMR ( 0) // Period Interval Mode Register -#define PITC_PISR ( 4) // Period Interval Status Register -#define PITC_PIVR ( 8) // Period Interval Value Register -#define PITC_PIIR (12) // Period Interval Image Register -// -------- SYSC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- -#define AT91C_SYSC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value -#define AT91C_SYSC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled -#define AT91C_SYSC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable -// -------- SYSC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- -#define AT91C_SYSC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status -// -------- SYSC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- -#define AT91C_SYSC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value -#define AT91C_SYSC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter -// -------- SYSC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_WDTC structure *** -#define WDTC_WDCR ( 0) // Watchdog Control Register -#define WDTC_WDMR ( 4) // Watchdog Mode Register -#define WDTC_WDSR ( 8) // Watchdog Status Register -// -------- SYSC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- -#define AT91C_SYSC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart -// -------- SYSC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- -#define AT91C_SYSC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart -#define AT91C_SYSC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable -#define AT91C_SYSC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable -#define AT91C_SYSC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart -#define AT91C_SYSC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable -#define AT91C_SYSC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value -#define AT91C_SYSC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt -#define AT91C_SYSC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt -// -------- SYSC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- -#define AT91C_SYSC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow -#define AT91C_SYSC_WDERR (0x1 << 1) // (WDTC) Watchdog Error - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Memory Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_MC structure *** -#define MC_RCR ( 0) // MC Remap Control Register -#define MC_ASR ( 4) // MC Abort Status Register -#define MC_AASR ( 8) // MC Abort Address Status Register -#define MC_FMR (96) // MC Flash Mode Register -#define MC_FCR (100) // MC Flash Command Register -#define MC_FSR (104) // MC Flash Status Register -// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit -// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status -#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status -#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status -#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte -#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word -#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word -#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status -#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read -#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write -#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch -#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source -#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source -#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source -#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source -// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- -#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready -#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error -#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error -#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming -#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State -#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations -#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations -#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations -#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations -#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number -// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- -#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command -#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN. -#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. -#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. -#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits. -#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits. -#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit. -#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number -#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key -// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- -#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status -#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status -#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status -#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status -#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status -#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status -#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status -#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status -#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status -#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status -#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status -#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status -#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status -#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status -#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status -#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status -#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status -#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status -#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status -#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status -#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status -#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status -#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Serial Parallel Interface -// ***************************************************************************** -// *** Register offset in AT91S_SPI structure *** -#define SPI_CR ( 0) // Control Register -#define SPI_MR ( 4) // Mode Register -#define SPI_RDR ( 8) // Receive Data Register -#define SPI_TDR (12) // Transmit Data Register -#define SPI_SR (16) // Status Register -#define SPI_IER (20) // Interrupt Enable Register -#define SPI_IDR (24) // Interrupt Disable Register -#define SPI_IMR (28) // Interrupt Mask Register -#define SPI_CSR (48) // Chip Select Register -#define SPI_RPR (256) // Receive Pointer Register -#define SPI_RCR (260) // Receive Counter Register -#define SPI_TPR (264) // Transmit Pointer Register -#define SPI_TCR (268) // Transmit Counter Register -#define SPI_RNPR (272) // Receive Next Pointer Register -#define SPI_RNCR (276) // Receive Next Counter Register -#define SPI_TNPR (280) // Transmit Next Pointer Register -#define SPI_TNCR (284) // Transmit Next Counter Register -#define SPI_PTCR (288) // PDC Transfer Control Register -#define SPI_PTSR (292) // PDC Transfer Status Register -// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable -#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable -#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset -#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer -// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode -#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select -#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select -#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select -#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode -#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection -#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection -#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection -#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select -#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects -// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data -#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data -#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full -#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty -#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error -#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status -#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer -#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer -#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt -#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt -#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt -#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt -#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status -// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity -#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase -#define AT91C_SPI_CSAAT (0x1 << 2) // (SPI) Chip Select Active After Transfer -#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer -#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer -#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer -#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer -#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer -#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer -#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer -#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer -#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer -#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer -#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Analog to Digital Convertor -// ***************************************************************************** -// *** Register offset in AT91S_ADC structure *** -#define ADC_CR ( 0) // ADC Control Register -#define ADC_MR ( 4) // ADC Mode Register -#define ADC_CHER (16) // ADC Channel Enable Register -#define ADC_CHDR (20) // ADC Channel Disable Register -#define ADC_CHSR (24) // ADC Channel Status Register -#define ADC_SR (28) // ADC Status Register -#define ADC_LCDR (32) // ADC Last Converted Data Register -#define ADC_IER (36) // ADC Interrupt Enable Register -#define ADC_IDR (40) // ADC Interrupt Disable Register -#define ADC_IMR (44) // ADC Interrupt Mask Register -#define ADC_CDR0 (48) // ADC Channel Data Register 0 -#define ADC_CDR1 (52) // ADC Channel Data Register 1 -#define ADC_CDR2 (56) // ADC Channel Data Register 2 -#define ADC_CDR3 (60) // ADC Channel Data Register 3 -#define ADC_CDR4 (64) // ADC Channel Data Register 4 -#define ADC_CDR5 (68) // ADC Channel Data Register 5 -#define ADC_CDR6 (72) // ADC Channel Data Register 6 -#define ADC_CDR7 (76) // ADC Channel Data Register 7 -#define ADC_RPR (256) // Receive Pointer Register -#define ADC_RCR (260) // Receive Counter Register -#define ADC_TPR (264) // Transmit Pointer Register -#define ADC_TCR (268) // Transmit Counter Register -#define ADC_RNPR (272) // Receive Next Pointer Register -#define ADC_RNCR (276) // Receive Next Counter Register -#define ADC_TNPR (280) // Transmit Next Pointer Register -#define ADC_TNCR (284) // Transmit Next Counter Register -#define ADC_PTCR (288) // PDC Transfer Control Register -#define ADC_PTSR (292) // PDC Transfer Status Register -// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- -#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset -#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion -// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- -#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable -#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software -#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. -#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection -#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 -#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 -#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 -#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 -#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 -#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 -#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger -#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. -#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution -#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution -#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode -#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection -#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time -#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time -// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- -#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 -#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 -#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 -#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 -#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 -#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 -#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 -#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 -// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- -// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- -// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- -#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion -#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion -#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion -#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion -#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion -#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion -#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion -#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion -#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error -#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error -#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error -#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error -#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error -#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error -#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error -#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error -#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready -#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun -#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer -#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt -// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- -#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted -// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- -// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- -// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- -// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- -#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data -// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- -// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- -// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- -// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- -// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- -// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- -// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_SSC structure *** -#define SSC_CR ( 0) // Control Register -#define SSC_CMR ( 4) // Clock Mode Register -#define SSC_RCMR (16) // Receive Clock ModeRegister -#define SSC_RFMR (20) // Receive Frame Mode Register -#define SSC_TCMR (24) // Transmit Clock Mode Register -#define SSC_TFMR (28) // Transmit Frame Mode Register -#define SSC_RHR (32) // Receive Holding Register -#define SSC_THR (36) // Transmit Holding Register -#define SSC_RSHR (48) // Receive Sync Holding Register -#define SSC_TSHR (52) // Transmit Sync Holding Register -#define SSC_RC0R (56) // Receive Compare 0 Register -#define SSC_RC1R (60) // Receive Compare 1 Register -#define SSC_SR (64) // Status Register -#define SSC_IER (68) // Interrupt Enable Register -#define SSC_IDR (72) // Interrupt Disable Register -#define SSC_IMR (76) // Interrupt Mask Register -#define SSC_RPR (256) // Receive Pointer Register -#define SSC_RCR (260) // Receive Counter Register -#define SSC_TPR (264) // Transmit Pointer Register -#define SSC_TCR (268) // Transmit Counter Register -#define SSC_RNPR (272) // Receive Next Pointer Register -#define SSC_RNCR (276) // Receive Next Counter Register -#define SSC_TNPR (280) // Transmit Next Pointer Register -#define SSC_TNCR (284) // Transmit Next Counter Register -#define SSC_PTCR (288) // PDC Transfer Control Register -#define SSC_PTSR (292) // PDC Transfer Status Register -// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable -#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable -#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable -#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable -#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset -// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection -#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock -#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal -#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin -#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection -#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output -#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion -#define AT91C_SSC_CKG (0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection -#define AT91C_SSC_CKG_NONE (0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock -#define AT91C_SSC_CKG_LOW (0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low -#define AT91C_SSC_CKG_HIGH (0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High -#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection -#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start -#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input -#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input -#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input -#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input -#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input -#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input -#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 -#define AT91C_SSC_STOP (0x1 << 12) // (SSC) Receive Stop Selection -#define AT91C_SSC_STTOUT (0x1 << 15) // (SSC) Receive/Transmit Start Output Selection -#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay -#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection -// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length -#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode -#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First -#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame -#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length -#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection -#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection -// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value -#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable -// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready -#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty -#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission -#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty -#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready -#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun -#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception -#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full -#define AT91C_SSC_CP0 (0x1 << 8) // (SSC) Compare 0 -#define AT91C_SSC_CP1 (0x1 << 9) // (SSC) Compare 1 -#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync -#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync -#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable -#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable -// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Usart -// ***************************************************************************** -// *** Register offset in AT91S_USART structure *** -#define US_CR ( 0) // Control Register -#define US_MR ( 4) // Mode Register -#define US_IER ( 8) // Interrupt Enable Register -#define US_IDR (12) // Interrupt Disable Register -#define US_IMR (16) // Interrupt Mask Register -#define US_CSR (20) // Channel Status Register -#define US_RHR (24) // Receiver Holding Register -#define US_THR (28) // Transmitter Holding Register -#define US_BRGR (32) // Baud Rate Generator Register -#define US_RTOR (36) // Receiver Time-out Register -#define US_TTGR (40) // Transmitter Time-guard Register -#define US_FIDI (64) // FI_DI_Ratio Register -#define US_NER (68) // Nb Errors Register -#define US_XXR (72) // XON_XOFF Register -#define US_IF (76) // IRDA_FILTER Register -#define US_RPR (256) // Receive Pointer Register -#define US_RCR (260) // Receive Counter Register -#define US_TPR (264) // Transmit Pointer Register -#define US_TCR (268) // Transmit Counter Register -#define US_RNPR (272) // Receive Next Pointer Register -#define US_RNCR (276) // Receive Next Counter Register -#define US_TNPR (280) // Transmit Next Pointer Register -#define US_TNCR (284) // Transmit Next Counter Register -#define US_PTCR (288) // PDC Transfer Control Register -#define US_PTSR (292) // PDC Transfer Status Register -// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTSTA (0x1 << 8) // (USART) Reset Status Bits -#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break -#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break -#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out -#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address -#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations -#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge -#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out -#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable -#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable -#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable -#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable -// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode -#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal -#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 -#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking -#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem -#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 -#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 -#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA -#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking -#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock -#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 -#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) -#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) -#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits -#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits -#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits -#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits -#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select -#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits -#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit -#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits -#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order -#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length -#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select -#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode -#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge -#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK -#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions -#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter -// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break -#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out -#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached -#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge -#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag -#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag -#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag -#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag -// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input -#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input -#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input -#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Two-wire Interface -// ***************************************************************************** -// *** Register offset in AT91S_TWI structure *** -#define TWI_CR ( 0) // Control Register -#define TWI_MMR ( 4) // Master Mode Register -#define TWI_SMR ( 8) // Slave Mode Register -#define TWI_IADR (12) // Internal Address Register -#define TWI_CWGR (16) // Clock Waveform Generator Register -#define TWI_SR (32) // Status Register -#define TWI_IER (36) // Interrupt Enable Register -#define TWI_IDR (40) // Interrupt Disable Register -#define TWI_IMR (44) // Interrupt Mask Register -#define TWI_RHR (48) // Receive Holding Register -#define TWI_THR (52) // Transmit Holding Register -// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition -#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition -#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled -#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled -#define AT91C_TWI_SVEN (0x1 << 4) // (TWI) TWI Slave Transfer Enabled -#define AT91C_TWI_SVDIS (0x1 << 5) // (TWI) TWI Slave Transfer Disabled -#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset -// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size -#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address -#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address -#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address -#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address -#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction -#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address -// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- -#define AT91C_TWI_SADR (0x7F << 16) // (TWI) Slave Device Address -// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider -#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider -#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider -// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed -#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY -#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY -#define AT91C_TWI_SVREAD (0x1 << 3) // (TWI) Slave Read -#define AT91C_TWI_SVACC (0x1 << 4) // (TWI) Slave Access -#define AT91C_TWI_GCACC (0x1 << 5) // (TWI) General Call Access -#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error -#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error -#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged -#define AT91C_TWI_ARBLST (0x1 << 9) // (TWI) Arbitration Lost -// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// ***************************************************************************** -// *** Register offset in AT91S_TC structure *** -#define TC_CCR ( 0) // Channel Control Register -#define TC_CMR ( 4) // Channel Mode Register (Capture Mode / Waveform Mode) -#define TC_CV (16) // Counter Value -#define TC_RA (20) // Register A -#define TC_RB (24) // Register B -#define TC_RC (28) // Register C -#define TC_SR (32) // Status Register -#define TC_IER (36) // Interrupt Enable Register -#define TC_IDR (40) // Interrupt Disable Register -#define TC_IMR (44) // Interrupt Mask Register -// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command -#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command -#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command -// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection -#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK -#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 -#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 -#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 -#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert -#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection -#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal -#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock -#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock -#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock -#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare -#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading -#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading -#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare -#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection -#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None -#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection -#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None -#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection -#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection -#define AT91C_TC_EEVT_NONE (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input -#define AT91C_TC_EEVT_RISING (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output -#define AT91C_TC_EEVT_FALLING (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output -#define AT91C_TC_EEVT_BOTH (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output -#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable -#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection -#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare -#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable -#define AT91C_TC_WAVE (0x1 << 15) // (TC) -#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection -#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None -#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA -#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA -#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none -#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set -#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear -#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle -#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection -#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None -#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA -#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA -#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none -#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set -#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear -#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle -#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA -#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none -#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set -#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear -#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle -#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA -#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none -#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set -#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear -#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle -#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB -#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none -#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set -#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear -#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle -#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB -#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none -#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set -#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear -#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle -#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB -#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none -#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set -#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear -#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle -#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB -#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none -#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set -#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear -#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle -// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow -#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun -#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare -#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare -#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare -#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading -#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading -#define AT91C_TC_ETRCS (0x1 << 7) // (TC) External Trigger -#define AT91C_TC_ETRGS (0x1 << 16) // (TC) Clock Enabling -#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror -#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror -// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Interface -// ***************************************************************************** -// *** Register offset in AT91S_TCB structure *** -#define TCB_TC0 ( 0) // TC Channel 0 -#define TCB_TC1 (64) // TC Channel 1 -#define TCB_TC2 (128) // TC Channel 2 -#define TCB_BCR (192) // TC Block Control Register -#define TCB_BMR (196) // TC Block Mode Register -// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command -// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -#define AT91C_TCB_TC0XC0S (0x1 << 0) // (TCB) External Clock Signal 0 Selection -#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 -#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 -#define AT91C_TCB_TC1XC1S (0x1 << 2) // (TCB) External Clock Signal 1 Selection -#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 -#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 -#define AT91C_TCB_TC2XC2S (0x1 << 4) // (TCB) External Clock Signal 2 Selection -#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 -#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA2 (0x3 << 4) // (TCB) TIOA2 connected to XC2 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR PWMC Channel Interface -// ***************************************************************************** -// *** Register offset in AT91S_PWMC_CH structure *** -#define PWMC_CMR ( 0) // Channel Mode Register -#define PWMC_CDTYR ( 4) // Channel Duty Cycle Register -#define PWMC_CPRDR ( 8) // Channel Period Register -#define PWMC_CCNTR (12) // Channel Counter Register -#define PWMC_CUPDR (16) // Channel Update Register -#define PWMC_Reserved (20) // Reserved -// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- -#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx -#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) -#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment -#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity -#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period -// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- -#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle -// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- -#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period -// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- -#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter -// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- -#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_PWMC structure *** -#define PWMC_MR ( 0) // PWMC Mode Register -#define PWMC_ENA ( 4) // PWMC Enable Register -#define PWMC_DIS ( 8) // PWMC Disable Register -#define PWMC_SR (12) // PWMC Status Register -#define PWMC_IER (16) // PWMC Interrupt Enable Register -#define PWMC_IDR (20) // PWMC Interrupt Disable Register -#define PWMC_IMR (24) // PWMC Interrupt Mask Register -#define PWMC_ISR (28) // PWMC Interrupt Status Register -#define PWMC_VR (252) // PWMC Version Register -#define PWMC_CH (512) // PWMC Channel 0 -// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- -#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. -#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A -#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) -#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. -#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B -#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) -// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- -#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 -#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 -#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 -#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 -#define AT91C_PWMC_CHID4 (0x1 << 4) // (PWMC) Channel ID 4 -#define AT91C_PWMC_CHID5 (0x1 << 5) // (PWMC) Channel ID 5 -#define AT91C_PWMC_CHID6 (0x1 << 6) // (PWMC) Channel ID 6 -#define AT91C_PWMC_CHID7 (0x1 << 7) // (PWMC) Channel ID 7 -// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- -// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- -// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- -// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- -// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- -// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Device Interface -// ***************************************************************************** -// *** Register offset in AT91S_UDP structure *** -#define UDP_NUM ( 0) // Frame Number Register -#define UDP_GLBSTATE ( 4) // Global State Register -#define UDP_FADDR ( 8) // Function Address Register -#define UDP_IER (16) // Interrupt Enable Register -#define UDP_IDR (20) // Interrupt Disable Register -#define UDP_IMR (24) // Interrupt Mask Register -#define UDP_ISR (28) // Interrupt Status Register -#define UDP_ICR (32) // Interrupt Clear Register -#define UDP_RSTEP (40) // Reset Endpoint Register -#define UDP_CSR (48) // Endpoint Control and Status Register -#define UDP_FDR (80) // Endpoint FIFO Data Register -// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats -#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error -#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK -// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable -#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured -#define AT91C_UDP_RMWUPE (0x1 << 2) // (UDP) Remote Wake Up Enable -#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host -// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value -#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable -// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt -#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt -#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt -#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt -#define AT91C_UDP_EPINT6 (0x1 << 6) // (UDP) Endpoint 6 Interrupt -#define AT91C_UDP_EPINT7 (0x1 << 7) // (UDP) Endpoint 7 Interrupt -#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt -#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt -#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt -#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt -#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt -// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt -// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 -#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 -#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 -#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 -#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4 -#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5 -#define AT91C_UDP_EP6 (0x1 << 6) // (UDP) Reset Endpoint 6 -#define AT91C_UDP_EP7 (0x1 << 7) // (UDP) Reset Endpoint 7 -// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR -#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 -#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) -#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) -#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready -#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction -#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type -#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control -#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT -#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT -#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT -#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN -#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN -#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN -#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle -#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable -#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO - -// ***************************************************************************** -// REGISTER ADDRESS DEFINITION FOR AT91SAM7S64 -// ***************************************************************************** -// ========== Register definition for SYSC peripheral ========== -#define AT91C_SYSC_SYSC_VRPM (0xFFFFFD60) // (SYSC) Voltage Regulator Power Mode Register -// ========== Register definition for AIC peripheral ========== -#define AT91C_AIC_ICCR (0xFFFFF128) // (AIC) Interrupt Clear Command Register -#define AT91C_AIC_IECR (0xFFFFF120) // (AIC) Interrupt Enable Command Register -#define AT91C_AIC_SMR (0xFFFFF000) // (AIC) Source Mode Register -#define AT91C_AIC_ISCR (0xFFFFF12C) // (AIC) Interrupt Set Command Register -#define AT91C_AIC_EOICR (0xFFFFF130) // (AIC) End of Interrupt Command Register -#define AT91C_AIC_DCR (0xFFFFF138) // (AIC) Debug Control Register (Protect) -#define AT91C_AIC_FFER (0xFFFFF140) // (AIC) Fast Forcing Enable Register -#define AT91C_AIC_SVR (0xFFFFF080) // (AIC) Source Vector Register -#define AT91C_AIC_SPU (0xFFFFF134) // (AIC) Spurious Vector Register -#define AT91C_AIC_FFDR (0xFFFFF144) // (AIC) Fast Forcing Disable Register -#define AT91C_AIC_FVR (0xFFFFF104) // (AIC) FIQ Vector Register -#define AT91C_AIC_FFSR (0xFFFFF148) // (AIC) Fast Forcing Status Register -#define AT91C_AIC_IMR (0xFFFFF110) // (AIC) Interrupt Mask Register -#define AT91C_AIC_ISR (0xFFFFF108) // (AIC) Interrupt Status Register -#define AT91C_AIC_IVR (0xFFFFF100) // (AIC) IRQ Vector Register -#define AT91C_AIC_IDCR (0xFFFFF124) // (AIC) Interrupt Disable Command Register -#define AT91C_AIC_CISR (0xFFFFF114) // (AIC) Core Interrupt Status Register -#define AT91C_AIC_IPR (0xFFFFF10C) // (AIC) Interrupt Pending Register -// ========== Register definition for DBGU peripheral ========== -#define AT91C_DBGU_C2R (0xFFFFF244) // (DBGU) Chip ID2 Register -#define AT91C_DBGU_THR (0xFFFFF21C) // (DBGU) Transmitter Holding Register -#define AT91C_DBGU_CSR (0xFFFFF214) // (DBGU) Channel Status Register -#define AT91C_DBGU_IDR (0xFFFFF20C) // (DBGU) Interrupt Disable Register -#define AT91C_DBGU_MR (0xFFFFF204) // (DBGU) Mode Register -#define AT91C_DBGU_FNTR (0xFFFFF248) // (DBGU) Force NTRST Register -#define AT91C_DBGU_C1R (0xFFFFF240) // (DBGU) Chip ID1 Register -#define AT91C_DBGU_BRGR (0xFFFFF220) // (DBGU) Baud Rate Generator Register -#define AT91C_DBGU_RHR (0xFFFFF218) // (DBGU) Receiver Holding Register -#define AT91C_DBGU_IMR (0xFFFFF210) // (DBGU) Interrupt Mask Register -#define AT91C_DBGU_IER (0xFFFFF208) // (DBGU) Interrupt Enable Register -#define AT91C_DBGU_CR (0xFFFFF200) // (DBGU) Control Register -// ========== Register definition for PDC_DBGU peripheral ========== -#define AT91C_DBGU_TNCR (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register -#define AT91C_DBGU_RNCR (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register -#define AT91C_DBGU_PTCR (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register -#define AT91C_DBGU_PTSR (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register -#define AT91C_DBGU_RCR (0xFFFFF304) // (PDC_DBGU) Receive Counter Register -#define AT91C_DBGU_TCR (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register -#define AT91C_DBGU_RPR (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register -#define AT91C_DBGU_TPR (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register -#define AT91C_DBGU_RNPR (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register -#define AT91C_DBGU_TNPR (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register -// ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_IMR (0xFFFFF448) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_IER (0xFFFFF440) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_OWDR (0xFFFFF4A4) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_ISR (0xFFFFF44C) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_PPUDR (0xFFFFF460) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_MDSR (0xFFFFF458) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_MDER (0xFFFFF450) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PER (0xFFFFF400) // (PIOA) PIO Enable Register -#define AT91C_PIOA_PSR (0xFFFFF408) // (PIOA) PIO Status Register -#define AT91C_PIOA_OER (0xFFFFF410) // (PIOA) Output Enable Register -#define AT91C_PIOA_BSR (0xFFFFF474) // (PIOA) Select B Register -#define AT91C_PIOA_PPUER (0xFFFFF464) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_MDDR (0xFFFFF454) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_PDR (0xFFFFF404) // (PIOA) PIO Disable Register -#define AT91C_PIOA_ODR (0xFFFFF414) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_IFDR (0xFFFFF424) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_ABSR (0xFFFFF478) // (PIOA) AB Select Status Register -#define AT91C_PIOA_ASR (0xFFFFF470) // (PIOA) Select A Register -#define AT91C_PIOA_PPUSR (0xFFFFF468) // (PIOA) Pad Pull-up Status Register -#define AT91C_PIOA_ODSR (0xFFFFF438) // (PIOA) Output Data Status Register -#define AT91C_PIOA_SODR (0xFFFFF430) // (PIOA) Set Output Data Register -#define AT91C_PIOA_IFSR (0xFFFFF428) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_IFER (0xFFFFF420) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_OSR (0xFFFFF418) // (PIOA) Output Status Register -#define AT91C_PIOA_IDR (0xFFFFF444) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_PDSR (0xFFFFF43C) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_CODR (0xFFFFF434) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_OWSR (0xFFFFF4A8) // (PIOA) Output Write Status Register -#define AT91C_PIOA_OWER (0xFFFFF4A0) // (PIOA) Output Write Enable Register -// ========== Register definition for CKGR peripheral ========== -#define AT91C_CKGR_PLLR (0xFFFFFC2C) // (CKGR) PLL Register -#define AT91C_CKGR_MCFR (0xFFFFFC24) // (CKGR) Main Clock Frequency Register -#define AT91C_CKGR_MOR (0xFFFFFC20) // (CKGR) Main Oscillator Register -// ========== Register definition for PMC peripheral ========== -#define AT91C_PMC_SCSR (0xFFFFFC08) // (PMC) System Clock Status Register -#define AT91C_PMC_SCER (0xFFFFFC00) // (PMC) System Clock Enable Register -#define AT91C_PMC_IMR (0xFFFFFC6C) // (PMC) Interrupt Mask Register -#define AT91C_PMC_IDR (0xFFFFFC64) // (PMC) Interrupt Disable Register -#define AT91C_PMC_PCDR (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register -#define AT91C_PMC_SCDR (0xFFFFFC04) // (PMC) System Clock Disable Register -#define AT91C_PMC_SR (0xFFFFFC68) // (PMC) Status Register -#define AT91C_PMC_IER (0xFFFFFC60) // (PMC) Interrupt Enable Register -#define AT91C_PMC_MCKR (0xFFFFFC30) // (PMC) Master Clock Register -#define AT91C_PMC_MOR (0xFFFFFC20) // (PMC) Main Oscillator Register -#define AT91C_PMC_PCER (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register -#define AT91C_PMC_PCSR (0xFFFFFC18) // (PMC) Peripheral Clock Status Register -#define AT91C_PMC_PLLR (0xFFFFFC2C) // (PMC) PLL Register -#define AT91C_PMC_MCFR (0xFFFFFC24) // (PMC) Main Clock Frequency Register -#define AT91C_PMC_PCKR (0xFFFFFC40) // (PMC) Programmable Clock Register -// ========== Register definition for RSTC peripheral ========== -#define AT91C_RSTC_RSR (0xFFFFFD04) // (RSTC) Reset Status Register -#define AT91C_RSTC_RMR (0xFFFFFD08) // (RSTC) Reset Mode Register -#define AT91C_RSTC_RCR (0xFFFFFD00) // (RSTC) Reset Control Register -// ========== Register definition for RTTC peripheral ========== -#define AT91C_RTTC_RTSR (0xFFFFFD2C) // (RTTC) Real-time Status Register -#define AT91C_RTTC_RTAR (0xFFFFFD24) // (RTTC) Real-time Alarm Register -#define AT91C_RTTC_RTVR (0xFFFFFD28) // (RTTC) Real-time Value Register -#define AT91C_RTTC_RTMR (0xFFFFFD20) // (RTTC) Real-time Mode Register -// ========== Register definition for PITC peripheral ========== -#define AT91C_PITC_PIIR (0xFFFFFD3C) // (PITC) Period Interval Image Register -#define AT91C_PITC_PISR (0xFFFFFD34) // (PITC) Period Interval Status Register -#define AT91C_PITC_PIVR (0xFFFFFD38) // (PITC) Period Interval Value Register -#define AT91C_PITC_PIMR (0xFFFFFD30) // (PITC) Period Interval Mode Register -// ========== Register definition for WDTC peripheral ========== -#define AT91C_WDTC_WDMR (0xFFFFFD44) // (WDTC) Watchdog Mode Register -#define AT91C_WDTC_WDSR (0xFFFFFD48) // (WDTC) Watchdog Status Register -#define AT91C_WDTC_WDCR (0xFFFFFD40) // (WDTC) Watchdog Control Register -// ========== Register definition for MC peripheral ========== -#define AT91C_MC_FCR (0xFFFFFF64) // (MC) MC Flash Command Register -#define AT91C_MC_ASR (0xFFFFFF04) // (MC) MC Abort Status Register -#define AT91C_MC_FSR (0xFFFFFF68) // (MC) MC Flash Status Register -#define AT91C_MC_FMR (0xFFFFFF60) // (MC) MC Flash Mode Register -#define AT91C_MC_AASR (0xFFFFFF08) // (MC) MC Abort Address Status Register -#define AT91C_MC_RCR (0xFFFFFF00) // (MC) MC Remap Control Register -// ========== Register definition for PDC_SPI peripheral ========== -#define AT91C_SPI_PTCR (0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register -#define AT91C_SPI_TNPR (0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register -#define AT91C_SPI_RNPR (0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register -#define AT91C_SPI_TPR (0xFFFE0108) // (PDC_SPI) Transmit Pointer Register -#define AT91C_SPI_RPR (0xFFFE0100) // (PDC_SPI) Receive Pointer Register -#define AT91C_SPI_PTSR (0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register -#define AT91C_SPI_TNCR (0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register -#define AT91C_SPI_RNCR (0xFFFE0114) // (PDC_SPI) Receive Next Counter Register -#define AT91C_SPI_TCR (0xFFFE010C) // (PDC_SPI) Transmit Counter Register -#define AT91C_SPI_RCR (0xFFFE0104) // (PDC_SPI) Receive Counter Register -// ========== Register definition for SPI peripheral ========== -#define AT91C_SPI_CSR (0xFFFE0030) // (SPI) Chip Select Register -#define AT91C_SPI_IDR (0xFFFE0018) // (SPI) Interrupt Disable Register -#define AT91C_SPI_SR (0xFFFE0010) // (SPI) Status Register -#define AT91C_SPI_RDR (0xFFFE0008) // (SPI) Receive Data Register -#define AT91C_SPI_CR (0xFFFE0000) // (SPI) Control Register -#define AT91C_SPI_IMR (0xFFFE001C) // (SPI) Interrupt Mask Register -#define AT91C_SPI_IER (0xFFFE0014) // (SPI) Interrupt Enable Register -#define AT91C_SPI_TDR (0xFFFE000C) // (SPI) Transmit Data Register -#define AT91C_SPI_MR (0xFFFE0004) // (SPI) Mode Register -// ========== Register definition for PDC_ADC peripheral ========== -#define AT91C_ADC_PTCR (0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register -#define AT91C_ADC_TNPR (0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register -#define AT91C_ADC_RNPR (0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register -#define AT91C_ADC_TPR (0xFFFD8108) // (PDC_ADC) Transmit Pointer Register -#define AT91C_ADC_RPR (0xFFFD8100) // (PDC_ADC) Receive Pointer Register -#define AT91C_ADC_PTSR (0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register -#define AT91C_ADC_TNCR (0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register -#define AT91C_ADC_RNCR (0xFFFD8114) // (PDC_ADC) Receive Next Counter Register -#define AT91C_ADC_TCR (0xFFFD810C) // (PDC_ADC) Transmit Counter Register -#define AT91C_ADC_RCR (0xFFFD8104) // (PDC_ADC) Receive Counter Register -// ========== Register definition for ADC peripheral ========== -#define AT91C_ADC_IMR (0xFFFD802C) // (ADC) ADC Interrupt Mask Register -#define AT91C_ADC_CDR4 (0xFFFD8040) // (ADC) ADC Channel Data Register 4 -#define AT91C_ADC_CDR2 (0xFFFD8038) // (ADC) ADC Channel Data Register 2 -#define AT91C_ADC_CDR0 (0xFFFD8030) // (ADC) ADC Channel Data Register 0 -#define AT91C_ADC_CDR7 (0xFFFD804C) // (ADC) ADC Channel Data Register 7 -#define AT91C_ADC_CDR1 (0xFFFD8034) // (ADC) ADC Channel Data Register 1 -#define AT91C_ADC_CDR3 (0xFFFD803C) // (ADC) ADC Channel Data Register 3 -#define AT91C_ADC_CDR5 (0xFFFD8044) // (ADC) ADC Channel Data Register 5 -#define AT91C_ADC_MR (0xFFFD8004) // (ADC) ADC Mode Register -#define AT91C_ADC_CDR6 (0xFFFD8048) // (ADC) ADC Channel Data Register 6 -#define AT91C_ADC_CR (0xFFFD8000) // (ADC) ADC Control Register -#define AT91C_ADC_CHER (0xFFFD8010) // (ADC) ADC Channel Enable Register -#define AT91C_ADC_CHSR (0xFFFD8018) // (ADC) ADC Channel Status Register -#define AT91C_ADC_IER (0xFFFD8024) // (ADC) ADC Interrupt Enable Register -#define AT91C_ADC_SR (0xFFFD801C) // (ADC) ADC Status Register -#define AT91C_ADC_CHDR (0xFFFD8014) // (ADC) ADC Channel Disable Register -#define AT91C_ADC_IDR (0xFFFD8028) // (ADC) ADC Interrupt Disable Register -#define AT91C_ADC_LCDR (0xFFFD8020) // (ADC) ADC Last Converted Data Register -// ========== Register definition for PDC_SSC peripheral ========== -#define AT91C_SSC_PTCR (0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register -#define AT91C_SSC_TNPR (0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register -#define AT91C_SSC_RNPR (0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register -#define AT91C_SSC_TPR (0xFFFD4108) // (PDC_SSC) Transmit Pointer Register -#define AT91C_SSC_RPR (0xFFFD4100) // (PDC_SSC) Receive Pointer Register -#define AT91C_SSC_PTSR (0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register -#define AT91C_SSC_TNCR (0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register -#define AT91C_SSC_RNCR (0xFFFD4114) // (PDC_SSC) Receive Next Counter Register -#define AT91C_SSC_TCR (0xFFFD410C) // (PDC_SSC) Transmit Counter Register -#define AT91C_SSC_RCR (0xFFFD4104) // (PDC_SSC) Receive Counter Register -// ========== Register definition for SSC peripheral ========== -#define AT91C_SSC_RFMR (0xFFFD4014) // (SSC) Receive Frame Mode Register -#define AT91C_SSC_CMR (0xFFFD4004) // (SSC) Clock Mode Register -#define AT91C_SSC_IDR (0xFFFD4048) // (SSC) Interrupt Disable Register -#define AT91C_SSC_SR (0xFFFD4040) // (SSC) Status Register -#define AT91C_SSC_RC0R (0xFFFD4038) // (SSC) Receive Compare 0 Register -#define AT91C_SSC_RSHR (0xFFFD4030) // (SSC) Receive Sync Holding Register -#define AT91C_SSC_RHR (0xFFFD4020) // (SSC) Receive Holding Register -#define AT91C_SSC_TCMR (0xFFFD4018) // (SSC) Transmit Clock Mode Register -#define AT91C_SSC_RCMR (0xFFFD4010) // (SSC) Receive Clock ModeRegister -#define AT91C_SSC_CR (0xFFFD4000) // (SSC) Control Register -#define AT91C_SSC_IMR (0xFFFD404C) // (SSC) Interrupt Mask Register -#define AT91C_SSC_IER (0xFFFD4044) // (SSC) Interrupt Enable Register -#define AT91C_SSC_RC1R (0xFFFD403C) // (SSC) Receive Compare 1 Register -#define AT91C_SSC_TSHR (0xFFFD4034) // (SSC) Transmit Sync Holding Register -#define AT91C_SSC_THR (0xFFFD4024) // (SSC) Transmit Holding Register -#define AT91C_SSC_TFMR (0xFFFD401C) // (SSC) Transmit Frame Mode Register -// ========== Register definition for PDC_US1 peripheral ========== -#define AT91C_US1_PTSR (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register -#define AT91C_US1_TNCR (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register -#define AT91C_US1_RNCR (0xFFFC4114) // (PDC_US1) Receive Next Counter Register -#define AT91C_US1_TCR (0xFFFC410C) // (PDC_US1) Transmit Counter Register -#define AT91C_US1_RCR (0xFFFC4104) // (PDC_US1) Receive Counter Register -#define AT91C_US1_PTCR (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register -#define AT91C_US1_TNPR (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register -#define AT91C_US1_RNPR (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register -#define AT91C_US1_TPR (0xFFFC4108) // (PDC_US1) Transmit Pointer Register -#define AT91C_US1_RPR (0xFFFC4100) // (PDC_US1) Receive Pointer Register -// ========== Register definition for US1 peripheral ========== -#define AT91C_US1_XXR (0xFFFC4048) // (US1) XON_XOFF Register -#define AT91C_US1_RHR (0xFFFC4018) // (US1) Receiver Holding Register -#define AT91C_US1_IMR (0xFFFC4010) // (US1) Interrupt Mask Register -#define AT91C_US1_IER (0xFFFC4008) // (US1) Interrupt Enable Register -#define AT91C_US1_CR (0xFFFC4000) // (US1) Control Register -#define AT91C_US1_RTOR (0xFFFC4024) // (US1) Receiver Time-out Register -#define AT91C_US1_THR (0xFFFC401C) // (US1) Transmitter Holding Register -#define AT91C_US1_CSR (0xFFFC4014) // (US1) Channel Status Register -#define AT91C_US1_IDR (0xFFFC400C) // (US1) Interrupt Disable Register -#define AT91C_US1_FIDI (0xFFFC4040) // (US1) FI_DI_Ratio Register -#define AT91C_US1_BRGR (0xFFFC4020) // (US1) Baud Rate Generator Register -#define AT91C_US1_TTGR (0xFFFC4028) // (US1) Transmitter Time-guard Register -#define AT91C_US1_IF (0xFFFC404C) // (US1) IRDA_FILTER Register -#define AT91C_US1_NER (0xFFFC4044) // (US1) Nb Errors Register -#define AT91C_US1_MR (0xFFFC4004) // (US1) Mode Register -// ========== Register definition for PDC_US0 peripheral ========== -#define AT91C_US0_PTCR (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register -#define AT91C_US0_TNPR (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register -#define AT91C_US0_RNPR (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register -#define AT91C_US0_TPR (0xFFFC0108) // (PDC_US0) Transmit Pointer Register -#define AT91C_US0_RPR (0xFFFC0100) // (PDC_US0) Receive Pointer Register -#define AT91C_US0_PTSR (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register -#define AT91C_US0_TNCR (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register -#define AT91C_US0_RNCR (0xFFFC0114) // (PDC_US0) Receive Next Counter Register -#define AT91C_US0_TCR (0xFFFC010C) // (PDC_US0) Transmit Counter Register -#define AT91C_US0_RCR (0xFFFC0104) // (PDC_US0) Receive Counter Register -// ========== Register definition for US0 peripheral ========== -#define AT91C_US0_TTGR (0xFFFC0028) // (US0) Transmitter Time-guard Register -#define AT91C_US0_BRGR (0xFFFC0020) // (US0) Baud Rate Generator Register -#define AT91C_US0_RHR (0xFFFC0018) // (US0) Receiver Holding Register -#define AT91C_US0_IMR (0xFFFC0010) // (US0) Interrupt Mask Register -#define AT91C_US0_NER (0xFFFC0044) // (US0) Nb Errors Register -#define AT91C_US0_RTOR (0xFFFC0024) // (US0) Receiver Time-out Register -#define AT91C_US0_XXR (0xFFFC0048) // (US0) XON_XOFF Register -#define AT91C_US0_FIDI (0xFFFC0040) // (US0) FI_DI_Ratio Register -#define AT91C_US0_CR (0xFFFC0000) // (US0) Control Register -#define AT91C_US0_IER (0xFFFC0008) // (US0) Interrupt Enable Register -#define AT91C_US0_IF (0xFFFC004C) // (US0) IRDA_FILTER Register -#define AT91C_US0_MR (0xFFFC0004) // (US0) Mode Register -#define AT91C_US0_IDR (0xFFFC000C) // (US0) Interrupt Disable Register -#define AT91C_US0_CSR (0xFFFC0014) // (US0) Channel Status Register -#define AT91C_US0_THR (0xFFFC001C) // (US0) Transmitter Holding Register -// ========== Register definition for TWI peripheral ========== -#define AT91C_TWI_RHR (0xFFFB8030) // (TWI) Receive Holding Register -#define AT91C_TWI_IDR (0xFFFB8028) // (TWI) Interrupt Disable Register -#define AT91C_TWI_SR (0xFFFB8020) // (TWI) Status Register -#define AT91C_TWI_CWGR (0xFFFB8010) // (TWI) Clock Waveform Generator Register -#define AT91C_TWI_SMR (0xFFFB8008) // (TWI) Slave Mode Register -#define AT91C_TWI_CR (0xFFFB8000) // (TWI) Control Register -#define AT91C_TWI_THR (0xFFFB8034) // (TWI) Transmit Holding Register -#define AT91C_TWI_IMR (0xFFFB802C) // (TWI) Interrupt Mask Register -#define AT91C_TWI_IER (0xFFFB8024) // (TWI) Interrupt Enable Register -#define AT91C_TWI_IADR (0xFFFB800C) // (TWI) Internal Address Register -#define AT91C_TWI_MMR (0xFFFB8004) // (TWI) Master Mode Register -// ========== Register definition for TC2 peripheral ========== -#define AT91C_TC2_IMR (0xFFFA00AC) // (TC2) Interrupt Mask Register -#define AT91C_TC2_IER (0xFFFA00A4) // (TC2) Interrupt Enable Register -#define AT91C_TC2_RC (0xFFFA009C) // (TC2) Register C -#define AT91C_TC2_RA (0xFFFA0094) // (TC2) Register A -#define AT91C_TC2_CMR (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC2_IDR (0xFFFA00A8) // (TC2) Interrupt Disable Register -#define AT91C_TC2_SR (0xFFFA00A0) // (TC2) Status Register -#define AT91C_TC2_RB (0xFFFA0098) // (TC2) Register B -#define AT91C_TC2_CV (0xFFFA0090) // (TC2) Counter Value -#define AT91C_TC2_CCR (0xFFFA0080) // (TC2) Channel Control Register -// ========== Register definition for TC1 peripheral ========== -#define AT91C_TC1_IMR (0xFFFA006C) // (TC1) Interrupt Mask Register -#define AT91C_TC1_IER (0xFFFA0064) // (TC1) Interrupt Enable Register -#define AT91C_TC1_RC (0xFFFA005C) // (TC1) Register C -#define AT91C_TC1_RA (0xFFFA0054) // (TC1) Register A -#define AT91C_TC1_CMR (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC1_IDR (0xFFFA0068) // (TC1) Interrupt Disable Register -#define AT91C_TC1_SR (0xFFFA0060) // (TC1) Status Register -#define AT91C_TC1_RB (0xFFFA0058) // (TC1) Register B -#define AT91C_TC1_CV (0xFFFA0050) // (TC1) Counter Value -#define AT91C_TC1_CCR (0xFFFA0040) // (TC1) Channel Control Register -// ========== Register definition for TC0 peripheral ========== -#define AT91C_TC0_IMR (0xFFFA002C) // (TC0) Interrupt Mask Register -#define AT91C_TC0_IER (0xFFFA0024) // (TC0) Interrupt Enable Register -#define AT91C_TC0_RC (0xFFFA001C) // (TC0) Register C -#define AT91C_TC0_RA (0xFFFA0014) // (TC0) Register A -#define AT91C_TC0_CMR (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC0_IDR (0xFFFA0028) // (TC0) Interrupt Disable Register -#define AT91C_TC0_SR (0xFFFA0020) // (TC0) Status Register -#define AT91C_TC0_RB (0xFFFA0018) // (TC0) Register B -#define AT91C_TC0_CV (0xFFFA0010) // (TC0) Counter Value -#define AT91C_TC0_CCR (0xFFFA0000) // (TC0) Channel Control Register -// ========== Register definition for TCB peripheral ========== -#define AT91C_TCB_BMR (0xFFFA00C4) // (TCB) TC Block Mode Register -#define AT91C_TCB_BCR (0xFFFA00C0) // (TCB) TC Block Control Register -// ========== Register definition for PWMC_CH3 peripheral ========== -#define AT91C_CH3_CUPDR (0xFFFCC270) // (PWMC_CH3) Channel Update Register -#define AT91C_CH3_CPRDR (0xFFFCC268) // (PWMC_CH3) Channel Period Register -#define AT91C_CH3_CMR (0xFFFCC260) // (PWMC_CH3) Channel Mode Register -#define AT91C_CH3_Reserved (0xFFFCC274) // (PWMC_CH3) Reserved -#define AT91C_CH3_CCNTR (0xFFFCC26C) // (PWMC_CH3) Channel Counter Register -#define AT91C_CH3_CDTYR (0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH2 peripheral ========== -#define AT91C_CH2_CUPDR (0xFFFCC250) // (PWMC_CH2) Channel Update Register -#define AT91C_CH2_CPRDR (0xFFFCC248) // (PWMC_CH2) Channel Period Register -#define AT91C_CH2_CMR (0xFFFCC240) // (PWMC_CH2) Channel Mode Register -#define AT91C_CH2_Reserved (0xFFFCC254) // (PWMC_CH2) Reserved -#define AT91C_CH2_CCNTR (0xFFFCC24C) // (PWMC_CH2) Channel Counter Register -#define AT91C_CH2_CDTYR (0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH1 peripheral ========== -#define AT91C_CH1_CUPDR (0xFFFCC230) // (PWMC_CH1) Channel Update Register -#define AT91C_CH1_CPRDR (0xFFFCC228) // (PWMC_CH1) Channel Period Register -#define AT91C_CH1_CMR (0xFFFCC220) // (PWMC_CH1) Channel Mode Register -#define AT91C_CH1_Reserved (0xFFFCC234) // (PWMC_CH1) Reserved -#define AT91C_CH1_CCNTR (0xFFFCC22C) // (PWMC_CH1) Channel Counter Register -#define AT91C_CH1_CDTYR (0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH0 peripheral ========== -#define AT91C_CH0_CUPDR (0xFFFCC210) // (PWMC_CH0) Channel Update Register -#define AT91C_CH0_CPRDR (0xFFFCC208) // (PWMC_CH0) Channel Period Register -#define AT91C_CH0_CMR (0xFFFCC200) // (PWMC_CH0) Channel Mode Register -#define AT91C_CH0_Reserved (0xFFFCC214) // (PWMC_CH0) Reserved -#define AT91C_CH0_CCNTR (0xFFFCC20C) // (PWMC_CH0) Channel Counter Register -#define AT91C_CH0_CDTYR (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register -// ========== Register definition for PWMC peripheral ========== -#define AT91C_PWMC_VR (0xFFFCC0FC) // (PWMC) PWMC Version Register -#define AT91C_PWMC_ISR (0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register -#define AT91C_PWMC_IDR (0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register -#define AT91C_PWMC_SR (0xFFFCC00C) // (PWMC) PWMC Status Register -#define AT91C_PWMC_ENA (0xFFFCC004) // (PWMC) PWMC Enable Register -#define AT91C_PWMC_IMR (0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register -#define AT91C_PWMC_MR (0xFFFCC000) // (PWMC) PWMC Mode Register -#define AT91C_PWMC_DIS (0xFFFCC008) // (PWMC) PWMC Disable Register -#define AT91C_PWMC_IER (0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register -// ========== Register definition for UDP peripheral ========== -#define AT91C_UDP_ISR (0xFFFB001C) // (UDP) Interrupt Status Register -#define AT91C_UDP_IDR (0xFFFB0014) // (UDP) Interrupt Disable Register -#define AT91C_UDP_GLBSTATE (0xFFFB0004) // (UDP) Global State Register -#define AT91C_UDP_FDR (0xFFFB0050) // (UDP) Endpoint FIFO Data Register -#define AT91C_UDP_CSR (0xFFFB0030) // (UDP) Endpoint Control and Status Register -#define AT91C_UDP_RSTEP (0xFFFB0028) // (UDP) Reset Endpoint Register -#define AT91C_UDP_ICR (0xFFFB0020) // (UDP) Interrupt Clear Register -#define AT91C_UDP_IMR (0xFFFB0018) // (UDP) Interrupt Mask Register -#define AT91C_UDP_IER (0xFFFB0010) // (UDP) Interrupt Enable Register -#define AT91C_UDP_FADDR (0xFFFB0008) // (UDP) Function Address Register -#define AT91C_UDP_NUM (0xFFFB0000) // (UDP) Frame Number Register - -// ***************************************************************************** -// PIO DEFINITIONS FOR AT91SAM7S64 -// ***************************************************************************** -#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 -#define AT91C_PA0_PWM0 (AT91C_PIO_PA0) // PWM Channel 0 -#define AT91C_PA0_TIOA0 (AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 -#define AT91C_PA1_PWM1 (AT91C_PIO_PA1) // PWM Channel 1 -#define AT91C_PA1_TIOB0 (AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 -#define AT91C_PA10_DTXD (AT91C_PIO_PA10) // DBGU Debug Transmit Data -#define AT91C_PA10_NPCS2 (AT91C_PIO_PA10) // SPI Peripheral Chip Select 2 -#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 -#define AT91C_PA11_NPCS0 (AT91C_PIO_PA11) // SPI Peripheral Chip Select 0 -#define AT91C_PA11_PWM0 (AT91C_PIO_PA11) // PWM Channel 0 -#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 -#define AT91C_PA12_MISO (AT91C_PIO_PA12) // SPI Master In Slave -#define AT91C_PA12_PWM1 (AT91C_PIO_PA12) // PWM Channel 1 -#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 -#define AT91C_PA13_MOSI (AT91C_PIO_PA13) // SPI Master Out Slave -#define AT91C_PA13_PWM2 (AT91C_PIO_PA13) // PWM Channel 2 -#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 -#define AT91C_PA14_SPCK (AT91C_PIO_PA14) // SPI Serial Clock -#define AT91C_PA14_PWM3 (AT91C_PIO_PA14) // PWM Channel 3 -#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 -#define AT91C_PA15_TF (AT91C_PIO_PA15) // SSC Transmit Frame Sync -#define AT91C_PA15_TIOA1 (AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 -#define AT91C_PA16_TK (AT91C_PIO_PA16) // SSC Transmit Clock -#define AT91C_PA16_TIOB1 (AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 -#define AT91C_PA17_TD (AT91C_PIO_PA17) // SSC Transmit data -#define AT91C_PA17_PCK1 (AT91C_PIO_PA17) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 -#define AT91C_PA18_RD (AT91C_PIO_PA18) // SSC Receive Data -#define AT91C_PA18_PCK2 (AT91C_PIO_PA18) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 -#define AT91C_PA19_RK (AT91C_PIO_PA19) // SSC Receive Clock -#define AT91C_PA19_FIQ (AT91C_PIO_PA19) // AIC Fast Interrupt Input -#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 -#define AT91C_PA2_PWM2 (AT91C_PIO_PA2) // PWM Channel 2 -#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock -#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 -#define AT91C_PA20_RF (AT91C_PIO_PA20) // SSC Receive Frame Sync -#define AT91C_PA20_IRQ0 (AT91C_PIO_PA20) // External Interrupt 0 -#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 -#define AT91C_PA21_RXD1 (AT91C_PIO_PA21) // USART 1 Receive Data -#define AT91C_PA21_PCK1 (AT91C_PIO_PA21) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 -#define AT91C_PA22_TXD1 (AT91C_PIO_PA22) // USART 1 Transmit Data -#define AT91C_PA22_NPCS3 (AT91C_PIO_PA22) // SPI Peripheral Chip Select 3 -#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 -#define AT91C_PA23_SCK1 (AT91C_PIO_PA23) // USART 1 Serial Clock -#define AT91C_PA23_PWM0 (AT91C_PIO_PA23) // PWM Channel 0 -#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 -#define AT91C_PA24_RTS1 (AT91C_PIO_PA24) // USART 1 Ready To Send -#define AT91C_PA24_PWM1 (AT91C_PIO_PA24) // PWM Channel 1 -#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 -#define AT91C_PA25_CTS1 (AT91C_PIO_PA25) // USART 1 Clear To Send -#define AT91C_PA25_PWM2 (AT91C_PIO_PA25) // PWM Channel 2 -#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 -#define AT91C_PA26_DCD1 (AT91C_PIO_PA26) // USART 1 Data Carrier Detect -#define AT91C_PA26_TIOA2 (AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 -#define AT91C_PA27_DTR1 (AT91C_PIO_PA27) // USART 1 Data Terminal ready -#define AT91C_PA27_TIOB2 (AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 -#define AT91C_PA28_DSR1 (AT91C_PIO_PA28) // USART 1 Data Set ready -#define AT91C_PA28_TCLK1 (AT91C_PIO_PA28) // Timer Counter 1 external clock input -#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 -#define AT91C_PA29_RI1 (AT91C_PIO_PA29) // USART 1 Ring Indicator -#define AT91C_PA29_TCLK2 (AT91C_PIO_PA29) // Timer Counter 2 external clock input -#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 -#define AT91C_PA3_TWD (AT91C_PIO_PA3) // TWI Two-wire Serial Data -#define AT91C_PA3_NPCS3 (AT91C_PIO_PA3) // SPI Peripheral Chip Select 3 -#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 -#define AT91C_PA30_IRQ1 (AT91C_PIO_PA30) // External Interrupt 1 -#define AT91C_PA30_NPCS2 (AT91C_PIO_PA30) // SPI Peripheral Chip Select 2 -#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31 -#define AT91C_PA31_NPCS1 (AT91C_PIO_PA31) // SPI Peripheral Chip Select 1 -#define AT91C_PA31_PCK2 (AT91C_PIO_PA31) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 -#define AT91C_PA4_TWCK (AT91C_PIO_PA4) // TWI Two-wire Serial Clock -#define AT91C_PA4_TCLK0 (AT91C_PIO_PA4) // Timer Counter 0 external clock input -#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 -#define AT91C_PA5_RXD0 (AT91C_PIO_PA5) // USART 0 Receive Data -#define AT91C_PA5_NPCS3 (AT91C_PIO_PA5) // SPI Peripheral Chip Select 3 -#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 -#define AT91C_PA6_TXD0 (AT91C_PIO_PA6) // USART 0 Transmit Data -#define AT91C_PA6_PCK0 (AT91C_PIO_PA6) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 -#define AT91C_PA7_RTS0 (AT91C_PIO_PA7) // USART 0 Ready To Send -#define AT91C_PA7_PWM3 (AT91C_PIO_PA7) // PWM Channel 3 -#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 -#define AT91C_PA8_CTS0 (AT91C_PIO_PA8) // USART 0 Clear To Send -#define AT91C_PA8_ADTRG (AT91C_PIO_PA8) // ADC External Trigger -#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 -#define AT91C_PA9_DRXD (AT91C_PIO_PA9) // DBGU Debug Receive Data -#define AT91C_PA9_NPCS1 (AT91C_PIO_PA9) // SPI Peripheral Chip Select 1 - -// ***************************************************************************** -// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64 -// ***************************************************************************** -#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) -#define AT91C_ID_SYS ( 1) // System Peripheral -#define AT91C_ID_PIOA ( 2) // Parallel IO Controller -#define AT91C_ID_3_Reserved ( 3) // Reserved -#define AT91C_ID_ADC ( 4) // Analog-to-Digital Converter -#define AT91C_ID_SPI ( 5) // Serial Peripheral Interface -#define AT91C_ID_US0 ( 6) // USART 0 -#define AT91C_ID_US1 ( 7) // USART 1 -#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller -#define AT91C_ID_TWI ( 9) // Two-Wire Interface -#define AT91C_ID_PWMC (10) // PWM Controller -#define AT91C_ID_UDP (11) // USB Device Port -#define AT91C_ID_TC0 (12) // Timer Counter 0 -#define AT91C_ID_TC1 (13) // Timer Counter 1 -#define AT91C_ID_TC2 (14) // Timer Counter 2 -#define AT91C_ID_15_Reserved (15) // Reserved -#define AT91C_ID_16_Reserved (16) // Reserved -#define AT91C_ID_17_Reserved (17) // Reserved -#define AT91C_ID_18_Reserved (18) // Reserved -#define AT91C_ID_19_Reserved (19) // Reserved -#define AT91C_ID_20_Reserved (20) // Reserved -#define AT91C_ID_21_Reserved (21) // Reserved -#define AT91C_ID_22_Reserved (22) // Reserved -#define AT91C_ID_23_Reserved (23) // Reserved -#define AT91C_ID_24_Reserved (24) // Reserved -#define AT91C_ID_25_Reserved (25) // Reserved -#define AT91C_ID_26_Reserved (26) // Reserved -#define AT91C_ID_27_Reserved (27) // Reserved -#define AT91C_ID_28_Reserved (28) // Reserved -#define AT91C_ID_29_Reserved (29) // Reserved -#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) -#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) - -// ***************************************************************************** -// BASE ADDRESS DEFINITIONS FOR AT91SAM7S64 -// ***************************************************************************** -#define AT91C_BASE_SYSC (0xFFFFF000) // (SYSC) Base Address -#define AT91C_BASE_AIC (0xFFFFF000) // (AIC) Base Address -#define AT91C_BASE_DBGU (0xFFFFF200) // (DBGU) Base Address -#define AT91C_BASE_PDC_DBGU (0xFFFFF300) // (PDC_DBGU) Base Address -#define AT91C_BASE_PIOA (0xFFFFF400) // (PIOA) Base Address -#define AT91C_BASE_CKGR (0xFFFFFC20) // (CKGR) Base Address -#define AT91C_BASE_PMC (0xFFFFFC00) // (PMC) Base Address -#define AT91C_BASE_RSTC (0xFFFFFD00) // (RSTC) Base Address -#define AT91C_BASE_RTTC (0xFFFFFD20) // (RTTC) Base Address -#define AT91C_BASE_PITC (0xFFFFFD30) // (PITC) Base Address -#define AT91C_BASE_WDTC (0xFFFFFD40) // (WDTC) Base Address -#define AT91C_BASE_MC (0xFFFFFF00) // (MC) Base Address -#define AT91C_BASE_PDC_SPI (0xFFFE0100) // (PDC_SPI) Base Address -#define AT91C_BASE_SPI (0xFFFE0000) // (SPI) Base Address -#define AT91C_BASE_PDC_ADC (0xFFFD8100) // (PDC_ADC) Base Address -#define AT91C_BASE_ADC (0xFFFD8000) // (ADC) Base Address -#define AT91C_BASE_PDC_SSC (0xFFFD4100) // (PDC_SSC) Base Address -#define AT91C_BASE_SSC (0xFFFD4000) // (SSC) Base Address -#define AT91C_BASE_PDC_US1 (0xFFFC4100) // (PDC_US1) Base Address -#define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address -#define AT91C_BASE_PDC_US0 (0xFFFC0100) // (PDC_US0) Base Address -#define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address -#define AT91C_BASE_TWI (0xFFFB8000) // (TWI) Base Address -#define AT91C_BASE_TC2 (0xFFFA0080) // (TC2) Base Address -#define AT91C_BASE_TC1 (0xFFFA0040) // (TC1) Base Address -#define AT91C_BASE_TC0 (0xFFFA0000) // (TC0) Base Address -#define AT91C_BASE_TCB (0xFFFA0000) // (TCB) Base Address -#define AT91C_BASE_PWMC_CH3 (0xFFFCC260) // (PWMC_CH3) Base Address -#define AT91C_BASE_PWMC_CH2 (0xFFFCC240) // (PWMC_CH2) Base Address -#define AT91C_BASE_PWMC_CH1 (0xFFFCC220) // (PWMC_CH1) Base Address -#define AT91C_BASE_PWMC_CH0 (0xFFFCC200) // (PWMC_CH0) Base Address -#define AT91C_BASE_PWMC (0xFFFCC000) // (PWMC) Base Address -#define AT91C_BASE_UDP (0xFFFB0000) // (UDP) Base Address - -// ***************************************************************************** -// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64 -// ***************************************************************************** -#define AT91C_ISRAM (0x00200000) // Internal SRAM base address -#define AT91C_ISRAM_SIZE (0x00004000) // Internal SRAM size in byte (16 Kbyte) -#define AT91C_IFLASH (0x00100000) // Internal ROM base address -#define AT91C_IFLASH_SIZE (0x00010000) // Internal ROM size in byte (64 Kbyte) - - diff --git a/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h b/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h deleted file mode 100644 index ae4f35f81..000000000 --- a/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h +++ /dev/null @@ -1,2715 +0,0 @@ -// ---------------------------------------------------------------------------- -// ATMEL Microcontroller Software Support - ROUSSET - -// ---------------------------------------------------------------------------- -// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// ---------------------------------------------------------------------------- -// File Name : AT91SAM7X128.h -// Object : AT91SAM7X128 definitions -// Generated : AT91 SW Application Group 05/20/2005 (16:22:23) -// -// CVS Reference : /AT91SAM7X128.pl/1.14/Tue May 10 12:12:05 2005// -// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// -// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// -// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// -// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// -// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// -// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// -// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// -// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// -// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// -// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// -// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// -// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// -// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// -// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// -// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// -// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// -// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// -// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// -// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// -// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// -// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// -// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// -// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// -// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// -// ---------------------------------------------------------------------------- - -#ifndef AT91SAM7X128_H -#define AT91SAM7X128_H - -typedef volatile unsigned int AT91_REG;// Hardware register definition - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Peripherals -// ***************************************************************************** -typedef struct _AT91S_SYS { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register - AT91_REG Reserved2[45]; // - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved3[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved4[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register - AT91_REG Reserved5[54]; // - AT91_REG PIOA_PER; // PIO Enable Register - AT91_REG PIOA_PDR; // PIO Disable Register - AT91_REG PIOA_PSR; // PIO Status Register - AT91_REG Reserved6[1]; // - AT91_REG PIOA_OER; // Output Enable Register - AT91_REG PIOA_ODR; // Output Disable Registerr - AT91_REG PIOA_OSR; // Output Status Register - AT91_REG Reserved7[1]; // - AT91_REG PIOA_IFER; // Input Filter Enable Register - AT91_REG PIOA_IFDR; // Input Filter Disable Register - AT91_REG PIOA_IFSR; // Input Filter Status Register - AT91_REG Reserved8[1]; // - AT91_REG PIOA_SODR; // Set Output Data Register - AT91_REG PIOA_CODR; // Clear Output Data Register - AT91_REG PIOA_ODSR; // Output Data Status Register - AT91_REG PIOA_PDSR; // Pin Data Status Register - AT91_REG PIOA_IER; // Interrupt Enable Register - AT91_REG PIOA_IDR; // Interrupt Disable Register - AT91_REG PIOA_IMR; // Interrupt Mask Register - AT91_REG PIOA_ISR; // Interrupt Status Register - AT91_REG PIOA_MDER; // Multi-driver Enable Register - AT91_REG PIOA_MDDR; // Multi-driver Disable Register - AT91_REG PIOA_MDSR; // Multi-driver Status Register - AT91_REG Reserved9[1]; // - AT91_REG PIOA_PPUDR; // Pull-up Disable Register - AT91_REG PIOA_PPUER; // Pull-up Enable Register - AT91_REG PIOA_PPUSR; // Pull-up Status Register - AT91_REG Reserved10[1]; // - AT91_REG PIOA_ASR; // Select A Register - AT91_REG PIOA_BSR; // Select B Register - AT91_REG PIOA_ABSR; // AB Select Status Register - AT91_REG Reserved11[9]; // - AT91_REG PIOA_OWER; // Output Write Enable Register - AT91_REG PIOA_OWDR; // Output Write Disable Register - AT91_REG PIOA_OWSR; // Output Write Status Register - AT91_REG Reserved12[85]; // - AT91_REG PIOB_PER; // PIO Enable Register - AT91_REG PIOB_PDR; // PIO Disable Register - AT91_REG PIOB_PSR; // PIO Status Register - AT91_REG Reserved13[1]; // - AT91_REG PIOB_OER; // Output Enable Register - AT91_REG PIOB_ODR; // Output Disable Registerr - AT91_REG PIOB_OSR; // Output Status Register - AT91_REG Reserved14[1]; // - AT91_REG PIOB_IFER; // Input Filter Enable Register - AT91_REG PIOB_IFDR; // Input Filter Disable Register - AT91_REG PIOB_IFSR; // Input Filter Status Register - AT91_REG Reserved15[1]; // - AT91_REG PIOB_SODR; // Set Output Data Register - AT91_REG PIOB_CODR; // Clear Output Data Register - AT91_REG PIOB_ODSR; // Output Data Status Register - AT91_REG PIOB_PDSR; // Pin Data Status Register - AT91_REG PIOB_IER; // Interrupt Enable Register - AT91_REG PIOB_IDR; // Interrupt Disable Register - AT91_REG PIOB_IMR; // Interrupt Mask Register - AT91_REG PIOB_ISR; // Interrupt Status Register - AT91_REG PIOB_MDER; // Multi-driver Enable Register - AT91_REG PIOB_MDDR; // Multi-driver Disable Register - AT91_REG PIOB_MDSR; // Multi-driver Status Register - AT91_REG Reserved16[1]; // - AT91_REG PIOB_PPUDR; // Pull-up Disable Register - AT91_REG PIOB_PPUER; // Pull-up Enable Register - AT91_REG PIOB_PPUSR; // Pull-up Status Register - AT91_REG Reserved17[1]; // - AT91_REG PIOB_ASR; // Select A Register - AT91_REG PIOB_BSR; // Select B Register - AT91_REG PIOB_ABSR; // AB Select Status Register - AT91_REG Reserved18[9]; // - AT91_REG PIOB_OWER; // Output Write Enable Register - AT91_REG PIOB_OWDR; // Output Write Disable Register - AT91_REG PIOB_OWSR; // Output Write Status Register - AT91_REG Reserved19[341]; // - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved20[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved21[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved22[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved23[3]; // - AT91_REG PMC_PCKR[4]; // Programmable Clock Register - AT91_REG Reserved24[4]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register - AT91_REG Reserved25[36]; // - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register - AT91_REG Reserved26[5]; // - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register - AT91_REG Reserved27[5]; // - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_SYS, *AT91PS_SYS; - - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// ***************************************************************************** -typedef struct _AT91S_AIC { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register -} AT91S_AIC, *AT91PS_AIC; - -// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level -#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level -#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level -#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type -#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive -#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered -#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered -#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered -// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status -#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status -// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode -#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Peripheral DMA Controller -// ***************************************************************************** -typedef struct _AT91S_PDC { - AT91_REG PDC_RPR; // Receive Pointer Register - AT91_REG PDC_RCR; // Receive Counter Register - AT91_REG PDC_TPR; // Transmit Pointer Register - AT91_REG PDC_TCR; // Transmit Counter Register - AT91_REG PDC_RNPR; // Receive Next Pointer Register - AT91_REG PDC_RNCR; // Receive Next Counter Register - AT91_REG PDC_TNPR; // Transmit Next Pointer Register - AT91_REG PDC_TNCR; // Transmit Next Counter Register - AT91_REG PDC_PTCR; // PDC Transfer Control Register - AT91_REG PDC_PTSR; // PDC Transfer Status Register -} AT91S_PDC, *AT91PS_PDC; - -// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable -#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable -#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable -#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable -// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Debug Unit -// ***************************************************************************** -typedef struct _AT91S_DBGU { - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved0[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved1[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register -} AT91S_DBGU, *AT91PS_DBGU; - -// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver -#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter -#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable -#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable -#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable -#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable -#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits -// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type -#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity -#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity -#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space) -#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark) -#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity -#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode -#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode -#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt -#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt -#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt -#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt -#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt -#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt -#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt -#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt -#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt -#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt -#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt -#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt -// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// ***************************************************************************** -typedef struct _AT91S_PIO { - AT91_REG PIO_PER; // PIO Enable Register - AT91_REG PIO_PDR; // PIO Disable Register - AT91_REG PIO_PSR; // PIO Status Register - AT91_REG Reserved0[1]; // - AT91_REG PIO_OER; // Output Enable Register - AT91_REG PIO_ODR; // Output Disable Registerr - AT91_REG PIO_OSR; // Output Status Register - AT91_REG Reserved1[1]; // - AT91_REG PIO_IFER; // Input Filter Enable Register - AT91_REG PIO_IFDR; // Input Filter Disable Register - AT91_REG PIO_IFSR; // Input Filter Status Register - AT91_REG Reserved2[1]; // - AT91_REG PIO_SODR; // Set Output Data Register - AT91_REG PIO_CODR; // Clear Output Data Register - AT91_REG PIO_ODSR; // Output Data Status Register - AT91_REG PIO_PDSR; // Pin Data Status Register - AT91_REG PIO_IER; // Interrupt Enable Register - AT91_REG PIO_IDR; // Interrupt Disable Register - AT91_REG PIO_IMR; // Interrupt Mask Register - AT91_REG PIO_ISR; // Interrupt Status Register - AT91_REG PIO_MDER; // Multi-driver Enable Register - AT91_REG PIO_MDDR; // Multi-driver Disable Register - AT91_REG PIO_MDSR; // Multi-driver Status Register - AT91_REG Reserved3[1]; // - AT91_REG PIO_PPUDR; // Pull-up Disable Register - AT91_REG PIO_PPUER; // Pull-up Enable Register - AT91_REG PIO_PPUSR; // Pull-up Status Register - AT91_REG Reserved4[1]; // - AT91_REG PIO_ASR; // Select A Register - AT91_REG PIO_BSR; // Select B Register - AT91_REG PIO_ABSR; // AB Select Status Register - AT91_REG Reserved5[9]; // - AT91_REG PIO_OWER; // Output Write Enable Register - AT91_REG PIO_OWDR; // Output Write Disable Register - AT91_REG PIO_OWSR; // Output Write Status Register -} AT91S_PIO, *AT91PS_PIO; - - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Clock Generator Controler -// ***************************************************************************** -typedef struct _AT91S_CKGR { - AT91_REG CKGR_MOR; // Main Oscillator Register - AT91_REG CKGR_MCFR; // Main Clock Frequency Register - AT91_REG Reserved0[1]; // - AT91_REG CKGR_PLLR; // PLL Register -} AT91S_CKGR, *AT91PS_CKGR; - -// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable -#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass -#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time -// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency -#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready -// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- -#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter -#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range -#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier -#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks -#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output -#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 -#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Power Management Controler -// ***************************************************************************** -typedef struct _AT91S_PMC { - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved0[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved1[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved2[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved3[3]; // - AT91_REG PMC_PCKR[4]; // Programmable Clock Register - AT91_REG Reserved4[4]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register -} AT91S_PMC, *AT91PS_PMC; - -// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock -#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock -#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output -// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- -// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- -// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- -// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection -#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected -#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected -#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected -#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler -#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock -#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 -#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 -#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 -#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 -#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 -#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 -// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask -#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask -#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask -// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Reset Controller Interface -// ***************************************************************************** -typedef struct _AT91S_RSTC { - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register -} AT91S_RSTC, *AT91PS_RSTC; - -// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- -#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset -#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset -#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset -#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password -// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- -#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status -#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status -#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type -#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. -#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. -#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low. -#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured. -#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level -#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress. -// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- -#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable -#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable -#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable -#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_RTTC { - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register -} AT91S_RTTC, *AT91PS_RTTC; - -// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- -#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value -#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable -#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable -#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart -// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- -#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value -// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- -#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value -// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- -#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status -#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_PITC { - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register -} AT91S_PITC, *AT91PS_PITC; - -// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- -#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value -#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled -#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable -// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- -#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status -// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- -#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value -#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter -// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_WDTC { - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register -} AT91S_WDTC, *AT91PS_WDTC; - -// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- -#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart -#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password -// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- -#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable -#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable -#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable -#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value -#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt -#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt -// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- -#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow -#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface -// ***************************************************************************** -typedef struct _AT91S_VREG { - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_VREG, *AT91PS_VREG; - -// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- -#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Memory Controller Interface -// ***************************************************************************** -typedef struct _AT91S_MC { - AT91_REG MC_RCR; // MC Remap Control Register - AT91_REG MC_ASR; // MC Abort Status Register - AT91_REG MC_AASR; // MC Abort Address Status Register - AT91_REG Reserved0[21]; // - AT91_REG MC_FMR; // MC Flash Mode Register - AT91_REG MC_FCR; // MC Flash Command Register - AT91_REG MC_FSR; // MC Flash Status Register -} AT91S_MC, *AT91PS_MC; - -// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit -// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status -#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status -#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status -#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte -#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word -#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word -#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status -#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read -#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write -#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch -#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source -#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source -#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source -#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source -// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- -#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready -#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error -#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error -#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming -#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State -#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations -#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations -#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations -#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations -#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number -// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- -#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command -#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN. -#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. -#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. -#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits. -#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits. -#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit. -#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number -#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key -// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- -#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status -#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status -#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status -#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status -#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status -#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status -#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status -#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status -#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status -#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status -#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status -#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status -#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status -#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status -#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status -#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status -#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status -#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status -#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status -#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status -#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status -#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status -#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Serial Parallel Interface -// ***************************************************************************** -typedef struct _AT91S_SPI { - AT91_REG SPI_CR; // Control Register - AT91_REG SPI_MR; // Mode Register - AT91_REG SPI_RDR; // Receive Data Register - AT91_REG SPI_TDR; // Transmit Data Register - AT91_REG SPI_SR; // Status Register - AT91_REG SPI_IER; // Interrupt Enable Register - AT91_REG SPI_IDR; // Interrupt Disable Register - AT91_REG SPI_IMR; // Interrupt Mask Register - AT91_REG Reserved0[4]; // - AT91_REG SPI_CSR[4]; // Chip Select Register - AT91_REG Reserved1[48]; // - AT91_REG SPI_RPR; // Receive Pointer Register - AT91_REG SPI_RCR; // Receive Counter Register - AT91_REG SPI_TPR; // Transmit Pointer Register - AT91_REG SPI_TCR; // Transmit Counter Register - AT91_REG SPI_RNPR; // Receive Next Pointer Register - AT91_REG SPI_RNCR; // Receive Next Counter Register - AT91_REG SPI_TNPR; // Transmit Next Pointer Register - AT91_REG SPI_TNCR; // Transmit Next Counter Register - AT91_REG SPI_PTCR; // PDC Transfer Control Register - AT91_REG SPI_PTSR; // PDC Transfer Status Register -} AT91S_SPI, *AT91PS_SPI; - -// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable -#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable -#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset -#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer -// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode -#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select -#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select -#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select -#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode -#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection -#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection -#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection -#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select -#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects -// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data -#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data -#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full -#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty -#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error -#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status -#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer -#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer -#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt -#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt -#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt -#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt -#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status -// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity -#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase -#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer -#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer -#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer -#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer -#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer -#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer -#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer -#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer -#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer -#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer -#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer -#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK -#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Usart -// ***************************************************************************** -typedef struct _AT91S_USART { - AT91_REG US_CR; // Control Register - AT91_REG US_MR; // Mode Register - AT91_REG US_IER; // Interrupt Enable Register - AT91_REG US_IDR; // Interrupt Disable Register - AT91_REG US_IMR; // Interrupt Mask Register - AT91_REG US_CSR; // Channel Status Register - AT91_REG US_RHR; // Receiver Holding Register - AT91_REG US_THR; // Transmitter Holding Register - AT91_REG US_BRGR; // Baud Rate Generator Register - AT91_REG US_RTOR; // Receiver Time-out Register - AT91_REG US_TTGR; // Transmitter Time-guard Register - AT91_REG Reserved0[5]; // - AT91_REG US_FIDI; // FI_DI_Ratio Register - AT91_REG US_NER; // Nb Errors Register - AT91_REG Reserved1[1]; // - AT91_REG US_IF; // IRDA_FILTER Register - AT91_REG Reserved2[44]; // - AT91_REG US_RPR; // Receive Pointer Register - AT91_REG US_RCR; // Receive Counter Register - AT91_REG US_TPR; // Transmit Pointer Register - AT91_REG US_TCR; // Transmit Counter Register - AT91_REG US_RNPR; // Receive Next Pointer Register - AT91_REG US_RNCR; // Receive Next Counter Register - AT91_REG US_TNPR; // Transmit Next Pointer Register - AT91_REG US_TNCR; // Transmit Next Counter Register - AT91_REG US_PTCR; // PDC Transfer Control Register - AT91_REG US_PTSR; // PDC Transfer Status Register -} AT91S_USART, *AT91PS_USART; - -// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break -#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break -#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out -#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address -#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations -#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge -#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out -#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable -#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable -#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable -#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable -// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode -#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal -#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 -#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking -#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem -#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0 -#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1 -#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA -#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking -#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock -#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 -#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) -#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) -#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits -#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits -#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits -#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits -#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select -#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits -#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit -#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits -#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order -#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length -#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select -#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode -#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge -#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK -#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions -#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter -// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break -#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out -#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached -#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge -#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag -#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag -#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag -#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag -// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input -#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input -#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input -#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// ***************************************************************************** -typedef struct _AT91S_SSC { - AT91_REG SSC_CR; // Control Register - AT91_REG SSC_CMR; // Clock Mode Register - AT91_REG Reserved0[2]; // - AT91_REG SSC_RCMR; // Receive Clock ModeRegister - AT91_REG SSC_RFMR; // Receive Frame Mode Register - AT91_REG SSC_TCMR; // Transmit Clock Mode Register - AT91_REG SSC_TFMR; // Transmit Frame Mode Register - AT91_REG SSC_RHR; // Receive Holding Register - AT91_REG SSC_THR; // Transmit Holding Register - AT91_REG Reserved1[2]; // - AT91_REG SSC_RSHR; // Receive Sync Holding Register - AT91_REG SSC_TSHR; // Transmit Sync Holding Register - AT91_REG Reserved2[2]; // - AT91_REG SSC_SR; // Status Register - AT91_REG SSC_IER; // Interrupt Enable Register - AT91_REG SSC_IDR; // Interrupt Disable Register - AT91_REG SSC_IMR; // Interrupt Mask Register - AT91_REG Reserved3[44]; // - AT91_REG SSC_RPR; // Receive Pointer Register - AT91_REG SSC_RCR; // Receive Counter Register - AT91_REG SSC_TPR; // Transmit Pointer Register - AT91_REG SSC_TCR; // Transmit Counter Register - AT91_REG SSC_RNPR; // Receive Next Pointer Register - AT91_REG SSC_RNCR; // Receive Next Counter Register - AT91_REG SSC_TNPR; // Transmit Next Pointer Register - AT91_REG SSC_TNCR; // Transmit Next Counter Register - AT91_REG SSC_PTCR; // PDC Transfer Control Register - AT91_REG SSC_PTSR; // PDC Transfer Status Register -} AT91S_SSC, *AT91PS_SSC; - -// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable -#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable -#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable -#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable -#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset -// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection -#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock -#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal -#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin -#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection -#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output -#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion -#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection -#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start -#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input -#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input -#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input -#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input -#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input -#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input -#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0 -#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay -#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection -// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length -#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode -#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First -#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame -#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length -#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection -#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection -// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value -#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable -// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready -#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty -#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission -#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty -#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready -#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun -#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception -#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full -#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync -#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync -#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable -#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable -// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Two-wire Interface -// ***************************************************************************** -typedef struct _AT91S_TWI { - AT91_REG TWI_CR; // Control Register - AT91_REG TWI_MMR; // Master Mode Register - AT91_REG Reserved0[1]; // - AT91_REG TWI_IADR; // Internal Address Register - AT91_REG TWI_CWGR; // Clock Waveform Generator Register - AT91_REG Reserved1[3]; // - AT91_REG TWI_SR; // Status Register - AT91_REG TWI_IER; // Interrupt Enable Register - AT91_REG TWI_IDR; // Interrupt Disable Register - AT91_REG TWI_IMR; // Interrupt Mask Register - AT91_REG TWI_RHR; // Receive Holding Register - AT91_REG TWI_THR; // Transmit Holding Register -} AT91S_TWI, *AT91PS_TWI; - -// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition -#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition -#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled -#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled -#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset -// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size -#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address -#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address -#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address -#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address -#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction -#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address -// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider -#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider -#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider -// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed -#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY -#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY -#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error -#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error -#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged -// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR PWMC Channel Interface -// ***************************************************************************** -typedef struct _AT91S_PWMC_CH { - AT91_REG PWMC_CMR; // Channel Mode Register - AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register - AT91_REG PWMC_CPRDR; // Channel Period Register - AT91_REG PWMC_CCNTR; // Channel Counter Register - AT91_REG PWMC_CUPDR; // Channel Update Register - AT91_REG PWMC_Reserved[3]; // Reserved -} AT91S_PWMC_CH, *AT91PS_PWMC_CH; - -// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- -#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx -#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) -#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment -#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity -#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period -// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- -#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle -// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- -#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period -// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- -#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter -// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- -#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface -// ***************************************************************************** -typedef struct _AT91S_PWMC { - AT91_REG PWMC_MR; // PWMC Mode Register - AT91_REG PWMC_ENA; // PWMC Enable Register - AT91_REG PWMC_DIS; // PWMC Disable Register - AT91_REG PWMC_SR; // PWMC Status Register - AT91_REG PWMC_IER; // PWMC Interrupt Enable Register - AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register - AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register - AT91_REG PWMC_ISR; // PWMC Interrupt Status Register - AT91_REG Reserved0[55]; // - AT91_REG PWMC_VR; // PWMC Version Register - AT91_REG Reserved1[64]; // - AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel -} AT91S_PWMC, *AT91PS_PWMC; - -// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- -#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor. -#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A -#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) -#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor. -#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B -#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) -// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- -#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0 -#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1 -#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2 -#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3 -// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- -// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- -// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- -// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- -// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- -// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Device Interface -// ***************************************************************************** -typedef struct _AT91S_UDP { - AT91_REG UDP_NUM; // Frame Number Register - AT91_REG UDP_GLBSTATE; // Global State Register - AT91_REG UDP_FADDR; // Function Address Register - AT91_REG Reserved0[1]; // - AT91_REG UDP_IER; // Interrupt Enable Register - AT91_REG UDP_IDR; // Interrupt Disable Register - AT91_REG UDP_IMR; // Interrupt Mask Register - AT91_REG UDP_ISR; // Interrupt Status Register - AT91_REG UDP_ICR; // Interrupt Clear Register - AT91_REG Reserved1[1]; // - AT91_REG UDP_RSTEP; // Reset Endpoint Register - AT91_REG Reserved2[1]; // - AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register - AT91_REG Reserved3[2]; // - AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register - AT91_REG Reserved4[3]; // - AT91_REG UDP_TXVC; // Transceiver Control Register -} AT91S_UDP, *AT91PS_UDP; - -// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats -#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error -#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK -// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable -#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured -#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume -#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host -#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable -// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value -#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable -// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt -#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt -#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt -#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt -#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt -#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt -#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt -#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt -#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt -// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt -// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 -#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 -#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 -#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3 -#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4 -#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5 -// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR -#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 -#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) -#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) -#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready -#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction -#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type -#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control -#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT -#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT -#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT -#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN -#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN -#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN -#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle -#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable -#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO -// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- -#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP) -#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// ***************************************************************************** -typedef struct _AT91S_TC { - AT91_REG TC_CCR; // Channel Control Register - AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) - AT91_REG Reserved0[2]; // - AT91_REG TC_CV; // Counter Value - AT91_REG TC_RA; // Register A - AT91_REG TC_RB; // Register B - AT91_REG TC_RC; // Register C - AT91_REG TC_SR; // Status Register - AT91_REG TC_IER; // Interrupt Enable Register - AT91_REG TC_IDR; // Interrupt Disable Register - AT91_REG TC_IMR; // Interrupt Mask Register -} AT91S_TC, *AT91PS_TC; - -// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command -#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command -#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command -// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection -#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK -#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0 -#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1 -#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2 -#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert -#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection -#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal -#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock -#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock -#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock -#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare -#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading -#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare -#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading -#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection -#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None -#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection -#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None -#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection -#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input -#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output -#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output -#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output -#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection -#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable -#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection -#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare -#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable -#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) -#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA -#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none -#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set -#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear -#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle -#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection -#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None -#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA -#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA -#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none -#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set -#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear -#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle -#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection -#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None -#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA -#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA -#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none -#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set -#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear -#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle -#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA -#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none -#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set -#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear -#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle -#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB -#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none -#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set -#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear -#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle -#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB -#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none -#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set -#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear -#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle -#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB -#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none -#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set -#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear -#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle -#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB -#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none -#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set -#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear -#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle -// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow -#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun -#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare -#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare -#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare -#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading -#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading -#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger -#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling -#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror -#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror -// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Interface -// ***************************************************************************** -typedef struct _AT91S_TCB { - AT91S_TC TCB_TC0; // TC Channel 0 - AT91_REG Reserved0[4]; // - AT91S_TC TCB_TC1; // TC Channel 1 - AT91_REG Reserved1[4]; // - AT91S_TC TCB_TC2; // TC Channel 2 - AT91_REG Reserved2[4]; // - AT91_REG TCB_BCR; // TC Block Control Register - AT91_REG TCB_BMR; // TC Block Mode Register -} AT91S_TCB, *AT91PS_TCB; - -// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command -// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection -#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 -#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 -#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection -#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 -#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 -#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection -#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 -#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface -// ***************************************************************************** -typedef struct _AT91S_CAN_MB { - AT91_REG CAN_MB_MMR; // MailBox Mode Register - AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register - AT91_REG CAN_MB_MID; // MailBox ID Register - AT91_REG CAN_MB_MFID; // MailBox Family ID Register - AT91_REG CAN_MB_MSR; // MailBox Status Register - AT91_REG CAN_MB_MDL; // MailBox Data Low Register - AT91_REG CAN_MB_MDH; // MailBox Data High Register - AT91_REG CAN_MB_MCR; // MailBox Control Register -} AT91S_CAN_MB, *AT91PS_CAN_MB; - -// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- -#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark -#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority -#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type -#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB) -// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- -#define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode -#define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode -#define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version -// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- -// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- -// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- -#define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value -#define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code -#define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request -#define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort -#define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready -#define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored -// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- -// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- -// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- -#define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox -#define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network Interface -// ***************************************************************************** -typedef struct _AT91S_CAN { - AT91_REG CAN_MR; // Mode Register - AT91_REG CAN_IER; // Interrupt Enable Register - AT91_REG CAN_IDR; // Interrupt Disable Register - AT91_REG CAN_IMR; // Interrupt Mask Register - AT91_REG CAN_SR; // Status Register - AT91_REG CAN_BR; // Baudrate Register - AT91_REG CAN_TIM; // Timer Register - AT91_REG CAN_TIMESTP; // Time Stamp Register - AT91_REG CAN_ECR; // Error Counter Register - AT91_REG CAN_TCR; // Transfer Command Register - AT91_REG CAN_ACR; // Abort Command Register - AT91_REG Reserved0[52]; // - AT91_REG CAN_VR; // Version Register - AT91_REG Reserved1[64]; // - AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0 - AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1 - AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2 - AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3 - AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4 - AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5 - AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6 - AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7 - AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8 - AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9 - AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10 - AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11 - AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12 - AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13 - AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14 - AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15 -} AT91S_CAN, *AT91PS_CAN; - -// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- -#define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable -#define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode -#define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode -#define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame -#define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame -#define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode -#define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze -#define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat -// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- -#define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag -#define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag -#define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag -#define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag -#define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag -#define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag -#define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag -#define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag -#define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag -#define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag -#define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag -#define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag -#define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag -#define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag -#define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag -#define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag -#define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag -#define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag -#define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag -#define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag -#define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag -#define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag -#define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag -#define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag -#define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error -#define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error -#define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error -#define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error -#define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error -// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- -// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- -// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- -#define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy -#define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy -#define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy -// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- -#define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment -#define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment -#define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment -#define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment -#define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler -#define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode -// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- -#define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field -// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- -// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- -#define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter -#define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter -// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- -#define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field -// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 -// ***************************************************************************** -typedef struct _AT91S_EMAC { - AT91_REG EMAC_NCR; // Network Control Register - AT91_REG EMAC_NCFGR; // Network Configuration Register - AT91_REG EMAC_NSR; // Network Status Register - AT91_REG Reserved0[2]; // - AT91_REG EMAC_TSR; // Transmit Status Register - AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer - AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer - AT91_REG EMAC_RSR; // Receive Status Register - AT91_REG EMAC_ISR; // Interrupt Status Register - AT91_REG EMAC_IER; // Interrupt Enable Register - AT91_REG EMAC_IDR; // Interrupt Disable Register - AT91_REG EMAC_IMR; // Interrupt Mask Register - AT91_REG EMAC_MAN; // PHY Maintenance Register - AT91_REG EMAC_PTR; // Pause Time Register - AT91_REG EMAC_PFR; // Pause Frames received Register - AT91_REG EMAC_FTO; // Frames Transmitted OK Register - AT91_REG EMAC_SCF; // Single Collision Frame Register - AT91_REG EMAC_MCF; // Multiple Collision Frame Register - AT91_REG EMAC_FRO; // Frames Received OK Register - AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register - AT91_REG EMAC_ALE; // Alignment Error Register - AT91_REG EMAC_DTF; // Deferred Transmission Frame Register - AT91_REG EMAC_LCOL; // Late Collision Register - AT91_REG EMAC_ECOL; // Excessive Collision Register - AT91_REG EMAC_TUND; // Transmit Underrun Error Register - AT91_REG EMAC_CSE; // Carrier Sense Error Register - AT91_REG EMAC_RRE; // Receive Ressource Error Register - AT91_REG EMAC_ROV; // Receive Overrun Errors Register - AT91_REG EMAC_RSE; // Receive Symbol Errors Register - AT91_REG EMAC_ELE; // Excessive Length Errors Register - AT91_REG EMAC_RJA; // Receive Jabbers Register - AT91_REG EMAC_USF; // Undersize Frames Register - AT91_REG EMAC_STE; // SQE Test Error Register - AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register - AT91_REG EMAC_TPF; // Transmitted Pause Frames Register - AT91_REG EMAC_HRB; // Hash Address Bottom[31:0] - AT91_REG EMAC_HRT; // Hash Address Top[63:32] - AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes - AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes - AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes - AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes - AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes - AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes - AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes - AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes - AT91_REG EMAC_TID; // Type ID Checking Register - AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register - AT91_REG EMAC_USRIO; // USER Input/Output Register - AT91_REG EMAC_WOL; // Wake On LAN Register - AT91_REG Reserved1[13]; // - AT91_REG EMAC_REV; // Revision Register -} AT91S_EMAC, *AT91PS_EMAC; - -// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- -#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. -#define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local. -#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable. -#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable. -#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable. -#define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers. -#define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers. -#define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers. -#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure. -#define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission. -#define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. -#define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame -#define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame -// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- -#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed. -#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex. -#define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames. -#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames. -#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast. -#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable -#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable. -#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes. -#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable. -#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC) -#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8 -#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16 -#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32 -#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64 -#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC) -#define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC) -#define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC) -#define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer -#define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable -#define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS -#define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC) -#define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS -// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- -#define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC) -// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- -#define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC) -#define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go -#define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame -#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC) -#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC) -// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- -#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC) -// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- -#define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC) -#define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC) -#define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC) -#define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC) -#define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC) -#define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC) -#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC) -#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC) -#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC) -#define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC) -#define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC) -// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- -// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- -// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- -// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- -#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC) -#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC) -#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC) -#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC) -#define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC) -// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- -#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII -// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- -#define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address -#define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable -#define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable -#define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable -// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- -#define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC) - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Analog to Digital Convertor -// ***************************************************************************** -typedef struct _AT91S_ADC { - AT91_REG ADC_CR; // ADC Control Register - AT91_REG ADC_MR; // ADC Mode Register - AT91_REG Reserved0[2]; // - AT91_REG ADC_CHER; // ADC Channel Enable Register - AT91_REG ADC_CHDR; // ADC Channel Disable Register - AT91_REG ADC_CHSR; // ADC Channel Status Register - AT91_REG ADC_SR; // ADC Status Register - AT91_REG ADC_LCDR; // ADC Last Converted Data Register - AT91_REG ADC_IER; // ADC Interrupt Enable Register - AT91_REG ADC_IDR; // ADC Interrupt Disable Register - AT91_REG ADC_IMR; // ADC Interrupt Mask Register - AT91_REG ADC_CDR0; // ADC Channel Data Register 0 - AT91_REG ADC_CDR1; // ADC Channel Data Register 1 - AT91_REG ADC_CDR2; // ADC Channel Data Register 2 - AT91_REG ADC_CDR3; // ADC Channel Data Register 3 - AT91_REG ADC_CDR4; // ADC Channel Data Register 4 - AT91_REG ADC_CDR5; // ADC Channel Data Register 5 - AT91_REG ADC_CDR6; // ADC Channel Data Register 6 - AT91_REG ADC_CDR7; // ADC Channel Data Register 7 - AT91_REG Reserved1[44]; // - AT91_REG ADC_RPR; // Receive Pointer Register - AT91_REG ADC_RCR; // Receive Counter Register - AT91_REG ADC_TPR; // Transmit Pointer Register - AT91_REG ADC_TCR; // Transmit Counter Register - AT91_REG ADC_RNPR; // Receive Next Pointer Register - AT91_REG ADC_RNCR; // Receive Next Counter Register - AT91_REG ADC_TNPR; // Transmit Next Pointer Register - AT91_REG ADC_TNCR; // Transmit Next Counter Register - AT91_REG ADC_PTCR; // PDC Transfer Control Register - AT91_REG ADC_PTSR; // PDC Transfer Status Register -} AT91S_ADC, *AT91PS_ADC; - -// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- -#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset -#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion -// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- -#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable -#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software -#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. -#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection -#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 -#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 -#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 -#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 -#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 -#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 -#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger -#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution. -#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution -#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution -#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode -#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection -#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time -#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time -// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- -#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0 -#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1 -#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2 -#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3 -#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4 -#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5 -#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6 -#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7 -// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- -// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- -// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- -#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion -#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion -#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion -#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion -#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion -#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion -#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion -#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion -#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error -#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error -#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error -#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error -#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error -#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error -#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error -#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error -#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready -#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun -#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer -#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt -// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- -#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted -// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- -// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- -// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- -// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- -#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data -// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- -// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- -// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- -// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- -// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- -// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- -// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Encryption Standard -// ***************************************************************************** -typedef struct _AT91S_AES { - AT91_REG AES_CR; // Control Register - AT91_REG AES_MR; // Mode Register - AT91_REG Reserved0[2]; // - AT91_REG AES_IER; // Interrupt Enable Register - AT91_REG AES_IDR; // Interrupt Disable Register - AT91_REG AES_IMR; // Interrupt Mask Register - AT91_REG AES_ISR; // Interrupt Status Register - AT91_REG AES_KEYWxR[4]; // Key Word x Register - AT91_REG Reserved1[4]; // - AT91_REG AES_IDATAxR[4]; // Input Data x Register - AT91_REG AES_ODATAxR[4]; // Output Data x Register - AT91_REG AES_IVxR[4]; // Initialization Vector x Register - AT91_REG Reserved2[35]; // - AT91_REG AES_VR; // AES Version Register - AT91_REG AES_RPR; // Receive Pointer Register - AT91_REG AES_RCR; // Receive Counter Register - AT91_REG AES_TPR; // Transmit Pointer Register - AT91_REG AES_TCR; // Transmit Counter Register - AT91_REG AES_RNPR; // Receive Next Pointer Register - AT91_REG AES_RNCR; // Receive Next Counter Register - AT91_REG AES_TNPR; // Transmit Next Pointer Register - AT91_REG AES_TNCR; // Transmit Next Counter Register - AT91_REG AES_PTCR; // PDC Transfer Control Register - AT91_REG AES_PTSR; // PDC Transfer Status Register -} AT91S_AES, *AT91PS_AES; - -// -------- AES_CR : (AES Offset: 0x0) Control Register -------- -#define AT91C_AES_START ((unsigned int) 0x1 << 0) // (AES) Starts Processing -#define AT91C_AES_SWRST ((unsigned int) 0x1 << 8) // (AES) Software Reset -#define AT91C_AES_LOADSEED ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading -// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- -#define AT91C_AES_CIPHER ((unsigned int) 0x1 << 0) // (AES) Processing Mode -#define AT91C_AES_PROCDLY ((unsigned int) 0xF << 4) // (AES) Processing Delay -#define AT91C_AES_SMOD ((unsigned int) 0x3 << 8) // (AES) Start Mode -#define AT91C_AES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. -#define AT91C_AES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). -#define AT91C_AES_SMOD_PDC ((unsigned int) 0x2 << 8) // (AES) PDC Mode (cf datasheet). -#define AT91C_AES_OPMOD ((unsigned int) 0x7 << 12) // (AES) Operation Mode -#define AT91C_AES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode. -#define AT91C_AES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode. -#define AT91C_AES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode. -#define AT91C_AES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode. -#define AT91C_AES_OPMOD_CTR ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode. -#define AT91C_AES_LOD ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode -#define AT91C_AES_CFBS ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size -#define AT91C_AES_CFBS_128_BIT ((unsigned int) 0x0 << 16) // (AES) 128-bit. -#define AT91C_AES_CFBS_64_BIT ((unsigned int) 0x1 << 16) // (AES) 64-bit. -#define AT91C_AES_CFBS_32_BIT ((unsigned int) 0x2 << 16) // (AES) 32-bit. -#define AT91C_AES_CFBS_16_BIT ((unsigned int) 0x3 << 16) // (AES) 16-bit. -#define AT91C_AES_CFBS_8_BIT ((unsigned int) 0x4 << 16) // (AES) 8-bit. -#define AT91C_AES_CKEY ((unsigned int) 0xF << 20) // (AES) Countermeasure Key -#define AT91C_AES_CTYPE ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type -#define AT91C_AES_CTYPE_TYPE1_EN ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled. -#define AT91C_AES_CTYPE_TYPE2_EN ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled. -#define AT91C_AES_CTYPE_TYPE3_EN ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled. -#define AT91C_AES_CTYPE_TYPE4_EN ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled. -#define AT91C_AES_CTYPE_TYPE5_EN ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled. -// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- -#define AT91C_AES_DATRDY ((unsigned int) 0x1 << 0) // (AES) DATRDY -#define AT91C_AES_ENDRX ((unsigned int) 0x1 << 1) // (AES) PDC Read Buffer End -#define AT91C_AES_ENDTX ((unsigned int) 0x1 << 2) // (AES) PDC Write Buffer End -#define AT91C_AES_RXBUFF ((unsigned int) 0x1 << 3) // (AES) PDC Read Buffer Full -#define AT91C_AES_TXBUFE ((unsigned int) 0x1 << 4) // (AES) PDC Write Buffer Empty -#define AT91C_AES_URAD ((unsigned int) 0x1 << 8) // (AES) Unspecified Register Access Detection -// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- -// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- -// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- -#define AT91C_AES_URAT ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status -#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode. -#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing. -#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing. -#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation. -#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation. -#define AT91C_AES_URAT_WO_REG_READ ((unsigned int) 0x5 << 12) // (AES) Write-only register read access. - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard -// ***************************************************************************** -typedef struct _AT91S_TDES { - AT91_REG TDES_CR; // Control Register - AT91_REG TDES_MR; // Mode Register - AT91_REG Reserved0[2]; // - AT91_REG TDES_IER; // Interrupt Enable Register - AT91_REG TDES_IDR; // Interrupt Disable Register - AT91_REG TDES_IMR; // Interrupt Mask Register - AT91_REG TDES_ISR; // Interrupt Status Register - AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register - AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register - AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register - AT91_REG Reserved1[2]; // - AT91_REG TDES_IDATAxR[2]; // Input Data x Register - AT91_REG Reserved2[2]; // - AT91_REG TDES_ODATAxR[2]; // Output Data x Register - AT91_REG Reserved3[2]; // - AT91_REG TDES_IVxR[2]; // Initialization Vector x Register - AT91_REG Reserved4[37]; // - AT91_REG TDES_VR; // TDES Version Register - AT91_REG TDES_RPR; // Receive Pointer Register - AT91_REG TDES_RCR; // Receive Counter Register - AT91_REG TDES_TPR; // Transmit Pointer Register - AT91_REG TDES_TCR; // Transmit Counter Register - AT91_REG TDES_RNPR; // Receive Next Pointer Register - AT91_REG TDES_RNCR; // Receive Next Counter Register - AT91_REG TDES_TNPR; // Transmit Next Pointer Register - AT91_REG TDES_TNCR; // Transmit Next Counter Register - AT91_REG TDES_PTCR; // PDC Transfer Control Register - AT91_REG TDES_PTSR; // PDC Transfer Status Register -} AT91S_TDES, *AT91PS_TDES; - -// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- -#define AT91C_TDES_START ((unsigned int) 0x1 << 0) // (TDES) Starts Processing -#define AT91C_TDES_SWRST ((unsigned int) 0x1 << 8) // (TDES) Software Reset -// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- -#define AT91C_TDES_CIPHER ((unsigned int) 0x1 << 0) // (TDES) Processing Mode -#define AT91C_TDES_TDESMOD ((unsigned int) 0x1 << 1) // (TDES) Single or Triple DES Mode -#define AT91C_TDES_KEYMOD ((unsigned int) 0x1 << 4) // (TDES) Key Mode -#define AT91C_TDES_SMOD ((unsigned int) 0x3 << 8) // (TDES) Start Mode -#define AT91C_TDES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. -#define AT91C_TDES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). -#define AT91C_TDES_SMOD_PDC ((unsigned int) 0x2 << 8) // (TDES) PDC Mode (cf datasheet). -#define AT91C_TDES_OPMOD ((unsigned int) 0x3 << 12) // (TDES) Operation Mode -#define AT91C_TDES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode. -#define AT91C_TDES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode. -#define AT91C_TDES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode. -#define AT91C_TDES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode. -#define AT91C_TDES_LOD ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode -#define AT91C_TDES_CFBS ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size -#define AT91C_TDES_CFBS_64_BIT ((unsigned int) 0x0 << 16) // (TDES) 64-bit. -#define AT91C_TDES_CFBS_32_BIT ((unsigned int) 0x1 << 16) // (TDES) 32-bit. -#define AT91C_TDES_CFBS_16_BIT ((unsigned int) 0x2 << 16) // (TDES) 16-bit. -#define AT91C_TDES_CFBS_8_BIT ((unsigned int) 0x3 << 16) // (TDES) 8-bit. -// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- -#define AT91C_TDES_DATRDY ((unsigned int) 0x1 << 0) // (TDES) DATRDY -#define AT91C_TDES_ENDRX ((unsigned int) 0x1 << 1) // (TDES) PDC Read Buffer End -#define AT91C_TDES_ENDTX ((unsigned int) 0x1 << 2) // (TDES) PDC Write Buffer End -#define AT91C_TDES_RXBUFF ((unsigned int) 0x1 << 3) // (TDES) PDC Read Buffer Full -#define AT91C_TDES_TXBUFE ((unsigned int) 0x1 << 4) // (TDES) PDC Write Buffer Empty -#define AT91C_TDES_URAD ((unsigned int) 0x1 << 8) // (TDES) Unspecified Register Access Detection -// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- -// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- -// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- -#define AT91C_TDES_URAT ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status -#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode. -#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing. -#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing. -#define AT91C_TDES_URAT_WO_REG_READ ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access. - -// ***************************************************************************** -// REGISTER ADDRESS DEFINITION FOR AT91SAM7X128 -// ***************************************************************************** -// ========== Register definition for SYS peripheral ========== -// ========== Register definition for AIC peripheral ========== -#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register -#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register -#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register -#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) -#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register -#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register -#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register -#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register -#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register -#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register -#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register -#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register -#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register -#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register -#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register -#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register -#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register -#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register -// ========== Register definition for PDC_DBGU peripheral ========== -#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register -#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register -#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register -#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register -#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register -#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register -#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register -#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register -#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register -#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register -// ========== Register definition for DBGU peripheral ========== -#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register -#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register -#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register -#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register -#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register -#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register -#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register -#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register -#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register -#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register -#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register -#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register -// ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register -#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register -#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register -#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register -#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register -#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register -#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register -#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register -#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register -#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register -#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register -#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register -#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register -// ========== Register definition for PIOB peripheral ========== -#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register -#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register -#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register -#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register -#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register -#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register -#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register -#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register -#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register -#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register -#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register -#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register -#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register -#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register -#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register -#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register -#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr -#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register -#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register -#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register -#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register -#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register -#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register -#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register -#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register -#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register -#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register -#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register -#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register -// ========== Register definition for CKGR peripheral ========== -#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register -#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register -#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register -// ========== Register definition for PMC peripheral ========== -#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register -#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register -#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register -#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register -#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register -#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register -#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register -#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register -#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register -#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register -#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register -#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register -#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register -#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register -#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register -// ========== Register definition for RSTC peripheral ========== -#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register -#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register -#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register -// ========== Register definition for RTTC peripheral ========== -#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register -#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register -#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register -#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register -// ========== Register definition for PITC peripheral ========== -#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register -#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register -#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register -#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register -// ========== Register definition for WDTC peripheral ========== -#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register -#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register -#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register -// ========== Register definition for VREG peripheral ========== -#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register -// ========== Register definition for MC peripheral ========== -#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register -#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register -#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register -#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register -#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register -#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register -// ========== Register definition for PDC_SPI1 peripheral ========== -#define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register -#define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register -#define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register -#define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register -#define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register -#define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register -#define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register -#define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register -#define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register -#define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register -// ========== Register definition for SPI1 peripheral ========== -#define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register -#define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register -#define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register -#define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register -#define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register -#define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register -#define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register -#define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register -#define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register -// ========== Register definition for PDC_SPI0 peripheral ========== -#define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register -#define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register -#define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register -#define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register -#define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register -#define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register -#define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register -#define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register -#define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register -#define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register -// ========== Register definition for SPI0 peripheral ========== -#define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register -#define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register -#define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register -#define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register -#define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register -#define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register -#define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register -#define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register -#define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register -// ========== Register definition for PDC_US1 peripheral ========== -#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register -#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register -#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register -#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register -#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register -#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register -#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register -#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register -#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register -#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register -// ========== Register definition for US1 peripheral ========== -#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register -#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register -#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register -#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register -#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register -#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register -#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register -#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register -#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register -#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register -#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register -#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register -#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register -#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register -// ========== Register definition for PDC_US0 peripheral ========== -#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register -#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register -#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register -#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register -#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register -#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register -#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register -#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register -#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register -#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register -// ========== Register definition for US0 peripheral ========== -#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register -#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register -#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register -#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register -#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register -#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register -#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register -#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register -#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register -#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register -#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register -#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register -#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register -#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register -// ========== Register definition for PDC_SSC peripheral ========== -#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register -#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register -#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register -#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register -#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register -#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register -#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register -#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register -#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register -#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register -// ========== Register definition for SSC peripheral ========== -#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register -#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register -#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register -#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register -#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register -#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister -#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register -#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register -#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register -#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register -#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register -#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register -#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register -#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register -// ========== Register definition for TWI peripheral ========== -#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register -#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register -#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register -#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register -#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register -#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register -#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register -#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register -#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register -#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register -// ========== Register definition for PWMC_CH3 peripheral ========== -#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register -#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved -#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register -#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register -#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register -#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register -// ========== Register definition for PWMC_CH2 peripheral ========== -#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved -#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register -#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register -#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register -#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register -#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH1 peripheral ========== -#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved -#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register -#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register -#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register -#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register -#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register -// ========== Register definition for PWMC_CH0 peripheral ========== -#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved -#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register -#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register -#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register -#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register -#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register -// ========== Register definition for PWMC peripheral ========== -#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register -#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register -#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register -#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register -#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register -#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register -#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register -#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register -#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register -// ========== Register definition for UDP peripheral ========== -#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register -#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register -#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register -#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register -#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register -#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register -#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register -#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register -#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register -#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register -#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register -#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register -// ========== Register definition for TC0 peripheral ========== -#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register -#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C -#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B -#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register -#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register -#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A -#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register -#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value -#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register -// ========== Register definition for TC1 peripheral ========== -#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B -#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register -#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register -#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register -#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register -#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A -#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C -#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register -#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value -// ========== Register definition for TC2 peripheral ========== -#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register -#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value -#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A -#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B -#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register -#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register -#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C -#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register -#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register -// ========== Register definition for TCB peripheral ========== -#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register -#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register -// ========== Register definition for CAN_MB0 peripheral ========== -#define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register -#define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register -#define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register -#define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register -#define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register -#define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register -#define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register -#define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register -// ========== Register definition for CAN_MB1 peripheral ========== -#define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register -#define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register -#define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register -#define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register -#define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register -#define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register -#define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register -#define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register -// ========== Register definition for CAN_MB2 peripheral ========== -#define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register -#define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register -#define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register -#define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register -#define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register -#define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register -#define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register -#define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register -// ========== Register definition for CAN_MB3 peripheral ========== -#define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register -#define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register -#define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register -#define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register -#define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register -#define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register -#define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register -#define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register -// ========== Register definition for CAN_MB4 peripheral ========== -#define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register -#define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register -#define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register -#define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register -#define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register -#define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register -#define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register -#define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register -// ========== Register definition for CAN_MB5 peripheral ========== -#define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register -#define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register -#define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register -#define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register -#define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register -#define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register -#define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register -#define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register -// ========== Register definition for CAN_MB6 peripheral ========== -#define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register -#define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register -#define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register -#define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register -#define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register -#define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register -#define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register -#define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register -// ========== Register definition for CAN_MB7 peripheral ========== -#define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register -#define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register -#define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register -#define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register -#define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register -#define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register -#define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register -#define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register -// ========== Register definition for CAN peripheral ========== -#define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register -#define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register -#define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register -#define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register -#define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register -#define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register -#define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register -#define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register -#define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register -#define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register -#define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register -#define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register -// ========== Register definition for EMAC peripheral ========== -#define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register -#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes -#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes -#define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register -#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register -#define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register -#define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register -#define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register -#define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register -#define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register -#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes -#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register -#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes -#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register -#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register -#define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register -#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register -#define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register -#define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] -#define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer -#define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register -#define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register -#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes -#define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register -#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register -#define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register -#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer -#define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register -#define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register -#define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32] -#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register -#define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register -#define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register -#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register -#define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register -#define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register -#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register -#define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register -#define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register -#define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register -#define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register -#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes -#define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register -#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register -#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes -#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register -#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes -#define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register -#define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register -// ========== Register definition for PDC_ADC peripheral ========== -#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register -#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register -#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register -#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register -#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register -#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register -#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register -#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register -#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register -#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register -// ========== Register definition for ADC peripheral ========== -#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 -#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 -#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 -#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 -#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register -#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register -#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 -#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 -#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register -#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register -#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register -#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 -#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 -#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register -#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register -#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register -#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register -#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register -// ========== Register definition for PDC_AES peripheral ========== -#define AT91C_AES_TPR ((AT91_REG *) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register -#define AT91C_AES_PTCR ((AT91_REG *) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register -#define AT91C_AES_RNPR ((AT91_REG *) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register -#define AT91C_AES_TNCR ((AT91_REG *) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register -#define AT91C_AES_TCR ((AT91_REG *) 0xFFFA410C) // (PDC_AES) Transmit Counter Register -#define AT91C_AES_RCR ((AT91_REG *) 0xFFFA4104) // (PDC_AES) Receive Counter Register -#define AT91C_AES_RNCR ((AT91_REG *) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register -#define AT91C_AES_TNPR ((AT91_REG *) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register -#define AT91C_AES_RPR ((AT91_REG *) 0xFFFA4100) // (PDC_AES) Receive Pointer Register -#define AT91C_AES_PTSR ((AT91_REG *) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register -// ========== Register definition for AES peripheral ========== -#define AT91C_AES_IVxR ((AT91_REG *) 0xFFFA4060) // (AES) Initialization Vector x Register -#define AT91C_AES_MR ((AT91_REG *) 0xFFFA4004) // (AES) Mode Register -#define AT91C_AES_VR ((AT91_REG *) 0xFFFA40FC) // (AES) AES Version Register -#define AT91C_AES_ODATAxR ((AT91_REG *) 0xFFFA4050) // (AES) Output Data x Register -#define AT91C_AES_IDATAxR ((AT91_REG *) 0xFFFA4040) // (AES) Input Data x Register -#define AT91C_AES_CR ((AT91_REG *) 0xFFFA4000) // (AES) Control Register -#define AT91C_AES_IDR ((AT91_REG *) 0xFFFA4014) // (AES) Interrupt Disable Register -#define AT91C_AES_IMR ((AT91_REG *) 0xFFFA4018) // (AES) Interrupt Mask Register -#define AT91C_AES_IER ((AT91_REG *) 0xFFFA4010) // (AES) Interrupt Enable Register -#define AT91C_AES_KEYWxR ((AT91_REG *) 0xFFFA4020) // (AES) Key Word x Register -#define AT91C_AES_ISR ((AT91_REG *) 0xFFFA401C) // (AES) Interrupt Status Register -// ========== Register definition for PDC_TDES peripheral ========== -#define AT91C_TDES_RNCR ((AT91_REG *) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register -#define AT91C_TDES_TCR ((AT91_REG *) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register -#define AT91C_TDES_RCR ((AT91_REG *) 0xFFFA8104) // (PDC_TDES) Receive Counter Register -#define AT91C_TDES_TNPR ((AT91_REG *) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register -#define AT91C_TDES_RNPR ((AT91_REG *) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register -#define AT91C_TDES_RPR ((AT91_REG *) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register -#define AT91C_TDES_TNCR ((AT91_REG *) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register -#define AT91C_TDES_TPR ((AT91_REG *) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register -#define AT91C_TDES_PTSR ((AT91_REG *) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register -#define AT91C_TDES_PTCR ((AT91_REG *) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register -// ========== Register definition for TDES peripheral ========== -#define AT91C_TDES_KEY2WxR ((AT91_REG *) 0xFFFA8028) // (TDES) Key 2 Word x Register -#define AT91C_TDES_KEY3WxR ((AT91_REG *) 0xFFFA8030) // (TDES) Key 3 Word x Register -#define AT91C_TDES_IDR ((AT91_REG *) 0xFFFA8014) // (TDES) Interrupt Disable Register -#define AT91C_TDES_VR ((AT91_REG *) 0xFFFA80FC) // (TDES) TDES Version Register -#define AT91C_TDES_IVxR ((AT91_REG *) 0xFFFA8060) // (TDES) Initialization Vector x Register -#define AT91C_TDES_ODATAxR ((AT91_REG *) 0xFFFA8050) // (TDES) Output Data x Register -#define AT91C_TDES_IMR ((AT91_REG *) 0xFFFA8018) // (TDES) Interrupt Mask Register -#define AT91C_TDES_MR ((AT91_REG *) 0xFFFA8004) // (TDES) Mode Register -#define AT91C_TDES_CR ((AT91_REG *) 0xFFFA8000) // (TDES) Control Register -#define AT91C_TDES_IER ((AT91_REG *) 0xFFFA8010) // (TDES) Interrupt Enable Register -#define AT91C_TDES_ISR ((AT91_REG *) 0xFFFA801C) // (TDES) Interrupt Status Register -#define AT91C_TDES_IDATAxR ((AT91_REG *) 0xFFFA8040) // (TDES) Input Data x Register -#define AT91C_TDES_KEY1WxR ((AT91_REG *) 0xFFFA8020) // (TDES) Key 1 Word x Register - -// ***************************************************************************** -// PIO DEFINITIONS FOR AT91SAM7X128 -// ***************************************************************************** -#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 -#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data -#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 -#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data -#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 -#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data -#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 -#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock -#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 -#define AT91C_PA12_NPCS00 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 -#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 -#define AT91C_PA13_NPCS01 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 -#define AT91C_PA14_NPCS02 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1 -#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 -#define AT91C_PA15_NPCS03 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input -#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 -#define AT91C_PA16_MISO0 ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave -#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 -#define AT91C_PA17_MOSI0 ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave -#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 -#define AT91C_PA18_SPCK0 ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock -#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 -#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive -#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 -#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock -#define AT91C_PA2_NPCS11 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 -#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit -#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 -#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync -#define AT91C_PA21_NPCS10 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 -#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 -#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock -#define AT91C_PA22_SPCK1 ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock -#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 -#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data -#define AT91C_PA23_MOSI1 ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave -#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 -#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data -#define AT91C_PA24_MISO1 ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave -#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 -#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock -#define AT91C_PA25_NPCS11 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 -#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync -#define AT91C_PA26_NPCS12 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 -#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data -#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3 -#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 -#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data -#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 -#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input -#define AT91C_PA29_NPCS13 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 -#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send -#define AT91C_PA3_NPCS12 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 -#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0 -#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 -#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send -#define AT91C_PA4_NPCS13 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 -#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data -#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 -#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data -#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 -#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock -#define AT91C_PA7_NPCS01 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 -#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send -#define AT91C_PA8_NPCS02 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 -#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send -#define AT91C_PA9_NPCS03 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0 -#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock -#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1 -#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable -#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10 -#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 -#define AT91C_PB10_NPCS11 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11 -#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 -#define AT91C_PB11_NPCS12 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12 -#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error -#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input -#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13 -#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 -#define AT91C_PB13_NPCS01 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14 -#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 -#define AT91C_PB14_NPCS02 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15 -#define AT91C_PB15_ERXDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid -#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16 -#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected -#define AT91C_PB16_NPCS13 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17 -#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock -#define AT91C_PB17_NPCS03 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18 -#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec -#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger -#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19 -#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0 -#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input -#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2 -#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 -#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20 -#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1 -#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21 -#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2 -#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22 -#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3 -#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23 -#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A -#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect -#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24 -#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B -#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready -#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25 -#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A -#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready -#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26 -#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B -#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator -#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27 -#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A -#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0 -#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28 -#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B -#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1 -#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29 -#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1 -#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2 -#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3 -#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 -#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30 -#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2 -#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3 -#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4 -#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid -#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5 -#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 -#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6 -#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 -#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7 -#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error -#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8 -#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock -#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9 -#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output - -// ***************************************************************************** -// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128 -// ***************************************************************************** -#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) -#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral -#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A -#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B -#define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0 -#define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1 -#define AT91C_ID_US0 ((unsigned int) 6) // USART 0 -#define AT91C_ID_US1 ((unsigned int) 7) // USART 1 -#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller -#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface -#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller -#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port -#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0 -#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1 -#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2 -#define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller -#define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC -#define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter -#define AT91C_ID_AES ((unsigned int) 18) // Advanced Encryption Standard 128-bit -#define AT91C_ID_TDES ((unsigned int) 19) // Triple Data Encryption Standard -#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved -#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved -#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved -#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved -#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved -#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved -#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved -#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved -#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved -#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved -#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0) -#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1) - -// ***************************************************************************** -// BASE ADDRESS DEFINITIONS FOR AT91SAM7X128 -// ***************************************************************************** -#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address -#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address -#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address -#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address -#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address -#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address -#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address -#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address -#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address -#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address -#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address -#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address -#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address -#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address -#define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address -#define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address -#define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address -#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address -#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address -#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address -#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address -#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address -#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address -#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address -#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address -#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address -#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address -#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address -#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address -#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address -#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address -#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address -#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address -#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address -#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address -#define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address -#define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address -#define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address -#define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address -#define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address -#define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address -#define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address -#define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address -#define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address -#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address -#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address -#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address -#define AT91C_BASE_PDC_AES ((AT91PS_PDC) 0xFFFA4100) // (PDC_AES) Base Address -#define AT91C_BASE_AES ((AT91PS_AES) 0xFFFA4000) // (AES) Base Address -#define AT91C_BASE_PDC_TDES ((AT91PS_PDC) 0xFFFA8100) // (PDC_TDES) Base Address -#define AT91C_BASE_TDES ((AT91PS_TDES) 0xFFFA8000) // (TDES) Base Address - -// ***************************************************************************** -// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128 -// ***************************************************************************** -#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address -#define AT91C_ISRAM_SIZE ((unsigned int) 0x00008000) // Internal SRAM size in byte (32 Kbyte) -#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address -#define AT91C_IFLASH_SIZE ((unsigned int) 0x00020000) // Internal ROM size in byte (128 Kbyte) - -#endif diff --git a/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h b/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h deleted file mode 100644 index 96b680a5e..000000000 --- a/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h +++ /dev/null @@ -1,2446 +0,0 @@ -// ---------------------------------------------------------------------------- -// ATMEL Microcontroller Software Support - ROUSSET - -// ---------------------------------------------------------------------------- -// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// ---------------------------------------------------------------------------- -// File Name : AT91SAM7X128.h -// Object : AT91SAM7X128 definitions -// Generated : AT91 SW Application Group 05/20/2005 (16:22:23) -// -// CVS Reference : /AT91SAM7X128.pl/1.14/Tue May 10 12:12:05 2005// -// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// -// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// -// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// -// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// -// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// -// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// -// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// -// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// -// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// -// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// -// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// -// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// -// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// -// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// -// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// -// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// -// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// -// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// -// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// -// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// -// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// -// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// -// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// -// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// -// ---------------------------------------------------------------------------- - -// Hardware register definition - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Peripherals -// ***************************************************************************** - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// ***************************************************************************** -// *** Register offset in AT91S_AIC structure *** -#define AIC_SMR ( 0) // Source Mode Register -#define AIC_SVR (128) // Source Vector Register -#define AIC_IVR (256) // IRQ Vector Register -#define AIC_FVR (260) // FIQ Vector Register -#define AIC_ISR (264) // Interrupt Status Register -#define AIC_IPR (268) // Interrupt Pending Register -#define AIC_IMR (272) // Interrupt Mask Register -#define AIC_CISR (276) // Core Interrupt Status Register -#define AIC_IECR (288) // Interrupt Enable Command Register -#define AIC_IDCR (292) // Interrupt Disable Command Register -#define AIC_ICCR (296) // Interrupt Clear Command Register -#define AIC_ISCR (300) // Interrupt Set Command Register -#define AIC_EOICR (304) // End of Interrupt Command Register -#define AIC_SPU (308) // Spurious Vector Register -#define AIC_DCR (312) // Debug Control Register (Protect) -#define AIC_FFER (320) // Fast Forcing Enable Register -#define AIC_FFDR (324) // Fast Forcing Disable Register -#define AIC_FFSR (328) // Fast Forcing Status Register -// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level -#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level -#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level -#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type -#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive -#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered -#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered -#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered -// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status -#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status -// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode -#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Peripheral DMA Controller -// ***************************************************************************** -// *** Register offset in AT91S_PDC structure *** -#define PDC_RPR ( 0) // Receive Pointer Register -#define PDC_RCR ( 4) // Receive Counter Register -#define PDC_TPR ( 8) // Transmit Pointer Register -#define PDC_TCR (12) // Transmit Counter Register -#define PDC_RNPR (16) // Receive Next Pointer Register -#define PDC_RNCR (20) // Receive Next Counter Register -#define PDC_TNPR (24) // Transmit Next Pointer Register -#define PDC_TNCR (28) // Transmit Next Counter Register -#define PDC_PTCR (32) // PDC Transfer Control Register -#define PDC_PTSR (36) // PDC Transfer Status Register -// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable -#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable -#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable -#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable -// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Debug Unit -// ***************************************************************************** -// *** Register offset in AT91S_DBGU structure *** -#define DBGU_CR ( 0) // Control Register -#define DBGU_MR ( 4) // Mode Register -#define DBGU_IER ( 8) // Interrupt Enable Register -#define DBGU_IDR (12) // Interrupt Disable Register -#define DBGU_IMR (16) // Interrupt Mask Register -#define DBGU_CSR (20) // Channel Status Register -#define DBGU_RHR (24) // Receiver Holding Register -#define DBGU_THR (28) // Transmitter Holding Register -#define DBGU_BRGR (32) // Baud Rate Generator Register -#define DBGU_CIDR (64) // Chip ID Register -#define DBGU_EXID (68) // Chip ID Extension Register -#define DBGU_FNTR (72) // Force NTRST Register -#define DBGU_RPR (256) // Receive Pointer Register -#define DBGU_RCR (260) // Receive Counter Register -#define DBGU_TPR (264) // Transmit Pointer Register -#define DBGU_TCR (268) // Transmit Counter Register -#define DBGU_RNPR (272) // Receive Next Pointer Register -#define DBGU_RNCR (276) // Receive Next Counter Register -#define DBGU_TNPR (280) // Transmit Next Pointer Register -#define DBGU_TNCR (284) // Transmit Next Counter Register -#define DBGU_PTCR (288) // PDC Transfer Control Register -#define DBGU_PTSR (292) // PDC Transfer Status Register -// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver -#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter -#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable -#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable -#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable -#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable -#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits -// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type -#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity -#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity -#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) -#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) -#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity -#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode -#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode -#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt -#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt -#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt -#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt -#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt -#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt -#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt -#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt -#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt -#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt -#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt -#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt -// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// ***************************************************************************** -// *** Register offset in AT91S_PIO structure *** -#define PIO_PER ( 0) // PIO Enable Register -#define PIO_PDR ( 4) // PIO Disable Register -#define PIO_PSR ( 8) // PIO Status Register -#define PIO_OER (16) // Output Enable Register -#define PIO_ODR (20) // Output Disable Registerr -#define PIO_OSR (24) // Output Status Register -#define PIO_IFER (32) // Input Filter Enable Register -#define PIO_IFDR (36) // Input Filter Disable Register -#define PIO_IFSR (40) // Input Filter Status Register -#define PIO_SODR (48) // Set Output Data Register -#define PIO_CODR (52) // Clear Output Data Register -#define PIO_ODSR (56) // Output Data Status Register -#define PIO_PDSR (60) // Pin Data Status Register -#define PIO_IER (64) // Interrupt Enable Register -#define PIO_IDR (68) // Interrupt Disable Register -#define PIO_IMR (72) // Interrupt Mask Register -#define PIO_ISR (76) // Interrupt Status Register -#define PIO_MDER (80) // Multi-driver Enable Register -#define PIO_MDDR (84) // Multi-driver Disable Register -#define PIO_MDSR (88) // Multi-driver Status Register -#define PIO_PPUDR (96) // Pull-up Disable Register -#define PIO_PPUER (100) // Pull-up Enable Register -#define PIO_PPUSR (104) // Pull-up Status Register -#define PIO_ASR (112) // Select A Register -#define PIO_BSR (116) // Select B Register -#define PIO_ABSR (120) // AB Select Status Register -#define PIO_OWER (160) // Output Write Enable Register -#define PIO_OWDR (164) // Output Write Disable Register -#define PIO_OWSR (168) // Output Write Status Register - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Clock Generator Controler -// ***************************************************************************** -// *** Register offset in AT91S_CKGR structure *** -#define CKGR_MOR ( 0) // Main Oscillator Register -#define CKGR_MCFR ( 4) // Main Clock Frequency Register -#define CKGR_PLLR (12) // PLL Register -// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable -#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass -#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time -// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency -#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready -// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- -#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter -#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range -#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier -#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks -#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output -#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 -#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Power Management Controler -// ***************************************************************************** -// *** Register offset in AT91S_PMC structure *** -#define PMC_SCER ( 0) // System Clock Enable Register -#define PMC_SCDR ( 4) // System Clock Disable Register -#define PMC_SCSR ( 8) // System Clock Status Register -#define PMC_PCER (16) // Peripheral Clock Enable Register -#define PMC_PCDR (20) // Peripheral Clock Disable Register -#define PMC_PCSR (24) // Peripheral Clock Status Register -#define PMC_MOR (32) // Main Oscillator Register -#define PMC_MCFR (36) // Main Clock Frequency Register -#define PMC_PLLR (44) // PLL Register -#define PMC_MCKR (48) // Master Clock Register -#define PMC_PCKR (64) // Programmable Clock Register -#define PMC_IER (96) // Interrupt Enable Register -#define PMC_IDR (100) // Interrupt Disable Register -#define PMC_SR (104) // Status Register -#define PMC_IMR (108) // Interrupt Mask Register -// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock -#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock -#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output -// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- -// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- -// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- -// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection -#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected -#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected -#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected -#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler -#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock -#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 -#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 -#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 -#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 -#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 -#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 -// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask -#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask -#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask -// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Reset Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_RSTC structure *** -#define RSTC_RCR ( 0) // Reset Control Register -#define RSTC_RSR ( 4) // Reset Status Register -#define RSTC_RMR ( 8) // Reset Mode Register -// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- -#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset -#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset -#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset -#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password -// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- -#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status -#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status -#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type -#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. -#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. -#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. -#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured. -#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level -#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. -// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- -#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable -#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable -#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Enable -#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_RTTC structure *** -#define RTTC_RTMR ( 0) // Real-time Mode Register -#define RTTC_RTAR ( 4) // Real-time Alarm Register -#define RTTC_RTVR ( 8) // Real-time Value Register -#define RTTC_RTSR (12) // Real-time Status Register -// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- -#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value -#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable -#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable -#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart -// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- -#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value -// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- -#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value -// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- -#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status -#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_PITC structure *** -#define PITC_PIMR ( 0) // Period Interval Mode Register -#define PITC_PISR ( 4) // Period Interval Status Register -#define PITC_PIVR ( 8) // Period Interval Value Register -#define PITC_PIIR (12) // Period Interval Image Register -// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- -#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value -#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled -#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable -// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- -#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status -// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- -#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value -#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter -// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_WDTC structure *** -#define WDTC_WDCR ( 0) // Watchdog Control Register -#define WDTC_WDMR ( 4) // Watchdog Mode Register -#define WDTC_WDSR ( 8) // Watchdog Status Register -// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- -#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart -#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password -// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- -#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable -#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable -#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable -#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value -#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt -#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt -// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- -#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow -#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_VREG structure *** -#define VREG_MR ( 0) // Voltage Regulator Mode Register -// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- -#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Memory Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_MC structure *** -#define MC_RCR ( 0) // MC Remap Control Register -#define MC_ASR ( 4) // MC Abort Status Register -#define MC_AASR ( 8) // MC Abort Address Status Register -#define MC_FMR (96) // MC Flash Mode Register -#define MC_FCR (100) // MC Flash Command Register -#define MC_FSR (104) // MC Flash Status Register -// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit -// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status -#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status -#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status -#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte -#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word -#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word -#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status -#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read -#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write -#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch -#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source -#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source -#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source -#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source -// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- -#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready -#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error -#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error -#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming -#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State -#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations -#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations -#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations -#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations -#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number -// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- -#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command -#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN. -#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. -#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. -#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits. -#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits. -#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit. -#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number -#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key -// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- -#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status -#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status -#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status -#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status -#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status -#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status -#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status -#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status -#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status -#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status -#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status -#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status -#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status -#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status -#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status -#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status -#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status -#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status -#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status -#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status -#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status -#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status -#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Serial Parallel Interface -// ***************************************************************************** -// *** Register offset in AT91S_SPI structure *** -#define SPI_CR ( 0) // Control Register -#define SPI_MR ( 4) // Mode Register -#define SPI_RDR ( 8) // Receive Data Register -#define SPI_TDR (12) // Transmit Data Register -#define SPI_SR (16) // Status Register -#define SPI_IER (20) // Interrupt Enable Register -#define SPI_IDR (24) // Interrupt Disable Register -#define SPI_IMR (28) // Interrupt Mask Register -#define SPI_CSR (48) // Chip Select Register -#define SPI_RPR (256) // Receive Pointer Register -#define SPI_RCR (260) // Receive Counter Register -#define SPI_TPR (264) // Transmit Pointer Register -#define SPI_TCR (268) // Transmit Counter Register -#define SPI_RNPR (272) // Receive Next Pointer Register -#define SPI_RNCR (276) // Receive Next Counter Register -#define SPI_TNPR (280) // Transmit Next Pointer Register -#define SPI_TNCR (284) // Transmit Next Counter Register -#define SPI_PTCR (288) // PDC Transfer Control Register -#define SPI_PTSR (292) // PDC Transfer Status Register -// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable -#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable -#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset -#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer -// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode -#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select -#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select -#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select -#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode -#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection -#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection -#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection -#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select -#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects -// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data -#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data -#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full -#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty -#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error -#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status -#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer -#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer -#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt -#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt -#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt -#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt -#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status -// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity -#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase -#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer -#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer -#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer -#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer -#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer -#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer -#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer -#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer -#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer -#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer -#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer -#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK -#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Usart -// ***************************************************************************** -// *** Register offset in AT91S_USART structure *** -#define US_CR ( 0) // Control Register -#define US_MR ( 4) // Mode Register -#define US_IER ( 8) // Interrupt Enable Register -#define US_IDR (12) // Interrupt Disable Register -#define US_IMR (16) // Interrupt Mask Register -#define US_CSR (20) // Channel Status Register -#define US_RHR (24) // Receiver Holding Register -#define US_THR (28) // Transmitter Holding Register -#define US_BRGR (32) // Baud Rate Generator Register -#define US_RTOR (36) // Receiver Time-out Register -#define US_TTGR (40) // Transmitter Time-guard Register -#define US_FIDI (64) // FI_DI_Ratio Register -#define US_NER (68) // Nb Errors Register -#define US_IF (76) // IRDA_FILTER Register -#define US_RPR (256) // Receive Pointer Register -#define US_RCR (260) // Receive Counter Register -#define US_TPR (264) // Transmit Pointer Register -#define US_TCR (268) // Transmit Counter Register -#define US_RNPR (272) // Receive Next Pointer Register -#define US_RNCR (276) // Receive Next Counter Register -#define US_TNPR (280) // Transmit Next Pointer Register -#define US_TNCR (284) // Transmit Next Counter Register -#define US_PTCR (288) // PDC Transfer Control Register -#define US_PTSR (292) // PDC Transfer Status Register -// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break -#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break -#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out -#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address -#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations -#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge -#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out -#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable -#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable -#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable -#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable -// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode -#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal -#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 -#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking -#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem -#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 -#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 -#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA -#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking -#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock -#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 -#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) -#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) -#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits -#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits -#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits -#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits -#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select -#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits -#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit -#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits -#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order -#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length -#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select -#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode -#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge -#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK -#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions -#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter -// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break -#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out -#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached -#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge -#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag -#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag -#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag -#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag -// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input -#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input -#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input -#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_SSC structure *** -#define SSC_CR ( 0) // Control Register -#define SSC_CMR ( 4) // Clock Mode Register -#define SSC_RCMR (16) // Receive Clock ModeRegister -#define SSC_RFMR (20) // Receive Frame Mode Register -#define SSC_TCMR (24) // Transmit Clock Mode Register -#define SSC_TFMR (28) // Transmit Frame Mode Register -#define SSC_RHR (32) // Receive Holding Register -#define SSC_THR (36) // Transmit Holding Register -#define SSC_RSHR (48) // Receive Sync Holding Register -#define SSC_TSHR (52) // Transmit Sync Holding Register -#define SSC_SR (64) // Status Register -#define SSC_IER (68) // Interrupt Enable Register -#define SSC_IDR (72) // Interrupt Disable Register -#define SSC_IMR (76) // Interrupt Mask Register -#define SSC_RPR (256) // Receive Pointer Register -#define SSC_RCR (260) // Receive Counter Register -#define SSC_TPR (264) // Transmit Pointer Register -#define SSC_TCR (268) // Transmit Counter Register -#define SSC_RNPR (272) // Receive Next Pointer Register -#define SSC_RNCR (276) // Receive Next Counter Register -#define SSC_TNPR (280) // Transmit Next Pointer Register -#define SSC_TNCR (284) // Transmit Next Counter Register -#define SSC_PTCR (288) // PDC Transfer Control Register -#define SSC_PTSR (292) // PDC Transfer Status Register -// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable -#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable -#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable -#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable -#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset -// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection -#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock -#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal -#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin -#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection -#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output -#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion -#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection -#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start -#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input -#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input -#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input -#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input -#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input -#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input -#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 -#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay -#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection -// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length -#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode -#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First -#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame -#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length -#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection -#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection -// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value -#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable -// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready -#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty -#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission -#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty -#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready -#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun -#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception -#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full -#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync -#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync -#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable -#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable -// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Two-wire Interface -// ***************************************************************************** -// *** Register offset in AT91S_TWI structure *** -#define TWI_CR ( 0) // Control Register -#define TWI_MMR ( 4) // Master Mode Register -#define TWI_IADR (12) // Internal Address Register -#define TWI_CWGR (16) // Clock Waveform Generator Register -#define TWI_SR (32) // Status Register -#define TWI_IER (36) // Interrupt Enable Register -#define TWI_IDR (40) // Interrupt Disable Register -#define TWI_IMR (44) // Interrupt Mask Register -#define TWI_RHR (48) // Receive Holding Register -#define TWI_THR (52) // Transmit Holding Register -// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition -#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition -#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled -#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled -#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset -// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size -#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address -#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address -#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address -#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address -#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction -#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address -// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider -#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider -#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider -// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed -#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY -#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY -#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error -#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error -#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged -// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR PWMC Channel Interface -// ***************************************************************************** -// *** Register offset in AT91S_PWMC_CH structure *** -#define PWMC_CMR ( 0) // Channel Mode Register -#define PWMC_CDTYR ( 4) // Channel Duty Cycle Register -#define PWMC_CPRDR ( 8) // Channel Period Register -#define PWMC_CCNTR (12) // Channel Counter Register -#define PWMC_CUPDR (16) // Channel Update Register -#define PWMC_Reserved (20) // Reserved -// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- -#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx -#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) -#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment -#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity -#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period -// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- -#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle -// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- -#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period -// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- -#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter -// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- -#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_PWMC structure *** -#define PWMC_MR ( 0) // PWMC Mode Register -#define PWMC_ENA ( 4) // PWMC Enable Register -#define PWMC_DIS ( 8) // PWMC Disable Register -#define PWMC_SR (12) // PWMC Status Register -#define PWMC_IER (16) // PWMC Interrupt Enable Register -#define PWMC_IDR (20) // PWMC Interrupt Disable Register -#define PWMC_IMR (24) // PWMC Interrupt Mask Register -#define PWMC_ISR (28) // PWMC Interrupt Status Register -#define PWMC_VR (252) // PWMC Version Register -#define PWMC_CH (512) // PWMC Channel -// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- -#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. -#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A -#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) -#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. -#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B -#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) -// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- -#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 -#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 -#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 -#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 -// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- -// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- -// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- -// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- -// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- -// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Device Interface -// ***************************************************************************** -// *** Register offset in AT91S_UDP structure *** -#define UDP_NUM ( 0) // Frame Number Register -#define UDP_GLBSTATE ( 4) // Global State Register -#define UDP_FADDR ( 8) // Function Address Register -#define UDP_IER (16) // Interrupt Enable Register -#define UDP_IDR (20) // Interrupt Disable Register -#define UDP_IMR (24) // Interrupt Mask Register -#define UDP_ISR (28) // Interrupt Status Register -#define UDP_ICR (32) // Interrupt Clear Register -#define UDP_RSTEP (40) // Reset Endpoint Register -#define UDP_CSR (48) // Endpoint Control and Status Register -#define UDP_FDR (80) // Endpoint FIFO Data Register -#define UDP_TXVC (116) // Transceiver Control Register -// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats -#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error -#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK -// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable -#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured -#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume -#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host -#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable -// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value -#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable -// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt -#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt -#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt -#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt -#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt -#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt -#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt -#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt -#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt -// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt -// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 -#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 -#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 -#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 -#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4 -#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5 -// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR -#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 -#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) -#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) -#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready -#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction -#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type -#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control -#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT -#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT -#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT -#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN -#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN -#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN -#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle -#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable -#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO -// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- -#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) -#define AT91C_UDP_PUON (0x1 << 9) // (UDP) Pull-up ON - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// ***************************************************************************** -// *** Register offset in AT91S_TC structure *** -#define TC_CCR ( 0) // Channel Control Register -#define TC_CMR ( 4) // Channel Mode Register (Capture Mode / Waveform Mode) -#define TC_CV (16) // Counter Value -#define TC_RA (20) // Register A -#define TC_RB (24) // Register B -#define TC_RC (28) // Register C -#define TC_SR (32) // Status Register -#define TC_IER (36) // Interrupt Enable Register -#define TC_IDR (40) // Interrupt Disable Register -#define TC_IMR (44) // Interrupt Mask Register -// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command -#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command -#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command -// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection -#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK -#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 -#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 -#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 -#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert -#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection -#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal -#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock -#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock -#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock -#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare -#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading -#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare -#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading -#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection -#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None -#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection -#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None -#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection -#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input -#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output -#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output -#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output -#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection -#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable -#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection -#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare -#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable -#define AT91C_TC_WAVE (0x1 << 15) // (TC) -#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA -#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none -#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set -#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear -#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle -#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection -#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None -#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA -#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA -#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none -#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set -#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear -#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle -#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection -#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None -#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA -#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA -#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none -#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set -#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear -#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle -#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA -#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none -#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set -#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear -#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle -#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB -#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none -#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set -#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear -#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle -#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB -#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none -#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set -#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear -#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle -#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB -#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none -#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set -#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear -#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle -#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB -#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none -#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set -#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear -#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle -// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow -#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun -#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare -#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare -#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare -#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading -#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading -#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger -#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling -#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror -#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror -// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Interface -// ***************************************************************************** -// *** Register offset in AT91S_TCB structure *** -#define TCB_TC0 ( 0) // TC Channel 0 -#define TCB_TC1 (64) // TC Channel 1 -#define TCB_TC2 (128) // TC Channel 2 -#define TCB_BCR (192) // TC Block Control Register -#define TCB_BMR (196) // TC Block Mode Register -// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command -// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection -#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 -#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 -#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection -#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 -#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 -#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection -#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 -#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface -// ***************************************************************************** -// *** Register offset in AT91S_CAN_MB structure *** -#define CAN_MB_MMR ( 0) // MailBox Mode Register -#define CAN_MB_MAM ( 4) // MailBox Acceptance Mask Register -#define CAN_MB_MID ( 8) // MailBox ID Register -#define CAN_MB_MFID (12) // MailBox Family ID Register -#define CAN_MB_MSR (16) // MailBox Status Register -#define CAN_MB_MDL (20) // MailBox Data Low Register -#define CAN_MB_MDH (24) // MailBox Data High Register -#define CAN_MB_MCR (28) // MailBox Control Register -// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- -#define AT91C_CAN_MTIMEMARK (0xFFFF << 0) // (CAN_MB) Mailbox Timemark -#define AT91C_CAN_PRIOR (0xF << 16) // (CAN_MB) Mailbox Priority -#define AT91C_CAN_MOT (0x7 << 24) // (CAN_MB) Mailbox Object Type -#define AT91C_CAN_MOT_DIS (0x0 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RX (0x1 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RXOVERWRITE (0x2 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_TX (0x3 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_CONSUMER (0x4 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_PRODUCER (0x5 << 24) // (CAN_MB) -// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- -#define AT91C_CAN_MIDvB (0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode -#define AT91C_CAN_MIDvA (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode -#define AT91C_CAN_MIDE (0x1 << 29) // (CAN_MB) Identifier Version -// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- -// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- -// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- -#define AT91C_CAN_MTIMESTAMP (0xFFFF << 0) // (CAN_MB) Timer Value -#define AT91C_CAN_MDLC (0xF << 16) // (CAN_MB) Mailbox Data Length Code -#define AT91C_CAN_MRTR (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request -#define AT91C_CAN_MABT (0x1 << 22) // (CAN_MB) Mailbox Message Abort -#define AT91C_CAN_MRDY (0x1 << 23) // (CAN_MB) Mailbox Ready -#define AT91C_CAN_MMI (0x1 << 24) // (CAN_MB) Mailbox Message Ignored -// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- -// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- -// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- -#define AT91C_CAN_MACR (0x1 << 22) // (CAN_MB) Abort Request for Mailbox -#define AT91C_CAN_MTCR (0x1 << 23) // (CAN_MB) Mailbox Transfer Command - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network Interface -// ***************************************************************************** -// *** Register offset in AT91S_CAN structure *** -#define CAN_MR ( 0) // Mode Register -#define CAN_IER ( 4) // Interrupt Enable Register -#define CAN_IDR ( 8) // Interrupt Disable Register -#define CAN_IMR (12) // Interrupt Mask Register -#define CAN_SR (16) // Status Register -#define CAN_BR (20) // Baudrate Register -#define CAN_TIM (24) // Timer Register -#define CAN_TIMESTP (28) // Time Stamp Register -#define CAN_ECR (32) // Error Counter Register -#define CAN_TCR (36) // Transfer Command Register -#define CAN_ACR (40) // Abort Command Register -#define CAN_VR (252) // Version Register -#define CAN_MB0 (512) // CAN Mailbox 0 -#define CAN_MB1 (544) // CAN Mailbox 1 -#define CAN_MB2 (576) // CAN Mailbox 2 -#define CAN_MB3 (608) // CAN Mailbox 3 -#define CAN_MB4 (640) // CAN Mailbox 4 -#define CAN_MB5 (672) // CAN Mailbox 5 -#define CAN_MB6 (704) // CAN Mailbox 6 -#define CAN_MB7 (736) // CAN Mailbox 7 -#define CAN_MB8 (768) // CAN Mailbox 8 -#define CAN_MB9 (800) // CAN Mailbox 9 -#define CAN_MB10 (832) // CAN Mailbox 10 -#define CAN_MB11 (864) // CAN Mailbox 11 -#define CAN_MB12 (896) // CAN Mailbox 12 -#define CAN_MB13 (928) // CAN Mailbox 13 -#define CAN_MB14 (960) // CAN Mailbox 14 -#define CAN_MB15 (992) // CAN Mailbox 15 -// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- -#define AT91C_CAN_CANEN (0x1 << 0) // (CAN) CAN Controller Enable -#define AT91C_CAN_LPM (0x1 << 1) // (CAN) Disable/Enable Low Power Mode -#define AT91C_CAN_ABM (0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode -#define AT91C_CAN_OVL (0x1 << 3) // (CAN) Disable/Enable Overload Frame -#define AT91C_CAN_TEOF (0x1 << 4) // (CAN) Time Stamp messages at each end of Frame -#define AT91C_CAN_TTM (0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode -#define AT91C_CAN_TIMFRZ (0x1 << 6) // (CAN) Enable Timer Freeze -#define AT91C_CAN_DRPT (0x1 << 7) // (CAN) Disable Repeat -// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- -#define AT91C_CAN_MB0 (0x1 << 0) // (CAN) Mailbox 0 Flag -#define AT91C_CAN_MB1 (0x1 << 1) // (CAN) Mailbox 1 Flag -#define AT91C_CAN_MB2 (0x1 << 2) // (CAN) Mailbox 2 Flag -#define AT91C_CAN_MB3 (0x1 << 3) // (CAN) Mailbox 3 Flag -#define AT91C_CAN_MB4 (0x1 << 4) // (CAN) Mailbox 4 Flag -#define AT91C_CAN_MB5 (0x1 << 5) // (CAN) Mailbox 5 Flag -#define AT91C_CAN_MB6 (0x1 << 6) // (CAN) Mailbox 6 Flag -#define AT91C_CAN_MB7 (0x1 << 7) // (CAN) Mailbox 7 Flag -#define AT91C_CAN_MB8 (0x1 << 8) // (CAN) Mailbox 8 Flag -#define AT91C_CAN_MB9 (0x1 << 9) // (CAN) Mailbox 9 Flag -#define AT91C_CAN_MB10 (0x1 << 10) // (CAN) Mailbox 10 Flag -#define AT91C_CAN_MB11 (0x1 << 11) // (CAN) Mailbox 11 Flag -#define AT91C_CAN_MB12 (0x1 << 12) // (CAN) Mailbox 12 Flag -#define AT91C_CAN_MB13 (0x1 << 13) // (CAN) Mailbox 13 Flag -#define AT91C_CAN_MB14 (0x1 << 14) // (CAN) Mailbox 14 Flag -#define AT91C_CAN_MB15 (0x1 << 15) // (CAN) Mailbox 15 Flag -#define AT91C_CAN_ERRA (0x1 << 16) // (CAN) Error Active Mode Flag -#define AT91C_CAN_WARN (0x1 << 17) // (CAN) Warning Limit Flag -#define AT91C_CAN_ERRP (0x1 << 18) // (CAN) Error Passive Mode Flag -#define AT91C_CAN_BOFF (0x1 << 19) // (CAN) Bus Off Mode Flag -#define AT91C_CAN_SLEEP (0x1 << 20) // (CAN) Sleep Flag -#define AT91C_CAN_WAKEUP (0x1 << 21) // (CAN) Wakeup Flag -#define AT91C_CAN_TOVF (0x1 << 22) // (CAN) Timer Overflow Flag -#define AT91C_CAN_TSTP (0x1 << 23) // (CAN) Timestamp Flag -#define AT91C_CAN_CERR (0x1 << 24) // (CAN) CRC Error -#define AT91C_CAN_SERR (0x1 << 25) // (CAN) Stuffing Error -#define AT91C_CAN_AERR (0x1 << 26) // (CAN) Acknowledgment Error -#define AT91C_CAN_FERR (0x1 << 27) // (CAN) Form Error -#define AT91C_CAN_BERR (0x1 << 28) // (CAN) Bit Error -// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- -// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- -// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- -#define AT91C_CAN_RBSY (0x1 << 29) // (CAN) Receiver Busy -#define AT91C_CAN_TBSY (0x1 << 30) // (CAN) Transmitter Busy -#define AT91C_CAN_OVLY (0x1 << 31) // (CAN) Overload Busy -// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- -#define AT91C_CAN_PHASE2 (0x7 << 0) // (CAN) Phase 2 segment -#define AT91C_CAN_PHASE1 (0x7 << 4) // (CAN) Phase 1 segment -#define AT91C_CAN_PROPAG (0x7 << 8) // (CAN) Programmation time segment -#define AT91C_CAN_SYNC (0x3 << 12) // (CAN) Re-synchronization jump width segment -#define AT91C_CAN_BRP (0x7F << 16) // (CAN) Baudrate Prescaler -#define AT91C_CAN_SMP (0x1 << 24) // (CAN) Sampling mode -// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- -#define AT91C_CAN_TIMER (0xFFFF << 0) // (CAN) Timer field -// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- -// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- -#define AT91C_CAN_REC (0xFF << 0) // (CAN) Receive Error Counter -#define AT91C_CAN_TEC (0xFF << 16) // (CAN) Transmit Error Counter -// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- -#define AT91C_CAN_TIMRST (0x1 << 31) // (CAN) Timer Reset Field -// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 -// ***************************************************************************** -// *** Register offset in AT91S_EMAC structure *** -#define EMAC_NCR ( 0) // Network Control Register -#define EMAC_NCFGR ( 4) // Network Configuration Register -#define EMAC_NSR ( 8) // Network Status Register -#define EMAC_TSR (20) // Transmit Status Register -#define EMAC_RBQP (24) // Receive Buffer Queue Pointer -#define EMAC_TBQP (28) // Transmit Buffer Queue Pointer -#define EMAC_RSR (32) // Receive Status Register -#define EMAC_ISR (36) // Interrupt Status Register -#define EMAC_IER (40) // Interrupt Enable Register -#define EMAC_IDR (44) // Interrupt Disable Register -#define EMAC_IMR (48) // Interrupt Mask Register -#define EMAC_MAN (52) // PHY Maintenance Register -#define EMAC_PTR (56) // Pause Time Register -#define EMAC_PFR (60) // Pause Frames received Register -#define EMAC_FTO (64) // Frames Transmitted OK Register -#define EMAC_SCF (68) // Single Collision Frame Register -#define EMAC_MCF (72) // Multiple Collision Frame Register -#define EMAC_FRO (76) // Frames Received OK Register -#define EMAC_FCSE (80) // Frame Check Sequence Error Register -#define EMAC_ALE (84) // Alignment Error Register -#define EMAC_DTF (88) // Deferred Transmission Frame Register -#define EMAC_LCOL (92) // Late Collision Register -#define EMAC_ECOL (96) // Excessive Collision Register -#define EMAC_TUND (100) // Transmit Underrun Error Register -#define EMAC_CSE (104) // Carrier Sense Error Register -#define EMAC_RRE (108) // Receive Ressource Error Register -#define EMAC_ROV (112) // Receive Overrun Errors Register -#define EMAC_RSE (116) // Receive Symbol Errors Register -#define EMAC_ELE (120) // Excessive Length Errors Register -#define EMAC_RJA (124) // Receive Jabbers Register -#define EMAC_USF (128) // Undersize Frames Register -#define EMAC_STE (132) // SQE Test Error Register -#define EMAC_RLE (136) // Receive Length Field Mismatch Register -#define EMAC_TPF (140) // Transmitted Pause Frames Register -#define EMAC_HRB (144) // Hash Address Bottom[31:0] -#define EMAC_HRT (148) // Hash Address Top[63:32] -#define EMAC_SA1L (152) // Specific Address 1 Bottom, First 4 bytes -#define EMAC_SA1H (156) // Specific Address 1 Top, Last 2 bytes -#define EMAC_SA2L (160) // Specific Address 2 Bottom, First 4 bytes -#define EMAC_SA2H (164) // Specific Address 2 Top, Last 2 bytes -#define EMAC_SA3L (168) // Specific Address 3 Bottom, First 4 bytes -#define EMAC_SA3H (172) // Specific Address 3 Top, Last 2 bytes -#define EMAC_SA4L (176) // Specific Address 4 Bottom, First 4 bytes -#define EMAC_SA4H (180) // Specific Address 4 Top, Last 2 bytes -#define EMAC_TID (184) // Type ID Checking Register -#define EMAC_TPQ (188) // Transmit Pause Quantum Register -#define EMAC_USRIO (192) // USER Input/Output Register -#define EMAC_WOL (196) // Wake On LAN Register -#define EMAC_REV (252) // Revision Register -// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- -#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. -#define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local. -#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable. -#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable. -#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable. -#define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers. -#define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers. -#define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers. -#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure. -#define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission. -#define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt. -#define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame -#define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame -// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- -#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed. -#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex. -#define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames. -#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames. -#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast. -#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable -#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable. -#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes. -#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable. -#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC) -#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8 -#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16 -#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32 -#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64 -#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC) -#define AT91C_EMAC_PAE (0x1 << 13) // (EMAC) -#define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC) -#define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer -#define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable -#define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS -#define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC) -#define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS -// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- -#define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC) -#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC) -#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC) -// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- -#define AT91C_EMAC_UBR (0x1 << 0) // (EMAC) -#define AT91C_EMAC_COL (0x1 << 1) // (EMAC) -#define AT91C_EMAC_RLES (0x1 << 2) // (EMAC) -#define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go -#define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame -#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC) -#define AT91C_EMAC_UND (0x1 << 6) // (EMAC) -// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- -#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC) -#define AT91C_EMAC_REC (0x1 << 1) // (EMAC) -#define AT91C_EMAC_OVR (0x1 << 2) // (EMAC) -// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- -#define AT91C_EMAC_MFD (0x1 << 0) // (EMAC) -#define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC) -#define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC) -#define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC) -#define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC) -#define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC) -#define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC) -#define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC) -#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC) -#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC) -#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC) -#define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC) -#define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC) -// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- -// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- -// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- -// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- -#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC) -#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC) -#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC) -#define AT91C_EMAC_RW (0x3 << 28) // (EMAC) -#define AT91C_EMAC_SOF (0x3 << 30) // (EMAC) -// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- -#define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII -// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- -#define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address -#define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable -#define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable -#define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable -// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- -#define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC) - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Analog to Digital Convertor -// ***************************************************************************** -// *** Register offset in AT91S_ADC structure *** -#define ADC_CR ( 0) // ADC Control Register -#define ADC_MR ( 4) // ADC Mode Register -#define ADC_CHER (16) // ADC Channel Enable Register -#define ADC_CHDR (20) // ADC Channel Disable Register -#define ADC_CHSR (24) // ADC Channel Status Register -#define ADC_SR (28) // ADC Status Register -#define ADC_LCDR (32) // ADC Last Converted Data Register -#define ADC_IER (36) // ADC Interrupt Enable Register -#define ADC_IDR (40) // ADC Interrupt Disable Register -#define ADC_IMR (44) // ADC Interrupt Mask Register -#define ADC_CDR0 (48) // ADC Channel Data Register 0 -#define ADC_CDR1 (52) // ADC Channel Data Register 1 -#define ADC_CDR2 (56) // ADC Channel Data Register 2 -#define ADC_CDR3 (60) // ADC Channel Data Register 3 -#define ADC_CDR4 (64) // ADC Channel Data Register 4 -#define ADC_CDR5 (68) // ADC Channel Data Register 5 -#define ADC_CDR6 (72) // ADC Channel Data Register 6 -#define ADC_CDR7 (76) // ADC Channel Data Register 7 -#define ADC_RPR (256) // Receive Pointer Register -#define ADC_RCR (260) // Receive Counter Register -#define ADC_TPR (264) // Transmit Pointer Register -#define ADC_TCR (268) // Transmit Counter Register -#define ADC_RNPR (272) // Receive Next Pointer Register -#define ADC_RNCR (276) // Receive Next Counter Register -#define ADC_TNPR (280) // Transmit Next Pointer Register -#define ADC_TNCR (284) // Transmit Next Counter Register -#define ADC_PTCR (288) // PDC Transfer Control Register -#define ADC_PTSR (292) // PDC Transfer Status Register -// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- -#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset -#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion -// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- -#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable -#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software -#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. -#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection -#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 -#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 -#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 -#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 -#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 -#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 -#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger -#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. -#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution -#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution -#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode -#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection -#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time -#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time -// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- -#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 -#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 -#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 -#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 -#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 -#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 -#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 -#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 -// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- -// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- -// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- -#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion -#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion -#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion -#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion -#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion -#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion -#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion -#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion -#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error -#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error -#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error -#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error -#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error -#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error -#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error -#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error -#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready -#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun -#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer -#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt -// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- -#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted -// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- -// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- -// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- -// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- -#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data -// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- -// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- -// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- -// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- -// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- -// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- -// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Encryption Standard -// ***************************************************************************** -// *** Register offset in AT91S_AES structure *** -#define AES_CR ( 0) // Control Register -#define AES_MR ( 4) // Mode Register -#define AES_IER (16) // Interrupt Enable Register -#define AES_IDR (20) // Interrupt Disable Register -#define AES_IMR (24) // Interrupt Mask Register -#define AES_ISR (28) // Interrupt Status Register -#define AES_KEYWxR (32) // Key Word x Register -#define AES_IDATAxR (64) // Input Data x Register -#define AES_ODATAxR (80) // Output Data x Register -#define AES_IVxR (96) // Initialization Vector x Register -#define AES_VR (252) // AES Version Register -#define AES_RPR (256) // Receive Pointer Register -#define AES_RCR (260) // Receive Counter Register -#define AES_TPR (264) // Transmit Pointer Register -#define AES_TCR (268) // Transmit Counter Register -#define AES_RNPR (272) // Receive Next Pointer Register -#define AES_RNCR (276) // Receive Next Counter Register -#define AES_TNPR (280) // Transmit Next Pointer Register -#define AES_TNCR (284) // Transmit Next Counter Register -#define AES_PTCR (288) // PDC Transfer Control Register -#define AES_PTSR (292) // PDC Transfer Status Register -// -------- AES_CR : (AES Offset: 0x0) Control Register -------- -#define AT91C_AES_START (0x1 << 0) // (AES) Starts Processing -#define AT91C_AES_SWRST (0x1 << 8) // (AES) Software Reset -#define AT91C_AES_LOADSEED (0x1 << 16) // (AES) Random Number Generator Seed Loading -// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- -#define AT91C_AES_CIPHER (0x1 << 0) // (AES) Processing Mode -#define AT91C_AES_PROCDLY (0xF << 4) // (AES) Processing Delay -#define AT91C_AES_SMOD (0x3 << 8) // (AES) Start Mode -#define AT91C_AES_SMOD_MANUAL (0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. -#define AT91C_AES_SMOD_AUTO (0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). -#define AT91C_AES_SMOD_PDC (0x2 << 8) // (AES) PDC Mode (cf datasheet). -#define AT91C_AES_OPMOD (0x7 << 12) // (AES) Operation Mode -#define AT91C_AES_OPMOD_ECB (0x0 << 12) // (AES) ECB Electronic CodeBook mode. -#define AT91C_AES_OPMOD_CBC (0x1 << 12) // (AES) CBC Cipher Block Chaining mode. -#define AT91C_AES_OPMOD_OFB (0x2 << 12) // (AES) OFB Output Feedback mode. -#define AT91C_AES_OPMOD_CFB (0x3 << 12) // (AES) CFB Cipher Feedback mode. -#define AT91C_AES_OPMOD_CTR (0x4 << 12) // (AES) CTR Counter mode. -#define AT91C_AES_LOD (0x1 << 15) // (AES) Last Output Data Mode -#define AT91C_AES_CFBS (0x7 << 16) // (AES) Cipher Feedback Data Size -#define AT91C_AES_CFBS_128_BIT (0x0 << 16) // (AES) 128-bit. -#define AT91C_AES_CFBS_64_BIT (0x1 << 16) // (AES) 64-bit. -#define AT91C_AES_CFBS_32_BIT (0x2 << 16) // (AES) 32-bit. -#define AT91C_AES_CFBS_16_BIT (0x3 << 16) // (AES) 16-bit. -#define AT91C_AES_CFBS_8_BIT (0x4 << 16) // (AES) 8-bit. -#define AT91C_AES_CKEY (0xF << 20) // (AES) Countermeasure Key -#define AT91C_AES_CTYPE (0x1F << 24) // (AES) Countermeasure Type -#define AT91C_AES_CTYPE_TYPE1_EN (0x1 << 24) // (AES) Countermeasure type 1 is enabled. -#define AT91C_AES_CTYPE_TYPE2_EN (0x2 << 24) // (AES) Countermeasure type 2 is enabled. -#define AT91C_AES_CTYPE_TYPE3_EN (0x4 << 24) // (AES) Countermeasure type 3 is enabled. -#define AT91C_AES_CTYPE_TYPE4_EN (0x8 << 24) // (AES) Countermeasure type 4 is enabled. -#define AT91C_AES_CTYPE_TYPE5_EN (0x10 << 24) // (AES) Countermeasure type 5 is enabled. -// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- -#define AT91C_AES_DATRDY (0x1 << 0) // (AES) DATRDY -#define AT91C_AES_ENDRX (0x1 << 1) // (AES) PDC Read Buffer End -#define AT91C_AES_ENDTX (0x1 << 2) // (AES) PDC Write Buffer End -#define AT91C_AES_RXBUFF (0x1 << 3) // (AES) PDC Read Buffer Full -#define AT91C_AES_TXBUFE (0x1 << 4) // (AES) PDC Write Buffer Empty -#define AT91C_AES_URAD (0x1 << 8) // (AES) Unspecified Register Access Detection -// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- -// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- -// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- -#define AT91C_AES_URAT (0x7 << 12) // (AES) Unspecified Register Access Type Status -#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (AES) Input data register written during the data processing in PDC mode. -#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (AES) Output data register read during the data processing. -#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (AES) Mode register written during the data processing. -#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY (0x3 << 12) // (AES) Output data register read during the sub-keys generation. -#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY (0x4 << 12) // (AES) Mode register written during the sub-keys generation. -#define AT91C_AES_URAT_WO_REG_READ (0x5 << 12) // (AES) Write-only register read access. - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard -// ***************************************************************************** -// *** Register offset in AT91S_TDES structure *** -#define TDES_CR ( 0) // Control Register -#define TDES_MR ( 4) // Mode Register -#define TDES_IER (16) // Interrupt Enable Register -#define TDES_IDR (20) // Interrupt Disable Register -#define TDES_IMR (24) // Interrupt Mask Register -#define TDES_ISR (28) // Interrupt Status Register -#define TDES_KEY1WxR (32) // Key 1 Word x Register -#define TDES_KEY2WxR (40) // Key 2 Word x Register -#define TDES_KEY3WxR (48) // Key 3 Word x Register -#define TDES_IDATAxR (64) // Input Data x Register -#define TDES_ODATAxR (80) // Output Data x Register -#define TDES_IVxR (96) // Initialization Vector x Register -#define TDES_VR (252) // TDES Version Register -#define TDES_RPR (256) // Receive Pointer Register -#define TDES_RCR (260) // Receive Counter Register -#define TDES_TPR (264) // Transmit Pointer Register -#define TDES_TCR (268) // Transmit Counter Register -#define TDES_RNPR (272) // Receive Next Pointer Register -#define TDES_RNCR (276) // Receive Next Counter Register -#define TDES_TNPR (280) // Transmit Next Pointer Register -#define TDES_TNCR (284) // Transmit Next Counter Register -#define TDES_PTCR (288) // PDC Transfer Control Register -#define TDES_PTSR (292) // PDC Transfer Status Register -// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- -#define AT91C_TDES_START (0x1 << 0) // (TDES) Starts Processing -#define AT91C_TDES_SWRST (0x1 << 8) // (TDES) Software Reset -// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- -#define AT91C_TDES_CIPHER (0x1 << 0) // (TDES) Processing Mode -#define AT91C_TDES_TDESMOD (0x1 << 1) // (TDES) Single or Triple DES Mode -#define AT91C_TDES_KEYMOD (0x1 << 4) // (TDES) Key Mode -#define AT91C_TDES_SMOD (0x3 << 8) // (TDES) Start Mode -#define AT91C_TDES_SMOD_MANUAL (0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. -#define AT91C_TDES_SMOD_AUTO (0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). -#define AT91C_TDES_SMOD_PDC (0x2 << 8) // (TDES) PDC Mode (cf datasheet). -#define AT91C_TDES_OPMOD (0x3 << 12) // (TDES) Operation Mode -#define AT91C_TDES_OPMOD_ECB (0x0 << 12) // (TDES) ECB Electronic CodeBook mode. -#define AT91C_TDES_OPMOD_CBC (0x1 << 12) // (TDES) CBC Cipher Block Chaining mode. -#define AT91C_TDES_OPMOD_OFB (0x2 << 12) // (TDES) OFB Output Feedback mode. -#define AT91C_TDES_OPMOD_CFB (0x3 << 12) // (TDES) CFB Cipher Feedback mode. -#define AT91C_TDES_LOD (0x1 << 15) // (TDES) Last Output Data Mode -#define AT91C_TDES_CFBS (0x3 << 16) // (TDES) Cipher Feedback Data Size -#define AT91C_TDES_CFBS_64_BIT (0x0 << 16) // (TDES) 64-bit. -#define AT91C_TDES_CFBS_32_BIT (0x1 << 16) // (TDES) 32-bit. -#define AT91C_TDES_CFBS_16_BIT (0x2 << 16) // (TDES) 16-bit. -#define AT91C_TDES_CFBS_8_BIT (0x3 << 16) // (TDES) 8-bit. -// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- -#define AT91C_TDES_DATRDY (0x1 << 0) // (TDES) DATRDY -#define AT91C_TDES_ENDRX (0x1 << 1) // (TDES) PDC Read Buffer End -#define AT91C_TDES_ENDTX (0x1 << 2) // (TDES) PDC Write Buffer End -#define AT91C_TDES_RXBUFF (0x1 << 3) // (TDES) PDC Read Buffer Full -#define AT91C_TDES_TXBUFE (0x1 << 4) // (TDES) PDC Write Buffer Empty -#define AT91C_TDES_URAD (0x1 << 8) // (TDES) Unspecified Register Access Detection -// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- -// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- -// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- -#define AT91C_TDES_URAT (0x3 << 12) // (TDES) Unspecified Register Access Type Status -#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode. -#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (TDES) Output data register read during the data processing. -#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (TDES) Mode register written during the data processing. -#define AT91C_TDES_URAT_WO_REG_READ (0x3 << 12) // (TDES) Write-only register read access. - -// ***************************************************************************** -// REGISTER ADDRESS DEFINITION FOR AT91SAM7X128 -// ***************************************************************************** -// ========== Register definition for SYS peripheral ========== -// ========== Register definition for AIC peripheral ========== -#define AT91C_AIC_IVR (0xFFFFF100) // (AIC) IRQ Vector Register -#define AT91C_AIC_SMR (0xFFFFF000) // (AIC) Source Mode Register -#define AT91C_AIC_FVR (0xFFFFF104) // (AIC) FIQ Vector Register -#define AT91C_AIC_DCR (0xFFFFF138) // (AIC) Debug Control Register (Protect) -#define AT91C_AIC_EOICR (0xFFFFF130) // (AIC) End of Interrupt Command Register -#define AT91C_AIC_SVR (0xFFFFF080) // (AIC) Source Vector Register -#define AT91C_AIC_FFSR (0xFFFFF148) // (AIC) Fast Forcing Status Register -#define AT91C_AIC_ICCR (0xFFFFF128) // (AIC) Interrupt Clear Command Register -#define AT91C_AIC_ISR (0xFFFFF108) // (AIC) Interrupt Status Register -#define AT91C_AIC_IMR (0xFFFFF110) // (AIC) Interrupt Mask Register -#define AT91C_AIC_IPR (0xFFFFF10C) // (AIC) Interrupt Pending Register -#define AT91C_AIC_FFER (0xFFFFF140) // (AIC) Fast Forcing Enable Register -#define AT91C_AIC_IECR (0xFFFFF120) // (AIC) Interrupt Enable Command Register -#define AT91C_AIC_ISCR (0xFFFFF12C) // (AIC) Interrupt Set Command Register -#define AT91C_AIC_FFDR (0xFFFFF144) // (AIC) Fast Forcing Disable Register -#define AT91C_AIC_CISR (0xFFFFF114) // (AIC) Core Interrupt Status Register -#define AT91C_AIC_IDCR (0xFFFFF124) // (AIC) Interrupt Disable Command Register -#define AT91C_AIC_SPU (0xFFFFF134) // (AIC) Spurious Vector Register -// ========== Register definition for PDC_DBGU peripheral ========== -#define AT91C_DBGU_TCR (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register -#define AT91C_DBGU_RNPR (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register -#define AT91C_DBGU_TNPR (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register -#define AT91C_DBGU_TPR (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register -#define AT91C_DBGU_RPR (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register -#define AT91C_DBGU_RCR (0xFFFFF304) // (PDC_DBGU) Receive Counter Register -#define AT91C_DBGU_RNCR (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register -#define AT91C_DBGU_PTCR (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register -#define AT91C_DBGU_PTSR (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register -#define AT91C_DBGU_TNCR (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register -// ========== Register definition for DBGU peripheral ========== -#define AT91C_DBGU_EXID (0xFFFFF244) // (DBGU) Chip ID Extension Register -#define AT91C_DBGU_BRGR (0xFFFFF220) // (DBGU) Baud Rate Generator Register -#define AT91C_DBGU_IDR (0xFFFFF20C) // (DBGU) Interrupt Disable Register -#define AT91C_DBGU_CSR (0xFFFFF214) // (DBGU) Channel Status Register -#define AT91C_DBGU_CIDR (0xFFFFF240) // (DBGU) Chip ID Register -#define AT91C_DBGU_MR (0xFFFFF204) // (DBGU) Mode Register -#define AT91C_DBGU_IMR (0xFFFFF210) // (DBGU) Interrupt Mask Register -#define AT91C_DBGU_CR (0xFFFFF200) // (DBGU) Control Register -#define AT91C_DBGU_FNTR (0xFFFFF248) // (DBGU) Force NTRST Register -#define AT91C_DBGU_THR (0xFFFFF21C) // (DBGU) Transmitter Holding Register -#define AT91C_DBGU_RHR (0xFFFFF218) // (DBGU) Receiver Holding Register -#define AT91C_DBGU_IER (0xFFFFF208) // (DBGU) Interrupt Enable Register -// ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_ODR (0xFFFFF414) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_SODR (0xFFFFF430) // (PIOA) Set Output Data Register -#define AT91C_PIOA_ISR (0xFFFFF44C) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_ABSR (0xFFFFF478) // (PIOA) AB Select Status Register -#define AT91C_PIOA_IER (0xFFFFF440) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_PPUDR (0xFFFFF460) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_IMR (0xFFFFF448) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_PER (0xFFFFF400) // (PIOA) PIO Enable Register -#define AT91C_PIOA_IFDR (0xFFFFF424) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_OWDR (0xFFFFF4A4) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_MDSR (0xFFFFF458) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_IDR (0xFFFFF444) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_ODSR (0xFFFFF438) // (PIOA) Output Data Status Register -#define AT91C_PIOA_PPUSR (0xFFFFF468) // (PIOA) Pull-up Status Register -#define AT91C_PIOA_OWSR (0xFFFFF4A8) // (PIOA) Output Write Status Register -#define AT91C_PIOA_BSR (0xFFFFF474) // (PIOA) Select B Register -#define AT91C_PIOA_OWER (0xFFFFF4A0) // (PIOA) Output Write Enable Register -#define AT91C_PIOA_IFER (0xFFFFF420) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_PDSR (0xFFFFF43C) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_PPUER (0xFFFFF464) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_OSR (0xFFFFF418) // (PIOA) Output Status Register -#define AT91C_PIOA_ASR (0xFFFFF470) // (PIOA) Select A Register -#define AT91C_PIOA_MDDR (0xFFFFF454) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_CODR (0xFFFFF434) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_MDER (0xFFFFF450) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PDR (0xFFFFF404) // (PIOA) PIO Disable Register -#define AT91C_PIOA_IFSR (0xFFFFF428) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_OER (0xFFFFF410) // (PIOA) Output Enable Register -#define AT91C_PIOA_PSR (0xFFFFF408) // (PIOA) PIO Status Register -// ========== Register definition for PIOB peripheral ========== -#define AT91C_PIOB_OWDR (0xFFFFF6A4) // (PIOB) Output Write Disable Register -#define AT91C_PIOB_MDER (0xFFFFF650) // (PIOB) Multi-driver Enable Register -#define AT91C_PIOB_PPUSR (0xFFFFF668) // (PIOB) Pull-up Status Register -#define AT91C_PIOB_IMR (0xFFFFF648) // (PIOB) Interrupt Mask Register -#define AT91C_PIOB_ASR (0xFFFFF670) // (PIOB) Select A Register -#define AT91C_PIOB_PPUDR (0xFFFFF660) // (PIOB) Pull-up Disable Register -#define AT91C_PIOB_PSR (0xFFFFF608) // (PIOB) PIO Status Register -#define AT91C_PIOB_IER (0xFFFFF640) // (PIOB) Interrupt Enable Register -#define AT91C_PIOB_CODR (0xFFFFF634) // (PIOB) Clear Output Data Register -#define AT91C_PIOB_OWER (0xFFFFF6A0) // (PIOB) Output Write Enable Register -#define AT91C_PIOB_ABSR (0xFFFFF678) // (PIOB) AB Select Status Register -#define AT91C_PIOB_IFDR (0xFFFFF624) // (PIOB) Input Filter Disable Register -#define AT91C_PIOB_PDSR (0xFFFFF63C) // (PIOB) Pin Data Status Register -#define AT91C_PIOB_IDR (0xFFFFF644) // (PIOB) Interrupt Disable Register -#define AT91C_PIOB_OWSR (0xFFFFF6A8) // (PIOB) Output Write Status Register -#define AT91C_PIOB_PDR (0xFFFFF604) // (PIOB) PIO Disable Register -#define AT91C_PIOB_ODR (0xFFFFF614) // (PIOB) Output Disable Registerr -#define AT91C_PIOB_IFSR (0xFFFFF628) // (PIOB) Input Filter Status Register -#define AT91C_PIOB_PPUER (0xFFFFF664) // (PIOB) Pull-up Enable Register -#define AT91C_PIOB_SODR (0xFFFFF630) // (PIOB) Set Output Data Register -#define AT91C_PIOB_ISR (0xFFFFF64C) // (PIOB) Interrupt Status Register -#define AT91C_PIOB_ODSR (0xFFFFF638) // (PIOB) Output Data Status Register -#define AT91C_PIOB_OSR (0xFFFFF618) // (PIOB) Output Status Register -#define AT91C_PIOB_MDSR (0xFFFFF658) // (PIOB) Multi-driver Status Register -#define AT91C_PIOB_IFER (0xFFFFF620) // (PIOB) Input Filter Enable Register -#define AT91C_PIOB_BSR (0xFFFFF674) // (PIOB) Select B Register -#define AT91C_PIOB_MDDR (0xFFFFF654) // (PIOB) Multi-driver Disable Register -#define AT91C_PIOB_OER (0xFFFFF610) // (PIOB) Output Enable Register -#define AT91C_PIOB_PER (0xFFFFF600) // (PIOB) PIO Enable Register -// ========== Register definition for CKGR peripheral ========== -#define AT91C_CKGR_MOR (0xFFFFFC20) // (CKGR) Main Oscillator Register -#define AT91C_CKGR_PLLR (0xFFFFFC2C) // (CKGR) PLL Register -#define AT91C_CKGR_MCFR (0xFFFFFC24) // (CKGR) Main Clock Frequency Register -// ========== Register definition for PMC peripheral ========== -#define AT91C_PMC_IDR (0xFFFFFC64) // (PMC) Interrupt Disable Register -#define AT91C_PMC_MOR (0xFFFFFC20) // (PMC) Main Oscillator Register -#define AT91C_PMC_PLLR (0xFFFFFC2C) // (PMC) PLL Register -#define AT91C_PMC_PCER (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register -#define AT91C_PMC_PCKR (0xFFFFFC40) // (PMC) Programmable Clock Register -#define AT91C_PMC_MCKR (0xFFFFFC30) // (PMC) Master Clock Register -#define AT91C_PMC_SCDR (0xFFFFFC04) // (PMC) System Clock Disable Register -#define AT91C_PMC_PCDR (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register -#define AT91C_PMC_SCSR (0xFFFFFC08) // (PMC) System Clock Status Register -#define AT91C_PMC_PCSR (0xFFFFFC18) // (PMC) Peripheral Clock Status Register -#define AT91C_PMC_MCFR (0xFFFFFC24) // (PMC) Main Clock Frequency Register -#define AT91C_PMC_SCER (0xFFFFFC00) // (PMC) System Clock Enable Register -#define AT91C_PMC_IMR (0xFFFFFC6C) // (PMC) Interrupt Mask Register -#define AT91C_PMC_IER (0xFFFFFC60) // (PMC) Interrupt Enable Register -#define AT91C_PMC_SR (0xFFFFFC68) // (PMC) Status Register -// ========== Register definition for RSTC peripheral ========== -#define AT91C_RSTC_RCR (0xFFFFFD00) // (RSTC) Reset Control Register -#define AT91C_RSTC_RMR (0xFFFFFD08) // (RSTC) Reset Mode Register -#define AT91C_RSTC_RSR (0xFFFFFD04) // (RSTC) Reset Status Register -// ========== Register definition for RTTC peripheral ========== -#define AT91C_RTTC_RTSR (0xFFFFFD2C) // (RTTC) Real-time Status Register -#define AT91C_RTTC_RTMR (0xFFFFFD20) // (RTTC) Real-time Mode Register -#define AT91C_RTTC_RTVR (0xFFFFFD28) // (RTTC) Real-time Value Register -#define AT91C_RTTC_RTAR (0xFFFFFD24) // (RTTC) Real-time Alarm Register -// ========== Register definition for PITC peripheral ========== -#define AT91C_PITC_PIVR (0xFFFFFD38) // (PITC) Period Interval Value Register -#define AT91C_PITC_PISR (0xFFFFFD34) // (PITC) Period Interval Status Register -#define AT91C_PITC_PIIR (0xFFFFFD3C) // (PITC) Period Interval Image Register -#define AT91C_PITC_PIMR (0xFFFFFD30) // (PITC) Period Interval Mode Register -// ========== Register definition for WDTC peripheral ========== -#define AT91C_WDTC_WDCR (0xFFFFFD40) // (WDTC) Watchdog Control Register -#define AT91C_WDTC_WDSR (0xFFFFFD48) // (WDTC) Watchdog Status Register -#define AT91C_WDTC_WDMR (0xFFFFFD44) // (WDTC) Watchdog Mode Register -// ========== Register definition for VREG peripheral ========== -#define AT91C_VREG_MR (0xFFFFFD60) // (VREG) Voltage Regulator Mode Register -// ========== Register definition for MC peripheral ========== -#define AT91C_MC_ASR (0xFFFFFF04) // (MC) MC Abort Status Register -#define AT91C_MC_RCR (0xFFFFFF00) // (MC) MC Remap Control Register -#define AT91C_MC_FCR (0xFFFFFF64) // (MC) MC Flash Command Register -#define AT91C_MC_AASR (0xFFFFFF08) // (MC) MC Abort Address Status Register -#define AT91C_MC_FSR (0xFFFFFF68) // (MC) MC Flash Status Register -#define AT91C_MC_FMR (0xFFFFFF60) // (MC) MC Flash Mode Register -// ========== Register definition for PDC_SPI1 peripheral ========== -#define AT91C_SPI1_PTCR (0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register -#define AT91C_SPI1_RPR (0xFFFE4100) // (PDC_SPI1) Receive Pointer Register -#define AT91C_SPI1_TNCR (0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register -#define AT91C_SPI1_TPR (0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register -#define AT91C_SPI1_TNPR (0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register -#define AT91C_SPI1_TCR (0xFFFE410C) // (PDC_SPI1) Transmit Counter Register -#define AT91C_SPI1_RCR (0xFFFE4104) // (PDC_SPI1) Receive Counter Register -#define AT91C_SPI1_RNPR (0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register -#define AT91C_SPI1_RNCR (0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register -#define AT91C_SPI1_PTSR (0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register -// ========== Register definition for SPI1 peripheral ========== -#define AT91C_SPI1_IMR (0xFFFE401C) // (SPI1) Interrupt Mask Register -#define AT91C_SPI1_IER (0xFFFE4014) // (SPI1) Interrupt Enable Register -#define AT91C_SPI1_MR (0xFFFE4004) // (SPI1) Mode Register -#define AT91C_SPI1_RDR (0xFFFE4008) // (SPI1) Receive Data Register -#define AT91C_SPI1_IDR (0xFFFE4018) // (SPI1) Interrupt Disable Register -#define AT91C_SPI1_SR (0xFFFE4010) // (SPI1) Status Register -#define AT91C_SPI1_TDR (0xFFFE400C) // (SPI1) Transmit Data Register -#define AT91C_SPI1_CR (0xFFFE4000) // (SPI1) Control Register -#define AT91C_SPI1_CSR (0xFFFE4030) // (SPI1) Chip Select Register -// ========== Register definition for PDC_SPI0 peripheral ========== -#define AT91C_SPI0_PTCR (0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register -#define AT91C_SPI0_TPR (0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register -#define AT91C_SPI0_TCR (0xFFFE010C) // (PDC_SPI0) Transmit Counter Register -#define AT91C_SPI0_RCR (0xFFFE0104) // (PDC_SPI0) Receive Counter Register -#define AT91C_SPI0_PTSR (0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register -#define AT91C_SPI0_RNPR (0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register -#define AT91C_SPI0_RPR (0xFFFE0100) // (PDC_SPI0) Receive Pointer Register -#define AT91C_SPI0_TNCR (0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register -#define AT91C_SPI0_RNCR (0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register -#define AT91C_SPI0_TNPR (0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register -// ========== Register definition for SPI0 peripheral ========== -#define AT91C_SPI0_IER (0xFFFE0014) // (SPI0) Interrupt Enable Register -#define AT91C_SPI0_SR (0xFFFE0010) // (SPI0) Status Register -#define AT91C_SPI0_IDR (0xFFFE0018) // (SPI0) Interrupt Disable Register -#define AT91C_SPI0_CR (0xFFFE0000) // (SPI0) Control Register -#define AT91C_SPI0_MR (0xFFFE0004) // (SPI0) Mode Register -#define AT91C_SPI0_IMR (0xFFFE001C) // (SPI0) Interrupt Mask Register -#define AT91C_SPI0_TDR (0xFFFE000C) // (SPI0) Transmit Data Register -#define AT91C_SPI0_RDR (0xFFFE0008) // (SPI0) Receive Data Register -#define AT91C_SPI0_CSR (0xFFFE0030) // (SPI0) Chip Select Register -// ========== Register definition for PDC_US1 peripheral ========== -#define AT91C_US1_RNCR (0xFFFC4114) // (PDC_US1) Receive Next Counter Register -#define AT91C_US1_PTCR (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register -#define AT91C_US1_TCR (0xFFFC410C) // (PDC_US1) Transmit Counter Register -#define AT91C_US1_PTSR (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register -#define AT91C_US1_TNPR (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register -#define AT91C_US1_RCR (0xFFFC4104) // (PDC_US1) Receive Counter Register -#define AT91C_US1_RNPR (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register -#define AT91C_US1_RPR (0xFFFC4100) // (PDC_US1) Receive Pointer Register -#define AT91C_US1_TNCR (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register -#define AT91C_US1_TPR (0xFFFC4108) // (PDC_US1) Transmit Pointer Register -// ========== Register definition for US1 peripheral ========== -#define AT91C_US1_IF (0xFFFC404C) // (US1) IRDA_FILTER Register -#define AT91C_US1_NER (0xFFFC4044) // (US1) Nb Errors Register -#define AT91C_US1_RTOR (0xFFFC4024) // (US1) Receiver Time-out Register -#define AT91C_US1_CSR (0xFFFC4014) // (US1) Channel Status Register -#define AT91C_US1_IDR (0xFFFC400C) // (US1) Interrupt Disable Register -#define AT91C_US1_IER (0xFFFC4008) // (US1) Interrupt Enable Register -#define AT91C_US1_THR (0xFFFC401C) // (US1) Transmitter Holding Register -#define AT91C_US1_TTGR (0xFFFC4028) // (US1) Transmitter Time-guard Register -#define AT91C_US1_RHR (0xFFFC4018) // (US1) Receiver Holding Register -#define AT91C_US1_BRGR (0xFFFC4020) // (US1) Baud Rate Generator Register -#define AT91C_US1_IMR (0xFFFC4010) // (US1) Interrupt Mask Register -#define AT91C_US1_FIDI (0xFFFC4040) // (US1) FI_DI_Ratio Register -#define AT91C_US1_CR (0xFFFC4000) // (US1) Control Register -#define AT91C_US1_MR (0xFFFC4004) // (US1) Mode Register -// ========== Register definition for PDC_US0 peripheral ========== -#define AT91C_US0_TNPR (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register -#define AT91C_US0_RNPR (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register -#define AT91C_US0_TCR (0xFFFC010C) // (PDC_US0) Transmit Counter Register -#define AT91C_US0_PTCR (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register -#define AT91C_US0_PTSR (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register -#define AT91C_US0_TNCR (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register -#define AT91C_US0_TPR (0xFFFC0108) // (PDC_US0) Transmit Pointer Register -#define AT91C_US0_RCR (0xFFFC0104) // (PDC_US0) Receive Counter Register -#define AT91C_US0_RPR (0xFFFC0100) // (PDC_US0) Receive Pointer Register -#define AT91C_US0_RNCR (0xFFFC0114) // (PDC_US0) Receive Next Counter Register -// ========== Register definition for US0 peripheral ========== -#define AT91C_US0_BRGR (0xFFFC0020) // (US0) Baud Rate Generator Register -#define AT91C_US0_NER (0xFFFC0044) // (US0) Nb Errors Register -#define AT91C_US0_CR (0xFFFC0000) // (US0) Control Register -#define AT91C_US0_IMR (0xFFFC0010) // (US0) Interrupt Mask Register -#define AT91C_US0_FIDI (0xFFFC0040) // (US0) FI_DI_Ratio Register -#define AT91C_US0_TTGR (0xFFFC0028) // (US0) Transmitter Time-guard Register -#define AT91C_US0_MR (0xFFFC0004) // (US0) Mode Register -#define AT91C_US0_RTOR (0xFFFC0024) // (US0) Receiver Time-out Register -#define AT91C_US0_CSR (0xFFFC0014) // (US0) Channel Status Register -#define AT91C_US0_RHR (0xFFFC0018) // (US0) Receiver Holding Register -#define AT91C_US0_IDR (0xFFFC000C) // (US0) Interrupt Disable Register -#define AT91C_US0_THR (0xFFFC001C) // (US0) Transmitter Holding Register -#define AT91C_US0_IF (0xFFFC004C) // (US0) IRDA_FILTER Register -#define AT91C_US0_IER (0xFFFC0008) // (US0) Interrupt Enable Register -// ========== Register definition for PDC_SSC peripheral ========== -#define AT91C_SSC_TNCR (0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register -#define AT91C_SSC_RPR (0xFFFD4100) // (PDC_SSC) Receive Pointer Register -#define AT91C_SSC_RNCR (0xFFFD4114) // (PDC_SSC) Receive Next Counter Register -#define AT91C_SSC_TPR (0xFFFD4108) // (PDC_SSC) Transmit Pointer Register -#define AT91C_SSC_PTCR (0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register -#define AT91C_SSC_TCR (0xFFFD410C) // (PDC_SSC) Transmit Counter Register -#define AT91C_SSC_RCR (0xFFFD4104) // (PDC_SSC) Receive Counter Register -#define AT91C_SSC_RNPR (0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register -#define AT91C_SSC_TNPR (0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register -#define AT91C_SSC_PTSR (0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register -// ========== Register definition for SSC peripheral ========== -#define AT91C_SSC_RHR (0xFFFD4020) // (SSC) Receive Holding Register -#define AT91C_SSC_RSHR (0xFFFD4030) // (SSC) Receive Sync Holding Register -#define AT91C_SSC_TFMR (0xFFFD401C) // (SSC) Transmit Frame Mode Register -#define AT91C_SSC_IDR (0xFFFD4048) // (SSC) Interrupt Disable Register -#define AT91C_SSC_THR (0xFFFD4024) // (SSC) Transmit Holding Register -#define AT91C_SSC_RCMR (0xFFFD4010) // (SSC) Receive Clock ModeRegister -#define AT91C_SSC_IER (0xFFFD4044) // (SSC) Interrupt Enable Register -#define AT91C_SSC_TSHR (0xFFFD4034) // (SSC) Transmit Sync Holding Register -#define AT91C_SSC_SR (0xFFFD4040) // (SSC) Status Register -#define AT91C_SSC_CMR (0xFFFD4004) // (SSC) Clock Mode Register -#define AT91C_SSC_TCMR (0xFFFD4018) // (SSC) Transmit Clock Mode Register -#define AT91C_SSC_CR (0xFFFD4000) // (SSC) Control Register -#define AT91C_SSC_IMR (0xFFFD404C) // (SSC) Interrupt Mask Register -#define AT91C_SSC_RFMR (0xFFFD4014) // (SSC) Receive Frame Mode Register -// ========== Register definition for TWI peripheral ========== -#define AT91C_TWI_IER (0xFFFB8024) // (TWI) Interrupt Enable Register -#define AT91C_TWI_CR (0xFFFB8000) // (TWI) Control Register -#define AT91C_TWI_SR (0xFFFB8020) // (TWI) Status Register -#define AT91C_TWI_IMR (0xFFFB802C) // (TWI) Interrupt Mask Register -#define AT91C_TWI_THR (0xFFFB8034) // (TWI) Transmit Holding Register -#define AT91C_TWI_IDR (0xFFFB8028) // (TWI) Interrupt Disable Register -#define AT91C_TWI_IADR (0xFFFB800C) // (TWI) Internal Address Register -#define AT91C_TWI_MMR (0xFFFB8004) // (TWI) Master Mode Register -#define AT91C_TWI_CWGR (0xFFFB8010) // (TWI) Clock Waveform Generator Register -#define AT91C_TWI_RHR (0xFFFB8030) // (TWI) Receive Holding Register -// ========== Register definition for PWMC_CH3 peripheral ========== -#define AT91C_PWMC_CH3_CUPDR (0xFFFCC270) // (PWMC_CH3) Channel Update Register -#define AT91C_PWMC_CH3_Reserved (0xFFFCC274) // (PWMC_CH3) Reserved -#define AT91C_PWMC_CH3_CPRDR (0xFFFCC268) // (PWMC_CH3) Channel Period Register -#define AT91C_PWMC_CH3_CDTYR (0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register -#define AT91C_PWMC_CH3_CCNTR (0xFFFCC26C) // (PWMC_CH3) Channel Counter Register -#define AT91C_PWMC_CH3_CMR (0xFFFCC260) // (PWMC_CH3) Channel Mode Register -// ========== Register definition for PWMC_CH2 peripheral ========== -#define AT91C_PWMC_CH2_Reserved (0xFFFCC254) // (PWMC_CH2) Reserved -#define AT91C_PWMC_CH2_CMR (0xFFFCC240) // (PWMC_CH2) Channel Mode Register -#define AT91C_PWMC_CH2_CCNTR (0xFFFCC24C) // (PWMC_CH2) Channel Counter Register -#define AT91C_PWMC_CH2_CPRDR (0xFFFCC248) // (PWMC_CH2) Channel Period Register -#define AT91C_PWMC_CH2_CUPDR (0xFFFCC250) // (PWMC_CH2) Channel Update Register -#define AT91C_PWMC_CH2_CDTYR (0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH1 peripheral ========== -#define AT91C_PWMC_CH1_Reserved (0xFFFCC234) // (PWMC_CH1) Reserved -#define AT91C_PWMC_CH1_CUPDR (0xFFFCC230) // (PWMC_CH1) Channel Update Register -#define AT91C_PWMC_CH1_CPRDR (0xFFFCC228) // (PWMC_CH1) Channel Period Register -#define AT91C_PWMC_CH1_CCNTR (0xFFFCC22C) // (PWMC_CH1) Channel Counter Register -#define AT91C_PWMC_CH1_CDTYR (0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register -#define AT91C_PWMC_CH1_CMR (0xFFFCC220) // (PWMC_CH1) Channel Mode Register -// ========== Register definition for PWMC_CH0 peripheral ========== -#define AT91C_PWMC_CH0_Reserved (0xFFFCC214) // (PWMC_CH0) Reserved -#define AT91C_PWMC_CH0_CPRDR (0xFFFCC208) // (PWMC_CH0) Channel Period Register -#define AT91C_PWMC_CH0_CDTYR (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register -#define AT91C_PWMC_CH0_CMR (0xFFFCC200) // (PWMC_CH0) Channel Mode Register -#define AT91C_PWMC_CH0_CUPDR (0xFFFCC210) // (PWMC_CH0) Channel Update Register -#define AT91C_PWMC_CH0_CCNTR (0xFFFCC20C) // (PWMC_CH0) Channel Counter Register -// ========== Register definition for PWMC peripheral ========== -#define AT91C_PWMC_IDR (0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register -#define AT91C_PWMC_DIS (0xFFFCC008) // (PWMC) PWMC Disable Register -#define AT91C_PWMC_IER (0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register -#define AT91C_PWMC_VR (0xFFFCC0FC) // (PWMC) PWMC Version Register -#define AT91C_PWMC_ISR (0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register -#define AT91C_PWMC_SR (0xFFFCC00C) // (PWMC) PWMC Status Register -#define AT91C_PWMC_IMR (0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register -#define AT91C_PWMC_MR (0xFFFCC000) // (PWMC) PWMC Mode Register -#define AT91C_PWMC_ENA (0xFFFCC004) // (PWMC) PWMC Enable Register -// ========== Register definition for UDP peripheral ========== -#define AT91C_UDP_IMR (0xFFFB0018) // (UDP) Interrupt Mask Register -#define AT91C_UDP_FADDR (0xFFFB0008) // (UDP) Function Address Register -#define AT91C_UDP_NUM (0xFFFB0000) // (UDP) Frame Number Register -#define AT91C_UDP_FDR (0xFFFB0050) // (UDP) Endpoint FIFO Data Register -#define AT91C_UDP_ISR (0xFFFB001C) // (UDP) Interrupt Status Register -#define AT91C_UDP_CSR (0xFFFB0030) // (UDP) Endpoint Control and Status Register -#define AT91C_UDP_IDR (0xFFFB0014) // (UDP) Interrupt Disable Register -#define AT91C_UDP_ICR (0xFFFB0020) // (UDP) Interrupt Clear Register -#define AT91C_UDP_RSTEP (0xFFFB0028) // (UDP) Reset Endpoint Register -#define AT91C_UDP_TXVC (0xFFFB0074) // (UDP) Transceiver Control Register -#define AT91C_UDP_GLBSTATE (0xFFFB0004) // (UDP) Global State Register -#define AT91C_UDP_IER (0xFFFB0010) // (UDP) Interrupt Enable Register -// ========== Register definition for TC0 peripheral ========== -#define AT91C_TC0_SR (0xFFFA0020) // (TC0) Status Register -#define AT91C_TC0_RC (0xFFFA001C) // (TC0) Register C -#define AT91C_TC0_RB (0xFFFA0018) // (TC0) Register B -#define AT91C_TC0_CCR (0xFFFA0000) // (TC0) Channel Control Register -#define AT91C_TC0_CMR (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC0_IER (0xFFFA0024) // (TC0) Interrupt Enable Register -#define AT91C_TC0_RA (0xFFFA0014) // (TC0) Register A -#define AT91C_TC0_IDR (0xFFFA0028) // (TC0) Interrupt Disable Register -#define AT91C_TC0_CV (0xFFFA0010) // (TC0) Counter Value -#define AT91C_TC0_IMR (0xFFFA002C) // (TC0) Interrupt Mask Register -// ========== Register definition for TC1 peripheral ========== -#define AT91C_TC1_RB (0xFFFA0058) // (TC1) Register B -#define AT91C_TC1_CCR (0xFFFA0040) // (TC1) Channel Control Register -#define AT91C_TC1_IER (0xFFFA0064) // (TC1) Interrupt Enable Register -#define AT91C_TC1_IDR (0xFFFA0068) // (TC1) Interrupt Disable Register -#define AT91C_TC1_SR (0xFFFA0060) // (TC1) Status Register -#define AT91C_TC1_CMR (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC1_RA (0xFFFA0054) // (TC1) Register A -#define AT91C_TC1_RC (0xFFFA005C) // (TC1) Register C -#define AT91C_TC1_IMR (0xFFFA006C) // (TC1) Interrupt Mask Register -#define AT91C_TC1_CV (0xFFFA0050) // (TC1) Counter Value -// ========== Register definition for TC2 peripheral ========== -#define AT91C_TC2_CMR (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC2_CCR (0xFFFA0080) // (TC2) Channel Control Register -#define AT91C_TC2_CV (0xFFFA0090) // (TC2) Counter Value -#define AT91C_TC2_RA (0xFFFA0094) // (TC2) Register A -#define AT91C_TC2_RB (0xFFFA0098) // (TC2) Register B -#define AT91C_TC2_IDR (0xFFFA00A8) // (TC2) Interrupt Disable Register -#define AT91C_TC2_IMR (0xFFFA00AC) // (TC2) Interrupt Mask Register -#define AT91C_TC2_RC (0xFFFA009C) // (TC2) Register C -#define AT91C_TC2_IER (0xFFFA00A4) // (TC2) Interrupt Enable Register -#define AT91C_TC2_SR (0xFFFA00A0) // (TC2) Status Register -// ========== Register definition for TCB peripheral ========== -#define AT91C_TCB_BMR (0xFFFA00C4) // (TCB) TC Block Mode Register -#define AT91C_TCB_BCR (0xFFFA00C0) // (TCB) TC Block Control Register -// ========== Register definition for CAN_MB0 peripheral ========== -#define AT91C_CAN_MB0_MDL (0xFFFD0214) // (CAN_MB0) MailBox Data Low Register -#define AT91C_CAN_MB0_MAM (0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register -#define AT91C_CAN_MB0_MCR (0xFFFD021C) // (CAN_MB0) MailBox Control Register -#define AT91C_CAN_MB0_MID (0xFFFD0208) // (CAN_MB0) MailBox ID Register -#define AT91C_CAN_MB0_MSR (0xFFFD0210) // (CAN_MB0) MailBox Status Register -#define AT91C_CAN_MB0_MFID (0xFFFD020C) // (CAN_MB0) MailBox Family ID Register -#define AT91C_CAN_MB0_MDH (0xFFFD0218) // (CAN_MB0) MailBox Data High Register -#define AT91C_CAN_MB0_MMR (0xFFFD0200) // (CAN_MB0) MailBox Mode Register -// ========== Register definition for CAN_MB1 peripheral ========== -#define AT91C_CAN_MB1_MDL (0xFFFD0234) // (CAN_MB1) MailBox Data Low Register -#define AT91C_CAN_MB1_MID (0xFFFD0228) // (CAN_MB1) MailBox ID Register -#define AT91C_CAN_MB1_MMR (0xFFFD0220) // (CAN_MB1) MailBox Mode Register -#define AT91C_CAN_MB1_MSR (0xFFFD0230) // (CAN_MB1) MailBox Status Register -#define AT91C_CAN_MB1_MAM (0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register -#define AT91C_CAN_MB1_MDH (0xFFFD0238) // (CAN_MB1) MailBox Data High Register -#define AT91C_CAN_MB1_MCR (0xFFFD023C) // (CAN_MB1) MailBox Control Register -#define AT91C_CAN_MB1_MFID (0xFFFD022C) // (CAN_MB1) MailBox Family ID Register -// ========== Register definition for CAN_MB2 peripheral ========== -#define AT91C_CAN_MB2_MCR (0xFFFD025C) // (CAN_MB2) MailBox Control Register -#define AT91C_CAN_MB2_MDH (0xFFFD0258) // (CAN_MB2) MailBox Data High Register -#define AT91C_CAN_MB2_MID (0xFFFD0248) // (CAN_MB2) MailBox ID Register -#define AT91C_CAN_MB2_MDL (0xFFFD0254) // (CAN_MB2) MailBox Data Low Register -#define AT91C_CAN_MB2_MMR (0xFFFD0240) // (CAN_MB2) MailBox Mode Register -#define AT91C_CAN_MB2_MAM (0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register -#define AT91C_CAN_MB2_MFID (0xFFFD024C) // (CAN_MB2) MailBox Family ID Register -#define AT91C_CAN_MB2_MSR (0xFFFD0250) // (CAN_MB2) MailBox Status Register -// ========== Register definition for CAN_MB3 peripheral ========== -#define AT91C_CAN_MB3_MFID (0xFFFD026C) // (CAN_MB3) MailBox Family ID Register -#define AT91C_CAN_MB3_MAM (0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register -#define AT91C_CAN_MB3_MID (0xFFFD0268) // (CAN_MB3) MailBox ID Register -#define AT91C_CAN_MB3_MCR (0xFFFD027C) // (CAN_MB3) MailBox Control Register -#define AT91C_CAN_MB3_MMR (0xFFFD0260) // (CAN_MB3) MailBox Mode Register -#define AT91C_CAN_MB3_MSR (0xFFFD0270) // (CAN_MB3) MailBox Status Register -#define AT91C_CAN_MB3_MDL (0xFFFD0274) // (CAN_MB3) MailBox Data Low Register -#define AT91C_CAN_MB3_MDH (0xFFFD0278) // (CAN_MB3) MailBox Data High Register -// ========== Register definition for CAN_MB4 peripheral ========== -#define AT91C_CAN_MB4_MID (0xFFFD0288) // (CAN_MB4) MailBox ID Register -#define AT91C_CAN_MB4_MMR (0xFFFD0280) // (CAN_MB4) MailBox Mode Register -#define AT91C_CAN_MB4_MDH (0xFFFD0298) // (CAN_MB4) MailBox Data High Register -#define AT91C_CAN_MB4_MFID (0xFFFD028C) // (CAN_MB4) MailBox Family ID Register -#define AT91C_CAN_MB4_MSR (0xFFFD0290) // (CAN_MB4) MailBox Status Register -#define AT91C_CAN_MB4_MCR (0xFFFD029C) // (CAN_MB4) MailBox Control Register -#define AT91C_CAN_MB4_MDL (0xFFFD0294) // (CAN_MB4) MailBox Data Low Register -#define AT91C_CAN_MB4_MAM (0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register -// ========== Register definition for CAN_MB5 peripheral ========== -#define AT91C_CAN_MB5_MSR (0xFFFD02B0) // (CAN_MB5) MailBox Status Register -#define AT91C_CAN_MB5_MCR (0xFFFD02BC) // (CAN_MB5) MailBox Control Register -#define AT91C_CAN_MB5_MFID (0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register -#define AT91C_CAN_MB5_MDH (0xFFFD02B8) // (CAN_MB5) MailBox Data High Register -#define AT91C_CAN_MB5_MID (0xFFFD02A8) // (CAN_MB5) MailBox ID Register -#define AT91C_CAN_MB5_MMR (0xFFFD02A0) // (CAN_MB5) MailBox Mode Register -#define AT91C_CAN_MB5_MDL (0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register -#define AT91C_CAN_MB5_MAM (0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register -// ========== Register definition for CAN_MB6 peripheral ========== -#define AT91C_CAN_MB6_MFID (0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register -#define AT91C_CAN_MB6_MID (0xFFFD02C8) // (CAN_MB6) MailBox ID Register -#define AT91C_CAN_MB6_MAM (0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register -#define AT91C_CAN_MB6_MSR (0xFFFD02D0) // (CAN_MB6) MailBox Status Register -#define AT91C_CAN_MB6_MDL (0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register -#define AT91C_CAN_MB6_MCR (0xFFFD02DC) // (CAN_MB6) MailBox Control Register -#define AT91C_CAN_MB6_MDH (0xFFFD02D8) // (CAN_MB6) MailBox Data High Register -#define AT91C_CAN_MB6_MMR (0xFFFD02C0) // (CAN_MB6) MailBox Mode Register -// ========== Register definition for CAN_MB7 peripheral ========== -#define AT91C_CAN_MB7_MCR (0xFFFD02FC) // (CAN_MB7) MailBox Control Register -#define AT91C_CAN_MB7_MDH (0xFFFD02F8) // (CAN_MB7) MailBox Data High Register -#define AT91C_CAN_MB7_MFID (0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register -#define AT91C_CAN_MB7_MDL (0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register -#define AT91C_CAN_MB7_MID (0xFFFD02E8) // (CAN_MB7) MailBox ID Register -#define AT91C_CAN_MB7_MMR (0xFFFD02E0) // (CAN_MB7) MailBox Mode Register -#define AT91C_CAN_MB7_MAM (0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register -#define AT91C_CAN_MB7_MSR (0xFFFD02F0) // (CAN_MB7) MailBox Status Register -// ========== Register definition for CAN peripheral ========== -#define AT91C_CAN_TCR (0xFFFD0024) // (CAN) Transfer Command Register -#define AT91C_CAN_IMR (0xFFFD000C) // (CAN) Interrupt Mask Register -#define AT91C_CAN_IER (0xFFFD0004) // (CAN) Interrupt Enable Register -#define AT91C_CAN_ECR (0xFFFD0020) // (CAN) Error Counter Register -#define AT91C_CAN_TIMESTP (0xFFFD001C) // (CAN) Time Stamp Register -#define AT91C_CAN_MR (0xFFFD0000) // (CAN) Mode Register -#define AT91C_CAN_IDR (0xFFFD0008) // (CAN) Interrupt Disable Register -#define AT91C_CAN_ACR (0xFFFD0028) // (CAN) Abort Command Register -#define AT91C_CAN_TIM (0xFFFD0018) // (CAN) Timer Register -#define AT91C_CAN_SR (0xFFFD0010) // (CAN) Status Register -#define AT91C_CAN_BR (0xFFFD0014) // (CAN) Baudrate Register -#define AT91C_CAN_VR (0xFFFD00FC) // (CAN) Version Register -// ========== Register definition for EMAC peripheral ========== -#define AT91C_EMAC_ISR (0xFFFDC024) // (EMAC) Interrupt Status Register -#define AT91C_EMAC_SA4H (0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes -#define AT91C_EMAC_SA1L (0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes -#define AT91C_EMAC_ELE (0xFFFDC078) // (EMAC) Excessive Length Errors Register -#define AT91C_EMAC_LCOL (0xFFFDC05C) // (EMAC) Late Collision Register -#define AT91C_EMAC_RLE (0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register -#define AT91C_EMAC_WOL (0xFFFDC0C4) // (EMAC) Wake On LAN Register -#define AT91C_EMAC_DTF (0xFFFDC058) // (EMAC) Deferred Transmission Frame Register -#define AT91C_EMAC_TUND (0xFFFDC064) // (EMAC) Transmit Underrun Error Register -#define AT91C_EMAC_NCR (0xFFFDC000) // (EMAC) Network Control Register -#define AT91C_EMAC_SA4L (0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes -#define AT91C_EMAC_RSR (0xFFFDC020) // (EMAC) Receive Status Register -#define AT91C_EMAC_SA3L (0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes -#define AT91C_EMAC_TSR (0xFFFDC014) // (EMAC) Transmit Status Register -#define AT91C_EMAC_IDR (0xFFFDC02C) // (EMAC) Interrupt Disable Register -#define AT91C_EMAC_RSE (0xFFFDC074) // (EMAC) Receive Symbol Errors Register -#define AT91C_EMAC_ECOL (0xFFFDC060) // (EMAC) Excessive Collision Register -#define AT91C_EMAC_TID (0xFFFDC0B8) // (EMAC) Type ID Checking Register -#define AT91C_EMAC_HRB (0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] -#define AT91C_EMAC_TBQP (0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer -#define AT91C_EMAC_USRIO (0xFFFDC0C0) // (EMAC) USER Input/Output Register -#define AT91C_EMAC_PTR (0xFFFDC038) // (EMAC) Pause Time Register -#define AT91C_EMAC_SA2H (0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes -#define AT91C_EMAC_ROV (0xFFFDC070) // (EMAC) Receive Overrun Errors Register -#define AT91C_EMAC_ALE (0xFFFDC054) // (EMAC) Alignment Error Register -#define AT91C_EMAC_RJA (0xFFFDC07C) // (EMAC) Receive Jabbers Register -#define AT91C_EMAC_RBQP (0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer -#define AT91C_EMAC_TPF (0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register -#define AT91C_EMAC_NCFGR (0xFFFDC004) // (EMAC) Network Configuration Register -#define AT91C_EMAC_HRT (0xFFFDC094) // (EMAC) Hash Address Top[63:32] -#define AT91C_EMAC_USF (0xFFFDC080) // (EMAC) Undersize Frames Register -#define AT91C_EMAC_FCSE (0xFFFDC050) // (EMAC) Frame Check Sequence Error Register -#define AT91C_EMAC_TPQ (0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register -#define AT91C_EMAC_MAN (0xFFFDC034) // (EMAC) PHY Maintenance Register -#define AT91C_EMAC_FTO (0xFFFDC040) // (EMAC) Frames Transmitted OK Register -#define AT91C_EMAC_REV (0xFFFDC0FC) // (EMAC) Revision Register -#define AT91C_EMAC_IMR (0xFFFDC030) // (EMAC) Interrupt Mask Register -#define AT91C_EMAC_SCF (0xFFFDC044) // (EMAC) Single Collision Frame Register -#define AT91C_EMAC_PFR (0xFFFDC03C) // (EMAC) Pause Frames received Register -#define AT91C_EMAC_MCF (0xFFFDC048) // (EMAC) Multiple Collision Frame Register -#define AT91C_EMAC_NSR (0xFFFDC008) // (EMAC) Network Status Register -#define AT91C_EMAC_SA2L (0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes -#define AT91C_EMAC_FRO (0xFFFDC04C) // (EMAC) Frames Received OK Register -#define AT91C_EMAC_IER (0xFFFDC028) // (EMAC) Interrupt Enable Register -#define AT91C_EMAC_SA1H (0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes -#define AT91C_EMAC_CSE (0xFFFDC068) // (EMAC) Carrier Sense Error Register -#define AT91C_EMAC_SA3H (0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes -#define AT91C_EMAC_RRE (0xFFFDC06C) // (EMAC) Receive Ressource Error Register -#define AT91C_EMAC_STE (0xFFFDC084) // (EMAC) SQE Test Error Register -// ========== Register definition for PDC_ADC peripheral ========== -#define AT91C_ADC_PTSR (0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register -#define AT91C_ADC_PTCR (0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register -#define AT91C_ADC_TNPR (0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register -#define AT91C_ADC_TNCR (0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register -#define AT91C_ADC_RNPR (0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register -#define AT91C_ADC_RNCR (0xFFFD8114) // (PDC_ADC) Receive Next Counter Register -#define AT91C_ADC_RPR (0xFFFD8100) // (PDC_ADC) Receive Pointer Register -#define AT91C_ADC_TCR (0xFFFD810C) // (PDC_ADC) Transmit Counter Register -#define AT91C_ADC_TPR (0xFFFD8108) // (PDC_ADC) Transmit Pointer Register -#define AT91C_ADC_RCR (0xFFFD8104) // (PDC_ADC) Receive Counter Register -// ========== Register definition for ADC peripheral ========== -#define AT91C_ADC_CDR2 (0xFFFD8038) // (ADC) ADC Channel Data Register 2 -#define AT91C_ADC_CDR3 (0xFFFD803C) // (ADC) ADC Channel Data Register 3 -#define AT91C_ADC_CDR0 (0xFFFD8030) // (ADC) ADC Channel Data Register 0 -#define AT91C_ADC_CDR5 (0xFFFD8044) // (ADC) ADC Channel Data Register 5 -#define AT91C_ADC_CHDR (0xFFFD8014) // (ADC) ADC Channel Disable Register -#define AT91C_ADC_SR (0xFFFD801C) // (ADC) ADC Status Register -#define AT91C_ADC_CDR4 (0xFFFD8040) // (ADC) ADC Channel Data Register 4 -#define AT91C_ADC_CDR1 (0xFFFD8034) // (ADC) ADC Channel Data Register 1 -#define AT91C_ADC_LCDR (0xFFFD8020) // (ADC) ADC Last Converted Data Register -#define AT91C_ADC_IDR (0xFFFD8028) // (ADC) ADC Interrupt Disable Register -#define AT91C_ADC_CR (0xFFFD8000) // (ADC) ADC Control Register -#define AT91C_ADC_CDR7 (0xFFFD804C) // (ADC) ADC Channel Data Register 7 -#define AT91C_ADC_CDR6 (0xFFFD8048) // (ADC) ADC Channel Data Register 6 -#define AT91C_ADC_IER (0xFFFD8024) // (ADC) ADC Interrupt Enable Register -#define AT91C_ADC_CHER (0xFFFD8010) // (ADC) ADC Channel Enable Register -#define AT91C_ADC_CHSR (0xFFFD8018) // (ADC) ADC Channel Status Register -#define AT91C_ADC_MR (0xFFFD8004) // (ADC) ADC Mode Register -#define AT91C_ADC_IMR (0xFFFD802C) // (ADC) ADC Interrupt Mask Register -// ========== Register definition for PDC_AES peripheral ========== -#define AT91C_AES_TPR (0xFFFA4108) // (PDC_AES) Transmit Pointer Register -#define AT91C_AES_PTCR (0xFFFA4120) // (PDC_AES) PDC Transfer Control Register -#define AT91C_AES_RNPR (0xFFFA4110) // (PDC_AES) Receive Next Pointer Register -#define AT91C_AES_TNCR (0xFFFA411C) // (PDC_AES) Transmit Next Counter Register -#define AT91C_AES_TCR (0xFFFA410C) // (PDC_AES) Transmit Counter Register -#define AT91C_AES_RCR (0xFFFA4104) // (PDC_AES) Receive Counter Register -#define AT91C_AES_RNCR (0xFFFA4114) // (PDC_AES) Receive Next Counter Register -#define AT91C_AES_TNPR (0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register -#define AT91C_AES_RPR (0xFFFA4100) // (PDC_AES) Receive Pointer Register -#define AT91C_AES_PTSR (0xFFFA4124) // (PDC_AES) PDC Transfer Status Register -// ========== Register definition for AES peripheral ========== -#define AT91C_AES_IVxR (0xFFFA4060) // (AES) Initialization Vector x Register -#define AT91C_AES_MR (0xFFFA4004) // (AES) Mode Register -#define AT91C_AES_VR (0xFFFA40FC) // (AES) AES Version Register -#define AT91C_AES_ODATAxR (0xFFFA4050) // (AES) Output Data x Register -#define AT91C_AES_IDATAxR (0xFFFA4040) // (AES) Input Data x Register -#define AT91C_AES_CR (0xFFFA4000) // (AES) Control Register -#define AT91C_AES_IDR (0xFFFA4014) // (AES) Interrupt Disable Register -#define AT91C_AES_IMR (0xFFFA4018) // (AES) Interrupt Mask Register -#define AT91C_AES_IER (0xFFFA4010) // (AES) Interrupt Enable Register -#define AT91C_AES_KEYWxR (0xFFFA4020) // (AES) Key Word x Register -#define AT91C_AES_ISR (0xFFFA401C) // (AES) Interrupt Status Register -// ========== Register definition for PDC_TDES peripheral ========== -#define AT91C_TDES_RNCR (0xFFFA8114) // (PDC_TDES) Receive Next Counter Register -#define AT91C_TDES_TCR (0xFFFA810C) // (PDC_TDES) Transmit Counter Register -#define AT91C_TDES_RCR (0xFFFA8104) // (PDC_TDES) Receive Counter Register -#define AT91C_TDES_TNPR (0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register -#define AT91C_TDES_RNPR (0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register -#define AT91C_TDES_RPR (0xFFFA8100) // (PDC_TDES) Receive Pointer Register -#define AT91C_TDES_TNCR (0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register -#define AT91C_TDES_TPR (0xFFFA8108) // (PDC_TDES) Transmit Pointer Register -#define AT91C_TDES_PTSR (0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register -#define AT91C_TDES_PTCR (0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register -// ========== Register definition for TDES peripheral ========== -#define AT91C_TDES_KEY2WxR (0xFFFA8028) // (TDES) Key 2 Word x Register -#define AT91C_TDES_KEY3WxR (0xFFFA8030) // (TDES) Key 3 Word x Register -#define AT91C_TDES_IDR (0xFFFA8014) // (TDES) Interrupt Disable Register -#define AT91C_TDES_VR (0xFFFA80FC) // (TDES) TDES Version Register -#define AT91C_TDES_IVxR (0xFFFA8060) // (TDES) Initialization Vector x Register -#define AT91C_TDES_ODATAxR (0xFFFA8050) // (TDES) Output Data x Register -#define AT91C_TDES_IMR (0xFFFA8018) // (TDES) Interrupt Mask Register -#define AT91C_TDES_MR (0xFFFA8004) // (TDES) Mode Register -#define AT91C_TDES_CR (0xFFFA8000) // (TDES) Control Register -#define AT91C_TDES_IER (0xFFFA8010) // (TDES) Interrupt Enable Register -#define AT91C_TDES_ISR (0xFFFA801C) // (TDES) Interrupt Status Register -#define AT91C_TDES_IDATAxR (0xFFFA8040) // (TDES) Input Data x Register -#define AT91C_TDES_KEY1WxR (0xFFFA8020) // (TDES) Key 1 Word x Register - -// ***************************************************************************** -// PIO DEFINITIONS FOR AT91SAM7X128 -// ***************************************************************************** -#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 -#define AT91C_PA0_RXD0 (AT91C_PIO_PA0) // USART 0 Receive Data -#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 -#define AT91C_PA1_TXD0 (AT91C_PIO_PA1) // USART 0 Transmit Data -#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 -#define AT91C_PA10_TWD (AT91C_PIO_PA10) // TWI Two-wire Serial Data -#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 -#define AT91C_PA11_TWCK (AT91C_PIO_PA11) // TWI Two-wire Serial Clock -#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 -#define AT91C_PA12_NPCS00 (AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 -#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 -#define AT91C_PA13_NPCS01 (AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PA13_PCK1 (AT91C_PIO_PA13) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 -#define AT91C_PA14_NPCS02 (AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PA14_IRQ1 (AT91C_PIO_PA14) // External Interrupt 1 -#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 -#define AT91C_PA15_NPCS03 (AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PA15_TCLK2 (AT91C_PIO_PA15) // Timer Counter 2 external clock input -#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 -#define AT91C_PA16_MISO0 (AT91C_PIO_PA16) // SPI 0 Master In Slave -#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 -#define AT91C_PA17_MOSI0 (AT91C_PIO_PA17) // SPI 0 Master Out Slave -#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 -#define AT91C_PA18_SPCK0 (AT91C_PIO_PA18) // SPI 0 Serial Clock -#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 -#define AT91C_PA19_CANRX (AT91C_PIO_PA19) // CAN Receive -#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 -#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock -#define AT91C_PA2_NPCS11 (AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 -#define AT91C_PA20_CANTX (AT91C_PIO_PA20) // CAN Transmit -#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 -#define AT91C_PA21_TF (AT91C_PIO_PA21) // SSC Transmit Frame Sync -#define AT91C_PA21_NPCS10 (AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 -#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 -#define AT91C_PA22_TK (AT91C_PIO_PA22) // SSC Transmit Clock -#define AT91C_PA22_SPCK1 (AT91C_PIO_PA22) // SPI 1 Serial Clock -#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 -#define AT91C_PA23_TD (AT91C_PIO_PA23) // SSC Transmit data -#define AT91C_PA23_MOSI1 (AT91C_PIO_PA23) // SPI 1 Master Out Slave -#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 -#define AT91C_PA24_RD (AT91C_PIO_PA24) // SSC Receive Data -#define AT91C_PA24_MISO1 (AT91C_PIO_PA24) // SPI 1 Master In Slave -#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 -#define AT91C_PA25_RK (AT91C_PIO_PA25) // SSC Receive Clock -#define AT91C_PA25_NPCS11 (AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 -#define AT91C_PA26_RF (AT91C_PIO_PA26) // SSC Receive Frame Sync -#define AT91C_PA26_NPCS12 (AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 -#define AT91C_PA27_DRXD (AT91C_PIO_PA27) // DBGU Debug Receive Data -#define AT91C_PA27_PCK3 (AT91C_PIO_PA27) // PMC Programmable Clock Output 3 -#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 -#define AT91C_PA28_DTXD (AT91C_PIO_PA28) // DBGU Debug Transmit Data -#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 -#define AT91C_PA29_FIQ (AT91C_PIO_PA29) // AIC Fast Interrupt Input -#define AT91C_PA29_NPCS13 (AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 -#define AT91C_PA3_RTS0 (AT91C_PIO_PA3) // USART 0 Ready To Send -#define AT91C_PA3_NPCS12 (AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 -#define AT91C_PA30_IRQ0 (AT91C_PIO_PA30) // External Interrupt 0 -#define AT91C_PA30_PCK2 (AT91C_PIO_PA30) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 -#define AT91C_PA4_CTS0 (AT91C_PIO_PA4) // USART 0 Clear To Send -#define AT91C_PA4_NPCS13 (AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 -#define AT91C_PA5_RXD1 (AT91C_PIO_PA5) // USART 1 Receive Data -#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 -#define AT91C_PA6_TXD1 (AT91C_PIO_PA6) // USART 1 Transmit Data -#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 -#define AT91C_PA7_SCK1 (AT91C_PIO_PA7) // USART 1 Serial Clock -#define AT91C_PA7_NPCS01 (AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 -#define AT91C_PA8_RTS1 (AT91C_PIO_PA8) // USART 1 Ready To Send -#define AT91C_PA8_NPCS02 (AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 -#define AT91C_PA9_CTS1 (AT91C_PIO_PA9) // USART 1 Clear To Send -#define AT91C_PA9_NPCS03 (AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0 -#define AT91C_PB0_ETXCK_EREFCK (AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock -#define AT91C_PB0_PCK0 (AT91C_PIO_PB0) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1 -#define AT91C_PB1_ETXEN (AT91C_PIO_PB1) // Ethernet MAC Transmit Enable -#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10 -#define AT91C_PB10_ETX2 (AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 -#define AT91C_PB10_NPCS11 (AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11 -#define AT91C_PB11_ETX3 (AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 -#define AT91C_PB11_NPCS12 (AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12 -#define AT91C_PB12_ETXER (AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error -#define AT91C_PB12_TCLK0 (AT91C_PIO_PB12) // Timer Counter 0 external clock input -#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13 -#define AT91C_PB13_ERX2 (AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 -#define AT91C_PB13_NPCS01 (AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14 -#define AT91C_PB14_ERX3 (AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 -#define AT91C_PB14_NPCS02 (AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15 -#define AT91C_PB15_ERXDV (AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid -#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16 -#define AT91C_PB16_ECOL (AT91C_PIO_PB16) // Ethernet MAC Collision Detected -#define AT91C_PB16_NPCS13 (AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17 -#define AT91C_PB17_ERXCK (AT91C_PIO_PB17) // Ethernet MAC Receive Clock -#define AT91C_PB17_NPCS03 (AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18 -#define AT91C_PB18_EF100 (AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec -#define AT91C_PB18_ADTRG (AT91C_PIO_PB18) // ADC External Trigger -#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19 -#define AT91C_PB19_PWM0 (AT91C_PIO_PB19) // PWM Channel 0 -#define AT91C_PB19_TCLK1 (AT91C_PIO_PB19) // Timer Counter 1 external clock input -#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2 -#define AT91C_PB2_ETX0 (AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 -#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20 -#define AT91C_PB20_PWM1 (AT91C_PIO_PB20) // PWM Channel 1 -#define AT91C_PB20_PCK0 (AT91C_PIO_PB20) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21 -#define AT91C_PB21_PWM2 (AT91C_PIO_PB21) // PWM Channel 2 -#define AT91C_PB21_PCK1 (AT91C_PIO_PB21) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22 -#define AT91C_PB22_PWM3 (AT91C_PIO_PB22) // PWM Channel 3 -#define AT91C_PB22_PCK2 (AT91C_PIO_PB22) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23 -#define AT91C_PB23_TIOA0 (AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A -#define AT91C_PB23_DCD1 (AT91C_PIO_PB23) // USART 1 Data Carrier Detect -#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24 -#define AT91C_PB24_TIOB0 (AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B -#define AT91C_PB24_DSR1 (AT91C_PIO_PB24) // USART 1 Data Set ready -#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25 -#define AT91C_PB25_TIOA1 (AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A -#define AT91C_PB25_DTR1 (AT91C_PIO_PB25) // USART 1 Data Terminal ready -#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26 -#define AT91C_PB26_TIOB1 (AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B -#define AT91C_PB26_RI1 (AT91C_PIO_PB26) // USART 1 Ring Indicator -#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27 -#define AT91C_PB27_TIOA2 (AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A -#define AT91C_PB27_PWM0 (AT91C_PIO_PB27) // PWM Channel 0 -#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28 -#define AT91C_PB28_TIOB2 (AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B -#define AT91C_PB28_PWM1 (AT91C_PIO_PB28) // PWM Channel 1 -#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29 -#define AT91C_PB29_PCK1 (AT91C_PIO_PB29) // PMC Programmable Clock Output 1 -#define AT91C_PB29_PWM2 (AT91C_PIO_PB29) // PWM Channel 2 -#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3 -#define AT91C_PB3_ETX1 (AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 -#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30 -#define AT91C_PB30_PCK2 (AT91C_PIO_PB30) // PMC Programmable Clock Output 2 -#define AT91C_PB30_PWM3 (AT91C_PIO_PB30) // PWM Channel 3 -#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4 -#define AT91C_PB4_ECRS_ECRSDV (AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid -#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5 -#define AT91C_PB5_ERX0 (AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 -#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6 -#define AT91C_PB6_ERX1 (AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 -#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7 -#define AT91C_PB7_ERXER (AT91C_PIO_PB7) // Ethernet MAC Receive Error -#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8 -#define AT91C_PB8_EMDC (AT91C_PIO_PB8) // Ethernet MAC Management Data Clock -#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9 -#define AT91C_PB9_EMDIO (AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output - -// ***************************************************************************** -// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128 -// ***************************************************************************** -#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) -#define AT91C_ID_SYS ( 1) // System Peripheral -#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A -#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B -#define AT91C_ID_SPI0 ( 4) // Serial Peripheral Interface 0 -#define AT91C_ID_SPI1 ( 5) // Serial Peripheral Interface 1 -#define AT91C_ID_US0 ( 6) // USART 0 -#define AT91C_ID_US1 ( 7) // USART 1 -#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller -#define AT91C_ID_TWI ( 9) // Two-Wire Interface -#define AT91C_ID_PWMC (10) // PWM Controller -#define AT91C_ID_UDP (11) // USB Device Port -#define AT91C_ID_TC0 (12) // Timer Counter 0 -#define AT91C_ID_TC1 (13) // Timer Counter 1 -#define AT91C_ID_TC2 (14) // Timer Counter 2 -#define AT91C_ID_CAN (15) // Control Area Network Controller -#define AT91C_ID_EMAC (16) // Ethernet MAC -#define AT91C_ID_ADC (17) // Analog-to-Digital Converter -#define AT91C_ID_AES (18) // Advanced Encryption Standard 128-bit -#define AT91C_ID_TDES (19) // Triple Data Encryption Standard -#define AT91C_ID_20_Reserved (20) // Reserved -#define AT91C_ID_21_Reserved (21) // Reserved -#define AT91C_ID_22_Reserved (22) // Reserved -#define AT91C_ID_23_Reserved (23) // Reserved -#define AT91C_ID_24_Reserved (24) // Reserved -#define AT91C_ID_25_Reserved (25) // Reserved -#define AT91C_ID_26_Reserved (26) // Reserved -#define AT91C_ID_27_Reserved (27) // Reserved -#define AT91C_ID_28_Reserved (28) // Reserved -#define AT91C_ID_29_Reserved (29) // Reserved -#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) -#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) - -// ***************************************************************************** -// BASE ADDRESS DEFINITIONS FOR AT91SAM7X128 -// ***************************************************************************** -#define AT91C_BASE_SYS (0xFFFFF000) // (SYS) Base Address -#define AT91C_BASE_AIC (0xFFFFF000) // (AIC) Base Address -#define AT91C_BASE_PDC_DBGU (0xFFFFF300) // (PDC_DBGU) Base Address -#define AT91C_BASE_DBGU (0xFFFFF200) // (DBGU) Base Address -#define AT91C_BASE_PIOA (0xFFFFF400) // (PIOA) Base Address -#define AT91C_BASE_PIOB (0xFFFFF600) // (PIOB) Base Address -#define AT91C_BASE_CKGR (0xFFFFFC20) // (CKGR) Base Address -#define AT91C_BASE_PMC (0xFFFFFC00) // (PMC) Base Address -#define AT91C_BASE_RSTC (0xFFFFFD00) // (RSTC) Base Address -#define AT91C_BASE_RTTC (0xFFFFFD20) // (RTTC) Base Address -#define AT91C_BASE_PITC (0xFFFFFD30) // (PITC) Base Address -#define AT91C_BASE_WDTC (0xFFFFFD40) // (WDTC) Base Address -#define AT91C_BASE_VREG (0xFFFFFD60) // (VREG) Base Address -#define AT91C_BASE_MC (0xFFFFFF00) // (MC) Base Address -#define AT91C_BASE_PDC_SPI1 (0xFFFE4100) // (PDC_SPI1) Base Address -#define AT91C_BASE_SPI1 (0xFFFE4000) // (SPI1) Base Address -#define AT91C_BASE_PDC_SPI0 (0xFFFE0100) // (PDC_SPI0) Base Address -#define AT91C_BASE_SPI0 (0xFFFE0000) // (SPI0) Base Address -#define AT91C_BASE_PDC_US1 (0xFFFC4100) // (PDC_US1) Base Address -#define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address -#define AT91C_BASE_PDC_US0 (0xFFFC0100) // (PDC_US0) Base Address -#define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address -#define AT91C_BASE_PDC_SSC (0xFFFD4100) // (PDC_SSC) Base Address -#define AT91C_BASE_SSC (0xFFFD4000) // (SSC) Base Address -#define AT91C_BASE_TWI (0xFFFB8000) // (TWI) Base Address -#define AT91C_BASE_PWMC_CH3 (0xFFFCC260) // (PWMC_CH3) Base Address -#define AT91C_BASE_PWMC_CH2 (0xFFFCC240) // (PWMC_CH2) Base Address -#define AT91C_BASE_PWMC_CH1 (0xFFFCC220) // (PWMC_CH1) Base Address -#define AT91C_BASE_PWMC_CH0 (0xFFFCC200) // (PWMC_CH0) Base Address -#define AT91C_BASE_PWMC (0xFFFCC000) // (PWMC) Base Address -#define AT91C_BASE_UDP (0xFFFB0000) // (UDP) Base Address -#define AT91C_BASE_TC0 (0xFFFA0000) // (TC0) Base Address -#define AT91C_BASE_TC1 (0xFFFA0040) // (TC1) Base Address -#define AT91C_BASE_TC2 (0xFFFA0080) // (TC2) Base Address -#define AT91C_BASE_TCB (0xFFFA0000) // (TCB) Base Address -#define AT91C_BASE_CAN_MB0 (0xFFFD0200) // (CAN_MB0) Base Address -#define AT91C_BASE_CAN_MB1 (0xFFFD0220) // (CAN_MB1) Base Address -#define AT91C_BASE_CAN_MB2 (0xFFFD0240) // (CAN_MB2) Base Address -#define AT91C_BASE_CAN_MB3 (0xFFFD0260) // (CAN_MB3) Base Address -#define AT91C_BASE_CAN_MB4 (0xFFFD0280) // (CAN_MB4) Base Address -#define AT91C_BASE_CAN_MB5 (0xFFFD02A0) // (CAN_MB5) Base Address -#define AT91C_BASE_CAN_MB6 (0xFFFD02C0) // (CAN_MB6) Base Address -#define AT91C_BASE_CAN_MB7 (0xFFFD02E0) // (CAN_MB7) Base Address -#define AT91C_BASE_CAN (0xFFFD0000) // (CAN) Base Address -#define AT91C_BASE_EMAC (0xFFFDC000) // (EMAC) Base Address -#define AT91C_BASE_PDC_ADC (0xFFFD8100) // (PDC_ADC) Base Address -#define AT91C_BASE_ADC (0xFFFD8000) // (ADC) Base Address -#define AT91C_BASE_PDC_AES (0xFFFA4100) // (PDC_AES) Base Address -#define AT91C_BASE_AES (0xFFFA4000) // (AES) Base Address -#define AT91C_BASE_PDC_TDES (0xFFFA8100) // (PDC_TDES) Base Address -#define AT91C_BASE_TDES (0xFFFA8000) // (TDES) Base Address - -// ***************************************************************************** -// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128 -// ***************************************************************************** -#define AT91C_ISRAM (0x00200000) // Internal SRAM base address -#define AT91C_ISRAM_SIZE (0x00008000) // Internal SRAM size in byte (32 Kbyte) -#define AT91C_IFLASH (0x00100000) // Internal ROM base address -#define AT91C_IFLASH_SIZE (0x00020000) // Internal ROM size in byte (128 Kbyte) - - diff --git a/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h b/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h deleted file mode 100644 index 6b73f8a93..000000000 --- a/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h +++ /dev/null @@ -1,2715 +0,0 @@ -// ---------------------------------------------------------------------------- -// ATMEL Microcontroller Software Support - ROUSSET - -// ---------------------------------------------------------------------------- -// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// ---------------------------------------------------------------------------- -// File Name : AT91SAM7X256.h -// Object : AT91SAM7X256 definitions -// Generated : AT91 SW Application Group 05/20/2005 (16:22:29) -// -// CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005// -// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// -// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// -// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// -// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// -// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// -// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// -// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// -// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// -// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// -// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// -// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// -// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// -// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// -// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// -// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// -// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// -// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// -// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// -// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// -// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// -// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// -// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// -// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// -// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// -// ---------------------------------------------------------------------------- - -#ifndef AT91SAM7X256_H -#define AT91SAM7X256_H - -typedef volatile unsigned int AT91_REG;// Hardware register definition - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Peripherals -// ***************************************************************************** -typedef struct _AT91S_SYS { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register - AT91_REG Reserved2[45]; // - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved3[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved4[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register - AT91_REG Reserved5[54]; // - AT91_REG PIOA_PER; // PIO Enable Register - AT91_REG PIOA_PDR; // PIO Disable Register - AT91_REG PIOA_PSR; // PIO Status Register - AT91_REG Reserved6[1]; // - AT91_REG PIOA_OER; // Output Enable Register - AT91_REG PIOA_ODR; // Output Disable Registerr - AT91_REG PIOA_OSR; // Output Status Register - AT91_REG Reserved7[1]; // - AT91_REG PIOA_IFER; // Input Filter Enable Register - AT91_REG PIOA_IFDR; // Input Filter Disable Register - AT91_REG PIOA_IFSR; // Input Filter Status Register - AT91_REG Reserved8[1]; // - AT91_REG PIOA_SODR; // Set Output Data Register - AT91_REG PIOA_CODR; // Clear Output Data Register - AT91_REG PIOA_ODSR; // Output Data Status Register - AT91_REG PIOA_PDSR; // Pin Data Status Register - AT91_REG PIOA_IER; // Interrupt Enable Register - AT91_REG PIOA_IDR; // Interrupt Disable Register - AT91_REG PIOA_IMR; // Interrupt Mask Register - AT91_REG PIOA_ISR; // Interrupt Status Register - AT91_REG PIOA_MDER; // Multi-driver Enable Register - AT91_REG PIOA_MDDR; // Multi-driver Disable Register - AT91_REG PIOA_MDSR; // Multi-driver Status Register - AT91_REG Reserved9[1]; // - AT91_REG PIOA_PPUDR; // Pull-up Disable Register - AT91_REG PIOA_PPUER; // Pull-up Enable Register - AT91_REG PIOA_PPUSR; // Pull-up Status Register - AT91_REG Reserved10[1]; // - AT91_REG PIOA_ASR; // Select A Register - AT91_REG PIOA_BSR; // Select B Register - AT91_REG PIOA_ABSR; // AB Select Status Register - AT91_REG Reserved11[9]; // - AT91_REG PIOA_OWER; // Output Write Enable Register - AT91_REG PIOA_OWDR; // Output Write Disable Register - AT91_REG PIOA_OWSR; // Output Write Status Register - AT91_REG Reserved12[85]; // - AT91_REG PIOB_PER; // PIO Enable Register - AT91_REG PIOB_PDR; // PIO Disable Register - AT91_REG PIOB_PSR; // PIO Status Register - AT91_REG Reserved13[1]; // - AT91_REG PIOB_OER; // Output Enable Register - AT91_REG PIOB_ODR; // Output Disable Registerr - AT91_REG PIOB_OSR; // Output Status Register - AT91_REG Reserved14[1]; // - AT91_REG PIOB_IFER; // Input Filter Enable Register - AT91_REG PIOB_IFDR; // Input Filter Disable Register - AT91_REG PIOB_IFSR; // Input Filter Status Register - AT91_REG Reserved15[1]; // - AT91_REG PIOB_SODR; // Set Output Data Register - AT91_REG PIOB_CODR; // Clear Output Data Register - AT91_REG PIOB_ODSR; // Output Data Status Register - AT91_REG PIOB_PDSR; // Pin Data Status Register - AT91_REG PIOB_IER; // Interrupt Enable Register - AT91_REG PIOB_IDR; // Interrupt Disable Register - AT91_REG PIOB_IMR; // Interrupt Mask Register - AT91_REG PIOB_ISR; // Interrupt Status Register - AT91_REG PIOB_MDER; // Multi-driver Enable Register - AT91_REG PIOB_MDDR; // Multi-driver Disable Register - AT91_REG PIOB_MDSR; // Multi-driver Status Register - AT91_REG Reserved16[1]; // - AT91_REG PIOB_PPUDR; // Pull-up Disable Register - AT91_REG PIOB_PPUER; // Pull-up Enable Register - AT91_REG PIOB_PPUSR; // Pull-up Status Register - AT91_REG Reserved17[1]; // - AT91_REG PIOB_ASR; // Select A Register - AT91_REG PIOB_BSR; // Select B Register - AT91_REG PIOB_ABSR; // AB Select Status Register - AT91_REG Reserved18[9]; // - AT91_REG PIOB_OWER; // Output Write Enable Register - AT91_REG PIOB_OWDR; // Output Write Disable Register - AT91_REG PIOB_OWSR; // Output Write Status Register - AT91_REG Reserved19[341]; // - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved20[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved21[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved22[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved23[3]; // - AT91_REG PMC_PCKR[4]; // Programmable Clock Register - AT91_REG Reserved24[4]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register - AT91_REG Reserved25[36]; // - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register - AT91_REG Reserved26[5]; // - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register - AT91_REG Reserved27[5]; // - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_SYS, *AT91PS_SYS; - - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// ***************************************************************************** -typedef struct _AT91S_AIC { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register -} AT91S_AIC, *AT91PS_AIC; - -// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level -#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level -#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level -#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type -#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive -#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered -#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered -#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered -// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status -#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status -// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode -#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Peripheral DMA Controller -// ***************************************************************************** -typedef struct _AT91S_PDC { - AT91_REG PDC_RPR; // Receive Pointer Register - AT91_REG PDC_RCR; // Receive Counter Register - AT91_REG PDC_TPR; // Transmit Pointer Register - AT91_REG PDC_TCR; // Transmit Counter Register - AT91_REG PDC_RNPR; // Receive Next Pointer Register - AT91_REG PDC_RNCR; // Receive Next Counter Register - AT91_REG PDC_TNPR; // Transmit Next Pointer Register - AT91_REG PDC_TNCR; // Transmit Next Counter Register - AT91_REG PDC_PTCR; // PDC Transfer Control Register - AT91_REG PDC_PTSR; // PDC Transfer Status Register -} AT91S_PDC, *AT91PS_PDC; - -// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable -#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable -#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable -#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable -// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Debug Unit -// ***************************************************************************** -typedef struct _AT91S_DBGU { - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved0[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved1[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register -} AT91S_DBGU, *AT91PS_DBGU; - -// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver -#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter -#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable -#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable -#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable -#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable -#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits -// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type -#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity -#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity -#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space) -#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark) -#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity -#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode -#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode -#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt -#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt -#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt -#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt -#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt -#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt -#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt -#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt -#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt -#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt -#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt -#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt -// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// ***************************************************************************** -typedef struct _AT91S_PIO { - AT91_REG PIO_PER; // PIO Enable Register - AT91_REG PIO_PDR; // PIO Disable Register - AT91_REG PIO_PSR; // PIO Status Register - AT91_REG Reserved0[1]; // - AT91_REG PIO_OER; // Output Enable Register - AT91_REG PIO_ODR; // Output Disable Registerr - AT91_REG PIO_OSR; // Output Status Register - AT91_REG Reserved1[1]; // - AT91_REG PIO_IFER; // Input Filter Enable Register - AT91_REG PIO_IFDR; // Input Filter Disable Register - AT91_REG PIO_IFSR; // Input Filter Status Register - AT91_REG Reserved2[1]; // - AT91_REG PIO_SODR; // Set Output Data Register - AT91_REG PIO_CODR; // Clear Output Data Register - AT91_REG PIO_ODSR; // Output Data Status Register - AT91_REG PIO_PDSR; // Pin Data Status Register - AT91_REG PIO_IER; // Interrupt Enable Register - AT91_REG PIO_IDR; // Interrupt Disable Register - AT91_REG PIO_IMR; // Interrupt Mask Register - AT91_REG PIO_ISR; // Interrupt Status Register - AT91_REG PIO_MDER; // Multi-driver Enable Register - AT91_REG PIO_MDDR; // Multi-driver Disable Register - AT91_REG PIO_MDSR; // Multi-driver Status Register - AT91_REG Reserved3[1]; // - AT91_REG PIO_PPUDR; // Pull-up Disable Register - AT91_REG PIO_PPUER; // Pull-up Enable Register - AT91_REG PIO_PPUSR; // Pull-up Status Register - AT91_REG Reserved4[1]; // - AT91_REG PIO_ASR; // Select A Register - AT91_REG PIO_BSR; // Select B Register - AT91_REG PIO_ABSR; // AB Select Status Register - AT91_REG Reserved5[9]; // - AT91_REG PIO_OWER; // Output Write Enable Register - AT91_REG PIO_OWDR; // Output Write Disable Register - AT91_REG PIO_OWSR; // Output Write Status Register -} AT91S_PIO, *AT91PS_PIO; - - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Clock Generator Controler -// ***************************************************************************** -typedef struct _AT91S_CKGR { - AT91_REG CKGR_MOR; // Main Oscillator Register - AT91_REG CKGR_MCFR; // Main Clock Frequency Register - AT91_REG Reserved0[1]; // - AT91_REG CKGR_PLLR; // PLL Register -} AT91S_CKGR, *AT91PS_CKGR; - -// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable -#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass -#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time -// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency -#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready -// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- -#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter -#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range -#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier -#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks -#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output -#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 -#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Power Management Controler -// ***************************************************************************** -typedef struct _AT91S_PMC { - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved0[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved1[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved2[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved3[3]; // - AT91_REG PMC_PCKR[4]; // Programmable Clock Register - AT91_REG Reserved4[4]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register -} AT91S_PMC, *AT91PS_PMC; - -// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock -#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock -#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output -// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- -// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- -// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- -// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection -#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected -#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected -#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected -#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler -#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock -#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 -#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 -#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 -#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 -#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 -#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 -// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask -#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask -#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask -// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Reset Controller Interface -// ***************************************************************************** -typedef struct _AT91S_RSTC { - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register -} AT91S_RSTC, *AT91PS_RSTC; - -// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- -#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset -#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset -#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset -#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password -// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- -#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status -#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status -#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type -#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. -#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. -#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low. -#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured. -#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level -#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress. -// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- -#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable -#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable -#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable -#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_RTTC { - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register -} AT91S_RTTC, *AT91PS_RTTC; - -// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- -#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value -#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable -#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable -#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart -// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- -#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value -// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- -#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value -// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- -#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status -#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_PITC { - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register -} AT91S_PITC, *AT91PS_PITC; - -// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- -#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value -#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled -#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable -// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- -#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status -// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- -#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value -#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter -// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_WDTC { - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register -} AT91S_WDTC, *AT91PS_WDTC; - -// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- -#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart -#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password -// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- -#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable -#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable -#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable -#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value -#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt -#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt -// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- -#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow -#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface -// ***************************************************************************** -typedef struct _AT91S_VREG { - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_VREG, *AT91PS_VREG; - -// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- -#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Memory Controller Interface -// ***************************************************************************** -typedef struct _AT91S_MC { - AT91_REG MC_RCR; // MC Remap Control Register - AT91_REG MC_ASR; // MC Abort Status Register - AT91_REG MC_AASR; // MC Abort Address Status Register - AT91_REG Reserved0[21]; // - AT91_REG MC_FMR; // MC Flash Mode Register - AT91_REG MC_FCR; // MC Flash Command Register - AT91_REG MC_FSR; // MC Flash Status Register -} AT91S_MC, *AT91PS_MC; - -// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit -// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status -#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status -#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status -#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte -#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word -#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word -#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status -#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read -#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write -#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch -#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source -#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source -#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source -#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source -// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- -#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready -#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error -#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error -#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming -#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State -#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations -#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations -#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations -#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations -#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number -// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- -#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command -#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN. -#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. -#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. -#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits. -#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits. -#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit. -#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number -#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key -// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- -#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status -#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status -#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status -#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status -#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status -#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status -#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status -#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status -#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status -#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status -#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status -#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status -#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status -#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status -#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status -#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status -#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status -#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status -#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status -#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status -#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status -#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status -#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Serial Parallel Interface -// ***************************************************************************** -typedef struct _AT91S_SPI { - AT91_REG SPI_CR; // Control Register - AT91_REG SPI_MR; // Mode Register - AT91_REG SPI_RDR; // Receive Data Register - AT91_REG SPI_TDR; // Transmit Data Register - AT91_REG SPI_SR; // Status Register - AT91_REG SPI_IER; // Interrupt Enable Register - AT91_REG SPI_IDR; // Interrupt Disable Register - AT91_REG SPI_IMR; // Interrupt Mask Register - AT91_REG Reserved0[4]; // - AT91_REG SPI_CSR[4]; // Chip Select Register - AT91_REG Reserved1[48]; // - AT91_REG SPI_RPR; // Receive Pointer Register - AT91_REG SPI_RCR; // Receive Counter Register - AT91_REG SPI_TPR; // Transmit Pointer Register - AT91_REG SPI_TCR; // Transmit Counter Register - AT91_REG SPI_RNPR; // Receive Next Pointer Register - AT91_REG SPI_RNCR; // Receive Next Counter Register - AT91_REG SPI_TNPR; // Transmit Next Pointer Register - AT91_REG SPI_TNCR; // Transmit Next Counter Register - AT91_REG SPI_PTCR; // PDC Transfer Control Register - AT91_REG SPI_PTSR; // PDC Transfer Status Register -} AT91S_SPI, *AT91PS_SPI; - -// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable -#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable -#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset -#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer -// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode -#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select -#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select -#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select -#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode -#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection -#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection -#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection -#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select -#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects -// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data -#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data -#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full -#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty -#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error -#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status -#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer -#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer -#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt -#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt -#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt -#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt -#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status -// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity -#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase -#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer -#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer -#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer -#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer -#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer -#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer -#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer -#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer -#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer -#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer -#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer -#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK -#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Usart -// ***************************************************************************** -typedef struct _AT91S_USART { - AT91_REG US_CR; // Control Register - AT91_REG US_MR; // Mode Register - AT91_REG US_IER; // Interrupt Enable Register - AT91_REG US_IDR; // Interrupt Disable Register - AT91_REG US_IMR; // Interrupt Mask Register - AT91_REG US_CSR; // Channel Status Register - AT91_REG US_RHR; // Receiver Holding Register - AT91_REG US_THR; // Transmitter Holding Register - AT91_REG US_BRGR; // Baud Rate Generator Register - AT91_REG US_RTOR; // Receiver Time-out Register - AT91_REG US_TTGR; // Transmitter Time-guard Register - AT91_REG Reserved0[5]; // - AT91_REG US_FIDI; // FI_DI_Ratio Register - AT91_REG US_NER; // Nb Errors Register - AT91_REG Reserved1[1]; // - AT91_REG US_IF; // IRDA_FILTER Register - AT91_REG Reserved2[44]; // - AT91_REG US_RPR; // Receive Pointer Register - AT91_REG US_RCR; // Receive Counter Register - AT91_REG US_TPR; // Transmit Pointer Register - AT91_REG US_TCR; // Transmit Counter Register - AT91_REG US_RNPR; // Receive Next Pointer Register - AT91_REG US_RNCR; // Receive Next Counter Register - AT91_REG US_TNPR; // Transmit Next Pointer Register - AT91_REG US_TNCR; // Transmit Next Counter Register - AT91_REG US_PTCR; // PDC Transfer Control Register - AT91_REG US_PTSR; // PDC Transfer Status Register -} AT91S_USART, *AT91PS_USART; - -// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break -#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break -#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out -#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address -#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations -#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge -#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out -#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable -#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable -#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable -#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable -// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode -#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal -#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 -#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking -#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem -#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0 -#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1 -#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA -#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking -#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock -#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 -#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) -#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) -#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits -#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits -#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits -#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits -#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select -#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits -#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit -#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits -#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order -#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length -#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select -#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode -#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge -#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK -#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions -#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter -// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break -#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out -#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached -#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge -#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag -#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag -#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag -#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag -// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input -#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input -#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input -#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// ***************************************************************************** -typedef struct _AT91S_SSC { - AT91_REG SSC_CR; // Control Register - AT91_REG SSC_CMR; // Clock Mode Register - AT91_REG Reserved0[2]; // - AT91_REG SSC_RCMR; // Receive Clock ModeRegister - AT91_REG SSC_RFMR; // Receive Frame Mode Register - AT91_REG SSC_TCMR; // Transmit Clock Mode Register - AT91_REG SSC_TFMR; // Transmit Frame Mode Register - AT91_REG SSC_RHR; // Receive Holding Register - AT91_REG SSC_THR; // Transmit Holding Register - AT91_REG Reserved1[2]; // - AT91_REG SSC_RSHR; // Receive Sync Holding Register - AT91_REG SSC_TSHR; // Transmit Sync Holding Register - AT91_REG Reserved2[2]; // - AT91_REG SSC_SR; // Status Register - AT91_REG SSC_IER; // Interrupt Enable Register - AT91_REG SSC_IDR; // Interrupt Disable Register - AT91_REG SSC_IMR; // Interrupt Mask Register - AT91_REG Reserved3[44]; // - AT91_REG SSC_RPR; // Receive Pointer Register - AT91_REG SSC_RCR; // Receive Counter Register - AT91_REG SSC_TPR; // Transmit Pointer Register - AT91_REG SSC_TCR; // Transmit Counter Register - AT91_REG SSC_RNPR; // Receive Next Pointer Register - AT91_REG SSC_RNCR; // Receive Next Counter Register - AT91_REG SSC_TNPR; // Transmit Next Pointer Register - AT91_REG SSC_TNCR; // Transmit Next Counter Register - AT91_REG SSC_PTCR; // PDC Transfer Control Register - AT91_REG SSC_PTSR; // PDC Transfer Status Register -} AT91S_SSC, *AT91PS_SSC; - -// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable -#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable -#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable -#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable -#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset -// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection -#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock -#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal -#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin -#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection -#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output -#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion -#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection -#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start -#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input -#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input -#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input -#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input -#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input -#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input -#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0 -#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay -#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection -// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length -#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode -#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First -#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame -#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length -#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection -#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection -// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value -#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable -// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready -#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty -#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission -#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty -#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready -#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun -#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception -#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full -#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync -#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync -#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable -#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable -// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Two-wire Interface -// ***************************************************************************** -typedef struct _AT91S_TWI { - AT91_REG TWI_CR; // Control Register - AT91_REG TWI_MMR; // Master Mode Register - AT91_REG Reserved0[1]; // - AT91_REG TWI_IADR; // Internal Address Register - AT91_REG TWI_CWGR; // Clock Waveform Generator Register - AT91_REG Reserved1[3]; // - AT91_REG TWI_SR; // Status Register - AT91_REG TWI_IER; // Interrupt Enable Register - AT91_REG TWI_IDR; // Interrupt Disable Register - AT91_REG TWI_IMR; // Interrupt Mask Register - AT91_REG TWI_RHR; // Receive Holding Register - AT91_REG TWI_THR; // Transmit Holding Register -} AT91S_TWI, *AT91PS_TWI; - -// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition -#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition -#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled -#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled -#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset -// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size -#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address -#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address -#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address -#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address -#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction -#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address -// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider -#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider -#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider -// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed -#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY -#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY -#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error -#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error -#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged -// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR PWMC Channel Interface -// ***************************************************************************** -typedef struct _AT91S_PWMC_CH { - AT91_REG PWMC_CMR; // Channel Mode Register - AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register - AT91_REG PWMC_CPRDR; // Channel Period Register - AT91_REG PWMC_CCNTR; // Channel Counter Register - AT91_REG PWMC_CUPDR; // Channel Update Register - AT91_REG PWMC_Reserved[3]; // Reserved -} AT91S_PWMC_CH, *AT91PS_PWMC_CH; - -// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- -#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx -#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) -#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment -#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity -#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period -// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- -#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle -// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- -#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period -// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- -#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter -// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- -#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface -// ***************************************************************************** -typedef struct _AT91S_PWMC { - AT91_REG PWMC_MR; // PWMC Mode Register - AT91_REG PWMC_ENA; // PWMC Enable Register - AT91_REG PWMC_DIS; // PWMC Disable Register - AT91_REG PWMC_SR; // PWMC Status Register - AT91_REG PWMC_IER; // PWMC Interrupt Enable Register - AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register - AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register - AT91_REG PWMC_ISR; // PWMC Interrupt Status Register - AT91_REG Reserved0[55]; // - AT91_REG PWMC_VR; // PWMC Version Register - AT91_REG Reserved1[64]; // - AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel -} AT91S_PWMC, *AT91PS_PWMC; - -// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- -#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor. -#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A -#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) -#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor. -#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B -#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) -// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- -#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0 -#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1 -#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2 -#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3 -// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- -// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- -// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- -// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- -// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- -// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Device Interface -// ***************************************************************************** -typedef struct _AT91S_UDP { - AT91_REG UDP_NUM; // Frame Number Register - AT91_REG UDP_GLBSTATE; // Global State Register - AT91_REG UDP_FADDR; // Function Address Register - AT91_REG Reserved0[1]; // - AT91_REG UDP_IER; // Interrupt Enable Register - AT91_REG UDP_IDR; // Interrupt Disable Register - AT91_REG UDP_IMR; // Interrupt Mask Register - AT91_REG UDP_ISR; // Interrupt Status Register - AT91_REG UDP_ICR; // Interrupt Clear Register - AT91_REG Reserved1[1]; // - AT91_REG UDP_RSTEP; // Reset Endpoint Register - AT91_REG Reserved2[1]; // - AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register - AT91_REG Reserved3[2]; // - AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register - AT91_REG Reserved4[3]; // - AT91_REG UDP_TXVC; // Transceiver Control Register -} AT91S_UDP, *AT91PS_UDP; - -// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats -#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error -#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK -// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable -#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured -#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume -#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host -#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable -// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value -#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable -// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt -#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt -#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt -#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt -#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt -#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt -#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt -#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt -#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt -// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt -// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 -#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 -#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 -#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3 -#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4 -#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5 -// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR -#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 -#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) -#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) -#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready -#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction -#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type -#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control -#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT -#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT -#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT -#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN -#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN -#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN -#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle -#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable -#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO -// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- -#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP) -#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// ***************************************************************************** -typedef struct _AT91S_TC { - AT91_REG TC_CCR; // Channel Control Register - AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) - AT91_REG Reserved0[2]; // - AT91_REG TC_CV; // Counter Value - AT91_REG TC_RA; // Register A - AT91_REG TC_RB; // Register B - AT91_REG TC_RC; // Register C - AT91_REG TC_SR; // Status Register - AT91_REG TC_IER; // Interrupt Enable Register - AT91_REG TC_IDR; // Interrupt Disable Register - AT91_REG TC_IMR; // Interrupt Mask Register -} AT91S_TC, *AT91PS_TC; - -// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command -#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command -#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command -// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection -#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK -#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0 -#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1 -#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2 -#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert -#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection -#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal -#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock -#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock -#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock -#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare -#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading -#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare -#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading -#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection -#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None -#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection -#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None -#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection -#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input -#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output -#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output -#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output -#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection -#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable -#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection -#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare -#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable -#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) -#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA -#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none -#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set -#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear -#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle -#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection -#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None -#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA -#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA -#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none -#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set -#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear -#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle -#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection -#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None -#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA -#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA -#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none -#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set -#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear -#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle -#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA -#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none -#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set -#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear -#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle -#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB -#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none -#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set -#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear -#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle -#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB -#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none -#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set -#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear -#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle -#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB -#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none -#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set -#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear -#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle -#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB -#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none -#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set -#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear -#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle -// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow -#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun -#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare -#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare -#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare -#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading -#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading -#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger -#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling -#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror -#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror -// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Interface -// ***************************************************************************** -typedef struct _AT91S_TCB { - AT91S_TC TCB_TC0; // TC Channel 0 - AT91_REG Reserved0[4]; // - AT91S_TC TCB_TC1; // TC Channel 1 - AT91_REG Reserved1[4]; // - AT91S_TC TCB_TC2; // TC Channel 2 - AT91_REG Reserved2[4]; // - AT91_REG TCB_BCR; // TC Block Control Register - AT91_REG TCB_BMR; // TC Block Mode Register -} AT91S_TCB, *AT91PS_TCB; - -// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command -// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection -#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 -#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 -#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection -#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 -#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 -#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection -#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 -#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface -// ***************************************************************************** -typedef struct _AT91S_CAN_MB { - AT91_REG CAN_MB_MMR; // MailBox Mode Register - AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register - AT91_REG CAN_MB_MID; // MailBox ID Register - AT91_REG CAN_MB_MFID; // MailBox Family ID Register - AT91_REG CAN_MB_MSR; // MailBox Status Register - AT91_REG CAN_MB_MDL; // MailBox Data Low Register - AT91_REG CAN_MB_MDH; // MailBox Data High Register - AT91_REG CAN_MB_MCR; // MailBox Control Register -} AT91S_CAN_MB, *AT91PS_CAN_MB; - -// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- -#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark -#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority -#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type -#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB) -// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- -#define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode -#define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode -#define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version -// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- -// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- -// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- -#define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value -#define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code -#define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request -#define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort -#define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready -#define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored -// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- -// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- -// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- -#define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox -#define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network Interface -// ***************************************************************************** -typedef struct _AT91S_CAN { - AT91_REG CAN_MR; // Mode Register - AT91_REG CAN_IER; // Interrupt Enable Register - AT91_REG CAN_IDR; // Interrupt Disable Register - AT91_REG CAN_IMR; // Interrupt Mask Register - AT91_REG CAN_SR; // Status Register - AT91_REG CAN_BR; // Baudrate Register - AT91_REG CAN_TIM; // Timer Register - AT91_REG CAN_TIMESTP; // Time Stamp Register - AT91_REG CAN_ECR; // Error Counter Register - AT91_REG CAN_TCR; // Transfer Command Register - AT91_REG CAN_ACR; // Abort Command Register - AT91_REG Reserved0[52]; // - AT91_REG CAN_VR; // Version Register - AT91_REG Reserved1[64]; // - AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0 - AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1 - AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2 - AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3 - AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4 - AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5 - AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6 - AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7 - AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8 - AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9 - AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10 - AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11 - AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12 - AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13 - AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14 - AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15 -} AT91S_CAN, *AT91PS_CAN; - -// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- -#define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable -#define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode -#define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode -#define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame -#define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame -#define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode -#define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze -#define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat -// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- -#define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag -#define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag -#define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag -#define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag -#define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag -#define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag -#define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag -#define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag -#define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag -#define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag -#define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag -#define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag -#define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag -#define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag -#define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag -#define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag -#define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag -#define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag -#define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag -#define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag -#define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag -#define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag -#define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag -#define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag -#define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error -#define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error -#define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error -#define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error -#define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error -// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- -// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- -// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- -#define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy -#define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy -#define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy -// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- -#define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment -#define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment -#define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment -#define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment -#define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler -#define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode -// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- -#define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field -// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- -// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- -#define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter -#define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter -// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- -#define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field -// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 -// ***************************************************************************** -typedef struct _AT91S_EMAC { - AT91_REG EMAC_NCR; // Network Control Register - AT91_REG EMAC_NCFGR; // Network Configuration Register - AT91_REG EMAC_NSR; // Network Status Register - AT91_REG Reserved0[2]; // - AT91_REG EMAC_TSR; // Transmit Status Register - AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer - AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer - AT91_REG EMAC_RSR; // Receive Status Register - AT91_REG EMAC_ISR; // Interrupt Status Register - AT91_REG EMAC_IER; // Interrupt Enable Register - AT91_REG EMAC_IDR; // Interrupt Disable Register - AT91_REG EMAC_IMR; // Interrupt Mask Register - AT91_REG EMAC_MAN; // PHY Maintenance Register - AT91_REG EMAC_PTR; // Pause Time Register - AT91_REG EMAC_PFR; // Pause Frames received Register - AT91_REG EMAC_FTO; // Frames Transmitted OK Register - AT91_REG EMAC_SCF; // Single Collision Frame Register - AT91_REG EMAC_MCF; // Multiple Collision Frame Register - AT91_REG EMAC_FRO; // Frames Received OK Register - AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register - AT91_REG EMAC_ALE; // Alignment Error Register - AT91_REG EMAC_DTF; // Deferred Transmission Frame Register - AT91_REG EMAC_LCOL; // Late Collision Register - AT91_REG EMAC_ECOL; // Excessive Collision Register - AT91_REG EMAC_TUND; // Transmit Underrun Error Register - AT91_REG EMAC_CSE; // Carrier Sense Error Register - AT91_REG EMAC_RRE; // Receive Ressource Error Register - AT91_REG EMAC_ROV; // Receive Overrun Errors Register - AT91_REG EMAC_RSE; // Receive Symbol Errors Register - AT91_REG EMAC_ELE; // Excessive Length Errors Register - AT91_REG EMAC_RJA; // Receive Jabbers Register - AT91_REG EMAC_USF; // Undersize Frames Register - AT91_REG EMAC_STE; // SQE Test Error Register - AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register - AT91_REG EMAC_TPF; // Transmitted Pause Frames Register - AT91_REG EMAC_HRB; // Hash Address Bottom[31:0] - AT91_REG EMAC_HRT; // Hash Address Top[63:32] - AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes - AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes - AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes - AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes - AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes - AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes - AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes - AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes - AT91_REG EMAC_TID; // Type ID Checking Register - AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register - AT91_REG EMAC_USRIO; // USER Input/Output Register - AT91_REG EMAC_WOL; // Wake On LAN Register - AT91_REG Reserved1[13]; // - AT91_REG EMAC_REV; // Revision Register -} AT91S_EMAC, *AT91PS_EMAC; - -// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- -#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. -#define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local. -#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable. -#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable. -#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable. -#define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers. -#define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers. -#define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers. -#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure. -#define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission. -#define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. -#define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame -#define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame -// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- -#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed. -#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex. -#define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames. -#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames. -#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast. -#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable -#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable. -#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes. -#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable. -#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC) -#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8 -#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16 -#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32 -#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64 -#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC) -#define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC) -#define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC) -#define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer -#define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable -#define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS -#define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC) -#define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS -// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- -#define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC) -// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- -#define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC) -#define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go -#define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame -#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC) -#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC) -// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- -#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC) -// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- -#define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC) -#define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC) -#define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC) -#define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC) -#define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC) -#define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC) -#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC) -#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC) -#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC) -#define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC) -#define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC) -// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- -// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- -// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- -// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- -#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC) -#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC) -#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC) -#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC) -#define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC) -// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- -#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII -// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- -#define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address -#define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable -#define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable -#define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable -// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- -#define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC) - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Analog to Digital Convertor -// ***************************************************************************** -typedef struct _AT91S_ADC { - AT91_REG ADC_CR; // ADC Control Register - AT91_REG ADC_MR; // ADC Mode Register - AT91_REG Reserved0[2]; // - AT91_REG ADC_CHER; // ADC Channel Enable Register - AT91_REG ADC_CHDR; // ADC Channel Disable Register - AT91_REG ADC_CHSR; // ADC Channel Status Register - AT91_REG ADC_SR; // ADC Status Register - AT91_REG ADC_LCDR; // ADC Last Converted Data Register - AT91_REG ADC_IER; // ADC Interrupt Enable Register - AT91_REG ADC_IDR; // ADC Interrupt Disable Register - AT91_REG ADC_IMR; // ADC Interrupt Mask Register - AT91_REG ADC_CDR0; // ADC Channel Data Register 0 - AT91_REG ADC_CDR1; // ADC Channel Data Register 1 - AT91_REG ADC_CDR2; // ADC Channel Data Register 2 - AT91_REG ADC_CDR3; // ADC Channel Data Register 3 - AT91_REG ADC_CDR4; // ADC Channel Data Register 4 - AT91_REG ADC_CDR5; // ADC Channel Data Register 5 - AT91_REG ADC_CDR6; // ADC Channel Data Register 6 - AT91_REG ADC_CDR7; // ADC Channel Data Register 7 - AT91_REG Reserved1[44]; // - AT91_REG ADC_RPR; // Receive Pointer Register - AT91_REG ADC_RCR; // Receive Counter Register - AT91_REG ADC_TPR; // Transmit Pointer Register - AT91_REG ADC_TCR; // Transmit Counter Register - AT91_REG ADC_RNPR; // Receive Next Pointer Register - AT91_REG ADC_RNCR; // Receive Next Counter Register - AT91_REG ADC_TNPR; // Transmit Next Pointer Register - AT91_REG ADC_TNCR; // Transmit Next Counter Register - AT91_REG ADC_PTCR; // PDC Transfer Control Register - AT91_REG ADC_PTSR; // PDC Transfer Status Register -} AT91S_ADC, *AT91PS_ADC; - -// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- -#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset -#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion -// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- -#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable -#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software -#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. -#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection -#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 -#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 -#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 -#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 -#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 -#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 -#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger -#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution. -#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution -#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution -#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode -#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection -#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time -#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time -// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- -#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0 -#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1 -#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2 -#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3 -#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4 -#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5 -#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6 -#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7 -// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- -// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- -// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- -#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion -#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion -#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion -#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion -#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion -#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion -#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion -#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion -#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error -#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error -#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error -#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error -#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error -#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error -#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error -#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error -#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready -#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun -#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer -#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt -// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- -#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted -// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- -// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- -// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- -// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- -#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data -// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- -// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- -// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- -// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- -// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- -// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- -// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Encryption Standard -// ***************************************************************************** -typedef struct _AT91S_AES { - AT91_REG AES_CR; // Control Register - AT91_REG AES_MR; // Mode Register - AT91_REG Reserved0[2]; // - AT91_REG AES_IER; // Interrupt Enable Register - AT91_REG AES_IDR; // Interrupt Disable Register - AT91_REG AES_IMR; // Interrupt Mask Register - AT91_REG AES_ISR; // Interrupt Status Register - AT91_REG AES_KEYWxR[4]; // Key Word x Register - AT91_REG Reserved1[4]; // - AT91_REG AES_IDATAxR[4]; // Input Data x Register - AT91_REG AES_ODATAxR[4]; // Output Data x Register - AT91_REG AES_IVxR[4]; // Initialization Vector x Register - AT91_REG Reserved2[35]; // - AT91_REG AES_VR; // AES Version Register - AT91_REG AES_RPR; // Receive Pointer Register - AT91_REG AES_RCR; // Receive Counter Register - AT91_REG AES_TPR; // Transmit Pointer Register - AT91_REG AES_TCR; // Transmit Counter Register - AT91_REG AES_RNPR; // Receive Next Pointer Register - AT91_REG AES_RNCR; // Receive Next Counter Register - AT91_REG AES_TNPR; // Transmit Next Pointer Register - AT91_REG AES_TNCR; // Transmit Next Counter Register - AT91_REG AES_PTCR; // PDC Transfer Control Register - AT91_REG AES_PTSR; // PDC Transfer Status Register -} AT91S_AES, *AT91PS_AES; - -// -------- AES_CR : (AES Offset: 0x0) Control Register -------- -#define AT91C_AES_START ((unsigned int) 0x1 << 0) // (AES) Starts Processing -#define AT91C_AES_SWRST ((unsigned int) 0x1 << 8) // (AES) Software Reset -#define AT91C_AES_LOADSEED ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading -// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- -#define AT91C_AES_CIPHER ((unsigned int) 0x1 << 0) // (AES) Processing Mode -#define AT91C_AES_PROCDLY ((unsigned int) 0xF << 4) // (AES) Processing Delay -#define AT91C_AES_SMOD ((unsigned int) 0x3 << 8) // (AES) Start Mode -#define AT91C_AES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. -#define AT91C_AES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). -#define AT91C_AES_SMOD_PDC ((unsigned int) 0x2 << 8) // (AES) PDC Mode (cf datasheet). -#define AT91C_AES_OPMOD ((unsigned int) 0x7 << 12) // (AES) Operation Mode -#define AT91C_AES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode. -#define AT91C_AES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode. -#define AT91C_AES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode. -#define AT91C_AES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode. -#define AT91C_AES_OPMOD_CTR ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode. -#define AT91C_AES_LOD ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode -#define AT91C_AES_CFBS ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size -#define AT91C_AES_CFBS_128_BIT ((unsigned int) 0x0 << 16) // (AES) 128-bit. -#define AT91C_AES_CFBS_64_BIT ((unsigned int) 0x1 << 16) // (AES) 64-bit. -#define AT91C_AES_CFBS_32_BIT ((unsigned int) 0x2 << 16) // (AES) 32-bit. -#define AT91C_AES_CFBS_16_BIT ((unsigned int) 0x3 << 16) // (AES) 16-bit. -#define AT91C_AES_CFBS_8_BIT ((unsigned int) 0x4 << 16) // (AES) 8-bit. -#define AT91C_AES_CKEY ((unsigned int) 0xF << 20) // (AES) Countermeasure Key -#define AT91C_AES_CTYPE ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type -#define AT91C_AES_CTYPE_TYPE1_EN ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled. -#define AT91C_AES_CTYPE_TYPE2_EN ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled. -#define AT91C_AES_CTYPE_TYPE3_EN ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled. -#define AT91C_AES_CTYPE_TYPE4_EN ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled. -#define AT91C_AES_CTYPE_TYPE5_EN ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled. -// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- -#define AT91C_AES_DATRDY ((unsigned int) 0x1 << 0) // (AES) DATRDY -#define AT91C_AES_ENDRX ((unsigned int) 0x1 << 1) // (AES) PDC Read Buffer End -#define AT91C_AES_ENDTX ((unsigned int) 0x1 << 2) // (AES) PDC Write Buffer End -#define AT91C_AES_RXBUFF ((unsigned int) 0x1 << 3) // (AES) PDC Read Buffer Full -#define AT91C_AES_TXBUFE ((unsigned int) 0x1 << 4) // (AES) PDC Write Buffer Empty -#define AT91C_AES_URAD ((unsigned int) 0x1 << 8) // (AES) Unspecified Register Access Detection -// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- -// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- -// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- -#define AT91C_AES_URAT ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status -#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode. -#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing. -#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing. -#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation. -#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation. -#define AT91C_AES_URAT_WO_REG_READ ((unsigned int) 0x5 << 12) // (AES) Write-only register read access. - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard -// ***************************************************************************** -typedef struct _AT91S_TDES { - AT91_REG TDES_CR; // Control Register - AT91_REG TDES_MR; // Mode Register - AT91_REG Reserved0[2]; // - AT91_REG TDES_IER; // Interrupt Enable Register - AT91_REG TDES_IDR; // Interrupt Disable Register - AT91_REG TDES_IMR; // Interrupt Mask Register - AT91_REG TDES_ISR; // Interrupt Status Register - AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register - AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register - AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register - AT91_REG Reserved1[2]; // - AT91_REG TDES_IDATAxR[2]; // Input Data x Register - AT91_REG Reserved2[2]; // - AT91_REG TDES_ODATAxR[2]; // Output Data x Register - AT91_REG Reserved3[2]; // - AT91_REG TDES_IVxR[2]; // Initialization Vector x Register - AT91_REG Reserved4[37]; // - AT91_REG TDES_VR; // TDES Version Register - AT91_REG TDES_RPR; // Receive Pointer Register - AT91_REG TDES_RCR; // Receive Counter Register - AT91_REG TDES_TPR; // Transmit Pointer Register - AT91_REG TDES_TCR; // Transmit Counter Register - AT91_REG TDES_RNPR; // Receive Next Pointer Register - AT91_REG TDES_RNCR; // Receive Next Counter Register - AT91_REG TDES_TNPR; // Transmit Next Pointer Register - AT91_REG TDES_TNCR; // Transmit Next Counter Register - AT91_REG TDES_PTCR; // PDC Transfer Control Register - AT91_REG TDES_PTSR; // PDC Transfer Status Register -} AT91S_TDES, *AT91PS_TDES; - -// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- -#define AT91C_TDES_START ((unsigned int) 0x1 << 0) // (TDES) Starts Processing -#define AT91C_TDES_SWRST ((unsigned int) 0x1 << 8) // (TDES) Software Reset -// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- -#define AT91C_TDES_CIPHER ((unsigned int) 0x1 << 0) // (TDES) Processing Mode -#define AT91C_TDES_TDESMOD ((unsigned int) 0x1 << 1) // (TDES) Single or Triple DES Mode -#define AT91C_TDES_KEYMOD ((unsigned int) 0x1 << 4) // (TDES) Key Mode -#define AT91C_TDES_SMOD ((unsigned int) 0x3 << 8) // (TDES) Start Mode -#define AT91C_TDES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. -#define AT91C_TDES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). -#define AT91C_TDES_SMOD_PDC ((unsigned int) 0x2 << 8) // (TDES) PDC Mode (cf datasheet). -#define AT91C_TDES_OPMOD ((unsigned int) 0x3 << 12) // (TDES) Operation Mode -#define AT91C_TDES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode. -#define AT91C_TDES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode. -#define AT91C_TDES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode. -#define AT91C_TDES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode. -#define AT91C_TDES_LOD ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode -#define AT91C_TDES_CFBS ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size -#define AT91C_TDES_CFBS_64_BIT ((unsigned int) 0x0 << 16) // (TDES) 64-bit. -#define AT91C_TDES_CFBS_32_BIT ((unsigned int) 0x1 << 16) // (TDES) 32-bit. -#define AT91C_TDES_CFBS_16_BIT ((unsigned int) 0x2 << 16) // (TDES) 16-bit. -#define AT91C_TDES_CFBS_8_BIT ((unsigned int) 0x3 << 16) // (TDES) 8-bit. -// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- -#define AT91C_TDES_DATRDY ((unsigned int) 0x1 << 0) // (TDES) DATRDY -#define AT91C_TDES_ENDRX ((unsigned int) 0x1 << 1) // (TDES) PDC Read Buffer End -#define AT91C_TDES_ENDTX ((unsigned int) 0x1 << 2) // (TDES) PDC Write Buffer End -#define AT91C_TDES_RXBUFF ((unsigned int) 0x1 << 3) // (TDES) PDC Read Buffer Full -#define AT91C_TDES_TXBUFE ((unsigned int) 0x1 << 4) // (TDES) PDC Write Buffer Empty -#define AT91C_TDES_URAD ((unsigned int) 0x1 << 8) // (TDES) Unspecified Register Access Detection -// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- -// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- -// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- -#define AT91C_TDES_URAT ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status -#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode. -#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing. -#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing. -#define AT91C_TDES_URAT_WO_REG_READ ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access. - -// ***************************************************************************** -// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 -// ***************************************************************************** -// ========== Register definition for SYS peripheral ========== -// ========== Register definition for AIC peripheral ========== -#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register -#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register -#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register -#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) -#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register -#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register -#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register -#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register -#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register -#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register -#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register -#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register -#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register -#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register -#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register -#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register -#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register -#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register -// ========== Register definition for PDC_DBGU peripheral ========== -#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register -#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register -#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register -#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register -#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register -#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register -#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register -#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register -#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register -#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register -// ========== Register definition for DBGU peripheral ========== -#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register -#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register -#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register -#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register -#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register -#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register -#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register -#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register -#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register -#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register -#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register -#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register -// ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register -#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register -#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register -#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register -#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register -#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register -#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register -#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register -#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register -#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register -#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register -#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register -#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register -// ========== Register definition for PIOB peripheral ========== -#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register -#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register -#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register -#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register -#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register -#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register -#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register -#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register -#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register -#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register -#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register -#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register -#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register -#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register -#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register -#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register -#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr -#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register -#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register -#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register -#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register -#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register -#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register -#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register -#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register -#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register -#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register -#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register -#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register -// ========== Register definition for CKGR peripheral ========== -#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register -#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register -#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register -// ========== Register definition for PMC peripheral ========== -#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register -#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register -#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register -#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register -#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register -#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register -#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register -#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register -#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register -#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register -#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register -#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register -#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register -#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register -#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register -// ========== Register definition for RSTC peripheral ========== -#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register -#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register -#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register -// ========== Register definition for RTTC peripheral ========== -#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register -#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register -#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register -#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register -// ========== Register definition for PITC peripheral ========== -#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register -#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register -#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register -#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register -// ========== Register definition for WDTC peripheral ========== -#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register -#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register -#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register -// ========== Register definition for VREG peripheral ========== -#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register -// ========== Register definition for MC peripheral ========== -#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register -#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register -#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register -#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register -#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register -#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register -// ========== Register definition for PDC_SPI1 peripheral ========== -#define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register -#define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register -#define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register -#define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register -#define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register -#define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register -#define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register -#define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register -#define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register -#define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register -// ========== Register definition for SPI1 peripheral ========== -#define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register -#define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register -#define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register -#define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register -#define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register -#define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register -#define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register -#define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register -#define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register -// ========== Register definition for PDC_SPI0 peripheral ========== -#define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register -#define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register -#define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register -#define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register -#define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register -#define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register -#define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register -#define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register -#define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register -#define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register -// ========== Register definition for SPI0 peripheral ========== -#define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register -#define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register -#define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register -#define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register -#define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register -#define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register -#define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register -#define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register -#define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register -// ========== Register definition for PDC_US1 peripheral ========== -#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register -#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register -#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register -#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register -#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register -#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register -#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register -#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register -#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register -#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register -// ========== Register definition for US1 peripheral ========== -#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register -#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register -#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register -#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register -#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register -#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register -#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register -#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register -#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register -#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register -#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register -#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register -#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register -#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register -// ========== Register definition for PDC_US0 peripheral ========== -#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register -#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register -#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register -#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register -#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register -#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register -#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register -#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register -#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register -#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register -// ========== Register definition for US0 peripheral ========== -#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register -#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register -#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register -#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register -#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register -#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register -#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register -#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register -#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register -#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register -#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register -#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register -#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register -#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register -// ========== Register definition for PDC_SSC peripheral ========== -#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register -#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register -#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register -#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register -#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register -#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register -#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register -#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register -#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register -#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register -// ========== Register definition for SSC peripheral ========== -#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register -#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register -#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register -#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register -#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register -#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister -#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register -#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register -#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register -#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register -#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register -#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register -#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register -#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register -// ========== Register definition for TWI peripheral ========== -#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register -#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register -#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register -#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register -#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register -#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register -#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register -#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register -#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register -#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register -// ========== Register definition for PWMC_CH3 peripheral ========== -#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register -#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved -#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register -#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register -#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register -#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register -// ========== Register definition for PWMC_CH2 peripheral ========== -#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved -#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register -#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register -#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register -#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register -#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH1 peripheral ========== -#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved -#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register -#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register -#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register -#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register -#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register -// ========== Register definition for PWMC_CH0 peripheral ========== -#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved -#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register -#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register -#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register -#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register -#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register -// ========== Register definition for PWMC peripheral ========== -#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register -#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register -#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register -#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register -#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register -#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register -#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register -#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register -#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register -// ========== Register definition for UDP peripheral ========== -#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register -#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register -#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register -#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register -#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register -#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register -#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register -#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register -#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register -#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register -#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register -#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register -// ========== Register definition for TC0 peripheral ========== -#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register -#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C -#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B -#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register -#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register -#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A -#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register -#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value -#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register -// ========== Register definition for TC1 peripheral ========== -#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B -#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register -#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register -#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register -#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register -#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A -#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C -#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register -#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value -// ========== Register definition for TC2 peripheral ========== -#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register -#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value -#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A -#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B -#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register -#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register -#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C -#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register -#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register -// ========== Register definition for TCB peripheral ========== -#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register -#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register -// ========== Register definition for CAN_MB0 peripheral ========== -#define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register -#define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register -#define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register -#define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register -#define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register -#define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register -#define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register -#define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register -// ========== Register definition for CAN_MB1 peripheral ========== -#define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register -#define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register -#define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register -#define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register -#define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register -#define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register -#define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register -#define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register -// ========== Register definition for CAN_MB2 peripheral ========== -#define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register -#define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register -#define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register -#define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register -#define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register -#define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register -#define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register -#define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register -// ========== Register definition for CAN_MB3 peripheral ========== -#define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register -#define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register -#define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register -#define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register -#define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register -#define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register -#define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register -#define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register -// ========== Register definition for CAN_MB4 peripheral ========== -#define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register -#define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register -#define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register -#define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register -#define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register -#define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register -#define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register -#define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register -// ========== Register definition for CAN_MB5 peripheral ========== -#define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register -#define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register -#define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register -#define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register -#define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register -#define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register -#define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register -#define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register -// ========== Register definition for CAN_MB6 peripheral ========== -#define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register -#define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register -#define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register -#define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register -#define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register -#define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register -#define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register -#define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register -// ========== Register definition for CAN_MB7 peripheral ========== -#define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register -#define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register -#define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register -#define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register -#define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register -#define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register -#define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register -#define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register -// ========== Register definition for CAN peripheral ========== -#define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register -#define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register -#define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register -#define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register -#define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register -#define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register -#define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register -#define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register -#define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register -#define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register -#define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register -#define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register -// ========== Register definition for EMAC peripheral ========== -#define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register -#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes -#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes -#define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register -#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register -#define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register -#define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register -#define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register -#define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register -#define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register -#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes -#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register -#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes -#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register -#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register -#define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register -#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register -#define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register -#define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] -#define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer -#define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register -#define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register -#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes -#define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register -#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register -#define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register -#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer -#define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register -#define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register -#define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32] -#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register -#define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register -#define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register -#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register -#define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register -#define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register -#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register -#define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register -#define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register -#define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register -#define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register -#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes -#define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register -#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register -#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes -#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register -#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes -#define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register -#define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register -// ========== Register definition for PDC_ADC peripheral ========== -#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register -#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register -#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register -#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register -#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register -#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register -#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register -#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register -#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register -#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register -// ========== Register definition for ADC peripheral ========== -#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 -#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 -#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 -#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 -#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register -#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register -#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 -#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 -#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register -#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register -#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register -#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 -#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 -#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register -#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register -#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register -#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register -#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register -// ========== Register definition for PDC_AES peripheral ========== -#define AT91C_AES_TPR ((AT91_REG *) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register -#define AT91C_AES_PTCR ((AT91_REG *) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register -#define AT91C_AES_RNPR ((AT91_REG *) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register -#define AT91C_AES_TNCR ((AT91_REG *) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register -#define AT91C_AES_TCR ((AT91_REG *) 0xFFFA410C) // (PDC_AES) Transmit Counter Register -#define AT91C_AES_RCR ((AT91_REG *) 0xFFFA4104) // (PDC_AES) Receive Counter Register -#define AT91C_AES_RNCR ((AT91_REG *) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register -#define AT91C_AES_TNPR ((AT91_REG *) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register -#define AT91C_AES_RPR ((AT91_REG *) 0xFFFA4100) // (PDC_AES) Receive Pointer Register -#define AT91C_AES_PTSR ((AT91_REG *) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register -// ========== Register definition for AES peripheral ========== -#define AT91C_AES_IVxR ((AT91_REG *) 0xFFFA4060) // (AES) Initialization Vector x Register -#define AT91C_AES_MR ((AT91_REG *) 0xFFFA4004) // (AES) Mode Register -#define AT91C_AES_VR ((AT91_REG *) 0xFFFA40FC) // (AES) AES Version Register -#define AT91C_AES_ODATAxR ((AT91_REG *) 0xFFFA4050) // (AES) Output Data x Register -#define AT91C_AES_IDATAxR ((AT91_REG *) 0xFFFA4040) // (AES) Input Data x Register -#define AT91C_AES_CR ((AT91_REG *) 0xFFFA4000) // (AES) Control Register -#define AT91C_AES_IDR ((AT91_REG *) 0xFFFA4014) // (AES) Interrupt Disable Register -#define AT91C_AES_IMR ((AT91_REG *) 0xFFFA4018) // (AES) Interrupt Mask Register -#define AT91C_AES_IER ((AT91_REG *) 0xFFFA4010) // (AES) Interrupt Enable Register -#define AT91C_AES_KEYWxR ((AT91_REG *) 0xFFFA4020) // (AES) Key Word x Register -#define AT91C_AES_ISR ((AT91_REG *) 0xFFFA401C) // (AES) Interrupt Status Register -// ========== Register definition for PDC_TDES peripheral ========== -#define AT91C_TDES_RNCR ((AT91_REG *) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register -#define AT91C_TDES_TCR ((AT91_REG *) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register -#define AT91C_TDES_RCR ((AT91_REG *) 0xFFFA8104) // (PDC_TDES) Receive Counter Register -#define AT91C_TDES_TNPR ((AT91_REG *) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register -#define AT91C_TDES_RNPR ((AT91_REG *) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register -#define AT91C_TDES_RPR ((AT91_REG *) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register -#define AT91C_TDES_TNCR ((AT91_REG *) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register -#define AT91C_TDES_TPR ((AT91_REG *) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register -#define AT91C_TDES_PTSR ((AT91_REG *) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register -#define AT91C_TDES_PTCR ((AT91_REG *) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register -// ========== Register definition for TDES peripheral ========== -#define AT91C_TDES_KEY2WxR ((AT91_REG *) 0xFFFA8028) // (TDES) Key 2 Word x Register -#define AT91C_TDES_KEY3WxR ((AT91_REG *) 0xFFFA8030) // (TDES) Key 3 Word x Register -#define AT91C_TDES_IDR ((AT91_REG *) 0xFFFA8014) // (TDES) Interrupt Disable Register -#define AT91C_TDES_VR ((AT91_REG *) 0xFFFA80FC) // (TDES) TDES Version Register -#define AT91C_TDES_IVxR ((AT91_REG *) 0xFFFA8060) // (TDES) Initialization Vector x Register -#define AT91C_TDES_ODATAxR ((AT91_REG *) 0xFFFA8050) // (TDES) Output Data x Register -#define AT91C_TDES_IMR ((AT91_REG *) 0xFFFA8018) // (TDES) Interrupt Mask Register -#define AT91C_TDES_MR ((AT91_REG *) 0xFFFA8004) // (TDES) Mode Register -#define AT91C_TDES_CR ((AT91_REG *) 0xFFFA8000) // (TDES) Control Register -#define AT91C_TDES_IER ((AT91_REG *) 0xFFFA8010) // (TDES) Interrupt Enable Register -#define AT91C_TDES_ISR ((AT91_REG *) 0xFFFA801C) // (TDES) Interrupt Status Register -#define AT91C_TDES_IDATAxR ((AT91_REG *) 0xFFFA8040) // (TDES) Input Data x Register -#define AT91C_TDES_KEY1WxR ((AT91_REG *) 0xFFFA8020) // (TDES) Key 1 Word x Register - -// ***************************************************************************** -// PIO DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 -#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data -#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 -#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data -#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 -#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data -#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 -#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock -#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 -#define AT91C_PA12_NPCS00 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 -#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 -#define AT91C_PA13_NPCS01 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 -#define AT91C_PA14_NPCS02 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1 -#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 -#define AT91C_PA15_NPCS03 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input -#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 -#define AT91C_PA16_MISO0 ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave -#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 -#define AT91C_PA17_MOSI0 ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave -#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 -#define AT91C_PA18_SPCK0 ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock -#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 -#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive -#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 -#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock -#define AT91C_PA2_NPCS11 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 -#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit -#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 -#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync -#define AT91C_PA21_NPCS10 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 -#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 -#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock -#define AT91C_PA22_SPCK1 ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock -#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 -#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data -#define AT91C_PA23_MOSI1 ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave -#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 -#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data -#define AT91C_PA24_MISO1 ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave -#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 -#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock -#define AT91C_PA25_NPCS11 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 -#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync -#define AT91C_PA26_NPCS12 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 -#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data -#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3 -#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 -#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data -#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 -#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input -#define AT91C_PA29_NPCS13 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 -#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send -#define AT91C_PA3_NPCS12 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 -#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0 -#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 -#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send -#define AT91C_PA4_NPCS13 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 -#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data -#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 -#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data -#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 -#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock -#define AT91C_PA7_NPCS01 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 -#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send -#define AT91C_PA8_NPCS02 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 -#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send -#define AT91C_PA9_NPCS03 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0 -#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock -#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1 -#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable -#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10 -#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 -#define AT91C_PB10_NPCS11 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11 -#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 -#define AT91C_PB11_NPCS12 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12 -#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error -#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input -#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13 -#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 -#define AT91C_PB13_NPCS01 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14 -#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 -#define AT91C_PB14_NPCS02 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15 -#define AT91C_PB15_ERXDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid -#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16 -#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected -#define AT91C_PB16_NPCS13 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17 -#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock -#define AT91C_PB17_NPCS03 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18 -#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec -#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger -#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19 -#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0 -#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input -#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2 -#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 -#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20 -#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1 -#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21 -#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2 -#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22 -#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3 -#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23 -#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A -#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect -#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24 -#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B -#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready -#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25 -#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A -#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready -#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26 -#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B -#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator -#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27 -#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A -#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0 -#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28 -#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B -#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1 -#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29 -#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1 -#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2 -#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3 -#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 -#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30 -#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2 -#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3 -#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4 -#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid -#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5 -#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 -#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6 -#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 -#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7 -#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error -#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8 -#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock -#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9 -#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output - -// ***************************************************************************** -// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) -#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral -#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A -#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B -#define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0 -#define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1 -#define AT91C_ID_US0 ((unsigned int) 6) // USART 0 -#define AT91C_ID_US1 ((unsigned int) 7) // USART 1 -#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller -#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface -#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller -#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port -#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0 -#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1 -#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2 -#define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller -#define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC -#define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter -#define AT91C_ID_AES ((unsigned int) 18) // Advanced Encryption Standard 128-bit -#define AT91C_ID_TDES ((unsigned int) 19) // Triple Data Encryption Standard -#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved -#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved -#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved -#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved -#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved -#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved -#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved -#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved -#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved -#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved -#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0) -#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1) - -// ***************************************************************************** -// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address -#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address -#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address -#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address -#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address -#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address -#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address -#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address -#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address -#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address -#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address -#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address -#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address -#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address -#define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address -#define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address -#define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address -#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address -#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address -#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address -#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address -#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address -#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address -#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address -#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address -#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address -#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address -#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address -#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address -#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address -#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address -#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address -#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address -#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address -#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address -#define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address -#define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address -#define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address -#define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address -#define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address -#define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address -#define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address -#define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address -#define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address -#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address -#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address -#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address -#define AT91C_BASE_PDC_AES ((AT91PS_PDC) 0xFFFA4100) // (PDC_AES) Base Address -#define AT91C_BASE_AES ((AT91PS_AES) 0xFFFA4000) // (AES) Base Address -#define AT91C_BASE_PDC_TDES ((AT91PS_PDC) 0xFFFA8100) // (PDC_TDES) Base Address -#define AT91C_BASE_TDES ((AT91PS_TDES) 0xFFFA8000) // (TDES) Base Address - -// ***************************************************************************** -// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address -#define AT91C_ISRAM_SIZE ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte) -#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address -#define AT91C_IFLASH_SIZE ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte) - -#endif diff --git a/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h b/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h deleted file mode 100644 index 5b8dfe811..000000000 --- a/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h +++ /dev/null @@ -1,2446 +0,0 @@ -// ---------------------------------------------------------------------------- -// ATMEL Microcontroller Software Support - ROUSSET - -// ---------------------------------------------------------------------------- -// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// ---------------------------------------------------------------------------- -// File Name : AT91SAM7X256.h -// Object : AT91SAM7X256 definitions -// Generated : AT91 SW Application Group 05/20/2005 (16:22:29) -// -// CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005// -// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// -// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// -// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// -// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// -// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// -// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// -// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// -// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// -// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// -// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// -// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// -// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// -// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// -// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// -// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// -// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// -// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// -// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// -// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// -// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// -// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// -// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// -// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// -// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// -// ---------------------------------------------------------------------------- - -// Hardware register definition - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Peripherals -// ***************************************************************************** - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// ***************************************************************************** -// *** Register offset in AT91S_AIC structure *** -#define AIC_SMR ( 0) // Source Mode Register -#define AIC_SVR (128) // Source Vector Register -#define AIC_IVR (256) // IRQ Vector Register -#define AIC_FVR (260) // FIQ Vector Register -#define AIC_ISR (264) // Interrupt Status Register -#define AIC_IPR (268) // Interrupt Pending Register -#define AIC_IMR (272) // Interrupt Mask Register -#define AIC_CISR (276) // Core Interrupt Status Register -#define AIC_IECR (288) // Interrupt Enable Command Register -#define AIC_IDCR (292) // Interrupt Disable Command Register -#define AIC_ICCR (296) // Interrupt Clear Command Register -#define AIC_ISCR (300) // Interrupt Set Command Register -#define AIC_EOICR (304) // End of Interrupt Command Register -#define AIC_SPU (308) // Spurious Vector Register -#define AIC_DCR (312) // Debug Control Register (Protect) -#define AIC_FFER (320) // Fast Forcing Enable Register -#define AIC_FFDR (324) // Fast Forcing Disable Register -#define AIC_FFSR (328) // Fast Forcing Status Register -// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level -#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level -#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level -#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type -#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive -#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered -#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered -#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered -// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status -#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status -// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode -#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Peripheral DMA Controller -// ***************************************************************************** -// *** Register offset in AT91S_PDC structure *** -#define PDC_RPR ( 0) // Receive Pointer Register -#define PDC_RCR ( 4) // Receive Counter Register -#define PDC_TPR ( 8) // Transmit Pointer Register -#define PDC_TCR (12) // Transmit Counter Register -#define PDC_RNPR (16) // Receive Next Pointer Register -#define PDC_RNCR (20) // Receive Next Counter Register -#define PDC_TNPR (24) // Transmit Next Pointer Register -#define PDC_TNCR (28) // Transmit Next Counter Register -#define PDC_PTCR (32) // PDC Transfer Control Register -#define PDC_PTSR (36) // PDC Transfer Status Register -// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable -#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable -#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable -#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable -// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Debug Unit -// ***************************************************************************** -// *** Register offset in AT91S_DBGU structure *** -#define DBGU_CR ( 0) // Control Register -#define DBGU_MR ( 4) // Mode Register -#define DBGU_IER ( 8) // Interrupt Enable Register -#define DBGU_IDR (12) // Interrupt Disable Register -#define DBGU_IMR (16) // Interrupt Mask Register -#define DBGU_CSR (20) // Channel Status Register -#define DBGU_RHR (24) // Receiver Holding Register -#define DBGU_THR (28) // Transmitter Holding Register -#define DBGU_BRGR (32) // Baud Rate Generator Register -#define DBGU_CIDR (64) // Chip ID Register -#define DBGU_EXID (68) // Chip ID Extension Register -#define DBGU_FNTR (72) // Force NTRST Register -#define DBGU_RPR (256) // Receive Pointer Register -#define DBGU_RCR (260) // Receive Counter Register -#define DBGU_TPR (264) // Transmit Pointer Register -#define DBGU_TCR (268) // Transmit Counter Register -#define DBGU_RNPR (272) // Receive Next Pointer Register -#define DBGU_RNCR (276) // Receive Next Counter Register -#define DBGU_TNPR (280) // Transmit Next Pointer Register -#define DBGU_TNCR (284) // Transmit Next Counter Register -#define DBGU_PTCR (288) // PDC Transfer Control Register -#define DBGU_PTSR (292) // PDC Transfer Status Register -// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver -#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter -#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable -#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable -#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable -#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable -#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits -// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type -#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity -#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity -#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) -#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) -#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity -#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode -#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode -#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt -#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt -#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt -#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt -#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt -#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt -#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt -#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt -#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt -#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt -#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt -#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt -// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// ***************************************************************************** -// *** Register offset in AT91S_PIO structure *** -#define PIO_PER ( 0) // PIO Enable Register -#define PIO_PDR ( 4) // PIO Disable Register -#define PIO_PSR ( 8) // PIO Status Register -#define PIO_OER (16) // Output Enable Register -#define PIO_ODR (20) // Output Disable Registerr -#define PIO_OSR (24) // Output Status Register -#define PIO_IFER (32) // Input Filter Enable Register -#define PIO_IFDR (36) // Input Filter Disable Register -#define PIO_IFSR (40) // Input Filter Status Register -#define PIO_SODR (48) // Set Output Data Register -#define PIO_CODR (52) // Clear Output Data Register -#define PIO_ODSR (56) // Output Data Status Register -#define PIO_PDSR (60) // Pin Data Status Register -#define PIO_IER (64) // Interrupt Enable Register -#define PIO_IDR (68) // Interrupt Disable Register -#define PIO_IMR (72) // Interrupt Mask Register -#define PIO_ISR (76) // Interrupt Status Register -#define PIO_MDER (80) // Multi-driver Enable Register -#define PIO_MDDR (84) // Multi-driver Disable Register -#define PIO_MDSR (88) // Multi-driver Status Register -#define PIO_PPUDR (96) // Pull-up Disable Register -#define PIO_PPUER (100) // Pull-up Enable Register -#define PIO_PPUSR (104) // Pull-up Status Register -#define PIO_ASR (112) // Select A Register -#define PIO_BSR (116) // Select B Register -#define PIO_ABSR (120) // AB Select Status Register -#define PIO_OWER (160) // Output Write Enable Register -#define PIO_OWDR (164) // Output Write Disable Register -#define PIO_OWSR (168) // Output Write Status Register - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Clock Generator Controler -// ***************************************************************************** -// *** Register offset in AT91S_CKGR structure *** -#define CKGR_MOR ( 0) // Main Oscillator Register -#define CKGR_MCFR ( 4) // Main Clock Frequency Register -#define CKGR_PLLR (12) // PLL Register -// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable -#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass -#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time -// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency -#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready -// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- -#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter -#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range -#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier -#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks -#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output -#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 -#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Power Management Controler -// ***************************************************************************** -// *** Register offset in AT91S_PMC structure *** -#define PMC_SCER ( 0) // System Clock Enable Register -#define PMC_SCDR ( 4) // System Clock Disable Register -#define PMC_SCSR ( 8) // System Clock Status Register -#define PMC_PCER (16) // Peripheral Clock Enable Register -#define PMC_PCDR (20) // Peripheral Clock Disable Register -#define PMC_PCSR (24) // Peripheral Clock Status Register -#define PMC_MOR (32) // Main Oscillator Register -#define PMC_MCFR (36) // Main Clock Frequency Register -#define PMC_PLLR (44) // PLL Register -#define PMC_MCKR (48) // Master Clock Register -#define PMC_PCKR (64) // Programmable Clock Register -#define PMC_IER (96) // Interrupt Enable Register -#define PMC_IDR (100) // Interrupt Disable Register -#define PMC_SR (104) // Status Register -#define PMC_IMR (108) // Interrupt Mask Register -// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock -#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock -#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output -// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- -// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- -// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- -// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection -#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected -#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected -#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected -#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler -#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock -#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 -#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 -#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 -#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 -#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 -#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 -// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask -#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask -#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask -// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Reset Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_RSTC structure *** -#define RSTC_RCR ( 0) // Reset Control Register -#define RSTC_RSR ( 4) // Reset Status Register -#define RSTC_RMR ( 8) // Reset Mode Register -// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- -#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset -#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset -#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset -#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password -// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- -#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status -#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status -#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type -#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. -#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. -#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. -#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured. -#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level -#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. -// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- -#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable -#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable -#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Enable -#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_RTTC structure *** -#define RTTC_RTMR ( 0) // Real-time Mode Register -#define RTTC_RTAR ( 4) // Real-time Alarm Register -#define RTTC_RTVR ( 8) // Real-time Value Register -#define RTTC_RTSR (12) // Real-time Status Register -// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- -#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value -#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable -#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable -#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart -// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- -#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value -// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- -#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value -// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- -#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status -#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_PITC structure *** -#define PITC_PIMR ( 0) // Period Interval Mode Register -#define PITC_PISR ( 4) // Period Interval Status Register -#define PITC_PIVR ( 8) // Period Interval Value Register -#define PITC_PIIR (12) // Period Interval Image Register -// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- -#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value -#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled -#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable -// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- -#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status -// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- -#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value -#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter -// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_WDTC structure *** -#define WDTC_WDCR ( 0) // Watchdog Control Register -#define WDTC_WDMR ( 4) // Watchdog Mode Register -#define WDTC_WDSR ( 8) // Watchdog Status Register -// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- -#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart -#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password -// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- -#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable -#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable -#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable -#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value -#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt -#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt -// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- -#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow -#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_VREG structure *** -#define VREG_MR ( 0) // Voltage Regulator Mode Register -// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- -#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Memory Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_MC structure *** -#define MC_RCR ( 0) // MC Remap Control Register -#define MC_ASR ( 4) // MC Abort Status Register -#define MC_AASR ( 8) // MC Abort Address Status Register -#define MC_FMR (96) // MC Flash Mode Register -#define MC_FCR (100) // MC Flash Command Register -#define MC_FSR (104) // MC Flash Status Register -// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit -// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status -#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status -#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status -#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte -#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word -#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word -#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status -#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read -#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write -#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch -#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source -#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source -#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source -#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source -// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- -#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready -#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error -#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error -#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming -#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State -#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations -#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations -#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations -#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations -#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number -// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- -#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command -#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN. -#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. -#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. -#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits. -#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits. -#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit. -#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number -#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key -// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- -#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status -#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status -#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status -#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status -#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status -#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status -#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status -#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status -#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status -#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status -#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status -#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status -#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status -#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status -#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status -#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status -#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status -#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status -#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status -#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status -#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status -#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status -#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Serial Parallel Interface -// ***************************************************************************** -// *** Register offset in AT91S_SPI structure *** -#define SPI_CR ( 0) // Control Register -#define SPI_MR ( 4) // Mode Register -#define SPI_RDR ( 8) // Receive Data Register -#define SPI_TDR (12) // Transmit Data Register -#define SPI_SR (16) // Status Register -#define SPI_IER (20) // Interrupt Enable Register -#define SPI_IDR (24) // Interrupt Disable Register -#define SPI_IMR (28) // Interrupt Mask Register -#define SPI_CSR (48) // Chip Select Register -#define SPI_RPR (256) // Receive Pointer Register -#define SPI_RCR (260) // Receive Counter Register -#define SPI_TPR (264) // Transmit Pointer Register -#define SPI_TCR (268) // Transmit Counter Register -#define SPI_RNPR (272) // Receive Next Pointer Register -#define SPI_RNCR (276) // Receive Next Counter Register -#define SPI_TNPR (280) // Transmit Next Pointer Register -#define SPI_TNCR (284) // Transmit Next Counter Register -#define SPI_PTCR (288) // PDC Transfer Control Register -#define SPI_PTSR (292) // PDC Transfer Status Register -// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable -#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable -#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset -#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer -// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode -#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select -#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select -#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select -#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode -#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection -#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection -#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection -#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select -#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects -// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data -#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data -#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full -#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty -#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error -#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status -#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer -#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer -#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt -#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt -#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt -#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt -#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status -// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity -#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase -#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer -#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer -#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer -#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer -#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer -#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer -#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer -#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer -#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer -#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer -#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer -#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK -#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Usart -// ***************************************************************************** -// *** Register offset in AT91S_USART structure *** -#define US_CR ( 0) // Control Register -#define US_MR ( 4) // Mode Register -#define US_IER ( 8) // Interrupt Enable Register -#define US_IDR (12) // Interrupt Disable Register -#define US_IMR (16) // Interrupt Mask Register -#define US_CSR (20) // Channel Status Register -#define US_RHR (24) // Receiver Holding Register -#define US_THR (28) // Transmitter Holding Register -#define US_BRGR (32) // Baud Rate Generator Register -#define US_RTOR (36) // Receiver Time-out Register -#define US_TTGR (40) // Transmitter Time-guard Register -#define US_FIDI (64) // FI_DI_Ratio Register -#define US_NER (68) // Nb Errors Register -#define US_IF (76) // IRDA_FILTER Register -#define US_RPR (256) // Receive Pointer Register -#define US_RCR (260) // Receive Counter Register -#define US_TPR (264) // Transmit Pointer Register -#define US_TCR (268) // Transmit Counter Register -#define US_RNPR (272) // Receive Next Pointer Register -#define US_RNCR (276) // Receive Next Counter Register -#define US_TNPR (280) // Transmit Next Pointer Register -#define US_TNCR (284) // Transmit Next Counter Register -#define US_PTCR (288) // PDC Transfer Control Register -#define US_PTSR (292) // PDC Transfer Status Register -// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break -#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break -#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out -#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address -#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations -#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge -#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out -#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable -#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable -#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable -#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable -// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode -#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal -#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 -#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking -#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem -#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 -#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 -#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA -#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking -#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock -#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 -#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) -#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) -#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits -#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits -#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits -#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits -#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select -#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits -#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit -#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits -#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order -#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length -#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select -#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode -#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge -#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK -#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions -#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter -// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break -#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out -#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached -#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge -#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag -#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag -#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag -#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag -// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input -#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input -#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input -#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_SSC structure *** -#define SSC_CR ( 0) // Control Register -#define SSC_CMR ( 4) // Clock Mode Register -#define SSC_RCMR (16) // Receive Clock ModeRegister -#define SSC_RFMR (20) // Receive Frame Mode Register -#define SSC_TCMR (24) // Transmit Clock Mode Register -#define SSC_TFMR (28) // Transmit Frame Mode Register -#define SSC_RHR (32) // Receive Holding Register -#define SSC_THR (36) // Transmit Holding Register -#define SSC_RSHR (48) // Receive Sync Holding Register -#define SSC_TSHR (52) // Transmit Sync Holding Register -#define SSC_SR (64) // Status Register -#define SSC_IER (68) // Interrupt Enable Register -#define SSC_IDR (72) // Interrupt Disable Register -#define SSC_IMR (76) // Interrupt Mask Register -#define SSC_RPR (256) // Receive Pointer Register -#define SSC_RCR (260) // Receive Counter Register -#define SSC_TPR (264) // Transmit Pointer Register -#define SSC_TCR (268) // Transmit Counter Register -#define SSC_RNPR (272) // Receive Next Pointer Register -#define SSC_RNCR (276) // Receive Next Counter Register -#define SSC_TNPR (280) // Transmit Next Pointer Register -#define SSC_TNCR (284) // Transmit Next Counter Register -#define SSC_PTCR (288) // PDC Transfer Control Register -#define SSC_PTSR (292) // PDC Transfer Status Register -// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable -#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable -#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable -#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable -#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset -// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection -#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock -#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal -#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin -#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection -#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output -#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion -#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection -#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start -#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input -#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input -#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input -#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input -#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input -#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input -#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 -#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay -#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection -// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length -#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode -#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First -#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame -#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length -#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection -#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection -// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value -#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable -// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready -#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty -#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission -#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty -#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready -#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun -#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception -#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full -#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync -#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync -#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable -#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable -// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Two-wire Interface -// ***************************************************************************** -// *** Register offset in AT91S_TWI structure *** -#define TWI_CR ( 0) // Control Register -#define TWI_MMR ( 4) // Master Mode Register -#define TWI_IADR (12) // Internal Address Register -#define TWI_CWGR (16) // Clock Waveform Generator Register -#define TWI_SR (32) // Status Register -#define TWI_IER (36) // Interrupt Enable Register -#define TWI_IDR (40) // Interrupt Disable Register -#define TWI_IMR (44) // Interrupt Mask Register -#define TWI_RHR (48) // Receive Holding Register -#define TWI_THR (52) // Transmit Holding Register -// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition -#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition -#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled -#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled -#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset -// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size -#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address -#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address -#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address -#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address -#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction -#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address -// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider -#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider -#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider -// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed -#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY -#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY -#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error -#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error -#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged -// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR PWMC Channel Interface -// ***************************************************************************** -// *** Register offset in AT91S_PWMC_CH structure *** -#define PWMC_CMR ( 0) // Channel Mode Register -#define PWMC_CDTYR ( 4) // Channel Duty Cycle Register -#define PWMC_CPRDR ( 8) // Channel Period Register -#define PWMC_CCNTR (12) // Channel Counter Register -#define PWMC_CUPDR (16) // Channel Update Register -#define PWMC_Reserved (20) // Reserved -// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- -#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx -#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) -#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment -#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity -#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period -// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- -#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle -// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- -#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period -// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- -#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter -// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- -#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_PWMC structure *** -#define PWMC_MR ( 0) // PWMC Mode Register -#define PWMC_ENA ( 4) // PWMC Enable Register -#define PWMC_DIS ( 8) // PWMC Disable Register -#define PWMC_SR (12) // PWMC Status Register -#define PWMC_IER (16) // PWMC Interrupt Enable Register -#define PWMC_IDR (20) // PWMC Interrupt Disable Register -#define PWMC_IMR (24) // PWMC Interrupt Mask Register -#define PWMC_ISR (28) // PWMC Interrupt Status Register -#define PWMC_VR (252) // PWMC Version Register -#define PWMC_CH (512) // PWMC Channel -// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- -#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. -#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A -#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) -#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. -#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B -#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) -// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- -#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 -#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 -#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 -#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 -// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- -// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- -// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- -// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- -// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- -// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Device Interface -// ***************************************************************************** -// *** Register offset in AT91S_UDP structure *** -#define UDP_NUM ( 0) // Frame Number Register -#define UDP_GLBSTATE ( 4) // Global State Register -#define UDP_FADDR ( 8) // Function Address Register -#define UDP_IER (16) // Interrupt Enable Register -#define UDP_IDR (20) // Interrupt Disable Register -#define UDP_IMR (24) // Interrupt Mask Register -#define UDP_ISR (28) // Interrupt Status Register -#define UDP_ICR (32) // Interrupt Clear Register -#define UDP_RSTEP (40) // Reset Endpoint Register -#define UDP_CSR (48) // Endpoint Control and Status Register -#define UDP_FDR (80) // Endpoint FIFO Data Register -#define UDP_TXVC (116) // Transceiver Control Register -// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats -#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error -#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK -// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable -#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured -#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume -#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host -#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable -// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value -#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable -// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt -#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt -#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt -#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt -#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt -#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt -#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt -#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt -#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt -// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt -// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 -#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 -#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 -#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 -#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4 -#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5 -// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR -#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 -#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) -#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) -#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready -#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction -#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type -#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control -#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT -#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT -#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT -#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN -#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN -#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN -#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle -#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable -#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO -// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- -#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) -#define AT91C_UDP_PUON (0x1 << 9) // (UDP) Pull-up ON - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// ***************************************************************************** -// *** Register offset in AT91S_TC structure *** -#define TC_CCR ( 0) // Channel Control Register -#define TC_CMR ( 4) // Channel Mode Register (Capture Mode / Waveform Mode) -#define TC_CV (16) // Counter Value -#define TC_RA (20) // Register A -#define TC_RB (24) // Register B -#define TC_RC (28) // Register C -#define TC_SR (32) // Status Register -#define TC_IER (36) // Interrupt Enable Register -#define TC_IDR (40) // Interrupt Disable Register -#define TC_IMR (44) // Interrupt Mask Register -// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command -#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command -#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command -// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection -#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK -#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 -#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 -#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 -#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert -#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection -#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal -#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock -#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock -#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock -#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare -#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading -#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare -#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading -#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection -#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None -#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection -#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None -#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection -#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input -#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output -#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output -#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output -#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection -#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable -#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection -#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare -#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable -#define AT91C_TC_WAVE (0x1 << 15) // (TC) -#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA -#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none -#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set -#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear -#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle -#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection -#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None -#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA -#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA -#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none -#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set -#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear -#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle -#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection -#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None -#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA -#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA -#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none -#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set -#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear -#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle -#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA -#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none -#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set -#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear -#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle -#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB -#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none -#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set -#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear -#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle -#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB -#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none -#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set -#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear -#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle -#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB -#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none -#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set -#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear -#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle -#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB -#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none -#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set -#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear -#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle -// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow -#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun -#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare -#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare -#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare -#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading -#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading -#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger -#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling -#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror -#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror -// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Interface -// ***************************************************************************** -// *** Register offset in AT91S_TCB structure *** -#define TCB_TC0 ( 0) // TC Channel 0 -#define TCB_TC1 (64) // TC Channel 1 -#define TCB_TC2 (128) // TC Channel 2 -#define TCB_BCR (192) // TC Block Control Register -#define TCB_BMR (196) // TC Block Mode Register -// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command -// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection -#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 -#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 -#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection -#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 -#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 -#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection -#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 -#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface -// ***************************************************************************** -// *** Register offset in AT91S_CAN_MB structure *** -#define CAN_MB_MMR ( 0) // MailBox Mode Register -#define CAN_MB_MAM ( 4) // MailBox Acceptance Mask Register -#define CAN_MB_MID ( 8) // MailBox ID Register -#define CAN_MB_MFID (12) // MailBox Family ID Register -#define CAN_MB_MSR (16) // MailBox Status Register -#define CAN_MB_MDL (20) // MailBox Data Low Register -#define CAN_MB_MDH (24) // MailBox Data High Register -#define CAN_MB_MCR (28) // MailBox Control Register -// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- -#define AT91C_CAN_MTIMEMARK (0xFFFF << 0) // (CAN_MB) Mailbox Timemark -#define AT91C_CAN_PRIOR (0xF << 16) // (CAN_MB) Mailbox Priority -#define AT91C_CAN_MOT (0x7 << 24) // (CAN_MB) Mailbox Object Type -#define AT91C_CAN_MOT_DIS (0x0 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RX (0x1 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RXOVERWRITE (0x2 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_TX (0x3 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_CONSUMER (0x4 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_PRODUCER (0x5 << 24) // (CAN_MB) -// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- -#define AT91C_CAN_MIDvB (0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode -#define AT91C_CAN_MIDvA (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode -#define AT91C_CAN_MIDE (0x1 << 29) // (CAN_MB) Identifier Version -// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- -// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- -// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- -#define AT91C_CAN_MTIMESTAMP (0xFFFF << 0) // (CAN_MB) Timer Value -#define AT91C_CAN_MDLC (0xF << 16) // (CAN_MB) Mailbox Data Length Code -#define AT91C_CAN_MRTR (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request -#define AT91C_CAN_MABT (0x1 << 22) // (CAN_MB) Mailbox Message Abort -#define AT91C_CAN_MRDY (0x1 << 23) // (CAN_MB) Mailbox Ready -#define AT91C_CAN_MMI (0x1 << 24) // (CAN_MB) Mailbox Message Ignored -// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- -// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- -// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- -#define AT91C_CAN_MACR (0x1 << 22) // (CAN_MB) Abort Request for Mailbox -#define AT91C_CAN_MTCR (0x1 << 23) // (CAN_MB) Mailbox Transfer Command - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network Interface -// ***************************************************************************** -// *** Register offset in AT91S_CAN structure *** -#define CAN_MR ( 0) // Mode Register -#define CAN_IER ( 4) // Interrupt Enable Register -#define CAN_IDR ( 8) // Interrupt Disable Register -#define CAN_IMR (12) // Interrupt Mask Register -#define CAN_SR (16) // Status Register -#define CAN_BR (20) // Baudrate Register -#define CAN_TIM (24) // Timer Register -#define CAN_TIMESTP (28) // Time Stamp Register -#define CAN_ECR (32) // Error Counter Register -#define CAN_TCR (36) // Transfer Command Register -#define CAN_ACR (40) // Abort Command Register -#define CAN_VR (252) // Version Register -#define CAN_MB0 (512) // CAN Mailbox 0 -#define CAN_MB1 (544) // CAN Mailbox 1 -#define CAN_MB2 (576) // CAN Mailbox 2 -#define CAN_MB3 (608) // CAN Mailbox 3 -#define CAN_MB4 (640) // CAN Mailbox 4 -#define CAN_MB5 (672) // CAN Mailbox 5 -#define CAN_MB6 (704) // CAN Mailbox 6 -#define CAN_MB7 (736) // CAN Mailbox 7 -#define CAN_MB8 (768) // CAN Mailbox 8 -#define CAN_MB9 (800) // CAN Mailbox 9 -#define CAN_MB10 (832) // CAN Mailbox 10 -#define CAN_MB11 (864) // CAN Mailbox 11 -#define CAN_MB12 (896) // CAN Mailbox 12 -#define CAN_MB13 (928) // CAN Mailbox 13 -#define CAN_MB14 (960) // CAN Mailbox 14 -#define CAN_MB15 (992) // CAN Mailbox 15 -// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- -#define AT91C_CAN_CANEN (0x1 << 0) // (CAN) CAN Controller Enable -#define AT91C_CAN_LPM (0x1 << 1) // (CAN) Disable/Enable Low Power Mode -#define AT91C_CAN_ABM (0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode -#define AT91C_CAN_OVL (0x1 << 3) // (CAN) Disable/Enable Overload Frame -#define AT91C_CAN_TEOF (0x1 << 4) // (CAN) Time Stamp messages at each end of Frame -#define AT91C_CAN_TTM (0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode -#define AT91C_CAN_TIMFRZ (0x1 << 6) // (CAN) Enable Timer Freeze -#define AT91C_CAN_DRPT (0x1 << 7) // (CAN) Disable Repeat -// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- -#define AT91C_CAN_MB0 (0x1 << 0) // (CAN) Mailbox 0 Flag -#define AT91C_CAN_MB1 (0x1 << 1) // (CAN) Mailbox 1 Flag -#define AT91C_CAN_MB2 (0x1 << 2) // (CAN) Mailbox 2 Flag -#define AT91C_CAN_MB3 (0x1 << 3) // (CAN) Mailbox 3 Flag -#define AT91C_CAN_MB4 (0x1 << 4) // (CAN) Mailbox 4 Flag -#define AT91C_CAN_MB5 (0x1 << 5) // (CAN) Mailbox 5 Flag -#define AT91C_CAN_MB6 (0x1 << 6) // (CAN) Mailbox 6 Flag -#define AT91C_CAN_MB7 (0x1 << 7) // (CAN) Mailbox 7 Flag -#define AT91C_CAN_MB8 (0x1 << 8) // (CAN) Mailbox 8 Flag -#define AT91C_CAN_MB9 (0x1 << 9) // (CAN) Mailbox 9 Flag -#define AT91C_CAN_MB10 (0x1 << 10) // (CAN) Mailbox 10 Flag -#define AT91C_CAN_MB11 (0x1 << 11) // (CAN) Mailbox 11 Flag -#define AT91C_CAN_MB12 (0x1 << 12) // (CAN) Mailbox 12 Flag -#define AT91C_CAN_MB13 (0x1 << 13) // (CAN) Mailbox 13 Flag -#define AT91C_CAN_MB14 (0x1 << 14) // (CAN) Mailbox 14 Flag -#define AT91C_CAN_MB15 (0x1 << 15) // (CAN) Mailbox 15 Flag -#define AT91C_CAN_ERRA (0x1 << 16) // (CAN) Error Active Mode Flag -#define AT91C_CAN_WARN (0x1 << 17) // (CAN) Warning Limit Flag -#define AT91C_CAN_ERRP (0x1 << 18) // (CAN) Error Passive Mode Flag -#define AT91C_CAN_BOFF (0x1 << 19) // (CAN) Bus Off Mode Flag -#define AT91C_CAN_SLEEP (0x1 << 20) // (CAN) Sleep Flag -#define AT91C_CAN_WAKEUP (0x1 << 21) // (CAN) Wakeup Flag -#define AT91C_CAN_TOVF (0x1 << 22) // (CAN) Timer Overflow Flag -#define AT91C_CAN_TSTP (0x1 << 23) // (CAN) Timestamp Flag -#define AT91C_CAN_CERR (0x1 << 24) // (CAN) CRC Error -#define AT91C_CAN_SERR (0x1 << 25) // (CAN) Stuffing Error -#define AT91C_CAN_AERR (0x1 << 26) // (CAN) Acknowledgment Error -#define AT91C_CAN_FERR (0x1 << 27) // (CAN) Form Error -#define AT91C_CAN_BERR (0x1 << 28) // (CAN) Bit Error -// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- -// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- -// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- -#define AT91C_CAN_RBSY (0x1 << 29) // (CAN) Receiver Busy -#define AT91C_CAN_TBSY (0x1 << 30) // (CAN) Transmitter Busy -#define AT91C_CAN_OVLY (0x1 << 31) // (CAN) Overload Busy -// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- -#define AT91C_CAN_PHASE2 (0x7 << 0) // (CAN) Phase 2 segment -#define AT91C_CAN_PHASE1 (0x7 << 4) // (CAN) Phase 1 segment -#define AT91C_CAN_PROPAG (0x7 << 8) // (CAN) Programmation time segment -#define AT91C_CAN_SYNC (0x3 << 12) // (CAN) Re-synchronization jump width segment -#define AT91C_CAN_BRP (0x7F << 16) // (CAN) Baudrate Prescaler -#define AT91C_CAN_SMP (0x1 << 24) // (CAN) Sampling mode -// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- -#define AT91C_CAN_TIMER (0xFFFF << 0) // (CAN) Timer field -// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- -// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- -#define AT91C_CAN_REC (0xFF << 0) // (CAN) Receive Error Counter -#define AT91C_CAN_TEC (0xFF << 16) // (CAN) Transmit Error Counter -// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- -#define AT91C_CAN_TIMRST (0x1 << 31) // (CAN) Timer Reset Field -// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 -// ***************************************************************************** -// *** Register offset in AT91S_EMAC structure *** -#define EMAC_NCR ( 0) // Network Control Register -#define EMAC_NCFGR ( 4) // Network Configuration Register -#define EMAC_NSR ( 8) // Network Status Register -#define EMAC_TSR (20) // Transmit Status Register -#define EMAC_RBQP (24) // Receive Buffer Queue Pointer -#define EMAC_TBQP (28) // Transmit Buffer Queue Pointer -#define EMAC_RSR (32) // Receive Status Register -#define EMAC_ISR (36) // Interrupt Status Register -#define EMAC_IER (40) // Interrupt Enable Register -#define EMAC_IDR (44) // Interrupt Disable Register -#define EMAC_IMR (48) // Interrupt Mask Register -#define EMAC_MAN (52) // PHY Maintenance Register -#define EMAC_PTR (56) // Pause Time Register -#define EMAC_PFR (60) // Pause Frames received Register -#define EMAC_FTO (64) // Frames Transmitted OK Register -#define EMAC_SCF (68) // Single Collision Frame Register -#define EMAC_MCF (72) // Multiple Collision Frame Register -#define EMAC_FRO (76) // Frames Received OK Register -#define EMAC_FCSE (80) // Frame Check Sequence Error Register -#define EMAC_ALE (84) // Alignment Error Register -#define EMAC_DTF (88) // Deferred Transmission Frame Register -#define EMAC_LCOL (92) // Late Collision Register -#define EMAC_ECOL (96) // Excessive Collision Register -#define EMAC_TUND (100) // Transmit Underrun Error Register -#define EMAC_CSE (104) // Carrier Sense Error Register -#define EMAC_RRE (108) // Receive Ressource Error Register -#define EMAC_ROV (112) // Receive Overrun Errors Register -#define EMAC_RSE (116) // Receive Symbol Errors Register -#define EMAC_ELE (120) // Excessive Length Errors Register -#define EMAC_RJA (124) // Receive Jabbers Register -#define EMAC_USF (128) // Undersize Frames Register -#define EMAC_STE (132) // SQE Test Error Register -#define EMAC_RLE (136) // Receive Length Field Mismatch Register -#define EMAC_TPF (140) // Transmitted Pause Frames Register -#define EMAC_HRB (144) // Hash Address Bottom[31:0] -#define EMAC_HRT (148) // Hash Address Top[63:32] -#define EMAC_SA1L (152) // Specific Address 1 Bottom, First 4 bytes -#define EMAC_SA1H (156) // Specific Address 1 Top, Last 2 bytes -#define EMAC_SA2L (160) // Specific Address 2 Bottom, First 4 bytes -#define EMAC_SA2H (164) // Specific Address 2 Top, Last 2 bytes -#define EMAC_SA3L (168) // Specific Address 3 Bottom, First 4 bytes -#define EMAC_SA3H (172) // Specific Address 3 Top, Last 2 bytes -#define EMAC_SA4L (176) // Specific Address 4 Bottom, First 4 bytes -#define EMAC_SA4H (180) // Specific Address 4 Top, Last 2 bytes -#define EMAC_TID (184) // Type ID Checking Register -#define EMAC_TPQ (188) // Transmit Pause Quantum Register -#define EMAC_USRIO (192) // USER Input/Output Register -#define EMAC_WOL (196) // Wake On LAN Register -#define EMAC_REV (252) // Revision Register -// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- -#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. -#define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local. -#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable. -#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable. -#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable. -#define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers. -#define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers. -#define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers. -#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure. -#define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission. -#define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt. -#define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame -#define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame -// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- -#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed. -#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex. -#define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames. -#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames. -#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast. -#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable -#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable. -#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes. -#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable. -#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC) -#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8 -#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16 -#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32 -#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64 -#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC) -#define AT91C_EMAC_PAE (0x1 << 13) // (EMAC) -#define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC) -#define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer -#define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable -#define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS -#define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC) -#define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS -// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- -#define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC) -#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC) -#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC) -// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- -#define AT91C_EMAC_UBR (0x1 << 0) // (EMAC) -#define AT91C_EMAC_COL (0x1 << 1) // (EMAC) -#define AT91C_EMAC_RLES (0x1 << 2) // (EMAC) -#define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go -#define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame -#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC) -#define AT91C_EMAC_UND (0x1 << 6) // (EMAC) -// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- -#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC) -#define AT91C_EMAC_REC (0x1 << 1) // (EMAC) -#define AT91C_EMAC_OVR (0x1 << 2) // (EMAC) -// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- -#define AT91C_EMAC_MFD (0x1 << 0) // (EMAC) -#define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC) -#define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC) -#define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC) -#define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC) -#define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC) -#define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC) -#define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC) -#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC) -#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC) -#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC) -#define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC) -#define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC) -// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- -// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- -// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- -// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- -#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC) -#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC) -#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC) -#define AT91C_EMAC_RW (0x3 << 28) // (EMAC) -#define AT91C_EMAC_SOF (0x3 << 30) // (EMAC) -// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- -#define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII -// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- -#define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address -#define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable -#define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable -#define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable -// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- -#define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC) - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Analog to Digital Convertor -// ***************************************************************************** -// *** Register offset in AT91S_ADC structure *** -#define ADC_CR ( 0) // ADC Control Register -#define ADC_MR ( 4) // ADC Mode Register -#define ADC_CHER (16) // ADC Channel Enable Register -#define ADC_CHDR (20) // ADC Channel Disable Register -#define ADC_CHSR (24) // ADC Channel Status Register -#define ADC_SR (28) // ADC Status Register -#define ADC_LCDR (32) // ADC Last Converted Data Register -#define ADC_IER (36) // ADC Interrupt Enable Register -#define ADC_IDR (40) // ADC Interrupt Disable Register -#define ADC_IMR (44) // ADC Interrupt Mask Register -#define ADC_CDR0 (48) // ADC Channel Data Register 0 -#define ADC_CDR1 (52) // ADC Channel Data Register 1 -#define ADC_CDR2 (56) // ADC Channel Data Register 2 -#define ADC_CDR3 (60) // ADC Channel Data Register 3 -#define ADC_CDR4 (64) // ADC Channel Data Register 4 -#define ADC_CDR5 (68) // ADC Channel Data Register 5 -#define ADC_CDR6 (72) // ADC Channel Data Register 6 -#define ADC_CDR7 (76) // ADC Channel Data Register 7 -#define ADC_RPR (256) // Receive Pointer Register -#define ADC_RCR (260) // Receive Counter Register -#define ADC_TPR (264) // Transmit Pointer Register -#define ADC_TCR (268) // Transmit Counter Register -#define ADC_RNPR (272) // Receive Next Pointer Register -#define ADC_RNCR (276) // Receive Next Counter Register -#define ADC_TNPR (280) // Transmit Next Pointer Register -#define ADC_TNCR (284) // Transmit Next Counter Register -#define ADC_PTCR (288) // PDC Transfer Control Register -#define ADC_PTSR (292) // PDC Transfer Status Register -// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- -#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset -#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion -// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- -#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable -#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software -#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. -#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection -#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 -#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 -#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 -#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 -#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 -#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 -#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger -#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. -#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution -#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution -#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode -#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection -#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time -#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time -// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- -#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 -#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 -#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 -#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 -#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 -#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 -#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 -#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 -// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- -// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- -// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- -#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion -#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion -#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion -#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion -#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion -#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion -#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion -#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion -#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error -#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error -#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error -#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error -#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error -#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error -#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error -#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error -#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready -#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun -#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer -#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt -// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- -#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted -// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- -// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- -// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- -// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- -#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data -// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- -// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- -// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- -// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- -// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- -// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- -// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Encryption Standard -// ***************************************************************************** -// *** Register offset in AT91S_AES structure *** -#define AES_CR ( 0) // Control Register -#define AES_MR ( 4) // Mode Register -#define AES_IER (16) // Interrupt Enable Register -#define AES_IDR (20) // Interrupt Disable Register -#define AES_IMR (24) // Interrupt Mask Register -#define AES_ISR (28) // Interrupt Status Register -#define AES_KEYWxR (32) // Key Word x Register -#define AES_IDATAxR (64) // Input Data x Register -#define AES_ODATAxR (80) // Output Data x Register -#define AES_IVxR (96) // Initialization Vector x Register -#define AES_VR (252) // AES Version Register -#define AES_RPR (256) // Receive Pointer Register -#define AES_RCR (260) // Receive Counter Register -#define AES_TPR (264) // Transmit Pointer Register -#define AES_TCR (268) // Transmit Counter Register -#define AES_RNPR (272) // Receive Next Pointer Register -#define AES_RNCR (276) // Receive Next Counter Register -#define AES_TNPR (280) // Transmit Next Pointer Register -#define AES_TNCR (284) // Transmit Next Counter Register -#define AES_PTCR (288) // PDC Transfer Control Register -#define AES_PTSR (292) // PDC Transfer Status Register -// -------- AES_CR : (AES Offset: 0x0) Control Register -------- -#define AT91C_AES_START (0x1 << 0) // (AES) Starts Processing -#define AT91C_AES_SWRST (0x1 << 8) // (AES) Software Reset -#define AT91C_AES_LOADSEED (0x1 << 16) // (AES) Random Number Generator Seed Loading -// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- -#define AT91C_AES_CIPHER (0x1 << 0) // (AES) Processing Mode -#define AT91C_AES_PROCDLY (0xF << 4) // (AES) Processing Delay -#define AT91C_AES_SMOD (0x3 << 8) // (AES) Start Mode -#define AT91C_AES_SMOD_MANUAL (0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. -#define AT91C_AES_SMOD_AUTO (0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). -#define AT91C_AES_SMOD_PDC (0x2 << 8) // (AES) PDC Mode (cf datasheet). -#define AT91C_AES_OPMOD (0x7 << 12) // (AES) Operation Mode -#define AT91C_AES_OPMOD_ECB (0x0 << 12) // (AES) ECB Electronic CodeBook mode. -#define AT91C_AES_OPMOD_CBC (0x1 << 12) // (AES) CBC Cipher Block Chaining mode. -#define AT91C_AES_OPMOD_OFB (0x2 << 12) // (AES) OFB Output Feedback mode. -#define AT91C_AES_OPMOD_CFB (0x3 << 12) // (AES) CFB Cipher Feedback mode. -#define AT91C_AES_OPMOD_CTR (0x4 << 12) // (AES) CTR Counter mode. -#define AT91C_AES_LOD (0x1 << 15) // (AES) Last Output Data Mode -#define AT91C_AES_CFBS (0x7 << 16) // (AES) Cipher Feedback Data Size -#define AT91C_AES_CFBS_128_BIT (0x0 << 16) // (AES) 128-bit. -#define AT91C_AES_CFBS_64_BIT (0x1 << 16) // (AES) 64-bit. -#define AT91C_AES_CFBS_32_BIT (0x2 << 16) // (AES) 32-bit. -#define AT91C_AES_CFBS_16_BIT (0x3 << 16) // (AES) 16-bit. -#define AT91C_AES_CFBS_8_BIT (0x4 << 16) // (AES) 8-bit. -#define AT91C_AES_CKEY (0xF << 20) // (AES) Countermeasure Key -#define AT91C_AES_CTYPE (0x1F << 24) // (AES) Countermeasure Type -#define AT91C_AES_CTYPE_TYPE1_EN (0x1 << 24) // (AES) Countermeasure type 1 is enabled. -#define AT91C_AES_CTYPE_TYPE2_EN (0x2 << 24) // (AES) Countermeasure type 2 is enabled. -#define AT91C_AES_CTYPE_TYPE3_EN (0x4 << 24) // (AES) Countermeasure type 3 is enabled. -#define AT91C_AES_CTYPE_TYPE4_EN (0x8 << 24) // (AES) Countermeasure type 4 is enabled. -#define AT91C_AES_CTYPE_TYPE5_EN (0x10 << 24) // (AES) Countermeasure type 5 is enabled. -// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- -#define AT91C_AES_DATRDY (0x1 << 0) // (AES) DATRDY -#define AT91C_AES_ENDRX (0x1 << 1) // (AES) PDC Read Buffer End -#define AT91C_AES_ENDTX (0x1 << 2) // (AES) PDC Write Buffer End -#define AT91C_AES_RXBUFF (0x1 << 3) // (AES) PDC Read Buffer Full -#define AT91C_AES_TXBUFE (0x1 << 4) // (AES) PDC Write Buffer Empty -#define AT91C_AES_URAD (0x1 << 8) // (AES) Unspecified Register Access Detection -// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- -// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- -// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- -#define AT91C_AES_URAT (0x7 << 12) // (AES) Unspecified Register Access Type Status -#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (AES) Input data register written during the data processing in PDC mode. -#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (AES) Output data register read during the data processing. -#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (AES) Mode register written during the data processing. -#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY (0x3 << 12) // (AES) Output data register read during the sub-keys generation. -#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY (0x4 << 12) // (AES) Mode register written during the sub-keys generation. -#define AT91C_AES_URAT_WO_REG_READ (0x5 << 12) // (AES) Write-only register read access. - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard -// ***************************************************************************** -// *** Register offset in AT91S_TDES structure *** -#define TDES_CR ( 0) // Control Register -#define TDES_MR ( 4) // Mode Register -#define TDES_IER (16) // Interrupt Enable Register -#define TDES_IDR (20) // Interrupt Disable Register -#define TDES_IMR (24) // Interrupt Mask Register -#define TDES_ISR (28) // Interrupt Status Register -#define TDES_KEY1WxR (32) // Key 1 Word x Register -#define TDES_KEY2WxR (40) // Key 2 Word x Register -#define TDES_KEY3WxR (48) // Key 3 Word x Register -#define TDES_IDATAxR (64) // Input Data x Register -#define TDES_ODATAxR (80) // Output Data x Register -#define TDES_IVxR (96) // Initialization Vector x Register -#define TDES_VR (252) // TDES Version Register -#define TDES_RPR (256) // Receive Pointer Register -#define TDES_RCR (260) // Receive Counter Register -#define TDES_TPR (264) // Transmit Pointer Register -#define TDES_TCR (268) // Transmit Counter Register -#define TDES_RNPR (272) // Receive Next Pointer Register -#define TDES_RNCR (276) // Receive Next Counter Register -#define TDES_TNPR (280) // Transmit Next Pointer Register -#define TDES_TNCR (284) // Transmit Next Counter Register -#define TDES_PTCR (288) // PDC Transfer Control Register -#define TDES_PTSR (292) // PDC Transfer Status Register -// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- -#define AT91C_TDES_START (0x1 << 0) // (TDES) Starts Processing -#define AT91C_TDES_SWRST (0x1 << 8) // (TDES) Software Reset -// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- -#define AT91C_TDES_CIPHER (0x1 << 0) // (TDES) Processing Mode -#define AT91C_TDES_TDESMOD (0x1 << 1) // (TDES) Single or Triple DES Mode -#define AT91C_TDES_KEYMOD (0x1 << 4) // (TDES) Key Mode -#define AT91C_TDES_SMOD (0x3 << 8) // (TDES) Start Mode -#define AT91C_TDES_SMOD_MANUAL (0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. -#define AT91C_TDES_SMOD_AUTO (0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). -#define AT91C_TDES_SMOD_PDC (0x2 << 8) // (TDES) PDC Mode (cf datasheet). -#define AT91C_TDES_OPMOD (0x3 << 12) // (TDES) Operation Mode -#define AT91C_TDES_OPMOD_ECB (0x0 << 12) // (TDES) ECB Electronic CodeBook mode. -#define AT91C_TDES_OPMOD_CBC (0x1 << 12) // (TDES) CBC Cipher Block Chaining mode. -#define AT91C_TDES_OPMOD_OFB (0x2 << 12) // (TDES) OFB Output Feedback mode. -#define AT91C_TDES_OPMOD_CFB (0x3 << 12) // (TDES) CFB Cipher Feedback mode. -#define AT91C_TDES_LOD (0x1 << 15) // (TDES) Last Output Data Mode -#define AT91C_TDES_CFBS (0x3 << 16) // (TDES) Cipher Feedback Data Size -#define AT91C_TDES_CFBS_64_BIT (0x0 << 16) // (TDES) 64-bit. -#define AT91C_TDES_CFBS_32_BIT (0x1 << 16) // (TDES) 32-bit. -#define AT91C_TDES_CFBS_16_BIT (0x2 << 16) // (TDES) 16-bit. -#define AT91C_TDES_CFBS_8_BIT (0x3 << 16) // (TDES) 8-bit. -// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- -#define AT91C_TDES_DATRDY (0x1 << 0) // (TDES) DATRDY -#define AT91C_TDES_ENDRX (0x1 << 1) // (TDES) PDC Read Buffer End -#define AT91C_TDES_ENDTX (0x1 << 2) // (TDES) PDC Write Buffer End -#define AT91C_TDES_RXBUFF (0x1 << 3) // (TDES) PDC Read Buffer Full -#define AT91C_TDES_TXBUFE (0x1 << 4) // (TDES) PDC Write Buffer Empty -#define AT91C_TDES_URAD (0x1 << 8) // (TDES) Unspecified Register Access Detection -// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- -// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- -// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- -#define AT91C_TDES_URAT (0x3 << 12) // (TDES) Unspecified Register Access Type Status -#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode. -#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (TDES) Output data register read during the data processing. -#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (TDES) Mode register written during the data processing. -#define AT91C_TDES_URAT_WO_REG_READ (0x3 << 12) // (TDES) Write-only register read access. - -// ***************************************************************************** -// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 -// ***************************************************************************** -// ========== Register definition for SYS peripheral ========== -// ========== Register definition for AIC peripheral ========== -#define AT91C_AIC_IVR (0xFFFFF100) // (AIC) IRQ Vector Register -#define AT91C_AIC_SMR (0xFFFFF000) // (AIC) Source Mode Register -#define AT91C_AIC_FVR (0xFFFFF104) // (AIC) FIQ Vector Register -#define AT91C_AIC_DCR (0xFFFFF138) // (AIC) Debug Control Register (Protect) -#define AT91C_AIC_EOICR (0xFFFFF130) // (AIC) End of Interrupt Command Register -#define AT91C_AIC_SVR (0xFFFFF080) // (AIC) Source Vector Register -#define AT91C_AIC_FFSR (0xFFFFF148) // (AIC) Fast Forcing Status Register -#define AT91C_AIC_ICCR (0xFFFFF128) // (AIC) Interrupt Clear Command Register -#define AT91C_AIC_ISR (0xFFFFF108) // (AIC) Interrupt Status Register -#define AT91C_AIC_IMR (0xFFFFF110) // (AIC) Interrupt Mask Register -#define AT91C_AIC_IPR (0xFFFFF10C) // (AIC) Interrupt Pending Register -#define AT91C_AIC_FFER (0xFFFFF140) // (AIC) Fast Forcing Enable Register -#define AT91C_AIC_IECR (0xFFFFF120) // (AIC) Interrupt Enable Command Register -#define AT91C_AIC_ISCR (0xFFFFF12C) // (AIC) Interrupt Set Command Register -#define AT91C_AIC_FFDR (0xFFFFF144) // (AIC) Fast Forcing Disable Register -#define AT91C_AIC_CISR (0xFFFFF114) // (AIC) Core Interrupt Status Register -#define AT91C_AIC_IDCR (0xFFFFF124) // (AIC) Interrupt Disable Command Register -#define AT91C_AIC_SPU (0xFFFFF134) // (AIC) Spurious Vector Register -// ========== Register definition for PDC_DBGU peripheral ========== -#define AT91C_DBGU_TCR (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register -#define AT91C_DBGU_RNPR (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register -#define AT91C_DBGU_TNPR (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register -#define AT91C_DBGU_TPR (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register -#define AT91C_DBGU_RPR (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register -#define AT91C_DBGU_RCR (0xFFFFF304) // (PDC_DBGU) Receive Counter Register -#define AT91C_DBGU_RNCR (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register -#define AT91C_DBGU_PTCR (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register -#define AT91C_DBGU_PTSR (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register -#define AT91C_DBGU_TNCR (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register -// ========== Register definition for DBGU peripheral ========== -#define AT91C_DBGU_EXID (0xFFFFF244) // (DBGU) Chip ID Extension Register -#define AT91C_DBGU_BRGR (0xFFFFF220) // (DBGU) Baud Rate Generator Register -#define AT91C_DBGU_IDR (0xFFFFF20C) // (DBGU) Interrupt Disable Register -#define AT91C_DBGU_CSR (0xFFFFF214) // (DBGU) Channel Status Register -#define AT91C_DBGU_CIDR (0xFFFFF240) // (DBGU) Chip ID Register -#define AT91C_DBGU_MR (0xFFFFF204) // (DBGU) Mode Register -#define AT91C_DBGU_IMR (0xFFFFF210) // (DBGU) Interrupt Mask Register -#define AT91C_DBGU_CR (0xFFFFF200) // (DBGU) Control Register -#define AT91C_DBGU_FNTR (0xFFFFF248) // (DBGU) Force NTRST Register -#define AT91C_DBGU_THR (0xFFFFF21C) // (DBGU) Transmitter Holding Register -#define AT91C_DBGU_RHR (0xFFFFF218) // (DBGU) Receiver Holding Register -#define AT91C_DBGU_IER (0xFFFFF208) // (DBGU) Interrupt Enable Register -// ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_ODR (0xFFFFF414) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_SODR (0xFFFFF430) // (PIOA) Set Output Data Register -#define AT91C_PIOA_ISR (0xFFFFF44C) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_ABSR (0xFFFFF478) // (PIOA) AB Select Status Register -#define AT91C_PIOA_IER (0xFFFFF440) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_PPUDR (0xFFFFF460) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_IMR (0xFFFFF448) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_PER (0xFFFFF400) // (PIOA) PIO Enable Register -#define AT91C_PIOA_IFDR (0xFFFFF424) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_OWDR (0xFFFFF4A4) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_MDSR (0xFFFFF458) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_IDR (0xFFFFF444) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_ODSR (0xFFFFF438) // (PIOA) Output Data Status Register -#define AT91C_PIOA_PPUSR (0xFFFFF468) // (PIOA) Pull-up Status Register -#define AT91C_PIOA_OWSR (0xFFFFF4A8) // (PIOA) Output Write Status Register -#define AT91C_PIOA_BSR (0xFFFFF474) // (PIOA) Select B Register -#define AT91C_PIOA_OWER (0xFFFFF4A0) // (PIOA) Output Write Enable Register -#define AT91C_PIOA_IFER (0xFFFFF420) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_PDSR (0xFFFFF43C) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_PPUER (0xFFFFF464) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_OSR (0xFFFFF418) // (PIOA) Output Status Register -#define AT91C_PIOA_ASR (0xFFFFF470) // (PIOA) Select A Register -#define AT91C_PIOA_MDDR (0xFFFFF454) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_CODR (0xFFFFF434) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_MDER (0xFFFFF450) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PDR (0xFFFFF404) // (PIOA) PIO Disable Register -#define AT91C_PIOA_IFSR (0xFFFFF428) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_OER (0xFFFFF410) // (PIOA) Output Enable Register -#define AT91C_PIOA_PSR (0xFFFFF408) // (PIOA) PIO Status Register -// ========== Register definition for PIOB peripheral ========== -#define AT91C_PIOB_OWDR (0xFFFFF6A4) // (PIOB) Output Write Disable Register -#define AT91C_PIOB_MDER (0xFFFFF650) // (PIOB) Multi-driver Enable Register -#define AT91C_PIOB_PPUSR (0xFFFFF668) // (PIOB) Pull-up Status Register -#define AT91C_PIOB_IMR (0xFFFFF648) // (PIOB) Interrupt Mask Register -#define AT91C_PIOB_ASR (0xFFFFF670) // (PIOB) Select A Register -#define AT91C_PIOB_PPUDR (0xFFFFF660) // (PIOB) Pull-up Disable Register -#define AT91C_PIOB_PSR (0xFFFFF608) // (PIOB) PIO Status Register -#define AT91C_PIOB_IER (0xFFFFF640) // (PIOB) Interrupt Enable Register -#define AT91C_PIOB_CODR (0xFFFFF634) // (PIOB) Clear Output Data Register -#define AT91C_PIOB_OWER (0xFFFFF6A0) // (PIOB) Output Write Enable Register -#define AT91C_PIOB_ABSR (0xFFFFF678) // (PIOB) AB Select Status Register -#define AT91C_PIOB_IFDR (0xFFFFF624) // (PIOB) Input Filter Disable Register -#define AT91C_PIOB_PDSR (0xFFFFF63C) // (PIOB) Pin Data Status Register -#define AT91C_PIOB_IDR (0xFFFFF644) // (PIOB) Interrupt Disable Register -#define AT91C_PIOB_OWSR (0xFFFFF6A8) // (PIOB) Output Write Status Register -#define AT91C_PIOB_PDR (0xFFFFF604) // (PIOB) PIO Disable Register -#define AT91C_PIOB_ODR (0xFFFFF614) // (PIOB) Output Disable Registerr -#define AT91C_PIOB_IFSR (0xFFFFF628) // (PIOB) Input Filter Status Register -#define AT91C_PIOB_PPUER (0xFFFFF664) // (PIOB) Pull-up Enable Register -#define AT91C_PIOB_SODR (0xFFFFF630) // (PIOB) Set Output Data Register -#define AT91C_PIOB_ISR (0xFFFFF64C) // (PIOB) Interrupt Status Register -#define AT91C_PIOB_ODSR (0xFFFFF638) // (PIOB) Output Data Status Register -#define AT91C_PIOB_OSR (0xFFFFF618) // (PIOB) Output Status Register -#define AT91C_PIOB_MDSR (0xFFFFF658) // (PIOB) Multi-driver Status Register -#define AT91C_PIOB_IFER (0xFFFFF620) // (PIOB) Input Filter Enable Register -#define AT91C_PIOB_BSR (0xFFFFF674) // (PIOB) Select B Register -#define AT91C_PIOB_MDDR (0xFFFFF654) // (PIOB) Multi-driver Disable Register -#define AT91C_PIOB_OER (0xFFFFF610) // (PIOB) Output Enable Register -#define AT91C_PIOB_PER (0xFFFFF600) // (PIOB) PIO Enable Register -// ========== Register definition for CKGR peripheral ========== -#define AT91C_CKGR_MOR (0xFFFFFC20) // (CKGR) Main Oscillator Register -#define AT91C_CKGR_PLLR (0xFFFFFC2C) // (CKGR) PLL Register -#define AT91C_CKGR_MCFR (0xFFFFFC24) // (CKGR) Main Clock Frequency Register -// ========== Register definition for PMC peripheral ========== -#define AT91C_PMC_IDR (0xFFFFFC64) // (PMC) Interrupt Disable Register -#define AT91C_PMC_MOR (0xFFFFFC20) // (PMC) Main Oscillator Register -#define AT91C_PMC_PLLR (0xFFFFFC2C) // (PMC) PLL Register -#define AT91C_PMC_PCER (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register -#define AT91C_PMC_PCKR (0xFFFFFC40) // (PMC) Programmable Clock Register -#define AT91C_PMC_MCKR (0xFFFFFC30) // (PMC) Master Clock Register -#define AT91C_PMC_SCDR (0xFFFFFC04) // (PMC) System Clock Disable Register -#define AT91C_PMC_PCDR (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register -#define AT91C_PMC_SCSR (0xFFFFFC08) // (PMC) System Clock Status Register -#define AT91C_PMC_PCSR (0xFFFFFC18) // (PMC) Peripheral Clock Status Register -#define AT91C_PMC_MCFR (0xFFFFFC24) // (PMC) Main Clock Frequency Register -#define AT91C_PMC_SCER (0xFFFFFC00) // (PMC) System Clock Enable Register -#define AT91C_PMC_IMR (0xFFFFFC6C) // (PMC) Interrupt Mask Register -#define AT91C_PMC_IER (0xFFFFFC60) // (PMC) Interrupt Enable Register -#define AT91C_PMC_SR (0xFFFFFC68) // (PMC) Status Register -// ========== Register definition for RSTC peripheral ========== -#define AT91C_RSTC_RCR (0xFFFFFD00) // (RSTC) Reset Control Register -#define AT91C_RSTC_RMR (0xFFFFFD08) // (RSTC) Reset Mode Register -#define AT91C_RSTC_RSR (0xFFFFFD04) // (RSTC) Reset Status Register -// ========== Register definition for RTTC peripheral ========== -#define AT91C_RTTC_RTSR (0xFFFFFD2C) // (RTTC) Real-time Status Register -#define AT91C_RTTC_RTMR (0xFFFFFD20) // (RTTC) Real-time Mode Register -#define AT91C_RTTC_RTVR (0xFFFFFD28) // (RTTC) Real-time Value Register -#define AT91C_RTTC_RTAR (0xFFFFFD24) // (RTTC) Real-time Alarm Register -// ========== Register definition for PITC peripheral ========== -#define AT91C_PITC_PIVR (0xFFFFFD38) // (PITC) Period Interval Value Register -#define AT91C_PITC_PISR (0xFFFFFD34) // (PITC) Period Interval Status Register -#define AT91C_PITC_PIIR (0xFFFFFD3C) // (PITC) Period Interval Image Register -#define AT91C_PITC_PIMR (0xFFFFFD30) // (PITC) Period Interval Mode Register -// ========== Register definition for WDTC peripheral ========== -#define AT91C_WDTC_WDCR (0xFFFFFD40) // (WDTC) Watchdog Control Register -#define AT91C_WDTC_WDSR (0xFFFFFD48) // (WDTC) Watchdog Status Register -#define AT91C_WDTC_WDMR (0xFFFFFD44) // (WDTC) Watchdog Mode Register -// ========== Register definition for VREG peripheral ========== -#define AT91C_VREG_MR (0xFFFFFD60) // (VREG) Voltage Regulator Mode Register -// ========== Register definition for MC peripheral ========== -#define AT91C_MC_ASR (0xFFFFFF04) // (MC) MC Abort Status Register -#define AT91C_MC_RCR (0xFFFFFF00) // (MC) MC Remap Control Register -#define AT91C_MC_FCR (0xFFFFFF64) // (MC) MC Flash Command Register -#define AT91C_MC_AASR (0xFFFFFF08) // (MC) MC Abort Address Status Register -#define AT91C_MC_FSR (0xFFFFFF68) // (MC) MC Flash Status Register -#define AT91C_MC_FMR (0xFFFFFF60) // (MC) MC Flash Mode Register -// ========== Register definition for PDC_SPI1 peripheral ========== -#define AT91C_SPI1_PTCR (0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register -#define AT91C_SPI1_RPR (0xFFFE4100) // (PDC_SPI1) Receive Pointer Register -#define AT91C_SPI1_TNCR (0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register -#define AT91C_SPI1_TPR (0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register -#define AT91C_SPI1_TNPR (0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register -#define AT91C_SPI1_TCR (0xFFFE410C) // (PDC_SPI1) Transmit Counter Register -#define AT91C_SPI1_RCR (0xFFFE4104) // (PDC_SPI1) Receive Counter Register -#define AT91C_SPI1_RNPR (0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register -#define AT91C_SPI1_RNCR (0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register -#define AT91C_SPI1_PTSR (0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register -// ========== Register definition for SPI1 peripheral ========== -#define AT91C_SPI1_IMR (0xFFFE401C) // (SPI1) Interrupt Mask Register -#define AT91C_SPI1_IER (0xFFFE4014) // (SPI1) Interrupt Enable Register -#define AT91C_SPI1_MR (0xFFFE4004) // (SPI1) Mode Register -#define AT91C_SPI1_RDR (0xFFFE4008) // (SPI1) Receive Data Register -#define AT91C_SPI1_IDR (0xFFFE4018) // (SPI1) Interrupt Disable Register -#define AT91C_SPI1_SR (0xFFFE4010) // (SPI1) Status Register -#define AT91C_SPI1_TDR (0xFFFE400C) // (SPI1) Transmit Data Register -#define AT91C_SPI1_CR (0xFFFE4000) // (SPI1) Control Register -#define AT91C_SPI1_CSR (0xFFFE4030) // (SPI1) Chip Select Register -// ========== Register definition for PDC_SPI0 peripheral ========== -#define AT91C_SPI0_PTCR (0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register -#define AT91C_SPI0_TPR (0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register -#define AT91C_SPI0_TCR (0xFFFE010C) // (PDC_SPI0) Transmit Counter Register -#define AT91C_SPI0_RCR (0xFFFE0104) // (PDC_SPI0) Receive Counter Register -#define AT91C_SPI0_PTSR (0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register -#define AT91C_SPI0_RNPR (0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register -#define AT91C_SPI0_RPR (0xFFFE0100) // (PDC_SPI0) Receive Pointer Register -#define AT91C_SPI0_TNCR (0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register -#define AT91C_SPI0_RNCR (0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register -#define AT91C_SPI0_TNPR (0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register -// ========== Register definition for SPI0 peripheral ========== -#define AT91C_SPI0_IER (0xFFFE0014) // (SPI0) Interrupt Enable Register -#define AT91C_SPI0_SR (0xFFFE0010) // (SPI0) Status Register -#define AT91C_SPI0_IDR (0xFFFE0018) // (SPI0) Interrupt Disable Register -#define AT91C_SPI0_CR (0xFFFE0000) // (SPI0) Control Register -#define AT91C_SPI0_MR (0xFFFE0004) // (SPI0) Mode Register -#define AT91C_SPI0_IMR (0xFFFE001C) // (SPI0) Interrupt Mask Register -#define AT91C_SPI0_TDR (0xFFFE000C) // (SPI0) Transmit Data Register -#define AT91C_SPI0_RDR (0xFFFE0008) // (SPI0) Receive Data Register -#define AT91C_SPI0_CSR (0xFFFE0030) // (SPI0) Chip Select Register -// ========== Register definition for PDC_US1 peripheral ========== -#define AT91C_US1_RNCR (0xFFFC4114) // (PDC_US1) Receive Next Counter Register -#define AT91C_US1_PTCR (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register -#define AT91C_US1_TCR (0xFFFC410C) // (PDC_US1) Transmit Counter Register -#define AT91C_US1_PTSR (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register -#define AT91C_US1_TNPR (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register -#define AT91C_US1_RCR (0xFFFC4104) // (PDC_US1) Receive Counter Register -#define AT91C_US1_RNPR (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register -#define AT91C_US1_RPR (0xFFFC4100) // (PDC_US1) Receive Pointer Register -#define AT91C_US1_TNCR (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register -#define AT91C_US1_TPR (0xFFFC4108) // (PDC_US1) Transmit Pointer Register -// ========== Register definition for US1 peripheral ========== -#define AT91C_US1_IF (0xFFFC404C) // (US1) IRDA_FILTER Register -#define AT91C_US1_NER (0xFFFC4044) // (US1) Nb Errors Register -#define AT91C_US1_RTOR (0xFFFC4024) // (US1) Receiver Time-out Register -#define AT91C_US1_CSR (0xFFFC4014) // (US1) Channel Status Register -#define AT91C_US1_IDR (0xFFFC400C) // (US1) Interrupt Disable Register -#define AT91C_US1_IER (0xFFFC4008) // (US1) Interrupt Enable Register -#define AT91C_US1_THR (0xFFFC401C) // (US1) Transmitter Holding Register -#define AT91C_US1_TTGR (0xFFFC4028) // (US1) Transmitter Time-guard Register -#define AT91C_US1_RHR (0xFFFC4018) // (US1) Receiver Holding Register -#define AT91C_US1_BRGR (0xFFFC4020) // (US1) Baud Rate Generator Register -#define AT91C_US1_IMR (0xFFFC4010) // (US1) Interrupt Mask Register -#define AT91C_US1_FIDI (0xFFFC4040) // (US1) FI_DI_Ratio Register -#define AT91C_US1_CR (0xFFFC4000) // (US1) Control Register -#define AT91C_US1_MR (0xFFFC4004) // (US1) Mode Register -// ========== Register definition for PDC_US0 peripheral ========== -#define AT91C_US0_TNPR (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register -#define AT91C_US0_RNPR (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register -#define AT91C_US0_TCR (0xFFFC010C) // (PDC_US0) Transmit Counter Register -#define AT91C_US0_PTCR (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register -#define AT91C_US0_PTSR (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register -#define AT91C_US0_TNCR (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register -#define AT91C_US0_TPR (0xFFFC0108) // (PDC_US0) Transmit Pointer Register -#define AT91C_US0_RCR (0xFFFC0104) // (PDC_US0) Receive Counter Register -#define AT91C_US0_RPR (0xFFFC0100) // (PDC_US0) Receive Pointer Register -#define AT91C_US0_RNCR (0xFFFC0114) // (PDC_US0) Receive Next Counter Register -// ========== Register definition for US0 peripheral ========== -#define AT91C_US0_BRGR (0xFFFC0020) // (US0) Baud Rate Generator Register -#define AT91C_US0_NER (0xFFFC0044) // (US0) Nb Errors Register -#define AT91C_US0_CR (0xFFFC0000) // (US0) Control Register -#define AT91C_US0_IMR (0xFFFC0010) // (US0) Interrupt Mask Register -#define AT91C_US0_FIDI (0xFFFC0040) // (US0) FI_DI_Ratio Register -#define AT91C_US0_TTGR (0xFFFC0028) // (US0) Transmitter Time-guard Register -#define AT91C_US0_MR (0xFFFC0004) // (US0) Mode Register -#define AT91C_US0_RTOR (0xFFFC0024) // (US0) Receiver Time-out Register -#define AT91C_US0_CSR (0xFFFC0014) // (US0) Channel Status Register -#define AT91C_US0_RHR (0xFFFC0018) // (US0) Receiver Holding Register -#define AT91C_US0_IDR (0xFFFC000C) // (US0) Interrupt Disable Register -#define AT91C_US0_THR (0xFFFC001C) // (US0) Transmitter Holding Register -#define AT91C_US0_IF (0xFFFC004C) // (US0) IRDA_FILTER Register -#define AT91C_US0_IER (0xFFFC0008) // (US0) Interrupt Enable Register -// ========== Register definition for PDC_SSC peripheral ========== -#define AT91C_SSC_TNCR (0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register -#define AT91C_SSC_RPR (0xFFFD4100) // (PDC_SSC) Receive Pointer Register -#define AT91C_SSC_RNCR (0xFFFD4114) // (PDC_SSC) Receive Next Counter Register -#define AT91C_SSC_TPR (0xFFFD4108) // (PDC_SSC) Transmit Pointer Register -#define AT91C_SSC_PTCR (0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register -#define AT91C_SSC_TCR (0xFFFD410C) // (PDC_SSC) Transmit Counter Register -#define AT91C_SSC_RCR (0xFFFD4104) // (PDC_SSC) Receive Counter Register -#define AT91C_SSC_RNPR (0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register -#define AT91C_SSC_TNPR (0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register -#define AT91C_SSC_PTSR (0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register -// ========== Register definition for SSC peripheral ========== -#define AT91C_SSC_RHR (0xFFFD4020) // (SSC) Receive Holding Register -#define AT91C_SSC_RSHR (0xFFFD4030) // (SSC) Receive Sync Holding Register -#define AT91C_SSC_TFMR (0xFFFD401C) // (SSC) Transmit Frame Mode Register -#define AT91C_SSC_IDR (0xFFFD4048) // (SSC) Interrupt Disable Register -#define AT91C_SSC_THR (0xFFFD4024) // (SSC) Transmit Holding Register -#define AT91C_SSC_RCMR (0xFFFD4010) // (SSC) Receive Clock ModeRegister -#define AT91C_SSC_IER (0xFFFD4044) // (SSC) Interrupt Enable Register -#define AT91C_SSC_TSHR (0xFFFD4034) // (SSC) Transmit Sync Holding Register -#define AT91C_SSC_SR (0xFFFD4040) // (SSC) Status Register -#define AT91C_SSC_CMR (0xFFFD4004) // (SSC) Clock Mode Register -#define AT91C_SSC_TCMR (0xFFFD4018) // (SSC) Transmit Clock Mode Register -#define AT91C_SSC_CR (0xFFFD4000) // (SSC) Control Register -#define AT91C_SSC_IMR (0xFFFD404C) // (SSC) Interrupt Mask Register -#define AT91C_SSC_RFMR (0xFFFD4014) // (SSC) Receive Frame Mode Register -// ========== Register definition for TWI peripheral ========== -#define AT91C_TWI_IER (0xFFFB8024) // (TWI) Interrupt Enable Register -#define AT91C_TWI_CR (0xFFFB8000) // (TWI) Control Register -#define AT91C_TWI_SR (0xFFFB8020) // (TWI) Status Register -#define AT91C_TWI_IMR (0xFFFB802C) // (TWI) Interrupt Mask Register -#define AT91C_TWI_THR (0xFFFB8034) // (TWI) Transmit Holding Register -#define AT91C_TWI_IDR (0xFFFB8028) // (TWI) Interrupt Disable Register -#define AT91C_TWI_IADR (0xFFFB800C) // (TWI) Internal Address Register -#define AT91C_TWI_MMR (0xFFFB8004) // (TWI) Master Mode Register -#define AT91C_TWI_CWGR (0xFFFB8010) // (TWI) Clock Waveform Generator Register -#define AT91C_TWI_RHR (0xFFFB8030) // (TWI) Receive Holding Register -// ========== Register definition for PWMC_CH3 peripheral ========== -#define AT91C_PWMC_CH3_CUPDR (0xFFFCC270) // (PWMC_CH3) Channel Update Register -#define AT91C_PWMC_CH3_Reserved (0xFFFCC274) // (PWMC_CH3) Reserved -#define AT91C_PWMC_CH3_CPRDR (0xFFFCC268) // (PWMC_CH3) Channel Period Register -#define AT91C_PWMC_CH3_CDTYR (0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register -#define AT91C_PWMC_CH3_CCNTR (0xFFFCC26C) // (PWMC_CH3) Channel Counter Register -#define AT91C_PWMC_CH3_CMR (0xFFFCC260) // (PWMC_CH3) Channel Mode Register -// ========== Register definition for PWMC_CH2 peripheral ========== -#define AT91C_PWMC_CH2_Reserved (0xFFFCC254) // (PWMC_CH2) Reserved -#define AT91C_PWMC_CH2_CMR (0xFFFCC240) // (PWMC_CH2) Channel Mode Register -#define AT91C_PWMC_CH2_CCNTR (0xFFFCC24C) // (PWMC_CH2) Channel Counter Register -#define AT91C_PWMC_CH2_CPRDR (0xFFFCC248) // (PWMC_CH2) Channel Period Register -#define AT91C_PWMC_CH2_CUPDR (0xFFFCC250) // (PWMC_CH2) Channel Update Register -#define AT91C_PWMC_CH2_CDTYR (0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH1 peripheral ========== -#define AT91C_PWMC_CH1_Reserved (0xFFFCC234) // (PWMC_CH1) Reserved -#define AT91C_PWMC_CH1_CUPDR (0xFFFCC230) // (PWMC_CH1) Channel Update Register -#define AT91C_PWMC_CH1_CPRDR (0xFFFCC228) // (PWMC_CH1) Channel Period Register -#define AT91C_PWMC_CH1_CCNTR (0xFFFCC22C) // (PWMC_CH1) Channel Counter Register -#define AT91C_PWMC_CH1_CDTYR (0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register -#define AT91C_PWMC_CH1_CMR (0xFFFCC220) // (PWMC_CH1) Channel Mode Register -// ========== Register definition for PWMC_CH0 peripheral ========== -#define AT91C_PWMC_CH0_Reserved (0xFFFCC214) // (PWMC_CH0) Reserved -#define AT91C_PWMC_CH0_CPRDR (0xFFFCC208) // (PWMC_CH0) Channel Period Register -#define AT91C_PWMC_CH0_CDTYR (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register -#define AT91C_PWMC_CH0_CMR (0xFFFCC200) // (PWMC_CH0) Channel Mode Register -#define AT91C_PWMC_CH0_CUPDR (0xFFFCC210) // (PWMC_CH0) Channel Update Register -#define AT91C_PWMC_CH0_CCNTR (0xFFFCC20C) // (PWMC_CH0) Channel Counter Register -// ========== Register definition for PWMC peripheral ========== -#define AT91C_PWMC_IDR (0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register -#define AT91C_PWMC_DIS (0xFFFCC008) // (PWMC) PWMC Disable Register -#define AT91C_PWMC_IER (0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register -#define AT91C_PWMC_VR (0xFFFCC0FC) // (PWMC) PWMC Version Register -#define AT91C_PWMC_ISR (0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register -#define AT91C_PWMC_SR (0xFFFCC00C) // (PWMC) PWMC Status Register -#define AT91C_PWMC_IMR (0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register -#define AT91C_PWMC_MR (0xFFFCC000) // (PWMC) PWMC Mode Register -#define AT91C_PWMC_ENA (0xFFFCC004) // (PWMC) PWMC Enable Register -// ========== Register definition for UDP peripheral ========== -#define AT91C_UDP_IMR (0xFFFB0018) // (UDP) Interrupt Mask Register -#define AT91C_UDP_FADDR (0xFFFB0008) // (UDP) Function Address Register -#define AT91C_UDP_NUM (0xFFFB0000) // (UDP) Frame Number Register -#define AT91C_UDP_FDR (0xFFFB0050) // (UDP) Endpoint FIFO Data Register -#define AT91C_UDP_ISR (0xFFFB001C) // (UDP) Interrupt Status Register -#define AT91C_UDP_CSR (0xFFFB0030) // (UDP) Endpoint Control and Status Register -#define AT91C_UDP_IDR (0xFFFB0014) // (UDP) Interrupt Disable Register -#define AT91C_UDP_ICR (0xFFFB0020) // (UDP) Interrupt Clear Register -#define AT91C_UDP_RSTEP (0xFFFB0028) // (UDP) Reset Endpoint Register -#define AT91C_UDP_TXVC (0xFFFB0074) // (UDP) Transceiver Control Register -#define AT91C_UDP_GLBSTATE (0xFFFB0004) // (UDP) Global State Register -#define AT91C_UDP_IER (0xFFFB0010) // (UDP) Interrupt Enable Register -// ========== Register definition for TC0 peripheral ========== -#define AT91C_TC0_SR (0xFFFA0020) // (TC0) Status Register -#define AT91C_TC0_RC (0xFFFA001C) // (TC0) Register C -#define AT91C_TC0_RB (0xFFFA0018) // (TC0) Register B -#define AT91C_TC0_CCR (0xFFFA0000) // (TC0) Channel Control Register -#define AT91C_TC0_CMR (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC0_IER (0xFFFA0024) // (TC0) Interrupt Enable Register -#define AT91C_TC0_RA (0xFFFA0014) // (TC0) Register A -#define AT91C_TC0_IDR (0xFFFA0028) // (TC0) Interrupt Disable Register -#define AT91C_TC0_CV (0xFFFA0010) // (TC0) Counter Value -#define AT91C_TC0_IMR (0xFFFA002C) // (TC0) Interrupt Mask Register -// ========== Register definition for TC1 peripheral ========== -#define AT91C_TC1_RB (0xFFFA0058) // (TC1) Register B -#define AT91C_TC1_CCR (0xFFFA0040) // (TC1) Channel Control Register -#define AT91C_TC1_IER (0xFFFA0064) // (TC1) Interrupt Enable Register -#define AT91C_TC1_IDR (0xFFFA0068) // (TC1) Interrupt Disable Register -#define AT91C_TC1_SR (0xFFFA0060) // (TC1) Status Register -#define AT91C_TC1_CMR (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC1_RA (0xFFFA0054) // (TC1) Register A -#define AT91C_TC1_RC (0xFFFA005C) // (TC1) Register C -#define AT91C_TC1_IMR (0xFFFA006C) // (TC1) Interrupt Mask Register -#define AT91C_TC1_CV (0xFFFA0050) // (TC1) Counter Value -// ========== Register definition for TC2 peripheral ========== -#define AT91C_TC2_CMR (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC2_CCR (0xFFFA0080) // (TC2) Channel Control Register -#define AT91C_TC2_CV (0xFFFA0090) // (TC2) Counter Value -#define AT91C_TC2_RA (0xFFFA0094) // (TC2) Register A -#define AT91C_TC2_RB (0xFFFA0098) // (TC2) Register B -#define AT91C_TC2_IDR (0xFFFA00A8) // (TC2) Interrupt Disable Register -#define AT91C_TC2_IMR (0xFFFA00AC) // (TC2) Interrupt Mask Register -#define AT91C_TC2_RC (0xFFFA009C) // (TC2) Register C -#define AT91C_TC2_IER (0xFFFA00A4) // (TC2) Interrupt Enable Register -#define AT91C_TC2_SR (0xFFFA00A0) // (TC2) Status Register -// ========== Register definition for TCB peripheral ========== -#define AT91C_TCB_BMR (0xFFFA00C4) // (TCB) TC Block Mode Register -#define AT91C_TCB_BCR (0xFFFA00C0) // (TCB) TC Block Control Register -// ========== Register definition for CAN_MB0 peripheral ========== -#define AT91C_CAN_MB0_MDL (0xFFFD0214) // (CAN_MB0) MailBox Data Low Register -#define AT91C_CAN_MB0_MAM (0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register -#define AT91C_CAN_MB0_MCR (0xFFFD021C) // (CAN_MB0) MailBox Control Register -#define AT91C_CAN_MB0_MID (0xFFFD0208) // (CAN_MB0) MailBox ID Register -#define AT91C_CAN_MB0_MSR (0xFFFD0210) // (CAN_MB0) MailBox Status Register -#define AT91C_CAN_MB0_MFID (0xFFFD020C) // (CAN_MB0) MailBox Family ID Register -#define AT91C_CAN_MB0_MDH (0xFFFD0218) // (CAN_MB0) MailBox Data High Register -#define AT91C_CAN_MB0_MMR (0xFFFD0200) // (CAN_MB0) MailBox Mode Register -// ========== Register definition for CAN_MB1 peripheral ========== -#define AT91C_CAN_MB1_MDL (0xFFFD0234) // (CAN_MB1) MailBox Data Low Register -#define AT91C_CAN_MB1_MID (0xFFFD0228) // (CAN_MB1) MailBox ID Register -#define AT91C_CAN_MB1_MMR (0xFFFD0220) // (CAN_MB1) MailBox Mode Register -#define AT91C_CAN_MB1_MSR (0xFFFD0230) // (CAN_MB1) MailBox Status Register -#define AT91C_CAN_MB1_MAM (0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register -#define AT91C_CAN_MB1_MDH (0xFFFD0238) // (CAN_MB1) MailBox Data High Register -#define AT91C_CAN_MB1_MCR (0xFFFD023C) // (CAN_MB1) MailBox Control Register -#define AT91C_CAN_MB1_MFID (0xFFFD022C) // (CAN_MB1) MailBox Family ID Register -// ========== Register definition for CAN_MB2 peripheral ========== -#define AT91C_CAN_MB2_MCR (0xFFFD025C) // (CAN_MB2) MailBox Control Register -#define AT91C_CAN_MB2_MDH (0xFFFD0258) // (CAN_MB2) MailBox Data High Register -#define AT91C_CAN_MB2_MID (0xFFFD0248) // (CAN_MB2) MailBox ID Register -#define AT91C_CAN_MB2_MDL (0xFFFD0254) // (CAN_MB2) MailBox Data Low Register -#define AT91C_CAN_MB2_MMR (0xFFFD0240) // (CAN_MB2) MailBox Mode Register -#define AT91C_CAN_MB2_MAM (0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register -#define AT91C_CAN_MB2_MFID (0xFFFD024C) // (CAN_MB2) MailBox Family ID Register -#define AT91C_CAN_MB2_MSR (0xFFFD0250) // (CAN_MB2) MailBox Status Register -// ========== Register definition for CAN_MB3 peripheral ========== -#define AT91C_CAN_MB3_MFID (0xFFFD026C) // (CAN_MB3) MailBox Family ID Register -#define AT91C_CAN_MB3_MAM (0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register -#define AT91C_CAN_MB3_MID (0xFFFD0268) // (CAN_MB3) MailBox ID Register -#define AT91C_CAN_MB3_MCR (0xFFFD027C) // (CAN_MB3) MailBox Control Register -#define AT91C_CAN_MB3_MMR (0xFFFD0260) // (CAN_MB3) MailBox Mode Register -#define AT91C_CAN_MB3_MSR (0xFFFD0270) // (CAN_MB3) MailBox Status Register -#define AT91C_CAN_MB3_MDL (0xFFFD0274) // (CAN_MB3) MailBox Data Low Register -#define AT91C_CAN_MB3_MDH (0xFFFD0278) // (CAN_MB3) MailBox Data High Register -// ========== Register definition for CAN_MB4 peripheral ========== -#define AT91C_CAN_MB4_MID (0xFFFD0288) // (CAN_MB4) MailBox ID Register -#define AT91C_CAN_MB4_MMR (0xFFFD0280) // (CAN_MB4) MailBox Mode Register -#define AT91C_CAN_MB4_MDH (0xFFFD0298) // (CAN_MB4) MailBox Data High Register -#define AT91C_CAN_MB4_MFID (0xFFFD028C) // (CAN_MB4) MailBox Family ID Register -#define AT91C_CAN_MB4_MSR (0xFFFD0290) // (CAN_MB4) MailBox Status Register -#define AT91C_CAN_MB4_MCR (0xFFFD029C) // (CAN_MB4) MailBox Control Register -#define AT91C_CAN_MB4_MDL (0xFFFD0294) // (CAN_MB4) MailBox Data Low Register -#define AT91C_CAN_MB4_MAM (0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register -// ========== Register definition for CAN_MB5 peripheral ========== -#define AT91C_CAN_MB5_MSR (0xFFFD02B0) // (CAN_MB5) MailBox Status Register -#define AT91C_CAN_MB5_MCR (0xFFFD02BC) // (CAN_MB5) MailBox Control Register -#define AT91C_CAN_MB5_MFID (0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register -#define AT91C_CAN_MB5_MDH (0xFFFD02B8) // (CAN_MB5) MailBox Data High Register -#define AT91C_CAN_MB5_MID (0xFFFD02A8) // (CAN_MB5) MailBox ID Register -#define AT91C_CAN_MB5_MMR (0xFFFD02A0) // (CAN_MB5) MailBox Mode Register -#define AT91C_CAN_MB5_MDL (0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register -#define AT91C_CAN_MB5_MAM (0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register -// ========== Register definition for CAN_MB6 peripheral ========== -#define AT91C_CAN_MB6_MFID (0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register -#define AT91C_CAN_MB6_MID (0xFFFD02C8) // (CAN_MB6) MailBox ID Register -#define AT91C_CAN_MB6_MAM (0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register -#define AT91C_CAN_MB6_MSR (0xFFFD02D0) // (CAN_MB6) MailBox Status Register -#define AT91C_CAN_MB6_MDL (0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register -#define AT91C_CAN_MB6_MCR (0xFFFD02DC) // (CAN_MB6) MailBox Control Register -#define AT91C_CAN_MB6_MDH (0xFFFD02D8) // (CAN_MB6) MailBox Data High Register -#define AT91C_CAN_MB6_MMR (0xFFFD02C0) // (CAN_MB6) MailBox Mode Register -// ========== Register definition for CAN_MB7 peripheral ========== -#define AT91C_CAN_MB7_MCR (0xFFFD02FC) // (CAN_MB7) MailBox Control Register -#define AT91C_CAN_MB7_MDH (0xFFFD02F8) // (CAN_MB7) MailBox Data High Register -#define AT91C_CAN_MB7_MFID (0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register -#define AT91C_CAN_MB7_MDL (0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register -#define AT91C_CAN_MB7_MID (0xFFFD02E8) // (CAN_MB7) MailBox ID Register -#define AT91C_CAN_MB7_MMR (0xFFFD02E0) // (CAN_MB7) MailBox Mode Register -#define AT91C_CAN_MB7_MAM (0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register -#define AT91C_CAN_MB7_MSR (0xFFFD02F0) // (CAN_MB7) MailBox Status Register -// ========== Register definition for CAN peripheral ========== -#define AT91C_CAN_TCR (0xFFFD0024) // (CAN) Transfer Command Register -#define AT91C_CAN_IMR (0xFFFD000C) // (CAN) Interrupt Mask Register -#define AT91C_CAN_IER (0xFFFD0004) // (CAN) Interrupt Enable Register -#define AT91C_CAN_ECR (0xFFFD0020) // (CAN) Error Counter Register -#define AT91C_CAN_TIMESTP (0xFFFD001C) // (CAN) Time Stamp Register -#define AT91C_CAN_MR (0xFFFD0000) // (CAN) Mode Register -#define AT91C_CAN_IDR (0xFFFD0008) // (CAN) Interrupt Disable Register -#define AT91C_CAN_ACR (0xFFFD0028) // (CAN) Abort Command Register -#define AT91C_CAN_TIM (0xFFFD0018) // (CAN) Timer Register -#define AT91C_CAN_SR (0xFFFD0010) // (CAN) Status Register -#define AT91C_CAN_BR (0xFFFD0014) // (CAN) Baudrate Register -#define AT91C_CAN_VR (0xFFFD00FC) // (CAN) Version Register -// ========== Register definition for EMAC peripheral ========== -#define AT91C_EMAC_ISR (0xFFFDC024) // (EMAC) Interrupt Status Register -#define AT91C_EMAC_SA4H (0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes -#define AT91C_EMAC_SA1L (0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes -#define AT91C_EMAC_ELE (0xFFFDC078) // (EMAC) Excessive Length Errors Register -#define AT91C_EMAC_LCOL (0xFFFDC05C) // (EMAC) Late Collision Register -#define AT91C_EMAC_RLE (0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register -#define AT91C_EMAC_WOL (0xFFFDC0C4) // (EMAC) Wake On LAN Register -#define AT91C_EMAC_DTF (0xFFFDC058) // (EMAC) Deferred Transmission Frame Register -#define AT91C_EMAC_TUND (0xFFFDC064) // (EMAC) Transmit Underrun Error Register -#define AT91C_EMAC_NCR (0xFFFDC000) // (EMAC) Network Control Register -#define AT91C_EMAC_SA4L (0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes -#define AT91C_EMAC_RSR (0xFFFDC020) // (EMAC) Receive Status Register -#define AT91C_EMAC_SA3L (0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes -#define AT91C_EMAC_TSR (0xFFFDC014) // (EMAC) Transmit Status Register -#define AT91C_EMAC_IDR (0xFFFDC02C) // (EMAC) Interrupt Disable Register -#define AT91C_EMAC_RSE (0xFFFDC074) // (EMAC) Receive Symbol Errors Register -#define AT91C_EMAC_ECOL (0xFFFDC060) // (EMAC) Excessive Collision Register -#define AT91C_EMAC_TID (0xFFFDC0B8) // (EMAC) Type ID Checking Register -#define AT91C_EMAC_HRB (0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] -#define AT91C_EMAC_TBQP (0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer -#define AT91C_EMAC_USRIO (0xFFFDC0C0) // (EMAC) USER Input/Output Register -#define AT91C_EMAC_PTR (0xFFFDC038) // (EMAC) Pause Time Register -#define AT91C_EMAC_SA2H (0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes -#define AT91C_EMAC_ROV (0xFFFDC070) // (EMAC) Receive Overrun Errors Register -#define AT91C_EMAC_ALE (0xFFFDC054) // (EMAC) Alignment Error Register -#define AT91C_EMAC_RJA (0xFFFDC07C) // (EMAC) Receive Jabbers Register -#define AT91C_EMAC_RBQP (0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer -#define AT91C_EMAC_TPF (0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register -#define AT91C_EMAC_NCFGR (0xFFFDC004) // (EMAC) Network Configuration Register -#define AT91C_EMAC_HRT (0xFFFDC094) // (EMAC) Hash Address Top[63:32] -#define AT91C_EMAC_USF (0xFFFDC080) // (EMAC) Undersize Frames Register -#define AT91C_EMAC_FCSE (0xFFFDC050) // (EMAC) Frame Check Sequence Error Register -#define AT91C_EMAC_TPQ (0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register -#define AT91C_EMAC_MAN (0xFFFDC034) // (EMAC) PHY Maintenance Register -#define AT91C_EMAC_FTO (0xFFFDC040) // (EMAC) Frames Transmitted OK Register -#define AT91C_EMAC_REV (0xFFFDC0FC) // (EMAC) Revision Register -#define AT91C_EMAC_IMR (0xFFFDC030) // (EMAC) Interrupt Mask Register -#define AT91C_EMAC_SCF (0xFFFDC044) // (EMAC) Single Collision Frame Register -#define AT91C_EMAC_PFR (0xFFFDC03C) // (EMAC) Pause Frames received Register -#define AT91C_EMAC_MCF (0xFFFDC048) // (EMAC) Multiple Collision Frame Register -#define AT91C_EMAC_NSR (0xFFFDC008) // (EMAC) Network Status Register -#define AT91C_EMAC_SA2L (0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes -#define AT91C_EMAC_FRO (0xFFFDC04C) // (EMAC) Frames Received OK Register -#define AT91C_EMAC_IER (0xFFFDC028) // (EMAC) Interrupt Enable Register -#define AT91C_EMAC_SA1H (0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes -#define AT91C_EMAC_CSE (0xFFFDC068) // (EMAC) Carrier Sense Error Register -#define AT91C_EMAC_SA3H (0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes -#define AT91C_EMAC_RRE (0xFFFDC06C) // (EMAC) Receive Ressource Error Register -#define AT91C_EMAC_STE (0xFFFDC084) // (EMAC) SQE Test Error Register -// ========== Register definition for PDC_ADC peripheral ========== -#define AT91C_ADC_PTSR (0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register -#define AT91C_ADC_PTCR (0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register -#define AT91C_ADC_TNPR (0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register -#define AT91C_ADC_TNCR (0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register -#define AT91C_ADC_RNPR (0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register -#define AT91C_ADC_RNCR (0xFFFD8114) // (PDC_ADC) Receive Next Counter Register -#define AT91C_ADC_RPR (0xFFFD8100) // (PDC_ADC) Receive Pointer Register -#define AT91C_ADC_TCR (0xFFFD810C) // (PDC_ADC) Transmit Counter Register -#define AT91C_ADC_TPR (0xFFFD8108) // (PDC_ADC) Transmit Pointer Register -#define AT91C_ADC_RCR (0xFFFD8104) // (PDC_ADC) Receive Counter Register -// ========== Register definition for ADC peripheral ========== -#define AT91C_ADC_CDR2 (0xFFFD8038) // (ADC) ADC Channel Data Register 2 -#define AT91C_ADC_CDR3 (0xFFFD803C) // (ADC) ADC Channel Data Register 3 -#define AT91C_ADC_CDR0 (0xFFFD8030) // (ADC) ADC Channel Data Register 0 -#define AT91C_ADC_CDR5 (0xFFFD8044) // (ADC) ADC Channel Data Register 5 -#define AT91C_ADC_CHDR (0xFFFD8014) // (ADC) ADC Channel Disable Register -#define AT91C_ADC_SR (0xFFFD801C) // (ADC) ADC Status Register -#define AT91C_ADC_CDR4 (0xFFFD8040) // (ADC) ADC Channel Data Register 4 -#define AT91C_ADC_CDR1 (0xFFFD8034) // (ADC) ADC Channel Data Register 1 -#define AT91C_ADC_LCDR (0xFFFD8020) // (ADC) ADC Last Converted Data Register -#define AT91C_ADC_IDR (0xFFFD8028) // (ADC) ADC Interrupt Disable Register -#define AT91C_ADC_CR (0xFFFD8000) // (ADC) ADC Control Register -#define AT91C_ADC_CDR7 (0xFFFD804C) // (ADC) ADC Channel Data Register 7 -#define AT91C_ADC_CDR6 (0xFFFD8048) // (ADC) ADC Channel Data Register 6 -#define AT91C_ADC_IER (0xFFFD8024) // (ADC) ADC Interrupt Enable Register -#define AT91C_ADC_CHER (0xFFFD8010) // (ADC) ADC Channel Enable Register -#define AT91C_ADC_CHSR (0xFFFD8018) // (ADC) ADC Channel Status Register -#define AT91C_ADC_MR (0xFFFD8004) // (ADC) ADC Mode Register -#define AT91C_ADC_IMR (0xFFFD802C) // (ADC) ADC Interrupt Mask Register -// ========== Register definition for PDC_AES peripheral ========== -#define AT91C_AES_TPR (0xFFFA4108) // (PDC_AES) Transmit Pointer Register -#define AT91C_AES_PTCR (0xFFFA4120) // (PDC_AES) PDC Transfer Control Register -#define AT91C_AES_RNPR (0xFFFA4110) // (PDC_AES) Receive Next Pointer Register -#define AT91C_AES_TNCR (0xFFFA411C) // (PDC_AES) Transmit Next Counter Register -#define AT91C_AES_TCR (0xFFFA410C) // (PDC_AES) Transmit Counter Register -#define AT91C_AES_RCR (0xFFFA4104) // (PDC_AES) Receive Counter Register -#define AT91C_AES_RNCR (0xFFFA4114) // (PDC_AES) Receive Next Counter Register -#define AT91C_AES_TNPR (0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register -#define AT91C_AES_RPR (0xFFFA4100) // (PDC_AES) Receive Pointer Register -#define AT91C_AES_PTSR (0xFFFA4124) // (PDC_AES) PDC Transfer Status Register -// ========== Register definition for AES peripheral ========== -#define AT91C_AES_IVxR (0xFFFA4060) // (AES) Initialization Vector x Register -#define AT91C_AES_MR (0xFFFA4004) // (AES) Mode Register -#define AT91C_AES_VR (0xFFFA40FC) // (AES) AES Version Register -#define AT91C_AES_ODATAxR (0xFFFA4050) // (AES) Output Data x Register -#define AT91C_AES_IDATAxR (0xFFFA4040) // (AES) Input Data x Register -#define AT91C_AES_CR (0xFFFA4000) // (AES) Control Register -#define AT91C_AES_IDR (0xFFFA4014) // (AES) Interrupt Disable Register -#define AT91C_AES_IMR (0xFFFA4018) // (AES) Interrupt Mask Register -#define AT91C_AES_IER (0xFFFA4010) // (AES) Interrupt Enable Register -#define AT91C_AES_KEYWxR (0xFFFA4020) // (AES) Key Word x Register -#define AT91C_AES_ISR (0xFFFA401C) // (AES) Interrupt Status Register -// ========== Register definition for PDC_TDES peripheral ========== -#define AT91C_TDES_RNCR (0xFFFA8114) // (PDC_TDES) Receive Next Counter Register -#define AT91C_TDES_TCR (0xFFFA810C) // (PDC_TDES) Transmit Counter Register -#define AT91C_TDES_RCR (0xFFFA8104) // (PDC_TDES) Receive Counter Register -#define AT91C_TDES_TNPR (0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register -#define AT91C_TDES_RNPR (0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register -#define AT91C_TDES_RPR (0xFFFA8100) // (PDC_TDES) Receive Pointer Register -#define AT91C_TDES_TNCR (0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register -#define AT91C_TDES_TPR (0xFFFA8108) // (PDC_TDES) Transmit Pointer Register -#define AT91C_TDES_PTSR (0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register -#define AT91C_TDES_PTCR (0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register -// ========== Register definition for TDES peripheral ========== -#define AT91C_TDES_KEY2WxR (0xFFFA8028) // (TDES) Key 2 Word x Register -#define AT91C_TDES_KEY3WxR (0xFFFA8030) // (TDES) Key 3 Word x Register -#define AT91C_TDES_IDR (0xFFFA8014) // (TDES) Interrupt Disable Register -#define AT91C_TDES_VR (0xFFFA80FC) // (TDES) TDES Version Register -#define AT91C_TDES_IVxR (0xFFFA8060) // (TDES) Initialization Vector x Register -#define AT91C_TDES_ODATAxR (0xFFFA8050) // (TDES) Output Data x Register -#define AT91C_TDES_IMR (0xFFFA8018) // (TDES) Interrupt Mask Register -#define AT91C_TDES_MR (0xFFFA8004) // (TDES) Mode Register -#define AT91C_TDES_CR (0xFFFA8000) // (TDES) Control Register -#define AT91C_TDES_IER (0xFFFA8010) // (TDES) Interrupt Enable Register -#define AT91C_TDES_ISR (0xFFFA801C) // (TDES) Interrupt Status Register -#define AT91C_TDES_IDATAxR (0xFFFA8040) // (TDES) Input Data x Register -#define AT91C_TDES_KEY1WxR (0xFFFA8020) // (TDES) Key 1 Word x Register - -// ***************************************************************************** -// PIO DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 -#define AT91C_PA0_RXD0 (AT91C_PIO_PA0) // USART 0 Receive Data -#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 -#define AT91C_PA1_TXD0 (AT91C_PIO_PA1) // USART 0 Transmit Data -#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 -#define AT91C_PA10_TWD (AT91C_PIO_PA10) // TWI Two-wire Serial Data -#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 -#define AT91C_PA11_TWCK (AT91C_PIO_PA11) // TWI Two-wire Serial Clock -#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 -#define AT91C_PA12_NPCS00 (AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 -#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 -#define AT91C_PA13_NPCS01 (AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PA13_PCK1 (AT91C_PIO_PA13) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 -#define AT91C_PA14_NPCS02 (AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PA14_IRQ1 (AT91C_PIO_PA14) // External Interrupt 1 -#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 -#define AT91C_PA15_NPCS03 (AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PA15_TCLK2 (AT91C_PIO_PA15) // Timer Counter 2 external clock input -#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 -#define AT91C_PA16_MISO0 (AT91C_PIO_PA16) // SPI 0 Master In Slave -#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 -#define AT91C_PA17_MOSI0 (AT91C_PIO_PA17) // SPI 0 Master Out Slave -#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 -#define AT91C_PA18_SPCK0 (AT91C_PIO_PA18) // SPI 0 Serial Clock -#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 -#define AT91C_PA19_CANRX (AT91C_PIO_PA19) // CAN Receive -#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 -#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock -#define AT91C_PA2_NPCS11 (AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 -#define AT91C_PA20_CANTX (AT91C_PIO_PA20) // CAN Transmit -#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 -#define AT91C_PA21_TF (AT91C_PIO_PA21) // SSC Transmit Frame Sync -#define AT91C_PA21_NPCS10 (AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 -#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 -#define AT91C_PA22_TK (AT91C_PIO_PA22) // SSC Transmit Clock -#define AT91C_PA22_SPCK1 (AT91C_PIO_PA22) // SPI 1 Serial Clock -#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 -#define AT91C_PA23_TD (AT91C_PIO_PA23) // SSC Transmit data -#define AT91C_PA23_MOSI1 (AT91C_PIO_PA23) // SPI 1 Master Out Slave -#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 -#define AT91C_PA24_RD (AT91C_PIO_PA24) // SSC Receive Data -#define AT91C_PA24_MISO1 (AT91C_PIO_PA24) // SPI 1 Master In Slave -#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 -#define AT91C_PA25_RK (AT91C_PIO_PA25) // SSC Receive Clock -#define AT91C_PA25_NPCS11 (AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 -#define AT91C_PA26_RF (AT91C_PIO_PA26) // SSC Receive Frame Sync -#define AT91C_PA26_NPCS12 (AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 -#define AT91C_PA27_DRXD (AT91C_PIO_PA27) // DBGU Debug Receive Data -#define AT91C_PA27_PCK3 (AT91C_PIO_PA27) // PMC Programmable Clock Output 3 -#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 -#define AT91C_PA28_DTXD (AT91C_PIO_PA28) // DBGU Debug Transmit Data -#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 -#define AT91C_PA29_FIQ (AT91C_PIO_PA29) // AIC Fast Interrupt Input -#define AT91C_PA29_NPCS13 (AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 -#define AT91C_PA3_RTS0 (AT91C_PIO_PA3) // USART 0 Ready To Send -#define AT91C_PA3_NPCS12 (AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 -#define AT91C_PA30_IRQ0 (AT91C_PIO_PA30) // External Interrupt 0 -#define AT91C_PA30_PCK2 (AT91C_PIO_PA30) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 -#define AT91C_PA4_CTS0 (AT91C_PIO_PA4) // USART 0 Clear To Send -#define AT91C_PA4_NPCS13 (AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 -#define AT91C_PA5_RXD1 (AT91C_PIO_PA5) // USART 1 Receive Data -#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 -#define AT91C_PA6_TXD1 (AT91C_PIO_PA6) // USART 1 Transmit Data -#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 -#define AT91C_PA7_SCK1 (AT91C_PIO_PA7) // USART 1 Serial Clock -#define AT91C_PA7_NPCS01 (AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 -#define AT91C_PA8_RTS1 (AT91C_PIO_PA8) // USART 1 Ready To Send -#define AT91C_PA8_NPCS02 (AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 -#define AT91C_PA9_CTS1 (AT91C_PIO_PA9) // USART 1 Clear To Send -#define AT91C_PA9_NPCS03 (AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0 -#define AT91C_PB0_ETXCK_EREFCK (AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock -#define AT91C_PB0_PCK0 (AT91C_PIO_PB0) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1 -#define AT91C_PB1_ETXEN (AT91C_PIO_PB1) // Ethernet MAC Transmit Enable -#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10 -#define AT91C_PB10_ETX2 (AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 -#define AT91C_PB10_NPCS11 (AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11 -#define AT91C_PB11_ETX3 (AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 -#define AT91C_PB11_NPCS12 (AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12 -#define AT91C_PB12_ETXER (AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error -#define AT91C_PB12_TCLK0 (AT91C_PIO_PB12) // Timer Counter 0 external clock input -#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13 -#define AT91C_PB13_ERX2 (AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 -#define AT91C_PB13_NPCS01 (AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14 -#define AT91C_PB14_ERX3 (AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 -#define AT91C_PB14_NPCS02 (AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15 -#define AT91C_PB15_ERXDV (AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid -#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16 -#define AT91C_PB16_ECOL (AT91C_PIO_PB16) // Ethernet MAC Collision Detected -#define AT91C_PB16_NPCS13 (AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17 -#define AT91C_PB17_ERXCK (AT91C_PIO_PB17) // Ethernet MAC Receive Clock -#define AT91C_PB17_NPCS03 (AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18 -#define AT91C_PB18_EF100 (AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec -#define AT91C_PB18_ADTRG (AT91C_PIO_PB18) // ADC External Trigger -#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19 -#define AT91C_PB19_PWM0 (AT91C_PIO_PB19) // PWM Channel 0 -#define AT91C_PB19_TCLK1 (AT91C_PIO_PB19) // Timer Counter 1 external clock input -#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2 -#define AT91C_PB2_ETX0 (AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 -#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20 -#define AT91C_PB20_PWM1 (AT91C_PIO_PB20) // PWM Channel 1 -#define AT91C_PB20_PCK0 (AT91C_PIO_PB20) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21 -#define AT91C_PB21_PWM2 (AT91C_PIO_PB21) // PWM Channel 2 -#define AT91C_PB21_PCK1 (AT91C_PIO_PB21) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22 -#define AT91C_PB22_PWM3 (AT91C_PIO_PB22) // PWM Channel 3 -#define AT91C_PB22_PCK2 (AT91C_PIO_PB22) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23 -#define AT91C_PB23_TIOA0 (AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A -#define AT91C_PB23_DCD1 (AT91C_PIO_PB23) // USART 1 Data Carrier Detect -#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24 -#define AT91C_PB24_TIOB0 (AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B -#define AT91C_PB24_DSR1 (AT91C_PIO_PB24) // USART 1 Data Set ready -#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25 -#define AT91C_PB25_TIOA1 (AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A -#define AT91C_PB25_DTR1 (AT91C_PIO_PB25) // USART 1 Data Terminal ready -#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26 -#define AT91C_PB26_TIOB1 (AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B -#define AT91C_PB26_RI1 (AT91C_PIO_PB26) // USART 1 Ring Indicator -#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27 -#define AT91C_PB27_TIOA2 (AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A -#define AT91C_PB27_PWM0 (AT91C_PIO_PB27) // PWM Channel 0 -#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28 -#define AT91C_PB28_TIOB2 (AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B -#define AT91C_PB28_PWM1 (AT91C_PIO_PB28) // PWM Channel 1 -#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29 -#define AT91C_PB29_PCK1 (AT91C_PIO_PB29) // PMC Programmable Clock Output 1 -#define AT91C_PB29_PWM2 (AT91C_PIO_PB29) // PWM Channel 2 -#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3 -#define AT91C_PB3_ETX1 (AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 -#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30 -#define AT91C_PB30_PCK2 (AT91C_PIO_PB30) // PMC Programmable Clock Output 2 -#define AT91C_PB30_PWM3 (AT91C_PIO_PB30) // PWM Channel 3 -#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4 -#define AT91C_PB4_ECRS_ECRSDV (AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid -#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5 -#define AT91C_PB5_ERX0 (AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 -#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6 -#define AT91C_PB6_ERX1 (AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 -#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7 -#define AT91C_PB7_ERXER (AT91C_PIO_PB7) // Ethernet MAC Receive Error -#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8 -#define AT91C_PB8_EMDC (AT91C_PIO_PB8) // Ethernet MAC Management Data Clock -#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9 -#define AT91C_PB9_EMDIO (AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output - -// ***************************************************************************** -// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) -#define AT91C_ID_SYS ( 1) // System Peripheral -#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A -#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B -#define AT91C_ID_SPI0 ( 4) // Serial Peripheral Interface 0 -#define AT91C_ID_SPI1 ( 5) // Serial Peripheral Interface 1 -#define AT91C_ID_US0 ( 6) // USART 0 -#define AT91C_ID_US1 ( 7) // USART 1 -#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller -#define AT91C_ID_TWI ( 9) // Two-Wire Interface -#define AT91C_ID_PWMC (10) // PWM Controller -#define AT91C_ID_UDP (11) // USB Device Port -#define AT91C_ID_TC0 (12) // Timer Counter 0 -#define AT91C_ID_TC1 (13) // Timer Counter 1 -#define AT91C_ID_TC2 (14) // Timer Counter 2 -#define AT91C_ID_CAN (15) // Control Area Network Controller -#define AT91C_ID_EMAC (16) // Ethernet MAC -#define AT91C_ID_ADC (17) // Analog-to-Digital Converter -#define AT91C_ID_AES (18) // Advanced Encryption Standard 128-bit -#define AT91C_ID_TDES (19) // Triple Data Encryption Standard -#define AT91C_ID_20_Reserved (20) // Reserved -#define AT91C_ID_21_Reserved (21) // Reserved -#define AT91C_ID_22_Reserved (22) // Reserved -#define AT91C_ID_23_Reserved (23) // Reserved -#define AT91C_ID_24_Reserved (24) // Reserved -#define AT91C_ID_25_Reserved (25) // Reserved -#define AT91C_ID_26_Reserved (26) // Reserved -#define AT91C_ID_27_Reserved (27) // Reserved -#define AT91C_ID_28_Reserved (28) // Reserved -#define AT91C_ID_29_Reserved (29) // Reserved -#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) -#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) - -// ***************************************************************************** -// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_BASE_SYS (0xFFFFF000) // (SYS) Base Address -#define AT91C_BASE_AIC (0xFFFFF000) // (AIC) Base Address -#define AT91C_BASE_PDC_DBGU (0xFFFFF300) // (PDC_DBGU) Base Address -#define AT91C_BASE_DBGU (0xFFFFF200) // (DBGU) Base Address -#define AT91C_BASE_PIOA (0xFFFFF400) // (PIOA) Base Address -#define AT91C_BASE_PIOB (0xFFFFF600) // (PIOB) Base Address -#define AT91C_BASE_CKGR (0xFFFFFC20) // (CKGR) Base Address -#define AT91C_BASE_PMC (0xFFFFFC00) // (PMC) Base Address -#define AT91C_BASE_RSTC (0xFFFFFD00) // (RSTC) Base Address -#define AT91C_BASE_RTTC (0xFFFFFD20) // (RTTC) Base Address -#define AT91C_BASE_PITC (0xFFFFFD30) // (PITC) Base Address -#define AT91C_BASE_WDTC (0xFFFFFD40) // (WDTC) Base Address -#define AT91C_BASE_VREG (0xFFFFFD60) // (VREG) Base Address -#define AT91C_BASE_MC (0xFFFFFF00) // (MC) Base Address -#define AT91C_BASE_PDC_SPI1 (0xFFFE4100) // (PDC_SPI1) Base Address -#define AT91C_BASE_SPI1 (0xFFFE4000) // (SPI1) Base Address -#define AT91C_BASE_PDC_SPI0 (0xFFFE0100) // (PDC_SPI0) Base Address -#define AT91C_BASE_SPI0 (0xFFFE0000) // (SPI0) Base Address -#define AT91C_BASE_PDC_US1 (0xFFFC4100) // (PDC_US1) Base Address -#define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address -#define AT91C_BASE_PDC_US0 (0xFFFC0100) // (PDC_US0) Base Address -#define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address -#define AT91C_BASE_PDC_SSC (0xFFFD4100) // (PDC_SSC) Base Address -#define AT91C_BASE_SSC (0xFFFD4000) // (SSC) Base Address -#define AT91C_BASE_TWI (0xFFFB8000) // (TWI) Base Address -#define AT91C_BASE_PWMC_CH3 (0xFFFCC260) // (PWMC_CH3) Base Address -#define AT91C_BASE_PWMC_CH2 (0xFFFCC240) // (PWMC_CH2) Base Address -#define AT91C_BASE_PWMC_CH1 (0xFFFCC220) // (PWMC_CH1) Base Address -#define AT91C_BASE_PWMC_CH0 (0xFFFCC200) // (PWMC_CH0) Base Address -#define AT91C_BASE_PWMC (0xFFFCC000) // (PWMC) Base Address -#define AT91C_BASE_UDP (0xFFFB0000) // (UDP) Base Address -#define AT91C_BASE_TC0 (0xFFFA0000) // (TC0) Base Address -#define AT91C_BASE_TC1 (0xFFFA0040) // (TC1) Base Address -#define AT91C_BASE_TC2 (0xFFFA0080) // (TC2) Base Address -#define AT91C_BASE_TCB (0xFFFA0000) // (TCB) Base Address -#define AT91C_BASE_CAN_MB0 (0xFFFD0200) // (CAN_MB0) Base Address -#define AT91C_BASE_CAN_MB1 (0xFFFD0220) // (CAN_MB1) Base Address -#define AT91C_BASE_CAN_MB2 (0xFFFD0240) // (CAN_MB2) Base Address -#define AT91C_BASE_CAN_MB3 (0xFFFD0260) // (CAN_MB3) Base Address -#define AT91C_BASE_CAN_MB4 (0xFFFD0280) // (CAN_MB4) Base Address -#define AT91C_BASE_CAN_MB5 (0xFFFD02A0) // (CAN_MB5) Base Address -#define AT91C_BASE_CAN_MB6 (0xFFFD02C0) // (CAN_MB6) Base Address -#define AT91C_BASE_CAN_MB7 (0xFFFD02E0) // (CAN_MB7) Base Address -#define AT91C_BASE_CAN (0xFFFD0000) // (CAN) Base Address -#define AT91C_BASE_EMAC (0xFFFDC000) // (EMAC) Base Address -#define AT91C_BASE_PDC_ADC (0xFFFD8100) // (PDC_ADC) Base Address -#define AT91C_BASE_ADC (0xFFFD8000) // (ADC) Base Address -#define AT91C_BASE_PDC_AES (0xFFFA4100) // (PDC_AES) Base Address -#define AT91C_BASE_AES (0xFFFA4000) // (AES) Base Address -#define AT91C_BASE_PDC_TDES (0xFFFA8100) // (PDC_TDES) Base Address -#define AT91C_BASE_TDES (0xFFFA8000) // (TDES) Base Address - -// ***************************************************************************** -// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_ISRAM (0x00200000) // Internal SRAM base address -#define AT91C_ISRAM_SIZE (0x00010000) // Internal SRAM size in byte (64 Kbyte) -#define AT91C_IFLASH (0x00100000) // Internal ROM base address -#define AT91C_IFLASH_SIZE (0x00040000) // Internal ROM size in byte (256 Kbyte) - - diff --git a/Source/portable/IAR/AtmelSAM7S64/ISR_Support.h b/Source/portable/IAR/AtmelSAM7S64/ISR_Support.h deleted file mode 100644 index 4a32f3976..000000000 --- a/Source/portable/IAR/AtmelSAM7S64/ISR_Support.h +++ /dev/null @@ -1,78 +0,0 @@ - EXTERN pxCurrentTCB - EXTERN ulCriticalNesting - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Context save and restore macro definitions -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - -portSAVE_CONTEXT MACRO - - ; Push R0 as we are going to use the register. - STMDB SP!, {R0} - - ; Set R0 to point to the task stack pointer. - STMDB SP, {SP}^ - NOP - SUB SP, SP, #4 - LDMIA SP!, {R0} - - ; Push the return address onto the stack. - STMDB R0!, {LR} - - ; Now we have saved LR we can use it instead of R0. - MOV LR, R0 - - ; Pop R0 so we can save it onto the system mode stack. - LDMIA SP!, {R0} - - ; Push all the system mode registers onto the task stack. - STMDB LR, {R0-LR}^ - NOP - SUB LR, LR, #60 - - ; Push the SPSR onto the task stack. - MRS R0, SPSR - STMDB LR!, {R0} - - LDR R0, =ulCriticalNesting - LDR R0, [R0] - STMDB LR!, {R0} - - ; Store the new top of stack for the task. - LDR R1, =pxCurrentTCB - LDR R0, [R1] - STR LR, [R0] - - ENDM - - -portRESTORE_CONTEXT MACRO - - ; Set the LR to the task stack. - LDR R1, =pxCurrentTCB - LDR R0, [R1] - LDR LR, [R0] - - ; The critical nesting depth is the first item on the stack. - ; Load it into the ulCriticalNesting variable. - LDR R0, =ulCriticalNesting - LDMFD LR!, {R1} - STR R1, [R0] - - ; Get the SPSR from the stack. - LDMFD LR!, {R0} - MSR SPSR_cxsf, R0 - - ; Restore all system mode registers for the task. - LDMFD LR, {R0-R14}^ - NOP - - ; Restore the return address. - LDR LR, [LR, #+60] - - ; And return - correcting the offset in the LR to obtain the - ; correct address. - SUBS PC, LR, #4 - - ENDM - diff --git a/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h b/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h deleted file mode 100644 index 9d012c4d7..000000000 --- a/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h +++ /dev/null @@ -1,3265 +0,0 @@ -//*---------------------------------------------------------------------------- -//* ATMEL Microcontroller Software Support - ROUSSET - -//*---------------------------------------------------------------------------- -//* The software is delivered "AS IS" without warranty or condition of any -//* kind, either express, implied or statutory. This includes without -//* limitation any warranty or condition with respect to merchantability or -//* fitness for any particular purpose, or against the infringements of -//* intellectual property rights of others. -//*---------------------------------------------------------------------------- -//* File Name : lib_AT91SAM7S64.h -//* Object : AT91SAM7S64 inlined functions -//* Generated : AT91 SW Application Group 07/16/2004 (07:43:09) -//* -//* CVS Reference : /lib_MC_SAM.h/1.3/Thu Mar 25 15:19:14 2004// -//* CVS Reference : /lib_pdc_1363d.h/1.2/Wed Feb 19 09:25:22 2003// -//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// -//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// -//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 13:23:52 2003// -//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// -//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// -//* CVS Reference : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004// -//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 08:12:38 2003// -//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// -//* CVS Reference : /lib_twi.h/1.2/Fri Jan 31 12:19:38 2003// -//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// -//* CVS Reference : /lib_udp.h/1.3/Fri Jan 31 12:19:48 2003// -//* CVS Reference : /lib_aic.h/1.3/Fri Jul 12 07:46:12 2002// -//*---------------------------------------------------------------------------- - -#ifndef lib_AT91SAM7S64_H -#define lib_AT91SAM7S64_H - -/* ***************************************************************************** - SOFTWARE API FOR MC - ***************************************************************************** */ - -#define AT91C_MC_CORRECT_KEY ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_Remap -//* \brief Make Remap -//*---------------------------------------------------------------------------- -__inline void AT91F_MC_Remap (void) // -{ - AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC; - - pMC->MC_RCR = AT91C_MC_RCB; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_CfgModeReg -//* \brief Configure the EFC Mode Register of the MC controller -//*---------------------------------------------------------------------------- -__inline void AT91F_MC_EFC_CfgModeReg ( - AT91PS_MC pMC, // pointer to a MC controller - unsigned int mode) // mode register -{ - // Write to the FMR register - pMC->MC_FMR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_GetModeReg -//* \brief Return MC EFC Mode Regsiter -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MC_EFC_GetModeReg( - AT91PS_MC pMC) // pointer to a MC controller -{ - return pMC->MC_FMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_ComputeFMCN -//* \brief Return MC EFC Mode Regsiter -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MC_EFC_ComputeFMCN( - int master_clock) // master clock in Hz -{ - return (master_clock/1000000 +2); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_PerformCmd -//* \brief Perform EFC Command -//*---------------------------------------------------------------------------- -__inline void AT91F_MC_EFC_PerformCmd ( - AT91PS_MC pMC, // pointer to a MC controller - unsigned int transfer_cmd) -{ - pMC->MC_FCR = transfer_cmd; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_GetStatus -//* \brief Return MC EFC Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MC_EFC_GetStatus( - AT91PS_MC pMC) // pointer to a MC controller -{ - return pMC->MC_FSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_IsInterruptMasked -//* \brief Test if EFC MC Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MC_EFC_IsInterruptMasked( - AT91PS_MC pMC, // \arg pointer to a MC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_MC_EFC_GetModeReg(pMC) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_IsInterruptSet -//* \brief Test if EFC MC Interrupt is Set -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MC_EFC_IsInterruptSet( - AT91PS_MC pMC, // \arg pointer to a MC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_MC_EFC_GetStatus(pMC) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR PDC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetNextRx -//* \brief Set the next receive transfer descriptor -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_SetNextRx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be received - unsigned int bytes) // \arg number of bytes to be received -{ - pPDC->PDC_RNPR = (unsigned int) address; - pPDC->PDC_RNCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetNextTx -//* \brief Set the next transmit transfer descriptor -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_SetNextTx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be transmitted - unsigned int bytes) // \arg number of bytes to be transmitted -{ - pPDC->PDC_TNPR = (unsigned int) address; - pPDC->PDC_TNCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetRx -//* \brief Set the receive transfer descriptor -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_SetRx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be received - unsigned int bytes) // \arg number of bytes to be received -{ - pPDC->PDC_RPR = (unsigned int) address; - pPDC->PDC_RCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetTx -//* \brief Set the transmit transfer descriptor -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_SetTx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be transmitted - unsigned int bytes) // \arg number of bytes to be transmitted -{ - pPDC->PDC_TPR = (unsigned int) address; - pPDC->PDC_TCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_EnableTx -//* \brief Enable transmit -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_EnableTx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_TXTEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_EnableRx -//* \brief Enable receive -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_EnableRx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_RXTEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_DisableTx -//* \brief Disable transmit -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_DisableTx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_DisableRx -//* \brief Disable receive -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_DisableRx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsTxEmpty -//* \brief Test if the current transfer descriptor has been sent -//*---------------------------------------------------------------------------- -__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_TCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsNextTxEmpty -//* \brief Test if the next transfer descriptor has been moved to the current td -//*---------------------------------------------------------------------------- -__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_TNCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsRxEmpty -//* \brief Test if the current transfer descriptor has been filled -//*---------------------------------------------------------------------------- -__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_RCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsNextRxEmpty -//* \brief Test if the next transfer descriptor has been moved to the current td -//*---------------------------------------------------------------------------- -__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_RNCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_Open -//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_Open ( - AT91PS_PDC pPDC) // \arg pointer to a PDC controller -{ - //* Disable the RX and TX PDC transfer requests - AT91F_PDC_DisableRx(pPDC); - AT91F_PDC_DisableTx(pPDC); - - //* Reset all Counter register Next buffer first - AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); - AT91F_PDC_SetTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetRx(pPDC, (char *) 0, 0); - - //* Enable the RX and TX PDC transfer requests - AT91F_PDC_EnableRx(pPDC); - AT91F_PDC_EnableTx(pPDC); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_Close -//* \brief Close PDC: disable TX and RX reset transfer descriptors -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_Close ( - AT91PS_PDC pPDC) // \arg pointer to a PDC controller -{ - //* Disable the RX and TX PDC transfer requests - AT91F_PDC_DisableRx(pPDC); - AT91F_PDC_DisableTx(pPDC); - - //* Reset all Counter register Next buffer first - AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); - AT91F_PDC_SetTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetRx(pPDC, (char *) 0, 0); - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SendFrame -//* \brief Close PDC: disable TX and RX reset transfer descriptors -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PDC_SendFrame( - AT91PS_PDC pPDC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - if (AT91F_PDC_IsTxEmpty(pPDC)) { - //* Buffer and next buffer can be initialized - AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer); - AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer); - return 2; - } - else if (AT91F_PDC_IsNextTxEmpty(pPDC)) { - //* Only one buffer can be initialized - AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer); - return 1; - } - else { - //* All buffer are in use... - return 0; - } -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_ReceiveFrame -//* \brief Close PDC: disable TX and RX reset transfer descriptors -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PDC_ReceiveFrame ( - AT91PS_PDC pPDC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - if (AT91F_PDC_IsRxEmpty(pPDC)) { - //* Buffer and next buffer can be initialized - AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer); - AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer); - return 2; - } - else if (AT91F_PDC_IsNextRxEmpty(pPDC)) { - //* Only one buffer can be initialized - AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer); - return 1; - } - else { - //* All buffer are in use... - return 0; - } -} -/* ***************************************************************************** - SOFTWARE API FOR DBGU - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_InterruptEnable -//* \brief Enable DBGU Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_DBGU_InterruptEnable( - AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller - unsigned int flag) // \arg dbgu interrupt to be enabled -{ - pDbgu->DBGU_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_InterruptDisable -//* \brief Disable DBGU Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_DBGU_InterruptDisable( - AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller - unsigned int flag) // \arg dbgu interrupt to be disabled -{ - pDbgu->DBGU_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_GetInterruptMaskStatus -//* \brief Return DBGU Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status - AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller -{ - return pDbgu->DBGU_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_IsInterruptMasked -//* \brief Test if DBGU Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_DBGU_IsInterruptMasked( - AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR SSC - ***************************************************************************** */ -//* Define the standard I2S mode configuration - -//* Configuration to set in the SSC Transmit Clock Mode Register -//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits -//* nb_slot_by_frame : number of channels -#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ - AT91C_SSC_CKS_DIV +\ - AT91C_SSC_CKO_CONTINOUS +\ - AT91C_SSC_CKG_NONE +\ - AT91C_SSC_START_FALL_RF +\ - AT91C_SSC_STTOUT +\ - ((1<<16) & AT91C_SSC_STTDLY) +\ - ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24)) - - -//* Configuration to set in the SSC Transmit Frame Mode Register -//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits -//* nb_slot_by_frame : number of channels -#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ - (nb_bit_by_slot-1) +\ - AT91C_SSC_MSBF +\ - (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\ - (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\ - AT91C_SSC_FSOS_NEGATIVE) - - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_SetBaudrate -//* \brief Set the baudrate according to the CPU clock -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_SetBaudrate ( - AT91PS_SSC pSSC, // \arg pointer to a SSC controller - unsigned int mainClock, // \arg peripheral clock - unsigned int speed) // \arg SSC baudrate -{ - unsigned int baud_value; - //* Define the baud rate divisor register - if (speed == 0) - baud_value = 0; - else - { - baud_value = (unsigned int) (mainClock * 10)/(2*speed); - if ((baud_value % 10) >= 5) - baud_value = (baud_value / 10) + 1; - else - baud_value /= 10; - } - - pSSC->SSC_CMR = baud_value; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_Configure -//* \brief Configure SSC -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_Configure ( - AT91PS_SSC pSSC, // \arg pointer to a SSC controller - unsigned int syst_clock, // \arg System Clock Frequency - unsigned int baud_rate, // \arg Expected Baud Rate Frequency - unsigned int clock_rx, // \arg Receiver Clock Parameters - unsigned int mode_rx, // \arg mode Register to be programmed - unsigned int clock_tx, // \arg Transmitter Clock Parameters - unsigned int mode_tx) // \arg mode Register to be programmed -{ - //* Disable interrupts - pSSC->SSC_IDR = (unsigned int) -1; - - //* Reset receiver and transmitter - pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ; - - //* Define the Clock Mode Register - AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate); - - //* Write the Receive Clock Mode Register - pSSC->SSC_RCMR = clock_rx; - - //* Write the Transmit Clock Mode Register - pSSC->SSC_TCMR = clock_tx; - - //* Write the Receive Frame Mode Register - pSSC->SSC_RFMR = mode_rx; - - //* Write the Transmit Frame Mode Register - pSSC->SSC_TFMR = mode_tx; - - //* Clear Transmit and Receive Counters - AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR)); - - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_EnableRx -//* \brief Enable receiving datas -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_EnableRx ( - AT91PS_SSC pSSC) // \arg pointer to a SSC controller -{ - //* Enable receiver - pSSC->SSC_CR = AT91C_SSC_RXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_DisableRx -//* \brief Disable receiving datas -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_DisableRx ( - AT91PS_SSC pSSC) // \arg pointer to a SSC controller -{ - //* Disable receiver - pSSC->SSC_CR = AT91C_SSC_RXDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_EnableTx -//* \brief Enable sending datas -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_EnableTx ( - AT91PS_SSC pSSC) // \arg pointer to a SSC controller -{ - //* Enable transmitter - pSSC->SSC_CR = AT91C_SSC_TXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_DisableTx -//* \brief Disable sending datas -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_DisableTx ( - AT91PS_SSC pSSC) // \arg pointer to a SSC controller -{ - //* Disable transmitter - pSSC->SSC_CR = AT91C_SSC_TXDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_EnableIt -//* \brief Enable SSC IT -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_EnableIt ( - AT91PS_SSC pSSC, // \arg pointer to a SSC controller - unsigned int flag) // \arg IT to be enabled -{ - //* Write to the IER register - pSSC->SSC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_DisableIt -//* \brief Disable SSC IT -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_DisableIt ( - AT91PS_SSC pSSC, // \arg pointer to a SSC controller - unsigned int flag) // \arg IT to be disabled -{ - //* Write to the IDR register - pSSC->SSC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_ReceiveFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SSC_ReceiveFrame ( - AT91PS_SSC pSSC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_ReceiveFrame( - (AT91PS_PDC) &(pSSC->SSC_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_SendFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SSC_SendFrame( - AT91PS_SSC pSSC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_SendFrame( - (AT91PS_PDC) &(pSSC->SSC_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_GetInterruptMaskStatus -//* \brief Return SSC Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status - AT91PS_SSC pSsc) // \arg pointer to a SSC controller -{ - return pSsc->SSC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_IsInterruptMasked -//* \brief Test if SSC Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_SSC_IsInterruptMasked( - AT91PS_SSC pSsc, // \arg pointer to a SSC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR SPI - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Open -//* \brief Open a SPI Port -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SPI_Open ( - const unsigned int null) // \arg -{ - /* NOT DEFINED AT THIS MOMENT */ - return ( 0 ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_CfgCs -//* \brief Configure SPI chip select register -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_CfgCs ( - AT91PS_SPI pSPI, // pointer to a SPI controller - int cs, // SPI cs number (0 to 3) - int val) // chip select register -{ - //* Write to the CSR register - *(pSPI->SPI_CSR + cs) = val; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_EnableIt -//* \brief Enable SPI interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_EnableIt ( - AT91PS_SPI pSPI, // pointer to a SPI controller - unsigned int flag) // IT to be enabled -{ - //* Write to the IER register - pSPI->SPI_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_DisableIt -//* \brief Disable SPI interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_DisableIt ( - AT91PS_SPI pSPI, // pointer to a SPI controller - unsigned int flag) // IT to be disabled -{ - //* Write to the IDR register - pSPI->SPI_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Reset -//* \brief Reset the SPI controller -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_Reset ( - AT91PS_SPI pSPI // pointer to a SPI controller - ) -{ - //* Write to the CR register - pSPI->SPI_CR = AT91C_SPI_SWRST; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Enable -//* \brief Enable the SPI controller -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_Enable ( - AT91PS_SPI pSPI // pointer to a SPI controller - ) -{ - //* Write to the CR register - pSPI->SPI_CR = AT91C_SPI_SPIEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Disable -//* \brief Disable the SPI controller -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_Disable ( - AT91PS_SPI pSPI // pointer to a SPI controller - ) -{ - //* Write to the CR register - pSPI->SPI_CR = AT91C_SPI_SPIDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_CfgMode -//* \brief Enable the SPI controller -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_CfgMode ( - AT91PS_SPI pSPI, // pointer to a SPI controller - int mode) // mode register -{ - //* Write to the MR register - pSPI->SPI_MR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_CfgPCS -//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_CfgPCS ( - AT91PS_SPI pSPI, // pointer to a SPI controller - char PCS_Device) // PCS of the Device -{ - //* Write to the MR register - pSPI->SPI_MR &= 0xFFF0FFFF; - pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_ReceiveFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SPI_ReceiveFrame ( - AT91PS_SPI pSPI, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_ReceiveFrame( - (AT91PS_PDC) &(pSPI->SPI_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_SendFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SPI_SendFrame( - AT91PS_SPI pSPI, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_SendFrame( - (AT91PS_PDC) &(pSPI->SPI_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Close -//* \brief Close SPI: disable IT disable transfert, close PDC -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_Close ( - AT91PS_SPI pSPI) // \arg pointer to a SPI controller -{ - //* Reset all the Chip Select register - pSPI->SPI_CSR[0] = 0 ; - pSPI->SPI_CSR[1] = 0 ; - pSPI->SPI_CSR[2] = 0 ; - pSPI->SPI_CSR[3] = 0 ; - - //* Reset the SPI mode - pSPI->SPI_MR = 0 ; - - //* Disable all interrupts - pSPI->SPI_IDR = 0xFFFFFFFF ; - - //* Abort the Peripheral Data Transfers - AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR)); - - //* Disable receiver and transmitter and stop any activity immediately - pSPI->SPI_CR = AT91C_SPI_SPIDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_PutChar -//* \brief Send a character,does not check if ready to send -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_PutChar ( - AT91PS_SPI pSPI, - unsigned int character, - unsigned int cs_number ) -{ - unsigned int value_for_cs; - value_for_cs = (~(1 << cs_number)) & 0xF; //Place a zero among a 4 ONEs number - pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_GetChar -//* \brief Receive a character,does not check if a character is available -//*---------------------------------------------------------------------------- -__inline int AT91F_SPI_GetChar ( - const AT91PS_SPI pSPI) -{ - return((pSPI->SPI_RDR) & 0xFFFF); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_GetInterruptMaskStatus -//* \brief Return SPI Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status - AT91PS_SPI pSpi) // \arg pointer to a SPI controller -{ - return pSpi->SPI_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_IsInterruptMasked -//* \brief Test if SPI Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_SPI_IsInterruptMasked( - AT91PS_SPI pSpi, // \arg pointer to a SPI controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR PWMC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_GetStatus -//* \brief Return PWM Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status - AT91PS_PWMC pPWM) // pointer to a PWM controller -{ - return pPWM->PWMC_SR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_InterruptEnable -//* \brief Enable PWM Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_InterruptEnable( - AT91PS_PWMC pPwm, // \arg pointer to a PWM controller - unsigned int flag) // \arg PWM interrupt to be enabled -{ - pPwm->PWMC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_InterruptDisable -//* \brief Disable PWM Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_InterruptDisable( - AT91PS_PWMC pPwm, // \arg pointer to a PWM controller - unsigned int flag) // \arg PWM interrupt to be disabled -{ - pPwm->PWMC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_GetInterruptMaskStatus -//* \brief Return PWM Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status - AT91PS_PWMC pPwm) // \arg pointer to a PWM controller -{ - return pPwm->PWMC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_IsInterruptMasked -//* \brief Test if PWM Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PWMC_IsInterruptMasked( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_IsStatusSet -//* \brief Test if PWM Interrupt is Set -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PWMC_IsStatusSet( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PWMC_GetStatus(pPWM) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_CfgChannel -//* \brief Test if PWM Interrupt is Set -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CfgChannel( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int channelId, // \arg PWM channel ID - unsigned int mode, // \arg PWM mode - unsigned int period, // \arg PWM period - unsigned int duty) // \arg PWM duty cycle -{ - pPWM->PWMC_CH[channelId].PWMC_CMR = mode; - pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty; - pPWM->PWMC_CH[channelId].PWMC_CPRDR = period; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_StartChannel -//* \brief Enable channel -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_StartChannel( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int flag) // \arg Channels IDs to be enabled -{ - pPWM->PWMC_ENA = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_StopChannel -//* \brief Disable channel -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_StopChannel( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int flag) // \arg Channels IDs to be enabled -{ - pPWM->PWMC_DIS = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_UpdateChannel -//* \brief Update Period or Duty Cycle -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_UpdateChannel( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int channelId, // \arg PWM channel ID - unsigned int update) // \arg Channels IDs to be enabled -{ - pPWM->PWMC_CH[channelId].PWMC_CUPDR = update; -} - -/* ***************************************************************************** - SOFTWARE API FOR TC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC_InterruptEnable -//* \brief Enable TC Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_TC_InterruptEnable( - AT91PS_TC pTc, // \arg pointer to a TC controller - unsigned int flag) // \arg TC interrupt to be enabled -{ - pTc->TC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC_InterruptDisable -//* \brief Disable TC Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_TC_InterruptDisable( - AT91PS_TC pTc, // \arg pointer to a TC controller - unsigned int flag) // \arg TC interrupt to be disabled -{ - pTc->TC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC_GetInterruptMaskStatus -//* \brief Return TC Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status - AT91PS_TC pTc) // \arg pointer to a TC controller -{ - return pTc->TC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC_IsInterruptMasked -//* \brief Test if TC Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_TC_IsInterruptMasked( - AT91PS_TC pTc, // \arg pointer to a TC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR PMC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgSysClkEnableReg -//* \brief Configure the System Clock Enable Register of the PMC controller -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_CfgSysClkEnableReg ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int mode) -{ - //* Write to the SCER register - pPMC->PMC_SCER = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgSysClkDisableReg -//* \brief Configure the System Clock Disable Register of the PMC controller -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_CfgSysClkDisableReg ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int mode) -{ - //* Write to the SCDR register - pPMC->PMC_SCDR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetSysClkStatusReg -//* \brief Return the System Clock Status Register of the PMC controller -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetSysClkStatusReg ( - AT91PS_PMC pPMC // pointer to a CAN controller - ) -{ - return pPMC->PMC_SCSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_EnablePeriphClock -//* \brief Enable peripheral clock -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_EnablePeriphClock ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int periphIds) // \arg IDs of peripherals to enable -{ - pPMC->PMC_PCER = periphIds; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_DisablePeriphClock -//* \brief Disable peripheral clock -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_DisablePeriphClock ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int periphIds) // \arg IDs of peripherals to enable -{ - pPMC->PMC_PCDR = periphIds; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetPeriphClock -//* \brief Get peripheral clock status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetPeriphClock ( - AT91PS_PMC pPMC) // \arg pointer to PMC controller -{ - return pPMC->PMC_PCSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_CfgMainOscillatorReg -//* \brief Cfg the main oscillator -//*---------------------------------------------------------------------------- -__inline void AT91F_CKGR_CfgMainOscillatorReg ( - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int mode) -{ - pCKGR->CKGR_MOR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_GetMainOscillatorReg -//* \brief Cfg the main oscillator -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CKGR_GetMainOscillatorReg ( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller -{ - return pCKGR->CKGR_MOR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_EnableMainOscillator -//* \brief Enable the main oscillator -//*---------------------------------------------------------------------------- -__inline void AT91F_CKGR_EnableMainOscillator( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller -{ - pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_DisableMainOscillator -//* \brief Disable the main oscillator -//*---------------------------------------------------------------------------- -__inline void AT91F_CKGR_DisableMainOscillator ( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller -{ - pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_CfgMainOscStartUpTime -//* \brief Cfg MOR Register according to the main osc startup time -//*---------------------------------------------------------------------------- -__inline void AT91F_CKGR_CfgMainOscStartUpTime ( - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int startup_time, // \arg main osc startup time in microsecond (us) - unsigned int slowClock) // \arg slowClock in Hz -{ - pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT; - pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_GetMainClockFreqReg -//* \brief Cfg the main oscillator -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CKGR_GetMainClockFreqReg ( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller -{ - return pCKGR->CKGR_MCFR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_GetMainClock -//* \brief Return Main clock in Hz -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CKGR_GetMainClock ( - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int slowClock) // \arg slowClock in Hz -{ - return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgMCKReg -//* \brief Cfg Master Clock Register -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_CfgMCKReg ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int mode) -{ - pPMC->PMC_MCKR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetMCKReg -//* \brief Return Master Clock Register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetMCKReg( - AT91PS_PMC pPMC) // \arg pointer to PMC controller -{ - return pPMC->PMC_MCKR; -} - -//*------------------------------------------------------------------------------ -//* \fn AT91F_PMC_GetMasterClock -//* \brief Return master clock in Hz which correponds to processor clock for ARM7 -//*------------------------------------------------------------------------------ -__inline unsigned int AT91F_PMC_GetMasterClock ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int slowClock) // \arg slowClock in Hz -{ - unsigned int reg = pPMC->PMC_MCKR; - unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2)); - unsigned int pllDivider, pllMultiplier; - - switch (reg & AT91C_PMC_CSS) { - case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected - return slowClock / prescaler; - case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected - return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler; - case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected - reg = pCKGR->CKGR_PLLR; - pllDivider = (reg & AT91C_CKGR_DIV); - pllMultiplier = ((reg & AT91C_CKGR_MUL) >> 16) + 1; - return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler; - } - return 0; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_EnablePCK -//* \brief Enable peripheral clock -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_EnablePCK ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int pck, // \arg Peripheral clock identifier 0 .. 7 - unsigned int mode) -{ - pPMC->PMC_PCKR[pck] = mode; - pPMC->PMC_SCER = (1 << pck) << 8; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_DisablePCK -//* \brief Enable peripheral clock -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_DisablePCK ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int pck) // \arg Peripheral clock identifier 0 .. 7 -{ - pPMC->PMC_SCDR = (1 << pck) << 8; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_EnableIt -//* \brief Enable PMC interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_EnableIt ( - AT91PS_PMC pPMC, // pointer to a PMC controller - unsigned int flag) // IT to be enabled -{ - //* Write to the IER register - pPMC->PMC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_DisableIt -//* \brief Disable PMC interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_DisableIt ( - AT91PS_PMC pPMC, // pointer to a PMC controller - unsigned int flag) // IT to be disabled -{ - //* Write to the IDR register - pPMC->PMC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetStatus -//* \brief Return PMC Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status - AT91PS_PMC pPMC) // pointer to a PMC controller -{ - return pPMC->PMC_SR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetInterruptMaskStatus -//* \brief Return PMC Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status - AT91PS_PMC pPMC) // pointer to a PMC controller -{ - return pPMC->PMC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_IsInterruptMasked -//* \brief Test if PMC Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_IsInterruptMasked( - AT91PS_PMC pPMC, // \arg pointer to a PMC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_IsStatusSet -//* \brief Test if PMC Status is Set -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_IsStatusSet( - AT91PS_PMC pPMC, // \arg pointer to a PMC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PMC_GetStatus(pPMC) & flag); -}/* ***************************************************************************** - SOFTWARE API FOR ADC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_EnableIt -//* \brief Enable ADC interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_EnableIt ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int flag) // IT to be enabled -{ - //* Write to the IER register - pADC->ADC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_DisableIt -//* \brief Disable ADC interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_DisableIt ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int flag) // IT to be disabled -{ - //* Write to the IDR register - pADC->ADC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetStatus -//* \brief Return ADC Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status - AT91PS_ADC pADC) // pointer to a ADC controller -{ - return pADC->ADC_SR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetInterruptMaskStatus -//* \brief Return ADC Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status - AT91PS_ADC pADC) // pointer to a ADC controller -{ - return pADC->ADC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_IsInterruptMasked -//* \brief Test if ADC Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_IsInterruptMasked( - AT91PS_ADC pADC, // \arg pointer to a ADC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_IsStatusSet -//* \brief Test if ADC Status is Set -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_IsStatusSet( - AT91PS_ADC pADC, // \arg pointer to a ADC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_ADC_GetStatus(pADC) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_CfgModeReg -//* \brief Configure the Mode Register of the ADC controller -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_CfgModeReg ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int mode) // mode register -{ - //* Write to the MR register - pADC->ADC_MR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetModeReg -//* \brief Return the Mode Register of the ADC controller value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetModeReg ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_MR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_CfgTimings -//* \brief Configure the different necessary timings of the ADC controller -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_CfgTimings ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int mck_clock, // in MHz - unsigned int adc_clock, // in MHz - unsigned int startup_time, // in us - unsigned int sample_and_hold_time) // in ns -{ - unsigned int prescal,startup,shtim; - - prescal = mck_clock/(2*adc_clock) - 1; - startup = adc_clock*startup_time/8 - 1; - shtim = adc_clock*sample_and_hold_time/1000 - 1; - - //* Write to the MR register - pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_EnableChannel -//* \brief Return ADC Timer Register Value -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_EnableChannel ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int channel) // mode register -{ - //* Write to the CHER register - pADC->ADC_CHER = channel; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_DisableChannel -//* \brief Return ADC Timer Register Value -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_DisableChannel ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int channel) // mode register -{ - //* Write to the CHDR register - pADC->ADC_CHDR = channel; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetChannelStatus -//* \brief Return ADC Timer Register Value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetChannelStatus ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CHSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_StartConversion -//* \brief Software request for a analog to digital conversion -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_StartConversion ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - pADC->ADC_CR = AT91C_ADC_START; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_SoftReset -//* \brief Software reset -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_SoftReset ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - pADC->ADC_CR = AT91C_ADC_SWRST; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetLastConvertedData -//* \brief Return the Last Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetLastConvertedData ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_LCDR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH0 -//* \brief Return the Channel 0 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH0 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR0; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH1 -//* \brief Return the Channel 1 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH1 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR1; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH2 -//* \brief Return the Channel 2 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH2 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR2; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH3 -//* \brief Return the Channel 3 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH3 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR3; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH4 -//* \brief Return the Channel 4 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH4 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR4; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH5 -//* \brief Return the Channel 5 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH5 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR5; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH6 -//* \brief Return the Channel 6 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH6 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR6; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH7 -//* \brief Return the Channel 7 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH7 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR7; -} - -/* ***************************************************************************** - SOFTWARE API FOR PIO - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgPeriph -//* \brief Enable pins to be drived by peripheral -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgPeriph( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int periphAEnable, // \arg PERIPH A to enable - unsigned int periphBEnable) // \arg PERIPH B to enable - -{ - pPio->PIO_ASR = periphAEnable; - pPio->PIO_BSR = periphBEnable; - pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgOutput -//* \brief Enable PIO in output mode -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int pioEnable) // \arg PIO to be enabled -{ - pPio->PIO_PER = pioEnable; // Set in PIO mode - pPio->PIO_OER = pioEnable; // Configure in Output -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgInput -//* \brief Enable PIO in input mode -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgInput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int inputEnable) // \arg PIO to be enabled -{ - // Disable output - pPio->PIO_ODR = inputEnable; - pPio->PIO_PER = inputEnable; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgOpendrain -//* \brief Configure PIO in open drain -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgOpendrain( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int multiDrvEnable) // \arg pio to be configured in open drain -{ - // Configure the multi-drive option - pPio->PIO_MDDR = ~multiDrvEnable; - pPio->PIO_MDER = multiDrvEnable; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgPullup -//* \brief Enable pullup on PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgPullup( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int pullupEnable) // \arg enable pullup on PIO -{ - // Connect or not Pullup - pPio->PIO_PPUDR = ~pullupEnable; - pPio->PIO_PPUER = pullupEnable; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgDirectDrive -//* \brief Enable direct drive on PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgDirectDrive( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int directDrive) // \arg PIO to be configured with direct drive - -{ - // Configure the Direct Drive - pPio->PIO_OWDR = ~directDrive; - pPio->PIO_OWER = directDrive; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgInputFilter -//* \brief Enable input filter on input PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgInputFilter( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int inputFilter) // \arg PIO to be configured with input filter - -{ - // Configure the Direct Drive - pPio->PIO_IFDR = ~inputFilter; - pPio->PIO_IFER = inputFilter; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInput -//* \brief Return PIO input value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetInput( // \return PIO input - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_PDSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInputSet -//* \brief Test if PIO is input flag is active -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsInputSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInput(pPio) & flag); -} - - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_SetOutput -//* \brief Set to 1 output PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_SetOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg output to be set -{ - pPio->PIO_SODR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_ClearOutput -//* \brief Set to 0 output PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_ClearOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg output to be cleared -{ - pPio->PIO_CODR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_ForceOutput -//* \brief Force output when Direct drive option is enabled -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_ForceOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg output to be forced -{ - pPio->PIO_ODSR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_Enable -//* \brief Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_Enable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be enabled -{ - pPio->PIO_PER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_Disable -//* \brief Disable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_Disable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be disabled -{ - pPio->PIO_PDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetStatus -//* \brief Return PIO Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_PSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsSet -//* \brief Test if PIO is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputEnable -//* \brief Output Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_OutputEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output to be enabled -{ - pPio->PIO_OER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputDisable -//* \brief Output Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_OutputDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output to be disabled -{ - pPio->PIO_ODR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetOutputStatus -//* \brief Return PIO Output Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_OSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsOuputSet -//* \brief Test if PIO Output is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsOutputSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetOutputStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InputFilterEnable -//* \brief Input Filter Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_InputFilterEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio input filter to be enabled -{ - pPio->PIO_IFER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InputFilterDisable -//* \brief Input Filter Disable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_InputFilterDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio input filter to be disabled -{ - pPio->PIO_IFDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInputFilterStatus -//* \brief Return PIO Input Filter Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_IFSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInputFilterSet -//* \brief Test if PIO Input filter is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsInputFilterSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInputFilterStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetOutputDataStatus -//* \brief Return PIO Output Data Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_ODSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InterruptEnable -//* \brief Enable PIO Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_InterruptEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio interrupt to be enabled -{ - pPio->PIO_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InterruptDisable -//* \brief Disable PIO Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_InterruptDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio interrupt to be disabled -{ - pPio->PIO_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInterruptMaskStatus -//* \brief Return PIO Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInterruptStatus -//* \brief Return PIO Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_ISR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInterruptMasked -//* \brief Test if PIO Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsInterruptMasked( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInterruptSet -//* \brief Test if PIO Interrupt is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsInterruptSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInterruptStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_MultiDriverEnable -//* \brief Multi Driver Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_MultiDriverEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be enabled -{ - pPio->PIO_MDER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_MultiDriverDisable -//* \brief Multi Driver Disable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_MultiDriverDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be disabled -{ - pPio->PIO_MDDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetMultiDriverStatus -//* \brief Return PIO Multi Driver Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_MDSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsMultiDriverSet -//* \brief Test if PIO MultiDriver is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsMultiDriverSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_A_RegisterSelection -//* \brief PIO A Register Selection -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_A_RegisterSelection( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio A register selection -{ - pPio->PIO_ASR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_B_RegisterSelection -//* \brief PIO B Register Selection -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_B_RegisterSelection( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio B register selection -{ - pPio->PIO_BSR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_Get_AB_RegisterStatus -//* \brief Return PIO Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_ABSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsAB_RegisterSet -//* \brief Test if PIO AB Register is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsAB_RegisterSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputWriteEnable -//* \brief Output Write Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_OutputWriteEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output write to be enabled -{ - pPio->PIO_OWER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputWriteDisable -//* \brief Output Write Disable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_OutputWriteDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output write to be disabled -{ - pPio->PIO_OWDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetOutputWriteStatus -//* \brief Return PIO Output Write Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_OWSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsOutputWriteSet -//* \brief Test if PIO OutputWrite is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsOutputWriteSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetCfgPullup -//* \brief Return PIO Configuration Pullup -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_PPUSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsOutputDataStatusSet -//* \brief Test if PIO Output Data Status is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsOutputDataStatusSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetOutputDataStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsCfgPullupStatusSet -//* \brief Test if PIO Configuration Pullup Status is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsCfgPullupStatusSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (~AT91F_PIO_GetCfgPullup(pPio) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR TWI - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_EnableIt -//* \brief Enable TWI IT -//*---------------------------------------------------------------------------- -__inline void AT91F_TWI_EnableIt ( - AT91PS_TWI pTWI, // \arg pointer to a TWI controller - unsigned int flag) // \arg IT to be enabled -{ - //* Write to the IER register - pTWI->TWI_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_DisableIt -//* \brief Disable TWI IT -//*---------------------------------------------------------------------------- -__inline void AT91F_TWI_DisableIt ( - AT91PS_TWI pTWI, // \arg pointer to a TWI controller - unsigned int flag) // \arg IT to be disabled -{ - //* Write to the IDR register - pTWI->TWI_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_Configure -//* \brief Configure TWI in master mode -//*---------------------------------------------------------------------------- -__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI ) // \arg pointer to a TWI controller -{ - //* Disable interrupts - pTWI->TWI_IDR = (unsigned int) -1; - - //* Reset peripheral - pTWI->TWI_CR = AT91C_TWI_SWRST; - - //* Set Master mode - pTWI->TWI_CR = AT91C_TWI_MSEN | AT91C_TWI_SVDIS; - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_GetInterruptMaskStatus -//* \brief Return TWI Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status - AT91PS_TWI pTwi) // \arg pointer to a TWI controller -{ - return pTwi->TWI_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_IsInterruptMasked -//* \brief Test if TWI Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_TWI_IsInterruptMasked( - AT91PS_TWI pTwi, // \arg pointer to a TWI controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR USART - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Baudrate -//* \brief Calculate the baudrate -//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity -#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_NONE + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CLKS_CLOCK ) - -//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity -#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_NONE + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CLKS_EXT ) - -//* Standard Synchronous Mode : 8 bits , 1 stop , no parity -#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \ - AT91C_US_USMODE_NORMAL + \ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_NONE + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CLKS_CLOCK ) - -//* SCK used Label -#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT) - -//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity -#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \ - AT91C_US_CLKS_CLOCK +\ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_EVEN + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CKLO +\ - AT91C_US_OVER) - -//* Standard IRDA mode -#define AT91C_US_ASYNC_IRDA_MODE ( AT91C_US_USMODE_IRDA + \ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_NONE + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CLKS_CLOCK ) - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Baudrate -//* \brief Caluculate baud_value according to the main clock and the baud rate -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_US_Baudrate ( - const unsigned int main_clock, // \arg peripheral clock - const unsigned int baud_rate) // \arg UART baudrate -{ - unsigned int baud_value = ((main_clock*10)/(baud_rate * 16)); - if ((baud_value % 10) >= 5) - baud_value = (baud_value / 10) + 1; - else - baud_value /= 10; - return baud_value; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_SetBaudrate -//* \brief Set the baudrate according to the CPU clock -//*---------------------------------------------------------------------------- -__inline void AT91F_US_SetBaudrate ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int mainClock, // \arg peripheral clock - unsigned int speed) // \arg UART baudrate -{ - //* Define the baud rate divisor register - pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_SetTimeguard -//* \brief Set USART timeguard -//*---------------------------------------------------------------------------- -__inline void AT91F_US_SetTimeguard ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int timeguard) // \arg timeguard value -{ - //* Write the Timeguard Register - pUSART->US_TTGR = timeguard ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_EnableIt -//* \brief Enable USART IT -//*---------------------------------------------------------------------------- -__inline void AT91F_US_EnableIt ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int flag) // \arg IT to be enabled -{ - //* Write to the IER register - pUSART->US_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_DisableIt -//* \brief Disable USART IT -//*---------------------------------------------------------------------------- -__inline void AT91F_US_DisableIt ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int flag) // \arg IT to be disabled -{ - //* Write to the IER register - pUSART->US_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Configure -//* \brief Configure USART -//*---------------------------------------------------------------------------- -__inline void AT91F_US_Configure ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int mainClock, // \arg peripheral clock - unsigned int mode , // \arg mode Register to be programmed - unsigned int baudRate , // \arg baudrate to be programmed - unsigned int timeguard ) // \arg timeguard to be programmed -{ - //* Disable interrupts - pUSART->US_IDR = (unsigned int) -1; - - //* Reset receiver and transmitter - pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ; - - //* Define the baud rate divisor register - AT91F_US_SetBaudrate(pUSART, mainClock, baudRate); - - //* Write the Timeguard Register - AT91F_US_SetTimeguard(pUSART, timeguard); - - //* Clear Transmit and Receive Counters - AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR)); - - //* Define the USART mode - pUSART->US_MR = mode ; - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_EnableRx -//* \brief Enable receiving characters -//*---------------------------------------------------------------------------- -__inline void AT91F_US_EnableRx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Enable receiver - pUSART->US_CR = AT91C_US_RXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_EnableTx -//* \brief Enable sending characters -//*---------------------------------------------------------------------------- -__inline void AT91F_US_EnableTx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Enable transmitter - pUSART->US_CR = AT91C_US_TXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_ResetRx -//* \brief Reset Receiver and re-enable it -//*---------------------------------------------------------------------------- -__inline void AT91F_US_ResetRx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Reset receiver - pUSART->US_CR = AT91C_US_RSTRX; - //* Re-Enable receiver - pUSART->US_CR = AT91C_US_RXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_ResetTx -//* \brief Reset Transmitter and re-enable it -//*---------------------------------------------------------------------------- -__inline void AT91F_US_ResetTx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Reset transmitter - pUSART->US_CR = AT91C_US_RSTTX; - //* Enable transmitter - pUSART->US_CR = AT91C_US_TXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_DisableRx -//* \brief Disable Receiver -//*---------------------------------------------------------------------------- -__inline void AT91F_US_DisableRx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Disable receiver - pUSART->US_CR = AT91C_US_RXDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_DisableTx -//* \brief Disable Transmitter -//*---------------------------------------------------------------------------- -__inline void AT91F_US_DisableTx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Disable transmitter - pUSART->US_CR = AT91C_US_TXDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Close -//* \brief Close USART: disable IT disable receiver and transmitter, close PDC -//*---------------------------------------------------------------------------- -__inline void AT91F_US_Close ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Reset the baud rate divisor register - pUSART->US_BRGR = 0 ; - - //* Reset the USART mode - pUSART->US_MR = 0 ; - - //* Reset the Timeguard Register - pUSART->US_TTGR = 0; - - //* Disable all interrupts - pUSART->US_IDR = 0xFFFFFFFF ; - - //* Abort the Peripheral Data Transfers - AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR)); - - //* Disable receiver and transmitter and stop any activity immediately - pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_TxReady -//* \brief Return 1 if a character can be written in US_THR -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_US_TxReady ( - AT91PS_USART pUSART ) // \arg pointer to a USART controller -{ - return (pUSART->US_CSR & AT91C_US_TXRDY); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_RxReady -//* \brief Return 1 if a character can be read in US_RHR -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_US_RxReady ( - AT91PS_USART pUSART ) // \arg pointer to a USART controller -{ - return (pUSART->US_CSR & AT91C_US_RXRDY); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Error -//* \brief Return the error flag -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_US_Error ( - AT91PS_USART pUSART ) // \arg pointer to a USART controller -{ - return (pUSART->US_CSR & - (AT91C_US_OVRE | // Overrun error - AT91C_US_FRAME | // Framing error - AT91C_US_PARE)); // Parity error -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_PutChar -//* \brief Send a character,does not check if ready to send -//*---------------------------------------------------------------------------- -__inline void AT91F_US_PutChar ( - AT91PS_USART pUSART, - int character ) -{ - pUSART->US_THR = (character & 0x1FF); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_GetChar -//* \brief Receive a character,does not check if a character is available -//*---------------------------------------------------------------------------- -__inline int AT91F_US_GetChar ( - const AT91PS_USART pUSART) -{ - return((pUSART->US_RHR) & 0x1FF); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_SendFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_US_SendFrame( - AT91PS_USART pUSART, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_SendFrame( - (AT91PS_PDC) &(pUSART->US_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_ReceiveFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_US_ReceiveFrame ( - AT91PS_USART pUSART, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_ReceiveFrame( - (AT91PS_PDC) &(pUSART->US_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_SetIrdaFilter -//* \brief Set the value of IrDa filter tregister -//*---------------------------------------------------------------------------- -__inline void AT91F_US_SetIrdaFilter ( - AT91PS_USART pUSART, - unsigned char value -) -{ - pUSART->US_IF = value; -} - -/* ***************************************************************************** - SOFTWARE API FOR UDP - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EnableIt -//* \brief Enable UDP IT -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EnableIt ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg IT to be enabled -{ - //* Write to the IER register - pUDP->UDP_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_DisableIt -//* \brief Disable UDP IT -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_DisableIt ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg IT to be disabled -{ - //* Write to the IDR register - pUDP->UDP_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_SetAddress -//* \brief Set UDP functional address -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_SetAddress ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char address) // \arg new UDP address -{ - pUDP->UDP_FADDR = (AT91C_UDP_FEN | address); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EnableEp -//* \brief Enable Endpoint -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EnableEp ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg endpoints to be enabled -{ - pUDP->UDP_GLBSTATE |= flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_DisableEp -//* \brief Enable Endpoint -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_DisableEp ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg endpoints to be enabled -{ - pUDP->UDP_GLBSTATE &= ~(flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_SetState -//* \brief Set UDP Device state -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_SetState ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg new UDP address -{ - pUDP->UDP_GLBSTATE &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG); - pUDP->UDP_GLBSTATE |= flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_GetState -//* \brief return UDP Device state -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state - AT91PS_UDP pUDP) // \arg pointer to a UDP controller -{ - return (pUDP->UDP_GLBSTATE & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_ResetEp -//* \brief Reset UDP endpoint -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_ResetEp ( // \return the UDP device state - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg Endpoints to be reset -{ - pUDP->UDP_RSTEP = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpStall -//* \brief Endpoint will STALL requests -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EpStall( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpWrite -//* \brief Write value in the DPR -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EpWrite( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint, // \arg endpoint number - unsigned char value) // \arg value to be written in the DPR -{ - pUDP->UDP_FDR[endpoint] = value; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpRead -//* \brief Return value from the DPR -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_UDP_EpRead( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - return pUDP->UDP_FDR[endpoint]; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpEndOfWr -//* \brief Notify the UDP that values in DPR are ready to be sent -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EpEndOfWr( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpClear -//* \brief Clear flag in the endpoint CSR register -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EpClear( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint, // \arg endpoint number - unsigned int flag) // \arg flag to be cleared -{ - pUDP->UDP_CSR[endpoint] &= ~(flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpSet -//* \brief Set flag in the endpoint CSR register -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EpSet( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint, // \arg endpoint number - unsigned int flag) // \arg flag to be cleared -{ - pUDP->UDP_CSR[endpoint] |= flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpStatus -//* \brief Return the endpoint CSR register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_UDP_EpStatus( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - return pUDP->UDP_CSR[endpoint]; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_GetInterruptMaskStatus -//* \brief Return UDP Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status - AT91PS_UDP pUdp) // \arg pointer to a UDP controller -{ - return pUdp->UDP_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_IsInterruptMasked -//* \brief Test if UDP Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_UDP_IsInterruptMasked( - AT91PS_UDP pUdp, // \arg pointer to a UDP controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR AIC - ***************************************************************************** */ -#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20] - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_ConfigureIt -//* \brief Interrupt Handler Initialization -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AIC_ConfigureIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id, // \arg interrupt number to initialize - unsigned int priority, // \arg priority to give to the interrupt - unsigned int src_type, // \arg activation and sense of activation - void (*newHandler) (void) ) // \arg address of the interrupt handler -{ - unsigned int oldHandler; - unsigned int mask ; - - oldHandler = pAic->AIC_SVR[irq_id]; - - mask = 0x1 << irq_id ; - //* Disable the interrupt on the interrupt controller - pAic->AIC_IDCR = mask ; - //* Save the interrupt handler routine pointer and the interrupt priority - pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ; - //* Store the Source Mode Register - pAic->AIC_SMR[irq_id] = src_type | priority ; - //* Clear the interrupt on the interrupt controller - pAic->AIC_ICCR = mask ; - - return oldHandler; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_EnableIt -//* \brief Enable corresponding IT number -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_EnableIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id ) // \arg interrupt number to initialize -{ - //* Enable the interrupt on the interrupt controller - pAic->AIC_IECR = 0x1 << irq_id ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_DisableIt -//* \brief Disable corresponding IT number -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_DisableIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id ) // \arg interrupt number to initialize -{ - unsigned int mask = 0x1 << irq_id; - //* Disable the interrupt on the interrupt controller - pAic->AIC_IDCR = mask ; - //* Clear the interrupt on the Interrupt Controller ( if one is pending ) - pAic->AIC_ICCR = mask ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_ClearIt -//* \brief Clear corresponding IT number -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_ClearIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg interrupt number to initialize -{ - //* Clear the interrupt on the Interrupt Controller ( if one is pending ) - pAic->AIC_ICCR = (0x1 << irq_id); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_AcknowledgeIt -//* \brief Acknowledge corresponding IT number -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_AcknowledgeIt ( - AT91PS_AIC pAic) // \arg pointer to the AIC registers -{ - pAic->AIC_EOICR = pAic->AIC_EOICR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_SetExceptionVector -//* \brief Configure vector handler -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AIC_SetExceptionVector ( - unsigned int *pVector, // \arg pointer to the AIC registers - void (*Handler) () ) // \arg Interrupt Handler -{ - unsigned int oldVector = *pVector; - - if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE) - *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE; - else - *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000; - - return oldVector; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_Trig -//* \brief Trig an IT -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_Trig ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg interrupt number -{ - pAic->AIC_ISCR = (0x1 << irq_id) ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_IsActive -//* \brief Test if an IT is active -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AIC_IsActive ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg Interrupt Number -{ - return (pAic->AIC_ISR & (0x1 << irq_id)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_IsPending -//* \brief Test if an IT is pending -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AIC_IsPending ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg Interrupt Number -{ - return (pAic->AIC_IPR & (0x1 << irq_id)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_Open -//* \brief Set exception vectors and AIC registers to default values -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_Open( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - void (*IrqHandler) (), // \arg Default IRQ vector exception - void (*FiqHandler) (), // \arg Default FIQ vector exception - void (*DefaultHandler) (), // \arg Default Handler set in ISR - void (*SpuriousHandler) (), // \arg Default Spurious Handler - unsigned int protectMode) // \arg Debug Control Register -{ - int i; - - // Disable all interrupts and set IVR to the default handler - for (i = 0; i < 32; ++i) { - AT91F_AIC_DisableIt(pAic, i); - AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, DefaultHandler); - } - - // Set the IRQ exception vector - AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler); - // Set the Fast Interrupt exception vector - AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler); - - pAic->AIC_SPU = (unsigned int) SpuriousHandler; - pAic->AIC_DCR = protectMode; -} -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_CfgPMC -//* \brief Enable Peripheral clock in PMC for MC -//*---------------------------------------------------------------------------- -__inline void AT91F_MC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_CfgPMC -//* \brief Enable Peripheral clock in PMC for DBGU -//*---------------------------------------------------------------------------- -__inline void AT91F_DBGU_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_CfgPIO -//* \brief Configure PIO controllers to drive DBGU signals -//*---------------------------------------------------------------------------- -__inline void AT91F_DBGU_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA10_DTXD ) | - ((unsigned int) AT91C_PA9_DRXD ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CH3_CfgPIO -//* \brief Configure PIO controllers to drive PWMC_CH3 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CH3_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PA14_PWM3 ) | - ((unsigned int) AT91C_PA7_PWM3 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CH2_CfgPIO -//* \brief Configure PIO controllers to drive PWMC_CH2 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CH2_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA2_PWM2 ), // Peripheral A - ((unsigned int) AT91C_PA25_PWM2 ) | - ((unsigned int) AT91C_PA13_PWM2 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CH1_CfgPIO -//* \brief Configure PIO controllers to drive PWMC_CH1 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CH1_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA1_PWM1 ), // Peripheral A - ((unsigned int) AT91C_PA24_PWM1 ) | - ((unsigned int) AT91C_PA12_PWM1 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CH0_CfgPIO -//* \brief Configure PIO controllers to drive PWMC_CH0 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CH0_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA0_PWM0 ), // Peripheral A - ((unsigned int) AT91C_PA23_PWM0 ) | - ((unsigned int) AT91C_PA11_PWM0 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_CfgPMC -//* \brief Enable Peripheral clock in PMC for SSC -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SSC)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_CfgPIO -//* \brief Configure PIO controllers to drive SSC signals -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA17_TD ) | - ((unsigned int) AT91C_PA15_TF ) | - ((unsigned int) AT91C_PA19_RK ) | - ((unsigned int) AT91C_PA18_RD ) | - ((unsigned int) AT91C_PA20_RF ) | - ((unsigned int) AT91C_PA16_TK ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_CfgPMC -//* \brief Enable Peripheral clock in PMC for SPI -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SPI)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_CfgPIO -//* \brief Configure PIO controllers to drive SPI signals -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA11_NPCS0 ) | - ((unsigned int) AT91C_PA13_MOSI ) | - ((unsigned int) AT91C_PA31_NPCS1 ) | - ((unsigned int) AT91C_PA12_MISO ) | - ((unsigned int) AT91C_PA14_SPCK ), // Peripheral A - ((unsigned int) AT91C_PA9_NPCS1 ) | - ((unsigned int) AT91C_PA30_NPCS2 ) | - ((unsigned int) AT91C_PA10_NPCS2 ) | - ((unsigned int) AT91C_PA22_NPCS3 ) | - ((unsigned int) AT91C_PA3_NPCS3 ) | - ((unsigned int) AT91C_PA5_NPCS3 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CfgPMC -//* \brief Enable Peripheral clock in PMC for PWMC -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_PWMC)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC2_CfgPMC -//* \brief Enable Peripheral clock in PMC for TC2 -//*---------------------------------------------------------------------------- -__inline void AT91F_TC2_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TC2)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC2_CfgPIO -//* \brief Configure PIO controllers to drive TC2 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_TC2_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PA26_TIOA2 ) | - ((unsigned int) AT91C_PA27_TIOB2 ) | - ((unsigned int) AT91C_PA29_TCLK2 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC1_CfgPMC -//* \brief Enable Peripheral clock in PMC for TC1 -//*---------------------------------------------------------------------------- -__inline void AT91F_TC1_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TC1)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC1_CfgPIO -//* \brief Configure PIO controllers to drive TC1 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_TC1_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PA15_TIOA1 ) | - ((unsigned int) AT91C_PA16_TIOB1 ) | - ((unsigned int) AT91C_PA28_TCLK1 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC0_CfgPMC -//* \brief Enable Peripheral clock in PMC for TC0 -//*---------------------------------------------------------------------------- -__inline void AT91F_TC0_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TC0)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC0_CfgPIO -//* \brief Configure PIO controllers to drive TC0 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_TC0_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PA0_TIOA0 ) | - ((unsigned int) AT91C_PA1_TIOB0 ) | - ((unsigned int) AT91C_PA4_TCLK0 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgPMC -//* \brief Enable Peripheral clock in PMC for PMC -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgPIO -//* \brief Configure PIO controllers to drive PMC signals -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PA17_PCK1 ) | - ((unsigned int) AT91C_PA21_PCK1 ) | - ((unsigned int) AT91C_PA31_PCK2 ) | - ((unsigned int) AT91C_PA18_PCK2 ) | - ((unsigned int) AT91C_PA6_PCK0 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_CfgPMC -//* \brief Enable Peripheral clock in PMC for ADC -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_ADC)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_CfgPIO -//* \brief Configure PIO controllers to drive ADC signals -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PA8_ADTRG )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIOA_CfgPMC -//* \brief Enable Peripheral clock in PMC for PIOA -//*---------------------------------------------------------------------------- -__inline void AT91F_PIOA_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_PIOA)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_CfgPMC -//* \brief Enable Peripheral clock in PMC for TWI -//*---------------------------------------------------------------------------- -__inline void AT91F_TWI_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TWI)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_CfgPIO -//* \brief Configure PIO controllers to drive TWI signals -//*---------------------------------------------------------------------------- -__inline void AT91F_TWI_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA3_TWD ) | - ((unsigned int) AT91C_PA4_TWCK ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US1_CfgPMC -//* \brief Enable Peripheral clock in PMC for US1 -//*---------------------------------------------------------------------------- -__inline void AT91F_US1_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_US1)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US1_CfgPIO -//* \brief Configure PIO controllers to drive US1 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_US1_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA21_RXD1 ) | - ((unsigned int) AT91C_PA27_DTR1 ) | - ((unsigned int) AT91C_PA26_DCD1 ) | - ((unsigned int) AT91C_PA22_TXD1 ) | - ((unsigned int) AT91C_PA24_RTS1 ) | - ((unsigned int) AT91C_PA23_SCK1 ) | - ((unsigned int) AT91C_PA28_DSR1 ) | - ((unsigned int) AT91C_PA29_RI1 ) | - ((unsigned int) AT91C_PA25_CTS1 ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US0_CfgPMC -//* \brief Enable Peripheral clock in PMC for US0 -//*---------------------------------------------------------------------------- -__inline void AT91F_US0_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_US0)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US0_CfgPIO -//* \brief Configure PIO controllers to drive US0 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_US0_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA5_RXD0 ) | - ((unsigned int) AT91C_PA6_TXD0 ) | - ((unsigned int) AT91C_PA7_RTS0 ) | - ((unsigned int) AT91C_PA8_CTS0 ), // Peripheral A - ((unsigned int) AT91C_PA2_SCK0 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_CfgPMC -//* \brief Enable Peripheral clock in PMC for UDP -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_UDP)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_CfgPMC -//* \brief Enable Peripheral clock in PMC for AIC -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_IRQ0) | - ((unsigned int) 1 << AT91C_ID_FIQ) | - ((unsigned int) 1 << AT91C_ID_IRQ1)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_CfgPIO -//* \brief Configure PIO controllers to drive AIC signals -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA30_IRQ1 ), // Peripheral A - ((unsigned int) AT91C_PA20_IRQ0 ) | - ((unsigned int) AT91C_PA19_FIQ )); // Peripheral B -} - -#endif // lib_AT91SAM7S64_H diff --git a/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h b/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h deleted file mode 100644 index 805a2bce9..000000000 --- a/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h +++ /dev/null @@ -1,4558 +0,0 @@ -//* ---------------------------------------------------------------------------- -//* ATMEL Microcontroller Software Support - ROUSSET - -//* ---------------------------------------------------------------------------- -//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -//* ---------------------------------------------------------------------------- -//* File Name : lib_AT91SAM7X128.h -//* Object : AT91SAM7X128 inlined functions -//* Generated : AT91 SW Application Group 05/20/2005 (16:22:23) -//* -//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// -//* CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005// -//* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005// -//* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004// -//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// -//* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004// -//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// -//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003// -//* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004// -//* CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005// -//* CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005// -//* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// -//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// -//* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004// -//* CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005// -//* CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005// -//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// -//* CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004// -//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// -//* CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003// -//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// -//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002// -//* ---------------------------------------------------------------------------- - -#ifndef lib_AT91SAM7X128_H -#define lib_AT91SAM7X128_H - -/* ***************************************************************************** - SOFTWARE API FOR AIC - ***************************************************************************** */ -#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20] - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_ConfigureIt -//* \brief Interrupt Handler Initialization -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AIC_ConfigureIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id, // \arg interrupt number to initialize - unsigned int priority, // \arg priority to give to the interrupt - unsigned int src_type, // \arg activation and sense of activation - void (*newHandler) (void) ) // \arg address of the interrupt handler -{ - unsigned int oldHandler; - unsigned int mask ; - - oldHandler = pAic->AIC_SVR[irq_id]; - - mask = 0x1 << irq_id ; - //* Disable the interrupt on the interrupt controller - pAic->AIC_IDCR = mask ; - //* Save the interrupt handler routine pointer and the interrupt priority - pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ; - //* Store the Source Mode Register - pAic->AIC_SMR[irq_id] = src_type | priority ; - //* Clear the interrupt on the interrupt controller - pAic->AIC_ICCR = mask ; - - return oldHandler; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_EnableIt -//* \brief Enable corresponding IT number -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_EnableIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id ) // \arg interrupt number to initialize -{ - //* Enable the interrupt on the interrupt controller - pAic->AIC_IECR = 0x1 << irq_id ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_DisableIt -//* \brief Disable corresponding IT number -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_DisableIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id ) // \arg interrupt number to initialize -{ - unsigned int mask = 0x1 << irq_id; - //* Disable the interrupt on the interrupt controller - pAic->AIC_IDCR = mask ; - //* Clear the interrupt on the Interrupt Controller ( if one is pending ) - pAic->AIC_ICCR = mask ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_ClearIt -//* \brief Clear corresponding IT number -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_ClearIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg interrupt number to initialize -{ - //* Clear the interrupt on the Interrupt Controller ( if one is pending ) - pAic->AIC_ICCR = (0x1 << irq_id); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_AcknowledgeIt -//* \brief Acknowledge corresponding IT number -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_AcknowledgeIt ( - AT91PS_AIC pAic) // \arg pointer to the AIC registers -{ - pAic->AIC_EOICR = pAic->AIC_EOICR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_SetExceptionVector -//* \brief Configure vector handler -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AIC_SetExceptionVector ( - unsigned int *pVector, // \arg pointer to the AIC registers - void (*Handler) () ) // \arg Interrupt Handler -{ - unsigned int oldVector = *pVector; - - if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE) - *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE; - else - *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000; - - return oldVector; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_Trig -//* \brief Trig an IT -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_Trig ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg interrupt number -{ - pAic->AIC_ISCR = (0x1 << irq_id) ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_IsActive -//* \brief Test if an IT is active -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AIC_IsActive ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg Interrupt Number -{ - return (pAic->AIC_ISR & (0x1 << irq_id)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_IsPending -//* \brief Test if an IT is pending -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AIC_IsPending ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg Interrupt Number -{ - return (pAic->AIC_IPR & (0x1 << irq_id)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_Open -//* \brief Set exception vectors and AIC registers to default values -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_Open( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - void (*IrqHandler) (), // \arg Default IRQ vector exception - void (*FiqHandler) (), // \arg Default FIQ vector exception - void (*DefaultHandler) (), // \arg Default Handler set in ISR - void (*SpuriousHandler) (), // \arg Default Spurious Handler - unsigned int protectMode) // \arg Debug Control Register -{ - int i; - - // Disable all interrupts and set IVR to the default handler - for (i = 0; i < 32; ++i) { - AT91F_AIC_DisableIt(pAic, i); - AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler); - } - - // Set the IRQ exception vector - AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler); - // Set the Fast Interrupt exception vector - AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler); - - pAic->AIC_SPU = (unsigned int) SpuriousHandler; - pAic->AIC_DCR = protectMode; -} -/* ***************************************************************************** - SOFTWARE API FOR PDC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetNextRx -//* \brief Set the next receive transfer descriptor -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_SetNextRx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be received - unsigned int bytes) // \arg number of bytes to be received -{ - pPDC->PDC_RNPR = (unsigned int) address; - pPDC->PDC_RNCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetNextTx -//* \brief Set the next transmit transfer descriptor -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_SetNextTx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be transmitted - unsigned int bytes) // \arg number of bytes to be transmitted -{ - pPDC->PDC_TNPR = (unsigned int) address; - pPDC->PDC_TNCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetRx -//* \brief Set the receive transfer descriptor -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_SetRx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be received - unsigned int bytes) // \arg number of bytes to be received -{ - pPDC->PDC_RPR = (unsigned int) address; - pPDC->PDC_RCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetTx -//* \brief Set the transmit transfer descriptor -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_SetTx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be transmitted - unsigned int bytes) // \arg number of bytes to be transmitted -{ - pPDC->PDC_TPR = (unsigned int) address; - pPDC->PDC_TCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_EnableTx -//* \brief Enable transmit -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_EnableTx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_TXTEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_EnableRx -//* \brief Enable receive -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_EnableRx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_RXTEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_DisableTx -//* \brief Disable transmit -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_DisableTx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_DisableRx -//* \brief Disable receive -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_DisableRx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsTxEmpty -//* \brief Test if the current transfer descriptor has been sent -//*---------------------------------------------------------------------------- -__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_TCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsNextTxEmpty -//* \brief Test if the next transfer descriptor has been moved to the current td -//*---------------------------------------------------------------------------- -__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_TNCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsRxEmpty -//* \brief Test if the current transfer descriptor has been filled -//*---------------------------------------------------------------------------- -__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_RCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsNextRxEmpty -//* \brief Test if the next transfer descriptor has been moved to the current td -//*---------------------------------------------------------------------------- -__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_RNCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_Open -//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_Open ( - AT91PS_PDC pPDC) // \arg pointer to a PDC controller -{ - //* Disable the RX and TX PDC transfer requests - AT91F_PDC_DisableRx(pPDC); - AT91F_PDC_DisableTx(pPDC); - - //* Reset all Counter register Next buffer first - AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); - AT91F_PDC_SetTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetRx(pPDC, (char *) 0, 0); - - //* Enable the RX and TX PDC transfer requests - AT91F_PDC_EnableRx(pPDC); - AT91F_PDC_EnableTx(pPDC); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_Close -//* \brief Close PDC: disable TX and RX reset transfer descriptors -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_Close ( - AT91PS_PDC pPDC) // \arg pointer to a PDC controller -{ - //* Disable the RX and TX PDC transfer requests - AT91F_PDC_DisableRx(pPDC); - AT91F_PDC_DisableTx(pPDC); - - //* Reset all Counter register Next buffer first - AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); - AT91F_PDC_SetTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetRx(pPDC, (char *) 0, 0); - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SendFrame -//* \brief Close PDC: disable TX and RX reset transfer descriptors -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PDC_SendFrame( - AT91PS_PDC pPDC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - if (AT91F_PDC_IsTxEmpty(pPDC)) { - //* Buffer and next buffer can be initialized - AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer); - AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer); - return 2; - } - else if (AT91F_PDC_IsNextTxEmpty(pPDC)) { - //* Only one buffer can be initialized - AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer); - return 1; - } - else { - //* All buffer are in use... - return 0; - } -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_ReceiveFrame -//* \brief Close PDC: disable TX and RX reset transfer descriptors -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PDC_ReceiveFrame ( - AT91PS_PDC pPDC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - if (AT91F_PDC_IsRxEmpty(pPDC)) { - //* Buffer and next buffer can be initialized - AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer); - AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer); - return 2; - } - else if (AT91F_PDC_IsNextRxEmpty(pPDC)) { - //* Only one buffer can be initialized - AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer); - return 1; - } - else { - //* All buffer are in use... - return 0; - } -} -/* ***************************************************************************** - SOFTWARE API FOR DBGU - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_InterruptEnable -//* \brief Enable DBGU Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_DBGU_InterruptEnable( - AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller - unsigned int flag) // \arg dbgu interrupt to be enabled -{ - pDbgu->DBGU_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_InterruptDisable -//* \brief Disable DBGU Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_DBGU_InterruptDisable( - AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller - unsigned int flag) // \arg dbgu interrupt to be disabled -{ - pDbgu->DBGU_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_GetInterruptMaskStatus -//* \brief Return DBGU Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status - AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller -{ - return pDbgu->DBGU_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_IsInterruptMasked -//* \brief Test if DBGU Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_DBGU_IsInterruptMasked( - AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR PIO - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgPeriph -//* \brief Enable pins to be drived by peripheral -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgPeriph( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int periphAEnable, // \arg PERIPH A to enable - unsigned int periphBEnable) // \arg PERIPH B to enable - -{ - pPio->PIO_ASR = periphAEnable; - pPio->PIO_BSR = periphBEnable; - pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgOutput -//* \brief Enable PIO in output mode -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int pioEnable) // \arg PIO to be enabled -{ - pPio->PIO_PER = pioEnable; // Set in PIO mode - pPio->PIO_OER = pioEnable; // Configure in Output -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgInput -//* \brief Enable PIO in input mode -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgInput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int inputEnable) // \arg PIO to be enabled -{ - // Disable output - pPio->PIO_ODR = inputEnable; - pPio->PIO_PER = inputEnable; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgOpendrain -//* \brief Configure PIO in open drain -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgOpendrain( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int multiDrvEnable) // \arg pio to be configured in open drain -{ - // Configure the multi-drive option - pPio->PIO_MDDR = ~multiDrvEnable; - pPio->PIO_MDER = multiDrvEnable; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgPullup -//* \brief Enable pullup on PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgPullup( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int pullupEnable) // \arg enable pullup on PIO -{ - // Connect or not Pullup - pPio->PIO_PPUDR = ~pullupEnable; - pPio->PIO_PPUER = pullupEnable; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgDirectDrive -//* \brief Enable direct drive on PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgDirectDrive( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int directDrive) // \arg PIO to be configured with direct drive - -{ - // Configure the Direct Drive - pPio->PIO_OWDR = ~directDrive; - pPio->PIO_OWER = directDrive; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgInputFilter -//* \brief Enable input filter on input PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgInputFilter( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int inputFilter) // \arg PIO to be configured with input filter - -{ - // Configure the Direct Drive - pPio->PIO_IFDR = ~inputFilter; - pPio->PIO_IFER = inputFilter; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInput -//* \brief Return PIO input value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetInput( // \return PIO input - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_PDSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInputSet -//* \brief Test if PIO is input flag is active -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsInputSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInput(pPio) & flag); -} - - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_SetOutput -//* \brief Set to 1 output PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_SetOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg output to be set -{ - pPio->PIO_SODR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_ClearOutput -//* \brief Set to 0 output PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_ClearOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg output to be cleared -{ - pPio->PIO_CODR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_ForceOutput -//* \brief Force output when Direct drive option is enabled -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_ForceOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg output to be forced -{ - pPio->PIO_ODSR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_Enable -//* \brief Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_Enable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be enabled -{ - pPio->PIO_PER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_Disable -//* \brief Disable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_Disable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be disabled -{ - pPio->PIO_PDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetStatus -//* \brief Return PIO Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_PSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsSet -//* \brief Test if PIO is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputEnable -//* \brief Output Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_OutputEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output to be enabled -{ - pPio->PIO_OER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputDisable -//* \brief Output Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_OutputDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output to be disabled -{ - pPio->PIO_ODR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetOutputStatus -//* \brief Return PIO Output Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_OSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsOuputSet -//* \brief Test if PIO Output is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsOutputSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetOutputStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InputFilterEnable -//* \brief Input Filter Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_InputFilterEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio input filter to be enabled -{ - pPio->PIO_IFER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InputFilterDisable -//* \brief Input Filter Disable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_InputFilterDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio input filter to be disabled -{ - pPio->PIO_IFDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInputFilterStatus -//* \brief Return PIO Input Filter Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_IFSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInputFilterSet -//* \brief Test if PIO Input filter is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsInputFilterSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInputFilterStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetOutputDataStatus -//* \brief Return PIO Output Data Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_ODSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InterruptEnable -//* \brief Enable PIO Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_InterruptEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio interrupt to be enabled -{ - pPio->PIO_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InterruptDisable -//* \brief Disable PIO Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_InterruptDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio interrupt to be disabled -{ - pPio->PIO_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInterruptMaskStatus -//* \brief Return PIO Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInterruptStatus -//* \brief Return PIO Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_ISR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInterruptMasked -//* \brief Test if PIO Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsInterruptMasked( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInterruptSet -//* \brief Test if PIO Interrupt is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsInterruptSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInterruptStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_MultiDriverEnable -//* \brief Multi Driver Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_MultiDriverEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be enabled -{ - pPio->PIO_MDER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_MultiDriverDisable -//* \brief Multi Driver Disable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_MultiDriverDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be disabled -{ - pPio->PIO_MDDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetMultiDriverStatus -//* \brief Return PIO Multi Driver Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_MDSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsMultiDriverSet -//* \brief Test if PIO MultiDriver is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsMultiDriverSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_A_RegisterSelection -//* \brief PIO A Register Selection -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_A_RegisterSelection( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio A register selection -{ - pPio->PIO_ASR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_B_RegisterSelection -//* \brief PIO B Register Selection -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_B_RegisterSelection( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio B register selection -{ - pPio->PIO_BSR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_Get_AB_RegisterStatus -//* \brief Return PIO Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_ABSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsAB_RegisterSet -//* \brief Test if PIO AB Register is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsAB_RegisterSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputWriteEnable -//* \brief Output Write Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_OutputWriteEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output write to be enabled -{ - pPio->PIO_OWER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputWriteDisable -//* \brief Output Write Disable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_OutputWriteDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output write to be disabled -{ - pPio->PIO_OWDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetOutputWriteStatus -//* \brief Return PIO Output Write Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_OWSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsOutputWriteSet -//* \brief Test if PIO OutputWrite is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsOutputWriteSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetCfgPullup -//* \brief Return PIO Configuration Pullup -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_PPUSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsOutputDataStatusSet -//* \brief Test if PIO Output Data Status is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsOutputDataStatusSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetOutputDataStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsCfgPullupStatusSet -//* \brief Test if PIO Configuration Pullup Status is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsCfgPullupStatusSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (~AT91F_PIO_GetCfgPullup(pPio) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR PMC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgSysClkEnableReg -//* \brief Configure the System Clock Enable Register of the PMC controller -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_CfgSysClkEnableReg ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int mode) -{ - //* Write to the SCER register - pPMC->PMC_SCER = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgSysClkDisableReg -//* \brief Configure the System Clock Disable Register of the PMC controller -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_CfgSysClkDisableReg ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int mode) -{ - //* Write to the SCDR register - pPMC->PMC_SCDR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetSysClkStatusReg -//* \brief Return the System Clock Status Register of the PMC controller -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetSysClkStatusReg ( - AT91PS_PMC pPMC // pointer to a CAN controller - ) -{ - return pPMC->PMC_SCSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_EnablePeriphClock -//* \brief Enable peripheral clock -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_EnablePeriphClock ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int periphIds) // \arg IDs of peripherals to enable -{ - pPMC->PMC_PCER = periphIds; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_DisablePeriphClock -//* \brief Disable peripheral clock -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_DisablePeriphClock ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int periphIds) // \arg IDs of peripherals to enable -{ - pPMC->PMC_PCDR = periphIds; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetPeriphClock -//* \brief Get peripheral clock status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetPeriphClock ( - AT91PS_PMC pPMC) // \arg pointer to PMC controller -{ - return pPMC->PMC_PCSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_CfgMainOscillatorReg -//* \brief Cfg the main oscillator -//*---------------------------------------------------------------------------- -__inline void AT91F_CKGR_CfgMainOscillatorReg ( - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int mode) -{ - pCKGR->CKGR_MOR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_GetMainOscillatorReg -//* \brief Cfg the main oscillator -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CKGR_GetMainOscillatorReg ( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller -{ - return pCKGR->CKGR_MOR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_EnableMainOscillator -//* \brief Enable the main oscillator -//*---------------------------------------------------------------------------- -__inline void AT91F_CKGR_EnableMainOscillator( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller -{ - pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_DisableMainOscillator -//* \brief Disable the main oscillator -//*---------------------------------------------------------------------------- -__inline void AT91F_CKGR_DisableMainOscillator ( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller -{ - pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_CfgMainOscStartUpTime -//* \brief Cfg MOR Register according to the main osc startup time -//*---------------------------------------------------------------------------- -__inline void AT91F_CKGR_CfgMainOscStartUpTime ( - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int startup_time, // \arg main osc startup time in microsecond (us) - unsigned int slowClock) // \arg slowClock in Hz -{ - pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT; - pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_GetMainClockFreqReg -//* \brief Cfg the main oscillator -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CKGR_GetMainClockFreqReg ( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller -{ - return pCKGR->CKGR_MCFR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_GetMainClock -//* \brief Return Main clock in Hz -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CKGR_GetMainClock ( - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int slowClock) // \arg slowClock in Hz -{ - return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgMCKReg -//* \brief Cfg Master Clock Register -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_CfgMCKReg ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int mode) -{ - pPMC->PMC_MCKR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetMCKReg -//* \brief Return Master Clock Register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetMCKReg( - AT91PS_PMC pPMC) // \arg pointer to PMC controller -{ - return pPMC->PMC_MCKR; -} - -//*------------------------------------------------------------------------------ -//* \fn AT91F_PMC_GetMasterClock -//* \brief Return master clock in Hz which correponds to processor clock for ARM7 -//*------------------------------------------------------------------------------ -__inline unsigned int AT91F_PMC_GetMasterClock ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int slowClock) // \arg slowClock in Hz -{ - unsigned int reg = pPMC->PMC_MCKR; - unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2)); - unsigned int pllDivider, pllMultiplier; - - switch (reg & AT91C_PMC_CSS) { - case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected - return slowClock / prescaler; - case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected - return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler; - case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected - reg = pCKGR->CKGR_PLLR; - pllDivider = (reg & AT91C_CKGR_DIV); - pllMultiplier = ((reg & AT91C_CKGR_MUL) >> 16) + 1; - return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler; - } - return 0; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_EnablePCK -//* \brief Enable peripheral clock -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_EnablePCK ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int pck, // \arg Peripheral clock identifier 0 .. 7 - unsigned int mode) -{ - pPMC->PMC_PCKR[pck] = mode; - pPMC->PMC_SCER = (1 << pck) << 8; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_DisablePCK -//* \brief Enable peripheral clock -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_DisablePCK ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int pck) // \arg Peripheral clock identifier 0 .. 7 -{ - pPMC->PMC_SCDR = (1 << pck) << 8; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_EnableIt -//* \brief Enable PMC interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_EnableIt ( - AT91PS_PMC pPMC, // pointer to a PMC controller - unsigned int flag) // IT to be enabled -{ - //* Write to the IER register - pPMC->PMC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_DisableIt -//* \brief Disable PMC interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_DisableIt ( - AT91PS_PMC pPMC, // pointer to a PMC controller - unsigned int flag) // IT to be disabled -{ - //* Write to the IDR register - pPMC->PMC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetStatus -//* \brief Return PMC Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status - AT91PS_PMC pPMC) // pointer to a PMC controller -{ - return pPMC->PMC_SR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetInterruptMaskStatus -//* \brief Return PMC Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status - AT91PS_PMC pPMC) // pointer to a PMC controller -{ - return pPMC->PMC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_IsInterruptMasked -//* \brief Test if PMC Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_IsInterruptMasked( - AT91PS_PMC pPMC, // \arg pointer to a PMC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_IsStatusSet -//* \brief Test if PMC Status is Set -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_IsStatusSet( - AT91PS_PMC pPMC, // \arg pointer to a PMC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PMC_GetStatus(pPMC) & flag); -}/* ***************************************************************************** - SOFTWARE API FOR RSTC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTSoftReset -//* \brief Start Software Reset -//*---------------------------------------------------------------------------- -__inline void AT91F_RSTSoftReset( - AT91PS_RSTC pRSTC, - unsigned int reset) -{ - pRSTC->RSTC_RCR = (0xA5000000 | reset); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTSetMode -//* \brief Set Reset Mode -//*---------------------------------------------------------------------------- -__inline void AT91F_RSTSetMode( - AT91PS_RSTC pRSTC, - unsigned int mode) -{ - pRSTC->RSTC_RMR = (0xA5000000 | mode); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTGetMode -//* \brief Get Reset Mode -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_RSTGetMode( - AT91PS_RSTC pRSTC) -{ - return (pRSTC->RSTC_RMR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTGetStatus -//* \brief Get Reset Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_RSTGetStatus( - AT91PS_RSTC pRSTC) -{ - return (pRSTC->RSTC_RSR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTIsSoftRstActive -//* \brief Return !=0 if software reset is still not completed -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_RSTIsSoftRstActive( - AT91PS_RSTC pRSTC) -{ - return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP); -} -/* ***************************************************************************** - SOFTWARE API FOR RTTC - ***************************************************************************** */ -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_SetRTT_TimeBase() -//* \brief Set the RTT prescaler according to the TimeBase in ms -//*-------------------------------------------------------------------------------------- -__inline unsigned int AT91F_RTTSetTimeBase( - AT91PS_RTTC pRTTC, - unsigned int ms) -{ - if (ms > 2000) - return 1; // AT91C_TIME_OUT_OF_RANGE - pRTTC->RTTC_RTMR &= ~0xFFFF; - pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF); - return 0; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTTSetPrescaler() -//* \brief Set the new prescaler value -//*-------------------------------------------------------------------------------------- -__inline unsigned int AT91F_RTTSetPrescaler( - AT91PS_RTTC pRTTC, - unsigned int rtpres) -{ - pRTTC->RTTC_RTMR &= ~0xFFFF; - pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF); - return (pRTTC->RTTC_RTMR); -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTTRestart() -//* \brief Restart the RTT prescaler -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTRestart( - AT91PS_RTTC pRTTC) -{ - pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST; -} - - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_SetAlarmINT() -//* \brief Enable RTT Alarm Interrupt -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTSetAlarmINT( - AT91PS_RTTC pRTTC) -{ - pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_ClearAlarmINT() -//* \brief Disable RTT Alarm Interrupt -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTClearAlarmINT( - AT91PS_RTTC pRTTC) -{ - pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_SetRttIncINT() -//* \brief Enable RTT INC Interrupt -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTSetRttIncINT( - AT91PS_RTTC pRTTC) -{ - pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_ClearRttIncINT() -//* \brief Disable RTT INC Interrupt -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTClearRttIncINT( - AT91PS_RTTC pRTTC) -{ - pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_SetAlarmValue() -//* \brief Set RTT Alarm Value -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTSetAlarmValue( - AT91PS_RTTC pRTTC, unsigned int alarm) -{ - pRTTC->RTTC_RTAR = alarm; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_GetAlarmValue() -//* \brief Get RTT Alarm Value -//*-------------------------------------------------------------------------------------- -__inline unsigned int AT91F_RTTGetAlarmValue( - AT91PS_RTTC pRTTC) -{ - return(pRTTC->RTTC_RTAR); -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTTGetStatus() -//* \brief Read the RTT status -//*-------------------------------------------------------------------------------------- -__inline unsigned int AT91F_RTTGetStatus( - AT91PS_RTTC pRTTC) -{ - return(pRTTC->RTTC_RTSR); -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_ReadValue() -//* \brief Read the RTT value -//*-------------------------------------------------------------------------------------- -__inline unsigned int AT91F_RTTReadValue( - AT91PS_RTTC pRTTC) -{ - register volatile unsigned int val1,val2; - do - { - val1 = pRTTC->RTTC_RTVR; - val2 = pRTTC->RTTC_RTVR; - } - while(val1 != val2); - return(val1); -} -/* ***************************************************************************** - SOFTWARE API FOR PITC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITInit -//* \brief System timer init : period in µsecond, system clock freq in MHz -//*---------------------------------------------------------------------------- -__inline void AT91F_PITInit( - AT91PS_PITC pPITC, - unsigned int period, - unsigned int pit_frequency) -{ - pPITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0; // +8 to avoid %10 and /10 - pPITC->PITC_PIMR |= AT91C_PITC_PITEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITSetPIV -//* \brief Set the PIT Periodic Interval Value -//*---------------------------------------------------------------------------- -__inline void AT91F_PITSetPIV( - AT91PS_PITC pPITC, - unsigned int piv) -{ - pPITC->PITC_PIMR = piv | (pPITC->PITC_PIMR & (AT91C_PITC_PITEN | AT91C_PITC_PITIEN)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITEnableInt -//* \brief Enable PIT periodic interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PITEnableInt( - AT91PS_PITC pPITC) -{ - pPITC->PITC_PIMR |= AT91C_PITC_PITIEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITDisableInt -//* \brief Disable PIT periodic interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PITDisableInt( - AT91PS_PITC pPITC) -{ - pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITGetMode -//* \brief Read PIT mode register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PITGetMode( - AT91PS_PITC pPITC) -{ - return(pPITC->PITC_PIMR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITGetStatus -//* \brief Read PIT status register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PITGetStatus( - AT91PS_PITC pPITC) -{ - return(pPITC->PITC_PISR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITGetPIIR -//* \brief Read PIT CPIV and PICNT without ressetting the counters -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PITGetPIIR( - AT91PS_PITC pPITC) -{ - return(pPITC->PITC_PIIR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITGetPIVR -//* \brief Read System timer CPIV and PICNT without ressetting the counters -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PITGetPIVR( - AT91PS_PITC pPITC) -{ - return(pPITC->PITC_PIVR); -} -/* ***************************************************************************** - SOFTWARE API FOR WDTC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_WDTSetMode -//* \brief Set Watchdog Mode Register -//*---------------------------------------------------------------------------- -__inline void AT91F_WDTSetMode( - AT91PS_WDTC pWDTC, - unsigned int Mode) -{ - pWDTC->WDTC_WDMR = Mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_WDTRestart -//* \brief Restart Watchdog -//*---------------------------------------------------------------------------- -__inline void AT91F_WDTRestart( - AT91PS_WDTC pWDTC) -{ - pWDTC->WDTC_WDCR = 0xA5000001; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_WDTSGettatus -//* \brief Get Watchdog Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_WDTSGettatus( - AT91PS_WDTC pWDTC) -{ - return(pWDTC->WDTC_WDSR & 0x3); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_WDTGetPeriod -//* \brief Translate ms into Watchdog Compatible value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_WDTGetPeriod(unsigned int ms) -{ - if ((ms < 4) || (ms > 16000)) - return 0; - return((ms << 8) / 1000); -} -/* ***************************************************************************** - SOFTWARE API FOR VREG - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_VREG_Enable_LowPowerMode -//* \brief Enable VREG Low Power Mode -//*---------------------------------------------------------------------------- -__inline void AT91F_VREG_Enable_LowPowerMode( - AT91PS_VREG pVREG) -{ - pVREG->VREG_MR |= AT91C_VREG_PSTDBY; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_VREG_Disable_LowPowerMode -//* \brief Disable VREG Low Power Mode -//*---------------------------------------------------------------------------- -__inline void AT91F_VREG_Disable_LowPowerMode( - AT91PS_VREG pVREG) -{ - pVREG->VREG_MR &= ~AT91C_VREG_PSTDBY; -}/* ***************************************************************************** - SOFTWARE API FOR MC - ***************************************************************************** */ - -#define AT91C_MC_CORRECT_KEY ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_Remap -//* \brief Make Remap -//*---------------------------------------------------------------------------- -__inline void AT91F_MC_Remap (void) // -{ - AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC; - - pMC->MC_RCR = AT91C_MC_RCB; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_CfgModeReg -//* \brief Configure the EFC Mode Register of the MC controller -//*---------------------------------------------------------------------------- -__inline void AT91F_MC_EFC_CfgModeReg ( - AT91PS_MC pMC, // pointer to a MC controller - unsigned int mode) // mode register -{ - // Write to the FMR register - pMC->MC_FMR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_GetModeReg -//* \brief Return MC EFC Mode Regsiter -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MC_EFC_GetModeReg( - AT91PS_MC pMC) // pointer to a MC controller -{ - return pMC->MC_FMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_ComputeFMCN -//* \brief Return MC EFC Mode Regsiter -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MC_EFC_ComputeFMCN( - int master_clock) // master clock in Hz -{ - return (master_clock/1000000 +2); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_PerformCmd -//* \brief Perform EFC Command -//*---------------------------------------------------------------------------- -__inline void AT91F_MC_EFC_PerformCmd ( - AT91PS_MC pMC, // pointer to a MC controller - unsigned int transfer_cmd) -{ - pMC->MC_FCR = transfer_cmd; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_GetStatus -//* \brief Return MC EFC Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MC_EFC_GetStatus( - AT91PS_MC pMC) // pointer to a MC controller -{ - return pMC->MC_FSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_IsInterruptMasked -//* \brief Test if EFC MC Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MC_EFC_IsInterruptMasked( - AT91PS_MC pMC, // \arg pointer to a MC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_MC_EFC_GetModeReg(pMC) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_IsInterruptSet -//* \brief Test if EFC MC Interrupt is Set -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MC_EFC_IsInterruptSet( - AT91PS_MC pMC, // \arg pointer to a MC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_MC_EFC_GetStatus(pMC) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR SPI - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Open -//* \brief Open a SPI Port -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SPI_Open ( - const unsigned int null) // \arg -{ - /* NOT DEFINED AT THIS MOMENT */ - return ( 0 ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_CfgCs -//* \brief Configure SPI chip select register -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_CfgCs ( - AT91PS_SPI pSPI, // pointer to a SPI controller - int cs, // SPI cs number (0 to 3) - int val) // chip select register -{ - //* Write to the CSR register - *(pSPI->SPI_CSR + cs) = val; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_EnableIt -//* \brief Enable SPI interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_EnableIt ( - AT91PS_SPI pSPI, // pointer to a SPI controller - unsigned int flag) // IT to be enabled -{ - //* Write to the IER register - pSPI->SPI_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_DisableIt -//* \brief Disable SPI interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_DisableIt ( - AT91PS_SPI pSPI, // pointer to a SPI controller - unsigned int flag) // IT to be disabled -{ - //* Write to the IDR register - pSPI->SPI_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Reset -//* \brief Reset the SPI controller -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_Reset ( - AT91PS_SPI pSPI // pointer to a SPI controller - ) -{ - //* Write to the CR register - pSPI->SPI_CR = AT91C_SPI_SWRST; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Enable -//* \brief Enable the SPI controller -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_Enable ( - AT91PS_SPI pSPI // pointer to a SPI controller - ) -{ - //* Write to the CR register - pSPI->SPI_CR = AT91C_SPI_SPIEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Disable -//* \brief Disable the SPI controller -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_Disable ( - AT91PS_SPI pSPI // pointer to a SPI controller - ) -{ - //* Write to the CR register - pSPI->SPI_CR = AT91C_SPI_SPIDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_CfgMode -//* \brief Enable the SPI controller -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_CfgMode ( - AT91PS_SPI pSPI, // pointer to a SPI controller - int mode) // mode register -{ - //* Write to the MR register - pSPI->SPI_MR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_CfgPCS -//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_CfgPCS ( - AT91PS_SPI pSPI, // pointer to a SPI controller - char PCS_Device) // PCS of the Device -{ - //* Write to the MR register - pSPI->SPI_MR &= 0xFFF0FFFF; - pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_ReceiveFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SPI_ReceiveFrame ( - AT91PS_SPI pSPI, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_ReceiveFrame( - (AT91PS_PDC) &(pSPI->SPI_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_SendFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SPI_SendFrame( - AT91PS_SPI pSPI, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_SendFrame( - (AT91PS_PDC) &(pSPI->SPI_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Close -//* \brief Close SPI: disable IT disable transfert, close PDC -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_Close ( - AT91PS_SPI pSPI) // \arg pointer to a SPI controller -{ - //* Reset all the Chip Select register - pSPI->SPI_CSR[0] = 0 ; - pSPI->SPI_CSR[1] = 0 ; - pSPI->SPI_CSR[2] = 0 ; - pSPI->SPI_CSR[3] = 0 ; - - //* Reset the SPI mode - pSPI->SPI_MR = 0 ; - - //* Disable all interrupts - pSPI->SPI_IDR = 0xFFFFFFFF ; - - //* Abort the Peripheral Data Transfers - AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR)); - - //* Disable receiver and transmitter and stop any activity immediately - pSPI->SPI_CR = AT91C_SPI_SPIDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_PutChar -//* \brief Send a character,does not check if ready to send -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_PutChar ( - AT91PS_SPI pSPI, - unsigned int character, - unsigned int cs_number ) -{ - unsigned int value_for_cs; - value_for_cs = (~(1 << cs_number)) & 0xF; //Place a zero among a 4 ONEs number - pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_GetChar -//* \brief Receive a character,does not check if a character is available -//*---------------------------------------------------------------------------- -__inline int AT91F_SPI_GetChar ( - const AT91PS_SPI pSPI) -{ - return((pSPI->SPI_RDR) & 0xFFFF); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_GetInterruptMaskStatus -//* \brief Return SPI Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status - AT91PS_SPI pSpi) // \arg pointer to a SPI controller -{ - return pSpi->SPI_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_IsInterruptMasked -//* \brief Test if SPI Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_SPI_IsInterruptMasked( - AT91PS_SPI pSpi, // \arg pointer to a SPI controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR USART - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Baudrate -//* \brief Calculate the baudrate -//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity -#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_NONE + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CLKS_CLOCK ) - -//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity -#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_NONE + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CLKS_EXT ) - -//* Standard Synchronous Mode : 8 bits , 1 stop , no parity -#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \ - AT91C_US_USMODE_NORMAL + \ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_NONE + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CLKS_CLOCK ) - -//* SCK used Label -#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT) - -//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity -#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \ - AT91C_US_CLKS_CLOCK +\ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_EVEN + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CKLO +\ - AT91C_US_OVER) - -//* Standard IRDA mode -#define AT91C_US_ASYNC_IRDA_MODE ( AT91C_US_USMODE_IRDA + \ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_NONE + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CLKS_CLOCK ) - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Baudrate -//* \brief Caluculate baud_value according to the main clock and the baud rate -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_US_Baudrate ( - const unsigned int main_clock, // \arg peripheral clock - const unsigned int baud_rate) // \arg UART baudrate -{ - unsigned int baud_value = ((main_clock*10)/(baud_rate * 16)); - if ((baud_value % 10) >= 5) - baud_value = (baud_value / 10) + 1; - else - baud_value /= 10; - return baud_value; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_SetBaudrate -//* \brief Set the baudrate according to the CPU clock -//*---------------------------------------------------------------------------- -__inline void AT91F_US_SetBaudrate ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int mainClock, // \arg peripheral clock - unsigned int speed) // \arg UART baudrate -{ - //* Define the baud rate divisor register - pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_SetTimeguard -//* \brief Set USART timeguard -//*---------------------------------------------------------------------------- -__inline void AT91F_US_SetTimeguard ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int timeguard) // \arg timeguard value -{ - //* Write the Timeguard Register - pUSART->US_TTGR = timeguard ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_EnableIt -//* \brief Enable USART IT -//*---------------------------------------------------------------------------- -__inline void AT91F_US_EnableIt ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int flag) // \arg IT to be enabled -{ - //* Write to the IER register - pUSART->US_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_DisableIt -//* \brief Disable USART IT -//*---------------------------------------------------------------------------- -__inline void AT91F_US_DisableIt ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int flag) // \arg IT to be disabled -{ - //* Write to the IER register - pUSART->US_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Configure -//* \brief Configure USART -//*---------------------------------------------------------------------------- -__inline void AT91F_US_Configure ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int mainClock, // \arg peripheral clock - unsigned int mode , // \arg mode Register to be programmed - unsigned int baudRate , // \arg baudrate to be programmed - unsigned int timeguard ) // \arg timeguard to be programmed -{ - //* Disable interrupts - pUSART->US_IDR = (unsigned int) -1; - - //* Reset receiver and transmitter - pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ; - - //* Define the baud rate divisor register - AT91F_US_SetBaudrate(pUSART, mainClock, baudRate); - - //* Write the Timeguard Register - AT91F_US_SetTimeguard(pUSART, timeguard); - - //* Clear Transmit and Receive Counters - AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR)); - - //* Define the USART mode - pUSART->US_MR = mode ; - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_EnableRx -//* \brief Enable receiving characters -//*---------------------------------------------------------------------------- -__inline void AT91F_US_EnableRx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Enable receiver - pUSART->US_CR = AT91C_US_RXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_EnableTx -//* \brief Enable sending characters -//*---------------------------------------------------------------------------- -__inline void AT91F_US_EnableTx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Enable transmitter - pUSART->US_CR = AT91C_US_TXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_ResetRx -//* \brief Reset Receiver and re-enable it -//*---------------------------------------------------------------------------- -__inline void AT91F_US_ResetRx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Reset receiver - pUSART->US_CR = AT91C_US_RSTRX; - //* Re-Enable receiver - pUSART->US_CR = AT91C_US_RXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_ResetTx -//* \brief Reset Transmitter and re-enable it -//*---------------------------------------------------------------------------- -__inline void AT91F_US_ResetTx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Reset transmitter - pUSART->US_CR = AT91C_US_RSTTX; - //* Enable transmitter - pUSART->US_CR = AT91C_US_TXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_DisableRx -//* \brief Disable Receiver -//*---------------------------------------------------------------------------- -__inline void AT91F_US_DisableRx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Disable receiver - pUSART->US_CR = AT91C_US_RXDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_DisableTx -//* \brief Disable Transmitter -//*---------------------------------------------------------------------------- -__inline void AT91F_US_DisableTx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Disable transmitter - pUSART->US_CR = AT91C_US_TXDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Close -//* \brief Close USART: disable IT disable receiver and transmitter, close PDC -//*---------------------------------------------------------------------------- -__inline void AT91F_US_Close ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Reset the baud rate divisor register - pUSART->US_BRGR = 0 ; - - //* Reset the USART mode - pUSART->US_MR = 0 ; - - //* Reset the Timeguard Register - pUSART->US_TTGR = 0; - - //* Disable all interrupts - pUSART->US_IDR = 0xFFFFFFFF ; - - //* Abort the Peripheral Data Transfers - AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR)); - - //* Disable receiver and transmitter and stop any activity immediately - pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_TxReady -//* \brief Return 1 if a character can be written in US_THR -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_US_TxReady ( - AT91PS_USART pUSART ) // \arg pointer to a USART controller -{ - return (pUSART->US_CSR & AT91C_US_TXRDY); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_RxReady -//* \brief Return 1 if a character can be read in US_RHR -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_US_RxReady ( - AT91PS_USART pUSART ) // \arg pointer to a USART controller -{ - return (pUSART->US_CSR & AT91C_US_RXRDY); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Error -//* \brief Return the error flag -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_US_Error ( - AT91PS_USART pUSART ) // \arg pointer to a USART controller -{ - return (pUSART->US_CSR & - (AT91C_US_OVRE | // Overrun error - AT91C_US_FRAME | // Framing error - AT91C_US_PARE)); // Parity error -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_PutChar -//* \brief Send a character,does not check if ready to send -//*---------------------------------------------------------------------------- -__inline void AT91F_US_PutChar ( - AT91PS_USART pUSART, - int character ) -{ - pUSART->US_THR = (character & 0x1FF); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_GetChar -//* \brief Receive a character,does not check if a character is available -//*---------------------------------------------------------------------------- -__inline int AT91F_US_GetChar ( - const AT91PS_USART pUSART) -{ - return((pUSART->US_RHR) & 0x1FF); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_SendFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_US_SendFrame( - AT91PS_USART pUSART, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_SendFrame( - (AT91PS_PDC) &(pUSART->US_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_ReceiveFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_US_ReceiveFrame ( - AT91PS_USART pUSART, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_ReceiveFrame( - (AT91PS_PDC) &(pUSART->US_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_SetIrdaFilter -//* \brief Set the value of IrDa filter tregister -//*---------------------------------------------------------------------------- -__inline void AT91F_US_SetIrdaFilter ( - AT91PS_USART pUSART, - unsigned char value -) -{ - pUSART->US_IF = value; -} - -/* ***************************************************************************** - SOFTWARE API FOR SSC - ***************************************************************************** */ -//* Define the standard I2S mode configuration - -//* Configuration to set in the SSC Transmit Clock Mode Register -//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits -//* nb_slot_by_frame : number of channels -#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ - AT91C_SSC_CKS_DIV +\ - AT91C_SSC_CKO_CONTINOUS +\ - AT91C_SSC_CKG_NONE +\ - AT91C_SSC_START_FALL_RF +\ - AT91C_SSC_STTOUT +\ - ((1<<16) & AT91C_SSC_STTDLY) +\ - ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24)) - - -//* Configuration to set in the SSC Transmit Frame Mode Register -//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits -//* nb_slot_by_frame : number of channels -#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ - (nb_bit_by_slot-1) +\ - AT91C_SSC_MSBF +\ - (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\ - (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\ - AT91C_SSC_FSOS_NEGATIVE) - - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_SetBaudrate -//* \brief Set the baudrate according to the CPU clock -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_SetBaudrate ( - AT91PS_SSC pSSC, // \arg pointer to a SSC controller - unsigned int mainClock, // \arg peripheral clock - unsigned int speed) // \arg SSC baudrate -{ - unsigned int baud_value; - //* Define the baud rate divisor register - if (speed == 0) - baud_value = 0; - else - { - baud_value = (unsigned int) (mainClock * 10)/(2*speed); - if ((baud_value % 10) >= 5) - baud_value = (baud_value / 10) + 1; - else - baud_value /= 10; - } - - pSSC->SSC_CMR = baud_value; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_Configure -//* \brief Configure SSC -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_Configure ( - AT91PS_SSC pSSC, // \arg pointer to a SSC controller - unsigned int syst_clock, // \arg System Clock Frequency - unsigned int baud_rate, // \arg Expected Baud Rate Frequency - unsigned int clock_rx, // \arg Receiver Clock Parameters - unsigned int mode_rx, // \arg mode Register to be programmed - unsigned int clock_tx, // \arg Transmitter Clock Parameters - unsigned int mode_tx) // \arg mode Register to be programmed -{ - //* Disable interrupts - pSSC->SSC_IDR = (unsigned int) -1; - - //* Reset receiver and transmitter - pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ; - - //* Define the Clock Mode Register - AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate); - - //* Write the Receive Clock Mode Register - pSSC->SSC_RCMR = clock_rx; - - //* Write the Transmit Clock Mode Register - pSSC->SSC_TCMR = clock_tx; - - //* Write the Receive Frame Mode Register - pSSC->SSC_RFMR = mode_rx; - - //* Write the Transmit Frame Mode Register - pSSC->SSC_TFMR = mode_tx; - - //* Clear Transmit and Receive Counters - AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR)); - - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_EnableRx -//* \brief Enable receiving datas -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_EnableRx ( - AT91PS_SSC pSSC) // \arg pointer to a SSC controller -{ - //* Enable receiver - pSSC->SSC_CR = AT91C_SSC_RXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_DisableRx -//* \brief Disable receiving datas -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_DisableRx ( - AT91PS_SSC pSSC) // \arg pointer to a SSC controller -{ - //* Disable receiver - pSSC->SSC_CR = AT91C_SSC_RXDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_EnableTx -//* \brief Enable sending datas -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_EnableTx ( - AT91PS_SSC pSSC) // \arg pointer to a SSC controller -{ - //* Enable transmitter - pSSC->SSC_CR = AT91C_SSC_TXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_DisableTx -//* \brief Disable sending datas -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_DisableTx ( - AT91PS_SSC pSSC) // \arg pointer to a SSC controller -{ - //* Disable transmitter - pSSC->SSC_CR = AT91C_SSC_TXDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_EnableIt -//* \brief Enable SSC IT -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_EnableIt ( - AT91PS_SSC pSSC, // \arg pointer to a SSC controller - unsigned int flag) // \arg IT to be enabled -{ - //* Write to the IER register - pSSC->SSC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_DisableIt -//* \brief Disable SSC IT -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_DisableIt ( - AT91PS_SSC pSSC, // \arg pointer to a SSC controller - unsigned int flag) // \arg IT to be disabled -{ - //* Write to the IDR register - pSSC->SSC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_ReceiveFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SSC_ReceiveFrame ( - AT91PS_SSC pSSC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_ReceiveFrame( - (AT91PS_PDC) &(pSSC->SSC_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_SendFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SSC_SendFrame( - AT91PS_SSC pSSC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_SendFrame( - (AT91PS_PDC) &(pSSC->SSC_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_GetInterruptMaskStatus -//* \brief Return SSC Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status - AT91PS_SSC pSsc) // \arg pointer to a SSC controller -{ - return pSsc->SSC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_IsInterruptMasked -//* \brief Test if SSC Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_SSC_IsInterruptMasked( - AT91PS_SSC pSsc, // \arg pointer to a SSC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR TWI - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_EnableIt -//* \brief Enable TWI IT -//*---------------------------------------------------------------------------- -__inline void AT91F_TWI_EnableIt ( - AT91PS_TWI pTWI, // \arg pointer to a TWI controller - unsigned int flag) // \arg IT to be enabled -{ - //* Write to the IER register - pTWI->TWI_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_DisableIt -//* \brief Disable TWI IT -//*---------------------------------------------------------------------------- -__inline void AT91F_TWI_DisableIt ( - AT91PS_TWI pTWI, // \arg pointer to a TWI controller - unsigned int flag) // \arg IT to be disabled -{ - //* Write to the IDR register - pTWI->TWI_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_Configure -//* \brief Configure TWI in master mode -//*---------------------------------------------------------------------------- -__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI ) // \arg pointer to a TWI controller -{ - //* Disable interrupts - pTWI->TWI_IDR = (unsigned int) -1; - - //* Reset peripheral - pTWI->TWI_CR = AT91C_TWI_SWRST; - - //* Set Master mode - pTWI->TWI_CR = AT91C_TWI_MSEN; - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_GetInterruptMaskStatus -//* \brief Return TWI Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status - AT91PS_TWI pTwi) // \arg pointer to a TWI controller -{ - return pTwi->TWI_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_IsInterruptMasked -//* \brief Test if TWI Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_TWI_IsInterruptMasked( - AT91PS_TWI pTwi, // \arg pointer to a TWI controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR PWMC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_GetStatus -//* \brief Return PWM Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status - AT91PS_PWMC pPWM) // pointer to a PWM controller -{ - return pPWM->PWMC_SR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_InterruptEnable -//* \brief Enable PWM Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_InterruptEnable( - AT91PS_PWMC pPwm, // \arg pointer to a PWM controller - unsigned int flag) // \arg PWM interrupt to be enabled -{ - pPwm->PWMC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_InterruptDisable -//* \brief Disable PWM Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_InterruptDisable( - AT91PS_PWMC pPwm, // \arg pointer to a PWM controller - unsigned int flag) // \arg PWM interrupt to be disabled -{ - pPwm->PWMC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_GetInterruptMaskStatus -//* \brief Return PWM Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status - AT91PS_PWMC pPwm) // \arg pointer to a PWM controller -{ - return pPwm->PWMC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_IsInterruptMasked -//* \brief Test if PWM Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PWMC_IsInterruptMasked( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_IsStatusSet -//* \brief Test if PWM Interrupt is Set -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PWMC_IsStatusSet( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PWMC_GetStatus(pPWM) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_CfgChannel -//* \brief Test if PWM Interrupt is Set -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CfgChannel( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int channelId, // \arg PWM channel ID - unsigned int mode, // \arg PWM mode - unsigned int period, // \arg PWM period - unsigned int duty) // \arg PWM duty cycle -{ - pPWM->PWMC_CH[channelId].PWMC_CMR = mode; - pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty; - pPWM->PWMC_CH[channelId].PWMC_CPRDR = period; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_StartChannel -//* \brief Enable channel -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_StartChannel( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int flag) // \arg Channels IDs to be enabled -{ - pPWM->PWMC_ENA = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_StopChannel -//* \brief Disable channel -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_StopChannel( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int flag) // \arg Channels IDs to be enabled -{ - pPWM->PWMC_DIS = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_UpdateChannel -//* \brief Update Period or Duty Cycle -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_UpdateChannel( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int channelId, // \arg PWM channel ID - unsigned int update) // \arg Channels IDs to be enabled -{ - pPWM->PWMC_CH[channelId].PWMC_CUPDR = update; -} - -/* ***************************************************************************** - SOFTWARE API FOR UDP - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EnableIt -//* \brief Enable UDP IT -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EnableIt ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg IT to be enabled -{ - //* Write to the IER register - pUDP->UDP_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_DisableIt -//* \brief Disable UDP IT -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_DisableIt ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg IT to be disabled -{ - //* Write to the IDR register - pUDP->UDP_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_SetAddress -//* \brief Set UDP functional address -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_SetAddress ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char address) // \arg new UDP address -{ - pUDP->UDP_FADDR = (AT91C_UDP_FEN | address); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EnableEp -//* \brief Enable Endpoint -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EnableEp ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - pUDP->UDP_CSR[endpoint] |= AT91C_UDP_EPEDS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_DisableEp -//* \brief Enable Endpoint -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_DisableEp ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - pUDP->UDP_CSR[endpoint] &= ~AT91C_UDP_EPEDS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_SetState -//* \brief Set UDP Device state -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_SetState ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg new UDP address -{ - pUDP->UDP_GLBSTATE &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG); - pUDP->UDP_GLBSTATE |= flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_GetState -//* \brief return UDP Device state -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state - AT91PS_UDP pUDP) // \arg pointer to a UDP controller -{ - return (pUDP->UDP_GLBSTATE & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_ResetEp -//* \brief Reset UDP endpoint -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_ResetEp ( // \return the UDP device state - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg Endpoints to be reset -{ - pUDP->UDP_RSTEP = flag; - pUDP->UDP_RSTEP = 0; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpStall -//* \brief Endpoint will STALL requests -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EpStall( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpWrite -//* \brief Write value in the DPR -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EpWrite( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint, // \arg endpoint number - unsigned char value) // \arg value to be written in the DPR -{ - pUDP->UDP_FDR[endpoint] = value; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpRead -//* \brief Return value from the DPR -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_UDP_EpRead( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - return pUDP->UDP_FDR[endpoint]; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpEndOfWr -//* \brief Notify the UDP that values in DPR are ready to be sent -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EpEndOfWr( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpClear -//* \brief Clear flag in the endpoint CSR register -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EpClear( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint, // \arg endpoint number - unsigned int flag) // \arg flag to be cleared -{ - pUDP->UDP_CSR[endpoint] &= ~(flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpSet -//* \brief Set flag in the endpoint CSR register -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EpSet( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint, // \arg endpoint number - unsigned int flag) // \arg flag to be cleared -{ - pUDP->UDP_CSR[endpoint] |= flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpStatus -//* \brief Return the endpoint CSR register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_UDP_EpStatus( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - return pUDP->UDP_CSR[endpoint]; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_GetInterruptMaskStatus -//* \brief Return UDP Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status - AT91PS_UDP pUdp) // \arg pointer to a UDP controller -{ - return pUdp->UDP_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_IsInterruptMasked -//* \brief Test if UDP Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_UDP_IsInterruptMasked( - AT91PS_UDP pUdp, // \arg pointer to a UDP controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR TC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC_InterruptEnable -//* \brief Enable TC Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_TC_InterruptEnable( - AT91PS_TC pTc, // \arg pointer to a TC controller - unsigned int flag) // \arg TC interrupt to be enabled -{ - pTc->TC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC_InterruptDisable -//* \brief Disable TC Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_TC_InterruptDisable( - AT91PS_TC pTc, // \arg pointer to a TC controller - unsigned int flag) // \arg TC interrupt to be disabled -{ - pTc->TC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC_GetInterruptMaskStatus -//* \brief Return TC Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status - AT91PS_TC pTc) // \arg pointer to a TC controller -{ - return pTc->TC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC_IsInterruptMasked -//* \brief Test if TC Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_TC_IsInterruptMasked( - AT91PS_TC pTc, // \arg pointer to a TC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR CAN - ***************************************************************************** */ -#define STANDARD_FORMAT 0 -#define EXTENDED_FORMAT 1 - -//*---------------------------------------------------------------------------- -//* \fn AT91F_InitMailboxRegisters() -//* \brief Configure the corresponding mailbox -//*---------------------------------------------------------------------------- -__inline void AT91F_InitMailboxRegisters(AT91PS_CAN_MB CAN_Mailbox, - int mode_reg, - int acceptance_mask_reg, - int id_reg, - int data_low_reg, - int data_high_reg, - int control_reg) -{ - CAN_Mailbox->CAN_MB_MCR = 0x0; - CAN_Mailbox->CAN_MB_MMR = mode_reg; - CAN_Mailbox->CAN_MB_MAM = acceptance_mask_reg; - CAN_Mailbox->CAN_MB_MID = id_reg; - CAN_Mailbox->CAN_MB_MDL = data_low_reg; - CAN_Mailbox->CAN_MB_MDH = data_high_reg; - CAN_Mailbox->CAN_MB_MCR = control_reg; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_EnableCAN() -//* \brief -//*---------------------------------------------------------------------------- -__inline void AT91F_EnableCAN( - AT91PS_CAN pCAN) // pointer to a CAN controller -{ - pCAN->CAN_MR |= AT91C_CAN_CANEN; - - // Wait for WAKEUP flag raising <=> 11-recessive-bit were scanned by the transceiver - while( (pCAN->CAN_SR & AT91C_CAN_WAKEUP) != AT91C_CAN_WAKEUP ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DisableCAN() -//* \brief -//*---------------------------------------------------------------------------- -__inline void AT91F_DisableCAN( - AT91PS_CAN pCAN) // pointer to a CAN controller -{ - pCAN->CAN_MR &= ~AT91C_CAN_CANEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_EnableIt -//* \brief Enable CAN interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_EnableIt ( - AT91PS_CAN pCAN, // pointer to a CAN controller - unsigned int flag) // IT to be enabled -{ - //* Write to the IER register - pCAN->CAN_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_DisableIt -//* \brief Disable CAN interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_DisableIt ( - AT91PS_CAN pCAN, // pointer to a CAN controller - unsigned int flag) // IT to be disabled -{ - //* Write to the IDR register - pCAN->CAN_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetStatus -//* \brief Return CAN Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetStatus( // \return CAN Interrupt Status - AT91PS_CAN pCAN) // pointer to a CAN controller -{ - return pCAN->CAN_SR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetInterruptMaskStatus -//* \brief Return CAN Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetInterruptMaskStatus( // \return CAN Interrupt Mask Status - AT91PS_CAN pCAN) // pointer to a CAN controller -{ - return pCAN->CAN_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_IsInterruptMasked -//* \brief Test if CAN Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_IsInterruptMasked( - AT91PS_CAN pCAN, // \arg pointer to a CAN controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_CAN_GetInterruptMaskStatus(pCAN) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_IsStatusSet -//* \brief Test if CAN Interrupt is Set -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_IsStatusSet( - AT91PS_CAN pCAN, // \arg pointer to a CAN controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_CAN_GetStatus(pCAN) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgModeReg -//* \brief Configure the Mode Register of the CAN controller -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgModeReg ( - AT91PS_CAN pCAN, // pointer to a CAN controller - unsigned int mode) // mode register -{ - //* Write to the MR register - pCAN->CAN_MR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetModeReg -//* \brief Return the Mode Register of the CAN controller value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetModeReg ( - AT91PS_CAN pCAN // pointer to a CAN controller - ) -{ - return pCAN->CAN_MR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgBaudrateReg -//* \brief Configure the Baudrate of the CAN controller for the network -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgBaudrateReg ( - AT91PS_CAN pCAN, // pointer to a CAN controller - unsigned int baudrate_cfg) -{ - //* Write to the BR register - pCAN->CAN_BR = baudrate_cfg; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetBaudrate -//* \brief Return the Baudrate of the CAN controller for the network value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetBaudrate ( - AT91PS_CAN pCAN // pointer to a CAN controller - ) -{ - return pCAN->CAN_BR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetInternalCounter -//* \brief Return CAN Timer Regsiter Value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetInternalCounter ( - AT91PS_CAN pCAN // pointer to a CAN controller - ) -{ - return pCAN->CAN_TIM; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetTimestamp -//* \brief Return CAN Timestamp Register Value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetTimestamp ( - AT91PS_CAN pCAN // pointer to a CAN controller - ) -{ - return pCAN->CAN_TIMESTP; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetErrorCounter -//* \brief Return CAN Error Counter Register Value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetErrorCounter ( - AT91PS_CAN pCAN // pointer to a CAN controller - ) -{ - return pCAN->CAN_ECR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_InitTransferRequest -//* \brief Request for a transfer on the corresponding mailboxes -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_InitTransferRequest ( - AT91PS_CAN pCAN, // pointer to a CAN controller - unsigned int transfer_cmd) -{ - pCAN->CAN_TCR = transfer_cmd; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_InitAbortRequest -//* \brief Abort the corresponding mailboxes -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_InitAbortRequest ( - AT91PS_CAN pCAN, // pointer to a CAN controller - unsigned int abort_cmd) -{ - pCAN->CAN_ACR = abort_cmd; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgMessageModeReg -//* \brief Program the Message Mode Register -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgMessageModeReg ( - AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox - unsigned int mode) -{ - CAN_Mailbox->CAN_MB_MMR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetMessageModeReg -//* \brief Return the Message Mode Register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetMessageModeReg ( - AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox -{ - return CAN_Mailbox->CAN_MB_MMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgMessageIDReg -//* \brief Program the Message ID Register -//* \brief Version == 0 for Standard messsage, Version == 1 for Extended -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgMessageIDReg ( - AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox - unsigned int id, - unsigned char version) -{ - if(version==0) // IDvA Standard Format - CAN_Mailbox->CAN_MB_MID = id<<18; - else // IDvB Extended Format - CAN_Mailbox->CAN_MB_MID = id | (1<<29); // set MIDE bit -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetMessageIDReg -//* \brief Return the Message ID Register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetMessageIDReg ( - AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox -{ - return CAN_Mailbox->CAN_MB_MID; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgMessageAcceptanceMaskReg -//* \brief Program the Message Acceptance Mask Register -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgMessageAcceptanceMaskReg ( - AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox - unsigned int mask) -{ - CAN_Mailbox->CAN_MB_MAM = mask; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetMessageAcceptanceMaskReg -//* \brief Return the Message Acceptance Mask Register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetMessageAcceptanceMaskReg ( - AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox -{ - return CAN_Mailbox->CAN_MB_MAM; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetFamilyID -//* \brief Return the Message ID Register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetFamilyID ( - AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox -{ - return CAN_Mailbox->CAN_MB_MFID; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgMessageCtrl -//* \brief Request and config for a transfer on the corresponding mailbox -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgMessageCtrlReg ( - AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox - unsigned int message_ctrl_cmd) -{ - CAN_Mailbox->CAN_MB_MCR = message_ctrl_cmd; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetMessageStatus -//* \brief Return CAN Mailbox Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetMessageStatus ( - AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox -{ - return CAN_Mailbox->CAN_MB_MSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgMessageDataLow -//* \brief Program data low value -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgMessageDataLow ( - AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox - unsigned int data) -{ - CAN_Mailbox->CAN_MB_MDL = data; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetMessageDataLow -//* \brief Return data low value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetMessageDataLow ( - AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox -{ - return CAN_Mailbox->CAN_MB_MDL; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgMessageDataHigh -//* \brief Program data high value -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgMessageDataHigh ( - AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox - unsigned int data) -{ - CAN_Mailbox->CAN_MB_MDH = data; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetMessageDataHigh -//* \brief Return data high value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetMessageDataHigh ( - AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox -{ - return CAN_Mailbox->CAN_MB_MDH; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_Open -//* \brief Open a CAN Port -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_Open ( - const unsigned int null) // \arg -{ - /* NOT DEFINED AT THIS MOMENT */ - return ( 0 ); -} -/* ***************************************************************************** - SOFTWARE API FOR ADC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_EnableIt -//* \brief Enable ADC interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_EnableIt ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int flag) // IT to be enabled -{ - //* Write to the IER register - pADC->ADC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_DisableIt -//* \brief Disable ADC interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_DisableIt ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int flag) // IT to be disabled -{ - //* Write to the IDR register - pADC->ADC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetStatus -//* \brief Return ADC Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status - AT91PS_ADC pADC) // pointer to a ADC controller -{ - return pADC->ADC_SR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetInterruptMaskStatus -//* \brief Return ADC Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status - AT91PS_ADC pADC) // pointer to a ADC controller -{ - return pADC->ADC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_IsInterruptMasked -//* \brief Test if ADC Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_IsInterruptMasked( - AT91PS_ADC pADC, // \arg pointer to a ADC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_IsStatusSet -//* \brief Test if ADC Status is Set -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_IsStatusSet( - AT91PS_ADC pADC, // \arg pointer to a ADC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_ADC_GetStatus(pADC) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_CfgModeReg -//* \brief Configure the Mode Register of the ADC controller -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_CfgModeReg ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int mode) // mode register -{ - //* Write to the MR register - pADC->ADC_MR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetModeReg -//* \brief Return the Mode Register of the ADC controller value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetModeReg ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_MR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_CfgTimings -//* \brief Configure the different necessary timings of the ADC controller -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_CfgTimings ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int mck_clock, // in MHz - unsigned int adc_clock, // in MHz - unsigned int startup_time, // in us - unsigned int sample_and_hold_time) // in ns -{ - unsigned int prescal,startup,shtim; - - prescal = mck_clock/(2*adc_clock) - 1; - startup = adc_clock*startup_time/8 - 1; - shtim = adc_clock*sample_and_hold_time/1000 - 1; - - //* Write to the MR register - pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_EnableChannel -//* \brief Return ADC Timer Register Value -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_EnableChannel ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int channel) // mode register -{ - //* Write to the CHER register - pADC->ADC_CHER = channel; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_DisableChannel -//* \brief Return ADC Timer Register Value -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_DisableChannel ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int channel) // mode register -{ - //* Write to the CHDR register - pADC->ADC_CHDR = channel; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetChannelStatus -//* \brief Return ADC Timer Register Value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetChannelStatus ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CHSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_StartConversion -//* \brief Software request for a analog to digital conversion -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_StartConversion ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - pADC->ADC_CR = AT91C_ADC_START; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_SoftReset -//* \brief Software reset -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_SoftReset ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - pADC->ADC_CR = AT91C_ADC_SWRST; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetLastConvertedData -//* \brief Return the Last Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetLastConvertedData ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_LCDR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH0 -//* \brief Return the Channel 0 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH0 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR0; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH1 -//* \brief Return the Channel 1 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH1 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR1; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH2 -//* \brief Return the Channel 2 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH2 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR2; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH3 -//* \brief Return the Channel 3 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH3 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR3; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH4 -//* \brief Return the Channel 4 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH4 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR4; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH5 -//* \brief Return the Channel 5 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH5 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR5; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH6 -//* \brief Return the Channel 6 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH6 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR6; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH7 -//* \brief Return the Channel 7 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH7 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR7; -} - -/* ***************************************************************************** - SOFTWARE API FOR AES - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_EnableIt -//* \brief Enable AES interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_AES_EnableIt ( - AT91PS_AES pAES, // pointer to a AES controller - unsigned int flag) // IT to be enabled -{ - //* Write to the IER register - pAES->AES_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_DisableIt -//* \brief Disable AES interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_AES_DisableIt ( - AT91PS_AES pAES, // pointer to a AES controller - unsigned int flag) // IT to be disabled -{ - //* Write to the IDR register - pAES->AES_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_GetStatus -//* \brief Return AES Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AES_GetStatus( // \return AES Interrupt Status - AT91PS_AES pAES) // pointer to a AES controller -{ - return pAES->AES_ISR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_GetInterruptMaskStatus -//* \brief Return AES Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AES_GetInterruptMaskStatus( // \return AES Interrupt Mask Status - AT91PS_AES pAES) // pointer to a AES controller -{ - return pAES->AES_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_IsInterruptMasked -//* \brief Test if AES Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AES_IsInterruptMasked( - AT91PS_AES pAES, // \arg pointer to a AES controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_AES_GetInterruptMaskStatus(pAES) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_IsStatusSet -//* \brief Test if AES Status is Set -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AES_IsStatusSet( - AT91PS_AES pAES, // \arg pointer to a AES controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_AES_GetStatus(pAES) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_CfgModeReg -//* \brief Configure the Mode Register of the AES controller -//*---------------------------------------------------------------------------- -__inline void AT91F_AES_CfgModeReg ( - AT91PS_AES pAES, // pointer to a AES controller - unsigned int mode) // mode register -{ - //* Write to the MR register - pAES->AES_MR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_GetModeReg -//* \brief Return the Mode Register of the AES controller value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AES_GetModeReg ( - AT91PS_AES pAES // pointer to a AES controller - ) -{ - return pAES->AES_MR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_StartProcessing -//* \brief Start Encryption or Decryption -//*---------------------------------------------------------------------------- -__inline void AT91F_AES_StartProcessing ( - AT91PS_AES pAES // pointer to a AES controller - ) -{ - pAES->AES_CR = AT91C_AES_START; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_SoftReset -//* \brief Reset AES -//*---------------------------------------------------------------------------- -__inline void AT91F_AES_SoftReset ( - AT91PS_AES pAES // pointer to a AES controller - ) -{ - pAES->AES_CR = AT91C_AES_SWRST; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_LoadNewSeed -//* \brief Load New Seed in the random number generator -//*---------------------------------------------------------------------------- -__inline void AT91F_AES_LoadNewSeed ( - AT91PS_AES pAES // pointer to a AES controller - ) -{ - pAES->AES_CR = AT91C_AES_LOADSEED; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_SetCryptoKey -//* \brief Set Cryptographic Key x -//*---------------------------------------------------------------------------- -__inline void AT91F_AES_SetCryptoKey ( - AT91PS_AES pAES, // pointer to a AES controller - unsigned char index, - unsigned int keyword - ) -{ - pAES->AES_KEYWxR[index] = keyword; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_InputData -//* \brief Set Input Data x -//*---------------------------------------------------------------------------- -__inline void AT91F_AES_InputData ( - AT91PS_AES pAES, // pointer to a AES controller - unsigned char index, - unsigned int indata - ) -{ - pAES->AES_IDATAxR[index] = indata; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_GetOutputData -//* \brief Get Output Data x -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AES_GetOutputData ( - AT91PS_AES pAES, // pointer to a AES controller - unsigned char index - ) -{ - return pAES->AES_ODATAxR[index]; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_SetInitializationVector -//* \brief Set Initialization Vector (or Counter) x -//*---------------------------------------------------------------------------- -__inline void AT91F_AES_SetInitializationVector ( - AT91PS_AES pAES, // pointer to a AES controller - unsigned char index, - unsigned int initvector - ) -{ - pAES->AES_IVxR[index] = initvector; -} - -/* ***************************************************************************** - SOFTWARE API FOR TDES - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_EnableIt -//* \brief Enable TDES interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_TDES_EnableIt ( - AT91PS_TDES pTDES, // pointer to a TDES controller - unsigned int flag) // IT to be enabled -{ - //* Write to the IER register - pTDES->TDES_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_DisableIt -//* \brief Disable TDES interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_TDES_DisableIt ( - AT91PS_TDES pTDES, // pointer to a TDES controller - unsigned int flag) // IT to be disabled -{ - //* Write to the IDR register - pTDES->TDES_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_GetStatus -//* \brief Return TDES Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_TDES_GetStatus( // \return TDES Interrupt Status - AT91PS_TDES pTDES) // pointer to a TDES controller -{ - return pTDES->TDES_ISR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_GetInterruptMaskStatus -//* \brief Return TDES Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_TDES_GetInterruptMaskStatus( // \return TDES Interrupt Mask Status - AT91PS_TDES pTDES) // pointer to a TDES controller -{ - return pTDES->TDES_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_IsInterruptMasked -//* \brief Test if TDES Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_TDES_IsInterruptMasked( - AT91PS_TDES pTDES, // \arg pointer to a TDES controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_TDES_GetInterruptMaskStatus(pTDES) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_IsStatusSet -//* \brief Test if TDES Status is Set -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_TDES_IsStatusSet( - AT91PS_TDES pTDES, // \arg pointer to a TDES controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_TDES_GetStatus(pTDES) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_CfgModeReg -//* \brief Configure the Mode Register of the TDES controller -//*---------------------------------------------------------------------------- -__inline void AT91F_TDES_CfgModeReg ( - AT91PS_TDES pTDES, // pointer to a TDES controller - unsigned int mode) // mode register -{ - //* Write to the MR register - pTDES->TDES_MR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_GetModeReg -//* \brief Return the Mode Register of the TDES controller value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_TDES_GetModeReg ( - AT91PS_TDES pTDES // pointer to a TDES controller - ) -{ - return pTDES->TDES_MR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_StartProcessing -//* \brief Start Encryption or Decryption -//*---------------------------------------------------------------------------- -__inline void AT91F_TDES_StartProcessing ( - AT91PS_TDES pTDES // pointer to a TDES controller - ) -{ - pTDES->TDES_CR = AT91C_TDES_START; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_SoftReset -//* \brief Reset TDES -//*---------------------------------------------------------------------------- -__inline void AT91F_TDES_SoftReset ( - AT91PS_TDES pTDES // pointer to a TDES controller - ) -{ - pTDES->TDES_CR = AT91C_TDES_SWRST; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_SetCryptoKey1 -//* \brief Set Cryptographic Key 1 Word x -//*---------------------------------------------------------------------------- -__inline void AT91F_TDES_SetCryptoKey1 ( - AT91PS_TDES pTDES, // pointer to a TDES controller - unsigned char index, - unsigned int keyword - ) -{ - pTDES->TDES_KEY1WxR[index] = keyword; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_SetCryptoKey2 -//* \brief Set Cryptographic Key 2 Word x -//*---------------------------------------------------------------------------- -__inline void AT91F_TDES_SetCryptoKey2 ( - AT91PS_TDES pTDES, // pointer to a TDES controller - unsigned char index, - unsigned int keyword - ) -{ - pTDES->TDES_KEY2WxR[index] = keyword; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_SetCryptoKey3 -//* \brief Set Cryptographic Key 3 Word x -//*---------------------------------------------------------------------------- -__inline void AT91F_TDES_SetCryptoKey3 ( - AT91PS_TDES pTDES, // pointer to a TDES controller - unsigned char index, - unsigned int keyword - ) -{ - pTDES->TDES_KEY3WxR[index] = keyword; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_InputData -//* \brief Set Input Data x -//*---------------------------------------------------------------------------- -__inline void AT91F_TDES_InputData ( - AT91PS_TDES pTDES, // pointer to a TDES controller - unsigned char index, - unsigned int indata - ) -{ - pTDES->TDES_IDATAxR[index] = indata; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_GetOutputData -//* \brief Get Output Data x -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_TDES_GetOutputData ( - AT91PS_TDES pTDES, // pointer to a TDES controller - unsigned char index - ) -{ - return pTDES->TDES_ODATAxR[index]; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_SetInitializationVector -//* \brief Set Initialization Vector x -//*---------------------------------------------------------------------------- -__inline void AT91F_TDES_SetInitializationVector ( - AT91PS_TDES pTDES, // pointer to a TDES controller - unsigned char index, - unsigned int initvector - ) -{ - pTDES->TDES_IVxR[index] = initvector; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_CfgPMC -//* \brief Enable Peripheral clock in PMC for DBGU -//*---------------------------------------------------------------------------- -__inline void AT91F_DBGU_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_CfgPIO -//* \brief Configure PIO controllers to drive DBGU signals -//*---------------------------------------------------------------------------- -__inline void AT91F_DBGU_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA27_DRXD ) | - ((unsigned int) AT91C_PA28_DTXD ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgPMC -//* \brief Enable Peripheral clock in PMC for PMC -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgPIO -//* \brief Configure PIO controllers to drive PMC signals -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB30_PCK2 ) | - ((unsigned int) AT91C_PB29_PCK1 ), // Peripheral A - ((unsigned int) AT91C_PB20_PCK0 ) | - ((unsigned int) AT91C_PB0_PCK0 ) | - ((unsigned int) AT91C_PB22_PCK2 ) | - ((unsigned int) AT91C_PB21_PCK1 )); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PA30_PCK2 ) | - ((unsigned int) AT91C_PA13_PCK1 ) | - ((unsigned int) AT91C_PA27_PCK3 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_VREG_CfgPMC -//* \brief Enable Peripheral clock in PMC for VREG -//*---------------------------------------------------------------------------- -__inline void AT91F_VREG_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTC_CfgPMC -//* \brief Enable Peripheral clock in PMC for RSTC -//*---------------------------------------------------------------------------- -__inline void AT91F_RSTC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_CfgPMC -//* \brief Enable Peripheral clock in PMC for SSC -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SSC)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_CfgPIO -//* \brief Configure PIO controllers to drive SSC signals -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA25_RK ) | - ((unsigned int) AT91C_PA22_TK ) | - ((unsigned int) AT91C_PA21_TF ) | - ((unsigned int) AT91C_PA24_RD ) | - ((unsigned int) AT91C_PA26_RF ) | - ((unsigned int) AT91C_PA23_TD ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_WDTC_CfgPMC -//* \brief Enable Peripheral clock in PMC for WDTC -//*---------------------------------------------------------------------------- -__inline void AT91F_WDTC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US1_CfgPMC -//* \brief Enable Peripheral clock in PMC for US1 -//*---------------------------------------------------------------------------- -__inline void AT91F_US1_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_US1)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US1_CfgPIO -//* \brief Configure PIO controllers to drive US1 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_US1_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PB26_RI1 ) | - ((unsigned int) AT91C_PB24_DSR1 ) | - ((unsigned int) AT91C_PB23_DCD1 ) | - ((unsigned int) AT91C_PB25_DTR1 )); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA7_SCK1 ) | - ((unsigned int) AT91C_PA8_RTS1 ) | - ((unsigned int) AT91C_PA6_TXD1 ) | - ((unsigned int) AT91C_PA5_RXD1 ) | - ((unsigned int) AT91C_PA9_CTS1 ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US0_CfgPMC -//* \brief Enable Peripheral clock in PMC for US0 -//*---------------------------------------------------------------------------- -__inline void AT91F_US0_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_US0)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US0_CfgPIO -//* \brief Configure PIO controllers to drive US0 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_US0_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA0_RXD0 ) | - ((unsigned int) AT91C_PA4_CTS0 ) | - ((unsigned int) AT91C_PA3_RTS0 ) | - ((unsigned int) AT91C_PA2_SCK0 ) | - ((unsigned int) AT91C_PA1_TXD0 ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI1_CfgPMC -//* \brief Enable Peripheral clock in PMC for SPI1 -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI1_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SPI1)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI1_CfgPIO -//* \brief Configure PIO controllers to drive SPI1 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI1_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PB16_NPCS13 ) | - ((unsigned int) AT91C_PB10_NPCS11 ) | - ((unsigned int) AT91C_PB11_NPCS12 )); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PA4_NPCS13 ) | - ((unsigned int) AT91C_PA29_NPCS13 ) | - ((unsigned int) AT91C_PA21_NPCS10 ) | - ((unsigned int) AT91C_PA22_SPCK1 ) | - ((unsigned int) AT91C_PA25_NPCS11 ) | - ((unsigned int) AT91C_PA2_NPCS11 ) | - ((unsigned int) AT91C_PA24_MISO1 ) | - ((unsigned int) AT91C_PA3_NPCS12 ) | - ((unsigned int) AT91C_PA26_NPCS12 ) | - ((unsigned int) AT91C_PA23_MOSI1 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI0_CfgPMC -//* \brief Enable Peripheral clock in PMC for SPI0 -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI0_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SPI0)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI0_CfgPIO -//* \brief Configure PIO controllers to drive SPI0 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI0_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PB13_NPCS01 ) | - ((unsigned int) AT91C_PB17_NPCS03 ) | - ((unsigned int) AT91C_PB14_NPCS02 )); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA16_MISO0 ) | - ((unsigned int) AT91C_PA13_NPCS01 ) | - ((unsigned int) AT91C_PA15_NPCS03 ) | - ((unsigned int) AT91C_PA17_MOSI0 ) | - ((unsigned int) AT91C_PA18_SPCK0 ) | - ((unsigned int) AT91C_PA14_NPCS02 ) | - ((unsigned int) AT91C_PA12_NPCS00 ), // Peripheral A - ((unsigned int) AT91C_PA7_NPCS01 ) | - ((unsigned int) AT91C_PA9_NPCS03 ) | - ((unsigned int) AT91C_PA8_NPCS02 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITC_CfgPMC -//* \brief Enable Peripheral clock in PMC for PITC -//*---------------------------------------------------------------------------- -__inline void AT91F_PITC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_CfgPMC -//* \brief Enable Peripheral clock in PMC for AIC -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_FIQ) | - ((unsigned int) 1 << AT91C_ID_IRQ0) | - ((unsigned int) 1 << AT91C_ID_IRQ1)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_CfgPIO -//* \brief Configure PIO controllers to drive AIC signals -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA30_IRQ0 ) | - ((unsigned int) AT91C_PA29_FIQ ), // Peripheral A - ((unsigned int) AT91C_PA14_IRQ1 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_CfgPMC -//* \brief Enable Peripheral clock in PMC for AES -//*---------------------------------------------------------------------------- -__inline void AT91F_AES_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_AES)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_CfgPMC -//* \brief Enable Peripheral clock in PMC for TWI -//*---------------------------------------------------------------------------- -__inline void AT91F_TWI_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TWI)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_CfgPIO -//* \brief Configure PIO controllers to drive TWI signals -//*---------------------------------------------------------------------------- -__inline void AT91F_TWI_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA11_TWCK ) | - ((unsigned int) AT91C_PA10_TWD ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_CfgPMC -//* \brief Enable Peripheral clock in PMC for ADC -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_ADC)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_CfgPIO -//* \brief Configure PIO controllers to drive ADC signals -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PB18_ADTRG )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CH3_CfgPIO -//* \brief Configure PIO controllers to drive PWMC_CH3 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CH3_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB22_PWM3 ), // Peripheral A - ((unsigned int) AT91C_PB30_PWM3 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CH2_CfgPIO -//* \brief Configure PIO controllers to drive PWMC_CH2 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CH2_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB21_PWM2 ), // Peripheral A - ((unsigned int) AT91C_PB29_PWM2 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CH1_CfgPIO -//* \brief Configure PIO controllers to drive PWMC_CH1 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CH1_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB20_PWM1 ), // Peripheral A - ((unsigned int) AT91C_PB28_PWM1 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CH0_CfgPIO -//* \brief Configure PIO controllers to drive PWMC_CH0 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CH0_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB19_PWM0 ), // Peripheral A - ((unsigned int) AT91C_PB27_PWM0 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RTTC_CfgPMC -//* \brief Enable Peripheral clock in PMC for RTTC -//*---------------------------------------------------------------------------- -__inline void AT91F_RTTC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_CfgPMC -//* \brief Enable Peripheral clock in PMC for UDP -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_UDP)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_CfgPMC -//* \brief Enable Peripheral clock in PMC for TDES -//*---------------------------------------------------------------------------- -__inline void AT91F_TDES_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TDES)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_EMAC_CfgPMC -//* \brief Enable Peripheral clock in PMC for EMAC -//*---------------------------------------------------------------------------- -__inline void AT91F_EMAC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_EMAC)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_EMAC_CfgPIO -//* \brief Configure PIO controllers to drive EMAC signals -//*---------------------------------------------------------------------------- -__inline void AT91F_EMAC_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB2_ETX0 ) | - ((unsigned int) AT91C_PB12_ETXER ) | - ((unsigned int) AT91C_PB16_ECOL ) | - ((unsigned int) AT91C_PB11_ETX3 ) | - ((unsigned int) AT91C_PB6_ERX1 ) | - ((unsigned int) AT91C_PB15_ERXDV ) | - ((unsigned int) AT91C_PB13_ERX2 ) | - ((unsigned int) AT91C_PB3_ETX1 ) | - ((unsigned int) AT91C_PB8_EMDC ) | - ((unsigned int) AT91C_PB5_ERX0 ) | - //((unsigned int) AT91C_PB18_EF100 ) | - ((unsigned int) AT91C_PB14_ERX3 ) | - ((unsigned int) AT91C_PB4_ECRS_ECRSDV) | - ((unsigned int) AT91C_PB1_ETXEN ) | - ((unsigned int) AT91C_PB10_ETX2 ) | - ((unsigned int) AT91C_PB0_ETXCK_EREFCK) | - ((unsigned int) AT91C_PB9_EMDIO ) | - ((unsigned int) AT91C_PB7_ERXER ) | - ((unsigned int) AT91C_PB17_ERXCK ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC0_CfgPMC -//* \brief Enable Peripheral clock in PMC for TC0 -//*---------------------------------------------------------------------------- -__inline void AT91F_TC0_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TC0)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC0_CfgPIO -//* \brief Configure PIO controllers to drive TC0 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_TC0_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB23_TIOA0 ) | - ((unsigned int) AT91C_PB24_TIOB0 ), // Peripheral A - ((unsigned int) AT91C_PB12_TCLK0 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC1_CfgPMC -//* \brief Enable Peripheral clock in PMC for TC1 -//*---------------------------------------------------------------------------- -__inline void AT91F_TC1_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TC1)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC1_CfgPIO -//* \brief Configure PIO controllers to drive TC1 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_TC1_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB25_TIOA1 ) | - ((unsigned int) AT91C_PB26_TIOB1 ), // Peripheral A - ((unsigned int) AT91C_PB19_TCLK1 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC2_CfgPMC -//* \brief Enable Peripheral clock in PMC for TC2 -//*---------------------------------------------------------------------------- -__inline void AT91F_TC2_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TC2)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC2_CfgPIO -//* \brief Configure PIO controllers to drive TC2 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_TC2_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB28_TIOB2 ) | - ((unsigned int) AT91C_PB27_TIOA2 ), // Peripheral A - 0); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PA15_TCLK2 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_CfgPMC -//* \brief Enable Peripheral clock in PMC for MC -//*---------------------------------------------------------------------------- -__inline void AT91F_MC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIOA_CfgPMC -//* \brief Enable Peripheral clock in PMC for PIOA -//*---------------------------------------------------------------------------- -__inline void AT91F_PIOA_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_PIOA)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIOB_CfgPMC -//* \brief Enable Peripheral clock in PMC for PIOB -//*---------------------------------------------------------------------------- -__inline void AT91F_PIOB_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_PIOB)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgPMC -//* \brief Enable Peripheral clock in PMC for CAN -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_CAN)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgPIO -//* \brief Configure PIO controllers to drive CAN signals -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA20_CANTX ) | - ((unsigned int) AT91C_PA19_CANRX ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CfgPMC -//* \brief Enable Peripheral clock in PMC for PWMC -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_PWMC)); -} - -#endif // lib_AT91SAM7X128_H diff --git a/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h b/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h deleted file mode 100644 index 02ee9008d..000000000 --- a/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h +++ /dev/null @@ -1,4558 +0,0 @@ -//* ---------------------------------------------------------------------------- -//* ATMEL Microcontroller Software Support - ROUSSET - -//* ---------------------------------------------------------------------------- -//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -//* ---------------------------------------------------------------------------- -//* File Name : lib_AT91SAM7X256.h -//* Object : AT91SAM7X256 inlined functions -//* Generated : AT91 SW Application Group 05/20/2005 (16:22:29) -//* -//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// -//* CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005// -//* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005// -//* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004// -//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// -//* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004// -//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// -//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003// -//* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004// -//* CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005// -//* CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005// -//* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// -//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// -//* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004// -//* CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005// -//* CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005// -//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// -//* CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004// -//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// -//* CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003// -//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// -//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002// -//* ---------------------------------------------------------------------------- - -#ifndef lib_AT91SAM7X256_H -#define lib_AT91SAM7X256_H - -/* ***************************************************************************** - SOFTWARE API FOR AIC - ***************************************************************************** */ -#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20] - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_ConfigureIt -//* \brief Interrupt Handler Initialization -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AIC_ConfigureIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id, // \arg interrupt number to initialize - unsigned int priority, // \arg priority to give to the interrupt - unsigned int src_type, // \arg activation and sense of activation - void (*newHandler) (void) ) // \arg address of the interrupt handler -{ - unsigned int oldHandler; - unsigned int mask ; - - oldHandler = pAic->AIC_SVR[irq_id]; - - mask = 0x1 << irq_id ; - //* Disable the interrupt on the interrupt controller - pAic->AIC_IDCR = mask ; - //* Save the interrupt handler routine pointer and the interrupt priority - pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ; - //* Store the Source Mode Register - pAic->AIC_SMR[irq_id] = src_type | priority ; - //* Clear the interrupt on the interrupt controller - pAic->AIC_ICCR = mask ; - - return oldHandler; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_EnableIt -//* \brief Enable corresponding IT number -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_EnableIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id ) // \arg interrupt number to initialize -{ - //* Enable the interrupt on the interrupt controller - pAic->AIC_IECR = 0x1 << irq_id ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_DisableIt -//* \brief Disable corresponding IT number -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_DisableIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id ) // \arg interrupt number to initialize -{ - unsigned int mask = 0x1 << irq_id; - //* Disable the interrupt on the interrupt controller - pAic->AIC_IDCR = mask ; - //* Clear the interrupt on the Interrupt Controller ( if one is pending ) - pAic->AIC_ICCR = mask ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_ClearIt -//* \brief Clear corresponding IT number -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_ClearIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg interrupt number to initialize -{ - //* Clear the interrupt on the Interrupt Controller ( if one is pending ) - pAic->AIC_ICCR = (0x1 << irq_id); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_AcknowledgeIt -//* \brief Acknowledge corresponding IT number -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_AcknowledgeIt ( - AT91PS_AIC pAic) // \arg pointer to the AIC registers -{ - pAic->AIC_EOICR = pAic->AIC_EOICR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_SetExceptionVector -//* \brief Configure vector handler -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AIC_SetExceptionVector ( - unsigned int *pVector, // \arg pointer to the AIC registers - void (*Handler) () ) // \arg Interrupt Handler -{ - unsigned int oldVector = *pVector; - - if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE) - *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE; - else - *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000; - - return oldVector; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_Trig -//* \brief Trig an IT -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_Trig ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg interrupt number -{ - pAic->AIC_ISCR = (0x1 << irq_id) ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_IsActive -//* \brief Test if an IT is active -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AIC_IsActive ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg Interrupt Number -{ - return (pAic->AIC_ISR & (0x1 << irq_id)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_IsPending -//* \brief Test if an IT is pending -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AIC_IsPending ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg Interrupt Number -{ - return (pAic->AIC_IPR & (0x1 << irq_id)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_Open -//* \brief Set exception vectors and AIC registers to default values -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_Open( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - void (*IrqHandler) (), // \arg Default IRQ vector exception - void (*FiqHandler) (), // \arg Default FIQ vector exception - void (*DefaultHandler) (), // \arg Default Handler set in ISR - void (*SpuriousHandler) (), // \arg Default Spurious Handler - unsigned int protectMode) // \arg Debug Control Register -{ - int i; - - // Disable all interrupts and set IVR to the default handler - for (i = 0; i < 32; ++i) { - AT91F_AIC_DisableIt(pAic, i); - AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler); - } - - // Set the IRQ exception vector - AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler); - // Set the Fast Interrupt exception vector - AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler); - - pAic->AIC_SPU = (unsigned int) SpuriousHandler; - pAic->AIC_DCR = protectMode; -} -/* ***************************************************************************** - SOFTWARE API FOR PDC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetNextRx -//* \brief Set the next receive transfer descriptor -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_SetNextRx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be received - unsigned int bytes) // \arg number of bytes to be received -{ - pPDC->PDC_RNPR = (unsigned int) address; - pPDC->PDC_RNCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetNextTx -//* \brief Set the next transmit transfer descriptor -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_SetNextTx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be transmitted - unsigned int bytes) // \arg number of bytes to be transmitted -{ - pPDC->PDC_TNPR = (unsigned int) address; - pPDC->PDC_TNCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetRx -//* \brief Set the receive transfer descriptor -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_SetRx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be received - unsigned int bytes) // \arg number of bytes to be received -{ - pPDC->PDC_RPR = (unsigned int) address; - pPDC->PDC_RCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetTx -//* \brief Set the transmit transfer descriptor -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_SetTx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be transmitted - unsigned int bytes) // \arg number of bytes to be transmitted -{ - pPDC->PDC_TPR = (unsigned int) address; - pPDC->PDC_TCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_EnableTx -//* \brief Enable transmit -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_EnableTx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_TXTEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_EnableRx -//* \brief Enable receive -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_EnableRx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_RXTEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_DisableTx -//* \brief Disable transmit -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_DisableTx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_DisableRx -//* \brief Disable receive -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_DisableRx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsTxEmpty -//* \brief Test if the current transfer descriptor has been sent -//*---------------------------------------------------------------------------- -__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_TCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsNextTxEmpty -//* \brief Test if the next transfer descriptor has been moved to the current td -//*---------------------------------------------------------------------------- -__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_TNCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsRxEmpty -//* \brief Test if the current transfer descriptor has been filled -//*---------------------------------------------------------------------------- -__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_RCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsNextRxEmpty -//* \brief Test if the next transfer descriptor has been moved to the current td -//*---------------------------------------------------------------------------- -__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_RNCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_Open -//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_Open ( - AT91PS_PDC pPDC) // \arg pointer to a PDC controller -{ - //* Disable the RX and TX PDC transfer requests - AT91F_PDC_DisableRx(pPDC); - AT91F_PDC_DisableTx(pPDC); - - //* Reset all Counter register Next buffer first - AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); - AT91F_PDC_SetTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetRx(pPDC, (char *) 0, 0); - - //* Enable the RX and TX PDC transfer requests - AT91F_PDC_EnableRx(pPDC); - AT91F_PDC_EnableTx(pPDC); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_Close -//* \brief Close PDC: disable TX and RX reset transfer descriptors -//*---------------------------------------------------------------------------- -__inline void AT91F_PDC_Close ( - AT91PS_PDC pPDC) // \arg pointer to a PDC controller -{ - //* Disable the RX and TX PDC transfer requests - AT91F_PDC_DisableRx(pPDC); - AT91F_PDC_DisableTx(pPDC); - - //* Reset all Counter register Next buffer first - AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); - AT91F_PDC_SetTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetRx(pPDC, (char *) 0, 0); - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SendFrame -//* \brief Close PDC: disable TX and RX reset transfer descriptors -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PDC_SendFrame( - AT91PS_PDC pPDC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - if (AT91F_PDC_IsTxEmpty(pPDC)) { - //* Buffer and next buffer can be initialized - AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer); - AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer); - return 2; - } - else if (AT91F_PDC_IsNextTxEmpty(pPDC)) { - //* Only one buffer can be initialized - AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer); - return 1; - } - else { - //* All buffer are in use... - return 0; - } -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_ReceiveFrame -//* \brief Close PDC: disable TX and RX reset transfer descriptors -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PDC_ReceiveFrame ( - AT91PS_PDC pPDC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - if (AT91F_PDC_IsRxEmpty(pPDC)) { - //* Buffer and next buffer can be initialized - AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer); - AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer); - return 2; - } - else if (AT91F_PDC_IsNextRxEmpty(pPDC)) { - //* Only one buffer can be initialized - AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer); - return 1; - } - else { - //* All buffer are in use... - return 0; - } -} -/* ***************************************************************************** - SOFTWARE API FOR DBGU - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_InterruptEnable -//* \brief Enable DBGU Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_DBGU_InterruptEnable( - AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller - unsigned int flag) // \arg dbgu interrupt to be enabled -{ - pDbgu->DBGU_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_InterruptDisable -//* \brief Disable DBGU Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_DBGU_InterruptDisable( - AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller - unsigned int flag) // \arg dbgu interrupt to be disabled -{ - pDbgu->DBGU_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_GetInterruptMaskStatus -//* \brief Return DBGU Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status - AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller -{ - return pDbgu->DBGU_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_IsInterruptMasked -//* \brief Test if DBGU Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_DBGU_IsInterruptMasked( - AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR PIO - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgPeriph -//* \brief Enable pins to be drived by peripheral -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgPeriph( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int periphAEnable, // \arg PERIPH A to enable - unsigned int periphBEnable) // \arg PERIPH B to enable - -{ - pPio->PIO_ASR = periphAEnable; - pPio->PIO_BSR = periphBEnable; - pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgOutput -//* \brief Enable PIO in output mode -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int pioEnable) // \arg PIO to be enabled -{ - pPio->PIO_PER = pioEnable; // Set in PIO mode - pPio->PIO_OER = pioEnable; // Configure in Output -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgInput -//* \brief Enable PIO in input mode -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgInput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int inputEnable) // \arg PIO to be enabled -{ - // Disable output - pPio->PIO_ODR = inputEnable; - pPio->PIO_PER = inputEnable; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgOpendrain -//* \brief Configure PIO in open drain -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgOpendrain( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int multiDrvEnable) // \arg pio to be configured in open drain -{ - // Configure the multi-drive option - pPio->PIO_MDDR = ~multiDrvEnable; - pPio->PIO_MDER = multiDrvEnable; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgPullup -//* \brief Enable pullup on PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgPullup( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int pullupEnable) // \arg enable pullup on PIO -{ - // Connect or not Pullup - pPio->PIO_PPUDR = ~pullupEnable; - pPio->PIO_PPUER = pullupEnable; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgDirectDrive -//* \brief Enable direct drive on PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgDirectDrive( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int directDrive) // \arg PIO to be configured with direct drive - -{ - // Configure the Direct Drive - pPio->PIO_OWDR = ~directDrive; - pPio->PIO_OWER = directDrive; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgInputFilter -//* \brief Enable input filter on input PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_CfgInputFilter( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int inputFilter) // \arg PIO to be configured with input filter - -{ - // Configure the Direct Drive - pPio->PIO_IFDR = ~inputFilter; - pPio->PIO_IFER = inputFilter; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInput -//* \brief Return PIO input value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetInput( // \return PIO input - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_PDSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInputSet -//* \brief Test if PIO is input flag is active -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsInputSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInput(pPio) & flag); -} - - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_SetOutput -//* \brief Set to 1 output PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_SetOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg output to be set -{ - pPio->PIO_SODR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_ClearOutput -//* \brief Set to 0 output PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_ClearOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg output to be cleared -{ - pPio->PIO_CODR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_ForceOutput -//* \brief Force output when Direct drive option is enabled -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_ForceOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg output to be forced -{ - pPio->PIO_ODSR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_Enable -//* \brief Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_Enable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be enabled -{ - pPio->PIO_PER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_Disable -//* \brief Disable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_Disable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be disabled -{ - pPio->PIO_PDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetStatus -//* \brief Return PIO Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_PSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsSet -//* \brief Test if PIO is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputEnable -//* \brief Output Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_OutputEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output to be enabled -{ - pPio->PIO_OER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputDisable -//* \brief Output Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_OutputDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output to be disabled -{ - pPio->PIO_ODR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetOutputStatus -//* \brief Return PIO Output Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_OSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsOuputSet -//* \brief Test if PIO Output is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsOutputSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetOutputStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InputFilterEnable -//* \brief Input Filter Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_InputFilterEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio input filter to be enabled -{ - pPio->PIO_IFER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InputFilterDisable -//* \brief Input Filter Disable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_InputFilterDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio input filter to be disabled -{ - pPio->PIO_IFDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInputFilterStatus -//* \brief Return PIO Input Filter Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_IFSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInputFilterSet -//* \brief Test if PIO Input filter is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsInputFilterSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInputFilterStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetOutputDataStatus -//* \brief Return PIO Output Data Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_ODSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InterruptEnable -//* \brief Enable PIO Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_InterruptEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio interrupt to be enabled -{ - pPio->PIO_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InterruptDisable -//* \brief Disable PIO Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_InterruptDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio interrupt to be disabled -{ - pPio->PIO_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInterruptMaskStatus -//* \brief Return PIO Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInterruptStatus -//* \brief Return PIO Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_ISR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInterruptMasked -//* \brief Test if PIO Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsInterruptMasked( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInterruptSet -//* \brief Test if PIO Interrupt is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsInterruptSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInterruptStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_MultiDriverEnable -//* \brief Multi Driver Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_MultiDriverEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be enabled -{ - pPio->PIO_MDER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_MultiDriverDisable -//* \brief Multi Driver Disable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_MultiDriverDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be disabled -{ - pPio->PIO_MDDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetMultiDriverStatus -//* \brief Return PIO Multi Driver Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_MDSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsMultiDriverSet -//* \brief Test if PIO MultiDriver is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsMultiDriverSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_A_RegisterSelection -//* \brief PIO A Register Selection -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_A_RegisterSelection( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio A register selection -{ - pPio->PIO_ASR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_B_RegisterSelection -//* \brief PIO B Register Selection -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_B_RegisterSelection( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio B register selection -{ - pPio->PIO_BSR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_Get_AB_RegisterStatus -//* \brief Return PIO Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_ABSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsAB_RegisterSet -//* \brief Test if PIO AB Register is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsAB_RegisterSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputWriteEnable -//* \brief Output Write Enable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_OutputWriteEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output write to be enabled -{ - pPio->PIO_OWER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputWriteDisable -//* \brief Output Write Disable PIO -//*---------------------------------------------------------------------------- -__inline void AT91F_PIO_OutputWriteDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output write to be disabled -{ - pPio->PIO_OWDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetOutputWriteStatus -//* \brief Return PIO Output Write Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_OWSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsOutputWriteSet -//* \brief Test if PIO OutputWrite is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsOutputWriteSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetCfgPullup -//* \brief Return PIO Configuration Pullup -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_PPUSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsOutputDataStatusSet -//* \brief Test if PIO Output Data Status is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsOutputDataStatusSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetOutputDataStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsCfgPullupStatusSet -//* \brief Test if PIO Configuration Pullup Status is Set -//*---------------------------------------------------------------------------- -__inline int AT91F_PIO_IsCfgPullupStatusSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (~AT91F_PIO_GetCfgPullup(pPio) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR PMC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgSysClkEnableReg -//* \brief Configure the System Clock Enable Register of the PMC controller -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_CfgSysClkEnableReg ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int mode) -{ - //* Write to the SCER register - pPMC->PMC_SCER = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgSysClkDisableReg -//* \brief Configure the System Clock Disable Register of the PMC controller -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_CfgSysClkDisableReg ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int mode) -{ - //* Write to the SCDR register - pPMC->PMC_SCDR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetSysClkStatusReg -//* \brief Return the System Clock Status Register of the PMC controller -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetSysClkStatusReg ( - AT91PS_PMC pPMC // pointer to a CAN controller - ) -{ - return pPMC->PMC_SCSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_EnablePeriphClock -//* \brief Enable peripheral clock -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_EnablePeriphClock ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int periphIds) // \arg IDs of peripherals to enable -{ - pPMC->PMC_PCER = periphIds; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_DisablePeriphClock -//* \brief Disable peripheral clock -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_DisablePeriphClock ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int periphIds) // \arg IDs of peripherals to enable -{ - pPMC->PMC_PCDR = periphIds; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetPeriphClock -//* \brief Get peripheral clock status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetPeriphClock ( - AT91PS_PMC pPMC) // \arg pointer to PMC controller -{ - return pPMC->PMC_PCSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_CfgMainOscillatorReg -//* \brief Cfg the main oscillator -//*---------------------------------------------------------------------------- -__inline void AT91F_CKGR_CfgMainOscillatorReg ( - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int mode) -{ - pCKGR->CKGR_MOR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_GetMainOscillatorReg -//* \brief Cfg the main oscillator -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CKGR_GetMainOscillatorReg ( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller -{ - return pCKGR->CKGR_MOR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_EnableMainOscillator -//* \brief Enable the main oscillator -//*---------------------------------------------------------------------------- -__inline void AT91F_CKGR_EnableMainOscillator( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller -{ - pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_DisableMainOscillator -//* \brief Disable the main oscillator -//*---------------------------------------------------------------------------- -__inline void AT91F_CKGR_DisableMainOscillator ( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller -{ - pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_CfgMainOscStartUpTime -//* \brief Cfg MOR Register according to the main osc startup time -//*---------------------------------------------------------------------------- -__inline void AT91F_CKGR_CfgMainOscStartUpTime ( - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int startup_time, // \arg main osc startup time in microsecond (us) - unsigned int slowClock) // \arg slowClock in Hz -{ - pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT; - pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_GetMainClockFreqReg -//* \brief Cfg the main oscillator -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CKGR_GetMainClockFreqReg ( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller -{ - return pCKGR->CKGR_MCFR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_GetMainClock -//* \brief Return Main clock in Hz -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CKGR_GetMainClock ( - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int slowClock) // \arg slowClock in Hz -{ - return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgMCKReg -//* \brief Cfg Master Clock Register -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_CfgMCKReg ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int mode) -{ - pPMC->PMC_MCKR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetMCKReg -//* \brief Return Master Clock Register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetMCKReg( - AT91PS_PMC pPMC) // \arg pointer to PMC controller -{ - return pPMC->PMC_MCKR; -} - -//*------------------------------------------------------------------------------ -//* \fn AT91F_PMC_GetMasterClock -//* \brief Return master clock in Hz which correponds to processor clock for ARM7 -//*------------------------------------------------------------------------------ -__inline unsigned int AT91F_PMC_GetMasterClock ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int slowClock) // \arg slowClock in Hz -{ - unsigned int reg = pPMC->PMC_MCKR; - unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2)); - unsigned int pllDivider, pllMultiplier; - - switch (reg & AT91C_PMC_CSS) { - case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected - return slowClock / prescaler; - case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected - return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler; - case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected - reg = pCKGR->CKGR_PLLR; - pllDivider = (reg & AT91C_CKGR_DIV); - pllMultiplier = ((reg & AT91C_CKGR_MUL) >> 16) + 1; - return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler; - } - return 0; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_EnablePCK -//* \brief Enable peripheral clock -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_EnablePCK ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int pck, // \arg Peripheral clock identifier 0 .. 7 - unsigned int mode) -{ - pPMC->PMC_PCKR[pck] = mode; - pPMC->PMC_SCER = (1 << pck) << 8; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_DisablePCK -//* \brief Enable peripheral clock -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_DisablePCK ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int pck) // \arg Peripheral clock identifier 0 .. 7 -{ - pPMC->PMC_SCDR = (1 << pck) << 8; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_EnableIt -//* \brief Enable PMC interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_EnableIt ( - AT91PS_PMC pPMC, // pointer to a PMC controller - unsigned int flag) // IT to be enabled -{ - //* Write to the IER register - pPMC->PMC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_DisableIt -//* \brief Disable PMC interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_DisableIt ( - AT91PS_PMC pPMC, // pointer to a PMC controller - unsigned int flag) // IT to be disabled -{ - //* Write to the IDR register - pPMC->PMC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetStatus -//* \brief Return PMC Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status - AT91PS_PMC pPMC) // pointer to a PMC controller -{ - return pPMC->PMC_SR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetInterruptMaskStatus -//* \brief Return PMC Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status - AT91PS_PMC pPMC) // pointer to a PMC controller -{ - return pPMC->PMC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_IsInterruptMasked -//* \brief Test if PMC Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_IsInterruptMasked( - AT91PS_PMC pPMC, // \arg pointer to a PMC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_IsStatusSet -//* \brief Test if PMC Status is Set -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PMC_IsStatusSet( - AT91PS_PMC pPMC, // \arg pointer to a PMC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PMC_GetStatus(pPMC) & flag); -}/* ***************************************************************************** - SOFTWARE API FOR RSTC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTSoftReset -//* \brief Start Software Reset -//*---------------------------------------------------------------------------- -__inline void AT91F_RSTSoftReset( - AT91PS_RSTC pRSTC, - unsigned int reset) -{ - pRSTC->RSTC_RCR = (0xA5000000 | reset); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTSetMode -//* \brief Set Reset Mode -//*---------------------------------------------------------------------------- -__inline void AT91F_RSTSetMode( - AT91PS_RSTC pRSTC, - unsigned int mode) -{ - pRSTC->RSTC_RMR = (0xA5000000 | mode); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTGetMode -//* \brief Get Reset Mode -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_RSTGetMode( - AT91PS_RSTC pRSTC) -{ - return (pRSTC->RSTC_RMR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTGetStatus -//* \brief Get Reset Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_RSTGetStatus( - AT91PS_RSTC pRSTC) -{ - return (pRSTC->RSTC_RSR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTIsSoftRstActive -//* \brief Return !=0 if software reset is still not completed -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_RSTIsSoftRstActive( - AT91PS_RSTC pRSTC) -{ - return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP); -} -/* ***************************************************************************** - SOFTWARE API FOR RTTC - ***************************************************************************** */ -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_SetRTT_TimeBase() -//* \brief Set the RTT prescaler according to the TimeBase in ms -//*-------------------------------------------------------------------------------------- -__inline unsigned int AT91F_RTTSetTimeBase( - AT91PS_RTTC pRTTC, - unsigned int ms) -{ - if (ms > 2000) - return 1; // AT91C_TIME_OUT_OF_RANGE - pRTTC->RTTC_RTMR &= ~0xFFFF; - pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF); - return 0; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTTSetPrescaler() -//* \brief Set the new prescaler value -//*-------------------------------------------------------------------------------------- -__inline unsigned int AT91F_RTTSetPrescaler( - AT91PS_RTTC pRTTC, - unsigned int rtpres) -{ - pRTTC->RTTC_RTMR &= ~0xFFFF; - pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF); - return (pRTTC->RTTC_RTMR); -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTTRestart() -//* \brief Restart the RTT prescaler -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTRestart( - AT91PS_RTTC pRTTC) -{ - pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST; -} - - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_SetAlarmINT() -//* \brief Enable RTT Alarm Interrupt -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTSetAlarmINT( - AT91PS_RTTC pRTTC) -{ - pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_ClearAlarmINT() -//* \brief Disable RTT Alarm Interrupt -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTClearAlarmINT( - AT91PS_RTTC pRTTC) -{ - pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_SetRttIncINT() -//* \brief Enable RTT INC Interrupt -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTSetRttIncINT( - AT91PS_RTTC pRTTC) -{ - pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_ClearRttIncINT() -//* \brief Disable RTT INC Interrupt -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTClearRttIncINT( - AT91PS_RTTC pRTTC) -{ - pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_SetAlarmValue() -//* \brief Set RTT Alarm Value -//*-------------------------------------------------------------------------------------- -__inline void AT91F_RTTSetAlarmValue( - AT91PS_RTTC pRTTC, unsigned int alarm) -{ - pRTTC->RTTC_RTAR = alarm; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_GetAlarmValue() -//* \brief Get RTT Alarm Value -//*-------------------------------------------------------------------------------------- -__inline unsigned int AT91F_RTTGetAlarmValue( - AT91PS_RTTC pRTTC) -{ - return(pRTTC->RTTC_RTAR); -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTTGetStatus() -//* \brief Read the RTT status -//*-------------------------------------------------------------------------------------- -__inline unsigned int AT91F_RTTGetStatus( - AT91PS_RTTC pRTTC) -{ - return(pRTTC->RTTC_RTSR); -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_ReadValue() -//* \brief Read the RTT value -//*-------------------------------------------------------------------------------------- -__inline unsigned int AT91F_RTTReadValue( - AT91PS_RTTC pRTTC) -{ - register volatile unsigned int val1,val2; - do - { - val1 = pRTTC->RTTC_RTVR; - val2 = pRTTC->RTTC_RTVR; - } - while(val1 != val2); - return(val1); -} -/* ***************************************************************************** - SOFTWARE API FOR PITC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITInit -//* \brief System timer init : period in µsecond, system clock freq in MHz -//*---------------------------------------------------------------------------- -__inline void AT91F_PITInit( - AT91PS_PITC pPITC, - unsigned int period, - unsigned int pit_frequency) -{ - pPITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0; // +8 to avoid %10 and /10 - pPITC->PITC_PIMR |= AT91C_PITC_PITEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITSetPIV -//* \brief Set the PIT Periodic Interval Value -//*---------------------------------------------------------------------------- -__inline void AT91F_PITSetPIV( - AT91PS_PITC pPITC, - unsigned int piv) -{ - pPITC->PITC_PIMR = piv | (pPITC->PITC_PIMR & (AT91C_PITC_PITEN | AT91C_PITC_PITIEN)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITEnableInt -//* \brief Enable PIT periodic interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PITEnableInt( - AT91PS_PITC pPITC) -{ - pPITC->PITC_PIMR |= AT91C_PITC_PITIEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITDisableInt -//* \brief Disable PIT periodic interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PITDisableInt( - AT91PS_PITC pPITC) -{ - pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITGetMode -//* \brief Read PIT mode register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PITGetMode( - AT91PS_PITC pPITC) -{ - return(pPITC->PITC_PIMR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITGetStatus -//* \brief Read PIT status register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PITGetStatus( - AT91PS_PITC pPITC) -{ - return(pPITC->PITC_PISR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITGetPIIR -//* \brief Read PIT CPIV and PICNT without ressetting the counters -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PITGetPIIR( - AT91PS_PITC pPITC) -{ - return(pPITC->PITC_PIIR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITGetPIVR -//* \brief Read System timer CPIV and PICNT without ressetting the counters -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PITGetPIVR( - AT91PS_PITC pPITC) -{ - return(pPITC->PITC_PIVR); -} -/* ***************************************************************************** - SOFTWARE API FOR WDTC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_WDTSetMode -//* \brief Set Watchdog Mode Register -//*---------------------------------------------------------------------------- -__inline void AT91F_WDTSetMode( - AT91PS_WDTC pWDTC, - unsigned int Mode) -{ - pWDTC->WDTC_WDMR = Mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_WDTRestart -//* \brief Restart Watchdog -//*---------------------------------------------------------------------------- -__inline void AT91F_WDTRestart( - AT91PS_WDTC pWDTC) -{ - pWDTC->WDTC_WDCR = 0xA5000001; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_WDTSGettatus -//* \brief Get Watchdog Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_WDTSGettatus( - AT91PS_WDTC pWDTC) -{ - return(pWDTC->WDTC_WDSR & 0x3); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_WDTGetPeriod -//* \brief Translate ms into Watchdog Compatible value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_WDTGetPeriod(unsigned int ms) -{ - if ((ms < 4) || (ms > 16000)) - return 0; - return((ms << 8) / 1000); -} -/* ***************************************************************************** - SOFTWARE API FOR VREG - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_VREG_Enable_LowPowerMode -//* \brief Enable VREG Low Power Mode -//*---------------------------------------------------------------------------- -__inline void AT91F_VREG_Enable_LowPowerMode( - AT91PS_VREG pVREG) -{ - pVREG->VREG_MR |= AT91C_VREG_PSTDBY; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_VREG_Disable_LowPowerMode -//* \brief Disable VREG Low Power Mode -//*---------------------------------------------------------------------------- -__inline void AT91F_VREG_Disable_LowPowerMode( - AT91PS_VREG pVREG) -{ - pVREG->VREG_MR &= ~AT91C_VREG_PSTDBY; -}/* ***************************************************************************** - SOFTWARE API FOR MC - ***************************************************************************** */ - -#define AT91C_MC_CORRECT_KEY ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_Remap -//* \brief Make Remap -//*---------------------------------------------------------------------------- -__inline void AT91F_MC_Remap (void) // -{ - AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC; - - pMC->MC_RCR = AT91C_MC_RCB; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_CfgModeReg -//* \brief Configure the EFC Mode Register of the MC controller -//*---------------------------------------------------------------------------- -__inline void AT91F_MC_EFC_CfgModeReg ( - AT91PS_MC pMC, // pointer to a MC controller - unsigned int mode) // mode register -{ - // Write to the FMR register - pMC->MC_FMR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_GetModeReg -//* \brief Return MC EFC Mode Regsiter -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MC_EFC_GetModeReg( - AT91PS_MC pMC) // pointer to a MC controller -{ - return pMC->MC_FMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_ComputeFMCN -//* \brief Return MC EFC Mode Regsiter -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MC_EFC_ComputeFMCN( - int master_clock) // master clock in Hz -{ - return (master_clock/1000000 +2); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_PerformCmd -//* \brief Perform EFC Command -//*---------------------------------------------------------------------------- -__inline void AT91F_MC_EFC_PerformCmd ( - AT91PS_MC pMC, // pointer to a MC controller - unsigned int transfer_cmd) -{ - pMC->MC_FCR = transfer_cmd; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_GetStatus -//* \brief Return MC EFC Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MC_EFC_GetStatus( - AT91PS_MC pMC) // pointer to a MC controller -{ - return pMC->MC_FSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_IsInterruptMasked -//* \brief Test if EFC MC Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MC_EFC_IsInterruptMasked( - AT91PS_MC pMC, // \arg pointer to a MC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_MC_EFC_GetModeReg(pMC) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_IsInterruptSet -//* \brief Test if EFC MC Interrupt is Set -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_MC_EFC_IsInterruptSet( - AT91PS_MC pMC, // \arg pointer to a MC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_MC_EFC_GetStatus(pMC) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR SPI - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Open -//* \brief Open a SPI Port -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SPI_Open ( - const unsigned int null) // \arg -{ - /* NOT DEFINED AT THIS MOMENT */ - return ( 0 ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_CfgCs -//* \brief Configure SPI chip select register -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_CfgCs ( - AT91PS_SPI pSPI, // pointer to a SPI controller - int cs, // SPI cs number (0 to 3) - int val) // chip select register -{ - //* Write to the CSR register - *(pSPI->SPI_CSR + cs) = val; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_EnableIt -//* \brief Enable SPI interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_EnableIt ( - AT91PS_SPI pSPI, // pointer to a SPI controller - unsigned int flag) // IT to be enabled -{ - //* Write to the IER register - pSPI->SPI_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_DisableIt -//* \brief Disable SPI interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_DisableIt ( - AT91PS_SPI pSPI, // pointer to a SPI controller - unsigned int flag) // IT to be disabled -{ - //* Write to the IDR register - pSPI->SPI_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Reset -//* \brief Reset the SPI controller -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_Reset ( - AT91PS_SPI pSPI // pointer to a SPI controller - ) -{ - //* Write to the CR register - pSPI->SPI_CR = AT91C_SPI_SWRST; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Enable -//* \brief Enable the SPI controller -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_Enable ( - AT91PS_SPI pSPI // pointer to a SPI controller - ) -{ - //* Write to the CR register - pSPI->SPI_CR = AT91C_SPI_SPIEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Disable -//* \brief Disable the SPI controller -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_Disable ( - AT91PS_SPI pSPI // pointer to a SPI controller - ) -{ - //* Write to the CR register - pSPI->SPI_CR = AT91C_SPI_SPIDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_CfgMode -//* \brief Enable the SPI controller -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_CfgMode ( - AT91PS_SPI pSPI, // pointer to a SPI controller - int mode) // mode register -{ - //* Write to the MR register - pSPI->SPI_MR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_CfgPCS -//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_CfgPCS ( - AT91PS_SPI pSPI, // pointer to a SPI controller - char PCS_Device) // PCS of the Device -{ - //* Write to the MR register - pSPI->SPI_MR &= 0xFFF0FFFF; - pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_ReceiveFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SPI_ReceiveFrame ( - AT91PS_SPI pSPI, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_ReceiveFrame( - (AT91PS_PDC) &(pSPI->SPI_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_SendFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SPI_SendFrame( - AT91PS_SPI pSPI, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_SendFrame( - (AT91PS_PDC) &(pSPI->SPI_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Close -//* \brief Close SPI: disable IT disable transfert, close PDC -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_Close ( - AT91PS_SPI pSPI) // \arg pointer to a SPI controller -{ - //* Reset all the Chip Select register - pSPI->SPI_CSR[0] = 0 ; - pSPI->SPI_CSR[1] = 0 ; - pSPI->SPI_CSR[2] = 0 ; - pSPI->SPI_CSR[3] = 0 ; - - //* Reset the SPI mode - pSPI->SPI_MR = 0 ; - - //* Disable all interrupts - pSPI->SPI_IDR = 0xFFFFFFFF ; - - //* Abort the Peripheral Data Transfers - AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR)); - - //* Disable receiver and transmitter and stop any activity immediately - pSPI->SPI_CR = AT91C_SPI_SPIDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_PutChar -//* \brief Send a character,does not check if ready to send -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI_PutChar ( - AT91PS_SPI pSPI, - unsigned int character, - unsigned int cs_number ) -{ - unsigned int value_for_cs; - value_for_cs = (~(1 << cs_number)) & 0xF; //Place a zero among a 4 ONEs number - pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_GetChar -//* \brief Receive a character,does not check if a character is available -//*---------------------------------------------------------------------------- -__inline int AT91F_SPI_GetChar ( - const AT91PS_SPI pSPI) -{ - return((pSPI->SPI_RDR) & 0xFFFF); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_GetInterruptMaskStatus -//* \brief Return SPI Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status - AT91PS_SPI pSpi) // \arg pointer to a SPI controller -{ - return pSpi->SPI_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_IsInterruptMasked -//* \brief Test if SPI Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_SPI_IsInterruptMasked( - AT91PS_SPI pSpi, // \arg pointer to a SPI controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR USART - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Baudrate -//* \brief Calculate the baudrate -//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity -#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_NONE + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CLKS_CLOCK ) - -//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity -#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_NONE + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CLKS_EXT ) - -//* Standard Synchronous Mode : 8 bits , 1 stop , no parity -#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \ - AT91C_US_USMODE_NORMAL + \ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_NONE + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CLKS_CLOCK ) - -//* SCK used Label -#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT) - -//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity -#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \ - AT91C_US_CLKS_CLOCK +\ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_EVEN + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CKLO +\ - AT91C_US_OVER) - -//* Standard IRDA mode -#define AT91C_US_ASYNC_IRDA_MODE ( AT91C_US_USMODE_IRDA + \ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_NONE + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CLKS_CLOCK ) - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Baudrate -//* \brief Caluculate baud_value according to the main clock and the baud rate -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_US_Baudrate ( - const unsigned int main_clock, // \arg peripheral clock - const unsigned int baud_rate) // \arg UART baudrate -{ - unsigned int baud_value = ((main_clock*10)/(baud_rate * 16)); - if ((baud_value % 10) >= 5) - baud_value = (baud_value / 10) + 1; - else - baud_value /= 10; - return baud_value; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_SetBaudrate -//* \brief Set the baudrate according to the CPU clock -//*---------------------------------------------------------------------------- -__inline void AT91F_US_SetBaudrate ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int mainClock, // \arg peripheral clock - unsigned int speed) // \arg UART baudrate -{ - //* Define the baud rate divisor register - pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_SetTimeguard -//* \brief Set USART timeguard -//*---------------------------------------------------------------------------- -__inline void AT91F_US_SetTimeguard ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int timeguard) // \arg timeguard value -{ - //* Write the Timeguard Register - pUSART->US_TTGR = timeguard ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_EnableIt -//* \brief Enable USART IT -//*---------------------------------------------------------------------------- -__inline void AT91F_US_EnableIt ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int flag) // \arg IT to be enabled -{ - //* Write to the IER register - pUSART->US_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_DisableIt -//* \brief Disable USART IT -//*---------------------------------------------------------------------------- -__inline void AT91F_US_DisableIt ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int flag) // \arg IT to be disabled -{ - //* Write to the IER register - pUSART->US_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Configure -//* \brief Configure USART -//*---------------------------------------------------------------------------- -__inline void AT91F_US_Configure ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int mainClock, // \arg peripheral clock - unsigned int mode , // \arg mode Register to be programmed - unsigned int baudRate , // \arg baudrate to be programmed - unsigned int timeguard ) // \arg timeguard to be programmed -{ - //* Disable interrupts - pUSART->US_IDR = (unsigned int) -1; - - //* Reset receiver and transmitter - pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ; - - //* Define the baud rate divisor register - AT91F_US_SetBaudrate(pUSART, mainClock, baudRate); - - //* Write the Timeguard Register - AT91F_US_SetTimeguard(pUSART, timeguard); - - //* Clear Transmit and Receive Counters - AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR)); - - //* Define the USART mode - pUSART->US_MR = mode ; - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_EnableRx -//* \brief Enable receiving characters -//*---------------------------------------------------------------------------- -__inline void AT91F_US_EnableRx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Enable receiver - pUSART->US_CR = AT91C_US_RXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_EnableTx -//* \brief Enable sending characters -//*---------------------------------------------------------------------------- -__inline void AT91F_US_EnableTx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Enable transmitter - pUSART->US_CR = AT91C_US_TXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_ResetRx -//* \brief Reset Receiver and re-enable it -//*---------------------------------------------------------------------------- -__inline void AT91F_US_ResetRx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Reset receiver - pUSART->US_CR = AT91C_US_RSTRX; - //* Re-Enable receiver - pUSART->US_CR = AT91C_US_RXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_ResetTx -//* \brief Reset Transmitter and re-enable it -//*---------------------------------------------------------------------------- -__inline void AT91F_US_ResetTx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Reset transmitter - pUSART->US_CR = AT91C_US_RSTTX; - //* Enable transmitter - pUSART->US_CR = AT91C_US_TXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_DisableRx -//* \brief Disable Receiver -//*---------------------------------------------------------------------------- -__inline void AT91F_US_DisableRx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Disable receiver - pUSART->US_CR = AT91C_US_RXDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_DisableTx -//* \brief Disable Transmitter -//*---------------------------------------------------------------------------- -__inline void AT91F_US_DisableTx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Disable transmitter - pUSART->US_CR = AT91C_US_TXDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Close -//* \brief Close USART: disable IT disable receiver and transmitter, close PDC -//*---------------------------------------------------------------------------- -__inline void AT91F_US_Close ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Reset the baud rate divisor register - pUSART->US_BRGR = 0 ; - - //* Reset the USART mode - pUSART->US_MR = 0 ; - - //* Reset the Timeguard Register - pUSART->US_TTGR = 0; - - //* Disable all interrupts - pUSART->US_IDR = 0xFFFFFFFF ; - - //* Abort the Peripheral Data Transfers - AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR)); - - //* Disable receiver and transmitter and stop any activity immediately - pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_TxReady -//* \brief Return 1 if a character can be written in US_THR -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_US_TxReady ( - AT91PS_USART pUSART ) // \arg pointer to a USART controller -{ - return (pUSART->US_CSR & AT91C_US_TXRDY); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_RxReady -//* \brief Return 1 if a character can be read in US_RHR -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_US_RxReady ( - AT91PS_USART pUSART ) // \arg pointer to a USART controller -{ - return (pUSART->US_CSR & AT91C_US_RXRDY); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Error -//* \brief Return the error flag -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_US_Error ( - AT91PS_USART pUSART ) // \arg pointer to a USART controller -{ - return (pUSART->US_CSR & - (AT91C_US_OVRE | // Overrun error - AT91C_US_FRAME | // Framing error - AT91C_US_PARE)); // Parity error -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_PutChar -//* \brief Send a character,does not check if ready to send -//*---------------------------------------------------------------------------- -__inline void AT91F_US_PutChar ( - AT91PS_USART pUSART, - int character ) -{ - pUSART->US_THR = (character & 0x1FF); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_GetChar -//* \brief Receive a character,does not check if a character is available -//*---------------------------------------------------------------------------- -__inline int AT91F_US_GetChar ( - const AT91PS_USART pUSART) -{ - return((pUSART->US_RHR) & 0x1FF); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_SendFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_US_SendFrame( - AT91PS_USART pUSART, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_SendFrame( - (AT91PS_PDC) &(pUSART->US_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_ReceiveFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_US_ReceiveFrame ( - AT91PS_USART pUSART, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_ReceiveFrame( - (AT91PS_PDC) &(pUSART->US_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_SetIrdaFilter -//* \brief Set the value of IrDa filter tregister -//*---------------------------------------------------------------------------- -__inline void AT91F_US_SetIrdaFilter ( - AT91PS_USART pUSART, - unsigned char value -) -{ - pUSART->US_IF = value; -} - -/* ***************************************************************************** - SOFTWARE API FOR SSC - ***************************************************************************** */ -//* Define the standard I2S mode configuration - -//* Configuration to set in the SSC Transmit Clock Mode Register -//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits -//* nb_slot_by_frame : number of channels -#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ - AT91C_SSC_CKS_DIV +\ - AT91C_SSC_CKO_CONTINOUS +\ - AT91C_SSC_CKG_NONE +\ - AT91C_SSC_START_FALL_RF +\ - AT91C_SSC_STTOUT +\ - ((1<<16) & AT91C_SSC_STTDLY) +\ - ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24)) - - -//* Configuration to set in the SSC Transmit Frame Mode Register -//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits -//* nb_slot_by_frame : number of channels -#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ - (nb_bit_by_slot-1) +\ - AT91C_SSC_MSBF +\ - (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\ - (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\ - AT91C_SSC_FSOS_NEGATIVE) - - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_SetBaudrate -//* \brief Set the baudrate according to the CPU clock -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_SetBaudrate ( - AT91PS_SSC pSSC, // \arg pointer to a SSC controller - unsigned int mainClock, // \arg peripheral clock - unsigned int speed) // \arg SSC baudrate -{ - unsigned int baud_value; - //* Define the baud rate divisor register - if (speed == 0) - baud_value = 0; - else - { - baud_value = (unsigned int) (mainClock * 10)/(2*speed); - if ((baud_value % 10) >= 5) - baud_value = (baud_value / 10) + 1; - else - baud_value /= 10; - } - - pSSC->SSC_CMR = baud_value; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_Configure -//* \brief Configure SSC -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_Configure ( - AT91PS_SSC pSSC, // \arg pointer to a SSC controller - unsigned int syst_clock, // \arg System Clock Frequency - unsigned int baud_rate, // \arg Expected Baud Rate Frequency - unsigned int clock_rx, // \arg Receiver Clock Parameters - unsigned int mode_rx, // \arg mode Register to be programmed - unsigned int clock_tx, // \arg Transmitter Clock Parameters - unsigned int mode_tx) // \arg mode Register to be programmed -{ - //* Disable interrupts - pSSC->SSC_IDR = (unsigned int) -1; - - //* Reset receiver and transmitter - pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ; - - //* Define the Clock Mode Register - AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate); - - //* Write the Receive Clock Mode Register - pSSC->SSC_RCMR = clock_rx; - - //* Write the Transmit Clock Mode Register - pSSC->SSC_TCMR = clock_tx; - - //* Write the Receive Frame Mode Register - pSSC->SSC_RFMR = mode_rx; - - //* Write the Transmit Frame Mode Register - pSSC->SSC_TFMR = mode_tx; - - //* Clear Transmit and Receive Counters - AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR)); - - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_EnableRx -//* \brief Enable receiving datas -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_EnableRx ( - AT91PS_SSC pSSC) // \arg pointer to a SSC controller -{ - //* Enable receiver - pSSC->SSC_CR = AT91C_SSC_RXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_DisableRx -//* \brief Disable receiving datas -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_DisableRx ( - AT91PS_SSC pSSC) // \arg pointer to a SSC controller -{ - //* Disable receiver - pSSC->SSC_CR = AT91C_SSC_RXDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_EnableTx -//* \brief Enable sending datas -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_EnableTx ( - AT91PS_SSC pSSC) // \arg pointer to a SSC controller -{ - //* Enable transmitter - pSSC->SSC_CR = AT91C_SSC_TXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_DisableTx -//* \brief Disable sending datas -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_DisableTx ( - AT91PS_SSC pSSC) // \arg pointer to a SSC controller -{ - //* Disable transmitter - pSSC->SSC_CR = AT91C_SSC_TXDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_EnableIt -//* \brief Enable SSC IT -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_EnableIt ( - AT91PS_SSC pSSC, // \arg pointer to a SSC controller - unsigned int flag) // \arg IT to be enabled -{ - //* Write to the IER register - pSSC->SSC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_DisableIt -//* \brief Disable SSC IT -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_DisableIt ( - AT91PS_SSC pSSC, // \arg pointer to a SSC controller - unsigned int flag) // \arg IT to be disabled -{ - //* Write to the IDR register - pSSC->SSC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_ReceiveFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SSC_ReceiveFrame ( - AT91PS_SSC pSSC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_ReceiveFrame( - (AT91PS_PDC) &(pSSC->SSC_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_SendFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SSC_SendFrame( - AT91PS_SSC pSSC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_SendFrame( - (AT91PS_PDC) &(pSSC->SSC_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_GetInterruptMaskStatus -//* \brief Return SSC Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status - AT91PS_SSC pSsc) // \arg pointer to a SSC controller -{ - return pSsc->SSC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_IsInterruptMasked -//* \brief Test if SSC Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_SSC_IsInterruptMasked( - AT91PS_SSC pSsc, // \arg pointer to a SSC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR TWI - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_EnableIt -//* \brief Enable TWI IT -//*---------------------------------------------------------------------------- -__inline void AT91F_TWI_EnableIt ( - AT91PS_TWI pTWI, // \arg pointer to a TWI controller - unsigned int flag) // \arg IT to be enabled -{ - //* Write to the IER register - pTWI->TWI_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_DisableIt -//* \brief Disable TWI IT -//*---------------------------------------------------------------------------- -__inline void AT91F_TWI_DisableIt ( - AT91PS_TWI pTWI, // \arg pointer to a TWI controller - unsigned int flag) // \arg IT to be disabled -{ - //* Write to the IDR register - pTWI->TWI_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_Configure -//* \brief Configure TWI in master mode -//*---------------------------------------------------------------------------- -__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI ) // \arg pointer to a TWI controller -{ - //* Disable interrupts - pTWI->TWI_IDR = (unsigned int) -1; - - //* Reset peripheral - pTWI->TWI_CR = AT91C_TWI_SWRST; - - //* Set Master mode - pTWI->TWI_CR = AT91C_TWI_MSEN; - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_GetInterruptMaskStatus -//* \brief Return TWI Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status - AT91PS_TWI pTwi) // \arg pointer to a TWI controller -{ - return pTwi->TWI_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_IsInterruptMasked -//* \brief Test if TWI Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_TWI_IsInterruptMasked( - AT91PS_TWI pTwi, // \arg pointer to a TWI controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR PWMC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_GetStatus -//* \brief Return PWM Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status - AT91PS_PWMC pPWM) // pointer to a PWM controller -{ - return pPWM->PWMC_SR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_InterruptEnable -//* \brief Enable PWM Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_InterruptEnable( - AT91PS_PWMC pPwm, // \arg pointer to a PWM controller - unsigned int flag) // \arg PWM interrupt to be enabled -{ - pPwm->PWMC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_InterruptDisable -//* \brief Disable PWM Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_InterruptDisable( - AT91PS_PWMC pPwm, // \arg pointer to a PWM controller - unsigned int flag) // \arg PWM interrupt to be disabled -{ - pPwm->PWMC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_GetInterruptMaskStatus -//* \brief Return PWM Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status - AT91PS_PWMC pPwm) // \arg pointer to a PWM controller -{ - return pPwm->PWMC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_IsInterruptMasked -//* \brief Test if PWM Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PWMC_IsInterruptMasked( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_IsStatusSet -//* \brief Test if PWM Interrupt is Set -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_PWMC_IsStatusSet( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PWMC_GetStatus(pPWM) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_CfgChannel -//* \brief Test if PWM Interrupt is Set -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CfgChannel( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int channelId, // \arg PWM channel ID - unsigned int mode, // \arg PWM mode - unsigned int period, // \arg PWM period - unsigned int duty) // \arg PWM duty cycle -{ - pPWM->PWMC_CH[channelId].PWMC_CMR = mode; - pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty; - pPWM->PWMC_CH[channelId].PWMC_CPRDR = period; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_StartChannel -//* \brief Enable channel -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_StartChannel( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int flag) // \arg Channels IDs to be enabled -{ - pPWM->PWMC_ENA = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_StopChannel -//* \brief Disable channel -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_StopChannel( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int flag) // \arg Channels IDs to be enabled -{ - pPWM->PWMC_DIS = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_UpdateChannel -//* \brief Update Period or Duty Cycle -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_UpdateChannel( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int channelId, // \arg PWM channel ID - unsigned int update) // \arg Channels IDs to be enabled -{ - pPWM->PWMC_CH[channelId].PWMC_CUPDR = update; -} - -/* ***************************************************************************** - SOFTWARE API FOR UDP - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EnableIt -//* \brief Enable UDP IT -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EnableIt ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg IT to be enabled -{ - //* Write to the IER register - pUDP->UDP_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_DisableIt -//* \brief Disable UDP IT -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_DisableIt ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg IT to be disabled -{ - //* Write to the IDR register - pUDP->UDP_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_SetAddress -//* \brief Set UDP functional address -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_SetAddress ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char address) // \arg new UDP address -{ - pUDP->UDP_FADDR = (AT91C_UDP_FEN | address); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EnableEp -//* \brief Enable Endpoint -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EnableEp ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - pUDP->UDP_CSR[endpoint] |= AT91C_UDP_EPEDS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_DisableEp -//* \brief Enable Endpoint -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_DisableEp ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - pUDP->UDP_CSR[endpoint] &= ~AT91C_UDP_EPEDS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_SetState -//* \brief Set UDP Device state -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_SetState ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg new UDP address -{ - pUDP->UDP_GLBSTATE &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG); - pUDP->UDP_GLBSTATE |= flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_GetState -//* \brief return UDP Device state -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state - AT91PS_UDP pUDP) // \arg pointer to a UDP controller -{ - return (pUDP->UDP_GLBSTATE & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_ResetEp -//* \brief Reset UDP endpoint -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_ResetEp ( // \return the UDP device state - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg Endpoints to be reset -{ - pUDP->UDP_RSTEP = flag; - pUDP->UDP_RSTEP = 0; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpStall -//* \brief Endpoint will STALL requests -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EpStall( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpWrite -//* \brief Write value in the DPR -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EpWrite( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint, // \arg endpoint number - unsigned char value) // \arg value to be written in the DPR -{ - pUDP->UDP_FDR[endpoint] = value; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpRead -//* \brief Return value from the DPR -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_UDP_EpRead( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - return pUDP->UDP_FDR[endpoint]; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpEndOfWr -//* \brief Notify the UDP that values in DPR are ready to be sent -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EpEndOfWr( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpClear -//* \brief Clear flag in the endpoint CSR register -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EpClear( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint, // \arg endpoint number - unsigned int flag) // \arg flag to be cleared -{ - pUDP->UDP_CSR[endpoint] &= ~(flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpSet -//* \brief Set flag in the endpoint CSR register -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_EpSet( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint, // \arg endpoint number - unsigned int flag) // \arg flag to be cleared -{ - pUDP->UDP_CSR[endpoint] |= flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpStatus -//* \brief Return the endpoint CSR register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_UDP_EpStatus( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - return pUDP->UDP_CSR[endpoint]; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_GetInterruptMaskStatus -//* \brief Return UDP Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status - AT91PS_UDP pUdp) // \arg pointer to a UDP controller -{ - return pUdp->UDP_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_IsInterruptMasked -//* \brief Test if UDP Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_UDP_IsInterruptMasked( - AT91PS_UDP pUdp, // \arg pointer to a UDP controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR TC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC_InterruptEnable -//* \brief Enable TC Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_TC_InterruptEnable( - AT91PS_TC pTc, // \arg pointer to a TC controller - unsigned int flag) // \arg TC interrupt to be enabled -{ - pTc->TC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC_InterruptDisable -//* \brief Disable TC Interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_TC_InterruptDisable( - AT91PS_TC pTc, // \arg pointer to a TC controller - unsigned int flag) // \arg TC interrupt to be disabled -{ - pTc->TC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC_GetInterruptMaskStatus -//* \brief Return TC Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status - AT91PS_TC pTc) // \arg pointer to a TC controller -{ - return pTc->TC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC_IsInterruptMasked -//* \brief Test if TC Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline int AT91F_TC_IsInterruptMasked( - AT91PS_TC pTc, // \arg pointer to a TC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR CAN - ***************************************************************************** */ -#define STANDARD_FORMAT 0 -#define EXTENDED_FORMAT 1 - -//*---------------------------------------------------------------------------- -//* \fn AT91F_InitMailboxRegisters() -//* \brief Configure the corresponding mailbox -//*---------------------------------------------------------------------------- -__inline void AT91F_InitMailboxRegisters(AT91PS_CAN_MB CAN_Mailbox, - int mode_reg, - int acceptance_mask_reg, - int id_reg, - int data_low_reg, - int data_high_reg, - int control_reg) -{ - CAN_Mailbox->CAN_MB_MCR = 0x0; - CAN_Mailbox->CAN_MB_MMR = mode_reg; - CAN_Mailbox->CAN_MB_MAM = acceptance_mask_reg; - CAN_Mailbox->CAN_MB_MID = id_reg; - CAN_Mailbox->CAN_MB_MDL = data_low_reg; - CAN_Mailbox->CAN_MB_MDH = data_high_reg; - CAN_Mailbox->CAN_MB_MCR = control_reg; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_EnableCAN() -//* \brief -//*---------------------------------------------------------------------------- -__inline void AT91F_EnableCAN( - AT91PS_CAN pCAN) // pointer to a CAN controller -{ - pCAN->CAN_MR |= AT91C_CAN_CANEN; - - // Wait for WAKEUP flag raising <=> 11-recessive-bit were scanned by the transceiver - while( (pCAN->CAN_SR & AT91C_CAN_WAKEUP) != AT91C_CAN_WAKEUP ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DisableCAN() -//* \brief -//*---------------------------------------------------------------------------- -__inline void AT91F_DisableCAN( - AT91PS_CAN pCAN) // pointer to a CAN controller -{ - pCAN->CAN_MR &= ~AT91C_CAN_CANEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_EnableIt -//* \brief Enable CAN interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_EnableIt ( - AT91PS_CAN pCAN, // pointer to a CAN controller - unsigned int flag) // IT to be enabled -{ - //* Write to the IER register - pCAN->CAN_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_DisableIt -//* \brief Disable CAN interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_DisableIt ( - AT91PS_CAN pCAN, // pointer to a CAN controller - unsigned int flag) // IT to be disabled -{ - //* Write to the IDR register - pCAN->CAN_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetStatus -//* \brief Return CAN Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetStatus( // \return CAN Interrupt Status - AT91PS_CAN pCAN) // pointer to a CAN controller -{ - return pCAN->CAN_SR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetInterruptMaskStatus -//* \brief Return CAN Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetInterruptMaskStatus( // \return CAN Interrupt Mask Status - AT91PS_CAN pCAN) // pointer to a CAN controller -{ - return pCAN->CAN_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_IsInterruptMasked -//* \brief Test if CAN Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_IsInterruptMasked( - AT91PS_CAN pCAN, // \arg pointer to a CAN controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_CAN_GetInterruptMaskStatus(pCAN) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_IsStatusSet -//* \brief Test if CAN Interrupt is Set -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_IsStatusSet( - AT91PS_CAN pCAN, // \arg pointer to a CAN controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_CAN_GetStatus(pCAN) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgModeReg -//* \brief Configure the Mode Register of the CAN controller -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgModeReg ( - AT91PS_CAN pCAN, // pointer to a CAN controller - unsigned int mode) // mode register -{ - //* Write to the MR register - pCAN->CAN_MR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetModeReg -//* \brief Return the Mode Register of the CAN controller value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetModeReg ( - AT91PS_CAN pCAN // pointer to a CAN controller - ) -{ - return pCAN->CAN_MR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgBaudrateReg -//* \brief Configure the Baudrate of the CAN controller for the network -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgBaudrateReg ( - AT91PS_CAN pCAN, // pointer to a CAN controller - unsigned int baudrate_cfg) -{ - //* Write to the BR register - pCAN->CAN_BR = baudrate_cfg; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetBaudrate -//* \brief Return the Baudrate of the CAN controller for the network value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetBaudrate ( - AT91PS_CAN pCAN // pointer to a CAN controller - ) -{ - return pCAN->CAN_BR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetInternalCounter -//* \brief Return CAN Timer Regsiter Value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetInternalCounter ( - AT91PS_CAN pCAN // pointer to a CAN controller - ) -{ - return pCAN->CAN_TIM; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetTimestamp -//* \brief Return CAN Timestamp Register Value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetTimestamp ( - AT91PS_CAN pCAN // pointer to a CAN controller - ) -{ - return pCAN->CAN_TIMESTP; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetErrorCounter -//* \brief Return CAN Error Counter Register Value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetErrorCounter ( - AT91PS_CAN pCAN // pointer to a CAN controller - ) -{ - return pCAN->CAN_ECR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_InitTransferRequest -//* \brief Request for a transfer on the corresponding mailboxes -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_InitTransferRequest ( - AT91PS_CAN pCAN, // pointer to a CAN controller - unsigned int transfer_cmd) -{ - pCAN->CAN_TCR = transfer_cmd; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_InitAbortRequest -//* \brief Abort the corresponding mailboxes -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_InitAbortRequest ( - AT91PS_CAN pCAN, // pointer to a CAN controller - unsigned int abort_cmd) -{ - pCAN->CAN_ACR = abort_cmd; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgMessageModeReg -//* \brief Program the Message Mode Register -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgMessageModeReg ( - AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox - unsigned int mode) -{ - CAN_Mailbox->CAN_MB_MMR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetMessageModeReg -//* \brief Return the Message Mode Register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetMessageModeReg ( - AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox -{ - return CAN_Mailbox->CAN_MB_MMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgMessageIDReg -//* \brief Program the Message ID Register -//* \brief Version == 0 for Standard messsage, Version == 1 for Extended -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgMessageIDReg ( - AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox - unsigned int id, - unsigned char version) -{ - if(version==0) // IDvA Standard Format - CAN_Mailbox->CAN_MB_MID = id<<18; - else // IDvB Extended Format - CAN_Mailbox->CAN_MB_MID = id | (1<<29); // set MIDE bit -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetMessageIDReg -//* \brief Return the Message ID Register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetMessageIDReg ( - AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox -{ - return CAN_Mailbox->CAN_MB_MID; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgMessageAcceptanceMaskReg -//* \brief Program the Message Acceptance Mask Register -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgMessageAcceptanceMaskReg ( - AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox - unsigned int mask) -{ - CAN_Mailbox->CAN_MB_MAM = mask; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetMessageAcceptanceMaskReg -//* \brief Return the Message Acceptance Mask Register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetMessageAcceptanceMaskReg ( - AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox -{ - return CAN_Mailbox->CAN_MB_MAM; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetFamilyID -//* \brief Return the Message ID Register -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetFamilyID ( - AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox -{ - return CAN_Mailbox->CAN_MB_MFID; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgMessageCtrl -//* \brief Request and config for a transfer on the corresponding mailbox -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgMessageCtrlReg ( - AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox - unsigned int message_ctrl_cmd) -{ - CAN_Mailbox->CAN_MB_MCR = message_ctrl_cmd; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetMessageStatus -//* \brief Return CAN Mailbox Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetMessageStatus ( - AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox -{ - return CAN_Mailbox->CAN_MB_MSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgMessageDataLow -//* \brief Program data low value -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgMessageDataLow ( - AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox - unsigned int data) -{ - CAN_Mailbox->CAN_MB_MDL = data; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetMessageDataLow -//* \brief Return data low value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetMessageDataLow ( - AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox -{ - return CAN_Mailbox->CAN_MB_MDL; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgMessageDataHigh -//* \brief Program data high value -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgMessageDataHigh ( - AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox - unsigned int data) -{ - CAN_Mailbox->CAN_MB_MDH = data; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetMessageDataHigh -//* \brief Return data high value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_GetMessageDataHigh ( - AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox -{ - return CAN_Mailbox->CAN_MB_MDH; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_Open -//* \brief Open a CAN Port -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_CAN_Open ( - const unsigned int null) // \arg -{ - /* NOT DEFINED AT THIS MOMENT */ - return ( 0 ); -} -/* ***************************************************************************** - SOFTWARE API FOR ADC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_EnableIt -//* \brief Enable ADC interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_EnableIt ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int flag) // IT to be enabled -{ - //* Write to the IER register - pADC->ADC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_DisableIt -//* \brief Disable ADC interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_DisableIt ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int flag) // IT to be disabled -{ - //* Write to the IDR register - pADC->ADC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetStatus -//* \brief Return ADC Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status - AT91PS_ADC pADC) // pointer to a ADC controller -{ - return pADC->ADC_SR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetInterruptMaskStatus -//* \brief Return ADC Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status - AT91PS_ADC pADC) // pointer to a ADC controller -{ - return pADC->ADC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_IsInterruptMasked -//* \brief Test if ADC Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_IsInterruptMasked( - AT91PS_ADC pADC, // \arg pointer to a ADC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_IsStatusSet -//* \brief Test if ADC Status is Set -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_IsStatusSet( - AT91PS_ADC pADC, // \arg pointer to a ADC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_ADC_GetStatus(pADC) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_CfgModeReg -//* \brief Configure the Mode Register of the ADC controller -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_CfgModeReg ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int mode) // mode register -{ - //* Write to the MR register - pADC->ADC_MR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetModeReg -//* \brief Return the Mode Register of the ADC controller value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetModeReg ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_MR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_CfgTimings -//* \brief Configure the different necessary timings of the ADC controller -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_CfgTimings ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int mck_clock, // in MHz - unsigned int adc_clock, // in MHz - unsigned int startup_time, // in us - unsigned int sample_and_hold_time) // in ns -{ - unsigned int prescal,startup,shtim; - - prescal = mck_clock/(2*adc_clock) - 1; - startup = adc_clock*startup_time/8 - 1; - shtim = adc_clock*sample_and_hold_time/1000 - 1; - - //* Write to the MR register - pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_EnableChannel -//* \brief Return ADC Timer Register Value -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_EnableChannel ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int channel) // mode register -{ - //* Write to the CHER register - pADC->ADC_CHER = channel; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_DisableChannel -//* \brief Return ADC Timer Register Value -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_DisableChannel ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int channel) // mode register -{ - //* Write to the CHDR register - pADC->ADC_CHDR = channel; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetChannelStatus -//* \brief Return ADC Timer Register Value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetChannelStatus ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CHSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_StartConversion -//* \brief Software request for a analog to digital conversion -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_StartConversion ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - pADC->ADC_CR = AT91C_ADC_START; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_SoftReset -//* \brief Software reset -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_SoftReset ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - pADC->ADC_CR = AT91C_ADC_SWRST; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetLastConvertedData -//* \brief Return the Last Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetLastConvertedData ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_LCDR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH0 -//* \brief Return the Channel 0 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH0 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR0; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH1 -//* \brief Return the Channel 1 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH1 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR1; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH2 -//* \brief Return the Channel 2 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH2 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR2; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH3 -//* \brief Return the Channel 3 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH3 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR3; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH4 -//* \brief Return the Channel 4 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH4 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR4; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH5 -//* \brief Return the Channel 5 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH5 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR5; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH6 -//* \brief Return the Channel 6 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH6 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR6; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH7 -//* \brief Return the Channel 7 Converted Data -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_ADC_GetConvertedDataCH7 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR7; -} - -/* ***************************************************************************** - SOFTWARE API FOR AES - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_EnableIt -//* \brief Enable AES interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_AES_EnableIt ( - AT91PS_AES pAES, // pointer to a AES controller - unsigned int flag) // IT to be enabled -{ - //* Write to the IER register - pAES->AES_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_DisableIt -//* \brief Disable AES interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_AES_DisableIt ( - AT91PS_AES pAES, // pointer to a AES controller - unsigned int flag) // IT to be disabled -{ - //* Write to the IDR register - pAES->AES_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_GetStatus -//* \brief Return AES Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AES_GetStatus( // \return AES Interrupt Status - AT91PS_AES pAES) // pointer to a AES controller -{ - return pAES->AES_ISR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_GetInterruptMaskStatus -//* \brief Return AES Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AES_GetInterruptMaskStatus( // \return AES Interrupt Mask Status - AT91PS_AES pAES) // pointer to a AES controller -{ - return pAES->AES_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_IsInterruptMasked -//* \brief Test if AES Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AES_IsInterruptMasked( - AT91PS_AES pAES, // \arg pointer to a AES controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_AES_GetInterruptMaskStatus(pAES) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_IsStatusSet -//* \brief Test if AES Status is Set -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AES_IsStatusSet( - AT91PS_AES pAES, // \arg pointer to a AES controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_AES_GetStatus(pAES) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_CfgModeReg -//* \brief Configure the Mode Register of the AES controller -//*---------------------------------------------------------------------------- -__inline void AT91F_AES_CfgModeReg ( - AT91PS_AES pAES, // pointer to a AES controller - unsigned int mode) // mode register -{ - //* Write to the MR register - pAES->AES_MR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_GetModeReg -//* \brief Return the Mode Register of the AES controller value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AES_GetModeReg ( - AT91PS_AES pAES // pointer to a AES controller - ) -{ - return pAES->AES_MR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_StartProcessing -//* \brief Start Encryption or Decryption -//*---------------------------------------------------------------------------- -__inline void AT91F_AES_StartProcessing ( - AT91PS_AES pAES // pointer to a AES controller - ) -{ - pAES->AES_CR = AT91C_AES_START; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_SoftReset -//* \brief Reset AES -//*---------------------------------------------------------------------------- -__inline void AT91F_AES_SoftReset ( - AT91PS_AES pAES // pointer to a AES controller - ) -{ - pAES->AES_CR = AT91C_AES_SWRST; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_LoadNewSeed -//* \brief Load New Seed in the random number generator -//*---------------------------------------------------------------------------- -__inline void AT91F_AES_LoadNewSeed ( - AT91PS_AES pAES // pointer to a AES controller - ) -{ - pAES->AES_CR = AT91C_AES_LOADSEED; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_SetCryptoKey -//* \brief Set Cryptographic Key x -//*---------------------------------------------------------------------------- -__inline void AT91F_AES_SetCryptoKey ( - AT91PS_AES pAES, // pointer to a AES controller - unsigned char index, - unsigned int keyword - ) -{ - pAES->AES_KEYWxR[index] = keyword; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_InputData -//* \brief Set Input Data x -//*---------------------------------------------------------------------------- -__inline void AT91F_AES_InputData ( - AT91PS_AES pAES, // pointer to a AES controller - unsigned char index, - unsigned int indata - ) -{ - pAES->AES_IDATAxR[index] = indata; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_GetOutputData -//* \brief Get Output Data x -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_AES_GetOutputData ( - AT91PS_AES pAES, // pointer to a AES controller - unsigned char index - ) -{ - return pAES->AES_ODATAxR[index]; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_SetInitializationVector -//* \brief Set Initialization Vector (or Counter) x -//*---------------------------------------------------------------------------- -__inline void AT91F_AES_SetInitializationVector ( - AT91PS_AES pAES, // pointer to a AES controller - unsigned char index, - unsigned int initvector - ) -{ - pAES->AES_IVxR[index] = initvector; -} - -/* ***************************************************************************** - SOFTWARE API FOR TDES - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_EnableIt -//* \brief Enable TDES interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_TDES_EnableIt ( - AT91PS_TDES pTDES, // pointer to a TDES controller - unsigned int flag) // IT to be enabled -{ - //* Write to the IER register - pTDES->TDES_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_DisableIt -//* \brief Disable TDES interrupt -//*---------------------------------------------------------------------------- -__inline void AT91F_TDES_DisableIt ( - AT91PS_TDES pTDES, // pointer to a TDES controller - unsigned int flag) // IT to be disabled -{ - //* Write to the IDR register - pTDES->TDES_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_GetStatus -//* \brief Return TDES Interrupt Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_TDES_GetStatus( // \return TDES Interrupt Status - AT91PS_TDES pTDES) // pointer to a TDES controller -{ - return pTDES->TDES_ISR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_GetInterruptMaskStatus -//* \brief Return TDES Interrupt Mask Status -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_TDES_GetInterruptMaskStatus( // \return TDES Interrupt Mask Status - AT91PS_TDES pTDES) // pointer to a TDES controller -{ - return pTDES->TDES_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_IsInterruptMasked -//* \brief Test if TDES Interrupt is Masked -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_TDES_IsInterruptMasked( - AT91PS_TDES pTDES, // \arg pointer to a TDES controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_TDES_GetInterruptMaskStatus(pTDES) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_IsStatusSet -//* \brief Test if TDES Status is Set -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_TDES_IsStatusSet( - AT91PS_TDES pTDES, // \arg pointer to a TDES controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_TDES_GetStatus(pTDES) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_CfgModeReg -//* \brief Configure the Mode Register of the TDES controller -//*---------------------------------------------------------------------------- -__inline void AT91F_TDES_CfgModeReg ( - AT91PS_TDES pTDES, // pointer to a TDES controller - unsigned int mode) // mode register -{ - //* Write to the MR register - pTDES->TDES_MR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_GetModeReg -//* \brief Return the Mode Register of the TDES controller value -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_TDES_GetModeReg ( - AT91PS_TDES pTDES // pointer to a TDES controller - ) -{ - return pTDES->TDES_MR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_StartProcessing -//* \brief Start Encryption or Decryption -//*---------------------------------------------------------------------------- -__inline void AT91F_TDES_StartProcessing ( - AT91PS_TDES pTDES // pointer to a TDES controller - ) -{ - pTDES->TDES_CR = AT91C_TDES_START; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_SoftReset -//* \brief Reset TDES -//*---------------------------------------------------------------------------- -__inline void AT91F_TDES_SoftReset ( - AT91PS_TDES pTDES // pointer to a TDES controller - ) -{ - pTDES->TDES_CR = AT91C_TDES_SWRST; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_SetCryptoKey1 -//* \brief Set Cryptographic Key 1 Word x -//*---------------------------------------------------------------------------- -__inline void AT91F_TDES_SetCryptoKey1 ( - AT91PS_TDES pTDES, // pointer to a TDES controller - unsigned char index, - unsigned int keyword - ) -{ - pTDES->TDES_KEY1WxR[index] = keyword; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_SetCryptoKey2 -//* \brief Set Cryptographic Key 2 Word x -//*---------------------------------------------------------------------------- -__inline void AT91F_TDES_SetCryptoKey2 ( - AT91PS_TDES pTDES, // pointer to a TDES controller - unsigned char index, - unsigned int keyword - ) -{ - pTDES->TDES_KEY2WxR[index] = keyword; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_SetCryptoKey3 -//* \brief Set Cryptographic Key 3 Word x -//*---------------------------------------------------------------------------- -__inline void AT91F_TDES_SetCryptoKey3 ( - AT91PS_TDES pTDES, // pointer to a TDES controller - unsigned char index, - unsigned int keyword - ) -{ - pTDES->TDES_KEY3WxR[index] = keyword; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_InputData -//* \brief Set Input Data x -//*---------------------------------------------------------------------------- -__inline void AT91F_TDES_InputData ( - AT91PS_TDES pTDES, // pointer to a TDES controller - unsigned char index, - unsigned int indata - ) -{ - pTDES->TDES_IDATAxR[index] = indata; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_GetOutputData -//* \brief Get Output Data x -//*---------------------------------------------------------------------------- -__inline unsigned int AT91F_TDES_GetOutputData ( - AT91PS_TDES pTDES, // pointer to a TDES controller - unsigned char index - ) -{ - return pTDES->TDES_ODATAxR[index]; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_SetInitializationVector -//* \brief Set Initialization Vector x -//*---------------------------------------------------------------------------- -__inline void AT91F_TDES_SetInitializationVector ( - AT91PS_TDES pTDES, // pointer to a TDES controller - unsigned char index, - unsigned int initvector - ) -{ - pTDES->TDES_IVxR[index] = initvector; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_CfgPMC -//* \brief Enable Peripheral clock in PMC for DBGU -//*---------------------------------------------------------------------------- -__inline void AT91F_DBGU_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_CfgPIO -//* \brief Configure PIO controllers to drive DBGU signals -//*---------------------------------------------------------------------------- -__inline void AT91F_DBGU_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA27_DRXD ) | - ((unsigned int) AT91C_PA28_DTXD ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgPMC -//* \brief Enable Peripheral clock in PMC for PMC -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgPIO -//* \brief Configure PIO controllers to drive PMC signals -//*---------------------------------------------------------------------------- -__inline void AT91F_PMC_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB30_PCK2 ) | - ((unsigned int) AT91C_PB29_PCK1 ), // Peripheral A - ((unsigned int) AT91C_PB20_PCK0 ) | - ((unsigned int) AT91C_PB0_PCK0 ) | - ((unsigned int) AT91C_PB22_PCK2 ) | - ((unsigned int) AT91C_PB21_PCK1 )); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PA30_PCK2 ) | - ((unsigned int) AT91C_PA13_PCK1 ) | - ((unsigned int) AT91C_PA27_PCK3 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_VREG_CfgPMC -//* \brief Enable Peripheral clock in PMC for VREG -//*---------------------------------------------------------------------------- -__inline void AT91F_VREG_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTC_CfgPMC -//* \brief Enable Peripheral clock in PMC for RSTC -//*---------------------------------------------------------------------------- -__inline void AT91F_RSTC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_CfgPMC -//* \brief Enable Peripheral clock in PMC for SSC -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SSC)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_CfgPIO -//* \brief Configure PIO controllers to drive SSC signals -//*---------------------------------------------------------------------------- -__inline void AT91F_SSC_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA25_RK ) | - ((unsigned int) AT91C_PA22_TK ) | - ((unsigned int) AT91C_PA21_TF ) | - ((unsigned int) AT91C_PA24_RD ) | - ((unsigned int) AT91C_PA26_RF ) | - ((unsigned int) AT91C_PA23_TD ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_WDTC_CfgPMC -//* \brief Enable Peripheral clock in PMC for WDTC -//*---------------------------------------------------------------------------- -__inline void AT91F_WDTC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US1_CfgPMC -//* \brief Enable Peripheral clock in PMC for US1 -//*---------------------------------------------------------------------------- -__inline void AT91F_US1_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_US1)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US1_CfgPIO -//* \brief Configure PIO controllers to drive US1 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_US1_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PB26_RI1 ) | - ((unsigned int) AT91C_PB24_DSR1 ) | - ((unsigned int) AT91C_PB23_DCD1 ) | - ((unsigned int) AT91C_PB25_DTR1 )); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA7_SCK1 ) | - ((unsigned int) AT91C_PA8_RTS1 ) | - ((unsigned int) AT91C_PA6_TXD1 ) | - ((unsigned int) AT91C_PA5_RXD1 ) | - ((unsigned int) AT91C_PA9_CTS1 ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US0_CfgPMC -//* \brief Enable Peripheral clock in PMC for US0 -//*---------------------------------------------------------------------------- -__inline void AT91F_US0_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_US0)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US0_CfgPIO -//* \brief Configure PIO controllers to drive US0 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_US0_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA0_RXD0 ) | - ((unsigned int) AT91C_PA4_CTS0 ) | - ((unsigned int) AT91C_PA3_RTS0 ) | - ((unsigned int) AT91C_PA2_SCK0 ) | - ((unsigned int) AT91C_PA1_TXD0 ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI1_CfgPMC -//* \brief Enable Peripheral clock in PMC for SPI1 -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI1_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SPI1)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI1_CfgPIO -//* \brief Configure PIO controllers to drive SPI1 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI1_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PB16_NPCS13 ) | - ((unsigned int) AT91C_PB10_NPCS11 ) | - ((unsigned int) AT91C_PB11_NPCS12 )); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PA4_NPCS13 ) | - ((unsigned int) AT91C_PA29_NPCS13 ) | - ((unsigned int) AT91C_PA21_NPCS10 ) | - ((unsigned int) AT91C_PA22_SPCK1 ) | - ((unsigned int) AT91C_PA25_NPCS11 ) | - ((unsigned int) AT91C_PA2_NPCS11 ) | - ((unsigned int) AT91C_PA24_MISO1 ) | - ((unsigned int) AT91C_PA3_NPCS12 ) | - ((unsigned int) AT91C_PA26_NPCS12 ) | - ((unsigned int) AT91C_PA23_MOSI1 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI0_CfgPMC -//* \brief Enable Peripheral clock in PMC for SPI0 -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI0_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SPI0)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI0_CfgPIO -//* \brief Configure PIO controllers to drive SPI0 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_SPI0_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PB13_NPCS01 ) | - ((unsigned int) AT91C_PB17_NPCS03 ) | - ((unsigned int) AT91C_PB14_NPCS02 )); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA16_MISO0 ) | - ((unsigned int) AT91C_PA13_NPCS01 ) | - ((unsigned int) AT91C_PA15_NPCS03 ) | - ((unsigned int) AT91C_PA17_MOSI0 ) | - ((unsigned int) AT91C_PA18_SPCK0 ) | - ((unsigned int) AT91C_PA14_NPCS02 ) | - ((unsigned int) AT91C_PA12_NPCS00 ), // Peripheral A - ((unsigned int) AT91C_PA7_NPCS01 ) | - ((unsigned int) AT91C_PA9_NPCS03 ) | - ((unsigned int) AT91C_PA8_NPCS02 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITC_CfgPMC -//* \brief Enable Peripheral clock in PMC for PITC -//*---------------------------------------------------------------------------- -__inline void AT91F_PITC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_CfgPMC -//* \brief Enable Peripheral clock in PMC for AIC -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_FIQ) | - ((unsigned int) 1 << AT91C_ID_IRQ0) | - ((unsigned int) 1 << AT91C_ID_IRQ1)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_CfgPIO -//* \brief Configure PIO controllers to drive AIC signals -//*---------------------------------------------------------------------------- -__inline void AT91F_AIC_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA30_IRQ0 ) | - ((unsigned int) AT91C_PA29_FIQ ), // Peripheral A - ((unsigned int) AT91C_PA14_IRQ1 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AES_CfgPMC -//* \brief Enable Peripheral clock in PMC for AES -//*---------------------------------------------------------------------------- -__inline void AT91F_AES_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_AES)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_CfgPMC -//* \brief Enable Peripheral clock in PMC for TWI -//*---------------------------------------------------------------------------- -__inline void AT91F_TWI_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TWI)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_CfgPIO -//* \brief Configure PIO controllers to drive TWI signals -//*---------------------------------------------------------------------------- -__inline void AT91F_TWI_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA11_TWCK ) | - ((unsigned int) AT91C_PA10_TWD ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_CfgPMC -//* \brief Enable Peripheral clock in PMC for ADC -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_ADC)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_CfgPIO -//* \brief Configure PIO controllers to drive ADC signals -//*---------------------------------------------------------------------------- -__inline void AT91F_ADC_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PB18_ADTRG )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CH3_CfgPIO -//* \brief Configure PIO controllers to drive PWMC_CH3 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CH3_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB22_PWM3 ), // Peripheral A - ((unsigned int) AT91C_PB30_PWM3 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CH2_CfgPIO -//* \brief Configure PIO controllers to drive PWMC_CH2 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CH2_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB21_PWM2 ), // Peripheral A - ((unsigned int) AT91C_PB29_PWM2 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CH1_CfgPIO -//* \brief Configure PIO controllers to drive PWMC_CH1 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CH1_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB20_PWM1 ), // Peripheral A - ((unsigned int) AT91C_PB28_PWM1 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CH0_CfgPIO -//* \brief Configure PIO controllers to drive PWMC_CH0 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CH0_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB19_PWM0 ), // Peripheral A - ((unsigned int) AT91C_PB27_PWM0 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RTTC_CfgPMC -//* \brief Enable Peripheral clock in PMC for RTTC -//*---------------------------------------------------------------------------- -__inline void AT91F_RTTC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_CfgPMC -//* \brief Enable Peripheral clock in PMC for UDP -//*---------------------------------------------------------------------------- -__inline void AT91F_UDP_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_UDP)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TDES_CfgPMC -//* \brief Enable Peripheral clock in PMC for TDES -//*---------------------------------------------------------------------------- -__inline void AT91F_TDES_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TDES)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_EMAC_CfgPMC -//* \brief Enable Peripheral clock in PMC for EMAC -//*---------------------------------------------------------------------------- -__inline void AT91F_EMAC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_EMAC)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_EMAC_CfgPIO -//* \brief Configure PIO controllers to drive EMAC signals -//*---------------------------------------------------------------------------- -__inline void AT91F_EMAC_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB2_ETX0 ) | - ((unsigned int) AT91C_PB12_ETXER ) | - ((unsigned int) AT91C_PB16_ECOL ) | - ((unsigned int) AT91C_PB11_ETX3 ) | - ((unsigned int) AT91C_PB6_ERX1 ) | - ((unsigned int) AT91C_PB15_ERXDV ) | - ((unsigned int) AT91C_PB13_ERX2 ) | - ((unsigned int) AT91C_PB3_ETX1 ) | - ((unsigned int) AT91C_PB8_EMDC ) | - ((unsigned int) AT91C_PB5_ERX0 ) | - //((unsigned int) AT91C_PB18_EF100 ) | - ((unsigned int) AT91C_PB14_ERX3 ) | - ((unsigned int) AT91C_PB4_ECRS_ECRSDV) | - ((unsigned int) AT91C_PB1_ETXEN ) | - ((unsigned int) AT91C_PB10_ETX2 ) | - ((unsigned int) AT91C_PB0_ETXCK_EREFCK) | - ((unsigned int) AT91C_PB9_EMDIO ) | - ((unsigned int) AT91C_PB7_ERXER ) | - ((unsigned int) AT91C_PB17_ERXCK ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC0_CfgPMC -//* \brief Enable Peripheral clock in PMC for TC0 -//*---------------------------------------------------------------------------- -__inline void AT91F_TC0_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TC0)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC0_CfgPIO -//* \brief Configure PIO controllers to drive TC0 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_TC0_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB23_TIOA0 ) | - ((unsigned int) AT91C_PB24_TIOB0 ), // Peripheral A - ((unsigned int) AT91C_PB12_TCLK0 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC1_CfgPMC -//* \brief Enable Peripheral clock in PMC for TC1 -//*---------------------------------------------------------------------------- -__inline void AT91F_TC1_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TC1)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC1_CfgPIO -//* \brief Configure PIO controllers to drive TC1 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_TC1_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB25_TIOA1 ) | - ((unsigned int) AT91C_PB26_TIOB1 ), // Peripheral A - ((unsigned int) AT91C_PB19_TCLK1 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC2_CfgPMC -//* \brief Enable Peripheral clock in PMC for TC2 -//*---------------------------------------------------------------------------- -__inline void AT91F_TC2_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TC2)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC2_CfgPIO -//* \brief Configure PIO controllers to drive TC2 signals -//*---------------------------------------------------------------------------- -__inline void AT91F_TC2_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOB, // PIO controller base address - ((unsigned int) AT91C_PB28_TIOB2 ) | - ((unsigned int) AT91C_PB27_TIOA2 ), // Peripheral A - 0); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PA15_TCLK2 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_CfgPMC -//* \brief Enable Peripheral clock in PMC for MC -//*---------------------------------------------------------------------------- -__inline void AT91F_MC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIOA_CfgPMC -//* \brief Enable Peripheral clock in PMC for PIOA -//*---------------------------------------------------------------------------- -__inline void AT91F_PIOA_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_PIOA)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIOB_CfgPMC -//* \brief Enable Peripheral clock in PMC for PIOB -//*---------------------------------------------------------------------------- -__inline void AT91F_PIOB_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_PIOB)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgPMC -//* \brief Enable Peripheral clock in PMC for CAN -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_CAN)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgPIO -//* \brief Configure PIO controllers to drive CAN signals -//*---------------------------------------------------------------------------- -__inline void AT91F_CAN_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA20_CANTX ) | - ((unsigned int) AT91C_PA19_CANRX ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CfgPMC -//* \brief Enable Peripheral clock in PMC for PWMC -//*---------------------------------------------------------------------------- -__inline void AT91F_PWMC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_PWMC)); -} - -#endif // lib_AT91SAM7X256_H diff --git a/Source/portable/IAR/AtmelSAM7S64/port.c b/Source/portable/IAR/AtmelSAM7S64/port.c deleted file mode 100644 index bb17de14c..000000000 --- a/Source/portable/IAR/AtmelSAM7S64/port.c +++ /dev/null @@ -1,253 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the Atmel ARM7 port. - *----------------------------------------------------------*/ - - -/* Standard includes. */ -#include -#include - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Constants required to setup the initial stack. */ -#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */ -#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 ) - -/* Constants required to setup the PIT. */ -#define portPIT_CLOCK_DIVISOR ( ( unsigned portLONG ) 16 ) -#define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_RATE_MS ) - -/* Constants required to handle critical sections. */ -#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 ) - - -#define portINT_LEVEL_SENSITIVE 0 -#define portPIT_ENABLE ( ( unsigned portSHORT ) 0x1 << 24 ) -#define portPIT_INT_ENABLE ( ( unsigned portSHORT ) 0x1 << 25 ) -/*-----------------------------------------------------------*/ - -/* Setup the PIT to generate the tick interrupts. */ -static void prvSetupTimerInterrupt( void ); - -/* ulCriticalNesting will get set to zero when the first task starts. It -cannot be initialised to 0 as this will cause interrupts to be enabled -during the kernel initialisation process. */ -unsigned portLONG ulCriticalNesting = ( unsigned portLONG ) 9999; - -/*-----------------------------------------------------------*/ - -/* - * Initialise the stack of a task to look exactly as if a call to - * portSAVE_CONTEXT had been called. - * - * See header file for description. - */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) -{ -portSTACK_TYPE *pxOriginalTOS; - - pxOriginalTOS = pxTopOfStack; - - /* Setup the initial stack of the task. The stack is set exactly as - expected by the portRESTORE_CONTEXT() macro. */ - - /* First on the stack is the return address - which in this case is the - start of the task. The offset is added to make the return address appear - as it would within an IRQ ISR. */ - *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; - pxTopOfStack--; - - *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */ - pxTopOfStack--; - - /* When the task starts is will expect to find the function parameter in - R0. */ - *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ - pxTopOfStack--; - - /* The status register is set for system mode, with interrupts enabled. */ - *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR; - pxTopOfStack--; - - /* Interrupt flags cannot always be stored on the stack and will - instead be stored in a variable, which is then saved as part of the - tasks context. */ - *pxTopOfStack = portNO_CRITICAL_NESTING; - - return pxTopOfStack; -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xPortStartScheduler( void ) -{ -extern void vPortStartFirstTask( void ); - - /* Start the timer that generates the tick ISR. Interrupts are disabled - here already. */ - prvSetupTimerInterrupt(); - - /* Start the first task. */ - vPortStartFirstTask(); - - /* Should not get here! */ - return 0; -} -/*-----------------------------------------------------------*/ - -void vPortEndScheduler( void ) -{ - /* It is unlikely that the ARM port will require this function as there - is nothing to return to. */ -} -/*-----------------------------------------------------------*/ - -#if configUSE_PREEMPTION == 0 - - /* The cooperative scheduler requires a normal IRQ service routine to - simply increment the system tick. */ - static __arm __irq void vPortNonPreemptiveTick( void ); - static __arm __irq void vPortNonPreemptiveTick( void ) - { - unsigned portLONG ulDummy; - - /* Increment the tick count - which may wake some tasks but as the - preemptive scheduler is not being used any woken task is not given - processor time no matter what its priority. */ - vTaskIncrementTick(); - - /* Clear the PIT interrupt. */ - ulDummy = AT91C_BASE_PITC->PITC_PIVR; - - /* End the interrupt in the AIC. */ - AT91C_BASE_AIC->AIC_EOICR = ulDummy; - } - -#else - - /* Currently the IAR port requires the preemptive tick function to be - defined in an asm file. */ - -#endif - -/*-----------------------------------------------------------*/ - -static void prvSetupTimerInterrupt( void ) -{ -AT91PS_PITC pxPIT = AT91C_BASE_PITC; - - /* Setup the AIC for PIT interrupts. The interrupt routine chosen depends - on whether the preemptive or cooperative scheduler is being used. */ - #if configUSE_PREEMPTION == 0 - - AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPortNonPreemptiveTick ); - - #else - - extern void ( vPortPreemptiveTick )( void ); - AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPortPreemptiveTick ); - - #endif - - /* Configure the PIT period. */ - pxPIT->PITC_PIMR = portPIT_ENABLE | portPIT_INT_ENABLE | portPIT_COUNTER_VALUE; - - /* Enable the interrupt. Global interrupts are disables at this point so - this is safe. */ - AT91F_AIC_EnableIt( AT91C_BASE_AIC, AT91C_ID_SYS ); -} -/*-----------------------------------------------------------*/ - -void vPortEnterCritical( void ) -{ - /* Disable interrupts first! */ - __disable_interrupt(); - - /* Now interrupts are disabled ulCriticalNesting can be accessed - directly. Increment ulCriticalNesting to keep a count of how many times - portENTER_CRITICAL() has been called. */ - ulCriticalNesting++; -} -/*-----------------------------------------------------------*/ - -void vPortExitCritical( void ) -{ - if( ulCriticalNesting > portNO_CRITICAL_NESTING ) - { - /* Decrement the nesting count as we are leaving a critical section. */ - ulCriticalNesting--; - - /* If the nesting level has reached zero then interrupts should be - re-enabled. */ - if( ulCriticalNesting == portNO_CRITICAL_NESTING ) - { - __enable_interrupt(); - } - } -} -/*-----------------------------------------------------------*/ - - - - - - diff --git a/Source/portable/IAR/AtmelSAM7S64/portasm.s79 b/Source/portable/IAR/AtmelSAM7S64/portasm.s79 deleted file mode 100644 index 691b95be4..000000000 --- a/Source/portable/IAR/AtmelSAM7S64/portasm.s79 +++ /dev/null @@ -1,59 +0,0 @@ - RSEG ICODE:CODE - CODE32 - - EXTERN vTaskSwitchContext - EXTERN vTaskIncrementTick - - PUBLIC vPortYieldProcessor - PUBLIC vPortPreemptiveTick - PUBLIC vPortStartFirstTask - -#include "AT91SAM7S64_inc.h" -#include "ISR_Support.h" - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Starting the first task is just a matter of restoring the context that -; was created by pxPortInitialiseStack(). -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -vPortStartFirstTask: - portRESTORE_CONTEXT - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Manual context switch function. This is the SWI hander. -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -vPortYieldProcessor: - ADD LR, LR, #4 ; Add 4 to the LR to make the LR appear exactly - ; as if the context was saved during and IRQ - ; handler. - - portSAVE_CONTEXT ; Save the context of the current task... - LDR R0, =vTaskSwitchContext ; before selecting the next task to execute. - mov lr, pc - BX R0 - portRESTORE_CONTEXT ; Restore the context of the selected task. - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Preemptive context switch function. This will only ever get installed if -; portUSE_PREEMPTION is set to 1 in portmacro.h. -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -vPortPreemptiveTick: - portSAVE_CONTEXT ; Save the context of the current task. - - LDR R0, =vTaskIncrementTick ; Increment the tick count - this may wake a task. - mov lr, pc - BX R0 - LDR R0, =vTaskSwitchContext ; Select the next task to execute. - mov lr, pc - BX R0 - - LDR R14, =AT91C_BASE_PITC ; Clear the PIT interrupt - LDR R0, [R14, #PITC_PIVR ] - - LDR R14, =AT91C_BASE_AIC ; Mark the End of Interrupt on the AIC - STR R14, [R14, #AIC_EOICR] - - portRESTORE_CONTEXT ; Restore the context of the selected task. - - - END - diff --git a/Source/portable/IAR/AtmelSAM7S64/portmacro.h b/Source/portable/IAR/AtmelSAM7S64/portmacro.h deleted file mode 100644 index fc088cd52..000000000 --- a/Source/portable/IAR/AtmelSAM7S64/portmacro.h +++ /dev/null @@ -1,109 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -#include - -/*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the - * given hardware and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - -/* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE unsigned portLONG -#define portBASE_TYPE portLONG - -#if( configUSE_16_BIT_TICKS == 1 ) - typedef unsigned portSHORT portTickType; - #define portMAX_DELAY ( portTickType ) 0xffff -#else - typedef unsigned portLONG portTickType; - #define portMAX_DELAY ( portTickType ) 0xffffffff -#endif -/*-----------------------------------------------------------*/ - -/* Hardware specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 4 -#define portYIELD() asm ( "SWI 0" ) -#define portNOP() asm ( "NOP" ) -/*-----------------------------------------------------------*/ - -/* Critical section handling. */ -__arm __interwork void vPortDisableInterruptsFromThumb( void ); -__arm __interwork void vPortEnableInterruptsFromThumb( void ); -__arm __interwork void vPortEnterCritical( void ); -__arm __interwork void vPortExitCritical( void ); - -#define portDISABLE_INTERRUPTS() __disable_interrupt() -#define portENABLE_INTERRUPTS() __enable_interrupt() -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() -/*-----------------------------------------------------------*/ - -/* Task utilities. */ -#define portEND_SWITCHING_ISR( xSwitchRequired ) \ -{ \ -extern void vTaskSwitchContext( void ); \ - \ - if( xSwitchRequired ) \ - { \ - vTaskSwitchContext(); \ - } \ -} -/*-----------------------------------------------------------*/ - -/* Compiler specifics. */ -#define inline -/*-----------------------------------------------------------*/ - -/* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) - -#endif /* PORTMACRO_H */ - - diff --git a/Source/portable/IAR/LPC2000/ISR_Support.h b/Source/portable/IAR/LPC2000/ISR_Support.h deleted file mode 100644 index 4a32f3976..000000000 --- a/Source/portable/IAR/LPC2000/ISR_Support.h +++ /dev/null @@ -1,78 +0,0 @@ - EXTERN pxCurrentTCB - EXTERN ulCriticalNesting - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Context save and restore macro definitions -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - -portSAVE_CONTEXT MACRO - - ; Push R0 as we are going to use the register. - STMDB SP!, {R0} - - ; Set R0 to point to the task stack pointer. - STMDB SP, {SP}^ - NOP - SUB SP, SP, #4 - LDMIA SP!, {R0} - - ; Push the return address onto the stack. - STMDB R0!, {LR} - - ; Now we have saved LR we can use it instead of R0. - MOV LR, R0 - - ; Pop R0 so we can save it onto the system mode stack. - LDMIA SP!, {R0} - - ; Push all the system mode registers onto the task stack. - STMDB LR, {R0-LR}^ - NOP - SUB LR, LR, #60 - - ; Push the SPSR onto the task stack. - MRS R0, SPSR - STMDB LR!, {R0} - - LDR R0, =ulCriticalNesting - LDR R0, [R0] - STMDB LR!, {R0} - - ; Store the new top of stack for the task. - LDR R1, =pxCurrentTCB - LDR R0, [R1] - STR LR, [R0] - - ENDM - - -portRESTORE_CONTEXT MACRO - - ; Set the LR to the task stack. - LDR R1, =pxCurrentTCB - LDR R0, [R1] - LDR LR, [R0] - - ; The critical nesting depth is the first item on the stack. - ; Load it into the ulCriticalNesting variable. - LDR R0, =ulCriticalNesting - LDMFD LR!, {R1} - STR R1, [R0] - - ; Get the SPSR from the stack. - LDMFD LR!, {R0} - MSR SPSR_cxsf, R0 - - ; Restore all system mode registers for the task. - LDMFD LR, {R0-R14}^ - NOP - - ; Restore the return address. - LDR LR, [LR, #+60] - - ; And return - correcting the offset in the LR to obtain the - ; correct address. - SUBS PC, LR, #4 - - ENDM - diff --git a/Source/portable/IAR/LPC2000/port.c b/Source/portable/IAR/LPC2000/port.c deleted file mode 100644 index de3391be0..000000000 --- a/Source/portable/IAR/LPC2000/port.c +++ /dev/null @@ -1,313 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the Philips ARM7 port. - *----------------------------------------------------------*/ - -/* - Changes from V3.2.2 - - + Bug fix - The prescale value for the timer setup is now written to T0PR - instead of T0PC. This bug would have had no effect unless a prescale - value was actually used. -*/ - -/* Standard includes. */ -#include -#include - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Constants required to setup the tick ISR. */ -#define portENABLE_TIMER ( ( unsigned portCHAR ) 0x01 ) -#define portPRESCALE_VALUE 0x00 -#define portINTERRUPT_ON_MATCH ( ( unsigned portLONG ) 0x01 ) -#define portRESET_COUNT_ON_MATCH ( ( unsigned portLONG ) 0x02 ) - -/* Constants required to setup the initial stack. */ -#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */ -#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 ) - -/* Constants required to setup the PIT. */ -#define portPIT_CLOCK_DIVISOR ( ( unsigned portLONG ) 16 ) -#define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_RATE_MS ) - -/* Constants required to handle interrupts. */ -#define portTIMER_MATCH_ISR_BIT ( ( unsigned portCHAR ) 0x01 ) -#define portCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 ) - -/* Constants required to handle critical sections. */ -#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 ) - - -#define portINT_LEVEL_SENSITIVE 0 -#define portPIT_ENABLE ( ( unsigned portSHORT ) 0x1 << 24 ) -#define portPIT_INT_ENABLE ( ( unsigned portSHORT ) 0x1 << 25 ) - -/* Constants required to setup the VIC for the tick ISR. */ -#define portTIMER_VIC_CHANNEL ( ( unsigned portLONG ) 0x0004 ) -#define portTIMER_VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x0010 ) -#define portTIMER_VIC_ENABLE ( ( unsigned portLONG ) 0x0020 ) - -/*-----------------------------------------------------------*/ - -/* Setup the PIT to generate the tick interrupts. */ -static void prvSetupTimerInterrupt( void ); - -/* ulCriticalNesting will get set to zero when the first task starts. It -cannot be initialised to 0 as this will cause interrupts to be enabled -during the kernel initialisation process. */ -unsigned portLONG ulCriticalNesting = ( unsigned portLONG ) 9999; - -/*-----------------------------------------------------------*/ - -/* - * Initialise the stack of a task to look exactly as if a call to - * portSAVE_CONTEXT had been called. - * - * See header file for description. - */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) -{ -portSTACK_TYPE *pxOriginalTOS; - - pxOriginalTOS = pxTopOfStack; - - /* Setup the initial stack of the task. The stack is set exactly as - expected by the portRESTORE_CONTEXT() macro. */ - - /* First on the stack is the return address - which in this case is the - start of the task. The offset is added to make the return address appear - as it would within an IRQ ISR. */ - *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; - pxTopOfStack--; - - *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */ - pxTopOfStack--; - - /* When the task starts is will expect to find the function parameter in - R0. */ - *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ - pxTopOfStack--; - - /* The status register is set for system mode, with interrupts enabled. */ - *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR; - pxTopOfStack--; - - /* Interrupt flags cannot always be stored on the stack and will - instead be stored in a variable, which is then saved as part of the - tasks context. */ - *pxTopOfStack = portNO_CRITICAL_NESTING; - - return pxTopOfStack; -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xPortStartScheduler( void ) -{ -extern void vPortStartFirstTask( void ); - - /* Start the timer that generates the tick ISR. Interrupts are disabled - here already. */ - prvSetupTimerInterrupt(); - - /* Start the first task. */ - vPortStartFirstTask(); - - /* Should not get here! */ - return 0; -} -/*-----------------------------------------------------------*/ - -void vPortEndScheduler( void ) -{ - /* It is unlikely that the ARM port will require this function as there - is nothing to return to. */ -} -/*-----------------------------------------------------------*/ - -#if configUSE_PREEMPTION == 0 - - /* The cooperative scheduler requires a normal IRQ service routine to - simply increment the system tick. */ - static __arm __irq void vPortNonPreemptiveTick( void ); - static __arm __irq void vPortNonPreemptiveTick( void ) - { - /* Increment the tick count - which may wake some tasks but as the - preemptive scheduler is not being used any woken task is not given - processor time no matter what its priority. */ - vTaskIncrementTick(); - - /* Ready for the next interrupt. */ - T0IR = portTIMER_MATCH_ISR_BIT; - VICVectAddr = portCLEAR_VIC_INTERRUPT; - } - -#else - - /* This function is called from an asm wrapper, so does not require the __irq - keyword. */ - void vPortPreemptiveTick( void ); - void vPortPreemptiveTick( void ) - { - /* Increment the tick counter. */ - vTaskIncrementTick(); - - /* The new tick value might unblock a task. Ensure the highest task that - is ready to execute is the task that will execute when the tick ISR - exits. */ - vTaskSwitchContext(); - - /* Ready for the next interrupt. */ - T0IR = portTIMER_MATCH_ISR_BIT; - VICVectAddr = portCLEAR_VIC_INTERRUPT; - } - -#endif - -/*-----------------------------------------------------------*/ - -static void prvSetupTimerInterrupt( void ) -{ -unsigned portLONG ulCompareMatch; - - /* A 1ms tick does not require the use of the timer prescale. This is - defaulted to zero but can be used if necessary. */ - T0PR = portPRESCALE_VALUE; - - /* Calculate the match value required for our wanted tick rate. */ - ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ; - - /* Protect against divide by zero. Using an if() statement still results - in a warning - hence the #if. */ - #if portPRESCALE_VALUE != 0 - { - ulCompareMatch /= ( portPRESCALE_VALUE + 1 ); - } - #endif - - T0MR0 = ulCompareMatch; - - /* Generate tick with timer 0 compare match. */ - T0MCR = portRESET_COUNT_ON_MATCH | portINTERRUPT_ON_MATCH; - - /* Setup the VIC for the timer. */ - VICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT ); - VICIntEnable |= portTIMER_VIC_CHANNEL_BIT; - - /* The ISR installed depends on whether the preemptive or cooperative - scheduler is being used. */ - #if configUSE_PREEMPTION == 1 - { - extern void ( vPortPreemptiveTickEntry )( void ); - - VICVectAddr0 = ( unsigned portLONG ) vPortPreemptiveTickEntry; - } - #else - { - extern void ( vNonPreemptiveTick )( void ); - - VICVectAddr0 = ( portLONG ) vPortNonPreemptiveTick; - } - #endif - - VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE; - - /* Start the timer - interrupts are disabled when this function is called - so it is okay to do this here. */ - T0TCR = portENABLE_TIMER; -} -/*-----------------------------------------------------------*/ - -void vPortEnterCritical( void ) -{ - /* Disable interrupts first! */ - __disable_interrupt(); - - /* Now interrupts are disabled ulCriticalNesting can be accessed - directly. Increment ulCriticalNesting to keep a count of how many times - portENTER_CRITICAL() has been called. */ - ulCriticalNesting++; -} -/*-----------------------------------------------------------*/ - -void vPortExitCritical( void ) -{ - if( ulCriticalNesting > portNO_CRITICAL_NESTING ) - { - /* Decrement the nesting count as we are leaving a critical section. */ - ulCriticalNesting--; - - /* If the nesting level has reached zero then interrupts should be - re-enabled. */ - if( ulCriticalNesting == portNO_CRITICAL_NESTING ) - { - __enable_interrupt(); - } - } -} -/*-----------------------------------------------------------*/ - - - - - - diff --git a/Source/portable/IAR/LPC2000/portasm.s79 b/Source/portable/IAR/LPC2000/portasm.s79 deleted file mode 100644 index d679660f2..000000000 --- a/Source/portable/IAR/LPC2000/portasm.s79 +++ /dev/null @@ -1,50 +0,0 @@ - RSEG ICODE:CODE - CODE32 - - EXTERN vTaskSwitchContext - EXTERN vTaskIncrementTick - EXTERN vPortPreemptiveTick - - PUBLIC vPortPreemptiveTickEntry - PUBLIC vPortYieldProcessor - PUBLIC vPortStartFirstTask - -#include "FreeRTOSConfig.h" -#include "ISR_Support.h" - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Starting the first task is just a matter of restoring the context that -; was created by pxPortInitialiseStack(). -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -vPortStartFirstTask: - portRESTORE_CONTEXT - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Manual context switch function. This is the SWI hander. -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -vPortYieldProcessor: - ADD LR, LR, #4 ; Add 4 to the LR to make the LR appear exactly - ; as if the context was saved during and IRQ - ; handler. - - portSAVE_CONTEXT ; Save the context of the current task... - LDR R0, =vTaskSwitchContext ; before selecting the next task to execute. - mov lr, pc - BX R0 - portRESTORE_CONTEXT ; Restore the context of the selected task. - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Preemptive context switch function. This will only ever get installed if -; portUSE_PREEMPTION is set to 1 in portmacro.h. -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -vPortPreemptiveTickEntry: -#if configUSE_PREEMPTION == 1 - portSAVE_CONTEXT ; Save the context of the current task... - LDR R0, =vPortPreemptiveTick; before selecting the next task to execute. - mov lr, pc - BX R0 - portRESTORE_CONTEXT ; Restore the context of the selected task. -#endif - - END - diff --git a/Source/portable/IAR/LPC2000/portmacro.h b/Source/portable/IAR/LPC2000/portmacro.h deleted file mode 100644 index fc088cd52..000000000 --- a/Source/portable/IAR/LPC2000/portmacro.h +++ /dev/null @@ -1,109 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -#include - -/*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the - * given hardware and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - -/* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE unsigned portLONG -#define portBASE_TYPE portLONG - -#if( configUSE_16_BIT_TICKS == 1 ) - typedef unsigned portSHORT portTickType; - #define portMAX_DELAY ( portTickType ) 0xffff -#else - typedef unsigned portLONG portTickType; - #define portMAX_DELAY ( portTickType ) 0xffffffff -#endif -/*-----------------------------------------------------------*/ - -/* Hardware specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 4 -#define portYIELD() asm ( "SWI 0" ) -#define portNOP() asm ( "NOP" ) -/*-----------------------------------------------------------*/ - -/* Critical section handling. */ -__arm __interwork void vPortDisableInterruptsFromThumb( void ); -__arm __interwork void vPortEnableInterruptsFromThumb( void ); -__arm __interwork void vPortEnterCritical( void ); -__arm __interwork void vPortExitCritical( void ); - -#define portDISABLE_INTERRUPTS() __disable_interrupt() -#define portENABLE_INTERRUPTS() __enable_interrupt() -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() -/*-----------------------------------------------------------*/ - -/* Task utilities. */ -#define portEND_SWITCHING_ISR( xSwitchRequired ) \ -{ \ -extern void vTaskSwitchContext( void ); \ - \ - if( xSwitchRequired ) \ - { \ - vTaskSwitchContext(); \ - } \ -} -/*-----------------------------------------------------------*/ - -/* Compiler specifics. */ -#define inline -/*-----------------------------------------------------------*/ - -/* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) - -#endif /* PORTMACRO_H */ - - diff --git a/Source/portable/IAR/STR71x/ISR_Support.h b/Source/portable/IAR/STR71x/ISR_Support.h deleted file mode 100644 index 4a32f3976..000000000 --- a/Source/portable/IAR/STR71x/ISR_Support.h +++ /dev/null @@ -1,78 +0,0 @@ - EXTERN pxCurrentTCB - EXTERN ulCriticalNesting - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Context save and restore macro definitions -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - -portSAVE_CONTEXT MACRO - - ; Push R0 as we are going to use the register. - STMDB SP!, {R0} - - ; Set R0 to point to the task stack pointer. - STMDB SP, {SP}^ - NOP - SUB SP, SP, #4 - LDMIA SP!, {R0} - - ; Push the return address onto the stack. - STMDB R0!, {LR} - - ; Now we have saved LR we can use it instead of R0. - MOV LR, R0 - - ; Pop R0 so we can save it onto the system mode stack. - LDMIA SP!, {R0} - - ; Push all the system mode registers onto the task stack. - STMDB LR, {R0-LR}^ - NOP - SUB LR, LR, #60 - - ; Push the SPSR onto the task stack. - MRS R0, SPSR - STMDB LR!, {R0} - - LDR R0, =ulCriticalNesting - LDR R0, [R0] - STMDB LR!, {R0} - - ; Store the new top of stack for the task. - LDR R1, =pxCurrentTCB - LDR R0, [R1] - STR LR, [R0] - - ENDM - - -portRESTORE_CONTEXT MACRO - - ; Set the LR to the task stack. - LDR R1, =pxCurrentTCB - LDR R0, [R1] - LDR LR, [R0] - - ; The critical nesting depth is the first item on the stack. - ; Load it into the ulCriticalNesting variable. - LDR R0, =ulCriticalNesting - LDMFD LR!, {R1} - STR R1, [R0] - - ; Get the SPSR from the stack. - LDMFD LR!, {R0} - MSR SPSR_cxsf, R0 - - ; Restore all system mode registers for the task. - LDMFD LR, {R0-R14}^ - NOP - - ; Restore the return address. - LDR LR, [LR, #+60] - - ; And return - correcting the offset in the LR to obtain the - ; correct address. - SUBS PC, LR, #4 - - ENDM - diff --git a/Source/portable/IAR/STR71x/port.c b/Source/portable/IAR/STR71x/port.c deleted file mode 100644 index a2bdea58a..000000000 --- a/Source/portable/IAR/STR71x/port.c +++ /dev/null @@ -1,252 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the ST STR71x ARM7 - * port. - *----------------------------------------------------------*/ - -/* Library includes. */ -#include "wdg.h" -#include "eic.h" - -/* Standard includes. */ -#include - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Constants required to setup the initial stack. */ -#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */ -#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 ) - -/* Constants required to handle critical sections. */ -#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 ) - -#define portMICROS_PER_SECOND 1000000 - -/*-----------------------------------------------------------*/ - -/* Setup the watchdog to generate the tick interrupts. */ -static void prvSetupTimerInterrupt( void ); - -/* ulCriticalNesting will get set to zero when the first task starts. It -cannot be initialised to 0 as this will cause interrupts to be enabled -during the kernel initialisation process. */ -unsigned portLONG ulCriticalNesting = ( unsigned portLONG ) 9999; - -/* Tick interrupt routines for cooperative and preemptive operation -respectively. The preemptive version is not defined as __irq as it is called -from an asm wrapper function. */ -__arm __irq void vPortNonPreemptiveTick( void ); -void vPortPreemptiveTick( void ); - -/*-----------------------------------------------------------*/ - -/* - * Initialise the stack of a task to look exactly as if a call to - * portSAVE_CONTEXT had been called. - * - * See header file for description. - */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) -{ -portSTACK_TYPE *pxOriginalTOS; - - pxOriginalTOS = pxTopOfStack; - - /* Setup the initial stack of the task. The stack is set exactly as - expected by the portRESTORE_CONTEXT() macro. */ - - /* First on the stack is the return address - which in this case is the - start of the task. The offset is added to make the return address appear - as it would within an IRQ ISR. */ - *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; - pxTopOfStack--; - - *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */ - pxTopOfStack--; - - /* When the task starts is will expect to find the function parameter in - R0. */ - *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ - pxTopOfStack--; - - /* The status register is set for system mode, with interrupts enabled. */ - *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR; - pxTopOfStack--; - - /* Interrupt flags cannot always be stored on the stack and will - instead be stored in a variable, which is then saved as part of the - tasks context. */ - *pxTopOfStack = portNO_CRITICAL_NESTING; - - return pxTopOfStack; -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xPortStartScheduler( void ) -{ -extern void vPortStartFirstTask( void ); - - /* Start the timer that generates the tick ISR. Interrupts are disabled - here already. */ - prvSetupTimerInterrupt(); - - /* Start the first task. */ - vPortStartFirstTask(); - - /* Should not get here! */ - return 0; -} -/*-----------------------------------------------------------*/ - -void vPortEndScheduler( void ) -{ - /* It is unlikely that the ARM port will require this function as there - is nothing to return to. */ -} -/*-----------------------------------------------------------*/ - -/* The cooperative scheduler requires a normal IRQ service routine to -simply increment the system tick. */ -__arm __irq void vPortNonPreemptiveTick( void ) -{ - /* Increment the tick count - which may wake some tasks but as the - preemptive scheduler is not being used any woken task is not given - processor time no matter what its priority. */ - vTaskIncrementTick(); - - /* Clear the interrupt in the watchdog and EIC. */ - WDG->SR = 0x0000; - portCLEAR_EIC(); -} -/*-----------------------------------------------------------*/ - -/* This function is called from an asm wrapper, so does not require the __irq -keyword. */ -void vPortPreemptiveTick( void ) -{ - /* Increment the tick counter. */ - vTaskIncrementTick(); - - /* The new tick value might unblock a task. Ensure the highest task that - is ready to execute is the task that will execute when the tick ISR - exits. */ - vTaskSwitchContext(); - - /* Clear the interrupt in the watchdog and EIC. */ - WDG->SR = 0x0000; - portCLEAR_EIC(); -} -/*-----------------------------------------------------------*/ - -static void prvSetupTimerInterrupt( void ) -{ - /* Set the watchdog up to generate a periodic tick. */ - WDG_ECITConfig( DISABLE ); - WDG_CntOnOffConfig( DISABLE ); - WDG_PeriodValueConfig( portMICROS_PER_SECOND / configTICK_RATE_HZ ); - - /* Setup the tick interrupt in the EIC. */ - EIC_IRQChannelPriorityConfig( WDG_IRQChannel, 1 ); - EIC_IRQChannelConfig( WDG_IRQChannel, ENABLE ); - EIC_IRQConfig( ENABLE ); - WDG_ECITConfig( ENABLE ); - - /* Start the timer - interrupts are actually disabled at this point so - it is safe to do this here. */ - WDG_CntOnOffConfig( ENABLE ); -} -/*-----------------------------------------------------------*/ - -__arm __interwork void vPortEnterCritical( void ) -{ - /* Disable interrupts first! */ - __disable_interrupt(); - - /* Now interrupts are disabled ulCriticalNesting can be accessed - directly. Increment ulCriticalNesting to keep a count of how many times - portENTER_CRITICAL() has been called. */ - ulCriticalNesting++; -} -/*-----------------------------------------------------------*/ - -__arm __interwork void vPortExitCritical( void ) -{ - if( ulCriticalNesting > portNO_CRITICAL_NESTING ) - { - /* Decrement the nesting count as we are leaving a critical section. */ - ulCriticalNesting--; - - /* If the nesting level has reached zero then interrupts should be - re-enabled. */ - if( ulCriticalNesting == portNO_CRITICAL_NESTING ) - { - __enable_interrupt(); - } - } -} -/*-----------------------------------------------------------*/ - - - - - - diff --git a/Source/portable/IAR/STR71x/portasm.s79 b/Source/portable/IAR/STR71x/portasm.s79 deleted file mode 100644 index d9f0fc347..000000000 --- a/Source/portable/IAR/STR71x/portasm.s79 +++ /dev/null @@ -1,49 +0,0 @@ - RSEG ICODE:CODE - CODE32 - - EXTERN vPortPreemptiveTick - EXTERN vTaskSwitchContext - - PUBLIC vPortYieldProcessor - PUBLIC vPortStartFirstTask - PUBLIC vPortPreemptiveTickISR - -#include "ISR_Support.h" - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Starting the first task is just a matter of restoring the context that -; was created by pxPortInitialiseStack(). -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -vPortStartFirstTask: - portRESTORE_CONTEXT - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Manual context switch function. This is the SWI hander. -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -vPortYieldProcessor: - ADD LR, LR, #4 ; Add 4 to the LR to make the LR appear exactly - ; as if the context was saved during and IRQ - ; handler. - - portSAVE_CONTEXT ; Save the context of the current task... - LDR R0, =vTaskSwitchContext ; before selecting the next task to execute. - mov lr, pc - BX R0 - portRESTORE_CONTEXT ; Restore the context of the selected task. - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Preemptive context switch function. This will only ever get used if -; portUSE_PREEMPTION is set to 1 in portmacro.h. -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -vPortPreemptiveTickISR: - portSAVE_CONTEXT ; Save the context of the current task. - - LDR R0, =vPortPreemptiveTick ; Increment the tick count - this may wake a task. - MOV lr, pc - BX R0 - - portRESTORE_CONTEXT ; Restore the context of the selected task. - - - END - diff --git a/Source/portable/IAR/STR71x/portmacro.h b/Source/portable/IAR/STR71x/portmacro.h deleted file mode 100644 index 12c50dd63..000000000 --- a/Source/portable/IAR/STR71x/portmacro.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -/*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the - * given hardware and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - -#include - -/* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE unsigned portLONG -#define portBASE_TYPE portLONG - -#if( configUSE_16_BIT_TICKS == 1 ) - typedef unsigned portSHORT portTickType; - #define portMAX_DELAY ( portTickType ) 0xffff -#else - typedef unsigned portLONG portTickType; - #define portMAX_DELAY ( portTickType ) 0xffffffff -#endif -/*-----------------------------------------------------------*/ - -/* Hardware specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 4 -#define portYIELD() asm ( "SWI 0" ) -#define portNOP() asm ( "NOP" ) -/*-----------------------------------------------------------*/ - -/* Critical section handling. */ -__arm __interwork void vPortDisableInterruptsFromThumb( void ); -__arm __interwork void vPortEnableInterruptsFromThumb( void ); -__arm __interwork void vPortEnterCritical( void ); -__arm __interwork void vPortExitCritical( void ); - -#define portDISABLE_INTERRUPTS() __disable_interrupt() -#define portENABLE_INTERRUPTS() __enable_interrupt() -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() -/*-----------------------------------------------------------*/ - -/* Task utilities. */ -#define portEND_SWITCHING_ISR( xSwitchRequired ) \ -{ \ -extern void vTaskSwitchContext( void ); \ - \ - if( xSwitchRequired ) \ - { \ - vTaskSwitchContext(); \ - } \ -} -/*-----------------------------------------------------------*/ - -/* EIC utilities. */ -#define portEIC_CICR_ADDR *( ( unsigned portLONG * ) 0xFFFFF804 ) -#define portEIC_IPR_ADDR *( ( unsigned portLONG * ) 0xFFFFF840 ) -#define portCLEAR_EIC() portEIC_IPR_ADDR = 0x01 << portEIC_CICR_ADDR - -/*-----------------------------------------------------------*/ - -/* Compiler specifics */ -#define inline - -/* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) - -#endif /* PORTMACRO_H */ - - diff --git a/Source/portable/IAR/STR75x/ISR_Support.h b/Source/portable/IAR/STR75x/ISR_Support.h deleted file mode 100644 index fa69ad0aa..000000000 --- a/Source/portable/IAR/STR75x/ISR_Support.h +++ /dev/null @@ -1,108 +0,0 @@ -; FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. -; -; This file is part of the FreeRTOS.org distribution. -; -; FreeRTOS.org is free software; you can redistribute it and/or modify -; it under the terms of the GNU General Public License as published by -; the Free Software Foundation; either version 2 of the License, or -; (at your option) any later version. -; -; FreeRTOS.org is distributed in the hope that it will be useful, -; but WITHOUT ANY WARRANTY; without even the implied warranty of -; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; GNU General Public License for more details. -; -; You should have received a copy of the GNU General Public License -; along with FreeRTOS.org; if not, write to the Free Software -; Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -; -; A special exception to the GPL can be applied should you wish to distribute -; a combined work that includes FreeRTOS.org, without being obliged to provide -; the source code for any proprietary components. See the licensing section -; of http://www.FreeRTOS.org for full details of how and when the exception -; can be applied. -; -; *************************************************************************** -; See http://www.FreeRTOS.org for documentation, latest information, license -; and contact details. Please ensure to read the configuration and relevant -; port sections of the online documentation. -; *************************************************************************** - - EXTERN pxCurrentTCB - EXTERN ulCriticalNesting - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Context save and restore macro definitions -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - -portSAVE_CONTEXT MACRO - - ; Push R0 as we are going to use the register. - STMDB SP!, {R0} - - ; Set R0 to point to the task stack pointer. - STMDB SP, {SP}^ - NOP - SUB SP, SP, #4 - LDMIA SP!, {R0} - - ; Push the return address onto the stack. - STMDB R0!, {LR} - - ; Now we have saved LR we can use it instead of R0. - MOV LR, R0 - - ; Pop R0 so we can save it onto the system mode stack. - LDMIA SP!, {R0} - - ; Push all the system mode registers onto the task stack. - STMDB LR, {R0-LR}^ - NOP - SUB LR, LR, #60 - - ; Push the SPSR onto the task stack. - MRS R0, SPSR - STMDB LR!, {R0} - - LDR R0, =ulCriticalNesting - LDR R0, [R0] - STMDB LR!, {R0} - - ; Store the new top of stack for the task. - LDR R1, =pxCurrentTCB - LDR R0, [R1] - STR LR, [R0] - - ENDM - - -portRESTORE_CONTEXT MACRO - - ; Set the LR to the task stack. - LDR R1, =pxCurrentTCB - LDR R0, [R1] - LDR LR, [R0] - - ; The critical nesting depth is the first item on the stack. - ; Load it into the ulCriticalNesting variable. - LDR R0, =ulCriticalNesting - LDMFD LR!, {R1} - STR R1, [R0] - - ; Get the SPSR from the stack. - LDMFD LR!, {R0} - MSR SPSR_cxsf, R0 - - ; Restore all system mode registers for the task. - LDMFD LR, {R0-R14}^ - NOP - - ; Restore the return address. - LDR LR, [LR, #+60] - - ; And return - correcting the offset in the LR to obtain the - ; correct address. - SUBS PC, LR, #4 - - ENDM - diff --git a/Source/portable/IAR/STR75x/port.c b/Source/portable/IAR/STR75x/port.c deleted file mode 100644 index 2df22a70d..000000000 --- a/Source/portable/IAR/STR75x/port.c +++ /dev/null @@ -1,241 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the ST STR75x ARM7 - * port. - *----------------------------------------------------------*/ - -/* Library includes. */ -#include "75x_tb.h" -#include "75x_eic.h" - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Constants required to setup the initial stack. */ -#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */ -#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 ) - -/* Constants required to handle critical sections. */ -#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 ) - -/* Prescale used on the timer clock when calculating the tick period. */ -#define portPRESCALE 20 - - -/*-----------------------------------------------------------*/ - -/* Setup the TB to generate the tick interrupts. */ -static void prvSetupTimerInterrupt( void ); - -/* ulCriticalNesting will get set to zero when the first task starts. It -cannot be initialised to 0 as this will cause interrupts to be enabled -during the kernel initialisation process. */ -unsigned portLONG ulCriticalNesting = ( unsigned portLONG ) 9999; - -/* Tick interrupt routines for preemptive operation. */ -__arm void vPortPreemptiveTick( void ); - -/*-----------------------------------------------------------*/ - -/* - * Initialise the stack of a task to look exactly as if a call to - * portSAVE_CONTEXT had been called. - * - * See header file for description. - */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) -{ -portSTACK_TYPE *pxOriginalTOS; - - pxOriginalTOS = pxTopOfStack; - - /* Setup the initial stack of the task. The stack is set exactly as - expected by the portRESTORE_CONTEXT() macro. */ - - /* First on the stack is the return address - which in this case is the - start of the task. The offset is added to make the return address appear - as it would within an IRQ ISR. */ - *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; - pxTopOfStack--; - - *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */ - pxTopOfStack--; - - /* When the task starts is will expect to find the function parameter in - R0. */ - *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ - pxTopOfStack--; - - /* The status register is set for system mode, with interrupts enabled. */ - *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR; - pxTopOfStack--; - - /* Interrupt flags cannot always be stored on the stack and will - instead be stored in a variable, which is then saved as part of the - tasks context. */ - *pxTopOfStack = portNO_CRITICAL_NESTING; - - return pxTopOfStack; -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xPortStartScheduler( void ) -{ -extern void vPortStartFirstTask( void ); - - /* Start the timer that generates the tick ISR. Interrupts are disabled - here already. */ - prvSetupTimerInterrupt(); - - /* Start the first task. */ - vPortStartFirstTask(); - - /* Should not get here! */ - return 0; -} -/*-----------------------------------------------------------*/ - -void vPortEndScheduler( void ) -{ - /* It is unlikely that the ARM port will require this function as there - is nothing to return to. */ -} -/*-----------------------------------------------------------*/ - -__arm void vPortPreemptiveTick( void ) -{ - /* Increment the tick counter. */ - vTaskIncrementTick(); - - /* The new tick value might unblock a task. Ensure the highest task that - is ready to execute is the task that will execute when the tick ISR - exits. */ - #if configUSE_PREEMPTION == 1 - vTaskSwitchContext(); - #endif - - TB_ClearITPendingBit( TB_IT_Update ); -} -/*-----------------------------------------------------------*/ - -static void prvSetupTimerInterrupt( void ) -{ -EIC_IRQInitTypeDef EIC_IRQInitStructure; -TB_InitTypeDef TB_InitStructure; - - /* Setup the EIC for the TB. */ - EIC_IRQInitStructure.EIC_IRQChannelCmd = ENABLE; - EIC_IRQInitStructure.EIC_IRQChannel = TB_IRQChannel; - EIC_IRQInitStructure.EIC_IRQChannelPriority = 1; - EIC_IRQInit(&EIC_IRQInitStructure); - - /* Setup the TB for the generation of the tick interrupt. */ - TB_InitStructure.TB_Mode = TB_Mode_Timing; - TB_InitStructure.TB_CounterMode = TB_CounterMode_Down; - TB_InitStructure.TB_Prescaler = portPRESCALE; - TB_InitStructure.TB_AutoReload = ( ( configCPU_CLOCK_HZ / ( portPRESCALE + 1 ) ) / configTICK_RATE_HZ ) + 1; - TB_Init(&TB_InitStructure); - - /* Enable TB Update interrupt */ - TB_ITConfig(TB_IT_Update, ENABLE); - - /* Clear TB Update interrupt pending bit */ - TB_ClearITPendingBit(TB_IT_Update); - - /* Enable TB */ - TB_Cmd(ENABLE); -} -/*-----------------------------------------------------------*/ - -__arm __interwork void vPortEnterCritical( void ) -{ - /* Disable interrupts first! */ - __disable_interrupt(); - - /* Now interrupts are disabled ulCriticalNesting can be accessed - directly. Increment ulCriticalNesting to keep a count of how many times - portENTER_CRITICAL() has been called. */ - ulCriticalNesting++; -} -/*-----------------------------------------------------------*/ - -__arm __interwork void vPortExitCritical( void ) -{ - if( ulCriticalNesting > portNO_CRITICAL_NESTING ) - { - /* Decrement the nesting count as we are leaving a critical section. */ - ulCriticalNesting--; - - /* If the nesting level has reached zero then interrupts should be - re-enabled. */ - if( ulCriticalNesting == portNO_CRITICAL_NESTING ) - { - __enable_interrupt(); - } - } -} -/*-----------------------------------------------------------*/ - - - - - - diff --git a/Source/portable/IAR/STR75x/portasm.s79 b/Source/portable/IAR/STR75x/portasm.s79 deleted file mode 100644 index 563bc14a7..000000000 --- a/Source/portable/IAR/STR75x/portasm.s79 +++ /dev/null @@ -1,66 +0,0 @@ -; FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. -; -; This file is part of the FreeRTOS.org distribution. -; -; FreeRTOS.org is free software; you can redistribute it and/or modify -; it under the terms of the GNU General Public License as published by -; the Free Software Foundation; either version 2 of the License, or -; (at your option) any later version. -; -; FreeRTOS.org is distributed in the hope that it will be useful, -; but WITHOUT ANY WARRANTY; without even the implied warranty of -; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; GNU General Public License for more details. -; -; You should have received a copy of the GNU General Public License -; along with FreeRTOS.org; if not, write to the Free Software -; Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -; -; A special exception to the GPL can be applied should you wish to distribute -; a combined work that includes FreeRTOS.org, without being obliged to provide -; the source code for any proprietary components. See the licensing section -; of http://www.FreeRTOS.org for full details of how and when the exception -; can be applied. -; -; *************************************************************************** -; See http://www.FreeRTOS.org for documentation, latest information, license -; and contact details. Please ensure to read the configuration and relevant -; port sections of the online documentation. -; *************************************************************************** - - RSEG ICODE:CODE - CODE32 - - EXTERN vPortPreemptiveTick - EXTERN vTaskSwitchContext - - PUBLIC vPortYieldProcessor - PUBLIC vPortStartFirstTask - -#include "ISR_Support.h" - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Starting the first task is just a matter of restoring the context that -; was created by pxPortInitialiseStack(). -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -vPortStartFirstTask: - portRESTORE_CONTEXT - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Manual context switch function. This is the SWI hander. -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -vPortYieldProcessor: - ADD LR, LR, #4 ; Add 4 to the LR to make the LR appear exactly - ; as if the context was saved during and IRQ - ; handler. - - portSAVE_CONTEXT ; Save the context of the current task... - LDR R0, =vTaskSwitchContext ; before selecting the next task to execute. - mov lr, pc - BX R0 - portRESTORE_CONTEXT ; Restore the context of the selected task. - - - - END - diff --git a/Source/portable/IAR/STR75x/portmacro.h b/Source/portable/IAR/STR75x/portmacro.h deleted file mode 100644 index 2a4adb361..000000000 --- a/Source/portable/IAR/STR75x/portmacro.h +++ /dev/null @@ -1,106 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -/*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the - * given hardware and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - -#include - -/* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE unsigned portLONG -#define portBASE_TYPE portLONG - -#if( configUSE_16_BIT_TICKS == 1 ) - typedef unsigned portSHORT portTickType; - #define portMAX_DELAY ( portTickType ) 0xffff -#else - typedef unsigned portLONG portTickType; - #define portMAX_DELAY ( portTickType ) 0xffffffff -#endif -/*-----------------------------------------------------------*/ - -/* Hardware specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 4 -#define portYIELD() asm ( "SWI 0" ) -#define portNOP() asm ( "NOP" ) -/*-----------------------------------------------------------*/ - -/* Critical section handling. */ -__arm __interwork void vPortEnterCritical( void ); -__arm __interwork void vPortExitCritical( void ); - -#define portDISABLE_INTERRUPTS() __disable_interrupt() -#define portENABLE_INTERRUPTS() __enable_interrupt() -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() -/*-----------------------------------------------------------*/ - -/* Task utilities. */ -#define portEND_SWITCHING_ISR( xSwitchRequired ) \ -{ \ -extern void vTaskSwitchContext( void ); \ - \ - if( xSwitchRequired ) \ - { \ - vTaskSwitchContext(); \ - } \ -} -/*-----------------------------------------------------------*/ - -/* Compiler specifics */ -#define inline - -/* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) - -#endif /* PORTMACRO_H */ - - diff --git a/Source/portable/IAR/STR91x/ISR_Support.h b/Source/portable/IAR/STR91x/ISR_Support.h deleted file mode 100644 index ba62c7aed..000000000 --- a/Source/portable/IAR/STR91x/ISR_Support.h +++ /dev/null @@ -1,110 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - EXTERN pxCurrentTCB - EXTERN ulCriticalNesting - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Context save and restore macro definitions -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - -portSAVE_CONTEXT MACRO - - ; Push R0 as we are going to use the register. - STMDB SP!, {R0} - - ; Set R0 to point to the task stack pointer. - STMDB SP, {SP}^ - NOP - SUB SP, SP, #4 - LDMIA SP!, {R0} - - ; Push the return address onto the stack. - STMDB R0!, {LR} - - ; Now we have saved LR we can use it instead of R0. - MOV LR, R0 - - ; Pop R0 so we can save it onto the system mode stack. - LDMIA SP!, {R0} - - ; Push all the system mode registers onto the task stack. - STMDB LR, {R0-LR}^ - NOP - SUB LR, LR, #60 - - ; Push the SPSR onto the task stack. - MRS R0, SPSR - STMDB LR!, {R0} - - LDR R0, =ulCriticalNesting - LDR R0, [R0] - STMDB LR!, {R0} - - ; Store the new top of stack for the task. - LDR R1, =pxCurrentTCB - LDR R0, [R1] - STR LR, [R0] - - ENDM - - -portRESTORE_CONTEXT MACRO - - ; Set the LR to the task stack. - LDR R1, =pxCurrentTCB - LDR R0, [R1] - LDR LR, [R0] - - ; The critical nesting depth is the first item on the stack. - ; Load it into the ulCriticalNesting variable. - LDR R0, =ulCriticalNesting - LDMFD LR!, {R1} - STR R1, [R0] - - ; Get the SPSR from the stack. - LDMFD LR!, {R0} - MSR SPSR_cxsf, R0 - - ; Restore all system mode registers for the task. - LDMFD LR, {R0-R14}^ - NOP - - ; Restore the return address. - LDR LR, [LR, #+60] - - ; And return - correcting the offset in the LR to obtain the - ; correct address. - SUBS PC, LR, #4 - - ENDM - diff --git a/Source/portable/IAR/STR91x/port.c b/Source/portable/IAR/STR91x/port.c deleted file mode 100644 index c827c04a5..000000000 --- a/Source/portable/IAR/STR91x/port.c +++ /dev/null @@ -1,297 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the ST STR91x ARM7 - * port. - *----------------------------------------------------------*/ - -/* Library includes. */ -#include "91x_lib.h" - -/* Standard includes. */ -#include - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Constants required to setup the initial stack. */ -#ifndef _RUN_TASK_IN_ARM_MODE_ - #define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */ -#else - #define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ -#endif -#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 ) - -/* Constants required to handle critical sections. */ -#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 ) - - -/*-----------------------------------------------------------*/ - -/* Setup the watchdog to generate the tick interrupts. */ -static void prvSetupTimerInterrupt( void ); - -/* ulCriticalNesting will get set to zero when the first task starts. It -cannot be initialised to 0 as this will cause interrupts to be enabled -during the kernel initialisation process. */ -unsigned portLONG ulCriticalNesting = ( unsigned portLONG ) 9999; - -/* Tick interrupt routines for cooperative and preemptive operation -respectively. The preemptive version is not defined as __irq as it is called -from an asm wrapper function. */ -__arm __irq void vPortNonPreemptiveTick( void ); -void WDG_IRQHandler( void ); - -/* VIC interrupt default handler. */ -static void prvDefaultHandler( void ); - -/*-----------------------------------------------------------*/ - -/* - * Initialise the stack of a task to look exactly as if a call to - * portSAVE_CONTEXT had been called. - * - * See header file for description. - */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) -{ - portSTACK_TYPE *pxOriginalTOS; - - pxOriginalTOS = pxTopOfStack; - - /* Setup the initial stack of the task. The stack is set exactly as - expected by the portRESTORE_CONTEXT() macro. */ - - /* First on the stack is the return address - which in this case is the - start of the task. The offset is added to make the return address appear - as it would within an IRQ ISR. */ - *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; - pxTopOfStack--; - - *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */ - pxTopOfStack--; - - /* When the task starts is will expect to find the function parameter in - R0. */ - *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ - pxTopOfStack--; - - /* The status register is set for system mode, with interrupts enabled. */ - *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR; - pxTopOfStack--; - - /* Interrupt flags cannot always be stored on the stack and will - instead be stored in a variable, which is then saved as part of the - tasks context. */ - *pxTopOfStack = portNO_CRITICAL_NESTING; - - return pxTopOfStack; -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xPortStartScheduler( void ) -{ -extern void vPortStartFirstTask( void ); - - /* Start the timer that generates the tick ISR. Interrupts are disabled - here already. */ - prvSetupTimerInterrupt(); - - /* Start the first task. */ - vPortStartFirstTask(); - - /* Should not get here! */ - return 0; -} -/*-----------------------------------------------------------*/ - -void vPortEndScheduler( void ) -{ - /* It is unlikely that the ARM port will require this function as there - is nothing to return to. */ -} -/*-----------------------------------------------------------*/ - -/* This function is called from an asm wrapper, so does not require the __irq -keyword. */ -void WDG_IRQHandler( void ) -{ - /* Increment the tick counter. */ - vTaskIncrementTick(); - - #if configUSE_PREEMPTION == 1 - /* The new tick value might unblock a task. Ensure the highest task that - is ready to execute is the task that will execute when the tick ISR - exits. */ - vTaskSwitchContext(); - #endif - - /* Clear the interrupt in the watchdog. */ - WDG->SR &= ~0x0001; -} -/*-----------------------------------------------------------*/ - -#ifndef abs - #define abs(x) ((x)>0 ? (x) : -(x)) -#endif - -static void prvFindFactors(u32 n, u16 *a, u32 *b) -{ - /* This function is copied from the ST STR7 library and is - copyright STMicroelectronics. Reproduced with permission. */ - - u32 b0; - u16 a0; - long err, err_min=n; - - *a = a0 = ((n-1)/65536ul) + 1; - *b = b0 = n / *a; - - for (; *a <= 256; (*a)++) - { - *b = n / *a; - err = (long)*a * (long)*b - (long)n; - if (abs(err) > (*a / 2)) - { - (*b)++; - err = (long)*a * (long)*b - (long)n; - } - if (abs(err) < abs(err_min)) - { - err_min = err; - a0 = *a; - b0 = *b; - if (err == 0) break; - } - } - - *a = a0; - *b = b0; -} -/*-----------------------------------------------------------*/ - -static void prvSetupTimerInterrupt( void ) -{ -WDG_InitTypeDef xWdg; -unsigned portSHORT a; -unsigned portLONG n = configCPU_PERIPH_HZ / configTICK_RATE_HZ, b; - - /* Configure the watchdog as a free running timer that generates a - periodic interrupt. */ - - SCU_APBPeriphClockConfig( __WDG, ENABLE ); - WDG_DeInit(); - WDG_StructInit(&xWdg); - prvFindFactors( n, &a, &b ); - xWdg.WDG_Prescaler = a - 1; - xWdg.WDG_Preload = b - 1; - WDG_Init( &xWdg ); - WDG_ITConfig(ENABLE); - - /* Configure the VIC for the WDG interrupt. */ - VIC_Config( WDG_ITLine, VIC_IRQ, 10 ); - VIC_ITCmd( WDG_ITLine, ENABLE ); - - /* Install the default handlers for both VIC's. */ - VIC0->DVAR = ( unsigned portLONG ) prvDefaultHandler; - VIC1->DVAR = ( unsigned portLONG ) prvDefaultHandler; - - WDG_Cmd(ENABLE); -} - -/*-----------------------------------------------------------*/ - -__arm __interwork void vPortEnterCritical( void ) -{ - /* Disable interrupts first! */ - portDISABLE_INTERRUPTS(); - - /* Now interrupts are disabled ulCriticalNesting can be accessed - directly. Increment ulCriticalNesting to keep a count of how many times - portENTER_CRITICAL() has been called. */ - ulCriticalNesting++; -} -/*-----------------------------------------------------------*/ - -__arm __interwork void vPortExitCritical( void ) -{ - if( ulCriticalNesting > portNO_CRITICAL_NESTING ) - { - /* Decrement the nesting count as we are leaving a critical section. */ - ulCriticalNesting--; - - /* If the nesting level has reached zero then interrupts should be - re-enabled. */ - if( ulCriticalNesting == portNO_CRITICAL_NESTING ) - { - portENABLE_INTERRUPTS(); - } - } -} -/*-----------------------------------------------------------*/ - -static void prvDefaultHandler( void ) -{ -} - - - - - diff --git a/Source/portable/IAR/STR91x/portasm.s79 b/Source/portable/IAR/STR91x/portasm.s79 deleted file mode 100644 index 6a244f124..000000000 --- a/Source/portable/IAR/STR91x/portasm.s79 +++ /dev/null @@ -1,65 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - RSEG ICODE:CODE - CODE32 - - EXTERN vTaskSwitchContext - - PUBLIC vPortYieldProcessor - PUBLIC vPortStartFirstTask - -#include "ISR_Support.h" - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Starting the first task is just a matter of restoring the context that -; was created by pxPortInitialiseStack(). -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -vPortStartFirstTask: - portRESTORE_CONTEXT - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Manual context switch function. This is the SWI hander. -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -vPortYieldProcessor: - ADD LR, LR, #4 ; Add 4 to the LR to make the LR appear exactly - ; as if the context was saved during and IRQ - ; handler. - - portSAVE_CONTEXT ; Save the context of the current task... - LDR R0, =vTaskSwitchContext ; before selecting the next task to execute. - MOV lr, pc - BX R0 - portRESTORE_CONTEXT ; Restore the context of the selected task. - - END - diff --git a/Source/portable/IAR/STR91x/portmacro.h b/Source/portable/IAR/STR91x/portmacro.h deleted file mode 100644 index 52f1dbeb5..000000000 --- a/Source/portable/IAR/STR91x/portmacro.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -/*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the - * given hardware and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - -#include - -/* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE unsigned portLONG -#define portBASE_TYPE portLONG - -#if( configUSE_16_BIT_TICKS == 1 ) - typedef unsigned portSHORT portTickType; - #define portMAX_DELAY ( portTickType ) 0xffff -#else - typedef unsigned portLONG portTickType; - #define portMAX_DELAY ( portTickType ) 0xffffffff -#endif -/*-----------------------------------------------------------*/ - -/* Hardware specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 4 -#define portYIELD() asm ( "SWI 0" ) -#define portNOP() asm ( "NOP" ) -/*-----------------------------------------------------------*/ - -/* Critical section handling. */ -__arm __interwork void vPortEnterCritical( void ); -__arm __interwork void vPortExitCritical( void ); -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() - -#define portDISABLE_INTERRUPTS() __disable_interrupt() -#define portENABLE_INTERRUPTS() __enable_interrupt() - - -/*-----------------------------------------------------------*/ - -/* Task utilities. */ -#define portEND_SWITCHING_ISR( xSwitchRequired ) \ -{ \ -extern void vTaskSwitchContext( void ); \ - \ - if( xSwitchRequired ) \ - { \ - vTaskSwitchContext(); \ - } \ -} -/*-----------------------------------------------------------*/ - -/* Compiler specifics */ -#define inline - -/* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) - -#endif /* PORTMACRO_H */ - - diff --git a/Source/portable/Keil/ARM7/port.c b/Source/portable/Keil/ARM7/port.c deleted file mode 100644 index 011367980..000000000 --- a/Source/portable/Keil/ARM7/port.c +++ /dev/null @@ -1,242 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the ARM7 port - * using the Keil compiler. - * - * Components that can be compiled to either ARM or THUMB mode are - * contained in this file. The ISR routines, which can only be compiled - * to ARM mode are contained in portISR.c. - *----------------------------------------------------------*/ - -/* - Changes from V3.2.2 - - + Bug fix - The prescale value for the timer setup is now written to T0PR - instead of T0PC. This bug would have had no effect unless a prescale - value was actually used. -*/ - -/* Standard includes. */ -#include - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Constants required to setup the initial task context. */ -#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ -#define portTHUMB_MODE_BIT ( ( portSTACK_TYPE ) 0x20 ) -#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 ) -#define portNO_CRITICAL_SECTION_NESTING ( ( portSTACK_TYPE ) 0 ) - -/* Constants required to setup the tick ISR. */ -#define portENABLE_TIMER ( ( unsigned portCHAR ) 0x01 ) -#define portPRESCALE_VALUE 0x00 -#define portINTERRUPT_ON_MATCH ( ( unsigned portLONG ) 0x01 ) -#define portRESET_COUNT_ON_MATCH ( ( unsigned portLONG ) 0x02 ) - -/* Constants required to setup the VIC for the tick ISR. */ -#define portTIMER_VIC_CHANNEL ( ( unsigned portLONG ) 0x0004 ) -#define portTIMER_VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x0010 ) -#define portTIMER_VIC_ENABLE ( ( unsigned portLONG ) 0x0020 ) - -/*-----------------------------------------------------------*/ - -/* Setup the timer to generate the tick interrupts. */ -static void prvSetupTimerInterrupt( void ); - -/* - * The scheduler can only be started from ARM mode, so - * vPortISRStartFirstSTask() is defined in portISR.c. - */ -extern void vPortISRStartFirstTask( void ); - -/*-----------------------------------------------------------*/ - -/* - * See header file for description. - */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) -{ -portSTACK_TYPE *pxOriginalTOS; - - /* Setup the initial stack of the task. The stack is set exactly as - expected by the portRESTORE_CONTEXT() macro. - - Remember where the top of the (simulated) stack is before we place - anything on it. */ - pxOriginalTOS = pxTopOfStack; - - /* First on the stack is the return address - which in this case is the - start of the task. The offset is added to make the return address appear - as it would within an IRQ ISR. */ - *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; - pxTopOfStack--; - - *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ - pxTopOfStack--; - - /* The last thing onto the stack is the status register, which is set for - system mode, with interrupts enabled. */ - *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR; - - #ifdef KEIL_THUMB_INTERWORK - { - /* We want the task to start in thumb mode. */ - *pxTopOfStack |= portTHUMB_MODE_BIT; - } - #endif - - pxTopOfStack--; - - /* The code generated by the Keil compiler does not maintain separate - stack and frame pointers. The portENTER_CRITICAL macro cannot therefore - use the stack as per other ports. Instead a variable is used to keep - track of the critical section nesting. This variable has to be stored - as part of the task context and is initially set to zero. */ - *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING; - - return pxTopOfStack; -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xPortStartScheduler( void ) -{ - /* Start the timer that generates the tick ISR. */ - prvSetupTimerInterrupt(); - - /* Start the first task. This is done from portISR.c as ARM mode must be - used. */ - vPortISRStartFirstTask(); - - /* Should not get here! */ - return 0; -} -/*-----------------------------------------------------------*/ - -void vPortEndScheduler( void ) -{ - /* It is unlikely that the ARM port will require this function as there - is nothing to return to. If this is required - stop the tick ISR then - return back to main. */ -} -/*-----------------------------------------------------------*/ - -static void prvSetupTimerInterrupt( void ) -{ -unsigned portLONG ulCompareMatch; - - /* A 1ms tick does not require the use of the timer prescale. This is - defaulted to zero but can be used if necessary. */ - T0PR = portPRESCALE_VALUE; - - /* Calculate the match value required for our wanted tick rate. */ - ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ; - - /* Protect against divide by zero. Using an if() statement still results - in a warning - hence the #if. */ - #if portPRESCALE_VALUE != 0 - { - ulCompareMatch /= ( portPRESCALE_VALUE + 1 ); - } - #endif - - T0MR0 = ulCompareMatch; - - /* Generate tick with timer 0 compare match. */ - T0MCR = portRESET_COUNT_ON_MATCH | portINTERRUPT_ON_MATCH; - - /* Setup the VIC for the timer. */ - VICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT ); - VICIntEnable |= portTIMER_VIC_CHANNEL_BIT; - - /* The ISR installed depends on whether the preemptive or cooperative - scheduler is being used. */ - #if configUSE_PREEMPTION == 1 - { - #ifdef KEIL_THUMB_INTERWORK - extern void ( vPreemptiveTick )( void ) __arm __task; - #else - extern void ( vPreemptiveTick )( void ) __task; - #endif - - VICVectAddr0 = ( unsigned portLONG ) vPreemptiveTick; - } - #else - { - extern void ( vNonPreemptiveTick )( void ) __irq; - - VICVectAddr0 = ( portLONG ) vNonPreemptiveTick; - } - #endif - - VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE; - - /* Start the timer - interrupts are disabled when this function is called - so it is okay to do this here. */ - T0TCR = portENABLE_TIMER; -} -/*-----------------------------------------------------------*/ - - - diff --git a/Source/portable/Keil/ARM7/portISR.c b/Source/portable/Keil/ARM7/portISR.c deleted file mode 100644 index 709d590f2..000000000 --- a/Source/portable/Keil/ARM7/portISR.c +++ /dev/null @@ -1,244 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/*----------------------------------------------------------- - * Components that can be compiled to either ARM or THUMB mode are - * contained in port.c The ISR routines, which can only be compiled - * to ARM mode, are contained in this file. - *----------------------------------------------------------*/ - -/* This file must always be compiled to ARM mode as it contains ISR -definitions. */ -#pragma ARM - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Constants required to handle interrupts. */ -#define portTIMER_MATCH_ISR_BIT ( ( unsigned portCHAR ) 0x01 ) -#define portCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 ) - -/*-----------------------------------------------------------*/ - -/* The code generated by the Keil compiler does not maintain separate -stack and frame pointers. The portENTER_CRITICAL macro cannot therefore -use the stack as per other ports. Instead a variable is used to keep -track of the critical section nesting. This variable has to be stored -as part of the task context and must be initialised to a non zero value. */ - -#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 ) -volatile unsigned portLONG ulCriticalNesting = 9999UL; - -/*-----------------------------------------------------------*/ - -/* ISR to handle manual context switches (from a call to taskYIELD()). */ -void vPortYieldProcessor( void ); - -/* - * The scheduler can only be started from ARM mode, hence the inclusion of this - * function here. - */ -void vPortISRStartFirstTask( void ); - -/*-----------------------------------------------------------*/ - -void vPortISRStartFirstTask( void ) -{ - /* Simply start the scheduler. This is included here as it can only be - called from ARM mode. */ - portRESTORE_CONTEXT(); -} -/*-----------------------------------------------------------*/ - -/* - * Interrupt service routine for the SWI interrupt. The vector table is - * configured within startup.s. - * - * vPortYieldProcessor() is used to manually force a context switch. The - * SWI interrupt is generated by a call to taskYIELD() or portYIELD(). - */ -void vPortYieldProcessor( void ) __task -{ - /* Within an IRQ ISR the link register has an offset from the true return - address, but an SWI ISR does not. Add the offset manually so the same - ISR return code can be used in both cases. */ - __asm{ ADD LR, LR, #4 }; - - /* Perform the context switch. */ - portSAVE_CONTEXT(); - vTaskSwitchContext(); - portRESTORE_CONTEXT(); -} -/*-----------------------------------------------------------*/ - -/* - * The ISR used for the scheduler tick depends on whether the cooperative or - * the preemptive scheduler is being used. - */ - -#if configUSE_PREEMPTION == 0 - - /* - * The cooperative scheduler requires a normal IRQ service routine to - * simply increment the system tick. - */ - void vNonPreemptiveTick( void ); - void vNonPreemptiveTick( void ) __irq - { - /* Increment the tick count - this may make a delaying task ready - to run - but a context switch is not performed. */ - vTaskIncrementTick(); - - /* Ready for the next interrupt. */ - T0IR = portTIMER_MATCH_ISR_BIT; - VICVectAddr = portCLEAR_VIC_INTERRUPT; - } - -#else - - /* - * The preemptive scheduler ISR is defined as "naked" as the full context - * is saved on entry as part of the context switch. - */ - void vPreemptiveTick( void ); - void vPreemptiveTick( void ) __task - { - /* Save the context of the current task. */ - portSAVE_CONTEXT(); - - /* Increment the tick count - this may make a delayed task ready to - run. */ - vTaskIncrementTick(); - - /* Find the highest priority task that is ready to run. */ - vTaskSwitchContext(); - - /* Ready for the next interrupt. */ - T0IR = portTIMER_MATCH_ISR_BIT; - VICVectAddr = portCLEAR_VIC_INTERRUPT; - - /* Restore the context of the highest priority task that is ready to - run. */ - portRESTORE_CONTEXT(); - } -#endif -/*-----------------------------------------------------------*/ - -/* - * The interrupt management utilities can only be called from ARM mode. When - * KEIL_THUMB_INTERWORK is defined the utilities are defined as functions here - * to ensure a switch to ARM mode. When KEIL_THUMB_INTERWORK is not defined - * then the utilities are defined as macros in portmacro.h - as per other - * ports. - */ -#ifdef KEIL_THUMB_INTERWORK - - void vPortDisableInterruptsFromThumb( void ) __task; - void vPortEnableInterruptsFromThumb( void ) __task; - - void vPortDisableInterruptsFromThumb( void ) __task - { - __asm{ STMDB SP!, {R0} }; /* Push R0. */ - __asm{ MRS R0, CPSR }; /* Get CPSR. */ - __asm{ ORR R0, R0, #0xC0 }; /* Disable IRQ, FIQ. */ - __asm{ MSR CPSR_CXSF, R0 }; /* Write back modified value. */ - __asm{ LDMIA SP!, {R0} }; /* Pop R0. */ - __asm{ BX R14 }; /* Return back to thumb. */ - } - - void vPortEnableInterruptsFromThumb( void ) __task - { - __asm{ STMDB SP!, {R0} }; /* Push R0. */ - __asm{ MRS R0, CPSR }; /* Get CPSR. */ - __asm{ BIC R0, R0, #0xC0 }; /* Enable IRQ, FIQ. */ - __asm{ MSR CPSR_CXSF, R0 }; /* Write back modified value. */ - __asm{ LDMIA SP!, {R0} }; /* Pop R0. */ - __asm{ BX R14 }; /* Return back to thumb. */ - } - -#endif /* KEIL_THUMB_INTERWORK */ - - - -/* The code generated by the Keil compiler does not maintain separate -stack and frame pointers. The portENTER_CRITICAL macro cannot therefore -use the stack as per other ports. Instead a variable is used to keep -track of the critical section nesting. This necessitates the use of a -function in place of the macro. */ - -void vPortEnterCritical( void ) -{ - /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ - __asm{ STMDB SP!, {R0} }; /* Push R0. */ - __asm{ MRS R0, CPSR }; /* Get CPSR. */ - __asm{ ORR R0, R0, #0xC0 }; /* Disable IRQ, FIQ. */ - __asm{ MSR CPSR_CXSF, R0 }; /* Write back modified value. */ - __asm{ LDMIA SP!, {R0} }; /* Pop R0. */ - - /* Now interrupts are disabled ulCriticalNesting can be accessed - directly. Increment ulCriticalNesting to keep a count of how many times - portENTER_CRITICAL() has been called. */ - ulCriticalNesting++; -} - -void vPortExitCritical( void ) -{ - if( ulCriticalNesting > portNO_CRITICAL_NESTING ) - { - /* Decrement the nesting count as we are leaving a critical section. */ - ulCriticalNesting--; - - /* If the nesting level has reached zero then interrupts should be - re-enabled. */ - if( ulCriticalNesting == portNO_CRITICAL_NESTING ) - { - /* Enable interrupts as per portEXIT_CRITICAL(). */ - __asm{ STMDB SP!, {R0} }; /* Push R0. */ - __asm{ MRS R0, CPSR }; /* Get CPSR. */ - __asm{ BIC R0, R0, #0xC0 }; /* Enable IRQ, FIQ. */ - __asm{ MSR CPSR_CXSF, R0 }; /* Write back modified value. */ - __asm{ LDMIA SP!, {R0} }; /* Pop R0. */ - } - } -} - - - - - - - - - - diff --git a/Source/portable/Keil/ARM7/portmacro.h b/Source/portable/Keil/ARM7/portmacro.h deleted file mode 100644 index 86b859664..000000000 --- a/Source/portable/Keil/ARM7/portmacro.h +++ /dev/null @@ -1,224 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -/*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the - * given hardware and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - -/* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE unsigned portLONG -#define portBASE_TYPE portLONG - -#if( configUSE_16_BIT_TICKS == 1 ) - typedef unsigned portSHORT portTickType; - #define portMAX_DELAY ( portTickType ) 0xffff -#else - typedef unsigned portLONG portTickType; - #define portMAX_DELAY ( portTickType ) 0xffffffff -#endif -/*-----------------------------------------------------------*/ - -/* Hardware specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 4 -/*-----------------------------------------------------------*/ - -/* Task utilities. */ -#define portRESTORE_CONTEXT() \ -{ \ -extern volatile unsigned portLONG ulCriticalNesting; \ -extern volatile void * volatile pxCurrentTCB; \ - \ - __asm{ LDR R1, =pxCurrentTCB };/* Set the LR to the task stack. The location was ... */ \ - __asm{ LDR R0, [R1] }; /* ... stored in pxCurrentTCB. */ \ - __asm{ LDR LR, [R0] }; \ - \ - __asm{ LDR R0, =ulCriticalNesting }; /* The critical nesting depth is the first item on ... */ \ - __asm{ LDMFD LR!, {R1 } } /* ... the stack. Load it into the ulCriticalNesting var. */ \ - __asm{ STR R1, [R0] } \ - \ - __asm{ LDMFD LR!, {R0} }; /* Get the SPSR from the stack. */ \ - __asm{ MSR SPSR_CXSF, R0 }; \ - \ - __asm{ LDMFD LR, {R0-R14}^ }; /* Restore all system mode registers for the task. */ \ - __asm{ NOP }; \ - \ - __asm{ LDR LR, [LR, #+60] }; /* Restore the return address. */ \ - \ - /* And return - correcting the offset in the LR to obtain ... */ \ - __asm{ SUBS PC, LR, #4 }; /* ... the correct address. */ \ -} -/*----------------------------------------------------------*/ - -#define portSAVE_CONTEXT() \ -{ \ -extern volatile unsigned portLONG ulCriticalNesting; \ -extern volatile void * volatile pxCurrentTCB; \ - \ - __asm{ STMDB SP!, {R0} }; /* Store R0 first as we need to use it. */ \ - \ - __asm{ STMDB SP,{SP}^ }; /* Set R0 to point to the task stack pointer. */ \ - __asm{ NOP }; \ - __asm{ SUB SP, SP, #4 }; \ - __asm{ LDMIA SP!,{R0} }; \ - \ - __asm{ STMDB R0!, {LR} }; /* Push the return address onto the stack. */ \ - __asm{ MOV LR, R0 }; /* Now we have saved LR we can use it instead of R0. */ \ - __asm{ LDMIA SP!, {R0} }; /* Pop R0 so we can save it onto the system mode stack. */ \ - \ - __asm{ STMDB LR,{R0-LR}^ }; /* Push all the system mode registers onto the task stack. */ \ - __asm{ NOP }; \ - __asm{ SUB LR, LR, #60 }; \ - \ - __asm{ MRS R0, SPSR }; /* Push the SPSR onto the task stack. */ \ - __asm{ STMDB LR!, {R0} }; \ - \ - __asm{ LDR R0, =ulCriticalNesting }; \ - __asm{ LDR R0, [R0] }; \ - __asm{ STMDB LR!, {R0} }; \ - \ - __asm{ LDR R0, =pxCurrentTCB };/* Store the new top of stack for the task. */ \ - __asm{ LDR R1, [R0] }; \ - __asm{ STR LR, [R1] }; \ -} - -/*----------------------------------------------------------- - * ISR entry and exit macros. These are only required if a task switch - * is required from an ISR. - *----------------------------------------------------------*/ - -#define portENTER_SWITCHING_ISR() \ - portSAVE_CONTEXT(); \ - { - -#define portEXIT_SWITCHING_ISR( SwitchRequired ) \ - /* If a switch is required then we just need to call */ \ - /* vTaskSwitchContext() as the context has already been */ \ - /* saved. */ \ - if( SwitchRequired ) \ - { \ - vTaskSwitchContext(); \ - } \ - } \ - /* Restore the context of which ever task is now the highest */ \ - /* priority that is ready to run. */ \ - portRESTORE_CONTEXT(); - - -/* Yield the processor - force a context switch. */ -#define portYIELD() __asm{ SWI 0 }; -/*-----------------------------------------------------------*/ - -/* Critical section management. */ - -/*----------------------------------------------------------- - * Interrupt control macros. - * - * The interrupt management utilities can only be called from ARM mode. When - * KEIL_THUMB_INTERWORK is defined the utilities are defined as functions in - * portISR.c to ensure a switch to ARM mode. When KEIL_THUMB_INTERWORK is not - * defined then the utilities are defined as macros here - as per other ports. - *----------------------------------------------------------*/ - -#ifdef KEIL_THUMB_INTERWORK - - extern void vPortDisableInterruptsFromThumb( void ) __task; - extern void vPortEnableInterruptsFromThumb( void ) __task; - - #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb() - #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb() - -#else - - /*-----------------------------------------------------------*/ - - #define portDISABLE_INTERRUPTS() \ - __asm{ STMDB SP!, {R0} }; /* Push R0. */ \ - __asm{ MRS R0, CPSR }; /* Get CPSR. */ \ - __asm{ ORR R0, R0, #0xC0 }; /* Disable IRQ, FIQ. */ \ - __asm{ MSR CPSR_CXSF, R0 }; /* Write back modified value. */ \ - __asm{ LDMIA SP!, {R0} } /* Pop R0. */ - - #define portENABLE_INTERRUPTS() \ - __asm{ STMDB SP!, {R0} }; /* Push R0. */ \ - __asm{ MRS R0, CPSR }; /* Get CPSR. */ \ - __asm{ BIC R0, R0, #0xC0 }; /* Enable IRQ, FIQ. */ \ - __asm{ MSR CPSR_CXSF, R0 }; /* Write back modified value. */ \ - __asm{ LDMIA SP!, {R0} } /* Pop R0. */ - -#endif /* KEIL_THUMB_INTERWORK */ - -/*----------------------------------------------------------- - * Critical section control - * - * The code generated by the Keil compiler does not maintain separate - * stack and frame pointers. The portENTER_CRITICAL macro cannot therefore - * use the stack as per other ports. Instead a variable is used to keep - * track of the critical section nesting. This necessitates the use of a - * function in place of the macro. - *----------------------------------------------------------*/ - -extern void vPortEnterCritical( void ); -extern void vPortExitCritical( void ); - -#define portENTER_CRITICAL() vPortEnterCritical(); -#define portEXIT_CRITICAL() vPortExitCritical(); -/*-----------------------------------------------------------*/ - -/* Compiler specifics. */ -#define inline -#define register -#define portNOP() __asm{ NOP } -/*-----------------------------------------------------------*/ - -/* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __task -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) - -#endif /* PORTMACRO_H */ - diff --git a/Source/portable/MPLAB/PIC18F/port.c b/Source/portable/MPLAB/PIC18F/port.c deleted file mode 100644 index 5a7214e0f..000000000 --- a/Source/portable/MPLAB/PIC18F/port.c +++ /dev/null @@ -1,626 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes between V1.2.4 and V1.2.5 - - + Introduced portGLOBAL_INTERRUPT_FLAG definition to test the global - interrupt flag setting. Using the two bits defined within - portINITAL_INTERRUPT_STATE was causing the w register to get clobbered - before the test was performed. - -Changes from V1.2.5 - - + Set the interrupt vector address to 0x08. Previously it was at the - incorrect address for compatibility mode of 0x18. - -Changes from V2.1.1 - - + PCLATU and PCLATH are now saved as part of the context. This allows - function pointers to be used within tasks. Thanks to Javier Espeche - for the enhancement. - -Changes from V2.3.1 - - + TABLAT is now saved as part of the task context. - -Changes from V3.2.0 - - + TBLPTRU is now initialised to zero as the MPLAB compiler expects this - value and does not write to the register. -*/ - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" - -/* MPLAB library include file. */ -#include "timers.h" - -/*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the PIC port. - *----------------------------------------------------------*/ - -/* Hardware setup for tick. */ -#define portTIMER_FOSC_SCALE ( ( unsigned portLONG ) 4 ) - -/* Initial interrupt enable state for newly created tasks. This value is -copied into INTCON when a task switches in for the first time. */ -#define portINITAL_INTERRUPT_STATE 0xc0 - -/* Just the bit within INTCON for the global interrupt flag. */ -#define portGLOBAL_INTERRUPT_FLAG 0x80 - -/* Constant used for context switch macro when we require the interrupt -enable state to be unchanged when the interrupted task is switched back in. */ -#define portINTERRUPTS_UNCHANGED 0x00 - -/* Some memory areas get saved as part of the task context. These memory -area's get used by the compiler for temporary storage, especially when -performing mathematical operations, or when using 32bit data types. This -constant defines the size of memory area which must be saved. */ -#define portCOMPILER_MANAGED_MEMORY_SIZE ( ( unsigned portCHAR ) 0x13 ) - -/* We require the address of the pxCurrentTCB variable, but don't want to know -any details of its type. */ -typedef void tskTCB; -extern volatile tskTCB * volatile pxCurrentTCB; - -/* IO port constants. */ -#define portBIT_SET ( ( unsigned portCHAR ) 1 ) -#define portBIT_CLEAR ( ( unsigned portCHAR ) 0 ) - -/* - * The serial port ISR's are defined in serial.c, but are called from portable - * as they use the same vector as the tick ISR. - */ -void vSerialTxISR( void ); -void vSerialRxISR( void ); - -/* - * Perform hardware setup to enable ticks. - */ -static void prvSetupTimerInterrupt( void ); - -/* - * ISR to maintain the tick, and perform tick context switches if the - * preemptive scheduler is being used. - */ -static void prvTickISR( void ); - -/* - * ISR placed on the low priority vector. This calls the appropriate ISR for - * the actual interrupt. - */ -static void prvLowInterrupt( void ); - -/* - * Macro that pushes all the registers that make up the context of a task onto - * the stack, then saves the new top of stack into the TCB. - * - * If this is called from an ISR then the interrupt enable bits must have been - * set for the ISR to ever get called. Therefore we want to save the INTCON - * register with the enable bits forced to be set - and ucForcedInterruptFlags - * must contain these bit settings. This means the interrupts will again be - * enabled when the interrupted task is switched back in. - * - * If this is called from a manual context switch (i.e. from a call to yield), - * then we want to save the INTCON so it is restored with its current state, - * and ucForcedInterruptFlags must be 0. This allows a yield from within - * a critical section. - * - * The compiler uses some locations at the bottom of the memory for temporary - * storage during math and other computations. This is especially true if - * 32bit data types are utilised (as they are by the scheduler). The .tmpdata - * and MATH_DATA sections have to be stored in there entirety as part of a task - * context. This macro stores from data address 0x00 to - * portCOMPILER_MANAGED_MEMORY_SIZE. This is sufficient for the demo - * applications but you should check the map file for your project to ensure - * this is sufficient for your needs. It is not clear whether this size is - * fixed for all compilations or has the potential to be program specific. - */ -#define portSAVE_CONTEXT( ucForcedInterruptFlags ) \ -{ \ - _asm \ - /* Save the status and WREG registers first, as these will get modified \ - by the operations below. */ \ - MOVFF WREG, PREINC1 \ - MOVFF STATUS, PREINC1 \ - /* Save the INTCON register with the appropriate bits forced if \ - necessary - as described above. */ \ - MOVFF INTCON, WREG \ - IORLW ucForcedInterruptFlags \ - MOVFF WREG, PREINC1 \ - _endasm \ - \ - portDISABLE_INTERRUPTS(); \ - \ - _asm \ - /* Store the necessary registers to the stack. */ \ - MOVFF BSR, PREINC1 \ - MOVFF FSR2L, PREINC1 \ - MOVFF FSR2H, PREINC1 \ - MOVFF FSR0L, PREINC1 \ - MOVFF FSR0H, PREINC1 \ - MOVFF TABLAT, PREINC1 \ - MOVFF TBLPTRU, PREINC1 \ - MOVFF TBLPTRH, PREINC1 \ - MOVFF TBLPTRL, PREINC1 \ - MOVFF PRODH, PREINC1 \ - MOVFF PRODL, PREINC1 \ - MOVFF PCLATU, PREINC1 \ - MOVFF PCLATH, PREINC1 \ - /* Store the .tempdata and MATH_DATA areas as described above. */ \ - CLRF FSR0L, 0 \ - CLRF FSR0H, 0 \ - MOVFF POSTINC0, PREINC1 \ - MOVFF POSTINC0, PREINC1 \ - MOVFF POSTINC0, PREINC1 \ - MOVFF POSTINC0, PREINC1 \ - MOVFF POSTINC0, PREINC1 \ - MOVFF POSTINC0, PREINC1 \ - MOVFF POSTINC0, PREINC1 \ - MOVFF POSTINC0, PREINC1 \ - MOVFF POSTINC0, PREINC1 \ - MOVFF POSTINC0, PREINC1 \ - MOVFF POSTINC0, PREINC1 \ - MOVFF POSTINC0, PREINC1 \ - MOVFF POSTINC0, PREINC1 \ - MOVFF POSTINC0, PREINC1 \ - MOVFF POSTINC0, PREINC1 \ - MOVFF POSTINC0, PREINC1 \ - MOVFF POSTINC0, PREINC1 \ - MOVFF POSTINC0, PREINC1 \ - MOVFF POSTINC0, PREINC1 \ - MOVFF INDF0, PREINC1 \ - MOVFF FSR0L, PREINC1 \ - MOVFF FSR0H, PREINC1 \ - /* Store the hardware stack pointer in a temp register before we \ - modify it. */ \ - MOVFF STKPTR, FSR0L \ - _endasm \ - \ - /* Store each address from the hardware stack. */ \ - while( STKPTR > ( unsigned portCHAR ) 0 ) \ - { \ - _asm \ - MOVFF TOSL, PREINC1 \ - MOVFF TOSH, PREINC1 \ - MOVFF TOSU, PREINC1 \ - POP \ - _endasm \ - } \ - \ - _asm \ - /* Store the number of addresses on the hardware stack (from the \ - temporary register). */ \ - MOVFF FSR0L, PREINC1 \ - MOVF PREINC1, 1, 0 \ - _endasm \ - \ - /* Save the new top of the software stack in the TCB. */ \ - _asm \ - MOVFF pxCurrentTCB, FSR0L \ - MOVFF pxCurrentTCB + 1, FSR0H \ - MOVFF FSR1L, POSTINC0 \ - MOVFF FSR1H, POSTINC0 \ - _endasm \ -} -/*-----------------------------------------------------------*/ - -/* - * This is the reverse of portSAVE_CONTEXT. See portSAVE_CONTEXT for more - * details. - */ -#define portRESTORE_CONTEXT() \ -{ \ - _asm \ - /* Set FSR0 to point to pxCurrentTCB->pxTopOfStack. */ \ - MOVFF pxCurrentTCB, FSR0L \ - MOVFF pxCurrentTCB + 1, FSR0H \ - \ - /* De-reference FSR0 to set the address it holds into FSR1. \ - (i.e. *( pxCurrentTCB->pxTopOfStack ) ). */ \ - MOVFF POSTINC0, FSR1L \ - MOVFF POSTINC0, FSR1H \ - \ - /* How many return addresses are there on the hardware stack? Discard \ - the first byte as we are pointing to the next free space. */ \ - MOVFF POSTDEC1, FSR0L \ - MOVFF POSTDEC1, FSR0L \ - _endasm \ - \ - /* Fill the hardware stack from our software stack. */ \ - STKPTR = 0; \ - \ - while( STKPTR < FSR0L ) \ - { \ - _asm \ - PUSH \ - MOVF POSTDEC1, 0, 0 \ - MOVWF TOSU, 0 \ - MOVF POSTDEC1, 0, 0 \ - MOVWF TOSH, 0 \ - MOVF POSTDEC1, 0, 0 \ - MOVWF TOSL, 0 \ - _endasm \ - } \ - \ - _asm \ - /* Restore the .tmpdata and MATH_DATA memory. */ \ - MOVFF POSTDEC1, FSR0H \ - MOVFF POSTDEC1, FSR0L \ - MOVFF POSTDEC1, POSTDEC0 \ - MOVFF POSTDEC1, POSTDEC0 \ - MOVFF POSTDEC1, POSTDEC0 \ - MOVFF POSTDEC1, POSTDEC0 \ - MOVFF POSTDEC1, POSTDEC0 \ - MOVFF POSTDEC1, POSTDEC0 \ - MOVFF POSTDEC1, POSTDEC0 \ - MOVFF POSTDEC1, POSTDEC0 \ - MOVFF POSTDEC1, POSTDEC0 \ - MOVFF POSTDEC1, POSTDEC0 \ - MOVFF POSTDEC1, POSTDEC0 \ - MOVFF POSTDEC1, POSTDEC0 \ - MOVFF POSTDEC1, POSTDEC0 \ - MOVFF POSTDEC1, POSTDEC0 \ - MOVFF POSTDEC1, POSTDEC0 \ - MOVFF POSTDEC1, POSTDEC0 \ - MOVFF POSTDEC1, POSTDEC0 \ - MOVFF POSTDEC1, POSTDEC0 \ - MOVFF POSTDEC1, POSTDEC0 \ - MOVFF POSTDEC1, INDF0 \ - /* Restore the other registers forming the tasks context. */ \ - MOVFF POSTDEC1, PCLATH \ - MOVFF POSTDEC1, PCLATU \ - MOVFF POSTDEC1, PRODL \ - MOVFF POSTDEC1, PRODH \ - MOVFF POSTDEC1, TBLPTRL \ - MOVFF POSTDEC1, TBLPTRH \ - MOVFF POSTDEC1, TBLPTRU \ - MOVFF POSTDEC1, TABLAT \ - MOVFF POSTDEC1, FSR0H \ - MOVFF POSTDEC1, FSR0L \ - MOVFF POSTDEC1, FSR2H \ - MOVFF POSTDEC1, FSR2L \ - MOVFF POSTDEC1, BSR \ - /* The next byte is the INTCON register. Read this into WREG as some \ - manipulation is required. */ \ - MOVFF POSTDEC1, WREG \ - _endasm \ - \ - /* From the INTCON register, only the interrupt enable bits form part \ - of the tasks context. It is perfectly legitimate for another task to \ - have modified any other bits. We therefore only restore the top two bits. \ - */ \ - if( WREG & portGLOBAL_INTERRUPT_FLAG ) \ - { \ - _asm \ - MOVFF POSTDEC1, STATUS \ - MOVFF POSTDEC1, WREG \ - /* Return enabling interrupts. */ \ - RETFIE 0 \ - _endasm \ - } \ - else \ - { \ - _asm \ - MOVFF POSTDEC1, STATUS \ - MOVFF POSTDEC1, WREG \ - /* Return without effecting interrupts. The context may have \ - been saved from a critical region. */ \ - RETURN 0 \ - _endasm \ - } \ -} -/*-----------------------------------------------------------*/ - -/* - * See header file for description. - */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) -{ -unsigned portLONG ulAddress; -unsigned portCHAR ucBlock; - - /* Place a few bytes of known values on the bottom of the stack. - This is just useful for debugging. */ - - *pxTopOfStack = 0x11; - pxTopOfStack++; - *pxTopOfStack = 0x22; - pxTopOfStack++; - *pxTopOfStack = 0x33; - pxTopOfStack++; - - - /* Simulate how the stack would look after a call to vPortYield() generated - by the compiler. - - First store the function parameters. This is where the task will expect to - find them when it starts running. */ - ulAddress = ( unsigned portLONG ) pvParameters; - *pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned portLONG ) 0x00ff ); - pxTopOfStack++; - - ulAddress >>= 8; - *pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned portLONG ) 0x00ff ); - pxTopOfStack++; - - /* Next we just leave a space. When a context is saved the stack pointer - is incremented before it is used so as not to corrupt whatever the stack - pointer is actually pointing to. This is especially necessary during - function epilogue code generated by the compiler. */ - *pxTopOfStack = 0x44; - pxTopOfStack++; - - /* Next are all the registers that form part of the task context. */ - - *pxTopOfStack = ( portSTACK_TYPE ) 0x66; /* WREG. */ - pxTopOfStack++; - - *pxTopOfStack = ( portSTACK_TYPE ) 0xcc; /* Status. */ - pxTopOfStack++; - - /* INTCON is saved with interrupts enabled. */ - *pxTopOfStack = ( portSTACK_TYPE ) portINITAL_INTERRUPT_STATE; /* INTCON */ - pxTopOfStack++; - - *pxTopOfStack = ( portSTACK_TYPE ) 0x11; /* BSR. */ - pxTopOfStack++; - - *pxTopOfStack = ( portSTACK_TYPE ) 0x22; /* FSR2L. */ - pxTopOfStack++; - - *pxTopOfStack = ( portSTACK_TYPE ) 0x33; /* FSR2H. */ - pxTopOfStack++; - - *pxTopOfStack = ( portSTACK_TYPE ) 0x44; /* FSR0L. */ - pxTopOfStack++; - - *pxTopOfStack = ( portSTACK_TYPE ) 0x55; /* FSR0H. */ - pxTopOfStack++; - - *pxTopOfStack = ( portSTACK_TYPE ) 0x66; /* TABLAT. */ - pxTopOfStack++; - - *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* TBLPTRU. */ - pxTopOfStack++; - - *pxTopOfStack = ( portSTACK_TYPE ) 0x88; /* TBLPTRUH. */ - pxTopOfStack++; - - *pxTopOfStack = ( portSTACK_TYPE ) 0x99; /* TBLPTRUL. */ - pxTopOfStack++; - - *pxTopOfStack = ( portSTACK_TYPE ) 0xaa; /* PRODH. */ - pxTopOfStack++; - - *pxTopOfStack = ( portSTACK_TYPE ) 0xbb; /* PRODL. */ - pxTopOfStack++; - - *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* PCLATU. */ - pxTopOfStack++; - - *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* PCLATH. */ - pxTopOfStack++; - - /* Next the .tmpdata and MATH_DATA sections. */ - for( ucBlock = 0; ucBlock <= portCOMPILER_MANAGED_MEMORY_SIZE; ucBlock++ ) - { - *pxTopOfStack = ( portSTACK_TYPE ) ucBlock; - *pxTopOfStack++; - } - - /* Store the top of the global data section. */ - *pxTopOfStack = ( portSTACK_TYPE ) portCOMPILER_MANAGED_MEMORY_SIZE; /* Low. */ - pxTopOfStack++; - - *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* High. */ - pxTopOfStack++; - - /* The only function return address so far is the address of the - task. */ - ulAddress = ( unsigned portLONG ) pxCode; - - /* TOS low. */ - *pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned portLONG ) 0x00ff ); - pxTopOfStack++; - ulAddress >>= 8; - - /* TOS high. */ - *pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned portLONG ) 0x00ff ); - pxTopOfStack++; - ulAddress >>= 8; - - /* TOS even higher. */ - *pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned portLONG ) 0x00ff ); - pxTopOfStack++; - - /* Store the number of return addresses on the hardware stack - so far only - the address of the task entry point. */ - *pxTopOfStack = ( portSTACK_TYPE ) 1; - pxTopOfStack++; - - return pxTopOfStack; -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xPortStartScheduler( void ) -{ - /* In this port we ignore the parameter and use the configUSE_PREEMPTION - definition instead. */ - - /* Setup a timer for the tick ISR is using the preemptive scheduler. */ - prvSetupTimerInterrupt(); - - /* Restore the context of the first task to run. */ - portRESTORE_CONTEXT(); - - /* Should not get here. Use the function name to stop compiler warnings. */ - ( void ) prvLowInterrupt; - ( void ) prvTickISR; - - return pdTRUE; -} -/*-----------------------------------------------------------*/ - -void vPortEndScheduler( void ) -{ - /* It is unlikely that the scheduler for the PIC port will get stopped - once running. If required disable the tick interrupt here, then return - to xPortStartScheduler(). */ -} -/*-----------------------------------------------------------*/ - -/* - * Manual context switch. This is similar to the tick context switch, - * but does not increment the tick count. It must be identical to the - * tick context switch in how it stores the stack of a task. - */ -void vPortYield( void ) -{ - /* This can get called with interrupts either enabled or disabled. We - will save the INTCON register with the interrupt enable bits unmodified. */ - portSAVE_CONTEXT( portINTERRUPTS_UNCHANGED ); - - /* Switch to the highest priority task that is ready to run. */ - vTaskSwitchContext(); - - /* Start executing the task we have just switched to. */ - portRESTORE_CONTEXT(); -} -/*-----------------------------------------------------------*/ - -/* - * Vector for ISR. Nothing here must alter any registers! - */ -#pragma code high_vector=0x08 -static void prvLowInterrupt( void ) -{ - /* Was the interrupt the tick? */ - if( PIR1bits.CCP1IF ) - { - _asm - goto prvTickISR - _endasm - } - - /* Was the interrupt a byte being received? */ - if( PIR1bits.RCIF ) - { - _asm - goto vSerialRxISR - _endasm - } - - /* Was the interrupt the Tx register becoming empty? */ - if( PIR1bits.TXIF ) - { - if( PIE1bits.TXIE ) - { - _asm - goto vSerialTxISR - _endasm - } - } -} -#pragma code - -/*-----------------------------------------------------------*/ - -/* - * ISR for the tick. - * This increments the tick count and, if using the preemptive scheduler, - * performs a context switch. This must be identical to the manual - * context switch in how it stores the context of a task. - */ -static void prvTickISR( void ) -{ - /* Interrupts must have been enabled for the ISR to fire, so we have to - save the context with interrupts enabled. */ - portSAVE_CONTEXT( portGLOBAL_INTERRUPT_FLAG ); - PIR1bits.CCP1IF = 0; - - /* Maintain the tick count. */ - vTaskIncrementTick(); - - #if configUSE_PREEMPTION == 1 - { - /* Switch to the highest priority task that is ready to run. */ - vTaskSwitchContext(); - } - #endif - - portRESTORE_CONTEXT(); -} -/*-----------------------------------------------------------*/ - -/* - * Setup a timer for a regular tick. - */ -static void prvSetupTimerInterrupt( void ) -{ -const unsigned portLONG ulConstCompareValue = ( ( configCPU_CLOCK_HZ / portTIMER_FOSC_SCALE ) / configTICK_RATE_HZ ); -unsigned portLONG ulCompareValue; -unsigned portCHAR ucByte; - - /* Interrupts are disabled when this function is called. - - Setup CCP1 to provide the tick interrupt using a compare match on timer - 1. - - Clear the time count then setup timer. */ - TMR1H = ( unsigned portCHAR ) 0x00; - TMR1L = ( unsigned portCHAR ) 0x00; - - /* Set the compare match value. */ - ulCompareValue = ulConstCompareValue; - CCPR1L = ( unsigned portCHAR ) ( ulCompareValue & ( unsigned portLONG ) 0xff ); - ulCompareValue >>= ( unsigned portLONG ) 8; - CCPR1H = ( unsigned portCHAR ) ( ulCompareValue & ( unsigned portLONG ) 0xff ); - - CCP1CONbits.CCP1M0 = portBIT_SET; /*< Compare match mode. */ - CCP1CONbits.CCP1M1 = portBIT_SET; /*< Compare match mode. */ - CCP1CONbits.CCP1M2 = portBIT_CLEAR; /*< Compare match mode. */ - CCP1CONbits.CCP1M3 = portBIT_SET; /*< Compare match mode. */ - PIE1bits.CCP1IE = portBIT_SET; /*< Interrupt enable. */ - - /* We are only going to use the global interrupt bit, so set the peripheral - bit to true. */ - INTCONbits.GIEL = portBIT_SET; - - /* Provided library function for setting up the timer that will produce the - tick. */ - OpenTimer1( T1_16BIT_RW & T1_SOURCE_INT & T1_PS_1_1 & T1_CCP1_T3_CCP2 ); -} - diff --git a/Source/portable/MPLAB/PIC18F/portmacro.h b/Source/portable/MPLAB/PIC18F/portmacro.h deleted file mode 100644 index bd6a2028b..000000000 --- a/Source/portable/MPLAB/PIC18F/portmacro.h +++ /dev/null @@ -1,110 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -/*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the - * given hardware and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - -/* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT int -#define portSTACK_TYPE unsigned char -#define portBASE_TYPE char - -#if( configUSE_16_BIT_TICKS == 1 ) - typedef unsigned portSHORT portTickType; - #define portMAX_DELAY ( portTickType ) 0xffff -#else - typedef unsigned portLONG portTickType; - #define portMAX_DELAY ( portTickType ) 0xffffffff -#endif -/*-----------------------------------------------------------*/ - -/* Hardware specifics. */ -#define portBYTE_ALIGNMENT 1 -#define portGLOBAL_INT_ENABLE_BIT 0x80 -#define portSTACK_GROWTH 1 -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) -/*-----------------------------------------------------------*/ - -/* Critical section management. */ -#define portDISABLE_INTERRUPTS() INTCONbits.GIEH = 0; -#define portENABLE_INTERRUPTS() INTCONbits.GIEH = 1; - -/* Push the INTCON register onto the stack, then disable interrupts. */ -#define portENTER_CRITICAL() POSTINC1 = INTCON; \ - INTCONbits.GIEH = 0; - -/* Retrieve the INTCON register from the stack, and enable interrupts -if they were saved as being enabled. Don't modify any other bits -within the INTCON register as these may have lagitimately have been -modified within the critical region. */ -#define portEXIT_CRITICAL() _asm \ - MOVF POSTDEC1, 1, 0 \ - _endasm \ - if( INDF1 & portGLOBAL_INT_ENABLE_BIT ) \ - { \ - portENABLE_INTERRUPTS(); \ - } -/*-----------------------------------------------------------*/ - -/* Task utilities. */ -extern void vPortYield( void ); -#define portYIELD() vPortYield() -/*-----------------------------------------------------------*/ - -/* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) -/*-----------------------------------------------------------*/ - -/* Compiler specifics. */ -#define inline - -#define portNOP() _asm \ - NOP \ - _endasm - -#endif /* PORTMACRO_H */ - diff --git a/Source/portable/MPLAB/PIC24_dsPIC/port.c b/Source/portable/MPLAB/PIC24_dsPIC/port.c deleted file mode 100644 index d976e015f..000000000 --- a/Source/portable/MPLAB/PIC24_dsPIC/port.c +++ /dev/null @@ -1,349 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the PIC24 port. - *----------------------------------------------------------*/ - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Hardware specifics. */ -#define portBIT_SET 1 -#define portTIMER_PRESCALE 8 -#define portINITIAL_SR 0 - -/* The program counter is only 23 bits. */ -#define portUNUSED_PR_BITS 0x7f - -/* Records the nesting depth of calls to portENTER_CRITICAL(). */ -unsigned portBASE_TYPE uxCriticalNesting = 0xef; - -#ifdef MPLAB_PIC24_PORT - - #define portRESTORE_CONTEXT() \ - asm volatile( "MOV _pxCurrentTCB, W0 \n" /* Restore the stack pointer for the task. */ \ - "MOV [W0], W15 \n" \ - "POP W0 \n" /* Restore the critical nesting counter for the task. */ \ - "MOV W0, _uxCriticalNesting \n" \ - "POP PSVPAG \n" \ - "POP CORCON \n" \ - "POP TBLPAG \n" \ - "POP RCOUNT \n" /* Restore the registers from the stack. */ \ - "POP W14 \n" \ - "POP.D W12 \n" \ - "POP.D W10 \n" \ - "POP.D W8 \n" \ - "POP.D W6 \n" \ - "POP.D W4 \n" \ - "POP.D W2 \n" \ - "POP.D W0 \n" \ - "POP SR " ); - - - #define portSAVE_CONTEXT() \ - asm volatile( "PUSH SR \n" /* Save the SR used by the task.... */ \ - "PUSH W0 \n" /* ....then disable interrupts. */ \ - "MOV #224, W0 \n" \ - "MOV W0, SR \n" \ - "PUSH W1 \n" /* Save registers to the stack. */ \ - "PUSH.D W2 \n" \ - "PUSH.D W4 \n" \ - "PUSH.D W6 \n" \ - "PUSH.D W8 \n" \ - "PUSH.D W10 \n" \ - "PUSH.D W12 \n" \ - "PUSH W14 \n" \ - "PUSH RCOUNT \n" \ - "PUSH TBLPAG \n" \ - "PUSH CORCON \n" \ - "PUSH PSVPAG \n" \ - "MOV _uxCriticalNesting, W0 \n" /* Save the critical nesting counter for the task. */ \ - "PUSH W0 \n" \ - "MOV _pxCurrentTCB, W0 \n" /* Save the new top of stack into the TCB. */ \ - "MOV W15, [W0] "); - -#endif /* MPLAB_PIC24_PORT */ - -#ifdef MPLAB_DSPIC_PORT - - #define portRESTORE_CONTEXT() \ - asm volatile( "MOV _pxCurrentTCB, W0 \n" /* Restore the stack pointer for the task. */ \ - "MOV [W0], W15 \n" \ - "POP W0 \n" /* Restore the critical nesting counter for the task. */ \ - "MOV W0, _uxCriticalNesting \n" \ - "POP PSVPAG \n" \ - "POP CORCON \n" \ - "POP DOENDH \n" \ - "POP DOENDL \n" \ - "POP DOSTARTH \n" \ - "POP DOSTARTL \n" \ - "POP DCOUNT \n" \ - "POP ACCBU \n" \ - "POP ACCBH \n" \ - "POP ACCBL \n" \ - "POP ACCAU \n" \ - "POP ACCAH \n" \ - "POP ACCAL \n" \ - "POP TBLPAG \n" \ - "POP RCOUNT \n" /* Restore the registers from the stack. */ \ - "POP W14 \n" \ - "POP.D W12 \n" \ - "POP.D W10 \n" \ - "POP.D W8 \n" \ - "POP.D W6 \n" \ - "POP.D W4 \n" \ - "POP.D W2 \n" \ - "POP.D W0 \n" \ - "POP SR " ); - - - #define portSAVE_CONTEXT() \ - asm volatile( "PUSH SR \n" /* Save the SR used by the task.... */ \ - "PUSH W0 \n" /* ....then disable interrupts. */ \ - "MOV #224, W0 \n" \ - "MOV W0, SR \n" \ - "PUSH W1 \n" /* Save registers to the stack. */ \ - "PUSH.D W2 \n" \ - "PUSH.D W4 \n" \ - "PUSH.D W6 \n" \ - "PUSH.D W8 \n" \ - "PUSH.D W10 \n" \ - "PUSH.D W12 \n" \ - "PUSH W14 \n" \ - "PUSH RCOUNT \n" \ - "PUSH TBLPAG \n" \ - "PUSH ACCAL \n" \ - "PUSH ACCAH \n" \ - "PUSH ACCAU \n" \ - "PUSH ACCBL \n" \ - "PUSH ACCBH \n" \ - "PUSH ACCBU \n" \ - "PUSH DCOUNT \n" \ - "PUSH DOSTARTL \n" \ - "PUSH DOSTARTH \n" \ - "PUSH DOENDL \n" \ - "PUSH DOENDH \n" \ - "PUSH CORCON \n" \ - "PUSH PSVPAG \n" \ - "MOV _uxCriticalNesting, W0 \n" /* Save the critical nesting counter for the task. */ \ - "PUSH W0 \n" \ - "MOV _pxCurrentTCB, W0 \n" /* Save the new top of stack into the TCB. */ \ - "MOV W15, [W0] " ); - -#endif /* MPLAB_DSPIC_PORT */ - -/* - * Setup the timer used to generate the tick interrupt. - */ -static void prvSetupTimerInterrupt( void ); - -/* - * See header file for description. - */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) -{ -unsigned portSHORT usCode; -portBASE_TYPE i; - -const portSTACK_TYPE xInitialStack[] = -{ - 0x1111, /* W1 */ - 0x2222, /* W2 */ - 0x3333, /* W3 */ - 0x4444, /* W4 */ - 0x5555, /* W5 */ - 0x6666, /* W6 */ - 0x7777, /* W7 */ - 0x8888, /* W8 */ - 0x9999, /* W9 */ - 0xaaaa, /* W10 */ - 0xbbbb, /* W11 */ - 0xcccc, /* W12 */ - 0xdddd, /* W13 */ - 0xeeee, /* W14 */ - 0xcdce, /* RCOUNT */ - 0xabac, /* TBLPAG */ - - /* dsPIC specific registers. */ - #ifdef MPLAB_DSPIC_PORT - 0x0202, /* ACCAL */ - 0x0303, /* ACCAH */ - 0x0404, /* ACCAU */ - 0x0505, /* ACCBL */ - 0x0606, /* ACCBH */ - 0x0707, /* ACCBU */ - 0x0808, /* DCOUNT */ - 0x090a, /* DOSTARTL */ - 0x1010, /* DOSTARTH */ - 0x1110, /* DOENDL */ - 0x1212, /* DOENDH */ - #endif -}; - - /* Setup the stack as if a yield had occurred. - - Save the low bytes of the program counter. */ - usCode = ( unsigned portSHORT ) pxCode; - *pxTopOfStack = ( portSTACK_TYPE ) usCode; - pxTopOfStack++; - - /* Save the high byte of the program counter. This will always be zero - here as it is passed in a 16bit pointer. If the address is greater than - 16 bits then the pointer will point to a jump table. */ - *pxTopOfStack = ( portSTACK_TYPE ) 0; - pxTopOfStack++; - - /* Status register with interrupts enabled. */ - *pxTopOfStack = portINITIAL_SR; - pxTopOfStack++; - - /* Parameters are passed in W0. */ - *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; - pxTopOfStack++; - - for( i = 0; i < ( sizeof( xInitialStack ) / sizeof( portSTACK_TYPE ) ); i++ ) - { - *pxTopOfStack = xInitialStack[ i ]; - pxTopOfStack++; - } - - *pxTopOfStack = CORCON; - pxTopOfStack++; - *pxTopOfStack = PSVPAG; - pxTopOfStack++; - - /* Finally the critical nesting depth. */ - *pxTopOfStack = 0x00; - pxTopOfStack++; - - return pxTopOfStack; -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xPortStartScheduler( void ) -{ - /* Setup a timer for the tick ISR. */ - prvSetupTimerInterrupt(); - - /* Restore the context of the first task to run. */ - portRESTORE_CONTEXT(); - - /* Simulate the end of the yield function. */ - asm volatile ( "return" ); - - /* Should not reach here. */ - return pdTRUE; -} -/*-----------------------------------------------------------*/ - -void vPortEndScheduler( void ) -{ - /* It is unlikely that the scheduler for the PIC port will get stopped - once running. If required disable the tick interrupt here, then return - to xPortStartScheduler(). */ -} -/*-----------------------------------------------------------*/ - -/* - * Manual context switch. This is similar to the tick context switch, - * but does not increment the tick count. It must be identical to the - * tick context switch in how it stores the stack of a task. - */ -void vPortYield( void ) -{ - portSAVE_CONTEXT(); - vTaskSwitchContext(); - portRESTORE_CONTEXT(); -} -/*-----------------------------------------------------------*/ - -/* - * Setup a timer for a regular tick. - */ -static void prvSetupTimerInterrupt( void ) -{ -const unsigned portLONG ulCompareMatch = ( configCPU_CLOCK_HZ / portTIMER_PRESCALE ) / configTICK_RATE_HZ; - - /* Prescale of 8. */ - T1CON = 0; - TMR1 = 0; - - PR1 = ( unsigned portSHORT ) ulCompareMatch; - - /* Setup timer 1 interrupt priority. */ - IPC0bits.T1IP = portKERNEL_INTERRUPT_PRIORITY; - - /* Clear the interrupt as a starting condition. */ - IFS0bits.T1IF = 0; - - /* Enable the interrupt. */ - IEC0bits.T1IE = 1; - - /* Setup the prescale value. */ - T1CONbits.TCKPS0 = 1; - T1CONbits.TCKPS1 = 0; - - /* Start the timer. */ - T1CONbits.TON = 1; -} -/*-----------------------------------------------------------*/ - -void vPortEnterCritical( void ) -{ - portDISABLE_INTERRUPTS(); - uxCriticalNesting++; -} -/*-----------------------------------------------------------*/ - -void vPortExitCritical( void ) -{ - uxCriticalNesting--; - if( uxCriticalNesting == 0 ) - { - portENABLE_INTERRUPTS(); - } -} -/*-----------------------------------------------------------*/ - -void __attribute__((__interrupt__)) _T1Interrupt( void ) -{ - vTaskIncrementTick(); - - /* Clear the timer interrupt. */ - IFS0bits.T1IF = 0; - - #if configUSE_PREEMPTION == 1 - portYIELD(); - #endif -} diff --git a/Source/portable/MPLAB/PIC24_dsPIC/portmacro.h b/Source/portable/MPLAB/PIC24_dsPIC/portmacro.h deleted file mode 100644 index 797dd7b84..000000000 --- a/Source/portable/MPLAB/PIC24_dsPIC/portmacro.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -/*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the - * given hardware and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - -/* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE unsigned short -#define portBASE_TYPE short - -#if( configUSE_16_BIT_TICKS == 1 ) - typedef unsigned portSHORT portTickType; - #define portMAX_DELAY ( portTickType ) 0xffff -#else - typedef unsigned portLONG portTickType; - #define portMAX_DELAY ( portTickType ) 0xffffffff -#endif -/*-----------------------------------------------------------*/ - -/* Hardware specifics. */ -#define portBYTE_ALIGNMENT 2 -#define portSTACK_GROWTH 1 -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) -#define portKERNEL_INTERRUPT_PRIORITY 0x01 -/*-----------------------------------------------------------*/ - -/* Critical section management. */ -#define portINTERRUPT_BITS ( 0x00e0 ) -#define portDISABLE_INTERRUPTS() SR |= portINTERRUPT_BITS -#define portENABLE_INTERRUPTS() SR &= ~portINTERRUPT_BITS - -/* Note that exiting a critical sectino will set the IPL bits to 0, nomatter -what their value was prior to entering the critical section. */ -extern void vPortEnterCritical( void ); -extern void vPortExitCritical( void ); -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() -/*-----------------------------------------------------------*/ - -/* Task utilities. */ -extern void vPortYield( void ); -#define portYIELD() asm volatile ( "CALL _vPortYield \n" \ - "NOP " ); -/*-----------------------------------------------------------*/ - -/* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) -/*-----------------------------------------------------------*/ - -/* Compiler specifics. */ -#define inline - -#define portNOP() asm volatile ( "NOP" ) - -#endif /* PORTMACRO_H */ - diff --git a/Source/portable/MemMang/heap_1.c b/Source/portable/MemMang/heap_1.c deleted file mode 100644 index b99a3fb23..000000000 --- a/Source/portable/MemMang/heap_1.c +++ /dev/null @@ -1,132 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - -Changes between V2.5.1 and V2.5.1 - - + The memory pool has been defined within a struct to ensure correct memory - alignment on 32bit systems. - -Changes between V2.6.1 and V3.0.0 - - + An overflow check has been added to ensure the next free byte variable - does not wrap around. -*/ - - -/* - * The simplest possible implementation of pvPortMalloc(). Note that this - * implementation does NOT allow allocated memory to be freed again. - * - * See heap_2.c and heap_3.c for alternative implementations, and the memory - * management pages of http://www.FreeRTOS.org for more information. - */ -#include -#include "FreeRTOS.h" -#include "task.h" - -/* Setup the correct byte alignment mask for the defined byte alignment. */ -#if portBYTE_ALIGNMENT == 4 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0003 ) -#endif - -#if portBYTE_ALIGNMENT == 2 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0001 ) -#endif - -#if portBYTE_ALIGNMENT == 1 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0000 ) -#endif - -#ifndef heapBYTE_ALIGNMENT_MASK - #error "Invalid portBYTE_ALIGNMENT definition" -#endif - -/* Allocate the memory for the heap. The struct is used to force byte -alignment without using any non-portable code. */ -static struct xRTOS_HEAP -{ - unsigned portLONG ulDummy; - unsigned portCHAR ucHeap[ configTOTAL_HEAP_SIZE ]; -} xHeap; - -static size_t xNextFreeByte = ( size_t ) 0; -/*-----------------------------------------------------------*/ - -void *pvPortMalloc( size_t xWantedSize ) -{ -void *pvReturn = NULL; - - /* Ensure that blocks are always aligned to the required number of bytes. */ - #if portBYTE_ALIGNMENT != 1 - if( xWantedSize & heapBYTE_ALIGNMENT_MASK ) - { - /* Byte alignment required. */ - xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & heapBYTE_ALIGNMENT_MASK ) ); - } - #endif - - vTaskSuspendAll(); - { - /* Check there is enough room left for the allocation. */ - if( ( ( xNextFreeByte + xWantedSize ) < configTOTAL_HEAP_SIZE ) && - ( ( xNextFreeByte + xWantedSize ) > xNextFreeByte ) )/* Check for overflow. */ - { - /* Return the next free byte then increment the index past this - block. */ - pvReturn = &( xHeap.ucHeap[ xNextFreeByte ] ); - xNextFreeByte += xWantedSize; - } - } - xTaskResumeAll(); - - return pvReturn; -} -/*-----------------------------------------------------------*/ - -void vPortFree( void *pv ) -{ - /* Memory cannot be freed using this scheme. See heap_2.c and heap_3.c - for alternative implementations, and the memory management pages of - http://www.FreeRTOS.org for more information. */ - ( void ) pv; -} -/*-----------------------------------------------------------*/ - -void vPortInitialiseBlocks( void ) -{ - /* Only required when static memory is not cleared. */ - xNextFreeByte = ( size_t ) 0; -} - - diff --git a/Source/portable/MemMang/heap_2.c b/Source/portable/MemMang/heap_2.c deleted file mode 100644 index 6be0139e6..000000000 --- a/Source/portable/MemMang/heap_2.c +++ /dev/null @@ -1,236 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * A sample implementation of pvPortMalloc() and vPortFree() that permits - * allocated blocks to be freed, but does not combine adjacent free blocks - * into a single larger block. - * - * See heap_1.c and heap_3.c for alternative implementations, and the memory - * management pages of http://www.FreeRTOS.org for more information. - */ -#include - -#include "FreeRTOS.h" -#include "task.h" - -/* Setup the correct byte alignment mask for the defined byte alignment. */ -#if portBYTE_ALIGNMENT == 4 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0003 ) -#endif - -#if portBYTE_ALIGNMENT == 2 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0001 ) -#endif - -#if portBYTE_ALIGNMENT == 1 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0000 ) -#endif - -#ifndef heapBYTE_ALIGNMENT_MASK - #error "Invalid portBYTE_ALIGNMENT definition" -#endif - -/* Allocate the memory for the heap. The struct is used to force byte -alignment without using any non-portable code. */ -static struct xRTOS_HEAP -{ - unsigned portLONG ulDummy; - unsigned portCHAR ucHeap[ configTOTAL_HEAP_SIZE ]; -} xHeap; - -/* Define the linked list structure. This is used to link free blocks in order -of their size. */ -typedef struct A_BLOCK_LINK -{ - struct A_BLOCK_LINK *pxNextFreeBlock; /*<< The next free block in the list. */ - size_t xBlockSize; /*<< The size of the free block. */ -} xBlockLink; - - -static const unsigned portSHORT heapSTRUCT_SIZE = ( sizeof( xBlockLink ) + ( sizeof( xBlockLink ) % portBYTE_ALIGNMENT ) ); -#define heapMINIMUM_BLOCK_SIZE ( ( size_t ) ( heapSTRUCT_SIZE * 2 ) ) - -/* Create a couple of list links to mark the start and end of the list. */ -static xBlockLink xStart, xEnd; - -/* STATIC FUNCTIONS ARE DEFINED AS MACROS TO MINIMIZE THE FUNCTION CALL DEPTH. */ - -/* - * Insert a block into the list of free blocks - which is ordered by size of - * the block. Small blocks at the start of the list and large blocks at the end - * of the list. - */ -#define prvInsertBlockIntoFreeList( pxBlockToInsert ) \ -{ \ -xBlockLink *pxIterator; \ -size_t xBlockSize; \ - \ - xBlockSize = pxBlockToInsert->xBlockSize; \ - \ - /* Iterate through the list until a block is found that has a larger size */ \ - /* than the block we are inserting. */ \ - for( pxIterator = &xStart; pxIterator->pxNextFreeBlock->xBlockSize < xBlockSize; pxIterator = pxIterator->pxNextFreeBlock ) \ - { \ - /* There is nothing to do here - just iterate to the correct position. */ \ - } \ - \ - /* Update the list to include the block being inserted in the correct */ \ - /* position. */ \ - pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; \ - pxIterator->pxNextFreeBlock = pxBlockToInsert; \ -} -/*-----------------------------------------------------------*/ - -#define prvHeapInit() \ -{ \ -xBlockLink *pxFirstFreeBlock; \ - \ - /* xStart is used to hold a pointer to the first item in the list of free */ \ - /* blocks. The void cast is used to prevent compiler warnings. */ \ - xStart.pxNextFreeBlock = ( void * ) xHeap.ucHeap; \ - xStart.xBlockSize = ( size_t ) 0; \ - \ - /* xEnd is used to mark the end of the list of free blocks. */ \ - xEnd.xBlockSize = configTOTAL_HEAP_SIZE; \ - xEnd.pxNextFreeBlock = NULL; \ - \ - /* To start with there is a single free block that is sized to take up the \ - entire heap space. */ \ - pxFirstFreeBlock = ( void * ) xHeap.ucHeap; \ - pxFirstFreeBlock->xBlockSize = configTOTAL_HEAP_SIZE; \ - pxFirstFreeBlock->pxNextFreeBlock = &xEnd; \ -} -/*-----------------------------------------------------------*/ - -void *pvPortMalloc( size_t xWantedSize ) -{ -xBlockLink *pxBlock, *pxPreviousBlock, *pxNewBlockLink; -static portBASE_TYPE xHeapHasBeenInitialised = pdFALSE; -void *pvReturn = NULL; - - vTaskSuspendAll(); - { - /* If this is the first call to malloc then the heap will require - initialisation to setup the list of free blocks. */ - if( xHeapHasBeenInitialised == pdFALSE ) - { - prvHeapInit(); - xHeapHasBeenInitialised = pdTRUE; - } - - /* The wanted size is increased so it can contain a xBlockLink - structure in addition to the requested amount of bytes. */ - if( xWantedSize > 0 ) - { - xWantedSize += heapSTRUCT_SIZE; - - /* Ensure that blocks are always aligned to the required number of bytes. */ - if( xWantedSize & heapBYTE_ALIGNMENT_MASK ) - { - /* Byte alignment required. */ - xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & heapBYTE_ALIGNMENT_MASK ) ); - } - } - - if( ( xWantedSize > 0 ) && ( xWantedSize < configTOTAL_HEAP_SIZE ) ) - { - /* Blocks are stored in byte order - traverse the list from the start - (smallest) block until one of adequate size is found. */ - pxPreviousBlock = &xStart; - pxBlock = xStart.pxNextFreeBlock; - while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock ) ) - { - pxPreviousBlock = pxBlock; - pxBlock = pxBlock->pxNextFreeBlock; - } - - /* If we found the end marker then a block of adequate size was not found. */ - if( pxBlock != &xEnd ) - { - /* Return the memory space - jumping over the xBlockLink structure - at its start. */ - pvReturn = ( void * ) ( ( ( unsigned portCHAR * ) pxPreviousBlock->pxNextFreeBlock ) + heapSTRUCT_SIZE ); - - /* This block is being returned for use so must be taken our of the - list of free blocks. */ - pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; - - /* If the block is larger than required it can be split into two. */ - if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE ) - { - /* This block is to be split into two. Create a new block - following the number of bytes requested. The void cast is - used to prevent byte alignment warnings from the compiler. */ - pxNewBlockLink = ( void * ) ( ( ( unsigned portCHAR * ) pxBlock ) + xWantedSize ); - - /* Calculate the sizes of two blocks split from the single - block. */ - pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; - pxBlock->xBlockSize = xWantedSize; - - /* Insert the new block into the list of free blocks. */ - prvInsertBlockIntoFreeList( ( pxNewBlockLink ) ); - } - } - } - } - xTaskResumeAll(); - - return pvReturn; -} -/*-----------------------------------------------------------*/ - -void vPortFree( void *pv ) -{ -unsigned portCHAR *puc = ( unsigned portCHAR * ) pv; -xBlockLink *pxLink; - - if( pv ) - { - /* The memory being freed will have an xBlockLink structure immediately - before it. */ - puc -= heapSTRUCT_SIZE; - - /* This casting is to keep the compiler from issuing warnings. */ - pxLink = ( void * ) puc; - - vTaskSuspendAll(); - { - /* Add this block to the list of free blocks. */ - prvInsertBlockIntoFreeList( ( ( xBlockLink * ) pxLink ) ); - } - xTaskResumeAll(); - } -} -/*-----------------------------------------------------------*/ - diff --git a/Source/portable/MemMang/heap_3.c b/Source/portable/MemMang/heap_3.c deleted file mode 100644 index f721f7a85..000000000 --- a/Source/portable/MemMang/heap_3.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/* - * Implementation of pvPortMalloc() and vPortFree() that relies on the - * compilers own malloc() and free() implementations. - * - * This file can only be used if the linker is configured to to generate - * a heap memory area. - * - * See heap_2.c and heap_1.c for alternative implementations, and the memory - * management pages of http://www.FreeRTOS.org for more information. - */ - -#include - -#include "FreeRTOS.h" -#include "task.h" - -/*-----------------------------------------------------------*/ - -void *pvPortMalloc( size_t xWantedSize ) -{ -void *pvReturn; - - vTaskSuspendAll(); - { - pvReturn = malloc( xWantedSize ); - } - xTaskResumeAll(); - - return pvReturn; -} -/*-----------------------------------------------------------*/ - -void vPortFree( void *pv ) -{ - if( pv ) - { - vTaskSuspendAll(); - { - free( pv ); - } - xTaskResumeAll(); - } -} - - - diff --git a/Source/portable/Paradigm/Tern_EE/large_untested/port.c b/Source/portable/Paradigm/Tern_EE/large_untested/port.c deleted file mode 100644 index 85e51ac0c..000000000 --- a/Source/portable/Paradigm/Tern_EE/large_untested/port.c +++ /dev/null @@ -1,220 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the Tern EE 186 - * port. - *----------------------------------------------------------*/ - -/* Library includes. */ -#include -#include - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "portasm.h" - -/* The timer increments every four clocks, hence the divide by 4. */ -#define portTIMER_COMPARE ( unsigned portSHORT ) ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) / ( unsigned portLONG ) 4 ) - -/* From the RDC data sheet. */ -#define portENABLE_TIMER_AND_INTERRUPT ( unsigned portSHORT ) 0xe001 - -/* Interrupt control. */ -#define portEIO_REGISTER 0xff22 -#define portCLEAR_INTERRUPT 0x0008 - -/* Setup the hardware to generate the required tick frequency. */ -static void prvSetupTimerInterrupt( void ); - -/* The ISR used depends on whether the preemptive or cooperative scheduler -is being used. */ -#if( configUSE_PREEMPTION == 1 ) - /* Tick service routine used by the scheduler when preemptive scheduling is - being used. */ - static void __interrupt __far prvPreemptiveTick( void ); -#else - /* Tick service routine used by the scheduler when cooperative scheduling is - being used. */ - static void __interrupt __far prvNonPreemptiveTick( void ); -#endif - -/* Trap routine used by taskYIELD() to manually cause a context switch. */ -static void __interrupt __far prvYieldProcessor( void ); - -/*-----------------------------------------------------------*/ -/* See header file for description. */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) -{ -portSTACK_TYPE DS_Reg = 0; - - /* Place a few bytes of known values on the bottom of the stack. - This is just useful for debugging. */ - - *pxTopOfStack = 0x1111; - pxTopOfStack--; - *pxTopOfStack = 0x2222; - pxTopOfStack--; - *pxTopOfStack = 0x3333; - pxTopOfStack--; - - /* We are going to start the scheduler using a return from interrupt - instruction to load the program counter, so first there would be the - function call with parameters preamble. */ - - *pxTopOfStack = FP_SEG( pvParameters ); - pxTopOfStack--; - *pxTopOfStack = FP_OFF( pvParameters ); - pxTopOfStack--; - *pxTopOfStack = FP_SEG( pxCode ); - pxTopOfStack--; - *pxTopOfStack = FP_OFF( pxCode ); - pxTopOfStack--; - - /* Next the status register and interrupt return address. */ - *pxTopOfStack = portINITIAL_SW; - pxTopOfStack--; - *pxTopOfStack = FP_SEG( pxCode ); - pxTopOfStack--; - *pxTopOfStack = FP_OFF( pxCode ); - pxTopOfStack--; - - /* The remaining registers would be pushed on the stack by our context - switch function. These are loaded with values simply to make debugging - easier. */ - *pxTopOfStack = ( portSTACK_TYPE ) 0xAAAA; /* AX */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xBBBB; /* BX */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xCCCC; /* CX */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xDDDD; /* DX */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xEEEE; /* ES */ - pxTopOfStack--; - - /* We need the true data segment. */ - __asm{ MOV DS_Reg, DS }; - - *pxTopOfStack = DS_Reg; /* DS */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x0123; /* SI */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xDDDD; /* DI */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xBBBB; /* BP */ - - return pxTopOfStack; -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xPortStartScheduler( void ) -{ - /* This is called with interrupts already disabled. */ - - /* Put our manual switch (yield) function on a known - vector. */ - setvect( portSWITCH_INT_NUMBER, prvYieldProcessor ); - - /* Setup the tick interrupt. */ - prvSetupTimerInterrupt(); - - /* Kick off the scheduler by setting up the context of the first task. */ - portFIRST_CONTEXT(); - - /* Should not get here! */ - return pdFALSE; -} -/*-----------------------------------------------------------*/ - -/* The ISR used depends on whether the preemptive or cooperative scheduler -is being used. */ -#if( configUSE_PREEMPTION == 1 ) - static void __interrupt __far prvPreemptiveTick( void ) - { - /* Get the scheduler to update the task states following the tick. */ - vTaskIncrementTick(); - - /* Switch in the context of the next task to be run. */ - portSWITCH_CONTEXT(); - - /* Reset interrupt. */ - outport( portEIO_REGISTER, portCLEAR_INTERRUPT ); - } -#else - static void __interrupt __far prvNonPreemptiveTick( void ) - { - /* Same as preemptive tick, but the cooperative scheduler is being used - so we don't have to switch in the context of the next task. */ - vTaskIncrementTick(); - /* Reset interrupt. */ - outport( portEIO_REGISTER, portCLEAR_INTERRUPT ); - } -#endif -/*-----------------------------------------------------------*/ - -static void __interrupt __far prvYieldProcessor( void ) -{ - /* Switch in the context of the next task to be run. */ - portSWITCH_CONTEXT(); -} -/*-----------------------------------------------------------*/ - -void vPortEndScheduler( void ) -{ - /* Not implemented. */ -} -/*-----------------------------------------------------------*/ - -static void prvSetupTimerInterrupt( void ) -{ -const unsigned portSHORT usTimerACompare = portTIMER_COMPARE, usTimerAMode = portENABLE_TIMER_AND_INTERRUPT; - - #if( configUSE_PREEMPTION == 1 ) - /* Tick service routine used by the scheduler when preemptive scheduling is - being used. */ - t2_init( usTimerAMode, usTimerACompare, prvPreemptiveTick ); - #else - /* Tick service routine used by the scheduler when cooperative scheduling is - being used. */ - t2_init( usTimerAMode, usTimerACompare, prvNonPreemptiveTick ); - #endif -} - - - - - - - diff --git a/Source/portable/Paradigm/Tern_EE/large_untested/portasm.h b/Source/portable/Paradigm/Tern_EE/large_untested/portasm.h deleted file mode 100644 index 56e72b5f5..000000000 --- a/Source/portable/Paradigm/Tern_EE/large_untested/portasm.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -typedef void tskTCB; -extern volatile tskTCB * volatile pxCurrentTCB; -extern void vTaskSwitchContext( void ); - -/* - * Saves the stack pointer for one task into its TCB, calls - * vTaskSwitchContext() to update the TCB being used, then restores the stack - * from the new TCB read to run the task. - */ -void portSWITCH_CONTEXT( void ); - -/* - * Load the stack pointer from the TCB of the task which is going to be first - * to execute. Then force an IRET so the registers and IP are popped off the - * stack. - */ -void portFIRST_CONTEXT( void ); - -#define portSWITCH_CONTEXT() -// asm { mov ax, seg pxCurrentTCB } -// asm { mov ds, ax } -// asm { les bx, pxCurrentTCB } /* Save the stack pointer into the TCB. */ -// asm { mov es:0x2[ bx ], ss } -// asm { mov es:[ bx ], sp } -// asm { call far ptr vTaskSwitchContext } /* Perform the switch. */ -// asm { mov ax, seg pxCurrentTCB } /* Restore the stack pointer from the TCB. */ -// asm { mov ds, ax } -// asm { les bx, dword ptr pxCurrentTCB } -// asm { mov ss, es:[ bx + 2 ] } -// asm { mov sp, es:[ bx ] } - -#define portFIRST_CONTEXT() \ - asm { mov ax, seg pxCurrentTCB } \ - asm { mov ds, ax } \ - asm { les bx, dword ptr pxCurrentTCB } \ - asm { mov ss, es:[ bx + 2 ] } \ - asm { mov sp, es:[ bx ] } \ - asm { pop bx } \ - asm { pop di } \ - asm { pop si } \ - asm { pop ds } \ - asm { pop es } \ - asm { pop dx } \ - asm { pop cx } \ - asm { pop bx } \ - asm { pop ax } \ - asm { iret } - - diff --git a/Source/portable/Paradigm/Tern_EE/large_untested/portmacro.h b/Source/portable/Paradigm/Tern_EE/large_untested/portmacro.h deleted file mode 100644 index c84de0cb3..000000000 --- a/Source/portable/Paradigm/Tern_EE/large_untested/portmacro.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -/*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the - * given hardware and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - -/* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE long -#define portLONG long -#define portSHORT int -#define portSTACK_TYPE unsigned portSHORT -#define portBASE_TYPE portSHORT - -#if( configUSE_16_BIT_TICKS == 1 ) - typedef unsigned portSHORT portTickType; - #define portMAX_DELAY ( portTickType ) 0xffff -#else - typedef unsigned portLONG portTickType; - #define portMAX_DELAY ( portTickType ) 0xffffffff -#endif -/*-----------------------------------------------------------*/ - -/* Critical section handling. */ -#define portENTER_CRITICAL() __asm{ pushf } \ - __asm{ cli } \ - -#define portEXIT_CRITICAL() __asm{ popf } - -#define portDISABLE_INTERRUPTS() __asm{ cli } - -#define portENABLE_INTERRUPTS() __asm{ sti } -/*-----------------------------------------------------------*/ - -/* Hardware specifics. */ -#define portNOP() __asm{ nop } -#define portSTACK_GROWTH ( -1 ) -#define portSWITCH_INT_NUMBER 0x80 -#define portYIELD() __asm{ int portSWITCH_INT_NUMBER } -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 2 -#define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */ -/*-----------------------------------------------------------*/ - -/* Compiler specifics. */ -#define portINPUT_BYTE( xAddr ) inp( xAddr ) -#define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue ) -#define portINPUT_WORD( xAddr ) inpw( xAddr ) -#define portOUTPUT_WORD( xAddr, usValue ) outpw( xAddr, usValue ) -#define inline -/*-----------------------------------------------------------*/ - -/* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters ) -#define portTASK_FUNCTION( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters ) - -#endif /* PORTMACRO_H */ - diff --git a/Source/portable/Paradigm/Tern_EE/small/PORTASM.bak b/Source/portable/Paradigm/Tern_EE/small/PORTASM.bak deleted file mode 100644 index 2355e618b..000000000 --- a/Source/portable/Paradigm/Tern_EE/small/PORTASM.bak +++ /dev/null @@ -1,76 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef PORT_ASM_H -#define PORT_ASM_H - -typedef void tskTCB; -extern volatile tskTCB * volatile pxCurrentTCB; -extern void vTaskSwitchContext( void ); - -/* - * Saves the stack pointer for one task into its TCB, calls - * vTaskSwitchContext() to update the TCB being used, then restores the stack - * from the new TCB read to run the task. - */ -void portSWITCH_CONTEXT( void ); - -/* - * Load the stack pointer from the TCB of the task which is going to be first - * to execute. Then force an IRET so the registers and IP are popped off the - * stack. - */ -void portFIRST_CONTEXT( void ); - -#define portSWITCH_CONTEXT() \ - asm { mov bx, [pxCurrentTCB] } \ - asm { mov word ptr [bx], sp } \ - asm { call far ptr vTaskSwitchContext } \ - asm { mov bx, [pxCurrentTCB] } \ - asm { mov sp, [bx] } - -#define portFIRST_CONTEXT() \ - asm { mov bx, [pxCurrentTCB] } \ - asm { mov sp, [bx] } \ - asm { pop bp } \ - asm { pop di } \ - asm { pop si } \ - asm { pop ds } \ - asm { pop es } \ - asm { pop dx } \ - asm { pop cx } \ - asm { pop bx } \ - asm { pop ax } \ - asm { iret } - - -#endif diff --git a/Source/portable/Paradigm/Tern_EE/small/port.bak b/Source/portable/Paradigm/Tern_EE/small/port.bak deleted file mode 100644 index be47413b2..000000000 --- a/Source/portable/Paradigm/Tern_EE/small/port.bak +++ /dev/null @@ -1,222 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the Tern EE 186 - * port. - *----------------------------------------------------------*/ - -/* Library includes. */ -#include -#include - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "portasm.h" - -/* The timer increments every four clocks, hence the divide by 4. */ -#define portPRESCALE_VALUE ( 16 ) -#define portTIMER_COMPARE ( configCPU_CLOCK_HZ / ( configTICK_RATE_HZ * 4UL ) ) - -/* From the RDC data sheet. */ -#define portENABLE_TIMER_AND_INTERRUPT ( unsigned portSHORT ) 0xe00b -#define portENABLE_TIMER ( unsigned portSHORT ) 0xC001 - -/* Interrupt control. */ -#define portEIO_REGISTER 0xff22 -#define portCLEAR_INTERRUPT 0x0008 - -/* Setup the hardware to generate the required tick frequency. */ -static void prvSetupTimerInterrupt( void ); - -/* The ISR used depends on whether the preemptive or cooperative scheduler -is being used. */ -#if( configUSE_PREEMPTION == 1 ) - /* Tick service routine used by the scheduler when preemptive scheduling is - being used. */ - static void __interrupt __far prvPreemptiveTick( void ); -#else - /* Tick service routine used by the scheduler when cooperative scheduling is - being used. */ - static void __interrupt __far prvNonPreemptiveTick( void ); -#endif - -/* Trap routine used by taskYIELD() to manually cause a context switch. */ -static void __interrupt __far prvYieldProcessor( void ); - -/*-----------------------------------------------------------*/ -/* See header file for description. */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) -{ -portSTACK_TYPE DS_Reg = 0; - - /* We need the true data segment. */ - __asm{ MOV DS_Reg, DS }; - - /* Place a few bytes of known values on the bottom of the stack. - This is just useful for debugging. */ - - *pxTopOfStack = 0x1111; - pxTopOfStack--; - *pxTopOfStack = 0x2222; - pxTopOfStack--; - *pxTopOfStack = 0x3333; - pxTopOfStack--; - - /* We are going to start the scheduler using a return from interrupt - instruction to load the program counter, so first there would be the - function call with parameters preamble. */ - - *pxTopOfStack = FP_OFF( pvParameters ); - pxTopOfStack--; - *pxTopOfStack = FP_OFF( pxCode ); - pxTopOfStack--; - - /* Next the status register and interrupt return address. */ - *pxTopOfStack = portINITIAL_SW; - pxTopOfStack--; - *pxTopOfStack = FP_SEG( pxCode ); - pxTopOfStack--; - *pxTopOfStack = FP_OFF( pxCode ); - pxTopOfStack--; - - /* The remaining registers would be pushed on the stack by our context - switch function. These are loaded with values simply to make debugging - easier. */ - *pxTopOfStack = ( portSTACK_TYPE ) 0xAAAA; /* AX */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xBBBB; /* BX */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xCCCC; /* CX */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xDDDD; /* DX */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xEEEE; /* ES */ - pxTopOfStack--; - - *pxTopOfStack = DS_Reg; /* DS */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x0123; /* SI */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xDDDD; /* DI */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xBBBB; /* BP */ - - return pxTopOfStack; -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xPortStartScheduler( void ) -{ - /* This is called with interrupts already disabled. */ - - /* Put our manual switch (yield) function on a known - vector. */ - setvect( portSWITCH_INT_NUMBER, prvYieldProcessor ); - - /* Setup the tick interrupt. */ - prvSetupTimerInterrupt(); - - /* Kick off the scheduler by setting up the context of the first task. */ - portFIRST_CONTEXT(); - - /* Should not get here! */ - return pdFALSE; -} -/*-----------------------------------------------------------*/ - -/* The ISR used depends on whether the preemptive or cooperative scheduler -is being used. */ -#if( configUSE_PREEMPTION == 1 ) - static void __interrupt __far prvPreemptiveTick( void ) - { - /* Get the scheduler to update the task states following the tick. */ - vTaskIncrementTick(); - - /* Switch in the context of the next task to be run. */ - portEND_SWITCHING_ISR(); - - /* Reset interrupt. */ - outport( portEIO_REGISTER, portCLEAR_INTERRUPT ); - } -#else - static void __interrupt __far prvNonPreemptiveTick( void ) - { - /* Same as preemptive tick, but the cooperative scheduler is being used - so we don't have to switch in the context of the next task. */ - vTaskIncrementTick(); - /* Reset interrupt. */ - outport( portEIO_REGISTER, portCLEAR_INTERRUPT ); - } -#endif -/*-----------------------------------------------------------*/ - -static void __interrupt __far prvYieldProcessor( void ) -{ - /* Switch in the context of the next task to be run. */ - portEND_SWITCHING_ISR(); -} -/*-----------------------------------------------------------*/ - -void vPortEndScheduler( void ) -{ - /* Not implemented. */ -} -/*-----------------------------------------------------------*/ - -static void prvSetupTimerInterrupt( void ) -{ -const unsigned portLONG ulCompareValue = portTIMER_COMPARE; -unsigned portSHORT usTimerCompare; - - usTimerCompare = ( unsigned portSHORT ) ( ulCompareValue >> 4UL ); - t2_init( portENABLE_TIMER, portPRESCALE_VALUE, NULL ); - - #if( configUSE_PREEMPTION == 1 ) - /* Tick service routine used by the scheduler when preemptive scheduling is - being used. */ - t1_init( portENABLE_TIMER_AND_INTERRUPT, usTimerCompare, usTimerCompare, prvPreemptiveTick ); - #else - /* Tick service routine used by the scheduler when cooperative scheduling is - being used. */ - t1_init( portENABLE_TIMER_AND_INTERRUPT, usTimerCompare, usTimerCompare, prvNonPreemptiveTick ); - #endif -} - - - - - - - diff --git a/Source/portable/Paradigm/Tern_EE/small/port.c b/Source/portable/Paradigm/Tern_EE/small/port.c deleted file mode 100644 index f8771c455..000000000 --- a/Source/portable/Paradigm/Tern_EE/small/port.c +++ /dev/null @@ -1,222 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the Tern EE 186 - * port. - *----------------------------------------------------------*/ - -/* Library includes. */ -#include -#include - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "portasm.h" - -/* The timer increments every four clocks, hence the divide by 4. */ -#define portPRESCALE_VALUE ( 16 ) -#define portTIMER_COMPARE ( configCPU_CLOCK_HZ / ( configTICK_RATE_HZ * 4UL ) ) - -/* From the RDC data sheet. */ -#define portENABLE_TIMER_AND_INTERRUPT ( unsigned portSHORT ) 0xe00b -#define portENABLE_TIMER ( unsigned portSHORT ) 0xC001 - -/* Interrupt control. */ -#define portEIO_REGISTER 0xff22 -#define portCLEAR_INTERRUPT 0x0008 - -/* Setup the hardware to generate the required tick frequency. */ -static void prvSetupTimerInterrupt( void ); - -/* The ISR used depends on whether the preemptive or cooperative scheduler -is being used. */ -#if( configUSE_PREEMPTION == 1 ) - /* Tick service routine used by the scheduler when preemptive scheduling is - being used. */ - static void __interrupt __far prvPreemptiveTick( void ); -#else - /* Tick service routine used by the scheduler when cooperative scheduling is - being used. */ - static void __interrupt __far prvNonPreemptiveTick( void ); -#endif - -/* Trap routine used by taskYIELD() to manually cause a context switch. */ -static void __interrupt __far prvYieldProcessor( void ); - -/*-----------------------------------------------------------*/ -/* See header file for description. */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) -{ -portSTACK_TYPE DS_Reg = 0; - - /* We need the true data segment. */ - __asm{ MOV DS_Reg, DS }; - - /* Place a few bytes of known values on the bottom of the stack. - This is just useful for debugging. */ - - *pxTopOfStack = 0x1111; - pxTopOfStack--; - *pxTopOfStack = 0x2222; - pxTopOfStack--; - *pxTopOfStack = 0x3333; - pxTopOfStack--; - - /* We are going to start the scheduler using a return from interrupt - instruction to load the program counter, so first there would be the - function call with parameters preamble. */ - - *pxTopOfStack = FP_OFF( pvParameters ); - pxTopOfStack--; - *pxTopOfStack = FP_OFF( pxCode ); - pxTopOfStack--; - - /* Next the status register and interrupt return address. */ - *pxTopOfStack = portINITIAL_SW; - pxTopOfStack--; - *pxTopOfStack = FP_SEG( pxCode ); - pxTopOfStack--; - *pxTopOfStack = FP_OFF( pxCode ); - pxTopOfStack--; - - /* The remaining registers would be pushed on the stack by our context - switch function. These are loaded with values simply to make debugging - easier. */ - *pxTopOfStack = ( portSTACK_TYPE ) 0xAAAA; /* AX */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xBBBB; /* BX */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xCCCC; /* CX */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xDDDD; /* DX */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xEEEE; /* ES */ - pxTopOfStack--; - - *pxTopOfStack = DS_Reg; /* DS */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x0123; /* SI */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xDDDD; /* DI */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xBBBB; /* BP */ - - return pxTopOfStack; -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xPortStartScheduler( void ) -{ - /* This is called with interrupts already disabled. */ - - /* Put our manual switch (yield) function on a known - vector. */ - setvect( portSWITCH_INT_NUMBER, prvYieldProcessor ); - - /* Setup the tick interrupt. */ - prvSetupTimerInterrupt(); - - /* Kick off the scheduler by setting up the context of the first task. */ - portFIRST_CONTEXT(); - - /* Should not get here! */ - return pdFALSE; -} -/*-----------------------------------------------------------*/ - -/* The ISR used depends on whether the preemptive or cooperative scheduler -is being used. */ -#if( configUSE_PREEMPTION == 1 ) - static void __interrupt __far prvPreemptiveTick( void ) - { - /* Get the scheduler to update the task states following the tick. */ - vTaskIncrementTick(); - - /* Switch in the context of the next task to be run. */ - portEND_SWITCHING_ISR(); - - /* Reset interrupt. */ - outport( portEIO_REGISTER, portCLEAR_INTERRUPT ); - } -#else - static void __interrupt __far prvNonPreemptiveTick( void ) - { - /* Same as preemptive tick, but the cooperative scheduler is being used - so we don't have to switch in the context of the next task. */ - vTaskIncrementTick(); - /* Reset interrupt. */ - outport( portEIO_REGISTER, portCLEAR_INTERRUPT ); - } -#endif -/*-----------------------------------------------------------*/ - -static void __interrupt __far prvYieldProcessor( void ) -{ - /* Switch in the context of the next task to be run. */ - portEND_SWITCHING_ISR(); -} -/*-----------------------------------------------------------*/ - -void vPortEndScheduler( void ) -{ - /* Not implemented. */ -} -/*-----------------------------------------------------------*/ - -static void prvSetupTimerInterrupt( void ) -{ -const unsigned portLONG ulCompareValue = portTIMER_COMPARE; -unsigned portSHORT usTimerCompare; - - usTimerCompare = ( unsigned portSHORT ) ( ulCompareValue >> 4 ); - t2_init( portENABLE_TIMER, portPRESCALE_VALUE, NULL ); - - #if( configUSE_PREEMPTION == 1 ) - /* Tick service routine used by the scheduler when preemptive scheduling is - being used. */ - t1_init( portENABLE_TIMER_AND_INTERRUPT, usTimerCompare, usTimerCompare, prvPreemptiveTick ); - #else - /* Tick service routine used by the scheduler when cooperative scheduling is - being used. */ - t1_init( portENABLE_TIMER_AND_INTERRUPT, usTimerCompare, usTimerCompare, prvNonPreemptiveTick ); - #endif -} - - - - - - - diff --git a/Source/portable/Paradigm/Tern_EE/small/portasm.h b/Source/portable/Paradigm/Tern_EE/small/portasm.h deleted file mode 100644 index eca88dbaf..000000000 --- a/Source/portable/Paradigm/Tern_EE/small/portasm.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef PORT_ASM_H -#define PORT_ASM_H - -typedef void tskTCB; -extern volatile tskTCB * volatile pxCurrentTCB; -extern void vTaskSwitchContext( void ); - -/* - * Saves the stack pointer for one task into its TCB, calls - * vTaskSwitchContext() to update the TCB being used, then restores the stack - * from the new TCB read to run the task. - */ -void portEND_SWITCHING_ISR( void ); - -/* - * Load the stack pointer from the TCB of the task which is going to be first - * to execute. Then force an IRET so the registers and IP are popped off the - * stack. - */ -void portFIRST_CONTEXT( void ); - -#define portEND_SWITCHING_ISR() \ - asm { mov bx, [pxCurrentTCB] } \ - asm { mov word ptr [bx], sp } \ - asm { call far ptr vTaskSwitchContext } \ - asm { mov bx, [pxCurrentTCB] } \ - asm { mov sp, [bx] } - -#define portFIRST_CONTEXT() \ - asm { mov bx, [pxCurrentTCB] } \ - asm { mov sp, [bx] } \ - asm { pop bp } \ - asm { pop di } \ - asm { pop si } \ - asm { pop ds } \ - asm { pop es } \ - asm { pop dx } \ - asm { pop cx } \ - asm { pop bx } \ - asm { pop ax } \ - asm { iret } - - -#endif - diff --git a/Source/portable/Paradigm/Tern_EE/small/portmacro.h b/Source/portable/Paradigm/Tern_EE/small/portmacro.h deleted file mode 100644 index 65a57577e..000000000 --- a/Source/portable/Paradigm/Tern_EE/small/portmacro.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -/*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the - * given hardware and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - -/* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE long -#define portLONG long -#define portSHORT int -#define portSTACK_TYPE unsigned portSHORT -#define portBASE_TYPE portSHORT - -typedef void ( __interrupt __far *pxISR )(); - -#if( configUSE_16_BIT_TICKS == 1 ) - typedef unsigned portSHORT portTickType; - #define portMAX_DELAY ( portTickType ) 0xffff -#else - typedef unsigned portLONG portTickType; - #define portMAX_DELAY ( portTickType ) 0xffffffff -#endif -/*-----------------------------------------------------------*/ - -/* Critical section handling. */ -#define portENTER_CRITICAL() __asm{ pushf } \ - __asm{ cli } \ - -#define portEXIT_CRITICAL() __asm{ popf } - -#define portDISABLE_INTERRUPTS() __asm{ cli } - -#define portENABLE_INTERRUPTS() __asm{ sti } -/*-----------------------------------------------------------*/ - -/* Hardware specifics. */ -#define portNOP() __asm{ nop } -#define portSTACK_GROWTH ( -1 ) -#define portSWITCH_INT_NUMBER 0x80 -#define portYIELD() __asm{ int portSWITCH_INT_NUMBER } -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 2 -#define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */ -/*-----------------------------------------------------------*/ - -/* Compiler specifics. */ -#define portINPUT_BYTE( xAddr ) inp( xAddr ) -#define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue ) -#define portINPUT_WORD( xAddr ) inpw( xAddr ) -#define portOUTPUT_WORD( xAddr, usValue ) outpw( xAddr, usValue ) -#define inline -/*-----------------------------------------------------------*/ - -/* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters ) -#define portTASK_FUNCTION( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters ) - -#endif /* PORTMACRO_H */ - diff --git a/Source/portable/RVDS/ARM_CM3/port.c b/Source/portable/RVDS/ARM_CM3/port.c deleted file mode 100644 index e0be09259..000000000 --- a/Source/portable/RVDS/ARM_CM3/port.c +++ /dev/null @@ -1,304 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - Changes between V4.0.0 and V4.0.1 - - + Reduced the code used to setup the initial stack frame. - + The kernel no longer has to install or handle the fault interrupt. -*/ - -/*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the ARM CM3 port. - *----------------------------------------------------------*/ - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Constants required to manipulate the NVIC. */ -#define portNVIC_SYSTICK_CTRL ( ( volatile unsigned portLONG *) 0xe000e010 ) -#define portNVIC_SYSTICK_LOAD ( ( volatile unsigned portLONG *) 0xe000e014 ) -#define portNVIC_INT_CTRL ( ( volatile unsigned portLONG *) 0xe000ed04 ) -#define portNVIC_SYSPRI2 ( ( volatile unsigned portLONG *) 0xe000ed20 ) -#define portNVIC_SYSPRI1 ( ( volatile unsigned portLONG *) 0xe000ed1c ) -#define portNVIC_HARD_FAULT_STATUS 0xe000ed2c -#define portNVIC_FORCED_FAULT_BIT 0x40000000 -#define portNVIC_SYSTICK_CLK 0x00000004 -#define portNVIC_SYSTICK_INT 0x00000002 -#define portNVIC_SYSTICK_ENABLE 0x00000001 -#define portNVIC_PENDSVSET 0x10000000 -#define portNVIC_PENDSV_PRI 0x00ff0000 -#define portNVIC_SVCALL_PRI 0xff000000 -#define portNVIC_SYSTICK_PRI 0xff000000 - -/* Constants required to set up the initial stack. */ -#define portINITIAL_XPSR ( 0x01000000 ) - -/* Each task maintains its own interrupt status in the critical nesting -variable. */ -unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa; - -/* Constant hardware definitions to assist asm code. */ -const unsigned long ulHardFaultStatus = portNVIC_HARD_FAULT_STATUS; -const unsigned long ulNVICIntCtrl = ( unsigned long ) 0xe000ed04; -const unsigned long ulForceFaultBit = portNVIC_FORCED_FAULT_BIT; -const unsigned long ulPendSVBit = portNVIC_PENDSVSET; - -/* - * Setup the timer to generate the tick interrupts. - */ -static void prvSetupTimerInterrupt( void ); - -/* - * Set the MSP/PSP to a known value. - */ -void prvSetMSP( unsigned long ulValue ); -void prvSetPSP( unsigned long ulValue ); - -/*-----------------------------------------------------------*/ - -/* - * See header file for description. - */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) -{ - /* Simulate the stack frame as it would be created by a context switch - interrupt. */ - *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* PC */ - pxTopOfStack--; - *pxTopOfStack = 0xfffffffd; /* LR */ - pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ - *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ - pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ - *pxTopOfStack = 0x00000000; /* uxCriticalNesting. */ - - return pxTopOfStack; -} -/*-----------------------------------------------------------*/ - -__asm void prvSetPSP( unsigned long ulValue ) -{ - PRESERVE8 - msr psp, r0 - bx lr; -} -/*-----------------------------------------------------------*/ - -__asm void prvSetMSP( unsigned long ulValue ) -{ - PRESERVE8 - msr msp, r0 - bx lr; -} -/*-----------------------------------------------------------*/ - -/* - * See header file for description. - */ -portBASE_TYPE xPortStartScheduler( void ) -{ - /* Start the timer that generates the tick ISR. Interrupts are disabled - here already. */ - prvSetupTimerInterrupt(); - - /* Make PendSV, CallSV and SysTick the lowest priority interrupts. */ - *(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI; - *(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI; - *(portNVIC_SYSPRI1) |= portNVIC_SVCALL_PRI; - - /* Start the first task. */ - prvSetPSP( 0 ); - prvSetMSP( *((unsigned portLONG *) 0 ) ); - *(portNVIC_INT_CTRL) |= portNVIC_PENDSVSET; - - /* Enable interrupts */ - portENABLE_INTERRUPTS(); - - /* Should not get here! */ - return 0; -} -/*-----------------------------------------------------------*/ - -void vPortEndScheduler( void ) -{ - /* It is unlikely that the CM3 port will require this function as there - is nothing to return to. */ -} -/*-----------------------------------------------------------*/ - -void vPortYieldFromISR( void ) -{ - /* Set a PendSV to request a context switch. */ - *(portNVIC_INT_CTRL) |= portNVIC_PENDSVSET; - portENABLE_INTERRUPTS(); -} -/*-----------------------------------------------------------*/ - -__asm void vPortDisableInterrupts( void ) -{ - PRESERVE8 - cpsid i; - bx lr; -} -/*-----------------------------------------------------------*/ - -__asm void vPortEnableInterrupts( void ) -{ - PRESERVE8 - cpsie i; - bx lr; -} -/*-----------------------------------------------------------*/ - -void vPortEnterCritical( void ) -{ - vPortDisableInterrupts(); - uxCriticalNesting++; -} -/*-----------------------------------------------------------*/ - -void vPortExitCritical( void ) -{ - uxCriticalNesting--; - if( uxCriticalNesting == 0 ) - { - vPortEnableInterrupts(); - } -} -/*-----------------------------------------------------------*/ - -__asm void xPortPendSVHandler( void ) -{ - extern uxCriticalNesting; - extern pxCurrentTCB; - extern vTaskSwitchContext; - - PRESERVE8 - - /* Start first task if the stack has not yet been setup. */ - mrs r0, psp - cbz r0, no_save - - /* Save the context into the TCB. */ - sub r0, #0x20 - stm r0, {r4-r11} - sub r0, #0x04 - ldr r1, =uxCriticalNesting - ldr r1, [r1] - stm r0, {r1} - ldr r1, =pxCurrentTCB - ldr r1, [r1] - str r0, [r1] - -no_save; - - /* Find the task to execute. */ - ldr r0, =vTaskSwitchContext - push {r14} - cpsid i - blx r0 - cpsie i - pop {r14} - - /* Restore the context. */ - ldr r1, =pxCurrentTCB - ldr r1, [r1]; - ldr r0, [r1]; - ldm r0, {r1, r4-r11} - ldr r2, =uxCriticalNesting - str r1, [r2] - ldr r2, [r2] - add r0, #0x24 - msr psp, r0 - orr r14, #0xd - - /* Exit with interrupts in the state required by the task. */ - cbnz r2, sv_disable_interrupts - - bx r14 - -sv_disable_interrupts; - cpsid i - bx r14 -} -/*-----------------------------------------------------------*/ - -__asm void xPortSysTickHandler( void ) -{ - extern vTaskIncrementTick - PRESERVE8 - - /* Call the scheduler tick function. */ - ldr r0, =vTaskIncrementTick - push {r14} - cpsid i - blx r0 - cpsie i - pop {r14} - - /* If using preemption, also force a context switch. */ - #if configUSE_PREEMPTION == 1 - extern vPortYieldFromISR - push {r14} - ldr r0, =vPortYieldFromISR - blx r0 - pop {r14} - #endif - - /* Exit with interrupts in the correct state. */ - ldr r2, =uxCriticalNesting - ldr r2, [r2] - cbnz r2, tick_disable_interrupts - - bx r14 - -tick_disable_interrupts; - cpsid i - bx r14 -} -/*-----------------------------------------------------------*/ - -/* - * Setup the systick timer to generate the tick interrupts at the required - * frequency. - */ -void prvSetupTimerInterrupt( void ) -{ - /* Configure SysTick to interrupt at the requested rate. */ - *(portNVIC_SYSTICK_LOAD) = configCPU_CLOCK_HZ / configTICK_RATE_HZ; - *(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE; -} - - diff --git a/Source/portable/RVDS/ARM_CM3/portmacro.h b/Source/portable/RVDS/ARM_CM3/portmacro.h deleted file mode 100644 index a2a220e8a..000000000 --- a/Source/portable/RVDS/ARM_CM3/portmacro.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -/*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the - * given hardware and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - -/* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE unsigned portLONG -#define portBASE_TYPE long - -#if( configUSE_16_BIT_TICKS == 1 ) - typedef unsigned portSHORT portTickType; - #define portMAX_DELAY ( portTickType ) 0xffff -#else - typedef unsigned portLONG portTickType; - #define portMAX_DELAY ( portTickType ) 0xffffffff -#endif -/*-----------------------------------------------------------*/ - -/* Architecture specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 4 -/*-----------------------------------------------------------*/ - - -/* Scheduler utilities. */ -extern void vPortYield( void ); -extern void vPortYieldFromISR( void ); - -#define portYIELD() vPortYieldFromISR() -#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vPortYieldFromISR() -/*-----------------------------------------------------------*/ - - -/* Critical section management. */ - -extern void vPortDisableInterrupts( void ); -extern void vPortEnableInterrupts( void ); -extern void vPortEnterCritical( void ); -extern void vPortExitCritical( void ); - -#define portDISABLE_INTERRUPTS() vPortDisableInterrupts() -#define portENABLE_INTERRUPTS() vPortEnableInterrupts() -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() -/*-----------------------------------------------------------*/ - -/* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) - -#define inline -#define portNOP() - -#endif /* PORTMACRO_H */ - diff --git a/Source/portable/Rowley/ARM7/readme.txt b/Source/portable/Rowley/ARM7/readme.txt deleted file mode 100644 index 8d3e87f57..000000000 --- a/Source/portable/Rowley/ARM7/readme.txt +++ /dev/null @@ -1 +0,0 @@ -The Rowley ARM7 demo uses the GCC ARM7 port files. \ No newline at end of file diff --git a/Source/portable/Rowley/MSP430F449/Port1/port.c b/Source/portable/Rowley/MSP430F449/Port1/port.c deleted file mode 100644 index e2140c9e1..000000000 --- a/Source/portable/Rowley/MSP430F449/Port1/port.c +++ /dev/null @@ -1,177 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the MSP430 port. - *----------------------------------------------------------*/ - -/* Constants required for hardware setup. The tick ISR runs off the ACLK, -not the MCLK. */ -#define portACLK_FREQUENCY_HZ ( ( portTickType ) 32768 ) -#define portINITIAL_CRITICAL_NESTING ( ( unsigned portSHORT ) 10 ) -#define portFLAGS_INT_ENABLED ( ( portSTACK_TYPE ) 0x08 ) - -/* We require the address of the pxCurrentTCB variable, but don't want to know -any details of its type. */ -typedef void tskTCB; -extern volatile tskTCB * volatile pxCurrentTCB; - -/* Each task maintains a count of the critical section nesting depth. Each -time a critical section is entered the count is incremented. Each time a -critical section is exited the count is decremented - with interrupts only -being re-enabled if the count is zero. - -usCriticalNesting will get set to zero when the scheduler starts, but must -not be initialised to zero as this will cause problems during the startup -sequence. */ -volatile unsigned portSHORT usCriticalNesting = portINITIAL_CRITICAL_NESTING; -/*-----------------------------------------------------------*/ - - -/* - * Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but - * could have alternatively used the watchdog timer or timer 1. - */ -void prvSetupTimerInterrupt( void ); -/*-----------------------------------------------------------*/ - -/* - * Initialise the stack of a task to look exactly as if a call to - * portSAVE_CONTEXT had been called. - * - * See the header file portable.h. - */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) -{ - /* - Place a few bytes of known values on the bottom of the stack. - This is just useful for debugging and can be included if required. - - *pxTopOfStack = ( portSTACK_TYPE ) 0x1111; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x2222; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x3333; - pxTopOfStack--; - */ - - /* The msp430 automatically pushes the PC then SR onto the stack before - executing an ISR. We want the stack to look just as if this has happened - so place a pointer to the start of the task on the stack first - followed - by the flags we want the task to use when it starts up. */ - *pxTopOfStack = ( portSTACK_TYPE ) pxCode; - pxTopOfStack--; - *pxTopOfStack = portFLAGS_INT_ENABLED; - pxTopOfStack--; - - /* Next the general purpose registers. */ - *pxTopOfStack = ( portSTACK_TYPE ) 0x4444; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x5555; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x6666; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x7777; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x8888; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x9999; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaa; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xbbbb; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xcccc; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xdddd; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xeeee; - pxTopOfStack--; - - /* When the task starts is will expect to find the function parameter in - R15. */ - *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; - pxTopOfStack--; - - /* A variable is used to keep track of the critical section nesting. - This variable has to be stored as part of the task context and is - initially set to zero. */ - *pxTopOfStack = ( portSTACK_TYPE ) portNO_CRITICAL_SECTION_NESTING; - - /* Return a pointer to the top of the stack we have generated so this can - be stored in the task control block for the task. */ - return pxTopOfStack; -} -/*-----------------------------------------------------------*/ - -void vPortEndScheduler( void ) -{ - /* It is unlikely that the MSP430 port will get stopped. If required simply - disable the tick interrupt here. */ -} -/*-----------------------------------------------------------*/ - -/* - * Hardware initialisation to generate the RTOS tick. This uses timer 0 - * but could alternatively use the watchdog timer or timer 1. - */ -void prvSetupTimerInterrupt( void ) -{ - /* Ensure the timer is stopped. */ - TACTL = 0; - - /* Run the timer of the ACLK. */ - TACTL = TASSEL_1; - - /* Clear everything to start with. */ - TACTL |= TACLR; - - /* Set the compare match value according to the tick rate we want. */ - TACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ; - - /* Enable the interrupts. */ - TACCTL0 = CCIE; - - /* Start up clean. */ - TACTL |= TACLR; - - /* Up mode. */ - TACTL |= MC_1; -} -/*-----------------------------------------------------------*/ - - - diff --git a/Source/portable/Rowley/MSP430F449/Port1/portext.asm b/Source/portable/Rowley/MSP430F449/Port1/portext.asm deleted file mode 100644 index 4bf0aeb06..000000000 --- a/Source/portable/Rowley/MSP430F449/Port1/portext.asm +++ /dev/null @@ -1,116 +0,0 @@ -#include "FreeRTOSConfig.h" - -portSAVE_CONTEXT macro - push r4 - push r5 - push r6 - push r7 - push r8 - push r9 - push r10 - push r11 - push r12 - push r13 - push r14 - push r15 - mov.w &_usCriticalNesting, r14 - push r14 - mov.w &_pxCurrentTCB, r12 - mov.w r1, @r12 - endm -/*-----------------------------------------------------------*/ - -portRESTORE_CONTEXT macro - mov.w &_pxCurrentTCB, r12 - mov.w @r12, r1 - pop r15 - mov.w r15, &_usCriticalNesting - pop r15 - pop r14 - pop r13 - pop r12 - pop r11 - pop r10 - pop r9 - pop r8 - pop r7 - pop r6 - pop r5 - pop r4 - reti - endm -/*-----------------------------------------------------------*/ - - -.CODE - -/* - * The RTOS tick ISR. - * - * If the cooperative scheduler is in use this simply increments the tick - * count. - * - * If the preemptive scheduler is in use a context switch can also occur. - */ -_vTickISR: - portSAVE_CONTEXT - - call #_vTaskIncrementTick - - #if configUSE_PREEMPTION == 1 - call #_vTaskSwitchContext - #endif - - portRESTORE_CONTEXT -/*-----------------------------------------------------------*/ - - -/* - * Manual context switch called by the portYIELD() macro. - */ -_vPortYield:: - - /* Mimic an interrupt by pushing the SR. */ - push SR - - /* Now the SR is stacked we can disable interrupts. */ - dint - - /* Save the context of the current task. */ - portSAVE_CONTEXT - - /* Switch to the highest priority task that is ready to run. */ - call #_vTaskSwitchContext - - /* Restore the context of the new task. */ - portRESTORE_CONTEXT -/*-----------------------------------------------------------*/ - - -/* - * Start off the scheduler by initialising the RTOS tick timer, then restoring - * the context of the first task. - */ -_xPortStartScheduler:: - - /* Setup the hardware to generate the tick. Interrupts are disabled - when this function is called. */ - call #_prvSetupTimerInterrupt - - /* Restore the context of the first task that is going to run. */ - portRESTORE_CONTEXT -/*-----------------------------------------------------------*/ - - - /* Place the tick ISR in the correct vector. */ - .VECTORS - - .KEEP - - ORG TIMERA0_VECTOR - DW _vTickISR - - - - END - diff --git a/Source/portable/Rowley/MSP430F449/Port1/portmacro.h b/Source/portable/Rowley/MSP430F449/Port1/portmacro.h deleted file mode 100644 index c9cb03624..000000000 --- a/Source/portable/Rowley/MSP430F449/Port1/portmacro.h +++ /dev/null @@ -1,134 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -/*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the - * given hardware and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - -/* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT int -#define portSTACK_TYPE unsigned portSHORT -#define portBASE_TYPE portSHORT - -#if( configUSE_16_BIT_TICKS == 1 ) - typedef unsigned portSHORT portTickType; - #define portMAX_DELAY ( portTickType ) 0xffff -#else - typedef unsigned portLONG portTickType; - #define portMAX_DELAY ( portTickType ) 0xffffffff -#endif - -/*-----------------------------------------------------------*/ - -/* Interrupt control macros. */ -#define portDISABLE_INTERRUPTS() _DINT(); -#define portENABLE_INTERRUPTS() _EINT(); -/*-----------------------------------------------------------*/ - -/* Critical section control macros. */ -#define portNO_CRITICAL_SECTION_NESTING ( ( unsigned portSHORT ) 0 ) - -#define portENTER_CRITICAL() \ -{ \ -extern volatile unsigned portSHORT usCriticalNesting; \ - \ - portDISABLE_INTERRUPTS(); \ - \ - /* Now interrupts are disabled usCriticalNesting can be accessed */ \ - /* directly. Increment ulCriticalNesting to keep a count of how many */ \ - /* times portENTER_CRITICAL() has been called. */ \ - usCriticalNesting++; \ -} - -#define portEXIT_CRITICAL() \ -{ \ -extern volatile unsigned portSHORT usCriticalNesting; \ - \ - if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ - { \ - /* Decrement the nesting count as we are leaving a critical section. */ \ - usCriticalNesting--; \ - \ - /* If the nesting level has reached zero then interrupts should be */ \ - /* re-enabled. */ \ - if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ - { \ - portENABLE_INTERRUPTS(); \ - } \ - } \ -} -/*-----------------------------------------------------------*/ - -/* Task utilities. */ - -/* - * Manual context switch called by portYIELD or taskYIELD. - */ -extern void vPortYield( void ); -#define portYIELD() vPortYield() -/*-----------------------------------------------------------*/ - -/* Hardware specifics. */ -#define portBYTE_ALIGNMENT 2 -#define portSTACK_GROWTH ( -1 ) -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) -/*-----------------------------------------------------------*/ - -/* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) __toplevel - -/* Compiler specifics. */ -#define inline - -/* Just used by the demo application to indicate which form of interrupt -service routine should be used. See the online port documentation for more -information. */ -#define MSP_ROWLEY_RB_PORT - -#define portNOP() - -#endif /* PORTMACRO_H */ - diff --git a/Source/portable/Rowley/MSP430F449/Port2/port.c b/Source/portable/Rowley/MSP430F449/Port2/port.c deleted file mode 100644 index b32aa914e..000000000 --- a/Source/portable/Rowley/MSP430F449/Port2/port.c +++ /dev/null @@ -1,221 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/* - * Milos Prokic - * - * File adopted from the MSP430 GCC port - * Interrupt handling, xPortStartScheduler, vPortYield, portSAVE_CONTEXT(), portRESTORE_CONTEXT() -/* Standard includes. */ - -#include - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the MSP430 port. - *----------------------------------------------------------*/ - -/* Constants required for hardware setup. The tick ISR runs off the ACLK, -not the MCLK. */ -#define portACLK_FREQUENCY_HZ ( ( portTickType ) 32768 ) -#define portINITIAL_CRITICAL_NESTING ( ( unsigned portSHORT ) 10 ) -#define portFLAGS_INT_ENABLED ( ( portSTACK_TYPE ) 0x08 ) - -/* We require the address of the pxCurrentTCB variable, but don't want to know -any details of its type. */ -typedef void tskTCB; -extern volatile tskTCB * volatile pxCurrentTCB; - -unsigned portCHAR ucReschedule; - -/* Each task maintains a count of the critical section nesting depth. Each -time a critical section is entered the count is incremented. Each time a -critical section is exited the count is decremented - with interrupts only -being re-enabled if the count is zero. - -usCriticalNesting will get set to zero when the scheduler starts, but must -not be initialised to zero as this will cause problems during the startup -sequence. */ -volatile unsigned portSHORT usCriticalNesting = portINITIAL_CRITICAL_NESTING; -/*-----------------------------------------------------------*/ - -/* - * Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but - * could have alternatively used the watchdog timer or timer 1. - */ -void prvSetupTimerInterrupt( void ); -/*-----------------------------------------------------------*/ - -/* - * Initialise the stack of a task to look exactly as if a call to - * portSAVE_CONTEXT had been called. - * - * See the header file portable.h. - */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) -{ - /* - Place a few bytes of known values on the bottom of the stack. - This is just useful for debugging and can be included if required. - - *pxTopOfStack = ( portSTACK_TYPE ) 0x1111; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x2222; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x3333; - pxTopOfStack--; - */ - - /* The msp430 automatically pushes the PC then SR onto the stack before - executing an ISR. We want the stack to look just as if this has happened - so place a pointer to the start of the task on the stack first - followed - by the flags we want the task to use when it starts up. */ - *pxTopOfStack = ( portSTACK_TYPE ) pxCode; - pxTopOfStack--; - *pxTopOfStack = portFLAGS_INT_ENABLED; - pxTopOfStack--; - - /* Next the general purpose registers. */ - *pxTopOfStack = ( portSTACK_TYPE ) 0x4444; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x5555; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x6666; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x7777; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x8888; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x9999; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaa; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xbbbb; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xcccc; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xdddd; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xeeee; - pxTopOfStack--; - - /* When the task starts is will expect to find the function parameter in - R15. */ - *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; - pxTopOfStack--; - - /* A variable is used to keep track of the critical section nesting. - This variable has to be stored as part of the task context and is - initially set to zero. */ - *pxTopOfStack = ( portSTACK_TYPE ) portNO_CRITICAL_SECTION_NESTING; - - /* Return a pointer to the top of the stack we have generated so this can - be stored in the task control block for the task. */ - return pxTopOfStack; -} -/*-----------------------------------------------------------*/ - -void vPortEndScheduler( void ) -{ - /* It is unlikely that the MSP430 port will get stopped. If required simply - disable the tick interrupt here. */ -} -/*-----------------------------------------------------------*/ - -/* - * Hardware initialisation to generate the RTOS tick. This uses timer 0 - * but could alternatively use the watchdog timer or timer 1. - */ -void prvSetupTimerInterrupt( void ) -{ - /* Ensure the timer is stopped. */ - TACTL = 0; - - /* Run the timer of the ACLK. */ - TACTL = TASSEL_1; - - /* Clear everything to start with. */ - TACTL |= TACLR; - - /* Set the compare match value according to the tick rate we want. */ - TACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ; - - /* Enable the interrupts. */ - TACCTL0 = CCIE; - - /* Start up clean. */ - TACTL |= TACLR; - - /* Up mode. */ - TACTL |= MC_1; -} -/*-----------------------------------------------------------*/ - -/* - * The interrupt service routine used depends on whether the pre-emptive - * scheduler is being used or not. - */ - -#if configUSE_PREEMPTION == 1 - - /* - * Tick ISR for preemptive scheduler. We can use a naked attribute as - * the context is saved at the start of vPortYieldFromTick(). The tick - * count is incremented after the context is saved. - */ - void ISROsTick( void ) - { - /* Increment the tick count then switch to the highest priority task - that is ready to run. */ - vTaskIncrementTick(); - vTaskSwitchContext(); - } - -#else - - /* - * Tick ISR for the cooperative scheduler. All this does is increment the - * tick count. We don't need to switch context, this can only be done by - * manual calls to taskYIELD(); - */ - void ISROsTick( void ) - { - vTaskIncrementTick(); - } -#endif - - - diff --git a/Source/portable/Rowley/MSP430F449/Port2/portext.asm b/Source/portable/Rowley/MSP430F449/Port2/portext.asm deleted file mode 100644 index 0eb8b6bf3..000000000 --- a/Source/portable/Rowley/MSP430F449/Port2/portext.asm +++ /dev/null @@ -1,147 +0,0 @@ -#include - -/* - * Milos Prokic - */ - -/********************************************************** -All Interrupts should follow the naming convention : ISR"name" and declared -as a normal function in C. - -One must not forget to allocate interrupts below (see the line "MSPINT OsTick" -below for an example). - -By default the ISR will not cause the context switch, but if called in -conjunction with portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR(wakeup), where -wakeup = TRUE upon exit the ISR will force the context switch via the -ucReschedule global variable. -**********************************************************/ -MSPINT macro name -_##name:: - call #_portSAVE_CONTEXT - call #_ISR##name - br #_portSWITCH_EXIT - endm - - -/********************************************************** -API code -**********************************************************/ - - .CODE -_vPortYield:: - /* Mimic an INT call by pushing SR. */ - push SR - /* no INTs !! */ - dint - /* Save the context of the current task. */ - call #_portSAVE_CONTEXT - /* Switch to the highest priority task that is ready to run. */ - call #_vTaskSwitchContext - /* Restore the context of the new task. */ - br #_portSWITCH_EXIT - -_xPortStartScheduler:: - /* Setup the hardware to generate the tick. Interrupts are disabled when - this function is called. */ - call #_prvSetupTimerInterrupt - - /* Restore the context of the first task that is going to run. */ - jmp _portRESTORE_CONTEXT - -_portSAVE_CONTEXT:: - /* Function to save the context. When this function is called the - return address will appear on the stack. This does not need to be - saved so is overwritten by R4 - hence R4 is not saved initially. - - Save the general purpose registers. */ - push R5 - push R6 - push R7 - push R8 - push R9 - push R10 - push R11 - push R12 - push R13 - push R14 - push R15 - - /* Now R10 has been saved we can use it to hold the return address, - which is about to be overwritten. */ - mov 22(R1),R10 - - /* Store R4 where the return address was on the stack. */ - mov R4,22(R1) - - /* Save the critical nesting depth. */ - mov.w &_usCriticalNesting, R14 - push R14 - - /* Finally save the new top of stack. */ - mov.w &_pxCurrentTCB, R12 - mov.w R1, @R12 - - /* No rescheduling by default. */ - mov.b #0,&_ucReschedule - - /* Return using the saved return address. */ - br R10 - - -_portSWITCH_EXIT:: - /* Check ucReschedule to see if a context switch is required. */ - tst.b &_ucReschedule - jz _portRESTORE_CONTEXT - call #_vTaskSwitchContext -_portRESTORE_CONTEXT:: - /* Restore the context in the opposite order to the save. */ - mov.w &_pxCurrentTCB, R12 - mov.w @R12, R1 - pop R15 - mov.w R15, &_usCriticalNesting - pop R15 - pop R14 - pop R13 - pop R12 - pop R11 - pop R10 - pop R9 - pop R8 - pop R7 - pop R6 - pop R5 - pop R4 - reti - - -/********************************************************** -Allocate Interrupts using the MSPINT macro (defined at the top of this file. -ex: MSPINT "name" -**********************************************************/ - - MSPINT OsTick - MSPINT Com1Rx - MSPINT Com1Tx - - -/********************************************************* -Interrupt Vectors -Timer_A0 -ex: PORT1 would look like: -ORG PORT1_VECTOR -DW _"name" -**********************************************************/ - .VECTORS - .KEEP - - ORG TIMERA0_VECTOR - DW _OsTick - - ORG UART1RX_VECTOR - DW _Com1Rx - - ORG UART1TX_VECTOR - DW _Com1Tx - - END diff --git a/Source/portable/Rowley/MSP430F449/Port2/portmacro.h b/Source/portable/Rowley/MSP430F449/Port2/portmacro.h deleted file mode 100644 index cc71d5c02..000000000 --- a/Source/portable/Rowley/MSP430F449/Port2/portmacro.h +++ /dev/null @@ -1,144 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -/*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the - * given hardware and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - -/* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT int -#define portSTACK_TYPE unsigned portSHORT -#define portBASE_TYPE portSHORT - -#if( configUSE_16_BIT_TICKS == 1 ) - typedef unsigned portSHORT portTickType; - #define portMAX_DELAY ( portTickType ) 0xffff -#else - typedef unsigned portLONG portTickType; - #define portMAX_DELAY ( portTickType ) 0xffffffff -#endif -/*-----------------------------------------------------------*/ - -/* Interrupt control macros. */ -#define portDISABLE_INTERRUPTS() _DINT(); -#define portENABLE_INTERRUPTS() _EINT(); -/*-----------------------------------------------------------*/ - -/* Critical section control macros. */ -#define portNO_CRITICAL_SECTION_NESTING ( ( unsigned portSHORT ) 0 ) - -#define portENTER_CRITICAL() \ -{ \ -extern volatile unsigned portSHORT usCriticalNesting; \ - \ - portDISABLE_INTERRUPTS(); \ - \ - /* Now interrupts are disabled ulCriticalNesting can be accessed */ \ - /* directly. Increment ulCriticalNesting to keep a count of how many */ \ - /* times portENTER_CRITICAL() has been called. */ \ - usCriticalNesting++; \ -} - -#define portEXIT_CRITICAL() \ -{ \ -extern volatile unsigned portSHORT usCriticalNesting; \ - \ - if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ - { \ - /* Decrement the nesting count as we are leaving a critical section. */ \ - usCriticalNesting--; \ - \ - /* If the nesting level has reached zero then interrupts should be */ \ - /* re-enabled. */ \ - if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ - { \ - portENABLE_INTERRUPTS(); \ - } \ - } \ -} -/*-----------------------------------------------------------*/ - -/* Task utilities. */ - -/* - * Manual context switch called by portYIELD or taskYIELD. - */ -extern void vPortYield( void ); - -#define portYIELD() vPortYield() -/*-----------------------------------------------------------*/ - -#define portENTER_SWITCHING_ISR() -#define portEXIT_SWITCHING_ISR( SwitchRequired ) \ - { \ - extern unsigned portCHAR ucReschedule; \ - if( SwitchRequired ) \ - { \ - ucReschedule = 1; \ - } \ - } - -/* Hardwware specifics. */ -#define portBYTE_ALIGNMENT 2 -#define portSTACK_GROWTH ( -1 ) -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) -/*-----------------------------------------------------------*/ - -/* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) __toplevel - -/* Compiler specifics. */ -#define inline -#define portNOP() - - -/* Just used by the demo application to indicate which form of interrupt -service routine should be used. See the online port documentation for more -information. */ -#define MSP_ROWLEY_MP_PORT - -#endif /* PORTMACRO_H */ - diff --git a/Source/portable/Rowley/MSP430F449/port.c b/Source/portable/Rowley/MSP430F449/port.c deleted file mode 100644 index e2140c9e1..000000000 --- a/Source/portable/Rowley/MSP430F449/port.c +++ /dev/null @@ -1,177 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the MSP430 port. - *----------------------------------------------------------*/ - -/* Constants required for hardware setup. The tick ISR runs off the ACLK, -not the MCLK. */ -#define portACLK_FREQUENCY_HZ ( ( portTickType ) 32768 ) -#define portINITIAL_CRITICAL_NESTING ( ( unsigned portSHORT ) 10 ) -#define portFLAGS_INT_ENABLED ( ( portSTACK_TYPE ) 0x08 ) - -/* We require the address of the pxCurrentTCB variable, but don't want to know -any details of its type. */ -typedef void tskTCB; -extern volatile tskTCB * volatile pxCurrentTCB; - -/* Each task maintains a count of the critical section nesting depth. Each -time a critical section is entered the count is incremented. Each time a -critical section is exited the count is decremented - with interrupts only -being re-enabled if the count is zero. - -usCriticalNesting will get set to zero when the scheduler starts, but must -not be initialised to zero as this will cause problems during the startup -sequence. */ -volatile unsigned portSHORT usCriticalNesting = portINITIAL_CRITICAL_NESTING; -/*-----------------------------------------------------------*/ - - -/* - * Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but - * could have alternatively used the watchdog timer or timer 1. - */ -void prvSetupTimerInterrupt( void ); -/*-----------------------------------------------------------*/ - -/* - * Initialise the stack of a task to look exactly as if a call to - * portSAVE_CONTEXT had been called. - * - * See the header file portable.h. - */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) -{ - /* - Place a few bytes of known values on the bottom of the stack. - This is just useful for debugging and can be included if required. - - *pxTopOfStack = ( portSTACK_TYPE ) 0x1111; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x2222; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x3333; - pxTopOfStack--; - */ - - /* The msp430 automatically pushes the PC then SR onto the stack before - executing an ISR. We want the stack to look just as if this has happened - so place a pointer to the start of the task on the stack first - followed - by the flags we want the task to use when it starts up. */ - *pxTopOfStack = ( portSTACK_TYPE ) pxCode; - pxTopOfStack--; - *pxTopOfStack = portFLAGS_INT_ENABLED; - pxTopOfStack--; - - /* Next the general purpose registers. */ - *pxTopOfStack = ( portSTACK_TYPE ) 0x4444; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x5555; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x6666; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x7777; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x8888; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x9999; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaa; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xbbbb; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xcccc; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xdddd; - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xeeee; - pxTopOfStack--; - - /* When the task starts is will expect to find the function parameter in - R15. */ - *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; - pxTopOfStack--; - - /* A variable is used to keep track of the critical section nesting. - This variable has to be stored as part of the task context and is - initially set to zero. */ - *pxTopOfStack = ( portSTACK_TYPE ) portNO_CRITICAL_SECTION_NESTING; - - /* Return a pointer to the top of the stack we have generated so this can - be stored in the task control block for the task. */ - return pxTopOfStack; -} -/*-----------------------------------------------------------*/ - -void vPortEndScheduler( void ) -{ - /* It is unlikely that the MSP430 port will get stopped. If required simply - disable the tick interrupt here. */ -} -/*-----------------------------------------------------------*/ - -/* - * Hardware initialisation to generate the RTOS tick. This uses timer 0 - * but could alternatively use the watchdog timer or timer 1. - */ -void prvSetupTimerInterrupt( void ) -{ - /* Ensure the timer is stopped. */ - TACTL = 0; - - /* Run the timer of the ACLK. */ - TACTL = TASSEL_1; - - /* Clear everything to start with. */ - TACTL |= TACLR; - - /* Set the compare match value according to the tick rate we want. */ - TACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ; - - /* Enable the interrupts. */ - TACCTL0 = CCIE; - - /* Start up clean. */ - TACTL |= TACLR; - - /* Up mode. */ - TACTL |= MC_1; -} -/*-----------------------------------------------------------*/ - - - diff --git a/Source/portable/Rowley/MSP430F449/portext.asm b/Source/portable/Rowley/MSP430F449/portext.asm deleted file mode 100644 index 4bf0aeb06..000000000 --- a/Source/portable/Rowley/MSP430F449/portext.asm +++ /dev/null @@ -1,116 +0,0 @@ -#include "FreeRTOSConfig.h" - -portSAVE_CONTEXT macro - push r4 - push r5 - push r6 - push r7 - push r8 - push r9 - push r10 - push r11 - push r12 - push r13 - push r14 - push r15 - mov.w &_usCriticalNesting, r14 - push r14 - mov.w &_pxCurrentTCB, r12 - mov.w r1, @r12 - endm -/*-----------------------------------------------------------*/ - -portRESTORE_CONTEXT macro - mov.w &_pxCurrentTCB, r12 - mov.w @r12, r1 - pop r15 - mov.w r15, &_usCriticalNesting - pop r15 - pop r14 - pop r13 - pop r12 - pop r11 - pop r10 - pop r9 - pop r8 - pop r7 - pop r6 - pop r5 - pop r4 - reti - endm -/*-----------------------------------------------------------*/ - - -.CODE - -/* - * The RTOS tick ISR. - * - * If the cooperative scheduler is in use this simply increments the tick - * count. - * - * If the preemptive scheduler is in use a context switch can also occur. - */ -_vTickISR: - portSAVE_CONTEXT - - call #_vTaskIncrementTick - - #if configUSE_PREEMPTION == 1 - call #_vTaskSwitchContext - #endif - - portRESTORE_CONTEXT -/*-----------------------------------------------------------*/ - - -/* - * Manual context switch called by the portYIELD() macro. - */ -_vPortYield:: - - /* Mimic an interrupt by pushing the SR. */ - push SR - - /* Now the SR is stacked we can disable interrupts. */ - dint - - /* Save the context of the current task. */ - portSAVE_CONTEXT - - /* Switch to the highest priority task that is ready to run. */ - call #_vTaskSwitchContext - - /* Restore the context of the new task. */ - portRESTORE_CONTEXT -/*-----------------------------------------------------------*/ - - -/* - * Start off the scheduler by initialising the RTOS tick timer, then restoring - * the context of the first task. - */ -_xPortStartScheduler:: - - /* Setup the hardware to generate the tick. Interrupts are disabled - when this function is called. */ - call #_prvSetupTimerInterrupt - - /* Restore the context of the first task that is going to run. */ - portRESTORE_CONTEXT -/*-----------------------------------------------------------*/ - - - /* Place the tick ISR in the correct vector. */ - .VECTORS - - .KEEP - - ORG TIMERA0_VECTOR - DW _vTickISR - - - - END - diff --git a/Source/portable/Rowley/MSP430F449/portmacro.h b/Source/portable/Rowley/MSP430F449/portmacro.h deleted file mode 100644 index e38cd8663..000000000 --- a/Source/portable/Rowley/MSP430F449/portmacro.h +++ /dev/null @@ -1,133 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -/*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the - * given hardware and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - -/* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT int -#define portSTACK_TYPE unsigned portSHORT -#define portBASE_TYPE portSHORT - -#if( configUSE_16_BIT_TICKS == 1 ) - typedef unsigned portSHORT portTickType; - #define portMAX_DELAY ( portTickType ) 0xffff -#else - typedef unsigned portLONG portTickType; - #define portMAX_DELAY ( portTickType ) 0xffffffff -#endif - -/*-----------------------------------------------------------*/ - -/* Interrupt control macros. */ -#define portDISABLE_INTERRUPTS() _DINT(); -#define portENABLE_INTERRUPTS() _EINT(); -/*-----------------------------------------------------------*/ - -/* Critical section control macros. */ -#define portNO_CRITICAL_SECTION_NESTING ( ( unsigned portSHORT ) 0 ) - -#define portENTER_CRITICAL() \ -{ \ -extern volatile unsigned portSHORT usCriticalNesting; \ - \ - portDISABLE_INTERRUPTS(); \ - \ - /* Now interrupts are disabled usCriticalNesting can be accessed */ \ - /* directly. Increment ulCriticalNesting to keep a count of how many */ \ - /* times portENTER_CRITICAL() has been called. */ \ - usCriticalNesting++; \ -} - -#define portEXIT_CRITICAL() \ -{ \ -extern volatile unsigned portSHORT usCriticalNesting; \ - \ - if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ - { \ - /* Decrement the nesting count as we are leaving a critical section. */ \ - usCriticalNesting--; \ - \ - /* If the nesting level has reached zero then interrupts should be */ \ - /* re-enabled. */ \ - if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ - { \ - portENABLE_INTERRUPTS(); \ - } \ - } \ -} -/*-----------------------------------------------------------*/ - -/* Task utilities. */ - -/* - * Manual context switch called by portYIELD or taskYIELD. - */ -extern void vPortYield( void ); -#define portYIELD() vPortYield() -/*-----------------------------------------------------------*/ - -/* Hardware specifics. */ -#define portBYTE_ALIGNMENT 2 -#define portSTACK_GROWTH ( -1 ) -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) -#define portNOP() -/*-----------------------------------------------------------*/ - -/* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) __toplevel - -/* Compiler specifics. */ -#define inline - -/* Just used by the demo application to indicate which form of interrupt -service routine should be used. See the online port documentation for more -information. */ -#define MSP_ROWLEY_RB_PORT - -#endif /* PORTMACRO_H */ - diff --git a/Source/portable/Rowley/MSP430F449/readme.txt b/Source/portable/Rowley/MSP430F449/readme.txt deleted file mode 100644 index f438b3642..000000000 --- a/Source/portable/Rowley/MSP430F449/readme.txt +++ /dev/null @@ -1,5 +0,0 @@ -To use Port1, copy the three files from the Port1 directory into this directory. - -To use Port2, copy the three files from the Port2 directory into this directory. - -Ensure to perform a complete rebuild. \ No newline at end of file diff --git a/Source/portable/SDCC/Cygnal/port.c b/Source/portable/SDCC/Cygnal/port.c deleted file mode 100644 index ccd4751a9..000000000 --- a/Source/portable/SDCC/Cygnal/port.c +++ /dev/null @@ -1,427 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the Cygnal port. - *----------------------------------------------------------*/ - -/* Standard includes. */ -#include - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Constants required to setup timer 2 to produce the RTOS tick. */ -#define portCLOCK_DIVISOR ( ( unsigned portLONG ) 12 ) -#define portMAX_TIMER_VALUE ( ( unsigned portLONG ) 0xffff ) -#define portENABLE_TIMER ( ( unsigned portCHAR ) 0x04 ) -#define portTIMER_2_INTERRUPT_ENABLE ( ( unsigned portCHAR ) 0x20 ) - -/* The value used in the IE register when a task first starts. */ -#define portGLOBAL_INTERRUPT_BIT ( ( portSTACK_TYPE ) 0x80 ) - -/* The value used in the PSW register when a task first starts. */ -#define portINITIAL_PSW ( ( portSTACK_TYPE ) 0x00 ) - -/* Macro to clear the timer 2 interrupt flag. */ -#define portCLEAR_INTERRUPT_FLAG() TMR2CN &= ~0x80; - -/* Used during a context switch to store the size of the stack being copied -to or from XRAM. */ -data static unsigned portCHAR ucStackBytes; - -/* Used during a context switch to point to the next byte in XRAM from/to which -a RAM byte is to be copied. */ -xdata static portSTACK_TYPE * data pxXRAMStack; - -/* Used during a context switch to point to the next byte in RAM from/to which -an XRAM byte is to be copied. */ -data static portSTACK_TYPE * data pxRAMStack; - -/* We require the address of the pxCurrentTCB variable, but don't want to know -any details of its type. */ -typedef void tskTCB; -extern volatile tskTCB * volatile pxCurrentTCB; - -/* - * Setup the hardware to generate an interrupt off timer 2 at the required - * frequency. - */ -static void prvSetupTimerInterrupt( void ); - -/*-----------------------------------------------------------*/ -/* - * Macro that copies the current stack from internal RAM to XRAM. This is - * required as the 8051 only contains enough internal RAM for a single stack, - * but we have a stack for every task. - */ -#define portCOPY_STACK_TO_XRAM() \ -{ \ - /* pxCurrentTCB points to a TCB which itself points to the location into \ - which the first stack byte should be copied. Set pxXRAMStack to point \ - to the location into which the first stack byte is to be copied. */ \ - pxXRAMStack = ( xdata portSTACK_TYPE * ) *( ( xdata portSTACK_TYPE ** ) pxCurrentTCB ); \ - \ - /* Set pxRAMStack to point to the first byte to be coped from the stack. */ \ - pxRAMStack = ( data portSTACK_TYPE * data ) configSTACK_START; \ - \ - /* Calculate the size of the stack we are about to copy from the current \ - stack pointer value. */ \ - ucStackBytes = SP - ( configSTACK_START - 1 ); \ - \ - /* Before starting to copy the stack, store the calculated stack size so \ - the stack can be restored when the task is resumed. */ \ - *pxXRAMStack = ucStackBytes; \ - \ - /* Copy each stack byte in turn. pxXRAMStack is incremented first as we \ - have already stored the stack size into XRAM. */ \ - while( ucStackBytes ) \ - { \ - pxXRAMStack++; \ - *pxXRAMStack = *pxRAMStack; \ - pxRAMStack++; \ - ucStackBytes--; \ - } \ -} -/*-----------------------------------------------------------*/ - -/* - * Macro that copies the stack of the task being resumed from XRAM into - * internal RAM. - */ -#define portCOPY_XRAM_TO_STACK() \ -{ \ - /* Setup the pointers as per portCOPY_STACK_TO_XRAM(), but this time to \ - copy the data back out of XRAM and into the stack. */ \ - pxXRAMStack = ( xdata portSTACK_TYPE * ) *( ( xdata portSTACK_TYPE ** ) pxCurrentTCB ); \ - pxRAMStack = ( data portSTACK_TYPE * data ) ( configSTACK_START - 1 ); \ - \ - /* The first value stored in XRAM was the size of the stack - i.e. the \ - number of bytes we need to copy back. */ \ - ucStackBytes = pxXRAMStack[ 0 ]; \ - \ - /* Copy the required number of bytes back into the stack. */ \ - do \ - { \ - pxXRAMStack++; \ - pxRAMStack++; \ - *pxRAMStack = *pxXRAMStack; \ - ucStackBytes--; \ - } while( ucStackBytes ); \ - \ - /* Restore the stack pointer ready to use the restored stack. */ \ - SP = ( unsigned portCHAR ) pxRAMStack; \ -} -/*-----------------------------------------------------------*/ - -/* - * Macro to push the current execution context onto the stack, before the stack - * is moved to XRAM. - */ -#define portSAVE_CONTEXT() \ -{ \ - _asm \ - /* Push ACC first, as when restoring the context it must be restored \ - last (it is used to set the IE register). */ \ - push ACC \ - /* Store the IE register then disable interrupts. */ \ - push IE \ - clr _EA \ - push DPL \ - push DPH \ - push b \ - push ar2 \ - push ar3 \ - push ar4 \ - push ar5 \ - push ar6 \ - push ar7 \ - push ar0 \ - push ar1 \ - push PSW \ - _endasm; \ - PSW = 0; \ - _asm \ - push _bp \ - _endasm; \ -} -/*-----------------------------------------------------------*/ - -/* - * Macro that restores the execution context from the stack. The execution - * context was saved into the stack before the stack was copied into XRAM. - */ -#define portRESTORE_CONTEXT() \ -{ \ - _asm \ - pop _bp \ - pop PSW \ - pop ar1 \ - pop ar0 \ - pop ar7 \ - pop ar6 \ - pop ar5 \ - pop ar4 \ - pop ar3 \ - pop ar2 \ - pop b \ - pop DPH \ - pop DPL \ - /* The next byte of the stack is the IE register. Only the global \ - enable bit forms part of the task context. Pop off the IE then set \ - the global enable bit to match that of the stored IE register. */ \ - pop ACC \ - JB ACC.7,0098$ \ - CLR IE.7 \ - LJMP 0099$ \ - 0098$: \ - SETB IE.7 \ - 0099$: \ - /* Finally pop off the ACC, which was the first register saved. */ \ - pop ACC \ - reti \ - _endasm; \ -} -/*-----------------------------------------------------------*/ - -/* - * See header file for description. - */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) -{ -unsigned portLONG ulAddress; -portSTACK_TYPE *pxStartOfStack; - - /* Leave space to write the size of the stack as the first byte. */ - pxStartOfStack = pxTopOfStack; - pxTopOfStack++; - - /* Place a few bytes of known values on the bottom of the stack. - This is just useful for debugging and can be uncommented if required. - *pxTopOfStack = 0x11; - pxTopOfStack++; - *pxTopOfStack = 0x22; - pxTopOfStack++; - *pxTopOfStack = 0x33; - pxTopOfStack++; - */ - - /* Simulate how the stack would look after a call to the scheduler tick - ISR. - - The return address that would have been pushed by the MCU. */ - ulAddress = ( unsigned portLONG ) pxCode; - *pxTopOfStack = ( portSTACK_TYPE ) ulAddress; - ulAddress >>= 8; - pxTopOfStack++; - *pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress ); - pxTopOfStack++; - - /* Next all the registers will have been pushed by portSAVE_CONTEXT(). */ - *pxTopOfStack = 0xaa; /* acc */ - pxTopOfStack++; - - /* We want tasks to start with interrupts enabled. */ - *pxTopOfStack = portGLOBAL_INTERRUPT_BIT; - pxTopOfStack++; - - /* The function parameters will be passed in the DPTR and B register as - a three byte generic pointer is used. */ - ulAddress = ( unsigned portLONG ) pvParameters; - *pxTopOfStack = ( portSTACK_TYPE ) ulAddress; /* DPL */ - ulAddress >>= 8; - *pxTopOfStack++; - *pxTopOfStack = ( portSTACK_TYPE ) ulAddress; /* DPH */ - ulAddress >>= 8; - pxTopOfStack++; - *pxTopOfStack = ( portSTACK_TYPE ) ulAddress; /* b */ - pxTopOfStack++; - - /* The remaining registers are straight forward. */ - *pxTopOfStack = 0x02; /* R2 */ - pxTopOfStack++; - *pxTopOfStack = 0x03; /* R3 */ - pxTopOfStack++; - *pxTopOfStack = 0x04; /* R4 */ - pxTopOfStack++; - *pxTopOfStack = 0x05; /* R5 */ - pxTopOfStack++; - *pxTopOfStack = 0x06; /* R6 */ - pxTopOfStack++; - *pxTopOfStack = 0x07; /* R7 */ - pxTopOfStack++; - *pxTopOfStack = 0x00; /* R0 */ - pxTopOfStack++; - *pxTopOfStack = 0x01; /* R1 */ - pxTopOfStack++; - *pxTopOfStack = 0x00; /* PSW */ - pxTopOfStack++; - *pxTopOfStack = 0xbb; /* BP */ - - /* Dont increment the stack size here as we don't want to include - the stack size byte as part of the stack size count. - - Finally we place the stack size at the beginning. */ - *pxStartOfStack = ( portSTACK_TYPE ) ( pxTopOfStack - pxStartOfStack ); - - /* Unlike most ports, we return the start of the stack as this is where the - size of the stack is stored. */ - return pxStartOfStack; -} -/*-----------------------------------------------------------*/ - -/* - * See header file for description. - */ -portBASE_TYPE xPortStartScheduler( void ) -{ - /* Setup timer 2 to generate the RTOS tick. */ - prvSetupTimerInterrupt(); - - /* Make sure we start with the expected SFR page. This line should not - really be required. */ - SFRPAGE = 0; - - /* Copy the stack for the first task to execute from XRAM into the stack, - restore the task context from the new stack, then start running the task. */ - portCOPY_XRAM_TO_STACK(); - portRESTORE_CONTEXT(); - - /* Should never get here! */ - return pdTRUE; -} -/*-----------------------------------------------------------*/ - -void vPortEndScheduler( void ) -{ - /* Not implemented for this port. */ -} -/*-----------------------------------------------------------*/ - -/* - * Manual context switch. The first thing we do is save the registers so we - * can use a naked attribute. - */ -void vPortYield( void ) _naked -{ - /* Save the execution context onto the stack, then copy the entire stack - to XRAM. This is necessary as the internal RAM is only large enough to - hold one stack, and we want one per task. - - PERFORMANCE COULD BE IMPROVED BY ONLY COPYING TO XRAM IF A TASK SWITCH - IS REQUIRED. */ - portSAVE_CONTEXT(); - portCOPY_STACK_TO_XRAM(); - - /* Call the standard scheduler context switch function. */ - vTaskSwitchContext(); - - /* Copy the stack of the task about to execute from XRAM into RAM and - restore it's context ready to run on exiting. */ - portCOPY_XRAM_TO_STACK(); - portRESTORE_CONTEXT(); -} -/*-----------------------------------------------------------*/ - -#if configUSE_PREEMPTION == 1 - void vTimer2ISR( void ) interrupt 5 _naked - { - /* Preemptive context switch function triggered by the timer 2 ISR. - This does the same as vPortYield() (see above) with the addition - of incrementing the RTOS tick count. */ - - portSAVE_CONTEXT(); - portCOPY_STACK_TO_XRAM(); - - vTaskIncrementTick(); - vTaskSwitchContext(); - - portCLEAR_INTERRUPT_FLAG(); - portCOPY_XRAM_TO_STACK(); - portRESTORE_CONTEXT(); - } -#else - void vTimer2ISR( void ) interrupt 5 - { - /* When using the cooperative scheduler the timer 2 ISR is only - required to increment the RTOS tick count. */ - - vTaskIncrementTick(); - portCLEAR_INTERRUPT_FLAG(); - } -#endif -/*-----------------------------------------------------------*/ - -static void prvSetupTimerInterrupt( void ) -{ -unsigned portCHAR ucOriginalSFRPage; - -/* Constants calculated to give the required timer capture values. */ -const unsigned portLONG ulTicksPerSecond = configCPU_CLOCK_HZ / portCLOCK_DIVISOR; -const unsigned portLONG ulCaptureTime = ulTicksPerSecond / configTICK_RATE_HZ; -const unsigned portLONG ulCaptureValue = portMAX_TIMER_VALUE - ulCaptureTime; -const unsigned portCHAR ucLowCaptureByte = ( unsigned portCHAR ) ( ulCaptureValue & ( unsigned portLONG ) 0xff ); -const unsigned portCHAR ucHighCaptureByte = ( unsigned portCHAR ) ( ulCaptureValue >> ( unsigned portLONG ) 8 ); - - /* NOTE: This uses a timer only present on 8052 architecture. */ - - /* Remember the current SFR page so we can restore it at the end of the - function. */ - ucOriginalSFRPage = SFRPAGE; - SFRPAGE = 0; - - /* TMR2CF can be left in its default state. */ - TMR2CF = ( unsigned portCHAR ) 0; - - /* Setup the overflow reload value. */ - RCAP2L = ucLowCaptureByte; - RCAP2H = ucHighCaptureByte; - - /* The initial load is performed manually. */ - TMR2L = ucLowCaptureByte; - TMR2H = ucHighCaptureByte; - - /* Enable the timer 2 interrupts. */ - IE |= portTIMER_2_INTERRUPT_ENABLE; - - /* Interrupts are disabled when this is called so the timer can be started - here. */ - TMR2CN = portENABLE_TIMER; - - /* Restore the original SFR page. */ - SFRPAGE = ucOriginalSFRPage; -} - - - - diff --git a/Source/portable/SDCC/Cygnal/portmacro.h b/Source/portable/SDCC/Cygnal/portmacro.h deleted file mode 100644 index 356a489aa..000000000 --- a/Source/portable/SDCC/Cygnal/portmacro.h +++ /dev/null @@ -1,118 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -#if configUSE_PREEMPTION == 0 - void vTimer2ISR( void ) interrupt 5; -#else - void vTimer2ISR( void ) interrupt 5 _naked; -#endif - -void vSerialISR( void ) interrupt 4; - - -/*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the - * given hardware and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - -/* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE float -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE unsigned portCHAR -#define portBASE_TYPE char - -#if( configUSE_16_BIT_TICKS == 1 ) - typedef unsigned portSHORT portTickType; - #define portMAX_DELAY ( portTickType ) 0xffff -#else - typedef unsigned portLONG portTickType; - #define portMAX_DELAY ( portTickType ) 0xffffffff -#endif -/*-----------------------------------------------------------*/ - -/* Critical section management. */ -#define portENTER_CRITICAL() _asm \ - push ACC \ - push IE \ - _endasm; \ - EA = 0; - -#define portEXIT_CRITICAL() _asm \ - pop ACC \ - _endasm; \ - ACC &= 0x80; \ - IE |= ACC; \ - _asm \ - pop ACC \ - _endasm; - -#define portDISABLE_INTERRUPTS() EA = 0; -#define portENABLE_INTERRUPTS() EA = 1; -/*-----------------------------------------------------------*/ - -/* Hardware specifics. */ -#define portBYTE_ALIGNMENT 1 -#define portSTACK_GROWTH ( 1 ) -#define portTICK_RATE_MS ( ( unsigned portLONG ) 1000 / configTICK_RATE_HZ ) -/*-----------------------------------------------------------*/ - -/* Task utilities. */ -void vPortYield( void ) _naked; -#define portYIELD() vPortYield(); -/*-----------------------------------------------------------*/ - -/* Compiler specifics. */ -#define inline -#define portNOP() _asm \ - nop \ - _endasm; - -/*-----------------------------------------------------------*/ - -/* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) - -#endif /* PORTMACRO_H */ - - diff --git a/Source/portable/WizC/PIC18/Drivers/Tick/Tick.c b/Source/portable/WizC/PIC18/Drivers/Tick/Tick.c deleted file mode 100644 index f4bf60d78..000000000 --- a/Source/portable/WizC/PIC18/Drivers/Tick/Tick.c +++ /dev/null @@ -1,143 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V3.0.0 - + ISRcode is pulled inline and portTICKisr() is therefore - deleted from this file. - - + Prescaler logic for Timer1 added to allow for a wider - range of TickRates. - -Changes from V3.0.1 -*/ - -#include -#include - -/* IO port constants. */ -#define portBIT_SET (1) -#define portBIT_CLEAR (0) - -/* - * Hardware setup for the tick. - * We use a compare match on timer1. Depending on MPU-frequency - * and requested tickrate, a prescaled value with a matching - * prescaler are determined. - */ -#define portTIMER_COMPARE_BASE ((APROCFREQ/4)/configTICK_RATE_HZ) - -#if portTIMER_COMPARE_BASE < 0x10000 - #define portTIMER_COMPARE_VALUE (portTIMER_COMPARE_BASE) - #define portTIMER_COMPARE_PS1 (portBIT_CLEAR) - #define portTIMER_COMPARE_PS0 (portBIT_CLEAR) -#elif portTIMER_COMPARE_BASE < 0x20000 - #define portTIMER_COMPARE_VALUE (portTIMER_COMPARE_BASE / 2) - #define portTIMER_COMPARE_PS1 (portBIT_CLEAR) - #define portTIMER_COMPARE_PS0 (portBIT_SET) -#elif portTIMER_COMPARE_BASE < 0x40000 - #define portTIMER_COMPARE_VALUE (portTIMER_COMPARE_BASE / 4) - #define portTIMER_COMPARE_PS1 (portBIT_SET) - #define portTIMER_COMPARE_PS0 (portBIT_CLEAR) -#elif portTIMER_COMPARE_BASE < 0x80000 - #define portTIMER_COMPARE_VALUE (portTIMER_COMPARE_BASE / 8) - #define portTIMER_COMPARE_PS1 (portBIT_SET) - #define portTIMER_COMPARE_PS0 (portBIT_SET) -#else - #error "TickRate out of range" -#endif - -/*-----------------------------------------------------------*/ - -/* - * Setup a timer for a regular tick. - */ -void portSetupTick( void ) -{ - /* - * Interrupts are disabled when this function is called. - */ - - /* - * Setup CCP1 - * Provide the tick interrupt using a compare match on timer1. - */ - - /* - * Set the compare match value. - */ - CCPR1H = ( unsigned portCHAR ) ( ( portTIMER_COMPARE_VALUE >> 8 ) & 0xff ); - CCPR1L = ( unsigned portCHAR ) ( portTIMER_COMPARE_VALUE & 0xff ); - - /* - * Set Compare Special Event Trigger Mode - */ - bCCP1M3 = portBIT_SET; - bCCP1M2 = portBIT_CLEAR; - bCCP1M1 = portBIT_SET; - bCCP1M0 = portBIT_SET; - - /* - * Enable CCP1 interrupt - */ - bCCP1IE = portBIT_SET; - - /* - * We are only going to use the global interrupt bit, so disable - * interruptpriorities and enable peripheral interrupts. - */ - bIPEN = portBIT_CLEAR; - bPEIE = portBIT_SET; - - /* - * Set up timer1 - * It will produce the system tick. - */ - - /* - * Clear the time count - */ - TMR1H = ( unsigned portCHAR ) 0x00; - TMR1L = ( unsigned portCHAR ) 0x00; - - /* - * Setup the timer - */ - bRD16 = portBIT_SET; // 16-bit - bT1CKPS1 = portTIMER_COMPARE_PS1; // prescaler - bT1CKPS0 = portTIMER_COMPARE_PS0; // prescaler - bT1OSCEN = portBIT_SET; // Oscillator enable - bT1SYNC = portBIT_SET; // No external clock sync - bTMR1CS = portBIT_CLEAR; // Internal clock - - bTMR1ON = portBIT_SET; // Start timer1 -} diff --git a/Source/portable/WizC/PIC18/Drivers/Tick/isrTick.c b/Source/portable/WizC/PIC18/Drivers/Tick/isrTick.c deleted file mode 100644 index 6ec72e25c..000000000 --- a/Source/portable/WizC/PIC18/Drivers/Tick/isrTick.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V3.0.0 - + ISRcode pulled inline to reduce stack-usage. - - + Added functionality to only call vTaskSwitchContext() once - when handling multiple interruptsources in a single interruptcall. - - + Filename changed to a .c extension to allow stepping through code - using F7. - -Changes from V3.0.1 -*/ - -/* - * ISR for the tick. - * This increments the tick count and, if using the preemptive scheduler, - * performs a context switch. This must be identical to the manual - * context switch in how it stores the context of a task. - */ - -#ifndef _FREERTOS_DRIVERS_TICK_ISRTICK_C -#define _FREERTOS_DRIVERS_TICK_ISRTICK_C - -{ - /* - * Was the interrupt the SystemClock? - */ - if( bCCP1IF && bCCP1IE ) - { - /* - * Reset the interrupt flag - */ - bCCP1IF = 0; - - /* - * Maintain the tick count. - */ - vTaskIncrementTick(); - - #if configUSE_PREEMPTION == 1 - { - /* - * Ask for a switch to the highest priority task - * that is ready to run. - */ - uxSwitchRequested = pdTRUE; - } - #endif - } -} - -#pragma wizcpp uselib "$__PATHNAME__/Tick.c" - -#endif /* _FREERTOS_DRIVERS_TICK_ISRTICK_C */ diff --git a/Source/portable/WizC/PIC18/addFreeRTOS.h b/Source/portable/WizC/PIC18/addFreeRTOS.h deleted file mode 100644 index 2d79b5c92..000000000 --- a/Source/portable/WizC/PIC18/addFreeRTOS.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V3.0.0 - -Changes from V3.0.1 - -Changes from V4.0.1 - Uselib pragma added for Croutine.c -*/ - -/* - * The installation script will automatically prepend this file to the default FreeRTOS.h. - */ - -#ifndef WIZC_FREERTOS_H -#define WIZC_FREERTOS_H - -#pragma noheap -#pragma wizcpp expandnl on -#pragma wizcpp searchpath "$__PATHNAME__/libFreeRTOS/Include/" -#pragma wizcpp uselib "$__PATHNAME__/libFreeRTOS/Modules/Croutine.c" -#pragma wizcpp uselib "$__PATHNAME__/libFreeRTOS/Modules/Tasks.c" -#pragma wizcpp uselib "$__PATHNAME__/libFreeRTOS/Modules/Queue.c" -#pragma wizcpp uselib "$__PATHNAME__/libFreeRTOS/Modules/List.c" -#pragma wizcpp uselib "$__PATHNAME__/libFreeRTOS/Modules/Port.c" - -#endif /* WIZC_FREERTOS_H */ diff --git a/Source/portable/WizC/PIC18/port.c b/Source/portable/WizC/PIC18/port.c deleted file mode 100644 index 4bcb57fad..000000000 --- a/Source/portable/WizC/PIC18/port.c +++ /dev/null @@ -1,313 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V3.2.1 - + CallReturn Depth increased from 8 to 10 levels to accomodate wizC/fedC V12. - -Changes from V3.2.0 - + TBLPTRU is now initialised to zero during the initial stack creation of a new task. This solves - an error on devices with more than 64kB ROM. - -Changes from V3.0.0 - + ucCriticalNesting is now initialised to 0x7F to prevent interrupts from being - handled before the scheduler is started. - -Changes from V3.0.1 -*/ - -/* Scheduler include files. */ -#include -#include - -#include - -/*--------------------------------------------------------------------------- - * Implementation of functions defined in portable.h for the WizC PIC18 port. - *---------------------------------------------------------------------------*/ - -/* - * We require the address of the pxCurrentTCB variable, but don't want to - * know any details of its type. - */ -typedef void tskTCB; -extern volatile tskTCB * volatile pxCurrentTCB; - -/* - * Define minimal-stack constants - * ----- - * FSR's: - * STATUS, WREG, BSR, PRODH, PRODL, FSR0H, FSR0L, - * FSR1H, FSR1L,TABLAT, (TBLPTRU), TBLPTRH, TBLPTRL, - * (PCLATU), PCLATH - * sfr's within parenthesis only on devices > 64kB - * ----- - * Call/Return stack: - * 2 bytes per entry on devices <= 64kB - * 3 bytes per entry on devices > 64kB - * ----- - * Other bytes: - * 2 bytes: FunctionParameter for initial taskcode - * 1 byte : Number of entries on call/return stack - * 1 byte : ucCriticalNesting - * 16 bytes: Free space on stack - */ -#if _ROMSIZE > 0x8000 - #define portSTACK_FSR_BYTES ( 15 ) - #define portSTACK_CALLRETURN_ENTRY_SIZE ( 3 ) -#else - #define portSTACK_FSR_BYTES ( 13 ) - #define portSTACK_CALLRETURN_ENTRY_SIZE ( 2 ) -#endif - -#define portSTACK_MINIMAL_CALLRETURN_DEPTH ( 10 ) -#define portSTACK_OTHER_BYTES ( 20 ) - -unsigned portSHORT usCalcMinStackSize = 0; - -/*-----------------------------------------------------------*/ - -/* - * We initialise ucCriticalNesting to the middle value an - * unsigned char can contain. This way portENTER_CRITICAL() - * and portEXIT_CRITICAL() can be called without interrupts - * being enabled before the scheduler starts. - */ -register unsigned portCHAR ucCriticalNesting = 0x7F; - -/*-----------------------------------------------------------*/ - -/* - * Initialise the stack of a new task. - * See portSAVE_CONTEXT macro for description. - */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) -{ -unsigned portCHAR ucScratch; - /* - * Get the size of the RAMarea in page 0 used by the compiler - * We do this here already to avoid W-register conflicts. - */ - _Pragma("asm") - movlw OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE - movwf PRODL,ACCESS ; PRODL is used as temp register - _Pragma("asmend") - ucScratch = PRODL; - - /* - * Place a few bytes of known values on the bottom of the stack. - * This is just useful for debugging. - */ -// *pxTopOfStack-- = 0x11; -// *pxTopOfStack-- = 0x22; -// *pxTopOfStack-- = 0x33; - - /* - * Simulate how the stack would look after a call to vPortYield() - * generated by the compiler. - */ - - /* - * First store the function parameters. This is where the task expects - * to find them when it starts running. - */ - *pxTopOfStack-- = ( portSTACK_TYPE ) ( (( unsigned portSHORT ) pvParameters >> 8) & 0x00ff ); - *pxTopOfStack-- = ( portSTACK_TYPE ) ( ( unsigned portSHORT ) pvParameters & 0x00ff ); - - /* - * Next are all the registers that form part of the task context. - */ - *pxTopOfStack-- = ( portSTACK_TYPE ) 0x11; /* STATUS. */ - *pxTopOfStack-- = ( portSTACK_TYPE ) 0x22; /* WREG. */ - *pxTopOfStack-- = ( portSTACK_TYPE ) 0x33; /* BSR. */ - *pxTopOfStack-- = ( portSTACK_TYPE ) 0x44; /* PRODH. */ - *pxTopOfStack-- = ( portSTACK_TYPE ) 0x55; /* PRODL. */ - *pxTopOfStack-- = ( portSTACK_TYPE ) 0x66; /* FSR0H. */ - *pxTopOfStack-- = ( portSTACK_TYPE ) 0x77; /* FSR0L. */ - *pxTopOfStack-- = ( portSTACK_TYPE ) 0x88; /* FSR1H. */ - *pxTopOfStack-- = ( portSTACK_TYPE ) 0x99; /* FSR1L. */ - *pxTopOfStack-- = ( portSTACK_TYPE ) 0xAA; /* TABLAT. */ -#if _ROMSIZE > 0x8000 - *pxTopOfStack-- = ( portSTACK_TYPE ) 0x00; /* TBLPTRU. */ -#endif - *pxTopOfStack-- = ( portSTACK_TYPE ) 0xCC; /* TBLPTRH. */ - *pxTopOfStack-- = ( portSTACK_TYPE ) 0xDD; /* TBLPTRL. */ -#if _ROMSIZE > 0x8000 - *pxTopOfStack-- = ( portSTACK_TYPE ) 0xEE; /* PCLATU. */ -#endif - *pxTopOfStack-- = ( portSTACK_TYPE ) 0xFF; /* PCLATH. */ - - /* - * Next the compiler's scratchspace. - */ - while(ucScratch-- > 0) - { - *pxTopOfStack-- = ( portSTACK_TYPE ) 0; - } - - /* - * The only function return address so far is the address of the task entry. - * The order is TOSU/TOSH/TOSL. For devices > 64kB, TOSU is put on the - * stack, too. TOSU is always written as zero here because wizC does not allow - * functionpointers to point above 64kB in ROM. - */ -#if _ROMSIZE > 0x8000 - *pxTopOfStack-- = ( portSTACK_TYPE ) 0; -#endif - *pxTopOfStack-- = ( portSTACK_TYPE ) ( ( ( unsigned portSHORT ) pxCode >> 8 ) & 0x00ff ); - *pxTopOfStack-- = ( portSTACK_TYPE ) ( ( unsigned portSHORT ) pxCode & 0x00ff ); - - /* - * Store the number of return addresses on the hardware stack. - * So far only the address of the task entry point. - */ - *pxTopOfStack-- = ( portSTACK_TYPE ) 1; - - /* - * The code generated by wizC does not maintain separate - * stack and frame pointers. Therefore the portENTER_CRITICAL macro cannot - * use the stack as per other ports. Instead a variable is used to keep - * track of the critical section nesting. This variable has to be stored - * as part of the task context and is initially set to zero. - */ - *pxTopOfStack-- = ( portSTACK_TYPE ) portNO_CRITICAL_SECTION_NESTING; - - return pxTopOfStack; -} -/*-----------------------------------------------------------*/ - -unsigned portSHORT usPortCALCULATE_MINIMAL_STACK_SIZE( void ) -{ - /* - * Fetch the size of compiler's scratchspace. - */ - _Pragma("asm") - movlw OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE - movlb usCalcMinStackSize>>8 - movwf usCalcMinStackSize,BANKED - _Pragma("asmend") - - /* - * Add minimum needed stackspace - */ - usCalcMinStackSize += ( portSTACK_FSR_BYTES ) - + ( portSTACK_MINIMAL_CALLRETURN_DEPTH * portSTACK_CALLRETURN_ENTRY_SIZE ) - + ( portSTACK_OTHER_BYTES ); - - return(usCalcMinStackSize); -} - -/*-----------------------------------------------------------*/ - -portBASE_TYPE xPortStartScheduler( void ) -{ - extern void portSetupTick( void ); - - /* - * Setup a timer for the tick ISR for the preemptive scheduler. - */ - portSetupTick(); - - /* - * Restore the context of the first task to run. - */ - portRESTORE_CONTEXT(); - - /* - * This point should never be reached during execution. - */ - return pdTRUE; -} - -/*-----------------------------------------------------------*/ - -void vPortEndScheduler( void ) -{ - /* - * It is unlikely that the scheduler for the PIC port will get stopped - * once running. When called a reset is done which is probably the - * most valid action. - */ - _Pragma(asmline reset); -} - -/*-----------------------------------------------------------*/ - -/* - * Manual context switch. This is similar to the tick context switch, - * but does not increment the tick count. It must be identical to the - * tick context switch in how it stores the stack of a task. - */ -void vPortYield( void ) -{ - /* - * Save the context of the current task. - */ - portSAVE_CONTEXT( portINTERRUPTS_UNCHANGED ); - - /* - * Switch to the highest priority task that is ready to run. - */ - vTaskSwitchContext(); - - /* - * Start executing the task we have just switched to. - */ - portRESTORE_CONTEXT(); -} - -/*-----------------------------------------------------------*/ - -void *pvPortMalloc( unsigned portSHORT usWantedSize ) -{ -void *pvReturn; - - vTaskSuspendAll(); - { - pvReturn = malloc( ( malloc_t ) usWantedSize ); - } - xTaskResumeAll(); - - return pvReturn; -} - -void vPortFree( void *pv ) -{ - if( pv ) - { - vTaskSuspendAll(); - { - free( pv ); - } - xTaskResumeAll(); - } -} diff --git a/Source/portable/WizC/PIC18/portmacro.h b/Source/portable/WizC/PIC18/portmacro.h deleted file mode 100644 index 2cf8bd723..000000000 --- a/Source/portable/WizC/PIC18/portmacro.h +++ /dev/null @@ -1,423 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V3.0.0 - -Changes from V3.0.1 -*/ -#ifndef PORTMACRO_H -#define PORTMACRO_H - -#if !defined(_SERIES) || _SERIES != 18 - #error "WizC supports FreeRTOS on the Microchip PIC18-series only" -#endif - -#if !defined(QUICKCALL) || QUICKCALL != 1 - #error "QuickCall must be enabled (see ProjectOptions/Optimisations)" -#endif - -#include -#include - -#define portCHAR char -#define portFLOAT float -#define portDOUBLE portFLOAT -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE unsigned char -#define portBASE_TYPE char - -#if( configUSE_16_BIT_TICKS == 1 ) - typedef unsigned portSHORT portTickType; - #define portMAX_DELAY ( portTickType ) ( 0xFFFF ) -#else - typedef unsigned portLONG portTickType; - #define portMAX_DELAY ( portTickType ) ( 0xFFFFFFFF ) -#endif - -#define portBYTE_ALIGNMENT 1 - -/*-----------------------------------------------------------*/ - -/* - * Constant used for context switch macro when we require the interrupt - * enable state to be forced when the interrupted task is switched back in. - */ -#define portINTERRUPTS_FORCED (0x01) - -/* - * Constant used for context switch macro when we require the interrupt - * enable state to be unchanged when the interrupted task is switched back in. - */ -#define portINTERRUPTS_UNCHANGED (0x00) - -/* Initial interrupt enable state for newly created tasks. This value is - * used when a task switches in for the first time. - */ -#define portINTERRUPTS_INITIAL_STATE (portINTERRUPTS_FORCED) - -/* - * Macros to modify the global interrupt enable bit in INTCON. - */ -#define portDISABLE_INTERRUPTS() \ - do \ - { \ - bGIE=0; \ - } while(bGIE) // MicroChip recommends this check! - -#define portENABLE_INTERRUPTS() \ - do \ - { \ - bGIE=1; \ - } while(0) - -/*-----------------------------------------------------------*/ - -/* - * Critical section macros. - */ -extern unsigned portCHAR ucCriticalNesting; - -#define portNO_CRITICAL_SECTION_NESTING ( ( unsigned portCHAR ) 0 ) - -#define portENTER_CRITICAL() \ - do \ - { \ - portDISABLE_INTERRUPTS(); \ - \ - /* \ - * Now interrupts are disabled ucCriticalNesting \ - * can be accessed directly. Increment \ - * ucCriticalNesting to keep a count of how \ - * many times portENTER_CRITICAL() has been called. \ - */ \ - ucCriticalNesting++; \ - } while(0) - -#define portEXIT_CRITICAL() \ - do \ - { \ - if(ucCriticalNesting > portNO_CRITICAL_SECTION_NESTING) \ - { \ - /* \ - * Decrement the nesting count as we are leaving a \ - * critical section. \ - */ \ - ucCriticalNesting--; \ - } \ - \ - /* \ - * If the nesting level has reached zero then \ - * interrupts should be re-enabled. \ - */ \ - if( ucCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ - { \ - portENABLE_INTERRUPTS(); \ - } \ - } while(0) - -/*-----------------------------------------------------------*/ - -/* - * The minimal stacksize is calculated on the first reference of - * portMINIMAL_STACK_SIZE. Some input to this calculation is - * compiletime determined, other input is port-defined (see port.c) - */ -extern unsigned portSHORT usPortCALCULATE_MINIMAL_STACK_SIZE( void ); -extern unsigned portSHORT usCalcMinStackSize; - -#define portMINIMAL_STACK_SIZE \ - ((usCalcMinStackSize == 0) \ - ? usPortCALCULATE_MINIMAL_STACK_SIZE() \ - : usCalcMinStackSize ) - -/* - * WizC uses a downgrowing stack - */ -#define portSTACK_GROWTH ( -1 ) - -/*-----------------------------------------------------------*/ - -/* - * Macro's that pushes all the registers that make up the context of a task onto - * the stack, then saves the new top of stack into the TCB. TOSU and TBLPTRU - * are only saved/restored on devices with more than 64kB (32k Words) ROM. - * - * The stackpointer is helt by WizC in FSR2 and points to the first free byte. - * WizC uses a "downgrowing" stack. There is no framepointer. - * - * We keep track of the interruptstatus using ucCriticalNesting. When this - * value equals zero, interrupts have to be enabled upon exit from the - * portRESTORE_CONTEXT macro. - * - * If this is called from an ISR then the interrupt enable bits must have been - * set for the ISR to ever get called. Therefore we want to save - * ucCriticalNesting with value zero. This means the interrupts will again be - * re-enabled when the interrupted task is switched back in. - * - * If this is called from a manual context switch (i.e. from a call to yield), - * then we want to keep the current value of ucCritialNesting so it is restored - * with its current value. This allows a yield from within a critical section. - * - * The compiler uses some locations at the bottom of RAM for temporary - * storage. The compiler may also have been instructed to optimize - * function-parameters and local variables to global storage. The compiler - * uses an area called LocOpt for this wizC feature. - * The total overheadstorage has to be saved in it's entirety as part of - * a task context. These macro's store/restore from data address 0x0000 to - * (OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE - 1). - * OVERHEADPAGE0, LOCOPTSIZE and MAXLOCOPTSIZE are compiler-generated - * assembler definitions. - */ - -#define portSAVE_CONTEXT( ucInterruptForced ) \ - do \ - { \ - portDISABLE_INTERRUPTS(); \ - \ - _Pragma("asm") \ - ; \ - ; Push the relevant SFR's onto the task's stack \ - ; \ - movff STATUS,POSTDEC2 \ - movff WREG,POSTDEC2 \ - movff BSR,POSTDEC2 \ - movff PRODH,POSTDEC2 \ - movff PRODL,POSTDEC2 \ - movff FSR0H,POSTDEC2 \ - movff FSR0L,POSTDEC2 \ - movff FSR1H,POSTDEC2 \ - movff FSR1L,POSTDEC2 \ - movff TABLAT,POSTDEC2 \ - if __ROMSIZE > 0x8000 \ - movff TBLPTRU,POSTDEC2 \ - endif \ - movff TBLPTRH,POSTDEC2 \ - movff TBLPTRL,POSTDEC2 \ - if __ROMSIZE > 0x8000 \ - movff PCLATU,POSTDEC2 \ - endif \ - movff PCLATH,POSTDEC2 \ - ; \ - ; Store the compiler-scratch-area as described above. \ - ; \ - movlw OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE \ - clrf FSR0L,ACCESS \ - clrf FSR0H,ACCESS \ - _rtos_S1: \ - movff POSTINC0,POSTDEC2 \ - decfsz WREG,W,ACCESS \ - SMARTJUMP _rtos_S1 \ - ; \ - ; Save the pic call/return-stack belonging to the \ - ; current task by copying it to the task's software- \ - ; stack. We save the hardware stack pointer (which \ - ; is the number of addresses on the stack) in the \ - ; W-register first because we need it later and it \ - ; is modified in the save-loop by executing pop's. \ - ; After the loop the W-register is stored on the \ - ; stack, too. \ - ; \ - movf STKPTR,W,ACCESS \ - bz _rtos_s3 \ - _rtos_S2: \ - if __ROMSIZE > 0x8000 \ - movff TOSU,POSTDEC2 \ - endif \ - movff TOSH,POSTDEC2 \ - movff TOSL,POSTDEC2 \ - pop \ - tstfsz STKPTR,ACCESS \ - SMARTJUMP _rtos_S2 \ - _rtos_s3: \ - movwf POSTDEC2,ACCESS \ - ; \ - ; Next the value for ucCriticalNesting used by the \ - ; task is stored on the stack. When \ - ; (ucInterruptForced == portINTERRUPTS_FORCED), we save \ - ; it as 0 (portNO_CRITICAL_SECTION_NESTING). \ - ; \ - if ucInterruptForced == portINTERRUPTS_FORCED \ - clrf POSTDEC2,ACCESS \ - else \ - movff ucCriticalNesting,POSTDEC2 \ - endif \ - ; \ - ; Save the new top of the software stack in the TCB. \ - ; \ - movff pxCurrentTCB,FSR0L \ - movff pxCurrentTCB+1,FSR0H \ - movff FSR2L,POSTINC0 \ - movff FSR2H,POSTINC0 \ - _Pragma("asmend") \ - } while(0) - -/************************************************************/ - -/* - * This is the reverse of portSAVE_CONTEXT. - */ -#define portRESTORE_CONTEXT() \ - do \ - { \ - _Pragma("asm") \ - ; \ - ; Set FSR0 to point to pxCurrentTCB->pxTopOfStack. \ - ; \ - movff pxCurrentTCB,FSR0L \ - movff pxCurrentTCB+1,FSR0H \ - ; \ - ; De-reference FSR0 to set the address it holds into \ - ; FSR2 (i.e. *( pxCurrentTCB->pxTopOfStack ) ). FSR2 \ - ; is used by wizC as stackpointer. \ - ; \ - movff POSTINC0,FSR2L \ - movff POSTINC0,FSR2H \ - ; \ - ; Next, the value for ucCriticalNesting used by the \ - ; task is retrieved from the stack. \ - ; \ - movff PREINC2,ucCriticalNesting \ - ; \ - ; Rebuild the pic call/return-stack. The number of \ - ; return addresses is the next item on the task stack. \ - ; Save this number in PRODL. Then fetch the addresses \ - ; and store them on the hardwarestack. \ - ; The datasheets say we can't use movff here... \ - ; \ - movff PREINC2,PRODL // Use PRODL as tempregister \ - clrf STKPTR,ACCESS \ - _rtos_R1: \ - push \ - movf PREINC2,W,ACCESS \ - movwf TOSL,ACCESS \ - movf PREINC2,W,ACCESS \ - movwf TOSH,ACCESS \ - if __ROMSIZE > 0x8000 \ - movf PREINC2,W,ACCESS \ - movwf TOSU,ACCESS \ - else \ - clrf TOSU,ACCESS \ - endif \ - decfsz PRODL,F,ACCESS \ - SMARTJUMP _rtos_R1 \ - ; \ - ; Restore the compiler's working storage area to page 0 \ - ; \ - movlw OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE \ - movwf FSR0L,ACCESS \ - clrf FSR0H,ACCESS \ - _rtos_R2: \ - decf FSR0L,F,ACCESS \ - movff PREINC2,INDF0 \ - tstfsz FSR0L,ACCESS \ - SMARTJUMP _rtos_R2 \ - ; \ - ; Restore the sfr's forming the tasks context. \ - ; We cannot yet restore bsr, w and status because \ - ; we need these registers for a final test. \ - ; \ - movff PREINC2,PCLATH \ - if __ROMSIZE > 0x8000 \ - movff PREINC2,PCLATU \ - else \ - clrf PCLATU,ACCESS \ - endif \ - movff PREINC2,TBLPTRL \ - movff PREINC2,TBLPTRH \ - if __ROMSIZE > 0x8000 \ - movff PREINC2,TBLPTRU \ - else \ - clrf TBLPTRU,ACCESS \ - endif \ - movff PREINC2,TABLAT \ - movff PREINC2,FSR1L \ - movff PREINC2,FSR1H \ - movff PREINC2,FSR0L \ - movff PREINC2,FSR0H \ - movff PREINC2,PRODL \ - movff PREINC2,PRODH \ - ; \ - ; The return from portRESTORE_CONTEXT() depends on \ - ; the value of ucCriticalNesting. When it is zero, \ - ; interrupts need to be enabled. This is done via a \ - ; retfie instruction because we need the \ - ; interrupt-enabling and the return to the restored \ - ; task to be uninterruptable. \ - ; Because bsr, status and W are affected by the test \ - ; they are restored after the test. \ - ; \ - movlb ucCriticalNesting>>8 \ - tstfsz ucCriticalNesting,BANKED \ - SMARTJUMP _rtos_R4 \ - _rtos_R3: \ - movff PREINC2,BSR \ - movff PREINC2,WREG \ - movff PREINC2,STATUS \ - retfie 0 ; Return enabling interrupts \ - _rtos_R4: \ - movff PREINC2,BSR \ - movff PREINC2,WREG \ - movff PREINC2,STATUS \ - return 0 ; Return without affecting interrupts \ - _Pragma("asmend") \ - } while(0) - -/*-----------------------------------------------------------*/ - -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) - -/*-----------------------------------------------------------*/ - -extern void vPortYield( void ); -#define portYIELD() vPortYield() - -#define portNOP() _Pragma("asm") \ - nop \ - _Pragma("asmend") - -/*-----------------------------------------------------------*/ - -#define portTASK_FUNCTION( xFunction, pvParameters ) \ - void pointed xFunction( void *pvParameters ) \ - _Pragma(asmfunc xFunction) - -#define portTASK_FUNCTION_PROTO portTASK_FUNCTION -/*-----------------------------------------------------------*/ - -#define inline -#define volatile -#define register - -#endif /* PORTMACRO_H */ - diff --git a/Source/portable/oWatcom/16BitDOS/Flsh186/port.c b/Source/portable/oWatcom/16BitDOS/Flsh186/port.c deleted file mode 100644 index 7254a9705..000000000 --- a/Source/portable/oWatcom/16BitDOS/Flsh186/port.c +++ /dev/null @@ -1,255 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V1.00: - - + Call to taskYIELD() from within tick ISR has been replaced by the more - efficient portSWITCH_CONTEXT(). - + ISR function definitions renamed to include the prv prefix. - -Changes from V1.2.0: - - + portRESET_PIC() is now called last thing before the end of the preemptive - tick routine. - -Changes from V2.6.1 - - + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION - macro to be consistent with the later ports. -*/ - -/*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the Flashlite 186 - * port. - *----------------------------------------------------------*/ - -#include -#include -#include -#include - -#include "FreeRTOS.h" -#include "task.h" -#include "portasm.h" - -/*lint -e950 Non ANSI reserved words okay in this file only. */ - -#define portTIMER_EOI_TYPE ( 8 ) -#define portRESET_PIC() portOUTPUT_WORD( ( unsigned portSHORT ) 0xff22, portTIMER_EOI_TYPE ) -#define portTIMER_INT_NUMBER 0x12 - -#define portTIMER_1_CONTROL_REGISTER ( ( unsigned portSHORT ) 0xff5e ) -#define portTIMER_0_CONTROL_REGISTER ( ( unsigned portSHORT ) 0xff56 ) -#define portTIMER_INTERRUPT_ENABLE ( ( unsigned portSHORT ) 0x2000 ) - -/* Setup the hardware to generate the required tick frequency. */ -static void prvSetTickFrequency( unsigned portLONG ulTickRateHz ); - -/* Set the hardware back to the state as per before the scheduler started. */ -static void prvExitFunction( void ); - -#if configUSE_PREEMPTION == 1 - /* Tick service routine used by the scheduler when preemptive scheduling is - being used. */ - static void __interrupt __far prvPreemptiveTick( void ); -#else - /* Tick service routine used by the scheduler when cooperative scheduling is - being used. */ - static void __interrupt __far prvNonPreemptiveTick( void ); -#endif - -/* Trap routine used by taskYIELD() to manually cause a context switch. */ -static void __interrupt __far prvYieldProcessor( void ); - -/*lint -e956 File scopes necessary here. */ - -/* Set true when the vectors are set so the scheduler will service the tick. */ -static portSHORT sSchedulerRunning = pdFALSE; - -/* Points to the original routine installed on the vector we use for manual context switches. This is then used to restore the original routine during prvExitFunction(). */ -static void ( __interrupt __far *pxOldSwitchISR )(); - -/* Used to restore the original DOS context when the scheduler is ended. */ -static jmp_buf xJumpBuf; - -/*lint +e956 */ - -/*-----------------------------------------------------------*/ -portBASE_TYPE xPortStartScheduler( void ) -{ - /* This is called with interrupts already disabled. */ - - /* Remember what was on the interrupts we are going to use - so we can put them back later if required. */ - pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER ); - - /* Put our manual switch (yield) function on a known - vector. */ - _dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor ); - - #if configUSE_PREEMPTION == 1 - { - /* Put our tick switch function on the timer interrupt. */ - _dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick ); - } - #else - { - /* We want the timer interrupt to just increment the tick count. */ - _dos_setvect( portTIMER_INT_NUMBER, prvNonPreemptiveTick ); - } - #endif - - prvSetTickFrequency( configTICK_RATE_HZ ); - - /* Clean up function if we want to return to DOS. */ - if( setjmp( xJumpBuf ) != 0 ) - { - prvExitFunction(); - sSchedulerRunning = pdFALSE; - } - else - { - sSchedulerRunning = pdTRUE; - - /* Kick off the scheduler by setting up the context of the first task. */ - portFIRST_CONTEXT(); - } - - return sSchedulerRunning; -} -/*-----------------------------------------------------------*/ - -/* The tick ISR used depend on whether or not the preemptive or cooperative -kernel is being used. */ -#if configUSE_PREEMPTION == 1 - static void __interrupt __far prvPreemptiveTick( void ) - { - /* Get the scheduler to update the task states following the tick. */ - vTaskIncrementTick(); - - /* Switch in the context of the next task to be run. */ - portSWITCH_CONTEXT(); - - /* Reset the PIC ready for the next time. */ - portRESET_PIC(); - } -#else - static void __interrupt __far prvNonPreemptiveTick( void ) - { - /* Same as preemptive tick, but the cooperative scheduler is being used - so we don't have to switch in the context of the next task. */ - vTaskIncrementTick(); - portRESET_PIC(); - } -#endif -/*-----------------------------------------------------------*/ - -static void __interrupt __far prvYieldProcessor( void ) -{ - /* Switch in the context of the next task to be run. */ - portSWITCH_CONTEXT(); -} -/*-----------------------------------------------------------*/ - -void vPortEndScheduler( void ) -{ - /* Jump back to the processor state prior to starting the - scheduler. This means we are not going to be using a - task stack frame so the task can be deleted. */ - longjmp( xJumpBuf, 1 ); -} -/*-----------------------------------------------------------*/ - -static void prvExitFunction( void ) -{ -const unsigned portSHORT usTimerDisable = 0x0000; -unsigned portSHORT usTimer0Control; - - /* Interrupts should be disabled here anyway - but no - harm in making sure. */ - portDISABLE_INTERRUPTS(); - if( sSchedulerRunning == pdTRUE ) - { - /* Put back the switch interrupt routines that was in place - before the scheduler started. */ - _dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR ); - } - - /* Disable the timer used for the tick to ensure the scheduler is - not called before restoring interrupts. There was previously nothing - on this timer so there is no old ISR to restore. */ - portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerDisable ); - - /* Restart the DOS tick. */ - usTimer0Control = portINPUT_WORD( portTIMER_0_CONTROL_REGISTER ); - usTimer0Control |= portTIMER_INTERRUPT_ENABLE; - portOUTPUT_WORD( portTIMER_0_CONTROL_REGISTER, usTimer0Control ); - - - portENABLE_INTERRUPTS(); - - /* This will free up all the memory used by the scheduler. - exiting back to dos with INT21 AH=4CH will do this anyway so - it is not necessary to call this. */ - vTaskCleanUpResources(); -} -/*-----------------------------------------------------------*/ - -static void prvSetTickFrequency( unsigned portLONG ulTickRateHz ) -{ -const unsigned portSHORT usMaxCountRegister = 0xff5a; -const unsigned portSHORT usTimerPriorityRegister = 0xff32; -const unsigned portSHORT usTimerEnable = 0xC000; -const unsigned portSHORT usRetrigger = 0x0001; -const unsigned portSHORT usTimerHighPriority = 0x0000; -unsigned portSHORT usTimer0Control; - -/* ( CPU frequency / 4 ) / clock 2 max count [inpw( 0xff62 ) = 7] */ - -const unsigned portLONG ulClockFrequency = 0x7f31a0; - -unsigned portLONG ulTimerCount = ulClockFrequency / ulTickRateHz; - - portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerEnable | portTIMER_INTERRUPT_ENABLE | usRetrigger ); - portOUTPUT_WORD( usMaxCountRegister, ( unsigned portSHORT ) ulTimerCount ); - portOUTPUT_WORD( usTimerPriorityRegister, usTimerHighPriority ); - - /* Stop the DOS tick - don't do this if you want to maintain a TOD clock. */ - usTimer0Control = portINPUT_WORD( portTIMER_0_CONTROL_REGISTER ); - usTimer0Control &= ~portTIMER_INTERRUPT_ENABLE; - portOUTPUT_WORD( portTIMER_0_CONTROL_REGISTER, usTimer0Control ); -} - - -/*lint +e950 */ - diff --git a/Source/portable/oWatcom/16BitDOS/Flsh186/portmacro.h b/Source/portable/oWatcom/16BitDOS/Flsh186/portmacro.h deleted file mode 100644 index 19d31c99b..000000000 --- a/Source/portable/oWatcom/16BitDOS/Flsh186/portmacro.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -/*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the - * given hardware and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - - -/* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE long -#define portLONG long -#define portSHORT int -#define portSTACK_TYPE unsigned portSHORT -#define portBASE_TYPE portSHORT - -#if( configUSE_16_BIT_TICKS == 1 ) - typedef unsigned portSHORT portTickType; - #define portMAX_DELAY ( portTickType ) 0xffff -#else - typedef unsigned portLONG portTickType; - #define portMAX_DELAY ( portTickType ) 0xffffffff -#endif -/*-----------------------------------------------------------*/ - -/* Critical section management. */ -void portENTER_CRITICAL( void ); -#pragma aux portENTER_CRITICAL = "pushf" \ - "cli"; - -void portEXIT_CRITICAL( void ); -#pragma aux portEXIT_CRITICAL = "popf"; - -void portDISABLE_INTERRUPTS( void ); -#pragma aux portDISABLE_INTERRUPTS = "cli"; - -void portENABLE_INTERRUPTS( void ); -#pragma aux portENABLE_INTERRUPTS = "sti"; -/*-----------------------------------------------------------*/ - -/* Architecture specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portSWITCH_INT_NUMBER 0x80 -#define portYIELD() __asm{ int portSWITCH_INT_NUMBER } -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 2 -#define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */ -#define portNOP() __asm{ nop } -/*-----------------------------------------------------------*/ - -/* Compiler specifics. */ -#define portINPUT_BYTE( xAddr ) inp( xAddr ) -#define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue ) -#define portINPUT_WORD( xAddr ) inpw( xAddr ) -#define portOUTPUT_WORD( xAddr, usValue ) outpw( xAddr, usValue ) -#define inline -/*-----------------------------------------------------------*/ - -/* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) - - -#endif /* PORTMACRO_H */ - diff --git a/Source/portable/oWatcom/16BitDOS/PC/port.c b/Source/portable/oWatcom/16BitDOS/PC/port.c deleted file mode 100644 index 1c7c4a689..000000000 --- a/Source/portable/oWatcom/16BitDOS/PC/port.c +++ /dev/null @@ -1,311 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V1.00: - - + Call to taskYIELD() from within tick ISR has been replaced by the more - efficient portSWITCH_CONTEXT(). - + ISR function definitions renamed to include the prv prefix. - -Changes from V1.2.0: - - + prvPortResetPIC() is now called last thing before the end of the - preemptive tick routine. - -Changes from V2.6.1 - - + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION - macro to be consistent with the later ports. - -Changes from V4.0.1 - - + Add function prvSetTickFrequencyDefault() to set the DOS tick back to - its proper value when the scheduler exits. -*/ - -#include -#include -#include -#include -#include - -#include "FreeRTOS.h" -#include "task.h" -#include "portasm.h" - -/*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the industrial - * PC port. - *----------------------------------------------------------*/ - -/*lint -e950 Non ANSI reserved words okay in this file only. */ - -#define portTIMER_INT_NUMBER 0x08 - -/* Setup hardware for required tick interrupt rate. */ -static void prvSetTickFrequency( unsigned portLONG ulTickRateHz ); - -/* Restore hardware to as it was prior to starting the scheduler. */ -static void prvExitFunction( void ); - -/* Either chain to the DOS tick (which itself clears the PIC) or clear the PIC -directly. We chain to the DOS tick as close as possible to the standard DOS -tick rate. */ -static void prvPortResetPIC( void ); - -/* The tick ISR used depends on whether the preemptive or cooperative scheduler -is being used. */ -#if configUSE_PREEMPTION == 1 - /* Tick service routine used by the scheduler when preemptive scheduling is - being used. */ - static void __interrupt __far prvPreemptiveTick( void ); -#else - /* Tick service routine used by the scheduler when cooperative scheduling is - being used. */ - static void __interrupt __far prvNonPreemptiveTick( void ); -#endif -/* Trap routine used by taskYIELD() to manually cause a context switch. */ -static void __interrupt __far prvYieldProcessor( void ); - -/* Set the tick frequency back so the floppy drive works correctly when the -scheduler exits. */ -static void prvSetTickFrequencyDefault( void ); - -/*lint -e956 File scopes necessary here. */ - -/* Used to signal when to chain to the DOS tick, and when to just clear the PIC ourselves. */ -static portSHORT sDOSTickCounter; - -/* Set true when the vectors are set so the scheduler will service the tick. */ -static portSHORT sSchedulerRunning = pdFALSE; - -/* Points to the original routine installed on the vector we use for manual context switches. This is then used to restore the original routine during prvExitFunction(). */ -static void ( __interrupt __far *pxOldSwitchISR )(); - -/* Points to the original routine installed on the vector we use to chain to the DOS tick. This is then used to restore the original routine during prvExitFunction(). */ -static void ( __interrupt __far *pxOldSwitchISRPlus1 )(); - -/* Used to restore the original DOS context when the scheduler is ended. */ -static jmp_buf xJumpBuf; - -/*lint +e956 */ - -/*-----------------------------------------------------------*/ -portBASE_TYPE xPortStartScheduler( void ) -{ -pxISR pxOriginalTickISR; - - /* This is called with interrupts already disabled. */ - - /* Remember what was on the interrupts we are going to use - so we can put them back later if required. */ - pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER ); - pxOriginalTickISR = _dos_getvect( portTIMER_INT_NUMBER ); - pxOldSwitchISRPlus1 = _dos_getvect( portSWITCH_INT_NUMBER + 1 ); - - prvSetTickFrequency( configTICK_RATE_HZ ); - - /* Put our manual switch (yield) function on a known - vector. */ - _dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor ); - - /* Put the old tick on a different interrupt number so we can - call it when we want. */ - _dos_setvect( portSWITCH_INT_NUMBER + 1, pxOriginalTickISR ); - - #if configUSE_PREEMPTION == 1 - { - /* Put our tick switch function on the timer interrupt. */ - _dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick ); - } - #else - { - /* We want the timer interrupt to just increment the tick count. */ - _dos_setvect( portTIMER_INT_NUMBER, prvNonPreemptiveTick ); - } - #endif - - /* Setup a counter that is used to call the DOS interrupt as close - to it's original frequency as can be achieved given our chosen tick - frequency. */ - sDOSTickCounter = portTICKS_PER_DOS_TICK; - - /* Clean up function if we want to return to DOS. */ - if( setjmp( xJumpBuf ) != 0 ) - { - prvExitFunction(); - sSchedulerRunning = pdFALSE; - } - else - { - sSchedulerRunning = pdTRUE; - - /* Kick off the scheduler by setting up the context of the first task. */ - portFIRST_CONTEXT(); - } - - return sSchedulerRunning; -} -/*-----------------------------------------------------------*/ - -/* The tick ISR used depends on whether the preemptive or cooperative scheduler -is being used. */ -#if configUSE_PREEMPTION == 1 - /* Tick service routine used by the scheduler when preemptive scheduling is - being used. */ - static void __interrupt __far prvPreemptiveTick( void ) - { - /* Get the scheduler to update the task states following the tick. */ - vTaskIncrementTick(); - - /* Switch in the context of the next task to be run. */ - portSWITCH_CONTEXT(); - - /* Reset the PIC ready for the next time. */ - prvPortResetPIC(); - } -#else - static void __interrupt __far prvNonPreemptiveTick( void ) - { - /* Same as preemptive tick, but the cooperative scheduler is being used - so we don't have to switch in the context of the next task. */ - vTaskIncrementTick(); - prvPortResetPIC(); - } -#endif -/*-----------------------------------------------------------*/ - - -static void __interrupt __far prvYieldProcessor( void ) -{ - /* Switch in the context of the next task to be run. */ - portSWITCH_CONTEXT(); -} -/*-----------------------------------------------------------*/ - -static void prvPortResetPIC( void ) -{ - /* We are going to call the DOS tick interrupt at as close a - frequency to the normal DOS tick as possible. */ - - /* WE SHOULD NOT DO THIS IF YIELD WAS CALLED. */ - --sDOSTickCounter; - if( sDOSTickCounter <= 0 ) - { - sDOSTickCounter = ( portSHORT ) portTICKS_PER_DOS_TICK; - __asm{ int portSWITCH_INT_NUMBER + 1 }; - } - else - { - /* Reset the PIC as the DOS tick is not being called to - do it. */ - __asm - { - mov al, 20H - out 20H, al - }; - } -} -/*-----------------------------------------------------------*/ - -void vPortEndScheduler( void ) -{ - /* Jump back to the processor state prior to starting the - scheduler. This means we are not going to be using a - task stack frame so the task can be deleted. */ - longjmp( xJumpBuf, 1 ); -} -/*-----------------------------------------------------------*/ - -static void prvExitFunction( void ) -{ -void ( __interrupt __far *pxOriginalTickISR )(); - - /* Interrupts should be disabled here anyway - but no - harm in making sure. */ - portDISABLE_INTERRUPTS(); - if( sSchedulerRunning == pdTRUE ) - { - /* Set the DOS tick back onto the timer ticker. */ - pxOriginalTickISR = _dos_getvect( portSWITCH_INT_NUMBER + 1 ); - _dos_setvect( portTIMER_INT_NUMBER, pxOriginalTickISR ); - prvSetTickFrequencyDefault(); - - /* Put back the switch interrupt routines that was in place - before the scheduler started. */ - _dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR ); - _dos_setvect( portSWITCH_INT_NUMBER + 1, pxOldSwitchISRPlus1 ); - } - /* The tick timer is back how DOS wants it. We can re-enable - interrupts without the scheduler being called. */ - portENABLE_INTERRUPTS(); - - /* This will free up all the memory used by the scheduler. - exiting back to dos with INT21 AH=4CH will do this anyway so - it is not necessary to call this. */ - vTaskCleanUpResources(); -} -/*-----------------------------------------------------------*/ - -static void prvSetTickFrequency( unsigned portLONG ulTickRateHz ) -{ -const unsigned portSHORT usPIT_MODE = ( unsigned portSHORT ) 0x43; -const unsigned portSHORT usPIT0 = ( unsigned portSHORT ) 0x40; -const unsigned portLONG ulPIT_CONST = ( unsigned portLONG ) 1193180; -const unsigned portSHORT us8254_CTR0_MODE3 = ( unsigned portSHORT ) 0x36; -unsigned portLONG ulOutput; - - /* Setup the 8245 to tick at the wanted frequency. */ - portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 ); - ulOutput = ulPIT_CONST / ulTickRateHz; - - portOUTPUT_BYTE( usPIT0, ( unsigned portSHORT )( ulOutput & ( unsigned portLONG ) 0xff ) ); - ulOutput >>= 8; - portOUTPUT_BYTE( usPIT0, ( unsigned portSHORT ) ( ulOutput & ( unsigned portLONG ) 0xff ) ); -} -/*-----------------------------------------------------------*/ - -static void prvSetTickFrequencyDefault( void ) -{ -const unsigned portSHORT usPIT_MODE = ( unsigned portSHORT ) 0x43; -const unsigned portSHORT usPIT0 = ( unsigned portSHORT ) 0x40; -const unsigned portSHORT us8254_CTR0_MODE3 = ( unsigned portSHORT ) 0x36; - - portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 ); - portOUTPUT_BYTE( usPIT0,0 ); - portOUTPUT_BYTE( usPIT0,0 ); -} - - -/*lint +e950 */ - diff --git a/Source/portable/oWatcom/16BitDOS/PC/portmacro.h b/Source/portable/oWatcom/16BitDOS/PC/portmacro.h deleted file mode 100644 index 4b68ca0f9..000000000 --- a/Source/portable/oWatcom/16BitDOS/PC/portmacro.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -/*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the - * given hardware and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - -/* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT int -#define portSTACK_TYPE unsigned portSHORT -#define portBASE_TYPE portSHORT - -#if( configUSE_16_BIT_TICKS == 1 ) - typedef unsigned portSHORT portTickType; - #define portMAX_DELAY ( portTickType ) 0xffff -#else - typedef unsigned portLONG portTickType; - #define portMAX_DELAY ( portTickType ) 0xffffffff -#endif -/*-----------------------------------------------------------*/ - -/* Critical section definitions. */ -void portENTER_CRITICAL( void ); -#pragma aux portENTER_CRITICAL = "pushf" \ - "cli"; -void portEXIT_CRITICAL( void ); -#pragma aux portEXIT_CRITICAL = "popf"; - -void portDISABLE_INTERRUPTS( void ); -#pragma aux portDISABLE_INTERRUPTS = "cli"; - -void portENABLE_INTERRUPTS( void ); -#pragma aux portENABLE_INTERRUPTS = "sti"; -/*-----------------------------------------------------------*/ - -/* Architecture specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portSWITCH_INT_NUMBER 0x80 -#define portYIELD() __asm{ int portSWITCH_INT_NUMBER } -#define portDOS_TICK_RATE ( 18.20648 ) -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) -#define portTICKS_PER_DOS_TICK ( ( unsigned portSHORT ) ( ( ( portDOUBLE ) configTICK_RATE_HZ / portDOS_TICK_RATE ) + 0.5 ) ) -#define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */ -/*-----------------------------------------------------------*/ - -/* Compiler specifics. */ -#define portINPUT_BYTE( xAddr ) inp( xAddr ) -#define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue ) -#define inline -#define portNOP() __asm{ nop } -/*-----------------------------------------------------------*/ - -/* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters ) -#define portTASK_FUNCTION( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters ) - -#endif /* PORTMACRO_H */ - diff --git a/Source/portable/oWatcom/16BitDOS/common/portasm.h b/Source/portable/oWatcom/16BitDOS/common/portasm.h deleted file mode 100644 index 6b84472f4..000000000 --- a/Source/portable/oWatcom/16BitDOS/common/portasm.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -typedef void tskTCB; -extern volatile tskTCB * volatile pxCurrentTCB; -extern void vTaskSwitchContext( void ); - -/* - * Saves the stack pointer for one task into its TCB, calls - * vTaskSwitchContext() to update the TCB being used, then restores the stack - * from the new TCB read to run the task. - */ -void portSWITCH_CONTEXT( void ); - -/* - * Load the stack pointer from the TCB of the task which is going to be first - * to execute. Then force an IRET so the registers and IP are popped off the - * stack. - */ -void portFIRST_CONTEXT( void ); - -/* There are slightly different versions depending on whether you are building -to include debugger information. If debugger information is used then there -are a couple of extra bytes left of the ISR stack (presumably for use by the -debugger). The true stack pointer is then stored in the bp register. We add -2 to the stack pointer to remove the extra bytes before we restore our context. */ - -#ifdef DEBUG_BUILD - - #pragma aux portSWITCH_CONTEXT = "mov ax, seg pxCurrentTCB" \ - "mov ds, ax" \ - "les bx, pxCurrentTCB" /* Save the stack pointer into the TCB. */ \ - "mov es:0x2[ bx ], ss" \ - "mov es:[ bx ], sp" \ - "call vTaskSwitchContext" /* Perform the switch. */ \ - "mov ax, seg pxCurrentTCB" /* Restore the stack pointer from the TCB. */ \ - "mov ds, ax" \ - "les bx, dword ptr pxCurrentTCB" \ - "mov ss, es:[ bx + 2 ]" \ - "mov sp, es:[ bx ]" \ - "mov bp, sp" /* Prepair the bp register for the restoration of the SP in the compiler generated portion of the ISR */ \ - "add bp, 0x0002" - - - - #pragma aux portFIRST_CONTEXT = "mov ax, seg pxCurrentTCB" \ - "mov ds, ax" \ - "les bx, dword ptr pxCurrentTCB" \ - "mov ss, es:[ bx + 2 ]" \ - "mov sp, es:[ bx ]" \ - "add sp, 0x0002" /* Remove the extra bytes that exist in debug builds before restoring the context. */ \ - "pop ax" \ - "pop ax" \ - "pop es" \ - "pop ds" \ - "popa" \ - "iret" -#else - - #pragma aux portSWITCH_CONTEXT = "mov ax, seg pxCurrentTCB" \ - "mov ds, ax" \ - "les bx, pxCurrentTCB" /* Save the stack pointer into the TCB. */ \ - "mov es:0x2[ bx ], ss" \ - "mov es:[ bx ], sp" \ - "call vTaskSwitchContext" /* Perform the switch. */ \ - "mov ax, seg pxCurrentTCB" /* Restore the stack pointer from the TCB. */ \ - "mov ds, ax" \ - "les bx, dword ptr pxCurrentTCB" \ - "mov ss, es:[ bx + 2 ]" \ - "mov sp, es:[ bx ]" - - - #pragma aux portFIRST_CONTEXT = "mov ax, seg pxCurrentTCB" \ - "mov ds, ax" \ - "les bx, dword ptr pxCurrentTCB" \ - "mov ss, es:[ bx + 2 ]" \ - "mov sp, es:[ bx ]" \ - "pop ax" \ - "pop ax" \ - "pop es" \ - "pop ds" \ - "popa" \ - "iret" -#endif - - diff --git a/Source/portable/oWatcom/16BitDOS/common/portcomn.c b/Source/portable/oWatcom/16BitDOS/common/portcomn.c deleted file mode 100644 index 541b9bc16..000000000 --- a/Source/portable/oWatcom/16BitDOS/common/portcomn.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V1.00: - - + pxPortInitialiseStack() now initialises the stack of new tasks to the - same format used by the compiler. This allows the compiler generated - interrupt mechanism to be used for context switches. - -Changes from V2.4.2: - - + pvPortMalloc and vPortFree have been removed. The projects now use - the definitions from the source/portable/MemMang directory. - -Changes from V2.6.1: - - + usPortCheckFreeStackSpace() has been moved to tasks.c. -*/ - - - -#include -#include "FreeRTOS.h" - -/*-----------------------------------------------------------*/ - -/* See header file for description. */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) -{ -portSTACK_TYPE DS_Reg = 0, *pxOriginalSP; - - /* Place a few bytes of known values on the bottom of the stack. - This is just useful for debugging. */ - - *pxTopOfStack = 0x1111; - pxTopOfStack--; - *pxTopOfStack = 0x2222; - pxTopOfStack--; - *pxTopOfStack = 0x3333; - pxTopOfStack--; - *pxTopOfStack = 0x4444; - pxTopOfStack--; - *pxTopOfStack = 0x5555; - pxTopOfStack--; - - - /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */ - - /* We are going to start the scheduler using a return from interrupt - instruction to load the program counter, so first there would be the - status register and interrupt return address. We make this the start - of the task. */ - *pxTopOfStack = portINITIAL_SW; - pxTopOfStack--; - *pxTopOfStack = FP_SEG( pxCode ); - pxTopOfStack--; - *pxTopOfStack = FP_OFF( pxCode ); - pxTopOfStack--; - - /* We are going to setup the stack for the new task to look like - the stack frame was setup by a compiler generated ISR. We need to know - the address of the existing stack top to place in the SP register within - the stack frame. pxOriginalSP holds SP before (simulated) pusha was - called. */ - pxOriginalSP = pxTopOfStack; - - /* The remaining registers would be pushed on the stack by our context - switch function. These are loaded with values simply to make debugging - easier. */ - *pxTopOfStack = FP_OFF( pvParameters ); /* AX */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xCCCC; /* CX */ - pxTopOfStack--; - *pxTopOfStack = FP_SEG( pvParameters ); /* DX */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xBBBB; /* BX */ - pxTopOfStack--; - *pxTopOfStack = FP_OFF( pxOriginalSP ); /* SP */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xBBBB; /* BP */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x0123; /* SI */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xDDDD; /* DI */ - - /* We need the true data segment. */ - __asm{ MOV DS_Reg, DS }; - - pxTopOfStack--; - *pxTopOfStack = DS_Reg; /* DS */ - - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xEEEE; /* ES */ - - /* The AX register is pushed again twice - don't know why. */ - pxTopOfStack--; - *pxTopOfStack = FP_OFF( pvParameters ); /* AX */ - pxTopOfStack--; - *pxTopOfStack = FP_OFF( pvParameters ); /* AX */ - - - #ifdef DEBUG_BUILD - /* The compiler adds space to each ISR stack if building to - include debug information. Presumably this is used by the - debugger - we don't need to initialise it to anything just - make sure it is there. */ - pxTopOfStack--; - #endif - - /*lint +e950 +e611 +e923 */ - - return pxTopOfStack; -} -/*-----------------------------------------------------------*/ - - diff --git a/Source/portable/readme.txt b/Source/portable/readme.txt deleted file mode 100644 index a20d687e0..000000000 --- a/Source/portable/readme.txt +++ /dev/null @@ -1,19 +0,0 @@ -Each real time kernel port consists of three files that contain the core kernel -components and are common to every port, and one or more files that are -specific to a particular microcontroller and/or compiler. - - -+ The FreeRTOS/Source/Portable/MemMang directory contains the three sample -memory allocators as described on the http://www.FreeRTOS.org WEB site. - -+ The other directories each contain files specific to a particular -microcontroller or compiler. - - - -For example, if you are interested in the GCC port for the ATMega323 -microcontroller then the port specific files are contained in -FreeRTOS/Source/Portable/GCC/ATMega323 directory. If this is the only -port you are interested in then all the other directories can be -ignored. - diff --git a/Source/queue.c b/Source/queue.c deleted file mode 100644 index 009e68360..000000000 --- a/Source/queue.c +++ /dev/null @@ -1,927 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V1.01 - - + More use of 8bit data types. - + Function name prefixes changed where the data type returned has changed. - -Changed from V2.0.0 - - + Added the queue locking mechanism and make more use of the scheduler - suspension feature to minimise the time interrupts have to be disabled - when accessing a queue. - -Changed from V2.2.0 - - + Explicit use of 'signed' qualifier on portCHAR types added. - -Changes from V3.0.0 - - + API changes as described on the FreeRTOS.org WEB site. - -Changes from V3.2.3 - - + Added the queue functions that can be used from co-routines. - -Changes from V4.0.5 - - + Added a loop within xQueueSend() and xQueueReceive() to prevent the - functions exiting when a block time remains and the function has - not completed. - -Changes from V4.1.2: - - + BUG FIX: Removed the call to prvIsQueueEmpty from within xQueueCRReceive - as it exited with interrupts enabled. Thanks Paul Katz. - -Changes from V4.1.3: - - + Modified xQueueSend() and xQueueReceive() to handle the (very unlikely) - case whereby a task unblocking due to a temporal event can remove/send an - item from/to a queue when a higher priority task is still blocked on the - queue. This modification is a result of the SafeRTOS testing. -*/ - -#include -#include -#include "FreeRTOS.h" -#include "task.h" -#include "croutine.h" - -/*----------------------------------------------------------- - * PUBLIC LIST API documented in list.h - *----------------------------------------------------------*/ - -/* Constants used with the cRxLock and cTxLock structure members. */ -#define queueUNLOCKED ( ( signed portBASE_TYPE ) -1 ) -#define queueERRONEOUS_UNBLOCK ( -1 ) - -/* - * Definition of the queue used by the scheduler. - * Items are queued by copy, not reference. - */ -typedef struct QueueDefinition -{ - signed portCHAR *pcHead; /*< Points to the beginning of the queue storage area. */ - signed portCHAR *pcTail; /*< Points to the byte at the end of the queue storage area. Once more byte is allocated than necessary to store the queue items, this is used as a marker. */ - - signed portCHAR *pcWriteTo; /*< Points to the free next place in the storage area. */ - signed portCHAR *pcReadFrom; /*< Points to the last place that a queued item was read from. */ - - xList xTasksWaitingToSend; /*< List of tasks that are blocked waiting to post onto this queue. Stored in priority order. */ - xList xTasksWaitingToReceive; /*< List of tasks that are blocked waiting to read from this queue. Stored in priority order. */ - - unsigned portBASE_TYPE uxMessagesWaiting;/*< The number of items currently in the queue. */ - unsigned portBASE_TYPE uxLength; /*< The length of the queue defined as the number of items it will hold, not the number of bytes. */ - unsigned portBASE_TYPE uxItemSize; /*< The size of each items that the queue will hold. */ - - signed portBASE_TYPE xRxLock; /*< Stores the number of items received from the queue (removed from the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */ - signed portBASE_TYPE xTxLock; /*< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */ -} xQUEUE; -/*-----------------------------------------------------------*/ - -/* - * Inside this file xQueueHandle is a pointer to a xQUEUE structure. - * To keep the definition private the API header file defines it as a - * pointer to void. - */ -typedef xQUEUE * xQueueHandle; - -/* - * Prototypes for public functions are included here so we don't have to - * include the API header file (as it defines xQueueHandle differently). These - * functions are documented in the API header file. - */ -xQueueHandle xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize ); -signed portBASE_TYPE xQueueSend( xQueueHandle xQueue, const void * pvItemToQueue, portTickType xTicksToWait ); -unsigned portBASE_TYPE uxQueueMessagesWaiting( xQueueHandle pxQueue ); -void vQueueDelete( xQueueHandle xQueue ); -signed portBASE_TYPE xQueueSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xTaskPreviouslyWoken ); -signed portBASE_TYPE xQueueReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait ); -signed portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken ); - -#if configUSE_CO_ROUTINES == 1 - signed portBASE_TYPE xQueueCRSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xCoRoutinePreviouslyWoken ); - signed portBASE_TYPE xQueueCRReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken ); - signed portBASE_TYPE xQueueCRSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait ); - signed portBASE_TYPE xQueueCRReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait ); -#endif - -/* - * Unlocks a queue locked by a call to prvLockQueue. Locking a queue does not - * prevent an ISR from adding or removing items to the queue, but does prevent - * an ISR from removing tasks from the queue event lists. If an ISR finds a - * queue is locked it will instead increment the appropriate queue lock count - * to indicate that a task may require unblocking. When the queue in unlocked - * these lock counts are inspected, and the appropriate action taken. - */ -static void prvUnlockQueue( xQueueHandle pxQueue ); - -/* - * Uses a critical section to determine if there is any data in a queue. - * - * @return pdTRUE if the queue contains no items, otherwise pdFALSE. - */ -static signed portBASE_TYPE prvIsQueueEmpty( const xQueueHandle pxQueue ); - -/* - * Uses a critical section to determine if there is any space in a queue. - * - * @return pdTRUE if there is no space, otherwise pdFALSE; - */ -static signed portBASE_TYPE prvIsQueueFull( const xQueueHandle pxQueue ); - -/* - * Macro that copies an item into the queue. This is done by copying the item - * byte for byte, not by reference. Updates the queue state to ensure it's - * integrity after the copy. - */ -#define prvCopyQueueData( pxQueue, pvItemToQueue ) \ -{ \ - memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( unsigned ) pxQueue->uxItemSize ); \ - ++( pxQueue->uxMessagesWaiting ); \ - pxQueue->pcWriteTo += pxQueue->uxItemSize; \ - if( pxQueue->pcWriteTo >= pxQueue->pcTail ) \ - { \ - pxQueue->pcWriteTo = pxQueue->pcHead; \ - } \ -} -/*-----------------------------------------------------------*/ - -/* - * Macro to mark a queue as locked. Locking a queue prevents an ISR from - * accessing the queue event lists. - */ -#define prvLockQueue( pxQueue ) \ -{ \ - taskENTER_CRITICAL(); \ - ++( pxQueue->xRxLock ); \ - ++( pxQueue->xTxLock ); \ - taskEXIT_CRITICAL(); \ -} -/*-----------------------------------------------------------*/ - - -/*----------------------------------------------------------- - * PUBLIC QUEUE MANAGEMENT API documented in queue.h - *----------------------------------------------------------*/ - -xQueueHandle xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize ) -{ -xQUEUE *pxNewQueue; -size_t xQueueSizeInBytes; - - /* Allocate the new queue structure. */ - if( uxQueueLength > ( unsigned portBASE_TYPE ) 0 ) - { - pxNewQueue = ( xQUEUE * ) pvPortMalloc( sizeof( xQUEUE ) ); - if( pxNewQueue != NULL ) - { - /* Create the list of pointers to queue items. The queue is one byte - longer than asked for to make wrap checking easier/faster. */ - xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ) + ( size_t ) 1; - - pxNewQueue->pcHead = ( signed portCHAR * ) pvPortMalloc( xQueueSizeInBytes ); - if( pxNewQueue->pcHead != NULL ) - { - /* Initialise the queue members as described above where the - queue type is defined. */ - pxNewQueue->pcTail = pxNewQueue->pcHead + ( uxQueueLength * uxItemSize ); - pxNewQueue->uxMessagesWaiting = 0; - pxNewQueue->pcWriteTo = pxNewQueue->pcHead; - pxNewQueue->pcReadFrom = pxNewQueue->pcHead + ( ( uxQueueLength - 1 ) * uxItemSize ); - pxNewQueue->uxLength = uxQueueLength; - pxNewQueue->uxItemSize = uxItemSize; - pxNewQueue->xRxLock = queueUNLOCKED; - pxNewQueue->xTxLock = queueUNLOCKED; - - /* Likewise ensure the event queues start with the correct state. */ - vListInitialise( &( pxNewQueue->xTasksWaitingToSend ) ); - vListInitialise( &( pxNewQueue->xTasksWaitingToReceive ) ); - - return pxNewQueue; - } - else - { - vPortFree( pxNewQueue ); - } - } - } - - /* Will only reach here if we could not allocate enough memory or no memory - was required. */ - return NULL; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xQueueSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait ) -{ -signed portBASE_TYPE xReturn = pdPASS; -xTimeOutType xTimeOut; - - /* Make sure other tasks do not access the queue. */ - vTaskSuspendAll(); - - /* Capture the current time status for future reference. */ - vTaskSetTimeOutState( &xTimeOut ); - - /* It is important that this is the only thread/ISR that modifies the - ready or delayed lists until xTaskResumeAll() is called. Places where - the ready/delayed lists are modified include: - - + vTaskDelay() - Nothing can call vTaskDelay as the scheduler is - suspended, vTaskDelay() cannot be called from an ISR. - + vTaskPrioritySet() - Has a critical section around the access. - + vTaskSwitchContext() - This will not get executed while the scheduler - is suspended. - + prvCheckDelayedTasks() - This will not get executed while the - scheduler is suspended. - + xTaskCreate() - Has a critical section around the access. - + vTaskResume() - Has a critical section around the access. - + xTaskResumeAll() - Has a critical section around the access. - + xTaskRemoveFromEventList - Checks to see if the scheduler is - suspended. If so then the TCB being removed from the event is - removed from the event and added to the xPendingReadyList. - */ - - /* Make sure interrupts do not access the queue event list. */ - prvLockQueue( pxQueue ); - - /* It is important that interrupts to not access the event list of the - queue being modified here. Places where the event list is modified - include: - - + xQueueSendFromISR(). This checks the lock on the queue to see if - it has access. If the queue is locked then the Tx lock count is - incremented to signify that a task waiting for data can be made ready - once the queue lock is removed. If the queue is not locked then - a task can be moved from the event list, but will not be removed - from the delayed list or placed in the ready list until the scheduler - is unlocked. - - + xQueueReceiveFromISR(). As per xQueueSendFromISR(). - */ - - /* If the queue is already full we may have to block. */ - do - { - if( prvIsQueueFull( pxQueue ) ) - { - /* The queue is full - do we want to block or just leave without - posting? */ - if( xTicksToWait > ( portTickType ) 0 ) - { - /* We are going to place ourselves on the xTasksWaitingToSend event - list, and will get woken should the delay expire, or space become - available on the queue. - - As detailed above we do not require mutual exclusion on the event - list as nothing else can modify it or the ready lists while we - have the scheduler suspended and queue locked. - - It is possible that an ISR has removed data from the queue since we - checked if any was available. If this is the case then the data - will have been copied from the queue, and the queue variables - updated, but the event list will not yet have been checked to see if - anything is waiting as the queue is locked. */ - vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait ); - - /* Force a context switch now as we are blocked. We can do - this from within a critical section as the task we are - switching to has its own context. When we return here (i.e. we - unblock) we will leave the critical section as normal. - - It is possible that an ISR has caused an event on an unrelated and - unlocked queue. If this was the case then the event list for that - queue will have been updated but the ready lists left unchanged - - instead the readied task will have been added to the pending ready - list. */ - taskENTER_CRITICAL(); - { - /* We can safely unlock the queue and scheduler here as - interrupts are disabled. We must not yield with anything - locked, but we can yield from within a critical section. - - Tasks that have been placed on the pending ready list cannot - be tasks that are waiting for events on this queue. See - in comment xTaskRemoveFromEventList(). */ - prvUnlockQueue( pxQueue ); - - /* Resuming the scheduler may cause a yield. If so then there - is no point yielding again here. */ - if( !xTaskResumeAll() ) - { - taskYIELD(); - } - - /* We want to check to see if the queue is still full - before leaving the critical section. This is to prevent - this task placing an item into the queue due to an - interrupt making space on the queue between critical - sections (when there might be a higher priority task - blocked on the queue that cannot run yet because the - scheduler gets suspended). */ - if( pxQueue->uxMessagesWaiting == pxQueue->uxLength ) - { - /* We unblocked but there is no space in the queue, - we probably timed out. */ - xReturn = errQUEUE_FULL; - } - - /* Before leaving the critical section we have to ensure - exclusive access again. */ - vTaskSuspendAll(); - prvLockQueue( pxQueue ); - } - taskEXIT_CRITICAL(); - } - } - - /* If xReturn is errQUEUE_FULL then we unblocked when the queue - was still full. Don't check it again now as it is possible that - an interrupt has removed an item from the queue since we left the - critical section and we don't want to write to the queue in case - there is a task of higher priority blocked waiting for space to - be available on the queue. If this is the case the higher priority - task will execute when the scheduler is unsupended. */ - if( xReturn != errQUEUE_FULL ) - { - /* When we are here it is possible that we unblocked as space became - available on the queue. It is also possible that an ISR posted to the - queue since we left the critical section, so it may be that again there - is no space. This would only happen if a task and ISR post onto the - same queue. */ - taskENTER_CRITICAL(); - { - if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) - { - /* There is room in the queue, copy the data into the queue. */ - prvCopyQueueData( pxQueue, pvItemToQueue ); - xReturn = pdPASS; - - /* Update the TxLock count so prvUnlockQueue knows to check for - tasks waiting for data to become available in the queue. */ - ++( pxQueue->xTxLock ); - } - else - { - xReturn = errQUEUE_FULL; - } - } - taskEXIT_CRITICAL(); - } - - if( xReturn == errQUEUE_FULL ) - { - if( xTicksToWait > 0 ) - { - if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) - { - xReturn = queueERRONEOUS_UNBLOCK; - } - } - } - } - while( xReturn == queueERRONEOUS_UNBLOCK ); - - prvUnlockQueue( pxQueue ); - xTaskResumeAll(); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xQueueSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xTaskPreviouslyWoken ) -{ - /* Similar to xQueueSend, except we don't block if there is no room in the - queue. Also we don't directly wake a task that was blocked on a queue - read, instead we return a flag to say whether a context switch is required - or not (i.e. has a task with a higher priority than us been woken by this - post). */ - if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) - { - prvCopyQueueData( pxQueue, pvItemToQueue ); - - /* If the queue is locked we do not alter the event list. This will - be done when the queue is unlocked later. */ - if( pxQueue->xTxLock == queueUNLOCKED ) - { - /* We only want to wake one task per ISR, so check that a task has - not already been woken. */ - if( !xTaskPreviouslyWoken ) - { - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) ) - { - if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) - { - /* The task waiting has a higher priority so record that a - context switch is required. */ - return pdTRUE; - } - } - } - } - else - { - /* Increment the lock count so the task that unlocks the queue - knows that data was posted while it was locked. */ - ++( pxQueue->xTxLock ); - } - } - - return xTaskPreviouslyWoken; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xQueueReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait ) -{ -signed portBASE_TYPE xReturn = pdTRUE; -xTimeOutType xTimeOut; - - /* This function is very similar to xQueueSend(). See comments within - xQueueSend() for a more detailed explanation. - - Make sure other tasks do not access the queue. */ - vTaskSuspendAll(); - - /* Capture the current time status for future reference. */ - vTaskSetTimeOutState( &xTimeOut ); - - /* Make sure interrupts do not access the queue. */ - prvLockQueue( pxQueue ); - - do - { - /* If there are no messages in the queue we may have to block. */ - if( prvIsQueueEmpty( pxQueue ) ) - { - /* There are no messages in the queue, do we want to block or just - leave with nothing? */ - if( xTicksToWait > ( portTickType ) 0 ) - { - vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); - taskENTER_CRITICAL(); - { - prvUnlockQueue( pxQueue ); - if( !xTaskResumeAll() ) - { - taskYIELD(); - } - - if( pxQueue->uxMessagesWaiting == ( unsigned portBASE_TYPE ) 0 ) - { - /* We unblocked but the queue is empty. We probably - timed out. */ - xReturn = errQUEUE_EMPTY; - } - - vTaskSuspendAll(); - prvLockQueue( pxQueue ); - } - taskEXIT_CRITICAL(); - } - } - - if( xReturn != errQUEUE_EMPTY ) - { - taskENTER_CRITICAL(); - { - if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 ) - { - pxQueue->pcReadFrom += pxQueue->uxItemSize; - if( pxQueue->pcReadFrom >= pxQueue->pcTail ) - { - pxQueue->pcReadFrom = pxQueue->pcHead; - } - --( pxQueue->uxMessagesWaiting ); - memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); - - /* Increment the lock count so prvUnlockQueue knows to check for - tasks waiting for space to become available on the queue. */ - ++( pxQueue->xRxLock ); - xReturn = pdPASS; - } - else - { - xReturn = errQUEUE_EMPTY; - } - } - taskEXIT_CRITICAL(); - } - - if( xReturn == errQUEUE_EMPTY ) - { - if( xTicksToWait > 0 ) - { - if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) - { - xReturn = queueERRONEOUS_UNBLOCK; - } - } - } - } while( xReturn == queueERRONEOUS_UNBLOCK ); - - /* We no longer require exclusive access to the queue. */ - prvUnlockQueue( pxQueue ); - xTaskResumeAll(); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken ) -{ -signed portBASE_TYPE xReturn; - - /* We cannot block from an ISR, so check there is data available. */ - if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 ) - { - /* Copy the data from the queue. */ - pxQueue->pcReadFrom += pxQueue->uxItemSize; - if( pxQueue->pcReadFrom >= pxQueue->pcTail ) - { - pxQueue->pcReadFrom = pxQueue->pcHead; - } - --( pxQueue->uxMessagesWaiting ); - memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); - - /* If the queue is locked we will not modify the event list. Instead - we update the lock count so the task that unlocks the queue will know - that an ISR has removed data while the queue was locked. */ - if( pxQueue->xRxLock == queueUNLOCKED ) - { - /* We only want to wake one task per ISR, so check that a task has - not already been woken. */ - if( !( *pxTaskWoken ) ) - { - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) ) - { - if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) - { - /* The task waiting has a higher priority than us so - force a context switch. */ - *pxTaskWoken = pdTRUE; - } - } - } - } - else - { - /* Increment the lock count so the task that unlocks the queue - knows that data was removed while it was locked. */ - ++( pxQueue->xRxLock ); - } - - xReturn = pdPASS; - } - else - { - xReturn = pdFAIL; - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -unsigned portBASE_TYPE uxQueueMessagesWaiting( xQueueHandle pxQueue ) -{ -unsigned portBASE_TYPE uxReturn; - - taskENTER_CRITICAL(); - uxReturn = pxQueue->uxMessagesWaiting; - taskEXIT_CRITICAL(); - - return uxReturn; -} -/*-----------------------------------------------------------*/ - -void vQueueDelete( xQueueHandle pxQueue ) -{ - vPortFree( pxQueue->pcHead ); - vPortFree( pxQueue ); -} -/*-----------------------------------------------------------*/ - -static void prvUnlockQueue( xQueueHandle pxQueue ) -{ - /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */ - - /* The lock counts contains the number of extra data items placed or - removed from the queue while the queue was locked. When a queue is - locked items can be added or removed, but the event lists cannot be - updated. */ - taskENTER_CRITICAL(); - { - --( pxQueue->xTxLock ); - - /* See if data was added to the queue while it was locked. */ - if( pxQueue->xTxLock > queueUNLOCKED ) - { - pxQueue->xTxLock = queueUNLOCKED; - - /* Data was posted while the queue was locked. Are any tasks - blocked waiting for data to become available? */ - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) ) - { - /* Tasks that are removed from the event list will get added to - the pending ready list as the scheduler is still suspended. */ - if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) - { - /* The task waiting has a higher priority so record that a - context switch is required. */ - vTaskMissedYield(); - } - } - } - } - taskEXIT_CRITICAL(); - - /* Do the same for the Rx lock. */ - taskENTER_CRITICAL(); - { - --( pxQueue->xRxLock ); - - if( pxQueue->xRxLock > queueUNLOCKED ) - { - pxQueue->xRxLock = queueUNLOCKED; - - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) ) - { - if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) - { - vTaskMissedYield(); - } - } - } - } - taskEXIT_CRITICAL(); -} -/*-----------------------------------------------------------*/ - -static signed portBASE_TYPE prvIsQueueEmpty( const xQueueHandle pxQueue ) -{ -signed portBASE_TYPE xReturn; - - taskENTER_CRITICAL(); - xReturn = ( pxQueue->uxMessagesWaiting == ( unsigned portBASE_TYPE ) 0 ); - taskEXIT_CRITICAL(); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -static signed portBASE_TYPE prvIsQueueFull( const xQueueHandle pxQueue ) -{ -signed portBASE_TYPE xReturn; - - taskENTER_CRITICAL(); - xReturn = ( pxQueue->uxMessagesWaiting == pxQueue->uxLength ); - taskEXIT_CRITICAL(); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -#if configUSE_CO_ROUTINES == 1 -signed portBASE_TYPE xQueueCRSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait ) -{ -signed portBASE_TYPE xReturn; - - /* If the queue is already full we may have to block. A critical section - is required to prevent an interrupt removing something from the queue - between the check to see if the queue is full and blocking on the queue. */ - portDISABLE_INTERRUPTS(); - { - if( prvIsQueueFull( pxQueue ) ) - { - /* The queue is full - do we want to block or just leave without - posting? */ - if( xTicksToWait > ( portTickType ) 0 ) - { - /* As this is called from a coroutine we cannot block directly, but - return indicating that we need to block. */ - vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) ); - portENABLE_INTERRUPTS(); - return errQUEUE_BLOCKED; - } - else - { - portENABLE_INTERRUPTS(); - return errQUEUE_FULL; - } - } - } - portENABLE_INTERRUPTS(); - - portNOP(); - - portDISABLE_INTERRUPTS(); - { - if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) - { - /* There is room in the queue, copy the data into the queue. */ - prvCopyQueueData( pxQueue, pvItemToQueue ); - xReturn = pdPASS; - - /* Were any co-routines waiting for data to become available? */ - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) ) - { - /* In this instance the co-routine could be placed directly - into the ready list as we are within a critical section. - Instead the same pending ready list mechansim is used as if - the event were caused from within an interrupt. */ - if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) - { - /* The co-routine waiting has a higher priority so record - that a yield might be appropriate. */ - xReturn = errQUEUE_YIELD; - } - } - } - else - { - xReturn = errQUEUE_FULL; - } - } - portENABLE_INTERRUPTS(); - - return xReturn; -} -#endif -/*-----------------------------------------------------------*/ - -#if configUSE_CO_ROUTINES == 1 -signed portBASE_TYPE xQueueCRReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait ) -{ -signed portBASE_TYPE xReturn; - - /* If the queue is already empty we may have to block. A critical section - is required to prevent an interrupt adding something to the queue - between the check to see if the queue is empty and blocking on the queue. */ - portDISABLE_INTERRUPTS(); - { - if( pxQueue->uxMessagesWaiting == ( unsigned portBASE_TYPE ) 0 ) - { - /* There are no messages in the queue, do we want to block or just - leave with nothing? */ - if( xTicksToWait > ( portTickType ) 0 ) - { - /* As this is a co-routine we cannot block directly, but return - indicating that we need to block. */ - vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) ); - portENABLE_INTERRUPTS(); - return errQUEUE_BLOCKED; - } - else - { - portENABLE_INTERRUPTS(); - return errQUEUE_FULL; - } - } - } - portENABLE_INTERRUPTS(); - - portNOP(); - - portDISABLE_INTERRUPTS(); - { - if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 ) - { - /* Data is available from the queue. */ - pxQueue->pcReadFrom += pxQueue->uxItemSize; - if( pxQueue->pcReadFrom >= pxQueue->pcTail ) - { - pxQueue->pcReadFrom = pxQueue->pcHead; - } - --( pxQueue->uxMessagesWaiting ); - memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); - - xReturn = pdPASS; - - /* Were any co-routines waiting for space to become available? */ - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) ) - { - /* In this instance the co-routine could be placed directly - into the ready list as we are within a critical section. - Instead the same pending ready list mechansim is used as if - the event were caused from within an interrupt. */ - if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) - { - xReturn = errQUEUE_YIELD; - } - } - } - else - { - xReturn = pdFAIL; - } - } - portENABLE_INTERRUPTS(); - - return xReturn; -} -#endif -/*-----------------------------------------------------------*/ - - - -#if configUSE_CO_ROUTINES == 1 -signed portBASE_TYPE xQueueCRSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xCoRoutinePreviouslyWoken ) -{ - /* Cannot block within an ISR so if there is no space on the queue then - exit without doing anything. */ - if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) - { - prvCopyQueueData( pxQueue, pvItemToQueue ); - - /* We only want to wake one co-routine per ISR, so check that a - co-routine has not already been woken. */ - if( !xCoRoutinePreviouslyWoken ) - { - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) ) - { - if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) - { - return pdTRUE; - } - } - } - } - - return xCoRoutinePreviouslyWoken; -} -#endif -/*-----------------------------------------------------------*/ - -#if configUSE_CO_ROUTINES == 1 -signed portBASE_TYPE xQueueCRReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxCoRoutineWoken ) -{ -signed portBASE_TYPE xReturn; - - /* We cannot block from an ISR, so check there is data available. If - not then just leave without doing anything. */ - if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 ) - { - /* Copy the data from the queue. */ - pxQueue->pcReadFrom += pxQueue->uxItemSize; - if( pxQueue->pcReadFrom >= pxQueue->pcTail ) - { - pxQueue->pcReadFrom = pxQueue->pcHead; - } - --( pxQueue->uxMessagesWaiting ); - memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); - - if( !( *pxCoRoutineWoken ) ) - { - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) ) - { - if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) - { - *pxCoRoutineWoken = pdTRUE; - } - } - } - - xReturn = pdPASS; - } - else - { - xReturn = pdFAIL; - } - - return xReturn; -} -#endif -/*-----------------------------------------------------------*/ - diff --git a/Source/readme.txt b/Source/readme.txt deleted file mode 100644 index 01a878152..000000000 --- a/Source/readme.txt +++ /dev/null @@ -1,15 +0,0 @@ -Each real time kernel port consists of three files that contain the core kernel -components and are common to every port, and one or more files that are -specific to a particular microcontroller and or compiler. - -+ The FreeRTOS/Source directory contains the three files that are common to -every port. The kernel is contained within these three files. - -+ The FreeRTOS/Source/Portable directory contains the files that are specific to -a particular microcontroller and or compiler. - -+ The FreeRTOS/Source/include directory contains the real time kernel header -files. - -See the readme file in the FreeRTOS/Source/Portable directory for more -information. \ No newline at end of file diff --git a/Source/tasks.c b/Source/tasks.c deleted file mode 100644 index f4a7f35c7..000000000 --- a/Source/tasks.c +++ /dev/null @@ -1,1860 +0,0 @@ -/* - FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V1.00: - - + Call to portRESTORE_CONTEXT has been removed. The first context - switch is now performed within sPortStartScheduler(). - -Changes from V1.01: - - + More use of 8bit data types. - + Function name prefixes changed where the data type returned has changed. - + configUSE_TRACE_FACILITY is no longer defined by default. - -Changes from V1.2.0 - - + Introduced ucTopReadyPriority. This tracks the highest priority ready - queue that contains a valid TCB and thus makes the context switch - slightly faster. - - + prvAddTaskToReadyQueue() has been made a macro. - -Changes from V1.2.6 - - + Added conditional compilation directives. - + Extended API. - + Rearranged function order. - + Creating a task now causes a context switch if the task being created - has a higher priority than the calling task - assuming the kernel is - running. - + vTaskDelete() now only causes a context switch if the calling task is - the task being deleted. - -Changes from V2.0.0 - - + Allow the type of the tick count to be 16 or 32 bits. - + Introduce xPendingReadyList feature to allow the time interrupts have to - be disabled to be minimised. - + Remove the #if( INCLUDE_vTaskSuspendAll ) statements. vTaskSuspendAll() - is now always included as it is used by the scheduler itself. - -Changes from V2.1.0 - - + Bug fix - pxCurrentTCB is now initialised before the call to - prvInitializeTaskLists(). Previously pxCurrentTCB could be accessed - while null. - -Changed from V2.1.1 - - + Change to where lStackSize is declared within sTaskCreate() to prevent - compiler warnings with 8051 port. - -Changes from V2.2.0 - - + Explicit use of 'signed' qualifier on portCHAR types added. - + Changed odd calculation of initial pxTopOfStack value when - portSTACK_GROWTH < 0. - + Removed pcVersionNumber definition. - -Changes from V2.5.3 - - + cTaskResumeAll() modified to ensure it can be called prior to the task - lists being initialised. - -Changes from V2.5.5 - - + Added API function vTaskDelayUntil(). - + Added INCLUDE_vTaskDelay conditional compilation. - -Changes from V2.6.0 - - + Updated the vWriteTraceToBuffer macro to always be 4 byte aligned so it - can be used on ARM architectures. - + tskMAX_TASK_NAME_LEN definition replaced with the port specific - configMAX_TASK_NAME_LEN definition. - + Removed the call to strcpy when copying across the task name into the - TCB. - + Added ucTasksDeleted variable to prevent vTaskSuspendAll() being called - too often in the idle task. - -Changes between V3.0.0 and V2.6.1 - - + When resuming the scheduler a yield is performed if either a tick has - been missed, or a task is moved from the pending ready list into a ready - list. Previously a yield was not performed on this second condition. - + Introduced the type portBASE_TYPE. This necessitates several API - changes. - + Removed the sUsingPreemption variable. The constant defined in - portmacro.h is now used directly. - + The idle task can now include an optional hook function - and no longer - completes its time slice if other tasks with equal priority to it are - ready to run. - + See the FreeRTOS.org documentation for more information on V2.x.x to - V3.x.x modifications. - -Changes from V3.1.1 - - + Modified vTaskPrioritySet() and vTaskResume() to allow these functions to - be called while the scheduler is suspended. - + Corrected the task ordering within event lists. - -Changes from V3.2.0 - - + Added function xTaskGetCurrentTaskHandle(). - -Changes from V3.2.4 - - + Changed the volatile declarations on some variables to reflect the - changes to the list definitions. - + Changed the order of the TCB definition so there is commonality between - the task control block and a co-routine control block. - + Allow the scheduler to be started even if no tasks other than the idle - task has been created. This allows co-routines to run even when no tasks - have been created. - + The need for a context switch is now signalled if a task woken by an - event has a priority greater or equal to the currently running task. - Previously this was only greater than. - -Changes from V4.0.0 - - + Added the xMissedYield handling. - -Changes from V4.0.1 - - + The function vTaskList() now suspends the scheduler rather than disabling - interrupts during the creation of the task list. - + Allow a task to delete itself by passing in its own handle. Previously - this could only be done by passing in NULL. - + The tick hook function is now called only within a tick isr. Previously - it was also called when the tick function was called during the scheduler - unlocking process. - -Changes from V4.0.3 - - + Extra checks have been placed in vTaskPrioritySet() to avoid unnecessary - yields. - -Changed from V4.0.4 - - + Bug fix: The 'value' of the event list item is updated when the priority - of a task is changed. Previously only the priority of the TCB itself was - changed. - + When resuming a task a check is first made to see if the task is actually - suspended. - + vTaskPrioritySet() and vTaskResume() no longer use the event list item. - This has not been necessary since V4.0.1 when the xMissedYield handling - was added. - + Implement xTaskResumeFromISR(). - -Changes from V4.0.5 - - + Added utility functions and xOverflowCount variable to facilitate the - queue.c changes. - -Changes from V4.1.2 - - + Tasks that block on events with a timeout of portMAX_DELAY are now - blocked indefinitely if configINCLUDE_vTaskSuspend is defined. - Previously portMAX_DELAY was just the longest block time possible. - -Changes from V4.1.3 - - + Very small change made to xTaskCheckForTimeout() as a result of the - SafeRTOS testing. This corrects the case where the function can return an - invalid value - but only in an extremely unlikely scenario. -*/ - -#include -#include -#include - -#include "FreeRTOS.h" -#include "task.h" - -/* - * Macro to define the amount of stack available to the idle task. - */ -#define tskIDLE_STACK_SIZE configMINIMAL_STACK_SIZE - - -/* - * Default a definitions for backwards compatibility with old - * portmacro.h files. - */ -#ifndef configMAX_TASK_NAME_LEN - #define configMAX_TASK_NAME_LEN 16 -#endif - -#ifndef INCLUDE_xTaskGetCurrentTaskHandle - #define INCLUDE_xTaskGetCurrentTaskHandle 0 -#endif - -#ifndef configIDLE_SHOULD_YIELD - #define configIDLE_SHOULD_YIELD 1 -#endif - -#if configMAX_TASK_NAME_LEN < 1 - #undef configMAX_TASK_NAME_LEN - #define configMAX_TASK_NAME_LEN 1 -#endif - -#ifndef INCLUDE_xTaskResumeFromISR - #define INCLUDE_xTaskResumeFromISR 1 -#endif - -/* - * Task control block. A task control block (TCB) is allocated to each task, - * and stores the context of the task. - */ -typedef struct tskTaskControlBlock -{ - volatile portSTACK_TYPE *pxTopOfStack; /*< Points to the location of the last item placed on the tasks stack. THIS MUST BE THE FIRST MEMBER OF THE STRUCT. */ - xListItem xGenericListItem; /*< List item used to place the TCB in ready and blocked queues. */ - xListItem xEventListItem; /*< List item used to place the TCB in event lists. */ - unsigned portBASE_TYPE uxPriority; /*< The priority of the task where 0 is the lowest priority. */ - portSTACK_TYPE *pxStack; /*< Points to the start of the stack. */ - unsigned portBASE_TYPE uxTCBNumber; /*< This is used for tracing the scheduler and making debugging easier only. */ - signed portCHAR pcTaskName[ configMAX_TASK_NAME_LEN ];/*< Descriptive name given to the task when created. Facilitates debugging only. */ - unsigned portSHORT usStackDepth; /*< Total depth of the stack (when empty). This is defined as the number of variables the stack can hold, not the number of bytes. */ -} tskTCB; - -/*lint -e956 */ - -tskTCB * volatile pxCurrentTCB = NULL; - -/* Lists for ready and blocked tasks. --------------------*/ - -static xList pxReadyTasksLists[ configMAX_PRIORITIES ]; /*< Prioritised ready tasks. */ -static xList xDelayedTaskList1; /*< Delayed tasks. */ -static xList xDelayedTaskList2; /*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */ -static xList * volatile pxDelayedTaskList; /*< Points to the delayed task list currently being used. */ -static xList * volatile pxOverflowDelayedTaskList; /*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */ -static xList xPendingReadyList; /*< Tasks that have been readied while the scheduler was suspended. They will be moved to the ready queue when the scheduler is resumed. */ - -#if ( INCLUDE_vTaskDelete == 1 ) - - static volatile xList xTasksWaitingTermination; /*< Tasks that have been deleted - but the their memory not yet freed. */ - static volatile unsigned portBASE_TYPE uxTasksDeleted = ( unsigned portBASE_TYPE ) 0; - -#endif - -#if ( INCLUDE_vTaskSuspend == 1 ) - - static xList xSuspendedTaskList; /*< Tasks that are currently suspended. */ - -#endif - -/* File private variables. --------------------------------*/ -static volatile unsigned portBASE_TYPE uxCurrentNumberOfTasks = ( unsigned portBASE_TYPE ) 0; -static volatile portTickType xTickCount = ( portTickType ) 0; -static unsigned portBASE_TYPE uxTopUsedPriority = tskIDLE_PRIORITY; -static volatile unsigned portBASE_TYPE uxTopReadyPriority = tskIDLE_PRIORITY; -static volatile signed portBASE_TYPE xSchedulerRunning = pdFALSE; -static volatile unsigned portBASE_TYPE uxSchedulerSuspended = ( unsigned portBASE_TYPE ) pdFALSE; -static volatile unsigned portBASE_TYPE uxMissedTicks = ( unsigned portBASE_TYPE ) 0; -static volatile portBASE_TYPE xMissedYield = ( portBASE_TYPE ) pdFALSE; -static volatile portBASE_TYPE xNumOfOverflows = ( portBASE_TYPE ) 0; -/* Debugging and trace facilities private variables and macros. ------------*/ - -/* - * The value used to fill the stack of a task when the task is created. This - * is used purely for checking the high water mark for tasks. - */ -#define tskSTACK_FILL_BYTE ( 0xa5 ) - -/* - * Macros used by vListTask to indicate which state a task is in. - */ -#define tskBLOCKED_CHAR ( ( signed portCHAR ) 'B' ) -#define tskREADY_CHAR ( ( signed portCHAR ) 'R' ) -#define tskDELETED_CHAR ( ( signed portCHAR ) 'D' ) -#define tskSUSPENDED_CHAR ( ( signed portCHAR ) 'S' ) - -/* - * Macros and private variables used by the trace facility. - */ -#if ( configUSE_TRACE_FACILITY == 1 ) - - #define tskSIZE_OF_EACH_TRACE_LINE ( ( unsigned portLONG ) ( sizeof( unsigned portLONG ) + sizeof( unsigned portLONG ) ) ) - static volatile signed portCHAR * volatile pcTraceBuffer; - static signed portCHAR *pcTraceBufferStart; - static signed portCHAR *pcTraceBufferEnd; - static signed portBASE_TYPE xTracing = pdFALSE; - -#endif - -/* - * Macro that writes a trace of scheduler activity to a buffer. This trace - * shows which task is running when and is very useful as a debugging tool. - * As this macro is called each context switch it is a good idea to undefine - * it if not using the facility. - */ -#if ( configUSE_TRACE_FACILITY == 1 ) - - #define vWriteTraceToBuffer() \ - { \ - if( xTracing ) \ - { \ - static unsigned portBASE_TYPE uxPreviousTask = 255; \ - \ - if( uxPreviousTask != pxCurrentTCB->uxTCBNumber ) \ - { \ - if( ( pcTraceBuffer + tskSIZE_OF_EACH_TRACE_LINE ) < pcTraceBufferEnd ) \ - { \ - uxPreviousTask = pxCurrentTCB->uxTCBNumber; \ - *( unsigned portLONG * ) pcTraceBuffer = ( unsigned portLONG ) xTickCount; \ - pcTraceBuffer += sizeof( unsigned portLONG ); \ - *( unsigned portLONG * ) pcTraceBuffer = ( unsigned portLONG ) uxPreviousTask; \ - pcTraceBuffer += sizeof( unsigned portLONG ); \ - } \ - else \ - { \ - xTracing = pdFALSE; \ - } \ - } \ - } \ - } - -#else - - #define vWriteTraceToBuffer() - -#endif - - -/* - * Place the task represented by pxTCB into the appropriate ready queue for - * the task. It is inserted at the end of the list. One quirk of this is - * that if the task being inserted is at the same priority as the currently - * executing task, then it will only be rescheduled after the currently - * executing task has been rescheduled. - */ -#define prvAddTaskToReadyQueue( pxTCB ) \ -{ \ - if( pxTCB->uxPriority > uxTopReadyPriority ) \ - { \ - uxTopReadyPriority = pxTCB->uxPriority; \ - } \ - vListInsertEnd( ( xList * ) &( pxReadyTasksLists[ pxTCB->uxPriority ] ), &( pxTCB->xGenericListItem ) ); \ -} - -/* - * Macro that looks at the list of tasks that are currently delayed to see if - * any require waking. - * - * Tasks are stored in the queue in the order of their wake time - meaning - * once one tasks has been found whose timer has not expired we need not look - * any further down the list. - */ -#define prvCheckDelayedTasks() \ -{ \ -register tskTCB *pxTCB; \ - \ - while( ( pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ) ) != NULL ) \ - { \ - if( xTickCount < listGET_LIST_ITEM_VALUE( &( pxTCB->xGenericListItem ) ) ) \ - { \ - break; \ - } \ - vListRemove( &( pxTCB->xGenericListItem ) ); \ - /* Is the task waiting on an event also? */ \ - if( pxTCB->xEventListItem.pvContainer ) \ - { \ - vListRemove( &( pxTCB->xEventListItem ) ); \ - } \ - prvAddTaskToReadyQueue( pxTCB ); \ - } \ -} - -/* - * Several functions take an xTaskHandle parameter that can optionally be NULL, - * where NULL is used to indicate that the handle of the currently executing - * task should be used in place of the parameter. This macro simply checks to - * see if the parameter is NULL and returns a pointer to the appropriate TCB. - */ -#define prvGetTCBFromHandle( pxHandle ) ( ( pxHandle == NULL ) ? ( tskTCB * ) pxCurrentTCB : ( tskTCB * ) pxHandle ) - - -/* File private functions. --------------------------------*/ - -/* - * Utility to ready a TCB for a given task. Mainly just copies the parameters - * into the TCB structure. - */ -static void prvInitialiseTCBVariables( tskTCB *pxTCB, unsigned portSHORT usStackDepth, const signed portCHAR * const pcName, unsigned portBASE_TYPE uxPriority ); - -/* - * Utility to ready all the lists used by the scheduler. This is called - * automatically upon the creation of the first task. - */ -static void prvInitialiseTaskLists( void ); - -/* - * The idle task, which as all tasks is implemented as a never ending loop. - * The idle task is automatically created and added to the ready lists upon - * creation of the first user task. - * - * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific - * language extensions. The equivalent prototype for this function is: - * - * void prvIdleTask( void *pvParameters ); - * - */ -static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters ); - -/* - * Utility to free all memory allocated by the scheduler to hold a TCB, - * including the stack pointed to by the TCB. - * - * This does not free memory allocated by the task itself (i.e. memory - * allocated by calls to pvPortMalloc from within the tasks application code). - */ -#if ( ( INCLUDE_vTaskDelete == 1 ) || ( INCLUDE_vTaskCleanUpResources == 1 ) ) - static void prvDeleteTCB( tskTCB *pxTCB ); -#endif - -/* - * Used only by the idle task. This checks to see if anything has been placed - * in the list of tasks waiting to be deleted. If so the task is cleaned up - * and its TCB deleted. - */ -static void prvCheckTasksWaitingTermination( void ); - -/* - * Allocates memory from the heap for a TCB and associated stack. Checks the - * allocation was successful. - */ -static tskTCB *prvAllocateTCBAndStack( unsigned portSHORT usStackDepth ); - -/* - * Called from vTaskList. vListTasks details all the tasks currently under - * control of the scheduler. The tasks may be in one of a number of lists. - * prvListTaskWithinSingleList accepts a list and details the tasks from - * within just that list. - * - * THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM - * NORMAL APPLICATION CODE. - */ -#if ( configUSE_TRACE_FACILITY == 1 ) - - static void prvListTaskWithinSingleList( signed portCHAR *pcWriteBuffer, xList *pxList, signed portCHAR cStatus ); - -#endif - -/* - * When a task is created, the stack of the task is filled with a known value. - * This function determines the 'high water mark' of the task stack by - * determining how much of the stack remains at the original preset value. - */ -#if ( configUSE_TRACE_FACILITY == 1 ) - - unsigned portSHORT usTaskCheckFreeStackSpace( const unsigned portCHAR *pucStackByte ); - -#endif - -/*lint +e956 */ - - - - - -/*----------------------------------------------------------- - * TASK CREATION API documented in task.h - *----------------------------------------------------------*/ - -signed portBASE_TYPE xTaskCreate( pdTASK_CODE pvTaskCode, const signed portCHAR * const pcName, unsigned portSHORT usStackDepth, void *pvParameters, unsigned portBASE_TYPE uxPriority, xTaskHandle *pxCreatedTask ) -{ -signed portBASE_TYPE xReturn; -tskTCB * pxNewTCB; -static unsigned portBASE_TYPE uxTaskNumber = 0; /*lint !e956 Static is deliberate - this is guarded before use. */ - - /* Allocate the memory required by the TCB and stack for the new task. - checking that the allocation was successful. */ - pxNewTCB = prvAllocateTCBAndStack( usStackDepth ); - - if( pxNewTCB != NULL ) - { - portSTACK_TYPE *pxTopOfStack; - - /* Setup the newly allocated TCB with the initial state of the task. */ - prvInitialiseTCBVariables( pxNewTCB, usStackDepth, pcName, uxPriority ); - - /* Calculate the top of stack address. This depends on whether the - stack grows from high memory to low (as per the 80x86) or visa versa. - portSTACK_GROWTH is used to make the result positive or negative as - required by the port. */ - #if portSTACK_GROWTH < 0 - { - pxTopOfStack = pxNewTCB->pxStack + ( pxNewTCB->usStackDepth - 1 ); - } - #else - { - pxTopOfStack = pxNewTCB->pxStack; - } - #endif - - /* Initialize the TCB stack to look as if the task was already running, - but had been interrupted by the scheduler. The return address is set - to the start of the task function. Once the stack has been initialised - the top of stack variable is updated. */ - pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pvTaskCode, pvParameters ); - - /* We are going to manipulate the task queues to add this task to a - ready list, so must make sure no interrupts occur. */ - portENTER_CRITICAL(); - { - uxCurrentNumberOfTasks++; - if( uxCurrentNumberOfTasks == ( unsigned portBASE_TYPE ) 1 ) - { - /* As this is the first task it must also be the current task. */ - pxCurrentTCB = pxNewTCB; - - /* This is the first task to be created so do the preliminary - initialisation required. We will not recover if this call - fails, but we will report the failure. */ - prvInitialiseTaskLists(); - } - else - { - /* If the scheduler is not already running, make this task the - current task if it is the highest priority task to be created - so far. */ - if( xSchedulerRunning == pdFALSE ) - { - if( pxCurrentTCB->uxPriority <= uxPriority ) - { - pxCurrentTCB = pxNewTCB; - } - } - } - - /* Remember the top priority to make context switching faster. Use - the priority in pxNewTCB as this has been capped to a valid value. */ - if( pxNewTCB->uxPriority > uxTopUsedPriority ) - { - uxTopUsedPriority = pxNewTCB->uxPriority; - } - - /* Add a counter into the TCB for tracing only. */ - pxNewTCB->uxTCBNumber = uxTaskNumber; - uxTaskNumber++; - - prvAddTaskToReadyQueue( pxNewTCB ); - - xReturn = pdPASS; - } - portEXIT_CRITICAL(); - } - else - { - xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; - } - - if( xReturn == pdPASS ) - { - if( ( void * ) pxCreatedTask != NULL ) - { - /* Pass the TCB out - in an anonymous way. The calling function/ - task can use this as a handle to delete the task later if - required.*/ - *pxCreatedTask = ( xTaskHandle ) pxNewTCB; - } - - if( xSchedulerRunning != pdFALSE ) - { - /* If the created task is of a higher priority than the current task - then it should run now. */ - if( pxCurrentTCB->uxPriority < uxPriority ) - { - taskYIELD(); - } - } - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskDelete == 1 ) - - void vTaskDelete( xTaskHandle pxTaskToDelete ) - { - tskTCB *pxTCB; - - taskENTER_CRITICAL(); - { - /* Ensure a yield is performed if the current task is being - deleted. */ - if( pxTaskToDelete == pxCurrentTCB ) - { - pxTaskToDelete = NULL; - } - - /* If null is passed in here then we are deleting ourselves. */ - pxTCB = prvGetTCBFromHandle( pxTaskToDelete ); - - /* Remove task from the ready list and place in the termination list. - This will stop the task from be scheduled. The idle task will check - the termination list and free up any memory allocated by the - scheduler for the TCB and stack. */ - vListRemove( &( pxTCB->xGenericListItem ) ); - - /* Is the task waiting on an event also? */ - if( pxTCB->xEventListItem.pvContainer ) - { - vListRemove( &( pxTCB->xEventListItem ) ); - } - - vListInsertEnd( ( xList * ) &xTasksWaitingTermination, &( pxTCB->xGenericListItem ) ); - - /* Increment the ucTasksDeleted variable so the idle task knows - there is a task that has been deleted and that it should therefore - check the xTasksWaitingTermination list. */ - ++uxTasksDeleted; - } - taskEXIT_CRITICAL(); - - /* Force a reschedule if we have just deleted the current task. */ - if( xSchedulerRunning != pdFALSE ) - { - if( ( void * ) pxTaskToDelete == NULL ) - { - taskYIELD(); - } - } - } - -#endif - - - - - - -/*----------------------------------------------------------- - * TASK CONTROL API documented in task.h - *----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskDelayUntil == 1 ) - - void vTaskDelayUntil( portTickType *pxPreviousWakeTime, portTickType xTimeIncrement ) - { - portTickType xTimeToWake; - portBASE_TYPE xAlreadyYielded, xShouldDelay = pdFALSE; - - vTaskSuspendAll(); - { - /* Generate the tick time at which the task wants to wake. */ - xTimeToWake = *pxPreviousWakeTime + xTimeIncrement; - - if( xTickCount < *pxPreviousWakeTime ) - { - /* The tick count has overflowed since this function was - lasted called. In this case the only time we should ever - actually delay is if the wake time has also overflowed, - and the wake time is greater than the tick time. When this - is the case it is as if neither time had overflowed. */ - if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xTickCount ) ) - { - xShouldDelay = pdTRUE; - } - } - else - { - /* The tick time has not overflowed. In this case we will - delay if either the wake time has overflowed, and/or the - tick time is less than the wake time. */ - if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xTickCount ) ) - { - xShouldDelay = pdTRUE; - } - } - - /* Update the wake time ready for the next call. */ - *pxPreviousWakeTime = xTimeToWake; - - if( xShouldDelay ) - { - /* We must remove ourselves from the ready list before adding - ourselves to the blocked list as the same list item is used for - both lists. */ - vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - - /* The list item will be inserted in wake time order. */ - listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake ); - - if( xTimeToWake < xTickCount ) - { - /* Wake time has overflowed. Place this item in the - overflow list. */ - vListInsert( ( xList * ) pxOverflowDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - else - { - /* The wake time has not overflowed, so we can use the - current block list. */ - vListInsert( ( xList * ) pxDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - } - } - xAlreadyYielded = xTaskResumeAll(); - - /* Force a reschedule if xTaskResumeAll has not already done so, we may - have put ourselves to sleep. */ - if( !xAlreadyYielded ) - { - taskYIELD(); - } - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskDelay == 1 ) - - void vTaskDelay( portTickType xTicksToDelay ) - { - portTickType xTimeToWake; - signed portBASE_TYPE xAlreadyYielded = pdFALSE; - - /* A delay time of zero just forces a reschedule. */ - if( xTicksToDelay > ( portTickType ) 0 ) - { - vTaskSuspendAll(); - { - /* A task that is removed from the event list while the - scheduler is suspended will not get placed in the ready - list or removed from the blocked list until the scheduler - is resumed. - - This task cannot be in an event list as it is the currently - executing task. */ - - /* Calculate the time to wake - this may overflow but this is - not a problem. */ - xTimeToWake = xTickCount + xTicksToDelay; - - /* We must remove ourselves from the ready list before adding - ourselves to the blocked list as the same list item is used for - both lists. */ - vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - - /* The list item will be inserted in wake time order. */ - listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake ); - - if( xTimeToWake < xTickCount ) - { - /* Wake time has overflowed. Place this item in the - overflow list. */ - vListInsert( ( xList * ) pxOverflowDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - else - { - /* The wake time has not overflowed, so we can use the - current block list. */ - vListInsert( ( xList * ) pxDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - } - xAlreadyYielded = xTaskResumeAll(); - } - - /* Force a reschedule if xTaskResumeAll has not already done so, we may - have put ourselves to sleep. */ - if( !xAlreadyYielded ) - { - taskYIELD(); - } - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_uxTaskPriorityGet == 1 ) - - unsigned portBASE_TYPE uxTaskPriorityGet( xTaskHandle pxTask ) - { - tskTCB *pxTCB; - unsigned portBASE_TYPE uxReturn; - - taskENTER_CRITICAL(); - { - /* If null is passed in here then we are changing the - priority of the calling function. */ - pxTCB = prvGetTCBFromHandle( pxTask ); - uxReturn = pxTCB->uxPriority; - } - taskEXIT_CRITICAL(); - - return uxReturn; - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskPrioritySet == 1 ) - - void vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority ) - { - tskTCB *pxTCB; - unsigned portBASE_TYPE uxCurrentPriority, xYieldRequired = pdFALSE; - - /* Ensure the new priority is valid. */ - if( uxNewPriority >= configMAX_PRIORITIES ) - { - uxNewPriority = configMAX_PRIORITIES - 1; - } - - taskENTER_CRITICAL(); - { - /* If null is passed in here then we are changing the - priority of the calling function. */ - pxTCB = prvGetTCBFromHandle( pxTask ); - uxCurrentPriority = pxTCB->uxPriority; - - if( uxCurrentPriority != uxNewPriority ) - { - /* The priority change may have readied a task of higher - priority than the calling task. */ - if( uxNewPriority > pxCurrentTCB->uxPriority ) - { - if( pxTask != NULL ) - { - /* The priority of another task is being raised. If we - were raising the priority of the currently running task - there would be no need to switch as it must have already - been the highest priority task. */ - xYieldRequired = pdTRUE; - } - } - else if( pxTask == NULL ) - { - /* Setting our own priority down means there may now be another - task of higher priority that is ready to execute. */ - xYieldRequired = pdTRUE; - } - - pxTCB->uxPriority = uxNewPriority; - listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), configMAX_PRIORITIES - ( portTickType ) uxNewPriority ); - - /* If the task is in the blocked or suspended list we need do - nothing more than change it's priority variable. However, if - the task is in a ready list it needs to be removed and placed - in the queue appropriate to its new priority. */ - if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxCurrentPriority ] ), &( pxTCB->xGenericListItem ) ) ) - { - /* The task is currently in its ready list - remove before adding - it to it's new ready list. As we are in a critical section we - can do this even if the scheduler is suspended. */ - vListRemove( &( pxTCB->xGenericListItem ) ); - prvAddTaskToReadyQueue( pxTCB ); - } - - if( xYieldRequired == pdTRUE ) - { - taskYIELD(); - } - } - } - taskEXIT_CRITICAL(); - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskSuspend == 1 ) - - void vTaskSuspend( xTaskHandle pxTaskToSuspend ) - { - tskTCB *pxTCB; - - taskENTER_CRITICAL(); - { - /* Ensure a yield is performed if the current task is being - suspended. */ - if( pxTaskToSuspend == pxCurrentTCB ) - { - pxTaskToSuspend = NULL; - } - - /* If null is passed in here then we are suspending ourselves. */ - pxTCB = prvGetTCBFromHandle( pxTaskToSuspend ); - - /* Remove task from the ready/delayed list and place in the suspended list. */ - vListRemove( &( pxTCB->xGenericListItem ) ); - - /* Is the task waiting on an event also? */ - if( pxTCB->xEventListItem.pvContainer ) - { - vListRemove( &( pxTCB->xEventListItem ) ); - } - - vListInsertEnd( ( xList * ) &xSuspendedTaskList, &( pxTCB->xGenericListItem ) ); - } - taskEXIT_CRITICAL(); - - /* We may have just suspended the current task. */ - if( ( void * ) pxTaskToSuspend == NULL ) - { - taskYIELD(); - } - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskSuspend == 1 ) - - void vTaskResume( xTaskHandle pxTaskToResume ) - { - tskTCB *pxTCB; - - /* Remove the task from whichever list it is currently in, and place - it in the ready list. */ - pxTCB = ( tskTCB * ) pxTaskToResume; - - /* The parameter cannot be NULL as it is impossible to resume the - currently executing task. */ - if( pxTCB != NULL ) - { - taskENTER_CRITICAL(); - { - /* Is the task we are attempting to resume actually suspended? */ - if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xGenericListItem ) ) != pdFALSE ) - { - /* Has the task already been resumed from within an ISR? */ - if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) != pdTRUE ) - { - /* As we are in a critical section we can access the ready - lists even if the scheduler is suspended. */ - vListRemove( &( pxTCB->xGenericListItem ) ); - prvAddTaskToReadyQueue( pxTCB ); - - /* We may have just resumed a higher priority task. */ - if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) - { - /* This yield may not cause the task just resumed to run, but - will leave the lists in the correct state for the next yield. */ - taskYIELD(); - } - } - } - } - taskEXIT_CRITICAL(); - } - } - -#endif - -/*-----------------------------------------------------------*/ - -#if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) - - portBASE_TYPE xTaskResumeFromISR( xTaskHandle pxTaskToResume ) - { - portBASE_TYPE xYieldRequired = pdFALSE; - tskTCB *pxTCB; - - pxTCB = ( tskTCB * ) pxTaskToResume; - - /* Is the task we are attempting to resume actually suspended? */ - if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xGenericListItem ) ) != pdFALSE ) - { - /* Has the task already been resumed from within an ISR? */ - if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) != pdTRUE ) - { - if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE ) - { - xYieldRequired = ( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ); - vListRemove( &( pxTCB->xGenericListItem ) ); - prvAddTaskToReadyQueue( pxTCB ); - } - else - { - /* We cannot access the delayed or ready lists, so will hold this - task pending until the scheduler is resumed, at which point a - yield will be preformed if necessary. */ - vListInsertEnd( ( xList * ) &( xPendingReadyList ), &( pxTCB->xEventListItem ) ); - } - } - } - - return xYieldRequired; - } - -#endif - - - - -/*----------------------------------------------------------- - * PUBLIC SCHEDULER CONTROL documented in task.h - *----------------------------------------------------------*/ - - -void vTaskStartScheduler( void ) -{ -portBASE_TYPE xReturn; - - /* Add the idle task at the lowest priority. */ - xReturn = xTaskCreate( prvIdleTask, ( signed portCHAR * ) "IDLE", tskIDLE_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL ); - - if( xReturn == pdPASS ) - { - /* Interrupts are turned off here, to ensure a tick does not occur - before or during the call to xPortStartScheduler(). The stacks of - the created tasks contain a status word with interrupts switched on - so interrupts will automatically get re-enabled when the first task - starts to run. - - STEPPING THROUGH HERE USING A DEBUGGER CAN CAUSE BIG PROBLEMS IF THE - DEBUGGER ALLOWS INTERRUPTS TO BE PROCESSED. */ - portDISABLE_INTERRUPTS(); - - xSchedulerRunning = pdTRUE; - xTickCount = ( portTickType ) 0; - - /* Setting up the timer tick is hardware specific and thus in the - portable interface. */ - if( xPortStartScheduler() ) - { - /* Should not reach here as if the scheduler is running the - function will not return. */ - } - else - { - /* Should only reach here if a task calls xTaskEndScheduler(). */ - } - } -} -/*-----------------------------------------------------------*/ - -void vTaskEndScheduler( void ) -{ - /* Stop the scheduler interrupts and call the portable scheduler end - routine so the original ISRs can be restored if necessary. The port - layer must ensure interrupts enable bit is left in the correct state. */ - portDISABLE_INTERRUPTS(); - xSchedulerRunning = pdFALSE; - vPortEndScheduler(); -} -/*----------------------------------------------------------*/ - -void vTaskSuspendAll( void ) -{ - portENTER_CRITICAL(); - ++uxSchedulerSuspended; - portEXIT_CRITICAL(); -} -/*----------------------------------------------------------*/ - -signed portBASE_TYPE xTaskResumeAll( void ) -{ -register tskTCB *pxTCB; -signed portBASE_TYPE xAlreadyYielded = pdFALSE; - - /* It is possible that an ISR caused a task to be removed from an event - list while the scheduler was suspended. If this was the case then the - removed task will have been added to the xPendingReadyList. Once the - scheduler has been resumed it is safe to move all the pending ready - tasks from this list into their appropriate ready list. */ - portENTER_CRITICAL(); - { - --uxSchedulerSuspended; - - if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE ) - { - if( uxCurrentNumberOfTasks > ( unsigned portBASE_TYPE ) 0 ) - { - portBASE_TYPE xYieldRequired = pdFALSE; - - /* Move any readied tasks from the pending list into the - appropriate ready list. */ - while( ( pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( ( ( xList * ) &xPendingReadyList ) ) ) != NULL ) - { - vListRemove( &( pxTCB->xEventListItem ) ); - vListRemove( &( pxTCB->xGenericListItem ) ); - prvAddTaskToReadyQueue( pxTCB ); - - /* If we have moved a task that has a priority higher than - the current task then we should yield. */ - if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) - { - xYieldRequired = pdTRUE; - } - } - - /* If any ticks occurred while the scheduler was suspended then - they should be processed now. This ensures the tick count does not - slip, and that any delayed tasks are resumed at the correct time. */ - if( uxMissedTicks > ( unsigned portBASE_TYPE ) 0 ) - { - while( uxMissedTicks > ( unsigned portBASE_TYPE ) 0 ) - { - vTaskIncrementTick(); - --uxMissedTicks; - } - - /* As we have processed some ticks it is appropriate to yield - to ensure the highest priority task that is ready to run is - the task actually running. */ - xYieldRequired = pdTRUE; - } - - if( ( xYieldRequired == pdTRUE ) || ( xMissedYield == pdTRUE ) ) - { - xAlreadyYielded = pdTRUE; - xMissedYield = pdFALSE; - taskYIELD(); - } - } - } - } - portEXIT_CRITICAL(); - - return xAlreadyYielded; -} - - - - - - -/*----------------------------------------------------------- - * PUBLIC TASK UTILITIES documented in task.h - *----------------------------------------------------------*/ - - - -portTickType xTaskGetTickCount( void ) -{ -portTickType xTicks; - - /* Critical section required if running on a 16 bit processor. */ - taskENTER_CRITICAL(); - { - xTicks = xTickCount; - } - taskEXIT_CRITICAL(); - - return xTicks; -} -/*-----------------------------------------------------------*/ - -unsigned portBASE_TYPE uxTaskGetNumberOfTasks( void ) -{ -unsigned portBASE_TYPE uxNumberOfTasks; - - taskENTER_CRITICAL(); - uxNumberOfTasks = uxCurrentNumberOfTasks; - taskEXIT_CRITICAL(); - - return uxNumberOfTasks; -} -/*-----------------------------------------------------------*/ - -#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_vTaskDelete == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) - - void vTaskList( signed portCHAR *pcWriteBuffer ) - { - unsigned portBASE_TYPE uxQueue; - - /* This is a VERY costly function that should be used for debug only. - It leaves interrupts disabled for a LONG time. */ - - vTaskSuspendAll(); - { - /* Run through all the lists that could potentially contain a TCB and - report the task name, state and stack high water mark. */ - - pcWriteBuffer[ 0 ] = ( signed portCHAR ) 0x00; - strcat( ( portCHAR * ) pcWriteBuffer, ( const portCHAR * ) "\r\n" ); - - uxQueue = uxTopUsedPriority + 1; - - do - { - uxQueue--; - - if( !listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxQueue ] ) ) ) - { - prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) &( pxReadyTasksLists[ uxQueue ] ), tskREADY_CHAR ); - } - }while( uxQueue > ( unsigned portSHORT ) tskIDLE_PRIORITY ); - - if( !listLIST_IS_EMPTY( pxDelayedTaskList ) ) - { - prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) pxDelayedTaskList, tskBLOCKED_CHAR ); - } - - if( !listLIST_IS_EMPTY( pxOverflowDelayedTaskList ) ) - { - prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) pxOverflowDelayedTaskList, tskBLOCKED_CHAR ); - } - - if( !listLIST_IS_EMPTY( &xTasksWaitingTermination ) ) - { - prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) &xTasksWaitingTermination, tskDELETED_CHAR ); - } - - if( !listLIST_IS_EMPTY( &xSuspendedTaskList ) ) - { - prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) &xSuspendedTaskList, tskSUSPENDED_CHAR ); - } - } - xTaskResumeAll(); - } - -#endif -/*----------------------------------------------------------*/ - -#if ( configUSE_TRACE_FACILITY == 1 ) - - void vTaskStartTrace( signed portCHAR * pcBuffer, unsigned portLONG ulBufferSize ) - { - portENTER_CRITICAL(); - { - pcTraceBuffer = ( volatile signed portCHAR * volatile )pcBuffer; - pcTraceBufferStart = pcBuffer; - pcTraceBufferEnd = pcBuffer + ( ulBufferSize - tskSIZE_OF_EACH_TRACE_LINE ); - xTracing = pdTRUE; - } - portEXIT_CRITICAL(); - } - -#endif -/*----------------------------------------------------------*/ - -#if ( configUSE_TRACE_FACILITY == 1 ) - - unsigned portLONG ulTaskEndTrace( void ) - { - unsigned portLONG ulBufferLength; - - portENTER_CRITICAL(); - xTracing = pdFALSE; - portEXIT_CRITICAL(); - - ulBufferLength = ( unsigned portLONG ) ( pcTraceBuffer - pcTraceBufferStart ); - - return ulBufferLength; - } - -#endif - - - -/*----------------------------------------------------------- - * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES - * documented in task.h - *----------------------------------------------------------*/ - - -inline void vTaskIncrementTick( void ) -{ - /* Called by the portable layer each time a tick interrupt occurs. - Increments the tick then checks to see if the new tick value will cause any - tasks to be unblocked. */ - if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE ) - { - ++xTickCount; - if( xTickCount == ( portTickType ) 0 ) - { - xList *pxTemp; - - /* Tick count has overflowed so we need to swap the delay lists. - If there are any items in pxDelayedTaskList here then there is - an error! */ - pxTemp = pxDelayedTaskList; - pxDelayedTaskList = pxOverflowDelayedTaskList; - pxOverflowDelayedTaskList = pxTemp; - xNumOfOverflows++; - } - - /* See if this tick has made a timeout expire. */ - prvCheckDelayedTasks(); - } - else - { - ++uxMissedTicks; - - /* The tick hook gets called at regular intervals, even if the - scheduler is locked. */ - #if ( configUSE_TICK_HOOK == 1 ) - { - extern void vApplicationTickHook( void ); - - vApplicationTickHook(); - } - #endif - } - - #if ( configUSE_TICK_HOOK == 1 ) - { - extern void vApplicationTickHook( void ); - - /* Guard against the tick hook being called when the missed tick - count is being unwound (when the scheduler is being unlocked. */ - if( uxMissedTicks == 0 ) - { - vApplicationTickHook(); - } - } - #endif -} -/*-----------------------------------------------------------*/ - -#if ( ( INCLUDE_vTaskCleanUpResources == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) - - void vTaskCleanUpResources( void ) - { - unsigned portSHORT usQueue; - volatile tskTCB *pxTCB; - - usQueue = ( unsigned portSHORT ) uxTopUsedPriority + ( unsigned portSHORT ) 1; - - /* Remove any TCB's from the ready queues. */ - do - { - usQueue--; - - while( !listLIST_IS_EMPTY( &( pxReadyTasksLists[ usQueue ] ) ) ) - { - listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &( pxReadyTasksLists[ usQueue ] ) ); - vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); - - prvDeleteTCB( ( tskTCB * ) pxTCB ); - } - }while( usQueue > ( unsigned portSHORT ) tskIDLE_PRIORITY ); - - /* Remove any TCB's from the delayed queue. */ - while( !listLIST_IS_EMPTY( &xDelayedTaskList1 ) ) - { - listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &xDelayedTaskList1 ); - vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); - - prvDeleteTCB( ( tskTCB * ) pxTCB ); - } - - /* Remove any TCB's from the overflow delayed queue. */ - while( !listLIST_IS_EMPTY( &xDelayedTaskList2 ) ) - { - listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &xDelayedTaskList2 ); - vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); - - prvDeleteTCB( ( tskTCB * ) pxTCB ); - } - - while( !listLIST_IS_EMPTY( &xSuspendedTaskList ) ) - { - listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &xSuspendedTaskList ); - vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); - - prvDeleteTCB( ( tskTCB * ) pxTCB ); - } - - while( !listLIST_IS_EMPTY( &xPendingReadyList ) ) - { - listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &xPendingReadyList ); - vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); - - prvDeleteTCB( ( tskTCB * ) pxTCB ); - } - } - -#endif -/*-----------------------------------------------------------*/ - -void vTaskSwitchContext( void ) -{ - if( uxSchedulerSuspended != ( unsigned portBASE_TYPE ) pdFALSE ) - { - /* The scheduler is currently suspended - do not allow a context - switch. */ - xMissedYield = pdTRUE; - return; - } - - /* Find the highest priority queue that contains ready tasks. */ - while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopReadyPriority ] ) ) ) - { - --uxTopReadyPriority; - } - - /* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the tasks of the - same priority get an equal share of the processor time. */ - listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopReadyPriority ] ) ); - vWriteTraceToBuffer(); -} -/*-----------------------------------------------------------*/ - -void vTaskPlaceOnEventList( xList *pxEventList, portTickType xTicksToWait ) -{ -portTickType xTimeToWake; - - /* THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED OR THE - SCHEDULER SUSPENDED. */ - - /* Place the event list item of the TCB in the appropriate event list. - This is placed in the list in priority order so the highest priority task - is the first to be woken by the event. */ - vListInsert( ( xList * ) pxEventList, ( xListItem * ) &( pxCurrentTCB->xEventListItem ) ); - - /* We must remove ourselves from the ready list before adding ourselves - to the blocked list as the same list item is used for both lists. We have - exclusive access to the ready lists as the scheduler is locked. */ - vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - - - #if ( INCLUDE_vTaskSuspend == 1 ) - { - if( xTicksToWait == portMAX_DELAY ) - { - /* Add ourselves to the suspended task list instead of a delayed task - list to ensure we are not woken by a timing event. We will block - indefinitely. */ - vListInsertEnd( ( xList * ) &xSuspendedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - else - { - /* Calculate the time at which the task should be woken if the event does - not occur. This may overflow but this doesn't matter. */ - xTimeToWake = xTickCount + xTicksToWait; - - listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake ); - - if( xTimeToWake < xTickCount ) - { - /* Wake time has overflowed. Place this item in the overflow list. */ - vListInsert( ( xList * ) pxOverflowDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - else - { - /* The wake time has not overflowed, so we can use the current block list. */ - vListInsert( ( xList * ) pxDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - } - } - #else - { - /* Calculate the time at which the task should be woken if the event does - not occur. This may overflow but this doesn't matter. */ - xTimeToWake = xTickCount + xTicksToWait; - - listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake ); - - if( xTimeToWake < xTickCount ) - { - /* Wake time has overflowed. Place this item in the overflow list. */ - vListInsert( ( xList * ) pxOverflowDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - else - { - /* The wake time has not overflowed, so we can use the current block list. */ - vListInsert( ( xList * ) pxDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - } - #endif -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xTaskRemoveFromEventList( const xList *pxEventList ) -{ -tskTCB *pxUnblockedTCB; -portBASE_TYPE xReturn; - - /* THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED OR THE - SCHEDULER SUSPENDED. It can also be called from within an ISR. */ - - /* The event list is sorted in priority order, so we can remove the - first in the list, remove the TCB from the delayed list, and add - it to the ready list. - - If an event is for a queue that is locked then this function will never - get called - the lock count on the queue will get modified instead. This - means we can always expect exclusive access to the event list here. */ - pxUnblockedTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); - vListRemove( &( pxUnblockedTCB->xEventListItem ) ); - - if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE ) - { - vListRemove( &( pxUnblockedTCB->xGenericListItem ) ); - prvAddTaskToReadyQueue( pxUnblockedTCB ); - } - else - { - /* We cannot access the delayed or ready lists, so will hold this - task pending until the scheduler is resumed. */ - vListInsertEnd( ( xList * ) &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) ); - } - - if( pxUnblockedTCB->uxPriority >= pxCurrentTCB->uxPriority ) - { - /* Return true if the task removed from the event list has - a higher priority than the calling task. This allows - the calling task to know if it should force a context - switch now. */ - xReturn = pdTRUE; - } - else - { - xReturn = pdFALSE; - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -void vTaskSetTimeOutState( xTimeOutType *pxTimeOut ) -{ - pxTimeOut->xOverflowCount = xNumOfOverflows; - pxTimeOut->xTimeOnEntering = xTickCount; -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xTaskCheckForTimeOut( xTimeOutType *pxTimeOut, portTickType *pxTicksToWait ) -{ -portBASE_TYPE xReturn; - - if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xTickCount >= pxTimeOut->xTimeOnEntering ) ) - { - /* The tick count is greater than the time at which vTaskSetTimeout() - was called, but has also overflowed since vTaskSetTimeOut() was called. - It must have wrapped all the way around and gone past us again. This - passed since vTaskSetTimeout() was called. */ - xReturn = pdTRUE; - } - else if( ( xTickCount - pxTimeOut->xTimeOnEntering ) < *pxTicksToWait ) - { - /* Not a genuine timeout. Adjust parameters for time remaining. */ - *pxTicksToWait -= ( xTickCount - pxTimeOut->xTimeOnEntering ); - vTaskSetTimeOutState( pxTimeOut ); - xReturn = pdFALSE; - } - else - { - xReturn = pdTRUE; - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -void vTaskMissedYield( void ) -{ - xMissedYield = pdTRUE; -} - -/* - * ----------------------------------------------------------- - * The Idle task. - * ---------------------------------------------------------- - * - * The portTASK_FUNCTION() macro is used to allow port/compiler specific - * language extensions. The equivalent prototype for this function is: - * - * void prvIdleTask( void *pvParameters ); - * - */ -static portTASK_FUNCTION( prvIdleTask, pvParameters ) -{ - /* Stop warnings. */ - ( void ) pvParameters; - - for( ;; ) - { - /* See if any tasks have been deleted. */ - prvCheckTasksWaitingTermination(); - - #if ( configUSE_PREEMPTION == 0 ) - { - /* If we are not using preemption we keep forcing a task switch to - see if any other task has become available. If we are using - preemption we don't need to do this as any task becoming available - will automatically get the processor anyway. */ - taskYIELD(); - } - #endif - - #if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) - { - /* When using preemption tasks of equal priority will be - timesliced. If a task that is sharing the idle priority is ready - to run then the idle task should yield before the end of the - timeslice. - - A critical region is not required here as we are just reading from - the list, and an occasional incorrect value will not matter. If - the ready list at the idle priority contains more than one task - then a task other than the idle task is ready to execute. */ - if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( unsigned portBASE_TYPE ) 1 ) - { - taskYIELD(); - } - } - #endif - - #if ( configUSE_IDLE_HOOK == 1 ) - { - extern void vApplicationIdleHook( void ); - - /* Call the user defined function from within the idle task. This - allows the application designer to add background functionality - without the overhead of a separate task. - NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES, - CALL A FUNCTION THAT MIGHT BLOCK. */ - vApplicationIdleHook(); - } - #endif - } -} /*lint !e715 pvParameters is not accessed but all task functions require the same prototype. */ - - - - - - - -/*----------------------------------------------------------- - * File private functions documented at the top of the file. - *----------------------------------------------------------*/ - - - -static void prvInitialiseTCBVariables( tskTCB *pxTCB, unsigned portSHORT usStackDepth, const signed portCHAR * const pcName, unsigned portBASE_TYPE uxPriority ) -{ - pxTCB->usStackDepth = usStackDepth; - - /* Store the function name in the TCB. */ - strncpy( ( char * ) pxTCB->pcTaskName, ( const char * ) pcName, ( unsigned portSHORT ) configMAX_TASK_NAME_LEN ); - pxTCB->pcTaskName[ ( unsigned portSHORT ) configMAX_TASK_NAME_LEN - ( unsigned portSHORT ) 1 ] = '\0'; - - /* This is used as an array index so must ensure it's not too large. */ - if( uxPriority >= configMAX_PRIORITIES ) - { - uxPriority = configMAX_PRIORITIES - 1; - } - - pxTCB->uxPriority = uxPriority; - - vListInitialiseItem( &( pxTCB->xGenericListItem ) ); - vListInitialiseItem( &( pxTCB->xEventListItem ) ); - - /* Set the pxTCB as a link back from the xListItem. This is so we can get - back to the containing TCB from a generic item in a list. */ - listSET_LIST_ITEM_OWNER( &( pxTCB->xGenericListItem ), pxTCB ); - - /* Event lists are always in priority order. */ - listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), configMAX_PRIORITIES - ( portTickType ) uxPriority ); - listSET_LIST_ITEM_OWNER( &( pxTCB->xEventListItem ), pxTCB ); -} -/*-----------------------------------------------------------*/ - -static void prvInitialiseTaskLists( void ) -{ -unsigned portBASE_TYPE uxPriority; - - for( uxPriority = 0; uxPriority < configMAX_PRIORITIES; uxPriority++ ) - { - vListInitialise( ( xList * ) &( pxReadyTasksLists[ uxPriority ] ) ); - } - - vListInitialise( ( xList * ) &xDelayedTaskList1 ); - vListInitialise( ( xList * ) &xDelayedTaskList2 ); - vListInitialise( ( xList * ) &xPendingReadyList ); - - #if ( INCLUDE_vTaskDelete == 1 ) - { - vListInitialise( ( xList * ) &xTasksWaitingTermination ); - } - #endif - - #if ( INCLUDE_vTaskSuspend == 1 ) - { - vListInitialise( ( xList * ) &xSuspendedTaskList ); - } - #endif - - /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList - using list2. */ - pxDelayedTaskList = &xDelayedTaskList1; - pxOverflowDelayedTaskList = &xDelayedTaskList2; -} -/*-----------------------------------------------------------*/ - -static void prvCheckTasksWaitingTermination( void ) -{ - #if ( INCLUDE_vTaskDelete == 1 ) - { - portBASE_TYPE xListIsEmpty; - - /* ucTasksDeleted is used to prevent vTaskSuspendAll() being called - too often in the idle task. */ - if( uxTasksDeleted > ( unsigned portBASE_TYPE ) 0 ) - { - vTaskSuspendAll(); - xListIsEmpty = listLIST_IS_EMPTY( &xTasksWaitingTermination ); - xTaskResumeAll(); - - if( !xListIsEmpty ) - { - tskTCB *pxTCB; - - portENTER_CRITICAL(); - { - pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( ( ( xList * ) &xTasksWaitingTermination ) ); - vListRemove( &( pxTCB->xGenericListItem ) ); - --uxCurrentNumberOfTasks; - --uxTasksDeleted; - } - portEXIT_CRITICAL(); - - prvDeleteTCB( pxTCB ); - } - } - } - #endif -} -/*-----------------------------------------------------------*/ - -static tskTCB *prvAllocateTCBAndStack( unsigned portSHORT usStackDepth ) -{ -tskTCB *pxNewTCB; - - /* Allocate space for the TCB. Where the memory comes from depends on - the implementation of the port malloc function. */ - pxNewTCB = ( tskTCB * ) pvPortMalloc( sizeof( tskTCB ) ); - - if( pxNewTCB != NULL ) - { - /* Allocate space for the stack used by the task being created. - The base of the stack memory stored in the TCB so the task can - be deleted later if required. */ - pxNewTCB->pxStack = ( portSTACK_TYPE * ) pvPortMalloc( ( ( size_t )usStackDepth ) * sizeof( portSTACK_TYPE ) ); - - if( pxNewTCB->pxStack == NULL ) - { - /* Could not allocate the stack. Delete the allocated TCB. */ - vPortFree( pxNewTCB ); - pxNewTCB = NULL; - } - else - { - /* Just to help debugging. */ - memset( pxNewTCB->pxStack, tskSTACK_FILL_BYTE, usStackDepth * sizeof( portSTACK_TYPE ) ); - } - } - - return pxNewTCB; -} -/*-----------------------------------------------------------*/ - -#if ( configUSE_TRACE_FACILITY == 1 ) - - static void prvListTaskWithinSingleList( signed portCHAR *pcWriteBuffer, xList *pxList, signed portCHAR cStatus ) - { - volatile tskTCB *pxNextTCB, *pxFirstTCB; - static portCHAR pcStatusString[ 50 ]; - unsigned portSHORT usStackRemaining; - - /* Write the details of all the TCB's in pxList into the buffer. */ - listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); - do - { - listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); - usStackRemaining = usTaskCheckFreeStackSpace( ( unsigned portCHAR * ) pxNextTCB->pxStack ); - sprintf( pcStatusString, ( portCHAR * ) "%s\t\t%c\t%u\t%u\t%u\r\n", pxNextTCB->pcTaskName, cStatus, ( unsigned int ) pxNextTCB->uxPriority, usStackRemaining, ( unsigned int ) pxNextTCB->uxTCBNumber ); - strcat( ( portCHAR * ) pcWriteBuffer, ( portCHAR * ) pcStatusString ); - - } while( pxNextTCB != pxFirstTCB ); - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( configUSE_TRACE_FACILITY == 1 ) - unsigned portSHORT usTaskCheckFreeStackSpace( const unsigned portCHAR *pucStackByte ) - { - register unsigned portSHORT usCount = 0; - - while( *pucStackByte == tskSTACK_FILL_BYTE ) - { - pucStackByte -= portSTACK_GROWTH; - usCount++; - } - - usCount /= sizeof( portSTACK_TYPE ); - - return usCount; - } -#endif -/*-----------------------------------------------------------*/ - - - -#if ( ( INCLUDE_vTaskDelete == 1 ) || ( INCLUDE_vTaskCleanUpResources == 1 ) ) - - static void prvDeleteTCB( tskTCB *pxTCB ) - { - /* Free up the memory allocated by the scheduler for the task. It is up to - the task to free any memory allocated at the application level. */ - vPortFree( pxTCB->pxStack ); - vPortFree( pxTCB ); - } - -#endif - - -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) - - xTaskHandle xTaskGetCurrentTaskHandle( void ) - { - xTaskHandle xReturn; - - portENTER_CRITICAL(); - { - xReturn = ( xTaskHandle ) pxCurrentTCB; - } - portEXIT_CRITICAL(); - - return xReturn; - } - -#endif - - - - - diff --git a/TraceCon/readme.txt b/TraceCon/readme.txt deleted file mode 100644 index ae78ac933..000000000 --- a/TraceCon/readme.txt +++ /dev/null @@ -1,6 +0,0 @@ -Tracecon.exe is a very simplistic utility for converting the trace data captured by the scheduler into a tab delimited text file. The text file can be opened using a spread sheet program as described on www.FreeRTOS.org. - -Tracecon should be executed from a command prompt. It looks for a file called Trace.bin in the current directory and creates a file called trace.txt. - -Use the big endian version for file captured on big endian targets. - diff --git a/TraceCon/tracecon_big_endian_untested.exe b/TraceCon/tracecon_big_endian_untested.exe deleted file mode 100644 index 3b5d0b079..000000000 Binary files a/TraceCon/tracecon_big_endian_untested.exe and /dev/null differ diff --git a/TraceCon/tracecon_little_endian.exe b/TraceCon/tracecon_little_endian.exe deleted file mode 100644 index 171e0d03b..000000000 Binary files a/TraceCon/tracecon_little_endian.exe and /dev/null differ diff --git a/croutine.c b/croutine.c new file mode 100644 index 000000000..84e1b99bd --- /dev/null +++ b/croutine.c @@ -0,0 +1,405 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include "FreeRTOS.h" +#include "task.h" +#include "croutine.h" + +/* Remove the whole file if co-routines are not being used. */ +#if ( configUSE_CO_ROUTINES != 0 ) + +/* + * Some kernel aware debuggers require data to be viewed to be global, rather + * than file scope. + */ + #ifdef portREMOVE_STATIC_QUALIFIER + #define static + #endif + + +/* Lists for ready and blocked co-routines. --------------------*/ + static List_t pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ]; /**< Prioritised ready co-routines. */ + static List_t xDelayedCoRoutineList1; /**< Delayed co-routines. */ + static List_t xDelayedCoRoutineList2; /**< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */ + static List_t * pxDelayedCoRoutineList = NULL; /**< Points to the delayed co-routine list currently being used. */ + static List_t * pxOverflowDelayedCoRoutineList = NULL; /**< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */ + static List_t xPendingReadyCoRoutineList; /**< Holds co-routines that have been readied by an external event. They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */ + +/* Other file private variables. --------------------------------*/ + CRCB_t * pxCurrentCoRoutine = NULL; + static UBaseType_t uxTopCoRoutineReadyPriority = ( UBaseType_t ) 0U; + static TickType_t xCoRoutineTickCount = ( TickType_t ) 0U; + static TickType_t xLastTickCount = ( TickType_t ) 0U; + static TickType_t xPassedTicks = ( TickType_t ) 0U; + +/* The initial state of the co-routine when it is created. */ + #define corINITIAL_STATE ( 0 ) + +/* + * Place the co-routine represented by pxCRCB into the appropriate ready queue + * for the priority. It is inserted at the end of the list. + * + * This macro accesses the co-routine ready lists and therefore must not be + * used from within an ISR. + */ + #define prvAddCoRoutineToReadyQueue( pxCRCB ) \ + do { \ + if( ( pxCRCB )->uxPriority > uxTopCoRoutineReadyPriority ) \ + { \ + uxTopCoRoutineReadyPriority = ( pxCRCB )->uxPriority; \ + } \ + vListInsertEnd( ( List_t * ) &( pxReadyCoRoutineLists[ ( pxCRCB )->uxPriority ] ), &( ( pxCRCB )->xGenericListItem ) ); \ + } while( 0 ) + +/* + * Utility to ready all the lists used by the scheduler. This is called + * automatically upon the creation of the first co-routine. + */ + static void prvInitialiseCoRoutineLists( void ); + +/* + * Co-routines that are readied by an interrupt cannot be placed directly into + * the ready lists (there is no mutual exclusion). Instead they are placed in + * in the pending ready list in order that they can later be moved to the ready + * list by the co-routine scheduler. + */ + static void prvCheckPendingReadyList( void ); + +/* + * Macro that looks at the list of co-routines that are currently delayed to + * see if any require waking. + * + * Co-routines are stored in the queue in the order of their wake time - + * meaning once one co-routine has been found whose timer has not expired + * we need not look any further down the list. + */ + static void prvCheckDelayedList( void ); + +/*-----------------------------------------------------------*/ + + BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, + UBaseType_t uxPriority, + UBaseType_t uxIndex ) + { + BaseType_t xReturn; + CRCB_t * pxCoRoutine; + + traceENTER_xCoRoutineCreate( pxCoRoutineCode, uxPriority, uxIndex ); + + /* Allocate the memory that will store the co-routine control block. */ + /* MISRA Ref 11.5.1 [Malloc memory assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + pxCoRoutine = ( CRCB_t * ) pvPortMalloc( sizeof( CRCB_t ) ); + + if( pxCoRoutine ) + { + /* If pxCurrentCoRoutine is NULL then this is the first co-routine to + * be created and the co-routine data structures need initialising. */ + if( pxCurrentCoRoutine == NULL ) + { + pxCurrentCoRoutine = pxCoRoutine; + prvInitialiseCoRoutineLists(); + } + + /* Check the priority is within limits. */ + if( uxPriority >= configMAX_CO_ROUTINE_PRIORITIES ) + { + uxPriority = configMAX_CO_ROUTINE_PRIORITIES - 1; + } + + /* Fill out the co-routine control block from the function parameters. */ + pxCoRoutine->uxState = corINITIAL_STATE; + pxCoRoutine->uxPriority = uxPriority; + pxCoRoutine->uxIndex = uxIndex; + pxCoRoutine->pxCoRoutineFunction = pxCoRoutineCode; + + /* Initialise all the other co-routine control block parameters. */ + vListInitialiseItem( &( pxCoRoutine->xGenericListItem ) ); + vListInitialiseItem( &( pxCoRoutine->xEventListItem ) ); + + /* Set the co-routine control block as a link back from the ListItem_t. + * This is so we can get back to the containing CRCB from a generic item + * in a list. */ + listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xGenericListItem ), pxCoRoutine ); + listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xEventListItem ), pxCoRoutine ); + + /* Event lists are always in priority order. */ + listSET_LIST_ITEM_VALUE( &( pxCoRoutine->xEventListItem ), ( ( TickType_t ) configMAX_CO_ROUTINE_PRIORITIES - ( TickType_t ) uxPriority ) ); + + /* Now the co-routine has been initialised it can be added to the ready + * list at the correct priority. */ + prvAddCoRoutineToReadyQueue( pxCoRoutine ); + + xReturn = pdPASS; + } + else + { + xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + } + + traceRETURN_xCoRoutineCreate( xReturn ); + + return xReturn; + } +/*-----------------------------------------------------------*/ + + void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, + List_t * pxEventList ) + { + TickType_t xTimeToWake; + + traceENTER_vCoRoutineAddToDelayedList( xTicksToDelay, pxEventList ); + + /* Calculate the time to wake - this may overflow but this is + * not a problem. */ + xTimeToWake = xCoRoutineTickCount + xTicksToDelay; + + /* We must remove ourselves from the ready list before adding + * ourselves to the blocked list as the same list item is used for + * both lists. */ + ( void ) uxListRemove( ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) ); + + /* The list item will be inserted in wake time order. */ + listSET_LIST_ITEM_VALUE( &( pxCurrentCoRoutine->xGenericListItem ), xTimeToWake ); + + if( xTimeToWake < xCoRoutineTickCount ) + { + /* Wake time has overflowed. Place this item in the + * overflow list. */ + vListInsert( ( List_t * ) pxOverflowDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) ); + } + else + { + /* The wake time has not overflowed, so we can use the + * current block list. */ + vListInsert( ( List_t * ) pxDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) ); + } + + if( pxEventList ) + { + /* Also add the co-routine to an event list. If this is done then the + * function must be called with interrupts disabled. */ + vListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) ); + } + + traceRETURN_vCoRoutineAddToDelayedList(); + } +/*-----------------------------------------------------------*/ + + static void prvCheckPendingReadyList( void ) + { + /* Are there any co-routines waiting to get moved to the ready list? These + * are co-routines that have been readied by an ISR. The ISR cannot access + * the ready lists itself. */ + while( listLIST_IS_EMPTY( &xPendingReadyCoRoutineList ) == pdFALSE ) + { + CRCB_t * pxUnblockedCRCB; + + /* The pending ready list can be accessed by an ISR. */ + portDISABLE_INTERRUPTS(); + { + pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyCoRoutineList ) ); + ( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) ); + } + portENABLE_INTERRUPTS(); + + ( void ) uxListRemove( &( pxUnblockedCRCB->xGenericListItem ) ); + prvAddCoRoutineToReadyQueue( pxUnblockedCRCB ); + } + } +/*-----------------------------------------------------------*/ + + static void prvCheckDelayedList( void ) + { + CRCB_t * pxCRCB; + + xPassedTicks = xTaskGetTickCount() - xLastTickCount; + + while( xPassedTicks ) + { + xCoRoutineTickCount++; + xPassedTicks--; + + /* If the tick count has overflowed we need to swap the ready lists. */ + if( xCoRoutineTickCount == 0 ) + { + List_t * pxTemp; + + /* Tick count has overflowed so we need to swap the delay lists. If there are + * any items in pxDelayedCoRoutineList here then there is an error! */ + pxTemp = pxDelayedCoRoutineList; + pxDelayedCoRoutineList = pxOverflowDelayedCoRoutineList; + pxOverflowDelayedCoRoutineList = pxTemp; + } + + /* See if this tick has made a timeout expire. */ + while( listLIST_IS_EMPTY( pxDelayedCoRoutineList ) == pdFALSE ) + { + pxCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedCoRoutineList ); + + if( xCoRoutineTickCount < listGET_LIST_ITEM_VALUE( &( pxCRCB->xGenericListItem ) ) ) + { + /* Timeout not yet expired. */ + break; + } + + portDISABLE_INTERRUPTS(); + { + /* The event could have occurred just before this critical + * section. If this is the case then the generic list item will + * have been moved to the pending ready list and the following + * line is still valid. Also the pvContainer parameter will have + * been set to NULL so the following lines are also valid. */ + ( void ) uxListRemove( &( pxCRCB->xGenericListItem ) ); + + /* Is the co-routine waiting on an event also? */ + if( pxCRCB->xEventListItem.pxContainer ) + { + ( void ) uxListRemove( &( pxCRCB->xEventListItem ) ); + } + } + portENABLE_INTERRUPTS(); + + prvAddCoRoutineToReadyQueue( pxCRCB ); + } + } + + xLastTickCount = xCoRoutineTickCount; + } +/*-----------------------------------------------------------*/ + + void vCoRoutineSchedule( void ) + { + traceENTER_vCoRoutineSchedule(); + + /* Only run a co-routine after prvInitialiseCoRoutineLists() has been + * called. prvInitialiseCoRoutineLists() is called automatically when a + * co-routine is created. */ + if( pxDelayedCoRoutineList != NULL ) + { + /* See if any co-routines readied by events need moving to the ready lists. */ + prvCheckPendingReadyList(); + + /* See if any delayed co-routines have timed out. */ + prvCheckDelayedList(); + + /* Find the highest priority queue that contains ready co-routines. */ + while( listLIST_IS_EMPTY( &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ) ) + { + if( uxTopCoRoutineReadyPriority == 0 ) + { + /* No more co-routines to check. */ + return; + } + + --uxTopCoRoutineReadyPriority; + } + + /* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the co-routines + * of the same priority get an equal share of the processor time. */ + listGET_OWNER_OF_NEXT_ENTRY( pxCurrentCoRoutine, &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ); + + /* Call the co-routine. */ + ( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex ); + } + + traceRETURN_vCoRoutineSchedule(); + } +/*-----------------------------------------------------------*/ + + static void prvInitialiseCoRoutineLists( void ) + { + UBaseType_t uxPriority; + + for( uxPriority = 0; uxPriority < configMAX_CO_ROUTINE_PRIORITIES; uxPriority++ ) + { + vListInitialise( ( List_t * ) &( pxReadyCoRoutineLists[ uxPriority ] ) ); + } + + vListInitialise( ( List_t * ) &xDelayedCoRoutineList1 ); + vListInitialise( ( List_t * ) &xDelayedCoRoutineList2 ); + vListInitialise( ( List_t * ) &xPendingReadyCoRoutineList ); + + /* Start with pxDelayedCoRoutineList using list1 and the + * pxOverflowDelayedCoRoutineList using list2. */ + pxDelayedCoRoutineList = &xDelayedCoRoutineList1; + pxOverflowDelayedCoRoutineList = &xDelayedCoRoutineList2; + } +/*-----------------------------------------------------------*/ + + BaseType_t xCoRoutineRemoveFromEventList( const List_t * pxEventList ) + { + CRCB_t * pxUnblockedCRCB; + BaseType_t xReturn; + + traceENTER_xCoRoutineRemoveFromEventList( pxEventList ); + + /* This function is called from within an interrupt. It can only access + * event lists and the pending ready list. This function assumes that a + * check has already been made to ensure pxEventList is not empty. */ + pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); + ( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) ); + vListInsertEnd( ( List_t * ) &( xPendingReadyCoRoutineList ), &( pxUnblockedCRCB->xEventListItem ) ); + + if( pxUnblockedCRCB->uxPriority >= pxCurrentCoRoutine->uxPriority ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + traceRETURN_xCoRoutineRemoveFromEventList( xReturn ); + + return xReturn; + } +/*-----------------------------------------------------------*/ + +/* + * Reset state in this file. This state is normally initialized at start up. + * This function must be called by the application before restarting the + * scheduler. + */ + void vCoRoutineResetState( void ) + { + /* Lists for ready and blocked co-routines. */ + pxDelayedCoRoutineList = NULL; + pxOverflowDelayedCoRoutineList = NULL; + + /* Other file private variables. */ + pxCurrentCoRoutine = NULL; + uxTopCoRoutineReadyPriority = ( UBaseType_t ) 0U; + xCoRoutineTickCount = ( TickType_t ) 0U; + xLastTickCount = ( TickType_t ) 0U; + xPassedTicks = ( TickType_t ) 0U; + } +/*-----------------------------------------------------------*/ + +#endif /* configUSE_CO_ROUTINES == 0 */ diff --git a/cspell.config.yaml b/cspell.config.yaml new file mode 100644 index 000000000..911ce1d8f --- /dev/null +++ b/cspell.config.yaml @@ -0,0 +1,31 @@ +--- +$schema: https://raw.githubusercontent.com/streetsidesoftware/cspell/main/cspell.schema.json +version: '0.2' +# Allows things like stringLength +allowCompoundWords: true + +# Read files not to spell check from the git ignore +useGitignore: true + +# Language settings for C +languageSettings: + - caseSensitive: false + enabled: true + languageId: c + locale: "*" + +# Add a dictionary, and the path to the word list +dictionaryDefinitions: + - name: freertos-words + path: '.github/.cSpellWords.txt' + addWords: true + +dictionaries: + - freertos-words + +# Paths and files to ignore +ignorePaths: + - 'dependency' + - 'docs' + - 'ThirdParty' + - 'History.txt' diff --git a/event_groups.c b/event_groups.c new file mode 100644 index 000000000..7c5c15db7 --- /dev/null +++ b/event_groups.c @@ -0,0 +1,887 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "event_groups.h" + +/* The MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined + * for the header files above, but not in this file, in order to generate the + * correct privileged Vs unprivileged linkage and placement. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* This entire source file will be skipped if the application is not configured + * to include event groups functionality. This #if is closed at the very bottom + * of this file. If you want to include event groups then ensure + * configUSE_EVENT_GROUPS is set to 1 in FreeRTOSConfig.h. */ +#if ( configUSE_EVENT_GROUPS == 1 ) + + typedef struct EventGroupDef_t + { + EventBits_t uxEventBits; + List_t xTasksWaitingForBits; /**< List of tasks waiting for a bit to be set. */ + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxEventGroupNumber; + #endif + + #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucStaticallyAllocated; /**< Set to pdTRUE if the event group is statically allocated to ensure no attempt is made to free the memory. */ + #endif + } EventGroup_t; + +/*-----------------------------------------------------------*/ + +/* + * Test the bits set in uxCurrentEventBits to see if the wait condition is met. + * The wait condition is defined by xWaitForAllBits. If xWaitForAllBits is + * pdTRUE then the wait condition is met if all the bits set in uxBitsToWaitFor + * are also set in uxCurrentEventBits. If xWaitForAllBits is pdFALSE then the + * wait condition is met if any of the bits set in uxBitsToWaitFor are also set + * in uxCurrentEventBits. + */ + static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, + const EventBits_t uxBitsToWaitFor, + const BaseType_t xWaitForAllBits ) PRIVILEGED_FUNCTION; + +/*-----------------------------------------------------------*/ + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + + EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) + { + EventGroup_t * pxEventBits; + + traceENTER_xEventGroupCreateStatic( pxEventGroupBuffer ); + + /* A StaticEventGroup_t object must be provided. */ + configASSERT( pxEventGroupBuffer ); + + #if ( configASSERT_DEFINED == 1 ) + { + /* Sanity check that the size of the structure used to declare a + * variable of type StaticEventGroup_t equals the size of the real + * event group structure. */ + volatile size_t xSize = sizeof( StaticEventGroup_t ); + configASSERT( xSize == sizeof( EventGroup_t ) ); + } + #endif /* configASSERT_DEFINED */ + + /* The user has provided a statically allocated event group - use it. */ + /* MISRA Ref 11.3.1 [Misaligned access] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */ + /* coverity[misra_c_2012_rule_11_3_violation] */ + pxEventBits = ( EventGroup_t * ) pxEventGroupBuffer; + + if( pxEventBits != NULL ) + { + pxEventBits->uxEventBits = 0; + vListInitialise( &( pxEventBits->xTasksWaitingForBits ) ); + + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + { + /* Both static and dynamic allocation can be used, so note that + * this event group was created statically in case the event group + * is later deleted. */ + pxEventBits->ucStaticallyAllocated = pdTRUE; + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + + traceEVENT_GROUP_CREATE( pxEventBits ); + } + else + { + /* xEventGroupCreateStatic should only ever be called with + * pxEventGroupBuffer pointing to a pre-allocated (compile time + * allocated) StaticEventGroup_t variable. */ + traceEVENT_GROUP_CREATE_FAILED(); + } + + traceRETURN_xEventGroupCreateStatic( pxEventBits ); + + return pxEventBits; + } + + #endif /* configSUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + EventGroupHandle_t xEventGroupCreate( void ) + { + EventGroup_t * pxEventBits; + + traceENTER_xEventGroupCreate(); + + /* MISRA Ref 11.5.1 [Malloc memory assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) ); + + if( pxEventBits != NULL ) + { + pxEventBits->uxEventBits = 0; + vListInitialise( &( pxEventBits->xTasksWaitingForBits ) ); + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + /* Both static and dynamic allocation can be used, so note this + * event group was allocated statically in case the event group is + * later deleted. */ + pxEventBits->ucStaticallyAllocated = pdFALSE; + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ + + traceEVENT_GROUP_CREATE( pxEventBits ); + } + else + { + traceEVENT_GROUP_CREATE_FAILED(); + } + + traceRETURN_xEventGroupCreate( pxEventBits ); + + return pxEventBits; + } + + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + + EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) + { + EventBits_t uxOriginalBitValue, uxReturn; + EventGroup_t * pxEventBits = xEventGroup; + BaseType_t xAlreadyYielded; + BaseType_t xTimeoutOccurred = pdFALSE; + + traceENTER_xEventGroupSync( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTicksToWait ); + + configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + configASSERT( uxBitsToWaitFor != 0 ); + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + } + #endif + + vTaskSuspendAll(); + { + uxOriginalBitValue = pxEventBits->uxEventBits; + + ( void ) xEventGroupSetBits( xEventGroup, uxBitsToSet ); + + if( ( ( uxOriginalBitValue | uxBitsToSet ) & uxBitsToWaitFor ) == uxBitsToWaitFor ) + { + /* All the rendezvous bits are now set - no need to block. */ + uxReturn = ( uxOriginalBitValue | uxBitsToSet ); + + /* Rendezvous always clear the bits. They will have been cleared + * already unless this is the only task in the rendezvous. */ + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + + xTicksToWait = 0; + } + else + { + if( xTicksToWait != ( TickType_t ) 0 ) + { + traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor ); + + /* Store the bits that the calling task is waiting for in the + * task's event list item so the kernel knows when a match is + * found. Then enter the blocked state. */ + vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | eventCLEAR_EVENTS_ON_EXIT_BIT | eventWAIT_FOR_ALL_BITS ), xTicksToWait ); + + /* This assignment is obsolete as uxReturn will get set after + * the task unblocks, but some compilers mistakenly generate a + * warning about uxReturn being returned without being set if the + * assignment is omitted. */ + uxReturn = 0; + } + else + { + /* The rendezvous bits were not set, but no block time was + * specified - just return the current event bit value. */ + uxReturn = pxEventBits->uxEventBits; + xTimeoutOccurred = pdTRUE; + } + } + } + xAlreadyYielded = xTaskResumeAll(); + + if( xTicksToWait != ( TickType_t ) 0 ) + { + if( xAlreadyYielded == pdFALSE ) + { + taskYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* The task blocked to wait for its required bits to be set - at this + * point either the required bits were set or the block time expired. If + * the required bits were set they will have been stored in the task's + * event list item, and they should now be retrieved then cleared. */ + uxReturn = uxTaskResetEventItemValue(); + + if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 ) + { + /* The task timed out, just return the current event bit value. */ + taskENTER_CRITICAL(); + { + uxReturn = pxEventBits->uxEventBits; + + /* Although the task got here because it timed out before the + * bits it was waiting for were set, it is possible that since it + * unblocked another task has set the bits. If this is the case + * then it needs to clear the bits before exiting. */ + if( ( uxReturn & uxBitsToWaitFor ) == uxBitsToWaitFor ) + { + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + + xTimeoutOccurred = pdTRUE; + } + else + { + /* The task unblocked because the bits were set. */ + } + + /* Control bits might be set as the task had blocked should not be + * returned. */ + uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES; + } + + traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xTimeoutOccurred; + + traceRETURN_xEventGroupSync( uxReturn ); + + return uxReturn; + } +/*-----------------------------------------------------------*/ + + EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToWaitFor, + const BaseType_t xClearOnExit, + const BaseType_t xWaitForAllBits, + TickType_t xTicksToWait ) + { + EventGroup_t * pxEventBits = xEventGroup; + EventBits_t uxReturn, uxControlBits = 0; + BaseType_t xWaitConditionMet, xAlreadyYielded; + BaseType_t xTimeoutOccurred = pdFALSE; + + traceENTER_xEventGroupWaitBits( xEventGroup, uxBitsToWaitFor, xClearOnExit, xWaitForAllBits, xTicksToWait ); + + /* Check the user is not attempting to wait on the bits used by the kernel + * itself, and that at least one bit is being requested. */ + configASSERT( xEventGroup ); + configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + configASSERT( uxBitsToWaitFor != 0 ); + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + } + #endif + + vTaskSuspendAll(); + { + const EventBits_t uxCurrentEventBits = pxEventBits->uxEventBits; + + /* Check to see if the wait condition is already met or not. */ + xWaitConditionMet = prvTestWaitCondition( uxCurrentEventBits, uxBitsToWaitFor, xWaitForAllBits ); + + if( xWaitConditionMet != pdFALSE ) + { + /* The wait condition has already been met so there is no need to + * block. */ + uxReturn = uxCurrentEventBits; + xTicksToWait = ( TickType_t ) 0; + + /* Clear the wait bits if requested to do so. */ + if( xClearOnExit != pdFALSE ) + { + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else if( xTicksToWait == ( TickType_t ) 0 ) + { + /* The wait condition has not been met, but no block time was + * specified, so just return the current value. */ + uxReturn = uxCurrentEventBits; + xTimeoutOccurred = pdTRUE; + } + else + { + /* The task is going to block to wait for its required bits to be + * set. uxControlBits are used to remember the specified behaviour of + * this call to xEventGroupWaitBits() - for use when the event bits + * unblock the task. */ + if( xClearOnExit != pdFALSE ) + { + uxControlBits |= eventCLEAR_EVENTS_ON_EXIT_BIT; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xWaitForAllBits != pdFALSE ) + { + uxControlBits |= eventWAIT_FOR_ALL_BITS; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Store the bits that the calling task is waiting for in the + * task's event list item so the kernel knows when a match is + * found. Then enter the blocked state. */ + vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | uxControlBits ), xTicksToWait ); + + /* This is obsolete as it will get set after the task unblocks, but + * some compilers mistakenly generate a warning about the variable + * being returned without being set if it is not done. */ + uxReturn = 0; + + traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor ); + } + } + xAlreadyYielded = xTaskResumeAll(); + + if( xTicksToWait != ( TickType_t ) 0 ) + { + if( xAlreadyYielded == pdFALSE ) + { + taskYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* The task blocked to wait for its required bits to be set - at this + * point either the required bits were set or the block time expired. If + * the required bits were set they will have been stored in the task's + * event list item, and they should now be retrieved then cleared. */ + uxReturn = uxTaskResetEventItemValue(); + + if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 ) + { + taskENTER_CRITICAL(); + { + /* The task timed out, just return the current event bit value. */ + uxReturn = pxEventBits->uxEventBits; + + /* It is possible that the event bits were updated between this + * task leaving the Blocked state and running again. */ + if( prvTestWaitCondition( uxReturn, uxBitsToWaitFor, xWaitForAllBits ) != pdFALSE ) + { + if( xClearOnExit != pdFALSE ) + { + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xTimeoutOccurred = pdTRUE; + } + taskEXIT_CRITICAL(); + } + else + { + /* The task unblocked because the bits were set. */ + } + + /* The task blocked so control bits may have been set. */ + uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES; + } + + traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xTimeoutOccurred; + + traceRETURN_xEventGroupWaitBits( uxReturn ); + + return uxReturn; + } +/*-----------------------------------------------------------*/ + + EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) + { + EventGroup_t * pxEventBits = xEventGroup; + EventBits_t uxReturn; + + traceENTER_xEventGroupClearBits( xEventGroup, uxBitsToClear ); + + /* Check the user is not attempting to clear the bits used by the kernel + * itself. */ + configASSERT( xEventGroup ); + configASSERT( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + + taskENTER_CRITICAL(); + { + traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear ); + + /* The value returned is the event group value prior to the bits being + * cleared. */ + uxReturn = pxEventBits->uxEventBits; + + /* Clear the bits. */ + pxEventBits->uxEventBits &= ~uxBitsToClear; + } + taskEXIT_CRITICAL(); + + traceRETURN_xEventGroupClearBits( uxReturn ); + + return uxReturn; + } +/*-----------------------------------------------------------*/ + + #if ( ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) + + BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) + { + BaseType_t xReturn; + + traceENTER_xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear ); + + traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear ); + xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ); + + traceRETURN_xEventGroupClearBitsFromISR( xReturn ); + + return xReturn; + } + + #endif /* if ( ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */ +/*-----------------------------------------------------------*/ + + EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) + { + UBaseType_t uxSavedInterruptStatus; + EventGroup_t const * const pxEventBits = xEventGroup; + EventBits_t uxReturn; + + traceENTER_xEventGroupGetBitsFromISR( xEventGroup ); + + /* MISRA Ref 4.7.1 [Return value shall be checked] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */ + /* coverity[misra_c_2012_directive_4_7_violation] */ + uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR(); + { + uxReturn = pxEventBits->uxEventBits; + } + taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + + traceRETURN_xEventGroupGetBitsFromISR( uxReturn ); + + return uxReturn; + } +/*-----------------------------------------------------------*/ + + EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) + { + ListItem_t * pxListItem; + ListItem_t * pxNext; + ListItem_t const * pxListEnd; + List_t const * pxList; + EventBits_t uxBitsToClear = 0, uxBitsWaitedFor, uxControlBits, uxReturnBits; + EventGroup_t * pxEventBits = xEventGroup; + BaseType_t xMatchFound = pdFALSE; + + traceENTER_xEventGroupSetBits( xEventGroup, uxBitsToSet ); + + /* Check the user is not attempting to set the bits used by the kernel + * itself. */ + configASSERT( xEventGroup ); + configASSERT( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + + pxList = &( pxEventBits->xTasksWaitingForBits ); + pxListEnd = listGET_END_MARKER( pxList ); + vTaskSuspendAll(); + { + traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet ); + + pxListItem = listGET_HEAD_ENTRY( pxList ); + + /* Set the bits. */ + pxEventBits->uxEventBits |= uxBitsToSet; + + /* See if the new bit value should unblock any tasks. */ + while( pxListItem != pxListEnd ) + { + pxNext = listGET_NEXT( pxListItem ); + uxBitsWaitedFor = listGET_LIST_ITEM_VALUE( pxListItem ); + xMatchFound = pdFALSE; + + /* Split the bits waited for from the control bits. */ + uxControlBits = uxBitsWaitedFor & eventEVENT_BITS_CONTROL_BYTES; + uxBitsWaitedFor &= ~eventEVENT_BITS_CONTROL_BYTES; + + if( ( uxControlBits & eventWAIT_FOR_ALL_BITS ) == ( EventBits_t ) 0 ) + { + /* Just looking for single bit being set. */ + if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) != ( EventBits_t ) 0 ) + { + xMatchFound = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) == uxBitsWaitedFor ) + { + /* All bits are set. */ + xMatchFound = pdTRUE; + } + else + { + /* Need all bits to be set, but not all the bits were set. */ + } + + if( xMatchFound != pdFALSE ) + { + /* The bits match. Should the bits be cleared on exit? */ + if( ( uxControlBits & eventCLEAR_EVENTS_ON_EXIT_BIT ) != ( EventBits_t ) 0 ) + { + uxBitsToClear |= uxBitsWaitedFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Store the actual event flag value in the task's event list + * item before removing the task from the event list. The + * eventUNBLOCKED_DUE_TO_BIT_SET bit is set so the task knows + * that is was unblocked due to its required bits matching, rather + * than because it timed out. */ + vTaskRemoveFromUnorderedEventList( pxListItem, pxEventBits->uxEventBits | eventUNBLOCKED_DUE_TO_BIT_SET ); + } + + /* Move onto the next list item. Note pxListItem->pxNext is not + * used here as the list item may have been removed from the event list + * and inserted into the ready/pending reading list. */ + pxListItem = pxNext; + } + + /* Clear any bits that matched when the eventCLEAR_EVENTS_ON_EXIT_BIT + * bit was set in the control word. */ + pxEventBits->uxEventBits &= ~uxBitsToClear; + + /* Snapshot resulting bits. */ + uxReturnBits = pxEventBits->uxEventBits; + } + ( void ) xTaskResumeAll(); + + traceRETURN_xEventGroupSetBits( uxReturnBits ); + + return uxReturnBits; + } +/*-----------------------------------------------------------*/ + + void vEventGroupDelete( EventGroupHandle_t xEventGroup ) + { + EventGroup_t * pxEventBits = xEventGroup; + const List_t * pxTasksWaitingForBits; + + traceENTER_vEventGroupDelete( xEventGroup ); + + configASSERT( pxEventBits ); + + pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits ); + + vTaskSuspendAll(); + { + traceEVENT_GROUP_DELETE( xEventGroup ); + + while( listCURRENT_LIST_LENGTH( pxTasksWaitingForBits ) > ( UBaseType_t ) 0 ) + { + /* Unblock the task, returning 0 as the event list is being deleted + * and cannot therefore have any bits set. */ + configASSERT( pxTasksWaitingForBits->xListEnd.pxNext != ( const ListItem_t * ) &( pxTasksWaitingForBits->xListEnd ) ); + vTaskRemoveFromUnorderedEventList( pxTasksWaitingForBits->xListEnd.pxNext, eventUNBLOCKED_DUE_TO_BIT_SET ); + } + } + ( void ) xTaskResumeAll(); + + #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) ) + { + /* The event group can only have been allocated dynamically - free + * it again. */ + vPortFree( pxEventBits ); + } + #elif ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + { + /* The event group could have been allocated statically or + * dynamically, so check before attempting to free the memory. */ + if( pxEventBits->ucStaticallyAllocated == ( uint8_t ) pdFALSE ) + { + vPortFree( pxEventBits ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + + traceRETURN_vEventGroupDelete(); + } +/*-----------------------------------------------------------*/ + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + BaseType_t xEventGroupGetStaticBuffer( EventGroupHandle_t xEventGroup, + StaticEventGroup_t ** ppxEventGroupBuffer ) + { + BaseType_t xReturn; + EventGroup_t * pxEventBits = xEventGroup; + + traceENTER_xEventGroupGetStaticBuffer( xEventGroup, ppxEventGroupBuffer ); + + configASSERT( pxEventBits ); + configASSERT( ppxEventGroupBuffer ); + + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + { + /* Check if the event group was statically allocated. */ + if( pxEventBits->ucStaticallyAllocated == ( uint8_t ) pdTRUE ) + { + /* MISRA Ref 11.3.1 [Misaligned access] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */ + /* coverity[misra_c_2012_rule_11_3_violation] */ + *ppxEventGroupBuffer = ( StaticEventGroup_t * ) pxEventBits; + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + } + #else /* configSUPPORT_DYNAMIC_ALLOCATION */ + { + /* Event group must have been statically allocated. */ + /* MISRA Ref 11.3.1 [Misaligned access] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */ + /* coverity[misra_c_2012_rule_11_3_violation] */ + *ppxEventGroupBuffer = ( StaticEventGroup_t * ) pxEventBits; + xReturn = pdTRUE; + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + + traceRETURN_xEventGroupGetStaticBuffer( xReturn ); + + return xReturn; + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +/* For internal use only - execute a 'set bits' command that was pended from + * an interrupt. */ + void vEventGroupSetBitsCallback( void * pvEventGroup, + uint32_t ulBitsToSet ) + { + traceENTER_vEventGroupSetBitsCallback( pvEventGroup, ulBitsToSet ); + + /* MISRA Ref 11.5.4 [Callback function parameter] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + ( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet ); + + traceRETURN_vEventGroupSetBitsCallback(); + } +/*-----------------------------------------------------------*/ + +/* For internal use only - execute a 'clear bits' command that was pended from + * an interrupt. */ + void vEventGroupClearBitsCallback( void * pvEventGroup, + uint32_t ulBitsToClear ) + { + traceENTER_vEventGroupClearBitsCallback( pvEventGroup, ulBitsToClear ); + + /* MISRA Ref 11.5.4 [Callback function parameter] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + ( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear ); + + traceRETURN_vEventGroupClearBitsCallback(); + } +/*-----------------------------------------------------------*/ + + static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, + const EventBits_t uxBitsToWaitFor, + const BaseType_t xWaitForAllBits ) + { + BaseType_t xWaitConditionMet = pdFALSE; + + if( xWaitForAllBits == pdFALSE ) + { + /* Task only has to wait for one bit within uxBitsToWaitFor to be + * set. Is one already set? */ + if( ( uxCurrentEventBits & uxBitsToWaitFor ) != ( EventBits_t ) 0 ) + { + xWaitConditionMet = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* Task has to wait for all the bits in uxBitsToWaitFor to be set. + * Are they set already? */ + if( ( uxCurrentEventBits & uxBitsToWaitFor ) == uxBitsToWaitFor ) + { + xWaitConditionMet = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + return xWaitConditionMet; + } +/*-----------------------------------------------------------*/ + + #if ( ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) + + BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + BaseType_t * pxHigherPriorityTaskWoken ) + { + BaseType_t xReturn; + + traceENTER_xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken ); + + traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet ); + xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ); + + traceRETURN_xEventGroupSetBitsFromISR( xReturn ); + + return xReturn; + } + + #endif /* if ( ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t uxEventGroupGetNumber( void * xEventGroup ) + { + UBaseType_t xReturn; + + /* MISRA Ref 11.5.2 [Opaque pointer] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + EventGroup_t const * pxEventBits = ( EventGroup_t * ) xEventGroup; + + traceENTER_uxEventGroupGetNumber( xEventGroup ); + + if( xEventGroup == NULL ) + { + xReturn = 0; + } + else + { + xReturn = pxEventBits->uxEventGroupNumber; + } + + traceRETURN_uxEventGroupGetNumber( xReturn ); + + return xReturn; + } + + #endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + void vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) + { + traceENTER_vEventGroupSetNumber( xEventGroup, uxEventGroupNumber ); + + /* MISRA Ref 11.5.2 [Opaque pointer] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + ( ( EventGroup_t * ) xEventGroup )->uxEventGroupNumber = uxEventGroupNumber; + + traceRETURN_vEventGroupSetNumber(); + } + + #endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +/* This entire source file will be skipped if the application is not configured + * to include event groups functionality. If you want to include event groups + * then ensure configUSE_EVENT_GROUPS is set to 1 in FreeRTOSConfig.h. */ +#endif /* configUSE_EVENT_GROUPS == 1 */ diff --git a/examples/README.md b/examples/README.md new file mode 100644 index 000000000..3b36b607e --- /dev/null +++ b/examples/README.md @@ -0,0 +1,17 @@ +# README for FreeRTOS-Kernel/examples + +The easiest way to use FreeRTOS is to start with one of the pre-configured demo application projects. +See [FreeRTOS/FreeRTOS/Demo](https://github.com/FreeRTOS/FreeRTOS/tree/main/FreeRTOS/Demo) to find a list of pre-configured demos on multiple platforms which demonstrate the working of the FreeRTOS-Kernel. +This directory aims to further facilitate the beginners in building their first FreeRTOS project. + + +## Directory Structure: + +* The [cmake_example](./cmake_example) directory contains a minimal FreeRTOS example project, which uses the configuration file in the template_configuration directory listed below. This will provide you with a starting point for building your applications using FreeRTOS-Kernel. +* The [coverity](./coverity) directory contains a project to run [Synopsys Coverity](https://www.synopsys.com/software-integrity/static-analysis-tools-sast/coverity.html) for checking MISRA compliance. This directory contains further readme files and links to documentation. +* The [template_configuration](./template_configuration) directory contains a sample configuration file FreeRTOSConfig.h which helps you in preparing your application configuration + + +## Additional examples + +Additional examples of the kernel being used in real life applications in tandem with many other libraries (i.e. FreeRTOS+TCP, coreMQTT, coreHTTP etc.) can be found [here](https://github.com/FreeRTOS/FreeRTOS/tree/main/FreeRTOS-Plus/Demo). diff --git a/examples/cmake_example/CMakeLists.txt b/examples/cmake_example/CMakeLists.txt new file mode 100644 index 000000000..7b31cc52a --- /dev/null +++ b/examples/cmake_example/CMakeLists.txt @@ -0,0 +1,74 @@ +cmake_minimum_required(VERSION 3.15) +project(example) + +set(FREERTOS_KERNEL_PATH "../../") + +# Add the freertos_config for FreeRTOS-Kernel +add_library(freertos_config INTERFACE) + +target_include_directories(freertos_config + INTERFACE + "../template_configuration" +) + +if (DEFINED FREERTOS_SMP_EXAMPLE AND FREERTOS_SMP_EXAMPLE STREQUAL "1") + message(STATUS "Build FreeRTOS SMP example") + # Adding the following configurations to build SMP template port + add_compile_options( -DconfigNUMBER_OF_CORES=2 -DconfigUSE_PASSIVE_IDLE_HOOK=0 ) +endif() + +# Select the heap port. values between 1-4 will pick a heap. +set(FREERTOS_HEAP "4" CACHE STRING "" FORCE) + +# Select the native compile PORT +set(FREERTOS_PORT "TEMPLATE" CACHE STRING "" FORCE) + +# Adding the FreeRTOS-Kernel subdirectory +add_subdirectory(${FREERTOS_KERNEL_PATH} FreeRTOS-Kernel) + +######################################################################## +# Overall Compile Options +# Note the compile option strategy is to error on everything and then +# Per library opt-out of things that are warnings/errors. +# This ensures that no matter what strategy for compilation you take, the +# builds will still occur. +# +# Only tested with GNU and Clang. +# Other options are https://cmake.org/cmake/help/latest/variable/CMAKE_LANG_COMPILER_ID.html#variable:CMAKE_%3CLANG%3E_COMPILER_ID +# Naming of compilers translation map: +# +# FreeRTOS | CMake +# ------------------- +# CCS | ?TBD? +# GCC | GNU, Clang, *Clang Others? +# IAR | IAR +# Keil | ARMCC +# MSVC | MSVC # Note only for MinGW? +# Renesas | ?TBD? + +target_compile_options(freertos_kernel PRIVATE + ### Gnu/Clang C Options + $<$:-fdiagnostics-color=always> + $<$:-fcolor-diagnostics> + + $<$:-Wall> + $<$:-Wextra> + $<$:-Wpedantic> + $<$:-Werror> + $<$:-Wconversion> + $<$:-Weverything> + + # Suppressions required to build clean with clang. + $<$:-Wno-unused-macros> + $<$:-Wno-padded> + $<$:-Wno-missing-variable-declarations> + $<$:-Wno-covered-switch-default> + $<$:-Wno-cast-align> ) + +add_executable(${PROJECT_NAME} + main.c +) + +target_link_libraries(${PROJECT_NAME} freertos_kernel freertos_config) + +set_property(TARGET freertos_kernel PROPERTY C_STANDARD 90) \ No newline at end of file diff --git a/examples/cmake_example/main.c b/examples/cmake_example/main.c new file mode 100644 index 000000000..96a2abfe1 --- /dev/null +++ b/examples/cmake_example/main.c @@ -0,0 +1,104 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * This is a simple main that will start the FreeRTOS-Kernel and run a periodic task + * that only delays if compiled with the template port, this project will do nothing. + * For more information on getting started please look here: + * https://www.freertos.org/Documentation/01-FreeRTOS-quick-start/01-Beginners-guide/02-Quick-start-guide + */ + +/* FreeRTOS includes. */ +#include +#include +#include +#include +#include + +/* Standard includes. */ +#include + +/*-----------------------------------------------------------*/ + +static void exampleTask( void * parameters ) __attribute__( ( noreturn ) ); + +/*-----------------------------------------------------------*/ + +static void exampleTask( void * parameters ) +{ + /* Unused parameters. */ + ( void ) parameters; + + for( ; ; ) + { + /* Example Task Code */ + vTaskDelay( 100 ); /* delay 100 ticks */ + } +} +/*-----------------------------------------------------------*/ + +int main( void ) +{ + static StaticTask_t exampleTaskTCB; + static StackType_t exampleTaskStack[ configMINIMAL_STACK_SIZE ]; + + ( void ) printf( "Example FreeRTOS Project\n" ); + + ( void ) xTaskCreateStatic( exampleTask, + "example", + configMINIMAL_STACK_SIZE, + NULL, + configMAX_PRIORITIES - 1U, + &( exampleTaskStack[ 0 ] ), + &( exampleTaskTCB ) ); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + for( ; ; ) + { + /* Should not reach here. */ + } + + return 0; +} +/*-----------------------------------------------------------*/ + +#if ( configCHECK_FOR_STACK_OVERFLOW > 0 ) + + void vApplicationStackOverflowHook( TaskHandle_t xTask, + char * pcTaskName ) + { + /* Check pcTaskName for the name of the offending task, + * or pxCurrentTCB if pcTaskName has itself been corrupted. */ + ( void ) xTask; + ( void ) pcTaskName; + } + +#endif /* #if ( configCHECK_FOR_STACK_OVERFLOW > 0 ) */ +/*-----------------------------------------------------------*/ diff --git a/examples/coverity/CMakeLists.txt b/examples/coverity/CMakeLists.txt new file mode 100644 index 000000000..3c0f4e452 --- /dev/null +++ b/examples/coverity/CMakeLists.txt @@ -0,0 +1,46 @@ +cmake_minimum_required(VERSION 3.15) + +project(coverity) + +set(FREERTOS_KERNEL_PATH "../..") +FILE(GLOB FREERTOS_KERNEL_SOURCE ${FREERTOS_KERNEL_PATH}/*.c) +FILE(GLOB FREERTOS_PORT_CODE ${FREERTOS_KERNEL_PATH}/portable/template/*.c) + +# Coverity incorrectly infers the type of pdTRUE and pdFALSE as boolean because +# of their names. This generates multiple false positive warnings about type +# mismatch. Replace pdTRUE with pdPASS and pdFALSE with pdFAIL to avoid these +# false positive warnings. This workaround will not be needed after Coverity +# fixes the issue of incorrectly inferring the type of pdTRUE and pdFALSE as +# boolean. +add_custom_target(fix_source ALL + COMMAND sed -i -b -e 's/pdFALSE/pdFAIL/g' -e 's/pdTRUE/pdPASS/g' ${FREERTOS_KERNEL_SOURCE} ${FREERTOS_PORT_CODE} + DEPENDS ${FREERTOS_KERNEL_SOURCE} ${FREERTOS_PORT_CODE}) + +# Add the freertos_config for FreeRTOS-Kernel. +add_library(freertos_config INTERFACE) + +target_include_directories(freertos_config + INTERFACE + ./) + +if (DEFINED FREERTOS_SMP_EXAMPLE AND FREERTOS_SMP_EXAMPLE STREQUAL "1") + message(STATUS "Build FreeRTOS SMP example") + # Adding the following configurations to build SMP template port + add_compile_options( -DconfigNUMBER_OF_CORES=2 -DconfigUSE_PASSIVE_IDLE_HOOK=0 ) +endif() + +# Select the heap. Values between 1-5 will pick a heap. +set(FREERTOS_HEAP "3" CACHE STRING "" FORCE) + +# Select the FreeRTOS port. +set(FREERTOS_PORT "TEMPLATE" CACHE STRING "" FORCE) + +# Add the FreeRTOS-Kernel subdirectory. +add_subdirectory(${FREERTOS_KERNEL_PATH} FreeRTOS-Kernel) + +add_executable(${PROJECT_NAME} + ../cmake_example/main.c) + +add_dependencies(${PROJECT_NAME} fix_source) + +target_link_libraries(${PROJECT_NAME} freertos_kernel freertos_config) diff --git a/examples/coverity/FreeRTOSConfig.h b/examples/coverity/FreeRTOSConfig.h new file mode 100644 index 000000000..5feaa40de --- /dev/null +++ b/examples/coverity/FreeRTOSConfig.h @@ -0,0 +1,133 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/******************************************************************************/ +/* Hardware description related definitions. **********************************/ +/******************************************************************************/ + +#define configCPU_CLOCK_HZ ( ( unsigned long ) 20000000 ) + +/******************************************************************************/ +/* Scheduling behaviour related definitions. **********************************/ +/******************************************************************************/ + +#define configTICK_RATE_HZ ( 100U ) +#define configUSE_PREEMPTION 1 +#define configUSE_TIME_SLICING 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configUSE_TICKLESS_IDLE 1 +#define configMAX_PRIORITIES 5U +#define configMINIMAL_STACK_SIZE 128U +#define configMAX_TASK_NAME_LEN 4U +#define configTICK_TYPE_WIDTH_IN_BITS TICK_TYPE_WIDTH_64_BITS +#define configIDLE_SHOULD_YIELD 1 +#define configTASK_NOTIFICATION_ARRAY_ENTRIES 1U +#define configQUEUE_REGISTRY_SIZE 0U +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 0 +#define configSTACK_DEPTH_TYPE size_t +#define configMESSAGE_BUFFER_LENGTH_TYPE size_t +#define configUSE_NEWLIB_REENTRANT 0 + +/******************************************************************************/ +/* Software timer related definitions. ****************************************/ +/******************************************************************************/ + +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1U ) +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE +#define configTIMER_QUEUE_LENGTH 10U + +/******************************************************************************/ +/* Memory allocation related definitions. *************************************/ +/******************************************************************************/ + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configTOTAL_HEAP_SIZE 4096U +#define configAPPLICATION_ALLOCATED_HEAP 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 +#define configUSE_MINI_LIST_ITEM 0 + +/******************************************************************************/ +/* Interrupt nesting behaviour configuration. *********************************/ +/******************************************************************************/ + +#define configKERNEL_INTERRUPT_PRIORITY 0U +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 0U +#define configMAX_API_CALL_INTERRUPT_PRIORITY 0U + +/******************************************************************************/ +/* Hook and callback function related definitions. ****************************/ +/******************************************************************************/ + +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 +#define configCHECK_FOR_STACK_OVERFLOW 0 + +/******************************************************************************/ +/* Run time and task stats gathering related definitions. *********************/ +/******************************************************************************/ + +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 0 +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 +#define configKERNEL_PROVIDED_STATIC_MEMORY 1 + +/******************************************************************************/ +/* Definitions that include or exclude functionality. *************************/ +/******************************************************************************/ + +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_QUEUE_SETS 1 +#define configUSE_APPLICATION_TASK_TAG 1 +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define INCLUDE_xTaskGetIdleTaskHandle 1 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskAbortDelay 1 +#define INCLUDE_xTaskGetHandle 1 +#define INCLUDE_xTaskResumeFromISR 1 + +#endif /* FREERTOS_CONFIG_H */ diff --git a/examples/coverity/README.md b/examples/coverity/README.md new file mode 100644 index 000000000..60df69343 --- /dev/null +++ b/examples/coverity/README.md @@ -0,0 +1,64 @@ +# MISRA Compliance for FreeRTOS-Kernel +FreeRTOS-Kernel is MISRA C:2012 compliant. This directory contains a project to +run [Synopsys Coverity](https://www.blackduck.com/static-analysis-tools-sast/coverity.html) +for checking MISRA compliance. + +> **Note** +Coverity version 2023.6.1 incorrectly infers the type of `pdTRUE` and `pdFALSE` +as boolean because of their names, resulting in multiple false positive warnings +about type mismatch. We replace `pdTRUE` with `pdPASS` and `pdFALSE` with +`pdFAIL` to avoid these false positive warnings. This workaround will not be +needed after Coverity fixes the issue of incorrectly inferring the type of +`pdTRUE` and `pdFALSE` as boolean. + +Deviations from the MISRA C:2012 guidelines are documented in +[MISRA.md](../../MISRA.md) and [coverity_misra.config](coverity_misra.config) +files. + +## Getting Started +### Prerequisites +Coverity can be run on any platform mentioned [here](https://documentation.blackduck.com/bundle/coverity-docs/page/deploy-install-guide/topics/supported_platforms_for_coverity_analysis.html). +The following are the prerequisites to generate coverity report: + +1. CMake version > 3.13.0 (You can check whether you have this by typing `cmake --version`). +2. GCC compiler. + - See download and installation instructions [here](https://gcc.gnu.org/install/). +3. Clone the repo using the following command: + - `git clone https://github.com/FreeRTOS/FreeRTOS-Kernel.git ./FreeRTOS-Kernel` + +### Generating Report +Go to the root directory of the FreeRTOS-Kernel repo and run the following +commands in a terminal: +1. Update the compiler configuration in Coverity: + ~~~ + cov-configure --force --compiler cc --comptype gcc + ~~~ +2. Create the build files using CMake in a `build` directory: + +Single core FreeRTOS: + ~~~ + cmake -B build -S examples/coverity + ~~~ + +SMP FreeRTOS: + ~~~ + cmake -B build -S examples/coverity -DFREERTOS_SMP_EXAMPLE=1 + ~~~ +3. Build the (pseudo) application: + ~~~ + cd build/ + cov-build --emit-complementary-info --dir cov-out make coverity + ~~~ +4. Go to the Coverity output directory (`cov-out`) and begin Coverity static + analysis: + ~~~ + cov-analyze --dir ./cov-out \ + --coding-standard-config ../examples/coverity/coverity_misra.config \ + --tu-pattern "file('[A-Za-z_]+\.c') && ( ! file('main.c') ) && ( ! file('port.c') )" + ~~~ +5. Generate the HTML report: + ~~~ + cov-format-errors --dir ./cov-out --html-output html-output + ~~~ + +HTML report should now be generated in a directory named `html-output`. diff --git a/examples/coverity/coverity_misra.config b/examples/coverity/coverity_misra.config new file mode 100644 index 000000000..631142806 --- /dev/null +++ b/examples/coverity/coverity_misra.config @@ -0,0 +1,95 @@ +{ + "version" : "2.0", + "standard" : "c2012", + "title": "Coverity MISRA Configuration", + "deviations" : [ + { + "deviation": "Rule 1.2", + "reason": "Allow use of __attribute__ for necessary functions placement in specific memory regions." + }, + { + "deviation": "Rule 3.1", + "reason": "We post HTTP links in code comments which contain // inside comments blocks." + }, + { + "deviation": "Rule 14.4", + "reason": "do while( 0 ) pattern is used in macros to prevent extra semi-colon." + }, + { + "deviation": "Directive 4.4", + "reason": "Code snippet is used in comment to help explanation." + }, + { + "deviation": "Directive 4.5", + "reason": "Allow names that MISRA considers ambiguous." + }, + { + "deviation": "Directive 4.6", + "reason": "Allow port to use primitive type with typedefs." + }, + { + "deviation": "Directive 4.8", + "reason": "HeapRegion_t and HeapStats_t are used only in heap files but declared in portable.h which is included in multiple source files. As a result, these definitions appear in multiple source files where they are not used." + }, + { + "deviation": "Directive 4.9", + "reason": "FreeRTOS-Kernel is optimised to work on small micro-controllers. To achieve that, function-like macros are used." + }, + { + "deviation": "Rule 2.3", + "reason": "FreeRTOS defines types which is used in application." + }, + { + "deviation": "Rule 2.4", + "reason": "Allow to define unused tag." + }, + { + "deviation": "Rule 2.5", + "reason": "Allow to define unused macro." + }, + { + "deviation": "Rule 5.9", + "reason": "Allow to define identifier with the same name in structure and global variable." + }, + { + "deviation": "Rule 8.7", + "reason": "API functions are not used by the library outside of the files they are defined; however, they must be externally visible in order to be used by an application." + }, + { + "deviation": "Rule 8.9", + "reason": "Allow to object to be defined in wider scope for debug purpose." + }, + { + "deviation": "Rule 8.13", + "reason": "Allow to not to use const-qualified type for callback function." + }, + { + "deviation": "Rule 11.4", + "reason": "Allow to convert between a pointer to object and an interger type for stack alignment." + }, + { + "deviation": "Rule 15.4", + "reason": "Allow to use multiple break statements in a loop." + }, + { + "deviation": "Rule 15.5", + "reason": "Allow to use multiple points of exit." + }, + { + "deviation": "Rule 17.8", + "reason": "Allow to update the parameters of a function." + }, + { + "deviation": "Rule 18.4", + "reason": "Allow to use pointer arithmetic." + }, + { + "deviation": "Rule 19.2", + "reason": "Allow to use union." + }, + { + "deviation": "Rule 20.5", + "reason": "Allow to use #undef for MPU wrappers." + } + ] +} diff --git a/examples/template_configuration/FreeRTOSConfig.h b/examples/template_configuration/FreeRTOSConfig.h new file mode 100644 index 000000000..7859a5c77 --- /dev/null +++ b/examples/template_configuration/FreeRTOSConfig.h @@ -0,0 +1,668 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/******************************************************************************* + * This file provides an example FreeRTOSConfig.h header file, inclusive of an + * abbreviated explanation of each configuration item. Online and reference + * documentation provides more information. + * https://www.freertos.org/a00110.html + * + * Constant values enclosed in square brackets ('[' and ']') must be completed + * before this file will build. + * + * Use the FreeRTOSConfig.h supplied with the RTOS port in use rather than this + * generic file, if one is available. + ******************************************************************************/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/******************************************************************************/ +/* Hardware description related definitions. **********************************/ +/******************************************************************************/ + +/* In most cases, configCPU_CLOCK_HZ must be set to the frequency of the clock + * that drives the peripheral used to generate the kernels periodic tick + * interrupt. The default value is set to 20MHz and matches the QEMU demo + * settings. Your application will certainly need a different value so set this + * correctly. This is very often, but not always, equal to the main system clock + * frequency. */ +#define configCPU_CLOCK_HZ ( ( unsigned long ) 20000000 ) + +/* configSYSTICK_CLOCK_HZ is an optional parameter for ARM Cortex-M ports only. + * + * By default ARM Cortex-M ports generate the RTOS tick interrupt from the + * Cortex-M SysTick timer. Most Cortex-M MCUs run the SysTick timer at the same + * frequency as the MCU itself - when that is the case configSYSTICK_CLOCK_HZ is + * not needed and should be left undefined. If the SysTick timer is clocked at a + * different frequency to the MCU core then set configCPU_CLOCK_HZ to the MCU + * clock frequency, as normal, and configSYSTICK_CLOCK_HZ to the SysTick clock + * frequency. Not used if left undefined. + * The default value is undefined (commented out). If you need this value bring + * it back and set it to a suitable value. */ + +/* + #define configSYSTICK_CLOCK_HZ [Platform specific] + */ + +/******************************************************************************/ +/* Scheduling behaviour related definitions. **********************************/ +/******************************************************************************/ + +/* configTICK_RATE_HZ sets frequency of the tick interrupt in Hz, normally + * calculated from the configCPU_CLOCK_HZ value. */ +#define configTICK_RATE_HZ 100 + +/* Set configUSE_PREEMPTION to 1 to use pre-emptive scheduling. Set + * configUSE_PREEMPTION to 0 to use co-operative scheduling. + * See https://www.freertos.org/single-core-amp-smp-rtos-scheduling.html. */ +#define configUSE_PREEMPTION 1 + +/* Set configUSE_TIME_SLICING to 1 to have the scheduler switch between Ready + * state tasks of equal priority on every tick interrupt. Set + * configUSE_TIME_SLICING to 0 to prevent the scheduler switching between Ready + * state tasks just because there was a tick interrupt. See + * https://freertos.org/single-core-amp-smp-rtos-scheduling.html. */ +#define configUSE_TIME_SLICING 0 + +/* Set configUSE_PORT_OPTIMISED_TASK_SELECTION to 1 to select the next task to + * run using an algorithm optimised to the instruction set of the target + * hardware - normally using a count leading zeros assembly instruction. Set to + * 0 to select the next task to run using a generic C algorithm that works for + * all FreeRTOS ports. Not all FreeRTOS ports have this option. Defaults to 0 + * if left undefined. */ +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + +/* Set configUSE_TICKLESS_IDLE to 1 to use the low power tickless mode. Set to + * 0 to keep the tick interrupt running at all times. Not all FreeRTOS ports + * support tickless mode. See + * https://www.freertos.org/low-power-tickless-rtos.html Defaults to 0 if left + * undefined. */ +#define configUSE_TICKLESS_IDLE 0 + +/* configMAX_PRIORITIES Sets the number of available task priorities. Tasks can + * be assigned priorities of 0 to (configMAX_PRIORITIES - 1). Zero is the + * lowest priority. */ +#define configMAX_PRIORITIES 5 + +/* configMINIMAL_STACK_SIZE defines the size of the stack used by the Idle task + * (in words, not in bytes!). The kernel does not use this constant for any + * other purpose. Demo applications use the constant to make the demos somewhat + * portable across hardware architectures. */ +#define configMINIMAL_STACK_SIZE 128 + +/* configMAX_TASK_NAME_LEN sets the maximum length (in characters) of a task's + * human readable name. Includes the NULL terminator. */ +#define configMAX_TASK_NAME_LEN 16 + +/* Time is measured in 'ticks' - which is the number of times the tick interrupt + * has executed since the RTOS kernel was started. + * The tick count is held in a variable of type TickType_t. + * + * configTICK_TYPE_WIDTH_IN_BITS controls the type (and therefore bit-width) of + * TickType_t: + * + * Defining configTICK_TYPE_WIDTH_IN_BITS as TICK_TYPE_WIDTH_16_BITS causes + * TickType_t to be defined (typedef'ed) as an unsigned 16-bit type. + * + * Defining configTICK_TYPE_WIDTH_IN_BITS as TICK_TYPE_WIDTH_32_BITS causes + * TickType_t to be defined (typedef'ed) as an unsigned 32-bit type. + * + * Defining configTICK_TYPE_WIDTH_IN_BITS as TICK_TYPE_WIDTH_64_BITS causes + * TickType_t to be defined (typedef'ed) as an unsigned 64-bit type. */ +#define configTICK_TYPE_WIDTH_IN_BITS TICK_TYPE_WIDTH_64_BITS + +/* Set configIDLE_SHOULD_YIELD to 1 to have the Idle task yield to an + * application task if there is an Idle priority (priority 0) application task + * that can run. Set to 0 to have the Idle task use all of its timeslice. + * Default to 1 if left undefined. */ +#define configIDLE_SHOULD_YIELD 1 + +/* Each task has an array of task notifications. + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array. See https://www.freertos.org/RTOS-task-notifications.html Defaults to + * 1 if left undefined. */ +#define configTASK_NOTIFICATION_ARRAY_ENTRIES 1 + +/* configQUEUE_REGISTRY_SIZE sets the maximum number of queues and semaphores + * that can be referenced from the queue registry. Only required when using a + * kernel aware debugger. Defaults to 0 if left undefined. */ +#define configQUEUE_REGISTRY_SIZE 0 + +/* Set configENABLE_BACKWARD_COMPATIBILITY to 1 to map function names and + * datatypes from old version of FreeRTOS to their latest equivalent. Defaults + * to 1 if left undefined. */ +#define configENABLE_BACKWARD_COMPATIBILITY 0 + +/* Each task has its own array of pointers that can be used as thread local + * storage. configNUM_THREAD_LOCAL_STORAGE_POINTERS set the number of indexes + * in the array. See + * https://www.freertos.org/thread-local-storage-pointers.html Defaults to 0 if + * left undefined. */ +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 0 + +/* When configUSE_MINI_LIST_ITEM is set to 0, MiniListItem_t and ListItem_t are + * both the same. When configUSE_MINI_LIST_ITEM is set to 1, MiniListItem_t + * contains 3 fewer fields than ListItem_t which saves some RAM at the cost of + * violating strict aliasing rules which some compilers depend on for + * optimization. Defaults to 1 if left undefined. */ +#define configUSE_MINI_LIST_ITEM 1 + +/* Sets the type used by the parameter to xTaskCreate() that specifies the stack + * size of the task being created. The same type is used to return information + * about stack usage in various other API calls. Defaults to size_t if left + * undefined. */ +#define configSTACK_DEPTH_TYPE size_t + +/* configMESSAGE_BUFFER_LENGTH_TYPE sets the type used to store the length of + * each message written to a FreeRTOS message buffer (the length is also written + * to the message buffer. Defaults to size_t if left undefined - but that may + * waste space if messages never go above a length that could be held in a + * uint8_t. */ +#define configMESSAGE_BUFFER_LENGTH_TYPE size_t + +/* If configHEAP_CLEAR_MEMORY_ON_FREE is set to 1, then blocks of memory + * allocated using pvPortMalloc() will be cleared (i.e. set to zero) when freed + * using vPortFree(). Defaults to 0 if left undefined. */ +#define configHEAP_CLEAR_MEMORY_ON_FREE 1 + +/* vTaskList and vTaskGetRunTimeStats APIs take a buffer as a parameter and + * assume that the length of the buffer is configSTATS_BUFFER_MAX_LENGTH. + * Defaults to 0xFFFF if left undefined. New applications are recommended to use + * vTaskListTasks and vTaskGetRunTimeStatistics APIs instead and supply the + * length of the buffer explicitly to avoid memory corruption. */ +#define configSTATS_BUFFER_MAX_LENGTH 0xFFFF + +/* Set configUSE_NEWLIB_REENTRANT to 1 to have a newlib reent structure + * allocated for each task. Set to 0 to not support newlib reent structures. + * Default to 0 if left undefined. + * + * Note Newlib support has been included by popular demand, but is not used or + * tested by the FreeRTOS maintainers themselves. FreeRTOS is not responsible + * for resulting newlib operation. User must be familiar with newlib and must + * provide system-wide implementations of the necessary stubs. Note that (at the + * time of writing) the current newlib design implements a system-wide malloc() + * that must be provided with locks. */ +#define configUSE_NEWLIB_REENTRANT 0 + +/******************************************************************************/ +/* Software timer related definitions. ****************************************/ +/******************************************************************************/ + +/* Set configUSE_TIMERS to 1 to include software timer functionality in the + * build. Set to 0 to exclude software timer functionality from the build. The + * FreeRTOS/source/timers.c source file must be included in the build if + * configUSE_TIMERS is set to 1. Default to 0 if left undefined. See + * https://www.freertos.org/RTOS-software-timer.html. */ +#define configUSE_TIMERS 1 + +/* configTIMER_TASK_PRIORITY sets the priority used by the timer task. Only + * used if configUSE_TIMERS is set to 1. The timer task is a standard FreeRTOS + * task, so its priority is set like any other task. See + * https://www.freertos.org/RTOS-software-timer-service-daemon-task.html Only + * used if configUSE_TIMERS is set to 1. */ +#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) + +/* configTIMER_TASK_STACK_DEPTH sets the size of the stack allocated to the + * timer task (in words, not in bytes!). The timer task is a standard FreeRTOS + * task. See + * https://www.freertos.org/RTOS-software-timer-service-daemon-task.html Only + * used if configUSE_TIMERS is set to 1. */ +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* configTIMER_QUEUE_LENGTH sets the length of the queue (the number of discrete + * items the queue can hold) used to send commands to the timer task. See + * https://www.freertos.org/RTOS-software-timer-service-daemon-task.html Only + * used if configUSE_TIMERS is set to 1. */ +#define configTIMER_QUEUE_LENGTH 10 + +/******************************************************************************/ +/* Event Group related definitions. *******************************************/ +/******************************************************************************/ + +/* Set configUSE_EVENT_GROUPS to 1 to include event group functionality in the + * build. Set to 0 to exclude event group functionality from the build. The + * FreeRTOS/source/event_groups.c source file must be included in the build if + * configUSE_EVENT_GROUPS is set to 1. Defaults to 1 if left undefined. */ + +#define configUSE_EVENT_GROUPS 1 + +/******************************************************************************/ +/* Stream Buffer related definitions. *****************************************/ +/******************************************************************************/ + +/* Set configUSE_STREAM_BUFFERS to 1 to include stream buffer functionality in + * the build. Set to 0 to exclude event group functionality from the build. The + * FreeRTOS/source/stream_buffer.c source file must be included in the build if + * configUSE_STREAM_BUFFERS is set to 1. Defaults to 1 if left undefined. */ + +#define configUSE_STREAM_BUFFERS 1 + +/******************************************************************************/ +/* Memory allocation related definitions. *************************************/ +/******************************************************************************/ + +/* Set configSUPPORT_STATIC_ALLOCATION to 1 to include FreeRTOS API functions + * that create FreeRTOS objects (tasks, queues, etc.) using statically allocated + * memory in the build. Set to 0 to exclude the ability to create statically + * allocated objects from the build. Defaults to 0 if left undefined. See + * https://www.freertos.org/Static_Vs_Dynamic_Memory_Allocation.html. */ +#define configSUPPORT_STATIC_ALLOCATION 1 + +/* Set configSUPPORT_DYNAMIC_ALLOCATION to 1 to include FreeRTOS API functions + * that create FreeRTOS objects (tasks, queues, etc.) using dynamically + * allocated memory in the build. Set to 0 to exclude the ability to create + * dynamically allocated objects from the build. Defaults to 1 if left + * undefined. See + * https://www.freertos.org/Static_Vs_Dynamic_Memory_Allocation.html. */ +#define configSUPPORT_DYNAMIC_ALLOCATION 1 + +/* Sets the total size of the FreeRTOS heap, in bytes, when heap_1.c, heap_2.c + * or heap_4.c are included in the build. This value is defaulted to 4096 bytes + * but it must be tailored to each application. Note the heap will appear in + * the .bss section. See https://www.freertos.org/a00111.html. */ +#define configTOTAL_HEAP_SIZE 4096 + +/* Set configAPPLICATION_ALLOCATED_HEAP to 1 to have the application allocate + * the array used as the FreeRTOS heap. Set to 0 to have the linker allocate + * the array used as the FreeRTOS heap. Defaults to 0 if left undefined. */ +#define configAPPLICATION_ALLOCATED_HEAP 0 + +/* Set configSTACK_ALLOCATION_FROM_SEPARATE_HEAP to 1 to have task stacks + * allocated from somewhere other than the FreeRTOS heap. This is useful if you + * want to ensure stacks are held in fast memory. Set to 0 to have task stacks + * come from the standard FreeRTOS heap. The application writer must provide + * implementations for pvPortMallocStack() and vPortFreeStack() if set to 1. + * Defaults to 0 if left undefined. */ +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +/* Set configENABLE_HEAP_PROTECTOR to 1 to enable bounds checking and + * obfuscation to internal heap block pointers in heap_4.c and heap_5.c to help + * catch pointer corruptions. Defaults to 0 if left undefined. */ +#define configENABLE_HEAP_PROTECTOR 0 + +/******************************************************************************/ +/* Interrupt nesting behaviour configuration. *********************************/ +/******************************************************************************/ + +/* configKERNEL_INTERRUPT_PRIORITY sets the priority of the tick and context + * switch performing interrupts. Not supported by all FreeRTOS ports. See + * https://www.freertos.org/RTOS-Cortex-M3-M4.html for information specific to + * ARM Cortex-M devices. */ +#define configKERNEL_INTERRUPT_PRIORITY 0 + +/* configMAX_SYSCALL_INTERRUPT_PRIORITY sets the interrupt priority above which + * FreeRTOS API calls must not be made. Interrupts above this priority are + * never disabled, so never delayed by RTOS activity. The default value is set + * to the highest interrupt priority (0). Not supported by all FreeRTOS ports. + * See https://www.freertos.org/RTOS-Cortex-M3-M4.html for information specific + * to ARM Cortex-M devices. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 0 + +/* Another name for configMAX_SYSCALL_INTERRUPT_PRIORITY - the name used depends + * on the FreeRTOS port. */ +#define configMAX_API_CALL_INTERRUPT_PRIORITY 0 + +/******************************************************************************/ +/* Hook and callback function related definitions. ****************************/ +/******************************************************************************/ + +/* Set the following configUSE_* constants to 1 to include the named hook + * functionality in the build. Set to 0 to exclude the hook functionality from + * the build. The application writer is responsible for providing the hook + * function for any set to 1. See https://www.freertos.org/a00016.html. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 + +/* Set configUSE_SB_COMPLETED_CALLBACK to 1 to have send and receive completed + * callbacks for each instance of a stream buffer or message buffer. When the + * option is set to 1, APIs xStreamBufferCreateWithCallback() and + * xStreamBufferCreateStaticWithCallback() (and likewise APIs for message + * buffer) can be used to create a stream buffer or message buffer instance + * with application provided callbacks. Defaults to 0 if left undefined. */ +#define configUSE_SB_COMPLETED_CALLBACK 0 + +/* Set configCHECK_FOR_STACK_OVERFLOW to 1 or 2 for FreeRTOS to check for a + * stack overflow at the time of a context switch. Set to 0 to not look for a + * stack overflow. If configCHECK_FOR_STACK_OVERFLOW is 1 then the check only + * looks for the stack pointer being out of bounds when a task's context is + * saved to its stack - this is fast but somewhat ineffective. If + * configCHECK_FOR_STACK_OVERFLOW is 2 then the check looks for a pattern + * written to the end of a task's stack having been overwritten. This is + * slower, but will catch most (but not all) stack overflows. The application + * writer must provide the stack overflow callback when + * configCHECK_FOR_STACK_OVERFLOW is set to 1. See + * https://www.freertos.org/Stacks-and-stack-overflow-checking.html Defaults to + * 0 if left undefined. */ +#define configCHECK_FOR_STACK_OVERFLOW 2 + +/******************************************************************************/ +/* Run time and task stats gathering related definitions. *********************/ +/******************************************************************************/ + +/* Set configGENERATE_RUN_TIME_STATS to 1 to have FreeRTOS collect data on the + * processing time used by each task. Set to 0 to not collect the data. The + * application writer needs to provide a clock source if set to 1. Defaults to + * 0 if left undefined. See https://www.freertos.org/rtos-run-time-stats.html. + */ +#define configGENERATE_RUN_TIME_STATS 0 + +/* Set configUSE_TRACE_FACILITY to include additional task structure members + * are used by trace and visualisation functions and tools. Set to 0 to exclude + * the additional information from the structures. Defaults to 0 if left + * undefined. */ +#define configUSE_TRACE_FACILITY 0 + +/* Set to 1 to include the vTaskList() and vTaskGetRunTimeStats() functions in + * the build. Set to 0 to exclude these functions from the build. These two + * functions introduce a dependency on string formatting functions that would + * otherwise not exist - hence they are kept separate. Defaults to 0 if left + * undefined. */ +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/******************************************************************************/ +/* Co-routine related definitions. ********************************************/ +/******************************************************************************/ + +/* Set configUSE_CO_ROUTINES to 1 to include co-routine functionality in the + * build, or 0 to omit co-routine functionality from the build. To include + * co-routines, croutine.c must be included in the project. Defaults to 0 if + * left undefined. */ +#define configUSE_CO_ROUTINES 0 + +/* configMAX_CO_ROUTINE_PRIORITIES defines the number of priorities available + * to the application co-routines. Any number of co-routines can share the same + * priority. Defaults to 0 if left undefined. */ +#define configMAX_CO_ROUTINE_PRIORITIES 1 + +/******************************************************************************/ +/* Debugging assistance. ******************************************************/ +/******************************************************************************/ + +/* configASSERT() has the same semantics as the standard C assert(). It can + * either be defined to take an action when the assertion fails, or not defined + * at all (i.e. comment out or delete the definitions) to completely remove + * assertions. configASSERT() can be defined to anything you want, for example + * you can call a function if an assert fails that passes the filename and line + * number of the failing assert (for example, "vAssertCalled( __FILE__, __LINE__ + * )" or it can simple disable interrupts and sit in a loop to halt all + * execution on the failing line for viewing in a debugger. */ + +/* *INDENT-OFF* */ +#define configASSERT( x ) \ + if( ( x ) == 0 ) \ + { \ + taskDISABLE_INTERRUPTS(); \ + for( ; ; ) \ + ; \ + } +/* *INDENT-ON* */ + +/******************************************************************************/ +/* FreeRTOS MPU specific definitions. *****************************************/ +/******************************************************************************/ + +/* If configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS is set to 1 then + * the application writer can provide functions that execute in privileged mode. + * See: + * https://www.freertos.org/a00110.html#configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS + * Defaults to 0 if left undefined. Only used by the FreeRTOS Cortex-M MPU + * ports, not the standard ARMv7-M Cortex-M port. */ +#define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS 0 + +/* Set configTOTAL_MPU_REGIONS to the number of MPU regions implemented on your + * target hardware. Normally 8 or 16. Only used by the FreeRTOS Cortex-M MPU + * ports, not the standard ARMv7-M Cortex-M port. Defaults to 8 if left + * undefined. */ +#define configTOTAL_MPU_REGIONS 8 + +/* configTEX_S_C_B_FLASH allows application writers to override the default + * values for the for TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits + * for the MPU region covering Flash. Defaults to 0x07UL (which means TEX=000, + * S=1, C=1, B=1) if left undefined. Only used by the FreeRTOS Cortex-M MPU + * ports, not the standard ARMv7-M Cortex-M port. */ +#define configTEX_S_C_B_FLASH 0x07UL + +/* configTEX_S_C_B_SRAM allows application writers to override the default + * values for the for TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits + * for the MPU region covering RAM. Defaults to 0x07UL (which means TEX=000, + * S=1, C=1, B=1) if left undefined. Only used by the FreeRTOS Cortex-M MPU + * ports, not the standard ARMv7-M Cortex-M port. */ +#define configTEX_S_C_B_SRAM 0x07UL + +/* Set configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY to 0 to prevent any privilege + * escalations originating from outside of the kernel code itself. Set to 1 to + * allow application tasks to raise privilege. Defaults to 1 if left undefined. + * Only used by the FreeRTOS Cortex-M MPU ports, not the standard ARMv7-M + * Cortex-M port. */ +#define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 1 + +/* Set configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS to 1 to allow unprivileged + * tasks enter critical sections (effectively mask interrupts). Set to 0 to + * prevent unprivileged tasks entering critical sections. Defaults to 1 if left + * undefined. Only used by the FreeRTOS Cortex-M MPU ports, not the standard + * ARMv7-M Cortex-M port. */ +#define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS 0 + +/* FreeRTOS Kernel version 10.6.0 introduced a new v2 MPU wrapper, namely + * mpu_wrappers_v2.c. Set configUSE_MPU_WRAPPERS_V1 to 0 to use the new v2 MPU + * wrapper. Set configUSE_MPU_WRAPPERS_V1 to 1 to use the old v1 MPU wrapper + * (mpu_wrappers.c). Defaults to 0 if left undefined. */ +#define configUSE_MPU_WRAPPERS_V1 0 + +/* When using the v2 MPU wrapper, set configPROTECTED_KERNEL_OBJECT_POOL_SIZE to + * the total number of kernel objects, which includes tasks, queues, semaphores, + * mutexes, event groups, timers, stream buffers and message buffers, in your + * application. The application will not be able to have more than + * configPROTECTED_KERNEL_OBJECT_POOL_SIZE kernel objects at any point of + * time. */ +#define configPROTECTED_KERNEL_OBJECT_POOL_SIZE 10 + +/* When using the v2 MPU wrapper, set configSYSTEM_CALL_STACK_SIZE to the size + * of the system call stack in words. Each task has a statically allocated + * memory buffer of this size which is used as the stack to execute system + * calls. For example, if configSYSTEM_CALL_STACK_SIZE is defined as 128 and + * there are 10 tasks in the application, the total amount of memory used for + * system call stacks is 128 * 10 = 1280 words. */ +#define configSYSTEM_CALL_STACK_SIZE 128 + +/* When using the v2 MPU wrapper, set configENABLE_ACCESS_CONTROL_LIST to 1 to + * enable Access Control List (ACL) feature. When ACL is enabled, an + * unprivileged task by default does not have access to any kernel object other + * than itself. The application writer needs to explicitly grant the + * unprivileged task access to the kernel objects it needs using the APIs + * provided for the same. Defaults to 0 if left undefined. */ +#define configENABLE_ACCESS_CONTROL_LIST 1 + +/******************************************************************************/ +/* SMP( Symmetric MultiProcessing ) Specific Configuration definitions. *******/ +/******************************************************************************/ + +/* Set configNUMBER_OF_CORES to the number of available processor cores. + * Defaults to 1 if left undefined. */ + +/* + #define configNUMBER_OF_CORES [Num of available cores] + */ + +/* When using SMP (i.e. configNUMBER_OF_CORES is greater than one), set + * configRUN_MULTIPLE_PRIORITIES to 0 to allow multiple tasks to run + * simultaneously only if they do not have equal priority, thereby maintaining + * the paradigm of a lower priority task never running if a higher priority task + * is able to run. If configRUN_MULTIPLE_PRIORITIES is set to 1, multiple tasks + * with different priorities may run simultaneously - so a higher and lower + * priority task may run on different cores at the same time. */ +#define configRUN_MULTIPLE_PRIORITIES 0 + +/* When using SMP (i.e. configNUMBER_OF_CORES is greater than one), set + * configUSE_CORE_AFFINITY to 1 to enable core affinity feature. When core + * affinity feature is enabled, the vTaskCoreAffinitySet and + * vTaskCoreAffinityGet APIs can be used to set and retrieve which cores a task + * can run on. If configUSE_CORE_AFFINITY is set to 0 then the FreeRTOS + * scheduler is free to run any task on any available core. */ +#define configUSE_CORE_AFFINITY 0 + +/* When using SMP with core affinity feature enabled, set + * configTASK_DEFAULT_CORE_AFFINITY to change the default core affinity mask for + * tasks created without an affinity mask specified. Setting the define to 1 + * would make such tasks run on core 0 and setting it to (1 << + * portGET_CORE_ID()) would make such tasks run on the current core. This config + * value is useful, if swapping tasks between cores is not supported (e.g. + * Tricore) or if legacy code should be controlled. Defaults to tskNO_AFFINITY + * if left undefined. */ +#define configTASK_DEFAULT_CORE_AFFINITY tskNO_AFFINITY + +/* When using SMP (i.e. configNUMBER_OF_CORES is greater than one), if + * configUSE_TASK_PREEMPTION_DISABLE is set to 1, individual tasks can be set to + * either pre-emptive or co-operative mode using the vTaskPreemptionDisable and + * vTaskPreemptionEnable APIs. */ +#define configUSE_TASK_PREEMPTION_DISABLE 0 + +/* When using SMP (i.e. configNUMBER_OF_CORES is greater than one), set + * configUSE_PASSIVE_IDLE_HOOK to 1 to allow the application writer to use + * the passive idle task hook to add background functionality without the + * overhead of a separate task. Defaults to 0 if left undefined. */ +#define configUSE_PASSIVE_IDLE_HOOK 0 + +/* When using SMP (i.e. configNUMBER_OF_CORES is greater than one), + * configTIMER_SERVICE_TASK_CORE_AFFINITY allows the application writer to set + * the core affinity of the RTOS Daemon/Timer Service task. Defaults to + * tskNO_AFFINITY if left undefined. */ +#define configTIMER_SERVICE_TASK_CORE_AFFINITY tskNO_AFFINITY + +/******************************************************************************/ +/* ARMv8-M secure side port related definitions. ******************************/ +/******************************************************************************/ + +/* secureconfigMAX_SECURE_CONTEXTS define the maximum number of tasks that can + * call into the secure side of an ARMv8-M chip. Not used by any other ports. + */ +#define secureconfigMAX_SECURE_CONTEXTS 5 + +/* Defines the kernel provided implementation of + * vApplicationGetIdleTaskMemory() and vApplicationGetTimerTaskMemory() + * to provide the memory that is used by the Idle task and Timer task + * respectively. The application can provide it's own implementation of + * vApplicationGetIdleTaskMemory() and vApplicationGetTimerTaskMemory() by + * setting configKERNEL_PROVIDED_STATIC_MEMORY to 0 or leaving it undefined. */ +#define configKERNEL_PROVIDED_STATIC_MEMORY 1 + +/******************************************************************************/ +/* ARMv8-M port Specific Configuration definitions. ***************************/ +/******************************************************************************/ + +/* Set configENABLE_TRUSTZONE to 1 when running FreeRTOS on the non-secure side + * to enable the TrustZone support in FreeRTOS ARMv8-M ports which allows the + * non-secure FreeRTOS tasks to call the (non-secure callable) functions + * exported from secure side. */ +#define configENABLE_TRUSTZONE 1 + +/* If the application writer does not want to use TrustZone, but the hardware + * does not support disabling TrustZone then the entire application (including + * the FreeRTOS scheduler) can run on the secure side without ever branching to + * the non-secure side. To do that, in addition to setting + * configENABLE_TRUSTZONE to 0, also set configRUN_FREERTOS_SECURE_ONLY to 1. */ +#define configRUN_FREERTOS_SECURE_ONLY 1 + +/* Set configENABLE_MPU to 1 to enable the Memory Protection Unit (MPU), or 0 + * to leave the Memory Protection Unit disabled. */ +#define configENABLE_MPU 1 + +/* Set configENABLE_FPU to 1 to enable the Floating Point Unit (FPU), or 0 + * to leave the Floating Point Unit disabled. */ +#define configENABLE_FPU 1 + +/* Set configENABLE_MVE to 1 to enable the M-Profile Vector Extension (MVE) + * support, or 0 to leave the MVE support disabled. This option is only + * applicable to Cortex-M52, Cortex-M55, Cortex-M85 and STAR-MC3 ports as + * M-Profile Vector Extension (MVE) is available only on these architectures. + * configENABLE_MVE must be left undefined, or defined to 0 for the + * Cortex-M23,Cortex-M33 and Cortex-M35P ports. */ +#define configENABLE_MVE 1 + +/******************************************************************************/ +/* ARMv7-M and ARMv8-M port Specific Configuration definitions. ***************/ +/******************************************************************************/ + +/* Set configCHECK_HANDLER_INSTALLATION to 1 to enable additional asserts to + * verify that the application has correctly installed FreeRTOS interrupt + * handlers. + * + * An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions vPortSVCHandler and + * xPortPendSVHandler for SVC call and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVC call and PendSV + * interrupts and route program control from those + * handlers to vPortSVCHandler and xPortPendSVHandler functions. The + * applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0. + * + * Defaults to 1 if left undefined. */ +#define configCHECK_HANDLER_INSTALLATION 1 + +/******************************************************************************/ +/* Definitions that include or exclude functionality. *************************/ +/******************************************************************************/ + +/* Set the following configUSE_* constants to 1 to include the named feature in + * the build, or 0 to exclude the named feature from the build. */ +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_QUEUE_SETS 0 +#define configUSE_APPLICATION_TASK_TAG 0 + +/* USE_POSIX_ERRNO enables the task global FreeRTOS_errno variable which will + * contain the most recent error for that task. */ +#define configUSE_POSIX_ERRNO 0 + +/* Set the following INCLUDE_* constants to 1 to include the named API function, + * or 0 to exclude the named API function. Most linkers will remove unused + * functions even when the constant is 1. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_xTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xTimerPendFunctionCall 0 +#define INCLUDE_xTaskAbortDelay 0 +#define INCLUDE_xTaskGetHandle 0 +#define INCLUDE_xTaskResumeFromISR 1 + +#endif /* FREERTOS_CONFIG_H */ diff --git a/examples/template_configuration/readme.md b/examples/template_configuration/readme.md new file mode 100644 index 000000000..61c81f975 --- /dev/null +++ b/examples/template_configuration/readme.md @@ -0,0 +1,7 @@ +# Configuration support for FreeRTOS + +## Overview + +Every FreeRTOS project requires FreeRTOSConfig.h located in their include path. In this folder you will find a sample FreeRTOSConfig.h that will assist you in preparing the configuration for your application. + +The FreeRTOSConfig.h in this folder is used in the minimal_freertos_example project provided and it not guaranteed to have the same configuration between updates. \ No newline at end of file diff --git a/include/CMakeLists.txt b/include/CMakeLists.txt new file mode 100644 index 000000000..46a1c3e7f --- /dev/null +++ b/include/CMakeLists.txt @@ -0,0 +1,15 @@ +# FreeRTOS internal cmake file. Do not use it in user top-level project + +add_library(freertos_kernel_include INTERFACE) + +target_include_directories(freertos_kernel_include + INTERFACE + . + # Note: DEPRECATED but still supported, may be removed in a future release. + $<$>:${FREERTOS_CONFIG_FILE_DIRECTORY}> +) + +target_link_libraries(freertos_kernel_include + INTERFACE + $<$:freertos_config> +) diff --git a/include/FreeRTOS.h b/include/FreeRTOS.h new file mode 100644 index 000000000..63e2feb51 --- /dev/null +++ b/include/FreeRTOS.h @@ -0,0 +1,3359 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef INC_FREERTOS_H +#define INC_FREERTOS_H + +/* + * Include the generic headers required for the FreeRTOS port being used. + */ +#include + +/* + * If stdint.h cannot be located then: + * + If using GCC ensure the -nostdint options is *not* being used. + * + Ensure the project's include path includes the directory in which your + * compiler stores stdint.h. + * + Set any compiler options necessary for it to support C99, as technically + * stdint.h is only mandatory with C99 (FreeRTOS does not require C99 in any + * other way). + * + The FreeRTOS download includes a simple stdint.h definition that can be + * used in cases where none is provided by the compiler. The files only + * contains the typedefs required to build FreeRTOS. Read the instructions + * in FreeRTOS/source/stdint.readme for more information. + */ +#include /* READ COMMENT ABOVE. */ + +/* Acceptable values for configTICK_TYPE_WIDTH_IN_BITS. */ +#define TICK_TYPE_WIDTH_16_BITS 0 +#define TICK_TYPE_WIDTH_32_BITS 1 +#define TICK_TYPE_WIDTH_64_BITS 2 + +/* Application specific configuration options. */ +#include "FreeRTOSConfig.h" + +#if !defined( configUSE_16_BIT_TICKS ) && !defined( configTICK_TYPE_WIDTH_IN_BITS ) + #error Missing definition: One of configUSE_16_BIT_TICKS and configTICK_TYPE_WIDTH_IN_BITS must be defined in FreeRTOSConfig.h. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#if defined( configUSE_16_BIT_TICKS ) && defined( configTICK_TYPE_WIDTH_IN_BITS ) + #error Only one of configUSE_16_BIT_TICKS and configTICK_TYPE_WIDTH_IN_BITS must be defined in FreeRTOSConfig.h. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +/* Define configTICK_TYPE_WIDTH_IN_BITS according to the + * value of configUSE_16_BIT_TICKS for backward compatibility. */ +#ifndef configTICK_TYPE_WIDTH_IN_BITS + #if ( configUSE_16_BIT_TICKS == 1 ) + #define configTICK_TYPE_WIDTH_IN_BITS TICK_TYPE_WIDTH_16_BITS + #else + #define configTICK_TYPE_WIDTH_IN_BITS TICK_TYPE_WIDTH_32_BITS + #endif +#endif + +/* Set configUSE_MPU_WRAPPERS_V1 to 1 to use MPU wrappers v1. */ +#ifndef configUSE_MPU_WRAPPERS_V1 + #define configUSE_MPU_WRAPPERS_V1 0 +#endif + +/* Set configENABLE_ACCESS_CONTROL_LIST to 1 to enable access control list support. */ +#ifndef configENABLE_ACCESS_CONTROL_LIST + #define configENABLE_ACCESS_CONTROL_LIST 0 +#endif + +/* Set default value of configNUMBER_OF_CORES to 1 to use single core FreeRTOS. */ +#ifndef configNUMBER_OF_CORES + #define configNUMBER_OF_CORES 1 +#endif + +#ifndef configUSE_MALLOC_FAILED_HOOK + #define configUSE_MALLOC_FAILED_HOOK 0 +#endif + +#ifndef configASSERT + #define configASSERT( x ) + #define configASSERT_DEFINED 0 +#else + #define configASSERT_DEFINED 1 +#endif + +/* Set configENABLE_PAC and/or configENABLE_BTI to 1 to enable PAC and/or BTI + * support and 0 to disable them. These are currently used in ARMv8.1-M ports. */ +#ifndef configENABLE_PAC + #define configENABLE_PAC 0 +#endif + +#ifndef configENABLE_BTI + #define configENABLE_BTI 0 +#endif + +/* Basic FreeRTOS definitions. */ +#include "projdefs.h" + +/* Definitions specific to the port being used. */ +#include "portable.h" + +/* Must be defaulted before configUSE_NEWLIB_REENTRANT is used below. */ +#ifndef configUSE_NEWLIB_REENTRANT + #define configUSE_NEWLIB_REENTRANT 0 +#endif + +/* Required if struct _reent is used. */ +#if ( configUSE_NEWLIB_REENTRANT == 1 ) + + #include "newlib-freertos.h" + +#endif /* if ( configUSE_NEWLIB_REENTRANT == 1 ) */ + +/* Must be defaulted before configUSE_PICOLIBC_TLS is used below. */ +#ifndef configUSE_PICOLIBC_TLS + #define configUSE_PICOLIBC_TLS 0 +#endif + +#if ( configUSE_PICOLIBC_TLS == 1 ) + + #include "picolibc-freertos.h" + +#endif /* if ( configUSE_PICOLIBC_TLS == 1 ) */ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +#ifndef configUSE_C_RUNTIME_TLS_SUPPORT + #define configUSE_C_RUNTIME_TLS_SUPPORT 0 +#endif + +#if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) + + #ifndef configTLS_BLOCK_TYPE + #error Missing definition: configTLS_BLOCK_TYPE must be defined in FreeRTOSConfig.h when configUSE_C_RUNTIME_TLS_SUPPORT is set to 1. + #endif + + #ifndef configINIT_TLS_BLOCK + #error Missing definition: configINIT_TLS_BLOCK must be defined in FreeRTOSConfig.h when configUSE_C_RUNTIME_TLS_SUPPORT is set to 1. + #endif + + #ifndef configSET_TLS_BLOCK + #error Missing definition: configSET_TLS_BLOCK must be defined in FreeRTOSConfig.h when configUSE_C_RUNTIME_TLS_SUPPORT is set to 1. + #endif + + #ifndef configDEINIT_TLS_BLOCK + #error Missing definition: configDEINIT_TLS_BLOCK must be defined in FreeRTOSConfig.h when configUSE_C_RUNTIME_TLS_SUPPORT is set to 1. + #endif +#endif /* if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) */ + +/* + * Check all the required application specific macros have been defined. + * These macros are application specific and (as downloaded) are defined + * within FreeRTOSConfig.h. + */ + +#ifndef configMINIMAL_STACK_SIZE + #error Missing definition: configMINIMAL_STACK_SIZE must be defined in FreeRTOSConfig.h. configMINIMAL_STACK_SIZE defines the size (in words) of the stack allocated to the idle task. Refer to the demo project provided for your port for a suitable value. +#endif + +#ifndef configMAX_PRIORITIES + #error Missing definition: configMAX_PRIORITIES must be defined in FreeRTOSConfig.h. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#if configMAX_PRIORITIES < 1 + #error configMAX_PRIORITIES must be defined to be greater than or equal to 1. +#endif + +#ifndef configUSE_PREEMPTION + #error Missing definition: configUSE_PREEMPTION must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_IDLE_HOOK + #error Missing definition: configUSE_IDLE_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#if ( configNUMBER_OF_CORES > 1 ) + #ifndef configUSE_PASSIVE_IDLE_HOOK + #error Missing definition: configUSE_PASSIVE_IDLE_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. + #endif +#endif + +#ifndef configUSE_TICK_HOOK + #error Missing definition: configUSE_TICK_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#if ( ( configTICK_TYPE_WIDTH_IN_BITS != TICK_TYPE_WIDTH_16_BITS ) && \ + ( configTICK_TYPE_WIDTH_IN_BITS != TICK_TYPE_WIDTH_32_BITS ) && \ + ( configTICK_TYPE_WIDTH_IN_BITS != TICK_TYPE_WIDTH_64_BITS ) ) + #error Macro configTICK_TYPE_WIDTH_IN_BITS is defined to incorrect value. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_CO_ROUTINES + #define configUSE_CO_ROUTINES 0 +#endif + +#ifndef INCLUDE_vTaskPrioritySet + #define INCLUDE_vTaskPrioritySet 0 +#endif + +#ifndef INCLUDE_uxTaskPriorityGet + #define INCLUDE_uxTaskPriorityGet 0 +#endif + +#ifndef INCLUDE_vTaskDelete + #define INCLUDE_vTaskDelete 0 +#endif + +#ifndef INCLUDE_vTaskSuspend + #define INCLUDE_vTaskSuspend 0 +#endif + +#ifdef INCLUDE_xTaskDelayUntil + #ifdef INCLUDE_vTaskDelayUntil + +/* INCLUDE_vTaskDelayUntil was replaced by INCLUDE_xTaskDelayUntil. Backward + * compatibility is maintained if only one or the other is defined, but + * there is a conflict if both are defined. */ + #error INCLUDE_vTaskDelayUntil and INCLUDE_xTaskDelayUntil are both defined. INCLUDE_vTaskDelayUntil is no longer required and should be removed + #endif +#endif + +#ifndef INCLUDE_xTaskDelayUntil + #ifdef INCLUDE_vTaskDelayUntil + +/* If INCLUDE_vTaskDelayUntil is set but INCLUDE_xTaskDelayUntil is not then + * the project's FreeRTOSConfig.h probably pre-dates the introduction of + * xTaskDelayUntil and setting INCLUDE_xTaskDelayUntil to whatever + * INCLUDE_vTaskDelayUntil is set to will ensure backward compatibility. + */ + #define INCLUDE_xTaskDelayUntil INCLUDE_vTaskDelayUntil + #endif +#endif + +#ifndef INCLUDE_xTaskDelayUntil + #define INCLUDE_xTaskDelayUntil 0 +#endif + +#ifndef INCLUDE_vTaskDelay + #define INCLUDE_vTaskDelay 0 +#endif + +#ifndef INCLUDE_xTaskGetIdleTaskHandle + #define INCLUDE_xTaskGetIdleTaskHandle 0 +#endif + +#ifndef INCLUDE_xTaskAbortDelay + #define INCLUDE_xTaskAbortDelay 0 +#endif + +#ifndef INCLUDE_xQueueGetMutexHolder + #define INCLUDE_xQueueGetMutexHolder 0 +#endif + +#ifndef INCLUDE_xSemaphoreGetMutexHolder + #define INCLUDE_xSemaphoreGetMutexHolder INCLUDE_xQueueGetMutexHolder +#endif + +#ifndef INCLUDE_xTaskGetHandle + #define INCLUDE_xTaskGetHandle 0 +#endif + +#ifndef INCLUDE_uxTaskGetStackHighWaterMark + #define INCLUDE_uxTaskGetStackHighWaterMark 0 +#endif + +#ifndef INCLUDE_uxTaskGetStackHighWaterMark2 + #define INCLUDE_uxTaskGetStackHighWaterMark2 0 +#endif + +#ifndef INCLUDE_eTaskGetState + #define INCLUDE_eTaskGetState 0 +#endif + +#ifndef INCLUDE_xTaskResumeFromISR + #define INCLUDE_xTaskResumeFromISR 1 +#endif + +#ifndef INCLUDE_xTimerPendFunctionCall + #define INCLUDE_xTimerPendFunctionCall 0 +#endif + +#ifndef INCLUDE_xTaskGetSchedulerState + #define INCLUDE_xTaskGetSchedulerState 0 +#endif + +#ifndef INCLUDE_xTaskGetCurrentTaskHandle + #define INCLUDE_xTaskGetCurrentTaskHandle 1 +#endif + +#if configUSE_CO_ROUTINES != 0 + #ifndef configMAX_CO_ROUTINE_PRIORITIES + #error configMAX_CO_ROUTINE_PRIORITIES must be greater than or equal to 1. + #endif +#endif + +#ifndef configUSE_APPLICATION_TASK_TAG + #define configUSE_APPLICATION_TASK_TAG 0 +#endif + +#ifndef configNUM_THREAD_LOCAL_STORAGE_POINTERS + #define configNUM_THREAD_LOCAL_STORAGE_POINTERS 0 +#endif + +#ifndef configUSE_RECURSIVE_MUTEXES + #define configUSE_RECURSIVE_MUTEXES 0 +#endif + +#ifndef configUSE_MUTEXES + #define configUSE_MUTEXES 0 +#endif + +#ifndef configUSE_TIMERS + #define configUSE_TIMERS 0 +#endif + +#ifndef configUSE_EVENT_GROUPS + #define configUSE_EVENT_GROUPS 1 +#endif + +#ifndef configUSE_STREAM_BUFFERS + #define configUSE_STREAM_BUFFERS 1 +#endif + +#ifndef configUSE_DAEMON_TASK_STARTUP_HOOK + #define configUSE_DAEMON_TASK_STARTUP_HOOK 0 +#endif + +#if ( configUSE_DAEMON_TASK_STARTUP_HOOK != 0 ) + #if ( configUSE_TIMERS == 0 ) + #error configUSE_DAEMON_TASK_STARTUP_HOOK is set, but the daemon task is not created because configUSE_TIMERS is 0. + #endif +#endif + +#ifndef configUSE_COUNTING_SEMAPHORES + #define configUSE_COUNTING_SEMAPHORES 0 +#endif + +#ifndef configUSE_TASK_PREEMPTION_DISABLE + #define configUSE_TASK_PREEMPTION_DISABLE 0 +#endif + +#ifndef configUSE_ALTERNATIVE_API + #define configUSE_ALTERNATIVE_API 0 +#endif + +#ifndef portCRITICAL_NESTING_IN_TCB + #define portCRITICAL_NESTING_IN_TCB 0 +#endif + +#ifndef configMAX_TASK_NAME_LEN + #define configMAX_TASK_NAME_LEN 16 +#endif + +#ifndef configIDLE_SHOULD_YIELD + #define configIDLE_SHOULD_YIELD 1 +#endif + +#if configMAX_TASK_NAME_LEN < 1 + #error configMAX_TASK_NAME_LEN must be set to a minimum of 1 in FreeRTOSConfig.h +#endif + +/* configPRECONDITION should be defined as configASSERT. + * The CBMC proofs need a way to track assumptions and assertions. + * A configPRECONDITION statement should express an implicit invariant or + * assumption made. A configASSERT statement should express an invariant that must + * hold explicit before calling the code. */ +#ifndef configPRECONDITION + #define configPRECONDITION( X ) configASSERT( X ) + #define configPRECONDITION_DEFINED 0 +#else + #define configPRECONDITION_DEFINED 1 +#endif + +#ifndef configCHECK_HANDLER_INSTALLATION + #define configCHECK_HANDLER_INSTALLATION 1 +#else + +/* The application has explicitly defined configCHECK_HANDLER_INSTALLATION + * to 1. The checks requires configASSERT() to be defined. */ + #if ( ( configCHECK_HANDLER_INSTALLATION == 1 ) && ( configASSERT_DEFINED == 0 ) ) + #error You must define configASSERT() when configCHECK_HANDLER_INSTALLATION is 1. + #endif +#endif + +#ifndef portMEMORY_BARRIER + #define portMEMORY_BARRIER() +#endif + +#ifndef portSOFTWARE_BARRIER + #define portSOFTWARE_BARRIER() +#endif + +#ifndef configRUN_MULTIPLE_PRIORITIES + #define configRUN_MULTIPLE_PRIORITIES 0 +#endif + +#ifndef portGET_CORE_ID + + #if ( configNUMBER_OF_CORES == 1 ) + #define portGET_CORE_ID() 0 + #else + #error configNUMBER_OF_CORES is set to more than 1 then portGET_CORE_ID must also be defined. + #endif /* configNUMBER_OF_CORES */ + +#endif /* portGET_CORE_ID */ + +#ifndef portYIELD_CORE + + #if ( configNUMBER_OF_CORES == 1 ) + #define portYIELD_CORE( x ) portYIELD() + #else + #error configNUMBER_OF_CORES is set to more than 1 then portYIELD_CORE must also be defined. + #endif /* configNUMBER_OF_CORES */ + +#endif /* portYIELD_CORE */ + +#ifndef portSET_INTERRUPT_MASK + + #if ( configNUMBER_OF_CORES > 1 ) + #error portSET_INTERRUPT_MASK is required in SMP + #endif + +#endif /* portSET_INTERRUPT_MASK */ + +#ifndef portCLEAR_INTERRUPT_MASK + + #if ( configNUMBER_OF_CORES > 1 ) + #error portCLEAR_INTERRUPT_MASK is required in SMP + #endif + +#endif /* portCLEAR_INTERRUPT_MASK */ + +#ifndef portRELEASE_TASK_LOCK + + #if ( configNUMBER_OF_CORES == 1 ) + #define portRELEASE_TASK_LOCK( xCoreID ) + #else + #error portRELEASE_TASK_LOCK is required in SMP + #endif + +#endif /* portRELEASE_TASK_LOCK */ + +#ifndef portGET_TASK_LOCK + + #if ( configNUMBER_OF_CORES == 1 ) + #define portGET_TASK_LOCK( xCoreID ) + #else + #error portGET_TASK_LOCK is required in SMP + #endif + +#endif /* portGET_TASK_LOCK */ + +#ifndef portRELEASE_ISR_LOCK + + #if ( configNUMBER_OF_CORES == 1 ) + #define portRELEASE_ISR_LOCK( xCoreID ) + #else + #error portRELEASE_ISR_LOCK is required in SMP + #endif + +#endif /* portRELEASE_ISR_LOCK */ + +#ifndef portGET_ISR_LOCK + + #if ( configNUMBER_OF_CORES == 1 ) + #define portGET_ISR_LOCK( xCoreID ) + #else + #error portGET_ISR_LOCK is required in SMP + #endif + +#endif /* portGET_ISR_LOCK */ + +#ifndef portENTER_CRITICAL_FROM_ISR + + #if ( configNUMBER_OF_CORES > 1 ) + #error portENTER_CRITICAL_FROM_ISR is required in SMP + #endif + +#endif + +#ifndef portEXIT_CRITICAL_FROM_ISR + + #if ( configNUMBER_OF_CORES > 1 ) + #error portEXIT_CRITICAL_FROM_ISR is required in SMP + #endif + +#endif + +#ifndef configUSE_CORE_AFFINITY + #define configUSE_CORE_AFFINITY 0 +#endif /* configUSE_CORE_AFFINITY */ + +#if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) + #ifndef configTASK_DEFAULT_CORE_AFFINITY + #define configTASK_DEFAULT_CORE_AFFINITY tskNO_AFFINITY + #endif +#endif + +#ifndef configUSE_PASSIVE_IDLE_HOOK + #define configUSE_PASSIVE_IDLE_HOOK 0 +#endif /* configUSE_PASSIVE_IDLE_HOOK */ + +/* The timers module relies on xTaskGetSchedulerState(). */ +#if configUSE_TIMERS == 1 + + #ifndef configTIMER_TASK_PRIORITY + #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_PRIORITY must also be defined. + #endif /* configTIMER_TASK_PRIORITY */ + + #ifndef configTIMER_QUEUE_LENGTH + #error If configUSE_TIMERS is set to 1 then configTIMER_QUEUE_LENGTH must also be defined. + #endif /* configTIMER_QUEUE_LENGTH */ + + #ifndef configTIMER_TASK_STACK_DEPTH + #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_STACK_DEPTH must also be defined. + #endif /* configTIMER_TASK_STACK_DEPTH */ + + #ifndef portTIMER_CALLBACK_ATTRIBUTE + #define portTIMER_CALLBACK_ATTRIBUTE + #endif /* portTIMER_CALLBACK_ATTRIBUTE */ + +#endif /* configUSE_TIMERS */ + +#ifndef portHAS_NESTED_INTERRUPTS + #if defined( portSET_INTERRUPT_MASK_FROM_ISR ) && defined( portCLEAR_INTERRUPT_MASK_FROM_ISR ) + #define portHAS_NESTED_INTERRUPTS 1 + #else + #define portHAS_NESTED_INTERRUPTS 0 + #endif +#endif + +#ifndef portSET_INTERRUPT_MASK_FROM_ISR + #if ( portHAS_NESTED_INTERRUPTS == 1 ) + #error portSET_INTERRUPT_MASK_FROM_ISR must be defined for ports that support nested interrupts (i.e. portHAS_NESTED_INTERRUPTS is set to 1) + #else + #define portSET_INTERRUPT_MASK_FROM_ISR() 0 + #endif +#else + #if ( portHAS_NESTED_INTERRUPTS == 0 ) + #error portSET_INTERRUPT_MASK_FROM_ISR must not be defined for ports that do not support nested interrupts (i.e. portHAS_NESTED_INTERRUPTS is set to 0) + #endif +#endif + +#ifndef portCLEAR_INTERRUPT_MASK_FROM_ISR + #if ( portHAS_NESTED_INTERRUPTS == 1 ) + #error portCLEAR_INTERRUPT_MASK_FROM_ISR must be defined for ports that support nested interrupts (i.e. portHAS_NESTED_INTERRUPTS is set to 1) + #else + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) ( uxSavedStatusValue ) + #endif +#else + #if ( portHAS_NESTED_INTERRUPTS == 0 ) + #error portCLEAR_INTERRUPT_MASK_FROM_ISR must not be defined for ports that do not support nested interrupts (i.e. portHAS_NESTED_INTERRUPTS is set to 0) + #endif +#endif + +#ifndef portCLEAN_UP_TCB + #define portCLEAN_UP_TCB( pxTCB ) ( void ) ( pxTCB ) +#endif + +#ifndef portPRE_TASK_DELETE_HOOK + #define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxYieldPending ) +#endif + +#ifndef portSETUP_TCB + #define portSETUP_TCB( pxTCB ) ( void ) ( pxTCB ) +#endif + +#ifndef portTASK_SWITCH_HOOK + #define portTASK_SWITCH_HOOK( pxTCB ) ( void ) ( pxTCB ) +#endif + +#ifndef configQUEUE_REGISTRY_SIZE + #define configQUEUE_REGISTRY_SIZE 0U +#endif + +#if ( configQUEUE_REGISTRY_SIZE < 1 ) + #define vQueueAddToRegistry( xQueue, pcName ) + #define vQueueUnregisterQueue( xQueue ) + #define pcQueueGetName( xQueue ) +#endif + +#ifndef configUSE_MINI_LIST_ITEM + #define configUSE_MINI_LIST_ITEM 1 +#endif + +#ifndef portPOINTER_SIZE_TYPE + #define portPOINTER_SIZE_TYPE uint32_t +#endif + +/* Remove any unused trace macros. */ +#ifndef traceSTART + +/* Used to perform any necessary initialisation - for example, open a file + * into which trace is to be written. */ + #define traceSTART() +#endif + +#ifndef traceEND + +/* Use to close a trace, for example close a file into which trace has been + * written. */ + #define traceEND() +#endif + +#ifndef traceTASK_SWITCHED_IN + +/* Called after a task has been selected to run. pxCurrentTCB holds a pointer + * to the task control block of the selected task. */ + #define traceTASK_SWITCHED_IN() +#endif + +#ifndef traceSTARTING_SCHEDULER + +/* Called after all idle tasks and timer task (if enabled) have been created + * successfully, just before the scheduler is started. */ + #define traceSTARTING_SCHEDULER( xIdleTaskHandles ) +#endif + +#ifndef traceINCREASE_TICK_COUNT + +/* Called before stepping the tick count after waking from tickless idle + * sleep. */ + #define traceINCREASE_TICK_COUNT( x ) +#endif + +#ifndef traceLOW_POWER_IDLE_BEGIN + /* Called immediately before entering tickless idle. */ + #define traceLOW_POWER_IDLE_BEGIN() +#endif + +#ifndef traceLOW_POWER_IDLE_END + /* Called when returning to the Idle task after a tickless idle. */ + #define traceLOW_POWER_IDLE_END() +#endif + +#ifndef traceTASK_SWITCHED_OUT + +/* Called before a task has been selected to run. pxCurrentTCB holds a pointer + * to the task control block of the task being switched out. */ + #define traceTASK_SWITCHED_OUT() +#endif + +#ifndef traceTASK_PRIORITY_INHERIT + +/* Called when a task attempts to take a mutex that is already held by a + * lower priority task. pxTCBOfMutexHolder is a pointer to the TCB of the task + * that holds the mutex. uxInheritedPriority is the priority the mutex holder + * will inherit (the priority of the task that is attempting to obtain the + * muted. */ + #define traceTASK_PRIORITY_INHERIT( pxTCBOfMutexHolder, uxInheritedPriority ) +#endif + +#ifndef traceTASK_PRIORITY_DISINHERIT + +/* Called when a task releases a mutex, the holding of which had resulted in + * the task inheriting the priority of a higher priority task. + * pxTCBOfMutexHolder is a pointer to the TCB of the task that is releasing the + * mutex. uxOriginalPriority is the task's configured (base) priority. */ + #define traceTASK_PRIORITY_DISINHERIT( pxTCBOfMutexHolder, uxOriginalPriority ) +#endif + +#ifndef traceBLOCKING_ON_QUEUE_RECEIVE + +/* Task is about to block because it cannot read from a + * queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore + * upon which the read was attempted. pxCurrentTCB points to the TCB of the + * task that attempted the read. */ + #define traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ) +#endif + +#ifndef traceBLOCKING_ON_QUEUE_PEEK + +/* Task is about to block because it cannot read from a + * queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore + * upon which the read was attempted. pxCurrentTCB points to the TCB of the + * task that attempted the read. */ + #define traceBLOCKING_ON_QUEUE_PEEK( pxQueue ) +#endif + +#ifndef traceBLOCKING_ON_QUEUE_SEND + +/* Task is about to block because it cannot write to a + * queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore + * upon which the write was attempted. pxCurrentTCB points to the TCB of the + * task that attempted the write. */ + #define traceBLOCKING_ON_QUEUE_SEND( pxQueue ) +#endif + +#ifndef configCHECK_FOR_STACK_OVERFLOW + #define configCHECK_FOR_STACK_OVERFLOW 0 +#endif + +#ifndef configRECORD_STACK_HIGH_ADDRESS + #define configRECORD_STACK_HIGH_ADDRESS 0 +#endif + +#ifndef configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H + #define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 0 +#endif + +/* The following event macros are embedded in the kernel API calls. */ + +#ifndef traceMOVED_TASK_TO_READY_STATE + #define traceMOVED_TASK_TO_READY_STATE( pxTCB ) +#endif + +#ifndef tracePOST_MOVED_TASK_TO_READY_STATE + #define tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB ) +#endif + +#ifndef traceMOVED_TASK_TO_DELAYED_LIST + #define traceMOVED_TASK_TO_DELAYED_LIST() +#endif + +#ifndef traceMOVED_TASK_TO_OVERFLOW_DELAYED_LIST + #define traceMOVED_TASK_TO_OVERFLOW_DELAYED_LIST() +#endif + +#ifndef traceQUEUE_CREATE + #define traceQUEUE_CREATE( pxNewQueue ) +#endif + +#ifndef traceQUEUE_CREATE_FAILED + #define traceQUEUE_CREATE_FAILED( ucQueueType ) +#endif + +#ifndef traceCREATE_MUTEX + #define traceCREATE_MUTEX( pxNewQueue ) +#endif + +#ifndef traceCREATE_MUTEX_FAILED + #define traceCREATE_MUTEX_FAILED() +#endif + +#ifndef traceGIVE_MUTEX_RECURSIVE + #define traceGIVE_MUTEX_RECURSIVE( pxMutex ) +#endif + +#ifndef traceGIVE_MUTEX_RECURSIVE_FAILED + #define traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex ) +#endif + +#ifndef traceTAKE_MUTEX_RECURSIVE + #define traceTAKE_MUTEX_RECURSIVE( pxMutex ) +#endif + +#ifndef traceTAKE_MUTEX_RECURSIVE_FAILED + #define traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex ) +#endif + +#ifndef traceCREATE_COUNTING_SEMAPHORE + #define traceCREATE_COUNTING_SEMAPHORE() +#endif + +#ifndef traceCREATE_COUNTING_SEMAPHORE_FAILED + #define traceCREATE_COUNTING_SEMAPHORE_FAILED() +#endif + +#ifndef traceQUEUE_SET_SEND + #define traceQUEUE_SET_SEND traceQUEUE_SEND +#endif + +#ifndef traceQUEUE_SEND + #define traceQUEUE_SEND( pxQueue ) +#endif + +#ifndef traceQUEUE_SEND_FAILED + #define traceQUEUE_SEND_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE + #define traceQUEUE_RECEIVE( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK + #define traceQUEUE_PEEK( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK_FAILED + #define traceQUEUE_PEEK_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK_FROM_ISR + #define traceQUEUE_PEEK_FROM_ISR( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE_FAILED + #define traceQUEUE_RECEIVE_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_SEND_FROM_ISR + #define traceQUEUE_SEND_FROM_ISR( pxQueue ) +#endif + +#ifndef traceQUEUE_SEND_FROM_ISR_FAILED + #define traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE_FROM_ISR + #define traceQUEUE_RECEIVE_FROM_ISR( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE_FROM_ISR_FAILED + #define traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK_FROM_ISR_FAILED + #define traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_DELETE + #define traceQUEUE_DELETE( pxQueue ) +#endif + +#ifndef traceTASK_CREATE + #define traceTASK_CREATE( pxNewTCB ) +#endif + +#ifndef traceTASK_CREATE_FAILED + #define traceTASK_CREATE_FAILED() +#endif + +#ifndef traceTASK_DELETE + #define traceTASK_DELETE( pxTaskToDelete ) +#endif + +#ifndef traceTASK_DELAY_UNTIL + #define traceTASK_DELAY_UNTIL( x ) +#endif + +#ifndef traceTASK_DELAY + #define traceTASK_DELAY() +#endif + +#ifndef traceTASK_PRIORITY_SET + #define traceTASK_PRIORITY_SET( pxTask, uxNewPriority ) +#endif + +#ifndef traceTASK_SUSPEND + #define traceTASK_SUSPEND( pxTaskToSuspend ) +#endif + +#ifndef traceTASK_RESUME + #define traceTASK_RESUME( pxTaskToResume ) +#endif + +#ifndef traceTASK_RESUME_FROM_ISR + #define traceTASK_RESUME_FROM_ISR( pxTaskToResume ) +#endif + +#ifndef traceTASK_INCREMENT_TICK + #define traceTASK_INCREMENT_TICK( xTickCount ) +#endif + +#ifndef traceTIMER_CREATE + #define traceTIMER_CREATE( pxNewTimer ) +#endif + +#ifndef traceTIMER_CREATE_FAILED + #define traceTIMER_CREATE_FAILED() +#endif + +#ifndef traceTIMER_COMMAND_SEND + #define traceTIMER_COMMAND_SEND( xTimer, xMessageID, xMessageValueValue, xReturn ) +#endif + +#ifndef traceTIMER_EXPIRED + #define traceTIMER_EXPIRED( pxTimer ) +#endif + +#ifndef traceTIMER_COMMAND_RECEIVED + #define traceTIMER_COMMAND_RECEIVED( pxTimer, xMessageID, xMessageValue ) +#endif + +#ifndef traceMALLOC + #define traceMALLOC( pvAddress, uiSize ) +#endif + +#ifndef traceFREE + #define traceFREE( pvAddress, uiSize ) +#endif + +#ifndef traceEVENT_GROUP_CREATE + #define traceEVENT_GROUP_CREATE( xEventGroup ) +#endif + +#ifndef traceEVENT_GROUP_CREATE_FAILED + #define traceEVENT_GROUP_CREATE_FAILED() +#endif + +#ifndef traceEVENT_GROUP_SYNC_BLOCK + #define traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor ) +#endif + +#ifndef traceEVENT_GROUP_SYNC_END + #define traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) ( xTimeoutOccurred ) +#endif + +#ifndef traceEVENT_GROUP_WAIT_BITS_BLOCK + #define traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor ) +#endif + +#ifndef traceEVENT_GROUP_WAIT_BITS_END + #define traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) ( xTimeoutOccurred ) +#endif + +#ifndef traceEVENT_GROUP_CLEAR_BITS + #define traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear ) +#endif + +#ifndef traceEVENT_GROUP_CLEAR_BITS_FROM_ISR + #define traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear ) +#endif + +#ifndef traceEVENT_GROUP_SET_BITS + #define traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet ) +#endif + +#ifndef traceEVENT_GROUP_SET_BITS_FROM_ISR + #define traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet ) +#endif + +#ifndef traceEVENT_GROUP_DELETE + #define traceEVENT_GROUP_DELETE( xEventGroup ) +#endif + +#ifndef tracePEND_FUNC_CALL + #define tracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, ret ) +#endif + +#ifndef tracePEND_FUNC_CALL_FROM_ISR + #define tracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, ret ) +#endif + +#ifndef traceQUEUE_REGISTRY_ADD + #define traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName ) +#endif + +#ifndef traceTASK_NOTIFY_TAKE_BLOCK + #define traceTASK_NOTIFY_TAKE_BLOCK( uxIndexToWait ) +#endif + +#ifndef traceTASK_NOTIFY_TAKE + #define traceTASK_NOTIFY_TAKE( uxIndexToWait ) +#endif + +#ifndef traceTASK_NOTIFY_WAIT_BLOCK + #define traceTASK_NOTIFY_WAIT_BLOCK( uxIndexToWait ) +#endif + +#ifndef traceTASK_NOTIFY_WAIT + #define traceTASK_NOTIFY_WAIT( uxIndexToWait ) +#endif + +#ifndef traceTASK_NOTIFY + #define traceTASK_NOTIFY( uxIndexToNotify ) +#endif + +#ifndef traceTASK_NOTIFY_FROM_ISR + #define traceTASK_NOTIFY_FROM_ISR( uxIndexToNotify ) +#endif + +#ifndef traceTASK_NOTIFY_GIVE_FROM_ISR + #define traceTASK_NOTIFY_GIVE_FROM_ISR( uxIndexToNotify ) +#endif + +#ifndef traceISR_EXIT_TO_SCHEDULER + #define traceISR_EXIT_TO_SCHEDULER() +#endif + +#ifndef traceISR_EXIT + #define traceISR_EXIT() +#endif + +#ifndef traceISR_ENTER + #define traceISR_ENTER() +#endif + +#ifndef traceSTREAM_BUFFER_CREATE_FAILED + #define traceSTREAM_BUFFER_CREATE_FAILED( xStreamBufferType ) +#endif + +#ifndef traceSTREAM_BUFFER_CREATE_STATIC_FAILED + #define traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xStreamBufferType ) +#endif + +#ifndef traceSTREAM_BUFFER_CREATE + #define traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xStreamBufferType ) +#endif + +#ifndef traceSTREAM_BUFFER_DELETE + #define traceSTREAM_BUFFER_DELETE( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_RESET + #define traceSTREAM_BUFFER_RESET( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_RESET_FROM_ISR + #define traceSTREAM_BUFFER_RESET_FROM_ISR( xStreamBuffer ) +#endif + +#ifndef traceBLOCKING_ON_STREAM_BUFFER_SEND + #define traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_SEND + #define traceSTREAM_BUFFER_SEND( xStreamBuffer, xBytesSent ) +#endif + +#ifndef traceSTREAM_BUFFER_SEND_FAILED + #define traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_SEND_FROM_ISR + #define traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xBytesSent ) +#endif + +#ifndef traceBLOCKING_ON_STREAM_BUFFER_RECEIVE + #define traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_RECEIVE + #define traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength ) +#endif + +#ifndef traceSTREAM_BUFFER_RECEIVE_FAILED + #define traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_RECEIVE_FROM_ISR + #define traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength ) +#endif + +#ifndef traceENTER_xEventGroupCreateStatic + #define traceENTER_xEventGroupCreateStatic( pxEventGroupBuffer ) +#endif + +#ifndef traceRETURN_xEventGroupCreateStatic + #define traceRETURN_xEventGroupCreateStatic( pxEventBits ) +#endif + +#ifndef traceENTER_xEventGroupCreate + #define traceENTER_xEventGroupCreate() +#endif + +#ifndef traceRETURN_xEventGroupCreate + #define traceRETURN_xEventGroupCreate( pxEventBits ) +#endif + +#ifndef traceENTER_xEventGroupSync + #define traceENTER_xEventGroupSync( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTicksToWait ) +#endif + +#ifndef traceRETURN_xEventGroupSync + #define traceRETURN_xEventGroupSync( uxReturn ) +#endif + +#ifndef traceENTER_xEventGroupWaitBits + #define traceENTER_xEventGroupWaitBits( xEventGroup, uxBitsToWaitFor, xClearOnExit, xWaitForAllBits, xTicksToWait ) +#endif + +#ifndef traceRETURN_xEventGroupWaitBits + #define traceRETURN_xEventGroupWaitBits( uxReturn ) +#endif + +#ifndef traceENTER_xEventGroupClearBits + #define traceENTER_xEventGroupClearBits( xEventGroup, uxBitsToClear ) +#endif + +#ifndef traceRETURN_xEventGroupClearBits + #define traceRETURN_xEventGroupClearBits( uxReturn ) +#endif + +#ifndef traceENTER_xEventGroupClearBitsFromISR + #define traceENTER_xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear ) +#endif + +#ifndef traceRETURN_xEventGroupClearBitsFromISR + #define traceRETURN_xEventGroupClearBitsFromISR( xReturn ) +#endif + +#ifndef traceENTER_xEventGroupGetBitsFromISR + #define traceENTER_xEventGroupGetBitsFromISR( xEventGroup ) +#endif + +#ifndef traceRETURN_xEventGroupGetBitsFromISR + #define traceRETURN_xEventGroupGetBitsFromISR( uxReturn ) +#endif + +#ifndef traceENTER_xEventGroupSetBits + #define traceENTER_xEventGroupSetBits( xEventGroup, uxBitsToSet ) +#endif + +#ifndef traceRETURN_xEventGroupSetBits + #define traceRETURN_xEventGroupSetBits( uxEventBits ) +#endif + +#ifndef traceENTER_vEventGroupDelete + #define traceENTER_vEventGroupDelete( xEventGroup ) +#endif + +#ifndef traceRETURN_vEventGroupDelete + #define traceRETURN_vEventGroupDelete() +#endif + +#ifndef traceENTER_xEventGroupGetStaticBuffer + #define traceENTER_xEventGroupGetStaticBuffer( xEventGroup, ppxEventGroupBuffer ) +#endif + +#ifndef traceRETURN_xEventGroupGetStaticBuffer + #define traceRETURN_xEventGroupGetStaticBuffer( xReturn ) +#endif + +#ifndef traceENTER_vEventGroupSetBitsCallback + #define traceENTER_vEventGroupSetBitsCallback( pvEventGroup, ulBitsToSet ) +#endif + +#ifndef traceRETURN_vEventGroupSetBitsCallback + #define traceRETURN_vEventGroupSetBitsCallback() +#endif + +#ifndef traceENTER_vEventGroupClearBitsCallback + #define traceENTER_vEventGroupClearBitsCallback( pvEventGroup, ulBitsToClear ) +#endif + +#ifndef traceRETURN_vEventGroupClearBitsCallback + #define traceRETURN_vEventGroupClearBitsCallback() +#endif + +#ifndef traceENTER_xEventGroupSetBitsFromISR + #define traceENTER_xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken ) +#endif + +#ifndef traceRETURN_xEventGroupSetBitsFromISR + #define traceRETURN_xEventGroupSetBitsFromISR( xReturn ) +#endif + +#ifndef traceENTER_uxEventGroupGetNumber + #define traceENTER_uxEventGroupGetNumber( xEventGroup ) +#endif + +#ifndef traceRETURN_uxEventGroupGetNumber + #define traceRETURN_uxEventGroupGetNumber( xReturn ) +#endif + +#ifndef traceENTER_vEventGroupSetNumber + #define traceENTER_vEventGroupSetNumber( xEventGroup, uxEventGroupNumber ) +#endif + +#ifndef traceRETURN_vEventGroupSetNumber + #define traceRETURN_vEventGroupSetNumber() +#endif + +#ifndef traceENTER_xQueueGenericReset + #define traceENTER_xQueueGenericReset( xQueue, xNewQueue ) +#endif + +#ifndef traceRETURN_xQueueGenericReset + #define traceRETURN_xQueueGenericReset( xReturn ) +#endif + +#ifndef traceENTER_xQueueGenericCreateStatic + #define traceENTER_xQueueGenericCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxStaticQueue, ucQueueType ) +#endif + +#ifndef traceRETURN_xQueueGenericCreateStatic + #define traceRETURN_xQueueGenericCreateStatic( pxNewQueue ) +#endif + +#ifndef traceENTER_xQueueGenericGetStaticBuffers + #define traceENTER_xQueueGenericGetStaticBuffers( xQueue, ppucQueueStorage, ppxStaticQueue ) +#endif + +#ifndef traceRETURN_xQueueGenericGetStaticBuffers + #define traceRETURN_xQueueGenericGetStaticBuffers( xReturn ) +#endif + +#ifndef traceENTER_xQueueGenericCreate + #define traceENTER_xQueueGenericCreate( uxQueueLength, uxItemSize, ucQueueType ) +#endif + +#ifndef traceRETURN_xQueueGenericCreate + #define traceRETURN_xQueueGenericCreate( pxNewQueue ) +#endif + +#ifndef traceENTER_xQueueCreateMutex + #define traceENTER_xQueueCreateMutex( ucQueueType ) +#endif + +#ifndef traceRETURN_xQueueCreateMutex + #define traceRETURN_xQueueCreateMutex( xNewQueue ) +#endif + +#ifndef traceENTER_xQueueCreateMutexStatic + #define traceENTER_xQueueCreateMutexStatic( ucQueueType, pxStaticQueue ) +#endif + +#ifndef traceRETURN_xQueueCreateMutexStatic + #define traceRETURN_xQueueCreateMutexStatic( xNewQueue ) +#endif + +#ifndef traceENTER_xQueueGetMutexHolder + #define traceENTER_xQueueGetMutexHolder( xSemaphore ) +#endif + +#ifndef traceRETURN_xQueueGetMutexHolder + #define traceRETURN_xQueueGetMutexHolder( pxReturn ) +#endif + +#ifndef traceENTER_xQueueGetMutexHolderFromISR + #define traceENTER_xQueueGetMutexHolderFromISR( xSemaphore ) +#endif + +#ifndef traceRETURN_xQueueGetMutexHolderFromISR + #define traceRETURN_xQueueGetMutexHolderFromISR( pxReturn ) +#endif + +#ifndef traceENTER_xQueueGiveMutexRecursive + #define traceENTER_xQueueGiveMutexRecursive( xMutex ) +#endif + +#ifndef traceRETURN_xQueueGiveMutexRecursive + #define traceRETURN_xQueueGiveMutexRecursive( xReturn ) +#endif + +#ifndef traceENTER_xQueueTakeMutexRecursive + #define traceENTER_xQueueTakeMutexRecursive( xMutex, xTicksToWait ) +#endif + +#ifndef traceRETURN_xQueueTakeMutexRecursive + #define traceRETURN_xQueueTakeMutexRecursive( xReturn ) +#endif + +#ifndef traceENTER_xQueueCreateCountingSemaphoreStatic + #define traceENTER_xQueueCreateCountingSemaphoreStatic( uxMaxCount, uxInitialCount, pxStaticQueue ) +#endif + +#ifndef traceRETURN_xQueueCreateCountingSemaphoreStatic + #define traceRETURN_xQueueCreateCountingSemaphoreStatic( xHandle ) +#endif + +#ifndef traceENTER_xQueueCreateCountingSemaphore + #define traceENTER_xQueueCreateCountingSemaphore( uxMaxCount, uxInitialCount ) +#endif + +#ifndef traceRETURN_xQueueCreateCountingSemaphore + #define traceRETURN_xQueueCreateCountingSemaphore( xHandle ) +#endif + +#ifndef traceENTER_xQueueGenericSend + #define traceENTER_xQueueGenericSend( xQueue, pvItemToQueue, xTicksToWait, xCopyPosition ) +#endif + +#ifndef traceRETURN_xQueueGenericSend + #define traceRETURN_xQueueGenericSend( xReturn ) +#endif + +#ifndef traceENTER_xQueueGenericSendFromISR + #define traceENTER_xQueueGenericSendFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken, xCopyPosition ) +#endif + +#ifndef traceRETURN_xQueueGenericSendFromISR + #define traceRETURN_xQueueGenericSendFromISR( xReturn ) +#endif + +#ifndef traceENTER_xQueueGiveFromISR + #define traceENTER_xQueueGiveFromISR( xQueue, pxHigherPriorityTaskWoken ) +#endif + +#ifndef traceRETURN_xQueueGiveFromISR + #define traceRETURN_xQueueGiveFromISR( xReturn ) +#endif + +#ifndef traceENTER_xQueueReceive + #define traceENTER_xQueueReceive( xQueue, pvBuffer, xTicksToWait ) +#endif + +#ifndef traceRETURN_xQueueReceive + #define traceRETURN_xQueueReceive( xReturn ) +#endif + +#ifndef traceENTER_xQueueSemaphoreTake + #define traceENTER_xQueueSemaphoreTake( xQueue, xTicksToWait ) +#endif + +#ifndef traceRETURN_xQueueSemaphoreTake + #define traceRETURN_xQueueSemaphoreTake( xReturn ) +#endif + +#ifndef traceENTER_xQueuePeek + #define traceENTER_xQueuePeek( xQueue, pvBuffer, xTicksToWait ) +#endif + +#ifndef traceRETURN_xQueuePeek + #define traceRETURN_xQueuePeek( xReturn ) +#endif + +#ifndef traceENTER_xQueueReceiveFromISR + #define traceENTER_xQueueReceiveFromISR( xQueue, pvBuffer, pxHigherPriorityTaskWoken ) +#endif + +#ifndef traceRETURN_xQueueReceiveFromISR + #define traceRETURN_xQueueReceiveFromISR( xReturn ) +#endif + +#ifndef traceENTER_xQueuePeekFromISR + #define traceENTER_xQueuePeekFromISR( xQueue, pvBuffer ) +#endif + +#ifndef traceRETURN_xQueuePeekFromISR + #define traceRETURN_xQueuePeekFromISR( xReturn ) +#endif + +#ifndef traceENTER_uxQueueMessagesWaiting + #define traceENTER_uxQueueMessagesWaiting( xQueue ) +#endif + +#ifndef traceRETURN_uxQueueMessagesWaiting + #define traceRETURN_uxQueueMessagesWaiting( uxReturn ) +#endif + +#ifndef traceENTER_uxQueueSpacesAvailable + #define traceENTER_uxQueueSpacesAvailable( xQueue ) +#endif + +#ifndef traceRETURN_uxQueueSpacesAvailable + #define traceRETURN_uxQueueSpacesAvailable( uxReturn ) +#endif + +#ifndef traceENTER_uxQueueMessagesWaitingFromISR + #define traceENTER_uxQueueMessagesWaitingFromISR( xQueue ) +#endif + +#ifndef traceRETURN_uxQueueMessagesWaitingFromISR + #define traceRETURN_uxQueueMessagesWaitingFromISR( uxReturn ) +#endif + +#ifndef traceENTER_vQueueDelete + #define traceENTER_vQueueDelete( xQueue ) +#endif + +#ifndef traceRETURN_vQueueDelete + #define traceRETURN_vQueueDelete() +#endif + +#ifndef traceENTER_uxQueueGetQueueNumber + #define traceENTER_uxQueueGetQueueNumber( xQueue ) +#endif + +#ifndef traceRETURN_uxQueueGetQueueNumber + #define traceRETURN_uxQueueGetQueueNumber( uxQueueNumber ) +#endif + +#ifndef traceENTER_vQueueSetQueueNumber + #define traceENTER_vQueueSetQueueNumber( xQueue, uxQueueNumber ) +#endif + +#ifndef traceRETURN_vQueueSetQueueNumber + #define traceRETURN_vQueueSetQueueNumber() +#endif + +#ifndef traceENTER_ucQueueGetQueueType + #define traceENTER_ucQueueGetQueueType( xQueue ) +#endif + +#ifndef traceRETURN_ucQueueGetQueueType + #define traceRETURN_ucQueueGetQueueType( ucQueueType ) +#endif + +#ifndef traceENTER_uxQueueGetQueueItemSize + #define traceENTER_uxQueueGetQueueItemSize( xQueue ) +#endif + +#ifndef traceRETURN_uxQueueGetQueueItemSize + #define traceRETURN_uxQueueGetQueueItemSize( uxItemSize ) +#endif + +#ifndef traceENTER_uxQueueGetQueueLength + #define traceENTER_uxQueueGetQueueLength( xQueue ) +#endif + +#ifndef traceRETURN_uxQueueGetQueueLength + #define traceRETURN_uxQueueGetQueueLength( uxLength ) +#endif + +#ifndef traceENTER_xQueueIsQueueEmptyFromISR + #define traceENTER_xQueueIsQueueEmptyFromISR( xQueue ) +#endif + +#ifndef traceRETURN_xQueueIsQueueEmptyFromISR + #define traceRETURN_xQueueIsQueueEmptyFromISR( xReturn ) +#endif + +#ifndef traceENTER_xQueueIsQueueFullFromISR + #define traceENTER_xQueueIsQueueFullFromISR( xQueue ) +#endif + +#ifndef traceRETURN_xQueueIsQueueFullFromISR + #define traceRETURN_xQueueIsQueueFullFromISR( xReturn ) +#endif + +#ifndef traceENTER_xQueueCRSend + #define traceENTER_xQueueCRSend( xQueue, pvItemToQueue, xTicksToWait ) +#endif + +#ifndef traceRETURN_xQueueCRSend + #define traceRETURN_xQueueCRSend( xReturn ) +#endif + +#ifndef traceENTER_xQueueCRReceive + #define traceENTER_xQueueCRReceive( xQueue, pvBuffer, xTicksToWait ) +#endif + +#ifndef traceRETURN_xQueueCRReceive + #define traceRETURN_xQueueCRReceive( xReturn ) +#endif + +#ifndef traceENTER_xQueueCRSendFromISR + #define traceENTER_xQueueCRSendFromISR( xQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) +#endif + +#ifndef traceRETURN_xQueueCRSendFromISR + #define traceRETURN_xQueueCRSendFromISR( xCoRoutinePreviouslyWoken ) +#endif + +#ifndef traceENTER_xQueueCRReceiveFromISR + #define traceENTER_xQueueCRReceiveFromISR( xQueue, pvBuffer, pxCoRoutineWoken ) +#endif + +#ifndef traceRETURN_xQueueCRReceiveFromISR + #define traceRETURN_xQueueCRReceiveFromISR( xReturn ) +#endif + +#ifndef traceENTER_vQueueAddToRegistry + #define traceENTER_vQueueAddToRegistry( xQueue, pcQueueName ) +#endif + +#ifndef traceRETURN_vQueueAddToRegistry + #define traceRETURN_vQueueAddToRegistry() +#endif + +#ifndef traceENTER_pcQueueGetName + #define traceENTER_pcQueueGetName( xQueue ) +#endif + +#ifndef traceRETURN_pcQueueGetName + #define traceRETURN_pcQueueGetName( pcReturn ) +#endif + +#ifndef traceENTER_vQueueUnregisterQueue + #define traceENTER_vQueueUnregisterQueue( xQueue ) +#endif + +#ifndef traceRETURN_vQueueUnregisterQueue + #define traceRETURN_vQueueUnregisterQueue() +#endif + +#ifndef traceENTER_vQueueWaitForMessageRestricted + #define traceENTER_vQueueWaitForMessageRestricted( xQueue, xTicksToWait, xWaitIndefinitely ) +#endif + +#ifndef traceRETURN_vQueueWaitForMessageRestricted + #define traceRETURN_vQueueWaitForMessageRestricted() +#endif + +#ifndef traceENTER_xQueueCreateSet + #define traceENTER_xQueueCreateSet( uxEventQueueLength ) +#endif + +#ifndef traceRETURN_xQueueCreateSet + #define traceRETURN_xQueueCreateSet( pxQueue ) +#endif + +#ifndef traceENTER_xQueueCreateSetStatic + #define traceENTER_xQueueCreateSetStatic( uxEventQueueLength ) +#endif + +#ifndef traceRETURN_xQueueCreateSetStatic + #define traceRETURN_xQueueCreateSetStatic( pxQueue ) +#endif + +#ifndef traceENTER_xQueueAddToSet + #define traceENTER_xQueueAddToSet( xQueueOrSemaphore, xQueueSet ) +#endif + +#ifndef traceRETURN_xQueueAddToSet + #define traceRETURN_xQueueAddToSet( xReturn ) +#endif + +#ifndef traceENTER_xQueueRemoveFromSet + #define traceENTER_xQueueRemoveFromSet( xQueueOrSemaphore, xQueueSet ) +#endif + +#ifndef traceRETURN_xQueueRemoveFromSet + #define traceRETURN_xQueueRemoveFromSet( xReturn ) +#endif + +#ifndef traceENTER_xQueueSelectFromSet + #define traceENTER_xQueueSelectFromSet( xQueueSet, xTicksToWait ) +#endif + +#ifndef traceRETURN_xQueueSelectFromSet + #define traceRETURN_xQueueSelectFromSet( xReturn ) +#endif + +#ifndef traceENTER_xQueueSelectFromSetFromISR + #define traceENTER_xQueueSelectFromSetFromISR( xQueueSet ) +#endif + +#ifndef traceRETURN_xQueueSelectFromSetFromISR + #define traceRETURN_xQueueSelectFromSetFromISR( xReturn ) +#endif + +#ifndef traceENTER_xTimerCreateTimerTask + #define traceENTER_xTimerCreateTimerTask() +#endif + +#ifndef traceRETURN_xTimerCreateTimerTask + #define traceRETURN_xTimerCreateTimerTask( xReturn ) +#endif + +#ifndef traceENTER_xTimerCreate + #define traceENTER_xTimerCreate( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, pxCallbackFunction ) +#endif + +#ifndef traceRETURN_xTimerCreate + #define traceRETURN_xTimerCreate( pxNewTimer ) +#endif + +#ifndef traceENTER_xTimerCreateStatic + #define traceENTER_xTimerCreateStatic( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, pxCallbackFunction, pxTimerBuffer ) +#endif + +#ifndef traceRETURN_xTimerCreateStatic + #define traceRETURN_xTimerCreateStatic( pxNewTimer ) +#endif + +#ifndef traceENTER_xTimerGenericCommandFromTask + #define traceENTER_xTimerGenericCommandFromTask( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait ) +#endif + +#ifndef traceRETURN_xTimerGenericCommandFromTask + #define traceRETURN_xTimerGenericCommandFromTask( xReturn ) +#endif + +#ifndef traceENTER_xTimerGenericCommandFromISR + #define traceENTER_xTimerGenericCommandFromISR( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait ) +#endif + +#ifndef traceRETURN_xTimerGenericCommandFromISR + #define traceRETURN_xTimerGenericCommandFromISR( xReturn ) +#endif + +#ifndef traceENTER_xTimerGetTimerDaemonTaskHandle + #define traceENTER_xTimerGetTimerDaemonTaskHandle() +#endif + +#ifndef traceRETURN_xTimerGetTimerDaemonTaskHandle + #define traceRETURN_xTimerGetTimerDaemonTaskHandle( xTimerTaskHandle ) +#endif + +#ifndef traceENTER_xTimerGetPeriod + #define traceENTER_xTimerGetPeriod( xTimer ) +#endif + +#ifndef traceRETURN_xTimerGetPeriod + #define traceRETURN_xTimerGetPeriod( xTimerPeriodInTicks ) +#endif + +#ifndef traceENTER_vTimerSetReloadMode + #define traceENTER_vTimerSetReloadMode( xTimer, xAutoReload ) +#endif + +#ifndef traceRETURN_vTimerSetReloadMode + #define traceRETURN_vTimerSetReloadMode() +#endif + +#ifndef traceENTER_xTimerGetReloadMode + #define traceENTER_xTimerGetReloadMode( xTimer ) +#endif + +#ifndef traceRETURN_xTimerGetReloadMode + #define traceRETURN_xTimerGetReloadMode( xReturn ) +#endif + +#ifndef traceENTER_uxTimerGetReloadMode + #define traceENTER_uxTimerGetReloadMode( xTimer ) +#endif + +#ifndef traceRETURN_uxTimerGetReloadMode + #define traceRETURN_uxTimerGetReloadMode( uxReturn ) +#endif + +#ifndef traceENTER_xTimerGetExpiryTime + #define traceENTER_xTimerGetExpiryTime( xTimer ) +#endif + +#ifndef traceRETURN_xTimerGetExpiryTime + #define traceRETURN_xTimerGetExpiryTime( xReturn ) +#endif + +#ifndef traceENTER_xTimerGetStaticBuffer + #define traceENTER_xTimerGetStaticBuffer( xTimer, ppxTimerBuffer ) +#endif + +#ifndef traceRETURN_xTimerGetStaticBuffer + #define traceRETURN_xTimerGetStaticBuffer( xReturn ) +#endif + +#ifndef traceENTER_pcTimerGetName + #define traceENTER_pcTimerGetName( xTimer ) +#endif + +#ifndef traceRETURN_pcTimerGetName + #define traceRETURN_pcTimerGetName( pcTimerName ) +#endif + +#ifndef traceENTER_xTimerIsTimerActive + #define traceENTER_xTimerIsTimerActive( xTimer ) +#endif + +#ifndef traceRETURN_xTimerIsTimerActive + #define traceRETURN_xTimerIsTimerActive( xReturn ) +#endif + +#ifndef traceENTER_pvTimerGetTimerID + #define traceENTER_pvTimerGetTimerID( xTimer ) +#endif + +#ifndef traceRETURN_pvTimerGetTimerID + #define traceRETURN_pvTimerGetTimerID( pvReturn ) +#endif + +#ifndef traceENTER_vTimerSetTimerID + #define traceENTER_vTimerSetTimerID( xTimer, pvNewID ) +#endif + +#ifndef traceRETURN_vTimerSetTimerID + #define traceRETURN_vTimerSetTimerID() +#endif + +#ifndef traceENTER_xTimerPendFunctionCallFromISR + #define traceENTER_xTimerPendFunctionCallFromISR( xFunctionToPend, pvParameter1, ulParameter2, pxHigherPriorityTaskWoken ) +#endif + +#ifndef traceRETURN_xTimerPendFunctionCallFromISR + #define traceRETURN_xTimerPendFunctionCallFromISR( xReturn ) +#endif + +#ifndef traceENTER_xTimerPendFunctionCall + #define traceENTER_xTimerPendFunctionCall( xFunctionToPend, pvParameter1, ulParameter2, xTicksToWait ) +#endif + +#ifndef traceRETURN_xTimerPendFunctionCall + #define traceRETURN_xTimerPendFunctionCall( xReturn ) +#endif + +#ifndef traceENTER_uxTimerGetTimerNumber + #define traceENTER_uxTimerGetTimerNumber( xTimer ) +#endif + +#ifndef traceRETURN_uxTimerGetTimerNumber + #define traceRETURN_uxTimerGetTimerNumber( uxTimerNumber ) +#endif + +#ifndef traceENTER_vTimerSetTimerNumber + #define traceENTER_vTimerSetTimerNumber( xTimer, uxTimerNumber ) +#endif + +#ifndef traceRETURN_vTimerSetTimerNumber + #define traceRETURN_vTimerSetTimerNumber() +#endif + +#ifndef traceENTER_xTaskCreateStatic + #define traceENTER_xTaskCreateStatic( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer ) +#endif + +#ifndef traceRETURN_xTaskCreateStatic + #define traceRETURN_xTaskCreateStatic( xReturn ) +#endif + +#ifndef traceENTER_xTaskCreateStaticAffinitySet + #define traceENTER_xTaskCreateStaticAffinitySet( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer, uxCoreAffinityMask ) +#endif + +#ifndef traceRETURN_xTaskCreateStaticAffinitySet + #define traceRETURN_xTaskCreateStaticAffinitySet( xReturn ) +#endif + +#ifndef traceENTER_xTaskCreateRestrictedStatic + #define traceENTER_xTaskCreateRestrictedStatic( pxTaskDefinition, pxCreatedTask ) +#endif + +#ifndef traceRETURN_xTaskCreateRestrictedStatic + #define traceRETURN_xTaskCreateRestrictedStatic( xReturn ) +#endif + +#ifndef traceENTER_xTaskCreateRestrictedStaticAffinitySet + #define traceENTER_xTaskCreateRestrictedStaticAffinitySet( pxTaskDefinition, uxCoreAffinityMask, pxCreatedTask ) +#endif + +#ifndef traceRETURN_xTaskCreateRestrictedStaticAffinitySet + #define traceRETURN_xTaskCreateRestrictedStaticAffinitySet( xReturn ) +#endif + +#ifndef traceENTER_xTaskCreateRestricted + #define traceENTER_xTaskCreateRestricted( pxTaskDefinition, pxCreatedTask ) +#endif + +#ifndef traceRETURN_xTaskCreateRestricted + #define traceRETURN_xTaskCreateRestricted( xReturn ) +#endif + +#ifndef traceENTER_xTaskCreateRestrictedAffinitySet + #define traceENTER_xTaskCreateRestrictedAffinitySet( pxTaskDefinition, uxCoreAffinityMask, pxCreatedTask ) +#endif + +#ifndef traceRETURN_xTaskCreateRestrictedAffinitySet + #define traceRETURN_xTaskCreateRestrictedAffinitySet( xReturn ) +#endif + +#ifndef traceENTER_xTaskCreate + #define traceENTER_xTaskCreate( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, pxCreatedTask ) +#endif + +#ifndef traceRETURN_xTaskCreate + #define traceRETURN_xTaskCreate( xReturn ) +#endif + +#ifndef traceENTER_xTaskCreateAffinitySet + #define traceENTER_xTaskCreateAffinitySet( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, uxCoreAffinityMask, pxCreatedTask ) +#endif + +#ifndef traceRETURN_xTaskCreateAffinitySet + #define traceRETURN_xTaskCreateAffinitySet( xReturn ) +#endif + +#ifndef traceENTER_vTaskDelete + #define traceENTER_vTaskDelete( xTaskToDelete ) +#endif + +#ifndef traceRETURN_vTaskDelete + #define traceRETURN_vTaskDelete() +#endif + +#ifndef traceENTER_xTaskDelayUntil + #define traceENTER_xTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement ) +#endif + +#ifndef traceRETURN_xTaskDelayUntil + #define traceRETURN_xTaskDelayUntil( xShouldDelay ) +#endif + +#ifndef traceENTER_vTaskDelay + #define traceENTER_vTaskDelay( xTicksToDelay ) +#endif + +#ifndef traceRETURN_vTaskDelay + #define traceRETURN_vTaskDelay() +#endif + +#ifndef traceENTER_eTaskGetState + #define traceENTER_eTaskGetState( xTask ) +#endif + +#ifndef traceRETURN_eTaskGetState + #define traceRETURN_eTaskGetState( eReturn ) +#endif + +#ifndef traceENTER_uxTaskPriorityGet + #define traceENTER_uxTaskPriorityGet( xTask ) +#endif + +#ifndef traceRETURN_uxTaskPriorityGet + #define traceRETURN_uxTaskPriorityGet( uxReturn ) +#endif + +#ifndef traceENTER_uxTaskPriorityGetFromISR + #define traceENTER_uxTaskPriorityGetFromISR( xTask ) +#endif + +#ifndef traceRETURN_uxTaskPriorityGetFromISR + #define traceRETURN_uxTaskPriorityGetFromISR( uxReturn ) +#endif + +#ifndef traceENTER_uxTaskBasePriorityGet + #define traceENTER_uxTaskBasePriorityGet( xTask ) +#endif + +#ifndef traceRETURN_uxTaskBasePriorityGet + #define traceRETURN_uxTaskBasePriorityGet( uxReturn ) +#endif + +#ifndef traceENTER_uxTaskBasePriorityGetFromISR + #define traceENTER_uxTaskBasePriorityGetFromISR( xTask ) +#endif + +#ifndef traceRETURN_uxTaskBasePriorityGetFromISR + #define traceRETURN_uxTaskBasePriorityGetFromISR( uxReturn ) +#endif + +#ifndef traceENTER_vTaskPrioritySet + #define traceENTER_vTaskPrioritySet( xTask, uxNewPriority ) +#endif + +#ifndef traceRETURN_vTaskPrioritySet + #define traceRETURN_vTaskPrioritySet() +#endif + +#ifndef traceENTER_vTaskCoreAffinitySet + #define traceENTER_vTaskCoreAffinitySet( xTask, uxCoreAffinityMask ) +#endif + +#ifndef traceRETURN_vTaskCoreAffinitySet + #define traceRETURN_vTaskCoreAffinitySet() +#endif + +#ifndef traceENTER_vTaskCoreAffinityGet + #define traceENTER_vTaskCoreAffinityGet( xTask ) +#endif + +#ifndef traceRETURN_vTaskCoreAffinityGet + #define traceRETURN_vTaskCoreAffinityGet( uxCoreAffinityMask ) +#endif + +#ifndef traceENTER_vTaskPreemptionDisable + #define traceENTER_vTaskPreemptionDisable( xTask ) +#endif + +#ifndef traceRETURN_vTaskPreemptionDisable + #define traceRETURN_vTaskPreemptionDisable() +#endif + +#ifndef traceENTER_vTaskPreemptionEnable + #define traceENTER_vTaskPreemptionEnable( xTask ) +#endif + +#ifndef traceRETURN_vTaskPreemptionEnable + #define traceRETURN_vTaskPreemptionEnable() +#endif + +#ifndef traceENTER_vTaskSuspend + #define traceENTER_vTaskSuspend( xTaskToSuspend ) +#endif + +#ifndef traceRETURN_vTaskSuspend + #define traceRETURN_vTaskSuspend() +#endif + +#ifndef traceENTER_vTaskResume + #define traceENTER_vTaskResume( xTaskToResume ) +#endif + +#ifndef traceRETURN_vTaskResume + #define traceRETURN_vTaskResume() +#endif + +#ifndef traceENTER_xTaskResumeFromISR + #define traceENTER_xTaskResumeFromISR( xTaskToResume ) +#endif + +#ifndef traceRETURN_xTaskResumeFromISR + #define traceRETURN_xTaskResumeFromISR( xYieldRequired ) +#endif + +#ifndef traceENTER_vTaskStartScheduler + #define traceENTER_vTaskStartScheduler() +#endif + +#ifndef traceRETURN_vTaskStartScheduler + #define traceRETURN_vTaskStartScheduler() +#endif + +#ifndef traceENTER_vTaskEndScheduler + #define traceENTER_vTaskEndScheduler() +#endif + +#ifndef traceRETURN_vTaskEndScheduler + #define traceRETURN_vTaskEndScheduler() +#endif + +#ifndef traceENTER_vTaskSuspendAll + #define traceENTER_vTaskSuspendAll() +#endif + +#ifndef traceRETURN_vTaskSuspendAll + #define traceRETURN_vTaskSuspendAll() +#endif + +#ifndef traceENTER_xTaskResumeAll + #define traceENTER_xTaskResumeAll() +#endif + +#ifndef traceRETURN_xTaskResumeAll + #define traceRETURN_xTaskResumeAll( xAlreadyYielded ) +#endif + +#ifndef traceENTER_xTaskGetTickCount + #define traceENTER_xTaskGetTickCount() +#endif + +#ifndef traceRETURN_xTaskGetTickCount + #define traceRETURN_xTaskGetTickCount( xTicks ) +#endif + +#ifndef traceENTER_xTaskGetTickCountFromISR + #define traceENTER_xTaskGetTickCountFromISR() +#endif + +#ifndef traceRETURN_xTaskGetTickCountFromISR + #define traceRETURN_xTaskGetTickCountFromISR( xReturn ) +#endif + +#ifndef traceENTER_uxTaskGetNumberOfTasks + #define traceENTER_uxTaskGetNumberOfTasks() +#endif + +#ifndef traceRETURN_uxTaskGetNumberOfTasks + #define traceRETURN_uxTaskGetNumberOfTasks( uxCurrentNumberOfTasks ) +#endif + +#ifndef traceENTER_pcTaskGetName + #define traceENTER_pcTaskGetName( xTaskToQuery ) +#endif + +#ifndef traceRETURN_pcTaskGetName + #define traceRETURN_pcTaskGetName( pcTaskName ) +#endif + +#ifndef traceENTER_xTaskGetHandle + #define traceENTER_xTaskGetHandle( pcNameToQuery ) +#endif + +#ifndef traceRETURN_xTaskGetHandle + #define traceRETURN_xTaskGetHandle( pxTCB ) +#endif + +#ifndef traceENTER_xTaskGetStaticBuffers + #define traceENTER_xTaskGetStaticBuffers( xTask, ppuxStackBuffer, ppxTaskBuffer ) +#endif + +#ifndef traceRETURN_xTaskGetStaticBuffers + #define traceRETURN_xTaskGetStaticBuffers( xReturn ) +#endif + +#ifndef traceENTER_uxTaskGetSystemState + #define traceENTER_uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, pulTotalRunTime ) +#endif + +#ifndef traceRETURN_uxTaskGetSystemState + #define traceRETURN_uxTaskGetSystemState( uxTask ) +#endif + +#if ( configNUMBER_OF_CORES == 1 ) + #ifndef traceENTER_xTaskGetIdleTaskHandle + #define traceENTER_xTaskGetIdleTaskHandle() + #endif +#endif + +#if ( configNUMBER_OF_CORES == 1 ) + #ifndef traceRETURN_xTaskGetIdleTaskHandle + #define traceRETURN_xTaskGetIdleTaskHandle( xIdleTaskHandle ) + #endif +#endif + +#ifndef traceENTER_xTaskGetIdleTaskHandleForCore + #define traceENTER_xTaskGetIdleTaskHandleForCore( xCoreID ) +#endif + +#ifndef traceRETURN_xTaskGetIdleTaskHandleForCore + #define traceRETURN_xTaskGetIdleTaskHandleForCore( xIdleTaskHandle ) +#endif + +#ifndef traceENTER_vTaskStepTick + #define traceENTER_vTaskStepTick( xTicksToJump ) +#endif + +#ifndef traceRETURN_vTaskStepTick + #define traceRETURN_vTaskStepTick() +#endif + +#ifndef traceENTER_xTaskCatchUpTicks + #define traceENTER_xTaskCatchUpTicks( xTicksToCatchUp ) +#endif + +#ifndef traceRETURN_xTaskCatchUpTicks + #define traceRETURN_xTaskCatchUpTicks( xYieldOccurred ) +#endif + +#ifndef traceENTER_xTaskAbortDelay + #define traceENTER_xTaskAbortDelay( xTask ) +#endif + +#ifndef traceRETURN_xTaskAbortDelay + #define traceRETURN_xTaskAbortDelay( xReturn ) +#endif + +#ifndef traceENTER_xTaskIncrementTick + #define traceENTER_xTaskIncrementTick() +#endif + +#ifndef traceRETURN_xTaskIncrementTick + #define traceRETURN_xTaskIncrementTick( xSwitchRequired ) +#endif + +#ifndef traceENTER_vTaskSetApplicationTaskTag + #define traceENTER_vTaskSetApplicationTaskTag( xTask, pxHookFunction ) +#endif + +#ifndef traceRETURN_vTaskSetApplicationTaskTag + #define traceRETURN_vTaskSetApplicationTaskTag() +#endif + +#ifndef traceENTER_xTaskGetApplicationTaskTag + #define traceENTER_xTaskGetApplicationTaskTag( xTask ) +#endif + +#ifndef traceRETURN_xTaskGetApplicationTaskTag + #define traceRETURN_xTaskGetApplicationTaskTag( xReturn ) +#endif + +#ifndef traceENTER_xTaskGetApplicationTaskTagFromISR + #define traceENTER_xTaskGetApplicationTaskTagFromISR( xTask ) +#endif + +#ifndef traceRETURN_xTaskGetApplicationTaskTagFromISR + #define traceRETURN_xTaskGetApplicationTaskTagFromISR( xReturn ) +#endif + +#ifndef traceENTER_xTaskCallApplicationTaskHook + #define traceENTER_xTaskCallApplicationTaskHook( xTask, pvParameter ) +#endif + +#ifndef traceRETURN_xTaskCallApplicationTaskHook + #define traceRETURN_xTaskCallApplicationTaskHook( xReturn ) +#endif + +#ifndef traceENTER_vTaskSwitchContext + #define traceENTER_vTaskSwitchContext() +#endif + +#ifndef traceRETURN_vTaskSwitchContext + #define traceRETURN_vTaskSwitchContext() +#endif + +#ifndef traceENTER_vTaskPlaceOnEventList + #define traceENTER_vTaskPlaceOnEventList( pxEventList, xTicksToWait ) +#endif + +#ifndef traceRETURN_vTaskPlaceOnEventList + #define traceRETURN_vTaskPlaceOnEventList() +#endif + +#ifndef traceENTER_vTaskPlaceOnUnorderedEventList + #define traceENTER_vTaskPlaceOnUnorderedEventList( pxEventList, xItemValue, xTicksToWait ) +#endif + +#ifndef traceRETURN_vTaskPlaceOnUnorderedEventList + #define traceRETURN_vTaskPlaceOnUnorderedEventList() +#endif + +#ifndef traceENTER_vTaskPlaceOnEventListRestricted + #define traceENTER_vTaskPlaceOnEventListRestricted( pxEventList, xTicksToWait, xWaitIndefinitely ) +#endif + +#ifndef traceRETURN_vTaskPlaceOnEventListRestricted + #define traceRETURN_vTaskPlaceOnEventListRestricted() +#endif + +#ifndef traceENTER_xTaskRemoveFromEventList + #define traceENTER_xTaskRemoveFromEventList( pxEventList ) +#endif + +#ifndef traceRETURN_xTaskRemoveFromEventList + #define traceRETURN_xTaskRemoveFromEventList( xReturn ) +#endif + +#ifndef traceENTER_vTaskRemoveFromUnorderedEventList + #define traceENTER_vTaskRemoveFromUnorderedEventList( pxEventListItem, xItemValue ) +#endif + +#ifndef traceRETURN_vTaskRemoveFromUnorderedEventList + #define traceRETURN_vTaskRemoveFromUnorderedEventList() +#endif + +#ifndef traceENTER_vTaskSetTimeOutState + #define traceENTER_vTaskSetTimeOutState( pxTimeOut ) +#endif + +#ifndef traceRETURN_vTaskSetTimeOutState + #define traceRETURN_vTaskSetTimeOutState() +#endif + +#ifndef traceENTER_vTaskInternalSetTimeOutState + #define traceENTER_vTaskInternalSetTimeOutState( pxTimeOut ) +#endif + +#ifndef traceRETURN_vTaskInternalSetTimeOutState + #define traceRETURN_vTaskInternalSetTimeOutState() +#endif + +#ifndef traceENTER_xTaskCheckForTimeOut + #define traceENTER_xTaskCheckForTimeOut( pxTimeOut, pxTicksToWait ) +#endif + +#ifndef traceRETURN_xTaskCheckForTimeOut + #define traceRETURN_xTaskCheckForTimeOut( xReturn ) +#endif + +#ifndef traceENTER_vTaskMissedYield + #define traceENTER_vTaskMissedYield() +#endif + +#ifndef traceRETURN_vTaskMissedYield + #define traceRETURN_vTaskMissedYield() +#endif + +#ifndef traceENTER_uxTaskGetTaskNumber + #define traceENTER_uxTaskGetTaskNumber( xTask ) +#endif + +#ifndef traceRETURN_uxTaskGetTaskNumber + #define traceRETURN_uxTaskGetTaskNumber( uxReturn ) +#endif + +#ifndef traceENTER_vTaskSetTaskNumber + #define traceENTER_vTaskSetTaskNumber( xTask, uxHandle ) +#endif + +#ifndef traceRETURN_vTaskSetTaskNumber + #define traceRETURN_vTaskSetTaskNumber() +#endif + +#ifndef traceENTER_eTaskConfirmSleepModeStatus + #define traceENTER_eTaskConfirmSleepModeStatus() +#endif + +#ifndef traceRETURN_eTaskConfirmSleepModeStatus + #define traceRETURN_eTaskConfirmSleepModeStatus( eReturn ) +#endif + +#ifndef traceENTER_vTaskSetThreadLocalStoragePointer + #define traceENTER_vTaskSetThreadLocalStoragePointer( xTaskToSet, xIndex, pvValue ) +#endif + +#ifndef traceRETURN_vTaskSetThreadLocalStoragePointer + #define traceRETURN_vTaskSetThreadLocalStoragePointer() +#endif + +#ifndef traceENTER_pvTaskGetThreadLocalStoragePointer + #define traceENTER_pvTaskGetThreadLocalStoragePointer( xTaskToQuery, xIndex ) +#endif + +#ifndef traceRETURN_pvTaskGetThreadLocalStoragePointer + #define traceRETURN_pvTaskGetThreadLocalStoragePointer( pvReturn ) +#endif + +#ifndef traceENTER_vTaskAllocateMPURegions + #define traceENTER_vTaskAllocateMPURegions( xTaskToModify, pxRegions ) +#endif + +#ifndef traceRETURN_vTaskAllocateMPURegions + #define traceRETURN_vTaskAllocateMPURegions() +#endif + +#ifndef traceENTER_vTaskGetInfo + #define traceENTER_vTaskGetInfo( xTask, pxTaskStatus, xGetFreeStackSpace, eState ) +#endif + +#ifndef traceRETURN_vTaskGetInfo + #define traceRETURN_vTaskGetInfo() +#endif + +#ifndef traceENTER_uxTaskGetStackHighWaterMark2 + #define traceENTER_uxTaskGetStackHighWaterMark2( xTask ) +#endif + +#ifndef traceRETURN_uxTaskGetStackHighWaterMark2 + #define traceRETURN_uxTaskGetStackHighWaterMark2( uxReturn ) +#endif + +#ifndef traceENTER_uxTaskGetStackHighWaterMark + #define traceENTER_uxTaskGetStackHighWaterMark( xTask ) +#endif + +#ifndef traceRETURN_uxTaskGetStackHighWaterMark + #define traceRETURN_uxTaskGetStackHighWaterMark( uxReturn ) +#endif + +#ifndef traceENTER_xTaskGetCurrentTaskHandle + #define traceENTER_xTaskGetCurrentTaskHandle() +#endif + +#ifndef traceRETURN_xTaskGetCurrentTaskHandle + #define traceRETURN_xTaskGetCurrentTaskHandle( xReturn ) +#endif + +#ifndef traceENTER_xTaskGetCurrentTaskHandleForCore + #define traceENTER_xTaskGetCurrentTaskHandleForCore( xCoreID ) +#endif + +#ifndef traceRETURN_xTaskGetCurrentTaskHandleForCore + #define traceRETURN_xTaskGetCurrentTaskHandleForCore( xReturn ) +#endif + +#ifndef traceENTER_xTaskGetSchedulerState + #define traceENTER_xTaskGetSchedulerState() +#endif + +#ifndef traceRETURN_xTaskGetSchedulerState + #define traceRETURN_xTaskGetSchedulerState( xReturn ) +#endif + +#ifndef traceENTER_xTaskPriorityInherit + #define traceENTER_xTaskPriorityInherit( pxMutexHolder ) +#endif + +#ifndef traceRETURN_xTaskPriorityInherit + #define traceRETURN_xTaskPriorityInherit( xReturn ) +#endif + +#ifndef traceENTER_xTaskPriorityDisinherit + #define traceENTER_xTaskPriorityDisinherit( pxMutexHolder ) +#endif + +#ifndef traceRETURN_xTaskPriorityDisinherit + #define traceRETURN_xTaskPriorityDisinherit( xReturn ) +#endif + +#ifndef traceENTER_vTaskPriorityDisinheritAfterTimeout + #define traceENTER_vTaskPriorityDisinheritAfterTimeout( pxMutexHolder, uxHighestPriorityWaitingTask ) +#endif + +#ifndef traceRETURN_vTaskPriorityDisinheritAfterTimeout + #define traceRETURN_vTaskPriorityDisinheritAfterTimeout() +#endif + +#ifndef traceENTER_vTaskYieldWithinAPI + #define traceENTER_vTaskYieldWithinAPI() +#endif + +#ifndef traceRETURN_vTaskYieldWithinAPI + #define traceRETURN_vTaskYieldWithinAPI() +#endif + +#ifndef traceENTER_vTaskEnterCritical + #define traceENTER_vTaskEnterCritical() +#endif + +#ifndef traceRETURN_vTaskEnterCritical + #define traceRETURN_vTaskEnterCritical() +#endif + +#ifndef traceENTER_vTaskEnterCriticalFromISR + #define traceENTER_vTaskEnterCriticalFromISR() +#endif + +#ifndef traceRETURN_vTaskEnterCriticalFromISR + #define traceRETURN_vTaskEnterCriticalFromISR( uxSavedInterruptStatus ) +#endif + +#ifndef traceENTER_vTaskExitCritical + #define traceENTER_vTaskExitCritical() +#endif + +#ifndef traceRETURN_vTaskExitCritical + #define traceRETURN_vTaskExitCritical() +#endif + +#ifndef traceENTER_vTaskExitCriticalFromISR + #define traceENTER_vTaskExitCriticalFromISR( uxSavedInterruptStatus ) +#endif + +#ifndef traceRETURN_vTaskExitCriticalFromISR + #define traceRETURN_vTaskExitCriticalFromISR() +#endif + +#ifndef traceENTER_vTaskListTasks + #define traceENTER_vTaskListTasks( pcWriteBuffer, uxBufferLength ) +#endif + +#ifndef traceRETURN_vTaskListTasks + #define traceRETURN_vTaskListTasks() +#endif + +#ifndef traceENTER_vTaskGetRunTimeStatistics + #define traceENTER_vTaskGetRunTimeStatistics( pcWriteBuffer, uxBufferLength ) +#endif + +#ifndef traceRETURN_vTaskGetRunTimeStatistics + #define traceRETURN_vTaskGetRunTimeStatistics() +#endif + +#ifndef traceENTER_uxTaskResetEventItemValue + #define traceENTER_uxTaskResetEventItemValue() +#endif + +#ifndef traceRETURN_uxTaskResetEventItemValue + #define traceRETURN_uxTaskResetEventItemValue( uxReturn ) +#endif + +#ifndef traceENTER_pvTaskIncrementMutexHeldCount + #define traceENTER_pvTaskIncrementMutexHeldCount() +#endif + +#ifndef traceRETURN_pvTaskIncrementMutexHeldCount + #define traceRETURN_pvTaskIncrementMutexHeldCount( pxTCB ) +#endif + +#ifndef traceENTER_ulTaskGenericNotifyTake + #define traceENTER_ulTaskGenericNotifyTake( uxIndexToWaitOn, xClearCountOnExit, xTicksToWait ) +#endif + +#ifndef traceRETURN_ulTaskGenericNotifyTake + #define traceRETURN_ulTaskGenericNotifyTake( ulReturn ) +#endif + +#ifndef traceENTER_xTaskGenericNotifyWait + #define traceENTER_xTaskGenericNotifyWait( uxIndexToWaitOn, ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait ) +#endif + +#ifndef traceRETURN_xTaskGenericNotifyWait + #define traceRETURN_xTaskGenericNotifyWait( xReturn ) +#endif + +#ifndef traceENTER_xTaskGenericNotify + #define traceENTER_xTaskGenericNotify( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue ) +#endif + +#ifndef traceRETURN_xTaskGenericNotify + #define traceRETURN_xTaskGenericNotify( xReturn ) +#endif + +#ifndef traceENTER_xTaskGenericNotifyFromISR + #define traceENTER_xTaskGenericNotifyFromISR( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken ) +#endif + +#ifndef traceRETURN_xTaskGenericNotifyFromISR + #define traceRETURN_xTaskGenericNotifyFromISR( xReturn ) +#endif + +#ifndef traceENTER_vTaskGenericNotifyGiveFromISR + #define traceENTER_vTaskGenericNotifyGiveFromISR( xTaskToNotify, uxIndexToNotify, pxHigherPriorityTaskWoken ) +#endif + +#ifndef traceRETURN_vTaskGenericNotifyGiveFromISR + #define traceRETURN_vTaskGenericNotifyGiveFromISR() +#endif + +#ifndef traceENTER_xTaskGenericNotifyStateClear + #define traceENTER_xTaskGenericNotifyStateClear( xTask, uxIndexToClear ) +#endif + +#ifndef traceRETURN_xTaskGenericNotifyStateClear + #define traceRETURN_xTaskGenericNotifyStateClear( xReturn ) +#endif + +#ifndef traceENTER_ulTaskGenericNotifyValueClear + #define traceENTER_ulTaskGenericNotifyValueClear( xTask, uxIndexToClear, ulBitsToClear ) +#endif + +#ifndef traceRETURN_ulTaskGenericNotifyValueClear + #define traceRETURN_ulTaskGenericNotifyValueClear( ulReturn ) +#endif + +#ifndef traceENTER_ulTaskGetRunTimeCounter + #define traceENTER_ulTaskGetRunTimeCounter( xTask ) +#endif + +#ifndef traceRETURN_ulTaskGetRunTimeCounter + #define traceRETURN_ulTaskGetRunTimeCounter( ulRunTimeCounter ) +#endif + +#ifndef traceENTER_ulTaskGetRunTimePercent + #define traceENTER_ulTaskGetRunTimePercent( xTask ) +#endif + +#ifndef traceRETURN_ulTaskGetRunTimePercent + #define traceRETURN_ulTaskGetRunTimePercent( ulReturn ) +#endif + +#ifndef traceENTER_ulTaskGetIdleRunTimeCounter + #define traceENTER_ulTaskGetIdleRunTimeCounter() +#endif + +#ifndef traceRETURN_ulTaskGetIdleRunTimeCounter + #define traceRETURN_ulTaskGetIdleRunTimeCounter( ulReturn ) +#endif + +#ifndef traceENTER_ulTaskGetIdleRunTimePercent + #define traceENTER_ulTaskGetIdleRunTimePercent() +#endif + +#ifndef traceRETURN_ulTaskGetIdleRunTimePercent + #define traceRETURN_ulTaskGetIdleRunTimePercent( ulReturn ) +#endif + +#ifndef traceENTER_xTaskGetMPUSettings + #define traceENTER_xTaskGetMPUSettings( xTask ) +#endif + +#ifndef traceRETURN_xTaskGetMPUSettings + #define traceRETURN_xTaskGetMPUSettings( xMPUSettings ) +#endif + +#ifndef traceENTER_xStreamBufferGenericCreate + #define traceENTER_xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, xStreamBufferType, pxSendCompletedCallback, pxReceiveCompletedCallback ) +#endif + +#ifndef traceRETURN_xStreamBufferGenericCreate + #define traceRETURN_xStreamBufferGenericCreate( pvAllocatedMemory ) +#endif + +#ifndef traceENTER_xStreamBufferGenericCreateStatic + #define traceENTER_xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, xStreamBufferType, pucStreamBufferStorageArea, pxStaticStreamBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback ) +#endif + +#ifndef traceRETURN_xStreamBufferGenericCreateStatic + #define traceRETURN_xStreamBufferGenericCreateStatic( xReturn ) +#endif + +#ifndef traceENTER_xStreamBufferGetStaticBuffers + #define traceENTER_xStreamBufferGetStaticBuffers( xStreamBuffer, ppucStreamBufferStorageArea, ppxStaticStreamBuffer ) +#endif + +#ifndef traceRETURN_xStreamBufferGetStaticBuffers + #define traceRETURN_xStreamBufferGetStaticBuffers( xReturn ) +#endif + +#ifndef traceENTER_vStreamBufferDelete + #define traceENTER_vStreamBufferDelete( xStreamBuffer ) +#endif + +#ifndef traceRETURN_vStreamBufferDelete + #define traceRETURN_vStreamBufferDelete() +#endif + +#ifndef traceENTER_xStreamBufferReset + #define traceENTER_xStreamBufferReset( xStreamBuffer ) +#endif + +#ifndef traceRETURN_xStreamBufferReset + #define traceRETURN_xStreamBufferReset( xReturn ) +#endif + +#ifndef traceENTER_xStreamBufferResetFromISR + #define traceENTER_xStreamBufferResetFromISR( xStreamBuffer ) +#endif + +#ifndef traceRETURN_xStreamBufferResetFromISR + #define traceRETURN_xStreamBufferResetFromISR( xReturn ) +#endif + +#ifndef traceENTER_xStreamBufferSetTriggerLevel + #define traceENTER_xStreamBufferSetTriggerLevel( xStreamBuffer, xTriggerLevel ) +#endif + +#ifndef traceRETURN_xStreamBufferSetTriggerLevel + #define traceRETURN_xStreamBufferSetTriggerLevel( xReturn ) +#endif + +#ifndef traceENTER_xStreamBufferSpacesAvailable + #define traceENTER_xStreamBufferSpacesAvailable( xStreamBuffer ) +#endif + +#ifndef traceRETURN_xStreamBufferSpacesAvailable + #define traceRETURN_xStreamBufferSpacesAvailable( xSpace ) +#endif + +#ifndef traceENTER_xStreamBufferBytesAvailable + #define traceENTER_xStreamBufferBytesAvailable( xStreamBuffer ) +#endif + +#ifndef traceRETURN_xStreamBufferBytesAvailable + #define traceRETURN_xStreamBufferBytesAvailable( xReturn ) +#endif + +#ifndef traceENTER_xStreamBufferSend + #define traceENTER_xStreamBufferSend( xStreamBuffer, pvTxData, xDataLengthBytes, xTicksToWait ) +#endif + +#ifndef traceRETURN_xStreamBufferSend + #define traceRETURN_xStreamBufferSend( xReturn ) +#endif + +#ifndef traceENTER_xStreamBufferSendFromISR + #define traceENTER_xStreamBufferSendFromISR( xStreamBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken ) +#endif + +#ifndef traceRETURN_xStreamBufferSendFromISR + #define traceRETURN_xStreamBufferSendFromISR( xReturn ) +#endif + +#ifndef traceENTER_xStreamBufferReceive + #define traceENTER_xStreamBufferReceive( xStreamBuffer, pvRxData, xBufferLengthBytes, xTicksToWait ) +#endif + +#ifndef traceRETURN_xStreamBufferReceive + #define traceRETURN_xStreamBufferReceive( xReceivedLength ) +#endif + +#ifndef traceENTER_xStreamBufferNextMessageLengthBytes + #define traceENTER_xStreamBufferNextMessageLengthBytes( xStreamBuffer ) +#endif + +#ifndef traceRETURN_xStreamBufferNextMessageLengthBytes + #define traceRETURN_xStreamBufferNextMessageLengthBytes( xReturn ) +#endif + +#ifndef traceENTER_xStreamBufferReceiveFromISR + #define traceENTER_xStreamBufferReceiveFromISR( xStreamBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken ) +#endif + +#ifndef traceRETURN_xStreamBufferReceiveFromISR + #define traceRETURN_xStreamBufferReceiveFromISR( xReceivedLength ) +#endif + +#ifndef traceENTER_xStreamBufferIsEmpty + #define traceENTER_xStreamBufferIsEmpty( xStreamBuffer ) +#endif + +#ifndef traceRETURN_xStreamBufferIsEmpty + #define traceRETURN_xStreamBufferIsEmpty( xReturn ) +#endif + +#ifndef traceENTER_xStreamBufferIsFull + #define traceENTER_xStreamBufferIsFull( xStreamBuffer ) +#endif + +#ifndef traceRETURN_xStreamBufferIsFull + #define traceRETURN_xStreamBufferIsFull( xReturn ) +#endif + +#ifndef traceENTER_xStreamBufferSendCompletedFromISR + #define traceENTER_xStreamBufferSendCompletedFromISR( xStreamBuffer, pxHigherPriorityTaskWoken ) +#endif + +#ifndef traceRETURN_xStreamBufferSendCompletedFromISR + #define traceRETURN_xStreamBufferSendCompletedFromISR( xReturn ) +#endif + +#ifndef traceENTER_xStreamBufferReceiveCompletedFromISR + #define traceENTER_xStreamBufferReceiveCompletedFromISR( xStreamBuffer, pxHigherPriorityTaskWoken ) +#endif + +#ifndef traceRETURN_xStreamBufferReceiveCompletedFromISR + #define traceRETURN_xStreamBufferReceiveCompletedFromISR( xReturn ) +#endif + +#ifndef traceENTER_uxStreamBufferGetStreamBufferNotificationIndex + #define traceENTER_uxStreamBufferGetStreamBufferNotificationIndex( xStreamBuffer ) +#endif + +#ifndef traceRETURN_uxStreamBufferGetStreamBufferNotificationIndex + #define traceRETURN_uxStreamBufferGetStreamBufferNotificationIndex( uxNotificationIndex ) +#endif + +#ifndef traceENTER_vStreamBufferSetStreamBufferNotificationIndex + #define traceENTER_vStreamBufferSetStreamBufferNotificationIndex( xStreamBuffer, uxNotificationIndex ) +#endif + +#ifndef traceRETURN_vStreamBufferSetStreamBufferNotificationIndex + #define traceRETURN_vStreamBufferSetStreamBufferNotificationIndex() +#endif + +#ifndef traceENTER_uxStreamBufferGetStreamBufferNumber + #define traceENTER_uxStreamBufferGetStreamBufferNumber( xStreamBuffer ) +#endif + +#ifndef traceRETURN_uxStreamBufferGetStreamBufferNumber + #define traceRETURN_uxStreamBufferGetStreamBufferNumber( uxStreamBufferNumber ) +#endif + +#ifndef traceENTER_vStreamBufferSetStreamBufferNumber + #define traceENTER_vStreamBufferSetStreamBufferNumber( xStreamBuffer, uxStreamBufferNumber ) +#endif + +#ifndef traceRETURN_vStreamBufferSetStreamBufferNumber + #define traceRETURN_vStreamBufferSetStreamBufferNumber() +#endif + +#ifndef traceENTER_ucStreamBufferGetStreamBufferType + #define traceENTER_ucStreamBufferGetStreamBufferType( xStreamBuffer ) +#endif + +#ifndef traceRETURN_ucStreamBufferGetStreamBufferType + #define traceRETURN_ucStreamBufferGetStreamBufferType( ucStreamBufferType ) +#endif + +#ifndef traceENTER_vListInitialise + #define traceENTER_vListInitialise( pxList ) +#endif + +#ifndef traceRETURN_vListInitialise + #define traceRETURN_vListInitialise() +#endif + +#ifndef traceENTER_vListInitialiseItem + #define traceENTER_vListInitialiseItem( pxItem ) +#endif + +#ifndef traceRETURN_vListInitialiseItem + #define traceRETURN_vListInitialiseItem() +#endif + +#ifndef traceENTER_vListInsertEnd + #define traceENTER_vListInsertEnd( pxList, pxNewListItem ) +#endif + +#ifndef traceRETURN_vListInsertEnd + #define traceRETURN_vListInsertEnd() +#endif + +#ifndef traceENTER_vListInsert + #define traceENTER_vListInsert( pxList, pxNewListItem ) +#endif + +#ifndef traceRETURN_vListInsert + #define traceRETURN_vListInsert() +#endif + +#ifndef traceENTER_uxListRemove + #define traceENTER_uxListRemove( pxItemToRemove ) +#endif + +#ifndef traceRETURN_uxListRemove + #define traceRETURN_uxListRemove( uxNumberOfItems ) +#endif + +#ifndef traceENTER_xCoRoutineCreate + #define traceENTER_xCoRoutineCreate( pxCoRoutineCode, uxPriority, uxIndex ) +#endif + +#ifndef traceRETURN_xCoRoutineCreate + #define traceRETURN_xCoRoutineCreate( xReturn ) +#endif + +#ifndef traceENTER_vCoRoutineAddToDelayedList + #define traceENTER_vCoRoutineAddToDelayedList( xTicksToDelay, pxEventList ) +#endif + +#ifndef traceRETURN_vCoRoutineAddToDelayedList + #define traceRETURN_vCoRoutineAddToDelayedList() +#endif + +#ifndef traceENTER_vCoRoutineSchedule + #define traceENTER_vCoRoutineSchedule() +#endif + +#ifndef traceRETURN_vCoRoutineSchedule + #define traceRETURN_vCoRoutineSchedule() +#endif + +#ifndef traceENTER_xCoRoutineRemoveFromEventList + #define traceENTER_xCoRoutineRemoveFromEventList( pxEventList ) +#endif + +#ifndef traceRETURN_xCoRoutineRemoveFromEventList + #define traceRETURN_xCoRoutineRemoveFromEventList( xReturn ) +#endif + +#ifndef configGENERATE_RUN_TIME_STATS + #define configGENERATE_RUN_TIME_STATS 0 +#endif + +#if ( configGENERATE_RUN_TIME_STATS == 1 ) + + #ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS + #error If configGENERATE_RUN_TIME_STATS is defined then portCONFIGURE_TIMER_FOR_RUN_TIME_STATS must also be defined. portCONFIGURE_TIMER_FOR_RUN_TIME_STATS should call a port layer function to setup a peripheral timer/counter that can then be used as the run time counter time base. + #endif /* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS */ + + #ifndef portGET_RUN_TIME_COUNTER_VALUE + #ifndef portALT_GET_RUN_TIME_COUNTER_VALUE + #error If configGENERATE_RUN_TIME_STATS is defined then either portGET_RUN_TIME_COUNTER_VALUE or portALT_GET_RUN_TIME_COUNTER_VALUE must also be defined. See the examples provided and the FreeRTOS web site for more information. + #endif /* portALT_GET_RUN_TIME_COUNTER_VALUE */ + #endif /* portGET_RUN_TIME_COUNTER_VALUE */ + +#endif /* configGENERATE_RUN_TIME_STATS */ + +#ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS + #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() +#endif + +#ifndef portPRIVILEGE_BIT + #define portPRIVILEGE_BIT ( ( UBaseType_t ) 0x00 ) +#endif + +#ifndef portYIELD_WITHIN_API + #define portYIELD_WITHIN_API portYIELD +#endif + +#ifndef portSUPPRESS_TICKS_AND_SLEEP + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) +#endif + +#ifndef configEXPECTED_IDLE_TIME_BEFORE_SLEEP + #define configEXPECTED_IDLE_TIME_BEFORE_SLEEP 2 +#endif + +#if configEXPECTED_IDLE_TIME_BEFORE_SLEEP < 2 + #error configEXPECTED_IDLE_TIME_BEFORE_SLEEP must not be less than 2 +#endif + +#ifndef configUSE_TICKLESS_IDLE + #define configUSE_TICKLESS_IDLE 0 +#endif + +#ifndef configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING + #define configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( x ) +#endif + +#ifndef configPRE_SLEEP_PROCESSING + #define configPRE_SLEEP_PROCESSING( x ) +#endif + +#ifndef configPOST_SLEEP_PROCESSING + #define configPOST_SLEEP_PROCESSING( x ) +#endif + +#ifndef configUSE_QUEUE_SETS + #define configUSE_QUEUE_SETS 0 +#endif + +#ifndef portTASK_USES_FLOATING_POINT + #define portTASK_USES_FLOATING_POINT() +#endif + +#ifndef portALLOCATE_SECURE_CONTEXT + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) +#endif + +#ifndef portDONT_DISCARD + #define portDONT_DISCARD +#endif + +#ifndef configUSE_TIME_SLICING + #define configUSE_TIME_SLICING 1 +#endif + +#ifndef configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS + #define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS 0 +#endif + +#ifndef configUSE_STATS_FORMATTING_FUNCTIONS + #define configUSE_STATS_FORMATTING_FUNCTIONS 0 +#endif + +#ifndef portASSERT_IF_INTERRUPT_PRIORITY_INVALID + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() +#endif + +#ifndef configUSE_TRACE_FACILITY + #define configUSE_TRACE_FACILITY 0 +#endif + +#ifndef mtCOVERAGE_TEST_MARKER + #define mtCOVERAGE_TEST_MARKER() +#endif + +#ifndef mtCOVERAGE_TEST_DELAY + #define mtCOVERAGE_TEST_DELAY() +#endif + +#ifndef portASSERT_IF_IN_ISR + #define portASSERT_IF_IN_ISR() +#endif + +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#endif + +#ifndef configAPPLICATION_ALLOCATED_HEAP + #define configAPPLICATION_ALLOCATED_HEAP 0 +#endif + +#ifndef configENABLE_HEAP_PROTECTOR + #define configENABLE_HEAP_PROTECTOR 0 +#endif + +#ifndef configUSE_TASK_NOTIFICATIONS + #define configUSE_TASK_NOTIFICATIONS 1 +#endif + +#ifndef configTASK_NOTIFICATION_ARRAY_ENTRIES + #define configTASK_NOTIFICATION_ARRAY_ENTRIES 1 +#endif + +#if configTASK_NOTIFICATION_ARRAY_ENTRIES < 1 + #error configTASK_NOTIFICATION_ARRAY_ENTRIES must be at least 1 +#endif + +#ifndef configUSE_POSIX_ERRNO + #define configUSE_POSIX_ERRNO 0 +#endif + +#ifndef configUSE_SB_COMPLETED_CALLBACK + +/* By default per-instance callbacks are not enabled for stream buffer or message buffer. */ + #define configUSE_SB_COMPLETED_CALLBACK 0 +#endif + +#ifndef portTICK_TYPE_IS_ATOMIC + #define portTICK_TYPE_IS_ATOMIC 0 +#endif + +#ifndef configSUPPORT_STATIC_ALLOCATION + /* Defaults to 0 for backward compatibility. */ + #define configSUPPORT_STATIC_ALLOCATION 0 +#endif + +#ifndef configKERNEL_PROVIDED_STATIC_MEMORY + #define configKERNEL_PROVIDED_STATIC_MEMORY 0 +#endif + +#ifndef configSUPPORT_DYNAMIC_ALLOCATION + /* Defaults to 1 for backward compatibility. */ + #define configSUPPORT_DYNAMIC_ALLOCATION 1 +#endif + +#if ( ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION != 1 ) ) + #error configUSE_STATS_FORMATTING_FUNCTIONS cannot be used without dynamic allocation, but configSUPPORT_DYNAMIC_ALLOCATION is not set to 1. +#endif + +#if ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) + #if ( ( configUSE_TRACE_FACILITY != 1 ) && ( configGENERATE_RUN_TIME_STATS != 1 ) ) + #error configUSE_STATS_FORMATTING_FUNCTIONS is 1 but the functions it enables are not used because neither configUSE_TRACE_FACILITY or configGENERATE_RUN_TIME_STATS are 1. Set configUSE_STATS_FORMATTING_FUNCTIONS to 0 in FreeRTOSConfig.h. + #endif +#endif + +#ifndef configSTATS_BUFFER_MAX_LENGTH + #define configSTATS_BUFFER_MAX_LENGTH 0xFFFF +#endif + +#ifndef configSTACK_DEPTH_TYPE + +/* Defaults to StackType_t for backward compatibility, but can be overridden + * in FreeRTOSConfig.h if StackType_t is too restrictive. */ + #define configSTACK_DEPTH_TYPE StackType_t +#endif + +#ifndef configRUN_TIME_COUNTER_TYPE + +/* Defaults to uint32_t for backward compatibility, but can be overridden in + * FreeRTOSConfig.h if uint32_t is too restrictive. */ + + #define configRUN_TIME_COUNTER_TYPE uint32_t +#endif + +#ifndef configMESSAGE_BUFFER_LENGTH_TYPE + +/* Defaults to size_t for backward compatibility, but can be overridden + * in FreeRTOSConfig.h if lengths will always be less than the number of bytes + * in a size_t. */ + #define configMESSAGE_BUFFER_LENGTH_TYPE size_t +#endif + +/* Sanity check the configuration. */ +#if ( ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) ) + #error configSUPPORT_STATIC_ALLOCATION and configSUPPORT_DYNAMIC_ALLOCATION cannot both be 0, but can both be 1. +#endif + +#if ( ( configUSE_RECURSIVE_MUTEXES == 1 ) && ( configUSE_MUTEXES != 1 ) ) + #error configUSE_MUTEXES must be set to 1 to use recursive mutexes +#endif + +#if ( ( configRUN_MULTIPLE_PRIORITIES == 0 ) && ( configUSE_TASK_PREEMPTION_DISABLE != 0 ) ) + #error configRUN_MULTIPLE_PRIORITIES must be set to 1 to use task preemption disable +#endif + +#if ( ( configUSE_PREEMPTION == 0 ) && ( configUSE_TASK_PREEMPTION_DISABLE != 0 ) ) + #error configUSE_PREEMPTION must be set to 1 to use task preemption disable +#endif + +#if ( ( configNUMBER_OF_CORES == 1 ) && ( configUSE_TASK_PREEMPTION_DISABLE != 0 ) ) + #error configUSE_TASK_PREEMPTION_DISABLE is not supported in single core FreeRTOS +#endif + +#if ( ( configNUMBER_OF_CORES == 1 ) && ( configUSE_CORE_AFFINITY != 0 ) ) + #error configUSE_CORE_AFFINITY is not supported in single core FreeRTOS +#endif + +#if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_PORT_OPTIMISED_TASK_SELECTION != 0 ) ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION is not supported in SMP FreeRTOS +#endif + +#ifndef configINITIAL_TICK_COUNT + #define configINITIAL_TICK_COUNT 0 +#endif + +#if ( portTICK_TYPE_IS_ATOMIC == 0 ) + +/* Either variables of tick type cannot be read atomically, or + * portTICK_TYPE_IS_ATOMIC was not set - map the critical sections used when + * the tick count is returned to the standard critical section macros. */ + #define portTICK_TYPE_ENTER_CRITICAL() portENTER_CRITICAL() + #define portTICK_TYPE_EXIT_CRITICAL() portEXIT_CRITICAL() + #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR() + #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( ( x ) ) +#else + +/* The tick type can be read atomically, so critical sections used when the + * tick count is returned can be defined away. */ + #define portTICK_TYPE_ENTER_CRITICAL() + #define portTICK_TYPE_EXIT_CRITICAL() + #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() 0 + #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) ( void ) ( x ) +#endif /* if ( portTICK_TYPE_IS_ATOMIC == 0 ) */ + +/* Definitions to allow backward compatibility with FreeRTOS versions prior to + * V8 if desired. */ +#ifndef configENABLE_BACKWARD_COMPATIBILITY + #define configENABLE_BACKWARD_COMPATIBILITY 1 +#endif + +#ifndef configPRINTF + +/* configPRINTF() was not defined, so define it away to nothing. To use + * configPRINTF() then define it as follows (where MyPrintFunction() is + * provided by the application writer): + * + * void MyPrintFunction(const char *pcFormat, ... ); + #define configPRINTF( X ) MyPrintFunction X + * + * Then call like a standard printf() function, but placing brackets around + * all parameters so they are passed as a single parameter. For example: + * configPRINTF( ("Value = %d", MyVariable) ); */ + #define configPRINTF( X ) +#endif + +#ifndef configMAX + +/* The application writer has not provided their own MAX macro, so define + * the following generic implementation. */ + #define configMAX( a, b ) ( ( ( a ) > ( b ) ) ? ( a ) : ( b ) ) +#endif + +#ifndef configMIN + +/* The application writer has not provided their own MIN macro, so define + * the following generic implementation. */ + #define configMIN( a, b ) ( ( ( a ) < ( b ) ) ? ( a ) : ( b ) ) +#endif + +#if configENABLE_BACKWARD_COMPATIBILITY == 1 + #define eTaskStateGet eTaskGetState + #define portTickType TickType_t + #define xTaskHandle TaskHandle_t + #define xQueueHandle QueueHandle_t + #define xSemaphoreHandle SemaphoreHandle_t + #define xQueueSetHandle QueueSetHandle_t + #define xQueueSetMemberHandle QueueSetMemberHandle_t + #define xTimeOutType TimeOut_t + #define xMemoryRegion MemoryRegion_t + #define xTaskParameters TaskParameters_t + #define xTaskStatusType TaskStatus_t + #define xTimerHandle TimerHandle_t + #define xCoRoutineHandle CoRoutineHandle_t + #define pdTASK_HOOK_CODE TaskHookFunction_t + #define portTICK_RATE_MS portTICK_PERIOD_MS + #define pcTaskGetTaskName pcTaskGetName + #define pcTimerGetTimerName pcTimerGetName + #define pcQueueGetQueueName pcQueueGetName + #define vTaskGetTaskInfo vTaskGetInfo + #define xTaskGetIdleRunTimeCounter ulTaskGetIdleRunTimeCounter + +/* Backward compatibility within the scheduler code only - these definitions + * are not really required but are included for completeness. */ + #define tmrTIMER_CALLBACK TimerCallbackFunction_t + #define pdTASK_CODE TaskFunction_t + #define xListItem ListItem_t + #define xList List_t + +/* For libraries that break the list data hiding, and access list structure + * members directly (which is not supposed to be done). */ + #define pxContainer pvContainer +#endif /* configENABLE_BACKWARD_COMPATIBILITY */ + +#if ( configUSE_ALTERNATIVE_API != 0 ) + #error The alternative API was deprecated some time ago, and was removed in FreeRTOS V9.0 0 +#endif + +/* Set configUSE_TASK_FPU_SUPPORT to 0 to omit floating point support even + * if floating point hardware is otherwise supported by the FreeRTOS port in use. + * This constant is not supported by all FreeRTOS ports that include floating + * point support. */ +#ifndef configUSE_TASK_FPU_SUPPORT + #define configUSE_TASK_FPU_SUPPORT 1 +#endif + +/* Set configENABLE_MPU to 1 to enable MPU support and 0 to disable it. This is + * currently used in ARMv8M ports. */ +#ifndef configENABLE_MPU + #define configENABLE_MPU 0 +#endif + +/* Set configENABLE_FPU to 1 to enable FPU support and 0 to disable it. This is + * currently used in ARMv8M ports. */ +#ifndef configENABLE_FPU + #define configENABLE_FPU 1 +#endif + +/* Set configENABLE_MVE to 1 to enable MVE support and 0 to disable it. This is + * currently used in ARMv8M ports. */ +#ifndef configENABLE_MVE + #define configENABLE_MVE 0 +#endif + +/* Set configENABLE_TRUSTZONE to 1 enable TrustZone support and 0 to disable it. + * This is currently used in ARMv8M ports. */ +#ifndef configENABLE_TRUSTZONE + #define configENABLE_TRUSTZONE 1 +#endif + +/* Set configRUN_FREERTOS_SECURE_ONLY to 1 to run the FreeRTOS ARMv8M port on + * the Secure Side only. */ +#ifndef configRUN_FREERTOS_SECURE_ONLY + #define configRUN_FREERTOS_SECURE_ONLY 0 +#endif + +#ifndef configRUN_ADDITIONAL_TESTS + #define configRUN_ADDITIONAL_TESTS 0 +#endif + +/* The following config allows infinite loop control. For example, control the + * infinite loop in idle task function when performing unit tests. */ +#ifndef configCONTROL_INFINITE_LOOP + #define configCONTROL_INFINITE_LOOP() +#endif + +/* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using + * dynamically allocated RAM, in which case when any task is deleted it is known + * that both the task's stack and TCB need to be freed. Sometimes the + * FreeRTOSConfig.h settings only allow a task to be created using statically + * allocated RAM, in which case when any task is deleted it is known that neither + * the task's stack or TCB should be freed. Sometimes the FreeRTOSConfig.h + * settings allow a task to be created using either statically or dynamically + * allocated RAM, in which case a member of the TCB is used to record whether the + * stack and/or TCB were allocated statically or dynamically, so when a task is + * deleted the RAM that was allocated dynamically is freed again and no attempt is + * made to free the RAM that was allocated statically. + * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE is only true if it is possible for a + * task to be created using either statically or dynamically allocated RAM. Note + * that if portUSING_MPU_WRAPPERS is 1 then a protected task can be created with + * a statically allocated stack and a dynamically allocated TCB. + * + * The following table lists various combinations of portUSING_MPU_WRAPPERS, + * configSUPPORT_DYNAMIC_ALLOCATION and configSUPPORT_STATIC_ALLOCATION and + * when it is possible to have both static and dynamic allocation: + * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+ + * | MPU | Dynamic | Static | Available Functions | Possible Allocations | Both Dynamic and | Need Free | + * | | | | | | Static Possible | | + * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+ + * | 0 | 0 | 1 | xTaskCreateStatic | TCB - Static, Stack - Static | No | No | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 0 | 1 | 0 | xTaskCreate | TCB - Dynamic, Stack - Dynamic | No | Yes | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 0 | 1 | 1 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes | + * | | | | xTaskCreateStatic | 2. TCB - Static, Stack - Static | | | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 1 | 0 | 1 | xTaskCreateStatic, | TCB - Static, Stack - Static | No | No | + * | | | | xTaskCreateRestrictedStatic | | | | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 1 | 1 | 0 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes | + * | | | | xTaskCreateRestricted | 2. TCB - Dynamic, Stack - Static | | | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 1 | 1 | 1 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes | + * | | | | xTaskCreateStatic, | 2. TCB - Dynamic, Stack - Static | | | + * | | | | xTaskCreateRestricted, | 3. TCB - Static, Stack - Static | | | + * | | | | xTaskCreateRestrictedStatic | | | | + * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+ + */ +#define tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE \ + ( ( ( portUSING_MPU_WRAPPERS == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) || \ + ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) ) + +/* + * In line with software engineering best practice, FreeRTOS implements a strict + * data hiding policy, so the real structures used by FreeRTOS to maintain the + * state of tasks, queues, semaphores, etc. are not accessible to the application + * code. However, if the application writer wants to statically allocate such + * an object then the size of the object needs to be known. Dummy structures + * that are guaranteed to have the same size and alignment requirements of the + * real objects are used for this purpose. The dummy list and list item + * structures below are used for inclusion in such a dummy structure. + */ +struct xSTATIC_LIST_ITEM +{ + #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy1; + #endif + TickType_t xDummy2; + void * pvDummy3[ 4 ]; + #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy4; + #endif +}; +typedef struct xSTATIC_LIST_ITEM StaticListItem_t; + +#if ( configUSE_MINI_LIST_ITEM == 1 ) + /* See the comments above the struct xSTATIC_LIST_ITEM definition. */ + struct xSTATIC_MINI_LIST_ITEM + { + #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy1; + #endif + TickType_t xDummy2; + void * pvDummy3[ 2 ]; + }; + typedef struct xSTATIC_MINI_LIST_ITEM StaticMiniListItem_t; +#else /* if ( configUSE_MINI_LIST_ITEM == 1 ) */ + typedef struct xSTATIC_LIST_ITEM StaticMiniListItem_t; +#endif /* if ( configUSE_MINI_LIST_ITEM == 1 ) */ + +/* See the comments above the struct xSTATIC_LIST_ITEM definition. */ +typedef struct xSTATIC_LIST +{ + #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy1; + #endif + UBaseType_t uxDummy2; + void * pvDummy3; + StaticMiniListItem_t xDummy4; + #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy5; + #endif +} StaticList_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the Task structure used internally by + * FreeRTOS is not accessible to application code. However, if the application + * writer wants to statically allocate the memory required to create a task then + * the size of the task object needs to be known. The StaticTask_t structure + * below is provided for this purpose. Its sizes and alignment requirements are + * guaranteed to match those of the genuine structure, no matter which + * architecture is being used, and no matter how the values in FreeRTOSConfig.h + * are set. Its contents are somewhat obfuscated in the hope users will + * recognise that it would be unwise to make direct use of the structure members. + */ +typedef struct xSTATIC_TCB +{ + void * pxDummy1; + #if ( portUSING_MPU_WRAPPERS == 1 ) + xMPU_SETTINGS xDummy2; + #endif + #if ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) + UBaseType_t uxDummy26; + #endif + StaticListItem_t xDummy3[ 2 ]; + UBaseType_t uxDummy5; + void * pxDummy6; + #if ( configNUMBER_OF_CORES > 1 ) + BaseType_t xDummy23; + UBaseType_t uxDummy24; + #endif + uint8_t ucDummy7[ configMAX_TASK_NAME_LEN ]; + #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 ) + BaseType_t xDummy25; + #endif + #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) ) + void * pxDummy8; + #endif + #if ( portCRITICAL_NESTING_IN_TCB == 1 ) + UBaseType_t uxDummy9; + #endif + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy10[ 2 ]; + #endif + #if ( configUSE_MUTEXES == 1 ) + UBaseType_t uxDummy12[ 2 ]; + #endif + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + void * pxDummy14; + #endif + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 ) + void * pvDummy15[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ]; + #endif + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + configRUN_TIME_COUNTER_TYPE ulDummy16; + #endif + #if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) + configTLS_BLOCK_TYPE xDummy17; + #endif + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + uint32_t ulDummy18[ configTASK_NOTIFICATION_ARRAY_ENTRIES ]; + uint8_t ucDummy19[ configTASK_NOTIFICATION_ARRAY_ENTRIES ]; + #endif + #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) + uint8_t uxDummy20; + #endif + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + uint8_t ucDummy21; + #endif + #if ( configUSE_POSIX_ERRNO == 1 ) + int iDummy22; + #endif +} StaticTask_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the Queue structure used internally by + * FreeRTOS is not accessible to application code. However, if the application + * writer wants to statically allocate the memory required to create a queue + * then the size of the queue object needs to be known. The StaticQueue_t + * structure below is provided for this purpose. Its sizes and alignment + * requirements are guaranteed to match those of the genuine structure, no + * matter which architecture is being used, and no matter how the values in + * FreeRTOSConfig.h are set. Its contents are somewhat obfuscated in the hope + * users will recognise that it would be unwise to make direct use of the + * structure members. + */ +typedef struct xSTATIC_QUEUE +{ + void * pvDummy1[ 3 ]; + + union + { + void * pvDummy2; + UBaseType_t uxDummy2; + } u; + + StaticList_t xDummy3[ 2 ]; + UBaseType_t uxDummy4[ 3 ]; + uint8_t ucDummy5[ 2 ]; + + #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucDummy6; + #endif + + #if ( configUSE_QUEUE_SETS == 1 ) + void * pvDummy7; + #endif + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy8; + uint8_t ucDummy9; + #endif +} StaticQueue_t; +typedef StaticQueue_t StaticSemaphore_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the event group structure used + * internally by FreeRTOS is not accessible to application code. However, if + * the application writer wants to statically allocate the memory required to + * create an event group then the size of the event group object needs to be + * know. The StaticEventGroup_t structure below is provided for this purpose. + * Its sizes and alignment requirements are guaranteed to match those of the + * genuine structure, no matter which architecture is being used, and no matter + * how the values in FreeRTOSConfig.h are set. Its contents are somewhat + * obfuscated in the hope users will recognise that it would be unwise to make + * direct use of the structure members. + */ +typedef struct xSTATIC_EVENT_GROUP +{ + TickType_t xDummy1; + StaticList_t xDummy2; + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy3; + #endif + + #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucDummy4; + #endif +} StaticEventGroup_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the software timer structure used + * internally by FreeRTOS is not accessible to application code. However, if + * the application writer wants to statically allocate the memory required to + * create a software timer then the size of the queue object needs to be known. + * The StaticTimer_t structure below is provided for this purpose. Its sizes + * and alignment requirements are guaranteed to match those of the genuine + * structure, no matter which architecture is being used, and no matter how the + * values in FreeRTOSConfig.h are set. Its contents are somewhat obfuscated in + * the hope users will recognise that it would be unwise to make direct use of + * the structure members. + */ +typedef struct xSTATIC_TIMER +{ + void * pvDummy1; + StaticListItem_t xDummy2; + TickType_t xDummy3; + void * pvDummy5; + TaskFunction_t pvDummy6; + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy7; + #endif + uint8_t ucDummy8; +} StaticTimer_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the stream buffer structure used + * internally by FreeRTOS is not accessible to application code. However, if + * the application writer wants to statically allocate the memory required to + * create a stream buffer then the size of the stream buffer object needs to be + * known. The StaticStreamBuffer_t structure below is provided for this + * purpose. Its size and alignment requirements are guaranteed to match those + * of the genuine structure, no matter which architecture is being used, and + * no matter how the values in FreeRTOSConfig.h are set. Its contents are + * somewhat obfuscated in the hope users will recognise that it would be unwise + * to make direct use of the structure members. + */ +typedef struct xSTATIC_STREAM_BUFFER +{ + size_t uxDummy1[ 4 ]; + void * pvDummy2[ 3 ]; + uint8_t ucDummy3; + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy4; + #endif + #if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) + void * pvDummy5[ 2 ]; + #endif + UBaseType_t uxDummy6; +} StaticStreamBuffer_t; + +/* Message buffers are built on stream buffers. */ +typedef StaticStreamBuffer_t StaticMessageBuffer_t; + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* INC_FREERTOS_H */ diff --git a/include/StackMacros.h b/include/StackMacros.h new file mode 100644 index 000000000..d0c624733 --- /dev/null +++ b/include/StackMacros.h @@ -0,0 +1,34 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef _MSC_VER /* Visual Studio doesn't support #warning. */ + #warning The name of this file has changed to stack_macros.h. Please update your code accordingly. This source file (which has the original name) will be removed in a future release. +#endif + +#include "stack_macros.h" diff --git a/include/atomic.h b/include/atomic.h new file mode 100644 index 000000000..335a77fdf --- /dev/null +++ b/include/atomic.h @@ -0,0 +1,427 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/** + * @file atomic.h + * @brief FreeRTOS atomic operation support. + * + * This file implements atomic functions by disabling interrupts globally. + * Implementations with architecture specific atomic instructions can be + * provided under each compiler directory. + * + * The atomic interface can be used in FreeRTOS tasks on all FreeRTOS ports. It + * can also be used in Interrupt Service Routines (ISRs) on FreeRTOS ports that + * support nested interrupts (i.e. portHAS_NESTED_INTERRUPTS is set to 1). The + * atomic interface must not be used in ISRs on FreeRTOS ports that do not + * support nested interrupts (i.e. portHAS_NESTED_INTERRUPTS is set to 0) + * because ISRs on these ports cannot be interrupted and therefore, do not need + * atomics in ISRs. + */ + +#ifndef ATOMIC_H +#define ATOMIC_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include atomic.h" +#endif + +/* Standard includes. */ +#include + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/* + * Port specific definitions -- entering/exiting critical section. + * Refer template -- ./lib/FreeRTOS/portable/Compiler/Arch/portmacro.h + * + * Every call to ATOMIC_EXIT_CRITICAL() must be closely paired with + * ATOMIC_ENTER_CRITICAL(). + * + */ +#if ( portHAS_NESTED_INTERRUPTS == 1 ) + +/* Nested interrupt scheme is supported in this port. */ + #define ATOMIC_ENTER_CRITICAL() \ + UBaseType_t uxCriticalSectionType = portSET_INTERRUPT_MASK_FROM_ISR() + + #define ATOMIC_EXIT_CRITICAL() \ + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxCriticalSectionType ) + +#else + +/* Nested interrupt scheme is NOT supported in this port. */ + #define ATOMIC_ENTER_CRITICAL() portENTER_CRITICAL() + #define ATOMIC_EXIT_CRITICAL() portEXIT_CRITICAL() + +#endif /* portSET_INTERRUPT_MASK_FROM_ISR() */ + +/* + * Port specific definition -- "always inline". + * Inline is compiler specific, and may not always get inlined depending on your + * optimization level. Also, inline is considered as performance optimization + * for atomic. Thus, if portFORCE_INLINE is not provided by portmacro.h, + * instead of resulting error, simply define it away. + */ +#ifndef portFORCE_INLINE + #define portFORCE_INLINE +#endif + +#define ATOMIC_COMPARE_AND_SWAP_SUCCESS 0x1U /**< Compare and swap succeeded, swapped. */ +#define ATOMIC_COMPARE_AND_SWAP_FAILURE 0x0U /**< Compare and swap failed, did not swap. */ + +/*----------------------------- Swap && CAS ------------------------------*/ + +/** + * Atomic compare-and-swap + * + * @brief Performs an atomic compare-and-swap operation on the specified values. + * + * @param[in, out] pulDestination Pointer to memory location from where value is + * to be loaded and checked. + * @param[in] ulExchange If condition meets, write this value to memory. + * @param[in] ulComparand Swap condition. + * + * @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped. + * + * @note This function only swaps *pulDestination with ulExchange, if previous + * *pulDestination value equals ulComparand. + */ +static portFORCE_INLINE uint32_t Atomic_CompareAndSwap_u32( uint32_t volatile * pulDestination, + uint32_t ulExchange, + uint32_t ulComparand ) +{ + uint32_t ulReturnValue; + + ATOMIC_ENTER_CRITICAL(); + { + if( *pulDestination == ulComparand ) + { + *pulDestination = ulExchange; + ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS; + } + else + { + ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE; + } + } + ATOMIC_EXIT_CRITICAL(); + + return ulReturnValue; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic swap (pointers) + * + * @brief Atomically sets the address pointed to by *ppvDestination to the value + * of *pvExchange. + * + * @param[in, out] ppvDestination Pointer to memory location from where a pointer + * value is to be loaded and written back to. + * @param[in] pvExchange Pointer value to be written to *ppvDestination. + * + * @return The initial value of *ppvDestination. + */ +static portFORCE_INLINE void * Atomic_SwapPointers_p32( void * volatile * ppvDestination, + void * pvExchange ) +{ + void * pReturnValue; + + ATOMIC_ENTER_CRITICAL(); + { + pReturnValue = *ppvDestination; + *ppvDestination = pvExchange; + } + ATOMIC_EXIT_CRITICAL(); + + return pReturnValue; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic compare-and-swap (pointers) + * + * @brief Performs an atomic compare-and-swap operation on the specified pointer + * values. + * + * @param[in, out] ppvDestination Pointer to memory location from where a pointer + * value is to be loaded and checked. + * @param[in] pvExchange If condition meets, write this value to memory. + * @param[in] pvComparand Swap condition. + * + * @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped. + * + * @note This function only swaps *ppvDestination with pvExchange, if previous + * *ppvDestination value equals pvComparand. + */ +static portFORCE_INLINE uint32_t Atomic_CompareAndSwapPointers_p32( void * volatile * ppvDestination, + void * pvExchange, + void * pvComparand ) +{ + uint32_t ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE; + + ATOMIC_ENTER_CRITICAL(); + { + if( *ppvDestination == pvComparand ) + { + *ppvDestination = pvExchange; + ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS; + } + } + ATOMIC_EXIT_CRITICAL(); + + return ulReturnValue; +} + + +/*----------------------------- Arithmetic ------------------------------*/ + +/** + * Atomic add + * + * @brief Atomically adds count to the value of the specified pointer points to. + * + * @param[in,out] pulAddend Pointer to memory location from where value is to be + * loaded and written back to. + * @param[in] ulCount Value to be added to *pulAddend. + * + * @return previous *pulAddend value. + */ +static portFORCE_INLINE uint32_t Atomic_Add_u32( uint32_t volatile * pulAddend, + uint32_t ulCount ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulAddend; + *pulAddend += ulCount; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic subtract + * + * @brief Atomically subtracts count from the value of the specified pointer + * pointers to. + * + * @param[in,out] pulAddend Pointer to memory location from where value is to be + * loaded and written back to. + * @param[in] ulCount Value to be subtract from *pulAddend. + * + * @return previous *pulAddend value. + */ +static portFORCE_INLINE uint32_t Atomic_Subtract_u32( uint32_t volatile * pulAddend, + uint32_t ulCount ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulAddend; + *pulAddend -= ulCount; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic increment + * + * @brief Atomically increments the value of the specified pointer points to. + * + * @param[in,out] pulAddend Pointer to memory location from where value is to be + * loaded and written back to. + * + * @return *pulAddend value before increment. + */ +static portFORCE_INLINE uint32_t Atomic_Increment_u32( uint32_t volatile * pulAddend ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulAddend; + *pulAddend += 1; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic decrement + * + * @brief Atomically decrements the value of the specified pointer points to + * + * @param[in,out] pulAddend Pointer to memory location from where value is to be + * loaded and written back to. + * + * @return *pulAddend value before decrement. + */ +static portFORCE_INLINE uint32_t Atomic_Decrement_u32( uint32_t volatile * pulAddend ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulAddend; + *pulAddend -= 1; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} + +/*----------------------------- Bitwise Logical ------------------------------*/ + +/** + * Atomic OR + * + * @brief Performs an atomic OR operation on the specified values. + * + * @param [in, out] pulDestination Pointer to memory location from where value is + * to be loaded and written back to. + * @param [in] ulValue Value to be ORed with *pulDestination. + * + * @return The original value of *pulDestination. + */ +static portFORCE_INLINE uint32_t Atomic_OR_u32( uint32_t volatile * pulDestination, + uint32_t ulValue ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulDestination; + *pulDestination |= ulValue; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic AND + * + * @brief Performs an atomic AND operation on the specified values. + * + * @param [in, out] pulDestination Pointer to memory location from where value is + * to be loaded and written back to. + * @param [in] ulValue Value to be ANDed with *pulDestination. + * + * @return The original value of *pulDestination. + */ +static portFORCE_INLINE uint32_t Atomic_AND_u32( uint32_t volatile * pulDestination, + uint32_t ulValue ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulDestination; + *pulDestination &= ulValue; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic NAND + * + * @brief Performs an atomic NAND operation on the specified values. + * + * @param [in, out] pulDestination Pointer to memory location from where value is + * to be loaded and written back to. + * @param [in] ulValue Value to be NANDed with *pulDestination. + * + * @return The original value of *pulDestination. + */ +static portFORCE_INLINE uint32_t Atomic_NAND_u32( uint32_t volatile * pulDestination, + uint32_t ulValue ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulDestination; + *pulDestination = ~( ulCurrent & ulValue ); + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic XOR + * + * @brief Performs an atomic XOR operation on the specified values. + * + * @param [in, out] pulDestination Pointer to memory location from where value is + * to be loaded and written back to. + * @param [in] ulValue Value to be XORed with *pulDestination. + * + * @return The original value of *pulDestination. + */ +static portFORCE_INLINE uint32_t Atomic_XOR_u32( uint32_t volatile * pulDestination, + uint32_t ulValue ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulDestination; + *pulDestination ^= ulValue; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* ATOMIC_H */ diff --git a/include/croutine.h b/include/croutine.h new file mode 100644 index 000000000..a5e2e4462 --- /dev/null +++ b/include/croutine.h @@ -0,0 +1,765 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef CO_ROUTINE_H +#define CO_ROUTINE_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include croutine.h" +#endif + +#include "list.h" + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/* Used to hide the implementation of the co-routine control block. The + * control block structure however has to be included in the header due to + * the macro implementation of the co-routine functionality. */ +typedef void * CoRoutineHandle_t; + +/* Defines the prototype to which co-routine functions must conform. */ +typedef void (* crCOROUTINE_CODE)( CoRoutineHandle_t xHandle, + UBaseType_t uxIndex ); + +typedef struct corCoRoutineControlBlock +{ + crCOROUTINE_CODE pxCoRoutineFunction; + ListItem_t xGenericListItem; /**< List item used to place the CRCB in ready and blocked queues. */ + ListItem_t xEventListItem; /**< List item used to place the CRCB in event lists. */ + UBaseType_t uxPriority; /**< The priority of the co-routine in relation to other co-routines. */ + UBaseType_t uxIndex; /**< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */ + uint16_t uxState; /**< Used internally by the co-routine implementation. */ +} CRCB_t; /* Co-routine control block. Note must be identical in size down to uxPriority with TCB_t. */ + +/** + * croutine. h + * @code{c} + * BaseType_t xCoRoutineCreate( + * crCOROUTINE_CODE pxCoRoutineCode, + * UBaseType_t uxPriority, + * UBaseType_t uxIndex + * ); + * @endcode + * + * Create a new co-routine and add it to the list of co-routines that are + * ready to run. + * + * @param pxCoRoutineCode Pointer to the co-routine function. Co-routine + * functions require special syntax - see the co-routine section of the WEB + * documentation for more information. + * + * @param uxPriority The priority with respect to other co-routines at which + * the co-routine will run. + * + * @param uxIndex Used to distinguish between different co-routines that + * execute the same function. See the example below and the co-routine section + * of the WEB documentation for further information. + * + * @return pdPASS if the co-routine was successfully created and added to a ready + * list, otherwise an error code defined with ProjDefs.h. + * + * Example usage: + * @code{c} + * // Co-routine to be created. + * void vFlashCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex ) + * { + * // Variables in co-routines must be declared static if they must maintain value across a blocking call. + * // This may not be necessary for const variables. + * static const char cLedToFlash[ 2 ] = { 5, 6 }; + * static const TickType_t uxFlashRates[ 2 ] = { 200, 400 }; + * + * // Must start every co-routine with a call to crSTART(); + * crSTART( xHandle ); + * + * for( ;; ) + * { + * // This co-routine just delays for a fixed period, then toggles + * // an LED. Two co-routines are created using this function, so + * // the uxIndex parameter is used to tell the co-routine which + * // LED to flash and how int32_t to delay. This assumes xQueue has + * // already been created. + * vParTestToggleLED( cLedToFlash[ uxIndex ] ); + * crDELAY( xHandle, uxFlashRates[ uxIndex ] ); + * } + * + * // Must end every co-routine with a call to crEND(); + * crEND(); + * } + * + * // Function that creates two co-routines. + * void vOtherFunction( void ) + * { + * uint8_t ucParameterToPass; + * TaskHandle_t xHandle; + * + * // Create two co-routines at priority 0. The first is given index 0 + * // so (from the code above) toggles LED 5 every 200 ticks. The second + * // is given index 1 so toggles LED 6 every 400 ticks. + * for( uxIndex = 0; uxIndex < 2; uxIndex++ ) + * { + * xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex ); + * } + * } + * @endcode + * \defgroup xCoRoutineCreate xCoRoutineCreate + * \ingroup Tasks + */ +BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, + UBaseType_t uxPriority, + UBaseType_t uxIndex ); + + +/** + * croutine. h + * @code{c} + * void vCoRoutineSchedule( void ); + * @endcode + * + * Run a co-routine. + * + * vCoRoutineSchedule() executes the highest priority co-routine that is able + * to run. The co-routine will execute until it either blocks, yields or is + * preempted by a task. Co-routines execute cooperatively so one + * co-routine cannot be preempted by another, but can be preempted by a task. + * + * If an application comprises of both tasks and co-routines then + * vCoRoutineSchedule should be called from the idle task (in an idle task + * hook). + * + * Example usage: + * @code{c} + * // This idle task hook will schedule a co-routine each time it is called. + * // The rest of the idle task will execute between co-routine calls. + * void vApplicationIdleHook( void ) + * { + * vCoRoutineSchedule(); + * } + * + * // Alternatively, if you do not require any other part of the idle task to + * // execute, the idle task hook can call vCoRoutineSchedule() within an + * // infinite loop. + * void vApplicationIdleHook( void ) + * { + * for( ;; ) + * { + * vCoRoutineSchedule(); + * } + * } + * @endcode + * \defgroup vCoRoutineSchedule vCoRoutineSchedule + * \ingroup Tasks + */ +void vCoRoutineSchedule( void ); + +/** + * croutine. h + * @code{c} + * crSTART( CoRoutineHandle_t xHandle ); + * @endcode + * + * This macro MUST always be called at the start of a co-routine function. + * + * Example usage: + * @code{c} + * // Co-routine to be created. + * void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex ) + * { + * // Variables in co-routines must be declared static if they must maintain value across a blocking call. + * static int32_t ulAVariable; + * + * // Must start every co-routine with a call to crSTART(); + * crSTART( xHandle ); + * + * for( ;; ) + * { + * // Co-routine functionality goes here. + * } + * + * // Must end every co-routine with a call to crEND(); + * crEND(); + * } + * @endcode + * \defgroup crSTART crSTART + * \ingroup Tasks + */ +#define crSTART( pxCRCB ) \ + switch( ( ( CRCB_t * ) ( pxCRCB ) )->uxState ) { \ + case 0: + +/** + * croutine. h + * @code{c} + * crEND(); + * @endcode + * + * This macro MUST always be called at the end of a co-routine function. + * + * Example usage: + * @code{c} + * // Co-routine to be created. + * void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex ) + * { + * // Variables in co-routines must be declared static if they must maintain value across a blocking call. + * static int32_t ulAVariable; + * + * // Must start every co-routine with a call to crSTART(); + * crSTART( xHandle ); + * + * for( ;; ) + * { + * // Co-routine functionality goes here. + * } + * + * // Must end every co-routine with a call to crEND(); + * crEND(); + * } + * @endcode + * \defgroup crSTART crSTART + * \ingroup Tasks + */ + +/* *INDENT-OFF* */ +#define crEND() } +/* *INDENT-ON* */ + +/* + * These macros are intended for internal use by the co-routine implementation + * only. The macros should not be used directly by application writers. + */ +#define crSET_STATE0( xHandle ) \ + ( ( CRCB_t * ) ( xHandle ) )->uxState = ( __LINE__ * 2 ); return; \ + case ( __LINE__ * 2 ): +#define crSET_STATE1( xHandle ) \ + ( ( CRCB_t * ) ( xHandle ) )->uxState = ( ( __LINE__ * 2 ) + 1 ); return; \ + case ( ( __LINE__ * 2 ) + 1 ): + +/** + * croutine. h + * @code{c} + * crDELAY( CoRoutineHandle_t xHandle, TickType_t xTicksToDelay ); + * @endcode + * + * Delay a co-routine for a fixed period of time. + * + * crDELAY can only be called from the co-routine function itself - not + * from within a function called by the co-routine function. This is because + * co-routines do not maintain their own stack. + * + * @param xHandle The handle of the co-routine to delay. This is the xHandle + * parameter of the co-routine function. + * + * @param xTickToDelay The number of ticks that the co-routine should delay + * for. The actual amount of time this equates to is defined by + * configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant portTICK_PERIOD_MS + * can be used to convert ticks to milliseconds. + * + * Example usage: + * @code{c} + * // Co-routine to be created. + * void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex ) + * { + * // Variables in co-routines must be declared static if they must maintain value across a blocking call. + * // This may not be necessary for const variables. + * // We are to delay for 200ms. + * static const xTickType xDelayTime = 200 / portTICK_PERIOD_MS; + * + * // Must start every co-routine with a call to crSTART(); + * crSTART( xHandle ); + * + * for( ;; ) + * { + * // Delay for 200ms. + * crDELAY( xHandle, xDelayTime ); + * + * // Do something here. + * } + * + * // Must end every co-routine with a call to crEND(); + * crEND(); + * } + * @endcode + * \defgroup crDELAY crDELAY + * \ingroup Tasks + */ +#define crDELAY( xHandle, xTicksToDelay ) \ + do { \ + if( ( xTicksToDelay ) > 0 ) \ + { \ + vCoRoutineAddToDelayedList( ( xTicksToDelay ), NULL ); \ + } \ + crSET_STATE0( ( xHandle ) ); \ + } while( 0 ) + +/** + * @code{c} + * crQUEUE_SEND( + * CoRoutineHandle_t xHandle, + * QueueHandle_t pxQueue, + * void *pvItemToQueue, + * TickType_t xTicksToWait, + * BaseType_t *pxResult + * ) + * @endcode + * + * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine + * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. + * + * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas + * xQueueSend() and xQueueReceive() can only be used from tasks. + * + * crQUEUE_SEND can only be called from the co-routine function itself - not + * from within a function called by the co-routine function. This is because + * co-routines do not maintain their own stack. + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xHandle The handle of the calling co-routine. This is the xHandle + * parameter of the co-routine function. + * + * @param pxQueue The handle of the queue on which the data will be posted. + * The handle is obtained as the return value when the queue is created using + * the xQueueCreate() API function. + * + * @param pvItemToQueue A pointer to the data being posted onto the queue. + * The number of bytes of each queued item is specified when the queue is + * created. This number of bytes is copied from pvItemToQueue into the queue + * itself. + * + * @param xTickToDelay The number of ticks that the co-routine should block + * to wait for space to become available on the queue, should space not be + * available immediately. The actual amount of time this equates to is defined + * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant + * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see example + * below). + * + * @param pxResult The variable pointed to by pxResult will be set to pdPASS if + * data was successfully posted onto the queue, otherwise it will be set to an + * error defined within ProjDefs.h. + * + * Example usage: + * @code{c} + * // Co-routine function that blocks for a fixed period then posts a number onto + * // a queue. + * static void prvCoRoutineFlashTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex ) + * { + * // Variables in co-routines must be declared static if they must maintain value across a blocking call. + * static BaseType_t xNumberToPost = 0; + * static BaseType_t xResult; + * + * // Co-routines must begin with a call to crSTART(). + * crSTART( xHandle ); + * + * for( ;; ) + * { + * // This assumes the queue has already been created. + * crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult ); + * + * if( xResult != pdPASS ) + * { + * // The message was not posted! + * } + * + * // Increment the number to be posted onto the queue. + * xNumberToPost++; + * + * // Delay for 100 ticks. + * crDELAY( xHandle, 100 ); + * } + * + * // Co-routines must end with a call to crEND(). + * crEND(); + * } + * @endcode + * \defgroup crQUEUE_SEND crQUEUE_SEND + * \ingroup Tasks + */ +#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult ) \ + do { \ + *( pxResult ) = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), ( xTicksToWait ) ); \ + if( *( pxResult ) == errQUEUE_BLOCKED ) \ + { \ + crSET_STATE0( ( xHandle ) ); \ + *pxResult = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), 0 ); \ + } \ + if( *pxResult == errQUEUE_YIELD ) \ + { \ + crSET_STATE1( ( xHandle ) ); \ + *pxResult = pdPASS; \ + } \ + } while( 0 ) + +/** + * croutine. h + * @code{c} + * crQUEUE_RECEIVE( + * CoRoutineHandle_t xHandle, + * QueueHandle_t pxQueue, + * void *pvBuffer, + * TickType_t xTicksToWait, + * BaseType_t *pxResult + * ) + * @endcode + * + * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine + * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. + * + * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas + * xQueueSend() and xQueueReceive() can only be used from tasks. + * + * crQUEUE_RECEIVE can only be called from the co-routine function itself - not + * from within a function called by the co-routine function. This is because + * co-routines do not maintain their own stack. + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xHandle The handle of the calling co-routine. This is the xHandle + * parameter of the co-routine function. + * + * @param pxQueue The handle of the queue from which the data will be received. + * The handle is obtained as the return value when the queue is created using + * the xQueueCreate() API function. + * + * @param pvBuffer The buffer into which the received item is to be copied. + * The number of bytes of each queued item is specified when the queue is + * created. This number of bytes is copied into pvBuffer. + * + * @param xTickToDelay The number of ticks that the co-routine should block + * to wait for data to become available from the queue, should data not be + * available immediately. The actual amount of time this equates to is defined + * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant + * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see the + * crQUEUE_SEND example). + * + * @param pxResult The variable pointed to by pxResult will be set to pdPASS if + * data was successfully retrieved from the queue, otherwise it will be set to + * an error code as defined within ProjDefs.h. + * + * Example usage: + * @code{c} + * // A co-routine receives the number of an LED to flash from a queue. It + * // blocks on the queue until the number is received. + * static void prvCoRoutineFlashWorkTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex ) + * { + * // Variables in co-routines must be declared static if they must maintain value across a blocking call. + * static BaseType_t xResult; + * static UBaseType_t uxLEDToFlash; + * + * // All co-routines must start with a call to crSTART(). + * crSTART( xHandle ); + * + * for( ;; ) + * { + * // Wait for data to become available on the queue. + * crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult ); + * + * if( xResult == pdPASS ) + * { + * // We received the LED to flash - flash it! + * vParTestToggleLED( uxLEDToFlash ); + * } + * } + * + * crEND(); + * } + * @endcode + * \defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE + * \ingroup Tasks + */ +#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult ) \ + do { \ + *( pxResult ) = xQueueCRReceive( ( pxQueue ), ( pvBuffer ), ( xTicksToWait ) ); \ + if( *( pxResult ) == errQUEUE_BLOCKED ) \ + { \ + crSET_STATE0( ( xHandle ) ); \ + *( pxResult ) = xQueueCRReceive( ( pxQueue ), ( pvBuffer ), 0 ); \ + } \ + if( *( pxResult ) == errQUEUE_YIELD ) \ + { \ + crSET_STATE1( ( xHandle ) ); \ + *( pxResult ) = pdPASS; \ + } \ + } while( 0 ) + +/** + * croutine. h + * @code{c} + * crQUEUE_SEND_FROM_ISR( + * QueueHandle_t pxQueue, + * void *pvItemToQueue, + * BaseType_t xCoRoutinePreviouslyWoken + * ) + * @endcode + * + * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the + * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() + * functions used by tasks. + * + * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to + * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and + * xQueueReceiveFromISR() can only be used to pass data between a task and and + * ISR. + * + * crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue + * that is being used from within a co-routine. + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto + * the same queue multiple times from a single interrupt. The first call + * should always pass in pdFALSE. Subsequent calls should pass in + * the value returned from the previous call. + * + * @return pdTRUE if a co-routine was woken by posting onto the queue. This is + * used by the ISR to determine if a context switch may be required following + * the ISR. + * + * Example usage: + * @code{c} + * // A co-routine that blocks on a queue waiting for characters to be received. + * static void vReceivingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex ) + * { + * char cRxedChar; + * BaseType_t xResult; + * + * // All co-routines must start with a call to crSTART(). + * crSTART( xHandle ); + * + * for( ;; ) + * { + * // Wait for data to become available on the queue. This assumes the + * // queue xCommsRxQueue has already been created! + * crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult ); + * + * // Was a character received? + * if( xResult == pdPASS ) + * { + * // Process the character here. + * } + * } + * + * // All co-routines must end with a call to crEND(). + * crEND(); + * } + * + * // An ISR that uses a queue to send characters received on a serial port to + * // a co-routine. + * void vUART_ISR( void ) + * { + * char cRxedChar; + * BaseType_t xCRWokenByPost = pdFALSE; + * + * // We loop around reading characters until there are none left in the UART. + * while( UART_RX_REG_NOT_EMPTY() ) + * { + * // Obtain the character from the UART. + * cRxedChar = UART_RX_REG; + * + * // Post the character onto a queue. xCRWokenByPost will be pdFALSE + * // the first time around the loop. If the post causes a co-routine + * // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE. + * // In this manner we can ensure that if more than one co-routine is + * // blocked on the queue only one is woken by this ISR no matter how + * // many characters are posted to the queue. + * xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost ); + * } + * } + * @endcode + * \defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR + * \ingroup Tasks + */ +#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) \ + xQueueCRSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( xCoRoutinePreviouslyWoken ) ) + + +/** + * croutine. h + * @code{c} + * crQUEUE_SEND_FROM_ISR( + * QueueHandle_t pxQueue, + * void *pvBuffer, + * BaseType_t * pxCoRoutineWoken + * ) + * @endcode + * + * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the + * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() + * functions used by tasks. + * + * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to + * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and + * xQueueReceiveFromISR() can only be used to pass data between a task and and + * ISR. + * + * crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data + * from a queue that is being used from within a co-routine (a co-routine + * posted to the queue). + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvBuffer A pointer to a buffer into which the received item will be + * placed. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from the queue into + * pvBuffer. + * + * @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become + * available on the queue. If crQUEUE_RECEIVE_FROM_ISR causes such a + * co-routine to unblock *pxCoRoutineWoken will get set to pdTRUE, otherwise + * *pxCoRoutineWoken will remain unchanged. + * + * @return pdTRUE an item was successfully received from the queue, otherwise + * pdFALSE. + * + * Example usage: + * @code{c} + * // A co-routine that posts a character to a queue then blocks for a fixed + * // period. The character is incremented each time. + * static void vSendingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex ) + * { + * // cChar holds its value while this co-routine is blocked and must therefore + * // be declared static. + * static char cCharToTx = 'a'; + * BaseType_t xResult; + * + * // All co-routines must start with a call to crSTART(). + * crSTART( xHandle ); + * + * for( ;; ) + * { + * // Send the next character to the queue. + * crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult ); + * + * if( xResult == pdPASS ) + * { + * // The character was successfully posted to the queue. + * } + * else + * { + * // Could not post the character to the queue. + * } + * + * // Enable the UART Tx interrupt to cause an interrupt in this + * // hypothetical UART. The interrupt will obtain the character + * // from the queue and send it. + * ENABLE_RX_INTERRUPT(); + * + * // Increment to the next character then block for a fixed period. + * // cCharToTx will maintain its value across the delay as it is + * // declared static. + * cCharToTx++; + * if( cCharToTx > 'x' ) + * { + * cCharToTx = 'a'; + * } + * crDELAY( 100 ); + * } + * + * // All co-routines must end with a call to crEND(). + * crEND(); + * } + * + * // An ISR that uses a queue to receive characters to send on a UART. + * void vUART_ISR( void ) + * { + * char cCharToTx; + * BaseType_t xCRWokenByPost = pdFALSE; + * + * while( UART_TX_REG_EMPTY() ) + * { + * // Are there any characters in the queue waiting to be sent? + * // xCRWokenByPost will automatically be set to pdTRUE if a co-routine + * // is woken by the post - ensuring that only a single co-routine is + * // woken no matter how many times we go around this loop. + * if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) ) + * { + * SEND_CHARACTER( cCharToTx ); + * } + * } + * } + * @endcode + * \defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR + * \ingroup Tasks + */ +#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) \ + xQueueCRReceiveFromISR( ( pxQueue ), ( pvBuffer ), ( pxCoRoutineWoken ) ) + +/* + * This function is intended for internal use by the co-routine macros only. + * The macro nature of the co-routine implementation requires that the + * prototype appears here. The function should not be used by application + * writers. + * + * Removes the current co-routine from its ready list and places it in the + * appropriate delayed list. + */ +void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, + List_t * pxEventList ); + +/* + * This function is intended for internal use by the queue implementation only. + * The function should not be used by application writers. + * + * Removes the highest priority co-routine from the event list and places it in + * the pending ready list. + */ +BaseType_t xCoRoutineRemoveFromEventList( const List_t * pxEventList ); + + +/* + * This function resets the internal state of the coroutine module. It must be + * called by the application before restarting the scheduler. + */ +void vCoRoutineResetState( void ) PRIVILEGED_FUNCTION; + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* CO_ROUTINE_H */ diff --git a/include/deprecated_definitions.h b/include/deprecated_definitions.h new file mode 100644 index 000000000..edc0f2246 --- /dev/null +++ b/include/deprecated_definitions.h @@ -0,0 +1,281 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef DEPRECATED_DEFINITIONS_H +#define DEPRECATED_DEFINITIONS_H + + +/* Each FreeRTOS port has a unique portmacro.h header file. Originally a + * pre-processor definition was used to ensure the pre-processor found the correct + * portmacro.h file for the port being used. That scheme was deprecated in favour + * of setting the compiler's include path such that it found the correct + * portmacro.h file - removing the need for the constant and allowing the + * portmacro.h file to be located anywhere in relation to the port being used. The + * definitions below remain in the code for backward compatibility only. New + * projects should not use them. */ + +#ifdef OPEN_WATCOM_INDUSTRIAL_PC_PORT + #include "..\..\Source\portable\owatcom\16bitdos\pc\portmacro.h" + typedef void ( __interrupt __far * pxISR )(); +#endif + +#ifdef OPEN_WATCOM_FLASH_LITE_186_PORT + #include "..\..\Source\portable\owatcom\16bitdos\flsh186\portmacro.h" + typedef void ( __interrupt __far * pxISR )(); +#endif + +#ifdef GCC_MEGA_AVR + #include "../portable/GCC/ATMega323/portmacro.h" +#endif + +#ifdef IAR_MEGA_AVR + #include "../portable/IAR/ATMega323/portmacro.h" +#endif + +#ifdef MPLAB_PIC24_PORT + #include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h" +#endif + +#ifdef MPLAB_DSPIC_PORT + #include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h" +#endif + +#ifdef MPLAB_PIC18F_PORT + #include "../../Source/portable/MPLAB/PIC18F/portmacro.h" +#endif + +#ifdef MPLAB_PIC32MX_PORT + #include "../../Source/portable/MPLAB/PIC32MX/portmacro.h" +#endif + +#ifdef _FEDPICC + #include "libFreeRTOS/Include/portmacro.h" +#endif + +#ifdef SDCC_CYGNAL + #include "../../Source/portable/SDCC/Cygnal/portmacro.h" +#endif + +#ifdef GCC_ARM7 + #include "../../Source/portable/GCC/ARM7_LPC2000/portmacro.h" +#endif + +#ifdef GCC_ARM7_ECLIPSE + #include "portmacro.h" +#endif + +#ifdef ROWLEY_LPC23xx + #include "../../Source/portable/GCC/ARM7_LPC23xx/portmacro.h" +#endif + +#ifdef IAR_MSP430 + #include "..\..\Source\portable\IAR\MSP430\portmacro.h" +#endif + +#ifdef GCC_MSP430 + #include "../../Source/portable/GCC/MSP430F449/portmacro.h" +#endif + +#ifdef ROWLEY_MSP430 + #include "../../Source/portable/Rowley/MSP430F449/portmacro.h" +#endif + +#ifdef ARM7_LPC21xx_KEIL_RVDS + #include "..\..\Source\portable\RVDS\ARM7_LPC21xx\portmacro.h" +#endif + +#ifdef SAM7_GCC + #include "../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h" +#endif + +#ifdef SAM7_IAR + #include "..\..\Source\portable\IAR\AtmelSAM7S64\portmacro.h" +#endif + +#ifdef SAM9XE_IAR + #include "..\..\Source\portable\IAR\AtmelSAM9XE\portmacro.h" +#endif + +#ifdef LPC2000_IAR + #include "..\..\Source\portable\IAR\LPC2000\portmacro.h" +#endif + +#ifdef STR71X_IAR + #include "..\..\Source\portable\IAR\STR71x\portmacro.h" +#endif + +#ifdef STR75X_IAR + #include "..\..\Source\portable\IAR\STR75x\portmacro.h" +#endif + +#ifdef STR75X_GCC + #include "..\..\Source\portable\GCC\STR75x\portmacro.h" +#endif + +#ifdef STR91X_IAR + #include "..\..\Source\portable\IAR\STR91x\portmacro.h" +#endif + +#ifdef GCC_H8S + #include "../../Source/portable/GCC/H8S2329/portmacro.h" +#endif + +#ifdef GCC_AT91FR40008 + #include "../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h" +#endif + +#ifdef RVDS_ARMCM3_LM3S102 + #include "../../Source/portable/RVDS/ARM_CM3/portmacro.h" +#endif + +#ifdef GCC_ARMCM3_LM3S102 + #include "../../Source/portable/GCC/ARM_CM3/portmacro.h" +#endif + +#ifdef GCC_ARMCM3 + #include "../../Source/portable/GCC/ARM_CM3/portmacro.h" +#endif + +#ifdef IAR_ARM_CM3 + #include "../../Source/portable/IAR/ARM_CM3/portmacro.h" +#endif + +#ifdef IAR_ARMCM3_LM + #include "../../Source/portable/IAR/ARM_CM3/portmacro.h" +#endif + +#ifdef HCS12_CODE_WARRIOR + #include "../../Source/portable/CodeWarrior/HCS12/portmacro.h" +#endif + +#ifdef MICROBLAZE_GCC + #include "../../Source/portable/GCC/MicroBlaze/portmacro.h" +#endif + +#ifdef TERN_EE + #include "..\..\Source\portable\Paradigm\Tern_EE\small\portmacro.h" +#endif + +#ifdef GCC_HCS12 + #include "../../Source/portable/GCC/HCS12/portmacro.h" +#endif + +#ifdef GCC_MCF5235 + #include "../../Source/portable/GCC/MCF5235/portmacro.h" +#endif + +#ifdef COLDFIRE_V2_GCC + #include "../../../Source/portable/GCC/ColdFire_V2/portmacro.h" +#endif + +#ifdef COLDFIRE_V2_CODEWARRIOR + #include "../../Source/portable/CodeWarrior/ColdFire_V2/portmacro.h" +#endif + +#ifdef GCC_PPC405 + #include "../../Source/portable/GCC/PPC405_Xilinx/portmacro.h" +#endif + +#ifdef GCC_PPC440 + #include "../../Source/portable/GCC/PPC440_Xilinx/portmacro.h" +#endif + +#ifdef _16FX_SOFTUNE + #include "..\..\Source\portable\Softune\MB96340\portmacro.h" +#endif + +#ifdef BCC_INDUSTRIAL_PC_PORT + +/* A short file name has to be used in place of the normal + * FreeRTOSConfig.h when using the Borland compiler. */ + #include "frconfig.h" + #include "..\portable\BCC\16BitDOS\PC\prtmacro.h" + typedef void ( __interrupt __far * pxISR )(); +#endif + +#ifdef BCC_FLASH_LITE_186_PORT + +/* A short file name has to be used in place of the normal + * FreeRTOSConfig.h when using the Borland compiler. */ + #include "frconfig.h" + #include "..\portable\BCC\16BitDOS\flsh186\prtmacro.h" + typedef void ( __interrupt __far * pxISR )(); +#endif + +#ifdef __GNUC__ + #ifdef __AVR32_AVR32A__ + #include "portmacro.h" + #endif +#endif + +#ifdef __ICCAVR32__ + #ifdef __CORE__ + #if __CORE__ == __AVR32A__ + #include "portmacro.h" + #endif + #endif +#endif + +#ifdef __91467D + #include "portmacro.h" +#endif + +#ifdef __96340 + #include "portmacro.h" +#endif + + +#ifdef __IAR_V850ES_Fx3__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Jx3__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Jx3_L__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Jx2__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Hx2__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_78K0R_Kx3__ + #include "../../Source/portable/IAR/78K0R/portmacro.h" +#endif + +#ifdef __IAR_78K0R_Kx3L__ + #include "../../Source/portable/IAR/78K0R/portmacro.h" +#endif + +#endif /* DEPRECATED_DEFINITIONS_H */ diff --git a/include/event_groups.h b/include/event_groups.h new file mode 100644 index 000000000..d42c87b28 --- /dev/null +++ b/include/event_groups.h @@ -0,0 +1,848 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef EVENT_GROUPS_H +#define EVENT_GROUPS_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h" must appear in source files before "include event_groups.h" +#endif + +/* FreeRTOS includes. */ +#include "timers.h" + +/* The following bit fields convey control information in a task's event list + * item value. It is important they don't clash with the + * taskEVENT_LIST_ITEM_VALUE_IN_USE definition. */ +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + #define eventCLEAR_EVENTS_ON_EXIT_BIT ( ( uint16_t ) 0x0100U ) + #define eventUNBLOCKED_DUE_TO_BIT_SET ( ( uint16_t ) 0x0200U ) + #define eventWAIT_FOR_ALL_BITS ( ( uint16_t ) 0x0400U ) + #define eventEVENT_BITS_CONTROL_BYTES ( ( uint16_t ) 0xff00U ) +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + #define eventCLEAR_EVENTS_ON_EXIT_BIT ( ( uint32_t ) 0x01000000U ) + #define eventUNBLOCKED_DUE_TO_BIT_SET ( ( uint32_t ) 0x02000000U ) + #define eventWAIT_FOR_ALL_BITS ( ( uint32_t ) 0x04000000U ) + #define eventEVENT_BITS_CONTROL_BYTES ( ( uint32_t ) 0xff000000U ) +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_64_BITS ) + #define eventCLEAR_EVENTS_ON_EXIT_BIT ( ( uint64_t ) 0x0100000000000000U ) + #define eventUNBLOCKED_DUE_TO_BIT_SET ( ( uint64_t ) 0x0200000000000000U ) + #define eventWAIT_FOR_ALL_BITS ( ( uint64_t ) 0x0400000000000000U ) + #define eventEVENT_BITS_CONTROL_BYTES ( ( uint64_t ) 0xff00000000000000U ) +#endif /* if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) */ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/** + * An event group is a collection of bits to which an application can assign a + * meaning. For example, an application may create an event group to convey + * the status of various CAN bus related events in which bit 0 might mean "A CAN + * message has been received and is ready for processing", bit 1 might mean "The + * application has queued a message that is ready for sending onto the CAN + * network", and bit 2 might mean "It is time to send a SYNC message onto the + * CAN network" etc. A task can then test the bit values to see which events + * are active, and optionally enter the Blocked state to wait for a specified + * bit or a group of specified bits to be active. To continue the CAN bus + * example, a CAN controlling task can enter the Blocked state (and therefore + * not consume any processing time) until either bit 0, bit 1 or bit 2 are + * active, at which time the bit that was actually active would inform the task + * which action it had to take (process a received message, send a message, or + * send a SYNC). + * + * The event groups implementation contains intelligence to avoid race + * conditions that would otherwise occur were an application to use a simple + * variable for the same purpose. This is particularly important with respect + * to when a bit within an event group is to be cleared, and when bits have to + * be set and then tested atomically - as is the case where event groups are + * used to create a synchronisation point between multiple tasks (a + * 'rendezvous'). + */ + + + +/** + * event_groups.h + * + * Type by which event groups are referenced. For example, a call to + * xEventGroupCreate() returns an EventGroupHandle_t variable that can then + * be used as a parameter to other event group functions. + * + * \defgroup EventGroupHandle_t EventGroupHandle_t + * \ingroup EventGroup + */ +struct EventGroupDef_t; +typedef struct EventGroupDef_t * EventGroupHandle_t; + +/* + * The type that holds event bits always matches TickType_t - therefore the + * number of bits it holds is set by configTICK_TYPE_WIDTH_IN_BITS (16 bits if set to 0, + * 32 bits if set to 1, 64 bits if set to 2. + * + * \defgroup EventBits_t EventBits_t + * \ingroup EventGroup + */ +typedef TickType_t EventBits_t; + +/** + * event_groups.h + * @code{c} + * EventGroupHandle_t xEventGroupCreate( void ); + * @endcode + * + * Create a new event group. + * + * Internally, within the FreeRTOS implementation, event groups use a [small] + * block of memory, in which the event group's structure is stored. If an event + * groups is created using xEventGroupCreate() then the required memory is + * automatically dynamically allocated inside the xEventGroupCreate() function. + * (see https://www.FreeRTOS.org/a00111.html). If an event group is created + * using xEventGroupCreateStatic() then the application writer must instead + * provide the memory that will get used by the event group. + * xEventGroupCreateStatic() therefore allows an event group to be created + * without using any dynamic memory allocation. + * + * Although event groups are not related to ticks, for internal implementation + * reasons the number of bits available for use in an event group is dependent + * on the configTICK_TYPE_WIDTH_IN_BITS setting in FreeRTOSConfig.h. If + * configTICK_TYPE_WIDTH_IN_BITS is 0 then each event group contains 8 usable bits (bit + * 0 to bit 7). If configTICK_TYPE_WIDTH_IN_BITS is set to 1 then each event group has + * 24 usable bits (bit 0 to bit 23). If configTICK_TYPE_WIDTH_IN_BITS is set to 2 then + * each event group has 56 usable bits (bit 0 to bit 53). The EventBits_t type + * is used to store event bits within an event group. + * + * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for xEventGroupCreate() + * to be available. + * + * @return If the event group was created then a handle to the event group is + * returned. If there was insufficient FreeRTOS heap available to create the + * event group then NULL is returned. See https://www.FreeRTOS.org/a00111.html + * + * Example usage: + * @code{c} + * // Declare a variable to hold the created event group. + * EventGroupHandle_t xCreatedEventGroup; + * + * // Attempt to create the event group. + * xCreatedEventGroup = xEventGroupCreate(); + * + * // Was the event group created successfully? + * if( xCreatedEventGroup == NULL ) + * { + * // The event group was not created because there was insufficient + * // FreeRTOS heap available. + * } + * else + * { + * // The event group was created. + * } + * @endcode + * \defgroup xEventGroupCreate xEventGroupCreate + * \ingroup EventGroup + */ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + EventGroupHandle_t xEventGroupCreate( void ) PRIVILEGED_FUNCTION; +#endif + +/** + * event_groups.h + * @code{c} + * EventGroupHandle_t xEventGroupCreateStatic( EventGroupHandle_t * pxEventGroupBuffer ); + * @endcode + * + * Create a new event group. + * + * Internally, within the FreeRTOS implementation, event groups use a [small] + * block of memory, in which the event group's structure is stored. If an event + * groups is created using xEventGroupCreate() then the required memory is + * automatically dynamically allocated inside the xEventGroupCreate() function. + * (see https://www.FreeRTOS.org/a00111.html). If an event group is created + * using xEventGroupCreateStatic() then the application writer must instead + * provide the memory that will get used by the event group. + * xEventGroupCreateStatic() therefore allows an event group to be created + * without using any dynamic memory allocation. + * + * Although event groups are not related to ticks, for internal implementation + * reasons the number of bits available for use in an event group is dependent + * on the configTICK_TYPE_WIDTH_IN_BITS setting in FreeRTOSConfig.h. If + * configTICK_TYPE_WIDTH_IN_BITS is 0 then each event group contains 8 usable bits (bit + * 0 to bit 7). If configTICK_TYPE_WIDTH_IN_BITS is set to 1 then each event group has + * 24 usable bits (bit 0 to bit 23). If configTICK_TYPE_WIDTH_IN_BITS is set to 2 then + * each event group has 56 usable bits (bit 0 to bit 53). The EventBits_t type + * is used to store event bits within an event group. + * + * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for xEventGroupCreateStatic() + * to be available. + * + * @param pxEventGroupBuffer pxEventGroupBuffer must point to a variable of type + * StaticEventGroup_t, which will be then be used to hold the event group's data + * structures, removing the need for the memory to be allocated dynamically. + * + * @return If the event group was created then a handle to the event group is + * returned. If pxEventGroupBuffer was NULL then NULL is returned. + * + * Example usage: + * @code{c} + * // StaticEventGroup_t is a publicly accessible structure that has the same + * // size and alignment requirements as the real event group structure. It is + * // provided as a mechanism for applications to know the size of the event + * // group (which is dependent on the architecture and configuration file + * // settings) without breaking the strict data hiding policy by exposing the + * // real event group internals. This StaticEventGroup_t variable is passed + * // into the xSemaphoreCreateEventGroupStatic() function and is used to store + * // the event group's data structures + * StaticEventGroup_t xEventGroupBuffer; + * + * // Create the event group without dynamically allocating any memory. + * xEventGroup = xEventGroupCreateStatic( &xEventGroupBuffer ); + * @endcode + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) PRIVILEGED_FUNCTION; +#endif + +/** + * event_groups.h + * @code{c} + * EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, + * const EventBits_t uxBitsToWaitFor, + * const BaseType_t xClearOnExit, + * const BaseType_t xWaitForAllBits, + * const TickType_t xTicksToWait ); + * @endcode + * + * [Potentially] block to wait for one or more bits to be set within a + * previously created event group. + * + * This function cannot be called from an interrupt. + * + * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for xEventGroupWaitBits() + * to be available. + * + * @param xEventGroup The event group in which the bits are being tested. The + * event group must have previously been created using a call to + * xEventGroupCreate(). + * + * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test + * inside the event group. For example, to wait for bit 0 and/or bit 2 set + * uxBitsToWaitFor to 0x05. To wait for bits 0 and/or bit 1 and/or bit 2 set + * uxBitsToWaitFor to 0x07. Etc. + * + * @param xClearOnExit If xClearOnExit is set to pdTRUE then any bits within + * uxBitsToWaitFor that are set within the event group will be cleared before + * xEventGroupWaitBits() returns if the wait condition was met (if the function + * returns for a reason other than a timeout). If xClearOnExit is set to + * pdFALSE then the bits set in the event group are not altered when the call to + * xEventGroupWaitBits() returns. + * + * @param xWaitForAllBits If xWaitForAllBits is set to pdTRUE then + * xEventGroupWaitBits() will return when either all the bits in uxBitsToWaitFor + * are set or the specified block time expires. If xWaitForAllBits is set to + * pdFALSE then xEventGroupWaitBits() will return when any one of the bits set + * in uxBitsToWaitFor is set or the specified block time expires. The block + * time is specified by the xTicksToWait parameter. + * + * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait + * for one/all (depending on the xWaitForAllBits value) of the bits specified by + * uxBitsToWaitFor to become set. A value of portMAX_DELAY can be used to block + * indefinitely (provided INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h). + * + * @return The value of the event group at the time either the bits being waited + * for became set, or the block time expired. Test the return value to know + * which bits were set. If xEventGroupWaitBits() returned because its timeout + * expired then not all the bits being waited for will be set. If + * xEventGroupWaitBits() returned because the bits it was waiting for were set + * then the returned value is the event group value before any bits were + * automatically cleared in the case that xClearOnExit parameter was set to + * pdTRUE. + * + * Example usage: + * @code{c} + * #define BIT_0 ( 1 << 0 ) + * #define BIT_4 ( 1 << 4 ) + * + * void aFunction( EventGroupHandle_t xEventGroup ) + * { + * EventBits_t uxBits; + * const TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS; + * + * // Wait a maximum of 100ms for either bit 0 or bit 4 to be set within + * // the event group. Clear the bits before exiting. + * uxBits = xEventGroupWaitBits( + * xEventGroup, // The event group being tested. + * BIT_0 | BIT_4, // The bits within the event group to wait for. + * pdTRUE, // BIT_0 and BIT_4 should be cleared before returning. + * pdFALSE, // Don't wait for both bits, either bit will do. + * xTicksToWait ); // Wait a maximum of 100ms for either bit to be set. + * + * if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) ) + * { + * // xEventGroupWaitBits() returned because both bits were set. + * } + * else if( ( uxBits & BIT_0 ) != 0 ) + * { + * // xEventGroupWaitBits() returned because just BIT_0 was set. + * } + * else if( ( uxBits & BIT_4 ) != 0 ) + * { + * // xEventGroupWaitBits() returned because just BIT_4 was set. + * } + * else + * { + * // xEventGroupWaitBits() returned because xTicksToWait ticks passed + * // without either BIT_0 or BIT_4 becoming set. + * } + * } + * @endcode + * \defgroup xEventGroupWaitBits xEventGroupWaitBits + * \ingroup EventGroup + */ +EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToWaitFor, + const BaseType_t xClearOnExit, + const BaseType_t xWaitForAllBits, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + * @code{c} + * EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ); + * @endcode + * + * Clear bits within an event group. This function cannot be called from an + * interrupt. + * + * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for xEventGroupClearBits() + * to be available. + * + * @param xEventGroup The event group in which the bits are to be cleared. + * + * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear + * in the event group. For example, to clear bit 3 only, set uxBitsToClear to + * 0x08. To clear bit 3 and bit 0 set uxBitsToClear to 0x09. + * + * @return The value of the event group before the specified bits were cleared. + * + * Example usage: + * @code{c} + * #define BIT_0 ( 1 << 0 ) + * #define BIT_4 ( 1 << 4 ) + * + * void aFunction( EventGroupHandle_t xEventGroup ) + * { + * EventBits_t uxBits; + * + * // Clear bit 0 and bit 4 in xEventGroup. + * uxBits = xEventGroupClearBits( + * xEventGroup, // The event group being updated. + * BIT_0 | BIT_4 );// The bits being cleared. + * + * if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) ) + * { + * // Both bit 0 and bit 4 were set before xEventGroupClearBits() was + * // called. Both will now be clear (not set). + * } + * else if( ( uxBits & BIT_0 ) != 0 ) + * { + * // Bit 0 was set before xEventGroupClearBits() was called. It will + * // now be clear. + * } + * else if( ( uxBits & BIT_4 ) != 0 ) + * { + * // Bit 4 was set before xEventGroupClearBits() was called. It will + * // now be clear. + * } + * else + * { + * // Neither bit 0 nor bit 4 were set in the first place. + * } + * } + * @endcode + * \defgroup xEventGroupClearBits xEventGroupClearBits + * \ingroup EventGroup + */ +EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + * @code{c} + * BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ); + * @endcode + * + * A version of xEventGroupClearBits() that can be called from an interrupt. + * + * Setting bits in an event group is not a deterministic operation because there + * are an unknown number of tasks that may be waiting for the bit or bits being + * set. FreeRTOS does not allow nondeterministic operations to be performed + * while interrupts are disabled, so protects event groups that are accessed + * from tasks by suspending the scheduler rather than disabling interrupts. As + * a result event groups cannot be accessed directly from an interrupt service + * routine. Therefore xEventGroupClearBitsFromISR() sends a message to the + * timer task to have the clear operation performed in the context of the timer + * task. + * + * @note If this function returns pdPASS then the timer task is ready to run + * and a portYIELD_FROM_ISR(pdTRUE) should be executed to perform the needed + * clear on the event group. This behavior is different from + * xEventGroupSetBitsFromISR because the parameter xHigherPriorityTaskWoken is + * not present. + * + * @param xEventGroup The event group in which the bits are to be cleared. + * + * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear. + * For example, to clear bit 3 only, set uxBitsToClear to 0x08. To clear bit 3 + * and bit 0 set uxBitsToClear to 0x09. + * + * @return If the request to execute the function was posted successfully then + * pdPASS is returned, otherwise pdFALSE is returned. pdFALSE will be returned + * if the timer service queue was full. + * + * Example usage: + * @code{c} + * #define BIT_0 ( 1 << 0 ) + * #define BIT_4 ( 1 << 4 ) + * + * // An event group which it is assumed has already been created by a call to + * // xEventGroupCreate(). + * EventGroupHandle_t xEventGroup; + * + * void anInterruptHandler( void ) + * { + * // Clear bit 0 and bit 4 in xEventGroup. + * xResult = xEventGroupClearBitsFromISR( + * xEventGroup, // The event group being updated. + * BIT_0 | BIT_4 ); // The bits being set. + * + * if( xResult == pdPASS ) + * { + * // The message was posted successfully. + * portYIELD_FROM_ISR(pdTRUE); + * } + * } + * @endcode + * \defgroup xEventGroupClearBitsFromISR xEventGroupClearBitsFromISR + * \ingroup EventGroup + */ +#if ( ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) + BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION; +#endif /* if ( ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */ + +/** + * event_groups.h + * @code{c} + * EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ); + * @endcode + * + * Set bits within an event group. + * This function cannot be called from an interrupt. xEventGroupSetBitsFromISR() + * is a version that can be called from an interrupt. + * + * Setting bits in an event group will automatically unblock tasks that are + * blocked waiting for the bits. + * + * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for xEventGroupSetBits() + * to be available. + * + * @param xEventGroup The event group in which the bits are to be set. + * + * @param uxBitsToSet A bitwise value that indicates the bit or bits to set. + * For example, to set bit 3 only, set uxBitsToSet to 0x08. To set bit 3 + * and bit 0 set uxBitsToSet to 0x09. + * + * @return The value of the event group at the time the call to + * xEventGroupSetBits() returns. Returned value might have the bits specified + * by the uxBitsToSet parameter cleared if setting a bit results in a task + * that was waiting for the bit leaving the blocked state then it is possible + * the bit will be cleared automatically (see the xClearBitOnExit parameter + * of xEventGroupWaitBits()). + * + * Example usage: + * @code{c} + * #define BIT_0 ( 1 << 0 ) + * #define BIT_4 ( 1 << 4 ) + * + * void aFunction( EventGroupHandle_t xEventGroup ) + * { + * EventBits_t uxBits; + * + * // Set bit 0 and bit 4 in xEventGroup. + * uxBits = xEventGroupSetBits( + * xEventGroup, // The event group being updated. + * BIT_0 | BIT_4 );// The bits being set. + * + * if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) ) + * { + * // Both bit 0 and bit 4 remained set when the function returned. + * } + * else if( ( uxBits & BIT_0 ) != 0 ) + * { + * // Bit 0 remained set when the function returned, but bit 4 was + * // cleared. It might be that bit 4 was cleared automatically as a + * // task that was waiting for bit 4 was removed from the Blocked + * // state. + * } + * else if( ( uxBits & BIT_4 ) != 0 ) + * { + * // Bit 4 remained set when the function returned, but bit 0 was + * // cleared. It might be that bit 0 was cleared automatically as a + * // task that was waiting for bit 0 was removed from the Blocked + * // state. + * } + * else + * { + * // Neither bit 0 nor bit 4 remained set. It might be that a task + * // was waiting for both of the bits to be set, and the bits were + * // cleared as the task left the Blocked state. + * } + * } + * @endcode + * \defgroup xEventGroupSetBits xEventGroupSetBits + * \ingroup EventGroup + */ +EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + * @code{c} + * BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken ); + * @endcode + * + * A version of xEventGroupSetBits() that can be called from an interrupt. + * + * Setting bits in an event group is not a deterministic operation because there + * are an unknown number of tasks that may be waiting for the bit or bits being + * set. FreeRTOS does not allow nondeterministic operations to be performed in + * interrupts or from critical sections. Therefore xEventGroupSetBitsFromISR() + * sends a message to the timer task to have the set operation performed in the + * context of the timer task - where a scheduler lock is used in place of a + * critical section. + * + * @param xEventGroup The event group in which the bits are to be set. + * + * @param uxBitsToSet A bitwise value that indicates the bit or bits to set. + * For example, to set bit 3 only, set uxBitsToSet to 0x08. To set bit 3 + * and bit 0 set uxBitsToSet to 0x09. + * + * @param pxHigherPriorityTaskWoken As mentioned above, calling this function + * will result in a message being sent to the timer daemon task. If the + * priority of the timer daemon task is higher than the priority of the + * currently running task (the task the interrupt interrupted) then + * *pxHigherPriorityTaskWoken will be set to pdTRUE by + * xEventGroupSetBitsFromISR(), indicating that a context switch should be + * requested before the interrupt exits. For that reason + * *pxHigherPriorityTaskWoken must be initialised to pdFALSE. See the + * example code below. + * + * @return If the request to execute the function was posted successfully then + * pdPASS is returned, otherwise pdFALSE is returned. pdFALSE will be returned + * if the timer service queue was full. + * + * Example usage: + * @code{c} + * #define BIT_0 ( 1 << 0 ) + * #define BIT_4 ( 1 << 4 ) + * + * // An event group which it is assumed has already been created by a call to + * // xEventGroupCreate(). + * EventGroupHandle_t xEventGroup; + * + * void anInterruptHandler( void ) + * { + * BaseType_t xHigherPriorityTaskWoken, xResult; + * + * // xHigherPriorityTaskWoken must be initialised to pdFALSE. + * xHigherPriorityTaskWoken = pdFALSE; + * + * // Set bit 0 and bit 4 in xEventGroup. + * xResult = xEventGroupSetBitsFromISR( + * xEventGroup, // The event group being updated. + * BIT_0 | BIT_4 // The bits being set. + * &xHigherPriorityTaskWoken ); + * + * // Was the message posted successfully? + * if( xResult == pdPASS ) + * { + * // If xHigherPriorityTaskWoken is now set to pdTRUE then a context + * // switch should be requested. The macro used is port specific and + * // will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - + * // refer to the documentation page for the port being used. + * portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + * } + * } + * @endcode + * \defgroup xEventGroupSetBitsFromISR xEventGroupSetBitsFromISR + * \ingroup EventGroup + */ +#if ( ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) + BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; +#endif /* if ( ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */ + +/** + * event_groups.h + * @code{c} + * EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, + * const EventBits_t uxBitsToSet, + * const EventBits_t uxBitsToWaitFor, + * TickType_t xTicksToWait ); + * @endcode + * + * Atomically set bits within an event group, then wait for a combination of + * bits to be set within the same event group. This functionality is typically + * used to synchronise multiple tasks, where each task has to wait for the other + * tasks to reach a synchronisation point before proceeding. + * + * This function cannot be used from an interrupt. + * + * The function will return before its block time expires if the bits specified + * by the uxBitsToWait parameter are set, or become set within that time. In + * this case all the bits specified by uxBitsToWait will be automatically + * cleared before the function returns. + * + * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for xEventGroupSync() + * to be available. + * + * @param xEventGroup The event group in which the bits are being tested. The + * event group must have previously been created using a call to + * xEventGroupCreate(). + * + * @param uxBitsToSet The bits to set in the event group before determining + * if, and possibly waiting for, all the bits specified by the uxBitsToWait + * parameter are set. + * + * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test + * inside the event group. For example, to wait for bit 0 and bit 2 set + * uxBitsToWaitFor to 0x05. To wait for bits 0 and bit 1 and bit 2 set + * uxBitsToWaitFor to 0x07. Etc. + * + * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait + * for all of the bits specified by uxBitsToWaitFor to become set. + * + * @return The value of the event group at the time either the bits being waited + * for became set, or the block time expired. Test the return value to know + * which bits were set. If xEventGroupSync() returned because its timeout + * expired then not all the bits being waited for will be set. If + * xEventGroupSync() returned because all the bits it was waiting for were + * set then the returned value is the event group value before any bits were + * automatically cleared. + * + * Example usage: + * @code{c} + * // Bits used by the three tasks. + * #define TASK_0_BIT ( 1 << 0 ) + * #define TASK_1_BIT ( 1 << 1 ) + * #define TASK_2_BIT ( 1 << 2 ) + * + * #define ALL_SYNC_BITS ( TASK_0_BIT | TASK_1_BIT | TASK_2_BIT ) + * + * // Use an event group to synchronise three tasks. It is assumed this event + * // group has already been created elsewhere. + * EventGroupHandle_t xEventBits; + * + * void vTask0( void *pvParameters ) + * { + * EventBits_t uxReturn; + * TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS; + * + * for( ;; ) + * { + * // Perform task functionality here. + * + * // Set bit 0 in the event flag to note this task has reached the + * // sync point. The other two tasks will set the other two bits defined + * // by ALL_SYNC_BITS. All three tasks have reached the synchronisation + * // point when all the ALL_SYNC_BITS are set. Wait a maximum of 100ms + * // for this to happen. + * uxReturn = xEventGroupSync( xEventBits, TASK_0_BIT, ALL_SYNC_BITS, xTicksToWait ); + * + * if( ( uxReturn & ALL_SYNC_BITS ) == ALL_SYNC_BITS ) + * { + * // All three tasks reached the synchronisation point before the call + * // to xEventGroupSync() timed out. + * } + * } + * } + * + * void vTask1( void *pvParameters ) + * { + * for( ;; ) + * { + * // Perform task functionality here. + * + * // Set bit 1 in the event flag to note this task has reached the + * // synchronisation point. The other two tasks will set the other two + * // bits defined by ALL_SYNC_BITS. All three tasks have reached the + * // synchronisation point when all the ALL_SYNC_BITS are set. Wait + * // indefinitely for this to happen. + * xEventGroupSync( xEventBits, TASK_1_BIT, ALL_SYNC_BITS, portMAX_DELAY ); + * + * // xEventGroupSync() was called with an indefinite block time, so + * // this task will only reach here if the synchronisation was made by all + * // three tasks, so there is no need to test the return value. + * } + * } + * + * void vTask2( void *pvParameters ) + * { + * for( ;; ) + * { + * // Perform task functionality here. + * + * // Set bit 2 in the event flag to note this task has reached the + * // synchronisation point. The other two tasks will set the other two + * // bits defined by ALL_SYNC_BITS. All three tasks have reached the + * // synchronisation point when all the ALL_SYNC_BITS are set. Wait + * // indefinitely for this to happen. + * xEventGroupSync( xEventBits, TASK_2_BIT, ALL_SYNC_BITS, portMAX_DELAY ); + * + * // xEventGroupSync() was called with an indefinite block time, so + * // this task will only reach here if the synchronisation was made by all + * // three tasks, so there is no need to test the return value. + * } + * } + * + * @endcode + * \defgroup xEventGroupSync xEventGroupSync + * \ingroup EventGroup + */ +EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + + +/** + * event_groups.h + * @code{c} + * EventBits_t xEventGroupGetBits( EventGroupHandle_t xEventGroup ); + * @endcode + * + * Returns the current value of the bits in an event group. This function + * cannot be used from an interrupt. + * + * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for xEventGroupGetBits() + * to be available. + * + * @param xEventGroup The event group being queried. + * + * @return The event group bits at the time xEventGroupGetBits() was called. + * + * \defgroup xEventGroupGetBits xEventGroupGetBits + * \ingroup EventGroup + */ +#define xEventGroupGetBits( xEventGroup ) xEventGroupClearBits( ( xEventGroup ), 0 ) + +/** + * event_groups.h + * @code{c} + * EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ); + * @endcode + * + * A version of xEventGroupGetBits() that can be called from an ISR. + * + * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for xEventGroupGetBitsFromISR() + * to be available. + * + * @param xEventGroup The event group being queried. + * + * @return The event group bits at the time xEventGroupGetBitsFromISR() was called. + * + * \defgroup xEventGroupGetBitsFromISR xEventGroupGetBitsFromISR + * \ingroup EventGroup + */ +EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + * @code{c} + * void xEventGroupDelete( EventGroupHandle_t xEventGroup ); + * @endcode + * + * Delete an event group that was previously created by a call to + * xEventGroupCreate(). Tasks that are blocked on the event group will be + * unblocked and obtain 0 as the event group's value. + * + * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for vEventGroupDelete() + * to be available. + * + * @param xEventGroup The event group being deleted. + */ +void vEventGroupDelete( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + * @code{c} + * BaseType_t xEventGroupGetStaticBuffer( EventGroupHandle_t xEventGroup, + * StaticEventGroup_t ** ppxEventGroupBuffer ); + * @endcode + * + * Retrieve a pointer to a statically created event groups's data structure + * buffer. It is the same buffer that is supplied at the time of creation. + * + * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for xEventGroupGetStaticBuffer() + * to be available. + * + * @param xEventGroup The event group for which to retrieve the buffer. + * + * @param ppxEventGroupBuffer Used to return a pointer to the event groups's + * data structure buffer. + * + * @return pdTRUE if the buffer was retrieved, pdFALSE otherwise. + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + BaseType_t xEventGroupGetStaticBuffer( EventGroupHandle_t xEventGroup, + StaticEventGroup_t ** ppxEventGroupBuffer ) PRIVILEGED_FUNCTION; +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +/* For internal use only. */ +void vEventGroupSetBitsCallback( void * pvEventGroup, + uint32_t ulBitsToSet ) PRIVILEGED_FUNCTION; +void vEventGroupClearBitsCallback( void * pvEventGroup, + uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION; + + +#if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxEventGroupGetNumber( void * xEventGroup ) PRIVILEGED_FUNCTION; + void vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) PRIVILEGED_FUNCTION; +#endif + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* EVENT_GROUPS_H */ diff --git a/include/list.h b/include/list.h new file mode 100644 index 000000000..b6e0d34f4 --- /dev/null +++ b/include/list.h @@ -0,0 +1,511 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * This is the list implementation used by the scheduler. While it is tailored + * heavily for the schedulers needs, it is also available for use by + * application code. + * + * list_ts can only store pointers to list_item_ts. Each ListItem_t contains a + * numeric value (xItemValue). Most of the time the lists are sorted in + * ascending item value order. + * + * Lists are created already containing one list item. The value of this + * item is the maximum possible that can be stored, it is therefore always at + * the end of the list and acts as a marker. The list member pxHead always + * points to this marker - even though it is at the tail of the list. This + * is because the tail contains a wrap back pointer to the true head of + * the list. + * + * In addition to it's value, each list item contains a pointer to the next + * item in the list (pxNext), a pointer to the list it is in (pxContainer) + * and a pointer back to the object that contains it. These later two + * pointers are included for efficiency of list manipulation. There is + * effectively a two way link between the object containing the list item and + * the list item itself. + * + * + * \page ListIntroduction List Implementation + * \ingroup FreeRTOSIntro + */ + + +#ifndef LIST_H +#define LIST_H + +#ifndef INC_FREERTOS_H + #error "FreeRTOS.h must be included before list.h" +#endif + +/* + * The list structure members are modified from within interrupts, and therefore + * by rights should be declared volatile. However, they are only modified in a + * functionally atomic way (within critical sections of with the scheduler + * suspended) and are either passed by reference into a function or indexed via + * a volatile variable. Therefore, in all use cases tested so far, the volatile + * qualifier can be omitted in order to provide a moderate performance + * improvement without adversely affecting functional behaviour. The assembly + * instructions generated by the IAR, ARM and GCC compilers when the respective + * compiler's options were set for maximum optimisation has been inspected and + * deemed to be as intended. That said, as compiler technology advances, and + * especially if aggressive cross module optimisation is used (a use case that + * has not been exercised to any great extend) then it is feasible that the + * volatile qualifier will be needed for correct optimisation. It is expected + * that a compiler removing essential code because, without the volatile + * qualifier on the list structure members and with aggressive cross module + * optimisation, the compiler deemed the code unnecessary will result in + * complete and obvious failure of the scheduler. If this is ever experienced + * then the volatile qualifier can be inserted in the relevant places within the + * list structures by simply defining configLIST_VOLATILE to volatile in + * FreeRTOSConfig.h (as per the example at the bottom of this comment block). + * If configLIST_VOLATILE is not defined then the preprocessor directives below + * will simply #define configLIST_VOLATILE away completely. + * + * To use volatile list structure members then add the following line to + * FreeRTOSConfig.h (without the quotes): + * "#define configLIST_VOLATILE volatile" + */ +#ifndef configLIST_VOLATILE + #define configLIST_VOLATILE +#endif /* configSUPPORT_CROSS_MODULE_OPTIMISATION */ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/* Macros that can be used to place known values within the list structures, + * then check that the known values do not get corrupted during the execution of + * the application. These may catch the list data structures being overwritten in + * memory. They will not catch data errors caused by incorrect configuration or + * use of FreeRTOS.*/ +#if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 ) + /* Define the macros to do nothing. */ + #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE + #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE + #define listFIRST_LIST_INTEGRITY_CHECK_VALUE + #define listSECOND_LIST_INTEGRITY_CHECK_VALUE + #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) + #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) + #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ) + #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ) + #define listTEST_LIST_ITEM_INTEGRITY( pxItem ) + #define listTEST_LIST_INTEGRITY( pxList ) +#else /* if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 ) */ + /* Define macros that add new members into the list structures. */ + #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE TickType_t xListItemIntegrityValue1; + #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE TickType_t xListItemIntegrityValue2; + #define listFIRST_LIST_INTEGRITY_CHECK_VALUE TickType_t xListIntegrityValue1; + #define listSECOND_LIST_INTEGRITY_CHECK_VALUE TickType_t xListIntegrityValue2; + +/* Define macros that set the new structure members to known values. */ + #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) ( pxItem )->xListItemIntegrityValue1 = pdINTEGRITY_CHECK_VALUE + #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) ( pxItem )->xListItemIntegrityValue2 = pdINTEGRITY_CHECK_VALUE + #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ) ( pxList )->xListIntegrityValue1 = pdINTEGRITY_CHECK_VALUE + #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ) ( pxList )->xListIntegrityValue2 = pdINTEGRITY_CHECK_VALUE + +/* Define macros that will assert if one of the structure members does not + * contain its expected value. */ + #define listTEST_LIST_ITEM_INTEGRITY( pxItem ) configASSERT( ( ( pxItem )->xListItemIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxItem )->xListItemIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) ) + #define listTEST_LIST_INTEGRITY( pxList ) configASSERT( ( ( pxList )->xListIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxList )->xListIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) ) +#endif /* configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES */ + + +/* + * Definition of the only type of object that a list can contain. + */ +struct xLIST; +struct xLIST_ITEM +{ + listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /**< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + configLIST_VOLATILE TickType_t xItemValue; /**< The value being listed. In most cases this is used to sort the list in ascending order. */ + struct xLIST_ITEM * configLIST_VOLATILE pxNext; /**< Pointer to the next ListItem_t in the list. */ + struct xLIST_ITEM * configLIST_VOLATILE pxPrevious; /**< Pointer to the previous ListItem_t in the list. */ + void * pvOwner; /**< Pointer to the object (normally a TCB) that contains the list item. There is therefore a two way link between the object containing the list item and the list item itself. */ + struct xLIST * configLIST_VOLATILE pxContainer; /**< Pointer to the list in which this list item is placed (if any). */ + listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE /**< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ +}; +typedef struct xLIST_ITEM ListItem_t; + +#if ( configUSE_MINI_LIST_ITEM == 1 ) + struct xMINI_LIST_ITEM + { + listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /**< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + configLIST_VOLATILE TickType_t xItemValue; + struct xLIST_ITEM * configLIST_VOLATILE pxNext; + struct xLIST_ITEM * configLIST_VOLATILE pxPrevious; + }; + typedef struct xMINI_LIST_ITEM MiniListItem_t; +#else + typedef struct xLIST_ITEM MiniListItem_t; +#endif + +/* + * Definition of the type of queue used by the scheduler. + */ +typedef struct xLIST +{ + listFIRST_LIST_INTEGRITY_CHECK_VALUE /**< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + configLIST_VOLATILE UBaseType_t uxNumberOfItems; + ListItem_t * configLIST_VOLATILE pxIndex; /**< Used to walk through the list. Points to the last item returned by a call to listGET_OWNER_OF_NEXT_ENTRY (). */ + MiniListItem_t xListEnd; /**< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */ + listSECOND_LIST_INTEGRITY_CHECK_VALUE /**< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ +} List_t; + +/* + * Access macro to set the owner of a list item. The owner of a list item + * is the object (usually a TCB) that contains the list item. + * + * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER + * \ingroup LinkedList + */ +#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner ) ( ( pxListItem )->pvOwner = ( void * ) ( pxOwner ) ) + +/* + * Access macro to get the owner of a list item. The owner of a list item + * is the object (usually a TCB) that contains the list item. + * + * \page listGET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER + * \ingroup LinkedList + */ +#define listGET_LIST_ITEM_OWNER( pxListItem ) ( ( pxListItem )->pvOwner ) + +/* + * Access macro to set the value of the list item. In most cases the value is + * used to sort the list in ascending order. + * + * \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE + * \ingroup LinkedList + */ +#define listSET_LIST_ITEM_VALUE( pxListItem, xValue ) ( ( pxListItem )->xItemValue = ( xValue ) ) + +/* + * Access macro to retrieve the value of the list item. The value can + * represent anything - for example the priority of a task, or the time at + * which a task should be unblocked. + * + * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE + * \ingroup LinkedList + */ +#define listGET_LIST_ITEM_VALUE( pxListItem ) ( ( pxListItem )->xItemValue ) + +/* + * Access macro to retrieve the value of the list item at the head of a given + * list. + * + * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE + * \ingroup LinkedList + */ +#define listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxList ) ( ( ( pxList )->xListEnd ).pxNext->xItemValue ) + +/* + * Return the list item at the head of the list. + * + * \page listGET_HEAD_ENTRY listGET_HEAD_ENTRY + * \ingroup LinkedList + */ +#define listGET_HEAD_ENTRY( pxList ) ( ( ( pxList )->xListEnd ).pxNext ) + +/* + * Return the next list item. + * + * \page listGET_NEXT listGET_NEXT + * \ingroup LinkedList + */ +#define listGET_NEXT( pxListItem ) ( ( pxListItem )->pxNext ) + +/* + * Return the list item that marks the end of the list + * + * \page listGET_END_MARKER listGET_END_MARKER + * \ingroup LinkedList + */ +#define listGET_END_MARKER( pxList ) ( ( ListItem_t const * ) ( &( ( pxList )->xListEnd ) ) ) + +/* + * Access macro to determine if a list contains any items. The macro will + * only have the value true if the list is empty. + * + * \page listLIST_IS_EMPTY listLIST_IS_EMPTY + * \ingroup LinkedList + */ +#define listLIST_IS_EMPTY( pxList ) ( ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) ? pdTRUE : pdFALSE ) + +/* + * Access macro to return the number of items in the list. + */ +#define listCURRENT_LIST_LENGTH( pxList ) ( ( pxList )->uxNumberOfItems ) + +/* + * Access function to obtain the owner of the next entry in a list. + * + * The list member pxIndex is used to walk through a list. Calling + * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list + * and returns that entry's pxOwner parameter. Using multiple calls to this + * function it is therefore possible to move through every item contained in + * a list. + * + * The pxOwner parameter of a list item is a pointer to the object that owns + * the list item. In the scheduler this is normally a task control block. + * The pxOwner parameter effectively creates a two way link between the list + * item and its owner. + * + * @param pxTCB pxTCB is set to the address of the owner of the next list item. + * @param pxList The list from which the next item owner is to be returned. + * + * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY + * \ingroup LinkedList + */ +#if ( configNUMBER_OF_CORES == 1 ) + #define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList ) \ + do { \ + List_t * const pxConstList = ( pxList ); \ + /* Increment the index to the next item and return the item, ensuring */ \ + /* we don't return the marker used at the end of the list. */ \ + ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \ + if( ( void * ) ( pxConstList )->pxIndex == ( void * ) &( ( pxConstList )->xListEnd ) ) \ + { \ + ( pxConstList )->pxIndex = ( pxConstList )->xListEnd.pxNext; \ + } \ + ( pxTCB ) = ( pxConstList )->pxIndex->pvOwner; \ + } while( 0 ) +#else /* #if ( configNUMBER_OF_CORES == 1 ) */ + +/* This function is not required in SMP. FreeRTOS SMP scheduler doesn't use + * pxIndex and it should always point to the xListEnd. Not defining this macro + * here to prevent updating pxIndex. + */ +#endif /* #if ( configNUMBER_OF_CORES == 1 ) */ + +/* + * Version of uxListRemove() that does not return a value. Provided as a slight + * optimisation for xTaskIncrementTick() by being inline. + * + * Remove an item from a list. The list item has a pointer to the list that + * it is in, so only the list item need be passed into the function. + * + * @param uxListRemove The item to be removed. The item will remove itself from + * the list pointed to by it's pxContainer parameter. + * + * @return The number of items that remain in the list after the list item has + * been removed. + * + * \page listREMOVE_ITEM listREMOVE_ITEM + * \ingroup LinkedList + */ +#define listREMOVE_ITEM( pxItemToRemove ) \ + do { \ + /* The list item knows which list it is in. Obtain the list from the list \ + * item. */ \ + List_t * const pxList = ( pxItemToRemove )->pxContainer; \ + \ + ( pxItemToRemove )->pxNext->pxPrevious = ( pxItemToRemove )->pxPrevious; \ + ( pxItemToRemove )->pxPrevious->pxNext = ( pxItemToRemove )->pxNext; \ + /* Make sure the index is left pointing to a valid item. */ \ + if( pxList->pxIndex == ( pxItemToRemove ) ) \ + { \ + pxList->pxIndex = ( pxItemToRemove )->pxPrevious; \ + } \ + \ + ( pxItemToRemove )->pxContainer = NULL; \ + ( ( pxList )->uxNumberOfItems ) = ( UBaseType_t ) ( ( ( pxList )->uxNumberOfItems ) - 1U ); \ + } while( 0 ) + +/* + * Inline version of vListInsertEnd() to provide slight optimisation for + * xTaskIncrementTick(). + * + * Insert a list item into a list. The item will be inserted in a position + * such that it will be the last item within the list returned by multiple + * calls to listGET_OWNER_OF_NEXT_ENTRY. + * + * The list member pxIndex is used to walk through a list. Calling + * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list. + * Placing an item in a list using vListInsertEnd effectively places the item + * in the list position pointed to by pxIndex. This means that every other + * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before + * the pxIndex parameter again points to the item being inserted. + * + * @param pxList The list into which the item is to be inserted. + * + * @param pxNewListItem The list item to be inserted into the list. + * + * \page listINSERT_END listINSERT_END + * \ingroup LinkedList + */ +#define listINSERT_END( pxList, pxNewListItem ) \ + do { \ + ListItem_t * const pxIndex = ( pxList )->pxIndex; \ + \ + /* Only effective when configASSERT() is also defined, these tests may catch \ + * the list data structures being overwritten in memory. They will not catch \ + * data errors caused by incorrect configuration or use of FreeRTOS. */ \ + listTEST_LIST_INTEGRITY( ( pxList ) ); \ + listTEST_LIST_ITEM_INTEGRITY( ( pxNewListItem ) ); \ + \ + /* Insert a new list item into ( pxList ), but rather than sort the list, \ + * makes the new list item the last item to be removed by a call to \ + * listGET_OWNER_OF_NEXT_ENTRY(). */ \ + ( pxNewListItem )->pxNext = pxIndex; \ + ( pxNewListItem )->pxPrevious = pxIndex->pxPrevious; \ + \ + pxIndex->pxPrevious->pxNext = ( pxNewListItem ); \ + pxIndex->pxPrevious = ( pxNewListItem ); \ + \ + /* Remember which list the item is in. */ \ + ( pxNewListItem )->pxContainer = ( pxList ); \ + \ + ( ( pxList )->uxNumberOfItems ) = ( UBaseType_t ) ( ( ( pxList )->uxNumberOfItems ) + 1U ); \ + } while( 0 ) + +/* + * Access function to obtain the owner of the first entry in a list. Lists + * are normally sorted in ascending item value order. + * + * This function returns the pxOwner member of the first item in the list. + * The pxOwner parameter of a list item is a pointer to the object that owns + * the list item. In the scheduler this is normally a task control block. + * The pxOwner parameter effectively creates a two way link between the list + * item and its owner. + * + * @param pxList The list from which the owner of the head item is to be + * returned. + * + * \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY + * \ingroup LinkedList + */ +#define listGET_OWNER_OF_HEAD_ENTRY( pxList ) ( ( &( ( pxList )->xListEnd ) )->pxNext->pvOwner ) + +/* + * Check to see if a list item is within a list. The list item maintains a + * "container" pointer that points to the list it is in. All this macro does + * is check to see if the container and the list match. + * + * @param pxList The list we want to know if the list item is within. + * @param pxListItem The list item we want to know if is in the list. + * @return pdTRUE if the list item is in the list, otherwise pdFALSE. + */ +#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( ( pxListItem )->pxContainer == ( pxList ) ) ? ( pdTRUE ) : ( pdFALSE ) ) + +/* + * Return the list a list item is contained within (referenced from). + * + * @param pxListItem The list item being queried. + * @return A pointer to the List_t object that references the pxListItem + */ +#define listLIST_ITEM_CONTAINER( pxListItem ) ( ( pxListItem )->pxContainer ) + +/* + * This provides a crude means of knowing if a list has been initialised, as + * pxList->xListEnd.xItemValue is set to portMAX_DELAY by the vListInitialise() + * function. + */ +#define listLIST_IS_INITIALISED( pxList ) ( ( pxList )->xListEnd.xItemValue == portMAX_DELAY ) + +/* + * Must be called before a list is used! This initialises all the members + * of the list structure and inserts the xListEnd item into the list as a + * marker to the back of the list. + * + * @param pxList Pointer to the list being initialised. + * + * \page vListInitialise vListInitialise + * \ingroup LinkedList + */ +void vListInitialise( List_t * const pxList ) PRIVILEGED_FUNCTION; + +/* + * Must be called before a list item is used. This sets the list container to + * null so the item does not think that it is already contained in a list. + * + * @param pxItem Pointer to the list item being initialised. + * + * \page vListInitialiseItem vListInitialiseItem + * \ingroup LinkedList + */ +void vListInitialiseItem( ListItem_t * const pxItem ) PRIVILEGED_FUNCTION; + +/* + * Insert a list item into a list. The item will be inserted into the list in + * a position determined by its item value (ascending item value order). + * + * @param pxList The list into which the item is to be inserted. + * + * @param pxNewListItem The item that is to be placed in the list. + * + * \page vListInsert vListInsert + * \ingroup LinkedList + */ +void vListInsert( List_t * const pxList, + ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION; + +/* + * Insert a list item into a list. The item will be inserted in a position + * such that it will be the last item within the list returned by multiple + * calls to listGET_OWNER_OF_NEXT_ENTRY. + * + * The list member pxIndex is used to walk through a list. Calling + * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list. + * Placing an item in a list using vListInsertEnd effectively places the item + * in the list position pointed to by pxIndex. This means that every other + * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before + * the pxIndex parameter again points to the item being inserted. + * + * @param pxList The list into which the item is to be inserted. + * + * @param pxNewListItem The list item to be inserted into the list. + * + * \page vListInsertEnd vListInsertEnd + * \ingroup LinkedList + */ +void vListInsertEnd( List_t * const pxList, + ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION; + +/* + * Remove an item from a list. The list item has a pointer to the list that + * it is in, so only the list item need be passed into the function. + * + * @param uxListRemove The item to be removed. The item will remove itself from + * the list pointed to by it's pxContainer parameter. + * + * @return The number of items that remain in the list after the list item has + * been removed. + * + * \page uxListRemove uxListRemove + * \ingroup LinkedList + */ +UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) PRIVILEGED_FUNCTION; + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* ifndef LIST_H */ diff --git a/include/message_buffer.h b/include/message_buffer.h new file mode 100644 index 000000000..9fb97ffd0 --- /dev/null +++ b/include/message_buffer.h @@ -0,0 +1,967 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/* + * Message buffers build functionality on top of FreeRTOS stream buffers. + * Whereas stream buffers are used to send a continuous stream of data from one + * task or interrupt to another, message buffers are used to send variable + * length discrete messages from one task or interrupt to another. Their + * implementation is light weight, making them particularly suited for interrupt + * to task and core to core communication scenarios. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must serialize calls to writing API functions + * (such as xStreamBufferSend()). Likewise, if there are to be multiple + * different readers then the application writer must serialize calls to reading + * API functions (such as xStreamBufferReceive()). One way to achieve such + * serialization in single core or SMP kernel is to place each API call inside a + * critical section and use a block time of 0. + * + * Message buffers hold variable length messages. To enable that, when a + * message is written to the message buffer an additional sizeof( size_t ) bytes + * are also written to store the message's length (that happens internally, with + * the API function). sizeof( size_t ) is typically 4 bytes on a 32-bit + * architecture, so writing a 10 byte message to a message buffer on a 32-bit + * architecture will actually reduce the available space in the message buffer + * by 14 bytes (10 byte are used by the message, and 4 bytes to hold the length + * of the message). + */ + +#ifndef FREERTOS_MESSAGE_BUFFER_H +#define FREERTOS_MESSAGE_BUFFER_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include message_buffer.h" +#endif + +/* Message buffers are built onto of stream buffers. */ +#include "stream_buffer.h" + +/* *INDENT-OFF* */ +#if defined( __cplusplus ) + extern "C" { +#endif +/* *INDENT-ON* */ + +/** + * Type by which message buffers are referenced. For example, a call to + * xMessageBufferCreate() returns an MessageBufferHandle_t variable that can + * then be used as a parameter to xMessageBufferSend(), xMessageBufferReceive(), + * etc. Message buffer is essentially built as a stream buffer hence its handle + * is also set to same type as a stream buffer handle. + */ +typedef StreamBufferHandle_t MessageBufferHandle_t; + +/*-----------------------------------------------------------*/ + +/** + * message_buffer.h + * + * @code{c} + * MessageBufferHandle_t xMessageBufferCreate( size_t xBufferSizeBytes ); + * @endcode + * + * Creates a new message buffer using dynamically allocated memory. See + * xMessageBufferCreateStatic() for a version that uses statically allocated + * memory (memory that is allocated at compile time). + * + * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in + * FreeRTOSConfig.h for xMessageBufferCreate() to be available. + * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for + * xMessageBufferCreate() to be available. + * + * @param xBufferSizeBytes The total number of bytes (not messages) the message + * buffer will be able to hold at any one time. When a message is written to + * the message buffer an additional sizeof( size_t ) bytes are also written to + * store the message's length. sizeof( size_t ) is typically 4 bytes on a + * 32-bit architecture, so on most 32-bit architectures a 10 byte message will + * take up 14 bytes of message buffer space. + * + * @param pxSendCompletedCallback Callback invoked when a send operation to the + * message buffer is complete. If the parameter is NULL or xMessageBufferCreate() + * is called without the parameter, then it will use the default implementation + * provided by sbSEND_COMPLETED macro. To enable the callback, + * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h. + * + * @param pxReceiveCompletedCallback Callback invoked when a receive operation from + * the message buffer is complete. If the parameter is NULL or xMessageBufferCreate() + * is called without the parameter, it will use the default implementation provided + * by sbRECEIVE_COMPLETED macro. To enable the callback, + * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h. + * + * @return If NULL is returned, then the message buffer cannot be created + * because there is insufficient heap memory available for FreeRTOS to allocate + * the message buffer data structures and storage area. A non-NULL value being + * returned indicates that the message buffer has been created successfully - + * the returned value should be stored as the handle to the created message + * buffer. + * + * Example use: + * @code{c} + * + * void vAFunction( void ) + * { + * MessageBufferHandle_t xMessageBuffer; + * const size_t xMessageBufferSizeBytes = 100; + * + * // Create a message buffer that can hold 100 bytes. The memory used to hold + * // both the message buffer structure and the messages themselves is allocated + * // dynamically. Each message added to the buffer consumes an additional 4 + * // bytes which are used to hold the length of the message. + * xMessageBuffer = xMessageBufferCreate( xMessageBufferSizeBytes ); + * + * if( xMessageBuffer == NULL ) + * { + * // There was not enough heap memory space available to create the + * // message buffer. + * } + * else + * { + * // The message buffer was created successfully and can now be used. + * } + * + * @endcode + * \defgroup xMessageBufferCreate xMessageBufferCreate + * \ingroup MessageBufferManagement + */ +#define xMessageBufferCreate( xBufferSizeBytes ) \ + xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( size_t ) 0, sbTYPE_MESSAGE_BUFFER, NULL, NULL ) + +#if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) + #define xMessageBufferCreateWithCallback( xBufferSizeBytes, pxSendCompletedCallback, pxReceiveCompletedCallback ) \ + xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( size_t ) 0, sbTYPE_MESSAGE_BUFFER, ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) ) +#endif + +/** + * message_buffer.h + * + * @code{c} + * MessageBufferHandle_t xMessageBufferCreateStatic( size_t xBufferSizeBytes, + * uint8_t *pucMessageBufferStorageArea, + * StaticMessageBuffer_t *pxStaticMessageBuffer ); + * @endcode + * Creates a new message buffer using statically allocated memory. See + * xMessageBufferCreate() for a version that uses dynamically allocated memory. + * + * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for + * xMessageBufferCreateStatic() to be available. + * + * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the + * pucMessageBufferStorageArea parameter. When a message is written to the + * message buffer an additional sizeof( size_t ) bytes are also written to store + * the message's length. sizeof( size_t ) is typically 4 bytes on a 32-bit + * architecture, so on most 32-bit architecture a 10 byte message will take up + * 14 bytes of message buffer space. The maximum number of bytes that can be + * stored in the message buffer is actually (xBufferSizeBytes - 1). + * + * @param pucMessageBufferStorageArea Must point to a uint8_t array that is at + * least xBufferSizeBytes big. This is the array to which messages are + * copied when they are written to the message buffer. + * + * @param pxStaticMessageBuffer Must point to a variable of type + * StaticMessageBuffer_t, which will be used to hold the message buffer's data + * structure. + * + * @param pxSendCompletedCallback Callback invoked when a new message is sent to the message buffer. + * If the parameter is NULL or xMessageBufferCreate() is called without the parameter, then it will use the default + * implementation provided by sbSEND_COMPLETED macro. To enable the callback, + * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h. + * + * @param pxReceiveCompletedCallback Callback invoked when a message is read from a + * message buffer. If the parameter is NULL or xMessageBufferCreate() is called without the parameter, it will + * use the default implementation provided by sbRECEIVE_COMPLETED macro. To enable the callback, + * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h. + * + * @return If the message buffer is created successfully then a handle to the + * created message buffer is returned. If either pucMessageBufferStorageArea or + * pxStaticmessageBuffer are NULL then NULL is returned. + * + * Example use: + * @code{c} + * + * // Used to dimension the array used to hold the messages. The available space + * // will actually be one less than this, so 999. + #define STORAGE_SIZE_BYTES 1000 + * + * // Defines the memory that will actually hold the messages within the message + * // buffer. + * static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ]; + * + * // The variable used to hold the message buffer structure. + * StaticMessageBuffer_t xMessageBufferStruct; + * + * void MyFunction( void ) + * { + * MessageBufferHandle_t xMessageBuffer; + * + * xMessageBuffer = xMessageBufferCreateStatic( sizeof( ucStorageBuffer ), + * ucStorageBuffer, + * &xMessageBufferStruct ); + * + * // As neither the pucMessageBufferStorageArea or pxStaticMessageBuffer + * // parameters were NULL, xMessageBuffer will not be NULL, and can be used to + * // reference the created message buffer in other message buffer API calls. + * + * // Other code that uses the message buffer can go here. + * } + * + * @endcode + * \defgroup xMessageBufferCreateStatic xMessageBufferCreateStatic + * \ingroup MessageBufferManagement + */ +#define xMessageBufferCreateStatic( xBufferSizeBytes, pucMessageBufferStorageArea, pxStaticMessageBuffer ) \ + xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), 0, sbTYPE_MESSAGE_BUFFER, ( pucMessageBufferStorageArea ), ( pxStaticMessageBuffer ), NULL, NULL ) + +#if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) + #define xMessageBufferCreateStaticWithCallback( xBufferSizeBytes, pucMessageBufferStorageArea, pxStaticMessageBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback ) \ + xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), 0, sbTYPE_MESSAGE_BUFFER, ( pucMessageBufferStorageArea ), ( pxStaticMessageBuffer ), ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) ) +#endif + +/** + * message_buffer.h + * + * @code{c} + * BaseType_t xMessageBufferGetStaticBuffers( MessageBufferHandle_t xMessageBuffer, + * uint8_t ** ppucMessageBufferStorageArea, + * StaticMessageBuffer_t ** ppxStaticMessageBuffer ); + * @endcode + * + * Retrieve pointers to a statically created message buffer's data structure + * buffer and storage area buffer. These are the same buffers that are supplied + * at the time of creation. + * + * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for + * xMessageBufferGetStaticBuffers() to be available. + * + * @param xMessageBuffer The message buffer for which to retrieve the buffers. + * + * @param ppucMessageBufferStorageArea Used to return a pointer to the + * message buffer's storage area buffer. + * + * @param ppxStaticMessageBuffer Used to return a pointer to the message + * buffer's data structure buffer. + * + * @return pdTRUE if buffers were retrieved, pdFALSE otherwise.. + * + * \defgroup xMessageBufferGetStaticBuffers xMessageBufferGetStaticBuffers + * \ingroup MessageBufferManagement + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + #define xMessageBufferGetStaticBuffers( xMessageBuffer, ppucMessageBufferStorageArea, ppxStaticMessageBuffer ) \ + xStreamBufferGetStaticBuffers( ( xMessageBuffer ), ( ppucMessageBufferStorageArea ), ( ppxStaticMessageBuffer ) ) +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +/** + * message_buffer.h + * + * @code{c} + * size_t xMessageBufferSend( MessageBufferHandle_t xMessageBuffer, + * const void *pvTxData, + * size_t xDataLengthBytes, + * TickType_t xTicksToWait ); + * @endcode + * + * Sends a discrete message to the message buffer. The message can be any + * length that fits within the buffer's free space, and is copied into the + * buffer. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must serialize calls to writing API functions + * (such as xStreamBufferSend()). Likewise, if there are to be multiple + * different readers then the application writer must serialize calls to reading + * API functions (such as xStreamBufferReceive()). One way to achieve such + * serialization in single core or SMP kernel is to place each API call inside a + * critical section and use a block time of 0. + * + * Use xMessageBufferSend() to write to a message buffer from a task. Use + * xMessageBufferSendFromISR() to write to a message buffer from an interrupt + * service routine (ISR). + * + * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for + * xMessageBufferSend() to be available. + * + * @param xMessageBuffer The handle of the message buffer to which a message is + * being sent. + * + * @param pvTxData A pointer to the message that is to be copied into the + * message buffer. + * + * @param xDataLengthBytes The length of the message. That is, the number of + * bytes to copy from pvTxData into the message buffer. When a message is + * written to the message buffer an additional sizeof( size_t ) bytes are also + * written to store the message's length. sizeof( size_t ) is typically 4 bytes + * on a 32-bit architecture, so on most 32-bit architecture setting + * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24 + * bytes (20 bytes of message data and 4 bytes to hold the message length). + * + * @param xTicksToWait The maximum amount of time the calling task should remain + * in the Blocked state to wait for enough space to become available in the + * message buffer, should the message buffer have insufficient space when + * xMessageBufferSend() is called. The calling task will never block if + * xTicksToWait is zero. The block time is specified in tick periods, so the + * absolute time it represents is dependent on the tick frequency. The macro + * pdMS_TO_TICKS() can be used to convert a time specified in milliseconds into + * a time specified in ticks. Setting xTicksToWait to portMAX_DELAY will cause + * the task to wait indefinitely (without timing out), provided + * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h. Tasks do not use any + * CPU time when they are in the Blocked state. + * + * @return The number of bytes written to the message buffer. If the call to + * xMessageBufferSend() times out before there was enough space to write the + * message into the message buffer then zero is returned. If the call did not + * time out then xDataLengthBytes is returned. + * + * Example use: + * @code{c} + * void vAFunction( MessageBufferHandle_t xMessageBuffer ) + * { + * size_t xBytesSent; + * uint8_t ucArrayToSend[] = { 0, 1, 2, 3 }; + * char *pcStringToSend = "String to send"; + * const TickType_t x100ms = pdMS_TO_TICKS( 100 ); + * + * // Send an array to the message buffer, blocking for a maximum of 100ms to + * // wait for enough space to be available in the message buffer. + * xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms ); + * + * if( xBytesSent != sizeof( ucArrayToSend ) ) + * { + * // The call to xMessageBufferSend() times out before there was enough + * // space in the buffer for the data to be written. + * } + * + * // Send the string to the message buffer. Return immediately if there is + * // not enough space in the buffer. + * xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 ); + * + * if( xBytesSent != strlen( pcStringToSend ) ) + * { + * // The string could not be added to the message buffer because there was + * // not enough free space in the buffer. + * } + * } + * @endcode + * \defgroup xMessageBufferSend xMessageBufferSend + * \ingroup MessageBufferManagement + */ +#define xMessageBufferSend( xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait ) \ + xStreamBufferSend( ( xMessageBuffer ), ( pvTxData ), ( xDataLengthBytes ), ( xTicksToWait ) ) + +/** + * message_buffer.h + * + * @code{c} + * size_t xMessageBufferSendFromISR( MessageBufferHandle_t xMessageBuffer, + * const void *pvTxData, + * size_t xDataLengthBytes, + * BaseType_t *pxHigherPriorityTaskWoken ); + * @endcode + * + * Interrupt safe version of the API function that sends a discrete message to + * the message buffer. The message can be any length that fits within the + * buffer's free space, and is copied into the buffer. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must serialize calls to writing API functions + * (such as xStreamBufferSend()). Likewise, if there are to be multiple + * different readers then the application writer must serialize calls to reading + * API functions (such as xStreamBufferReceive()). One way to achieve such + * serialization in single core or SMP kernel is to place each API call inside a + * critical section and use a block time of 0. + * + * Use xMessageBufferSend() to write to a message buffer from a task. Use + * xMessageBufferSendFromISR() to write to a message buffer from an interrupt + * service routine (ISR). + * + * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for + * xMessageBufferSendFromISR() to be available. + * + * @param xMessageBuffer The handle of the message buffer to which a message is + * being sent. + * + * @param pvTxData A pointer to the message that is to be copied into the + * message buffer. + * + * @param xDataLengthBytes The length of the message. That is, the number of + * bytes to copy from pvTxData into the message buffer. When a message is + * written to the message buffer an additional sizeof( size_t ) bytes are also + * written to store the message's length. sizeof( size_t ) is typically 4 bytes + * on a 32-bit architecture, so on most 32-bit architecture setting + * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24 + * bytes (20 bytes of message data and 4 bytes to hold the message length). + * + * @param pxHigherPriorityTaskWoken It is possible that a message buffer will + * have a task blocked on it waiting for data. Calling + * xMessageBufferSendFromISR() can make data available, and so cause a task that + * was waiting for data to leave the Blocked state. If calling + * xMessageBufferSendFromISR() causes a task to leave the Blocked state, and the + * unblocked task has a priority higher than the currently executing task (the + * task that was interrupted), then, internally, xMessageBufferSendFromISR() + * will set *pxHigherPriorityTaskWoken to pdTRUE. If + * xMessageBufferSendFromISR() sets this value to pdTRUE, then normally a + * context switch should be performed before the interrupt is exited. This will + * ensure that the interrupt returns directly to the highest priority Ready + * state task. *pxHigherPriorityTaskWoken should be set to pdFALSE before it + * is passed into the function. See the code example below for an example. + * + * @return The number of bytes actually written to the message buffer. If the + * message buffer didn't have enough free space for the message to be stored + * then 0 is returned, otherwise xDataLengthBytes is returned. + * + * Example use: + * @code{c} + * // A message buffer that has already been created. + * MessageBufferHandle_t xMessageBuffer; + * + * void vAnInterruptServiceRoutine( void ) + * { + * size_t xBytesSent; + * char *pcStringToSend = "String to send"; + * BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE. + * + * // Attempt to send the string to the message buffer. + * xBytesSent = xMessageBufferSendFromISR( xMessageBuffer, + * ( void * ) pcStringToSend, + * strlen( pcStringToSend ), + * &xHigherPriorityTaskWoken ); + * + * if( xBytesSent != strlen( pcStringToSend ) ) + * { + * // The string could not be added to the message buffer because there was + * // not enough free space in the buffer. + * } + * + * // If xHigherPriorityTaskWoken was set to pdTRUE inside + * // xMessageBufferSendFromISR() then a task that has a priority above the + * // priority of the currently executing task was unblocked and a context + * // switch should be performed to ensure the ISR returns to the unblocked + * // task. In most FreeRTOS ports this is done by simply passing + * // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the + * // variables value, and perform the context switch if necessary. Check the + * // documentation for the port in use for port specific instructions. + * portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + * } + * @endcode + * \defgroup xMessageBufferSendFromISR xMessageBufferSendFromISR + * \ingroup MessageBufferManagement + */ +#define xMessageBufferSendFromISR( xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken ) \ + xStreamBufferSendFromISR( ( xMessageBuffer ), ( pvTxData ), ( xDataLengthBytes ), ( pxHigherPriorityTaskWoken ) ) + +/** + * message_buffer.h + * + * @code{c} + * size_t xMessageBufferReceive( MessageBufferHandle_t xMessageBuffer, + * void *pvRxData, + * size_t xBufferLengthBytes, + * TickType_t xTicksToWait ); + * @endcode + * + * Receives a discrete message from a message buffer. Messages can be of + * variable length and are copied out of the buffer. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must serialize calls to writing API functions + * (such as xStreamBufferSend()). Likewise, if there are to be multiple + * different readers then the application writer must serialize calls to reading + * API functions (such as xStreamBufferReceive()). One way to achieve such + * serialization in single core or SMP kernel is to place each API call inside a + * critical section and use a block time of 0. + * + * Use xMessageBufferReceive() to read from a message buffer from a task. Use + * xMessageBufferReceiveFromISR() to read from a message buffer from an + * interrupt service routine (ISR). + * + * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for + * xMessageBufferReceive() to be available. + * + * @param xMessageBuffer The handle of the message buffer from which a message + * is being received. + * + * @param pvRxData A pointer to the buffer into which the received message is + * to be copied. + * + * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData + * parameter. This sets the maximum length of the message that can be received. + * If xBufferLengthBytes is too small to hold the next message then the message + * will be left in the message buffer and 0 will be returned. + * + * @param xTicksToWait The maximum amount of time the task should remain in the + * Blocked state to wait for a message, should the message buffer be empty. + * xMessageBufferReceive() will return immediately if xTicksToWait is zero and + * the message buffer is empty. The block time is specified in tick periods, so + * the absolute time it represents is dependent on the tick frequency. The + * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds + * into a time specified in ticks. Setting xTicksToWait to portMAX_DELAY will + * cause the task to wait indefinitely (without timing out), provided + * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h. Tasks do not use any + * CPU time when they are in the Blocked state. + * + * @return The length, in bytes, of the message read from the message buffer, if + * any. If xMessageBufferReceive() times out before a message became available + * then zero is returned. If the length of the message is greater than + * xBufferLengthBytes then the message will be left in the message buffer and + * zero is returned. + * + * Example use: + * @code{c} + * void vAFunction( MessageBuffer_t xMessageBuffer ) + * { + * uint8_t ucRxData[ 20 ]; + * size_t xReceivedBytes; + * const TickType_t xBlockTime = pdMS_TO_TICKS( 20 ); + * + * // Receive the next message from the message buffer. Wait in the Blocked + * // state (so not using any CPU processing time) for a maximum of 100ms for + * // a message to become available. + * xReceivedBytes = xMessageBufferReceive( xMessageBuffer, + * ( void * ) ucRxData, + * sizeof( ucRxData ), + * xBlockTime ); + * + * if( xReceivedBytes > 0 ) + * { + * // A ucRxData contains a message that is xReceivedBytes long. Process + * // the message here.... + * } + * } + * @endcode + * \defgroup xMessageBufferReceive xMessageBufferReceive + * \ingroup MessageBufferManagement + */ +#define xMessageBufferReceive( xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait ) \ + xStreamBufferReceive( ( xMessageBuffer ), ( pvRxData ), ( xBufferLengthBytes ), ( xTicksToWait ) ) + + +/** + * message_buffer.h + * + * @code{c} + * size_t xMessageBufferReceiveFromISR( MessageBufferHandle_t xMessageBuffer, + * void *pvRxData, + * size_t xBufferLengthBytes, + * BaseType_t *pxHigherPriorityTaskWoken ); + * @endcode + * + * An interrupt safe version of the API function that receives a discrete + * message from a message buffer. Messages can be of variable length and are + * copied out of the buffer. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must serialize calls to writing API functions + * (such as xStreamBufferSend()). Likewise, if there are to be multiple + * different readers then the application writer must serialize calls to reading + * API functions (such as xStreamBufferReceive()). One way to achieve such + * serialization in single core or SMP kernel is to place each API call inside a + * critical section and use a block time of 0. + * + * Use xMessageBufferReceive() to read from a message buffer from a task. Use + * xMessageBufferReceiveFromISR() to read from a message buffer from an + * interrupt service routine (ISR). + * + * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for + * xMessageBufferReceiveFromISR() to be available. + * + * @param xMessageBuffer The handle of the message buffer from which a message + * is being received. + * + * @param pvRxData A pointer to the buffer into which the received message is + * to be copied. + * + * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData + * parameter. This sets the maximum length of the message that can be received. + * If xBufferLengthBytes is too small to hold the next message then the message + * will be left in the message buffer and 0 will be returned. + * + * @param pxHigherPriorityTaskWoken It is possible that a message buffer will + * have a task blocked on it waiting for space to become available. Calling + * xMessageBufferReceiveFromISR() can make space available, and so cause a task + * that is waiting for space to leave the Blocked state. If calling + * xMessageBufferReceiveFromISR() causes a task to leave the Blocked state, and + * the unblocked task has a priority higher than the currently executing task + * (the task that was interrupted), then, internally, + * xMessageBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE. + * If xMessageBufferReceiveFromISR() sets this value to pdTRUE, then normally a + * context switch should be performed before the interrupt is exited. That will + * ensure the interrupt returns directly to the highest priority Ready state + * task. *pxHigherPriorityTaskWoken should be set to pdFALSE before it is + * passed into the function. See the code example below for an example. + * + * @return The length, in bytes, of the message read from the message buffer, if + * any. + * + * Example use: + * @code{c} + * // A message buffer that has already been created. + * MessageBuffer_t xMessageBuffer; + * + * void vAnInterruptServiceRoutine( void ) + * { + * uint8_t ucRxData[ 20 ]; + * size_t xReceivedBytes; + * BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE. + * + * // Receive the next message from the message buffer. + * xReceivedBytes = xMessageBufferReceiveFromISR( xMessageBuffer, + * ( void * ) ucRxData, + * sizeof( ucRxData ), + * &xHigherPriorityTaskWoken ); + * + * if( xReceivedBytes > 0 ) + * { + * // A ucRxData contains a message that is xReceivedBytes long. Process + * // the message here.... + * } + * + * // If xHigherPriorityTaskWoken was set to pdTRUE inside + * // xMessageBufferReceiveFromISR() then a task that has a priority above the + * // priority of the currently executing task was unblocked and a context + * // switch should be performed to ensure the ISR returns to the unblocked + * // task. In most FreeRTOS ports this is done by simply passing + * // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the + * // variables value, and perform the context switch if necessary. Check the + * // documentation for the port in use for port specific instructions. + * portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + * } + * @endcode + * \defgroup xMessageBufferReceiveFromISR xMessageBufferReceiveFromISR + * \ingroup MessageBufferManagement + */ +#define xMessageBufferReceiveFromISR( xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken ) \ + xStreamBufferReceiveFromISR( ( xMessageBuffer ), ( pvRxData ), ( xBufferLengthBytes ), ( pxHigherPriorityTaskWoken ) ) + +/** + * message_buffer.h + * + * @code{c} + * void vMessageBufferDelete( MessageBufferHandle_t xMessageBuffer ); + * @endcode + * + * Deletes a message buffer that was previously created using a call to + * xMessageBufferCreate() or xMessageBufferCreateStatic(). If the message + * buffer was created using dynamic memory (that is, by xMessageBufferCreate()), + * then the allocated memory is freed. + * + * A message buffer handle must not be used after the message buffer has been + * deleted. + * + * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for + * vMessageBufferDelete() to be available. + * + * @param xMessageBuffer The handle of the message buffer to be deleted. + * + */ +#define vMessageBufferDelete( xMessageBuffer ) \ + vStreamBufferDelete( xMessageBuffer ) + +/** + * message_buffer.h + * @code{c} + * BaseType_t xMessageBufferIsFull( MessageBufferHandle_t xMessageBuffer ); + * @endcode + * + * Tests to see if a message buffer is full. A message buffer is full if it + * cannot accept any more messages, of any size, until space is made available + * by a message being removed from the message buffer. + * + * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for + * xMessageBufferIsFull() to be available. + * + * @param xMessageBuffer The handle of the message buffer being queried. + * + * @return If the message buffer referenced by xMessageBuffer is full then + * pdTRUE is returned. Otherwise pdFALSE is returned. + */ +#define xMessageBufferIsFull( xMessageBuffer ) \ + xStreamBufferIsFull( xMessageBuffer ) + +/** + * message_buffer.h + * @code{c} + * BaseType_t xMessageBufferIsEmpty( MessageBufferHandle_t xMessageBuffer ); + * @endcode + * + * Tests to see if a message buffer is empty (does not contain any messages). + * + * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for + * xMessageBufferIsEmpty() to be available. + * + * @param xMessageBuffer The handle of the message buffer being queried. + * + * @return If the message buffer referenced by xMessageBuffer is empty then + * pdTRUE is returned. Otherwise pdFALSE is returned. + * + */ +#define xMessageBufferIsEmpty( xMessageBuffer ) \ + xStreamBufferIsEmpty( xMessageBuffer ) + +/** + * message_buffer.h + * @code{c} + * BaseType_t xMessageBufferReset( MessageBufferHandle_t xMessageBuffer ); + * @endcode + * + * Resets a message buffer to its initial empty state, discarding any message it + * contained. + * + * A message buffer can only be reset if there are no tasks blocked on it. + * + * Use xMessageBufferReset() to reset a message buffer from a task. + * Use xMessageBufferResetFromISR() to reset a message buffer from an + * interrupt service routine (ISR). + * + * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for + * xMessageBufferReset() to be available. + * + * @param xMessageBuffer The handle of the message buffer being reset. + * + * @return If the message buffer was reset then pdPASS is returned. If the + * message buffer could not be reset because either there was a task blocked on + * the message queue to wait for space to become available, or to wait for a + * a message to be available, then pdFAIL is returned. + * + * \defgroup xMessageBufferReset xMessageBufferReset + * \ingroup MessageBufferManagement + */ +#define xMessageBufferReset( xMessageBuffer ) \ + xStreamBufferReset( xMessageBuffer ) + + +/** + * message_buffer.h + * @code{c} + * BaseType_t xMessageBufferResetFromISR( MessageBufferHandle_t xMessageBuffer ); + * @endcode + * + * An interrupt safe version of the API function that resets the message buffer. + * Resets a message buffer to its initial empty state, discarding any message it + * contained. + * + * A message buffer can only be reset if there are no tasks blocked on it. + * + * Use xMessageBufferReset() to reset a message buffer from a task. + * Use xMessageBufferResetFromISR() to reset a message buffer from an + * interrupt service routine (ISR). + * + * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for + * xMessageBufferResetFromISR() to be available. + * + * @param xMessageBuffer The handle of the message buffer being reset. + * + * @return If the message buffer was reset then pdPASS is returned. If the + * message buffer could not be reset because either there was a task blocked on + * the message queue to wait for space to become available, or to wait for a + * a message to be available, then pdFAIL is returned. + * + * \defgroup xMessageBufferResetFromISR xMessageBufferResetFromISR + * \ingroup MessageBufferManagement + */ +#define xMessageBufferResetFromISR( xMessageBuffer ) \ + xStreamBufferResetFromISR( xMessageBuffer ) + +/** + * message_buffer.h + * @code{c} + * size_t xMessageBufferSpaceAvailable( MessageBufferHandle_t xMessageBuffer ); + * @endcode + * Returns the number of bytes of free space in the message buffer. + * + * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for + * xMessageBufferSpaceAvailable() to be available. + * + * @param xMessageBuffer The handle of the message buffer being queried. + * + * @return The number of bytes that can be written to the message buffer before + * the message buffer would be full. When a message is written to the message + * buffer an additional sizeof( size_t ) bytes are also written to store the + * message's length. sizeof( size_t ) is typically 4 bytes on a 32-bit + * architecture, so if xMessageBufferSpacesAvailable() returns 10, then the size + * of the largest message that can be written to the message buffer is 6 bytes. + * + * \defgroup xMessageBufferSpaceAvailable xMessageBufferSpaceAvailable + * \ingroup MessageBufferManagement + */ +#define xMessageBufferSpaceAvailable( xMessageBuffer ) \ + xStreamBufferSpacesAvailable( xMessageBuffer ) +#define xMessageBufferSpacesAvailable( xMessageBuffer ) \ + xStreamBufferSpacesAvailable( xMessageBuffer ) /* Corrects typo in original macro name. */ + +/** + * message_buffer.h + * @code{c} + * size_t xMessageBufferNextLengthBytes( MessageBufferHandle_t xMessageBuffer ); + * @endcode + * Returns the length (in bytes) of the next message in a message buffer. + * Useful if xMessageBufferReceive() returned 0 because the size of the buffer + * passed into xMessageBufferReceive() was too small to hold the next message. + * + * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for + * xMessageBufferNextLengthBytes() to be available. + * + * @param xMessageBuffer The handle of the message buffer being queried. + * + * @return The length (in bytes) of the next message in the message buffer, or 0 + * if the message buffer is empty. + * + * \defgroup xMessageBufferNextLengthBytes xMessageBufferNextLengthBytes + * \ingroup MessageBufferManagement + */ +#define xMessageBufferNextLengthBytes( xMessageBuffer ) \ + xStreamBufferNextMessageLengthBytes( xMessageBuffer ) + +/** + * message_buffer.h + * + * @code{c} + * BaseType_t xMessageBufferSendCompletedFromISR( MessageBufferHandle_t xMessageBuffer, BaseType_t *pxHigherPriorityTaskWoken ); + * @endcode + * + * For advanced users only. + * + * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when + * data is sent to a message buffer or stream buffer. If there was a task that + * was blocked on the message or stream buffer waiting for data to arrive then + * the sbSEND_COMPLETED() macro sends a notification to the task to remove it + * from the Blocked state. xMessageBufferSendCompletedFromISR() does the same + * thing. It is provided to enable application writers to implement their own + * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME. + * + * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for + * additional information. + * + * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for + * xMessageBufferSendCompletedFromISR() to be available. + * + * @param xMessageBuffer The handle of the stream buffer to which data was + * written. + * + * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be + * initialised to pdFALSE before it is passed into + * xMessageBufferSendCompletedFromISR(). If calling + * xMessageBufferSendCompletedFromISR() removes a task from the Blocked state, + * and the task has a priority above the priority of the currently running task, + * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a + * context switch should be performed before exiting the ISR. + * + * @return If a task was removed from the Blocked state then pdTRUE is returned. + * Otherwise pdFALSE is returned. + * + * \defgroup xMessageBufferSendCompletedFromISR xMessageBufferSendCompletedFromISR + * \ingroup StreamBufferManagement + */ +#define xMessageBufferSendCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) \ + xStreamBufferSendCompletedFromISR( ( xMessageBuffer ), ( pxHigherPriorityTaskWoken ) ) + +/** + * message_buffer.h + * + * @code{c} + * BaseType_t xMessageBufferReceiveCompletedFromISR( MessageBufferHandle_t xMessageBuffer, BaseType_t *pxHigherPriorityTaskWoken ); + * @endcode + * + * For advanced users only. + * + * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when + * data is read out of a message buffer or stream buffer. If there was a task + * that was blocked on the message or stream buffer waiting for data to arrive + * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to + * remove it from the Blocked state. xMessageBufferReceiveCompletedFromISR() + * does the same thing. It is provided to enable application writers to + * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT + * ANY OTHER TIME. + * + * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for + * additional information. + * + * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for + * xMessageBufferReceiveCompletedFromISR() to be available. + * + * @param xMessageBuffer The handle of the stream buffer from which data was + * read. + * + * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be + * initialised to pdFALSE before it is passed into + * xMessageBufferReceiveCompletedFromISR(). If calling + * xMessageBufferReceiveCompletedFromISR() removes a task from the Blocked state, + * and the task has a priority above the priority of the currently running task, + * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a + * context switch should be performed before exiting the ISR. + * + * @return If a task was removed from the Blocked state then pdTRUE is returned. + * Otherwise pdFALSE is returned. + * + * \defgroup xMessageBufferReceiveCompletedFromISR xMessageBufferReceiveCompletedFromISR + * \ingroup StreamBufferManagement + */ +#define xMessageBufferReceiveCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) \ + xStreamBufferReceiveCompletedFromISR( ( xMessageBuffer ), ( pxHigherPriorityTaskWoken ) ) + +/* *INDENT-OFF* */ +#if defined( __cplusplus ) + } /* extern "C" */ +#endif +/* *INDENT-ON* */ + +#endif /* !defined( FREERTOS_MESSAGE_BUFFER_H ) */ diff --git a/include/mpu_prototypes.h b/include/mpu_prototypes.h new file mode 100644 index 000000000..b4c0f4745 --- /dev/null +++ b/include/mpu_prototypes.h @@ -0,0 +1,495 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * When the MPU is used the standard (non MPU) API functions are mapped to + * equivalents that start "MPU_", the prototypes for which are defined in this + * header files. This will cause the application code to call the MPU_ version + * which wraps the non-MPU version with privilege promoting then demoting code, + * so the kernel code always runs will full privileges. + */ + + +#ifndef MPU_PROTOTYPES_H +#define MPU_PROTOTYPES_H + +typedef struct xTaskGenericNotifyParams +{ + TaskHandle_t xTaskToNotify; + UBaseType_t uxIndexToNotify; + uint32_t ulValue; + eNotifyAction eAction; + uint32_t * pulPreviousNotificationValue; +} xTaskGenericNotifyParams_t; + +typedef struct xTaskGenericNotifyWaitParams +{ + UBaseType_t uxIndexToWaitOn; + uint32_t ulBitsToClearOnEntry; + uint32_t ulBitsToClearOnExit; + uint32_t * pulNotificationValue; + TickType_t xTicksToWait; +} xTaskGenericNotifyWaitParams_t; + +typedef struct xTimerGenericCommandFromTaskParams +{ + TimerHandle_t xTimer; + BaseType_t xCommandID; + TickType_t xOptionalValue; + BaseType_t * pxHigherPriorityTaskWoken; + TickType_t xTicksToWait; +} xTimerGenericCommandFromTaskParams_t; + +typedef struct xEventGroupWaitBitsParams +{ + EventGroupHandle_t xEventGroup; + EventBits_t uxBitsToWaitFor; + BaseType_t xClearOnExit; + BaseType_t xWaitForAllBits; + TickType_t xTicksToWait; +} xEventGroupWaitBitsParams_t; + +/* MPU versions of task.h API functions. */ +void MPU_vTaskDelay( const TickType_t xTicksToDelay ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskResume( TaskHandle_t xTaskToResume ) FREERTOS_SYSTEM_CALL; +TickType_t MPU_xTaskGetTickCount( void ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) FREERTOS_SYSTEM_CALL; +TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) FREERTOS_SYSTEM_CALL; +void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) FREERTOS_SYSTEM_CALL; +configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) FREERTOS_SYSTEM_CALL; +configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, + UBaseType_t uxIndexToNotify, + uint32_t ulValue, + eNotifyAction eAction, + uint32_t * pulPreviousNotificationValue ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn, + uint32_t ulBitsToClearOnEntry, + uint32_t ulBitsToClearOnExit, + uint32_t * pulNotificationValue, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) FREERTOS_SYSTEM_CALL; +uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) FREERTOS_SYSTEM_CALL; +uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskGetSchedulerState( void ) FREERTOS_SYSTEM_CALL; + +/* Privileged only wrappers for Task APIs. These are needed so that + * the application can use opaque handles maintained in mpu_wrappers.c + * with all the APIs. */ +#if ( configUSE_MPU_WRAPPERS_V1 == 1 ) + + BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode, + const char * const pcName, + const configSTACK_DEPTH_TYPE uxStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * const pxCreatedTask ) FREERTOS_SYSTEM_CALL; + TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, + const char * const pcName, + const configSTACK_DEPTH_TYPE uxStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + StackType_t * const puxStackBuffer, + StaticTask_t * const pxTaskBuffer ) FREERTOS_SYSTEM_CALL; + void MPU_vTaskDelete( TaskHandle_t xTaskToDelete ) FREERTOS_SYSTEM_CALL; + void MPU_vTaskPrioritySet( TaskHandle_t xTask, + UBaseType_t uxNewPriority ) FREERTOS_SYSTEM_CALL; + TaskHandle_t MPU_xTaskGetHandle( const char * pcNameToQuery ) FREERTOS_SYSTEM_CALL; + BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, + void * pvParameter ) FREERTOS_SYSTEM_CALL; + void MPU_vTaskGetRunTimeStatistics( char * pcWriteBuffer, + size_t uxBufferLength ) FREERTOS_SYSTEM_CALL; + void MPU_vTaskListTasks( char * pcWriteBuffer, + size_t uxBufferLength ) FREERTOS_SYSTEM_CALL; + void MPU_vTaskSuspendAll( void ) FREERTOS_SYSTEM_CALL; + BaseType_t MPU_xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) FREERTOS_SYSTEM_CALL; + BaseType_t MPU_xTaskResumeAll( void ) FREERTOS_SYSTEM_CALL; + +#else /* #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode, + const char * const pcName, + const configSTACK_DEPTH_TYPE uxStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION; + TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, + const char * const pcName, + const configSTACK_DEPTH_TYPE uxStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + StackType_t * const puxStackBuffer, + StaticTask_t * const pxTaskBuffer ) PRIVILEGED_FUNCTION; + void MPU_vTaskDelete( TaskHandle_t xTaskToDelete ) PRIVILEGED_FUNCTION; + void MPU_vTaskPrioritySet( TaskHandle_t xTask, + UBaseType_t uxNewPriority ) PRIVILEGED_FUNCTION; + TaskHandle_t MPU_xTaskGetHandle( const char * pcNameToQuery ) PRIVILEGED_FUNCTION; + BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, + void * pvParameter ) PRIVILEGED_FUNCTION; + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + +char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION; +BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, + TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION; +BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, + TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION; +void MPU_vTaskAllocateMPURegions( TaskHandle_t xTaskToModify, + const MemoryRegion_t * const xRegions ) PRIVILEGED_FUNCTION; +BaseType_t MPU_xTaskGetStaticBuffers( TaskHandle_t xTask, + StackType_t ** ppuxStackBuffer, + StaticTask_t ** ppxTaskBuffer ) PRIVILEGED_FUNCTION; +UBaseType_t MPU_uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION; +UBaseType_t MPU_uxTaskBasePriorityGet( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION; +UBaseType_t MPU_uxTaskBasePriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION; +BaseType_t MPU_xTaskResumeFromISR( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION; +TaskHookFunction_t MPU_xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; +BaseType_t MPU_xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, + UBaseType_t uxIndexToNotify, + uint32_t ulValue, + eNotifyAction eAction, + uint32_t * pulPreviousNotificationValue, + BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; +void MPU_vTaskGenericNotifyGiveFromISR( TaskHandle_t xTaskToNotify, + UBaseType_t uxIndexToNotify, + BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; + +/* MPU versions of queue.h API functions. */ +BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) FREERTOS_SYSTEM_CALL; +void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) FREERTOS_SYSTEM_CALL; +void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL; +QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +void MPU_vQueueSetQueueNumber( QueueHandle_t xQueue, + UBaseType_t uxQueueNumber ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxQueueGetQueueNumber( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +uint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; + +/* Privileged only wrappers for Queue APIs. These are needed so that + * the application can use opaque handles maintained in mpu_wrappers.c + * with all the APIs. */ +#if ( configUSE_MPU_WRAPPERS_V1 == 1 ) + + void MPU_vQueueDelete( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; + QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL; + QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, + StaticQueue_t * pxStaticQueue ) FREERTOS_SYSTEM_CALL; + QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, + const UBaseType_t uxInitialCount ) FREERTOS_SYSTEM_CALL; + QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, + const UBaseType_t uxInitialCount, + StaticQueue_t * pxStaticQueue ) FREERTOS_SYSTEM_CALL; + QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength, + const UBaseType_t uxItemSize, + const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL; + QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, + const UBaseType_t uxItemSize, + uint8_t * pucQueueStorage, + StaticQueue_t * pxStaticQueue, + const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL; + QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength ) FREERTOS_SYSTEM_CALL; + QueueSetHandle_t MPU_xQueueCreateSetStatic( const UBaseType_t uxEventQueueLength, + uint8_t * pucQueueStorage, + StaticQueue_t * pxStaticQueue ) FREERTOS_SYSTEM_CALL; + BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL; + BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue, + BaseType_t xNewQueue ) FREERTOS_SYSTEM_CALL; + +#else /* #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + void MPU_vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; + QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) PRIVILEGED_FUNCTION; + QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, + StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION; + QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, + const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION; + QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, + const UBaseType_t uxInitialCount, + StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION; + QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength, + const UBaseType_t uxItemSize, + const uint8_t ucQueueType ) PRIVILEGED_FUNCTION; + QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, + const UBaseType_t uxItemSize, + uint8_t * pucQueueStorage, + StaticQueue_t * pxStaticQueue, + const uint8_t ucQueueType ) PRIVILEGED_FUNCTION; + QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION; + QueueSetHandle_t MPU_xQueueCreateSetStatic( const UBaseType_t uxEventQueueLength, + uint8_t * pucQueueStorage, + StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION; + BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION; + BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue, + BaseType_t xNewQueue ) PRIVILEGED_FUNCTION; + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + +BaseType_t MPU_xQueueGenericGetStaticBuffers( QueueHandle_t xQueue, + uint8_t ** ppucQueueStorage, + StaticQueue_t ** ppxStaticQueue ) PRIVILEGED_FUNCTION; +BaseType_t MPU_xQueueGenericSendFromISR( QueueHandle_t xQueue, + const void * const pvItemToQueue, + BaseType_t * const pxHigherPriorityTaskWoken, + const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION; +BaseType_t MPU_xQueueGiveFromISR( QueueHandle_t xQueue, + BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; +BaseType_t MPU_xQueuePeekFromISR( QueueHandle_t xQueue, + void * const pvBuffer ) PRIVILEGED_FUNCTION; +BaseType_t MPU_xQueueReceiveFromISR( QueueHandle_t xQueue, + void * const pvBuffer, + BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; +BaseType_t MPU_xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; +BaseType_t MPU_xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; +UBaseType_t MPU_uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; +TaskHandle_t MPU_xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION; +QueueSetMemberHandle_t MPU_xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION; + +/* MPU versions of timers.h API functions. */ +void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer, + const BaseType_t xCommandID, + const TickType_t xOptionalValue, + BaseType_t * const pxHigherPriorityTaskWoken, + const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) FREERTOS_SYSTEM_CALL; +const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; + +/* Privileged only wrappers for Timer APIs. These are needed so that + * the application can use opaque handles maintained in mpu_wrappers.c + * with all the APIs. */ +TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, + const TickType_t xTimerPeriodInTicks, + const BaseType_t xAutoReload, + void * const pvTimerID, + TimerCallbackFunction_t pxCallbackFunction ) PRIVILEGED_FUNCTION; +TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, + const TickType_t xTimerPeriodInTicks, + const BaseType_t xAutoReload, + void * const pvTimerID, + TimerCallbackFunction_t pxCallbackFunction, + StaticTimer_t * pxTimerBuffer ) PRIVILEGED_FUNCTION; +BaseType_t MPU_xTimerGetStaticBuffer( TimerHandle_t xTimer, + StaticTimer_t ** ppxTimerBuffer ) PRIVILEGED_FUNCTION; +BaseType_t MPU_xTimerGenericCommandFromISR( TimerHandle_t xTimer, + const BaseType_t xCommandID, + const TickType_t xOptionalValue, + BaseType_t * const pxHigherPriorityTaskWoken, + const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/* MPU versions of event_group.h API functions. */ +EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToWaitFor, + const BaseType_t xClearOnExit, + const BaseType_t xWaitForAllBits, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) FREERTOS_SYSTEM_CALL; +EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) FREERTOS_SYSTEM_CALL; +EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) FREERTOS_SYSTEM_CALL; +EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +#if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) FREERTOS_SYSTEM_CALL; + void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) FREERTOS_SYSTEM_CALL; +#endif /* #if ( configUSE_TRACE_FACILITY == 1 ) */ + +/* Privileged only wrappers for Event Group APIs. These are needed so that + * the application can use opaque handles maintained in mpu_wrappers.c + * with all the APIs. */ +#if ( configUSE_MPU_WRAPPERS_V1 == 1 ) + + EventGroupHandle_t MPU_xEventGroupCreate( void ) FREERTOS_SYSTEM_CALL; + EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) FREERTOS_SYSTEM_CALL; + void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) FREERTOS_SYSTEM_CALL; + +#else /* #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + EventGroupHandle_t MPU_xEventGroupCreate( void ) PRIVILEGED_FUNCTION; + EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) PRIVILEGED_FUNCTION; + void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION; + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + +BaseType_t MPU_xEventGroupGetStaticBuffer( EventGroupHandle_t xEventGroup, + StaticEventGroup_t ** ppxEventGroupBuffer ) PRIVILEGED_FUNCTION; +EventBits_t MPU_xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION; + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + BaseType_t MPU_xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) FREERTOS_SYSTEM_CALL; + BaseType_t MPU_xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + BaseType_t * pxHigherPriorityTaskWoken ) FREERTOS_SYSTEM_CALL; +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/* MPU versions of message/stream_buffer.h API functions. */ +size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) FREERTOS_SYSTEM_CALL; +size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; + +/* Privileged only wrappers for Stream Buffer APIs. These are needed so that + * the application can use opaque handles maintained in mpu_wrappers.c + * with all the APIs. */ +#if ( configUSE_MPU_WRAPPERS_V1 == 1 ) + + StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + BaseType_t xStreamBufferType, + StreamBufferCallbackFunction_t pxSendCompletedCallback, + StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) FREERTOS_SYSTEM_CALL; + StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + BaseType_t xStreamBufferType, + uint8_t * const pucStreamBufferStorageArea, + StaticStreamBuffer_t * const pxStaticStreamBuffer, + StreamBufferCallbackFunction_t pxSendCompletedCallback, + StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) FREERTOS_SYSTEM_CALL; + void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; + BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; + +#else /* #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + BaseType_t xStreamBufferType, + StreamBufferCallbackFunction_t pxSendCompletedCallback, + StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION; + StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + BaseType_t xStreamBufferType, + uint8_t * const pucStreamBufferStorageArea, + StaticStreamBuffer_t * const pxStaticStreamBuffer, + StreamBufferCallbackFunction_t pxSendCompletedCallback, + StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION; + void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + +BaseType_t MPU_xStreamBufferGetStaticBuffers( StreamBufferHandle_t xStreamBuffers, + uint8_t * ppucStreamBufferStorageArea, + StaticStreamBuffer_t * ppxStaticStreamBuffer ) PRIVILEGED_FUNCTION; +size_t MPU_xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; +size_t MPU_xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; +BaseType_t MPU_xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, + BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; +BaseType_t MPU_xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, + BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; +BaseType_t MPU_xStreamBufferResetFromISR( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + +#endif /* MPU_PROTOTYPES_H */ diff --git a/include/mpu_syscall_numbers.h b/include/mpu_syscall_numbers.h new file mode 100644 index 000000000..7c625a78d --- /dev/null +++ b/include/mpu_syscall_numbers.h @@ -0,0 +1,105 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef MPU_SYSCALL_NUMBERS_H +#define MPU_SYSCALL_NUMBERS_H + +/* Numbers assigned to various system calls. */ +#define SYSTEM_CALL_xTaskGenericNotify 0 +#define SYSTEM_CALL_xTaskGenericNotifyWait 1 +#define SYSTEM_CALL_xTimerGenericCommandFromTask 2 +#define SYSTEM_CALL_xEventGroupWaitBits 3 +#define SYSTEM_CALL_xTaskDelayUntil 4 +#define SYSTEM_CALL_xTaskAbortDelay 5 +#define SYSTEM_CALL_vTaskDelay 6 +#define SYSTEM_CALL_uxTaskPriorityGet 7 +#define SYSTEM_CALL_eTaskGetState 8 +#define SYSTEM_CALL_vTaskGetInfo 9 +#define SYSTEM_CALL_xTaskGetIdleTaskHandle 10 +#define SYSTEM_CALL_vTaskSuspend 11 +#define SYSTEM_CALL_vTaskResume 12 +#define SYSTEM_CALL_xTaskGetTickCount 13 +#define SYSTEM_CALL_uxTaskGetNumberOfTasks 14 +#define SYSTEM_CALL_ulTaskGetRunTimeCounter 15 +#define SYSTEM_CALL_ulTaskGetRunTimePercent 16 +#define SYSTEM_CALL_ulTaskGetIdleRunTimePercent 17 +#define SYSTEM_CALL_ulTaskGetIdleRunTimeCounter 18 +#define SYSTEM_CALL_vTaskSetApplicationTaskTag 19 +#define SYSTEM_CALL_xTaskGetApplicationTaskTag 20 +#define SYSTEM_CALL_vTaskSetThreadLocalStoragePointer 21 +#define SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer 22 +#define SYSTEM_CALL_uxTaskGetSystemState 23 +#define SYSTEM_CALL_uxTaskGetStackHighWaterMark 24 +#define SYSTEM_CALL_uxTaskGetStackHighWaterMark2 25 +#define SYSTEM_CALL_xTaskGetCurrentTaskHandle 26 +#define SYSTEM_CALL_xTaskGetSchedulerState 27 +#define SYSTEM_CALL_vTaskSetTimeOutState 28 +#define SYSTEM_CALL_xTaskCheckForTimeOut 29 +#define SYSTEM_CALL_ulTaskGenericNotifyTake 30 +#define SYSTEM_CALL_xTaskGenericNotifyStateClear 31 +#define SYSTEM_CALL_ulTaskGenericNotifyValueClear 32 +#define SYSTEM_CALL_xQueueGenericSend 33 +#define SYSTEM_CALL_uxQueueMessagesWaiting 34 +#define SYSTEM_CALL_uxQueueSpacesAvailable 35 +#define SYSTEM_CALL_xQueueReceive 36 +#define SYSTEM_CALL_xQueuePeek 37 +#define SYSTEM_CALL_xQueueSemaphoreTake 38 +#define SYSTEM_CALL_xQueueGetMutexHolder 39 +#define SYSTEM_CALL_xQueueTakeMutexRecursive 40 +#define SYSTEM_CALL_xQueueGiveMutexRecursive 41 +#define SYSTEM_CALL_xQueueSelectFromSet 42 +#define SYSTEM_CALL_xQueueAddToSet 43 +#define SYSTEM_CALL_vQueueAddToRegistry 44 +#define SYSTEM_CALL_vQueueUnregisterQueue 45 +#define SYSTEM_CALL_pcQueueGetName 46 +#define SYSTEM_CALL_pvTimerGetTimerID 47 +#define SYSTEM_CALL_vTimerSetTimerID 48 +#define SYSTEM_CALL_xTimerIsTimerActive 49 +#define SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle 50 +#define SYSTEM_CALL_pcTimerGetName 51 +#define SYSTEM_CALL_vTimerSetReloadMode 52 +#define SYSTEM_CALL_xTimerGetReloadMode 53 +#define SYSTEM_CALL_uxTimerGetReloadMode 54 +#define SYSTEM_CALL_xTimerGetPeriod 55 +#define SYSTEM_CALL_xTimerGetExpiryTime 56 +#define SYSTEM_CALL_xEventGroupClearBits 57 +#define SYSTEM_CALL_xEventGroupSetBits 58 +#define SYSTEM_CALL_xEventGroupSync 59 +#define SYSTEM_CALL_uxEventGroupGetNumber 60 +#define SYSTEM_CALL_vEventGroupSetNumber 61 +#define SYSTEM_CALL_xStreamBufferSend 62 +#define SYSTEM_CALL_xStreamBufferReceive 63 +#define SYSTEM_CALL_xStreamBufferIsFull 64 +#define SYSTEM_CALL_xStreamBufferIsEmpty 65 +#define SYSTEM_CALL_xStreamBufferSpacesAvailable 66 +#define SYSTEM_CALL_xStreamBufferBytesAvailable 67 +#define SYSTEM_CALL_xStreamBufferSetTriggerLevel 68 +#define SYSTEM_CALL_xStreamBufferNextMessageLengthBytes 69 +#define NUM_SYSTEM_CALLS 70 /* Total number of system calls. */ + +#endif /* MPU_SYSCALL_NUMBERS_H */ diff --git a/include/mpu_wrappers.h b/include/mpu_wrappers.h new file mode 100644 index 000000000..3b4738e96 --- /dev/null +++ b/include/mpu_wrappers.h @@ -0,0 +1,292 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef MPU_WRAPPERS_H +#define MPU_WRAPPERS_H + +/* This file redefines API functions to be called through a wrapper macro, but + * only for ports that are using the MPU. */ +#if ( portUSING_MPU_WRAPPERS == 1 ) + +/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE will be defined when this file is + * included from queue.c or task.c to prevent it from having an effect within + * those files. */ + #ifndef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* + * Map standard (non MPU) API functions to equivalents that start + * "MPU_". This will cause the application code to call the MPU_ + * version, which wraps the non-MPU version with privilege promoting + * then demoting code, so the kernel code always runs will full + * privileges. + */ + +/* Map standard task.h API functions to the MPU equivalents. */ + #define vTaskDelay MPU_vTaskDelay + #define xTaskDelayUntil MPU_xTaskDelayUntil + #define xTaskAbortDelay MPU_xTaskAbortDelay + #define uxTaskPriorityGet MPU_uxTaskPriorityGet + #define eTaskGetState MPU_eTaskGetState + #define vTaskGetInfo MPU_vTaskGetInfo + #define vTaskSuspend MPU_vTaskSuspend + #define vTaskResume MPU_vTaskResume + #define xTaskGetTickCount MPU_xTaskGetTickCount + #define uxTaskGetNumberOfTasks MPU_uxTaskGetNumberOfTasks + #define uxTaskGetStackHighWaterMark MPU_uxTaskGetStackHighWaterMark + #define uxTaskGetStackHighWaterMark2 MPU_uxTaskGetStackHighWaterMark2 + #define vTaskSetApplicationTaskTag MPU_vTaskSetApplicationTaskTag + #define xTaskGetApplicationTaskTag MPU_xTaskGetApplicationTaskTag + #define vTaskSetThreadLocalStoragePointer MPU_vTaskSetThreadLocalStoragePointer + #define pvTaskGetThreadLocalStoragePointer MPU_pvTaskGetThreadLocalStoragePointer + #define xTaskGetIdleTaskHandle MPU_xTaskGetIdleTaskHandle + #define uxTaskGetSystemState MPU_uxTaskGetSystemState + #define ulTaskGetIdleRunTimeCounter MPU_ulTaskGetIdleRunTimeCounter + #define ulTaskGetIdleRunTimePercent MPU_ulTaskGetIdleRunTimePercent + #define xTaskGenericNotify MPU_xTaskGenericNotify + #define xTaskGenericNotifyWait MPU_xTaskGenericNotifyWait + #define ulTaskGenericNotifyTake MPU_ulTaskGenericNotifyTake + #define xTaskGenericNotifyStateClear MPU_xTaskGenericNotifyStateClear + #define ulTaskGenericNotifyValueClear MPU_ulTaskGenericNotifyValueClear + #define vTaskSetTimeOutState MPU_vTaskSetTimeOutState + #define xTaskCheckForTimeOut MPU_xTaskCheckForTimeOut + #define xTaskGetCurrentTaskHandle MPU_xTaskGetCurrentTaskHandle + #define xTaskGetSchedulerState MPU_xTaskGetSchedulerState + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + #define ulTaskGetRunTimeCounter MPU_ulTaskGetRunTimeCounter + #define ulTaskGetRunTimePercent MPU_ulTaskGetRunTimePercent + #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/* Privileged only wrappers for Task APIs. These are needed so that + * the application can use opaque handles maintained in mpu_wrappers.c + * with all the APIs. */ + #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) + +/* These are not needed in v2 because they do not take a task + * handle and therefore, no lookup is needed. Needed in v1 because + * these are available as system calls in v1. */ + #define vTaskGetRunTimeStatistics MPU_vTaskGetRunTimeStatistics + #define vTaskListTasks MPU_vTaskListTasks + #define vTaskSuspendAll MPU_vTaskSuspendAll + #define xTaskCatchUpTicks MPU_xTaskCatchUpTicks + #define xTaskResumeAll MPU_xTaskResumeAll + #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #define xTaskCreate MPU_xTaskCreate + #define xTaskCreateStatic MPU_xTaskCreateStatic + #define vTaskDelete MPU_vTaskDelete + #define vTaskPrioritySet MPU_vTaskPrioritySet + #define xTaskGetHandle MPU_xTaskGetHandle + #define xTaskCallApplicationTaskHook MPU_xTaskCallApplicationTaskHook + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + #define pcTaskGetName MPU_pcTaskGetName + #define xTaskCreateRestricted MPU_xTaskCreateRestricted + #define xTaskCreateRestrictedStatic MPU_xTaskCreateRestrictedStatic + #define vTaskAllocateMPURegions MPU_vTaskAllocateMPURegions + #define xTaskGetStaticBuffers MPU_xTaskGetStaticBuffers + #define uxTaskPriorityGetFromISR MPU_uxTaskPriorityGetFromISR + #define uxTaskBasePriorityGet MPU_uxTaskBasePriorityGet + #define uxTaskBasePriorityGetFromISR MPU_uxTaskBasePriorityGetFromISR + #define xTaskResumeFromISR MPU_xTaskResumeFromISR + #define xTaskGetApplicationTaskTagFromISR MPU_xTaskGetApplicationTaskTagFromISR + #define xTaskGenericNotifyFromISR MPU_xTaskGenericNotifyFromISR + #define vTaskGenericNotifyGiveFromISR MPU_vTaskGenericNotifyGiveFromISR + #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/* Map standard queue.h API functions to the MPU equivalents. */ + #define xQueueGenericSend MPU_xQueueGenericSend + #define xQueueReceive MPU_xQueueReceive + #define xQueuePeek MPU_xQueuePeek + #define xQueueSemaphoreTake MPU_xQueueSemaphoreTake + #define uxQueueMessagesWaiting MPU_uxQueueMessagesWaiting + #define uxQueueSpacesAvailable MPU_uxQueueSpacesAvailable + #define xQueueGetMutexHolder MPU_xQueueGetMutexHolder + #define xQueueTakeMutexRecursive MPU_xQueueTakeMutexRecursive + #define xQueueGiveMutexRecursive MPU_xQueueGiveMutexRecursive + #define xQueueAddToSet MPU_xQueueAddToSet + #define xQueueSelectFromSet MPU_xQueueSelectFromSet + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + #define vQueueAddToRegistry MPU_vQueueAddToRegistry + #define vQueueUnregisterQueue MPU_vQueueUnregisterQueue + #define pcQueueGetName MPU_pcQueueGetName + #endif /* #if ( configQUEUE_REGISTRY_SIZE > 0 ) */ + +/* Privileged only wrappers for Queue APIs. These are needed so that + * the application can use opaque handles maintained in mpu_wrappers.c + * with all the APIs. */ + #define vQueueDelete MPU_vQueueDelete + #define xQueueCreateMutex MPU_xQueueCreateMutex + #define xQueueCreateMutexStatic MPU_xQueueCreateMutexStatic + #define xQueueCreateCountingSemaphore MPU_xQueueCreateCountingSemaphore + #define xQueueCreateCountingSemaphoreStatic MPU_xQueueCreateCountingSemaphoreStatic + #define xQueueGenericCreate MPU_xQueueGenericCreate + #define xQueueGenericCreateStatic MPU_xQueueGenericCreateStatic + #define xQueueGenericReset MPU_xQueueGenericReset + #define xQueueCreateSet MPU_xQueueCreateSet + #define xQueueCreateSetStatic MPU_xQueueCreateSetStatic + #define xQueueRemoveFromSet MPU_xQueueRemoveFromSet + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + #define xQueueGenericGetStaticBuffers MPU_xQueueGenericGetStaticBuffers + #define xQueueGenericSendFromISR MPU_xQueueGenericSendFromISR + #define xQueueGiveFromISR MPU_xQueueGiveFromISR + #define xQueuePeekFromISR MPU_xQueuePeekFromISR + #define xQueueReceiveFromISR MPU_xQueueReceiveFromISR + #define xQueueIsQueueEmptyFromISR MPU_xQueueIsQueueEmptyFromISR + #define xQueueIsQueueFullFromISR MPU_xQueueIsQueueFullFromISR + #define uxQueueMessagesWaitingFromISR MPU_uxQueueMessagesWaitingFromISR + #define xQueueGetMutexHolderFromISR MPU_xQueueGetMutexHolderFromISR + #define xQueueSelectFromSetFromISR MPU_xQueueSelectFromSetFromISR + #endif /* if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/* Map standard timer.h API functions to the MPU equivalents. */ + #define pvTimerGetTimerID MPU_pvTimerGetTimerID + #define vTimerSetTimerID MPU_vTimerSetTimerID + #define xTimerIsTimerActive MPU_xTimerIsTimerActive + #define xTimerGetTimerDaemonTaskHandle MPU_xTimerGetTimerDaemonTaskHandle + #define xTimerGenericCommandFromTask MPU_xTimerGenericCommandFromTask + #define pcTimerGetName MPU_pcTimerGetName + #define vTimerSetReloadMode MPU_vTimerSetReloadMode + #define uxTimerGetReloadMode MPU_uxTimerGetReloadMode + #define xTimerGetPeriod MPU_xTimerGetPeriod + #define xTimerGetExpiryTime MPU_xTimerGetExpiryTime + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + #define xTimerGetReloadMode MPU_xTimerGetReloadMode + #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/* Privileged only wrappers for Timer APIs. These are needed so that + * the application can use opaque handles maintained in mpu_wrappers.c + * with all the APIs. */ + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + #define xTimerCreate MPU_xTimerCreate + #define xTimerCreateStatic MPU_xTimerCreateStatic + #define xTimerGetStaticBuffer MPU_xTimerGetStaticBuffer + #define xTimerGenericCommandFromISR MPU_xTimerGenericCommandFromISR + #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/* Map standard event_group.h API functions to the MPU equivalents. */ + #define xEventGroupWaitBits MPU_xEventGroupWaitBits + #define xEventGroupClearBits MPU_xEventGroupClearBits + #define xEventGroupSetBits MPU_xEventGroupSetBits + #define xEventGroupSync MPU_xEventGroupSync + + #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + #define uxEventGroupGetNumber MPU_uxEventGroupGetNumber + #define vEventGroupSetNumber MPU_vEventGroupSetNumber + #endif /* #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ + +/* Privileged only wrappers for Event Group APIs. These are needed so that + * the application can use opaque handles maintained in mpu_wrappers.c + * with all the APIs. */ + #define xEventGroupCreate MPU_xEventGroupCreate + #define xEventGroupCreateStatic MPU_xEventGroupCreateStatic + #define vEventGroupDelete MPU_vEventGroupDelete + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + #define xEventGroupGetStaticBuffer MPU_xEventGroupGetStaticBuffer + #define xEventGroupClearBitsFromISR MPU_xEventGroupClearBitsFromISR + #define xEventGroupSetBitsFromISR MPU_xEventGroupSetBitsFromISR + #define xEventGroupGetBitsFromISR MPU_xEventGroupGetBitsFromISR + #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/* Map standard message/stream_buffer.h API functions to the MPU + * equivalents. */ + #define xStreamBufferSend MPU_xStreamBufferSend + #define xStreamBufferReceive MPU_xStreamBufferReceive + #define xStreamBufferIsFull MPU_xStreamBufferIsFull + #define xStreamBufferIsEmpty MPU_xStreamBufferIsEmpty + #define xStreamBufferSpacesAvailable MPU_xStreamBufferSpacesAvailable + #define xStreamBufferBytesAvailable MPU_xStreamBufferBytesAvailable + #define xStreamBufferSetTriggerLevel MPU_xStreamBufferSetTriggerLevel + #define xStreamBufferNextMessageLengthBytes MPU_xStreamBufferNextMessageLengthBytes + +/* Privileged only wrappers for Stream Buffer APIs. These are needed so that + * the application can use opaque handles maintained in mpu_wrappers.c + * with all the APIs. */ + + #define xStreamBufferGenericCreate MPU_xStreamBufferGenericCreate + #define xStreamBufferGenericCreateStatic MPU_xStreamBufferGenericCreateStatic + #define vStreamBufferDelete MPU_vStreamBufferDelete + #define xStreamBufferReset MPU_xStreamBufferReset + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + #define xStreamBufferGetStaticBuffers MPU_xStreamBufferGetStaticBuffers + #define xStreamBufferSendFromISR MPU_xStreamBufferSendFromISR + #define xStreamBufferReceiveFromISR MPU_xStreamBufferReceiveFromISR + #define xStreamBufferSendCompletedFromISR MPU_xStreamBufferSendCompletedFromISR + #define xStreamBufferReceiveCompletedFromISR MPU_xStreamBufferReceiveCompletedFromISR + #define xStreamBufferResetFromISR MPU_xStreamBufferResetFromISR + #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + #define vGrantAccessToTask( xTask, xTaskToGrantAccess ) vGrantAccessToKernelObject( ( xTask ), ( int32_t ) ( xTaskToGrantAccess ) ) + #define vRevokeAccessToTask( xTask, xTaskToRevokeAccess ) vRevokeAccessToKernelObject( ( xTask ), ( int32_t ) ( xTaskToRevokeAccess ) ) + + #define vGrantAccessToSemaphore( xTask, xSemaphoreToGrantAccess ) vGrantAccessToKernelObject( ( xTask ), ( int32_t ) ( xSemaphoreToGrantAccess ) ) + #define vRevokeAccessToSemaphore( xTask, xSemaphoreToRevokeAccess ) vRevokeAccessToKernelObject( ( xTask ), ( int32_t ) ( xSemaphoreToRevokeAccess ) ) + + #define vGrantAccessToQueue( xTask, xQueueToGrantAccess ) vGrantAccessToKernelObject( ( xTask ), ( int32_t ) ( xQueueToGrantAccess ) ) + #define vRevokeAccessToQueue( xTask, xQueueToRevokeAccess ) vRevokeAccessToKernelObject( ( xTask ), ( int32_t ) ( xQueueToRevokeAccess ) ) + + #define vGrantAccessToQueueSet( xTask, xQueueSetToGrantAccess ) vGrantAccessToKernelObject( ( xTask ), ( int32_t ) ( xQueueSetToGrantAccess ) ) + #define vRevokeAccessToQueueSet( xTask, xQueueSetToRevokeAccess ) vRevokeAccessToKernelObject( ( xTask ), ( int32_t ) ( xQueueSetToRevokeAccess ) ) + + #define vGrantAccessToEventGroup( xTask, xEventGroupToGrantAccess ) vGrantAccessToKernelObject( ( xTask ), ( int32_t ) ( xEventGroupToGrantAccess ) ) + #define vRevokeAccessToEventGroup( xTask, xEventGroupToRevokeAccess ) vRevokeAccessToKernelObject( ( xTask ), ( int32_t ) ( xEventGroupToRevokeAccess ) ) + + #define vGrantAccessToStreamBuffer( xTask, xStreamBufferToGrantAccess ) vGrantAccessToKernelObject( ( xTask ), ( int32_t ) ( xStreamBufferToGrantAccess ) ) + #define vRevokeAccessToStreamBuffer( xTask, xStreamBufferToRevokeAccess ) vRevokeAccessToKernelObject( ( xTask ), ( int32_t ) ( xStreamBufferToRevokeAccess ) ) + + #define vGrantAccessToMessageBuffer( xTask, xMessageBufferToGrantAccess ) vGrantAccessToKernelObject( ( xTask ), ( int32_t ) ( xMessageBufferToGrantAccess ) ) + #define vRevokeAccessToMessageBuffer( xTask, xMessageBufferToRevokeAccess ) vRevokeAccessToKernelObject( ( xTask ), ( int32_t ) ( xMessageBufferToRevokeAccess ) ) + + #define vGrantAccessToTimer( xTask, xTimerToGrantAccess ) vGrantAccessToKernelObject( ( xTask ), ( int32_t ) ( xTimerToGrantAccess ) ) + #define vRevokeAccessToTimer( xTask, xTimerToRevokeAccess ) vRevokeAccessToKernelObject( ( xTask ), ( int32_t ) ( xTimerToRevokeAccess ) ) + + #endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ + + #endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */ + + #define PRIVILEGED_FUNCTION __attribute__( ( section( "privileged_functions" ) ) ) + #define PRIVILEGED_DATA __attribute__( ( section( "privileged_data" ) ) ) + #define FREERTOS_SYSTEM_CALL __attribute__( ( section( "freertos_system_calls" ) ) ) + +#else /* portUSING_MPU_WRAPPERS */ + + #define PRIVILEGED_FUNCTION + #define PRIVILEGED_DATA + #define FREERTOS_SYSTEM_CALL + +#endif /* portUSING_MPU_WRAPPERS */ + + +#endif /* MPU_WRAPPERS_H */ diff --git a/include/newlib-freertos.h b/include/newlib-freertos.h new file mode 100644 index 000000000..4414d24ad --- /dev/null +++ b/include/newlib-freertos.h @@ -0,0 +1,62 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef INC_NEWLIB_FREERTOS_H +#define INC_NEWLIB_FREERTOS_H + +/* Note Newlib support has been included by popular demand, but is not + * used by the FreeRTOS maintainers themselves. FreeRTOS is not + * responsible for resulting newlib operation. User must be familiar with + * newlib and must provide system-wide implementations of the necessary + * stubs. Be warned that (at the time of writing) the current newlib design + * implements a system-wide malloc() that must be provided with locks. + * + * See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html + * for additional information. */ + +#include + +#define configUSE_C_RUNTIME_TLS_SUPPORT 1 + +#ifndef configTLS_BLOCK_TYPE + #define configTLS_BLOCK_TYPE struct _reent +#endif + +#ifndef configINIT_TLS_BLOCK + #define configINIT_TLS_BLOCK( xTLSBlock, pxTopOfStack ) _REENT_INIT_PTR( &( xTLSBlock ) ) +#endif + +#ifndef configSET_TLS_BLOCK + #define configSET_TLS_BLOCK( xTLSBlock ) ( _impure_ptr = &( xTLSBlock ) ) +#endif + +#ifndef configDEINIT_TLS_BLOCK + #define configDEINIT_TLS_BLOCK( xTLSBlock ) _reclaim_reent( &( xTLSBlock ) ) +#endif + +#endif /* INC_NEWLIB_FREERTOS_H */ diff --git a/include/picolibc-freertos.h b/include/picolibc-freertos.h new file mode 100644 index 000000000..5cf01afa8 --- /dev/null +++ b/include/picolibc-freertos.h @@ -0,0 +1,91 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef INC_PICOLIBC_FREERTOS_H +#define INC_PICOLIBC_FREERTOS_H + +/* Use picolibc TLS support to allocate space for __thread variables, + * initialize them at thread creation and set the TLS context at + * thread switch time. + * + * See the picolibc TLS docs: + * https://github.com/picolibc/picolibc/blob/main/doc/tls.md + * for additional information. */ + +#include + +#define configUSE_C_RUNTIME_TLS_SUPPORT 1 + +#define configTLS_BLOCK_TYPE void * + +#define picolibcTLS_SIZE ( ( portPOINTER_SIZE_TYPE ) _tls_size() ) +#define picolibcSTACK_ALIGNMENT_MASK ( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) + +#if __PICOLIBC_MAJOR__ > 1 || __PICOLIBC_MINOR__ >= 8 + +/* Picolibc 1.8 and newer have explicit alignment values provided + * by the _tls_align() inline */ + #define picolibcTLS_ALIGNMENT_MASK ( ( portPOINTER_SIZE_TYPE ) ( _tls_align() - 1 ) ) +#else + +/* For older Picolibc versions, use the general port alignment value */ + #define picolibcTLS_ALIGNMENT_MASK ( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) +#endif + +/* Allocate thread local storage block off the end of the + * stack. The picolibcTLS_SIZE macro returns the size (in + * bytes) of the total TLS area used by the application. + * Calculate the top of stack address. */ +#if ( portSTACK_GROWTH < 0 ) + + #define configINIT_TLS_BLOCK( xTLSBlock, pxTopOfStack ) \ + do { \ + xTLSBlock = ( void * ) ( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) - \ + picolibcTLS_SIZE ) & \ + ~picolibcTLS_ALIGNMENT_MASK ); \ + pxTopOfStack = ( StackType_t * ) ( ( ( ( portPOINTER_SIZE_TYPE ) xTLSBlock ) - 1 ) & \ + ~picolibcSTACK_ALIGNMENT_MASK ); \ + _init_tls( xTLSBlock ); \ + } while( 0 ) +#else /* portSTACK_GROWTH */ + #define configINIT_TLS_BLOCK( xTLSBlock, pxTopOfStack ) \ + do { \ + xTLSBlock = ( void * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack + \ + picolibcTLS_ALIGNMENT_MASK ) & ~picolibcTLS_ALIGNMENT_MASK ); \ + pxTopOfStack = ( StackType_t * ) ( ( ( ( ( portPOINTER_SIZE_TYPE ) xTLSBlock ) + \ + picolibcTLS_SIZE ) + picolibcSTACK_ALIGNMENT_MASK ) & \ + ~picolibcSTACK_ALIGNMENT_MASK ); \ + _init_tls( xTLSBlock ); \ + } while( 0 ) +#endif /* portSTACK_GROWTH */ + +#define configSET_TLS_BLOCK( xTLSBlock ) _set_tls( xTLSBlock ) + +#define configDEINIT_TLS_BLOCK( xTLSBlock ) + +#endif /* INC_PICOLIBC_FREERTOS_H */ diff --git a/include/portable.h b/include/portable.h new file mode 100644 index 000000000..68e11e793 --- /dev/null +++ b/include/portable.h @@ -0,0 +1,290 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Portable layer API. Each function must be defined for each port. +*----------------------------------------------------------*/ + +#ifndef PORTABLE_H +#define PORTABLE_H + +/* Each FreeRTOS port has a unique portmacro.h header file. Originally a + * pre-processor definition was used to ensure the pre-processor found the correct + * portmacro.h file for the port being used. That scheme was deprecated in favour + * of setting the compiler's include path such that it found the correct + * portmacro.h file - removing the need for the constant and allowing the + * portmacro.h file to be located anywhere in relation to the port being used. + * Purely for reasons of backward compatibility the old method is still valid, but + * to make it clear that new projects should not use it, support for the port + * specific constants has been moved into the deprecated_definitions.h header + * file. */ +#include "deprecated_definitions.h" + +/* If portENTER_CRITICAL is not defined then including deprecated_definitions.h + * did not result in a portmacro.h header file being included - and it should be + * included here. In this case the path to the correct portmacro.h header file + * must be set in the compiler's include path. */ +#ifndef portENTER_CRITICAL + #include "portmacro.h" +#endif + +#if portBYTE_ALIGNMENT == 32 + #define portBYTE_ALIGNMENT_MASK ( 0x001f ) +#elif portBYTE_ALIGNMENT == 16 + #define portBYTE_ALIGNMENT_MASK ( 0x000f ) +#elif portBYTE_ALIGNMENT == 8 + #define portBYTE_ALIGNMENT_MASK ( 0x0007 ) +#elif portBYTE_ALIGNMENT == 4 + #define portBYTE_ALIGNMENT_MASK ( 0x0003 ) +#elif portBYTE_ALIGNMENT == 2 + #define portBYTE_ALIGNMENT_MASK ( 0x0001 ) +#elif portBYTE_ALIGNMENT == 1 + #define portBYTE_ALIGNMENT_MASK ( 0x0000 ) +#else /* if portBYTE_ALIGNMENT == 32 */ + #error "Invalid portBYTE_ALIGNMENT definition" +#endif /* if portBYTE_ALIGNMENT == 32 */ + +#ifndef portUSING_MPU_WRAPPERS + #define portUSING_MPU_WRAPPERS 0 +#endif + +#ifndef portNUM_CONFIGURABLE_REGIONS + #define portNUM_CONFIGURABLE_REGIONS 1 +#endif + +#ifndef portHAS_STACK_OVERFLOW_CHECKING + #define portHAS_STACK_OVERFLOW_CHECKING 0 +#endif + +#ifndef portARCH_NAME + #define portARCH_NAME NULL +#endif + +#ifndef portBASE_TYPE_ENTER_CRITICAL + #define portBASE_TYPE_ENTER_CRITICAL() taskENTER_CRITICAL() +#endif + +#ifndef portBASE_TYPE_EXIT_CRITICAL + #define portBASE_TYPE_EXIT_CRITICAL() taskEXIT_CRITICAL() +#endif + +#ifndef configSTACK_DEPTH_TYPE + #define configSTACK_DEPTH_TYPE StackType_t +#endif + +#ifndef configSTACK_ALLOCATION_FROM_SEPARATE_HEAP + /* Defaults to 0 for backward compatibility. */ + #define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 +#endif + +#include "mpu_wrappers.h" + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/* + * Setup the stack of a new task so it is ready to be placed under the + * scheduler control. The registers have to be placed on the stack in + * the order that the port expects to find them. + * + */ +#if ( portUSING_MPU_WRAPPERS == 1 ) + #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 ) + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged, + xMPU_SETTINGS * xMPUSettings ) PRIVILEGED_FUNCTION; + #else + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged, + xMPU_SETTINGS * xMPUSettings ) PRIVILEGED_FUNCTION; + #endif /* if ( portHAS_STACK_OVERFLOW_CHECKING == 1 ) */ +#else /* if ( portUSING_MPU_WRAPPERS == 1 ) */ + #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 ) + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) PRIVILEGED_FUNCTION; + #else + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) PRIVILEGED_FUNCTION; + #endif +#endif /* if ( portUSING_MPU_WRAPPERS == 1 ) */ + +/* Used by heap_5.c to define the start address and size of each memory region + * that together comprise the total FreeRTOS heap space. */ +typedef struct HeapRegion +{ + uint8_t * pucStartAddress; + size_t xSizeInBytes; +} HeapRegion_t; + +/* Used to pass information about the heap out of vPortGetHeapStats(). */ +typedef struct xHeapStats +{ + size_t xAvailableHeapSpaceInBytes; /* The total heap size currently available - this is the sum of all the free blocks, not the largest block that can be allocated. */ + size_t xSizeOfLargestFreeBlockInBytes; /* The maximum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */ + size_t xSizeOfSmallestFreeBlockInBytes; /* The minimum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */ + size_t xNumberOfFreeBlocks; /* The number of free memory blocks within the heap at the time vPortGetHeapStats() is called. */ + size_t xMinimumEverFreeBytesRemaining; /* The minimum amount of total free memory (sum of all free blocks) there has been in the heap since the system booted. */ + size_t xNumberOfSuccessfulAllocations; /* The number of calls to pvPortMalloc() that have returned a valid memory block. */ + size_t xNumberOfSuccessfulFrees; /* The number of calls to vPortFree() that has successfully freed a block of memory. */ +} HeapStats_t; + +/* + * Used to define multiple heap regions for use by heap_5.c. This function + * must be called before any calls to pvPortMalloc() - not creating a task, + * queue, semaphore, mutex, software timer, event group, etc. will result in + * pvPortMalloc being called. + * + * pxHeapRegions passes in an array of HeapRegion_t structures - each of which + * defines a region of memory that can be used as the heap. The array is + * terminated by a HeapRegions_t structure that has a size of 0. The region + * with the lowest start address must appear first in the array. + */ +void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) PRIVILEGED_FUNCTION; + +/* + * Returns a HeapStats_t structure filled with information about the current + * heap state. + */ +void vPortGetHeapStats( HeapStats_t * pxHeapStats ); + +/* + * Map to the memory management routines required for the port. + */ +void * pvPortMalloc( size_t xWantedSize ) PRIVILEGED_FUNCTION; +void * pvPortCalloc( size_t xNum, + size_t xSize ) PRIVILEGED_FUNCTION; +void vPortFree( void * pv ) PRIVILEGED_FUNCTION; +void vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION; +size_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION; +size_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION; +void xPortResetHeapMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION; + +#if ( configSTACK_ALLOCATION_FROM_SEPARATE_HEAP == 1 ) + void * pvPortMallocStack( size_t xSize ) PRIVILEGED_FUNCTION; + void vPortFreeStack( void * pv ) PRIVILEGED_FUNCTION; +#else + #define pvPortMallocStack pvPortMalloc + #define vPortFreeStack vPortFree +#endif + +/* + * This function resets the internal state of the heap module. It must be called + * by the application before restarting the scheduler. + */ +void vPortHeapResetState( void ) PRIVILEGED_FUNCTION; + +#if ( configUSE_MALLOC_FAILED_HOOK == 1 ) + +/** + * task.h + * @code{c} + * void vApplicationMallocFailedHook( void ) + * @endcode + * + * This hook function is called when allocation failed. + */ + void vApplicationMallocFailedHook( void ); +#endif + +/* + * Setup the hardware ready for the scheduler to take control. This generally + * sets up a tick interrupt and sets timers for the correct tick frequency. + */ +BaseType_t xPortStartScheduler( void ) PRIVILEGED_FUNCTION; + +/* + * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so + * the hardware is left in its original condition after the scheduler stops + * executing. + */ +void vPortEndScheduler( void ) PRIVILEGED_FUNCTION; + +/* + * The structures and methods of manipulating the MPU are contained within the + * port layer. + * + * Fills the xMPUSettings structure with the memory region information + * contained in xRegions. + */ +#if ( portUSING_MPU_WRAPPERS == 1 ) + struct xMEMORY_REGION; + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + configSTACK_DEPTH_TYPE uxStackDepth ) PRIVILEGED_FUNCTION; +#endif + +/** + * @brief Checks if the calling task is authorized to access the given buffer. + * + * @param pvBuffer The buffer which the calling task wants to access. + * @param ulBufferLength The length of the pvBuffer. + * @param ulAccessRequested The permissions that the calling task wants. + * + * @return pdTRUE if the calling task is authorized to access the buffer, + * pdFALSE otherwise. + */ +#if ( portUSING_MPU_WRAPPERS == 1 ) + BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, + uint32_t ulBufferLength, + uint32_t ulAccessRequested ) PRIVILEGED_FUNCTION; +#endif + +/** + * @brief Checks if the calling task is authorized to access the given kernel object. + * + * @param lInternalIndexOfKernelObject The index of the kernel object in the kernel + * object handle pool. + * + * @return pdTRUE if the calling task is authorized to access the kernel object, + * pdFALSE otherwise. + */ +#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) PRIVILEGED_FUNCTION; + +#endif + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTABLE_H */ diff --git a/include/projdefs.h b/include/projdefs.h new file mode 100644 index 000000000..04ec47fae --- /dev/null +++ b/include/projdefs.h @@ -0,0 +1,138 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PROJDEFS_H +#define PROJDEFS_H + +/* + * Defines the prototype to which task functions must conform. Defined in this + * file to ensure the type is known before portable.h is included. + */ +typedef void (* TaskFunction_t)( void * arg ); + +/* Converts a time in milliseconds to a time in ticks. This macro can be + * overridden by a macro of the same name defined in FreeRTOSConfig.h in case the + * definition here is not suitable for your application. */ +#ifndef pdMS_TO_TICKS + #define pdMS_TO_TICKS( xTimeInMs ) ( ( TickType_t ) ( ( ( uint64_t ) ( xTimeInMs ) * ( uint64_t ) configTICK_RATE_HZ ) / ( uint64_t ) 1000U ) ) +#endif + +/* Converts a time in ticks to a time in milliseconds. This macro can be + * overridden by a macro of the same name defined in FreeRTOSConfig.h in case the + * definition here is not suitable for your application. */ +#ifndef pdTICKS_TO_MS + #define pdTICKS_TO_MS( xTimeInTicks ) ( ( TickType_t ) ( ( ( uint64_t ) ( xTimeInTicks ) * ( uint64_t ) 1000U ) / ( uint64_t ) configTICK_RATE_HZ ) ) +#endif + +#define pdFALSE ( ( BaseType_t ) 0 ) +#define pdTRUE ( ( BaseType_t ) 1 ) +#define pdFALSE_SIGNED ( ( BaseType_t ) 0 ) +#define pdTRUE_SIGNED ( ( BaseType_t ) 1 ) +#define pdFALSE_UNSIGNED ( ( UBaseType_t ) 0 ) +#define pdTRUE_UNSIGNED ( ( UBaseType_t ) 1 ) + +#define pdPASS ( pdTRUE ) +#define pdFAIL ( pdFALSE ) +#define errQUEUE_EMPTY ( ( BaseType_t ) 0 ) +#define errQUEUE_FULL ( ( BaseType_t ) 0 ) + +/* FreeRTOS error definitions. */ +#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ( -1 ) +#define errQUEUE_BLOCKED ( -4 ) +#define errQUEUE_YIELD ( -5 ) + +/* Macros used for basic data corruption checks. */ +#ifndef configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES + #define configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES 0 +#endif + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + #define pdINTEGRITY_CHECK_VALUE 0x5a5a +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + #define pdINTEGRITY_CHECK_VALUE 0x5a5a5a5aUL +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_64_BITS ) + #define pdINTEGRITY_CHECK_VALUE 0x5a5a5a5a5a5a5a5aULL +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif + +/* The following errno values are used by FreeRTOS+ components, not FreeRTOS + * itself. */ +#define pdFREERTOS_ERRNO_NONE 0 /* No errors */ +#define pdFREERTOS_ERRNO_ENOENT 2 /* No such file or directory */ +#define pdFREERTOS_ERRNO_EINTR 4 /* Interrupted system call */ +#define pdFREERTOS_ERRNO_EIO 5 /* I/O error */ +#define pdFREERTOS_ERRNO_ENXIO 6 /* No such device or address */ +#define pdFREERTOS_ERRNO_EBADF 9 /* Bad file number */ +#define pdFREERTOS_ERRNO_EAGAIN 11 /* No more processes */ +#define pdFREERTOS_ERRNO_EWOULDBLOCK 11 /* Operation would block */ +#define pdFREERTOS_ERRNO_ENOMEM 12 /* Not enough memory */ +#define pdFREERTOS_ERRNO_EACCES 13 /* Permission denied */ +#define pdFREERTOS_ERRNO_EFAULT 14 /* Bad address */ +#define pdFREERTOS_ERRNO_EBUSY 16 /* Mount device busy */ +#define pdFREERTOS_ERRNO_EEXIST 17 /* File exists */ +#define pdFREERTOS_ERRNO_EXDEV 18 /* Cross-device link */ +#define pdFREERTOS_ERRNO_ENODEV 19 /* No such device */ +#define pdFREERTOS_ERRNO_ENOTDIR 20 /* Not a directory */ +#define pdFREERTOS_ERRNO_EISDIR 21 /* Is a directory */ +#define pdFREERTOS_ERRNO_EINVAL 22 /* Invalid argument */ +#define pdFREERTOS_ERRNO_ENOSPC 28 /* No space left on device */ +#define pdFREERTOS_ERRNO_ESPIPE 29 /* Illegal seek */ +#define pdFREERTOS_ERRNO_EROFS 30 /* Read only file system */ +#define pdFREERTOS_ERRNO_EUNATCH 42 /* Protocol driver not attached */ +#define pdFREERTOS_ERRNO_EBADE 50 /* Invalid exchange */ +#define pdFREERTOS_ERRNO_EFTYPE 79 /* Inappropriate file type or format */ +#define pdFREERTOS_ERRNO_ENMFILE 89 /* No more files */ +#define pdFREERTOS_ERRNO_ENOTEMPTY 90 /* Directory not empty */ +#define pdFREERTOS_ERRNO_ENAMETOOLONG 91 /* File or path name too long */ +#define pdFREERTOS_ERRNO_EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ +#define pdFREERTOS_ERRNO_EAFNOSUPPORT 97 /* Address family not supported by protocol */ +#define pdFREERTOS_ERRNO_ENOBUFS 105 /* No buffer space available */ +#define pdFREERTOS_ERRNO_ENOPROTOOPT 109 /* Protocol not available */ +#define pdFREERTOS_ERRNO_EADDRINUSE 112 /* Address already in use */ +#define pdFREERTOS_ERRNO_ETIMEDOUT 116 /* Connection timed out */ +#define pdFREERTOS_ERRNO_EINPROGRESS 119 /* Connection already in progress */ +#define pdFREERTOS_ERRNO_EALREADY 120 /* Socket already connected */ +#define pdFREERTOS_ERRNO_EADDRNOTAVAIL 125 /* Address not available */ +#define pdFREERTOS_ERRNO_EISCONN 127 /* Socket is already connected */ +#define pdFREERTOS_ERRNO_ENOTCONN 128 /* Socket is not connected */ +#define pdFREERTOS_ERRNO_ENOMEDIUM 135 /* No medium inserted */ +#define pdFREERTOS_ERRNO_EILSEQ 138 /* An invalid UTF-16 sequence was encountered. */ +#define pdFREERTOS_ERRNO_ECANCELED 140 /* Operation canceled. */ + +/* The following endian values are used by FreeRTOS+ components, not FreeRTOS + * itself. */ +#define pdFREERTOS_LITTLE_ENDIAN 0 +#define pdFREERTOS_BIG_ENDIAN 1 + +/* Re-defining endian values for generic naming. */ +#define pdLITTLE_ENDIAN pdFREERTOS_LITTLE_ENDIAN +#define pdBIG_ENDIAN pdFREERTOS_BIG_ENDIAN + + +#endif /* PROJDEFS_H */ diff --git a/include/queue.h b/include/queue.h new file mode 100644 index 000000000..e3dbbefd2 --- /dev/null +++ b/include/queue.h @@ -0,0 +1,1882 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef QUEUE_H +#define QUEUE_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h" must appear in source files before "include queue.h" +#endif + +#include "task.h" + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/** + * Type by which queues are referenced. For example, a call to xQueueCreate() + * returns an QueueHandle_t variable that can then be used as a parameter to + * xQueueSend(), xQueueReceive(), etc. + */ +struct QueueDefinition; /* Using old naming convention so as not to break kernel aware debuggers. */ +typedef struct QueueDefinition * QueueHandle_t; + +/** + * Type by which queue sets are referenced. For example, a call to + * xQueueCreateSet() returns an xQueueSet variable that can then be used as a + * parameter to xQueueSelectFromSet(), xQueueAddToSet(), etc. + */ +typedef struct QueueDefinition * QueueSetHandle_t; + +/** + * Queue sets can contain both queues and semaphores, so the + * QueueSetMemberHandle_t is defined as a type to be used where a parameter or + * return value can be either an QueueHandle_t or an SemaphoreHandle_t. + */ +typedef struct QueueDefinition * QueueSetMemberHandle_t; + +/* For internal use only. */ +#define queueSEND_TO_BACK ( ( BaseType_t ) 0 ) +#define queueSEND_TO_FRONT ( ( BaseType_t ) 1 ) +#define queueOVERWRITE ( ( BaseType_t ) 2 ) + +/* For internal use only. These definitions *must* match those in queue.c. */ +#define queueQUEUE_TYPE_BASE ( ( uint8_t ) 0U ) +#define queueQUEUE_TYPE_MUTEX ( ( uint8_t ) 1U ) +#define queueQUEUE_TYPE_COUNTING_SEMAPHORE ( ( uint8_t ) 2U ) +#define queueQUEUE_TYPE_BINARY_SEMAPHORE ( ( uint8_t ) 3U ) +#define queueQUEUE_TYPE_RECURSIVE_MUTEX ( ( uint8_t ) 4U ) +#define queueQUEUE_TYPE_SET ( ( uint8_t ) 5U ) + +/** + * queue. h + * @code{c} + * QueueHandle_t xQueueCreate( + * UBaseType_t uxQueueLength, + * UBaseType_t uxItemSize + * ); + * @endcode + * + * Creates a new queue instance, and returns a handle by which the new queue + * can be referenced. + * + * Internally, within the FreeRTOS implementation, queues use two blocks of + * memory. The first block is used to hold the queue's data structures. The + * second block is used to hold items placed into the queue. If a queue is + * created using xQueueCreate() then both blocks of memory are automatically + * dynamically allocated inside the xQueueCreate() function. (see + * https://www.FreeRTOS.org/a00111.html). If a queue is created using + * xQueueCreateStatic() then the application writer must provide the memory that + * will get used by the queue. xQueueCreateStatic() therefore allows a queue to + * be created without using any dynamic memory allocation. + * + * https://www.FreeRTOS.org/Embedded-RTOS-Queues.html + * + * @param uxQueueLength The maximum number of items that the queue can contain. + * + * @param uxItemSize The number of bytes each item in the queue will require. + * Items are queued by copy, not by reference, so this is the number of bytes + * that will be copied for each posted item. Each item on the queue must be + * the same size. + * + * @return If the queue is successfully create then a handle to the newly + * created queue is returned. If the queue cannot be created then NULL is + * returned. + * + * Example usage: + * @code{c} + * struct AMessage + * { + * char ucMessageID; + * char ucData[ 20 ]; + * }; + * + * void vATask( void *pvParameters ) + * { + * QueueHandle_t xQueue1, xQueue2; + * + * // Create a queue capable of containing 10 uint32_t values. + * xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) ); + * if( xQueue1 == NULL ) + * { + * // Queue was not created and must not be used. + * } + * + * // Create a queue capable of containing 10 pointers to AMessage structures. + * // These should be passed by pointer as they contain a lot of data. + * xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) ); + * if( xQueue2 == NULL ) + * { + * // Queue was not created and must not be used. + * } + * + * // ... Rest of task code. + * } + * @endcode + * \defgroup xQueueCreate xQueueCreate + * \ingroup QueueManagement + */ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + #define xQueueCreate( uxQueueLength, uxItemSize ) xQueueGenericCreate( ( uxQueueLength ), ( uxItemSize ), ( queueQUEUE_TYPE_BASE ) ) +#endif + +/** + * queue. h + * @code{c} + * QueueHandle_t xQueueCreateStatic( + * UBaseType_t uxQueueLength, + * UBaseType_t uxItemSize, + * uint8_t *pucQueueStorage, + * StaticQueue_t *pxQueueBuffer + * ); + * @endcode + * + * Creates a new queue instance, and returns a handle by which the new queue + * can be referenced. + * + * Internally, within the FreeRTOS implementation, queues use two blocks of + * memory. The first block is used to hold the queue's data structures. The + * second block is used to hold items placed into the queue. If a queue is + * created using xQueueCreate() then both blocks of memory are automatically + * dynamically allocated inside the xQueueCreate() function. (see + * https://www.FreeRTOS.org/a00111.html). If a queue is created using + * xQueueCreateStatic() then the application writer must provide the memory that + * will get used by the queue. xQueueCreateStatic() therefore allows a queue to + * be created without using any dynamic memory allocation. + * + * https://www.FreeRTOS.org/Embedded-RTOS-Queues.html + * + * @param uxQueueLength The maximum number of items that the queue can contain. + * + * @param uxItemSize The number of bytes each item in the queue will require. + * Items are queued by copy, not by reference, so this is the number of bytes + * that will be copied for each posted item. Each item on the queue must be + * the same size. + * + * @param pucQueueStorage If uxItemSize is not zero then + * pucQueueStorage must point to a uint8_t array that is at least large + * enough to hold the maximum number of items that can be in the queue at any + * one time - which is ( uxQueueLength * uxItemsSize ) bytes. If uxItemSize is + * zero then pucQueueStorage can be NULL. + * + * @param pxQueueBuffer Must point to a variable of type StaticQueue_t, which + * will be used to hold the queue's data structure. + * + * @return If the queue is created then a handle to the created queue is + * returned. If pxQueueBuffer is NULL then NULL is returned. + * + * Example usage: + * @code{c} + * struct AMessage + * { + * char ucMessageID; + * char ucData[ 20 ]; + * }; + * + * #define QUEUE_LENGTH 10 + * #define ITEM_SIZE sizeof( uint32_t ) + * + * // xQueueBuffer will hold the queue structure. + * StaticQueue_t xQueueBuffer; + * + * // ucQueueStorage will hold the items posted to the queue. Must be at least + * // [(queue length) * ( queue item size)] bytes long. + * uint8_t ucQueueStorage[ QUEUE_LENGTH * ITEM_SIZE ]; + * + * void vATask( void *pvParameters ) + * { + * QueueHandle_t xQueue1; + * + * // Create a queue capable of containing 10 uint32_t values. + * xQueue1 = xQueueCreateStatic( QUEUE_LENGTH, // The number of items the queue can hold. + * ITEM_SIZE, // The size of each item in the queue. + * &( ucQueueStorage[ 0 ] ), // The buffer that will hold the items in the queue. + * &xQueueBuffer ); // The buffer that will hold the queue structure. + * + * // The queue is guaranteed to be created successfully as no dynamic memory + * // allocation is used. Therefore xQueue1 is now a handle to a valid queue. + * + * // ... Rest of task code. + * } + * @endcode + * \defgroup xQueueCreateStatic xQueueCreateStatic + * \ingroup QueueManagement + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + #define xQueueCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxQueueBuffer ) xQueueGenericCreateStatic( ( uxQueueLength ), ( uxItemSize ), ( pucQueueStorage ), ( pxQueueBuffer ), ( queueQUEUE_TYPE_BASE ) ) +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +/** + * queue. h + * @code{c} + * BaseType_t xQueueGetStaticBuffers( QueueHandle_t xQueue, + * uint8_t ** ppucQueueStorage, + * StaticQueue_t ** ppxStaticQueue ); + * @endcode + * + * Retrieve pointers to a statically created queue's data structure buffer + * and storage area buffer. These are the same buffers that are supplied + * at the time of creation. + * + * @param xQueue The queue for which to retrieve the buffers. + * + * @param ppucQueueStorage Used to return a pointer to the queue's storage + * area buffer. + * + * @param ppxStaticQueue Used to return a pointer to the queue's data + * structure buffer. + * + * @return pdTRUE if buffers were retrieved, pdFALSE otherwise. + * + * \defgroup xQueueGetStaticBuffers xQueueGetStaticBuffers + * \ingroup QueueManagement + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + #define xQueueGetStaticBuffers( xQueue, ppucQueueStorage, ppxStaticQueue ) xQueueGenericGetStaticBuffers( ( xQueue ), ( ppucQueueStorage ), ( ppxStaticQueue ) ) +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +/** + * queue. h + * @code{c} + * BaseType_t xQueueSendToFront( + * QueueHandle_t xQueue, + * const void *pvItemToQueue, + * TickType_t xTicksToWait + * ); + * @endcode + * + * Post an item to the front of a queue. The item is queued by copy, not by + * reference. This function must not be called from an interrupt service + * routine. See xQueueSendFromISR () for an alternative which may be used + * in an ISR. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for space to become available on the queue, should it already + * be full. The call will return immediately if this is set to 0 and the + * queue is full. The time is defined in tick periods so the constant + * portTICK_PERIOD_MS should be used to convert to real time if this is required. + * + * @return pdPASS if the item was successfully posted, otherwise errQUEUE_FULL. + * + * Example usage: + * @code{c} + * struct AMessage + * { + * char ucMessageID; + * char ucData[ 20 ]; + * } xMessage; + * + * uint32_t ulVar = 10U; + * + * void vATask( void *pvParameters ) + * { + * QueueHandle_t xQueue1, xQueue2; + * struct AMessage *pxMessage; + * + * // Create a queue capable of containing 10 uint32_t values. + * xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) ); + * + * // Create a queue capable of containing 10 pointers to AMessage structures. + * // These should be passed by pointer as they contain a lot of data. + * xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) ); + * + * // ... + * + * if( xQueue1 != 0 ) + * { + * // Send an uint32_t. Wait for 10 ticks for space to become + * // available if necessary. + * if( xQueueSendToFront( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS ) + * { + * // Failed to post the message, even after 10 ticks. + * } + * } + * + * if( xQueue2 != 0 ) + * { + * // Send a pointer to a struct AMessage object. Don't block if the + * // queue is already full. + * pxMessage = & xMessage; + * xQueueSendToFront( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 ); + * } + * + * // ... Rest of task code. + * } + * @endcode + * \defgroup xQueueSend xQueueSend + * \ingroup QueueManagement + */ +#define xQueueSendToFront( xQueue, pvItemToQueue, xTicksToWait ) \ + xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_FRONT ) + +/** + * queue. h + * @code{c} + * BaseType_t xQueueSendToBack( + * QueueHandle_t xQueue, + * const void *pvItemToQueue, + * TickType_t xTicksToWait + * ); + * @endcode + * + * This is a macro that calls xQueueGenericSend(). + * + * Post an item to the back of a queue. The item is queued by copy, not by + * reference. This function must not be called from an interrupt service + * routine. See xQueueSendFromISR () for an alternative which may be used + * in an ISR. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for space to become available on the queue, should it already + * be full. The call will return immediately if this is set to 0 and the queue + * is full. The time is defined in tick periods so the constant + * portTICK_PERIOD_MS should be used to convert to real time if this is required. + * + * @return pdPASS if the item was successfully posted, otherwise errQUEUE_FULL. + * + * Example usage: + * @code{c} + * struct AMessage + * { + * char ucMessageID; + * char ucData[ 20 ]; + * } xMessage; + * + * uint32_t ulVar = 10U; + * + * void vATask( void *pvParameters ) + * { + * QueueHandle_t xQueue1, xQueue2; + * struct AMessage *pxMessage; + * + * // Create a queue capable of containing 10 uint32_t values. + * xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) ); + * + * // Create a queue capable of containing 10 pointers to AMessage structures. + * // These should be passed by pointer as they contain a lot of data. + * xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) ); + * + * // ... + * + * if( xQueue1 != 0 ) + * { + * // Send an uint32_t. Wait for 10 ticks for space to become + * // available if necessary. + * if( xQueueSendToBack( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS ) + * { + * // Failed to post the message, even after 10 ticks. + * } + * } + * + * if( xQueue2 != 0 ) + * { + * // Send a pointer to a struct AMessage object. Don't block if the + * // queue is already full. + * pxMessage = & xMessage; + * xQueueSendToBack( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 ); + * } + * + * // ... Rest of task code. + * } + * @endcode + * \defgroup xQueueSend xQueueSend + * \ingroup QueueManagement + */ +#define xQueueSendToBack( xQueue, pvItemToQueue, xTicksToWait ) \ + xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK ) + +/** + * queue. h + * @code{c} + * BaseType_t xQueueSend( + * QueueHandle_t xQueue, + * const void * pvItemToQueue, + * TickType_t xTicksToWait + * ); + * @endcode + * + * This is a macro that calls xQueueGenericSend(). It is included for + * backward compatibility with versions of FreeRTOS.org that did not + * include the xQueueSendToFront() and xQueueSendToBack() macros. It is + * equivalent to xQueueSendToBack(). + * + * Post an item on a queue. The item is queued by copy, not by reference. + * This function must not be called from an interrupt service routine. + * See xQueueSendFromISR () for an alternative which may be used in an ISR. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for space to become available on the queue, should it already + * be full. The call will return immediately if this is set to 0 and the + * queue is full. The time is defined in tick periods so the constant + * portTICK_PERIOD_MS should be used to convert to real time if this is required. + * + * @return pdPASS if the item was successfully posted, otherwise errQUEUE_FULL. + * + * Example usage: + * @code{c} + * struct AMessage + * { + * char ucMessageID; + * char ucData[ 20 ]; + * } xMessage; + * + * uint32_t ulVar = 10U; + * + * void vATask( void *pvParameters ) + * { + * QueueHandle_t xQueue1, xQueue2; + * struct AMessage *pxMessage; + * + * // Create a queue capable of containing 10 uint32_t values. + * xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) ); + * + * // Create a queue capable of containing 10 pointers to AMessage structures. + * // These should be passed by pointer as they contain a lot of data. + * xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) ); + * + * // ... + * + * if( xQueue1 != 0 ) + * { + * // Send an uint32_t. Wait for 10 ticks for space to become + * // available if necessary. + * if( xQueueSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS ) + * { + * // Failed to post the message, even after 10 ticks. + * } + * } + * + * if( xQueue2 != 0 ) + * { + * // Send a pointer to a struct AMessage object. Don't block if the + * // queue is already full. + * pxMessage = & xMessage; + * xQueueSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 ); + * } + * + * // ... Rest of task code. + * } + * @endcode + * \defgroup xQueueSend xQueueSend + * \ingroup QueueManagement + */ +#define xQueueSend( xQueue, pvItemToQueue, xTicksToWait ) \ + xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK ) + +/** + * queue. h + * @code{c} + * BaseType_t xQueueOverwrite( + * QueueHandle_t xQueue, + * const void * pvItemToQueue + * ); + * @endcode + * + * Only for use with queues that have a length of one - so the queue is either + * empty or full. + * + * Post an item on a queue. If the queue is already full then overwrite the + * value held in the queue. The item is queued by copy, not by reference. + * + * This function must not be called from an interrupt service routine. + * See xQueueOverwriteFromISR () for an alternative which may be used in an ISR. + * + * @param xQueue The handle of the queue to which the data is being sent. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @return xQueueOverwrite() is a macro that calls xQueueGenericSend(), and + * therefore has the same return values as xQueueSendToFront(). However, pdPASS + * is the only value that can be returned because xQueueOverwrite() will write + * to the queue even when the queue is already full. + * + * Example usage: + * @code{c} + * + * void vFunction( void *pvParameters ) + * { + * QueueHandle_t xQueue; + * uint32_t ulVarToSend, ulValReceived; + * + * // Create a queue to hold one uint32_t value. It is strongly + * // recommended *not* to use xQueueOverwrite() on queues that can + * // contain more than one value, and doing so will trigger an assertion + * // if configASSERT() is defined. + * xQueue = xQueueCreate( 1, sizeof( uint32_t ) ); + * + * // Write the value 10 to the queue using xQueueOverwrite(). + * ulVarToSend = 10; + * xQueueOverwrite( xQueue, &ulVarToSend ); + * + * // Peeking the queue should now return 10, but leave the value 10 in + * // the queue. A block time of zero is used as it is known that the + * // queue holds a value. + * ulValReceived = 0; + * xQueuePeek( xQueue, &ulValReceived, 0 ); + * + * if( ulValReceived != 10 ) + * { + * // Error unless the item was removed by a different task. + * } + * + * // The queue is still full. Use xQueueOverwrite() to overwrite the + * // value held in the queue with 100. + * ulVarToSend = 100; + * xQueueOverwrite( xQueue, &ulVarToSend ); + * + * // This time read from the queue, leaving the queue empty once more. + * // A block time of 0 is used again. + * xQueueReceive( xQueue, &ulValReceived, 0 ); + * + * // The value read should be the last value written, even though the + * // queue was already full when the value was written. + * if( ulValReceived != 100 ) + * { + * // Error! + * } + * + * // ... + * } + * @endcode + * \defgroup xQueueOverwrite xQueueOverwrite + * \ingroup QueueManagement + */ +#define xQueueOverwrite( xQueue, pvItemToQueue ) \ + xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), 0, queueOVERWRITE ) + + +/** + * queue. h + * @code{c} + * BaseType_t xQueueGenericSend( + * QueueHandle_t xQueue, + * const void * pvItemToQueue, + * TickType_t xTicksToWait + * BaseType_t xCopyPosition + * ); + * @endcode + * + * It is preferred that the macros xQueueSend(), xQueueSendToFront() and + * xQueueSendToBack() are used in place of calling this function directly. + * + * Post an item on a queue. The item is queued by copy, not by reference. + * This function must not be called from an interrupt service routine. + * See xQueueSendFromISR () for an alternative which may be used in an ISR. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for space to become available on the queue, should it already + * be full. The call will return immediately if this is set to 0 and the + * queue is full. The time is defined in tick periods so the constant + * portTICK_PERIOD_MS should be used to convert to real time if this is required. + * + * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the + * item at the back of the queue, or queueSEND_TO_FRONT to place the item + * at the front of the queue (for high priority messages). + * + * @return pdPASS if the item was successfully posted, otherwise errQUEUE_FULL. + * + * Example usage: + * @code{c} + * struct AMessage + * { + * char ucMessageID; + * char ucData[ 20 ]; + * } xMessage; + * + * uint32_t ulVar = 10U; + * + * void vATask( void *pvParameters ) + * { + * QueueHandle_t xQueue1, xQueue2; + * struct AMessage *pxMessage; + * + * // Create a queue capable of containing 10 uint32_t values. + * xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) ); + * + * // Create a queue capable of containing 10 pointers to AMessage structures. + * // These should be passed by pointer as they contain a lot of data. + * xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) ); + * + * // ... + * + * if( xQueue1 != 0 ) + * { + * // Send an uint32_t. Wait for 10 ticks for space to become + * // available if necessary. + * if( xQueueGenericSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10, queueSEND_TO_BACK ) != pdPASS ) + * { + * // Failed to post the message, even after 10 ticks. + * } + * } + * + * if( xQueue2 != 0 ) + * { + * // Send a pointer to a struct AMessage object. Don't block if the + * // queue is already full. + * pxMessage = & xMessage; + * xQueueGenericSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0, queueSEND_TO_BACK ); + * } + * + * // ... Rest of task code. + * } + * @endcode + * \defgroup xQueueSend xQueueSend + * \ingroup QueueManagement + */ +BaseType_t xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * @code{c} + * BaseType_t xQueuePeek( + * QueueHandle_t xQueue, + * void * const pvBuffer, + * TickType_t xTicksToWait + * ); + * @endcode + * + * Receive an item from a queue without removing the item from the queue. + * The item is received by copy so a buffer of adequate size must be + * provided. The number of bytes copied into the buffer was defined when + * the queue was created. + * + * Successfully received items remain on the queue so will be returned again + * by the next call, or a call to xQueueReceive(). + * + * This macro must not be used in an interrupt service routine. See + * xQueuePeekFromISR() for an alternative that can be called from an interrupt + * service routine. + * + * @param xQueue The handle to the queue from which the item is to be + * received. + * + * @param pvBuffer Pointer to the buffer into which the received item will + * be copied. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for an item to receive should the queue be empty at the time + * of the call. The time is defined in tick periods so the constant + * portTICK_PERIOD_MS should be used to convert to real time if this is required. + * xQueuePeek() will return immediately if xTicksToWait is 0 and the queue + * is empty. + * + * @return pdPASS if an item was successfully received from the queue, + * otherwise errQUEUE_EMPTY. + * + * Example usage: + * @code{c} + * struct AMessage + * { + * char ucMessageID; + * char ucData[ 20 ]; + * } xMessage; + * + * QueueHandle_t xQueue; + * + * // Task to create a queue and post a value. + * void vATask( void *pvParameters ) + * { + * struct AMessage *pxMessage; + * + * // Create a queue capable of containing 10 pointers to AMessage structures. + * // These should be passed by pointer as they contain a lot of data. + * xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) ); + * if( xQueue == 0 ) + * { + * // Failed to create the queue. + * } + * + * // ... + * + * // Send a pointer to a struct AMessage object. Don't block if the + * // queue is already full. + * pxMessage = & xMessage; + * xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 ); + * + * // ... Rest of task code. + * } + * + * // Task to peek the data from the queue. + * void vADifferentTask( void *pvParameters ) + * { + * struct AMessage *pxRxedMessage; + * + * if( xQueue != 0 ) + * { + * // Peek a message on the created queue. Block for 10 ticks if a + * // message is not immediately available. + * if( xQueuePeek( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) ) + * { + * // pcRxedMessage now points to the struct AMessage variable posted + * // by vATask, but the item still remains on the queue. + * } + * } + * + * // ... Rest of task code. + * } + * @endcode + * \defgroup xQueuePeek xQueuePeek + * \ingroup QueueManagement + */ +BaseType_t xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * @code{c} + * BaseType_t xQueuePeekFromISR( + * QueueHandle_t xQueue, + * void *pvBuffer, + * ); + * @endcode + * + * A version of xQueuePeek() that can be called from an interrupt service + * routine (ISR). + * + * Receive an item from a queue without removing the item from the queue. + * The item is received by copy so a buffer of adequate size must be + * provided. The number of bytes copied into the buffer was defined when + * the queue was created. + * + * Successfully received items remain on the queue so will be returned again + * by the next call, or a call to xQueueReceive(). + * + * @param xQueue The handle to the queue from which the item is to be + * received. + * + * @param pvBuffer Pointer to the buffer into which the received item will + * be copied. + * + * @return pdPASS if an item was successfully received from the queue, + * otherwise pdFAIL. + * + * \defgroup xQueuePeekFromISR xQueuePeekFromISR + * \ingroup QueueManagement + */ +BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, + void * const pvBuffer ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * @code{c} + * BaseType_t xQueueReceive( + * QueueHandle_t xQueue, + * void *pvBuffer, + * TickType_t xTicksToWait + * ); + * @endcode + * + * Receive an item from a queue. The item is received by copy so a buffer of + * adequate size must be provided. The number of bytes copied into the buffer + * was defined when the queue was created. + * + * Successfully received items are removed from the queue. + * + * This function must not be used in an interrupt service routine. See + * xQueueReceiveFromISR for an alternative that can. + * + * @param xQueue The handle to the queue from which the item is to be + * received. + * + * @param pvBuffer Pointer to the buffer into which the received item will + * be copied. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for an item to receive should the queue be empty at the time + * of the call. xQueueReceive() will return immediately if xTicksToWait + * is zero and the queue is empty. The time is defined in tick periods so the + * constant portTICK_PERIOD_MS should be used to convert to real time if this is + * required. + * + * @return pdPASS if an item was successfully received from the queue, + * otherwise errQUEUE_EMPTY. + * + * Example usage: + * @code{c} + * struct AMessage + * { + * char ucMessageID; + * char ucData[ 20 ]; + * } xMessage; + * + * QueueHandle_t xQueue; + * + * // Task to create a queue and post a value. + * void vATask( void *pvParameters ) + * { + * struct AMessage *pxMessage; + * + * // Create a queue capable of containing 10 pointers to AMessage structures. + * // These should be passed by pointer as they contain a lot of data. + * xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) ); + * if( xQueue == 0 ) + * { + * // Failed to create the queue. + * } + * + * // ... + * + * // Send a pointer to a struct AMessage object. Don't block if the + * // queue is already full. + * pxMessage = & xMessage; + * xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 ); + * + * // ... Rest of task code. + * } + * + * // Task to receive from the queue. + * void vADifferentTask( void *pvParameters ) + * { + * struct AMessage *pxRxedMessage; + * + * if( xQueue != 0 ) + * { + * // Receive a message on the created queue. Block for 10 ticks if a + * // message is not immediately available. + * if( xQueueReceive( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) ) + * { + * // pcRxedMessage now points to the struct AMessage variable posted + * // by vATask. + * } + * } + * + * // ... Rest of task code. + * } + * @endcode + * \defgroup xQueueReceive xQueueReceive + * \ingroup QueueManagement + */ +BaseType_t xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * @code{c} + * UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ); + * @endcode + * + * Return the number of messages stored in a queue. + * + * @param xQueue A handle to the queue being queried. + * + * @return The number of messages available in the queue. + * + * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting + * \ingroup QueueManagement + */ +UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * @code{c} + * UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ); + * @endcode + * + * Return the number of free spaces available in a queue. This is equal to the + * number of items that can be sent to the queue before the queue becomes full + * if no items are removed. + * + * @param xQueue A handle to the queue being queried. + * + * @return The number of spaces available in the queue. + * + * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting + * \ingroup QueueManagement + */ +UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * @code{c} + * void vQueueDelete( QueueHandle_t xQueue ); + * @endcode + * + * Delete a queue - freeing all the memory allocated for storing of items + * placed on the queue. + * + * @param xQueue A handle to the queue to be deleted. + * + * \defgroup vQueueDelete vQueueDelete + * \ingroup QueueManagement + */ +void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * @code{c} + * BaseType_t xQueueSendToFrontFromISR( + * QueueHandle_t xQueue, + * const void *pvItemToQueue, + * BaseType_t *pxHigherPriorityTaskWoken + * ); + * @endcode + * + * This is a macro that calls xQueueGenericSendFromISR(). + * + * Post an item to the front of a queue. It is safe to use this macro from + * within an interrupt service routine. + * + * Items are queued by copy not reference so it is preferable to only + * queue small items, especially when called from an ISR. In most cases + * it would be preferable to store a pointer to the item being queued. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param pxHigherPriorityTaskWoken xQueueSendToFrontFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xQueueSendToFrontFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @return pdPASS if the data was successfully sent to the queue, otherwise + * errQUEUE_FULL. + * + * Example usage for buffered IO (where the ISR can obtain more than one value + * per call): + * @code{c} + * void vBufferISR( void ) + * { + * char cIn; + * BaseType_t xHigherPriorityTaskWoken; + * + * // We have not woken a task at the start of the ISR. + * xHigherPriorityTaskWoken = pdFALSE; + * + * // Loop until the buffer is empty. + * do + * { + * // Obtain a byte from the buffer. + * cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS ); + * + * // Post the byte. + * xQueueSendToFrontFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken ); + * + * } while( portINPUT_BYTE( BUFFER_COUNT ) ); + * + * // Now the buffer is empty we can switch context if necessary. + * if( xHigherPriorityTaskWoken ) + * { + * // As xHigherPriorityTaskWoken is now set to pdTRUE then a context + * // switch should be requested. The macro used is port specific and + * // will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - + * // refer to the documentation page for the port being used. + * portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + * } + * } + * @endcode + * + * \defgroup xQueueSendFromISR xQueueSendFromISR + * \ingroup QueueManagement + */ +#define xQueueSendToFrontFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) \ + xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_FRONT ) + + +/** + * queue. h + * @code{c} + * BaseType_t xQueueSendToBackFromISR( + * QueueHandle_t xQueue, + * const void *pvItemToQueue, + * BaseType_t *pxHigherPriorityTaskWoken + * ); + * @endcode + * + * This is a macro that calls xQueueGenericSendFromISR(). + * + * Post an item to the back of a queue. It is safe to use this macro from + * within an interrupt service routine. + * + * Items are queued by copy not reference so it is preferable to only + * queue small items, especially when called from an ISR. In most cases + * it would be preferable to store a pointer to the item being queued. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param pxHigherPriorityTaskWoken xQueueSendToBackFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xQueueSendToBackFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @return pdPASS if the data was successfully sent to the queue, otherwise + * errQUEUE_FULL. + * + * Example usage for buffered IO (where the ISR can obtain more than one value + * per call): + * @code{c} + * void vBufferISR( void ) + * { + * char cIn; + * BaseType_t xHigherPriorityTaskWoken; + * + * // We have not woken a task at the start of the ISR. + * xHigherPriorityTaskWoken = pdFALSE; + * + * // Loop until the buffer is empty. + * do + * { + * // Obtain a byte from the buffer. + * cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS ); + * + * // Post the byte. + * xQueueSendToBackFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken ); + * + * } while( portINPUT_BYTE( BUFFER_COUNT ) ); + * + * // Now the buffer is empty we can switch context if necessary. + * if( xHigherPriorityTaskWoken ) + * { + * // As xHigherPriorityTaskWoken is now set to pdTRUE then a context + * // switch should be requested. The macro used is port specific and + * // will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - + * // refer to the documentation page for the port being used. + * portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + * } + * } + * @endcode + * + * \defgroup xQueueSendFromISR xQueueSendFromISR + * \ingroup QueueManagement + */ +#define xQueueSendToBackFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) \ + xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK ) + +/** + * queue. h + * @code{c} + * BaseType_t xQueueOverwriteFromISR( + * QueueHandle_t xQueue, + * const void * pvItemToQueue, + * BaseType_t *pxHigherPriorityTaskWoken + * ); + * @endcode + * + * A version of xQueueOverwrite() that can be used in an interrupt service + * routine (ISR). + * + * Only for use with queues that can hold a single item - so the queue is either + * empty or full. + * + * Post an item on a queue. If the queue is already full then overwrite the + * value held in the queue. The item is queued by copy, not by reference. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param pxHigherPriorityTaskWoken xQueueOverwriteFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xQueueOverwriteFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @return xQueueOverwriteFromISR() is a macro that calls + * xQueueGenericSendFromISR(), and therefore has the same return values as + * xQueueSendToFrontFromISR(). However, pdPASS is the only value that can be + * returned because xQueueOverwriteFromISR() will write to the queue even when + * the queue is already full. + * + * Example usage: + * @code{c} + * + * QueueHandle_t xQueue; + * + * void vFunction( void *pvParameters ) + * { + * // Create a queue to hold one uint32_t value. It is strongly + * // recommended *not* to use xQueueOverwriteFromISR() on queues that can + * // contain more than one value, and doing so will trigger an assertion + * // if configASSERT() is defined. + * xQueue = xQueueCreate( 1, sizeof( uint32_t ) ); + * } + * + * void vAnInterruptHandler( void ) + * { + * // xHigherPriorityTaskWoken must be set to pdFALSE before it is used. + * BaseType_t xHigherPriorityTaskWoken = pdFALSE; + * uint32_t ulVarToSend, ulValReceived; + * + * // Write the value 10 to the queue using xQueueOverwriteFromISR(). + * ulVarToSend = 10; + * xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken ); + * + * // The queue is full, but calling xQueueOverwriteFromISR() again will still + * // pass because the value held in the queue will be overwritten with the + * // new value. + * ulVarToSend = 100; + * xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken ); + * + * // Reading from the queue will now return 100. + * + * // ... + * + * if( xHigherPrioritytaskWoken == pdTRUE ) + * { + * // Writing to the queue caused a task to unblock and the unblocked task + * // has a priority higher than or equal to the priority of the currently + * // executing task (the task this interrupt interrupted). Perform a context + * // switch so this interrupt returns directly to the unblocked task. + * // The macro used is port specific and will be either + * // portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - refer to the documentation + * // page for the port being used. + * portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + * } + * } + * @endcode + * \defgroup xQueueOverwriteFromISR xQueueOverwriteFromISR + * \ingroup QueueManagement + */ +#define xQueueOverwriteFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) \ + xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueOVERWRITE ) + +/** + * queue. h + * @code{c} + * BaseType_t xQueueSendFromISR( + * QueueHandle_t xQueue, + * const void *pvItemToQueue, + * BaseType_t *pxHigherPriorityTaskWoken + * ); + * @endcode + * + * This is a macro that calls xQueueGenericSendFromISR(). It is included + * for backward compatibility with versions of FreeRTOS.org that did not + * include the xQueueSendToBackFromISR() and xQueueSendToFrontFromISR() + * macros. + * + * Post an item to the back of a queue. It is safe to use this function from + * within an interrupt service routine. + * + * Items are queued by copy not reference so it is preferable to only + * queue small items, especially when called from an ISR. In most cases + * it would be preferable to store a pointer to the item being queued. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param pxHigherPriorityTaskWoken xQueueSendFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xQueueSendFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @return pdPASS if the data was successfully sent to the queue, otherwise + * errQUEUE_FULL. + * + * Example usage for buffered IO (where the ISR can obtain more than one value + * per call): + * @code{c} + * void vBufferISR( void ) + * { + * char cIn; + * BaseType_t xHigherPriorityTaskWoken; + * + * // We have not woken a task at the start of the ISR. + * xHigherPriorityTaskWoken = pdFALSE; + * + * // Loop until the buffer is empty. + * do + * { + * // Obtain a byte from the buffer. + * cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS ); + * + * // Post the byte. + * xQueueSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken ); + * + * } while( portINPUT_BYTE( BUFFER_COUNT ) ); + * + * // Now the buffer is empty we can switch context if necessary. + * if( xHigherPriorityTaskWoken ) + * { + * // As xHigherPriorityTaskWoken is now set to pdTRUE then a context + * // switch should be requested. The macro used is port specific and + * // will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - + * // refer to the documentation page for the port being used. + * portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + * } + * } + * @endcode + * + * \defgroup xQueueSendFromISR xQueueSendFromISR + * \ingroup QueueManagement + */ +#define xQueueSendFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) \ + xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK ) + +/** + * queue. h + * @code{c} + * BaseType_t xQueueGenericSendFromISR( + * QueueHandle_t xQueue, + * const void *pvItemToQueue, + * BaseType_t *pxHigherPriorityTaskWoken, + * BaseType_t xCopyPosition + * ); + * @endcode + * + * It is preferred that the macros xQueueSendFromISR(), + * xQueueSendToFrontFromISR() and xQueueSendToBackFromISR() be used in place + * of calling this function directly. xQueueGiveFromISR() is an + * equivalent for use by semaphores that don't actually copy any data. + * + * Post an item on a queue. It is safe to use this function from within an + * interrupt service routine. + * + * Items are queued by copy not reference so it is preferable to only + * queue small items, especially when called from an ISR. In most cases + * it would be preferable to store a pointer to the item being queued. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param pxHigherPriorityTaskWoken xQueueGenericSendFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xQueueGenericSendFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the + * item at the back of the queue, or queueSEND_TO_FRONT to place the item + * at the front of the queue (for high priority messages). + * + * @return pdPASS if the data was successfully sent to the queue, otherwise + * errQUEUE_FULL. + * + * Example usage for buffered IO (where the ISR can obtain more than one value + * per call): + * @code{c} + * void vBufferISR( void ) + * { + * char cIn; + * BaseType_t xHigherPriorityTaskWokenByPost; + * + * // We have not woken a task at the start of the ISR. + * xHigherPriorityTaskWokenByPost = pdFALSE; + * + * // Loop until the buffer is empty. + * do + * { + * // Obtain a byte from the buffer. + * cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS ); + * + * // Post each byte. + * xQueueGenericSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWokenByPost, queueSEND_TO_BACK ); + * + * } while( portINPUT_BYTE( BUFFER_COUNT ) ); + * + * // Now the buffer is empty we can switch context if necessary. + * if( xHigherPriorityTaskWokenByPost ) + * { + * // As xHigherPriorityTaskWokenByPost is now set to pdTRUE then a context + * // switch should be requested. The macro used is port specific and + * // will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - + * // refer to the documentation page for the port being used. + * portYIELD_FROM_ISR( xHigherPriorityTaskWokenByPost ); + * } + * } + * @endcode + * + * \defgroup xQueueSendFromISR xQueueSendFromISR + * \ingroup QueueManagement + */ +BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, + const void * const pvItemToQueue, + BaseType_t * const pxHigherPriorityTaskWoken, + const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION; +BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, + BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * @code{c} + * BaseType_t xQueueReceiveFromISR( + * QueueHandle_t xQueue, + * void *pvBuffer, + * BaseType_t *pxTaskWoken + * ); + * @endcode + * + * Receive an item from a queue. It is safe to use this function from within an + * interrupt service routine. + * + * @param xQueue The handle to the queue from which the item is to be + * received. + * + * @param pvBuffer Pointer to the buffer into which the received item will + * be copied. + * + * @param pxHigherPriorityTaskWoken A task may be blocked waiting for space to + * become available on the queue. If xQueueReceiveFromISR causes such a task + * to unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will + * remain unchanged. + * + * @return pdPASS if an item was successfully received from the queue, + * otherwise pdFAIL. + * + * Example usage: + * @code{c} + * + * QueueHandle_t xQueue; + * + * // Function to create a queue and post some values. + * void vAFunction( void *pvParameters ) + * { + * char cValueToPost; + * const TickType_t xTicksToWait = ( TickType_t )0xff; + * + * // Create a queue capable of containing 10 characters. + * xQueue = xQueueCreate( 10, sizeof( char ) ); + * if( xQueue == 0 ) + * { + * // Failed to create the queue. + * } + * + * // ... + * + * // Post some characters that will be used within an ISR. If the queue + * // is full then this task will block for xTicksToWait ticks. + * cValueToPost = 'a'; + * xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait ); + * cValueToPost = 'b'; + * xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait ); + * + * // ... keep posting characters ... this task may block when the queue + * // becomes full. + * + * cValueToPost = 'c'; + * xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait ); + * } + * + * // ISR that outputs all the characters received on the queue. + * void vISR_Routine( void ) + * { + * BaseType_t xHigherPriorityTaskWoken = pdFALSE; + * char cRxedChar; + * + * while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xHigherPriorityTaskWoken) ) + * { + * // A character was received. Output the character now. + * vOutputCharacter( cRxedChar ); + * + * // If removing the character from the queue woke the task that was + * // posting onto the queue xHigherPriorityTaskWoken will have been set to + * // pdTRUE. No matter how many times this loop iterates only one + * // task will be woken. + * } + * + * if( xHigherPrioritytaskWoken == pdTRUE ); + * { + * // As xHigherPriorityTaskWoken is now set to pdTRUE then a context + * // switch should be requested. The macro used is port specific and + * // will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - + * // refer to the documentation page for the port being used. + * portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + * } + * } + * @endcode + * \defgroup xQueueReceiveFromISR xQueueReceiveFromISR + * \ingroup QueueManagement + */ +BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, + void * const pvBuffer, + BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; + +/* + * Utilities to query queues that are safe to use from an ISR. These utilities + * should be used only from within an ISR, or within a critical section. + */ +BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; +BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; +UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; + +#if ( configUSE_CO_ROUTINES == 1 ) + +/* + * The functions defined above are for passing data to and from tasks. The + * functions below are the equivalents for passing data to and from + * co-routines. + * + * These functions are called from the co-routine macro implementation and + * should not be called directly from application code. Instead use the macro + * wrappers defined within croutine.h. + */ + BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, + const void * pvItemToQueue, + BaseType_t xCoRoutinePreviouslyWoken ); + BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, + void * pvBuffer, + BaseType_t * pxTaskWoken ); + BaseType_t xQueueCRSend( QueueHandle_t xQueue, + const void * pvItemToQueue, + TickType_t xTicksToWait ); + BaseType_t xQueueCRReceive( QueueHandle_t xQueue, + void * pvBuffer, + TickType_t xTicksToWait ); + +#endif /* if ( configUSE_CO_ROUTINES == 1 ) */ + +/* + * For internal use only. Use xSemaphoreCreateMutex(), + * xSemaphoreCreateCounting() or xSemaphoreGetMutexHolder() instead of calling + * these functions directly. + */ +QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) PRIVILEGED_FUNCTION; + +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, + StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION; +#endif + +#if ( configUSE_COUNTING_SEMAPHORES == 1 ) + QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, + const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION; +#endif + +#if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, + const UBaseType_t uxInitialCount, + StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION; +#endif + +BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) + TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION; + TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION; +#endif + +/* + * For internal use only. Use xSemaphoreTakeRecursive() or + * xSemaphoreGiveRecursive() instead of calling these functions directly. + */ +BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; +BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) PRIVILEGED_FUNCTION; + +/* + * Reset a queue back to its original empty state. The return value is now + * obsolete and is always set to pdPASS. + */ +#define xQueueReset( xQueue ) xQueueGenericReset( ( xQueue ), pdFALSE ) + +/* + * The registry is provided as a means for kernel aware debuggers to + * locate queues, semaphores and mutexes. Call vQueueAddToRegistry() add + * a queue, semaphore or mutex handle to the registry if you want the handle + * to be available to a kernel aware debugger. If you are not using a kernel + * aware debugger then this function can be ignored. + * + * configQUEUE_REGISTRY_SIZE defines the maximum number of handles the + * registry can hold. configQUEUE_REGISTRY_SIZE must be greater than 0 + * within FreeRTOSConfig.h for the registry to be available. Its value + * does not affect the number of queues, semaphores and mutexes that can be + * created - just the number that the registry can hold. + * + * If vQueueAddToRegistry is called more than once with the same xQueue + * parameter, the registry will store the pcQueueName parameter from the + * most recent call to vQueueAddToRegistry. + * + * @param xQueue The handle of the queue being added to the registry. This + * is the handle returned by a call to xQueueCreate(). Semaphore and mutex + * handles can also be passed in here. + * + * @param pcQueueName The name to be associated with the handle. This is the + * name that the kernel aware debugger will display. The queue registry only + * stores a pointer to the string - so the string must be persistent (global or + * preferably in ROM/Flash), not on the stack. + */ +#if ( configQUEUE_REGISTRY_SIZE > 0 ) + void vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcQueueName ) PRIVILEGED_FUNCTION; +#endif + +/* + * The registry is provided as a means for kernel aware debuggers to + * locate queues, semaphores and mutexes. Call vQueueAddToRegistry() add + * a queue, semaphore or mutex handle to the registry if you want the handle + * to be available to a kernel aware debugger, and vQueueUnregisterQueue() to + * remove the queue, semaphore or mutex from the register. If you are not using + * a kernel aware debugger then this function can be ignored. + * + * @param xQueue The handle of the queue being removed from the registry. + */ +#if ( configQUEUE_REGISTRY_SIZE > 0 ) + void vQueueUnregisterQueue( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; +#endif + +/* + * The queue registry is provided as a means for kernel aware debuggers to + * locate queues, semaphores and mutexes. Call pcQueueGetName() to look + * up and return the name of a queue in the queue registry from the queue's + * handle. + * + * @param xQueue The handle of the queue the name of which will be returned. + * @return If the queue is in the registry then a pointer to the name of the + * queue is returned. If the queue is not in the registry then NULL is + * returned. + */ +#if ( configQUEUE_REGISTRY_SIZE > 0 ) + const char * pcQueueGetName( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; +#endif + +/* + * Generic version of the function used to create a queue using dynamic memory + * allocation. This is called by other functions and macros that create other + * RTOS objects that use the queue structure as their base. + */ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, + const UBaseType_t uxItemSize, + const uint8_t ucQueueType ) PRIVILEGED_FUNCTION; +#endif + +/* + * Generic version of the function used to create a queue using dynamic memory + * allocation. This is called by other functions and macros that create other + * RTOS objects that use the queue structure as their base. + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, + const UBaseType_t uxItemSize, + uint8_t * pucQueueStorage, + StaticQueue_t * pxStaticQueue, + const uint8_t ucQueueType ) PRIVILEGED_FUNCTION; +#endif + +/* + * Generic version of the function used to retrieve the buffers of statically + * created queues. This is called by other functions and macros that retrieve + * the buffers of other statically created RTOS objects that use the queue + * structure as their base. + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + BaseType_t xQueueGenericGetStaticBuffers( QueueHandle_t xQueue, + uint8_t ** ppucQueueStorage, + StaticQueue_t ** ppxStaticQueue ) PRIVILEGED_FUNCTION; +#endif + +/* + * Queue sets provide a mechanism to allow a task to block (pend) on a read + * operation from multiple queues or semaphores simultaneously. + * + * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this + * function. + * + * A queue set must be explicitly created using a call to xQueueCreateSet() or + * xQueueCreateSetStatic() before it can be used. Once created, standard + * FreeRTOS queues and semaphores can be added to the set using calls to + * xQueueAddToSet(). xQueueSelectFromSet() is then used to determine which, if + * any, of the queues or semaphores contained in the set is in a state where a + * queue read or semaphore take operation would be successful. + * + * Note 1: See the documentation on https://www.freertos.org/Documentation/02-Kernel/04-API-references/07-Queue-sets/00-RTOS-queue-sets + * for reasons why queue sets are very rarely needed in practice as there are + * simpler methods of blocking on multiple objects. + * + * Note 2: Blocking on a queue set that contains a mutex will not cause the + * mutex holder to inherit the priority of the blocked task. + * + * Note 3: An additional 4 bytes of RAM is required for each space in a every + * queue added to a queue set. Therefore counting semaphores that have a high + * maximum count value should not be added to a queue set. + * + * Note 4: A receive (in the case of a queue) or take (in the case of a + * semaphore) operation must not be performed on a member of a queue set unless + * a call to xQueueSelectFromSet() has first returned a handle to that set member. + * + * @param uxEventQueueLength Queue sets store events that occur on + * the queues and semaphores contained in the set. uxEventQueueLength specifies + * the maximum number of events that can be queued at once. To be absolutely + * certain that events are not lost uxEventQueueLength should be set to the + * total sum of the length of the queues added to the set, where binary + * semaphores and mutexes have a length of 1, and counting semaphores have a + * length set by their maximum count value. Examples: + * + If a queue set is to hold a queue of length 5, another queue of length 12, + * and a binary semaphore, then uxEventQueueLength should be set to + * (5 + 12 + 1), or 18. + * + If a queue set is to hold three binary semaphores then uxEventQueueLength + * should be set to (1 + 1 + 1 ), or 3. + * + If a queue set is to hold a counting semaphore that has a maximum count of + * 5, and a counting semaphore that has a maximum count of 3, then + * uxEventQueueLength should be set to (5 + 3), or 8. + * + * @return If the queue set is created successfully then a handle to the created + * queue set is returned. Otherwise NULL is returned. + */ +#if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION; +#endif + +/* + * Queue sets provide a mechanism to allow a task to block (pend) on a read + * operation from multiple queues or semaphores simultaneously. + * + * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this + * function. + * + * A queue set must be explicitly created using a call to xQueueCreateSet() + * or xQueueCreateSetStatic() before it can be used. Once created, standard + * FreeRTOS queues and semaphores can be added to the set using calls to + * xQueueAddToSet(). xQueueSelectFromSet() is then used to determine which, if + * any, of the queues or semaphores contained in the set is in a state where a + * queue read or semaphore take operation would be successful. + * + * Note 1: See the documentation on https://www.freertos.org/Documentation/02-Kernel/04-API-references/07-Queue-sets/00-RTOS-queue-sets + * for reasons why queue sets are very rarely needed in practice as there are + * simpler methods of blocking on multiple objects. + * + * Note 2: Blocking on a queue set that contains a mutex will not cause the + * mutex holder to inherit the priority of the blocked task. + * + * Note 3: An additional 4 bytes of RAM is required for each space in a every + * queue added to a queue set. Therefore counting semaphores that have a high + * maximum count value should not be added to a queue set. + * + * Note 4: A receive (in the case of a queue) or take (in the case of a + * semaphore) operation must not be performed on a member of a queue set unless + * a call to xQueueSelectFromSet() has first returned a handle to that set member. + * + * @param uxEventQueueLength Queue sets store events that occur on + * the queues and semaphores contained in the set. uxEventQueueLength specifies + * the maximum number of events that can be queued at once. To be absolutely + * certain that events are not lost uxEventQueueLength should be set to the + * total sum of the length of the queues added to the set, where binary + * semaphores and mutexes have a length of 1, and counting semaphores have a + * length set by their maximum count value. Examples: + * + If a queue set is to hold a queue of length 5, another queue of length 12, + * and a binary semaphore, then uxEventQueueLength should be set to + * (5 + 12 + 1), or 18. + * + If a queue set is to hold three binary semaphores then uxEventQueueLength + * should be set to (1 + 1 + 1 ), or 3. + * + If a queue set is to hold a counting semaphore that has a maximum count of + * 5, and a counting semaphore that has a maximum count of 3, then + * uxEventQueueLength should be set to (5 + 3), or 8. + * + * @param pucQueueStorage pucQueueStorage must point to a uint8_t array that is + * at least large enough to hold uxEventQueueLength events. + * + * @param pxQueueBuffer Must point to a variable of type StaticQueue_t, which + * will be used to hold the queue's data structure. + * + * @return If the queue set is created successfully then a handle to the created + * queue set is returned. If pxQueueBuffer is NULL then NULL is returned. + */ +#if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + QueueSetHandle_t xQueueCreateSetStatic( const UBaseType_t uxEventQueueLength, + uint8_t * pucQueueStorage, + StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION; +#endif + +/* + * Adds a queue or semaphore to a queue set that was previously created by a + * call to xQueueCreateSet() or xQueueCreateSetStatic(). + * + * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this + * function. + * + * Note 1: A receive (in the case of a queue) or take (in the case of a + * semaphore) operation must not be performed on a member of a queue set unless + * a call to xQueueSelectFromSet() has first returned a handle to that set member. + * + * @param xQueueOrSemaphore The handle of the queue or semaphore being added to + * the queue set (cast to an QueueSetMemberHandle_t type). + * + * @param xQueueSet The handle of the queue set to which the queue or semaphore + * is being added. + * + * @return If the queue or semaphore was successfully added to the queue set + * then pdPASS is returned. If the queue could not be successfully added to the + * queue set because it is already a member of a different queue set then pdFAIL + * is returned. + */ +#if ( configUSE_QUEUE_SETS == 1 ) + BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION; +#endif + +/* + * Removes a queue or semaphore from a queue set. A queue or semaphore can only + * be removed from a set if the queue or semaphore is empty. + * + * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this + * function. + * + * @param xQueueOrSemaphore The handle of the queue or semaphore being removed + * from the queue set (cast to an QueueSetMemberHandle_t type). + * + * @param xQueueSet The handle of the queue set in which the queue or semaphore + * is included. + * + * @return If the queue or semaphore was successfully removed from the queue set + * then pdPASS is returned. If the queue was not in the queue set, or the + * queue (or semaphore) was not empty, then pdFAIL is returned. + */ +#if ( configUSE_QUEUE_SETS == 1 ) + BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION; +#endif + +/* + * xQueueSelectFromSet() selects from the members of a queue set a queue or + * semaphore that either contains data (in the case of a queue) or is available + * to take (in the case of a semaphore). xQueueSelectFromSet() effectively + * allows a task to block (pend) on a read operation on all the queues and + * semaphores in a queue set simultaneously. + * + * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this + * function. + * + * Note 1: See the documentation on https://www.freertos.org/Documentation/02-Kernel/04-API-references/07-Queue-sets/00-RTOS-queue-sets + * for reasons why queue sets are very rarely needed in practice as there are + * simpler methods of blocking on multiple objects. + * + * Note 2: Blocking on a queue set that contains a mutex will not cause the + * mutex holder to inherit the priority of the blocked task. + * + * Note 3: A receive (in the case of a queue) or take (in the case of a + * semaphore) operation must not be performed on a member of a queue set unless + * a call to xQueueSelectFromSet() has first returned a handle to that set member. + * + * @param xQueueSet The queue set on which the task will (potentially) block. + * + * @param xTicksToWait The maximum time, in ticks, that the calling task will + * remain in the Blocked state (with other tasks executing) to wait for a member + * of the queue set to be ready for a successful queue read or semaphore take + * operation. + * + * @return xQueueSelectFromSet() will return the handle of a queue (cast to + * a QueueSetMemberHandle_t type) contained in the queue set that contains data, + * or the handle of a semaphore (cast to a QueueSetMemberHandle_t type) contained + * in the queue set that is available, or NULL if no such queue or semaphore + * exists before before the specified block time expires. + */ +#if ( configUSE_QUEUE_SETS == 1 ) + QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; +#endif + +/* + * A version of xQueueSelectFromSet() that can be used from an ISR. + */ +#if ( configUSE_QUEUE_SETS == 1 ) + QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION; +#endif + +/* Not public API functions. */ +void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, + TickType_t xTicksToWait, + const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION; +BaseType_t xQueueGenericReset( QueueHandle_t xQueue, + BaseType_t xNewQueue ) PRIVILEGED_FUNCTION; + +#if ( configUSE_TRACE_FACILITY == 1 ) + void vQueueSetQueueNumber( QueueHandle_t xQueue, + UBaseType_t uxQueueNumber ) PRIVILEGED_FUNCTION; +#endif + +#if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; +#endif + +#if ( configUSE_TRACE_FACILITY == 1 ) + uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; +#endif + +UBaseType_t uxQueueGetQueueItemSize( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; +UBaseType_t uxQueueGetQueueLength( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* QUEUE_H */ diff --git a/include/semphr.h b/include/semphr.h new file mode 100644 index 000000000..7b44d78c0 --- /dev/null +++ b/include/semphr.h @@ -0,0 +1,1215 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef SEMAPHORE_H +#define SEMAPHORE_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h" must appear in source files before "include semphr.h" +#endif + +#include "queue.h" + +typedef QueueHandle_t SemaphoreHandle_t; + +#define semBINARY_SEMAPHORE_QUEUE_LENGTH ( ( UBaseType_t ) 1U ) +#define semSEMAPHORE_QUEUE_ITEM_LENGTH ( ( UBaseType_t ) 0U ) +#define semGIVE_BLOCK_TIME ( ( TickType_t ) 0U ) + + +/** + * semphr. h + * @code{c} + * vSemaphoreCreateBinary( SemaphoreHandle_t xSemaphore ); + * @endcode + * + * In many usage scenarios it is faster and more memory efficient to use a + * direct to task notification in place of a binary semaphore! + * https://www.FreeRTOS.org/RTOS-task-notifications.html + * + * This old vSemaphoreCreateBinary() macro is now deprecated in favour of the + * xSemaphoreCreateBinary() function. Note that binary semaphores created using + * the vSemaphoreCreateBinary() macro are created in a state such that the + * first call to 'take' the semaphore would pass, whereas binary semaphores + * created using xSemaphoreCreateBinary() are created in a state such that the + * the semaphore must first be 'given' before it can be 'taken'. + * + * Macro that implements a semaphore by using the existing queue mechanism. + * The queue length is 1 as this is a binary semaphore. The data size is 0 + * as we don't want to actually store any data - we just want to know if the + * queue is empty or full. + * + * This type of semaphore can be used for pure synchronisation between tasks or + * between an interrupt and a task. The semaphore need not be given back once + * obtained, so one task/interrupt can continuously 'give' the semaphore while + * another continuously 'takes' the semaphore. For this reason this type of + * semaphore does not use a priority inheritance mechanism. For an alternative + * that does use priority inheritance see xSemaphoreCreateMutex(). + * + * @param xSemaphore Handle to the created semaphore. Should be of type SemaphoreHandle_t. + * + * Example usage: + * @code{c} + * SemaphoreHandle_t xSemaphore = NULL; + * + * void vATask( void * pvParameters ) + * { + * // Semaphore cannot be used before a call to vSemaphoreCreateBinary (). + * // This is a macro so pass the variable in directly. + * vSemaphoreCreateBinary( xSemaphore ); + * + * if( xSemaphore != NULL ) + * { + * // The semaphore was created successfully. + * // The semaphore can now be used. + * } + * } + * @endcode + * \defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary + * \ingroup Semaphores + */ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + #define vSemaphoreCreateBinary( xSemaphore ) \ + do { \ + ( xSemaphore ) = xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE ); \ + if( ( xSemaphore ) != NULL ) \ + { \ + ( void ) xSemaphoreGive( ( xSemaphore ) ); \ + } \ + } while( 0 ) +#endif + +/** + * semphr. h + * @code{c} + * SemaphoreHandle_t xSemaphoreCreateBinary( void ); + * @endcode + * + * Creates a new binary semaphore instance, and returns a handle by which the + * new semaphore can be referenced. + * + * In many usage scenarios it is faster and more memory efficient to use a + * direct to task notification in place of a binary semaphore! + * https://www.FreeRTOS.org/RTOS-task-notifications.html + * + * Internally, within the FreeRTOS implementation, binary semaphores use a block + * of memory, in which the semaphore structure is stored. If a binary semaphore + * is created using xSemaphoreCreateBinary() then the required memory is + * automatically dynamically allocated inside the xSemaphoreCreateBinary() + * function. (see https://www.FreeRTOS.org/a00111.html). If a binary semaphore + * is created using xSemaphoreCreateBinaryStatic() then the application writer + * must provide the memory. xSemaphoreCreateBinaryStatic() therefore allows a + * binary semaphore to be created without using any dynamic memory allocation. + * + * The old vSemaphoreCreateBinary() macro is now deprecated in favour of this + * xSemaphoreCreateBinary() function. Note that binary semaphores created using + * the vSemaphoreCreateBinary() macro are created in a state such that the + * first call to 'take' the semaphore would pass, whereas binary semaphores + * created using xSemaphoreCreateBinary() are created in a state such that the + * the semaphore must first be 'given' before it can be 'taken'. + * + * This type of semaphore can be used for pure synchronisation between tasks or + * between an interrupt and a task. The semaphore need not be given back once + * obtained, so one task/interrupt can continuously 'give' the semaphore while + * another continuously 'takes' the semaphore. For this reason this type of + * semaphore does not use a priority inheritance mechanism. For an alternative + * that does use priority inheritance see xSemaphoreCreateMutex(). + * + * @return Handle to the created semaphore, or NULL if the memory required to + * hold the semaphore's data structures could not be allocated. + * + * Example usage: + * @code{c} + * SemaphoreHandle_t xSemaphore = NULL; + * + * void vATask( void * pvParameters ) + * { + * // Semaphore cannot be used before a call to xSemaphoreCreateBinary(). + * // This is a macro so pass the variable in directly. + * xSemaphore = xSemaphoreCreateBinary(); + * + * if( xSemaphore != NULL ) + * { + * // The semaphore was created successfully. + * // The semaphore can now be used. + * } + * } + * @endcode + * \defgroup xSemaphoreCreateBinary xSemaphoreCreateBinary + * \ingroup Semaphores + */ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + #define xSemaphoreCreateBinary() xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE ) +#endif + +/** + * semphr. h + * @code{c} + * SemaphoreHandle_t xSemaphoreCreateBinaryStatic( StaticSemaphore_t *pxSemaphoreBuffer ); + * @endcode + * + * Creates a new binary semaphore instance, and returns a handle by which the + * new semaphore can be referenced. + * + * NOTE: In many usage scenarios it is faster and more memory efficient to use a + * direct to task notification in place of a binary semaphore! + * https://www.FreeRTOS.org/RTOS-task-notifications.html + * + * Internally, within the FreeRTOS implementation, binary semaphores use a block + * of memory, in which the semaphore structure is stored. If a binary semaphore + * is created using xSemaphoreCreateBinary() then the required memory is + * automatically dynamically allocated inside the xSemaphoreCreateBinary() + * function. (see https://www.FreeRTOS.org/a00111.html). If a binary semaphore + * is created using xSemaphoreCreateBinaryStatic() then the application writer + * must provide the memory. xSemaphoreCreateBinaryStatic() therefore allows a + * binary semaphore to be created without using any dynamic memory allocation. + * + * This type of semaphore can be used for pure synchronisation between tasks or + * between an interrupt and a task. The semaphore need not be given back once + * obtained, so one task/interrupt can continuously 'give' the semaphore while + * another continuously 'takes' the semaphore. For this reason this type of + * semaphore does not use a priority inheritance mechanism. For an alternative + * that does use priority inheritance see xSemaphoreCreateMutex(). + * + * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t, + * which will then be used to hold the semaphore's data structure, removing the + * need for the memory to be allocated dynamically. + * + * @return If the semaphore is created then a handle to the created semaphore is + * returned. If pxSemaphoreBuffer is NULL then NULL is returned. + * + * Example usage: + * @code{c} + * SemaphoreHandle_t xSemaphore = NULL; + * StaticSemaphore_t xSemaphoreBuffer; + * + * void vATask( void * pvParameters ) + * { + * // Semaphore cannot be used before a call to xSemaphoreCreateBinary(). + * // The semaphore's data structures will be placed in the xSemaphoreBuffer + * // variable, the address of which is passed into the function. The + * // function's parameter is not NULL, so the function will not attempt any + * // dynamic memory allocation, and therefore the function will not return + * // return NULL. + * xSemaphore = xSemaphoreCreateBinary( &xSemaphoreBuffer ); + * + * // Rest of task code goes here. + * } + * @endcode + * \defgroup xSemaphoreCreateBinaryStatic xSemaphoreCreateBinaryStatic + * \ingroup Semaphores + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + #define xSemaphoreCreateBinaryStatic( pxStaticSemaphore ) xQueueGenericCreateStatic( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, ( pxStaticSemaphore ), queueQUEUE_TYPE_BINARY_SEMAPHORE ) +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +/** + * semphr. h + * @code{c} + * xSemaphoreTake( + * SemaphoreHandle_t xSemaphore, + * TickType_t xBlockTime + * ); + * @endcode + * + * Macro to obtain a semaphore. The semaphore must have previously been + * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or + * xSemaphoreCreateCounting(). + * + * @param xSemaphore A handle to the semaphore being taken - obtained when + * the semaphore was created. + * + * @param xBlockTime The time in ticks to wait for the semaphore to become + * available. The macro portTICK_PERIOD_MS can be used to convert this to a + * real time. A block time of zero can be used to poll the semaphore. A block + * time of portMAX_DELAY can be used to block indefinitely (provided + * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h). + * + * @return pdTRUE if the semaphore was obtained. pdFALSE + * if xBlockTime expired without the semaphore becoming available. + * + * Example usage: + * @code{c} + * SemaphoreHandle_t xSemaphore = NULL; + * + * // A task that creates a semaphore. + * void vATask( void * pvParameters ) + * { + * // Create the semaphore to guard a shared resource. + * xSemaphore = xSemaphoreCreateBinary(); + * } + * + * // A task that uses the semaphore. + * void vAnotherTask( void * pvParameters ) + * { + * // ... Do other things. + * + * if( xSemaphore != NULL ) + * { + * // See if we can obtain the semaphore. If the semaphore is not available + * // wait 10 ticks to see if it becomes free. + * if( xSemaphoreTake( xSemaphore, ( TickType_t ) 10 ) == pdTRUE ) + * { + * // We were able to obtain the semaphore and can now access the + * // shared resource. + * + * // ... + * + * // We have finished accessing the shared resource. Release the + * // semaphore. + * xSemaphoreGive( xSemaphore ); + * } + * else + * { + * // We could not obtain the semaphore and can therefore not access + * // the shared resource safely. + * } + * } + * } + * @endcode + * \defgroup xSemaphoreTake xSemaphoreTake + * \ingroup Semaphores + */ +#define xSemaphoreTake( xSemaphore, xBlockTime ) xQueueSemaphoreTake( ( xSemaphore ), ( xBlockTime ) ) + +/** + * semphr. h + * @code{c} + * xSemaphoreTakeRecursive( + * SemaphoreHandle_t xMutex, + * TickType_t xBlockTime + * ); + * @endcode + * + * Macro to recursively obtain, or 'take', a mutex type semaphore. + * The mutex must have previously been created using a call to + * xSemaphoreCreateRecursiveMutex(); + * + * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this + * macro to be available. + * + * This macro must not be used on mutexes created using xSemaphoreCreateMutex(). + * + * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex + * doesn't become available again until the owner has called + * xSemaphoreGiveRecursive() for each successful 'take' request. For example, + * if a task successfully 'takes' the same mutex 5 times then the mutex will + * not be available to any other task until it has also 'given' the mutex back + * exactly five times. + * + * @param xMutex A handle to the mutex being obtained. This is the + * handle returned by xSemaphoreCreateRecursiveMutex(); + * + * @param xBlockTime The time in ticks to wait for the semaphore to become + * available. The macro portTICK_PERIOD_MS can be used to convert this to a + * real time. A block time of zero can be used to poll the semaphore. If + * the task already owns the semaphore then xSemaphoreTakeRecursive() will + * return immediately no matter what the value of xBlockTime. + * + * @return pdTRUE if the semaphore was obtained. pdFALSE if xBlockTime + * expired without the semaphore becoming available. + * + * Example usage: + * @code{c} + * SemaphoreHandle_t xMutex = NULL; + * + * // A task that creates a mutex. + * void vATask( void * pvParameters ) + * { + * // Create the mutex to guard a shared resource. + * xMutex = xSemaphoreCreateRecursiveMutex(); + * } + * + * // A task that uses the mutex. + * void vAnotherTask( void * pvParameters ) + * { + * // ... Do other things. + * + * if( xMutex != NULL ) + * { + * // See if we can obtain the mutex. If the mutex is not available + * // wait 10 ticks to see if it becomes free. + * if( xSemaphoreTakeRecursive( xSemaphore, ( TickType_t ) 10 ) == pdTRUE ) + * { + * // We were able to obtain the mutex and can now access the + * // shared resource. + * + * // ... + * // For some reason due to the nature of the code further calls to + * // xSemaphoreTakeRecursive() are made on the same mutex. In real + * // code these would not be just sequential calls as this would make + * // no sense. Instead the calls are likely to be buried inside + * // a more complex call structure. + * xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 ); + * xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 ); + * + * // The mutex has now been 'taken' three times, so will not be + * // available to another task until it has also been given back + * // three times. Again it is unlikely that real code would have + * // these calls sequentially, but instead buried in a more complex + * // call structure. This is just for illustrative purposes. + * xSemaphoreGiveRecursive( xMutex ); + * xSemaphoreGiveRecursive( xMutex ); + * xSemaphoreGiveRecursive( xMutex ); + * + * // Now the mutex can be taken by other tasks. + * } + * else + * { + * // We could not obtain the mutex and can therefore not access + * // the shared resource safely. + * } + * } + * } + * @endcode + * \defgroup xSemaphoreTakeRecursive xSemaphoreTakeRecursive + * \ingroup Semaphores + */ +#if ( configUSE_RECURSIVE_MUTEXES == 1 ) + #define xSemaphoreTakeRecursive( xMutex, xBlockTime ) xQueueTakeMutexRecursive( ( xMutex ), ( xBlockTime ) ) +#endif + +/** + * semphr. h + * @code{c} + * xSemaphoreGive( SemaphoreHandle_t xSemaphore ); + * @endcode + * + * Macro to release a semaphore. The semaphore must have previously been + * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or + * xSemaphoreCreateCounting(). and obtained using sSemaphoreTake(). + * + * This macro must not be used from an ISR. See xSemaphoreGiveFromISR () for + * an alternative which can be used from an ISR. + * + * This macro must also not be used on semaphores created using + * xSemaphoreCreateRecursiveMutex(). + * + * @param xSemaphore A handle to the semaphore being released. This is the + * handle returned when the semaphore was created. + * + * @return pdTRUE if the semaphore was released. pdFALSE if an error occurred. + * Semaphores are implemented using queues. An error can occur if there is + * no space on the queue to post a message - indicating that the + * semaphore was not first obtained correctly. + * + * Example usage: + * @code{c} + * SemaphoreHandle_t xSemaphore = NULL; + * + * void vATask( void * pvParameters ) + * { + * // Create the semaphore to guard a shared resource. + * xSemaphore = vSemaphoreCreateBinary(); + * + * if( xSemaphore != NULL ) + * { + * if( xSemaphoreGive( xSemaphore ) != pdTRUE ) + * { + * // We would expect this call to fail because we cannot give + * // a semaphore without first "taking" it! + * } + * + * // Obtain the semaphore - don't block if the semaphore is not + * // immediately available. + * if( xSemaphoreTake( xSemaphore, ( TickType_t ) 0 ) ) + * { + * // We now have the semaphore and can access the shared resource. + * + * // ... + * + * // We have finished accessing the shared resource so can free the + * // semaphore. + * if( xSemaphoreGive( xSemaphore ) != pdTRUE ) + * { + * // We would not expect this call to fail because we must have + * // obtained the semaphore to get here. + * } + * } + * } + * } + * @endcode + * \defgroup xSemaphoreGive xSemaphoreGive + * \ingroup Semaphores + */ +#define xSemaphoreGive( xSemaphore ) xQueueGenericSend( ( QueueHandle_t ) ( xSemaphore ), NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK ) + +/** + * semphr. h + * @code{c} + * xSemaphoreGiveRecursive( SemaphoreHandle_t xMutex ); + * @endcode + * + * Macro to recursively release, or 'give', a mutex type semaphore. + * The mutex must have previously been created using a call to + * xSemaphoreCreateRecursiveMutex(); + * + * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this + * macro to be available. + * + * This macro must not be used on mutexes created using xSemaphoreCreateMutex(). + * + * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex + * doesn't become available again until the owner has called + * xSemaphoreGiveRecursive() for each successful 'take' request. For example, + * if a task successfully 'takes' the same mutex 5 times then the mutex will + * not be available to any other task until it has also 'given' the mutex back + * exactly five times. + * + * @param xMutex A handle to the mutex being released, or 'given'. This is the + * handle returned by xSemaphoreCreateMutex(); + * + * @return pdTRUE if the semaphore was given. + * + * Example usage: + * @code{c} + * SemaphoreHandle_t xMutex = NULL; + * + * // A task that creates a mutex. + * void vATask( void * pvParameters ) + * { + * // Create the mutex to guard a shared resource. + * xMutex = xSemaphoreCreateRecursiveMutex(); + * } + * + * // A task that uses the mutex. + * void vAnotherTask( void * pvParameters ) + * { + * // ... Do other things. + * + * if( xMutex != NULL ) + * { + * // See if we can obtain the mutex. If the mutex is not available + * // wait 10 ticks to see if it becomes free. + * if( xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 ) == pdTRUE ) + * { + * // We were able to obtain the mutex and can now access the + * // shared resource. + * + * // ... + * // For some reason due to the nature of the code further calls to + * // xSemaphoreTakeRecursive() are made on the same mutex. In real + * // code these would not be just sequential calls as this would make + * // no sense. Instead the calls are likely to be buried inside + * // a more complex call structure. + * xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 ); + * xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 ); + * + * // The mutex has now been 'taken' three times, so will not be + * // available to another task until it has also been given back + * // three times. Again it is unlikely that real code would have + * // these calls sequentially, it would be more likely that the calls + * // to xSemaphoreGiveRecursive() would be called as a call stack + * // unwound. This is just for demonstrative purposes. + * xSemaphoreGiveRecursive( xMutex ); + * xSemaphoreGiveRecursive( xMutex ); + * xSemaphoreGiveRecursive( xMutex ); + * + * // Now the mutex can be taken by other tasks. + * } + * else + * { + * // We could not obtain the mutex and can therefore not access + * // the shared resource safely. + * } + * } + * } + * @endcode + * \defgroup xSemaphoreGiveRecursive xSemaphoreGiveRecursive + * \ingroup Semaphores + */ +#if ( configUSE_RECURSIVE_MUTEXES == 1 ) + #define xSemaphoreGiveRecursive( xMutex ) xQueueGiveMutexRecursive( ( xMutex ) ) +#endif + +/** + * semphr. h + * @code{c} + * xSemaphoreGiveFromISR( + * SemaphoreHandle_t xSemaphore, + * BaseType_t *pxHigherPriorityTaskWoken + * ); + * @endcode + * + * Macro to release a semaphore. The semaphore must have previously been + * created with a call to xSemaphoreCreateBinary() or xSemaphoreCreateCounting(). + * + * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex()) + * must not be used with this macro. + * + * This macro can be used from an ISR. + * + * @param xSemaphore A handle to the semaphore being released. This is the + * handle returned when the semaphore was created. + * + * @param pxHigherPriorityTaskWoken xSemaphoreGiveFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if giving the semaphore caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xSemaphoreGiveFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @return pdTRUE if the semaphore was successfully given, otherwise errQUEUE_FULL. + * + * Example usage: + * @code{c} + \#define LONG_TIME 0xffff + \#define TICKS_TO_WAIT 10 + * SemaphoreHandle_t xSemaphore = NULL; + * + * // Repetitive task. + * void vATask( void * pvParameters ) + * { + * for( ;; ) + * { + * // We want this task to run every 10 ticks of a timer. The semaphore + * // was created before this task was started. + * + * // Block waiting for the semaphore to become available. + * if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE ) + * { + * // It is time to execute. + * + * // ... + * + * // We have finished our task. Return to the top of the loop where + * // we will block on the semaphore until it is time to execute + * // again. Note when using the semaphore for synchronisation with an + * // ISR in this manner there is no need to 'give' the semaphore back. + * } + * } + * } + * + * // Timer ISR + * void vTimerISR( void * pvParameters ) + * { + * static uint8_t ucLocalTickCount = 0; + * static BaseType_t xHigherPriorityTaskWoken; + * + * // A timer tick has occurred. + * + * // ... Do other time functions. + * + * // Is it time for vATask () to run? + * xHigherPriorityTaskWoken = pdFALSE; + * ucLocalTickCount++; + * if( ucLocalTickCount >= TICKS_TO_WAIT ) + * { + * // Unblock the task by releasing the semaphore. + * xSemaphoreGiveFromISR( xSemaphore, &xHigherPriorityTaskWoken ); + * + * // Reset the count so we release the semaphore again in 10 ticks time. + * ucLocalTickCount = 0; + * } + * + * if( xHigherPriorityTaskWoken != pdFALSE ) + * { + * // We can force a context switch here. Context switching from an + * // ISR uses port specific syntax. Check the demo task for your port + * // to find the syntax required. + * } + * } + * @endcode + * \defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR + * \ingroup Semaphores + */ +#define xSemaphoreGiveFromISR( xSemaphore, pxHigherPriorityTaskWoken ) xQueueGiveFromISR( ( QueueHandle_t ) ( xSemaphore ), ( pxHigherPriorityTaskWoken ) ) + +/** + * semphr. h + * @code{c} + * xSemaphoreTakeFromISR( + * SemaphoreHandle_t xSemaphore, + * BaseType_t *pxHigherPriorityTaskWoken + * ); + * @endcode + * + * Macro to take a semaphore from an ISR. The semaphore must have + * previously been created with a call to xSemaphoreCreateBinary() or + * xSemaphoreCreateCounting(). + * + * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex()) + * must not be used with this macro. + * + * This macro can be used from an ISR, however taking a semaphore from an ISR + * is not a common operation. It is likely to only be useful when taking a + * counting semaphore when an interrupt is obtaining an object from a resource + * pool (when the semaphore count indicates the number of resources available). + * + * @param xSemaphore A handle to the semaphore being taken. This is the + * handle returned when the semaphore was created. + * + * @param pxHigherPriorityTaskWoken xSemaphoreTakeFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if taking the semaphore caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xSemaphoreTakeFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @return pdTRUE if the semaphore was successfully taken, otherwise + * pdFALSE + */ +#define xSemaphoreTakeFromISR( xSemaphore, pxHigherPriorityTaskWoken ) xQueueReceiveFromISR( ( QueueHandle_t ) ( xSemaphore ), NULL, ( pxHigherPriorityTaskWoken ) ) + +/** + * semphr. h + * @code{c} + * SemaphoreHandle_t xSemaphoreCreateMutex( void ); + * @endcode + * + * Creates a new mutex type semaphore instance, and returns a handle by which + * the new mutex can be referenced. + * + * Internally, within the FreeRTOS implementation, mutex semaphores use a block + * of memory, in which the mutex structure is stored. If a mutex is created + * using xSemaphoreCreateMutex() then the required memory is automatically + * dynamically allocated inside the xSemaphoreCreateMutex() function. (see + * https://www.FreeRTOS.org/a00111.html). If a mutex is created using + * xSemaphoreCreateMutexStatic() then the application writer must provided the + * memory. xSemaphoreCreateMutexStatic() therefore allows a mutex to be created + * without using any dynamic memory allocation. + * + * Mutexes created using this function can be accessed using the xSemaphoreTake() + * and xSemaphoreGive() macros. The xSemaphoreTakeRecursive() and + * xSemaphoreGiveRecursive() macros must not be used. + * + * This type of semaphore uses a priority inheritance mechanism so a task + * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the + * semaphore it is no longer required. + * + * Mutex type semaphores cannot be used from within interrupt service routines. + * + * See xSemaphoreCreateBinary() for an alternative implementation that can be + * used for pure synchronisation (where one task or interrupt always 'gives' the + * semaphore and another always 'takes' the semaphore) and from within interrupt + * service routines. + * + * @return If the mutex was successfully created then a handle to the created + * semaphore is returned. If there was not enough heap to allocate the mutex + * data structures then NULL is returned. + * + * Example usage: + * @code{c} + * SemaphoreHandle_t xSemaphore; + * + * void vATask( void * pvParameters ) + * { + * // Semaphore cannot be used before a call to xSemaphoreCreateMutex(). + * // This is a macro so pass the variable in directly. + * xSemaphore = xSemaphoreCreateMutex(); + * + * if( xSemaphore != NULL ) + * { + * // The semaphore was created successfully. + * // The semaphore can now be used. + * } + * } + * @endcode + * \defgroup xSemaphoreCreateMutex xSemaphoreCreateMutex + * \ingroup Semaphores + */ +#if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_MUTEXES == 1 ) ) + #define xSemaphoreCreateMutex() xQueueCreateMutex( queueQUEUE_TYPE_MUTEX ) +#endif + +/** + * semphr. h + * @code{c} + * SemaphoreHandle_t xSemaphoreCreateMutexStatic( StaticSemaphore_t *pxMutexBuffer ); + * @endcode + * + * Creates a new mutex type semaphore instance, and returns a handle by which + * the new mutex can be referenced. + * + * Internally, within the FreeRTOS implementation, mutex semaphores use a block + * of memory, in which the mutex structure is stored. If a mutex is created + * using xSemaphoreCreateMutex() then the required memory is automatically + * dynamically allocated inside the xSemaphoreCreateMutex() function. (see + * https://www.FreeRTOS.org/a00111.html). If a mutex is created using + * xSemaphoreCreateMutexStatic() then the application writer must provided the + * memory. xSemaphoreCreateMutexStatic() therefore allows a mutex to be created + * without using any dynamic memory allocation. + * + * Mutexes created using this function can be accessed using the xSemaphoreTake() + * and xSemaphoreGive() macros. The xSemaphoreTakeRecursive() and + * xSemaphoreGiveRecursive() macros must not be used. + * + * This type of semaphore uses a priority inheritance mechanism so a task + * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the + * semaphore it is no longer required. + * + * Mutex type semaphores cannot be used from within interrupt service routines. + * + * See xSemaphoreCreateBinary() for an alternative implementation that can be + * used for pure synchronisation (where one task or interrupt always 'gives' the + * semaphore and another always 'takes' the semaphore) and from within interrupt + * service routines. + * + * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t, + * which will be used to hold the mutex's data structure, removing the need for + * the memory to be allocated dynamically. + * + * @return If the mutex was successfully created then a handle to the created + * mutex is returned. If pxMutexBuffer was NULL then NULL is returned. + * + * Example usage: + * @code{c} + * SemaphoreHandle_t xSemaphore; + * StaticSemaphore_t xMutexBuffer; + * + * void vATask( void * pvParameters ) + * { + * // A mutex cannot be used before it has been created. xMutexBuffer is + * // into xSemaphoreCreateMutexStatic() so no dynamic memory allocation is + * // attempted. + * xSemaphore = xSemaphoreCreateMutexStatic( &xMutexBuffer ); + * + * // As no dynamic memory allocation was performed, xSemaphore cannot be NULL, + * // so there is no need to check it. + * } + * @endcode + * \defgroup xSemaphoreCreateMutexStatic xSemaphoreCreateMutexStatic + * \ingroup Semaphores + */ +#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_MUTEXES == 1 ) ) + #define xSemaphoreCreateMutexStatic( pxMutexBuffer ) xQueueCreateMutexStatic( queueQUEUE_TYPE_MUTEX, ( pxMutexBuffer ) ) +#endif + + +/** + * semphr. h + * @code{c} + * SemaphoreHandle_t xSemaphoreCreateRecursiveMutex( void ); + * @endcode + * + * Creates a new recursive mutex type semaphore instance, and returns a handle + * by which the new recursive mutex can be referenced. + * + * Internally, within the FreeRTOS implementation, recursive mutexes use a block + * of memory, in which the mutex structure is stored. If a recursive mutex is + * created using xSemaphoreCreateRecursiveMutex() then the required memory is + * automatically dynamically allocated inside the + * xSemaphoreCreateRecursiveMutex() function. (see + * https://www.FreeRTOS.org/a00111.html). If a recursive mutex is created using + * xSemaphoreCreateRecursiveMutexStatic() then the application writer must + * provide the memory that will get used by the mutex. + * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to + * be created without using any dynamic memory allocation. + * + * Mutexes created using this macro can be accessed using the + * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros. The + * xSemaphoreTake() and xSemaphoreGive() macros must not be used. + * + * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex + * doesn't become available again until the owner has called + * xSemaphoreGiveRecursive() for each successful 'take' request. For example, + * if a task successfully 'takes' the same mutex 5 times then the mutex will + * not be available to any other task until it has also 'given' the mutex back + * exactly five times. + * + * This type of semaphore uses a priority inheritance mechanism so a task + * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the + * semaphore it is no longer required. + * + * Mutex type semaphores cannot be used from within interrupt service routines. + * + * See xSemaphoreCreateBinary() for an alternative implementation that can be + * used for pure synchronisation (where one task or interrupt always 'gives' the + * semaphore and another always 'takes' the semaphore) and from within interrupt + * service routines. + * + * @return xSemaphore Handle to the created mutex semaphore. Should be of type + * SemaphoreHandle_t. + * + * Example usage: + * @code{c} + * SemaphoreHandle_t xSemaphore; + * + * void vATask( void * pvParameters ) + * { + * // Semaphore cannot be used before a call to xSemaphoreCreateMutex(). + * // This is a macro so pass the variable in directly. + * xSemaphore = xSemaphoreCreateRecursiveMutex(); + * + * if( xSemaphore != NULL ) + * { + * // The semaphore was created successfully. + * // The semaphore can now be used. + * } + * } + * @endcode + * \defgroup xSemaphoreCreateRecursiveMutex xSemaphoreCreateRecursiveMutex + * \ingroup Semaphores + */ +#if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) ) + #define xSemaphoreCreateRecursiveMutex() xQueueCreateMutex( queueQUEUE_TYPE_RECURSIVE_MUTEX ) +#endif + +/** + * semphr. h + * @code{c} + * SemaphoreHandle_t xSemaphoreCreateRecursiveMutexStatic( StaticSemaphore_t *pxMutexBuffer ); + * @endcode + * + * Creates a new recursive mutex type semaphore instance, and returns a handle + * by which the new recursive mutex can be referenced. + * + * Internally, within the FreeRTOS implementation, recursive mutexes use a block + * of memory, in which the mutex structure is stored. If a recursive mutex is + * created using xSemaphoreCreateRecursiveMutex() then the required memory is + * automatically dynamically allocated inside the + * xSemaphoreCreateRecursiveMutex() function. (see + * https://www.FreeRTOS.org/a00111.html). If a recursive mutex is created using + * xSemaphoreCreateRecursiveMutexStatic() then the application writer must + * provide the memory that will get used by the mutex. + * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to + * be created without using any dynamic memory allocation. + * + * Mutexes created using this macro can be accessed using the + * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros. The + * xSemaphoreTake() and xSemaphoreGive() macros must not be used. + * + * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex + * doesn't become available again until the owner has called + * xSemaphoreGiveRecursive() for each successful 'take' request. For example, + * if a task successfully 'takes' the same mutex 5 times then the mutex will + * not be available to any other task until it has also 'given' the mutex back + * exactly five times. + * + * This type of semaphore uses a priority inheritance mechanism so a task + * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the + * semaphore it is no longer required. + * + * Mutex type semaphores cannot be used from within interrupt service routines. + * + * See xSemaphoreCreateBinary() for an alternative implementation that can be + * used for pure synchronisation (where one task or interrupt always 'gives' the + * semaphore and another always 'takes' the semaphore) and from within interrupt + * service routines. + * + * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t, + * which will then be used to hold the recursive mutex's data structure, + * removing the need for the memory to be allocated dynamically. + * + * @return If the recursive mutex was successfully created then a handle to the + * created recursive mutex is returned. If pxMutexBuffer was NULL then NULL is + * returned. + * + * Example usage: + * @code{c} + * SemaphoreHandle_t xSemaphore; + * StaticSemaphore_t xMutexBuffer; + * + * void vATask( void * pvParameters ) + * { + * // A recursive semaphore cannot be used before it is created. Here a + * // recursive mutex is created using xSemaphoreCreateRecursiveMutexStatic(). + * // The address of xMutexBuffer is passed into the function, and will hold + * // the mutexes data structures - so no dynamic memory allocation will be + * // attempted. + * xSemaphore = xSemaphoreCreateRecursiveMutexStatic( &xMutexBuffer ); + * + * // As no dynamic memory allocation was performed, xSemaphore cannot be NULL, + * // so there is no need to check it. + * } + * @endcode + * \defgroup xSemaphoreCreateRecursiveMutexStatic xSemaphoreCreateRecursiveMutexStatic + * \ingroup Semaphores + */ +#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) ) + #define xSemaphoreCreateRecursiveMutexStatic( pxStaticSemaphore ) xQueueCreateMutexStatic( queueQUEUE_TYPE_RECURSIVE_MUTEX, ( pxStaticSemaphore ) ) +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +/** + * semphr. h + * @code{c} + * SemaphoreHandle_t xSemaphoreCreateCounting( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount ); + * @endcode + * + * Creates a new counting semaphore instance, and returns a handle by which the + * new counting semaphore can be referenced. + * + * In many usage scenarios it is faster and more memory efficient to use a + * direct to task notification in place of a counting semaphore! + * https://www.FreeRTOS.org/RTOS-task-notifications.html + * + * Internally, within the FreeRTOS implementation, counting semaphores use a + * block of memory, in which the counting semaphore structure is stored. If a + * counting semaphore is created using xSemaphoreCreateCounting() then the + * required memory is automatically dynamically allocated inside the + * xSemaphoreCreateCounting() function. (see + * https://www.FreeRTOS.org/a00111.html). If a counting semaphore is created + * using xSemaphoreCreateCountingStatic() then the application writer can + * instead optionally provide the memory that will get used by the counting + * semaphore. xSemaphoreCreateCountingStatic() therefore allows a counting + * semaphore to be created without using any dynamic memory allocation. + * + * Counting semaphores are typically used for two things: + * + * 1) Counting events. + * + * In this usage scenario an event handler will 'give' a semaphore each time + * an event occurs (incrementing the semaphore count value), and a handler + * task will 'take' a semaphore each time it processes an event + * (decrementing the semaphore count value). The count value is therefore + * the difference between the number of events that have occurred and the + * number that have been processed. In this case it is desirable for the + * initial count value to be zero. + * + * 2) Resource management. + * + * In this usage scenario the count value indicates the number of resources + * available. To obtain control of a resource a task must first obtain a + * semaphore - decrementing the semaphore count value. When the count value + * reaches zero there are no free resources. When a task finishes with the + * resource it 'gives' the semaphore back - incrementing the semaphore count + * value. In this case it is desirable for the initial count value to be + * equal to the maximum count value, indicating that all resources are free. + * + * @param uxMaxCount The maximum count value that can be reached. When the + * semaphore reaches this value it can no longer be 'given'. + * + * @param uxInitialCount The count value assigned to the semaphore when it is + * created. + * + * @return Handle to the created semaphore. Null if the semaphore could not be + * created. + * + * Example usage: + * @code{c} + * SemaphoreHandle_t xSemaphore; + * + * void vATask( void * pvParameters ) + * { + * SemaphoreHandle_t xSemaphore = NULL; + * + * // Semaphore cannot be used before a call to xSemaphoreCreateCounting(). + * // The max value to which the semaphore can count should be 10, and the + * // initial value assigned to the count should be 0. + * xSemaphore = xSemaphoreCreateCounting( 10, 0 ); + * + * if( xSemaphore != NULL ) + * { + * // The semaphore was created successfully. + * // The semaphore can now be used. + * } + * } + * @endcode + * \defgroup xSemaphoreCreateCounting xSemaphoreCreateCounting + * \ingroup Semaphores + */ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + #define xSemaphoreCreateCounting( uxMaxCount, uxInitialCount ) xQueueCreateCountingSemaphore( ( uxMaxCount ), ( uxInitialCount ) ) +#endif + +/** + * semphr. h + * @code{c} + * SemaphoreHandle_t xSemaphoreCreateCountingStatic( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount, StaticSemaphore_t *pxSemaphoreBuffer ); + * @endcode + * + * Creates a new counting semaphore instance, and returns a handle by which the + * new counting semaphore can be referenced. + * + * In many usage scenarios it is faster and more memory efficient to use a + * direct to task notification in place of a counting semaphore! + * https://www.FreeRTOS.org/RTOS-task-notifications.html + * + * Internally, within the FreeRTOS implementation, counting semaphores use a + * block of memory, in which the counting semaphore structure is stored. If a + * counting semaphore is created using xSemaphoreCreateCounting() then the + * required memory is automatically dynamically allocated inside the + * xSemaphoreCreateCounting() function. (see + * https://www.FreeRTOS.org/a00111.html). If a counting semaphore is created + * using xSemaphoreCreateCountingStatic() then the application writer must + * provide the memory. xSemaphoreCreateCountingStatic() therefore allows a + * counting semaphore to be created without using any dynamic memory allocation. + * + * Counting semaphores are typically used for two things: + * + * 1) Counting events. + * + * In this usage scenario an event handler will 'give' a semaphore each time + * an event occurs (incrementing the semaphore count value), and a handler + * task will 'take' a semaphore each time it processes an event + * (decrementing the semaphore count value). The count value is therefore + * the difference between the number of events that have occurred and the + * number that have been processed. In this case it is desirable for the + * initial count value to be zero. + * + * 2) Resource management. + * + * In this usage scenario the count value indicates the number of resources + * available. To obtain control of a resource a task must first obtain a + * semaphore - decrementing the semaphore count value. When the count value + * reaches zero there are no free resources. When a task finishes with the + * resource it 'gives' the semaphore back - incrementing the semaphore count + * value. In this case it is desirable for the initial count value to be + * equal to the maximum count value, indicating that all resources are free. + * + * @param uxMaxCount The maximum count value that can be reached. When the + * semaphore reaches this value it can no longer be 'given'. + * + * @param uxInitialCount The count value assigned to the semaphore when it is + * created. + * + * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t, + * which will then be used to hold the semaphore's data structure, removing the + * need for the memory to be allocated dynamically. + * + * @return If the counting semaphore was successfully created then a handle to + * the created counting semaphore is returned. If pxSemaphoreBuffer was NULL + * then NULL is returned. + * + * Example usage: + * @code{c} + * SemaphoreHandle_t xSemaphore; + * StaticSemaphore_t xSemaphoreBuffer; + * + * void vATask( void * pvParameters ) + * { + * SemaphoreHandle_t xSemaphore = NULL; + * + * // Counting semaphore cannot be used before they have been created. Create + * // a counting semaphore using xSemaphoreCreateCountingStatic(). The max + * // value to which the semaphore can count is 10, and the initial value + * // assigned to the count will be 0. The address of xSemaphoreBuffer is + * // passed in and will be used to hold the semaphore structure, so no dynamic + * // memory allocation will be used. + * xSemaphore = xSemaphoreCreateCounting( 10, 0, &xSemaphoreBuffer ); + * + * // No memory allocation was attempted so xSemaphore cannot be NULL, so there + * // is no need to check its value. + * } + * @endcode + * \defgroup xSemaphoreCreateCountingStatic xSemaphoreCreateCountingStatic + * \ingroup Semaphores + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + #define xSemaphoreCreateCountingStatic( uxMaxCount, uxInitialCount, pxSemaphoreBuffer ) xQueueCreateCountingSemaphoreStatic( ( uxMaxCount ), ( uxInitialCount ), ( pxSemaphoreBuffer ) ) +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +/** + * semphr. h + * @code{c} + * void vSemaphoreDelete( SemaphoreHandle_t xSemaphore ); + * @endcode + * + * Delete a semaphore. This function must be used with care. For example, + * do not delete a mutex type semaphore if the mutex is held by a task. + * + * @param xSemaphore A handle to the semaphore to be deleted. + * + * \defgroup vSemaphoreDelete vSemaphoreDelete + * \ingroup Semaphores + */ +#define vSemaphoreDelete( xSemaphore ) vQueueDelete( ( QueueHandle_t ) ( xSemaphore ) ) + +/** + * semphr.h + * @code{c} + * TaskHandle_t xSemaphoreGetMutexHolder( SemaphoreHandle_t xMutex ); + * @endcode + * + * If xMutex is indeed a mutex type semaphore, return the current mutex holder. + * If xMutex is not a mutex type semaphore, or the mutex is available (not held + * by a task), return NULL. + * + * Note: This is a good way of determining if the calling task is the mutex + * holder, but not a good way of determining the identity of the mutex holder as + * the holder may change between the function exiting and the returned value + * being tested. + */ +#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) + #define xSemaphoreGetMutexHolder( xSemaphore ) xQueueGetMutexHolder( ( xSemaphore ) ) +#endif + +/** + * semphr.h + * @code{c} + * TaskHandle_t xSemaphoreGetMutexHolderFromISR( SemaphoreHandle_t xMutex ); + * @endcode + * + * If xMutex is indeed a mutex type semaphore, return the current mutex holder. + * If xMutex is not a mutex type semaphore, or the mutex is available (not held + * by a task), return NULL. + * + */ +#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) + #define xSemaphoreGetMutexHolderFromISR( xSemaphore ) xQueueGetMutexHolderFromISR( ( xSemaphore ) ) +#endif + +/** + * semphr.h + * @code{c} + * UBaseType_t uxSemaphoreGetCount( SemaphoreHandle_t xSemaphore ); + * @endcode + * + * If the semaphore is a counting semaphore then uxSemaphoreGetCount() returns + * its current count value. If the semaphore is a binary semaphore then + * uxSemaphoreGetCount() returns 1 if the semaphore is available, and 0 if the + * semaphore is not available. + * + */ +#define uxSemaphoreGetCount( xSemaphore ) uxQueueMessagesWaiting( ( QueueHandle_t ) ( xSemaphore ) ) + +/** + * semphr.h + * @code{c} + * UBaseType_t uxSemaphoreGetCountFromISR( SemaphoreHandle_t xSemaphore ); + * @endcode + * + * If the semaphore is a counting semaphore then uxSemaphoreGetCountFromISR() returns + * its current count value. If the semaphore is a binary semaphore then + * uxSemaphoreGetCountFromISR() returns 1 if the semaphore is available, and 0 if the + * semaphore is not available. + * + */ +#define uxSemaphoreGetCountFromISR( xSemaphore ) uxQueueMessagesWaitingFromISR( ( QueueHandle_t ) ( xSemaphore ) ) + +/** + * semphr.h + * @code{c} + * BaseType_t xSemaphoreGetStaticBuffer( SemaphoreHandle_t xSemaphore, + * StaticSemaphore_t ** ppxSemaphoreBuffer ); + * @endcode + * + * Retrieve pointer to a statically created binary semaphore, counting semaphore, + * or mutex semaphore's data structure buffer. This is the same buffer that is + * supplied at the time of creation. + * + * @param xSemaphore The semaphore for which to retrieve the buffer. + * + * @param ppxSemaphoreBuffer Used to return a pointer to the semaphore's + * data structure buffer. + * + * @return pdTRUE if buffer was retrieved, pdFALSE otherwise. + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + #define xSemaphoreGetStaticBuffer( xSemaphore, ppxSemaphoreBuffer ) xQueueGenericGetStaticBuffers( ( QueueHandle_t ) ( xSemaphore ), NULL, ( ppxSemaphoreBuffer ) ) +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +#endif /* SEMAPHORE_H */ diff --git a/include/stack_macros.h b/include/stack_macros.h new file mode 100644 index 000000000..6d0117722 --- /dev/null +++ b/include/stack_macros.h @@ -0,0 +1,155 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef STACK_MACROS_H +#define STACK_MACROS_H + +/* + * Call the stack overflow hook function if the stack of the task being swapped + * out is currently overflowed, or looks like it might have overflowed in the + * past. + * + * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check + * the current stack state only - comparing the current top of stack value to + * the stack limit. Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1 + * will also cause the last few stack bytes to be checked to ensure the value + * to which the bytes were set when the task was created have not been + * overwritten. Note this second test does not guarantee that an overflowed + * stack will always be recognised. + */ + +/*-----------------------------------------------------------*/ + +/* + * portSTACK_LIMIT_PADDING is a number of extra words to consider to be in + * use on the stack. + */ +#ifndef portSTACK_LIMIT_PADDING + #define portSTACK_LIMIT_PADDING 0 +#endif + +/* Stack overflow check is not straight forward to implement for MPU ports + * because of the following reasons: + * 1. The context is stored in TCB and as a result, pxTopOfStack member points + * to the context location in TCB. + * 2. System calls are executed on a separate privileged only stack. + * + * It is still okay because an MPU region is used to protect task stack which + * means task stack overflow will trigger an MPU fault for unprivileged tasks. + * Additionally, architectures with hardware stack overflow checking support + * (such as Armv8-M) will trigger a fault when a task's stack overflows. + */ +#if ( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) && ( portUSING_MPU_WRAPPERS != 1 ) ) + +/* Only the current stack state is to be checked. */ + #define taskCHECK_FOR_STACK_OVERFLOW() \ + do \ + { \ + /* Is the currently saved stack pointer within the stack limit? */ \ + if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack + portSTACK_LIMIT_PADDING ) \ + { \ + char * pcOverflowTaskName = pxCurrentTCB->pcTaskName; \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pcOverflowTaskName ); \ + } \ + } while( 0 ) + +#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */ +/*-----------------------------------------------------------*/ + +#if ( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) && ( portUSING_MPU_WRAPPERS != 1 ) ) + +/* Only the current stack state is to be checked. */ + #define taskCHECK_FOR_STACK_OVERFLOW() \ + do \ + { \ + /* Is the currently saved stack pointer within the stack limit? */ \ + if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack - portSTACK_LIMIT_PADDING ) \ + { \ + char * pcOverflowTaskName = pxCurrentTCB->pcTaskName; \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pcOverflowTaskName ); \ + } \ + } while( 0 ) + +#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */ +/*-----------------------------------------------------------*/ + +#if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) && ( portUSING_MPU_WRAPPERS != 1 ) ) + + #define taskCHECK_FOR_STACK_OVERFLOW() \ + do \ + { \ + const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack; \ + const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5U; \ + \ + if( ( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack + portSTACK_LIMIT_PADDING ) || \ + ( pulStack[ 0 ] != ulCheckValue ) || \ + ( pulStack[ 1 ] != ulCheckValue ) || \ + ( pulStack[ 2 ] != ulCheckValue ) || \ + ( pulStack[ 3 ] != ulCheckValue ) ) \ + { \ + char * pcOverflowTaskName = pxCurrentTCB->pcTaskName; \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pcOverflowTaskName ); \ + } \ + } while( 0 ) + +#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) && ( portUSING_MPU_WRAPPERS != 1 ) ) + + #define taskCHECK_FOR_STACK_OVERFLOW() \ + do \ + { \ + int8_t * pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack; \ + static const uint8_t ucExpectedStackBytes[] = { tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE }; \ + \ + pcEndOfStack -= sizeof( ucExpectedStackBytes ); \ + \ + if( ( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack - portSTACK_LIMIT_PADDING ) || \ + ( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 ) ) \ + { \ + char * pcOverflowTaskName = pxCurrentTCB->pcTaskName; \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pcOverflowTaskName ); \ + } \ + } while( 0 ) + +#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */ +/*-----------------------------------------------------------*/ + +/* Remove stack overflow macro if not being used. */ +#ifndef taskCHECK_FOR_STACK_OVERFLOW + #define taskCHECK_FOR_STACK_OVERFLOW() +#endif + + + +#endif /* STACK_MACROS_H */ diff --git a/include/stdint.readme b/include/stdint.readme new file mode 100644 index 000000000..bfe3bb6f8 --- /dev/null +++ b/include/stdint.readme @@ -0,0 +1,58 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef FREERTOS_STDINT +#define FREERTOS_STDINT + +/******************************************************************************* + * THIS IS NOT A FULL stdint.h IMPLEMENTATION - It only contains the definitions + * necessary to build the FreeRTOS code. It is provided to allow FreeRTOS to be + * built using compilers that do not provide their own stdint.h definition. + * + * To use this file: + * + * 1) Copy this file into the directory that contains your FreeRTOSConfig.h + * header file, as that directory will already be in the compiler's include + * path. + * + * 2) Rename the copied file stdint.h. + * + */ + +typedef signed char int8_t; +typedef unsigned char uint8_t; +typedef short int16_t; +typedef unsigned short uint16_t; +typedef long int32_t; +typedef unsigned long uint32_t; + +#ifndef SIZE_MAX + #define SIZE_MAX ( ( size_t ) -1 ) +#endif + +#endif /* FREERTOS_STDINT */ diff --git a/include/stream_buffer.h b/include/stream_buffer.h new file mode 100644 index 000000000..b0093fc80 --- /dev/null +++ b/include/stream_buffer.h @@ -0,0 +1,1280 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * Stream buffers are used to send a continuous stream of data from one task or + * interrupt to another. Their implementation is light weight, making them + * particularly suited for interrupt to task and core to core communication + * scenarios. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must serialize calls to writing API functions + * (such as xStreamBufferSend()). Likewise, if there are to be multiple + * different readers then the application writer must serialize calls to reading + * API functions (such as xStreamBufferReceive()). One way to achieve such + * serialization in single core or SMP kernel is to place each API call inside a + * critical section and use a block time of 0. + * + */ + +#ifndef STREAM_BUFFER_H +#define STREAM_BUFFER_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include stream_buffer.h" +#endif + +/* *INDENT-OFF* */ +#if defined( __cplusplus ) + extern "C" { +#endif +/* *INDENT-ON* */ + +/** + * Type of stream buffer. For internal use only. + */ +#define sbTYPE_STREAM_BUFFER ( ( BaseType_t ) 0 ) +#define sbTYPE_MESSAGE_BUFFER ( ( BaseType_t ) 1 ) +#define sbTYPE_STREAM_BATCHING_BUFFER ( ( BaseType_t ) 2 ) + +/** + * Type by which stream buffers are referenced. For example, a call to + * xStreamBufferCreate() returns an StreamBufferHandle_t variable that can + * then be used as a parameter to xStreamBufferSend(), xStreamBufferReceive(), + * etc. + */ +struct StreamBufferDef_t; +typedef struct StreamBufferDef_t * StreamBufferHandle_t; + +/** + * Type used as a stream buffer's optional callback. + */ +typedef void (* StreamBufferCallbackFunction_t)( StreamBufferHandle_t xStreamBuffer, + BaseType_t xIsInsideISR, + BaseType_t * const pxHigherPriorityTaskWoken ); + +/** + * stream_buffer.h + * + * @code{c} + * StreamBufferHandle_t xStreamBufferCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes ); + * @endcode + * + * Creates a new stream buffer using dynamically allocated memory. See + * xStreamBufferCreateStatic() for a version that uses statically allocated + * memory (memory that is allocated at compile time). + * + * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in + * FreeRTOSConfig.h for xStreamBufferCreate() to be available. + * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for + * xStreamBufferCreate() to be available. + * + * @param xBufferSizeBytes The total number of bytes the stream buffer will be + * able to hold at any one time. + * + * @param xTriggerLevelBytes The number of bytes that must be in the stream + * buffer before a task that is blocked on the stream buffer to wait for data is + * moved out of the blocked state. For example, if a task is blocked on a read + * of an empty stream buffer that has a trigger level of 1 then the task will be + * unblocked when a single byte is written to the buffer or the task's block + * time expires. As another example, if a task is blocked on a read of an empty + * stream buffer that has a trigger level of 10 then the task will not be + * unblocked until the stream buffer contains at least 10 bytes or the task's + * block time expires. If a reading task's block time expires before the + * trigger level is reached then the task will still receive however many bytes + * are actually available. Setting a trigger level of 0 will result in a + * trigger level of 1 being used. It is not valid to specify a trigger level + * that is greater than the buffer size. + * + * @param pxSendCompletedCallback Callback invoked when number of bytes at least equal to + * trigger level is sent to the stream buffer. If the parameter is NULL, it will use the default + * implementation provided by sbSEND_COMPLETED macro. To enable the callback, + * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h. + * + * @param pxReceiveCompletedCallback Callback invoked when more than zero bytes are read from a + * stream buffer. If the parameter is NULL, it will use the default + * implementation provided by sbRECEIVE_COMPLETED macro. To enable the callback, + * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h. + * + * @return If NULL is returned, then the stream buffer cannot be created + * because there is insufficient heap memory available for FreeRTOS to allocate + * the stream buffer data structures and storage area. A non-NULL value being + * returned indicates that the stream buffer has been created successfully - + * the returned value should be stored as the handle to the created stream + * buffer. + * + * Example use: + * @code{c} + * + * void vAFunction( void ) + * { + * StreamBufferHandle_t xStreamBuffer; + * const size_t xStreamBufferSizeBytes = 100, xTriggerLevel = 10; + * + * // Create a stream buffer that can hold 100 bytes. The memory used to hold + * // both the stream buffer structure and the data in the stream buffer is + * // allocated dynamically. + * xStreamBuffer = xStreamBufferCreate( xStreamBufferSizeBytes, xTriggerLevel ); + * + * if( xStreamBuffer == NULL ) + * { + * // There was not enough heap memory space available to create the + * // stream buffer. + * } + * else + * { + * // The stream buffer was created successfully and can now be used. + * } + * } + * @endcode + * \defgroup xStreamBufferCreate xStreamBufferCreate + * \ingroup StreamBufferManagement + */ + +#define xStreamBufferCreate( xBufferSizeBytes, xTriggerLevelBytes ) \ + xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), sbTYPE_STREAM_BUFFER, NULL, NULL ) + +#if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) + #define xStreamBufferCreateWithCallback( xBufferSizeBytes, xTriggerLevelBytes, pxSendCompletedCallback, pxReceiveCompletedCallback ) \ + xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), sbTYPE_STREAM_BUFFER, ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) ) +#endif + +/** + * stream_buffer.h + * + * @code{c} + * StreamBufferHandle_t xStreamBufferCreateStatic( size_t xBufferSizeBytes, + * size_t xTriggerLevelBytes, + * uint8_t *pucStreamBufferStorageArea, + * StaticStreamBuffer_t *pxStaticStreamBuffer ); + * @endcode + * Creates a new stream buffer using statically allocated memory. See + * xStreamBufferCreate() for a version that uses dynamically allocated memory. + * + * configSUPPORT_STATIC_ALLOCATION must be set to 1 in FreeRTOSConfig.h for + * xStreamBufferCreateStatic() to be available. configUSE_STREAM_BUFFERS must be + * set to 1 in for FreeRTOSConfig.h for xStreamBufferCreateStatic() to be + * available. + * + * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the + * pucStreamBufferStorageArea parameter. + * + * @param xTriggerLevelBytes The number of bytes that must be in the stream + * buffer before a task that is blocked on the stream buffer to wait for data is + * moved out of the blocked state. For example, if a task is blocked on a read + * of an empty stream buffer that has a trigger level of 1 then the task will be + * unblocked when a single byte is written to the buffer or the task's block + * time expires. As another example, if a task is blocked on a read of an empty + * stream buffer that has a trigger level of 10 then the task will not be + * unblocked until the stream buffer contains at least 10 bytes or the task's + * block time expires. If a reading task's block time expires before the + * trigger level is reached then the task will still receive however many bytes + * are actually available. Setting a trigger level of 0 will result in a + * trigger level of 1 being used. It is not valid to specify a trigger level + * that is greater than the buffer size. + * + * @param pucStreamBufferStorageArea Must point to a uint8_t array that is at + * least xBufferSizeBytes big. This is the array to which streams are + * copied when they are written to the stream buffer. + * + * @param pxStaticStreamBuffer Must point to a variable of type + * StaticStreamBuffer_t, which will be used to hold the stream buffer's data + * structure. + * + * @param pxSendCompletedCallback Callback invoked when number of bytes at least equal to + * trigger level is sent to the stream buffer. If the parameter is NULL, it will use the default + * implementation provided by sbSEND_COMPLETED macro. To enable the callback, + * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h. + * + * @param pxReceiveCompletedCallback Callback invoked when more than zero bytes are read from a + * stream buffer. If the parameter is NULL, it will use the default + * implementation provided by sbRECEIVE_COMPLETED macro. To enable the callback, + * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h. + * + * @return If the stream buffer is created successfully then a handle to the + * created stream buffer is returned. If either pucStreamBufferStorageArea or + * pxStaticstreamBuffer are NULL then NULL is returned. + * + * Example use: + * @code{c} + * + * // Used to dimension the array used to hold the streams. The available space + * // will actually be one less than this, so 999. + #define STORAGE_SIZE_BYTES 1000 + * + * // Defines the memory that will actually hold the streams within the stream + * // buffer. + * static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ]; + * + * // The variable used to hold the stream buffer structure. + * StaticStreamBuffer_t xStreamBufferStruct; + * + * void MyFunction( void ) + * { + * StreamBufferHandle_t xStreamBuffer; + * const size_t xTriggerLevel = 1; + * + * xStreamBuffer = xStreamBufferCreateStatic( sizeof( ucStorageBuffer ), + * xTriggerLevel, + * ucStorageBuffer, + * &xStreamBufferStruct ); + * + * // As neither the pucStreamBufferStorageArea or pxStaticStreamBuffer + * // parameters were NULL, xStreamBuffer will not be NULL, and can be used to + * // reference the created stream buffer in other stream buffer API calls. + * + * // Other code that uses the stream buffer can go here. + * } + * + * @endcode + * \defgroup xStreamBufferCreateStatic xStreamBufferCreateStatic + * \ingroup StreamBufferManagement + */ + +#define xStreamBufferCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer ) \ + xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), sbTYPE_STREAM_BUFFER, ( pucStreamBufferStorageArea ), ( pxStaticStreamBuffer ), NULL, NULL ) + +#if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) + #define xStreamBufferCreateStaticWithCallback( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback ) \ + xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), sbTYPE_STREAM_BUFFER, ( pucStreamBufferStorageArea ), ( pxStaticStreamBuffer ), ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) ) +#endif + +/** + * stream_buffer.h + * + * @code{c} + * StreamBufferHandle_t xStreamBatchingBufferCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes ); + * @endcode + * + * Creates a new stream batching buffer using dynamically allocated memory. See + * xStreamBatchingBufferCreateStatic() for a version that uses statically + * allocated memory (memory that is allocated at compile time). + * + * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in + * FreeRTOSConfig.h for xStreamBatchingBufferCreate() to be available. + * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for + * xStreamBatchingBufferCreate() to be available. + * + * The difference between a stream buffer and a stream batching buffer is when + * a task performs read on a non-empty buffer: + * - The task reading from a non-empty stream buffer returns immediately + * regardless of the amount of data in the buffer. + * - The task reading from a non-empty steam batching buffer blocks until the + * amount of data in the buffer exceeds the trigger level or the block time + * expires. + * + * @param xBufferSizeBytes The total number of bytes the stream batching buffer + * will be able to hold at any one time. + * + * @param xTriggerLevelBytes The number of bytes that must be in the stream + * batching buffer to unblock a task calling xStreamBufferReceive before the + * block time expires. + * + * @param pxSendCompletedCallback Callback invoked when number of bytes at least + * equal to trigger level is sent to the stream batching buffer. If the + * parameter is NULL, it will use the default implementation provided by + * sbSEND_COMPLETED macro. To enable the callback, configUSE_SB_COMPLETED_CALLBACK + * must be set to 1 in FreeRTOSConfig.h. + * + * @param pxReceiveCompletedCallback Callback invoked when more than zero bytes + * are read from a stream batching buffer. If the parameter is NULL, it will use + * the default implementation provided by sbRECEIVE_COMPLETED macro. To enable + * the callback, configUSE_SB_COMPLETED_CALLBACK must be set to 1 in + * FreeRTOSConfig.h. + * + * @return If NULL is returned, then the stream batching buffer cannot be created + * because there is insufficient heap memory available for FreeRTOS to allocate + * the stream batching buffer data structures and storage area. A non-NULL value + * being returned indicates that the stream batching buffer has been created + * successfully - the returned value should be stored as the handle to the + * created stream batching buffer. + * + * Example use: + * @code{c} + * + * void vAFunction( void ) + * { + * StreamBufferHandle_t xStreamBatchingBuffer; + * const size_t xStreamBufferSizeBytes = 100, xTriggerLevel = 10; + * + * // Create a stream batching buffer that can hold 100 bytes. The memory used + * // to hold both the stream batching buffer structure and the data in the stream + * // batching buffer is allocated dynamically. + * xStreamBatchingBuffer = xStreamBatchingBufferCreate( xStreamBufferSizeBytes, xTriggerLevel ); + * + * if( xStreamBatchingBuffer == NULL ) + * { + * // There was not enough heap memory space available to create the + * // stream batching buffer. + * } + * else + * { + * // The stream batching buffer was created successfully and can now be used. + * } + * } + * @endcode + * \defgroup xStreamBatchingBufferCreate xStreamBatchingBufferCreate + * \ingroup StreamBatchingBufferManagement + */ + +#define xStreamBatchingBufferCreate( xBufferSizeBytes, xTriggerLevelBytes ) \ + xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), sbTYPE_STREAM_BATCHING_BUFFER, NULL, NULL ) + +#if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) + #define xStreamBatchingBufferCreateWithCallback( xBufferSizeBytes, xTriggerLevelBytes, pxSendCompletedCallback, pxReceiveCompletedCallback ) \ + xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), sbTYPE_STREAM_BATCHING_BUFFER, ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) ) +#endif + +/** + * stream_buffer.h + * + * @code{c} + * StreamBufferHandle_t xStreamBatchingBufferCreateStatic( size_t xBufferSizeBytes, + * size_t xTriggerLevelBytes, + * uint8_t *pucStreamBufferStorageArea, + * StaticStreamBuffer_t *pxStaticStreamBuffer ); + * @endcode + * Creates a new stream batching buffer using statically allocated memory. See + * xStreamBatchingBufferCreate() for a version that uses dynamically allocated + * memory. + * + * configSUPPORT_STATIC_ALLOCATION must be set to 1 in FreeRTOSConfig.h for + * xStreamBatchingBufferCreateStatic() to be available. configUSE_STREAM_BUFFERS + * must be set to 1 in for FreeRTOSConfig.h for xStreamBatchingBufferCreateStatic() + * to be available. + * + * The difference between a stream buffer and a stream batching buffer is when + * a task performs read on a non-empty buffer: + * - The task reading from a non-empty stream buffer returns immediately + * regardless of the amount of data in the buffer. + * - The task reading from a non-empty steam batching buffer blocks until the + * amount of data in the buffer exceeds the trigger level or the block time + * expires. + * + * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the + * pucStreamBufferStorageArea parameter. + * + * @param xTriggerLevelBytes The number of bytes that must be in the stream + * batching buffer to unblock a task calling xStreamBufferReceive before the + * block time expires. + * + * @param pucStreamBufferStorageArea Must point to a uint8_t array that is at + * least xBufferSizeBytes big. This is the array to which streams are + * copied when they are written to the stream batching buffer. + * + * @param pxStaticStreamBuffer Must point to a variable of type + * StaticStreamBuffer_t, which will be used to hold the stream batching buffer's + * data structure. + * + * @param pxSendCompletedCallback Callback invoked when number of bytes at least + * equal to trigger level is sent to the stream batching buffer. If the parameter + * is NULL, it will use the default implementation provided by sbSEND_COMPLETED + * macro. To enable the callback, configUSE_SB_COMPLETED_CALLBACK must be set to + * 1 in FreeRTOSConfig.h. + * + * @param pxReceiveCompletedCallback Callback invoked when more than zero bytes + * are read from a stream batching buffer. If the parameter is NULL, it will use + * the default implementation provided by sbRECEIVE_COMPLETED macro. To enable + * the callback, configUSE_SB_COMPLETED_CALLBACK must be set to 1 in + * FreeRTOSConfig.h. + * + * @return If the stream batching buffer is created successfully then a handle + * to the created stream batching buffer is returned. If either pucStreamBufferStorageArea + * or pxStaticstreamBuffer are NULL then NULL is returned. + * + * Example use: + * @code{c} + * + * // Used to dimension the array used to hold the streams. The available space + * // will actually be one less than this, so 999. + * #define STORAGE_SIZE_BYTES 1000 + * + * // Defines the memory that will actually hold the streams within the stream + * // batching buffer. + * static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ]; + * + * // The variable used to hold the stream batching buffer structure. + * StaticStreamBuffer_t xStreamBufferStruct; + * + * void MyFunction( void ) + * { + * StreamBufferHandle_t xStreamBatchingBuffer; + * const size_t xTriggerLevel = 1; + * + * xStreamBatchingBuffer = xStreamBatchingBufferCreateStatic( sizeof( ucStorageBuffer ), + * xTriggerLevel, + * ucStorageBuffer, + * &xStreamBufferStruct ); + * + * // As neither the pucStreamBufferStorageArea or pxStaticStreamBuffer + * // parameters were NULL, xStreamBatchingBuffer will not be NULL, and can be + * // used to reference the created stream batching buffer in other stream + * // buffer API calls. + * + * // Other code that uses the stream batching buffer can go here. + * } + * + * @endcode + * \defgroup xStreamBatchingBufferCreateStatic xStreamBatchingBufferCreateStatic + * \ingroup StreamBatchingBufferManagement + */ + +#define xStreamBatchingBufferCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer ) \ + xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), sbTYPE_STREAM_BATCHING_BUFFER, ( pucStreamBufferStorageArea ), ( pxStaticStreamBuffer ), NULL, NULL ) + +#if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) + #define xStreamBatchingBufferCreateStaticWithCallback( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback ) \ + xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), sbTYPE_STREAM_BATCHING_BUFFER, ( pucStreamBufferStorageArea ), ( pxStaticStreamBuffer ), ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) ) +#endif + +/** + * stream_buffer.h + * + * @code{c} + * BaseType_t xStreamBufferGetStaticBuffers( StreamBufferHandle_t xStreamBuffer, + * uint8_t ** ppucStreamBufferStorageArea, + * StaticStreamBuffer_t ** ppxStaticStreamBuffer ); + * @endcode + * + * Retrieve pointers to a statically created stream buffer's data structure + * buffer and storage area buffer. These are the same buffers that are supplied + * at the time of creation. + * + * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for + * xStreamBufferGetStaticBuffers() to be available. + * + * @param xStreamBuffer The stream buffer for which to retrieve the buffers. + * + * @param ppucStreamBufferStorageArea Used to return a pointer to the stream + * buffer's storage area buffer. + * + * @param ppxStaticStreamBuffer Used to return a pointer to the stream + * buffer's data structure buffer. + * + * @return pdTRUE if buffers were retrieved, pdFALSE otherwise. + * + * \defgroup xStreamBufferGetStaticBuffers xStreamBufferGetStaticBuffers + * \ingroup StreamBufferManagement + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + BaseType_t xStreamBufferGetStaticBuffers( StreamBufferHandle_t xStreamBuffer, + uint8_t ** ppucStreamBufferStorageArea, + StaticStreamBuffer_t ** ppxStaticStreamBuffer ) PRIVILEGED_FUNCTION; +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +/** + * stream_buffer.h + * + * @code{c} + * size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + * const void *pvTxData, + * size_t xDataLengthBytes, + * TickType_t xTicksToWait ); + * @endcode + * + * Sends bytes to a stream buffer. The bytes are copied into the stream buffer. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must serialize calls to writing API functions + * (such as xStreamBufferSend()). Likewise, if there are to be multiple + * different readers then the application writer must serialize calls to reading + * API functions (such as xStreamBufferReceive()). One way to achieve such + * serialization in single core or SMP kernel is to place each API call inside a + * critical section and use a block time of 0. + * + * Use xStreamBufferSend() to write to a stream buffer from a task. Use + * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt + * service routine (ISR). + * + * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for + * xStreamBufferSend() to be available. + * + * @param xStreamBuffer The handle of the stream buffer to which a stream is + * being sent. + * + * @param pvTxData A pointer to the buffer that holds the bytes to be copied + * into the stream buffer. + * + * @param xDataLengthBytes The maximum number of bytes to copy from pvTxData + * into the stream buffer. + * + * @param xTicksToWait The maximum amount of time the task should remain in the + * Blocked state to wait for enough space to become available in the stream + * buffer, should the stream buffer contain too little space to hold the + * another xDataLengthBytes bytes. The block time is specified in tick periods, + * so the absolute time it represents is dependent on the tick frequency. The + * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds + * into a time specified in ticks. Setting xTicksToWait to portMAX_DELAY will + * cause the task to wait indefinitely (without timing out), provided + * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h. If a task times out + * before it can write all xDataLengthBytes into the buffer it will still write + * as many bytes as possible. A task does not use any CPU time when it is in + * the blocked state. + * + * @return The number of bytes written to the stream buffer. If a task times + * out before it can write all xDataLengthBytes into the buffer it will still + * write as many bytes as possible. + * + * Example use: + * @code{c} + * void vAFunction( StreamBufferHandle_t xStreamBuffer ) + * { + * size_t xBytesSent; + * uint8_t ucArrayToSend[] = { 0, 1, 2, 3 }; + * char *pcStringToSend = "String to send"; + * const TickType_t x100ms = pdMS_TO_TICKS( 100 ); + * + * // Send an array to the stream buffer, blocking for a maximum of 100ms to + * // wait for enough space to be available in the stream buffer. + * xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms ); + * + * if( xBytesSent != sizeof( ucArrayToSend ) ) + * { + * // The call to xStreamBufferSend() times out before there was enough + * // space in the buffer for the data to be written, but it did + * // successfully write xBytesSent bytes. + * } + * + * // Send the string to the stream buffer. Return immediately if there is not + * // enough space in the buffer. + * xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 ); + * + * if( xBytesSent != strlen( pcStringToSend ) ) + * { + * // The entire string could not be added to the stream buffer because + * // there was not enough free space in the buffer, but xBytesSent bytes + * // were sent. Could try again to send the remaining bytes. + * } + * } + * @endcode + * \defgroup xStreamBufferSend xStreamBufferSend + * \ingroup StreamBufferManagement + */ +size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * @code{c} + * size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer, + * const void *pvTxData, + * size_t xDataLengthBytes, + * BaseType_t *pxHigherPriorityTaskWoken ); + * @endcode + * + * Interrupt safe version of the API function that sends a stream of bytes to + * the stream buffer. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must serialize calls to writing API functions + * (such as xStreamBufferSend()). Likewise, if there are to be multiple + * different readers then the application writer must serialize calls to reading + * API functions (such as xStreamBufferReceive()). One way to achieve such + * serialization in single core or SMP kernel is to place each API call inside a + * critical section and use a block time of 0. + * + * Use xStreamBufferSend() to write to a stream buffer from a task. Use + * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt + * service routine (ISR). + * + * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for + * xStreamBufferSendFromISR() to be available. + * + * @param xStreamBuffer The handle of the stream buffer to which a stream is + * being sent. + * + * @param pvTxData A pointer to the data that is to be copied into the stream + * buffer. + * + * @param xDataLengthBytes The maximum number of bytes to copy from pvTxData + * into the stream buffer. + * + * @param pxHigherPriorityTaskWoken It is possible that a stream buffer will + * have a task blocked on it waiting for data. Calling + * xStreamBufferSendFromISR() can make data available, and so cause a task that + * was waiting for data to leave the Blocked state. If calling + * xStreamBufferSendFromISR() causes a task to leave the Blocked state, and the + * unblocked task has a priority higher than the currently executing task (the + * task that was interrupted), then, internally, xStreamBufferSendFromISR() + * will set *pxHigherPriorityTaskWoken to pdTRUE. If + * xStreamBufferSendFromISR() sets this value to pdTRUE, then normally a + * context switch should be performed before the interrupt is exited. This will + * ensure that the interrupt returns directly to the highest priority Ready + * state task. *pxHigherPriorityTaskWoken should be set to pdFALSE before it + * is passed into the function. See the example code below for an example. + * + * @return The number of bytes actually written to the stream buffer, which will + * be less than xDataLengthBytes if the stream buffer didn't have enough free + * space for all the bytes to be written. + * + * Example use: + * @code{c} + * // A stream buffer that has already been created. + * StreamBufferHandle_t xStreamBuffer; + * + * void vAnInterruptServiceRoutine( void ) + * { + * size_t xBytesSent; + * char *pcStringToSend = "String to send"; + * BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE. + * + * // Attempt to send the string to the stream buffer. + * xBytesSent = xStreamBufferSendFromISR( xStreamBuffer, + * ( void * ) pcStringToSend, + * strlen( pcStringToSend ), + * &xHigherPriorityTaskWoken ); + * + * if( xBytesSent != strlen( pcStringToSend ) ) + * { + * // There was not enough free space in the stream buffer for the entire + * // string to be written, ut xBytesSent bytes were written. + * } + * + * // If xHigherPriorityTaskWoken was set to pdTRUE inside + * // xStreamBufferSendFromISR() then a task that has a priority above the + * // priority of the currently executing task was unblocked and a context + * // switch should be performed to ensure the ISR returns to the unblocked + * // task. In most FreeRTOS ports this is done by simply passing + * // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the + * // variables value, and perform the context switch if necessary. Check the + * // documentation for the port in use for port specific instructions. + * portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + * } + * @endcode + * \defgroup xStreamBufferSendFromISR xStreamBufferSendFromISR + * \ingroup StreamBufferManagement + */ +size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * @code{c} + * size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + * void *pvRxData, + * size_t xBufferLengthBytes, + * TickType_t xTicksToWait ); + * @endcode + * + * Receives bytes from a stream buffer. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must serialize calls to writing API functions + * (such as xStreamBufferSend()). Likewise, if there are to be multiple + * different readers then the application writer must serialize calls to reading + * API functions (such as xStreamBufferReceive()). One way to achieve such + * serialization in single core or SMP kernel is to place each API call inside a + * critical section and use a block time of 0. + * + * Use xStreamBufferReceive() to read from a stream buffer from a task. Use + * xStreamBufferReceiveFromISR() to read from a stream buffer from an + * interrupt service routine (ISR). + * + * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for + * xStreamBufferReceive() to be available. + * + * @param xStreamBuffer The handle of the stream buffer from which bytes are to + * be received. + * + * @param pvRxData A pointer to the buffer into which the received bytes will be + * copied. + * + * @param xBufferLengthBytes The length of the buffer pointed to by the + * pvRxData parameter. This sets the maximum number of bytes to receive in one + * call. xStreamBufferReceive will return as many bytes as possible up to a + * maximum set by xBufferLengthBytes. + * + * @param xTicksToWait The maximum amount of time the task should remain in the + * Blocked state to wait for data to become available if the stream buffer is + * empty. xStreamBufferReceive() will return immediately if xTicksToWait is + * zero. The block time is specified in tick periods, so the absolute time it + * represents is dependent on the tick frequency. The macro pdMS_TO_TICKS() can + * be used to convert a time specified in milliseconds into a time specified in + * ticks. Setting xTicksToWait to portMAX_DELAY will cause the task to wait + * indefinitely (without timing out), provided INCLUDE_vTaskSuspend is set to 1 + * in FreeRTOSConfig.h. A task does not use any CPU time when it is in the + * Blocked state. + * + * @return The number of bytes actually read from the stream buffer, which will + * be less than xBufferLengthBytes if the call to xStreamBufferReceive() timed + * out before xBufferLengthBytes were available. + * + * Example use: + * @code{c} + * void vAFunction( StreamBuffer_t xStreamBuffer ) + * { + * uint8_t ucRxData[ 20 ]; + * size_t xReceivedBytes; + * const TickType_t xBlockTime = pdMS_TO_TICKS( 20 ); + * + * // Receive up to another sizeof( ucRxData ) bytes from the stream buffer. + * // Wait in the Blocked state (so not using any CPU processing time) for a + * // maximum of 100ms for the full sizeof( ucRxData ) number of bytes to be + * // available. + * xReceivedBytes = xStreamBufferReceive( xStreamBuffer, + * ( void * ) ucRxData, + * sizeof( ucRxData ), + * xBlockTime ); + * + * if( xReceivedBytes > 0 ) + * { + * // A ucRxData contains another xReceivedBytes bytes of data, which can + * // be processed here.... + * } + * } + * @endcode + * \defgroup xStreamBufferReceive xStreamBufferReceive + * \ingroup StreamBufferManagement + */ +size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * @code{c} + * size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer, + * void *pvRxData, + * size_t xBufferLengthBytes, + * BaseType_t *pxHigherPriorityTaskWoken ); + * @endcode + * + * An interrupt safe version of the API function that receives bytes from a + * stream buffer. + * + * Use xStreamBufferReceive() to read bytes from a stream buffer from a task. + * Use xStreamBufferReceiveFromISR() to read bytes from a stream buffer from an + * interrupt service routine (ISR). + * + * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for + * xStreamBufferReceiveFromISR() to be available. + * + * @param xStreamBuffer The handle of the stream buffer from which a stream + * is being received. + * + * @param pvRxData A pointer to the buffer into which the received bytes are + * copied. + * + * @param xBufferLengthBytes The length of the buffer pointed to by the + * pvRxData parameter. This sets the maximum number of bytes to receive in one + * call. xStreamBufferReceive will return as many bytes as possible up to a + * maximum set by xBufferLengthBytes. + * + * @param pxHigherPriorityTaskWoken It is possible that a stream buffer will + * have a task blocked on it waiting for space to become available. Calling + * xStreamBufferReceiveFromISR() can make space available, and so cause a task + * that is waiting for space to leave the Blocked state. If calling + * xStreamBufferReceiveFromISR() causes a task to leave the Blocked state, and + * the unblocked task has a priority higher than the currently executing task + * (the task that was interrupted), then, internally, + * xStreamBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE. + * If xStreamBufferReceiveFromISR() sets this value to pdTRUE, then normally a + * context switch should be performed before the interrupt is exited. That will + * ensure the interrupt returns directly to the highest priority Ready state + * task. *pxHigherPriorityTaskWoken should be set to pdFALSE before it is + * passed into the function. See the code example below for an example. + * + * @return The number of bytes read from the stream buffer, if any. + * + * Example use: + * @code{c} + * // A stream buffer that has already been created. + * StreamBuffer_t xStreamBuffer; + * + * void vAnInterruptServiceRoutine( void ) + * { + * uint8_t ucRxData[ 20 ]; + * size_t xReceivedBytes; + * BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE. + * + * // Receive the next stream from the stream buffer. + * xReceivedBytes = xStreamBufferReceiveFromISR( xStreamBuffer, + * ( void * ) ucRxData, + * sizeof( ucRxData ), + * &xHigherPriorityTaskWoken ); + * + * if( xReceivedBytes > 0 ) + * { + * // ucRxData contains xReceivedBytes read from the stream buffer. + * // Process the stream here.... + * } + * + * // If xHigherPriorityTaskWoken was set to pdTRUE inside + * // xStreamBufferReceiveFromISR() then a task that has a priority above the + * // priority of the currently executing task was unblocked and a context + * // switch should be performed to ensure the ISR returns to the unblocked + * // task. In most FreeRTOS ports this is done by simply passing + * // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the + * // variables value, and perform the context switch if necessary. Check the + * // documentation for the port in use for port specific instructions. + * portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + * } + * @endcode + * \defgroup xStreamBufferReceiveFromISR xStreamBufferReceiveFromISR + * \ingroup StreamBufferManagement + */ +size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * @code{c} + * void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ); + * @endcode + * + * Deletes a stream buffer that was previously created using a call to + * xStreamBufferCreate() or xStreamBufferCreateStatic(). If the stream + * buffer was created using dynamic memory (that is, by xStreamBufferCreate()), + * then the allocated memory is freed. + * + * A stream buffer handle must not be used after the stream buffer has been + * deleted. + * + * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for + * vStreamBufferDelete() to be available. + * + * @param xStreamBuffer The handle of the stream buffer to be deleted. + * + * \defgroup vStreamBufferDelete vStreamBufferDelete + * \ingroup StreamBufferManagement + */ +void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * @code{c} + * BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ); + * @endcode + * + * Queries a stream buffer to see if it is full. A stream buffer is full if it + * does not have any free space, and therefore cannot accept any more data. + * + * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for + * xStreamBufferIsFull() to be available. + * + * @param xStreamBuffer The handle of the stream buffer being queried. + * + * @return If the stream buffer is full then pdTRUE is returned. Otherwise + * pdFALSE is returned. + * + * \defgroup xStreamBufferIsFull xStreamBufferIsFull + * \ingroup StreamBufferManagement + */ +BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * @code{c} + * BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ); + * @endcode + * + * Queries a stream buffer to see if it is empty. A stream buffer is empty if + * it does not contain any data. + * + * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for + * xStreamBufferIsEmpty() to be available. + * + * @param xStreamBuffer The handle of the stream buffer being queried. + * + * @return If the stream buffer is empty then pdTRUE is returned. Otherwise + * pdFALSE is returned. + * + * \defgroup xStreamBufferIsEmpty xStreamBufferIsEmpty + * \ingroup StreamBufferManagement + */ +BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * @code{c} + * BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ); + * @endcode + * + * Resets a stream buffer to its initial, empty, state. Any data that was in + * the stream buffer is discarded. A stream buffer can only be reset if there + * are no tasks blocked waiting to either send to or receive from the stream + * buffer. + * + * Use xStreamBufferReset() to reset a stream buffer from a task. + * Use xStreamBufferResetFromISR() to reset a stream buffer from an + * interrupt service routine (ISR). + * + * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for + * xStreamBufferReset() to be available. + * + * @param xStreamBuffer The handle of the stream buffer being reset. + * + * @return If the stream buffer is reset then pdPASS is returned. If there was + * a task blocked waiting to send to or read from the stream buffer then the + * stream buffer is not reset and pdFAIL is returned. + * + * \defgroup xStreamBufferReset xStreamBufferReset + * \ingroup StreamBufferManagement + */ +BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * @code{c} + * BaseType_t xStreamBufferResetFromISR( StreamBufferHandle_t xStreamBuffer ); + * @endcode + * + * An interrupt safe version of the API function that resets the stream buffer. + * + * Resets a stream buffer to its initial, empty, state. Any data that was in + * the stream buffer is discarded. A stream buffer can only be reset if there + * are no tasks blocked waiting to either send to or receive from the stream + * buffer. + * + * Use xStreamBufferReset() to reset a stream buffer from a task. + * Use xStreamBufferResetFromISR() to reset a stream buffer from an + * interrupt service routine (ISR). + * + * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for + * xStreamBufferResetFromISR() to be available. + * + * @param xStreamBuffer The handle of the stream buffer being reset. + * + * @return If the stream buffer is reset then pdPASS is returned. If there was + * a task blocked waiting to send to or read from the stream buffer then the + * stream buffer is not reset and pdFAIL is returned. + * + * \defgroup xStreamBufferResetFromISR xStreamBufferResetFromISR + * \ingroup StreamBufferManagement + */ +BaseType_t xStreamBufferResetFromISR( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * @code{c} + * size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ); + * @endcode + * + * Queries a stream buffer to see how much free space it contains, which is + * equal to the amount of data that can be sent to the stream buffer before it + * is full. + * + * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for + * xStreamBufferSpacesAvailable() to be available. + * + * @param xStreamBuffer The handle of the stream buffer being queried. + * + * @return The number of bytes that can be written to the stream buffer before + * the stream buffer would be full. + * + * \defgroup xStreamBufferSpacesAvailable xStreamBufferSpacesAvailable + * \ingroup StreamBufferManagement + */ +size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * @code{c} + * size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ); + * @endcode + * + * Queries a stream buffer to see how much data it contains, which is equal to + * the number of bytes that can be read from the stream buffer before the stream + * buffer would be empty. + * + * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for + * xStreamBufferBytesAvailable() to be available. + * + * @param xStreamBuffer The handle of the stream buffer being queried. + * + * @return The number of bytes that can be read from the stream buffer before + * the stream buffer would be empty. + * + * \defgroup xStreamBufferBytesAvailable xStreamBufferBytesAvailable + * \ingroup StreamBufferManagement + */ +size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * @code{c} + * BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ); + * @endcode + * + * A stream buffer's trigger level is the number of bytes that must be in the + * stream buffer before a task that is blocked on the stream buffer to + * wait for data is moved out of the blocked state. For example, if a task is + * blocked on a read of an empty stream buffer that has a trigger level of 1 + * then the task will be unblocked when a single byte is written to the buffer + * or the task's block time expires. As another example, if a task is blocked + * on a read of an empty stream buffer that has a trigger level of 10 then the + * task will not be unblocked until the stream buffer contains at least 10 bytes + * or the task's block time expires. If a reading task's block time expires + * before the trigger level is reached then the task will still receive however + * many bytes are actually available. Setting a trigger level of 0 will result + * in a trigger level of 1 being used. It is not valid to specify a trigger + * level that is greater than the buffer size. + * + * A trigger level is set when the stream buffer is created, and can be modified + * using xStreamBufferSetTriggerLevel(). + * + * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for + * xStreamBufferSetTriggerLevel() to be available. + * + * @param xStreamBuffer The handle of the stream buffer being updated. + * + * @param xTriggerLevel The new trigger level for the stream buffer. + * + * @return If xTriggerLevel was less than or equal to the stream buffer's length + * then the trigger level will be updated and pdTRUE is returned. Otherwise + * pdFALSE is returned. + * + * \defgroup xStreamBufferSetTriggerLevel xStreamBufferSetTriggerLevel + * \ingroup StreamBufferManagement + */ +BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * @code{c} + * BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken ); + * @endcode + * + * For advanced users only. + * + * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when + * data is sent to a message buffer or stream buffer. If there was a task that + * was blocked on the message or stream buffer waiting for data to arrive then + * the sbSEND_COMPLETED() macro sends a notification to the task to remove it + * from the Blocked state. xStreamBufferSendCompletedFromISR() does the same + * thing. It is provided to enable application writers to implement their own + * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME. + * + * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for + * additional information. + * + * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for + * xStreamBufferSendCompletedFromISR() to be available. + * + * @param xStreamBuffer The handle of the stream buffer to which data was + * written. + * + * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be + * initialised to pdFALSE before it is passed into + * xStreamBufferSendCompletedFromISR(). If calling + * xStreamBufferSendCompletedFromISR() removes a task from the Blocked state, + * and the task has a priority above the priority of the currently running task, + * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a + * context switch should be performed before exiting the ISR. + * + * @return If a task was removed from the Blocked state then pdTRUE is returned. + * Otherwise pdFALSE is returned. + * + * \defgroup xStreamBufferSendCompletedFromISR xStreamBufferSendCompletedFromISR + * \ingroup StreamBufferManagement + */ +BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, + BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * @code{c} + * BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken ); + * @endcode + * + * For advanced users only. + * + * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when + * data is read out of a message buffer or stream buffer. If there was a task + * that was blocked on the message or stream buffer waiting for data to arrive + * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to + * remove it from the Blocked state. xStreamBufferReceiveCompletedFromISR() + * does the same thing. It is provided to enable application writers to + * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT + * ANY OTHER TIME. + * + * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for + * additional information. + * + * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for + * xStreamBufferReceiveCompletedFromISR() to be available. + * + * @param xStreamBuffer The handle of the stream buffer from which data was + * read. + * + * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be + * initialised to pdFALSE before it is passed into + * xStreamBufferReceiveCompletedFromISR(). If calling + * xStreamBufferReceiveCompletedFromISR() removes a task from the Blocked state, + * and the task has a priority above the priority of the currently running task, + * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a + * context switch should be performed before exiting the ISR. + * + * @return If a task was removed from the Blocked state then pdTRUE is returned. + * Otherwise pdFALSE is returned. + * + * \defgroup xStreamBufferReceiveCompletedFromISR xStreamBufferReceiveCompletedFromISR + * \ingroup StreamBufferManagement + */ +BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, + BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * @code{c} + * UBaseType_t uxStreamBufferGetStreamBufferNotificationIndex( StreamBufferHandle_t xStreamBuffer ); + * @endcode + * + * Get the task notification index used for the supplied stream buffer which can + * be set using vStreamBufferSetStreamBufferNotificationIndex. If the task + * notification index for the stream buffer is not changed using + * vStreamBufferSetStreamBufferNotificationIndex, this function returns the + * default value (tskDEFAULT_INDEX_TO_NOTIFY). + * + * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for + * uxStreamBufferGetStreamBufferNotificationIndex() to be available. + * + * @param xStreamBuffer The handle of the stream buffer for which the task + * notification index is retrieved. + * + * @return The task notification index for the stream buffer. + * + * \defgroup uxStreamBufferGetStreamBufferNotificationIndex uxStreamBufferGetStreamBufferNotificationIndex + * \ingroup StreamBufferManagement + */ +UBaseType_t uxStreamBufferGetStreamBufferNotificationIndex( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * @code{c} + * void vStreamBufferSetStreamBufferNotificationIndex ( StreamBuffer_t xStreamBuffer, UBaseType_t uxNotificationIndex ); + * @endcode + * + * Set the task notification index used for the supplied stream buffer. + * Successive calls to stream buffer APIs (like xStreamBufferSend or + * xStreamBufferReceive) for this stream buffer will use this new index for + * their task notifications. + * + * If this function is not called, the default index (tskDEFAULT_INDEX_TO_NOTIFY) + * is used for task notifications. It is recommended to call this function + * before attempting to send or receive data from the stream buffer to avoid + * inconsistencies. + * + * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for + * vStreamBufferSetStreamBufferNotificationIndex() to be available. + * + * @param xStreamBuffer The handle of the stream buffer for which the task + * notification index is set. + * + * @param uxNotificationIndex The task notification index to set. + * + * \defgroup vStreamBufferSetStreamBufferNotificationIndex vStreamBufferSetStreamBufferNotificationIndex + * \ingroup StreamBufferManagement + */ +void vStreamBufferSetStreamBufferNotificationIndex( StreamBufferHandle_t xStreamBuffer, + UBaseType_t uxNotificationIndex ) PRIVILEGED_FUNCTION; + +/* Functions below here are not part of the public API. */ +StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + BaseType_t xStreamBufferType, + StreamBufferCallbackFunction_t pxSendCompletedCallback, + StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION; + +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + BaseType_t xStreamBufferType, + uint8_t * const pucStreamBufferStorageArea, + StaticStreamBuffer_t * const pxStaticStreamBuffer, + StreamBufferCallbackFunction_t pxSendCompletedCallback, + StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION; +#endif + +size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + +#if ( configUSE_TRACE_FACILITY == 1 ) + void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, + UBaseType_t uxStreamBufferNumber ) PRIVILEGED_FUNCTION; + UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; +#endif + +/* *INDENT-OFF* */ +#if defined( __cplusplus ) + } +#endif +/* *INDENT-ON* */ + +#endif /* !defined( STREAM_BUFFER_H ) */ diff --git a/include/task.h b/include/task.h new file mode 100644 index 000000000..2a19fa73f --- /dev/null +++ b/include/task.h @@ -0,0 +1,3800 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2025 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef INC_TASK_H +#define INC_TASK_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include task.h" +#endif + +#include "list.h" + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- +* MACROS AND DEFINITIONS +*----------------------------------------------------------*/ + +/* + * If tskKERNEL_VERSION_NUMBER ends with + it represents the version in development + * after the numbered release. + * + * The tskKERNEL_VERSION_MAJOR, tskKERNEL_VERSION_MINOR, tskKERNEL_VERSION_BUILD + * values will reflect the last released version number. + */ +#define tskKERNEL_VERSION_NUMBER "V11.1.0+" +#define tskKERNEL_VERSION_MAJOR 11 +#define tskKERNEL_VERSION_MINOR 1 +#define tskKERNEL_VERSION_BUILD 0 + +/* MPU region parameters passed in ulParameters + * of MemoryRegion_t struct. */ +#define tskMPU_REGION_READ_ONLY ( 1U << 0U ) +#define tskMPU_REGION_READ_WRITE ( 1U << 1U ) +#define tskMPU_REGION_EXECUTE_NEVER ( 1U << 2U ) +#define tskMPU_REGION_NORMAL_MEMORY ( 1U << 3U ) +#define tskMPU_REGION_DEVICE_MEMORY ( 1U << 4U ) +#if defined( portARMV8M_MINOR_VERSION ) && ( portARMV8M_MINOR_VERSION >= 1 ) + #define tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ( 1U << 5U ) +#endif /* portARMV8M_MINOR_VERSION >= 1 */ +#define tskMPU_REGION_NON_SHAREABLE ( 1U << 6U ) +#define tskMPU_REGION_OUTER_SHAREABLE ( 1U << 7U ) +#define tskMPU_REGION_INNER_SHAREABLE ( 1U << 8U ) + +/* MPU region permissions stored in MPU settings to + * authorize access requests. */ +#define tskMPU_READ_PERMISSION ( 1U << 0U ) +#define tskMPU_WRITE_PERMISSION ( 1U << 1U ) + +/* The direct to task notification feature used to have only a single notification + * per task. Now there is an array of notifications per task that is dimensioned by + * configTASK_NOTIFICATION_ARRAY_ENTRIES. For backward compatibility, any use of the + * original direct to task notification defaults to using the first index in the + * array. */ +#define tskDEFAULT_INDEX_TO_NOTIFY ( 0 ) + +/** + * task. h + * + * Type by which tasks are referenced. For example, a call to xTaskCreate + * returns (via a pointer parameter) an TaskHandle_t variable that can then + * be used as a parameter to vTaskDelete to delete the task. + * + * \defgroup TaskHandle_t TaskHandle_t + * \ingroup Tasks + */ +struct tskTaskControlBlock; /* The old naming convention is used to prevent breaking kernel aware debuggers. */ +typedef struct tskTaskControlBlock * TaskHandle_t; +typedef const struct tskTaskControlBlock * ConstTaskHandle_t; + +/* + * Defines the prototype to which the application task hook function must + * conform. + */ +typedef BaseType_t (* TaskHookFunction_t)( void * arg ); + +/* Task states returned by eTaskGetState. */ +typedef enum +{ + eRunning = 0, /* A task is querying the state of itself, so must be running. */ + eReady, /* The task being queried is in a ready or pending ready list. */ + eBlocked, /* The task being queried is in the Blocked state. */ + eSuspended, /* The task being queried is in the Suspended state, or is in the Blocked state with an infinite time out. */ + eDeleted, /* The task being queried has been deleted, but its TCB has not yet been freed. */ + eInvalid /* Used as an 'invalid state' value. */ +} eTaskState; + +/* Actions that can be performed when vTaskNotify() is called. */ +typedef enum +{ + eNoAction = 0, /* Notify the task without updating its notify value. */ + eSetBits, /* Set bits in the task's notification value. */ + eIncrement, /* Increment the task's notification value. */ + eSetValueWithOverwrite, /* Set the task's notification value to a specific value even if the previous value has not yet been read by the task. */ + eSetValueWithoutOverwrite /* Set the task's notification value if the previous value has been read by the task. */ +} eNotifyAction; + +/* + * Used internally only. + */ +typedef struct xTIME_OUT +{ + BaseType_t xOverflowCount; + TickType_t xTimeOnEntering; +} TimeOut_t; + +/* + * Defines the memory ranges allocated to the task when an MPU is used. + */ +typedef struct xMEMORY_REGION +{ + void * pvBaseAddress; + uint32_t ulLengthInBytes; + uint32_t ulParameters; +} MemoryRegion_t; + +/* + * Parameters required to create an MPU protected task. + */ +typedef struct xTASK_PARAMETERS +{ + TaskFunction_t pvTaskCode; + const char * pcName; + configSTACK_DEPTH_TYPE usStackDepth; + void * pvParameters; + UBaseType_t uxPriority; + StackType_t * puxStackBuffer; + MemoryRegion_t xRegions[ portNUM_CONFIGURABLE_REGIONS ]; + #if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + StaticTask_t * const pxTaskBuffer; + #endif +} TaskParameters_t; + +/* Used with the uxTaskGetSystemState() function to return the state of each task + * in the system. */ +typedef struct xTASK_STATUS +{ + TaskHandle_t xHandle; /* The handle of the task to which the rest of the information in the structure relates. */ + const char * pcTaskName; /* A pointer to the task's name. This value will be invalid if the task was deleted since the structure was populated! */ + UBaseType_t xTaskNumber; /* A number unique to the task. Note that this is not the task number that may be modified using vTaskSetTaskNumber() and uxTaskGetTaskNumber(), but a separate TCB-specific and unique identifier automatically assigned on task generation. */ + eTaskState eCurrentState; /* The state in which the task existed when the structure was populated. */ + UBaseType_t uxCurrentPriority; /* The priority at which the task was running (may be inherited) when the structure was populated. */ + UBaseType_t uxBasePriority; /* The priority to which the task will return if the task's current priority has been inherited to avoid unbounded priority inversion when obtaining a mutex. Only valid if configUSE_MUTEXES is defined as 1 in FreeRTOSConfig.h. */ + configRUN_TIME_COUNTER_TYPE ulRunTimeCounter; /* The total run time allocated to the task so far, as defined by the run time stats clock. See https://www.FreeRTOS.org/rtos-run-time-stats.html. Only valid when configGENERATE_RUN_TIME_STATS is defined as 1 in FreeRTOSConfig.h. */ + StackType_t * pxStackBase; /* Points to the lowest address of the task's stack area. */ + #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) ) + StackType_t * pxTopOfStack; /* Points to the top address of the task's stack area. */ + StackType_t * pxEndOfStack; /* Points to the end address of the task's stack area. */ + #endif + configSTACK_DEPTH_TYPE usStackHighWaterMark; /* The minimum amount of stack space that has remained for the task since the task was created. The closer this value is to zero the closer the task has come to overflowing its stack. */ + #if ( ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) ) + UBaseType_t uxCoreAffinityMask; /* The core affinity mask for the task */ + #endif +} TaskStatus_t; + +/* Possible return values for eTaskConfirmSleepModeStatus(). */ +typedef enum +{ + eAbortSleep = 0, /* A task has been made ready or a context switch pended since portSUPPRESS_TICKS_AND_SLEEP() was called - abort entering a sleep mode. */ + eStandardSleep /* Enter a sleep mode that will not last any longer than the expected idle time. */ + #if ( INCLUDE_vTaskSuspend == 1 ) + , + eNoTasksWaitingTimeout /* No tasks are waiting for a timeout so it is safe to enter a sleep mode that can only be exited by an external interrupt. */ + #endif /* INCLUDE_vTaskSuspend */ +} eSleepModeStatus; + +/** + * Defines the priority used by the idle task. This must not be modified. + * + * \ingroup TaskUtils + */ +#define tskIDLE_PRIORITY ( ( UBaseType_t ) 0U ) + +/** + * Defines affinity to all available cores. + * + * \ingroup TaskUtils + */ +#define tskNO_AFFINITY ( ( UBaseType_t ) -1 ) + +/** + * task. h + * + * Macro for forcing a context switch. + * + * \defgroup taskYIELD taskYIELD + * \ingroup SchedulerControl + */ +#define taskYIELD() portYIELD() + +/** + * task. h + * + * Macro to mark the start of a critical code region. Preemptive context + * switches cannot occur when in a critical region. + * + * NOTE: This may alter the stack (depending on the portable implementation) + * so must be used with care! + * + * \defgroup taskENTER_CRITICAL taskENTER_CRITICAL + * \ingroup SchedulerControl + */ +#define taskENTER_CRITICAL() portENTER_CRITICAL() +#if ( configNUMBER_OF_CORES == 1 ) + #define taskENTER_CRITICAL_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR() +#else + #define taskENTER_CRITICAL_FROM_ISR() portENTER_CRITICAL_FROM_ISR() +#endif + +/** + * task. h + * + * Macro to mark the end of a critical code region. Preemptive context + * switches cannot occur when in a critical region. + * + * NOTE: This may alter the stack (depending on the portable implementation) + * so must be used with care! + * + * \defgroup taskEXIT_CRITICAL taskEXIT_CRITICAL + * \ingroup SchedulerControl + */ +#define taskEXIT_CRITICAL() portEXIT_CRITICAL() +#if ( configNUMBER_OF_CORES == 1 ) + #define taskEXIT_CRITICAL_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) +#else + #define taskEXIT_CRITICAL_FROM_ISR( x ) portEXIT_CRITICAL_FROM_ISR( x ) +#endif + +/** + * task. h + * + * Macro to disable all maskable interrupts. + * + * \defgroup taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS + * \ingroup SchedulerControl + */ +#define taskDISABLE_INTERRUPTS() portDISABLE_INTERRUPTS() + +/** + * task. h + * + * Macro to enable microcontroller interrupts. + * + * \defgroup taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS + * \ingroup SchedulerControl + */ +#define taskENABLE_INTERRUPTS() portENABLE_INTERRUPTS() + +/* Definitions returned by xTaskGetSchedulerState(). taskSCHEDULER_SUSPENDED is + * 0 to generate more optimal code when configASSERT() is defined as the constant + * is used in assert() statements. */ +#define taskSCHEDULER_SUSPENDED ( ( BaseType_t ) 0 ) +#define taskSCHEDULER_NOT_STARTED ( ( BaseType_t ) 1 ) +#define taskSCHEDULER_RUNNING ( ( BaseType_t ) 2 ) + +/* Checks if core ID is valid. */ +#define taskVALID_CORE_ID( xCoreID ) ( ( ( ( ( BaseType_t ) 0 <= ( xCoreID ) ) && ( ( xCoreID ) < ( BaseType_t ) configNUMBER_OF_CORES ) ) ) ? ( pdTRUE ) : ( pdFALSE ) ) + +/*----------------------------------------------------------- +* TASK CREATION API +*----------------------------------------------------------*/ + +/** + * task. h + * @code{c} + * BaseType_t xTaskCreate( + * TaskFunction_t pxTaskCode, + * const char * const pcName, + * const configSTACK_DEPTH_TYPE uxStackDepth, + * void *pvParameters, + * UBaseType_t uxPriority, + * TaskHandle_t *pxCreatedTask + * ); + * @endcode + * + * Create a new task and add it to the list of tasks that are ready to run. + * + * Internally, within the FreeRTOS implementation, tasks use two blocks of + * memory. The first block is used to hold the task's data structures. The + * second block is used by the task as its stack. If a task is created using + * xTaskCreate() then both blocks of memory are automatically dynamically + * allocated inside the xTaskCreate() function. (see + * https://www.FreeRTOS.org/a00111.html). If a task is created using + * xTaskCreateStatic() then the application writer must provide the required + * memory. xTaskCreateStatic() therefore allows a task to be created without + * using any dynamic memory allocation. + * + * See xTaskCreateStatic() for a version that does not use any dynamic memory + * allocation. + * + * xTaskCreate() can only be used to create a task that has unrestricted + * access to the entire microcontroller memory map. Systems that include MPU + * support can alternatively create an MPU constrained task using + * xTaskCreateRestricted(). + * + * @param pxTaskCode Pointer to the task entry function. Tasks + * must be implemented to never return (i.e. continuous loop). + * + * @param pcName A descriptive name for the task. This is mainly used to + * facilitate debugging. Max length defined by configMAX_TASK_NAME_LEN - default + * is 16. + * + * @param uxStackDepth The size of the task stack specified as the number of + * variables the stack can hold - not the number of bytes. For example, if + * the stack is 16 bits wide and uxStackDepth is defined as 100, 200 bytes + * will be allocated for stack storage. + * + * @param pvParameters Pointer that will be used as the parameter for the task + * being created. + * + * @param uxPriority The priority at which the task should run. Systems that + * include MPU support can optionally create tasks in a privileged (system) + * mode by setting bit portPRIVILEGE_BIT of the priority parameter. For + * example, to create a privileged task at priority 2 the uxPriority parameter + * should be set to ( 2 | portPRIVILEGE_BIT ). + * + * @param pxCreatedTask Used to pass back a handle by which the created task + * can be referenced. + * + * @return pdPASS if the task was successfully created and added to a ready + * list, otherwise an error code defined in the file projdefs.h + * + * Example usage: + * @code{c} + * // Task to be created. + * void vTaskCode( void * pvParameters ) + * { + * for( ;; ) + * { + * // Task code goes here. + * } + * } + * + * // Function that creates a task. + * void vOtherFunction( void ) + * { + * static uint8_t ucParameterToPass; + * TaskHandle_t xHandle = NULL; + * + * // Create the task, storing the handle. Note that the passed parameter ucParameterToPass + * // must exist for the lifetime of the task, so in this case is declared static. If it was just an + * // an automatic stack variable it might no longer exist, or at least have been corrupted, by the time + * // the new task attempts to access it. + * xTaskCreate( vTaskCode, "NAME", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle ); + * configASSERT( xHandle ); + * + * // Use the handle to delete the task. + * if( xHandle != NULL ) + * { + * vTaskDelete( xHandle ); + * } + * } + * @endcode + * \defgroup xTaskCreate xTaskCreate + * \ingroup Tasks + */ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + BaseType_t xTaskCreate( TaskFunction_t pxTaskCode, + const char * const pcName, + const configSTACK_DEPTH_TYPE uxStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION; +#endif + +#if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) + BaseType_t xTaskCreateAffinitySet( TaskFunction_t pxTaskCode, + const char * const pcName, + const configSTACK_DEPTH_TYPE uxStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + UBaseType_t uxCoreAffinityMask, + TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION; +#endif + +/** + * task. h + * @code{c} + * TaskHandle_t xTaskCreateStatic( TaskFunction_t pxTaskCode, + * const char * const pcName, + * const configSTACK_DEPTH_TYPE uxStackDepth, + * void *pvParameters, + * UBaseType_t uxPriority, + * StackType_t *puxStackBuffer, + * StaticTask_t *pxTaskBuffer ); + * @endcode + * + * Create a new task and add it to the list of tasks that are ready to run. + * + * Internally, within the FreeRTOS implementation, tasks use two blocks of + * memory. The first block is used to hold the task's data structures. The + * second block is used by the task as its stack. If a task is created using + * xTaskCreate() then both blocks of memory are automatically dynamically + * allocated inside the xTaskCreate() function. (see + * https://www.FreeRTOS.org/a00111.html). If a task is created using + * xTaskCreateStatic() then the application writer must provide the required + * memory. xTaskCreateStatic() therefore allows a task to be created without + * using any dynamic memory allocation. + * + * @param pxTaskCode Pointer to the task entry function. Tasks + * must be implemented to never return (i.e. continuous loop). + * + * @param pcName A descriptive name for the task. This is mainly used to + * facilitate debugging. The maximum length of the string is defined by + * configMAX_TASK_NAME_LEN in FreeRTOSConfig.h. + * + * @param uxStackDepth The size of the task stack specified as the number of + * variables the stack can hold - not the number of bytes. For example, if + * the stack is 32-bits wide and uxStackDepth is defined as 100 then 400 bytes + * will be allocated for stack storage. + * + * @param pvParameters Pointer that will be used as the parameter for the task + * being created. + * + * @param uxPriority The priority at which the task will run. + * + * @param puxStackBuffer Must point to a StackType_t array that has at least + * uxStackDepth indexes - the array will then be used as the task's stack, + * removing the need for the stack to be allocated dynamically. + * + * @param pxTaskBuffer Must point to a variable of type StaticTask_t, which will + * then be used to hold the task's data structures, removing the need for the + * memory to be allocated dynamically. + * + * @return If neither puxStackBuffer nor pxTaskBuffer are NULL, then the task + * will be created and a handle to the created task is returned. If either + * puxStackBuffer or pxTaskBuffer are NULL then the task will not be created and + * NULL is returned. + * + * Example usage: + * @code{c} + * + * // Dimensions of the buffer that the task being created will use as its stack. + * // NOTE: This is the number of words the stack will hold, not the number of + * // bytes. For example, if each stack item is 32-bits, and this is set to 100, + * // then 400 bytes (100 * 32-bits) will be allocated. + #define STACK_SIZE 200 + * + * // Structure that will hold the TCB of the task being created. + * StaticTask_t xTaskBuffer; + * + * // Buffer that the task being created will use as its stack. Note this is + * // an array of StackType_t variables. The size of StackType_t is dependent on + * // the RTOS port. + * StackType_t xStack[ STACK_SIZE ]; + * + * // Function that implements the task being created. + * void vTaskCode( void * pvParameters ) + * { + * // The parameter value is expected to be 1 as 1 is passed in the + * // pvParameters value in the call to xTaskCreateStatic(). + * configASSERT( ( uint32_t ) pvParameters == 1U ); + * + * for( ;; ) + * { + * // Task code goes here. + * } + * } + * + * // Function that creates a task. + * void vOtherFunction( void ) + * { + * TaskHandle_t xHandle = NULL; + * + * // Create the task without using any dynamic memory allocation. + * xHandle = xTaskCreateStatic( + * vTaskCode, // Function that implements the task. + * "NAME", // Text name for the task. + * STACK_SIZE, // Stack size in words, not bytes. + * ( void * ) 1, // Parameter passed into the task. + * tskIDLE_PRIORITY,// Priority at which the task is created. + * xStack, // Array to use as the task's stack. + * &xTaskBuffer ); // Variable to hold the task's data structure. + * + * // puxStackBuffer and pxTaskBuffer were not NULL, so the task will have + * // been created, and xHandle will be the task's handle. Use the handle + * // to suspend the task. + * vTaskSuspend( xHandle ); + * } + * @endcode + * \defgroup xTaskCreateStatic xTaskCreateStatic + * \ingroup Tasks + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + TaskHandle_t xTaskCreateStatic( TaskFunction_t pxTaskCode, + const char * const pcName, + const configSTACK_DEPTH_TYPE uxStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + StackType_t * const puxStackBuffer, + StaticTask_t * const pxTaskBuffer ) PRIVILEGED_FUNCTION; +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) + TaskHandle_t xTaskCreateStaticAffinitySet( TaskFunction_t pxTaskCode, + const char * const pcName, + const configSTACK_DEPTH_TYPE uxStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + StackType_t * const puxStackBuffer, + StaticTask_t * const pxTaskBuffer, + UBaseType_t uxCoreAffinityMask ) PRIVILEGED_FUNCTION; +#endif + +/** + * task. h + * @code{c} + * BaseType_t xTaskCreateRestricted( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask ); + * @endcode + * + * Only available when configSUPPORT_DYNAMIC_ALLOCATION is set to 1. + * + * xTaskCreateRestricted() should only be used in systems that include an MPU + * implementation. + * + * Create a new task and add it to the list of tasks that are ready to run. + * The function parameters define the memory regions and associated access + * permissions allocated to the task. + * + * See xTaskCreateRestrictedStatic() for a version that does not use any + * dynamic memory allocation. + * + * @param pxTaskDefinition Pointer to a structure that contains a member + * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API + * documentation) plus an optional stack buffer and the memory region + * definitions. + * + * @param pxCreatedTask Used to pass back a handle by which the created task + * can be referenced. + * + * @return pdPASS if the task was successfully created and added to a ready + * list, otherwise an error code defined in the file projdefs.h + * + * Example usage: + * @code{c} + * // Create an TaskParameters_t structure that defines the task to be created. + * static const TaskParameters_t xCheckTaskParameters = + * { + * vATask, // pvTaskCode - the function that implements the task. + * "ATask", // pcName - just a text name for the task to assist debugging. + * 100, // uxStackDepth - the stack size DEFINED IN WORDS. + * NULL, // pvParameters - passed into the task function as the function parameters. + * ( 1U | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state. + * cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack. + * + * // xRegions - Allocate up to three separate memory regions for access by + * // the task, with appropriate access permissions. Different processors have + * // different memory alignment requirements - refer to the FreeRTOS documentation + * // for full information. + * { + * // Base address Length Parameters + * { cReadWriteArray, 32, portMPU_REGION_READ_WRITE }, + * { cReadOnlyArray, 32, portMPU_REGION_READ_ONLY }, + * { cPrivilegedOnlyAccessArray, 128, portMPU_REGION_PRIVILEGED_READ_WRITE } + * } + * }; + * + * int main( void ) + * { + * TaskHandle_t xHandle; + * + * // Create a task from the const structure defined above. The task handle + * // is requested (the second parameter is not NULL) but in this case just for + * // demonstration purposes as its not actually used. + * xTaskCreateRestricted( &xRegTest1Parameters, &xHandle ); + * + * // Start the scheduler. + * vTaskStartScheduler(); + * + * // Will only get here if there was insufficient memory to create the idle + * // and/or timer task. + * for( ;; ); + * } + * @endcode + * \defgroup xTaskCreateRestricted xTaskCreateRestricted + * \ingroup Tasks + */ +#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, + TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION; +#endif + +#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) + BaseType_t xTaskCreateRestrictedAffinitySet( const TaskParameters_t * const pxTaskDefinition, + UBaseType_t uxCoreAffinityMask, + TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION; +#endif + +/** + * task. h + * @code{c} + * BaseType_t xTaskCreateRestrictedStatic( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask ); + * @endcode + * + * Only available when configSUPPORT_STATIC_ALLOCATION is set to 1. + * + * xTaskCreateRestrictedStatic() should only be used in systems that include an + * MPU implementation. + * + * Internally, within the FreeRTOS implementation, tasks use two blocks of + * memory. The first block is used to hold the task's data structures. The + * second block is used by the task as its stack. If a task is created using + * xTaskCreateRestricted() then the stack is provided by the application writer, + * and the memory used to hold the task's data structure is automatically + * dynamically allocated inside the xTaskCreateRestricted() function. If a task + * is created using xTaskCreateRestrictedStatic() then the application writer + * must provide the memory used to hold the task's data structures too. + * xTaskCreateRestrictedStatic() therefore allows a memory protected task to be + * created without using any dynamic memory allocation. + * + * @param pxTaskDefinition Pointer to a structure that contains a member + * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API + * documentation) plus an optional stack buffer and the memory region + * definitions. If configSUPPORT_STATIC_ALLOCATION is set to 1 the structure + * contains an additional member, which is used to point to a variable of type + * StaticTask_t - which is then used to hold the task's data structure. + * + * @param pxCreatedTask Used to pass back a handle by which the created task + * can be referenced. + * + * @return pdPASS if the task was successfully created and added to a ready + * list, otherwise an error code defined in the file projdefs.h + * + * Example usage: + * @code{c} + * // Create an TaskParameters_t structure that defines the task to be created. + * // The StaticTask_t variable is only included in the structure when + * // configSUPPORT_STATIC_ALLOCATION is set to 1. The PRIVILEGED_DATA macro can + * // be used to force the variable into the RTOS kernel's privileged data area. + * static PRIVILEGED_DATA StaticTask_t xTaskBuffer; + * static const TaskParameters_t xCheckTaskParameters = + * { + * vATask, // pvTaskCode - the function that implements the task. + * "ATask", // pcName - just a text name for the task to assist debugging. + * 100, // uxStackDepth - the stack size DEFINED IN WORDS. + * NULL, // pvParameters - passed into the task function as the function parameters. + * ( 1U | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state. + * cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack. + * + * // xRegions - Allocate up to three separate memory regions for access by + * // the task, with appropriate access permissions. Different processors have + * // different memory alignment requirements - refer to the FreeRTOS documentation + * // for full information. + * { + * // Base address Length Parameters + * { cReadWriteArray, 32, portMPU_REGION_READ_WRITE }, + * { cReadOnlyArray, 32, portMPU_REGION_READ_ONLY }, + * { cPrivilegedOnlyAccessArray, 128, portMPU_REGION_PRIVILEGED_READ_WRITE } + * } + * + * &xTaskBuffer; // Holds the task's data structure. + * }; + * + * int main( void ) + * { + * TaskHandle_t xHandle; + * + * // Create a task from the const structure defined above. The task handle + * // is requested (the second parameter is not NULL) but in this case just for + * // demonstration purposes as its not actually used. + * xTaskCreateRestrictedStatic( &xRegTest1Parameters, &xHandle ); + * + * // Start the scheduler. + * vTaskStartScheduler(); + * + * // Will only get here if there was insufficient memory to create the idle + * // and/or timer task. + * for( ;; ); + * } + * @endcode + * \defgroup xTaskCreateRestrictedStatic xTaskCreateRestrictedStatic + * \ingroup Tasks + */ +#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, + TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION; +#endif + +#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) + BaseType_t xTaskCreateRestrictedStaticAffinitySet( const TaskParameters_t * const pxTaskDefinition, + UBaseType_t uxCoreAffinityMask, + TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION; +#endif + +/** + * task. h + * @code{c} + * void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ); + * @endcode + * + * Memory regions are assigned to a restricted task when the task is created by + * a call to xTaskCreateRestricted(). These regions can be redefined using + * vTaskAllocateMPURegions(). + * + * @param xTaskToModify The handle of the task being updated. + * + * @param[in] pxRegions A pointer to a MemoryRegion_t structure that contains the + * new memory region definitions. + * + * Example usage: + * @code{c} + * // Define an array of MemoryRegion_t structures that configures an MPU region + * // allowing read/write access for 1024 bytes starting at the beginning of the + * // ucOneKByte array. The other two of the maximum 3 definable regions are + * // unused so set to zero. + * static const MemoryRegion_t xAltRegions[ portNUM_CONFIGURABLE_REGIONS ] = + * { + * // Base address Length Parameters + * { ucOneKByte, 1024, portMPU_REGION_READ_WRITE }, + * { 0, 0, 0 }, + * { 0, 0, 0 } + * }; + * + * void vATask( void *pvParameters ) + * { + * // This task was created such that it has access to certain regions of + * // memory as defined by the MPU configuration. At some point it is + * // desired that these MPU regions are replaced with that defined in the + * // xAltRegions const struct above. Use a call to vTaskAllocateMPURegions() + * // for this purpose. NULL is used as the task handle to indicate that this + * // function should modify the MPU regions of the calling task. + * vTaskAllocateMPURegions( NULL, xAltRegions ); + * + * // Now the task can continue its function, but from this point on can only + * // access its stack and the ucOneKByte array (unless any other statically + * // defined or shared regions have been declared elsewhere). + * } + * @endcode + * \defgroup vTaskAllocateMPURegions vTaskAllocateMPURegions + * \ingroup Tasks + */ +#if ( portUSING_MPU_WRAPPERS == 1 ) + void vTaskAllocateMPURegions( TaskHandle_t xTaskToModify, + const MemoryRegion_t * const pxRegions ) PRIVILEGED_FUNCTION; +#endif + +/** + * task. h + * @code{c} + * void vTaskDelete( TaskHandle_t xTaskToDelete ); + * @endcode + * + * INCLUDE_vTaskDelete must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Remove a task from the RTOS real time kernel's management. The task being + * deleted will be removed from all ready, blocked, suspended and event lists. + * + * NOTE: The idle task is responsible for freeing the kernel allocated + * memory from tasks that have been deleted. It is therefore important that + * the idle task is not starved of microcontroller processing time if your + * application makes any calls to vTaskDelete (). Memory allocated by the + * task code is not automatically freed, and should be freed before the task + * is deleted. + * + * See the demo application file death.c for sample code that utilises + * vTaskDelete (). + * + * @param xTaskToDelete The handle of the task to be deleted. Passing NULL will + * cause the calling task to be deleted. + * + * Example usage: + * @code{c} + * void vOtherFunction( void ) + * { + * TaskHandle_t xHandle; + * + * // Create the task, storing the handle. + * xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle ); + * + * // Use the handle to delete the task. + * vTaskDelete( xHandle ); + * } + * @endcode + * \defgroup vTaskDelete vTaskDelete + * \ingroup Tasks + */ +void vTaskDelete( TaskHandle_t xTaskToDelete ) PRIVILEGED_FUNCTION; + +/*----------------------------------------------------------- +* TASK CONTROL API +*----------------------------------------------------------*/ + +/** + * task. h + * @code{c} + * void vTaskDelay( const TickType_t xTicksToDelay ); + * @endcode + * + * Delay a task for a given number of ticks. The actual time that the + * task remains blocked depends on the tick rate. The constant + * portTICK_PERIOD_MS can be used to calculate real time from the tick + * rate - with the resolution of one tick period. + * + * INCLUDE_vTaskDelay must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * + * vTaskDelay() specifies a time at which the task wishes to unblock relative to + * the time at which vTaskDelay() is called. For example, specifying a block + * period of 100 ticks will cause the task to unblock 100 ticks after + * vTaskDelay() is called. vTaskDelay() does not therefore provide a good method + * of controlling the frequency of a periodic task as the path taken through the + * code, as well as other task and interrupt activity, will affect the frequency + * at which vTaskDelay() gets called and therefore the time at which the task + * next executes. See xTaskDelayUntil() for an alternative API function designed + * to facilitate fixed frequency execution. It does this by specifying an + * absolute time (rather than a relative time) at which the calling task should + * unblock. + * + * @param xTicksToDelay The amount of time, in tick periods, that + * the calling task should block. + * + * Example usage: + * + * void vTaskFunction( void * pvParameters ) + * { + * // Block for 500ms. + * const TickType_t xDelay = 500 / portTICK_PERIOD_MS; + * + * for( ;; ) + * { + * // Simply toggle the LED every 500ms, blocking between each toggle. + * vToggleLED(); + * vTaskDelay( xDelay ); + * } + * } + * + * \defgroup vTaskDelay vTaskDelay + * \ingroup TaskCtrl + */ +void vTaskDelay( const TickType_t xTicksToDelay ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * BaseType_t xTaskDelayUntil( TickType_t *pxPreviousWakeTime, const TickType_t xTimeIncrement ); + * @endcode + * + * INCLUDE_xTaskDelayUntil must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Delay a task until a specified time. This function can be used by periodic + * tasks to ensure a constant execution frequency. + * + * This function differs from vTaskDelay () in one important aspect: vTaskDelay () will + * cause a task to block for the specified number of ticks from the time vTaskDelay () is + * called. It is therefore difficult to use vTaskDelay () by itself to generate a fixed + * execution frequency as the time between a task starting to execute and that task + * calling vTaskDelay () may not be fixed [the task may take a different path though the + * code between calls, or may get interrupted or preempted a different number of times + * each time it executes]. + * + * Whereas vTaskDelay () specifies a wake time relative to the time at which the function + * is called, xTaskDelayUntil () specifies the absolute (exact) time at which it wishes to + * unblock. + * + * The macro pdMS_TO_TICKS() can be used to calculate the number of ticks from a + * time specified in milliseconds with a resolution of one tick period. + * + * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the + * task was last unblocked. The variable must be initialised with the current time + * prior to its first use (see the example below). Following this the variable is + * automatically updated within xTaskDelayUntil (). + * + * @param xTimeIncrement The cycle time period. The task will be unblocked at + * time *pxPreviousWakeTime + xTimeIncrement. Calling xTaskDelayUntil with the + * same xTimeIncrement parameter value will cause the task to execute with + * a fixed interface period. + * + * @return Value which can be used to check whether the task was actually delayed. + * Will be pdTRUE if the task way delayed and pdFALSE otherwise. A task will not + * be delayed if the next expected wake time is in the past. This prevents periodic + * tasks from accumulating delays and allows them to resume their regular timing pattern. + * + * Example usage: + * @code{c} + * // Perform an action every 10 ticks. + * void vTaskFunction( void * pvParameters ) + * { + * TickType_t xLastWakeTime; + * const TickType_t xFrequency = 10; + * BaseType_t xWasDelayed; + * + * // Initialise the xLastWakeTime variable with the current time. + * xLastWakeTime = xTaskGetTickCount (); + * for( ;; ) + * { + * // Wait for the next cycle. + * xWasDelayed = xTaskDelayUntil( &xLastWakeTime, xFrequency ); + * + * // Perform action here. xWasDelayed value can be used to determine + * // whether a deadline was missed if the code here took too long. + * } + * } + * @endcode + * \defgroup xTaskDelayUntil xTaskDelayUntil + * \ingroup TaskCtrl + */ +BaseType_t xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) PRIVILEGED_FUNCTION; + +/* + * vTaskDelayUntil() is the older version of xTaskDelayUntil() and does not + * return a value. + */ +#define vTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement ) \ + do { \ + ( void ) xTaskDelayUntil( ( pxPreviousWakeTime ), ( xTimeIncrement ) ); \ + } while( 0 ) + + +/** + * task. h + * @code{c} + * BaseType_t xTaskAbortDelay( TaskHandle_t xTask ); + * @endcode + * + * INCLUDE_xTaskAbortDelay must be defined as 1 in FreeRTOSConfig.h for this + * function to be available. + * + * A task will enter the Blocked state when it is waiting for an event. The + * event it is waiting for can be a temporal event (waiting for a time), such + * as when vTaskDelay() is called, or an event on an object, such as when + * xQueueReceive() or ulTaskNotifyTake() is called. If the handle of a task + * that is in the Blocked state is used in a call to xTaskAbortDelay() then the + * task will leave the Blocked state, and return from whichever function call + * placed the task into the Blocked state. + * + * There is no 'FromISR' version of this function as an interrupt would need to + * know which object a task was blocked on in order to know which actions to + * take. For example, if the task was blocked on a queue the interrupt handler + * would then need to know if the queue was locked. + * + * @param xTask The handle of the task to remove from the Blocked state. + * + * @return If the task referenced by xTask was not in the Blocked state then + * pdFAIL is returned. Otherwise pdPASS is returned. + * + * \defgroup xTaskAbortDelay xTaskAbortDelay + * \ingroup TaskCtrl + */ +#if ( INCLUDE_xTaskAbortDelay == 1 ) + BaseType_t xTaskAbortDelay( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; +#endif + +/** + * task. h + * @code{c} + * UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask ); + * @endcode + * + * INCLUDE_uxTaskPriorityGet must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Obtain the priority of any task. + * + * @param xTask Handle of the task to be queried. Passing a NULL + * handle results in the priority of the calling task being returned. + * + * @return The priority of xTask. + * + * Example usage: + * @code{c} + * void vAFunction( void ) + * { + * TaskHandle_t xHandle; + * + * // Create a task, storing the handle. + * xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle ); + * + * // ... + * + * // Use the handle to obtain the priority of the created task. + * // It was created with tskIDLE_PRIORITY, but may have changed + * // it itself. + * if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY ) + * { + * // The task has changed it's priority. + * } + * + * // ... + * + * // Is our priority higher than the created task? + * if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) ) + * { + * // Our priority (obtained using NULL handle) is higher. + * } + * } + * @endcode + * \defgroup uxTaskPriorityGet uxTaskPriorityGet + * \ingroup TaskCtrl + */ +UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask ); + * @endcode + * + * A version of uxTaskPriorityGet() that can be used from an ISR. + */ +UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * UBaseType_t uxTaskBasePriorityGet( const TaskHandle_t xTask ); + * @endcode + * + * INCLUDE_uxTaskPriorityGet and configUSE_MUTEXES must be defined as 1 for this + * function to be available. See the configuration section for more information. + * + * Obtain the base priority of any task. + * + * @param xTask Handle of the task to be queried. Passing a NULL + * handle results in the base priority of the calling task being returned. + * + * @return The base priority of xTask. + * + * \defgroup uxTaskPriorityGet uxTaskBasePriorityGet + * \ingroup TaskCtrl + */ +UBaseType_t uxTaskBasePriorityGet( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * UBaseType_t uxTaskBasePriorityGetFromISR( const TaskHandle_t xTask ); + * @endcode + * + * A version of uxTaskBasePriorityGet() that can be used from an ISR. + */ +UBaseType_t uxTaskBasePriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * eTaskState eTaskGetState( TaskHandle_t xTask ); + * @endcode + * + * INCLUDE_eTaskGetState must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Obtain the state of any task. States are encoded by the eTaskState + * enumerated type. + * + * @param xTask Handle of the task to be queried. + * + * @return The state of xTask at the time the function was called. Note the + * state of the task might change between the function being called, and the + * functions return value being tested by the calling task. + */ +#if ( ( INCLUDE_eTaskGetState == 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_xTaskAbortDelay == 1 ) ) + eTaskState eTaskGetState( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; +#endif + +/** + * task. h + * @code{c} + * void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ); + * @endcode + * + * configUSE_TRACE_FACILITY must be defined as 1 for this function to be + * available. See the configuration section for more information. + * + * Populates a TaskStatus_t structure with information about a task. + * + * @param xTask Handle of the task being queried. If xTask is NULL then + * information will be returned about the calling task. + * + * @param pxTaskStatus A pointer to the TaskStatus_t structure that will be + * filled with information about the task referenced by the handle passed using + * the xTask parameter. + * + * @param xGetFreeStackSpace The TaskStatus_t structure contains a member to report + * the stack high water mark of the task being queried. Calculating the stack + * high water mark takes a relatively long time, and can make the system + * temporarily unresponsive - so the xGetFreeStackSpace parameter is provided to + * allow the high water mark checking to be skipped. The high watermark value + * will only be written to the TaskStatus_t structure if xGetFreeStackSpace is + * not set to pdFALSE; + * + * @param eState The TaskStatus_t structure contains a member to report the + * state of the task being queried. Obtaining the task state is not as fast as + * a simple assignment - so the eState parameter is provided to allow the state + * information to be omitted from the TaskStatus_t structure. To obtain state + * information then set eState to eInvalid - otherwise the value passed in + * eState will be reported as the task state in the TaskStatus_t structure. + * + * Example usage: + * @code{c} + * void vAFunction( void ) + * { + * TaskHandle_t xHandle; + * TaskStatus_t xTaskDetails; + * + * // Obtain the handle of a task from its name. + * xHandle = xTaskGetHandle( "Task_Name" ); + * + * // Check the handle is not NULL. + * configASSERT( xHandle ); + * + * // Use the handle to obtain further information about the task. + * vTaskGetInfo( xHandle, + * &xTaskDetails, + * pdTRUE, // Include the high water mark in xTaskDetails. + * eInvalid ); // Include the task state in xTaskDetails. + * } + * @endcode + * \defgroup vTaskGetInfo vTaskGetInfo + * \ingroup TaskCtrl + */ +#if ( configUSE_TRACE_FACILITY == 1 ) + void vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) PRIVILEGED_FUNCTION; +#endif + +/** + * task. h + * @code{c} + * void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ); + * @endcode + * + * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Set the priority of any task. + * + * A context switch will occur before the function returns if the priority + * being set is higher than the currently executing task. + * + * @param xTask Handle to the task for which the priority is being set. + * Passing a NULL handle results in the priority of the calling task being set. + * + * @param uxNewPriority The priority to which the task will be set. + * + * Example usage: + * @code{c} + * void vAFunction( void ) + * { + * TaskHandle_t xHandle; + * + * // Create a task, storing the handle. + * xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle ); + * + * // ... + * + * // Use the handle to raise the priority of the created task. + * vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 ); + * + * // ... + * + * // Use a NULL handle to raise our priority to the same value. + * vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 ); + * } + * @endcode + * \defgroup vTaskPrioritySet vTaskPrioritySet + * \ingroup TaskCtrl + */ +void vTaskPrioritySet( TaskHandle_t xTask, + UBaseType_t uxNewPriority ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * void vTaskSuspend( TaskHandle_t xTaskToSuspend ); + * @endcode + * + * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Suspend any task. When suspended a task will never get any microcontroller + * processing time, no matter what its priority. + * + * Calls to vTaskSuspend are not accumulative - + * i.e. calling vTaskSuspend () twice on the same task still only requires one + * call to vTaskResume () to ready the suspended task. + * + * @param xTaskToSuspend Handle to the task being suspended. Passing a NULL + * handle will cause the calling task to be suspended. + * + * Example usage: + * @code{c} + * void vAFunction( void ) + * { + * TaskHandle_t xHandle; + * + * // Create a task, storing the handle. + * xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle ); + * + * // ... + * + * // Use the handle to suspend the created task. + * vTaskSuspend( xHandle ); + * + * // ... + * + * // The created task will not run during this period, unless + * // another task calls vTaskResume( xHandle ). + * + * //... + * + * + * // Suspend ourselves. + * vTaskSuspend( NULL ); + * + * // We cannot get here unless another task calls vTaskResume + * // with our handle as the parameter. + * } + * @endcode + * \defgroup vTaskSuspend vTaskSuspend + * \ingroup TaskCtrl + */ +void vTaskSuspend( TaskHandle_t xTaskToSuspend ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * void vTaskResume( TaskHandle_t xTaskToResume ); + * @endcode + * + * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Resumes a suspended task. + * + * A task that has been suspended by one or more calls to vTaskSuspend () + * will be made available for running again by a single call to + * vTaskResume (). + * + * @param xTaskToResume Handle to the task being readied. + * + * Example usage: + * @code{c} + * void vAFunction( void ) + * { + * TaskHandle_t xHandle; + * + * // Create a task, storing the handle. + * xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle ); + * + * // ... + * + * // Use the handle to suspend the created task. + * vTaskSuspend( xHandle ); + * + * // ... + * + * // The created task will not run during this period, unless + * // another task calls vTaskResume( xHandle ). + * + * //... + * + * + * // Resume the suspended task ourselves. + * vTaskResume( xHandle ); + * + * // The created task will once again get microcontroller processing + * // time in accordance with its priority within the system. + * } + * @endcode + * \defgroup vTaskResume vTaskResume + * \ingroup TaskCtrl + */ +void vTaskResume( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * void xTaskResumeFromISR( TaskHandle_t xTaskToResume ); + * @endcode + * + * INCLUDE_xTaskResumeFromISR must be defined as 1 for this function to be + * available. See the configuration section for more information. + * + * An implementation of vTaskResume() that can be called from within an ISR. + * + * A task that has been suspended by one or more calls to vTaskSuspend () + * will be made available for running again by a single call to + * xTaskResumeFromISR (). + * + * xTaskResumeFromISR() should not be used to synchronise a task with an + * interrupt if there is a chance that the interrupt could arrive prior to the + * task being suspended - as this can lead to interrupts being missed. Use of a + * semaphore as a synchronisation mechanism would avoid this eventuality. + * + * @param xTaskToResume Handle to the task being readied. + * + * @return pdTRUE if resuming the task should result in a context switch, + * otherwise pdFALSE. This is used by the ISR to determine if a context switch + * may be required following the ISR. + * + * \defgroup vTaskResumeFromISR vTaskResumeFromISR + * \ingroup TaskCtrl + */ +BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION; + +#if ( configUSE_CORE_AFFINITY == 1 ) + +/** + * @brief Sets the core affinity mask for a task. + * + * It sets the cores on which a task can run. configUSE_CORE_AFFINITY must + * be defined as 1 for this function to be available. + * + * @param xTask The handle of the task to set the core affinity mask for. + * Passing NULL will set the core affinity mask for the calling task. + * + * @param uxCoreAffinityMask A bitwise value that indicates the cores on + * which the task can run. Cores are numbered from 0 to configNUMBER_OF_CORES - 1. + * For example, to ensure that a task can run on core 0 and core 1, set + * uxCoreAffinityMask to 0x03. + * + * Example usage: + * + * // The function that creates task. + * void vAFunction( void ) + * { + * TaskHandle_t xHandle; + * UBaseType_t uxCoreAffinityMask; + * + * // Create a task, storing the handle. + * xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &( xHandle ) ); + * + * // Define the core affinity mask such that this task can only run + * // on core 0 and core 2. + * uxCoreAffinityMask = ( ( 1 << 0 ) | ( 1 << 2 ) ); + * + * //Set the core affinity mask for the task. + * vTaskCoreAffinitySet( xHandle, uxCoreAffinityMask ); + * } + */ + void vTaskCoreAffinitySet( const TaskHandle_t xTask, + UBaseType_t uxCoreAffinityMask ); +#endif + +#if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) + +/** + * @brief Gets the core affinity mask for a task. + * + * configUSE_CORE_AFFINITY must be defined as 1 for this function to be + * available. + * + * @param xTask The handle of the task to get the core affinity mask for. + * Passing NULL will get the core affinity mask for the calling task. + * + * @return The core affinity mask which is a bitwise value that indicates + * the cores on which a task can run. Cores are numbered from 0 to + * configNUMBER_OF_CORES - 1. For example, if a task can run on core 0 and core 1, + * the core affinity mask is 0x03. + * + * Example usage: + * + * // Task handle of the networking task - it is populated elsewhere. + * TaskHandle_t xNetworkingTaskHandle; + * + * void vAFunction( void ) + * { + * TaskHandle_t xHandle; + * UBaseType_t uxNetworkingCoreAffinityMask; + * + * // Create a task, storing the handle. + * xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &( xHandle ) ); + * + * //Get the core affinity mask for the networking task. + * uxNetworkingCoreAffinityMask = vTaskCoreAffinityGet( xNetworkingTaskHandle ); + * + * // Here is a hypothetical scenario, just for the example. Assume that we + * // have 2 cores - Core 0 and core 1. We want to pin the application task to + * // the core different than the networking task to ensure that the + * // application task does not interfere with networking. + * if( ( uxNetworkingCoreAffinityMask & ( 1 << 0 ) ) != 0 ) + * { + * // The networking task can run on core 0, pin our task to core 1. + * vTaskCoreAffinitySet( xHandle, ( 1 << 1 ) ); + * } + * else + * { + * // Otherwise, pin our task to core 0. + * vTaskCoreAffinitySet( xHandle, ( 1 << 0 ) ); + * } + * } + */ + UBaseType_t vTaskCoreAffinityGet( ConstTaskHandle_t xTask ); +#endif + +#if ( configUSE_TASK_PREEMPTION_DISABLE == 1 ) + +/** + * @brief Disables preemption for a task. + * + * @param xTask The handle of the task to disable preemption. Passing NULL + * disables preemption for the calling task. + * + * Example usage: + * + * void vTaskCode( void *pvParameters ) + * { + * // Silence warnings about unused parameters. + * ( void ) pvParameters; + * + * for( ;; ) + * { + * // ... Perform some function here. + * + * // Disable preemption for this task. + * vTaskPreemptionDisable( NULL ); + * + * // The task will not be preempted when it is executing in this portion ... + * + * // ... until the preemption is enabled again. + * vTaskPreemptionEnable( NULL ); + * + * // The task can be preempted when it is executing in this portion. + * } + * } + */ + void vTaskPreemptionDisable( const TaskHandle_t xTask ); +#endif + +#if ( configUSE_TASK_PREEMPTION_DISABLE == 1 ) + +/** + * @brief Enables preemption for a task. + * + * @param xTask The handle of the task to enable preemption. Passing NULL + * enables preemption for the calling task. + * + * Example usage: + * + * void vTaskCode( void *pvParameters ) + * { + * // Silence warnings about unused parameters. + * ( void ) pvParameters; + * + * for( ;; ) + * { + * // ... Perform some function here. + * + * // Disable preemption for this task. + * vTaskPreemptionDisable( NULL ); + * + * // The task will not be preempted when it is executing in this portion ... + * + * // ... until the preemption is enabled again. + * vTaskPreemptionEnable( NULL ); + * + * // The task can be preempted when it is executing in this portion. + * } + * } + */ + void vTaskPreemptionEnable( const TaskHandle_t xTask ); +#endif + +/*----------------------------------------------------------- +* SCHEDULER CONTROL +*----------------------------------------------------------*/ + +/** + * task. h + * @code{c} + * void vTaskStartScheduler( void ); + * @endcode + * + * Starts the real time kernel tick processing. After calling the kernel + * has control over which tasks are executed and when. + * + * See the demo application file main.c for an example of creating + * tasks and starting the kernel. + * + * Example usage: + * @code{c} + * void vAFunction( void ) + * { + * // Create at least one task before starting the kernel. + * xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + * + * // Start the real time kernel with preemption. + * vTaskStartScheduler (); + * + * // Will not get here unless a task calls vTaskEndScheduler () + * } + * @endcode + * + * \defgroup vTaskStartScheduler vTaskStartScheduler + * \ingroup SchedulerControl + */ +void vTaskStartScheduler( void ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * void vTaskEndScheduler( void ); + * @endcode + * + * NOTE: At the time of writing only the x86 real mode port, which runs on a PC + * in place of DOS, implements this function. + * + * Stops the real time kernel tick. All created tasks will be automatically + * deleted and multitasking (either preemptive or cooperative) will + * stop. Execution then resumes from the point where vTaskStartScheduler () + * was called, as if vTaskStartScheduler () had just returned. + * + * See the demo application file main. c in the demo/PC directory for an + * example that uses vTaskEndScheduler (). + * + * vTaskEndScheduler () requires an exit function to be defined within the + * portable layer (see vPortEndScheduler () in port. c for the PC port). This + * performs hardware specific operations such as stopping the kernel tick. + * + * vTaskEndScheduler () will cause all of the resources allocated by the + * kernel to be freed - but will not free resources allocated by application + * tasks. + * + * Example usage: + * @code{c} + * void vTaskCode( void * pvParameters ) + * { + * for( ;; ) + * { + * // Task code goes here. + * + * // At some point we want to end the real time kernel processing + * // so call ... + * vTaskEndScheduler (); + * } + * } + * + * void vAFunction( void ) + * { + * // Create at least one task before starting the kernel. + * xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + * + * // Start the real time kernel with preemption. + * vTaskStartScheduler (); + * + * // Will only get here when the vTaskCode () task has called + * // vTaskEndScheduler (). When we get here we are back to single task + * // execution. + * } + * @endcode + * + * \defgroup vTaskEndScheduler vTaskEndScheduler + * \ingroup SchedulerControl + */ +void vTaskEndScheduler( void ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * void vTaskSuspendAll( void ); + * @endcode + * + * Suspends the scheduler without disabling interrupts. Context switches will + * not occur while the scheduler is suspended. + * + * After calling vTaskSuspendAll () the calling task will continue to execute + * without risk of being swapped out until a call to xTaskResumeAll () has been + * made. + * + * API functions that have the potential to cause a context switch (for example, + * xTaskDelayUntil(), xQueueSend(), etc.) must not be called while the scheduler + * is suspended. + * + * Example usage: + * @code{c} + * void vTask1( void * pvParameters ) + * { + * for( ;; ) + * { + * // Task code goes here. + * + * // ... + * + * // At some point the task wants to perform a long operation during + * // which it does not want to get swapped out. It cannot use + * // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the + * // operation may cause interrupts to be missed - including the + * // ticks. + * + * // Prevent the real time kernel swapping out the task. + * vTaskSuspendAll (); + * + * // Perform the operation here. There is no need to use critical + * // sections as we have all the microcontroller processing time. + * // During this time interrupts will still operate and the kernel + * // tick count will be maintained. + * + * // ... + * + * // The operation is complete. Restart the kernel. + * xTaskResumeAll (); + * } + * } + * @endcode + * \defgroup vTaskSuspendAll vTaskSuspendAll + * \ingroup SchedulerControl + */ +void vTaskSuspendAll( void ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * BaseType_t xTaskResumeAll( void ); + * @endcode + * + * Resumes scheduler activity after it was suspended by a call to + * vTaskSuspendAll(). + * + * xTaskResumeAll() only resumes the scheduler. It does not unsuspend tasks + * that were previously suspended by a call to vTaskSuspend(). + * + * @return If resuming the scheduler caused a context switch then pdTRUE is + * returned, otherwise pdFALSE is returned. + * + * Example usage: + * @code{c} + * void vTask1( void * pvParameters ) + * { + * for( ;; ) + * { + * // Task code goes here. + * + * // ... + * + * // At some point the task wants to perform a long operation during + * // which it does not want to get swapped out. It cannot use + * // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the + * // operation may cause interrupts to be missed - including the + * // ticks. + * + * // Prevent the real time kernel swapping out the task. + * vTaskSuspendAll (); + * + * // Perform the operation here. There is no need to use critical + * // sections as we have all the microcontroller processing time. + * // During this time interrupts will still operate and the real + * // time kernel tick count will be maintained. + * + * // ... + * + * // The operation is complete. Restart the kernel. We want to force + * // a context switch - but there is no point if resuming the scheduler + * // caused a context switch already. + * if( !xTaskResumeAll () ) + * { + * taskYIELD (); + * } + * } + * } + * @endcode + * \defgroup xTaskResumeAll xTaskResumeAll + * \ingroup SchedulerControl + */ +BaseType_t xTaskResumeAll( void ) PRIVILEGED_FUNCTION; + +/*----------------------------------------------------------- +* TASK UTILITIES +*----------------------------------------------------------*/ + +/** + * task. h + * @code{c} + * TickType_t xTaskGetTickCount( void ); + * @endcode + * + * @return The count of ticks since vTaskStartScheduler was called. + * + * \defgroup xTaskGetTickCount xTaskGetTickCount + * \ingroup TaskUtils + */ +TickType_t xTaskGetTickCount( void ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * TickType_t xTaskGetTickCountFromISR( void ); + * @endcode + * + * @return The count of ticks since vTaskStartScheduler was called. + * + * This is a version of xTaskGetTickCount() that is safe to be called from an + * ISR - provided that TickType_t is the natural word size of the + * microcontroller being used or interrupt nesting is either not supported or + * not being used. + * + * \defgroup xTaskGetTickCountFromISR xTaskGetTickCountFromISR + * \ingroup TaskUtils + */ +TickType_t xTaskGetTickCountFromISR( void ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * uint16_t uxTaskGetNumberOfTasks( void ); + * @endcode + * + * @return The number of tasks that the real time kernel is currently managing. + * This includes all ready, blocked and suspended tasks. A task that + * has been deleted but not yet freed by the idle task will also be + * included in the count. + * + * \defgroup uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks + * \ingroup TaskUtils + */ +UBaseType_t uxTaskGetNumberOfTasks( void ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * char *pcTaskGetName( TaskHandle_t xTaskToQuery ); + * @endcode + * + * @return The text (human readable) name of the task referenced by the handle + * xTaskToQuery. A task can query its own name by either passing in its own + * handle, or by setting xTaskToQuery to NULL. + * + * \defgroup pcTaskGetName pcTaskGetName + * \ingroup TaskUtils + */ +char * pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION; + +/** + * task. h + * @code{c} + * TaskHandle_t xTaskGetHandle( const char *pcNameToQuery ); + * @endcode + * + * NOTE: This function takes a relatively long time to complete and should be + * used sparingly. + * + * @return The handle of the task that has the human readable name pcNameToQuery. + * NULL is returned if no matching name is found. INCLUDE_xTaskGetHandle + * must be set to 1 in FreeRTOSConfig.h for pcTaskGetHandle() to be available. + * + * \defgroup pcTaskGetHandle pcTaskGetHandle + * \ingroup TaskUtils + */ +#if ( INCLUDE_xTaskGetHandle == 1 ) + TaskHandle_t xTaskGetHandle( const char * pcNameToQuery ) PRIVILEGED_FUNCTION; +#endif + +/** + * task. h + * @code{c} + * BaseType_t xTaskGetStaticBuffers( TaskHandle_t xTask, + * StackType_t ** ppuxStackBuffer, + * StaticTask_t ** ppxTaskBuffer ); + * @endcode + * + * Retrieve pointers to a statically created task's data structure + * buffer and stack buffer. These are the same buffers that are supplied + * at the time of creation. + * + * @param xTask The task for which to retrieve the buffers. + * + * @param ppuxStackBuffer Used to return a pointer to the task's stack buffer. + * + * @param ppxTaskBuffer Used to return a pointer to the task's data structure + * buffer. + * + * @return pdTRUE if buffers were retrieved, pdFALSE otherwise. + * + * \defgroup xTaskGetStaticBuffers xTaskGetStaticBuffers + * \ingroup TaskUtils + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + BaseType_t xTaskGetStaticBuffers( TaskHandle_t xTask, + StackType_t ** ppuxStackBuffer, + StaticTask_t ** ppxTaskBuffer ) PRIVILEGED_FUNCTION; +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +/** + * task.h + * @code{c} + * UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ); + * @endcode + * + * INCLUDE_uxTaskGetStackHighWaterMark must be set to 1 in FreeRTOSConfig.h for + * this function to be available. + * + * Returns the high water mark of the stack associated with xTask. That is, + * the minimum free stack space there has been (in words, so on a 32 bit machine + * a value of 1 means 4 bytes) since the task started. The smaller the returned + * number the closer the task has come to overflowing its stack. + * + * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the + * same except for their return type. Using configSTACK_DEPTH_TYPE allows the + * user to determine the return type. It gets around the problem of the value + * overflowing on 8-bit types without breaking backward compatibility for + * applications that expect an 8-bit return type. + * + * @param xTask Handle of the task associated with the stack to be checked. + * Set xTask to NULL to check the stack of the calling task. + * + * @return The smallest amount of free stack space there has been (in words, so + * actual spaces on the stack rather than bytes) since the task referenced by + * xTask was created. + */ +#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) + UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; +#endif + +/** + * task.h + * @code{c} + * configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ); + * @endcode + * + * INCLUDE_uxTaskGetStackHighWaterMark2 must be set to 1 in FreeRTOSConfig.h for + * this function to be available. + * + * Returns the high water mark of the stack associated with xTask. That is, + * the minimum free stack space there has been (in words, so on a 32 bit machine + * a value of 1 means 4 bytes) since the task started. The smaller the returned + * number the closer the task has come to overflowing its stack. + * + * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the + * same except for their return type. Using configSTACK_DEPTH_TYPE allows the + * user to determine the return type. It gets around the problem of the value + * overflowing on 8-bit types without breaking backward compatibility for + * applications that expect an 8-bit return type. + * + * @param xTask Handle of the task associated with the stack to be checked. + * Set xTask to NULL to check the stack of the calling task. + * + * @return The smallest amount of free stack space there has been (in words, so + * actual spaces on the stack rather than bytes) since the task referenced by + * xTask was created. + */ +#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) + configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; +#endif + +/* When using trace macros it is sometimes necessary to include task.h before + * FreeRTOS.h. When this is done TaskHookFunction_t will not yet have been defined, + * so the following two prototypes will cause a compilation error. This can be + * fixed by simply guarding against the inclusion of these two prototypes unless + * they are explicitly required by the configUSE_APPLICATION_TASK_TAG configuration + * constant. */ +#ifdef configUSE_APPLICATION_TASK_TAG + #if configUSE_APPLICATION_TASK_TAG == 1 + +/** + * task.h + * @code{c} + * void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ); + * @endcode + * + * Sets pxHookFunction to be the task hook function used by the task xTask. + * Passing xTask as NULL has the effect of setting the calling tasks hook + * function. + */ + void vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) PRIVILEGED_FUNCTION; + +/** + * task.h + * @code{c} + * void xTaskGetApplicationTaskTag( TaskHandle_t xTask ); + * @endcode + * + * Returns the pxHookFunction value assigned to the task xTask. Do not + * call from an interrupt service routine - call + * xTaskGetApplicationTaskTagFromISR() instead. + */ + TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +/** + * task.h + * @code{c} + * void xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask ); + * @endcode + * + * Returns the pxHookFunction value assigned to the task xTask. Can + * be called from an interrupt service routine. + */ + TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + #endif /* configUSE_APPLICATION_TASK_TAG ==1 */ +#endif /* ifdef configUSE_APPLICATION_TASK_TAG */ + +#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 ) + +/* Each task contains an array of pointers that is dimensioned by the + * configNUM_THREAD_LOCAL_STORAGE_POINTERS setting in FreeRTOSConfig.h. The + * kernel does not use the pointers itself, so the application writer can use + * the pointers for any purpose they wish. The following two functions are + * used to set and query a pointer respectively. */ + void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) PRIVILEGED_FUNCTION; + void * pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) PRIVILEGED_FUNCTION; + +#endif + +#if ( configCHECK_FOR_STACK_OVERFLOW > 0 ) + +/** + * task.h + * @code{c} + * void vApplicationStackOverflowHook( TaskHandle_t xTask, char *pcTaskName); + * @endcode + * + * The application stack overflow hook is called when a stack overflow is detected for a task. + * + * Details on stack overflow detection can be found here: https://www.FreeRTOS.org/Stacks-and-stack-overflow-checking.html + * + * @param xTask the task that just exceeded its stack boundaries. + * @param pcTaskName A character string containing the name of the offending task. + */ + /* MISRA Ref 8.6.1 [External linkage] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-86 */ + /* coverity[misra_c_2012_rule_8_6_violation] */ + void vApplicationStackOverflowHook( TaskHandle_t xTask, + char * pcTaskName ); + +#endif + +#if ( configUSE_IDLE_HOOK == 1 ) + +/** + * task.h + * @code{c} + * void vApplicationIdleHook( void ); + * @endcode + * + * The application idle hook is called by the idle task. + * This allows the application designer to add background functionality without + * the overhead of a separate task. + * NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES, CALL A FUNCTION THAT MIGHT BLOCK. + */ + /* MISRA Ref 8.6.1 [External linkage] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-86 */ + /* coverity[misra_c_2012_rule_8_6_violation] */ + void vApplicationIdleHook( void ); + +#endif + + +#if ( configUSE_TICK_HOOK != 0 ) + +/** + * task.h + * @code{c} + * void vApplicationTickHook( void ); + * @endcode + * + * This hook function is called in the system tick handler after any OS work is completed. + */ + /* MISRA Ref 8.6.1 [External linkage] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-86 */ + /* coverity[misra_c_2012_rule_8_6_violation] */ + void vApplicationTickHook( void ); + +#endif + +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + +/** + * task.h + * @code{c} + * void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, StackType_t ** ppxIdleTaskStackBuffer, configSTACK_DEPTH_TYPE * puxIdleTaskStackSize ) + * @endcode + * + * This function is used to provide a statically allocated block of memory to FreeRTOS to hold the Idle Task TCB. This function is required when + * configSUPPORT_STATIC_ALLOCATION is set. For more information see this URI: https://www.FreeRTOS.org/a00110.html#configSUPPORT_STATIC_ALLOCATION + * + * @param ppxIdleTaskTCBBuffer A handle to a statically allocated TCB buffer + * @param ppxIdleTaskStackBuffer A handle to a statically allocated Stack buffer for the idle task + * @param puxIdleTaskStackSize A pointer to the number of elements that will fit in the allocated stack buffer + */ + void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, + StackType_t ** ppxIdleTaskStackBuffer, + configSTACK_DEPTH_TYPE * puxIdleTaskStackSize ); + +/** + * task.h + * @code{c} + * void vApplicationGetPassiveIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, StackType_t ** ppxIdleTaskStackBuffer, configSTACK_DEPTH_TYPE * puxIdleTaskStackSize, BaseType_t xCoreID ) + * @endcode + * + * This function is used to provide a statically allocated block of memory to FreeRTOS to hold the Idle Tasks TCB. This function is required when + * configSUPPORT_STATIC_ALLOCATION is set. For more information see this URI: https://www.FreeRTOS.org/a00110.html#configSUPPORT_STATIC_ALLOCATION + * + * In the FreeRTOS SMP, there are a total of configNUMBER_OF_CORES idle tasks: + * 1. 1 Active idle task which does all the housekeeping. + * 2. ( configNUMBER_OF_CORES - 1 ) Passive idle tasks which do nothing. + * These idle tasks are created to ensure that each core has an idle task to run when + * no other task is available to run. + * + * The function vApplicationGetPassiveIdleTaskMemory is called with passive idle + * task index 0, 1 ... ( configNUMBER_OF_CORES - 2 ) to get memory for passive idle + * tasks. + * + * @param ppxIdleTaskTCBBuffer A handle to a statically allocated TCB buffer + * @param ppxIdleTaskStackBuffer A handle to a statically allocated Stack buffer for the idle task + * @param puxIdleTaskStackSize A pointer to the number of elements that will fit in the allocated stack buffer + * @param xPassiveIdleTaskIndex The passive idle task index of the idle task buffer + */ + #if ( configNUMBER_OF_CORES > 1 ) + void vApplicationGetPassiveIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, + StackType_t ** ppxIdleTaskStackBuffer, + configSTACK_DEPTH_TYPE * puxIdleTaskStackSize, + BaseType_t xPassiveIdleTaskIndex ); + #endif /* #if ( configNUMBER_OF_CORES > 1 ) */ +#endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ + +/** + * task.h + * @code{c} + * BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ); + * @endcode + * + * Calls the hook function associated with xTask. Passing xTask as NULL has + * the effect of calling the Running tasks (the calling task) hook function. + * + * pvParameter is passed to the hook function for the task to interpret as it + * wants. The return value is the value returned by the task hook function + * registered by the user. + */ +#if ( configUSE_APPLICATION_TASK_TAG == 1 ) + BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, + void * pvParameter ) PRIVILEGED_FUNCTION; +#endif + +/** + * xTaskGetIdleTaskHandle() is only available if + * INCLUDE_xTaskGetIdleTaskHandle is set to 1 in FreeRTOSConfig.h. + * + * In single-core FreeRTOS, this function simply returns the handle of the idle + * task. It is not valid to call xTaskGetIdleTaskHandle() before the scheduler + * has been started. + * + * In the FreeRTOS SMP, there are a total of configNUMBER_OF_CORES idle tasks: + * 1. 1 Active idle task which does all the housekeeping. + * 2. ( configNUMBER_OF_CORES - 1 ) Passive idle tasks which do nothing. + * These idle tasks are created to ensure that each core has an idle task to run when + * no other task is available to run. Call xTaskGetIdleTaskHandle() or + * xTaskGetIdleTaskHandleForCore() with xCoreID set to 0 to get the Active + * idle task handle. Call xTaskGetIdleTaskHandleForCore() with xCoreID set to + * 1,2 ... ( configNUMBER_OF_CORES - 1 ) to get the Passive idle task handles. + */ +#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) + #if ( configNUMBER_OF_CORES == 1 ) + TaskHandle_t xTaskGetIdleTaskHandle( void ) PRIVILEGED_FUNCTION; + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ + + TaskHandle_t xTaskGetIdleTaskHandleForCore( BaseType_t xCoreID ) PRIVILEGED_FUNCTION; +#endif /* #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */ + +/** + * configUSE_TRACE_FACILITY must be defined as 1 in FreeRTOSConfig.h for + * uxTaskGetSystemState() to be available. + * + * uxTaskGetSystemState() populates an TaskStatus_t structure for each task in + * the system. TaskStatus_t structures contain, among other things, members + * for the task handle, task name, task priority, task state, and total amount + * of run time consumed by the task. See the TaskStatus_t structure + * definition in this file for the full member list. + * + * NOTE: This function is intended for debugging use only as its use results in + * the scheduler remaining suspended for an extended period. + * + * @param pxTaskStatusArray A pointer to an array of TaskStatus_t structures. + * The array must contain at least one TaskStatus_t structure for each task + * that is under the control of the RTOS. The number of tasks under the control + * of the RTOS can be determined using the uxTaskGetNumberOfTasks() API function. + * + * @param uxArraySize The size of the array pointed to by the pxTaskStatusArray + * parameter. The size is specified as the number of indexes in the array, or + * the number of TaskStatus_t structures contained in the array, not by the + * number of bytes in the array. + * + * @param pulTotalRunTime If configGENERATE_RUN_TIME_STATS is set to 1 in + * FreeRTOSConfig.h then *pulTotalRunTime is set by uxTaskGetSystemState() to the + * total run time (as defined by the run time stats clock, see + * https://www.FreeRTOS.org/rtos-run-time-stats.html) since the target booted. + * pulTotalRunTime can be set to NULL to omit the total run time information. + * + * @return The number of TaskStatus_t structures that were populated by + * uxTaskGetSystemState(). This should equal the number returned by the + * uxTaskGetNumberOfTasks() API function, but will be zero if the value passed + * in the uxArraySize parameter was too small. + * + * Example usage: + * @code{c} + * // This example demonstrates how a human readable table of run time stats + * // information is generated from raw data provided by uxTaskGetSystemState(). + * // The human readable table is written to pcWriteBuffer + * void vTaskGetRunTimeStats( char *pcWriteBuffer ) + * { + * TaskStatus_t *pxTaskStatusArray; + * volatile UBaseType_t uxArraySize, x; + * configRUN_TIME_COUNTER_TYPE ulTotalRunTime, ulStatsAsPercentage; + * + * // Make sure the write buffer does not contain a string. + * pcWriteBuffer = 0x00; + * + * // Take a snapshot of the number of tasks in case it changes while this + * // function is executing. + * uxArraySize = uxTaskGetNumberOfTasks(); + * + * // Allocate a TaskStatus_t structure for each task. An array could be + * // allocated statically at compile time. + * pxTaskStatusArray = pvPortMalloc( uxArraySize * sizeof( TaskStatus_t ) ); + * + * if( pxTaskStatusArray != NULL ) + * { + * // Generate raw status information about each task. + * uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalRunTime ); + * + * // For percentage calculations. + * ulTotalRunTime /= 100U; + * + * // Avoid divide by zero errors. + * if( ulTotalRunTime > 0 ) + * { + * // For each populated position in the pxTaskStatusArray array, + * // format the raw data as human readable ASCII data + * for( x = 0; x < uxArraySize; x++ ) + * { + * // What percentage of the total run time has the task used? + * // This will always be rounded down to the nearest integer. + * // ulTotalRunTimeDiv100 has already been divided by 100. + * ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalRunTime; + * + * if( ulStatsAsPercentage > 0U ) + * { + * sprintf( pcWriteBuffer, "%s\t\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage ); + * } + * else + * { + * // If the percentage is zero here then the task has + * // consumed less than 1% of the total run time. + * sprintf( pcWriteBuffer, "%s\t\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter ); + * } + * + * pcWriteBuffer += strlen( ( char * ) pcWriteBuffer ); + * } + * } + * + * // The array is no longer needed, free the memory it consumes. + * vPortFree( pxTaskStatusArray ); + * } + * } + * @endcode + */ +#if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) PRIVILEGED_FUNCTION; +#endif + +/** + * task. h + * @code{c} + * void vTaskListTasks( char *pcWriteBuffer, size_t uxBufferLength ); + * @endcode + * + * configUSE_TRACE_FACILITY and configUSE_STATS_FORMATTING_FUNCTIONS must + * both be defined as 1 for this function to be available. See the + * configuration section of the FreeRTOS.org website for more information. + * + * NOTE 1: This function will disable interrupts for its duration. It is + * not intended for normal application runtime use but as a debug aid. + * + * Lists all the current tasks, along with their current state and stack + * usage high water mark. + * + * Tasks are reported as running ('X'), blocked ('B'), ready ('R'), deleted ('D') + * or suspended ('S'). + * + * PLEASE NOTE: + * + * This function is provided for convenience only, and is used by many of the + * demo applications. Do not consider it to be part of the scheduler. + * + * vTaskListTasks() calls uxTaskGetSystemState(), then formats part of the + * uxTaskGetSystemState() output into a human readable table that displays task + * information in the following format: + * Task Name, Task State, Task Priority, Task Stack High Watermak, Task Number. + * + * The following is a sample output: + * Task A X 2 67 2 + * Task B R 1 67 3 + * IDLE R 0 67 5 + * Tmr Svc B 6 137 6 + * + * Stack usage specified as the number of unused StackType_t words stack can hold + * on top of stack - not the number of bytes. + * + * vTaskListTasks() has a dependency on the snprintf() C library function that might + * bloat the code size, use a lot of stack, and provide different results on + * different platforms. An alternative, tiny, third party, and limited + * functionality implementation of snprintf() is provided in many of the + * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note + * printf-stdarg.c does not provide a full snprintf() implementation!). + * + * It is recommended that production systems call uxTaskGetSystemState() + * directly to get access to raw stats data, rather than indirectly through a + * call to vTaskListTasks(). + * + * @param pcWriteBuffer A buffer into which the above mentioned details + * will be written, in ASCII form. This buffer is assumed to be large + * enough to contain the generated report. Approximately 40 bytes per + * task should be sufficient. + * + * @param uxBufferLength Length of the pcWriteBuffer. + * + * \defgroup vTaskListTasks vTaskListTasks + * \ingroup TaskUtils + */ +#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) + void vTaskListTasks( char * pcWriteBuffer, + size_t uxBufferLength ) PRIVILEGED_FUNCTION; +#endif + +/** + * task. h + * @code{c} + * void vTaskList( char *pcWriteBuffer ); + * @endcode + * + * configUSE_TRACE_FACILITY and configUSE_STATS_FORMATTING_FUNCTIONS must + * both be defined as 1 for this function to be available. See the + * configuration section of the FreeRTOS.org website for more information. + * + * WARN: This function assumes that the pcWriteBuffer is of length + * configSTATS_BUFFER_MAX_LENGTH. This function is there only for + * backward compatibility. New applications are recommended to + * use vTaskListTasks and supply the length of the pcWriteBuffer explicitly. + * + * NOTE 1: This function will disable interrupts for its duration. It is + * not intended for normal application runtime use but as a debug aid. + * + * Lists all the current tasks, along with their current state and stack + * usage high water mark. + * + * Tasks are reported as running ('X'), blocked ('B'), ready ('R'), deleted ('D') + * or suspended ('S'). + * + * PLEASE NOTE: + * + * This function is provided for convenience only, and is used by many of the + * demo applications. Do not consider it to be part of the scheduler. + * + * vTaskList() calls uxTaskGetSystemState(), then formats part of the + * uxTaskGetSystemState() output into a human readable table that displays task + * information in the following format: + * Task Name, Task State, Task Priority, Task Stack High Watermak, Task Number. + * + * The following is a sample output: + * Task A X 2 67 2 + * Task B R 1 67 3 + * IDLE R 0 67 5 + * Tmr Svc B 6 137 6 + * + * Stack usage specified as the number of unused StackType_t words stack can hold + * on top of stack - not the number of bytes. + * + * vTaskList() has a dependency on the snprintf() C library function that might + * bloat the code size, use a lot of stack, and provide different results on + * different platforms. An alternative, tiny, third party, and limited + * functionality implementation of snprintf() is provided in many of the + * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note + * printf-stdarg.c does not provide a full snprintf() implementation!). + * + * It is recommended that production systems call uxTaskGetSystemState() + * directly to get access to raw stats data, rather than indirectly through a + * call to vTaskList(). + * + * @param pcWriteBuffer A buffer into which the above mentioned details + * will be written, in ASCII form. This buffer is assumed to be large + * enough to contain the generated report. Approximately 40 bytes per + * task should be sufficient. + * + * \defgroup vTaskList vTaskList + * \ingroup TaskUtils + */ +#define vTaskList( pcWriteBuffer ) vTaskListTasks( ( pcWriteBuffer ), configSTATS_BUFFER_MAX_LENGTH ) + +/** + * task. h + * @code{c} + * void vTaskGetRunTimeStatistics( char *pcWriteBuffer, size_t uxBufferLength ); + * @endcode + * + * configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS + * must both be defined as 1 for this function to be available. The application + * must also then provide definitions for + * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE() + * to configure a peripheral timer/counter and return the timers current count + * value respectively. The counter should be at least 10 times the frequency of + * the tick count. + * + * NOTE 1: This function will disable interrupts for its duration. It is + * not intended for normal application runtime use but as a debug aid. + * + * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total + * accumulated execution time being stored for each task. The resolution + * of the accumulated time value depends on the frequency of the timer + * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro. + * Calling vTaskGetRunTimeStatistics() writes the total execution time of each + * task into a buffer, both as an absolute count value and as a percentage + * of the total system execution time. + * + * NOTE 2: + * + * This function is provided for convenience only, and is used by many of the + * demo applications. Do not consider it to be part of the scheduler. + * + * vTaskGetRunTimeStatistics() calls uxTaskGetSystemState(), then formats part of + * the uxTaskGetSystemState() output into a human readable table that displays the + * amount of time each task has spent in the Running state in both absolute and + * percentage terms. + * + * vTaskGetRunTimeStatistics() has a dependency on the snprintf() C library function + * that might bloat the code size, use a lot of stack, and provide different + * results on different platforms. An alternative, tiny, third party, and + * limited functionality implementation of snprintf() is provided in many of the + * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note + * printf-stdarg.c does not provide a full snprintf() implementation!). + * + * It is recommended that production systems call uxTaskGetSystemState() directly + * to get access to raw stats data, rather than indirectly through a call to + * vTaskGetRunTimeStatistics(). + * + * @param pcWriteBuffer A buffer into which the execution times will be + * written, in ASCII form. This buffer is assumed to be large enough to + * contain the generated report. Approximately 40 bytes per task should + * be sufficient. + * + * @param uxBufferLength Length of the pcWriteBuffer. + * + * \defgroup vTaskGetRunTimeStatistics vTaskGetRunTimeStatistics + * \ingroup TaskUtils + */ +#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + void vTaskGetRunTimeStatistics( char * pcWriteBuffer, + size_t uxBufferLength ) PRIVILEGED_FUNCTION; +#endif + +/** + * task. h + * @code{c} + * void vTaskGetRunTimeStats( char *pcWriteBuffer ); + * @endcode + * + * configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS + * must both be defined as 1 for this function to be available. The application + * must also then provide definitions for + * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE() + * to configure a peripheral timer/counter and return the timers current count + * value respectively. The counter should be at least 10 times the frequency of + * the tick count. + * + * WARN: This function assumes that the pcWriteBuffer is of length + * configSTATS_BUFFER_MAX_LENGTH. This function is there only for + * backward compatibility. New applications are recommended to use + * vTaskGetRunTimeStatistics and supply the length of the pcWriteBuffer + * explicitly. + * + * NOTE 1: This function will disable interrupts for its duration. It is + * not intended for normal application runtime use but as a debug aid. + * + * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total + * accumulated execution time being stored for each task. The resolution + * of the accumulated time value depends on the frequency of the timer + * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro. + * Calling vTaskGetRunTimeStats() writes the total execution time of each + * task into a buffer, both as an absolute count value and as a percentage + * of the total system execution time. + * + * NOTE 2: + * + * This function is provided for convenience only, and is used by many of the + * demo applications. Do not consider it to be part of the scheduler. + * + * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part of the + * uxTaskGetSystemState() output into a human readable table that displays the + * amount of time each task has spent in the Running state in both absolute and + * percentage terms. + * + * vTaskGetRunTimeStats() has a dependency on the snprintf() C library function + * that might bloat the code size, use a lot of stack, and provide different + * results on different platforms. An alternative, tiny, third party, and + * limited functionality implementation of snprintf() is provided in many of the + * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note + * printf-stdarg.c does not provide a full snprintf() implementation!). + * + * It is recommended that production systems call uxTaskGetSystemState() directly + * to get access to raw stats data, rather than indirectly through a call to + * vTaskGetRunTimeStats(). + * + * @param pcWriteBuffer A buffer into which the execution times will be + * written, in ASCII form. This buffer is assumed to be large enough to + * contain the generated report. Approximately 40 bytes per task should + * be sufficient. + * + * \defgroup vTaskGetRunTimeStats vTaskGetRunTimeStats + * \ingroup TaskUtils + */ +#define vTaskGetRunTimeStats( pcWriteBuffer ) vTaskGetRunTimeStatistics( ( pcWriteBuffer ), configSTATS_BUFFER_MAX_LENGTH ) + +/** + * task. h + * @code{c} + * configRUN_TIME_COUNTER_TYPE ulTaskGetRunTimeCounter( const TaskHandle_t xTask ); + * configRUN_TIME_COUNTER_TYPE ulTaskGetRunTimePercent( const TaskHandle_t xTask ); + * @endcode + * + * configGENERATE_RUN_TIME_STATS must be defined as 1 for these functions to be + * available. The application must also then provide definitions for + * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and + * portGET_RUN_TIME_COUNTER_VALUE() to configure a peripheral timer/counter and + * return the timers current count value respectively. The counter should be + * at least 10 times the frequency of the tick count. + * + * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total + * accumulated execution time being stored for each task. The resolution + * of the accumulated time value depends on the frequency of the timer + * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro. + * While uxTaskGetSystemState() and vTaskGetRunTimeStats() writes the total + * execution time of each task into a buffer, ulTaskGetRunTimeCounter() + * returns the total execution time of just one task and + * ulTaskGetRunTimePercent() returns the percentage of the CPU time used by + * just one task. + * + * @return The total run time of the given task or the percentage of the total + * run time consumed by the given task. This is the amount of time the task + * has actually been executing. The unit of time is dependent on the frequency + * configured using the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and + * portGET_RUN_TIME_COUNTER_VALUE() macros. + * + * \defgroup ulTaskGetRunTimeCounter ulTaskGetRunTimeCounter + * \ingroup TaskUtils + */ +#if ( configGENERATE_RUN_TIME_STATS == 1 ) + configRUN_TIME_COUNTER_TYPE ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + configRUN_TIME_COUNTER_TYPE ulTaskGetRunTimePercent( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION; +#endif + +/** + * task. h + * @code{c} + * configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimeCounter( void ); + * configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimePercent( void ); + * @endcode + * + * configGENERATE_RUN_TIME_STATS must be defined as 1 for these functions to be + * available. The application must also then provide definitions for + * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and + * portGET_RUN_TIME_COUNTER_VALUE() to configure a peripheral timer/counter and + * return the timers current count value respectively. The counter should be + * at least 10 times the frequency of the tick count. + * + * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total + * accumulated execution time being stored for each task. The resolution + * of the accumulated time value depends on the frequency of the timer + * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro. + * While uxTaskGetSystemState() and vTaskGetRunTimeStats() writes the total + * execution time of each task into a buffer, ulTaskGetIdleRunTimeCounter() + * returns the total execution time of just the idle task and + * ulTaskGetIdleRunTimePercent() returns the percentage of the CPU time used by + * just the idle task. + * + * Note the amount of idle time is only a good measure of the slack time in a + * system if there are no other tasks executing at the idle priority, tickless + * idle is not used, and configIDLE_SHOULD_YIELD is set to 0. + * + * @return The total run time of the idle task or the percentage of the total + * run time consumed by the idle task. This is the amount of time the + * idle task has actually been executing. The unit of time is dependent on the + * frequency configured using the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and + * portGET_RUN_TIME_COUNTER_VALUE() macros. + * + * \defgroup ulTaskGetIdleRunTimeCounter ulTaskGetIdleRunTimeCounter + * \ingroup TaskUtils + */ +#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimeCounter( void ) PRIVILEGED_FUNCTION; + configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimePercent( void ) PRIVILEGED_FUNCTION; +#endif + +/** + * task. h + * @code{c} + * BaseType_t xTaskNotifyIndexed( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify, uint32_t ulValue, eNotifyAction eAction ); + * BaseType_t xTaskNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction ); + * @endcode + * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these + * functions to be available. + * + * Sends a direct to task notification to a task, with an optional value and + * action. + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * Events can be sent to a task using an intermediary object. Examples of such + * objects are queues, semaphores, mutexes and event groups. Task notifications + * are a method of sending an event directly to a task without the need for such + * an intermediary object. + * + * A notification sent to a task can optionally perform an action, such as + * update, overwrite or increment one of the task's notification values. In + * that way task notifications can be used to send data to a task, or be used as + * light weight and fast binary or counting semaphores. + * + * A task can use xTaskNotifyWaitIndexed() or ulTaskNotifyTakeIndexed() to + * [optionally] block to wait for a notification to be pending. The task does + * not consume any CPU time while it is in the Blocked state. + * + * A notification sent to a task will remain pending until it is cleared by the + * task calling xTaskNotifyWaitIndexed() or ulTaskNotifyTakeIndexed() (or their + * un-indexed equivalents). If the task was already in the Blocked state to + * wait for a notification when the notification arrives then the task will + * automatically be removed from the Blocked state (unblocked) and the + * notification cleared. + * + * **NOTE** Each notification within the array operates independently - a task + * can only block on one notification within the array at a time and will not be + * unblocked by a notification sent to any other array index. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. xTaskNotify() is the original API function, and remains backward + * compatible by always operating on the notification value at index 0 in the + * array. Calling xTaskNotify() is equivalent to calling xTaskNotifyIndexed() + * with the uxIndexToNotify parameter set to 0. + * + * @param xTaskToNotify The handle of the task being notified. The handle to a + * task can be returned from the xTaskCreate() API function used to create the + * task, and the handle of the currently running task can be obtained by calling + * xTaskGetCurrentTaskHandle(). + * + * @param uxIndexToNotify The index within the target task's array of + * notification values to which the notification is to be sent. uxIndexToNotify + * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES. xTaskNotify() does + * not have this parameter and always sends notifications to index 0. + * + * @param ulValue Data that can be sent with the notification. How the data is + * used depends on the value of the eAction parameter. + * + * @param eAction Specifies how the notification updates the task's notification + * value, if at all. Valid values for eAction are as follows: + * + * eSetBits - + * The target notification value is bitwise ORed with ulValue. + * xTaskNotifyIndexed() always returns pdPASS in this case. + * + * eIncrement - + * The target notification value is incremented. ulValue is not used and + * xTaskNotifyIndexed() always returns pdPASS in this case. + * + * eSetValueWithOverwrite - + * The target notification value is set to the value of ulValue, even if the + * task being notified had not yet processed the previous notification at the + * same array index (the task already had a notification pending at that index). + * xTaskNotifyIndexed() always returns pdPASS in this case. + * + * eSetValueWithoutOverwrite - + * If the task being notified did not already have a notification pending at the + * same array index then the target notification value is set to ulValue and + * xTaskNotifyIndexed() will return pdPASS. If the task being notified already + * had a notification pending at the same array index then no action is + * performed and pdFAIL is returned. + * + * eNoAction - + * The task receives a notification at the specified array index without the + * notification value at that index being updated. ulValue is not used and + * xTaskNotifyIndexed() always returns pdPASS in this case. + * + * @param pulPreviousNotificationValue Can be used to pass out the subject + * task's notification value before any bits are modified by the notify function. + * + * @return Dependent on the value of eAction. See the description of the + * eAction parameter. + * + * \defgroup xTaskNotifyIndexed xTaskNotifyIndexed + * \ingroup TaskNotifications + */ +BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, + UBaseType_t uxIndexToNotify, + uint32_t ulValue, + eNotifyAction eAction, + uint32_t * pulPreviousNotificationValue ) PRIVILEGED_FUNCTION; +#define xTaskNotify( xTaskToNotify, ulValue, eAction ) \ + xTaskGenericNotify( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), NULL ) +#define xTaskNotifyIndexed( xTaskToNotify, uxIndexToNotify, ulValue, eAction ) \ + xTaskGenericNotify( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), NULL ) + +/** + * task. h + * @code{c} + * BaseType_t xTaskNotifyAndQueryIndexed( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotifyValue ); + * BaseType_t xTaskNotifyAndQuery( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotifyValue ); + * @endcode + * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * xTaskNotifyAndQueryIndexed() performs the same operation as + * xTaskNotifyIndexed() with the addition that it also returns the subject + * task's prior notification value (the notification value at the time the + * function is called rather than when the function returns) in the additional + * pulPreviousNotifyValue parameter. + * + * xTaskNotifyAndQuery() performs the same operation as xTaskNotify() with the + * addition that it also returns the subject task's prior notification value + * (the notification value as it was at the time the function is called, rather + * than when the function returns) in the additional pulPreviousNotifyValue + * parameter. + * + * \defgroup xTaskNotifyAndQueryIndexed xTaskNotifyAndQueryIndexed + * \ingroup TaskNotifications + */ +#define xTaskNotifyAndQuery( xTaskToNotify, ulValue, eAction, pulPreviousNotifyValue ) \ + xTaskGenericNotify( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), ( pulPreviousNotifyValue ) ) +#define xTaskNotifyAndQueryIndexed( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotifyValue ) \ + xTaskGenericNotify( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotifyValue ) ) + +/** + * task. h + * @code{c} + * BaseType_t xTaskNotifyIndexedFromISR( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify, uint32_t ulValue, eNotifyAction eAction, BaseType_t *pxHigherPriorityTaskWoken ); + * BaseType_t xTaskNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, BaseType_t *pxHigherPriorityTaskWoken ); + * @endcode + * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these + * functions to be available. + * + * A version of xTaskNotifyIndexed() that can be used from an interrupt service + * routine (ISR). + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * Events can be sent to a task using an intermediary object. Examples of such + * objects are queues, semaphores, mutexes and event groups. Task notifications + * are a method of sending an event directly to a task without the need for such + * an intermediary object. + * + * A notification sent to a task can optionally perform an action, such as + * update, overwrite or increment one of the task's notification values. In + * that way task notifications can be used to send data to a task, or be used as + * light weight and fast binary or counting semaphores. + * + * A task can use xTaskNotifyWaitIndexed() to [optionally] block to wait for a + * notification to be pending, or ulTaskNotifyTakeIndexed() to [optionally] block + * to wait for a notification value to have a non-zero value. The task does + * not consume any CPU time while it is in the Blocked state. + * + * A notification sent to a task will remain pending until it is cleared by the + * task calling xTaskNotifyWaitIndexed() or ulTaskNotifyTakeIndexed() (or their + * un-indexed equivalents). If the task was already in the Blocked state to + * wait for a notification when the notification arrives then the task will + * automatically be removed from the Blocked state (unblocked) and the + * notification cleared. + * + * **NOTE** Each notification within the array operates independently - a task + * can only block on one notification within the array at a time and will not be + * unblocked by a notification sent to any other array index. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. xTaskNotifyFromISR() is the original API function, and remains + * backward compatible by always operating on the notification value at index 0 + * within the array. Calling xTaskNotifyFromISR() is equivalent to calling + * xTaskNotifyIndexedFromISR() with the uxIndexToNotify parameter set to 0. + * + * @param uxIndexToNotify The index within the target task's array of + * notification values to which the notification is to be sent. uxIndexToNotify + * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES. xTaskNotifyFromISR() + * does not have this parameter and always sends notifications to index 0. + * + * @param xTaskToNotify The handle of the task being notified. The handle to a + * task can be returned from the xTaskCreate() API function used to create the + * task, and the handle of the currently running task can be obtained by calling + * xTaskGetCurrentTaskHandle(). + * + * @param ulValue Data that can be sent with the notification. How the data is + * used depends on the value of the eAction parameter. + * + * @param eAction Specifies how the notification updates the task's notification + * value, if at all. Valid values for eAction are as follows: + * + * eSetBits - + * The task's notification value is bitwise ORed with ulValue. xTaskNotify() + * always returns pdPASS in this case. + * + * eIncrement - + * The task's notification value is incremented. ulValue is not used and + * xTaskNotify() always returns pdPASS in this case. + * + * eSetValueWithOverwrite - + * The task's notification value is set to the value of ulValue, even if the + * task being notified had not yet processed the previous notification (the + * task already had a notification pending). xTaskNotify() always returns + * pdPASS in this case. + * + * eSetValueWithoutOverwrite - + * If the task being notified did not already have a notification pending then + * the task's notification value is set to ulValue and xTaskNotify() will + * return pdPASS. If the task being notified already had a notification + * pending then no action is performed and pdFAIL is returned. + * + * eNoAction - + * The task receives a notification without its notification value being + * updated. ulValue is not used and xTaskNotify() always returns pdPASS in + * this case. + * + * @param pulPreviousNotificationValue Can be used to pass out the subject + * task's notification value before any bits are modified by the notify function. + * + * @param pxHigherPriorityTaskWoken xTaskNotifyFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the + * task to which the notification was sent to leave the Blocked state, and the + * unblocked task has a priority higher than the currently running task. If + * xTaskNotifyFromISR() sets this value to pdTRUE then a context switch should + * be requested before the interrupt is exited. How a context switch is + * requested from an ISR is dependent on the port - see the documentation page + * for the port in use. + * + * @return Dependent on the value of eAction. See the description of the + * eAction parameter. + * + * \defgroup xTaskNotifyIndexedFromISR xTaskNotifyIndexedFromISR + * \ingroup TaskNotifications + */ +BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, + UBaseType_t uxIndexToNotify, + uint32_t ulValue, + eNotifyAction eAction, + uint32_t * pulPreviousNotificationValue, + BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; +#define xTaskNotifyFromISR( xTaskToNotify, ulValue, eAction, pxHigherPriorityTaskWoken ) \ + xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), NULL, ( pxHigherPriorityTaskWoken ) ) +#define xTaskNotifyIndexedFromISR( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pxHigherPriorityTaskWoken ) \ + xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), NULL, ( pxHigherPriorityTaskWoken ) ) + +/** + * task. h + * @code{c} + * BaseType_t xTaskNotifyAndQueryIndexedFromISR( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken ); + * BaseType_t xTaskNotifyAndQueryFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken ); + * @endcode + * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * xTaskNotifyAndQueryIndexedFromISR() performs the same operation as + * xTaskNotifyIndexedFromISR() with the addition that it also returns the + * subject task's prior notification value (the notification value at the time + * the function is called rather than at the time the function returns) in the + * additional pulPreviousNotifyValue parameter. + * + * xTaskNotifyAndQueryFromISR() performs the same operation as + * xTaskNotifyFromISR() with the addition that it also returns the subject + * task's prior notification value (the notification value at the time the + * function is called rather than at the time the function returns) in the + * additional pulPreviousNotifyValue parameter. + * + * \defgroup xTaskNotifyAndQueryIndexedFromISR xTaskNotifyAndQueryIndexedFromISR + * \ingroup TaskNotifications + */ +#define xTaskNotifyAndQueryIndexedFromISR( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken ) \ + xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotificationValue ), ( pxHigherPriorityTaskWoken ) ) +#define xTaskNotifyAndQueryFromISR( xTaskToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken ) \ + xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), ( pulPreviousNotificationValue ), ( pxHigherPriorityTaskWoken ) ) + +/** + * task. h + * @code{c} + * BaseType_t xTaskNotifyWaitIndexed( UBaseType_t uxIndexToWaitOn, uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ); + * + * BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ); + * @endcode + * + * Waits for a direct to task notification to be pending at a given index within + * an array of direct to task notifications. + * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this + * function to be available. + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * Events can be sent to a task using an intermediary object. Examples of such + * objects are queues, semaphores, mutexes and event groups. Task notifications + * are a method of sending an event directly to a task without the need for such + * an intermediary object. + * + * A notification sent to a task can optionally perform an action, such as + * update, overwrite or increment one of the task's notification values. In + * that way task notifications can be used to send data to a task, or be used as + * light weight and fast binary or counting semaphores. + * + * A notification sent to a task will remain pending until it is cleared by the + * task calling xTaskNotifyWaitIndexed() or ulTaskNotifyTakeIndexed() (or their + * un-indexed equivalents). If the task was already in the Blocked state to + * wait for a notification when the notification arrives then the task will + * automatically be removed from the Blocked state (unblocked) and the + * notification cleared. + * + * A task can use xTaskNotifyWaitIndexed() to [optionally] block to wait for a + * notification to be pending, or ulTaskNotifyTakeIndexed() to [optionally] block + * to wait for a notification value to have a non-zero value. The task does + * not consume any CPU time while it is in the Blocked state. + * + * **NOTE** Each notification within the array operates independently - a task + * can only block on one notification within the array at a time and will not be + * unblocked by a notification sent to any other array index. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. xTaskNotifyWait() is the original API function, and remains backward + * compatible by always operating on the notification value at index 0 in the + * array. Calling xTaskNotifyWait() is equivalent to calling + * xTaskNotifyWaitIndexed() with the uxIndexToWaitOn parameter set to 0. + * + * @param uxIndexToWaitOn The index within the calling task's array of + * notification values on which the calling task will wait for a notification to + * be received. uxIndexToWaitOn must be less than + * configTASK_NOTIFICATION_ARRAY_ENTRIES. xTaskNotifyWait() does + * not have this parameter and always waits for notifications on index 0. + * + * @param ulBitsToClearOnEntry Bits that are set in ulBitsToClearOnEntry value + * will be cleared in the calling task's notification value before the task + * checks to see if any notifications are pending, and optionally blocks if no + * notifications are pending. Setting ulBitsToClearOnEntry to ULONG_MAX (if + * limits.h is included) or 0xffffffffU (if limits.h is not included) will have + * the effect of resetting the task's notification value to 0. Setting + * ulBitsToClearOnEntry to 0 will leave the task's notification value unchanged. + * + * @param ulBitsToClearOnExit If a notification is pending or received before + * the calling task exits the xTaskNotifyWait() function then the task's + * notification value (see the xTaskNotify() API function) is passed out using + * the pulNotificationValue parameter. Then any bits that are set in + * ulBitsToClearOnExit will be cleared in the task's notification value (note + * *pulNotificationValue is set before any bits are cleared). Setting + * ulBitsToClearOnExit to ULONG_MAX (if limits.h is included) or 0xffffffffUL + * (if limits.h is not included) will have the effect of resetting the task's + * notification value to 0 before the function exits. Setting + * ulBitsToClearOnExit to 0 will leave the task's notification value unchanged + * when the function exits (in which case the value passed out in + * pulNotificationValue will match the task's notification value). + * + * @param pulNotificationValue Used to pass the task's notification value out + * of the function. Note the value passed out will not be effected by the + * clearing of any bits caused by ulBitsToClearOnExit being non-zero. + * + * @param xTicksToWait The maximum amount of time that the task should wait in + * the Blocked state for a notification to be received, should a notification + * not already be pending when xTaskNotifyWait() was called. The task + * will not consume any processing time while it is in the Blocked state. This + * is specified in kernel ticks, the macro pdMS_TO_TICKS( value_in_ms ) can be + * used to convert a time specified in milliseconds to a time specified in + * ticks. + * + * @return If a notification was received (including notifications that were + * already pending when xTaskNotifyWait was called) then pdPASS is + * returned. Otherwise pdFAIL is returned. + * + * \defgroup xTaskNotifyWaitIndexed xTaskNotifyWaitIndexed + * \ingroup TaskNotifications + */ +BaseType_t xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn, + uint32_t ulBitsToClearOnEntry, + uint32_t ulBitsToClearOnExit, + uint32_t * pulNotificationValue, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; +#define xTaskNotifyWait( ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait ) \ + xTaskGenericNotifyWait( tskDEFAULT_INDEX_TO_NOTIFY, ( ulBitsToClearOnEntry ), ( ulBitsToClearOnExit ), ( pulNotificationValue ), ( xTicksToWait ) ) +#define xTaskNotifyWaitIndexed( uxIndexToWaitOn, ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait ) \ + xTaskGenericNotifyWait( ( uxIndexToWaitOn ), ( ulBitsToClearOnEntry ), ( ulBitsToClearOnExit ), ( pulNotificationValue ), ( xTicksToWait ) ) + +/** + * task. h + * @code{c} + * BaseType_t xTaskNotifyGiveIndexed( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify ); + * BaseType_t xTaskNotifyGive( TaskHandle_t xTaskToNotify ); + * @endcode + * + * Sends a direct to task notification to a particular index in the target + * task's notification array in a manner similar to giving a counting semaphore. + * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for more details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these + * macros to be available. + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * Events can be sent to a task using an intermediary object. Examples of such + * objects are queues, semaphores, mutexes and event groups. Task notifications + * are a method of sending an event directly to a task without the need for such + * an intermediary object. + * + * A notification sent to a task can optionally perform an action, such as + * update, overwrite or increment one of the task's notification values. In + * that way task notifications can be used to send data to a task, or be used as + * light weight and fast binary or counting semaphores. + * + * xTaskNotifyGiveIndexed() is a helper macro intended for use when task + * notifications are used as light weight and faster binary or counting + * semaphore equivalents. Actual FreeRTOS semaphores are given using the + * xSemaphoreGive() API function, the equivalent action that instead uses a task + * notification is xTaskNotifyGiveIndexed(). + * + * When task notifications are being used as a binary or counting semaphore + * equivalent then the task being notified should wait for the notification + * using the ulTaskNotifyTakeIndexed() API function rather than the + * xTaskNotifyWaitIndexed() API function. + * + * **NOTE** Each notification within the array operates independently - a task + * can only block on one notification within the array at a time and will not be + * unblocked by a notification sent to any other array index. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. xTaskNotifyGive() is the original API function, and remains backward + * compatible by always operating on the notification value at index 0 in the + * array. Calling xTaskNotifyGive() is equivalent to calling + * xTaskNotifyGiveIndexed() with the uxIndexToNotify parameter set to 0. + * + * @param xTaskToNotify The handle of the task being notified. The handle to a + * task can be returned from the xTaskCreate() API function used to create the + * task, and the handle of the currently running task can be obtained by calling + * xTaskGetCurrentTaskHandle(). + * + * @param uxIndexToNotify The index within the target task's array of + * notification values to which the notification is to be sent. uxIndexToNotify + * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES. xTaskNotifyGive() + * does not have this parameter and always sends notifications to index 0. + * + * @return xTaskNotifyGive() is a macro that calls xTaskNotify() with the + * eAction parameter set to eIncrement - so pdPASS is always returned. + * + * \defgroup xTaskNotifyGiveIndexed xTaskNotifyGiveIndexed + * \ingroup TaskNotifications + */ +#define xTaskNotifyGive( xTaskToNotify ) \ + xTaskGenericNotify( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( 0 ), eIncrement, NULL ) +#define xTaskNotifyGiveIndexed( xTaskToNotify, uxIndexToNotify ) \ + xTaskGenericNotify( ( xTaskToNotify ), ( uxIndexToNotify ), ( 0 ), eIncrement, NULL ) + +/** + * task. h + * @code{c} + * void vTaskNotifyGiveIndexedFromISR( TaskHandle_t xTaskHandle, UBaseType_t uxIndexToNotify, BaseType_t *pxHigherPriorityTaskWoken ); + * void vTaskNotifyGiveFromISR( TaskHandle_t xTaskHandle, BaseType_t *pxHigherPriorityTaskWoken ); + * @endcode + * + * A version of xTaskNotifyGiveIndexed() that can be called from an interrupt + * service routine (ISR). + * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for more details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro + * to be available. + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * Events can be sent to a task using an intermediary object. Examples of such + * objects are queues, semaphores, mutexes and event groups. Task notifications + * are a method of sending an event directly to a task without the need for such + * an intermediary object. + * + * A notification sent to a task can optionally perform an action, such as + * update, overwrite or increment one of the task's notification values. In + * that way task notifications can be used to send data to a task, or be used as + * light weight and fast binary or counting semaphores. + * + * vTaskNotifyGiveIndexedFromISR() is intended for use when task notifications + * are used as light weight and faster binary or counting semaphore equivalents. + * Actual FreeRTOS semaphores are given from an ISR using the + * xSemaphoreGiveFromISR() API function, the equivalent action that instead uses + * a task notification is vTaskNotifyGiveIndexedFromISR(). + * + * When task notifications are being used as a binary or counting semaphore + * equivalent then the task being notified should wait for the notification + * using the ulTaskNotifyTakeIndexed() API function rather than the + * xTaskNotifyWaitIndexed() API function. + * + * **NOTE** Each notification within the array operates independently - a task + * can only block on one notification within the array at a time and will not be + * unblocked by a notification sent to any other array index. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. xTaskNotifyFromISR() is the original API function, and remains + * backward compatible by always operating on the notification value at index 0 + * within the array. Calling xTaskNotifyGiveFromISR() is equivalent to calling + * xTaskNotifyGiveIndexedFromISR() with the uxIndexToNotify parameter set to 0. + * + * @param xTaskToNotify The handle of the task being notified. The handle to a + * task can be returned from the xTaskCreate() API function used to create the + * task, and the handle of the currently running task can be obtained by calling + * xTaskGetCurrentTaskHandle(). + * + * @param uxIndexToNotify The index within the target task's array of + * notification values to which the notification is to be sent. uxIndexToNotify + * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES. + * xTaskNotifyGiveFromISR() does not have this parameter and always sends + * notifications to index 0. + * + * @param pxHigherPriorityTaskWoken vTaskNotifyGiveFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the + * task to which the notification was sent to leave the Blocked state, and the + * unblocked task has a priority higher than the currently running task. If + * vTaskNotifyGiveFromISR() sets this value to pdTRUE then a context switch + * should be requested before the interrupt is exited. How a context switch is + * requested from an ISR is dependent on the port - see the documentation page + * for the port in use. + * + * \defgroup vTaskNotifyGiveIndexedFromISR vTaskNotifyGiveIndexedFromISR + * \ingroup TaskNotifications + */ +void vTaskGenericNotifyGiveFromISR( TaskHandle_t xTaskToNotify, + UBaseType_t uxIndexToNotify, + BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; +#define vTaskNotifyGiveFromISR( xTaskToNotify, pxHigherPriorityTaskWoken ) \ + vTaskGenericNotifyGiveFromISR( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( pxHigherPriorityTaskWoken ) ) +#define vTaskNotifyGiveIndexedFromISR( xTaskToNotify, uxIndexToNotify, pxHigherPriorityTaskWoken ) \ + vTaskGenericNotifyGiveFromISR( ( xTaskToNotify ), ( uxIndexToNotify ), ( pxHigherPriorityTaskWoken ) ) + +/** + * task. h + * @code{c} + * uint32_t ulTaskNotifyTakeIndexed( UBaseType_t uxIndexToWaitOn, BaseType_t xClearCountOnExit, TickType_t xTicksToWait ); + * + * uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ); + * @endcode + * + * Waits for a direct to task notification on a particular index in the calling + * task's notification array in a manner similar to taking a counting semaphore. + * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this + * function to be available. + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * Events can be sent to a task using an intermediary object. Examples of such + * objects are queues, semaphores, mutexes and event groups. Task notifications + * are a method of sending an event directly to a task without the need for such + * an intermediary object. + * + * A notification sent to a task can optionally perform an action, such as + * update, overwrite or increment one of the task's notification values. In + * that way task notifications can be used to send data to a task, or be used as + * light weight and fast binary or counting semaphores. + * + * ulTaskNotifyTakeIndexed() is intended for use when a task notification is + * used as a faster and lighter weight binary or counting semaphore alternative. + * Actual FreeRTOS semaphores are taken using the xSemaphoreTake() API function, + * the equivalent action that instead uses a task notification is + * ulTaskNotifyTakeIndexed(). + * + * When a task is using its notification value as a binary or counting semaphore + * other tasks should send notifications to it using the xTaskNotifyGiveIndexed() + * macro, or xTaskNotifyIndex() function with the eAction parameter set to + * eIncrement. + * + * ulTaskNotifyTakeIndexed() can either clear the task's notification value at + * the array index specified by the uxIndexToWaitOn parameter to zero on exit, + * in which case the notification value acts like a binary semaphore, or + * decrement the notification value on exit, in which case the notification + * value acts like a counting semaphore. + * + * A task can use ulTaskNotifyTakeIndexed() to [optionally] block to wait for + * a notification. The task does not consume any CPU time while it is in the + * Blocked state. + * + * Where as xTaskNotifyWaitIndexed() will return when a notification is pending, + * ulTaskNotifyTakeIndexed() will return when the task's notification value is + * not zero. + * + * **NOTE** Each notification within the array operates independently - a task + * can only block on one notification within the array at a time and will not be + * unblocked by a notification sent to any other array index. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. ulTaskNotifyTake() is the original API function, and remains backward + * compatible by always operating on the notification value at index 0 in the + * array. Calling ulTaskNotifyTake() is equivalent to calling + * ulTaskNotifyTakeIndexed() with the uxIndexToWaitOn parameter set to 0. + * + * @param uxIndexToWaitOn The index within the calling task's array of + * notification values on which the calling task will wait for a notification to + * be non-zero. uxIndexToWaitOn must be less than + * configTASK_NOTIFICATION_ARRAY_ENTRIES. xTaskNotifyTake() does + * not have this parameter and always waits for notifications on index 0. + * + * @param xClearCountOnExit if xClearCountOnExit is pdFALSE then the task's + * notification value is decremented when the function exits. In this way the + * notification value acts like a counting semaphore. If xClearCountOnExit is + * not pdFALSE then the task's notification value is cleared to zero when the + * function exits. In this way the notification value acts like a binary + * semaphore. + * + * @param xTicksToWait The maximum amount of time that the task should wait in + * the Blocked state for the task's notification value to be greater than zero, + * should the count not already be greater than zero when + * ulTaskNotifyTake() was called. The task will not consume any processing + * time while it is in the Blocked state. This is specified in kernel ticks, + * the macro pdMS_TO_TICKS( value_in_ms ) can be used to convert a time + * specified in milliseconds to a time specified in ticks. + * + * @return The task's notification count before it is either cleared to zero or + * decremented (see the xClearCountOnExit parameter). + * + * \defgroup ulTaskNotifyTakeIndexed ulTaskNotifyTakeIndexed + * \ingroup TaskNotifications + */ +uint32_t ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; +#define ulTaskNotifyTake( xClearCountOnExit, xTicksToWait ) \ + ulTaskGenericNotifyTake( ( tskDEFAULT_INDEX_TO_NOTIFY ), ( xClearCountOnExit ), ( xTicksToWait ) ) +#define ulTaskNotifyTakeIndexed( uxIndexToWaitOn, xClearCountOnExit, xTicksToWait ) \ + ulTaskGenericNotifyTake( ( uxIndexToWaitOn ), ( xClearCountOnExit ), ( xTicksToWait ) ) + +/** + * task. h + * @code{c} + * BaseType_t xTaskNotifyStateClearIndexed( TaskHandle_t xTask, UBaseType_t uxIndexToCLear ); + * + * BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask ); + * @endcode + * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these + * functions to be available. + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * If a notification is sent to an index within the array of notifications then + * the notification at that index is said to be 'pending' until it is read or + * explicitly cleared by the receiving task. xTaskNotifyStateClearIndexed() + * is the function that clears a pending notification without reading the + * notification value. The notification value at the same array index is not + * altered. Set xTask to NULL to clear the notification state of the calling + * task. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. xTaskNotifyStateClear() is the original API function, and remains + * backward compatible by always operating on the notification value at index 0 + * within the array. Calling xTaskNotifyStateClear() is equivalent to calling + * xTaskNotifyStateClearIndexed() with the uxIndexToNotify parameter set to 0. + * + * @param xTask The handle of the RTOS task that will have a notification state + * cleared. Set xTask to NULL to clear a notification state in the calling + * task. To obtain a task's handle create the task using xTaskCreate() and + * make use of the pxCreatedTask parameter, or create the task using + * xTaskCreateStatic() and store the returned value, or use the task's name in + * a call to xTaskGetHandle(). + * + * @param uxIndexToClear The index within the target task's array of + * notification values to act upon. For example, setting uxIndexToClear to 1 + * will clear the state of the notification at index 1 within the array. + * uxIndexToClear must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES. + * ulTaskNotifyStateClear() does not have this parameter and always acts on the + * notification at index 0. + * + * @return pdTRUE if the task's notification state was set to + * eNotWaitingNotification, otherwise pdFALSE. + * + * \defgroup xTaskNotifyStateClearIndexed xTaskNotifyStateClearIndexed + * \ingroup TaskNotifications + */ +BaseType_t xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) PRIVILEGED_FUNCTION; +#define xTaskNotifyStateClear( xTask ) \ + xTaskGenericNotifyStateClear( ( xTask ), ( tskDEFAULT_INDEX_TO_NOTIFY ) ) +#define xTaskNotifyStateClearIndexed( xTask, uxIndexToClear ) \ + xTaskGenericNotifyStateClear( ( xTask ), ( uxIndexToClear ) ) + +/** + * task. h + * @code{c} + * uint32_t ulTaskNotifyValueClearIndexed( TaskHandle_t xTask, UBaseType_t uxIndexToClear, uint32_t ulBitsToClear ); + * + * uint32_t ulTaskNotifyValueClear( TaskHandle_t xTask, uint32_t ulBitsToClear ); + * @endcode + * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these + * functions to be available. + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * ulTaskNotifyValueClearIndexed() clears the bits specified by the + * ulBitsToClear bit mask in the notification value at array index uxIndexToClear + * of the task referenced by xTask. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. ulTaskNotifyValueClear() is the original API function, and remains + * backward compatible by always operating on the notification value at index 0 + * within the array. Calling ulTaskNotifyValueClear() is equivalent to calling + * ulTaskNotifyValueClearIndexed() with the uxIndexToClear parameter set to 0. + * + * @param xTask The handle of the RTOS task that will have bits in one of its + * notification values cleared. Set xTask to NULL to clear bits in a + * notification value of the calling task. To obtain a task's handle create the + * task using xTaskCreate() and make use of the pxCreatedTask parameter, or + * create the task using xTaskCreateStatic() and store the returned value, or + * use the task's name in a call to xTaskGetHandle(). + * + * @param uxIndexToClear The index within the target task's array of + * notification values in which to clear the bits. uxIndexToClear + * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES. + * ulTaskNotifyValueClear() does not have this parameter and always clears bits + * in the notification value at index 0. + * + * @param ulBitsToClear Bit mask of the bits to clear in the notification value of + * xTask. Set a bit to 1 to clear the corresponding bits in the task's notification + * value. Set ulBitsToClear to 0xffffffff (UINT_MAX on 32-bit architectures) to clear + * the notification value to 0. Set ulBitsToClear to 0 to query the task's + * notification value without clearing any bits. + * + * + * @return The value of the target task's notification value before the bits + * specified by ulBitsToClear were cleared. + * \defgroup ulTaskNotifyValueClear ulTaskNotifyValueClear + * \ingroup TaskNotifications + */ +uint32_t ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION; +#define ulTaskNotifyValueClear( xTask, ulBitsToClear ) \ + ulTaskGenericNotifyValueClear( ( xTask ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulBitsToClear ) ) +#define ulTaskNotifyValueClearIndexed( xTask, uxIndexToClear, ulBitsToClear ) \ + ulTaskGenericNotifyValueClear( ( xTask ), ( uxIndexToClear ), ( ulBitsToClear ) ) + +/** + * task.h + * @code{c} + * void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ); + * @endcode + * + * Capture the current time for future use with xTaskCheckForTimeOut(). + * + * @param pxTimeOut Pointer to a timeout object into which the current time + * is to be captured. The captured time includes the tick count and the number + * of times the tick count has overflowed since the system first booted. + * \defgroup vTaskSetTimeOutState vTaskSetTimeOutState + * \ingroup TaskCtrl + */ +void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION; + +/** + * task.h + * @code{c} + * BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ); + * @endcode + * + * Determines if pxTicksToWait ticks has passed since a time was captured + * using a call to vTaskSetTimeOutState(). The captured time includes the tick + * count and the number of times the tick count has overflowed. + * + * @param pxTimeOut The time status as captured previously using + * vTaskSetTimeOutState. If the timeout has not yet occurred, it is updated + * to reflect the current time status. + * @param pxTicksToWait The number of ticks to check for timeout i.e. if + * pxTicksToWait ticks have passed since pxTimeOut was last updated (either by + * vTaskSetTimeOutState() or xTaskCheckForTimeOut()), the timeout has occurred. + * If the timeout has not occurred, pxTicksToWait is updated to reflect the + * number of remaining ticks. + * + * @return If timeout has occurred, pdTRUE is returned. Otherwise pdFALSE is + * returned and pxTicksToWait is updated to reflect the number of remaining + * ticks. + * + * @see https://www.FreeRTOS.org/xTaskCheckForTimeOut.html + * + * Example Usage: + * @code{c} + * // Driver library function used to receive uxWantedBytes from an Rx buffer + * // that is filled by a UART interrupt. If there are not enough bytes in the + * // Rx buffer then the task enters the Blocked state until it is notified that + * // more data has been placed into the buffer. If there is still not enough + * // data then the task re-enters the Blocked state, and xTaskCheckForTimeOut() + * // is used to re-calculate the Block time to ensure the total amount of time + * // spent in the Blocked state does not exceed MAX_TIME_TO_WAIT. This + * // continues until either the buffer contains at least uxWantedBytes bytes, + * // or the total amount of time spent in the Blocked state reaches + * // MAX_TIME_TO_WAIT - at which point the task reads however many bytes are + * // available up to a maximum of uxWantedBytes. + * + * size_t xUART_Receive( uint8_t *pucBuffer, size_t uxWantedBytes ) + * { + * size_t uxReceived = 0; + * TickType_t xTicksToWait = MAX_TIME_TO_WAIT; + * TimeOut_t xTimeOut; + * + * // Initialize xTimeOut. This records the time at which this function + * // was entered. + * vTaskSetTimeOutState( &xTimeOut ); + * + * // Loop until the buffer contains the wanted number of bytes, or a + * // timeout occurs. + * while( UART_bytes_in_rx_buffer( pxUARTInstance ) < uxWantedBytes ) + * { + * // The buffer didn't contain enough data so this task is going to + * // enter the Blocked state. Adjusting xTicksToWait to account for + * // any time that has been spent in the Blocked state within this + * // function so far to ensure the total amount of time spent in the + * // Blocked state does not exceed MAX_TIME_TO_WAIT. + * if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) != pdFALSE ) + * { + * //Timed out before the wanted number of bytes were available, + * // exit the loop. + * break; + * } + * + * // Wait for a maximum of xTicksToWait ticks to be notified that the + * // receive interrupt has placed more data into the buffer. + * ulTaskNotifyTake( pdTRUE, xTicksToWait ); + * } + * + * // Attempt to read uxWantedBytes from the receive buffer into pucBuffer. + * // The actual number of bytes read (which might be less than + * // uxWantedBytes) is returned. + * uxReceived = UART_read_from_receive_buffer( pxUARTInstance, + * pucBuffer, + * uxWantedBytes ); + * + * return uxReceived; + * } + * @endcode + * \defgroup xTaskCheckForTimeOut xTaskCheckForTimeOut + * \ingroup TaskCtrl + */ +BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) PRIVILEGED_FUNCTION; + +/** + * task.h + * @code{c} + * BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp ); + * @endcode + * + * This function corrects the tick count value after the application code has held + * interrupts disabled for an extended period resulting in tick interrupts having + * been missed. + * + * This function is similar to vTaskStepTick(), however, unlike + * vTaskStepTick(), xTaskCatchUpTicks() may move the tick count forward past a + * time at which a task should be removed from the blocked state. That means + * tasks may have to be removed from the blocked state as the tick count is + * moved. + * + * @param xTicksToCatchUp The number of tick interrupts that have been missed due to + * interrupts being disabled. Its value is not computed automatically, so must be + * computed by the application writer. + * + * @return pdTRUE if moving the tick count forward resulted in a task leaving the + * blocked state and a context switch being performed. Otherwise pdFALSE. + * + * \defgroup xTaskCatchUpTicks xTaskCatchUpTicks + * \ingroup TaskCtrl + */ +BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) PRIVILEGED_FUNCTION; + +/** + * task.h + * @code{c} + * void vTaskResetState( void ); + * @endcode + * + * This function resets the internal state of the task. It must be called by the + * application before restarting the scheduler. + * + * \defgroup vTaskResetState vTaskResetState + * \ingroup SchedulerControl + */ +void vTaskResetState( void ) PRIVILEGED_FUNCTION; + + +/*----------------------------------------------------------- +* SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES +*----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES == 1 ) + #define taskYIELD_WITHIN_API() portYIELD_WITHIN_API() +#else /* #if ( configNUMBER_OF_CORES == 1 ) */ + #define taskYIELD_WITHIN_API() vTaskYieldWithinAPI() +#endif /* #if ( configNUMBER_OF_CORES == 1 ) */ + +/* + * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY + * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS + * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. + * + * Called from the real time kernel tick (either preemptive or cooperative), + * this increments the tick count and checks if any tasks that are blocked + * for a finite period required removing from a blocked list and placing on + * a ready list. If a non-zero value is returned then a context switch is + * required because either: + * + A task was removed from a blocked list because its timeout had expired, + * or + * + Time slicing is in use and there is a task of equal priority to the + * currently running task. + */ +BaseType_t xTaskIncrementTick( void ) PRIVILEGED_FUNCTION; + +/* + * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN + * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. + * + * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED. + * + * Removes the calling task from the ready list and places it both + * on the list of tasks waiting for a particular event, and the + * list of delayed tasks. The task will be removed from both lists + * and replaced on the ready list should either the event occur (and + * there be no higher priority tasks waiting on the same event) or + * the delay period expires. + * + * The 'unordered' version replaces the event list item value with the + * xItemValue value, and inserts the list item at the end of the list. + * + * The 'ordered' version uses the existing event list item value (which is the + * owning task's priority) to insert the list item into the event list in task + * priority order. + * + * @param pxEventList The list containing tasks that are blocked waiting + * for the event to occur. + * + * @param xItemValue The item value to use for the event list item when the + * event list is not ordered by task priority. + * + * @param xTicksToWait The maximum amount of time that the task should wait + * for the event to occur. This is specified in kernel ticks, the constant + * portTICK_PERIOD_MS can be used to convert kernel ticks into a real time + * period. + */ +void vTaskPlaceOnEventList( List_t * const pxEventList, + const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; +void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, + const TickType_t xItemValue, + const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/* + * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN + * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. + * + * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED. + * + * This function performs nearly the same function as vTaskPlaceOnEventList(). + * The difference being that this function does not permit tasks to block + * indefinitely, whereas vTaskPlaceOnEventList() does. + * + */ +void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, + TickType_t xTicksToWait, + const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION; + +/* + * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN + * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. + * + * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED. + * + * Removes a task from both the specified event list and the list of blocked + * tasks, and places it on a ready queue. + * + * xTaskRemoveFromEventList()/vTaskRemoveFromUnorderedEventList() will be called + * if either an event occurs to unblock a task, or the block timeout period + * expires. + * + * xTaskRemoveFromEventList() is used when the event list is in task priority + * order. It removes the list item from the head of the event list as that will + * have the highest priority owning task of all the tasks on the event list. + * vTaskRemoveFromUnorderedEventList() is used when the event list is not + * ordered and the event list items hold something other than the owning tasks + * priority. In this case the event list item value is updated to the value + * passed in the xItemValue parameter. + * + * @return pdTRUE if the task being removed has a higher priority than the task + * making the call, otherwise pdFALSE. + */ +BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) PRIVILEGED_FUNCTION; +void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, + const TickType_t xItemValue ) PRIVILEGED_FUNCTION; + +/* + * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY + * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS + * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. + * + * Sets the pointer to the current TCB to the TCB of the highest priority task + * that is ready to run. + */ +#if ( configNUMBER_OF_CORES == 1 ) + portDONT_DISCARD void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION; +#else + portDONT_DISCARD void vTaskSwitchContext( BaseType_t xCoreID ) PRIVILEGED_FUNCTION; +#endif + +/* + * THESE FUNCTIONS MUST NOT BE USED FROM APPLICATION CODE. THEY ARE USED BY + * THE EVENT BITS MODULE. + */ +TickType_t uxTaskResetEventItemValue( void ) PRIVILEGED_FUNCTION; + +/* + * Return the handle of the calling task. + */ +TaskHandle_t xTaskGetCurrentTaskHandle( void ) PRIVILEGED_FUNCTION; + +/* + * Return the handle of the task running on specified core. + */ +TaskHandle_t xTaskGetCurrentTaskHandleForCore( BaseType_t xCoreID ) PRIVILEGED_FUNCTION; + +/* + * Shortcut used by the queue implementation to prevent unnecessary call to + * taskYIELD(); + */ +void vTaskMissedYield( void ) PRIVILEGED_FUNCTION; + +/* + * Returns the scheduler state as taskSCHEDULER_RUNNING, + * taskSCHEDULER_NOT_STARTED or taskSCHEDULER_SUSPENDED. + */ +BaseType_t xTaskGetSchedulerState( void ) PRIVILEGED_FUNCTION; + +/* + * Raises the priority of the mutex holder to that of the calling task should + * the mutex holder have a priority less than the calling task. + */ +BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION; + +/* + * Set the priority of a task back to its proper priority in the case that it + * inherited a higher priority while it was holding a semaphore. + */ +BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION; + +/* + * If a higher priority task attempting to obtain a mutex caused a lower + * priority task to inherit the higher priority task's priority - but the higher + * priority task then timed out without obtaining the mutex, then the lower + * priority task will disinherit the priority again - but only down as far as + * the highest priority task that is still waiting for the mutex (if there were + * more than one task waiting for the mutex). + */ +void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, + UBaseType_t uxHighestPriorityWaitingTask ) PRIVILEGED_FUNCTION; + +/* + * Get the uxTaskNumber assigned to the task referenced by the xTask parameter. + */ +#if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; +#endif + +/* + * Set the uxTaskNumber of the task referenced by the xTask parameter to + * uxHandle. + */ +#if ( configUSE_TRACE_FACILITY == 1 ) + void vTaskSetTaskNumber( TaskHandle_t xTask, + const UBaseType_t uxHandle ) PRIVILEGED_FUNCTION; +#endif + +/* + * Only available when configUSE_TICKLESS_IDLE is set to 1. + * If tickless mode is being used, or a low power mode is implemented, then + * the tick interrupt will not execute during idle periods. When this is the + * case, the tick count value maintained by the scheduler needs to be kept up + * to date with the actual execution time by being skipped forward by a time + * equal to the idle period. + */ +#if ( configUSE_TICKLESS_IDLE != 0 ) + void vTaskStepTick( TickType_t xTicksToJump ) PRIVILEGED_FUNCTION; +#endif + +/* + * Only available when configUSE_TICKLESS_IDLE is set to 1. + * Provided for use within portSUPPRESS_TICKS_AND_SLEEP() to allow the port + * specific sleep function to determine if it is ok to proceed with the sleep, + * and if it is ok to proceed, if it is ok to sleep indefinitely. + * + * This function is necessary because portSUPPRESS_TICKS_AND_SLEEP() is only + * called with the scheduler suspended, not from within a critical section. It + * is therefore possible for an interrupt to request a context switch between + * portSUPPRESS_TICKS_AND_SLEEP() and the low power mode actually being + * entered. eTaskConfirmSleepModeStatus() should be called from a short + * critical section between the timer being stopped and the sleep mode being + * entered to ensure it is ok to proceed into the sleep mode. + */ +#if ( configUSE_TICKLESS_IDLE != 0 ) + eSleepModeStatus eTaskConfirmSleepModeStatus( void ) PRIVILEGED_FUNCTION; +#endif + +/* + * For internal use only. Increment the mutex held count when a mutex is + * taken and return the handle of the task that has taken the mutex. + */ +TaskHandle_t pvTaskIncrementMutexHeldCount( void ) PRIVILEGED_FUNCTION; + +/* + * For internal use only. Same as vTaskSetTimeOutState(), but without a critical + * section. + */ +void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION; + +/* + * For internal use only. Same as portYIELD_WITHIN_API() in single core FreeRTOS. + * For SMP this is not defined by the port. + */ +#if ( configNUMBER_OF_CORES > 1 ) + void vTaskYieldWithinAPI( void ); +#endif + +/* + * This function is only intended for use when implementing a port of the scheduler + * and is only available when portCRITICAL_NESTING_IN_TCB is set to 1 or configNUMBER_OF_CORES + * is greater than 1. This function can be used in the implementation of portENTER_CRITICAL + * if port wants to maintain critical nesting count in TCB in single core FreeRTOS. + * It should be used in the implementation of portENTER_CRITICAL if port is running a + * multiple core FreeRTOS. + */ +#if ( ( portCRITICAL_NESTING_IN_TCB == 1 ) || ( configNUMBER_OF_CORES > 1 ) ) + void vTaskEnterCritical( void ); +#endif + +/* + * This function is only intended for use when implementing a port of the scheduler + * and is only available when portCRITICAL_NESTING_IN_TCB is set to 1 or configNUMBER_OF_CORES + * is greater than 1. This function can be used in the implementation of portEXIT_CRITICAL + * if port wants to maintain critical nesting count in TCB in single core FreeRTOS. + * It should be used in the implementation of portEXIT_CRITICAL if port is running a + * multiple core FreeRTOS. + */ +#if ( ( portCRITICAL_NESTING_IN_TCB == 1 ) || ( configNUMBER_OF_CORES > 1 ) ) + void vTaskExitCritical( void ); +#endif + +/* + * This function is only intended for use when implementing a port of the scheduler + * and is only available when configNUMBER_OF_CORES is greater than 1. This function + * should be used in the implementation of portENTER_CRITICAL_FROM_ISR if port is + * running a multiple core FreeRTOS. + */ +#if ( configNUMBER_OF_CORES > 1 ) + UBaseType_t vTaskEnterCriticalFromISR( void ); +#endif + +/* + * This function is only intended for use when implementing a port of the scheduler + * and is only available when configNUMBER_OF_CORES is greater than 1. This function + * should be used in the implementation of portEXIT_CRITICAL_FROM_ISR if port is + * running a multiple core FreeRTOS. + */ +#if ( configNUMBER_OF_CORES > 1 ) + void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus ); +#endif + +#if ( portUSING_MPU_WRAPPERS == 1 ) + +/* + * For internal use only. Get MPU settings associated with a task. + */ + xMPU_SETTINGS * xTaskGetMPUSettings( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +#endif /* portUSING_MPU_WRAPPERS */ + + +#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + +/* + * For internal use only. Grant/Revoke a task's access to a kernel object. + */ + void vGrantAccessToKernelObject( TaskHandle_t xExternalTaskHandle, + int32_t lExternalKernelObjectHandle ) PRIVILEGED_FUNCTION; + void vRevokeAccessToKernelObject( TaskHandle_t xExternalTaskHandle, + int32_t lExternalKernelObjectHandle ) PRIVILEGED_FUNCTION; + +/* + * For internal use only. Grant/Revoke a task's access to a kernel object. + */ + void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) PRIVILEGED_FUNCTION; + void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) PRIVILEGED_FUNCTION; + +#endif /* #if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ +#endif /* INC_TASK_H */ diff --git a/include/timers.h b/include/timers.h new file mode 100644 index 000000000..7d99d3536 --- /dev/null +++ b/include/timers.h @@ -0,0 +1,1434 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef TIMERS_H +#define TIMERS_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include timers.h" +#endif + +#include "task.h" + + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- +* MACROS AND DEFINITIONS +*----------------------------------------------------------*/ + +/* IDs for commands that can be sent/received on the timer queue. These are to + * be used solely through the macros that make up the public software timer API, + * as defined below. The commands that are sent from interrupts must use the + * highest numbers as tmrFIRST_FROM_ISR_COMMAND is used to determine if the task + * or interrupt version of the queue send function should be used. */ +#define tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR ( ( BaseType_t ) -2 ) +#define tmrCOMMAND_EXECUTE_CALLBACK ( ( BaseType_t ) -1 ) +#define tmrCOMMAND_START_DONT_TRACE ( ( BaseType_t ) 0 ) +#define tmrCOMMAND_START ( ( BaseType_t ) 1 ) +#define tmrCOMMAND_RESET ( ( BaseType_t ) 2 ) +#define tmrCOMMAND_STOP ( ( BaseType_t ) 3 ) +#define tmrCOMMAND_CHANGE_PERIOD ( ( BaseType_t ) 4 ) +#define tmrCOMMAND_DELETE ( ( BaseType_t ) 5 ) + +#define tmrFIRST_FROM_ISR_COMMAND ( ( BaseType_t ) 6 ) +#define tmrCOMMAND_START_FROM_ISR ( ( BaseType_t ) 6 ) +#define tmrCOMMAND_RESET_FROM_ISR ( ( BaseType_t ) 7 ) +#define tmrCOMMAND_STOP_FROM_ISR ( ( BaseType_t ) 8 ) +#define tmrCOMMAND_CHANGE_PERIOD_FROM_ISR ( ( BaseType_t ) 9 ) + + +/** + * Type by which software timers are referenced. For example, a call to + * xTimerCreate() returns an TimerHandle_t variable that can then be used to + * reference the subject timer in calls to other software timer API functions + * (for example, xTimerStart(), xTimerReset(), etc.). + */ +struct tmrTimerControl; /* The old naming convention is used to prevent breaking kernel aware debuggers. */ +typedef struct tmrTimerControl * TimerHandle_t; + +/* + * Defines the prototype to which timer callback functions must conform. + */ +typedef void (* TimerCallbackFunction_t)( TimerHandle_t xTimer ); + +/* + * Defines the prototype to which functions used with the + * xTimerPendFunctionCallFromISR() function must conform. + */ +typedef void (* PendedFunction_t)( void * arg1, + uint32_t arg2 ); + +/** + * TimerHandle_t xTimerCreate( const char * const pcTimerName, + * TickType_t xTimerPeriodInTicks, + * BaseType_t xAutoReload, + * void * pvTimerID, + * TimerCallbackFunction_t pxCallbackFunction ); + * + * Creates a new software timer instance, and returns a handle by which the + * created software timer can be referenced. + * + * Internally, within the FreeRTOS implementation, software timers use a block + * of memory, in which the timer data structure is stored. If a software timer + * is created using xTimerCreate() then the required memory is automatically + * dynamically allocated inside the xTimerCreate() function. (see + * https://www.FreeRTOS.org/a00111.html). If a software timer is created using + * xTimerCreateStatic() then the application writer must provide the memory that + * will get used by the software timer. xTimerCreateStatic() therefore allows a + * software timer to be created without using any dynamic memory allocation. + * + * Timers are created in the dormant state. The xTimerStart(), xTimerReset(), + * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and + * xTimerChangePeriodFromISR() API functions can all be used to transition a + * timer into the active state. + * + * @param pcTimerName A text name that is assigned to the timer. This is done + * purely to assist debugging. The kernel itself only ever references a timer + * by its handle, and never by its name. + * + * @param xTimerPeriodInTicks The timer period. The time is defined in tick + * periods so the constant portTICK_PERIOD_MS can be used to convert a time that + * has been specified in milliseconds. For example, if the timer must expire + * after 100 ticks, then xTimerPeriodInTicks should be set to 100. + * Alternatively, if the timer must expire after 500ms, then xPeriod can be set + * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or + * equal to 1000. Time timer period must be greater than 0. + * + * @param xAutoReload If xAutoReload is set to pdTRUE then the timer will + * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter. + * If xAutoReload is set to pdFALSE then the timer will be a one-shot timer and + * enter the dormant state after it expires. + * + * @param pvTimerID An identifier that is assigned to the timer being created. + * Typically this would be used in the timer callback function to identify which + * timer expired when the same callback function is assigned to more than one + * timer. + * + * @param pxCallbackFunction The function to call when the timer expires. + * Callback functions must have the prototype defined by TimerCallbackFunction_t, + * which is "void vCallbackFunction( TimerHandle_t xTimer );". + * + * @return If the timer is successfully created then a handle to the newly + * created timer is returned. If the timer cannot be created because there is + * insufficient FreeRTOS heap remaining to allocate the timer + * structures then NULL is returned. + * + * Example usage: + * @verbatim + * #define NUM_TIMERS 5 + * + * // An array to hold handles to the created timers. + * TimerHandle_t xTimers[ NUM_TIMERS ]; + * + * // An array to hold a count of the number of times each timer expires. + * int32_t lExpireCounters[ NUM_TIMERS ] = { 0 }; + * + * // Define a callback function that will be used by multiple timer instances. + * // The callback function does nothing but count the number of times the + * // associated timer expires, and stop the timer once the timer has expired + * // 10 times. + * void vTimerCallback( TimerHandle_t pxTimer ) + * { + * int32_t lArrayIndex; + * const int32_t xMaxExpiryCountBeforeStopping = 10; + * + * // Optionally do something if the pxTimer parameter is NULL. + * configASSERT( pxTimer ); + * + * // Which timer expired? + * lArrayIndex = ( int32_t ) pvTimerGetTimerID( pxTimer ); + * + * // Increment the number of times that pxTimer has expired. + * lExpireCounters[ lArrayIndex ] += 1; + * + * // If the timer has expired 10 times then stop it from running. + * if( lExpireCounters[ lArrayIndex ] == xMaxExpiryCountBeforeStopping ) + * { + * // Do not use a block time if calling a timer API function from a + * // timer callback function, as doing so could cause a deadlock! + * xTimerStop( pxTimer, 0 ); + * } + * } + * + * void main( void ) + * { + * int32_t x; + * + * // Create then start some timers. Starting the timers before the scheduler + * // has been started means the timers will start running immediately that + * // the scheduler starts. + * for( x = 0; x < NUM_TIMERS; x++ ) + * { + * xTimers[ x ] = xTimerCreate( "Timer", // Just a text name, not used by the kernel. + * ( 100 * ( x + 1 ) ), // The timer period in ticks. + * pdTRUE, // The timers will auto-reload themselves when they expire. + * ( void * ) x, // Assign each timer a unique id equal to its array index. + * vTimerCallback // Each timer calls the same callback when it expires. + * ); + * + * if( xTimers[ x ] == NULL ) + * { + * // The timer was not created. + * } + * else + * { + * // Start the timer. No block time is specified, and even if one was + * // it would be ignored because the scheduler has not yet been + * // started. + * if( xTimerStart( xTimers[ x ], 0 ) != pdPASS ) + * { + * // The timer could not be set into the Active state. + * } + * } + * } + * + * // ... + * // Create tasks here. + * // ... + * + * // Starting the scheduler will start the timers running as they have already + * // been set into the active state. + * vTaskStartScheduler(); + * + * // Should not reach here. + * for( ;; ); + * } + * @endverbatim + */ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + TimerHandle_t xTimerCreate( const char * const pcTimerName, + const TickType_t xTimerPeriodInTicks, + const BaseType_t xAutoReload, + void * const pvTimerID, + TimerCallbackFunction_t pxCallbackFunction ) PRIVILEGED_FUNCTION; +#endif + +/** + * TimerHandle_t xTimerCreateStatic(const char * const pcTimerName, + * TickType_t xTimerPeriodInTicks, + * BaseType_t xAutoReload, + * void * pvTimerID, + * TimerCallbackFunction_t pxCallbackFunction, + * StaticTimer_t *pxTimerBuffer ); + * + * Creates a new software timer instance, and returns a handle by which the + * created software timer can be referenced. + * + * Internally, within the FreeRTOS implementation, software timers use a block + * of memory, in which the timer data structure is stored. If a software timer + * is created using xTimerCreate() then the required memory is automatically + * dynamically allocated inside the xTimerCreate() function. (see + * https://www.FreeRTOS.org/a00111.html). If a software timer is created using + * xTimerCreateStatic() then the application writer must provide the memory that + * will get used by the software timer. xTimerCreateStatic() therefore allows a + * software timer to be created without using any dynamic memory allocation. + * + * Timers are created in the dormant state. The xTimerStart(), xTimerReset(), + * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and + * xTimerChangePeriodFromISR() API functions can all be used to transition a + * timer into the active state. + * + * @param pcTimerName A text name that is assigned to the timer. This is done + * purely to assist debugging. The kernel itself only ever references a timer + * by its handle, and never by its name. + * + * @param xTimerPeriodInTicks The timer period. The time is defined in tick + * periods so the constant portTICK_PERIOD_MS can be used to convert a time that + * has been specified in milliseconds. For example, if the timer must expire + * after 100 ticks, then xTimerPeriodInTicks should be set to 100. + * Alternatively, if the timer must expire after 500ms, then xPeriod can be set + * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or + * equal to 1000. The timer period must be greater than 0. + * + * @param xAutoReload If xAutoReload is set to pdTRUE then the timer will + * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter. + * If xAutoReload is set to pdFALSE then the timer will be a one-shot timer and + * enter the dormant state after it expires. + * + * @param pvTimerID An identifier that is assigned to the timer being created. + * Typically this would be used in the timer callback function to identify which + * timer expired when the same callback function is assigned to more than one + * timer. + * + * @param pxCallbackFunction The function to call when the timer expires. + * Callback functions must have the prototype defined by TimerCallbackFunction_t, + * which is "void vCallbackFunction( TimerHandle_t xTimer );". + * + * @param pxTimerBuffer Must point to a variable of type StaticTimer_t, which + * will be then be used to hold the software timer's data structures, removing + * the need for the memory to be allocated dynamically. + * + * @return If the timer is created then a handle to the created timer is + * returned. If pxTimerBuffer was NULL then NULL is returned. + * + * Example usage: + * @verbatim + * + * // The buffer used to hold the software timer's data structure. + * static StaticTimer_t xTimerBuffer; + * + * // A variable that will be incremented by the software timer's callback + * // function. + * UBaseType_t uxVariableToIncrement = 0; + * + * // A software timer callback function that increments a variable passed to + * // it when the software timer was created. After the 5th increment the + * // callback function stops the software timer. + * static void prvTimerCallback( TimerHandle_t xExpiredTimer ) + * { + * UBaseType_t *puxVariableToIncrement; + * BaseType_t xReturned; + * + * // Obtain the address of the variable to increment from the timer ID. + * puxVariableToIncrement = ( UBaseType_t * ) pvTimerGetTimerID( xExpiredTimer ); + * + * // Increment the variable to show the timer callback has executed. + * ( *puxVariableToIncrement )++; + * + * // If this callback has executed the required number of times, stop the + * // timer. + * if( *puxVariableToIncrement == 5 ) + * { + * // This is called from a timer callback so must not block. + * xTimerStop( xExpiredTimer, staticDONT_BLOCK ); + * } + * } + * + * + * void main( void ) + * { + * // Create the software time. xTimerCreateStatic() has an extra parameter + * // than the normal xTimerCreate() API function. The parameter is a pointer + * // to the StaticTimer_t structure that will hold the software timer + * // structure. If the parameter is passed as NULL then the structure will be + * // allocated dynamically, just as if xTimerCreate() had been called. + * xTimer = xTimerCreateStatic( "T1", // Text name for the task. Helps debugging only. Not used by FreeRTOS. + * xTimerPeriod, // The period of the timer in ticks. + * pdTRUE, // This is an auto-reload timer. + * ( void * ) &uxVariableToIncrement, // A variable incremented by the software timer's callback function + * prvTimerCallback, // The function to execute when the timer expires. + * &xTimerBuffer ); // The buffer that will hold the software timer structure. + * + * // The scheduler has not started yet so a block time is not used. + * xReturned = xTimerStart( xTimer, 0 ); + * + * // ... + * // Create tasks here. + * // ... + * + * // Starting the scheduler will start the timers running as they have already + * // been set into the active state. + * vTaskStartScheduler(); + * + * // Should not reach here. + * for( ;; ); + * } + * @endverbatim + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + TimerHandle_t xTimerCreateStatic( const char * const pcTimerName, + const TickType_t xTimerPeriodInTicks, + const BaseType_t xAutoReload, + void * const pvTimerID, + TimerCallbackFunction_t pxCallbackFunction, + StaticTimer_t * pxTimerBuffer ) PRIVILEGED_FUNCTION; +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +/** + * void *pvTimerGetTimerID( TimerHandle_t xTimer ); + * + * Returns the ID assigned to the timer. + * + * IDs are assigned to timers using the pvTimerID parameter of the call to + * xTimerCreated() that was used to create the timer, and by calling the + * vTimerSetTimerID() API function. + * + * If the same callback function is assigned to multiple timers then the timer + * ID can be used as time specific (timer local) storage. + * + * @param xTimer The timer being queried. + * + * @return The ID assigned to the timer being queried. + * + * Example usage: + * + * See the xTimerCreate() API function example usage scenario. + */ +void * pvTimerGetTimerID( const TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; + +/** + * void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ); + * + * Sets the ID assigned to the timer. + * + * IDs are assigned to timers using the pvTimerID parameter of the call to + * xTimerCreated() that was used to create the timer. + * + * If the same callback function is assigned to multiple timers then the timer + * ID can be used as time specific (timer local) storage. + * + * @param xTimer The timer being updated. + * + * @param pvNewID The ID to assign to the timer. + * + * Example usage: + * + * See the xTimerCreate() API function example usage scenario. + */ +void vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) PRIVILEGED_FUNCTION; + +/** + * BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ); + * + * Queries a timer to see if it is active or dormant. + * + * A timer will be dormant if: + * 1) It has been created but not started, or + * 2) It is an expired one-shot timer that has not been restarted. + * + * Timers are created in the dormant state. The xTimerStart(), xTimerReset(), + * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and + * xTimerChangePeriodFromISR() API functions can all be used to transition a timer into the + * active state. + * + * @param xTimer The timer being queried. + * + * @return pdFALSE will be returned if the timer is dormant. A value other than + * pdFALSE will be returned if the timer is active. + * + * Example usage: + * @verbatim + * // This function assumes xTimer has already been created. + * void vAFunction( TimerHandle_t xTimer ) + * { + * if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )" + * { + * // xTimer is active, do something. + * } + * else + * { + * // xTimer is not active, do something else. + * } + * } + * @endverbatim + */ +BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; + +/** + * TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ); + * + * Simply returns the handle of the timer service/daemon task. It it not valid + * to call xTimerGetTimerDaemonTaskHandle() before the scheduler has been started. + */ +TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ) PRIVILEGED_FUNCTION; + +/** + * BaseType_t xTimerStart( TimerHandle_t xTimer, TickType_t xTicksToWait ); + * + * Timer functionality is provided by a timer service/daemon task. Many of the + * public FreeRTOS timer API functions send commands to the timer service task + * through a queue called the timer command queue. The timer command queue is + * private to the kernel itself and is not directly accessible to application + * code. The length of the timer command queue is set by the + * configTIMER_QUEUE_LENGTH configuration constant. + * + * xTimerStart() starts a timer that was previously created using the + * xTimerCreate() API function. If the timer had already been started and was + * already in the active state, then xTimerStart() has equivalent functionality + * to the xTimerReset() API function. + * + * Starting a timer ensures the timer is in the active state. If the timer + * is not stopped, deleted, or reset in the mean time, the callback function + * associated with the timer will get called 'n' ticks after xTimerStart() was + * called, where 'n' is the timers defined period. + * + * It is valid to call xTimerStart() before the scheduler has been started, but + * when this is done the timer will not actually start until the scheduler is + * started, and the timers expiry time will be relative to when the scheduler is + * started, not relative to when xTimerStart() was called. + * + * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStart() + * to be available. + * + * @param xTimer The handle of the timer being started/restarted. + * + * @param xTicksToWait Specifies the time, in ticks, that the calling task should + * be held in the Blocked state to wait for the start command to be successfully + * sent to the timer command queue, should the queue already be full when + * xTimerStart() was called. xTicksToWait is ignored if xTimerStart() is called + * before the scheduler is started. + * + * @return pdFAIL will be returned if the start command could not be sent to + * the timer command queue even after xTicksToWait ticks had passed. pdPASS will + * be returned if the command was successfully sent to the timer command queue. + * When the command is actually processed will depend on the priority of the + * timer service/daemon task relative to other tasks in the system, although the + * timers expiry time is relative to when xTimerStart() is actually called. The + * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY + * configuration constant. + * + * Example usage: + * + * See the xTimerCreate() API function example usage scenario. + * + */ +#define xTimerStart( xTimer, xTicksToWait ) \ + xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) ) + +/** + * BaseType_t xTimerStop( TimerHandle_t xTimer, TickType_t xTicksToWait ); + * + * Timer functionality is provided by a timer service/daemon task. Many of the + * public FreeRTOS timer API functions send commands to the timer service task + * through a queue called the timer command queue. The timer command queue is + * private to the kernel itself and is not directly accessible to application + * code. The length of the timer command queue is set by the + * configTIMER_QUEUE_LENGTH configuration constant. + * + * xTimerStop() stops a timer that was previously started using either of the + * The xTimerStart(), xTimerReset(), xTimerStartFromISR(), xTimerResetFromISR(), + * xTimerChangePeriod() or xTimerChangePeriodFromISR() API functions. + * + * Stopping a timer ensures the timer is not in the active state. + * + * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStop() + * to be available. + * + * @param xTimer The handle of the timer being stopped. + * + * @param xTicksToWait Specifies the time, in ticks, that the calling task should + * be held in the Blocked state to wait for the stop command to be successfully + * sent to the timer command queue, should the queue already be full when + * xTimerStop() was called. xTicksToWait is ignored if xTimerStop() is called + * before the scheduler is started. + * + * @return pdFAIL will be returned if the stop command could not be sent to + * the timer command queue even after xTicksToWait ticks had passed. pdPASS will + * be returned if the command was successfully sent to the timer command queue. + * When the command is actually processed will depend on the priority of the + * timer service/daemon task relative to other tasks in the system. The timer + * service/daemon task priority is set by the configTIMER_TASK_PRIORITY + * configuration constant. + * + * Example usage: + * + * See the xTimerCreate() API function example usage scenario. + * + */ +#define xTimerStop( xTimer, xTicksToWait ) \ + xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP, 0U, NULL, ( xTicksToWait ) ) + +/** + * BaseType_t xTimerChangePeriod( TimerHandle_t xTimer, + * TickType_t xNewPeriod, + * TickType_t xTicksToWait ); + * + * Timer functionality is provided by a timer service/daemon task. Many of the + * public FreeRTOS timer API functions send commands to the timer service task + * through a queue called the timer command queue. The timer command queue is + * private to the kernel itself and is not directly accessible to application + * code. The length of the timer command queue is set by the + * configTIMER_QUEUE_LENGTH configuration constant. + * + * xTimerChangePeriod() changes the period of a timer that was previously + * created using the xTimerCreate() API function. + * + * xTimerChangePeriod() can be called to change the period of an active or + * dormant state timer. + * + * The configUSE_TIMERS configuration constant must be set to 1 for + * xTimerChangePeriod() to be available. + * + * @param xTimer The handle of the timer that is having its period changed. + * + * @param xNewPeriod The new period for xTimer. Timer periods are specified in + * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time + * that has been specified in milliseconds. For example, if the timer must + * expire after 100 ticks, then xNewPeriod should be set to 100. Alternatively, + * if the timer must expire after 500ms, then xNewPeriod can be set to + * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than + * or equal to 1000. + * + * @param xTicksToWait Specifies the time, in ticks, that the calling task should + * be held in the Blocked state to wait for the change period command to be + * successfully sent to the timer command queue, should the queue already be + * full when xTimerChangePeriod() was called. xTicksToWait is ignored if + * xTimerChangePeriod() is called before the scheduler is started. + * + * @return pdFAIL will be returned if the change period command could not be + * sent to the timer command queue even after xTicksToWait ticks had passed. + * pdPASS will be returned if the command was successfully sent to the timer + * command queue. When the command is actually processed will depend on the + * priority of the timer service/daemon task relative to other tasks in the + * system. The timer service/daemon task priority is set by the + * configTIMER_TASK_PRIORITY configuration constant. + * + * Example usage: + * @verbatim + * // This function assumes xTimer has already been created. If the timer + * // referenced by xTimer is already active when it is called, then the timer + * // is deleted. If the timer referenced by xTimer is not active when it is + * // called, then the period of the timer is set to 500ms and the timer is + * // started. + * void vAFunction( TimerHandle_t xTimer ) + * { + * if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )" + * { + * // xTimer is already active - delete it. + * xTimerDelete( xTimer ); + * } + * else + * { + * // xTimer is not active, change its period to 500ms. This will also + * // cause the timer to start. Block for a maximum of 100 ticks if the + * // change period command cannot immediately be sent to the timer + * // command queue. + * if( xTimerChangePeriod( xTimer, 500 / portTICK_PERIOD_MS, 100 ) == pdPASS ) + * { + * // The command was successfully sent. + * } + * else + * { + * // The command could not be sent, even after waiting for 100 ticks + * // to pass. Take appropriate action here. + * } + * } + * } + * @endverbatim + */ +#define xTimerChangePeriod( xTimer, xNewPeriod, xTicksToWait ) \ + xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD, ( xNewPeriod ), NULL, ( xTicksToWait ) ) + +/** + * BaseType_t xTimerDelete( TimerHandle_t xTimer, TickType_t xTicksToWait ); + * + * Timer functionality is provided by a timer service/daemon task. Many of the + * public FreeRTOS timer API functions send commands to the timer service task + * through a queue called the timer command queue. The timer command queue is + * private to the kernel itself and is not directly accessible to application + * code. The length of the timer command queue is set by the + * configTIMER_QUEUE_LENGTH configuration constant. + * + * xTimerDelete() deletes a timer that was previously created using the + * xTimerCreate() API function. + * + * The configUSE_TIMERS configuration constant must be set to 1 for + * xTimerDelete() to be available. + * + * @param xTimer The handle of the timer being deleted. + * + * @param xTicksToWait Specifies the time, in ticks, that the calling task should + * be held in the Blocked state to wait for the delete command to be + * successfully sent to the timer command queue, should the queue already be + * full when xTimerDelete() was called. xTicksToWait is ignored if xTimerDelete() + * is called before the scheduler is started. + * + * @return pdFAIL will be returned if the delete command could not be sent to + * the timer command queue even after xTicksToWait ticks had passed. pdPASS will + * be returned if the command was successfully sent to the timer command queue. + * When the command is actually processed will depend on the priority of the + * timer service/daemon task relative to other tasks in the system. The timer + * service/daemon task priority is set by the configTIMER_TASK_PRIORITY + * configuration constant. + * + * Example usage: + * + * See the xTimerChangePeriod() API function example usage scenario. + */ +#define xTimerDelete( xTimer, xTicksToWait ) \ + xTimerGenericCommand( ( xTimer ), tmrCOMMAND_DELETE, 0U, NULL, ( xTicksToWait ) ) + +/** + * BaseType_t xTimerReset( TimerHandle_t xTimer, TickType_t xTicksToWait ); + * + * Timer functionality is provided by a timer service/daemon task. Many of the + * public FreeRTOS timer API functions send commands to the timer service task + * through a queue called the timer command queue. The timer command queue is + * private to the kernel itself and is not directly accessible to application + * code. The length of the timer command queue is set by the + * configTIMER_QUEUE_LENGTH configuration constant. + * + * xTimerReset() re-starts a timer that was previously created using the + * xTimerCreate() API function. If the timer had already been started and was + * already in the active state, then xTimerReset() will cause the timer to + * re-evaluate its expiry time so that it is relative to when xTimerReset() was + * called. If the timer was in the dormant state then xTimerReset() has + * equivalent functionality to the xTimerStart() API function. + * + * Resetting a timer ensures the timer is in the active state. If the timer + * is not stopped, deleted, or reset in the mean time, the callback function + * associated with the timer will get called 'n' ticks after xTimerReset() was + * called, where 'n' is the timers defined period. + * + * It is valid to call xTimerReset() before the scheduler has been started, but + * when this is done the timer will not actually start until the scheduler is + * started, and the timers expiry time will be relative to when the scheduler is + * started, not relative to when xTimerReset() was called. + * + * The configUSE_TIMERS configuration constant must be set to 1 for xTimerReset() + * to be available. + * + * @param xTimer The handle of the timer being reset/started/restarted. + * + * @param xTicksToWait Specifies the time, in ticks, that the calling task should + * be held in the Blocked state to wait for the reset command to be successfully + * sent to the timer command queue, should the queue already be full when + * xTimerReset() was called. xTicksToWait is ignored if xTimerReset() is called + * before the scheduler is started. + * + * @return pdFAIL will be returned if the reset command could not be sent to + * the timer command queue even after xTicksToWait ticks had passed. pdPASS will + * be returned if the command was successfully sent to the timer command queue. + * When the command is actually processed will depend on the priority of the + * timer service/daemon task relative to other tasks in the system, although the + * timers expiry time is relative to when xTimerStart() is actually called. The + * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY + * configuration constant. + * + * Example usage: + * @verbatim + * // When a key is pressed, an LCD back-light is switched on. If 5 seconds pass + * // without a key being pressed, then the LCD back-light is switched off. In + * // this case, the timer is a one-shot timer. + * + * TimerHandle_t xBacklightTimer = NULL; + * + * // The callback function assigned to the one-shot timer. In this case the + * // parameter is not used. + * void vBacklightTimerCallback( TimerHandle_t pxTimer ) + * { + * // The timer expired, therefore 5 seconds must have passed since a key + * // was pressed. Switch off the LCD back-light. + * vSetBacklightState( BACKLIGHT_OFF ); + * } + * + * // The key press event handler. + * void vKeyPressEventHandler( char cKey ) + * { + * // Reset the timer that is responsible for turning the back-light off after + * // 5 seconds of key inactivity. Wait 10 ticks for the command to be + * // successfully sent if it cannot be sent immediately. + * if( xTimerReset( xBacklightTimer, 10 ) == pdPASS ) + * { + * // Turn on the LCD back-light. It will be turned off in the + * // vBacklightTimerCallback after 5 seconds of key inactivity. + * vSetBacklightState( BACKLIGHT_ON ); + * } + * else + * { + * // The reset command was not executed successfully. Take appropriate + * // action here. + * } + * + * // Perform the rest of the key processing here. + * } + * + * void main( void ) + * { + * + * // Create then start the one-shot timer that is responsible for turning + * // the back-light off if no keys are pressed within a 5 second period. + * xBacklightTimer = xTimerCreate( "BacklightTimer", // Just a text name, not used by the kernel. + * pdMS_TO_TICKS( 5000 ), // The timer period in ticks. + * pdFALSE, // The timer is a one-shot timer. + * 0, // The id is not used by the callback so can take any value. + * vBacklightTimerCallback // The callback function that switches the LCD back-light off. + * ); + * + * if( xBacklightTimer == NULL ) + * { + * // The timer was not created. + * } + * else + * { + * // Start the timer. No block time is specified, and even if one was + * // it would be ignored because the scheduler has not yet been + * // started. + * if( xTimerStart( xBacklightTimer, 0 ) != pdPASS ) + * { + * // The timer could not be set into the Active state. + * } + * } + * + * // ... + * // Create tasks here. + * // ... + * + * // Starting the scheduler will start the timer running as it has already + * // been set into the active state. + * vTaskStartScheduler(); + * + * // Should not reach here. + * for( ;; ); + * } + * @endverbatim + */ +#define xTimerReset( xTimer, xTicksToWait ) \ + xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) ) + +/** + * BaseType_t xTimerStartFromISR( TimerHandle_t xTimer, + * BaseType_t *pxHigherPriorityTaskWoken ); + * + * A version of xTimerStart() that can be called from an interrupt service + * routine. + * + * @param xTimer The handle of the timer being started/restarted. + * + * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most + * of its time in the Blocked state, waiting for messages to arrive on the timer + * command queue. Calling xTimerStartFromISR() writes a message to the timer + * command queue, so has the potential to transition the timer service/daemon + * task out of the Blocked state. If calling xTimerStartFromISR() causes the + * timer service/daemon task to leave the Blocked state, and the timer service/ + * daemon task has a priority equal to or greater than the currently executing + * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will + * get set to pdTRUE internally within the xTimerStartFromISR() function. If + * xTimerStartFromISR() sets this value to pdTRUE then a context switch should + * be performed before the interrupt exits. + * + * @return pdFAIL will be returned if the start command could not be sent to + * the timer command queue. pdPASS will be returned if the command was + * successfully sent to the timer command queue. When the command is actually + * processed will depend on the priority of the timer service/daemon task + * relative to other tasks in the system, although the timers expiry time is + * relative to when xTimerStartFromISR() is actually called. The timer + * service/daemon task priority is set by the configTIMER_TASK_PRIORITY + * configuration constant. + * + * Example usage: + * @verbatim + * // This scenario assumes xBacklightTimer has already been created. When a + * // key is pressed, an LCD back-light is switched on. If 5 seconds pass + * // without a key being pressed, then the LCD back-light is switched off. In + * // this case, the timer is a one-shot timer, and unlike the example given for + * // the xTimerReset() function, the key press event handler is an interrupt + * // service routine. + * + * // The callback function assigned to the one-shot timer. In this case the + * // parameter is not used. + * void vBacklightTimerCallback( TimerHandle_t pxTimer ) + * { + * // The timer expired, therefore 5 seconds must have passed since a key + * // was pressed. Switch off the LCD back-light. + * vSetBacklightState( BACKLIGHT_OFF ); + * } + * + * // The key press interrupt service routine. + * void vKeyPressEventInterruptHandler( void ) + * { + * BaseType_t xHigherPriorityTaskWoken = pdFALSE; + * + * // Ensure the LCD back-light is on, then restart the timer that is + * // responsible for turning the back-light off after 5 seconds of + * // key inactivity. This is an interrupt service routine so can only + * // call FreeRTOS API functions that end in "FromISR". + * vSetBacklightState( BACKLIGHT_ON ); + * + * // xTimerStartFromISR() or xTimerResetFromISR() could be called here + * // as both cause the timer to re-calculate its expiry time. + * // xHigherPriorityTaskWoken was initialised to pdFALSE when it was + * // declared (in this function). + * if( xTimerStartFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS ) + * { + * // The start command was not executed successfully. Take appropriate + * // action here. + * } + * + * // Perform the rest of the key processing here. + * + * // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch + * // should be performed. The syntax required to perform a context switch + * // from inside an ISR varies from port to port, and from compiler to + * // compiler. Inspect the demos for the port you are using to find the + * // actual syntax required. + * if( xHigherPriorityTaskWoken != pdFALSE ) + * { + * // Call the interrupt safe yield function here (actual function + * // depends on the FreeRTOS port being used). + * } + * } + * @endverbatim + */ +#define xTimerStartFromISR( xTimer, pxHigherPriorityTaskWoken ) \ + xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U ) + +/** + * BaseType_t xTimerStopFromISR( TimerHandle_t xTimer, + * BaseType_t *pxHigherPriorityTaskWoken ); + * + * A version of xTimerStop() that can be called from an interrupt service + * routine. + * + * @param xTimer The handle of the timer being stopped. + * + * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most + * of its time in the Blocked state, waiting for messages to arrive on the timer + * command queue. Calling xTimerStopFromISR() writes a message to the timer + * command queue, so has the potential to transition the timer service/daemon + * task out of the Blocked state. If calling xTimerStopFromISR() causes the + * timer service/daemon task to leave the Blocked state, and the timer service/ + * daemon task has a priority equal to or greater than the currently executing + * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will + * get set to pdTRUE internally within the xTimerStopFromISR() function. If + * xTimerStopFromISR() sets this value to pdTRUE then a context switch should + * be performed before the interrupt exits. + * + * @return pdFAIL will be returned if the stop command could not be sent to + * the timer command queue. pdPASS will be returned if the command was + * successfully sent to the timer command queue. When the command is actually + * processed will depend on the priority of the timer service/daemon task + * relative to other tasks in the system. The timer service/daemon task + * priority is set by the configTIMER_TASK_PRIORITY configuration constant. + * + * Example usage: + * @verbatim + * // This scenario assumes xTimer has already been created and started. When + * // an interrupt occurs, the timer should be simply stopped. + * + * // The interrupt service routine that stops the timer. + * void vAnExampleInterruptServiceRoutine( void ) + * { + * BaseType_t xHigherPriorityTaskWoken = pdFALSE; + * + * // The interrupt has occurred - simply stop the timer. + * // xHigherPriorityTaskWoken was set to pdFALSE where it was defined + * // (within this function). As this is an interrupt service routine, only + * // FreeRTOS API functions that end in "FromISR" can be used. + * if( xTimerStopFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS ) + * { + * // The stop command was not executed successfully. Take appropriate + * // action here. + * } + * + * // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch + * // should be performed. The syntax required to perform a context switch + * // from inside an ISR varies from port to port, and from compiler to + * // compiler. Inspect the demos for the port you are using to find the + * // actual syntax required. + * if( xHigherPriorityTaskWoken != pdFALSE ) + * { + * // Call the interrupt safe yield function here (actual function + * // depends on the FreeRTOS port being used). + * } + * } + * @endverbatim + */ +#define xTimerStopFromISR( xTimer, pxHigherPriorityTaskWoken ) \ + xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP_FROM_ISR, 0, ( pxHigherPriorityTaskWoken ), 0U ) + +/** + * BaseType_t xTimerChangePeriodFromISR( TimerHandle_t xTimer, + * TickType_t xNewPeriod, + * BaseType_t *pxHigherPriorityTaskWoken ); + * + * A version of xTimerChangePeriod() that can be called from an interrupt + * service routine. + * + * @param xTimer The handle of the timer that is having its period changed. + * + * @param xNewPeriod The new period for xTimer. Timer periods are specified in + * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time + * that has been specified in milliseconds. For example, if the timer must + * expire after 100 ticks, then xNewPeriod should be set to 100. Alternatively, + * if the timer must expire after 500ms, then xNewPeriod can be set to + * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than + * or equal to 1000. + * + * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most + * of its time in the Blocked state, waiting for messages to arrive on the timer + * command queue. Calling xTimerChangePeriodFromISR() writes a message to the + * timer command queue, so has the potential to transition the timer service/ + * daemon task out of the Blocked state. If calling xTimerChangePeriodFromISR() + * causes the timer service/daemon task to leave the Blocked state, and the + * timer service/daemon task has a priority equal to or greater than the + * currently executing task (the task that was interrupted), then + * *pxHigherPriorityTaskWoken will get set to pdTRUE internally within the + * xTimerChangePeriodFromISR() function. If xTimerChangePeriodFromISR() sets + * this value to pdTRUE then a context switch should be performed before the + * interrupt exits. + * + * @return pdFAIL will be returned if the command to change the timers period + * could not be sent to the timer command queue. pdPASS will be returned if the + * command was successfully sent to the timer command queue. When the command + * is actually processed will depend on the priority of the timer service/daemon + * task relative to other tasks in the system. The timer service/daemon task + * priority is set by the configTIMER_TASK_PRIORITY configuration constant. + * + * Example usage: + * @verbatim + * // This scenario assumes xTimer has already been created and started. When + * // an interrupt occurs, the period of xTimer should be changed to 500ms. + * + * // The interrupt service routine that changes the period of xTimer. + * void vAnExampleInterruptServiceRoutine( void ) + * { + * BaseType_t xHigherPriorityTaskWoken = pdFALSE; + * + * // The interrupt has occurred - change the period of xTimer to 500ms. + * // xHigherPriorityTaskWoken was set to pdFALSE where it was defined + * // (within this function). As this is an interrupt service routine, only + * // FreeRTOS API functions that end in "FromISR" can be used. + * if( xTimerChangePeriodFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS ) + * { + * // The command to change the timers period was not executed + * // successfully. Take appropriate action here. + * } + * + * // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch + * // should be performed. The syntax required to perform a context switch + * // from inside an ISR varies from port to port, and from compiler to + * // compiler. Inspect the demos for the port you are using to find the + * // actual syntax required. + * if( xHigherPriorityTaskWoken != pdFALSE ) + * { + * // Call the interrupt safe yield function here (actual function + * // depends on the FreeRTOS port being used). + * } + * } + * @endverbatim + */ +#define xTimerChangePeriodFromISR( xTimer, xNewPeriod, pxHigherPriorityTaskWoken ) \ + xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD_FROM_ISR, ( xNewPeriod ), ( pxHigherPriorityTaskWoken ), 0U ) + +/** + * BaseType_t xTimerResetFromISR( TimerHandle_t xTimer, + * BaseType_t *pxHigherPriorityTaskWoken ); + * + * A version of xTimerReset() that can be called from an interrupt service + * routine. + * + * @param xTimer The handle of the timer that is to be started, reset, or + * restarted. + * + * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most + * of its time in the Blocked state, waiting for messages to arrive on the timer + * command queue. Calling xTimerResetFromISR() writes a message to the timer + * command queue, so has the potential to transition the timer service/daemon + * task out of the Blocked state. If calling xTimerResetFromISR() causes the + * timer service/daemon task to leave the Blocked state, and the timer service/ + * daemon task has a priority equal to or greater than the currently executing + * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will + * get set to pdTRUE internally within the xTimerResetFromISR() function. If + * xTimerResetFromISR() sets this value to pdTRUE then a context switch should + * be performed before the interrupt exits. + * + * @return pdFAIL will be returned if the reset command could not be sent to + * the timer command queue. pdPASS will be returned if the command was + * successfully sent to the timer command queue. When the command is actually + * processed will depend on the priority of the timer service/daemon task + * relative to other tasks in the system, although the timers expiry time is + * relative to when xTimerResetFromISR() is actually called. The timer service/daemon + * task priority is set by the configTIMER_TASK_PRIORITY configuration constant. + * + * Example usage: + * @verbatim + * // This scenario assumes xBacklightTimer has already been created. When a + * // key is pressed, an LCD back-light is switched on. If 5 seconds pass + * // without a key being pressed, then the LCD back-light is switched off. In + * // this case, the timer is a one-shot timer, and unlike the example given for + * // the xTimerReset() function, the key press event handler is an interrupt + * // service routine. + * + * // The callback function assigned to the one-shot timer. In this case the + * // parameter is not used. + * void vBacklightTimerCallback( TimerHandle_t pxTimer ) + * { + * // The timer expired, therefore 5 seconds must have passed since a key + * // was pressed. Switch off the LCD back-light. + * vSetBacklightState( BACKLIGHT_OFF ); + * } + * + * // The key press interrupt service routine. + * void vKeyPressEventInterruptHandler( void ) + * { + * BaseType_t xHigherPriorityTaskWoken = pdFALSE; + * + * // Ensure the LCD back-light is on, then reset the timer that is + * // responsible for turning the back-light off after 5 seconds of + * // key inactivity. This is an interrupt service routine so can only + * // call FreeRTOS API functions that end in "FromISR". + * vSetBacklightState( BACKLIGHT_ON ); + * + * // xTimerStartFromISR() or xTimerResetFromISR() could be called here + * // as both cause the timer to re-calculate its expiry time. + * // xHigherPriorityTaskWoken was initialised to pdFALSE when it was + * // declared (in this function). + * if( xTimerResetFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS ) + * { + * // The reset command was not executed successfully. Take appropriate + * // action here. + * } + * + * // Perform the rest of the key processing here. + * + * // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch + * // should be performed. The syntax required to perform a context switch + * // from inside an ISR varies from port to port, and from compiler to + * // compiler. Inspect the demos for the port you are using to find the + * // actual syntax required. + * if( xHigherPriorityTaskWoken != pdFALSE ) + * { + * // Call the interrupt safe yield function here (actual function + * // depends on the FreeRTOS port being used). + * } + * } + * @endverbatim + */ +#define xTimerResetFromISR( xTimer, pxHigherPriorityTaskWoken ) \ + xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U ) + + +/** + * BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, + * void *pvParameter1, + * uint32_t ulParameter2, + * BaseType_t *pxHigherPriorityTaskWoken ); + * + * + * Used from application interrupt service routines to defer the execution of a + * function to the RTOS daemon task (the timer service task, hence this function + * is implemented in timers.c and is prefixed with 'Timer'). + * + * Ideally an interrupt service routine (ISR) is kept as short as possible, but + * sometimes an ISR either has a lot of processing to do, or needs to perform + * processing that is not deterministic. In these cases + * xTimerPendFunctionCallFromISR() can be used to defer processing of a function + * to the RTOS daemon task. + * + * A mechanism is provided that allows the interrupt to return directly to the + * task that will subsequently execute the pended callback function. This + * allows the callback function to execute contiguously in time with the + * interrupt - just as if the callback had executed in the interrupt itself. + * + * @param xFunctionToPend The function to execute from the timer service/ + * daemon task. The function must conform to the PendedFunction_t + * prototype. + * + * @param pvParameter1 The value of the callback function's first parameter. + * The parameter has a void * type to allow it to be used to pass any type. + * For example, unsigned longs can be cast to a void *, or the void * can be + * used to point to a structure. + * + * @param ulParameter2 The value of the callback function's second parameter. + * + * @param pxHigherPriorityTaskWoken As mentioned above, calling this function + * will result in a message being sent to the timer daemon task. If the + * priority of the timer daemon task (which is set using + * configTIMER_TASK_PRIORITY in FreeRTOSConfig.h) is higher than the priority of + * the currently running task (the task the interrupt interrupted) then + * *pxHigherPriorityTaskWoken will be set to pdTRUE within + * xTimerPendFunctionCallFromISR(), indicating that a context switch should be + * requested before the interrupt exits. For that reason + * *pxHigherPriorityTaskWoken must be initialised to pdFALSE. See the + * example code below. + * + * @return pdPASS is returned if the message was successfully sent to the + * timer daemon task, otherwise pdFALSE is returned. + * + * Example usage: + * @verbatim + * + * // The callback function that will execute in the context of the daemon task. + * // Note callback functions must all use this same prototype. + * void vProcessInterface( void *pvParameter1, uint32_t ulParameter2 ) + * { + * BaseType_t xInterfaceToService; + * + * // The interface that requires servicing is passed in the second + * // parameter. The first parameter is not used in this case. + * xInterfaceToService = ( BaseType_t ) ulParameter2; + * + * // ...Perform the processing here... + * } + * + * // An ISR that receives data packets from multiple interfaces + * void vAnISR( void ) + * { + * BaseType_t xInterfaceToService, xHigherPriorityTaskWoken; + * + * // Query the hardware to determine which interface needs processing. + * xInterfaceToService = prvCheckInterfaces(); + * + * // The actual processing is to be deferred to a task. Request the + * // vProcessInterface() callback function is executed, passing in the + * // number of the interface that needs processing. The interface to + * // service is passed in the second parameter. The first parameter is + * // not used in this case. + * xHigherPriorityTaskWoken = pdFALSE; + * xTimerPendFunctionCallFromISR( vProcessInterface, NULL, ( uint32_t ) xInterfaceToService, &xHigherPriorityTaskWoken ); + * + * // If xHigherPriorityTaskWoken is now set to pdTRUE then a context + * // switch should be requested. The macro used is port specific and will + * // be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - refer to + * // the documentation page for the port being used. + * portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + * + * } + * @endverbatim + */ +#if ( INCLUDE_xTimerPendFunctionCall == 1 ) + BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, + void * pvParameter1, + uint32_t ulParameter2, + BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; +#endif + +/** + * BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, + * void *pvParameter1, + * uint32_t ulParameter2, + * TickType_t xTicksToWait ); + * + * + * Used to defer the execution of a function to the RTOS daemon task (the timer + * service task, hence this function is implemented in timers.c and is prefixed + * with 'Timer'). + * + * @param xFunctionToPend The function to execute from the timer service/ + * daemon task. The function must conform to the PendedFunction_t + * prototype. + * + * @param pvParameter1 The value of the callback function's first parameter. + * The parameter has a void * type to allow it to be used to pass any type. + * For example, unsigned longs can be cast to a void *, or the void * can be + * used to point to a structure. + * + * @param ulParameter2 The value of the callback function's second parameter. + * + * @param xTicksToWait Calling this function will result in a message being + * sent to the timer daemon task on a queue. xTicksToWait is the amount of + * time the calling task should remain in the Blocked state (so not using any + * processing time) for space to become available on the timer queue if the + * queue is found to be full. + * + * @return pdPASS is returned if the message was successfully sent to the + * timer daemon task, otherwise pdFALSE is returned. + * + */ +#if ( INCLUDE_xTimerPendFunctionCall == 1 ) + BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, + void * pvParameter1, + uint32_t ulParameter2, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; +#endif + +/** + * const char * const pcTimerGetName( TimerHandle_t xTimer ); + * + * Returns the name that was assigned to a timer when the timer was created. + * + * @param xTimer The handle of the timer being queried. + * + * @return The name assigned to the timer specified by the xTimer parameter. + */ +const char * pcTimerGetName( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; + +/** + * void vTimerSetReloadMode( TimerHandle_t xTimer, const BaseType_t xAutoReload ); + * + * Updates a timer to be either an auto-reload timer, in which case the timer + * automatically resets itself each time it expires, or a one-shot timer, in + * which case the timer will only expire once unless it is manually restarted. + * + * @param xTimer The handle of the timer being updated. + * + * @param xAutoReload If xAutoReload is set to pdTRUE then the timer will + * expire repeatedly with a frequency set by the timer's period (see the + * xTimerPeriodInTicks parameter of the xTimerCreate() API function). If + * xAutoReload is set to pdFALSE then the timer will be a one-shot timer and + * enter the dormant state after it expires. + */ +void vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) PRIVILEGED_FUNCTION; + +/** + * BaseType_t xTimerGetReloadMode( TimerHandle_t xTimer ); + * + * Queries a timer to determine if it is an auto-reload timer, in which case the timer + * automatically resets itself each time it expires, or a one-shot timer, in + * which case the timer will only expire once unless it is manually restarted. + * + * @param xTimer The handle of the timer being queried. + * + * @return If the timer is an auto-reload timer then pdTRUE is returned, otherwise + * pdFALSE is returned. + */ +BaseType_t xTimerGetReloadMode( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; + +/** + * UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer ); + * + * Queries a timer to determine if it is an auto-reload timer, in which case the timer + * automatically resets itself each time it expires, or a one-shot timer, in + * which case the timer will only expire once unless it is manually restarted. + * + * @param xTimer The handle of the timer being queried. + * + * @return If the timer is an auto-reload timer then pdTRUE is returned, otherwise + * pdFALSE is returned. + */ +UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; + +/** + * TickType_t xTimerGetPeriod( TimerHandle_t xTimer ); + * + * Returns the period of a timer. + * + * @param xTimer The handle of the timer being queried. + * + * @return The period of the timer in ticks. + */ +TickType_t xTimerGetPeriod( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; + +/** + * TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer ); + * + * Returns the time in ticks at which the timer will expire. If this is less + * than the current tick count then the expiry time has overflowed from the + * current time. + * + * @param xTimer The handle of the timer being queried. + * + * @return If the timer is running then the time in ticks at which the timer + * will next expire is returned. If the timer is not running then the return + * value is undefined. + */ +TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; + +/** + * BaseType_t xTimerGetStaticBuffer( TimerHandle_t xTimer, + * StaticTimer_t ** ppxTimerBuffer ); + * + * Retrieve pointer to a statically created timer's data structure + * buffer. This is the same buffer that is supplied at the time of + * creation. + * + * @param xTimer The timer for which to retrieve the buffer. + * + * @param ppxTaskBuffer Used to return a pointer to the timers's data + * structure buffer. + * + * @return pdTRUE if the buffer was retrieved, pdFALSE otherwise. + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + BaseType_t xTimerGetStaticBuffer( TimerHandle_t xTimer, + StaticTimer_t ** ppxTimerBuffer ) PRIVILEGED_FUNCTION; +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +/* + * Functions beyond this part are not part of the public API and are intended + * for use by the kernel only. + */ +BaseType_t xTimerCreateTimerTask( void ) PRIVILEGED_FUNCTION; + +/* + * Splitting the xTimerGenericCommand into two sub functions and making it a macro + * removes a recursion path when called from ISRs. This is primarily for the XCore + * XCC port which detects the recursion path and throws an error during compilation + * when this is not split. + */ +BaseType_t xTimerGenericCommandFromTask( TimerHandle_t xTimer, + const BaseType_t xCommandID, + const TickType_t xOptionalValue, + BaseType_t * const pxHigherPriorityTaskWoken, + const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +BaseType_t xTimerGenericCommandFromISR( TimerHandle_t xTimer, + const BaseType_t xCommandID, + const TickType_t xOptionalValue, + BaseType_t * const pxHigherPriorityTaskWoken, + const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +#define xTimerGenericCommand( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait ) \ + ( ( xCommandID ) < tmrFIRST_FROM_ISR_COMMAND ? \ + xTimerGenericCommandFromTask( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait ) : \ + xTimerGenericCommandFromISR( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait ) ) +#if ( configUSE_TRACE_FACILITY == 1 ) + void vTimerSetTimerNumber( TimerHandle_t xTimer, + UBaseType_t uxTimerNumber ) PRIVILEGED_FUNCTION; + UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; +#endif + +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + +/** + * task.h + * @code{c} + * void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, StackType_t ** ppxTimerTaskStackBuffer, configSTACK_DEPTH_TYPE * puxTimerTaskStackSize ) + * @endcode + * + * This function is used to provide a statically allocated block of memory to FreeRTOS to hold the Timer Task TCB. This function is required when + * configSUPPORT_STATIC_ALLOCATION is set. For more information see this URI: https://www.FreeRTOS.org/a00110.html#configSUPPORT_STATIC_ALLOCATION + * + * @param ppxTimerTaskTCBBuffer A handle to a statically allocated TCB buffer + * @param ppxTimerTaskStackBuffer A handle to a statically allocated Stack buffer for the idle task + * @param puxTimerTaskStackSize A pointer to the number of elements that will fit in the allocated stack buffer + */ + void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, + StackType_t ** ppxTimerTaskStackBuffer, + configSTACK_DEPTH_TYPE * puxTimerTaskStackSize ); + +#endif + +#if ( configUSE_DAEMON_TASK_STARTUP_HOOK != 0 ) + +/** + * timers.h + * @code{c} + * void vApplicationDaemonTaskStartupHook( void ); + * @endcode + * + * This hook function is called form the timer task once when the task starts running. + */ + /* MISRA Ref 8.6.1 [External linkage] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-86 */ + /* coverity[misra_c_2012_rule_8_6_violation] */ + void vApplicationDaemonTaskStartupHook( void ); + +#endif + +/* + * This function resets the internal state of the timer module. It must be called + * by the application before restarting the scheduler. + */ +void vTimerResetState( void ) PRIVILEGED_FUNCTION; + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ +#endif /* TIMERS_H */ diff --git a/list.c b/list.c new file mode 100644 index 000000000..0c0f3676e --- /dev/null +++ b/list.c @@ -0,0 +1,248 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#include "FreeRTOS.h" +#include "list.h" + +/* The MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be + * defined for the header files above, but not in this file, in order to + * generate the correct privileged Vs unprivileged linkage and placement. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/*----------------------------------------------------------- +* PUBLIC LIST API documented in list.h +*----------------------------------------------------------*/ + +void vListInitialise( List_t * const pxList ) +{ + traceENTER_vListInitialise( pxList ); + + /* The list structure contains a list item which is used to mark the + * end of the list. To initialise the list the list end is inserted + * as the only list entry. */ + pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); + + listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( &( pxList->xListEnd ) ); + + /* The list end value is the highest possible value in the list to + * ensure it remains at the end of the list. */ + pxList->xListEnd.xItemValue = portMAX_DELAY; + + /* The list end next and previous pointers point to itself so we know + * when the list is empty. */ + pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); + pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd ); + + /* Initialize the remaining fields of xListEnd when it is a proper ListItem_t */ + #if ( configUSE_MINI_LIST_ITEM == 0 ) + { + pxList->xListEnd.pvOwner = NULL; + pxList->xListEnd.pxContainer = NULL; + listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( &( pxList->xListEnd ) ); + } + #endif + + pxList->uxNumberOfItems = ( UBaseType_t ) 0U; + + /* Write known values into the list if + * configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ); + listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ); + + traceRETURN_vListInitialise(); +} +/*-----------------------------------------------------------*/ + +void vListInitialiseItem( ListItem_t * const pxItem ) +{ + traceENTER_vListInitialiseItem( pxItem ); + + /* Make sure the list item is not recorded as being on a list. */ + pxItem->pxContainer = NULL; + + /* Write known values into the list item if + * configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); + listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); + + traceRETURN_vListInitialiseItem(); +} +/*-----------------------------------------------------------*/ + +void vListInsertEnd( List_t * const pxList, + ListItem_t * const pxNewListItem ) +{ + ListItem_t * const pxIndex = pxList->pxIndex; + + traceENTER_vListInsertEnd( pxList, pxNewListItem ); + + /* Only effective when configASSERT() is also defined, these tests may catch + * the list data structures being overwritten in memory. They will not catch + * data errors caused by incorrect configuration or use of FreeRTOS. */ + listTEST_LIST_INTEGRITY( pxList ); + listTEST_LIST_ITEM_INTEGRITY( pxNewListItem ); + + /* Insert a new list item into pxList, but rather than sort the list, + * makes the new list item the last item to be removed by a call to + * listGET_OWNER_OF_NEXT_ENTRY(). */ + pxNewListItem->pxNext = pxIndex; + pxNewListItem->pxPrevious = pxIndex->pxPrevious; + + /* Only used during decision coverage testing. */ + mtCOVERAGE_TEST_DELAY(); + + pxIndex->pxPrevious->pxNext = pxNewListItem; + pxIndex->pxPrevious = pxNewListItem; + + /* Remember which list the item is in. */ + pxNewListItem->pxContainer = pxList; + + ( pxList->uxNumberOfItems ) = ( UBaseType_t ) ( pxList->uxNumberOfItems + 1U ); + + traceRETURN_vListInsertEnd(); +} +/*-----------------------------------------------------------*/ + +void vListInsert( List_t * const pxList, + ListItem_t * const pxNewListItem ) +{ + ListItem_t * pxIterator; + const TickType_t xValueOfInsertion = pxNewListItem->xItemValue; + + traceENTER_vListInsert( pxList, pxNewListItem ); + + /* Only effective when configASSERT() is also defined, these tests may catch + * the list data structures being overwritten in memory. They will not catch + * data errors caused by incorrect configuration or use of FreeRTOS. */ + listTEST_LIST_INTEGRITY( pxList ); + listTEST_LIST_ITEM_INTEGRITY( pxNewListItem ); + + /* Insert the new list item into the list, sorted in xItemValue order. + * + * If the list already contains a list item with the same item value then the + * new list item should be placed after it. This ensures that TCBs which are + * stored in ready lists (all of which have the same xItemValue value) get a + * share of the CPU. However, if the xItemValue is the same as the back marker + * the iteration loop below will not end. Therefore the value is checked + * first, and the algorithm slightly modified if necessary. */ + if( xValueOfInsertion == portMAX_DELAY ) + { + pxIterator = pxList->xListEnd.pxPrevious; + } + else + { + /* *** NOTE *********************************************************** + * If you find your application is crashing here then likely causes are + * listed below. In addition see https://www.freertos.org/Why-FreeRTOS/FAQs for + * more tips, and ensure configASSERT() is defined! + * https://www.FreeRTOS.org/a00110.html#configASSERT + * + * 1) Stack overflow - + * see https://www.FreeRTOS.org/Stacks-and-stack-overflow-checking.html + * 2) Incorrect interrupt priority assignment, especially on Cortex-M + * parts where numerically high priority values denote low actual + * interrupt priorities, which can seem counter intuitive. See + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html and the definition + * of configMAX_SYSCALL_INTERRUPT_PRIORITY on + * https://www.FreeRTOS.org/a00110.html + * 3) Calling an API function from within a critical section or when + * the scheduler is suspended, or calling an API function that does + * not end in "FromISR" from an interrupt. + * 4) Using a queue or semaphore before it has been initialised or + * before the scheduler has been started (are interrupts firing + * before vTaskStartScheduler() has been called?). + * 5) If the FreeRTOS port supports interrupt nesting then ensure that + * the priority of the tick interrupt is at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + **********************************************************************/ + + for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) + { + /* There is nothing to do here, just iterating to the wanted + * insertion position. + * IF YOU FIND YOUR CODE STUCK HERE, SEE THE NOTE JUST ABOVE. + */ + } + } + + pxNewListItem->pxNext = pxIterator->pxNext; + pxNewListItem->pxNext->pxPrevious = pxNewListItem; + pxNewListItem->pxPrevious = pxIterator; + pxIterator->pxNext = pxNewListItem; + + /* Remember which list the item is in. This allows fast removal of the + * item later. */ + pxNewListItem->pxContainer = pxList; + + ( pxList->uxNumberOfItems ) = ( UBaseType_t ) ( pxList->uxNumberOfItems + 1U ); + + traceRETURN_vListInsert(); +} +/*-----------------------------------------------------------*/ + + +UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) +{ + /* The list item knows which list it is in. Obtain the list from the list + * item. */ + List_t * const pxList = pxItemToRemove->pxContainer; + + traceENTER_uxListRemove( pxItemToRemove ); + + pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious; + pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext; + + /* Only used during decision coverage testing. */ + mtCOVERAGE_TEST_DELAY(); + + /* Make sure the index is left pointing to a valid item. */ + if( pxList->pxIndex == pxItemToRemove ) + { + pxList->pxIndex = pxItemToRemove->pxPrevious; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + pxItemToRemove->pxContainer = NULL; + ( pxList->uxNumberOfItems ) = ( UBaseType_t ) ( pxList->uxNumberOfItems - 1U ); + + traceRETURN_uxListRemove( pxList->uxNumberOfItems ); + + return pxList->uxNumberOfItems; +} +/*-----------------------------------------------------------*/ diff --git a/manifest.yml b/manifest.yml new file mode 100644 index 000000000..bd893f162 --- /dev/null +++ b/manifest.yml @@ -0,0 +1,4 @@ +name : "FreeRTOS-Kernel" +version: "V11.0.1+" +description: "FreeRTOS Kernel." +license: "MIT" diff --git a/portable/ARMClang/Use-the-GCC-ports.txt b/portable/ARMClang/Use-the-GCC-ports.txt new file mode 100644 index 000000000..9dd1bc71c --- /dev/null +++ b/portable/ARMClang/Use-the-GCC-ports.txt @@ -0,0 +1,2 @@ +The FreeRTOS GCC port layer also builds and works with the ARMClang compiler. +To use the ARMClang compiler build the port files from FreeRTOS/Source/portable/GCC. diff --git a/portable/ARMv8M/ReadMe.txt b/portable/ARMv8M/ReadMe.txt new file mode 100644 index 000000000..66c70d463 --- /dev/null +++ b/portable/ARMv8M/ReadMe.txt @@ -0,0 +1,11 @@ +This directory tree contains the master copy of the FreeRTOS Armv8-M and +Armv8.1-M ports. +Do not use the files located here! These file are copied into separate +FreeRTOS/Source/portable/[compiler]/ARM_[CM23|CM33|CM52|CM55|CM85|STAR_MC3]_NNN directories +prior to each FreeRTOS release. + +If your Armv8-M and Armv8.1-M application uses TrustZone then use the files from the +FreeRTOS/Source/portable/[compiler]/ARM_[CM23|CM33|CM52|CM55|CM85|STAR_MC3] directories. + +If your Armv8-M and Armv8.1-M application does not use TrustZone then use the files from +the FreeRTOS/Source/portable/[compiler]/ARM_[CM23|CM33|CM52|CM55|CM85|STAR_MC3]_NTZ directories. diff --git a/portable/ARMv8M/copy_files.py b/portable/ARMv8M/copy_files.py new file mode 100644 index 000000000..ddeeb13ea --- /dev/null +++ b/portable/ARMv8M/copy_files.py @@ -0,0 +1,202 @@ +#/* +# * FreeRTOS Kernel +# * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# * +# * SPDX-License-Identifier: MIT +# * +# * Permission is hereby granted, free of charge, to any person obtaining a copy of +# * this software and associated documentation files (the "Software"), to deal in +# * the Software without restriction, including without limitation the rights to +# * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +# * the Software, and to permit persons to whom the Software is furnished to do so, +# * subject to the following conditions: +# * +# * The above copyright notice and this permission notice shall be included in all +# * copies or substantial portions of the Software. +# * +# * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +# * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +# * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +# * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +# * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# * +# * https://www.FreeRTOS.org +# * https://github.com/FreeRTOS +# * +# */ + +import os +import shutil + +_THIS_FILE_DIRECTORY_ = os.path.dirname(os.path.realpath(__file__)) +_FREERTOS_PORTABLE_DIRECTORY_ = os.path.dirname(_THIS_FILE_DIRECTORY_) + +_COMPILERS_ = ['GCC', 'IAR'] +_ARCH_NS_ = ['ARM_CM85', 'ARM_CM85_NTZ', 'ARM_CM55', 'ARM_CM55_NTZ', 'ARM_CM52', 'ARM_CM52_NTZ', 'ARM_CM35P', 'ARM_CM35P_NTZ', 'ARM_CM33', 'ARM_CM33_NTZ', 'ARM_CM23', 'ARM_CM23_NTZ', 'ARM_STAR_MC3', 'ARM_STAR_MC3_NTZ'] +_ARCH_S_ = ['ARM_CM85', 'ARM_CM55', 'ARM_CM52', 'ARM_CM35P', 'ARM_CM33', 'ARM_CM23', 'ARM_STAR_MC3'] + +# Files to be compiled in the Secure Project +_SECURE_COMMON_FILE_PATHS_ = [ + os.path.join('secure', 'context'), + os.path.join('secure', 'heap'), + os.path.join('secure', 'init'), + os.path.join('secure', 'macros') +] + +_SECURE_PORTABLE_FILE_PATHS_ = { + 'GCC':{ + 'ARM_CM23' :[os.path.join('secure', 'context', 'portable', 'GCC', 'ARM_CM23')], + 'ARM_CM33' :[os.path.join('secure', 'context', 'portable', 'GCC', 'ARM_CM33')], + 'ARM_CM35P' :[os.path.join('secure', 'context', 'portable', 'GCC', 'ARM_CM33')], + 'ARM_CM52' :[os.path.join('secure', 'context', 'portable', 'GCC', 'ARM_CM33')], + 'ARM_CM55' :[os.path.join('secure', 'context', 'portable', 'GCC', 'ARM_CM33')], + 'ARM_CM85' :[os.path.join('secure', 'context', 'portable', 'GCC', 'ARM_CM33')], + 'ARM_STAR_MC3' :[os.path.join('secure', 'context', 'portable', 'GCC', 'ARM_CM33')] + }, + 'IAR':{ + 'ARM_CM23' :[os.path.join('secure', 'context', 'portable', 'IAR', 'ARM_CM23')], + 'ARM_CM33' :[os.path.join('secure', 'context', 'portable', 'IAR', 'ARM_CM33')], + 'ARM_CM35P' :[os.path.join('secure', 'context', 'portable', 'IAR', 'ARM_CM33')], + 'ARM_CM52' :[os.path.join('secure', 'context', 'portable', 'IAR', 'ARM_CM33')], + 'ARM_CM55' :[os.path.join('secure', 'context', 'portable', 'IAR', 'ARM_CM33')], + 'ARM_CM85' :[os.path.join('secure', 'context', 'portable', 'IAR', 'ARM_CM33')], + 'ARM_STAR_MC3' :[os.path.join('secure', 'context', 'portable', 'IAR', 'ARM_CM33')] + } +} + +# Files to be compiled in the Non-Secure Project +_NONSECURE_COMMON_FILE_PATHS_ = [ + 'non_secure' +] + +_NONSECURE_PORTABLE_FILE_PATHS_ = { + 'GCC':{ + 'ARM_CM23' : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM23')], + 'ARM_CM23_NTZ' : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM23_NTZ')], + 'ARM_CM33' : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33')], + 'ARM_CM33_NTZ' : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33_NTZ')], + 'ARM_CM35P' : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33', 'portasm.c'), + os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33', 'mpu_wrappers_v2_asm.c'), + os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM35P', 'portmacro.h')], + 'ARM_CM35P_NTZ' : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33_NTZ', 'portasm.c'), + os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33_NTZ', 'mpu_wrappers_v2_asm.c'), + os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM35P', 'portmacro.h')], + 'ARM_CM52' : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33', 'portasm.c'), + os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33', 'mpu_wrappers_v2_asm.c'), + os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM52', 'portmacro.h')], + 'ARM_CM52_NTZ' : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33_NTZ', 'portasm.c'), + os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33_NTZ', 'mpu_wrappers_v2_asm.c'), + os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM52', 'portmacro.h')], + 'ARM_CM55' : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33', 'portasm.c'), + os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33', 'mpu_wrappers_v2_asm.c'), + os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM55', 'portmacro.h')], + 'ARM_CM55_NTZ' : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33_NTZ', 'portasm.c'), + os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33_NTZ', 'mpu_wrappers_v2_asm.c'), + os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM55', 'portmacro.h')], + 'ARM_CM85' : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33', 'portasm.c'), + os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33', 'mpu_wrappers_v2_asm.c'), + os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM85', 'portmacro.h')], + 'ARM_CM85_NTZ' : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33_NTZ', 'portasm.c'), + os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33_NTZ', 'mpu_wrappers_v2_asm.c'), + os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM85', 'portmacro.h')], + 'ARM_STAR_MC3' : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33', 'portasm.c'), + os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33', 'mpu_wrappers_v2_asm.c'), + os.path.join('non_secure', 'portable', 'GCC', 'ARM_STAR_MC3', 'portmacro.h')], + 'ARM_STAR_MC3_NTZ' : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33_NTZ', 'portasm.c'), + os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33_NTZ', 'mpu_wrappers_v2_asm.c'), + os.path.join('non_secure', 'portable', 'GCC', 'ARM_STAR_MC3', 'portmacro.h')] + }, + 'IAR':{ + 'ARM_CM23' : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM23')], + 'ARM_CM23_NTZ' : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM23_NTZ')], + 'ARM_CM33' : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33')], + 'ARM_CM33_NTZ' : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33_NTZ')], + 'ARM_CM35P' : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33', 'portasm.s'), + os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33', 'mpu_wrappers_v2_asm.S'), + os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM35P', 'portmacro.h')], + 'ARM_CM35P_NTZ' : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33_NTZ', 'portasm.s'), + os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33_NTZ', 'mpu_wrappers_v2_asm.S'), + os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM35P', 'portmacro.h')], + 'ARM_CM52' : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33', 'portasm.s'), + os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33', 'mpu_wrappers_v2_asm.S'), + os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM52', 'portmacro.h')], + 'ARM_CM52_NTZ' : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33_NTZ', 'portasm.s'), + os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33_NTZ', 'mpu_wrappers_v2_asm.S'), + os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM52', 'portmacro.h')], + 'ARM_CM55' : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33', 'portasm.s'), + os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33', 'mpu_wrappers_v2_asm.S'), + os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM55', 'portmacro.h')], + 'ARM_CM55_NTZ' : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33_NTZ', 'portasm.s'), + os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33_NTZ', 'mpu_wrappers_v2_asm.S'), + os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM55', 'portmacro.h')], + 'ARM_CM85' : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33', 'portasm.s'), + os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33', 'mpu_wrappers_v2_asm.S'), + os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM85', 'portmacro.h')], + 'ARM_CM85_NTZ' : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33_NTZ', 'portasm.s'), + os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33_NTZ', 'mpu_wrappers_v2_asm.S'), + os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM85', 'portmacro.h')], + 'ARM_STAR_MC3' : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33', 'portasm.s'), + os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33', 'mpu_wrappers_v2_asm.S'), + os.path.join('non_secure', 'portable', 'IAR', 'ARM_STAR_MC3', 'portmacro.h')], + 'ARM_STAR_MC3_NTZ' : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33_NTZ', 'portasm.s'), + os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33_NTZ', 'mpu_wrappers_v2_asm.S'), + os.path.join('non_secure', 'portable', 'IAR', 'ARM_STAR_MC3', 'portmacro.h')] + }, +} + + +def copy_files_in_dir(src_abs_path, dst_abs_path): + if os.path.isfile(src_abs_path): + print('Src: {}'.format(src_abs_path)) + print('Dst: {}\n'.format(dst_abs_path)) + shutil.copy2(src_abs_path, dst_abs_path) + else: + for src_file in os.listdir(src_abs_path): + src_file_abs_path = os.path.join(src_abs_path, src_file) + if os.path.isfile(src_file_abs_path) and src_file != 'ReadMe.txt': + if not os.path.exists(dst_abs_path): + os.makedirs(dst_abs_path) + print('Src: {}'.format(src_file_abs_path)) + print('Dst: {}\n'.format(dst_abs_path)) + shutil.copy2(src_file_abs_path, dst_abs_path) + + +def copy_common_files_for_compiler_and_arch(compiler, arch, src_paths, dst_path): + for src_path in src_paths: + + src_abs_path = os.path.join(_THIS_FILE_DIRECTORY_, src_path) + dst_abs_path = os.path.join(_FREERTOS_PORTABLE_DIRECTORY_, compiler, arch, dst_path) + + copy_files_in_dir(src_abs_path, dst_abs_path) + + +def copy_portable_files_for_compiler_and_arch(compiler, arch, src_paths, dst_path): + for src_path in src_paths[compiler][arch]: + + src_abs_path = os.path.join(_THIS_FILE_DIRECTORY_, src_path) + dst_abs_path = os.path.join(_FREERTOS_PORTABLE_DIRECTORY_, compiler, arch, dst_path) + + copy_files_in_dir(src_abs_path, dst_abs_path) + + +def copy_files(): + # Copy Secure Files + for compiler in _COMPILERS_: + for arch in _ARCH_S_: + copy_common_files_for_compiler_and_arch(compiler, arch, _SECURE_COMMON_FILE_PATHS_, 'secure') + copy_portable_files_for_compiler_and_arch(compiler, arch, _SECURE_PORTABLE_FILE_PATHS_, 'secure') + + # Copy Non-Secure Files + for compiler in _COMPILERS_: + for arch in _ARCH_NS_: + copy_common_files_for_compiler_and_arch(compiler, arch, _NONSECURE_COMMON_FILE_PATHS_, 'non_secure') + copy_portable_files_for_compiler_and_arch(compiler, arch, _NONSECURE_PORTABLE_FILE_PATHS_, 'non_secure') + + +def main(): + copy_files() + + +if __name__ == '__main__': + main() diff --git a/portable/ARMv8M/non_secure/ReadMe.txt b/portable/ARMv8M/non_secure/ReadMe.txt new file mode 100644 index 000000000..5a8c28838 --- /dev/null +++ b/portable/ARMv8M/non_secure/ReadMe.txt @@ -0,0 +1,11 @@ +This directory tree contains the master copy of the FreeRTOS Armv8-M and +Armv8.1-M ports. +Do not use the files located here! These file are copied into separate +FreeRTOS/Source/portable/[compiler]/ARM_[CM23|CM33|CM52|CM55|CM85|STAR_MC3]_NNN directories +prior to each FreeRTOS release. + +If your Armv8-M/Armv8.1-M application uses TrustZone then use the files from the +FreeRTOS/Source/portable/[compiler]/ARM_[CM23|CM33|CM52|CM55|CM85|STAR_MC3] directories. + +If your Armv8-M/Armv8.1-M application does not use TrustZone then use the files from +the FreeRTOS/Source/portable/[compiler]/ARM_[CM23|CM33|CM52|CM55|CM85|STAR_MC3]_NTZ directories. diff --git a/portable/ARMv8M/non_secure/port.c b/portable/ARMv8M/non_secure/port.c new file mode 100644 index 000000000..76d2b2445 --- /dev/null +++ b/portable/ARMv8M/non_secure/port.c @@ -0,0 +1,2280 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024-2025 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU includes. */ +#include "mpu_wrappers.h" +#include "mpu_syscall_numbers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration settings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to check the validity of an interrupt priority. + */ +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) ) +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used during system call enter and exit. + */ +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Offsets in the stack to the parameters when inside the SVC handler. + */ +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +#if ( portARMV8M_MINOR_VERSION >= 1 ) + + /* Enable Privileged eXecute Never MPU attribute for the selected memory + * region. */ + #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL ) +#endif /* portARMV8M_MINOR_VERSION >= 1 */ + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Extract first address of the MPU region as encoded in the + * RBAR (Region Base Address Register) value. */ +#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \ + ( ( rbar ) & portMPU_RBAR_ADDRESS_MASK ) + +/* Extract last address of the MPU region as encoded in the + * RLAR (Region Limit Address Register) value. */ +#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \ + ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK ) + +/* Does addr lies within [start, end] address range? */ +#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \ + ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) ) + +/* Is the access request satisfied by the available permissions? */ +#define portIS_AUTHORIZED( accessRequest, permissions ) \ + ( ( ( permissions ) & ( accessRequest ) ) == accessRequest ) + +/* Max value that fits in a uint32_t type. */ +#define portUINT32_MAX ( ~( ( uint32_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. + */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 + +/** + * @brief Constants required to check and configure PACBTI security feature implementation. + */ +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) ) + + #define portCONTROL_UPAC_EN ( 1UL << 7UL ) + #define portCONTROL_PAC_EN ( 1UL << 6UL ) + #define portCONTROL_UBTI_EN ( 1UL << 5UL ) + #define portCONTROL_BTI_EN ( 1UL << 4UL ) + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Extract MPU region's access permissions from the Region Base Address + * Register (RBAR) value. + * + * @param ulRBARValue RBAR value for the MPU region. + * + * @return uint32_t Access permissions. + */ + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + + /** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + /** + * @brief Configures PACBTI features. + * + * This function configures the Pointer Authentication, and Branch Target + * Identification security features as per the user configuration. It returns + * the value of the special purpose CONTROL register accordingly, and optionally + * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M + * architecture based) target supports PACBTI security feature. + * + * @param xWriteControlRegister Used to control whether the special purpose + * CONTROL register should be updated or not. + * + * @return CONTROL register value according to the configured PACBTI option. + */ + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the system call stack so that upon returning from + * SVC, the system call stack is used. + * + * @param pulTaskStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + * @param ucSystemCallNumber The system call number of the system call. + */ + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Raise SVC for exiting from a system call. + */ + void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief This variable is set to pdTRUE when the scheduler is started. + */ + PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + + /** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +/** + * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + /** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + + /** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + + /** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the cpsid instruction + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessPermissions = 0; + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_ONLY ) + { + ulAccessPermissions = tskMPU_READ_PERMISSION; + } + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_WRITE ) + { + ulAccessPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION ); + } + + return ulAccessPermissions; + } + +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } + +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ portOFFSET_TO_PC ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ]; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulSystemCallStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the system call section (i.e. application is + * not raising SVC directly). + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as + * it is non-NULL only during the execution of a system call (i.e. + * between system call enter and exit). + * 3. System call is not for a kernel API disabled by the configuration + * in FreeRTOSConfig.h. + * 4. We do not need to check that ucSystemCallNumber is within range + * because the assembly SVC handler checks that before calling + * this function. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) && + ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) ) + { + pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the system call stack for the stack frame. */ + pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulSystemCallStack[ i ] = pulTaskStack[ i ]; + } + + /* Store the value of the Link Register before the SVC was raised. + * It contains the address of the caller of the System Call entry + * point (i.e. the caller of the MPU_). We need to restore it + * when we exit from the system call. */ + pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; + + /* Store the value of the PSPLIM register before the SVC was raised. + * We need to restore it when we exit from the system call. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* Use the pulSystemCallStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif + + /* Start executing the system call upon returning from this handler. */ + pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; + + /* Raise a request to exit from the system call upon finishing the + * system call. */ + pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; + + /* Remember the location where we should copy the stack frame when we exit from + * the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize; + + /* Record if the hardware used padding to force the stack pointer + * to be double word aligned. */ + if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK ) + { + pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG; + } + else + { + pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG ); + } + + /* We ensure in pxPortInitialiseStack that the system call stack is + * double word aligned and therefore, there is no need of padding. + * Clear the bit[9] of stacked xPSR. */ + pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + + /* Raise the privilege for the duration of the system call. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " bics r0, r1 \n" /* Clear nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */ + { + __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulTaskStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the privileged code (i.e. application is not + * raising SVC directly). This SVC is only raised from + * vRequestSystemCallExit which is in the privileged code section. + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL - + * this means that we previously entered a system call and the + * application is not attempting to exit without entering a system + * call. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) ) + { + pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the task stack for the stack frame. */ + pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulTaskStack[ i ] = pulSystemCallStack[ i ]; + } + + /* Use the pulTaskStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) ); + + /* Return to the caller of the System Call entry point (i.e. the + * caller of the MPU_). */ + pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + /* Ensure that LR has a valid value.*/ + pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + + /* Restore the PSPLIM register to what it was at the time of + * system call entry. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* If the hardware used padding to force the stack pointer + * to be double word aligned, set the stacked xPSR bit[9], + * otherwise clear it. */ + if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG ) + { + pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK; + } + else + { + pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + } + + /* This is not NULL only for the duration of the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; + + /* Drop the privilege before returning to the thread mode. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " orrs r0, r1 \n" /* Set nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xTaskIsPrivileged = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xTaskIsPrivileged = pdTRUE; + } + + return xTaskIsPrivileged; + } + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged, + xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulIndex = 0; + uint32_t ulControl = 0x0; + + xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ + ulIndex++; + + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + ulIndex++; + + #if ( configENABLE_TRUSTZONE == 1 ) + { + xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */ + ulIndex++; + } + #endif /* configENABLE_TRUSTZONE */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + ulIndex++; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Check PACBTI security feature configuration before pushing the + * CONTROL register's value on task's TCB. */ + ulControl = prvConfigurePACBTI( pdFALSE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + if( xRunPrivileged == pdTRUE ) + { + xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + else + { + xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG ); + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ + ulIndex++; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + { + /* Ensure that the system call stack is double word aligned. */ + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) + + ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + /* This is not NULL only for the duration of a system call. */ + xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL; + } + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ]; + ulIndex++; + } + } + #endif /* configENABLE_PAC */ + + return &( xMPUSettings->ulContext[ ulIndex ] ); + } + +#else /* configENABLE_MPU */ + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ + { + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + pxTopOfStack--; + *pxTopOfStack = ulTaskPacKey[ i ]; + } + } + #endif /* configENABLE_PAC */ + + return pxTopOfStack; + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Set the CONTROL register value based on PACBTI security feature + * configuration before starting the first task. */ + ( void ) prvConfigurePACBTI( pdTRUE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + { + xSchedulerRunning = pdTRUE; + } + #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + configSTACK_DEPTH_TYPE uxStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( uxStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* PXN. */ + #if ( portARMV8M_MINOR_VERSION >= 1 ) + { + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ); + } + } + #endif /* portARMV8M_MINOR_VERSION >= 1 */ + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, + uint32_t ulBufferLength, + uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */ + + { + uint32_t i, ulBufferStartAddress, ulBufferEndAddress; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE ) + { + ulBufferStartAddress = ( uint32_t ) pvBuffer; + ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL ); + + for( i = 0; i < portTOTAL_NUM_REGIONS; i++ ) + { + /* Is the MPU region enabled? */ + if( ( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR & portMPU_RLAR_REGION_ENABLE ) == portMPU_RLAR_REGION_ENABLE ) + { + if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_AUTHORIZED( ulAccessRequested, + prvGetRegionAccessPermissions( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ) ) ) + { + xAccessGranted = pdTRUE; + break; + } + } + } + } + } + + return xAccessGranted; + } + +#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings; + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else + { + xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 ) + { + xAccessGranted = pdTRUE; + } + } + } + + return xAccessGranted; + } + + #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + ( void ) lInternalIndexOfKernelObject; + + /* If Access Control List feature is not used, all the tasks have + * access to all the kernel objects. */ + return pdTRUE; + } + + #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + { + uint32_t ulControl = 0x0; + + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); + + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; + + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c new file mode 100644 index 000000000..7a62caff0 --- /dev/null +++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/mpu_wrappers_v2_asm.c @@ -0,0 +1,2125 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" +#include "event_groups.h" +#include "stream_buffer.h" +#include "mpu_prototypes.h" +#include "mpu_syscall_numbers.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( INCLUDE_xTaskDelayUntil == 1 ) + + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskDelayUntilImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskDelayUntil_Unpriv \n" + " MPU_xTaskDelayUntil_Priv: \n" + " b MPU_xTaskDelayUntilImpl \n" + " MPU_xTaskDelayUntil_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskAbortDelayImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskAbortDelay_Unpriv \n" + " MPU_xTaskAbortDelay_Priv: \n" + " b MPU_xTaskAbortDelayImpl \n" + " MPU_xTaskAbortDelay_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskDelay == 1 ) + + void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskDelayImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vTaskDelay_Unpriv \n" + " MPU_vTaskDelay_Priv: \n" + " b MPU_vTaskDelayImpl \n" + " MPU_vTaskDelay_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskPriorityGet == 1 ) + + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskPriorityGetImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_uxTaskPriorityGet_Unpriv \n" + " MPU_uxTaskPriorityGet_Priv: \n" + " b MPU_uxTaskPriorityGetImpl \n" + " MPU_uxTaskPriorityGet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_eTaskGetState == 1 ) + + eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_eTaskGetStateImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_eTaskGetState_Unpriv \n" + " MPU_eTaskGetState_Priv: \n" + " b MPU_eTaskGetStateImpl \n" + " MPU_eTaskGetState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory" + ); + } + + #endif /* if ( INCLUDE_eTaskGetState == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskGetInfoImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vTaskGetInfo_Unpriv \n" + " MPU_vTaskGetInfo_Priv: \n" + " b MPU_vTaskGetInfoImpl \n" + " MPU_vTaskGetInfo_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory" + ); + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) + + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetIdleTaskHandleImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskGetIdleTaskHandle_Unpriv \n" + " MPU_xTaskGetIdleTaskHandle_Priv: \n" + " b MPU_xTaskGetIdleTaskHandleImpl \n" + " MPU_xTaskGetIdleTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + + void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSuspendImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vTaskSuspend_Unpriv \n" + " MPU_vTaskSuspend_Priv: \n" + " b MPU_vTaskSuspendImpl \n" + " MPU_vTaskSuspend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + + void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskResumeImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vTaskResume_Unpriv \n" + " MPU_vTaskResume_Priv: \n" + " b MPU_vTaskResumeImpl \n" + " MPU_vTaskResume_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + TickType_t MPU_xTaskGetTickCount( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetTickCountImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskGetTickCount_Unpriv \n" + " MPU_xTaskGetTickCount_Priv: \n" + " b MPU_xTaskGetTickCountImpl \n" + " MPU_xTaskGetTickCount_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetNumberOfTasksImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_uxTaskGetNumberOfTasks_Unpriv \n" + " MPU_uxTaskGetNumberOfTasks_Priv: \n" + " b MPU_uxTaskGetNumberOfTasksImpl \n" + " MPU_uxTaskGetNumberOfTasks_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetRunTimeCounterImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_ulTaskGetRunTimeCounter_Unpriv \n" + " MPU_ulTaskGetRunTimeCounter_Priv: \n" + " b MPU_ulTaskGetRunTimeCounterImpl \n" + " MPU_ulTaskGetRunTimeCounter_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetRunTimePercentImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_ulTaskGetRunTimePercent_Unpriv \n" + " MPU_ulTaskGetRunTimePercent_Priv: \n" + " b MPU_ulTaskGetRunTimePercentImpl \n" + " MPU_ulTaskGetRunTimePercent_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetIdleRunTimePercentImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv \n" + " MPU_ulTaskGetIdleRunTimePercent_Priv: \n" + " b MPU_ulTaskGetIdleRunTimePercentImpl \n" + " MPU_ulTaskGetIdleRunTimePercent_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetIdleRunTimeCounterImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv \n" + " MPU_ulTaskGetIdleRunTimeCounter_Priv: \n" + " b MPU_ulTaskGetIdleRunTimeCounterImpl \n" + " MPU_ulTaskGetIdleRunTimeCounter_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetApplicationTaskTagImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vTaskSetApplicationTaskTag_Unpriv \n" + " MPU_vTaskSetApplicationTaskTag_Priv: \n" + " b MPU_vTaskSetApplicationTaskTagImpl \n" + " MPU_vTaskSetApplicationTaskTag_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory" + ); + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetApplicationTaskTagImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskGetApplicationTaskTag_Unpriv \n" + " MPU_xTaskGetApplicationTaskTag_Priv: \n" + " b MPU_xTaskGetApplicationTaskTagImpl \n" + " MPU_xTaskGetApplicationTaskTag_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory" + ); + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetThreadLocalStoragePointerImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv \n" + " MPU_vTaskSetThreadLocalStoragePointer_Priv: \n" + " b MPU_vTaskSetThreadLocalStoragePointerImpl \n" + " MPU_vTaskSetThreadLocalStoragePointer_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory" + ); + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv \n" + " MPU_pvTaskGetThreadLocalStoragePointer_Priv: \n" + " b MPU_pvTaskGetThreadLocalStoragePointerImpl \n" + " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory" + ); + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetSystemStateImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_uxTaskGetSystemState_Unpriv \n" + " MPU_uxTaskGetSystemState_Priv: \n" + " b MPU_uxTaskGetSystemStateImpl \n" + " MPU_uxTaskGetSystemState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory" + ); + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) + + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetStackHighWaterMarkImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_uxTaskGetStackHighWaterMark_Unpriv \n" + " MPU_uxTaskGetStackHighWaterMark_Priv: \n" + " b MPU_uxTaskGetStackHighWaterMarkImpl \n" + " MPU_uxTaskGetStackHighWaterMark_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetStackHighWaterMark2Impl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv \n" + " MPU_uxTaskGetStackHighWaterMark2_Priv: \n" + " b MPU_uxTaskGetStackHighWaterMark2Impl \n" + " MPU_uxTaskGetStackHighWaterMark2_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) + + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetCurrentTaskHandleImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskGetCurrentTaskHandle_Unpriv \n" + " MPU_xTaskGetCurrentTaskHandle_Priv: \n" + " b MPU_xTaskGetCurrentTaskHandleImpl \n" + " MPU_xTaskGetCurrentTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory" + ); + } + + #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetSchedulerState == 1 ) + + BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetSchedulerStateImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskGetSchedulerState_Unpriv \n" + " MPU_xTaskGetSchedulerState_Priv: \n" + " b MPU_xTaskGetSchedulerStateImpl \n" + " MPU_xTaskGetSchedulerState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */ +/*-----------------------------------------------------------*/ + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetTimeOutStateImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vTaskSetTimeOutState_Unpriv \n" + " MPU_vTaskSetTimeOutState_Priv: \n" + " b MPU_vTaskSetTimeOutStateImpl \n" + " MPU_vTaskSetTimeOutState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskCheckForTimeOutImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskCheckForTimeOut_Unpriv \n" + " MPU_xTaskCheckForTimeOut_Priv: \n" + " b MPU_xTaskCheckForTimeOutImpl \n" + " MPU_xTaskCheckForTimeOut_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskGenericNotify_Unpriv \n" + " MPU_xTaskGenericNotify_Priv: \n" + " b MPU_xTaskGenericNotifyImpl \n" + " MPU_xTaskGenericNotify_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyWaitImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskGenericNotifyWait_Unpriv \n" + " MPU_xTaskGenericNotifyWait_Priv: \n" + " b MPU_xTaskGenericNotifyWaitImpl \n" + " MPU_xTaskGenericNotifyWait_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGenericNotifyTakeImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_ulTaskGenericNotifyTake_Unpriv \n" + " MPU_ulTaskGenericNotifyTake_Priv: \n" + " b MPU_ulTaskGenericNotifyTakeImpl \n" + " MPU_ulTaskGenericNotifyTake_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyStateClearImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskGenericNotifyStateClear_Unpriv \n" + " MPU_xTaskGenericNotifyStateClear_Priv: \n" + " b MPU_xTaskGenericNotifyStateClearImpl \n" + " MPU_xTaskGenericNotifyStateClear_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGenericNotifyValueClearImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_ulTaskGenericNotifyValueClear_Unpriv \n" + " MPU_ulTaskGenericNotifyValueClear_Priv: \n" + " b MPU_ulTaskGenericNotifyValueClearImpl \n" + " MPU_ulTaskGenericNotifyValueClear_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGenericSendImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xQueueGenericSend_Unpriv \n" + " MPU_xQueueGenericSend_Priv: \n" + " b MPU_xQueueGenericSendImpl \n" + " MPU_xQueueGenericSend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxQueueMessagesWaitingImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_uxQueueMessagesWaiting_Unpriv \n" + " MPU_uxQueueMessagesWaiting_Priv: \n" + " b MPU_uxQueueMessagesWaitingImpl \n" + " MPU_uxQueueMessagesWaiting_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxQueueSpacesAvailableImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_uxQueueSpacesAvailable_Unpriv \n" + " MPU_uxQueueSpacesAvailable_Priv: \n" + " b MPU_uxQueueSpacesAvailableImpl \n" + " MPU_uxQueueSpacesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueReceiveImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xQueueReceive_Unpriv \n" + " MPU_xQueueReceive_Priv: \n" + " b MPU_xQueueReceiveImpl \n" + " MPU_xQueueReceive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueuePeekImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xQueuePeek_Unpriv \n" + " MPU_xQueuePeek_Priv: \n" + " b MPU_xQueuePeekImpl \n" + " MPU_xQueuePeek_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueSemaphoreTakeImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xQueueSemaphoreTake_Unpriv \n" + " MPU_xQueueSemaphoreTake_Priv: \n" + " b MPU_xQueueSemaphoreTakeImpl \n" + " MPU_xQueueSemaphoreTake_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) + + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGetMutexHolderImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xQueueGetMutexHolder_Unpriv \n" + " MPU_xQueueGetMutexHolder_Priv: \n" + " b MPU_xQueueGetMutexHolderImpl \n" + " MPU_xQueueGetMutexHolder_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory" + ); + } + + #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueTakeMutexRecursiveImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xQueueTakeMutexRecursive_Unpriv \n" + " MPU_xQueueTakeMutexRecursive_Priv: \n" + " b MPU_xQueueTakeMutexRecursiveImpl \n" + " MPU_xQueueTakeMutexRecursive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory" + ); + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGiveMutexRecursiveImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xQueueGiveMutexRecursive_Unpriv \n" + " MPU_xQueueGiveMutexRecursive_Priv: \n" + " b MPU_xQueueGiveMutexRecursiveImpl \n" + " MPU_xQueueGiveMutexRecursive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory" + ); + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueSelectFromSetImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xQueueSelectFromSet_Unpriv \n" + " MPU_xQueueSelectFromSet_Priv: \n" + " b MPU_xQueueSelectFromSetImpl \n" + " MPU_xQueueSelectFromSet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory" + ); + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueAddToSetImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xQueueAddToSet_Unpriv \n" + " MPU_xQueueAddToSet_Priv: \n" + " b MPU_xQueueAddToSetImpl \n" + " MPU_xQueueAddToSet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory" + ); + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vQueueAddToRegistryImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vQueueAddToRegistry_Unpriv \n" + " MPU_vQueueAddToRegistry_Priv: \n" + " b MPU_vQueueAddToRegistryImpl \n" + " MPU_vQueueAddToRegistry_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vQueueUnregisterQueueImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vQueueUnregisterQueue_Unpriv \n" + " MPU_vQueueUnregisterQueue_Priv: \n" + " b MPU_vQueueUnregisterQueueImpl \n" + " MPU_vQueueUnregisterQueue_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pcQueueGetNameImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_pcQueueGetName_Unpriv \n" + " MPU_pcQueueGetName_Priv: \n" + " b MPU_pcQueueGetNameImpl \n" + " MPU_pcQueueGetName_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pvTimerGetTimerIDImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_pvTimerGetTimerID_Unpriv \n" + " MPU_pvTimerGetTimerID_Priv: \n" + " b MPU_pvTimerGetTimerIDImpl \n" + " MPU_pvTimerGetTimerID_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTimerSetTimerIDImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vTimerSetTimerID_Unpriv \n" + " MPU_vTimerSetTimerID_Priv: \n" + " b MPU_vTimerSetTimerIDImpl \n" + " MPU_vTimerSetTimerID_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerIsTimerActiveImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTimerIsTimerActive_Unpriv \n" + " MPU_xTimerIsTimerActive_Priv: \n" + " b MPU_xTimerIsTimerActiveImpl \n" + " MPU_xTimerIsTimerActive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv \n" + " MPU_xTimerGetTimerDaemonTaskHandle_Priv: \n" + " b MPU_xTimerGetTimerDaemonTaskHandleImpl \n" + " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGenericCommandFromTaskImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTimerGenericCommandFromTask_Unpriv \n" + " MPU_xTimerGenericCommandFromTask_Priv: \n" + " b MPU_xTimerGenericCommandFromTaskImpl \n" + " MPU_xTimerGenericCommandFromTask_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pcTimerGetNameImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_pcTimerGetName_Unpriv \n" + " MPU_pcTimerGetName_Priv: \n" + " b MPU_pcTimerGetNameImpl \n" + " MPU_pcTimerGetName_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTimerSetReloadModeImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vTimerSetReloadMode_Unpriv \n" + " MPU_vTimerSetReloadMode_Priv: \n" + " b MPU_vTimerSetReloadModeImpl \n" + " MPU_vTimerSetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetReloadModeImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTimerGetReloadMode_Unpriv \n" + " MPU_xTimerGetReloadMode_Priv: \n" + " b MPU_xTimerGetReloadModeImpl \n" + " MPU_xTimerGetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTimerGetReloadModeImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_uxTimerGetReloadMode_Unpriv \n" + " MPU_uxTimerGetReloadMode_Priv: \n" + " b MPU_uxTimerGetReloadModeImpl \n" + " MPU_uxTimerGetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetPeriodImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTimerGetPeriod_Unpriv \n" + " MPU_xTimerGetPeriod_Priv: \n" + " b MPU_xTimerGetPeriodImpl \n" + " MPU_xTimerGetPeriod_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetExpiryTimeImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTimerGetExpiryTime_Unpriv \n" + " MPU_xTimerGetExpiryTime_Priv: \n" + " b MPU_xTimerGetExpiryTimeImpl \n" + " MPU_xTimerGetExpiryTime_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupWaitBitsImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xEventGroupWaitBits_Unpriv \n" + " MPU_xEventGroupWaitBits_Priv: \n" + " b MPU_xEventGroupWaitBitsImpl \n" + " MPU_xEventGroupWaitBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupClearBitsImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xEventGroupClearBits_Unpriv \n" + " MPU_xEventGroupClearBits_Priv: \n" + " b MPU_xEventGroupClearBitsImpl \n" + " MPU_xEventGroupClearBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupSetBitsImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xEventGroupSetBits_Unpriv \n" + " MPU_xEventGroupSetBits_Priv: \n" + " b MPU_xEventGroupSetBitsImpl \n" + " MPU_xEventGroupSetBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupSyncImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xEventGroupSync_Unpriv \n" + " MPU_xEventGroupSync_Priv: \n" + " b MPU_xEventGroupSyncImpl \n" + " MPU_xEventGroupSync_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxEventGroupGetNumberImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_uxEventGroupGetNumber_Unpriv \n" + " MPU_uxEventGroupGetNumber_Priv: \n" + " b MPU_uxEventGroupGetNumberImpl \n" + " MPU_uxEventGroupGetNumber_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory" + ); + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vEventGroupSetNumberImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vEventGroupSetNumber_Unpriv \n" + " MPU_vEventGroupSetNumber_Priv: \n" + " b MPU_vEventGroupSetNumberImpl \n" + " MPU_vEventGroupSetNumber_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory" + ); + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSendImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xStreamBufferSend_Unpriv \n" + " MPU_xStreamBufferSend_Priv: \n" + " b MPU_xStreamBufferSendImpl \n" + " MPU_xStreamBufferSend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferReceiveImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xStreamBufferReceive_Unpriv \n" + " MPU_xStreamBufferReceive_Priv: \n" + " b MPU_xStreamBufferReceiveImpl \n" + " MPU_xStreamBufferReceive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferIsFullImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xStreamBufferIsFull_Unpriv \n" + " MPU_xStreamBufferIsFull_Priv: \n" + " b MPU_xStreamBufferIsFullImpl \n" + " MPU_xStreamBufferIsFull_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferIsEmptyImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xStreamBufferIsEmpty_Unpriv \n" + " MPU_xStreamBufferIsEmpty_Priv: \n" + " b MPU_xStreamBufferIsEmptyImpl \n" + " MPU_xStreamBufferIsEmpty_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSpacesAvailableImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xStreamBufferSpacesAvailable_Unpriv \n" + " MPU_xStreamBufferSpacesAvailable_Priv: \n" + " b MPU_xStreamBufferSpacesAvailableImpl \n" + " MPU_xStreamBufferSpacesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferBytesAvailableImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xStreamBufferBytesAvailable_Unpriv \n" + " MPU_xStreamBufferBytesAvailable_Priv: \n" + " b MPU_xStreamBufferBytesAvailableImpl \n" + " MPU_xStreamBufferBytesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSetTriggerLevelImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xStreamBufferSetTriggerLevel_Unpriv \n" + " MPU_xStreamBufferSetTriggerLevel_Priv: \n" + " b MPU_xStreamBufferSetTriggerLevelImpl \n" + " MPU_xStreamBufferSetTriggerLevel_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferNextMessageLengthBytesImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv \n" + " MPU_xStreamBufferNextMessageLengthBytes_Priv: \n" + " b MPU_xStreamBufferNextMessageLengthBytesImpl \n" + " MPU_xStreamBufferNextMessageLengthBytes_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c new file mode 100644 index 000000000..978d35259 --- /dev/null +++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c @@ -0,0 +1,604 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION + * is defined correctly and privileged functions are placed in correct sections. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Portasm includes. */ +#include "portasm.h" + +/* System call numbers includes. */ +#include "mpu_syscall_numbers.h" + +/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the + * header files. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#if ( configENABLE_FPU == 1 ) + #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0. +#endif + +#if ( configENABLE_MPU == 1 ) + + void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " program_mpu_first_task: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r3] \n" /* r0 = pxCurrentTCB.*/ + " \n" + " dmb \n" /* Complete outstanding transfers before disabling MPU. */ + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " movs r3, #1 \n" /* r3 = 1. */ + " bics r2, r3 \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */ + " str r2, [r1] \n" /* Disable MPU. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */ + " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r1, [r2] \n" /* Program MAIR0. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */ + " \n" + " movs r3, #4 \n" /* r3 = 4. */ + " str r3, [r1] \n" /* Program RNR = 4. */ + " ldmia r0!, {r4-r5} \n" /* Read first set of RBAR/RLAR registers from TCB. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " stmia r2!, {r4-r5} \n" /* Write first set of RBAR/RLAR registers. */ + " movs r3, #5 \n" /* r3 = 5. */ + " str r3, [r1] \n" /* Program RNR = 5. */ + " ldmia r0!, {r4-r5} \n" /* Read second set of RBAR/RLAR registers from TCB. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " stmia r2!, {r4-r5} \n" /* Write second set of RBAR/RLAR registers. */ + " movs r3, #6 \n" /* r3 = 6. */ + " str r3, [r1] \n" /* Program RNR = 6. */ + " ldmia r0!, {r4-r5} \n" /* Read third set of RBAR/RLAR registers from TCB. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " stmia r2!, {r4-r5} \n" /* Write third set of RBAR/RLAR registers. */ + " movs r3, #7 \n" /* r3 = 6. */ + " str r3, [r1] \n" /* Program RNR = 7. */ + " ldmia r0!, {r4-r5} \n" /* Read fourth set of RBAR/RLAR registers from TCB. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " stmia r2!, {r4-r5} \n" /* Write fourth set of RBAR/RLAR registers. */ + " \n" + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " movs r3, #1 \n" /* r3 = 1. */ + " orrs r2, r3 \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */ + " str r2, [r1] \n" /* Enable MPU. */ + " dsb \n" /* Force memory writes before continuing. */ + " \n" + " restore_context_first_task: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* r1 = pxCurrentTCB.*/ + " ldr r2, [r1] \n" /* r2 = Location of saved context in TCB. */ + " \n" + " restore_special_regs_first_task: \n" + " subs r2, #20 \n" + " ldmia r2!, {r0, r3-r6} \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */ + " subs r2, #20 \n" + " msr psp, r3 \n" + " msr control, r5 \n" + " mov lr, r6 \n" + " ldr r4, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " str r0, [r4] \n" /* Restore xSecureContext. */ + " \n" + " restore_general_regs_first_task: \n" + " subs r2, #32 \n" + " ldmia r2!, {r4-r7} \n" /* r4-r7 contain half of the hardware saved context. */ + " stmia r3!, {r4-r7} \n" /* Copy half of the the hardware saved context on the task stack. */ + " ldmia r2!, {r4-r7} \n" /* r4-r7 contain rest half of the hardware saved context. */ + " stmia r3!, {r4-r7} \n" /* Copy rest half of the the hardware saved context on the task stack. */ + " subs r2, #48 \n" + " ldmia r2!, {r4-r7} \n" /* Restore r8-r11. */ + " mov r8, r4 \n" /* r8 = r4. */ + " mov r9, r5 \n" /* r9 = r5. */ + " mov r10, r6 \n" /* r10 = r6. */ + " mov r11, r7 \n" /* r11 = r7. */ + " subs r2, #32 \n" + " ldmia r2!, {r4-r7} \n" /* Restore r4-r7. */ + " subs r2, #16 \n" + " \n" + " restore_context_done_first_task: \n" + " str r2, [r1] \n" /* Save the location where the context should be saved next as the first member of TCB. */ + " bx lr \n" + ); + } + +#else /* configENABLE_MPU */ + + void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r3, [r2] \n" /* Read pxCurrentTCB. */ + " ldr r0, [r3] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + " \n" + " ldm r0!, {r1-r3} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */ + " ldr r4, =xSecureContext \n" + " str r1, [r4] \n" /* Set xSecureContext to this task's value for the same. */ + " movs r1, #2 \n" /* r1 = 2. */ + " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */ + " adds r0, #32 \n" /* Discard everything up to r0. */ + " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */ + " isb \n" + " bx r3 \n" /* Finally, branch to EXC_RETURN. */ + ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* r0 = CONTROL. */ + " movs r1, #1 \n" /* r1 = 1. */ + " tst r0, r1 \n" /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */ + " beq running_privileged \n" /* If the result of previous AND operation was 0, branch. */ + " movs r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + " bx lr \n" /* Return. */ + " running_privileged: \n" + " movs r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + " bx lr \n" /* Return. */ + ::: "r0", "r1", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* Read the CONTROL register. */ + " movs r1, #1 \n" /* r1 = 1. */ + " bics r0, r1 \n" /* Clear the bit 0. */ + " msr control, r0 \n" /* Write back the new CONTROL value. */ + " bx lr \n" /* Return to the caller. */ + ::: "r0", "r1", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vResetPrivilege( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* r0 = CONTROL. */ + " movs r1, #1 \n" /* r1 = 1. */ + " orrs r0, r1 \n" /* r0 = r0 | r1. */ + " msr control, r0 \n" /* CONTROL = r0. */ + " bx lr \n" /* Return to the caller. */ + ::: "r0", "r1", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r0, =0xe000ed08 \n" /* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */ + " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */ + " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */ + " cpsie i \n" /* Globally enable interrupts. */ + " dsb \n" + " isb \n" + " svc %0 \n" /* System call to start the first task. */ + " nop \n" + ::"i" ( portSVC_START_SCHEDULER ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, PRIMASK \n" + " cpsid i \n" + " bx lr \n" + ::: "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " msr PRIMASK, r0 \n" + " bx lr \n" + ::: "memory" + ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern SecureContext_SaveContext \n" + " .extern SecureContext_LoadContext \n" + " \n" + " ldr r3, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " ldr r0, [r3] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later.*/ + " ldr r2, [r1] \n" /* r2 = Location in TCB where the context should be saved. */ + " \n" + " cbz r0, save_ns_context \n" /* No secure context to save. */ + " save_s_context: \n" + " push {r0-r2, lr} \n" + " bl SecureContext_SaveContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r0-r3} \n" /* LR is now in r3. */ + " mov lr, r3 \n" /* Restore LR. */ + " \n" + " save_ns_context: \n" + " mov r3, lr \n" /* r3 = LR (EXC_RETURN). */ + " lsls r3, r3, #25 \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bmi save_special_regs \n" /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + " \n" + " save_general_regs: \n" + " mrs r3, psp \n" + " stmia r2!, {r4-r7} \n" /* Store r4-r7. */ + " mov r4, r8 \n" /* r4 = r8. */ + " mov r5, r9 \n" /* r5 = r9. */ + " mov r6, r10 \n" /* r6 = r10. */ + " mov r7, r11 \n" /* r7 = r11. */ + " stmia r2!, {r4-r7} \n" /* Store r8-r11. */ + " ldmia r3!, {r4-r7} \n" /* Copy half of the hardware saved context into r4-r7. */ + " stmia r2!, {r4-r7} \n" /* Store the hardware saved context. */ + " ldmia r3!, {r4-r7} \n" /* Copy rest half of the hardware saved context into r4-r7. */ + " stmia r2!, {r4-r7} \n" /* Store the hardware saved context. */ + " \n" + " save_special_regs: \n" + " mrs r3, psp \n" /* r3 = PSP. */ + " movs r4, #0 \n" /* r4 = 0. 0 is stored in the PSPLIM slot. */ + " mrs r5, control \n" /* r5 = CONTROL. */ + " mov r6, lr \n" /* r6 = LR. */ + " stmia r2!, {r0, r3-r6} \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ + " str r2, [r1] \n" /* Save the location from where the context should be restored as the first member of TCB. */ + " \n" + " select_next_task: \n" + " cpsid i \n" + " bl vTaskSwitchContext \n" + " cpsie i \n" + " \n" + " program_mpu: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r3] \n" /* r0 = pxCurrentTCB.*/ + " \n" + " dmb \n" /* Complete outstanding transfers before disabling MPU. */ + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " movs r3, #1 \n" /* r3 = 1. */ + " bics r2, r3 \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */ + " str r2, [r1] \n" /* Disable MPU. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */ + " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r1, [r2] \n" /* Program MAIR0. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */ + " \n" + " movs r3, #4 \n" /* r3 = 4. */ + " str r3, [r1] \n" /* Program RNR = 4. */ + " ldmia r0!, {r4-r5} \n" /* Read first set of RBAR/RLAR registers from TCB. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " stmia r2!, {r4-r5} \n" /* Write first set of RBAR/RLAR registers. */ + " movs r3, #5 \n" /* r3 = 5. */ + " str r3, [r1] \n" /* Program RNR = 5. */ + " ldmia r0!, {r4-r5} \n" /* Read second set of RBAR/RLAR registers from TCB. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " stmia r2!, {r4-r5} \n" /* Write second set of RBAR/RLAR registers. */ + " movs r3, #6 \n" /* r3 = 6. */ + " str r3, [r1] \n" /* Program RNR = 6. */ + " ldmia r0!, {r4-r5} \n" /* Read third set of RBAR/RLAR registers from TCB. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " stmia r2!, {r4-r5} \n" /* Write third set of RBAR/RLAR registers. */ + " movs r3, #7 \n" /* r3 = 6. */ + " str r3, [r1] \n" /* Program RNR = 7. */ + " ldmia r0!, {r4-r5} \n" /* Read fourth set of RBAR/RLAR registers from TCB. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " stmia r2!, {r4-r5} \n" /* Write fourth set of RBAR/RLAR registers. */ + " \n" + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " movs r3, #1 \n" /* r3 = 1. */ + " orrs r2, r3 \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */ + " str r2, [r1] \n" /* Enable MPU. */ + " dsb \n" /* Force memory writes before continuing. */ + " \n" + " restore_context: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* r1 = pxCurrentTCB.*/ + " ldr r2, [r1] \n" /* r2 = Location of saved context in TCB. */ + " \n" + " restore_special_regs: \n" + " subs r2, #20 \n" + " ldmia r2!, {r0, r3-r6} \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */ + " subs r2, #20 \n" + " msr psp, r3 \n" + " msr control, r5 \n" + " mov lr, r6 \n" + " ldr r4, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " str r0, [r4] \n" /* Restore xSecureContext. */ + " cbz r0, restore_ns_context \n" /* No secure context to restore. */ + " \n" + " restore_s_context: \n" + " push {r1-r3, lr} \n" + " bl SecureContext_LoadContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r1-r4} \n" /* LR is now in r4. */ + " mov lr, r4 \n" + " \n" + " restore_ns_context: \n" + " mov r0, lr \n" /* r0 = LR (EXC_RETURN). */ + " lsls r0, r0, #25 \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bmi restore_context_done \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + " \n" + " restore_general_regs: \n" + " subs r2, #32 \n" + " ldmia r2!, {r4-r7} \n" /* r4-r7 contain half of the hardware saved context. */ + " stmia r3!, {r4-r7} \n" /* Copy half of the the hardware saved context on the task stack. */ + " ldmia r2!, {r4-r7} \n" /* r4-r7 contain rest half of the hardware saved context. */ + " stmia r3!, {r4-r7} \n" /* Copy rest half of the the hardware saved context on the task stack. */ + " subs r2, #48 \n" + " ldmia r2!, {r4-r7} \n" /* Restore r8-r11. */ + " mov r8, r4 \n" /* r8 = r4. */ + " mov r9, r5 \n" /* r9 = r5. */ + " mov r10, r6 \n" /* r10 = r6. */ + " mov r11, r7 \n" /* r11 = r7. */ + " subs r2, #32 \n" + " ldmia r2!, {r4-r7} \n" /* Restore r4-r7. */ + " subs r2, #16 \n" + " \n" + " restore_context_done: \n" + " str r2, [r1] \n" /* Save the location where the context should be saved next as the first member of TCB. */ + " bx lr \n" + ); + } + +#else /* configENABLE_MPU */ + + void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern SecureContext_SaveContext \n" + " .extern SecureContext_LoadContext \n" + " \n" + " ldr r3, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " ldr r0, [r3] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later.*/ + " mrs r2, psp \n" /* Read PSP in r2. */ + " \n" + " cbz r0, save_ns_context \n" /* No secure context to save. */ + " push {r0-r2, r14} \n" + " bl SecureContext_SaveContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r0-r3} \n" /* LR is now in r3. */ + " mov lr, r3 \n" /* LR = r3. */ + " lsls r1, r3, #25 \n" /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bpl save_ns_context \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* Read pxCurrentTCB. */ + " subs r2, r2, #12 \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */ + " str r2, [r1] \n" /* Save the new top of stack in TCB. */ + " movs r1, #0 \n" /* r1 = 0. 0 is stored in the PSPLIM slot. */ + " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */ + " stmia r2!, {r0, r1, r3} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */ + " b select_next_task \n" + " \n" + " save_ns_context: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* Read pxCurrentTCB. */ + " subs r2, r2, #44 \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */ + " str r2, [r1] \n" /* Save the new top of stack in TCB. */ + " movs r1, #0 \n" /* r1 = 0. 0 is stored in the PSPLIM slot. */ + " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */ + " stmia r2!, {r0, r1, r3-r7} \n" /* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */ + " mov r4, r8 \n" /* r4 = r8. */ + " mov r5, r9 \n" /* r5 = r9. */ + " mov r6, r10 \n" /* r6 = r10. */ + " mov r7, r11 \n" /* r7 = r11. */ + " stmia r2!, {r4-r7} \n" /* Store the high registers that are not saved automatically. */ + " \n" + " select_next_task: \n" + " cpsid i \n" + " bl vTaskSwitchContext \n" + " cpsie i \n" + " \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* Read pxCurrentTCB. */ + " ldr r2, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */ + " \n" + " ldmia r2!, {r0, r1, r4} \n" /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */ + " mov lr, r4 \n" /* LR = r4. */ + " ldr r3, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " str r0, [r3] \n" /* Restore the task's xSecureContext. */ + " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */ + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* Read pxCurrentTCB. */ + " push {r2, r4} \n" + " bl SecureContext_LoadContext \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r2, r4} \n" + " mov lr, r4 \n" /* LR = r4. */ + " lsls r1, r4, #25 \n" /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bpl restore_ns_context \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + " msr psp, r2 \n" /* Remember the new top of stack for the task. */ + " bx lr \n" + " \n" + " restore_ns_context: \n" + " adds r2, r2, #16 \n" /* Move to the high registers. */ + " ldmia r2!, {r4-r7} \n" /* Restore the high registers that are not automatically restored. */ + " mov r8, r4 \n" /* r8 = r4. */ + " mov r9, r5 \n" /* r9 = r5. */ + " mov r10, r6 \n" /* r10 = r6. */ + " mov r11, r7 \n" /* r11 = r7. */ + " msr psp, r2 \n" /* Remember the new top of stack for the task. */ + " subs r2, r2, #32 \n" /* Go back to the low registers. */ + " ldmia r2!, {r4-r7} \n" /* Restore the low registers that are not automatically restored. */ + " bx lr \n" + ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + ".syntax unified \n" + ".extern vPortSVCHandler_C \n" + ".extern vSystemCallEnter \n" + ".extern vSystemCallExit \n" + " \n" + "movs r0, #4 \n" + "mov r1, lr \n" + "tst r0, r1 \n" + "beq stack_on_msp \n" + "stack_on_psp: \n" + " mrs r0, psp \n" + " b route_svc \n" + "stack_on_msp: \n" + " mrs r0, msp \n" + " b route_svc \n" + " \n" + "route_svc: \n" + " ldr r3, [r0, #24] \n" + " subs r3, #2 \n" + " ldrb r2, [r3, #0] \n" + " cmp r2, %0 \n" + " blt system_call_enter \n" + " cmp r2, %1 \n" + " beq system_call_exit \n" + " b vPortSVCHandler_C \n" + " \n" + "system_call_enter: \n" + " b vSystemCallEnter \n" + "system_call_exit: \n" + " b vSystemCallExit \n" + " \n" + : /* No outputs. */ + : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT ) + : "r0", "r1", "r2", "r3", "memory" + ); + } + +#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " movs r0, #4 \n" + " mov r1, lr \n" + " tst r0, r1 \n" + " beq stacking_used_msp \n" + " mrs r0, psp \n" + " ldr r2, =vPortSVCHandler_C \n" + " bx r2 \n" + " stacking_used_msp: \n" + " mrs r0, msp \n" + " ldr r2, =vPortSVCHandler_C \n" + " bx r2 \n" + ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " svc %0 \n" /* Secure context is allocated in the supervisor call. */ + " bx lr \n" /* Return. */ + ::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, [r0] \n" /* The first item in the TCB is the top of the stack. */ + " ldr r1, [r2] \n" /* The first item on the stack is the task's xSecureContext. */ + " cmp r1, #0 \n" /* Raise svc if task's xSecureContext is not NULL. */ + " bne free_secure_context \n" /* Branch if r1 != 0. */ + " bx lr \n" /* There is no secure context (xSecureContext is NULL). */ + " free_secure_context: \n" + " svc %0 \n" /* Secure context is freed in the supervisor call. */ + " bx lr \n" /* Return. */ + ::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory" + ); +} +/*-----------------------------------------------------------*/ diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h new file mode 100644 index 000000000..e81b89228 --- /dev/null +++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h @@ -0,0 +1,85 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M23" +#define portHAS_ARMV8M_MAIN_EXTENSION 0 +#define portARMV8M_MINOR_VERSION 0 +#define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +#if ( configTOTAL_MPU_REGIONS == 16 ) + #error 16 MPU regions are not yet supported for this port. +#endif + +#ifndef configENABLE_MVE + #define configENABLE_MVE 0 +#elif ( configENABLE_MVE != 0 ) + #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M23. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" ) +#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c new file mode 100644 index 000000000..7a62caff0 --- /dev/null +++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/mpu_wrappers_v2_asm.c @@ -0,0 +1,2125 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" +#include "event_groups.h" +#include "stream_buffer.h" +#include "mpu_prototypes.h" +#include "mpu_syscall_numbers.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( INCLUDE_xTaskDelayUntil == 1 ) + + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskDelayUntilImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskDelayUntil_Unpriv \n" + " MPU_xTaskDelayUntil_Priv: \n" + " b MPU_xTaskDelayUntilImpl \n" + " MPU_xTaskDelayUntil_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskAbortDelayImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskAbortDelay_Unpriv \n" + " MPU_xTaskAbortDelay_Priv: \n" + " b MPU_xTaskAbortDelayImpl \n" + " MPU_xTaskAbortDelay_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskDelay == 1 ) + + void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskDelayImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vTaskDelay_Unpriv \n" + " MPU_vTaskDelay_Priv: \n" + " b MPU_vTaskDelayImpl \n" + " MPU_vTaskDelay_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskPriorityGet == 1 ) + + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskPriorityGetImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_uxTaskPriorityGet_Unpriv \n" + " MPU_uxTaskPriorityGet_Priv: \n" + " b MPU_uxTaskPriorityGetImpl \n" + " MPU_uxTaskPriorityGet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_eTaskGetState == 1 ) + + eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_eTaskGetStateImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_eTaskGetState_Unpriv \n" + " MPU_eTaskGetState_Priv: \n" + " b MPU_eTaskGetStateImpl \n" + " MPU_eTaskGetState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory" + ); + } + + #endif /* if ( INCLUDE_eTaskGetState == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskGetInfoImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vTaskGetInfo_Unpriv \n" + " MPU_vTaskGetInfo_Priv: \n" + " b MPU_vTaskGetInfoImpl \n" + " MPU_vTaskGetInfo_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory" + ); + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) + + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetIdleTaskHandleImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskGetIdleTaskHandle_Unpriv \n" + " MPU_xTaskGetIdleTaskHandle_Priv: \n" + " b MPU_xTaskGetIdleTaskHandleImpl \n" + " MPU_xTaskGetIdleTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + + void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSuspendImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vTaskSuspend_Unpriv \n" + " MPU_vTaskSuspend_Priv: \n" + " b MPU_vTaskSuspendImpl \n" + " MPU_vTaskSuspend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + + void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskResumeImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vTaskResume_Unpriv \n" + " MPU_vTaskResume_Priv: \n" + " b MPU_vTaskResumeImpl \n" + " MPU_vTaskResume_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + TickType_t MPU_xTaskGetTickCount( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetTickCountImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskGetTickCount_Unpriv \n" + " MPU_xTaskGetTickCount_Priv: \n" + " b MPU_xTaskGetTickCountImpl \n" + " MPU_xTaskGetTickCount_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetNumberOfTasksImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_uxTaskGetNumberOfTasks_Unpriv \n" + " MPU_uxTaskGetNumberOfTasks_Priv: \n" + " b MPU_uxTaskGetNumberOfTasksImpl \n" + " MPU_uxTaskGetNumberOfTasks_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetRunTimeCounterImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_ulTaskGetRunTimeCounter_Unpriv \n" + " MPU_ulTaskGetRunTimeCounter_Priv: \n" + " b MPU_ulTaskGetRunTimeCounterImpl \n" + " MPU_ulTaskGetRunTimeCounter_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetRunTimePercentImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_ulTaskGetRunTimePercent_Unpriv \n" + " MPU_ulTaskGetRunTimePercent_Priv: \n" + " b MPU_ulTaskGetRunTimePercentImpl \n" + " MPU_ulTaskGetRunTimePercent_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetIdleRunTimePercentImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv \n" + " MPU_ulTaskGetIdleRunTimePercent_Priv: \n" + " b MPU_ulTaskGetIdleRunTimePercentImpl \n" + " MPU_ulTaskGetIdleRunTimePercent_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetIdleRunTimeCounterImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv \n" + " MPU_ulTaskGetIdleRunTimeCounter_Priv: \n" + " b MPU_ulTaskGetIdleRunTimeCounterImpl \n" + " MPU_ulTaskGetIdleRunTimeCounter_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetApplicationTaskTagImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vTaskSetApplicationTaskTag_Unpriv \n" + " MPU_vTaskSetApplicationTaskTag_Priv: \n" + " b MPU_vTaskSetApplicationTaskTagImpl \n" + " MPU_vTaskSetApplicationTaskTag_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory" + ); + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetApplicationTaskTagImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskGetApplicationTaskTag_Unpriv \n" + " MPU_xTaskGetApplicationTaskTag_Priv: \n" + " b MPU_xTaskGetApplicationTaskTagImpl \n" + " MPU_xTaskGetApplicationTaskTag_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory" + ); + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetThreadLocalStoragePointerImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv \n" + " MPU_vTaskSetThreadLocalStoragePointer_Priv: \n" + " b MPU_vTaskSetThreadLocalStoragePointerImpl \n" + " MPU_vTaskSetThreadLocalStoragePointer_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory" + ); + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv \n" + " MPU_pvTaskGetThreadLocalStoragePointer_Priv: \n" + " b MPU_pvTaskGetThreadLocalStoragePointerImpl \n" + " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory" + ); + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetSystemStateImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_uxTaskGetSystemState_Unpriv \n" + " MPU_uxTaskGetSystemState_Priv: \n" + " b MPU_uxTaskGetSystemStateImpl \n" + " MPU_uxTaskGetSystemState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory" + ); + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) + + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetStackHighWaterMarkImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_uxTaskGetStackHighWaterMark_Unpriv \n" + " MPU_uxTaskGetStackHighWaterMark_Priv: \n" + " b MPU_uxTaskGetStackHighWaterMarkImpl \n" + " MPU_uxTaskGetStackHighWaterMark_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetStackHighWaterMark2Impl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv \n" + " MPU_uxTaskGetStackHighWaterMark2_Priv: \n" + " b MPU_uxTaskGetStackHighWaterMark2Impl \n" + " MPU_uxTaskGetStackHighWaterMark2_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) + + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetCurrentTaskHandleImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskGetCurrentTaskHandle_Unpriv \n" + " MPU_xTaskGetCurrentTaskHandle_Priv: \n" + " b MPU_xTaskGetCurrentTaskHandleImpl \n" + " MPU_xTaskGetCurrentTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory" + ); + } + + #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetSchedulerState == 1 ) + + BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetSchedulerStateImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskGetSchedulerState_Unpriv \n" + " MPU_xTaskGetSchedulerState_Priv: \n" + " b MPU_xTaskGetSchedulerStateImpl \n" + " MPU_xTaskGetSchedulerState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */ +/*-----------------------------------------------------------*/ + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetTimeOutStateImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vTaskSetTimeOutState_Unpriv \n" + " MPU_vTaskSetTimeOutState_Priv: \n" + " b MPU_vTaskSetTimeOutStateImpl \n" + " MPU_vTaskSetTimeOutState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskCheckForTimeOutImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskCheckForTimeOut_Unpriv \n" + " MPU_xTaskCheckForTimeOut_Priv: \n" + " b MPU_xTaskCheckForTimeOutImpl \n" + " MPU_xTaskCheckForTimeOut_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskGenericNotify_Unpriv \n" + " MPU_xTaskGenericNotify_Priv: \n" + " b MPU_xTaskGenericNotifyImpl \n" + " MPU_xTaskGenericNotify_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyWaitImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskGenericNotifyWait_Unpriv \n" + " MPU_xTaskGenericNotifyWait_Priv: \n" + " b MPU_xTaskGenericNotifyWaitImpl \n" + " MPU_xTaskGenericNotifyWait_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGenericNotifyTakeImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_ulTaskGenericNotifyTake_Unpriv \n" + " MPU_ulTaskGenericNotifyTake_Priv: \n" + " b MPU_ulTaskGenericNotifyTakeImpl \n" + " MPU_ulTaskGenericNotifyTake_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyStateClearImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskGenericNotifyStateClear_Unpriv \n" + " MPU_xTaskGenericNotifyStateClear_Priv: \n" + " b MPU_xTaskGenericNotifyStateClearImpl \n" + " MPU_xTaskGenericNotifyStateClear_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGenericNotifyValueClearImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_ulTaskGenericNotifyValueClear_Unpriv \n" + " MPU_ulTaskGenericNotifyValueClear_Priv: \n" + " b MPU_ulTaskGenericNotifyValueClearImpl \n" + " MPU_ulTaskGenericNotifyValueClear_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGenericSendImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xQueueGenericSend_Unpriv \n" + " MPU_xQueueGenericSend_Priv: \n" + " b MPU_xQueueGenericSendImpl \n" + " MPU_xQueueGenericSend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxQueueMessagesWaitingImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_uxQueueMessagesWaiting_Unpriv \n" + " MPU_uxQueueMessagesWaiting_Priv: \n" + " b MPU_uxQueueMessagesWaitingImpl \n" + " MPU_uxQueueMessagesWaiting_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxQueueSpacesAvailableImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_uxQueueSpacesAvailable_Unpriv \n" + " MPU_uxQueueSpacesAvailable_Priv: \n" + " b MPU_uxQueueSpacesAvailableImpl \n" + " MPU_uxQueueSpacesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueReceiveImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xQueueReceive_Unpriv \n" + " MPU_xQueueReceive_Priv: \n" + " b MPU_xQueueReceiveImpl \n" + " MPU_xQueueReceive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueuePeekImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xQueuePeek_Unpriv \n" + " MPU_xQueuePeek_Priv: \n" + " b MPU_xQueuePeekImpl \n" + " MPU_xQueuePeek_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueSemaphoreTakeImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xQueueSemaphoreTake_Unpriv \n" + " MPU_xQueueSemaphoreTake_Priv: \n" + " b MPU_xQueueSemaphoreTakeImpl \n" + " MPU_xQueueSemaphoreTake_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) + + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGetMutexHolderImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xQueueGetMutexHolder_Unpriv \n" + " MPU_xQueueGetMutexHolder_Priv: \n" + " b MPU_xQueueGetMutexHolderImpl \n" + " MPU_xQueueGetMutexHolder_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory" + ); + } + + #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueTakeMutexRecursiveImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xQueueTakeMutexRecursive_Unpriv \n" + " MPU_xQueueTakeMutexRecursive_Priv: \n" + " b MPU_xQueueTakeMutexRecursiveImpl \n" + " MPU_xQueueTakeMutexRecursive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory" + ); + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGiveMutexRecursiveImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xQueueGiveMutexRecursive_Unpriv \n" + " MPU_xQueueGiveMutexRecursive_Priv: \n" + " b MPU_xQueueGiveMutexRecursiveImpl \n" + " MPU_xQueueGiveMutexRecursive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory" + ); + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueSelectFromSetImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xQueueSelectFromSet_Unpriv \n" + " MPU_xQueueSelectFromSet_Priv: \n" + " b MPU_xQueueSelectFromSetImpl \n" + " MPU_xQueueSelectFromSet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory" + ); + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueAddToSetImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xQueueAddToSet_Unpriv \n" + " MPU_xQueueAddToSet_Priv: \n" + " b MPU_xQueueAddToSetImpl \n" + " MPU_xQueueAddToSet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory" + ); + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vQueueAddToRegistryImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vQueueAddToRegistry_Unpriv \n" + " MPU_vQueueAddToRegistry_Priv: \n" + " b MPU_vQueueAddToRegistryImpl \n" + " MPU_vQueueAddToRegistry_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vQueueUnregisterQueueImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vQueueUnregisterQueue_Unpriv \n" + " MPU_vQueueUnregisterQueue_Priv: \n" + " b MPU_vQueueUnregisterQueueImpl \n" + " MPU_vQueueUnregisterQueue_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pcQueueGetNameImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_pcQueueGetName_Unpriv \n" + " MPU_pcQueueGetName_Priv: \n" + " b MPU_pcQueueGetNameImpl \n" + " MPU_pcQueueGetName_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pvTimerGetTimerIDImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_pvTimerGetTimerID_Unpriv \n" + " MPU_pvTimerGetTimerID_Priv: \n" + " b MPU_pvTimerGetTimerIDImpl \n" + " MPU_pvTimerGetTimerID_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTimerSetTimerIDImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vTimerSetTimerID_Unpriv \n" + " MPU_vTimerSetTimerID_Priv: \n" + " b MPU_vTimerSetTimerIDImpl \n" + " MPU_vTimerSetTimerID_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerIsTimerActiveImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTimerIsTimerActive_Unpriv \n" + " MPU_xTimerIsTimerActive_Priv: \n" + " b MPU_xTimerIsTimerActiveImpl \n" + " MPU_xTimerIsTimerActive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv \n" + " MPU_xTimerGetTimerDaemonTaskHandle_Priv: \n" + " b MPU_xTimerGetTimerDaemonTaskHandleImpl \n" + " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGenericCommandFromTaskImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTimerGenericCommandFromTask_Unpriv \n" + " MPU_xTimerGenericCommandFromTask_Priv: \n" + " b MPU_xTimerGenericCommandFromTaskImpl \n" + " MPU_xTimerGenericCommandFromTask_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pcTimerGetNameImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_pcTimerGetName_Unpriv \n" + " MPU_pcTimerGetName_Priv: \n" + " b MPU_pcTimerGetNameImpl \n" + " MPU_pcTimerGetName_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTimerSetReloadModeImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vTimerSetReloadMode_Unpriv \n" + " MPU_vTimerSetReloadMode_Priv: \n" + " b MPU_vTimerSetReloadModeImpl \n" + " MPU_vTimerSetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetReloadModeImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTimerGetReloadMode_Unpriv \n" + " MPU_xTimerGetReloadMode_Priv: \n" + " b MPU_xTimerGetReloadModeImpl \n" + " MPU_xTimerGetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTimerGetReloadModeImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_uxTimerGetReloadMode_Unpriv \n" + " MPU_uxTimerGetReloadMode_Priv: \n" + " b MPU_uxTimerGetReloadModeImpl \n" + " MPU_uxTimerGetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetPeriodImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTimerGetPeriod_Unpriv \n" + " MPU_xTimerGetPeriod_Priv: \n" + " b MPU_xTimerGetPeriodImpl \n" + " MPU_xTimerGetPeriod_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetExpiryTimeImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTimerGetExpiryTime_Unpriv \n" + " MPU_xTimerGetExpiryTime_Priv: \n" + " b MPU_xTimerGetExpiryTimeImpl \n" + " MPU_xTimerGetExpiryTime_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupWaitBitsImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xEventGroupWaitBits_Unpriv \n" + " MPU_xEventGroupWaitBits_Priv: \n" + " b MPU_xEventGroupWaitBitsImpl \n" + " MPU_xEventGroupWaitBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupClearBitsImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xEventGroupClearBits_Unpriv \n" + " MPU_xEventGroupClearBits_Priv: \n" + " b MPU_xEventGroupClearBitsImpl \n" + " MPU_xEventGroupClearBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupSetBitsImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xEventGroupSetBits_Unpriv \n" + " MPU_xEventGroupSetBits_Priv: \n" + " b MPU_xEventGroupSetBitsImpl \n" + " MPU_xEventGroupSetBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupSyncImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xEventGroupSync_Unpriv \n" + " MPU_xEventGroupSync_Priv: \n" + " b MPU_xEventGroupSyncImpl \n" + " MPU_xEventGroupSync_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxEventGroupGetNumberImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_uxEventGroupGetNumber_Unpriv \n" + " MPU_uxEventGroupGetNumber_Priv: \n" + " b MPU_uxEventGroupGetNumberImpl \n" + " MPU_uxEventGroupGetNumber_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory" + ); + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vEventGroupSetNumberImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vEventGroupSetNumber_Unpriv \n" + " MPU_vEventGroupSetNumber_Priv: \n" + " b MPU_vEventGroupSetNumberImpl \n" + " MPU_vEventGroupSetNumber_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory" + ); + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSendImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xStreamBufferSend_Unpriv \n" + " MPU_xStreamBufferSend_Priv: \n" + " b MPU_xStreamBufferSendImpl \n" + " MPU_xStreamBufferSend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferReceiveImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xStreamBufferReceive_Unpriv \n" + " MPU_xStreamBufferReceive_Priv: \n" + " b MPU_xStreamBufferReceiveImpl \n" + " MPU_xStreamBufferReceive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferIsFullImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xStreamBufferIsFull_Unpriv \n" + " MPU_xStreamBufferIsFull_Priv: \n" + " b MPU_xStreamBufferIsFullImpl \n" + " MPU_xStreamBufferIsFull_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferIsEmptyImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xStreamBufferIsEmpty_Unpriv \n" + " MPU_xStreamBufferIsEmpty_Priv: \n" + " b MPU_xStreamBufferIsEmptyImpl \n" + " MPU_xStreamBufferIsEmpty_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSpacesAvailableImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xStreamBufferSpacesAvailable_Unpriv \n" + " MPU_xStreamBufferSpacesAvailable_Priv: \n" + " b MPU_xStreamBufferSpacesAvailableImpl \n" + " MPU_xStreamBufferSpacesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferBytesAvailableImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xStreamBufferBytesAvailable_Unpriv \n" + " MPU_xStreamBufferBytesAvailable_Priv: \n" + " b MPU_xStreamBufferBytesAvailableImpl \n" + " MPU_xStreamBufferBytesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSetTriggerLevelImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xStreamBufferSetTriggerLevel_Unpriv \n" + " MPU_xStreamBufferSetTriggerLevel_Priv: \n" + " b MPU_xStreamBufferSetTriggerLevelImpl \n" + " MPU_xStreamBufferSetTriggerLevel_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferNextMessageLengthBytesImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv \n" + " MPU_xStreamBufferNextMessageLengthBytes_Priv: \n" + " b MPU_xStreamBufferNextMessageLengthBytesImpl \n" + " MPU_xStreamBufferNextMessageLengthBytes_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c new file mode 100644 index 000000000..d215f8f73 --- /dev/null +++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c @@ -0,0 +1,516 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION + * is defined correctly and privileged functions are placed in correct sections. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Portasm includes. */ +#include "portasm.h" + +/* System call numbers includes. */ +#include "mpu_syscall_numbers.h" + +/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the + * header files. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#if ( configENABLE_FPU == 1 ) + #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0. +#endif + +#if ( configENABLE_MPU == 1 ) + + void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " program_mpu_first_task: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r3] \n" /* r0 = pxCurrentTCB.*/ + " \n" + " dmb \n" /* Complete outstanding transfers before disabling MPU. */ + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " movs r3, #1 \n" /* r3 = 1. */ + " bics r2, r3 \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */ + " str r2, [r1] \n" /* Disable MPU. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */ + " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r1, [r2] \n" /* Program MAIR0. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */ + " \n" + " movs r3, #4 \n" /* r3 = 4. */ + " str r3, [r1] \n" /* Program RNR = 4. */ + " ldmia r0!, {r4-r5} \n" /* Read first set of RBAR/RLAR registers from TCB. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " stmia r2!, {r4-r5} \n" /* Write first set of RBAR/RLAR registers. */ + " movs r3, #5 \n" /* r3 = 5. */ + " str r3, [r1] \n" /* Program RNR = 5. */ + " ldmia r0!, {r4-r5} \n" /* Read second set of RBAR/RLAR registers from TCB. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " stmia r2!, {r4-r5} \n" /* Write second set of RBAR/RLAR registers. */ + " movs r3, #6 \n" /* r3 = 6. */ + " str r3, [r1] \n" /* Program RNR = 6. */ + " ldmia r0!, {r4-r5} \n" /* Read third set of RBAR/RLAR registers from TCB. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " stmia r2!, {r4-r5} \n" /* Write third set of RBAR/RLAR registers. */ + " movs r3, #7 \n" /* r3 = 6. */ + " str r3, [r1] \n" /* Program RNR = 7. */ + " ldmia r0!, {r4-r5} \n" /* Read fourth set of RBAR/RLAR registers from TCB. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " stmia r2!, {r4-r5} \n" /* Write fourth set of RBAR/RLAR registers. */ + " \n" + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " movs r3, #1 \n" /* r3 = 1. */ + " orrs r2, r3 \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */ + " str r2, [r1] \n" /* Enable MPU. */ + " dsb \n" /* Force memory writes before continuing. */ + " \n" + " restore_context_first_task: \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/ + " ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */ + " \n" + " restore_special_regs_first_task: \n" + " subs r1, #16 \n" + " ldmia r1!, {r2-r5} \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */ + " subs r1, #16 \n" + " msr psp, r2 \n" + #if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + " msr psplim, r3 \n" + #endif + " msr control, r4 \n" + " mov lr, r5 \n" + " \n" + " restore_general_regs_first_task: \n" + " subs r1, #32 \n" + " ldmia r1!, {r4-r7} \n" /* r4-r7 contain half of the hardware saved context. */ + " stmia r2!, {r4-r7} \n" /* Copy half of the the hardware saved context on the task stack. */ + " ldmia r1!, {r4-r7} \n" /* r4-r7 contain rest half of the hardware saved context. */ + " stmia r2!, {r4-r7} \n" /* Copy rest half of the the hardware saved context on the task stack. */ + " subs r1, #48 \n" + " ldmia r1!, {r4-r7} \n" /* Restore r8-r11. */ + " mov r8, r4 \n" /* r8 = r4. */ + " mov r9, r5 \n" /* r9 = r5. */ + " mov r10, r6 \n" /* r10 = r6. */ + " mov r11, r7 \n" /* r11 = r7. */ + " subs r1, #32 \n" + " ldmia r1!, {r4-r7} \n" /* Restore r4-r7. */ + " subs r1, #16 \n" + " \n" + " restore_context_done_first_task: \n" + " str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */ + " bx lr \n" + ); + } + +#else /* configENABLE_MPU */ + + void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + " ldr r0, [r1] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + " \n" + " ldm r0!, {r1-r2} \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */ + #if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + " msr psplim, r1 \n" /* Set this task's PSPLIM value. */ + #endif + " movs r1, #2 \n" /* r1 = 2. */ + " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */ + " adds r0, #32 \n" /* Discard everything up to r0. */ + " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */ + " isb \n" + " bx r2 \n" /* Finally, branch to EXC_RETURN. */ + ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* r0 = CONTROL. */ + " movs r1, #1 \n" /* r1 = 1. */ + " tst r0, r1 \n" /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */ + " beq running_privileged \n" /* If the result of previous AND operation was 0, branch. */ + " movs r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + " bx lr \n" /* Return. */ + " running_privileged: \n" + " movs r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + " bx lr \n" /* Return. */ + ::: "r0", "r1", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* Read the CONTROL register. */ + " movs r1, #1 \n" /* r1 = 1. */ + " bics r0, r1 \n" /* Clear the bit 0. */ + " msr control, r0 \n" /* Write back the new CONTROL value. */ + " bx lr \n" /* Return to the caller. */ + ::: "r0", "r1", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vResetPrivilege( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* r0 = CONTROL. */ + " movs r1, #1 \n" /* r1 = 1. */ + " orrs r0, r1 \n" /* r0 = r0 | r1. */ + " msr control, r0 \n" /* CONTROL = r0. */ + " bx lr \n" /* Return to the caller. */ + ::: "r0", "r1", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r0, =0xe000ed08 \n" /* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */ + " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */ + " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */ + " cpsie i \n" /* Globally enable interrupts. */ + " dsb \n" + " isb \n" + " svc %0 \n" /* System call to start the first task. */ + " nop \n" + ::"i" ( portSVC_START_SCHEDULER ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, PRIMASK \n" + " cpsid i \n" + " bx lr \n" + ::: "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " msr PRIMASK, r0 \n" + " bx lr \n" + ::: "memory" + ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */ + " ldr r1, [r0] \n" /* r1 = Location in TCB where the context should be saved. */ + " mrs r2, psp \n" /* r2 = PSP. */ + " \n" + " save_general_regs: \n" + " stmia r1!, {r4-r7} \n" /* Store r4-r7. */ + " mov r4, r8 \n" /* r4 = r8. */ + " mov r5, r9 \n" /* r5 = r9. */ + " mov r6, r10 \n" /* r6 = r10. */ + " mov r7, r11 \n" /* r7 = r11. */ + " stmia r1!, {r4-r7} \n" /* Store r8-r11. */ + " ldmia r2!, {r4-r7} \n" /* Copy half of the hardware saved context into r4-r7. */ + " stmia r1!, {r4-r7} \n" /* Store the hardware saved context. */ + " ldmia r2!, {r4-r7} \n" /* Copy rest half of the hardware saved context into r4-r7. */ + " stmia r1!, {r4-r7} \n" /* Store the hardware saved context. */ + " \n" + " save_special_regs: \n" + " mrs r2, psp \n" /* r2 = PSP. */ + #if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + " mrs r3, psplim \n" /* r3 = PSPLIM. */ + #else + " movs r3, #0 \n" /* r3 = 0. 0 is stored in the PSPLIM slot. */ + #endif + " mrs r4, control \n" /* r4 = CONTROL. */ + " mov r5, lr \n" /* r5 = LR. */ + " stmia r1!, {r2-r5} \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ + " str r1, [r0] \n" /* Save the location from where the context should be restored as the first member of TCB. */ + " \n" + " select_next_task: \n" + " cpsid i \n" + " bl vTaskSwitchContext \n" + " cpsie i \n" + " \n" + " program_mpu: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r3] \n" /* r0 = pxCurrentTCB.*/ + " \n" + " dmb \n" /* Complete outstanding transfers before disabling MPU. */ + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " movs r3, #1 \n" /* r3 = 1. */ + " bics r2, r3 \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */ + " str r2, [r1] \n" /* Disable MPU. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */ + " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r1, [r2] \n" /* Program MAIR0. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */ + " \n" + " movs r3, #4 \n" /* r3 = 4. */ + " str r3, [r1] \n" /* Program RNR = 4. */ + " ldmia r0!, {r4-r5} \n" /* Read first set of RBAR/RLAR registers from TCB. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " stmia r2!, {r4-r5} \n" /* Write first set of RBAR/RLAR registers. */ + " movs r3, #5 \n" /* r3 = 5. */ + " str r3, [r1] \n" /* Program RNR = 5. */ + " ldmia r0!, {r4-r5} \n" /* Read second set of RBAR/RLAR registers from TCB. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " stmia r2!, {r4-r5} \n" /* Write second set of RBAR/RLAR registers. */ + " movs r3, #6 \n" /* r3 = 6. */ + " str r3, [r1] \n" /* Program RNR = 6. */ + " ldmia r0!, {r4-r5} \n" /* Read third set of RBAR/RLAR registers from TCB. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " stmia r2!, {r4-r5} \n" /* Write third set of RBAR/RLAR registers. */ + " movs r3, #7 \n" /* r3 = 6. */ + " str r3, [r1] \n" /* Program RNR = 7. */ + " ldmia r0!, {r4-r5} \n" /* Read fourth set of RBAR/RLAR registers from TCB. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " stmia r2!, {r4-r5} \n" /* Write fourth set of RBAR/RLAR registers. */ + " \n" + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " movs r3, #1 \n" /* r3 = 1. */ + " orrs r2, r3 \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */ + " str r2, [r1] \n" /* Enable MPU. */ + " dsb \n" /* Force memory writes before continuing. */ + " \n" + " restore_context: \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/ + " ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */ + " \n" + " restore_special_regs: \n" + " subs r1, #16 \n" + " ldmia r1!, {r2-r5} \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */ + " subs r1, #16 \n" + " msr psp, r2 \n" + #if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + " msr psplim, r3 \n" + #endif + " msr control, r4 \n" + " mov lr, r5 \n" + " \n" + " restore_general_regs: \n" + " subs r1, #32 \n" + " ldmia r1!, {r4-r7} \n" /* r4-r7 contain half of the hardware saved context. */ + " stmia r2!, {r4-r7} \n" /* Copy half of the the hardware saved context on the task stack. */ + " ldmia r1!, {r4-r7} \n" /* r4-r7 contain rest half of the hardware saved context. */ + " stmia r2!, {r4-r7} \n" /* Copy rest half of the the hardware saved context on the task stack. */ + " subs r1, #48 \n" + " ldmia r1!, {r4-r7} \n" /* Restore r8-r11. */ + " mov r8, r4 \n" /* r8 = r4. */ + " mov r9, r5 \n" /* r9 = r5. */ + " mov r10, r6 \n" /* r10 = r6. */ + " mov r11, r7 \n" /* r11 = r7. */ + " subs r1, #32 \n" + " ldmia r1!, {r4-r7} \n" /* Restore r4-r7. */ + " subs r1, #16 \n" + " \n" + " restore_context_done: \n" + " str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */ + " bx lr \n" + ); + } + +#else /* configENABLE_MPU */ + + void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, psp \n" /* Read PSP in r0. */ + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + " subs r0, r0, #40 \n" /* Make space for PSPLIM, LR and the remaining registers on the stack. */ + " str r0, [r1] \n" /* Save the new top of stack in TCB. */ + #if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + " mrs r2, psplim \n" /* r2 = PSPLIM. */ + #else + " movs r2, #0 \n" /* r2 = 0. 0 is stored in the PSPLIM slot. */ + #endif + " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */ + " stmia r0!, {r2-r7} \n" /* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */ + " mov r4, r8 \n" /* r4 = r8. */ + " mov r5, r9 \n" /* r5 = r9. */ + " mov r6, r10 \n" /* r6 = r10. */ + " mov r7, r11 \n" /* r7 = r11. */ + " stmia r0!, {r4-r7} \n" /* Store the high registers that are not saved automatically. */ + " \n" + " cpsid i \n" + " bl vTaskSwitchContext \n" + " cpsie i \n" + " \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ + " \n" + " adds r0, r0, #24 \n" /* Move to the high registers. */ + " ldmia r0!, {r4-r7} \n" /* Restore the high registers that are not automatically restored. */ + " mov r8, r4 \n" /* r8 = r4. */ + " mov r9, r5 \n" /* r9 = r5. */ + " mov r10, r6 \n" /* r10 = r6. */ + " mov r11, r7 \n" /* r11 = r7. */ + " msr psp, r0 \n" /* Remember the new top of stack for the task. */ + " subs r0, r0, #40 \n" /* Move to the starting of the saved context. */ + " ldmia r0!, {r2-r7} \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */ + #if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */ + #endif + " bx r3 \n" + ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + ".syntax unified \n" + ".extern vPortSVCHandler_C \n" + ".extern vSystemCallEnter \n" + ".extern vSystemCallExit \n" + " \n" + "movs r0, #4 \n" + "mov r1, lr \n" + "tst r0, r1 \n" + "beq stack_on_msp \n" + "stack_on_psp: \n" + " mrs r0, psp \n" + " b route_svc \n" + "stack_on_msp: \n" + " mrs r0, msp \n" + " b route_svc \n" + " \n" + "route_svc: \n" + " ldr r3, [r0, #24] \n" + " subs r3, #2 \n" + " ldrb r2, [r3, #0] \n" + " cmp r2, %0 \n" + " blt system_call_enter \n" + " cmp r2, %1 \n" + " beq system_call_exit \n" + " b vPortSVCHandler_C \n" + " \n" + "system_call_enter: \n" + " b vSystemCallEnter \n" + "system_call_exit: \n" + " b vSystemCallExit \n" + " \n" + : /* No outputs. */ + : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT ) + : "r0", "r1", "r2", "r3", "memory" + ); + } + +#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " movs r0, #4 \n" + " mov r1, lr \n" + " tst r0, r1 \n" + " beq stacking_used_msp \n" + " mrs r0, psp \n" + " ldr r2, =vPortSVCHandler_C \n" + " bx r2 \n" + " stacking_used_msp: \n" + " mrs r0, msp \n" + " ldr r2, =vPortSVCHandler_C \n" + " bx r2 \n" + ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h new file mode 100644 index 000000000..e81b89228 --- /dev/null +++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h @@ -0,0 +1,85 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M23" +#define portHAS_ARMV8M_MAIN_EXTENSION 0 +#define portARMV8M_MINOR_VERSION 0 +#define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +#if ( configTOTAL_MPU_REGIONS == 16 ) + #error 16 MPU regions are not yet supported for this port. +#endif + +#ifndef configENABLE_MVE + #define configENABLE_MVE 0 +#elif ( configENABLE_MVE != 0 ) + #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M23. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" ) +#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c new file mode 100644 index 000000000..33410a0c3 --- /dev/null +++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/mpu_wrappers_v2_asm.c @@ -0,0 +1,2056 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" +#include "event_groups.h" +#include "stream_buffer.h" +#include "mpu_prototypes.h" +#include "mpu_syscall_numbers.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( INCLUDE_xTaskDelayUntil == 1 ) + + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskDelayUntilImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskDelayUntil_Unpriv \n" + " MPU_xTaskDelayUntil_Priv: \n" + " b MPU_xTaskDelayUntilImpl \n" + " MPU_xTaskDelayUntil_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskAbortDelayImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskAbortDelay_Unpriv \n" + " MPU_xTaskAbortDelay_Priv: \n" + " b MPU_xTaskAbortDelayImpl \n" + " MPU_xTaskAbortDelay_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskDelay == 1 ) + + void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskDelayImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskDelay_Unpriv \n" + " MPU_vTaskDelay_Priv: \n" + " b MPU_vTaskDelayImpl \n" + " MPU_vTaskDelay_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskPriorityGet == 1 ) + + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskPriorityGetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskPriorityGet_Unpriv \n" + " MPU_uxTaskPriorityGet_Priv: \n" + " b MPU_uxTaskPriorityGetImpl \n" + " MPU_uxTaskPriorityGet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_eTaskGetState == 1 ) + + eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_eTaskGetStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_eTaskGetState_Unpriv \n" + " MPU_eTaskGetState_Priv: \n" + " b MPU_eTaskGetStateImpl \n" + " MPU_eTaskGetState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory" + ); + } + + #endif /* if ( INCLUDE_eTaskGetState == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskGetInfoImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskGetInfo_Unpriv \n" + " MPU_vTaskGetInfo_Priv: \n" + " b MPU_vTaskGetInfoImpl \n" + " MPU_vTaskGetInfo_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory" + ); + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) + + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetIdleTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetIdleTaskHandle_Unpriv \n" + " MPU_xTaskGetIdleTaskHandle_Priv: \n" + " b MPU_xTaskGetIdleTaskHandleImpl \n" + " MPU_xTaskGetIdleTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + + void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSuspendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSuspend_Unpriv \n" + " MPU_vTaskSuspend_Priv: \n" + " b MPU_vTaskSuspendImpl \n" + " MPU_vTaskSuspend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + + void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskResumeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskResume_Unpriv \n" + " MPU_vTaskResume_Priv: \n" + " b MPU_vTaskResumeImpl \n" + " MPU_vTaskResume_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + TickType_t MPU_xTaskGetTickCount( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetTickCountImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetTickCount_Unpriv \n" + " MPU_xTaskGetTickCount_Priv: \n" + " b MPU_xTaskGetTickCountImpl \n" + " MPU_xTaskGetTickCount_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetNumberOfTasksImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetNumberOfTasks_Unpriv \n" + " MPU_uxTaskGetNumberOfTasks_Priv: \n" + " b MPU_uxTaskGetNumberOfTasksImpl \n" + " MPU_uxTaskGetNumberOfTasks_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetRunTimeCounterImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetRunTimeCounter_Unpriv \n" + " MPU_ulTaskGetRunTimeCounter_Priv: \n" + " b MPU_ulTaskGetRunTimeCounterImpl \n" + " MPU_ulTaskGetRunTimeCounter_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetRunTimePercentImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetRunTimePercent_Unpriv \n" + " MPU_ulTaskGetRunTimePercent_Priv: \n" + " b MPU_ulTaskGetRunTimePercentImpl \n" + " MPU_ulTaskGetRunTimePercent_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetIdleRunTimePercentImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv \n" + " MPU_ulTaskGetIdleRunTimePercent_Priv: \n" + " b MPU_ulTaskGetIdleRunTimePercentImpl \n" + " MPU_ulTaskGetIdleRunTimePercent_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetIdleRunTimeCounterImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv \n" + " MPU_ulTaskGetIdleRunTimeCounter_Priv: \n" + " b MPU_ulTaskGetIdleRunTimeCounterImpl \n" + " MPU_ulTaskGetIdleRunTimeCounter_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetApplicationTaskTagImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetApplicationTaskTag_Unpriv \n" + " MPU_vTaskSetApplicationTaskTag_Priv: \n" + " b MPU_vTaskSetApplicationTaskTagImpl \n" + " MPU_vTaskSetApplicationTaskTag_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory" + ); + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetApplicationTaskTagImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetApplicationTaskTag_Unpriv \n" + " MPU_xTaskGetApplicationTaskTag_Priv: \n" + " b MPU_xTaskGetApplicationTaskTagImpl \n" + " MPU_xTaskGetApplicationTaskTag_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory" + ); + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetThreadLocalStoragePointerImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv \n" + " MPU_vTaskSetThreadLocalStoragePointer_Priv: \n" + " b MPU_vTaskSetThreadLocalStoragePointerImpl \n" + " MPU_vTaskSetThreadLocalStoragePointer_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory" + ); + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv \n" + " MPU_pvTaskGetThreadLocalStoragePointer_Priv: \n" + " b MPU_pvTaskGetThreadLocalStoragePointerImpl \n" + " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory" + ); + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetSystemStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetSystemState_Unpriv \n" + " MPU_uxTaskGetSystemState_Priv: \n" + " b MPU_uxTaskGetSystemStateImpl \n" + " MPU_uxTaskGetSystemState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory" + ); + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) + + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetStackHighWaterMarkImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetStackHighWaterMark_Unpriv \n" + " MPU_uxTaskGetStackHighWaterMark_Priv: \n" + " b MPU_uxTaskGetStackHighWaterMarkImpl \n" + " MPU_uxTaskGetStackHighWaterMark_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetStackHighWaterMark2Impl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv \n" + " MPU_uxTaskGetStackHighWaterMark2_Priv: \n" + " b MPU_uxTaskGetStackHighWaterMark2Impl \n" + " MPU_uxTaskGetStackHighWaterMark2_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) + + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetCurrentTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetCurrentTaskHandle_Unpriv \n" + " MPU_xTaskGetCurrentTaskHandle_Priv: \n" + " b MPU_xTaskGetCurrentTaskHandleImpl \n" + " MPU_xTaskGetCurrentTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory" + ); + } + + #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetSchedulerState == 1 ) + + BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetSchedulerStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetSchedulerState_Unpriv \n" + " MPU_xTaskGetSchedulerState_Priv: \n" + " b MPU_xTaskGetSchedulerStateImpl \n" + " MPU_xTaskGetSchedulerState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */ +/*-----------------------------------------------------------*/ + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetTimeOutStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetTimeOutState_Unpriv \n" + " MPU_vTaskSetTimeOutState_Priv: \n" + " b MPU_vTaskSetTimeOutStateImpl \n" + " MPU_vTaskSetTimeOutState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskCheckForTimeOutImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskCheckForTimeOut_Unpriv \n" + " MPU_xTaskCheckForTimeOut_Priv: \n" + " b MPU_xTaskCheckForTimeOutImpl \n" + " MPU_xTaskCheckForTimeOut_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotify_Unpriv \n" + " MPU_xTaskGenericNotify_Priv: \n" + " b MPU_xTaskGenericNotifyImpl \n" + " MPU_xTaskGenericNotify_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyWaitImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotifyWait_Unpriv \n" + " MPU_xTaskGenericNotifyWait_Priv: \n" + " b MPU_xTaskGenericNotifyWaitImpl \n" + " MPU_xTaskGenericNotifyWait_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGenericNotifyTakeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGenericNotifyTake_Unpriv \n" + " MPU_ulTaskGenericNotifyTake_Priv: \n" + " b MPU_ulTaskGenericNotifyTakeImpl \n" + " MPU_ulTaskGenericNotifyTake_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyStateClearImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotifyStateClear_Unpriv \n" + " MPU_xTaskGenericNotifyStateClear_Priv: \n" + " b MPU_xTaskGenericNotifyStateClearImpl \n" + " MPU_xTaskGenericNotifyStateClear_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGenericNotifyValueClearImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGenericNotifyValueClear_Unpriv \n" + " MPU_ulTaskGenericNotifyValueClear_Priv: \n" + " b MPU_ulTaskGenericNotifyValueClearImpl \n" + " MPU_ulTaskGenericNotifyValueClear_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGenericSendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGenericSend_Unpriv \n" + " MPU_xQueueGenericSend_Priv: \n" + " b MPU_xQueueGenericSendImpl \n" + " MPU_xQueueGenericSend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxQueueMessagesWaitingImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxQueueMessagesWaiting_Unpriv \n" + " MPU_uxQueueMessagesWaiting_Priv: \n" + " b MPU_uxQueueMessagesWaitingImpl \n" + " MPU_uxQueueMessagesWaiting_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxQueueSpacesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxQueueSpacesAvailable_Unpriv \n" + " MPU_uxQueueSpacesAvailable_Priv: \n" + " b MPU_uxQueueSpacesAvailableImpl \n" + " MPU_uxQueueSpacesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueReceiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueReceive_Unpriv \n" + " MPU_xQueueReceive_Priv: \n" + " b MPU_xQueueReceiveImpl \n" + " MPU_xQueueReceive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueuePeekImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueuePeek_Unpriv \n" + " MPU_xQueuePeek_Priv: \n" + " b MPU_xQueuePeekImpl \n" + " MPU_xQueuePeek_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueSemaphoreTakeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueSemaphoreTake_Unpriv \n" + " MPU_xQueueSemaphoreTake_Priv: \n" + " b MPU_xQueueSemaphoreTakeImpl \n" + " MPU_xQueueSemaphoreTake_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) + + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGetMutexHolderImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGetMutexHolder_Unpriv \n" + " MPU_xQueueGetMutexHolder_Priv: \n" + " b MPU_xQueueGetMutexHolderImpl \n" + " MPU_xQueueGetMutexHolder_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory" + ); + } + + #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueTakeMutexRecursiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueTakeMutexRecursive_Unpriv \n" + " MPU_xQueueTakeMutexRecursive_Priv: \n" + " b MPU_xQueueTakeMutexRecursiveImpl \n" + " MPU_xQueueTakeMutexRecursive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory" + ); + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGiveMutexRecursiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGiveMutexRecursive_Unpriv \n" + " MPU_xQueueGiveMutexRecursive_Priv: \n" + " b MPU_xQueueGiveMutexRecursiveImpl \n" + " MPU_xQueueGiveMutexRecursive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory" + ); + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueSelectFromSetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueSelectFromSet_Unpriv \n" + " MPU_xQueueSelectFromSet_Priv: \n" + " b MPU_xQueueSelectFromSetImpl \n" + " MPU_xQueueSelectFromSet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory" + ); + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueAddToSetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueAddToSet_Unpriv \n" + " MPU_xQueueAddToSet_Priv: \n" + " b MPU_xQueueAddToSetImpl \n" + " MPU_xQueueAddToSet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory" + ); + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vQueueAddToRegistryImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vQueueAddToRegistry_Unpriv \n" + " MPU_vQueueAddToRegistry_Priv: \n" + " b MPU_vQueueAddToRegistryImpl \n" + " MPU_vQueueAddToRegistry_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vQueueUnregisterQueueImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vQueueUnregisterQueue_Unpriv \n" + " MPU_vQueueUnregisterQueue_Priv: \n" + " b MPU_vQueueUnregisterQueueImpl \n" + " MPU_vQueueUnregisterQueue_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pcQueueGetNameImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pcQueueGetName_Unpriv \n" + " MPU_pcQueueGetName_Priv: \n" + " b MPU_pcQueueGetNameImpl \n" + " MPU_pcQueueGetName_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pvTimerGetTimerIDImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pvTimerGetTimerID_Unpriv \n" + " MPU_pvTimerGetTimerID_Priv: \n" + " b MPU_pvTimerGetTimerIDImpl \n" + " MPU_pvTimerGetTimerID_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTimerSetTimerIDImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTimerSetTimerID_Unpriv \n" + " MPU_vTimerSetTimerID_Priv: \n" + " b MPU_vTimerSetTimerIDImpl \n" + " MPU_vTimerSetTimerID_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerIsTimerActiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerIsTimerActive_Unpriv \n" + " MPU_xTimerIsTimerActive_Priv: \n" + " b MPU_xTimerIsTimerActiveImpl \n" + " MPU_xTimerIsTimerActive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv \n" + " MPU_xTimerGetTimerDaemonTaskHandle_Priv: \n" + " b MPU_xTimerGetTimerDaemonTaskHandleImpl \n" + " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGenericCommandFromTaskImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGenericCommandFromTask_Unpriv \n" + " MPU_xTimerGenericCommandFromTask_Priv: \n" + " b MPU_xTimerGenericCommandFromTaskImpl \n" + " MPU_xTimerGenericCommandFromTask_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pcTimerGetNameImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pcTimerGetName_Unpriv \n" + " MPU_pcTimerGetName_Priv: \n" + " b MPU_pcTimerGetNameImpl \n" + " MPU_pcTimerGetName_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTimerSetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTimerSetReloadMode_Unpriv \n" + " MPU_vTimerSetReloadMode_Priv: \n" + " b MPU_vTimerSetReloadModeImpl \n" + " MPU_vTimerSetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetReloadMode_Unpriv \n" + " MPU_xTimerGetReloadMode_Priv: \n" + " b MPU_xTimerGetReloadModeImpl \n" + " MPU_xTimerGetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTimerGetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTimerGetReloadMode_Unpriv \n" + " MPU_uxTimerGetReloadMode_Priv: \n" + " b MPU_uxTimerGetReloadModeImpl \n" + " MPU_uxTimerGetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetPeriodImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetPeriod_Unpriv \n" + " MPU_xTimerGetPeriod_Priv: \n" + " b MPU_xTimerGetPeriodImpl \n" + " MPU_xTimerGetPeriod_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetExpiryTimeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetExpiryTime_Unpriv \n" + " MPU_xTimerGetExpiryTime_Priv: \n" + " b MPU_xTimerGetExpiryTimeImpl \n" + " MPU_xTimerGetExpiryTime_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupWaitBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupWaitBits_Unpriv \n" + " MPU_xEventGroupWaitBits_Priv: \n" + " b MPU_xEventGroupWaitBitsImpl \n" + " MPU_xEventGroupWaitBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupClearBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupClearBits_Unpriv \n" + " MPU_xEventGroupClearBits_Priv: \n" + " b MPU_xEventGroupClearBitsImpl \n" + " MPU_xEventGroupClearBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupSetBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupSetBits_Unpriv \n" + " MPU_xEventGroupSetBits_Priv: \n" + " b MPU_xEventGroupSetBitsImpl \n" + " MPU_xEventGroupSetBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ + +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupSyncImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupSync_Unpriv \n" + " MPU_xEventGroupSync_Priv: \n" + " b MPU_xEventGroupSyncImpl \n" + " MPU_xEventGroupSync_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxEventGroupGetNumberImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxEventGroupGetNumber_Unpriv \n" + " MPU_uxEventGroupGetNumber_Priv: \n" + " b MPU_uxEventGroupGetNumberImpl \n" + " MPU_uxEventGroupGetNumber_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory" + ); + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vEventGroupSetNumberImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vEventGroupSetNumber_Unpriv \n" + " MPU_vEventGroupSetNumber_Priv: \n" + " b MPU_vEventGroupSetNumberImpl \n" + " MPU_vEventGroupSetNumber_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory" + ); + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferSend_Unpriv \n" + " MPU_xStreamBufferSend_Priv: \n" + " b MPU_xStreamBufferSendImpl \n" + " MPU_xStreamBufferSend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferReceiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferReceive_Unpriv \n" + " MPU_xStreamBufferReceive_Priv: \n" + " b MPU_xStreamBufferReceiveImpl \n" + " MPU_xStreamBufferReceive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferIsFullImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferIsFull_Unpriv \n" + " MPU_xStreamBufferIsFull_Priv: \n" + " b MPU_xStreamBufferIsFullImpl \n" + " MPU_xStreamBufferIsFull_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferIsEmptyImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferIsEmpty_Unpriv \n" + " MPU_xStreamBufferIsEmpty_Priv: \n" + " b MPU_xStreamBufferIsEmptyImpl \n" + " MPU_xStreamBufferIsEmpty_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSpacesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferSpacesAvailable_Unpriv \n" + " MPU_xStreamBufferSpacesAvailable_Priv: \n" + " b MPU_xStreamBufferSpacesAvailableImpl \n" + " MPU_xStreamBufferSpacesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferBytesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferBytesAvailable_Unpriv \n" + " MPU_xStreamBufferBytesAvailable_Priv: \n" + " b MPU_xStreamBufferBytesAvailableImpl \n" + " MPU_xStreamBufferBytesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSetTriggerLevelImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferSetTriggerLevel_Unpriv \n" + " MPU_xStreamBufferSetTriggerLevel_Priv: \n" + " b MPU_xStreamBufferSetTriggerLevelImpl \n" + " MPU_xStreamBufferSetTriggerLevel_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferNextMessageLengthBytesImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv \n" + " MPU_xStreamBufferNextMessageLengthBytes_Priv: \n" + " b MPU_xStreamBufferNextMessageLengthBytesImpl \n" + " MPU_xStreamBufferNextMessageLengthBytes_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c new file mode 100644 index 000000000..0ebbe48a4 --- /dev/null +++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c @@ -0,0 +1,621 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION + * is defined correctly and privileged functions are placed in correct sections. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Portasm includes. */ +#include "portasm.h" + +/* System call numbers includes. */ +#include "mpu_syscall_numbers.h" + +/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the + * header files. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#if ( configENABLE_MPU == 1 ) + + void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " program_mpu_first_task: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r3] \n" /* r0 = pxCurrentTCB. */ + " \n" + " dmb \n" /* Complete outstanding transfers before disabling MPU. */ + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + " str r2, [r1] \n" /* Disable MPU. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */ + " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r1, [r2] \n" /* Program MAIR0. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " \n" + " movs r3, #4 \n" /* r3 = 4. */ + " str r3, [r1] \n" /* Program RNR = 4. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + " \n" + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " orr r2, #1 \n" /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */ + " str r2, [r1] \n" /* Enable MPU. */ + " dsb \n" /* Force memory writes before continuing. */ + " \n" + " restore_context_first_task: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* r1 = pxCurrentTCB.*/ + " ldr r2, [r1] \n" /* r2 = Location of saved context in TCB. */ + " \n" + " restore_special_regs_first_task: \n" + #if ( configENABLE_PAC == 1 ) + " ldmdb r2!, {r3-r6} \n" /* Read task's dedicated PAC key from the task's context. */ + " msr PAC_KEY_P_0, r3 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_1, r4 \n" + " msr PAC_KEY_P_2, r5 \n" + " msr PAC_KEY_P_3, r6 \n" + " clrm {r3-r6} \n" /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + " ldmdb r2!, {r0, r3-r5, lr} \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */ + " msr psp, r3 \n" + " msr psplim, r4 \n" + " msr control, r5 \n" + " ldr r4, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " str r0, [r4] \n" /* Restore xSecureContext. */ + " \n" + " restore_general_regs_first_task: \n" + " ldmdb r2!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */ + " stmia r3!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */ + " ldmdb r2!, {r4-r11} \n" /* r4-r11 restored. */ + " \n" + " restore_context_done_first_task: \n" + " str r2, [r1] \n" /* Save the location where the context should be saved next as the first member of TCB. */ + " mov r0, #0 \n" + " msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */ + " bx lr \n" + ); + } + +#else /* configENABLE_MPU */ + + void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r3, [r2] \n" /* Read pxCurrentTCB. */ + " ldr r0, [r3] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + " \n" + #if ( configENABLE_PAC == 1 ) + " ldmia r0!, {r1-r4} \n" /* Read task's dedicated PAC key from stack. */ + " msr PAC_KEY_P_3, r1 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_2, r2 \n" + " msr PAC_KEY_P_1, r3 \n" + " msr PAC_KEY_P_0, r4 \n" + " clrm {r1-r4} \n" /* Clear r1-r4. */ + #endif /* configENABLE_PAC */ + " \n" + " ldm r0!, {r1-r3} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */ + " ldr r4, =xSecureContext \n" + " str r1, [r4] \n" /* Set xSecureContext to this task's value for the same. */ + " msr psplim, r2 \n" /* Set this task's PSPLIM value. */ + " mrs r1, control \n" /* Obtain current control register value. */ + " orrs r1, r1, #2 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */ + " msr control, r1 \n" /* Write back the new control register value. */ + " adds r0, #32 \n" /* Discard everything up to r0. */ + " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */ + " isb \n" + " mov r0, #0 \n" + " msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */ + " bx r3 \n" /* Finally, branch to EXC_RETURN. */ + ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* r0 = CONTROL. */ + " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + " ite ne \n" + " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + " bx lr \n" /* Return. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* Read the CONTROL register. */ + " bic r0, #1 \n" /* Clear the bit 0. */ + " msr control, r0 \n" /* Write back the new CONTROL value. */ + " bx lr \n" /* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vResetPrivilege( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* r0 = CONTROL. */ + " orr r0, #1 \n" /* r0 = r0 | 1. */ + " msr control, r0 \n" /* CONTROL = r0. */ + " bx lr \n" /* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r0, =0xe000ed08 \n" /* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */ + " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */ + " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */ + " cpsie i \n" /* Globally enable interrupts. */ + " cpsie f \n" + " dsb \n" + " isb \n" + " svc %0 \n" /* System call to start the first task. */ + " nop \n" + ::"i" ( portSVC_START_SCHEDULER ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, basepri \n" /* r0 = basepri. Return original basepri value. */ + " mov r1, %0 \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r1 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bx lr \n" /* Return. */ + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " msr basepri, r0 \n" /* basepri = ulMask. */ + " dsb \n" + " isb \n" + " bx lr \n" /* Return. */ + ::: "memory" + ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern SecureContext_SaveContext \n" + " .extern SecureContext_LoadContext \n" + " \n" + " ldr r3, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " ldr r0, [r3] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */ + " ldr r2, [r1] \n" /* r2 = Location in TCB where the context should be saved. */ + " \n" + " cbz r0, save_ns_context \n" /* No secure context to save. */ + " save_s_context: \n" + " push {r0-r2, lr} \n" + " bl SecureContext_SaveContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r0-r2, lr} \n" + " \n" + " save_ns_context: \n" + " mov r3, lr \n" /* r3 = LR (EXC_RETURN). */ + " lsls r3, r3, #25 \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bmi save_special_regs \n" /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + " \n" + " save_general_regs: \n" + " mrs r3, psp \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " add r3, r3, #0x20 \n" /* Move r3 to location where s0 is saved. */ + " tst lr, #0x10 \n" + " ittt eq \n" + " vstmiaeq r2!, {s16-s31} \n" /* Store s16-s31. */ + " vldmiaeq r3, {s0-s16} \n" /* Copy hardware saved FP context into s0-s16. */ + " vstmiaeq r2!, {s0-s16} \n" /* Store hardware saved FP context. */ + " sub r3, r3, #0x20 \n" /* Set r3 back to the location of hardware saved context. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " stmia r2!, {r4-r11} \n" /* Store r4-r11. */ + " ldmia r3, {r4-r11} \n" /* Copy the hardware saved context into r4-r11. */ + " stmia r2!, {r4-r11} \n" /* Store the hardware saved context. */ + " \n" + " save_special_regs: \n" + " mrs r3, psp \n" /* r3 = PSP. */ + " mrs r4, psplim \n" /* r4 = PSPLIM. */ + " mrs r5, control \n" /* r5 = CONTROL. */ + " stmia r2!, {r0, r3-r5, lr} \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ + #if ( configENABLE_PAC == 1 ) + " mrs r3, PAC_KEY_P_0 \n" /* Read task's dedicated PAC key from the PAC key registers. */ + " mrs r4, PAC_KEY_P_1 \n" + " mrs r5, PAC_KEY_P_2 \n" + " mrs r6, PAC_KEY_P_3 \n" + " stmia r2!, {r3-r6} \n" /* Store the task's dedicated PAC key on the task's context. */ + " clrm {r3-r6} \n" /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + " str r2, [r1] \n" /* Save the location from where the context should be restored as the first member of TCB. */ + " \n" + " select_next_task: \n" + " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bl vTaskSwitchContext \n" + " mov r0, #0 \n" /* r0 = 0. */ + " msr basepri, r0 \n" /* Enable interrupts. */ + " \n" + " program_mpu: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r3] \n" /* r0 = pxCurrentTCB.*/ + " \n" + " dmb \n" /* Complete outstanding transfers before disabling MPU. */ + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + " str r2, [r1] \n" /* Disable MPU. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */ + " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r1, [r2] \n" /* Program MAIR0. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " \n" + " movs r3, #4 \n" /* r3 = 4. */ + " str r3, [r1] \n" /* Program RNR = 4. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + " \n" + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " orr r2, #1 \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */ + " str r2, [r1] \n" /* Enable MPU. */ + " dsb \n" /* Force memory writes before continuing. */ + " \n" + " restore_context: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* r1 = pxCurrentTCB.*/ + " ldr r2, [r1] \n" /* r2 = Location of saved context in TCB. */ + " \n" + " restore_special_regs: \n" + #if ( configENABLE_PAC == 1 ) + " ldmdb r2!, {r3-r6} \n" /* Read task's dedicated PAC key from the task's context. */ + " msr PAC_KEY_P_0, r3 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_1, r4 \n" + " msr PAC_KEY_P_2, r5 \n" + " msr PAC_KEY_P_3, r6 \n" + " clrm {r3-r6} \n" /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + " ldmdb r2!, {r0, r3-r5, lr} \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */ + " msr psp, r3 \n" + " msr psplim, r4 \n" + " msr control, r5 \n" + " ldr r4, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " str r0, [r4] \n" /* Restore xSecureContext. */ + " cbz r0, restore_ns_context \n" /* No secure context to restore. */ + " \n" + " restore_s_context: \n" + " push {r1-r3, lr} \n" + " bl SecureContext_LoadContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r1-r3, lr} \n" + " \n" + " restore_ns_context: \n" + " mov r0, lr \n" /* r0 = LR (EXC_RETURN). */ + " lsls r0, r0, #25 \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bmi restore_context_done \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + " \n" + " restore_general_regs: \n" + " ldmdb r2!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */ + " stmia r3!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */ + " ldmdb r2!, {r4-r11} \n" /* r4-r11 restored. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" + " ittt eq \n" + " vldmdbeq r2!, {s0-s16} \n" /* s0-s16 contain hardware saved FP context. */ + " vstmiaeq r3!, {s0-s16} \n" /* Copy hardware saved FP context on the task stack. */ + " vldmdbeq r2!, {s16-s31} \n" /* Restore s16-s31. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + " restore_context_done: \n" + " str r2, [r1] \n" /* Save the location where the context should be saved next as the first member of TCB. */ + " bx lr \n" + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); + } + +#else /* configENABLE_MPU */ + + void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern SecureContext_SaveContext \n" + " .extern SecureContext_LoadContext \n" + " \n" + " ldr r3, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " ldr r0, [r3] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */ + " mrs r2, psp \n" /* Read PSP in r2. */ + " \n" + " cbz r0, save_ns_context \n" /* No secure context to save. */ + " save_s_context: \n" + " push {r0-r2, lr} \n" + " bl SecureContext_SaveContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r0-r2, lr} \n" + " \n" + " save_ns_context: \n" + " mov r3, lr \n" /* r3 = LR (EXC_RETURN). */ + " lsls r3, r3, #25 \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bmi save_special_regs \n" /* If r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used. */ + " \n" + " save_general_regs: \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vstmdbeq r2!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " stmdb r2!, {r4-r11} \n" /* Store the registers that are not saved automatically. */ + " \n" + " save_special_regs: \n" + " mrs r3, psplim \n" /* r3 = PSPLIM. */ + " stmdb r2!, {r0, r3, lr} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */ + #if ( configENABLE_PAC == 1 ) + " mrs r3, PAC_KEY_P_3 \n" /* Read task's dedicated PAC key from the PAC key registers. */ + " mrs r4, PAC_KEY_P_2 \n" + " mrs r5, PAC_KEY_P_1 \n" + " mrs r6, PAC_KEY_P_0 \n" + " stmdb r2!, {r3-r6} \n" /* Store the task's dedicated PAC key on the stack. */ + " clrm {r3-r6} \n" /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + " \n" + " str r2, [r1] \n" /* Save the new top of stack in TCB. */ + " \n" + " select_next_task: \n" + " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bl vTaskSwitchContext \n" + " mov r0, #0 \n" /* r0 = 0. */ + " msr basepri, r0 \n" /* Enable interrupts. */ + " \n" + " restore_context: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* Read pxCurrentTCB. */ + " ldr r2, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */ + " \n" + " restore_special_regs: \n" + #if ( configENABLE_PAC == 1 ) + " ldmia r2!, {r3-r6} \n" /* Read task's dedicated PAC key from stack. */ + " msr PAC_KEY_P_3, r3 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_2, r4 \n" + " msr PAC_KEY_P_1, r5 \n" + " msr PAC_KEY_P_0, r6 \n" + " clrm {r3-r6} \n" /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + " ldmia r2!, {r0, r3, lr} \n" /* Read from stack - r0 = xSecureContext, r3 = PSPLIM and LR restored. */ + " msr psplim, r3 \n" /* Restore the PSPLIM register value for the task. */ + " ldr r3, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " str r0, [r3] \n" /* Restore the task's xSecureContext. */ + " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */ + " \n" + " restore_s_context: \n" + " push {r1-r3, lr} \n" + " bl SecureContext_LoadContext \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r1-r3, lr} \n" + " \n" + " restore_ns_context: \n" + " mov r0, lr \n" /* r0 = LR (EXC_RETURN). */ + " lsls r0, r0, #25 \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bmi restore_context_done \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + " \n" + " restore_general_regs: \n" + " ldmia r2!, {r4-r11} \n" /* Restore the registers that are not automatically restored. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vldmiaeq r2!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + " restore_context_done: \n" + " msr psp, r2 \n" /* Remember the new top of stack for the task. */ + " bx lr \n" + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + ".syntax unified \n" + ".extern vPortSVCHandler_C \n" + ".extern vSystemCallEnter \n" + ".extern vSystemCallExit \n" + " \n" + "tst lr, #4 \n" + "ite eq \n" + "mrseq r0, msp \n" + "mrsne r0, psp \n" + " \n" + "ldr r1, [r0, #24] \n" + "ldrb r2, [r1, #-2] \n" + "cmp r2, %0 \n" + "blt syscall_enter \n" + "cmp r2, %1 \n" + "beq syscall_exit \n" + "b vPortSVCHandler_C \n" + " \n" + "syscall_enter: \n" + " mov r1, lr \n" + " b vSystemCallEnter \n" + " \n" + "syscall_exit: \n" + " mov r1, lr \n" + " b vSystemCallExit \n" + " \n" + : /* No outputs. */ + : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT ) + : "r0", "r1", "r2", "memory" + ); + } + +#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " tst lr, #4 \n" + " ite eq \n" + " mrseq r0, msp \n" + " mrsne r0, psp \n" + " ldr r1, =vPortSVCHandler_C \n" + " bx r1 \n" + ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " svc %0 \n" /* Secure context is allocated in the supervisor call. */ + " bx lr \n" /* Return. */ + ::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, [r0] \n" /* The first item in the TCB is the top of the stack. */ + " ldr r1, [r2] \n" /* The first item on the stack is the task's xSecureContext. */ + " cmp r1, #0 \n" /* Raise svc if task's xSecureContext is not NULL. */ + " it ne \n" + " svcne %0 \n" /* Secure context is freed in the supervisor call. */ + " bx lr \n" /* Return. */ + ::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory" + ); +} +/*-----------------------------------------------------------*/ diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h new file mode 100644 index 000000000..2d435ca0b --- /dev/null +++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h @@ -0,0 +1,81 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M33" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portARMV8M_MINOR_VERSION 0 +#define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +#ifndef configENABLE_MVE + #define configENABLE_MVE 0 +#elif ( configENABLE_MVE != 0 ) + #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M33. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c new file mode 100644 index 000000000..4b984932d --- /dev/null +++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/mpu_wrappers_v2_asm.c @@ -0,0 +1,2055 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" +#include "event_groups.h" +#include "stream_buffer.h" +#include "mpu_prototypes.h" +#include "mpu_syscall_numbers.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( INCLUDE_xTaskDelayUntil == 1 ) + + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskDelayUntilImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskDelayUntil_Unpriv \n" + " MPU_xTaskDelayUntil_Priv: \n" + " b MPU_xTaskDelayUntilImpl \n" + " MPU_xTaskDelayUntil_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskAbortDelayImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskAbortDelay_Unpriv \n" + " MPU_xTaskAbortDelay_Priv: \n" + " b MPU_xTaskAbortDelayImpl \n" + " MPU_xTaskAbortDelay_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskDelay == 1 ) + + void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskDelayImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskDelay_Unpriv \n" + " MPU_vTaskDelay_Priv: \n" + " b MPU_vTaskDelayImpl \n" + " MPU_vTaskDelay_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskPriorityGet == 1 ) + + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskPriorityGetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskPriorityGet_Unpriv \n" + " MPU_uxTaskPriorityGet_Priv: \n" + " b MPU_uxTaskPriorityGetImpl \n" + " MPU_uxTaskPriorityGet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_eTaskGetState == 1 ) + + eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_eTaskGetStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_eTaskGetState_Unpriv \n" + " MPU_eTaskGetState_Priv: \n" + " b MPU_eTaskGetStateImpl \n" + " MPU_eTaskGetState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory" + ); + } + + #endif /* if ( INCLUDE_eTaskGetState == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskGetInfoImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskGetInfo_Unpriv \n" + " MPU_vTaskGetInfo_Priv: \n" + " b MPU_vTaskGetInfoImpl \n" + " MPU_vTaskGetInfo_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory" + ); + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) + + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetIdleTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetIdleTaskHandle_Unpriv \n" + " MPU_xTaskGetIdleTaskHandle_Priv: \n" + " b MPU_xTaskGetIdleTaskHandleImpl \n" + " MPU_xTaskGetIdleTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + + void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSuspendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSuspend_Unpriv \n" + " MPU_vTaskSuspend_Priv: \n" + " b MPU_vTaskSuspendImpl \n" + " MPU_vTaskSuspend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + + void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskResumeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskResume_Unpriv \n" + " MPU_vTaskResume_Priv: \n" + " b MPU_vTaskResumeImpl \n" + " MPU_vTaskResume_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + TickType_t MPU_xTaskGetTickCount( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetTickCountImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetTickCount_Unpriv \n" + " MPU_xTaskGetTickCount_Priv: \n" + " b MPU_xTaskGetTickCountImpl \n" + " MPU_xTaskGetTickCount_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetNumberOfTasksImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetNumberOfTasks_Unpriv \n" + " MPU_uxTaskGetNumberOfTasks_Priv: \n" + " b MPU_uxTaskGetNumberOfTasksImpl \n" + " MPU_uxTaskGetNumberOfTasks_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetRunTimeCounterImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetRunTimeCounter_Unpriv \n" + " MPU_ulTaskGetRunTimeCounter_Priv: \n" + " b MPU_ulTaskGetRunTimeCounterImpl \n" + " MPU_ulTaskGetRunTimeCounter_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetRunTimePercentImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetRunTimePercent_Unpriv \n" + " MPU_ulTaskGetRunTimePercent_Priv: \n" + " b MPU_ulTaskGetRunTimePercentImpl \n" + " MPU_ulTaskGetRunTimePercent_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetIdleRunTimePercentImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv \n" + " MPU_ulTaskGetIdleRunTimePercent_Priv: \n" + " b MPU_ulTaskGetIdleRunTimePercentImpl \n" + " MPU_ulTaskGetIdleRunTimePercent_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetIdleRunTimeCounterImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv \n" + " MPU_ulTaskGetIdleRunTimeCounter_Priv: \n" + " b MPU_ulTaskGetIdleRunTimeCounterImpl \n" + " MPU_ulTaskGetIdleRunTimeCounter_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetApplicationTaskTagImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetApplicationTaskTag_Unpriv \n" + " MPU_vTaskSetApplicationTaskTag_Priv: \n" + " b MPU_vTaskSetApplicationTaskTagImpl \n" + " MPU_vTaskSetApplicationTaskTag_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory" + ); + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetApplicationTaskTagImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetApplicationTaskTag_Unpriv \n" + " MPU_xTaskGetApplicationTaskTag_Priv: \n" + " b MPU_xTaskGetApplicationTaskTagImpl \n" + " MPU_xTaskGetApplicationTaskTag_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory" + ); + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetThreadLocalStoragePointerImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv \n" + " MPU_vTaskSetThreadLocalStoragePointer_Priv: \n" + " b MPU_vTaskSetThreadLocalStoragePointerImpl \n" + " MPU_vTaskSetThreadLocalStoragePointer_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory" + ); + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv \n" + " MPU_pvTaskGetThreadLocalStoragePointer_Priv: \n" + " b MPU_pvTaskGetThreadLocalStoragePointerImpl \n" + " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory" + ); + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetSystemStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetSystemState_Unpriv \n" + " MPU_uxTaskGetSystemState_Priv: \n" + " b MPU_uxTaskGetSystemStateImpl \n" + " MPU_uxTaskGetSystemState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory" + ); + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) + + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetStackHighWaterMarkImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetStackHighWaterMark_Unpriv \n" + " MPU_uxTaskGetStackHighWaterMark_Priv: \n" + " b MPU_uxTaskGetStackHighWaterMarkImpl \n" + " MPU_uxTaskGetStackHighWaterMark_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetStackHighWaterMark2Impl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv \n" + " MPU_uxTaskGetStackHighWaterMark2_Priv: \n" + " b MPU_uxTaskGetStackHighWaterMark2Impl \n" + " MPU_uxTaskGetStackHighWaterMark2_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) + + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetCurrentTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetCurrentTaskHandle_Unpriv \n" + " MPU_xTaskGetCurrentTaskHandle_Priv: \n" + " b MPU_xTaskGetCurrentTaskHandleImpl \n" + " MPU_xTaskGetCurrentTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory" + ); + } + + #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetSchedulerState == 1 ) + + BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetSchedulerStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetSchedulerState_Unpriv \n" + " MPU_xTaskGetSchedulerState_Priv: \n" + " b MPU_xTaskGetSchedulerStateImpl \n" + " MPU_xTaskGetSchedulerState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */ +/*-----------------------------------------------------------*/ + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetTimeOutStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetTimeOutState_Unpriv \n" + " MPU_vTaskSetTimeOutState_Priv: \n" + " b MPU_vTaskSetTimeOutStateImpl \n" + " MPU_vTaskSetTimeOutState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskCheckForTimeOutImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskCheckForTimeOut_Unpriv \n" + " MPU_xTaskCheckForTimeOut_Priv: \n" + " b MPU_xTaskCheckForTimeOutImpl \n" + " MPU_xTaskCheckForTimeOut_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotify_Unpriv \n" + " MPU_xTaskGenericNotify_Priv: \n" + " b MPU_xTaskGenericNotifyImpl \n" + " MPU_xTaskGenericNotify_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyWaitImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotifyWait_Unpriv \n" + " MPU_xTaskGenericNotifyWait_Priv: \n" + " b MPU_xTaskGenericNotifyWaitImpl \n" + " MPU_xTaskGenericNotifyWait_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGenericNotifyTakeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGenericNotifyTake_Unpriv \n" + " MPU_ulTaskGenericNotifyTake_Priv: \n" + " b MPU_ulTaskGenericNotifyTakeImpl \n" + " MPU_ulTaskGenericNotifyTake_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyStateClearImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotifyStateClear_Unpriv \n" + " MPU_xTaskGenericNotifyStateClear_Priv: \n" + " b MPU_xTaskGenericNotifyStateClearImpl \n" + " MPU_xTaskGenericNotifyStateClear_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGenericNotifyValueClearImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGenericNotifyValueClear_Unpriv \n" + " MPU_ulTaskGenericNotifyValueClear_Priv: \n" + " b MPU_ulTaskGenericNotifyValueClearImpl \n" + " MPU_ulTaskGenericNotifyValueClear_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGenericSendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGenericSend_Unpriv \n" + " MPU_xQueueGenericSend_Priv: \n" + " b MPU_xQueueGenericSendImpl \n" + " MPU_xQueueGenericSend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxQueueMessagesWaitingImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxQueueMessagesWaiting_Unpriv \n" + " MPU_uxQueueMessagesWaiting_Priv: \n" + " b MPU_uxQueueMessagesWaitingImpl \n" + " MPU_uxQueueMessagesWaiting_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxQueueSpacesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxQueueSpacesAvailable_Unpriv \n" + " MPU_uxQueueSpacesAvailable_Priv: \n" + " b MPU_uxQueueSpacesAvailableImpl \n" + " MPU_uxQueueSpacesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueReceiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueReceive_Unpriv \n" + " MPU_xQueueReceive_Priv: \n" + " b MPU_xQueueReceiveImpl \n" + " MPU_xQueueReceive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueuePeekImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueuePeek_Unpriv \n" + " MPU_xQueuePeek_Priv: \n" + " b MPU_xQueuePeekImpl \n" + " MPU_xQueuePeek_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueSemaphoreTakeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueSemaphoreTake_Unpriv \n" + " MPU_xQueueSemaphoreTake_Priv: \n" + " b MPU_xQueueSemaphoreTakeImpl \n" + " MPU_xQueueSemaphoreTake_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) + + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGetMutexHolderImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGetMutexHolder_Unpriv \n" + " MPU_xQueueGetMutexHolder_Priv: \n" + " b MPU_xQueueGetMutexHolderImpl \n" + " MPU_xQueueGetMutexHolder_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory" + ); + } + + #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueTakeMutexRecursiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueTakeMutexRecursive_Unpriv \n" + " MPU_xQueueTakeMutexRecursive_Priv: \n" + " b MPU_xQueueTakeMutexRecursiveImpl \n" + " MPU_xQueueTakeMutexRecursive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory" + ); + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGiveMutexRecursiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGiveMutexRecursive_Unpriv \n" + " MPU_xQueueGiveMutexRecursive_Priv: \n" + " b MPU_xQueueGiveMutexRecursiveImpl \n" + " MPU_xQueueGiveMutexRecursive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory" + ); + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueSelectFromSetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueSelectFromSet_Unpriv \n" + " MPU_xQueueSelectFromSet_Priv: \n" + " b MPU_xQueueSelectFromSetImpl \n" + " MPU_xQueueSelectFromSet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory" + ); + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueAddToSetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueAddToSet_Unpriv \n" + " MPU_xQueueAddToSet_Priv: \n" + " b MPU_xQueueAddToSetImpl \n" + " MPU_xQueueAddToSet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory" + ); + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vQueueAddToRegistryImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vQueueAddToRegistry_Unpriv \n" + " MPU_vQueueAddToRegistry_Priv: \n" + " b MPU_vQueueAddToRegistryImpl \n" + " MPU_vQueueAddToRegistry_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vQueueUnregisterQueueImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vQueueUnregisterQueue_Unpriv \n" + " MPU_vQueueUnregisterQueue_Priv: \n" + " b MPU_vQueueUnregisterQueueImpl \n" + " MPU_vQueueUnregisterQueue_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pcQueueGetNameImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pcQueueGetName_Unpriv \n" + " MPU_pcQueueGetName_Priv: \n" + " b MPU_pcQueueGetNameImpl \n" + " MPU_pcQueueGetName_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pvTimerGetTimerIDImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pvTimerGetTimerID_Unpriv \n" + " MPU_pvTimerGetTimerID_Priv: \n" + " b MPU_pvTimerGetTimerIDImpl \n" + " MPU_pvTimerGetTimerID_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTimerSetTimerIDImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTimerSetTimerID_Unpriv \n" + " MPU_vTimerSetTimerID_Priv: \n" + " b MPU_vTimerSetTimerIDImpl \n" + " MPU_vTimerSetTimerID_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerIsTimerActiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerIsTimerActive_Unpriv \n" + " MPU_xTimerIsTimerActive_Priv: \n" + " b MPU_xTimerIsTimerActiveImpl \n" + " MPU_xTimerIsTimerActive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv \n" + " MPU_xTimerGetTimerDaemonTaskHandle_Priv: \n" + " b MPU_xTimerGetTimerDaemonTaskHandleImpl \n" + " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGenericCommandFromTaskImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGenericCommandFromTask_Unpriv \n" + " MPU_xTimerGenericCommandFromTask_Priv: \n" + " b MPU_xTimerGenericCommandFromTaskImpl \n" + " MPU_xTimerGenericCommandFromTask_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pcTimerGetNameImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pcTimerGetName_Unpriv \n" + " MPU_pcTimerGetName_Priv: \n" + " b MPU_pcTimerGetNameImpl \n" + " MPU_pcTimerGetName_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTimerSetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTimerSetReloadMode_Unpriv \n" + " MPU_vTimerSetReloadMode_Priv: \n" + " b MPU_vTimerSetReloadModeImpl \n" + " MPU_vTimerSetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetReloadMode_Unpriv \n" + " MPU_xTimerGetReloadMode_Priv: \n" + " b MPU_xTimerGetReloadModeImpl \n" + " MPU_xTimerGetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTimerGetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTimerGetReloadMode_Unpriv \n" + " MPU_uxTimerGetReloadMode_Priv: \n" + " b MPU_uxTimerGetReloadModeImpl \n" + " MPU_uxTimerGetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetPeriodImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetPeriod_Unpriv \n" + " MPU_xTimerGetPeriod_Priv: \n" + " b MPU_xTimerGetPeriodImpl \n" + " MPU_xTimerGetPeriod_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetExpiryTimeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetExpiryTime_Unpriv \n" + " MPU_xTimerGetExpiryTime_Priv: \n" + " b MPU_xTimerGetExpiryTimeImpl \n" + " MPU_xTimerGetExpiryTime_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupWaitBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupWaitBits_Unpriv \n" + " MPU_xEventGroupWaitBits_Priv: \n" + " b MPU_xEventGroupWaitBitsImpl \n" + " MPU_xEventGroupWaitBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupClearBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupClearBits_Unpriv \n" + " MPU_xEventGroupClearBits_Priv: \n" + " b MPU_xEventGroupClearBitsImpl \n" + " MPU_xEventGroupClearBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupSetBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupSetBits_Unpriv \n" + " MPU_xEventGroupSetBits_Priv: \n" + " b MPU_xEventGroupSetBitsImpl \n" + " MPU_xEventGroupSetBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupSyncImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupSync_Unpriv \n" + " MPU_xEventGroupSync_Priv: \n" + " b MPU_xEventGroupSyncImpl \n" + " MPU_xEventGroupSync_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxEventGroupGetNumberImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxEventGroupGetNumber_Unpriv \n" + " MPU_uxEventGroupGetNumber_Priv: \n" + " b MPU_uxEventGroupGetNumberImpl \n" + " MPU_uxEventGroupGetNumber_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory" + ); + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vEventGroupSetNumberImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vEventGroupSetNumber_Unpriv \n" + " MPU_vEventGroupSetNumber_Priv: \n" + " b MPU_vEventGroupSetNumberImpl \n" + " MPU_vEventGroupSetNumber_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory" + ); + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferSend_Unpriv \n" + " MPU_xStreamBufferSend_Priv: \n" + " b MPU_xStreamBufferSendImpl \n" + " MPU_xStreamBufferSend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferReceiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferReceive_Unpriv \n" + " MPU_xStreamBufferReceive_Priv: \n" + " b MPU_xStreamBufferReceiveImpl \n" + " MPU_xStreamBufferReceive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferIsFullImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferIsFull_Unpriv \n" + " MPU_xStreamBufferIsFull_Priv: \n" + " b MPU_xStreamBufferIsFullImpl \n" + " MPU_xStreamBufferIsFull_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferIsEmptyImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferIsEmpty_Unpriv \n" + " MPU_xStreamBufferIsEmpty_Priv: \n" + " b MPU_xStreamBufferIsEmptyImpl \n" + " MPU_xStreamBufferIsEmpty_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSpacesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferSpacesAvailable_Unpriv \n" + " MPU_xStreamBufferSpacesAvailable_Priv: \n" + " b MPU_xStreamBufferSpacesAvailableImpl \n" + " MPU_xStreamBufferSpacesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferBytesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferBytesAvailable_Unpriv \n" + " MPU_xStreamBufferBytesAvailable_Priv: \n" + " b MPU_xStreamBufferBytesAvailableImpl \n" + " MPU_xStreamBufferBytesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSetTriggerLevelImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferSetTriggerLevel_Unpriv \n" + " MPU_xStreamBufferSetTriggerLevel_Priv: \n" + " b MPU_xStreamBufferSetTriggerLevelImpl \n" + " MPU_xStreamBufferSetTriggerLevel_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferNextMessageLengthBytesImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv \n" + " MPU_xStreamBufferNextMessageLengthBytes_Priv: \n" + " b MPU_xStreamBufferNextMessageLengthBytesImpl \n" + " MPU_xStreamBufferNextMessageLengthBytes_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c new file mode 100644 index 000000000..bc7bb6071 --- /dev/null +++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c @@ -0,0 +1,524 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION + * is defined correctly and privileged functions are placed in correct sections. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Portasm includes. */ +#include "portasm.h" + +/* System call numbers includes. */ +#include "mpu_syscall_numbers.h" + +/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the + * header files. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#if ( configENABLE_MPU == 1 ) + + void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " program_mpu_first_task: \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */ + " \n" + " dmb \n" /* Complete outstanding transfers before disabling MPU. */ + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + " str r2, [r1] \n" /* Disable MPU. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */ + " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r1, [r2] \n" /* Program MAIR0. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " \n" + " movs r3, #4 \n" /* r3 = 4. */ + " str r3, [r1] \n" /* Program RNR = 4. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + " \n" + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " orr r2, #1 \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */ + " str r2, [r1] \n" /* Enable MPU. */ + " dsb \n" /* Force memory writes before continuing. */ + " \n" + " restore_context_first_task: \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/ + " ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */ + " \n" + " restore_special_regs_first_task: \n" + #if ( configENABLE_PAC == 1 ) + " ldmdb r1!, {r2-r5} \n" /* Read task's dedicated PAC key from the task's context. */ + " msr PAC_KEY_P_0, r2 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_1, r3 \n" + " msr PAC_KEY_P_2, r4 \n" + " msr PAC_KEY_P_3, r5 \n" + " clrm {r2-r5} \n" /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + " ldmdb r1!, {r2-r4, lr} \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */ + " msr psp, r2 \n" + " msr psplim, r3 \n" + " msr control, r4 \n" + " \n" + " restore_general_regs_first_task: \n" + " ldmdb r1!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */ + " stmia r2!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */ + " ldmdb r1!, {r4-r11} \n" /* r4-r11 restored. */ + " \n" + " restore_context_done_first_task: \n" + " str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */ + " mov r0, #0 \n" + " msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */ + " bx lr \n" + ); + } + +#else /* configENABLE_MPU */ + + void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + " ldr r0, [r1] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + " \n" + #if ( configENABLE_PAC == 1 ) + " ldmia r0!, {r1-r4} \n" /* Read task's dedicated PAC key from stack. */ + " msr PAC_KEY_P_3, r1 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_2, r2 \n" + " msr PAC_KEY_P_1, r3 \n" + " msr PAC_KEY_P_0, r4 \n" + " clrm {r1-r4} \n" /* Clear r1-r4. */ + #endif /* configENABLE_PAC */ + " \n" + " ldm r0!, {r1-r2} \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */ + " msr psplim, r1 \n" /* Set this task's PSPLIM value. */ + " mrs r1, control \n" /* Obtain current control register value. */ + " orrs r1, r1, #2 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */ + " msr control, r1 \n" /* Write back the new control register value. */ + " adds r0, #32 \n" /* Discard everything up to r0. */ + " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */ + " isb \n" + " mov r0, #0 \n" + " msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */ + " bx r2 \n" /* Finally, branch to EXC_RETURN. */ + ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* r0 = CONTROL. */ + " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + " ite ne \n" + " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + " bx lr \n" /* Return. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* Read the CONTROL register. */ + " bic r0, #1 \n" /* Clear the bit 0. */ + " msr control, r0 \n" /* Write back the new CONTROL value. */ + " bx lr \n" /* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vResetPrivilege( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* r0 = CONTROL. */ + " orr r0, #1 \n" /* r0 = r0 | 1. */ + " msr control, r0 \n" /* CONTROL = r0. */ + " bx lr \n" /* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r0, =0xe000ed08 \n" /* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */ + " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */ + " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */ + " cpsie i \n" /* Globally enable interrupts. */ + " cpsie f \n" + " dsb \n" + " isb \n" + " svc %0 \n" /* System call to start the first task. */ + " nop \n" + ::"i" ( portSVC_START_SCHEDULER ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, basepri \n" /* r0 = basepri. Return original basepri value. */ + " mov r1, %0 \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r1 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bx lr \n" /* Return. */ + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " msr basepri, r0 \n" /* basepri = ulMask. */ + " dsb \n" + " isb \n" + " bx lr \n" /* Return. */ + ::: "memory" + ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */ + " ldr r1, [r0] \n" /* r1 = Location in TCB where the context should be saved. */ + " mrs r2, psp \n" /* r2 = PSP. */ + " \n" + " save_general_regs: \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " add r2, r2, #0x20 \n" /* Move r2 to location where s0 is saved. */ + " tst lr, #0x10 \n" + " ittt eq \n" + " vstmiaeq r1!, {s16-s31} \n" /* Store s16-s31. */ + " vldmiaeq r2, {s0-s16} \n" /* Copy hardware saved FP context into s0-s16. */ + " vstmiaeq r1!, {s0-s16} \n" /* Store hardware saved FP context. */ + " sub r2, r2, #0x20 \n" /* Set r2 back to the location of hardware saved context. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " stmia r1!, {r4-r11} \n" /* Store r4-r11. */ + " ldmia r2, {r4-r11} \n" /* Copy the hardware saved context into r4-r11. */ + " stmia r1!, {r4-r11} \n" /* Store the hardware saved context. */ + " \n" + " save_special_regs: \n" + " mrs r3, psplim \n" /* r3 = PSPLIM. */ + " mrs r4, control \n" /* r4 = CONTROL. */ + " stmia r1!, {r2-r4, lr} \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ + #if ( configENABLE_PAC == 1 ) + " mrs r2, PAC_KEY_P_0 \n" /* Read task's dedicated PAC key from the PAC key registers. */ + " mrs r3, PAC_KEY_P_1 \n" + " mrs r4, PAC_KEY_P_2 \n" + " mrs r5, PAC_KEY_P_3 \n" + " stmia r1!, {r2-r5} \n" /* Store the task's dedicated PAC key on the task's context. */ + " clrm {r2-r5} \n" /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + " str r1, [r0] \n" /* Save the location from where the context should be restored as the first member of TCB. */ + " \n" + " select_next_task: \n" + " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bl vTaskSwitchContext \n" + " mov r0, #0 \n" /* r0 = 0. */ + " msr basepri, r0 \n" /* Enable interrupts. */ + " \n" + " program_mpu: \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */ + " \n" + " dmb \n" /* Complete outstanding transfers before disabling MPU. */ + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + " str r2, [r1] \n" /* Disable MPU. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */ + " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r1, [r2] \n" /* Program MAIR0. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " \n" + " movs r3, #4 \n" /* r3 = 4. */ + " str r3, [r1] \n" /* Program RNR = 4. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + " \n" + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " orr r2, #1 \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */ + " str r2, [r1] \n" /* Enable MPU. */ + " dsb \n" /* Force memory writes before continuing. */ + " \n" + " restore_context: \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/ + " ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */ + " \n" + " restore_special_regs: \n" + #if ( configENABLE_PAC == 1 ) + " ldmdb r1!, {r2-r5} \n" /* Read task's dedicated PAC key from the task's context. */ + " msr PAC_KEY_P_0, r2 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_1, r3 \n" + " msr PAC_KEY_P_2, r4 \n" + " msr PAC_KEY_P_3, r5 \n" + " clrm {r2-r5} \n" /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + " ldmdb r1!, {r2-r4, lr} \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */ + " msr psp, r2 \n" + " msr psplim, r3 \n" + " msr control, r4 \n" + " \n" + " restore_general_regs: \n" + " ldmdb r1!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */ + " stmia r2!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */ + " ldmdb r1!, {r4-r11} \n" /* r4-r11 restored. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" + " ittt eq \n" + " vldmdbeq r1!, {s0-s16} \n" /* s0-s16 contain hardware saved FP context. */ + " vstmiaeq r2!, {s0-s16} \n" /* Copy hardware saved FP context on the task stack. */ + " vldmdbeq r1!, {s16-s31} \n" /* Restore s16-s31. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + " restore_context_done: \n" + " str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */ + " bx lr \n" + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); + } + +#else /* configENABLE_MPU */ + + void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, psp \n" /* Read PSP in r0. */ + " \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vstmdbeq r0!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + " mrs r2, psplim \n" /* r2 = PSPLIM. */ + " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */ + " stmdb r0!, {r2-r11} \n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */ + " \n" + #if ( configENABLE_PAC == 1 ) + " mrs r1, PAC_KEY_P_3 \n" /* Read task's dedicated PAC key from the PAC key registers. */ + " mrs r2, PAC_KEY_P_2 \n" + " mrs r3, PAC_KEY_P_1 \n" + " mrs r4, PAC_KEY_P_0 \n" + " stmdb r0!, {r1-r4} \n" /* Store the task's dedicated PAC key on the stack. */ + " clrm {r1-r4} \n" /* Clear r1-r4. */ + #endif /* configENABLE_PAC */ + " \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + " str r0, [r1] \n" /* Save the new top of stack in TCB. */ + " \n" + " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bl vTaskSwitchContext \n" + " mov r0, #0 \n" /* r0 = 0. */ + " msr basepri, r0 \n" /* Enable interrupts. */ + " \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ + " \n" + #if ( configENABLE_PAC == 1 ) + " ldmia r0!, {r2-r5} \n" /* Read task's dedicated PAC key from stack. */ + " msr PAC_KEY_P_3, r2 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_2, r3 \n" + " msr PAC_KEY_P_1, r4 \n" + " msr PAC_KEY_P_0, r5 \n" + " clrm {r2-r5} \n" /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + " \n" + " ldmia r0!, {r2-r11} \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */ + " \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst r3, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vldmiaeq r0!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */ + " msr psp, r0 \n" /* Remember the new top of stack for the task. */ + " bx r3 \n" + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + ".syntax unified \n" + ".extern vPortSVCHandler_C \n" + ".extern vSystemCallEnter \n" + ".extern vSystemCallExit \n" + " \n" + "tst lr, #4 \n" + "ite eq \n" + "mrseq r0, msp \n" + "mrsne r0, psp \n" + " \n" + "ldr r1, [r0, #24] \n" + "ldrb r2, [r1, #-2] \n" + "cmp r2, %0 \n" + "blt syscall_enter \n" + "cmp r2, %1 \n" + "beq syscall_exit \n" + "b vPortSVCHandler_C \n" + " \n" + "syscall_enter: \n" + " mov r1, lr \n" + " b vSystemCallEnter \n" + " \n" + "syscall_exit: \n" + " mov r1, lr \n" + " b vSystemCallExit \n" + " \n" + : /* No outputs. */ + : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT ) + : "r0", "r1", "r2", "memory" + ); + } + +#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " tst lr, #4 \n" + " ite eq \n" + " mrseq r0, msp \n" + " mrsne r0, psp \n" + " ldr r1, =vPortSVCHandler_C \n" + " bx r1 \n" + ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h new file mode 100644 index 000000000..2d435ca0b --- /dev/null +++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h @@ -0,0 +1,81 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M33" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portARMV8M_MINOR_VERSION 0 +#define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +#ifndef configENABLE_MVE + #define configENABLE_MVE 0 +#elif ( configENABLE_MVE != 0 ) + #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M33. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h new file mode 100644 index 000000000..b886287ac --- /dev/null +++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h @@ -0,0 +1,81 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M35P" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portARMV8M_MINOR_VERSION 0 +#define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +#ifndef configENABLE_MVE + #define configENABLE_MVE 0 +#elif ( configENABLE_MVE != 0 ) + #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M35. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM52/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM52/portmacro.h new file mode 100644 index 000000000..1041a03bd --- /dev/null +++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM52/portmacro.h @@ -0,0 +1,80 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (c) 2025 Arm Technology (China) Co., Ltd.All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_MVE + #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE. +#endif /* configENABLE_MVE */ +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M52" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portARMV8M_MINOR_VERSION 1 +#define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h new file mode 100644 index 000000000..c6a179c52 --- /dev/null +++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h @@ -0,0 +1,79 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_MVE + #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE. +#endif /* configENABLE_MVE */ +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M55" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portARMV8M_MINOR_VERSION 1 +#define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h new file mode 100644 index 000000000..7e14f2696 --- /dev/null +++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h @@ -0,0 +1,79 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_MVE + #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE. +#endif /* configENABLE_MVE */ +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M85" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portARMV8M_MINOR_VERSION 1 +#define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/ARMv8M/non_secure/portable/GCC/ARM_STAR_MC3/portmacro.h b/portable/ARMv8M/non_secure/portable/GCC/ARM_STAR_MC3/portmacro.h new file mode 100644 index 000000000..99538ef82 --- /dev/null +++ b/portable/ARMv8M/non_secure/portable/GCC/ARM_STAR_MC3/portmacro.h @@ -0,0 +1,80 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (c) 2026 Arm Technology (China) Co., Ltd.All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_MVE + #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE. +#endif /* configENABLE_MVE */ +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "STAR-MC3" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portARMV8M_MINOR_VERSION 1 +#define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/mpu_wrappers_v2_asm.S b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/mpu_wrappers_v2_asm.S new file mode 100644 index 000000000..9289bcbc2 --- /dev/null +++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/mpu_wrappers_v2_asm.S @@ -0,0 +1,1312 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + + SECTION freertos_system_calls:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +#include "FreeRTOSConfig.h" +#include "mpu_syscall_numbers.h" + +#ifndef configUSE_MPU_WRAPPERS_V1 + #define configUSE_MPU_WRAPPERS_V1 0 +#endif + +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + PUBLIC MPU_xTaskDelayUntil +MPU_xTaskDelayUntil: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTaskDelayUntil_Unpriv + MPU_xTaskDelayUntil_Priv: + b MPU_xTaskDelayUntilImpl + MPU_xTaskDelayUntil_Unpriv: + svc #SYSTEM_CALL_xTaskDelayUntil +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskAbortDelay +MPU_xTaskAbortDelay: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTaskAbortDelay_Unpriv + MPU_xTaskAbortDelay_Priv: + b MPU_xTaskAbortDelayImpl + MPU_xTaskAbortDelay_Unpriv: + svc #SYSTEM_CALL_xTaskAbortDelay +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskDelay +MPU_vTaskDelay: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vTaskDelay_Unpriv + MPU_vTaskDelay_Priv: + b MPU_vTaskDelayImpl + MPU_vTaskDelay_Unpriv: + svc #SYSTEM_CALL_vTaskDelay +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskPriorityGet +MPU_uxTaskPriorityGet: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_uxTaskPriorityGet_Unpriv + MPU_uxTaskPriorityGet_Priv: + b MPU_uxTaskPriorityGetImpl + MPU_uxTaskPriorityGet_Unpriv: + svc #SYSTEM_CALL_uxTaskPriorityGet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_eTaskGetState +MPU_eTaskGetState: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_eTaskGetState_Unpriv + MPU_eTaskGetState_Priv: + b MPU_eTaskGetStateImpl + MPU_eTaskGetState_Unpriv: + svc #SYSTEM_CALL_eTaskGetState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskGetInfo +MPU_vTaskGetInfo: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vTaskGetInfo_Unpriv + MPU_vTaskGetInfo_Priv: + b MPU_vTaskGetInfoImpl + MPU_vTaskGetInfo_Unpriv: + svc #SYSTEM_CALL_vTaskGetInfo +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetIdleTaskHandle +MPU_xTaskGetIdleTaskHandle: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTaskGetIdleTaskHandle_Unpriv + MPU_xTaskGetIdleTaskHandle_Priv: + b MPU_xTaskGetIdleTaskHandleImpl + MPU_xTaskGetIdleTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTaskGetIdleTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSuspend +MPU_vTaskSuspend: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vTaskSuspend_Unpriv + MPU_vTaskSuspend_Priv: + b MPU_vTaskSuspendImpl + MPU_vTaskSuspend_Unpriv: + svc #SYSTEM_CALL_vTaskSuspend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskResume +MPU_vTaskResume: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vTaskResume_Unpriv + MPU_vTaskResume_Priv: + b MPU_vTaskResumeImpl + MPU_vTaskResume_Unpriv: + svc #SYSTEM_CALL_vTaskResume +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetTickCount +MPU_xTaskGetTickCount: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTaskGetTickCount_Unpriv + MPU_xTaskGetTickCount_Priv: + b MPU_xTaskGetTickCountImpl + MPU_xTaskGetTickCount_Unpriv: + svc #SYSTEM_CALL_xTaskGetTickCount +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetNumberOfTasks +MPU_uxTaskGetNumberOfTasks: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_uxTaskGetNumberOfTasks_Unpriv + MPU_uxTaskGetNumberOfTasks_Priv: + b MPU_uxTaskGetNumberOfTasksImpl + MPU_uxTaskGetNumberOfTasks_Unpriv: + svc #SYSTEM_CALL_uxTaskGetNumberOfTasks +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetRunTimeCounter +MPU_ulTaskGetRunTimeCounter: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_ulTaskGetRunTimeCounter_Unpriv + MPU_ulTaskGetRunTimeCounter_Priv: + b MPU_ulTaskGetRunTimeCounterImpl + MPU_ulTaskGetRunTimeCounter_Unpriv: + svc #SYSTEM_CALL_ulTaskGetRunTimeCounter +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetRunTimePercent +MPU_ulTaskGetRunTimePercent: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_ulTaskGetRunTimePercent_Unpriv + MPU_ulTaskGetRunTimePercent_Priv: + b MPU_ulTaskGetRunTimePercentImpl + MPU_ulTaskGetRunTimePercent_Unpriv: + svc #SYSTEM_CALL_ulTaskGetRunTimePercent +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetIdleRunTimePercent +MPU_ulTaskGetIdleRunTimePercent: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_ulTaskGetIdleRunTimePercent_Unpriv + MPU_ulTaskGetIdleRunTimePercent_Priv: + b MPU_ulTaskGetIdleRunTimePercentImpl + MPU_ulTaskGetIdleRunTimePercent_Unpriv: + svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetIdleRunTimeCounter +MPU_ulTaskGetIdleRunTimeCounter: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv + MPU_ulTaskGetIdleRunTimeCounter_Priv: + b MPU_ulTaskGetIdleRunTimeCounterImpl + MPU_ulTaskGetIdleRunTimeCounter_Unpriv: + svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetApplicationTaskTag +MPU_vTaskSetApplicationTaskTag: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vTaskSetApplicationTaskTag_Unpriv + MPU_vTaskSetApplicationTaskTag_Priv: + b MPU_vTaskSetApplicationTaskTagImpl + MPU_vTaskSetApplicationTaskTag_Unpriv: + svc #SYSTEM_CALL_vTaskSetApplicationTaskTag +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetApplicationTaskTag +MPU_xTaskGetApplicationTaskTag: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTaskGetApplicationTaskTag_Unpriv + MPU_xTaskGetApplicationTaskTag_Priv: + b MPU_xTaskGetApplicationTaskTagImpl + MPU_xTaskGetApplicationTaskTag_Unpriv: + svc #SYSTEM_CALL_xTaskGetApplicationTaskTag +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetThreadLocalStoragePointer +MPU_vTaskSetThreadLocalStoragePointer: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv + MPU_vTaskSetThreadLocalStoragePointer_Priv: + b MPU_vTaskSetThreadLocalStoragePointerImpl + MPU_vTaskSetThreadLocalStoragePointer_Unpriv: + svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pvTaskGetThreadLocalStoragePointer +MPU_pvTaskGetThreadLocalStoragePointer: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv + MPU_pvTaskGetThreadLocalStoragePointer_Priv: + b MPU_pvTaskGetThreadLocalStoragePointerImpl + MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: + svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetSystemState +MPU_uxTaskGetSystemState: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_uxTaskGetSystemState_Unpriv + MPU_uxTaskGetSystemState_Priv: + b MPU_uxTaskGetSystemStateImpl + MPU_uxTaskGetSystemState_Unpriv: + svc #SYSTEM_CALL_uxTaskGetSystemState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetStackHighWaterMark +MPU_uxTaskGetStackHighWaterMark: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_uxTaskGetStackHighWaterMark_Unpriv + MPU_uxTaskGetStackHighWaterMark_Priv: + b MPU_uxTaskGetStackHighWaterMarkImpl + MPU_uxTaskGetStackHighWaterMark_Unpriv: + svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetStackHighWaterMark2 +MPU_uxTaskGetStackHighWaterMark2: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_uxTaskGetStackHighWaterMark2_Unpriv + MPU_uxTaskGetStackHighWaterMark2_Priv: + b MPU_uxTaskGetStackHighWaterMark2Impl + MPU_uxTaskGetStackHighWaterMark2_Unpriv: + svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2 +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetCurrentTaskHandle +MPU_xTaskGetCurrentTaskHandle: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTaskGetCurrentTaskHandle_Unpriv + MPU_xTaskGetCurrentTaskHandle_Priv: + b MPU_xTaskGetCurrentTaskHandleImpl + MPU_xTaskGetCurrentTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetSchedulerState +MPU_xTaskGetSchedulerState: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTaskGetSchedulerState_Unpriv + MPU_xTaskGetSchedulerState_Priv: + b MPU_xTaskGetSchedulerStateImpl + MPU_xTaskGetSchedulerState_Unpriv: + svc #SYSTEM_CALL_xTaskGetSchedulerState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetTimeOutState +MPU_vTaskSetTimeOutState: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vTaskSetTimeOutState_Unpriv + MPU_vTaskSetTimeOutState_Priv: + b MPU_vTaskSetTimeOutStateImpl + MPU_vTaskSetTimeOutState_Unpriv: + svc #SYSTEM_CALL_vTaskSetTimeOutState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskCheckForTimeOut +MPU_xTaskCheckForTimeOut: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTaskCheckForTimeOut_Unpriv + MPU_xTaskCheckForTimeOut_Priv: + b MPU_xTaskCheckForTimeOutImpl + MPU_xTaskCheckForTimeOut_Unpriv: + svc #SYSTEM_CALL_xTaskCheckForTimeOut +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyEntry +MPU_xTaskGenericNotifyEntry: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTaskGenericNotify_Unpriv + MPU_xTaskGenericNotify_Priv: + b MPU_xTaskGenericNotifyImpl + MPU_xTaskGenericNotify_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotify +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyWaitEntry +MPU_xTaskGenericNotifyWaitEntry: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTaskGenericNotifyWait_Unpriv + MPU_xTaskGenericNotifyWait_Priv: + b MPU_xTaskGenericNotifyWaitImpl + MPU_xTaskGenericNotifyWait_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotifyWait +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGenericNotifyTake +MPU_ulTaskGenericNotifyTake: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_ulTaskGenericNotifyTake_Unpriv + MPU_ulTaskGenericNotifyTake_Priv: + b MPU_ulTaskGenericNotifyTakeImpl + MPU_ulTaskGenericNotifyTake_Unpriv: + svc #SYSTEM_CALL_ulTaskGenericNotifyTake +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyStateClear +MPU_xTaskGenericNotifyStateClear: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTaskGenericNotifyStateClear_Unpriv + MPU_xTaskGenericNotifyStateClear_Priv: + b MPU_xTaskGenericNotifyStateClearImpl + MPU_xTaskGenericNotifyStateClear_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotifyStateClear +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGenericNotifyValueClear +MPU_ulTaskGenericNotifyValueClear: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_ulTaskGenericNotifyValueClear_Unpriv + MPU_ulTaskGenericNotifyValueClear_Priv: + b MPU_ulTaskGenericNotifyValueClearImpl + MPU_ulTaskGenericNotifyValueClear_Unpriv: + svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGenericSend +MPU_xQueueGenericSend: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xQueueGenericSend_Unpriv + MPU_xQueueGenericSend_Priv: + b MPU_xQueueGenericSendImpl + MPU_xQueueGenericSend_Unpriv: + svc #SYSTEM_CALL_xQueueGenericSend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxQueueMessagesWaiting +MPU_uxQueueMessagesWaiting: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_uxQueueMessagesWaiting_Unpriv + MPU_uxQueueMessagesWaiting_Priv: + b MPU_uxQueueMessagesWaitingImpl + MPU_uxQueueMessagesWaiting_Unpriv: + svc #SYSTEM_CALL_uxQueueMessagesWaiting +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxQueueSpacesAvailable +MPU_uxQueueSpacesAvailable: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_uxQueueSpacesAvailable_Unpriv + MPU_uxQueueSpacesAvailable_Priv: + b MPU_uxQueueSpacesAvailableImpl + MPU_uxQueueSpacesAvailable_Unpriv: + svc #SYSTEM_CALL_uxQueueSpacesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueReceive +MPU_xQueueReceive: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xQueueReceive_Unpriv + MPU_xQueueReceive_Priv: + b MPU_xQueueReceiveImpl + MPU_xQueueReceive_Unpriv: + svc #SYSTEM_CALL_xQueueReceive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueuePeek +MPU_xQueuePeek: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xQueuePeek_Unpriv + MPU_xQueuePeek_Priv: + b MPU_xQueuePeekImpl + MPU_xQueuePeek_Unpriv: + svc #SYSTEM_CALL_xQueuePeek +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueSemaphoreTake +MPU_xQueueSemaphoreTake: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xQueueSemaphoreTake_Unpriv + MPU_xQueueSemaphoreTake_Priv: + b MPU_xQueueSemaphoreTakeImpl + MPU_xQueueSemaphoreTake_Unpriv: + svc #SYSTEM_CALL_xQueueSemaphoreTake +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGetMutexHolder +MPU_xQueueGetMutexHolder: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xQueueGetMutexHolder_Unpriv + MPU_xQueueGetMutexHolder_Priv: + b MPU_xQueueGetMutexHolderImpl + MPU_xQueueGetMutexHolder_Unpriv: + svc #SYSTEM_CALL_xQueueGetMutexHolder +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueTakeMutexRecursive +MPU_xQueueTakeMutexRecursive: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xQueueTakeMutexRecursive_Unpriv + MPU_xQueueTakeMutexRecursive_Priv: + b MPU_xQueueTakeMutexRecursiveImpl + MPU_xQueueTakeMutexRecursive_Unpriv: + svc #SYSTEM_CALL_xQueueTakeMutexRecursive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGiveMutexRecursive +MPU_xQueueGiveMutexRecursive: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xQueueGiveMutexRecursive_Unpriv + MPU_xQueueGiveMutexRecursive_Priv: + b MPU_xQueueGiveMutexRecursiveImpl + MPU_xQueueGiveMutexRecursive_Unpriv: + svc #SYSTEM_CALL_xQueueGiveMutexRecursive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueSelectFromSet +MPU_xQueueSelectFromSet: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xQueueSelectFromSet_Unpriv + MPU_xQueueSelectFromSet_Priv: + b MPU_xQueueSelectFromSetImpl + MPU_xQueueSelectFromSet_Unpriv: + svc #SYSTEM_CALL_xQueueSelectFromSet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueAddToSet +MPU_xQueueAddToSet: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xQueueAddToSet_Unpriv + MPU_xQueueAddToSet_Priv: + b MPU_xQueueAddToSetImpl + MPU_xQueueAddToSet_Unpriv: + svc #SYSTEM_CALL_xQueueAddToSet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vQueueAddToRegistry +MPU_vQueueAddToRegistry: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vQueueAddToRegistry_Unpriv + MPU_vQueueAddToRegistry_Priv: + b MPU_vQueueAddToRegistryImpl + MPU_vQueueAddToRegistry_Unpriv: + svc #SYSTEM_CALL_vQueueAddToRegistry +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vQueueUnregisterQueue +MPU_vQueueUnregisterQueue: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vQueueUnregisterQueue_Unpriv + MPU_vQueueUnregisterQueue_Priv: + b MPU_vQueueUnregisterQueueImpl + MPU_vQueueUnregisterQueue_Unpriv: + svc #SYSTEM_CALL_vQueueUnregisterQueue +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pcQueueGetName +MPU_pcQueueGetName: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_pcQueueGetName_Unpriv + MPU_pcQueueGetName_Priv: + b MPU_pcQueueGetNameImpl + MPU_pcQueueGetName_Unpriv: + svc #SYSTEM_CALL_pcQueueGetName +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pvTimerGetTimerID +MPU_pvTimerGetTimerID: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_pvTimerGetTimerID_Unpriv + MPU_pvTimerGetTimerID_Priv: + b MPU_pvTimerGetTimerIDImpl + MPU_pvTimerGetTimerID_Unpriv: + svc #SYSTEM_CALL_pvTimerGetTimerID +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTimerSetTimerID +MPU_vTimerSetTimerID: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vTimerSetTimerID_Unpriv + MPU_vTimerSetTimerID_Priv: + b MPU_vTimerSetTimerIDImpl + MPU_vTimerSetTimerID_Unpriv: + svc #SYSTEM_CALL_vTimerSetTimerID +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerIsTimerActive +MPU_xTimerIsTimerActive: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTimerIsTimerActive_Unpriv + MPU_xTimerIsTimerActive_Priv: + b MPU_xTimerIsTimerActiveImpl + MPU_xTimerIsTimerActive_Unpriv: + svc #SYSTEM_CALL_xTimerIsTimerActive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetTimerDaemonTaskHandle +MPU_xTimerGetTimerDaemonTaskHandle: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv + MPU_xTimerGetTimerDaemonTaskHandle_Priv: + b MPU_xTimerGetTimerDaemonTaskHandleImpl + MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGenericCommandFromTaskEntry +MPU_xTimerGenericCommandFromTaskEntry: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTimerGenericCommandFromTask_Unpriv + MPU_xTimerGenericCommandFromTask_Priv: + b MPU_xTimerGenericCommandFromTaskImpl + MPU_xTimerGenericCommandFromTask_Unpriv: + svc #SYSTEM_CALL_xTimerGenericCommandFromTask +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pcTimerGetName +MPU_pcTimerGetName: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_pcTimerGetName_Unpriv + MPU_pcTimerGetName_Priv: + b MPU_pcTimerGetNameImpl + MPU_pcTimerGetName_Unpriv: + svc #SYSTEM_CALL_pcTimerGetName +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTimerSetReloadMode +MPU_vTimerSetReloadMode: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vTimerSetReloadMode_Unpriv + MPU_vTimerSetReloadMode_Priv: + b MPU_vTimerSetReloadModeImpl + MPU_vTimerSetReloadMode_Unpriv: + svc #SYSTEM_CALL_vTimerSetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetReloadMode +MPU_xTimerGetReloadMode: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTimerGetReloadMode_Unpriv + MPU_xTimerGetReloadMode_Priv: + b MPU_xTimerGetReloadModeImpl + MPU_xTimerGetReloadMode_Unpriv: + svc #SYSTEM_CALL_xTimerGetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTimerGetReloadMode +MPU_uxTimerGetReloadMode: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_uxTimerGetReloadMode_Unpriv + MPU_uxTimerGetReloadMode_Priv: + b MPU_uxTimerGetReloadModeImpl + MPU_uxTimerGetReloadMode_Unpriv: + svc #SYSTEM_CALL_uxTimerGetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetPeriod +MPU_xTimerGetPeriod: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTimerGetPeriod_Unpriv + MPU_xTimerGetPeriod_Priv: + b MPU_xTimerGetPeriodImpl + MPU_xTimerGetPeriod_Unpriv: + svc #SYSTEM_CALL_xTimerGetPeriod +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetExpiryTime +MPU_xTimerGetExpiryTime: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTimerGetExpiryTime_Unpriv + MPU_xTimerGetExpiryTime_Priv: + b MPU_xTimerGetExpiryTimeImpl + MPU_xTimerGetExpiryTime_Unpriv: + svc #SYSTEM_CALL_xTimerGetExpiryTime +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupWaitBitsEntry +MPU_xEventGroupWaitBitsEntry: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xEventGroupWaitBits_Unpriv + MPU_xEventGroupWaitBits_Priv: + b MPU_xEventGroupWaitBitsImpl + MPU_xEventGroupWaitBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupWaitBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupClearBits +MPU_xEventGroupClearBits: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xEventGroupClearBits_Unpriv + MPU_xEventGroupClearBits_Priv: + b MPU_xEventGroupClearBitsImpl + MPU_xEventGroupClearBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupClearBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupSetBits +MPU_xEventGroupSetBits: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xEventGroupSetBits_Unpriv + MPU_xEventGroupSetBits_Priv: + b MPU_xEventGroupSetBitsImpl + MPU_xEventGroupSetBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupSetBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupSync +MPU_xEventGroupSync: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xEventGroupSync_Unpriv + MPU_xEventGroupSync_Priv: + b MPU_xEventGroupSyncImpl + MPU_xEventGroupSync_Unpriv: + svc #SYSTEM_CALL_xEventGroupSync +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxEventGroupGetNumber +MPU_uxEventGroupGetNumber: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_uxEventGroupGetNumber_Unpriv + MPU_uxEventGroupGetNumber_Priv: + b MPU_uxEventGroupGetNumberImpl + MPU_uxEventGroupGetNumber_Unpriv: + svc #SYSTEM_CALL_uxEventGroupGetNumber +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vEventGroupSetNumber +MPU_vEventGroupSetNumber: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vEventGroupSetNumber_Unpriv + MPU_vEventGroupSetNumber_Priv: + b MPU_vEventGroupSetNumberImpl + MPU_vEventGroupSetNumber_Unpriv: + svc #SYSTEM_CALL_vEventGroupSetNumber +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSend +MPU_xStreamBufferSend: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xStreamBufferSend_Unpriv + MPU_xStreamBufferSend_Priv: + b MPU_xStreamBufferSendImpl + MPU_xStreamBufferSend_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferReceive +MPU_xStreamBufferReceive: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xStreamBufferReceive_Unpriv + MPU_xStreamBufferReceive_Priv: + b MPU_xStreamBufferReceiveImpl + MPU_xStreamBufferReceive_Unpriv: + svc #SYSTEM_CALL_xStreamBufferReceive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferIsFull +MPU_xStreamBufferIsFull: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xStreamBufferIsFull_Unpriv + MPU_xStreamBufferIsFull_Priv: + b MPU_xStreamBufferIsFullImpl + MPU_xStreamBufferIsFull_Unpriv: + svc #SYSTEM_CALL_xStreamBufferIsFull +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferIsEmpty +MPU_xStreamBufferIsEmpty: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xStreamBufferIsEmpty_Unpriv + MPU_xStreamBufferIsEmpty_Priv: + b MPU_xStreamBufferIsEmptyImpl + MPU_xStreamBufferIsEmpty_Unpriv: + svc #SYSTEM_CALL_xStreamBufferIsEmpty +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSpacesAvailable +MPU_xStreamBufferSpacesAvailable: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xStreamBufferSpacesAvailable_Unpriv + MPU_xStreamBufferSpacesAvailable_Priv: + b MPU_xStreamBufferSpacesAvailableImpl + MPU_xStreamBufferSpacesAvailable_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSpacesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferBytesAvailable +MPU_xStreamBufferBytesAvailable: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xStreamBufferBytesAvailable_Unpriv + MPU_xStreamBufferBytesAvailable_Priv: + b MPU_xStreamBufferBytesAvailableImpl + MPU_xStreamBufferBytesAvailable_Unpriv: + svc #SYSTEM_CALL_xStreamBufferBytesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSetTriggerLevel +MPU_xStreamBufferSetTriggerLevel: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xStreamBufferSetTriggerLevel_Unpriv + MPU_xStreamBufferSetTriggerLevel_Priv: + b MPU_xStreamBufferSetTriggerLevelImpl + MPU_xStreamBufferSetTriggerLevel_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferNextMessageLengthBytes +MPU_xStreamBufferNextMessageLengthBytes: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv + MPU_xStreamBufferNextMessageLengthBytes_Priv: + b MPU_xStreamBufferNextMessageLengthBytesImpl + MPU_xStreamBufferNextMessageLengthBytes_Unpriv: + svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes +/*-----------------------------------------------------------*/ + +/* Default weak implementations in case one is not available from + * mpu_wrappers because of config options. */ + + PUBWEAK MPU_xTaskDelayUntilImpl +MPU_xTaskDelayUntilImpl: + b MPU_xTaskDelayUntilImpl + + PUBWEAK MPU_xTaskAbortDelayImpl +MPU_xTaskAbortDelayImpl: + b MPU_xTaskAbortDelayImpl + + PUBWEAK MPU_vTaskDelayImpl +MPU_vTaskDelayImpl: + b MPU_vTaskDelayImpl + + PUBWEAK MPU_uxTaskPriorityGetImpl +MPU_uxTaskPriorityGetImpl: + b MPU_uxTaskPriorityGetImpl + + PUBWEAK MPU_eTaskGetStateImpl +MPU_eTaskGetStateImpl: + b MPU_eTaskGetStateImpl + + PUBWEAK MPU_vTaskGetInfoImpl +MPU_vTaskGetInfoImpl: + b MPU_vTaskGetInfoImpl + + PUBWEAK MPU_xTaskGetIdleTaskHandleImpl +MPU_xTaskGetIdleTaskHandleImpl: + b MPU_xTaskGetIdleTaskHandleImpl + + PUBWEAK MPU_vTaskSuspendImpl +MPU_vTaskSuspendImpl: + b MPU_vTaskSuspendImpl + + PUBWEAK MPU_vTaskResumeImpl +MPU_vTaskResumeImpl: + b MPU_vTaskResumeImpl + + PUBWEAK MPU_xTaskGetTickCountImpl +MPU_xTaskGetTickCountImpl: + b MPU_xTaskGetTickCountImpl + + PUBWEAK MPU_uxTaskGetNumberOfTasksImpl +MPU_uxTaskGetNumberOfTasksImpl: + b MPU_uxTaskGetNumberOfTasksImpl + + PUBWEAK MPU_ulTaskGetRunTimeCounterImpl +MPU_ulTaskGetRunTimeCounterImpl: + b MPU_ulTaskGetRunTimeCounterImpl + + PUBWEAK MPU_ulTaskGetRunTimePercentImpl +MPU_ulTaskGetRunTimePercentImpl: + b MPU_ulTaskGetRunTimePercentImpl + + PUBWEAK MPU_ulTaskGetIdleRunTimePercentImpl +MPU_ulTaskGetIdleRunTimePercentImpl: + b MPU_ulTaskGetIdleRunTimePercentImpl + + PUBWEAK MPU_ulTaskGetIdleRunTimeCounterImpl +MPU_ulTaskGetIdleRunTimeCounterImpl: + b MPU_ulTaskGetIdleRunTimeCounterImpl + + PUBWEAK MPU_vTaskSetApplicationTaskTagImpl +MPU_vTaskSetApplicationTaskTagImpl: + b MPU_vTaskSetApplicationTaskTagImpl + + PUBWEAK MPU_xTaskGetApplicationTaskTagImpl +MPU_xTaskGetApplicationTaskTagImpl: + b MPU_xTaskGetApplicationTaskTagImpl + + PUBWEAK MPU_vTaskSetThreadLocalStoragePointerImpl +MPU_vTaskSetThreadLocalStoragePointerImpl: + b MPU_vTaskSetThreadLocalStoragePointerImpl + + PUBWEAK MPU_pvTaskGetThreadLocalStoragePointerImpl +MPU_pvTaskGetThreadLocalStoragePointerImpl: + b MPU_pvTaskGetThreadLocalStoragePointerImpl + + PUBWEAK MPU_uxTaskGetSystemStateImpl +MPU_uxTaskGetSystemStateImpl: + b MPU_uxTaskGetSystemStateImpl + + PUBWEAK MPU_uxTaskGetStackHighWaterMarkImpl +MPU_uxTaskGetStackHighWaterMarkImpl: + b MPU_uxTaskGetStackHighWaterMarkImpl + + PUBWEAK MPU_uxTaskGetStackHighWaterMark2Impl +MPU_uxTaskGetStackHighWaterMark2Impl: + b MPU_uxTaskGetStackHighWaterMark2Impl + + PUBWEAK MPU_xTaskGetCurrentTaskHandleImpl +MPU_xTaskGetCurrentTaskHandleImpl: + b MPU_xTaskGetCurrentTaskHandleImpl + + PUBWEAK MPU_xTaskGetSchedulerStateImpl +MPU_xTaskGetSchedulerStateImpl: + b MPU_xTaskGetSchedulerStateImpl + + PUBWEAK MPU_vTaskSetTimeOutStateImpl +MPU_vTaskSetTimeOutStateImpl: + b MPU_vTaskSetTimeOutStateImpl + + PUBWEAK MPU_xTaskCheckForTimeOutImpl +MPU_xTaskCheckForTimeOutImpl: + b MPU_xTaskCheckForTimeOutImpl + + PUBWEAK MPU_xTaskGenericNotifyImpl +MPU_xTaskGenericNotifyImpl: + b MPU_xTaskGenericNotifyImpl + + PUBWEAK MPU_xTaskGenericNotifyWaitImpl +MPU_xTaskGenericNotifyWaitImpl: + b MPU_xTaskGenericNotifyWaitImpl + + PUBWEAK MPU_ulTaskGenericNotifyTakeImpl +MPU_ulTaskGenericNotifyTakeImpl: + b MPU_ulTaskGenericNotifyTakeImpl + + PUBWEAK MPU_xTaskGenericNotifyStateClearImpl +MPU_xTaskGenericNotifyStateClearImpl: + b MPU_xTaskGenericNotifyStateClearImpl + + PUBWEAK MPU_ulTaskGenericNotifyValueClearImpl +MPU_ulTaskGenericNotifyValueClearImpl: + b MPU_ulTaskGenericNotifyValueClearImpl + + PUBWEAK MPU_xQueueGenericSendImpl +MPU_xQueueGenericSendImpl: + b MPU_xQueueGenericSendImpl + + PUBWEAK MPU_uxQueueMessagesWaitingImpl +MPU_uxQueueMessagesWaitingImpl: + b MPU_uxQueueMessagesWaitingImpl + + PUBWEAK MPU_uxQueueSpacesAvailableImpl +MPU_uxQueueSpacesAvailableImpl: + b MPU_uxQueueSpacesAvailableImpl + + PUBWEAK MPU_xQueueReceiveImpl +MPU_xQueueReceiveImpl: + b MPU_xQueueReceiveImpl + + PUBWEAK MPU_xQueuePeekImpl +MPU_xQueuePeekImpl: + b MPU_xQueuePeekImpl + + PUBWEAK MPU_xQueueSemaphoreTakeImpl +MPU_xQueueSemaphoreTakeImpl: + b MPU_xQueueSemaphoreTakeImpl + + PUBWEAK MPU_xQueueGetMutexHolderImpl +MPU_xQueueGetMutexHolderImpl: + b MPU_xQueueGetMutexHolderImpl + + PUBWEAK MPU_xQueueTakeMutexRecursiveImpl +MPU_xQueueTakeMutexRecursiveImpl: + b MPU_xQueueTakeMutexRecursiveImpl + + PUBWEAK MPU_xQueueGiveMutexRecursiveImpl +MPU_xQueueGiveMutexRecursiveImpl: + b MPU_xQueueGiveMutexRecursiveImpl + + PUBWEAK MPU_xQueueSelectFromSetImpl +MPU_xQueueSelectFromSetImpl: + b MPU_xQueueSelectFromSetImpl + + PUBWEAK MPU_xQueueAddToSetImpl +MPU_xQueueAddToSetImpl: + b MPU_xQueueAddToSetImpl + + PUBWEAK MPU_vQueueAddToRegistryImpl +MPU_vQueueAddToRegistryImpl: + b MPU_vQueueAddToRegistryImpl + + PUBWEAK MPU_vQueueUnregisterQueueImpl +MPU_vQueueUnregisterQueueImpl: + b MPU_vQueueUnregisterQueueImpl + + PUBWEAK MPU_pcQueueGetNameImpl +MPU_pcQueueGetNameImpl: + b MPU_pcQueueGetNameImpl + + PUBWEAK MPU_pvTimerGetTimerIDImpl +MPU_pvTimerGetTimerIDImpl: + b MPU_pvTimerGetTimerIDImpl + + PUBWEAK MPU_vTimerSetTimerIDImpl +MPU_vTimerSetTimerIDImpl: + b MPU_vTimerSetTimerIDImpl + + PUBWEAK MPU_xTimerIsTimerActiveImpl +MPU_xTimerIsTimerActiveImpl: + b MPU_xTimerIsTimerActiveImpl + + PUBWEAK MPU_xTimerGetTimerDaemonTaskHandleImpl +MPU_xTimerGetTimerDaemonTaskHandleImpl: + b MPU_xTimerGetTimerDaemonTaskHandleImpl + + PUBWEAK MPU_xTimerGenericCommandFromTaskImpl +MPU_xTimerGenericCommandFromTaskImpl: + b MPU_xTimerGenericCommandFromTaskImpl + + PUBWEAK MPU_pcTimerGetNameImpl +MPU_pcTimerGetNameImpl: + b MPU_pcTimerGetNameImpl + + PUBWEAK MPU_vTimerSetReloadModeImpl +MPU_vTimerSetReloadModeImpl: + b MPU_vTimerSetReloadModeImpl + + PUBWEAK MPU_xTimerGetReloadModeImpl +MPU_xTimerGetReloadModeImpl: + b MPU_xTimerGetReloadModeImpl + + PUBWEAK MPU_uxTimerGetReloadModeImpl +MPU_uxTimerGetReloadModeImpl: + b MPU_uxTimerGetReloadModeImpl + + PUBWEAK MPU_xTimerGetPeriodImpl +MPU_xTimerGetPeriodImpl: + b MPU_xTimerGetPeriodImpl + + PUBWEAK MPU_xTimerGetExpiryTimeImpl +MPU_xTimerGetExpiryTimeImpl: + b MPU_xTimerGetExpiryTimeImpl + + PUBWEAK MPU_xEventGroupWaitBitsImpl +MPU_xEventGroupWaitBitsImpl: + b MPU_xEventGroupWaitBitsImpl + + PUBWEAK MPU_xEventGroupClearBitsImpl +MPU_xEventGroupClearBitsImpl: + b MPU_xEventGroupClearBitsImpl + + PUBWEAK MPU_xEventGroupSetBitsImpl +MPU_xEventGroupSetBitsImpl: + b MPU_xEventGroupSetBitsImpl + + PUBWEAK MPU_xEventGroupSyncImpl +MPU_xEventGroupSyncImpl: + b MPU_xEventGroupSyncImpl + + PUBWEAK MPU_uxEventGroupGetNumberImpl +MPU_uxEventGroupGetNumberImpl: + b MPU_uxEventGroupGetNumberImpl + + PUBWEAK MPU_vEventGroupSetNumberImpl +MPU_vEventGroupSetNumberImpl: + b MPU_vEventGroupSetNumberImpl + + PUBWEAK MPU_xStreamBufferSendImpl +MPU_xStreamBufferSendImpl: + b MPU_xStreamBufferSendImpl + + PUBWEAK MPU_xStreamBufferReceiveImpl +MPU_xStreamBufferReceiveImpl: + b MPU_xStreamBufferReceiveImpl + + PUBWEAK MPU_xStreamBufferIsFullImpl +MPU_xStreamBufferIsFullImpl: + b MPU_xStreamBufferIsFullImpl + + PUBWEAK MPU_xStreamBufferIsEmptyImpl +MPU_xStreamBufferIsEmptyImpl: + b MPU_xStreamBufferIsEmptyImpl + + PUBWEAK MPU_xStreamBufferSpacesAvailableImpl +MPU_xStreamBufferSpacesAvailableImpl: + b MPU_xStreamBufferSpacesAvailableImpl + + PUBWEAK MPU_xStreamBufferBytesAvailableImpl +MPU_xStreamBufferBytesAvailableImpl: + b MPU_xStreamBufferBytesAvailableImpl + + PUBWEAK MPU_xStreamBufferSetTriggerLevelImpl +MPU_xStreamBufferSetTriggerLevelImpl: + b MPU_xStreamBufferSetTriggerLevelImpl + + PUBWEAK MPU_xStreamBufferNextMessageLengthBytesImpl +MPU_xStreamBufferNextMessageLengthBytesImpl: + b MPU_xStreamBufferNextMessageLengthBytesImpl + +/*-----------------------------------------------------------*/ + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + END diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portasm.s b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portasm.s new file mode 100644 index 000000000..6817abd7a --- /dev/null +++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portasm.s @@ -0,0 +1,525 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" + +/* System call numbers includes. */ +#include "mpu_syscall_numbers.h" + +#ifndef configUSE_MPU_WRAPPERS_V1 + #define configUSE_MPU_WRAPPERS_V1 0 +#endif + + + EXTERN pxCurrentTCB + EXTERN xSecureContext + EXTERN vTaskSwitchContext + EXTERN vPortSVCHandler_C + EXTERN SecureContext_SaveContext + EXTERN SecureContext_LoadContext +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + EXTERN vSystemCallEnter + EXTERN vSystemCallExit +#endif + + PUBLIC xIsPrivileged + PUBLIC vResetPrivilege + PUBLIC vPortAllocateSecureContext + PUBLIC vRestoreContextOfFirstTask + PUBLIC vRaisePrivilege + PUBLIC vStartFirstTask + PUBLIC ulSetInterruptMask + PUBLIC vClearInterruptMask + PUBLIC PendSV_Handler + PUBLIC SVC_Handler + PUBLIC vPortFreeSecureContext + +#if ( configENABLE_FPU == 1 ) + #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0. +#endif +/*-----------------------------------------------------------*/ + +/*---------------- Unprivileged Functions -------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION .text:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +xIsPrivileged: + mrs r0, control /* r0 = CONTROL. */ + movs r1, #1 /* r1 = 1. */ + tst r0, r1 /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */ + beq running_privileged /* If the result of previous AND operation was 0, branch. */ + movs r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + bx lr /* Return. */ + running_privileged: + movs r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vResetPrivilege: + mrs r0, control /* r0 = CONTROL. */ + movs r1, #1 /* r1 = 1. */ + orrs r0, r1 /* r0 = r0 | r1. */ + msr control, r0 /* CONTROL = r0. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vPortAllocateSecureContext: + svc 100 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 100. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +/*----------------- Privileged Functions --------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION privileged_functions:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +vRestoreContextOfFirstTask: + program_mpu_first_task: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r3] /* r0 = pxCurrentTCB.*/ + + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + movs r3, #1 /* r3 = 1. */ + bics r2, r3 /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */ + str r2, [r1] /* Disable MPU. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r1, [r2] /* Program MAIR0. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */ + + movs r3, #4 /* r3 = 4. */ + str r3, [r1] /* Program RNR = 4. */ + ldmia r0!, {r4-r5} /* Read first set of RBAR/RLAR registers from TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + stmia r2!, {r4-r5} /* Write first set of RBAR/RLAR registers. */ + movs r3, #5 /* r3 = 5. */ + str r3, [r1] /* Program RNR = 5. */ + ldmia r0!, {r4-r5} /* Read second set of RBAR/RLAR registers from TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + stmia r2!, {r4-r5} /* Write second set of RBAR/RLAR registers. */ + movs r3, #6 /* r3 = 6. */ + str r3, [r1] /* Program RNR = 6. */ + ldmia r0!, {r4-r5} /* Read third set of RBAR/RLAR registers from TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + stmia r2!, {r4-r5} /* Write third set of RBAR/RLAR registers. */ + movs r3, #7 /* r3 = 6. */ + str r3, [r1] /* Program RNR = 7. */ + ldmia r0!, {r4-r5} /* Read fourth set of RBAR/RLAR registers from TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + stmia r2!, {r4-r5} /* Write fourth set of RBAR/RLAR registers. */ + + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + movs r3, #1 /* r3 = 1. */ + orrs r2, r3 /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */ + str r2, [r1] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + + restore_context_first_task: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* r1 = pxCurrentTCB.*/ + ldr r2, [r1] /* r2 = Location of saved context in TCB. */ + + restore_special_regs_first_task: + subs r2, #20 + ldmia r2!, {r0, r3-r6} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */ + subs r2, #20 + msr psp, r3 + msr control, r5 + mov lr, r6 + ldr r4, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + str r0, [r4] /* Restore xSecureContext. */ + + restore_general_regs_first_task: + subs r2, #32 + ldmia r2!, {r4-r7} /* r4-r7 contain half of the hardware saved context. */ + stmia r3!, {r4-r7} /* Copy half of the the hardware saved context on the task stack. */ + ldmia r2!, {r4-r7} /* r4-r7 contain rest half of the hardware saved context. */ + stmia r3!, {r4-r7} /* Copy rest half of the the hardware saved context on the task stack. */ + subs r2, #48 + ldmia r2!, {r4-r7} /* Restore r8-r11. */ + mov r8, r4 /* r8 = r4. */ + mov r9, r5 /* r9 = r5. */ + mov r10, r6 /* r10 = r6. */ + mov r11, r7 /* r11 = r7. */ + subs r2, #32 + ldmia r2!, {r4-r7} /* Restore r4-r7. */ + subs r2, #16 + + restore_context_done_first_task: + str r2, [r1] /* Save the location where the context should be saved next as the first member of TCB. */ + bx lr + +#else /* configENABLE_MPU */ + +vRestoreContextOfFirstTask: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r3, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + + ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */ + ldr r4, =xSecureContext + str r1, [r4] /* Set xSecureContext to this task's value for the same. */ + movs r1, #2 /* r1 = 2. */ + msr CONTROL, r1 /* Switch to use PSP in the thread mode. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + bx r3 /* Finally, branch to EXC_RETURN. */ + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +vRaisePrivilege: + mrs r0, control /* Read the CONTROL register. */ + movs r1, #1 /* r1 = 1. */ + bics r0, r1 /* Clear the bit 0. */ + msr control, r0 /* Write back the new CONTROL value. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vStartFirstTask: + ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */ + ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */ + ldr r0, [r0] /* The first entry in vector table is stack pointer. */ + msr msp, r0 /* Set the MSP back to the start of the stack. */ + cpsie i /* Globally enable interrupts. */ + dsb + isb + svc 102 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */ +/*-----------------------------------------------------------*/ + +ulSetInterruptMask: + mrs r0, PRIMASK + cpsid i + bx lr +/*-----------------------------------------------------------*/ + +vClearInterruptMask: + msr PRIMASK, r0 + bx lr +/*-----------------------------------------------------------*/ +#if ( configENABLE_MPU == 1 ) + +PendSV_Handler: + ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + ldr r0, [r3] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later.*/ + ldr r2, [r1] /* r2 = Location in TCB where the context should be saved. */ + + cbz r0, save_ns_context /* No secure context to save. */ + save_s_context: + push {r0-r2, lr} + bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r0-r3} /* LR is now in r3. */ + mov lr, r3 /* Restore LR. */ + + save_ns_context: + mov r3, lr /* r3 = LR (EXC_RETURN). */ + lsls r3, r3, #25 /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bmi save_special_regs /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + + save_general_regs: + mrs r3, psp + stmia r2!, {r4-r7} /* Store r4-r7. */ + mov r4, r8 /* r4 = r8. */ + mov r5, r9 /* r5 = r9. */ + mov r6, r10 /* r6 = r10. */ + mov r7, r11 /* r7 = r11. */ + stmia r2!, {r4-r7} /* Store r8-r11. */ + ldmia r3!, {r4-r7} /* Copy half of the hardware saved context into r4-r7. */ + stmia r2!, {r4-r7} /* Store the hardware saved context. */ + ldmia r3!, {r4-r7} /* Copy rest half of the hardware saved context into r4-r7. */ + stmia r2!, {r4-r7} /* Store the hardware saved context. */ + + save_special_regs: + mrs r3, psp /* r3 = PSP. */ + movs r4, #0 /* r4 = 0. 0 is stored in the PSPLIM slot. */ + mrs r5, control /* r5 = CONTROL. */ + mov r6, lr /* r6 = LR. */ + stmia r2!, {r0, r3-r6} /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ + str r2, [r1] /* Save the location from where the context should be restored as the first member of TCB. */ + + select_next_task: + cpsid i + bl vTaskSwitchContext + cpsie i + + program_mpu: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r3] /* r0 = pxCurrentTCB.*/ + + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + movs r3, #1 /* r3 = 1. */ + bics r2, r3 /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */ + str r2, [r1] /* Disable MPU. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r1, [r2] /* Program MAIR0. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */ + + movs r3, #4 /* r3 = 4. */ + str r3, [r1] /* Program RNR = 4. */ + ldmia r0!, {r4-r5} /* Read first set of RBAR/RLAR registers from TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + stmia r2!, {r4-r5} /* Write first set of RBAR/RLAR registers. */ + movs r3, #5 /* r3 = 5. */ + str r3, [r1] /* Program RNR = 5. */ + ldmia r0!, {r4-r5} /* Read second set of RBAR/RLAR registers from TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + stmia r2!, {r4-r5} /* Write second set of RBAR/RLAR registers. */ + movs r3, #6 /* r3 = 6. */ + str r3, [r1] /* Program RNR = 6. */ + ldmia r0!, {r4-r5} /* Read third set of RBAR/RLAR registers from TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + stmia r2!, {r4-r5} /* Write third set of RBAR/RLAR registers. */ + movs r3, #7 /* r3 = 6. */ + str r3, [r1] /* Program RNR = 7. */ + ldmia r0!, {r4-r5} /* Read fourth set of RBAR/RLAR registers from TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + stmia r2!, {r4-r5} /* Write fourth set of RBAR/RLAR registers. */ + + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + movs r3, #1 /* r3 = 1. */ + orrs r2, r3 /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */ + str r2, [r1] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + + restore_context: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* r1 = pxCurrentTCB.*/ + ldr r2, [r1] /* r2 = Location of saved context in TCB. */ + + restore_special_regs: + subs r2, #20 + ldmia r2!, {r0, r3-r6} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */ + subs r2, #20 + msr psp, r3 + msr control, r5 + mov lr, r6 + ldr r4, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + str r0, [r4] /* Restore xSecureContext. */ + cbz r0, restore_ns_context /* No secure context to restore. */ + + restore_s_context: + push {r1-r3, lr} + bl SecureContext_LoadContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r1-r4} /* LR is now in r4. */ + mov lr, r4 + + restore_ns_context: + mov r0, lr /* r0 = LR (EXC_RETURN). */ + lsls r0, r0, #25 /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bmi restore_context_done /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + + restore_general_regs: + subs r2, #32 + ldmia r2!, {r4-r7} /* r4-r7 contain half of the hardware saved context. */ + stmia r3!, {r4-r7} /* Copy half of the the hardware saved context on the task stack. */ + ldmia r2!, {r4-r7} /* r4-r7 contain rest half of the hardware saved context. */ + stmia r3!, {r4-r7} /* Copy rest half of the the hardware saved context on the task stack. */ + subs r2, #48 + ldmia r2!, {r4-r7} /* Restore r8-r11. */ + mov r8, r4 /* r8 = r4. */ + mov r9, r5 /* r9 = r5. */ + mov r10, r6 /* r10 = r6. */ + mov r11, r7 /* r11 = r7. */ + subs r2, #32 + ldmia r2!, {r4-r7} /* Restore r4-r7. */ + subs r2, #16 + + restore_context_done: + str r2, [r1] /* Save the location where the context should be saved next as the first member of TCB. */ + bx lr + +#else /* configENABLE_MPU */ + +PendSV_Handler: + ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + ldr r0, [r3] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */ + mrs r2, psp /* Read PSP in r2. */ + + cbz r0, save_ns_context /* No secure context to save. */ + push {r0-r2, r14} + bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r0-r3} /* LR is now in r3. */ + mov lr, r3 /* LR = r3. */ + lsls r1, r3, #25 /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bpl save_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB. */ + + subs r2, r2, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */ + str r2, [r1] /* Save the new top of stack in TCB. */ + movs r1, #0 /* r1 = 0. 0 is stored in the PSPLIM slot. */ + mov r3, lr /* r3 = LR/EXC_RETURN. */ + stmia r2!, {r0, r1, r3} /* Store xSecureContext, PSPLIM and LR on the stack. */ + + b select_next_task + + save_ns_context: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB. */ + subs r2, r2, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */ + str r2, [r1] /* Save the new top of stack in TCB. */ + movs r1, #0 /* r1 = 0. 0 is stored in the PSPLIM slot. */ + mov r3, lr /* r3 = LR/EXC_RETURN. */ + stmia r2!, {r0, r1, r3-r7} /* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */ + mov r4, r8 /* r4 = r8. */ + mov r5, r9 /* r5 = r9. */ + mov r6, r10 /* r6 = r10. */ + mov r7, r11 /* r7 = r11. */ + stmia r2!, {r4-r7} /* Store the high registers that are not saved automatically. */ + + select_next_task: + cpsid i + bl vTaskSwitchContext + cpsie i + + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB. */ + ldr r2, [r1] /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */ + + ldmia r2!, {r0, r1, r4} /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */ + mov lr, r4 /* LR = r4. */ + ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + str r0, [r3] /* Restore the task's xSecureContext. */ + cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */ + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB. */ + push {r2, r4} + bl SecureContext_LoadContext /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r2, r4} + mov lr, r4 /* LR = r4. */ + lsls r1, r4, #25 /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bpl restore_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + msr psp, r2 /* Remember the new top of stack for the task. */ + bx lr + + restore_ns_context: + adds r2, r2, #16 /* Move to the high registers. */ + ldmia r2!, {r4-r7} /* Restore the high registers that are not automatically restored. */ + mov r8, r4 /* r8 = r4. */ + mov r9, r5 /* r9 = r5. */ + mov r10, r6 /* r10 = r6. */ + mov r11, r7 /* r11 = r7. */ + msr psp, r2 /* Remember the new top of stack for the task. */ + subs r2, r2, #32 /* Go back to the low registers. */ + ldmia r2!, {r4-r7} /* Restore the low registers that are not automatically restored. */ + bx lr + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + +SVC_Handler: + movs r0, #4 + mov r1, lr + tst r0, r1 + beq stack_on_msp + stack_on_psp: + mrs r0, psp + b route_svc + stack_on_msp: + mrs r0, msp + b route_svc + + route_svc: + ldr r3, [r0, #24] + subs r3, #2 + ldrb r2, [r3, #0] + cmp r2, #NUM_SYSTEM_CALLS + blt system_call_enter + cmp r2, #104 /* portSVC_SYSTEM_CALL_EXIT. */ + beq system_call_exit + b vPortSVCHandler_C + + system_call_enter: + b vSystemCallEnter + system_call_exit: + b vSystemCallExit + +#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +SVC_Handler: + movs r0, #4 + mov r1, lr + tst r0, r1 + beq stacking_used_msp + mrs r0, psp + b vPortSVCHandler_C + stacking_used_msp: + mrs r0, msp + b vPortSVCHandler_C + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +vPortFreeSecureContext: + ldr r2, [r0] /* The first item in the TCB is the top of the stack. */ + ldr r1, [r2] /* The first item on the stack is the task's xSecureContext. */ + cmp r1, #0 /* Raise svc if task's xSecureContext is not NULL. */ + bne free_secure_context /* Branch if r1 != 0. */ + bx lr /* There is no secure context (xSecureContext is NULL). */ + free_secure_context: + svc 101 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 101. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + + END diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h new file mode 100644 index 000000000..9d6c3368e --- /dev/null +++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h @@ -0,0 +1,92 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M23" +#define portHAS_ARMV8M_MAIN_EXTENSION 0 +#define portARMV8M_MINOR_VERSION 0 +#define portDONT_DISCARD __root +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +#if ( configTOTAL_MPU_REGIONS == 16 ) + #error 16 MPU regions are not yet supported for this port. +#endif + +#ifndef configENABLE_MVE + #define configENABLE_MVE 0 +#elif ( configENABLE_MVE != 0 ) + #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M23. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" ) +#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ +#pragma diag_suppress=Be006 +#pragma diag_suppress=Pa082 +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/mpu_wrappers_v2_asm.S b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/mpu_wrappers_v2_asm.S new file mode 100644 index 000000000..9289bcbc2 --- /dev/null +++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/mpu_wrappers_v2_asm.S @@ -0,0 +1,1312 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + + SECTION freertos_system_calls:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +#include "FreeRTOSConfig.h" +#include "mpu_syscall_numbers.h" + +#ifndef configUSE_MPU_WRAPPERS_V1 + #define configUSE_MPU_WRAPPERS_V1 0 +#endif + +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + PUBLIC MPU_xTaskDelayUntil +MPU_xTaskDelayUntil: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTaskDelayUntil_Unpriv + MPU_xTaskDelayUntil_Priv: + b MPU_xTaskDelayUntilImpl + MPU_xTaskDelayUntil_Unpriv: + svc #SYSTEM_CALL_xTaskDelayUntil +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskAbortDelay +MPU_xTaskAbortDelay: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTaskAbortDelay_Unpriv + MPU_xTaskAbortDelay_Priv: + b MPU_xTaskAbortDelayImpl + MPU_xTaskAbortDelay_Unpriv: + svc #SYSTEM_CALL_xTaskAbortDelay +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskDelay +MPU_vTaskDelay: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vTaskDelay_Unpriv + MPU_vTaskDelay_Priv: + b MPU_vTaskDelayImpl + MPU_vTaskDelay_Unpriv: + svc #SYSTEM_CALL_vTaskDelay +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskPriorityGet +MPU_uxTaskPriorityGet: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_uxTaskPriorityGet_Unpriv + MPU_uxTaskPriorityGet_Priv: + b MPU_uxTaskPriorityGetImpl + MPU_uxTaskPriorityGet_Unpriv: + svc #SYSTEM_CALL_uxTaskPriorityGet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_eTaskGetState +MPU_eTaskGetState: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_eTaskGetState_Unpriv + MPU_eTaskGetState_Priv: + b MPU_eTaskGetStateImpl + MPU_eTaskGetState_Unpriv: + svc #SYSTEM_CALL_eTaskGetState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskGetInfo +MPU_vTaskGetInfo: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vTaskGetInfo_Unpriv + MPU_vTaskGetInfo_Priv: + b MPU_vTaskGetInfoImpl + MPU_vTaskGetInfo_Unpriv: + svc #SYSTEM_CALL_vTaskGetInfo +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetIdleTaskHandle +MPU_xTaskGetIdleTaskHandle: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTaskGetIdleTaskHandle_Unpriv + MPU_xTaskGetIdleTaskHandle_Priv: + b MPU_xTaskGetIdleTaskHandleImpl + MPU_xTaskGetIdleTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTaskGetIdleTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSuspend +MPU_vTaskSuspend: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vTaskSuspend_Unpriv + MPU_vTaskSuspend_Priv: + b MPU_vTaskSuspendImpl + MPU_vTaskSuspend_Unpriv: + svc #SYSTEM_CALL_vTaskSuspend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskResume +MPU_vTaskResume: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vTaskResume_Unpriv + MPU_vTaskResume_Priv: + b MPU_vTaskResumeImpl + MPU_vTaskResume_Unpriv: + svc #SYSTEM_CALL_vTaskResume +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetTickCount +MPU_xTaskGetTickCount: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTaskGetTickCount_Unpriv + MPU_xTaskGetTickCount_Priv: + b MPU_xTaskGetTickCountImpl + MPU_xTaskGetTickCount_Unpriv: + svc #SYSTEM_CALL_xTaskGetTickCount +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetNumberOfTasks +MPU_uxTaskGetNumberOfTasks: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_uxTaskGetNumberOfTasks_Unpriv + MPU_uxTaskGetNumberOfTasks_Priv: + b MPU_uxTaskGetNumberOfTasksImpl + MPU_uxTaskGetNumberOfTasks_Unpriv: + svc #SYSTEM_CALL_uxTaskGetNumberOfTasks +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetRunTimeCounter +MPU_ulTaskGetRunTimeCounter: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_ulTaskGetRunTimeCounter_Unpriv + MPU_ulTaskGetRunTimeCounter_Priv: + b MPU_ulTaskGetRunTimeCounterImpl + MPU_ulTaskGetRunTimeCounter_Unpriv: + svc #SYSTEM_CALL_ulTaskGetRunTimeCounter +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetRunTimePercent +MPU_ulTaskGetRunTimePercent: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_ulTaskGetRunTimePercent_Unpriv + MPU_ulTaskGetRunTimePercent_Priv: + b MPU_ulTaskGetRunTimePercentImpl + MPU_ulTaskGetRunTimePercent_Unpriv: + svc #SYSTEM_CALL_ulTaskGetRunTimePercent +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetIdleRunTimePercent +MPU_ulTaskGetIdleRunTimePercent: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_ulTaskGetIdleRunTimePercent_Unpriv + MPU_ulTaskGetIdleRunTimePercent_Priv: + b MPU_ulTaskGetIdleRunTimePercentImpl + MPU_ulTaskGetIdleRunTimePercent_Unpriv: + svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetIdleRunTimeCounter +MPU_ulTaskGetIdleRunTimeCounter: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv + MPU_ulTaskGetIdleRunTimeCounter_Priv: + b MPU_ulTaskGetIdleRunTimeCounterImpl + MPU_ulTaskGetIdleRunTimeCounter_Unpriv: + svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetApplicationTaskTag +MPU_vTaskSetApplicationTaskTag: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vTaskSetApplicationTaskTag_Unpriv + MPU_vTaskSetApplicationTaskTag_Priv: + b MPU_vTaskSetApplicationTaskTagImpl + MPU_vTaskSetApplicationTaskTag_Unpriv: + svc #SYSTEM_CALL_vTaskSetApplicationTaskTag +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetApplicationTaskTag +MPU_xTaskGetApplicationTaskTag: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTaskGetApplicationTaskTag_Unpriv + MPU_xTaskGetApplicationTaskTag_Priv: + b MPU_xTaskGetApplicationTaskTagImpl + MPU_xTaskGetApplicationTaskTag_Unpriv: + svc #SYSTEM_CALL_xTaskGetApplicationTaskTag +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetThreadLocalStoragePointer +MPU_vTaskSetThreadLocalStoragePointer: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv + MPU_vTaskSetThreadLocalStoragePointer_Priv: + b MPU_vTaskSetThreadLocalStoragePointerImpl + MPU_vTaskSetThreadLocalStoragePointer_Unpriv: + svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pvTaskGetThreadLocalStoragePointer +MPU_pvTaskGetThreadLocalStoragePointer: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv + MPU_pvTaskGetThreadLocalStoragePointer_Priv: + b MPU_pvTaskGetThreadLocalStoragePointerImpl + MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: + svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetSystemState +MPU_uxTaskGetSystemState: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_uxTaskGetSystemState_Unpriv + MPU_uxTaskGetSystemState_Priv: + b MPU_uxTaskGetSystemStateImpl + MPU_uxTaskGetSystemState_Unpriv: + svc #SYSTEM_CALL_uxTaskGetSystemState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetStackHighWaterMark +MPU_uxTaskGetStackHighWaterMark: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_uxTaskGetStackHighWaterMark_Unpriv + MPU_uxTaskGetStackHighWaterMark_Priv: + b MPU_uxTaskGetStackHighWaterMarkImpl + MPU_uxTaskGetStackHighWaterMark_Unpriv: + svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetStackHighWaterMark2 +MPU_uxTaskGetStackHighWaterMark2: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_uxTaskGetStackHighWaterMark2_Unpriv + MPU_uxTaskGetStackHighWaterMark2_Priv: + b MPU_uxTaskGetStackHighWaterMark2Impl + MPU_uxTaskGetStackHighWaterMark2_Unpriv: + svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2 +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetCurrentTaskHandle +MPU_xTaskGetCurrentTaskHandle: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTaskGetCurrentTaskHandle_Unpriv + MPU_xTaskGetCurrentTaskHandle_Priv: + b MPU_xTaskGetCurrentTaskHandleImpl + MPU_xTaskGetCurrentTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetSchedulerState +MPU_xTaskGetSchedulerState: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTaskGetSchedulerState_Unpriv + MPU_xTaskGetSchedulerState_Priv: + b MPU_xTaskGetSchedulerStateImpl + MPU_xTaskGetSchedulerState_Unpriv: + svc #SYSTEM_CALL_xTaskGetSchedulerState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetTimeOutState +MPU_vTaskSetTimeOutState: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vTaskSetTimeOutState_Unpriv + MPU_vTaskSetTimeOutState_Priv: + b MPU_vTaskSetTimeOutStateImpl + MPU_vTaskSetTimeOutState_Unpriv: + svc #SYSTEM_CALL_vTaskSetTimeOutState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskCheckForTimeOut +MPU_xTaskCheckForTimeOut: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTaskCheckForTimeOut_Unpriv + MPU_xTaskCheckForTimeOut_Priv: + b MPU_xTaskCheckForTimeOutImpl + MPU_xTaskCheckForTimeOut_Unpriv: + svc #SYSTEM_CALL_xTaskCheckForTimeOut +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyEntry +MPU_xTaskGenericNotifyEntry: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTaskGenericNotify_Unpriv + MPU_xTaskGenericNotify_Priv: + b MPU_xTaskGenericNotifyImpl + MPU_xTaskGenericNotify_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotify +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyWaitEntry +MPU_xTaskGenericNotifyWaitEntry: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTaskGenericNotifyWait_Unpriv + MPU_xTaskGenericNotifyWait_Priv: + b MPU_xTaskGenericNotifyWaitImpl + MPU_xTaskGenericNotifyWait_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotifyWait +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGenericNotifyTake +MPU_ulTaskGenericNotifyTake: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_ulTaskGenericNotifyTake_Unpriv + MPU_ulTaskGenericNotifyTake_Priv: + b MPU_ulTaskGenericNotifyTakeImpl + MPU_ulTaskGenericNotifyTake_Unpriv: + svc #SYSTEM_CALL_ulTaskGenericNotifyTake +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyStateClear +MPU_xTaskGenericNotifyStateClear: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTaskGenericNotifyStateClear_Unpriv + MPU_xTaskGenericNotifyStateClear_Priv: + b MPU_xTaskGenericNotifyStateClearImpl + MPU_xTaskGenericNotifyStateClear_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotifyStateClear +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGenericNotifyValueClear +MPU_ulTaskGenericNotifyValueClear: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_ulTaskGenericNotifyValueClear_Unpriv + MPU_ulTaskGenericNotifyValueClear_Priv: + b MPU_ulTaskGenericNotifyValueClearImpl + MPU_ulTaskGenericNotifyValueClear_Unpriv: + svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGenericSend +MPU_xQueueGenericSend: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xQueueGenericSend_Unpriv + MPU_xQueueGenericSend_Priv: + b MPU_xQueueGenericSendImpl + MPU_xQueueGenericSend_Unpriv: + svc #SYSTEM_CALL_xQueueGenericSend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxQueueMessagesWaiting +MPU_uxQueueMessagesWaiting: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_uxQueueMessagesWaiting_Unpriv + MPU_uxQueueMessagesWaiting_Priv: + b MPU_uxQueueMessagesWaitingImpl + MPU_uxQueueMessagesWaiting_Unpriv: + svc #SYSTEM_CALL_uxQueueMessagesWaiting +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxQueueSpacesAvailable +MPU_uxQueueSpacesAvailable: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_uxQueueSpacesAvailable_Unpriv + MPU_uxQueueSpacesAvailable_Priv: + b MPU_uxQueueSpacesAvailableImpl + MPU_uxQueueSpacesAvailable_Unpriv: + svc #SYSTEM_CALL_uxQueueSpacesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueReceive +MPU_xQueueReceive: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xQueueReceive_Unpriv + MPU_xQueueReceive_Priv: + b MPU_xQueueReceiveImpl + MPU_xQueueReceive_Unpriv: + svc #SYSTEM_CALL_xQueueReceive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueuePeek +MPU_xQueuePeek: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xQueuePeek_Unpriv + MPU_xQueuePeek_Priv: + b MPU_xQueuePeekImpl + MPU_xQueuePeek_Unpriv: + svc #SYSTEM_CALL_xQueuePeek +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueSemaphoreTake +MPU_xQueueSemaphoreTake: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xQueueSemaphoreTake_Unpriv + MPU_xQueueSemaphoreTake_Priv: + b MPU_xQueueSemaphoreTakeImpl + MPU_xQueueSemaphoreTake_Unpriv: + svc #SYSTEM_CALL_xQueueSemaphoreTake +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGetMutexHolder +MPU_xQueueGetMutexHolder: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xQueueGetMutexHolder_Unpriv + MPU_xQueueGetMutexHolder_Priv: + b MPU_xQueueGetMutexHolderImpl + MPU_xQueueGetMutexHolder_Unpriv: + svc #SYSTEM_CALL_xQueueGetMutexHolder +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueTakeMutexRecursive +MPU_xQueueTakeMutexRecursive: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xQueueTakeMutexRecursive_Unpriv + MPU_xQueueTakeMutexRecursive_Priv: + b MPU_xQueueTakeMutexRecursiveImpl + MPU_xQueueTakeMutexRecursive_Unpriv: + svc #SYSTEM_CALL_xQueueTakeMutexRecursive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGiveMutexRecursive +MPU_xQueueGiveMutexRecursive: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xQueueGiveMutexRecursive_Unpriv + MPU_xQueueGiveMutexRecursive_Priv: + b MPU_xQueueGiveMutexRecursiveImpl + MPU_xQueueGiveMutexRecursive_Unpriv: + svc #SYSTEM_CALL_xQueueGiveMutexRecursive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueSelectFromSet +MPU_xQueueSelectFromSet: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xQueueSelectFromSet_Unpriv + MPU_xQueueSelectFromSet_Priv: + b MPU_xQueueSelectFromSetImpl + MPU_xQueueSelectFromSet_Unpriv: + svc #SYSTEM_CALL_xQueueSelectFromSet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueAddToSet +MPU_xQueueAddToSet: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xQueueAddToSet_Unpriv + MPU_xQueueAddToSet_Priv: + b MPU_xQueueAddToSetImpl + MPU_xQueueAddToSet_Unpriv: + svc #SYSTEM_CALL_xQueueAddToSet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vQueueAddToRegistry +MPU_vQueueAddToRegistry: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vQueueAddToRegistry_Unpriv + MPU_vQueueAddToRegistry_Priv: + b MPU_vQueueAddToRegistryImpl + MPU_vQueueAddToRegistry_Unpriv: + svc #SYSTEM_CALL_vQueueAddToRegistry +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vQueueUnregisterQueue +MPU_vQueueUnregisterQueue: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vQueueUnregisterQueue_Unpriv + MPU_vQueueUnregisterQueue_Priv: + b MPU_vQueueUnregisterQueueImpl + MPU_vQueueUnregisterQueue_Unpriv: + svc #SYSTEM_CALL_vQueueUnregisterQueue +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pcQueueGetName +MPU_pcQueueGetName: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_pcQueueGetName_Unpriv + MPU_pcQueueGetName_Priv: + b MPU_pcQueueGetNameImpl + MPU_pcQueueGetName_Unpriv: + svc #SYSTEM_CALL_pcQueueGetName +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pvTimerGetTimerID +MPU_pvTimerGetTimerID: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_pvTimerGetTimerID_Unpriv + MPU_pvTimerGetTimerID_Priv: + b MPU_pvTimerGetTimerIDImpl + MPU_pvTimerGetTimerID_Unpriv: + svc #SYSTEM_CALL_pvTimerGetTimerID +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTimerSetTimerID +MPU_vTimerSetTimerID: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vTimerSetTimerID_Unpriv + MPU_vTimerSetTimerID_Priv: + b MPU_vTimerSetTimerIDImpl + MPU_vTimerSetTimerID_Unpriv: + svc #SYSTEM_CALL_vTimerSetTimerID +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerIsTimerActive +MPU_xTimerIsTimerActive: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTimerIsTimerActive_Unpriv + MPU_xTimerIsTimerActive_Priv: + b MPU_xTimerIsTimerActiveImpl + MPU_xTimerIsTimerActive_Unpriv: + svc #SYSTEM_CALL_xTimerIsTimerActive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetTimerDaemonTaskHandle +MPU_xTimerGetTimerDaemonTaskHandle: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv + MPU_xTimerGetTimerDaemonTaskHandle_Priv: + b MPU_xTimerGetTimerDaemonTaskHandleImpl + MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGenericCommandFromTaskEntry +MPU_xTimerGenericCommandFromTaskEntry: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTimerGenericCommandFromTask_Unpriv + MPU_xTimerGenericCommandFromTask_Priv: + b MPU_xTimerGenericCommandFromTaskImpl + MPU_xTimerGenericCommandFromTask_Unpriv: + svc #SYSTEM_CALL_xTimerGenericCommandFromTask +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pcTimerGetName +MPU_pcTimerGetName: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_pcTimerGetName_Unpriv + MPU_pcTimerGetName_Priv: + b MPU_pcTimerGetNameImpl + MPU_pcTimerGetName_Unpriv: + svc #SYSTEM_CALL_pcTimerGetName +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTimerSetReloadMode +MPU_vTimerSetReloadMode: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vTimerSetReloadMode_Unpriv + MPU_vTimerSetReloadMode_Priv: + b MPU_vTimerSetReloadModeImpl + MPU_vTimerSetReloadMode_Unpriv: + svc #SYSTEM_CALL_vTimerSetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetReloadMode +MPU_xTimerGetReloadMode: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTimerGetReloadMode_Unpriv + MPU_xTimerGetReloadMode_Priv: + b MPU_xTimerGetReloadModeImpl + MPU_xTimerGetReloadMode_Unpriv: + svc #SYSTEM_CALL_xTimerGetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTimerGetReloadMode +MPU_uxTimerGetReloadMode: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_uxTimerGetReloadMode_Unpriv + MPU_uxTimerGetReloadMode_Priv: + b MPU_uxTimerGetReloadModeImpl + MPU_uxTimerGetReloadMode_Unpriv: + svc #SYSTEM_CALL_uxTimerGetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetPeriod +MPU_xTimerGetPeriod: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTimerGetPeriod_Unpriv + MPU_xTimerGetPeriod_Priv: + b MPU_xTimerGetPeriodImpl + MPU_xTimerGetPeriod_Unpriv: + svc #SYSTEM_CALL_xTimerGetPeriod +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetExpiryTime +MPU_xTimerGetExpiryTime: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTimerGetExpiryTime_Unpriv + MPU_xTimerGetExpiryTime_Priv: + b MPU_xTimerGetExpiryTimeImpl + MPU_xTimerGetExpiryTime_Unpriv: + svc #SYSTEM_CALL_xTimerGetExpiryTime +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupWaitBitsEntry +MPU_xEventGroupWaitBitsEntry: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xEventGroupWaitBits_Unpriv + MPU_xEventGroupWaitBits_Priv: + b MPU_xEventGroupWaitBitsImpl + MPU_xEventGroupWaitBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupWaitBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupClearBits +MPU_xEventGroupClearBits: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xEventGroupClearBits_Unpriv + MPU_xEventGroupClearBits_Priv: + b MPU_xEventGroupClearBitsImpl + MPU_xEventGroupClearBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupClearBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupSetBits +MPU_xEventGroupSetBits: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xEventGroupSetBits_Unpriv + MPU_xEventGroupSetBits_Priv: + b MPU_xEventGroupSetBitsImpl + MPU_xEventGroupSetBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupSetBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupSync +MPU_xEventGroupSync: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xEventGroupSync_Unpriv + MPU_xEventGroupSync_Priv: + b MPU_xEventGroupSyncImpl + MPU_xEventGroupSync_Unpriv: + svc #SYSTEM_CALL_xEventGroupSync +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxEventGroupGetNumber +MPU_uxEventGroupGetNumber: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_uxEventGroupGetNumber_Unpriv + MPU_uxEventGroupGetNumber_Priv: + b MPU_uxEventGroupGetNumberImpl + MPU_uxEventGroupGetNumber_Unpriv: + svc #SYSTEM_CALL_uxEventGroupGetNumber +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vEventGroupSetNumber +MPU_vEventGroupSetNumber: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vEventGroupSetNumber_Unpriv + MPU_vEventGroupSetNumber_Priv: + b MPU_vEventGroupSetNumberImpl + MPU_vEventGroupSetNumber_Unpriv: + svc #SYSTEM_CALL_vEventGroupSetNumber +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSend +MPU_xStreamBufferSend: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xStreamBufferSend_Unpriv + MPU_xStreamBufferSend_Priv: + b MPU_xStreamBufferSendImpl + MPU_xStreamBufferSend_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferReceive +MPU_xStreamBufferReceive: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xStreamBufferReceive_Unpriv + MPU_xStreamBufferReceive_Priv: + b MPU_xStreamBufferReceiveImpl + MPU_xStreamBufferReceive_Unpriv: + svc #SYSTEM_CALL_xStreamBufferReceive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferIsFull +MPU_xStreamBufferIsFull: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xStreamBufferIsFull_Unpriv + MPU_xStreamBufferIsFull_Priv: + b MPU_xStreamBufferIsFullImpl + MPU_xStreamBufferIsFull_Unpriv: + svc #SYSTEM_CALL_xStreamBufferIsFull +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferIsEmpty +MPU_xStreamBufferIsEmpty: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xStreamBufferIsEmpty_Unpriv + MPU_xStreamBufferIsEmpty_Priv: + b MPU_xStreamBufferIsEmptyImpl + MPU_xStreamBufferIsEmpty_Unpriv: + svc #SYSTEM_CALL_xStreamBufferIsEmpty +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSpacesAvailable +MPU_xStreamBufferSpacesAvailable: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xStreamBufferSpacesAvailable_Unpriv + MPU_xStreamBufferSpacesAvailable_Priv: + b MPU_xStreamBufferSpacesAvailableImpl + MPU_xStreamBufferSpacesAvailable_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSpacesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferBytesAvailable +MPU_xStreamBufferBytesAvailable: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xStreamBufferBytesAvailable_Unpriv + MPU_xStreamBufferBytesAvailable_Priv: + b MPU_xStreamBufferBytesAvailableImpl + MPU_xStreamBufferBytesAvailable_Unpriv: + svc #SYSTEM_CALL_xStreamBufferBytesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSetTriggerLevel +MPU_xStreamBufferSetTriggerLevel: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xStreamBufferSetTriggerLevel_Unpriv + MPU_xStreamBufferSetTriggerLevel_Priv: + b MPU_xStreamBufferSetTriggerLevelImpl + MPU_xStreamBufferSetTriggerLevel_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferNextMessageLengthBytes +MPU_xStreamBufferNextMessageLengthBytes: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv + MPU_xStreamBufferNextMessageLengthBytes_Priv: + b MPU_xStreamBufferNextMessageLengthBytesImpl + MPU_xStreamBufferNextMessageLengthBytes_Unpriv: + svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes +/*-----------------------------------------------------------*/ + +/* Default weak implementations in case one is not available from + * mpu_wrappers because of config options. */ + + PUBWEAK MPU_xTaskDelayUntilImpl +MPU_xTaskDelayUntilImpl: + b MPU_xTaskDelayUntilImpl + + PUBWEAK MPU_xTaskAbortDelayImpl +MPU_xTaskAbortDelayImpl: + b MPU_xTaskAbortDelayImpl + + PUBWEAK MPU_vTaskDelayImpl +MPU_vTaskDelayImpl: + b MPU_vTaskDelayImpl + + PUBWEAK MPU_uxTaskPriorityGetImpl +MPU_uxTaskPriorityGetImpl: + b MPU_uxTaskPriorityGetImpl + + PUBWEAK MPU_eTaskGetStateImpl +MPU_eTaskGetStateImpl: + b MPU_eTaskGetStateImpl + + PUBWEAK MPU_vTaskGetInfoImpl +MPU_vTaskGetInfoImpl: + b MPU_vTaskGetInfoImpl + + PUBWEAK MPU_xTaskGetIdleTaskHandleImpl +MPU_xTaskGetIdleTaskHandleImpl: + b MPU_xTaskGetIdleTaskHandleImpl + + PUBWEAK MPU_vTaskSuspendImpl +MPU_vTaskSuspendImpl: + b MPU_vTaskSuspendImpl + + PUBWEAK MPU_vTaskResumeImpl +MPU_vTaskResumeImpl: + b MPU_vTaskResumeImpl + + PUBWEAK MPU_xTaskGetTickCountImpl +MPU_xTaskGetTickCountImpl: + b MPU_xTaskGetTickCountImpl + + PUBWEAK MPU_uxTaskGetNumberOfTasksImpl +MPU_uxTaskGetNumberOfTasksImpl: + b MPU_uxTaskGetNumberOfTasksImpl + + PUBWEAK MPU_ulTaskGetRunTimeCounterImpl +MPU_ulTaskGetRunTimeCounterImpl: + b MPU_ulTaskGetRunTimeCounterImpl + + PUBWEAK MPU_ulTaskGetRunTimePercentImpl +MPU_ulTaskGetRunTimePercentImpl: + b MPU_ulTaskGetRunTimePercentImpl + + PUBWEAK MPU_ulTaskGetIdleRunTimePercentImpl +MPU_ulTaskGetIdleRunTimePercentImpl: + b MPU_ulTaskGetIdleRunTimePercentImpl + + PUBWEAK MPU_ulTaskGetIdleRunTimeCounterImpl +MPU_ulTaskGetIdleRunTimeCounterImpl: + b MPU_ulTaskGetIdleRunTimeCounterImpl + + PUBWEAK MPU_vTaskSetApplicationTaskTagImpl +MPU_vTaskSetApplicationTaskTagImpl: + b MPU_vTaskSetApplicationTaskTagImpl + + PUBWEAK MPU_xTaskGetApplicationTaskTagImpl +MPU_xTaskGetApplicationTaskTagImpl: + b MPU_xTaskGetApplicationTaskTagImpl + + PUBWEAK MPU_vTaskSetThreadLocalStoragePointerImpl +MPU_vTaskSetThreadLocalStoragePointerImpl: + b MPU_vTaskSetThreadLocalStoragePointerImpl + + PUBWEAK MPU_pvTaskGetThreadLocalStoragePointerImpl +MPU_pvTaskGetThreadLocalStoragePointerImpl: + b MPU_pvTaskGetThreadLocalStoragePointerImpl + + PUBWEAK MPU_uxTaskGetSystemStateImpl +MPU_uxTaskGetSystemStateImpl: + b MPU_uxTaskGetSystemStateImpl + + PUBWEAK MPU_uxTaskGetStackHighWaterMarkImpl +MPU_uxTaskGetStackHighWaterMarkImpl: + b MPU_uxTaskGetStackHighWaterMarkImpl + + PUBWEAK MPU_uxTaskGetStackHighWaterMark2Impl +MPU_uxTaskGetStackHighWaterMark2Impl: + b MPU_uxTaskGetStackHighWaterMark2Impl + + PUBWEAK MPU_xTaskGetCurrentTaskHandleImpl +MPU_xTaskGetCurrentTaskHandleImpl: + b MPU_xTaskGetCurrentTaskHandleImpl + + PUBWEAK MPU_xTaskGetSchedulerStateImpl +MPU_xTaskGetSchedulerStateImpl: + b MPU_xTaskGetSchedulerStateImpl + + PUBWEAK MPU_vTaskSetTimeOutStateImpl +MPU_vTaskSetTimeOutStateImpl: + b MPU_vTaskSetTimeOutStateImpl + + PUBWEAK MPU_xTaskCheckForTimeOutImpl +MPU_xTaskCheckForTimeOutImpl: + b MPU_xTaskCheckForTimeOutImpl + + PUBWEAK MPU_xTaskGenericNotifyImpl +MPU_xTaskGenericNotifyImpl: + b MPU_xTaskGenericNotifyImpl + + PUBWEAK MPU_xTaskGenericNotifyWaitImpl +MPU_xTaskGenericNotifyWaitImpl: + b MPU_xTaskGenericNotifyWaitImpl + + PUBWEAK MPU_ulTaskGenericNotifyTakeImpl +MPU_ulTaskGenericNotifyTakeImpl: + b MPU_ulTaskGenericNotifyTakeImpl + + PUBWEAK MPU_xTaskGenericNotifyStateClearImpl +MPU_xTaskGenericNotifyStateClearImpl: + b MPU_xTaskGenericNotifyStateClearImpl + + PUBWEAK MPU_ulTaskGenericNotifyValueClearImpl +MPU_ulTaskGenericNotifyValueClearImpl: + b MPU_ulTaskGenericNotifyValueClearImpl + + PUBWEAK MPU_xQueueGenericSendImpl +MPU_xQueueGenericSendImpl: + b MPU_xQueueGenericSendImpl + + PUBWEAK MPU_uxQueueMessagesWaitingImpl +MPU_uxQueueMessagesWaitingImpl: + b MPU_uxQueueMessagesWaitingImpl + + PUBWEAK MPU_uxQueueSpacesAvailableImpl +MPU_uxQueueSpacesAvailableImpl: + b MPU_uxQueueSpacesAvailableImpl + + PUBWEAK MPU_xQueueReceiveImpl +MPU_xQueueReceiveImpl: + b MPU_xQueueReceiveImpl + + PUBWEAK MPU_xQueuePeekImpl +MPU_xQueuePeekImpl: + b MPU_xQueuePeekImpl + + PUBWEAK MPU_xQueueSemaphoreTakeImpl +MPU_xQueueSemaphoreTakeImpl: + b MPU_xQueueSemaphoreTakeImpl + + PUBWEAK MPU_xQueueGetMutexHolderImpl +MPU_xQueueGetMutexHolderImpl: + b MPU_xQueueGetMutexHolderImpl + + PUBWEAK MPU_xQueueTakeMutexRecursiveImpl +MPU_xQueueTakeMutexRecursiveImpl: + b MPU_xQueueTakeMutexRecursiveImpl + + PUBWEAK MPU_xQueueGiveMutexRecursiveImpl +MPU_xQueueGiveMutexRecursiveImpl: + b MPU_xQueueGiveMutexRecursiveImpl + + PUBWEAK MPU_xQueueSelectFromSetImpl +MPU_xQueueSelectFromSetImpl: + b MPU_xQueueSelectFromSetImpl + + PUBWEAK MPU_xQueueAddToSetImpl +MPU_xQueueAddToSetImpl: + b MPU_xQueueAddToSetImpl + + PUBWEAK MPU_vQueueAddToRegistryImpl +MPU_vQueueAddToRegistryImpl: + b MPU_vQueueAddToRegistryImpl + + PUBWEAK MPU_vQueueUnregisterQueueImpl +MPU_vQueueUnregisterQueueImpl: + b MPU_vQueueUnregisterQueueImpl + + PUBWEAK MPU_pcQueueGetNameImpl +MPU_pcQueueGetNameImpl: + b MPU_pcQueueGetNameImpl + + PUBWEAK MPU_pvTimerGetTimerIDImpl +MPU_pvTimerGetTimerIDImpl: + b MPU_pvTimerGetTimerIDImpl + + PUBWEAK MPU_vTimerSetTimerIDImpl +MPU_vTimerSetTimerIDImpl: + b MPU_vTimerSetTimerIDImpl + + PUBWEAK MPU_xTimerIsTimerActiveImpl +MPU_xTimerIsTimerActiveImpl: + b MPU_xTimerIsTimerActiveImpl + + PUBWEAK MPU_xTimerGetTimerDaemonTaskHandleImpl +MPU_xTimerGetTimerDaemonTaskHandleImpl: + b MPU_xTimerGetTimerDaemonTaskHandleImpl + + PUBWEAK MPU_xTimerGenericCommandFromTaskImpl +MPU_xTimerGenericCommandFromTaskImpl: + b MPU_xTimerGenericCommandFromTaskImpl + + PUBWEAK MPU_pcTimerGetNameImpl +MPU_pcTimerGetNameImpl: + b MPU_pcTimerGetNameImpl + + PUBWEAK MPU_vTimerSetReloadModeImpl +MPU_vTimerSetReloadModeImpl: + b MPU_vTimerSetReloadModeImpl + + PUBWEAK MPU_xTimerGetReloadModeImpl +MPU_xTimerGetReloadModeImpl: + b MPU_xTimerGetReloadModeImpl + + PUBWEAK MPU_uxTimerGetReloadModeImpl +MPU_uxTimerGetReloadModeImpl: + b MPU_uxTimerGetReloadModeImpl + + PUBWEAK MPU_xTimerGetPeriodImpl +MPU_xTimerGetPeriodImpl: + b MPU_xTimerGetPeriodImpl + + PUBWEAK MPU_xTimerGetExpiryTimeImpl +MPU_xTimerGetExpiryTimeImpl: + b MPU_xTimerGetExpiryTimeImpl + + PUBWEAK MPU_xEventGroupWaitBitsImpl +MPU_xEventGroupWaitBitsImpl: + b MPU_xEventGroupWaitBitsImpl + + PUBWEAK MPU_xEventGroupClearBitsImpl +MPU_xEventGroupClearBitsImpl: + b MPU_xEventGroupClearBitsImpl + + PUBWEAK MPU_xEventGroupSetBitsImpl +MPU_xEventGroupSetBitsImpl: + b MPU_xEventGroupSetBitsImpl + + PUBWEAK MPU_xEventGroupSyncImpl +MPU_xEventGroupSyncImpl: + b MPU_xEventGroupSyncImpl + + PUBWEAK MPU_uxEventGroupGetNumberImpl +MPU_uxEventGroupGetNumberImpl: + b MPU_uxEventGroupGetNumberImpl + + PUBWEAK MPU_vEventGroupSetNumberImpl +MPU_vEventGroupSetNumberImpl: + b MPU_vEventGroupSetNumberImpl + + PUBWEAK MPU_xStreamBufferSendImpl +MPU_xStreamBufferSendImpl: + b MPU_xStreamBufferSendImpl + + PUBWEAK MPU_xStreamBufferReceiveImpl +MPU_xStreamBufferReceiveImpl: + b MPU_xStreamBufferReceiveImpl + + PUBWEAK MPU_xStreamBufferIsFullImpl +MPU_xStreamBufferIsFullImpl: + b MPU_xStreamBufferIsFullImpl + + PUBWEAK MPU_xStreamBufferIsEmptyImpl +MPU_xStreamBufferIsEmptyImpl: + b MPU_xStreamBufferIsEmptyImpl + + PUBWEAK MPU_xStreamBufferSpacesAvailableImpl +MPU_xStreamBufferSpacesAvailableImpl: + b MPU_xStreamBufferSpacesAvailableImpl + + PUBWEAK MPU_xStreamBufferBytesAvailableImpl +MPU_xStreamBufferBytesAvailableImpl: + b MPU_xStreamBufferBytesAvailableImpl + + PUBWEAK MPU_xStreamBufferSetTriggerLevelImpl +MPU_xStreamBufferSetTriggerLevelImpl: + b MPU_xStreamBufferSetTriggerLevelImpl + + PUBWEAK MPU_xStreamBufferNextMessageLengthBytesImpl +MPU_xStreamBufferNextMessageLengthBytesImpl: + b MPU_xStreamBufferNextMessageLengthBytesImpl + +/*-----------------------------------------------------------*/ + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + END diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s new file mode 100644 index 000000000..bfe9eee4b --- /dev/null +++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s @@ -0,0 +1,456 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" + +/* System call numbers includes. */ +#include "mpu_syscall_numbers.h" + +#ifndef configUSE_MPU_WRAPPERS_V1 + #define configUSE_MPU_WRAPPERS_V1 0 +#endif + +#ifndef configRUN_FREERTOS_SECURE_ONLY + #define configRUN_FREERTOS_SECURE_ONLY 0 +#endif + + EXTERN pxCurrentTCB + EXTERN vTaskSwitchContext + EXTERN vPortSVCHandler_C +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + EXTERN vSystemCallEnter + EXTERN vSystemCallExit +#endif + + PUBLIC xIsPrivileged + PUBLIC vResetPrivilege + PUBLIC vRestoreContextOfFirstTask + PUBLIC vRaisePrivilege + PUBLIC vStartFirstTask + PUBLIC ulSetInterruptMask + PUBLIC vClearInterruptMask + PUBLIC PendSV_Handler + PUBLIC SVC_Handler + +#if ( configENABLE_FPU == 1 ) + #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0. +#endif +/*-----------------------------------------------------------*/ + +/*---------------- Unprivileged Functions -------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION .text:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +xIsPrivileged: + mrs r0, control /* r0 = CONTROL. */ + movs r1, #1 /* r1 = 1. */ + tst r0, r1 /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */ + beq running_privileged /* If the result of previous AND operation was 0, branch. */ + movs r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + bx lr /* Return. */ + running_privileged: + movs r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + bx lr /* Return. */ + +/*-----------------------------------------------------------*/ + +vResetPrivilege: + mrs r0, control /* r0 = CONTROL. */ + movs r1, #1 /* r1 = 1. */ + orrs r0, r1 /* r0 = r0 | r1. */ + msr control, r0 /* CONTROL = r0. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +/*----------------- Privileged Functions --------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION privileged_functions:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +vRestoreContextOfFirstTask: + program_mpu_first_task: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r3] /* r0 = pxCurrentTCB.*/ + + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + movs r3, #1 /* r3 = 1. */ + bics r2, r3 /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */ + str r2, [r1] /* Disable MPU. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r1, [r2] /* Program MAIR0. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */ + + movs r3, #4 /* r3 = 4. */ + str r3, [r1] /* Program RNR = 4. */ + ldmia r0!, {r4-r5} /* Read first set of RBAR/RLAR registers from TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + stmia r2!, {r4-r5} /* Write first set of RBAR/RLAR registers. */ + movs r3, #5 /* r3 = 5. */ + str r3, [r1] /* Program RNR = 5. */ + ldmia r0!, {r4-r5} /* Read second set of RBAR/RLAR registers from TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + stmia r2!, {r4-r5} /* Write second set of RBAR/RLAR registers. */ + movs r3, #6 /* r3 = 6. */ + str r3, [r1] /* Program RNR = 6. */ + ldmia r0!, {r4-r5} /* Read third set of RBAR/RLAR registers from TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + stmia r2!, {r4-r5} /* Write third set of RBAR/RLAR registers. */ + movs r3, #7 /* r3 = 6. */ + str r3, [r1] /* Program RNR = 7. */ + ldmia r0!, {r4-r5} /* Read fourth set of RBAR/RLAR registers from TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + stmia r2!, {r4-r5} /* Write fourth set of RBAR/RLAR registers. */ + + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + movs r3, #1 /* r3 = 1. */ + orrs r2, r3 /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */ + str r2, [r1] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + + restore_context_first_task: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r2] /* r0 = pxCurrentTCB.*/ + ldr r1, [r0] /* r1 = Location of saved context in TCB. */ + + restore_special_regs_first_task: + subs r1, #16 + ldmia r1!, {r2-r5} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */ + subs r1, #16 + msr psp, r2 + #if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + msr psplim, r3 + #endif + msr control, r4 + mov lr, r5 + + restore_general_regs_first_task: + subs r1, #32 + ldmia r1!, {r4-r7} /* r4-r7 contain half of the hardware saved context. */ + stmia r2!, {r4-r7} /* Copy half of the the hardware saved context on the task stack. */ + ldmia r1!, {r4-r7} /* r4-r7 contain rest half of the hardware saved context. */ + stmia r2!, {r4-r7} /* Copy rest half of the the hardware saved context on the task stack. */ + subs r1, #48 + ldmia r1!, {r4-r7} /* Restore r8-r11. */ + mov r8, r4 /* r8 = r4. */ + mov r9, r5 /* r9 = r5. */ + mov r10, r6 /* r10 = r6. */ + mov r11, r7 /* r11 = r7. */ + subs r1, #32 + ldmia r1!, {r4-r7} /* Restore r4-r7. */ + subs r1, #16 + + restore_context_done_first_task: + str r1, [r0] /* Save the location where the context should be saved next as the first member of TCB. */ + bx lr + +#else /* configENABLE_MPU */ + +vRestoreContextOfFirstTask: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + + ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */ +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + msr psplim, r1 /* Set this task's PSPLIM value. */ +#endif + movs r1, #2 /* r1 = 2. */ + msr CONTROL, r1 /* Switch to use PSP in the thread mode. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + bx r2 /* Finally, branch to EXC_RETURN. */ + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +vRaisePrivilege: + mrs r0, control /* Read the CONTROL register. */ + movs r1, #1 /* r1 = 1. */ + bics r0, r1 /* Clear the bit 0. */ + msr control, r0 /* Write back the new CONTROL value. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vStartFirstTask: + ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */ + ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */ + ldr r0, [r0] /* The first entry in vector table is stack pointer. */ + msr msp, r0 /* Set the MSP back to the start of the stack. */ + cpsie i /* Globally enable interrupts. */ + dsb + isb + svc 102 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */ + nop +/*-----------------------------------------------------------*/ + +ulSetInterruptMask: + mrs r0, PRIMASK + cpsid i + bx lr +/*-----------------------------------------------------------*/ + +vClearInterruptMask: + msr PRIMASK, r0 + bx lr +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +PendSV_Handler: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r2] /* r0 = pxCurrentTCB. */ + ldr r1, [r0] /* r1 = Location in TCB where the context should be saved. */ + mrs r2, psp /* r2 = PSP. */ + + save_general_regs: + stmia r1!, {r4-r7} /* Store r4-r7. */ + mov r4, r8 /* r4 = r8. */ + mov r5, r9 /* r5 = r9. */ + mov r6, r10 /* r6 = r10. */ + mov r7, r11 /* r7 = r11. */ + stmia r1!, {r4-r7} /* Store r8-r11. */ + ldmia r2!, {r4-r7} /* Copy half of the hardware saved context into r4-r7. */ + stmia r1!, {r4-r7} /* Store the hardware saved context. */ + ldmia r2!, {r4-r7} /* Copy rest half of the hardware saved context into r4-r7. */ + stmia r1!, {r4-r7} /* Store the hardware saved context. */ + + save_special_regs: + mrs r2, psp /* r2 = PSP. */ + #if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + mrs r3, psplim /* r3 = PSPLIM. */ + #else + movs r3, #0 /* r3 = 0. 0 is stored in the PSPLIM slot. */ + #endif + mrs r4, control /* r4 = CONTROL. */ + mov r5, lr /* r5 = LR. */ + stmia r1!, {r2-r5} /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ + str r1, [r0] /* Save the location from where the context should be restored as the first member of TCB. */ + + select_next_task: + cpsid i + bl vTaskSwitchContext + cpsie i + + program_mpu: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r3] /* r0 = pxCurrentTCB.*/ + + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + movs r3, #1 /* r3 = 1. */ + bics r2, r3 /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */ + str r2, [r1] /* Disable MPU. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r1, [r2] /* Program MAIR0. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */ + + movs r3, #4 /* r3 = 4. */ + str r3, [r1] /* Program RNR = 4. */ + ldmia r0!, {r4-r5} /* Read first set of RBAR/RLAR registers from TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + stmia r2!, {r4-r5} /* Write first set of RBAR/RLAR registers. */ + movs r3, #5 /* r3 = 5. */ + str r3, [r1] /* Program RNR = 5. */ + ldmia r0!, {r4-r5} /* Read second set of RBAR/RLAR registers from TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + stmia r2!, {r4-r5} /* Write second set of RBAR/RLAR registers. */ + movs r3, #6 /* r3 = 6. */ + str r3, [r1] /* Program RNR = 6. */ + ldmia r0!, {r4-r5} /* Read third set of RBAR/RLAR registers from TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + stmia r2!, {r4-r5} /* Write third set of RBAR/RLAR registers. */ + movs r3, #7 /* r3 = 6. */ + str r3, [r1] /* Program RNR = 7. */ + ldmia r0!, {r4-r5} /* Read fourth set of RBAR/RLAR registers from TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + stmia r2!, {r4-r5} /* Write fourth set of RBAR/RLAR registers. */ + + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + movs r3, #1 /* r3 = 1. */ + orrs r2, r3 /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */ + str r2, [r1] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + + restore_context: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r2] /* r0 = pxCurrentTCB.*/ + ldr r1, [r0] /* r1 = Location of saved context in TCB. */ + + restore_special_regs: + subs r1, #16 + ldmia r1!, {r2-r5} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */ + subs r1, #16 + msr psp, r2 + #if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + msr psplim, r3 + #endif + msr control, r4 + mov lr, r5 + + restore_general_regs: + subs r1, #32 + ldmia r1!, {r4-r7} /* r4-r7 contain half of the hardware saved context. */ + stmia r2!, {r4-r7} /* Copy half of the the hardware saved context on the task stack. */ + ldmia r1!, {r4-r7} /* r4-r7 contain rest half of the hardware saved context. */ + stmia r2!, {r4-r7} /* Copy rest half of the the hardware saved context on the task stack. */ + subs r1, #48 + ldmia r1!, {r4-r7} /* Restore r8-r11. */ + mov r8, r4 /* r8 = r4. */ + mov r9, r5 /* r9 = r5. */ + mov r10, r6 /* r10 = r6. */ + mov r11, r7 /* r11 = r7. */ + subs r1, #32 + ldmia r1!, {r4-r7} /* Restore r4-r7. */ + subs r1, #16 + + restore_context_done: + str r1, [r0] /* Save the location where the context should be saved next as the first member of TCB. */ + bx lr + +#else /* configENABLE_MPU */ + +PendSV_Handler: + mrs r0, psp /* Read PSP in r0. */ + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + + subs r0, r0, #40 /* Make space for PSPLIM, LR and the remaining registers on the stack. */ + str r0, [r1] /* Save the new top of stack in TCB. */ +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + mrs r2, psplim /* r2 = PSPLIM. */ +#else + movs r2, #0 /* r0 = 0. 0 is stored in the PSPLIM slot. */ +#endif + mov r3, lr /* r3 = LR/EXC_RETURN. */ + stmia r0!, {r2-r7} /* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */ + mov r4, r8 /* r4 = r8. */ + mov r5, r9 /* r5 = r9. */ + mov r6, r10 /* r6 = r10. */ + mov r7, r11 /* r7 = r11. */ + stmia r0!, {r4-r7} /* Store the high registers that are not saved automatically. */ + + cpsid i + bl vTaskSwitchContext + cpsie i + + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ + + adds r0, r0, #24 /* Move to the high registers. */ + ldmia r0!, {r4-r7} /* Restore the high registers that are not automatically restored. */ + mov r8, r4 /* r8 = r4. */ + mov r9, r5 /* r9 = r5. */ + mov r10, r6 /* r10 = r6. */ + mov r11, r7 /* r11 = r7. */ + msr psp, r0 /* Remember the new top of stack for the task. */ + subs r0, r0, #40 /* Move to the starting of the saved context. */ + ldmia r0!, {r2-r7} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */ +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + msr psplim, r2 /* Restore the PSPLIM register value for the task. */ +#endif + bx r3 + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + +SVC_Handler: + movs r0, #4 + mov r1, lr + tst r0, r1 + beq stack_on_msp + stack_on_psp: + mrs r0, psp + b route_svc + stack_on_msp: + mrs r0, msp + b route_svc + + route_svc: + ldr r3, [r0, #24] + subs r3, #2 + ldrb r2, [r3, #0] + cmp r2, #NUM_SYSTEM_CALLS + blt system_call_enter + cmp r2, #104 /* portSVC_SYSTEM_CALL_EXIT. */ + beq system_call_exit + b vPortSVCHandler_C + + system_call_enter: + b vSystemCallEnter + system_call_exit: + b vSystemCallExit + +#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +SVC_Handler: + movs r0, #4 + mov r1, lr + tst r0, r1 + beq stacking_used_msp + mrs r0, psp + b vPortSVCHandler_C + stacking_used_msp: + mrs r0, msp + b vPortSVCHandler_C + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + + END diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h new file mode 100644 index 000000000..9d6c3368e --- /dev/null +++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h @@ -0,0 +1,92 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M23" +#define portHAS_ARMV8M_MAIN_EXTENSION 0 +#define portARMV8M_MINOR_VERSION 0 +#define portDONT_DISCARD __root +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +#if ( configTOTAL_MPU_REGIONS == 16 ) + #error 16 MPU regions are not yet supported for this port. +#endif + +#ifndef configENABLE_MVE + #define configENABLE_MVE 0 +#elif ( configENABLE_MVE != 0 ) + #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M23. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" ) +#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ +#pragma diag_suppress=Be006 +#pragma diag_suppress=Pa082 +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/mpu_wrappers_v2_asm.S b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/mpu_wrappers_v2_asm.S new file mode 100644 index 000000000..d2cb78e92 --- /dev/null +++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/mpu_wrappers_v2_asm.S @@ -0,0 +1,1242 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + + SECTION freertos_system_calls:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +#include "FreeRTOSConfig.h" +#include "mpu_syscall_numbers.h" + +#ifndef configUSE_MPU_WRAPPERS_V1 + #define configUSE_MPU_WRAPPERS_V1 0 +#endif + +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + PUBLIC MPU_xTaskDelayUntil +MPU_xTaskDelayUntil: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskDelayUntil_Unpriv + MPU_xTaskDelayUntil_Priv: + b MPU_xTaskDelayUntilImpl + MPU_xTaskDelayUntil_Unpriv: + svc #SYSTEM_CALL_xTaskDelayUntil +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskAbortDelay +MPU_xTaskAbortDelay: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskAbortDelay_Unpriv + MPU_xTaskAbortDelay_Priv: + b MPU_xTaskAbortDelayImpl + MPU_xTaskAbortDelay_Unpriv: + svc #SYSTEM_CALL_xTaskAbortDelay +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskDelay +MPU_vTaskDelay: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskDelay_Unpriv + MPU_vTaskDelay_Priv: + b MPU_vTaskDelayImpl + MPU_vTaskDelay_Unpriv: + svc #SYSTEM_CALL_vTaskDelay +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskPriorityGet +MPU_uxTaskPriorityGet: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskPriorityGet_Unpriv + MPU_uxTaskPriorityGet_Priv: + b MPU_uxTaskPriorityGetImpl + MPU_uxTaskPriorityGet_Unpriv: + svc #SYSTEM_CALL_uxTaskPriorityGet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_eTaskGetState +MPU_eTaskGetState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_eTaskGetState_Unpriv + MPU_eTaskGetState_Priv: + b MPU_eTaskGetStateImpl + MPU_eTaskGetState_Unpriv: + svc #SYSTEM_CALL_eTaskGetState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskGetInfo +MPU_vTaskGetInfo: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskGetInfo_Unpriv + MPU_vTaskGetInfo_Priv: + b MPU_vTaskGetInfoImpl + MPU_vTaskGetInfo_Unpriv: + svc #SYSTEM_CALL_vTaskGetInfo +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetIdleTaskHandle +MPU_xTaskGetIdleTaskHandle: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetIdleTaskHandle_Unpriv + MPU_xTaskGetIdleTaskHandle_Priv: + b MPU_xTaskGetIdleTaskHandleImpl + MPU_xTaskGetIdleTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTaskGetIdleTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSuspend +MPU_vTaskSuspend: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSuspend_Unpriv + MPU_vTaskSuspend_Priv: + b MPU_vTaskSuspendImpl + MPU_vTaskSuspend_Unpriv: + svc #SYSTEM_CALL_vTaskSuspend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskResume +MPU_vTaskResume: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskResume_Unpriv + MPU_vTaskResume_Priv: + b MPU_vTaskResumeImpl + MPU_vTaskResume_Unpriv: + svc #SYSTEM_CALL_vTaskResume +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetTickCount +MPU_xTaskGetTickCount: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetTickCount_Unpriv + MPU_xTaskGetTickCount_Priv: + b MPU_xTaskGetTickCountImpl + MPU_xTaskGetTickCount_Unpriv: + svc #SYSTEM_CALL_xTaskGetTickCount +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetNumberOfTasks +MPU_uxTaskGetNumberOfTasks: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetNumberOfTasks_Unpriv + MPU_uxTaskGetNumberOfTasks_Priv: + b MPU_uxTaskGetNumberOfTasksImpl + MPU_uxTaskGetNumberOfTasks_Unpriv: + svc #SYSTEM_CALL_uxTaskGetNumberOfTasks +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetRunTimeCounter +MPU_ulTaskGetRunTimeCounter: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetRunTimeCounter_Unpriv + MPU_ulTaskGetRunTimeCounter_Priv: + b MPU_ulTaskGetRunTimeCounterImpl + MPU_ulTaskGetRunTimeCounter_Unpriv: + svc #SYSTEM_CALL_ulTaskGetRunTimeCounter +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetRunTimePercent +MPU_ulTaskGetRunTimePercent: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetRunTimePercent_Unpriv + MPU_ulTaskGetRunTimePercent_Priv: + b MPU_ulTaskGetRunTimePercentImpl + MPU_ulTaskGetRunTimePercent_Unpriv: + svc #SYSTEM_CALL_ulTaskGetRunTimePercent +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetIdleRunTimePercent +MPU_ulTaskGetIdleRunTimePercent: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetIdleRunTimePercent_Unpriv + MPU_ulTaskGetIdleRunTimePercent_Priv: + b MPU_ulTaskGetIdleRunTimePercentImpl + MPU_ulTaskGetIdleRunTimePercent_Unpriv: + svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetIdleRunTimeCounter +MPU_ulTaskGetIdleRunTimeCounter: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv + MPU_ulTaskGetIdleRunTimeCounter_Priv: + b MPU_ulTaskGetIdleRunTimeCounterImpl + MPU_ulTaskGetIdleRunTimeCounter_Unpriv: + svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetApplicationTaskTag +MPU_vTaskSetApplicationTaskTag: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetApplicationTaskTag_Unpriv + MPU_vTaskSetApplicationTaskTag_Priv: + b MPU_vTaskSetApplicationTaskTagImpl + MPU_vTaskSetApplicationTaskTag_Unpriv: + svc #SYSTEM_CALL_vTaskSetApplicationTaskTag +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetApplicationTaskTag +MPU_xTaskGetApplicationTaskTag: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetApplicationTaskTag_Unpriv + MPU_xTaskGetApplicationTaskTag_Priv: + b MPU_xTaskGetApplicationTaskTagImpl + MPU_xTaskGetApplicationTaskTag_Unpriv: + svc #SYSTEM_CALL_xTaskGetApplicationTaskTag +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetThreadLocalStoragePointer +MPU_vTaskSetThreadLocalStoragePointer: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv + MPU_vTaskSetThreadLocalStoragePointer_Priv: + b MPU_vTaskSetThreadLocalStoragePointerImpl + MPU_vTaskSetThreadLocalStoragePointer_Unpriv: + svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pvTaskGetThreadLocalStoragePointer +MPU_pvTaskGetThreadLocalStoragePointer: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv + MPU_pvTaskGetThreadLocalStoragePointer_Priv: + b MPU_pvTaskGetThreadLocalStoragePointerImpl + MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: + svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetSystemState +MPU_uxTaskGetSystemState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetSystemState_Unpriv + MPU_uxTaskGetSystemState_Priv: + b MPU_uxTaskGetSystemStateImpl + MPU_uxTaskGetSystemState_Unpriv: + svc #SYSTEM_CALL_uxTaskGetSystemState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetStackHighWaterMark +MPU_uxTaskGetStackHighWaterMark: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetStackHighWaterMark_Unpriv + MPU_uxTaskGetStackHighWaterMark_Priv: + b MPU_uxTaskGetStackHighWaterMarkImpl + MPU_uxTaskGetStackHighWaterMark_Unpriv: + svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetStackHighWaterMark2 +MPU_uxTaskGetStackHighWaterMark2: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetStackHighWaterMark2_Unpriv + MPU_uxTaskGetStackHighWaterMark2_Priv: + b MPU_uxTaskGetStackHighWaterMark2Impl + MPU_uxTaskGetStackHighWaterMark2_Unpriv: + svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2 +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetCurrentTaskHandle +MPU_xTaskGetCurrentTaskHandle: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetCurrentTaskHandle_Unpriv + MPU_xTaskGetCurrentTaskHandle_Priv: + b MPU_xTaskGetCurrentTaskHandleImpl + MPU_xTaskGetCurrentTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetSchedulerState +MPU_xTaskGetSchedulerState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetSchedulerState_Unpriv + MPU_xTaskGetSchedulerState_Priv: + b MPU_xTaskGetSchedulerStateImpl + MPU_xTaskGetSchedulerState_Unpriv: + svc #SYSTEM_CALL_xTaskGetSchedulerState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetTimeOutState +MPU_vTaskSetTimeOutState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetTimeOutState_Unpriv + MPU_vTaskSetTimeOutState_Priv: + b MPU_vTaskSetTimeOutStateImpl + MPU_vTaskSetTimeOutState_Unpriv: + svc #SYSTEM_CALL_vTaskSetTimeOutState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskCheckForTimeOut +MPU_xTaskCheckForTimeOut: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskCheckForTimeOut_Unpriv + MPU_xTaskCheckForTimeOut_Priv: + b MPU_xTaskCheckForTimeOutImpl + MPU_xTaskCheckForTimeOut_Unpriv: + svc #SYSTEM_CALL_xTaskCheckForTimeOut +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyEntry +MPU_xTaskGenericNotifyEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotify_Unpriv + MPU_xTaskGenericNotify_Priv: + b MPU_xTaskGenericNotifyImpl + MPU_xTaskGenericNotify_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotify +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyWaitEntry +MPU_xTaskGenericNotifyWaitEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotifyWait_Unpriv + MPU_xTaskGenericNotifyWait_Priv: + b MPU_xTaskGenericNotifyWaitImpl + MPU_xTaskGenericNotifyWait_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotifyWait +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGenericNotifyTake +MPU_ulTaskGenericNotifyTake: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGenericNotifyTake_Unpriv + MPU_ulTaskGenericNotifyTake_Priv: + b MPU_ulTaskGenericNotifyTakeImpl + MPU_ulTaskGenericNotifyTake_Unpriv: + svc #SYSTEM_CALL_ulTaskGenericNotifyTake +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyStateClear +MPU_xTaskGenericNotifyStateClear: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotifyStateClear_Unpriv + MPU_xTaskGenericNotifyStateClear_Priv: + b MPU_xTaskGenericNotifyStateClearImpl + MPU_xTaskGenericNotifyStateClear_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotifyStateClear +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGenericNotifyValueClear +MPU_ulTaskGenericNotifyValueClear: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGenericNotifyValueClear_Unpriv + MPU_ulTaskGenericNotifyValueClear_Priv: + b MPU_ulTaskGenericNotifyValueClearImpl + MPU_ulTaskGenericNotifyValueClear_Unpriv: + svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGenericSend +MPU_xQueueGenericSend: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGenericSend_Unpriv + MPU_xQueueGenericSend_Priv: + b MPU_xQueueGenericSendImpl + MPU_xQueueGenericSend_Unpriv: + svc #SYSTEM_CALL_xQueueGenericSend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxQueueMessagesWaiting +MPU_uxQueueMessagesWaiting: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxQueueMessagesWaiting_Unpriv + MPU_uxQueueMessagesWaiting_Priv: + b MPU_uxQueueMessagesWaitingImpl + MPU_uxQueueMessagesWaiting_Unpriv: + svc #SYSTEM_CALL_uxQueueMessagesWaiting +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxQueueSpacesAvailable +MPU_uxQueueSpacesAvailable: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxQueueSpacesAvailable_Unpriv + MPU_uxQueueSpacesAvailable_Priv: + b MPU_uxQueueSpacesAvailableImpl + MPU_uxQueueSpacesAvailable_Unpriv: + svc #SYSTEM_CALL_uxQueueSpacesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueReceive +MPU_xQueueReceive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueReceive_Unpriv + MPU_xQueueReceive_Priv: + b MPU_xQueueReceiveImpl + MPU_xQueueReceive_Unpriv: + svc #SYSTEM_CALL_xQueueReceive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueuePeek +MPU_xQueuePeek: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueuePeek_Unpriv + MPU_xQueuePeek_Priv: + b MPU_xQueuePeekImpl + MPU_xQueuePeek_Unpriv: + svc #SYSTEM_CALL_xQueuePeek +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueSemaphoreTake +MPU_xQueueSemaphoreTake: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueSemaphoreTake_Unpriv + MPU_xQueueSemaphoreTake_Priv: + b MPU_xQueueSemaphoreTakeImpl + MPU_xQueueSemaphoreTake_Unpriv: + svc #SYSTEM_CALL_xQueueSemaphoreTake +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGetMutexHolder +MPU_xQueueGetMutexHolder: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGetMutexHolder_Unpriv + MPU_xQueueGetMutexHolder_Priv: + b MPU_xQueueGetMutexHolderImpl + MPU_xQueueGetMutexHolder_Unpriv: + svc #SYSTEM_CALL_xQueueGetMutexHolder +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueTakeMutexRecursive +MPU_xQueueTakeMutexRecursive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueTakeMutexRecursive_Unpriv + MPU_xQueueTakeMutexRecursive_Priv: + b MPU_xQueueTakeMutexRecursiveImpl + MPU_xQueueTakeMutexRecursive_Unpriv: + svc #SYSTEM_CALL_xQueueTakeMutexRecursive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGiveMutexRecursive +MPU_xQueueGiveMutexRecursive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGiveMutexRecursive_Unpriv + MPU_xQueueGiveMutexRecursive_Priv: + b MPU_xQueueGiveMutexRecursiveImpl + MPU_xQueueGiveMutexRecursive_Unpriv: + svc #SYSTEM_CALL_xQueueGiveMutexRecursive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueSelectFromSet +MPU_xQueueSelectFromSet: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueSelectFromSet_Unpriv + MPU_xQueueSelectFromSet_Priv: + b MPU_xQueueSelectFromSetImpl + MPU_xQueueSelectFromSet_Unpriv: + svc #SYSTEM_CALL_xQueueSelectFromSet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueAddToSet +MPU_xQueueAddToSet: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueAddToSet_Unpriv + MPU_xQueueAddToSet_Priv: + b MPU_xQueueAddToSetImpl + MPU_xQueueAddToSet_Unpriv: + svc #SYSTEM_CALL_xQueueAddToSet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vQueueAddToRegistry +MPU_vQueueAddToRegistry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vQueueAddToRegistry_Unpriv + MPU_vQueueAddToRegistry_Priv: + b MPU_vQueueAddToRegistryImpl + MPU_vQueueAddToRegistry_Unpriv: + svc #SYSTEM_CALL_vQueueAddToRegistry +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vQueueUnregisterQueue +MPU_vQueueUnregisterQueue: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vQueueUnregisterQueue_Unpriv + MPU_vQueueUnregisterQueue_Priv: + b MPU_vQueueUnregisterQueueImpl + MPU_vQueueUnregisterQueue_Unpriv: + svc #SYSTEM_CALL_vQueueUnregisterQueue +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pcQueueGetName +MPU_pcQueueGetName: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pcQueueGetName_Unpriv + MPU_pcQueueGetName_Priv: + b MPU_pcQueueGetNameImpl + MPU_pcQueueGetName_Unpriv: + svc #SYSTEM_CALL_pcQueueGetName +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pvTimerGetTimerID +MPU_pvTimerGetTimerID: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pvTimerGetTimerID_Unpriv + MPU_pvTimerGetTimerID_Priv: + b MPU_pvTimerGetTimerIDImpl + MPU_pvTimerGetTimerID_Unpriv: + svc #SYSTEM_CALL_pvTimerGetTimerID +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTimerSetTimerID +MPU_vTimerSetTimerID: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTimerSetTimerID_Unpriv + MPU_vTimerSetTimerID_Priv: + b MPU_vTimerSetTimerIDImpl + MPU_vTimerSetTimerID_Unpriv: + svc #SYSTEM_CALL_vTimerSetTimerID +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerIsTimerActive +MPU_xTimerIsTimerActive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerIsTimerActive_Unpriv + MPU_xTimerIsTimerActive_Priv: + b MPU_xTimerIsTimerActiveImpl + MPU_xTimerIsTimerActive_Unpriv: + svc #SYSTEM_CALL_xTimerIsTimerActive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetTimerDaemonTaskHandle +MPU_xTimerGetTimerDaemonTaskHandle: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv + MPU_xTimerGetTimerDaemonTaskHandle_Priv: + b MPU_xTimerGetTimerDaemonTaskHandleImpl + MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGenericCommandFromTaskEntry +MPU_xTimerGenericCommandFromTaskEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGenericCommandFromTask_Unpriv + MPU_xTimerGenericCommandFromTask_Priv: + b MPU_xTimerGenericCommandFromTaskImpl + MPU_xTimerGenericCommandFromTask_Unpriv: + svc #SYSTEM_CALL_xTimerGenericCommandFromTask +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pcTimerGetName +MPU_pcTimerGetName: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pcTimerGetName_Unpriv + MPU_pcTimerGetName_Priv: + b MPU_pcTimerGetNameImpl + MPU_pcTimerGetName_Unpriv: + svc #SYSTEM_CALL_pcTimerGetName +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTimerSetReloadMode +MPU_vTimerSetReloadMode: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTimerSetReloadMode_Unpriv + MPU_vTimerSetReloadMode_Priv: + b MPU_vTimerSetReloadModeImpl + MPU_vTimerSetReloadMode_Unpriv: + svc #SYSTEM_CALL_vTimerSetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetReloadMode +MPU_xTimerGetReloadMode: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetReloadMode_Unpriv + MPU_xTimerGetReloadMode_Priv: + b MPU_xTimerGetReloadModeImpl + MPU_xTimerGetReloadMode_Unpriv: + svc #SYSTEM_CALL_xTimerGetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTimerGetReloadMode +MPU_uxTimerGetReloadMode: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTimerGetReloadMode_Unpriv + MPU_uxTimerGetReloadMode_Priv: + b MPU_uxTimerGetReloadModeImpl + MPU_uxTimerGetReloadMode_Unpriv: + svc #SYSTEM_CALL_uxTimerGetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetPeriod +MPU_xTimerGetPeriod: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetPeriod_Unpriv + MPU_xTimerGetPeriod_Priv: + b MPU_xTimerGetPeriodImpl + MPU_xTimerGetPeriod_Unpriv: + svc #SYSTEM_CALL_xTimerGetPeriod +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetExpiryTime +MPU_xTimerGetExpiryTime: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetExpiryTime_Unpriv + MPU_xTimerGetExpiryTime_Priv: + b MPU_xTimerGetExpiryTimeImpl + MPU_xTimerGetExpiryTime_Unpriv: + svc #SYSTEM_CALL_xTimerGetExpiryTime +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupWaitBitsEntry +MPU_xEventGroupWaitBitsEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupWaitBits_Unpriv + MPU_xEventGroupWaitBits_Priv: + b MPU_xEventGroupWaitBitsImpl + MPU_xEventGroupWaitBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupWaitBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupClearBits +MPU_xEventGroupClearBits: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupClearBits_Unpriv + MPU_xEventGroupClearBits_Priv: + b MPU_xEventGroupClearBitsImpl + MPU_xEventGroupClearBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupClearBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupSetBits +MPU_xEventGroupSetBits: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupSetBits_Unpriv + MPU_xEventGroupSetBits_Priv: + b MPU_xEventGroupSetBitsImpl + MPU_xEventGroupSetBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupSetBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupSync +MPU_xEventGroupSync: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupSync_Unpriv + MPU_xEventGroupSync_Priv: + b MPU_xEventGroupSyncImpl + MPU_xEventGroupSync_Unpriv: + svc #SYSTEM_CALL_xEventGroupSync +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxEventGroupGetNumber +MPU_uxEventGroupGetNumber: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxEventGroupGetNumber_Unpriv + MPU_uxEventGroupGetNumber_Priv: + b MPU_uxEventGroupGetNumberImpl + MPU_uxEventGroupGetNumber_Unpriv: + svc #SYSTEM_CALL_uxEventGroupGetNumber +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vEventGroupSetNumber +MPU_vEventGroupSetNumber: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vEventGroupSetNumber_Unpriv + MPU_vEventGroupSetNumber_Priv: + b MPU_vEventGroupSetNumberImpl + MPU_vEventGroupSetNumber_Unpriv: + svc #SYSTEM_CALL_vEventGroupSetNumber +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSend +MPU_xStreamBufferSend: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSend_Unpriv + MPU_xStreamBufferSend_Priv: + b MPU_xStreamBufferSendImpl + MPU_xStreamBufferSend_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferReceive +MPU_xStreamBufferReceive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferReceive_Unpriv + MPU_xStreamBufferReceive_Priv: + b MPU_xStreamBufferReceiveImpl + MPU_xStreamBufferReceive_Unpriv: + svc #SYSTEM_CALL_xStreamBufferReceive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferIsFull +MPU_xStreamBufferIsFull: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferIsFull_Unpriv + MPU_xStreamBufferIsFull_Priv: + b MPU_xStreamBufferIsFullImpl + MPU_xStreamBufferIsFull_Unpriv: + svc #SYSTEM_CALL_xStreamBufferIsFull +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferIsEmpty +MPU_xStreamBufferIsEmpty: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferIsEmpty_Unpriv + MPU_xStreamBufferIsEmpty_Priv: + b MPU_xStreamBufferIsEmptyImpl + MPU_xStreamBufferIsEmpty_Unpriv: + svc #SYSTEM_CALL_xStreamBufferIsEmpty +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSpacesAvailable +MPU_xStreamBufferSpacesAvailable: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSpacesAvailable_Unpriv + MPU_xStreamBufferSpacesAvailable_Priv: + b MPU_xStreamBufferSpacesAvailableImpl + MPU_xStreamBufferSpacesAvailable_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSpacesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferBytesAvailable +MPU_xStreamBufferBytesAvailable: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferBytesAvailable_Unpriv + MPU_xStreamBufferBytesAvailable_Priv: + b MPU_xStreamBufferBytesAvailableImpl + MPU_xStreamBufferBytesAvailable_Unpriv: + svc #SYSTEM_CALL_xStreamBufferBytesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSetTriggerLevel +MPU_xStreamBufferSetTriggerLevel: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSetTriggerLevel_Unpriv + MPU_xStreamBufferSetTriggerLevel_Priv: + b MPU_xStreamBufferSetTriggerLevelImpl + MPU_xStreamBufferSetTriggerLevel_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferNextMessageLengthBytes +MPU_xStreamBufferNextMessageLengthBytes: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv + MPU_xStreamBufferNextMessageLengthBytes_Priv: + b MPU_xStreamBufferNextMessageLengthBytesImpl + MPU_xStreamBufferNextMessageLengthBytes_Unpriv: + svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes +/*-----------------------------------------------------------*/ + +/* Default weak implementations in case one is not available from + * mpu_wrappers because of config options. */ + + PUBWEAK MPU_xTaskDelayUntilImpl +MPU_xTaskDelayUntilImpl: + b MPU_xTaskDelayUntilImpl + + PUBWEAK MPU_xTaskAbortDelayImpl +MPU_xTaskAbortDelayImpl: + b MPU_xTaskAbortDelayImpl + + PUBWEAK MPU_vTaskDelayImpl +MPU_vTaskDelayImpl: + b MPU_vTaskDelayImpl + + PUBWEAK MPU_uxTaskPriorityGetImpl +MPU_uxTaskPriorityGetImpl: + b MPU_uxTaskPriorityGetImpl + + PUBWEAK MPU_eTaskGetStateImpl +MPU_eTaskGetStateImpl: + b MPU_eTaskGetStateImpl + + PUBWEAK MPU_vTaskGetInfoImpl +MPU_vTaskGetInfoImpl: + b MPU_vTaskGetInfoImpl + + PUBWEAK MPU_xTaskGetIdleTaskHandleImpl +MPU_xTaskGetIdleTaskHandleImpl: + b MPU_xTaskGetIdleTaskHandleImpl + + PUBWEAK MPU_vTaskSuspendImpl +MPU_vTaskSuspendImpl: + b MPU_vTaskSuspendImpl + + PUBWEAK MPU_vTaskResumeImpl +MPU_vTaskResumeImpl: + b MPU_vTaskResumeImpl + + PUBWEAK MPU_xTaskGetTickCountImpl +MPU_xTaskGetTickCountImpl: + b MPU_xTaskGetTickCountImpl + + PUBWEAK MPU_uxTaskGetNumberOfTasksImpl +MPU_uxTaskGetNumberOfTasksImpl: + b MPU_uxTaskGetNumberOfTasksImpl + + PUBWEAK MPU_ulTaskGetRunTimeCounterImpl +MPU_ulTaskGetRunTimeCounterImpl: + b MPU_ulTaskGetRunTimeCounterImpl + + PUBWEAK MPU_ulTaskGetRunTimePercentImpl +MPU_ulTaskGetRunTimePercentImpl: + b MPU_ulTaskGetRunTimePercentImpl + + PUBWEAK MPU_ulTaskGetIdleRunTimePercentImpl +MPU_ulTaskGetIdleRunTimePercentImpl: + b MPU_ulTaskGetIdleRunTimePercentImpl + + PUBWEAK MPU_ulTaskGetIdleRunTimeCounterImpl +MPU_ulTaskGetIdleRunTimeCounterImpl: + b MPU_ulTaskGetIdleRunTimeCounterImpl + + PUBWEAK MPU_vTaskSetApplicationTaskTagImpl +MPU_vTaskSetApplicationTaskTagImpl: + b MPU_vTaskSetApplicationTaskTagImpl + + PUBWEAK MPU_xTaskGetApplicationTaskTagImpl +MPU_xTaskGetApplicationTaskTagImpl: + b MPU_xTaskGetApplicationTaskTagImpl + + PUBWEAK MPU_vTaskSetThreadLocalStoragePointerImpl +MPU_vTaskSetThreadLocalStoragePointerImpl: + b MPU_vTaskSetThreadLocalStoragePointerImpl + + PUBWEAK MPU_pvTaskGetThreadLocalStoragePointerImpl +MPU_pvTaskGetThreadLocalStoragePointerImpl: + b MPU_pvTaskGetThreadLocalStoragePointerImpl + + PUBWEAK MPU_uxTaskGetSystemStateImpl +MPU_uxTaskGetSystemStateImpl: + b MPU_uxTaskGetSystemStateImpl + + PUBWEAK MPU_uxTaskGetStackHighWaterMarkImpl +MPU_uxTaskGetStackHighWaterMarkImpl: + b MPU_uxTaskGetStackHighWaterMarkImpl + + PUBWEAK MPU_uxTaskGetStackHighWaterMark2Impl +MPU_uxTaskGetStackHighWaterMark2Impl: + b MPU_uxTaskGetStackHighWaterMark2Impl + + PUBWEAK MPU_xTaskGetCurrentTaskHandleImpl +MPU_xTaskGetCurrentTaskHandleImpl: + b MPU_xTaskGetCurrentTaskHandleImpl + + PUBWEAK MPU_xTaskGetSchedulerStateImpl +MPU_xTaskGetSchedulerStateImpl: + b MPU_xTaskGetSchedulerStateImpl + + PUBWEAK MPU_vTaskSetTimeOutStateImpl +MPU_vTaskSetTimeOutStateImpl: + b MPU_vTaskSetTimeOutStateImpl + + PUBWEAK MPU_xTaskCheckForTimeOutImpl +MPU_xTaskCheckForTimeOutImpl: + b MPU_xTaskCheckForTimeOutImpl + + PUBWEAK MPU_xTaskGenericNotifyImpl +MPU_xTaskGenericNotifyImpl: + b MPU_xTaskGenericNotifyImpl + + PUBWEAK MPU_xTaskGenericNotifyWaitImpl +MPU_xTaskGenericNotifyWaitImpl: + b MPU_xTaskGenericNotifyWaitImpl + + PUBWEAK MPU_ulTaskGenericNotifyTakeImpl +MPU_ulTaskGenericNotifyTakeImpl: + b MPU_ulTaskGenericNotifyTakeImpl + + PUBWEAK MPU_xTaskGenericNotifyStateClearImpl +MPU_xTaskGenericNotifyStateClearImpl: + b MPU_xTaskGenericNotifyStateClearImpl + + PUBWEAK MPU_ulTaskGenericNotifyValueClearImpl +MPU_ulTaskGenericNotifyValueClearImpl: + b MPU_ulTaskGenericNotifyValueClearImpl + + PUBWEAK MPU_xQueueGenericSendImpl +MPU_xQueueGenericSendImpl: + b MPU_xQueueGenericSendImpl + + PUBWEAK MPU_uxQueueMessagesWaitingImpl +MPU_uxQueueMessagesWaitingImpl: + b MPU_uxQueueMessagesWaitingImpl + + PUBWEAK MPU_uxQueueSpacesAvailableImpl +MPU_uxQueueSpacesAvailableImpl: + b MPU_uxQueueSpacesAvailableImpl + + PUBWEAK MPU_xQueueReceiveImpl +MPU_xQueueReceiveImpl: + b MPU_xQueueReceiveImpl + + PUBWEAK MPU_xQueuePeekImpl +MPU_xQueuePeekImpl: + b MPU_xQueuePeekImpl + + PUBWEAK MPU_xQueueSemaphoreTakeImpl +MPU_xQueueSemaphoreTakeImpl: + b MPU_xQueueSemaphoreTakeImpl + + PUBWEAK MPU_xQueueGetMutexHolderImpl +MPU_xQueueGetMutexHolderImpl: + b MPU_xQueueGetMutexHolderImpl + + PUBWEAK MPU_xQueueTakeMutexRecursiveImpl +MPU_xQueueTakeMutexRecursiveImpl: + b MPU_xQueueTakeMutexRecursiveImpl + + PUBWEAK MPU_xQueueGiveMutexRecursiveImpl +MPU_xQueueGiveMutexRecursiveImpl: + b MPU_xQueueGiveMutexRecursiveImpl + + PUBWEAK MPU_xQueueSelectFromSetImpl +MPU_xQueueSelectFromSetImpl: + b MPU_xQueueSelectFromSetImpl + + PUBWEAK MPU_xQueueAddToSetImpl +MPU_xQueueAddToSetImpl: + b MPU_xQueueAddToSetImpl + + PUBWEAK MPU_vQueueAddToRegistryImpl +MPU_vQueueAddToRegistryImpl: + b MPU_vQueueAddToRegistryImpl + + PUBWEAK MPU_vQueueUnregisterQueueImpl +MPU_vQueueUnregisterQueueImpl: + b MPU_vQueueUnregisterQueueImpl + + PUBWEAK MPU_pcQueueGetNameImpl +MPU_pcQueueGetNameImpl: + b MPU_pcQueueGetNameImpl + + PUBWEAK MPU_pvTimerGetTimerIDImpl +MPU_pvTimerGetTimerIDImpl: + b MPU_pvTimerGetTimerIDImpl + + PUBWEAK MPU_vTimerSetTimerIDImpl +MPU_vTimerSetTimerIDImpl: + b MPU_vTimerSetTimerIDImpl + + PUBWEAK MPU_xTimerIsTimerActiveImpl +MPU_xTimerIsTimerActiveImpl: + b MPU_xTimerIsTimerActiveImpl + + PUBWEAK MPU_xTimerGetTimerDaemonTaskHandleImpl +MPU_xTimerGetTimerDaemonTaskHandleImpl: + b MPU_xTimerGetTimerDaemonTaskHandleImpl + + PUBWEAK MPU_xTimerGenericCommandFromTaskImpl +MPU_xTimerGenericCommandFromTaskImpl: + b MPU_xTimerGenericCommandFromTaskImpl + + PUBWEAK MPU_pcTimerGetNameImpl +MPU_pcTimerGetNameImpl: + b MPU_pcTimerGetNameImpl + + PUBWEAK MPU_vTimerSetReloadModeImpl +MPU_vTimerSetReloadModeImpl: + b MPU_vTimerSetReloadModeImpl + + PUBWEAK MPU_xTimerGetReloadModeImpl +MPU_xTimerGetReloadModeImpl: + b MPU_xTimerGetReloadModeImpl + + PUBWEAK MPU_uxTimerGetReloadModeImpl +MPU_uxTimerGetReloadModeImpl: + b MPU_uxTimerGetReloadModeImpl + + PUBWEAK MPU_xTimerGetPeriodImpl +MPU_xTimerGetPeriodImpl: + b MPU_xTimerGetPeriodImpl + + PUBWEAK MPU_xTimerGetExpiryTimeImpl +MPU_xTimerGetExpiryTimeImpl: + b MPU_xTimerGetExpiryTimeImpl + + PUBWEAK MPU_xEventGroupWaitBitsImpl +MPU_xEventGroupWaitBitsImpl: + b MPU_xEventGroupWaitBitsImpl + + PUBWEAK MPU_xEventGroupClearBitsImpl +MPU_xEventGroupClearBitsImpl: + b MPU_xEventGroupClearBitsImpl + + PUBWEAK MPU_xEventGroupSetBitsImpl +MPU_xEventGroupSetBitsImpl: + b MPU_xEventGroupSetBitsImpl + + PUBWEAK MPU_xEventGroupSyncImpl +MPU_xEventGroupSyncImpl: + b MPU_xEventGroupSyncImpl + + PUBWEAK MPU_uxEventGroupGetNumberImpl +MPU_uxEventGroupGetNumberImpl: + b MPU_uxEventGroupGetNumberImpl + + PUBWEAK MPU_vEventGroupSetNumberImpl +MPU_vEventGroupSetNumberImpl: + b MPU_vEventGroupSetNumberImpl + + PUBWEAK MPU_xStreamBufferSendImpl +MPU_xStreamBufferSendImpl: + b MPU_xStreamBufferSendImpl + + PUBWEAK MPU_xStreamBufferReceiveImpl +MPU_xStreamBufferReceiveImpl: + b MPU_xStreamBufferReceiveImpl + + PUBWEAK MPU_xStreamBufferIsFullImpl +MPU_xStreamBufferIsFullImpl: + b MPU_xStreamBufferIsFullImpl + + PUBWEAK MPU_xStreamBufferIsEmptyImpl +MPU_xStreamBufferIsEmptyImpl: + b MPU_xStreamBufferIsEmptyImpl + + PUBWEAK MPU_xStreamBufferSpacesAvailableImpl +MPU_xStreamBufferSpacesAvailableImpl: + b MPU_xStreamBufferSpacesAvailableImpl + + PUBWEAK MPU_xStreamBufferBytesAvailableImpl +MPU_xStreamBufferBytesAvailableImpl: + b MPU_xStreamBufferBytesAvailableImpl + + PUBWEAK MPU_xStreamBufferSetTriggerLevelImpl +MPU_xStreamBufferSetTriggerLevelImpl: + b MPU_xStreamBufferSetTriggerLevelImpl + + PUBWEAK MPU_xStreamBufferNextMessageLengthBytesImpl +MPU_xStreamBufferNextMessageLengthBytesImpl: + b MPU_xStreamBufferNextMessageLengthBytesImpl + +/*-----------------------------------------------------------*/ + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + END diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s new file mode 100644 index 000000000..8d5988819 --- /dev/null +++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s @@ -0,0 +1,543 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" + +/* System call numbers includes. */ +#include "mpu_syscall_numbers.h" + +#ifndef configUSE_MPU_WRAPPERS_V1 + #define configUSE_MPU_WRAPPERS_V1 0 +#endif + + EXTERN pxCurrentTCB + EXTERN xSecureContext + EXTERN vTaskSwitchContext + EXTERN vPortSVCHandler_C + EXTERN SecureContext_SaveContext + EXTERN SecureContext_LoadContext +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + EXTERN vSystemCallEnter + EXTERN vSystemCallExit +#endif + + PUBLIC xIsPrivileged + PUBLIC vResetPrivilege + PUBLIC vPortAllocateSecureContext + PUBLIC vRestoreContextOfFirstTask + PUBLIC vRaisePrivilege + PUBLIC vStartFirstTask + PUBLIC ulSetInterruptMask + PUBLIC vClearInterruptMask + PUBLIC PendSV_Handler + PUBLIC SVC_Handler + PUBLIC vPortFreeSecureContext +/*-----------------------------------------------------------*/ + +/*---------------- Unprivileged Functions -------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION .text:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +xIsPrivileged: + mrs r0, control /* r0 = CONTROL. */ + tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + ite ne + movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vResetPrivilege: + mrs r0, control /* r0 = CONTROL. */ + orr r0, r0, #1 /* r0 = r0 | 1. */ + msr control, r0 /* CONTROL = r0. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vPortAllocateSecureContext: + svc 100 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 100. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +/*----------------- Privileged Functions --------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION privileged_functions:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +vRestoreContextOfFirstTask: + program_mpu_first_task: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r3] /* r0 = pxCurrentTCB. */ + + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + str r2, [r1] /* Disable MPU. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r1, [r2] /* Program MAIR0. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + + movs r3, #4 /* r3 = 4. */ + str r3, [r1] /* Program RNR = 4. */ + ldmia r0!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + #if ( configTOTAL_MPU_REGIONS == 16 ) + movs r3, #8 /* r3 = 8. */ + str r3, [r1] /* Program RNR = 8. */ + ldmia r0!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + movs r3, #12 /* r3 = 12. */ + str r3, [r1] /* Program RNR = 12. */ + ldmia r0!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + orr r2, #1 /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */ + str r2, [r1] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + + restore_context_first_task: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* r1 = pxCurrentTCB.*/ + ldr r2, [r1] /* r2 = Location of saved context in TCB. */ + + restore_special_regs_first_task: + #if ( configENABLE_PAC == 1 ) + ldmdb r2!, {r3-r6} /* Read task's dedicated PAC key from the task's context. */ + msr PAC_KEY_P_0, r3 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_1, r4 + msr PAC_KEY_P_2, r5 + msr PAC_KEY_P_3, r6 + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + ldmdb r2!, {r0, r3-r5, lr} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */ + msr psp, r3 + msr psplim, r4 + msr control, r5 + ldr r4, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + str r0, [r4] /* Restore xSecureContext. */ + + restore_general_regs_first_task: + ldmdb r2!, {r4-r11} /* r4-r11 contain hardware saved context. */ + stmia r3!, {r4-r11} /* Copy the hardware saved context on the task stack. */ + ldmdb r2!, {r4-r11} /* r4-r11 restored. */ + + restore_context_done_first_task: + str r2, [r1] /* Save the location where the context should be saved next as the first member of TCB. */ + mov r0, #0 + msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ + bx lr + +#else /* configENABLE_MPU */ + +vRestoreContextOfFirstTask: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r3, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + +#if ( configENABLE_PAC == 1 ) + ldmia r0!, {r1-r4} /* Read task's dedicated PAC key from stack. */ + msr PAC_KEY_P_3, r1 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_2, r2 + msr PAC_KEY_P_1, r3 + msr PAC_KEY_P_0, r4 + clrm {r1-r4} /* Clear r1-r4. */ +#endif /* configENABLE_PAC */ + + ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */ + ldr r4, =xSecureContext + str r1, [r4] /* Set xSecureContext to this task's value for the same. */ + msr psplim, r2 /* Set this task's PSPLIM value. */ + mrs r1, control /* Obtain current control register value. */ + orrs r1, r1, #2 /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */ + msr control, r1 /* Write back the new control register value. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + mov r0, #0 + msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ + bx r3 /* Finally, branch to EXC_RETURN. */ + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +vRaisePrivilege: + mrs r0, control /* Read the CONTROL register. */ + bic r0, r0, #1 /* Clear the bit 0. */ + msr control, r0 /* Write back the new CONTROL value. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vStartFirstTask: + ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */ + ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */ + ldr r0, [r0] /* The first entry in vector table is stack pointer. */ + msr msp, r0 /* Set the MSP back to the start of the stack. */ + cpsie i /* Globally enable interrupts. */ + cpsie f + dsb + isb + svc 102 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */ +/*-----------------------------------------------------------*/ + +ulSetInterruptMask: + mrs r0, basepri /* r0 = basepri. Return original basepri value. */ + mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r1 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vClearInterruptMask: + msr basepri, r0 /* basepri = ulMask. */ + dsb + isb + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +PendSV_Handler: + ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + ldr r0, [r3] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */ + ldr r2, [r1] /* r2 = Location in TCB where the context should be saved. */ + + cbz r0, save_ns_context /* No secure context to save. */ + save_s_context: + push {r0-r2, lr} + bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r0-r2, lr} + + save_ns_context: + mov r3, lr /* r3 = LR (EXC_RETURN). */ + lsls r3, r3, #25 /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bmi save_special_regs /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + + save_general_regs: + mrs r3, psp + + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + add r3, r3, #0x20 /* Move r3 to location where s0 is saved. */ + tst lr, #0x10 + ittt eq + vstmiaeq r2!, {s16-s31} /* Store s16-s31. */ + vldmiaeq r3, {s0-s16} /* Copy hardware saved FP context into s0-s16. */ + vstmiaeq r2!, {s0-s16} /* Store hardware saved FP context. */ + sub r3, r3, #0x20 /* Set r3 back to the location of hardware saved context. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + + stmia r2!, {r4-r11} /* Store r4-r11. */ + ldmia r3, {r4-r11} /* Copy the hardware saved context into r4-r11. */ + stmia r2!, {r4-r11} /* Store the hardware saved context. */ + + save_special_regs: + mrs r3, psp /* r3 = PSP. */ + mrs r4, psplim /* r4 = PSPLIM. */ + mrs r5, control /* r5 = CONTROL. */ + stmia r2!, {r0, r3-r5, lr} /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ + #if ( configENABLE_PAC == 1 ) + mrs r3, PAC_KEY_P_0 /* Read task's dedicated PAC key from the PAC key registers. */ + mrs r4, PAC_KEY_P_1 + mrs r5, PAC_KEY_P_2 + mrs r6, PAC_KEY_P_3 + stmia r2!, {r3-r6} /* Store the task's dedicated PAC key on the task's context. */ + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + + str r2, [r1] /* Save the location from where the context should be restored as the first member of TCB. */ + + select_next_task: + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bl vTaskSwitchContext + mov r0, #0 /* r0 = 0. */ + msr basepri, r0 /* Enable interrupts. */ + + program_mpu: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r3] /* r0 = pxCurrentTCB.*/ + + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + str r2, [r1] /* Disable MPU. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r1, [r2] /* Program MAIR0. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + + movs r3, #4 /* r3 = 4. */ + str r3, [r1] /* Program RNR = 4. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + #if ( configTOTAL_MPU_REGIONS == 16 ) + movs r3, #8 /* r3 = 8. */ + str r3, [r1] /* Program RNR = 8. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + movs r3, #12 /* r3 = 12. */ + str r3, [r1] /* Program RNR = 12. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + orr r2, #1 /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */ + str r2, [r1] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + + restore_context: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* r1 = pxCurrentTCB.*/ + ldr r2, [r1] /* r2 = Location of saved context in TCB. */ + + restore_special_regs: + #if ( configENABLE_PAC == 1 ) + ldmdb r2!, {r3-r6} /* Read task's dedicated PAC key from the task's context. */ + msr PAC_KEY_P_0, r3 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_1, r4 + msr PAC_KEY_P_2, r5 + msr PAC_KEY_P_3, r6 + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + ldmdb r2!, {r0, r3-r5, lr} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */ + msr psp, r3 + msr psplim, r4 + msr control, r5 + ldr r4, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + str r0, [r4] /* Restore xSecureContext. */ + cbz r0, restore_ns_context /* No secure context to restore. */ + + restore_s_context: + push {r1-r3, lr} + bl SecureContext_LoadContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r1-r3, lr} + + restore_ns_context: + mov r0, lr /* r0 = LR (EXC_RETURN). */ + lsls r0, r0, #25 /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bmi restore_context_done /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + + restore_general_regs: + ldmdb r2!, {r4-r11} /* r4-r11 contain hardware saved context. */ + stmia r3!, {r4-r11} /* Copy the hardware saved context on the task stack. */ + ldmdb r2!, {r4-r11} /* r4-r11 restored. */ + + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 + ittt eq + vldmdbeq r2!, {s0-s16} /* s0-s16 contain hardware saved FP context. */ + vstmiaeq r3!, {s0-s16} /* Copy hardware saved FP context on the task stack. */ + vldmdbeq r2!, {s16-s31} /* Restore s16-s31. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + + restore_context_done: + str r2, [r1] /* Save the location where the context should be saved next as the first member of TCB. */ + bx lr + +#else /* configENABLE_MPU */ + +PendSV_Handler: + ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + ldr r0, [r3] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */ + mrs r2, psp /* Read PSP in r2. */ + + cbz r0, save_ns_context /* No secure context to save. */ + save_s_context: + push {r0-r2, lr} + bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r0-r2, lr} + + save_ns_context: + mov r3, lr /* r3 = LR. */ + lsls r3, r3, #25 /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bmi save_special_regs /* If r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used. */ + + save_general_regs: + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + it eq + vstmdbeq r2!, {s16-s31} /* Store the additional FP context registers which are not saved automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + stmdb r2!, {r4-r11} /* Store the registers that are not saved automatically. */ + + save_special_regs: + mrs r3, psplim /* r3 = PSPLIM. */ + stmdb r2!, {r0, r3, lr} /* Store xSecureContext, PSPLIM and LR on the stack. */ + #if ( configENABLE_PAC == 1 ) + mrs r3, PAC_KEY_P_3 /* Read task's dedicated PAC key from the PAC key registers. */ + mrs r4, PAC_KEY_P_2 + mrs r5, PAC_KEY_P_1 + mrs r6, PAC_KEY_P_0 + stmdb r2!, {r3-r6} /* Store the task's dedicated PAC key on the stack. */ + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + + str r2, [r1] /* Save the new top of stack in TCB. */ + + select_next_task: + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bl vTaskSwitchContext + mov r0, #0 /* r0 = 0. */ + msr basepri, r0 /* Enable interrupts. */ + + restore_context: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB. */ + ldr r2, [r1] /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */ + + restore_special_regs: + #if ( configENABLE_PAC == 1 ) + ldmia r2!, {r3-r6} /* Read task's dedicated PAC key from stack. */ + msr PAC_KEY_P_3, r3 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_2, r4 + msr PAC_KEY_P_1, r5 + msr PAC_KEY_P_0, r6 + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + ldmia r2!, {r0, r3, lr} http://files.iar.com/ftp/pub/box/bxarm-9.60.3.deb/* Read from stack - r0 = xSecureContext, r3 = PSPLIM and LR restored. */ + msr psplim, r3 /* Restore the PSPLIM register value for the task. */ + ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + str r0, [r3] /* Restore the task's xSecureContext. */ + cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */ + + restore_s_context: + push {r1-r3, lr} + bl SecureContext_LoadContext /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r1-r3, lr} + + restore_ns_context: + mov r0, lr /* r0 = LR (EXC_RETURN). */ + lsls r0, r0, #25 /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bmi restore_context_done /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + + restore_general_regs: + ldmia r2!, {r4-r11} /* Restore the registers that are not automatically restored. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + it eq + vldmiaeq r2!, {s16-s31} /* Restore the additional FP context registers which are not restored automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + + restore_context_done: + msr psp, r2 /* Remember the new top of stack for the task. */ + bx lr + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + +SVC_Handler: + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + + ldr r1, [r0, #24] + ldrb r2, [r1, #-2] + cmp r2, #NUM_SYSTEM_CALLS + blt syscall_enter + cmp r2, #104 /* portSVC_SYSTEM_CALL_EXIT. */ + beq syscall_exit + b vPortSVCHandler_C + + syscall_enter: + mov r1, lr + b vSystemCallEnter + + syscall_exit: + mov r1, lr + b vSystemCallExit + +#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +SVC_Handler: + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + b vPortSVCHandler_C + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +vPortFreeSecureContext: + /* r0 = uint32_t *pulTCB. */ + ldr r2, [r0] /* The first item in the TCB is the top of the stack. */ + ldr r1, [r2] /* The first item on the stack is the task's xSecureContext. */ + cmp r1, #0 /* Raise svc if task's xSecureContext is not NULL. */ + it ne + svcne 101 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 101. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + + END diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h new file mode 100644 index 000000000..53b668b5b --- /dev/null +++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h @@ -0,0 +1,88 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M33" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portARMV8M_MINOR_VERSION 0 +#define portDONT_DISCARD __root +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +#ifndef configENABLE_MVE + #define configENABLE_MVE 0 +#elif ( configENABLE_MVE != 0 ) + #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M33. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ +#pragma diag_suppress=Be006 +#pragma diag_suppress=Pa082 +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/mpu_wrappers_v2_asm.S b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/mpu_wrappers_v2_asm.S new file mode 100644 index 000000000..d2cb78e92 --- /dev/null +++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/mpu_wrappers_v2_asm.S @@ -0,0 +1,1242 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + + SECTION freertos_system_calls:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +#include "FreeRTOSConfig.h" +#include "mpu_syscall_numbers.h" + +#ifndef configUSE_MPU_WRAPPERS_V1 + #define configUSE_MPU_WRAPPERS_V1 0 +#endif + +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + PUBLIC MPU_xTaskDelayUntil +MPU_xTaskDelayUntil: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskDelayUntil_Unpriv + MPU_xTaskDelayUntil_Priv: + b MPU_xTaskDelayUntilImpl + MPU_xTaskDelayUntil_Unpriv: + svc #SYSTEM_CALL_xTaskDelayUntil +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskAbortDelay +MPU_xTaskAbortDelay: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskAbortDelay_Unpriv + MPU_xTaskAbortDelay_Priv: + b MPU_xTaskAbortDelayImpl + MPU_xTaskAbortDelay_Unpriv: + svc #SYSTEM_CALL_xTaskAbortDelay +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskDelay +MPU_vTaskDelay: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskDelay_Unpriv + MPU_vTaskDelay_Priv: + b MPU_vTaskDelayImpl + MPU_vTaskDelay_Unpriv: + svc #SYSTEM_CALL_vTaskDelay +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskPriorityGet +MPU_uxTaskPriorityGet: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskPriorityGet_Unpriv + MPU_uxTaskPriorityGet_Priv: + b MPU_uxTaskPriorityGetImpl + MPU_uxTaskPriorityGet_Unpriv: + svc #SYSTEM_CALL_uxTaskPriorityGet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_eTaskGetState +MPU_eTaskGetState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_eTaskGetState_Unpriv + MPU_eTaskGetState_Priv: + b MPU_eTaskGetStateImpl + MPU_eTaskGetState_Unpriv: + svc #SYSTEM_CALL_eTaskGetState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskGetInfo +MPU_vTaskGetInfo: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskGetInfo_Unpriv + MPU_vTaskGetInfo_Priv: + b MPU_vTaskGetInfoImpl + MPU_vTaskGetInfo_Unpriv: + svc #SYSTEM_CALL_vTaskGetInfo +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetIdleTaskHandle +MPU_xTaskGetIdleTaskHandle: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetIdleTaskHandle_Unpriv + MPU_xTaskGetIdleTaskHandle_Priv: + b MPU_xTaskGetIdleTaskHandleImpl + MPU_xTaskGetIdleTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTaskGetIdleTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSuspend +MPU_vTaskSuspend: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSuspend_Unpriv + MPU_vTaskSuspend_Priv: + b MPU_vTaskSuspendImpl + MPU_vTaskSuspend_Unpriv: + svc #SYSTEM_CALL_vTaskSuspend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskResume +MPU_vTaskResume: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskResume_Unpriv + MPU_vTaskResume_Priv: + b MPU_vTaskResumeImpl + MPU_vTaskResume_Unpriv: + svc #SYSTEM_CALL_vTaskResume +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetTickCount +MPU_xTaskGetTickCount: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetTickCount_Unpriv + MPU_xTaskGetTickCount_Priv: + b MPU_xTaskGetTickCountImpl + MPU_xTaskGetTickCount_Unpriv: + svc #SYSTEM_CALL_xTaskGetTickCount +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetNumberOfTasks +MPU_uxTaskGetNumberOfTasks: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetNumberOfTasks_Unpriv + MPU_uxTaskGetNumberOfTasks_Priv: + b MPU_uxTaskGetNumberOfTasksImpl + MPU_uxTaskGetNumberOfTasks_Unpriv: + svc #SYSTEM_CALL_uxTaskGetNumberOfTasks +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetRunTimeCounter +MPU_ulTaskGetRunTimeCounter: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetRunTimeCounter_Unpriv + MPU_ulTaskGetRunTimeCounter_Priv: + b MPU_ulTaskGetRunTimeCounterImpl + MPU_ulTaskGetRunTimeCounter_Unpriv: + svc #SYSTEM_CALL_ulTaskGetRunTimeCounter +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetRunTimePercent +MPU_ulTaskGetRunTimePercent: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetRunTimePercent_Unpriv + MPU_ulTaskGetRunTimePercent_Priv: + b MPU_ulTaskGetRunTimePercentImpl + MPU_ulTaskGetRunTimePercent_Unpriv: + svc #SYSTEM_CALL_ulTaskGetRunTimePercent +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetIdleRunTimePercent +MPU_ulTaskGetIdleRunTimePercent: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetIdleRunTimePercent_Unpriv + MPU_ulTaskGetIdleRunTimePercent_Priv: + b MPU_ulTaskGetIdleRunTimePercentImpl + MPU_ulTaskGetIdleRunTimePercent_Unpriv: + svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetIdleRunTimeCounter +MPU_ulTaskGetIdleRunTimeCounter: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv + MPU_ulTaskGetIdleRunTimeCounter_Priv: + b MPU_ulTaskGetIdleRunTimeCounterImpl + MPU_ulTaskGetIdleRunTimeCounter_Unpriv: + svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetApplicationTaskTag +MPU_vTaskSetApplicationTaskTag: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetApplicationTaskTag_Unpriv + MPU_vTaskSetApplicationTaskTag_Priv: + b MPU_vTaskSetApplicationTaskTagImpl + MPU_vTaskSetApplicationTaskTag_Unpriv: + svc #SYSTEM_CALL_vTaskSetApplicationTaskTag +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetApplicationTaskTag +MPU_xTaskGetApplicationTaskTag: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetApplicationTaskTag_Unpriv + MPU_xTaskGetApplicationTaskTag_Priv: + b MPU_xTaskGetApplicationTaskTagImpl + MPU_xTaskGetApplicationTaskTag_Unpriv: + svc #SYSTEM_CALL_xTaskGetApplicationTaskTag +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetThreadLocalStoragePointer +MPU_vTaskSetThreadLocalStoragePointer: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv + MPU_vTaskSetThreadLocalStoragePointer_Priv: + b MPU_vTaskSetThreadLocalStoragePointerImpl + MPU_vTaskSetThreadLocalStoragePointer_Unpriv: + svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pvTaskGetThreadLocalStoragePointer +MPU_pvTaskGetThreadLocalStoragePointer: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv + MPU_pvTaskGetThreadLocalStoragePointer_Priv: + b MPU_pvTaskGetThreadLocalStoragePointerImpl + MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: + svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetSystemState +MPU_uxTaskGetSystemState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetSystemState_Unpriv + MPU_uxTaskGetSystemState_Priv: + b MPU_uxTaskGetSystemStateImpl + MPU_uxTaskGetSystemState_Unpriv: + svc #SYSTEM_CALL_uxTaskGetSystemState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetStackHighWaterMark +MPU_uxTaskGetStackHighWaterMark: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetStackHighWaterMark_Unpriv + MPU_uxTaskGetStackHighWaterMark_Priv: + b MPU_uxTaskGetStackHighWaterMarkImpl + MPU_uxTaskGetStackHighWaterMark_Unpriv: + svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetStackHighWaterMark2 +MPU_uxTaskGetStackHighWaterMark2: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetStackHighWaterMark2_Unpriv + MPU_uxTaskGetStackHighWaterMark2_Priv: + b MPU_uxTaskGetStackHighWaterMark2Impl + MPU_uxTaskGetStackHighWaterMark2_Unpriv: + svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2 +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetCurrentTaskHandle +MPU_xTaskGetCurrentTaskHandle: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetCurrentTaskHandle_Unpriv + MPU_xTaskGetCurrentTaskHandle_Priv: + b MPU_xTaskGetCurrentTaskHandleImpl + MPU_xTaskGetCurrentTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetSchedulerState +MPU_xTaskGetSchedulerState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetSchedulerState_Unpriv + MPU_xTaskGetSchedulerState_Priv: + b MPU_xTaskGetSchedulerStateImpl + MPU_xTaskGetSchedulerState_Unpriv: + svc #SYSTEM_CALL_xTaskGetSchedulerState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetTimeOutState +MPU_vTaskSetTimeOutState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetTimeOutState_Unpriv + MPU_vTaskSetTimeOutState_Priv: + b MPU_vTaskSetTimeOutStateImpl + MPU_vTaskSetTimeOutState_Unpriv: + svc #SYSTEM_CALL_vTaskSetTimeOutState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskCheckForTimeOut +MPU_xTaskCheckForTimeOut: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskCheckForTimeOut_Unpriv + MPU_xTaskCheckForTimeOut_Priv: + b MPU_xTaskCheckForTimeOutImpl + MPU_xTaskCheckForTimeOut_Unpriv: + svc #SYSTEM_CALL_xTaskCheckForTimeOut +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyEntry +MPU_xTaskGenericNotifyEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotify_Unpriv + MPU_xTaskGenericNotify_Priv: + b MPU_xTaskGenericNotifyImpl + MPU_xTaskGenericNotify_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotify +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyWaitEntry +MPU_xTaskGenericNotifyWaitEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotifyWait_Unpriv + MPU_xTaskGenericNotifyWait_Priv: + b MPU_xTaskGenericNotifyWaitImpl + MPU_xTaskGenericNotifyWait_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotifyWait +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGenericNotifyTake +MPU_ulTaskGenericNotifyTake: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGenericNotifyTake_Unpriv + MPU_ulTaskGenericNotifyTake_Priv: + b MPU_ulTaskGenericNotifyTakeImpl + MPU_ulTaskGenericNotifyTake_Unpriv: + svc #SYSTEM_CALL_ulTaskGenericNotifyTake +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyStateClear +MPU_xTaskGenericNotifyStateClear: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotifyStateClear_Unpriv + MPU_xTaskGenericNotifyStateClear_Priv: + b MPU_xTaskGenericNotifyStateClearImpl + MPU_xTaskGenericNotifyStateClear_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotifyStateClear +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGenericNotifyValueClear +MPU_ulTaskGenericNotifyValueClear: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGenericNotifyValueClear_Unpriv + MPU_ulTaskGenericNotifyValueClear_Priv: + b MPU_ulTaskGenericNotifyValueClearImpl + MPU_ulTaskGenericNotifyValueClear_Unpriv: + svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGenericSend +MPU_xQueueGenericSend: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGenericSend_Unpriv + MPU_xQueueGenericSend_Priv: + b MPU_xQueueGenericSendImpl + MPU_xQueueGenericSend_Unpriv: + svc #SYSTEM_CALL_xQueueGenericSend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxQueueMessagesWaiting +MPU_uxQueueMessagesWaiting: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxQueueMessagesWaiting_Unpriv + MPU_uxQueueMessagesWaiting_Priv: + b MPU_uxQueueMessagesWaitingImpl + MPU_uxQueueMessagesWaiting_Unpriv: + svc #SYSTEM_CALL_uxQueueMessagesWaiting +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxQueueSpacesAvailable +MPU_uxQueueSpacesAvailable: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxQueueSpacesAvailable_Unpriv + MPU_uxQueueSpacesAvailable_Priv: + b MPU_uxQueueSpacesAvailableImpl + MPU_uxQueueSpacesAvailable_Unpriv: + svc #SYSTEM_CALL_uxQueueSpacesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueReceive +MPU_xQueueReceive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueReceive_Unpriv + MPU_xQueueReceive_Priv: + b MPU_xQueueReceiveImpl + MPU_xQueueReceive_Unpriv: + svc #SYSTEM_CALL_xQueueReceive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueuePeek +MPU_xQueuePeek: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueuePeek_Unpriv + MPU_xQueuePeek_Priv: + b MPU_xQueuePeekImpl + MPU_xQueuePeek_Unpriv: + svc #SYSTEM_CALL_xQueuePeek +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueSemaphoreTake +MPU_xQueueSemaphoreTake: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueSemaphoreTake_Unpriv + MPU_xQueueSemaphoreTake_Priv: + b MPU_xQueueSemaphoreTakeImpl + MPU_xQueueSemaphoreTake_Unpriv: + svc #SYSTEM_CALL_xQueueSemaphoreTake +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGetMutexHolder +MPU_xQueueGetMutexHolder: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGetMutexHolder_Unpriv + MPU_xQueueGetMutexHolder_Priv: + b MPU_xQueueGetMutexHolderImpl + MPU_xQueueGetMutexHolder_Unpriv: + svc #SYSTEM_CALL_xQueueGetMutexHolder +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueTakeMutexRecursive +MPU_xQueueTakeMutexRecursive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueTakeMutexRecursive_Unpriv + MPU_xQueueTakeMutexRecursive_Priv: + b MPU_xQueueTakeMutexRecursiveImpl + MPU_xQueueTakeMutexRecursive_Unpriv: + svc #SYSTEM_CALL_xQueueTakeMutexRecursive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGiveMutexRecursive +MPU_xQueueGiveMutexRecursive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGiveMutexRecursive_Unpriv + MPU_xQueueGiveMutexRecursive_Priv: + b MPU_xQueueGiveMutexRecursiveImpl + MPU_xQueueGiveMutexRecursive_Unpriv: + svc #SYSTEM_CALL_xQueueGiveMutexRecursive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueSelectFromSet +MPU_xQueueSelectFromSet: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueSelectFromSet_Unpriv + MPU_xQueueSelectFromSet_Priv: + b MPU_xQueueSelectFromSetImpl + MPU_xQueueSelectFromSet_Unpriv: + svc #SYSTEM_CALL_xQueueSelectFromSet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueAddToSet +MPU_xQueueAddToSet: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueAddToSet_Unpriv + MPU_xQueueAddToSet_Priv: + b MPU_xQueueAddToSetImpl + MPU_xQueueAddToSet_Unpriv: + svc #SYSTEM_CALL_xQueueAddToSet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vQueueAddToRegistry +MPU_vQueueAddToRegistry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vQueueAddToRegistry_Unpriv + MPU_vQueueAddToRegistry_Priv: + b MPU_vQueueAddToRegistryImpl + MPU_vQueueAddToRegistry_Unpriv: + svc #SYSTEM_CALL_vQueueAddToRegistry +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vQueueUnregisterQueue +MPU_vQueueUnregisterQueue: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vQueueUnregisterQueue_Unpriv + MPU_vQueueUnregisterQueue_Priv: + b MPU_vQueueUnregisterQueueImpl + MPU_vQueueUnregisterQueue_Unpriv: + svc #SYSTEM_CALL_vQueueUnregisterQueue +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pcQueueGetName +MPU_pcQueueGetName: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pcQueueGetName_Unpriv + MPU_pcQueueGetName_Priv: + b MPU_pcQueueGetNameImpl + MPU_pcQueueGetName_Unpriv: + svc #SYSTEM_CALL_pcQueueGetName +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pvTimerGetTimerID +MPU_pvTimerGetTimerID: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pvTimerGetTimerID_Unpriv + MPU_pvTimerGetTimerID_Priv: + b MPU_pvTimerGetTimerIDImpl + MPU_pvTimerGetTimerID_Unpriv: + svc #SYSTEM_CALL_pvTimerGetTimerID +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTimerSetTimerID +MPU_vTimerSetTimerID: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTimerSetTimerID_Unpriv + MPU_vTimerSetTimerID_Priv: + b MPU_vTimerSetTimerIDImpl + MPU_vTimerSetTimerID_Unpriv: + svc #SYSTEM_CALL_vTimerSetTimerID +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerIsTimerActive +MPU_xTimerIsTimerActive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerIsTimerActive_Unpriv + MPU_xTimerIsTimerActive_Priv: + b MPU_xTimerIsTimerActiveImpl + MPU_xTimerIsTimerActive_Unpriv: + svc #SYSTEM_CALL_xTimerIsTimerActive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetTimerDaemonTaskHandle +MPU_xTimerGetTimerDaemonTaskHandle: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv + MPU_xTimerGetTimerDaemonTaskHandle_Priv: + b MPU_xTimerGetTimerDaemonTaskHandleImpl + MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGenericCommandFromTaskEntry +MPU_xTimerGenericCommandFromTaskEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGenericCommandFromTask_Unpriv + MPU_xTimerGenericCommandFromTask_Priv: + b MPU_xTimerGenericCommandFromTaskImpl + MPU_xTimerGenericCommandFromTask_Unpriv: + svc #SYSTEM_CALL_xTimerGenericCommandFromTask +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pcTimerGetName +MPU_pcTimerGetName: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pcTimerGetName_Unpriv + MPU_pcTimerGetName_Priv: + b MPU_pcTimerGetNameImpl + MPU_pcTimerGetName_Unpriv: + svc #SYSTEM_CALL_pcTimerGetName +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTimerSetReloadMode +MPU_vTimerSetReloadMode: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTimerSetReloadMode_Unpriv + MPU_vTimerSetReloadMode_Priv: + b MPU_vTimerSetReloadModeImpl + MPU_vTimerSetReloadMode_Unpriv: + svc #SYSTEM_CALL_vTimerSetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetReloadMode +MPU_xTimerGetReloadMode: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetReloadMode_Unpriv + MPU_xTimerGetReloadMode_Priv: + b MPU_xTimerGetReloadModeImpl + MPU_xTimerGetReloadMode_Unpriv: + svc #SYSTEM_CALL_xTimerGetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTimerGetReloadMode +MPU_uxTimerGetReloadMode: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTimerGetReloadMode_Unpriv + MPU_uxTimerGetReloadMode_Priv: + b MPU_uxTimerGetReloadModeImpl + MPU_uxTimerGetReloadMode_Unpriv: + svc #SYSTEM_CALL_uxTimerGetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetPeriod +MPU_xTimerGetPeriod: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetPeriod_Unpriv + MPU_xTimerGetPeriod_Priv: + b MPU_xTimerGetPeriodImpl + MPU_xTimerGetPeriod_Unpriv: + svc #SYSTEM_CALL_xTimerGetPeriod +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetExpiryTime +MPU_xTimerGetExpiryTime: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetExpiryTime_Unpriv + MPU_xTimerGetExpiryTime_Priv: + b MPU_xTimerGetExpiryTimeImpl + MPU_xTimerGetExpiryTime_Unpriv: + svc #SYSTEM_CALL_xTimerGetExpiryTime +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupWaitBitsEntry +MPU_xEventGroupWaitBitsEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupWaitBits_Unpriv + MPU_xEventGroupWaitBits_Priv: + b MPU_xEventGroupWaitBitsImpl + MPU_xEventGroupWaitBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupWaitBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupClearBits +MPU_xEventGroupClearBits: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupClearBits_Unpriv + MPU_xEventGroupClearBits_Priv: + b MPU_xEventGroupClearBitsImpl + MPU_xEventGroupClearBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupClearBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupSetBits +MPU_xEventGroupSetBits: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupSetBits_Unpriv + MPU_xEventGroupSetBits_Priv: + b MPU_xEventGroupSetBitsImpl + MPU_xEventGroupSetBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupSetBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupSync +MPU_xEventGroupSync: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupSync_Unpriv + MPU_xEventGroupSync_Priv: + b MPU_xEventGroupSyncImpl + MPU_xEventGroupSync_Unpriv: + svc #SYSTEM_CALL_xEventGroupSync +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxEventGroupGetNumber +MPU_uxEventGroupGetNumber: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxEventGroupGetNumber_Unpriv + MPU_uxEventGroupGetNumber_Priv: + b MPU_uxEventGroupGetNumberImpl + MPU_uxEventGroupGetNumber_Unpriv: + svc #SYSTEM_CALL_uxEventGroupGetNumber +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vEventGroupSetNumber +MPU_vEventGroupSetNumber: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vEventGroupSetNumber_Unpriv + MPU_vEventGroupSetNumber_Priv: + b MPU_vEventGroupSetNumberImpl + MPU_vEventGroupSetNumber_Unpriv: + svc #SYSTEM_CALL_vEventGroupSetNumber +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSend +MPU_xStreamBufferSend: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSend_Unpriv + MPU_xStreamBufferSend_Priv: + b MPU_xStreamBufferSendImpl + MPU_xStreamBufferSend_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferReceive +MPU_xStreamBufferReceive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferReceive_Unpriv + MPU_xStreamBufferReceive_Priv: + b MPU_xStreamBufferReceiveImpl + MPU_xStreamBufferReceive_Unpriv: + svc #SYSTEM_CALL_xStreamBufferReceive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferIsFull +MPU_xStreamBufferIsFull: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferIsFull_Unpriv + MPU_xStreamBufferIsFull_Priv: + b MPU_xStreamBufferIsFullImpl + MPU_xStreamBufferIsFull_Unpriv: + svc #SYSTEM_CALL_xStreamBufferIsFull +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferIsEmpty +MPU_xStreamBufferIsEmpty: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferIsEmpty_Unpriv + MPU_xStreamBufferIsEmpty_Priv: + b MPU_xStreamBufferIsEmptyImpl + MPU_xStreamBufferIsEmpty_Unpriv: + svc #SYSTEM_CALL_xStreamBufferIsEmpty +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSpacesAvailable +MPU_xStreamBufferSpacesAvailable: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSpacesAvailable_Unpriv + MPU_xStreamBufferSpacesAvailable_Priv: + b MPU_xStreamBufferSpacesAvailableImpl + MPU_xStreamBufferSpacesAvailable_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSpacesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferBytesAvailable +MPU_xStreamBufferBytesAvailable: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferBytesAvailable_Unpriv + MPU_xStreamBufferBytesAvailable_Priv: + b MPU_xStreamBufferBytesAvailableImpl + MPU_xStreamBufferBytesAvailable_Unpriv: + svc #SYSTEM_CALL_xStreamBufferBytesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSetTriggerLevel +MPU_xStreamBufferSetTriggerLevel: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSetTriggerLevel_Unpriv + MPU_xStreamBufferSetTriggerLevel_Priv: + b MPU_xStreamBufferSetTriggerLevelImpl + MPU_xStreamBufferSetTriggerLevel_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferNextMessageLengthBytes +MPU_xStreamBufferNextMessageLengthBytes: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv + MPU_xStreamBufferNextMessageLengthBytes_Priv: + b MPU_xStreamBufferNextMessageLengthBytesImpl + MPU_xStreamBufferNextMessageLengthBytes_Unpriv: + svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes +/*-----------------------------------------------------------*/ + +/* Default weak implementations in case one is not available from + * mpu_wrappers because of config options. */ + + PUBWEAK MPU_xTaskDelayUntilImpl +MPU_xTaskDelayUntilImpl: + b MPU_xTaskDelayUntilImpl + + PUBWEAK MPU_xTaskAbortDelayImpl +MPU_xTaskAbortDelayImpl: + b MPU_xTaskAbortDelayImpl + + PUBWEAK MPU_vTaskDelayImpl +MPU_vTaskDelayImpl: + b MPU_vTaskDelayImpl + + PUBWEAK MPU_uxTaskPriorityGetImpl +MPU_uxTaskPriorityGetImpl: + b MPU_uxTaskPriorityGetImpl + + PUBWEAK MPU_eTaskGetStateImpl +MPU_eTaskGetStateImpl: + b MPU_eTaskGetStateImpl + + PUBWEAK MPU_vTaskGetInfoImpl +MPU_vTaskGetInfoImpl: + b MPU_vTaskGetInfoImpl + + PUBWEAK MPU_xTaskGetIdleTaskHandleImpl +MPU_xTaskGetIdleTaskHandleImpl: + b MPU_xTaskGetIdleTaskHandleImpl + + PUBWEAK MPU_vTaskSuspendImpl +MPU_vTaskSuspendImpl: + b MPU_vTaskSuspendImpl + + PUBWEAK MPU_vTaskResumeImpl +MPU_vTaskResumeImpl: + b MPU_vTaskResumeImpl + + PUBWEAK MPU_xTaskGetTickCountImpl +MPU_xTaskGetTickCountImpl: + b MPU_xTaskGetTickCountImpl + + PUBWEAK MPU_uxTaskGetNumberOfTasksImpl +MPU_uxTaskGetNumberOfTasksImpl: + b MPU_uxTaskGetNumberOfTasksImpl + + PUBWEAK MPU_ulTaskGetRunTimeCounterImpl +MPU_ulTaskGetRunTimeCounterImpl: + b MPU_ulTaskGetRunTimeCounterImpl + + PUBWEAK MPU_ulTaskGetRunTimePercentImpl +MPU_ulTaskGetRunTimePercentImpl: + b MPU_ulTaskGetRunTimePercentImpl + + PUBWEAK MPU_ulTaskGetIdleRunTimePercentImpl +MPU_ulTaskGetIdleRunTimePercentImpl: + b MPU_ulTaskGetIdleRunTimePercentImpl + + PUBWEAK MPU_ulTaskGetIdleRunTimeCounterImpl +MPU_ulTaskGetIdleRunTimeCounterImpl: + b MPU_ulTaskGetIdleRunTimeCounterImpl + + PUBWEAK MPU_vTaskSetApplicationTaskTagImpl +MPU_vTaskSetApplicationTaskTagImpl: + b MPU_vTaskSetApplicationTaskTagImpl + + PUBWEAK MPU_xTaskGetApplicationTaskTagImpl +MPU_xTaskGetApplicationTaskTagImpl: + b MPU_xTaskGetApplicationTaskTagImpl + + PUBWEAK MPU_vTaskSetThreadLocalStoragePointerImpl +MPU_vTaskSetThreadLocalStoragePointerImpl: + b MPU_vTaskSetThreadLocalStoragePointerImpl + + PUBWEAK MPU_pvTaskGetThreadLocalStoragePointerImpl +MPU_pvTaskGetThreadLocalStoragePointerImpl: + b MPU_pvTaskGetThreadLocalStoragePointerImpl + + PUBWEAK MPU_uxTaskGetSystemStateImpl +MPU_uxTaskGetSystemStateImpl: + b MPU_uxTaskGetSystemStateImpl + + PUBWEAK MPU_uxTaskGetStackHighWaterMarkImpl +MPU_uxTaskGetStackHighWaterMarkImpl: + b MPU_uxTaskGetStackHighWaterMarkImpl + + PUBWEAK MPU_uxTaskGetStackHighWaterMark2Impl +MPU_uxTaskGetStackHighWaterMark2Impl: + b MPU_uxTaskGetStackHighWaterMark2Impl + + PUBWEAK MPU_xTaskGetCurrentTaskHandleImpl +MPU_xTaskGetCurrentTaskHandleImpl: + b MPU_xTaskGetCurrentTaskHandleImpl + + PUBWEAK MPU_xTaskGetSchedulerStateImpl +MPU_xTaskGetSchedulerStateImpl: + b MPU_xTaskGetSchedulerStateImpl + + PUBWEAK MPU_vTaskSetTimeOutStateImpl +MPU_vTaskSetTimeOutStateImpl: + b MPU_vTaskSetTimeOutStateImpl + + PUBWEAK MPU_xTaskCheckForTimeOutImpl +MPU_xTaskCheckForTimeOutImpl: + b MPU_xTaskCheckForTimeOutImpl + + PUBWEAK MPU_xTaskGenericNotifyImpl +MPU_xTaskGenericNotifyImpl: + b MPU_xTaskGenericNotifyImpl + + PUBWEAK MPU_xTaskGenericNotifyWaitImpl +MPU_xTaskGenericNotifyWaitImpl: + b MPU_xTaskGenericNotifyWaitImpl + + PUBWEAK MPU_ulTaskGenericNotifyTakeImpl +MPU_ulTaskGenericNotifyTakeImpl: + b MPU_ulTaskGenericNotifyTakeImpl + + PUBWEAK MPU_xTaskGenericNotifyStateClearImpl +MPU_xTaskGenericNotifyStateClearImpl: + b MPU_xTaskGenericNotifyStateClearImpl + + PUBWEAK MPU_ulTaskGenericNotifyValueClearImpl +MPU_ulTaskGenericNotifyValueClearImpl: + b MPU_ulTaskGenericNotifyValueClearImpl + + PUBWEAK MPU_xQueueGenericSendImpl +MPU_xQueueGenericSendImpl: + b MPU_xQueueGenericSendImpl + + PUBWEAK MPU_uxQueueMessagesWaitingImpl +MPU_uxQueueMessagesWaitingImpl: + b MPU_uxQueueMessagesWaitingImpl + + PUBWEAK MPU_uxQueueSpacesAvailableImpl +MPU_uxQueueSpacesAvailableImpl: + b MPU_uxQueueSpacesAvailableImpl + + PUBWEAK MPU_xQueueReceiveImpl +MPU_xQueueReceiveImpl: + b MPU_xQueueReceiveImpl + + PUBWEAK MPU_xQueuePeekImpl +MPU_xQueuePeekImpl: + b MPU_xQueuePeekImpl + + PUBWEAK MPU_xQueueSemaphoreTakeImpl +MPU_xQueueSemaphoreTakeImpl: + b MPU_xQueueSemaphoreTakeImpl + + PUBWEAK MPU_xQueueGetMutexHolderImpl +MPU_xQueueGetMutexHolderImpl: + b MPU_xQueueGetMutexHolderImpl + + PUBWEAK MPU_xQueueTakeMutexRecursiveImpl +MPU_xQueueTakeMutexRecursiveImpl: + b MPU_xQueueTakeMutexRecursiveImpl + + PUBWEAK MPU_xQueueGiveMutexRecursiveImpl +MPU_xQueueGiveMutexRecursiveImpl: + b MPU_xQueueGiveMutexRecursiveImpl + + PUBWEAK MPU_xQueueSelectFromSetImpl +MPU_xQueueSelectFromSetImpl: + b MPU_xQueueSelectFromSetImpl + + PUBWEAK MPU_xQueueAddToSetImpl +MPU_xQueueAddToSetImpl: + b MPU_xQueueAddToSetImpl + + PUBWEAK MPU_vQueueAddToRegistryImpl +MPU_vQueueAddToRegistryImpl: + b MPU_vQueueAddToRegistryImpl + + PUBWEAK MPU_vQueueUnregisterQueueImpl +MPU_vQueueUnregisterQueueImpl: + b MPU_vQueueUnregisterQueueImpl + + PUBWEAK MPU_pcQueueGetNameImpl +MPU_pcQueueGetNameImpl: + b MPU_pcQueueGetNameImpl + + PUBWEAK MPU_pvTimerGetTimerIDImpl +MPU_pvTimerGetTimerIDImpl: + b MPU_pvTimerGetTimerIDImpl + + PUBWEAK MPU_vTimerSetTimerIDImpl +MPU_vTimerSetTimerIDImpl: + b MPU_vTimerSetTimerIDImpl + + PUBWEAK MPU_xTimerIsTimerActiveImpl +MPU_xTimerIsTimerActiveImpl: + b MPU_xTimerIsTimerActiveImpl + + PUBWEAK MPU_xTimerGetTimerDaemonTaskHandleImpl +MPU_xTimerGetTimerDaemonTaskHandleImpl: + b MPU_xTimerGetTimerDaemonTaskHandleImpl + + PUBWEAK MPU_xTimerGenericCommandFromTaskImpl +MPU_xTimerGenericCommandFromTaskImpl: + b MPU_xTimerGenericCommandFromTaskImpl + + PUBWEAK MPU_pcTimerGetNameImpl +MPU_pcTimerGetNameImpl: + b MPU_pcTimerGetNameImpl + + PUBWEAK MPU_vTimerSetReloadModeImpl +MPU_vTimerSetReloadModeImpl: + b MPU_vTimerSetReloadModeImpl + + PUBWEAK MPU_xTimerGetReloadModeImpl +MPU_xTimerGetReloadModeImpl: + b MPU_xTimerGetReloadModeImpl + + PUBWEAK MPU_uxTimerGetReloadModeImpl +MPU_uxTimerGetReloadModeImpl: + b MPU_uxTimerGetReloadModeImpl + + PUBWEAK MPU_xTimerGetPeriodImpl +MPU_xTimerGetPeriodImpl: + b MPU_xTimerGetPeriodImpl + + PUBWEAK MPU_xTimerGetExpiryTimeImpl +MPU_xTimerGetExpiryTimeImpl: + b MPU_xTimerGetExpiryTimeImpl + + PUBWEAK MPU_xEventGroupWaitBitsImpl +MPU_xEventGroupWaitBitsImpl: + b MPU_xEventGroupWaitBitsImpl + + PUBWEAK MPU_xEventGroupClearBitsImpl +MPU_xEventGroupClearBitsImpl: + b MPU_xEventGroupClearBitsImpl + + PUBWEAK MPU_xEventGroupSetBitsImpl +MPU_xEventGroupSetBitsImpl: + b MPU_xEventGroupSetBitsImpl + + PUBWEAK MPU_xEventGroupSyncImpl +MPU_xEventGroupSyncImpl: + b MPU_xEventGroupSyncImpl + + PUBWEAK MPU_uxEventGroupGetNumberImpl +MPU_uxEventGroupGetNumberImpl: + b MPU_uxEventGroupGetNumberImpl + + PUBWEAK MPU_vEventGroupSetNumberImpl +MPU_vEventGroupSetNumberImpl: + b MPU_vEventGroupSetNumberImpl + + PUBWEAK MPU_xStreamBufferSendImpl +MPU_xStreamBufferSendImpl: + b MPU_xStreamBufferSendImpl + + PUBWEAK MPU_xStreamBufferReceiveImpl +MPU_xStreamBufferReceiveImpl: + b MPU_xStreamBufferReceiveImpl + + PUBWEAK MPU_xStreamBufferIsFullImpl +MPU_xStreamBufferIsFullImpl: + b MPU_xStreamBufferIsFullImpl + + PUBWEAK MPU_xStreamBufferIsEmptyImpl +MPU_xStreamBufferIsEmptyImpl: + b MPU_xStreamBufferIsEmptyImpl + + PUBWEAK MPU_xStreamBufferSpacesAvailableImpl +MPU_xStreamBufferSpacesAvailableImpl: + b MPU_xStreamBufferSpacesAvailableImpl + + PUBWEAK MPU_xStreamBufferBytesAvailableImpl +MPU_xStreamBufferBytesAvailableImpl: + b MPU_xStreamBufferBytesAvailableImpl + + PUBWEAK MPU_xStreamBufferSetTriggerLevelImpl +MPU_xStreamBufferSetTriggerLevelImpl: + b MPU_xStreamBufferSetTriggerLevelImpl + + PUBWEAK MPU_xStreamBufferNextMessageLengthBytesImpl +MPU_xStreamBufferNextMessageLengthBytesImpl: + b MPU_xStreamBufferNextMessageLengthBytesImpl + +/*-----------------------------------------------------------*/ + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + END diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s new file mode 100644 index 000000000..ba6e8e915 --- /dev/null +++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s @@ -0,0 +1,456 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" + +/* System call numbers includes. */ +#include "mpu_syscall_numbers.h" + +#ifndef configUSE_MPU_WRAPPERS_V1 + #define configUSE_MPU_WRAPPERS_V1 0 +#endif + + EXTERN pxCurrentTCB + EXTERN vTaskSwitchContext + EXTERN vPortSVCHandler_C +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + EXTERN vSystemCallEnter + EXTERN vSystemCallExit +#endif + + PUBLIC xIsPrivileged + PUBLIC vResetPrivilege + PUBLIC vRestoreContextOfFirstTask + PUBLIC vRaisePrivilege + PUBLIC vStartFirstTask + PUBLIC ulSetInterruptMask + PUBLIC vClearInterruptMask + PUBLIC PendSV_Handler + PUBLIC SVC_Handler +/*-----------------------------------------------------------*/ + +/*---------------- Unprivileged Functions -------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION .text:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +xIsPrivileged: + mrs r0, control /* r0 = CONTROL. */ + tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + ite ne + movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vResetPrivilege: + mrs r0, control /* r0 = CONTROL. */ + orr r0, r0, #1 /* r0 = r0 | 1. */ + msr control, r0 /* CONTROL = r0. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +/*----------------- Privileged Functions --------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION privileged_functions:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +vRestoreContextOfFirstTask: + program_mpu_first_task: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r2] /* r0 = pxCurrentTCB. */ + + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + str r2, [r1] /* Disable MPU. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r1, [r2] /* Program MAIR0. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + + movs r3, #4 /* r3 = 4. */ + str r3, [r1] /* Program RNR = 4. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + #if ( configTOTAL_MPU_REGIONS == 16 ) + movs r3, #8 /* r3 = 8. */ + str r3, [r1] /* Program RNR = 8. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + movs r3, #12 /* r3 = 12. */ + str r3, [r1] /* Program RNR = 12. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + orr r2, #1 /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */ + str r2, [r1] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + + restore_context_first_task: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r2] /* r0 = pxCurrentTCB.*/ + ldr r1, [r0] /* r1 = Location of saved context in TCB. */ + + restore_special_regs_first_task: + #if ( configENABLE_PAC == 1 ) + ldmdb r1!, {r2-r5} /* Read task's dedicated PAC key from the task's context. */ + msr PAC_KEY_P_0, r2 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_1, r3 + msr PAC_KEY_P_2, r4 + msr PAC_KEY_P_3, r5 + clrm {r2-r5} /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + ldmdb r1!, {r2-r4, lr} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */ + msr psp, r2 + msr psplim, r3 + msr control, r4 + + restore_general_regs_first_task: + ldmdb r1!, {r4-r11} /* r4-r11 contain hardware saved context. */ + stmia r2!, {r4-r11} /* Copy the hardware saved context on the task stack. */ + ldmdb r1!, {r4-r11} /* r4-r11 restored. */ + + restore_context_done_first_task: + str r1, [r0] /* Save the location where the context should be saved next as the first member of TCB. */ + mov r0, #0 + msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ + bx lr + +#else /* configENABLE_MPU */ + +vRestoreContextOfFirstTask: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + +#if ( configENABLE_PAC == 1 ) + ldmia r0!, {r1-r4} /* Read task's dedicated PAC key from stack. */ + msr PAC_KEY_P_3, r1 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_2, r2 + msr PAC_KEY_P_1, r3 + msr PAC_KEY_P_0, r4 + clrm {r1-r4} /* Clear r1-r4. */ +#endif /* configENABLE_PAC */ + + ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */ + msr psplim, r1 /* Set this task's PSPLIM value. */ + mrs r1, control /* Obtain current control register value. */ + orrs r1, r1, #2 /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */ + msr control, r1 /* Write back the new control register value. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + mov r0, #0 + msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ + bx r2 /* Finally, branch to EXC_RETURN. */ + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +vRaisePrivilege: + mrs r0, control /* Read the CONTROL register. */ + bic r0, r0, #1 /* Clear the bit 0. */ + msr control, r0 /* Write back the new CONTROL value. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vStartFirstTask: + ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */ + ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */ + ldr r0, [r0] /* The first entry in vector table is stack pointer. */ + msr msp, r0 /* Set the MSP back to the start of the stack. */ + cpsie i /* Globally enable interrupts. */ + cpsie f + dsb + isb + svc 102 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */ +/*-----------------------------------------------------------*/ + +ulSetInterruptMask: + mrs r0, basepri /* r0 = basepri. Return original basepri value. */ + mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r1 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vClearInterruptMask: + msr basepri, r0 /* basepri = ulMask. */ + dsb + isb + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +PendSV_Handler: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r2] /* r0 = pxCurrentTCB. */ + ldr r1, [r0] /* r1 = Location in TCB where the context should be saved. */ + mrs r2, psp /* r2 = PSP. */ + + save_general_regs: + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + add r2, r2, #0x20 /* Move r2 to location where s0 is saved. */ + tst lr, #0x10 + ittt eq + vstmiaeq r1!, {s16-s31} /* Store s16-s31. */ + vldmiaeq r2, {s0-s16} /* Copy hardware saved FP context into s0-s16. */ + vstmiaeq r1!, {s0-s16} /* Store hardware saved FP context. */ + sub r2, r2, #0x20 /* Set r2 back to the location of hardware saved context. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + stmia r1!, {r4-r11} /* Store r4-r11. */ + ldmia r2, {r4-r11} /* Copy the hardware saved context into r4-r11. */ + stmia r1!, {r4-r11} /* Store the hardware saved context. */ + + save_special_regs: + mrs r3, psplim /* r3 = PSPLIM. */ + mrs r4, control /* r4 = CONTROL. */ + stmia r1!, {r2-r4, lr} /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ + #if ( configENABLE_PAC == 1 ) + mrs r2, PAC_KEY_P_0 /* Read task's dedicated PAC key from the PAC key registers. */ + mrs r3, PAC_KEY_P_1 + mrs r4, PAC_KEY_P_2 + mrs r5, PAC_KEY_P_3 + stmia r1!, {r2-r5} /* Store the task's dedicated PAC key on the task's context. */ + clrm {r2-r5} /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + + str r1, [r0] /* Save the location from where the context should be restored as the first member of TCB. */ + + select_next_task: + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bl vTaskSwitchContext + mov r0, #0 /* r0 = 0. */ + msr basepri, r0 /* Enable interrupts. */ + + program_mpu: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r2] /* r0 = pxCurrentTCB. */ + + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + str r2, [r1] /* Disable MPU. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r1, [r2] /* Program MAIR0. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + + movs r3, #4 /* r3 = 4. */ + str r3, [r1] /* Program RNR = 4. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + #if ( configTOTAL_MPU_REGIONS == 16 ) + movs r3, #8 /* r3 = 8. */ + str r3, [r1] /* Program RNR = 8. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + movs r3, #12 /* r3 = 12. */ + str r3, [r1] /* Program RNR = 12. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + orr r2, #1 /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */ + str r2, [r1] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + + restore_context: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r2] /* r0 = pxCurrentTCB.*/ + ldr r1, [r0] /* r1 = Location of saved context in TCB. */ + + restore_special_regs: + #if ( configENABLE_PAC == 1 ) + ldmdb r1!, {r2-r5} /* Read task's dedicated PAC key from the task's context. */ + msr PAC_KEY_P_0, r2 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_1, r3 + msr PAC_KEY_P_2, r4 + msr PAC_KEY_P_3, r5 + clrm {r2-r5} /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + ldmdb r1!, {r2-r4, lr} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */ + msr psp, r2 + msr psplim, r3 + msr control, r4 + + restore_general_regs: + ldmdb r1!, {r4-r11} /* r4-r11 contain hardware saved context. */ + stmia r2!, {r4-r11} /* Copy the hardware saved context on the task stack. */ + ldmdb r1!, {r4-r11} /* r4-r11 restored. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 + ittt eq + vldmdbeq r1!, {s0-s16} /* s0-s16 contain hardware saved FP context. */ + vstmiaeq r2!, {s0-s16} /* Copy hardware saved FP context on the task stack. */ + vldmdbeq r1!, {s16-s31} /* Restore s16-s31. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + + restore_context_done: + str r1, [r0] /* Save the location where the context should be saved next as the first member of TCB. */ + bx lr + +#else /* configENABLE_MPU */ + +PendSV_Handler: + mrs r0, psp /* Read PSP in r0. */ +#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + it eq + vstmdbeq r0!, {s16-s31} /* Store the additional FP context registers which are not saved automatically. */ +#endif /* configENABLE_FPU || configENABLE_MVE */ + + mrs r2, psplim /* r2 = PSPLIM. */ + mov r3, lr /* r3 = LR/EXC_RETURN. */ + stmdb r0!, {r2-r11} /* Store on the stack - PSPLIM, LR and registers that are not automatically. */ + +#if ( configENABLE_PAC == 1 ) + mrs r1, PAC_KEY_P_3 /* Read task's dedicated PAC key from the PAC key registers. */ + mrs r2, PAC_KEY_P_2 + mrs r3, PAC_KEY_P_1 + mrs r4, PAC_KEY_P_0 + stmdb r0!, {r1-r4} /* Store the task's dedicated PAC key on the stack. */ + clrm {r1-r4} /* Clear r1-r4. */ +#endif /* configENABLE_PAC */ + + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + str r0, [r1] /* Save the new top of stack in TCB. */ + + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bl vTaskSwitchContext + mov r0, #0 /* r0 = 0. */ + msr basepri, r0 /* Enable interrupts. */ + + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ + +#if ( configENABLE_PAC == 1 ) + ldmia r0!, {r2-r5} /* Read task's dedicated PAC key from stack. */ + msr PAC_KEY_P_3, r2 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_2, r3 + msr PAC_KEY_P_1, r4 + msr PAC_KEY_P_0, r5 + clrm {r2-r5} /* Clear r2-r5. */ +#endif /* configENABLE_PAC */ + + ldmia r0!, {r2-r11} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */ + +#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst r3, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + it eq + vldmiaeq r0!, {s16-s31} /* Restore the additional FP context registers which are not restored automatically. */ +#endif /* configENABLE_FPU || configENABLE_MVE */ + + msr psplim, r2 /* Restore the PSPLIM register value for the task. */ + msr psp, r0 /* Remember the new top of stack for the task. */ + bx r3 + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + +SVC_Handler: + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + + ldr r1, [r0, #24] + ldrb r2, [r1, #-2] + cmp r2, #NUM_SYSTEM_CALLS + blt syscall_enter + cmp r2, #104 /* portSVC_SYSTEM_CALL_EXIT. */ + beq syscall_exit + b vPortSVCHandler_C + + syscall_enter: + mov r1, lr + b vSystemCallEnter + + syscall_exit: + mov r1, lr + b vSystemCallExit + +#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +SVC_Handler: + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + b vPortSVCHandler_C + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + + END diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h new file mode 100644 index 000000000..53b668b5b --- /dev/null +++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h @@ -0,0 +1,88 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M33" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portARMV8M_MINOR_VERSION 0 +#define portDONT_DISCARD __root +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +#ifndef configENABLE_MVE + #define configENABLE_MVE 0 +#elif ( configENABLE_MVE != 0 ) + #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M33. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ +#pragma diag_suppress=Be006 +#pragma diag_suppress=Pa082 +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h new file mode 100644 index 000000000..6e543efb5 --- /dev/null +++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h @@ -0,0 +1,88 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M35P" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portARMV8M_MINOR_VERSION 0 +#define portDONT_DISCARD __root +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +#ifndef configENABLE_MVE + #define configENABLE_MVE 0 +#elif ( configENABLE_MVE != 0 ) + #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M35. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ +#pragma diag_suppress=Be006 +#pragma diag_suppress=Pa082 +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM52/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM52/portmacro.h new file mode 100644 index 000000000..19de84eb8 --- /dev/null +++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM52/portmacro.h @@ -0,0 +1,87 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (c) 2025 Arm Technology (China) Co., Ltd.All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_MVE + #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE. +#endif /* configENABLE_MVE */ +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M52" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portARMV8M_MINOR_VERSION 1 +#define portDONT_DISCARD __root +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ +#pragma diag_suppress=Be006 +#pragma diag_suppress=Pa082 +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h new file mode 100644 index 000000000..597af66fa --- /dev/null +++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h @@ -0,0 +1,86 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_MVE + #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE. +#endif /* configENABLE_MVE */ +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M55" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portARMV8M_MINOR_VERSION 1 +#define portDONT_DISCARD __root +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ +#pragma diag_suppress=Be006 +#pragma diag_suppress=Pa082 +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h new file mode 100644 index 000000000..ff5c9895d --- /dev/null +++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h @@ -0,0 +1,86 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_MVE + #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE. +#endif /* configENABLE_MVE */ +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M85" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portARMV8M_MINOR_VERSION 1 +#define portDONT_DISCARD __root +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ +#pragma diag_suppress=Be006 +#pragma diag_suppress=Pa082 +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/ARMv8M/non_secure/portable/IAR/ARM_STAR_MC3/portmacro.h b/portable/ARMv8M/non_secure/portable/IAR/ARM_STAR_MC3/portmacro.h new file mode 100644 index 000000000..a0ee66907 --- /dev/null +++ b/portable/ARMv8M/non_secure/portable/IAR/ARM_STAR_MC3/portmacro.h @@ -0,0 +1,87 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (c) 2026 Arm Technology (China) Co., Ltd.All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_MVE + #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE. +#endif /* configENABLE_MVE */ +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "STAR-MC3" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portARMV8M_MINOR_VERSION 1 +#define portDONT_DISCARD __root +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ +#pragma diag_suppress=Be006 +#pragma diag_suppress=Pa082 +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/ARMv8M/non_secure/portasm.h b/portable/ARMv8M/non_secure/portasm.h new file mode 100644 index 000000000..b7021b024 --- /dev/null +++ b/portable/ARMv8M/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kernel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/portable/ARMv8M/non_secure/portmacrocommon.h b/portable/ARMv8M/non_secure/portmacrocommon.h new file mode 100644 index 000000000..f373bcad5 --- /dev/null +++ b/portable/ARMv8M/non_secure/portmacrocommon.h @@ -0,0 +1,582 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACROCOMMON_H +#define PORTMACROCOMMON_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. +#endif /* configENABLE_FPU */ + +#ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. +#endif /* configENABLE_MPU */ + +#ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. +#endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() +#define portINLINE __inline +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif +#define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ +extern BaseType_t xPortIsInsideInterrupt( void ); + +extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + +extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; +extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + +extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; +extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + +#if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_PAC == 1 ) + + /** + * @brief Generates 128-bit task's random PAC key. + * + * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be + * filled with a 128-bit random number. + */ + void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); + +#endif /* configENABLE_PAC */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ +#if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) +#else + #define portPRIVILEGE_BIT ( 0x0UL ) +#endif /* configENABLE_MPU */ + +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ +#define portPRIVILEGED_FLASH_REGION ( 0UL ) +#define portUNPRIVILEGED_FLASH_REGION ( 1UL ) +#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) +#define portPRIVILEGED_RAM_REGION ( 3UL ) +#define portSTACK_REGION ( 4UL ) +#define portFIRST_CONFIGURABLE_REGION ( 5UL ) +#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) +#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) +#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ +#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ +#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ +#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ +#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ +#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ +#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ +#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) +#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) +#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + +#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) +#define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) +#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) +#define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + +#define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + #ifndef configSYSTEM_CALL_STACK_SIZE + #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. + #endif + + /** + * @brief System call stack. + */ + typedef struct SYSTEM_CALL_STACK_INFO + { + uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; + uint32_t * pulSystemCallStack; + uint32_t * pulSystemCallStackLimit; + uint32_t * pulTaskStack; + uint32_t ulLinkRegisterAtSystemCallEntry; + uint32_t ulStackLimitRegisterAtSystemCallEntry; + } xSYSTEM_CALL_STACK_INFO; + + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + /** + * @brief MPU settings as stored in the TCB. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><-----------><----> + * 16 17 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 71 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 17 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 55 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | | | PC, xPSR | EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><-----------><----> + * 16 17 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 70 + + #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + /* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 17 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 54 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+------------------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +----------+-----------------+------------------------------+------------+-----+ + * + * <---------><----------------><------------------------------><-----------><----> + * 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 38 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+----------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | PC, xPSR | EXC_RETURN | | | + * +----------+-----------------+----------------------+------------+-----+ + * + * <---------><----------------><----------------------><-----------><----> + * 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 37 + + #else /* #if( configENABLE_TRUSTZONE == 1 ) */ + + /* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) + + /* Size of an Access Control List (ACL) entry in bits. */ + #define portACL_ENTRY_SIZE_BITS ( 32U ) + + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + uint32_t ulContext[ MAX_CONTEXT_SIZE ]; + uint32_t ulTaskFlags; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo; + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ]; + #endif + #endif + } xMPU_SETTINGS; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Validate priority of ISRs that are allowed to call FreeRTOS + * system calls. + */ +#if ( configASSERT_DEFINED == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif +#endif + +/** + * @brief SVC numbers. + */ +#define portSVC_ALLOCATE_SECURE_CONTEXT 100 +#define portSVC_FREE_SECURE_CONTEXT 101 +#define portSVC_START_SCHEDULER 102 +#define portSVC_RAISE_PRIVILEGE 103 +#define portSVC_SYSTEM_CALL_EXIT 104 +#define portSVC_YIELD 105 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) +#endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() +#else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + extern BaseType_t xPortIsTaskPrivileged( void ); + +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACROCOMMON_H */ diff --git a/portable/ARMv8M/secure/ReadMe.txt b/portable/ARMv8M/secure/ReadMe.txt new file mode 100644 index 000000000..5a8c28838 --- /dev/null +++ b/portable/ARMv8M/secure/ReadMe.txt @@ -0,0 +1,11 @@ +This directory tree contains the master copy of the FreeRTOS Armv8-M and +Armv8.1-M ports. +Do not use the files located here! These file are copied into separate +FreeRTOS/Source/portable/[compiler]/ARM_[CM23|CM33|CM52|CM55|CM85|STAR_MC3]_NNN directories +prior to each FreeRTOS release. + +If your Armv8-M/Armv8.1-M application uses TrustZone then use the files from the +FreeRTOS/Source/portable/[compiler]/ARM_[CM23|CM33|CM52|CM55|CM85|STAR_MC3] directories. + +If your Armv8-M/Armv8.1-M application does not use TrustZone then use the files from +the FreeRTOS/Source/portable/[compiler]/ARM_[CM23|CM33|CM52|CM55|CM85|STAR_MC3]_NTZ directories. diff --git a/portable/ARMv8M/secure/context/portable/GCC/ARM_CM23/secure_context_port.c b/portable/ARMv8M/secure/context/portable/GCC/ARM_CM23/secure_context_port.c new file mode 100644 index 000000000..32559ad04 --- /dev/null +++ b/portable/ARMv8M/secure/context/portable/GCC/ARM_CM23/secure_context_port.c @@ -0,0 +1,99 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Secure context includes. */ +#include "secure_context.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +#if ( configENABLE_FPU == 1 ) + #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0. +#endif + +void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) ); +void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) ); + +void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) +{ + /* pxSecureContext value is in r0. */ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r1, ipsr \n" /* r1 = IPSR. */ + " cbz r1, load_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */ + " ldmia r0!, {r1, r2} \n" /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */ + " \n" + #if ( configENABLE_MPU == 1 ) + " ldmia r1!, {r3} \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */ + " msr control, r3 \n" /* CONTROL = r3. */ + #endif /* configENABLE_MPU */ + " \n" + " msr psplim, r2 \n" /* PSPLIM = r2. */ + " msr psp, r1 \n" /* PSP = r1. */ + " \n" + " load_ctx_therad_mode: \n" + " bx lr \n" + " \n" + ::: "r0", "r1", "r2" + ); +} +/*-----------------------------------------------------------*/ + +void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) +{ + /* pxSecureContext value is in r0. */ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r1, ipsr \n" /* r1 = IPSR. */ + " cbz r1, save_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */ + " mrs r1, psp \n" /* r1 = PSP. */ + " \n" + #if ( configENABLE_MPU == 1 ) + " mrs r2, control \n" /* r2 = CONTROL. */ + " subs r1, r1, #4 \n" /* Make space for the CONTROL value on the stack. */ + " str r1, [r0] \n" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */ + " stmia r1!, {r2} \n" /* Store CONTROL value on the stack. */ + #else /* configENABLE_MPU */ + " str r1, [r0] \n" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */ + #endif /* configENABLE_MPU */ + " \n" + " movs r1, %0 \n" /* r1 = securecontextNO_STACK. */ + " msr psplim, r1 \n" /* PSPLIM = securecontextNO_STACK. */ + " msr psp, r1 \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */ + " \n" + " save_ctx_therad_mode: \n" + " bx lr \n" + " \n" + ::"i" ( securecontextNO_STACK ) : "r1", "memory" + ); +} +/*-----------------------------------------------------------*/ diff --git a/portable/ARMv8M/secure/context/portable/GCC/ARM_CM33/secure_context_port.c b/portable/ARMv8M/secure/context/portable/GCC/ARM_CM33/secure_context_port.c new file mode 100644 index 000000000..2d3d9439d --- /dev/null +++ b/portable/ARMv8M/secure/context/portable/GCC/ARM_CM33/secure_context_port.c @@ -0,0 +1,97 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Secure context includes. */ +#include "secure_context.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) ); +void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) ); + +void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) +{ + /* pxSecureContext value is in r0. */ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r1, ipsr \n" /* r1 = IPSR. */ + " cbz r1, load_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */ + " ldmia r0!, {r1, r2} \n" /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */ + " \n" + #if ( configENABLE_MPU == 1 ) + " ldmia r1!, {r3} \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */ + " msr control, r3 \n" /* CONTROL = r3. */ + #endif /* configENABLE_MPU */ + " \n" + " msr psplim, r2 \n" /* PSPLIM = r2. */ + " msr psp, r1 \n" /* PSP = r1. */ + " \n" + " load_ctx_therad_mode: \n" + " bx lr \n" + " \n" + ::: "r0", "r1", "r2" + ); +} +/*-----------------------------------------------------------*/ + +void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) +{ + /* pxSecureContext value is in r0. */ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r1, ipsr \n" /* r1 = IPSR. */ + " cbz r1, save_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */ + " mrs r1, psp \n" /* r1 = PSP. */ + " \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " vstmdb r1!, {s0} \n" /* Trigger the deferred stacking of FPU registers. */ + " vldmia r1!, {s0} \n" /* Nullify the effect of the previous statement. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + #if ( configENABLE_MPU == 1 ) + " mrs r2, control \n" /* r2 = CONTROL. */ + " stmdb r1!, {r2} \n" /* Store CONTROL value on the stack. */ + #endif /* configENABLE_MPU */ + " \n" + " str r1, [r0] \n" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */ + " movs r1, %0 \n" /* r1 = securecontextNO_STACK. */ + " msr psplim, r1 \n" /* PSPLIM = securecontextNO_STACK. */ + " msr psp, r1 \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */ + " \n" + " save_ctx_therad_mode: \n" + " bx lr \n" + " \n" + ::"i" ( securecontextNO_STACK ) : "r1", "memory" + ); +} +/*-----------------------------------------------------------*/ diff --git a/portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port_asm.s b/portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port_asm.s new file mode 100644 index 000000000..f70e89115 --- /dev/null +++ b/portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port_asm.s @@ -0,0 +1,88 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + SECTION .text:CODE:NOROOT(2) + THUMB + +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" + + PUBLIC SecureContext_LoadContextAsm + PUBLIC SecureContext_SaveContextAsm + +#if ( configENABLE_FPU == 1 ) + #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0. +#endif +/*-----------------------------------------------------------*/ + +SecureContext_LoadContextAsm: + /* pxSecureContext value is in r0. */ + mrs r1, ipsr /* r1 = IPSR. */ + cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */ + ldmia r0!, {r1, r2} /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */ + +#if ( configENABLE_MPU == 1 ) + ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL. */ + msr control, r3 /* CONTROL = r3. */ +#endif /* configENABLE_MPU */ + + msr psplim, r2 /* PSPLIM = r2. */ + msr psp, r1 /* PSP = r1. */ + + load_ctx_therad_mode: + bx lr +/*-----------------------------------------------------------*/ + +SecureContext_SaveContextAsm: + /* pxSecureContext value is in r0. */ + mrs r1, ipsr /* r1 = IPSR. */ + cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */ + mrs r1, psp /* r1 = PSP. */ + +#if ( configENABLE_MPU == 1 ) + mrs r2, control /* r2 = CONTROL. */ + subs r1, r1, #4 /* Make space for the CONTROL value on the stack. */ + str r1, [r0] /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */ + stmia r1!, {r2} /* Store CONTROL value on the stack. */ +#else /* configENABLE_MPU */ + str r1, [r0] /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */ +#endif /* configENABLE_MPU */ + + movs r1, #0 /* r1 = securecontextNO_STACK. */ + msr psplim, r1 /* PSPLIM = securecontextNO_STACK. */ + msr psp, r1 /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */ + + save_ctx_therad_mode: + bx lr +/*-----------------------------------------------------------*/ + + END diff --git a/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port_asm.s b/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port_asm.s new file mode 100644 index 000000000..27a8f3933 --- /dev/null +++ b/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port_asm.s @@ -0,0 +1,86 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + SECTION .text:CODE:NOROOT(2) + THUMB + +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" + + PUBLIC SecureContext_LoadContextAsm + PUBLIC SecureContext_SaveContextAsm +/*-----------------------------------------------------------*/ + +SecureContext_LoadContextAsm: + /* pxSecureContext value is in r0. */ + mrs r1, ipsr /* r1 = IPSR. */ + cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */ + ldmia r0!, {r1, r2} /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */ + +#if ( configENABLE_MPU == 1 ) + ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL. */ + msr control, r3 /* CONTROL = r3. */ +#endif /* configENABLE_MPU */ + + msr psplim, r2 /* PSPLIM = r2. */ + msr psp, r1 /* PSP = r1. */ + + load_ctx_therad_mode: + bx lr +/*-----------------------------------------------------------*/ + +SecureContext_SaveContextAsm: + /* pxSecureContext value is in r0. */ + mrs r1, ipsr /* r1 = IPSR. */ + cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */ + mrs r1, psp /* r1 = PSP. */ + +#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + vstmdb r1!, {s0} /* Trigger the deferred stacking of FPU registers. */ + vldmia r1!, {s0} /* Nullify the effect of the previous statement. */ +#endif /* configENABLE_FPU || configENABLE_MVE */ + +#if ( configENABLE_MPU == 1 ) + mrs r2, control /* r2 = CONTROL. */ + stmdb r1!, {r2} /* Store CONTROL value on the stack. */ +#endif /* configENABLE_MPU */ + + str r1, [r0] /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */ + movs r1, #0 /* r1 = securecontextNO_STACK. */ + msr psplim, r1 /* PSPLIM = securecontextNO_STACK. */ + msr psp, r1 /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */ + + save_ctx_therad_mode: + bx lr +/*-----------------------------------------------------------*/ + + END diff --git a/portable/ARMv8M/secure/context/secure_context.c b/portable/ARMv8M/secure/context/secure_context.c new file mode 100644 index 000000000..3aa335e63 --- /dev/null +++ b/portable/ARMv8M/secure/context/secure_context.c @@ -0,0 +1,354 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Secure context includes. */ +#include "secure_context.h" + +/* Secure heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief CONTROL value for privileged tasks. + * + * Bit[0] - 0 --> Thread mode is privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_PRIVILEGED 0x02 + +/** + * @brief CONTROL value for un-privileged tasks. + * + * Bit[0] - 1 --> Thread mode is un-privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03 + +/** + * @brief Size of stack seal values in bytes. + */ +#define securecontextSTACK_SEAL_SIZE 8 + +/** + * @brief Stack seal value as recommended by ARM. + */ +#define securecontextSTACK_SEAL_VALUE 0xFEF5EDA5 + +/** + * @brief Maximum number of secure contexts. + */ +#ifndef secureconfigMAX_SECURE_CONTEXTS + #define secureconfigMAX_SECURE_CONTEXTS 8UL +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Pre-allocated array of secure contexts. + */ +SecureContext_t xSecureContexts[ secureconfigMAX_SECURE_CONTEXTS ]; +/*-----------------------------------------------------------*/ + +/** + * @brief Get a free secure context for a task from the secure context pool (xSecureContexts). + * + * This function ensures that only one secure context is allocated for a task. + * + * @param[in] pvTaskHandle The task handle for which the secure context is allocated. + * + * @return Index of a free secure context in the xSecureContexts array. + */ +static uint32_t ulGetSecureContext( void * pvTaskHandle ); + +/** + * @brief Return the secure context to the secure context pool (xSecureContexts). + * + * @param[in] ulSecureContextIndex Index of the context in the xSecureContexts array. + */ +static void vReturnSecureContext( uint32_t ulSecureContextIndex ); + +/* These are implemented in assembly. */ +extern void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ); +extern void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ); +/*-----------------------------------------------------------*/ + +static uint32_t ulGetSecureContext( void * pvTaskHandle ) +{ + /* Start with invalid index. */ + uint32_t i, ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + if( ( xSecureContexts[ i ].pucCurrentStackPointer == NULL ) && + ( xSecureContexts[ i ].pucStackLimit == NULL ) && + ( xSecureContexts[ i ].pucStackStart == NULL ) && + ( xSecureContexts[ i ].pvTaskHandle == NULL ) && + ( ulSecureContextIndex == secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = i; + } + else if( xSecureContexts[ i ].pvTaskHandle == pvTaskHandle ) + { + /* A task can only have one secure context. Do not allocate a second + * context for the same task. */ + ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + break; + } + } + + return ulSecureContextIndex; +} +/*-----------------------------------------------------------*/ + +static void vReturnSecureContext( uint32_t ulSecureContextIndex ) +{ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackStart = NULL; + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = NULL; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) +{ + uint32_t ulIPSR, i; + static uint32_t ulSecureContextsInitialized = 0; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ( ulIPSR != 0 ) && ( ulSecureContextsInitialized == 0 ) ) + { + /* Ensure to initialize secure contexts only once. */ + ulSecureContextsInitialized = 1; + + /* No stack for thread mode until a task's context is loaded. */ + secureportSET_PSPLIM( securecontextNO_STACK ); + secureportSET_PSP( securecontextNO_STACK ); + + /* Initialize all secure contexts. */ + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + xSecureContexts[ i ].pucCurrentStackPointer = NULL; + xSecureContexts[ i ].pucStackLimit = NULL; + xSecureContexts[ i ].pucStackStart = NULL; + xSecureContexts[ i ].pvTaskHandle = NULL; + } + + #if ( configENABLE_MPU == 1 ) + { + /* Configure thread mode to use PSP and to be unprivileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); + } + #else /* configENABLE_MPU */ + { + /* Configure thread mode to use PSP and to be privileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); + } + #endif /* configENABLE_MPU */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ) +#else /* configENABLE_MPU */ + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ) +#endif /* configENABLE_MPU */ +{ + uint8_t * pucStackMemory = NULL; + uint8_t * pucStackLimit; + uint32_t ulIPSR, ulSecureContextIndex; + SecureContextHandle_t xSecureContextHandle = securecontextINVALID_CONTEXT_ID; + + #if ( configENABLE_MPU == 1 ) + uint32_t * pulCurrentStackPointer = NULL; + #endif /* configENABLE_MPU */ + + /* Read the Interrupt Program Status Register (IPSR) and Process Stack Limit + * Register (PSPLIM) value. */ + secureportREAD_IPSR( ulIPSR ); + secureportREAD_PSPLIM( pucStackLimit ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. + * Also do nothing, if a secure context us already loaded. PSPLIM is set to + * securecontextNO_STACK when no secure context is loaded. */ + if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) ) + { + /* Obtain a free secure context. */ + ulSecureContextIndex = ulGetSecureContext( pvTaskHandle ); + + /* Were we able to get a free context? */ + if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS ) + { + /* Allocate the stack space. */ + pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + + if( pucStackMemory != NULL ) + { + /* Since stack grows down, the starting point will be the last + * location. Note that this location is next to the last + * allocated byte for stack (excluding the space for seal values) + * because the hardware decrements the stack pointer before + * writing i.e. if stack pointer is 0x2, a push operation will + * decrement the stack pointer to 0x1 and then write at 0x1. */ + xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize; + + /* Seal the created secure process stack. */ + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; + + /* The stack cannot go beyond this location. This value is + * programmed in the PSPLIM register on context switch.*/ + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = pucStackMemory; + + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle; + + #if ( configENABLE_MPU == 1 ) + { + /* Store the correct CONTROL value for the task on the stack. + * This value is programmed in the CONTROL register on + * context switch. */ + pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; + pulCurrentStackPointer--; + + if( ulIsTaskPrivileged ) + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; + } + else + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; + } + + /* Store the current stack pointer. This value is programmed in + * the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + } + #else /* configENABLE_MPU */ + { + /* Current SP is set to the starting of the stack. This + * value programmed in the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + } + #endif /* configENABLE_MPU */ + + /* Ensure to never return 0 as a valid context handle. */ + xSecureContextHandle = ulSecureContextIndex + 1UL; + } + } + } + + return xSecureContextHandle; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) +{ + uint32_t ulIPSR, ulSecureContextIndex; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* Only free if a valid context handle is passed. */ + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + /* Ensure that the secure context being deleted is associated with + * the task. */ + if( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) + { + /* Free the stack space. */ + vPortFree( xSecureContexts[ ulSecureContextIndex ].pucStackLimit ); + + /* Return the secure context back to the free secure contexts pool. */ + vReturnSecureContext( ulSecureContextIndex ); + } + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that no secure context is loaded and the task is loading it's + * own context. */ + if( ( pucStackLimit == securecontextNO_STACK ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_LoadContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that task's context is loaded and the task is saving it's own + * context. */ + if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_SaveContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ diff --git a/portable/ARMv8M/secure/context/secure_context.h b/portable/ARMv8M/secure/context/secure_context.h new file mode 100644 index 000000000..e36a8e430 --- /dev/null +++ b/portable/ARMv8M/secure/context/secure_context.h @@ -0,0 +1,138 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_CONTEXT_H__ +#define __SECURE_CONTEXT_H__ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" + +/** + * @brief PSP value when no secure context is loaded. + */ +#define securecontextNO_STACK 0x0 + +/** + * @brief Invalid context ID. + */ +#define securecontextINVALID_CONTEXT_ID 0UL +/*-----------------------------------------------------------*/ + +/** + * @brief Structure to represent a secure context. + * + * @note Since stack grows down, pucStackStart is the highest address while + * pucStackLimit is the first address of the allocated memory. + */ +typedef struct SecureContext +{ + uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */ + uint8_t * pucStackLimit; /**< Last location of the stack memory (PSPLIM). */ + uint8_t * pucStackStart; /**< First location of the stack memory. */ + void * pvTaskHandle; /**< Task handle of the task this context is associated with. */ +} SecureContext_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Opaque handle for a secure context. + */ +typedef uint32_t SecureContextHandle_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Initializes the secure context management system. + * + * PSP is set to NULL and therefore a task must allocate and load a context + * before calling any secure side function in the thread mode. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureContext_Init( void ); + +/** + * @brief Allocates a context on the secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] ulSecureStackSize Size of the stack to allocate on secure side. + * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise. + * + * @return Opaque context handle if context is successfully allocated, NULL + * otherwise. + */ +#if ( configENABLE_MPU == 1 ) + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ); +#else /* configENABLE_MPU */ + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ); +#endif /* configENABLE_MPU */ + +/** + * @brief Frees the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the + * context to be freed. + */ +void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); + +/** + * @brief Loads the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be loaded. + */ +void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); + +/** + * @brief Saves the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be saved. + */ +void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); + +#endif /* __SECURE_CONTEXT_H__ */ diff --git a/portable/ARMv8M/secure/heap/secure_heap.c b/portable/ARMv8M/secure/heap/secure_heap.c new file mode 100644 index 000000000..896b53e2d --- /dev/null +++ b/portable/ARMv8M/secure/heap/secure_heap.c @@ -0,0 +1,485 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Configuration includes. */ +#include "FreeRTOSConfig.h" + +/* Secure context heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Total heap size. + */ +#ifndef secureconfigTOTAL_HEAP_SIZE + #define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) ) +#endif + +/* No test marker by default. */ +#ifndef mtCOVERAGE_TEST_MARKER + #define mtCOVERAGE_TEST_MARKER() +#endif + +/* No tracing by default. */ +#ifndef traceMALLOC + #define traceMALLOC( pvReturn, xWantedSize ) +#endif + +/* No tracing by default. */ +#ifndef traceFREE + #define traceFREE( pv, xBlockSize ) +#endif + +/* Block sizes must not get too small. */ +#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) ) + +/* Assumes 8bit bytes! */ +#define secureheapBITS_PER_BYTE ( ( size_t ) 8 ) + +/* Max value that fits in a size_t type. */ +#define secureheapSIZE_MAX ( ~( ( size_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define secureheapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) ) + +/* MSB of the xBlockSize member of an BlockLink_t structure is used to track + * the allocation status of a block. When MSB of the xBlockSize member of + * an BlockLink_t structure is set then the block belongs to the application. + * When the bit is free the block is still part of the free heap space. */ +#define secureheapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) ) +#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 ) +#define secureheapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 ) +#define secureheapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK ) +#define secureheapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK ) +/*-----------------------------------------------------------*/ + +/* Allocate the memory for the heap. */ +#if ( configAPPLICATION_ALLOCATED_HEAP == 1 ) + +/* The application writer has already defined the array used for the RTOS +* heap - probably so it can be placed in a special segment or address. */ + extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#else /* configAPPLICATION_ALLOCATED_HEAP */ + static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#endif /* configAPPLICATION_ALLOCATED_HEAP */ + +/** + * @brief The linked list structure. + * + * This is used to link free blocks in order of their memory address. + */ +typedef struct A_BLOCK_LINK +{ + struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */ + size_t xBlockSize; /**< The size of the free block. */ +} BlockLink_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Called automatically to setup the required heap structures the first + * time pvPortMalloc() is called. + */ +static void prvHeapInit( void ); + +/** + * @brief Inserts a block of memory that is being freed into the correct + * position in the list of free memory blocks. + * + * The block being freed will be merged with the block in front it and/or the + * block behind it if the memory blocks are adjacent to each other. + * + * @param[in] pxBlockToInsert The block being freed. + */ +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ); +/*-----------------------------------------------------------*/ + +/** + * @brief The size of the structure placed at the beginning of each allocated + * memory block must by correctly byte aligned. + */ +static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + +/** + * @brief Create a couple of list links to mark the start and end of the list. + */ +static BlockLink_t xStart; +static BlockLink_t * pxEnd = NULL; + +/** + * @brief Keeps track of the number of free bytes remaining, but says nothing + * about fragmentation. + */ +static size_t xFreeBytesRemaining = 0U; +static size_t xMinimumEverFreeBytesRemaining = 0U; + +/*-----------------------------------------------------------*/ + +static void prvHeapInit( void ) +{ + BlockLink_t * pxFirstFreeBlock; + uint8_t * pucAlignedHeap; + size_t uxAddress; + size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE; + + /* Ensure the heap starts on a correctly aligned boundary. */ + uxAddress = ( size_t ) ucHeap; + + if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 ) + { + uxAddress += ( secureportBYTE_ALIGNMENT - 1 ); + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; + } + + pucAlignedHeap = ( uint8_t * ) uxAddress; + + /* xStart is used to hold a pointer to the first item in the list of free + * blocks. The void cast is used to prevent compiler warnings. */ + xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; + xStart.xBlockSize = ( size_t ) 0; + + /* pxEnd is used to mark the end of the list of free blocks and is inserted + * at the end of the heap space. */ + uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; + uxAddress -= xHeapStructSize; + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + pxEnd = ( void * ) uxAddress; + pxEnd->xBlockSize = 0; + pxEnd->pxNextFreeBlock = NULL; + + /* To start with there is a single free block that is sized to take up the + * entire heap space, minus the space taken by pxEnd. */ + pxFirstFreeBlock = ( void * ) pucAlignedHeap; + pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; + pxFirstFreeBlock->pxNextFreeBlock = pxEnd; + + /* Only one block exists - and it covers the entire usable heap space. */ + xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; +} +/*-----------------------------------------------------------*/ + +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) +{ + BlockLink_t * pxIterator; + uint8_t * puc; + + /* Iterate through the list until a block is found that has a higher address + * than the block being inserted. */ + for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) + { + /* Nothing to do here, just iterate to the right position. */ + } + + /* Do the block being inserted, and the block it is being inserted after + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxIterator; + + if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) + { + pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; + pxBlockToInsert = pxIterator; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Do the block being inserted, and the block it is being inserted before + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxBlockToInsert; + + if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) + { + if( pxIterator->pxNextFreeBlock != pxEnd ) + { + /* Form one big block from the two blocks. */ + pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxEnd; + } + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; + } + + /* If the block being inserted plugged a gap, so was merged with the block + * before and the block after, then it's pxNextFreeBlock pointer will have + * already been set, and should not be set here as that would make it point + * to itself. */ + if( pxIterator != pxBlockToInsert ) + { + pxIterator->pxNextFreeBlock = pxBlockToInsert; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} +/*-----------------------------------------------------------*/ + +void * pvPortMalloc( size_t xWantedSize ) +{ + BlockLink_t * pxBlock; + BlockLink_t * pxPreviousBlock; + BlockLink_t * pxNewBlockLink; + void * pvReturn = NULL; + size_t xAdditionalRequiredSize; + size_t xAllocatedBlockSize = 0; + + /* If this is the first call to malloc then the heap will require + * initialisation to setup the list of free blocks. */ + if( pxEnd == NULL ) + { + prvHeapInit(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xWantedSize > 0 ) + { + /* The wanted size must be increased so it can contain a BlockLink_t + * structure in addition to the requested amount of bytes. */ + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 ) + { + xWantedSize += xHeapStructSize; + + /* Ensure that blocks are always aligned to the required number + * of bytes. */ + if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 ) + { + /* Byte alignment required. */ + xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ); + + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 ) + { + xWantedSize += xAdditionalRequiredSize; + } + else + { + xWantedSize = 0; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + xWantedSize = 0; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Check the requested block size is not so large that the top bit is set. + * The top bit of the block size member of the BlockLink_t structure is used + * to determine who owns the block - the application or the kernel, so it + * must be free. */ + if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 ) + { + if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) + { + /* Traverse the list from the start (lowest address) block until + * one of adequate size is found. */ + pxPreviousBlock = &xStart; + pxBlock = xStart.pxNextFreeBlock; + + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + { + pxPreviousBlock = pxBlock; + pxBlock = pxBlock->pxNextFreeBlock; + } + + /* If the end marker was reached then a block of adequate size was + * not found. */ + if( pxBlock != pxEnd ) + { + /* Return the memory space pointed to - jumping over the + * BlockLink_t structure at its start. */ + pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); + + /* This block is being returned for use so must be taken out + * of the list of free blocks. */ + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + + /* If the block is larger than required it can be split into + * two. */ + if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE ) + { + /* This block is to be split into two. Create a new + * block following the number of bytes requested. The void + * cast is used to prevent byte alignment warnings from the + * compiler. */ + pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); + secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + + /* Calculate the sizes of two blocks split from the single + * block. */ + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + pxBlock->xBlockSize = xWantedSize; + + /* Insert the new block into the list of free blocks. */ + pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock; + pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xFreeBytesRemaining -= pxBlock->xBlockSize; + + if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) + { + xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xAllocatedBlockSize = pxBlock->xBlockSize; + + /* The block is being returned - it is allocated and owned by + * the application and has no "next" block. */ + secureheapALLOCATE_BLOCK( pxBlock ); + pxBlock->pxNextFreeBlock = NULL; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceMALLOC( pvReturn, xAllocatedBlockSize ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xAllocatedBlockSize; + + #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) + { + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */ + + secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 ); + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void * pv ) +{ + uint8_t * puc = ( uint8_t * ) pv; + BlockLink_t * pxLink; + + if( pv != NULL ) + { + /* The memory being freed will have an BlockLink_t structure immediately + * before it. */ + puc -= xHeapStructSize; + + /* This casting is to keep the compiler from issuing warnings. */ + pxLink = ( void * ) puc; + + /* Check the block is actually allocated. */ + secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ); + secureportASSERT( pxLink->pxNextFreeBlock == NULL ); + + if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ) + { + if( pxLink->pxNextFreeBlock == NULL ) + { + /* The block is being returned to the heap - it is no longer + * allocated. */ + secureheapFREE_BLOCK( pxLink ); + + secureportDISABLE_NON_SECURE_INTERRUPTS(); + { + /* Add this block to the list of free blocks. */ + xFreeBytesRemaining += pxLink->xBlockSize; + traceFREE( pv, pxLink->xBlockSize ); + prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); + } + secureportENABLE_NON_SECURE_INTERRUPTS(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } +} +/*-----------------------------------------------------------*/ + +size_t xPortGetFreeHeapSize( void ) +{ + return xFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +size_t xPortGetMinimumEverFreeHeapSize( void ) +{ + return xMinimumEverFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ diff --git a/portable/ARMv8M/secure/heap/secure_heap.h b/portable/ARMv8M/secure/heap/secure_heap.h new file mode 100644 index 000000000..0e84a9d9d --- /dev/null +++ b/portable/ARMv8M/secure/heap/secure_heap.h @@ -0,0 +1,66 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_HEAP_H__ +#define __SECURE_HEAP_H__ + +/* Standard includes. */ +#include + +/** + * @brief Allocates memory from heap. + * + * @param[in] xWantedSize The size of the memory to be allocated. + * + * @return Pointer to the memory region if the allocation is successful, NULL + * otherwise. + */ +void * pvPortMalloc( size_t xWantedSize ); + +/** + * @brief Frees the previously allocated memory. + * + * @param[in] pv Pointer to the memory to be freed. + */ +void vPortFree( void * pv ); + +/** + * @brief Get the free heap size. + * + * @return Free heap size. + */ +size_t xPortGetFreeHeapSize( void ); + +/** + * @brief Get the minimum ever free heap size. + * + * @return Minimum ever free heap size. + */ +size_t xPortGetMinimumEverFreeHeapSize( void ); + +#endif /* __SECURE_HEAP_H__ */ diff --git a/portable/ARMv8M/secure/init/secure_init.c b/portable/ARMv8M/secure/init/secure_init.c new file mode 100644 index 000000000..c50d37668 --- /dev/null +++ b/portable/ARMv8M/secure/init/secure_init.c @@ -0,0 +1,106 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Secure init includes. */ +#include "secure_init.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Constants required to manipulate the SCB. + */ +#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */ +#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL ) +#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS ) +#define secureinitSCB_AIRCR_PRIS_POS ( 14UL ) +#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS ) + +/** + * @brief Constants required to manipulate the FPU. + */ +#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define secureinitFPCCR_LSPENS_POS ( 29UL ) +#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS ) +#define secureinitFPCCR_TS_POS ( 26UL ) +#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS ) + +#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */ +#define secureinitNSACR_CP10_POS ( 10UL ) +#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS ) +#define secureinitNSACR_CP11_POS ( 11UL ) +#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS ) +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) | + ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) | + ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK ); + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is + * permitted. CP11 should be programmed to the same value as CP10. */ + *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK ); + + /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures + * that we can enable/disable lazy stacking in port.c file. */ + *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK ); + + /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP + * registers (S16-S31) are also pushed to stack on exception entry and + * restored on exception return. */ + *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK ); + } +} +/*-----------------------------------------------------------*/ diff --git a/portable/ARMv8M/secure/init/secure_init.h b/portable/ARMv8M/secure/init/secure_init.h new file mode 100644 index 000000000..ebe04900f --- /dev/null +++ b/portable/ARMv8M/secure/init/secure_init.h @@ -0,0 +1,54 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_INIT_H__ +#define __SECURE_INIT_H__ + +/** + * @brief De-prioritizes the non-secure exceptions. + * + * This is needed to ensure that the non-secure PendSV runs at the lowest + * priority. Context switch is done in the non-secure PendSV handler. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_DePrioritizeNSExceptions( void ); + +/** + * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access. + * + * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point + * Registers are not leaked to the non-secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_EnableNSFPUAccess( void ); + +#endif /* __SECURE_INIT_H__ */ diff --git a/portable/ARMv8M/secure/macros/secure_port_macros.h b/portable/ARMv8M/secure/macros/secure_port_macros.h new file mode 100644 index 000000000..a70da2c65 --- /dev/null +++ b/portable/ARMv8M/secure/macros/secure_port_macros.h @@ -0,0 +1,140 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_PORT_MACROS_H__ +#define __SECURE_PORT_MACROS_H__ + +/** + * @brief Byte alignment requirements. + */ +#define secureportBYTE_ALIGNMENT 8 +#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 ) + +/** + * @brief Macro to declare a function as non-secure callable. + */ +#if defined( __IAR_SYSTEMS_ICC__ ) + #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry __root +#else + #define secureportNON_SECURE_CALLABLE __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) ) +#endif + +/** + * @brief Set the secure PRIMASK value. + */ +#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Set the non-secure PRIMASK value. + */ +#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Read the PSP value in the given variable. + */ +#define secureportREAD_PSP( pucOutCurrentStackPointer ) \ + __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) ) + +/** + * @brief Set the PSP to the given value. + */ +#define secureportSET_PSP( pucCurrentStackPointer ) \ + __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) ) + +/** + * @brief Read the PSPLIM value in the given variable. + */ +#define secureportREAD_PSPLIM( pucOutStackLimit ) \ + __asm volatile ( "mrs %0, psplim" : "=r" ( pucOutStackLimit ) ) + +/** + * @brief Set the PSPLIM to the given value. + */ +#define secureportSET_PSPLIM( pucStackLimit ) \ + __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) ) + +/** + * @brief Set the NonSecure MSP to the given value. + */ +#define secureportSET_MSP_NS( pucMainStackPointer ) \ + __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) ) + +/** + * @brief Set the CONTROL register to the given value. + */ +#define secureportSET_CONTROL( ulControl ) \ + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" ) + +/** + * @brief Read the Interrupt Program Status Register (IPSR) value in the given + * variable. + */ +#define secureportREAD_IPSR( ulIPSR ) \ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) ) + +/** + * @brief PRIMASK value to enable interrupts. + */ +#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0 + +/** + * @brief PRIMASK value to disable interrupts. + */ +#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1 + +/** + * @brief Disable secure interrupts. + */ +#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Disable non-secure interrupts. + * + * This effectively disables context switches. + */ +#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Enable non-secure interrupts. + */ +#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL ) + +/** + * @brief Assert definition. + */ +#define secureportASSERT( x ) \ + if( ( x ) == 0 ) \ + { \ + secureportDISABLE_SECURE_INTERRUPTS(); \ + secureportDISABLE_NON_SECURE_INTERRUPTS(); \ + for( ; ; ) {; } \ + } + +#endif /* __SECURE_PORT_MACROS_H__ */ diff --git a/portable/BCC/16BitDOS/Flsh186/port.c b/portable/BCC/16BitDOS/Flsh186/port.c new file mode 100644 index 000000000..14b1f6f5a --- /dev/null +++ b/portable/BCC/16BitDOS/Flsh186/port.c @@ -0,0 +1,244 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* +Changes from V1.00: + + + Call to taskYIELD() from within tick ISR has been replaced by the more + efficient portSWITCH_CONTEXT(). + + ISR function definitions renamed to include the prv prefix. + +Changes from V2.6.1 + + + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION + macro to be consistent with the later ports. +*/ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the Flashlite 186 + * port. + *----------------------------------------------------------*/ + +#include +#include +#include + +#include "FreeRTOS.h" +#include "task.h" +#include "portasm.h" + +/*lint -e950 Non ANSI reserved words okay in this file only. */ + +#define portTIMER_EOI_TYPE ( 8 ) +#define portRESET_PIC() portOUTPUT_WORD( ( uint16_t ) 0xff22, portTIMER_EOI_TYPE ) +#define portTIMER_INT_NUMBER 0x12 + +#define portTIMER_1_CONTROL_REGISTER ( ( uint16_t ) 0xff5e ) +#define portTIMER_0_CONTROL_REGISTER ( ( uint16_t ) 0xff56 ) +#define portTIMER_INTERRUPT_ENABLE ( ( uint16_t ) 0x2000 ) + +/* Setup the hardware to generate the required tick frequency. */ +static void prvSetTickFrequency( uint32_t ulTickRateHz ); + +/* Set the hardware back to the state as per before the scheduler started. */ +static void prvExitFunction( void ); + +/* The ISR used depends on whether the preemptive or cooperative scheduler +is being used. */ +#if( configUSE_PREEMPTION == 1 ) + /* Tick service routine used by the scheduler when preemptive scheduling is + being used. */ + static void __interrupt __far prvPreemptiveTick( void ); +#else + /* Tick service routine used by the scheduler when cooperative scheduling is + being used. */ + static void __interrupt __far prvNonPreemptiveTick( void ); +#endif + +/* Trap routine used by taskYIELD() to manually cause a context switch. */ +static void __interrupt __far prvYieldProcessor( void ); + +/*lint -e956 File scopes necessary here. */ + +/* Set true when the vectors are set so the scheduler will service the tick. */ +static BaseType_t xSchedulerRunning = pdFALSE; + +/* Points to the original routine installed on the vector we use for manual +context switches. This is then used to restore the original routine during +prvExitFunction(). */ +static void ( __interrupt __far *pxOldSwitchISR )(); + +/* Used to restore the original DOS context when the scheduler is ended. */ +static jmp_buf xJumpBuf; + +/*lint +e956 */ + +/*-----------------------------------------------------------*/ +BaseType_t xPortStartScheduler( void ) +{ + /* This is called with interrupts already disabled. */ + + /* Remember what was on the interrupts we are going to use + so we can put them back later if required. */ + pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER ); + + /* Put our manual switch (yield) function on a known + vector. */ + _dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor ); + + #if( configUSE_PREEMPTION == 1 ) + { + /* Put our tick switch function on the timer interrupt. */ + _dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick ); + } + #else + { + /* We want the timer interrupt to just increment the tick count. */ + _dos_setvect( portTIMER_INT_NUMBER, prvNonPreemptiveTick ); + } + #endif + + prvSetTickFrequency( configTICK_RATE_HZ ); + + /* Clean up function if we want to return to DOS. */ + if( setjmp( xJumpBuf ) != 0 ) + { + prvExitFunction(); + xSchedulerRunning = pdFALSE; + } + else + { + xSchedulerRunning = pdTRUE; + + /* Kick off the scheduler by setting up the context of the first task. */ + portFIRST_CONTEXT(); + } + + return xSchedulerRunning; +} +/*-----------------------------------------------------------*/ + +/* The ISR used depends on whether the preemptive or cooperative scheduler +is being used. */ +#if( configUSE_PREEMPTION == 1 ) + static void __interrupt __far prvPreemptiveTick( void ) + { + /* Get the scheduler to update the task states following the tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Switch in the context of the next task to be run. */ + portSWITCH_CONTEXT(); + } + + /* Reset the PIC ready for the next time. */ + portRESET_PIC(); + } +#else + static void __interrupt __far prvNonPreemptiveTick( void ) + { + /* Same as preemptive tick, but the cooperative scheduler is being used + so we don't have to switch in the context of the next task. */ + xTaskIncrementTick(); + portRESET_PIC(); + } +#endif +/*-----------------------------------------------------------*/ + +static void __interrupt __far prvYieldProcessor( void ) +{ + /* Switch in the context of the next task to be run. */ + portSWITCH_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Jump back to the processor state prior to starting the + scheduler. This means we are not going to be using a + task stack frame so the task can be deleted. */ + longjmp( xJumpBuf, 1 ); +} +/*-----------------------------------------------------------*/ + +static void prvExitFunction( void ) +{ +const uint16_t usTimerDisable = 0x0000; +uint16_t usTimer0Control; + + /* Interrupts should be disabled here anyway - but no + harm in making sure. */ + portDISABLE_INTERRUPTS(); + if( xSchedulerRunning == pdTRUE ) + { + /* Put back the switch interrupt routines that was in place + before the scheduler started. */ + _dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR ); + } + + /* Disable the timer used for the tick to ensure the scheduler is + not called before restoring interrupts. There was previously nothing + on this timer so there is no old ISR to restore. */ + portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerDisable ); + + /* Restart the DOS tick. */ + usTimer0Control = portINPUT_WORD( portTIMER_0_CONTROL_REGISTER ); + usTimer0Control |= portTIMER_INTERRUPT_ENABLE; + portOUTPUT_WORD( portTIMER_0_CONTROL_REGISTER, usTimer0Control ); + + + portENABLE_INTERRUPTS(); +} +/*-----------------------------------------------------------*/ + +static void prvSetTickFrequency( uint32_t ulTickRateHz ) +{ +const uint16_t usMaxCountRegister = 0xff5a; +const uint16_t usTimerPriorityRegister = 0xff32; +const uint16_t usTimerEnable = 0xC000; +const uint16_t usRetrigger = 0x0001; +const uint16_t usTimerHighPriority = 0x0000; +uint16_t usTimer0Control; + +/* ( CPU frequency / 4 ) / clock 2 max count [inpw( 0xff62 ) = 7] */ + +const uint32_t ulClockFrequency = ( uint32_t ) 0x7f31a0UL; + +uint32_t ulTimerCount = ulClockFrequency / ulTickRateHz; + + portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerEnable | portTIMER_INTERRUPT_ENABLE | usRetrigger ); + portOUTPUT_WORD( usMaxCountRegister, ( uint16_t ) ulTimerCount ); + portOUTPUT_WORD( usTimerPriorityRegister, usTimerHighPriority ); + + /* Stop the DOS tick - don't do this if you want to maintain a TOD clock. */ + usTimer0Control = portINPUT_WORD( portTIMER_0_CONTROL_REGISTER ); + usTimer0Control &= ~portTIMER_INTERRUPT_ENABLE; + portOUTPUT_WORD( portTIMER_0_CONTROL_REGISTER, usTimer0Control ); +} + + +/*lint +e950 */ diff --git a/portable/BCC/16BitDOS/Flsh186/prtmacro.h b/portable/BCC/16BitDOS/Flsh186/prtmacro.h new file mode 100644 index 000000000..b1b5c26eb --- /dev/null +++ b/portable/BCC/16BitDOS/Flsh186/prtmacro.h @@ -0,0 +1,99 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE long +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE uint16_t +#define portBASE_TYPE portSHORT + +typedef portSTACK_TYPE StackType_t; +typedef short BaseType_t; +typedef unsigned short UBaseType_t; + +#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +#define portENTER_CRITICAL() __asm{ pushf } \ + __asm{ cli } \ + +#define portEXIT_CRITICAL() __asm{ popf } + +#define portDISABLE_INTERRUPTS() __asm{ cli } + +#define portENABLE_INTERRUPTS() __asm{ sti } +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portNOP() __asm{ nop } +#define portSTACK_GROWTH ( -1 ) +#define portSWITCH_INT_NUMBER 0x80 +#define portYIELD() __asm{ int portSWITCH_INT_NUMBER } +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 2 +#define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */ +/*-----------------------------------------------------------*/ + +/* Compiler specifics. */ +#define portINPUT_BYTE( xAddr ) inp( xAddr ) +#define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue ) +#define portINPUT_WORD( xAddr ) inpw( xAddr ) +#define portOUTPUT_WORD( xAddr, usValue ) outpw( xAddr, usValue ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters ) +#define portTASK_FUNCTION( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters ) + +#endif /* PORTMACRO_H */ diff --git a/portable/BCC/16BitDOS/PC/port.c b/portable/BCC/16BitDOS/PC/port.c new file mode 100644 index 000000000..0c1c0644e --- /dev/null +++ b/portable/BCC/16BitDOS/PC/port.c @@ -0,0 +1,288 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* +Changes from V2.6.1 + + + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION + macro to be consistent with the later ports. + +Changes from V4.0.1 + + + Add function prvSetTickFrequencyDefault() to set the DOS tick back to + its proper value when the scheduler exits. +*/ + +#include +#include +#include + +#include "FreeRTOS.h" +#include "task.h" +#include "portasm.h" + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the industrial + * PC port. + *----------------------------------------------------------*/ + +/*lint -e950 Non ANSI reserved words okay in this file only. */ + +#define portTIMER_INT_NUMBER 0x08 + +/* Setup hardware for required tick interrupt rate. */ +static void prvSetTickFrequency( uint32_t ulTickRateHz ); + +/* Restore hardware to as it was prior to starting the scheduler. */ +static void prvExitFunction( void ); + +/* Either chain to the DOS tick (which itself clears the PIC) or clear the PIC +directly. We chain to the DOS tick as close as possible to the standard DOS +tick rate. */ +static void prvPortResetPIC( void ); + +/* The ISR used depends on whether the preemptive or cooperative +scheduler is being used. */ +#if( configUSE_PREEMPTION == 1 ) + /* Tick service routine used by the scheduler when preemptive scheduling is + being used. */ + static void __interrupt __far prvPreemptiveTick( void ); +#else + /* Tick service routine used by the scheduler when cooperative scheduling is + being used. */ + static void __interrupt __far prvNonPreemptiveTick( void ); +#endif + +/* Trap routine used by taskYIELD() to manually cause a context switch. */ +static void __interrupt __far prvYieldProcessor( void ); + +/* Set the tick frequency back so the floppy drive works correctly when the +scheduler exits. */ +static void prvSetTickFrequencyDefault( void ); + +/*lint -e956 File scopes necessary here. */ + +/* Used to signal when to chain to the DOS tick, and when to just clear the PIC ourselves. */ +static int16_t sDOSTickCounter; + +/* Set true when the vectors are set so the scheduler will service the tick. */ +static BaseType_t xSchedulerRunning = pdFALSE; + +/* Points to the original routine installed on the vector we use for manual context switches. This is then used to restore the original routine during prvExitFunction(). */ +static void ( __interrupt __far *pxOldSwitchISR )(); + +/* Points to the original routine installed on the vector we use to chain to the DOS tick. This is then used to restore the original routine during prvExitFunction(). */ +static void ( __interrupt __far *pxOldSwitchISRPlus1 )(); + +/* Used to restore the original DOS context when the scheduler is ended. */ +static jmp_buf xJumpBuf; + +/*lint +e956 */ + +/*-----------------------------------------------------------*/ +BaseType_t xPortStartScheduler( void ) +{ +pxISR pxOriginalTickISR; + + /* This is called with interrupts already disabled. */ + + /* Remember what was on the interrupts we are going to use + so we can put them back later if required. */ + pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER ); + pxOriginalTickISR = _dos_getvect( portTIMER_INT_NUMBER ); + pxOldSwitchISRPlus1 = _dos_getvect( portSWITCH_INT_NUMBER + 1 ); + + prvSetTickFrequency( configTICK_RATE_HZ ); + + /* Put our manual switch (yield) function on a known + vector. */ + _dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor ); + + /* Put the old tick on a different interrupt number so we can + call it when we want. */ + _dos_setvect( portSWITCH_INT_NUMBER + 1, pxOriginalTickISR ); + + /* The ISR used depends on whether the preemptive or cooperative + scheduler is being used. */ + #if( configUSE_PREEMPTION == 1 ) + { + /* Put our tick switch function on the timer interrupt. */ + _dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick ); + } + #else + { + /* We want the timer interrupt to just increment the tick count. */ + _dos_setvect( portTIMER_INT_NUMBER, prvNonPreemptiveTick ); + } + #endif + + /* Setup a counter that is used to call the DOS interrupt as close + to it's original frequency as can be achieved given our chosen tick + frequency. */ + sDOSTickCounter = portTICKS_PER_DOS_TICK; + + /* Clean up function if we want to return to DOS. */ + if( setjmp( xJumpBuf ) != 0 ) + { + prvExitFunction(); + xSchedulerRunning = pdFALSE; + } + else + { + xSchedulerRunning = pdTRUE; + + /* Kick off the scheduler by setting up the context of the first task. */ + portFIRST_CONTEXT(); + } + + return xSchedulerRunning; +} +/*-----------------------------------------------------------*/ + +/* The ISR used depends on whether the preemptive or cooperative +scheduler is being used. */ +#if( configUSE_PREEMPTION == 1 ) + static void __interrupt __far prvPreemptiveTick( void ) + { + /* Get the scheduler to update the task states following the tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Switch in the context of the next task to be run. */ + portSWITCH_CONTEXT(); + } + + /* Reset the PIC ready for the next time. */ + prvPortResetPIC(); + } +#else + static void __interrupt __far prvNonPreemptiveTick( void ) + { + /* Same as preemptive tick, but the cooperative scheduler is being used + so we don't have to switch in the context of the next task. */ + xTaskIncrementTick(); + prvPortResetPIC(); + } +#endif +/*-----------------------------------------------------------*/ + +static void __interrupt __far prvYieldProcessor( void ) +{ + /* Switch in the context of the next task to be run. */ + portSWITCH_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +static void prvPortResetPIC( void ) +{ + /* We are going to call the DOS tick interrupt at as close a + frequency to the normal DOS tick as possible. */ + + /* WE SHOULD NOT DO THIS IF YIELD WAS CALLED. */ + --sDOSTickCounter; + if( sDOSTickCounter <= 0 ) + { + sDOSTickCounter = ( int16_t ) portTICKS_PER_DOS_TICK; + __asm{ int portSWITCH_INT_NUMBER + 1 }; + } + else + { + /* Reset the PIC as the DOS tick is not being called to + do it. */ + __asm + { + mov al, 20H + out 20H, al + }; + } +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Jump back to the processor state prior to starting the + scheduler. This means we are not going to be using a + task stack frame so the task can be deleted. */ + longjmp( xJumpBuf, 1 ); +} +/*-----------------------------------------------------------*/ + +static void prvExitFunction( void ) +{ +void ( __interrupt __far *pxOriginalTickISR )(); + + /* Interrupts should be disabled here anyway - but no + harm in making sure. */ + portDISABLE_INTERRUPTS(); + if( xSchedulerRunning == pdTRUE ) + { + /* Set the DOS tick back onto the timer ticker. */ + pxOriginalTickISR = _dos_getvect( portSWITCH_INT_NUMBER + 1 ); + _dos_setvect( portTIMER_INT_NUMBER, pxOriginalTickISR ); + prvSetTickFrequencyDefault(); + + /* Put back the switch interrupt routines that was in place + before the scheduler started. */ + _dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR ); + _dos_setvect( portSWITCH_INT_NUMBER + 1, pxOldSwitchISRPlus1 ); + } + /* The tick timer is back how DOS wants it. We can re-enable + interrupts without the scheduler being called. */ + portENABLE_INTERRUPTS(); +} +/*-----------------------------------------------------------*/ + +static void prvSetTickFrequency( uint32_t ulTickRateHz ) +{ +const uint16_t usPIT_MODE = ( uint16_t ) 0x43; +const uint16_t usPIT0 = ( uint16_t ) 0x40; +const uint32_t ulPIT_CONST = ( uint32_t ) 1193180UL; +const uint16_t us8254_CTR0_MODE3 = ( uint16_t ) 0x36; +uint32_t ulOutput; + + /* Setup the 8245 to tick at the wanted frequency. */ + portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 ); + ulOutput = ulPIT_CONST / ulTickRateHz; + portOUTPUT_BYTE( usPIT0, ( uint16_t )( ulOutput & ( uint32_t ) 0xff ) ); + ulOutput >>= 8; + portOUTPUT_BYTE( usPIT0, ( uint16_t ) ( ulOutput & ( uint32_t ) 0xff ) ); +} +/*-----------------------------------------------------------*/ + +static void prvSetTickFrequencyDefault( void ) +{ +const uint16_t usPIT_MODE = ( uint16_t ) 0x43; +const uint16_t usPIT0 = ( uint16_t ) 0x40; +const uint16_t us8254_CTR0_MODE3 = ( uint16_t ) 0x36; + + portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 ); + portOUTPUT_BYTE( usPIT0,0 ); + portOUTPUT_BYTE( usPIT0,0 ); +} + + +/*lint +e950 */ diff --git a/portable/BCC/16BitDOS/PC/prtmacro.h b/portable/BCC/16BitDOS/PC/prtmacro.h new file mode 100644 index 000000000..d24431806 --- /dev/null +++ b/portable/BCC/16BitDOS/PC/prtmacro.h @@ -0,0 +1,99 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT long +#define portDOUBLE long +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE uint16_t +#define portBASE_TYPE portSHORT + +typedef portSTACK_TYPE StackType_t; +typedef short BaseType_t; +typedef unsigned short UBaseType_t; + +#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +#define portENTER_CRITICAL() __asm{ pushf } \ + __asm{ cli } \ + +#define portEXIT_CRITICAL() __asm{ popf } + +#define portDISABLE_INTERRUPTS() __asm{ cli } + +#define portENABLE_INTERRUPTS() __asm{ sti } +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portNOP() __asm{ nop } +#define portSTACK_GROWTH ( -1 ) +#define portSWITCH_INT_NUMBER 0x80 +#define portYIELD() __asm{ int portSWITCH_INT_NUMBER } +#define portDOS_TICK_RATE ( 18.20648 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portTICKS_PER_DOS_TICK ( ( uint16_t ) ( ( ( portDOUBLE ) configTICK_RATE_HZ / portDOS_TICK_RATE ) + 0.5 ) ) +#define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */ +#define portBYTE_ALIGNMENT ( 2 ) +/*-----------------------------------------------------------*/ + +/* Compiler specifics. */ +#define portINPUT_BYTE( xAddr ) inp( xAddr ) +#define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters ) +#define portTASK_FUNCTION( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters ) + +#endif /* PORTMACRO_H */ diff --git a/portable/BCC/16BitDOS/common/portasm.h b/portable/BCC/16BitDOS/common/portasm.h new file mode 100644 index 000000000..3e3acf0bd --- /dev/null +++ b/portable/BCC/16BitDOS/common/portasm.h @@ -0,0 +1,87 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORT_ASM_H +#define PORT_ASM_H + +typedef void TCB_t; +extern volatile TCB_t * volatile pxCurrentTCB; +extern void vTaskSwitchContext( void ); + +/* + * Saves the stack pointer for one task into its TCB, calls + * vTaskSwitchContext() to update the TCB being used, then restores the stack + * from the new TCB read to run the task. + */ +void portSWITCH_CONTEXT( void ); + +/* + * Load the stack pointer from the TCB of the task which is going to be first + * to execute. Then force an IRET so the registers and IP are popped off the + * stack. + */ +void portFIRST_CONTEXT( void ); + +/* There are slightly different versions depending on whether you are building +to include debugger information. If debugger information is used then there +are a couple of extra bytes left of the ISR stack (presumably for use by the +debugger). The true stack pointer is then stored in the bp register. We add +2 to the stack pointer to remove the extra bytes before we restore our context. */ + +#define portSWITCH_CONTEXT() \ + asm { mov ax, seg pxCurrentTCB } \ + asm { mov ds, ax } \ + asm { les bx, pxCurrentTCB } /* Save the stack pointer into the TCB. */ \ + asm { mov es:0x2[ bx ], ss } \ + asm { mov es:[ bx ], sp } \ + asm { call far ptr vTaskSwitchContext } /* Perform the switch. */ \ + asm { mov ax, seg pxCurrentTCB } /* Restore the stack pointer from the TCB. */ \ + asm { mov ds, ax } \ + asm { les bx, dword ptr pxCurrentTCB } \ + asm { mov ss, es:[ bx + 2 ] } \ + asm { mov sp, es:[ bx ] } + +#define portFIRST_CONTEXT() \ + __asm { mov ax, seg pxCurrentTCB } \ + __asm { mov ds, ax } \ + __asm { les bx, dword ptr pxCurrentTCB } \ + __asm { mov ss, es:[ bx + 2 ] } \ + __asm { mov sp, es:[ bx ] } \ + __asm { pop bp } \ + __asm { pop di } \ + __asm { pop si } \ + __asm { pop ds } \ + __asm { pop es } \ + __asm { pop dx } \ + __asm { pop cx } \ + __asm { pop bx } \ + __asm { pop ax } \ + __asm { iret } + + +#endif diff --git a/portable/BCC/16BitDOS/common/portcomn.c b/portable/BCC/16BitDOS/common/portcomn.c new file mode 100644 index 000000000..0e1bca1ab --- /dev/null +++ b/portable/BCC/16BitDOS/common/portcomn.c @@ -0,0 +1,120 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* +Changes from V1.00: + + + pxPortInitialiseStack() now initialises the stack of new tasks to the + same format used by the compiler. This allows the compiler generated + interrupt mechanism to be used for context switches. + +Changes from V2.6.1 + + + Move usPortCheckFreeStackSpace() to tasks.c. +*/ + + +#include +#include +#include "FreeRTOS.h" + +/*-----------------------------------------------------------*/ + +/* See header file for description. */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +StackType_t DS_Reg = 0; + + /* Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging. */ + + *pxTopOfStack = 0x1111; + pxTopOfStack--; + *pxTopOfStack = 0x2222; + pxTopOfStack--; + *pxTopOfStack = 0x3333; + pxTopOfStack--; + *pxTopOfStack = 0x4444; + pxTopOfStack--; + *pxTopOfStack = 0x5555; + pxTopOfStack--; + + + /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */ + + /* We are going to start the scheduler using a return from interrupt + instruction to load the program counter, so first there would be the + function call with parameters preamble. */ + + *pxTopOfStack = FP_SEG( pvParameters ); + pxTopOfStack--; + *pxTopOfStack = FP_OFF( pvParameters ); + pxTopOfStack--; + *pxTopOfStack = FP_SEG( pxCode ); + pxTopOfStack--; + *pxTopOfStack = FP_OFF( pxCode ); + pxTopOfStack--; + + /* Next the status register and interrupt return address. */ + *pxTopOfStack = portINITIAL_SW; + pxTopOfStack--; + *pxTopOfStack = FP_SEG( pxCode ); + pxTopOfStack--; + *pxTopOfStack = FP_OFF( pxCode ); + pxTopOfStack--; + + /* The remaining registers would be pushed on the stack by our context + switch function. These are loaded with values simply to make debugging + easier. */ + *pxTopOfStack = ( StackType_t ) 0xAAAA; /* AX */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xBBBB; /* BX */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xCCCC; /* CX */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xDDDD; /* DX */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xEEEE; /* ES */ + pxTopOfStack--; + + /* We need the true data segment. */ + __asm{ MOV DS_Reg, DS }; + + *pxTopOfStack = DS_Reg; /* DS */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x0123; /* SI */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xDDDD; /* DI */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xBBBB; /* BP */ + + /*lint +e950 +e611 +e923 */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ diff --git a/portable/CCRH/F1Kx/README.md b/portable/CCRH/F1Kx/README.md new file mode 100644 index 000000000..4cb9f07b6 --- /dev/null +++ b/portable/CCRH/F1Kx/README.md @@ -0,0 +1,46 @@ +# RH850/F1K and F1Kx FreeRTOS Port with CC-RH Compiler + +## Introduction + +This repository contains the port of FreeRTOS for Renesas RH850/F1K and F1Kx microcontrollers using the CC-RH compiler. The following sections provide instructions on how to use this port, a link to the test project, and other relevant information. + +## Prerequisites +- Compiler: CC-RH +- FreeRTOS version 11.1.0 + +| Device | FPU | SMP | +|----------|-----|-----| +| F1K | Yes | No | +| F1KM-S1 | Yes | No | +| F1KM-S2 | Yes | No | +| F1KM-S4 | Yes | No | +| F1KH-D8 | Yes | Yes | + +## Link to Test Project + +The test project can be found [here](https://github.com/FreeRTOS/FreeRTOS-Community-Supported-Demos) (`RH850_F1Kx_CCRH`). This project contains example tasks and configurations to help you get started with FreeRTOS on the RH850/F1K and F1Kx. + +## Note + 1. Configure IPIR Interrupt: Ensure that the bit specifying the destination for binding (requesting) an interrupt is enabled (e.g: IBDxxx register of F1KH-D8) (1) + 2. `Channel 0` and address `0xFFFEEC00` are used as default configuration for configIPIR_CHANNEL and configEXCLUSIVE_ADDRESS, in case of resource confliction other channel/address can be used. (2) + 3. The minimal stack size (configMINIMAL_STACK_SIZE) must be included the reserved memory for nested interrupt. This formula can be referred: `(task_context_size) * (2 + configMAX_INT_NESTING) + Stack_depth_of_taskcode` + In which, `task_context_size` is calculated as `36*4bytes = 144bytes` (when FPU enabled) or `34*4bytes = 136` (when FPU disabled), configMAX_INT_NESTING is `02` as default (Note that a value of `0` is not allowed). + 4. `configTIMER_PRESCALE`: This value is required in order to correctly configure clock for `CPUCLK_L`. Refer to Hardware Manual at `Table 44.22` for `option byte`: If the user sets the option byte `CKDIVMD to 1`, then `configTIMER_PRESCALE = 4`. Otherwise, if `CKDIVMD is set to 0`, then `configTIMER_PRESCALE = 2`. + +(1) This is applicable for F1KH-D8 with SMP only. + +(2) This is optional and applicable for SMP only. + +## Other Relevant Information + +- **Documentation:** + - Refer to the official [FreeRTOS documentation](https://www.freertos.org/Documentation/RTOS_book.html) for detailed information on configuring and using FreeRTOS. + - Consult the [RH850 F1K group user manual hardware manual](https://www.renesas.com/us/en/document/mah/rh850f1k-group-users-manual-hardware?r=1170166) for specific details about the microcontroller. + - For more information about Renesas RH850/F1K and F1Kx, please visit [this website](https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rh850-automotive-mcus) + - The CC-RH compiler can be downloaded [here](https://www.renesas.com/us/en/software-tool/c-compiler-package-rh850-family#downloads) + +- **Support:** + - If you encounter any issues or have questions about this port, please open an issue in this repository or contact the maintainer. + +- **Contributing:** + - Contributions to improve this port are welcome. Please fork the repository, make your changes, and submit a pull request. \ No newline at end of file diff --git a/portable/CCRH/F1Kx/port.c b/portable/CCRH/F1Kx/port.c new file mode 100644 index 000000000..3a43ff418 --- /dev/null +++ b/portable/CCRH/F1Kx/port.c @@ -0,0 +1,732 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* This port uses xTaskGetCurrentTaskHandle to get TCB stack, it is required to + * enable this API. */ +#if ( ( INCLUDE_xTaskGetCurrentTaskHandle != 1 ) && ( configNUMBER_OF_CORES == 1 ) ) + #error INCLUDE_xTaskGetCurrentTaskHandle must be set to 1 in single core. +#endif + +/*********************************************************** +* Macro definitions +***********************************************************/ + +/* Hardware specific macros */ +#define portPSW_REGISTER_ID ( 5 ) +#define portFPSR_REGISTER_ID ( 6 ) + +/* PSW.EBV and PSW.CUx bits are kept as current status */ +#define portINITIAL_PSW_MASK ( 0x000f8000 ) +#define portCURRENT_PSW_VALUE ( portSTSR( portPSW_REGISTER_ID ) ) +#define portCURRENT_SR_ZERO_VALUE ( ( StackType_t ) 0x00000000 ) +#define portCURRENT_FPSR_VALUE ( portSTSR( portFPSR_REGISTER_ID ) ) + +/* Mask for FPU configuration bits (FN, PEM, RM, FS) */ +#define portINITIAL_FPSR_MASK ( 0x00ae0000 ) +#define portPSW_ID_MASK ( 0x00000020 ) + +/* Define necessary hardware IO for OSTM timer. OSTM0 is used by default as + * it is common for almost device variants. If it conflicts with application, + * the application shall implement another timer.*/ +#define portOSTM_EIC_ADDR ( 0xFFFFB0A8 ) +#define portOSTM0CMP_ADDR ( 0xFFD70000 ) +#define portOSTM0CTL_ADDR ( 0xFFD70020 ) +#define portOSTM0TS_ADDR ( 0xFFD70014 ) + +#if ( configNUMBER_OF_CORES > 1 ) + +/* IPIR base address, the peripheral is used for Inter-Processor communication + * Hardware supports 4 channels which is offset by 0x0, 0x4, 0x8, 0xC bytes from + * base address. By default, channel 0 is selected. */ + #ifdef configIPIR_CHANNEL + #define portIPIR_BASE_ADDR ( ( 0xFFFEEC80 ) + ( configIPIR_CHANNEL << 2 ) ) + #else + #define portIPIR_BASE_ADDR ( 0xFFFEEC80 ) + #endif + +/* Address used for exclusive control for variable shared between PEs + * (common resources), each CPU cores have independent access path to + * this address. By default, G0MEV0 register is selected*/ + #ifdef configEXCLUSIVE_ADDRESS + #define portMEV_BASE_ADDR configEXCLUSIVE_ADDRESS + #else + #define portMEV_BASE_ADDR ( 0xFFFEEC00 ) + #endif +#endif /* if ( configNUMBER_OF_CORES > 1 ) */ + +/* Macros required to set up the initial stack. */ +#define portSTACK_INITIAL_VALUE_R1 ( ( StackType_t ) 0x01010101 ) +#define portSTACK_INITIAL_VALUE_R2 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x02 ) +#define portSTACK_INITIAL_VALUE_R3 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x03 ) +#define portSTACK_INITIAL_VALUE_R4 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x04 ) +#define portSTACK_INITIAL_VALUE_R5 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x05 ) +#define portSTACK_INITIAL_VALUE_R6 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x06 ) +#define portSTACK_INITIAL_VALUE_R7 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x07 ) +#define portSTACK_INITIAL_VALUE_R8 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x08 ) +#define portSTACK_INITIAL_VALUE_R9 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x09 ) +#define portSTACK_INITIAL_VALUE_R10 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x10 ) +#define portSTACK_INITIAL_VALUE_R11 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x11 ) +#define portSTACK_INITIAL_VALUE_R12 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x12 ) +#define portSTACK_INITIAL_VALUE_R13 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x13 ) +#define portSTACK_INITIAL_VALUE_R14 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x14 ) +#define portSTACK_INITIAL_VALUE_R15 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x15 ) +#define portSTACK_INITIAL_VALUE_R16 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x16 ) +#define portSTACK_INITIAL_VALUE_R17 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x17 ) +#define portSTACK_INITIAL_VALUE_R18 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x18 ) +#define portSTACK_INITIAL_VALUE_R19 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x19 ) +#define portSTACK_INITIAL_VALUE_R20 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x20 ) +#define portSTACK_INITIAL_VALUE_R21 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x21 ) +#define portSTACK_INITIAL_VALUE_R22 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x22 ) +#define portSTACK_INITIAL_VALUE_R23 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x23 ) +#define portSTACK_INITIAL_VALUE_R24 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x24 ) +#define portSTACK_INITIAL_VALUE_R25 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x25 ) +#define portSTACK_INITIAL_VALUE_R26 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x26 ) +#define portSTACK_INITIAL_VALUE_R27 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x27 ) +#define portSTACK_INITIAL_VALUE_R28 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x28 ) +#define portSTACK_INITIAL_VALUE_R29 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x29 ) +#define portSTACK_INITIAL_VALUE_R30 ( ( StackType_t ) portSTACK_INITIAL_VALUE_R1 * 0x30 ) + +/*********************************************************** +* Typedef definitions +***********************************************************/ + +/* OSTM Count Start Trigger Register (OSTMnTS) */ +#define portOSTM_COUNTER_START ( 0x01U ) /* Starts the counter */ + +/* OSTM Count Stop Trigger Register (OSTMnTT) */ +#define portOSTM_COUNTER_STOP ( 0x01U ) /* Stops the counter */ + +/* OSTM Control Register (OSTMnCTL) */ +#define portOSTM_MODE_INTERVAL_TIMER ( 0x00U ) +#define portOSTM_MODE_FREE_RUNNING ( 0x02U ) + +/* Disables or Enable the interrupts when counting starts */ +#define portOSTM_START_INTERRUPT_DISABLE ( 0x00U ) +#define portOSTM_START_INTERRUPT_ENABLE ( 0x01U ) + +/* Interrupt vector method select (TBxxx) */ +#define portINT_DIRECT_VECTOR ( 0x0U ) +#define portINT_TABLE_VECTOR ( 0x1U ) + +/* Interrupt mask (MKxxx) */ +#define portINT_PROCESSING_ENABLED ( 0x0U ) +#define portINT_PROCESSING_DISABLED ( 0x1U ) + +/* Specify 16 interrupt priority levels */ +#define portINT_PRIORITY_HIGHEST ( 0x0000U ) /* Level 0 (highest) */ +#define portINT_PRIORITY_LEVEL1 ( 0x0001U ) /* Level 1 */ +#define portINT_PRIORITY_LEVEL2 ( 0x0002U ) /* Level 2 */ +#define portINT_PRIORITY_LEVEL3 ( 0x0003U ) /* Level 3 */ +#define portINT_PRIORITY_LEVEL4 ( 0x0004U ) /* Level 4 */ +#define portINT_PRIORITY_LEVEL5 ( 0x0005U ) /* Level 5 */ +#define portINT_PRIORITY_LEVEL6 ( 0x0006U ) /* Level 6 */ +#define portINT_PRIORITY_LEVEL7 ( 0x0007U ) /* Level 7 */ +#define portINT_PRIORITY_LEVEL8 ( 0x0008U ) /* Level 8 */ +#define portINT_PRIORITY_LEVEL9 ( 0x0009U ) /* Level 9 */ +#define portINT_PRIORITY_LEVEL10 ( 0x000AU ) /* Level 10 */ +#define portINT_PRIORITY_LEVEL11 ( 0x000BU ) /* Level 11 */ +#define portINT_PRIORITY_LEVEL12 ( 0x000CU ) /* Level 12 */ +#define portINT_PRIORITY_LEVEL13 ( 0x000DU ) /* Level 13 */ +#define portINT_PRIORITY_LEVEL14 ( 0x000EU ) /* Level 14 */ +#define portINT_PRIORITY_LOWEST ( 0x000FU ) /* Level 15 (lowest) */ + +/* Macros indicating status of scheduler request */ +#define PORT_SCHEDULER_NOREQUEST 0UL +#define PORT_SCHEDULER_TASKSWITCH 1UL /* Do not modify */ +#define PORT_SCHEDULER_STARTFIRSTTASK 2UL /* Do not modify */ + +#ifndef configSETUP_TICK_INTERRUPT + +/* The user has not provided their own tick interrupt configuration so use + * the definition in this file (which uses the interval timer). */ + #define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt() +#endif /* configSETUP_TICK_INTERRUPT */ + +#if ( !defined( configMAX_INT_NESTING ) || ( configMAX_INT_NESTING == 0 ) ) + +/* Set the default value for depth of nested interrupt. In theory, the + * microcontroller have mechanism to limit number of nested level of interrupt + * by priority (maximum 16 levels). However, the large stack memory should be + * prepared for each task to save resource in interrupt handler. Therefore, it + * is necessary to limit depth of nesting interrupt to optimize memory usage. + * In addition, the execution time of interrupt handler should be very short + * (typically not exceed 20us), this constraint does not impact to system. + */ + #define configMAX_INT_NESTING 2UL +#endif + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/* + * Sets up the periodic ISR used for the RTOS tick using the OSTM. + * The application writer can define configSETUP_TICK_INTERRUPT() (in + * FreeRTOSConfig.h) such that their own tick interrupt configuration is used + * in place of prvSetupTimerInterrupt(). + */ +static void prvSetupTimerInterrupt( void ); + +#if ( configNUMBER_OF_CORES > 1 ) + +/* + * Functions implement spin-lock between cores by atomic accesses to Exclusive + * Control Register (G0MEVm). There are separated access path between CPU cores, + * but they should wait if access to same register + */ + static void prvExclusiveLock( BaseType_t xFromIsr ); + static void prvExclusiveRelease( BaseType_t xFromIsr ); + +#endif + +/* + * Function to start the first task executing + */ +extern void vPortStartFirstTask( void ); + +/* Scheduler request on each cores which are starting first task and switching + * context */ +volatile BaseType_t xPortScheduleStatus[ configNUMBER_OF_CORES ] = { 0 }; + +/* Counts the interrupt nesting depth. A context switch is only performed if + * the nesting depth is 0. In addition, the interrupt shares same stack + * allocated for each tasks. With supporting nesting interrupt, the stack + * may be overflowed. + * It is necessary to control maximum stack depth. + */ +volatile UBaseType_t uxInterruptNesting[ configNUMBER_OF_CORES ] = { 0 }; +volatile const UBaseType_t uxPortMaxInterruptDepth = configMAX_INT_NESTING; + +/* Count number of nested locks by same cores. The lock is completely released + * only if this count is decreased to 0, the lock is separated for task + * and isr */ +UBaseType_t uxLockNesting[ configNUMBER_OF_CORES ][ 2 ] = { 0 }; + +#if ( configNUMBER_OF_CORES > 1 ) + +/* Pointer to exclusive access memory */ + volatile BaseType_t * pxPortExclusiveReg = ( volatile BaseType_t * ) ( portMEV_BASE_ADDR ); +#endif + +/* Interrupt handler for OSTM timer which handling tick increment and resulting + * to switch context. */ +void vPortTickISR( void ); + +#if ( configNUMBER_OF_CORES > 1 ) + +/* Yield specific cores by send inter-processor interrupt */ + void vPortYieldCore( uint32_t xCoreID ); + +/* + * Inter-processor interrupt handler. The interrupt is triggered by + * portYIELD_CORE(). + */ + void vPortIPIHander( void ); + +/* These functions below implement recursive spinlock for exclusive access among + * cores. The core will wait until lock will be available, whilst the core which + * already had lock can acquire lock without waiting. This function could be + * call from task and interrupt context, the critical section is called + * as in ISR */ + void vPortRecursiveLockAcquire( BaseType_t xCoreID, BaseType_t xFromIsr ); + void vPortRecursiveLockRelease( BaseType_t xCoreID, BaseType_t xFromIsr ); + +#endif /* (configNUMBER_OF_CORES > 1) */ + +/*-----------------------------------------------------------*/ + +/* + * These below functions implement interrupt mask from interrupt. They are not + * called in nesting, it is protected by FreeRTOS kernel. + */ +portLONG xPortSetInterruptMask( void ) +{ + portLONG ulPSWValue = portSTSR( portPSW_REGISTER_ID ); + + portDISABLE_INTERRUPTS(); + + /* It returns current value of Program Status Word register */ + return ulPSWValue; +} + +/*-----------------------------------------------------------*/ + +void vPortClearInterruptMask( portLONG uxSavedInterruptStatus ) +{ + portLONG ulPSWValue = portSTSR( portPSW_REGISTER_ID ); + + /* Interrupt Disable status is indicates by bit#5 of PSW + * (1: Interrupt is disabled; 0: Interrupt is enabled) */ + + /* Revert to the status before interrupt mask. */ + ulPSWValue &= ( ~( portPSW_ID_MASK ) ); + ulPSWValue |= ( portPSW_ID_MASK & uxSavedInterruptStatus ); + portLDSR( portPSW_REGISTER_ID, ulPSWValue ); +} + +/*-----------------------------------------------------------*/ + +/* + * Using CC-RH intrinsic function to get HTCFG0 (regID, selID) = (0,2) + * Core ID is indicates by bit HTCFG0.PEID located at bit 18 to 16 + * Bit 31 to 19 are read only and always be read as 0. HTCFG0.PEID is 1 and 2 + * corresponding to core 0 (PE1) and core 1 (PE2). It is adjusted to 0 and 1. + */ +BaseType_t xPortGET_CORE_ID( void ) +{ + #if ( configNUMBER_OF_CORES > 1 ) + return ( portSTSR_CCRH( 0, 2 ) >> 16 ) - 1; + #else + + /* In single core, xPortGET_CORE_ID is used in this port only. + * The dummy core ID could be controlled inside this port. */ + return 0; + #endif +} + +/*-----------------------------------------------------------*/ + +/* + * This port supports both multi-cores and single-core, whilst TCB stack + * variables are different which are respectively pxCurrentTCB (single-core) + * and pxCurrentTCBs[] (multiple-cores). This function is defined to obtains + * TCBs of current cores. Also, the C function could switch to corresponding + * pointer by pre-compile conditions. + */ +void * pvPortGetCurrentTCB( void ) +{ + void * pvCurrentTCB = ( void * ) xTaskGetCurrentTaskHandle(); + + configASSERT( pvCurrentTCB != NULL ); + + return pvCurrentTCB; +} + +/*-----------------------------------------------------------*/ + +/* + * This function checks if a context switch is required and, if so, updates + * the scheduler status for the core on which the function is called. The + * scheduler status is set to indicate that a task switch should occur. + */ +void vPortSetSwitch( BaseType_t xSwitchRequired ) +{ + if( xSwitchRequired != pdFALSE ) + { + xPortScheduleStatus[ xPortGET_CORE_ID() ] = PORT_SCHEDULER_TASKSWITCH; + } +} + +/*-----------------------------------------------------------*/ + +/* + * Setup the stack of a new task so it is ready to be placed under the + * scheduler control. The registers have to be placed on the stack in the + * order that the port expects to find them. + * + * @param[in] pxTopOfStack Pointer to top of this task's stack + * @param[in] pxCode Task function, stored as initial PC for the task + * @param[in] pvParameters Parameters for task + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Simulate the stack frame as it would be created by + * a context switch interrupt. */ + *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* R31 (LP) */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R5; /* R5 (TP) */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R7; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R8; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R9; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R10; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R11; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R12; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R13; /* R13 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R14; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R15; /* R15 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R16; /* R16 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R17; /* R17 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R18; /* R18 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R19; /* R19 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R20; /* R20 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R21; /* R21 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R22; /* R22 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R23; /* R23 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R24; /* R24 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R25; /* R25 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R26; /* R26 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R27; /* R27 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R28; /* R28 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R29; /* R29 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R30; /* R30 (EP) */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R1; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portSTACK_INITIAL_VALUE_R2; /* R2 */ + + pxTopOfStack--; + + /* Keep System pre-configuration (HV, CUx, EBV) as current setting in + * PSW register */ + *pxTopOfStack = ( StackType_t ) ( portCURRENT_PSW_VALUE & portINITIAL_PSW_MASK ); /* EIPSW */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* EIPC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portCURRENT_SR_ZERO_VALUE; /* EIIC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) ( portCURRENT_PSW_VALUE & portINITIAL_PSW_MASK ); /* CTPSW */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portCURRENT_SR_ZERO_VALUE; /* CTPC */ + +/* __FPU is defined by CCRH compiler if FPU is enabled */ + #if ( configENABLE_FPU == 1 ) + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) ( portCURRENT_FPSR_VALUE & portINITIAL_FPSR_MASK ); /* FPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portCURRENT_SR_ZERO_VALUE; /* FPEPC */ + #endif /* (configENABLE_FPU == 1) */ + + return pxTopOfStack; +} + +/*-----------------------------------------------------------*/ + +/* + * Configures the tick frequency and starts the first task. + */ +BaseType_t xPortStartScheduler( void ) +{ + #if ( configNUMBER_OF_CORES > 1 ) + BaseType_t xCurrentCore = xPortGET_CORE_ID(); + #endif + + /* Prevent interrupt by timer interrupt during starting first task. + * The interrupt shall be enabled automatically by being restored from + * task stack */ + portDISABLE_INTERRUPTS(); + + /* Setup the tick interrupt */ + configSETUP_TICK_INTERRUPT(); + + #if ( configNUMBER_OF_CORES > 1 ) + /* Start scheduler on other cores */ + for( uint16_t xCoreID = 0; xCoreID < configNUMBER_OF_CORES; xCoreID++ ) + { + if( xCoreID != xCurrentCore ) + { + /* Send yielding request to other cores with flag to start + * first task. TaskContextSwitch is not executed */ + xPortScheduleStatus[ xCoreID ] = PORT_SCHEDULER_STARTFIRSTTASK; + vPortYieldCore( xCoreID ); + } + else + { + /* Nothing to do. The first task is started in this call by + * below vPortStartFirstTask() */ + xPortScheduleStatus[ xCoreID ] = PORT_SCHEDULER_NOREQUEST; + } + } + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + + /* Start first task in primary core */ + vPortStartFirstTask(); + + /* Should never get here as the tasks will now be executing! */ + prvTaskExitError(); + + /* To prevent compiler warnings in the case that the application writer + * overrides this functionality by defining configTASK_RETURN_ADDRESS. + * Call vTaskSwitchContext() so link time optimization does not remove + * the symbol. */ + vTaskSwitchContext( + #if ( configNUMBER_OF_CORES > 1 ) + xCurrentCore + #endif + ); + + return pdFALSE; +} + +/*-----------------------------------------------------------*/ + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ + + /* This statement will always fail, triggering the assert */ + configASSERT( pdFALSE ); + + /* + * The following statement may be unreachable because configASSERT(pdFALSE) + * always triggers an assertion failure, which typically halts program + * execution. + * The warning may be reported to indicate to indicate that the compiler + * detects the subsequent code will not be executed. + * The warning is acceptable to ensure program is halt regardless of + * configASSERT(pdFALSE) implementation + */ + portDISABLE_INTERRUPTS(); + + for( ; ; ) + { + /* Infinite loop to ensure the function does not return. */ + } +} + +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( pdFALSE ); +} + +/*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + + void vPortYieldCore( uint32_t xCoreID ) + { + /* Check if we need to yield on a different core */ + if( xCoreID != xPortGET_CORE_ID() ) + { + volatile uint32_t * pulIPIRReg; + + /* Determine the IPI register based on the target core ID */ + pulIPIRReg = ( volatile uint32_t * ) ( portIPIR_BASE_ADDR ); + + /*Inter-processor interrupt generates an interrupt request by + * writing 1 to applicable bits of target cores. The interrupt + * should be enabled by application in corresponding cores + * including PSW.ID (EI instruction) and interrupt control setting + * for ICIPIRn channel (interrupt mask, vector method) + */ + *pulIPIRReg = ( 1 << xCoreID ); + } + else + { + /* Yielding current core */ + vPortYield(); + } + } + +/*-----------------------------------------------------------*/ + +/* + * Handler for inter-processor interrupt in second cores. The interrupt is + * triggered by portYIELD_CORE(). vTaskSwitchContext() is invoked to + * switch tasks + */ + void vPortIPIHander( void ) + { + BaseType_t xCurrentCore = xPortGET_CORE_ID(); + + /* 1st execution starts 1st task, TaskSwitchContext is not executed */ + if( PORT_SCHEDULER_STARTFIRSTTASK != xPortScheduleStatus[ xCurrentCore ] ) + { + xPortScheduleStatus[ xCurrentCore ] = PORT_SCHEDULER_TASKSWITCH; + } + } + +/*-----------------------------------------------------------*/ + +#endif /* (configNUMBER_OF_CORES > 1) */ + +void vPortTickISR( void ) +{ + /* In case of multicores with SMP, xTaskIncrementTick is required to + * called in critical section to avoid conflict resource as this function + * could be called by xTaskResumeAll() from any cores. */ + #if ( configNUMBER_OF_CORES > 1 ) + BaseType_t xSavedInterruptStatus; + + xSavedInterruptStatus = portENTER_CRITICAL_FROM_ISR(); + #endif + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Pend a context switch. */ + xPortScheduleStatus[ xPortGET_CORE_ID() ] = PORT_SCHEDULER_TASKSWITCH; + } + } + #if ( configNUMBER_OF_CORES > 1 ) + portEXIT_CRITICAL_FROM_ISR( xSavedInterruptStatus ); + #endif +} + +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ + volatile uint32_t * pulOSTMIntReg; + + /* Interrupt configuration for OSTM Timer + * By default, the second lowest priority is set for timer interrupt to + * avoid blocking other interrupt. Normally, user could set the lowest + * priority for non-critical event. It try to keep timer on time. + * In addition, direct vector table is used by default. + */ + pulOSTMIntReg = ( volatile uint32_t * ) portOSTM_EIC_ADDR; + *pulOSTMIntReg = ( portINT_PROCESSING_ENABLED | portINT_DIRECT_VECTOR | portINT_PRIORITY_LEVEL14 ); + + /* Set OSTM0 control setting */ + *( ( volatile uint32_t * ) portOSTM0CTL_ADDR ) = + ( portOSTM_MODE_INTERVAL_TIMER | portOSTM_START_INTERRUPT_DISABLE ); + *( ( volatile uint32_t * ) portOSTM0CMP_ADDR ) = + ( ( configCPU_CLOCK_HZ / configTIMER_PRESCALE ) / configTICK_RATE_HZ ) - 1; + + /* Enable OSTM0 operation */ + *( ( volatile uint32_t * ) portOSTM0TS_ADDR ) = portOSTM_COUNTER_START; +} + +/*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + +/* + * These functions implement spin-lock mechanism among cores using hardware + * exclusive control with atomic access by CLR1 and SET1 instruction. + * Nesting calls to these APIs are possible. + */ + #pragma inline_asm prvExclusiveLock + static void prvExclusiveLock( BaseType_t xBitPosition ) + { + /* No problem with r19, CCRH does not required to restore same value + * before and after function call. */ + mov # _pxPortExclusiveReg, r19 + ld.w 0[ r19 ], r19 + +prvExclusiveLock_Lock: + + /* r6 is xBitPosition */ + set1 r6, [ r19 ] + bz prvExclusiveLock_Lock_success + snooze + br prvExclusiveLock_Lock + +prvExclusiveLock_Lock_success: + } + +/*-----------------------------------------------------------*/ + + #pragma inline_asm prvExclusiveRelease + static void prvExclusiveRelease( BaseType_t xBitPosition ) + { + mov # _pxPortExclusiveReg, r19 + ld.w 0[ r19 ], r19 + + /* r6 is xBitPosition */ + clr1 r6, [ r19 ] + } + +/*-----------------------------------------------------------*/ + void vPortRecursiveLockAcquire( BaseType_t xCoreID, BaseType_t xFromIsr ) + { + BaseType_t xSavedInterruptStatus; + BaseType_t xBitPosition = ( xFromIsr == pdTRUE ); + + xSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + + if( uxLockNesting[ xCoreID ][ xBitPosition ] == 0 ) + { + prvExclusiveLock( xBitPosition ); + } + + uxLockNesting[ xCoreID ][ xBitPosition ]++; + portCLEAR_INTERRUPT_MASK_FROM_ISR( xSavedInterruptStatus ); + } + + void vPortRecursiveLockRelease( BaseType_t xCoreID, BaseType_t xFromIsr ) + { + BaseType_t xSavedInterruptStatus; + BaseType_t xBitPosition = ( xFromIsr == pdTRUE ); + + xSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + + /* Sync memory */ + portSYNCM(); + + /* Error check whether vPortRecursiveLockRelease() is not called in + * pair with vPortRecursiveLockAcquire() */ + configASSERT( ( uxLockNesting[ xCoreID ][ xBitPosition ] > 0 ) ); + uxLockNesting[ xCoreID ][ xBitPosition ]--; + + if( uxLockNesting[ xCoreID ][ xBitPosition ] == 0 ) + { + prvExclusiveRelease( xBitPosition ); + } + + portCLEAR_INTERRUPT_MASK_FROM_ISR( xSavedInterruptStatus ); + } + +/*-----------------------------------------------------------*/ + +#endif /* (configNUMBER_OF_CORES > 1) */ diff --git a/portable/CCRH/F1Kx/portasm.s b/portable/CCRH/F1Kx/portasm.s new file mode 100644 index 000000000..ff8e7ee31 --- /dev/null +++ b/portable/CCRH/F1Kx/portasm.s @@ -0,0 +1,331 @@ +;/* +; * FreeRTOS Kernel +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + +;------------------------------------------------------------------------------ +; Extern symbols +;------------------------------------------------------------------------------ +.extern _uxInterruptNesting +.extern _uxPortMaxInterruptDepth +.extern _xPortScheduleStatus +.extern _vTaskSwitchContext +.extern _pvPortGetCurrentTCB +.extern _vCommonISRHandler +.extern _xPortGET_CORE_ID + +.public _vIrq_Handler +.public _vPortStartFirstTask +.public _vPortYield +.public _vTRAP0_Handler +;------------------------------------------------------------------------------ +; Macro definitions +;------------------------------------------------------------------------------ +EIPC .set 0 +EIPSW .set 1 +PSW .set 5 +FPSR .set 6 +FPEPC .set 7 +EIIC .set 13 +CTPC .set 16 +CTPSW .set 17 +EIIC_MSK .set 0x00000FFF +FPU_MSK .set 0x00010000 +;------------------------------------------------------------------------------ +; portSAVE_CONTEXT +; Context saving +;------------------------------------------------------------------------------ +portSAVE_CONTEXT .macro + prepare lp, 0 + + ; Save general-purpose registers and EIPSW, EIPC, EIIC, CTPSW, CTPC into stack. + pushsp r5, r30 + $nowarning + pushsp r1, r2 + $warning + + stsr EIPSW, r15 + stsr EIPC, r16 + stsr EIIC, r17 + stsr CTPSW, r18 + stsr CTPC, r19 + pushsp r15, r19 + + ; Save FPU registers to stack if FPU is enabled + mov FPU_MSK, r19 + tst r15, r19 + + ; Jump over next 3 instructions: stsr (4 bytes)*2 + pushsp (4 bytes) + bz 12 + stsr FPSR, r18 + stsr FPEPC, r19 + pushsp r18, r19 + + ; Save EIPSW register to stack + ; Due to the syntax of the pushsp instruction, using r14 as dummy value + pushsp r14, r15 + + ; Get current TCB, the return value is stored in r10 (CCRH compiler) + jarl _pvPortGetCurrentTCB, lp + st.w sp, 0[r10] + +.endm + +;------------------------------------------------------------------------------ +; portRESTORE_CONTEXT +; Context restoring +;------------------------------------------------------------------------------ +portRESTORE_CONTEXT .macro + ; Current TCB is returned by r10 (CCRH compiler) + jarl _pvPortGetCurrentTCB, lp + ld.w 0[r10], sp ; Restore the stack pointer from the TCB + + ; Restore FPU registers if FPU is enabled + mov FPU_MSK, r19 + ; Restore EIPSW register to check FPU + ; Due to the syntax of the popsp instruction, using r14 as dummy value + popsp r14, r15 + tst r15, r19 + ; Jump over next 3 instructions: stsr (4 bytes)*2 + popsp (4 bytes) + bz 12 + popsp r18, r19 + ldsr r19, FPEPC + ldsr r18, FPSR + + ;Restore general-purpose registers and EIPSW, EIPC, EIIC, CTPSW, CTPC + popsp r15, r19 + ldsr r19, CTPC + ldsr r18, CTPSW + ldsr r17, EIIC + ldsr r16, EIPC + ldsr r15, EIPSW + + $nowarning + popsp r1, r2 + $warning + popsp r5, r30 + + dispose 0, lp +.endm + +;------------------------------------------------------------------------------ +; Save used registers +;------------------------------------------------------------------------------ +SAVE_REGISTER .macro + ; Save general-purpose registers and EIPSW, EIPC, EIIC, CTPSW, CTPC into stack. + ; Callee-Save registers (r20 to r30) are not used in interrupt handler and + ; guaranteed no change after function call. So, don't need to save register + ; to optimize the used stack memory. + pushsp r5, r19 + $nowarning + pushsp r1, r2 + $warning + + stsr EIPSW, r19 + stsr EIPC, r18 + stsr EIIC, r17 + mov lp, r16 + mov ep, r15 + stsr CTPSW, r14 + stsr CTPC, r13 + pushsp r13, r18 + + mov FPU_MSK, r16 + tst r16, r19 + bz 8 + stsr FPSR, r17 + stsr FPEPC, r18 + + pushsp r17, r19 + +.endm +;------------------------------------------------------------------------------ +; Restore used registers +;------------------------------------------------------------------------------ +RESTORE_REGISTER .macro + + mov FPU_MSK, r15 + popsp r17, r19 + tst r19, r15 + bz 8 + ldsr r18, FPEPC + ldsr r17, FPSR + + popsp r13, r18 + ldsr r13, CTPC + ldsr r14, CTPSW + mov r15, ep + mov r16, lp + ldsr r17, EIIC + ldsr r18, EIPC + ldsr r19, EIPSW + + $nowarning + popsp r1, r2 + $warning + popsp r5, r19 +.endm + +;------------------------------------------------------------------------------ +; Start the first task. +;------------------------------------------------------------------------------ +_vPortStartFirstTask: + portRESTORE_CONTEXT + eiret + +;------------------------------------------------------------------------------ +; _vPortYield +;------------------------------------------------------------------------------ +_vPortYield: + trap 0 + jmp [lp] ; Return to caller function + +;------------------------------------------------------------------------------ +; PortYield handler. This is installed as the TRAP exception handler. +;------------------------------------------------------------------------------ +_vTRAP0_Handler: + ;Save the context of the current task. + portSAVE_CONTEXT + + ; The use case that portYield() is called from interrupt context as nested interrupt. + ; Context switch should be executed at the most outer of interrupt tree. + ; In that case, set xPortScheduleStatus to flag context switch in interrupt handler. + jarl _xPortGET_CORE_ID, lp ; return value is contained in r10 (CCRH compiler) + mov r10, r11 + shl 2, r11 + mov #_uxInterruptNesting, r19 + add r11, r19 + ld.w 0[r19], r18 + cmp r0, r18 + be _vTRAP0_Handler_ContextSwitch + + mov #_xPortScheduleStatus, r19 + add r11, r19 + + ; Set xPortScheduleStatus[coreID]=PORT_SCHEDULER_TASKSWITCH + mov 1, r17 + st.w r17, 0[r19] + br _vTRAP0_Handler_Exit + +_vTRAP0_Handler_ContextSwitch: + ; Pass coreID (r10) as parameter by r6 (CCRH compiler) in SMP support. + mov r10, r6 + ; Call the scheduler to select the next task. + ; vPortYeild may be called to current core again at the end of vTaskSwitchContext. + ; This may case nested interrupt, however, it is not necessary to set + ; uxInterruptNesting (currently 0) for nested trap0 exception. The user interrupt + ; (EI level interrupt) is not accepted inside of trap0 exception. + jarl _vTaskSwitchContext, lp + +_vTRAP0_Handler_Exit: + ; Restore the context of the next task to run. + portRESTORE_CONTEXT + eiret + +;------------------------------------------------------------------------------ +; _Irq_Handler +; Handler interrupt service routine (ISR). +;------------------------------------------------------------------------------ +_vIrq_Handler: + ; Save used registers. + SAVE_REGISTER + + ; Get core ID by HTCFG0, thread configuration register. + ; Then, increase nesting count for current core. + jarl _xPortGET_CORE_ID, lp ; return value is contained in r10 (CCRH compiler) + shl 2, r10 + mov r10, r17 + + mov #_uxInterruptNesting, r19 + add r17, r19 + ld.w 0[r19], r18 + addi 0x1, r18, r16 + st.w r16, 0[r19] + + pushsp r17, r19 + + ;Call the interrupt handler. + stsr EIIC, r6 + andi EIIC_MSK, r6, r6 + + ; Do not enable interrupt for nesting. Stackover flow may occurs if the + ; depth of nesting interrupt is exceeded. + mov #_uxPortMaxInterruptDepth, r19 + ld.w 0[r19], r15 + cmp r15, r16 + bge 4 ; Jump over ei instruction + ei + jarl _vCommonISRHandler, lp + di + synce + + popsp r17, r19 + st.w r18, 0[r19] ; Restore the old nesting count. + + ; A context switch if no nesting interrupt. + cmp 0x0, r18 + bne _vIrq_Handler_NotSwitchContext + + ; Check if context switch is requested. + mov #_xPortScheduleStatus, r19 + add r17, r19 + ld.w 0[r19], r18 + cmp r0, r18 + bne _vIrq_Handler_SwitchContext + +_vIrq_Handler_NotSwitchContext: + ; No context switch. Restore used registers + RESTORE_REGISTER + eiret + +;This sequence is executed for primary core only to switch context +_vIrq_Handler_SwitchContext: + ; Clear the context switch pending flag. + st.w r0, 0[r19] + + add -1, r18 + bnz _vIrq_Handler_StartFirstTask + ; Restore used registers before saving the context to the task stack. + RESTORE_REGISTER + portSAVE_CONTEXT + + ; Get Core ID and pass to vTaskSwitchContext as parameter (CCRH compiler) + ; The parameter is unused in single core, no problem with this redudant setting + jarl _xPortGET_CORE_ID, lp ; return value is contained in r10 (CCRH compiler) + mov r10, r6 + + ; vPortYeild may be called to current core again at the end of vTaskSwitchContext. + ; This may case nested interrupt, however, it is not necessary to set + ; uxInterruptNesting (currently 0) for trap0 exception. The user interrupt + ; (EI level interrupt) is not accepted inside of trap0 exception. + jarl _vTaskSwitchContext, lp ; + portRESTORE_CONTEXT + eiret + +_vIrq_Handler_StartFirstTask: + RESTORE_REGISTER + jr _vPortStartFirstTask + diff --git a/portable/CCRH/F1Kx/portmacro.h b/portable/CCRH/F1Kx/portmacro.h new file mode 100644 index 000000000..a665ad23d --- /dev/null +++ b/portable/CCRH/F1Kx/portmacro.h @@ -0,0 +1,193 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H + #define PORTMACRO_H + + #ifdef __cplusplus + extern "C" + { + #endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions - These are a bit legacy and not really used now, other + * than portSTACK_TYPE and portBASE_TYPE. */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + +/* Defines the maximum time when using a wait command in a task */ + #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. + #endif + +/*-----------------------------------------------------------*/ + +/* Architecture specifics */ + + #define portSTSR( reg ) __stsr( ( reg ) ) + #define portLDSR( reg, val ) __ldsr( ( reg ), ( val ) ) + #define portSTSR_CCRH( reg, sel ) __stsr_rh( ( reg ), ( sel ) ) + #define portSYNCM() __syncm() + +/* Determine the descending of the stack from high address to address */ + #define portSTACK_GROWTH ( -1 ) + +/* Determine the time (in milliseconds) corresponding to each tick */ + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + +/* It is a multiple of 4 (the two lower-order bits of the address = 0), + * otherwise it will cause MAE (Misaligned Exception) according to the manual */ + #define portBYTE_ALIGNMENT ( 4 ) + +/* Interrupt control macros. */ + + #define portENABLE_INTERRUPTS() __EI() /* Macro to enable all maskable interrupts. */ + #define portDISABLE_INTERRUPTS() __DI() /* Macro to disable all maskable interrupts. */ + #define taskENABLE_INTERRUPTS() portENABLE_INTERRUPTS() + #define taskDISABLE_INTERRUPTS() portDISABLE_INTERRUPTS() + +/* SMP build which means configNUM_CORES is relevant */ + #define portSUPPORT_SMP 1 + + #define portMAX_CORE_COUNT 2 + #ifndef configNUMBER_OF_CORES + #define configNUMBER_OF_CORES 1 + #endif + +/*-----------------------------------------------------------*/ +/* Scheduler utilities */ + +/* Called at the end of an ISR that can cause a context switch */ + extern void vPortSetSwitch( BaseType_t xSwitchRequired ); + + #define portEND_SWITCHING_ISR( x ) vPortSetSwitch( x ) + + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) + +/* Use to transfer control from one task to perform other tasks of + * higher priority */ + extern void vPortYield( void ); + + #define portYIELD() vPortYield() + #if ( configNUMBER_OF_CORES > 1 ) + +/* Return the core ID on which the code is running. */ + extern BaseType_t xPortGET_CORE_ID(); + + #define portGET_CORE_ID() xPortGET_CORE_ID() + #define coreid xPortGET_CORE_ID() + +/* Request the core ID x to yield. */ + extern void vPortYieldCore( uint32_t coreID ); + + #define portYIELD_CORE( x ) vPortYieldCore( x ) + + #define portENTER_CRITICAL_FROM_ISR() vTaskEnterCriticalFromISR() + #define portEXIT_CRITICAL_FROM_ISR( x ) vTaskExitCriticalFromISR( x ) + + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + + #if ( configNUMBER_OF_CORES == 1 ) + #define portGET_ISR_LOCK( xCoreID ) + #define portRELEASE_ISR_LOCK( xCoreID ) + #define portGET_TASK_LOCK( xCoreID ) + #define portRELEASE_TASK_LOCK( xCoreID ) + #else + extern void vPortRecursiveLockAcquire( BaseType_t xCoreID, BaseType_t xFromIsr ); + extern void vPortRecursiveLockRelease( BaseType_t xCoreID, BaseType_t xFromIsr ); + + #define portGET_ISR_LOCK( xCoreID ) vPortRecursiveLockAcquire( ( xCoreID ), pdTRUE ) + #define portRELEASE_ISR_LOCK( xCoreID ) vPortRecursiveLockRelease( ( xCoreID ), pdTRUE ) + #define portGET_TASK_LOCK( xCoreID ) vPortRecursiveLockAcquire( ( xCoreID ), pdFALSE ) + #define portRELEASE_TASK_LOCK( xCoreID ) vPortRecursiveLockRelease( ( xCoreID ), pdFALSE ) + #endif /* if ( configNUMBER_OF_CORES == 1 ) */ + +/*-----------------------------------------------------------*/ +/* Critical section management. */ + +/* The critical nesting functions defined within tasks.c */ + + extern void vTaskEnterCritical( void ); + extern void vTaskExitCritical( void ); + +/* Macro to mark the start of a critical code region */ + #define portENTER_CRITICAL() vTaskEnterCritical() + +/* Macro to mark the end of a critical code region */ + #define portEXIT_CRITICAL() vTaskExitCritical() + +/*-----------------------------------------------------------*/ +/* Macros to set and clear the interrupt mask. */ + portLONG xPortSetInterruptMask(); + void vPortClearInterruptMask( portLONG ); + + #define portSET_INTERRUPT_MASK() xPortSetInterruptMask() + #define portCLEAR_INTERRUPT_MASK( x ) vPortClearInterruptMask( ( x ) ) + #define portSET_INTERRUPT_MASK_FROM_ISR() xPortSetInterruptMask() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortClearInterruptMask( ( x ) ) + +/*-----------------------------------------------------------*/ +/* Task function macros as described on the FreeRTOS.org WEB site. */ + + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/*-----------------------------------------------------------*/ + + #ifdef __cplusplus +} + #endif +#endif /* PORTMACRO_H */ diff --git a/portable/CCS/ARM_CM3/port.c b/portable/CCS/ARM_CM3/port.c new file mode 100644 index 000000000..8373c14c0 --- /dev/null +++ b/portable/CCS/ARM_CM3/port.c @@ -0,0 +1,692 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ARM CM3 port. +*----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#if ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) + #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ +#endif + +/* Constants required to manipulate the core. Registers first... */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +/* ...then bits in the registers. */ +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) + +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL ) +#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL ) + +/* Constants required to check the validity of an interrupt priority. */ +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) + +/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */ +#define portVECTACTIVE_MASK ( 0xFFUL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) + +/* The systick is a 24-bit counter. */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/* A fiddle factor to estimate the number of SysTick counts that would have + * occurred while the SysTick counter is stopped during tickless idle + * calculations. */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) + +/* For strict compliance with the Cortex-M spec the task start address should + * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */ +#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL ) + +/* Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ); + +/* + * Exception handlers. + */ +void xPortSysTickHandler( void ); + +/* + * Start first task is a separate function so it can be tested in isolation. + */ +extern void vPortStartFirstTask( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* Required to allow portasm.asm access the configMAX_SYSCALL_INTERRUPT_PRIORITY + * setting. */ +const uint32_t ulMaxSyscallInterruptPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY; + +/* Each task maintains its own interrupt status in the critical nesting + * variable. */ +static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +/* + * The number of SysTick increments that make up one tick period. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulTimerCountsForOneTick = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * The maximum number of tick periods that can be suppressed is limited by the + * 24 bit resolution of the SysTick timer. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t xMaximumPossibleSuppressedTicks = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Compensate for the CPU cycles that pass while the SysTick is stopped (low + * power functionality only. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( configASSERT_DEFINED == 1 ) + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; +#endif /* configASSERT_DEFINED */ + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + + /* Offset added to account for the way the MCU uses the stack on entry/exit + * of interrupts, and to ensure alignment. */ + pxTopOfStack--; + + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */ + + /* Save code space by skipping register initialisation. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + + pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ + configASSERT( uxCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + #if ( configASSERT_DEFINED == 1 ) + { + volatile uint8_t ucOriginalPriority; + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * Save the interrupt priority value that is about to be clobbered. */ + ucOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to all + * possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + + /* Restore the clobbered interrupt priority register to its original + * value. */ + *pucFirstUserPriorityRegister = ucOriginalPriority; + } + #endif /* configASSERT_DEFINED */ + + /* Make PendSV and SysTick the lowest priority interrupts. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ + if( uxCriticalNesting == 1 ) + { + configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + /* The SysTick runs at the lowest interrupt priority, so when this interrupt + * executes all interrupts must be unmasked. There is therefore no need to + * save and then restore the interrupt mask value as its value is already + * known. */ + ( void ) portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + + /* A context switch is required. Context switching is performed in + * the PendSV interrupt. Pend the PendSV interrupt. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 ); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + #pragma WEAK( vPortSuppressTicksAndSleep ) + void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm( " cpsid i" ); + __asm( " dsb" ); + __asm( " isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the cpsid instruction + * above. */ + __asm( " cpsie i" ); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm( " dsb" ); + __asm( " wfi" ); + __asm( " isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm( " cpsie i" ); + __asm( " dsb" ); + __asm( " isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm( " cpsid i" ); + __asm( " dsb" ); + __asm( " isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __asm( " cpsie i" ); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +#pragma WEAK( vPortSetupTimerInterrupt ) +void vPortSetupTimerInterrupt( void ) +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and clear the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); +} +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + extern uint32_t ulPortGetIPSR( void ); + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + ulCurrentInterrupt = ulPortGetIPSR(); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* configASSERT_DEFINED */ diff --git a/portable/CCS/ARM_CM3/portasm.asm b/portable/CCS/ARM_CM3/portasm.asm new file mode 100644 index 000000000..483a66b49 --- /dev/null +++ b/portable/CCS/ARM_CM3/portasm.asm @@ -0,0 +1,144 @@ +;/* +; * FreeRTOS Kernel +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + + .thumb + + .ref pxCurrentTCB + .ref vTaskSwitchContext + .ref ulMaxSyscallInterruptPriority + + .def xPortPendSVHandler + .def ulPortGetIPSR + .def vPortSVCHandler + .def vPortStartFirstTask + +NVICOffsetConst: .word 0xE000ED08 +CPACRConst: .word 0xE000ED88 +pxCurrentTCBConst: .word pxCurrentTCB +ulMaxSyscallInterruptPriorityConst: .word ulMaxSyscallInterruptPriority + +; ----------------------------------------------------------- + + .align 4 +ulPortGetIPSR: .asmfunc + mrs r0, ipsr + bx r14 + .endasmfunc + ; ----------------------------------------------------------- + + .align 4 +vPortSetInterruptMask: .asmfunc + push {r0} + ldr r0, ulMaxSyscallInterruptPriorityConst + msr basepri, r0 + pop {r0} + bx r14 + .endasmfunc +; ----------------------------------------------------------- + + .align 4 +xPortPendSVHandler: .asmfunc + mrs r0, psp + isb + + ;/* Get the location of the current TCB. */ + ldr r3, pxCurrentTCBConst + ldr r2, [r3] + + ;/* Save the core registers. */ + stmdb r0!, {r4-r11} + + ;/* Save the new top of stack into the first member of the TCB. */ + str r0, [r2] + + stmdb sp!, {r3, r14} + ldr r0, ulMaxSyscallInterruptPriorityConst + ldr r1, [r0] + msr basepri, r1 + dsb + isb + bl vTaskSwitchContext + mov r0, #0 + msr basepri, r0 + ldmia sp!, {r3, r14} + + ;/* The first item in pxCurrentTCB is the task top of stack. */ + ldr r1, [r3] + ldr r0, [r1] + + ;/* Pop the core registers. */ + ldmia r0!, {r4-r11} + + msr psp, r0 + isb + bx r14 + .endasmfunc + +; ----------------------------------------------------------- + + .align 4 +vPortSVCHandler: .asmfunc + ;/* Get the location of the current TCB. */ + ldr r3, pxCurrentTCBConst + ldr r1, [r3] + ldr r0, [r1] + ;/* Pop the core registers. */ + ldmia r0!, {r4-r11} + msr psp, r0 + isb + mov r0, #0 + msr basepri, r0 + orr r14, #0xd + bx r14 + .endasmfunc + +; ----------------------------------------------------------- + + .align 4 +vPortStartFirstTask: .asmfunc + ;/* Use the NVIC offset register to locate the stack. */ + ldr r0, NVICOffsetConst + ldr r0, [r0] + ldr r0, [r0] + ;/* Set the msp back to the start of the stack. */ + msr msp, r0 + ;/* Clear the bit that indicates the FPU is in use in case the FPU was used + ;before the scheduler was started - which would otherwise result in the + ;unnecessary leaving of space in the SVC stack for lazy saving of FPU + ;registers. */ + mov r0, #0 + msr control, r0 + ;/* Call SVC to start the first task. */ + cpsie i + cpsie f + dsb + isb + svc #0 + .endasmfunc + +; ----------------------------------------------------------- diff --git a/portable/CCS/ARM_CM3/portmacro.h b/portable/CCS/ARM_CM3/portmacro.h new file mode 100644 index 000000000..42498555f --- /dev/null +++ b/portable/CCS/ARM_CM3/portmacro.h @@ -0,0 +1,189 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H + #define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. + #endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 + +/*-----------------------------------------------------------*/ + +/* Compiler directives. */ + #define portWEAK_SYMBOL __attribute__( ( weak ) ) + +/*-----------------------------------------------------------*/ + +/* Scheduler utilities. */ + #define portYIELD() \ + { \ + /* Set a PendSV to request a context switch. */ \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + __asm( " dsb"); \ + __asm( " isb"); \ + } + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portYIELD(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) + +/*-----------------------------------------------------------*/ + +/* Architecture specific optimisations. */ + #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #endif + + #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __clz( ( uxReadyPriorities ) ) ) + + #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* Critical section management. */ + extern void vPortEnterCritical( void ); + extern void vPortExitCritical( void ); + + #define portDISABLE_INTERRUPTS() \ + { \ + _set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \ + __asm( " dsb"); \ + __asm( " isb"); \ + } + + #define portENABLE_INTERRUPTS() _set_interrupt_priority( 0 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() + #define portSET_INTERRUPT_MASK_FROM_ISR() _set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY ); __asm( " dsb" ); __asm( " isb") + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) _set_interrupt_priority( x ) +/*-----------------------------------------------------------*/ + +/* Tickless idle/low power functionality. */ + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not necessary for to use this port. They are defined so the common demo files + * (which build with all the ports) will build. */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + + #if ( configASSERT_DEFINED == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif + +/* portNOP() is not required by this port. */ + #define portNOP() + +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/CCS/ARM_CM4F/port.c b/portable/CCS/ARM_CM4F/port.c new file mode 100644 index 000000000..1ad05077d --- /dev/null +++ b/portable/CCS/ARM_CM4F/port.c @@ -0,0 +1,717 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ARM CM4F port. +*----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#ifndef __TI_VFP_SUPPORT__ + #error This port can only be used when the project options are configured to enable hardware floating point support. +#endif + +#if ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) + #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ +#endif + +/* Constants required to manipulate the core. Registers first... */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +/* ...then bits in the registers. */ +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) + +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL ) +#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL ) + +/* Constants required to check the validity of an interrupt priority. */ +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) + +/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */ +#define portVECTACTIVE_MASK ( 0xFFUL ) + +/* Constants required to manipulate the VFP. */ +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */ +#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) +#define portINITIAL_EXC_RETURN ( 0xfffffffd ) + +/* The systick is a 24-bit counter. */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/* A fiddle factor to estimate the number of SysTick counts that would have + * occurred while the SysTick counter is stopped during tickless idle + * calculations. */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) + +/* For strict compliance with the Cortex-M spec the task start address should + * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */ +#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL ) + +/* Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ); + +/* + * Exception handlers. + */ +void xPortSysTickHandler( void ); + +/* + * Start first task is a separate function so it can be tested in isolation. + */ +extern void vPortStartFirstTask( void ); + +/* + * Turn the VFP on. + */ +extern void vPortEnableVFP( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* Required to allow portasm.asm access the configMAX_SYSCALL_INTERRUPT_PRIORITY + * setting. */ +const uint32_t ulMaxSyscallInterruptPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY; + +/* Each task maintains its own interrupt status in the critical nesting + * variable. */ +static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +/* + * The number of SysTick increments that make up one tick period. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulTimerCountsForOneTick = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * The maximum number of tick periods that can be suppressed is limited by the + * 24 bit resolution of the SysTick timer. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t xMaximumPossibleSuppressedTicks = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Compensate for the CPU cycles that pass while the SysTick is stopped (low + * power functionality only. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( configASSERT_DEFINED == 1 ) + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; +#endif /* configASSERT_DEFINED */ + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + + /* Offset added to account for the way the MCU uses the stack on entry/exit + * of interrupts, and to ensure alignment. */ + pxTopOfStack--; + + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */ + + /* Save code space by skipping register initialisation. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + + /* A save method is being used that requires each task to maintain its + * own exec return value. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; + + pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ + configASSERT( uxCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + #if ( configASSERT_DEFINED == 1 ) + { + volatile uint8_t ucOriginalPriority; + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * Save the interrupt priority value that is about to be clobbered. */ + ucOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to all + * possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + + /* Restore the clobbered interrupt priority register to its original + * value. */ + *pucFirstUserPriorityRegister = ucOriginalPriority; + } + #endif /* configASSERT_DEFINED */ + + /* Make PendSV and SysTick the lowest priority interrupts. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + /* Ensure the VFP is enabled - it should be anyway. */ + vPortEnableVFP(); + + /* Lazy save always. */ + *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ + if( uxCriticalNesting == 1 ) + { + configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + /* The SysTick runs at the lowest interrupt priority, so when this interrupt + * executes all interrupts must be unmasked. There is therefore no need to + * save and then restore the interrupt mask value as its value is already + * known. */ + ( void ) portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + + /* A context switch is required. Context switching is performed in + * the PendSV interrupt. Pend the PendSV interrupt. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 ); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + #pragma WEAK( vPortSuppressTicksAndSleep ) + void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm( " cpsid i" ); + __asm( " dsb" ); + __asm( " isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the cpsid instruction + * above. */ + __asm( " cpsie i" ); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm( " dsb" ); + __asm( " wfi" ); + __asm( " isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm( " cpsie i" ); + __asm( " dsb" ); + __asm( " isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm( " cpsid i" ); + __asm( " dsb" ); + __asm( " isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __asm( " cpsie i" ); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +#pragma WEAK( vPortSetupTimerInterrupt ) +void vPortSetupTimerInterrupt( void ) +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and clear the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); +} +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + extern uint32_t ulPortGetIPSR( void ); + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + ulCurrentInterrupt = ulPortGetIPSR(); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* configASSERT_DEFINED */ diff --git a/portable/CCS/ARM_CM4F/portasm.asm b/portable/CCS/ARM_CM4F/portasm.asm new file mode 100644 index 000000000..81d0a71c2 --- /dev/null +++ b/portable/CCS/ARM_CM4F/portasm.asm @@ -0,0 +1,171 @@ +;/* +; * FreeRTOS Kernel +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + + .thumb + + .ref pxCurrentTCB + .ref vTaskSwitchContext + .ref ulMaxSyscallInterruptPriority + + .def xPortPendSVHandler + .def ulPortGetIPSR + .def vPortSVCHandler + .def vPortStartFirstTask + .def vPortEnableVFP + +NVICOffsetConst: .word 0xE000ED08 +CPACRConst: .word 0xE000ED88 +pxCurrentTCBConst: .word pxCurrentTCB +ulMaxSyscallInterruptPriorityConst: .word ulMaxSyscallInterruptPriority + +; ----------------------------------------------------------- + + .align 4 +ulPortGetIPSR: .asmfunc + mrs r0, ipsr + bx r14 + .endasmfunc + ; ----------------------------------------------------------- + + .align 4 +vPortSetInterruptMask: .asmfunc + push {r0} + ldr r0, ulMaxSyscallInterruptPriorityConst + msr basepri, r0 + pop {r0} + bx r14 + .endasmfunc +; ----------------------------------------------------------- + + .align 4 +xPortPendSVHandler: .asmfunc + mrs r0, psp + isb + + ;/* Get the location of the current TCB. */ + ldr r3, pxCurrentTCBConst + ldr r2, [r3] + + ;/* Is the task using the FPU context? If so, push high vfp registers. */ + tst r14, #0x10 + it eq + vstmdbeq r0!, {s16-s31} + + ;/* Save the core registers. */ + stmdb r0!, {r4-r11, r14} + + ;/* Save the new top of stack into the first member of the TCB. */ + str r0, [r2] + + stmdb sp!, {r0, r3} + ldr r0, ulMaxSyscallInterruptPriorityConst + ldr r1, [r0] + msr basepri, r1 + dsb + isb + bl vTaskSwitchContext + mov r0, #0 + msr basepri, r0 + ldmia sp!, {r0, r3} + + ;/* The first item in pxCurrentTCB is the task top of stack. */ + ldr r1, [r3] + ldr r0, [r1] + + ;/* Pop the core registers. */ + ldmia r0!, {r4-r11, r14} + + ;/* Is the task using the FPU context? If so, pop the high vfp registers + ;too. */ + tst r14, #0x10 + it eq + vldmiaeq r0!, {s16-s31} + + msr psp, r0 + isb + bx r14 + .endasmfunc + +; ----------------------------------------------------------- + + .align 4 +vPortSVCHandler: .asmfunc + ;/* Get the location of the current TCB. */ + ldr r3, pxCurrentTCBConst + ldr r1, [r3] + ldr r0, [r1] + ;/* Pop the core registers. */ + ldmia r0!, {r4-r11, r14} + msr psp, r0 + isb + mov r0, #0 + msr basepri, r0 + bx r14 + .endasmfunc + +; ----------------------------------------------------------- + + .align 4 +vPortStartFirstTask: .asmfunc + ;/* Use the NVIC offset register to locate the stack. */ + ldr r0, NVICOffsetConst + ldr r0, [r0] + ldr r0, [r0] + ;/* Set the msp back to the start of the stack. */ + msr msp, r0 + ;/* Clear the bit that indicates the FPU is in use in case the FPU was used + ;before the scheduler was started - which would otherwise result in the + ;unnecessary leaving of space in the SVC stack for lazy saving of FPU + ;registers. */ + mov r0, #0 + msr control, r0 + ;/* Call SVC to start the first task. */ + cpsie i + cpsie f + dsb + isb + svc #0 + .endasmfunc + +; ----------------------------------------------------------- + + .align 4 +vPortEnableVFP: .asmfunc + ;/* The FPU enable bits are in the CPACR. */ + ldr.w r0, CPACRConst + ldr r1, [r0] + + ;/* Enable CP10 and CP11 coprocessors, then save back. */ + orr r1, r1, #( 0xf << 20 ) + str r1, [r0] + bx r14 + .endasmfunc + + .end + +; ----------------------------------------------------------- diff --git a/portable/CCS/ARM_CM4F/portmacro.h b/portable/CCS/ARM_CM4F/portmacro.h new file mode 100644 index 000000000..faefd124c --- /dev/null +++ b/portable/CCS/ARM_CM4F/portmacro.h @@ -0,0 +1,183 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H + #define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. + #endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 +/*-----------------------------------------------------------*/ + +/* Scheduler utilities. */ + #define portYIELD() \ + { \ + /* Set a PendSV to request a context switch. */ \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + __asm( " dsb"); \ + __asm( " isb"); \ + } + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portYIELD(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) + +/*-----------------------------------------------------------*/ + +/* Architecture specific optimisations. */ + #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #endif + + #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __clz( ( uxReadyPriorities ) ) ) + + #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* Critical section management. */ + extern void vPortEnterCritical( void ); + extern void vPortExitCritical( void ); + + #define portDISABLE_INTERRUPTS() \ + { \ + _set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \ + __asm( " dsb"); \ + __asm( " isb"); \ + } + + #define portENABLE_INTERRUPTS() _set_interrupt_priority( 0 ) + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() + #define portSET_INTERRUPT_MASK_FROM_ISR() _set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY ); __asm( " dsb" ); __asm( " isb") + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) _set_interrupt_priority( x ) +/*-----------------------------------------------------------*/ + +/* Tickless idle/low power functionality. */ + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not necessary for to use this port. They are defined so the common demo files + * (which build with all the ports) will build. */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + + #if ( configASSERT_DEFINED == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif + +/* portNOP() is not required by this port. */ + #define portNOP() + +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/CCS/ARM_Cortex-R4/port.c b/portable/CCS/ARM_Cortex-R4/port.c new file mode 100644 index 000000000..853248f40 --- /dev/null +++ b/portable/CCS/ARM_Cortex-R4/port.c @@ -0,0 +1,312 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/*-----------------------------------------------------------*/ + +/* Count of the critical section nesting depth. */ +uint32_t ulCriticalNesting = 9999; + +/*-----------------------------------------------------------*/ + +/* Registers required to configure the RTI. */ +#define portRTI_GCTRL_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC00 ) ) +#define portRTI_TBCTRL_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC04 ) ) +#define portRTI_COMPCTRL_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC0C ) ) +#define portRTI_CNT0_FRC0_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC10 ) ) +#define portRTI_CNT0_UC0_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC14 ) ) +#define portRTI_CNT0_CPUC0_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC18 ) ) +#define portRTI_CNT0_COMP0_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC50 ) ) +#define portRTI_CNT0_UDCP0_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC54 ) ) +#define portRTI_SETINTENA_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC80 ) ) +#define portRTI_CLEARINTENA_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC84 ) ) +#define portRTI_INTFLAG_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC88 ) ) + + +/* Constants required to set up the initial stack of each task. */ +#define portINITIAL_SPSR ( ( StackType_t ) 0x1F ) +#define portINITIAL_FPSCR ( ( StackType_t ) 0x00 ) +#define portINSTRUCTION_SIZE ( ( StackType_t ) 0x04 ) +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) + +/* The number of words on the stack frame between the saved Top Of Stack and +R0 (in which the parameters are passed. */ +#define portSPACE_BETWEEN_TOS_AND_PARAMETERS ( 12 ) + +/*-----------------------------------------------------------*/ + +/* vPortStartFirstSTask() is defined in portASM.asm */ +extern void vPortStartFirstTask( void ); + +/*-----------------------------------------------------------*/ + +/* Saved as part of the task context. Set to pdFALSE if the task does not +require an FPU context. */ +uint32_t ulTaskHasFPUContext = 0; + +/*-----------------------------------------------------------*/ + + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +StackType_t *pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + #if __TI_VFP_SUPPORT__ + { + /* Ensure the stack is correctly aligned on exit. */ + pxTopOfStack--; + } + #endif + + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which is the start of the as + the task has not executed yet. The offset is added to make the return + address appear as it would within an IRQ ISR. */ + *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0x00000000; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + + #ifdef portPRELOAD_TASK_REGISTERS + { + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + } + #else + { + pxTopOfStack -= portSPACE_BETWEEN_TOS_AND_PARAMETERS; + } + #endif + + /* Function parameters are passed in R0. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* Set the status register for system mode, with interrupts enabled. */ + *pxTopOfStack = ( StackType_t ) ( ( _get_CPSR() & ~0xFF ) | portINITIAL_SPSR ); + + if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00 ) + { + /* The task will start in thumb mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + + #ifdef __TI_VFP_SUPPORT__ + { + pxTopOfStack--; + + /* The last thing on the stack is the tasks ulUsingFPU value, which by + default is set to indicate that the stack frame does not include FPU + registers. */ + *pxTopOfStack = pdFALSE; + } + #endif + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt(void) +{ + /* Disable timer 0. */ + portRTI_GCTRL_REG &= 0xFFFFFFFEUL; + + /* Use the internal counter. */ + portRTI_TBCTRL_REG = 0x00000000U; + + /* COMPSEL0 will use the RTIFRC0 counter. */ + portRTI_COMPCTRL_REG = 0x00000000U; + + /* Initialise the counter and the prescale counter registers. */ + portRTI_CNT0_UC0_REG = 0x00000000U; + portRTI_CNT0_FRC0_REG = 0x00000000U; + + /* Set Prescalar for RTI clock. */ + portRTI_CNT0_CPUC0_REG = 0x00000001U; + portRTI_CNT0_COMP0_REG = ( configCPU_CLOCK_HZ / 2 ) / configTICK_RATE_HZ; + portRTI_CNT0_UDCP0_REG = ( configCPU_CLOCK_HZ / 2 ) / configTICK_RATE_HZ; + + /* Clear interrupts. */ + portRTI_INTFLAG_REG = 0x0007000FU; + portRTI_CLEARINTENA_REG = 0x00070F0FU; + + /* Enable the compare 0 interrupt. */ + portRTI_SETINTENA_REG = 0x00000001U; + portRTI_GCTRL_REG |= 0x00000001U; +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler(void) +{ + /* Start the timer that generates the tick ISR. */ + prvSetupTimerInterrupt(); + + /* Reset the critical section nesting count read to execute the first task. */ + ulCriticalNesting = 0; + + /* Start the first task. This is done from portASM.asm as ARM mode must be + used. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return pdFAIL; +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +void vPortEndScheduler(void) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if configUSE_PREEMPTION == 0 + + /* The cooperative scheduler requires a normal IRQ service routine to + * simply increment the system tick. */ + __interrupt void vPortNonPreemptiveTick( void ) + { + /* clear clock interrupt flag */ + portRTI_INTFLAG_REG = 0x00000001; + + /* Increment the tick count - this may make a delaying task ready + to run - but a context switch is not performed. */ + xTaskIncrementTick(); + } + + #else + + /* + ************************************************************************** + * The preemptive scheduler ISR is written in assembler and can be found + * in the portASM.asm file. This will only get used if portUSE_PREEMPTION + * is set to 1 in portmacro.h + ************************************************************************** + */ + void vPortPreemptiveTick( void ); + +#endif +/*-----------------------------------------------------------*/ + + +/* + * Disable interrupts, and keep a count of the nesting depth. + */ +void vPortEnterCritical( void ) +{ + /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ + portDISABLE_INTERRUPTS(); + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +/* + * Decrement the critical nesting count, and if it has reached zero, re-enable + * interrupts. + */ +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > 0 ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + re-enabled. */ + if( ulCriticalNesting == 0 ) + { + /* Enable interrupts as per portENABLE_INTERRUPTS(). */ + portENABLE_INTERRUPTS(); + } + } +} +/*-----------------------------------------------------------*/ + +#if __TI_VFP_SUPPORT__ + + void vPortTaskUsesFPU( void ) + { + extern void vPortInitialiseFPSCR( void ); + + /* A task is registering the fact that it needs an FPU context. Set the + FPU flag (saved as part of the task context. */ + ulTaskHasFPUContext = pdTRUE; + + /* Initialise the floating point status register. */ + vPortInitialiseFPSCR(); + } + +#endif /* __TI_VFP_SUPPORT__ */ + +/*-----------------------------------------------------------*/ diff --git a/portable/CCS/ARM_Cortex-R4/portASM.asm b/portable/CCS/ARM_Cortex-R4/portASM.asm new file mode 100644 index 000000000..f20af2941 --- /dev/null +++ b/portable/CCS/ARM_Cortex-R4/portASM.asm @@ -0,0 +1,229 @@ +;/* +; * FreeRTOS Kernel +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + + .text + .arm + .ref vTaskSwitchContext + .ref xTaskIncrementTick + .ref ulTaskHasFPUContext + .ref pxCurrentTCB + +;/*-----------------------------------------------------------*/ +; +; Save Task Context +; +portSAVE_CONTEXT .macro + DSB + + ; Push R0 as we are going to use it + STMDB SP!, {R0} + + ; Set R0 to point to the task stack pointer. + STMDB SP,{SP}^ + SUB SP, SP, #4 + LDMIA SP!,{R0} + + ; Push the return address onto the stack. + STMDB R0!, {LR} + + ; Now LR has been saved, it can be used instead of R0. + MOV LR, R0 + + ; Pop R0 so it can be saved onto the task stack. + LDMIA SP!, {R0} + + ; Push all the system mode registers onto the task stack. + STMDB LR,{R0-LR}^ + SUB LR, LR, #60 + + ; Push the SPSR onto the task stack. + MRS R0, SPSR + STMDB LR!, {R0} + + .if (__TI_VFP_SUPPORT__) + ;Determine if the task maintains an FPU context. + LDR R0, ulFPUContextConst + LDR R0, [R0] + + ; Test the flag + CMP R0, #0 + + ; If the task is not using a floating point context then skip the + ; saving of the FPU registers. + BEQ $+16 + FSTMDBD LR!, {D0-D15} + FMRX R1, FPSCR + STMFD LR!, {R1} + + ; Save the flag + STMDB LR!, {R0} + .endif + + ; Store the new top of stack for the task. + LDR R0, pxCurrentTCBConst + LDR R0, [R0] + STR LR, [R0] + + .endm + +;/*-----------------------------------------------------------*/ +; +; Restore Task Context +; +portRESTORE_CONTEXT .macro + LDR R0, pxCurrentTCBConst + LDR R0, [R0] + LDR LR, [R0] + + .if (__TI_VFP_SUPPORT__) + ; The floating point context flag is the first thing on the stack. + LDR R0, ulFPUContextConst + LDMFD LR!, {R1} + STR R1, [R0] + + ; Test the flag + CMP R1, #0 + + ; If the task is not using a floating point context then skip the + ; VFP register loads. + BEQ $+16 + + ; Restore the floating point context. + LDMFD LR!, {R0} + FLDMIAD LR!, {D0-D15} + FMXR FPSCR, R0 + .endif + + ; Get the SPSR from the stack. + LDMFD LR!, {R0} + MSR SPSR_CSXF, R0 + + ; Restore all system mode registers for the task. + LDMFD LR, {R0-R14}^ + + ; Restore the return address. + LDR LR, [LR, #+60] + + ; And return - correcting the offset in the LR to obtain the + ; correct address. + SUBS PC, LR, #4 + .endm + +;/*-----------------------------------------------------------*/ +; Start the first task by restoring its context. + + .def vPortStartFirstTask + +vPortStartFirstTask: + portRESTORE_CONTEXT + +;/*-----------------------------------------------------------*/ +; Yield to another task. + + .def vPortYieldProcessor + +vPortYieldProcessor: + ; Within an IRQ ISR the link register has an offset from the true return + ; address. SWI doesn't do this. Add the offset manually so the ISR + ; return code can be used. + ADD LR, LR, #4 + + ; First save the context of the current task. + portSAVE_CONTEXT + + ; Select the next task to execute. */ + BL vTaskSwitchContext + + ; Restore the context of the task selected to execute. + portRESTORE_CONTEXT + +;/*-----------------------------------------------------------*/ +; Yield to another task from within the FreeRTOS API + + .def vPortYeildWithinAPI + +vPortYeildWithinAPI: + ; Save the context of the current task. + + portSAVE_CONTEXT + ; Clear SSI flag. + MOVW R0, #0xFFF4 + MOVT R0, #0xFFFF + LDR R0, [R0] + + ; Select the next task to execute. */ + BL vTaskSwitchContext + + ; Restore the context of the task selected to execute. + portRESTORE_CONTEXT + +;/*-----------------------------------------------------------*/ +; Preemptive Tick + + .def vPortPreemptiveTick + +vPortPreemptiveTick: + + ; Save the context of the current task. + portSAVE_CONTEXT + + ; Clear interrupt flag + MOVW R0, #0xFC88 + MOVT R0, #0xFFFF + MOV R1, #1 + STR R1, [R0] + + ; Increment the tick count, making any adjustments to the blocked lists + ; that may be necessary. + BL xTaskIncrementTick + + ; Select the next task to execute. + CMP R0, #0 + BLNE vTaskSwitchContext + + ; Restore the context of the task selected to execute. + portRESTORE_CONTEXT + +;------------------------------------------------------------------------------- + + .if (__TI_VFP_SUPPORT__) + + .def vPortInitialiseFPSCR + +vPortInitialiseFPSCR: + + MOV R0, #0 + FMXR FPSCR, R0 + BX LR + + .endif ;__TI_VFP_SUPPORT__ + + +pxCurrentTCBConst .word pxCurrentTCB +ulFPUContextConst .word ulTaskHasFPUContext +;------------------------------------------------------------------------------- diff --git a/portable/CCS/ARM_Cortex-R4/portmacro.h b/portable/CCS/ARM_Cortex-R4/portmacro.h new file mode 100644 index 000000000..644f13a3c --- /dev/null +++ b/portable/CCS/ARM_Cortex-R4/portmacro.h @@ -0,0 +1,119 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORTMACRO_H__ +#define __PORTMACRO_H__ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if (configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS) + typedef uint16_t TickType_t; + #define portMAX_DELAY (TickType_t) 0xFFFF +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY (TickType_t) 0xFFFFFFFFF + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif + + +/* Architecture specifics. */ +#define portSTACK_GROWTH (-1) +#define portTICK_PERIOD_MS ((TickType_t) 1000 / configTICK_RATE_HZ) +#define portBYTE_ALIGNMENT 8 + +/* Critical section handling. */ +extern void vPortEnterCritical(void); +extern void vPortExitCritical(void); +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +#define portDISABLE_INTERRUPTS() asm( " CPSID I" ) +#define portENABLE_INTERRUPTS() asm( " CPSIE I" ) + +/* Scheduler utilities. */ +#pragma SWI_ALIAS( vPortYield, 0 ) +extern void vPortYield( void ); +#define portYIELD() vPortYield() +#define portSYS_SSIR1_REG ( * ( ( volatile uint32_t * ) 0xFFFFFFB0 ) ) +#define portSYS_SSIR1_SSKEY ( 0x7500UL ) +#define portYIELD_WITHIN_API() { portSYS_SSIR1_REG = portSYS_SSIR1_SSKEY; asm( " DSB " ); asm( " ISB " ); } +#define portYIELD_FROM_ISR( x ) do { if( x != pdFALSE ) { portSYS_SSIR1_REG = portSYS_SSIR1_SSKEY; ( void ) portSYS_SSIR1_REG; } } while( 0 ) + +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +/* Architecture specific optimisations. */ +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + + /* Check the configuration. */ + #if( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + + /* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + + /*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __clz( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION(vFunction, pvParameters) void vFunction(void *pvParameters) +#define portTASK_FUNCTION_PROTO(vFunction, pvParameters) void vFunction(void *pvParameters) + +#endif /* __PORTMACRO_H__ */ diff --git a/portable/CCS/MSP430X/data_model.h b/portable/CCS/MSP430X/data_model.h new file mode 100644 index 000000000..b199175c0 --- /dev/null +++ b/portable/CCS/MSP430X/data_model.h @@ -0,0 +1,49 @@ +;/* +; * FreeRTOS Kernel +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + + .if $DEFINED( __LARGE_DATA_MODEL__ ) + .define "pushm.a", pushm_x + .define "popm.a", popm_x + .define "push.a", push_x + .define "pop.a", pop_x + .define "mov.a", mov_x + .else + .define "pushm.w", pushm_x + .define "popm.w", popm_x + .define "push.w", push_x + .define "pop.w", pop_x + .define "mov.w", mov_x + .endif + + .if $DEFINED( __LARGE_CODE_MODEL__ ) + .define "calla", call_x + .define "reta", ret_x + .else + .define "call", call_x + .define "ret", ret_x + .endif diff --git a/portable/CCS/MSP430X/port.c b/portable/CCS/MSP430X/port.c new file mode 100644 index 000000000..2097a2931 --- /dev/null +++ b/portable/CCS/MSP430X/port.c @@ -0,0 +1,191 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Hardware includes. */ +#include "msp430.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the MSP430X port. + *----------------------------------------------------------*/ + +/* Constants required for hardware setup. The tick ISR runs off the ACLK, +not the MCLK. */ +#define portACLK_FREQUENCY_HZ ( ( TickType_t ) 32768 ) +#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 ) +#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x08 ) + +/* We require the address of the pxCurrentTCB variable, but don't want to know +any details of its type. */ +typedef void TCB_t; +extern volatile TCB_t * volatile pxCurrentTCB; + +/* Each task maintains a count of the critical section nesting depth. Each +time a critical section is entered the count is incremented. Each time a +critical section is exited the count is decremented - with interrupts only +being re-enabled if the count is zero. + +usCriticalNesting will get set to zero when the scheduler starts, but must +not be initialised to zero as this will cause problems during the startup +sequence. */ +volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING; +/*-----------------------------------------------------------*/ + + +/* + * Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but + * could have alternatively used the watchdog timer or timer 1. + */ +void vPortSetupTimerInterrupt( void ); +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See the header file portable.h. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +uint16_t *pusTopOfStack; +uint32_t *pulTopOfStack, ulTemp; + + /* + Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging and can be included if required. + + *pxTopOfStack = ( StackType_t ) 0x1111; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x2222; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x3333; + pxTopOfStack--; + */ + + /* Data types are need either 16 bits or 32 bits depending on the data + and code model used. */ + if( sizeof( pxCode ) == sizeof( uint16_t ) ) + { + pusTopOfStack = ( uint16_t * ) pxTopOfStack; + ulTemp = ( uint32_t ) pxCode; + *pusTopOfStack = ( uint16_t ) ulTemp; + } + else + { + /* Make room for a 20 bit value stored as a 32 bit value. */ + pusTopOfStack = ( uint16_t * ) pxTopOfStack; + pusTopOfStack--; + pulTopOfStack = ( uint32_t * ) pusTopOfStack; + *pulTopOfStack = ( uint32_t ) pxCode; + } + + pusTopOfStack--; + *pusTopOfStack = portFLAGS_INT_ENABLED; + pusTopOfStack -= ( sizeof( StackType_t ) / 2 ); + + /* From here on the size of stacked items depends on the memory model. */ + pxTopOfStack = ( StackType_t * ) pusTopOfStack; + + /* Next the general purpose registers. */ + #ifdef PRELOAD_REGISTER_VALUES + *pxTopOfStack = ( StackType_t ) 0xffff; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xeeee; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xdddd; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xbbbb; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xaaaa; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x9999; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x8888; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x5555; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x6666; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x5555; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x4444; + pxTopOfStack--; + #else + pxTopOfStack -= 3; + *pxTopOfStack = ( StackType_t ) pvParameters; + pxTopOfStack -= 9; + #endif + + /* A variable is used to keep track of the critical section nesting. + This variable has to be stored as part of the task context and is + initially set to zero. */ + *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING; + + /* Return a pointer to the top of the stack we have generated so this can + be stored in the task control block for the task. */ + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the MSP430 port will get stopped. If required simply + disable the tick interrupt here. */ +} +/*-----------------------------------------------------------*/ + +/* + * Hardware initialisation to generate the RTOS tick. + */ +void vPortSetupTimerInterrupt( void ) +{ + vApplicationSetupTimerInterrupt(); +} +/*-----------------------------------------------------------*/ + +#pragma vector=configTICK_VECTOR +interrupt void vTickISREntry( void ) +{ +extern void vPortTickISR( void ); + + __bic_SR_register_on_exit( SCG1 + SCG0 + OSCOFF + CPUOFF ); + #if configUSE_PREEMPTION == 1 + extern void vPortPreemptiveTickISR( void ); + vPortPreemptiveTickISR(); + #else + extern void vPortCooperativeTickISR( void ); + vPortCooperativeTickISR(); + #endif +} + + diff --git a/portable/CCS/MSP430X/portext.asm b/portable/CCS/MSP430X/portext.asm new file mode 100644 index 000000000..dbbcec0aa --- /dev/null +++ b/portable/CCS/MSP430X/portext.asm @@ -0,0 +1,159 @@ +;/* +; * FreeRTOS Kernel +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + +; * The definition of the "register test" tasks, as described at the top of +; * main.c + + .include data_model.h + + .global xTaskIncrementTick + .global vTaskSwitchContext + .global vPortSetupTimerInterrupt + .global pxCurrentTCB + .global usCriticalNesting + + .def vPortPreemptiveTickISR + .def vPortCooperativeTickISR + .def vPortYield + .def xPortStartScheduler + +;----------------------------------------------------------- + +portSAVE_CONTEXT .macro + + ;Save the remaining registers. + pushm_x #12, r15 + movx.w &usCriticalNesting, r14 + push_x r14 + mov_x &pxCurrentTCB, r12 + mov_x sp, 0( r12 ) + .endm +;----------------------------------------------------------- + +portRESTORE_CONTEXT .macro + + mov_x &pxCurrentTCB, r12 + mov_x @r12, sp + pop_x r15 + movx.w r15, &usCriticalNesting + popm_x #12, r15 + nop + pop.w sr + nop + ret_x + .endm +;----------------------------------------------------------- + +;* +;* The RTOS tick ISR. +;* +;* If the cooperative scheduler is in use this simply increments the tick +;* count. +;* +;* If the preemptive scheduler is in use a context switch can also occur. +;*/ + + .text + .align 2 + +vPortPreemptiveTickISR: .asmfunc + + ; The sr is not saved in portSAVE_CONTEXT() because vPortYield() needs + ;to save it manually before it gets modified (interrupts get disabled). + push.w sr + portSAVE_CONTEXT + + call_x #xTaskIncrementTick + call_x #vTaskSwitchContext + + portRESTORE_CONTEXT + .endasmfunc +;----------------------------------------------------------- + + .align 2 + +vPortCooperativeTickISR: .asmfunc + + ; The sr is not saved in portSAVE_CONTEXT() because vPortYield() needs + ;to save it manually before it gets modified (interrupts get disabled). + push.w sr + portSAVE_CONTEXT + + call_x #xTaskIncrementTick + + portRESTORE_CONTEXT + + .endasmfunc +;----------------------------------------------------------- + +; +; Manual context switch called by the portYIELD() macro. +; + + .align 2 + +vPortYield: .asmfunc + + ; The sr needs saving before it is modified. + push.w sr + + ; Now the SR is stacked we can disable interrupts. + dint + nop + + ; Save the context of the current task. + portSAVE_CONTEXT + + ; Select the next task to run. + call_x #vTaskSwitchContext + + ; Restore the context of the new task. + portRESTORE_CONTEXT + .endasmfunc +;----------------------------------------------------------- + + +; +; Start off the scheduler by initialising the RTOS tick timer, then restoring +; the context of the first task. +; + + .align 2 + +xPortStartScheduler: .asmfunc + + ; Setup the hardware to generate the tick. Interrupts are disabled + ; when this function is called. + call_x #vPortSetupTimerInterrupt + + ; Restore the context of the first task that is going to run. + portRESTORE_CONTEXT + .endasmfunc +;----------------------------------------------------------- + + .end diff --git a/portable/CCS/MSP430X/portmacro.h b/portable/CCS/MSP430X/portmacro.h new file mode 100644 index 000000000..c00c5a902 --- /dev/null +++ b/portable/CCS/MSP430X/portmacro.h @@ -0,0 +1,142 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portBASE_TYPE portSHORT + +/* The stack type changes depending on the data model. */ +#ifdef __LARGE_DATA_MODEL__ + #define portSTACK_TYPE uint32_t +#else + #define portSTACK_TYPE uint16_t + #define portPOINTER_SIZE_TYPE uint16_t +#endif + +typedef portSTACK_TYPE StackType_t; +typedef short BaseType_t; +typedef unsigned short UBaseType_t; + +#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif + +/*-----------------------------------------------------------*/ + +/* Interrupt control macros. */ +#define portDISABLE_INTERRUPTS() __asm volatile ( " DINT\n" " NOP" ) +#define portENABLE_INTERRUPTS() __asm volatile ( " NOP\n" " EINT\n" " NOP" ) +/*-----------------------------------------------------------*/ + +/* Critical section control macros. */ +#define portNO_CRITICAL_SECTION_NESTING ( ( uint16_t ) 0 ) + +#define portENTER_CRITICAL() \ +{ \ +extern volatile uint16_t usCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + \ + /* Now interrupts are disabled usCriticalNesting can be accessed */ \ + /* directly. Increment ulCriticalNesting to keep a count of how many */ \ + /* times portENTER_CRITICAL() has been called. */ \ + usCriticalNesting++; \ +} + +#define portEXIT_CRITICAL() \ +{ \ +extern volatile uint16_t usCriticalNesting; \ + \ + if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ + { \ + /* Decrement the nesting count as we are leaving a critical section. */ \ + usCriticalNesting--; \ + \ + /* If the nesting level has reached zero then interrupts should be */ \ + /* re-enabled. */ \ + if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } \ +} +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* + * Manual context switch called by portYIELD or taskYIELD. + */ +extern void vPortYield( void ); +#define portYIELD() vPortYield() +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 2 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() __asm volatile ( " NOP" ) +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +extern void vTaskSwitchContext( void ); +#define portYIELD_FROM_ISR( x ) do { if( x ) vPortYield(); } while( 0 ) + +void vApplicationSetupTimerInterrupt( void ); + +/* sizeof( int ) != sizeof( long ) so a full printf() library is required if +run time stats information is to be displayed. */ +#define portLU_PRINTF_SPECIFIER_REQUIRED + +#endif /* PORTMACRO_H */ diff --git a/portable/CMakeLists.txt b/portable/CMakeLists.txt new file mode 100644 index 000000000..ffbb6164c --- /dev/null +++ b/portable/CMakeLists.txt @@ -0,0 +1,1356 @@ +if( FREERTOS_PORT STREQUAL "GCC_RISC_V_GENERIC" ) + include( GCC/RISC-V/chip_extensions.cmake ) +endif() + +if( FREERTOS_PORT STREQUAL "IAR_RISC_V_GENERIC" ) + include( IAR/RISC-V/chip_extensions.cmake ) +endif() + +# FreeRTOS internal cmake file. Do not use it in user top-level project + +if (FREERTOS_PORT STREQUAL "A_CUSTOM_PORT") + message(STATUS "Using a custom FREERTOS_PORT.") + return() +endif() + +# FreeRTOS internal cmake file. Do not use it in user top-level project + +add_library(freertos_kernel_port OBJECT + # TEMPLATE Port + $<$: + template/port.c> + + # 16-Bit DOS ports for BCC + $<$: + BCC/16BitDOS/common/portcomn.c + BCC/16BitDOS/Flsh186/port.c> + + $<$: + BCC/16BitDOS/common/portcomn.c + BCC/16BitDOS/PC/port.c> + + # ARMv7-M port for Texas Instruments Code Composer Studio + $<$: + CCS/ARM_CM3/port.c + CCS/ARM_CM3/portasm.asm> + + # ARMv7E-M port for Texas Instruments Code Composer Studio + $<$: + CCS/ARM_CM4F/port.c + CCS/ARM_CM4F/portasm.asm> + + # ARMv7-R port for Texas Instruments Code Composer Studio + $<$: + CCS/ARM_Cortex-R4/port.c + CCS/ARM_Cortex-R4/portASM.asm> + + # Texas Instruments MSP430 port for Texas Instruments Code Composer Studio + $<$: + CCS/MSP430X/port.c + CCS/MSP430X/portext.asm> + + # NXP (formerly Motorola, Freescale) Cold Fire and 68HCS12 ports for Code Warrior + $<$: + CodeWarrior/ColdFire_V1/port.c + CodeWarrior/ColdFire_V1/portasm.S> + + $<$: + CodeWarrior/ColdFire_V2/port.c + CodeWarrior/ColdFire_V2/portasm.S> + + $<$: + CodeWarrior/HCS12/port.c> + + # ARMv7-A port for GCC + $<$: + GCC/ARM_CA9/port.c + GCC/ARM_CA9/portASM.S> + + # ARMv8-A ports for GCC + $<$: + GCC/ARM_AARCH64/port.c + GCC/ARM_AARCH64/portASM.S> + + $<$: + GCC/ARM_AARCH64_SRE/port.c + GCC/ARM_AARCH64_SRE/portASM.S> + + # ARMv6-M port for GCC + $<$: + GCC/ARM_CM0/port.c + GCC/ARM_CM0/portasm.c + GCC/ARM_CM0/mpu_wrappers_v2_asm.c> + + # ARMv6-M / Cortex-M0 Raspberry PI RP2040 port for GCC + $<$: + ThirdParty/GCC/RP2040/port.c> + + # ARMv7-M ports for GCC + $<$: + GCC/ARM_CM3/port.c> + + $<$: + GCC/ARM_CM3_MPU/port.c + GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c> + + # ARMv7E-M ports for GCC + $<$: + GCC/ARM_CM4_MPU/port.c + GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c> + + $<$: + GCC/ARM_CM4F/port.c> + + $<$: + GCC/ARM_CM7/r0p1/port.c> + + # ARMv8-M ports for GCC + $<$: + GCC/ARM_CM23/non_secure/port.c + GCC/ARM_CM23/non_secure/portasm.c + GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c> + + $<$: + GCC/ARM_CM23/secure/secure_context_port.c + GCC/ARM_CM23/secure/secure_context.c + GCC/ARM_CM23/secure/secure_heap.c + GCC/ARM_CM23/secure/secure_init.c> + + $<$: + GCC/ARM_CM23_NTZ/non_secure/port.c + GCC/ARM_CM23_NTZ/non_secure/portasm.c + GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c> + + $<$: + GCC/ARM_CM33/non_secure/port.c + GCC/ARM_CM33/non_secure/portasm.c + GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c> + + $<$: + GCC/ARM_CM33/secure/secure_context_port.c + GCC/ARM_CM33/secure/secure_context.c + GCC/ARM_CM33/secure/secure_heap.c + GCC/ARM_CM33/secure/secure_init.c> + + $<$: + GCC/ARM_CM33_NTZ/non_secure/port.c + GCC/ARM_CM33_NTZ/non_secure/portasm.c + GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c> + + $<$: + GCC/ARM_CM33_NTZ/non_secure/port.c + GCC/ARM_CM33_NTZ/non_secure/portasm.c + GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c + ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c> + + $<$: + GCC/ARM_CM35P/non_secure/port.c + GCC/ARM_CM35P/non_secure/portasm.c + GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c> + + $<$: + GCC/ARM_CM35P/secure/secure_context_port.c + GCC/ARM_CM35P/secure/secure_context.c + GCC/ARM_CM35P/secure/secure_heap.c + GCC/ARM_CM35P/secure/secure_init.c> + + $<$: + GCC/ARM_CM35P_NTZ/non_secure/port.c + GCC/ARM_CM35P_NTZ/non_secure/portasm.c + GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c> + + # ARMv8.1-M ports for GCC + $<$: + GCC/ARM_CM55/non_secure/port.c + GCC/ARM_CM55/non_secure/portasm.c + GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c> + + $<$: + GCC/ARM_CM55/secure/secure_context_port.c + GCC/ARM_CM55/secure/secure_context.c + GCC/ARM_CM55/secure/secure_heap.c + GCC/ARM_CM55/secure/secure_init.c> + + $<$: + GCC/ARM_CM55_NTZ/non_secure/port.c + GCC/ARM_CM55_NTZ/non_secure/portasm.c + GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c> + + $<$: + GCC/ARM_CM55_NTZ/non_secure/port.c + GCC/ARM_CM55_NTZ/non_secure/portasm.c + GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c + ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c> + + $<$: + GCC/ARM_CM52/non_secure/port.c + GCC/ARM_CM52/non_secure/portasm.c + GCC/ARM_CM52/non_secure/mpu_wrappers_v2_asm.c> + + $<$: + GCC/ARM_CM52/secure/secure_context_port.c + GCC/ARM_CM52/secure/secure_context.c + GCC/ARM_CM52/secure/secure_heap.c + GCC/ARM_CM52/secure/secure_init.c> + + $<$: + GCC/ARM_CM52_NTZ/non_secure/port.c + GCC/ARM_CM52_NTZ/non_secure/portasm.c + GCC/ARM_CM52_NTZ/non_secure/mpu_wrappers_v2_asm.c> + + $<$: + GCC/ARM_CM52_NTZ/non_secure/port.c + GCC/ARM_CM52_NTZ/non_secure/portasm.c + GCC/ARM_CM52_NTZ/non_secure/mpu_wrappers_v2_asm.c + ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c> + + $<$: + GCC/ARM_CM85/non_secure/port.c + GCC/ARM_CM85/non_secure/portasm.c + GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c> + + $<$: + GCC/ARM_CM85/secure/secure_context_port.c + GCC/ARM_CM85/secure/secure_context.c + GCC/ARM_CM85/secure/secure_heap.c + GCC/ARM_CM85/secure/secure_init.c> + + $<$: + GCC/ARM_CM85_NTZ/non_secure/port.c + GCC/ARM_CM85_NTZ/non_secure/portasm.c + GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c> + + $<$: + GCC/ARM_CM85_NTZ/non_secure/port.c + GCC/ARM_CM85_NTZ/non_secure/portasm.c + GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c + ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c> + + $<$: + GCC/ARM_STAR_MC3/non_secure/port.c + GCC/ARM_STAR_MC3/non_secure/portasm.c + GCC/ARM_STAR_MC3/non_secure/mpu_wrappers_v2_asm.c> + + $<$: + GCC/ARM_STAR_MC3/secure/secure_context_port.c + GCC/ARM_STAR_MC3/secure/secure_context.c + GCC/ARM_STAR_MC3/secure/secure_heap.c + GCC/ARM_STAR_MC3/secure/secure_init.c> + + $<$: + GCC/ARM_STAR_MC3_NTZ/non_secure/port.c + GCC/ARM_STAR_MC3_NTZ/non_secure/portasm.c + GCC/ARM_STAR_MC3_NTZ/non_secure/mpu_wrappers_v2_asm.c> + + $<$: + GCC/ARM_STAR_MC3_NTZ/non_secure/port.c + GCC/ARM_STAR_MC3_NTZ/non_secure/portasm.c + GCC/ARM_STAR_MC3_NTZ/non_secure/mpu_wrappers_v2_asm.c + ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c> + + # ARMv7-R ports for GCC + $<$: + GCC/ARM_CR5/port.c + GCC/ARM_CR5/portASM.S> + + $<$: + GCC/ARM_CRx_MPU/port.c + GCC/ARM_CRx_MPU/portASM.S + GCC/ARM_CRx_MPU/mpu_wrappers_v2_asm.S> + + $<$: + GCC/ARM_CRx_No_GIC/port.c + GCC/ARM_CRx_No_GIC/portASM.S> + + # ARMv8-R ports for GCC + $<$: + GCC/ARM_CR82/port.c + GCC/ARM_CR82/portASM.S + GCC/ARM_CR82/mpu_wrappers_v2_asm.c> + + # ARMv4T ARM7TDMI ports for GCC + $<$: + GCC/ARM7_AT91FR40008/port.c + GCC/ARM7_AT91FR40008/portISR.c> + + $<$: + GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c + GCC/ARM7_AT91SAM7S/port.c + GCC/ARM7_AT91SAM7S/portISR.c> + + $<$: + GCC/ARM7_LPC2000/port.c + GCC/ARM7_LPC2000/portISR.c> + + $<$: + GCC/ARM7_LPC23xx/port.c + GCC/ARM7_LPC23xx/portISR.c> + + $<$: + GCC/STR75x/port.c + GCC/STR75x/portISR.c> + + # Microchip (formerly Ateml) AVR8 ports for GCC + $<$: + GCC/ATMega323/port.c> + + $<$: + ThirdParty/GCC/ATmega/port.c> + + $<$: + ThirdParty/Partner-Supported-Ports/GCC/AVR_AVRDx/port.c> + + $<$: + ThirdParty/Partner-Supported-Ports/GCC/AVR_Mega0/port.c> + + # Microchip (formerly Ateml) AVR32 port for GCC + $<$: + GCC/AVR32_UC3/exception.S + GCC/AVR32_UC3/port.c> + + # NXP (formerly Motorola, Freescale) Cold Fire and 68HCS12 ports for GCC + $<$: + GCC/ColdFire_V2/port.c + GCC/ColdFire_V2/portasm.S> + + $<$: + GCC/HCS12/port.c> + + # Cortus APS3 soft core port for GCC + $<$: + GCC/CORTUS_APS3/port.c> + + # Renesas (formerly Hitach) H8S port for GCC + $<$: + GCC/H8S2329/port.c> + + # x86 / IA32 flat memory model port for GCC + $<$: + GCC/IA32_flat/port.c + GCC/IA32_flat/portASM.S> + + # Xilinx MicroBlaze soft core ports for GCC + $<$: + GCC/MicroBlaze/port.c + GCC/MicroBlaze/portasm.s> + + $<$: + GCC/MicroBlazeV8/port.c + GCC/MicroBlazeV8/port_exceptions.c + GCC/MicroBlazeV8/portasm.S> + + $<$: + GCC/MicroBlazeV9/port.c + GCC/MicroBlazeV9/port_exceptions.c + GCC/MicroBlazeV9/portasm.S> + + # Xilinx PCC4XX soft core ports for GCC + $<$: + GCC/PPC405_Xilinx/port.c + GCC/PPC405_Xilinx/portasm.S> + + $<$: + GCC/PPC440_Xilinx/port.c + GCC/PPC440_Xilinx/portasm.S> + + # Texas Instruments MSP430 port for GCC + $<$: + GCC/MSP430F449/port.c> + + # Intel (formerly Altera) NIOS II soft core port for GCC + $<$: + GCC/NiosII/port.c + GCC/NiosII/port_asm.S> + + # RISC-V architecture ports for GCC + $<$: + GCC/RISC-V/port.c + GCC/RISC-V/portASM.S> + + $<$: + GCC/RISC-V/port.c + GCC/RISC-V/portASM.S> + + $<$: + GCC/RISC-V/port.c + GCC/RISC-V/portASM.S> + + # Renesas RL78 port for GCC + $<$: + GCC/RL78/port.c + GCC/RL78/portasm.S> + + # Renesas RX architecture ports for GCC + $<$: + GCC/RX100/port.c> + + $<$: + GCC/RX200/port.c> + + $<$: + GCC/RX600/port.c> + + $<$: + GCC/RX600v2/port.c> + + $<$: + GCC/RX700v3_DPFPU/port.c> + + # Infineon TriCore 1782 port for GCC + $<$: + GCC/TriCore_1782/port.c + GCC/TriCore_1782/porttrap.c> + + # Synopsys ARC architecture ports for GCC + $<$: + ThirdParty/GCC/ARC_EM_HS/arc_freertos_exceptions.c + ThirdParty/GCC/ARC_EM_HS/arc_support.s + ThirdParty/GCC/ARC_EM_HS/freertos_tls.c + ThirdParty/GCC/ARC_EM_HS/port.c> + + $<$: + ThirdParty/GCC/ARC_v1/arc_freertos_exceptions.c + ThirdParty/GCC/ARC_v1/arc_support.s + ThirdParty/GCC/ARC_v1/port.c> + + # Posix Simulator port for GCC + $<$: + ThirdParty/GCC/Posix/port.c + ThirdParty/GCC/Posix/utils/wait_for_event.c> + + # Xtensa LX / Espressif ESP32 port for GCC + $<$: + ThirdParty/GCC/Xtensa_ESP32/FreeRTOS-openocd.c + ThirdParty/GCC/Xtensa_ESP32/port.c + ThirdParty/GCC/Xtensa_ESP32/portasm.S + ThirdParty/GCC/Xtensa_ESP32/xtensa_context.S + ThirdParty/GCC/Xtensa_ESP32/xtensa_init.c + ThirdParty/GCC/Xtensa_ESP32/xtensa_intr_asm.S + ThirdParty/GCC/Xtensa_ESP32/xtensa_intr.c + ThirdParty/GCC/Xtensa_ESP32/xtensa_loadstore_handler.S + ThirdParty/GCC/Xtensa_ESP32/xtensa_overlay_os_hook.c + ThirdParty/GCC/Xtensa_ESP32/xtensa_vector_defaults.S + ThirdParty/GCC/Xtensa_ESP32/xtensa_vectors.S> + + # Renesas (formerly NEC) 78K port for IAR EW78K + $<$: + IAR/78K0R/port.c + IAR/78K0R/portasm.s26> + + # ARMv7-A ports for IAR EWARM + $<$: + IAR/ARM_CA5_No_GIC/port.c + IAR/ARM_CA5_No_GIC/portASM.s> + + $<$: + IAR/ARM_CA9/port.c + IAR/ARM_CA9/portASM.s> + + # ARMv6-M port for IAR EWARM + $<$: + IAR/ARM_CM0/port.c + IAR/ARM_CM0/portasm.s> + + # ARMv7-M port for IAR EWARM + $<$: + IAR/ARM_CM3/port.c + IAR/ARM_CM3/portasm.s> + + # ARMv7E-M ports for IAR EWARM + $<$: + IAR/ARM_CM4F/port.c + IAR/ARM_CM4F/portasm.s> + + $<$: + IAR/ARM_CM4F_MPU/port.c + IAR/ARM_CM4F_MPU/portasm.s + IAR/ARM_CM4F_MPU/mpu_wrappers_v2_asm.S> + + $<$: + IAR/ARM_CM7/r0p1/port.c + IAR/ARM_CM7/r0p1/portasm.s> + + # ARMv8-M Ports for IAR EWARM + $<$: + IAR/ARM_CM23/non_secure/port.c + IAR/ARM_CM23/non_secure/portasm.s + IAR/ARM_CM23/non_secure/mpu_wrappers_v2_asm.S> + + $<$: + IAR/ARM_CM23/secure/secure_context_port_asm.s + IAR/ARM_CM23/secure/secure_context.c + IAR/ARM_CM23/secure/secure_heap.c + IAR/ARM_CM23/secure/secure_init.c> + + $<$: + IAR/ARM_CM23_NTZ/non_secure/port.c + IAR/ARM_CM23_NTZ/non_secure/portasm.s + IAR/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.S> + + $<$: + IAR/ARM_CM33/non_secure/port.c + IAR/ARM_CM33/non_secure/portasm.s + IAR/ARM_CM33/non_secure/mpu_wrappers_v2_asm.S> + + $<$: + IAR/ARM_CM33/secure/secure_context_port_asm.s + IAR/ARM_CM33/secure/secure_context.c + IAR/ARM_CM33/secure/secure_heap.c + IAR/ARM_CM33/secure/secure_init.c> + + $<$: + IAR/ARM_CM33_NTZ/non_secure/port.c + IAR/ARM_CM33_NTZ/non_secure/portasm.s + IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S> + + $<$: + IAR/ARM_CM33_NTZ/non_secure/port.c + IAR/ARM_CM33_NTZ/non_secure/portasm.s + IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S + ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c> + + $<$: + IAR/ARM_CM35P/non_secure/port.c + IAR/ARM_CM35P/non_secure/portasm.s + IAR/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.S> + + $<$: + IAR/ARM_CM35P/secure/secure_context_port_asm.s + IAR/ARM_CM35P/secure/secure_context.c + IAR/ARM_CM35P/secure/secure_heap.c + IAR/ARM_CM35P/secure/secure_init.c> + + $<$: + IAR/ARM_CM35P_NTZ/non_secure/port.c + IAR/ARM_CM35P_NTZ/non_secure/portasm.s + IAR/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.S> + + # ARMv8.1-M ports for IAR EWARM + $<$: + IAR/ARM_CM55/non_secure/port.c + IAR/ARM_CM55/non_secure/portasm.s + IAR/ARM_CM55/non_secure/mpu_wrappers_v2_asm.S> + + $<$: + IAR/ARM_CM55/secure/secure_context_port_asm.s + IAR/ARM_CM55/secure/secure_context.c + IAR/ARM_CM55/secure/secure_heap.c + IAR/ARM_CM55/secure/secure_init.c> + + $<$: + IAR/ARM_CM55_NTZ/non_secure/port.c + IAR/ARM_CM55_NTZ/non_secure/portasm.s + IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S> + + $<$: + IAR/ARM_CM55_NTZ/non_secure/port.c + IAR/ARM_CM55_NTZ/non_secure/portasm.s + IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S + ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c> + + $<$: + IAR/ARM_CM52/non_secure/port.c + IAR/ARM_CM52/non_secure/portasm.s + IAR/ARM_CM52/non_secure/mpu_wrappers_v2_asm.S> + + $<$: + IAR/ARM_CM52/secure/secure_context_port_asm.s + IAR/ARM_CM52/secure/secure_context.c + IAR/ARM_CM52/secure/secure_heap.c + IAR/ARM_CM52/secure/secure_init.c> + + $<$: + IAR/ARM_CM52_NTZ/non_secure/port.c + IAR/ARM_CM52_NTZ/non_secure/portasm.s + IAR/ARM_CM52_NTZ/non_secure/mpu_wrappers_v2_asm.S> + + $<$: + IAR/ARM_CM52_NTZ/non_secure/port.c + IAR/ARM_CM52_NTZ/non_secure/portasm.s + IAR/ARM_CM52_NTZ/non_secure/mpu_wrappers_v2_asm.S + ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c> + + $<$: + IAR/ARM_CM85/non_secure/port.c + IAR/ARM_CM85/non_secure/portasm.s + IAR/ARM_CM85/non_secure/mpu_wrappers_v2_asm.S> + + $<$: + IAR/ARM_CM85/secure/secure_context_port_asm.s + IAR/ARM_CM85/secure/secure_context.c + IAR/ARM_CM85/secure/secure_heap.c + IAR/ARM_CM85/secure/secure_init.c> + + $<$: + IAR/ARM_CM85_NTZ/non_secure/port.c + IAR/ARM_CM85_NTZ/non_secure/portasm.s + IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S> + + $<$: + IAR/ARM_CM85_NTZ/non_secure/port.c + IAR/ARM_CM85_NTZ/non_secure/portasm.s + IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S + ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c> + + $<$: + IAR/ARM_STAR_MC3/non_secure/port.c + IAR/ARM_STAR_MC3/non_secure/portasm.s + IAR/ARM_STAR_MC3/non_secure/mpu_wrappers_v2_asm.S> + + $<$: + IAR/ARM_STAR_MC3/secure/secure_context_port_asm.s + IAR/ARM_STAR_MC3/secure/secure_context.c + IAR/ARM_STAR_MC3/secure/secure_heap.c + IAR/ARM_STAR_MC3/secure/secure_init.c> + + $<$: + IAR/ARM_STAR_MC3_NTZ/non_secure/port.c + IAR/ARM_STAR_MC3_NTZ/non_secure/portasm.s + IAR/ARM_STAR_MC3_NTZ/non_secure/mpu_wrappers_v2_asm.S> + + $<$: + IAR/ARM_STAR_MC3_NTZ/non_secure/port.c + IAR/ARM_STAR_MC3_NTZ/non_secure/portasm.s + IAR/ARM_STAR_MC3_NTZ/non_secure/mpu_wrappers_v2_asm.S + ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c> + + # ARMv7-R Ports for IAR EWARM + $<$: + IAR/ARM_CRx_No_GIC/port.c + IAR/ARM_CRx_No_GIC/portASM.s> + + # Microchip (formerly Atmel) AVR8 ports for IAR EWAVR + $<$: + IAR/ATMega323/port.c + IAR/ATMega323/portmacro.s90> + + $<$: + IAR/AVR_AVRDx/port.c + IAR/AVR_AVRDx/portmacro.s90> + + $<$: + IAR/AVR_Mega0/port.c + IAR/AVR_Mega0/portmacro.s90> + + # Microchip (formerly Atmel) AVR32 port for IAR Embedded Workbench for AVR32 + $<$: + IAR/AVR32_UC3/exception.s82 + IAR/AVR32_UC3/port.c + IAR/AVR32_UC3/read.c + IAR/AVR32_UC3/write.c> + + # Texas Instruments MSP430 ports for IAR Embedded Workbench for MSP430 + $<$: + IAR/MSP430/port.c + IAR/MSP430/portext.s43> + + $<$: + IAR/MSP430X/port.c + IAR/MSP430X/portext.s43> + + # RISC-V architecture port for IAR Embedded Workbench for RISC-V + $<$: + IAR/RISC-V/port.c + IAR/RISC-V/portASM.s> + + $<$: + IAR/RISC-V/port.c + IAR/RISC-V/portASM.s> + + # Renesas RL78 port for IAR EWRL78 + $<$: + IAR/RL78/port.c + IAR/RL78/portasm.s87> + + # Renesas RX architecture ports for IAR EWRX + $<$: + IAR/RX100/port.c + IAR/RX100/port_asm.s> + + $<$: + IAR/RX600/port.c + IAR/RX600/port_asm.s> + + $<$: + IAR/RX700v3_DPFPU/port.c> + + $<$: + IAR/RXv2/port.c + IAR/RXv2/port_asm.s> + + # Renesas (formerly NEC) V850ES port for IAR EWV850 + $<$: + IAR/V850ES/port.c + IAR/V850ES/portasm_Fx3.s85> + + $<$: + IAR/V850ES/port.c + IAR/V850ES/portasm_Hx2.s85> + + # ARMv4T ARM7TDMI ports for IAR Embedded Workbench for ARM + $<$: + IAR/STR71x/port.c + IAR/STR71x/portasm.s79> + + $<$: + IAR/STR75x/port.c + IAR/STR75x/portasm.s79> + + $<$: + IAR/LPC2000/port.c + IAR/LPC2000/portasm.s79> + + $<$: + IAR/AtmelSAM7S64/port.c + IAR/AtmelSAM7S64/portasm.s79> + + # ARMv5TE ARM926 ports for IAR Embedded Workbench for ARM + $<$: + IAR/STR91x/port.c + IAR/STR91x/portasm.s79> + + $<$: + IAR/AtmelSAM9XE/port.c + IAR/AtmelSAM9XE/portasm.s79> + + # ARM Cortex-M4F port for the MikroElektronika MikroC compiler + $<$: + MikroC/ARM_CM4F/port.c> + + # Microchip PIC18 8-bit MCU port for MPLAB XC8 + $<$: + MPLAB/PIC18F/port.c> + + # Microchip PIC24 16-bit MCU port for MPLAB XC16 + $<$: + MPLAB/PIC24_dsPIC/port.c + MPLAB/PIC24_dsPIC/portasm_PIC24.S> # TODO: What to do with portasm_dsPIC.S ? + + # Microchip MIPS 32-Bit MCU ports for MPLAB XC32 + $<$: + MPLAB/PIC32MEC14xx/port.c + MPLAB/PIC32MEC14xx/port_asm.S> + + $<$: + MPLAB/PIC32MX/port.c + MPLAB/PIC32MX/port_asm.S> + + $<$: + MPLAB/PIC32MZ/port.c + MPLAB/PIC32MZ/port_asm.S> + + # Windows Simulator for Microsoft Visual C Compiler and MinGW GCC + $<$: + MSVC-MingW/port.c> + + # 16 bit DOS ports for Open Watcom + $<$: + oWatcom/16BitDOS/common/portcomn.c + oWatcom/16BitDOS/Flsh186/port.c> + + $<$: + oWatcom/16BitDOS/common/portcomn.c + oWatcom/16BitDOS/PC/port.c> + + $<$: + Paradigm/Tern_EE/large_untested/port.c> + + $<$: + Paradigm/Tern_EE/small/port.c> + + # Renesas RX mcu ports for Renesas CC-RX + $<$: + Renesas/RX100/port.c + Renesas/RX100/port_asm.src> + + $<$: + Renesas/RX200/port.c + Renesas/RX200/port_asm.src> + + $<$: + Renesas/RX600/port.c + Renesas/RX600/port_asm.src> + + $<$: + Renesas/RX600v2/port.c + Renesas/RX600v2/port_asm.src> + + $<$: + Renesas/RX700v3_DPFPU/port.c + Renesas/RX700v3_DPFPU/port_asm.src> + + # Renesas (formerly Hitach) SHA2 SuperH port for the Renesas SH C Compiler + $<$: + Renesas/SH2A_FPU/port.c + Renesas/SH2A_FPU/portasm.src> + + # Texas Instruments MSP430 port for Rowley CrossWorks + $<$: + Rowley/MSP430F449/port.c + Rowley/MSP430F449/portext.asm> + + # ARMv7-A Cortex-A9 port for ARM RVDS / armcc + $<$: + RVDS/ARM_CA9/port.c + RVDS/ARM_CA9/portASM.s> + + # ARMv6-M port for ARM RVDS / armcc + $<$: + RVDS/ARM_CM0/port.c> + + # ARMv7-M port for ARM RVDS / armcc + $<$: + RVDS/ARM_CM3/port.c> + + # ARMv7E-M ports for ARM RVDS / armcc + $<$: + RVDS/ARM_CM4_MPU/port.c + RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c> + + $<$: + RVDS/ARM_CM4F/port.c> + + $<$: + RVDS/ARM_CM7/r0p1/port.c> + + # ARMv4T / ARM7TDMI LPC21XX port for ARM RVDS / armcc + $<$: + RVDS/ARM7_LPC21xx/port.c + RVDS/ARM7_LPC21xx/portASM.s> + + # Cygnal c8051 port for SDCC (Small Device C Compiler) + $<$: + SDCC/Cygnal/port.c> + + # Infineon (formerly Fujitsu, Spansion, Cypress) MB9x ports for Softune C Compiler + $<$: + Softune/MB91460/__STD_LIB_sbrk.c + Softune/MB91460/port.c> + + $<$: + Softune/MB96340/__STD_LIB_sbrk.c + Softune/MB96340/port.c> + + # ARMv7E-M (Cortex-M4F) port for TASKING VX-toolset for ARM + $<$: + Tasking/ARM_CM4F/port.c + Tasking/ARM_CM4F/port_asm.asm> + + # Port for C-SKY T-HEAD CK802 + $<$: + ThirdParty/CDK/T-HEAD_CK802/port.c + ThirdParty/CDK/T-HEAD_CK802/portasm.S> + + # Tensilica Xtensa port for XCC + $<$: + ThirdParty/XCC/Xtensa/port.c + ThirdParty/XCC/Xtensa/portasm.S + ThirdParty/XCC/Xtensa/portclib.c + ThirdParty/XCC/Xtensa/xtensa_context.S + ThirdParty/XCC/Xtensa/xtensa_init.c + ThirdParty/XCC/Xtensa/xtensa_intr_asm.S + ThirdParty/XCC/Xtensa/xtensa_intr.c + ThirdParty/XCC/Xtensa/xtensa_overlay_os_hook.c + ThirdParty/XCC/Xtensa/xtensa_vectors.S> + + # Microchip PIC18 port for WIZ-C + $<$: + WizC/PIC18/port.c + WizC/PIC18/Drivers/Tick/isrTick.c + WizC/PIC18/Drivers/Tick/Tick.c> +) + +if( FREERTOS_PORT MATCHES "GCC_ARM_CM(3|4)_MPU" OR + FREERTOS_PORT STREQUAL "IAR_ARM_CM4F_MPU" OR + FREERTOS_PORT STREQUAL "RVDS_ARM_CM4_MPU" OR + FREERTOS_PORT STREQUAL "GCC_ARM_CRX_MPU" OR + FREERTOS_PORT MATCHES "GCC_ARM_(CM23|CM33|CM52|CM55|CM85|STAR_MC3)_NTZ_NONSECURE" OR + FREERTOS_PORT MATCHES "GCC_ARM_(CM23|CM33|CM52|CM55|CM85|STAR_MC3)_NONSECURE" OR + FREERTOS_PORT MATCHES "GCC_ARM_(CM33|CM52|CM55|CM85|STAR_MC3)_TFM" OR + FREERTOS_PORT MATCHES "GCC_ARM_CR82" OR + FREERTOS_PORT MATCHES "IAR_ARM_(CM23|CM33|CM52|CM55|CM85|STAR_MC3)_NTZ_NONSECURE" OR + FREERTOS_PORT MATCHES "IAR_ARM_(CM23|CM33|CM52|CM55|CM85|STAR_MC3)_NONSECURE" OR + FREERTOS_PORT MATCHES "IAR_ARM_(CM33|CM52|CM55|CM85|STAR_MC3)_TFM" +) + target_sources(freertos_kernel_port PRIVATE + Common/mpu_wrappers.c + Common/mpu_wrappers_v2.c + ) +endif() + +if (DEFINED FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG ) + + if(${CMAKE_C_COMPILER_ID} STREQUAL "GNU") + message(FATAL_ERROR "ARMv8.1-M PACBTI support in the kernel is not yet enabled for GNU toolchain due to known issues.") + endif() + + if(FREERTOS_PORT MATCHES ".*ARM_(CM52|CM85|STAR_MC3)") + if(FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG STREQUAL "ARM_V_8_1_M_PACBTI_CONFIG_STANDARD") + target_compile_options(freertos_kernel_port PUBLIC $<$:-mbranch-protection=standard>) + target_compile_options(freertos_kernel_port PUBLIC $<$:$<$:--branch_protection=bti+pac-ret>>) + target_compile_definitions(freertos_config + INTERFACE + configENABLE_PAC=1 + configENABLE_BTI=1 + ) + elseif(FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG STREQUAL "ARM_V_8_1_M_PACBTI_CONFIG_PACRET_LEAF_BTI") + if(${CMAKE_C_COMPILER_ID} STREQUAL "ARMClang") + target_compile_options(freertos_kernel_port + PUBLIC + -mbranch-protection=bti+pac-ret+leaf + ) + target_compile_definitions(freertos_config + INTERFACE + configENABLE_PAC=1 + configENABLE_BTI=1 + ) + elseif(${CMAKE_C_COMPILER_ID} STREQUAL "IAR") + message(FATAL_ERROR "ARM_V_8_1_M_PACBTI_CONFIG_PACRET_LEAF_BTI PACBTI option is not supported on IAR Compiler.") + endif() + elseif(FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG STREQUAL "ARM_V_8_1_M_PACBTI_CONFIG_PACRET") + target_compile_options(freertos_kernel_port PUBLIC $<$:-mbranch-protection=pac-ret>) + target_compile_options(freertos_kernel_port PUBLIC $<$:$<$:--branch_protection=pac-ret>>) + target_compile_definitions(freertos_config + INTERFACE + configENABLE_PAC=1 + ) + elseif(FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG STREQUAL "ARM_V_8_1_M_PACBTI_CONFIG_PACRET_LEAF") + if(${CMAKE_C_COMPILER_ID} STREQUAL "ARMClang") + target_compile_options(freertos_kernel_port + PUBLIC + -mbranch-protection=pac-ret+leaf + ) + target_compile_definitions(freertos_config + INTERFACE + configENABLE_PAC=1 + ) + elseif(${CMAKE_C_COMPILER_ID} STREQUAL "IAR") + message(FATAL_ERROR "ARM_V_8_1_M_PACBTI_CONFIG_PACRET_LEAF PACBTI option is not supported on IAR Compiler.") + endif() + elseif(FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG STREQUAL "ARM_V_8_1_M_PACBTI_CONFIG_BTI") + target_compile_options(freertos_kernel_port PUBLIC $<$:-mbranch-protection=bti>) + target_compile_options(freertos_kernel_port PUBLIC $<$:$<$:--branch_protection=bti>>) + target_compile_definitions(freertos_config + INTERFACE + configENABLE_BTI=1 + ) + elseif(FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG STREQUAL "ARM_V_8_1_M_PACBTI_CONFIG_NONE") + if(${CMAKE_C_COMPILER_ID} STREQUAL "ARMClang") + target_compile_options(freertos_kernel_port + PUBLIC + -mbranch-protection=none + ) + endif() + target_compile_definitions(freertos_config + INTERFACE + configENABLE_PAC=0 + configENABLE_BTI=0 + ) + else() + message(FATAL_ERROR "Invalid FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG configuration, the supported configurations are + ARM_V_8_1_M_PACBTI_CONFIG_STANDARD, + ARM_V_8_1_M_PACBTI_CONFIG_PACRET_LEAF_BTI, + ARM_V_8_1_M_PACBTI_CONFIG_PACRET, + ARM_V_8_1_M_PACBTI_CONFIG_PACRET_LEAF, + ARM_V_8_1_M_PACBTI_CONFIG_BTI, + ARM_V_8_1_M_PACBTI_CONFIG_NONE + ") + endif() + if(NOT FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG STREQUAL "ARM_V_8_1_M_PACBTI_CONFIG_NONE") + # The reason why `--library_security=pacbti-m` link option is defined for both `freertos_kernel_port`, and + # `freertos_kernel` targets even though `freertos_kernel_port` gets linked to `freertos_kernel` is that the + # `freertos_kernel_port` is an object library where its linker options don't propagate to the targets that + # link against it. + target_link_options(freertos_kernel_port + PUBLIC + --library_security=pacbti-m + ) + target_link_options(freertos_kernel + PUBLIC + --library_security=pacbti-m + ) + endif() + else() + message(FATAL_ERROR "FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG option is currently only supported on ARM Cortex-M85|M52 and Arm China STAR-MC3 FreeRTOS ports.") + endif() +endif() + +add_library(freertos_kernel_port_headers INTERFACE) + +target_include_directories(freertos_kernel_port_headers INTERFACE + # TEMPLATE Port + $<$:${CMAKE_CURRENT_LIST_DIR}/template> + + # 16-Bit DOS ports for BCC + $<$: + ${CMAKE_CURRENT_LIST_DIR}/BCC/16BitDOS/common + ${CMAKE_CURRENT_LIST_DIR}/BCC/16BitDOS/Flsh186> + + $<$: + ${CMAKE_CURRENT_LIST_DIR}/BCC/16BitDOS/common + ${CMAKE_CURRENT_LIST_DIR}/BCC/16BitDOS/PC> + + # ARMv7-M port for Texas Instruments Code Composer Studio + $<$:${CMAKE_CURRENT_LIST_DIR}/CCS/ARM_CM3> + + # ARMv7E-M port for Texas Instruments Code Composer Studio + $<$:${CMAKE_CURRENT_LIST_DIR}/CCS/ARM_CM4F> + + # ARMv7-R port for Texas Instruments Code Composer Studio + $<$:${CMAKE_CURRENT_LIST_DIR}/CCS/ARM_Cortex-R4> + + # Texas Instruments MSP430 port for Texas Instruments Code Composer Studio + $<$:${CMAKE_CURRENT_LIST_DIR}/CCS/MSP430X> + + # NXP (formerly Motorola, Freescale) Cold Fire and 68HCS12 ports for Code Warrior + $<$:${CMAKE_CURRENT_LIST_DIR}/CodeWarrior/ColdFire_V1> + $<$:${CMAKE_CURRENT_LIST_DIR}/CodeWarrior/ColdFire_V2> + $<$:${CMAKE_CURRENT_LIST_DIR}/CodeWarrior/HCS12> + + # ARMv7-A port for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CA9> + + # ARMv8-A ports for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_AARCH64> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_AARCH64_SRE> + + # ARMv6-M port for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM0> + + # ARMv6-M / Cortex-M0 Raspberry PI RP2040 port for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/ThirdParty/GCC/RP2040/include> + + # ARMv7-M ports for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM3> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM3_MPU> + + # ARMv7E-M ports for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM4_MPU> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM4F> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM7/r0p1> + + # ARMv8-M ports for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM23/non_secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM23/secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM23_NTZ/non_secure> + + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM33/non_secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM33/secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM33_NTZ/non_secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM33_NTZ/non_secure> + + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM35P/non_secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM35P/secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM35P_NTZ/non_secure> + + # ARMv8.1-M ports for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM55/non_secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM55/secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM55_NTZ/non_secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM55_NTZ/non_secure> + + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM52/non_secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM52/secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM52_NTZ/non_secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM52_NTZ/non_secure> + + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM85/non_secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM85/secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM85_NTZ/non_secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM85_NTZ/non_secure> + + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_STAR_MC3/non_secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_STAR_MC3/secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_STAR_MC3_NTZ/non_secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_STAR_MC3_NTZ/non_secure> + + # ARMv7-R ports for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CR5> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CRx_MPU> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CRx_No_GIC> + + # ARMv8-R ports for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CR82> + + # ARMv4T ARM7TDMI ports for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM7_AT91FR40008> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM7_AT91SAM7S> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM7_LPC2000> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM7_LPC23xx> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/STR75x> + + # Microchip (formerly Ateml) AVR8 ports for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ATMega323> + $<$:${CMAKE_CURRENT_LIST_DIR}/ThirdParty/GCC/ATmega> + $<$:${CMAKE_CURRENT_LIST_DIR}/ThirdParty/Partner-Supported-Ports/GCC/AVR_AVRDx> + $<$:${CMAKE_CURRENT_LIST_DIR}/ThirdParty/Partner-Supported-Ports/GCC/AVR_Mega0> + + # Microchip (formerly Ateml) AVR32 port for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/AVR32_UC3> + + # NXP (formerly Motorola, Freescale) Cold Fire and 68HCS12 ports for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ColdFire_V2> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/HCS12> + + # Cortus APS3 soft core port for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/CORTUS_APS3> + + # Renesas (formerly Hitach) H8S port for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/H8S2329> + + # x86 / IA32 flat memory model port for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/IA32_flat> + + # Intel (formerly Altera) NIOS II soft core port for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/NiosII> + + # Texas Instruments MSP430 port for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/MSP430F449> + + # Xilinx MicroBlaze soft core ports for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/MicroBlaze> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/MicroBlazeV8> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/MicroBlazeV9> + + # Xilinx PCC4XX soft core ports for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/PPC405_Xilinx> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/PPC440_Xilinx> + + # RISC-V architecture ports for GCC + $<$: + ${CMAKE_CURRENT_LIST_DIR}/GCC/RISC-V + ${CMAKE_CURRENT_LIST_DIR}/GCC/RISC-V/chip_specific_extensions/RISCV_MTIME_CLINT_no_extensions> + + $<$: + ${CMAKE_CURRENT_LIST_DIR}/GCC/RISC-V + ${CMAKE_CURRENT_LIST_DIR}/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM> + + $<$: + ${CMAKE_CURRENT_LIST_DIR}/GCC/RISC-V + ${CMAKE_CURRENT_LIST_DIR}/GCC/RISC-V/chip_specific_extensions/${FREERTOS_RISCV_EXTENSION}> + + # Renesas RL78 port for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/RL78> + + # Renesas RX architecture ports for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/RX100> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/RX200> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/RX600> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/RX600v2> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/RX700v3_DPFPU> + + # Infineon TriCore 1782 port for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/TriCore_1782> + + # Synopsys ARC architecture ports for GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/ThirdParty/GCC/ARC_EM_HS> + $<$:${CMAKE_CURRENT_LIST_DIR}/ThirdParty/GCC/ARC_v1> + + # Posix Simulator port for GCC + $<$: + ${CMAKE_CURRENT_LIST_DIR}/ThirdParty/GCC/Posix + ${CMAKE_CURRENT_LIST_DIR}/ThirdParty/GCC/Posix/utils> + + # Xtensa LX / Espressif ESP32 port for GCC + $<$: + ${CMAKE_CURRENT_LIST_DIR}/ThirdParty/GCC/Xtensa_ESP32 + ${CMAKE_CURRENT_LIST_DIR}/ThirdParty/GCC/Xtensa_ESP32/include> + + # Renesas (formerly NEC) 78K port for IAR EW78K + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/78K0R> + + # ARMv7-A ports for IAR EWARM + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CA5_No_GIC> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CA9> + + # ARMv6-M port for IAR EWARM + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM0> + + # ARMv7-M port for IAR EWARM + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM3> + + # ARMv7E-M ports for IAR EWARM + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM4F> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM4F_MPU> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM7/r0p1> + + # ARMv8-M Ports for IAR EWARM + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM23/non_secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM23/secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM23_NTZ/non_secure> + + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM33/non_secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM33/secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM33_NTZ/non_secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM33_NTZ/non_secure> + + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM35P/non_secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM35P/secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM35P_NTZ/non_secure> + + # ARMv8.1-M ports for IAR EWARM + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM55/non_secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM55/secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM55_NTZ/non_secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM55_NTZ/non_secure> + + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM52/non_secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM52/secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM52_NTZ/non_secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM52_NTZ/non_secure> + + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM85/non_secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM85/secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM85_NTZ/non_secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM85_NTZ/non_secure> + + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_STAR_MC3/non_secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_STAR_MC3/secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_STAR_MC3_NTZ/non_secure> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_STAR_MC3_NTZ/non_secure> + + # ARMv7-R Ports for IAR EWARM + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CRx_No_GIC> + + # ARMv4T ARM7TDMI ports for IAR Embedded Workbench for ARM + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/STR71x> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/STR75x> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/LPC2000> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/AtmelSAM7S64> + + # ARMv5TE ARM926 ports for IAR Embedded Workbench for ARM + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/STR91x> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/AtmelSAM9XE> + + # Microchip (formerly Atmel) AVR8 ports for IAR EWAVR + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/ATMega323> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/AVR_AVRDx> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/AVR_Mega0> + + # Microchip (formerly Atmel) AVR32 port for IAR Embedded Workbench for AVR32 + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/AVR32_UC3> + + # Texas Instruments MSP430 ports for IAR Embedded Workbench for MSP430 + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/MSP430> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/MSP430X> + + # RISC-V architecture port for IAR Embedded Workbench for RISC-V + $<$: + ${CMAKE_CURRENT_LIST_DIR}/IAR/RISC-V + ${CMAKE_CURRENT_LIST_DIR}/IAR/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions> + + $<$: + ${CMAKE_CURRENT_LIST_DIR}/IAR/RISC-V + ${CMAKE_CURRENT_LIST_DIR}/IAR/RISC-V/chip_specific_extensions/${FREERTOS_RISCV_EXTENSION}> + + # Renesas RL78 port for IAR EWRL78 + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/RL78> + + # Renesas RX architecture ports for IAR EWRX + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/RX100> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/RX600> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/RX700v3_DPFPU> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/RXv2> + + # Renesas (formerly NEC) V850ES port for IAR EWV850 + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/V850ES> + $<$:${CMAKE_CURRENT_LIST_DIR}/IAR/V850ES> + + # ARM Cortex-M4F port for the MikroElektronika MikroC compiler + $<$:${CMAKE_CURRENT_LIST_DIR}/MikroC/ARM_CM4F> + + # Microchip PIC18 8-bit MCU port for MPLAB XC8 + $<$:${CMAKE_CURRENT_LIST_DIR}/MPLAB/PIC18F> + + # Microchip PIC24 16-bit MCU port for MPLAB XC16 + $<$:${CMAKE_CURRENT_LIST_DIR}/MPLAB/PIC24_dsPIC> + + # Microchip MIPS 32-Bit MCU ports for MPLAB XC32 + $<$:${CMAKE_CURRENT_LIST_DIR}/MPLAB/PIC32MEC14xx> + $<$:${CMAKE_CURRENT_LIST_DIR}/MPLAB/PIC32MX> + $<$:${CMAKE_CURRENT_LIST_DIR}/MPLAB/PIC32MZ> + + # Windows Simulator for Microsoft Visual C Compiler and MinGW GCC + $<$:${CMAKE_CURRENT_LIST_DIR}/MSVC-MingW> + + # 16 bit DOS ports for Open Watcom + $<$: + ${CMAKE_CURRENT_LIST_DIR}/oWatcom/16BitDOS/common + ${CMAKE_CURRENT_LIST_DIR}/oWatcom/16BitDOS/Flsh186> + $<$: + ${CMAKE_CURRENT_LIST_DIR}/oWatcom/16BitDOS/common + ${CMAKE_CURRENT_LIST_DIR}/oWatcom/16BitDOS/PC> + + $<$:${CMAKE_CURRENT_LIST_DIR}/Paradigm/Tern_EE/large_untested> + $<$:${CMAKE_CURRENT_LIST_DIR}/Paradigm/Tern_EE/small> + + # Renesas RX mcu ports for Renesas CC-RX + $<$:${CMAKE_CURRENT_LIST_DIR}/Renesas/RX100> + $<$:${CMAKE_CURRENT_LIST_DIR}/Renesas/RX200> + $<$:${CMAKE_CURRENT_LIST_DIR}/Renesas/RX600> + $<$:${CMAKE_CURRENT_LIST_DIR}/Renesas/RX600v2> + $<$:${CMAKE_CURRENT_LIST_DIR}/Renesas/RX700v3_DPFPU> + + # Renesas (formerly Hitach) SHA2 SuperH port for the Renesas SH C Compiler + $<$:${CMAKE_CURRENT_LIST_DIR}/Renesas/SH2A_FPU> + + # Texas Instruments MSP430 port for Rowley CrossWorks + $<$:${CMAKE_CURRENT_LIST_DIR}/Rowley/MSP430F449> + + # ARMv7-A Cortex-A9 port for ARM RVDS / armcc + $<$:${CMAKE_CURRENT_LIST_DIR}/RVDS/ARM_CA9> + + # ARMv6-M port for ARM RVDS / armcc + $<$:${CMAKE_CURRENT_LIST_DIR}/RVDS/ARM_CM0> + + # ARMv7-M port for ARM RVDS / armcc + $<$:${CMAKE_CURRENT_LIST_DIR}/RVDS/ARM_CM3> + + # ARMv7E-M ports for ARM RVDS / armcc + $<$:${CMAKE_CURRENT_LIST_DIR}/RVDS/ARM_CM4_MPU> + $<$:${CMAKE_CURRENT_LIST_DIR}/RVDS/ARM_CM4F> + $<$:${CMAKE_CURRENT_LIST_DIR}/RVDS/ARM_CM7/r0p1> + + # ARMv4T / ARM7TDMI LPC21XX port for ARM RVDS / armcc + $<$:${CMAKE_CURRENT_LIST_DIR}/RVDS/ARM7_LPC21xx> + + # Cygnal c8051 port for SDCC (Small Device C Compiler) + $<$:${CMAKE_CURRENT_LIST_DIR}/SDCC/Cygnal> + + # Infineon (formerly Fujitsu, Spansion, Cypress) MB9x ports for Softune C Compiler + $<$:${CMAKE_CURRENT_LIST_DIR}/Softune/MB91460> + $<$:${CMAKE_CURRENT_LIST_DIR}/Softune/MB96340> + + # ARMv7E-M (Cortex-M4F) port for TASKING VX-toolset for ARM + $<$:${CMAKE_CURRENT_LIST_DIR}/Tasking/ARM_CM4F> + + # Port for C-SKY T-HEAD CK802 + $<$:${CMAKE_CURRENT_LIST_DIR}/ThirdParty/CDK/T-HEAD_CK802> + + # Tensilica Xtensa port for XCC + $<$:${CMAKE_CURRENT_LIST_DIR}/ThirdParty/XCC/Xtensa> + + # Microchip PIC18 port for WIZ-C + $<$:${CMAKE_CURRENT_LIST_DIR}/WizC/PIC18> +) + +target_link_libraries(freertos_kernel_port_headers + INTERFACE + $<$:hardware_sync> +) + +if(FREERTOS_PORT STREQUAL GCC_POSIX) + find_package(Threads REQUIRED) +endif() + +target_link_libraries(freertos_kernel_port + PUBLIC + $<$:pico_base_headers> + $<$:idf::esp32> + freertos_kernel_port_headers + PRIVATE + freertos_kernel_include + $<$:Threads::Threads> + "$<$:hardware_clocks;hardware_exception;pico_multicore>" + $<$:winmm> # Windows library which implements timers +) diff --git a/portable/CodeWarrior/ColdFire_V1/port.c b/portable/CodeWarrior/ColdFire_V1/port.c new file mode 100644 index 000000000..520c62ac5 --- /dev/null +++ b/portable/CodeWarrior/ColdFire_V1/port.c @@ -0,0 +1,183 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" + + +#define portINITIAL_FORMAT_VECTOR ( ( StackType_t ) 0x4000 ) + +/* Supervisor mode set. */ +#define portINITIAL_STATUS_REGISTER ( ( StackType_t ) 0x2000) + +/* The clock prescale into the timer peripheral. */ +#define portPRESCALE_VALUE ( ( uint8_t ) 10 ) + +/* The clock frequency into the RTC. */ +#define portRTC_CLOCK_HZ ( ( uint32_t ) 1000 ) + +asm void interrupt VectorNumber_VL1swi vPortYieldISR( void ); +static void prvSetupTimerInterrupt( void ); + +/* Used to keep track of the number of nested calls to taskENTER_CRITICAL(). This +will be set to 0 prior to the first task being started. */ +static uint32_t ulCriticalNesting = 0x9999UL; + +/*-----------------------------------------------------------*/ + +StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + +uint32_t ulOriginalA5; + + __asm{ MOVE.L A5, ulOriginalA5 }; + + + *pxTopOfStack = (StackType_t) 0xDEADBEEF; + pxTopOfStack--; + + /* Exception stack frame starts with the return address. */ + *pxTopOfStack = ( StackType_t ) pxCode; + pxTopOfStack--; + + *pxTopOfStack = ( portINITIAL_FORMAT_VECTOR << 16UL ) | ( portINITIAL_STATUS_REGISTER ); + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0x0; /*FP*/ + pxTopOfStack -= 14; /* A5 to D0. */ + + /* Parameter in A0. */ + *( pxTopOfStack + 8 ) = ( StackType_t ) pvParameters; + + /* A5 must be maintained as it is reserved by the compiler. */ + *( pxTopOfStack + 13 ) = ulOriginalA5; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void vPortStartFirstTask( void ); + + ulCriticalNesting = 0UL; + + /* Configure a timer to generate the tick interrupt. */ + prvSetupTimerInterrupt(); + + /* Start the first task executing. */ + vPortStartFirstTask(); + + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ + /* Prescale by 1 - ie no prescale. */ + RTCSC |= 8; + + /* Compare match value. */ + RTCMOD = portRTC_CLOCK_HZ / configTICK_RATE_HZ; + + /* Enable the RTC to generate interrupts - interrupts are already disabled + when this code executes. */ + RTCSC_RTIE = 1; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented as there is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + if( ulCriticalNesting == 0UL ) + { + /* Guard against context switches being pended simultaneously with a + critical section being entered. */ + do + { + portDISABLE_INTERRUPTS(); + if( INTC_FRC == 0UL ) + { + break; + } + + portENABLE_INTERRUPTS(); + + } while( 1 ); + } + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + ulCriticalNesting--; + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void vPortYieldHandler( void ) +{ +uint32_t ulSavedInterruptMask; + + ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR(); + { + /* Note this will clear all forced interrupts - this is done for speed. */ + INTC_CFRC = 0x3E; + vTaskSwitchContext(); + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask ); +} +/*-----------------------------------------------------------*/ + +void interrupt VectorNumber_Vrtc vPortTickISR( void ) +{ +uint32_t ulSavedInterruptMask; + + /* Clear the interrupt. */ + RTCSC |= RTCSC_RTIF_MASK; + + /* Increment the RTOS tick. */ + ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR(); + { + if( xTaskIncrementTick() != pdFALSE ) + { + taskYIELD(); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask ); +} diff --git a/portable/CodeWarrior/ColdFire_V1/portasm.S b/portable/CodeWarrior/ColdFire_V1/portasm.S new file mode 100644 index 000000000..1f00348af --- /dev/null +++ b/portable/CodeWarrior/ColdFire_V1/portasm.S @@ -0,0 +1,129 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * Purpose: Lowest level routines for all ColdFire processors. + * + * Notes: + * + * ulPortSetIPL() and mcf5xxx_wr_cacr() copied with permission from FreeScale + * supplied source files. + */ + + .global ulPortSetIPL + .global _ulPortSetIPL + .global mcf5xxx_wr_cacrx + .global _mcf5xxx_wr_cacrx + .global vPortYieldISR + .global _vPortYieldISR + .global vPortStartFirstTask + .global _vPortStartFirstTask + .extern _pxCurrentTCB + .extern _vPortYieldHandler + + .text + +.macro portSAVE_CONTEXT + + lea.l (-60, sp), sp + movem.l d0-a6, (sp) + move.l _pxCurrentTCB, a0 + move.l sp, (a0) + + .endm + +.macro portRESTORE_CONTEXT + + move.l _pxCurrentTCB, a0 + move.l (a0), sp + movem.l (sp), d0-a6 + lea.l (60, sp), sp + rte + + .endm + +/********************************************************************/ +/* + * This routines changes the IPL to the value passed into the routine. + * It also returns the old IPL value back. + * Calling convention from C: + * old_ipl = asm_set_ipl(new_ipl); + * For the Diab Data C compiler, it passes return value thru D0. + * Note that only the least significant three bits of the passed + * value are used. + */ + +ulPortSetIPL: +_ulPortSetIPL: + link A6,#-8 + movem.l D6-D7,(SP) + + move.w SR,D7 /* current sr */ + + move.l D7,D6 /* prepare return value */ + andi.l #0x0700,D6 /* mask out IPL */ + lsr.l #8,D6 /* IPL */ + + andi.l #0x07,D0 /* least significant three bits */ + lsl.l #8,D0 /* move over to make mask */ + + andi.l #0x0000F8FF,D7 /* zero out current IPL */ + or.l D0,D7 /* place new IPL in sr */ + move.w D7,SR + + move.l D6, D0 /* Return value in D0. */ + movem.l (SP),D6-D7 + lea 8(SP),SP + unlk A6 + rts +/********************************************************************/ + +mcf5xxx_wr_cacrx: +_mcf5xxx_wr_cacrx: + move.l 4(sp),d0 + .long 0x4e7b0002 /* movec d0,cacr */ + nop + rts + +/********************************************************************/ + +/* Yield interrupt. */ +_vPortYieldISR: +vPortYieldISR: + portSAVE_CONTEXT + jsr _vPortYieldHandler + portRESTORE_CONTEXT + +/********************************************************************/ + + +vPortStartFirstTask: +_vPortStartFirstTask: + portRESTORE_CONTEXT + + .end diff --git a/portable/CodeWarrior/ColdFire_V1/portmacro.h b/portable/CodeWarrior/ColdFire_V1/portmacro.h new file mode 100644 index 000000000..2f224d30b --- /dev/null +++ b/portable/CodeWarrior/ColdFire_V1/portmacro.h @@ -0,0 +1,130 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 4 +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +/*-----------------------------------------------------------*/ + +uint32_t ulPortSetIPL( uint32_t ); +#define portDISABLE_INTERRUPTS() ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#define portENABLE_INTERRUPTS() ulPortSetIPL( 0 ) + + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() + +extern UBaseType_t uxPortSetInterruptMaskFromISR( void ); +extern void vPortClearInterruptMaskFromISR( UBaseType_t ); +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) ulPortSetIPL( uxSavedStatusRegister ) + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +#define portNOP() asm volatile ( "nop" ) + +/* Context switches are requested using the force register. */ +#define portYIELD() INTC_SFRC = 0x3E; portNOP(); portNOP(); portNOP(); portNOP(); portNOP() + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn)) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +/*-----------------------------------------------------------*/ + + +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portYIELD(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/CodeWarrior/ColdFire_V2/port.c b/portable/CodeWarrior/ColdFire_V2/port.c new file mode 100644 index 000000000..64b2d078b --- /dev/null +++ b/portable/CodeWarrior/ColdFire_V2/port.c @@ -0,0 +1,147 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" + + +#define portINITIAL_FORMAT_VECTOR ( ( StackType_t ) 0x4000 ) + +/* Supervisor mode set. */ +#define portINITIAL_STATUS_REGISTER ( ( StackType_t ) 0x2000) + +/* Used to keep track of the number of nested calls to taskENTER_CRITICAL(). This +will be set to 0 prior to the first task being started. */ +static uint32_t ulCriticalNesting = 0x9999UL; + + +#define portSAVE_CONTEXT() \ + lea.l (-60, %sp), %sp; \ + movem.l %d0-%fp, (%sp); \ + move.l pxCurrentTCB, %a0; \ + move.l %sp, (%a0); + +#define portRESTORE_CONTEXT() \ + move.l pxCurrentTCB, %a0; \ + move.l (%a0), %sp; \ + movem.l (%sp), %d0-%fp; \ + lea.l %sp@(60), %sp; \ + rte + + + +/*-----------------------------------------------------------*/ + +StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + *pxTopOfStack = ( StackType_t ) pvParameters; + pxTopOfStack--; + + *pxTopOfStack = (StackType_t) 0xDEADBEEF; + pxTopOfStack--; + + /* Exception stack frame starts with the return address. */ + *pxTopOfStack = ( StackType_t ) pxCode; + pxTopOfStack--; + + *pxTopOfStack = ( portINITIAL_FORMAT_VECTOR << 16UL ) | ( portINITIAL_STATUS_REGISTER ); + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0x0; /*FP*/ + pxTopOfStack -= 14; /* A5 to D0. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void vPortStartFirstTask( void ); + + ulCriticalNesting = 0UL; + + /* Configure the interrupts used by this port. */ + vApplicationSetupInterrupts(); + + /* Start the first task executing. */ + vPortStartFirstTask(); + + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented as there is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + if( ulCriticalNesting == 0UL ) + { + /* Guard against context switches being pended simultaneously with a + critical section being entered. */ + do + { + portDISABLE_INTERRUPTS(); + if( MCF_INTC0_INTFRCH == 0UL ) + { + break; + } + + portENABLE_INTERRUPTS(); + + } while( 1 ); + } + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + ulCriticalNesting--; + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void vPortYieldHandler( void ) +{ +uint32_t ulSavedInterruptMask; + + ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR(); + /* Note this will clear all forced interrupts - this is done for speed. */ + MCF_INTC0_INTFRCL = 0; + vTaskSwitchContext(); + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask ); +} +/*-----------------------------------------------------------*/ diff --git a/portable/CodeWarrior/ColdFire_V2/portasm.S b/portable/CodeWarrior/ColdFire_V2/portasm.S new file mode 100644 index 000000000..66f429259 --- /dev/null +++ b/portable/CodeWarrior/ColdFire_V2/portasm.S @@ -0,0 +1,129 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * Purpose: Lowest level routines for all ColdFire processors. + * + * Notes: + * + * ulPortSetIPL() and mcf5xxx_wr_cacr() copied with permission from FreeScale + * supplied source files. + */ + + .global ulPortSetIPL + .global _ulPortSetIPL + .global mcf5xxx_wr_cacrx + .global _mcf5xxx_wr_cacrx + .global vPortYieldISR + .global _vPortYieldISR + .global vPortStartFirstTask + .global _vPortStartFirstTask + .extern _pxCurrentTCB + .extern _vPortYieldHandler + + .text + +.macro portSAVE_CONTEXT + + lea.l (-60, sp), sp + movem.l d0-a6, (sp) + move.l _pxCurrentTCB, a0 + move.l sp, (a0) + + .endm + +.macro portRESTORE_CONTEXT + + move.l _pxCurrentTCB, a0 + move.l (a0), sp + movem.l (sp), d0-a6 + lea.l (60, sp), sp + rte + + .endm + +/********************************************************************/ +/* + * This routines changes the IPL to the value passed into the routine. + * It also returns the old IPL value back. + * Calling convention from C: + * old_ipl = asm_set_ipl(new_ipl); + * For the Diab Data C compiler, it passes return value thru D0. + * Note that only the least significant three bits of the passed + * value are used. + */ + +ulPortSetIPL: +_ulPortSetIPL: + link A6,#-8 + movem.l D6-D7,(SP) + + move.w SR,D7 /* current sr */ + + move.l D7,D0 /* prepare return value */ + andi.l #0x0700,D0 /* mask out IPL */ + lsr.l #8,D0 /* IPL */ + + move.l 8(A6),D6 /* get argument */ + andi.l #0x07,D6 /* least significant three bits */ + lsl.l #8,D6 /* move over to make mask */ + + andi.l #0x0000F8FF,D7 /* zero out current IPL */ + or.l D6,D7 /* place new IPL in sr */ + move.w D7,SR + + movem.l (SP),D6-D7 + lea 8(SP),SP + unlk A6 + rts +/********************************************************************/ + +mcf5xxx_wr_cacrx: +_mcf5xxx_wr_cacrx: + move.l 4(sp),d0 + .long 0x4e7b0002 /* movec d0,cacr */ + nop + rts + +/********************************************************************/ + +/* Yield interrupt. */ +_vPortYieldISR: +vPortYieldISR: + portSAVE_CONTEXT + jsr _vPortYieldHandler + portRESTORE_CONTEXT + +/********************************************************************/ + + +vPortStartFirstTask: +_vPortStartFirstTask: + portRESTORE_CONTEXT + + .end diff --git a/portable/CodeWarrior/ColdFire_V2/portmacro.h b/portable/CodeWarrior/ColdFire_V2/portmacro.h new file mode 100644 index 000000000..55b38ae3a --- /dev/null +++ b/portable/CodeWarrior/ColdFire_V2/portmacro.h @@ -0,0 +1,128 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 4 +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +/*-----------------------------------------------------------*/ +uint32_t ulPortSetIPL( uint32_t ); +#define portDISABLE_INTERRUPTS() ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#define portENABLE_INTERRUPTS() ulPortSetIPL( 0 ) + + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() + +extern UBaseType_t uxPortSetInterruptMaskFromISR( void ); +extern void vPortClearInterruptMaskFromISR( UBaseType_t ); +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) ulPortSetIPL( uxSavedStatusRegister ) + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +#define portNOP() asm volatile ( "nop" ) + +/* Note this will overwrite all other bits in the force register, it is done this way for speed. */ +#define portYIELD() MCF_INTC0_INTFRCL = ( 1UL << configYIELD_INTERRUPT_VECTOR ); portNOP(); portNOP() /* -32 as we are using the high word of the 64bit mask. */ + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn)) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +/*-----------------------------------------------------------*/ + +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portYIELD(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/CodeWarrior/HCS12/port.c b/portable/CodeWarrior/HCS12/port.c new file mode 100644 index 000000000..2d564cd66 --- /dev/null +++ b/portable/CodeWarrior/HCS12/port.c @@ -0,0 +1,236 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the HCS12 port. + *----------------------------------------------------------*/ + + +/* + * Configure a timer to generate the RTOS tick at the frequency specified + * within FreeRTOSConfig.h. + */ +static void prvSetupTimerInterrupt( void ); + +/* Interrupt service routines have to be in non-banked memory - as does the +scheduler startup function. */ +#pragma CODE_SEG __NEAR_SEG NON_BANKED + + /* Manual context switch function. This is the SWI ISR. */ + void interrupt vPortYield( void ); + + /* Tick context switch function. This is the timer ISR. */ + void interrupt vPortTickInterrupt( void ); + + /* Simply called by xPortStartScheduler(). xPortStartScheduler() does not + start the scheduler directly because the header file containing the + xPortStartScheduler() prototype is part of the common kernel code, and + therefore cannot use the CODE_SEG pragma. */ + static BaseType_t xBankedStartScheduler( void ); + +#pragma CODE_SEG DEFAULT + +/* Calls to portENTER_CRITICAL() can be nested. When they are nested the +critical section should not be left (i.e. interrupts should not be re-enabled) +until the nesting depth reaches 0. This variable simply tracks the nesting +depth. Each task maintains it's own critical nesting depth variable so +uxCriticalNesting is saved and restored from the task stack during a context +switch. */ +volatile UBaseType_t uxCriticalNesting = 0xff; + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* + Place a few bytes of known values on the bottom of the stack. + This can be uncommented to provide useful stack markers when debugging. + + *pxTopOfStack = ( StackType_t ) 0x11; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x22; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x33; + pxTopOfStack--; + */ + + + + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. In this case the stack as + expected by the HCS12 RTI instruction. */ + + + /* The address of the task function is placed in the stack byte at a time. */ + *pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pxCode) ) + 1 ); + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pxCode) ) + 0 ); + pxTopOfStack--; + + /* Next are all the registers that form part of the task context. */ + + /* Y register */ + *pxTopOfStack = ( StackType_t ) 0xff; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xee; + pxTopOfStack--; + + /* X register */ + *pxTopOfStack = ( StackType_t ) 0xdd; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xcc; + pxTopOfStack--; + + /* A register contains parameter high byte. */ + *pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pvParameters) ) + 0 ); + pxTopOfStack--; + + /* B register contains parameter low byte. */ + *pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pvParameters) ) + 1 ); + pxTopOfStack--; + + /* CCR: Note that when the task starts interrupts will be enabled since + "I" bit of CCR is cleared */ + *pxTopOfStack = ( StackType_t ) 0x00; + pxTopOfStack--; + + #ifdef BANKED_MODEL + /* The page of the task. */ + *pxTopOfStack = ( StackType_t ) ( ( int ) pxCode ); + pxTopOfStack--; + #endif + + /* Finally the critical nesting depth is initialised with 0 (not within + a critical section). */ + *pxTopOfStack = ( StackType_t ) 0x00; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the HCS12 port will get stopped. */ +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ + TickTimer_SetFreqHz( configTICK_RATE_HZ ); + TickTimer_Enable(); +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* xPortStartScheduler() does not start the scheduler directly because + the header file containing the xPortStartScheduler() prototype is part + of the common kernel code, and therefore cannot use the CODE_SEG pragma. + Instead it simply calls the locally defined xBankedStartScheduler() - + which does use the CODE_SEG pragma. */ + + return xBankedStartScheduler(); +} +/*-----------------------------------------------------------*/ + +#pragma CODE_SEG __NEAR_SEG NON_BANKED + +static BaseType_t xBankedStartScheduler( void ) +{ + /* Configure the timer that will generate the RTOS tick. Interrupts are + disabled when this function is called. */ + prvSetupTimerInterrupt(); + + /* Restore the context of the first task. */ + portRESTORE_CONTEXT(); + + /* Simulate the end of an interrupt to start the scheduler off. */ + __asm( "rti" ); + + /* Should not get here! */ + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +/* + * Context switch functions. These are both interrupt service routines. + */ + +/* + * Manual context switch forced by calling portYIELD(). This is the SWI + * handler. + */ +void interrupt vPortYield( void ) +{ + portSAVE_CONTEXT(); + vTaskSwitchContext(); + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * RTOS tick interrupt service routine. If the cooperative scheduler is + * being used then this simply increments the tick count. If the + * preemptive scheduler is being used a context switch can occur. + */ +void interrupt vPortTickInterrupt( void ) +{ + #if configUSE_PREEMPTION == 1 + { + /* A context switch might happen so save the context. */ + portSAVE_CONTEXT(); + + /* Increment the tick ... */ + if( xTaskIncrementTick() != pdFALSE ) + { + vTaskSwitchContext(); + } + + TFLG1 = 1; + + /* Restore the context of a task - which may be a different task + to that interrupted. */ + portRESTORE_CONTEXT(); + } + #else + { + xTaskIncrementTick(); + TFLG1 = 1; + } + #endif +} + +#pragma CODE_SEG DEFAULT diff --git a/portable/CodeWarrior/HCS12/portmacro.h b/portable/CodeWarrior/HCS12/portmacro.h new file mode 100644 index 000000000..8e6eb1057 --- /dev/null +++ b/portable/CodeWarrior/HCS12/portmacro.h @@ -0,0 +1,204 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint8_t +#define portBASE_TYPE char + +typedef portSTACK_TYPE StackType_t; +typedef signed char BaseType_t; +typedef unsigned char UBaseType_t; + +#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 1 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portYIELD() __asm( "swi" ); +#define portNOP() __asm( "nop" ); +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +#define portENABLE_INTERRUPTS() __asm( "cli" ) +#define portDISABLE_INTERRUPTS() __asm( "sei" ) + +/* + * Disable interrupts before incrementing the count of critical section nesting. + * The nesting count is maintained so we know when interrupts should be + * re-enabled. Once interrupts are disabled the nesting count can be accessed + * directly. Each task maintains its own nesting count. + */ +#define portENTER_CRITICAL() \ +{ \ + extern volatile UBaseType_t uxCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + uxCriticalNesting++; \ +} + +/* + * Interrupts are disabled so we can access the nesting count directly. If the + * nesting is found to be 0 (no nesting) then we are leaving the critical + * section and interrupts can be re-enabled. + */ +#define portEXIT_CRITICAL() \ +{ \ + extern volatile UBaseType_t uxCriticalNesting; \ + \ + uxCriticalNesting--; \ + if( uxCriticalNesting == 0 ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ +} +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* + * These macros are very simple as the processor automatically saves and + * restores its registers as interrupts are entered and exited. In + * addition to the (automatically stacked) registers we also stack the + * critical nesting count. Each task maintains its own critical nesting + * count as it is legitimate for a task to yield from within a critical + * section. If the banked memory model is being used then the PPAGE + * register is also stored as part of the tasks context. + */ + +#ifdef BANKED_MODEL + /* + * Load the stack pointer for the task, then pull the critical nesting + * count and PPAGE register from the stack. The remains of the + * context are restored by the RTI instruction. + */ + #define portRESTORE_CONTEXT() \ + { \ + extern volatile void * pxCurrentTCB; \ + extern volatile UBaseType_t uxCriticalNesting; \ + \ + __asm( "ldx pxCurrentTCB" ); \ + __asm( "lds 0, x" ); \ + __asm( "pula" ); \ + __asm( "staa uxCriticalNesting" ); \ + __asm( "pula" ); \ + __asm( "staa 0x30" ); /* 0x30 = PPAGE */ \ + } + + /* + * By the time this macro is called the processor has already stacked the + * registers. Simply stack the nesting count and PPAGE value, then save + * the task stack pointer. + */ + #define portSAVE_CONTEXT() \ + { \ + extern volatile void * pxCurrentTCB; \ + extern volatile UBaseType_t uxCriticalNesting; \ + \ + __asm( "ldaa 0x30" ); /* 0x30 = PPAGE */ \ + __asm( "psha" ); \ + __asm( "ldaa uxCriticalNesting" ); \ + __asm( "psha" ); \ + __asm( "ldx pxCurrentTCB" ); \ + __asm( "sts 0, x" ); \ + } +#else + + /* + * These macros are as per the BANKED versions above, but without saving + * and restoring the PPAGE register. + */ + + #define portRESTORE_CONTEXT() \ + { \ + extern volatile void * pxCurrentTCB; \ + extern volatile UBaseType_t uxCriticalNesting; \ + \ + __asm( "ldx pxCurrentTCB" ); \ + __asm( "lds 0, x" ); \ + __asm( "pula" ); \ + __asm( "staa uxCriticalNesting" ); \ + } + + #define portSAVE_CONTEXT() \ + { \ + extern volatile void * pxCurrentTCB; \ + extern volatile UBaseType_t uxCriticalNesting; \ + \ + __asm( "ldaa uxCriticalNesting" ); \ + __asm( "psha" ); \ + __asm( "ldx pxCurrentTCB" ); \ + __asm( "sts 0, x" ); \ + } +#endif + +/* + * Utility macro to call macros above in correct order in order to perform a + * task switch from within a standard ISR. This macro can only be used if + * the ISR does not use any local (stack) variables. If the ISR uses stack + * variables portYIELD() should be used in it's place. + */ +#define portTASK_SWITCH_FROM_ISR() \ + portSAVE_CONTEXT(); \ + vTaskSwitchContext(); \ + portRESTORE_CONTEXT(); + + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#endif /* PORTMACRO_H */ diff --git a/portable/Common/mpu_wrappers.c b/portable/Common/mpu_wrappers.c new file mode 100644 index 000000000..5bc4181e2 --- /dev/null +++ b/portable/Common/mpu_wrappers.c @@ -0,0 +1,2581 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * Implementation of the wrapper functions used to raise the processor privilege + * before calling a standard FreeRTOS API function. + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" +#include "event_groups.h" +#include "stream_buffer.h" +#include "mpu_prototypes.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE +/*-----------------------------------------------------------*/ + +#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + #error Access control list is not available with this MPU wrapper. Please set configENABLE_ACCESS_CONTROL_LIST to 0. + #endif + + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + BaseType_t MPU_xTaskCreate( TaskFunction_t pvTaskCode, + const char * const pcName, + const configSTACK_DEPTH_TYPE uxStackDepth, + void * pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * pxCreatedTask ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + uxPriority = uxPriority & ~( portPRIVILEGE_BIT ); + portMEMORY_BARRIER(); + + xReturn = xTaskCreate( pvTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, pxCreatedTask ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xTaskCreate( pvTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, pxCreatedTask ); + } + + return xReturn; + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, + const char * const pcName, + const configSTACK_DEPTH_TYPE uxStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + StackType_t * const puxStackBuffer, + StaticTask_t * const pxTaskBuffer ) /* FREERTOS_SYSTEM_CALL */ + { + TaskHandle_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + uxPriority = uxPriority & ~( portPRIVILEGE_BIT ); + portMEMORY_BARRIER(); + + xReturn = xTaskCreateStatic( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xTaskCreateStatic( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer ); + } + + return xReturn; + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskDelete == 1 ) + void MPU_vTaskDelete( TaskHandle_t pxTaskToDelete ) /* FREERTOS_SYSTEM_CALL */ + { + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + vTaskDelete( pxTaskToDelete ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + vTaskDelete( pxTaskToDelete ); + } + } + #endif /* if ( INCLUDE_vTaskDelete == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskDelayUntil == 1 ) + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + TickType_t xTimeIncrement ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement ); + } + + return xReturn; + } + #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xTaskAbortDelay( xTask ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xTaskAbortDelay( xTask ); + } + + return xReturn; + } + #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskDelay == 1 ) + void MPU_vTaskDelay( TickType_t xTicksToDelay ) /* FREERTOS_SYSTEM_CALL */ + { + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + vTaskDelay( xTicksToDelay ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + vTaskDelay( xTicksToDelay ); + } + } + #endif /* if ( INCLUDE_vTaskDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskPriorityGet == 1 ) + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t pxTask ) /* FREERTOS_SYSTEM_CALL */ + { + UBaseType_t uxReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + uxReturn = uxTaskPriorityGet( pxTask ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + uxReturn = uxTaskPriorityGet( pxTask ); + } + + return uxReturn; + } + #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskPrioritySet == 1 ) + void MPU_vTaskPrioritySet( TaskHandle_t pxTask, + UBaseType_t uxNewPriority ) /* FREERTOS_SYSTEM_CALL */ + { + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + vTaskPrioritySet( pxTask, uxNewPriority ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + vTaskPrioritySet( pxTask, uxNewPriority ); + } + } + #endif /* if ( INCLUDE_vTaskPrioritySet == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_eTaskGetState == 1 ) + eTaskState MPU_eTaskGetState( TaskHandle_t pxTask ) /* FREERTOS_SYSTEM_CALL */ + { + eTaskState eReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + eReturn = eTaskGetState( pxTask ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + eReturn = eTaskGetState( pxTask ); + } + + return eReturn; + } + #endif /* if ( INCLUDE_eTaskGetState == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) /* FREERTOS_SYSTEM_CALL */ + { + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + vTaskGetInfo( xTask, pxTaskStatus, xGetFreeStackSpace, eState ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + vTaskGetInfo( xTask, pxTaskStatus, xGetFreeStackSpace, eState ); + } + } + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */ + { + TaskHandle_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + xReturn = xTaskGetIdleTaskHandle(); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xTaskGetIdleTaskHandle(); + } + + return xReturn; + } + #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + void MPU_vTaskSuspend( TaskHandle_t pxTaskToSuspend ) /* FREERTOS_SYSTEM_CALL */ + { + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + vTaskSuspend( pxTaskToSuspend ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + vTaskSuspend( pxTaskToSuspend ); + } + } + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + void MPU_vTaskResume( TaskHandle_t pxTaskToResume ) /* FREERTOS_SYSTEM_CALL */ + { + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + vTaskResume( pxTaskToResume ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + vTaskResume( pxTaskToResume ); + } + } + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + void MPU_vTaskSuspendAll( void ) /* FREERTOS_SYSTEM_CALL */ + { + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + vTaskSuspendAll(); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + vTaskSuspendAll(); + } + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xTaskResumeAll( void ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xTaskResumeAll(); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xTaskResumeAll(); + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + TickType_t MPU_xTaskGetTickCount( void ) /* FREERTOS_SYSTEM_CALL */ + { + TickType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xTaskGetTickCount(); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xTaskGetTickCount(); + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* FREERTOS_SYSTEM_CALL */ + { + UBaseType_t uxReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + uxReturn = uxTaskGetNumberOfTasks(); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + uxReturn = uxTaskGetNumberOfTasks(); + } + + return uxReturn; + } +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetHandle == 1 ) + TaskHandle_t MPU_xTaskGetHandle( const char * pcNameToQuery ) /* FREERTOS_SYSTEM_CALL */ + { + TaskHandle_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xTaskGetHandle( pcNameToQuery ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xTaskGetHandle( pcNameToQuery ); + } + + return xReturn; + } + #endif /* if ( INCLUDE_xTaskGetHandle == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + void MPU_vTaskListTasks( char * pcWriteBuffer, + size_t uxBufferLength ) /* FREERTOS_SYSTEM_CALL */ + { + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + vTaskListTasks( pcWriteBuffer, uxBufferLength ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + vTaskListTasks( pcWriteBuffer, uxBufferLength ); + } + } + #endif /* if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + void MPU_vTaskGetRunTimeStatistics( char * pcWriteBuffer, + size_t uxBufferLength ) /* FREERTOS_SYSTEM_CALL */ + { + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + vTaskGetRunTimeStatistics( pcWriteBuffer, uxBufferLength ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + vTaskGetRunTimeStatistics( pcWriteBuffer, uxBufferLength ); + } + } + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* FREERTOS_SYSTEM_CALL */ + { + configRUN_TIME_COUNTER_TYPE xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = ulTaskGetIdleRunTimePercent(); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = ulTaskGetIdleRunTimePercent(); + } + + return xReturn; + } + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* FREERTOS_SYSTEM_CALL */ + { + configRUN_TIME_COUNTER_TYPE xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = ulTaskGetIdleRunTimeCounter(); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = ulTaskGetIdleRunTimeCounter(); + } + + return xReturn; + } + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxTagValue ) /* FREERTOS_SYSTEM_CALL */ + { + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + vTaskSetApplicationTaskTag( xTask, pxTagValue ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + vTaskSetApplicationTaskTag( xTask, pxTagValue ); + } + } + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */ + { + TaskHookFunction_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xTaskGetApplicationTaskTag( xTask ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xTaskGetApplicationTaskTag( xTask ); + } + + return xReturn; + } + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) /* FREERTOS_SYSTEM_CALL */ + { + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + vTaskSetThreadLocalStoragePointer( xTaskToSet, xIndex, pvValue ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + vTaskSetThreadLocalStoragePointer( xTaskToSet, xIndex, pvValue ); + } + } + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) /* FREERTOS_SYSTEM_CALL */ + { + void * pvReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + pvReturn = pvTaskGetThreadLocalStoragePointer( xTaskToQuery, xIndex ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + pvReturn = pvTaskGetThreadLocalStoragePointer( xTaskToQuery, xIndex ); + } + + return pvReturn; + } + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, + void * pvParameter ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xTaskCallApplicationTaskHook( xTask, pvParameter ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xTaskCallApplicationTaskHook( xTask, pvParameter ); + } + + return xReturn; + } + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * pxTaskStatusArray, + UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * pulTotalRunTime ) /* FREERTOS_SYSTEM_CALL */ + { + UBaseType_t uxReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + uxReturn = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, pulTotalRunTime ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + uxReturn = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, pulTotalRunTime ); + } + + return uxReturn; + } + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xTaskCatchUpTicks( xTicksToCatchUp ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xTaskCatchUpTicks( xTicksToCatchUp ); + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */ + { + UBaseType_t uxReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + uxReturn = uxTaskGetStackHighWaterMark( xTask ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + uxReturn = uxTaskGetStackHighWaterMark( xTask ); + } + + return uxReturn; + } + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */ + { + configSTACK_DEPTH_TYPE uxReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + uxReturn = uxTaskGetStackHighWaterMark2( xTask ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + uxReturn = uxTaskGetStackHighWaterMark2( xTask ); + } + + return uxReturn; + } + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_RECURSIVE_MUTEXES == 1 ) ) + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */ + { + TaskHandle_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + xReturn = xTaskGetCurrentTaskHandle(); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xTaskGetCurrentTaskHandle(); + } + + return xReturn; + } + #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_RECURSIVE_MUTEXES == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetSchedulerState == 1 ) + BaseType_t MPU_xTaskGetSchedulerState( void ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xTaskGetSchedulerState(); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xTaskGetSchedulerState(); + } + + return xReturn; + } + #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */ +/*-----------------------------------------------------------*/ + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* FREERTOS_SYSTEM_CALL */ + { + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + vTaskSetTimeOutState( pxTimeOut ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + vTaskSetTimeOutState( pxTimeOut ); + } + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xTaskCheckForTimeOut( pxTimeOut, pxTicksToWait ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xTaskCheckForTimeOut( pxTimeOut, pxTicksToWait ); + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, + UBaseType_t uxIndexToNotify, + uint32_t ulValue, + eNotifyAction eAction, + uint32_t * pulPreviousNotificationValue ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xTaskGenericNotify( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xTaskGenericNotify( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue ); + } + + return xReturn; + } + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn, + uint32_t ulBitsToClearOnEntry, + uint32_t ulBitsToClearOnExit, + uint32_t * pulNotificationValue, + TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xTaskGenericNotifyWait( uxIndexToWaitOn, ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xTaskGenericNotifyWait( uxIndexToWaitOn, ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait ); + } + + return xReturn; + } + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ + { + uint32_t ulReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + ulReturn = ulTaskGenericNotifyTake( uxIndexToWaitOn, xClearCountOnExit, xTicksToWait ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + ulReturn = ulTaskGenericNotifyTake( uxIndexToWaitOn, xClearCountOnExit, xTicksToWait ); + } + + return ulReturn; + } + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xTaskGenericNotifyStateClear( xTask, uxIndexToClear ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xTaskGenericNotifyStateClear( xTask, uxIndexToClear ); + } + + return xReturn; + } + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) /* FREERTOS_SYSTEM_CALL */ + { + uint32_t ulReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + ulReturn = ulTaskGenericNotifyValueClear( xTask, uxIndexToClear, ulBitsToClear ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + ulReturn = ulTaskGenericNotifyValueClear( xTask, uxIndexToClear, ulBitsToClear ); + } + + return ulReturn; + } + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + QueueHandle_t MPU_xQueueGenericCreate( UBaseType_t uxQueueLength, + UBaseType_t uxItemSize, + uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */ + { + QueueHandle_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xQueueGenericCreate( uxQueueLength, uxItemSize, ucQueueType ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xQueueGenericCreate( uxQueueLength, uxItemSize, ucQueueType ); + } + + return xReturn; + } + #endif /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, + const UBaseType_t uxItemSize, + uint8_t * pucQueueStorage, + StaticQueue_t * pxStaticQueue, + const uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */ + { + QueueHandle_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xQueueGenericCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxStaticQueue, ucQueueType ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xQueueGenericCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxStaticQueue, ucQueueType ); + } + + return xReturn; + } + #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueGenericReset( QueueHandle_t pxQueue, + BaseType_t xNewQueue ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xQueueGenericReset( pxQueue, xNewQueue ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xQueueGenericReset( pxQueue, xNewQueue ); + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + BaseType_t xCopyPosition ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xQueueGenericSend( xQueue, pvItemToQueue, xTicksToWait, xCopyPosition ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xQueueGenericSend( xQueue, pvItemToQueue, xTicksToWait, xCopyPosition ); + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t pxQueue ) /* FREERTOS_SYSTEM_CALL */ + { + UBaseType_t uxReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + uxReturn = uxQueueMessagesWaiting( pxQueue ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + uxReturn = uxQueueMessagesWaiting( pxQueue ); + } + + return uxReturn; + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */ + { + UBaseType_t uxReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + uxReturn = uxQueueSpacesAvailable( xQueue ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + uxReturn = uxQueueSpacesAvailable( xQueue ); + } + + return uxReturn; + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueReceive( QueueHandle_t pxQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xQueueReceive( pxQueue, pvBuffer, xTicksToWait ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xQueueReceive( pxQueue, pvBuffer, xTicksToWait ); + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xQueuePeek( xQueue, pvBuffer, xTicksToWait ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xQueuePeek( xQueue, pvBuffer, xTicksToWait ); + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xQueueSemaphoreTake( xQueue, xTicksToWait ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xQueueSemaphoreTake( xQueue, xTicksToWait ); + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* FREERTOS_SYSTEM_CALL */ + { + void * xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xQueueGetMutexHolder( xSemaphore ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xQueueGetMutexHolder( xSemaphore ); + } + + return xReturn; + } + #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */ + { + QueueHandle_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xQueueCreateMutex( ucQueueType ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xQueueCreateMutex( ucQueueType ); + } + + return xReturn; + } + #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, + StaticQueue_t * pxStaticQueue ) /* FREERTOS_SYSTEM_CALL */ + { + QueueHandle_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xQueueCreateMutexStatic( ucQueueType, pxStaticQueue ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xQueueCreateMutexStatic( ucQueueType, pxStaticQueue ); + } + + return xReturn; + } + #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + QueueHandle_t MPU_xQueueCreateCountingSemaphore( UBaseType_t uxCountValue, + UBaseType_t uxInitialCount ) /* FREERTOS_SYSTEM_CALL */ + { + QueueHandle_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xQueueCreateCountingSemaphore( uxCountValue, uxInitialCount ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xQueueCreateCountingSemaphore( uxCountValue, uxInitialCount ); + } + + return xReturn; + } + #endif /* if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + + QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, + const UBaseType_t uxInitialCount, + StaticQueue_t * pxStaticQueue ) /* FREERTOS_SYSTEM_CALL */ + { + QueueHandle_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xQueueCreateCountingSemaphoreStatic( uxMaxCount, uxInitialCount, pxStaticQueue ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xQueueCreateCountingSemaphoreStatic( uxMaxCount, uxInitialCount, pxStaticQueue ); + } + + return xReturn; + } + #endif /* if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xBlockTime ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xQueueTakeMutexRecursive( xMutex, xBlockTime ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xQueueTakeMutexRecursive( xMutex, xBlockTime ); + } + + return xReturn; + } + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t xMutex ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xQueueGiveMutexRecursive( xMutex ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xQueueGiveMutexRecursive( xMutex ); + } + + return xReturn; + } + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + QueueSetHandle_t MPU_xQueueCreateSet( UBaseType_t uxEventQueueLength ) /* FREERTOS_SYSTEM_CALL */ + { + QueueSetHandle_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xQueueCreateSet( uxEventQueueLength ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xQueueCreateSet( uxEventQueueLength ); + } + + return xReturn; + } + #endif /* if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + QueueSetHandle_t MPU_xQueueCreateSetStatic( const UBaseType_t uxEventQueueLength, + uint8_t * pucQueueStorage, + StaticQueue_t * pxStaticQueue ) /* FREERTOS_SYSTEM_CALL */ + { + QueueSetHandle_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xQueueCreateSetStatic( uxEventQueueLength, pucQueueStorage, pxStaticQueue ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xQueueCreateSetStatic( uxEventQueueLength, pucQueueStorage, pxStaticQueue ); + } + + return xReturn; + } + #endif /* if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + TickType_t xBlockTimeTicks ) /* FREERTOS_SYSTEM_CALL */ + { + QueueSetMemberHandle_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xQueueSelectFromSet( xQueueSet, xBlockTimeTicks ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xQueueSelectFromSet( xQueueSet, xBlockTimeTicks ); + } + + return xReturn; + } + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xQueueAddToSet( xQueueOrSemaphore, xQueueSet ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xQueueAddToSet( xQueueOrSemaphore, xQueueSet ); + } + + return xReturn; + } + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xQueueRemoveFromSet( xQueueOrSemaphore, xQueueSet ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xQueueRemoveFromSet( xQueueOrSemaphore, xQueueSet ); + } + + return xReturn; + } + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if configQUEUE_REGISTRY_SIZE > 0 + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) /* FREERTOS_SYSTEM_CALL */ + { + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + vQueueAddToRegistry( xQueue, pcName ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + vQueueAddToRegistry( xQueue, pcName ); + } + } + #endif /* if configQUEUE_REGISTRY_SIZE > 0 */ +/*-----------------------------------------------------------*/ + + #if configQUEUE_REGISTRY_SIZE > 0 + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */ + { + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + vQueueUnregisterQueue( xQueue ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + vQueueUnregisterQueue( xQueue ); + } + } + #endif /* if configQUEUE_REGISTRY_SIZE > 0 */ +/*-----------------------------------------------------------*/ + + #if configQUEUE_REGISTRY_SIZE > 0 + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */ + { + const char * pcReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + pcReturn = pcQueueGetName( xQueue ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + pcReturn = pcQueueGetName( xQueue ); + } + + return pcReturn; + } + #endif /* if configQUEUE_REGISTRY_SIZE > 0 */ +/*-----------------------------------------------------------*/ + + void MPU_vQueueDelete( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */ + { + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + vQueueDelete( xQueue ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + vQueueDelete( xQueue ); + } + } +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */ + { + void * pvReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + pvReturn = pvTimerGetTimerID( xTimer ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + pvReturn = pvTimerGetTimerID( xTimer ); + } + + return pvReturn; + } + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) /* FREERTOS_SYSTEM_CALL */ + { + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + vTimerSetTimerID( xTimer, pvNewID ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + vTimerSetTimerID( xTimer, pvNewID ); + } + } + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xTimerIsTimerActive( xTimer ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xTimerIsTimerActive( xTimer ); + } + + return xReturn; + } + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */ + { + TaskHandle_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xTimerGetTimerDaemonTaskHandle(); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xTimerGetTimerDaemonTaskHandle(); + } + + return xReturn; + } + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) /* FREERTOS_SYSTEM_CALL */ + { + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + vTimerSetReloadMode( xTimer, xAutoReload ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + vTimerSetReloadMode( xTimer, xAutoReload ); + } + } + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) + { + UBaseType_t uxReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + uxReturn = uxTimerGetReloadMode( xTimer ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + uxReturn = uxTimerGetReloadMode( xTimer ); + } + + return uxReturn; + } + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */ + { + const char * pcReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + pcReturn = pcTimerGetName( xTimer ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + pcReturn = pcTimerGetName( xTimer ); + } + + return pcReturn; + } + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */ + { + TickType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xTimerGetPeriod( xTimer ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xTimerGetPeriod( xTimer ); + } + + return xReturn; + } + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */ + { + TickType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xTimerGetExpiryTime( xTimer ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xTimerGetExpiryTime( xTimer ); + } + + return xReturn; + } + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer, + const BaseType_t xCommandID, + const TickType_t xOptionalValue, + BaseType_t * const pxHigherPriorityTaskWoken, + const TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xTimerGenericCommandFromTask( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xTimerGenericCommandFromTask( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait ); + } + + return xReturn; + } + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_EVENT_GROUPS == 1 ) ) + EventGroupHandle_t MPU_xEventGroupCreate( void ) /* FREERTOS_SYSTEM_CALL */ + { + EventGroupHandle_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xEventGroupCreate(); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xEventGroupCreate(); + } + + return xReturn; + } + #endif /* #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_EVENT_GROUPS == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_EVENT_GROUPS == 1 ) ) + EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) /* FREERTOS_SYSTEM_CALL */ + { + EventGroupHandle_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xEventGroupCreateStatic( pxEventGroupBuffer ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xEventGroupCreateStatic( pxEventGroupBuffer ); + } + + return xReturn; + } + #endif /* #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_EVENT_GROUPS == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToWaitFor, + const BaseType_t xClearOnExit, + const BaseType_t xWaitForAllBits, + TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ + { + EventBits_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xEventGroupWaitBits( xEventGroup, uxBitsToWaitFor, xClearOnExit, xWaitForAllBits, xTicksToWait ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xEventGroupWaitBits( xEventGroup, uxBitsToWaitFor, xClearOnExit, xWaitForAllBits, xTicksToWait ); + } + + return xReturn; + } + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) /* FREERTOS_SYSTEM_CALL */ + { + EventBits_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xEventGroupClearBits( xEventGroup, uxBitsToClear ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xEventGroupClearBits( xEventGroup, uxBitsToClear ); + } + + return xReturn; + } + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) /* FREERTOS_SYSTEM_CALL */ + { + EventBits_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xEventGroupSetBits( xEventGroup, uxBitsToSet ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xEventGroupSetBits( xEventGroup, uxBitsToSet ); + } + + return xReturn; + } + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ + { + EventBits_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xEventGroupSync( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTicksToWait ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xEventGroupSync( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTicksToWait ); + } + + return xReturn; + } + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) /* FREERTOS_SYSTEM_CALL */ + { + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + vEventGroupDelete( xEventGroup ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + vEventGroupDelete( xEventGroup ); + } + } + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ + { + size_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xStreamBufferSend( xStreamBuffer, pvTxData, xDataLengthBytes, xTicksToWait ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xStreamBufferSend( xStreamBuffer, pvTxData, xDataLengthBytes, xTicksToWait ); + } + + return xReturn; + } + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */ + { + size_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xStreamBufferNextMessageLengthBytes( xStreamBuffer ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xStreamBufferNextMessageLengthBytes( xStreamBuffer ); + } + + return xReturn; + } + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ + { + size_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xStreamBufferReceive( xStreamBuffer, pvRxData, xBufferLengthBytes, xTicksToWait ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xStreamBufferReceive( xStreamBuffer, pvRxData, xBufferLengthBytes, xTicksToWait ); + } + + return xReturn; + } + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */ + { + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + vStreamBufferDelete( xStreamBuffer ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + vStreamBufferDelete( xStreamBuffer ); + } + } + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xStreamBufferIsFull( xStreamBuffer ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xStreamBufferIsFull( xStreamBuffer ); + } + + return xReturn; + } + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xStreamBufferIsEmpty( xStreamBuffer ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xStreamBufferIsEmpty( xStreamBuffer ); + } + + return xReturn; + } + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xStreamBufferReset( xStreamBuffer ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xStreamBufferReset( xStreamBuffer ); + } + + return xReturn; + } + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */ + { + size_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + xReturn = xStreamBufferSpacesAvailable( xStreamBuffer ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xStreamBufferSpacesAvailable( xStreamBuffer ); + } + + return xReturn; + } + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */ + { + size_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xStreamBufferBytesAvailable( xStreamBuffer ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xStreamBufferBytesAvailable( xStreamBuffer ); + } + + return xReturn; + } + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn; + + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xStreamBufferSetTriggerLevel( xStreamBuffer, xTriggerLevel ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xStreamBufferSetTriggerLevel( xStreamBuffer, xTriggerLevel ); + } + + return xReturn; + } + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_STREAM_BUFFERS == 1 ) ) + StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + BaseType_t xStreamBufferType, + StreamBufferCallbackFunction_t pxSendCompletedCallback, + StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) /* FREERTOS_SYSTEM_CALL */ + { + StreamBufferHandle_t xReturn; + + /** + * Stream buffer application level callback functionality is disabled for MPU + * enabled ports. + */ + configASSERT( ( pxSendCompletedCallback == NULL ) && + ( pxReceiveCompletedCallback == NULL ) ); + + if( ( pxSendCompletedCallback == NULL ) && + ( pxReceiveCompletedCallback == NULL ) ) + { + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xStreamBufferGenericCreate( xBufferSizeBytes, + xTriggerLevelBytes, + xStreamBufferType, + NULL, + NULL ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xStreamBufferGenericCreate( xBufferSizeBytes, + xTriggerLevelBytes, + xStreamBufferType, + NULL, + NULL ); + } + } + else + { + traceSTREAM_BUFFER_CREATE_FAILED( xStreamBufferType ); + xReturn = NULL; + } + + return xReturn; + } + #endif /* #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_STREAM_BUFFERS == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_STREAM_BUFFERS == 1 ) ) + StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + BaseType_t xStreamBufferType, + uint8_t * const pucStreamBufferStorageArea, + StaticStreamBuffer_t * const pxStaticStreamBuffer, + StreamBufferCallbackFunction_t pxSendCompletedCallback, + StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) /* FREERTOS_SYSTEM_CALL */ + { + StreamBufferHandle_t xReturn; + + /** + * Stream buffer application level callback functionality is disabled for MPU + * enabled ports. + */ + configASSERT( ( pxSendCompletedCallback == NULL ) && + ( pxReceiveCompletedCallback == NULL ) ); + + if( ( pxSendCompletedCallback == NULL ) && + ( pxReceiveCompletedCallback == NULL ) ) + { + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + xReturn = xStreamBufferGenericCreateStatic( xBufferSizeBytes, + xTriggerLevelBytes, + xStreamBufferType, + pucStreamBufferStorageArea, + pxStaticStreamBuffer, + NULL, + NULL ); + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + xReturn = xStreamBufferGenericCreateStatic( xBufferSizeBytes, + xTriggerLevelBytes, + xStreamBufferType, + pucStreamBufferStorageArea, + pxStaticStreamBuffer, + NULL, + NULL ); + } + } + else + { + traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xStreamBufferType ); + xReturn = NULL; + } + + return xReturn; + } + #endif /* #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_STREAM_BUFFERS == 1 ) ) */ +/*-----------------------------------------------------------*/ + + +/* Functions that the application writer wants to execute in privileged mode + * can be defined in application_defined_privileged_functions.h. The functions + * must take the same format as those above whereby the privilege state on exit + * equals the privilege state on entry. For example: + * + * void MPU_FunctionName( [parameters ] ) FREERTOS_SYSTEM_CALL; + * void MPU_FunctionName( [parameters ] ) + * { + * if( portIS_PRIVILEGED() == pdFALSE ) + * { + * portRAISE_PRIVILEGE(); + * portMEMORY_BARRIER(); + * + * FunctionName( [parameters ] ); + * portMEMORY_BARRIER(); + * + * portRESET_PRIVILEGE(); + * portMEMORY_BARRIER(); + * } + * else + * { + * FunctionName( [parameters ] ); + * } + * } + */ + + #if configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS == 1 + #include "application_defined_privileged_functions.h" + #endif +/*-----------------------------------------------------------*/ + +#endif /* #if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) */ +/*-----------------------------------------------------------*/ diff --git a/portable/Common/mpu_wrappers_v2.c b/portable/Common/mpu_wrappers_v2.c new file mode 100644 index 000000000..70082b829 --- /dev/null +++ b/portable/Common/mpu_wrappers_v2.c @@ -0,0 +1,5289 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * Implementation of the wrapper functions used to raise the processor privilege + * before calling a standard FreeRTOS API function. + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" +#include "event_groups.h" +#include "stream_buffer.h" +#include "mpu_prototypes.h" +#include "mpu_syscall_numbers.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE +/*-----------------------------------------------------------*/ + +#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #ifndef configPROTECTED_KERNEL_OBJECT_POOL_SIZE + #error configPROTECTED_KERNEL_OBJECT_POOL_SIZE must be defined to maximum number of kernel objects in the application. + #endif + +/** + * @brief Offset added to the index before returning to the user. + * + * If the actual handle is stored at index i, ( i + INDEX_OFFSET ) + * is returned to the user. + */ + #define INDEX_OFFSET 1 + +/** + * @brief Opaque type for a kernel object. + */ + struct OpaqueObject; + typedef struct OpaqueObject * OpaqueObjectHandle_t; + +/** + * @brief Defines kernel object in the kernel object pool. + */ + typedef struct KernelObject + { + OpaqueObjectHandle_t xInternalObjectHandle; + uint32_t ulKernelObjectType; + void * pvKernelObjectData; + } KernelObject_t; + +/** + * @brief Kernel object types. + */ + #define KERNEL_OBJECT_TYPE_INVALID ( 0UL ) + #define KERNEL_OBJECT_TYPE_QUEUE ( 1UL ) + #define KERNEL_OBJECT_TYPE_TASK ( 2UL ) + #define KERNEL_OBJECT_TYPE_STREAM_BUFFER ( 3UL ) + #define KERNEL_OBJECT_TYPE_EVENT_GROUP ( 4UL ) + #define KERNEL_OBJECT_TYPE_TIMER ( 5UL ) + +/** + * @brief Checks whether an external index is valid or not. + */ + #define IS_EXTERNAL_INDEX_VALID( lIndex ) \ + ( ( ( ( lIndex ) >= INDEX_OFFSET ) && \ + ( ( lIndex ) < ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE + INDEX_OFFSET ) ) ) ? pdTRUE : pdFALSE ) + +/** + * @brief Checks whether an internal index is valid or not. + */ + #define IS_INTERNAL_INDEX_VALID( lIndex ) \ + ( ( ( ( lIndex ) >= 0 ) && \ + ( ( lIndex ) < ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE ) ) ) ? pdTRUE : pdFALSE ) + +/** + * @brief Converts an internal index into external. + */ + #define CONVERT_TO_EXTERNAL_INDEX( lIndex ) ( ( lIndex ) + INDEX_OFFSET ) + +/** + * @brief Converts an external index into internal. + */ + #define CONVERT_TO_INTERNAL_INDEX( lIndex ) ( ( lIndex ) - INDEX_OFFSET ) + +/** + * @brief Max value that fits in a uint32_t type. + */ + #define mpuUINT32_MAX ( ~( ( uint32_t ) 0 ) ) + +/** + * @brief Check if multiplying a and b will result in overflow. + */ + #define mpuMULTIPLY_UINT32_WILL_OVERFLOW( a, b ) ( ( ( a ) > 0 ) && ( ( b ) > ( mpuUINT32_MAX / ( a ) ) ) ) + +/** + * @brief Get the index of a free slot in the kernel object pool. + * + * If a free slot is found, this function marks the slot as + * "not free". + * + * @return Index of a free slot is returned, if a free slot is + * found. Otherwise -1 is returned. + */ + static int32_t MPU_GetFreeIndexInKernelObjectPool( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Set the given index as free in the kernel object pool. + * + * @param lIndex The index to set as free. + */ + static void MPU_SetIndexFreeInKernelObjectPool( int32_t lIndex ) PRIVILEGED_FUNCTION; + +/** + * @brief Get the index at which a given kernel object is stored. + * + * @param xHandle The given kernel object handle. + * @param ulKernelObjectType The kernel object type. + * + * @return Index at which the kernel object is stored if it is a valid + * handle, -1 otherwise. + */ + static int32_t MPU_GetIndexForHandle( OpaqueObjectHandle_t xHandle, + uint32_t ulKernelObjectType ) PRIVILEGED_FUNCTION; + +/** + * @brief Store the given kernel object handle at the given index in + * the kernel object pool. + * + * @param lIndex Index to store the given handle at. + * @param xHandle Kernel object handle to store. + * @param pvKernelObjectData The data associated with the kernel object. + * Currently, only used for timer objects to store timer callback. + * @param ulKernelObjectType The kernel object type. + */ + static void MPU_StoreHandleAndDataAtIndex( int32_t lIndex, + OpaqueObjectHandle_t xHandle, + void * pvKernelObjectData, + uint32_t ulKernelObjectType ) PRIVILEGED_FUNCTION; + +/** + * @brief Get the kernel object handle at the given index from + * the kernel object pool. + * + * @param lIndex Index at which to get the kernel object handle. + * @param ulKernelObjectType The kernel object type. + * + * @return The kernel object handle at the index. + */ + static OpaqueObjectHandle_t MPU_GetHandleAtIndex( int32_t lIndex, + uint32_t ulKernelObjectType ) PRIVILEGED_FUNCTION; + + #if ( configUSE_TIMERS == 1 ) + +/** + * @brief The function registered as callback for all the timers. + * + * We intercept all the timer callbacks so that we can call application + * callbacks with opaque handle. + * + * @param xInternalHandle The internal timer handle. + */ + static void MPU_TimerCallback( TimerHandle_t xInternalHandle ) PRIVILEGED_FUNCTION; + + #endif /* #if ( configUSE_TIMERS == 1 ) */ + +/* + * Wrappers to keep all the casting in one place. + */ + #define MPU_StoreQueueHandleAtIndex( lIndex, xHandle ) MPU_StoreHandleAndDataAtIndex( ( lIndex ), ( OpaqueObjectHandle_t ) ( xHandle ), NULL, KERNEL_OBJECT_TYPE_QUEUE ) + #define MPU_GetQueueHandleAtIndex( lIndex ) ( QueueHandle_t ) MPU_GetHandleAtIndex( ( lIndex ), KERNEL_OBJECT_TYPE_QUEUE ) + + #if ( configUSE_QUEUE_SETS == 1 ) + #define MPU_StoreQueueSetHandleAtIndex( lIndex, xHandle ) MPU_StoreHandleAndDataAtIndex( ( lIndex ), ( OpaqueObjectHandle_t ) ( xHandle ), NULL, KERNEL_OBJECT_TYPE_QUEUE ) + #define MPU_GetQueueSetHandleAtIndex( lIndex ) ( QueueSetHandle_t ) MPU_GetHandleAtIndex( ( lIndex ), KERNEL_OBJECT_TYPE_QUEUE ) + #define MPU_StoreQueueSetMemberHandleAtIndex( lIndex, xHandle ) MPU_StoreHandleAndDataAtIndex( ( lIndex ), ( OpaqueObjectHandle_t ) ( xHandle ), NULL, KERNEL_OBJECT_TYPE_QUEUE ) + #define MPU_GetQueueSetMemberHandleAtIndex( lIndex ) ( QueueSetMemberHandle_t ) MPU_GetHandleAtIndex( ( lIndex ), KERNEL_OBJECT_TYPE_QUEUE ) + #define MPU_GetIndexForQueueSetMemberHandle( xHandle ) MPU_GetIndexForHandle( ( OpaqueObjectHandle_t ) ( xHandle ), KERNEL_OBJECT_TYPE_QUEUE ) + #endif + +/* + * Wrappers to keep all the casting in one place for Task APIs. + */ + #define MPU_StoreTaskHandleAtIndex( lIndex, xHandle ) MPU_StoreHandleAndDataAtIndex( ( lIndex ), ( OpaqueObjectHandle_t ) ( xHandle ), NULL, KERNEL_OBJECT_TYPE_TASK ) + #define MPU_GetTaskHandleAtIndex( lIndex ) ( TaskHandle_t ) MPU_GetHandleAtIndex( ( lIndex ), KERNEL_OBJECT_TYPE_TASK ) + #define MPU_GetIndexForTaskHandle( xHandle ) MPU_GetIndexForHandle( ( OpaqueObjectHandle_t ) ( xHandle ), KERNEL_OBJECT_TYPE_TASK ) + + #if ( configUSE_EVENT_GROUPS == 1 ) +/* + * Wrappers to keep all the casting in one place for Event Group APIs. + */ + #define MPU_StoreEventGroupHandleAtIndex( lIndex, xHandle ) MPU_StoreHandleAndDataAtIndex( ( lIndex ), ( OpaqueObjectHandle_t ) ( xHandle ), NULL, KERNEL_OBJECT_TYPE_EVENT_GROUP ) + #define MPU_GetEventGroupHandleAtIndex( lIndex ) ( EventGroupHandle_t ) MPU_GetHandleAtIndex( ( lIndex ), KERNEL_OBJECT_TYPE_EVENT_GROUP ) + #define MPU_GetIndexForEventGroupHandle( xHandle ) MPU_GetIndexForHandle( ( OpaqueObjectHandle_t ) ( xHandle ), KERNEL_OBJECT_TYPE_EVENT_GROUP ) + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ + + #if ( configUSE_STREAM_BUFFERS == 1 ) +/* + * Wrappers to keep all the casting in one place for Stream Buffer APIs. + */ + #define MPU_StoreStreamBufferHandleAtIndex( lIndex, xHandle ) MPU_StoreHandleAndDataAtIndex( ( lIndex ), ( OpaqueObjectHandle_t ) ( xHandle), NULL, KERNEL_OBJECT_TYPE_STREAM_BUFFER ) + #define MPU_GetStreamBufferHandleAtIndex( lIndex ) ( StreamBufferHandle_t ) MPU_GetHandleAtIndex( ( lIndex ), KERNEL_OBJECT_TYPE_STREAM_BUFFER ) + #define MPU_GetIndexForStreamBufferHandle( xHandle ) MPU_GetIndexForHandle( ( OpaqueObjectHandle_t ) ( xHandle ), KERNEL_OBJECT_TYPE_STREAM_BUFFER ) + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ + + #if ( configUSE_TIMERS == 1 ) +/* + * Wrappers to keep all the casting in one place for Timer APIs. + */ + #define MPU_StoreTimerHandleAtIndex( lIndex, xHandle, pxApplicationCallback ) MPU_StoreHandleAndDataAtIndex( ( lIndex ), ( OpaqueObjectHandle_t ) ( xHandle ), ( void * ) ( pxApplicationCallback ), KERNEL_OBJECT_TYPE_TIMER ) + #define MPU_GetTimerHandleAtIndex( lIndex ) ( TimerHandle_t ) MPU_GetHandleAtIndex( ( lIndex ), KERNEL_OBJECT_TYPE_TIMER ) + #define MPU_GetIndexForTimerHandle( xHandle ) MPU_GetIndexForHandle( ( OpaqueObjectHandle_t ) ( xHandle ), KERNEL_OBJECT_TYPE_TIMER ) + + #endif /* #if ( configUSE_TIMERS == 1 ) */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Kernel object pool. + */ + PRIVILEGED_DATA static KernelObject_t xKernelObjectPool[ configPROTECTED_KERNEL_OBJECT_POOL_SIZE ] = { 0 }; +/*-----------------------------------------------------------*/ + + static int32_t MPU_GetFreeIndexInKernelObjectPool( void ) /* PRIVILEGED_FUNCTION */ + { + int32_t i, lFreeIndex = -1; + + /* This function is called only from resource create APIs + * which are not supposed to be called from ISRs. Therefore, + * we only need to suspend the scheduler and do not require + * critical section. */ + vTaskSuspendAll(); + { + for( i = 0; i < configPROTECTED_KERNEL_OBJECT_POOL_SIZE; i++ ) + { + if( xKernelObjectPool[ i ].xInternalObjectHandle == NULL ) + { + /* Mark this index as not free. */ + xKernelObjectPool[ i ].xInternalObjectHandle = ( OpaqueObjectHandle_t ) ( ~0U ); + lFreeIndex = i; + break; + } + } + } + ( void ) xTaskResumeAll(); + + return lFreeIndex; + } +/*-----------------------------------------------------------*/ + + static void MPU_SetIndexFreeInKernelObjectPool( int32_t lIndex ) /* PRIVILEGED_FUNCTION */ + { + configASSERT( IS_INTERNAL_INDEX_VALID( lIndex ) != pdFALSE ); + + taskENTER_CRITICAL(); + { + xKernelObjectPool[ lIndex ].xInternalObjectHandle = NULL; + xKernelObjectPool[ lIndex ].ulKernelObjectType = KERNEL_OBJECT_TYPE_INVALID; + xKernelObjectPool[ lIndex ].pvKernelObjectData = NULL; + } + taskEXIT_CRITICAL(); + } +/*-----------------------------------------------------------*/ + + static int32_t MPU_GetIndexForHandle( OpaqueObjectHandle_t xHandle, + uint32_t ulKernelObjectType ) /* PRIVILEGED_FUNCTION */ + { + int32_t i, lIndex = -1; + + configASSERT( xHandle != NULL ); + + for( i = 0; i < configPROTECTED_KERNEL_OBJECT_POOL_SIZE; i++ ) + { + if( ( xKernelObjectPool[ i ].xInternalObjectHandle == xHandle ) && + ( xKernelObjectPool[ i ].ulKernelObjectType == ulKernelObjectType ) ) + { + lIndex = i; + break; + } + } + + return lIndex; + } +/*-----------------------------------------------------------*/ + + static void MPU_StoreHandleAndDataAtIndex( int32_t lIndex, + OpaqueObjectHandle_t xHandle, + void * pvKernelObjectData, + uint32_t ulKernelObjectType ) /* PRIVILEGED_FUNCTION */ + { + configASSERT( IS_INTERNAL_INDEX_VALID( lIndex ) != pdFALSE ); + xKernelObjectPool[ lIndex ].xInternalObjectHandle = xHandle; + xKernelObjectPool[ lIndex ].ulKernelObjectType = ulKernelObjectType; + xKernelObjectPool[ lIndex ].pvKernelObjectData = pvKernelObjectData; + } +/*-----------------------------------------------------------*/ + + static OpaqueObjectHandle_t MPU_GetHandleAtIndex( int32_t lIndex, + uint32_t ulKernelObjectType ) /* PRIVILEGED_FUNCTION */ + { + OpaqueObjectHandle_t xObjectHandle = NULL; + + configASSERT( IS_INTERNAL_INDEX_VALID( lIndex ) != pdFALSE ); + + if( xKernelObjectPool[ lIndex ].ulKernelObjectType == ulKernelObjectType ) + { + xObjectHandle = xKernelObjectPool[ lIndex ].xInternalObjectHandle; + } + + return xObjectHandle; + } +/*-----------------------------------------------------------*/ + + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + + void vGrantAccessToKernelObject( TaskHandle_t xExternalTaskHandle, + int32_t lExternalKernelObjectHandle ) /* PRIVILEGED_FUNCTION */ + { + int32_t lExternalTaskIndex; + TaskHandle_t xInternalTaskHandle = NULL; + + if( IS_EXTERNAL_INDEX_VALID( lExternalKernelObjectHandle ) != pdFALSE ) + { + if( xExternalTaskHandle == NULL ) + { + vPortGrantAccessToKernelObject( xExternalTaskHandle, CONVERT_TO_INTERNAL_INDEX( lExternalKernelObjectHandle ) ); + } + else + { + lExternalTaskIndex = ( int32_t ) xExternalTaskHandle; + + if( IS_EXTERNAL_INDEX_VALID( lExternalTaskIndex ) != pdFALSE ) + { + xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lExternalTaskIndex ) ); + + if( xInternalTaskHandle != NULL ) + { + vPortGrantAccessToKernelObject( xInternalTaskHandle, + CONVERT_TO_INTERNAL_INDEX( lExternalKernelObjectHandle ) ); + } + } + } + } + } + + #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + + void vRevokeAccessToKernelObject( TaskHandle_t xExternalTaskHandle, + int32_t lExternalKernelObjectHandle ) /* PRIVILEGED_FUNCTION */ + { + int32_t lExternalTaskIndex; + TaskHandle_t xInternalTaskHandle = NULL; + + if( IS_EXTERNAL_INDEX_VALID( lExternalKernelObjectHandle ) != pdFALSE ) + { + if( xExternalTaskHandle == NULL ) + { + vPortRevokeAccessToKernelObject( xExternalTaskHandle, CONVERT_TO_INTERNAL_INDEX( lExternalKernelObjectHandle ) ); + } + else + { + lExternalTaskIndex = ( int32_t ) xExternalTaskHandle; + + if( IS_EXTERNAL_INDEX_VALID( lExternalTaskIndex ) != pdFALSE ) + { + xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lExternalTaskIndex ) ); + + if( xInternalTaskHandle != NULL ) + { + vPortRevokeAccessToKernelObject( xInternalTaskHandle, + CONVERT_TO_INTERNAL_INDEX( lExternalKernelObjectHandle ) ); + } + } + } + } + } + + #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + static void MPU_TimerCallback( TimerHandle_t xInternalHandle ) /* PRIVILEGED_FUNCTION */ + { + int32_t i, lIndex = -1; + TimerHandle_t xExternalHandle = NULL; + TimerCallbackFunction_t pxApplicationCallBack = NULL; + + /* Coming from the timer task and therefore, should be valid. */ + configASSERT( xInternalHandle != NULL ); + + for( i = 0; i < configPROTECTED_KERNEL_OBJECT_POOL_SIZE; i++ ) + { + if( ( ( TimerHandle_t ) xKernelObjectPool[ i ].xInternalObjectHandle == xInternalHandle ) && + ( xKernelObjectPool[ i ].ulKernelObjectType == KERNEL_OBJECT_TYPE_TIMER ) ) + { + lIndex = i; + break; + } + } + + configASSERT( lIndex != -1 ); + xExternalHandle = ( TimerHandle_t ) CONVERT_TO_EXTERNAL_INDEX( lIndex ); + + pxApplicationCallBack = ( TimerCallbackFunction_t ) xKernelObjectPool[ lIndex ].pvKernelObjectData; + pxApplicationCallBack( xExternalHandle ); + } + + #endif /* #if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + +/*-----------------------------------------------------------*/ +/* MPU wrappers for tasks APIs. */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskDelayUntil == 1 ) + + BaseType_t MPU_xTaskDelayUntilImpl( TickType_t * const pxPreviousWakeTime, + TickType_t xTimeIncrement ) PRIVILEGED_FUNCTION; + + BaseType_t MPU_xTaskDelayUntilImpl( TickType_t * const pxPreviousWakeTime, + TickType_t xTimeIncrement ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xReturn = pdFAIL; + BaseType_t xIsPreviousWakeTimeAccessible = pdFALSE; + + if( ( pxPreviousWakeTime != NULL ) && ( xTimeIncrement > 0U ) ) + { + xIsPreviousWakeTimeAccessible = xPortIsAuthorizedToAccessBuffer( pxPreviousWakeTime, + sizeof( TickType_t ), + ( tskMPU_WRITE_PERMISSION | tskMPU_READ_PERMISSION ) ); + + if( xIsPreviousWakeTimeAccessible == pdTRUE ) + { + xReturn = xTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement ); + } + } + + return xReturn; + } + + #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + + BaseType_t MPU_xTaskAbortDelayImpl( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + + BaseType_t MPU_xTaskAbortDelayImpl( TaskHandle_t xTask ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xReturn = pdFAIL; + BaseType_t xCallingTaskIsAuthorizedToAccessTask = pdFALSE; + TaskHandle_t xInternalTaskHandle = NULL; + int32_t lIndex; + + lIndex = ( int32_t ) xTask; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessTask = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessTask == pdTRUE ) + { + xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTaskHandle != NULL ) + { + xReturn = xTaskAbortDelay( xInternalTaskHandle ); + } + } + } + + return xReturn; + } + + #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskDelay == 1 ) + + void MPU_vTaskDelayImpl( TickType_t xTicksToDelay ) PRIVILEGED_FUNCTION; + + void MPU_vTaskDelayImpl( TickType_t xTicksToDelay ) /* PRIVILEGED_FUNCTION */ + { + vTaskDelay( xTicksToDelay ); + } + + #endif /* if ( INCLUDE_vTaskDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskPriorityGet == 1 ) + + UBaseType_t MPU_uxTaskPriorityGetImpl( const TaskHandle_t pxTask ) PRIVILEGED_FUNCTION; + + UBaseType_t MPU_uxTaskPriorityGetImpl( const TaskHandle_t pxTask ) /* PRIVILEGED_FUNCTION */ + { + UBaseType_t uxReturn = configMAX_PRIORITIES; + BaseType_t xCallingTaskIsAuthorizedToAccessTask = pdFALSE; + int32_t lIndex; + TaskHandle_t xInternalTaskHandle = NULL; + + if( pxTask == NULL ) + { + uxReturn = uxTaskPriorityGet( pxTask ); + } + else + { + lIndex = ( int32_t ) pxTask; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessTask = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessTask == pdTRUE ) + { + xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTaskHandle != NULL ) + { + uxReturn = uxTaskPriorityGet( xInternalTaskHandle ); + } + } + } + } + + return uxReturn; + } + + #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_eTaskGetState == 1 ) + + eTaskState MPU_eTaskGetStateImpl( TaskHandle_t pxTask ) PRIVILEGED_FUNCTION; + + eTaskState MPU_eTaskGetStateImpl( TaskHandle_t pxTask ) /* PRIVILEGED_FUNCTION */ + { + eTaskState eReturn = eInvalid; + TaskHandle_t xInternalTaskHandle = NULL; + int32_t lIndex; + BaseType_t xCallingTaskIsAuthorizedToAccessTask = pdFALSE; + + lIndex = ( int32_t ) pxTask; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessTask = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessTask == pdTRUE ) + { + xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTaskHandle != NULL ) + { + eReturn = eTaskGetState( xInternalTaskHandle ); + } + } + } + + return eReturn; + } + + #endif /* if ( INCLUDE_eTaskGetState == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + void MPU_vTaskGetInfoImpl( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) PRIVILEGED_FUNCTION; + + void MPU_vTaskGetInfoImpl( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) /* PRIVILEGED_FUNCTION */ + { + int32_t lIndex; + TaskHandle_t xInternalTaskHandle = NULL; + BaseType_t xIsTaskStatusWriteable = pdFALSE; + BaseType_t xCallingTaskIsAuthorizedToAccessTask = pdFALSE; + + xIsTaskStatusWriteable = xPortIsAuthorizedToAccessBuffer( pxTaskStatus, + sizeof( TaskStatus_t ), + tskMPU_WRITE_PERMISSION ); + + if( xIsTaskStatusWriteable == pdTRUE ) + { + if( xTask == NULL ) + { + vTaskGetInfo( xTask, pxTaskStatus, xGetFreeStackSpace, eState ); + } + else + { + lIndex = ( int32_t ) xTask; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessTask = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessTask == pdTRUE ) + { + xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTaskHandle != NULL ) + { + vTaskGetInfo( xInternalTaskHandle, pxTaskStatus, xGetFreeStackSpace, eState ); + } + } + } + } + } + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) + + TaskHandle_t MPU_xTaskGetIdleTaskHandleImpl( void ) PRIVILEGED_FUNCTION; + + TaskHandle_t MPU_xTaskGetIdleTaskHandleImpl( void ) /* PRIVILEGED_FUNCTION */ + { + TaskHandle_t xIdleTaskHandle = NULL; + + xIdleTaskHandle = xTaskGetIdleTaskHandle(); + + return xIdleTaskHandle; + } + + #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + + void MPU_vTaskSuspendImpl( TaskHandle_t pxTaskToSuspend ) PRIVILEGED_FUNCTION; + + void MPU_vTaskSuspendImpl( TaskHandle_t pxTaskToSuspend ) /* PRIVILEGED_FUNCTION */ + { + int32_t lIndex; + TaskHandle_t xInternalTaskHandle = NULL; + BaseType_t xCallingTaskIsAuthorizedToAccessTask = pdFALSE; + + if( pxTaskToSuspend == NULL ) + { + vTaskSuspend( pxTaskToSuspend ); + } + else + { + /* After the scheduler starts, only privileged tasks are allowed + * to suspend other tasks. */ + #if ( INCLUDE_xTaskGetSchedulerState == 1 ) + if( ( xTaskGetSchedulerState() == taskSCHEDULER_NOT_STARTED ) || ( portIS_TASK_PRIVILEGED() == pdTRUE ) ) + #else + if( portIS_TASK_PRIVILEGED() == pdTRUE ) + #endif + { + lIndex = ( int32_t ) pxTaskToSuspend; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessTask = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessTask == pdTRUE ) + { + xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTaskHandle != NULL ) + { + vTaskSuspend( xInternalTaskHandle ); + } + } + } + } + } + } + + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + + void MPU_vTaskResumeImpl( TaskHandle_t pxTaskToResume ) PRIVILEGED_FUNCTION; + + void MPU_vTaskResumeImpl( TaskHandle_t pxTaskToResume ) /* PRIVILEGED_FUNCTION */ + { + int32_t lIndex; + TaskHandle_t xInternalTaskHandle = NULL; + BaseType_t xCallingTaskIsAuthorizedToAccessTask = pdFALSE; + + lIndex = ( int32_t ) pxTaskToResume; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessTask = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessTask == pdTRUE ) + { + xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTaskHandle != NULL ) + { + vTaskResume( xInternalTaskHandle ); + } + } + } + } + + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + TickType_t MPU_xTaskGetTickCountImpl( void ) PRIVILEGED_FUNCTION; + + TickType_t MPU_xTaskGetTickCountImpl( void ) /* PRIVILEGED_FUNCTION */ + { + TickType_t xReturn; + + xReturn = xTaskGetTickCount(); + + return xReturn; + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxTaskGetNumberOfTasksImpl( void ) PRIVILEGED_FUNCTION; + + UBaseType_t MPU_uxTaskGetNumberOfTasksImpl( void ) /* PRIVILEGED_FUNCTION */ + { + UBaseType_t uxReturn; + + uxReturn = uxTaskGetNumberOfTasks(); + + return uxReturn; + } +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounterImpl( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounterImpl( const TaskHandle_t xTask ) /* PRIVILEGED_FUNCTION */ + { + configRUN_TIME_COUNTER_TYPE xReturn = 0; + int32_t lIndex; + TaskHandle_t xInternalTaskHandle = NULL; + BaseType_t xCallingTaskIsAuthorizedToAccessTask = pdFALSE; + + if( xTask == NULL ) + { + xReturn = ulTaskGetRunTimeCounter( xTask ); + } + else + { + lIndex = ( int32_t ) xTask; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessTask = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessTask == pdTRUE ) + { + xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTaskHandle != NULL ) + { + xReturn = ulTaskGetRunTimeCounter( xInternalTaskHandle ); + } + } + } + } + + return xReturn; + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercentImpl( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercentImpl( const TaskHandle_t xTask ) /* PRIVILEGED_FUNCTION */ + { + configRUN_TIME_COUNTER_TYPE xReturn = 0; + int32_t lIndex; + TaskHandle_t xInternalTaskHandle = NULL; + BaseType_t xCallingTaskIsAuthorizedToAccessTask = pdFALSE; + + if( xTask == NULL ) + { + xReturn = ulTaskGetRunTimePercent( xTask ); + } + else + { + lIndex = ( int32_t ) xTask; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessTask = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessTask == pdTRUE ) + { + xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTaskHandle != NULL ) + { + xReturn = ulTaskGetRunTimePercent( xInternalTaskHandle ); + } + } + } + } + + return xReturn; + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercentImpl( void ) PRIVILEGED_FUNCTION; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercentImpl( void ) /* PRIVILEGED_FUNCTION */ + { + configRUN_TIME_COUNTER_TYPE xReturn; + + xReturn = ulTaskGetIdleRunTimePercent(); + + return xReturn; + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounterImpl( void ) PRIVILEGED_FUNCTION; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounterImpl( void ) /* PRIVILEGED_FUNCTION */ + { + configRUN_TIME_COUNTER_TYPE xReturn; + + xReturn = ulTaskGetIdleRunTimeCounter(); + + return xReturn; + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + void MPU_vTaskSetApplicationTaskTagImpl( TaskHandle_t xTask, + TaskHookFunction_t pxTagValue ) PRIVILEGED_FUNCTION; + + void MPU_vTaskSetApplicationTaskTagImpl( TaskHandle_t xTask, + TaskHookFunction_t pxTagValue ) /* PRIVILEGED_FUNCTION */ + { + TaskHandle_t xInternalTaskHandle = NULL; + int32_t lIndex; + BaseType_t xCallingTaskIsAuthorizedToAccessTask = pdFALSE; + + if( xTask == NULL ) + { + vTaskSetApplicationTaskTag( xTask, pxTagValue ); + } + else + { + lIndex = ( int32_t ) xTask; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessTask = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessTask == pdTRUE ) + { + xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTaskHandle != NULL ) + { + vTaskSetApplicationTaskTag( xInternalTaskHandle, pxTagValue ); + } + } + } + } + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTagImpl( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTagImpl( TaskHandle_t xTask ) /* PRIVILEGED_FUNCTION */ + { + TaskHookFunction_t xReturn = NULL; + int32_t lIndex; + TaskHandle_t xInternalTaskHandle = NULL; + BaseType_t xCallingTaskIsAuthorizedToAccessTask = pdFALSE; + + if( xTask == NULL ) + { + xReturn = xTaskGetApplicationTaskTag( xTask ); + } + else + { + lIndex = ( int32_t ) xTask; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessTask = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessTask == pdTRUE ) + { + xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTaskHandle != NULL ) + { + xReturn = xTaskGetApplicationTaskTag( xInternalTaskHandle ); + } + } + } + } + + return xReturn; + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void MPU_vTaskSetThreadLocalStoragePointerImpl( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) PRIVILEGED_FUNCTION; + + void MPU_vTaskSetThreadLocalStoragePointerImpl( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) /* PRIVILEGED_FUNCTION */ + { + int32_t lIndex; + TaskHandle_t xInternalTaskHandle = NULL; + BaseType_t xCallingTaskIsAuthorizedToAccessTask = pdFALSE; + + if( xTaskToSet == NULL ) + { + vTaskSetThreadLocalStoragePointer( xTaskToSet, xIndex, pvValue ); + } + else + { + lIndex = ( int32_t ) xTaskToSet; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessTask = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessTask == pdTRUE ) + { + xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTaskHandle != NULL ) + { + vTaskSetThreadLocalStoragePointer( xInternalTaskHandle, xIndex, pvValue ); + } + } + } + } + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void * MPU_pvTaskGetThreadLocalStoragePointerImpl( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) PRIVILEGED_FUNCTION; + + void * MPU_pvTaskGetThreadLocalStoragePointerImpl( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) /* PRIVILEGED_FUNCTION */ + { + void * pvReturn = NULL; + int32_t lIndex; + TaskHandle_t xInternalTaskHandle = NULL; + BaseType_t xCallingTaskIsAuthorizedToAccessTask = pdFALSE; + + if( xTaskToQuery == NULL ) + { + pvReturn = pvTaskGetThreadLocalStoragePointer( xTaskToQuery, xIndex ); + } + else + { + lIndex = ( int32_t ) xTaskToQuery; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessTask = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessTask == pdTRUE ) + { + xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTaskHandle != NULL ) + { + pvReturn = pvTaskGetThreadLocalStoragePointer( xInternalTaskHandle, xIndex ); + } + } + } + } + + return pvReturn; + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t MPU_uxTaskGetSystemStateImpl( TaskStatus_t * pxTaskStatusArray, + UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * pulTotalRunTime ) PRIVILEGED_FUNCTION; + + UBaseType_t MPU_uxTaskGetSystemStateImpl( TaskStatus_t * pxTaskStatusArray, + UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * pulTotalRunTime ) /* PRIVILEGED_FUNCTION */ + { + UBaseType_t uxReturn = 0; + BaseType_t xIsTaskStatusArrayWriteable = pdFALSE; + BaseType_t xIsTotalRunTimeWriteable = pdFALSE; + uint32_t ulArraySize = ( uint32_t ) uxArraySize; + uint32_t ulTaskStatusSize = ( uint32_t ) sizeof( TaskStatus_t ); + + if( mpuMULTIPLY_UINT32_WILL_OVERFLOW( ulTaskStatusSize, ulArraySize ) == 0 ) + { + xIsTaskStatusArrayWriteable = xPortIsAuthorizedToAccessBuffer( pxTaskStatusArray, + ulTaskStatusSize * ulArraySize, + tskMPU_WRITE_PERMISSION ); + + if( pulTotalRunTime != NULL ) + { + xIsTotalRunTimeWriteable = xPortIsAuthorizedToAccessBuffer( pulTotalRunTime, + sizeof( configRUN_TIME_COUNTER_TYPE ), + tskMPU_WRITE_PERMISSION ); + } + + if( ( xIsTaskStatusArrayWriteable == pdTRUE ) && + ( ( pulTotalRunTime == NULL ) || ( xIsTotalRunTimeWriteable == pdTRUE ) ) ) + { + uxReturn = uxTaskGetSystemState( pxTaskStatusArray, ( UBaseType_t ) ulArraySize, pulTotalRunTime ); + } + } + + return uxReturn; + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) + + UBaseType_t MPU_uxTaskGetStackHighWaterMarkImpl( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + + UBaseType_t MPU_uxTaskGetStackHighWaterMarkImpl( TaskHandle_t xTask ) /* PRIVILEGED_FUNCTION */ + { + UBaseType_t uxReturn = 0; + int32_t lIndex; + TaskHandle_t xInternalTaskHandle = NULL; + BaseType_t xCallingTaskIsAuthorizedToAccessTask = pdFALSE; + + if( xTask == NULL ) + { + uxReturn = uxTaskGetStackHighWaterMark( xTask ); + } + else + { + lIndex = ( int32_t ) xTask; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessTask = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessTask == pdTRUE ) + { + xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTaskHandle != NULL ) + { + uxReturn = uxTaskGetStackHighWaterMark( xInternalTaskHandle ); + } + } + } + } + + return uxReturn; + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2Impl( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2Impl( TaskHandle_t xTask ) /* PRIVILEGED_FUNCTION */ + { + configSTACK_DEPTH_TYPE uxReturn = 0; + int32_t lIndex; + TaskHandle_t xInternalTaskHandle = NULL; + BaseType_t xCallingTaskIsAuthorizedToAccessTask = pdFALSE; + + if( xTask == NULL ) + { + uxReturn = uxTaskGetStackHighWaterMark2( xTask ); + } + else + { + lIndex = ( int32_t ) xTask; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessTask = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessTask == pdTRUE ) + { + xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTaskHandle != NULL ) + { + uxReturn = uxTaskGetStackHighWaterMark2( xInternalTaskHandle ); + } + } + } + } + + return uxReturn; + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_RECURSIVE_MUTEXES == 1 ) ) + + TaskHandle_t MPU_xTaskGetCurrentTaskHandleImpl( void ) PRIVILEGED_FUNCTION; + + TaskHandle_t MPU_xTaskGetCurrentTaskHandleImpl( void ) /* PRIVILEGED_FUNCTION */ + { + TaskHandle_t xInternalTaskHandle = NULL; + TaskHandle_t xExternalTaskHandle = NULL; + int32_t lIndex; + + xInternalTaskHandle = xTaskGetCurrentTaskHandle(); + + if( xInternalTaskHandle != NULL ) + { + lIndex = MPU_GetIndexForTaskHandle( xInternalTaskHandle ); + + if( lIndex != -1 ) + { + xExternalTaskHandle = ( TaskHandle_t ) CONVERT_TO_EXTERNAL_INDEX( lIndex ); + } + } + + return xExternalTaskHandle; + } + + #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_RECURSIVE_MUTEXES == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetSchedulerState == 1 ) + + BaseType_t MPU_xTaskGetSchedulerStateImpl( void ) PRIVILEGED_FUNCTION; + + BaseType_t MPU_xTaskGetSchedulerStateImpl( void ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xReturn = taskSCHEDULER_NOT_STARTED; + + xReturn = xTaskGetSchedulerState(); + + return xReturn; + } + + #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */ +/*-----------------------------------------------------------*/ + + void MPU_vTaskSetTimeOutStateImpl( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION; + + void MPU_vTaskSetTimeOutStateImpl( TimeOut_t * const pxTimeOut ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xIsTimeOutWriteable = pdFALSE; + + if( pxTimeOut != NULL ) + { + xIsTimeOutWriteable = xPortIsAuthorizedToAccessBuffer( pxTimeOut, + sizeof( TimeOut_t ), + tskMPU_WRITE_PERMISSION ); + + if( xIsTimeOutWriteable == pdTRUE ) + { + vTaskSetTimeOutState( pxTimeOut ); + } + } + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xTaskCheckForTimeOutImpl( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) PRIVILEGED_FUNCTION; + + BaseType_t MPU_xTaskCheckForTimeOutImpl( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xReturn = pdFALSE; + BaseType_t xIsTimeOutWriteable = pdFALSE; + BaseType_t xIsTicksToWaitWriteable = pdFALSE; + + if( ( pxTimeOut != NULL ) && ( pxTicksToWait != NULL ) ) + { + xIsTimeOutWriteable = xPortIsAuthorizedToAccessBuffer( pxTimeOut, + sizeof( TimeOut_t ), + tskMPU_WRITE_PERMISSION ); + xIsTicksToWaitWriteable = xPortIsAuthorizedToAccessBuffer( pxTicksToWait, + sizeof( TickType_t ), + tskMPU_WRITE_PERMISSION ); + + if( ( xIsTimeOutWriteable == pdTRUE ) && ( xIsTicksToWaitWriteable == pdTRUE ) ) + { + xReturn = xTaskCheckForTimeOut( pxTimeOut, pxTicksToWait ); + } + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, + UBaseType_t uxIndexToNotify, + uint32_t ulValue, + eNotifyAction eAction, + uint32_t * pulPreviousNotificationValue ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn = pdFAIL; + xTaskGenericNotifyParams_t xParams; + + xParams.xTaskToNotify = xTaskToNotify; + xParams.uxIndexToNotify = uxIndexToNotify; + xParams.ulValue = ulValue; + xParams.eAction = eAction; + xParams.pulPreviousNotificationValue = pulPreviousNotificationValue; + + xReturn = MPU_xTaskGenericNotifyEntry( &( xParams ) ); + + return xReturn; + } + + BaseType_t MPU_xTaskGenericNotifyImpl( const xTaskGenericNotifyParams_t * pxParams ) PRIVILEGED_FUNCTION; + + BaseType_t MPU_xTaskGenericNotifyImpl( const xTaskGenericNotifyParams_t * pxParams ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xReturn = pdFAIL; + int32_t lIndex; + TaskHandle_t xInternalTaskHandle = NULL; + BaseType_t xIsPreviousNotificationValueWriteable = pdFALSE; + BaseType_t xCallingTaskIsAuthorizedToAccessTask = pdFALSE; + BaseType_t xAreParamsReadable = pdFALSE; + + if( pxParams != NULL ) + { + xAreParamsReadable = xPortIsAuthorizedToAccessBuffer( pxParams, + sizeof( xTaskGenericNotifyParams_t ), + tskMPU_READ_PERMISSION ); + } + + if( xAreParamsReadable == pdTRUE ) + { + if( ( pxParams->uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES ) && + ( ( pxParams->eAction == eNoAction ) || + ( pxParams->eAction == eSetBits ) || + ( pxParams->eAction == eIncrement ) || + ( pxParams->eAction == eSetValueWithOverwrite ) || + ( pxParams->eAction == eSetValueWithoutOverwrite ) ) ) + { + if( pxParams->pulPreviousNotificationValue != NULL ) + { + xIsPreviousNotificationValueWriteable = xPortIsAuthorizedToAccessBuffer( pxParams->pulPreviousNotificationValue, + sizeof( uint32_t ), + tskMPU_WRITE_PERMISSION ); + } + + if( ( pxParams->pulPreviousNotificationValue == NULL ) || + ( xIsPreviousNotificationValueWriteable == pdTRUE ) ) + { + lIndex = ( int32_t ) ( pxParams->xTaskToNotify ); + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessTask = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessTask == pdTRUE ) + { + xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTaskHandle != NULL ) + { + xReturn = xTaskGenericNotify( xInternalTaskHandle, + pxParams->uxIndexToNotify, + pxParams->ulValue, + pxParams->eAction, + pxParams->pulPreviousNotificationValue ); + } + } + } + } + } + } + + return xReturn; + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn, + uint32_t ulBitsToClearOnEntry, + uint32_t ulBitsToClearOnExit, + uint32_t * pulNotificationValue, + TickType_t xTicksToWait ) + { + BaseType_t xReturn = pdFAIL; + xTaskGenericNotifyWaitParams_t xParams; + + xParams.uxIndexToWaitOn = uxIndexToWaitOn; + xParams.ulBitsToClearOnEntry = ulBitsToClearOnEntry; + xParams.ulBitsToClearOnExit = ulBitsToClearOnExit; + xParams.pulNotificationValue = pulNotificationValue; + xParams.xTicksToWait = xTicksToWait; + + xReturn = MPU_xTaskGenericNotifyWaitEntry( &( xParams ) ); + + return xReturn; + } + + BaseType_t MPU_xTaskGenericNotifyWaitImpl( const xTaskGenericNotifyWaitParams_t * pxParams ) PRIVILEGED_FUNCTION; + + BaseType_t MPU_xTaskGenericNotifyWaitImpl( const xTaskGenericNotifyWaitParams_t * pxParams ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xReturn = pdFAIL; + BaseType_t xIsNotificationValueWritable = pdFALSE; + BaseType_t xAreParamsReadable = pdFALSE; + + if( pxParams != NULL ) + { + xAreParamsReadable = xPortIsAuthorizedToAccessBuffer( pxParams, + sizeof( xTaskGenericNotifyWaitParams_t ), + tskMPU_READ_PERMISSION ); + } + + if( xAreParamsReadable == pdTRUE ) + { + if( pxParams->uxIndexToWaitOn < configTASK_NOTIFICATION_ARRAY_ENTRIES ) + { + if( pxParams->pulNotificationValue != NULL ) + { + xIsNotificationValueWritable = xPortIsAuthorizedToAccessBuffer( pxParams->pulNotificationValue, + sizeof( uint32_t ), + tskMPU_WRITE_PERMISSION ); + } + + if( ( pxParams->pulNotificationValue == NULL ) || + ( xIsNotificationValueWritable == pdTRUE ) ) + { + xReturn = xTaskGenericNotifyWait( pxParams->uxIndexToWaitOn, + pxParams->ulBitsToClearOnEntry, + pxParams->ulBitsToClearOnExit, + pxParams->pulNotificationValue, + pxParams->xTicksToWait ); + } + } + } + + return xReturn; + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyTakeImpl( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + + uint32_t MPU_ulTaskGenericNotifyTakeImpl( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulReturn = 0; + + if( uxIndexToWaitOn < configTASK_NOTIFICATION_ARRAY_ENTRIES ) + { + ulReturn = ulTaskGenericNotifyTake( uxIndexToWaitOn, xClearCountOnExit, xTicksToWait ); + } + + return ulReturn; + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyStateClearImpl( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) PRIVILEGED_FUNCTION; + + BaseType_t MPU_xTaskGenericNotifyStateClearImpl( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xReturn = pdFAIL; + int32_t lIndex; + TaskHandle_t xInternalTaskHandle = NULL; + BaseType_t xCallingTaskIsAuthorizedToAccessTask = pdFALSE; + + if( uxIndexToClear < configTASK_NOTIFICATION_ARRAY_ENTRIES ) + { + if( xTask == NULL ) + { + xReturn = xTaskGenericNotifyStateClear( xTask, uxIndexToClear ); + } + else + { + lIndex = ( int32_t ) xTask; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessTask = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessTask == pdTRUE ) + { + xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTaskHandle != NULL ) + { + xReturn = xTaskGenericNotifyStateClear( xInternalTaskHandle, uxIndexToClear ); + } + } + } + } + } + + return xReturn; + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyValueClearImpl( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION; + + uint32_t MPU_ulTaskGenericNotifyValueClearImpl( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulReturn = 0; + int32_t lIndex; + TaskHandle_t xInternalTaskHandle = NULL; + BaseType_t xCallingTaskIsAuthorizedToAccessTask = pdFALSE; + + if( uxIndexToClear < configTASK_NOTIFICATION_ARRAY_ENTRIES ) + { + if( xTask == NULL ) + { + ulReturn = ulTaskGenericNotifyValueClear( xTask, uxIndexToClear, ulBitsToClear ); + } + else + { + lIndex = ( int32_t ) xTask; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessTask = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessTask == pdTRUE ) + { + xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTaskHandle != NULL ) + { + ulReturn = ulTaskGenericNotifyValueClear( xInternalTaskHandle, uxIndexToClear, ulBitsToClear ); + } + } + } + } + } + + return ulReturn; + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + +/* Privileged only wrappers for Task APIs. These are needed so that + * the application can use opaque handles maintained in mpu_wrappers.c + * with all the APIs. */ +/*-----------------------------------------------------------*/ + + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + BaseType_t MPU_xTaskCreate( TaskFunction_t pvTaskCode, + const char * const pcName, + const configSTACK_DEPTH_TYPE uxStackDepth, + void * pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * pxCreatedTask ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xReturn = pdFAIL; + int32_t lIndex; + TaskHandle_t xInternalTaskHandle = NULL; + + lIndex = MPU_GetFreeIndexInKernelObjectPool(); + + if( lIndex != -1 ) + { + /* xTaskCreate() can only be used to create privileged tasks in MPU port. */ + if( ( uxPriority & portPRIVILEGE_BIT ) != 0 ) + { + xReturn = xTaskCreate( pvTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, &( xInternalTaskHandle ) ); + + if( ( xReturn == pdPASS ) && ( xInternalTaskHandle != NULL ) ) + { + MPU_StoreTaskHandleAtIndex( lIndex, xInternalTaskHandle ); + + if( pxCreatedTask != NULL ) + { + *pxCreatedTask = ( TaskHandle_t ) CONVERT_TO_EXTERNAL_INDEX( lIndex ); + } + } + else + { + MPU_SetIndexFreeInKernelObjectPool( lIndex ); + } + } + } + + return xReturn; + } + + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + + TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, + const char * const pcName, + const configSTACK_DEPTH_TYPE uxStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + StackType_t * const puxStackBuffer, + StaticTask_t * const pxTaskBuffer ) /* PRIVILEGED_FUNCTION */ + { + TaskHandle_t xExternalTaskHandle = NULL; + TaskHandle_t xInternalTaskHandle = NULL; + int32_t lIndex; + + lIndex = MPU_GetFreeIndexInKernelObjectPool(); + + if( lIndex != -1 ) + { + xInternalTaskHandle = xTaskCreateStatic( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer ); + + if( xInternalTaskHandle != NULL ) + { + MPU_StoreTaskHandleAtIndex( lIndex, xInternalTaskHandle ); + + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + { + /* By default, an unprivileged task has access to itself. */ + if( ( uxPriority & portPRIVILEGE_BIT ) == 0 ) + { + vPortGrantAccessToKernelObject( xInternalTaskHandle, lIndex ); + } + } + #endif + + xExternalTaskHandle = ( TaskHandle_t ) CONVERT_TO_EXTERNAL_INDEX( lIndex ); + } + else + { + MPU_SetIndexFreeInKernelObjectPool( lIndex ); + } + } + + return xExternalTaskHandle; + } + + #endif /* configSUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskDelete == 1 ) + + void MPU_vTaskDelete( TaskHandle_t pxTaskToDelete ) /* PRIVILEGED_FUNCTION */ + { + TaskHandle_t xInternalTaskHandle = NULL; + int32_t lIndex; + + if( pxTaskToDelete == NULL ) + { + xInternalTaskHandle = xTaskGetCurrentTaskHandle(); + lIndex = MPU_GetIndexForTaskHandle( xInternalTaskHandle ); + + if( lIndex != -1 ) + { + MPU_SetIndexFreeInKernelObjectPool( lIndex ); + } + + vTaskDelete( xInternalTaskHandle ); + } + else + { + lIndex = ( int32_t ) pxTaskToDelete; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTaskHandle != NULL ) + { + MPU_SetIndexFreeInKernelObjectPool( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + vTaskDelete( xInternalTaskHandle ); + } + } + } + } + + #endif /* #if ( INCLUDE_vTaskDelete == 1 ) */ +/*-----------------------------------------------------------*/ + + + #if ( INCLUDE_vTaskPrioritySet == 1 ) + + void MPU_vTaskPrioritySet( TaskHandle_t pxTask, + UBaseType_t uxNewPriority ) /* PRIVILEGED_FUNCTION */ + { + TaskHandle_t xInternalTaskHandle = NULL; + int32_t lIndex; + + if( pxTask == NULL ) + { + vTaskPrioritySet( pxTask, uxNewPriority ); + } + else + { + lIndex = ( int32_t ) pxTask; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTaskHandle != NULL ) + { + vTaskPrioritySet( xInternalTaskHandle, uxNewPriority ); + } + } + } + } + + #endif /* if ( INCLUDE_vTaskPrioritySet == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetHandle == 1 ) + + TaskHandle_t MPU_xTaskGetHandle( const char * pcNameToQuery ) /* PRIVILEGED_FUNCTION */ + { + TaskHandle_t xInternalTaskHandle = NULL; + TaskHandle_t xExternalTaskHandle = NULL; + int32_t lIndex; + + xInternalTaskHandle = xTaskGetHandle( pcNameToQuery ); + + if( xInternalTaskHandle != NULL ) + { + lIndex = MPU_GetIndexForTaskHandle( xInternalTaskHandle ); + + if( lIndex != -1 ) + { + xExternalTaskHandle = ( TaskHandle_t ) CONVERT_TO_EXTERNAL_INDEX( lIndex ); + } + } + + return xExternalTaskHandle; + } + + #endif /* if ( INCLUDE_xTaskGetHandle == 1 ) */ +/*-----------------------------------------------------------*/ + + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, + void * pvParameter ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xReturn = pdFAIL; + int32_t lIndex; + TaskHandle_t xInternalTaskHandle = NULL; + + if( xTask == NULL ) + { + xReturn = xTaskCallApplicationTaskHook( xTask, pvParameter ); + } + else + { + lIndex = ( int32_t ) xTask; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTaskHandle != NULL ) + { + xReturn = xTaskCallApplicationTaskHook( xInternalTaskHandle, pvParameter ); + } + } + } + + return xReturn; + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, + TaskHandle_t * pxCreatedTask ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xReturn = pdFAIL; + int32_t lIndex; + TaskHandle_t xInternalTaskHandle = NULL; + + lIndex = MPU_GetFreeIndexInKernelObjectPool(); + + if( lIndex != -1 ) + { + xReturn = xTaskCreateRestricted( pxTaskDefinition, &( xInternalTaskHandle ) ); + + if( ( xReturn == pdPASS ) && ( xInternalTaskHandle != NULL ) ) + { + MPU_StoreTaskHandleAtIndex( lIndex, xInternalTaskHandle ); + + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + { + /* By default, an unprivileged task has access to itself. */ + if( ( pxTaskDefinition->uxPriority & portPRIVILEGE_BIT ) == 0 ) + { + vPortGrantAccessToKernelObject( xInternalTaskHandle, lIndex ); + } + } + #endif + + if( pxCreatedTask != NULL ) + { + *pxCreatedTask = ( TaskHandle_t ) CONVERT_TO_EXTERNAL_INDEX( lIndex ); + } + } + else + { + MPU_SetIndexFreeInKernelObjectPool( lIndex ); + } + } + + return xReturn; + } + + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + + BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, + TaskHandle_t * pxCreatedTask ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xReturn = pdFAIL; + int32_t lIndex; + TaskHandle_t xInternalTaskHandle = NULL; + + lIndex = MPU_GetFreeIndexInKernelObjectPool(); + + if( lIndex != -1 ) + { + xReturn = xTaskCreateRestrictedStatic( pxTaskDefinition, &( xInternalTaskHandle ) ); + + if( ( xReturn == pdPASS ) && ( xInternalTaskHandle != NULL ) ) + { + MPU_StoreTaskHandleAtIndex( lIndex, xInternalTaskHandle ); + + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + { + /* By default, an unprivileged task has access to itself. */ + if( ( pxTaskDefinition->uxPriority & portPRIVILEGE_BIT ) == 0 ) + { + vPortGrantAccessToKernelObject( xInternalTaskHandle, lIndex ); + } + } + #endif + + if( pxCreatedTask != NULL ) + { + *pxCreatedTask = ( TaskHandle_t ) CONVERT_TO_EXTERNAL_INDEX( lIndex ); + } + } + else + { + MPU_SetIndexFreeInKernelObjectPool( lIndex ); + } + } + + return xReturn; + } + + #endif /* configSUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + + void MPU_vTaskAllocateMPURegions( TaskHandle_t xTaskToModify, + const MemoryRegion_t * const xRegions ) /* PRIVILEGED_FUNCTION */ + { + TaskHandle_t xInternalTaskHandle = NULL; + int32_t lIndex; + + if( xTaskToModify == NULL ) + { + vTaskAllocateMPURegions( xTaskToModify, xRegions ); + } + else + { + lIndex = ( int32_t ) xTaskToModify; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTaskHandle != NULL ) + { + vTaskAllocateMPURegions( xInternalTaskHandle, xRegions ); + } + } + } + } +/*-----------------------------------------------------------*/ + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + + BaseType_t MPU_xTaskGetStaticBuffers( TaskHandle_t xTask, + StackType_t ** ppuxStackBuffer, + StaticTask_t ** ppxTaskBuffer ) /* PRIVILEGED_FUNCTION */ + { + TaskHandle_t xInternalTaskHandle = NULL; + int32_t lIndex; + BaseType_t xReturn = pdFALSE; + + if( xTask == NULL ) + { + xInternalTaskHandle = xTaskGetCurrentTaskHandle(); + xReturn = xTaskGetStaticBuffers( xInternalTaskHandle, ppuxStackBuffer, ppxTaskBuffer ); + } + else + { + lIndex = ( int32_t ) xTask; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTaskHandle != NULL ) + { + xReturn = xTaskGetStaticBuffers( xInternalTaskHandle, ppuxStackBuffer, ppxTaskBuffer ); + } + } + } + + return xReturn; + } + + #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ +/*-----------------------------------------------------------*/ + + char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* PRIVILEGED_FUNCTION */ + { + char * pcReturn = NULL; + int32_t lIndex; + TaskHandle_t xInternalTaskHandle = NULL; + + if( xTaskToQuery == NULL ) + { + pcReturn = pcTaskGetName( xTaskToQuery ); + } + else + { + lIndex = ( int32_t ) xTaskToQuery; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTaskHandle != NULL ) + { + pcReturn = pcTaskGetName( xInternalTaskHandle ); + } + } + } + + return pcReturn; + } +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskPriorityGet == 1 ) + + UBaseType_t MPU_uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) /* PRIVILEGED_FUNCTION */ + { + UBaseType_t uxReturn = configMAX_PRIORITIES; + int32_t lIndex; + TaskHandle_t xInternalTaskHandle = NULL; + + if( xTask == NULL ) + { + uxReturn = uxTaskPriorityGetFromISR( xTask ); + } + else + { + lIndex = ( int32_t ) xTask; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTaskHandle != NULL ) + { + uxReturn = uxTaskPriorityGetFromISR( xInternalTaskHandle ); + } + } + } + + return uxReturn; + } + + #endif /* #if ( INCLUDE_uxTaskPriorityGet == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( INCLUDE_uxTaskPriorityGet == 1 ) && ( configUSE_MUTEXES == 1 ) ) + + UBaseType_t MPU_uxTaskBasePriorityGet( const TaskHandle_t xTask ) /* PRIVILEGED_FUNCTION */ + { + UBaseType_t uxReturn = configMAX_PRIORITIES; + int32_t lIndex; + TaskHandle_t xInternalTaskHandle = NULL; + + if( xTask == NULL ) + { + uxReturn = uxTaskBasePriorityGet( xTask ); + } + else + { + lIndex = ( int32_t ) xTask; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTaskHandle != NULL ) + { + uxReturn = uxTaskBasePriorityGet( xInternalTaskHandle ); + } + } + } + + return uxReturn; + } + + #endif /* #if ( ( INCLUDE_uxTaskPriorityGet == 1 ) && ( configUSE_MUTEXES == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( INCLUDE_uxTaskPriorityGet == 1 ) && ( configUSE_MUTEXES == 1 ) ) + + UBaseType_t MPU_uxTaskBasePriorityGetFromISR( const TaskHandle_t xTask ) /* PRIVILEGED_FUNCTION */ + { + UBaseType_t uxReturn = configMAX_PRIORITIES; + int32_t lIndex; + TaskHandle_t xInternalTaskHandle = NULL; + + if( xTask == NULL ) + { + uxReturn = uxTaskBasePriorityGetFromISR( xTask ); + } + else + { + lIndex = ( int32_t ) xTask; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTaskHandle != NULL ) + { + uxReturn = uxTaskBasePriorityGetFromISR( xInternalTaskHandle ); + } + } + } + + return uxReturn; + } + + #endif /* #if ( ( INCLUDE_uxTaskPriorityGet == 1 ) && ( configUSE_MUTEXES == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) + + BaseType_t MPU_xTaskResumeFromISR( TaskHandle_t xTaskToResume ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xReturn = pdFAIL; + int32_t lIndex; + TaskHandle_t xInternalTaskHandle = NULL; + + lIndex = ( int32_t ) xTaskToResume; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTaskHandle != NULL ) + { + xReturn = xTaskResumeFromISR( xInternalTaskHandle ); + } + } + + return xReturn; + } + + #endif /* #if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) )*/ +/*---------------------------------------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask ) /* PRIVILEGED_FUNCTION */ + { + TaskHookFunction_t xReturn = NULL; + int32_t lIndex; + TaskHandle_t xInternalTaskHandle = NULL; + + if( xTask == NULL ) + { + xReturn = xTaskGetApplicationTaskTagFromISR( xTask ); + } + else + { + lIndex = ( int32_t ) xTask; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTaskHandle != NULL ) + { + xReturn = xTaskGetApplicationTaskTagFromISR( xInternalTaskHandle ); + } + } + } + + return xReturn; + } + + #endif /* #if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*---------------------------------------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, + UBaseType_t uxIndexToNotify, + uint32_t ulValue, + eNotifyAction eAction, + uint32_t * pulPreviousNotificationValue, + BaseType_t * pxHigherPriorityTaskWoken ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xReturn = pdFAIL; + int32_t lIndex; + TaskHandle_t xInternalTaskHandle = NULL; + + lIndex = ( int32_t ) xTaskToNotify; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTaskHandle != NULL ) + { + xReturn = xTaskGenericNotifyFromISR( xInternalTaskHandle, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken ); + } + } + + return xReturn; + } + + #endif /* #if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*---------------------------------------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + void MPU_vTaskGenericNotifyGiveFromISR( TaskHandle_t xTaskToNotify, + UBaseType_t uxIndexToNotify, + BaseType_t * pxHigherPriorityTaskWoken ) /* PRIVILEGED_FUNCTION */ + { + int32_t lIndex; + TaskHandle_t xInternalTaskHandle = NULL; + + lIndex = ( int32_t ) xTaskToNotify; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xInternalTaskHandle = MPU_GetTaskHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTaskHandle != NULL ) + { + vTaskGenericNotifyGiveFromISR( xInternalTaskHandle, uxIndexToNotify, pxHigherPriorityTaskWoken ); + } + } + } + #endif /*#if ( configUSE_TASK_NOTIFICATIONS == 1 )*/ +/*-----------------------------------------------------------*/ + +/*-----------------------------------------------------------*/ +/* MPU wrappers for queue APIs. */ +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueGenericSendImpl( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION; + + BaseType_t MPU_xQueueGenericSendImpl( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + BaseType_t xCopyPosition ) /* PRIVILEGED_FUNCTION */ + { + int32_t lIndex; + QueueHandle_t xInternalQueueHandle = NULL; + BaseType_t xReturn = pdFAIL; + BaseType_t xIsItemToQueueReadable = pdFALSE; + BaseType_t xCallingTaskIsAuthorizedToAccessQueue = pdFALSE; + UBaseType_t uxQueueItemSize, uxQueueLength; + + lIndex = ( int32_t ) xQueue; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessQueue = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessQueue == pdTRUE ) + { + xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalQueueHandle != NULL ) + { + uxQueueItemSize = uxQueueGetQueueItemSize( xInternalQueueHandle ); + uxQueueLength = uxQueueGetQueueLength( xInternalQueueHandle ); + + if( ( !( ( pvItemToQueue == NULL ) && ( uxQueueItemSize != ( UBaseType_t ) 0U ) ) ) && + ( !( ( xCopyPosition == queueOVERWRITE ) && ( uxQueueLength != ( UBaseType_t ) 1U ) ) ) + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0U ) ) ) + #endif + ) + { + if( pvItemToQueue != NULL ) + { + xIsItemToQueueReadable = xPortIsAuthorizedToAccessBuffer( pvItemToQueue, + uxQueueItemSize, + tskMPU_READ_PERMISSION ); + } + + if( ( pvItemToQueue == NULL ) || ( xIsItemToQueueReadable == pdTRUE ) ) + { + xReturn = xQueueGenericSend( xInternalQueueHandle, pvItemToQueue, xTicksToWait, xCopyPosition ); + } + } + } + } + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueMessagesWaitingImpl( const QueueHandle_t pxQueue ) PRIVILEGED_FUNCTION; + + UBaseType_t MPU_uxQueueMessagesWaitingImpl( const QueueHandle_t pxQueue ) /* PRIVILEGED_FUNCTION */ + { + int32_t lIndex; + QueueHandle_t xInternalQueueHandle = NULL; + UBaseType_t uxReturn = 0; + BaseType_t xCallingTaskIsAuthorizedToAccessQueue = pdFALSE; + + lIndex = ( int32_t ) pxQueue; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessQueue = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessQueue == pdTRUE ) + { + xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalQueueHandle != NULL ) + { + uxReturn = uxQueueMessagesWaiting( xInternalQueueHandle ); + } + } + } + + return uxReturn; + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueSpacesAvailableImpl( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; + + UBaseType_t MPU_uxQueueSpacesAvailableImpl( const QueueHandle_t xQueue ) /* PRIVILEGED_FUNCTION */ + { + int32_t lIndex; + QueueHandle_t xInternalQueueHandle = NULL; + UBaseType_t uxReturn = 0; + BaseType_t xCallingTaskIsAuthorizedToAccessQueue = pdFALSE; + + lIndex = ( int32_t ) xQueue; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessQueue = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessQueue == pdTRUE ) + { + xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalQueueHandle != NULL ) + { + uxReturn = uxQueueSpacesAvailable( xInternalQueueHandle ); + } + } + } + + return uxReturn; + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueReceiveImpl( QueueHandle_t pxQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + + BaseType_t MPU_xQueueReceiveImpl( QueueHandle_t pxQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* PRIVILEGED_FUNCTION */ + { + int32_t lIndex; + QueueHandle_t xInternalQueueHandle = NULL; + BaseType_t xReturn = pdFAIL; + BaseType_t xIsReceiveBufferWritable = pdFALSE; + BaseType_t xCallingTaskIsAuthorizedToAccessQueue = pdFALSE; + UBaseType_t uxQueueItemSize; + + lIndex = ( int32_t ) pxQueue; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessQueue = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessQueue == pdTRUE ) + { + xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalQueueHandle != NULL ) + { + uxQueueItemSize = uxQueueGetQueueItemSize( xInternalQueueHandle ); + + if( ( !( ( ( pvBuffer ) == NULL ) && ( uxQueueItemSize != ( UBaseType_t ) 0U ) ) ) + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0U ) ) ) + #endif + ) + { + xIsReceiveBufferWritable = xPortIsAuthorizedToAccessBuffer( pvBuffer, + uxQueueItemSize, + tskMPU_WRITE_PERMISSION ); + + if( xIsReceiveBufferWritable == pdTRUE ) + { + xReturn = xQueueReceive( xInternalQueueHandle, pvBuffer, xTicksToWait ); + } + } + } + } + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueuePeekImpl( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + + BaseType_t MPU_xQueuePeekImpl( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* PRIVILEGED_FUNCTION */ + { + int32_t lIndex; + QueueHandle_t xInternalQueueHandle = NULL; + BaseType_t xReturn = pdFAIL; + BaseType_t xIsReceiveBufferWritable = pdFALSE; + UBaseType_t uxQueueItemSize; + BaseType_t xCallingTaskIsAuthorizedToAccessQueue = pdFALSE; + + lIndex = ( int32_t ) xQueue; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessQueue = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessQueue == pdTRUE ) + { + xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalQueueHandle != NULL ) + { + uxQueueItemSize = uxQueueGetQueueItemSize( xInternalQueueHandle ); + + if( ( !( ( ( pvBuffer ) == NULL ) && ( uxQueueItemSize != ( UBaseType_t ) 0U ) ) ) + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0U ) ) ) + #endif + ) + { + xIsReceiveBufferWritable = xPortIsAuthorizedToAccessBuffer( pvBuffer, + uxQueueItemSize, + tskMPU_WRITE_PERMISSION ); + + if( xIsReceiveBufferWritable == pdTRUE ) + { + xReturn = xQueuePeek( xInternalQueueHandle, pvBuffer, xTicksToWait ); + } + } + } + } + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueSemaphoreTakeImpl( QueueHandle_t xQueue, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + + BaseType_t MPU_xQueueSemaphoreTakeImpl( QueueHandle_t xQueue, + TickType_t xTicksToWait ) /* PRIVILEGED_FUNCTION */ + { + int32_t lIndex; + QueueHandle_t xInternalQueueHandle = NULL; + BaseType_t xReturn = pdFAIL; + UBaseType_t uxQueueItemSize; + BaseType_t xCallingTaskIsAuthorizedToAccessQueue = pdFALSE; + + lIndex = ( int32_t ) xQueue; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessQueue = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessQueue == pdTRUE ) + { + xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalQueueHandle != NULL ) + { + uxQueueItemSize = uxQueueGetQueueItemSize( xInternalQueueHandle ); + + if( ( uxQueueItemSize == 0U ) + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0U ) ) ) + #endif + ) + { + xReturn = xQueueSemaphoreTake( xInternalQueueHandle, xTicksToWait ); + } + } + } + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) + + TaskHandle_t MPU_xQueueGetMutexHolderImpl( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION; + + TaskHandle_t MPU_xQueueGetMutexHolderImpl( QueueHandle_t xSemaphore ) /* PRIVILEGED_FUNCTION */ + { + TaskHandle_t xMutexHolderTaskInternalHandle = NULL; + TaskHandle_t xMutexHolderTaskExternalHandle = NULL; + int32_t lIndex, lMutexHolderTaskIndex; + QueueHandle_t xInternalQueueHandle = NULL; + BaseType_t xCallingTaskIsAuthorizedToAccessQueue = pdFALSE; + + + lIndex = ( int32_t ) xSemaphore; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessQueue = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessQueue == pdTRUE ) + { + xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalQueueHandle != NULL ) + { + xMutexHolderTaskInternalHandle = xQueueGetMutexHolder( xInternalQueueHandle ); + + if( xMutexHolderTaskInternalHandle != NULL ) + { + lMutexHolderTaskIndex = MPU_GetIndexForTaskHandle( xMutexHolderTaskInternalHandle ); + + if( lMutexHolderTaskIndex != -1 ) + { + xMutexHolderTaskExternalHandle = ( TaskHandle_t ) ( CONVERT_TO_EXTERNAL_INDEX( lMutexHolderTaskIndex ) ); + } + } + } + } + } + + return xMutexHolderTaskExternalHandle; + } + + #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueTakeMutexRecursiveImpl( QueueHandle_t xMutex, + TickType_t xBlockTime ) PRIVILEGED_FUNCTION; + + BaseType_t MPU_xQueueTakeMutexRecursiveImpl( QueueHandle_t xMutex, + TickType_t xBlockTime ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xReturn = pdFAIL; + BaseType_t xCallingTaskIsAuthorizedToAccessQueue = pdFALSE; + int32_t lIndex; + QueueHandle_t xInternalQueueHandle = NULL; + UBaseType_t uxQueueItemSize; + + lIndex = ( int32_t ) xMutex; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessQueue = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessQueue == pdTRUE ) + { + xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalQueueHandle != NULL ) + { + uxQueueItemSize = uxQueueGetQueueItemSize( xInternalQueueHandle ); + + if( uxQueueItemSize == 0 ) + { + xReturn = xQueueTakeMutexRecursive( xInternalQueueHandle, xBlockTime ); + } + } + } + } + + return xReturn; + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueGiveMutexRecursiveImpl( QueueHandle_t xMutex ) PRIVILEGED_FUNCTION; + + BaseType_t MPU_xQueueGiveMutexRecursiveImpl( QueueHandle_t xMutex ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xReturn = pdFAIL; + BaseType_t xCallingTaskIsAuthorizedToAccessQueue = pdFALSE; + int32_t lIndex; + QueueHandle_t xInternalQueueHandle = NULL; + + lIndex = ( int32_t ) xMutex; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessQueue = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessQueue == pdTRUE ) + { + xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalQueueHandle != NULL ) + { + xReturn = xQueueGiveMutexRecursive( xInternalQueueHandle ); + } + } + } + + return xReturn; + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + QueueSetMemberHandle_t MPU_xQueueSelectFromSetImpl( QueueSetHandle_t xQueueSet, + TickType_t xBlockTimeTicks ) PRIVILEGED_FUNCTION; + + QueueSetMemberHandle_t MPU_xQueueSelectFromSetImpl( QueueSetHandle_t xQueueSet, + TickType_t xBlockTimeTicks ) /* PRIVILEGED_FUNCTION */ + { + QueueSetHandle_t xInternalQueueSetHandle = NULL; + QueueSetMemberHandle_t xSelectedMemberInternal = NULL; + QueueSetMemberHandle_t xSelectedMemberExternal = NULL; + int32_t lIndexQueueSet, lIndexSelectedMember; + BaseType_t xCallingTaskIsAuthorizedToAccessQueueSet = pdFALSE; + + lIndexQueueSet = ( int32_t ) xQueueSet; + + if( IS_EXTERNAL_INDEX_VALID( lIndexQueueSet ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessQueueSet = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndexQueueSet ) ); + + if( xCallingTaskIsAuthorizedToAccessQueueSet == pdTRUE ) + { + xInternalQueueSetHandle = MPU_GetQueueSetHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndexQueueSet ) ); + + if( xInternalQueueSetHandle != NULL ) + { + xSelectedMemberInternal = xQueueSelectFromSet( xInternalQueueSetHandle, xBlockTimeTicks ); + + if( xSelectedMemberInternal != NULL ) + { + lIndexSelectedMember = MPU_GetIndexForQueueSetMemberHandle( xSelectedMemberInternal ); + + if( lIndexSelectedMember != -1 ) + { + xSelectedMemberExternal = ( QueueSetMemberHandle_t ) ( CONVERT_TO_EXTERNAL_INDEX( lIndexSelectedMember ) ); + } + } + } + } + } + + return xSelectedMemberExternal; + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + BaseType_t MPU_xQueueAddToSetImpl( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION; + + BaseType_t MPU_xQueueAddToSetImpl( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xReturn = pdFAIL; + QueueSetMemberHandle_t xInternalQueueSetMemberHandle = NULL; + QueueSetHandle_t xInternalQueueSetHandle = NULL; + int32_t lIndexQueueSet, lIndexQueueSetMember; + BaseType_t xCallingTaskIsAuthorizedToAccessQueueSet = pdFALSE; + BaseType_t xCallingTaskIsAuthorizedToAccessQueueSetMember = pdFALSE; + + lIndexQueueSet = ( int32_t ) xQueueSet; + lIndexQueueSetMember = ( int32_t ) xQueueOrSemaphore; + + if( ( IS_EXTERNAL_INDEX_VALID( lIndexQueueSet ) != pdFALSE ) && + ( IS_EXTERNAL_INDEX_VALID( lIndexQueueSetMember ) != pdFALSE ) ) + { + xCallingTaskIsAuthorizedToAccessQueueSet = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndexQueueSet ) ); + xCallingTaskIsAuthorizedToAccessQueueSetMember = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndexQueueSetMember ) ); + + if( ( xCallingTaskIsAuthorizedToAccessQueueSet == pdTRUE ) && ( xCallingTaskIsAuthorizedToAccessQueueSetMember == pdTRUE ) ) + { + xInternalQueueSetHandle = MPU_GetQueueSetHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndexQueueSet ) ); + xInternalQueueSetMemberHandle = MPU_GetQueueSetMemberHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndexQueueSetMember ) ); + + if( ( xInternalQueueSetHandle != NULL ) && ( xInternalQueueSetMemberHandle != NULL ) ) + { + xReturn = xQueueAddToSet( xInternalQueueSetMemberHandle, xInternalQueueSetHandle ); + } + } + } + + return xReturn; + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if configQUEUE_REGISTRY_SIZE > 0 + + void MPU_vQueueAddToRegistryImpl( QueueHandle_t xQueue, + const char * pcName ) PRIVILEGED_FUNCTION; + + void MPU_vQueueAddToRegistryImpl( QueueHandle_t xQueue, + const char * pcName ) /* PRIVILEGED_FUNCTION */ + { + int32_t lIndex; + QueueHandle_t xInternalQueueHandle = NULL; + BaseType_t xCallingTaskIsAuthorizedToAccessQueue = pdFALSE; + + lIndex = ( int32_t ) xQueue; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessQueue = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessQueue == pdTRUE ) + { + xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalQueueHandle != NULL ) + { + vQueueAddToRegistry( xInternalQueueHandle, pcName ); + } + } + } + } + + #endif /* if configQUEUE_REGISTRY_SIZE > 0 */ +/*-----------------------------------------------------------*/ + + #if configQUEUE_REGISTRY_SIZE > 0 + + void MPU_vQueueUnregisterQueueImpl( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; + + void MPU_vQueueUnregisterQueueImpl( QueueHandle_t xQueue ) /* PRIVILEGED_FUNCTION */ + { + int32_t lIndex; + QueueHandle_t xInternalQueueHandle = NULL; + BaseType_t xCallingTaskIsAuthorizedToAccessQueue = pdFALSE; + + lIndex = ( int32_t ) xQueue; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessQueue = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessQueue == pdTRUE ) + { + xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalQueueHandle != NULL ) + { + vQueueUnregisterQueue( xInternalQueueHandle ); + } + } + } + } + + #endif /* if configQUEUE_REGISTRY_SIZE > 0 */ +/*-----------------------------------------------------------*/ + + #if configQUEUE_REGISTRY_SIZE > 0 + + const char * MPU_pcQueueGetNameImpl( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; + + const char * MPU_pcQueueGetNameImpl( QueueHandle_t xQueue ) /* PRIVILEGED_FUNCTION */ + { + const char * pcReturn = NULL; + QueueHandle_t xInternalQueueHandle = NULL; + int32_t lIndex; + BaseType_t xCallingTaskIsAuthorizedToAccessQueue = pdFALSE; + + lIndex = ( int32_t ) xQueue; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessQueue = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessQueue == pdTRUE ) + { + xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalQueueHandle != NULL ) + { + pcReturn = pcQueueGetName( xInternalQueueHandle ); + } + } + } + + return pcReturn; + } + + #endif /* if configQUEUE_REGISTRY_SIZE > 0 */ +/*-----------------------------------------------------------*/ + +/* Privileged only wrappers for Queue APIs. These are needed so that + * the application can use opaque handles maintained in mpu_wrappers.c + * with all the APIs. */ +/*-----------------------------------------------------------*/ + + void MPU_vQueueDelete( QueueHandle_t xQueue ) /* PRIVILEGED_FUNCTION */ + { + QueueHandle_t xInternalQueueHandle = NULL; + int32_t lIndex; + + lIndex = ( int32_t ) xQueue; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalQueueHandle != NULL ) + { + vQueueDelete( xInternalQueueHandle ); + MPU_SetIndexFreeInKernelObjectPool( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + } + } + } +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + + QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) /* PRIVILEGED_FUNCTION */ + { + QueueHandle_t xInternalQueueHandle = NULL; + QueueHandle_t xExternalQueueHandle = NULL; + int32_t lIndex; + + lIndex = MPU_GetFreeIndexInKernelObjectPool(); + + if( lIndex != -1 ) + { + xInternalQueueHandle = xQueueCreateMutex( ucQueueType ); + + if( xInternalQueueHandle != NULL ) + { + MPU_StoreQueueHandleAtIndex( lIndex, xInternalQueueHandle ); + xExternalQueueHandle = ( QueueHandle_t ) CONVERT_TO_EXTERNAL_INDEX( lIndex ); + } + else + { + MPU_SetIndexFreeInKernelObjectPool( lIndex ); + } + } + + return xExternalQueueHandle; + } + + #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + + QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, + StaticQueue_t * pxStaticQueue ) /* PRIVILEGED_FUNCTION */ + { + QueueHandle_t xInternalQueueHandle = NULL; + QueueHandle_t xExternalQueueHandle = NULL; + int32_t lIndex; + + lIndex = MPU_GetFreeIndexInKernelObjectPool(); + + if( lIndex != -1 ) + { + xInternalQueueHandle = xQueueCreateMutexStatic( ucQueueType, pxStaticQueue ); + + if( xInternalQueueHandle != NULL ) + { + MPU_StoreQueueHandleAtIndex( lIndex, xInternalQueueHandle ); + xExternalQueueHandle = ( QueueHandle_t ) CONVERT_TO_EXTERNAL_INDEX( lIndex ); + } + else + { + MPU_SetIndexFreeInKernelObjectPool( lIndex ); + } + } + + return xExternalQueueHandle; + } + + #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + + QueueHandle_t MPU_xQueueCreateCountingSemaphore( UBaseType_t uxCountValue, + UBaseType_t uxInitialCount ) /* PRIVILEGED_FUNCTION */ + { + QueueHandle_t xInternalQueueHandle = NULL; + QueueHandle_t xExternalQueueHandle = NULL; + int32_t lIndex; + + lIndex = MPU_GetFreeIndexInKernelObjectPool(); + + if( lIndex != -1 ) + { + xInternalQueueHandle = xQueueCreateCountingSemaphore( uxCountValue, uxInitialCount ); + + if( xInternalQueueHandle != NULL ) + { + MPU_StoreQueueHandleAtIndex( lIndex, xInternalQueueHandle ); + xExternalQueueHandle = ( QueueHandle_t ) CONVERT_TO_EXTERNAL_INDEX( lIndex ); + } + else + { + MPU_SetIndexFreeInKernelObjectPool( lIndex ); + } + } + + return xExternalQueueHandle; + } + + #endif /* if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + + QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, + const UBaseType_t uxInitialCount, + StaticQueue_t * pxStaticQueue ) /* PRIVILEGED_FUNCTION */ + { + QueueHandle_t xInternalQueueHandle = NULL; + QueueHandle_t xExternalQueueHandle = NULL; + int32_t lIndex; + + lIndex = MPU_GetFreeIndexInKernelObjectPool(); + + if( lIndex != -1 ) + { + xInternalQueueHandle = xQueueCreateCountingSemaphoreStatic( uxMaxCount, uxInitialCount, pxStaticQueue ); + + if( xInternalQueueHandle != NULL ) + { + MPU_StoreQueueHandleAtIndex( lIndex, xInternalQueueHandle ); + xExternalQueueHandle = ( QueueHandle_t ) CONVERT_TO_EXTERNAL_INDEX( lIndex ); + } + else + { + MPU_SetIndexFreeInKernelObjectPool( lIndex ); + } + } + + return xExternalQueueHandle; + } + + #endif /* if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + QueueHandle_t MPU_xQueueGenericCreate( UBaseType_t uxQueueLength, + UBaseType_t uxItemSize, + uint8_t ucQueueType ) /* PRIVILEGED_FUNCTION */ + { + QueueHandle_t xInternalQueueHandle = NULL; + QueueHandle_t xExternalQueueHandle = NULL; + int32_t lIndex; + + lIndex = MPU_GetFreeIndexInKernelObjectPool(); + + if( lIndex != -1 ) + { + xInternalQueueHandle = xQueueGenericCreate( uxQueueLength, uxItemSize, ucQueueType ); + + if( xInternalQueueHandle != NULL ) + { + MPU_StoreQueueHandleAtIndex( lIndex, xInternalQueueHandle ); + xExternalQueueHandle = ( QueueHandle_t ) CONVERT_TO_EXTERNAL_INDEX( lIndex ); + } + else + { + MPU_SetIndexFreeInKernelObjectPool( lIndex ); + } + } + + return xExternalQueueHandle; + } + + #endif /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + + QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, + const UBaseType_t uxItemSize, + uint8_t * pucQueueStorage, + StaticQueue_t * pxStaticQueue, + const uint8_t ucQueueType ) /* PRIVILEGED_FUNCTION */ + { + QueueHandle_t xInternalQueueHandle = NULL; + QueueHandle_t xExternalQueueHandle = NULL; + int32_t lIndex; + + lIndex = MPU_GetFreeIndexInKernelObjectPool(); + + if( lIndex != -1 ) + { + xInternalQueueHandle = xQueueGenericCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxStaticQueue, ucQueueType ); + + if( xInternalQueueHandle != NULL ) + { + MPU_StoreQueueHandleAtIndex( lIndex, xInternalQueueHandle ); + xExternalQueueHandle = ( QueueHandle_t ) CONVERT_TO_EXTERNAL_INDEX( lIndex ); + } + else + { + MPU_SetIndexFreeInKernelObjectPool( lIndex ); + } + } + + return xExternalQueueHandle; + } + + #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue, + BaseType_t xNewQueue ) /* PRIVILEGED_FUNCTION */ + { + int32_t lIndex; + QueueHandle_t xInternalQueueHandle = NULL; + BaseType_t xReturn = pdFAIL; + + lIndex = ( int32_t ) xQueue; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalQueueHandle != NULL ) + { + xReturn = xQueueGenericReset( xInternalQueueHandle, xNewQueue ); + } + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + + QueueSetHandle_t MPU_xQueueCreateSet( UBaseType_t uxEventQueueLength ) /* PRIVILEGED_FUNCTION */ + { + QueueSetHandle_t xInternalQueueSetHandle = NULL; + QueueSetHandle_t xExternalQueueSetHandle = NULL; + int32_t lIndex; + + lIndex = MPU_GetFreeIndexInKernelObjectPool(); + + if( lIndex != -1 ) + { + xInternalQueueSetHandle = xQueueCreateSet( uxEventQueueLength ); + + if( xInternalQueueSetHandle != NULL ) + { + MPU_StoreQueueSetHandleAtIndex( lIndex, xInternalQueueSetHandle ); + xExternalQueueSetHandle = ( QueueSetHandle_t ) CONVERT_TO_EXTERNAL_INDEX( lIndex ); + } + else + { + MPU_SetIndexFreeInKernelObjectPool( lIndex ); + } + } + + return xExternalQueueSetHandle; + } + + #endif /* if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + + QueueSetHandle_t MPU_xQueueCreateSetStatic( const UBaseType_t uxEventQueueLength, + uint8_t * pucQueueStorage, + StaticQueue_t * pxStaticQueue ) /* PRIVILEGED_FUNCTION */ + { + QueueSetHandle_t xInternalQueueSetHandle = NULL; + QueueSetHandle_t xExternalQueueSetHandle = NULL; + int32_t lIndex; + + lIndex = MPU_GetFreeIndexInKernelObjectPool(); + + if( lIndex != -1 ) + { + xInternalQueueSetHandle = xQueueCreateSetStatic( uxEventQueueLength, pucQueueStorage, pxStaticQueue ); + + if( xInternalQueueSetHandle != NULL ) + { + MPU_StoreQueueSetHandleAtIndex( lIndex, xInternalQueueSetHandle ); + xExternalQueueSetHandle = ( QueueSetHandle_t ) CONVERT_TO_EXTERNAL_INDEX( lIndex ); + } + else + { + MPU_SetIndexFreeInKernelObjectPool( lIndex ); + } + } + + return xExternalQueueSetHandle; + } + + #endif /* if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xReturn = pdFAIL; + QueueSetMemberHandle_t xInternalQueueSetMemberHandle = NULL; + QueueSetHandle_t xInternalQueueSetHandle = NULL; + int32_t lIndexQueueSet, lIndexQueueSetMember; + + lIndexQueueSet = ( int32_t ) xQueueSet; + lIndexQueueSetMember = ( int32_t ) xQueueOrSemaphore; + + if( ( IS_EXTERNAL_INDEX_VALID( lIndexQueueSet ) != pdFALSE ) && + ( IS_EXTERNAL_INDEX_VALID( lIndexQueueSetMember ) != pdFALSE ) ) + { + xInternalQueueSetHandle = MPU_GetQueueSetHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndexQueueSet ) ); + xInternalQueueSetMemberHandle = MPU_GetQueueSetMemberHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndexQueueSetMember ) ); + + if( ( xInternalQueueSetHandle != NULL ) && ( xInternalQueueSetMemberHandle != NULL ) ) + { + xReturn = xQueueRemoveFromSet( xInternalQueueSetMemberHandle, xInternalQueueSetHandle ); + } + } + + return xReturn; + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + + BaseType_t MPU_xQueueGenericGetStaticBuffers( QueueHandle_t xQueue, + uint8_t ** ppucQueueStorage, + StaticQueue_t ** ppxStaticQueue ) /* PRIVILEGED_FUNCTION */ + { + int32_t lIndex; + QueueHandle_t xInternalQueueHandle = NULL; + BaseType_t xReturn = pdFALSE; + + lIndex = ( int32_t ) xQueue; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalQueueHandle != NULL ) + { + xReturn = xQueueGenericGetStaticBuffers( xInternalQueueHandle, ppucQueueStorage, ppxStaticQueue ); + } + } + + return xReturn; + } + + #endif /*if ( configSUPPORT_STATIC_ALLOCATION == 1 )*/ +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueGenericSendFromISR( QueueHandle_t xQueue, + const void * const pvItemToQueue, + BaseType_t * const pxHigherPriorityTaskWoken, + const BaseType_t xCopyPosition ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xReturn = pdFAIL; + int32_t lIndex; + QueueHandle_t xInternalQueueHandle = NULL; + + lIndex = ( int32_t ) xQueue; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalQueueHandle != NULL ) + { + xReturn = xQueueGenericSendFromISR( xInternalQueueHandle, pvItemToQueue, pxHigherPriorityTaskWoken, xCopyPosition ); + } + } + + return xReturn; + } + +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueGiveFromISR( QueueHandle_t xQueue, + BaseType_t * const pxHigherPriorityTaskWoken ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xReturn = pdFAIL; + int32_t lIndex; + QueueHandle_t xInternalQueueHandle = NULL; + + lIndex = ( int32_t ) xQueue; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalQueueHandle != NULL ) + { + xReturn = xQueueGiveFromISR( xInternalQueueHandle, pxHigherPriorityTaskWoken ); + } + } + + return xReturn; + } + +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueuePeekFromISR( QueueHandle_t xQueue, + void * const pvBuffer ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xReturn = pdFAIL; + int32_t lIndex; + QueueHandle_t xInternalQueueHandle = NULL; + + lIndex = ( int32_t ) xQueue; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalQueueHandle != NULL ) + { + xReturn = xQueuePeekFromISR( xInternalQueueHandle, pvBuffer ); + } + } + + return xReturn; + } + +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueReceiveFromISR( QueueHandle_t xQueue, + void * const pvBuffer, + BaseType_t * const pxHigherPriorityTaskWoken ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xReturn = pdFAIL; + int32_t lIndex; + QueueHandle_t xInternalQueueHandle = NULL; + + lIndex = ( int32_t ) xQueue; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalQueueHandle != NULL ) + { + xReturn = xQueueReceiveFromISR( xInternalQueueHandle, pvBuffer, pxHigherPriorityTaskWoken ); + } + } + + return xReturn; + } + +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xReturn = pdFAIL; + int32_t lIndex; + QueueHandle_t xInternalQueueHandle = NULL; + + lIndex = ( int32_t ) xQueue; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalQueueHandle != NULL ) + { + xReturn = xQueueIsQueueEmptyFromISR( xInternalQueueHandle ); + } + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xReturn = pdFAIL; + int32_t lIndex; + QueueHandle_t xInternalQueueHandle = NULL; + + lIndex = ( int32_t ) xQueue; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalQueueHandle != NULL ) + { + xReturn = xQueueIsQueueFullFromISR( xInternalQueueHandle ); + } + } + + return xReturn; + } + +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) /* PRIVILEGED_FUNCTION */ + { + UBaseType_t uxReturn = 0; + int32_t lIndex; + QueueHandle_t xInternalQueueHandle = NULL; + + lIndex = ( int32_t ) xQueue; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xInternalQueueHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalQueueHandle != NULL ) + { + uxReturn = uxQueueMessagesWaitingFromISR( xInternalQueueHandle ); + } + } + + return uxReturn; + } + +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) + + TaskHandle_t MPU_xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) /* PRIVILEGED_FUNCTION */ + { + TaskHandle_t xMutexHolderTaskInternalHandle = NULL; + TaskHandle_t xMutexHolderTaskExternalHandle = NULL; + int32_t lIndex, lMutexHolderTaskIndex; + QueueHandle_t xInternalSemaphoreHandle = NULL; + + lIndex = ( int32_t ) xSemaphore; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xInternalSemaphoreHandle = MPU_GetQueueHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalSemaphoreHandle != NULL ) + { + xMutexHolderTaskInternalHandle = xQueueGetMutexHolder( xInternalSemaphoreHandle ); + + if( xMutexHolderTaskInternalHandle != NULL ) + { + lMutexHolderTaskIndex = MPU_GetIndexForTaskHandle( xMutexHolderTaskInternalHandle ); + + if( lMutexHolderTaskIndex != -1 ) + { + xMutexHolderTaskExternalHandle = ( TaskHandle_t ) ( CONVERT_TO_EXTERNAL_INDEX( lMutexHolderTaskIndex ) ); + } + } + } + } + + return xMutexHolderTaskExternalHandle; + } + + #endif /* #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + QueueSetMemberHandle_t MPU_xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) /* PRIVILEGED_FUNCTION */ + { + QueueSetHandle_t xInternalQueueSetHandle = NULL; + QueueSetMemberHandle_t xSelectedMemberInternal = NULL; + QueueSetMemberHandle_t xSelectedMemberExternal = NULL; + int32_t lIndexQueueSet, lIndexSelectedMember; + + lIndexQueueSet = ( int32_t ) xQueueSet; + + if( IS_EXTERNAL_INDEX_VALID( lIndexQueueSet ) != pdFALSE ) + { + xInternalQueueSetHandle = MPU_GetQueueSetHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndexQueueSet ) ); + + if( xInternalQueueSetHandle != NULL ) + { + xSelectedMemberInternal = xQueueSelectFromSetFromISR( xInternalQueueSetHandle ); + + if( xSelectedMemberInternal != NULL ) + { + lIndexSelectedMember = MPU_GetIndexForQueueSetMemberHandle( xSelectedMemberInternal ); + + if( lIndexSelectedMember != -1 ) + { + xSelectedMemberExternal = ( QueueSetMemberHandle_t ) ( CONVERT_TO_EXTERNAL_INDEX( lIndexSelectedMember ) ); + } + } + } + } + + return xSelectedMemberExternal; + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + +/*-----------------------------------------------------------*/ +/* MPU wrappers for timers APIs. */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void * MPU_pvTimerGetTimerIDImpl( const TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; + + void * MPU_pvTimerGetTimerIDImpl( const TimerHandle_t xTimer ) /* PRIVILEGED_FUNCTION */ + { + void * pvReturn = NULL; + TimerHandle_t xInternalTimerHandle = NULL; + int32_t lIndex; + BaseType_t xCallingTaskIsAuthorizedToAccessTimer = pdFALSE; + + lIndex = ( int32_t ) xTimer; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessTimer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessTimer == pdTRUE ) + { + xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTimerHandle != NULL ) + { + pvReturn = pvTimerGetTimerID( xInternalTimerHandle ); + } + } + } + + return pvReturn; + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetTimerIDImpl( TimerHandle_t xTimer, + void * pvNewID ) PRIVILEGED_FUNCTION; + + void MPU_vTimerSetTimerIDImpl( TimerHandle_t xTimer, + void * pvNewID ) /* PRIVILEGED_FUNCTION */ + { + TimerHandle_t xInternalTimerHandle = NULL; + int32_t lIndex; + BaseType_t xCallingTaskIsAuthorizedToAccessTimer = pdFALSE; + + lIndex = ( int32_t ) xTimer; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessTimer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessTimer == pdTRUE ) + { + xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTimerHandle != NULL ) + { + vTimerSetTimerID( xInternalTimerHandle, pvNewID ); + } + } + } + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerIsTimerActiveImpl( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; + + BaseType_t MPU_xTimerIsTimerActiveImpl( TimerHandle_t xTimer ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xReturn = pdFALSE; + TimerHandle_t xInternalTimerHandle = NULL; + int32_t lIndex; + BaseType_t xCallingTaskIsAuthorizedToAccessTimer = pdFALSE; + + lIndex = ( int32_t ) xTimer; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessTimer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessTimer == pdTRUE ) + { + xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTimerHandle != NULL ) + { + xReturn = xTimerIsTimerActive( xInternalTimerHandle ); + } + } + } + + return xReturn; + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandleImpl( void ) PRIVILEGED_FUNCTION; + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandleImpl( void ) /* PRIVILEGED_FUNCTION */ + { + TaskHandle_t xReturn; + + xReturn = xTimerGetTimerDaemonTaskHandle(); + + return xReturn; + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer, + const BaseType_t xCommandID, + const TickType_t xOptionalValue, + BaseType_t * const pxHigherPriorityTaskWoken, + const TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ + { + BaseType_t xReturn = pdFALSE; + xTimerGenericCommandFromTaskParams_t xParams; + + xParams.xTimer = xTimer; + xParams.xCommandID = xCommandID; + xParams.xOptionalValue = xOptionalValue; + xParams.pxHigherPriorityTaskWoken = pxHigherPriorityTaskWoken; + xParams.xTicksToWait = xTicksToWait; + + xReturn = MPU_xTimerGenericCommandFromTaskEntry( &( xParams ) ); + + return xReturn; + } + + BaseType_t MPU_xTimerGenericCommandFromTaskImpl( const xTimerGenericCommandFromTaskParams_t * pxParams ) PRIVILEGED_FUNCTION; + + BaseType_t MPU_xTimerGenericCommandFromTaskImpl( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xReturn = pdFALSE; + TimerHandle_t xInternalTimerHandle = NULL; + int32_t lIndex; + BaseType_t xIsHigherPriorityTaskWokenWriteable = pdFALSE; + BaseType_t xCallingTaskIsAuthorizedToAccessTimer = pdFALSE; + BaseType_t xAreParamsReadable = pdFALSE; + + if( pxParams != NULL ) + { + xAreParamsReadable = xPortIsAuthorizedToAccessBuffer( pxParams, + sizeof( xTimerGenericCommandFromTaskParams_t ), + tskMPU_READ_PERMISSION ); + } + + if( xAreParamsReadable == pdTRUE ) + { + if( pxParams->xCommandID < tmrFIRST_FROM_ISR_COMMAND ) + { + if( pxParams->pxHigherPriorityTaskWoken != NULL ) + { + xIsHigherPriorityTaskWokenWriteable = xPortIsAuthorizedToAccessBuffer( pxParams->pxHigherPriorityTaskWoken, + sizeof( BaseType_t ), + tskMPU_WRITE_PERMISSION ); + } + + if( ( pxParams->pxHigherPriorityTaskWoken == NULL ) || + ( xIsHigherPriorityTaskWokenWriteable == pdTRUE ) ) + { + lIndex = ( int32_t ) ( pxParams->xTimer ); + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessTimer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessTimer == pdTRUE ) + { + xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTimerHandle != NULL ) + { + xReturn = xTimerGenericCommandFromTask( xInternalTimerHandle, + pxParams->xCommandID, + pxParams->xOptionalValue, + pxParams->pxHigherPriorityTaskWoken, + pxParams->xTicksToWait ); + } + } + } + } + } + } + + return xReturn; + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + const char * MPU_pcTimerGetNameImpl( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; + + const char * MPU_pcTimerGetNameImpl( TimerHandle_t xTimer ) /* PRIVILEGED_FUNCTION */ + { + const char * pcReturn = NULL; + TimerHandle_t xInternalTimerHandle = NULL; + int32_t lIndex; + BaseType_t xCallingTaskIsAuthorizedToAccessTimer = pdFALSE; + + lIndex = ( int32_t ) xTimer; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessTimer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessTimer == pdTRUE ) + { + xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTimerHandle != NULL ) + { + pcReturn = pcTimerGetName( xInternalTimerHandle ); + } + } + } + + return pcReturn; + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetReloadModeImpl( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) PRIVILEGED_FUNCTION; + + void MPU_vTimerSetReloadModeImpl( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) /* PRIVILEGED_FUNCTION */ + { + TimerHandle_t xInternalTimerHandle = NULL; + int32_t lIndex; + BaseType_t xCallingTaskIsAuthorizedToAccessTimer = pdFALSE; + + lIndex = ( int32_t ) xTimer; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessTimer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessTimer == pdTRUE ) + { + xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTimerHandle != NULL ) + { + vTimerSetReloadMode( xInternalTimerHandle, xAutoReload ); + } + } + } + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGetReloadModeImpl( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; + + BaseType_t MPU_xTimerGetReloadModeImpl( TimerHandle_t xTimer ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xReturn = pdFALSE; + TimerHandle_t xInternalTimerHandle = NULL; + int32_t lIndex; + BaseType_t xCallingTaskIsAuthorizedToAccessTimer = pdFALSE; + + lIndex = ( int32_t ) xTimer; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessTimer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessTimer == pdTRUE ) + { + xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTimerHandle != NULL ) + { + xReturn = xTimerGetReloadMode( xInternalTimerHandle ); + } + } + } + + return xReturn; + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + UBaseType_t MPU_uxTimerGetReloadModeImpl( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; + + UBaseType_t MPU_uxTimerGetReloadModeImpl( TimerHandle_t xTimer ) /* PRIVILEGED_FUNCTION */ + { + UBaseType_t uxReturn = 0; + TimerHandle_t xInternalTimerHandle = NULL; + int32_t lIndex; + BaseType_t xCallingTaskIsAuthorizedToAccessTimer = pdFALSE; + + lIndex = ( int32_t ) xTimer; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessTimer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessTimer == pdTRUE ) + { + xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTimerHandle != NULL ) + { + uxReturn = uxTimerGetReloadMode( xInternalTimerHandle ); + } + } + } + + return uxReturn; + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetPeriodImpl( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; + + TickType_t MPU_xTimerGetPeriodImpl( TimerHandle_t xTimer ) /* PRIVILEGED_FUNCTION */ + { + TickType_t xReturn = 0; + TimerHandle_t xInternalTimerHandle = NULL; + int32_t lIndex; + BaseType_t xCallingTaskIsAuthorizedToAccessTimer = pdFALSE; + + lIndex = ( int32_t ) xTimer; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessTimer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessTimer == pdTRUE ) + { + xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTimerHandle != NULL ) + { + xReturn = xTimerGetPeriod( xInternalTimerHandle ); + } + } + } + + return xReturn; + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetExpiryTimeImpl( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; + + TickType_t MPU_xTimerGetExpiryTimeImpl( TimerHandle_t xTimer ) /* PRIVILEGED_FUNCTION */ + { + TickType_t xReturn = 0; + TimerHandle_t xInternalTimerHandle = NULL; + int32_t lIndex; + BaseType_t xCallingTaskIsAuthorizedToAccessTimer = pdFALSE; + + lIndex = ( int32_t ) xTimer; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessTimer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessTimer == pdTRUE ) + { + xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTimerHandle != NULL ) + { + xReturn = xTimerGetExpiryTime( xInternalTimerHandle ); + } + } + } + + return xReturn; + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + +/* Privileged only wrappers for Timer APIs. These are needed so that + * the application can use opaque handles maintained in mpu_wrappers.c + * with all the APIs. */ +/*-----------------------------------------------------------*/ + + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_TIMERS == 1 ) + + TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, + const TickType_t xTimerPeriodInTicks, + const BaseType_t xAutoReload, + void * const pvTimerID, + TimerCallbackFunction_t pxCallbackFunction ) /* PRIVILEGED_FUNCTION */ + { + TimerHandle_t xInternalTimerHandle = NULL; + TimerHandle_t xExternalTimerHandle = NULL; + int32_t lIndex; + + lIndex = MPU_GetFreeIndexInKernelObjectPool(); + + if( lIndex != -1 ) + { + xInternalTimerHandle = xTimerCreate( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, MPU_TimerCallback ); + + if( xInternalTimerHandle != NULL ) + { + MPU_StoreTimerHandleAtIndex( lIndex, xInternalTimerHandle, pxCallbackFunction ); + xExternalTimerHandle = ( TimerHandle_t ) CONVERT_TO_EXTERNAL_INDEX( lIndex ); + } + else + { + MPU_SetIndexFreeInKernelObjectPool( lIndex ); + } + } + + return xExternalTimerHandle; + } + + #endif /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_TIMERS == 1 ) + + TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, + const TickType_t xTimerPeriodInTicks, + const BaseType_t xAutoReload, + void * const pvTimerID, + TimerCallbackFunction_t pxCallbackFunction, + StaticTimer_t * pxTimerBuffer ) /* PRIVILEGED_FUNCTION */ + { + TimerHandle_t xInternalTimerHandle = NULL; + TimerHandle_t xExternalTimerHandle = NULL; + int32_t lIndex; + + lIndex = MPU_GetFreeIndexInKernelObjectPool(); + + if( lIndex != -1 ) + { + xInternalTimerHandle = xTimerCreateStatic( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, MPU_TimerCallback, pxTimerBuffer ); + + if( xInternalTimerHandle != NULL ) + { + MPU_StoreTimerHandleAtIndex( lIndex, xInternalTimerHandle, pxCallbackFunction ); + xExternalTimerHandle = ( TimerHandle_t ) CONVERT_TO_EXTERNAL_INDEX( lIndex ); + } + else + { + MPU_SetIndexFreeInKernelObjectPool( lIndex ); + } + } + + return xExternalTimerHandle; + } + + #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGetStaticBuffer( TimerHandle_t xTimer, + StaticTimer_t ** ppxTimerBuffer ) /* PRIVILEGED_FUNCTION */ + { + TimerHandle_t xInternalTimerHandle = NULL; + int32_t lIndex; + BaseType_t xReturn = pdFALSE; + + lIndex = ( int32_t ) xTimer; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTimerHandle != NULL ) + { + xReturn = xTimerGetStaticBuffer( xInternalTimerHandle, ppxTimerBuffer ); + } + } + + return xReturn; + } + + #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGenericCommandFromISR( TimerHandle_t xTimer, + const BaseType_t xCommandID, + const TickType_t xOptionalValue, + BaseType_t * const pxHigherPriorityTaskWoken, + const TickType_t xTicksToWait ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xReturn = pdFALSE; + TimerHandle_t xInternalTimerHandle = NULL; + int32_t lIndex; + + lIndex = ( int32_t ) xTimer; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xInternalTimerHandle = MPU_GetTimerHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalTimerHandle != NULL ) + { + xReturn = xTimerGenericCommandFromISR( xInternalTimerHandle, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait ); + } + } + + return xReturn; + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + +/*-----------------------------------------------------------*/ +/* MPU wrappers for event group APIs. */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToWaitFor, + const BaseType_t xClearOnExit, + const BaseType_t xWaitForAllBits, + TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ + { + EventBits_t xReturn = 0; + xEventGroupWaitBitsParams_t xParams; + + xParams.xEventGroup = xEventGroup; + xParams.uxBitsToWaitFor = uxBitsToWaitFor; + xParams.xClearOnExit = xClearOnExit; + xParams.xWaitForAllBits = xWaitForAllBits; + xParams.xTicksToWait = xTicksToWait; + + xReturn = MPU_xEventGroupWaitBitsEntry( &( xParams ) ); + + return xReturn; + } + + EventBits_t MPU_xEventGroupWaitBitsImpl( const xEventGroupWaitBitsParams_t * pxParams ) PRIVILEGED_FUNCTION; + + EventBits_t MPU_xEventGroupWaitBitsImpl( const xEventGroupWaitBitsParams_t * pxParams ) /* PRIVILEGED_FUNCTION */ + { + EventBits_t xReturn = 0; + EventGroupHandle_t xInternalEventGroupHandle = NULL; + int32_t lIndex; + BaseType_t xCallingTaskIsAuthorizedToAccessEventGroup = pdFALSE; + BaseType_t xAreParamsReadable = pdFALSE; + + if( pxParams != NULL ) + { + xAreParamsReadable = xPortIsAuthorizedToAccessBuffer( pxParams, + sizeof( xEventGroupWaitBitsParams_t ), + tskMPU_READ_PERMISSION ); + } + + if( xAreParamsReadable == pdTRUE ) + { + if( ( ( pxParams->uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0U ) && + ( pxParams->uxBitsToWaitFor != 0U ) + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( pxParams->xTicksToWait != 0U ) ) ) + #endif + ) + { + lIndex = ( int32_t ) ( pxParams->xEventGroup ); + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessEventGroup = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessEventGroup == pdTRUE ) + { + xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalEventGroupHandle != NULL ) + { + xReturn = xEventGroupWaitBits( xInternalEventGroupHandle, + pxParams->uxBitsToWaitFor, + pxParams->xClearOnExit, + pxParams->xWaitForAllBits, + pxParams->xTicksToWait ); + } + } + } + } + } + + return xReturn; + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupClearBitsImpl( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION; + + EventBits_t MPU_xEventGroupClearBitsImpl( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) /* PRIVILEGED_FUNCTION */ + { + EventBits_t xReturn = 0; + EventGroupHandle_t xInternalEventGroupHandle = NULL; + int32_t lIndex; + BaseType_t xCallingTaskIsAuthorizedToAccessEventGroup = pdFALSE; + + if( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0U ) + { + lIndex = ( int32_t ) xEventGroup; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessEventGroup = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessEventGroup == pdTRUE ) + { + xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalEventGroupHandle != NULL ) + { + xReturn = xEventGroupClearBits( xInternalEventGroupHandle, uxBitsToClear ); + } + } + } + } + + return xReturn; + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupSetBitsImpl( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION; + + EventBits_t MPU_xEventGroupSetBitsImpl( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) /* PRIVILEGED_FUNCTION */ + { + EventBits_t xReturn = 0; + EventGroupHandle_t xInternalEventGroupHandle = NULL; + int32_t lIndex; + BaseType_t xCallingTaskIsAuthorizedToAccessEventGroup = pdFALSE; + + if( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0U ) + { + lIndex = ( int32_t ) xEventGroup; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessEventGroup = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessEventGroup == pdTRUE ) + { + xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalEventGroupHandle != NULL ) + { + xReturn = xEventGroupSetBits( xInternalEventGroupHandle, uxBitsToSet ); + } + } + } + } + + return xReturn; + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupSyncImpl( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + + EventBits_t MPU_xEventGroupSyncImpl( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) /* PRIVILEGED_FUNCTION */ + { + EventBits_t xReturn = 0; + EventGroupHandle_t xInternalEventGroupHandle = NULL; + int32_t lIndex; + BaseType_t xCallingTaskIsAuthorizedToAccessEventGroup = pdFALSE; + + if( ( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0U ) && + ( uxBitsToWaitFor != 0U ) + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + && ( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0U ) ) ) + #endif + ) + { + lIndex = ( int32_t ) xEventGroup; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessEventGroup = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessEventGroup == pdTRUE ) + { + xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalEventGroupHandle != NULL ) + { + xReturn = xEventGroupSync( xInternalEventGroupHandle, uxBitsToSet, uxBitsToWaitFor, xTicksToWait ); + } + } + } + } + + return xReturn; + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + UBaseType_t MPU_uxEventGroupGetNumberImpl( void * xEventGroup ) PRIVILEGED_FUNCTION; + + UBaseType_t MPU_uxEventGroupGetNumberImpl( void * xEventGroup ) /* PRIVILEGED_FUNCTION */ + { + UBaseType_t xReturn = 0; + EventGroupHandle_t xInternalEventGroupHandle = NULL; + int32_t lIndex; + BaseType_t xCallingTaskIsAuthorizedToAccessEventGroup = pdFALSE; + + lIndex = ( int32_t ) xEventGroup; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessEventGroup = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessEventGroup == pdTRUE ) + { + xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalEventGroupHandle != NULL ) + { + xReturn = uxEventGroupGetNumber( xInternalEventGroupHandle ); + } + } + } + + return xReturn; + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + void MPU_vEventGroupSetNumberImpl( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) PRIVILEGED_FUNCTION; + + void MPU_vEventGroupSetNumberImpl( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) /* PRIVILEGED_FUNCTION */ + { + EventGroupHandle_t xInternalEventGroupHandle = NULL; + int32_t lIndex; + BaseType_t xCallingTaskIsAuthorizedToAccessEventGroup = pdFALSE; + + lIndex = ( int32_t ) xEventGroup; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessEventGroup = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessEventGroup == pdTRUE ) + { + xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalEventGroupHandle != NULL ) + { + vEventGroupSetNumber( xInternalEventGroupHandle, uxEventGroupNumber ); + } + } + } + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + +/* Privileged only wrappers for Event Group APIs. These are needed so that + * the application can use opaque handles maintained in mpu_wrappers.c + * with all the APIs. */ +/*-----------------------------------------------------------*/ + + #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_EVENT_GROUPS == 1 ) ) + + EventGroupHandle_t MPU_xEventGroupCreate( void ) /* PRIVILEGED_FUNCTION */ + { + EventGroupHandle_t xInternalEventGroupHandle = NULL; + EventGroupHandle_t xExternalEventGroupHandle = NULL; + int32_t lIndex; + + lIndex = MPU_GetFreeIndexInKernelObjectPool(); + + if( lIndex != -1 ) + { + xInternalEventGroupHandle = xEventGroupCreate(); + + if( xInternalEventGroupHandle != NULL ) + { + MPU_StoreEventGroupHandleAtIndex( lIndex, xInternalEventGroupHandle ); + xExternalEventGroupHandle = ( EventGroupHandle_t ) CONVERT_TO_EXTERNAL_INDEX( lIndex ); + } + else + { + MPU_SetIndexFreeInKernelObjectPool( lIndex ); + } + } + + return xExternalEventGroupHandle; + } + + #endif /* #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_EVENT_GROUPS == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_EVENT_GROUPS == 1 ) ) + + EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) /* PRIVILEGED_FUNCTION */ + { + EventGroupHandle_t xInternalEventGroupHandle = NULL; + EventGroupHandle_t xExternalEventGroupHandle = NULL; + int32_t lIndex; + + lIndex = MPU_GetFreeIndexInKernelObjectPool(); + + if( lIndex != -1 ) + { + xInternalEventGroupHandle = xEventGroupCreateStatic( pxEventGroupBuffer ); + + if( xInternalEventGroupHandle != NULL ) + { + MPU_StoreEventGroupHandleAtIndex( lIndex, xInternalEventGroupHandle ); + xExternalEventGroupHandle = ( EventGroupHandle_t ) CONVERT_TO_EXTERNAL_INDEX( lIndex ); + } + else + { + MPU_SetIndexFreeInKernelObjectPool( lIndex ); + } + } + + return xExternalEventGroupHandle; + } + + #endif /* #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_EVENT_GROUPS == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) /* PRIVILEGED_FUNCTION */ + { + EventGroupHandle_t xInternalEventGroupHandle = NULL; + int32_t lIndex; + + lIndex = ( int32_t ) xEventGroup; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalEventGroupHandle != NULL ) + { + vEventGroupDelete( xInternalEventGroupHandle ); + MPU_SetIndexFreeInKernelObjectPool( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + } + } + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_EVENT_GROUPS == 1 ) ) + + BaseType_t MPU_xEventGroupGetStaticBuffer( EventGroupHandle_t xEventGroup, + StaticEventGroup_t ** ppxEventGroupBuffer ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xReturn = pdFALSE; + EventGroupHandle_t xInternalEventGroupHandle = NULL; + int32_t lIndex; + + lIndex = ( int32_t ) xEventGroup; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalEventGroupHandle != NULL ) + { + xReturn = xEventGroupGetStaticBuffer( xInternalEventGroupHandle, ppxEventGroupBuffer ); + } + } + + return xReturn; + } + + #endif /* #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_EVENT_GROUPS == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) + + BaseType_t MPU_xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xReturn = pdFALSE; + EventGroupHandle_t xInternalEventGroupHandle = NULL; + int32_t lIndex; + + lIndex = ( int32_t ) xEventGroup; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalEventGroupHandle != NULL ) + { + xReturn = xEventGroupClearBitsFromISR( xInternalEventGroupHandle, uxBitsToClear ); + } + } + + return xReturn; + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) + + BaseType_t MPU_xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + BaseType_t * pxHigherPriorityTaskWoken ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xReturn = pdFALSE; + EventGroupHandle_t xInternalEventGroupHandle = NULL; + int32_t lIndex; + + lIndex = ( int32_t ) xEventGroup; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalEventGroupHandle != NULL ) + { + xReturn = xEventGroupSetBitsFromISR( xInternalEventGroupHandle, uxBitsToSet, pxHigherPriorityTaskWoken ); + } + } + + return xReturn; + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) /* PRIVILEGED_FUNCTION */ + { + EventBits_t xReturn = 0; + EventGroupHandle_t xInternalEventGroupHandle = NULL; + int32_t lIndex; + + lIndex = ( int32_t ) xEventGroup; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xInternalEventGroupHandle = MPU_GetEventGroupHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalEventGroupHandle != NULL ) + { + xReturn = xEventGroupGetBitsFromISR( xInternalEventGroupHandle ); + } + } + + return xReturn; + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + +/*-----------------------------------------------------------*/ +/* MPU wrappers for stream buffer APIs. */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferSendImpl( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + + size_t MPU_xStreamBufferSendImpl( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) /* PRIVILEGED_FUNCTION */ + { + size_t xReturn = 0; + StreamBufferHandle_t xInternalStreamBufferHandle = NULL; + int32_t lIndex; + BaseType_t xIsTxDataBufferReadable = pdFALSE; + BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE; + + if( pvTxData != NULL ) + { + xIsTxDataBufferReadable = xPortIsAuthorizedToAccessBuffer( pvTxData, + xDataLengthBytes, + tskMPU_READ_PERMISSION ); + + if( xIsTxDataBufferReadable == pdTRUE ) + { + lIndex = ( int32_t ) xStreamBuffer; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE ) + { + xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalStreamBufferHandle != NULL ) + { + xReturn = xStreamBufferSend( xInternalStreamBufferHandle, pvTxData, xDataLengthBytes, xTicksToWait ); + } + } + } + } + } + + return xReturn; + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferReceiveImpl( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + + size_t MPU_xStreamBufferReceiveImpl( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) /* PRIVILEGED_FUNCTION */ + { + size_t xReturn = 0; + StreamBufferHandle_t xInternalStreamBufferHandle = NULL; + int32_t lIndex; + BaseType_t xIsRxDataBufferWriteable = pdFALSE; + BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE; + + if( pvRxData != NULL ) + { + xIsRxDataBufferWriteable = xPortIsAuthorizedToAccessBuffer( pvRxData, + xBufferLengthBytes, + tskMPU_WRITE_PERMISSION ); + + if( xIsRxDataBufferWriteable == pdTRUE ) + { + lIndex = ( int32_t ) xStreamBuffer; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE ) + { + xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalStreamBufferHandle != NULL ) + { + xReturn = xStreamBufferReceive( xInternalStreamBufferHandle, pvRxData, xBufferLengthBytes, xTicksToWait ); + } + } + } + } + } + + return xReturn; + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferIsFullImpl( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + + BaseType_t MPU_xStreamBufferIsFullImpl( StreamBufferHandle_t xStreamBuffer ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xReturn = pdFALSE; + StreamBufferHandle_t xInternalStreamBufferHandle = NULL; + int32_t lIndex; + BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE; + + lIndex = ( int32_t ) xStreamBuffer; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE ) + { + xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalStreamBufferHandle != NULL ) + { + xReturn = xStreamBufferIsFull( xInternalStreamBufferHandle ); + } + } + } + + return xReturn; + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferIsEmptyImpl( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + + BaseType_t MPU_xStreamBufferIsEmptyImpl( StreamBufferHandle_t xStreamBuffer ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xReturn = pdFALSE; + StreamBufferHandle_t xInternalStreamBufferHandle = NULL; + int32_t lIndex; + BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE; + + lIndex = ( int32_t ) xStreamBuffer; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE ) + { + xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalStreamBufferHandle != NULL ) + { + xReturn = xStreamBufferIsEmpty( xInternalStreamBufferHandle ); + } + } + } + + return xReturn; + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferSpacesAvailableImpl( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + + size_t MPU_xStreamBufferSpacesAvailableImpl( StreamBufferHandle_t xStreamBuffer ) /* PRIVILEGED_FUNCTION */ + { + size_t xReturn = 0; + StreamBufferHandle_t xInternalStreamBufferHandle = NULL; + int32_t lIndex; + BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE; + + lIndex = ( int32_t ) xStreamBuffer; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE ) + { + xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalStreamBufferHandle != NULL ) + { + xReturn = xStreamBufferSpacesAvailable( xInternalStreamBufferHandle ); + } + } + } + + return xReturn; + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferBytesAvailableImpl( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + + size_t MPU_xStreamBufferBytesAvailableImpl( StreamBufferHandle_t xStreamBuffer ) /* PRIVILEGED_FUNCTION */ + { + size_t xReturn = 0; + StreamBufferHandle_t xInternalStreamBufferHandle = NULL; + int32_t lIndex; + BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE; + + lIndex = ( int32_t ) xStreamBuffer; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE ) + { + xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalStreamBufferHandle != NULL ) + { + xReturn = xStreamBufferBytesAvailable( xInternalStreamBufferHandle ); + } + } + } + + return xReturn; + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferSetTriggerLevelImpl( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) PRIVILEGED_FUNCTION; + + BaseType_t MPU_xStreamBufferSetTriggerLevelImpl( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xReturn = pdFALSE; + StreamBufferHandle_t xInternalStreamBufferHandle = NULL; + int32_t lIndex; + BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE; + + lIndex = ( int32_t ) xStreamBuffer; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE ) + { + xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalStreamBufferHandle != NULL ) + { + xReturn = xStreamBufferSetTriggerLevel( xInternalStreamBufferHandle, xTriggerLevel ); + } + } + } + + return xReturn; + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferNextMessageLengthBytesImpl( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + + size_t MPU_xStreamBufferNextMessageLengthBytesImpl( StreamBufferHandle_t xStreamBuffer ) /* PRIVILEGED_FUNCTION */ + { + size_t xReturn = 0; + StreamBufferHandle_t xInternalStreamBufferHandle = NULL; + int32_t lIndex; + BaseType_t xCallingTaskIsAuthorizedToAccessStreamBuffer = pdFALSE; + + lIndex = ( int32_t ) xStreamBuffer; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xCallingTaskIsAuthorizedToAccessStreamBuffer = xPortIsAuthorizedToAccessKernelObject( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xCallingTaskIsAuthorizedToAccessStreamBuffer == pdTRUE ) + { + xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalStreamBufferHandle != NULL ) + { + xReturn = xStreamBufferNextMessageLengthBytes( xInternalStreamBufferHandle ); + } + } + } + + return xReturn; + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + +/* Privileged only wrappers for Stream Buffer APIs. These are needed so that + * the application can use opaque handles maintained in mpu_wrappers.c + * with all the APIs. */ +/*-----------------------------------------------------------*/ + + #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_STREAM_BUFFERS == 1 ) ) + + StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + BaseType_t xStreamBufferType, + StreamBufferCallbackFunction_t pxSendCompletedCallback, + StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) /* PRIVILEGED_FUNCTION */ + { + StreamBufferHandle_t xInternalStreamBufferHandle = NULL; + StreamBufferHandle_t xExternalStreamBufferHandle = NULL; + int32_t lIndex; + + /** + * Stream buffer application level callback functionality is disabled for MPU + * enabled ports. + */ + configASSERT( ( pxSendCompletedCallback == NULL ) && + ( pxReceiveCompletedCallback == NULL ) ); + + if( ( pxSendCompletedCallback == NULL ) && + ( pxReceiveCompletedCallback == NULL ) ) + { + lIndex = MPU_GetFreeIndexInKernelObjectPool(); + + if( lIndex != -1 ) + { + xInternalStreamBufferHandle = xStreamBufferGenericCreate( xBufferSizeBytes, + xTriggerLevelBytes, + xStreamBufferType, + NULL, + NULL ); + + if( xInternalStreamBufferHandle != NULL ) + { + MPU_StoreStreamBufferHandleAtIndex( lIndex, xInternalStreamBufferHandle ); + xExternalStreamBufferHandle = ( StreamBufferHandle_t ) CONVERT_TO_EXTERNAL_INDEX( lIndex ); + } + else + { + MPU_SetIndexFreeInKernelObjectPool( lIndex ); + } + } + } + else + { + traceSTREAM_BUFFER_CREATE_FAILED( xStreamBufferType ); + xExternalStreamBufferHandle = NULL; + } + + return xExternalStreamBufferHandle; + } + + #endif /* #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_STREAM_BUFFERS == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_STREAM_BUFFERS == 1 ) ) + + StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + BaseType_t xStreamBufferType, + uint8_t * const pucStreamBufferStorageArea, + StaticStreamBuffer_t * const pxStaticStreamBuffer, + StreamBufferCallbackFunction_t pxSendCompletedCallback, + StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) /* PRIVILEGED_FUNCTION */ + { + StreamBufferHandle_t xInternalStreamBufferHandle = NULL; + StreamBufferHandle_t xExternalStreamBufferHandle = NULL; + int32_t lIndex; + + /** + * Stream buffer application level callback functionality is disabled for MPU + * enabled ports. + */ + configASSERT( ( pxSendCompletedCallback == NULL ) && + ( pxReceiveCompletedCallback == NULL ) ); + + if( ( pxSendCompletedCallback == NULL ) && + ( pxReceiveCompletedCallback == NULL ) ) + { + lIndex = MPU_GetFreeIndexInKernelObjectPool(); + + if( lIndex != -1 ) + { + xInternalStreamBufferHandle = xStreamBufferGenericCreateStatic( xBufferSizeBytes, + xTriggerLevelBytes, + xStreamBufferType, + pucStreamBufferStorageArea, + pxStaticStreamBuffer, + NULL, + NULL ); + + if( xInternalStreamBufferHandle != NULL ) + { + MPU_StoreStreamBufferHandleAtIndex( lIndex, xInternalStreamBufferHandle ); + xExternalStreamBufferHandle = ( StreamBufferHandle_t ) CONVERT_TO_EXTERNAL_INDEX( lIndex ); + } + else + { + MPU_SetIndexFreeInKernelObjectPool( lIndex ); + } + } + } + else + { + traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xStreamBufferType ); + xExternalStreamBufferHandle = NULL; + } + + return xExternalStreamBufferHandle; + } + + #endif /* #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_STREAM_BUFFERS == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) /* PRIVILEGED_FUNCTION */ + { + StreamBufferHandle_t xInternalStreamBufferHandle = NULL; + int32_t lIndex; + + lIndex = ( int32_t ) xStreamBuffer; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalStreamBufferHandle != NULL ) + { + vStreamBufferDelete( xInternalStreamBufferHandle ); + } + + MPU_SetIndexFreeInKernelObjectPool( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + } + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xReturn = pdFALSE; + StreamBufferHandle_t xInternalStreamBufferHandle = NULL; + int32_t lIndex; + + lIndex = ( int32_t ) xStreamBuffer; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalStreamBufferHandle != NULL ) + { + xReturn = xStreamBufferReset( xInternalStreamBufferHandle ); + } + } + + return xReturn; + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_STREAM_BUFFERS == 1 ) ) + + BaseType_t MPU_xStreamBufferGetStaticBuffers( StreamBufferHandle_t xStreamBuffers, + uint8_t * ppucStreamBufferStorageArea, + StaticStreamBuffer_t * ppxStaticStreamBuffer ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xReturn = pdFALSE; + StreamBufferHandle_t xInternalStreamBufferHandle = NULL; + int32_t lIndex; + + lIndex = ( int32_t ) xStreamBuffers; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalStreamBufferHandle != NULL ) + { + xReturn = MPU_xStreamBufferGetStaticBuffers( xInternalStreamBufferHandle, ppucStreamBufferStorageArea, ppxStaticStreamBuffer ); + } + } + + return xReturn; + } + + #endif /* #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_STREAM_BUFFERS == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + BaseType_t * const pxHigherPriorityTaskWoken ) /* PRIVILEGED_FUNCTION */ + { + size_t xReturn = 0; + StreamBufferHandle_t xInternalStreamBufferHandle = NULL; + int32_t lIndex; + + lIndex = ( int32_t ) xStreamBuffer; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalStreamBufferHandle != NULL ) + { + xReturn = xStreamBufferSendFromISR( xInternalStreamBufferHandle, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken ); + } + } + + return xReturn; + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + BaseType_t * const pxHigherPriorityTaskWoken ) /* PRIVILEGED_FUNCTION */ + { + size_t xReturn = 0; + StreamBufferHandle_t xInternalStreamBufferHandle = NULL; + int32_t lIndex; + + lIndex = ( int32_t ) xStreamBuffer; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalStreamBufferHandle != NULL ) + { + xReturn = xStreamBufferReceiveFromISR( xInternalStreamBufferHandle, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken ); + } + } + + return xReturn; + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, + BaseType_t * pxHigherPriorityTaskWoken ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xReturn = pdFALSE; + StreamBufferHandle_t xInternalStreamBufferHandle = NULL; + int32_t lIndex; + + lIndex = ( int32_t ) xStreamBuffer; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalStreamBufferHandle != NULL ) + { + xReturn = xStreamBufferSendCompletedFromISR( xInternalStreamBufferHandle, pxHigherPriorityTaskWoken ); + } + } + + return xReturn; + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, + BaseType_t * pxHigherPriorityTaskWoken ) /*PRIVILEGED_FUNCTION */ + { + BaseType_t xReturn = pdFALSE; + StreamBufferHandle_t xInternalStreamBufferHandle = NULL; + int32_t lIndex; + + lIndex = ( int32_t ) xStreamBuffer; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalStreamBufferHandle != NULL ) + { + xReturn = xStreamBufferReceiveCompletedFromISR( xInternalStreamBufferHandle, pxHigherPriorityTaskWoken ); + } + } + + return xReturn; + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ + +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferResetFromISR( StreamBufferHandle_t xStreamBuffer ) /*PRIVILEGED_FUNCTION */ + { + BaseType_t xReturn = pdFAIL; + StreamBufferHandle_t xInternalStreamBufferHandle = NULL; + int32_t lIndex; + + lIndex = ( int32_t ) xStreamBuffer; + + if( IS_EXTERNAL_INDEX_VALID( lIndex ) != pdFALSE ) + { + xInternalStreamBufferHandle = MPU_GetStreamBufferHandleAtIndex( CONVERT_TO_INTERNAL_INDEX( lIndex ) ); + + if( xInternalStreamBufferHandle != NULL ) + { + xReturn = xStreamBufferResetFromISR( xInternalStreamBufferHandle ); + } + } + + return xReturn; + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ + +/*-----------------------------------------------------------*/ + +/* Functions that the application writer wants to execute in privileged mode + * can be defined in application_defined_privileged_functions.h. */ + + #if configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS == 1 + #include "application_defined_privileged_functions.h" + #endif +/*-----------------------------------------------------------*/ + +/** + * @brief Array of system call implementation functions. + * + * The index in the array MUST match the corresponding system call number + * defined in mpu_wrappers.h. + */ + PRIVILEGED_DATA UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ] = + { + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + ( UBaseType_t ) MPU_xTaskGenericNotifyImpl, /* SYSTEM_CALL_xTaskGenericNotify. */ + ( UBaseType_t ) MPU_xTaskGenericNotifyWaitImpl, /* SYSTEM_CALL_xTaskGenericNotifyWait. */ + #else + ( UBaseType_t ) 0, /* SYSTEM_CALL_xTaskGenericNotify. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_xTaskGenericNotifyWait. */ + #endif + + #if ( configUSE_TIMERS == 1 ) + ( UBaseType_t ) MPU_xTimerGenericCommandFromTaskImpl, /* SYSTEM_CALL_xTimerGenericCommandFromTask. */ + #else + ( UBaseType_t ) 0, /* SYSTEM_CALL_xTimerGenericCommandFromTask. */ + #endif + + #if ( configUSE_EVENT_GROUPS == 1 ) + ( UBaseType_t ) MPU_xEventGroupWaitBitsImpl, /* SYSTEM_CALL_xEventGroupWaitBits. */ + #else + ( UBaseType_t ) 0, /* SYSTEM_CALL_xEventGroupWaitBits. */ + #endif + + /* The system calls above this line take 5 parameters. */ + + #if ( INCLUDE_xTaskDelayUntil == 1 ) + ( UBaseType_t ) MPU_xTaskDelayUntilImpl, /* SYSTEM_CALL_xTaskDelayUntil. */ + #else + ( UBaseType_t ) 0, /* SYSTEM_CALL_xTaskDelayUntil. */ + #endif + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + ( UBaseType_t ) MPU_xTaskAbortDelayImpl, /* SYSTEM_CALL_xTaskAbortDelay. */ + #else + ( UBaseType_t ) 0, /* SYSTEM_CALL_xTaskAbortDelay. */ + #endif + + #if ( INCLUDE_vTaskDelay == 1 ) + ( UBaseType_t ) MPU_vTaskDelayImpl, /* SYSTEM_CALL_vTaskDelay. */ + #else + ( UBaseType_t ) 0, /* SYSTEM_CALL_vTaskDelay. */ + #endif + + #if ( INCLUDE_uxTaskPriorityGet == 1 ) + ( UBaseType_t ) MPU_uxTaskPriorityGetImpl, /* SYSTEM_CALL_uxTaskPriorityGet. */ + #else + ( UBaseType_t ) 0, /* SYSTEM_CALL_uxTaskPriorityGet. */ + #endif + + #if ( INCLUDE_eTaskGetState == 1 ) + ( UBaseType_t ) MPU_eTaskGetStateImpl, /* SYSTEM_CALL_eTaskGetState. */ + #else + ( UBaseType_t ) 0, /* SYSTEM_CALL_eTaskGetState. */ + #endif + + #if ( configUSE_TRACE_FACILITY == 1 ) + ( UBaseType_t ) MPU_vTaskGetInfoImpl, /* SYSTEM_CALL_vTaskGetInfo. */ + #else + ( UBaseType_t ) 0, /* SYSTEM_CALL_vTaskGetInfo. */ + #endif + + #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) + ( UBaseType_t ) MPU_xTaskGetIdleTaskHandleImpl, /* SYSTEM_CALL_xTaskGetIdleTaskHandle. */ + #else + ( UBaseType_t ) 0, /* SYSTEM_CALL_xTaskGetIdleTaskHandle. */ + #endif + + #if ( INCLUDE_vTaskSuspend == 1 ) + ( UBaseType_t ) MPU_vTaskSuspendImpl, /* SYSTEM_CALL_vTaskSuspend. */ + ( UBaseType_t ) MPU_vTaskResumeImpl, /* SYSTEM_CALL_vTaskResume. */ + #else + ( UBaseType_t ) 0, /* SYSTEM_CALL_vTaskSuspend. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_vTaskResume. */ + #endif + + ( UBaseType_t ) MPU_xTaskGetTickCountImpl, /* SYSTEM_CALL_xTaskGetTickCount. */ + ( UBaseType_t ) MPU_uxTaskGetNumberOfTasksImpl, /* SYSTEM_CALL_uxTaskGetNumberOfTasks. */ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + ( UBaseType_t ) MPU_ulTaskGetRunTimeCounterImpl, /* SYSTEM_CALL_ulTaskGetRunTimeCounter. */ + ( UBaseType_t ) MPU_ulTaskGetRunTimePercentImpl, /* SYSTEM_CALL_ulTaskGetRunTimePercent. */ + #else + ( UBaseType_t ) 0, /* SYSTEM_CALL_ulTaskGetRunTimeCounter. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_ulTaskGetRunTimePercent. */ + #endif + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + ( UBaseType_t ) MPU_ulTaskGetIdleRunTimePercentImpl, /* SYSTEM_CALL_ulTaskGetIdleRunTimePercent. */ + ( UBaseType_t ) MPU_ulTaskGetIdleRunTimeCounterImpl, /* SYSTEM_CALL_ulTaskGetIdleRunTimeCounter. */ + #else + ( UBaseType_t ) 0, /* SYSTEM_CALL_ulTaskGetIdleRunTimePercent. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_ulTaskGetIdleRunTimeCounter. */ + #endif + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + ( UBaseType_t ) MPU_vTaskSetApplicationTaskTagImpl, /* SYSTEM_CALL_vTaskSetApplicationTaskTag. */ + ( UBaseType_t ) MPU_xTaskGetApplicationTaskTagImpl, /* SYSTEM_CALL_xTaskGetApplicationTaskTag. */ + #else + ( UBaseType_t ) 0, /* SYSTEM_CALL_vTaskSetApplicationTaskTag. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_xTaskGetApplicationTaskTag. */ + #endif + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + ( UBaseType_t ) MPU_vTaskSetThreadLocalStoragePointerImpl, /* SYSTEM_CALL_vTaskSetThreadLocalStoragePointer. */ + ( UBaseType_t ) MPU_pvTaskGetThreadLocalStoragePointerImpl, /* SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer. */ + #else + ( UBaseType_t ) 0, /* SYSTEM_CALL_vTaskSetThreadLocalStoragePointer. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer. */ + #endif + + #if ( configUSE_TRACE_FACILITY == 1 ) + ( UBaseType_t ) MPU_uxTaskGetSystemStateImpl, /* SYSTEM_CALL_uxTaskGetSystemState. */ + #else + ( UBaseType_t ) 0, /* SYSTEM_CALL_uxTaskGetSystemState. */ + #endif + + #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) + ( UBaseType_t ) MPU_uxTaskGetStackHighWaterMarkImpl, /* SYSTEM_CALL_uxTaskGetStackHighWaterMark. */ + #else + ( UBaseType_t ) 0, /* SYSTEM_CALL_uxTaskGetStackHighWaterMark. */ + #endif + + #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) + ( UBaseType_t ) MPU_uxTaskGetStackHighWaterMark2Impl, /* SYSTEM_CALL_uxTaskGetStackHighWaterMark2. */ + #else + ( UBaseType_t ) 0, /* SYSTEM_CALL_uxTaskGetStackHighWaterMark2. */ + #endif + + #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) + ( UBaseType_t ) MPU_xTaskGetCurrentTaskHandleImpl, /* SYSTEM_CALL_xTaskGetCurrentTaskHandle. */ + #else + ( UBaseType_t ) 0, /* SYSTEM_CALL_xTaskGetCurrentTaskHandle. */ + #endif + + #if ( INCLUDE_xTaskGetSchedulerState == 1 ) + ( UBaseType_t ) MPU_xTaskGetSchedulerStateImpl, /* SYSTEM_CALL_xTaskGetSchedulerState. */ + #else + ( UBaseType_t ) 0, /* SYSTEM_CALL_xTaskGetSchedulerState. */ + #endif + + ( UBaseType_t ) MPU_vTaskSetTimeOutStateImpl, /* SYSTEM_CALL_vTaskSetTimeOutState. */ + ( UBaseType_t ) MPU_xTaskCheckForTimeOutImpl, /* SYSTEM_CALL_xTaskCheckForTimeOut. */ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + ( UBaseType_t ) MPU_ulTaskGenericNotifyTakeImpl, /* SYSTEM_CALL_ulTaskGenericNotifyTake. */ + ( UBaseType_t ) MPU_xTaskGenericNotifyStateClearImpl, /* SYSTEM_CALL_xTaskGenericNotifyStateClear. */ + ( UBaseType_t ) MPU_ulTaskGenericNotifyValueClearImpl, /* SYSTEM_CALL_ulTaskGenericNotifyValueClear. */ + #else + ( UBaseType_t ) 0, /* SYSTEM_CALL_ulTaskGenericNotifyTake. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_xTaskGenericNotifyStateClear. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_ulTaskGenericNotifyValueClear. */ + #endif + + ( UBaseType_t ) MPU_xQueueGenericSendImpl, /* SYSTEM_CALL_xQueueGenericSend. */ + ( UBaseType_t ) MPU_uxQueueMessagesWaitingImpl, /* SYSTEM_CALL_uxQueueMessagesWaiting. */ + ( UBaseType_t ) MPU_uxQueueSpacesAvailableImpl, /* SYSTEM_CALL_uxQueueSpacesAvailable. */ + ( UBaseType_t ) MPU_xQueueReceiveImpl, /* SYSTEM_CALL_xQueueReceive. */ + ( UBaseType_t ) MPU_xQueuePeekImpl, /* SYSTEM_CALL_xQueuePeek. */ + ( UBaseType_t ) MPU_xQueueSemaphoreTakeImpl, /* SYSTEM_CALL_xQueueSemaphoreTake. */ + + #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) + ( UBaseType_t ) MPU_xQueueGetMutexHolderImpl, /* SYSTEM_CALL_xQueueGetMutexHolder. */ + #else + ( UBaseType_t ) 0, /* SYSTEM_CALL_xQueueGetMutexHolder. */ + #endif + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + ( UBaseType_t ) MPU_xQueueTakeMutexRecursiveImpl, /* SYSTEM_CALL_xQueueTakeMutexRecursive. */ + ( UBaseType_t ) MPU_xQueueGiveMutexRecursiveImpl, /* SYSTEM_CALL_xQueueGiveMutexRecursive. */ + #else + ( UBaseType_t ) 0, /* SYSTEM_CALL_xQueueTakeMutexRecursive. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_xQueueGiveMutexRecursive. */ + #endif + + #if ( configUSE_QUEUE_SETS == 1 ) + ( UBaseType_t ) MPU_xQueueSelectFromSetImpl, /* SYSTEM_CALL_xQueueSelectFromSet. */ + ( UBaseType_t ) MPU_xQueueAddToSetImpl, /* SYSTEM_CALL_xQueueAddToSet. */ + #else + ( UBaseType_t ) 0, /* SYSTEM_CALL_xQueueSelectFromSet. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_xQueueAddToSet. */ + #endif + + #if configQUEUE_REGISTRY_SIZE > 0 + ( UBaseType_t ) MPU_vQueueAddToRegistryImpl, /* SYSTEM_CALL_vQueueAddToRegistry. */ + ( UBaseType_t ) MPU_vQueueUnregisterQueueImpl, /* SYSTEM_CALL_vQueueUnregisterQueue. */ + ( UBaseType_t ) MPU_pcQueueGetNameImpl, /* SYSTEM_CALL_pcQueueGetName. */ + #else + ( UBaseType_t ) 0, /* SYSTEM_CALL_vQueueAddToRegistry. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_vQueueUnregisterQueue. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_pcQueueGetName. */ + #endif + + #if ( configUSE_TIMERS == 1 ) + ( UBaseType_t ) MPU_pvTimerGetTimerIDImpl, /* SYSTEM_CALL_pvTimerGetTimerID. */ + ( UBaseType_t ) MPU_vTimerSetTimerIDImpl, /* SYSTEM_CALL_vTimerSetTimerID. */ + ( UBaseType_t ) MPU_xTimerIsTimerActiveImpl, /* SYSTEM_CALL_xTimerIsTimerActive. */ + ( UBaseType_t ) MPU_xTimerGetTimerDaemonTaskHandleImpl, /* SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle. */ + ( UBaseType_t ) MPU_pcTimerGetNameImpl, /* SYSTEM_CALL_pcTimerGetName. */ + ( UBaseType_t ) MPU_vTimerSetReloadModeImpl, /* SYSTEM_CALL_vTimerSetReloadMode. */ + ( UBaseType_t ) MPU_xTimerGetReloadModeImpl, /* SYSTEM_CALL_xTimerGetReloadMode. */ + ( UBaseType_t ) MPU_uxTimerGetReloadModeImpl, /* SYSTEM_CALL_uxTimerGetReloadMode. */ + ( UBaseType_t ) MPU_xTimerGetPeriodImpl, /* SYSTEM_CALL_xTimerGetPeriod. */ + ( UBaseType_t ) MPU_xTimerGetExpiryTimeImpl, /* SYSTEM_CALL_xTimerGetExpiryTime. */ + #else + ( UBaseType_t ) 0, /* SYSTEM_CALL_pvTimerGetTimerID. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_vTimerSetTimerID. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_xTimerIsTimerActive. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_pcTimerGetName. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_vTimerSetReloadMode. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_xTimerGetReloadMode. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_uxTimerGetReloadMode. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_xTimerGetPeriod. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_xTimerGetExpiryTime. */ + #endif + + #if ( configUSE_EVENT_GROUPS == 1 ) + ( UBaseType_t ) MPU_xEventGroupClearBitsImpl, /* SYSTEM_CALL_xEventGroupClearBits. */ + ( UBaseType_t ) MPU_xEventGroupSetBitsImpl, /* SYSTEM_CALL_xEventGroupSetBits. */ + ( UBaseType_t ) MPU_xEventGroupSyncImpl, /* SYSTEM_CALL_xEventGroupSync. */ + + #if ( configUSE_TRACE_FACILITY == 1 ) + ( UBaseType_t ) MPU_uxEventGroupGetNumberImpl, /* SYSTEM_CALL_uxEventGroupGetNumber. */ + ( UBaseType_t ) MPU_vEventGroupSetNumberImpl, /* SYSTEM_CALL_vEventGroupSetNumber. */ + #else + ( UBaseType_t ) 0, /* SYSTEM_CALL_uxEventGroupGetNumber. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_vEventGroupSetNumber. */ + #endif + #else + ( UBaseType_t ) 0, /* SYSTEM_CALL_xEventGroupClearBits. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_xEventGroupSetBits. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_xEventGroupSync. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_uxEventGroupGetNumber. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_vEventGroupSetNumber. */ + #endif + + #if ( configUSE_STREAM_BUFFERS == 1 ) + ( UBaseType_t ) MPU_xStreamBufferSendImpl, /* SYSTEM_CALL_xStreamBufferSend. */ + ( UBaseType_t ) MPU_xStreamBufferReceiveImpl, /* SYSTEM_CALL_xStreamBufferReceive. */ + ( UBaseType_t ) MPU_xStreamBufferIsFullImpl, /* SYSTEM_CALL_xStreamBufferIsFull. */ + ( UBaseType_t ) MPU_xStreamBufferIsEmptyImpl, /* SYSTEM_CALL_xStreamBufferIsEmpty. */ + ( UBaseType_t ) MPU_xStreamBufferSpacesAvailableImpl, /* SYSTEM_CALL_xStreamBufferSpacesAvailable. */ + ( UBaseType_t ) MPU_xStreamBufferBytesAvailableImpl, /* SYSTEM_CALL_xStreamBufferBytesAvailable. */ + ( UBaseType_t ) MPU_xStreamBufferSetTriggerLevelImpl, /* SYSTEM_CALL_xStreamBufferSetTriggerLevel. */ + ( UBaseType_t ) MPU_xStreamBufferNextMessageLengthBytesImpl /* SYSTEM_CALL_xStreamBufferNextMessageLengthBytes. */ + #else + ( UBaseType_t ) 0, /* SYSTEM_CALL_xStreamBufferSend. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_xStreamBufferReceive. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_xStreamBufferIsFull. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_xStreamBufferIsEmpty. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_xStreamBufferSpacesAvailable. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_xStreamBufferBytesAvailable. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_xStreamBufferSetTriggerLevel. */ + ( UBaseType_t ) 0, /* SYSTEM_CALL_xStreamBufferNextMessageLengthBytes. */ + #endif + + }; +/*-----------------------------------------------------------*/ + +#endif /* #if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM7_AT91FR40008/port.c b/portable/GCC/ARM7_AT91FR40008/port.c new file mode 100644 index 000000000..30bbb9f48 --- /dev/null +++ b/portable/GCC/ARM7_AT91FR40008/port.c @@ -0,0 +1,240 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the Atmel AT91R40008 +* port. +* +* Components that can be compiled to either ARM or THUMB mode are +* contained in this file. The ISR routines, which can only be compiled +* to ARM mode are contained in portISR.c. +*----------------------------------------------------------*/ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Hardware specific definitions. */ +#include "AT91R40008.h" +#include "pio.h" +#include "aic.h" +#include "tc.h" + +/* Constants required to setup the task context. */ +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) +#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 ) +#define portTICK_PRIORITY_6 ( 6 ) +/*-----------------------------------------------------------*/ + +/* Setup the timer to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* + * The scheduler can only be started from ARM mode, so + * vPortISRStartFirstSTask() is defined in portISR.c. + */ +extern void vPortISRStartFirstTask( void ); + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + StackType_t * pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + /* To ensure asserts in tasks.c don't fail, although in this case the assert + * is not really required. */ + pxTopOfStack--; + + /* Setup the initial stack of the task. The stack is set exactly as + * expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which in this case is the + * start of the task. The offset is added to make the return address appear + * as it would within an IRQ ISR. */ + *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + * R0. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The last thing onto the stack is the status register, which is set for + * system mode, with interrupts enabled. */ + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + + #ifdef THUMB_INTERWORK + { + /* We want the task to start in thumb mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + #endif + + pxTopOfStack--; + + /* Some optimisation levels use the stack differently to others. This + * means the interrupt flags cannot always be stored on the stack and will + * instead be stored in a variable, which is then saved as part of the + * tasks context. */ + *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortISRStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + * is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +/* + * Setup the tick timer to generate the tick interrupts at the required frequency. + */ +static void prvSetupTimerInterrupt( void ) +{ + volatile uint32_t ulDummy; + + /* Enable clock to the tick timer... */ + AT91C_BASE_PS->PS_PCER = portTIMER_CLK_ENABLE_BIT; + + /* Stop the tick timer... */ + portTIMER_REG_BASE_PTR->TC_CCR = TC_CLKDIS; + + /* Start with tick timer interrupts disabled... */ + portTIMER_REG_BASE_PTR->TC_IDR = 0xFFFFFFFF; + + /* Clear any pending tick timer interrupts... */ + ulDummy = portTIMER_REG_BASE_PTR->TC_SR; + + /* Store interrupt handler function address in tick timer vector register... + * The ISR installed depends on whether the preemptive or cooperative + * scheduler is being used. */ + #if configUSE_PREEMPTION == 1 + { + extern void( vPreemptiveTick )( void ); + AT91C_BASE_AIC->AIC_SVR[ portTIMER_AIC_CHANNEL ] = ( uint32_t ) vPreemptiveTick; + } + #else // else use cooperative scheduler + { + extern void( vNonPreemptiveTick )( void ); + AT91C_BASE_AIC->AIC_SVR[ portTIMER_AIC_CHANNEL ] = ( uint32_t ) vNonPreemptiveTick; + } + #endif + + /* Tick timer interrupt level-sensitive, priority 6... */ + AT91C_BASE_AIC->AIC_SMR[ portTIMER_AIC_CHANNEL ] = AIC_SRCTYPE_INT_LEVEL_SENSITIVE | portTICK_PRIORITY_6; + + /* Enable the tick timer interrupt... + * + * First at timer level */ + portTIMER_REG_BASE_PTR->TC_IER = TC_CPCS; + + /* Then at the AIC level. */ + AT91C_BASE_AIC->AIC_IECR = ( 1 << portTIMER_AIC_CHANNEL ); + + /* Calculate timer compare value to achieve the desired tick rate... */ + if( ( configCPU_CLOCK_HZ / ( configTICK_RATE_HZ * 2 ) ) <= 0xFFFF ) + { + /* The tick rate is fast enough for us to use the faster timer input + * clock (main clock / 2). */ + portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK2 | TC_BURST_NONE | TC_CPCTRG; + portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / ( configTICK_RATE_HZ * 2 ); + } + else + { + /* We must use a slower timer input clock (main clock / 8) because the + * tick rate is too slow for the faster input clock. */ + portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK8 | TC_BURST_NONE | TC_CPCTRG; + portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / ( configTICK_RATE_HZ * 8 ); + } + + /* Start tick timer... */ + portTIMER_REG_BASE_PTR->TC_CCR = TC_SWTRG | TC_CLKEN; +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM7_AT91FR40008/portISR.c b/portable/GCC/ARM7_AT91FR40008/portISR.c new file mode 100644 index 000000000..b4ddcc06d --- /dev/null +++ b/portable/GCC/ARM7_AT91FR40008/portISR.c @@ -0,0 +1,233 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/*----------------------------------------------------------- +* Components that can be compiled to either ARM or THUMB mode are +* contained in port.c The ISR routines, which can only be compiled +* to ARM mode, are contained in this file. +*----------------------------------------------------------*/ + +/* + * Changes from V3.2.4 + * + + The assembler statements are now included in a single asm block rather + + than each line having its own asm block. + */ + + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to handle interrupts. */ +#define portCLEAR_AIC_INTERRUPT ( ( uint32_t ) 0 ) + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) +volatile uint32_t ulCriticalNesting = 9999UL; + +/*-----------------------------------------------------------*/ + +/* ISR to handle manual context switches (from a call to taskYIELD()). */ +void vPortYieldProcessor( void ) __attribute__( ( interrupt( "SWI" ), naked ) ); + +/* + * The scheduler can only be started from ARM mode, hence the inclusion of this + * function here. + */ +void vPortISRStartFirstTask( void ); +/*-----------------------------------------------------------*/ + +void vPortISRStartFirstTask( void ) +{ + /* Simply start the scheduler. This is included here as it can only be + * called from ARM mode. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * Called by portYIELD() or taskYIELD() to manually force a context switch. + * + * When a context switch is performed from the task level the saved task + * context is made to look as if it occurred from within the tick ISR. This + * way the same restore context function can be used when restoring the context + * saved from the ISR or that saved from a call to vPortYieldProcessor. + */ +void vPortYieldProcessor( void ) +{ + /* Within an IRQ ISR the link register has an offset from the true return + * address, but an SWI ISR does not. Add the offset manually so the same + * ISR return code can be used in both cases. */ + asm volatile ( "ADD LR, LR, #4" ); + + /* Perform the context switch. First save the context of the current task. */ + portSAVE_CONTEXT(); + + /* Find the highest priority task that is ready to run. */ + vTaskSwitchContext(); + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * The ISR used for the scheduler tick depends on whether the cooperative or + * the preemptive scheduler is being used. + */ + +#if configUSE_PREEMPTION == 0 + +/* The cooperative scheduler requires a normal IRQ service routine to + * simply increment the system tick. */ + void vNonPreemptiveTick( void ) __attribute__( ( interrupt( "IRQ" ) ) ); + void vNonPreemptiveTick( void ) + { + static volatile uint32_t ulDummy; + + /* Clear tick timer interrupt indication. */ + ulDummy = portTIMER_REG_BASE_PTR->TC_SR; + + xTaskIncrementTick(); + + /* Acknowledge the interrupt at AIC level... */ + AT91C_BASE_AIC->AIC_EOICR = portCLEAR_AIC_INTERRUPT; + } + +#else /* else preemption is turned on */ + +/* The preemptive scheduler is defined as "naked" as the full context is + * saved on entry as part of the context switch. */ + void vPreemptiveTick( void ) __attribute__( ( naked ) ); + void vPreemptiveTick( void ) + { + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT(); + + /* WARNING - Do not use local (stack) variables here. Use globals + * if you must! */ + static volatile uint32_t ulDummy; + + /* Clear tick timer interrupt indication. */ + ulDummy = portTIMER_REG_BASE_PTR->TC_SR; + + /* Increment the RTOS tick count, then look for the highest priority + * task that is ready to run. */ + if( xTaskIncrementTick() != pdFALSE ) + { + vTaskSwitchContext(); + } + + /* Acknowledge the interrupt at AIC level... */ + AT91C_BASE_AIC->AIC_EOICR = portCLEAR_AIC_INTERRUPT; + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT(); + } + +#endif /* if configUSE_PREEMPTION == 0 */ +/*-----------------------------------------------------------*/ + +/* + * The interrupt management utilities can only be called from ARM mode. When + * THUMB_INTERWORK is defined the utilities are defined as functions here to + * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then + * the utilities are defined as macros in portmacro.h - as per other ports. + */ +#ifdef THUMB_INTERWORK + + void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) ); + void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) ); + + void vPortDisableInterruptsFromThumb( void ) + { + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ + } + + void vPortEnableInterruptsFromThumb( void ) + { + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ + } + +#endif /* THUMB_INTERWORK */ + +/* The code generated by the GCC compiler uses the stack in different ways at + * different optimisation levels. The interrupt flags can therefore not always + * be saved to the stack. Instead the critical section nesting level is stored + * in a variable, which is then saved as part of the stack context. */ +void vPortEnterCritical( void ) +{ + /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ + + /* Now that interrupts are disabled, ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + * re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Enable interrupts as per portEXIT_CRITICAL(). */ + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ + } + } +} diff --git a/portable/GCC/ARM7_AT91FR40008/portmacro.h b/portable/GCC/ARM7_AT91FR40008/portmacro.h new file mode 100644 index 000000000..4dbadab3f --- /dev/null +++ b/portable/GCC/ARM7_AT91FR40008/portmacro.h @@ -0,0 +1,261 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * Changes from V3.2.3 + * + + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1. + + + + Changes from V3.2.4 + + + + Removed the use of the %0 parameter within the assembler macros and + + replaced them with hard coded registers. This will ensure the + + assembler does not select the link register as the temp register as + + was occasionally happening previously. + + + + The assembler statements are now included in a single asm block rather + + than each line having its own asm block. + + + + Changes from V4.5.0 + + + + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros + + and replaced them with portYIELD_FROM_ISR() macro. Application code + + should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT() + + macros as per the V4.5.1 demo code. + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portYIELD() asm volatile ( "SWI 0" ) +#define portNOP() asm volatile ( "NOP" ) + +/* + * These define the timer to use for generating the tick interrupt. + * They are put in this file so they can be shared between "port.c" + * and "portisr.c". + */ +#define portTIMER_REG_BASE_PTR AT91C_BASE_TC0 +#define portTIMER_CLK_ENABLE_BIT AT91C_PS_TC0 +#define portTIMER_AIC_CHANNEL ( ( uint32_t ) 4 ) +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* + * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR + * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but + * are included here for efficiency. An attempt to call one from + * THUMB mode code will result in a compile time error. + */ + +#define portRESTORE_CONTEXT() \ + { \ + extern volatile void * volatile pxCurrentTCB; \ + extern volatile uint32_t ulCriticalNesting; \ + \ + /* Set the LR to the task stack. */ \ + asm volatile ( \ + "LDR R0, =pxCurrentTCB \n\t" \ + "LDR R0, [R0] \n\t" \ + "LDR LR, [R0] \n\t" \ + \ + /* The critical nesting depth is the first item on the stack. */ \ + /* Load it into the ulCriticalNesting variable. */ \ + "LDR R0, =ulCriticalNesting \n\t" \ + "LDMFD LR!, {R1} \n\t" \ + "STR R1, [R0] \n\t" \ + \ + /* Get the SPSR from the stack. */ \ + "LDMFD LR!, {R0} \n\t" \ + "MSR SPSR, R0 \n\t" \ + \ + /* Restore all system mode registers for the task. */ \ + "LDMFD LR, {R0-R14}^ \n\t" \ + "NOP \n\t" \ + \ + /* Restore the return address. */ \ + "LDR LR, [LR, #+60] \n\t" \ + \ + /* And return - correcting the offset in the LR to obtain the */ \ + /* correct address. */ \ + "SUBS PC, LR, #4 \n\t" \ + ); \ + ( void ) ulCriticalNesting; \ + ( void ) pxCurrentTCB; \ + } +/*-----------------------------------------------------------*/ + +#define portSAVE_CONTEXT() \ + { \ + extern volatile void * volatile pxCurrentTCB; \ + extern volatile uint32_t ulCriticalNesting; \ + \ + /* Push R0 as we are going to use the register. */ \ + asm volatile ( \ + "STMDB SP!, {R0} \n\t" \ + \ + /* Set R0 to point to the task stack pointer. */ \ + "STMDB SP,{SP}^ \n\t" \ + "NOP \n\t" \ + "SUB SP, SP, #4 \n\t" \ + "LDMIA SP!,{R0} \n\t" \ + \ + /* Push the return address onto the stack. */ \ + "STMDB R0!, {LR} \n\t" \ + \ + /* Now we have saved LR we can use it instead of R0. */ \ + "MOV LR, R0 \n\t" \ + \ + /* Pop R0 so we can save it onto the system mode stack. */ \ + "LDMIA SP!, {R0} \n\t" \ + \ + /* Push all the system mode registers onto the task stack. */ \ + "STMDB LR,{R0-LR}^ \n\t" \ + "NOP \n\t" \ + "SUB LR, LR, #60 \n\t" \ + \ + /* Push the SPSR onto the task stack. */ \ + "MRS R0, SPSR \n\t" \ + "STMDB LR!, {R0} \n\t" \ + \ + "LDR R0, =ulCriticalNesting \n\t" \ + "LDR R0, [R0] \n\t" \ + "STMDB LR!, {R0} \n\t" \ + \ + /* Store the new top of stack for the task. */ \ + "LDR R0, =pxCurrentTCB \n\t" \ + "LDR R0, [R0] \n\t" \ + "STR LR, [R0] \n\t" \ + ); \ + ( void ) ulCriticalNesting; \ + ( void ) pxCurrentTCB; \ + } + +#define portYIELD_FROM_ISR() vTaskSwitchContext() + +/* Critical section handling. */ + +/* + * The interrupt management utilities can only be called from ARM mode. When + * THUMB_INTERWORK is defined the utilities are defined as functions in + * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not + * defined then the utilities are defined as macros here - as per other ports. + */ + +#ifdef THUMB_INTERWORK + + extern void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) ); + extern void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) ); + + #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb() + #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb() + +#else + + #define portDISABLE_INTERRUPTS() \ + asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ + + #define portENABLE_INTERRUPTS() \ + asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ + +#endif /* THUMB_INTERWORK */ + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h b/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h new file mode 100644 index 000000000..e5aa862e0 --- /dev/null +++ b/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h @@ -0,0 +1,2759 @@ +/* ---------------------------------------------------------------------------- */ +/* ATMEL Microcontroller Software Support - ROUSSET - */ +/* ---------------------------------------------------------------------------- */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ +/* File Name : AT91SAM7X256.h */ +/* Object : AT91SAM7X256 definitions */ +/* Generated : AT91 SW Application Group 05/20/2005 (16:22:29) */ +/* */ +/* CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005// */ +/* CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// */ +/* CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// */ +/* CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// */ +/* CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// */ +/* CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// */ +/* CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// */ +/* CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// */ +/* CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// */ +/* CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// */ +/* CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// */ +/* CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// */ +/* CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// */ +/* CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// */ +/* CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// */ +/* CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// */ +/* CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// */ +/* CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// */ +/* CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// */ +/* CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// */ +/* CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// */ +/* CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// */ +/* CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// */ +/* CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// */ +/* CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// */ +/* ---------------------------------------------------------------------------- */ + +#ifndef AT91SAM7X256_H +#define AT91SAM7X256_H + +typedef volatile unsigned int AT91_REG; /* Hardware register definition */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR System Peripherals */ +/* ***************************************************************************** */ +typedef struct _AT91S_SYS +{ + AT91_REG AIC_SMR[ 32 ]; /* Source Mode Register */ + AT91_REG AIC_SVR[ 32 ]; /* Source Vector Register */ + AT91_REG AIC_IVR; /* IRQ Vector Register */ + AT91_REG AIC_FVR; /* FIQ Vector Register */ + AT91_REG AIC_ISR; /* Interrupt Status Register */ + AT91_REG AIC_IPR; /* Interrupt Pending Register */ + AT91_REG AIC_IMR; /* Interrupt Mask Register */ + AT91_REG AIC_CISR; /* Core Interrupt Status Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG AIC_IECR; /* Interrupt Enable Command Register */ + AT91_REG AIC_IDCR; /* Interrupt Disable Command Register */ + AT91_REG AIC_ICCR; /* Interrupt Clear Command Register */ + AT91_REG AIC_ISCR; /* Interrupt Set Command Register */ + AT91_REG AIC_EOICR; /* End of Interrupt Command Register */ + AT91_REG AIC_SPU; /* Spurious Vector Register */ + AT91_REG AIC_DCR; /* Debug Control Register (Protect) */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG AIC_FFER; /* Fast Forcing Enable Register */ + AT91_REG AIC_FFDR; /* Fast Forcing Disable Register */ + AT91_REG AIC_FFSR; /* Fast Forcing Status Register */ + AT91_REG Reserved2[ 45 ]; /* */ + AT91_REG DBGU_CR; /* Control Register */ + AT91_REG DBGU_MR; /* Mode Register */ + AT91_REG DBGU_IER; /* Interrupt Enable Register */ + AT91_REG DBGU_IDR; /* Interrupt Disable Register */ + AT91_REG DBGU_IMR; /* Interrupt Mask Register */ + AT91_REG DBGU_CSR; /* Channel Status Register */ + AT91_REG DBGU_RHR; /* Receiver Holding Register */ + AT91_REG DBGU_THR; /* Transmitter Holding Register */ + AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */ + AT91_REG Reserved3[ 7 ]; /* */ + AT91_REG DBGU_CIDR; /* Chip ID Register */ + AT91_REG DBGU_EXID; /* Chip ID Extension Register */ + AT91_REG DBGU_FNTR; /* Force NTRST Register */ + AT91_REG Reserved4[ 45 ]; /* */ + AT91_REG DBGU_RPR; /* Receive Pointer Register */ + AT91_REG DBGU_RCR; /* Receive Counter Register */ + AT91_REG DBGU_TPR; /* Transmit Pointer Register */ + AT91_REG DBGU_TCR; /* Transmit Counter Register */ + AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */ + AT91_REG DBGU_RNCR; /* Receive Next Counter Register */ + AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */ + AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */ + AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */ + AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */ + AT91_REG Reserved5[ 54 ]; /* */ + AT91_REG PIOA_PER; /* PIO Enable Register */ + AT91_REG PIOA_PDR; /* PIO Disable Register */ + AT91_REG PIOA_PSR; /* PIO Status Register */ + AT91_REG Reserved6[ 1 ]; /* */ + AT91_REG PIOA_OER; /* Output Enable Register */ + AT91_REG PIOA_ODR; /* Output Disable Registerr */ + AT91_REG PIOA_OSR; /* Output Status Register */ + AT91_REG Reserved7[ 1 ]; /* */ + AT91_REG PIOA_IFER; /* Input Filter Enable Register */ + AT91_REG PIOA_IFDR; /* Input Filter Disable Register */ + AT91_REG PIOA_IFSR; /* Input Filter Status Register */ + AT91_REG Reserved8[ 1 ]; /* */ + AT91_REG PIOA_SODR; /* Set Output Data Register */ + AT91_REG PIOA_CODR; /* Clear Output Data Register */ + AT91_REG PIOA_ODSR; /* Output Data Status Register */ + AT91_REG PIOA_PDSR; /* Pin Data Status Register */ + AT91_REG PIOA_IER; /* Interrupt Enable Register */ + AT91_REG PIOA_IDR; /* Interrupt Disable Register */ + AT91_REG PIOA_IMR; /* Interrupt Mask Register */ + AT91_REG PIOA_ISR; /* Interrupt Status Register */ + AT91_REG PIOA_MDER; /* Multi-driver Enable Register */ + AT91_REG PIOA_MDDR; /* Multi-driver Disable Register */ + AT91_REG PIOA_MDSR; /* Multi-driver Status Register */ + AT91_REG Reserved9[ 1 ]; /* */ + AT91_REG PIOA_PPUDR; /* Pull-up Disable Register */ + AT91_REG PIOA_PPUER; /* Pull-up Enable Register */ + AT91_REG PIOA_PPUSR; /* Pull-up Status Register */ + AT91_REG Reserved10[ 1 ]; /* */ + AT91_REG PIOA_ASR; /* Select A Register */ + AT91_REG PIOA_BSR; /* Select B Register */ + AT91_REG PIOA_ABSR; /* AB Select Status Register */ + AT91_REG Reserved11[ 9 ]; /* */ + AT91_REG PIOA_OWER; /* Output Write Enable Register */ + AT91_REG PIOA_OWDR; /* Output Write Disable Register */ + AT91_REG PIOA_OWSR; /* Output Write Status Register */ + AT91_REG Reserved12[ 85 ]; /* */ + AT91_REG PIOB_PER; /* PIO Enable Register */ + AT91_REG PIOB_PDR; /* PIO Disable Register */ + AT91_REG PIOB_PSR; /* PIO Status Register */ + AT91_REG Reserved13[ 1 ]; /* */ + AT91_REG PIOB_OER; /* Output Enable Register */ + AT91_REG PIOB_ODR; /* Output Disable Registerr */ + AT91_REG PIOB_OSR; /* Output Status Register */ + AT91_REG Reserved14[ 1 ]; /* */ + AT91_REG PIOB_IFER; /* Input Filter Enable Register */ + AT91_REG PIOB_IFDR; /* Input Filter Disable Register */ + AT91_REG PIOB_IFSR; /* Input Filter Status Register */ + AT91_REG Reserved15[ 1 ]; /* */ + AT91_REG PIOB_SODR; /* Set Output Data Register */ + AT91_REG PIOB_CODR; /* Clear Output Data Register */ + AT91_REG PIOB_ODSR; /* Output Data Status Register */ + AT91_REG PIOB_PDSR; /* Pin Data Status Register */ + AT91_REG PIOB_IER; /* Interrupt Enable Register */ + AT91_REG PIOB_IDR; /* Interrupt Disable Register */ + AT91_REG PIOB_IMR; /* Interrupt Mask Register */ + AT91_REG PIOB_ISR; /* Interrupt Status Register */ + AT91_REG PIOB_MDER; /* Multi-driver Enable Register */ + AT91_REG PIOB_MDDR; /* Multi-driver Disable Register */ + AT91_REG PIOB_MDSR; /* Multi-driver Status Register */ + AT91_REG Reserved16[ 1 ]; /* */ + AT91_REG PIOB_PPUDR; /* Pull-up Disable Register */ + AT91_REG PIOB_PPUER; /* Pull-up Enable Register */ + AT91_REG PIOB_PPUSR; /* Pull-up Status Register */ + AT91_REG Reserved17[ 1 ]; /* */ + AT91_REG PIOB_ASR; /* Select A Register */ + AT91_REG PIOB_BSR; /* Select B Register */ + AT91_REG PIOB_ABSR; /* AB Select Status Register */ + AT91_REG Reserved18[ 9 ]; /* */ + AT91_REG PIOB_OWER; /* Output Write Enable Register */ + AT91_REG PIOB_OWDR; /* Output Write Disable Register */ + AT91_REG PIOB_OWSR; /* Output Write Status Register */ + AT91_REG Reserved19[ 341 ]; /* */ + AT91_REG PMC_SCER; /* System Clock Enable Register */ + AT91_REG PMC_SCDR; /* System Clock Disable Register */ + AT91_REG PMC_SCSR; /* System Clock Status Register */ + AT91_REG Reserved20[ 1 ]; /* */ + AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */ + AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */ + AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */ + AT91_REG Reserved21[ 1 ]; /* */ + AT91_REG PMC_MOR; /* Main Oscillator Register */ + AT91_REG PMC_MCFR; /* Main Clock Frequency Register */ + AT91_REG Reserved22[ 1 ]; /* */ + AT91_REG PMC_PLLR; /* PLL Register */ + AT91_REG PMC_MCKR; /* Master Clock Register */ + AT91_REG Reserved23[ 3 ]; /* */ + AT91_REG PMC_PCKR[ 4 ]; /* Programmable Clock Register */ + AT91_REG Reserved24[ 4 ]; /* */ + AT91_REG PMC_IER; /* Interrupt Enable Register */ + AT91_REG PMC_IDR; /* Interrupt Disable Register */ + AT91_REG PMC_SR; /* Status Register */ + AT91_REG PMC_IMR; /* Interrupt Mask Register */ + AT91_REG Reserved25[ 36 ]; /* */ + AT91_REG RSTC_RCR; /* Reset Control Register */ + AT91_REG RSTC_RSR; /* Reset Status Register */ + AT91_REG RSTC_RMR; /* Reset Mode Register */ + AT91_REG Reserved26[ 5 ]; /* */ + AT91_REG RTTC_RTMR; /* Real-time Mode Register */ + AT91_REG RTTC_RTAR; /* Real-time Alarm Register */ + AT91_REG RTTC_RTVR; /* Real-time Value Register */ + AT91_REG RTTC_RTSR; /* Real-time Status Register */ + AT91_REG PITC_PIMR; /* Period Interval Mode Register */ + AT91_REG PITC_PISR; /* Period Interval Status Register */ + AT91_REG PITC_PIVR; /* Period Interval Value Register */ + AT91_REG PITC_PIIR; /* Period Interval Image Register */ + AT91_REG WDTC_WDCR; /* Watchdog Control Register */ + AT91_REG WDTC_WDMR; /* Watchdog Mode Register */ + AT91_REG WDTC_WDSR; /* Watchdog Status Register */ + AT91_REG Reserved27[ 5 ]; /* */ + AT91_REG VREG_MR; /* Voltage Regulator Mode Register */ +} AT91S_SYS, * AT91PS_SYS; + + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Advanced Interrupt Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_AIC +{ + AT91_REG AIC_SMR[ 32 ]; /* Source Mode Register */ + AT91_REG AIC_SVR[ 32 ]; /* Source Vector Register */ + AT91_REG AIC_IVR; /* IRQ Vector Register */ + AT91_REG AIC_FVR; /* FIQ Vector Register */ + AT91_REG AIC_ISR; /* Interrupt Status Register */ + AT91_REG AIC_IPR; /* Interrupt Pending Register */ + AT91_REG AIC_IMR; /* Interrupt Mask Register */ + AT91_REG AIC_CISR; /* Core Interrupt Status Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG AIC_IECR; /* Interrupt Enable Command Register */ + AT91_REG AIC_IDCR; /* Interrupt Disable Command Register */ + AT91_REG AIC_ICCR; /* Interrupt Clear Command Register */ + AT91_REG AIC_ISCR; /* Interrupt Set Command Register */ + AT91_REG AIC_EOICR; /* End of Interrupt Command Register */ + AT91_REG AIC_SPU; /* Spurious Vector Register */ + AT91_REG AIC_DCR; /* Debug Control Register (Protect) */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG AIC_FFER; /* Fast Forcing Enable Register */ + AT91_REG AIC_FFDR; /* Fast Forcing Disable Register */ + AT91_REG AIC_FFSR; /* Fast Forcing Status Register */ +} AT91S_AIC, * AT91PS_AIC; + +/* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */ +#define AT91C_AIC_PRIOR ( ( unsigned int ) 0x7 << 0 ) /* (AIC) Priority Level */ +#define AT91C_AIC_PRIOR_LOWEST ( ( unsigned int ) 0x0 ) /* (AIC) Lowest priority level */ +#define AT91C_AIC_PRIOR_HIGHEST ( ( unsigned int ) 0x7 ) /* (AIC) Highest priority level */ +#define AT91C_AIC_SRCTYPE ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Interrupt Source Type */ +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ( ( unsigned int ) 0x0 << 5 ) /* (AIC) Internal Sources Code Label High-level Sensitive */ +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ( ( unsigned int ) 0x0 << 5 ) /* (AIC) External Sources Code Label Low-level Sensitive */ +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ( ( unsigned int ) 0x1 << 5 ) /* (AIC) Internal Sources Code Label Positive Edge triggered */ +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ( ( unsigned int ) 0x1 << 5 ) /* (AIC) External Sources Code Label Negative Edge triggered */ +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ( ( unsigned int ) 0x2 << 5 ) /* (AIC) Internal Or External Sources Code Label High-level Sensitive */ +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Internal Or External Sources Code Label Positive Edge triggered */ +/* -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- */ +#define AT91C_AIC_NFIQ ( ( unsigned int ) 0x1 << 0 ) /* (AIC) NFIQ Status */ +#define AT91C_AIC_NIRQ ( ( unsigned int ) 0x1 << 1 ) /* (AIC) NIRQ Status */ +/* -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- */ +#define AT91C_AIC_DCR_PROT ( ( unsigned int ) 0x1 << 0 ) /* (AIC) Protection Mode */ +#define AT91C_AIC_DCR_GMSK ( ( unsigned int ) 0x1 << 1 ) /* (AIC) General Mask */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Peripheral DMA Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_PDC +{ + AT91_REG PDC_RPR; /* Receive Pointer Register */ + AT91_REG PDC_RCR; /* Receive Counter Register */ + AT91_REG PDC_TPR; /* Transmit Pointer Register */ + AT91_REG PDC_TCR; /* Transmit Counter Register */ + AT91_REG PDC_RNPR; /* Receive Next Pointer Register */ + AT91_REG PDC_RNCR; /* Receive Next Counter Register */ + AT91_REG PDC_TNPR; /* Transmit Next Pointer Register */ + AT91_REG PDC_TNCR; /* Transmit Next Counter Register */ + AT91_REG PDC_PTCR; /* PDC Transfer Control Register */ + AT91_REG PDC_PTSR; /* PDC Transfer Status Register */ +} AT91S_PDC, * AT91PS_PDC; + +/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */ +#define AT91C_PDC_RXTEN ( ( unsigned int ) 0x1 << 0 ) /* (PDC) Receiver Transfer Enable */ +#define AT91C_PDC_RXTDIS ( ( unsigned int ) 0x1 << 1 ) /* (PDC) Receiver Transfer Disable */ +#define AT91C_PDC_TXTEN ( ( unsigned int ) 0x1 << 8 ) /* (PDC) Transmitter Transfer Enable */ +#define AT91C_PDC_TXTDIS ( ( unsigned int ) 0x1 << 9 ) /* (PDC) Transmitter Transfer Disable */ +/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Debug Unit */ +/* ***************************************************************************** */ +typedef struct _AT91S_DBGU +{ + AT91_REG DBGU_CR; /* Control Register */ + AT91_REG DBGU_MR; /* Mode Register */ + AT91_REG DBGU_IER; /* Interrupt Enable Register */ + AT91_REG DBGU_IDR; /* Interrupt Disable Register */ + AT91_REG DBGU_IMR; /* Interrupt Mask Register */ + AT91_REG DBGU_CSR; /* Channel Status Register */ + AT91_REG DBGU_RHR; /* Receiver Holding Register */ + AT91_REG DBGU_THR; /* Transmitter Holding Register */ + AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */ + AT91_REG Reserved0[ 7 ]; /* */ + AT91_REG DBGU_CIDR; /* Chip ID Register */ + AT91_REG DBGU_EXID; /* Chip ID Extension Register */ + AT91_REG DBGU_FNTR; /* Force NTRST Register */ + AT91_REG Reserved1[ 45 ]; /* */ + AT91_REG DBGU_RPR; /* Receive Pointer Register */ + AT91_REG DBGU_RCR; /* Receive Counter Register */ + AT91_REG DBGU_TPR; /* Transmit Pointer Register */ + AT91_REG DBGU_TCR; /* Transmit Counter Register */ + AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */ + AT91_REG DBGU_RNCR; /* Receive Next Counter Register */ + AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */ + AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */ + AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */ + AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */ +} AT91S_DBGU, * AT91PS_DBGU; + +/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */ +#define AT91C_US_RSTRX ( ( unsigned int ) 0x1 << 2 ) /* (DBGU) Reset Receiver */ +#define AT91C_US_RSTTX ( ( unsigned int ) 0x1 << 3 ) /* (DBGU) Reset Transmitter */ +#define AT91C_US_RXEN ( ( unsigned int ) 0x1 << 4 ) /* (DBGU) Receiver Enable */ +#define AT91C_US_RXDIS ( ( unsigned int ) 0x1 << 5 ) /* (DBGU) Receiver Disable */ +#define AT91C_US_TXEN ( ( unsigned int ) 0x1 << 6 ) /* (DBGU) Transmitter Enable */ +#define AT91C_US_TXDIS ( ( unsigned int ) 0x1 << 7 ) /* (DBGU) Transmitter Disable */ +#define AT91C_US_RSTSTA ( ( unsigned int ) 0x1 << 8 ) /* (DBGU) Reset Status Bits */ +/* -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- */ +#define AT91C_US_PAR ( ( unsigned int ) 0x7 << 9 ) /* (DBGU) Parity type */ +#define AT91C_US_PAR_EVEN ( ( unsigned int ) 0x0 << 9 ) /* (DBGU) Even Parity */ +#define AT91C_US_PAR_ODD ( ( unsigned int ) 0x1 << 9 ) /* (DBGU) Odd Parity */ +#define AT91C_US_PAR_SPACE ( ( unsigned int ) 0x2 << 9 ) /* (DBGU) Parity forced to 0 (Space) */ +#define AT91C_US_PAR_MARK ( ( unsigned int ) 0x3 << 9 ) /* (DBGU) Parity forced to 1 (Mark) */ +#define AT91C_US_PAR_NONE ( ( unsigned int ) 0x4 << 9 ) /* (DBGU) No Parity */ +#define AT91C_US_PAR_MULTI_DROP ( ( unsigned int ) 0x6 << 9 ) /* (DBGU) Multi-drop mode */ +#define AT91C_US_CHMODE ( ( unsigned int ) 0x3 << 14 ) /* (DBGU) Channel Mode */ +#define AT91C_US_CHMODE_NORMAL ( ( unsigned int ) 0x0 << 14 ) /* (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. */ +#define AT91C_US_CHMODE_AUTO ( ( unsigned int ) 0x1 << 14 ) /* (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. */ +#define AT91C_US_CHMODE_LOCAL ( ( unsigned int ) 0x2 << 14 ) /* (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. */ +#define AT91C_US_CHMODE_REMOTE ( ( unsigned int ) 0x3 << 14 ) /* (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. */ +/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ +#define AT91C_US_RXRDY ( ( unsigned int ) 0x1 << 0 ) /* (DBGU) RXRDY Interrupt */ +#define AT91C_US_TXRDY ( ( unsigned int ) 0x1 << 1 ) /* (DBGU) TXRDY Interrupt */ +#define AT91C_US_ENDRX ( ( unsigned int ) 0x1 << 3 ) /* (DBGU) End of Receive Transfer Interrupt */ +#define AT91C_US_ENDTX ( ( unsigned int ) 0x1 << 4 ) /* (DBGU) End of Transmit Interrupt */ +#define AT91C_US_OVRE ( ( unsigned int ) 0x1 << 5 ) /* (DBGU) Overrun Interrupt */ +#define AT91C_US_FRAME ( ( unsigned int ) 0x1 << 6 ) /* (DBGU) Framing Error Interrupt */ +#define AT91C_US_PARE ( ( unsigned int ) 0x1 << 7 ) /* (DBGU) Parity Error Interrupt */ +#define AT91C_US_TXEMPTY ( ( unsigned int ) 0x1 << 9 ) /* (DBGU) TXEMPTY Interrupt */ +#define AT91C_US_TXBUFE ( ( unsigned int ) 0x1 << 11 ) /* (DBGU) TXBUFE Interrupt */ +#define AT91C_US_RXBUFF ( ( unsigned int ) 0x1 << 12 ) /* (DBGU) RXBUFF Interrupt */ +#define AT91C_US_COMM_TX ( ( unsigned int ) 0x1 << 30 ) /* (DBGU) COMM_TX Interrupt */ +#define AT91C_US_COMM_RX ( ( unsigned int ) 0x1 << 31 ) /* (DBGU) COMM_RX Interrupt */ +/* -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- */ +/* -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- */ +/* -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- */ +/* -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- */ +#define AT91C_US_FORCE_NTRST ( ( unsigned int ) 0x1 << 0 ) /* (DBGU) Force NTRST in JTAG */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Parallel Input Output Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_PIO +{ + AT91_REG PIO_PER; /* PIO Enable Register */ + AT91_REG PIO_PDR; /* PIO Disable Register */ + AT91_REG PIO_PSR; /* PIO Status Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG PIO_OER; /* Output Enable Register */ + AT91_REG PIO_ODR; /* Output Disable Registerr */ + AT91_REG PIO_OSR; /* Output Status Register */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG PIO_IFER; /* Input Filter Enable Register */ + AT91_REG PIO_IFDR; /* Input Filter Disable Register */ + AT91_REG PIO_IFSR; /* Input Filter Status Register */ + AT91_REG Reserved2[ 1 ]; /* */ + AT91_REG PIO_SODR; /* Set Output Data Register */ + AT91_REG PIO_CODR; /* Clear Output Data Register */ + AT91_REG PIO_ODSR; /* Output Data Status Register */ + AT91_REG PIO_PDSR; /* Pin Data Status Register */ + AT91_REG PIO_IER; /* Interrupt Enable Register */ + AT91_REG PIO_IDR; /* Interrupt Disable Register */ + AT91_REG PIO_IMR; /* Interrupt Mask Register */ + AT91_REG PIO_ISR; /* Interrupt Status Register */ + AT91_REG PIO_MDER; /* Multi-driver Enable Register */ + AT91_REG PIO_MDDR; /* Multi-driver Disable Register */ + AT91_REG PIO_MDSR; /* Multi-driver Status Register */ + AT91_REG Reserved3[ 1 ]; /* */ + AT91_REG PIO_PPUDR; /* Pull-up Disable Register */ + AT91_REG PIO_PPUER; /* Pull-up Enable Register */ + AT91_REG PIO_PPUSR; /* Pull-up Status Register */ + AT91_REG Reserved4[ 1 ]; /* */ + AT91_REG PIO_ASR; /* Select A Register */ + AT91_REG PIO_BSR; /* Select B Register */ + AT91_REG PIO_ABSR; /* AB Select Status Register */ + AT91_REG Reserved5[ 9 ]; /* */ + AT91_REG PIO_OWER; /* Output Write Enable Register */ + AT91_REG PIO_OWDR; /* Output Write Disable Register */ + AT91_REG PIO_OWSR; /* Output Write Status Register */ +} AT91S_PIO, * AT91PS_PIO; + + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Clock Generator Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_CKGR +{ + AT91_REG CKGR_MOR; /* Main Oscillator Register */ + AT91_REG CKGR_MCFR; /* Main Clock Frequency Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG CKGR_PLLR; /* PLL Register */ +} AT91S_CKGR, * AT91PS_CKGR; + +/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */ +#define AT91C_CKGR_MOSCEN ( ( unsigned int ) 0x1 << 0 ) /* (CKGR) Main Oscillator Enable */ +#define AT91C_CKGR_OSCBYPASS ( ( unsigned int ) 0x1 << 1 ) /* (CKGR) Main Oscillator Bypass */ +#define AT91C_CKGR_OSCOUNT ( ( unsigned int ) 0xFF << 8 ) /* (CKGR) Main Oscillator Start-up Time */ +/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */ +#define AT91C_CKGR_MAINF ( ( unsigned int ) 0xFFFF << 0 ) /* (CKGR) Main Clock Frequency */ +#define AT91C_CKGR_MAINRDY ( ( unsigned int ) 0x1 << 16 ) /* (CKGR) Main Clock Ready */ +/* -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- */ +#define AT91C_CKGR_DIV ( ( unsigned int ) 0xFF << 0 ) /* (CKGR) Divider Selected */ +#define AT91C_CKGR_DIV_0 ( ( unsigned int ) 0x0 ) /* (CKGR) Divider output is 0 */ +#define AT91C_CKGR_DIV_BYPASS ( ( unsigned int ) 0x1 ) /* (CKGR) Divider is bypassed */ +#define AT91C_CKGR_PLLCOUNT ( ( unsigned int ) 0x3F << 8 ) /* (CKGR) PLL Counter */ +#define AT91C_CKGR_OUT ( ( unsigned int ) 0x3 << 14 ) /* (CKGR) PLL Output Frequency Range */ +#define AT91C_CKGR_OUT_0 ( ( unsigned int ) 0x0 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_1 ( ( unsigned int ) 0x1 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_2 ( ( unsigned int ) 0x2 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_3 ( ( unsigned int ) 0x3 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_MUL ( ( unsigned int ) 0x7FF << 16 ) /* (CKGR) PLL Multiplier */ +#define AT91C_CKGR_USBDIV ( ( unsigned int ) 0x3 << 28 ) /* (CKGR) Divider for USB Clocks */ +#define AT91C_CKGR_USBDIV_0 ( ( unsigned int ) 0x0 << 28 ) /* (CKGR) Divider output is PLL clock output */ +#define AT91C_CKGR_USBDIV_1 ( ( unsigned int ) 0x1 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 2 */ +#define AT91C_CKGR_USBDIV_2 ( ( unsigned int ) 0x2 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 4 */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Power Management Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_PMC +{ + AT91_REG PMC_SCER; /* System Clock Enable Register */ + AT91_REG PMC_SCDR; /* System Clock Disable Register */ + AT91_REG PMC_SCSR; /* System Clock Status Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */ + AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */ + AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG PMC_MOR; /* Main Oscillator Register */ + AT91_REG PMC_MCFR; /* Main Clock Frequency Register */ + AT91_REG Reserved2[ 1 ]; /* */ + AT91_REG PMC_PLLR; /* PLL Register */ + AT91_REG PMC_MCKR; /* Master Clock Register */ + AT91_REG Reserved3[ 3 ]; /* */ + AT91_REG PMC_PCKR[ 4 ]; /* Programmable Clock Register */ + AT91_REG Reserved4[ 4 ]; /* */ + AT91_REG PMC_IER; /* Interrupt Enable Register */ + AT91_REG PMC_IDR; /* Interrupt Disable Register */ + AT91_REG PMC_SR; /* Status Register */ + AT91_REG PMC_IMR; /* Interrupt Mask Register */ +} AT91S_PMC, * AT91PS_PMC; + +/* -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- */ +#define AT91C_PMC_PCK ( ( unsigned int ) 0x1 << 0 ) /* (PMC) Processor Clock */ +#define AT91C_PMC_UDP ( ( unsigned int ) 0x1 << 7 ) /* (PMC) USB Device Port Clock */ +#define AT91C_PMC_PCK0 ( ( unsigned int ) 0x1 << 8 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK1 ( ( unsigned int ) 0x1 << 9 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK2 ( ( unsigned int ) 0x1 << 10 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK3 ( ( unsigned int ) 0x1 << 11 ) /* (PMC) Programmable Clock Output */ +/* -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- */ +/* -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- */ +/* -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- */ +/* -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- */ +/* -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- */ +/* -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */ +#define AT91C_PMC_CSS ( ( unsigned int ) 0x3 << 0 ) /* (PMC) Programmable Clock Selection */ +#define AT91C_PMC_CSS_SLOW_CLK ( ( unsigned int ) 0x0 ) /* (PMC) Slow Clock is selected */ +#define AT91C_PMC_CSS_MAIN_CLK ( ( unsigned int ) 0x1 ) /* (PMC) Main Clock is selected */ +#define AT91C_PMC_CSS_PLL_CLK ( ( unsigned int ) 0x3 ) /* (PMC) Clock from PLL is selected */ +#define AT91C_PMC_PRES ( ( unsigned int ) 0x7 << 2 ) /* (PMC) Programmable Clock Prescaler */ +#define AT91C_PMC_PRES_CLK ( ( unsigned int ) 0x0 << 2 ) /* (PMC) Selected clock */ +#define AT91C_PMC_PRES_CLK_2 ( ( unsigned int ) 0x1 << 2 ) /* (PMC) Selected clock divided by 2 */ +#define AT91C_PMC_PRES_CLK_4 ( ( unsigned int ) 0x2 << 2 ) /* (PMC) Selected clock divided by 4 */ +#define AT91C_PMC_PRES_CLK_8 ( ( unsigned int ) 0x3 << 2 ) /* (PMC) Selected clock divided by 8 */ +#define AT91C_PMC_PRES_CLK_16 ( ( unsigned int ) 0x4 << 2 ) /* (PMC) Selected clock divided by 16 */ +#define AT91C_PMC_PRES_CLK_32 ( ( unsigned int ) 0x5 << 2 ) /* (PMC) Selected clock divided by 32 */ +#define AT91C_PMC_PRES_CLK_64 ( ( unsigned int ) 0x6 << 2 ) /* (PMC) Selected clock divided by 64 */ +/* -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- */ +/* -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- */ +#define AT91C_PMC_MOSCS ( ( unsigned int ) 0x1 << 0 ) /* (PMC) MOSC Status/Enable/Disable/Mask */ +#define AT91C_PMC_LOCK ( ( unsigned int ) 0x1 << 2 ) /* (PMC) PLL Status/Enable/Disable/Mask */ +#define AT91C_PMC_MCKRDY ( ( unsigned int ) 0x1 << 3 ) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK0RDY ( ( unsigned int ) 0x1 << 8 ) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK1RDY ( ( unsigned int ) 0x1 << 9 ) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK2RDY ( ( unsigned int ) 0x1 << 10 ) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK3RDY ( ( unsigned int ) 0x1 << 11 ) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */ +/* -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */ +/* -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- */ +/* -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Reset Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_RSTC +{ + AT91_REG RSTC_RCR; /* Reset Control Register */ + AT91_REG RSTC_RSR; /* Reset Status Register */ + AT91_REG RSTC_RMR; /* Reset Mode Register */ +} AT91S_RSTC, * AT91PS_RSTC; + +/* -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- */ +#define AT91C_RSTC_PROCRST ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) Processor Reset */ +#define AT91C_RSTC_PERRST ( ( unsigned int ) 0x1 << 2 ) /* (RSTC) Peripheral Reset */ +#define AT91C_RSTC_EXTRST ( ( unsigned int ) 0x1 << 3 ) /* (RSTC) External Reset */ +#define AT91C_RSTC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (RSTC) Password */ +/* -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- */ +#define AT91C_RSTC_URSTS ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) User Reset Status */ +#define AT91C_RSTC_BODSTS ( ( unsigned int ) 0x1 << 1 ) /* (RSTC) Brownout Detection Status */ +#define AT91C_RSTC_RSTTYP ( ( unsigned int ) 0x7 << 8 ) /* (RSTC) Reset Type */ +#define AT91C_RSTC_RSTTYP_POWERUP ( ( unsigned int ) 0x0 << 8 ) /* (RSTC) Power-up Reset. VDDCORE rising. */ +#define AT91C_RSTC_RSTTYP_WAKEUP ( ( unsigned int ) 0x1 << 8 ) /* (RSTC) WakeUp Reset. VDDCORE rising. */ +#define AT91C_RSTC_RSTTYP_WATCHDOG ( ( unsigned int ) 0x2 << 8 ) /* (RSTC) Watchdog Reset. Watchdog overflow occurred. */ +#define AT91C_RSTC_RSTTYP_SOFTWARE ( ( unsigned int ) 0x3 << 8 ) /* (RSTC) Software Reset. Processor reset required by the software. */ +#define AT91C_RSTC_RSTTYP_USER ( ( unsigned int ) 0x4 << 8 ) /* (RSTC) User Reset. NRST pin detected low. */ +#define AT91C_RSTC_RSTTYP_BROWNOUT ( ( unsigned int ) 0x5 << 8 ) /* (RSTC) Brownout Reset occurred. */ +#define AT91C_RSTC_NRSTL ( ( unsigned int ) 0x1 << 16 ) /* (RSTC) NRST pin level */ +#define AT91C_RSTC_SRCMP ( ( unsigned int ) 0x1 << 17 ) /* (RSTC) Software Reset Command in Progress. */ +/* -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- */ +#define AT91C_RSTC_URSTEN ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) User Reset Enable */ +#define AT91C_RSTC_URSTIEN ( ( unsigned int ) 0x1 << 4 ) /* (RSTC) User Reset Interrupt Enable */ +#define AT91C_RSTC_ERSTL ( ( unsigned int ) 0xF << 8 ) /* (RSTC) User Reset Enable */ +#define AT91C_RSTC_BODIEN ( ( unsigned int ) 0x1 << 16 ) /* (RSTC) Brownout Detection Interrupt Enable */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_RTTC +{ + AT91_REG RTTC_RTMR; /* Real-time Mode Register */ + AT91_REG RTTC_RTAR; /* Real-time Alarm Register */ + AT91_REG RTTC_RTVR; /* Real-time Value Register */ + AT91_REG RTTC_RTSR; /* Real-time Status Register */ +} AT91S_RTTC, * AT91PS_RTTC; + +/* -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- */ +#define AT91C_RTTC_RTPRES ( ( unsigned int ) 0xFFFF << 0 ) /* (RTTC) Real-time Timer Prescaler Value */ +#define AT91C_RTTC_ALMIEN ( ( unsigned int ) 0x1 << 16 ) /* (RTTC) Alarm Interrupt Enable */ +#define AT91C_RTTC_RTTINCIEN ( ( unsigned int ) 0x1 << 17 ) /* (RTTC) Real Time Timer Increment Interrupt Enable */ +#define AT91C_RTTC_RTTRST ( ( unsigned int ) 0x1 << 18 ) /* (RTTC) Real Time Timer Restart */ +/* -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- */ +#define AT91C_RTTC_ALMV ( ( unsigned int ) 0x0 << 0 ) /* (RTTC) Alarm Value */ +/* -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- */ +#define AT91C_RTTC_CRTV ( ( unsigned int ) 0x0 << 0 ) /* (RTTC) Current Real-time Value */ +/* -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- */ +#define AT91C_RTTC_ALMS ( ( unsigned int ) 0x1 << 0 ) /* (RTTC) Real-time Alarm Status */ +#define AT91C_RTTC_RTTINC ( ( unsigned int ) 0x1 << 1 ) /* (RTTC) Real-time Timer Increment */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_PITC +{ + AT91_REG PITC_PIMR; /* Period Interval Mode Register */ + AT91_REG PITC_PISR; /* Period Interval Status Register */ + AT91_REG PITC_PIVR; /* Period Interval Value Register */ + AT91_REG PITC_PIIR; /* Period Interval Image Register */ +} AT91S_PITC, * AT91PS_PITC; + +/* -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- */ +#define AT91C_PITC_PIV ( ( unsigned int ) 0xFFFFF << 0 ) /* (PITC) Periodic Interval Value */ +#define AT91C_PITC_PITEN ( ( unsigned int ) 0x1 << 24 ) /* (PITC) Periodic Interval Timer Enabled */ +#define AT91C_PITC_PITIEN ( ( unsigned int ) 0x1 << 25 ) /* (PITC) Periodic Interval Timer Interrupt Enable */ +/* -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- */ +#define AT91C_PITC_PITS ( ( unsigned int ) 0x1 << 0 ) /* (PITC) Periodic Interval Timer Status */ +/* -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- */ +#define AT91C_PITC_CPIV ( ( unsigned int ) 0xFFFFF << 0 ) /* (PITC) Current Periodic Interval Value */ +#define AT91C_PITC_PICNT ( ( unsigned int ) 0xFFF << 20 ) /* (PITC) Periodic Interval Counter */ +/* -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_WDTC +{ + AT91_REG WDTC_WDCR; /* Watchdog Control Register */ + AT91_REG WDTC_WDMR; /* Watchdog Mode Register */ + AT91_REG WDTC_WDSR; /* Watchdog Status Register */ +} AT91S_WDTC, * AT91PS_WDTC; + +/* -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- */ +#define AT91C_WDTC_WDRSTT ( ( unsigned int ) 0x1 << 0 ) /* (WDTC) Watchdog Restart */ +#define AT91C_WDTC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (WDTC) Watchdog KEY Password */ +/* -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */ +#define AT91C_WDTC_WDV ( ( unsigned int ) 0xFFF << 0 ) /* (WDTC) Watchdog Timer Restart */ +#define AT91C_WDTC_WDFIEN ( ( unsigned int ) 0x1 << 12 ) /* (WDTC) Watchdog Fault Interrupt Enable */ +#define AT91C_WDTC_WDRSTEN ( ( unsigned int ) 0x1 << 13 ) /* (WDTC) Watchdog Reset Enable */ +#define AT91C_WDTC_WDRPROC ( ( unsigned int ) 0x1 << 14 ) /* (WDTC) Watchdog Timer Restart */ +#define AT91C_WDTC_WDDIS ( ( unsigned int ) 0x1 << 15 ) /* (WDTC) Watchdog Disable */ +#define AT91C_WDTC_WDD ( ( unsigned int ) 0xFFF << 16 ) /* (WDTC) Watchdog Delta Value */ +#define AT91C_WDTC_WDDBGHLT ( ( unsigned int ) 0x1 << 28 ) /* (WDTC) Watchdog Debug Halt */ +#define AT91C_WDTC_WDIDLEHLT ( ( unsigned int ) 0x1 << 29 ) /* (WDTC) Watchdog Idle Halt */ +/* -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- */ +#define AT91C_WDTC_WDUNF ( ( unsigned int ) 0x1 << 0 ) /* (WDTC) Watchdog Underflow */ +#define AT91C_WDTC_WDERR ( ( unsigned int ) 0x1 << 1 ) /* (WDTC) Watchdog Error */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_VREG +{ + AT91_REG VREG_MR; /* Voltage Regulator Mode Register */ +} AT91S_VREG, * AT91PS_VREG; + +/* -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- */ +#define AT91C_VREG_PSTDBY ( ( unsigned int ) 0x1 << 0 ) /* (VREG) Voltage Regulator Power Standby Mode */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Memory Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_MC +{ + AT91_REG MC_RCR; /* MC Remap Control Register */ + AT91_REG MC_ASR; /* MC Abort Status Register */ + AT91_REG MC_AASR; /* MC Abort Address Status Register */ + AT91_REG Reserved0[ 21 ]; /* */ + AT91_REG MC_FMR; /* MC Flash Mode Register */ + AT91_REG MC_FCR; /* MC Flash Command Register */ + AT91_REG MC_FSR; /* MC Flash Status Register */ +} AT91S_MC, * AT91PS_MC; + +/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */ +#define AT91C_MC_RCB ( ( unsigned int ) 0x1 << 0 ) /* (MC) Remap Command Bit */ +/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */ +#define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Address Abort Status */ +#define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Address Abort Status */ +#define AT91C_MC_ABTSZ ( ( unsigned int ) 0x3 << 8 ) /* (MC) Abort Size Status */ +#define AT91C_MC_ABTSZ_BYTE ( ( unsigned int ) 0x0 << 8 ) /* (MC) Byte */ +#define AT91C_MC_ABTSZ_HWORD ( ( unsigned int ) 0x1 << 8 ) /* (MC) Half-word */ +#define AT91C_MC_ABTSZ_WORD ( ( unsigned int ) 0x2 << 8 ) /* (MC) Word */ +#define AT91C_MC_ABTTYP ( ( unsigned int ) 0x3 << 10 ) /* (MC) Abort Type Status */ +#define AT91C_MC_ABTTYP_DATAR ( ( unsigned int ) 0x0 << 10 ) /* (MC) Data Read */ +#define AT91C_MC_ABTTYP_DATAW ( ( unsigned int ) 0x1 << 10 ) /* (MC) Data Write */ +#define AT91C_MC_ABTTYP_FETCH ( ( unsigned int ) 0x2 << 10 ) /* (MC) Code Fetch */ +#define AT91C_MC_MST0 ( ( unsigned int ) 0x1 << 16 ) /* (MC) Master 0 Abort Source */ +#define AT91C_MC_MST1 ( ( unsigned int ) 0x1 << 17 ) /* (MC) Master 1 Abort Source */ +#define AT91C_MC_SVMST0 ( ( unsigned int ) 0x1 << 24 ) /* (MC) Saved Master 0 Abort Source */ +#define AT91C_MC_SVMST1 ( ( unsigned int ) 0x1 << 25 ) /* (MC) Saved Master 1 Abort Source */ +/* -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- */ +#define AT91C_MC_FRDY ( ( unsigned int ) 0x1 << 0 ) /* (MC) Flash Ready */ +#define AT91C_MC_LOCKE ( ( unsigned int ) 0x1 << 2 ) /* (MC) Lock Error */ +#define AT91C_MC_PROGE ( ( unsigned int ) 0x1 << 3 ) /* (MC) Programming Error */ +#define AT91C_MC_NEBP ( ( unsigned int ) 0x1 << 7 ) /* (MC) No Erase Before Programming */ +#define AT91C_MC_FWS ( ( unsigned int ) 0x3 << 8 ) /* (MC) Flash Wait State */ +#define AT91C_MC_FWS_0FWS ( ( unsigned int ) 0x0 << 8 ) /* (MC) 1 cycle for Read, 2 for Write operations */ +#define AT91C_MC_FWS_1FWS ( ( unsigned int ) 0x1 << 8 ) /* (MC) 2 cycles for Read, 3 for Write operations */ +#define AT91C_MC_FWS_2FWS ( ( unsigned int ) 0x2 << 8 ) /* (MC) 3 cycles for Read, 4 for Write operations */ +#define AT91C_MC_FWS_3FWS ( ( unsigned int ) 0x3 << 8 ) /* (MC) 4 cycles for Read, 4 for Write operations */ +#define AT91C_MC_FMCN ( ( unsigned int ) 0xFF << 16 ) /* (MC) Flash Microsecond Cycle Number */ +/* -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- */ +#define AT91C_MC_FCMD ( ( unsigned int ) 0xF << 0 ) /* (MC) Flash Command */ +#define AT91C_MC_FCMD_START_PROG ( ( unsigned int ) 0x1 ) /* (MC) Starts the programming of th epage specified by PAGEN. */ +#define AT91C_MC_FCMD_LOCK ( ( unsigned int ) 0x2 ) /* (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */ +#define AT91C_MC_FCMD_PROG_AND_LOCK ( ( unsigned int ) 0x3 ) /* (MC) The lock sequence automatically happens after the programming sequence is completed. */ +#define AT91C_MC_FCMD_UNLOCK ( ( unsigned int ) 0x4 ) /* (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */ +#define AT91C_MC_FCMD_ERASE_ALL ( ( unsigned int ) 0x8 ) /* (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. */ +#define AT91C_MC_FCMD_SET_GP_NVM ( ( unsigned int ) 0xB ) /* (MC) Set General Purpose NVM bits. */ +#define AT91C_MC_FCMD_CLR_GP_NVM ( ( unsigned int ) 0xD ) /* (MC) Clear General Purpose NVM bits. */ +#define AT91C_MC_FCMD_SET_SECURITY ( ( unsigned int ) 0xF ) /* (MC) Set Security Bit. */ +#define AT91C_MC_PAGEN ( ( unsigned int ) 0x3FF << 8 ) /* (MC) Page Number */ +#define AT91C_MC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (MC) Writing Protect Key */ +/* -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- */ +#define AT91C_MC_SECURITY ( ( unsigned int ) 0x1 << 4 ) /* (MC) Security Bit Status */ +#define AT91C_MC_GPNVM0 ( ( unsigned int ) 0x1 << 8 ) /* (MC) Sector 0 Lock Status */ +#define AT91C_MC_GPNVM1 ( ( unsigned int ) 0x1 << 9 ) /* (MC) Sector 1 Lock Status */ +#define AT91C_MC_GPNVM2 ( ( unsigned int ) 0x1 << 10 ) /* (MC) Sector 2 Lock Status */ +#define AT91C_MC_GPNVM3 ( ( unsigned int ) 0x1 << 11 ) /* (MC) Sector 3 Lock Status */ +#define AT91C_MC_GPNVM4 ( ( unsigned int ) 0x1 << 12 ) /* (MC) Sector 4 Lock Status */ +#define AT91C_MC_GPNVM5 ( ( unsigned int ) 0x1 << 13 ) /* (MC) Sector 5 Lock Status */ +#define AT91C_MC_GPNVM6 ( ( unsigned int ) 0x1 << 14 ) /* (MC) Sector 6 Lock Status */ +#define AT91C_MC_GPNVM7 ( ( unsigned int ) 0x1 << 15 ) /* (MC) Sector 7 Lock Status */ +#define AT91C_MC_LOCKS0 ( ( unsigned int ) 0x1 << 16 ) /* (MC) Sector 0 Lock Status */ +#define AT91C_MC_LOCKS1 ( ( unsigned int ) 0x1 << 17 ) /* (MC) Sector 1 Lock Status */ +#define AT91C_MC_LOCKS2 ( ( unsigned int ) 0x1 << 18 ) /* (MC) Sector 2 Lock Status */ +#define AT91C_MC_LOCKS3 ( ( unsigned int ) 0x1 << 19 ) /* (MC) Sector 3 Lock Status */ +#define AT91C_MC_LOCKS4 ( ( unsigned int ) 0x1 << 20 ) /* (MC) Sector 4 Lock Status */ +#define AT91C_MC_LOCKS5 ( ( unsigned int ) 0x1 << 21 ) /* (MC) Sector 5 Lock Status */ +#define AT91C_MC_LOCKS6 ( ( unsigned int ) 0x1 << 22 ) /* (MC) Sector 6 Lock Status */ +#define AT91C_MC_LOCKS7 ( ( unsigned int ) 0x1 << 23 ) /* (MC) Sector 7 Lock Status */ +#define AT91C_MC_LOCKS8 ( ( unsigned int ) 0x1 << 24 ) /* (MC) Sector 8 Lock Status */ +#define AT91C_MC_LOCKS9 ( ( unsigned int ) 0x1 << 25 ) /* (MC) Sector 9 Lock Status */ +#define AT91C_MC_LOCKS10 ( ( unsigned int ) 0x1 << 26 ) /* (MC) Sector 10 Lock Status */ +#define AT91C_MC_LOCKS11 ( ( unsigned int ) 0x1 << 27 ) /* (MC) Sector 11 Lock Status */ +#define AT91C_MC_LOCKS12 ( ( unsigned int ) 0x1 << 28 ) /* (MC) Sector 12 Lock Status */ +#define AT91C_MC_LOCKS13 ( ( unsigned int ) 0x1 << 29 ) /* (MC) Sector 13 Lock Status */ +#define AT91C_MC_LOCKS14 ( ( unsigned int ) 0x1 << 30 ) /* (MC) Sector 14 Lock Status */ +#define AT91C_MC_LOCKS15 ( ( unsigned int ) 0x1 << 31 ) /* (MC) Sector 15 Lock Status */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_SPI +{ + AT91_REG SPI_CR; /* Control Register */ + AT91_REG SPI_MR; /* Mode Register */ + AT91_REG SPI_RDR; /* Receive Data Register */ + AT91_REG SPI_TDR; /* Transmit Data Register */ + AT91_REG SPI_SR; /* Status Register */ + AT91_REG SPI_IER; /* Interrupt Enable Register */ + AT91_REG SPI_IDR; /* Interrupt Disable Register */ + AT91_REG SPI_IMR; /* Interrupt Mask Register */ + AT91_REG Reserved0[ 4 ]; /* */ + AT91_REG SPI_CSR[ 4 ]; /* Chip Select Register */ + AT91_REG Reserved1[ 48 ]; /* */ + AT91_REG SPI_RPR; /* Receive Pointer Register */ + AT91_REG SPI_RCR; /* Receive Counter Register */ + AT91_REG SPI_TPR; /* Transmit Pointer Register */ + AT91_REG SPI_TCR; /* Transmit Counter Register */ + AT91_REG SPI_RNPR; /* Receive Next Pointer Register */ + AT91_REG SPI_RNCR; /* Receive Next Counter Register */ + AT91_REG SPI_TNPR; /* Transmit Next Pointer Register */ + AT91_REG SPI_TNCR; /* Transmit Next Counter Register */ + AT91_REG SPI_PTCR; /* PDC Transfer Control Register */ + AT91_REG SPI_PTSR; /* PDC Transfer Status Register */ +} AT91S_SPI, * AT91PS_SPI; + +/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */ +#define AT91C_SPI_SPIEN ( ( unsigned int ) 0x1 << 0 ) /* (SPI) SPI Enable */ +#define AT91C_SPI_SPIDIS ( ( unsigned int ) 0x1 << 1 ) /* (SPI) SPI Disable */ +#define AT91C_SPI_SWRST ( ( unsigned int ) 0x1 << 7 ) /* (SPI) SPI Software reset */ +#define AT91C_SPI_LASTXFER ( ( unsigned int ) 0x1 << 24 ) /* (SPI) SPI Last Transfer */ +/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */ +#define AT91C_SPI_MSTR ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Master/Slave Mode */ +#define AT91C_SPI_PS ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Peripheral Select */ +#define AT91C_SPI_PS_FIXED ( ( unsigned int ) 0x0 << 1 ) /* (SPI) Fixed Peripheral Select */ +#define AT91C_SPI_PS_VARIABLE ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Variable Peripheral Select */ +#define AT91C_SPI_PCSDEC ( ( unsigned int ) 0x1 << 2 ) /* (SPI) Chip Select Decode */ +#define AT91C_SPI_FDIV ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Clock Selection */ +#define AT91C_SPI_MODFDIS ( ( unsigned int ) 0x1 << 4 ) /* (SPI) Mode Fault Detection */ +#define AT91C_SPI_LLB ( ( unsigned int ) 0x1 << 7 ) /* (SPI) Clock Selection */ +#define AT91C_SPI_PCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select */ +#define AT91C_SPI_DLYBCS ( ( unsigned int ) 0xFF << 24 ) /* (SPI) Delay Between Chip Selects */ +/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */ +#define AT91C_SPI_RD ( ( unsigned int ) 0xFFFF << 0 ) /* (SPI) Receive Data */ +#define AT91C_SPI_RPCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */ +/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */ +#define AT91C_SPI_TD ( ( unsigned int ) 0xFFFF << 0 ) /* (SPI) Transmit Data */ +#define AT91C_SPI_TPCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */ +/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ +#define AT91C_SPI_RDRF ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Receive Data Register Full */ +#define AT91C_SPI_TDRE ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Transmit Data Register Empty */ +#define AT91C_SPI_MODF ( ( unsigned int ) 0x1 << 2 ) /* (SPI) Mode Fault Error */ +#define AT91C_SPI_OVRES ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Overrun Error Status */ +#define AT91C_SPI_ENDRX ( ( unsigned int ) 0x1 << 4 ) /* (SPI) End of Receiver Transfer */ +#define AT91C_SPI_ENDTX ( ( unsigned int ) 0x1 << 5 ) /* (SPI) End of Receiver Transfer */ +#define AT91C_SPI_RXBUFF ( ( unsigned int ) 0x1 << 6 ) /* (SPI) RXBUFF Interrupt */ +#define AT91C_SPI_TXBUFE ( ( unsigned int ) 0x1 << 7 ) /* (SPI) TXBUFE Interrupt */ +#define AT91C_SPI_NSSR ( ( unsigned int ) 0x1 << 8 ) /* (SPI) NSSR Interrupt */ +#define AT91C_SPI_TXEMPTY ( ( unsigned int ) 0x1 << 9 ) /* (SPI) TXEMPTY Interrupt */ +#define AT91C_SPI_SPIENS ( ( unsigned int ) 0x1 << 16 ) /* (SPI) Enable Status */ +/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ +/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ +/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */ +/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */ +#define AT91C_SPI_CPOL ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Clock Polarity */ +#define AT91C_SPI_NCPHA ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Clock Phase */ +#define AT91C_SPI_CSAAT ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Chip Select Active After Transfer */ +#define AT91C_SPI_BITS ( ( unsigned int ) 0xF << 4 ) /* (SPI) Bits Per Transfer */ +#define AT91C_SPI_BITS_8 ( ( unsigned int ) 0x0 << 4 ) /* (SPI) 8 Bits Per transfer */ +#define AT91C_SPI_BITS_9 ( ( unsigned int ) 0x1 << 4 ) /* (SPI) 9 Bits Per transfer */ +#define AT91C_SPI_BITS_10 ( ( unsigned int ) 0x2 << 4 ) /* (SPI) 10 Bits Per transfer */ +#define AT91C_SPI_BITS_11 ( ( unsigned int ) 0x3 << 4 ) /* (SPI) 11 Bits Per transfer */ +#define AT91C_SPI_BITS_12 ( ( unsigned int ) 0x4 << 4 ) /* (SPI) 12 Bits Per transfer */ +#define AT91C_SPI_BITS_13 ( ( unsigned int ) 0x5 << 4 ) /* (SPI) 13 Bits Per transfer */ +#define AT91C_SPI_BITS_14 ( ( unsigned int ) 0x6 << 4 ) /* (SPI) 14 Bits Per transfer */ +#define AT91C_SPI_BITS_15 ( ( unsigned int ) 0x7 << 4 ) /* (SPI) 15 Bits Per transfer */ +#define AT91C_SPI_BITS_16 ( ( unsigned int ) 0x8 << 4 ) /* (SPI) 16 Bits Per transfer */ +#define AT91C_SPI_SCBR ( ( unsigned int ) 0xFF << 8 ) /* (SPI) Serial Clock Baud Rate */ +#define AT91C_SPI_DLYBS ( ( unsigned int ) 0xFF << 16 ) /* (SPI) Delay Before SPCK */ +#define AT91C_SPI_DLYBCT ( ( unsigned int ) 0xFF << 24 ) /* (SPI) Delay Between Consecutive Transfers */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Usart */ +/* ***************************************************************************** */ +typedef struct _AT91S_USART +{ + AT91_REG US_CR; /* Control Register */ + AT91_REG US_MR; /* Mode Register */ + AT91_REG US_IER; /* Interrupt Enable Register */ + AT91_REG US_IDR; /* Interrupt Disable Register */ + AT91_REG US_IMR; /* Interrupt Mask Register */ + AT91_REG US_CSR; /* Channel Status Register */ + AT91_REG US_RHR; /* Receiver Holding Register */ + AT91_REG US_THR; /* Transmitter Holding Register */ + AT91_REG US_BRGR; /* Baud Rate Generator Register */ + AT91_REG US_RTOR; /* Receiver Time-out Register */ + AT91_REG US_TTGR; /* Transmitter Time-guard Register */ + AT91_REG Reserved0[ 5 ]; /* */ + AT91_REG US_FIDI; /* FI_DI_Ratio Register */ + AT91_REG US_NER; /* Nb Errors Register */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG US_IF; /* IRDA_FILTER Register */ + AT91_REG Reserved2[ 44 ]; /* */ + AT91_REG US_RPR; /* Receive Pointer Register */ + AT91_REG US_RCR; /* Receive Counter Register */ + AT91_REG US_TPR; /* Transmit Pointer Register */ + AT91_REG US_TCR; /* Transmit Counter Register */ + AT91_REG US_RNPR; /* Receive Next Pointer Register */ + AT91_REG US_RNCR; /* Receive Next Counter Register */ + AT91_REG US_TNPR; /* Transmit Next Pointer Register */ + AT91_REG US_TNCR; /* Transmit Next Counter Register */ + AT91_REG US_PTCR; /* PDC Transfer Control Register */ + AT91_REG US_PTSR; /* PDC Transfer Status Register */ +} AT91S_USART, * AT91PS_USART; + +/* -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- */ +#define AT91C_US_STTBRK ( ( unsigned int ) 0x1 << 9 ) /* (USART) Start Break */ +#define AT91C_US_STPBRK ( ( unsigned int ) 0x1 << 10 ) /* (USART) Stop Break */ +#define AT91C_US_STTTO ( ( unsigned int ) 0x1 << 11 ) /* (USART) Start Time-out */ +#define AT91C_US_SENDA ( ( unsigned int ) 0x1 << 12 ) /* (USART) Send Address */ +#define AT91C_US_RSTIT ( ( unsigned int ) 0x1 << 13 ) /* (USART) Reset Iterations */ +#define AT91C_US_RSTNACK ( ( unsigned int ) 0x1 << 14 ) /* (USART) Reset Non Acknowledge */ +#define AT91C_US_RETTO ( ( unsigned int ) 0x1 << 15 ) /* (USART) Rearm Time-out */ +#define AT91C_US_DTREN ( ( unsigned int ) 0x1 << 16 ) /* (USART) Data Terminal ready Enable */ +#define AT91C_US_DTRDIS ( ( unsigned int ) 0x1 << 17 ) /* (USART) Data Terminal ready Disable */ +#define AT91C_US_RTSEN ( ( unsigned int ) 0x1 << 18 ) /* (USART) Request to Send enable */ +#define AT91C_US_RTSDIS ( ( unsigned int ) 0x1 << 19 ) /* (USART) Request to Send Disable */ +/* -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- */ +#define AT91C_US_USMODE ( ( unsigned int ) 0xF << 0 ) /* (USART) Usart mode */ +#define AT91C_US_USMODE_NORMAL ( ( unsigned int ) 0x0 ) /* (USART) Normal */ +#define AT91C_US_USMODE_RS485 ( ( unsigned int ) 0x1 ) /* (USART) RS485 */ +#define AT91C_US_USMODE_HWHSH ( ( unsigned int ) 0x2 ) /* (USART) Hardware Handshaking */ +#define AT91C_US_USMODE_MODEM ( ( unsigned int ) 0x3 ) /* (USART) Modem */ +#define AT91C_US_USMODE_ISO7816_0 ( ( unsigned int ) 0x4 ) /* (USART) ISO7816 protocol: T = 0 */ +#define AT91C_US_USMODE_ISO7816_1 ( ( unsigned int ) 0x6 ) /* (USART) ISO7816 protocol: T = 1 */ +#define AT91C_US_USMODE_IRDA ( ( unsigned int ) 0x8 ) /* (USART) IrDA */ +#define AT91C_US_USMODE_SWHSH ( ( unsigned int ) 0xC ) /* (USART) Software Handshaking */ +#define AT91C_US_CLKS ( ( unsigned int ) 0x3 << 4 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */ +#define AT91C_US_CLKS_CLOCK ( ( unsigned int ) 0x0 << 4 ) /* (USART) Clock */ +#define AT91C_US_CLKS_FDIV1 ( ( unsigned int ) 0x1 << 4 ) /* (USART) fdiv1 */ +#define AT91C_US_CLKS_SLOW ( ( unsigned int ) 0x2 << 4 ) /* (USART) slow_clock (ARM) */ +#define AT91C_US_CLKS_EXT ( ( unsigned int ) 0x3 << 4 ) /* (USART) External (SCK) */ +#define AT91C_US_CHRL ( ( unsigned int ) 0x3 << 6 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */ +#define AT91C_US_CHRL_5_BITS ( ( unsigned int ) 0x0 << 6 ) /* (USART) Character Length: 5 bits */ +#define AT91C_US_CHRL_6_BITS ( ( unsigned int ) 0x1 << 6 ) /* (USART) Character Length: 6 bits */ +#define AT91C_US_CHRL_7_BITS ( ( unsigned int ) 0x2 << 6 ) /* (USART) Character Length: 7 bits */ +#define AT91C_US_CHRL_8_BITS ( ( unsigned int ) 0x3 << 6 ) /* (USART) Character Length: 8 bits */ +#define AT91C_US_SYNC ( ( unsigned int ) 0x1 << 8 ) /* (USART) Synchronous Mode Select */ +#define AT91C_US_NBSTOP ( ( unsigned int ) 0x3 << 12 ) /* (USART) Number of Stop bits */ +#define AT91C_US_NBSTOP_1_BIT ( ( unsigned int ) 0x0 << 12 ) /* (USART) 1 stop bit */ +#define AT91C_US_NBSTOP_15_BIT ( ( unsigned int ) 0x1 << 12 ) /* (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */ +#define AT91C_US_NBSTOP_2_BIT ( ( unsigned int ) 0x2 << 12 ) /* (USART) 2 stop bits */ +#define AT91C_US_MSBF ( ( unsigned int ) 0x1 << 16 ) /* (USART) Bit Order */ +#define AT91C_US_MODE9 ( ( unsigned int ) 0x1 << 17 ) /* (USART) 9-bit Character length */ +#define AT91C_US_CKLO ( ( unsigned int ) 0x1 << 18 ) /* (USART) Clock Output Select */ +#define AT91C_US_OVER ( ( unsigned int ) 0x1 << 19 ) /* (USART) Over Sampling Mode */ +#define AT91C_US_INACK ( ( unsigned int ) 0x1 << 20 ) /* (USART) Inhibit Non Acknowledge */ +#define AT91C_US_DSNACK ( ( unsigned int ) 0x1 << 21 ) /* (USART) Disable Successive NACK */ +#define AT91C_US_MAX_ITER ( ( unsigned int ) 0x1 << 24 ) /* (USART) Number of Repetitions */ +#define AT91C_US_FILTER ( ( unsigned int ) 0x1 << 28 ) /* (USART) Receive Line Filter */ +/* -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ +#define AT91C_US_RXBRK ( ( unsigned int ) 0x1 << 2 ) /* (USART) Break Received/End of Break */ +#define AT91C_US_TIMEOUT ( ( unsigned int ) 0x1 << 8 ) /* (USART) Receiver Time-out */ +#define AT91C_US_ITERATION ( ( unsigned int ) 0x1 << 10 ) /* (USART) Max number of Repetitions Reached */ +#define AT91C_US_NACK ( ( unsigned int ) 0x1 << 13 ) /* (USART) Non Acknowledge */ +#define AT91C_US_RIIC ( ( unsigned int ) 0x1 << 16 ) /* (USART) Ring INdicator Input Change Flag */ +#define AT91C_US_DSRIC ( ( unsigned int ) 0x1 << 17 ) /* (USART) Data Set Ready Input Change Flag */ +#define AT91C_US_DCDIC ( ( unsigned int ) 0x1 << 18 ) /* (USART) Data Carrier Flag */ +#define AT91C_US_CTSIC ( ( unsigned int ) 0x1 << 19 ) /* (USART) Clear To Send Input Change Flag */ +/* -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- */ +/* -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- */ +/* -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- */ +#define AT91C_US_RI ( ( unsigned int ) 0x1 << 20 ) /* (USART) Image of RI Input */ +#define AT91C_US_DSR ( ( unsigned int ) 0x1 << 21 ) /* (USART) Image of DSR Input */ +#define AT91C_US_DCD ( ( unsigned int ) 0x1 << 22 ) /* (USART) Image of DCD Input */ +#define AT91C_US_CTS ( ( unsigned int ) 0x1 << 23 ) /* (USART) Image of CTS Input */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_SSC +{ + AT91_REG SSC_CR; /* Control Register */ + AT91_REG SSC_CMR; /* Clock Mode Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG SSC_RCMR; /* Receive Clock ModeRegister */ + AT91_REG SSC_RFMR; /* Receive Frame Mode Register */ + AT91_REG SSC_TCMR; /* Transmit Clock Mode Register */ + AT91_REG SSC_TFMR; /* Transmit Frame Mode Register */ + AT91_REG SSC_RHR; /* Receive Holding Register */ + AT91_REG SSC_THR; /* Transmit Holding Register */ + AT91_REG Reserved1[ 2 ]; /* */ + AT91_REG SSC_RSHR; /* Receive Sync Holding Register */ + AT91_REG SSC_TSHR; /* Transmit Sync Holding Register */ + AT91_REG Reserved2[ 2 ]; /* */ + AT91_REG SSC_SR; /* Status Register */ + AT91_REG SSC_IER; /* Interrupt Enable Register */ + AT91_REG SSC_IDR; /* Interrupt Disable Register */ + AT91_REG SSC_IMR; /* Interrupt Mask Register */ + AT91_REG Reserved3[ 44 ]; /* */ + AT91_REG SSC_RPR; /* Receive Pointer Register */ + AT91_REG SSC_RCR; /* Receive Counter Register */ + AT91_REG SSC_TPR; /* Transmit Pointer Register */ + AT91_REG SSC_TCR; /* Transmit Counter Register */ + AT91_REG SSC_RNPR; /* Receive Next Pointer Register */ + AT91_REG SSC_RNCR; /* Receive Next Counter Register */ + AT91_REG SSC_TNPR; /* Transmit Next Pointer Register */ + AT91_REG SSC_TNCR; /* Transmit Next Counter Register */ + AT91_REG SSC_PTCR; /* PDC Transfer Control Register */ + AT91_REG SSC_PTSR; /* PDC Transfer Status Register */ +} AT91S_SSC, * AT91PS_SSC; + +/* -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- */ +#define AT91C_SSC_RXEN ( ( unsigned int ) 0x1 << 0 ) /* (SSC) Receive Enable */ +#define AT91C_SSC_RXDIS ( ( unsigned int ) 0x1 << 1 ) /* (SSC) Receive Disable */ +#define AT91C_SSC_TXEN ( ( unsigned int ) 0x1 << 8 ) /* (SSC) Transmit Enable */ +#define AT91C_SSC_TXDIS ( ( unsigned int ) 0x1 << 9 ) /* (SSC) Transmit Disable */ +#define AT91C_SSC_SWRST ( ( unsigned int ) 0x1 << 15 ) /* (SSC) Software Reset */ +/* -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- */ +#define AT91C_SSC_CKS ( ( unsigned int ) 0x3 << 0 ) /* (SSC) Receive/Transmit Clock Selection */ +#define AT91C_SSC_CKS_DIV ( ( unsigned int ) 0x0 ) /* (SSC) Divided Clock */ +#define AT91C_SSC_CKS_TK ( ( unsigned int ) 0x1 ) /* (SSC) TK Clock signal */ +#define AT91C_SSC_CKS_RK ( ( unsigned int ) 0x2 ) /* (SSC) RK pin */ +#define AT91C_SSC_CKO ( ( unsigned int ) 0x7 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode Selection */ +#define AT91C_SSC_CKO_NONE ( ( unsigned int ) 0x0 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only */ +#define AT91C_SSC_CKO_CONTINUOUS ( ( unsigned int ) 0x1 << 2 ) /* (SSC) Continuous Receive/Transmit Clock RK pin: Output */ +#define AT91C_SSC_CKO_DATA_TX ( ( unsigned int ) 0x2 << 2 ) /* (SSC) Receive/Transmit Clock only during data transfers RK pin: Output */ +#define AT91C_SSC_CKI ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Receive/Transmit Clock Inversion */ +#define AT91C_SSC_START ( ( unsigned int ) 0xF << 8 ) /* (SSC) Receive/Transmit Start Selection */ +#define AT91C_SSC_START_CONTINUOUS ( ( unsigned int ) 0x0 << 8 ) /* (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */ +#define AT91C_SSC_START_TX ( ( unsigned int ) 0x1 << 8 ) /* (SSC) Transmit/Receive start */ +#define AT91C_SSC_START_LOW_RF ( ( unsigned int ) 0x2 << 8 ) /* (SSC) Detection of a low level on RF input */ +#define AT91C_SSC_START_HIGH_RF ( ( unsigned int ) 0x3 << 8 ) /* (SSC) Detection of a high level on RF input */ +#define AT91C_SSC_START_FALL_RF ( ( unsigned int ) 0x4 << 8 ) /* (SSC) Detection of a falling edge on RF input */ +#define AT91C_SSC_START_RISE_RF ( ( unsigned int ) 0x5 << 8 ) /* (SSC) Detection of a rising edge on RF input */ +#define AT91C_SSC_START_LEVEL_RF ( ( unsigned int ) 0x6 << 8 ) /* (SSC) Detection of any level change on RF input */ +#define AT91C_SSC_START_EDGE_RF ( ( unsigned int ) 0x7 << 8 ) /* (SSC) Detection of any edge on RF input */ +#define AT91C_SSC_START_0 ( ( unsigned int ) 0x8 << 8 ) /* (SSC) Compare 0 */ +#define AT91C_SSC_STTDLY ( ( unsigned int ) 0xFF << 16 ) /* (SSC) Receive/Transmit Start Delay */ +#define AT91C_SSC_PERIOD ( ( unsigned int ) 0xFF << 24 ) /* (SSC) Receive/Transmit Period Divider Selection */ +/* -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- */ +#define AT91C_SSC_DATLEN ( ( unsigned int ) 0x1F << 0 ) /* (SSC) Data Length */ +#define AT91C_SSC_LOOP ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Loop Mode */ +#define AT91C_SSC_MSBF ( ( unsigned int ) 0x1 << 7 ) /* (SSC) Most Significant Bit First */ +#define AT91C_SSC_DATNB ( ( unsigned int ) 0xF << 8 ) /* (SSC) Data Number per Frame */ +#define AT91C_SSC_FSLEN ( ( unsigned int ) 0xF << 16 ) /* (SSC) Receive/Transmit Frame Sync length */ +#define AT91C_SSC_FSOS ( ( unsigned int ) 0x7 << 20 ) /* (SSC) Receive/Transmit Frame Sync Output Selection */ +#define AT91C_SSC_FSOS_NONE ( ( unsigned int ) 0x0 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only */ +#define AT91C_SSC_FSOS_NEGATIVE ( ( unsigned int ) 0x1 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse */ +#define AT91C_SSC_FSOS_POSITIVE ( ( unsigned int ) 0x2 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse */ +#define AT91C_SSC_FSOS_LOW ( ( unsigned int ) 0x3 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer */ +#define AT91C_SSC_FSOS_HIGH ( ( unsigned int ) 0x4 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer */ +#define AT91C_SSC_FSOS_TOGGLE ( ( unsigned int ) 0x5 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer */ +#define AT91C_SSC_FSEDGE ( ( unsigned int ) 0x1 << 24 ) /* (SSC) Frame Sync Edge Detection */ +/* -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- */ +/* -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- */ +#define AT91C_SSC_DATDEF ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Data Default Value */ +#define AT91C_SSC_FSDEN ( ( unsigned int ) 0x1 << 23 ) /* (SSC) Frame Sync Data Enable */ +/* -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- */ +#define AT91C_SSC_TXRDY ( ( unsigned int ) 0x1 << 0 ) /* (SSC) Transmit Ready */ +#define AT91C_SSC_TXEMPTY ( ( unsigned int ) 0x1 << 1 ) /* (SSC) Transmit Empty */ +#define AT91C_SSC_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (SSC) End Of Transmission */ +#define AT91C_SSC_TXBUFE ( ( unsigned int ) 0x1 << 3 ) /* (SSC) Transmit Buffer Empty */ +#define AT91C_SSC_RXRDY ( ( unsigned int ) 0x1 << 4 ) /* (SSC) Receive Ready */ +#define AT91C_SSC_OVRUN ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Receive Overrun */ +#define AT91C_SSC_ENDRX ( ( unsigned int ) 0x1 << 6 ) /* (SSC) End of Reception */ +#define AT91C_SSC_RXBUFF ( ( unsigned int ) 0x1 << 7 ) /* (SSC) Receive Buffer Full */ +#define AT91C_SSC_TXSYN ( ( unsigned int ) 0x1 << 10 ) /* (SSC) Transmit Sync */ +#define AT91C_SSC_RXSYN ( ( unsigned int ) 0x1 << 11 ) /* (SSC) Receive Sync */ +#define AT91C_SSC_TXENA ( ( unsigned int ) 0x1 << 16 ) /* (SSC) Transmit Enable */ +#define AT91C_SSC_RXENA ( ( unsigned int ) 0x1 << 17 ) /* (SSC) Receive Enable */ +/* -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- */ +/* -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- */ +/* -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Two-wire Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_TWI +{ + AT91_REG TWI_CR; /* Control Register */ + AT91_REG TWI_MMR; /* Master Mode Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG TWI_IADR; /* Internal Address Register */ + AT91_REG TWI_CWGR; /* Clock Waveform Generator Register */ + AT91_REG Reserved1[ 3 ]; /* */ + AT91_REG TWI_SR; /* Status Register */ + AT91_REG TWI_IER; /* Interrupt Enable Register */ + AT91_REG TWI_IDR; /* Interrupt Disable Register */ + AT91_REG TWI_IMR; /* Interrupt Mask Register */ + AT91_REG TWI_RHR; /* Receive Holding Register */ + AT91_REG TWI_THR; /* Transmit Holding Register */ +} AT91S_TWI, * AT91PS_TWI; + +/* -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */ +#define AT91C_TWI_START ( ( unsigned int ) 0x1 << 0 ) /* (TWI) Send a START Condition */ +#define AT91C_TWI_STOP ( ( unsigned int ) 0x1 << 1 ) /* (TWI) Send a STOP Condition */ +#define AT91C_TWI_MSEN ( ( unsigned int ) 0x1 << 2 ) /* (TWI) TWI Master Transfer Enabled */ +#define AT91C_TWI_MSDIS ( ( unsigned int ) 0x1 << 3 ) /* (TWI) TWI Master Transfer Disabled */ +#define AT91C_TWI_SWRST ( ( unsigned int ) 0x1 << 7 ) /* (TWI) Software Reset */ +/* -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */ +#define AT91C_TWI_IADRSZ ( ( unsigned int ) 0x3 << 8 ) /* (TWI) Internal Device Address Size */ +#define AT91C_TWI_IADRSZ_NO ( ( unsigned int ) 0x0 << 8 ) /* (TWI) No internal device address */ +#define AT91C_TWI_IADRSZ_1_BYTE ( ( unsigned int ) 0x1 << 8 ) /* (TWI) One-byte internal device address */ +#define AT91C_TWI_IADRSZ_2_BYTE ( ( unsigned int ) 0x2 << 8 ) /* (TWI) Two-byte internal device address */ +#define AT91C_TWI_IADRSZ_3_BYTE ( ( unsigned int ) 0x3 << 8 ) /* (TWI) Three-byte internal device address */ +#define AT91C_TWI_MREAD ( ( unsigned int ) 0x1 << 12 ) /* (TWI) Master Read Direction */ +#define AT91C_TWI_DADR ( ( unsigned int ) 0x7F << 16 ) /* (TWI) Device Address */ +/* -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */ +#define AT91C_TWI_CLDIV ( ( unsigned int ) 0xFF << 0 ) /* (TWI) Clock Low Divider */ +#define AT91C_TWI_CHDIV ( ( unsigned int ) 0xFF << 8 ) /* (TWI) Clock High Divider */ +#define AT91C_TWI_CKDIV ( ( unsigned int ) 0x7 << 16 ) /* (TWI) Clock Divider */ +/* -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */ +#define AT91C_TWI_TXCOMP ( ( unsigned int ) 0x1 << 0 ) /* (TWI) Transmission Completed */ +#define AT91C_TWI_RXRDY ( ( unsigned int ) 0x1 << 1 ) /* (TWI) Receive holding register ReaDY */ +#define AT91C_TWI_TXRDY ( ( unsigned int ) 0x1 << 2 ) /* (TWI) Transmit holding register ReaDY */ +#define AT91C_TWI_OVRE ( ( unsigned int ) 0x1 << 6 ) /* (TWI) Overrun Error */ +#define AT91C_TWI_UNRE ( ( unsigned int ) 0x1 << 7 ) /* (TWI) Underrun Error */ +#define AT91C_TWI_NACK ( ( unsigned int ) 0x1 << 8 ) /* (TWI) Not Acknowledged */ +/* -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */ +/* -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- */ +/* -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR PWMC Channel Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_PWMC_CH +{ + AT91_REG PWMC_CMR; /* Channel Mode Register */ + AT91_REG PWMC_CDTYR; /* Channel Duty Cycle Register */ + AT91_REG PWMC_CPRDR; /* Channel Period Register */ + AT91_REG PWMC_CCNTR; /* Channel Counter Register */ + AT91_REG PWMC_CUPDR; /* Channel Update Register */ + AT91_REG PWMC_Reserved[ 3 ]; /* Reserved */ +} AT91S_PWMC_CH, * AT91PS_PWMC_CH; + +/* -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- */ +#define AT91C_PWMC_CPRE ( ( unsigned int ) 0xF << 0 ) /* (PWMC_CH) Channel Pre-scaler : PWMC_CLKx */ +#define AT91C_PWMC_CPRE_MCK ( ( unsigned int ) 0x0 ) /* (PWMC_CH) */ +#define AT91C_PWMC_CPRE_MCKA ( ( unsigned int ) 0xB ) /* (PWMC_CH) */ +#define AT91C_PWMC_CPRE_MCKB ( ( unsigned int ) 0xC ) /* (PWMC_CH) */ +#define AT91C_PWMC_CALG ( ( unsigned int ) 0x1 << 8 ) /* (PWMC_CH) Channel Alignment */ +#define AT91C_PWMC_CPOL ( ( unsigned int ) 0x1 << 9 ) /* (PWMC_CH) Channel Polarity */ +#define AT91C_PWMC_CPD ( ( unsigned int ) 0x1 << 10 ) /* (PWMC_CH) Channel Update Period */ +/* -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- */ +#define AT91C_PWMC_CDTY ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Duty Cycle */ +/* -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- */ +#define AT91C_PWMC_CPRD ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Period */ +/* -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- */ +#define AT91C_PWMC_CCNT ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Counter */ +/* -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- */ +#define AT91C_PWMC_CUPD ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Update */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_PWMC +{ + AT91_REG PWMC_MR; /* PWMC Mode Register */ + AT91_REG PWMC_ENA; /* PWMC Enable Register */ + AT91_REG PWMC_DIS; /* PWMC Disable Register */ + AT91_REG PWMC_SR; /* PWMC Status Register */ + AT91_REG PWMC_IER; /* PWMC Interrupt Enable Register */ + AT91_REG PWMC_IDR; /* PWMC Interrupt Disable Register */ + AT91_REG PWMC_IMR; /* PWMC Interrupt Mask Register */ + AT91_REG PWMC_ISR; /* PWMC Interrupt Status Register */ + AT91_REG Reserved0[ 55 ]; /* */ + AT91_REG PWMC_VR; /* PWMC Version Register */ + AT91_REG Reserved1[ 64 ]; /* */ + AT91S_PWMC_CH PWMC_CH[ 4 ]; /* PWMC Channel */ +} AT91S_PWMC, * AT91PS_PWMC; + +/* -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- */ +#define AT91C_PWMC_DIVA ( ( unsigned int ) 0xFF << 0 ) /* (PWMC) CLKA divide factor. */ +#define AT91C_PWMC_PREA ( ( unsigned int ) 0xF << 8 ) /* (PWMC) Divider Input Clock Prescaler A */ +#define AT91C_PWMC_PREA_MCK ( ( unsigned int ) 0x0 << 8 ) /* (PWMC) */ +#define AT91C_PWMC_DIVB ( ( unsigned int ) 0xFF << 16 ) /* (PWMC) CLKB divide factor. */ +#define AT91C_PWMC_PREB ( ( unsigned int ) 0xF << 24 ) /* (PWMC) Divider Input Clock Prescaler B */ +#define AT91C_PWMC_PREB_MCK ( ( unsigned int ) 0x0 << 24 ) /* (PWMC) */ +/* -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- */ +#define AT91C_PWMC_CHID0 ( ( unsigned int ) 0x1 << 0 ) /* (PWMC) Channel ID 0 */ +#define AT91C_PWMC_CHID1 ( ( unsigned int ) 0x1 << 1 ) /* (PWMC) Channel ID 1 */ +#define AT91C_PWMC_CHID2 ( ( unsigned int ) 0x1 << 2 ) /* (PWMC) Channel ID 2 */ +#define AT91C_PWMC_CHID3 ( ( unsigned int ) 0x1 << 3 ) /* (PWMC) Channel ID 3 */ +/* -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- */ +/* -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- */ +/* -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- */ +/* -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- */ +/* -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- */ +/* -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR USB Device Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_UDP +{ + AT91_REG UDP_NUM; /* Frame Number Register */ + AT91_REG UDP_GLBSTATE; /* Global State Register */ + AT91_REG UDP_FADDR; /* Function Address Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG UDP_IER; /* Interrupt Enable Register */ + AT91_REG UDP_IDR; /* Interrupt Disable Register */ + AT91_REG UDP_IMR; /* Interrupt Mask Register */ + AT91_REG UDP_ISR; /* Interrupt Status Register */ + AT91_REG UDP_ICR; /* Interrupt Clear Register */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG UDP_RSTEP; /* Reset Endpoint Register */ + AT91_REG Reserved2[ 1 ]; /* */ + AT91_REG UDP_CSR[ 6 ]; /* Endpoint Control and Status Register */ + AT91_REG Reserved3[ 2 ]; /* */ + AT91_REG UDP_FDR[ 6 ]; /* Endpoint FIFO Data Register */ + AT91_REG Reserved4[ 3 ]; /* */ + AT91_REG UDP_TXVC; /* Transceiver Control Register */ +} AT91S_UDP, * AT91PS_UDP; + +/* -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- */ +#define AT91C_UDP_FRM_NUM ( ( unsigned int ) 0x7FF << 0 ) /* (UDP) Frame Number as Defined in the Packet Field Formats */ +#define AT91C_UDP_FRM_ERR ( ( unsigned int ) 0x1 << 16 ) /* (UDP) Frame Error */ +#define AT91C_UDP_FRM_OK ( ( unsigned int ) 0x1 << 17 ) /* (UDP) Frame OK */ +/* -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- */ +#define AT91C_UDP_FADDEN ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Function Address Enable */ +#define AT91C_UDP_CONFG ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Configured */ +#define AT91C_UDP_ESR ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Enable Send Resume */ +#define AT91C_UDP_RSMINPR ( ( unsigned int ) 0x1 << 3 ) /* (UDP) A Resume Has Been Sent to the Host */ +#define AT91C_UDP_RMWUPE ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Remote Wake Up Enable */ +/* -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- */ +#define AT91C_UDP_FADD ( ( unsigned int ) 0xFF << 0 ) /* (UDP) Function Address Value */ +#define AT91C_UDP_FEN ( ( unsigned int ) 0x1 << 8 ) /* (UDP) Function Enable */ +/* -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- */ +#define AT91C_UDP_EPINT0 ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Endpoint 0 Interrupt */ +#define AT91C_UDP_EPINT1 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Endpoint 0 Interrupt */ +#define AT91C_UDP_EPINT2 ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Endpoint 2 Interrupt */ +#define AT91C_UDP_EPINT3 ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Endpoint 3 Interrupt */ +#define AT91C_UDP_EPINT4 ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Endpoint 4 Interrupt */ +#define AT91C_UDP_EPINT5 ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Endpoint 5 Interrupt */ +#define AT91C_UDP_RXSUSP ( ( unsigned int ) 0x1 << 8 ) /* (UDP) USB Suspend Interrupt */ +#define AT91C_UDP_RXRSM ( ( unsigned int ) 0x1 << 9 ) /* (UDP) USB Resume Interrupt */ +#define AT91C_UDP_EXTRSM ( ( unsigned int ) 0x1 << 10 ) /* (UDP) USB External Resume Interrupt */ +#define AT91C_UDP_SOFINT ( ( unsigned int ) 0x1 << 11 ) /* (UDP) USB Start Of frame Interrupt */ +#define AT91C_UDP_WAKEUP ( ( unsigned int ) 0x1 << 13 ) /* (UDP) USB Resume Interrupt */ +/* -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- */ +/* -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- */ +/* -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- */ +#define AT91C_UDP_ENDBUSRES ( ( unsigned int ) 0x1 << 12 ) /* (UDP) USB End Of Bus Reset Interrupt */ +/* -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- */ +/* -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- */ +#define AT91C_UDP_EP0 ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Reset Endpoint 0 */ +#define AT91C_UDP_EP1 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Reset Endpoint 1 */ +#define AT91C_UDP_EP2 ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Reset Endpoint 2 */ +#define AT91C_UDP_EP3 ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Reset Endpoint 3 */ +#define AT91C_UDP_EP4 ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Reset Endpoint 4 */ +#define AT91C_UDP_EP5 ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Reset Endpoint 5 */ +/* -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- */ +#define AT91C_UDP_TXCOMP ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Generates an IN packet with data previously written in the DPR */ +#define AT91C_UDP_RX_DATA_BK0 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Receive Data Bank 0 */ +#define AT91C_UDP_RXSETUP ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Sends STALL to the Host (Control endpoints) */ +#define AT91C_UDP_ISOERROR ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Isochronous error (Isochronous endpoints) */ +#define AT91C_UDP_TXPKTRDY ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Transmit Packet Ready */ +#define AT91C_UDP_FORCESTALL ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). */ +#define AT91C_UDP_RX_DATA_BK1 ( ( unsigned int ) 0x1 << 6 ) /* (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). */ +#define AT91C_UDP_DIR ( ( unsigned int ) 0x1 << 7 ) /* (UDP) Transfer Direction */ +#define AT91C_UDP_EPTYPE ( ( unsigned int ) 0x7 << 8 ) /* (UDP) Endpoint type */ +#define AT91C_UDP_EPTYPE_CTRL ( ( unsigned int ) 0x0 << 8 ) /* (UDP) Control */ +#define AT91C_UDP_EPTYPE_ISO_OUT ( ( unsigned int ) 0x1 << 8 ) /* (UDP) Isochronous OUT */ +#define AT91C_UDP_EPTYPE_BULK_OUT ( ( unsigned int ) 0x2 << 8 ) /* (UDP) Bulk OUT */ +#define AT91C_UDP_EPTYPE_INT_OUT ( ( unsigned int ) 0x3 << 8 ) /* (UDP) Interrupt OUT */ +#define AT91C_UDP_EPTYPE_ISO_IN ( ( unsigned int ) 0x5 << 8 ) /* (UDP) Isochronous IN */ +#define AT91C_UDP_EPTYPE_BULK_IN ( ( unsigned int ) 0x6 << 8 ) /* (UDP) Bulk IN */ +#define AT91C_UDP_EPTYPE_INT_IN ( ( unsigned int ) 0x7 << 8 ) /* (UDP) Interrupt IN */ +#define AT91C_UDP_DTGLE ( ( unsigned int ) 0x1 << 11 ) /* (UDP) Data Toggle */ +#define AT91C_UDP_EPEDS ( ( unsigned int ) 0x1 << 15 ) /* (UDP) Endpoint Enable Disable */ +#define AT91C_UDP_RXBYTECNT ( ( unsigned int ) 0x7FF << 16 ) /* (UDP) Number Of Bytes Available in the FIFO */ +/* -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- */ +#define AT91C_UDP_TXVDIS ( ( unsigned int ) 0x1 << 8 ) /* (UDP) */ +#define AT91C_UDP_PUON ( ( unsigned int ) 0x1 << 9 ) /* (UDP) Pull-up ON */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_TC +{ + AT91_REG TC_CCR; /* Channel Control Register */ + AT91_REG TC_CMR; /* Channel Mode Register (Capture Mode / Waveform Mode) */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG TC_CV; /* Counter Value */ + AT91_REG TC_RA; /* Register A */ + AT91_REG TC_RB; /* Register B */ + AT91_REG TC_RC; /* Register C */ + AT91_REG TC_SR; /* Status Register */ + AT91_REG TC_IER; /* Interrupt Enable Register */ + AT91_REG TC_IDR; /* Interrupt Disable Register */ + AT91_REG TC_IMR; /* Interrupt Mask Register */ +} AT91S_TC, * AT91PS_TC; + +/* -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- */ +#define AT91C_TC_CLKEN ( ( unsigned int ) 0x1 << 0 ) /* (TC) Counter Clock Enable Command */ +#define AT91C_TC_CLKDIS ( ( unsigned int ) 0x1 << 1 ) /* (TC) Counter Clock Disable Command */ +#define AT91C_TC_SWTRG ( ( unsigned int ) 0x1 << 2 ) /* (TC) Software Trigger Command */ +/* -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- */ +#define AT91C_TC_CLKS ( ( unsigned int ) 0x7 << 0 ) /* (TC) Clock Selection */ +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ( ( unsigned int ) 0x0 ) /* (TC) Clock selected: TIMER_DIV1_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ( ( unsigned int ) 0x1 ) /* (TC) Clock selected: TIMER_DIV2_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ( ( unsigned int ) 0x2 ) /* (TC) Clock selected: TIMER_DIV3_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ( ( unsigned int ) 0x3 ) /* (TC) Clock selected: TIMER_DIV4_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ( ( unsigned int ) 0x4 ) /* (TC) Clock selected: TIMER_DIV5_CLOCK */ +#define AT91C_TC_CLKS_XC0 ( ( unsigned int ) 0x5 ) /* (TC) Clock selected: XC0 */ +#define AT91C_TC_CLKS_XC1 ( ( unsigned int ) 0x6 ) /* (TC) Clock selected: XC1 */ +#define AT91C_TC_CLKS_XC2 ( ( unsigned int ) 0x7 ) /* (TC) Clock selected: XC2 */ +#define AT91C_TC_CLKI ( ( unsigned int ) 0x1 << 3 ) /* (TC) Clock Invert */ +#define AT91C_TC_BURST ( ( unsigned int ) 0x3 << 4 ) /* (TC) Burst Signal Selection */ +#define AT91C_TC_BURST_NONE ( ( unsigned int ) 0x0 << 4 ) /* (TC) The clock is not gated by an external signal */ +#define AT91C_TC_BURST_XC0 ( ( unsigned int ) 0x1 << 4 ) /* (TC) XC0 is ANDed with the selected clock */ +#define AT91C_TC_BURST_XC1 ( ( unsigned int ) 0x2 << 4 ) /* (TC) XC1 is ANDed with the selected clock */ +#define AT91C_TC_BURST_XC2 ( ( unsigned int ) 0x3 << 4 ) /* (TC) XC2 is ANDed with the selected clock */ +#define AT91C_TC_CPCSTOP ( ( unsigned int ) 0x1 << 6 ) /* (TC) Counter Clock Stopped with RC Compare */ +#define AT91C_TC_LDBSTOP ( ( unsigned int ) 0x1 << 6 ) /* (TC) Counter Clock Stopped with RB Loading */ +#define AT91C_TC_CPCDIS ( ( unsigned int ) 0x1 << 7 ) /* (TC) Counter Clock Disable with RC Compare */ +#define AT91C_TC_LDBDIS ( ( unsigned int ) 0x1 << 7 ) /* (TC) Counter Clock Disabled with RB Loading */ +#define AT91C_TC_ETRGEDG ( ( unsigned int ) 0x3 << 8 ) /* (TC) External Trigger Edge Selection */ +#define AT91C_TC_ETRGEDG_NONE ( ( unsigned int ) 0x0 << 8 ) /* (TC) Edge: None */ +#define AT91C_TC_ETRGEDG_RISING ( ( unsigned int ) 0x1 << 8 ) /* (TC) Edge: rising edge */ +#define AT91C_TC_ETRGEDG_FALLING ( ( unsigned int ) 0x2 << 8 ) /* (TC) Edge: falling edge */ +#define AT91C_TC_ETRGEDG_BOTH ( ( unsigned int ) 0x3 << 8 ) /* (TC) Edge: each edge */ +#define AT91C_TC_EEVTEDG ( ( unsigned int ) 0x3 << 8 ) /* (TC) External Event Edge Selection */ +#define AT91C_TC_EEVTEDG_NONE ( ( unsigned int ) 0x0 << 8 ) /* (TC) Edge: None */ +#define AT91C_TC_EEVTEDG_RISING ( ( unsigned int ) 0x1 << 8 ) /* (TC) Edge: rising edge */ +#define AT91C_TC_EEVTEDG_FALLING ( ( unsigned int ) 0x2 << 8 ) /* (TC) Edge: falling edge */ +#define AT91C_TC_EEVTEDG_BOTH ( ( unsigned int ) 0x3 << 8 ) /* (TC) Edge: each edge */ +#define AT91C_TC_EEVT ( ( unsigned int ) 0x3 << 10 ) /* (TC) External Event Selection */ +#define AT91C_TC_EEVT_TIOB ( ( unsigned int ) 0x0 << 10 ) /* (TC) Signal selected as external event: TIOB TIOB direction: input */ +#define AT91C_TC_EEVT_XC0 ( ( unsigned int ) 0x1 << 10 ) /* (TC) Signal selected as external event: XC0 TIOB direction: output */ +#define AT91C_TC_EEVT_XC1 ( ( unsigned int ) 0x2 << 10 ) /* (TC) Signal selected as external event: XC1 TIOB direction: output */ +#define AT91C_TC_EEVT_XC2 ( ( unsigned int ) 0x3 << 10 ) /* (TC) Signal selected as external event: XC2 TIOB direction: output */ +#define AT91C_TC_ABETRG ( ( unsigned int ) 0x1 << 10 ) /* (TC) TIOA or TIOB External Trigger Selection */ +#define AT91C_TC_ENETRG ( ( unsigned int ) 0x1 << 12 ) /* (TC) External Event Trigger enable */ +#define AT91C_TC_WAVESEL ( ( unsigned int ) 0x3 << 13 ) /* (TC) Waveform Selection */ +#define AT91C_TC_WAVESEL_UP ( ( unsigned int ) 0x0 << 13 ) /* (TC) UP mode without atomatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UPDOWN ( ( unsigned int ) 0x1 << 13 ) /* (TC) UPDOWN mode without automatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UP_AUTO ( ( unsigned int ) 0x2 << 13 ) /* (TC) UP mode with automatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UPDOWN_AUTO ( ( unsigned int ) 0x3 << 13 ) /* (TC) UPDOWN mode with automatic trigger on RC Compare */ +#define AT91C_TC_CPCTRG ( ( unsigned int ) 0x1 << 14 ) /* (TC) RC Compare Trigger Enable */ +#define AT91C_TC_WAVE ( ( unsigned int ) 0x1 << 15 ) /* (TC) */ +#define AT91C_TC_ACPA ( ( unsigned int ) 0x3 << 16 ) /* (TC) RA Compare Effect on TIOA */ +#define AT91C_TC_ACPA_NONE ( ( unsigned int ) 0x0 << 16 ) /* (TC) Effect: none */ +#define AT91C_TC_ACPA_SET ( ( unsigned int ) 0x1 << 16 ) /* (TC) Effect: set */ +#define AT91C_TC_ACPA_CLEAR ( ( unsigned int ) 0x2 << 16 ) /* (TC) Effect: clear */ +#define AT91C_TC_ACPA_TOGGLE ( ( unsigned int ) 0x3 << 16 ) /* (TC) Effect: toggle */ +#define AT91C_TC_LDRA ( ( unsigned int ) 0x3 << 16 ) /* (TC) RA Loading Selection */ +#define AT91C_TC_LDRA_NONE ( ( unsigned int ) 0x0 << 16 ) /* (TC) Edge: None */ +#define AT91C_TC_LDRA_RISING ( ( unsigned int ) 0x1 << 16 ) /* (TC) Edge: rising edge of TIOA */ +#define AT91C_TC_LDRA_FALLING ( ( unsigned int ) 0x2 << 16 ) /* (TC) Edge: falling edge of TIOA */ +#define AT91C_TC_LDRA_BOTH ( ( unsigned int ) 0x3 << 16 ) /* (TC) Edge: each edge of TIOA */ +#define AT91C_TC_ACPC ( ( unsigned int ) 0x3 << 18 ) /* (TC) RC Compare Effect on TIOA */ +#define AT91C_TC_ACPC_NONE ( ( unsigned int ) 0x0 << 18 ) /* (TC) Effect: none */ +#define AT91C_TC_ACPC_SET ( ( unsigned int ) 0x1 << 18 ) /* (TC) Effect: set */ +#define AT91C_TC_ACPC_CLEAR ( ( unsigned int ) 0x2 << 18 ) /* (TC) Effect: clear */ +#define AT91C_TC_ACPC_TOGGLE ( ( unsigned int ) 0x3 << 18 ) /* (TC) Effect: toggle */ +#define AT91C_TC_LDRB ( ( unsigned int ) 0x3 << 18 ) /* (TC) RB Loading Selection */ +#define AT91C_TC_LDRB_NONE ( ( unsigned int ) 0x0 << 18 ) /* (TC) Edge: None */ +#define AT91C_TC_LDRB_RISING ( ( unsigned int ) 0x1 << 18 ) /* (TC) Edge: rising edge of TIOA */ +#define AT91C_TC_LDRB_FALLING ( ( unsigned int ) 0x2 << 18 ) /* (TC) Edge: falling edge of TIOA */ +#define AT91C_TC_LDRB_BOTH ( ( unsigned int ) 0x3 << 18 ) /* (TC) Edge: each edge of TIOA */ +#define AT91C_TC_AEEVT ( ( unsigned int ) 0x3 << 20 ) /* (TC) External Event Effect on TIOA */ +#define AT91C_TC_AEEVT_NONE ( ( unsigned int ) 0x0 << 20 ) /* (TC) Effect: none */ +#define AT91C_TC_AEEVT_SET ( ( unsigned int ) 0x1 << 20 ) /* (TC) Effect: set */ +#define AT91C_TC_AEEVT_CLEAR ( ( unsigned int ) 0x2 << 20 ) /* (TC) Effect: clear */ +#define AT91C_TC_AEEVT_TOGGLE ( ( unsigned int ) 0x3 << 20 ) /* (TC) Effect: toggle */ +#define AT91C_TC_ASWTRG ( ( unsigned int ) 0x3 << 22 ) /* (TC) Software Trigger Effect on TIOA */ +#define AT91C_TC_ASWTRG_NONE ( ( unsigned int ) 0x0 << 22 ) /* (TC) Effect: none */ +#define AT91C_TC_ASWTRG_SET ( ( unsigned int ) 0x1 << 22 ) /* (TC) Effect: set */ +#define AT91C_TC_ASWTRG_CLEAR ( ( unsigned int ) 0x2 << 22 ) /* (TC) Effect: clear */ +#define AT91C_TC_ASWTRG_TOGGLE ( ( unsigned int ) 0x3 << 22 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BCPB ( ( unsigned int ) 0x3 << 24 ) /* (TC) RB Compare Effect on TIOB */ +#define AT91C_TC_BCPB_NONE ( ( unsigned int ) 0x0 << 24 ) /* (TC) Effect: none */ +#define AT91C_TC_BCPB_SET ( ( unsigned int ) 0x1 << 24 ) /* (TC) Effect: set */ +#define AT91C_TC_BCPB_CLEAR ( ( unsigned int ) 0x2 << 24 ) /* (TC) Effect: clear */ +#define AT91C_TC_BCPB_TOGGLE ( ( unsigned int ) 0x3 << 24 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BCPC ( ( unsigned int ) 0x3 << 26 ) /* (TC) RC Compare Effect on TIOB */ +#define AT91C_TC_BCPC_NONE ( ( unsigned int ) 0x0 << 26 ) /* (TC) Effect: none */ +#define AT91C_TC_BCPC_SET ( ( unsigned int ) 0x1 << 26 ) /* (TC) Effect: set */ +#define AT91C_TC_BCPC_CLEAR ( ( unsigned int ) 0x2 << 26 ) /* (TC) Effect: clear */ +#define AT91C_TC_BCPC_TOGGLE ( ( unsigned int ) 0x3 << 26 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BEEVT ( ( unsigned int ) 0x3 << 28 ) /* (TC) External Event Effect on TIOB */ +#define AT91C_TC_BEEVT_NONE ( ( unsigned int ) 0x0 << 28 ) /* (TC) Effect: none */ +#define AT91C_TC_BEEVT_SET ( ( unsigned int ) 0x1 << 28 ) /* (TC) Effect: set */ +#define AT91C_TC_BEEVT_CLEAR ( ( unsigned int ) 0x2 << 28 ) /* (TC) Effect: clear */ +#define AT91C_TC_BEEVT_TOGGLE ( ( unsigned int ) 0x3 << 28 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BSWTRG ( ( unsigned int ) 0x3 << 30 ) /* (TC) Software Trigger Effect on TIOB */ +#define AT91C_TC_BSWTRG_NONE ( ( unsigned int ) 0x0 << 30 ) /* (TC) Effect: none */ +#define AT91C_TC_BSWTRG_SET ( ( unsigned int ) 0x1 << 30 ) /* (TC) Effect: set */ +#define AT91C_TC_BSWTRG_CLEAR ( ( unsigned int ) 0x2 << 30 ) /* (TC) Effect: clear */ +#define AT91C_TC_BSWTRG_TOGGLE ( ( unsigned int ) 0x3 << 30 ) /* (TC) Effect: toggle */ +/* -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- */ +#define AT91C_TC_COVFS ( ( unsigned int ) 0x1 << 0 ) /* (TC) Counter Overflow */ +#define AT91C_TC_LOVRS ( ( unsigned int ) 0x1 << 1 ) /* (TC) Load Overrun */ +#define AT91C_TC_CPAS ( ( unsigned int ) 0x1 << 2 ) /* (TC) RA Compare */ +#define AT91C_TC_CPBS ( ( unsigned int ) 0x1 << 3 ) /* (TC) RB Compare */ +#define AT91C_TC_CPCS ( ( unsigned int ) 0x1 << 4 ) /* (TC) RC Compare */ +#define AT91C_TC_LDRAS ( ( unsigned int ) 0x1 << 5 ) /* (TC) RA Loading */ +#define AT91C_TC_LDRBS ( ( unsigned int ) 0x1 << 6 ) /* (TC) RB Loading */ +#define AT91C_TC_ETRGS ( ( unsigned int ) 0x1 << 7 ) /* (TC) External Trigger */ +#define AT91C_TC_CLKSTA ( ( unsigned int ) 0x1 << 16 ) /* (TC) Clock Enabling */ +#define AT91C_TC_MTIOA ( ( unsigned int ) 0x1 << 17 ) /* (TC) TIOA Mirror */ +#define AT91C_TC_MTIOB ( ( unsigned int ) 0x1 << 18 ) /* (TC) TIOA Mirror */ +/* -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- */ +/* -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- */ +/* -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Timer Counter Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_TCB +{ + AT91S_TC TCB_TC0; /* TC Channel 0 */ + AT91_REG Reserved0[ 4 ]; /* */ + AT91S_TC TCB_TC1; /* TC Channel 1 */ + AT91_REG Reserved1[ 4 ]; /* */ + AT91S_TC TCB_TC2; /* TC Channel 2 */ + AT91_REG Reserved2[ 4 ]; /* */ + AT91_REG TCB_BCR; /* TC Block Control Register */ + AT91_REG TCB_BMR; /* TC Block Mode Register */ +} AT91S_TCB, * AT91PS_TCB; + +/* -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- */ +#define AT91C_TCB_SYNC ( ( unsigned int ) 0x1 << 0 ) /* (TCB) Synchro Command */ +/* -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- */ +#define AT91C_TCB_TC0XC0S ( ( unsigned int ) 0x3 << 0 ) /* (TCB) External Clock Signal 0 Selection */ +#define AT91C_TCB_TC0XC0S_TCLK0 ( ( unsigned int ) 0x0 ) /* (TCB) TCLK0 connected to XC0 */ +#define AT91C_TCB_TC0XC0S_NONE ( ( unsigned int ) 0x1 ) /* (TCB) None signal connected to XC0 */ +#define AT91C_TCB_TC0XC0S_TIOA1 ( ( unsigned int ) 0x2 ) /* (TCB) TIOA1 connected to XC0 */ +#define AT91C_TCB_TC0XC0S_TIOA2 ( ( unsigned int ) 0x3 ) /* (TCB) TIOA2 connected to XC0 */ +#define AT91C_TCB_TC1XC1S ( ( unsigned int ) 0x3 << 2 ) /* (TCB) External Clock Signal 1 Selection */ +#define AT91C_TCB_TC1XC1S_TCLK1 ( ( unsigned int ) 0x0 << 2 ) /* (TCB) TCLK1 connected to XC1 */ +#define AT91C_TCB_TC1XC1S_NONE ( ( unsigned int ) 0x1 << 2 ) /* (TCB) None signal connected to XC1 */ +#define AT91C_TCB_TC1XC1S_TIOA0 ( ( unsigned int ) 0x2 << 2 ) /* (TCB) TIOA0 connected to XC1 */ +#define AT91C_TCB_TC1XC1S_TIOA2 ( ( unsigned int ) 0x3 << 2 ) /* (TCB) TIOA2 connected to XC1 */ +#define AT91C_TCB_TC2XC2S ( ( unsigned int ) 0x3 << 4 ) /* (TCB) External Clock Signal 2 Selection */ +#define AT91C_TCB_TC2XC2S_TCLK2 ( ( unsigned int ) 0x0 << 4 ) /* (TCB) TCLK2 connected to XC2 */ +#define AT91C_TCB_TC2XC2S_NONE ( ( unsigned int ) 0x1 << 4 ) /* (TCB) None signal connected to XC2 */ +#define AT91C_TCB_TC2XC2S_TIOA0 ( ( unsigned int ) 0x2 << 4 ) /* (TCB) TIOA0 connected to XC2 */ +#define AT91C_TCB_TC2XC2S_TIOA1 ( ( unsigned int ) 0x3 << 4 ) /* (TCB) TIOA2 connected to XC2 */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_CAN_MB +{ + AT91_REG CAN_MB_MMR; /* MailBox Mode Register */ + AT91_REG CAN_MB_MAM; /* MailBox Acceptance Mask Register */ + AT91_REG CAN_MB_MID; /* MailBox ID Register */ + AT91_REG CAN_MB_MFID; /* MailBox Family ID Register */ + AT91_REG CAN_MB_MSR; /* MailBox Status Register */ + AT91_REG CAN_MB_MDL; /* MailBox Data Low Register */ + AT91_REG CAN_MB_MDH; /* MailBox Data High Register */ + AT91_REG CAN_MB_MCR; /* MailBox Control Register */ +} AT91S_CAN_MB, * AT91PS_CAN_MB; + +/* -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- */ +#define AT91C_CAN_MTIMEMARK ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN_MB) Mailbox Timemark */ +#define AT91C_CAN_PRIOR ( ( unsigned int ) 0xF << 16 ) /* (CAN_MB) Mailbox Priority */ +#define AT91C_CAN_MOT ( ( unsigned int ) 0x7 << 24 ) /* (CAN_MB) Mailbox Object Type */ +#define AT91C_CAN_MOT_DIS ( ( unsigned int ) 0x0 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_RX ( ( unsigned int ) 0x1 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_RXOVERWRITE ( ( unsigned int ) 0x2 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_TX ( ( unsigned int ) 0x3 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_CONSUMER ( ( unsigned int ) 0x4 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_PRODUCER ( ( unsigned int ) 0x5 << 24 ) /* (CAN_MB) */ +/* -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- */ +#define AT91C_CAN_MIDvB ( ( unsigned int ) 0x3FFFF << 0 ) /* (CAN_MB) Complementary bits for identifier in extended mode */ +#define AT91C_CAN_MIDvA ( ( unsigned int ) 0x7FF << 18 ) /* (CAN_MB) Identifier for standard frame mode */ +#define AT91C_CAN_MIDE ( ( unsigned int ) 0x1 << 29 ) /* (CAN_MB) Identifier Version */ +/* -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- */ +/* -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- */ +/* -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- */ +#define AT91C_CAN_MTIMESTAMP ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN_MB) Timer Value */ +#define AT91C_CAN_MDLC ( ( unsigned int ) 0xF << 16 ) /* (CAN_MB) Mailbox Data Length Code */ +#define AT91C_CAN_MRTR ( ( unsigned int ) 0x1 << 20 ) /* (CAN_MB) Mailbox Remote Transmission Request */ +#define AT91C_CAN_MABT ( ( unsigned int ) 0x1 << 22 ) /* (CAN_MB) Mailbox Message Abort */ +#define AT91C_CAN_MRDY ( ( unsigned int ) 0x1 << 23 ) /* (CAN_MB) Mailbox Ready */ +#define AT91C_CAN_MMI ( ( unsigned int ) 0x1 << 24 ) /* (CAN_MB) Mailbox Message Ignored */ +/* -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- */ +/* -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- */ +/* -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- */ +#define AT91C_CAN_MACR ( ( unsigned int ) 0x1 << 22 ) /* (CAN_MB) Abort Request for Mailbox */ +#define AT91C_CAN_MTCR ( ( unsigned int ) 0x1 << 23 ) /* (CAN_MB) Mailbox Transfer Command */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Control Area Network Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_CAN +{ + AT91_REG CAN_MR; /* Mode Register */ + AT91_REG CAN_IER; /* Interrupt Enable Register */ + AT91_REG CAN_IDR; /* Interrupt Disable Register */ + AT91_REG CAN_IMR; /* Interrupt Mask Register */ + AT91_REG CAN_SR; /* Status Register */ + AT91_REG CAN_BR; /* Baudrate Register */ + AT91_REG CAN_TIM; /* Timer Register */ + AT91_REG CAN_TIMESTP; /* Time Stamp Register */ + AT91_REG CAN_ECR; /* Error Counter Register */ + AT91_REG CAN_TCR; /* Transfer Command Register */ + AT91_REG CAN_ACR; /* Abort Command Register */ + AT91_REG Reserved0[ 52 ]; /* */ + AT91_REG CAN_VR; /* Version Register */ + AT91_REG Reserved1[ 64 ]; /* */ + AT91S_CAN_MB CAN_MB0; /* CAN Mailbox 0 */ + AT91S_CAN_MB CAN_MB1; /* CAN Mailbox 1 */ + AT91S_CAN_MB CAN_MB2; /* CAN Mailbox 2 */ + AT91S_CAN_MB CAN_MB3; /* CAN Mailbox 3 */ + AT91S_CAN_MB CAN_MB4; /* CAN Mailbox 4 */ + AT91S_CAN_MB CAN_MB5; /* CAN Mailbox 5 */ + AT91S_CAN_MB CAN_MB6; /* CAN Mailbox 6 */ + AT91S_CAN_MB CAN_MB7; /* CAN Mailbox 7 */ + AT91S_CAN_MB CAN_MB8; /* CAN Mailbox 8 */ + AT91S_CAN_MB CAN_MB9; /* CAN Mailbox 9 */ + AT91S_CAN_MB CAN_MB10; /* CAN Mailbox 10 */ + AT91S_CAN_MB CAN_MB11; /* CAN Mailbox 11 */ + AT91S_CAN_MB CAN_MB12; /* CAN Mailbox 12 */ + AT91S_CAN_MB CAN_MB13; /* CAN Mailbox 13 */ + AT91S_CAN_MB CAN_MB14; /* CAN Mailbox 14 */ + AT91S_CAN_MB CAN_MB15; /* CAN Mailbox 15 */ +} AT91S_CAN, * AT91PS_CAN; + +/* -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- */ +#define AT91C_CAN_CANEN ( ( unsigned int ) 0x1 << 0 ) /* (CAN) CAN Controller Enable */ +#define AT91C_CAN_LPM ( ( unsigned int ) 0x1 << 1 ) /* (CAN) Disable/Enable Low Power Mode */ +#define AT91C_CAN_ABM ( ( unsigned int ) 0x1 << 2 ) /* (CAN) Disable/Enable Autobaud/Listen Mode */ +#define AT91C_CAN_OVL ( ( unsigned int ) 0x1 << 3 ) /* (CAN) Disable/Enable Overload Frame */ +#define AT91C_CAN_TEOF ( ( unsigned int ) 0x1 << 4 ) /* (CAN) Time Stamp messages at each end of Frame */ +#define AT91C_CAN_TTM ( ( unsigned int ) 0x1 << 5 ) /* (CAN) Disable/Enable Time Trigger Mode */ +#define AT91C_CAN_TIMFRZ ( ( unsigned int ) 0x1 << 6 ) /* (CAN) Enable Timer Freeze */ +#define AT91C_CAN_DRPT ( ( unsigned int ) 0x1 << 7 ) /* (CAN) Disable Repeat */ +/* -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- */ +#define AT91C_CAN_MB0 ( ( unsigned int ) 0x1 << 0 ) /* (CAN) Mailbox 0 Flag */ +#define AT91C_CAN_MB1 ( ( unsigned int ) 0x1 << 1 ) /* (CAN) Mailbox 1 Flag */ +#define AT91C_CAN_MB2 ( ( unsigned int ) 0x1 << 2 ) /* (CAN) Mailbox 2 Flag */ +#define AT91C_CAN_MB3 ( ( unsigned int ) 0x1 << 3 ) /* (CAN) Mailbox 3 Flag */ +#define AT91C_CAN_MB4 ( ( unsigned int ) 0x1 << 4 ) /* (CAN) Mailbox 4 Flag */ +#define AT91C_CAN_MB5 ( ( unsigned int ) 0x1 << 5 ) /* (CAN) Mailbox 5 Flag */ +#define AT91C_CAN_MB6 ( ( unsigned int ) 0x1 << 6 ) /* (CAN) Mailbox 6 Flag */ +#define AT91C_CAN_MB7 ( ( unsigned int ) 0x1 << 7 ) /* (CAN) Mailbox 7 Flag */ +#define AT91C_CAN_MB8 ( ( unsigned int ) 0x1 << 8 ) /* (CAN) Mailbox 8 Flag */ +#define AT91C_CAN_MB9 ( ( unsigned int ) 0x1 << 9 ) /* (CAN) Mailbox 9 Flag */ +#define AT91C_CAN_MB10 ( ( unsigned int ) 0x1 << 10 ) /* (CAN) Mailbox 10 Flag */ +#define AT91C_CAN_MB11 ( ( unsigned int ) 0x1 << 11 ) /* (CAN) Mailbox 11 Flag */ +#define AT91C_CAN_MB12 ( ( unsigned int ) 0x1 << 12 ) /* (CAN) Mailbox 12 Flag */ +#define AT91C_CAN_MB13 ( ( unsigned int ) 0x1 << 13 ) /* (CAN) Mailbox 13 Flag */ +#define AT91C_CAN_MB14 ( ( unsigned int ) 0x1 << 14 ) /* (CAN) Mailbox 14 Flag */ +#define AT91C_CAN_MB15 ( ( unsigned int ) 0x1 << 15 ) /* (CAN) Mailbox 15 Flag */ +#define AT91C_CAN_ERRA ( ( unsigned int ) 0x1 << 16 ) /* (CAN) Error Active Mode Flag */ +#define AT91C_CAN_WARN ( ( unsigned int ) 0x1 << 17 ) /* (CAN) Warning Limit Flag */ +#define AT91C_CAN_ERRP ( ( unsigned int ) 0x1 << 18 ) /* (CAN) Error Passive Mode Flag */ +#define AT91C_CAN_BOFF ( ( unsigned int ) 0x1 << 19 ) /* (CAN) Bus Off Mode Flag */ +#define AT91C_CAN_SLEEP ( ( unsigned int ) 0x1 << 20 ) /* (CAN) Sleep Flag */ +#define AT91C_CAN_WAKEUP ( ( unsigned int ) 0x1 << 21 ) /* (CAN) Wakeup Flag */ +#define AT91C_CAN_TOVF ( ( unsigned int ) 0x1 << 22 ) /* (CAN) Timer Overflow Flag */ +#define AT91C_CAN_TSTP ( ( unsigned int ) 0x1 << 23 ) /* (CAN) Timestamp Flag */ +#define AT91C_CAN_CERR ( ( unsigned int ) 0x1 << 24 ) /* (CAN) CRC Error */ +#define AT91C_CAN_SERR ( ( unsigned int ) 0x1 << 25 ) /* (CAN) Stuffing Error */ +#define AT91C_CAN_AERR ( ( unsigned int ) 0x1 << 26 ) /* (CAN) Acknowledgment Error */ +#define AT91C_CAN_FERR ( ( unsigned int ) 0x1 << 27 ) /* (CAN) Form Error */ +#define AT91C_CAN_BERR ( ( unsigned int ) 0x1 << 28 ) /* (CAN) Bit Error */ +/* -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- */ +/* -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- */ +/* -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- */ +#define AT91C_CAN_RBSY ( ( unsigned int ) 0x1 << 29 ) /* (CAN) Receiver Busy */ +#define AT91C_CAN_TBSY ( ( unsigned int ) 0x1 << 30 ) /* (CAN) Transmitter Busy */ +#define AT91C_CAN_OVLY ( ( unsigned int ) 0x1 << 31 ) /* (CAN) Overload Busy */ +/* -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- */ +#define AT91C_CAN_PHASE2 ( ( unsigned int ) 0x7 << 0 ) /* (CAN) Phase 2 segment */ +#define AT91C_CAN_PHASE1 ( ( unsigned int ) 0x7 << 4 ) /* (CAN) Phase 1 segment */ +#define AT91C_CAN_PROPAG ( ( unsigned int ) 0x7 << 8 ) /* (CAN) Programmation time segment */ +#define AT91C_CAN_SYNC ( ( unsigned int ) 0x3 << 12 ) /* (CAN) Re-synchronization jump width segment */ +#define AT91C_CAN_BRP ( ( unsigned int ) 0x7F << 16 ) /* (CAN) Baudrate Prescaler */ +#define AT91C_CAN_SMP ( ( unsigned int ) 0x1 << 24 ) /* (CAN) Sampling mode */ +/* -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- */ +#define AT91C_CAN_TIMER ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN) Timer field */ +/* -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- */ +/* -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- */ +#define AT91C_CAN_REC ( ( unsigned int ) 0xFF << 0 ) /* (CAN) Receive Error Counter */ +#define AT91C_CAN_TEC ( ( unsigned int ) 0xFF << 16 ) /* (CAN) Transmit Error Counter */ +/* -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- */ +#define AT91C_CAN_TIMRST ( ( unsigned int ) 0x1 << 31 ) /* (CAN) Timer Reset Field */ +/* -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 */ +/* ***************************************************************************** */ +typedef struct _AT91S_EMAC +{ + AT91_REG EMAC_NCR; /* Network Control Register */ + AT91_REG EMAC_NCFGR; /* Network Configuration Register */ + AT91_REG EMAC_NSR; /* Network Status Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG EMAC_TSR; /* Transmit Status Register */ + AT91_REG EMAC_RBQP; /* Receive Buffer Queue Pointer */ + AT91_REG EMAC_TBQP; /* Transmit Buffer Queue Pointer */ + AT91_REG EMAC_RSR; /* Receive Status Register */ + AT91_REG EMAC_ISR; /* Interrupt Status Register */ + AT91_REG EMAC_IER; /* Interrupt Enable Register */ + AT91_REG EMAC_IDR; /* Interrupt Disable Register */ + AT91_REG EMAC_IMR; /* Interrupt Mask Register */ + AT91_REG EMAC_MAN; /* PHY Maintenance Register */ + AT91_REG EMAC_PTR; /* Pause Time Register */ + AT91_REG EMAC_PFR; /* Pause Frames received Register */ + AT91_REG EMAC_FTO; /* Frames Transmitted OK Register */ + AT91_REG EMAC_SCF; /* Single Collision Frame Register */ + AT91_REG EMAC_MCF; /* Multiple Collision Frame Register */ + AT91_REG EMAC_FRO; /* Frames Received OK Register */ + AT91_REG EMAC_FCSE; /* Frame Check Sequence Error Register */ + AT91_REG EMAC_ALE; /* Alignment Error Register */ + AT91_REG EMAC_DTF; /* Deferred Transmission Frame Register */ + AT91_REG EMAC_LCOL; /* Late Collision Register */ + AT91_REG EMAC_ECOL; /* Excessive Collision Register */ + AT91_REG EMAC_TUND; /* Transmit Underrun Error Register */ + AT91_REG EMAC_CSE; /* Carrier Sense Error Register */ + AT91_REG EMAC_RRE; /* Receive Resource Error Register */ + AT91_REG EMAC_ROV; /* Receive Overrun Errors Register */ + AT91_REG EMAC_RSE; /* Receive Symbol Errors Register */ + AT91_REG EMAC_ELE; /* Excessive Length Errors Register */ + AT91_REG EMAC_RJA; /* Receive Jabbers Register */ + AT91_REG EMAC_USF; /* Undersize Frames Register */ + AT91_REG EMAC_STE; /* SQE Test Error Register */ + AT91_REG EMAC_RLE; /* Receive Length Field Mismatch Register */ + AT91_REG EMAC_TPF; /* Transmitted Pause Frames Register */ + AT91_REG EMAC_HRB; /* Hash Address Bottom[31:0] */ + AT91_REG EMAC_HRT; /* Hash Address Top[63:32] */ + AT91_REG EMAC_SA1L; /* Specific Address 1 Bottom, First 4 bytes */ + AT91_REG EMAC_SA1H; /* Specific Address 1 Top, Last 2 bytes */ + AT91_REG EMAC_SA2L; /* Specific Address 2 Bottom, First 4 bytes */ + AT91_REG EMAC_SA2H; /* Specific Address 2 Top, Last 2 bytes */ + AT91_REG EMAC_SA3L; /* Specific Address 3 Bottom, First 4 bytes */ + AT91_REG EMAC_SA3H; /* Specific Address 3 Top, Last 2 bytes */ + AT91_REG EMAC_SA4L; /* Specific Address 4 Bottom, First 4 bytes */ + AT91_REG EMAC_SA4H; /* Specific Address 4 Top, Last 2 bytes */ + AT91_REG EMAC_TID; /* Type ID Checking Register */ + AT91_REG EMAC_TPQ; /* Transmit Pause Quantum Register */ + AT91_REG EMAC_USRIO; /* USER Input/Output Register */ + AT91_REG EMAC_WOL; /* Wake On LAN Register */ + AT91_REG Reserved1[ 13 ]; /* */ + AT91_REG EMAC_REV; /* Revision Register */ +} AT91S_EMAC, * AT91PS_EMAC; + +/* -------- EMAC_NCR : (EMAC Offset: 0x0) -------- */ +#define AT91C_EMAC_LB ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */ +#define AT91C_EMAC_LLB ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) Loopback local. */ +#define AT91C_EMAC_RE ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) Receive enable. */ +#define AT91C_EMAC_TE ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) Transmit enable. */ +#define AT91C_EMAC_MPE ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) Management port enable. */ +#define AT91C_EMAC_CLRSTAT ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) Clear statistics registers. */ +#define AT91C_EMAC_INCSTAT ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) Increment statistics registers. */ +#define AT91C_EMAC_WESTAT ( ( unsigned int ) 0x1 << 7 ) /* (EMAC) Write enable for statistics registers. */ +#define AT91C_EMAC_BP ( ( unsigned int ) 0x1 << 8 ) /* (EMAC) Back pressure. */ +#define AT91C_EMAC_TSTART ( ( unsigned int ) 0x1 << 9 ) /* (EMAC) Start Transmission. */ +#define AT91C_EMAC_THALT ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) Transmission Halt. */ +#define AT91C_EMAC_TPFR ( ( unsigned int ) 0x1 << 11 ) /* (EMAC) Transmit pause frame */ +#define AT91C_EMAC_TZQ ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) Transmit zero quantum pause frame */ +/* -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- */ +#define AT91C_EMAC_SPD ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) Speed. */ +#define AT91C_EMAC_FD ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) Full duplex. */ +#define AT91C_EMAC_JFRAME ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) Jumbo Frames. */ +#define AT91C_EMAC_CAF ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) Copy all frames. */ +#define AT91C_EMAC_NBC ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) No broadcast. */ +#define AT91C_EMAC_MTI ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) Multicast hash event enable */ +#define AT91C_EMAC_UNI ( ( unsigned int ) 0x1 << 7 ) /* (EMAC) Unicast hash enable. */ +#define AT91C_EMAC_BIG ( ( unsigned int ) 0x1 << 8 ) /* (EMAC) Receive 1522 bytes. */ +#define AT91C_EMAC_EAE ( ( unsigned int ) 0x1 << 9 ) /* (EMAC) External address match enable. */ +#define AT91C_EMAC_CLK ( ( unsigned int ) 0x3 << 10 ) /* (EMAC) */ +#define AT91C_EMAC_CLK_HCLK_8 ( ( unsigned int ) 0x0 << 10 ) /* (EMAC) HCLK divided by 8 */ +#define AT91C_EMAC_CLK_HCLK_16 ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) HCLK divided by 16 */ +#define AT91C_EMAC_CLK_HCLK_32 ( ( unsigned int ) 0x2 << 10 ) /* (EMAC) HCLK divided by 32 */ +#define AT91C_EMAC_CLK_HCLK_64 ( ( unsigned int ) 0x3 << 10 ) /* (EMAC) HCLK divided by 64 */ +#define AT91C_EMAC_RTY ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) */ +#define AT91C_EMAC_PAE ( ( unsigned int ) 0x1 << 13 ) /* (EMAC) */ +#define AT91C_EMAC_RBOF ( ( unsigned int ) 0x3 << 14 ) /* (EMAC) */ +#define AT91C_EMAC_RBOF_OFFSET_0 ( ( unsigned int ) 0x0 << 14 ) /* (EMAC) no offset from start of receive buffer */ +#define AT91C_EMAC_RBOF_OFFSET_1 ( ( unsigned int ) 0x1 << 14 ) /* (EMAC) one byte offset from start of receive buffer */ +#define AT91C_EMAC_RBOF_OFFSET_2 ( ( unsigned int ) 0x2 << 14 ) /* (EMAC) two bytes offset from start of receive buffer */ +#define AT91C_EMAC_RBOF_OFFSET_3 ( ( unsigned int ) 0x3 << 14 ) /* (EMAC) three bytes offset from start of receive buffer */ +#define AT91C_EMAC_RLCE ( ( unsigned int ) 0x1 << 16 ) /* (EMAC) Receive Length field Checking Enable */ +#define AT91C_EMAC_DRFCS ( ( unsigned int ) 0x1 << 17 ) /* (EMAC) Discard Receive FCS */ +#define AT91C_EMAC_EFRHD ( ( unsigned int ) 0x1 << 18 ) /* (EMAC) */ +#define AT91C_EMAC_IRXFCS ( ( unsigned int ) 0x1 << 19 ) /* (EMAC) Ignore RX FCS */ +/* -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- */ +#define AT91C_EMAC_LINKR ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_MDIO ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_IDLE ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */ +/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- */ +#define AT91C_EMAC_UBR ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_COL ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_RLES ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */ +#define AT91C_EMAC_TGO ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) Transmit Go */ +#define AT91C_EMAC_BEX ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) Buffers exhausted mid frame */ +#define AT91C_EMAC_COMP ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) */ +#define AT91C_EMAC_UND ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) */ +/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */ +#define AT91C_EMAC_BNA ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_REC ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_OVR ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */ +/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */ +#define AT91C_EMAC_MFD ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_RCOMP ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_RXUBR ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */ +#define AT91C_EMAC_TXUBR ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) */ +#define AT91C_EMAC_TUNDR ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) */ +#define AT91C_EMAC_RLEX ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) */ +#define AT91C_EMAC_TXERR ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) */ +#define AT91C_EMAC_TCOMP ( ( unsigned int ) 0x1 << 7 ) /* (EMAC) */ +#define AT91C_EMAC_LINK ( ( unsigned int ) 0x1 << 9 ) /* (EMAC) */ +#define AT91C_EMAC_ROVR ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) */ +#define AT91C_EMAC_HRESP ( ( unsigned int ) 0x1 << 11 ) /* (EMAC) */ +#define AT91C_EMAC_PFRE ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) */ +#define AT91C_EMAC_PTZ ( ( unsigned int ) 0x1 << 13 ) /* (EMAC) */ +/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */ +/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */ +/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */ +/* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */ +#define AT91C_EMAC_DATA ( ( unsigned int ) 0xFFFF << 0 ) /* (EMAC) */ +#define AT91C_EMAC_CODE ( ( unsigned int ) 0x3 << 16 ) /* (EMAC) */ +#define AT91C_EMAC_REGA ( ( unsigned int ) 0x1F << 18 ) /* (EMAC) */ +#define AT91C_EMAC_PHYA ( ( unsigned int ) 0x1F << 23 ) /* (EMAC) */ +#define AT91C_EMAC_RW ( ( unsigned int ) 0x3 << 28 ) /* (EMAC) */ +#define AT91C_EMAC_SOF ( ( unsigned int ) 0x3 << 30 ) /* (EMAC) */ +/* -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- */ +#define AT91C_EMAC_RMII ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) Reduce MII */ +/* -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- */ +#define AT91C_EMAC_IP ( ( unsigned int ) 0xFFFF << 0 ) /* (EMAC) ARP request IP address */ +#define AT91C_EMAC_MAG ( ( unsigned int ) 0x1 << 16 ) /* (EMAC) Magic packet event enable */ +#define AT91C_EMAC_ARP ( ( unsigned int ) 0x1 << 17 ) /* (EMAC) ARP request event enable */ +#define AT91C_EMAC_SA1 ( ( unsigned int ) 0x1 << 18 ) /* (EMAC) Specific address register 1 event enable */ +/* -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- */ +#define AT91C_EMAC_REVREF ( ( unsigned int ) 0xFFFF << 0 ) /* (EMAC) */ +#define AT91C_EMAC_PARTREF ( ( unsigned int ) 0xFFFF << 16 ) /* (EMAC) */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Analog to Digital Convertor */ +/* ***************************************************************************** */ +typedef struct _AT91S_ADC +{ + AT91_REG ADC_CR; /* ADC Control Register */ + AT91_REG ADC_MR; /* ADC Mode Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG ADC_CHER; /* ADC Channel Enable Register */ + AT91_REG ADC_CHDR; /* ADC Channel Disable Register */ + AT91_REG ADC_CHSR; /* ADC Channel Status Register */ + AT91_REG ADC_SR; /* ADC Status Register */ + AT91_REG ADC_LCDR; /* ADC Last Converted Data Register */ + AT91_REG ADC_IER; /* ADC Interrupt Enable Register */ + AT91_REG ADC_IDR; /* ADC Interrupt Disable Register */ + AT91_REG ADC_IMR; /* ADC Interrupt Mask Register */ + AT91_REG ADC_CDR0; /* ADC Channel Data Register 0 */ + AT91_REG ADC_CDR1; /* ADC Channel Data Register 1 */ + AT91_REG ADC_CDR2; /* ADC Channel Data Register 2 */ + AT91_REG ADC_CDR3; /* ADC Channel Data Register 3 */ + AT91_REG ADC_CDR4; /* ADC Channel Data Register 4 */ + AT91_REG ADC_CDR5; /* ADC Channel Data Register 5 */ + AT91_REG ADC_CDR6; /* ADC Channel Data Register 6 */ + AT91_REG ADC_CDR7; /* ADC Channel Data Register 7 */ + AT91_REG Reserved1[ 44 ]; /* */ + AT91_REG ADC_RPR; /* Receive Pointer Register */ + AT91_REG ADC_RCR; /* Receive Counter Register */ + AT91_REG ADC_TPR; /* Transmit Pointer Register */ + AT91_REG ADC_TCR; /* Transmit Counter Register */ + AT91_REG ADC_RNPR; /* Receive Next Pointer Register */ + AT91_REG ADC_RNCR; /* Receive Next Counter Register */ + AT91_REG ADC_TNPR; /* Transmit Next Pointer Register */ + AT91_REG ADC_TNCR; /* Transmit Next Counter Register */ + AT91_REG ADC_PTCR; /* PDC Transfer Control Register */ + AT91_REG ADC_PTSR; /* PDC Transfer Status Register */ +} AT91S_ADC, * AT91PS_ADC; + +/* -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- */ +#define AT91C_ADC_SWRST ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Software Reset */ +#define AT91C_ADC_START ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Start Conversion */ +/* -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- */ +#define AT91C_ADC_TRGEN ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Trigger Enable */ +#define AT91C_ADC_TRGEN_DIS ( ( unsigned int ) 0x0 ) /* (ADC) Hardware triggers are disabled. Starting a conversion is only possible by software */ +#define AT91C_ADC_TRGEN_EN ( ( unsigned int ) 0x1 ) /* (ADC) Hardware trigger selected by TRGSEL field is enabled. */ +#define AT91C_ADC_TRGSEL ( ( unsigned int ) 0x7 << 1 ) /* (ADC) Trigger Selection */ +#define AT91C_ADC_TRGSEL_TIOA0 ( ( unsigned int ) 0x0 << 1 ) /* (ADC) Selected TRGSEL = TIAO0 */ +#define AT91C_ADC_TRGSEL_TIOA1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Selected TRGSEL = TIAO1 */ +#define AT91C_ADC_TRGSEL_TIOA2 ( ( unsigned int ) 0x2 << 1 ) /* (ADC) Selected TRGSEL = TIAO2 */ +#define AT91C_ADC_TRGSEL_TIOA3 ( ( unsigned int ) 0x3 << 1 ) /* (ADC) Selected TRGSEL = TIAO3 */ +#define AT91C_ADC_TRGSEL_TIOA4 ( ( unsigned int ) 0x4 << 1 ) /* (ADC) Selected TRGSEL = TIAO4 */ +#define AT91C_ADC_TRGSEL_TIOA5 ( ( unsigned int ) 0x5 << 1 ) /* (ADC) Selected TRGSEL = TIAO5 */ +#define AT91C_ADC_TRGSEL_EXT ( ( unsigned int ) 0x6 << 1 ) /* (ADC) Selected TRGSEL = External Trigger */ +#define AT91C_ADC_LOWRES ( ( unsigned int ) 0x1 << 4 ) /* (ADC) Resolution. */ +#define AT91C_ADC_LOWRES_10_BIT ( ( unsigned int ) 0x0 << 4 ) /* (ADC) 10-bit resolution */ +#define AT91C_ADC_LOWRES_8_BIT ( ( unsigned int ) 0x1 << 4 ) /* (ADC) 8-bit resolution */ +#define AT91C_ADC_SLEEP ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Sleep Mode */ +#define AT91C_ADC_SLEEP_NORMAL_MODE ( ( unsigned int ) 0x0 << 5 ) /* (ADC) Normal Mode */ +#define AT91C_ADC_SLEEP_MODE ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Sleep Mode */ +#define AT91C_ADC_PRESCAL ( ( unsigned int ) 0x3F << 8 ) /* (ADC) Prescaler rate selection */ +#define AT91C_ADC_STARTUP ( ( unsigned int ) 0x1F << 16 ) /* (ADC) Startup Time */ +#define AT91C_ADC_SHTIM ( ( unsigned int ) 0xF << 24 ) /* (ADC) Sample & Hold Time */ +/* -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- */ +#define AT91C_ADC_CH0 ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Channel 0 */ +#define AT91C_ADC_CH1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Channel 1 */ +#define AT91C_ADC_CH2 ( ( unsigned int ) 0x1 << 2 ) /* (ADC) Channel 2 */ +#define AT91C_ADC_CH3 ( ( unsigned int ) 0x1 << 3 ) /* (ADC) Channel 3 */ +#define AT91C_ADC_CH4 ( ( unsigned int ) 0x1 << 4 ) /* (ADC) Channel 4 */ +#define AT91C_ADC_CH5 ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Channel 5 */ +#define AT91C_ADC_CH6 ( ( unsigned int ) 0x1 << 6 ) /* (ADC) Channel 6 */ +#define AT91C_ADC_CH7 ( ( unsigned int ) 0x1 << 7 ) /* (ADC) Channel 7 */ +/* -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- */ +/* -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- */ +/* -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- */ +#define AT91C_ADC_EOC0 ( ( unsigned int ) 0x1 << 0 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC2 ( ( unsigned int ) 0x1 << 2 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC3 ( ( unsigned int ) 0x1 << 3 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC4 ( ( unsigned int ) 0x1 << 4 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC5 ( ( unsigned int ) 0x1 << 5 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC6 ( ( unsigned int ) 0x1 << 6 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC7 ( ( unsigned int ) 0x1 << 7 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_OVRE0 ( ( unsigned int ) 0x1 << 8 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE1 ( ( unsigned int ) 0x1 << 9 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE2 ( ( unsigned int ) 0x1 << 10 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE3 ( ( unsigned int ) 0x1 << 11 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE4 ( ( unsigned int ) 0x1 << 12 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE5 ( ( unsigned int ) 0x1 << 13 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE6 ( ( unsigned int ) 0x1 << 14 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE7 ( ( unsigned int ) 0x1 << 15 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_DRDY ( ( unsigned int ) 0x1 << 16 ) /* (ADC) Data Ready */ +#define AT91C_ADC_GOVRE ( ( unsigned int ) 0x1 << 17 ) /* (ADC) General Overrun */ +#define AT91C_ADC_ENDRX ( ( unsigned int ) 0x1 << 18 ) /* (ADC) End of Receiver Transfer */ +#define AT91C_ADC_RXBUFF ( ( unsigned int ) 0x1 << 19 ) /* (ADC) RXBUFF Interrupt */ +/* -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- */ +#define AT91C_ADC_LDATA ( ( unsigned int ) 0x3FF << 0 ) /* (ADC) Last Data Converted */ +/* -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- */ +/* -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- */ +/* -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- */ +/* -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- */ +#define AT91C_ADC_DATA ( ( unsigned int ) 0x3FF << 0 ) /* (ADC) Converted Data */ +/* -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- */ +/* -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- */ +/* -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- */ +/* -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- */ +/* -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- */ +/* -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- */ +/* -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Advanced Encryption Standard */ +/* ***************************************************************************** */ +typedef struct _AT91S_AES +{ + AT91_REG AES_CR; /* Control Register */ + AT91_REG AES_MR; /* Mode Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG AES_IER; /* Interrupt Enable Register */ + AT91_REG AES_IDR; /* Interrupt Disable Register */ + AT91_REG AES_IMR; /* Interrupt Mask Register */ + AT91_REG AES_ISR; /* Interrupt Status Register */ + AT91_REG AES_KEYWxR[ 4 ]; /* Key Word x Register */ + AT91_REG Reserved1[ 4 ]; /* */ + AT91_REG AES_IDATAxR[ 4 ]; /* Input Data x Register */ + AT91_REG AES_ODATAxR[ 4 ]; /* Output Data x Register */ + AT91_REG AES_IVxR[ 4 ]; /* Initialization Vector x Register */ + AT91_REG Reserved2[ 35 ]; /* */ + AT91_REG AES_VR; /* AES Version Register */ + AT91_REG AES_RPR; /* Receive Pointer Register */ + AT91_REG AES_RCR; /* Receive Counter Register */ + AT91_REG AES_TPR; /* Transmit Pointer Register */ + AT91_REG AES_TCR; /* Transmit Counter Register */ + AT91_REG AES_RNPR; /* Receive Next Pointer Register */ + AT91_REG AES_RNCR; /* Receive Next Counter Register */ + AT91_REG AES_TNPR; /* Transmit Next Pointer Register */ + AT91_REG AES_TNCR; /* Transmit Next Counter Register */ + AT91_REG AES_PTCR; /* PDC Transfer Control Register */ + AT91_REG AES_PTSR; /* PDC Transfer Status Register */ +} AT91S_AES, * AT91PS_AES; + +/* -------- AES_CR : (AES Offset: 0x0) Control Register -------- */ +#define AT91C_AES_START ( ( unsigned int ) 0x1 << 0 ) /* (AES) Starts Processing */ +#define AT91C_AES_SWRST ( ( unsigned int ) 0x1 << 8 ) /* (AES) Software Reset */ +#define AT91C_AES_LOADSEED ( ( unsigned int ) 0x1 << 16 ) /* (AES) Random Number Generator Seed Loading */ +/* -------- AES_MR : (AES Offset: 0x4) Mode Register -------- */ +#define AT91C_AES_CIPHER ( ( unsigned int ) 0x1 << 0 ) /* (AES) Processing Mode */ +#define AT91C_AES_PROCDLY ( ( unsigned int ) 0xF << 4 ) /* (AES) Processing Delay */ +#define AT91C_AES_SMOD ( ( unsigned int ) 0x3 << 8 ) /* (AES) Start Mode */ +#define AT91C_AES_SMOD_MANUAL ( ( unsigned int ) 0x0 << 8 ) /* (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. */ +#define AT91C_AES_SMOD_AUTO ( ( unsigned int ) 0x1 << 8 ) /* (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). */ +#define AT91C_AES_SMOD_PDC ( ( unsigned int ) 0x2 << 8 ) /* (AES) PDC Mode (cf datasheet). */ +#define AT91C_AES_OPMOD ( ( unsigned int ) 0x7 << 12 ) /* (AES) Operation Mode */ +#define AT91C_AES_OPMOD_ECB ( ( unsigned int ) 0x0 << 12 ) /* (AES) ECB Electronic CodeBook mode. */ +#define AT91C_AES_OPMOD_CBC ( ( unsigned int ) 0x1 << 12 ) /* (AES) CBC Cipher Block Chaining mode. */ +#define AT91C_AES_OPMOD_OFB ( ( unsigned int ) 0x2 << 12 ) /* (AES) OFB Output Feedback mode. */ +#define AT91C_AES_OPMOD_CFB ( ( unsigned int ) 0x3 << 12 ) /* (AES) CFB Cipher Feedback mode. */ +#define AT91C_AES_OPMOD_CTR ( ( unsigned int ) 0x4 << 12 ) /* (AES) CTR Counter mode. */ +#define AT91C_AES_LOD ( ( unsigned int ) 0x1 << 15 ) /* (AES) Last Output Data Mode */ +#define AT91C_AES_CFBS ( ( unsigned int ) 0x7 << 16 ) /* (AES) Cipher Feedback Data Size */ +#define AT91C_AES_CFBS_128_BIT ( ( unsigned int ) 0x0 << 16 ) /* (AES) 128-bit. */ +#define AT91C_AES_CFBS_64_BIT ( ( unsigned int ) 0x1 << 16 ) /* (AES) 64-bit. */ +#define AT91C_AES_CFBS_32_BIT ( ( unsigned int ) 0x2 << 16 ) /* (AES) 32-bit. */ +#define AT91C_AES_CFBS_16_BIT ( ( unsigned int ) 0x3 << 16 ) /* (AES) 16-bit. */ +#define AT91C_AES_CFBS_8_BIT ( ( unsigned int ) 0x4 << 16 ) /* (AES) 8-bit. */ +#define AT91C_AES_CKEY ( ( unsigned int ) 0xF << 20 ) /* (AES) Countermeasure Key */ +#define AT91C_AES_CTYPE ( ( unsigned int ) 0x1F << 24 ) /* (AES) Countermeasure Type */ +#define AT91C_AES_CTYPE_TYPE1_EN ( ( unsigned int ) 0x1 << 24 ) /* (AES) Countermeasure type 1 is enabled. */ +#define AT91C_AES_CTYPE_TYPE2_EN ( ( unsigned int ) 0x2 << 24 ) /* (AES) Countermeasure type 2 is enabled. */ +#define AT91C_AES_CTYPE_TYPE3_EN ( ( unsigned int ) 0x4 << 24 ) /* (AES) Countermeasure type 3 is enabled. */ +#define AT91C_AES_CTYPE_TYPE4_EN ( ( unsigned int ) 0x8 << 24 ) /* (AES) Countermeasure type 4 is enabled. */ +#define AT91C_AES_CTYPE_TYPE5_EN ( ( unsigned int ) 0x10 << 24 ) /* (AES) Countermeasure type 5 is enabled. */ +/* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */ +#define AT91C_AES_DATRDY ( ( unsigned int ) 0x1 << 0 ) /* (AES) DATRDY */ +#define AT91C_AES_ENDRX ( ( unsigned int ) 0x1 << 1 ) /* (AES) PDC Read Buffer End */ +#define AT91C_AES_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (AES) PDC Write Buffer End */ +#define AT91C_AES_RXBUFF ( ( unsigned int ) 0x1 << 3 ) /* (AES) PDC Read Buffer Full */ +#define AT91C_AES_TXBUFE ( ( unsigned int ) 0x1 << 4 ) /* (AES) PDC Write Buffer Empty */ +#define AT91C_AES_URAD ( ( unsigned int ) 0x1 << 8 ) /* (AES) Unspecified Register Access Detection */ +/* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */ +/* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */ +/* -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- */ +#define AT91C_AES_URAT ( ( unsigned int ) 0x7 << 12 ) /* (AES) Unspecified Register Access Type Status */ +#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ( ( unsigned int ) 0x0 << 12 ) /* (AES) Input data register written during the data processing in PDC mode. */ +#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ( ( unsigned int ) 0x1 << 12 ) /* (AES) Output data register read during the data processing. */ +#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ( ( unsigned int ) 0x2 << 12 ) /* (AES) Mode register written during the data processing. */ +#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ( ( unsigned int ) 0x3 << 12 ) /* (AES) Output data register read during the sub-keys generation. */ +#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ( ( unsigned int ) 0x4 << 12 ) /* (AES) Mode register written during the sub-keys generation. */ +#define AT91C_AES_URAT_WO_REG_READ ( ( unsigned int ) 0x5 << 12 ) /* (AES) Write-only register read access. */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Triple Data Encryption Standard */ +/* ***************************************************************************** */ +typedef struct _AT91S_TDES +{ + AT91_REG TDES_CR; /* Control Register */ + AT91_REG TDES_MR; /* Mode Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG TDES_IER; /* Interrupt Enable Register */ + AT91_REG TDES_IDR; /* Interrupt Disable Register */ + AT91_REG TDES_IMR; /* Interrupt Mask Register */ + AT91_REG TDES_ISR; /* Interrupt Status Register */ + AT91_REG TDES_KEY1WxR[ 2 ]; /* Key 1 Word x Register */ + AT91_REG TDES_KEY2WxR[ 2 ]; /* Key 2 Word x Register */ + AT91_REG TDES_KEY3WxR[ 2 ]; /* Key 3 Word x Register */ + AT91_REG Reserved1[ 2 ]; /* */ + AT91_REG TDES_IDATAxR[ 2 ]; /* Input Data x Register */ + AT91_REG Reserved2[ 2 ]; /* */ + AT91_REG TDES_ODATAxR[ 2 ]; /* Output Data x Register */ + AT91_REG Reserved3[ 2 ]; /* */ + AT91_REG TDES_IVxR[ 2 ]; /* Initialization Vector x Register */ + AT91_REG Reserved4[ 37 ]; /* */ + AT91_REG TDES_VR; /* TDES Version Register */ + AT91_REG TDES_RPR; /* Receive Pointer Register */ + AT91_REG TDES_RCR; /* Receive Counter Register */ + AT91_REG TDES_TPR; /* Transmit Pointer Register */ + AT91_REG TDES_TCR; /* Transmit Counter Register */ + AT91_REG TDES_RNPR; /* Receive Next Pointer Register */ + AT91_REG TDES_RNCR; /* Receive Next Counter Register */ + AT91_REG TDES_TNPR; /* Transmit Next Pointer Register */ + AT91_REG TDES_TNCR; /* Transmit Next Counter Register */ + AT91_REG TDES_PTCR; /* PDC Transfer Control Register */ + AT91_REG TDES_PTSR; /* PDC Transfer Status Register */ +} AT91S_TDES, * AT91PS_TDES; + +/* -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- */ +#define AT91C_TDES_START ( ( unsigned int ) 0x1 << 0 ) /* (TDES) Starts Processing */ +#define AT91C_TDES_SWRST ( ( unsigned int ) 0x1 << 8 ) /* (TDES) Software Reset */ +/* -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- */ +#define AT91C_TDES_CIPHER ( ( unsigned int ) 0x1 << 0 ) /* (TDES) Processing Mode */ +#define AT91C_TDES_TDESMOD ( ( unsigned int ) 0x1 << 1 ) /* (TDES) Single or Triple DES Mode */ +#define AT91C_TDES_KEYMOD ( ( unsigned int ) 0x1 << 4 ) /* (TDES) Key Mode */ +#define AT91C_TDES_SMOD ( ( unsigned int ) 0x3 << 8 ) /* (TDES) Start Mode */ +#define AT91C_TDES_SMOD_MANUAL ( ( unsigned int ) 0x0 << 8 ) /* (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. */ +#define AT91C_TDES_SMOD_AUTO ( ( unsigned int ) 0x1 << 8 ) /* (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). */ +#define AT91C_TDES_SMOD_PDC ( ( unsigned int ) 0x2 << 8 ) /* (TDES) PDC Mode (cf datasheet). */ +#define AT91C_TDES_OPMOD ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Operation Mode */ +#define AT91C_TDES_OPMOD_ECB ( ( unsigned int ) 0x0 << 12 ) /* (TDES) ECB Electronic CodeBook mode. */ +#define AT91C_TDES_OPMOD_CBC ( ( unsigned int ) 0x1 << 12 ) /* (TDES) CBC Cipher Block Chaining mode. */ +#define AT91C_TDES_OPMOD_OFB ( ( unsigned int ) 0x2 << 12 ) /* (TDES) OFB Output Feedback mode. */ +#define AT91C_TDES_OPMOD_CFB ( ( unsigned int ) 0x3 << 12 ) /* (TDES) CFB Cipher Feedback mode. */ +#define AT91C_TDES_LOD ( ( unsigned int ) 0x1 << 15 ) /* (TDES) Last Output Data Mode */ +#define AT91C_TDES_CFBS ( ( unsigned int ) 0x3 << 16 ) /* (TDES) Cipher Feedback Data Size */ +#define AT91C_TDES_CFBS_64_BIT ( ( unsigned int ) 0x0 << 16 ) /* (TDES) 64-bit. */ +#define AT91C_TDES_CFBS_32_BIT ( ( unsigned int ) 0x1 << 16 ) /* (TDES) 32-bit. */ +#define AT91C_TDES_CFBS_16_BIT ( ( unsigned int ) 0x2 << 16 ) /* (TDES) 16-bit. */ +#define AT91C_TDES_CFBS_8_BIT ( ( unsigned int ) 0x3 << 16 ) /* (TDES) 8-bit. */ +/* -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- */ +#define AT91C_TDES_DATRDY ( ( unsigned int ) 0x1 << 0 ) /* (TDES) DATRDY */ +#define AT91C_TDES_ENDRX ( ( unsigned int ) 0x1 << 1 ) /* (TDES) PDC Read Buffer End */ +#define AT91C_TDES_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (TDES) PDC Write Buffer End */ +#define AT91C_TDES_RXBUFF ( ( unsigned int ) 0x1 << 3 ) /* (TDES) PDC Read Buffer Full */ +#define AT91C_TDES_TXBUFE ( ( unsigned int ) 0x1 << 4 ) /* (TDES) PDC Write Buffer Empty */ +#define AT91C_TDES_URAD ( ( unsigned int ) 0x1 << 8 ) /* (TDES) Unspecified Register Access Detection */ +/* -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- */ +/* -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- */ +/* -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- */ +#define AT91C_TDES_URAT ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Unspecified Register Access Type Status */ +#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ( ( unsigned int ) 0x0 << 12 ) /* (TDES) Input data register written during the data processing in PDC mode. */ +#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ( ( unsigned int ) 0x1 << 12 ) /* (TDES) Output data register read during the data processing. */ +#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ( ( unsigned int ) 0x2 << 12 ) /* (TDES) Mode register written during the data processing. */ +#define AT91C_TDES_URAT_WO_REG_READ ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Write-only register read access. */ + +/* ***************************************************************************** */ +/* REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 */ +/* ***************************************************************************** */ +/* ========== Register definition for SYS peripheral ========== */ +/* ========== Register definition for AIC peripheral ========== */ +#define AT91C_AIC_IVR ( ( AT91_REG * ) 0xFFFFF100 ) /* (AIC) IRQ Vector Register */ +#define AT91C_AIC_SMR ( ( AT91_REG * ) 0xFFFFF000 ) /* (AIC) Source Mode Register */ +#define AT91C_AIC_FVR ( ( AT91_REG * ) 0xFFFFF104 ) /* (AIC) FIQ Vector Register */ +#define AT91C_AIC_DCR ( ( AT91_REG * ) 0xFFFFF138 ) /* (AIC) Debug Control Register (Protect) */ +#define AT91C_AIC_EOICR ( ( AT91_REG * ) 0xFFFFF130 ) /* (AIC) End of Interrupt Command Register */ +#define AT91C_AIC_SVR ( ( AT91_REG * ) 0xFFFFF080 ) /* (AIC) Source Vector Register */ +#define AT91C_AIC_FFSR ( ( AT91_REG * ) 0xFFFFF148 ) /* (AIC) Fast Forcing Status Register */ +#define AT91C_AIC_ICCR ( ( AT91_REG * ) 0xFFFFF128 ) /* (AIC) Interrupt Clear Command Register */ +#define AT91C_AIC_ISR ( ( AT91_REG * ) 0xFFFFF108 ) /* (AIC) Interrupt Status Register */ +#define AT91C_AIC_IMR ( ( AT91_REG * ) 0xFFFFF110 ) /* (AIC) Interrupt Mask Register */ +#define AT91C_AIC_IPR ( ( AT91_REG * ) 0xFFFFF10C ) /* (AIC) Interrupt Pending Register */ +#define AT91C_AIC_FFER ( ( AT91_REG * ) 0xFFFFF140 ) /* (AIC) Fast Forcing Enable Register */ +#define AT91C_AIC_IECR ( ( AT91_REG * ) 0xFFFFF120 ) /* (AIC) Interrupt Enable Command Register */ +#define AT91C_AIC_ISCR ( ( AT91_REG * ) 0xFFFFF12C ) /* (AIC) Interrupt Set Command Register */ +#define AT91C_AIC_FFDR ( ( AT91_REG * ) 0xFFFFF144 ) /* (AIC) Fast Forcing Disable Register */ +#define AT91C_AIC_CISR ( ( AT91_REG * ) 0xFFFFF114 ) /* (AIC) Core Interrupt Status Register */ +#define AT91C_AIC_IDCR ( ( AT91_REG * ) 0xFFFFF124 ) /* (AIC) Interrupt Disable Command Register */ +#define AT91C_AIC_SPU ( ( AT91_REG * ) 0xFFFFF134 ) /* (AIC) Spurious Vector Register */ +/* ========== Register definition for PDC_DBGU peripheral ========== */ +#define AT91C_DBGU_TCR ( ( AT91_REG * ) 0xFFFFF30C ) /* (PDC_DBGU) Transmit Counter Register */ +#define AT91C_DBGU_RNPR ( ( AT91_REG * ) 0xFFFFF310 ) /* (PDC_DBGU) Receive Next Pointer Register */ +#define AT91C_DBGU_TNPR ( ( AT91_REG * ) 0xFFFFF318 ) /* (PDC_DBGU) Transmit Next Pointer Register */ +#define AT91C_DBGU_TPR ( ( AT91_REG * ) 0xFFFFF308 ) /* (PDC_DBGU) Transmit Pointer Register */ +#define AT91C_DBGU_RPR ( ( AT91_REG * ) 0xFFFFF300 ) /* (PDC_DBGU) Receive Pointer Register */ +#define AT91C_DBGU_RCR ( ( AT91_REG * ) 0xFFFFF304 ) /* (PDC_DBGU) Receive Counter Register */ +#define AT91C_DBGU_RNCR ( ( AT91_REG * ) 0xFFFFF314 ) /* (PDC_DBGU) Receive Next Counter Register */ +#define AT91C_DBGU_PTCR ( ( AT91_REG * ) 0xFFFFF320 ) /* (PDC_DBGU) PDC Transfer Control Register */ +#define AT91C_DBGU_PTSR ( ( AT91_REG * ) 0xFFFFF324 ) /* (PDC_DBGU) PDC Transfer Status Register */ +#define AT91C_DBGU_TNCR ( ( AT91_REG * ) 0xFFFFF31C ) /* (PDC_DBGU) Transmit Next Counter Register */ +/* ========== Register definition for DBGU peripheral ========== */ +#define AT91C_DBGU_EXID ( ( AT91_REG * ) 0xFFFFF244 ) /* (DBGU) Chip ID Extension Register */ +#define AT91C_DBGU_BRGR ( ( AT91_REG * ) 0xFFFFF220 ) /* (DBGU) Baud Rate Generator Register */ +#define AT91C_DBGU_IDR ( ( AT91_REG * ) 0xFFFFF20C ) /* (DBGU) Interrupt Disable Register */ +#define AT91C_DBGU_CSR ( ( AT91_REG * ) 0xFFFFF214 ) /* (DBGU) Channel Status Register */ +#define AT91C_DBGU_CIDR ( ( AT91_REG * ) 0xFFFFF240 ) /* (DBGU) Chip ID Register */ +#define AT91C_DBGU_MR ( ( AT91_REG * ) 0xFFFFF204 ) /* (DBGU) Mode Register */ +#define AT91C_DBGU_IMR ( ( AT91_REG * ) 0xFFFFF210 ) /* (DBGU) Interrupt Mask Register */ +#define AT91C_DBGU_CR ( ( AT91_REG * ) 0xFFFFF200 ) /* (DBGU) Control Register */ +#define AT91C_DBGU_FNTR ( ( AT91_REG * ) 0xFFFFF248 ) /* (DBGU) Force NTRST Register */ +#define AT91C_DBGU_THR ( ( AT91_REG * ) 0xFFFFF21C ) /* (DBGU) Transmitter Holding Register */ +#define AT91C_DBGU_RHR ( ( AT91_REG * ) 0xFFFFF218 ) /* (DBGU) Receiver Holding Register */ +#define AT91C_DBGU_IER ( ( AT91_REG * ) 0xFFFFF208 ) /* (DBGU) Interrupt Enable Register */ +/* ========== Register definition for PIOA peripheral ========== */ +#define AT91C_PIOA_ODR ( ( AT91_REG * ) 0xFFFFF414 ) /* (PIOA) Output Disable Registerr */ +#define AT91C_PIOA_SODR ( ( AT91_REG * ) 0xFFFFF430 ) /* (PIOA) Set Output Data Register */ +#define AT91C_PIOA_ISR ( ( AT91_REG * ) 0xFFFFF44C ) /* (PIOA) Interrupt Status Register */ +#define AT91C_PIOA_ABSR ( ( AT91_REG * ) 0xFFFFF478 ) /* (PIOA) AB Select Status Register */ +#define AT91C_PIOA_IER ( ( AT91_REG * ) 0xFFFFF440 ) /* (PIOA) Interrupt Enable Register */ +#define AT91C_PIOA_PPUDR ( ( AT91_REG * ) 0xFFFFF460 ) /* (PIOA) Pull-up Disable Register */ +#define AT91C_PIOA_IMR ( ( AT91_REG * ) 0xFFFFF448 ) /* (PIOA) Interrupt Mask Register */ +#define AT91C_PIOA_PER ( ( AT91_REG * ) 0xFFFFF400 ) /* (PIOA) PIO Enable Register */ +#define AT91C_PIOA_IFDR ( ( AT91_REG * ) 0xFFFFF424 ) /* (PIOA) Input Filter Disable Register */ +#define AT91C_PIOA_OWDR ( ( AT91_REG * ) 0xFFFFF4A4 ) /* (PIOA) Output Write Disable Register */ +#define AT91C_PIOA_MDSR ( ( AT91_REG * ) 0xFFFFF458 ) /* (PIOA) Multi-driver Status Register */ +#define AT91C_PIOA_IDR ( ( AT91_REG * ) 0xFFFFF444 ) /* (PIOA) Interrupt Disable Register */ +#define AT91C_PIOA_ODSR ( ( AT91_REG * ) 0xFFFFF438 ) /* (PIOA) Output Data Status Register */ +#define AT91C_PIOA_PPUSR ( ( AT91_REG * ) 0xFFFFF468 ) /* (PIOA) Pull-up Status Register */ +#define AT91C_PIOA_OWSR ( ( AT91_REG * ) 0xFFFFF4A8 ) /* (PIOA) Output Write Status Register */ +#define AT91C_PIOA_BSR ( ( AT91_REG * ) 0xFFFFF474 ) /* (PIOA) Select B Register */ +#define AT91C_PIOA_OWER ( ( AT91_REG * ) 0xFFFFF4A0 ) /* (PIOA) Output Write Enable Register */ +#define AT91C_PIOA_IFER ( ( AT91_REG * ) 0xFFFFF420 ) /* (PIOA) Input Filter Enable Register */ +#define AT91C_PIOA_PDSR ( ( AT91_REG * ) 0xFFFFF43C ) /* (PIOA) Pin Data Status Register */ +#define AT91C_PIOA_PPUER ( ( AT91_REG * ) 0xFFFFF464 ) /* (PIOA) Pull-up Enable Register */ +#define AT91C_PIOA_OSR ( ( AT91_REG * ) 0xFFFFF418 ) /* (PIOA) Output Status Register */ +#define AT91C_PIOA_ASR ( ( AT91_REG * ) 0xFFFFF470 ) /* (PIOA) Select A Register */ +#define AT91C_PIOA_MDDR ( ( AT91_REG * ) 0xFFFFF454 ) /* (PIOA) Multi-driver Disable Register */ +#define AT91C_PIOA_CODR ( ( AT91_REG * ) 0xFFFFF434 ) /* (PIOA) Clear Output Data Register */ +#define AT91C_PIOA_MDER ( ( AT91_REG * ) 0xFFFFF450 ) /* (PIOA) Multi-driver Enable Register */ +#define AT91C_PIOA_PDR ( ( AT91_REG * ) 0xFFFFF404 ) /* (PIOA) PIO Disable Register */ +#define AT91C_PIOA_IFSR ( ( AT91_REG * ) 0xFFFFF428 ) /* (PIOA) Input Filter Status Register */ +#define AT91C_PIOA_OER ( ( AT91_REG * ) 0xFFFFF410 ) /* (PIOA) Output Enable Register */ +#define AT91C_PIOA_PSR ( ( AT91_REG * ) 0xFFFFF408 ) /* (PIOA) PIO Status Register */ +/* ========== Register definition for PIOB peripheral ========== */ +#define AT91C_PIOB_OWDR ( ( AT91_REG * ) 0xFFFFF6A4 ) /* (PIOB) Output Write Disable Register */ +#define AT91C_PIOB_MDER ( ( AT91_REG * ) 0xFFFFF650 ) /* (PIOB) Multi-driver Enable Register */ +#define AT91C_PIOB_PPUSR ( ( AT91_REG * ) 0xFFFFF668 ) /* (PIOB) Pull-up Status Register */ +#define AT91C_PIOB_IMR ( ( AT91_REG * ) 0xFFFFF648 ) /* (PIOB) Interrupt Mask Register */ +#define AT91C_PIOB_ASR ( ( AT91_REG * ) 0xFFFFF670 ) /* (PIOB) Select A Register */ +#define AT91C_PIOB_PPUDR ( ( AT91_REG * ) 0xFFFFF660 ) /* (PIOB) Pull-up Disable Register */ +#define AT91C_PIOB_PSR ( ( AT91_REG * ) 0xFFFFF608 ) /* (PIOB) PIO Status Register */ +#define AT91C_PIOB_IER ( ( AT91_REG * ) 0xFFFFF640 ) /* (PIOB) Interrupt Enable Register */ +#define AT91C_PIOB_CODR ( ( AT91_REG * ) 0xFFFFF634 ) /* (PIOB) Clear Output Data Register */ +#define AT91C_PIOB_OWER ( ( AT91_REG * ) 0xFFFFF6A0 ) /* (PIOB) Output Write Enable Register */ +#define AT91C_PIOB_ABSR ( ( AT91_REG * ) 0xFFFFF678 ) /* (PIOB) AB Select Status Register */ +#define AT91C_PIOB_IFDR ( ( AT91_REG * ) 0xFFFFF624 ) /* (PIOB) Input Filter Disable Register */ +#define AT91C_PIOB_PDSR ( ( AT91_REG * ) 0xFFFFF63C ) /* (PIOB) Pin Data Status Register */ +#define AT91C_PIOB_IDR ( ( AT91_REG * ) 0xFFFFF644 ) /* (PIOB) Interrupt Disable Register */ +#define AT91C_PIOB_OWSR ( ( AT91_REG * ) 0xFFFFF6A8 ) /* (PIOB) Output Write Status Register */ +#define AT91C_PIOB_PDR ( ( AT91_REG * ) 0xFFFFF604 ) /* (PIOB) PIO Disable Register */ +#define AT91C_PIOB_ODR ( ( AT91_REG * ) 0xFFFFF614 ) /* (PIOB) Output Disable Registerr */ +#define AT91C_PIOB_IFSR ( ( AT91_REG * ) 0xFFFFF628 ) /* (PIOB) Input Filter Status Register */ +#define AT91C_PIOB_PPUER ( ( AT91_REG * ) 0xFFFFF664 ) /* (PIOB) Pull-up Enable Register */ +#define AT91C_PIOB_SODR ( ( AT91_REG * ) 0xFFFFF630 ) /* (PIOB) Set Output Data Register */ +#define AT91C_PIOB_ISR ( ( AT91_REG * ) 0xFFFFF64C ) /* (PIOB) Interrupt Status Register */ +#define AT91C_PIOB_ODSR ( ( AT91_REG * ) 0xFFFFF638 ) /* (PIOB) Output Data Status Register */ +#define AT91C_PIOB_OSR ( ( AT91_REG * ) 0xFFFFF618 ) /* (PIOB) Output Status Register */ +#define AT91C_PIOB_MDSR ( ( AT91_REG * ) 0xFFFFF658 ) /* (PIOB) Multi-driver Status Register */ +#define AT91C_PIOB_IFER ( ( AT91_REG * ) 0xFFFFF620 ) /* (PIOB) Input Filter Enable Register */ +#define AT91C_PIOB_BSR ( ( AT91_REG * ) 0xFFFFF674 ) /* (PIOB) Select B Register */ +#define AT91C_PIOB_MDDR ( ( AT91_REG * ) 0xFFFFF654 ) /* (PIOB) Multi-driver Disable Register */ +#define AT91C_PIOB_OER ( ( AT91_REG * ) 0xFFFFF610 ) /* (PIOB) Output Enable Register */ +#define AT91C_PIOB_PER ( ( AT91_REG * ) 0xFFFFF600 ) /* (PIOB) PIO Enable Register */ +/* ========== Register definition for CKGR peripheral ========== */ +#define AT91C_CKGR_MOR ( ( AT91_REG * ) 0xFFFFFC20 ) /* (CKGR) Main Oscillator Register */ +#define AT91C_CKGR_PLLR ( ( AT91_REG * ) 0xFFFFFC2C ) /* (CKGR) PLL Register */ +#define AT91C_CKGR_MCFR ( ( AT91_REG * ) 0xFFFFFC24 ) /* (CKGR) Main Clock Frequency Register */ +/* ========== Register definition for PMC peripheral ========== */ +#define AT91C_PMC_IDR ( ( AT91_REG * ) 0xFFFFFC64 ) /* (PMC) Interrupt Disable Register */ +#define AT91C_PMC_MOR ( ( AT91_REG * ) 0xFFFFFC20 ) /* (PMC) Main Oscillator Register */ +#define AT91C_PMC_PLLR ( ( AT91_REG * ) 0xFFFFFC2C ) /* (PMC) PLL Register */ +#define AT91C_PMC_PCER ( ( AT91_REG * ) 0xFFFFFC10 ) /* (PMC) Peripheral Clock Enable Register */ +#define AT91C_PMC_PCKR ( ( AT91_REG * ) 0xFFFFFC40 ) /* (PMC) Programmable Clock Register */ +#define AT91C_PMC_MCKR ( ( AT91_REG * ) 0xFFFFFC30 ) /* (PMC) Master Clock Register */ +#define AT91C_PMC_SCDR ( ( AT91_REG * ) 0xFFFFFC04 ) /* (PMC) System Clock Disable Register */ +#define AT91C_PMC_PCDR ( ( AT91_REG * ) 0xFFFFFC14 ) /* (PMC) Peripheral Clock Disable Register */ +#define AT91C_PMC_SCSR ( ( AT91_REG * ) 0xFFFFFC08 ) /* (PMC) System Clock Status Register */ +#define AT91C_PMC_PCSR ( ( AT91_REG * ) 0xFFFFFC18 ) /* (PMC) Peripheral Clock Status Register */ +#define AT91C_PMC_MCFR ( ( AT91_REG * ) 0xFFFFFC24 ) /* (PMC) Main Clock Frequency Register */ +#define AT91C_PMC_SCER ( ( AT91_REG * ) 0xFFFFFC00 ) /* (PMC) System Clock Enable Register */ +#define AT91C_PMC_IMR ( ( AT91_REG * ) 0xFFFFFC6C ) /* (PMC) Interrupt Mask Register */ +#define AT91C_PMC_IER ( ( AT91_REG * ) 0xFFFFFC60 ) /* (PMC) Interrupt Enable Register */ +#define AT91C_PMC_SR ( ( AT91_REG * ) 0xFFFFFC68 ) /* (PMC) Status Register */ +/* ========== Register definition for RSTC peripheral ========== */ +#define AT91C_RSTC_RCR ( ( AT91_REG * ) 0xFFFFFD00 ) /* (RSTC) Reset Control Register */ +#define AT91C_RSTC_RMR ( ( AT91_REG * ) 0xFFFFFD08 ) /* (RSTC) Reset Mode Register */ +#define AT91C_RSTC_RSR ( ( AT91_REG * ) 0xFFFFFD04 ) /* (RSTC) Reset Status Register */ +/* ========== Register definition for RTTC peripheral ========== */ +#define AT91C_RTTC_RTSR ( ( AT91_REG * ) 0xFFFFFD2C ) /* (RTTC) Real-time Status Register */ +#define AT91C_RTTC_RTMR ( ( AT91_REG * ) 0xFFFFFD20 ) /* (RTTC) Real-time Mode Register */ +#define AT91C_RTTC_RTVR ( ( AT91_REG * ) 0xFFFFFD28 ) /* (RTTC) Real-time Value Register */ +#define AT91C_RTTC_RTAR ( ( AT91_REG * ) 0xFFFFFD24 ) /* (RTTC) Real-time Alarm Register */ +/* ========== Register definition for PITC peripheral ========== */ +#define AT91C_PITC_PIVR ( ( AT91_REG * ) 0xFFFFFD38 ) /* (PITC) Period Interval Value Register */ +#define AT91C_PITC_PISR ( ( AT91_REG * ) 0xFFFFFD34 ) /* (PITC) Period Interval Status Register */ +#define AT91C_PITC_PIIR ( ( AT91_REG * ) 0xFFFFFD3C ) /* (PITC) Period Interval Image Register */ +#define AT91C_PITC_PIMR ( ( AT91_REG * ) 0xFFFFFD30 ) /* (PITC) Period Interval Mode Register */ +/* ========== Register definition for WDTC peripheral ========== */ +#define AT91C_WDTC_WDCR ( ( AT91_REG * ) 0xFFFFFD40 ) /* (WDTC) Watchdog Control Register */ +#define AT91C_WDTC_WDSR ( ( AT91_REG * ) 0xFFFFFD48 ) /* (WDTC) Watchdog Status Register */ +#define AT91C_WDTC_WDMR ( ( AT91_REG * ) 0xFFFFFD44 ) /* (WDTC) Watchdog Mode Register */ +/* ========== Register definition for VREG peripheral ========== */ +#define AT91C_VREG_MR ( ( AT91_REG * ) 0xFFFFFD60 ) /* (VREG) Voltage Regulator Mode Register */ +/* ========== Register definition for MC peripheral ========== */ +#define AT91C_MC_ASR ( ( AT91_REG * ) 0xFFFFFF04 ) /* (MC) MC Abort Status Register */ +#define AT91C_MC_RCR ( ( AT91_REG * ) 0xFFFFFF00 ) /* (MC) MC Remap Control Register */ +#define AT91C_MC_FCR ( ( AT91_REG * ) 0xFFFFFF64 ) /* (MC) MC Flash Command Register */ +#define AT91C_MC_AASR ( ( AT91_REG * ) 0xFFFFFF08 ) /* (MC) MC Abort Address Status Register */ +#define AT91C_MC_FSR ( ( AT91_REG * ) 0xFFFFFF68 ) /* (MC) MC Flash Status Register */ +#define AT91C_MC_FMR ( ( AT91_REG * ) 0xFFFFFF60 ) /* (MC) MC Flash Mode Register */ +/* ========== Register definition for PDC_SPI1 peripheral ========== */ +#define AT91C_SPI1_PTCR ( ( AT91_REG * ) 0xFFFE4120 ) /* (PDC_SPI1) PDC Transfer Control Register */ +#define AT91C_SPI1_RPR ( ( AT91_REG * ) 0xFFFE4100 ) /* (PDC_SPI1) Receive Pointer Register */ +#define AT91C_SPI1_TNCR ( ( AT91_REG * ) 0xFFFE411C ) /* (PDC_SPI1) Transmit Next Counter Register */ +#define AT91C_SPI1_TPR ( ( AT91_REG * ) 0xFFFE4108 ) /* (PDC_SPI1) Transmit Pointer Register */ +#define AT91C_SPI1_TNPR ( ( AT91_REG * ) 0xFFFE4118 ) /* (PDC_SPI1) Transmit Next Pointer Register */ +#define AT91C_SPI1_TCR ( ( AT91_REG * ) 0xFFFE410C ) /* (PDC_SPI1) Transmit Counter Register */ +#define AT91C_SPI1_RCR ( ( AT91_REG * ) 0xFFFE4104 ) /* (PDC_SPI1) Receive Counter Register */ +#define AT91C_SPI1_RNPR ( ( AT91_REG * ) 0xFFFE4110 ) /* (PDC_SPI1) Receive Next Pointer Register */ +#define AT91C_SPI1_RNCR ( ( AT91_REG * ) 0xFFFE4114 ) /* (PDC_SPI1) Receive Next Counter Register */ +#define AT91C_SPI1_PTSR ( ( AT91_REG * ) 0xFFFE4124 ) /* (PDC_SPI1) PDC Transfer Status Register */ +/* ========== Register definition for SPI1 peripheral ========== */ +#define AT91C_SPI1_IMR ( ( AT91_REG * ) 0xFFFE401C ) /* (SPI1) Interrupt Mask Register */ +#define AT91C_SPI1_IER ( ( AT91_REG * ) 0xFFFE4014 ) /* (SPI1) Interrupt Enable Register */ +#define AT91C_SPI1_MR ( ( AT91_REG * ) 0xFFFE4004 ) /* (SPI1) Mode Register */ +#define AT91C_SPI1_RDR ( ( AT91_REG * ) 0xFFFE4008 ) /* (SPI1) Receive Data Register */ +#define AT91C_SPI1_IDR ( ( AT91_REG * ) 0xFFFE4018 ) /* (SPI1) Interrupt Disable Register */ +#define AT91C_SPI1_SR ( ( AT91_REG * ) 0xFFFE4010 ) /* (SPI1) Status Register */ +#define AT91C_SPI1_TDR ( ( AT91_REG * ) 0xFFFE400C ) /* (SPI1) Transmit Data Register */ +#define AT91C_SPI1_CR ( ( AT91_REG * ) 0xFFFE4000 ) /* (SPI1) Control Register */ +#define AT91C_SPI1_CSR ( ( AT91_REG * ) 0xFFFE4030 ) /* (SPI1) Chip Select Register */ +/* ========== Register definition for PDC_SPI0 peripheral ========== */ +#define AT91C_SPI0_PTCR ( ( AT91_REG * ) 0xFFFE0120 ) /* (PDC_SPI0) PDC Transfer Control Register */ +#define AT91C_SPI0_TPR ( ( AT91_REG * ) 0xFFFE0108 ) /* (PDC_SPI0) Transmit Pointer Register */ +#define AT91C_SPI0_TCR ( ( AT91_REG * ) 0xFFFE010C ) /* (PDC_SPI0) Transmit Counter Register */ +#define AT91C_SPI0_RCR ( ( AT91_REG * ) 0xFFFE0104 ) /* (PDC_SPI0) Receive Counter Register */ +#define AT91C_SPI0_PTSR ( ( AT91_REG * ) 0xFFFE0124 ) /* (PDC_SPI0) PDC Transfer Status Register */ +#define AT91C_SPI0_RNPR ( ( AT91_REG * ) 0xFFFE0110 ) /* (PDC_SPI0) Receive Next Pointer Register */ +#define AT91C_SPI0_RPR ( ( AT91_REG * ) 0xFFFE0100 ) /* (PDC_SPI0) Receive Pointer Register */ +#define AT91C_SPI0_TNCR ( ( AT91_REG * ) 0xFFFE011C ) /* (PDC_SPI0) Transmit Next Counter Register */ +#define AT91C_SPI0_RNCR ( ( AT91_REG * ) 0xFFFE0114 ) /* (PDC_SPI0) Receive Next Counter Register */ +#define AT91C_SPI0_TNPR ( ( AT91_REG * ) 0xFFFE0118 ) /* (PDC_SPI0) Transmit Next Pointer Register */ +/* ========== Register definition for SPI0 peripheral ========== */ +#define AT91C_SPI0_IER ( ( AT91_REG * ) 0xFFFE0014 ) /* (SPI0) Interrupt Enable Register */ +#define AT91C_SPI0_SR ( ( AT91_REG * ) 0xFFFE0010 ) /* (SPI0) Status Register */ +#define AT91C_SPI0_IDR ( ( AT91_REG * ) 0xFFFE0018 ) /* (SPI0) Interrupt Disable Register */ +#define AT91C_SPI0_CR ( ( AT91_REG * ) 0xFFFE0000 ) /* (SPI0) Control Register */ +#define AT91C_SPI0_MR ( ( AT91_REG * ) 0xFFFE0004 ) /* (SPI0) Mode Register */ +#define AT91C_SPI0_IMR ( ( AT91_REG * ) 0xFFFE001C ) /* (SPI0) Interrupt Mask Register */ +#define AT91C_SPI0_TDR ( ( AT91_REG * ) 0xFFFE000C ) /* (SPI0) Transmit Data Register */ +#define AT91C_SPI0_RDR ( ( AT91_REG * ) 0xFFFE0008 ) /* (SPI0) Receive Data Register */ +#define AT91C_SPI0_CSR ( ( AT91_REG * ) 0xFFFE0030 ) /* (SPI0) Chip Select Register */ +/* ========== Register definition for PDC_US1 peripheral ========== */ +#define AT91C_US1_RNCR ( ( AT91_REG * ) 0xFFFC4114 ) /* (PDC_US1) Receive Next Counter Register */ +#define AT91C_US1_PTCR ( ( AT91_REG * ) 0xFFFC4120 ) /* (PDC_US1) PDC Transfer Control Register */ +#define AT91C_US1_TCR ( ( AT91_REG * ) 0xFFFC410C ) /* (PDC_US1) Transmit Counter Register */ +#define AT91C_US1_PTSR ( ( AT91_REG * ) 0xFFFC4124 ) /* (PDC_US1) PDC Transfer Status Register */ +#define AT91C_US1_TNPR ( ( AT91_REG * ) 0xFFFC4118 ) /* (PDC_US1) Transmit Next Pointer Register */ +#define AT91C_US1_RCR ( ( AT91_REG * ) 0xFFFC4104 ) /* (PDC_US1) Receive Counter Register */ +#define AT91C_US1_RNPR ( ( AT91_REG * ) 0xFFFC4110 ) /* (PDC_US1) Receive Next Pointer Register */ +#define AT91C_US1_RPR ( ( AT91_REG * ) 0xFFFC4100 ) /* (PDC_US1) Receive Pointer Register */ +#define AT91C_US1_TNCR ( ( AT91_REG * ) 0xFFFC411C ) /* (PDC_US1) Transmit Next Counter Register */ +#define AT91C_US1_TPR ( ( AT91_REG * ) 0xFFFC4108 ) /* (PDC_US1) Transmit Pointer Register */ +/* ========== Register definition for US1 peripheral ========== */ +#define AT91C_US1_IF ( ( AT91_REG * ) 0xFFFC404C ) /* (US1) IRDA_FILTER Register */ +#define AT91C_US1_NER ( ( AT91_REG * ) 0xFFFC4044 ) /* (US1) Nb Errors Register */ +#define AT91C_US1_RTOR ( ( AT91_REG * ) 0xFFFC4024 ) /* (US1) Receiver Time-out Register */ +#define AT91C_US1_CSR ( ( AT91_REG * ) 0xFFFC4014 ) /* (US1) Channel Status Register */ +#define AT91C_US1_IDR ( ( AT91_REG * ) 0xFFFC400C ) /* (US1) Interrupt Disable Register */ +#define AT91C_US1_IER ( ( AT91_REG * ) 0xFFFC4008 ) /* (US1) Interrupt Enable Register */ +#define AT91C_US1_THR ( ( AT91_REG * ) 0xFFFC401C ) /* (US1) Transmitter Holding Register */ +#define AT91C_US1_TTGR ( ( AT91_REG * ) 0xFFFC4028 ) /* (US1) Transmitter Time-guard Register */ +#define AT91C_US1_RHR ( ( AT91_REG * ) 0xFFFC4018 ) /* (US1) Receiver Holding Register */ +#define AT91C_US1_BRGR ( ( AT91_REG * ) 0xFFFC4020 ) /* (US1) Baud Rate Generator Register */ +#define AT91C_US1_IMR ( ( AT91_REG * ) 0xFFFC4010 ) /* (US1) Interrupt Mask Register */ +#define AT91C_US1_FIDI ( ( AT91_REG * ) 0xFFFC4040 ) /* (US1) FI_DI_Ratio Register */ +#define AT91C_US1_CR ( ( AT91_REG * ) 0xFFFC4000 ) /* (US1) Control Register */ +#define AT91C_US1_MR ( ( AT91_REG * ) 0xFFFC4004 ) /* (US1) Mode Register */ +/* ========== Register definition for PDC_US0 peripheral ========== */ +#define AT91C_US0_TNPR ( ( AT91_REG * ) 0xFFFC0118 ) /* (PDC_US0) Transmit Next Pointer Register */ +#define AT91C_US0_RNPR ( ( AT91_REG * ) 0xFFFC0110 ) /* (PDC_US0) Receive Next Pointer Register */ +#define AT91C_US0_TCR ( ( AT91_REG * ) 0xFFFC010C ) /* (PDC_US0) Transmit Counter Register */ +#define AT91C_US0_PTCR ( ( AT91_REG * ) 0xFFFC0120 ) /* (PDC_US0) PDC Transfer Control Register */ +#define AT91C_US0_PTSR ( ( AT91_REG * ) 0xFFFC0124 ) /* (PDC_US0) PDC Transfer Status Register */ +#define AT91C_US0_TNCR ( ( AT91_REG * ) 0xFFFC011C ) /* (PDC_US0) Transmit Next Counter Register */ +#define AT91C_US0_TPR ( ( AT91_REG * ) 0xFFFC0108 ) /* (PDC_US0) Transmit Pointer Register */ +#define AT91C_US0_RCR ( ( AT91_REG * ) 0xFFFC0104 ) /* (PDC_US0) Receive Counter Register */ +#define AT91C_US0_RPR ( ( AT91_REG * ) 0xFFFC0100 ) /* (PDC_US0) Receive Pointer Register */ +#define AT91C_US0_RNCR ( ( AT91_REG * ) 0xFFFC0114 ) /* (PDC_US0) Receive Next Counter Register */ +/* ========== Register definition for US0 peripheral ========== */ +#define AT91C_US0_BRGR ( ( AT91_REG * ) 0xFFFC0020 ) /* (US0) Baud Rate Generator Register */ +#define AT91C_US0_NER ( ( AT91_REG * ) 0xFFFC0044 ) /* (US0) Nb Errors Register */ +#define AT91C_US0_CR ( ( AT91_REG * ) 0xFFFC0000 ) /* (US0) Control Register */ +#define AT91C_US0_IMR ( ( AT91_REG * ) 0xFFFC0010 ) /* (US0) Interrupt Mask Register */ +#define AT91C_US0_FIDI ( ( AT91_REG * ) 0xFFFC0040 ) /* (US0) FI_DI_Ratio Register */ +#define AT91C_US0_TTGR ( ( AT91_REG * ) 0xFFFC0028 ) /* (US0) Transmitter Time-guard Register */ +#define AT91C_US0_MR ( ( AT91_REG * ) 0xFFFC0004 ) /* (US0) Mode Register */ +#define AT91C_US0_RTOR ( ( AT91_REG * ) 0xFFFC0024 ) /* (US0) Receiver Time-out Register */ +#define AT91C_US0_CSR ( ( AT91_REG * ) 0xFFFC0014 ) /* (US0) Channel Status Register */ +#define AT91C_US0_RHR ( ( AT91_REG * ) 0xFFFC0018 ) /* (US0) Receiver Holding Register */ +#define AT91C_US0_IDR ( ( AT91_REG * ) 0xFFFC000C ) /* (US0) Interrupt Disable Register */ +#define AT91C_US0_THR ( ( AT91_REG * ) 0xFFFC001C ) /* (US0) Transmitter Holding Register */ +#define AT91C_US0_IF ( ( AT91_REG * ) 0xFFFC004C ) /* (US0) IRDA_FILTER Register */ +#define AT91C_US0_IER ( ( AT91_REG * ) 0xFFFC0008 ) /* (US0) Interrupt Enable Register */ +/* ========== Register definition for PDC_SSC peripheral ========== */ +#define AT91C_SSC_TNCR ( ( AT91_REG * ) 0xFFFD411C ) /* (PDC_SSC) Transmit Next Counter Register */ +#define AT91C_SSC_RPR ( ( AT91_REG * ) 0xFFFD4100 ) /* (PDC_SSC) Receive Pointer Register */ +#define AT91C_SSC_RNCR ( ( AT91_REG * ) 0xFFFD4114 ) /* (PDC_SSC) Receive Next Counter Register */ +#define AT91C_SSC_TPR ( ( AT91_REG * ) 0xFFFD4108 ) /* (PDC_SSC) Transmit Pointer Register */ +#define AT91C_SSC_PTCR ( ( AT91_REG * ) 0xFFFD4120 ) /* (PDC_SSC) PDC Transfer Control Register */ +#define AT91C_SSC_TCR ( ( AT91_REG * ) 0xFFFD410C ) /* (PDC_SSC) Transmit Counter Register */ +#define AT91C_SSC_RCR ( ( AT91_REG * ) 0xFFFD4104 ) /* (PDC_SSC) Receive Counter Register */ +#define AT91C_SSC_RNPR ( ( AT91_REG * ) 0xFFFD4110 ) /* (PDC_SSC) Receive Next Pointer Register */ +#define AT91C_SSC_TNPR ( ( AT91_REG * ) 0xFFFD4118 ) /* (PDC_SSC) Transmit Next Pointer Register */ +#define AT91C_SSC_PTSR ( ( AT91_REG * ) 0xFFFD4124 ) /* (PDC_SSC) PDC Transfer Status Register */ +/* ========== Register definition for SSC peripheral ========== */ +#define AT91C_SSC_RHR ( ( AT91_REG * ) 0xFFFD4020 ) /* (SSC) Receive Holding Register */ +#define AT91C_SSC_RSHR ( ( AT91_REG * ) 0xFFFD4030 ) /* (SSC) Receive Sync Holding Register */ +#define AT91C_SSC_TFMR ( ( AT91_REG * ) 0xFFFD401C ) /* (SSC) Transmit Frame Mode Register */ +#define AT91C_SSC_IDR ( ( AT91_REG * ) 0xFFFD4048 ) /* (SSC) Interrupt Disable Register */ +#define AT91C_SSC_THR ( ( AT91_REG * ) 0xFFFD4024 ) /* (SSC) Transmit Holding Register */ +#define AT91C_SSC_RCMR ( ( AT91_REG * ) 0xFFFD4010 ) /* (SSC) Receive Clock ModeRegister */ +#define AT91C_SSC_IER ( ( AT91_REG * ) 0xFFFD4044 ) /* (SSC) Interrupt Enable Register */ +#define AT91C_SSC_TSHR ( ( AT91_REG * ) 0xFFFD4034 ) /* (SSC) Transmit Sync Holding Register */ +#define AT91C_SSC_SR ( ( AT91_REG * ) 0xFFFD4040 ) /* (SSC) Status Register */ +#define AT91C_SSC_CMR ( ( AT91_REG * ) 0xFFFD4004 ) /* (SSC) Clock Mode Register */ +#define AT91C_SSC_TCMR ( ( AT91_REG * ) 0xFFFD4018 ) /* (SSC) Transmit Clock Mode Register */ +#define AT91C_SSC_CR ( ( AT91_REG * ) 0xFFFD4000 ) /* (SSC) Control Register */ +#define AT91C_SSC_IMR ( ( AT91_REG * ) 0xFFFD404C ) /* (SSC) Interrupt Mask Register */ +#define AT91C_SSC_RFMR ( ( AT91_REG * ) 0xFFFD4014 ) /* (SSC) Receive Frame Mode Register */ +/* ========== Register definition for TWI peripheral ========== */ +#define AT91C_TWI_IER ( ( AT91_REG * ) 0xFFFB8024 ) /* (TWI) Interrupt Enable Register */ +#define AT91C_TWI_CR ( ( AT91_REG * ) 0xFFFB8000 ) /* (TWI) Control Register */ +#define AT91C_TWI_SR ( ( AT91_REG * ) 0xFFFB8020 ) /* (TWI) Status Register */ +#define AT91C_TWI_IMR ( ( AT91_REG * ) 0xFFFB802C ) /* (TWI) Interrupt Mask Register */ +#define AT91C_TWI_THR ( ( AT91_REG * ) 0xFFFB8034 ) /* (TWI) Transmit Holding Register */ +#define AT91C_TWI_IDR ( ( AT91_REG * ) 0xFFFB8028 ) /* (TWI) Interrupt Disable Register */ +#define AT91C_TWI_IADR ( ( AT91_REG * ) 0xFFFB800C ) /* (TWI) Internal Address Register */ +#define AT91C_TWI_MMR ( ( AT91_REG * ) 0xFFFB8004 ) /* (TWI) Master Mode Register */ +#define AT91C_TWI_CWGR ( ( AT91_REG * ) 0xFFFB8010 ) /* (TWI) Clock Waveform Generator Register */ +#define AT91C_TWI_RHR ( ( AT91_REG * ) 0xFFFB8030 ) /* (TWI) Receive Holding Register */ +/* ========== Register definition for PWMC_CH3 peripheral ========== */ +#define AT91C_PWMC_CH3_CUPDR ( ( AT91_REG * ) 0xFFFCC270 ) /* (PWMC_CH3) Channel Update Register */ +#define AT91C_PWMC_CH3_Reserved ( ( AT91_REG * ) 0xFFFCC274 ) /* (PWMC_CH3) Reserved */ +#define AT91C_PWMC_CH3_CPRDR ( ( AT91_REG * ) 0xFFFCC268 ) /* (PWMC_CH3) Channel Period Register */ +#define AT91C_PWMC_CH3_CDTYR ( ( AT91_REG * ) 0xFFFCC264 ) /* (PWMC_CH3) Channel Duty Cycle Register */ +#define AT91C_PWMC_CH3_CCNTR ( ( AT91_REG * ) 0xFFFCC26C ) /* (PWMC_CH3) Channel Counter Register */ +#define AT91C_PWMC_CH3_CMR ( ( AT91_REG * ) 0xFFFCC260 ) /* (PWMC_CH3) Channel Mode Register */ +/* ========== Register definition for PWMC_CH2 peripheral ========== */ +#define AT91C_PWMC_CH2_Reserved ( ( AT91_REG * ) 0xFFFCC254 ) /* (PWMC_CH2) Reserved */ +#define AT91C_PWMC_CH2_CMR ( ( AT91_REG * ) 0xFFFCC240 ) /* (PWMC_CH2) Channel Mode Register */ +#define AT91C_PWMC_CH2_CCNTR ( ( AT91_REG * ) 0xFFFCC24C ) /* (PWMC_CH2) Channel Counter Register */ +#define AT91C_PWMC_CH2_CPRDR ( ( AT91_REG * ) 0xFFFCC248 ) /* (PWMC_CH2) Channel Period Register */ +#define AT91C_PWMC_CH2_CUPDR ( ( AT91_REG * ) 0xFFFCC250 ) /* (PWMC_CH2) Channel Update Register */ +#define AT91C_PWMC_CH2_CDTYR ( ( AT91_REG * ) 0xFFFCC244 ) /* (PWMC_CH2) Channel Duty Cycle Register */ +/* ========== Register definition for PWMC_CH1 peripheral ========== */ +#define AT91C_PWMC_CH1_Reserved ( ( AT91_REG * ) 0xFFFCC234 ) /* (PWMC_CH1) Reserved */ +#define AT91C_PWMC_CH1_CUPDR ( ( AT91_REG * ) 0xFFFCC230 ) /* (PWMC_CH1) Channel Update Register */ +#define AT91C_PWMC_CH1_CPRDR ( ( AT91_REG * ) 0xFFFCC228 ) /* (PWMC_CH1) Channel Period Register */ +#define AT91C_PWMC_CH1_CCNTR ( ( AT91_REG * ) 0xFFFCC22C ) /* (PWMC_CH1) Channel Counter Register */ +#define AT91C_PWMC_CH1_CDTYR ( ( AT91_REG * ) 0xFFFCC224 ) /* (PWMC_CH1) Channel Duty Cycle Register */ +#define AT91C_PWMC_CH1_CMR ( ( AT91_REG * ) 0xFFFCC220 ) /* (PWMC_CH1) Channel Mode Register */ +/* ========== Register definition for PWMC_CH0 peripheral ========== */ +#define AT91C_PWMC_CH0_Reserved ( ( AT91_REG * ) 0xFFFCC214 ) /* (PWMC_CH0) Reserved */ +#define AT91C_PWMC_CH0_CPRDR ( ( AT91_REG * ) 0xFFFCC208 ) /* (PWMC_CH0) Channel Period Register */ +#define AT91C_PWMC_CH0_CDTYR ( ( AT91_REG * ) 0xFFFCC204 ) /* (PWMC_CH0) Channel Duty Cycle Register */ +#define AT91C_PWMC_CH0_CMR ( ( AT91_REG * ) 0xFFFCC200 ) /* (PWMC_CH0) Channel Mode Register */ +#define AT91C_PWMC_CH0_CUPDR ( ( AT91_REG * ) 0xFFFCC210 ) /* (PWMC_CH0) Channel Update Register */ +#define AT91C_PWMC_CH0_CCNTR ( ( AT91_REG * ) 0xFFFCC20C ) /* (PWMC_CH0) Channel Counter Register */ +/* ========== Register definition for PWMC peripheral ========== */ +#define AT91C_PWMC_IDR ( ( AT91_REG * ) 0xFFFCC014 ) /* (PWMC) PWMC Interrupt Disable Register */ +#define AT91C_PWMC_DIS ( ( AT91_REG * ) 0xFFFCC008 ) /* (PWMC) PWMC Disable Register */ +#define AT91C_PWMC_IER ( ( AT91_REG * ) 0xFFFCC010 ) /* (PWMC) PWMC Interrupt Enable Register */ +#define AT91C_PWMC_VR ( ( AT91_REG * ) 0xFFFCC0FC ) /* (PWMC) PWMC Version Register */ +#define AT91C_PWMC_ISR ( ( AT91_REG * ) 0xFFFCC01C ) /* (PWMC) PWMC Interrupt Status Register */ +#define AT91C_PWMC_SR ( ( AT91_REG * ) 0xFFFCC00C ) /* (PWMC) PWMC Status Register */ +#define AT91C_PWMC_IMR ( ( AT91_REG * ) 0xFFFCC018 ) /* (PWMC) PWMC Interrupt Mask Register */ +#define AT91C_PWMC_MR ( ( AT91_REG * ) 0xFFFCC000 ) /* (PWMC) PWMC Mode Register */ +#define AT91C_PWMC_ENA ( ( AT91_REG * ) 0xFFFCC004 ) /* (PWMC) PWMC Enable Register */ +/* ========== Register definition for UDP peripheral ========== */ +#define AT91C_UDP_IMR ( ( AT91_REG * ) 0xFFFB0018 ) /* (UDP) Interrupt Mask Register */ +#define AT91C_UDP_FADDR ( ( AT91_REG * ) 0xFFFB0008 ) /* (UDP) Function Address Register */ +#define AT91C_UDP_NUM ( ( AT91_REG * ) 0xFFFB0000 ) /* (UDP) Frame Number Register */ +#define AT91C_UDP_FDR ( ( AT91_REG * ) 0xFFFB0050 ) /* (UDP) Endpoint FIFO Data Register */ +#define AT91C_UDP_ISR ( ( AT91_REG * ) 0xFFFB001C ) /* (UDP) Interrupt Status Register */ +#define AT91C_UDP_CSR ( ( AT91_REG * ) 0xFFFB0030 ) /* (UDP) Endpoint Control and Status Register */ +#define AT91C_UDP_IDR ( ( AT91_REG * ) 0xFFFB0014 ) /* (UDP) Interrupt Disable Register */ +#define AT91C_UDP_ICR ( ( AT91_REG * ) 0xFFFB0020 ) /* (UDP) Interrupt Clear Register */ +#define AT91C_UDP_RSTEP ( ( AT91_REG * ) 0xFFFB0028 ) /* (UDP) Reset Endpoint Register */ +#define AT91C_UDP_TXVC ( ( AT91_REG * ) 0xFFFB0074 ) /* (UDP) Transceiver Control Register */ +#define AT91C_UDP_GLBSTATE ( ( AT91_REG * ) 0xFFFB0004 ) /* (UDP) Global State Register */ +#define AT91C_UDP_IER ( ( AT91_REG * ) 0xFFFB0010 ) /* (UDP) Interrupt Enable Register */ +/* ========== Register definition for TC0 peripheral ========== */ +#define AT91C_TC0_SR ( ( AT91_REG * ) 0xFFFA0020 ) /* (TC0) Status Register */ +#define AT91C_TC0_RC ( ( AT91_REG * ) 0xFFFA001C ) /* (TC0) Register C */ +#define AT91C_TC0_RB ( ( AT91_REG * ) 0xFFFA0018 ) /* (TC0) Register B */ +#define AT91C_TC0_CCR ( ( AT91_REG * ) 0xFFFA0000 ) /* (TC0) Channel Control Register */ +#define AT91C_TC0_CMR ( ( AT91_REG * ) 0xFFFA0004 ) /* (TC0) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC0_IER ( ( AT91_REG * ) 0xFFFA0024 ) /* (TC0) Interrupt Enable Register */ +#define AT91C_TC0_RA ( ( AT91_REG * ) 0xFFFA0014 ) /* (TC0) Register A */ +#define AT91C_TC0_IDR ( ( AT91_REG * ) 0xFFFA0028 ) /* (TC0) Interrupt Disable Register */ +#define AT91C_TC0_CV ( ( AT91_REG * ) 0xFFFA0010 ) /* (TC0) Counter Value */ +#define AT91C_TC0_IMR ( ( AT91_REG * ) 0xFFFA002C ) /* (TC0) Interrupt Mask Register */ +/* ========== Register definition for TC1 peripheral ========== */ +#define AT91C_TC1_RB ( ( AT91_REG * ) 0xFFFA0058 ) /* (TC1) Register B */ +#define AT91C_TC1_CCR ( ( AT91_REG * ) 0xFFFA0040 ) /* (TC1) Channel Control Register */ +#define AT91C_TC1_IER ( ( AT91_REG * ) 0xFFFA0064 ) /* (TC1) Interrupt Enable Register */ +#define AT91C_TC1_IDR ( ( AT91_REG * ) 0xFFFA0068 ) /* (TC1) Interrupt Disable Register */ +#define AT91C_TC1_SR ( ( AT91_REG * ) 0xFFFA0060 ) /* (TC1) Status Register */ +#define AT91C_TC1_CMR ( ( AT91_REG * ) 0xFFFA0044 ) /* (TC1) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC1_RA ( ( AT91_REG * ) 0xFFFA0054 ) /* (TC1) Register A */ +#define AT91C_TC1_RC ( ( AT91_REG * ) 0xFFFA005C ) /* (TC1) Register C */ +#define AT91C_TC1_IMR ( ( AT91_REG * ) 0xFFFA006C ) /* (TC1) Interrupt Mask Register */ +#define AT91C_TC1_CV ( ( AT91_REG * ) 0xFFFA0050 ) /* (TC1) Counter Value */ +/* ========== Register definition for TC2 peripheral ========== */ +#define AT91C_TC2_CMR ( ( AT91_REG * ) 0xFFFA0084 ) /* (TC2) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC2_CCR ( ( AT91_REG * ) 0xFFFA0080 ) /* (TC2) Channel Control Register */ +#define AT91C_TC2_CV ( ( AT91_REG * ) 0xFFFA0090 ) /* (TC2) Counter Value */ +#define AT91C_TC2_RA ( ( AT91_REG * ) 0xFFFA0094 ) /* (TC2) Register A */ +#define AT91C_TC2_RB ( ( AT91_REG * ) 0xFFFA0098 ) /* (TC2) Register B */ +#define AT91C_TC2_IDR ( ( AT91_REG * ) 0xFFFA00A8 ) /* (TC2) Interrupt Disable Register */ +#define AT91C_TC2_IMR ( ( AT91_REG * ) 0xFFFA00AC ) /* (TC2) Interrupt Mask Register */ +#define AT91C_TC2_RC ( ( AT91_REG * ) 0xFFFA009C ) /* (TC2) Register C */ +#define AT91C_TC2_IER ( ( AT91_REG * ) 0xFFFA00A4 ) /* (TC2) Interrupt Enable Register */ +#define AT91C_TC2_SR ( ( AT91_REG * ) 0xFFFA00A0 ) /* (TC2) Status Register */ +/* ========== Register definition for TCB peripheral ========== */ +#define AT91C_TCB_BMR ( ( AT91_REG * ) 0xFFFA00C4 ) /* (TCB) TC Block Mode Register */ +#define AT91C_TCB_BCR ( ( AT91_REG * ) 0xFFFA00C0 ) /* (TCB) TC Block Control Register */ +/* ========== Register definition for CAN_MB0 peripheral ========== */ +#define AT91C_CAN_MB0_MDL ( ( AT91_REG * ) 0xFFFD0214 ) /* (CAN_MB0) MailBox Data Low Register */ +#define AT91C_CAN_MB0_MAM ( ( AT91_REG * ) 0xFFFD0204 ) /* (CAN_MB0) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB0_MCR ( ( AT91_REG * ) 0xFFFD021C ) /* (CAN_MB0) MailBox Control Register */ +#define AT91C_CAN_MB0_MID ( ( AT91_REG * ) 0xFFFD0208 ) /* (CAN_MB0) MailBox ID Register */ +#define AT91C_CAN_MB0_MSR ( ( AT91_REG * ) 0xFFFD0210 ) /* (CAN_MB0) MailBox Status Register */ +#define AT91C_CAN_MB0_MFID ( ( AT91_REG * ) 0xFFFD020C ) /* (CAN_MB0) MailBox Family ID Register */ +#define AT91C_CAN_MB0_MDH ( ( AT91_REG * ) 0xFFFD0218 ) /* (CAN_MB0) MailBox Data High Register */ +#define AT91C_CAN_MB0_MMR ( ( AT91_REG * ) 0xFFFD0200 ) /* (CAN_MB0) MailBox Mode Register */ +/* ========== Register definition for CAN_MB1 peripheral ========== */ +#define AT91C_CAN_MB1_MDL ( ( AT91_REG * ) 0xFFFD0234 ) /* (CAN_MB1) MailBox Data Low Register */ +#define AT91C_CAN_MB1_MID ( ( AT91_REG * ) 0xFFFD0228 ) /* (CAN_MB1) MailBox ID Register */ +#define AT91C_CAN_MB1_MMR ( ( AT91_REG * ) 0xFFFD0220 ) /* (CAN_MB1) MailBox Mode Register */ +#define AT91C_CAN_MB1_MSR ( ( AT91_REG * ) 0xFFFD0230 ) /* (CAN_MB1) MailBox Status Register */ +#define AT91C_CAN_MB1_MAM ( ( AT91_REG * ) 0xFFFD0224 ) /* (CAN_MB1) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB1_MDH ( ( AT91_REG * ) 0xFFFD0238 ) /* (CAN_MB1) MailBox Data High Register */ +#define AT91C_CAN_MB1_MCR ( ( AT91_REG * ) 0xFFFD023C ) /* (CAN_MB1) MailBox Control Register */ +#define AT91C_CAN_MB1_MFID ( ( AT91_REG * ) 0xFFFD022C ) /* (CAN_MB1) MailBox Family ID Register */ +/* ========== Register definition for CAN_MB2 peripheral ========== */ +#define AT91C_CAN_MB2_MCR ( ( AT91_REG * ) 0xFFFD025C ) /* (CAN_MB2) MailBox Control Register */ +#define AT91C_CAN_MB2_MDH ( ( AT91_REG * ) 0xFFFD0258 ) /* (CAN_MB2) MailBox Data High Register */ +#define AT91C_CAN_MB2_MID ( ( AT91_REG * ) 0xFFFD0248 ) /* (CAN_MB2) MailBox ID Register */ +#define AT91C_CAN_MB2_MDL ( ( AT91_REG * ) 0xFFFD0254 ) /* (CAN_MB2) MailBox Data Low Register */ +#define AT91C_CAN_MB2_MMR ( ( AT91_REG * ) 0xFFFD0240 ) /* (CAN_MB2) MailBox Mode Register */ +#define AT91C_CAN_MB2_MAM ( ( AT91_REG * ) 0xFFFD0244 ) /* (CAN_MB2) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB2_MFID ( ( AT91_REG * ) 0xFFFD024C ) /* (CAN_MB2) MailBox Family ID Register */ +#define AT91C_CAN_MB2_MSR ( ( AT91_REG * ) 0xFFFD0250 ) /* (CAN_MB2) MailBox Status Register */ +/* ========== Register definition for CAN_MB3 peripheral ========== */ +#define AT91C_CAN_MB3_MFID ( ( AT91_REG * ) 0xFFFD026C ) /* (CAN_MB3) MailBox Family ID Register */ +#define AT91C_CAN_MB3_MAM ( ( AT91_REG * ) 0xFFFD0264 ) /* (CAN_MB3) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB3_MID ( ( AT91_REG * ) 0xFFFD0268 ) /* (CAN_MB3) MailBox ID Register */ +#define AT91C_CAN_MB3_MCR ( ( AT91_REG * ) 0xFFFD027C ) /* (CAN_MB3) MailBox Control Register */ +#define AT91C_CAN_MB3_MMR ( ( AT91_REG * ) 0xFFFD0260 ) /* (CAN_MB3) MailBox Mode Register */ +#define AT91C_CAN_MB3_MSR ( ( AT91_REG * ) 0xFFFD0270 ) /* (CAN_MB3) MailBox Status Register */ +#define AT91C_CAN_MB3_MDL ( ( AT91_REG * ) 0xFFFD0274 ) /* (CAN_MB3) MailBox Data Low Register */ +#define AT91C_CAN_MB3_MDH ( ( AT91_REG * ) 0xFFFD0278 ) /* (CAN_MB3) MailBox Data High Register */ +/* ========== Register definition for CAN_MB4 peripheral ========== */ +#define AT91C_CAN_MB4_MID ( ( AT91_REG * ) 0xFFFD0288 ) /* (CAN_MB4) MailBox ID Register */ +#define AT91C_CAN_MB4_MMR ( ( AT91_REG * ) 0xFFFD0280 ) /* (CAN_MB4) MailBox Mode Register */ +#define AT91C_CAN_MB4_MDH ( ( AT91_REG * ) 0xFFFD0298 ) /* (CAN_MB4) MailBox Data High Register */ +#define AT91C_CAN_MB4_MFID ( ( AT91_REG * ) 0xFFFD028C ) /* (CAN_MB4) MailBox Family ID Register */ +#define AT91C_CAN_MB4_MSR ( ( AT91_REG * ) 0xFFFD0290 ) /* (CAN_MB4) MailBox Status Register */ +#define AT91C_CAN_MB4_MCR ( ( AT91_REG * ) 0xFFFD029C ) /* (CAN_MB4) MailBox Control Register */ +#define AT91C_CAN_MB4_MDL ( ( AT91_REG * ) 0xFFFD0294 ) /* (CAN_MB4) MailBox Data Low Register */ +#define AT91C_CAN_MB4_MAM ( ( AT91_REG * ) 0xFFFD0284 ) /* (CAN_MB4) MailBox Acceptance Mask Register */ +/* ========== Register definition for CAN_MB5 peripheral ========== */ +#define AT91C_CAN_MB5_MSR ( ( AT91_REG * ) 0xFFFD02B0 ) /* (CAN_MB5) MailBox Status Register */ +#define AT91C_CAN_MB5_MCR ( ( AT91_REG * ) 0xFFFD02BC ) /* (CAN_MB5) MailBox Control Register */ +#define AT91C_CAN_MB5_MFID ( ( AT91_REG * ) 0xFFFD02AC ) /* (CAN_MB5) MailBox Family ID Register */ +#define AT91C_CAN_MB5_MDH ( ( AT91_REG * ) 0xFFFD02B8 ) /* (CAN_MB5) MailBox Data High Register */ +#define AT91C_CAN_MB5_MID ( ( AT91_REG * ) 0xFFFD02A8 ) /* (CAN_MB5) MailBox ID Register */ +#define AT91C_CAN_MB5_MMR ( ( AT91_REG * ) 0xFFFD02A0 ) /* (CAN_MB5) MailBox Mode Register */ +#define AT91C_CAN_MB5_MDL ( ( AT91_REG * ) 0xFFFD02B4 ) /* (CAN_MB5) MailBox Data Low Register */ +#define AT91C_CAN_MB5_MAM ( ( AT91_REG * ) 0xFFFD02A4 ) /* (CAN_MB5) MailBox Acceptance Mask Register */ +/* ========== Register definition for CAN_MB6 peripheral ========== */ +#define AT91C_CAN_MB6_MFID ( ( AT91_REG * ) 0xFFFD02CC ) /* (CAN_MB6) MailBox Family ID Register */ +#define AT91C_CAN_MB6_MID ( ( AT91_REG * ) 0xFFFD02C8 ) /* (CAN_MB6) MailBox ID Register */ +#define AT91C_CAN_MB6_MAM ( ( AT91_REG * ) 0xFFFD02C4 ) /* (CAN_MB6) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB6_MSR ( ( AT91_REG * ) 0xFFFD02D0 ) /* (CAN_MB6) MailBox Status Register */ +#define AT91C_CAN_MB6_MDL ( ( AT91_REG * ) 0xFFFD02D4 ) /* (CAN_MB6) MailBox Data Low Register */ +#define AT91C_CAN_MB6_MCR ( ( AT91_REG * ) 0xFFFD02DC ) /* (CAN_MB6) MailBox Control Register */ +#define AT91C_CAN_MB6_MDH ( ( AT91_REG * ) 0xFFFD02D8 ) /* (CAN_MB6) MailBox Data High Register */ +#define AT91C_CAN_MB6_MMR ( ( AT91_REG * ) 0xFFFD02C0 ) /* (CAN_MB6) MailBox Mode Register */ +/* ========== Register definition for CAN_MB7 peripheral ========== */ +#define AT91C_CAN_MB7_MCR ( ( AT91_REG * ) 0xFFFD02FC ) /* (CAN_MB7) MailBox Control Register */ +#define AT91C_CAN_MB7_MDH ( ( AT91_REG * ) 0xFFFD02F8 ) /* (CAN_MB7) MailBox Data High Register */ +#define AT91C_CAN_MB7_MFID ( ( AT91_REG * ) 0xFFFD02EC ) /* (CAN_MB7) MailBox Family ID Register */ +#define AT91C_CAN_MB7_MDL ( ( AT91_REG * ) 0xFFFD02F4 ) /* (CAN_MB7) MailBox Data Low Register */ +#define AT91C_CAN_MB7_MID ( ( AT91_REG * ) 0xFFFD02E8 ) /* (CAN_MB7) MailBox ID Register */ +#define AT91C_CAN_MB7_MMR ( ( AT91_REG * ) 0xFFFD02E0 ) /* (CAN_MB7) MailBox Mode Register */ +#define AT91C_CAN_MB7_MAM ( ( AT91_REG * ) 0xFFFD02E4 ) /* (CAN_MB7) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB7_MSR ( ( AT91_REG * ) 0xFFFD02F0 ) /* (CAN_MB7) MailBox Status Register */ +/* ========== Register definition for CAN peripheral ========== */ +#define AT91C_CAN_TCR ( ( AT91_REG * ) 0xFFFD0024 ) /* (CAN) Transfer Command Register */ +#define AT91C_CAN_IMR ( ( AT91_REG * ) 0xFFFD000C ) /* (CAN) Interrupt Mask Register */ +#define AT91C_CAN_IER ( ( AT91_REG * ) 0xFFFD0004 ) /* (CAN) Interrupt Enable Register */ +#define AT91C_CAN_ECR ( ( AT91_REG * ) 0xFFFD0020 ) /* (CAN) Error Counter Register */ +#define AT91C_CAN_TIMESTP ( ( AT91_REG * ) 0xFFFD001C ) /* (CAN) Time Stamp Register */ +#define AT91C_CAN_MR ( ( AT91_REG * ) 0xFFFD0000 ) /* (CAN) Mode Register */ +#define AT91C_CAN_IDR ( ( AT91_REG * ) 0xFFFD0008 ) /* (CAN) Interrupt Disable Register */ +#define AT91C_CAN_ACR ( ( AT91_REG * ) 0xFFFD0028 ) /* (CAN) Abort Command Register */ +#define AT91C_CAN_TIM ( ( AT91_REG * ) 0xFFFD0018 ) /* (CAN) Timer Register */ +#define AT91C_CAN_SR ( ( AT91_REG * ) 0xFFFD0010 ) /* (CAN) Status Register */ +#define AT91C_CAN_BR ( ( AT91_REG * ) 0xFFFD0014 ) /* (CAN) Baudrate Register */ +#define AT91C_CAN_VR ( ( AT91_REG * ) 0xFFFD00FC ) /* (CAN) Version Register */ +/* ========== Register definition for EMAC peripheral ========== */ +#define AT91C_EMAC_ISR ( ( AT91_REG * ) 0xFFFDC024 ) /* (EMAC) Interrupt Status Register */ +#define AT91C_EMAC_SA4H ( ( AT91_REG * ) 0xFFFDC0B4 ) /* (EMAC) Specific Address 4 Top, Last 2 bytes */ +#define AT91C_EMAC_SA1L ( ( AT91_REG * ) 0xFFFDC098 ) /* (EMAC) Specific Address 1 Bottom, First 4 bytes */ +#define AT91C_EMAC_ELE ( ( AT91_REG * ) 0xFFFDC078 ) /* (EMAC) Excessive Length Errors Register */ +#define AT91C_EMAC_LCOL ( ( AT91_REG * ) 0xFFFDC05C ) /* (EMAC) Late Collision Register */ +#define AT91C_EMAC_RLE ( ( AT91_REG * ) 0xFFFDC088 ) /* (EMAC) Receive Length Field Mismatch Register */ +#define AT91C_EMAC_WOL ( ( AT91_REG * ) 0xFFFDC0C4 ) /* (EMAC) Wake On LAN Register */ +#define AT91C_EMAC_DTF ( ( AT91_REG * ) 0xFFFDC058 ) /* (EMAC) Deferred Transmission Frame Register */ +#define AT91C_EMAC_TUND ( ( AT91_REG * ) 0xFFFDC064 ) /* (EMAC) Transmit Underrun Error Register */ +#define AT91C_EMAC_NCR ( ( AT91_REG * ) 0xFFFDC000 ) /* (EMAC) Network Control Register */ +#define AT91C_EMAC_SA4L ( ( AT91_REG * ) 0xFFFDC0B0 ) /* (EMAC) Specific Address 4 Bottom, First 4 bytes */ +#define AT91C_EMAC_RSR ( ( AT91_REG * ) 0xFFFDC020 ) /* (EMAC) Receive Status Register */ +#define AT91C_EMAC_SA3L ( ( AT91_REG * ) 0xFFFDC0A8 ) /* (EMAC) Specific Address 3 Bottom, First 4 bytes */ +#define AT91C_EMAC_TSR ( ( AT91_REG * ) 0xFFFDC014 ) /* (EMAC) Transmit Status Register */ +#define AT91C_EMAC_IDR ( ( AT91_REG * ) 0xFFFDC02C ) /* (EMAC) Interrupt Disable Register */ +#define AT91C_EMAC_RSE ( ( AT91_REG * ) 0xFFFDC074 ) /* (EMAC) Receive Symbol Errors Register */ +#define AT91C_EMAC_ECOL ( ( AT91_REG * ) 0xFFFDC060 ) /* (EMAC) Excessive Collision Register */ +#define AT91C_EMAC_TID ( ( AT91_REG * ) 0xFFFDC0B8 ) /* (EMAC) Type ID Checking Register */ +#define AT91C_EMAC_HRB ( ( AT91_REG * ) 0xFFFDC090 ) /* (EMAC) Hash Address Bottom[31:0] */ +#define AT91C_EMAC_TBQP ( ( AT91_REG * ) 0xFFFDC01C ) /* (EMAC) Transmit Buffer Queue Pointer */ +#define AT91C_EMAC_USRIO ( ( AT91_REG * ) 0xFFFDC0C0 ) /* (EMAC) USER Input/Output Register */ +#define AT91C_EMAC_PTR ( ( AT91_REG * ) 0xFFFDC038 ) /* (EMAC) Pause Time Register */ +#define AT91C_EMAC_SA2H ( ( AT91_REG * ) 0xFFFDC0A4 ) /* (EMAC) Specific Address 2 Top, Last 2 bytes */ +#define AT91C_EMAC_ROV ( ( AT91_REG * ) 0xFFFDC070 ) /* (EMAC) Receive Overrun Errors Register */ +#define AT91C_EMAC_ALE ( ( AT91_REG * ) 0xFFFDC054 ) /* (EMAC) Alignment Error Register */ +#define AT91C_EMAC_RJA ( ( AT91_REG * ) 0xFFFDC07C ) /* (EMAC) Receive Jabbers Register */ +#define AT91C_EMAC_RBQP ( ( AT91_REG * ) 0xFFFDC018 ) /* (EMAC) Receive Buffer Queue Pointer */ +#define AT91C_EMAC_TPF ( ( AT91_REG * ) 0xFFFDC08C ) /* (EMAC) Transmitted Pause Frames Register */ +#define AT91C_EMAC_NCFGR ( ( AT91_REG * ) 0xFFFDC004 ) /* (EMAC) Network Configuration Register */ +#define AT91C_EMAC_HRT ( ( AT91_REG * ) 0xFFFDC094 ) /* (EMAC) Hash Address Top[63:32] */ +#define AT91C_EMAC_USF ( ( AT91_REG * ) 0xFFFDC080 ) /* (EMAC) Undersize Frames Register */ +#define AT91C_EMAC_FCSE ( ( AT91_REG * ) 0xFFFDC050 ) /* (EMAC) Frame Check Sequence Error Register */ +#define AT91C_EMAC_TPQ ( ( AT91_REG * ) 0xFFFDC0BC ) /* (EMAC) Transmit Pause Quantum Register */ +#define AT91C_EMAC_MAN ( ( AT91_REG * ) 0xFFFDC034 ) /* (EMAC) PHY Maintenance Register */ +#define AT91C_EMAC_FTO ( ( AT91_REG * ) 0xFFFDC040 ) /* (EMAC) Frames Transmitted OK Register */ +#define AT91C_EMAC_REV ( ( AT91_REG * ) 0xFFFDC0FC ) /* (EMAC) Revision Register */ +#define AT91C_EMAC_IMR ( ( AT91_REG * ) 0xFFFDC030 ) /* (EMAC) Interrupt Mask Register */ +#define AT91C_EMAC_SCF ( ( AT91_REG * ) 0xFFFDC044 ) /* (EMAC) Single Collision Frame Register */ +#define AT91C_EMAC_PFR ( ( AT91_REG * ) 0xFFFDC03C ) /* (EMAC) Pause Frames received Register */ +#define AT91C_EMAC_MCF ( ( AT91_REG * ) 0xFFFDC048 ) /* (EMAC) Multiple Collision Frame Register */ +#define AT91C_EMAC_NSR ( ( AT91_REG * ) 0xFFFDC008 ) /* (EMAC) Network Status Register */ +#define AT91C_EMAC_SA2L ( ( AT91_REG * ) 0xFFFDC0A0 ) /* (EMAC) Specific Address 2 Bottom, First 4 bytes */ +#define AT91C_EMAC_FRO ( ( AT91_REG * ) 0xFFFDC04C ) /* (EMAC) Frames Received OK Register */ +#define AT91C_EMAC_IER ( ( AT91_REG * ) 0xFFFDC028 ) /* (EMAC) Interrupt Enable Register */ +#define AT91C_EMAC_SA1H ( ( AT91_REG * ) 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */ +#define AT91C_EMAC_CSE ( ( AT91_REG * ) 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */ +#define AT91C_EMAC_SA3H ( ( AT91_REG * ) 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */ +#define AT91C_EMAC_RRE ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Resource Error Register */ +#define AT91C_EMAC_STE ( ( AT91_REG * ) 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */ +/* ========== Register definition for PDC_ADC peripheral ========== */ +#define AT91C_ADC_PTSR ( ( AT91_REG * ) 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */ +#define AT91C_ADC_PTCR ( ( AT91_REG * ) 0xFFFD8120 ) /* (PDC_ADC) PDC Transfer Control Register */ +#define AT91C_ADC_TNPR ( ( AT91_REG * ) 0xFFFD8118 ) /* (PDC_ADC) Transmit Next Pointer Register */ +#define AT91C_ADC_TNCR ( ( AT91_REG * ) 0xFFFD811C ) /* (PDC_ADC) Transmit Next Counter Register */ +#define AT91C_ADC_RNPR ( ( AT91_REG * ) 0xFFFD8110 ) /* (PDC_ADC) Receive Next Pointer Register */ +#define AT91C_ADC_RNCR ( ( AT91_REG * ) 0xFFFD8114 ) /* (PDC_ADC) Receive Next Counter Register */ +#define AT91C_ADC_RPR ( ( AT91_REG * ) 0xFFFD8100 ) /* (PDC_ADC) Receive Pointer Register */ +#define AT91C_ADC_TCR ( ( AT91_REG * ) 0xFFFD810C ) /* (PDC_ADC) Transmit Counter Register */ +#define AT91C_ADC_TPR ( ( AT91_REG * ) 0xFFFD8108 ) /* (PDC_ADC) Transmit Pointer Register */ +#define AT91C_ADC_RCR ( ( AT91_REG * ) 0xFFFD8104 ) /* (PDC_ADC) Receive Counter Register */ +/* ========== Register definition for ADC peripheral ========== */ +#define AT91C_ADC_CDR2 ( ( AT91_REG * ) 0xFFFD8038 ) /* (ADC) ADC Channel Data Register 2 */ +#define AT91C_ADC_CDR3 ( ( AT91_REG * ) 0xFFFD803C ) /* (ADC) ADC Channel Data Register 3 */ +#define AT91C_ADC_CDR0 ( ( AT91_REG * ) 0xFFFD8030 ) /* (ADC) ADC Channel Data Register 0 */ +#define AT91C_ADC_CDR5 ( ( AT91_REG * ) 0xFFFD8044 ) /* (ADC) ADC Channel Data Register 5 */ +#define AT91C_ADC_CHDR ( ( AT91_REG * ) 0xFFFD8014 ) /* (ADC) ADC Channel Disable Register */ +#define AT91C_ADC_SR ( ( AT91_REG * ) 0xFFFD801C ) /* (ADC) ADC Status Register */ +#define AT91C_ADC_CDR4 ( ( AT91_REG * ) 0xFFFD8040 ) /* (ADC) ADC Channel Data Register 4 */ +#define AT91C_ADC_CDR1 ( ( AT91_REG * ) 0xFFFD8034 ) /* (ADC) ADC Channel Data Register 1 */ +#define AT91C_ADC_LCDR ( ( AT91_REG * ) 0xFFFD8020 ) /* (ADC) ADC Last Converted Data Register */ +#define AT91C_ADC_IDR ( ( AT91_REG * ) 0xFFFD8028 ) /* (ADC) ADC Interrupt Disable Register */ +#define AT91C_ADC_CR ( ( AT91_REG * ) 0xFFFD8000 ) /* (ADC) ADC Control Register */ +#define AT91C_ADC_CDR7 ( ( AT91_REG * ) 0xFFFD804C ) /* (ADC) ADC Channel Data Register 7 */ +#define AT91C_ADC_CDR6 ( ( AT91_REG * ) 0xFFFD8048 ) /* (ADC) ADC Channel Data Register 6 */ +#define AT91C_ADC_IER ( ( AT91_REG * ) 0xFFFD8024 ) /* (ADC) ADC Interrupt Enable Register */ +#define AT91C_ADC_CHER ( ( AT91_REG * ) 0xFFFD8010 ) /* (ADC) ADC Channel Enable Register */ +#define AT91C_ADC_CHSR ( ( AT91_REG * ) 0xFFFD8018 ) /* (ADC) ADC Channel Status Register */ +#define AT91C_ADC_MR ( ( AT91_REG * ) 0xFFFD8004 ) /* (ADC) ADC Mode Register */ +#define AT91C_ADC_IMR ( ( AT91_REG * ) 0xFFFD802C ) /* (ADC) ADC Interrupt Mask Register */ +/* ========== Register definition for PDC_AES peripheral ========== */ +#define AT91C_AES_TPR ( ( AT91_REG * ) 0xFFFA4108 ) /* (PDC_AES) Transmit Pointer Register */ +#define AT91C_AES_PTCR ( ( AT91_REG * ) 0xFFFA4120 ) /* (PDC_AES) PDC Transfer Control Register */ +#define AT91C_AES_RNPR ( ( AT91_REG * ) 0xFFFA4110 ) /* (PDC_AES) Receive Next Pointer Register */ +#define AT91C_AES_TNCR ( ( AT91_REG * ) 0xFFFA411C ) /* (PDC_AES) Transmit Next Counter Register */ +#define AT91C_AES_TCR ( ( AT91_REG * ) 0xFFFA410C ) /* (PDC_AES) Transmit Counter Register */ +#define AT91C_AES_RCR ( ( AT91_REG * ) 0xFFFA4104 ) /* (PDC_AES) Receive Counter Register */ +#define AT91C_AES_RNCR ( ( AT91_REG * ) 0xFFFA4114 ) /* (PDC_AES) Receive Next Counter Register */ +#define AT91C_AES_TNPR ( ( AT91_REG * ) 0xFFFA4118 ) /* (PDC_AES) Transmit Next Pointer Register */ +#define AT91C_AES_RPR ( ( AT91_REG * ) 0xFFFA4100 ) /* (PDC_AES) Receive Pointer Register */ +#define AT91C_AES_PTSR ( ( AT91_REG * ) 0xFFFA4124 ) /* (PDC_AES) PDC Transfer Status Register */ +/* ========== Register definition for AES peripheral ========== */ +#define AT91C_AES_IVxR ( ( AT91_REG * ) 0xFFFA4060 ) /* (AES) Initialization Vector x Register */ +#define AT91C_AES_MR ( ( AT91_REG * ) 0xFFFA4004 ) /* (AES) Mode Register */ +#define AT91C_AES_VR ( ( AT91_REG * ) 0xFFFA40FC ) /* (AES) AES Version Register */ +#define AT91C_AES_ODATAxR ( ( AT91_REG * ) 0xFFFA4050 ) /* (AES) Output Data x Register */ +#define AT91C_AES_IDATAxR ( ( AT91_REG * ) 0xFFFA4040 ) /* (AES) Input Data x Register */ +#define AT91C_AES_CR ( ( AT91_REG * ) 0xFFFA4000 ) /* (AES) Control Register */ +#define AT91C_AES_IDR ( ( AT91_REG * ) 0xFFFA4014 ) /* (AES) Interrupt Disable Register */ +#define AT91C_AES_IMR ( ( AT91_REG * ) 0xFFFA4018 ) /* (AES) Interrupt Mask Register */ +#define AT91C_AES_IER ( ( AT91_REG * ) 0xFFFA4010 ) /* (AES) Interrupt Enable Register */ +#define AT91C_AES_KEYWxR ( ( AT91_REG * ) 0xFFFA4020 ) /* (AES) Key Word x Register */ +#define AT91C_AES_ISR ( ( AT91_REG * ) 0xFFFA401C ) /* (AES) Interrupt Status Register */ +/* ========== Register definition for PDC_TDES peripheral ========== */ +#define AT91C_TDES_RNCR ( ( AT91_REG * ) 0xFFFA8114 ) /* (PDC_TDES) Receive Next Counter Register */ +#define AT91C_TDES_TCR ( ( AT91_REG * ) 0xFFFA810C ) /* (PDC_TDES) Transmit Counter Register */ +#define AT91C_TDES_RCR ( ( AT91_REG * ) 0xFFFA8104 ) /* (PDC_TDES) Receive Counter Register */ +#define AT91C_TDES_TNPR ( ( AT91_REG * ) 0xFFFA8118 ) /* (PDC_TDES) Transmit Next Pointer Register */ +#define AT91C_TDES_RNPR ( ( AT91_REG * ) 0xFFFA8110 ) /* (PDC_TDES) Receive Next Pointer Register */ +#define AT91C_TDES_RPR ( ( AT91_REG * ) 0xFFFA8100 ) /* (PDC_TDES) Receive Pointer Register */ +#define AT91C_TDES_TNCR ( ( AT91_REG * ) 0xFFFA811C ) /* (PDC_TDES) Transmit Next Counter Register */ +#define AT91C_TDES_TPR ( ( AT91_REG * ) 0xFFFA8108 ) /* (PDC_TDES) Transmit Pointer Register */ +#define AT91C_TDES_PTSR ( ( AT91_REG * ) 0xFFFA8124 ) /* (PDC_TDES) PDC Transfer Status Register */ +#define AT91C_TDES_PTCR ( ( AT91_REG * ) 0xFFFA8120 ) /* (PDC_TDES) PDC Transfer Control Register */ +/* ========== Register definition for TDES peripheral ========== */ +#define AT91C_TDES_KEY2WxR ( ( AT91_REG * ) 0xFFFA8028 ) /* (TDES) Key 2 Word x Register */ +#define AT91C_TDES_KEY3WxR ( ( AT91_REG * ) 0xFFFA8030 ) /* (TDES) Key 3 Word x Register */ +#define AT91C_TDES_IDR ( ( AT91_REG * ) 0xFFFA8014 ) /* (TDES) Interrupt Disable Register */ +#define AT91C_TDES_VR ( ( AT91_REG * ) 0xFFFA80FC ) /* (TDES) TDES Version Register */ +#define AT91C_TDES_IVxR ( ( AT91_REG * ) 0xFFFA8060 ) /* (TDES) Initialization Vector x Register */ +#define AT91C_TDES_ODATAxR ( ( AT91_REG * ) 0xFFFA8050 ) /* (TDES) Output Data x Register */ +#define AT91C_TDES_IMR ( ( AT91_REG * ) 0xFFFA8018 ) /* (TDES) Interrupt Mask Register */ +#define AT91C_TDES_MR ( ( AT91_REG * ) 0xFFFA8004 ) /* (TDES) Mode Register */ +#define AT91C_TDES_CR ( ( AT91_REG * ) 0xFFFA8000 ) /* (TDES) Control Register */ +#define AT91C_TDES_IER ( ( AT91_REG * ) 0xFFFA8010 ) /* (TDES) Interrupt Enable Register */ +#define AT91C_TDES_ISR ( ( AT91_REG * ) 0xFFFA801C ) /* (TDES) Interrupt Status Register */ +#define AT91C_TDES_IDATAxR ( ( AT91_REG * ) 0xFFFA8040 ) /* (TDES) Input Data x Register */ +#define AT91C_TDES_KEY1WxR ( ( AT91_REG * ) 0xFFFA8020 ) /* (TDES) Key 1 Word x Register */ + +/* ***************************************************************************** */ +/* PIO DEFINITIONS FOR AT91SAM7X256 */ +/* ***************************************************************************** */ +#define AT91C_PIO_PA0 ( ( unsigned int ) 1 << 0 ) /* Pin Controlled by PA0 */ +#define AT91C_PA0_RXD0 ( ( unsigned int ) AT91C_PIO_PA0 ) /* USART 0 Receive Data */ +#define AT91C_PIO_PA1 ( ( unsigned int ) 1 << 1 ) /* Pin Controlled by PA1 */ +#define AT91C_PA1_TXD0 ( ( unsigned int ) AT91C_PIO_PA1 ) /* USART 0 Transmit Data */ +#define AT91C_PIO_PA10 ( ( unsigned int ) 1 << 10 ) /* Pin Controlled by PA10 */ +#define AT91C_PA10_TWD ( ( unsigned int ) AT91C_PIO_PA10 ) /* TWI Two-wire Serial Data */ +#define AT91C_PIO_PA11 ( ( unsigned int ) 1 << 11 ) /* Pin Controlled by PA11 */ +#define AT91C_PA11_TWCK ( ( unsigned int ) AT91C_PIO_PA11 ) /* TWI Two-wire Serial Clock */ +#define AT91C_PIO_PA12 ( ( unsigned int ) 1 << 12 ) /* Pin Controlled by PA12 */ +#define AT91C_PA12_NPCS00 ( ( unsigned int ) AT91C_PIO_PA12 ) /* SPI 0 Peripheral Chip Select 0 */ +#define AT91C_PIO_PA13 ( ( unsigned int ) 1 << 13 ) /* Pin Controlled by PA13 */ +#define AT91C_PA13_NPCS01 ( ( unsigned int ) AT91C_PIO_PA13 ) /* SPI 0 Peripheral Chip Select 1 */ +#define AT91C_PA13_PCK1 ( ( unsigned int ) AT91C_PIO_PA13 ) /* PMC Programmable Clock Output 1 */ +#define AT91C_PIO_PA14 ( ( unsigned int ) 1 << 14 ) /* Pin Controlled by PA14 */ +#define AT91C_PA14_NPCS02 ( ( unsigned int ) AT91C_PIO_PA14 ) /* SPI 0 Peripheral Chip Select 2 */ +#define AT91C_PA14_IRQ1 ( ( unsigned int ) AT91C_PIO_PA14 ) /* External Interrupt 1 */ +#define AT91C_PIO_PA15 ( ( unsigned int ) 1 << 15 ) /* Pin Controlled by PA15 */ +#define AT91C_PA15_NPCS03 ( ( unsigned int ) AT91C_PIO_PA15 ) /* SPI 0 Peripheral Chip Select 3 */ +#define AT91C_PA15_TCLK2 ( ( unsigned int ) AT91C_PIO_PA15 ) /* Timer Counter 2 external clock input */ +#define AT91C_PIO_PA16 ( ( unsigned int ) 1 << 16 ) /* Pin Controlled by PA16 */ +#define AT91C_PA16_MISO0 ( ( unsigned int ) AT91C_PIO_PA16 ) /* SPI 0 Master In Slave */ +#define AT91C_PIO_PA17 ( ( unsigned int ) 1 << 17 ) /* Pin Controlled by PA17 */ +#define AT91C_PA17_MOSI0 ( ( unsigned int ) AT91C_PIO_PA17 ) /* SPI 0 Master Out Slave */ +#define AT91C_PIO_PA18 ( ( unsigned int ) 1 << 18 ) /* Pin Controlled by PA18 */ +#define AT91C_PA18_SPCK0 ( ( unsigned int ) AT91C_PIO_PA18 ) /* SPI 0 Serial Clock */ +#define AT91C_PIO_PA19 ( ( unsigned int ) 1 << 19 ) /* Pin Controlled by PA19 */ +#define AT91C_PA19_CANRX ( ( unsigned int ) AT91C_PIO_PA19 ) /* CAN Receive */ +#define AT91C_PIO_PA2 ( ( unsigned int ) 1 << 2 ) /* Pin Controlled by PA2 */ +#define AT91C_PA2_SCK0 ( ( unsigned int ) AT91C_PIO_PA2 ) /* USART 0 Serial Clock */ +#define AT91C_PA2_NPCS11 ( ( unsigned int ) AT91C_PIO_PA2 ) /* SPI 1 Peripheral Chip Select 1 */ +#define AT91C_PIO_PA20 ( ( unsigned int ) 1 << 20 ) /* Pin Controlled by PA20 */ +#define AT91C_PA20_CANTX ( ( unsigned int ) AT91C_PIO_PA20 ) /* CAN Transmit */ +#define AT91C_PIO_PA21 ( ( unsigned int ) 1 << 21 ) /* Pin Controlled by PA21 */ +#define AT91C_PA21_TF ( ( unsigned int ) AT91C_PIO_PA21 ) /* SSC Transmit Frame Sync */ +#define AT91C_PA21_NPCS10 ( ( unsigned int ) AT91C_PIO_PA21 ) /* SPI 1 Peripheral Chip Select 0 */ +#define AT91C_PIO_PA22 ( ( unsigned int ) 1 << 22 ) /* Pin Controlled by PA22 */ +#define AT91C_PA22_TK ( ( unsigned int ) AT91C_PIO_PA22 ) /* SSC Transmit Clock */ +#define AT91C_PA22_SPCK1 ( ( unsigned int ) AT91C_PIO_PA22 ) /* SPI 1 Serial Clock */ +#define AT91C_PIO_PA23 ( ( unsigned int ) 1 << 23 ) /* Pin Controlled by PA23 */ +#define AT91C_PA23_TD ( ( unsigned int ) AT91C_PIO_PA23 ) /* SSC Transmit data */ +#define AT91C_PA23_MOSI1 ( ( unsigned int ) AT91C_PIO_PA23 ) /* SPI 1 Master Out Slave */ +#define AT91C_PIO_PA24 ( ( unsigned int ) 1 << 24 ) /* Pin Controlled by PA24 */ +#define AT91C_PA24_RD ( ( unsigned int ) AT91C_PIO_PA24 ) /* SSC Receive Data */ +#define AT91C_PA24_MISO1 ( ( unsigned int ) AT91C_PIO_PA24 ) /* SPI 1 Master In Slave */ +#define AT91C_PIO_PA25 ( ( unsigned int ) 1 << 25 ) /* Pin Controlled by PA25 */ +#define AT91C_PA25_RK ( ( unsigned int ) AT91C_PIO_PA25 ) /* SSC Receive Clock */ +#define AT91C_PA25_NPCS11 ( ( unsigned int ) AT91C_PIO_PA25 ) /* SPI 1 Peripheral Chip Select 1 */ +#define AT91C_PIO_PA26 ( ( unsigned int ) 1 << 26 ) /* Pin Controlled by PA26 */ +#define AT91C_PA26_RF ( ( unsigned int ) AT91C_PIO_PA26 ) /* SSC Receive Frame Sync */ +#define AT91C_PA26_NPCS12 ( ( unsigned int ) AT91C_PIO_PA26 ) /* SPI 1 Peripheral Chip Select 2 */ +#define AT91C_PIO_PA27 ( ( unsigned int ) 1 << 27 ) /* Pin Controlled by PA27 */ +#define AT91C_PA27_DRXD ( ( unsigned int ) AT91C_PIO_PA27 ) /* DBGU Debug Receive Data */ +#define AT91C_PA27_PCK3 ( ( unsigned int ) AT91C_PIO_PA27 ) /* PMC Programmable Clock Output 3 */ +#define AT91C_PIO_PA28 ( ( unsigned int ) 1 << 28 ) /* Pin Controlled by PA28 */ +#define AT91C_PA28_DTXD ( ( unsigned int ) AT91C_PIO_PA28 ) /* DBGU Debug Transmit Data */ +#define AT91C_PIO_PA29 ( ( unsigned int ) 1 << 29 ) /* Pin Controlled by PA29 */ +#define AT91C_PA29_FIQ ( ( unsigned int ) AT91C_PIO_PA29 ) /* AIC Fast Interrupt Input */ +#define AT91C_PA29_NPCS13 ( ( unsigned int ) AT91C_PIO_PA29 ) /* SPI 1 Peripheral Chip Select 3 */ +#define AT91C_PIO_PA3 ( ( unsigned int ) 1 << 3 ) /* Pin Controlled by PA3 */ +#define AT91C_PA3_RTS0 ( ( unsigned int ) AT91C_PIO_PA3 ) /* USART 0 Ready To Send */ +#define AT91C_PA3_NPCS12 ( ( unsigned int ) AT91C_PIO_PA3 ) /* SPI 1 Peripheral Chip Select 2 */ +#define AT91C_PIO_PA30 ( ( unsigned int ) 1 << 30 ) /* Pin Controlled by PA30 */ +#define AT91C_PA30_IRQ0 ( ( unsigned int ) AT91C_PIO_PA30 ) /* External Interrupt 0 */ +#define AT91C_PA30_PCK2 ( ( unsigned int ) AT91C_PIO_PA30 ) /* PMC Programmable Clock Output 2 */ +#define AT91C_PIO_PA4 ( ( unsigned int ) 1 << 4 ) /* Pin Controlled by PA4 */ +#define AT91C_PA4_CTS0 ( ( unsigned int ) AT91C_PIO_PA4 ) /* USART 0 Clear To Send */ +#define AT91C_PA4_NPCS13 ( ( unsigned int ) AT91C_PIO_PA4 ) /* SPI 1 Peripheral Chip Select 3 */ +#define AT91C_PIO_PA5 ( ( unsigned int ) 1 << 5 ) /* Pin Controlled by PA5 */ +#define AT91C_PA5_RXD1 ( ( unsigned int ) AT91C_PIO_PA5 ) /* USART 1 Receive Data */ +#define AT91C_PIO_PA6 ( ( unsigned int ) 1 << 6 ) /* Pin Controlled by PA6 */ +#define AT91C_PA6_TXD1 ( ( unsigned int ) AT91C_PIO_PA6 ) /* USART 1 Transmit Data */ +#define AT91C_PIO_PA7 ( ( unsigned int ) 1 << 7 ) /* Pin Controlled by PA7 */ +#define AT91C_PA7_SCK1 ( ( unsigned int ) AT91C_PIO_PA7 ) /* USART 1 Serial Clock */ +#define AT91C_PA7_NPCS01 ( ( unsigned int ) AT91C_PIO_PA7 ) /* SPI 0 Peripheral Chip Select 1 */ +#define AT91C_PIO_PA8 ( ( unsigned int ) 1 << 8 ) /* Pin Controlled by PA8 */ +#define AT91C_PA8_RTS1 ( ( unsigned int ) AT91C_PIO_PA8 ) /* USART 1 Ready To Send */ +#define AT91C_PA8_NPCS02 ( ( unsigned int ) AT91C_PIO_PA8 ) /* SPI 0 Peripheral Chip Select 2 */ +#define AT91C_PIO_PA9 ( ( unsigned int ) 1 << 9 ) /* Pin Controlled by PA9 */ +#define AT91C_PA9_CTS1 ( ( unsigned int ) AT91C_PIO_PA9 ) /* USART 1 Clear To Send */ +#define AT91C_PA9_NPCS03 ( ( unsigned int ) AT91C_PIO_PA9 ) /* SPI 0 Peripheral Chip Select 3 */ +#define AT91C_PIO_PB0 ( ( unsigned int ) 1 << 0 ) /* Pin Controlled by PB0 */ +#define AT91C_PB0_ETXCK_EREFCK ( ( unsigned int ) AT91C_PIO_PB0 ) /* Ethernet MAC Transmit Clock/Reference Clock */ +#define AT91C_PB0_PCK0 ( ( unsigned int ) AT91C_PIO_PB0 ) /* PMC Programmable Clock Output 0 */ +#define AT91C_PIO_PB1 ( ( unsigned int ) 1 << 1 ) /* Pin Controlled by PB1 */ +#define AT91C_PB1_ETXEN ( ( unsigned int ) AT91C_PIO_PB1 ) /* Ethernet MAC Transmit Enable */ +#define AT91C_PIO_PB10 ( ( unsigned int ) 1 << 10 ) /* Pin Controlled by PB10 */ +#define AT91C_PB10_ETX2 ( ( unsigned int ) AT91C_PIO_PB10 ) /* Ethernet MAC Transmit Data 2 */ +#define AT91C_PB10_NPCS11 ( ( unsigned int ) AT91C_PIO_PB10 ) /* SPI 1 Peripheral Chip Select 1 */ +#define AT91C_PIO_PB11 ( ( unsigned int ) 1 << 11 ) /* Pin Controlled by PB11 */ +#define AT91C_PB11_ETX3 ( ( unsigned int ) AT91C_PIO_PB11 ) /* Ethernet MAC Transmit Data 3 */ +#define AT91C_PB11_NPCS12 ( ( unsigned int ) AT91C_PIO_PB11 ) /* SPI 1 Peripheral Chip Select 2 */ +#define AT91C_PIO_PB12 ( ( unsigned int ) 1 << 12 ) /* Pin Controlled by PB12 */ +#define AT91C_PB12_ETXER ( ( unsigned int ) AT91C_PIO_PB12 ) /* Ethernet MAC Transmit Coding Error */ +#define AT91C_PB12_TCLK0 ( ( unsigned int ) AT91C_PIO_PB12 ) /* Timer Counter 0 external clock input */ +#define AT91C_PIO_PB13 ( ( unsigned int ) 1 << 13 ) /* Pin Controlled by PB13 */ +#define AT91C_PB13_ERX2 ( ( unsigned int ) AT91C_PIO_PB13 ) /* Ethernet MAC Receive Data 2 */ +#define AT91C_PB13_NPCS01 ( ( unsigned int ) AT91C_PIO_PB13 ) /* SPI 0 Peripheral Chip Select 1 */ +#define AT91C_PIO_PB14 ( ( unsigned int ) 1 << 14 ) /* Pin Controlled by PB14 */ +#define AT91C_PB14_ERX3 ( ( unsigned int ) AT91C_PIO_PB14 ) /* Ethernet MAC Receive Data 3 */ +#define AT91C_PB14_NPCS02 ( ( unsigned int ) AT91C_PIO_PB14 ) /* SPI 0 Peripheral Chip Select 2 */ +#define AT91C_PIO_PB15 ( ( unsigned int ) 1 << 15 ) /* Pin Controlled by PB15 */ +#define AT91C_PB15_ERXDV ( ( unsigned int ) AT91C_PIO_PB15 ) /* Ethernet MAC Receive Data Valid */ +#define AT91C_PIO_PB16 ( ( unsigned int ) 1 << 16 ) /* Pin Controlled by PB16 */ +#define AT91C_PB16_ECOL ( ( unsigned int ) AT91C_PIO_PB16 ) /* Ethernet MAC Collision Detected */ +#define AT91C_PB16_NPCS13 ( ( unsigned int ) AT91C_PIO_PB16 ) /* SPI 1 Peripheral Chip Select 3 */ +#define AT91C_PIO_PB17 ( ( unsigned int ) 1 << 17 ) /* Pin Controlled by PB17 */ +#define AT91C_PB17_ERXCK ( ( unsigned int ) AT91C_PIO_PB17 ) /* Ethernet MAC Receive Clock */ +#define AT91C_PB17_NPCS03 ( ( unsigned int ) AT91C_PIO_PB17 ) /* SPI 0 Peripheral Chip Select 3 */ +#define AT91C_PIO_PB18 ( ( unsigned int ) 1 << 18 ) /* Pin Controlled by PB18 */ +#define AT91C_PB18_EF100 ( ( unsigned int ) AT91C_PIO_PB18 ) /* Ethernet MAC Force 100 Mbits/sec */ +#define AT91C_PB18_ADTRG ( ( unsigned int ) AT91C_PIO_PB18 ) /* ADC External Trigger */ +#define AT91C_PIO_PB19 ( ( unsigned int ) 1 << 19 ) /* Pin Controlled by PB19 */ +#define AT91C_PB19_PWM0 ( ( unsigned int ) AT91C_PIO_PB19 ) /* PWM Channel 0 */ +#define AT91C_PB19_TCLK1 ( ( unsigned int ) AT91C_PIO_PB19 ) /* Timer Counter 1 external clock input */ +#define AT91C_PIO_PB2 ( ( unsigned int ) 1 << 2 ) /* Pin Controlled by PB2 */ +#define AT91C_PB2_ETX0 ( ( unsigned int ) AT91C_PIO_PB2 ) /* Ethernet MAC Transmit Data 0 */ +#define AT91C_PIO_PB20 ( ( unsigned int ) 1 << 20 ) /* Pin Controlled by PB20 */ +#define AT91C_PB20_PWM1 ( ( unsigned int ) AT91C_PIO_PB20 ) /* PWM Channel 1 */ +#define AT91C_PB20_PCK0 ( ( unsigned int ) AT91C_PIO_PB20 ) /* PMC Programmable Clock Output 0 */ +#define AT91C_PIO_PB21 ( ( unsigned int ) 1 << 21 ) /* Pin Controlled by PB21 */ +#define AT91C_PB21_PWM2 ( ( unsigned int ) AT91C_PIO_PB21 ) /* PWM Channel 2 */ +#define AT91C_PB21_PCK1 ( ( unsigned int ) AT91C_PIO_PB21 ) /* PMC Programmable Clock Output 1 */ +#define AT91C_PIO_PB22 ( ( unsigned int ) 1 << 22 ) /* Pin Controlled by PB22 */ +#define AT91C_PB22_PWM3 ( ( unsigned int ) AT91C_PIO_PB22 ) /* PWM Channel 3 */ +#define AT91C_PB22_PCK2 ( ( unsigned int ) AT91C_PIO_PB22 ) /* PMC Programmable Clock Output 2 */ +#define AT91C_PIO_PB23 ( ( unsigned int ) 1 << 23 ) /* Pin Controlled by PB23 */ +#define AT91C_PB23_TIOA0 ( ( unsigned int ) AT91C_PIO_PB23 ) /* Timer Counter 0 Multipurpose Timer I/O Pin A */ +#define AT91C_PB23_DCD1 ( ( unsigned int ) AT91C_PIO_PB23 ) /* USART 1 Data Carrier Detect */ +#define AT91C_PIO_PB24 ( ( unsigned int ) 1 << 24 ) /* Pin Controlled by PB24 */ +#define AT91C_PB24_TIOB0 ( ( unsigned int ) AT91C_PIO_PB24 ) /* Timer Counter 0 Multipurpose Timer I/O Pin B */ +#define AT91C_PB24_DSR1 ( ( unsigned int ) AT91C_PIO_PB24 ) /* USART 1 Data Set ready */ +#define AT91C_PIO_PB25 ( ( unsigned int ) 1 << 25 ) /* Pin Controlled by PB25 */ +#define AT91C_PB25_TIOA1 ( ( unsigned int ) AT91C_PIO_PB25 ) /* Timer Counter 1 Multipurpose Timer I/O Pin A */ +#define AT91C_PB25_DTR1 ( ( unsigned int ) AT91C_PIO_PB25 ) /* USART 1 Data Terminal ready */ +#define AT91C_PIO_PB26 ( ( unsigned int ) 1 << 26 ) /* Pin Controlled by PB26 */ +#define AT91C_PB26_TIOB1 ( ( unsigned int ) AT91C_PIO_PB26 ) /* Timer Counter 1 Multipurpose Timer I/O Pin B */ +#define AT91C_PB26_RI1 ( ( unsigned int ) AT91C_PIO_PB26 ) /* USART 1 Ring Indicator */ +#define AT91C_PIO_PB27 ( ( unsigned int ) 1 << 27 ) /* Pin Controlled by PB27 */ +#define AT91C_PB27_TIOA2 ( ( unsigned int ) AT91C_PIO_PB27 ) /* Timer Counter 2 Multipurpose Timer I/O Pin A */ +#define AT91C_PB27_PWM0 ( ( unsigned int ) AT91C_PIO_PB27 ) /* PWM Channel 0 */ +#define AT91C_PIO_PB28 ( ( unsigned int ) 1 << 28 ) /* Pin Controlled by PB28 */ +#define AT91C_PB28_TIOB2 ( ( unsigned int ) AT91C_PIO_PB28 ) /* Timer Counter 2 Multipurpose Timer I/O Pin B */ +#define AT91C_PB28_PWM1 ( ( unsigned int ) AT91C_PIO_PB28 ) /* PWM Channel 1 */ +#define AT91C_PIO_PB29 ( ( unsigned int ) 1 << 29 ) /* Pin Controlled by PB29 */ +#define AT91C_PB29_PCK1 ( ( unsigned int ) AT91C_PIO_PB29 ) /* PMC Programmable Clock Output 1 */ +#define AT91C_PB29_PWM2 ( ( unsigned int ) AT91C_PIO_PB29 ) /* PWM Channel 2 */ +#define AT91C_PIO_PB3 ( ( unsigned int ) 1 << 3 ) /* Pin Controlled by PB3 */ +#define AT91C_PB3_ETX1 ( ( unsigned int ) AT91C_PIO_PB3 ) /* Ethernet MAC Transmit Data 1 */ +#define AT91C_PIO_PB30 ( ( unsigned int ) 1 << 30 ) /* Pin Controlled by PB30 */ +#define AT91C_PB30_PCK2 ( ( unsigned int ) AT91C_PIO_PB30 ) /* PMC Programmable Clock Output 2 */ +#define AT91C_PB30_PWM3 ( ( unsigned int ) AT91C_PIO_PB30 ) /* PWM Channel 3 */ +#define AT91C_PIO_PB4 ( ( unsigned int ) 1 << 4 ) /* Pin Controlled by PB4 */ +#define AT91C_PB4_ECRS_ECRSDV ( ( unsigned int ) AT91C_PIO_PB4 ) /* Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */ +#define AT91C_PIO_PB5 ( ( unsigned int ) 1 << 5 ) /* Pin Controlled by PB5 */ +#define AT91C_PB5_ERX0 ( ( unsigned int ) AT91C_PIO_PB5 ) /* Ethernet MAC Receive Data 0 */ +#define AT91C_PIO_PB6 ( ( unsigned int ) 1 << 6 ) /* Pin Controlled by PB6 */ +#define AT91C_PB6_ERX1 ( ( unsigned int ) AT91C_PIO_PB6 ) /* Ethernet MAC Receive Data 1 */ +#define AT91C_PIO_PB7 ( ( unsigned int ) 1 << 7 ) /* Pin Controlled by PB7 */ +#define AT91C_PB7_ERXER ( ( unsigned int ) AT91C_PIO_PB7 ) /* Ethernet MAC Receive Error */ +#define AT91C_PIO_PB8 ( ( unsigned int ) 1 << 8 ) /* Pin Controlled by PB8 */ +#define AT91C_PB8_EMDC ( ( unsigned int ) AT91C_PIO_PB8 ) /* Ethernet MAC Management Data Clock */ +#define AT91C_PIO_PB9 ( ( unsigned int ) 1 << 9 ) /* Pin Controlled by PB9 */ +#define AT91C_PB9_EMDIO ( ( unsigned int ) AT91C_PIO_PB9 ) /* Ethernet MAC Management Data Input/Output */ + +/* ***************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 */ +/* ***************************************************************************** */ +#define AT91C_ID_FIQ ( ( unsigned int ) 0 ) /* Advanced Interrupt Controller (FIQ) */ +#define AT91C_ID_SYS ( ( unsigned int ) 1 ) /* System Peripheral */ +#define AT91C_ID_PIOA ( ( unsigned int ) 2 ) /* Parallel IO Controller A */ +#define AT91C_ID_PIOB ( ( unsigned int ) 3 ) /* Parallel IO Controller B */ +#define AT91C_ID_SPI0 ( ( unsigned int ) 4 ) /* Serial Peripheral Interface 0 */ +#define AT91C_ID_SPI1 ( ( unsigned int ) 5 ) /* Serial Peripheral Interface 1 */ +#define AT91C_ID_US0 ( ( unsigned int ) 6 ) /* USART 0 */ +#define AT91C_ID_US1 ( ( unsigned int ) 7 ) /* USART 1 */ +#define AT91C_ID_SSC ( ( unsigned int ) 8 ) /* Serial Synchronous Controller */ +#define AT91C_ID_TWI ( ( unsigned int ) 9 ) /* Two-Wire Interface */ +#define AT91C_ID_PWMC ( ( unsigned int ) 10 ) /* PWM Controller */ +#define AT91C_ID_UDP ( ( unsigned int ) 11 ) /* USB Device Port */ +#define AT91C_ID_TC0 ( ( unsigned int ) 12 ) /* Timer Counter 0 */ +#define AT91C_ID_TC1 ( ( unsigned int ) 13 ) /* Timer Counter 1 */ +#define AT91C_ID_TC2 ( ( unsigned int ) 14 ) /* Timer Counter 2 */ +#define AT91C_ID_CAN ( ( unsigned int ) 15 ) /* Control Area Network Controller */ +#define AT91C_ID_EMAC ( ( unsigned int ) 16 ) /* Ethernet MAC */ +#define AT91C_ID_ADC ( ( unsigned int ) 17 ) /* Analog-to-Digital Converter */ +#define AT91C_ID_AES ( ( unsigned int ) 18 ) /* Advanced Encryption Standard 128-bit */ +#define AT91C_ID_TDES ( ( unsigned int ) 19 ) /* Triple Data Encryption Standard */ +#define AT91C_ID_20_Reserved ( ( unsigned int ) 20 ) /* Reserved */ +#define AT91C_ID_21_Reserved ( ( unsigned int ) 21 ) /* Reserved */ +#define AT91C_ID_22_Reserved ( ( unsigned int ) 22 ) /* Reserved */ +#define AT91C_ID_23_Reserved ( ( unsigned int ) 23 ) /* Reserved */ +#define AT91C_ID_24_Reserved ( ( unsigned int ) 24 ) /* Reserved */ +#define AT91C_ID_25_Reserved ( ( unsigned int ) 25 ) /* Reserved */ +#define AT91C_ID_26_Reserved ( ( unsigned int ) 26 ) /* Reserved */ +#define AT91C_ID_27_Reserved ( ( unsigned int ) 27 ) /* Reserved */ +#define AT91C_ID_28_Reserved ( ( unsigned int ) 28 ) /* Reserved */ +#define AT91C_ID_29_Reserved ( ( unsigned int ) 29 ) /* Reserved */ +#define AT91C_ID_IRQ0 ( ( unsigned int ) 30 ) /* Advanced Interrupt Controller (IRQ0) */ +#define AT91C_ID_IRQ1 ( ( unsigned int ) 31 ) /* Advanced Interrupt Controller (IRQ1) */ + +/* ***************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 */ +/* ***************************************************************************** */ +#define AT91C_BASE_SYS ( ( AT91PS_SYS ) 0xFFFFF000 ) /* (SYS) Base Address */ +#define AT91C_BASE_AIC ( ( AT91PS_AIC ) 0xFFFFF000 ) /* (AIC) Base Address */ +#define AT91C_BASE_PDC_DBGU ( ( AT91PS_PDC ) 0xFFFFF300 ) /* (PDC_DBGU) Base Address */ +#define AT91C_BASE_DBGU ( ( AT91PS_DBGU ) 0xFFFFF200 ) /* (DBGU) Base Address */ +#define AT91C_BASE_PIOA ( ( AT91PS_PIO ) 0xFFFFF400 ) /* (PIOA) Base Address */ +#define AT91C_BASE_PIOB ( ( AT91PS_PIO ) 0xFFFFF600 ) /* (PIOB) Base Address */ +#define AT91C_BASE_CKGR ( ( AT91PS_CKGR ) 0xFFFFFC20 ) /* (CKGR) Base Address */ +#define AT91C_BASE_PMC ( ( AT91PS_PMC ) 0xFFFFFC00 ) /* (PMC) Base Address */ +#define AT91C_BASE_RSTC ( ( AT91PS_RSTC ) 0xFFFFFD00 ) /* (RSTC) Base Address */ +#define AT91C_BASE_RTTC ( ( AT91PS_RTTC ) 0xFFFFFD20 ) /* (RTTC) Base Address */ +#define AT91C_BASE_PITC ( ( AT91PS_PITC ) 0xFFFFFD30 ) /* (PITC) Base Address */ +#define AT91C_BASE_WDTC ( ( AT91PS_WDTC ) 0xFFFFFD40 ) /* (WDTC) Base Address */ +#define AT91C_BASE_VREG ( ( AT91PS_VREG ) 0xFFFFFD60 ) /* (VREG) Base Address */ +#define AT91C_BASE_MC ( ( AT91PS_MC ) 0xFFFFFF00 ) /* (MC) Base Address */ +#define AT91C_BASE_PDC_SPI1 ( ( AT91PS_PDC ) 0xFFFE4100 ) /* (PDC_SPI1) Base Address */ +#define AT91C_BASE_SPI1 ( ( AT91PS_SPI ) 0xFFFE4000 ) /* (SPI1) Base Address */ +#define AT91C_BASE_PDC_SPI0 ( ( AT91PS_PDC ) 0xFFFE0100 ) /* (PDC_SPI0) Base Address */ +#define AT91C_BASE_SPI0 ( ( AT91PS_SPI ) 0xFFFE0000 ) /* (SPI0) Base Address */ +#define AT91C_BASE_PDC_US1 ( ( AT91PS_PDC ) 0xFFFC4100 ) /* (PDC_US1) Base Address */ +#define AT91C_BASE_US1 ( ( AT91PS_USART ) 0xFFFC4000 ) /* (US1) Base Address */ +#define AT91C_BASE_PDC_US0 ( ( AT91PS_PDC ) 0xFFFC0100 ) /* (PDC_US0) Base Address */ +#define AT91C_BASE_US0 ( ( AT91PS_USART ) 0xFFFC0000 ) /* (US0) Base Address */ +#define AT91C_BASE_PDC_SSC ( ( AT91PS_PDC ) 0xFFFD4100 ) /* (PDC_SSC) Base Address */ +#define AT91C_BASE_SSC ( ( AT91PS_SSC ) 0xFFFD4000 ) /* (SSC) Base Address */ +#define AT91C_BASE_TWI ( ( AT91PS_TWI ) 0xFFFB8000 ) /* (TWI) Base Address */ +#define AT91C_BASE_PWMC_CH3 ( ( AT91PS_PWMC_CH ) 0xFFFCC260 ) /* (PWMC_CH3) Base Address */ +#define AT91C_BASE_PWMC_CH2 ( ( AT91PS_PWMC_CH ) 0xFFFCC240 ) /* (PWMC_CH2) Base Address */ +#define AT91C_BASE_PWMC_CH1 ( ( AT91PS_PWMC_CH ) 0xFFFCC220 ) /* (PWMC_CH1) Base Address */ +#define AT91C_BASE_PWMC_CH0 ( ( AT91PS_PWMC_CH ) 0xFFFCC200 ) /* (PWMC_CH0) Base Address */ +#define AT91C_BASE_PWMC ( ( AT91PS_PWMC ) 0xFFFCC000 ) /* (PWMC) Base Address */ +#define AT91C_BASE_UDP ( ( AT91PS_UDP ) 0xFFFB0000 ) /* (UDP) Base Address */ +#define AT91C_BASE_TC0 ( ( AT91PS_TC ) 0xFFFA0000 ) /* (TC0) Base Address */ +#define AT91C_BASE_TC1 ( ( AT91PS_TC ) 0xFFFA0040 ) /* (TC1) Base Address */ +#define AT91C_BASE_TC2 ( ( AT91PS_TC ) 0xFFFA0080 ) /* (TC2) Base Address */ +#define AT91C_BASE_TCB ( ( AT91PS_TCB ) 0xFFFA0000 ) /* (TCB) Base Address */ +#define AT91C_BASE_CAN_MB0 ( ( AT91PS_CAN_MB ) 0xFFFD0200 ) /* (CAN_MB0) Base Address */ +#define AT91C_BASE_CAN_MB1 ( ( AT91PS_CAN_MB ) 0xFFFD0220 ) /* (CAN_MB1) Base Address */ +#define AT91C_BASE_CAN_MB2 ( ( AT91PS_CAN_MB ) 0xFFFD0240 ) /* (CAN_MB2) Base Address */ +#define AT91C_BASE_CAN_MB3 ( ( AT91PS_CAN_MB ) 0xFFFD0260 ) /* (CAN_MB3) Base Address */ +#define AT91C_BASE_CAN_MB4 ( ( AT91PS_CAN_MB ) 0xFFFD0280 ) /* (CAN_MB4) Base Address */ +#define AT91C_BASE_CAN_MB5 ( ( AT91PS_CAN_MB ) 0xFFFD02A0 ) /* (CAN_MB5) Base Address */ +#define AT91C_BASE_CAN_MB6 ( ( AT91PS_CAN_MB ) 0xFFFD02C0 ) /* (CAN_MB6) Base Address */ +#define AT91C_BASE_CAN_MB7 ( ( AT91PS_CAN_MB ) 0xFFFD02E0 ) /* (CAN_MB7) Base Address */ +#define AT91C_BASE_CAN ( ( AT91PS_CAN ) 0xFFFD0000 ) /* (CAN) Base Address */ +#define AT91C_BASE_EMAC ( ( AT91PS_EMAC ) 0xFFFDC000 ) /* (EMAC) Base Address */ +#define AT91C_BASE_PDC_ADC ( ( AT91PS_PDC ) 0xFFFD8100 ) /* (PDC_ADC) Base Address */ +#define AT91C_BASE_ADC ( ( AT91PS_ADC ) 0xFFFD8000 ) /* (ADC) Base Address */ +#define AT91C_BASE_PDC_AES ( ( AT91PS_PDC ) 0xFFFA4100 ) /* (PDC_AES) Base Address */ +#define AT91C_BASE_AES ( ( AT91PS_AES ) 0xFFFA4000 ) /* (AES) Base Address */ +#define AT91C_BASE_PDC_TDES ( ( AT91PS_PDC ) 0xFFFA8100 ) /* (PDC_TDES) Base Address */ +#define AT91C_BASE_TDES ( ( AT91PS_TDES ) 0xFFFA8000 ) /* (TDES) Base Address */ + +/* ***************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 */ +/* ***************************************************************************** */ +#define AT91C_ISRAM ( ( char * ) 0x00200000 ) /* Internal SRAM base address */ +#define AT91C_ISRAM_SIZE ( ( unsigned int ) 0x00010000 ) /* Internal SRAM size in byte (64 Kbyte) */ +#define AT91C_IFLASH ( ( char * ) 0x00100000 ) /* Internal ROM base address */ +#define AT91C_IFLASH_SIZE ( ( unsigned int ) 0x00040000 ) /* Internal ROM size in byte (256 Kbyte) */ + +#define AT91F_AIC_ConfigureIt( irq_id, priority, src_type, newHandler ) \ + { \ + unsigned int mask; \ + \ + mask = 0x1 << irq_id; \ + /* Disable the interrupt on the interrupt controller */ \ + AT91C_BASE_AIC->AIC_IDCR = mask; \ + /* Save the interrupt handler routine pointer and the interrupt priority */ \ + AT91C_BASE_AIC->AIC_SVR[ irq_id ] = ( unsigned int ) newHandler; \ + /* Store the Source Mode Register */ \ + AT91C_BASE_AIC->AIC_SMR[ irq_id ] = src_type | priority; \ + /* Clear the interrupt on the interrupt controller */ \ + AT91C_BASE_AIC->AIC_ICCR = mask; \ + } + + +#endif /* ifndef AT91SAM7X256_H */ diff --git a/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h b/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h new file mode 100644 index 000000000..a148b18a6 --- /dev/null +++ b/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h @@ -0,0 +1,6373 @@ +/* - ---------------------------------------------------------------------------- */ +/* - ATMEL Microcontroller Software Support - ROUSSET - */ +/* - ---------------------------------------------------------------------------- */ +/* - DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* - IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* - DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* - INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* - LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* - OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* - LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* - NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* - EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* - ---------------------------------------------------------------------------- */ +/* - File Name : AT91SAM7X256.h */ +/* - Object : AT91SAM7X256 definitions */ +/* - Generated : AT91 SW Application Group 05/20/2005 (16:22:29) */ +/* - */ +/* - CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005// */ +/* - CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// */ +/* - CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// */ +/* - CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// */ +/* - CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// */ +/* - CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// */ +/* - CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// */ +/* - CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// */ +/* - CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// */ +/* - CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// */ +/* - CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// */ +/* - CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// */ +/* - CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// */ +/* - CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// */ +/* - CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// */ +/* - CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// */ +/* - CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// */ +/* - CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// */ +/* - CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// */ +/* - CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// */ +/* - CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// */ +/* - CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// */ +/* - CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// */ +/* - CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// */ +/* - CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// */ +/* - ---------------------------------------------------------------------------- */ + +#ifndef AT91SAM7X256_H +#define AT91SAM7X256_H + +typedef volatile unsigned int AT91_REG; /* Hardware register definition */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR System Peripherals */ +/* ***************************************************************************** */ +typedef struct _AT91S_SYS +{ + AT91_REG AIC_SMR[ 32 ]; /* Source Mode Register */ + AT91_REG AIC_SVR[ 32 ]; /* Source Vector Register */ + AT91_REG AIC_IVR; /* IRQ Vector Register */ + AT91_REG AIC_FVR; /* FIQ Vector Register */ + AT91_REG AIC_ISR; /* Interrupt Status Register */ + AT91_REG AIC_IPR; /* Interrupt Pending Register */ + AT91_REG AIC_IMR; /* Interrupt Mask Register */ + AT91_REG AIC_CISR; /* Core Interrupt Status Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG AIC_IECR; /* Interrupt Enable Command Register */ + AT91_REG AIC_IDCR; /* Interrupt Disable Command Register */ + AT91_REG AIC_ICCR; /* Interrupt Clear Command Register */ + AT91_REG AIC_ISCR; /* Interrupt Set Command Register */ + AT91_REG AIC_EOICR; /* End of Interrupt Command Register */ + AT91_REG AIC_SPU; /* Spurious Vector Register */ + AT91_REG AIC_DCR; /* Debug Control Register (Protect) */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG AIC_FFER; /* Fast Forcing Enable Register */ + AT91_REG AIC_FFDR; /* Fast Forcing Disable Register */ + AT91_REG AIC_FFSR; /* Fast Forcing Status Register */ + AT91_REG Reserved2[ 45 ]; /* */ + AT91_REG DBGU_CR; /* Control Register */ + AT91_REG DBGU_MR; /* Mode Register */ + AT91_REG DBGU_IER; /* Interrupt Enable Register */ + AT91_REG DBGU_IDR; /* Interrupt Disable Register */ + AT91_REG DBGU_IMR; /* Interrupt Mask Register */ + AT91_REG DBGU_CSR; /* Channel Status Register */ + AT91_REG DBGU_RHR; /* Receiver Holding Register */ + AT91_REG DBGU_THR; /* Transmitter Holding Register */ + AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */ + AT91_REG Reserved3[ 7 ]; /* */ + AT91_REG DBGU_CIDR; /* Chip ID Register */ + AT91_REG DBGU_EXID; /* Chip ID Extension Register */ + AT91_REG DBGU_FNTR; /* Force NTRST Register */ + AT91_REG Reserved4[ 45 ]; /* */ + AT91_REG DBGU_RPR; /* Receive Pointer Register */ + AT91_REG DBGU_RCR; /* Receive Counter Register */ + AT91_REG DBGU_TPR; /* Transmit Pointer Register */ + AT91_REG DBGU_TCR; /* Transmit Counter Register */ + AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */ + AT91_REG DBGU_RNCR; /* Receive Next Counter Register */ + AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */ + AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */ + AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */ + AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */ + AT91_REG Reserved5[ 54 ]; /* */ + AT91_REG PIOA_PER; /* PIO Enable Register */ + AT91_REG PIOA_PDR; /* PIO Disable Register */ + AT91_REG PIOA_PSR; /* PIO Status Register */ + AT91_REG Reserved6[ 1 ]; /* */ + AT91_REG PIOA_OER; /* Output Enable Register */ + AT91_REG PIOA_ODR; /* Output Disable Registerr */ + AT91_REG PIOA_OSR; /* Output Status Register */ + AT91_REG Reserved7[ 1 ]; /* */ + AT91_REG PIOA_IFER; /* Input Filter Enable Register */ + AT91_REG PIOA_IFDR; /* Input Filter Disable Register */ + AT91_REG PIOA_IFSR; /* Input Filter Status Register */ + AT91_REG Reserved8[ 1 ]; /* */ + AT91_REG PIOA_SODR; /* Set Output Data Register */ + AT91_REG PIOA_CODR; /* Clear Output Data Register */ + AT91_REG PIOA_ODSR; /* Output Data Status Register */ + AT91_REG PIOA_PDSR; /* Pin Data Status Register */ + AT91_REG PIOA_IER; /* Interrupt Enable Register */ + AT91_REG PIOA_IDR; /* Interrupt Disable Register */ + AT91_REG PIOA_IMR; /* Interrupt Mask Register */ + AT91_REG PIOA_ISR; /* Interrupt Status Register */ + AT91_REG PIOA_MDER; /* Multi-driver Enable Register */ + AT91_REG PIOA_MDDR; /* Multi-driver Disable Register */ + AT91_REG PIOA_MDSR; /* Multi-driver Status Register */ + AT91_REG Reserved9[ 1 ]; /* */ + AT91_REG PIOA_PPUDR; /* Pull-up Disable Register */ + AT91_REG PIOA_PPUER; /* Pull-up Enable Register */ + AT91_REG PIOA_PPUSR; /* Pull-up Status Register */ + AT91_REG Reserved10[ 1 ]; /* */ + AT91_REG PIOA_ASR; /* Select A Register */ + AT91_REG PIOA_BSR; /* Select B Register */ + AT91_REG PIOA_ABSR; /* AB Select Status Register */ + AT91_REG Reserved11[ 9 ]; /* */ + AT91_REG PIOA_OWER; /* Output Write Enable Register */ + AT91_REG PIOA_OWDR; /* Output Write Disable Register */ + AT91_REG PIOA_OWSR; /* Output Write Status Register */ + AT91_REG Reserved12[ 85 ]; /* */ + AT91_REG PIOB_PER; /* PIO Enable Register */ + AT91_REG PIOB_PDR; /* PIO Disable Register */ + AT91_REG PIOB_PSR; /* PIO Status Register */ + AT91_REG Reserved13[ 1 ]; /* */ + AT91_REG PIOB_OER; /* Output Enable Register */ + AT91_REG PIOB_ODR; /* Output Disable Registerr */ + AT91_REG PIOB_OSR; /* Output Status Register */ + AT91_REG Reserved14[ 1 ]; /* */ + AT91_REG PIOB_IFER; /* Input Filter Enable Register */ + AT91_REG PIOB_IFDR; /* Input Filter Disable Register */ + AT91_REG PIOB_IFSR; /* Input Filter Status Register */ + AT91_REG Reserved15[ 1 ]; /* */ + AT91_REG PIOB_SODR; /* Set Output Data Register */ + AT91_REG PIOB_CODR; /* Clear Output Data Register */ + AT91_REG PIOB_ODSR; /* Output Data Status Register */ + AT91_REG PIOB_PDSR; /* Pin Data Status Register */ + AT91_REG PIOB_IER; /* Interrupt Enable Register */ + AT91_REG PIOB_IDR; /* Interrupt Disable Register */ + AT91_REG PIOB_IMR; /* Interrupt Mask Register */ + AT91_REG PIOB_ISR; /* Interrupt Status Register */ + AT91_REG PIOB_MDER; /* Multi-driver Enable Register */ + AT91_REG PIOB_MDDR; /* Multi-driver Disable Register */ + AT91_REG PIOB_MDSR; /* Multi-driver Status Register */ + AT91_REG Reserved16[ 1 ]; /* */ + AT91_REG PIOB_PPUDR; /* Pull-up Disable Register */ + AT91_REG PIOB_PPUER; /* Pull-up Enable Register */ + AT91_REG PIOB_PPUSR; /* Pull-up Status Register */ + AT91_REG Reserved17[ 1 ]; /* */ + AT91_REG PIOB_ASR; /* Select A Register */ + AT91_REG PIOB_BSR; /* Select B Register */ + AT91_REG PIOB_ABSR; /* AB Select Status Register */ + AT91_REG Reserved18[ 9 ]; /* */ + AT91_REG PIOB_OWER; /* Output Write Enable Register */ + AT91_REG PIOB_OWDR; /* Output Write Disable Register */ + AT91_REG PIOB_OWSR; /* Output Write Status Register */ + AT91_REG Reserved19[ 341 ]; /* */ + AT91_REG PMC_SCER; /* System Clock Enable Register */ + AT91_REG PMC_SCDR; /* System Clock Disable Register */ + AT91_REG PMC_SCSR; /* System Clock Status Register */ + AT91_REG Reserved20[ 1 ]; /* */ + AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */ + AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */ + AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */ + AT91_REG Reserved21[ 1 ]; /* */ + AT91_REG PMC_MOR; /* Main Oscillator Register */ + AT91_REG PMC_MCFR; /* Main Clock Frequency Register */ + AT91_REG Reserved22[ 1 ]; /* */ + AT91_REG PMC_PLLR; /* PLL Register */ + AT91_REG PMC_MCKR; /* Master Clock Register */ + AT91_REG Reserved23[ 3 ]; /* */ + AT91_REG PMC_PCKR[ 4 ]; /* Programmable Clock Register */ + AT91_REG Reserved24[ 4 ]; /* */ + AT91_REG PMC_IER; /* Interrupt Enable Register */ + AT91_REG PMC_IDR; /* Interrupt Disable Register */ + AT91_REG PMC_SR; /* Status Register */ + AT91_REG PMC_IMR; /* Interrupt Mask Register */ + AT91_REG Reserved25[ 36 ]; /* */ + AT91_REG RSTC_RCR; /* Reset Control Register */ + AT91_REG RSTC_RSR; /* Reset Status Register */ + AT91_REG RSTC_RMR; /* Reset Mode Register */ + AT91_REG Reserved26[ 5 ]; /* */ + AT91_REG RTTC_RTMR; /* Real-time Mode Register */ + AT91_REG RTTC_RTAR; /* Real-time Alarm Register */ + AT91_REG RTTC_RTVR; /* Real-time Value Register */ + AT91_REG RTTC_RTSR; /* Real-time Status Register */ + AT91_REG PITC_PIMR; /* Period Interval Mode Register */ + AT91_REG PITC_PISR; /* Period Interval Status Register */ + AT91_REG PITC_PIVR; /* Period Interval Value Register */ + AT91_REG PITC_PIIR; /* Period Interval Image Register */ + AT91_REG WDTC_WDCR; /* Watchdog Control Register */ + AT91_REG WDTC_WDMR; /* Watchdog Mode Register */ + AT91_REG WDTC_WDSR; /* Watchdog Status Register */ + AT91_REG Reserved27[ 5 ]; /* */ + AT91_REG VREG_MR; /* Voltage Regulator Mode Register */ +} AT91S_SYS, * AT91PS_SYS; + + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Advanced Interrupt Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_AIC +{ + AT91_REG AIC_SMR[ 32 ]; /* Source Mode Register */ + AT91_REG AIC_SVR[ 32 ]; /* Source Vector Register */ + AT91_REG AIC_IVR; /* IRQ Vector Register */ + AT91_REG AIC_FVR; /* FIQ Vector Register */ + AT91_REG AIC_ISR; /* Interrupt Status Register */ + AT91_REG AIC_IPR; /* Interrupt Pending Register */ + AT91_REG AIC_IMR; /* Interrupt Mask Register */ + AT91_REG AIC_CISR; /* Core Interrupt Status Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG AIC_IECR; /* Interrupt Enable Command Register */ + AT91_REG AIC_IDCR; /* Interrupt Disable Command Register */ + AT91_REG AIC_ICCR; /* Interrupt Clear Command Register */ + AT91_REG AIC_ISCR; /* Interrupt Set Command Register */ + AT91_REG AIC_EOICR; /* End of Interrupt Command Register */ + AT91_REG AIC_SPU; /* Spurious Vector Register */ + AT91_REG AIC_DCR; /* Debug Control Register (Protect) */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG AIC_FFER; /* Fast Forcing Enable Register */ + AT91_REG AIC_FFDR; /* Fast Forcing Disable Register */ + AT91_REG AIC_FFSR; /* Fast Forcing Status Register */ +} AT91S_AIC, * AT91PS_AIC; + +/* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */ +#define AT91C_AIC_PRIOR ( ( unsigned int ) 0x7 << 0 ) /* (AIC) Priority Level */ +#define AT91C_AIC_PRIOR_LOWEST ( ( unsigned int ) 0x0 ) /* (AIC) Lowest priority level */ +#define AT91C_AIC_PRIOR_HIGHEST ( ( unsigned int ) 0x7 ) /* (AIC) Highest priority level */ +#define AT91C_AIC_SRCTYPE ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Interrupt Source Type */ +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ( ( unsigned int ) 0x0 << 5 ) /* (AIC) Internal Sources Code Label High-level Sensitive */ +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ( ( unsigned int ) 0x0 << 5 ) /* (AIC) External Sources Code Label Low-level Sensitive */ +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ( ( unsigned int ) 0x1 << 5 ) /* (AIC) Internal Sources Code Label Positive Edge triggered */ +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ( ( unsigned int ) 0x1 << 5 ) /* (AIC) External Sources Code Label Negative Edge triggered */ +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ( ( unsigned int ) 0x2 << 5 ) /* (AIC) Internal Or External Sources Code Label High-level Sensitive */ +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Internal Or External Sources Code Label Positive Edge triggered */ +/* -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- */ +#define AT91C_AIC_NFIQ ( ( unsigned int ) 0x1 << 0 ) /* (AIC) NFIQ Status */ +#define AT91C_AIC_NIRQ ( ( unsigned int ) 0x1 << 1 ) /* (AIC) NIRQ Status */ +/* -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- */ +#define AT91C_AIC_DCR_PROT ( ( unsigned int ) 0x1 << 0 ) /* (AIC) Protection Mode */ +#define AT91C_AIC_DCR_GMSK ( ( unsigned int ) 0x1 << 1 ) /* (AIC) General Mask */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Peripheral DMA Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_PDC +{ + AT91_REG PDC_RPR; /* Receive Pointer Register */ + AT91_REG PDC_RCR; /* Receive Counter Register */ + AT91_REG PDC_TPR; /* Transmit Pointer Register */ + AT91_REG PDC_TCR; /* Transmit Counter Register */ + AT91_REG PDC_RNPR; /* Receive Next Pointer Register */ + AT91_REG PDC_RNCR; /* Receive Next Counter Register */ + AT91_REG PDC_TNPR; /* Transmit Next Pointer Register */ + AT91_REG PDC_TNCR; /* Transmit Next Counter Register */ + AT91_REG PDC_PTCR; /* PDC Transfer Control Register */ + AT91_REG PDC_PTSR; /* PDC Transfer Status Register */ +} AT91S_PDC, * AT91PS_PDC; + +/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */ +#define AT91C_PDC_RXTEN ( ( unsigned int ) 0x1 << 0 ) /* (PDC) Receiver Transfer Enable */ +#define AT91C_PDC_RXTDIS ( ( unsigned int ) 0x1 << 1 ) /* (PDC) Receiver Transfer Disable */ +#define AT91C_PDC_TXTEN ( ( unsigned int ) 0x1 << 8 ) /* (PDC) Transmitter Transfer Enable */ +#define AT91C_PDC_TXTDIS ( ( unsigned int ) 0x1 << 9 ) /* (PDC) Transmitter Transfer Disable */ +/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Debug Unit */ +/* ***************************************************************************** */ +typedef struct _AT91S_DBGU +{ + AT91_REG DBGU_CR; /* Control Register */ + AT91_REG DBGU_MR; /* Mode Register */ + AT91_REG DBGU_IER; /* Interrupt Enable Register */ + AT91_REG DBGU_IDR; /* Interrupt Disable Register */ + AT91_REG DBGU_IMR; /* Interrupt Mask Register */ + AT91_REG DBGU_CSR; /* Channel Status Register */ + AT91_REG DBGU_RHR; /* Receiver Holding Register */ + AT91_REG DBGU_THR; /* Transmitter Holding Register */ + AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */ + AT91_REG Reserved0[ 7 ]; /* */ + AT91_REG DBGU_CIDR; /* Chip ID Register */ + AT91_REG DBGU_EXID; /* Chip ID Extension Register */ + AT91_REG DBGU_FNTR; /* Force NTRST Register */ + AT91_REG Reserved1[ 45 ]; /* */ + AT91_REG DBGU_RPR; /* Receive Pointer Register */ + AT91_REG DBGU_RCR; /* Receive Counter Register */ + AT91_REG DBGU_TPR; /* Transmit Pointer Register */ + AT91_REG DBGU_TCR; /* Transmit Counter Register */ + AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */ + AT91_REG DBGU_RNCR; /* Receive Next Counter Register */ + AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */ + AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */ + AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */ + AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */ +} AT91S_DBGU, * AT91PS_DBGU; + +/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */ +#define AT91C_US_RSTRX ( ( unsigned int ) 0x1 << 2 ) /* (DBGU) Reset Receiver */ +#define AT91C_US_RSTTX ( ( unsigned int ) 0x1 << 3 ) /* (DBGU) Reset Transmitter */ +#define AT91C_US_RXEN ( ( unsigned int ) 0x1 << 4 ) /* (DBGU) Receiver Enable */ +#define AT91C_US_RXDIS ( ( unsigned int ) 0x1 << 5 ) /* (DBGU) Receiver Disable */ +#define AT91C_US_TXEN ( ( unsigned int ) 0x1 << 6 ) /* (DBGU) Transmitter Enable */ +#define AT91C_US_TXDIS ( ( unsigned int ) 0x1 << 7 ) /* (DBGU) Transmitter Disable */ +#define AT91C_US_RSTSTA ( ( unsigned int ) 0x1 << 8 ) /* (DBGU) Reset Status Bits */ +/* -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- */ +#define AT91C_US_PAR ( ( unsigned int ) 0x7 << 9 ) /* (DBGU) Parity type */ +#define AT91C_US_PAR_EVEN ( ( unsigned int ) 0x0 << 9 ) /* (DBGU) Even Parity */ +#define AT91C_US_PAR_ODD ( ( unsigned int ) 0x1 << 9 ) /* (DBGU) Odd Parity */ +#define AT91C_US_PAR_SPACE ( ( unsigned int ) 0x2 << 9 ) /* (DBGU) Parity forced to 0 (Space) */ +#define AT91C_US_PAR_MARK ( ( unsigned int ) 0x3 << 9 ) /* (DBGU) Parity forced to 1 (Mark) */ +#define AT91C_US_PAR_NONE ( ( unsigned int ) 0x4 << 9 ) /* (DBGU) No Parity */ +#define AT91C_US_PAR_MULTI_DROP ( ( unsigned int ) 0x6 << 9 ) /* (DBGU) Multi-drop mode */ +#define AT91C_US_CHMODE ( ( unsigned int ) 0x3 << 14 ) /* (DBGU) Channel Mode */ +#define AT91C_US_CHMODE_NORMAL ( ( unsigned int ) 0x0 << 14 ) /* (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. */ +#define AT91C_US_CHMODE_AUTO ( ( unsigned int ) 0x1 << 14 ) /* (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. */ +#define AT91C_US_CHMODE_LOCAL ( ( unsigned int ) 0x2 << 14 ) /* (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. */ +#define AT91C_US_CHMODE_REMOTE ( ( unsigned int ) 0x3 << 14 ) /* (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. */ +/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ +#define AT91C_US_RXRDY ( ( unsigned int ) 0x1 << 0 ) /* (DBGU) RXRDY Interrupt */ +#define AT91C_US_TXRDY ( ( unsigned int ) 0x1 << 1 ) /* (DBGU) TXRDY Interrupt */ +#define AT91C_US_ENDRX ( ( unsigned int ) 0x1 << 3 ) /* (DBGU) End of Receive Transfer Interrupt */ +#define AT91C_US_ENDTX ( ( unsigned int ) 0x1 << 4 ) /* (DBGU) End of Transmit Interrupt */ +#define AT91C_US_OVRE ( ( unsigned int ) 0x1 << 5 ) /* (DBGU) Overrun Interrupt */ +#define AT91C_US_FRAME ( ( unsigned int ) 0x1 << 6 ) /* (DBGU) Framing Error Interrupt */ +#define AT91C_US_PARE ( ( unsigned int ) 0x1 << 7 ) /* (DBGU) Parity Error Interrupt */ +#define AT91C_US_TXEMPTY ( ( unsigned int ) 0x1 << 9 ) /* (DBGU) TXEMPTY Interrupt */ +#define AT91C_US_TXBUFE ( ( unsigned int ) 0x1 << 11 ) /* (DBGU) TXBUFE Interrupt */ +#define AT91C_US_RXBUFF ( ( unsigned int ) 0x1 << 12 ) /* (DBGU) RXBUFF Interrupt */ +#define AT91C_US_COMM_TX ( ( unsigned int ) 0x1 << 30 ) /* (DBGU) COMM_TX Interrupt */ +#define AT91C_US_COMM_RX ( ( unsigned int ) 0x1 << 31 ) /* (DBGU) COMM_RX Interrupt */ +/* -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- */ +/* -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- */ +/* -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- */ +/* -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- */ +#define AT91C_US_FORCE_NTRST ( ( unsigned int ) 0x1 << 0 ) /* (DBGU) Force NTRST in JTAG */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Parallel Input Output Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_PIO +{ + AT91_REG PIO_PER; /* PIO Enable Register */ + AT91_REG PIO_PDR; /* PIO Disable Register */ + AT91_REG PIO_PSR; /* PIO Status Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG PIO_OER; /* Output Enable Register */ + AT91_REG PIO_ODR; /* Output Disable Registerr */ + AT91_REG PIO_OSR; /* Output Status Register */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG PIO_IFER; /* Input Filter Enable Register */ + AT91_REG PIO_IFDR; /* Input Filter Disable Register */ + AT91_REG PIO_IFSR; /* Input Filter Status Register */ + AT91_REG Reserved2[ 1 ]; /* */ + AT91_REG PIO_SODR; /* Set Output Data Register */ + AT91_REG PIO_CODR; /* Clear Output Data Register */ + AT91_REG PIO_ODSR; /* Output Data Status Register */ + AT91_REG PIO_PDSR; /* Pin Data Status Register */ + AT91_REG PIO_IER; /* Interrupt Enable Register */ + AT91_REG PIO_IDR; /* Interrupt Disable Register */ + AT91_REG PIO_IMR; /* Interrupt Mask Register */ + AT91_REG PIO_ISR; /* Interrupt Status Register */ + AT91_REG PIO_MDER; /* Multi-driver Enable Register */ + AT91_REG PIO_MDDR; /* Multi-driver Disable Register */ + AT91_REG PIO_MDSR; /* Multi-driver Status Register */ + AT91_REG Reserved3[ 1 ]; /* */ + AT91_REG PIO_PPUDR; /* Pull-up Disable Register */ + AT91_REG PIO_PPUER; /* Pull-up Enable Register */ + AT91_REG PIO_PPUSR; /* Pull-up Status Register */ + AT91_REG Reserved4[ 1 ]; /* */ + AT91_REG PIO_ASR; /* Select A Register */ + AT91_REG PIO_BSR; /* Select B Register */ + AT91_REG PIO_ABSR; /* AB Select Status Register */ + AT91_REG Reserved5[ 9 ]; /* */ + AT91_REG PIO_OWER; /* Output Write Enable Register */ + AT91_REG PIO_OWDR; /* Output Write Disable Register */ + AT91_REG PIO_OWSR; /* Output Write Status Register */ +} AT91S_PIO, * AT91PS_PIO; + + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Clock Generator Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_CKGR +{ + AT91_REG CKGR_MOR; /* Main Oscillator Register */ + AT91_REG CKGR_MCFR; /* Main Clock Frequency Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG CKGR_PLLR; /* PLL Register */ +} AT91S_CKGR, * AT91PS_CKGR; + +/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */ +#define AT91C_CKGR_MOSCEN ( ( unsigned int ) 0x1 << 0 ) /* (CKGR) Main Oscillator Enable */ +#define AT91C_CKGR_OSCBYPASS ( ( unsigned int ) 0x1 << 1 ) /* (CKGR) Main Oscillator Bypass */ +#define AT91C_CKGR_OSCOUNT ( ( unsigned int ) 0xFF << 8 ) /* (CKGR) Main Oscillator Start-up Time */ +/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */ +#define AT91C_CKGR_MAINF ( ( unsigned int ) 0xFFFF << 0 ) /* (CKGR) Main Clock Frequency */ +#define AT91C_CKGR_MAINRDY ( ( unsigned int ) 0x1 << 16 ) /* (CKGR) Main Clock Ready */ +/* -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- */ +#define AT91C_CKGR_DIV ( ( unsigned int ) 0xFF << 0 ) /* (CKGR) Divider Selected */ +#define AT91C_CKGR_DIV_0 ( ( unsigned int ) 0x0 ) /* (CKGR) Divider output is 0 */ +#define AT91C_CKGR_DIV_BYPASS ( ( unsigned int ) 0x1 ) /* (CKGR) Divider is bypassed */ +#define AT91C_CKGR_PLLCOUNT ( ( unsigned int ) 0x3F << 8 ) /* (CKGR) PLL Counter */ +#define AT91C_CKGR_OUT ( ( unsigned int ) 0x3 << 14 ) /* (CKGR) PLL Output Frequency Range */ +#define AT91C_CKGR_OUT_0 ( ( unsigned int ) 0x0 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_1 ( ( unsigned int ) 0x1 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_2 ( ( unsigned int ) 0x2 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_3 ( ( unsigned int ) 0x3 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_MUL ( ( unsigned int ) 0x7FF << 16 ) /* (CKGR) PLL Multiplier */ +#define AT91C_CKGR_USBDIV ( ( unsigned int ) 0x3 << 28 ) /* (CKGR) Divider for USB Clocks */ +#define AT91C_CKGR_USBDIV_0 ( ( unsigned int ) 0x0 << 28 ) /* (CKGR) Divider output is PLL clock output */ +#define AT91C_CKGR_USBDIV_1 ( ( unsigned int ) 0x1 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 2 */ +#define AT91C_CKGR_USBDIV_2 ( ( unsigned int ) 0x2 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 4 */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Power Management Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_PMC +{ + AT91_REG PMC_SCER; /* System Clock Enable Register */ + AT91_REG PMC_SCDR; /* System Clock Disable Register */ + AT91_REG PMC_SCSR; /* System Clock Status Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */ + AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */ + AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG PMC_MOR; /* Main Oscillator Register */ + AT91_REG PMC_MCFR; /* Main Clock Frequency Register */ + AT91_REG Reserved2[ 1 ]; /* */ + AT91_REG PMC_PLLR; /* PLL Register */ + AT91_REG PMC_MCKR; /* Master Clock Register */ + AT91_REG Reserved3[ 3 ]; /* */ + AT91_REG PMC_PCKR[ 4 ]; /* Programmable Clock Register */ + AT91_REG Reserved4[ 4 ]; /* */ + AT91_REG PMC_IER; /* Interrupt Enable Register */ + AT91_REG PMC_IDR; /* Interrupt Disable Register */ + AT91_REG PMC_SR; /* Status Register */ + AT91_REG PMC_IMR; /* Interrupt Mask Register */ +} AT91S_PMC, * AT91PS_PMC; + +/* -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- */ +#define AT91C_PMC_PCK ( ( unsigned int ) 0x1 << 0 ) /* (PMC) Processor Clock */ +#define AT91C_PMC_UDP ( ( unsigned int ) 0x1 << 7 ) /* (PMC) USB Device Port Clock */ +#define AT91C_PMC_PCK0 ( ( unsigned int ) 0x1 << 8 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK1 ( ( unsigned int ) 0x1 << 9 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK2 ( ( unsigned int ) 0x1 << 10 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK3 ( ( unsigned int ) 0x1 << 11 ) /* (PMC) Programmable Clock Output */ +/* -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- */ +/* -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- */ +/* -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- */ +/* -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- */ +/* -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- */ +/* -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */ +#define AT91C_PMC_CSS ( ( unsigned int ) 0x3 << 0 ) /* (PMC) Programmable Clock Selection */ +#define AT91C_PMC_CSS_SLOW_CLK ( ( unsigned int ) 0x0 ) /* (PMC) Slow Clock is selected */ +#define AT91C_PMC_CSS_MAIN_CLK ( ( unsigned int ) 0x1 ) /* (PMC) Main Clock is selected */ +#define AT91C_PMC_CSS_PLL_CLK ( ( unsigned int ) 0x3 ) /* (PMC) Clock from PLL is selected */ +#define AT91C_PMC_PRES ( ( unsigned int ) 0x7 << 2 ) /* (PMC) Programmable Clock Prescaler */ +#define AT91C_PMC_PRES_CLK ( ( unsigned int ) 0x0 << 2 ) /* (PMC) Selected clock */ +#define AT91C_PMC_PRES_CLK_2 ( ( unsigned int ) 0x1 << 2 ) /* (PMC) Selected clock divided by 2 */ +#define AT91C_PMC_PRES_CLK_4 ( ( unsigned int ) 0x2 << 2 ) /* (PMC) Selected clock divided by 4 */ +#define AT91C_PMC_PRES_CLK_8 ( ( unsigned int ) 0x3 << 2 ) /* (PMC) Selected clock divided by 8 */ +#define AT91C_PMC_PRES_CLK_16 ( ( unsigned int ) 0x4 << 2 ) /* (PMC) Selected clock divided by 16 */ +#define AT91C_PMC_PRES_CLK_32 ( ( unsigned int ) 0x5 << 2 ) /* (PMC) Selected clock divided by 32 */ +#define AT91C_PMC_PRES_CLK_64 ( ( unsigned int ) 0x6 << 2 ) /* (PMC) Selected clock divided by 64 */ +/* -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- */ +/* -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- */ +#define AT91C_PMC_MOSCS ( ( unsigned int ) 0x1 << 0 ) /* (PMC) MOSC Status/Enable/Disable/Mask */ +#define AT91C_PMC_LOCK ( ( unsigned int ) 0x1 << 2 ) /* (PMC) PLL Status/Enable/Disable/Mask */ +#define AT91C_PMC_MCKRDY ( ( unsigned int ) 0x1 << 3 ) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK0RDY ( ( unsigned int ) 0x1 << 8 ) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK1RDY ( ( unsigned int ) 0x1 << 9 ) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK2RDY ( ( unsigned int ) 0x1 << 10 ) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK3RDY ( ( unsigned int ) 0x1 << 11 ) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */ +/* -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */ +/* -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- */ +/* -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Reset Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_RSTC +{ + AT91_REG RSTC_RCR; /* Reset Control Register */ + AT91_REG RSTC_RSR; /* Reset Status Register */ + AT91_REG RSTC_RMR; /* Reset Mode Register */ +} AT91S_RSTC, * AT91PS_RSTC; + +/* -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- */ +#define AT91C_RSTC_PROCRST ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) Processor Reset */ +#define AT91C_RSTC_PERRST ( ( unsigned int ) 0x1 << 2 ) /* (RSTC) Peripheral Reset */ +#define AT91C_RSTC_EXTRST ( ( unsigned int ) 0x1 << 3 ) /* (RSTC) External Reset */ +#define AT91C_RSTC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (RSTC) Password */ +/* -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- */ +#define AT91C_RSTC_URSTS ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) User Reset Status */ +#define AT91C_RSTC_BODSTS ( ( unsigned int ) 0x1 << 1 ) /* (RSTC) Brownout Detection Status */ +#define AT91C_RSTC_RSTTYP ( ( unsigned int ) 0x7 << 8 ) /* (RSTC) Reset Type */ +#define AT91C_RSTC_RSTTYP_POWERUP ( ( unsigned int ) 0x0 << 8 ) /* (RSTC) Power-up Reset. VDDCORE rising. */ +#define AT91C_RSTC_RSTTYP_WAKEUP ( ( unsigned int ) 0x1 << 8 ) /* (RSTC) WakeUp Reset. VDDCORE rising. */ +#define AT91C_RSTC_RSTTYP_WATCHDOG ( ( unsigned int ) 0x2 << 8 ) /* (RSTC) Watchdog Reset. Watchdog overflow occurred. */ +#define AT91C_RSTC_RSTTYP_SOFTWARE ( ( unsigned int ) 0x3 << 8 ) /* (RSTC) Software Reset. Processor reset required by the software. */ +#define AT91C_RSTC_RSTTYP_USER ( ( unsigned int ) 0x4 << 8 ) /* (RSTC) User Reset. NRST pin detected low. */ +#define AT91C_RSTC_RSTTYP_BROWNOUT ( ( unsigned int ) 0x5 << 8 ) /* (RSTC) Brownout Reset occurred. */ +#define AT91C_RSTC_NRSTL ( ( unsigned int ) 0x1 << 16 ) /* (RSTC) NRST pin level */ +#define AT91C_RSTC_SRCMP ( ( unsigned int ) 0x1 << 17 ) /* (RSTC) Software Reset Command in Progress. */ +/* -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- */ +#define AT91C_RSTC_URSTEN ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) User Reset Enable */ +#define AT91C_RSTC_URSTIEN ( ( unsigned int ) 0x1 << 4 ) /* (RSTC) User Reset Interrupt Enable */ +#define AT91C_RSTC_ERSTL ( ( unsigned int ) 0xF << 8 ) /* (RSTC) User Reset Enable */ +#define AT91C_RSTC_BODIEN ( ( unsigned int ) 0x1 << 16 ) /* (RSTC) Brownout Detection Interrupt Enable */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_RTTC +{ + AT91_REG RTTC_RTMR; /* Real-time Mode Register */ + AT91_REG RTTC_RTAR; /* Real-time Alarm Register */ + AT91_REG RTTC_RTVR; /* Real-time Value Register */ + AT91_REG RTTC_RTSR; /* Real-time Status Register */ +} AT91S_RTTC, * AT91PS_RTTC; + +/* -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- */ +#define AT91C_RTTC_RTPRES ( ( unsigned int ) 0xFFFF << 0 ) /* (RTTC) Real-time Timer Prescaler Value */ +#define AT91C_RTTC_ALMIEN ( ( unsigned int ) 0x1 << 16 ) /* (RTTC) Alarm Interrupt Enable */ +#define AT91C_RTTC_RTTINCIEN ( ( unsigned int ) 0x1 << 17 ) /* (RTTC) Real Time Timer Increment Interrupt Enable */ +#define AT91C_RTTC_RTTRST ( ( unsigned int ) 0x1 << 18 ) /* (RTTC) Real Time Timer Restart */ +/* -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- */ +#define AT91C_RTTC_ALMV ( ( unsigned int ) 0x0 << 0 ) /* (RTTC) Alarm Value */ +/* -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- */ +#define AT91C_RTTC_CRTV ( ( unsigned int ) 0x0 << 0 ) /* (RTTC) Current Real-time Value */ +/* -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- */ +#define AT91C_RTTC_ALMS ( ( unsigned int ) 0x1 << 0 ) /* (RTTC) Real-time Alarm Status */ +#define AT91C_RTTC_RTTINC ( ( unsigned int ) 0x1 << 1 ) /* (RTTC) Real-time Timer Increment */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_PITC +{ + AT91_REG PITC_PIMR; /* Period Interval Mode Register */ + AT91_REG PITC_PISR; /* Period Interval Status Register */ + AT91_REG PITC_PIVR; /* Period Interval Value Register */ + AT91_REG PITC_PIIR; /* Period Interval Image Register */ +} AT91S_PITC, * AT91PS_PITC; + +/* -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- */ +#define AT91C_PITC_PIV ( ( unsigned int ) 0xFFFFF << 0 ) /* (PITC) Periodic Interval Value */ +#define AT91C_PITC_PITEN ( ( unsigned int ) 0x1 << 24 ) /* (PITC) Periodic Interval Timer Enabled */ +#define AT91C_PITC_PITIEN ( ( unsigned int ) 0x1 << 25 ) /* (PITC) Periodic Interval Timer Interrupt Enable */ +/* -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- */ +#define AT91C_PITC_PITS ( ( unsigned int ) 0x1 << 0 ) /* (PITC) Periodic Interval Timer Status */ +/* -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- */ +#define AT91C_PITC_CPIV ( ( unsigned int ) 0xFFFFF << 0 ) /* (PITC) Current Periodic Interval Value */ +#define AT91C_PITC_PICNT ( ( unsigned int ) 0xFFF << 20 ) /* (PITC) Periodic Interval Counter */ +/* -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_WDTC +{ + AT91_REG WDTC_WDCR; /* Watchdog Control Register */ + AT91_REG WDTC_WDMR; /* Watchdog Mode Register */ + AT91_REG WDTC_WDSR; /* Watchdog Status Register */ +} AT91S_WDTC, * AT91PS_WDTC; + +/* -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- */ +#define AT91C_WDTC_WDRSTT ( ( unsigned int ) 0x1 << 0 ) /* (WDTC) Watchdog Restart */ +#define AT91C_WDTC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (WDTC) Watchdog KEY Password */ +/* -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */ +#define AT91C_WDTC_WDV ( ( unsigned int ) 0xFFF << 0 ) /* (WDTC) Watchdog Timer Restart */ +#define AT91C_WDTC_WDFIEN ( ( unsigned int ) 0x1 << 12 ) /* (WDTC) Watchdog Fault Interrupt Enable */ +#define AT91C_WDTC_WDRSTEN ( ( unsigned int ) 0x1 << 13 ) /* (WDTC) Watchdog Reset Enable */ +#define AT91C_WDTC_WDRPROC ( ( unsigned int ) 0x1 << 14 ) /* (WDTC) Watchdog Timer Restart */ +#define AT91C_WDTC_WDDIS ( ( unsigned int ) 0x1 << 15 ) /* (WDTC) Watchdog Disable */ +#define AT91C_WDTC_WDD ( ( unsigned int ) 0xFFF << 16 ) /* (WDTC) Watchdog Delta Value */ +#define AT91C_WDTC_WDDBGHLT ( ( unsigned int ) 0x1 << 28 ) /* (WDTC) Watchdog Debug Halt */ +#define AT91C_WDTC_WDIDLEHLT ( ( unsigned int ) 0x1 << 29 ) /* (WDTC) Watchdog Idle Halt */ +/* -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- */ +#define AT91C_WDTC_WDUNF ( ( unsigned int ) 0x1 << 0 ) /* (WDTC) Watchdog Underflow */ +#define AT91C_WDTC_WDERR ( ( unsigned int ) 0x1 << 1 ) /* (WDTC) Watchdog Error */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_VREG +{ + AT91_REG VREG_MR; /* Voltage Regulator Mode Register */ +} AT91S_VREG, * AT91PS_VREG; + +/* -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- */ +#define AT91C_VREG_PSTDBY ( ( unsigned int ) 0x1 << 0 ) /* (VREG) Voltage Regulator Power Standby Mode */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Memory Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_MC +{ + AT91_REG MC_RCR; /* MC Remap Control Register */ + AT91_REG MC_ASR; /* MC Abort Status Register */ + AT91_REG MC_AASR; /* MC Abort Address Status Register */ + AT91_REG Reserved0[ 21 ]; /* */ + AT91_REG MC_FMR; /* MC Flash Mode Register */ + AT91_REG MC_FCR; /* MC Flash Command Register */ + AT91_REG MC_FSR; /* MC Flash Status Register */ +} AT91S_MC, * AT91PS_MC; + +/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */ +#define AT91C_MC_RCB ( ( unsigned int ) 0x1 << 0 ) /* (MC) Remap Command Bit */ +/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */ +#define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Address Abort Status */ +#define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Address Abort Status */ +#define AT91C_MC_ABTSZ ( ( unsigned int ) 0x3 << 8 ) /* (MC) Abort Size Status */ +#define AT91C_MC_ABTSZ_BYTE ( ( unsigned int ) 0x0 << 8 ) /* (MC) Byte */ +#define AT91C_MC_ABTSZ_HWORD ( ( unsigned int ) 0x1 << 8 ) /* (MC) Half-word */ +#define AT91C_MC_ABTSZ_WORD ( ( unsigned int ) 0x2 << 8 ) /* (MC) Word */ +#define AT91C_MC_ABTTYP ( ( unsigned int ) 0x3 << 10 ) /* (MC) Abort Type Status */ +#define AT91C_MC_ABTTYP_DATAR ( ( unsigned int ) 0x0 << 10 ) /* (MC) Data Read */ +#define AT91C_MC_ABTTYP_DATAW ( ( unsigned int ) 0x1 << 10 ) /* (MC) Data Write */ +#define AT91C_MC_ABTTYP_FETCH ( ( unsigned int ) 0x2 << 10 ) /* (MC) Code Fetch */ +#define AT91C_MC_MST0 ( ( unsigned int ) 0x1 << 16 ) /* (MC) Master 0 Abort Source */ +#define AT91C_MC_MST1 ( ( unsigned int ) 0x1 << 17 ) /* (MC) Master 1 Abort Source */ +#define AT91C_MC_SVMST0 ( ( unsigned int ) 0x1 << 24 ) /* (MC) Saved Master 0 Abort Source */ +#define AT91C_MC_SVMST1 ( ( unsigned int ) 0x1 << 25 ) /* (MC) Saved Master 1 Abort Source */ +/* -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- */ +#define AT91C_MC_FRDY ( ( unsigned int ) 0x1 << 0 ) /* (MC) Flash Ready */ +#define AT91C_MC_LOCKE ( ( unsigned int ) 0x1 << 2 ) /* (MC) Lock Error */ +#define AT91C_MC_PROGE ( ( unsigned int ) 0x1 << 3 ) /* (MC) Programming Error */ +#define AT91C_MC_NEBP ( ( unsigned int ) 0x1 << 7 ) /* (MC) No Erase Before Programming */ +#define AT91C_MC_FWS ( ( unsigned int ) 0x3 << 8 ) /* (MC) Flash Wait State */ +#define AT91C_MC_FWS_0FWS ( ( unsigned int ) 0x0 << 8 ) /* (MC) 1 cycle for Read, 2 for Write operations */ +#define AT91C_MC_FWS_1FWS ( ( unsigned int ) 0x1 << 8 ) /* (MC) 2 cycles for Read, 3 for Write operations */ +#define AT91C_MC_FWS_2FWS ( ( unsigned int ) 0x2 << 8 ) /* (MC) 3 cycles for Read, 4 for Write operations */ +#define AT91C_MC_FWS_3FWS ( ( unsigned int ) 0x3 << 8 ) /* (MC) 4 cycles for Read, 4 for Write operations */ +#define AT91C_MC_FMCN ( ( unsigned int ) 0xFF << 16 ) /* (MC) Flash Microsecond Cycle Number */ +/* -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- */ +#define AT91C_MC_FCMD ( ( unsigned int ) 0xF << 0 ) /* (MC) Flash Command */ +#define AT91C_MC_FCMD_START_PROG ( ( unsigned int ) 0x1 ) /* (MC) Starts the programming of th epage specified by PAGEN. */ +#define AT91C_MC_FCMD_LOCK ( ( unsigned int ) 0x2 ) /* (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */ +#define AT91C_MC_FCMD_PROG_AND_LOCK ( ( unsigned int ) 0x3 ) /* (MC) The lock sequence automatically happens after the programming sequence is completed. */ +#define AT91C_MC_FCMD_UNLOCK ( ( unsigned int ) 0x4 ) /* (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */ +#define AT91C_MC_FCMD_ERASE_ALL ( ( unsigned int ) 0x8 ) /* (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. */ +#define AT91C_MC_FCMD_SET_GP_NVM ( ( unsigned int ) 0xB ) /* (MC) Set General Purpose NVM bits. */ +#define AT91C_MC_FCMD_CLR_GP_NVM ( ( unsigned int ) 0xD ) /* (MC) Clear General Purpose NVM bits. */ +#define AT91C_MC_FCMD_SET_SECURITY ( ( unsigned int ) 0xF ) /* (MC) Set Security Bit. */ +#define AT91C_MC_PAGEN ( ( unsigned int ) 0x3FF << 8 ) /* (MC) Page Number */ +#define AT91C_MC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (MC) Writing Protect Key */ +/* -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- */ +#define AT91C_MC_SECURITY ( ( unsigned int ) 0x1 << 4 ) /* (MC) Security Bit Status */ +#define AT91C_MC_GPNVM0 ( ( unsigned int ) 0x1 << 8 ) /* (MC) Sector 0 Lock Status */ +#define AT91C_MC_GPNVM1 ( ( unsigned int ) 0x1 << 9 ) /* (MC) Sector 1 Lock Status */ +#define AT91C_MC_GPNVM2 ( ( unsigned int ) 0x1 << 10 ) /* (MC) Sector 2 Lock Status */ +#define AT91C_MC_GPNVM3 ( ( unsigned int ) 0x1 << 11 ) /* (MC) Sector 3 Lock Status */ +#define AT91C_MC_GPNVM4 ( ( unsigned int ) 0x1 << 12 ) /* (MC) Sector 4 Lock Status */ +#define AT91C_MC_GPNVM5 ( ( unsigned int ) 0x1 << 13 ) /* (MC) Sector 5 Lock Status */ +#define AT91C_MC_GPNVM6 ( ( unsigned int ) 0x1 << 14 ) /* (MC) Sector 6 Lock Status */ +#define AT91C_MC_GPNVM7 ( ( unsigned int ) 0x1 << 15 ) /* (MC) Sector 7 Lock Status */ +#define AT91C_MC_LOCKS0 ( ( unsigned int ) 0x1 << 16 ) /* (MC) Sector 0 Lock Status */ +#define AT91C_MC_LOCKS1 ( ( unsigned int ) 0x1 << 17 ) /* (MC) Sector 1 Lock Status */ +#define AT91C_MC_LOCKS2 ( ( unsigned int ) 0x1 << 18 ) /* (MC) Sector 2 Lock Status */ +#define AT91C_MC_LOCKS3 ( ( unsigned int ) 0x1 << 19 ) /* (MC) Sector 3 Lock Status */ +#define AT91C_MC_LOCKS4 ( ( unsigned int ) 0x1 << 20 ) /* (MC) Sector 4 Lock Status */ +#define AT91C_MC_LOCKS5 ( ( unsigned int ) 0x1 << 21 ) /* (MC) Sector 5 Lock Status */ +#define AT91C_MC_LOCKS6 ( ( unsigned int ) 0x1 << 22 ) /* (MC) Sector 6 Lock Status */ +#define AT91C_MC_LOCKS7 ( ( unsigned int ) 0x1 << 23 ) /* (MC) Sector 7 Lock Status */ +#define AT91C_MC_LOCKS8 ( ( unsigned int ) 0x1 << 24 ) /* (MC) Sector 8 Lock Status */ +#define AT91C_MC_LOCKS9 ( ( unsigned int ) 0x1 << 25 ) /* (MC) Sector 9 Lock Status */ +#define AT91C_MC_LOCKS10 ( ( unsigned int ) 0x1 << 26 ) /* (MC) Sector 10 Lock Status */ +#define AT91C_MC_LOCKS11 ( ( unsigned int ) 0x1 << 27 ) /* (MC) Sector 11 Lock Status */ +#define AT91C_MC_LOCKS12 ( ( unsigned int ) 0x1 << 28 ) /* (MC) Sector 12 Lock Status */ +#define AT91C_MC_LOCKS13 ( ( unsigned int ) 0x1 << 29 ) /* (MC) Sector 13 Lock Status */ +#define AT91C_MC_LOCKS14 ( ( unsigned int ) 0x1 << 30 ) /* (MC) Sector 14 Lock Status */ +#define AT91C_MC_LOCKS15 ( ( unsigned int ) 0x1 << 31 ) /* (MC) Sector 15 Lock Status */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_SPI +{ + AT91_REG SPI_CR; /* Control Register */ + AT91_REG SPI_MR; /* Mode Register */ + AT91_REG SPI_RDR; /* Receive Data Register */ + AT91_REG SPI_TDR; /* Transmit Data Register */ + AT91_REG SPI_SR; /* Status Register */ + AT91_REG SPI_IER; /* Interrupt Enable Register */ + AT91_REG SPI_IDR; /* Interrupt Disable Register */ + AT91_REG SPI_IMR; /* Interrupt Mask Register */ + AT91_REG Reserved0[ 4 ]; /* */ + AT91_REG SPI_CSR[ 4 ]; /* Chip Select Register */ + AT91_REG Reserved1[ 48 ]; /* */ + AT91_REG SPI_RPR; /* Receive Pointer Register */ + AT91_REG SPI_RCR; /* Receive Counter Register */ + AT91_REG SPI_TPR; /* Transmit Pointer Register */ + AT91_REG SPI_TCR; /* Transmit Counter Register */ + AT91_REG SPI_RNPR; /* Receive Next Pointer Register */ + AT91_REG SPI_RNCR; /* Receive Next Counter Register */ + AT91_REG SPI_TNPR; /* Transmit Next Pointer Register */ + AT91_REG SPI_TNCR; /* Transmit Next Counter Register */ + AT91_REG SPI_PTCR; /* PDC Transfer Control Register */ + AT91_REG SPI_PTSR; /* PDC Transfer Status Register */ +} AT91S_SPI, * AT91PS_SPI; + +/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */ +#define AT91C_SPI_SPIEN ( ( unsigned int ) 0x1 << 0 ) /* (SPI) SPI Enable */ +#define AT91C_SPI_SPIDIS ( ( unsigned int ) 0x1 << 1 ) /* (SPI) SPI Disable */ +#define AT91C_SPI_SWRST ( ( unsigned int ) 0x1 << 7 ) /* (SPI) SPI Software reset */ +#define AT91C_SPI_LASTXFER ( ( unsigned int ) 0x1 << 24 ) /* (SPI) SPI Last Transfer */ +/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */ +#define AT91C_SPI_MSTR ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Master/Slave Mode */ +#define AT91C_SPI_PS ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Peripheral Select */ +#define AT91C_SPI_PS_FIXED ( ( unsigned int ) 0x0 << 1 ) /* (SPI) Fixed Peripheral Select */ +#define AT91C_SPI_PS_VARIABLE ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Variable Peripheral Select */ +#define AT91C_SPI_PCSDEC ( ( unsigned int ) 0x1 << 2 ) /* (SPI) Chip Select Decode */ +#define AT91C_SPI_FDIV ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Clock Selection */ +#define AT91C_SPI_MODFDIS ( ( unsigned int ) 0x1 << 4 ) /* (SPI) Mode Fault Detection */ +#define AT91C_SPI_LLB ( ( unsigned int ) 0x1 << 7 ) /* (SPI) Clock Selection */ +#define AT91C_SPI_PCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select */ +#define AT91C_SPI_DLYBCS ( ( unsigned int ) 0xFF << 24 ) /* (SPI) Delay Between Chip Selects */ +/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */ +#define AT91C_SPI_RD ( ( unsigned int ) 0xFFFF << 0 ) /* (SPI) Receive Data */ +#define AT91C_SPI_RPCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */ +/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */ +#define AT91C_SPI_TD ( ( unsigned int ) 0xFFFF << 0 ) /* (SPI) Transmit Data */ +#define AT91C_SPI_TPCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */ +/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ +#define AT91C_SPI_RDRF ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Receive Data Register Full */ +#define AT91C_SPI_TDRE ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Transmit Data Register Empty */ +#define AT91C_SPI_MODF ( ( unsigned int ) 0x1 << 2 ) /* (SPI) Mode Fault Error */ +#define AT91C_SPI_OVRES ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Overrun Error Status */ +#define AT91C_SPI_ENDRX ( ( unsigned int ) 0x1 << 4 ) /* (SPI) End of Receiver Transfer */ +#define AT91C_SPI_ENDTX ( ( unsigned int ) 0x1 << 5 ) /* (SPI) End of Receiver Transfer */ +#define AT91C_SPI_RXBUFF ( ( unsigned int ) 0x1 << 6 ) /* (SPI) RXBUFF Interrupt */ +#define AT91C_SPI_TXBUFE ( ( unsigned int ) 0x1 << 7 ) /* (SPI) TXBUFE Interrupt */ +#define AT91C_SPI_NSSR ( ( unsigned int ) 0x1 << 8 ) /* (SPI) NSSR Interrupt */ +#define AT91C_SPI_TXEMPTY ( ( unsigned int ) 0x1 << 9 ) /* (SPI) TXEMPTY Interrupt */ +#define AT91C_SPI_SPIENS ( ( unsigned int ) 0x1 << 16 ) /* (SPI) Enable Status */ +/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ +/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ +/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */ +/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */ +#define AT91C_SPI_CPOL ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Clock Polarity */ +#define AT91C_SPI_NCPHA ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Clock Phase */ +#define AT91C_SPI_CSAAT ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Chip Select Active After Transfer */ +#define AT91C_SPI_BITS ( ( unsigned int ) 0xF << 4 ) /* (SPI) Bits Per Transfer */ +#define AT91C_SPI_BITS_8 ( ( unsigned int ) 0x0 << 4 ) /* (SPI) 8 Bits Per transfer */ +#define AT91C_SPI_BITS_9 ( ( unsigned int ) 0x1 << 4 ) /* (SPI) 9 Bits Per transfer */ +#define AT91C_SPI_BITS_10 ( ( unsigned int ) 0x2 << 4 ) /* (SPI) 10 Bits Per transfer */ +#define AT91C_SPI_BITS_11 ( ( unsigned int ) 0x3 << 4 ) /* (SPI) 11 Bits Per transfer */ +#define AT91C_SPI_BITS_12 ( ( unsigned int ) 0x4 << 4 ) /* (SPI) 12 Bits Per transfer */ +#define AT91C_SPI_BITS_13 ( ( unsigned int ) 0x5 << 4 ) /* (SPI) 13 Bits Per transfer */ +#define AT91C_SPI_BITS_14 ( ( unsigned int ) 0x6 << 4 ) /* (SPI) 14 Bits Per transfer */ +#define AT91C_SPI_BITS_15 ( ( unsigned int ) 0x7 << 4 ) /* (SPI) 15 Bits Per transfer */ +#define AT91C_SPI_BITS_16 ( ( unsigned int ) 0x8 << 4 ) /* (SPI) 16 Bits Per transfer */ +#define AT91C_SPI_SCBR ( ( unsigned int ) 0xFF << 8 ) /* (SPI) Serial Clock Baud Rate */ +#define AT91C_SPI_DLYBS ( ( unsigned int ) 0xFF << 16 ) /* (SPI) Delay Before SPCK */ +#define AT91C_SPI_DLYBCT ( ( unsigned int ) 0xFF << 24 ) /* (SPI) Delay Between Consecutive Transfers */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Usart */ +/* ***************************************************************************** */ +typedef struct _AT91S_USART +{ + AT91_REG US_CR; /* Control Register */ + AT91_REG US_MR; /* Mode Register */ + AT91_REG US_IER; /* Interrupt Enable Register */ + AT91_REG US_IDR; /* Interrupt Disable Register */ + AT91_REG US_IMR; /* Interrupt Mask Register */ + AT91_REG US_CSR; /* Channel Status Register */ + AT91_REG US_RHR; /* Receiver Holding Register */ + AT91_REG US_THR; /* Transmitter Holding Register */ + AT91_REG US_BRGR; /* Baud Rate Generator Register */ + AT91_REG US_RTOR; /* Receiver Time-out Register */ + AT91_REG US_TTGR; /* Transmitter Time-guard Register */ + AT91_REG Reserved0[ 5 ]; /* */ + AT91_REG US_FIDI; /* FI_DI_Ratio Register */ + AT91_REG US_NER; /* Nb Errors Register */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG US_IF; /* IRDA_FILTER Register */ + AT91_REG Reserved2[ 44 ]; /* */ + AT91_REG US_RPR; /* Receive Pointer Register */ + AT91_REG US_RCR; /* Receive Counter Register */ + AT91_REG US_TPR; /* Transmit Pointer Register */ + AT91_REG US_TCR; /* Transmit Counter Register */ + AT91_REG US_RNPR; /* Receive Next Pointer Register */ + AT91_REG US_RNCR; /* Receive Next Counter Register */ + AT91_REG US_TNPR; /* Transmit Next Pointer Register */ + AT91_REG US_TNCR; /* Transmit Next Counter Register */ + AT91_REG US_PTCR; /* PDC Transfer Control Register */ + AT91_REG US_PTSR; /* PDC Transfer Status Register */ +} AT91S_USART, * AT91PS_USART; + +/* -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- */ +#define AT91C_US_STTBRK ( ( unsigned int ) 0x1 << 9 ) /* (USART) Start Break */ +#define AT91C_US_STPBRK ( ( unsigned int ) 0x1 << 10 ) /* (USART) Stop Break */ +#define AT91C_US_STTTO ( ( unsigned int ) 0x1 << 11 ) /* (USART) Start Time-out */ +#define AT91C_US_SENDA ( ( unsigned int ) 0x1 << 12 ) /* (USART) Send Address */ +#define AT91C_US_RSTIT ( ( unsigned int ) 0x1 << 13 ) /* (USART) Reset Iterations */ +#define AT91C_US_RSTNACK ( ( unsigned int ) 0x1 << 14 ) /* (USART) Reset Non Acknowledge */ +#define AT91C_US_RETTO ( ( unsigned int ) 0x1 << 15 ) /* (USART) Rearm Time-out */ +#define AT91C_US_DTREN ( ( unsigned int ) 0x1 << 16 ) /* (USART) Data Terminal ready Enable */ +#define AT91C_US_DTRDIS ( ( unsigned int ) 0x1 << 17 ) /* (USART) Data Terminal ready Disable */ +#define AT91C_US_RTSEN ( ( unsigned int ) 0x1 << 18 ) /* (USART) Request to Send enable */ +#define AT91C_US_RTSDIS ( ( unsigned int ) 0x1 << 19 ) /* (USART) Request to Send Disable */ +/* -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- */ +#define AT91C_US_USMODE ( ( unsigned int ) 0xF << 0 ) /* (USART) Usart mode */ +#define AT91C_US_USMODE_NORMAL ( ( unsigned int ) 0x0 ) /* (USART) Normal */ +#define AT91C_US_USMODE_RS485 ( ( unsigned int ) 0x1 ) /* (USART) RS485 */ +#define AT91C_US_USMODE_HWHSH ( ( unsigned int ) 0x2 ) /* (USART) Hardware Handshaking */ +#define AT91C_US_USMODE_MODEM ( ( unsigned int ) 0x3 ) /* (USART) Modem */ +#define AT91C_US_USMODE_ISO7816_0 ( ( unsigned int ) 0x4 ) /* (USART) ISO7816 protocol: T = 0 */ +#define AT91C_US_USMODE_ISO7816_1 ( ( unsigned int ) 0x6 ) /* (USART) ISO7816 protocol: T = 1 */ +#define AT91C_US_USMODE_IRDA ( ( unsigned int ) 0x8 ) /* (USART) IrDA */ +#define AT91C_US_USMODE_SWHSH ( ( unsigned int ) 0xC ) /* (USART) Software Handshaking */ +#define AT91C_US_CLKS ( ( unsigned int ) 0x3 << 4 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */ +#define AT91C_US_CLKS_CLOCK ( ( unsigned int ) 0x0 << 4 ) /* (USART) Clock */ +#define AT91C_US_CLKS_FDIV1 ( ( unsigned int ) 0x1 << 4 ) /* (USART) fdiv1 */ +#define AT91C_US_CLKS_SLOW ( ( unsigned int ) 0x2 << 4 ) /* (USART) slow_clock (ARM) */ +#define AT91C_US_CLKS_EXT ( ( unsigned int ) 0x3 << 4 ) /* (USART) External (SCK) */ +#define AT91C_US_CHRL ( ( unsigned int ) 0x3 << 6 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */ +#define AT91C_US_CHRL_5_BITS ( ( unsigned int ) 0x0 << 6 ) /* (USART) Character Length: 5 bits */ +#define AT91C_US_CHRL_6_BITS ( ( unsigned int ) 0x1 << 6 ) /* (USART) Character Length: 6 bits */ +#define AT91C_US_CHRL_7_BITS ( ( unsigned int ) 0x2 << 6 ) /* (USART) Character Length: 7 bits */ +#define AT91C_US_CHRL_8_BITS ( ( unsigned int ) 0x3 << 6 ) /* (USART) Character Length: 8 bits */ +#define AT91C_US_SYNC ( ( unsigned int ) 0x1 << 8 ) /* (USART) Synchronous Mode Select */ +#define AT91C_US_NBSTOP ( ( unsigned int ) 0x3 << 12 ) /* (USART) Number of Stop bits */ +#define AT91C_US_NBSTOP_1_BIT ( ( unsigned int ) 0x0 << 12 ) /* (USART) 1 stop bit */ +#define AT91C_US_NBSTOP_15_BIT ( ( unsigned int ) 0x1 << 12 ) /* (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */ +#define AT91C_US_NBSTOP_2_BIT ( ( unsigned int ) 0x2 << 12 ) /* (USART) 2 stop bits */ +#define AT91C_US_MSBF ( ( unsigned int ) 0x1 << 16 ) /* (USART) Bit Order */ +#define AT91C_US_MODE9 ( ( unsigned int ) 0x1 << 17 ) /* (USART) 9-bit Character length */ +#define AT91C_US_CKLO ( ( unsigned int ) 0x1 << 18 ) /* (USART) Clock Output Select */ +#define AT91C_US_OVER ( ( unsigned int ) 0x1 << 19 ) /* (USART) Over Sampling Mode */ +#define AT91C_US_INACK ( ( unsigned int ) 0x1 << 20 ) /* (USART) Inhibit Non Acknowledge */ +#define AT91C_US_DSNACK ( ( unsigned int ) 0x1 << 21 ) /* (USART) Disable Successive NACK */ +#define AT91C_US_MAX_ITER ( ( unsigned int ) 0x1 << 24 ) /* (USART) Number of Repetitions */ +#define AT91C_US_FILTER ( ( unsigned int ) 0x1 << 28 ) /* (USART) Receive Line Filter */ +/* -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ +#define AT91C_US_RXBRK ( ( unsigned int ) 0x1 << 2 ) /* (USART) Break Received/End of Break */ +#define AT91C_US_TIMEOUT ( ( unsigned int ) 0x1 << 8 ) /* (USART) Receiver Time-out */ +#define AT91C_US_ITERATION ( ( unsigned int ) 0x1 << 10 ) /* (USART) Max number of Repetitions Reached */ +#define AT91C_US_NACK ( ( unsigned int ) 0x1 << 13 ) /* (USART) Non Acknowledge */ +#define AT91C_US_RIIC ( ( unsigned int ) 0x1 << 16 ) /* (USART) Ring INdicator Input Change Flag */ +#define AT91C_US_DSRIC ( ( unsigned int ) 0x1 << 17 ) /* (USART) Data Set Ready Input Change Flag */ +#define AT91C_US_DCDIC ( ( unsigned int ) 0x1 << 18 ) /* (USART) Data Carrier Flag */ +#define AT91C_US_CTSIC ( ( unsigned int ) 0x1 << 19 ) /* (USART) Clear To Send Input Change Flag */ +/* -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- */ +/* -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- */ +/* -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- */ +#define AT91C_US_RI ( ( unsigned int ) 0x1 << 20 ) /* (USART) Image of RI Input */ +#define AT91C_US_DSR ( ( unsigned int ) 0x1 << 21 ) /* (USART) Image of DSR Input */ +#define AT91C_US_DCD ( ( unsigned int ) 0x1 << 22 ) /* (USART) Image of DCD Input */ +#define AT91C_US_CTS ( ( unsigned int ) 0x1 << 23 ) /* (USART) Image of CTS Input */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_SSC +{ + AT91_REG SSC_CR; /* Control Register */ + AT91_REG SSC_CMR; /* Clock Mode Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG SSC_RCMR; /* Receive Clock ModeRegister */ + AT91_REG SSC_RFMR; /* Receive Frame Mode Register */ + AT91_REG SSC_TCMR; /* Transmit Clock Mode Register */ + AT91_REG SSC_TFMR; /* Transmit Frame Mode Register */ + AT91_REG SSC_RHR; /* Receive Holding Register */ + AT91_REG SSC_THR; /* Transmit Holding Register */ + AT91_REG Reserved1[ 2 ]; /* */ + AT91_REG SSC_RSHR; /* Receive Sync Holding Register */ + AT91_REG SSC_TSHR; /* Transmit Sync Holding Register */ + AT91_REG Reserved2[ 2 ]; /* */ + AT91_REG SSC_SR; /* Status Register */ + AT91_REG SSC_IER; /* Interrupt Enable Register */ + AT91_REG SSC_IDR; /* Interrupt Disable Register */ + AT91_REG SSC_IMR; /* Interrupt Mask Register */ + AT91_REG Reserved3[ 44 ]; /* */ + AT91_REG SSC_RPR; /* Receive Pointer Register */ + AT91_REG SSC_RCR; /* Receive Counter Register */ + AT91_REG SSC_TPR; /* Transmit Pointer Register */ + AT91_REG SSC_TCR; /* Transmit Counter Register */ + AT91_REG SSC_RNPR; /* Receive Next Pointer Register */ + AT91_REG SSC_RNCR; /* Receive Next Counter Register */ + AT91_REG SSC_TNPR; /* Transmit Next Pointer Register */ + AT91_REG SSC_TNCR; /* Transmit Next Counter Register */ + AT91_REG SSC_PTCR; /* PDC Transfer Control Register */ + AT91_REG SSC_PTSR; /* PDC Transfer Status Register */ +} AT91S_SSC, * AT91PS_SSC; + +/* -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- */ +#define AT91C_SSC_RXEN ( ( unsigned int ) 0x1 << 0 ) /* (SSC) Receive Enable */ +#define AT91C_SSC_RXDIS ( ( unsigned int ) 0x1 << 1 ) /* (SSC) Receive Disable */ +#define AT91C_SSC_TXEN ( ( unsigned int ) 0x1 << 8 ) /* (SSC) Transmit Enable */ +#define AT91C_SSC_TXDIS ( ( unsigned int ) 0x1 << 9 ) /* (SSC) Transmit Disable */ +#define AT91C_SSC_SWRST ( ( unsigned int ) 0x1 << 15 ) /* (SSC) Software Reset */ +/* -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- */ +#define AT91C_SSC_CKS ( ( unsigned int ) 0x3 << 0 ) /* (SSC) Receive/Transmit Clock Selection */ +#define AT91C_SSC_CKS_DIV ( ( unsigned int ) 0x0 ) /* (SSC) Divided Clock */ +#define AT91C_SSC_CKS_TK ( ( unsigned int ) 0x1 ) /* (SSC) TK Clock signal */ +#define AT91C_SSC_CKS_RK ( ( unsigned int ) 0x2 ) /* (SSC) RK pin */ +#define AT91C_SSC_CKO ( ( unsigned int ) 0x7 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode Selection */ +#define AT91C_SSC_CKO_NONE ( ( unsigned int ) 0x0 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only */ +#define AT91C_SSC_CKO_CONTINUOUS ( ( unsigned int ) 0x1 << 2 ) /* (SSC) Continuous Receive/Transmit Clock RK pin: Output */ +#define AT91C_SSC_CKO_DATA_TX ( ( unsigned int ) 0x2 << 2 ) /* (SSC) Receive/Transmit Clock only during data transfers RK pin: Output */ +#define AT91C_SSC_CKI ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Receive/Transmit Clock Inversion */ +#define AT91C_SSC_START ( ( unsigned int ) 0xF << 8 ) /* (SSC) Receive/Transmit Start Selection */ +#define AT91C_SSC_START_CONTINUOUS ( ( unsigned int ) 0x0 << 8 ) /* (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */ +#define AT91C_SSC_START_TX ( ( unsigned int ) 0x1 << 8 ) /* (SSC) Transmit/Receive start */ +#define AT91C_SSC_START_LOW_RF ( ( unsigned int ) 0x2 << 8 ) /* (SSC) Detection of a low level on RF input */ +#define AT91C_SSC_START_HIGH_RF ( ( unsigned int ) 0x3 << 8 ) /* (SSC) Detection of a high level on RF input */ +#define AT91C_SSC_START_FALL_RF ( ( unsigned int ) 0x4 << 8 ) /* (SSC) Detection of a falling edge on RF input */ +#define AT91C_SSC_START_RISE_RF ( ( unsigned int ) 0x5 << 8 ) /* (SSC) Detection of a rising edge on RF input */ +#define AT91C_SSC_START_LEVEL_RF ( ( unsigned int ) 0x6 << 8 ) /* (SSC) Detection of any level change on RF input */ +#define AT91C_SSC_START_EDGE_RF ( ( unsigned int ) 0x7 << 8 ) /* (SSC) Detection of any edge on RF input */ +#define AT91C_SSC_START_0 ( ( unsigned int ) 0x8 << 8 ) /* (SSC) Compare 0 */ +#define AT91C_SSC_STTDLY ( ( unsigned int ) 0xFF << 16 ) /* (SSC) Receive/Transmit Start Delay */ +#define AT91C_SSC_PERIOD ( ( unsigned int ) 0xFF << 24 ) /* (SSC) Receive/Transmit Period Divider Selection */ +/* -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- */ +#define AT91C_SSC_DATLEN ( ( unsigned int ) 0x1F << 0 ) /* (SSC) Data Length */ +#define AT91C_SSC_LOOP ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Loop Mode */ +#define AT91C_SSC_MSBF ( ( unsigned int ) 0x1 << 7 ) /* (SSC) Most Significant Bit First */ +#define AT91C_SSC_DATNB ( ( unsigned int ) 0xF << 8 ) /* (SSC) Data Number per Frame */ +#define AT91C_SSC_FSLEN ( ( unsigned int ) 0xF << 16 ) /* (SSC) Receive/Transmit Frame Sync length */ +#define AT91C_SSC_FSOS ( ( unsigned int ) 0x7 << 20 ) /* (SSC) Receive/Transmit Frame Sync Output Selection */ +#define AT91C_SSC_FSOS_NONE ( ( unsigned int ) 0x0 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only */ +#define AT91C_SSC_FSOS_NEGATIVE ( ( unsigned int ) 0x1 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse */ +#define AT91C_SSC_FSOS_POSITIVE ( ( unsigned int ) 0x2 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse */ +#define AT91C_SSC_FSOS_LOW ( ( unsigned int ) 0x3 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer */ +#define AT91C_SSC_FSOS_HIGH ( ( unsigned int ) 0x4 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer */ +#define AT91C_SSC_FSOS_TOGGLE ( ( unsigned int ) 0x5 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer */ +#define AT91C_SSC_FSEDGE ( ( unsigned int ) 0x1 << 24 ) /* (SSC) Frame Sync Edge Detection */ +/* -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- */ +/* -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- */ +#define AT91C_SSC_DATDEF ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Data Default Value */ +#define AT91C_SSC_FSDEN ( ( unsigned int ) 0x1 << 23 ) /* (SSC) Frame Sync Data Enable */ +/* -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- */ +#define AT91C_SSC_TXRDY ( ( unsigned int ) 0x1 << 0 ) /* (SSC) Transmit Ready */ +#define AT91C_SSC_TXEMPTY ( ( unsigned int ) 0x1 << 1 ) /* (SSC) Transmit Empty */ +#define AT91C_SSC_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (SSC) End Of Transmission */ +#define AT91C_SSC_TXBUFE ( ( unsigned int ) 0x1 << 3 ) /* (SSC) Transmit Buffer Empty */ +#define AT91C_SSC_RXRDY ( ( unsigned int ) 0x1 << 4 ) /* (SSC) Receive Ready */ +#define AT91C_SSC_OVRUN ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Receive Overrun */ +#define AT91C_SSC_ENDRX ( ( unsigned int ) 0x1 << 6 ) /* (SSC) End of Reception */ +#define AT91C_SSC_RXBUFF ( ( unsigned int ) 0x1 << 7 ) /* (SSC) Receive Buffer Full */ +#define AT91C_SSC_TXSYN ( ( unsigned int ) 0x1 << 10 ) /* (SSC) Transmit Sync */ +#define AT91C_SSC_RXSYN ( ( unsigned int ) 0x1 << 11 ) /* (SSC) Receive Sync */ +#define AT91C_SSC_TXENA ( ( unsigned int ) 0x1 << 16 ) /* (SSC) Transmit Enable */ +#define AT91C_SSC_RXENA ( ( unsigned int ) 0x1 << 17 ) /* (SSC) Receive Enable */ +/* -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- */ +/* -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- */ +/* -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Two-wire Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_TWI +{ + AT91_REG TWI_CR; /* Control Register */ + AT91_REG TWI_MMR; /* Master Mode Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG TWI_IADR; /* Internal Address Register */ + AT91_REG TWI_CWGR; /* Clock Waveform Generator Register */ + AT91_REG Reserved1[ 3 ]; /* */ + AT91_REG TWI_SR; /* Status Register */ + AT91_REG TWI_IER; /* Interrupt Enable Register */ + AT91_REG TWI_IDR; /* Interrupt Disable Register */ + AT91_REG TWI_IMR; /* Interrupt Mask Register */ + AT91_REG TWI_RHR; /* Receive Holding Register */ + AT91_REG TWI_THR; /* Transmit Holding Register */ +} AT91S_TWI, * AT91PS_TWI; + +/* -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */ +#define AT91C_TWI_START ( ( unsigned int ) 0x1 << 0 ) /* (TWI) Send a START Condition */ +#define AT91C_TWI_STOP ( ( unsigned int ) 0x1 << 1 ) /* (TWI) Send a STOP Condition */ +#define AT91C_TWI_MSEN ( ( unsigned int ) 0x1 << 2 ) /* (TWI) TWI Master Transfer Enabled */ +#define AT91C_TWI_MSDIS ( ( unsigned int ) 0x1 << 3 ) /* (TWI) TWI Master Transfer Disabled */ +#define AT91C_TWI_SWRST ( ( unsigned int ) 0x1 << 7 ) /* (TWI) Software Reset */ +/* -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */ +#define AT91C_TWI_IADRSZ ( ( unsigned int ) 0x3 << 8 ) /* (TWI) Internal Device Address Size */ +#define AT91C_TWI_IADRSZ_NO ( ( unsigned int ) 0x0 << 8 ) /* (TWI) No internal device address */ +#define AT91C_TWI_IADRSZ_1_BYTE ( ( unsigned int ) 0x1 << 8 ) /* (TWI) One-byte internal device address */ +#define AT91C_TWI_IADRSZ_2_BYTE ( ( unsigned int ) 0x2 << 8 ) /* (TWI) Two-byte internal device address */ +#define AT91C_TWI_IADRSZ_3_BYTE ( ( unsigned int ) 0x3 << 8 ) /* (TWI) Three-byte internal device address */ +#define AT91C_TWI_MREAD ( ( unsigned int ) 0x1 << 12 ) /* (TWI) Master Read Direction */ +#define AT91C_TWI_DADR ( ( unsigned int ) 0x7F << 16 ) /* (TWI) Device Address */ +/* -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */ +#define AT91C_TWI_CLDIV ( ( unsigned int ) 0xFF << 0 ) /* (TWI) Clock Low Divider */ +#define AT91C_TWI_CHDIV ( ( unsigned int ) 0xFF << 8 ) /* (TWI) Clock High Divider */ +#define AT91C_TWI_CKDIV ( ( unsigned int ) 0x7 << 16 ) /* (TWI) Clock Divider */ +/* -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */ +#define AT91C_TWI_TXCOMP ( ( unsigned int ) 0x1 << 0 ) /* (TWI) Transmission Completed */ +#define AT91C_TWI_RXRDY ( ( unsigned int ) 0x1 << 1 ) /* (TWI) Receive holding register ReaDY */ +#define AT91C_TWI_TXRDY ( ( unsigned int ) 0x1 << 2 ) /* (TWI) Transmit holding register ReaDY */ +#define AT91C_TWI_OVRE ( ( unsigned int ) 0x1 << 6 ) /* (TWI) Overrun Error */ +#define AT91C_TWI_UNRE ( ( unsigned int ) 0x1 << 7 ) /* (TWI) Underrun Error */ +#define AT91C_TWI_NACK ( ( unsigned int ) 0x1 << 8 ) /* (TWI) Not Acknowledged */ +/* -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */ +/* -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- */ +/* -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR PWMC Channel Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_PWMC_CH +{ + AT91_REG PWMC_CMR; /* Channel Mode Register */ + AT91_REG PWMC_CDTYR; /* Channel Duty Cycle Register */ + AT91_REG PWMC_CPRDR; /* Channel Period Register */ + AT91_REG PWMC_CCNTR; /* Channel Counter Register */ + AT91_REG PWMC_CUPDR; /* Channel Update Register */ + AT91_REG PWMC_Reserved[ 3 ]; /* Reserved */ +} AT91S_PWMC_CH, * AT91PS_PWMC_CH; + +/* -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- */ +#define AT91C_PWMC_CPRE ( ( unsigned int ) 0xF << 0 ) /* (PWMC_CH) Channel Pre-scaler : PWMC_CLKx */ +#define AT91C_PWMC_CPRE_MCK ( ( unsigned int ) 0x0 ) /* (PWMC_CH) */ +#define AT91C_PWMC_CPRE_MCKA ( ( unsigned int ) 0xB ) /* (PWMC_CH) */ +#define AT91C_PWMC_CPRE_MCKB ( ( unsigned int ) 0xC ) /* (PWMC_CH) */ +#define AT91C_PWMC_CALG ( ( unsigned int ) 0x1 << 8 ) /* (PWMC_CH) Channel Alignment */ +#define AT91C_PWMC_CPOL ( ( unsigned int ) 0x1 << 9 ) /* (PWMC_CH) Channel Polarity */ +#define AT91C_PWMC_CPD ( ( unsigned int ) 0x1 << 10 ) /* (PWMC_CH) Channel Update Period */ +/* -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- */ +#define AT91C_PWMC_CDTY ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Duty Cycle */ +/* -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- */ +#define AT91C_PWMC_CPRD ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Period */ +/* -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- */ +#define AT91C_PWMC_CCNT ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Counter */ +/* -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- */ +#define AT91C_PWMC_CUPD ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Update */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_PWMC +{ + AT91_REG PWMC_MR; /* PWMC Mode Register */ + AT91_REG PWMC_ENA; /* PWMC Enable Register */ + AT91_REG PWMC_DIS; /* PWMC Disable Register */ + AT91_REG PWMC_SR; /* PWMC Status Register */ + AT91_REG PWMC_IER; /* PWMC Interrupt Enable Register */ + AT91_REG PWMC_IDR; /* PWMC Interrupt Disable Register */ + AT91_REG PWMC_IMR; /* PWMC Interrupt Mask Register */ + AT91_REG PWMC_ISR; /* PWMC Interrupt Status Register */ + AT91_REG Reserved0[ 55 ]; /* */ + AT91_REG PWMC_VR; /* PWMC Version Register */ + AT91_REG Reserved1[ 64 ]; /* */ + AT91S_PWMC_CH PWMC_CH[ 4 ]; /* PWMC Channel */ +} AT91S_PWMC, * AT91PS_PWMC; + +/* -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- */ +#define AT91C_PWMC_DIVA ( ( unsigned int ) 0xFF << 0 ) /* (PWMC) CLKA divide factor. */ +#define AT91C_PWMC_PREA ( ( unsigned int ) 0xF << 8 ) /* (PWMC) Divider Input Clock Prescaler A */ +#define AT91C_PWMC_PREA_MCK ( ( unsigned int ) 0x0 << 8 ) /* (PWMC) */ +#define AT91C_PWMC_DIVB ( ( unsigned int ) 0xFF << 16 ) /* (PWMC) CLKB divide factor. */ +#define AT91C_PWMC_PREB ( ( unsigned int ) 0xF << 24 ) /* (PWMC) Divider Input Clock Prescaler B */ +#define AT91C_PWMC_PREB_MCK ( ( unsigned int ) 0x0 << 24 ) /* (PWMC) */ +/* -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- */ +#define AT91C_PWMC_CHID0 ( ( unsigned int ) 0x1 << 0 ) /* (PWMC) Channel ID 0 */ +#define AT91C_PWMC_CHID1 ( ( unsigned int ) 0x1 << 1 ) /* (PWMC) Channel ID 1 */ +#define AT91C_PWMC_CHID2 ( ( unsigned int ) 0x1 << 2 ) /* (PWMC) Channel ID 2 */ +#define AT91C_PWMC_CHID3 ( ( unsigned int ) 0x1 << 3 ) /* (PWMC) Channel ID 3 */ +/* -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- */ +/* -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- */ +/* -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- */ +/* -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- */ +/* -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- */ +/* -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR USB Device Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_UDP +{ + AT91_REG UDP_NUM; /* Frame Number Register */ + AT91_REG UDP_GLBSTATE; /* Global State Register */ + AT91_REG UDP_FADDR; /* Function Address Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG UDP_IER; /* Interrupt Enable Register */ + AT91_REG UDP_IDR; /* Interrupt Disable Register */ + AT91_REG UDP_IMR; /* Interrupt Mask Register */ + AT91_REG UDP_ISR; /* Interrupt Status Register */ + AT91_REG UDP_ICR; /* Interrupt Clear Register */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG UDP_RSTEP; /* Reset Endpoint Register */ + AT91_REG Reserved2[ 1 ]; /* */ + AT91_REG UDP_CSR[ 6 ]; /* Endpoint Control and Status Register */ + AT91_REG Reserved3[ 2 ]; /* */ + AT91_REG UDP_FDR[ 6 ]; /* Endpoint FIFO Data Register */ + AT91_REG Reserved4[ 3 ]; /* */ + AT91_REG UDP_TXVC; /* Transceiver Control Register */ +} AT91S_UDP, * AT91PS_UDP; + +/* -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- */ +#define AT91C_UDP_FRM_NUM ( ( unsigned int ) 0x7FF << 0 ) /* (UDP) Frame Number as Defined in the Packet Field Formats */ +#define AT91C_UDP_FRM_ERR ( ( unsigned int ) 0x1 << 16 ) /* (UDP) Frame Error */ +#define AT91C_UDP_FRM_OK ( ( unsigned int ) 0x1 << 17 ) /* (UDP) Frame OK */ +/* -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- */ +#define AT91C_UDP_FADDEN ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Function Address Enable */ +#define AT91C_UDP_CONFG ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Configured */ +#define AT91C_UDP_ESR ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Enable Send Resume */ +#define AT91C_UDP_RSMINPR ( ( unsigned int ) 0x1 << 3 ) /* (UDP) A Resume Has Been Sent to the Host */ +#define AT91C_UDP_RMWUPE ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Remote Wake Up Enable */ +/* -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- */ +#define AT91C_UDP_FADD ( ( unsigned int ) 0xFF << 0 ) /* (UDP) Function Address Value */ +#define AT91C_UDP_FEN ( ( unsigned int ) 0x1 << 8 ) /* (UDP) Function Enable */ +/* -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- */ +#define AT91C_UDP_EPINT0 ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Endpoint 0 Interrupt */ +#define AT91C_UDP_EPINT1 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Endpoint 0 Interrupt */ +#define AT91C_UDP_EPINT2 ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Endpoint 2 Interrupt */ +#define AT91C_UDP_EPINT3 ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Endpoint 3 Interrupt */ +#define AT91C_UDP_EPINT4 ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Endpoint 4 Interrupt */ +#define AT91C_UDP_EPINT5 ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Endpoint 5 Interrupt */ +#define AT91C_UDP_RXSUSP ( ( unsigned int ) 0x1 << 8 ) /* (UDP) USB Suspend Interrupt */ +#define AT91C_UDP_RXRSM ( ( unsigned int ) 0x1 << 9 ) /* (UDP) USB Resume Interrupt */ +#define AT91C_UDP_EXTRSM ( ( unsigned int ) 0x1 << 10 ) /* (UDP) USB External Resume Interrupt */ +#define AT91C_UDP_SOFINT ( ( unsigned int ) 0x1 << 11 ) /* (UDP) USB Start Of frame Interrupt */ +#define AT91C_UDP_WAKEUP ( ( unsigned int ) 0x1 << 13 ) /* (UDP) USB Resume Interrupt */ +/* -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- */ +/* -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- */ +/* -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- */ +#define AT91C_UDP_ENDBUSRES ( ( unsigned int ) 0x1 << 12 ) /* (UDP) USB End Of Bus Reset Interrupt */ +/* -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- */ +/* -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- */ +#define AT91C_UDP_EP0 ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Reset Endpoint 0 */ +#define AT91C_UDP_EP1 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Reset Endpoint 1 */ +#define AT91C_UDP_EP2 ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Reset Endpoint 2 */ +#define AT91C_UDP_EP3 ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Reset Endpoint 3 */ +#define AT91C_UDP_EP4 ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Reset Endpoint 4 */ +#define AT91C_UDP_EP5 ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Reset Endpoint 5 */ +/* -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- */ +#define AT91C_UDP_TXCOMP ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Generates an IN packet with data previously written in the DPR */ +#define AT91C_UDP_RX_DATA_BK0 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Receive Data Bank 0 */ +#define AT91C_UDP_RXSETUP ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Sends STALL to the Host (Control endpoints) */ +#define AT91C_UDP_ISOERROR ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Isochronous error (Isochronous endpoints) */ +#define AT91C_UDP_TXPKTRDY ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Transmit Packet Ready */ +#define AT91C_UDP_FORCESTALL ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). */ +#define AT91C_UDP_RX_DATA_BK1 ( ( unsigned int ) 0x1 << 6 ) /* (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). */ +#define AT91C_UDP_DIR ( ( unsigned int ) 0x1 << 7 ) /* (UDP) Transfer Direction */ +#define AT91C_UDP_EPTYPE ( ( unsigned int ) 0x7 << 8 ) /* (UDP) Endpoint type */ +#define AT91C_UDP_EPTYPE_CTRL ( ( unsigned int ) 0x0 << 8 ) /* (UDP) Control */ +#define AT91C_UDP_EPTYPE_ISO_OUT ( ( unsigned int ) 0x1 << 8 ) /* (UDP) Isochronous OUT */ +#define AT91C_UDP_EPTYPE_BULK_OUT ( ( unsigned int ) 0x2 << 8 ) /* (UDP) Bulk OUT */ +#define AT91C_UDP_EPTYPE_INT_OUT ( ( unsigned int ) 0x3 << 8 ) /* (UDP) Interrupt OUT */ +#define AT91C_UDP_EPTYPE_ISO_IN ( ( unsigned int ) 0x5 << 8 ) /* (UDP) Isochronous IN */ +#define AT91C_UDP_EPTYPE_BULK_IN ( ( unsigned int ) 0x6 << 8 ) /* (UDP) Bulk IN */ +#define AT91C_UDP_EPTYPE_INT_IN ( ( unsigned int ) 0x7 << 8 ) /* (UDP) Interrupt IN */ +#define AT91C_UDP_DTGLE ( ( unsigned int ) 0x1 << 11 ) /* (UDP) Data Toggle */ +#define AT91C_UDP_EPEDS ( ( unsigned int ) 0x1 << 15 ) /* (UDP) Endpoint Enable Disable */ +#define AT91C_UDP_RXBYTECNT ( ( unsigned int ) 0x7FF << 16 ) /* (UDP) Number Of Bytes Available in the FIFO */ +/* -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- */ +#define AT91C_UDP_TXVDIS ( ( unsigned int ) 0x1 << 8 ) /* (UDP) */ +#define AT91C_UDP_PUON ( ( unsigned int ) 0x1 << 9 ) /* (UDP) Pull-up ON */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_TC +{ + AT91_REG TC_CCR; /* Channel Control Register */ + AT91_REG TC_CMR; /* Channel Mode Register (Capture Mode / Waveform Mode) */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG TC_CV; /* Counter Value */ + AT91_REG TC_RA; /* Register A */ + AT91_REG TC_RB; /* Register B */ + AT91_REG TC_RC; /* Register C */ + AT91_REG TC_SR; /* Status Register */ + AT91_REG TC_IER; /* Interrupt Enable Register */ + AT91_REG TC_IDR; /* Interrupt Disable Register */ + AT91_REG TC_IMR; /* Interrupt Mask Register */ +} AT91S_TC, * AT91PS_TC; + +/* -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- */ +#define AT91C_TC_CLKEN ( ( unsigned int ) 0x1 << 0 ) /* (TC) Counter Clock Enable Command */ +#define AT91C_TC_CLKDIS ( ( unsigned int ) 0x1 << 1 ) /* (TC) Counter Clock Disable Command */ +#define AT91C_TC_SWTRG ( ( unsigned int ) 0x1 << 2 ) /* (TC) Software Trigger Command */ +/* -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- */ +#define AT91C_TC_CLKS ( ( unsigned int ) 0x7 << 0 ) /* (TC) Clock Selection */ +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ( ( unsigned int ) 0x0 ) /* (TC) Clock selected: TIMER_DIV1_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ( ( unsigned int ) 0x1 ) /* (TC) Clock selected: TIMER_DIV2_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ( ( unsigned int ) 0x2 ) /* (TC) Clock selected: TIMER_DIV3_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ( ( unsigned int ) 0x3 ) /* (TC) Clock selected: TIMER_DIV4_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ( ( unsigned int ) 0x4 ) /* (TC) Clock selected: TIMER_DIV5_CLOCK */ +#define AT91C_TC_CLKS_XC0 ( ( unsigned int ) 0x5 ) /* (TC) Clock selected: XC0 */ +#define AT91C_TC_CLKS_XC1 ( ( unsigned int ) 0x6 ) /* (TC) Clock selected: XC1 */ +#define AT91C_TC_CLKS_XC2 ( ( unsigned int ) 0x7 ) /* (TC) Clock selected: XC2 */ +#define AT91C_TC_CLKI ( ( unsigned int ) 0x1 << 3 ) /* (TC) Clock Invert */ +#define AT91C_TC_BURST ( ( unsigned int ) 0x3 << 4 ) /* (TC) Burst Signal Selection */ +#define AT91C_TC_BURST_NONE ( ( unsigned int ) 0x0 << 4 ) /* (TC) The clock is not gated by an external signal */ +#define AT91C_TC_BURST_XC0 ( ( unsigned int ) 0x1 << 4 ) /* (TC) XC0 is ANDed with the selected clock */ +#define AT91C_TC_BURST_XC1 ( ( unsigned int ) 0x2 << 4 ) /* (TC) XC1 is ANDed with the selected clock */ +#define AT91C_TC_BURST_XC2 ( ( unsigned int ) 0x3 << 4 ) /* (TC) XC2 is ANDed with the selected clock */ +#define AT91C_TC_CPCSTOP ( ( unsigned int ) 0x1 << 6 ) /* (TC) Counter Clock Stopped with RC Compare */ +#define AT91C_TC_LDBSTOP ( ( unsigned int ) 0x1 << 6 ) /* (TC) Counter Clock Stopped with RB Loading */ +#define AT91C_TC_CPCDIS ( ( unsigned int ) 0x1 << 7 ) /* (TC) Counter Clock Disable with RC Compare */ +#define AT91C_TC_LDBDIS ( ( unsigned int ) 0x1 << 7 ) /* (TC) Counter Clock Disabled with RB Loading */ +#define AT91C_TC_ETRGEDG ( ( unsigned int ) 0x3 << 8 ) /* (TC) External Trigger Edge Selection */ +#define AT91C_TC_ETRGEDG_NONE ( ( unsigned int ) 0x0 << 8 ) /* (TC) Edge: None */ +#define AT91C_TC_ETRGEDG_RISING ( ( unsigned int ) 0x1 << 8 ) /* (TC) Edge: rising edge */ +#define AT91C_TC_ETRGEDG_FALLING ( ( unsigned int ) 0x2 << 8 ) /* (TC) Edge: falling edge */ +#define AT91C_TC_ETRGEDG_BOTH ( ( unsigned int ) 0x3 << 8 ) /* (TC) Edge: each edge */ +#define AT91C_TC_EEVTEDG ( ( unsigned int ) 0x3 << 8 ) /* (TC) External Event Edge Selection */ +#define AT91C_TC_EEVTEDG_NONE ( ( unsigned int ) 0x0 << 8 ) /* (TC) Edge: None */ +#define AT91C_TC_EEVTEDG_RISING ( ( unsigned int ) 0x1 << 8 ) /* (TC) Edge: rising edge */ +#define AT91C_TC_EEVTEDG_FALLING ( ( unsigned int ) 0x2 << 8 ) /* (TC) Edge: falling edge */ +#define AT91C_TC_EEVTEDG_BOTH ( ( unsigned int ) 0x3 << 8 ) /* (TC) Edge: each edge */ +#define AT91C_TC_EEVT ( ( unsigned int ) 0x3 << 10 ) /* (TC) External Event Selection */ +#define AT91C_TC_EEVT_TIOB ( ( unsigned int ) 0x0 << 10 ) /* (TC) Signal selected as external event: TIOB TIOB direction: input */ +#define AT91C_TC_EEVT_XC0 ( ( unsigned int ) 0x1 << 10 ) /* (TC) Signal selected as external event: XC0 TIOB direction: output */ +#define AT91C_TC_EEVT_XC1 ( ( unsigned int ) 0x2 << 10 ) /* (TC) Signal selected as external event: XC1 TIOB direction: output */ +#define AT91C_TC_EEVT_XC2 ( ( unsigned int ) 0x3 << 10 ) /* (TC) Signal selected as external event: XC2 TIOB direction: output */ +#define AT91C_TC_ABETRG ( ( unsigned int ) 0x1 << 10 ) /* (TC) TIOA or TIOB External Trigger Selection */ +#define AT91C_TC_ENETRG ( ( unsigned int ) 0x1 << 12 ) /* (TC) External Event Trigger enable */ +#define AT91C_TC_WAVESEL ( ( unsigned int ) 0x3 << 13 ) /* (TC) Waveform Selection */ +#define AT91C_TC_WAVESEL_UP ( ( unsigned int ) 0x0 << 13 ) /* (TC) UP mode without atomatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UPDOWN ( ( unsigned int ) 0x1 << 13 ) /* (TC) UPDOWN mode without automatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UP_AUTO ( ( unsigned int ) 0x2 << 13 ) /* (TC) UP mode with automatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UPDOWN_AUTO ( ( unsigned int ) 0x3 << 13 ) /* (TC) UPDOWN mode with automatic trigger on RC Compare */ +#define AT91C_TC_CPCTRG ( ( unsigned int ) 0x1 << 14 ) /* (TC) RC Compare Trigger Enable */ +#define AT91C_TC_WAVE ( ( unsigned int ) 0x1 << 15 ) /* (TC) */ +#define AT91C_TC_ACPA ( ( unsigned int ) 0x3 << 16 ) /* (TC) RA Compare Effect on TIOA */ +#define AT91C_TC_ACPA_NONE ( ( unsigned int ) 0x0 << 16 ) /* (TC) Effect: none */ +#define AT91C_TC_ACPA_SET ( ( unsigned int ) 0x1 << 16 ) /* (TC) Effect: set */ +#define AT91C_TC_ACPA_CLEAR ( ( unsigned int ) 0x2 << 16 ) /* (TC) Effect: clear */ +#define AT91C_TC_ACPA_TOGGLE ( ( unsigned int ) 0x3 << 16 ) /* (TC) Effect: toggle */ +#define AT91C_TC_LDRA ( ( unsigned int ) 0x3 << 16 ) /* (TC) RA Loading Selection */ +#define AT91C_TC_LDRA_NONE ( ( unsigned int ) 0x0 << 16 ) /* (TC) Edge: None */ +#define AT91C_TC_LDRA_RISING ( ( unsigned int ) 0x1 << 16 ) /* (TC) Edge: rising edge of TIOA */ +#define AT91C_TC_LDRA_FALLING ( ( unsigned int ) 0x2 << 16 ) /* (TC) Edge: falling edge of TIOA */ +#define AT91C_TC_LDRA_BOTH ( ( unsigned int ) 0x3 << 16 ) /* (TC) Edge: each edge of TIOA */ +#define AT91C_TC_ACPC ( ( unsigned int ) 0x3 << 18 ) /* (TC) RC Compare Effect on TIOA */ +#define AT91C_TC_ACPC_NONE ( ( unsigned int ) 0x0 << 18 ) /* (TC) Effect: none */ +#define AT91C_TC_ACPC_SET ( ( unsigned int ) 0x1 << 18 ) /* (TC) Effect: set */ +#define AT91C_TC_ACPC_CLEAR ( ( unsigned int ) 0x2 << 18 ) /* (TC) Effect: clear */ +#define AT91C_TC_ACPC_TOGGLE ( ( unsigned int ) 0x3 << 18 ) /* (TC) Effect: toggle */ +#define AT91C_TC_LDRB ( ( unsigned int ) 0x3 << 18 ) /* (TC) RB Loading Selection */ +#define AT91C_TC_LDRB_NONE ( ( unsigned int ) 0x0 << 18 ) /* (TC) Edge: None */ +#define AT91C_TC_LDRB_RISING ( ( unsigned int ) 0x1 << 18 ) /* (TC) Edge: rising edge of TIOA */ +#define AT91C_TC_LDRB_FALLING ( ( unsigned int ) 0x2 << 18 ) /* (TC) Edge: falling edge of TIOA */ +#define AT91C_TC_LDRB_BOTH ( ( unsigned int ) 0x3 << 18 ) /* (TC) Edge: each edge of TIOA */ +#define AT91C_TC_AEEVT ( ( unsigned int ) 0x3 << 20 ) /* (TC) External Event Effect on TIOA */ +#define AT91C_TC_AEEVT_NONE ( ( unsigned int ) 0x0 << 20 ) /* (TC) Effect: none */ +#define AT91C_TC_AEEVT_SET ( ( unsigned int ) 0x1 << 20 ) /* (TC) Effect: set */ +#define AT91C_TC_AEEVT_CLEAR ( ( unsigned int ) 0x2 << 20 ) /* (TC) Effect: clear */ +#define AT91C_TC_AEEVT_TOGGLE ( ( unsigned int ) 0x3 << 20 ) /* (TC) Effect: toggle */ +#define AT91C_TC_ASWTRG ( ( unsigned int ) 0x3 << 22 ) /* (TC) Software Trigger Effect on TIOA */ +#define AT91C_TC_ASWTRG_NONE ( ( unsigned int ) 0x0 << 22 ) /* (TC) Effect: none */ +#define AT91C_TC_ASWTRG_SET ( ( unsigned int ) 0x1 << 22 ) /* (TC) Effect: set */ +#define AT91C_TC_ASWTRG_CLEAR ( ( unsigned int ) 0x2 << 22 ) /* (TC) Effect: clear */ +#define AT91C_TC_ASWTRG_TOGGLE ( ( unsigned int ) 0x3 << 22 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BCPB ( ( unsigned int ) 0x3 << 24 ) /* (TC) RB Compare Effect on TIOB */ +#define AT91C_TC_BCPB_NONE ( ( unsigned int ) 0x0 << 24 ) /* (TC) Effect: none */ +#define AT91C_TC_BCPB_SET ( ( unsigned int ) 0x1 << 24 ) /* (TC) Effect: set */ +#define AT91C_TC_BCPB_CLEAR ( ( unsigned int ) 0x2 << 24 ) /* (TC) Effect: clear */ +#define AT91C_TC_BCPB_TOGGLE ( ( unsigned int ) 0x3 << 24 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BCPC ( ( unsigned int ) 0x3 << 26 ) /* (TC) RC Compare Effect on TIOB */ +#define AT91C_TC_BCPC_NONE ( ( unsigned int ) 0x0 << 26 ) /* (TC) Effect: none */ +#define AT91C_TC_BCPC_SET ( ( unsigned int ) 0x1 << 26 ) /* (TC) Effect: set */ +#define AT91C_TC_BCPC_CLEAR ( ( unsigned int ) 0x2 << 26 ) /* (TC) Effect: clear */ +#define AT91C_TC_BCPC_TOGGLE ( ( unsigned int ) 0x3 << 26 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BEEVT ( ( unsigned int ) 0x3 << 28 ) /* (TC) External Event Effect on TIOB */ +#define AT91C_TC_BEEVT_NONE ( ( unsigned int ) 0x0 << 28 ) /* (TC) Effect: none */ +#define AT91C_TC_BEEVT_SET ( ( unsigned int ) 0x1 << 28 ) /* (TC) Effect: set */ +#define AT91C_TC_BEEVT_CLEAR ( ( unsigned int ) 0x2 << 28 ) /* (TC) Effect: clear */ +#define AT91C_TC_BEEVT_TOGGLE ( ( unsigned int ) 0x3 << 28 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BSWTRG ( ( unsigned int ) 0x3 << 30 ) /* (TC) Software Trigger Effect on TIOB */ +#define AT91C_TC_BSWTRG_NONE ( ( unsigned int ) 0x0 << 30 ) /* (TC) Effect: none */ +#define AT91C_TC_BSWTRG_SET ( ( unsigned int ) 0x1 << 30 ) /* (TC) Effect: set */ +#define AT91C_TC_BSWTRG_CLEAR ( ( unsigned int ) 0x2 << 30 ) /* (TC) Effect: clear */ +#define AT91C_TC_BSWTRG_TOGGLE ( ( unsigned int ) 0x3 << 30 ) /* (TC) Effect: toggle */ +/* -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- */ +#define AT91C_TC_COVFS ( ( unsigned int ) 0x1 << 0 ) /* (TC) Counter Overflow */ +#define AT91C_TC_LOVRS ( ( unsigned int ) 0x1 << 1 ) /* (TC) Load Overrun */ +#define AT91C_TC_CPAS ( ( unsigned int ) 0x1 << 2 ) /* (TC) RA Compare */ +#define AT91C_TC_CPBS ( ( unsigned int ) 0x1 << 3 ) /* (TC) RB Compare */ +#define AT91C_TC_CPCS ( ( unsigned int ) 0x1 << 4 ) /* (TC) RC Compare */ +#define AT91C_TC_LDRAS ( ( unsigned int ) 0x1 << 5 ) /* (TC) RA Loading */ +#define AT91C_TC_LDRBS ( ( unsigned int ) 0x1 << 6 ) /* (TC) RB Loading */ +#define AT91C_TC_ETRGS ( ( unsigned int ) 0x1 << 7 ) /* (TC) External Trigger */ +#define AT91C_TC_CLKSTA ( ( unsigned int ) 0x1 << 16 ) /* (TC) Clock Enabling */ +#define AT91C_TC_MTIOA ( ( unsigned int ) 0x1 << 17 ) /* (TC) TIOA Mirror */ +#define AT91C_TC_MTIOB ( ( unsigned int ) 0x1 << 18 ) /* (TC) TIOA Mirror */ +/* -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- */ +/* -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- */ +/* -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Timer Counter Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_TCB +{ + AT91S_TC TCB_TC0; /* TC Channel 0 */ + AT91_REG Reserved0[ 4 ]; /* */ + AT91S_TC TCB_TC1; /* TC Channel 1 */ + AT91_REG Reserved1[ 4 ]; /* */ + AT91S_TC TCB_TC2; /* TC Channel 2 */ + AT91_REG Reserved2[ 4 ]; /* */ + AT91_REG TCB_BCR; /* TC Block Control Register */ + AT91_REG TCB_BMR; /* TC Block Mode Register */ +} AT91S_TCB, * AT91PS_TCB; + +/* -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- */ +#define AT91C_TCB_SYNC ( ( unsigned int ) 0x1 << 0 ) /* (TCB) Synchro Command */ +/* -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- */ +#define AT91C_TCB_TC0XC0S ( ( unsigned int ) 0x3 << 0 ) /* (TCB) External Clock Signal 0 Selection */ +#define AT91C_TCB_TC0XC0S_TCLK0 ( ( unsigned int ) 0x0 ) /* (TCB) TCLK0 connected to XC0 */ +#define AT91C_TCB_TC0XC0S_NONE ( ( unsigned int ) 0x1 ) /* (TCB) None signal connected to XC0 */ +#define AT91C_TCB_TC0XC0S_TIOA1 ( ( unsigned int ) 0x2 ) /* (TCB) TIOA1 connected to XC0 */ +#define AT91C_TCB_TC0XC0S_TIOA2 ( ( unsigned int ) 0x3 ) /* (TCB) TIOA2 connected to XC0 */ +#define AT91C_TCB_TC1XC1S ( ( unsigned int ) 0x3 << 2 ) /* (TCB) External Clock Signal 1 Selection */ +#define AT91C_TCB_TC1XC1S_TCLK1 ( ( unsigned int ) 0x0 << 2 ) /* (TCB) TCLK1 connected to XC1 */ +#define AT91C_TCB_TC1XC1S_NONE ( ( unsigned int ) 0x1 << 2 ) /* (TCB) None signal connected to XC1 */ +#define AT91C_TCB_TC1XC1S_TIOA0 ( ( unsigned int ) 0x2 << 2 ) /* (TCB) TIOA0 connected to XC1 */ +#define AT91C_TCB_TC1XC1S_TIOA2 ( ( unsigned int ) 0x3 << 2 ) /* (TCB) TIOA2 connected to XC1 */ +#define AT91C_TCB_TC2XC2S ( ( unsigned int ) 0x3 << 4 ) /* (TCB) External Clock Signal 2 Selection */ +#define AT91C_TCB_TC2XC2S_TCLK2 ( ( unsigned int ) 0x0 << 4 ) /* (TCB) TCLK2 connected to XC2 */ +#define AT91C_TCB_TC2XC2S_NONE ( ( unsigned int ) 0x1 << 4 ) /* (TCB) None signal connected to XC2 */ +#define AT91C_TCB_TC2XC2S_TIOA0 ( ( unsigned int ) 0x2 << 4 ) /* (TCB) TIOA0 connected to XC2 */ +#define AT91C_TCB_TC2XC2S_TIOA1 ( ( unsigned int ) 0x3 << 4 ) /* (TCB) TIOA2 connected to XC2 */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_CAN_MB +{ + AT91_REG CAN_MB_MMR; /* MailBox Mode Register */ + AT91_REG CAN_MB_MAM; /* MailBox Acceptance Mask Register */ + AT91_REG CAN_MB_MID; /* MailBox ID Register */ + AT91_REG CAN_MB_MFID; /* MailBox Family ID Register */ + AT91_REG CAN_MB_MSR; /* MailBox Status Register */ + AT91_REG CAN_MB_MDL; /* MailBox Data Low Register */ + AT91_REG CAN_MB_MDH; /* MailBox Data High Register */ + AT91_REG CAN_MB_MCR; /* MailBox Control Register */ +} AT91S_CAN_MB, * AT91PS_CAN_MB; + +/* -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- */ +#define AT91C_CAN_MTIMEMARK ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN_MB) Mailbox Timemark */ +#define AT91C_CAN_PRIOR ( ( unsigned int ) 0xF << 16 ) /* (CAN_MB) Mailbox Priority */ +#define AT91C_CAN_MOT ( ( unsigned int ) 0x7 << 24 ) /* (CAN_MB) Mailbox Object Type */ +#define AT91C_CAN_MOT_DIS ( ( unsigned int ) 0x0 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_RX ( ( unsigned int ) 0x1 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_RXOVERWRITE ( ( unsigned int ) 0x2 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_TX ( ( unsigned int ) 0x3 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_CONSUMER ( ( unsigned int ) 0x4 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_PRODUCER ( ( unsigned int ) 0x5 << 24 ) /* (CAN_MB) */ +/* -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- */ +#define AT91C_CAN_MIDvB ( ( unsigned int ) 0x3FFFF << 0 ) /* (CAN_MB) Complementary bits for identifier in extended mode */ +#define AT91C_CAN_MIDvA ( ( unsigned int ) 0x7FF << 18 ) /* (CAN_MB) Identifier for standard frame mode */ +#define AT91C_CAN_MIDE ( ( unsigned int ) 0x1 << 29 ) /* (CAN_MB) Identifier Version */ +/* -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- */ +/* -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- */ +/* -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- */ +#define AT91C_CAN_MTIMESTAMP ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN_MB) Timer Value */ +#define AT91C_CAN_MDLC ( ( unsigned int ) 0xF << 16 ) /* (CAN_MB) Mailbox Data Length Code */ +#define AT91C_CAN_MRTR ( ( unsigned int ) 0x1 << 20 ) /* (CAN_MB) Mailbox Remote Transmission Request */ +#define AT91C_CAN_MABT ( ( unsigned int ) 0x1 << 22 ) /* (CAN_MB) Mailbox Message Abort */ +#define AT91C_CAN_MRDY ( ( unsigned int ) 0x1 << 23 ) /* (CAN_MB) Mailbox Ready */ +#define AT91C_CAN_MMI ( ( unsigned int ) 0x1 << 24 ) /* (CAN_MB) Mailbox Message Ignored */ +/* -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- */ +/* -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- */ +/* -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- */ +#define AT91C_CAN_MACR ( ( unsigned int ) 0x1 << 22 ) /* (CAN_MB) Abort Request for Mailbox */ +#define AT91C_CAN_MTCR ( ( unsigned int ) 0x1 << 23 ) /* (CAN_MB) Mailbox Transfer Command */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Control Area Network Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_CAN +{ + AT91_REG CAN_MR; /* Mode Register */ + AT91_REG CAN_IER; /* Interrupt Enable Register */ + AT91_REG CAN_IDR; /* Interrupt Disable Register */ + AT91_REG CAN_IMR; /* Interrupt Mask Register */ + AT91_REG CAN_SR; /* Status Register */ + AT91_REG CAN_BR; /* Baudrate Register */ + AT91_REG CAN_TIM; /* Timer Register */ + AT91_REG CAN_TIMESTP; /* Time Stamp Register */ + AT91_REG CAN_ECR; /* Error Counter Register */ + AT91_REG CAN_TCR; /* Transfer Command Register */ + AT91_REG CAN_ACR; /* Abort Command Register */ + AT91_REG Reserved0[ 52 ]; /* */ + AT91_REG CAN_VR; /* Version Register */ + AT91_REG Reserved1[ 64 ]; /* */ + AT91S_CAN_MB CAN_MB0; /* CAN Mailbox 0 */ + AT91S_CAN_MB CAN_MB1; /* CAN Mailbox 1 */ + AT91S_CAN_MB CAN_MB2; /* CAN Mailbox 2 */ + AT91S_CAN_MB CAN_MB3; /* CAN Mailbox 3 */ + AT91S_CAN_MB CAN_MB4; /* CAN Mailbox 4 */ + AT91S_CAN_MB CAN_MB5; /* CAN Mailbox 5 */ + AT91S_CAN_MB CAN_MB6; /* CAN Mailbox 6 */ + AT91S_CAN_MB CAN_MB7; /* CAN Mailbox 7 */ + AT91S_CAN_MB CAN_MB8; /* CAN Mailbox 8 */ + AT91S_CAN_MB CAN_MB9; /* CAN Mailbox 9 */ + AT91S_CAN_MB CAN_MB10; /* CAN Mailbox 10 */ + AT91S_CAN_MB CAN_MB11; /* CAN Mailbox 11 */ + AT91S_CAN_MB CAN_MB12; /* CAN Mailbox 12 */ + AT91S_CAN_MB CAN_MB13; /* CAN Mailbox 13 */ + AT91S_CAN_MB CAN_MB14; /* CAN Mailbox 14 */ + AT91S_CAN_MB CAN_MB15; /* CAN Mailbox 15 */ +} AT91S_CAN, * AT91PS_CAN; + +/* -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- */ +#define AT91C_CAN_CANEN ( ( unsigned int ) 0x1 << 0 ) /* (CAN) CAN Controller Enable */ +#define AT91C_CAN_LPM ( ( unsigned int ) 0x1 << 1 ) /* (CAN) Disable/Enable Low Power Mode */ +#define AT91C_CAN_ABM ( ( unsigned int ) 0x1 << 2 ) /* (CAN) Disable/Enable Autobaud/Listen Mode */ +#define AT91C_CAN_OVL ( ( unsigned int ) 0x1 << 3 ) /* (CAN) Disable/Enable Overload Frame */ +#define AT91C_CAN_TEOF ( ( unsigned int ) 0x1 << 4 ) /* (CAN) Time Stamp messages at each end of Frame */ +#define AT91C_CAN_TTM ( ( unsigned int ) 0x1 << 5 ) /* (CAN) Disable/Enable Time Trigger Mode */ +#define AT91C_CAN_TIMFRZ ( ( unsigned int ) 0x1 << 6 ) /* (CAN) Enable Timer Freeze */ +#define AT91C_CAN_DRPT ( ( unsigned int ) 0x1 << 7 ) /* (CAN) Disable Repeat */ +/* -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- */ +#define AT91C_CAN_MB0 ( ( unsigned int ) 0x1 << 0 ) /* (CAN) Mailbox 0 Flag */ +#define AT91C_CAN_MB1 ( ( unsigned int ) 0x1 << 1 ) /* (CAN) Mailbox 1 Flag */ +#define AT91C_CAN_MB2 ( ( unsigned int ) 0x1 << 2 ) /* (CAN) Mailbox 2 Flag */ +#define AT91C_CAN_MB3 ( ( unsigned int ) 0x1 << 3 ) /* (CAN) Mailbox 3 Flag */ +#define AT91C_CAN_MB4 ( ( unsigned int ) 0x1 << 4 ) /* (CAN) Mailbox 4 Flag */ +#define AT91C_CAN_MB5 ( ( unsigned int ) 0x1 << 5 ) /* (CAN) Mailbox 5 Flag */ +#define AT91C_CAN_MB6 ( ( unsigned int ) 0x1 << 6 ) /* (CAN) Mailbox 6 Flag */ +#define AT91C_CAN_MB7 ( ( unsigned int ) 0x1 << 7 ) /* (CAN) Mailbox 7 Flag */ +#define AT91C_CAN_MB8 ( ( unsigned int ) 0x1 << 8 ) /* (CAN) Mailbox 8 Flag */ +#define AT91C_CAN_MB9 ( ( unsigned int ) 0x1 << 9 ) /* (CAN) Mailbox 9 Flag */ +#define AT91C_CAN_MB10 ( ( unsigned int ) 0x1 << 10 ) /* (CAN) Mailbox 10 Flag */ +#define AT91C_CAN_MB11 ( ( unsigned int ) 0x1 << 11 ) /* (CAN) Mailbox 11 Flag */ +#define AT91C_CAN_MB12 ( ( unsigned int ) 0x1 << 12 ) /* (CAN) Mailbox 12 Flag */ +#define AT91C_CAN_MB13 ( ( unsigned int ) 0x1 << 13 ) /* (CAN) Mailbox 13 Flag */ +#define AT91C_CAN_MB14 ( ( unsigned int ) 0x1 << 14 ) /* (CAN) Mailbox 14 Flag */ +#define AT91C_CAN_MB15 ( ( unsigned int ) 0x1 << 15 ) /* (CAN) Mailbox 15 Flag */ +#define AT91C_CAN_ERRA ( ( unsigned int ) 0x1 << 16 ) /* (CAN) Error Active Mode Flag */ +#define AT91C_CAN_WARN ( ( unsigned int ) 0x1 << 17 ) /* (CAN) Warning Limit Flag */ +#define AT91C_CAN_ERRP ( ( unsigned int ) 0x1 << 18 ) /* (CAN) Error Passive Mode Flag */ +#define AT91C_CAN_BOFF ( ( unsigned int ) 0x1 << 19 ) /* (CAN) Bus Off Mode Flag */ +#define AT91C_CAN_SLEEP ( ( unsigned int ) 0x1 << 20 ) /* (CAN) Sleep Flag */ +#define AT91C_CAN_WAKEUP ( ( unsigned int ) 0x1 << 21 ) /* (CAN) Wakeup Flag */ +#define AT91C_CAN_TOVF ( ( unsigned int ) 0x1 << 22 ) /* (CAN) Timer Overflow Flag */ +#define AT91C_CAN_TSTP ( ( unsigned int ) 0x1 << 23 ) /* (CAN) Timestamp Flag */ +#define AT91C_CAN_CERR ( ( unsigned int ) 0x1 << 24 ) /* (CAN) CRC Error */ +#define AT91C_CAN_SERR ( ( unsigned int ) 0x1 << 25 ) /* (CAN) Stuffing Error */ +#define AT91C_CAN_AERR ( ( unsigned int ) 0x1 << 26 ) /* (CAN) Acknowledgment Error */ +#define AT91C_CAN_FERR ( ( unsigned int ) 0x1 << 27 ) /* (CAN) Form Error */ +#define AT91C_CAN_BERR ( ( unsigned int ) 0x1 << 28 ) /* (CAN) Bit Error */ +/* -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- */ +/* -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- */ +/* -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- */ +#define AT91C_CAN_RBSY ( ( unsigned int ) 0x1 << 29 ) /* (CAN) Receiver Busy */ +#define AT91C_CAN_TBSY ( ( unsigned int ) 0x1 << 30 ) /* (CAN) Transmitter Busy */ +#define AT91C_CAN_OVLY ( ( unsigned int ) 0x1 << 31 ) /* (CAN) Overload Busy */ +/* -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- */ +#define AT91C_CAN_PHASE2 ( ( unsigned int ) 0x7 << 0 ) /* (CAN) Phase 2 segment */ +#define AT91C_CAN_PHASE1 ( ( unsigned int ) 0x7 << 4 ) /* (CAN) Phase 1 segment */ +#define AT91C_CAN_PROPAG ( ( unsigned int ) 0x7 << 8 ) /* (CAN) Programmation time segment */ +#define AT91C_CAN_SYNC ( ( unsigned int ) 0x3 << 12 ) /* (CAN) Re-synchronization jump width segment */ +#define AT91C_CAN_BRP ( ( unsigned int ) 0x7F << 16 ) /* (CAN) Baudrate Prescaler */ +#define AT91C_CAN_SMP ( ( unsigned int ) 0x1 << 24 ) /* (CAN) Sampling mode */ +/* -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- */ +#define AT91C_CAN_TIMER ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN) Timer field */ +/* -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- */ +/* -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- */ +#define AT91C_CAN_REC ( ( unsigned int ) 0xFF << 0 ) /* (CAN) Receive Error Counter */ +#define AT91C_CAN_TEC ( ( unsigned int ) 0xFF << 16 ) /* (CAN) Transmit Error Counter */ +/* -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- */ +#define AT91C_CAN_TIMRST ( ( unsigned int ) 0x1 << 31 ) /* (CAN) Timer Reset Field */ +/* -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 */ +/* ***************************************************************************** */ +typedef struct _AT91S_EMAC +{ + AT91_REG EMAC_NCR; /* Network Control Register */ + AT91_REG EMAC_NCFGR; /* Network Configuration Register */ + AT91_REG EMAC_NSR; /* Network Status Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG EMAC_TSR; /* Transmit Status Register */ + AT91_REG EMAC_RBQP; /* Receive Buffer Queue Pointer */ + AT91_REG EMAC_TBQP; /* Transmit Buffer Queue Pointer */ + AT91_REG EMAC_RSR; /* Receive Status Register */ + AT91_REG EMAC_ISR; /* Interrupt Status Register */ + AT91_REG EMAC_IER; /* Interrupt Enable Register */ + AT91_REG EMAC_IDR; /* Interrupt Disable Register */ + AT91_REG EMAC_IMR; /* Interrupt Mask Register */ + AT91_REG EMAC_MAN; /* PHY Maintenance Register */ + AT91_REG EMAC_PTR; /* Pause Time Register */ + AT91_REG EMAC_PFR; /* Pause Frames received Register */ + AT91_REG EMAC_FTO; /* Frames Transmitted OK Register */ + AT91_REG EMAC_SCF; /* Single Collision Frame Register */ + AT91_REG EMAC_MCF; /* Multiple Collision Frame Register */ + AT91_REG EMAC_FRO; /* Frames Received OK Register */ + AT91_REG EMAC_FCSE; /* Frame Check Sequence Error Register */ + AT91_REG EMAC_ALE; /* Alignment Error Register */ + AT91_REG EMAC_DTF; /* Deferred Transmission Frame Register */ + AT91_REG EMAC_LCOL; /* Late Collision Register */ + AT91_REG EMAC_ECOL; /* Excessive Collision Register */ + AT91_REG EMAC_TUND; /* Transmit Underrun Error Register */ + AT91_REG EMAC_CSE; /* Carrier Sense Error Register */ + AT91_REG EMAC_RRE; /* Receive Resource Error Register */ + AT91_REG EMAC_ROV; /* Receive Overrun Errors Register */ + AT91_REG EMAC_RSE; /* Receive Symbol Errors Register */ + AT91_REG EMAC_ELE; /* Excessive Length Errors Register */ + AT91_REG EMAC_RJA; /* Receive Jabbers Register */ + AT91_REG EMAC_USF; /* Undersize Frames Register */ + AT91_REG EMAC_STE; /* SQE Test Error Register */ + AT91_REG EMAC_RLE; /* Receive Length Field Mismatch Register */ + AT91_REG EMAC_TPF; /* Transmitted Pause Frames Register */ + AT91_REG EMAC_HRB; /* Hash Address Bottom[31:0] */ + AT91_REG EMAC_HRT; /* Hash Address Top[63:32] */ + AT91_REG EMAC_SA1L; /* Specific Address 1 Bottom, First 4 bytes */ + AT91_REG EMAC_SA1H; /* Specific Address 1 Top, Last 2 bytes */ + AT91_REG EMAC_SA2L; /* Specific Address 2 Bottom, First 4 bytes */ + AT91_REG EMAC_SA2H; /* Specific Address 2 Top, Last 2 bytes */ + AT91_REG EMAC_SA3L; /* Specific Address 3 Bottom, First 4 bytes */ + AT91_REG EMAC_SA3H; /* Specific Address 3 Top, Last 2 bytes */ + AT91_REG EMAC_SA4L; /* Specific Address 4 Bottom, First 4 bytes */ + AT91_REG EMAC_SA4H; /* Specific Address 4 Top, Last 2 bytes */ + AT91_REG EMAC_TID; /* Type ID Checking Register */ + AT91_REG EMAC_TPQ; /* Transmit Pause Quantum Register */ + AT91_REG EMAC_USRIO; /* USER Input/Output Register */ + AT91_REG EMAC_WOL; /* Wake On LAN Register */ + AT91_REG Reserved1[ 13 ]; /* */ + AT91_REG EMAC_REV; /* Revision Register */ +} AT91S_EMAC, * AT91PS_EMAC; + +/* -------- EMAC_NCR : (EMAC Offset: 0x0) -------- */ +#define AT91C_EMAC_LB ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */ +#define AT91C_EMAC_LLB ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) Loopback local. */ +#define AT91C_EMAC_RE ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) Receive enable. */ +#define AT91C_EMAC_TE ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) Transmit enable. */ +#define AT91C_EMAC_MPE ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) Management port enable. */ +#define AT91C_EMAC_CLRSTAT ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) Clear statistics registers. */ +#define AT91C_EMAC_INCSTAT ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) Increment statistics registers. */ +#define AT91C_EMAC_WESTAT ( ( unsigned int ) 0x1 << 7 ) /* (EMAC) Write enable for statistics registers. */ +#define AT91C_EMAC_BP ( ( unsigned int ) 0x1 << 8 ) /* (EMAC) Back pressure. */ +#define AT91C_EMAC_TSTART ( ( unsigned int ) 0x1 << 9 ) /* (EMAC) Start Transmission. */ +#define AT91C_EMAC_THALT ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) Transmission Halt. */ +#define AT91C_EMAC_TPFR ( ( unsigned int ) 0x1 << 11 ) /* (EMAC) Transmit pause frame */ +#define AT91C_EMAC_TZQ ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) Transmit zero quantum pause frame */ +/* -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- */ +#define AT91C_EMAC_SPD ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) Speed. */ +#define AT91C_EMAC_FD ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) Full duplex. */ +#define AT91C_EMAC_JFRAME ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) Jumbo Frames. */ +#define AT91C_EMAC_CAF ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) Copy all frames. */ +#define AT91C_EMAC_NBC ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) No broadcast. */ +#define AT91C_EMAC_MTI ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) Multicast hash event enable */ +#define AT91C_EMAC_UNI ( ( unsigned int ) 0x1 << 7 ) /* (EMAC) Unicast hash enable. */ +#define AT91C_EMAC_BIG ( ( unsigned int ) 0x1 << 8 ) /* (EMAC) Receive 1522 bytes. */ +#define AT91C_EMAC_EAE ( ( unsigned int ) 0x1 << 9 ) /* (EMAC) External address match enable. */ +#define AT91C_EMAC_CLK ( ( unsigned int ) 0x3 << 10 ) /* (EMAC) */ +#define AT91C_EMAC_CLK_HCLK_8 ( ( unsigned int ) 0x0 << 10 ) /* (EMAC) HCLK divided by 8 */ +#define AT91C_EMAC_CLK_HCLK_16 ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) HCLK divided by 16 */ +#define AT91C_EMAC_CLK_HCLK_32 ( ( unsigned int ) 0x2 << 10 ) /* (EMAC) HCLK divided by 32 */ +#define AT91C_EMAC_CLK_HCLK_64 ( ( unsigned int ) 0x3 << 10 ) /* (EMAC) HCLK divided by 64 */ +#define AT91C_EMAC_RTY ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) */ +#define AT91C_EMAC_PAE ( ( unsigned int ) 0x1 << 13 ) /* (EMAC) */ +#define AT91C_EMAC_RBOF ( ( unsigned int ) 0x3 << 14 ) /* (EMAC) */ +#define AT91C_EMAC_RBOF_OFFSET_0 ( ( unsigned int ) 0x0 << 14 ) /* (EMAC) no offset from start of receive buffer */ +#define AT91C_EMAC_RBOF_OFFSET_1 ( ( unsigned int ) 0x1 << 14 ) /* (EMAC) one byte offset from start of receive buffer */ +#define AT91C_EMAC_RBOF_OFFSET_2 ( ( unsigned int ) 0x2 << 14 ) /* (EMAC) two bytes offset from start of receive buffer */ +#define AT91C_EMAC_RBOF_OFFSET_3 ( ( unsigned int ) 0x3 << 14 ) /* (EMAC) three bytes offset from start of receive buffer */ +#define AT91C_EMAC_RLCE ( ( unsigned int ) 0x1 << 16 ) /* (EMAC) Receive Length field Checking Enable */ +#define AT91C_EMAC_DRFCS ( ( unsigned int ) 0x1 << 17 ) /* (EMAC) Discard Receive FCS */ +#define AT91C_EMAC_EFRHD ( ( unsigned int ) 0x1 << 18 ) /* (EMAC) */ +#define AT91C_EMAC_IRXFCS ( ( unsigned int ) 0x1 << 19 ) /* (EMAC) Ignore RX FCS */ +/* -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- */ +#define AT91C_EMAC_LINKR ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_MDIO ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_IDLE ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */ +/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- */ +#define AT91C_EMAC_UBR ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_COL ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_RLES ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */ +#define AT91C_EMAC_TGO ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) Transmit Go */ +#define AT91C_EMAC_BEX ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) Buffers exhausted mid frame */ +#define AT91C_EMAC_COMP ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) */ +#define AT91C_EMAC_UND ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) */ +/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */ +#define AT91C_EMAC_BNA ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_REC ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_OVR ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */ +/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */ +#define AT91C_EMAC_MFD ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_RCOMP ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_RXUBR ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */ +#define AT91C_EMAC_TXUBR ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) */ +#define AT91C_EMAC_TUNDR ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) */ +#define AT91C_EMAC_RLEX ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) */ +#define AT91C_EMAC_TXERR ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) */ +#define AT91C_EMAC_TCOMP ( ( unsigned int ) 0x1 << 7 ) /* (EMAC) */ +#define AT91C_EMAC_LINK ( ( unsigned int ) 0x1 << 9 ) /* (EMAC) */ +#define AT91C_EMAC_ROVR ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) */ +#define AT91C_EMAC_HRESP ( ( unsigned int ) 0x1 << 11 ) /* (EMAC) */ +#define AT91C_EMAC_PFRE ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) */ +#define AT91C_EMAC_PTZ ( ( unsigned int ) 0x1 << 13 ) /* (EMAC) */ +/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */ +/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */ +/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */ +/* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */ +#define AT91C_EMAC_DATA ( ( unsigned int ) 0xFFFF << 0 ) /* (EMAC) */ +#define AT91C_EMAC_CODE ( ( unsigned int ) 0x3 << 16 ) /* (EMAC) */ +#define AT91C_EMAC_REGA ( ( unsigned int ) 0x1F << 18 ) /* (EMAC) */ +#define AT91C_EMAC_PHYA ( ( unsigned int ) 0x1F << 23 ) /* (EMAC) */ +#define AT91C_EMAC_RW ( ( unsigned int ) 0x3 << 28 ) /* (EMAC) */ +#define AT91C_EMAC_SOF ( ( unsigned int ) 0x3 << 30 ) /* (EMAC) */ +/* -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- */ +#define AT91C_EMAC_RMII ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) Reduce MII */ +/* -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- */ +#define AT91C_EMAC_IP ( ( unsigned int ) 0xFFFF << 0 ) /* (EMAC) ARP request IP address */ +#define AT91C_EMAC_MAG ( ( unsigned int ) 0x1 << 16 ) /* (EMAC) Magic packet event enable */ +#define AT91C_EMAC_ARP ( ( unsigned int ) 0x1 << 17 ) /* (EMAC) ARP request event enable */ +#define AT91C_EMAC_SA1 ( ( unsigned int ) 0x1 << 18 ) /* (EMAC) Specific address register 1 event enable */ +/* -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- */ +#define AT91C_EMAC_REVREF ( ( unsigned int ) 0xFFFF << 0 ) /* (EMAC) */ +#define AT91C_EMAC_PARTREF ( ( unsigned int ) 0xFFFF << 16 ) /* (EMAC) */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Analog to Digital Convertor */ +/* ***************************************************************************** */ +typedef struct _AT91S_ADC +{ + AT91_REG ADC_CR; /* ADC Control Register */ + AT91_REG ADC_MR; /* ADC Mode Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG ADC_CHER; /* ADC Channel Enable Register */ + AT91_REG ADC_CHDR; /* ADC Channel Disable Register */ + AT91_REG ADC_CHSR; /* ADC Channel Status Register */ + AT91_REG ADC_SR; /* ADC Status Register */ + AT91_REG ADC_LCDR; /* ADC Last Converted Data Register */ + AT91_REG ADC_IER; /* ADC Interrupt Enable Register */ + AT91_REG ADC_IDR; /* ADC Interrupt Disable Register */ + AT91_REG ADC_IMR; /* ADC Interrupt Mask Register */ + AT91_REG ADC_CDR0; /* ADC Channel Data Register 0 */ + AT91_REG ADC_CDR1; /* ADC Channel Data Register 1 */ + AT91_REG ADC_CDR2; /* ADC Channel Data Register 2 */ + AT91_REG ADC_CDR3; /* ADC Channel Data Register 3 */ + AT91_REG ADC_CDR4; /* ADC Channel Data Register 4 */ + AT91_REG ADC_CDR5; /* ADC Channel Data Register 5 */ + AT91_REG ADC_CDR6; /* ADC Channel Data Register 6 */ + AT91_REG ADC_CDR7; /* ADC Channel Data Register 7 */ + AT91_REG Reserved1[ 44 ]; /* */ + AT91_REG ADC_RPR; /* Receive Pointer Register */ + AT91_REG ADC_RCR; /* Receive Counter Register */ + AT91_REG ADC_TPR; /* Transmit Pointer Register */ + AT91_REG ADC_TCR; /* Transmit Counter Register */ + AT91_REG ADC_RNPR; /* Receive Next Pointer Register */ + AT91_REG ADC_RNCR; /* Receive Next Counter Register */ + AT91_REG ADC_TNPR; /* Transmit Next Pointer Register */ + AT91_REG ADC_TNCR; /* Transmit Next Counter Register */ + AT91_REG ADC_PTCR; /* PDC Transfer Control Register */ + AT91_REG ADC_PTSR; /* PDC Transfer Status Register */ +} AT91S_ADC, * AT91PS_ADC; + +/* -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- */ +#define AT91C_ADC_SWRST ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Software Reset */ +#define AT91C_ADC_START ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Start Conversion */ +/* -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- */ +#define AT91C_ADC_TRGEN ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Trigger Enable */ +#define AT91C_ADC_TRGEN_DIS ( ( unsigned int ) 0x0 ) /* (ADC) Hardware triggers are disabled. Starting a conversion is only possible by software */ +#define AT91C_ADC_TRGEN_EN ( ( unsigned int ) 0x1 ) /* (ADC) Hardware trigger selected by TRGSEL field is enabled. */ +#define AT91C_ADC_TRGSEL ( ( unsigned int ) 0x7 << 1 ) /* (ADC) Trigger Selection */ +#define AT91C_ADC_TRGSEL_TIOA0 ( ( unsigned int ) 0x0 << 1 ) /* (ADC) Selected TRGSEL = TIAO0 */ +#define AT91C_ADC_TRGSEL_TIOA1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Selected TRGSEL = TIAO1 */ +#define AT91C_ADC_TRGSEL_TIOA2 ( ( unsigned int ) 0x2 << 1 ) /* (ADC) Selected TRGSEL = TIAO2 */ +#define AT91C_ADC_TRGSEL_TIOA3 ( ( unsigned int ) 0x3 << 1 ) /* (ADC) Selected TRGSEL = TIAO3 */ +#define AT91C_ADC_TRGSEL_TIOA4 ( ( unsigned int ) 0x4 << 1 ) /* (ADC) Selected TRGSEL = TIAO4 */ +#define AT91C_ADC_TRGSEL_TIOA5 ( ( unsigned int ) 0x5 << 1 ) /* (ADC) Selected TRGSEL = TIAO5 */ +#define AT91C_ADC_TRGSEL_EXT ( ( unsigned int ) 0x6 << 1 ) /* (ADC) Selected TRGSEL = External Trigger */ +#define AT91C_ADC_LOWRES ( ( unsigned int ) 0x1 << 4 ) /* (ADC) Resolution. */ +#define AT91C_ADC_LOWRES_10_BIT ( ( unsigned int ) 0x0 << 4 ) /* (ADC) 10-bit resolution */ +#define AT91C_ADC_LOWRES_8_BIT ( ( unsigned int ) 0x1 << 4 ) /* (ADC) 8-bit resolution */ +#define AT91C_ADC_SLEEP ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Sleep Mode */ +#define AT91C_ADC_SLEEP_NORMAL_MODE ( ( unsigned int ) 0x0 << 5 ) /* (ADC) Normal Mode */ +#define AT91C_ADC_SLEEP_MODE ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Sleep Mode */ +#define AT91C_ADC_PRESCAL ( ( unsigned int ) 0x3F << 8 ) /* (ADC) Prescaler rate selection */ +#define AT91C_ADC_STARTUP ( ( unsigned int ) 0x1F << 16 ) /* (ADC) Startup Time */ +#define AT91C_ADC_SHTIM ( ( unsigned int ) 0xF << 24 ) /* (ADC) Sample & Hold Time */ +/* -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- */ +#define AT91C_ADC_CH0 ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Channel 0 */ +#define AT91C_ADC_CH1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Channel 1 */ +#define AT91C_ADC_CH2 ( ( unsigned int ) 0x1 << 2 ) /* (ADC) Channel 2 */ +#define AT91C_ADC_CH3 ( ( unsigned int ) 0x1 << 3 ) /* (ADC) Channel 3 */ +#define AT91C_ADC_CH4 ( ( unsigned int ) 0x1 << 4 ) /* (ADC) Channel 4 */ +#define AT91C_ADC_CH5 ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Channel 5 */ +#define AT91C_ADC_CH6 ( ( unsigned int ) 0x1 << 6 ) /* (ADC) Channel 6 */ +#define AT91C_ADC_CH7 ( ( unsigned int ) 0x1 << 7 ) /* (ADC) Channel 7 */ +/* -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- */ +/* -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- */ +/* -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- */ +#define AT91C_ADC_EOC0 ( ( unsigned int ) 0x1 << 0 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC2 ( ( unsigned int ) 0x1 << 2 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC3 ( ( unsigned int ) 0x1 << 3 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC4 ( ( unsigned int ) 0x1 << 4 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC5 ( ( unsigned int ) 0x1 << 5 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC6 ( ( unsigned int ) 0x1 << 6 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC7 ( ( unsigned int ) 0x1 << 7 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_OVRE0 ( ( unsigned int ) 0x1 << 8 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE1 ( ( unsigned int ) 0x1 << 9 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE2 ( ( unsigned int ) 0x1 << 10 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE3 ( ( unsigned int ) 0x1 << 11 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE4 ( ( unsigned int ) 0x1 << 12 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE5 ( ( unsigned int ) 0x1 << 13 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE6 ( ( unsigned int ) 0x1 << 14 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE7 ( ( unsigned int ) 0x1 << 15 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_DRDY ( ( unsigned int ) 0x1 << 16 ) /* (ADC) Data Ready */ +#define AT91C_ADC_GOVRE ( ( unsigned int ) 0x1 << 17 ) /* (ADC) General Overrun */ +#define AT91C_ADC_ENDRX ( ( unsigned int ) 0x1 << 18 ) /* (ADC) End of Receiver Transfer */ +#define AT91C_ADC_RXBUFF ( ( unsigned int ) 0x1 << 19 ) /* (ADC) RXBUFF Interrupt */ +/* -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- */ +#define AT91C_ADC_LDATA ( ( unsigned int ) 0x3FF << 0 ) /* (ADC) Last Data Converted */ +/* -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- */ +/* -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- */ +/* -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- */ +/* -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- */ +#define AT91C_ADC_DATA ( ( unsigned int ) 0x3FF << 0 ) /* (ADC) Converted Data */ +/* -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- */ +/* -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- */ +/* -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- */ +/* -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- */ +/* -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- */ +/* -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- */ +/* -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Advanced Encryption Standard */ +/* ***************************************************************************** */ +typedef struct _AT91S_AES +{ + AT91_REG AES_CR; /* Control Register */ + AT91_REG AES_MR; /* Mode Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG AES_IER; /* Interrupt Enable Register */ + AT91_REG AES_IDR; /* Interrupt Disable Register */ + AT91_REG AES_IMR; /* Interrupt Mask Register */ + AT91_REG AES_ISR; /* Interrupt Status Register */ + AT91_REG AES_KEYWxR[ 4 ]; /* Key Word x Register */ + AT91_REG Reserved1[ 4 ]; /* */ + AT91_REG AES_IDATAxR[ 4 ]; /* Input Data x Register */ + AT91_REG AES_ODATAxR[ 4 ]; /* Output Data x Register */ + AT91_REG AES_IVxR[ 4 ]; /* Initialization Vector x Register */ + AT91_REG Reserved2[ 35 ]; /* */ + AT91_REG AES_VR; /* AES Version Register */ + AT91_REG AES_RPR; /* Receive Pointer Register */ + AT91_REG AES_RCR; /* Receive Counter Register */ + AT91_REG AES_TPR; /* Transmit Pointer Register */ + AT91_REG AES_TCR; /* Transmit Counter Register */ + AT91_REG AES_RNPR; /* Receive Next Pointer Register */ + AT91_REG AES_RNCR; /* Receive Next Counter Register */ + AT91_REG AES_TNPR; /* Transmit Next Pointer Register */ + AT91_REG AES_TNCR; /* Transmit Next Counter Register */ + AT91_REG AES_PTCR; /* PDC Transfer Control Register */ + AT91_REG AES_PTSR; /* PDC Transfer Status Register */ +} AT91S_AES, * AT91PS_AES; + +/* -------- AES_CR : (AES Offset: 0x0) Control Register -------- */ +#define AT91C_AES_START ( ( unsigned int ) 0x1 << 0 ) /* (AES) Starts Processing */ +#define AT91C_AES_SWRST ( ( unsigned int ) 0x1 << 8 ) /* (AES) Software Reset */ +#define AT91C_AES_LOADSEED ( ( unsigned int ) 0x1 << 16 ) /* (AES) Random Number Generator Seed Loading */ +/* -------- AES_MR : (AES Offset: 0x4) Mode Register -------- */ +#define AT91C_AES_CIPHER ( ( unsigned int ) 0x1 << 0 ) /* (AES) Processing Mode */ +#define AT91C_AES_PROCDLY ( ( unsigned int ) 0xF << 4 ) /* (AES) Processing Delay */ +#define AT91C_AES_SMOD ( ( unsigned int ) 0x3 << 8 ) /* (AES) Start Mode */ +#define AT91C_AES_SMOD_MANUAL ( ( unsigned int ) 0x0 << 8 ) /* (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. */ +#define AT91C_AES_SMOD_AUTO ( ( unsigned int ) 0x1 << 8 ) /* (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). */ +#define AT91C_AES_SMOD_PDC ( ( unsigned int ) 0x2 << 8 ) /* (AES) PDC Mode (cf datasheet). */ +#define AT91C_AES_OPMOD ( ( unsigned int ) 0x7 << 12 ) /* (AES) Operation Mode */ +#define AT91C_AES_OPMOD_ECB ( ( unsigned int ) 0x0 << 12 ) /* (AES) ECB Electronic CodeBook mode. */ +#define AT91C_AES_OPMOD_CBC ( ( unsigned int ) 0x1 << 12 ) /* (AES) CBC Cipher Block Chaining mode. */ +#define AT91C_AES_OPMOD_OFB ( ( unsigned int ) 0x2 << 12 ) /* (AES) OFB Output Feedback mode. */ +#define AT91C_AES_OPMOD_CFB ( ( unsigned int ) 0x3 << 12 ) /* (AES) CFB Cipher Feedback mode. */ +#define AT91C_AES_OPMOD_CTR ( ( unsigned int ) 0x4 << 12 ) /* (AES) CTR Counter mode. */ +#define AT91C_AES_LOD ( ( unsigned int ) 0x1 << 15 ) /* (AES) Last Output Data Mode */ +#define AT91C_AES_CFBS ( ( unsigned int ) 0x7 << 16 ) /* (AES) Cipher Feedback Data Size */ +#define AT91C_AES_CFBS_128_BIT ( ( unsigned int ) 0x0 << 16 ) /* (AES) 128-bit. */ +#define AT91C_AES_CFBS_64_BIT ( ( unsigned int ) 0x1 << 16 ) /* (AES) 64-bit. */ +#define AT91C_AES_CFBS_32_BIT ( ( unsigned int ) 0x2 << 16 ) /* (AES) 32-bit. */ +#define AT91C_AES_CFBS_16_BIT ( ( unsigned int ) 0x3 << 16 ) /* (AES) 16-bit. */ +#define AT91C_AES_CFBS_8_BIT ( ( unsigned int ) 0x4 << 16 ) /* (AES) 8-bit. */ +#define AT91C_AES_CKEY ( ( unsigned int ) 0xF << 20 ) /* (AES) Countermeasure Key */ +#define AT91C_AES_CTYPE ( ( unsigned int ) 0x1F << 24 ) /* (AES) Countermeasure Type */ +#define AT91C_AES_CTYPE_TYPE1_EN ( ( unsigned int ) 0x1 << 24 ) /* (AES) Countermeasure type 1 is enabled. */ +#define AT91C_AES_CTYPE_TYPE2_EN ( ( unsigned int ) 0x2 << 24 ) /* (AES) Countermeasure type 2 is enabled. */ +#define AT91C_AES_CTYPE_TYPE3_EN ( ( unsigned int ) 0x4 << 24 ) /* (AES) Countermeasure type 3 is enabled. */ +#define AT91C_AES_CTYPE_TYPE4_EN ( ( unsigned int ) 0x8 << 24 ) /* (AES) Countermeasure type 4 is enabled. */ +#define AT91C_AES_CTYPE_TYPE5_EN ( ( unsigned int ) 0x10 << 24 ) /* (AES) Countermeasure type 5 is enabled. */ +/* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */ +#define AT91C_AES_DATRDY ( ( unsigned int ) 0x1 << 0 ) /* (AES) DATRDY */ +#define AT91C_AES_ENDRX ( ( unsigned int ) 0x1 << 1 ) /* (AES) PDC Read Buffer End */ +#define AT91C_AES_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (AES) PDC Write Buffer End */ +#define AT91C_AES_RXBUFF ( ( unsigned int ) 0x1 << 3 ) /* (AES) PDC Read Buffer Full */ +#define AT91C_AES_TXBUFE ( ( unsigned int ) 0x1 << 4 ) /* (AES) PDC Write Buffer Empty */ +#define AT91C_AES_URAD ( ( unsigned int ) 0x1 << 8 ) /* (AES) Unspecified Register Access Detection */ +/* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */ +/* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */ +/* -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- */ +#define AT91C_AES_URAT ( ( unsigned int ) 0x7 << 12 ) /* (AES) Unspecified Register Access Type Status */ +#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ( ( unsigned int ) 0x0 << 12 ) /* (AES) Input data register written during the data processing in PDC mode. */ +#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ( ( unsigned int ) 0x1 << 12 ) /* (AES) Output data register read during the data processing. */ +#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ( ( unsigned int ) 0x2 << 12 ) /* (AES) Mode register written during the data processing. */ +#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ( ( unsigned int ) 0x3 << 12 ) /* (AES) Output data register read during the sub-keys generation. */ +#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ( ( unsigned int ) 0x4 << 12 ) /* (AES) Mode register written during the sub-keys generation. */ +#define AT91C_AES_URAT_WO_REG_READ ( ( unsigned int ) 0x5 << 12 ) /* (AES) Write-only register read access. */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Triple Data Encryption Standard */ +/* ***************************************************************************** */ +typedef struct _AT91S_TDES +{ + AT91_REG TDES_CR; /* Control Register */ + AT91_REG TDES_MR; /* Mode Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG TDES_IER; /* Interrupt Enable Register */ + AT91_REG TDES_IDR; /* Interrupt Disable Register */ + AT91_REG TDES_IMR; /* Interrupt Mask Register */ + AT91_REG TDES_ISR; /* Interrupt Status Register */ + AT91_REG TDES_KEY1WxR[ 2 ]; /* Key 1 Word x Register */ + AT91_REG TDES_KEY2WxR[ 2 ]; /* Key 2 Word x Register */ + AT91_REG TDES_KEY3WxR[ 2 ]; /* Key 3 Word x Register */ + AT91_REG Reserved1[ 2 ]; /* */ + AT91_REG TDES_IDATAxR[ 2 ]; /* Input Data x Register */ + AT91_REG Reserved2[ 2 ]; /* */ + AT91_REG TDES_ODATAxR[ 2 ]; /* Output Data x Register */ + AT91_REG Reserved3[ 2 ]; /* */ + AT91_REG TDES_IVxR[ 2 ]; /* Initialization Vector x Register */ + AT91_REG Reserved4[ 37 ]; /* */ + AT91_REG TDES_VR; /* TDES Version Register */ + AT91_REG TDES_RPR; /* Receive Pointer Register */ + AT91_REG TDES_RCR; /* Receive Counter Register */ + AT91_REG TDES_TPR; /* Transmit Pointer Register */ + AT91_REG TDES_TCR; /* Transmit Counter Register */ + AT91_REG TDES_RNPR; /* Receive Next Pointer Register */ + AT91_REG TDES_RNCR; /* Receive Next Counter Register */ + AT91_REG TDES_TNPR; /* Transmit Next Pointer Register */ + AT91_REG TDES_TNCR; /* Transmit Next Counter Register */ + AT91_REG TDES_PTCR; /* PDC Transfer Control Register */ + AT91_REG TDES_PTSR; /* PDC Transfer Status Register */ +} AT91S_TDES, * AT91PS_TDES; + +/* -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- */ +#define AT91C_TDES_START ( ( unsigned int ) 0x1 << 0 ) /* (TDES) Starts Processing */ +#define AT91C_TDES_SWRST ( ( unsigned int ) 0x1 << 8 ) /* (TDES) Software Reset */ +/* -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- */ +#define AT91C_TDES_CIPHER ( ( unsigned int ) 0x1 << 0 ) /* (TDES) Processing Mode */ +#define AT91C_TDES_TDESMOD ( ( unsigned int ) 0x1 << 1 ) /* (TDES) Single or Triple DES Mode */ +#define AT91C_TDES_KEYMOD ( ( unsigned int ) 0x1 << 4 ) /* (TDES) Key Mode */ +#define AT91C_TDES_SMOD ( ( unsigned int ) 0x3 << 8 ) /* (TDES) Start Mode */ +#define AT91C_TDES_SMOD_MANUAL ( ( unsigned int ) 0x0 << 8 ) /* (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. */ +#define AT91C_TDES_SMOD_AUTO ( ( unsigned int ) 0x1 << 8 ) /* (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). */ +#define AT91C_TDES_SMOD_PDC ( ( unsigned int ) 0x2 << 8 ) /* (TDES) PDC Mode (cf datasheet). */ +#define AT91C_TDES_OPMOD ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Operation Mode */ +#define AT91C_TDES_OPMOD_ECB ( ( unsigned int ) 0x0 << 12 ) /* (TDES) ECB Electronic CodeBook mode. */ +#define AT91C_TDES_OPMOD_CBC ( ( unsigned int ) 0x1 << 12 ) /* (TDES) CBC Cipher Block Chaining mode. */ +#define AT91C_TDES_OPMOD_OFB ( ( unsigned int ) 0x2 << 12 ) /* (TDES) OFB Output Feedback mode. */ +#define AT91C_TDES_OPMOD_CFB ( ( unsigned int ) 0x3 << 12 ) /* (TDES) CFB Cipher Feedback mode. */ +#define AT91C_TDES_LOD ( ( unsigned int ) 0x1 << 15 ) /* (TDES) Last Output Data Mode */ +#define AT91C_TDES_CFBS ( ( unsigned int ) 0x3 << 16 ) /* (TDES) Cipher Feedback Data Size */ +#define AT91C_TDES_CFBS_64_BIT ( ( unsigned int ) 0x0 << 16 ) /* (TDES) 64-bit. */ +#define AT91C_TDES_CFBS_32_BIT ( ( unsigned int ) 0x1 << 16 ) /* (TDES) 32-bit. */ +#define AT91C_TDES_CFBS_16_BIT ( ( unsigned int ) 0x2 << 16 ) /* (TDES) 16-bit. */ +#define AT91C_TDES_CFBS_8_BIT ( ( unsigned int ) 0x3 << 16 ) /* (TDES) 8-bit. */ +/* -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- */ +#define AT91C_TDES_DATRDY ( ( unsigned int ) 0x1 << 0 ) /* (TDES) DATRDY */ +#define AT91C_TDES_ENDRX ( ( unsigned int ) 0x1 << 1 ) /* (TDES) PDC Read Buffer End */ +#define AT91C_TDES_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (TDES) PDC Write Buffer End */ +#define AT91C_TDES_RXBUFF ( ( unsigned int ) 0x1 << 3 ) /* (TDES) PDC Read Buffer Full */ +#define AT91C_TDES_TXBUFE ( ( unsigned int ) 0x1 << 4 ) /* (TDES) PDC Write Buffer Empty */ +#define AT91C_TDES_URAD ( ( unsigned int ) 0x1 << 8 ) /* (TDES) Unspecified Register Access Detection */ +/* -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- */ +/* -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- */ +/* -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- */ +#define AT91C_TDES_URAT ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Unspecified Register Access Type Status */ +#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ( ( unsigned int ) 0x0 << 12 ) /* (TDES) Input data register written during the data processing in PDC mode. */ +#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ( ( unsigned int ) 0x1 << 12 ) /* (TDES) Output data register read during the data processing. */ +#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ( ( unsigned int ) 0x2 << 12 ) /* (TDES) Mode register written during the data processing. */ +#define AT91C_TDES_URAT_WO_REG_READ ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Write-only register read access. */ + +/* ***************************************************************************** */ +/* REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 */ +/* ***************************************************************************** */ +/* ========== Register definition for SYS peripheral ========== */ +/* ========== Register definition for AIC peripheral ========== */ +#define AT91C_AIC_IVR ( ( AT91_REG * ) 0xFFFFF100 ) /* (AIC) IRQ Vector Register */ +#define AT91C_AIC_SMR ( ( AT91_REG * ) 0xFFFFF000 ) /* (AIC) Source Mode Register */ +#define AT91C_AIC_FVR ( ( AT91_REG * ) 0xFFFFF104 ) /* (AIC) FIQ Vector Register */ +#define AT91C_AIC_DCR ( ( AT91_REG * ) 0xFFFFF138 ) /* (AIC) Debug Control Register (Protect) */ +#define AT91C_AIC_EOICR ( ( AT91_REG * ) 0xFFFFF130 ) /* (AIC) End of Interrupt Command Register */ +#define AT91C_AIC_SVR ( ( AT91_REG * ) 0xFFFFF080 ) /* (AIC) Source Vector Register */ +#define AT91C_AIC_FFSR ( ( AT91_REG * ) 0xFFFFF148 ) /* (AIC) Fast Forcing Status Register */ +#define AT91C_AIC_ICCR ( ( AT91_REG * ) 0xFFFFF128 ) /* (AIC) Interrupt Clear Command Register */ +#define AT91C_AIC_ISR ( ( AT91_REG * ) 0xFFFFF108 ) /* (AIC) Interrupt Status Register */ +#define AT91C_AIC_IMR ( ( AT91_REG * ) 0xFFFFF110 ) /* (AIC) Interrupt Mask Register */ +#define AT91C_AIC_IPR ( ( AT91_REG * ) 0xFFFFF10C ) /* (AIC) Interrupt Pending Register */ +#define AT91C_AIC_FFER ( ( AT91_REG * ) 0xFFFFF140 ) /* (AIC) Fast Forcing Enable Register */ +#define AT91C_AIC_IECR ( ( AT91_REG * ) 0xFFFFF120 ) /* (AIC) Interrupt Enable Command Register */ +#define AT91C_AIC_ISCR ( ( AT91_REG * ) 0xFFFFF12C ) /* (AIC) Interrupt Set Command Register */ +#define AT91C_AIC_FFDR ( ( AT91_REG * ) 0xFFFFF144 ) /* (AIC) Fast Forcing Disable Register */ +#define AT91C_AIC_CISR ( ( AT91_REG * ) 0xFFFFF114 ) /* (AIC) Core Interrupt Status Register */ +#define AT91C_AIC_IDCR ( ( AT91_REG * ) 0xFFFFF124 ) /* (AIC) Interrupt Disable Command Register */ +#define AT91C_AIC_SPU ( ( AT91_REG * ) 0xFFFFF134 ) /* (AIC) Spurious Vector Register */ +/* ========== Register definition for PDC_DBGU peripheral ========== */ +#define AT91C_DBGU_TCR ( ( AT91_REG * ) 0xFFFFF30C ) /* (PDC_DBGU) Transmit Counter Register */ +#define AT91C_DBGU_RNPR ( ( AT91_REG * ) 0xFFFFF310 ) /* (PDC_DBGU) Receive Next Pointer Register */ +#define AT91C_DBGU_TNPR ( ( AT91_REG * ) 0xFFFFF318 ) /* (PDC_DBGU) Transmit Next Pointer Register */ +#define AT91C_DBGU_TPR ( ( AT91_REG * ) 0xFFFFF308 ) /* (PDC_DBGU) Transmit Pointer Register */ +#define AT91C_DBGU_RPR ( ( AT91_REG * ) 0xFFFFF300 ) /* (PDC_DBGU) Receive Pointer Register */ +#define AT91C_DBGU_RCR ( ( AT91_REG * ) 0xFFFFF304 ) /* (PDC_DBGU) Receive Counter Register */ +#define AT91C_DBGU_RNCR ( ( AT91_REG * ) 0xFFFFF314 ) /* (PDC_DBGU) Receive Next Counter Register */ +#define AT91C_DBGU_PTCR ( ( AT91_REG * ) 0xFFFFF320 ) /* (PDC_DBGU) PDC Transfer Control Register */ +#define AT91C_DBGU_PTSR ( ( AT91_REG * ) 0xFFFFF324 ) /* (PDC_DBGU) PDC Transfer Status Register */ +#define AT91C_DBGU_TNCR ( ( AT91_REG * ) 0xFFFFF31C ) /* (PDC_DBGU) Transmit Next Counter Register */ +/* ========== Register definition for DBGU peripheral ========== */ +#define AT91C_DBGU_EXID ( ( AT91_REG * ) 0xFFFFF244 ) /* (DBGU) Chip ID Extension Register */ +#define AT91C_DBGU_BRGR ( ( AT91_REG * ) 0xFFFFF220 ) /* (DBGU) Baud Rate Generator Register */ +#define AT91C_DBGU_IDR ( ( AT91_REG * ) 0xFFFFF20C ) /* (DBGU) Interrupt Disable Register */ +#define AT91C_DBGU_CSR ( ( AT91_REG * ) 0xFFFFF214 ) /* (DBGU) Channel Status Register */ +#define AT91C_DBGU_CIDR ( ( AT91_REG * ) 0xFFFFF240 ) /* (DBGU) Chip ID Register */ +#define AT91C_DBGU_MR ( ( AT91_REG * ) 0xFFFFF204 ) /* (DBGU) Mode Register */ +#define AT91C_DBGU_IMR ( ( AT91_REG * ) 0xFFFFF210 ) /* (DBGU) Interrupt Mask Register */ +#define AT91C_DBGU_CR ( ( AT91_REG * ) 0xFFFFF200 ) /* (DBGU) Control Register */ +#define AT91C_DBGU_FNTR ( ( AT91_REG * ) 0xFFFFF248 ) /* (DBGU) Force NTRST Register */ +#define AT91C_DBGU_THR ( ( AT91_REG * ) 0xFFFFF21C ) /* (DBGU) Transmitter Holding Register */ +#define AT91C_DBGU_RHR ( ( AT91_REG * ) 0xFFFFF218 ) /* (DBGU) Receiver Holding Register */ +#define AT91C_DBGU_IER ( ( AT91_REG * ) 0xFFFFF208 ) /* (DBGU) Interrupt Enable Register */ +/* ========== Register definition for PIOA peripheral ========== */ +#define AT91C_PIOA_ODR ( ( AT91_REG * ) 0xFFFFF414 ) /* (PIOA) Output Disable Registerr */ +#define AT91C_PIOA_SODR ( ( AT91_REG * ) 0xFFFFF430 ) /* (PIOA) Set Output Data Register */ +#define AT91C_PIOA_ISR ( ( AT91_REG * ) 0xFFFFF44C ) /* (PIOA) Interrupt Status Register */ +#define AT91C_PIOA_ABSR ( ( AT91_REG * ) 0xFFFFF478 ) /* (PIOA) AB Select Status Register */ +#define AT91C_PIOA_IER ( ( AT91_REG * ) 0xFFFFF440 ) /* (PIOA) Interrupt Enable Register */ +#define AT91C_PIOA_PPUDR ( ( AT91_REG * ) 0xFFFFF460 ) /* (PIOA) Pull-up Disable Register */ +#define AT91C_PIOA_IMR ( ( AT91_REG * ) 0xFFFFF448 ) /* (PIOA) Interrupt Mask Register */ +#define AT91C_PIOA_PER ( ( AT91_REG * ) 0xFFFFF400 ) /* (PIOA) PIO Enable Register */ +#define AT91C_PIOA_IFDR ( ( AT91_REG * ) 0xFFFFF424 ) /* (PIOA) Input Filter Disable Register */ +#define AT91C_PIOA_OWDR ( ( AT91_REG * ) 0xFFFFF4A4 ) /* (PIOA) Output Write Disable Register */ +#define AT91C_PIOA_MDSR ( ( AT91_REG * ) 0xFFFFF458 ) /* (PIOA) Multi-driver Status Register */ +#define AT91C_PIOA_IDR ( ( AT91_REG * ) 0xFFFFF444 ) /* (PIOA) Interrupt Disable Register */ +#define AT91C_PIOA_ODSR ( ( AT91_REG * ) 0xFFFFF438 ) /* (PIOA) Output Data Status Register */ +#define AT91C_PIOA_PPUSR ( ( AT91_REG * ) 0xFFFFF468 ) /* (PIOA) Pull-up Status Register */ +#define AT91C_PIOA_OWSR ( ( AT91_REG * ) 0xFFFFF4A8 ) /* (PIOA) Output Write Status Register */ +#define AT91C_PIOA_BSR ( ( AT91_REG * ) 0xFFFFF474 ) /* (PIOA) Select B Register */ +#define AT91C_PIOA_OWER ( ( AT91_REG * ) 0xFFFFF4A0 ) /* (PIOA) Output Write Enable Register */ +#define AT91C_PIOA_IFER ( ( AT91_REG * ) 0xFFFFF420 ) /* (PIOA) Input Filter Enable Register */ +#define AT91C_PIOA_PDSR ( ( AT91_REG * ) 0xFFFFF43C ) /* (PIOA) Pin Data Status Register */ +#define AT91C_PIOA_PPUER ( ( AT91_REG * ) 0xFFFFF464 ) /* (PIOA) Pull-up Enable Register */ +#define AT91C_PIOA_OSR ( ( AT91_REG * ) 0xFFFFF418 ) /* (PIOA) Output Status Register */ +#define AT91C_PIOA_ASR ( ( AT91_REG * ) 0xFFFFF470 ) /* (PIOA) Select A Register */ +#define AT91C_PIOA_MDDR ( ( AT91_REG * ) 0xFFFFF454 ) /* (PIOA) Multi-driver Disable Register */ +#define AT91C_PIOA_CODR ( ( AT91_REG * ) 0xFFFFF434 ) /* (PIOA) Clear Output Data Register */ +#define AT91C_PIOA_MDER ( ( AT91_REG * ) 0xFFFFF450 ) /* (PIOA) Multi-driver Enable Register */ +#define AT91C_PIOA_PDR ( ( AT91_REG * ) 0xFFFFF404 ) /* (PIOA) PIO Disable Register */ +#define AT91C_PIOA_IFSR ( ( AT91_REG * ) 0xFFFFF428 ) /* (PIOA) Input Filter Status Register */ +#define AT91C_PIOA_OER ( ( AT91_REG * ) 0xFFFFF410 ) /* (PIOA) Output Enable Register */ +#define AT91C_PIOA_PSR ( ( AT91_REG * ) 0xFFFFF408 ) /* (PIOA) PIO Status Register */ +/* ========== Register definition for PIOB peripheral ========== */ +#define AT91C_PIOB_OWDR ( ( AT91_REG * ) 0xFFFFF6A4 ) /* (PIOB) Output Write Disable Register */ +#define AT91C_PIOB_MDER ( ( AT91_REG * ) 0xFFFFF650 ) /* (PIOB) Multi-driver Enable Register */ +#define AT91C_PIOB_PPUSR ( ( AT91_REG * ) 0xFFFFF668 ) /* (PIOB) Pull-up Status Register */ +#define AT91C_PIOB_IMR ( ( AT91_REG * ) 0xFFFFF648 ) /* (PIOB) Interrupt Mask Register */ +#define AT91C_PIOB_ASR ( ( AT91_REG * ) 0xFFFFF670 ) /* (PIOB) Select A Register */ +#define AT91C_PIOB_PPUDR ( ( AT91_REG * ) 0xFFFFF660 ) /* (PIOB) Pull-up Disable Register */ +#define AT91C_PIOB_PSR ( ( AT91_REG * ) 0xFFFFF608 ) /* (PIOB) PIO Status Register */ +#define AT91C_PIOB_IER ( ( AT91_REG * ) 0xFFFFF640 ) /* (PIOB) Interrupt Enable Register */ +#define AT91C_PIOB_CODR ( ( AT91_REG * ) 0xFFFFF634 ) /* (PIOB) Clear Output Data Register */ +#define AT91C_PIOB_OWER ( ( AT91_REG * ) 0xFFFFF6A0 ) /* (PIOB) Output Write Enable Register */ +#define AT91C_PIOB_ABSR ( ( AT91_REG * ) 0xFFFFF678 ) /* (PIOB) AB Select Status Register */ +#define AT91C_PIOB_IFDR ( ( AT91_REG * ) 0xFFFFF624 ) /* (PIOB) Input Filter Disable Register */ +#define AT91C_PIOB_PDSR ( ( AT91_REG * ) 0xFFFFF63C ) /* (PIOB) Pin Data Status Register */ +#define AT91C_PIOB_IDR ( ( AT91_REG * ) 0xFFFFF644 ) /* (PIOB) Interrupt Disable Register */ +#define AT91C_PIOB_OWSR ( ( AT91_REG * ) 0xFFFFF6A8 ) /* (PIOB) Output Write Status Register */ +#define AT91C_PIOB_PDR ( ( AT91_REG * ) 0xFFFFF604 ) /* (PIOB) PIO Disable Register */ +#define AT91C_PIOB_ODR ( ( AT91_REG * ) 0xFFFFF614 ) /* (PIOB) Output Disable Registerr */ +#define AT91C_PIOB_IFSR ( ( AT91_REG * ) 0xFFFFF628 ) /* (PIOB) Input Filter Status Register */ +#define AT91C_PIOB_PPUER ( ( AT91_REG * ) 0xFFFFF664 ) /* (PIOB) Pull-up Enable Register */ +#define AT91C_PIOB_SODR ( ( AT91_REG * ) 0xFFFFF630 ) /* (PIOB) Set Output Data Register */ +#define AT91C_PIOB_ISR ( ( AT91_REG * ) 0xFFFFF64C ) /* (PIOB) Interrupt Status Register */ +#define AT91C_PIOB_ODSR ( ( AT91_REG * ) 0xFFFFF638 ) /* (PIOB) Output Data Status Register */ +#define AT91C_PIOB_OSR ( ( AT91_REG * ) 0xFFFFF618 ) /* (PIOB) Output Status Register */ +#define AT91C_PIOB_MDSR ( ( AT91_REG * ) 0xFFFFF658 ) /* (PIOB) Multi-driver Status Register */ +#define AT91C_PIOB_IFER ( ( AT91_REG * ) 0xFFFFF620 ) /* (PIOB) Input Filter Enable Register */ +#define AT91C_PIOB_BSR ( ( AT91_REG * ) 0xFFFFF674 ) /* (PIOB) Select B Register */ +#define AT91C_PIOB_MDDR ( ( AT91_REG * ) 0xFFFFF654 ) /* (PIOB) Multi-driver Disable Register */ +#define AT91C_PIOB_OER ( ( AT91_REG * ) 0xFFFFF610 ) /* (PIOB) Output Enable Register */ +#define AT91C_PIOB_PER ( ( AT91_REG * ) 0xFFFFF600 ) /* (PIOB) PIO Enable Register */ +/* ========== Register definition for CKGR peripheral ========== */ +#define AT91C_CKGR_MOR ( ( AT91_REG * ) 0xFFFFFC20 ) /* (CKGR) Main Oscillator Register */ +#define AT91C_CKGR_PLLR ( ( AT91_REG * ) 0xFFFFFC2C ) /* (CKGR) PLL Register */ +#define AT91C_CKGR_MCFR ( ( AT91_REG * ) 0xFFFFFC24 ) /* (CKGR) Main Clock Frequency Register */ +/* ========== Register definition for PMC peripheral ========== */ +#define AT91C_PMC_IDR ( ( AT91_REG * ) 0xFFFFFC64 ) /* (PMC) Interrupt Disable Register */ +#define AT91C_PMC_MOR ( ( AT91_REG * ) 0xFFFFFC20 ) /* (PMC) Main Oscillator Register */ +#define AT91C_PMC_PLLR ( ( AT91_REG * ) 0xFFFFFC2C ) /* (PMC) PLL Register */ +#define AT91C_PMC_PCER ( ( AT91_REG * ) 0xFFFFFC10 ) /* (PMC) Peripheral Clock Enable Register */ +#define AT91C_PMC_PCKR ( ( AT91_REG * ) 0xFFFFFC40 ) /* (PMC) Programmable Clock Register */ +#define AT91C_PMC_MCKR ( ( AT91_REG * ) 0xFFFFFC30 ) /* (PMC) Master Clock Register */ +#define AT91C_PMC_SCDR ( ( AT91_REG * ) 0xFFFFFC04 ) /* (PMC) System Clock Disable Register */ +#define AT91C_PMC_PCDR ( ( AT91_REG * ) 0xFFFFFC14 ) /* (PMC) Peripheral Clock Disable Register */ +#define AT91C_PMC_SCSR ( ( AT91_REG * ) 0xFFFFFC08 ) /* (PMC) System Clock Status Register */ +#define AT91C_PMC_PCSR ( ( AT91_REG * ) 0xFFFFFC18 ) /* (PMC) Peripheral Clock Status Register */ +#define AT91C_PMC_MCFR ( ( AT91_REG * ) 0xFFFFFC24 ) /* (PMC) Main Clock Frequency Register */ +#define AT91C_PMC_SCER ( ( AT91_REG * ) 0xFFFFFC00 ) /* (PMC) System Clock Enable Register */ +#define AT91C_PMC_IMR ( ( AT91_REG * ) 0xFFFFFC6C ) /* (PMC) Interrupt Mask Register */ +#define AT91C_PMC_IER ( ( AT91_REG * ) 0xFFFFFC60 ) /* (PMC) Interrupt Enable Register */ +#define AT91C_PMC_SR ( ( AT91_REG * ) 0xFFFFFC68 ) /* (PMC) Status Register */ +/* ========== Register definition for RSTC peripheral ========== */ +#define AT91C_RSTC_RCR ( ( AT91_REG * ) 0xFFFFFD00 ) /* (RSTC) Reset Control Register */ +#define AT91C_RSTC_RMR ( ( AT91_REG * ) 0xFFFFFD08 ) /* (RSTC) Reset Mode Register */ +#define AT91C_RSTC_RSR ( ( AT91_REG * ) 0xFFFFFD04 ) /* (RSTC) Reset Status Register */ +/* ========== Register definition for RTTC peripheral ========== */ +#define AT91C_RTTC_RTSR ( ( AT91_REG * ) 0xFFFFFD2C ) /* (RTTC) Real-time Status Register */ +#define AT91C_RTTC_RTMR ( ( AT91_REG * ) 0xFFFFFD20 ) /* (RTTC) Real-time Mode Register */ +#define AT91C_RTTC_RTVR ( ( AT91_REG * ) 0xFFFFFD28 ) /* (RTTC) Real-time Value Register */ +#define AT91C_RTTC_RTAR ( ( AT91_REG * ) 0xFFFFFD24 ) /* (RTTC) Real-time Alarm Register */ +/* ========== Register definition for PITC peripheral ========== */ +#define AT91C_PITC_PIVR ( ( AT91_REG * ) 0xFFFFFD38 ) /* (PITC) Period Interval Value Register */ +#define AT91C_PITC_PISR ( ( AT91_REG * ) 0xFFFFFD34 ) /* (PITC) Period Interval Status Register */ +#define AT91C_PITC_PIIR ( ( AT91_REG * ) 0xFFFFFD3C ) /* (PITC) Period Interval Image Register */ +#define AT91C_PITC_PIMR ( ( AT91_REG * ) 0xFFFFFD30 ) /* (PITC) Period Interval Mode Register */ +/* ========== Register definition for WDTC peripheral ========== */ +#define AT91C_WDTC_WDCR ( ( AT91_REG * ) 0xFFFFFD40 ) /* (WDTC) Watchdog Control Register */ +#define AT91C_WDTC_WDSR ( ( AT91_REG * ) 0xFFFFFD48 ) /* (WDTC) Watchdog Status Register */ +#define AT91C_WDTC_WDMR ( ( AT91_REG * ) 0xFFFFFD44 ) /* (WDTC) Watchdog Mode Register */ +/* ========== Register definition for VREG peripheral ========== */ +#define AT91C_VREG_MR ( ( AT91_REG * ) 0xFFFFFD60 ) /* (VREG) Voltage Regulator Mode Register */ +/* ========== Register definition for MC peripheral ========== */ +#define AT91C_MC_ASR ( ( AT91_REG * ) 0xFFFFFF04 ) /* (MC) MC Abort Status Register */ +#define AT91C_MC_RCR ( ( AT91_REG * ) 0xFFFFFF00 ) /* (MC) MC Remap Control Register */ +#define AT91C_MC_FCR ( ( AT91_REG * ) 0xFFFFFF64 ) /* (MC) MC Flash Command Register */ +#define AT91C_MC_AASR ( ( AT91_REG * ) 0xFFFFFF08 ) /* (MC) MC Abort Address Status Register */ +#define AT91C_MC_FSR ( ( AT91_REG * ) 0xFFFFFF68 ) /* (MC) MC Flash Status Register */ +#define AT91C_MC_FMR ( ( AT91_REG * ) 0xFFFFFF60 ) /* (MC) MC Flash Mode Register */ +/* ========== Register definition for PDC_SPI1 peripheral ========== */ +#define AT91C_SPI1_PTCR ( ( AT91_REG * ) 0xFFFE4120 ) /* (PDC_SPI1) PDC Transfer Control Register */ +#define AT91C_SPI1_RPR ( ( AT91_REG * ) 0xFFFE4100 ) /* (PDC_SPI1) Receive Pointer Register */ +#define AT91C_SPI1_TNCR ( ( AT91_REG * ) 0xFFFE411C ) /* (PDC_SPI1) Transmit Next Counter Register */ +#define AT91C_SPI1_TPR ( ( AT91_REG * ) 0xFFFE4108 ) /* (PDC_SPI1) Transmit Pointer Register */ +#define AT91C_SPI1_TNPR ( ( AT91_REG * ) 0xFFFE4118 ) /* (PDC_SPI1) Transmit Next Pointer Register */ +#define AT91C_SPI1_TCR ( ( AT91_REG * ) 0xFFFE410C ) /* (PDC_SPI1) Transmit Counter Register */ +#define AT91C_SPI1_RCR ( ( AT91_REG * ) 0xFFFE4104 ) /* (PDC_SPI1) Receive Counter Register */ +#define AT91C_SPI1_RNPR ( ( AT91_REG * ) 0xFFFE4110 ) /* (PDC_SPI1) Receive Next Pointer Register */ +#define AT91C_SPI1_RNCR ( ( AT91_REG * ) 0xFFFE4114 ) /* (PDC_SPI1) Receive Next Counter Register */ +#define AT91C_SPI1_PTSR ( ( AT91_REG * ) 0xFFFE4124 ) /* (PDC_SPI1) PDC Transfer Status Register */ +/* ========== Register definition for SPI1 peripheral ========== */ +#define AT91C_SPI1_IMR ( ( AT91_REG * ) 0xFFFE401C ) /* (SPI1) Interrupt Mask Register */ +#define AT91C_SPI1_IER ( ( AT91_REG * ) 0xFFFE4014 ) /* (SPI1) Interrupt Enable Register */ +#define AT91C_SPI1_MR ( ( AT91_REG * ) 0xFFFE4004 ) /* (SPI1) Mode Register */ +#define AT91C_SPI1_RDR ( ( AT91_REG * ) 0xFFFE4008 ) /* (SPI1) Receive Data Register */ +#define AT91C_SPI1_IDR ( ( AT91_REG * ) 0xFFFE4018 ) /* (SPI1) Interrupt Disable Register */ +#define AT91C_SPI1_SR ( ( AT91_REG * ) 0xFFFE4010 ) /* (SPI1) Status Register */ +#define AT91C_SPI1_TDR ( ( AT91_REG * ) 0xFFFE400C ) /* (SPI1) Transmit Data Register */ +#define AT91C_SPI1_CR ( ( AT91_REG * ) 0xFFFE4000 ) /* (SPI1) Control Register */ +#define AT91C_SPI1_CSR ( ( AT91_REG * ) 0xFFFE4030 ) /* (SPI1) Chip Select Register */ +/* ========== Register definition for PDC_SPI0 peripheral ========== */ +#define AT91C_SPI0_PTCR ( ( AT91_REG * ) 0xFFFE0120 ) /* (PDC_SPI0) PDC Transfer Control Register */ +#define AT91C_SPI0_TPR ( ( AT91_REG * ) 0xFFFE0108 ) /* (PDC_SPI0) Transmit Pointer Register */ +#define AT91C_SPI0_TCR ( ( AT91_REG * ) 0xFFFE010C ) /* (PDC_SPI0) Transmit Counter Register */ +#define AT91C_SPI0_RCR ( ( AT91_REG * ) 0xFFFE0104 ) /* (PDC_SPI0) Receive Counter Register */ +#define AT91C_SPI0_PTSR ( ( AT91_REG * ) 0xFFFE0124 ) /* (PDC_SPI0) PDC Transfer Status Register */ +#define AT91C_SPI0_RNPR ( ( AT91_REG * ) 0xFFFE0110 ) /* (PDC_SPI0) Receive Next Pointer Register */ +#define AT91C_SPI0_RPR ( ( AT91_REG * ) 0xFFFE0100 ) /* (PDC_SPI0) Receive Pointer Register */ +#define AT91C_SPI0_TNCR ( ( AT91_REG * ) 0xFFFE011C ) /* (PDC_SPI0) Transmit Next Counter Register */ +#define AT91C_SPI0_RNCR ( ( AT91_REG * ) 0xFFFE0114 ) /* (PDC_SPI0) Receive Next Counter Register */ +#define AT91C_SPI0_TNPR ( ( AT91_REG * ) 0xFFFE0118 ) /* (PDC_SPI0) Transmit Next Pointer Register */ +/* ========== Register definition for SPI0 peripheral ========== */ +#define AT91C_SPI0_IER ( ( AT91_REG * ) 0xFFFE0014 ) /* (SPI0) Interrupt Enable Register */ +#define AT91C_SPI0_SR ( ( AT91_REG * ) 0xFFFE0010 ) /* (SPI0) Status Register */ +#define AT91C_SPI0_IDR ( ( AT91_REG * ) 0xFFFE0018 ) /* (SPI0) Interrupt Disable Register */ +#define AT91C_SPI0_CR ( ( AT91_REG * ) 0xFFFE0000 ) /* (SPI0) Control Register */ +#define AT91C_SPI0_MR ( ( AT91_REG * ) 0xFFFE0004 ) /* (SPI0) Mode Register */ +#define AT91C_SPI0_IMR ( ( AT91_REG * ) 0xFFFE001C ) /* (SPI0) Interrupt Mask Register */ +#define AT91C_SPI0_TDR ( ( AT91_REG * ) 0xFFFE000C ) /* (SPI0) Transmit Data Register */ +#define AT91C_SPI0_RDR ( ( AT91_REG * ) 0xFFFE0008 ) /* (SPI0) Receive Data Register */ +#define AT91C_SPI0_CSR ( ( AT91_REG * ) 0xFFFE0030 ) /* (SPI0) Chip Select Register */ +/* ========== Register definition for PDC_US1 peripheral ========== */ +#define AT91C_US1_RNCR ( ( AT91_REG * ) 0xFFFC4114 ) /* (PDC_US1) Receive Next Counter Register */ +#define AT91C_US1_PTCR ( ( AT91_REG * ) 0xFFFC4120 ) /* (PDC_US1) PDC Transfer Control Register */ +#define AT91C_US1_TCR ( ( AT91_REG * ) 0xFFFC410C ) /* (PDC_US1) Transmit Counter Register */ +#define AT91C_US1_PTSR ( ( AT91_REG * ) 0xFFFC4124 ) /* (PDC_US1) PDC Transfer Status Register */ +#define AT91C_US1_TNPR ( ( AT91_REG * ) 0xFFFC4118 ) /* (PDC_US1) Transmit Next Pointer Register */ +#define AT91C_US1_RCR ( ( AT91_REG * ) 0xFFFC4104 ) /* (PDC_US1) Receive Counter Register */ +#define AT91C_US1_RNPR ( ( AT91_REG * ) 0xFFFC4110 ) /* (PDC_US1) Receive Next Pointer Register */ +#define AT91C_US1_RPR ( ( AT91_REG * ) 0xFFFC4100 ) /* (PDC_US1) Receive Pointer Register */ +#define AT91C_US1_TNCR ( ( AT91_REG * ) 0xFFFC411C ) /* (PDC_US1) Transmit Next Counter Register */ +#define AT91C_US1_TPR ( ( AT91_REG * ) 0xFFFC4108 ) /* (PDC_US1) Transmit Pointer Register */ +/* ========== Register definition for US1 peripheral ========== */ +#define AT91C_US1_IF ( ( AT91_REG * ) 0xFFFC404C ) /* (US1) IRDA_FILTER Register */ +#define AT91C_US1_NER ( ( AT91_REG * ) 0xFFFC4044 ) /* (US1) Nb Errors Register */ +#define AT91C_US1_RTOR ( ( AT91_REG * ) 0xFFFC4024 ) /* (US1) Receiver Time-out Register */ +#define AT91C_US1_CSR ( ( AT91_REG * ) 0xFFFC4014 ) /* (US1) Channel Status Register */ +#define AT91C_US1_IDR ( ( AT91_REG * ) 0xFFFC400C ) /* (US1) Interrupt Disable Register */ +#define AT91C_US1_IER ( ( AT91_REG * ) 0xFFFC4008 ) /* (US1) Interrupt Enable Register */ +#define AT91C_US1_THR ( ( AT91_REG * ) 0xFFFC401C ) /* (US1) Transmitter Holding Register */ +#define AT91C_US1_TTGR ( ( AT91_REG * ) 0xFFFC4028 ) /* (US1) Transmitter Time-guard Register */ +#define AT91C_US1_RHR ( ( AT91_REG * ) 0xFFFC4018 ) /* (US1) Receiver Holding Register */ +#define AT91C_US1_BRGR ( ( AT91_REG * ) 0xFFFC4020 ) /* (US1) Baud Rate Generator Register */ +#define AT91C_US1_IMR ( ( AT91_REG * ) 0xFFFC4010 ) /* (US1) Interrupt Mask Register */ +#define AT91C_US1_FIDI ( ( AT91_REG * ) 0xFFFC4040 ) /* (US1) FI_DI_Ratio Register */ +#define AT91C_US1_CR ( ( AT91_REG * ) 0xFFFC4000 ) /* (US1) Control Register */ +#define AT91C_US1_MR ( ( AT91_REG * ) 0xFFFC4004 ) /* (US1) Mode Register */ +/* ========== Register definition for PDC_US0 peripheral ========== */ +#define AT91C_US0_TNPR ( ( AT91_REG * ) 0xFFFC0118 ) /* (PDC_US0) Transmit Next Pointer Register */ +#define AT91C_US0_RNPR ( ( AT91_REG * ) 0xFFFC0110 ) /* (PDC_US0) Receive Next Pointer Register */ +#define AT91C_US0_TCR ( ( AT91_REG * ) 0xFFFC010C ) /* (PDC_US0) Transmit Counter Register */ +#define AT91C_US0_PTCR ( ( AT91_REG * ) 0xFFFC0120 ) /* (PDC_US0) PDC Transfer Control Register */ +#define AT91C_US0_PTSR ( ( AT91_REG * ) 0xFFFC0124 ) /* (PDC_US0) PDC Transfer Status Register */ +#define AT91C_US0_TNCR ( ( AT91_REG * ) 0xFFFC011C ) /* (PDC_US0) Transmit Next Counter Register */ +#define AT91C_US0_TPR ( ( AT91_REG * ) 0xFFFC0108 ) /* (PDC_US0) Transmit Pointer Register */ +#define AT91C_US0_RCR ( ( AT91_REG * ) 0xFFFC0104 ) /* (PDC_US0) Receive Counter Register */ +#define AT91C_US0_RPR ( ( AT91_REG * ) 0xFFFC0100 ) /* (PDC_US0) Receive Pointer Register */ +#define AT91C_US0_RNCR ( ( AT91_REG * ) 0xFFFC0114 ) /* (PDC_US0) Receive Next Counter Register */ +/* ========== Register definition for US0 peripheral ========== */ +#define AT91C_US0_BRGR ( ( AT91_REG * ) 0xFFFC0020 ) /* (US0) Baud Rate Generator Register */ +#define AT91C_US0_NER ( ( AT91_REG * ) 0xFFFC0044 ) /* (US0) Nb Errors Register */ +#define AT91C_US0_CR ( ( AT91_REG * ) 0xFFFC0000 ) /* (US0) Control Register */ +#define AT91C_US0_IMR ( ( AT91_REG * ) 0xFFFC0010 ) /* (US0) Interrupt Mask Register */ +#define AT91C_US0_FIDI ( ( AT91_REG * ) 0xFFFC0040 ) /* (US0) FI_DI_Ratio Register */ +#define AT91C_US0_TTGR ( ( AT91_REG * ) 0xFFFC0028 ) /* (US0) Transmitter Time-guard Register */ +#define AT91C_US0_MR ( ( AT91_REG * ) 0xFFFC0004 ) /* (US0) Mode Register */ +#define AT91C_US0_RTOR ( ( AT91_REG * ) 0xFFFC0024 ) /* (US0) Receiver Time-out Register */ +#define AT91C_US0_CSR ( ( AT91_REG * ) 0xFFFC0014 ) /* (US0) Channel Status Register */ +#define AT91C_US0_RHR ( ( AT91_REG * ) 0xFFFC0018 ) /* (US0) Receiver Holding Register */ +#define AT91C_US0_IDR ( ( AT91_REG * ) 0xFFFC000C ) /* (US0) Interrupt Disable Register */ +#define AT91C_US0_THR ( ( AT91_REG * ) 0xFFFC001C ) /* (US0) Transmitter Holding Register */ +#define AT91C_US0_IF ( ( AT91_REG * ) 0xFFFC004C ) /* (US0) IRDA_FILTER Register */ +#define AT91C_US0_IER ( ( AT91_REG * ) 0xFFFC0008 ) /* (US0) Interrupt Enable Register */ +/* ========== Register definition for PDC_SSC peripheral ========== */ +#define AT91C_SSC_TNCR ( ( AT91_REG * ) 0xFFFD411C ) /* (PDC_SSC) Transmit Next Counter Register */ +#define AT91C_SSC_RPR ( ( AT91_REG * ) 0xFFFD4100 ) /* (PDC_SSC) Receive Pointer Register */ +#define AT91C_SSC_RNCR ( ( AT91_REG * ) 0xFFFD4114 ) /* (PDC_SSC) Receive Next Counter Register */ +#define AT91C_SSC_TPR ( ( AT91_REG * ) 0xFFFD4108 ) /* (PDC_SSC) Transmit Pointer Register */ +#define AT91C_SSC_PTCR ( ( AT91_REG * ) 0xFFFD4120 ) /* (PDC_SSC) PDC Transfer Control Register */ +#define AT91C_SSC_TCR ( ( AT91_REG * ) 0xFFFD410C ) /* (PDC_SSC) Transmit Counter Register */ +#define AT91C_SSC_RCR ( ( AT91_REG * ) 0xFFFD4104 ) /* (PDC_SSC) Receive Counter Register */ +#define AT91C_SSC_RNPR ( ( AT91_REG * ) 0xFFFD4110 ) /* (PDC_SSC) Receive Next Pointer Register */ +#define AT91C_SSC_TNPR ( ( AT91_REG * ) 0xFFFD4118 ) /* (PDC_SSC) Transmit Next Pointer Register */ +#define AT91C_SSC_PTSR ( ( AT91_REG * ) 0xFFFD4124 ) /* (PDC_SSC) PDC Transfer Status Register */ +/* ========== Register definition for SSC peripheral ========== */ +#define AT91C_SSC_RHR ( ( AT91_REG * ) 0xFFFD4020 ) /* (SSC) Receive Holding Register */ +#define AT91C_SSC_RSHR ( ( AT91_REG * ) 0xFFFD4030 ) /* (SSC) Receive Sync Holding Register */ +#define AT91C_SSC_TFMR ( ( AT91_REG * ) 0xFFFD401C ) /* (SSC) Transmit Frame Mode Register */ +#define AT91C_SSC_IDR ( ( AT91_REG * ) 0xFFFD4048 ) /* (SSC) Interrupt Disable Register */ +#define AT91C_SSC_THR ( ( AT91_REG * ) 0xFFFD4024 ) /* (SSC) Transmit Holding Register */ +#define AT91C_SSC_RCMR ( ( AT91_REG * ) 0xFFFD4010 ) /* (SSC) Receive Clock ModeRegister */ +#define AT91C_SSC_IER ( ( AT91_REG * ) 0xFFFD4044 ) /* (SSC) Interrupt Enable Register */ +#define AT91C_SSC_TSHR ( ( AT91_REG * ) 0xFFFD4034 ) /* (SSC) Transmit Sync Holding Register */ +#define AT91C_SSC_SR ( ( AT91_REG * ) 0xFFFD4040 ) /* (SSC) Status Register */ +#define AT91C_SSC_CMR ( ( AT91_REG * ) 0xFFFD4004 ) /* (SSC) Clock Mode Register */ +#define AT91C_SSC_TCMR ( ( AT91_REG * ) 0xFFFD4018 ) /* (SSC) Transmit Clock Mode Register */ +#define AT91C_SSC_CR ( ( AT91_REG * ) 0xFFFD4000 ) /* (SSC) Control Register */ +#define AT91C_SSC_IMR ( ( AT91_REG * ) 0xFFFD404C ) /* (SSC) Interrupt Mask Register */ +#define AT91C_SSC_RFMR ( ( AT91_REG * ) 0xFFFD4014 ) /* (SSC) Receive Frame Mode Register */ +/* ========== Register definition for TWI peripheral ========== */ +#define AT91C_TWI_IER ( ( AT91_REG * ) 0xFFFB8024 ) /* (TWI) Interrupt Enable Register */ +#define AT91C_TWI_CR ( ( AT91_REG * ) 0xFFFB8000 ) /* (TWI) Control Register */ +#define AT91C_TWI_SR ( ( AT91_REG * ) 0xFFFB8020 ) /* (TWI) Status Register */ +#define AT91C_TWI_IMR ( ( AT91_REG * ) 0xFFFB802C ) /* (TWI) Interrupt Mask Register */ +#define AT91C_TWI_THR ( ( AT91_REG * ) 0xFFFB8034 ) /* (TWI) Transmit Holding Register */ +#define AT91C_TWI_IDR ( ( AT91_REG * ) 0xFFFB8028 ) /* (TWI) Interrupt Disable Register */ +#define AT91C_TWI_IADR ( ( AT91_REG * ) 0xFFFB800C ) /* (TWI) Internal Address Register */ +#define AT91C_TWI_MMR ( ( AT91_REG * ) 0xFFFB8004 ) /* (TWI) Master Mode Register */ +#define AT91C_TWI_CWGR ( ( AT91_REG * ) 0xFFFB8010 ) /* (TWI) Clock Waveform Generator Register */ +#define AT91C_TWI_RHR ( ( AT91_REG * ) 0xFFFB8030 ) /* (TWI) Receive Holding Register */ +/* ========== Register definition for PWMC_CH3 peripheral ========== */ +#define AT91C_PWMC_CH3_CUPDR ( ( AT91_REG * ) 0xFFFCC270 ) /* (PWMC_CH3) Channel Update Register */ +#define AT91C_PWMC_CH3_Reserved ( ( AT91_REG * ) 0xFFFCC274 ) /* (PWMC_CH3) Reserved */ +#define AT91C_PWMC_CH3_CPRDR ( ( AT91_REG * ) 0xFFFCC268 ) /* (PWMC_CH3) Channel Period Register */ +#define AT91C_PWMC_CH3_CDTYR ( ( AT91_REG * ) 0xFFFCC264 ) /* (PWMC_CH3) Channel Duty Cycle Register */ +#define AT91C_PWMC_CH3_CCNTR ( ( AT91_REG * ) 0xFFFCC26C ) /* (PWMC_CH3) Channel Counter Register */ +#define AT91C_PWMC_CH3_CMR ( ( AT91_REG * ) 0xFFFCC260 ) /* (PWMC_CH3) Channel Mode Register */ +/* ========== Register definition for PWMC_CH2 peripheral ========== */ +#define AT91C_PWMC_CH2_Reserved ( ( AT91_REG * ) 0xFFFCC254 ) /* (PWMC_CH2) Reserved */ +#define AT91C_PWMC_CH2_CMR ( ( AT91_REG * ) 0xFFFCC240 ) /* (PWMC_CH2) Channel Mode Register */ +#define AT91C_PWMC_CH2_CCNTR ( ( AT91_REG * ) 0xFFFCC24C ) /* (PWMC_CH2) Channel Counter Register */ +#define AT91C_PWMC_CH2_CPRDR ( ( AT91_REG * ) 0xFFFCC248 ) /* (PWMC_CH2) Channel Period Register */ +#define AT91C_PWMC_CH2_CUPDR ( ( AT91_REG * ) 0xFFFCC250 ) /* (PWMC_CH2) Channel Update Register */ +#define AT91C_PWMC_CH2_CDTYR ( ( AT91_REG * ) 0xFFFCC244 ) /* (PWMC_CH2) Channel Duty Cycle Register */ +/* ========== Register definition for PWMC_CH1 peripheral ========== */ +#define AT91C_PWMC_CH1_Reserved ( ( AT91_REG * ) 0xFFFCC234 ) /* (PWMC_CH1) Reserved */ +#define AT91C_PWMC_CH1_CUPDR ( ( AT91_REG * ) 0xFFFCC230 ) /* (PWMC_CH1) Channel Update Register */ +#define AT91C_PWMC_CH1_CPRDR ( ( AT91_REG * ) 0xFFFCC228 ) /* (PWMC_CH1) Channel Period Register */ +#define AT91C_PWMC_CH1_CCNTR ( ( AT91_REG * ) 0xFFFCC22C ) /* (PWMC_CH1) Channel Counter Register */ +#define AT91C_PWMC_CH1_CDTYR ( ( AT91_REG * ) 0xFFFCC224 ) /* (PWMC_CH1) Channel Duty Cycle Register */ +#define AT91C_PWMC_CH1_CMR ( ( AT91_REG * ) 0xFFFCC220 ) /* (PWMC_CH1) Channel Mode Register */ +/* ========== Register definition for PWMC_CH0 peripheral ========== */ +#define AT91C_PWMC_CH0_Reserved ( ( AT91_REG * ) 0xFFFCC214 ) /* (PWMC_CH0) Reserved */ +#define AT91C_PWMC_CH0_CPRDR ( ( AT91_REG * ) 0xFFFCC208 ) /* (PWMC_CH0) Channel Period Register */ +#define AT91C_PWMC_CH0_CDTYR ( ( AT91_REG * ) 0xFFFCC204 ) /* (PWMC_CH0) Channel Duty Cycle Register */ +#define AT91C_PWMC_CH0_CMR ( ( AT91_REG * ) 0xFFFCC200 ) /* (PWMC_CH0) Channel Mode Register */ +#define AT91C_PWMC_CH0_CUPDR ( ( AT91_REG * ) 0xFFFCC210 ) /* (PWMC_CH0) Channel Update Register */ +#define AT91C_PWMC_CH0_CCNTR ( ( AT91_REG * ) 0xFFFCC20C ) /* (PWMC_CH0) Channel Counter Register */ +/* ========== Register definition for PWMC peripheral ========== */ +#define AT91C_PWMC_IDR ( ( AT91_REG * ) 0xFFFCC014 ) /* (PWMC) PWMC Interrupt Disable Register */ +#define AT91C_PWMC_DIS ( ( AT91_REG * ) 0xFFFCC008 ) /* (PWMC) PWMC Disable Register */ +#define AT91C_PWMC_IER ( ( AT91_REG * ) 0xFFFCC010 ) /* (PWMC) PWMC Interrupt Enable Register */ +#define AT91C_PWMC_VR ( ( AT91_REG * ) 0xFFFCC0FC ) /* (PWMC) PWMC Version Register */ +#define AT91C_PWMC_ISR ( ( AT91_REG * ) 0xFFFCC01C ) /* (PWMC) PWMC Interrupt Status Register */ +#define AT91C_PWMC_SR ( ( AT91_REG * ) 0xFFFCC00C ) /* (PWMC) PWMC Status Register */ +#define AT91C_PWMC_IMR ( ( AT91_REG * ) 0xFFFCC018 ) /* (PWMC) PWMC Interrupt Mask Register */ +#define AT91C_PWMC_MR ( ( AT91_REG * ) 0xFFFCC000 ) /* (PWMC) PWMC Mode Register */ +#define AT91C_PWMC_ENA ( ( AT91_REG * ) 0xFFFCC004 ) /* (PWMC) PWMC Enable Register */ +/* ========== Register definition for UDP peripheral ========== */ +#define AT91C_UDP_IMR ( ( AT91_REG * ) 0xFFFB0018 ) /* (UDP) Interrupt Mask Register */ +#define AT91C_UDP_FADDR ( ( AT91_REG * ) 0xFFFB0008 ) /* (UDP) Function Address Register */ +#define AT91C_UDP_NUM ( ( AT91_REG * ) 0xFFFB0000 ) /* (UDP) Frame Number Register */ +#define AT91C_UDP_FDR ( ( AT91_REG * ) 0xFFFB0050 ) /* (UDP) Endpoint FIFO Data Register */ +#define AT91C_UDP_ISR ( ( AT91_REG * ) 0xFFFB001C ) /* (UDP) Interrupt Status Register */ +#define AT91C_UDP_CSR ( ( AT91_REG * ) 0xFFFB0030 ) /* (UDP) Endpoint Control and Status Register */ +#define AT91C_UDP_IDR ( ( AT91_REG * ) 0xFFFB0014 ) /* (UDP) Interrupt Disable Register */ +#define AT91C_UDP_ICR ( ( AT91_REG * ) 0xFFFB0020 ) /* (UDP) Interrupt Clear Register */ +#define AT91C_UDP_RSTEP ( ( AT91_REG * ) 0xFFFB0028 ) /* (UDP) Reset Endpoint Register */ +#define AT91C_UDP_TXVC ( ( AT91_REG * ) 0xFFFB0074 ) /* (UDP) Transceiver Control Register */ +#define AT91C_UDP_GLBSTATE ( ( AT91_REG * ) 0xFFFB0004 ) /* (UDP) Global State Register */ +#define AT91C_UDP_IER ( ( AT91_REG * ) 0xFFFB0010 ) /* (UDP) Interrupt Enable Register */ +/* ========== Register definition for TC0 peripheral ========== */ +#define AT91C_TC0_SR ( ( AT91_REG * ) 0xFFFA0020 ) /* (TC0) Status Register */ +#define AT91C_TC0_RC ( ( AT91_REG * ) 0xFFFA001C ) /* (TC0) Register C */ +#define AT91C_TC0_RB ( ( AT91_REG * ) 0xFFFA0018 ) /* (TC0) Register B */ +#define AT91C_TC0_CCR ( ( AT91_REG * ) 0xFFFA0000 ) /* (TC0) Channel Control Register */ +#define AT91C_TC0_CMR ( ( AT91_REG * ) 0xFFFA0004 ) /* (TC0) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC0_IER ( ( AT91_REG * ) 0xFFFA0024 ) /* (TC0) Interrupt Enable Register */ +#define AT91C_TC0_RA ( ( AT91_REG * ) 0xFFFA0014 ) /* (TC0) Register A */ +#define AT91C_TC0_IDR ( ( AT91_REG * ) 0xFFFA0028 ) /* (TC0) Interrupt Disable Register */ +#define AT91C_TC0_CV ( ( AT91_REG * ) 0xFFFA0010 ) /* (TC0) Counter Value */ +#define AT91C_TC0_IMR ( ( AT91_REG * ) 0xFFFA002C ) /* (TC0) Interrupt Mask Register */ +/* ========== Register definition for TC1 peripheral ========== */ +#define AT91C_TC1_RB ( ( AT91_REG * ) 0xFFFA0058 ) /* (TC1) Register B */ +#define AT91C_TC1_CCR ( ( AT91_REG * ) 0xFFFA0040 ) /* (TC1) Channel Control Register */ +#define AT91C_TC1_IER ( ( AT91_REG * ) 0xFFFA0064 ) /* (TC1) Interrupt Enable Register */ +#define AT91C_TC1_IDR ( ( AT91_REG * ) 0xFFFA0068 ) /* (TC1) Interrupt Disable Register */ +#define AT91C_TC1_SR ( ( AT91_REG * ) 0xFFFA0060 ) /* (TC1) Status Register */ +#define AT91C_TC1_CMR ( ( AT91_REG * ) 0xFFFA0044 ) /* (TC1) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC1_RA ( ( AT91_REG * ) 0xFFFA0054 ) /* (TC1) Register A */ +#define AT91C_TC1_RC ( ( AT91_REG * ) 0xFFFA005C ) /* (TC1) Register C */ +#define AT91C_TC1_IMR ( ( AT91_REG * ) 0xFFFA006C ) /* (TC1) Interrupt Mask Register */ +#define AT91C_TC1_CV ( ( AT91_REG * ) 0xFFFA0050 ) /* (TC1) Counter Value */ +/* ========== Register definition for TC2 peripheral ========== */ +#define AT91C_TC2_CMR ( ( AT91_REG * ) 0xFFFA0084 ) /* (TC2) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC2_CCR ( ( AT91_REG * ) 0xFFFA0080 ) /* (TC2) Channel Control Register */ +#define AT91C_TC2_CV ( ( AT91_REG * ) 0xFFFA0090 ) /* (TC2) Counter Value */ +#define AT91C_TC2_RA ( ( AT91_REG * ) 0xFFFA0094 ) /* (TC2) Register A */ +#define AT91C_TC2_RB ( ( AT91_REG * ) 0xFFFA0098 ) /* (TC2) Register B */ +#define AT91C_TC2_IDR ( ( AT91_REG * ) 0xFFFA00A8 ) /* (TC2) Interrupt Disable Register */ +#define AT91C_TC2_IMR ( ( AT91_REG * ) 0xFFFA00AC ) /* (TC2) Interrupt Mask Register */ +#define AT91C_TC2_RC ( ( AT91_REG * ) 0xFFFA009C ) /* (TC2) Register C */ +#define AT91C_TC2_IER ( ( AT91_REG * ) 0xFFFA00A4 ) /* (TC2) Interrupt Enable Register */ +#define AT91C_TC2_SR ( ( AT91_REG * ) 0xFFFA00A0 ) /* (TC2) Status Register */ +/* ========== Register definition for TCB peripheral ========== */ +#define AT91C_TCB_BMR ( ( AT91_REG * ) 0xFFFA00C4 ) /* (TCB) TC Block Mode Register */ +#define AT91C_TCB_BCR ( ( AT91_REG * ) 0xFFFA00C0 ) /* (TCB) TC Block Control Register */ +/* ========== Register definition for CAN_MB0 peripheral ========== */ +#define AT91C_CAN_MB0_MDL ( ( AT91_REG * ) 0xFFFD0214 ) /* (CAN_MB0) MailBox Data Low Register */ +#define AT91C_CAN_MB0_MAM ( ( AT91_REG * ) 0xFFFD0204 ) /* (CAN_MB0) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB0_MCR ( ( AT91_REG * ) 0xFFFD021C ) /* (CAN_MB0) MailBox Control Register */ +#define AT91C_CAN_MB0_MID ( ( AT91_REG * ) 0xFFFD0208 ) /* (CAN_MB0) MailBox ID Register */ +#define AT91C_CAN_MB0_MSR ( ( AT91_REG * ) 0xFFFD0210 ) /* (CAN_MB0) MailBox Status Register */ +#define AT91C_CAN_MB0_MFID ( ( AT91_REG * ) 0xFFFD020C ) /* (CAN_MB0) MailBox Family ID Register */ +#define AT91C_CAN_MB0_MDH ( ( AT91_REG * ) 0xFFFD0218 ) /* (CAN_MB0) MailBox Data High Register */ +#define AT91C_CAN_MB0_MMR ( ( AT91_REG * ) 0xFFFD0200 ) /* (CAN_MB0) MailBox Mode Register */ +/* ========== Register definition for CAN_MB1 peripheral ========== */ +#define AT91C_CAN_MB1_MDL ( ( AT91_REG * ) 0xFFFD0234 ) /* (CAN_MB1) MailBox Data Low Register */ +#define AT91C_CAN_MB1_MID ( ( AT91_REG * ) 0xFFFD0228 ) /* (CAN_MB1) MailBox ID Register */ +#define AT91C_CAN_MB1_MMR ( ( AT91_REG * ) 0xFFFD0220 ) /* (CAN_MB1) MailBox Mode Register */ +#define AT91C_CAN_MB1_MSR ( ( AT91_REG * ) 0xFFFD0230 ) /* (CAN_MB1) MailBox Status Register */ +#define AT91C_CAN_MB1_MAM ( ( AT91_REG * ) 0xFFFD0224 ) /* (CAN_MB1) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB1_MDH ( ( AT91_REG * ) 0xFFFD0238 ) /* (CAN_MB1) MailBox Data High Register */ +#define AT91C_CAN_MB1_MCR ( ( AT91_REG * ) 0xFFFD023C ) /* (CAN_MB1) MailBox Control Register */ +#define AT91C_CAN_MB1_MFID ( ( AT91_REG * ) 0xFFFD022C ) /* (CAN_MB1) MailBox Family ID Register */ +/* ========== Register definition for CAN_MB2 peripheral ========== */ +#define AT91C_CAN_MB2_MCR ( ( AT91_REG * ) 0xFFFD025C ) /* (CAN_MB2) MailBox Control Register */ +#define AT91C_CAN_MB2_MDH ( ( AT91_REG * ) 0xFFFD0258 ) /* (CAN_MB2) MailBox Data High Register */ +#define AT91C_CAN_MB2_MID ( ( AT91_REG * ) 0xFFFD0248 ) /* (CAN_MB2) MailBox ID Register */ +#define AT91C_CAN_MB2_MDL ( ( AT91_REG * ) 0xFFFD0254 ) /* (CAN_MB2) MailBox Data Low Register */ +#define AT91C_CAN_MB2_MMR ( ( AT91_REG * ) 0xFFFD0240 ) /* (CAN_MB2) MailBox Mode Register */ +#define AT91C_CAN_MB2_MAM ( ( AT91_REG * ) 0xFFFD0244 ) /* (CAN_MB2) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB2_MFID ( ( AT91_REG * ) 0xFFFD024C ) /* (CAN_MB2) MailBox Family ID Register */ +#define AT91C_CAN_MB2_MSR ( ( AT91_REG * ) 0xFFFD0250 ) /* (CAN_MB2) MailBox Status Register */ +/* ========== Register definition for CAN_MB3 peripheral ========== */ +#define AT91C_CAN_MB3_MFID ( ( AT91_REG * ) 0xFFFD026C ) /* (CAN_MB3) MailBox Family ID Register */ +#define AT91C_CAN_MB3_MAM ( ( AT91_REG * ) 0xFFFD0264 ) /* (CAN_MB3) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB3_MID ( ( AT91_REG * ) 0xFFFD0268 ) /* (CAN_MB3) MailBox ID Register */ +#define AT91C_CAN_MB3_MCR ( ( AT91_REG * ) 0xFFFD027C ) /* (CAN_MB3) MailBox Control Register */ +#define AT91C_CAN_MB3_MMR ( ( AT91_REG * ) 0xFFFD0260 ) /* (CAN_MB3) MailBox Mode Register */ +#define AT91C_CAN_MB3_MSR ( ( AT91_REG * ) 0xFFFD0270 ) /* (CAN_MB3) MailBox Status Register */ +#define AT91C_CAN_MB3_MDL ( ( AT91_REG * ) 0xFFFD0274 ) /* (CAN_MB3) MailBox Data Low Register */ +#define AT91C_CAN_MB3_MDH ( ( AT91_REG * ) 0xFFFD0278 ) /* (CAN_MB3) MailBox Data High Register */ +/* ========== Register definition for CAN_MB4 peripheral ========== */ +#define AT91C_CAN_MB4_MID ( ( AT91_REG * ) 0xFFFD0288 ) /* (CAN_MB4) MailBox ID Register */ +#define AT91C_CAN_MB4_MMR ( ( AT91_REG * ) 0xFFFD0280 ) /* (CAN_MB4) MailBox Mode Register */ +#define AT91C_CAN_MB4_MDH ( ( AT91_REG * ) 0xFFFD0298 ) /* (CAN_MB4) MailBox Data High Register */ +#define AT91C_CAN_MB4_MFID ( ( AT91_REG * ) 0xFFFD028C ) /* (CAN_MB4) MailBox Family ID Register */ +#define AT91C_CAN_MB4_MSR ( ( AT91_REG * ) 0xFFFD0290 ) /* (CAN_MB4) MailBox Status Register */ +#define AT91C_CAN_MB4_MCR ( ( AT91_REG * ) 0xFFFD029C ) /* (CAN_MB4) MailBox Control Register */ +#define AT91C_CAN_MB4_MDL ( ( AT91_REG * ) 0xFFFD0294 ) /* (CAN_MB4) MailBox Data Low Register */ +#define AT91C_CAN_MB4_MAM ( ( AT91_REG * ) 0xFFFD0284 ) /* (CAN_MB4) MailBox Acceptance Mask Register */ +/* ========== Register definition for CAN_MB5 peripheral ========== */ +#define AT91C_CAN_MB5_MSR ( ( AT91_REG * ) 0xFFFD02B0 ) /* (CAN_MB5) MailBox Status Register */ +#define AT91C_CAN_MB5_MCR ( ( AT91_REG * ) 0xFFFD02BC ) /* (CAN_MB5) MailBox Control Register */ +#define AT91C_CAN_MB5_MFID ( ( AT91_REG * ) 0xFFFD02AC ) /* (CAN_MB5) MailBox Family ID Register */ +#define AT91C_CAN_MB5_MDH ( ( AT91_REG * ) 0xFFFD02B8 ) /* (CAN_MB5) MailBox Data High Register */ +#define AT91C_CAN_MB5_MID ( ( AT91_REG * ) 0xFFFD02A8 ) /* (CAN_MB5) MailBox ID Register */ +#define AT91C_CAN_MB5_MMR ( ( AT91_REG * ) 0xFFFD02A0 ) /* (CAN_MB5) MailBox Mode Register */ +#define AT91C_CAN_MB5_MDL ( ( AT91_REG * ) 0xFFFD02B4 ) /* (CAN_MB5) MailBox Data Low Register */ +#define AT91C_CAN_MB5_MAM ( ( AT91_REG * ) 0xFFFD02A4 ) /* (CAN_MB5) MailBox Acceptance Mask Register */ +/* ========== Register definition for CAN_MB6 peripheral ========== */ +#define AT91C_CAN_MB6_MFID ( ( AT91_REG * ) 0xFFFD02CC ) /* (CAN_MB6) MailBox Family ID Register */ +#define AT91C_CAN_MB6_MID ( ( AT91_REG * ) 0xFFFD02C8 ) /* (CAN_MB6) MailBox ID Register */ +#define AT91C_CAN_MB6_MAM ( ( AT91_REG * ) 0xFFFD02C4 ) /* (CAN_MB6) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB6_MSR ( ( AT91_REG * ) 0xFFFD02D0 ) /* (CAN_MB6) MailBox Status Register */ +#define AT91C_CAN_MB6_MDL ( ( AT91_REG * ) 0xFFFD02D4 ) /* (CAN_MB6) MailBox Data Low Register */ +#define AT91C_CAN_MB6_MCR ( ( AT91_REG * ) 0xFFFD02DC ) /* (CAN_MB6) MailBox Control Register */ +#define AT91C_CAN_MB6_MDH ( ( AT91_REG * ) 0xFFFD02D8 ) /* (CAN_MB6) MailBox Data High Register */ +#define AT91C_CAN_MB6_MMR ( ( AT91_REG * ) 0xFFFD02C0 ) /* (CAN_MB6) MailBox Mode Register */ +/* ========== Register definition for CAN_MB7 peripheral ========== */ +#define AT91C_CAN_MB7_MCR ( ( AT91_REG * ) 0xFFFD02FC ) /* (CAN_MB7) MailBox Control Register */ +#define AT91C_CAN_MB7_MDH ( ( AT91_REG * ) 0xFFFD02F8 ) /* (CAN_MB7) MailBox Data High Register */ +#define AT91C_CAN_MB7_MFID ( ( AT91_REG * ) 0xFFFD02EC ) /* (CAN_MB7) MailBox Family ID Register */ +#define AT91C_CAN_MB7_MDL ( ( AT91_REG * ) 0xFFFD02F4 ) /* (CAN_MB7) MailBox Data Low Register */ +#define AT91C_CAN_MB7_MID ( ( AT91_REG * ) 0xFFFD02E8 ) /* (CAN_MB7) MailBox ID Register */ +#define AT91C_CAN_MB7_MMR ( ( AT91_REG * ) 0xFFFD02E0 ) /* (CAN_MB7) MailBox Mode Register */ +#define AT91C_CAN_MB7_MAM ( ( AT91_REG * ) 0xFFFD02E4 ) /* (CAN_MB7) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB7_MSR ( ( AT91_REG * ) 0xFFFD02F0 ) /* (CAN_MB7) MailBox Status Register */ +/* ========== Register definition for CAN peripheral ========== */ +#define AT91C_CAN_TCR ( ( AT91_REG * ) 0xFFFD0024 ) /* (CAN) Transfer Command Register */ +#define AT91C_CAN_IMR ( ( AT91_REG * ) 0xFFFD000C ) /* (CAN) Interrupt Mask Register */ +#define AT91C_CAN_IER ( ( AT91_REG * ) 0xFFFD0004 ) /* (CAN) Interrupt Enable Register */ +#define AT91C_CAN_ECR ( ( AT91_REG * ) 0xFFFD0020 ) /* (CAN) Error Counter Register */ +#define AT91C_CAN_TIMESTP ( ( AT91_REG * ) 0xFFFD001C ) /* (CAN) Time Stamp Register */ +#define AT91C_CAN_MR ( ( AT91_REG * ) 0xFFFD0000 ) /* (CAN) Mode Register */ +#define AT91C_CAN_IDR ( ( AT91_REG * ) 0xFFFD0008 ) /* (CAN) Interrupt Disable Register */ +#define AT91C_CAN_ACR ( ( AT91_REG * ) 0xFFFD0028 ) /* (CAN) Abort Command Register */ +#define AT91C_CAN_TIM ( ( AT91_REG * ) 0xFFFD0018 ) /* (CAN) Timer Register */ +#define AT91C_CAN_SR ( ( AT91_REG * ) 0xFFFD0010 ) /* (CAN) Status Register */ +#define AT91C_CAN_BR ( ( AT91_REG * ) 0xFFFD0014 ) /* (CAN) Baudrate Register */ +#define AT91C_CAN_VR ( ( AT91_REG * ) 0xFFFD00FC ) /* (CAN) Version Register */ +/* ========== Register definition for EMAC peripheral ========== */ +#define AT91C_EMAC_ISR ( ( AT91_REG * ) 0xFFFDC024 ) /* (EMAC) Interrupt Status Register */ +#define AT91C_EMAC_SA4H ( ( AT91_REG * ) 0xFFFDC0B4 ) /* (EMAC) Specific Address 4 Top, Last 2 bytes */ +#define AT91C_EMAC_SA1L ( ( AT91_REG * ) 0xFFFDC098 ) /* (EMAC) Specific Address 1 Bottom, First 4 bytes */ +#define AT91C_EMAC_ELE ( ( AT91_REG * ) 0xFFFDC078 ) /* (EMAC) Excessive Length Errors Register */ +#define AT91C_EMAC_LCOL ( ( AT91_REG * ) 0xFFFDC05C ) /* (EMAC) Late Collision Register */ +#define AT91C_EMAC_RLE ( ( AT91_REG * ) 0xFFFDC088 ) /* (EMAC) Receive Length Field Mismatch Register */ +#define AT91C_EMAC_WOL ( ( AT91_REG * ) 0xFFFDC0C4 ) /* (EMAC) Wake On LAN Register */ +#define AT91C_EMAC_DTF ( ( AT91_REG * ) 0xFFFDC058 ) /* (EMAC) Deferred Transmission Frame Register */ +#define AT91C_EMAC_TUND ( ( AT91_REG * ) 0xFFFDC064 ) /* (EMAC) Transmit Underrun Error Register */ +#define AT91C_EMAC_NCR ( ( AT91_REG * ) 0xFFFDC000 ) /* (EMAC) Network Control Register */ +#define AT91C_EMAC_SA4L ( ( AT91_REG * ) 0xFFFDC0B0 ) /* (EMAC) Specific Address 4 Bottom, First 4 bytes */ +#define AT91C_EMAC_RSR ( ( AT91_REG * ) 0xFFFDC020 ) /* (EMAC) Receive Status Register */ +#define AT91C_EMAC_SA3L ( ( AT91_REG * ) 0xFFFDC0A8 ) /* (EMAC) Specific Address 3 Bottom, First 4 bytes */ +#define AT91C_EMAC_TSR ( ( AT91_REG * ) 0xFFFDC014 ) /* (EMAC) Transmit Status Register */ +#define AT91C_EMAC_IDR ( ( AT91_REG * ) 0xFFFDC02C ) /* (EMAC) Interrupt Disable Register */ +#define AT91C_EMAC_RSE ( ( AT91_REG * ) 0xFFFDC074 ) /* (EMAC) Receive Symbol Errors Register */ +#define AT91C_EMAC_ECOL ( ( AT91_REG * ) 0xFFFDC060 ) /* (EMAC) Excessive Collision Register */ +#define AT91C_EMAC_TID ( ( AT91_REG * ) 0xFFFDC0B8 ) /* (EMAC) Type ID Checking Register */ +#define AT91C_EMAC_HRB ( ( AT91_REG * ) 0xFFFDC090 ) /* (EMAC) Hash Address Bottom[31:0] */ +#define AT91C_EMAC_TBQP ( ( AT91_REG * ) 0xFFFDC01C ) /* (EMAC) Transmit Buffer Queue Pointer */ +#define AT91C_EMAC_USRIO ( ( AT91_REG * ) 0xFFFDC0C0 ) /* (EMAC) USER Input/Output Register */ +#define AT91C_EMAC_PTR ( ( AT91_REG * ) 0xFFFDC038 ) /* (EMAC) Pause Time Register */ +#define AT91C_EMAC_SA2H ( ( AT91_REG * ) 0xFFFDC0A4 ) /* (EMAC) Specific Address 2 Top, Last 2 bytes */ +#define AT91C_EMAC_ROV ( ( AT91_REG * ) 0xFFFDC070 ) /* (EMAC) Receive Overrun Errors Register */ +#define AT91C_EMAC_ALE ( ( AT91_REG * ) 0xFFFDC054 ) /* (EMAC) Alignment Error Register */ +#define AT91C_EMAC_RJA ( ( AT91_REG * ) 0xFFFDC07C ) /* (EMAC) Receive Jabbers Register */ +#define AT91C_EMAC_RBQP ( ( AT91_REG * ) 0xFFFDC018 ) /* (EMAC) Receive Buffer Queue Pointer */ +#define AT91C_EMAC_TPF ( ( AT91_REG * ) 0xFFFDC08C ) /* (EMAC) Transmitted Pause Frames Register */ +#define AT91C_EMAC_NCFGR ( ( AT91_REG * ) 0xFFFDC004 ) /* (EMAC) Network Configuration Register */ +#define AT91C_EMAC_HRT ( ( AT91_REG * ) 0xFFFDC094 ) /* (EMAC) Hash Address Top[63:32] */ +#define AT91C_EMAC_USF ( ( AT91_REG * ) 0xFFFDC080 ) /* (EMAC) Undersize Frames Register */ +#define AT91C_EMAC_FCSE ( ( AT91_REG * ) 0xFFFDC050 ) /* (EMAC) Frame Check Sequence Error Register */ +#define AT91C_EMAC_TPQ ( ( AT91_REG * ) 0xFFFDC0BC ) /* (EMAC) Transmit Pause Quantum Register */ +#define AT91C_EMAC_MAN ( ( AT91_REG * ) 0xFFFDC034 ) /* (EMAC) PHY Maintenance Register */ +#define AT91C_EMAC_FTO ( ( AT91_REG * ) 0xFFFDC040 ) /* (EMAC) Frames Transmitted OK Register */ +#define AT91C_EMAC_REV ( ( AT91_REG * ) 0xFFFDC0FC ) /* (EMAC) Revision Register */ +#define AT91C_EMAC_IMR ( ( AT91_REG * ) 0xFFFDC030 ) /* (EMAC) Interrupt Mask Register */ +#define AT91C_EMAC_SCF ( ( AT91_REG * ) 0xFFFDC044 ) /* (EMAC) Single Collision Frame Register */ +#define AT91C_EMAC_PFR ( ( AT91_REG * ) 0xFFFDC03C ) /* (EMAC) Pause Frames received Register */ +#define AT91C_EMAC_MCF ( ( AT91_REG * ) 0xFFFDC048 ) /* (EMAC) Multiple Collision Frame Register */ +#define AT91C_EMAC_NSR ( ( AT91_REG * ) 0xFFFDC008 ) /* (EMAC) Network Status Register */ +#define AT91C_EMAC_SA2L ( ( AT91_REG * ) 0xFFFDC0A0 ) /* (EMAC) Specific Address 2 Bottom, First 4 bytes */ +#define AT91C_EMAC_FRO ( ( AT91_REG * ) 0xFFFDC04C ) /* (EMAC) Frames Received OK Register */ +#define AT91C_EMAC_IER ( ( AT91_REG * ) 0xFFFDC028 ) /* (EMAC) Interrupt Enable Register */ +#define AT91C_EMAC_SA1H ( ( AT91_REG * ) 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */ +#define AT91C_EMAC_CSE ( ( AT91_REG * ) 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */ +#define AT91C_EMAC_SA3H ( ( AT91_REG * ) 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */ +#define AT91C_EMAC_RRE ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Resource Error Register */ +#define AT91C_EMAC_STE ( ( AT91_REG * ) 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */ +/* ========== Register definition for PDC_ADC peripheral ========== */ +#define AT91C_ADC_PTSR ( ( AT91_REG * ) 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */ +#define AT91C_ADC_PTCR ( ( AT91_REG * ) 0xFFFD8120 ) /* (PDC_ADC) PDC Transfer Control Register */ +#define AT91C_ADC_TNPR ( ( AT91_REG * ) 0xFFFD8118 ) /* (PDC_ADC) Transmit Next Pointer Register */ +#define AT91C_ADC_TNCR ( ( AT91_REG * ) 0xFFFD811C ) /* (PDC_ADC) Transmit Next Counter Register */ +#define AT91C_ADC_RNPR ( ( AT91_REG * ) 0xFFFD8110 ) /* (PDC_ADC) Receive Next Pointer Register */ +#define AT91C_ADC_RNCR ( ( AT91_REG * ) 0xFFFD8114 ) /* (PDC_ADC) Receive Next Counter Register */ +#define AT91C_ADC_RPR ( ( AT91_REG * ) 0xFFFD8100 ) /* (PDC_ADC) Receive Pointer Register */ +#define AT91C_ADC_TCR ( ( AT91_REG * ) 0xFFFD810C ) /* (PDC_ADC) Transmit Counter Register */ +#define AT91C_ADC_TPR ( ( AT91_REG * ) 0xFFFD8108 ) /* (PDC_ADC) Transmit Pointer Register */ +#define AT91C_ADC_RCR ( ( AT91_REG * ) 0xFFFD8104 ) /* (PDC_ADC) Receive Counter Register */ +/* ========== Register definition for ADC peripheral ========== */ +#define AT91C_ADC_CDR2 ( ( AT91_REG * ) 0xFFFD8038 ) /* (ADC) ADC Channel Data Register 2 */ +#define AT91C_ADC_CDR3 ( ( AT91_REG * ) 0xFFFD803C ) /* (ADC) ADC Channel Data Register 3 */ +#define AT91C_ADC_CDR0 ( ( AT91_REG * ) 0xFFFD8030 ) /* (ADC) ADC Channel Data Register 0 */ +#define AT91C_ADC_CDR5 ( ( AT91_REG * ) 0xFFFD8044 ) /* (ADC) ADC Channel Data Register 5 */ +#define AT91C_ADC_CHDR ( ( AT91_REG * ) 0xFFFD8014 ) /* (ADC) ADC Channel Disable Register */ +#define AT91C_ADC_SR ( ( AT91_REG * ) 0xFFFD801C ) /* (ADC) ADC Status Register */ +#define AT91C_ADC_CDR4 ( ( AT91_REG * ) 0xFFFD8040 ) /* (ADC) ADC Channel Data Register 4 */ +#define AT91C_ADC_CDR1 ( ( AT91_REG * ) 0xFFFD8034 ) /* (ADC) ADC Channel Data Register 1 */ +#define AT91C_ADC_LCDR ( ( AT91_REG * ) 0xFFFD8020 ) /* (ADC) ADC Last Converted Data Register */ +#define AT91C_ADC_IDR ( ( AT91_REG * ) 0xFFFD8028 ) /* (ADC) ADC Interrupt Disable Register */ +#define AT91C_ADC_CR ( ( AT91_REG * ) 0xFFFD8000 ) /* (ADC) ADC Control Register */ +#define AT91C_ADC_CDR7 ( ( AT91_REG * ) 0xFFFD804C ) /* (ADC) ADC Channel Data Register 7 */ +#define AT91C_ADC_CDR6 ( ( AT91_REG * ) 0xFFFD8048 ) /* (ADC) ADC Channel Data Register 6 */ +#define AT91C_ADC_IER ( ( AT91_REG * ) 0xFFFD8024 ) /* (ADC) ADC Interrupt Enable Register */ +#define AT91C_ADC_CHER ( ( AT91_REG * ) 0xFFFD8010 ) /* (ADC) ADC Channel Enable Register */ +#define AT91C_ADC_CHSR ( ( AT91_REG * ) 0xFFFD8018 ) /* (ADC) ADC Channel Status Register */ +#define AT91C_ADC_MR ( ( AT91_REG * ) 0xFFFD8004 ) /* (ADC) ADC Mode Register */ +#define AT91C_ADC_IMR ( ( AT91_REG * ) 0xFFFD802C ) /* (ADC) ADC Interrupt Mask Register */ +/* ========== Register definition for PDC_AES peripheral ========== */ +#define AT91C_AES_TPR ( ( AT91_REG * ) 0xFFFA4108 ) /* (PDC_AES) Transmit Pointer Register */ +#define AT91C_AES_PTCR ( ( AT91_REG * ) 0xFFFA4120 ) /* (PDC_AES) PDC Transfer Control Register */ +#define AT91C_AES_RNPR ( ( AT91_REG * ) 0xFFFA4110 ) /* (PDC_AES) Receive Next Pointer Register */ +#define AT91C_AES_TNCR ( ( AT91_REG * ) 0xFFFA411C ) /* (PDC_AES) Transmit Next Counter Register */ +#define AT91C_AES_TCR ( ( AT91_REG * ) 0xFFFA410C ) /* (PDC_AES) Transmit Counter Register */ +#define AT91C_AES_RCR ( ( AT91_REG * ) 0xFFFA4104 ) /* (PDC_AES) Receive Counter Register */ +#define AT91C_AES_RNCR ( ( AT91_REG * ) 0xFFFA4114 ) /* (PDC_AES) Receive Next Counter Register */ +#define AT91C_AES_TNPR ( ( AT91_REG * ) 0xFFFA4118 ) /* (PDC_AES) Transmit Next Pointer Register */ +#define AT91C_AES_RPR ( ( AT91_REG * ) 0xFFFA4100 ) /* (PDC_AES) Receive Pointer Register */ +#define AT91C_AES_PTSR ( ( AT91_REG * ) 0xFFFA4124 ) /* (PDC_AES) PDC Transfer Status Register */ +/* ========== Register definition for AES peripheral ========== */ +#define AT91C_AES_IVxR ( ( AT91_REG * ) 0xFFFA4060 ) /* (AES) Initialization Vector x Register */ +#define AT91C_AES_MR ( ( AT91_REG * ) 0xFFFA4004 ) /* (AES) Mode Register */ +#define AT91C_AES_VR ( ( AT91_REG * ) 0xFFFA40FC ) /* (AES) AES Version Register */ +#define AT91C_AES_ODATAxR ( ( AT91_REG * ) 0xFFFA4050 ) /* (AES) Output Data x Register */ +#define AT91C_AES_IDATAxR ( ( AT91_REG * ) 0xFFFA4040 ) /* (AES) Input Data x Register */ +#define AT91C_AES_CR ( ( AT91_REG * ) 0xFFFA4000 ) /* (AES) Control Register */ +#define AT91C_AES_IDR ( ( AT91_REG * ) 0xFFFA4014 ) /* (AES) Interrupt Disable Register */ +#define AT91C_AES_IMR ( ( AT91_REG * ) 0xFFFA4018 ) /* (AES) Interrupt Mask Register */ +#define AT91C_AES_IER ( ( AT91_REG * ) 0xFFFA4010 ) /* (AES) Interrupt Enable Register */ +#define AT91C_AES_KEYWxR ( ( AT91_REG * ) 0xFFFA4020 ) /* (AES) Key Word x Register */ +#define AT91C_AES_ISR ( ( AT91_REG * ) 0xFFFA401C ) /* (AES) Interrupt Status Register */ +/* ========== Register definition for PDC_TDES peripheral ========== */ +#define AT91C_TDES_RNCR ( ( AT91_REG * ) 0xFFFA8114 ) /* (PDC_TDES) Receive Next Counter Register */ +#define AT91C_TDES_TCR ( ( AT91_REG * ) 0xFFFA810C ) /* (PDC_TDES) Transmit Counter Register */ +#define AT91C_TDES_RCR ( ( AT91_REG * ) 0xFFFA8104 ) /* (PDC_TDES) Receive Counter Register */ +#define AT91C_TDES_TNPR ( ( AT91_REG * ) 0xFFFA8118 ) /* (PDC_TDES) Transmit Next Pointer Register */ +#define AT91C_TDES_RNPR ( ( AT91_REG * ) 0xFFFA8110 ) /* (PDC_TDES) Receive Next Pointer Register */ +#define AT91C_TDES_RPR ( ( AT91_REG * ) 0xFFFA8100 ) /* (PDC_TDES) Receive Pointer Register */ +#define AT91C_TDES_TNCR ( ( AT91_REG * ) 0xFFFA811C ) /* (PDC_TDES) Transmit Next Counter Register */ +#define AT91C_TDES_TPR ( ( AT91_REG * ) 0xFFFA8108 ) /* (PDC_TDES) Transmit Pointer Register */ +#define AT91C_TDES_PTSR ( ( AT91_REG * ) 0xFFFA8124 ) /* (PDC_TDES) PDC Transfer Status Register */ +#define AT91C_TDES_PTCR ( ( AT91_REG * ) 0xFFFA8120 ) /* (PDC_TDES) PDC Transfer Control Register */ +/* ========== Register definition for TDES peripheral ========== */ +#define AT91C_TDES_KEY2WxR ( ( AT91_REG * ) 0xFFFA8028 ) /* (TDES) Key 2 Word x Register */ +#define AT91C_TDES_KEY3WxR ( ( AT91_REG * ) 0xFFFA8030 ) /* (TDES) Key 3 Word x Register */ +#define AT91C_TDES_IDR ( ( AT91_REG * ) 0xFFFA8014 ) /* (TDES) Interrupt Disable Register */ +#define AT91C_TDES_VR ( ( AT91_REG * ) 0xFFFA80FC ) /* (TDES) TDES Version Register */ +#define AT91C_TDES_IVxR ( ( AT91_REG * ) 0xFFFA8060 ) /* (TDES) Initialization Vector x Register */ +#define AT91C_TDES_ODATAxR ( ( AT91_REG * ) 0xFFFA8050 ) /* (TDES) Output Data x Register */ +#define AT91C_TDES_IMR ( ( AT91_REG * ) 0xFFFA8018 ) /* (TDES) Interrupt Mask Register */ +#define AT91C_TDES_MR ( ( AT91_REG * ) 0xFFFA8004 ) /* (TDES) Mode Register */ +#define AT91C_TDES_CR ( ( AT91_REG * ) 0xFFFA8000 ) /* (TDES) Control Register */ +#define AT91C_TDES_IER ( ( AT91_REG * ) 0xFFFA8010 ) /* (TDES) Interrupt Enable Register */ +#define AT91C_TDES_ISR ( ( AT91_REG * ) 0xFFFA801C ) /* (TDES) Interrupt Status Register */ +#define AT91C_TDES_IDATAxR ( ( AT91_REG * ) 0xFFFA8040 ) /* (TDES) Input Data x Register */ +#define AT91C_TDES_KEY1WxR ( ( AT91_REG * ) 0xFFFA8020 ) /* (TDES) Key 1 Word x Register */ + +/* ***************************************************************************** */ +/* PIO DEFINITIONS FOR AT91SAM7X256 */ +/* ***************************************************************************** */ +#define AT91C_PIO_PA0 ( ( unsigned int ) 1 << 0 ) /* Pin Controlled by PA0 */ +#define AT91C_PA0_RXD0 ( ( unsigned int ) AT91C_PIO_PA0 ) /* USART 0 Receive Data */ +#define AT91C_PIO_PA1 ( ( unsigned int ) 1 << 1 ) /* Pin Controlled by PA1 */ +#define AT91C_PA1_TXD0 ( ( unsigned int ) AT91C_PIO_PA1 ) /* USART 0 Transmit Data */ +#define AT91C_PIO_PA10 ( ( unsigned int ) 1 << 10 ) /* Pin Controlled by PA10 */ +#define AT91C_PA10_TWD ( ( unsigned int ) AT91C_PIO_PA10 ) /* TWI Two-wire Serial Data */ +#define AT91C_PIO_PA11 ( ( unsigned int ) 1 << 11 ) /* Pin Controlled by PA11 */ +#define AT91C_PA11_TWCK ( ( unsigned int ) AT91C_PIO_PA11 ) /* TWI Two-wire Serial Clock */ +#define AT91C_PIO_PA12 ( ( unsigned int ) 1 << 12 ) /* Pin Controlled by PA12 */ +#define AT91C_PA12_NPCS00 ( ( unsigned int ) AT91C_PIO_PA12 ) /* SPI 0 Peripheral Chip Select 0 */ +#define AT91C_PIO_PA13 ( ( unsigned int ) 1 << 13 ) /* Pin Controlled by PA13 */ +#define AT91C_PA13_NPCS01 ( ( unsigned int ) AT91C_PIO_PA13 ) /* SPI 0 Peripheral Chip Select 1 */ +#define AT91C_PA13_PCK1 ( ( unsigned int ) AT91C_PIO_PA13 ) /* PMC Programmable Clock Output 1 */ +#define AT91C_PIO_PA14 ( ( unsigned int ) 1 << 14 ) /* Pin Controlled by PA14 */ +#define AT91C_PA14_NPCS02 ( ( unsigned int ) AT91C_PIO_PA14 ) /* SPI 0 Peripheral Chip Select 2 */ +#define AT91C_PA14_IRQ1 ( ( unsigned int ) AT91C_PIO_PA14 ) /* External Interrupt 1 */ +#define AT91C_PIO_PA15 ( ( unsigned int ) 1 << 15 ) /* Pin Controlled by PA15 */ +#define AT91C_PA15_NPCS03 ( ( unsigned int ) AT91C_PIO_PA15 ) /* SPI 0 Peripheral Chip Select 3 */ +#define AT91C_PA15_TCLK2 ( ( unsigned int ) AT91C_PIO_PA15 ) /* Timer Counter 2 external clock input */ +#define AT91C_PIO_PA16 ( ( unsigned int ) 1 << 16 ) /* Pin Controlled by PA16 */ +#define AT91C_PA16_MISO0 ( ( unsigned int ) AT91C_PIO_PA16 ) /* SPI 0 Master In Slave */ +#define AT91C_PIO_PA17 ( ( unsigned int ) 1 << 17 ) /* Pin Controlled by PA17 */ +#define AT91C_PA17_MOSI0 ( ( unsigned int ) AT91C_PIO_PA17 ) /* SPI 0 Master Out Slave */ +#define AT91C_PIO_PA18 ( ( unsigned int ) 1 << 18 ) /* Pin Controlled by PA18 */ +#define AT91C_PA18_SPCK0 ( ( unsigned int ) AT91C_PIO_PA18 ) /* SPI 0 Serial Clock */ +#define AT91C_PIO_PA19 ( ( unsigned int ) 1 << 19 ) /* Pin Controlled by PA19 */ +#define AT91C_PA19_CANRX ( ( unsigned int ) AT91C_PIO_PA19 ) /* CAN Receive */ +#define AT91C_PIO_PA2 ( ( unsigned int ) 1 << 2 ) /* Pin Controlled by PA2 */ +#define AT91C_PA2_SCK0 ( ( unsigned int ) AT91C_PIO_PA2 ) /* USART 0 Serial Clock */ +#define AT91C_PA2_NPCS11 ( ( unsigned int ) AT91C_PIO_PA2 ) /* SPI 1 Peripheral Chip Select 1 */ +#define AT91C_PIO_PA20 ( ( unsigned int ) 1 << 20 ) /* Pin Controlled by PA20 */ +#define AT91C_PA20_CANTX ( ( unsigned int ) AT91C_PIO_PA20 ) /* CAN Transmit */ +#define AT91C_PIO_PA21 ( ( unsigned int ) 1 << 21 ) /* Pin Controlled by PA21 */ +#define AT91C_PA21_TF ( ( unsigned int ) AT91C_PIO_PA21 ) /* SSC Transmit Frame Sync */ +#define AT91C_PA21_NPCS10 ( ( unsigned int ) AT91C_PIO_PA21 ) /* SPI 1 Peripheral Chip Select 0 */ +#define AT91C_PIO_PA22 ( ( unsigned int ) 1 << 22 ) /* Pin Controlled by PA22 */ +#define AT91C_PA22_TK ( ( unsigned int ) AT91C_PIO_PA22 ) /* SSC Transmit Clock */ +#define AT91C_PA22_SPCK1 ( ( unsigned int ) AT91C_PIO_PA22 ) /* SPI 1 Serial Clock */ +#define AT91C_PIO_PA23 ( ( unsigned int ) 1 << 23 ) /* Pin Controlled by PA23 */ +#define AT91C_PA23_TD ( ( unsigned int ) AT91C_PIO_PA23 ) /* SSC Transmit data */ +#define AT91C_PA23_MOSI1 ( ( unsigned int ) AT91C_PIO_PA23 ) /* SPI 1 Master Out Slave */ +#define AT91C_PIO_PA24 ( ( unsigned int ) 1 << 24 ) /* Pin Controlled by PA24 */ +#define AT91C_PA24_RD ( ( unsigned int ) AT91C_PIO_PA24 ) /* SSC Receive Data */ +#define AT91C_PA24_MISO1 ( ( unsigned int ) AT91C_PIO_PA24 ) /* SPI 1 Master In Slave */ +#define AT91C_PIO_PA25 ( ( unsigned int ) 1 << 25 ) /* Pin Controlled by PA25 */ +#define AT91C_PA25_RK ( ( unsigned int ) AT91C_PIO_PA25 ) /* SSC Receive Clock */ +#define AT91C_PA25_NPCS11 ( ( unsigned int ) AT91C_PIO_PA25 ) /* SPI 1 Peripheral Chip Select 1 */ +#define AT91C_PIO_PA26 ( ( unsigned int ) 1 << 26 ) /* Pin Controlled by PA26 */ +#define AT91C_PA26_RF ( ( unsigned int ) AT91C_PIO_PA26 ) /* SSC Receive Frame Sync */ +#define AT91C_PA26_NPCS12 ( ( unsigned int ) AT91C_PIO_PA26 ) /* SPI 1 Peripheral Chip Select 2 */ +#define AT91C_PIO_PA27 ( ( unsigned int ) 1 << 27 ) /* Pin Controlled by PA27 */ +#define AT91C_PA27_DRXD ( ( unsigned int ) AT91C_PIO_PA27 ) /* DBGU Debug Receive Data */ +#define AT91C_PA27_PCK3 ( ( unsigned int ) AT91C_PIO_PA27 ) /* PMC Programmable Clock Output 3 */ +#define AT91C_PIO_PA28 ( ( unsigned int ) 1 << 28 ) /* Pin Controlled by PA28 */ +#define AT91C_PA28_DTXD ( ( unsigned int ) AT91C_PIO_PA28 ) /* DBGU Debug Transmit Data */ +#define AT91C_PIO_PA29 ( ( unsigned int ) 1 << 29 ) /* Pin Controlled by PA29 */ +#define AT91C_PA29_FIQ ( ( unsigned int ) AT91C_PIO_PA29 ) /* AIC Fast Interrupt Input */ +#define AT91C_PA29_NPCS13 ( ( unsigned int ) AT91C_PIO_PA29 ) /* SPI 1 Peripheral Chip Select 3 */ +#define AT91C_PIO_PA3 ( ( unsigned int ) 1 << 3 ) /* Pin Controlled by PA3 */ +#define AT91C_PA3_RTS0 ( ( unsigned int ) AT91C_PIO_PA3 ) /* USART 0 Ready To Send */ +#define AT91C_PA3_NPCS12 ( ( unsigned int ) AT91C_PIO_PA3 ) /* SPI 1 Peripheral Chip Select 2 */ +#define AT91C_PIO_PA30 ( ( unsigned int ) 1 << 30 ) /* Pin Controlled by PA30 */ +#define AT91C_PA30_IRQ0 ( ( unsigned int ) AT91C_PIO_PA30 ) /* External Interrupt 0 */ +#define AT91C_PA30_PCK2 ( ( unsigned int ) AT91C_PIO_PA30 ) /* PMC Programmable Clock Output 2 */ +#define AT91C_PIO_PA4 ( ( unsigned int ) 1 << 4 ) /* Pin Controlled by PA4 */ +#define AT91C_PA4_CTS0 ( ( unsigned int ) AT91C_PIO_PA4 ) /* USART 0 Clear To Send */ +#define AT91C_PA4_NPCS13 ( ( unsigned int ) AT91C_PIO_PA4 ) /* SPI 1 Peripheral Chip Select 3 */ +#define AT91C_PIO_PA5 ( ( unsigned int ) 1 << 5 ) /* Pin Controlled by PA5 */ +#define AT91C_PA5_RXD1 ( ( unsigned int ) AT91C_PIO_PA5 ) /* USART 1 Receive Data */ +#define AT91C_PIO_PA6 ( ( unsigned int ) 1 << 6 ) /* Pin Controlled by PA6 */ +#define AT91C_PA6_TXD1 ( ( unsigned int ) AT91C_PIO_PA6 ) /* USART 1 Transmit Data */ +#define AT91C_PIO_PA7 ( ( unsigned int ) 1 << 7 ) /* Pin Controlled by PA7 */ +#define AT91C_PA7_SCK1 ( ( unsigned int ) AT91C_PIO_PA7 ) /* USART 1 Serial Clock */ +#define AT91C_PA7_NPCS01 ( ( unsigned int ) AT91C_PIO_PA7 ) /* SPI 0 Peripheral Chip Select 1 */ +#define AT91C_PIO_PA8 ( ( unsigned int ) 1 << 8 ) /* Pin Controlled by PA8 */ +#define AT91C_PA8_RTS1 ( ( unsigned int ) AT91C_PIO_PA8 ) /* USART 1 Ready To Send */ +#define AT91C_PA8_NPCS02 ( ( unsigned int ) AT91C_PIO_PA8 ) /* SPI 0 Peripheral Chip Select 2 */ +#define AT91C_PIO_PA9 ( ( unsigned int ) 1 << 9 ) /* Pin Controlled by PA9 */ +#define AT91C_PA9_CTS1 ( ( unsigned int ) AT91C_PIO_PA9 ) /* USART 1 Clear To Send */ +#define AT91C_PA9_NPCS03 ( ( unsigned int ) AT91C_PIO_PA9 ) /* SPI 0 Peripheral Chip Select 3 */ +#define AT91C_PIO_PB0 ( ( unsigned int ) 1 << 0 ) /* Pin Controlled by PB0 */ +#define AT91C_PB0_ETXCK_EREFCK ( ( unsigned int ) AT91C_PIO_PB0 ) /* Ethernet MAC Transmit Clock/Reference Clock */ +#define AT91C_PB0_PCK0 ( ( unsigned int ) AT91C_PIO_PB0 ) /* PMC Programmable Clock Output 0 */ +#define AT91C_PIO_PB1 ( ( unsigned int ) 1 << 1 ) /* Pin Controlled by PB1 */ +#define AT91C_PB1_ETXEN ( ( unsigned int ) AT91C_PIO_PB1 ) /* Ethernet MAC Transmit Enable */ +#define AT91C_PIO_PB10 ( ( unsigned int ) 1 << 10 ) /* Pin Controlled by PB10 */ +#define AT91C_PB10_ETX2 ( ( unsigned int ) AT91C_PIO_PB10 ) /* Ethernet MAC Transmit Data 2 */ +#define AT91C_PB10_NPCS11 ( ( unsigned int ) AT91C_PIO_PB10 ) /* SPI 1 Peripheral Chip Select 1 */ +#define AT91C_PIO_PB11 ( ( unsigned int ) 1 << 11 ) /* Pin Controlled by PB11 */ +#define AT91C_PB11_ETX3 ( ( unsigned int ) AT91C_PIO_PB11 ) /* Ethernet MAC Transmit Data 3 */ +#define AT91C_PB11_NPCS12 ( ( unsigned int ) AT91C_PIO_PB11 ) /* SPI 1 Peripheral Chip Select 2 */ +#define AT91C_PIO_PB12 ( ( unsigned int ) 1 << 12 ) /* Pin Controlled by PB12 */ +#define AT91C_PB12_ETXER ( ( unsigned int ) AT91C_PIO_PB12 ) /* Ethernet MAC Transmit Coding Error */ +#define AT91C_PB12_TCLK0 ( ( unsigned int ) AT91C_PIO_PB12 ) /* Timer Counter 0 external clock input */ +#define AT91C_PIO_PB13 ( ( unsigned int ) 1 << 13 ) /* Pin Controlled by PB13 */ +#define AT91C_PB13_ERX2 ( ( unsigned int ) AT91C_PIO_PB13 ) /* Ethernet MAC Receive Data 2 */ +#define AT91C_PB13_NPCS01 ( ( unsigned int ) AT91C_PIO_PB13 ) /* SPI 0 Peripheral Chip Select 1 */ +#define AT91C_PIO_PB14 ( ( unsigned int ) 1 << 14 ) /* Pin Controlled by PB14 */ +#define AT91C_PB14_ERX3 ( ( unsigned int ) AT91C_PIO_PB14 ) /* Ethernet MAC Receive Data 3 */ +#define AT91C_PB14_NPCS02 ( ( unsigned int ) AT91C_PIO_PB14 ) /* SPI 0 Peripheral Chip Select 2 */ +#define AT91C_PIO_PB15 ( ( unsigned int ) 1 << 15 ) /* Pin Controlled by PB15 */ +#define AT91C_PB15_ERXDV ( ( unsigned int ) AT91C_PIO_PB15 ) /* Ethernet MAC Receive Data Valid */ +#define AT91C_PIO_PB16 ( ( unsigned int ) 1 << 16 ) /* Pin Controlled by PB16 */ +#define AT91C_PB16_ECOL ( ( unsigned int ) AT91C_PIO_PB16 ) /* Ethernet MAC Collision Detected */ +#define AT91C_PB16_NPCS13 ( ( unsigned int ) AT91C_PIO_PB16 ) /* SPI 1 Peripheral Chip Select 3 */ +#define AT91C_PIO_PB17 ( ( unsigned int ) 1 << 17 ) /* Pin Controlled by PB17 */ +#define AT91C_PB17_ERXCK ( ( unsigned int ) AT91C_PIO_PB17 ) /* Ethernet MAC Receive Clock */ +#define AT91C_PB17_NPCS03 ( ( unsigned int ) AT91C_PIO_PB17 ) /* SPI 0 Peripheral Chip Select 3 */ +#define AT91C_PIO_PB18 ( ( unsigned int ) 1 << 18 ) /* Pin Controlled by PB18 */ +#define AT91C_PB18_EF100 ( ( unsigned int ) AT91C_PIO_PB18 ) /* Ethernet MAC Force 100 Mbits/sec */ +#define AT91C_PB18_ADTRG ( ( unsigned int ) AT91C_PIO_PB18 ) /* ADC External Trigger */ +#define AT91C_PIO_PB19 ( ( unsigned int ) 1 << 19 ) /* Pin Controlled by PB19 */ +#define AT91C_PB19_PWM0 ( ( unsigned int ) AT91C_PIO_PB19 ) /* PWM Channel 0 */ +#define AT91C_PB19_TCLK1 ( ( unsigned int ) AT91C_PIO_PB19 ) /* Timer Counter 1 external clock input */ +#define AT91C_PIO_PB2 ( ( unsigned int ) 1 << 2 ) /* Pin Controlled by PB2 */ +#define AT91C_PB2_ETX0 ( ( unsigned int ) AT91C_PIO_PB2 ) /* Ethernet MAC Transmit Data 0 */ +#define AT91C_PIO_PB20 ( ( unsigned int ) 1 << 20 ) /* Pin Controlled by PB20 */ +#define AT91C_PB20_PWM1 ( ( unsigned int ) AT91C_PIO_PB20 ) /* PWM Channel 1 */ +#define AT91C_PB20_PCK0 ( ( unsigned int ) AT91C_PIO_PB20 ) /* PMC Programmable Clock Output 0 */ +#define AT91C_PIO_PB21 ( ( unsigned int ) 1 << 21 ) /* Pin Controlled by PB21 */ +#define AT91C_PB21_PWM2 ( ( unsigned int ) AT91C_PIO_PB21 ) /* PWM Channel 2 */ +#define AT91C_PB21_PCK1 ( ( unsigned int ) AT91C_PIO_PB21 ) /* PMC Programmable Clock Output 1 */ +#define AT91C_PIO_PB22 ( ( unsigned int ) 1 << 22 ) /* Pin Controlled by PB22 */ +#define AT91C_PB22_PWM3 ( ( unsigned int ) AT91C_PIO_PB22 ) /* PWM Channel 3 */ +#define AT91C_PB22_PCK2 ( ( unsigned int ) AT91C_PIO_PB22 ) /* PMC Programmable Clock Output 2 */ +#define AT91C_PIO_PB23 ( ( unsigned int ) 1 << 23 ) /* Pin Controlled by PB23 */ +#define AT91C_PB23_TIOA0 ( ( unsigned int ) AT91C_PIO_PB23 ) /* Timer Counter 0 Multipurpose Timer I/O Pin A */ +#define AT91C_PB23_DCD1 ( ( unsigned int ) AT91C_PIO_PB23 ) /* USART 1 Data Carrier Detect */ +#define AT91C_PIO_PB24 ( ( unsigned int ) 1 << 24 ) /* Pin Controlled by PB24 */ +#define AT91C_PB24_TIOB0 ( ( unsigned int ) AT91C_PIO_PB24 ) /* Timer Counter 0 Multipurpose Timer I/O Pin B */ +#define AT91C_PB24_DSR1 ( ( unsigned int ) AT91C_PIO_PB24 ) /* USART 1 Data Set ready */ +#define AT91C_PIO_PB25 ( ( unsigned int ) 1 << 25 ) /* Pin Controlled by PB25 */ +#define AT91C_PB25_TIOA1 ( ( unsigned int ) AT91C_PIO_PB25 ) /* Timer Counter 1 Multipurpose Timer I/O Pin A */ +#define AT91C_PB25_DTR1 ( ( unsigned int ) AT91C_PIO_PB25 ) /* USART 1 Data Terminal ready */ +#define AT91C_PIO_PB26 ( ( unsigned int ) 1 << 26 ) /* Pin Controlled by PB26 */ +#define AT91C_PB26_TIOB1 ( ( unsigned int ) AT91C_PIO_PB26 ) /* Timer Counter 1 Multipurpose Timer I/O Pin B */ +#define AT91C_PB26_RI1 ( ( unsigned int ) AT91C_PIO_PB26 ) /* USART 1 Ring Indicator */ +#define AT91C_PIO_PB27 ( ( unsigned int ) 1 << 27 ) /* Pin Controlled by PB27 */ +#define AT91C_PB27_TIOA2 ( ( unsigned int ) AT91C_PIO_PB27 ) /* Timer Counter 2 Multipurpose Timer I/O Pin A */ +#define AT91C_PB27_PWM0 ( ( unsigned int ) AT91C_PIO_PB27 ) /* PWM Channel 0 */ +#define AT91C_PIO_PB28 ( ( unsigned int ) 1 << 28 ) /* Pin Controlled by PB28 */ +#define AT91C_PB28_TIOB2 ( ( unsigned int ) AT91C_PIO_PB28 ) /* Timer Counter 2 Multipurpose Timer I/O Pin B */ +#define AT91C_PB28_PWM1 ( ( unsigned int ) AT91C_PIO_PB28 ) /* PWM Channel 1 */ +#define AT91C_PIO_PB29 ( ( unsigned int ) 1 << 29 ) /* Pin Controlled by PB29 */ +#define AT91C_PB29_PCK1 ( ( unsigned int ) AT91C_PIO_PB29 ) /* PMC Programmable Clock Output 1 */ +#define AT91C_PB29_PWM2 ( ( unsigned int ) AT91C_PIO_PB29 ) /* PWM Channel 2 */ +#define AT91C_PIO_PB3 ( ( unsigned int ) 1 << 3 ) /* Pin Controlled by PB3 */ +#define AT91C_PB3_ETX1 ( ( unsigned int ) AT91C_PIO_PB3 ) /* Ethernet MAC Transmit Data 1 */ +#define AT91C_PIO_PB30 ( ( unsigned int ) 1 << 30 ) /* Pin Controlled by PB30 */ +#define AT91C_PB30_PCK2 ( ( unsigned int ) AT91C_PIO_PB30 ) /* PMC Programmable Clock Output 2 */ +#define AT91C_PB30_PWM3 ( ( unsigned int ) AT91C_PIO_PB30 ) /* PWM Channel 3 */ +#define AT91C_PIO_PB4 ( ( unsigned int ) 1 << 4 ) /* Pin Controlled by PB4 */ +#define AT91C_PB4_ECRS_ECRSDV ( ( unsigned int ) AT91C_PIO_PB4 ) /* Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */ +#define AT91C_PIO_PB5 ( ( unsigned int ) 1 << 5 ) /* Pin Controlled by PB5 */ +#define AT91C_PB5_ERX0 ( ( unsigned int ) AT91C_PIO_PB5 ) /* Ethernet MAC Receive Data 0 */ +#define AT91C_PIO_PB6 ( ( unsigned int ) 1 << 6 ) /* Pin Controlled by PB6 */ +#define AT91C_PB6_ERX1 ( ( unsigned int ) AT91C_PIO_PB6 ) /* Ethernet MAC Receive Data 1 */ +#define AT91C_PIO_PB7 ( ( unsigned int ) 1 << 7 ) /* Pin Controlled by PB7 */ +#define AT91C_PB7_ERXER ( ( unsigned int ) AT91C_PIO_PB7 ) /* Ethernet MAC Receive Error */ +#define AT91C_PIO_PB8 ( ( unsigned int ) 1 << 8 ) /* Pin Controlled by PB8 */ +#define AT91C_PB8_EMDC ( ( unsigned int ) AT91C_PIO_PB8 ) /* Ethernet MAC Management Data Clock */ +#define AT91C_PIO_PB9 ( ( unsigned int ) 1 << 9 ) /* Pin Controlled by PB9 */ +#define AT91C_PB9_EMDIO ( ( unsigned int ) AT91C_PIO_PB9 ) /* Ethernet MAC Management Data Input/Output */ + +/* ***************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 */ +/* ***************************************************************************** */ +#define AT91C_ID_FIQ ( ( unsigned int ) 0 ) /* Advanced Interrupt Controller (FIQ) */ +#define AT91C_ID_SYS ( ( unsigned int ) 1 ) /* System Peripheral */ +#define AT91C_ID_PIOA ( ( unsigned int ) 2 ) /* Parallel IO Controller A */ +#define AT91C_ID_PIOB ( ( unsigned int ) 3 ) /* Parallel IO Controller B */ +#define AT91C_ID_SPI0 ( ( unsigned int ) 4 ) /* Serial Peripheral Interface 0 */ +#define AT91C_ID_SPI1 ( ( unsigned int ) 5 ) /* Serial Peripheral Interface 1 */ +#define AT91C_ID_US0 ( ( unsigned int ) 6 ) /* USART 0 */ +#define AT91C_ID_US1 ( ( unsigned int ) 7 ) /* USART 1 */ +#define AT91C_ID_SSC ( ( unsigned int ) 8 ) /* Serial Synchronous Controller */ +#define AT91C_ID_TWI ( ( unsigned int ) 9 ) /* Two-Wire Interface */ +#define AT91C_ID_PWMC ( ( unsigned int ) 10 ) /* PWM Controller */ +#define AT91C_ID_UDP ( ( unsigned int ) 11 ) /* USB Device Port */ +#define AT91C_ID_TC0 ( ( unsigned int ) 12 ) /* Timer Counter 0 */ +#define AT91C_ID_TC1 ( ( unsigned int ) 13 ) /* Timer Counter 1 */ +#define AT91C_ID_TC2 ( ( unsigned int ) 14 ) /* Timer Counter 2 */ +#define AT91C_ID_CAN ( ( unsigned int ) 15 ) /* Control Area Network Controller */ +#define AT91C_ID_EMAC ( ( unsigned int ) 16 ) /* Ethernet MAC */ +#define AT91C_ID_ADC ( ( unsigned int ) 17 ) /* Analog-to-Digital Converter */ +#define AT91C_ID_AES ( ( unsigned int ) 18 ) /* Advanced Encryption Standard 128-bit */ +#define AT91C_ID_TDES ( ( unsigned int ) 19 ) /* Triple Data Encryption Standard */ +#define AT91C_ID_20_Reserved ( ( unsigned int ) 20 ) /* Reserved */ +#define AT91C_ID_21_Reserved ( ( unsigned int ) 21 ) /* Reserved */ +#define AT91C_ID_22_Reserved ( ( unsigned int ) 22 ) /* Reserved */ +#define AT91C_ID_23_Reserved ( ( unsigned int ) 23 ) /* Reserved */ +#define AT91C_ID_24_Reserved ( ( unsigned int ) 24 ) /* Reserved */ +#define AT91C_ID_25_Reserved ( ( unsigned int ) 25 ) /* Reserved */ +#define AT91C_ID_26_Reserved ( ( unsigned int ) 26 ) /* Reserved */ +#define AT91C_ID_27_Reserved ( ( unsigned int ) 27 ) /* Reserved */ +#define AT91C_ID_28_Reserved ( ( unsigned int ) 28 ) /* Reserved */ +#define AT91C_ID_29_Reserved ( ( unsigned int ) 29 ) /* Reserved */ +#define AT91C_ID_IRQ0 ( ( unsigned int ) 30 ) /* Advanced Interrupt Controller (IRQ0) */ +#define AT91C_ID_IRQ1 ( ( unsigned int ) 31 ) /* Advanced Interrupt Controller (IRQ1) */ + +/* ***************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 */ +/* ***************************************************************************** */ +#define AT91C_BASE_SYS ( ( AT91PS_SYS ) 0xFFFFF000 ) /* (SYS) Base Address */ +#define AT91C_BASE_AIC ( ( AT91PS_AIC ) 0xFFFFF000 ) /* (AIC) Base Address */ +#define AT91C_BASE_PDC_DBGU ( ( AT91PS_PDC ) 0xFFFFF300 ) /* (PDC_DBGU) Base Address */ +#define AT91C_BASE_DBGU ( ( AT91PS_DBGU ) 0xFFFFF200 ) /* (DBGU) Base Address */ +#define AT91C_BASE_PIOA ( ( AT91PS_PIO ) 0xFFFFF400 ) /* (PIOA) Base Address */ +#define AT91C_BASE_PIOB ( ( AT91PS_PIO ) 0xFFFFF600 ) /* (PIOB) Base Address */ +#define AT91C_BASE_CKGR ( ( AT91PS_CKGR ) 0xFFFFFC20 ) /* (CKGR) Base Address */ +#define AT91C_BASE_PMC ( ( AT91PS_PMC ) 0xFFFFFC00 ) /* (PMC) Base Address */ +#define AT91C_BASE_RSTC ( ( AT91PS_RSTC ) 0xFFFFFD00 ) /* (RSTC) Base Address */ +#define AT91C_BASE_RTTC ( ( AT91PS_RTTC ) 0xFFFFFD20 ) /* (RTTC) Base Address */ +#define AT91C_BASE_PITC ( ( AT91PS_PITC ) 0xFFFFFD30 ) /* (PITC) Base Address */ +#define AT91C_BASE_WDTC ( ( AT91PS_WDTC ) 0xFFFFFD40 ) /* (WDTC) Base Address */ +#define AT91C_BASE_VREG ( ( AT91PS_VREG ) 0xFFFFFD60 ) /* (VREG) Base Address */ +#define AT91C_BASE_MC ( ( AT91PS_MC ) 0xFFFFFF00 ) /* (MC) Base Address */ +#define AT91C_BASE_PDC_SPI1 ( ( AT91PS_PDC ) 0xFFFE4100 ) /* (PDC_SPI1) Base Address */ +#define AT91C_BASE_SPI1 ( ( AT91PS_SPI ) 0xFFFE4000 ) /* (SPI1) Base Address */ +#define AT91C_BASE_PDC_SPI0 ( ( AT91PS_PDC ) 0xFFFE0100 ) /* (PDC_SPI0) Base Address */ +#define AT91C_BASE_SPI0 ( ( AT91PS_SPI ) 0xFFFE0000 ) /* (SPI0) Base Address */ +#define AT91C_BASE_PDC_US1 ( ( AT91PS_PDC ) 0xFFFC4100 ) /* (PDC_US1) Base Address */ +#define AT91C_BASE_US1 ( ( AT91PS_USART ) 0xFFFC4000 ) /* (US1) Base Address */ +#define AT91C_BASE_PDC_US0 ( ( AT91PS_PDC ) 0xFFFC0100 ) /* (PDC_US0) Base Address */ +#define AT91C_BASE_US0 ( ( AT91PS_USART ) 0xFFFC0000 ) /* (US0) Base Address */ +#define AT91C_BASE_PDC_SSC ( ( AT91PS_PDC ) 0xFFFD4100 ) /* (PDC_SSC) Base Address */ +#define AT91C_BASE_SSC ( ( AT91PS_SSC ) 0xFFFD4000 ) /* (SSC) Base Address */ +#define AT91C_BASE_TWI ( ( AT91PS_TWI ) 0xFFFB8000 ) /* (TWI) Base Address */ +#define AT91C_BASE_PWMC_CH3 ( ( AT91PS_PWMC_CH ) 0xFFFCC260 ) /* (PWMC_CH3) Base Address */ +#define AT91C_BASE_PWMC_CH2 ( ( AT91PS_PWMC_CH ) 0xFFFCC240 ) /* (PWMC_CH2) Base Address */ +#define AT91C_BASE_PWMC_CH1 ( ( AT91PS_PWMC_CH ) 0xFFFCC220 ) /* (PWMC_CH1) Base Address */ +#define AT91C_BASE_PWMC_CH0 ( ( AT91PS_PWMC_CH ) 0xFFFCC200 ) /* (PWMC_CH0) Base Address */ +#define AT91C_BASE_PWMC ( ( AT91PS_PWMC ) 0xFFFCC000 ) /* (PWMC) Base Address */ +#define AT91C_BASE_UDP ( ( AT91PS_UDP ) 0xFFFB0000 ) /* (UDP) Base Address */ +#define AT91C_BASE_TC0 ( ( AT91PS_TC ) 0xFFFA0000 ) /* (TC0) Base Address */ +#define AT91C_BASE_TC1 ( ( AT91PS_TC ) 0xFFFA0040 ) /* (TC1) Base Address */ +#define AT91C_BASE_TC2 ( ( AT91PS_TC ) 0xFFFA0080 ) /* (TC2) Base Address */ +#define AT91C_BASE_TCB ( ( AT91PS_TCB ) 0xFFFA0000 ) /* (TCB) Base Address */ +#define AT91C_BASE_CAN_MB0 ( ( AT91PS_CAN_MB ) 0xFFFD0200 ) /* (CAN_MB0) Base Address */ +#define AT91C_BASE_CAN_MB1 ( ( AT91PS_CAN_MB ) 0xFFFD0220 ) /* (CAN_MB1) Base Address */ +#define AT91C_BASE_CAN_MB2 ( ( AT91PS_CAN_MB ) 0xFFFD0240 ) /* (CAN_MB2) Base Address */ +#define AT91C_BASE_CAN_MB3 ( ( AT91PS_CAN_MB ) 0xFFFD0260 ) /* (CAN_MB3) Base Address */ +#define AT91C_BASE_CAN_MB4 ( ( AT91PS_CAN_MB ) 0xFFFD0280 ) /* (CAN_MB4) Base Address */ +#define AT91C_BASE_CAN_MB5 ( ( AT91PS_CAN_MB ) 0xFFFD02A0 ) /* (CAN_MB5) Base Address */ +#define AT91C_BASE_CAN_MB6 ( ( AT91PS_CAN_MB ) 0xFFFD02C0 ) /* (CAN_MB6) Base Address */ +#define AT91C_BASE_CAN_MB7 ( ( AT91PS_CAN_MB ) 0xFFFD02E0 ) /* (CAN_MB7) Base Address */ +#define AT91C_BASE_CAN ( ( AT91PS_CAN ) 0xFFFD0000 ) /* (CAN) Base Address */ +#define AT91C_BASE_EMAC ( ( AT91PS_EMAC ) 0xFFFDC000 ) /* (EMAC) Base Address */ +#define AT91C_BASE_PDC_ADC ( ( AT91PS_PDC ) 0xFFFD8100 ) /* (PDC_ADC) Base Address */ +#define AT91C_BASE_ADC ( ( AT91PS_ADC ) 0xFFFD8000 ) /* (ADC) Base Address */ +#define AT91C_BASE_PDC_AES ( ( AT91PS_PDC ) 0xFFFA4100 ) /* (PDC_AES) Base Address */ +#define AT91C_BASE_AES ( ( AT91PS_AES ) 0xFFFA4000 ) /* (AES) Base Address */ +#define AT91C_BASE_PDC_TDES ( ( AT91PS_PDC ) 0xFFFA8100 ) /* (PDC_TDES) Base Address */ +#define AT91C_BASE_TDES ( ( AT91PS_TDES ) 0xFFFA8000 ) /* (TDES) Base Address */ + +/* ***************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 */ +/* ***************************************************************************** */ +#define AT91C_ISRAM ( ( char * ) 0x00200000 ) /* Internal SRAM base address */ +#define AT91C_ISRAM_SIZE ( ( unsigned int ) 0x00010000 ) /* Internal SRAM size in byte (64 Kbyte) */ +#define AT91C_IFLASH ( ( char * ) 0x00100000 ) /* Internal ROM base address */ +#define AT91C_IFLASH_SIZE ( ( unsigned int ) 0x00040000 ) /* Internal ROM size in byte (256 Kbyte) */ + + + +/* - Hardware register definition */ + +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR System Peripherals */ +/* - ***************************************************************************** */ + +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Advanced Interrupt Controller */ +/* - ***************************************************************************** */ +/* - -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */ +#if 0 /*_RB_*/ + AT91C_AIC_PRIOR EQU( 0x7 << 0 ); + -( AIC ) Priority Level + AT91C_AIC_PRIOR_LOWEST EQU( 0x0 ); + -( AIC ) Lowest priority level + AT91C_AIC_PRIOR_HIGHEST EQU( 0x7 ); + -( AIC ) Highest priority level + AT91C_AIC_SRCTYPE EQU( 0x3 << 5 ); + -( AIC ) Interrupt Source Type + AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL EQU( 0x0 << 5 ); + -( AIC ) Internal Sources Code Label High - level Sensitive + AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL EQU( 0x0 << 5 ); + -( AIC ) External Sources Code Label Low - level Sensitive + AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE EQU( 0x1 << 5 ); + -( AIC ) Internal Sources Code Label Positive Edge triggered + AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE EQU( 0x1 << 5 ); + -( AIC ) External Sources Code Label Negative Edge triggered + AT91C_AIC_SRCTYPE_HIGH_LEVEL EQU( 0x2 << 5 ); + -( AIC ) Internal Or External Sources Code Label High - level Sensitive + AT91C_AIC_SRCTYPE_POSITIVE_EDGE EQU( 0x3 << 5 ); + -( AIC ) Internal Or External Sources Code Label Positive Edge triggered +/* - -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- */ + AT91C_AIC_NFIQ EQU( 0x1 << 0 ); + -( AIC ) NFIQ Status + AT91C_AIC_NIRQ EQU( 0x1 << 1 ); + -( AIC ) NIRQ Status +/* - -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- */ + AT91C_AIC_DCR_PROT EQU( 0x1 << 0 ); + -( AIC ) Protection Mode + AT91C_AIC_DCR_GMSK EQU( 0x1 << 1 ); + -( AIC ) General Mask +#endif /* if 0 */ +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Peripheral DMA Controller */ +/* - ***************************************************************************** */ +/* - -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */ +AT91C_PDC_RXTEN EQU( 0x1 << 0 ); +-( PDC ) Receiver Transfer Enable +AT91C_PDC_RXTDIS EQU( 0x1 << 1 ); +-( PDC ) Receiver Transfer Disable +AT91C_PDC_TXTEN EQU( 0x1 << 8 ); +-( PDC ) Transmitter Transfer Enable +AT91C_PDC_TXTDIS EQU( 0x1 << 9 ); +-( PDC ) Transmitter Transfer Disable +/* - -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */ + +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Debug Unit */ +/* - ***************************************************************************** */ +/* - -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */ +AT91C_US_RSTRX EQU( 0x1 << 2 ); +-( DBGU ) Reset Receiver +AT91C_US_RSTTX EQU( 0x1 << 3 ); +-( DBGU ) Reset Transmitter +AT91C_US_RXEN EQU( 0x1 << 4 ); +-( DBGU ) Receiver Enable +AT91C_US_RXDIS EQU( 0x1 << 5 ); +-( DBGU ) Receiver Disable +AT91C_US_TXEN EQU( 0x1 << 6 ); +-( DBGU ) Transmitter Enable +AT91C_US_TXDIS EQU( 0x1 << 7 ); +-( DBGU ) Transmitter Disable +AT91C_US_RSTSTA EQU( 0x1 << 8 ); +-( DBGU ) Reset Status Bits +/* - -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- */ +AT91C_US_PAR EQU( 0x7 << 9 ); +-( DBGU ) Parity type +AT91C_US_PAR_EVEN EQU( 0x0 << 9 ); +-( DBGU ) Even Parity +AT91C_US_PAR_ODD EQU( 0x1 << 9 ); +-( DBGU ) Odd Parity +AT91C_US_PAR_SPACE EQU( 0x2 << 9 ); +-( DBGU ) Parity forced to 0 ( Space ) +AT91C_US_PAR_MARK EQU( 0x3 << 9 ); +-( DBGU ) Parity forced to 1 ( Mark ) +AT91C_US_PAR_NONE EQU( 0x4 << 9 ); +-( DBGU ) No Parity +AT91C_US_PAR_MULTI_DROP EQU( 0x6 << 9 ); +-( DBGU ) Multi - drop mode +AT91C_US_CHMODE EQU( 0x3 << 14 ); +-( DBGU ) Channel Mode +AT91C_US_CHMODE_NORMAL EQU( 0x0 << 14 ); +-( DBGU ) Normal Mode: The USART channel operates as an RX / TX USART. + AT91C_US_CHMODE_AUTO EQU( 0x1 << 14 ); +-( DBGU ) Automatic Echo: Receiver Data Input is connected to the TXD pin. + AT91C_US_CHMODE_LOCAL EQU( 0x2 << 14 ); +-( DBGU ) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. + AT91C_US_CHMODE_REMOTE EQU( 0x3 << 14 ); +-( DBGU ) Remote Loopback: RXD pin is internally connected to TXD pin. +/* - -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ + AT91C_US_RXRDY EQU( 0x1 << 0 ); +-( DBGU ) RXRDY Interrupt +AT91C_US_TXRDY EQU( 0x1 << 1 ); +-( DBGU ) TXRDY Interrupt +AT91C_US_ENDRX EQU( 0x1 << 3 ); +-( DBGU ) End of Receive Transfer Interrupt +AT91C_US_ENDTX EQU( 0x1 << 4 ); +-( DBGU ) End of Transmit Interrupt +AT91C_US_OVRE EQU( 0x1 << 5 ); +-( DBGU ) Overrun Interrupt +AT91C_US_FRAME EQU( 0x1 << 6 ); +-( DBGU ) Framing Error Interrupt +AT91C_US_PARE EQU( 0x1 << 7 ); +-( DBGU ) Parity Error Interrupt +AT91C_US_TXEMPTY EQU( 0x1 << 9 ); +-( DBGU ) TXEMPTY Interrupt +AT91C_US_TXBUFE EQU( 0x1 << 11 ); +-( DBGU ) TXBUFE Interrupt +AT91C_US_RXBUFF EQU( 0x1 << 12 ); +-( DBGU ) RXBUFF Interrupt +AT91C_US_COMM_TX EQU( 0x1 << 30 ); +-( DBGU ) COMM_TX Interrupt +AT91C_US_COMM_RX EQU( 0x1 << 31 ); +-( DBGU ) COMM_RX Interrupt +/* - -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- */ +/* - -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- */ +/* - -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- */ +/* - -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- */ +AT91C_US_FORCE_NTRST EQU( 0x1 << 0 ); +-( DBGU ) Force NTRST in JTAG + +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Parallel Input Output Controller */ +/* - ***************************************************************************** */ + +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Clock Generator Controller */ +/* - ***************************************************************************** */ +/* - -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */ +AT91C_CKGR_MOSCEN EQU( 0x1 << 0 ); +-( CKGR ) Main Oscillator Enable +AT91C_CKGR_OSCBYPASS EQU( 0x1 << 1 ); +-( CKGR ) Main Oscillator Bypass +AT91C_CKGR_OSCOUNT EQU( 0xFF << 8 ); +-( CKGR ) Main Oscillator Start - up Time +/* - -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */ +AT91C_CKGR_MAINF EQU( 0xFFFF << 0 ); +-( CKGR ) Main Clock Frequency +AT91C_CKGR_MAINRDY EQU( 0x1 << 16 ); +-( CKGR ) Main Clock Ready +/* - -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- */ +AT91C_CKGR_DIV EQU( 0xFF << 0 ); +-( CKGR ) Divider Selected +AT91C_CKGR_DIV_0 EQU( 0x0 ); +-( CKGR ) Divider output is 0 +AT91C_CKGR_DIV_BYPASS EQU( 0x1 ); +-( CKGR ) Divider is bypassed +AT91C_CKGR_PLLCOUNT EQU( 0x3F << 8 ); +-( CKGR ) PLL Counter +AT91C_CKGR_OUT EQU( 0x3 << 14 ); +-( CKGR ) PLL Output Frequency Range +AT91C_CKGR_OUT_0 EQU( 0x0 << 14 ); +-( CKGR ) Please refer to the PLL datasheet +AT91C_CKGR_OUT_1 EQU( 0x1 << 14 ); +-( CKGR ) Please refer to the PLL datasheet +AT91C_CKGR_OUT_2 EQU( 0x2 << 14 ); +-( CKGR ) Please refer to the PLL datasheet +AT91C_CKGR_OUT_3 EQU( 0x3 << 14 ); +-( CKGR ) Please refer to the PLL datasheet +AT91C_CKGR_MUL EQU( 0x7FF << 16 ); +-( CKGR ) PLL Multiplier +AT91C_CKGR_USBDIV EQU( 0x3 << 28 ); +-( CKGR ) Divider + +for USB Clocks +AT91C_CKGR_USBDIV_0 EQU( 0x0 << 28 ); +-( CKGR ) Divider output is PLL clock output +AT91C_CKGR_USBDIV_1 EQU( 0x1 << 28 ); +-( CKGR ) Divider output is PLL clock output divided by 2 +AT91C_CKGR_USBDIV_2 EQU( 0x2 << 28 ); +-( CKGR ) Divider output is PLL clock output divided by 4 + +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Power Management Controller */ +/* - ***************************************************************************** */ +/* - -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- */ +AT91C_PMC_PCK EQU( 0x1 << 0 ); +-( PMC ) Processor Clock +AT91C_PMC_UDP EQU( 0x1 << 7 ); +-( PMC ) USB Device Port Clock +AT91C_PMC_PCK0 EQU( 0x1 << 8 ); +-( PMC ) Programmable Clock Output +AT91C_PMC_PCK1 EQU( 0x1 << 9 ); +-( PMC ) Programmable Clock Output +AT91C_PMC_PCK2 EQU( 0x1 << 10 ); +-( PMC ) Programmable Clock Output +AT91C_PMC_PCK3 EQU( 0x1 << 11 ); +-( PMC ) Programmable Clock Output +/* - -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- */ +/* - -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- */ +/* - -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- */ +/* - -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- */ +/* - -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- */ +/* - -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */ +AT91C_PMC_CSS EQU( 0x3 << 0 ); +-( PMC ) Programmable Clock Selection +AT91C_PMC_CSS_SLOW_CLK EQU( 0x0 ); +-( PMC ) Slow Clock is selected +AT91C_PMC_CSS_MAIN_CLK EQU( 0x1 ); +-( PMC ) Main Clock is selected +AT91C_PMC_CSS_PLL_CLK EQU( 0x3 ); +-( PMC ) Clock from PLL is selected +AT91C_PMC_PRES EQU( 0x7 << 2 ); +-( PMC ) Programmable Clock Prescaler +AT91C_PMC_PRES_CLK EQU( 0x0 << 2 ); +-( PMC ) Selected clock +AT91C_PMC_PRES_CLK_2 EQU( 0x1 << 2 ); +-( PMC ) Selected clock divided by 2 +AT91C_PMC_PRES_CLK_4 EQU( 0x2 << 2 ); +-( PMC ) Selected clock divided by 4 +AT91C_PMC_PRES_CLK_8 EQU( 0x3 << 2 ); +-( PMC ) Selected clock divided by 8 +AT91C_PMC_PRES_CLK_16 EQU( 0x4 << 2 ); +-( PMC ) Selected clock divided by 16 +AT91C_PMC_PRES_CLK_32 EQU( 0x5 << 2 ); +-( PMC ) Selected clock divided by 32 +AT91C_PMC_PRES_CLK_64 EQU( 0x6 << 2 ); +-( PMC ) Selected clock divided by 64 +/* - -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- */ +/* - -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- */ +AT91C_PMC_MOSCS EQU( 0x1 << 0 ); +-( PMC ) MOSC Status / Enable / Disable / Mask +AT91C_PMC_LOCK EQU( 0x1 << 2 ); +-( PMC ) PLL Status / Enable / Disable / Mask +AT91C_PMC_MCKRDY EQU( 0x1 << 3 ); +-( PMC ) MCK_RDY Status / Enable / Disable / Mask +AT91C_PMC_PCK0RDY EQU( 0x1 << 8 ); +-( PMC ) PCK0_RDY Status / Enable / Disable / Mask +AT91C_PMC_PCK1RDY EQU( 0x1 << 9 ); +-( PMC ) PCK1_RDY Status / Enable / Disable / Mask +AT91C_PMC_PCK2RDY EQU( 0x1 << 10 ); +-( PMC ) PCK2_RDY Status / Enable / Disable / Mask +AT91C_PMC_PCK3RDY EQU( 0x1 << 11 ); +-( PMC ) PCK3_RDY Status / Enable / Disable / Mask +/* - -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */ +/* - -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- */ +/* - -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- */ + +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Reset Controller Interface */ +/* - ***************************************************************************** */ +/* - -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- */ +AT91C_RSTC_PROCRST EQU( 0x1 << 0 ); +-( RSTC ) Processor Reset +AT91C_RSTC_PERRST EQU( 0x1 << 2 ); +-( RSTC ) Peripheral Reset +AT91C_RSTC_EXTRST EQU( 0x1 << 3 ); +-( RSTC ) External Reset +AT91C_RSTC_KEY EQU( 0xFF << 24 ); +-( RSTC ) Password +/* - -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- */ +AT91C_RSTC_URSTS EQU( 0x1 << 0 ); +-( RSTC ) User Reset Status +AT91C_RSTC_BODSTS EQU( 0x1 << 1 ); +-( RSTC ) Brownout Detection Status +AT91C_RSTC_RSTTYP EQU( 0x7 << 8 ); +-( RSTC ) Reset Type +AT91C_RSTC_RSTTYP_POWERUP EQU( 0x0 << 8 ); +-( RSTC ) Power - up Reset.VDDCORE rising. + AT91C_RSTC_RSTTYP_WAKEUP EQU( 0x1 << 8 ); +-( RSTC ) WakeUp Reset.VDDCORE rising. + AT91C_RSTC_RSTTYP_WATCHDOG EQU( 0x2 << 8 ); +-( RSTC ) Watchdog Reset.Watchdog overflow occurred. + AT91C_RSTC_RSTTYP_SOFTWARE EQU( 0x3 << 8 ); +-( RSTC ) Software Reset.Processor reset required by the software. + AT91C_RSTC_RSTTYP_USER EQU( 0x4 << 8 ); +-( RSTC ) User Reset.NRST pin detected low. + AT91C_RSTC_RSTTYP_BROWNOUT EQU( 0x5 << 8 ); +-( RSTC ) Brownout Reset occurred. + AT91C_RSTC_NRSTL EQU( 0x1 << 16 ); +-( RSTC ) NRST pin level +AT91C_RSTC_SRCMP EQU( 0x1 << 17 ); +-( RSTC ) Software Reset Command in Progress. +/* - -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- */ + AT91C_RSTC_URSTEN EQU( 0x1 << 0 ); +-( RSTC ) User Reset Enable +AT91C_RSTC_URSTIEN EQU( 0x1 << 4 ); +-( RSTC ) User Reset Interrupt Enable +AT91C_RSTC_ERSTL EQU( 0xF << 8 ); +-( RSTC ) User Reset Enable +AT91C_RSTC_BODIEN EQU( 0x1 << 16 ); +-( RSTC ) Brownout Detection Interrupt Enable + +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface */ +/* - ***************************************************************************** */ +/* - -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- */ +AT91C_RTTC_RTPRES EQU( 0xFFFF << 0 ); +-( RTTC ) Real - time Timer Prescaler Value +AT91C_RTTC_ALMIEN EQU( 0x1 << 16 ); +-( RTTC ) Alarm Interrupt Enable +AT91C_RTTC_RTTINCIEN EQU( 0x1 << 17 ); +-( RTTC ) Real Time Timer Increment Interrupt Enable +AT91C_RTTC_RTTRST EQU( 0x1 << 18 ); +-( RTTC ) Real Time Timer Restart +/* - -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- */ +AT91C_RTTC_ALMV EQU( 0x0 << 0 ); +-( RTTC ) Alarm Value +/* - -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- */ +AT91C_RTTC_CRTV EQU( 0x0 << 0 ); +-( RTTC ) Current Real - time Value +/* - -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- */ +AT91C_RTTC_ALMS EQU( 0x1 << 0 ); +-( RTTC ) Real - time Alarm Status +AT91C_RTTC_RTTINC EQU( 0x1 << 1 ); +-( RTTC ) Real - time Timer Increment + +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface */ +/* - ***************************************************************************** */ +/* - -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- */ +AT91C_PITC_PIV EQU( 0xFFFFF << 0 ); +-( PITC ) Periodic Interval Value +AT91C_PITC_PITEN EQU( 0x1 << 24 ); +-( PITC ) Periodic Interval Timer Enabled +AT91C_PITC_PITIEN EQU( 0x1 << 25 ); +-( PITC ) Periodic Interval Timer Interrupt Enable +/* - -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- */ +AT91C_PITC_PITS EQU( 0x1 << 0 ); +-( PITC ) Periodic Interval Timer Status +/* - -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- */ +AT91C_PITC_CPIV EQU( 0xFFFFF << 0 ); +-( PITC ) Current Periodic Interval Value +AT91C_PITC_PICNT EQU( 0xFFF << 20 ); +-( PITC ) Periodic Interval Counter +/* - -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- */ + +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface */ +/* - ***************************************************************************** */ +/* - -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- */ +AT91C_WDTC_WDRSTT EQU( 0x1 << 0 ); +-( WDTC ) Watchdog Restart +AT91C_WDTC_KEY EQU( 0xFF << 24 ); +-( WDTC ) Watchdog KEY Password +/* - -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */ +AT91C_WDTC_WDV EQU( 0xFFF << 0 ); +-( WDTC ) Watchdog Timer Restart +AT91C_WDTC_WDFIEN EQU( 0x1 << 12 ); +-( WDTC ) Watchdog Fault Interrupt Enable +AT91C_WDTC_WDRSTEN EQU( 0x1 << 13 ); +-( WDTC ) Watchdog Reset Enable +AT91C_WDTC_WDRPROC EQU( 0x1 << 14 ); +-( WDTC ) Watchdog Timer Restart +AT91C_WDTC_WDDIS EQU( 0x1 << 15 ); +-( WDTC ) Watchdog Disable +AT91C_WDTC_WDD EQU( 0xFFF << 16 ); +-( WDTC ) Watchdog Delta Value +AT91C_WDTC_WDDBGHLT EQU( 0x1 << 28 ); +-( WDTC ) Watchdog Debug Halt +AT91C_WDTC_WDIDLEHLT EQU( 0x1 << 29 ); +-( WDTC ) Watchdog Idle Halt +/* - -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- */ +AT91C_WDTC_WDUNF EQU( 0x1 << 0 ); +-( WDTC ) Watchdog Underflow +AT91C_WDTC_WDERR EQU( 0x1 << 1 ); +-( WDTC ) Watchdog Error + +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface */ +/* - ***************************************************************************** */ +/* - -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- */ +AT91C_VREG_PSTDBY EQU( 0x1 << 0 ); +-( VREG ) Voltage Regulator Power Standby Mode + +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Memory Controller Interface */ +/* - ***************************************************************************** */ +/* - -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */ +AT91C_MC_RCB EQU( 0x1 << 0 ); +-( MC ) Remap Command Bit +/* - -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */ +AT91C_MC_UNDADD EQU( 0x1 << 0 ); +-( MC ) Undefined Address Abort Status +AT91C_MC_MISADD EQU( 0x1 << 1 ); +-( MC ) Misaligned Address Abort Status +AT91C_MC_ABTSZ EQU( 0x3 << 8 ); +-( MC ) Abort Size Status +AT91C_MC_ABTSZ_BYTE EQU( 0x0 << 8 ); +-( MC ) Byte +AT91C_MC_ABTSZ_HWORD EQU( 0x1 << 8 ); +-( MC ) Half - word +AT91C_MC_ABTSZ_WORD EQU( 0x2 << 8 ); +-( MC ) Word +AT91C_MC_ABTTYP EQU( 0x3 << 10 ); +-( MC ) Abort Type Status +AT91C_MC_ABTTYP_DATAR EQU( 0x0 << 10 ); +-( MC ) Data Read +AT91C_MC_ABTTYP_DATAW EQU( 0x1 << 10 ); +-( MC ) Data Write +AT91C_MC_ABTTYP_FETCH EQU( 0x2 << 10 ); +-( MC ) Code Fetch +AT91C_MC_MST0 EQU( 0x1 << 16 ); +-( MC ) Master 0 Abort Source +AT91C_MC_MST1 EQU( 0x1 << 17 ); +-( MC ) Master 1 Abort Source +AT91C_MC_SVMST0 EQU( 0x1 << 24 ); +-( MC ) Saved Master 0 Abort Source +AT91C_MC_SVMST1 EQU( 0x1 << 25 ); +-( MC ) Saved Master 1 Abort Source +/* - -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- */ +AT91C_MC_FRDY EQU( 0x1 << 0 ); +-( MC ) Flash Ready +AT91C_MC_LOCKE EQU( 0x1 << 2 ); +-( MC ) Lock Error +AT91C_MC_PROGE EQU( 0x1 << 3 ); +-( MC ) Programming Error +AT91C_MC_NEBP EQU( 0x1 << 7 ); +-( MC ) No Erase Before Programming +AT91C_MC_FWS EQU( 0x3 << 8 ); +-( MC ) Flash Wait State +AT91C_MC_FWS_0FWS EQU( 0x0 << 8 ); +-( MC ) 1 cycle + +for Read, 2 + +for Write operations +AT91C_MC_FWS_1FWS EQU( 0x1 << 8 ); +-( MC ) 2 cycles + +for Read, 3 + +for Write operations +AT91C_MC_FWS_2FWS EQU( 0x2 << 8 ); +-( MC ) 3 cycles + +for Read, 4 + +for Write operations +AT91C_MC_FWS_3FWS EQU( 0x3 << 8 ); +-( MC ) 4 cycles + +for Read, 4 + +for Write operations +AT91C_MC_FMCN EQU( 0xFF << 16 ); +-( MC ) Flash Microsecond Cycle Number +/* - -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- */ +AT91C_MC_FCMD EQU( 0xF << 0 ); +-( MC ) Flash Command +AT91C_MC_FCMD_START_PROG EQU( 0x1 ); +-( MC ) Starts the programming of th epage specified by PAGEN. + AT91C_MC_FCMD_LOCK EQU( 0x2 ); +-( MC ) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. + AT91C_MC_FCMD_PROG_AND_LOCK EQU( 0x3 ); +-( MC ) The lock sequence automatically happens after the programming sequence is completed. + AT91C_MC_FCMD_UNLOCK EQU( 0x4 ); +-( MC ) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. + AT91C_MC_FCMD_ERASE_ALL EQU( 0x8 ); +-( MC ) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. + AT91C_MC_FCMD_SET_GP_NVM EQU( 0xB ); +-( MC ) Set General Purpose NVM bits. + AT91C_MC_FCMD_CLR_GP_NVM EQU( 0xD ); +-( MC ) Clear General Purpose NVM bits. + AT91C_MC_FCMD_SET_SECURITY EQU( 0xF ); +-( MC ) Set Security Bit. + AT91C_MC_PAGEN EQU( 0x3FF << 8 ); +-( MC ) Page Number +AT91C_MC_KEY EQU( 0xFF << 24 ); +-( MC ) Writing Protect Key +/* - -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- */ +AT91C_MC_SECURITY EQU( 0x1 << 4 ); +-( MC ) Security Bit Status +AT91C_MC_GPNVM0 EQU( 0x1 << 8 ); +-( MC ) Sector 0 Lock Status +AT91C_MC_GPNVM1 EQU( 0x1 << 9 ); +-( MC ) Sector 1 Lock Status +AT91C_MC_GPNVM2 EQU( 0x1 << 10 ); +-( MC ) Sector 2 Lock Status +AT91C_MC_GPNVM3 EQU( 0x1 << 11 ); +-( MC ) Sector 3 Lock Status +AT91C_MC_GPNVM4 EQU( 0x1 << 12 ); +-( MC ) Sector 4 Lock Status +AT91C_MC_GPNVM5 EQU( 0x1 << 13 ); +-( MC ) Sector 5 Lock Status +AT91C_MC_GPNVM6 EQU( 0x1 << 14 ); +-( MC ) Sector 6 Lock Status +AT91C_MC_GPNVM7 EQU( 0x1 << 15 ); +-( MC ) Sector 7 Lock Status +AT91C_MC_LOCKS0 EQU( 0x1 << 16 ); +-( MC ) Sector 0 Lock Status +AT91C_MC_LOCKS1 EQU( 0x1 << 17 ); +-( MC ) Sector 1 Lock Status +AT91C_MC_LOCKS2 EQU( 0x1 << 18 ); +-( MC ) Sector 2 Lock Status +AT91C_MC_LOCKS3 EQU( 0x1 << 19 ); +-( MC ) Sector 3 Lock Status +AT91C_MC_LOCKS4 EQU( 0x1 << 20 ); +-( MC ) Sector 4 Lock Status +AT91C_MC_LOCKS5 EQU( 0x1 << 21 ); +-( MC ) Sector 5 Lock Status +AT91C_MC_LOCKS6 EQU( 0x1 << 22 ); +-( MC ) Sector 6 Lock Status +AT91C_MC_LOCKS7 EQU( 0x1 << 23 ); +-( MC ) Sector 7 Lock Status +AT91C_MC_LOCKS8 EQU( 0x1 << 24 ); +-( MC ) Sector 8 Lock Status +AT91C_MC_LOCKS9 EQU( 0x1 << 25 ); +-( MC ) Sector 9 Lock Status +AT91C_MC_LOCKS10 EQU( 0x1 << 26 ); +-( MC ) Sector 10 Lock Status +AT91C_MC_LOCKS11 EQU( 0x1 << 27 ); +-( MC ) Sector 11 Lock Status +AT91C_MC_LOCKS12 EQU( 0x1 << 28 ); +-( MC ) Sector 12 Lock Status +AT91C_MC_LOCKS13 EQU( 0x1 << 29 ); +-( MC ) Sector 13 Lock Status +AT91C_MC_LOCKS14 EQU( 0x1 << 30 ); +-( MC ) Sector 14 Lock Status +AT91C_MC_LOCKS15 EQU( 0x1 << 31 ); +-( MC ) Sector 15 Lock Status + +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Serial Parallel Interface */ +/* - ***************************************************************************** */ +/* - -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */ +AT91C_SPI_SPIEN EQU( 0x1 << 0 ); +-( SPI ) SPI Enable +AT91C_SPI_SPIDIS EQU( 0x1 << 1 ); +-( SPI ) SPI Disable +AT91C_SPI_SWRST EQU( 0x1 << 7 ); +-( SPI ) SPI Software reset +AT91C_SPI_LASTXFER EQU( 0x1 << 24 ); +-( SPI ) SPI Last Transfer +/* - -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */ +AT91C_SPI_MSTR EQU( 0x1 << 0 ); +-( SPI ) Master / Slave Mode +AT91C_SPI_PS EQU( 0x1 << 1 ); +-( SPI ) Peripheral Select +AT91C_SPI_PS_FIXED EQU( 0x0 << 1 ); +-( SPI ) Fixed Peripheral Select +AT91C_SPI_PS_VARIABLE EQU( 0x1 << 1 ); +-( SPI ) Variable Peripheral Select +AT91C_SPI_PCSDEC EQU( 0x1 << 2 ); +-( SPI ) Chip Select Decode +AT91C_SPI_FDIV EQU( 0x1 << 3 ); +-( SPI ) Clock Selection +AT91C_SPI_MODFDIS EQU( 0x1 << 4 ); +-( SPI ) Mode Fault Detection +AT91C_SPI_LLB EQU( 0x1 << 7 ); +-( SPI ) Clock Selection +AT91C_SPI_PCS EQU( 0xF << 16 ); +-( SPI ) Peripheral Chip Select +AT91C_SPI_DLYBCS EQU( 0xFF << 24 ); +-( SPI ) Delay Between Chip Selects +/* - -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */ +AT91C_SPI_RD EQU( 0xFFFF << 0 ); +-( SPI ) Receive Data +AT91C_SPI_RPCS EQU( 0xF << 16 ); +-( SPI ) Peripheral Chip Select Status +/* - -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */ +AT91C_SPI_TD EQU( 0xFFFF << 0 ); +-( SPI ) Transmit Data +AT91C_SPI_TPCS EQU( 0xF << 16 ); +-( SPI ) Peripheral Chip Select Status +/* - -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ +AT91C_SPI_RDRF EQU( 0x1 << 0 ); +-( SPI ) Receive Data Register Full +AT91C_SPI_TDRE EQU( 0x1 << 1 ); +-( SPI ) Transmit Data Register Empty +AT91C_SPI_MODF EQU( 0x1 << 2 ); +-( SPI ) Mode Fault Error +AT91C_SPI_OVRES EQU( 0x1 << 3 ); +-( SPI ) Overrun Error Status +AT91C_SPI_ENDRX EQU( 0x1 << 4 ); +-( SPI ) End of Receiver Transfer +AT91C_SPI_ENDTX EQU( 0x1 << 5 ); +-( SPI ) End of Receiver Transfer +AT91C_SPI_RXBUFF EQU( 0x1 << 6 ); +-( SPI ) RXBUFF Interrupt +AT91C_SPI_TXBUFE EQU( 0x1 << 7 ); +-( SPI ) TXBUFE Interrupt +AT91C_SPI_NSSR EQU( 0x1 << 8 ); +-( SPI ) NSSR Interrupt +AT91C_SPI_TXEMPTY EQU( 0x1 << 9 ); +-( SPI ) TXEMPTY Interrupt +AT91C_SPI_SPIENS EQU( 0x1 << 16 ); +-( SPI ) Enable Status +/* - -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ +/* - -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ +/* - -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */ +/* - -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */ +AT91C_SPI_CPOL EQU( 0x1 << 0 ); +-( SPI ) Clock Polarity +AT91C_SPI_NCPHA EQU( 0x1 << 1 ); +-( SPI ) Clock Phase +AT91C_SPI_CSAAT EQU( 0x1 << 3 ); +-( SPI ) Chip Select Active After Transfer +AT91C_SPI_BITS EQU( 0xF << 4 ); +-( SPI ) Bits Per Transfer +AT91C_SPI_BITS_8 EQU( 0x0 << 4 ); +-( SPI ) 8 Bits Per transfer +AT91C_SPI_BITS_9 EQU( 0x1 << 4 ); +-( SPI ) 9 Bits Per transfer +AT91C_SPI_BITS_10 EQU( 0x2 << 4 ); +-( SPI ) 10 Bits Per transfer +AT91C_SPI_BITS_11 EQU( 0x3 << 4 ); +-( SPI ) 11 Bits Per transfer +AT91C_SPI_BITS_12 EQU( 0x4 << 4 ); +-( SPI ) 12 Bits Per transfer +AT91C_SPI_BITS_13 EQU( 0x5 << 4 ); +-( SPI ) 13 Bits Per transfer +AT91C_SPI_BITS_14 EQU( 0x6 << 4 ); +-( SPI ) 14 Bits Per transfer +AT91C_SPI_BITS_15 EQU( 0x7 << 4 ); +-( SPI ) 15 Bits Per transfer +AT91C_SPI_BITS_16 EQU( 0x8 << 4 ); +-( SPI ) 16 Bits Per transfer +AT91C_SPI_SCBR EQU( 0xFF << 8 ); +-( SPI ) Serial Clock Baud Rate +AT91C_SPI_DLYBS EQU( 0xFF << 16 ); +-( SPI ) Delay Before SPCK +AT91C_SPI_DLYBCT EQU( 0xFF << 24 ); +-( SPI ) Delay Between Consecutive Transfers + +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Usart */ +/* - ***************************************************************************** */ +/* - -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- */ +AT91C_US_STTBRK EQU( 0x1 << 9 ); +-( USART ) Start Break +AT91C_US_STPBRK EQU( 0x1 << 10 ); +-( USART ) Stop Break +AT91C_US_STTTO EQU( 0x1 << 11 ); +-( USART ) Start Time - out +AT91C_US_SENDA EQU( 0x1 << 12 ); +-( USART ) Send Address +AT91C_US_RSTIT EQU( 0x1 << 13 ); +-( USART ) Reset Iterations +AT91C_US_RSTNACK EQU( 0x1 << 14 ); +-( USART ) Reset Non Acknowledge +AT91C_US_RETTO EQU( 0x1 << 15 ); +-( USART ) Rearm Time - out +AT91C_US_DTREN EQU( 0x1 << 16 ); +-( USART ) Data Terminal ready Enable +AT91C_US_DTRDIS EQU( 0x1 << 17 ); +-( USART ) Data Terminal ready Disable +AT91C_US_RTSEN EQU( 0x1 << 18 ); +-( USART ) Request to Send enable +AT91C_US_RTSDIS EQU( 0x1 << 19 ); +-( USART ) Request to Send Disable +/* - -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- */ +AT91C_US_USMODE EQU( 0xF << 0 ); +-( USART ) Usart mode +AT91C_US_USMODE_NORMAL EQU( 0x0 ); +-( USART ) Normal +AT91C_US_USMODE_RS485 EQU( 0x1 ); +-( USART ) RS485 +AT91C_US_USMODE_HWHSH EQU( 0x2 ); +-( USART ) Hardware Handshaking +AT91C_US_USMODE_MODEM EQU( 0x3 ); +-( USART ) Modem +AT91C_US_USMODE_ISO7816_0 EQU( 0x4 ); +-( USART ) ISO7816 protocol: T = 0 + AT91C_US_USMODE_ISO7816_1 EQU( 0x6 ); +-( USART ) ISO7816 protocol: T = 1 + AT91C_US_USMODE_IRDA EQU( 0x8 ); +-( USART ) IrDA +AT91C_US_USMODE_SWHSH EQU( 0xC ); +-( USART ) Software Handshaking +AT91C_US_CLKS EQU( 0x3 << 4 ); +-( USART ) Clock Selection ( Baud Rate generator Input Clock + AT91C_US_CLKS_CLOCK EQU( 0x0 << 4 ); + -( USART ) Clock + AT91C_US_CLKS_FDIV1 EQU( 0x1 << 4 ); + -( USART ) fdiv1 + AT91C_US_CLKS_SLOW EQU( 0x2 << 4 ); + -( USART ) slow_clock( ARM ) + AT91C_US_CLKS_EXT EQU( 0x3 << 4 ); + -( USART ) External( SCK ) + AT91C_US_CHRL EQU( 0x3 << 6 ); + -( USART ) Clock Selection ( Baud Rate generator Input Clock + AT91C_US_CHRL_5_BITS EQU( 0x0 << 6 ); + -( USART ) Character Length : 5 bits + AT91C_US_CHRL_6_BITS EQU( 0x1 << 6 ); + -( USART ) Character Length : 6 bits + AT91C_US_CHRL_7_BITS EQU( 0x2 << 6 ); + -( USART ) Character Length : 7 bits + AT91C_US_CHRL_8_BITS EQU( 0x3 << 6 ); + -( USART ) Character Length : 8 bits + AT91C_US_SYNC EQU( 0x1 << 8 ); + -( USART ) Synchronous Mode Select + AT91C_US_NBSTOP EQU( 0x3 << 12 ); + -( USART ) Number of Stop bits + AT91C_US_NBSTOP_1_BIT EQU( 0x0 << 12 ); + -( USART ) 1 stop bit + AT91C_US_NBSTOP_15_BIT EQU( 0x1 << 12 ); + -( USART ) Asynchronous( SYNC = 0 ) 2 stop bits Synchronous( SYNC = 1 ) 2 stop bits + AT91C_US_NBSTOP_2_BIT EQU( 0x2 << 12 ); + -( USART ) 2 stop bits + AT91C_US_MSBF EQU( 0x1 << 16 ); + -( USART ) Bit Order + AT91C_US_MODE9 EQU( 0x1 << 17 ); + -( USART ) 9 - bit Character length + AT91C_US_CKLO EQU( 0x1 << 18 ); + -( USART ) Clock Output Select + AT91C_US_OVER EQU( 0x1 << 19 ); + -( USART ) Over Sampling Mode + AT91C_US_INACK EQU( 0x1 << 20 ); + -( USART ) Inhibit Non Acknowledge + AT91C_US_DSNACK EQU( 0x1 << 21 ); + -( USART ) Disable Successive NACK + AT91C_US_MAX_ITER EQU( 0x1 << 24 ); + -( USART ) Number of Repetitions + AT91C_US_FILTER EQU( 0x1 << 28 ); + -( USART ) Receive Line Filter +/* - -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ + AT91C_US_RXBRK EQU( 0x1 << 2 ); + -( USART ) Break Received / End of Break + AT91C_US_TIMEOUT EQU( 0x1 << 8 ); + -( USART ) Receiver Time - out + AT91C_US_ITERATION EQU( 0x1 << 10 ); + -( USART ) Max number of Repetitions Reached + AT91C_US_NACK EQU( 0x1 << 13 ); + -( USART ) Non Acknowledge + AT91C_US_RIIC EQU( 0x1 << 16 ); + -( USART ) Ring INdicator Input Change Flag + AT91C_US_DSRIC EQU( 0x1 << 17 ); + -( USART ) Data Set Ready Input Change Flag + AT91C_US_DCDIC EQU( 0x1 << 18 ); + -( USART ) Data Carrier Flag + AT91C_US_CTSIC EQU( 0x1 << 19 ); + -( USART ) Clear To Send Input Change Flag +/* - -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- */ +/* - -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- */ +/* - -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- */ + AT91C_US_RI EQU( 0x1 << 20 ); + -( USART ) Image of RI Input + AT91C_US_DSR EQU( 0x1 << 21 ); + -( USART ) Image of DSR Input + AT91C_US_DCD EQU( 0x1 << 22 ); + -( USART ) Image of DCD Input + AT91C_US_CTS EQU( 0x1 << 23 ); + -( USART ) Image of CTS Input + +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface */ +/* - ***************************************************************************** */ +/* - -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- */ + AT91C_SSC_RXEN EQU( 0x1 << 0 ); + -( SSC ) Receive Enable + AT91C_SSC_RXDIS EQU( 0x1 << 1 ); + -( SSC ) Receive Disable + AT91C_SSC_TXEN EQU( 0x1 << 8 ); + -( SSC ) Transmit Enable + AT91C_SSC_TXDIS EQU( 0x1 << 9 ); + -( SSC ) Transmit Disable + AT91C_SSC_SWRST EQU( 0x1 << 15 ); + -( SSC ) Software Reset +/* - -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- */ + AT91C_SSC_CKS EQU( 0x3 << 0 ); + -( SSC ) Receive / Transmit Clock Selection + AT91C_SSC_CKS_DIV EQU( 0x0 ); + -( SSC ) Divided Clock + AT91C_SSC_CKS_TK EQU( 0x1 ); + -( SSC ) TK Clock signal + AT91C_SSC_CKS_RK EQU( 0x2 ); + -( SSC ) RK pin + AT91C_SSC_CKO EQU( 0x7 << 2 ); + -( SSC ) Receive / Transmit Clock Output Mode Selection + AT91C_SSC_CKO_NONE EQU( 0x0 << 2 ); + -( SSC ) Receive / Transmit Clock Output Mode:None RK pin: Input - only + AT91C_SSC_CKO_CONTINUOUS EQU( 0x1 << 2 ); + -( SSC ) Continuous Receive / Transmit Clock RK pin:Output + AT91C_SSC_CKO_DATA_TX EQU( 0x2 << 2 ); + -( SSC ) Receive / Transmit Clock only during data transfers RK pin:Output + AT91C_SSC_CKI EQU( 0x1 << 5 ); + -( SSC ) Receive / Transmit Clock Inversion + AT91C_SSC_START EQU( 0xF << 8 ); + -( SSC ) Receive / Transmit Start Selection + AT91C_SSC_START_CONTINUOUS EQU( 0x0 << 8 ); + -( SSC ) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. + AT91C_SSC_START_TX EQU( 0x1 << 8 ); + -( SSC ) Transmit / Receive start + AT91C_SSC_START_LOW_RF EQU( 0x2 << 8 ); + -( SSC ) Detection of a low level on RF input + AT91C_SSC_START_HIGH_RF EQU( 0x3 << 8 ); + -( SSC ) Detection of a high level on RF input + AT91C_SSC_START_FALL_RF EQU( 0x4 << 8 ); + -( SSC ) Detection of a falling edge on RF input + AT91C_SSC_START_RISE_RF EQU( 0x5 << 8 ); + -( SSC ) Detection of a rising edge on RF input + AT91C_SSC_START_LEVEL_RF EQU( 0x6 << 8 ); + -( SSC ) Detection of any level change on RF input + AT91C_SSC_START_EDGE_RF EQU( 0x7 << 8 ); + -( SSC ) Detection of any edge on RF input + AT91C_SSC_START_0 EQU( 0x8 << 8 ); + -( SSC ) Compare 0 + AT91C_SSC_STTDLY EQU( 0xFF << 16 ); + -( SSC ) Receive / Transmit Start Delay + AT91C_SSC_PERIOD EQU( 0xFF << 24 ); + -( SSC ) Receive / Transmit Period Divider Selection +/* - -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- */ + AT91C_SSC_DATLEN EQU( 0x1F << 0 ); + -( SSC ) Data Length + AT91C_SSC_LOOP EQU( 0x1 << 5 ); + -( SSC ) Loop Mode + AT91C_SSC_MSBF EQU( 0x1 << 7 ); + -( SSC ) Most Significant Bit First + AT91C_SSC_DATNB EQU( 0xF << 8 ); + -( SSC ) Data Number per Frame + AT91C_SSC_FSLEN EQU( 0xF << 16 ); + -( SSC ) Receive / Transmit Frame Sync length + AT91C_SSC_FSOS EQU( 0x7 << 20 ); + -( SSC ) Receive / Transmit Frame Sync Output Selection + AT91C_SSC_FSOS_NONE EQU( 0x0 << 20 ); + -( SSC ) Selected Receive / Transmit Frame Sync Signal:None RK pin Input - only + AT91C_SSC_FSOS_NEGATIVE EQU( 0x1 << 20 ); + -( SSC ) Selected Receive / Transmit Frame Sync Signal:Negative Pulse + AT91C_SSC_FSOS_POSITIVE EQU( 0x2 << 20 ); + -( SSC ) Selected Receive / Transmit Frame Sync Signal:Positive Pulse + AT91C_SSC_FSOS_LOW EQU( 0x3 << 20 ); + -( SSC ) Selected Receive / Transmit Frame Sync Signal:Driver Low during data transfer + AT91C_SSC_FSOS_HIGH EQU( 0x4 << 20 ); + -( SSC ) Selected Receive / Transmit Frame Sync Signal:Driver High during data transfer + AT91C_SSC_FSOS_TOGGLE EQU( 0x5 << 20 ); + -( SSC ) Selected Receive / Transmit Frame Sync Signal:Toggling at each start of data transfer + AT91C_SSC_FSEDGE EQU( 0x1 << 24 ); + -( SSC ) Frame Sync Edge Detection +/* - -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- */ +/* - -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- */ + AT91C_SSC_DATDEF EQU( 0x1 << 5 ); + -( SSC ) Data Default Value + AT91C_SSC_FSDEN EQU( 0x1 << 23 ); + -( SSC ) Frame Sync Data Enable +/* - -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- */ + AT91C_SSC_TXRDY EQU( 0x1 << 0 ); + -( SSC ) Transmit Ready + AT91C_SSC_TXEMPTY EQU( 0x1 << 1 ); + -( SSC ) Transmit Empty + AT91C_SSC_ENDTX EQU( 0x1 << 2 ); + -( SSC ) End Of Transmission + AT91C_SSC_TXBUFE EQU( 0x1 << 3 ); + -( SSC ) Transmit Buffer Empty + AT91C_SSC_RXRDY EQU( 0x1 << 4 ); + -( SSC ) Receive Ready + AT91C_SSC_OVRUN EQU( 0x1 << 5 ); + -( SSC ) Receive Overrun + AT91C_SSC_ENDRX EQU( 0x1 << 6 ); + -( SSC ) End of Reception + AT91C_SSC_RXBUFF EQU( 0x1 << 7 ); + -( SSC ) Receive Buffer Full + AT91C_SSC_TXSYN EQU( 0x1 << 10 ); + -( SSC ) Transmit Sync + AT91C_SSC_RXSYN EQU( 0x1 << 11 ); + -( SSC ) Receive Sync + AT91C_SSC_TXENA EQU( 0x1 << 16 ); + -( SSC ) Transmit Enable + AT91C_SSC_RXENA EQU( 0x1 << 17 ); + -( SSC ) Receive Enable +/* - -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- */ +/* - -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- */ +/* - -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- */ + +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Two-wire Interface */ +/* - ***************************************************************************** */ +/* - -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */ + AT91C_TWI_START EQU( 0x1 << 0 ); + -( TWI ) Send a START Condition + AT91C_TWI_STOP EQU( 0x1 << 1 ); + -( TWI ) Send a STOP Condition + AT91C_TWI_MSEN EQU( 0x1 << 2 ); + -( TWI ) TWI Master Transfer Enabled + AT91C_TWI_MSDIS EQU( 0x1 << 3 ); + -( TWI ) TWI Master Transfer Disabled + AT91C_TWI_SWRST EQU( 0x1 << 7 ); + -( TWI ) Software Reset +/* - -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */ + AT91C_TWI_IADRSZ EQU( 0x3 << 8 ); + -( TWI ) Internal Device Address Size + AT91C_TWI_IADRSZ_NO EQU( 0x0 << 8 ); + -( TWI ) No internal device address + AT91C_TWI_IADRSZ_1_BYTE EQU( 0x1 << 8 ); + -( TWI ) One - byte internal device address + AT91C_TWI_IADRSZ_2_BYTE EQU( 0x2 << 8 ); + -( TWI ) Two - byte internal device address + AT91C_TWI_IADRSZ_3_BYTE EQU( 0x3 << 8 ); + -( TWI ) Three - byte internal device address + AT91C_TWI_MREAD EQU( 0x1 << 12 ); + -( TWI ) Master Read Direction + AT91C_TWI_DADR EQU( 0x7F << 16 ); + -( TWI ) Device Address +/* - -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */ + AT91C_TWI_CLDIV EQU( 0xFF << 0 ); + -( TWI ) Clock Low Divider + AT91C_TWI_CHDIV EQU( 0xFF << 8 ); + -( TWI ) Clock High Divider + AT91C_TWI_CKDIV EQU( 0x7 << 16 ); + -( TWI ) Clock Divider +/* - -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */ + AT91C_TWI_TXCOMP EQU( 0x1 << 0 ); + -( TWI ) Transmission Completed + AT91C_TWI_RXRDY EQU( 0x1 << 1 ); + -( TWI ) Receive holding register ReaDY + AT91C_TWI_TXRDY EQU( 0x1 << 2 ); + -( TWI ) Transmit holding register ReaDY + AT91C_TWI_OVRE EQU( 0x1 << 6 ); + -( TWI ) Overrun Error + AT91C_TWI_UNRE EQU( 0x1 << 7 ); + -( TWI ) Underrun Error + AT91C_TWI_NACK EQU( 0x1 << 8 ); + -( TWI ) Not Acknowledged +/* - -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */ +/* - -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- */ +/* - -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */ + +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR PWMC Channel Interface */ +/* - ***************************************************************************** */ +/* - -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- */ + AT91C_PWMC_CPRE EQU( 0xF << 0 ); + -( PWMC_CH ) Channel Pre - scaler:PWMC_CLKx + AT91C_PWMC_CPRE_MCK EQU( 0x0 ); + -( PWMC_CH ) + AT91C_PWMC_CPRE_MCKA EQU( 0xB ); + -( PWMC_CH ) + AT91C_PWMC_CPRE_MCKB EQU( 0xC ); + -( PWMC_CH ) + AT91C_PWMC_CALG EQU( 0x1 << 8 ); + -( PWMC_CH ) Channel Alignment + AT91C_PWMC_CPOL EQU( 0x1 << 9 ); + -( PWMC_CH ) Channel Polarity + AT91C_PWMC_CPD EQU( 0x1 << 10 ); + -( PWMC_CH ) Channel Update Period +/* - -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- */ + AT91C_PWMC_CDTY EQU( 0x0 << 0 ); + -( PWMC_CH ) Channel Duty Cycle +/* - -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- */ + AT91C_PWMC_CPRD EQU( 0x0 << 0 ); + -( PWMC_CH ) Channel Period +/* - -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- */ + AT91C_PWMC_CCNT EQU( 0x0 << 0 ); + -( PWMC_CH ) Channel Counter +/* - -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- */ + AT91C_PWMC_CUPD EQU( 0x0 << 0 ); + -( PWMC_CH ) Channel Update + +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface */ +/* - ***************************************************************************** */ +/* - -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- */ + AT91C_PWMC_DIVA EQU( 0xFF << 0 ); + -( PWMC ) CLKA divide factor. + AT91C_PWMC_PREA EQU( 0xF << 8 ); + -( PWMC ) Divider Input Clock Prescaler A + AT91C_PWMC_PREA_MCK EQU( 0x0 << 8 ); + -( PWMC ) + AT91C_PWMC_DIVB EQU( 0xFF << 16 ); + -( PWMC ) CLKB divide factor. + AT91C_PWMC_PREB EQU( 0xF << 24 ); + -( PWMC ) Divider Input Clock Prescaler B + AT91C_PWMC_PREB_MCK EQU( 0x0 << 24 ); + -( PWMC ) +/* - -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- */ + AT91C_PWMC_CHID0 EQU( 0x1 << 0 ); + -( PWMC ) Channel ID 0 + AT91C_PWMC_CHID1 EQU( 0x1 << 1 ); + -( PWMC ) Channel ID 1 + AT91C_PWMC_CHID2 EQU( 0x1 << 2 ); + -( PWMC ) Channel ID 2 + AT91C_PWMC_CHID3 EQU( 0x1 << 3 ); + -( PWMC ) Channel ID 3 +/* - -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- */ +/* - -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- */ +/* - -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- */ +/* - -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- */ +/* - -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- */ +/* - -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- */ + +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR USB Device Interface */ +/* - ***************************************************************************** */ +/* - -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- */ + AT91C_UDP_FRM_NUM EQU( 0x7FF << 0 ); + -( UDP ) Frame Number as Defined in the Packet Field Formats + AT91C_UDP_FRM_ERR EQU( 0x1 << 16 ); + -( UDP ) Frame Error + AT91C_UDP_FRM_OK EQU( 0x1 << 17 ); + -( UDP ) Frame OK +/* - -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- */ + AT91C_UDP_FADDEN EQU( 0x1 << 0 ); + -( UDP ) Function Address Enable + AT91C_UDP_CONFG EQU( 0x1 << 1 ); + -( UDP ) Configured + AT91C_UDP_ESR EQU( 0x1 << 2 ); + -( UDP ) Enable Send Resume + AT91C_UDP_RSMINPR EQU( 0x1 << 3 ); + -( UDP ) A Resume Has Been Sent to the Host + AT91C_UDP_RMWUPE EQU( 0x1 << 4 ); + -( UDP ) Remote Wake Up Enable +/* - -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- */ + AT91C_UDP_FADD EQU( 0xFF << 0 ); + -( UDP ) Function Address Value + AT91C_UDP_FEN EQU( 0x1 << 8 ); + -( UDP ) Function Enable +/* - -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- */ + AT91C_UDP_EPINT0 EQU( 0x1 << 0 ); + -( UDP ) Endpoint 0 Interrupt + AT91C_UDP_EPINT1 EQU( 0x1 << 1 ); + -( UDP ) Endpoint 0 Interrupt + AT91C_UDP_EPINT2 EQU( 0x1 << 2 ); + -( UDP ) Endpoint 2 Interrupt + AT91C_UDP_EPINT3 EQU( 0x1 << 3 ); + -( UDP ) Endpoint 3 Interrupt + AT91C_UDP_EPINT4 EQU( 0x1 << 4 ); + -( UDP ) Endpoint 4 Interrupt + AT91C_UDP_EPINT5 EQU( 0x1 << 5 ); + -( UDP ) Endpoint 5 Interrupt + AT91C_UDP_RXSUSP EQU( 0x1 << 8 ); + -( UDP ) USB Suspend Interrupt + AT91C_UDP_RXRSM EQU( 0x1 << 9 ); + -( UDP ) USB Resume Interrupt + AT91C_UDP_EXTRSM EQU( 0x1 << 10 ); + -( UDP ) USB External Resume Interrupt + AT91C_UDP_SOFINT EQU( 0x1 << 11 ); + -( UDP ) USB Start Of frame Interrupt + AT91C_UDP_WAKEUP EQU( 0x1 << 13 ); + -( UDP ) USB Resume Interrupt +/* - -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- */ +/* - -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- */ +/* - -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- */ + AT91C_UDP_ENDBUSRES EQU( 0x1 << 12 ); + -( UDP ) USB End Of Bus Reset Interrupt +/* - -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- */ +/* - -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- */ + AT91C_UDP_EP0 EQU( 0x1 << 0 ); + -( UDP ) Reset Endpoint 0 + AT91C_UDP_EP1 EQU( 0x1 << 1 ); + -( UDP ) Reset Endpoint 1 + AT91C_UDP_EP2 EQU( 0x1 << 2 ); + -( UDP ) Reset Endpoint 2 + AT91C_UDP_EP3 EQU( 0x1 << 3 ); + -( UDP ) Reset Endpoint 3 + AT91C_UDP_EP4 EQU( 0x1 << 4 ); + -( UDP ) Reset Endpoint 4 + AT91C_UDP_EP5 EQU( 0x1 << 5 ); + -( UDP ) Reset Endpoint 5 +/* - -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- */ + AT91C_UDP_TXCOMP EQU( 0x1 << 0 ); + -( UDP ) Generates an IN packet with data previously written in the DPR + AT91C_UDP_RX_DATA_BK0 EQU( 0x1 << 1 ); + -( UDP ) Receive Data Bank 0 + AT91C_UDP_RXSETUP EQU( 0x1 << 2 ); + -( UDP ) Sends STALL to the Host( Control endpoints ) + AT91C_UDP_ISOERROR EQU( 0x1 << 3 ); + -( UDP ) Isochronous error( Isochronous endpoints ) + AT91C_UDP_TXPKTRDY EQU( 0x1 << 4 ); + -( UDP ) Transmit Packet Ready + AT91C_UDP_FORCESTALL EQU( 0x1 << 5 ); + -( UDP ) Force Stall( used by Control, Bulk and Isochronous endpoints ). + AT91C_UDP_RX_DATA_BK1 EQU( 0x1 << 6 ); + -( UDP ) Receive Data Bank 1 ( only used by endpoints with ping - pong attributes ). + AT91C_UDP_DIR EQU( 0x1 << 7 ); + -( UDP ) Transfer Direction + AT91C_UDP_EPTYPE EQU( 0x7 << 8 ); + -( UDP ) Endpoint type + AT91C_UDP_EPTYPE_CTRL EQU( 0x0 << 8 ); + -( UDP ) Control + AT91C_UDP_EPTYPE_ISO_OUT EQU( 0x1 << 8 ); + -( UDP ) Isochronous OUT + AT91C_UDP_EPTYPE_BULK_OUT EQU( 0x2 << 8 ); + -( UDP ) Bulk OUT + AT91C_UDP_EPTYPE_INT_OUT EQU( 0x3 << 8 ); + -( UDP ) Interrupt OUT + AT91C_UDP_EPTYPE_ISO_IN EQU( 0x5 << 8 ); + -( UDP ) Isochronous IN + AT91C_UDP_EPTYPE_BULK_IN EQU( 0x6 << 8 ); + -( UDP ) Bulk IN + AT91C_UDP_EPTYPE_INT_IN EQU( 0x7 << 8 ); + -( UDP ) Interrupt IN + AT91C_UDP_DTGLE EQU( 0x1 << 11 ); + -( UDP ) Data Toggle + AT91C_UDP_EPEDS EQU( 0x1 << 15 ); + -( UDP ) Endpoint Enable Disable + AT91C_UDP_RXBYTECNT EQU( 0x7FF << 16 ); + -( UDP ) Number Of Bytes Available in the FIFO +/* - -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- */ + AT91C_UDP_TXVDIS EQU( 0x1 << 8 ); + -( UDP ) + AT91C_UDP_PUON EQU( 0x1 << 9 ); + -( UDP ) Pull - up ON + +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */ +/* - ***************************************************************************** */ +/* - -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- */ + AT91C_TC_CLKEN EQU( 0x1 << 0 ); + -( TC ) Counter Clock Enable Command + AT91C_TC_CLKDIS EQU( 0x1 << 1 ); + -( TC ) Counter Clock Disable Command + AT91C_TC_SWTRG EQU( 0x1 << 2 ); + -( TC ) Software Trigger Command +/* - -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- */ + AT91C_TC_CLKS EQU( 0x7 << 0 ); + -( TC ) Clock Selection + AT91C_TC_CLKS_TIMER_DIV1_CLOCK EQU( 0x0 ); + -( TC ) Clock selected:TIMER_DIV1_CLOCK + AT91C_TC_CLKS_TIMER_DIV2_CLOCK EQU( 0x1 ); + -( TC ) Clock selected:TIMER_DIV2_CLOCK + AT91C_TC_CLKS_TIMER_DIV3_CLOCK EQU( 0x2 ); + -( TC ) Clock selected:TIMER_DIV3_CLOCK + AT91C_TC_CLKS_TIMER_DIV4_CLOCK EQU( 0x3 ); + -( TC ) Clock selected:TIMER_DIV4_CLOCK + AT91C_TC_CLKS_TIMER_DIV5_CLOCK EQU( 0x4 ); + -( TC ) Clock selected:TIMER_DIV5_CLOCK + AT91C_TC_CLKS_XC0 EQU( 0x5 ); + -( TC ) Clock selected:XC0 + AT91C_TC_CLKS_XC1 EQU( 0x6 ); + -( TC ) Clock selected:XC1 + AT91C_TC_CLKS_XC2 EQU( 0x7 ); + -( TC ) Clock selected:XC2 + AT91C_TC_CLKI EQU( 0x1 << 3 ); + -( TC ) Clock Invert + AT91C_TC_BURST EQU( 0x3 << 4 ); + -( TC ) Burst Signal Selection + AT91C_TC_BURST_NONE EQU( 0x0 << 4 ); + -( TC ) The clock is not gated by an external signal + AT91C_TC_BURST_XC0 EQU( 0x1 << 4 ); + -( TC ) XC0 is ANDed with the selected clock + AT91C_TC_BURST_XC1 EQU( 0x2 << 4 ); + -( TC ) XC1 is ANDed with the selected clock + AT91C_TC_BURST_XC2 EQU( 0x3 << 4 ); + -( TC ) XC2 is ANDed with the selected clock + AT91C_TC_CPCSTOP EQU( 0x1 << 6 ); + -( TC ) Counter Clock Stopped with RC Compare + AT91C_TC_LDBSTOP EQU( 0x1 << 6 ); + -( TC ) Counter Clock Stopped with RB Loading + AT91C_TC_CPCDIS EQU( 0x1 << 7 ); + -( TC ) Counter Clock Disable with RC Compare + AT91C_TC_LDBDIS EQU( 0x1 << 7 ); + -( TC ) Counter Clock Disabled with RB Loading + AT91C_TC_ETRGEDG EQU( 0x3 << 8 ); + -( TC ) External Trigger Edge Selection + AT91C_TC_ETRGEDG_NONE EQU( 0x0 << 8 ); + -( TC ) Edge:None + AT91C_TC_ETRGEDG_RISING EQU( 0x1 << 8 ); + -( TC ) Edge:rising edge + AT91C_TC_ETRGEDG_FALLING EQU( 0x2 << 8 ); + -( TC ) Edge:falling edge + AT91C_TC_ETRGEDG_BOTH EQU( 0x3 << 8 ); + -( TC ) Edge:each edge + AT91C_TC_EEVTEDG EQU( 0x3 << 8 ); + -( TC ) External Event Edge Selection + AT91C_TC_EEVTEDG_NONE EQU( 0x0 << 8 ); + -( TC ) Edge:None + AT91C_TC_EEVTEDG_RISING EQU( 0x1 << 8 ); + -( TC ) Edge:rising edge + AT91C_TC_EEVTEDG_FALLING EQU( 0x2 << 8 ); + -( TC ) Edge:falling edge + AT91C_TC_EEVTEDG_BOTH EQU( 0x3 << 8 ); + -( TC ) Edge:each edge + AT91C_TC_EEVT EQU( 0x3 << 10 ); + -( TC ) External Event Selection + AT91C_TC_EEVT_TIOB EQU( 0x0 << 10 ); + -( TC ) Signal selected as external event:TIOB TIOB direction: input + AT91C_TC_EEVT_XC0 EQU( 0x1 << 10 ); + -( TC ) Signal selected as external event:XC0 TIOB direction: output + AT91C_TC_EEVT_XC1 EQU( 0x2 << 10 ); + -( TC ) Signal selected as external event:XC1 TIOB direction: output + AT91C_TC_EEVT_XC2 EQU( 0x3 << 10 ); + -( TC ) Signal selected as external event:XC2 TIOB direction: output + AT91C_TC_ABETRG EQU( 0x1 << 10 ); + -( TC ) TIOA or TIOB External Trigger Selection + AT91C_TC_ENETRG EQU( 0x1 << 12 ); + -( TC ) External Event Trigger enable + AT91C_TC_WAVESEL EQU( 0x3 << 13 ); + -( TC ) Waveform Selection + AT91C_TC_WAVESEL_UP EQU( 0x0 << 13 ); + -( TC ) UP mode without atomatic trigger on RC Compare + AT91C_TC_WAVESEL_UPDOWN EQU( 0x1 << 13 ); + -( TC ) UPDOWN mode without automatic trigger on RC Compare + AT91C_TC_WAVESEL_UP_AUTO EQU( 0x2 << 13 ); + -( TC ) UP mode with automatic trigger on RC Compare + AT91C_TC_WAVESEL_UPDOWN_AUTO EQU( 0x3 << 13 ); + -( TC ) UPDOWN mode with automatic trigger on RC Compare + AT91C_TC_CPCTRG EQU( 0x1 << 14 ); + -( TC ) RC Compare Trigger Enable + AT91C_TC_WAVE EQU( 0x1 << 15 ); + -( TC ) + AT91C_TC_ACPA EQU( 0x3 << 16 ); + -( TC ) RA Compare Effect on TIOA + AT91C_TC_ACPA_NONE EQU( 0x0 << 16 ); + -( TC ) Effect:none + AT91C_TC_ACPA_SET EQU( 0x1 << 16 ); + -( TC ) Effect:set + AT91C_TC_ACPA_CLEAR EQU( 0x2 << 16 ); + -( TC ) Effect:clear + AT91C_TC_ACPA_TOGGLE EQU( 0x3 << 16 ); + -( TC ) Effect:toggle + AT91C_TC_LDRA EQU( 0x3 << 16 ); + -( TC ) RA Loading Selection + AT91C_TC_LDRA_NONE EQU( 0x0 << 16 ); + -( TC ) Edge:None + AT91C_TC_LDRA_RISING EQU( 0x1 << 16 ); + -( TC ) Edge:rising edge of TIOA + AT91C_TC_LDRA_FALLING EQU( 0x2 << 16 ); + -( TC ) Edge:falling edge of TIOA + AT91C_TC_LDRA_BOTH EQU( 0x3 << 16 ); + -( TC ) Edge:each edge of TIOA + AT91C_TC_ACPC EQU( 0x3 << 18 ); + -( TC ) RC Compare Effect on TIOA + AT91C_TC_ACPC_NONE EQU( 0x0 << 18 ); + -( TC ) Effect:none + AT91C_TC_ACPC_SET EQU( 0x1 << 18 ); + -( TC ) Effect:set + AT91C_TC_ACPC_CLEAR EQU( 0x2 << 18 ); + -( TC ) Effect:clear + AT91C_TC_ACPC_TOGGLE EQU( 0x3 << 18 ); + -( TC ) Effect:toggle + AT91C_TC_LDRB EQU( 0x3 << 18 ); + -( TC ) RB Loading Selection + AT91C_TC_LDRB_NONE EQU( 0x0 << 18 ); + -( TC ) Edge:None + AT91C_TC_LDRB_RISING EQU( 0x1 << 18 ); + -( TC ) Edge:rising edge of TIOA + AT91C_TC_LDRB_FALLING EQU( 0x2 << 18 ); + -( TC ) Edge:falling edge of TIOA + AT91C_TC_LDRB_BOTH EQU( 0x3 << 18 ); + -( TC ) Edge:each edge of TIOA + AT91C_TC_AEEVT EQU( 0x3 << 20 ); + -( TC ) External Event Effect on TIOA + AT91C_TC_AEEVT_NONE EQU( 0x0 << 20 ); + -( TC ) Effect:none + AT91C_TC_AEEVT_SET EQU( 0x1 << 20 ); + -( TC ) Effect:set + AT91C_TC_AEEVT_CLEAR EQU( 0x2 << 20 ); + -( TC ) Effect:clear + AT91C_TC_AEEVT_TOGGLE EQU( 0x3 << 20 ); + -( TC ) Effect:toggle + AT91C_TC_ASWTRG EQU( 0x3 << 22 ); + -( TC ) Software Trigger Effect on TIOA + AT91C_TC_ASWTRG_NONE EQU( 0x0 << 22 ); + -( TC ) Effect:none + AT91C_TC_ASWTRG_SET EQU( 0x1 << 22 ); + -( TC ) Effect:set + AT91C_TC_ASWTRG_CLEAR EQU( 0x2 << 22 ); + -( TC ) Effect:clear + AT91C_TC_ASWTRG_TOGGLE EQU( 0x3 << 22 ); + -( TC ) Effect:toggle + AT91C_TC_BCPB EQU( 0x3 << 24 ); + -( TC ) RB Compare Effect on TIOB + AT91C_TC_BCPB_NONE EQU( 0x0 << 24 ); + -( TC ) Effect:none + AT91C_TC_BCPB_SET EQU( 0x1 << 24 ); + -( TC ) Effect:set + AT91C_TC_BCPB_CLEAR EQU( 0x2 << 24 ); + -( TC ) Effect:clear + AT91C_TC_BCPB_TOGGLE EQU( 0x3 << 24 ); + -( TC ) Effect:toggle + AT91C_TC_BCPC EQU( 0x3 << 26 ); + -( TC ) RC Compare Effect on TIOB + AT91C_TC_BCPC_NONE EQU( 0x0 << 26 ); + -( TC ) Effect:none + AT91C_TC_BCPC_SET EQU( 0x1 << 26 ); + -( TC ) Effect:set + AT91C_TC_BCPC_CLEAR EQU( 0x2 << 26 ); + -( TC ) Effect:clear + AT91C_TC_BCPC_TOGGLE EQU( 0x3 << 26 ); + -( TC ) Effect:toggle + AT91C_TC_BEEVT EQU( 0x3 << 28 ); + -( TC ) External Event Effect on TIOB + AT91C_TC_BEEVT_NONE EQU( 0x0 << 28 ); + -( TC ) Effect:none + AT91C_TC_BEEVT_SET EQU( 0x1 << 28 ); + -( TC ) Effect:set + AT91C_TC_BEEVT_CLEAR EQU( 0x2 << 28 ); + -( TC ) Effect:clear + AT91C_TC_BEEVT_TOGGLE EQU( 0x3 << 28 ); + -( TC ) Effect:toggle + AT91C_TC_BSWTRG EQU( 0x3 << 30 ); + -( TC ) Software Trigger Effect on TIOB + AT91C_TC_BSWTRG_NONE EQU( 0x0 << 30 ); + -( TC ) Effect:none + AT91C_TC_BSWTRG_SET EQU( 0x1 << 30 ); + -( TC ) Effect:set + AT91C_TC_BSWTRG_CLEAR EQU( 0x2 << 30 ); + -( TC ) Effect:clear + AT91C_TC_BSWTRG_TOGGLE EQU( 0x3 << 30 ); + -( TC ) Effect:toggle +/* - -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- */ + AT91C_TC_COVFS EQU( 0x1 << 0 ); + -( TC ) Counter Overflow + AT91C_TC_LOVRS EQU( 0x1 << 1 ); + -( TC ) Load Overrun + AT91C_TC_CPAS EQU( 0x1 << 2 ); + -( TC ) RA Compare + AT91C_TC_CPBS EQU( 0x1 << 3 ); + -( TC ) RB Compare + AT91C_TC_CPCS EQU( 0x1 << 4 ); + -( TC ) RC Compare + AT91C_TC_LDRAS EQU( 0x1 << 5 ); + -( TC ) RA Loading + AT91C_TC_LDRBS EQU( 0x1 << 6 ); + -( TC ) RB Loading + AT91C_TC_ETRGS EQU( 0x1 << 7 ); + -( TC ) External Trigger + AT91C_TC_CLKSTA EQU( 0x1 << 16 ); + -( TC ) Clock Enabling + AT91C_TC_MTIOA EQU( 0x1 << 17 ); + -( TC ) TIOA Mirror + AT91C_TC_MTIOB EQU( 0x1 << 18 ); + -( TC ) TIOA Mirror +/* - -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- */ +/* - -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- */ +/* - -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- */ + +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Timer Counter Interface */ +/* - ***************************************************************************** */ +/* - -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- */ + AT91C_TCB_SYNC EQU( 0x1 << 0 ); + -( TCB ) Synchro Command +/* - -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- */ + AT91C_TCB_TC0XC0S EQU( 0x3 << 0 ); + -( TCB ) External Clock Signal 0 Selection + AT91C_TCB_TC0XC0S_TCLK0 EQU( 0x0 ); + -( TCB ) TCLK0 connected to XC0 + AT91C_TCB_TC0XC0S_NONE EQU( 0x1 ); + -( TCB ) None signal connected to XC0 + AT91C_TCB_TC0XC0S_TIOA1 EQU( 0x2 ); + -( TCB ) TIOA1 connected to XC0 + AT91C_TCB_TC0XC0S_TIOA2 EQU( 0x3 ); + -( TCB ) TIOA2 connected to XC0 + AT91C_TCB_TC1XC1S EQU( 0x3 << 2 ); + -( TCB ) External Clock Signal 1 Selection + AT91C_TCB_TC1XC1S_TCLK1 EQU( 0x0 << 2 ); + -( TCB ) TCLK1 connected to XC1 + AT91C_TCB_TC1XC1S_NONE EQU( 0x1 << 2 ); + -( TCB ) None signal connected to XC1 + AT91C_TCB_TC1XC1S_TIOA0 EQU( 0x2 << 2 ); + -( TCB ) TIOA0 connected to XC1 + AT91C_TCB_TC1XC1S_TIOA2 EQU( 0x3 << 2 ); + -( TCB ) TIOA2 connected to XC1 + AT91C_TCB_TC2XC2S EQU( 0x3 << 4 ); + -( TCB ) External Clock Signal 2 Selection + AT91C_TCB_TC2XC2S_TCLK2 EQU( 0x0 << 4 ); + -( TCB ) TCLK2 connected to XC2 + AT91C_TCB_TC2XC2S_NONE EQU( 0x1 << 4 ); + -( TCB ) None signal connected to XC2 + AT91C_TCB_TC2XC2S_TIOA0 EQU( 0x2 << 4 ); + -( TCB ) TIOA0 connected to XC2 + AT91C_TCB_TC2XC2S_TIOA1 EQU( 0x3 << 4 ); + -( TCB ) TIOA2 connected to XC2 + +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface */ +/* - ***************************************************************************** */ +/* - -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- */ + AT91C_CAN_MTIMEMARK EQU( 0xFFFF << 0 ); + -( CAN_MB ) Mailbox Timemark + AT91C_CAN_PRIOR EQU( 0xF << 16 ); + -( CAN_MB ) Mailbox Priority + AT91C_CAN_MOT EQU( 0x7 << 24 ); + -( CAN_MB ) Mailbox Object Type + AT91C_CAN_MOT_DIS EQU( 0x0 << 24 ); + -( CAN_MB ) + AT91C_CAN_MOT_RX EQU( 0x1 << 24 ); + -( CAN_MB ) + AT91C_CAN_MOT_RXOVERWRITE EQU( 0x2 << 24 ); + -( CAN_MB ) + AT91C_CAN_MOT_TX EQU( 0x3 << 24 ); + -( CAN_MB ) + AT91C_CAN_MOT_CONSUMER EQU( 0x4 << 24 ); + -( CAN_MB ) + AT91C_CAN_MOT_PRODUCER EQU( 0x5 << 24 ); + -( CAN_MB ) +/* - -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- */ + AT91C_CAN_MIDvB EQU( 0x3FFFF << 0 ); + -( CAN_MB ) Complementary bits + + for identifier in extended mode + AT91C_CAN_MIDvA EQU( 0x7FF << 18 ); + -( CAN_MB ) Identifier + + for standard frame mode + AT91C_CAN_MIDE EQU( 0x1 << 29 ); + -( CAN_MB ) Identifier Version +/* - -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- */ +/* - -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- */ +/* - -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- */ + AT91C_CAN_MTIMESTAMP EQU( 0xFFFF << 0 ); + -( CAN_MB ) Timer Value + AT91C_CAN_MDLC EQU( 0xF << 16 ); + -( CAN_MB ) Mailbox Data Length Code + AT91C_CAN_MRTR EQU( 0x1 << 20 ); + -( CAN_MB ) Mailbox Remote Transmission Request + AT91C_CAN_MABT EQU( 0x1 << 22 ); + -( CAN_MB ) Mailbox Message Abort + AT91C_CAN_MRDY EQU( 0x1 << 23 ); + -( CAN_MB ) Mailbox Ready + AT91C_CAN_MMI EQU( 0x1 << 24 ); + -( CAN_MB ) Mailbox Message Ignored +/* - -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- */ +/* - -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- */ +/* - -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- */ + AT91C_CAN_MACR EQU( 0x1 << 22 ); + -( CAN_MB ) Abort Request + + for Mailbox + AT91C_CAN_MTCR EQU( 0x1 << 23 ); + -( CAN_MB ) Mailbox Transfer Command + +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Control Area Network Interface */ +/* - ***************************************************************************** */ +/* - -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- */ + AT91C_CAN_CANEN EQU( 0x1 << 0 ); + -( CAN ) CAN Controller Enable + AT91C_CAN_LPM EQU( 0x1 << 1 ); + -( CAN ) Disable / Enable Low Power Mode + AT91C_CAN_ABM EQU( 0x1 << 2 ); + -( CAN ) Disable / Enable Autobaud / Listen Mode + AT91C_CAN_OVL EQU( 0x1 << 3 ); + -( CAN ) Disable / Enable Overload Frame + AT91C_CAN_TEOF EQU( 0x1 << 4 ); + -( CAN ) Time Stamp messages at each end of Frame + AT91C_CAN_TTM EQU( 0x1 << 5 ); + -( CAN ) Disable / Enable Time Trigger Mode + AT91C_CAN_TIMFRZ EQU( 0x1 << 6 ); + -( CAN ) Enable Timer Freeze + AT91C_CAN_DRPT EQU( 0x1 << 7 ); + -( CAN ) Disable Repeat +/* - -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- */ + AT91C_CAN_MB0 EQU( 0x1 << 0 ); + -( CAN ) Mailbox 0 Flag + AT91C_CAN_MB1 EQU( 0x1 << 1 ); + -( CAN ) Mailbox 1 Flag + AT91C_CAN_MB2 EQU( 0x1 << 2 ); + -( CAN ) Mailbox 2 Flag + AT91C_CAN_MB3 EQU( 0x1 << 3 ); + -( CAN ) Mailbox 3 Flag + AT91C_CAN_MB4 EQU( 0x1 << 4 ); + -( CAN ) Mailbox 4 Flag + AT91C_CAN_MB5 EQU( 0x1 << 5 ); + -( CAN ) Mailbox 5 Flag + AT91C_CAN_MB6 EQU( 0x1 << 6 ); + -( CAN ) Mailbox 6 Flag + AT91C_CAN_MB7 EQU( 0x1 << 7 ); + -( CAN ) Mailbox 7 Flag + AT91C_CAN_MB8 EQU( 0x1 << 8 ); + -( CAN ) Mailbox 8 Flag + AT91C_CAN_MB9 EQU( 0x1 << 9 ); + -( CAN ) Mailbox 9 Flag + AT91C_CAN_MB10 EQU( 0x1 << 10 ); + -( CAN ) Mailbox 10 Flag + AT91C_CAN_MB11 EQU( 0x1 << 11 ); + -( CAN ) Mailbox 11 Flag + AT91C_CAN_MB12 EQU( 0x1 << 12 ); + -( CAN ) Mailbox 12 Flag + AT91C_CAN_MB13 EQU( 0x1 << 13 ); + -( CAN ) Mailbox 13 Flag + AT91C_CAN_MB14 EQU( 0x1 << 14 ); + -( CAN ) Mailbox 14 Flag + AT91C_CAN_MB15 EQU( 0x1 << 15 ); + -( CAN ) Mailbox 15 Flag + AT91C_CAN_ERRA EQU( 0x1 << 16 ); + -( CAN ) Error Active Mode Flag + AT91C_CAN_WARN EQU( 0x1 << 17 ); + -( CAN ) Warning Limit Flag + AT91C_CAN_ERRP EQU( 0x1 << 18 ); + -( CAN ) Error Passive Mode Flag + AT91C_CAN_BOFF EQU( 0x1 << 19 ); + -( CAN ) Bus Off Mode Flag + AT91C_CAN_SLEEP EQU( 0x1 << 20 ); + -( CAN ) Sleep Flag + AT91C_CAN_WAKEUP EQU( 0x1 << 21 ); + -( CAN ) Wakeup Flag + AT91C_CAN_TOVF EQU( 0x1 << 22 ); + -( CAN ) Timer Overflow Flag + AT91C_CAN_TSTP EQU( 0x1 << 23 ); + -( CAN ) Timestamp Flag + AT91C_CAN_CERR EQU( 0x1 << 24 ); + -( CAN ) CRC Error + AT91C_CAN_SERR EQU( 0x1 << 25 ); + -( CAN ) Stuffing Error + AT91C_CAN_AERR EQU( 0x1 << 26 ); + -( CAN ) Acknowledgment Error + AT91C_CAN_FERR EQU( 0x1 << 27 ); + -( CAN ) Form Error + AT91C_CAN_BERR EQU( 0x1 << 28 ); + -( CAN ) Bit Error +/* - -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- */ +/* - -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- */ +/* - -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- */ + AT91C_CAN_RBSY EQU( 0x1 << 29 ); + -( CAN ) Receiver Busy + AT91C_CAN_TBSY EQU( 0x1 << 30 ); + -( CAN ) Transmitter Busy + AT91C_CAN_OVLY EQU( 0x1 << 31 ); + -( CAN ) Overload Busy +/* - -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- */ + AT91C_CAN_PHASE2 EQU( 0x7 << 0 ); + -( CAN ) Phase 2 segment + AT91C_CAN_PHASE1 EQU( 0x7 << 4 ); + -( CAN ) Phase 1 segment + AT91C_CAN_PROPAG EQU( 0x7 << 8 ); + -( CAN ) Programmation time segment + AT91C_CAN_SYNC EQU( 0x3 << 12 ); + -( CAN ) Re - synchronization jump width segment + AT91C_CAN_BRP EQU( 0x7F << 16 ); + -( CAN ) Baudrate Prescaler + AT91C_CAN_SMP EQU( 0x1 << 24 ); + -( CAN ) Sampling mode +/* - -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- */ + AT91C_CAN_TIMER EQU( 0xFFFF << 0 ); + -( CAN ) Timer field +/* - -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- */ +/* - -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- */ + AT91C_CAN_REC EQU( 0xFF << 0 ); + -( CAN ) Receive Error Counter + AT91C_CAN_TEC EQU( 0xFF << 16 ); + -( CAN ) Transmit Error Counter +/* - -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- */ + AT91C_CAN_TIMRST EQU( 0x1 << 31 ); + -( CAN ) Timer Reset Field +/* - -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- */ + +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 */ +/* - ***************************************************************************** */ +/* - -------- EMAC_NCR : (EMAC Offset: 0x0) -------- */ + AT91C_EMAC_LB EQU( 0x1 << 0 ); + -( EMAC ) Loopback.Optional.When set, loopback signal is at high level. + AT91C_EMAC_LLB EQU( 0x1 << 1 ); + -( EMAC ) Loopback local. + AT91C_EMAC_RE EQU( 0x1 << 2 ); + -( EMAC ) Receive enable. + AT91C_EMAC_TE EQU( 0x1 << 3 ); + -( EMAC ) Transmit enable. + AT91C_EMAC_MPE EQU( 0x1 << 4 ); + -( EMAC ) Management port enable. + AT91C_EMAC_CLRSTAT EQU( 0x1 << 5 ); + -( EMAC ) Clear statistics registers. + AT91C_EMAC_INCSTAT EQU( 0x1 << 6 ); + -( EMAC ) Increment statistics registers. + AT91C_EMAC_WESTAT EQU( 0x1 << 7 ); + -( EMAC ) Write enable + + for statistics registers. + AT91C_EMAC_BP EQU( 0x1 << 8 ); + -( EMAC ) Back pressure. + AT91C_EMAC_TSTART EQU( 0x1 << 9 ); + -( EMAC ) Start Transmission. + AT91C_EMAC_THALT EQU( 0x1 << 10 ); + -( EMAC ) Transmission Halt. + AT91C_EMAC_TPFR EQU( 0x1 << 11 ); + -( EMAC ) Transmit pause frame + AT91C_EMAC_TZQ EQU( 0x1 << 12 ); + -( EMAC ) Transmit zero quantum pause frame +/* - -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- */ + AT91C_EMAC_SPD EQU( 0x1 << 0 ); + -( EMAC ) Speed. + AT91C_EMAC_FD EQU( 0x1 << 1 ); + -( EMAC ) Full duplex. + AT91C_EMAC_JFRAME EQU( 0x1 << 3 ); + -( EMAC ) Jumbo Frames. + AT91C_EMAC_CAF EQU( 0x1 << 4 ); + -( EMAC ) Copy all frames. + AT91C_EMAC_NBC EQU( 0x1 << 5 ); + -( EMAC ) No broadcast. + AT91C_EMAC_MTI EQU( 0x1 << 6 ); + -( EMAC ) Multicast hash event enable + AT91C_EMAC_UNI EQU( 0x1 << 7 ); + -( EMAC ) Unicast hash enable. + AT91C_EMAC_BIG EQU( 0x1 << 8 ); + -( EMAC ) Receive 1522 bytes. + AT91C_EMAC_EAE EQU( 0x1 << 9 ); + -( EMAC ) External address match enable. + AT91C_EMAC_CLK EQU( 0x3 << 10 ); + -( EMAC ) + AT91C_EMAC_CLK_HCLK_8 EQU( 0x0 << 10 ); + -( EMAC ) HCLK divided by 8 + AT91C_EMAC_CLK_HCLK_16 EQU( 0x1 << 10 ); + -( EMAC ) HCLK divided by 16 + AT91C_EMAC_CLK_HCLK_32 EQU( 0x2 << 10 ); + -( EMAC ) HCLK divided by 32 + AT91C_EMAC_CLK_HCLK_64 EQU( 0x3 << 10 ); + -( EMAC ) HCLK divided by 64 + AT91C_EMAC_RTY EQU( 0x1 << 12 ); + -( EMAC ) + AT91C_EMAC_PAE EQU( 0x1 << 13 ); + -( EMAC ) + AT91C_EMAC_RBOF EQU( 0x3 << 14 ); + -( EMAC ) + AT91C_EMAC_RBOF_OFFSET_0 EQU( 0x0 << 14 ); + -( EMAC ) no offset from start of receive buffer + AT91C_EMAC_RBOF_OFFSET_1 EQU( 0x1 << 14 ); + -( EMAC ) one byte offset from start of receive buffer + AT91C_EMAC_RBOF_OFFSET_2 EQU( 0x2 << 14 ); + -( EMAC ) two bytes offset from start of receive buffer + AT91C_EMAC_RBOF_OFFSET_3 EQU( 0x3 << 14 ); + -( EMAC ) three bytes offset from start of receive buffer + AT91C_EMAC_RLCE EQU( 0x1 << 16 ); + -( EMAC ) Receive Length field Checking Enable + AT91C_EMAC_DRFCS EQU( 0x1 << 17 ); + -( EMAC ) Discard Receive FCS + AT91C_EMAC_EFRHD EQU( 0x1 << 18 ); + -( EMAC ) + AT91C_EMAC_IRXFCS EQU( 0x1 << 19 ); + -( EMAC ) Ignore RX FCS +/* - -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- */ + AT91C_EMAC_LINKR EQU( 0x1 << 0 ); + -( EMAC ) + AT91C_EMAC_MDIO EQU( 0x1 << 1 ); + -( EMAC ) + AT91C_EMAC_IDLE EQU( 0x1 << 2 ); + -( EMAC ) +/* - -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- */ + AT91C_EMAC_UBR EQU( 0x1 << 0 ); + -( EMAC ) + AT91C_EMAC_COL EQU( 0x1 << 1 ); + -( EMAC ) + AT91C_EMAC_RLES EQU( 0x1 << 2 ); + -( EMAC ) + AT91C_EMAC_TGO EQU( 0x1 << 3 ); + -( EMAC ) Transmit Go + AT91C_EMAC_BEX EQU( 0x1 << 4 ); + -( EMAC ) Buffers exhausted mid frame + AT91C_EMAC_COMP EQU( 0x1 << 5 ); + -( EMAC ) + AT91C_EMAC_UND EQU( 0x1 << 6 ); + -( EMAC ) +/* - -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */ + AT91C_EMAC_BNA EQU( 0x1 << 0 ); + -( EMAC ) + AT91C_EMAC_REC EQU( 0x1 << 1 ); + -( EMAC ) + AT91C_EMAC_OVR EQU( 0x1 << 2 ); + -( EMAC ) +/* - -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */ + AT91C_EMAC_MFD EQU( 0x1 << 0 ); + -( EMAC ) + AT91C_EMAC_RCOMP EQU( 0x1 << 1 ); + -( EMAC ) + AT91C_EMAC_RXUBR EQU( 0x1 << 2 ); + -( EMAC ) + AT91C_EMAC_TXUBR EQU( 0x1 << 3 ); + -( EMAC ) + AT91C_EMAC_TUNDR EQU( 0x1 << 4 ); + -( EMAC ) + AT91C_EMAC_RLEX EQU( 0x1 << 5 ); + -( EMAC ) + AT91C_EMAC_TXERR EQU( 0x1 << 6 ); + -( EMAC ) + AT91C_EMAC_TCOMP EQU( 0x1 << 7 ); + -( EMAC ) + AT91C_EMAC_LINK EQU( 0x1 << 9 ); + -( EMAC ) + AT91C_EMAC_ROVR EQU( 0x1 << 10 ); + -( EMAC ) + AT91C_EMAC_HRESP EQU( 0x1 << 11 ); + -( EMAC ) + AT91C_EMAC_PFRE EQU( 0x1 << 12 ); + -( EMAC ) + AT91C_EMAC_PTZ EQU( 0x1 << 13 ); + -( EMAC ) +/* - -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */ +/* - -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */ +/* - -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */ +/* - -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */ + AT91C_EMAC_DATA EQU( 0xFFFF << 0 ); + -( EMAC ) + AT91C_EMAC_CODE EQU( 0x3 << 16 ); + -( EMAC ) + AT91C_EMAC_REGA EQU( 0x1F << 18 ); + -( EMAC ) + AT91C_EMAC_PHYA EQU( 0x1F << 23 ); + -( EMAC ) + AT91C_EMAC_RW EQU( 0x3 << 28 ); + -( EMAC ) + AT91C_EMAC_SOF EQU( 0x3 << 30 ); + -( EMAC ) +/* - -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- */ + AT91C_EMAC_RMII EQU( 0x1 << 0 ); + -( EMAC ) Reduce MII +/* - -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- */ + AT91C_EMAC_IP EQU( 0xFFFF << 0 ); + -( EMAC ) ARP request IP address + AT91C_EMAC_MAG EQU( 0x1 << 16 ); + -( EMAC ) Magic packet event enable + AT91C_EMAC_ARP EQU( 0x1 << 17 ); + -( EMAC ) ARP request event enable + AT91C_EMAC_SA1 EQU( 0x1 << 18 ); + -( EMAC ) Specific address register 1 event enable +/* - -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- */ + AT91C_EMAC_REVREF EQU( 0xFFFF << 0 ); + -( EMAC ) + AT91C_EMAC_PARTREF EQU( 0xFFFF << 16 ); + -( EMAC ) + +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Analog to Digital Convertor */ +/* - ***************************************************************************** */ +/* - -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- */ + AT91C_ADC_SWRST EQU( 0x1 << 0 ); + -( ADC ) Software Reset + AT91C_ADC_START EQU( 0x1 << 1 ); + -( ADC ) Start Conversion +/* - -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- */ + AT91C_ADC_TRGEN EQU( 0x1 << 0 ); + -( ADC ) Trigger Enable + AT91C_ADC_TRGEN_DIS EQU( 0x0 ); + -( ADC ) Hardware triggers are disabled.Starting a conversion is only possible by software + AT91C_ADC_TRGEN_EN EQU( 0x1 ); + -( ADC ) Hardware trigger selected by TRGSEL field is enabled. + AT91C_ADC_TRGSEL EQU( 0x7 << 1 ); + -( ADC ) Trigger Selection + AT91C_ADC_TRGSEL_TIOA0 EQU( 0x0 << 1 ); + -( ADC ) Selected TRGSEL = TIAO0 + AT91C_ADC_TRGSEL_TIOA1 EQU( 0x1 << 1 ); + -( ADC ) Selected TRGSEL = TIAO1 + AT91C_ADC_TRGSEL_TIOA2 EQU( 0x2 << 1 ); + -( ADC ) Selected TRGSEL = TIAO2 + AT91C_ADC_TRGSEL_TIOA3 EQU( 0x3 << 1 ); + -( ADC ) Selected TRGSEL = TIAO3 + AT91C_ADC_TRGSEL_TIOA4 EQU( 0x4 << 1 ); + -( ADC ) Selected TRGSEL = TIAO4 + AT91C_ADC_TRGSEL_TIOA5 EQU( 0x5 << 1 ); + -( ADC ) Selected TRGSEL = TIAO5 + AT91C_ADC_TRGSEL_EXT EQU( 0x6 << 1 ); + -( ADC ) Selected TRGSEL = External Trigger + AT91C_ADC_LOWRES EQU( 0x1 << 4 ); + -( ADC ) Resolution. + AT91C_ADC_LOWRES_10_BIT EQU( 0x0 << 4 ); + -( ADC ) 10 - bit resolution + AT91C_ADC_LOWRES_8_BIT EQU( 0x1 << 4 ); + -( ADC ) 8 - bit resolution + AT91C_ADC_SLEEP EQU( 0x1 << 5 ); + -( ADC ) Sleep Mode + AT91C_ADC_SLEEP_NORMAL_MODE EQU( 0x0 << 5 ); + -( ADC ) Normal Mode + AT91C_ADC_SLEEP_MODE EQU( 0x1 << 5 ); + -( ADC ) Sleep Mode + AT91C_ADC_PRESCAL EQU( 0x3F << 8 ); + -( ADC ) Prescaler rate selection + AT91C_ADC_STARTUP EQU( 0x1F << 16 ); + -( ADC ) Startup Time + AT91C_ADC_SHTIM EQU( 0xF << 24 ); + -( ADC ) Sample & Hold Time +/* - -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- */ + AT91C_ADC_CH0 EQU( 0x1 << 0 ); + -( ADC ) Channel 0 + AT91C_ADC_CH1 EQU( 0x1 << 1 ); + -( ADC ) Channel 1 + AT91C_ADC_CH2 EQU( 0x1 << 2 ); + -( ADC ) Channel 2 + AT91C_ADC_CH3 EQU( 0x1 << 3 ); + -( ADC ) Channel 3 + AT91C_ADC_CH4 EQU( 0x1 << 4 ); + -( ADC ) Channel 4 + AT91C_ADC_CH5 EQU( 0x1 << 5 ); + -( ADC ) Channel 5 + AT91C_ADC_CH6 EQU( 0x1 << 6 ); + -( ADC ) Channel 6 + AT91C_ADC_CH7 EQU( 0x1 << 7 ); + -( ADC ) Channel 7 +/* - -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- */ +/* - -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- */ +/* - -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- */ + AT91C_ADC_EOC0 EQU( 0x1 << 0 ); + -( ADC ) End of Conversion + AT91C_ADC_EOC1 EQU( 0x1 << 1 ); + -( ADC ) End of Conversion + AT91C_ADC_EOC2 EQU( 0x1 << 2 ); + -( ADC ) End of Conversion + AT91C_ADC_EOC3 EQU( 0x1 << 3 ); + -( ADC ) End of Conversion + AT91C_ADC_EOC4 EQU( 0x1 << 4 ); + -( ADC ) End of Conversion + AT91C_ADC_EOC5 EQU( 0x1 << 5 ); + -( ADC ) End of Conversion + AT91C_ADC_EOC6 EQU( 0x1 << 6 ); + -( ADC ) End of Conversion + AT91C_ADC_EOC7 EQU( 0x1 << 7 ); + -( ADC ) End of Conversion + AT91C_ADC_OVRE0 EQU( 0x1 << 8 ); + -( ADC ) Overrun Error + AT91C_ADC_OVRE1 EQU( 0x1 << 9 ); + -( ADC ) Overrun Error + AT91C_ADC_OVRE2 EQU( 0x1 << 10 ); + -( ADC ) Overrun Error + AT91C_ADC_OVRE3 EQU( 0x1 << 11 ); + -( ADC ) Overrun Error + AT91C_ADC_OVRE4 EQU( 0x1 << 12 ); + -( ADC ) Overrun Error + AT91C_ADC_OVRE5 EQU( 0x1 << 13 ); + -( ADC ) Overrun Error + AT91C_ADC_OVRE6 EQU( 0x1 << 14 ); + -( ADC ) Overrun Error + AT91C_ADC_OVRE7 EQU( 0x1 << 15 ); + -( ADC ) Overrun Error + AT91C_ADC_DRDY EQU( 0x1 << 16 ); + -( ADC ) Data Ready + AT91C_ADC_GOVRE EQU( 0x1 << 17 ); + -( ADC ) General Overrun + AT91C_ADC_ENDRX EQU( 0x1 << 18 ); + -( ADC ) End of Receiver Transfer + AT91C_ADC_RXBUFF EQU( 0x1 << 19 ); + -( ADC ) RXBUFF Interrupt +/* - -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- */ + AT91C_ADC_LDATA EQU( 0x3FF << 0 ); + -( ADC ) Last Data Converted +/* - -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- */ +/* - -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- */ +/* - -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- */ +/* - -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- */ + AT91C_ADC_DATA EQU( 0x3FF << 0 ); + -( ADC ) Converted Data +/* - -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- */ +/* - -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- */ +/* - -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- */ +/* - -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- */ +/* - -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- */ +/* - -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- */ +/* - -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- */ + +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Advanced Encryption Standard */ +/* - ***************************************************************************** */ +/* - -------- AES_CR : (AES Offset: 0x0) Control Register -------- */ + AT91C_AES_START EQU( 0x1 << 0 ); + -( AES ) Starts Processing + AT91C_AES_SWRST EQU( 0x1 << 8 ); + -( AES ) Software Reset + AT91C_AES_LOADSEED EQU( 0x1 << 16 ); + -( AES ) Random Number Generator Seed Loading +/* - -------- AES_MR : (AES Offset: 0x4) Mode Register -------- */ + AT91C_AES_CIPHER EQU( 0x1 << 0 ); + -( AES ) Processing Mode + AT91C_AES_PROCDLY EQU( 0xF << 4 ); + -( AES ) Processing Delay + AT91C_AES_SMOD EQU( 0x3 << 8 ); + -( AES ) Start Mode + AT91C_AES_SMOD_MANUAL EQU( 0x0 << 8 ); + -( AES ) Manual Mode:The START bit in register AES_CR must be set to begin encryption or decryption. + AT91C_AES_SMOD_AUTO EQU( 0x1 << 8 ); + -( AES ) Auto Mode:no action in AES_CR is necessary( cf datasheet ). + AT91C_AES_SMOD_PDC EQU( 0x2 << 8 ); + -( AES ) PDC Mode( cf datasheet ). + AT91C_AES_OPMOD EQU( 0x7 << 12 ); + -( AES ) Operation Mode + AT91C_AES_OPMOD_ECB EQU( 0x0 << 12 ); + -( AES ) ECB Electronic CodeBook mode. + AT91C_AES_OPMOD_CBC EQU( 0x1 << 12 ); + -( AES ) CBC Cipher Block Chaining mode. + AT91C_AES_OPMOD_OFB EQU( 0x2 << 12 ); + -( AES ) OFB Output Feedback mode. + AT91C_AES_OPMOD_CFB EQU( 0x3 << 12 ); + -( AES ) CFB Cipher Feedback mode. + AT91C_AES_OPMOD_CTR EQU( 0x4 << 12 ); + -( AES ) CTR Counter mode. + AT91C_AES_LOD EQU( 0x1 << 15 ); + -( AES ) Last Output Data Mode + AT91C_AES_CFBS EQU( 0x7 << 16 ); + -( AES ) Cipher Feedback Data Size + AT91C_AES_CFBS_128_BIT EQU( 0x0 << 16 ); + -( AES ) 128 - bit. + AT91C_AES_CFBS_64_BIT EQU( 0x1 << 16 ); + -( AES ) 64 - bit. + AT91C_AES_CFBS_32_BIT EQU( 0x2 << 16 ); + -( AES ) 32 - bit. + AT91C_AES_CFBS_16_BIT EQU( 0x3 << 16 ); + -( AES ) 16 - bit. + AT91C_AES_CFBS_8_BIT EQU( 0x4 << 16 ); + -( AES ) 8 - bit. + AT91C_AES_CKEY EQU( 0xF << 20 ); + -( AES ) Countermeasure Key + AT91C_AES_CTYPE EQU( 0x1F << 24 ); + -( AES ) Countermeasure Type + AT91C_AES_CTYPE_TYPE1_EN EQU( 0x1 << 24 ); + -( AES ) Countermeasure type 1 is enabled. + AT91C_AES_CTYPE_TYPE2_EN EQU( 0x2 << 24 ); + -( AES ) Countermeasure type 2 is enabled. + AT91C_AES_CTYPE_TYPE3_EN EQU( 0x4 << 24 ); + -( AES ) Countermeasure type 3 is enabled. + AT91C_AES_CTYPE_TYPE4_EN EQU( 0x8 << 24 ); + -( AES ) Countermeasure type 4 is enabled. + AT91C_AES_CTYPE_TYPE5_EN EQU( 0x10 << 24 ); + -( AES ) Countermeasure type 5 is enabled. +/* - -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */ + AT91C_AES_DATRDY EQU( 0x1 << 0 ); + -( AES ) DATRDY + AT91C_AES_ENDRX EQU( 0x1 << 1 ); + -( AES ) PDC Read Buffer End + AT91C_AES_ENDTX EQU( 0x1 << 2 ); + -( AES ) PDC Write Buffer End + AT91C_AES_RXBUFF EQU( 0x1 << 3 ); + -( AES ) PDC Read Buffer Full + AT91C_AES_TXBUFE EQU( 0x1 << 4 ); + -( AES ) PDC Write Buffer Empty + AT91C_AES_URAD EQU( 0x1 << 8 ); + -( AES ) Unspecified Register Access Detection +/* - -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */ +/* - -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */ +/* - -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- */ + AT91C_AES_URAT EQU( 0x7 << 12 ); + -( AES ) Unspecified Register Access Type Status + AT91C_AES_URAT_IN_DAT_WRITE_DATPROC EQU( 0x0 << 12 ); + -( AES ) Input data register written during the data processing in PDC mode. + AT91C_AES_URAT_OUT_DAT_READ_DATPROC EQU( 0x1 << 12 ); + -( AES ) Output data register read during the data processing. + AT91C_AES_URAT_MODEREG_WRITE_DATPROC EQU( 0x2 << 12 ); + -( AES ) Mode register written during the data processing. + AT91C_AES_URAT_OUT_DAT_READ_SUBKEY EQU( 0x3 << 12 ); + -( AES ) Output data register read during the sub - keys generation. + AT91C_AES_URAT_MODEREG_WRITE_SUBKEY EQU( 0x4 << 12 ); + -( AES ) Mode register written during the sub - keys generation. + AT91C_AES_URAT_WO_REG_READ EQU( 0x5 << 12 ); + -( AES ) Write - only register read access. + +/* - ***************************************************************************** */ +/* - SOFTWARE API DEFINITION FOR Triple Data Encryption Standard */ +/* - ***************************************************************************** */ +/* - -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- */ + AT91C_TDES_START EQU( 0x1 << 0 ); + -( TDES ) Starts Processing + AT91C_TDES_SWRST EQU( 0x1 << 8 ); + -( TDES ) Software Reset +/* - -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- */ + AT91C_TDES_CIPHER EQU( 0x1 << 0 ); + -( TDES ) Processing Mode + AT91C_TDES_TDESMOD EQU( 0x1 << 1 ); + -( TDES ) Single or Triple DES Mode + AT91C_TDES_KEYMOD EQU( 0x1 << 4 ); + -( TDES ) Key Mode + AT91C_TDES_SMOD EQU( 0x3 << 8 ); + -( TDES ) Start Mode + AT91C_TDES_SMOD_MANUAL EQU( 0x0 << 8 ); + -( TDES ) Manual Mode:The START bit in register TDES_CR must be set to begin encryption or decryption. + AT91C_TDES_SMOD_AUTO EQU( 0x1 << 8 ); + -( TDES ) Auto Mode:no action in TDES_CR is necessary( cf datasheet ). + AT91C_TDES_SMOD_PDC EQU( 0x2 << 8 ); + -( TDES ) PDC Mode( cf datasheet ). + AT91C_TDES_OPMOD EQU( 0x3 << 12 ); + -( TDES ) Operation Mode + AT91C_TDES_OPMOD_ECB EQU( 0x0 << 12 ); + -( TDES ) ECB Electronic CodeBook mode. + AT91C_TDES_OPMOD_CBC EQU( 0x1 << 12 ); + -( TDES ) CBC Cipher Block Chaining mode. + AT91C_TDES_OPMOD_OFB EQU( 0x2 << 12 ); + -( TDES ) OFB Output Feedback mode. + AT91C_TDES_OPMOD_CFB EQU( 0x3 << 12 ); + -( TDES ) CFB Cipher Feedback mode. + AT91C_TDES_LOD EQU( 0x1 << 15 ); + -( TDES ) Last Output Data Mode + AT91C_TDES_CFBS EQU( 0x3 << 16 ); + -( TDES ) Cipher Feedback Data Size + AT91C_TDES_CFBS_64_BIT EQU( 0x0 << 16 ); + -( TDES ) 64 - bit. + AT91C_TDES_CFBS_32_BIT EQU( 0x1 << 16 ); + -( TDES ) 32 - bit. + AT91C_TDES_CFBS_16_BIT EQU( 0x2 << 16 ); + -( TDES ) 16 - bit. + AT91C_TDES_CFBS_8_BIT EQU( 0x3 << 16 ); + -( TDES ) 8 - bit. +/* - -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- */ + AT91C_TDES_DATRDY EQU( 0x1 << 0 ); + -( TDES ) DATRDY + AT91C_TDES_ENDRX EQU( 0x1 << 1 ); + -( TDES ) PDC Read Buffer End + AT91C_TDES_ENDTX EQU( 0x1 << 2 ); + -( TDES ) PDC Write Buffer End + AT91C_TDES_RXBUFF EQU( 0x1 << 3 ); + -( TDES ) PDC Read Buffer Full + AT91C_TDES_TXBUFE EQU( 0x1 << 4 ); + -( TDES ) PDC Write Buffer Empty + AT91C_TDES_URAD EQU( 0x1 << 8 ); + -( TDES ) Unspecified Register Access Detection +/* - -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- */ +/* - -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- */ +/* - -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- */ + AT91C_TDES_URAT EQU( 0x3 << 12 ); + -( TDES ) Unspecified Register Access Type Status + AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC EQU( 0x0 << 12 ); + -( TDES ) Input data register written during the data processing in PDC mode. + AT91C_TDES_URAT_OUT_DAT_READ_DATPROC EQU( 0x1 << 12 ); + -( TDES ) Output data register read during the data processing. + AT91C_TDES_URAT_MODEREG_WRITE_DATPROC EQU( 0x2 << 12 ); + -( TDES ) Mode register written during the data processing. + AT91C_TDES_URAT_WO_REG_READ EQU( 0x3 << 12 ); + -( TDES ) Write - only register read access. + +/* - ***************************************************************************** */ +/* - REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 */ +/* - ***************************************************************************** */ +/* - ========== Register definition for SYS peripheral ========== */ +/* - ========== Register definition for AIC peripheral ========== */ + AT91C_AIC_IVR EQU( 0xFFFFF100 ); + -( AIC ) IRQ Vector Register + AT91C_AIC_SMR EQU( 0xFFFFF000 ); + -( AIC ) Source Mode Register + AT91C_AIC_FVR EQU( 0xFFFFF104 ); + -( AIC ) FIQ Vector Register + AT91C_AIC_DCR EQU( 0xFFFFF138 ); + -( AIC ) Debug Control Register( Protect ) + AT91C_AIC_EOICR EQU( 0xFFFFF130 ); + -( AIC ) End of Interrupt Command Register + AT91C_AIC_SVR EQU( 0xFFFFF080 ); + -( AIC ) Source Vector Register + AT91C_AIC_FFSR EQU( 0xFFFFF148 ); + -( AIC ) Fast Forcing Status Register + AT91C_AIC_ICCR EQU( 0xFFFFF128 ); + -( AIC ) Interrupt Clear Command Register + AT91C_AIC_ISR EQU( 0xFFFFF108 ); + -( AIC ) Interrupt Status Register + AT91C_AIC_IMR EQU( 0xFFFFF110 ); + -( AIC ) Interrupt Mask Register + AT91C_AIC_IPR EQU( 0xFFFFF10C ); + -( AIC ) Interrupt Pending Register + AT91C_AIC_FFER EQU( 0xFFFFF140 ); + -( AIC ) Fast Forcing Enable Register + AT91C_AIC_IECR EQU( 0xFFFFF120 ); + -( AIC ) Interrupt Enable Command Register + AT91C_AIC_ISCR EQU( 0xFFFFF12C ); + -( AIC ) Interrupt Set Command Register + AT91C_AIC_FFDR EQU( 0xFFFFF144 ); + -( AIC ) Fast Forcing Disable Register + AT91C_AIC_CISR EQU( 0xFFFFF114 ); + -( AIC ) Core Interrupt Status Register + AT91C_AIC_IDCR EQU( 0xFFFFF124 ); + -( AIC ) Interrupt Disable Command Register + AT91C_AIC_SPU EQU( 0xFFFFF134 ); + -( AIC ) Spurious Vector Register +/* - ========== Register definition for PDC_DBGU peripheral ========== */ + AT91C_DBGU_TCR EQU( 0xFFFFF30C ); + -( PDC_DBGU ) Transmit Counter Register + AT91C_DBGU_RNPR EQU( 0xFFFFF310 ); + -( PDC_DBGU ) Receive Next Pointer Register + AT91C_DBGU_TNPR EQU( 0xFFFFF318 ); + -( PDC_DBGU ) Transmit Next Pointer Register + AT91C_DBGU_TPR EQU( 0xFFFFF308 ); + -( PDC_DBGU ) Transmit Pointer Register + AT91C_DBGU_RPR EQU( 0xFFFFF300 ); + -( PDC_DBGU ) Receive Pointer Register + AT91C_DBGU_RCR EQU( 0xFFFFF304 ); + -( PDC_DBGU ) Receive Counter Register + AT91C_DBGU_RNCR EQU( 0xFFFFF314 ); + -( PDC_DBGU ) Receive Next Counter Register + AT91C_DBGU_PTCR EQU( 0xFFFFF320 ); + -( PDC_DBGU ) PDC Transfer Control Register + AT91C_DBGU_PTSR EQU( 0xFFFFF324 ); + -( PDC_DBGU ) PDC Transfer Status Register + AT91C_DBGU_TNCR EQU( 0xFFFFF31C ); + -( PDC_DBGU ) Transmit Next Counter Register +/* - ========== Register definition for DBGU peripheral ========== */ + AT91C_DBGU_EXID EQU( 0xFFFFF244 ); + -( DBGU ) Chip ID Extension Register + AT91C_DBGU_BRGR EQU( 0xFFFFF220 ); + -( DBGU ) Baud Rate Generator Register + AT91C_DBGU_IDR EQU( 0xFFFFF20C ); + -( DBGU ) Interrupt Disable Register + AT91C_DBGU_CSR EQU( 0xFFFFF214 ); + -( DBGU ) Channel Status Register + AT91C_DBGU_CIDR EQU( 0xFFFFF240 ); + -( DBGU ) Chip ID Register + AT91C_DBGU_MR EQU( 0xFFFFF204 ); + -( DBGU ) Mode Register + AT91C_DBGU_IMR EQU( 0xFFFFF210 ); + -( DBGU ) Interrupt Mask Register + AT91C_DBGU_CR EQU( 0xFFFFF200 ); + -( DBGU ) Control Register + AT91C_DBGU_FNTR EQU( 0xFFFFF248 ); + -( DBGU ) Force NTRST Register + AT91C_DBGU_THR EQU( 0xFFFFF21C ); + -( DBGU ) Transmitter Holding Register + AT91C_DBGU_RHR EQU( 0xFFFFF218 ); + -( DBGU ) Receiver Holding Register + AT91C_DBGU_IER EQU( 0xFFFFF208 ); + -( DBGU ) Interrupt Enable Register +/* - ========== Register definition for PIOA peripheral ========== */ + AT91C_PIOA_ODR EQU( 0xFFFFF414 ); + -( PIOA ) Output Disable Registerr + AT91C_PIOA_SODR EQU( 0xFFFFF430 ); + -( PIOA ) Set Output Data Register + AT91C_PIOA_ISR EQU( 0xFFFFF44C ); + -( PIOA ) Interrupt Status Register + AT91C_PIOA_ABSR EQU( 0xFFFFF478 ); + -( PIOA ) AB Select Status Register + AT91C_PIOA_IER EQU( 0xFFFFF440 ); + -( PIOA ) Interrupt Enable Register + AT91C_PIOA_PPUDR EQU( 0xFFFFF460 ); + -( PIOA ) Pull - up Disable Register + AT91C_PIOA_IMR EQU( 0xFFFFF448 ); + -( PIOA ) Interrupt Mask Register + AT91C_PIOA_PER EQU( 0xFFFFF400 ); + -( PIOA ) PIO Enable Register + AT91C_PIOA_IFDR EQU( 0xFFFFF424 ); + -( PIOA ) Input Filter Disable Register + AT91C_PIOA_OWDR EQU( 0xFFFFF4A4 ); + -( PIOA ) Output Write Disable Register + AT91C_PIOA_MDSR EQU( 0xFFFFF458 ); + -( PIOA ) Multi - driver Status Register + AT91C_PIOA_IDR EQU( 0xFFFFF444 ); + -( PIOA ) Interrupt Disable Register + AT91C_PIOA_ODSR EQU( 0xFFFFF438 ); + -( PIOA ) Output Data Status Register + AT91C_PIOA_PPUSR EQU( 0xFFFFF468 ); + -( PIOA ) Pull - up Status Register + AT91C_PIOA_OWSR EQU( 0xFFFFF4A8 ); + -( PIOA ) Output Write Status Register + AT91C_PIOA_BSR EQU( 0xFFFFF474 ); + -( PIOA ) Select B Register + AT91C_PIOA_OWER EQU( 0xFFFFF4A0 ); + -( PIOA ) Output Write Enable Register + AT91C_PIOA_IFER EQU( 0xFFFFF420 ); + -( PIOA ) Input Filter Enable Register + AT91C_PIOA_PDSR EQU( 0xFFFFF43C ); + -( PIOA ) Pin Data Status Register + AT91C_PIOA_PPUER EQU( 0xFFFFF464 ); + -( PIOA ) Pull - up Enable Register + AT91C_PIOA_OSR EQU( 0xFFFFF418 ); + -( PIOA ) Output Status Register + AT91C_PIOA_ASR EQU( 0xFFFFF470 ); + -( PIOA ) Select A Register + AT91C_PIOA_MDDR EQU( 0xFFFFF454 ); + -( PIOA ) Multi - driver Disable Register + AT91C_PIOA_CODR EQU( 0xFFFFF434 ); + -( PIOA ) Clear Output Data Register + AT91C_PIOA_MDER EQU( 0xFFFFF450 ); + -( PIOA ) Multi - driver Enable Register + AT91C_PIOA_PDR EQU( 0xFFFFF404 ); + -( PIOA ) PIO Disable Register + AT91C_PIOA_IFSR EQU( 0xFFFFF428 ); + -( PIOA ) Input Filter Status Register + AT91C_PIOA_OER EQU( 0xFFFFF410 ); + -( PIOA ) Output Enable Register + AT91C_PIOA_PSR EQU( 0xFFFFF408 ); + -( PIOA ) PIO Status Register +/* - ========== Register definition for PIOB peripheral ========== */ + AT91C_PIOB_OWDR EQU( 0xFFFFF6A4 ); + -( PIOB ) Output Write Disable Register + AT91C_PIOB_MDER EQU( 0xFFFFF650 ); + -( PIOB ) Multi - driver Enable Register + AT91C_PIOB_PPUSR EQU( 0xFFFFF668 ); + -( PIOB ) Pull - up Status Register + AT91C_PIOB_IMR EQU( 0xFFFFF648 ); + -( PIOB ) Interrupt Mask Register + AT91C_PIOB_ASR EQU( 0xFFFFF670 ); + -( PIOB ) Select A Register + AT91C_PIOB_PPUDR EQU( 0xFFFFF660 ); + -( PIOB ) Pull - up Disable Register + AT91C_PIOB_PSR EQU( 0xFFFFF608 ); + -( PIOB ) PIO Status Register + AT91C_PIOB_IER EQU( 0xFFFFF640 ); + -( PIOB ) Interrupt Enable Register + AT91C_PIOB_CODR EQU( 0xFFFFF634 ); + -( PIOB ) Clear Output Data Register + AT91C_PIOB_OWER EQU( 0xFFFFF6A0 ); + -( PIOB ) Output Write Enable Register + AT91C_PIOB_ABSR EQU( 0xFFFFF678 ); + -( PIOB ) AB Select Status Register + AT91C_PIOB_IFDR EQU( 0xFFFFF624 ); + -( PIOB ) Input Filter Disable Register + AT91C_PIOB_PDSR EQU( 0xFFFFF63C ); + -( PIOB ) Pin Data Status Register + AT91C_PIOB_IDR EQU( 0xFFFFF644 ); + -( PIOB ) Interrupt Disable Register + AT91C_PIOB_OWSR EQU( 0xFFFFF6A8 ); + -( PIOB ) Output Write Status Register + AT91C_PIOB_PDR EQU( 0xFFFFF604 ); + -( PIOB ) PIO Disable Register + AT91C_PIOB_ODR EQU( 0xFFFFF614 ); + -( PIOB ) Output Disable Registerr + AT91C_PIOB_IFSR EQU( 0xFFFFF628 ); + -( PIOB ) Input Filter Status Register + AT91C_PIOB_PPUER EQU( 0xFFFFF664 ); + -( PIOB ) Pull - up Enable Register + AT91C_PIOB_SODR EQU( 0xFFFFF630 ); + -( PIOB ) Set Output Data Register + AT91C_PIOB_ISR EQU( 0xFFFFF64C ); + -( PIOB ) Interrupt Status Register + AT91C_PIOB_ODSR EQU( 0xFFFFF638 ); + -( PIOB ) Output Data Status Register + AT91C_PIOB_OSR EQU( 0xFFFFF618 ); + -( PIOB ) Output Status Register + AT91C_PIOB_MDSR EQU( 0xFFFFF658 ); + -( PIOB ) Multi - driver Status Register + AT91C_PIOB_IFER EQU( 0xFFFFF620 ); + -( PIOB ) Input Filter Enable Register + AT91C_PIOB_BSR EQU( 0xFFFFF674 ); + -( PIOB ) Select B Register + AT91C_PIOB_MDDR EQU( 0xFFFFF654 ); + -( PIOB ) Multi - driver Disable Register + AT91C_PIOB_OER EQU( 0xFFFFF610 ); + -( PIOB ) Output Enable Register + AT91C_PIOB_PER EQU( 0xFFFFF600 ); + -( PIOB ) PIO Enable Register +/* - ========== Register definition for CKGR peripheral ========== */ + AT91C_CKGR_MOR EQU( 0xFFFFFC20 ); + -( CKGR ) Main Oscillator Register + AT91C_CKGR_PLLR EQU( 0xFFFFFC2C ); + -( CKGR ) PLL Register + AT91C_CKGR_MCFR EQU( 0xFFFFFC24 ); + -( CKGR ) Main Clock Frequency Register +/* - ========== Register definition for PMC peripheral ========== */ + AT91C_PMC_IDR EQU( 0xFFFFFC64 ); + -( PMC ) Interrupt Disable Register + AT91C_PMC_MOR EQU( 0xFFFFFC20 ); + -( PMC ) Main Oscillator Register + AT91C_PMC_PLLR EQU( 0xFFFFFC2C ); + -( PMC ) PLL Register + AT91C_PMC_PCER EQU( 0xFFFFFC10 ); + -( PMC ) Peripheral Clock Enable Register + AT91C_PMC_PCKR EQU( 0xFFFFFC40 ); + -( PMC ) Programmable Clock Register + AT91C_PMC_MCKR EQU( 0xFFFFFC30 ); + -( PMC ) Master Clock Register + AT91C_PMC_SCDR EQU( 0xFFFFFC04 ); + -( PMC ) System Clock Disable Register + AT91C_PMC_PCDR EQU( 0xFFFFFC14 ); + -( PMC ) Peripheral Clock Disable Register + AT91C_PMC_SCSR EQU( 0xFFFFFC08 ); + -( PMC ) System Clock Status Register + AT91C_PMC_PCSR EQU( 0xFFFFFC18 ); + -( PMC ) Peripheral Clock Status Register + AT91C_PMC_MCFR EQU( 0xFFFFFC24 ); + -( PMC ) Main Clock Frequency Register + AT91C_PMC_SCER EQU( 0xFFFFFC00 ); + -( PMC ) System Clock Enable Register + AT91C_PMC_IMR EQU( 0xFFFFFC6C ); + -( PMC ) Interrupt Mask Register + AT91C_PMC_IER EQU( 0xFFFFFC60 ); + -( PMC ) Interrupt Enable Register + AT91C_PMC_SR EQU( 0xFFFFFC68 ); + -( PMC ) Status Register +/* - ========== Register definition for RSTC peripheral ========== */ + AT91C_RSTC_RCR EQU( 0xFFFFFD00 ); + -( RSTC ) Reset Control Register + AT91C_RSTC_RMR EQU( 0xFFFFFD08 ); + -( RSTC ) Reset Mode Register + AT91C_RSTC_RSR EQU( 0xFFFFFD04 ); + -( RSTC ) Reset Status Register +/* - ========== Register definition for RTTC peripheral ========== */ + AT91C_RTTC_RTSR EQU( 0xFFFFFD2C ); + -( RTTC ) Real - time Status Register + AT91C_RTTC_RTMR EQU( 0xFFFFFD20 ); + -( RTTC ) Real - time Mode Register + AT91C_RTTC_RTVR EQU( 0xFFFFFD28 ); + -( RTTC ) Real - time Value Register + AT91C_RTTC_RTAR EQU( 0xFFFFFD24 ); + -( RTTC ) Real - time Alarm Register +/* - ========== Register definition for PITC peripheral ========== */ + AT91C_PITC_PIVR EQU( 0xFFFFFD38 ); + -( PITC ) Period Interval Value Register + AT91C_PITC_PISR EQU( 0xFFFFFD34 ); + -( PITC ) Period Interval Status Register + AT91C_PITC_PIIR EQU( 0xFFFFFD3C ); + -( PITC ) Period Interval Image Register + AT91C_PITC_PIMR EQU( 0xFFFFFD30 ); + -( PITC ) Period Interval Mode Register +/* - ========== Register definition for WDTC peripheral ========== */ + AT91C_WDTC_WDCR EQU( 0xFFFFFD40 ); + -( WDTC ) Watchdog Control Register + AT91C_WDTC_WDSR EQU( 0xFFFFFD48 ); + -( WDTC ) Watchdog Status Register + AT91C_WDTC_WDMR EQU( 0xFFFFFD44 ); + -( WDTC ) Watchdog Mode Register +/* - ========== Register definition for VREG peripheral ========== */ + AT91C_VREG_MR EQU( 0xFFFFFD60 ); + -( VREG ) Voltage Regulator Mode Register +/* - ========== Register definition for MC peripheral ========== */ + AT91C_MC_ASR EQU( 0xFFFFFF04 ); + -( MC ) MC Abort Status Register + AT91C_MC_RCR EQU( 0xFFFFFF00 ); + -( MC ) MC Remap Control Register + AT91C_MC_FCR EQU( 0xFFFFFF64 ); + -( MC ) MC Flash Command Register + AT91C_MC_AASR EQU( 0xFFFFFF08 ); + -( MC ) MC Abort Address Status Register + AT91C_MC_FSR EQU( 0xFFFFFF68 ); + -( MC ) MC Flash Status Register + AT91C_MC_FMR EQU( 0xFFFFFF60 ); + -( MC ) MC Flash Mode Register +/* - ========== Register definition for PDC_SPI1 peripheral ========== */ + AT91C_SPI1_PTCR EQU( 0xFFFE4120 ); + -( PDC_SPI1 ) PDC Transfer Control Register + AT91C_SPI1_RPR EQU( 0xFFFE4100 ); + -( PDC_SPI1 ) Receive Pointer Register + AT91C_SPI1_TNCR EQU( 0xFFFE411C ); + -( PDC_SPI1 ) Transmit Next Counter Register + AT91C_SPI1_TPR EQU( 0xFFFE4108 ); + -( PDC_SPI1 ) Transmit Pointer Register + AT91C_SPI1_TNPR EQU( 0xFFFE4118 ); + -( PDC_SPI1 ) Transmit Next Pointer Register + AT91C_SPI1_TCR EQU( 0xFFFE410C ); + -( PDC_SPI1 ) Transmit Counter Register + AT91C_SPI1_RCR EQU( 0xFFFE4104 ); + -( PDC_SPI1 ) Receive Counter Register + AT91C_SPI1_RNPR EQU( 0xFFFE4110 ); + -( PDC_SPI1 ) Receive Next Pointer Register + AT91C_SPI1_RNCR EQU( 0xFFFE4114 ); + -( PDC_SPI1 ) Receive Next Counter Register + AT91C_SPI1_PTSR EQU( 0xFFFE4124 ); + -( PDC_SPI1 ) PDC Transfer Status Register +/* - ========== Register definition for SPI1 peripheral ========== */ + AT91C_SPI1_IMR EQU( 0xFFFE401C ); + -( SPI1 ) Interrupt Mask Register + AT91C_SPI1_IER EQU( 0xFFFE4014 ); + -( SPI1 ) Interrupt Enable Register + AT91C_SPI1_MR EQU( 0xFFFE4004 ); + -( SPI1 ) Mode Register + AT91C_SPI1_RDR EQU( 0xFFFE4008 ); + -( SPI1 ) Receive Data Register + AT91C_SPI1_IDR EQU( 0xFFFE4018 ); + -( SPI1 ) Interrupt Disable Register + AT91C_SPI1_SR EQU( 0xFFFE4010 ); + -( SPI1 ) Status Register + AT91C_SPI1_TDR EQU( 0xFFFE400C ); + -( SPI1 ) Transmit Data Register + AT91C_SPI1_CR EQU( 0xFFFE4000 ); + -( SPI1 ) Control Register + AT91C_SPI1_CSR EQU( 0xFFFE4030 ); + -( SPI1 ) Chip Select Register +/* - ========== Register definition for PDC_SPI0 peripheral ========== */ + AT91C_SPI0_PTCR EQU( 0xFFFE0120 ); + -( PDC_SPI0 ) PDC Transfer Control Register + AT91C_SPI0_TPR EQU( 0xFFFE0108 ); + -( PDC_SPI0 ) Transmit Pointer Register + AT91C_SPI0_TCR EQU( 0xFFFE010C ); + -( PDC_SPI0 ) Transmit Counter Register + AT91C_SPI0_RCR EQU( 0xFFFE0104 ); + -( PDC_SPI0 ) Receive Counter Register + AT91C_SPI0_PTSR EQU( 0xFFFE0124 ); + -( PDC_SPI0 ) PDC Transfer Status Register + AT91C_SPI0_RNPR EQU( 0xFFFE0110 ); + -( PDC_SPI0 ) Receive Next Pointer Register + AT91C_SPI0_RPR EQU( 0xFFFE0100 ); + -( PDC_SPI0 ) Receive Pointer Register + AT91C_SPI0_TNCR EQU( 0xFFFE011C ); + -( PDC_SPI0 ) Transmit Next Counter Register + AT91C_SPI0_RNCR EQU( 0xFFFE0114 ); + -( PDC_SPI0 ) Receive Next Counter Register + AT91C_SPI0_TNPR EQU( 0xFFFE0118 ); + -( PDC_SPI0 ) Transmit Next Pointer Register +/* - ========== Register definition for SPI0 peripheral ========== */ + AT91C_SPI0_IER EQU( 0xFFFE0014 ); + -( SPI0 ) Interrupt Enable Register + AT91C_SPI0_SR EQU( 0xFFFE0010 ); + -( SPI0 ) Status Register + AT91C_SPI0_IDR EQU( 0xFFFE0018 ); + -( SPI0 ) Interrupt Disable Register + AT91C_SPI0_CR EQU( 0xFFFE0000 ); + -( SPI0 ) Control Register + AT91C_SPI0_MR EQU( 0xFFFE0004 ); + -( SPI0 ) Mode Register + AT91C_SPI0_IMR EQU( 0xFFFE001C ); + -( SPI0 ) Interrupt Mask Register + AT91C_SPI0_TDR EQU( 0xFFFE000C ); + -( SPI0 ) Transmit Data Register + AT91C_SPI0_RDR EQU( 0xFFFE0008 ); + -( SPI0 ) Receive Data Register + AT91C_SPI0_CSR EQU( 0xFFFE0030 ); + -( SPI0 ) Chip Select Register +/* - ========== Register definition for PDC_US1 peripheral ========== */ + AT91C_US1_RNCR EQU( 0xFFFC4114 ); + -( PDC_US1 ) Receive Next Counter Register + AT91C_US1_PTCR EQU( 0xFFFC4120 ); + -( PDC_US1 ) PDC Transfer Control Register + AT91C_US1_TCR EQU( 0xFFFC410C ); + -( PDC_US1 ) Transmit Counter Register + AT91C_US1_PTSR EQU( 0xFFFC4124 ); + -( PDC_US1 ) PDC Transfer Status Register + AT91C_US1_TNPR EQU( 0xFFFC4118 ); + -( PDC_US1 ) Transmit Next Pointer Register + AT91C_US1_RCR EQU( 0xFFFC4104 ); + -( PDC_US1 ) Receive Counter Register + AT91C_US1_RNPR EQU( 0xFFFC4110 ); + -( PDC_US1 ) Receive Next Pointer Register + AT91C_US1_RPR EQU( 0xFFFC4100 ); + -( PDC_US1 ) Receive Pointer Register + AT91C_US1_TNCR EQU( 0xFFFC411C ); + -( PDC_US1 ) Transmit Next Counter Register + AT91C_US1_TPR EQU( 0xFFFC4108 ); + -( PDC_US1 ) Transmit Pointer Register +/* - ========== Register definition for US1 peripheral ========== */ + AT91C_US1_IF EQU( 0xFFFC404C ); + -( US1 ) IRDA_FILTER Register + AT91C_US1_NER EQU( 0xFFFC4044 ); + -( US1 ) Nb Errors Register + AT91C_US1_RTOR EQU( 0xFFFC4024 ); + -( US1 ) Receiver Time - out Register + AT91C_US1_CSR EQU( 0xFFFC4014 ); + -( US1 ) Channel Status Register + AT91C_US1_IDR EQU( 0xFFFC400C ); + -( US1 ) Interrupt Disable Register + AT91C_US1_IER EQU( 0xFFFC4008 ); + -( US1 ) Interrupt Enable Register + AT91C_US1_THR EQU( 0xFFFC401C ); + -( US1 ) Transmitter Holding Register + AT91C_US1_TTGR EQU( 0xFFFC4028 ); + -( US1 ) Transmitter Time - guard Register + AT91C_US1_RHR EQU( 0xFFFC4018 ); + -( US1 ) Receiver Holding Register + AT91C_US1_BRGR EQU( 0xFFFC4020 ); + -( US1 ) Baud Rate Generator Register + AT91C_US1_IMR EQU( 0xFFFC4010 ); + -( US1 ) Interrupt Mask Register + AT91C_US1_FIDI EQU( 0xFFFC4040 ); + -( US1 ) FI_DI_Ratio Register + AT91C_US1_CR EQU( 0xFFFC4000 ); + -( US1 ) Control Register + AT91C_US1_MR EQU( 0xFFFC4004 ); + -( US1 ) Mode Register +/* - ========== Register definition for PDC_US0 peripheral ========== */ + AT91C_US0_TNPR EQU( 0xFFFC0118 ); + -( PDC_US0 ) Transmit Next Pointer Register + AT91C_US0_RNPR EQU( 0xFFFC0110 ); + -( PDC_US0 ) Receive Next Pointer Register + AT91C_US0_TCR EQU( 0xFFFC010C ); + -( PDC_US0 ) Transmit Counter Register + AT91C_US0_PTCR EQU( 0xFFFC0120 ); + -( PDC_US0 ) PDC Transfer Control Register + AT91C_US0_PTSR EQU( 0xFFFC0124 ); + -( PDC_US0 ) PDC Transfer Status Register + AT91C_US0_TNCR EQU( 0xFFFC011C ); + -( PDC_US0 ) Transmit Next Counter Register + AT91C_US0_TPR EQU( 0xFFFC0108 ); + -( PDC_US0 ) Transmit Pointer Register + AT91C_US0_RCR EQU( 0xFFFC0104 ); + -( PDC_US0 ) Receive Counter Register + AT91C_US0_RPR EQU( 0xFFFC0100 ); + -( PDC_US0 ) Receive Pointer Register + AT91C_US0_RNCR EQU( 0xFFFC0114 ); + -( PDC_US0 ) Receive Next Counter Register +/* - ========== Register definition for US0 peripheral ========== */ + AT91C_US0_BRGR EQU( 0xFFFC0020 ); + -( US0 ) Baud Rate Generator Register + AT91C_US0_NER EQU( 0xFFFC0044 ); + -( US0 ) Nb Errors Register + AT91C_US0_CR EQU( 0xFFFC0000 ); + -( US0 ) Control Register + AT91C_US0_IMR EQU( 0xFFFC0010 ); + -( US0 ) Interrupt Mask Register + AT91C_US0_FIDI EQU( 0xFFFC0040 ); + -( US0 ) FI_DI_Ratio Register + AT91C_US0_TTGR EQU( 0xFFFC0028 ); + -( US0 ) Transmitter Time - guard Register + AT91C_US0_MR EQU( 0xFFFC0004 ); + -( US0 ) Mode Register + AT91C_US0_RTOR EQU( 0xFFFC0024 ); + -( US0 ) Receiver Time - out Register + AT91C_US0_CSR EQU( 0xFFFC0014 ); + -( US0 ) Channel Status Register + AT91C_US0_RHR EQU( 0xFFFC0018 ); + -( US0 ) Receiver Holding Register + AT91C_US0_IDR EQU( 0xFFFC000C ); + -( US0 ) Interrupt Disable Register + AT91C_US0_THR EQU( 0xFFFC001C ); + -( US0 ) Transmitter Holding Register + AT91C_US0_IF EQU( 0xFFFC004C ); + -( US0 ) IRDA_FILTER Register + AT91C_US0_IER EQU( 0xFFFC0008 ); + -( US0 ) Interrupt Enable Register +/* - ========== Register definition for PDC_SSC peripheral ========== */ + AT91C_SSC_TNCR EQU( 0xFFFD411C ); + -( PDC_SSC ) Transmit Next Counter Register + AT91C_SSC_RPR EQU( 0xFFFD4100 ); + -( PDC_SSC ) Receive Pointer Register + AT91C_SSC_RNCR EQU( 0xFFFD4114 ); + -( PDC_SSC ) Receive Next Counter Register + AT91C_SSC_TPR EQU( 0xFFFD4108 ); + -( PDC_SSC ) Transmit Pointer Register + AT91C_SSC_PTCR EQU( 0xFFFD4120 ); + -( PDC_SSC ) PDC Transfer Control Register + AT91C_SSC_TCR EQU( 0xFFFD410C ); + -( PDC_SSC ) Transmit Counter Register + AT91C_SSC_RCR EQU( 0xFFFD4104 ); + -( PDC_SSC ) Receive Counter Register + AT91C_SSC_RNPR EQU( 0xFFFD4110 ); + -( PDC_SSC ) Receive Next Pointer Register + AT91C_SSC_TNPR EQU( 0xFFFD4118 ); + -( PDC_SSC ) Transmit Next Pointer Register + AT91C_SSC_PTSR EQU( 0xFFFD4124 ); + -( PDC_SSC ) PDC Transfer Status Register +/* - ========== Register definition for SSC peripheral ========== */ + AT91C_SSC_RHR EQU( 0xFFFD4020 ); + -( SSC ) Receive Holding Register + AT91C_SSC_RSHR EQU( 0xFFFD4030 ); + -( SSC ) Receive Sync Holding Register + AT91C_SSC_TFMR EQU( 0xFFFD401C ); + -( SSC ) Transmit Frame Mode Register + AT91C_SSC_IDR EQU( 0xFFFD4048 ); + -( SSC ) Interrupt Disable Register + AT91C_SSC_THR EQU( 0xFFFD4024 ); + -( SSC ) Transmit Holding Register + AT91C_SSC_RCMR EQU( 0xFFFD4010 ); + -( SSC ) Receive Clock ModeRegister + AT91C_SSC_IER EQU( 0xFFFD4044 ); + -( SSC ) Interrupt Enable Register + AT91C_SSC_TSHR EQU( 0xFFFD4034 ); + -( SSC ) Transmit Sync Holding Register + AT91C_SSC_SR EQU( 0xFFFD4040 ); + -( SSC ) Status Register + AT91C_SSC_CMR EQU( 0xFFFD4004 ); + -( SSC ) Clock Mode Register + AT91C_SSC_TCMR EQU( 0xFFFD4018 ); + -( SSC ) Transmit Clock Mode Register + AT91C_SSC_CR EQU( 0xFFFD4000 ); + -( SSC ) Control Register + AT91C_SSC_IMR EQU( 0xFFFD404C ); + -( SSC ) Interrupt Mask Register + AT91C_SSC_RFMR EQU( 0xFFFD4014 ); + -( SSC ) Receive Frame Mode Register +/* - ========== Register definition for TWI peripheral ========== */ + AT91C_TWI_IER EQU( 0xFFFB8024 ); + -( TWI ) Interrupt Enable Register + AT91C_TWI_CR EQU( 0xFFFB8000 ); + -( TWI ) Control Register + AT91C_TWI_SR EQU( 0xFFFB8020 ); + -( TWI ) Status Register + AT91C_TWI_IMR EQU( 0xFFFB802C ); + -( TWI ) Interrupt Mask Register + AT91C_TWI_THR EQU( 0xFFFB8034 ); + -( TWI ) Transmit Holding Register + AT91C_TWI_IDR EQU( 0xFFFB8028 ); + -( TWI ) Interrupt Disable Register + AT91C_TWI_IADR EQU( 0xFFFB800C ); + -( TWI ) Internal Address Register + AT91C_TWI_MMR EQU( 0xFFFB8004 ); + -( TWI ) Master Mode Register + AT91C_TWI_CWGR EQU( 0xFFFB8010 ); + -( TWI ) Clock Waveform Generator Register + AT91C_TWI_RHR EQU( 0xFFFB8030 ); + -( TWI ) Receive Holding Register +/* - ========== Register definition for PWMC_CH3 peripheral ========== */ + AT91C_PWMC_CH3_CUPDR EQU( 0xFFFCC270 ); + -( PWMC_CH3 ) Channel Update Register + AT91C_PWMC_CH3_Reserved EQU( 0xFFFCC274 ); + -( PWMC_CH3 ) Reserved + AT91C_PWMC_CH3_CPRDR EQU( 0xFFFCC268 ); + -( PWMC_CH3 ) Channel Period Register + AT91C_PWMC_CH3_CDTYR EQU( 0xFFFCC264 ); + -( PWMC_CH3 ) Channel Duty Cycle Register + AT91C_PWMC_CH3_CCNTR EQU( 0xFFFCC26C ); + -( PWMC_CH3 ) Channel Counter Register + AT91C_PWMC_CH3_CMR EQU( 0xFFFCC260 ); + -( PWMC_CH3 ) Channel Mode Register +/* - ========== Register definition for PWMC_CH2 peripheral ========== */ + AT91C_PWMC_CH2_Reserved EQU( 0xFFFCC254 ); + -( PWMC_CH2 ) Reserved + AT91C_PWMC_CH2_CMR EQU( 0xFFFCC240 ); + -( PWMC_CH2 ) Channel Mode Register + AT91C_PWMC_CH2_CCNTR EQU( 0xFFFCC24C ); + -( PWMC_CH2 ) Channel Counter Register + AT91C_PWMC_CH2_CPRDR EQU( 0xFFFCC248 ); + -( PWMC_CH2 ) Channel Period Register + AT91C_PWMC_CH2_CUPDR EQU( 0xFFFCC250 ); + -( PWMC_CH2 ) Channel Update Register + AT91C_PWMC_CH2_CDTYR EQU( 0xFFFCC244 ); + -( PWMC_CH2 ) Channel Duty Cycle Register +/* - ========== Register definition for PWMC_CH1 peripheral ========== */ + AT91C_PWMC_CH1_Reserved EQU( 0xFFFCC234 ); + -( PWMC_CH1 ) Reserved + AT91C_PWMC_CH1_CUPDR EQU( 0xFFFCC230 ); + -( PWMC_CH1 ) Channel Update Register + AT91C_PWMC_CH1_CPRDR EQU( 0xFFFCC228 ); + -( PWMC_CH1 ) Channel Period Register + AT91C_PWMC_CH1_CCNTR EQU( 0xFFFCC22C ); + -( PWMC_CH1 ) Channel Counter Register + AT91C_PWMC_CH1_CDTYR EQU( 0xFFFCC224 ); + -( PWMC_CH1 ) Channel Duty Cycle Register + AT91C_PWMC_CH1_CMR EQU( 0xFFFCC220 ); + -( PWMC_CH1 ) Channel Mode Register +/* - ========== Register definition for PWMC_CH0 peripheral ========== */ + AT91C_PWMC_CH0_Reserved EQU( 0xFFFCC214 ); + -( PWMC_CH0 ) Reserved + AT91C_PWMC_CH0_CPRDR EQU( 0xFFFCC208 ); + -( PWMC_CH0 ) Channel Period Register + AT91C_PWMC_CH0_CDTYR EQU( 0xFFFCC204 ); + -( PWMC_CH0 ) Channel Duty Cycle Register + AT91C_PWMC_CH0_CMR EQU( 0xFFFCC200 ); + -( PWMC_CH0 ) Channel Mode Register + AT91C_PWMC_CH0_CUPDR EQU( 0xFFFCC210 ); + -( PWMC_CH0 ) Channel Update Register + AT91C_PWMC_CH0_CCNTR EQU( 0xFFFCC20C ); + -( PWMC_CH0 ) Channel Counter Register +/* - ========== Register definition for PWMC peripheral ========== */ + AT91C_PWMC_IDR EQU( 0xFFFCC014 ); + -( PWMC ) PWMC Interrupt Disable Register + AT91C_PWMC_DIS EQU( 0xFFFCC008 ); + -( PWMC ) PWMC Disable Register + AT91C_PWMC_IER EQU( 0xFFFCC010 ); + -( PWMC ) PWMC Interrupt Enable Register + AT91C_PWMC_VR EQU( 0xFFFCC0FC ); + -( PWMC ) PWMC Version Register + AT91C_PWMC_ISR EQU( 0xFFFCC01C ); + -( PWMC ) PWMC Interrupt Status Register + AT91C_PWMC_SR EQU( 0xFFFCC00C ); + -( PWMC ) PWMC Status Register + AT91C_PWMC_IMR EQU( 0xFFFCC018 ); + -( PWMC ) PWMC Interrupt Mask Register + AT91C_PWMC_MR EQU( 0xFFFCC000 ); + -( PWMC ) PWMC Mode Register + AT91C_PWMC_ENA EQU( 0xFFFCC004 ); + -( PWMC ) PWMC Enable Register +/* - ========== Register definition for UDP peripheral ========== */ + AT91C_UDP_IMR EQU( 0xFFFB0018 ); + -( UDP ) Interrupt Mask Register + AT91C_UDP_FADDR EQU( 0xFFFB0008 ); + -( UDP ) Function Address Register + AT91C_UDP_NUM EQU( 0xFFFB0000 ); + -( UDP ) Frame Number Register + AT91C_UDP_FDR EQU( 0xFFFB0050 ); + -( UDP ) Endpoint FIFO Data Register + AT91C_UDP_ISR EQU( 0xFFFB001C ); + -( UDP ) Interrupt Status Register + AT91C_UDP_CSR EQU( 0xFFFB0030 ); + -( UDP ) Endpoint Control and Status Register + AT91C_UDP_IDR EQU( 0xFFFB0014 ); + -( UDP ) Interrupt Disable Register + AT91C_UDP_ICR EQU( 0xFFFB0020 ); + -( UDP ) Interrupt Clear Register + AT91C_UDP_RSTEP EQU( 0xFFFB0028 ); + -( UDP ) Reset Endpoint Register + AT91C_UDP_TXVC EQU( 0xFFFB0074 ); + -( UDP ) Transceiver Control Register + AT91C_UDP_GLBSTATE EQU( 0xFFFB0004 ); + -( UDP ) Global State Register + AT91C_UDP_IER EQU( 0xFFFB0010 ); + -( UDP ) Interrupt Enable Register +/* - ========== Register definition for TC0 peripheral ========== */ + AT91C_TC0_SR EQU( 0xFFFA0020 ); + -( TC0 ) Status Register + AT91C_TC0_RC EQU( 0xFFFA001C ); + -( TC0 ) Register C + AT91C_TC0_RB EQU( 0xFFFA0018 ); + -( TC0 ) Register B + AT91C_TC0_CCR EQU( 0xFFFA0000 ); + -( TC0 ) Channel Control Register + AT91C_TC0_CMR EQU( 0xFFFA0004 ); + -( TC0 ) Channel Mode Register( Capture Mode / Waveform Mode ) + AT91C_TC0_IER EQU( 0xFFFA0024 ); + -( TC0 ) Interrupt Enable Register + AT91C_TC0_RA EQU( 0xFFFA0014 ); + -( TC0 ) Register A + AT91C_TC0_IDR EQU( 0xFFFA0028 ); + -( TC0 ) Interrupt Disable Register + AT91C_TC0_CV EQU( 0xFFFA0010 ); + -( TC0 ) Counter Value + AT91C_TC0_IMR EQU( 0xFFFA002C ); + -( TC0 ) Interrupt Mask Register +/* - ========== Register definition for TC1 peripheral ========== */ + AT91C_TC1_RB EQU( 0xFFFA0058 ); + -( TC1 ) Register B + AT91C_TC1_CCR EQU( 0xFFFA0040 ); + -( TC1 ) Channel Control Register + AT91C_TC1_IER EQU( 0xFFFA0064 ); + -( TC1 ) Interrupt Enable Register + AT91C_TC1_IDR EQU( 0xFFFA0068 ); + -( TC1 ) Interrupt Disable Register + AT91C_TC1_SR EQU( 0xFFFA0060 ); + -( TC1 ) Status Register + AT91C_TC1_CMR EQU( 0xFFFA0044 ); + -( TC1 ) Channel Mode Register( Capture Mode / Waveform Mode ) + AT91C_TC1_RA EQU( 0xFFFA0054 ); + -( TC1 ) Register A + AT91C_TC1_RC EQU( 0xFFFA005C ); + -( TC1 ) Register C + AT91C_TC1_IMR EQU( 0xFFFA006C ); + -( TC1 ) Interrupt Mask Register + AT91C_TC1_CV EQU( 0xFFFA0050 ); + -( TC1 ) Counter Value +/* - ========== Register definition for TC2 peripheral ========== */ + AT91C_TC2_CMR EQU( 0xFFFA0084 ); + -( TC2 ) Channel Mode Register( Capture Mode / Waveform Mode ) + AT91C_TC2_CCR EQU( 0xFFFA0080 ); + -( TC2 ) Channel Control Register + AT91C_TC2_CV EQU( 0xFFFA0090 ); + -( TC2 ) Counter Value + AT91C_TC2_RA EQU( 0xFFFA0094 ); + -( TC2 ) Register A + AT91C_TC2_RB EQU( 0xFFFA0098 ); + -( TC2 ) Register B + AT91C_TC2_IDR EQU( 0xFFFA00A8 ); + -( TC2 ) Interrupt Disable Register + AT91C_TC2_IMR EQU( 0xFFFA00AC ); + -( TC2 ) Interrupt Mask Register + AT91C_TC2_RC EQU( 0xFFFA009C ); + -( TC2 ) Register C + AT91C_TC2_IER EQU( 0xFFFA00A4 ); + -( TC2 ) Interrupt Enable Register + AT91C_TC2_SR EQU( 0xFFFA00A0 ); + -( TC2 ) Status Register +/* - ========== Register definition for TCB peripheral ========== */ + AT91C_TCB_BMR EQU( 0xFFFA00C4 ); + -( TCB ) TC Block Mode Register + AT91C_TCB_BCR EQU( 0xFFFA00C0 ); + -( TCB ) TC Block Control Register +/* - ========== Register definition for CAN_MB0 peripheral ========== */ + AT91C_CAN_MB0_MDL EQU( 0xFFFD0214 ); + -( CAN_MB0 ) MailBox Data Low Register + AT91C_CAN_MB0_MAM EQU( 0xFFFD0204 ); + -( CAN_MB0 ) MailBox Acceptance Mask Register + AT91C_CAN_MB0_MCR EQU( 0xFFFD021C ); + -( CAN_MB0 ) MailBox Control Register + AT91C_CAN_MB0_MID EQU( 0xFFFD0208 ); + -( CAN_MB0 ) MailBox ID Register + AT91C_CAN_MB0_MSR EQU( 0xFFFD0210 ); + -( CAN_MB0 ) MailBox Status Register + AT91C_CAN_MB0_MFID EQU( 0xFFFD020C ); + -( CAN_MB0 ) MailBox Family ID Register + AT91C_CAN_MB0_MDH EQU( 0xFFFD0218 ); + -( CAN_MB0 ) MailBox Data High Register + AT91C_CAN_MB0_MMR EQU( 0xFFFD0200 ); + -( CAN_MB0 ) MailBox Mode Register +/* - ========== Register definition for CAN_MB1 peripheral ========== */ + AT91C_CAN_MB1_MDL EQU( 0xFFFD0234 ); + -( CAN_MB1 ) MailBox Data Low Register + AT91C_CAN_MB1_MID EQU( 0xFFFD0228 ); + -( CAN_MB1 ) MailBox ID Register + AT91C_CAN_MB1_MMR EQU( 0xFFFD0220 ); + -( CAN_MB1 ) MailBox Mode Register + AT91C_CAN_MB1_MSR EQU( 0xFFFD0230 ); + -( CAN_MB1 ) MailBox Status Register + AT91C_CAN_MB1_MAM EQU( 0xFFFD0224 ); + -( CAN_MB1 ) MailBox Acceptance Mask Register + AT91C_CAN_MB1_MDH EQU( 0xFFFD0238 ); + -( CAN_MB1 ) MailBox Data High Register + AT91C_CAN_MB1_MCR EQU( 0xFFFD023C ); + -( CAN_MB1 ) MailBox Control Register + AT91C_CAN_MB1_MFID EQU( 0xFFFD022C ); + -( CAN_MB1 ) MailBox Family ID Register +/* - ========== Register definition for CAN_MB2 peripheral ========== */ + AT91C_CAN_MB2_MCR EQU( 0xFFFD025C ); + -( CAN_MB2 ) MailBox Control Register + AT91C_CAN_MB2_MDH EQU( 0xFFFD0258 ); + -( CAN_MB2 ) MailBox Data High Register + AT91C_CAN_MB2_MID EQU( 0xFFFD0248 ); + -( CAN_MB2 ) MailBox ID Register + AT91C_CAN_MB2_MDL EQU( 0xFFFD0254 ); + -( CAN_MB2 ) MailBox Data Low Register + AT91C_CAN_MB2_MMR EQU( 0xFFFD0240 ); + -( CAN_MB2 ) MailBox Mode Register + AT91C_CAN_MB2_MAM EQU( 0xFFFD0244 ); + -( CAN_MB2 ) MailBox Acceptance Mask Register + AT91C_CAN_MB2_MFID EQU( 0xFFFD024C ); + -( CAN_MB2 ) MailBox Family ID Register + AT91C_CAN_MB2_MSR EQU( 0xFFFD0250 ); + -( CAN_MB2 ) MailBox Status Register +/* - ========== Register definition for CAN_MB3 peripheral ========== */ + AT91C_CAN_MB3_MFID EQU( 0xFFFD026C ); + -( CAN_MB3 ) MailBox Family ID Register + AT91C_CAN_MB3_MAM EQU( 0xFFFD0264 ); + -( CAN_MB3 ) MailBox Acceptance Mask Register + AT91C_CAN_MB3_MID EQU( 0xFFFD0268 ); + -( CAN_MB3 ) MailBox ID Register + AT91C_CAN_MB3_MCR EQU( 0xFFFD027C ); + -( CAN_MB3 ) MailBox Control Register + AT91C_CAN_MB3_MMR EQU( 0xFFFD0260 ); + -( CAN_MB3 ) MailBox Mode Register + AT91C_CAN_MB3_MSR EQU( 0xFFFD0270 ); + -( CAN_MB3 ) MailBox Status Register + AT91C_CAN_MB3_MDL EQU( 0xFFFD0274 ); + -( CAN_MB3 ) MailBox Data Low Register + AT91C_CAN_MB3_MDH EQU( 0xFFFD0278 ); + -( CAN_MB3 ) MailBox Data High Register +/* - ========== Register definition for CAN_MB4 peripheral ========== */ + AT91C_CAN_MB4_MID EQU( 0xFFFD0288 ); + -( CAN_MB4 ) MailBox ID Register + AT91C_CAN_MB4_MMR EQU( 0xFFFD0280 ); + -( CAN_MB4 ) MailBox Mode Register + AT91C_CAN_MB4_MDH EQU( 0xFFFD0298 ); + -( CAN_MB4 ) MailBox Data High Register + AT91C_CAN_MB4_MFID EQU( 0xFFFD028C ); + -( CAN_MB4 ) MailBox Family ID Register + AT91C_CAN_MB4_MSR EQU( 0xFFFD0290 ); + -( CAN_MB4 ) MailBox Status Register + AT91C_CAN_MB4_MCR EQU( 0xFFFD029C ); + -( CAN_MB4 ) MailBox Control Register + AT91C_CAN_MB4_MDL EQU( 0xFFFD0294 ); + -( CAN_MB4 ) MailBox Data Low Register + AT91C_CAN_MB4_MAM EQU( 0xFFFD0284 ); + -( CAN_MB4 ) MailBox Acceptance Mask Register +/* - ========== Register definition for CAN_MB5 peripheral ========== */ + AT91C_CAN_MB5_MSR EQU( 0xFFFD02B0 ); + -( CAN_MB5 ) MailBox Status Register + AT91C_CAN_MB5_MCR EQU( 0xFFFD02BC ); + -( CAN_MB5 ) MailBox Control Register + AT91C_CAN_MB5_MFID EQU( 0xFFFD02AC ); + -( CAN_MB5 ) MailBox Family ID Register + AT91C_CAN_MB5_MDH EQU( 0xFFFD02B8 ); + -( CAN_MB5 ) MailBox Data High Register + AT91C_CAN_MB5_MID EQU( 0xFFFD02A8 ); + -( CAN_MB5 ) MailBox ID Register + AT91C_CAN_MB5_MMR EQU( 0xFFFD02A0 ); + -( CAN_MB5 ) MailBox Mode Register + AT91C_CAN_MB5_MDL EQU( 0xFFFD02B4 ); + -( CAN_MB5 ) MailBox Data Low Register + AT91C_CAN_MB5_MAM EQU( 0xFFFD02A4 ); + -( CAN_MB5 ) MailBox Acceptance Mask Register +/* - ========== Register definition for CAN_MB6 peripheral ========== */ + AT91C_CAN_MB6_MFID EQU( 0xFFFD02CC ); + -( CAN_MB6 ) MailBox Family ID Register + AT91C_CAN_MB6_MID EQU( 0xFFFD02C8 ); + -( CAN_MB6 ) MailBox ID Register + AT91C_CAN_MB6_MAM EQU( 0xFFFD02C4 ); + -( CAN_MB6 ) MailBox Acceptance Mask Register + AT91C_CAN_MB6_MSR EQU( 0xFFFD02D0 ); + -( CAN_MB6 ) MailBox Status Register + AT91C_CAN_MB6_MDL EQU( 0xFFFD02D4 ); + -( CAN_MB6 ) MailBox Data Low Register + AT91C_CAN_MB6_MCR EQU( 0xFFFD02DC ); + -( CAN_MB6 ) MailBox Control Register + AT91C_CAN_MB6_MDH EQU( 0xFFFD02D8 ); + -( CAN_MB6 ) MailBox Data High Register + AT91C_CAN_MB6_MMR EQU( 0xFFFD02C0 ); + -( CAN_MB6 ) MailBox Mode Register +/* - ========== Register definition for CAN_MB7 peripheral ========== */ + AT91C_CAN_MB7_MCR EQU( 0xFFFD02FC ); + -( CAN_MB7 ) MailBox Control Register + AT91C_CAN_MB7_MDH EQU( 0xFFFD02F8 ); + -( CAN_MB7 ) MailBox Data High Register + AT91C_CAN_MB7_MFID EQU( 0xFFFD02EC ); + -( CAN_MB7 ) MailBox Family ID Register + AT91C_CAN_MB7_MDL EQU( 0xFFFD02F4 ); + -( CAN_MB7 ) MailBox Data Low Register + AT91C_CAN_MB7_MID EQU( 0xFFFD02E8 ); + -( CAN_MB7 ) MailBox ID Register + AT91C_CAN_MB7_MMR EQU( 0xFFFD02E0 ); + -( CAN_MB7 ) MailBox Mode Register + AT91C_CAN_MB7_MAM EQU( 0xFFFD02E4 ); + -( CAN_MB7 ) MailBox Acceptance Mask Register + AT91C_CAN_MB7_MSR EQU( 0xFFFD02F0 ); + -( CAN_MB7 ) MailBox Status Register +/* - ========== Register definition for CAN peripheral ========== */ + AT91C_CAN_TCR EQU( 0xFFFD0024 ); + -( CAN ) Transfer Command Register + AT91C_CAN_IMR EQU( 0xFFFD000C ); + -( CAN ) Interrupt Mask Register + AT91C_CAN_IER EQU( 0xFFFD0004 ); + -( CAN ) Interrupt Enable Register + AT91C_CAN_ECR EQU( 0xFFFD0020 ); + -( CAN ) Error Counter Register + AT91C_CAN_TIMESTP EQU( 0xFFFD001C ); + -( CAN ) Time Stamp Register + AT91C_CAN_MR EQU( 0xFFFD0000 ); + -( CAN ) Mode Register + AT91C_CAN_IDR EQU( 0xFFFD0008 ); + -( CAN ) Interrupt Disable Register + AT91C_CAN_ACR EQU( 0xFFFD0028 ); + -( CAN ) Abort Command Register + AT91C_CAN_TIM EQU( 0xFFFD0018 ); + -( CAN ) Timer Register + AT91C_CAN_SR EQU( 0xFFFD0010 ); + -( CAN ) Status Register + AT91C_CAN_BR EQU( 0xFFFD0014 ); + -( CAN ) Baudrate Register + AT91C_CAN_VR EQU( 0xFFFD00FC ); + -( CAN ) Version Register +/* - ========== Register definition for EMAC peripheral ========== */ + AT91C_EMAC_ISR EQU( 0xFFFDC024 ); + -( EMAC ) Interrupt Status Register + AT91C_EMAC_SA4H EQU( 0xFFFDC0B4 ); + -( EMAC ) Specific Address 4 Top, Last 2 bytes + AT91C_EMAC_SA1L EQU( 0xFFFDC098 ); + -( EMAC ) Specific Address 1 Bottom, First 4 bytes + AT91C_EMAC_ELE EQU( 0xFFFDC078 ); + -( EMAC ) Excessive Length Errors Register + AT91C_EMAC_LCOL EQU( 0xFFFDC05C ); + -( EMAC ) Late Collision Register + AT91C_EMAC_RLE EQU( 0xFFFDC088 ); + -( EMAC ) Receive Length Field Mismatch Register + AT91C_EMAC_WOL EQU( 0xFFFDC0C4 ); + -( EMAC ) Wake On LAN Register + AT91C_EMAC_DTF EQU( 0xFFFDC058 ); + -( EMAC ) Deferred Transmission Frame Register + AT91C_EMAC_TUND EQU( 0xFFFDC064 ); + -( EMAC ) Transmit Underrun Error Register + AT91C_EMAC_NCR EQU( 0xFFFDC000 ); + -( EMAC ) Network Control Register + AT91C_EMAC_SA4L EQU( 0xFFFDC0B0 ); + -( EMAC ) Specific Address 4 Bottom, First 4 bytes + AT91C_EMAC_RSR EQU( 0xFFFDC020 ); + -( EMAC ) Receive Status Register + AT91C_EMAC_SA3L EQU( 0xFFFDC0A8 ); + -( EMAC ) Specific Address 3 Bottom, First 4 bytes + AT91C_EMAC_TSR EQU( 0xFFFDC014 ); + -( EMAC ) Transmit Status Register + AT91C_EMAC_IDR EQU( 0xFFFDC02C ); + -( EMAC ) Interrupt Disable Register + AT91C_EMAC_RSE EQU( 0xFFFDC074 ); + -( EMAC ) Receive Symbol Errors Register + AT91C_EMAC_ECOL EQU( 0xFFFDC060 ); + -( EMAC ) Excessive Collision Register + AT91C_EMAC_TID EQU( 0xFFFDC0B8 ); + -( EMAC ) Type ID Checking Register + AT91C_EMAC_HRB EQU( 0xFFFDC090 ); + -( EMAC ) Hash Address Bottom[ 31 : 0 ] + AT91C_EMAC_TBQP EQU( 0xFFFDC01C ); + -( EMAC ) Transmit Buffer Queue Pointer + AT91C_EMAC_USRIO EQU( 0xFFFDC0C0 ); + -( EMAC ) USER Input / Output Register + AT91C_EMAC_PTR EQU( 0xFFFDC038 ); + -( EMAC ) Pause Time Register + AT91C_EMAC_SA2H EQU( 0xFFFDC0A4 ); + -( EMAC ) Specific Address 2 Top, Last 2 bytes + AT91C_EMAC_ROV EQU( 0xFFFDC070 ); + -( EMAC ) Receive Overrun Errors Register + AT91C_EMAC_ALE EQU( 0xFFFDC054 ); + -( EMAC ) Alignment Error Register + AT91C_EMAC_RJA EQU( 0xFFFDC07C ); + -( EMAC ) Receive Jabbers Register + AT91C_EMAC_RBQP EQU( 0xFFFDC018 ); + -( EMAC ) Receive Buffer Queue Pointer + AT91C_EMAC_TPF EQU( 0xFFFDC08C ); + -( EMAC ) Transmitted Pause Frames Register + AT91C_EMAC_NCFGR EQU( 0xFFFDC004 ); + -( EMAC ) Network Configuration Register + AT91C_EMAC_HRT EQU( 0xFFFDC094 ); + -( EMAC ) Hash Address Top[ 63 : 32 ] + AT91C_EMAC_USF EQU( 0xFFFDC080 ); + -( EMAC ) Undersize Frames Register + AT91C_EMAC_FCSE EQU( 0xFFFDC050 ); + -( EMAC ) Frame Check Sequence Error Register + AT91C_EMAC_TPQ EQU( 0xFFFDC0BC ); + -( EMAC ) Transmit Pause Quantum Register + AT91C_EMAC_MAN EQU( 0xFFFDC034 ); + -( EMAC ) PHY Maintenance Register + AT91C_EMAC_FTO EQU( 0xFFFDC040 ); + -( EMAC ) Frames Transmitted OK Register + AT91C_EMAC_REV EQU( 0xFFFDC0FC ); + -( EMAC ) Revision Register + AT91C_EMAC_IMR EQU( 0xFFFDC030 ); + -( EMAC ) Interrupt Mask Register + AT91C_EMAC_SCF EQU( 0xFFFDC044 ); + -( EMAC ) Single Collision Frame Register + AT91C_EMAC_PFR EQU( 0xFFFDC03C ); + -( EMAC ) Pause Frames received Register + AT91C_EMAC_MCF EQU( 0xFFFDC048 ); + -( EMAC ) Multiple Collision Frame Register + AT91C_EMAC_NSR EQU( 0xFFFDC008 ); + -( EMAC ) Network Status Register + AT91C_EMAC_SA2L EQU( 0xFFFDC0A0 ); + -( EMAC ) Specific Address 2 Bottom, First 4 bytes + AT91C_EMAC_FRO EQU( 0xFFFDC04C ); + -( EMAC ) Frames Received OK Register + AT91C_EMAC_IER EQU( 0xFFFDC028 ); + -( EMAC ) Interrupt Enable Register + AT91C_EMAC_SA1H EQU( 0xFFFDC09C ); + -( EMAC ) Specific Address 1 Top, Last 2 bytes + AT91C_EMAC_CSE EQU( 0xFFFDC068 ); + -( EMAC ) Carrier Sense Error Register + AT91C_EMAC_SA3H EQU( 0xFFFDC0AC ); + -( EMAC ) Specific Address 3 Top, Last 2 bytes + AT91C_EMAC_RRE EQU( 0xFFFDC06C ); + -( EMAC ) Receive Resource Error Register + AT91C_EMAC_STE EQU( 0xFFFDC084 ); + -( EMAC ) SQE Test Error Register +/* - ========== Register definition for PDC_ADC peripheral ========== */ + AT91C_ADC_PTSR EQU( 0xFFFD8124 ); + -( PDC_ADC ) PDC Transfer Status Register + AT91C_ADC_PTCR EQU( 0xFFFD8120 ); + -( PDC_ADC ) PDC Transfer Control Register + AT91C_ADC_TNPR EQU( 0xFFFD8118 ); + -( PDC_ADC ) Transmit Next Pointer Register + AT91C_ADC_TNCR EQU( 0xFFFD811C ); + -( PDC_ADC ) Transmit Next Counter Register + AT91C_ADC_RNPR EQU( 0xFFFD8110 ); + -( PDC_ADC ) Receive Next Pointer Register + AT91C_ADC_RNCR EQU( 0xFFFD8114 ); + -( PDC_ADC ) Receive Next Counter Register + AT91C_ADC_RPR EQU( 0xFFFD8100 ); + -( PDC_ADC ) Receive Pointer Register + AT91C_ADC_TCR EQU( 0xFFFD810C ); + -( PDC_ADC ) Transmit Counter Register + AT91C_ADC_TPR EQU( 0xFFFD8108 ); + -( PDC_ADC ) Transmit Pointer Register + AT91C_ADC_RCR EQU( 0xFFFD8104 ); + -( PDC_ADC ) Receive Counter Register +/* - ========== Register definition for ADC peripheral ========== */ + AT91C_ADC_CDR2 EQU( 0xFFFD8038 ); + -( ADC ) ADC Channel Data Register 2 + AT91C_ADC_CDR3 EQU( 0xFFFD803C ); + -( ADC ) ADC Channel Data Register 3 + AT91C_ADC_CDR0 EQU( 0xFFFD8030 ); + -( ADC ) ADC Channel Data Register 0 + AT91C_ADC_CDR5 EQU( 0xFFFD8044 ); + -( ADC ) ADC Channel Data Register 5 + AT91C_ADC_CHDR EQU( 0xFFFD8014 ); + -( ADC ) ADC Channel Disable Register + AT91C_ADC_SR EQU( 0xFFFD801C ); + -( ADC ) ADC Status Register + AT91C_ADC_CDR4 EQU( 0xFFFD8040 ); + -( ADC ) ADC Channel Data Register 4 + AT91C_ADC_CDR1 EQU( 0xFFFD8034 ); + -( ADC ) ADC Channel Data Register 1 + AT91C_ADC_LCDR EQU( 0xFFFD8020 ); + -( ADC ) ADC Last Converted Data Register + AT91C_ADC_IDR EQU( 0xFFFD8028 ); + -( ADC ) ADC Interrupt Disable Register + AT91C_ADC_CR EQU( 0xFFFD8000 ); + -( ADC ) ADC Control Register + AT91C_ADC_CDR7 EQU( 0xFFFD804C ); + -( ADC ) ADC Channel Data Register 7 + AT91C_ADC_CDR6 EQU( 0xFFFD8048 ); + -( ADC ) ADC Channel Data Register 6 + AT91C_ADC_IER EQU( 0xFFFD8024 ); + -( ADC ) ADC Interrupt Enable Register + AT91C_ADC_CHER EQU( 0xFFFD8010 ); + -( ADC ) ADC Channel Enable Register + AT91C_ADC_CHSR EQU( 0xFFFD8018 ); + -( ADC ) ADC Channel Status Register + AT91C_ADC_MR EQU( 0xFFFD8004 ); + -( ADC ) ADC Mode Register + AT91C_ADC_IMR EQU( 0xFFFD802C ); + -( ADC ) ADC Interrupt Mask Register +/* - ========== Register definition for PDC_AES peripheral ========== */ + AT91C_AES_TPR EQU( 0xFFFA4108 ); + -( PDC_AES ) Transmit Pointer Register + AT91C_AES_PTCR EQU( 0xFFFA4120 ); + -( PDC_AES ) PDC Transfer Control Register + AT91C_AES_RNPR EQU( 0xFFFA4110 ); + -( PDC_AES ) Receive Next Pointer Register + AT91C_AES_TNCR EQU( 0xFFFA411C ); + -( PDC_AES ) Transmit Next Counter Register + AT91C_AES_TCR EQU( 0xFFFA410C ); + -( PDC_AES ) Transmit Counter Register + AT91C_AES_RCR EQU( 0xFFFA4104 ); + -( PDC_AES ) Receive Counter Register + AT91C_AES_RNCR EQU( 0xFFFA4114 ); + -( PDC_AES ) Receive Next Counter Register + AT91C_AES_TNPR EQU( 0xFFFA4118 ); + -( PDC_AES ) Transmit Next Pointer Register + AT91C_AES_RPR EQU( 0xFFFA4100 ); + -( PDC_AES ) Receive Pointer Register + AT91C_AES_PTSR EQU( 0xFFFA4124 ); + -( PDC_AES ) PDC Transfer Status Register +/* - ========== Register definition for AES peripheral ========== */ + AT91C_AES_IVxR EQU( 0xFFFA4060 ); + -( AES ) Initialization Vector x Register + AT91C_AES_MR EQU( 0xFFFA4004 ); + -( AES ) Mode Register + AT91C_AES_VR EQU( 0xFFFA40FC ); + -( AES ) AES Version Register + AT91C_AES_ODATAxR EQU( 0xFFFA4050 ); + -( AES ) Output Data x Register + AT91C_AES_IDATAxR EQU( 0xFFFA4040 ); + -( AES ) Input Data x Register + AT91C_AES_CR EQU( 0xFFFA4000 ); + -( AES ) Control Register + AT91C_AES_IDR EQU( 0xFFFA4014 ); + -( AES ) Interrupt Disable Register + AT91C_AES_IMR EQU( 0xFFFA4018 ); + -( AES ) Interrupt Mask Register + AT91C_AES_IER EQU( 0xFFFA4010 ); + -( AES ) Interrupt Enable Register + AT91C_AES_KEYWxR EQU( 0xFFFA4020 ); + -( AES ) Key Word x Register + AT91C_AES_ISR EQU( 0xFFFA401C ); + -( AES ) Interrupt Status Register +/* - ========== Register definition for PDC_TDES peripheral ========== */ + AT91C_TDES_RNCR EQU( 0xFFFA8114 ); + -( PDC_TDES ) Receive Next Counter Register + AT91C_TDES_TCR EQU( 0xFFFA810C ); + -( PDC_TDES ) Transmit Counter Register + AT91C_TDES_RCR EQU( 0xFFFA8104 ); + -( PDC_TDES ) Receive Counter Register + AT91C_TDES_TNPR EQU( 0xFFFA8118 ); + -( PDC_TDES ) Transmit Next Pointer Register + AT91C_TDES_RNPR EQU( 0xFFFA8110 ); + -( PDC_TDES ) Receive Next Pointer Register + AT91C_TDES_RPR EQU( 0xFFFA8100 ); + -( PDC_TDES ) Receive Pointer Register + AT91C_TDES_TNCR EQU( 0xFFFA811C ); + -( PDC_TDES ) Transmit Next Counter Register + AT91C_TDES_TPR EQU( 0xFFFA8108 ); + -( PDC_TDES ) Transmit Pointer Register + AT91C_TDES_PTSR EQU( 0xFFFA8124 ); + -( PDC_TDES ) PDC Transfer Status Register + AT91C_TDES_PTCR EQU( 0xFFFA8120 ); + -( PDC_TDES ) PDC Transfer Control Register +/* - ========== Register definition for TDES peripheral ========== */ + AT91C_TDES_KEY2WxR EQU( 0xFFFA8028 ); + -( TDES ) Key 2 Word x Register + AT91C_TDES_KEY3WxR EQU( 0xFFFA8030 ); + -( TDES ) Key 3 Word x Register + AT91C_TDES_IDR EQU( 0xFFFA8014 ); + -( TDES ) Interrupt Disable Register + AT91C_TDES_VR EQU( 0xFFFA80FC ); + -( TDES ) TDES Version Register + AT91C_TDES_IVxR EQU( 0xFFFA8060 ); + -( TDES ) Initialization Vector x Register + AT91C_TDES_ODATAxR EQU( 0xFFFA8050 ); + -( TDES ) Output Data x Register + AT91C_TDES_IMR EQU( 0xFFFA8018 ); + -( TDES ) Interrupt Mask Register + AT91C_TDES_MR EQU( 0xFFFA8004 ); + -( TDES ) Mode Register + AT91C_TDES_CR EQU( 0xFFFA8000 ); + -( TDES ) Control Register + AT91C_TDES_IER EQU( 0xFFFA8010 ); + -( TDES ) Interrupt Enable Register + AT91C_TDES_ISR EQU( 0xFFFA801C ); + -( TDES ) Interrupt Status Register + AT91C_TDES_IDATAxR EQU( 0xFFFA8040 ); + -( TDES ) Input Data x Register + AT91C_TDES_KEY1WxR EQU( 0xFFFA8020 ); + -( TDES ) Key 1 Word x Register + +/* - ***************************************************************************** */ +/* - PIO DEFINITIONS FOR AT91SAM7X256 */ +/* - ***************************************************************************** */ + AT91C_PIO_PA0 EQU( 1 << 0 ); + -Pin Controlled by PA0 + AT91C_PA0_RXD0 EQU( AT91C_PIO_PA0 ); + -USART 0 Receive Data + AT91C_PIO_PA1 EQU( 1 << 1 ); + -Pin Controlled by PA1 + AT91C_PA1_TXD0 EQU( AT91C_PIO_PA1 ); + -USART 0 Transmit Data + AT91C_PIO_PA10 EQU( 1 << 10 ); + -Pin Controlled by PA10 + AT91C_PA10_TWD EQU( AT91C_PIO_PA10 ); + -TWI Two - wire Serial Data + AT91C_PIO_PA11 EQU( 1 << 11 ); + -Pin Controlled by PA11 + AT91C_PA11_TWCK EQU( AT91C_PIO_PA11 ); + -TWI Two - wire Serial Clock + AT91C_PIO_PA12 EQU( 1 << 12 ); + -Pin Controlled by PA12 + AT91C_PA12_NPCS00 EQU( AT91C_PIO_PA12 ); + -SPI 0 Peripheral Chip Select 0 + AT91C_PIO_PA13 EQU( 1 << 13 ); + -Pin Controlled by PA13 + AT91C_PA13_NPCS01 EQU( AT91C_PIO_PA13 ); + -SPI 0 Peripheral Chip Select 1 + AT91C_PA13_PCK1 EQU( AT91C_PIO_PA13 ); + -PMC Programmable Clock Output 1 + AT91C_PIO_PA14 EQU( 1 << 14 ); + -Pin Controlled by PA14 + AT91C_PA14_NPCS02 EQU( AT91C_PIO_PA14 ); + -SPI 0 Peripheral Chip Select 2 + AT91C_PA14_IRQ1 EQU( AT91C_PIO_PA14 ); + -External Interrupt 1 + AT91C_PIO_PA15 EQU( 1 << 15 ); + -Pin Controlled by PA15 + AT91C_PA15_NPCS03 EQU( AT91C_PIO_PA15 ); + -SPI 0 Peripheral Chip Select 3 + AT91C_PA15_TCLK2 EQU( AT91C_PIO_PA15 ); + -Timer Counter 2 external clock input + AT91C_PIO_PA16 EQU( 1 << 16 ); + -Pin Controlled by PA16 + AT91C_PA16_MISO0 EQU( AT91C_PIO_PA16 ); + -SPI 0 Master In Slave + AT91C_PIO_PA17 EQU( 1 << 17 ); + -Pin Controlled by PA17 + AT91C_PA17_MOSI0 EQU( AT91C_PIO_PA17 ); + -SPI 0 Master Out Slave + AT91C_PIO_PA18 EQU( 1 << 18 ); + -Pin Controlled by PA18 + AT91C_PA18_SPCK0 EQU( AT91C_PIO_PA18 ); + -SPI 0 Serial Clock + AT91C_PIO_PA19 EQU( 1 << 19 ); + -Pin Controlled by PA19 + AT91C_PA19_CANRX EQU( AT91C_PIO_PA19 ); + -CAN Receive + AT91C_PIO_PA2 EQU( 1 << 2 ); + -Pin Controlled by PA2 + AT91C_PA2_SCK0 EQU( AT91C_PIO_PA2 ); + -USART 0 Serial Clock + AT91C_PA2_NPCS11 EQU( AT91C_PIO_PA2 ); + -SPI 1 Peripheral Chip Select 1 + AT91C_PIO_PA20 EQU( 1 << 20 ); + -Pin Controlled by PA20 + AT91C_PA20_CANTX EQU( AT91C_PIO_PA20 ); + -CAN Transmit + AT91C_PIO_PA21 EQU( 1 << 21 ); + -Pin Controlled by PA21 + AT91C_PA21_TF EQU( AT91C_PIO_PA21 ); + -SSC Transmit Frame Sync + AT91C_PA21_NPCS10 EQU( AT91C_PIO_PA21 ); + -SPI 1 Peripheral Chip Select 0 + AT91C_PIO_PA22 EQU( 1 << 22 ); + -Pin Controlled by PA22 + AT91C_PA22_TK EQU( AT91C_PIO_PA22 ); + -SSC Transmit Clock + AT91C_PA22_SPCK1 EQU( AT91C_PIO_PA22 ); + -SPI 1 Serial Clock + AT91C_PIO_PA23 EQU( 1 << 23 ); + -Pin Controlled by PA23 + AT91C_PA23_TD EQU( AT91C_PIO_PA23 ); + -SSC Transmit data + AT91C_PA23_MOSI1 EQU( AT91C_PIO_PA23 ); + -SPI 1 Master Out Slave + AT91C_PIO_PA24 EQU( 1 << 24 ); + -Pin Controlled by PA24 + AT91C_PA24_RD EQU( AT91C_PIO_PA24 ); + -SSC Receive Data + AT91C_PA24_MISO1 EQU( AT91C_PIO_PA24 ); + -SPI 1 Master In Slave + AT91C_PIO_PA25 EQU( 1 << 25 ); + -Pin Controlled by PA25 + AT91C_PA25_RK EQU( AT91C_PIO_PA25 ); + -SSC Receive Clock + AT91C_PA25_NPCS11 EQU( AT91C_PIO_PA25 ); + -SPI 1 Peripheral Chip Select 1 + AT91C_PIO_PA26 EQU( 1 << 26 ); + -Pin Controlled by PA26 + AT91C_PA26_RF EQU( AT91C_PIO_PA26 ); + -SSC Receive Frame Sync + AT91C_PA26_NPCS12 EQU( AT91C_PIO_PA26 ); + -SPI 1 Peripheral Chip Select 2 + AT91C_PIO_PA27 EQU( 1 << 27 ); + -Pin Controlled by PA27 + AT91C_PA27_DRXD EQU( AT91C_PIO_PA27 ); + -DBGU Debug Receive Data + AT91C_PA27_PCK3 EQU( AT91C_PIO_PA27 ); + -PMC Programmable Clock Output 3 + AT91C_PIO_PA28 EQU( 1 << 28 ); + -Pin Controlled by PA28 + AT91C_PA28_DTXD EQU( AT91C_PIO_PA28 ); + -DBGU Debug Transmit Data + AT91C_PIO_PA29 EQU( 1 << 29 ); + -Pin Controlled by PA29 + AT91C_PA29_FIQ EQU( AT91C_PIO_PA29 ); + -AIC Fast Interrupt Input + AT91C_PA29_NPCS13 EQU( AT91C_PIO_PA29 ); + -SPI 1 Peripheral Chip Select 3 + AT91C_PIO_PA3 EQU( 1 << 3 ); + -Pin Controlled by PA3 + AT91C_PA3_RTS0 EQU( AT91C_PIO_PA3 ); + -USART 0 Ready To Send + AT91C_PA3_NPCS12 EQU( AT91C_PIO_PA3 ); + -SPI 1 Peripheral Chip Select 2 + AT91C_PIO_PA30 EQU( 1 << 30 ); + -Pin Controlled by PA30 + AT91C_PA30_IRQ0 EQU( AT91C_PIO_PA30 ); + -External Interrupt 0 + AT91C_PA30_PCK2 EQU( AT91C_PIO_PA30 ); + -PMC Programmable Clock Output 2 + AT91C_PIO_PA4 EQU( 1 << 4 ); + -Pin Controlled by PA4 + AT91C_PA4_CTS0 EQU( AT91C_PIO_PA4 ); + -USART 0 Clear To Send + AT91C_PA4_NPCS13 EQU( AT91C_PIO_PA4 ); + -SPI 1 Peripheral Chip Select 3 + AT91C_PIO_PA5 EQU( 1 << 5 ); + -Pin Controlled by PA5 + AT91C_PA5_RXD1 EQU( AT91C_PIO_PA5 ); + -USART 1 Receive Data + AT91C_PIO_PA6 EQU( 1 << 6 ); + -Pin Controlled by PA6 + AT91C_PA6_TXD1 EQU( AT91C_PIO_PA6 ); + -USART 1 Transmit Data + AT91C_PIO_PA7 EQU( 1 << 7 ); + -Pin Controlled by PA7 + AT91C_PA7_SCK1 EQU( AT91C_PIO_PA7 ); + -USART 1 Serial Clock + AT91C_PA7_NPCS01 EQU( AT91C_PIO_PA7 ); + -SPI 0 Peripheral Chip Select 1 + AT91C_PIO_PA8 EQU( 1 << 8 ); + -Pin Controlled by PA8 + AT91C_PA8_RTS1 EQU( AT91C_PIO_PA8 ); + -USART 1 Ready To Send + AT91C_PA8_NPCS02 EQU( AT91C_PIO_PA8 ); + -SPI 0 Peripheral Chip Select 2 + AT91C_PIO_PA9 EQU( 1 << 9 ); + -Pin Controlled by PA9 + AT91C_PA9_CTS1 EQU( AT91C_PIO_PA9 ); + -USART 1 Clear To Send + AT91C_PA9_NPCS03 EQU( AT91C_PIO_PA9 ); + -SPI 0 Peripheral Chip Select 3 + AT91C_PIO_PB0 EQU( 1 << 0 ); + -Pin Controlled by PB0 + AT91C_PB0_ETXCK_EREFCK EQU( AT91C_PIO_PB0 ); + -Ethernet MAC Transmit Clock / Reference Clock + AT91C_PB0_PCK0 EQU( AT91C_PIO_PB0 ); + -PMC Programmable Clock Output 0 + AT91C_PIO_PB1 EQU( 1 << 1 ); + -Pin Controlled by PB1 + AT91C_PB1_ETXEN EQU( AT91C_PIO_PB1 ); + -Ethernet MAC Transmit Enable + AT91C_PIO_PB10 EQU( 1 << 10 ); + -Pin Controlled by PB10 + AT91C_PB10_ETX2 EQU( AT91C_PIO_PB10 ); + -Ethernet MAC Transmit Data 2 + AT91C_PB10_NPCS11 EQU( AT91C_PIO_PB10 ); + -SPI 1 Peripheral Chip Select 1 + AT91C_PIO_PB11 EQU( 1 << 11 ); + -Pin Controlled by PB11 + AT91C_PB11_ETX3 EQU( AT91C_PIO_PB11 ); + -Ethernet MAC Transmit Data 3 + AT91C_PB11_NPCS12 EQU( AT91C_PIO_PB11 ); + -SPI 1 Peripheral Chip Select 2 + AT91C_PIO_PB12 EQU( 1 << 12 ); + -Pin Controlled by PB12 + AT91C_PB12_ETXER EQU( AT91C_PIO_PB12 ); + -Ethernet MAC Transmit Coding Error + AT91C_PB12_TCLK0 EQU( AT91C_PIO_PB12 ); + -Timer Counter 0 external clock input + AT91C_PIO_PB13 EQU( 1 << 13 ); + -Pin Controlled by PB13 + AT91C_PB13_ERX2 EQU( AT91C_PIO_PB13 ); + -Ethernet MAC Receive Data 2 + AT91C_PB13_NPCS01 EQU( AT91C_PIO_PB13 ); + -SPI 0 Peripheral Chip Select 1 + AT91C_PIO_PB14 EQU( 1 << 14 ); + -Pin Controlled by PB14 + AT91C_PB14_ERX3 EQU( AT91C_PIO_PB14 ); + -Ethernet MAC Receive Data 3 + AT91C_PB14_NPCS02 EQU( AT91C_PIO_PB14 ); + -SPI 0 Peripheral Chip Select 2 + AT91C_PIO_PB15 EQU( 1 << 15 ); + -Pin Controlled by PB15 + AT91C_PB15_ERXDV EQU( AT91C_PIO_PB15 ); + -Ethernet MAC Receive Data Valid + AT91C_PIO_PB16 EQU( 1 << 16 ); + -Pin Controlled by PB16 + AT91C_PB16_ECOL EQU( AT91C_PIO_PB16 ); + -Ethernet MAC Collision Detected + AT91C_PB16_NPCS13 EQU( AT91C_PIO_PB16 ); + -SPI 1 Peripheral Chip Select 3 + AT91C_PIO_PB17 EQU( 1 << 17 ); + -Pin Controlled by PB17 + AT91C_PB17_ERXCK EQU( AT91C_PIO_PB17 ); + -Ethernet MAC Receive Clock + AT91C_PB17_NPCS03 EQU( AT91C_PIO_PB17 ); + -SPI 0 Peripheral Chip Select 3 + AT91C_PIO_PB18 EQU( 1 << 18 ); + -Pin Controlled by PB18 + AT91C_PB18_EF100 EQU( AT91C_PIO_PB18 ); + -Ethernet MAC Force 100 Mbits / sec + AT91C_PB18_ADTRG EQU( AT91C_PIO_PB18 ); + -ADC External Trigger + AT91C_PIO_PB19 EQU( 1 << 19 ); + -Pin Controlled by PB19 + AT91C_PB19_PWM0 EQU( AT91C_PIO_PB19 ); + -PWM Channel 0 + AT91C_PB19_TCLK1 EQU( AT91C_PIO_PB19 ); + -Timer Counter 1 external clock input + AT91C_PIO_PB2 EQU( 1 << 2 ); + -Pin Controlled by PB2 + AT91C_PB2_ETX0 EQU( AT91C_PIO_PB2 ); + -Ethernet MAC Transmit Data 0 + AT91C_PIO_PB20 EQU( 1 << 20 ); + -Pin Controlled by PB20 + AT91C_PB20_PWM1 EQU( AT91C_PIO_PB20 ); + -PWM Channel 1 + AT91C_PB20_PCK0 EQU( AT91C_PIO_PB20 ); + -PMC Programmable Clock Output 0 + AT91C_PIO_PB21 EQU( 1 << 21 ); + -Pin Controlled by PB21 + AT91C_PB21_PWM2 EQU( AT91C_PIO_PB21 ); + -PWM Channel 2 + AT91C_PB21_PCK1 EQU( AT91C_PIO_PB21 ); + -PMC Programmable Clock Output 1 + AT91C_PIO_PB22 EQU( 1 << 22 ); + -Pin Controlled by PB22 + AT91C_PB22_PWM3 EQU( AT91C_PIO_PB22 ); + -PWM Channel 3 + AT91C_PB22_PCK2 EQU( AT91C_PIO_PB22 ); + -PMC Programmable Clock Output 2 + AT91C_PIO_PB23 EQU( 1 << 23 ); + -Pin Controlled by PB23 + AT91C_PB23_TIOA0 EQU( AT91C_PIO_PB23 ); + -Timer Counter 0 Multipurpose Timer I / O Pin A + AT91C_PB23_DCD1 EQU( AT91C_PIO_PB23 ); + -USART 1 Data Carrier Detect + AT91C_PIO_PB24 EQU( 1 << 24 ); + -Pin Controlled by PB24 + AT91C_PB24_TIOB0 EQU( AT91C_PIO_PB24 ); + -Timer Counter 0 Multipurpose Timer I / O Pin B + AT91C_PB24_DSR1 EQU( AT91C_PIO_PB24 ); + -USART 1 Data Set ready + AT91C_PIO_PB25 EQU( 1 << 25 ); + -Pin Controlled by PB25 + AT91C_PB25_TIOA1 EQU( AT91C_PIO_PB25 ); + -Timer Counter 1 Multipurpose Timer I / O Pin A + AT91C_PB25_DTR1 EQU( AT91C_PIO_PB25 ); + -USART 1 Data Terminal ready + AT91C_PIO_PB26 EQU( 1 << 26 ); + -Pin Controlled by PB26 + AT91C_PB26_TIOB1 EQU( AT91C_PIO_PB26 ); + -Timer Counter 1 Multipurpose Timer I / O Pin B + AT91C_PB26_RI1 EQU( AT91C_PIO_PB26 ); + -USART 1 Ring Indicator + AT91C_PIO_PB27 EQU( 1 << 27 ); + -Pin Controlled by PB27 + AT91C_PB27_TIOA2 EQU( AT91C_PIO_PB27 ); + -Timer Counter 2 Multipurpose Timer I / O Pin A + AT91C_PB27_PWM0 EQU( AT91C_PIO_PB27 ); + -PWM Channel 0 + AT91C_PIO_PB28 EQU( 1 << 28 ); + -Pin Controlled by PB28 + AT91C_PB28_TIOB2 EQU( AT91C_PIO_PB28 ); + -Timer Counter 2 Multipurpose Timer I / O Pin B + AT91C_PB28_PWM1 EQU( AT91C_PIO_PB28 ); + -PWM Channel 1 + AT91C_PIO_PB29 EQU( 1 << 29 ); + -Pin Controlled by PB29 + AT91C_PB29_PCK1 EQU( AT91C_PIO_PB29 ); + -PMC Programmable Clock Output 1 + AT91C_PB29_PWM2 EQU( AT91C_PIO_PB29 ); + -PWM Channel 2 + AT91C_PIO_PB3 EQU( 1 << 3 ); + -Pin Controlled by PB3 + AT91C_PB3_ETX1 EQU( AT91C_PIO_PB3 ); + -Ethernet MAC Transmit Data 1 + AT91C_PIO_PB30 EQU( 1 << 30 ); + -Pin Controlled by PB30 + AT91C_PB30_PCK2 EQU( AT91C_PIO_PB30 ); + -PMC Programmable Clock Output 2 + AT91C_PB30_PWM3 EQU( AT91C_PIO_PB30 ); + -PWM Channel 3 + AT91C_PIO_PB4 EQU( 1 << 4 ); + -Pin Controlled by PB4 + AT91C_PB4_ECRS_ECRSDV EQU( AT91C_PIO_PB4 ); + -Ethernet MAC Carrier Sense / Carrier Sense and Data Valid + AT91C_PIO_PB5 EQU( 1 << 5 ); + -Pin Controlled by PB5 + AT91C_PB5_ERX0 EQU( AT91C_PIO_PB5 ); + -Ethernet MAC Receive Data 0 + AT91C_PIO_PB6 EQU( 1 << 6 ); + -Pin Controlled by PB6 + AT91C_PB6_ERX1 EQU( AT91C_PIO_PB6 ); + -Ethernet MAC Receive Data 1 + AT91C_PIO_PB7 EQU( 1 << 7 ); + -Pin Controlled by PB7 + AT91C_PB7_ERXER EQU( AT91C_PIO_PB7 ); + -Ethernet MAC Receive Error + AT91C_PIO_PB8 EQU( 1 << 8 ); + -Pin Controlled by PB8 + AT91C_PB8_EMDC EQU( AT91C_PIO_PB8 ); + -Ethernet MAC Management Data Clock + AT91C_PIO_PB9 EQU( 1 << 9 ); + -Pin Controlled by PB9 + AT91C_PB9_EMDIO EQU( AT91C_PIO_PB9 ); + -Ethernet MAC Management Data Input / Output + +/* - ***************************************************************************** */ +/* - PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 */ +/* - ***************************************************************************** */ + AT91C_ID_FIQ EQU( 0 ); + -Advanced Interrupt Controller( FIQ ) + AT91C_ID_SYS EQU( 1 ); + -System Peripheral + AT91C_ID_PIOA EQU( 2 ); + -Parallel IO Controller A + AT91C_ID_PIOB EQU( 3 ); + -Parallel IO Controller B + AT91C_ID_SPI0 EQU( 4 ); + -Serial Peripheral Interface 0 + AT91C_ID_SPI1 EQU( 5 ); + -Serial Peripheral Interface 1 + AT91C_ID_US0 EQU( 6 ); + -USART 0 + AT91C_ID_US1 EQU( 7 ); + -USART 1 + AT91C_ID_SSC EQU( 8 ); + -Serial Synchronous Controller + AT91C_ID_TWI EQU( 9 ); + -Two - Wire Interface + AT91C_ID_PWMC EQU( 10 ); + -PWM Controller + AT91C_ID_UDP EQU( 11 ); + -USB Device Port + AT91C_ID_TC0 EQU( 12 ); + -Timer Counter 0 + AT91C_ID_TC1 EQU( 13 ); + -Timer Counter 1 + AT91C_ID_TC2 EQU( 14 ); + -Timer Counter 2 + AT91C_ID_CAN EQU( 15 ); + -Control Area Network Controller + AT91C_ID_EMAC EQU( 16 ); + -Ethernet MAC + AT91C_ID_ADC EQU( 17 ); + -Analog - to - Digital Converter + AT91C_ID_AES EQU( 18 ); + -Advanced Encryption Standard 128 - bit + AT91C_ID_TDES EQU( 19 ); + -Triple Data Encryption Standard + AT91C_ID_20_Reserved EQU( 20 ); + -Reserved + AT91C_ID_21_Reserved EQU( 21 ); + -Reserved + AT91C_ID_22_Reserved EQU( 22 ); + -Reserved + AT91C_ID_23_Reserved EQU( 23 ); + -Reserved + AT91C_ID_24_Reserved EQU( 24 ); + -Reserved + AT91C_ID_25_Reserved EQU( 25 ); + -Reserved + AT91C_ID_26_Reserved EQU( 26 ); + -Reserved + AT91C_ID_27_Reserved EQU( 27 ); + -Reserved + AT91C_ID_28_Reserved EQU( 28 ); + -Reserved + AT91C_ID_29_Reserved EQU( 29 ); + -Reserved + AT91C_ID_IRQ0 EQU( 30 ); + -Advanced Interrupt Controller( IRQ0 ) + AT91C_ID_IRQ1 EQU( 31 ); + -Advanced Interrupt Controller( IRQ1 ) + +/* - ***************************************************************************** */ +/* - BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 */ +/* - ***************************************************************************** */ + AT91C_BASE_SYS EQU( 0xFFFFF000 ); + -( SYS ) Base Address + AT91C_BASE_AIC EQU( 0xFFFFF000 ); + -( AIC ) Base Address + AT91C_BASE_PDC_DBGU EQU( 0xFFFFF300 ); + -( PDC_DBGU ) Base Address + AT91C_BASE_DBGU EQU( 0xFFFFF200 ); + -( DBGU ) Base Address + AT91C_BASE_PIOA EQU( 0xFFFFF400 ); + -( PIOA ) Base Address + AT91C_BASE_PIOB EQU( 0xFFFFF600 ); + -( PIOB ) Base Address + AT91C_BASE_CKGR EQU( 0xFFFFFC20 ); + -( CKGR ) Base Address + AT91C_BASE_PMC EQU( 0xFFFFFC00 ); + -( PMC ) Base Address + AT91C_BASE_RSTC EQU( 0xFFFFFD00 ); + -( RSTC ) Base Address + AT91C_BASE_RTTC EQU( 0xFFFFFD20 ); + -( RTTC ) Base Address + AT91C_BASE_PITC EQU( 0xFFFFFD30 ); + -( PITC ) Base Address + AT91C_BASE_WDTC EQU( 0xFFFFFD40 ); + -( WDTC ) Base Address + AT91C_BASE_VREG EQU( 0xFFFFFD60 ); + -( VREG ) Base Address + AT91C_BASE_MC EQU( 0xFFFFFF00 ); + -( MC ) Base Address + AT91C_BASE_PDC_SPI1 EQU( 0xFFFE4100 ); + -( PDC_SPI1 ) Base Address + AT91C_BASE_SPI1 EQU( 0xFFFE4000 ); + -( SPI1 ) Base Address + AT91C_BASE_PDC_SPI0 EQU( 0xFFFE0100 ); + -( PDC_SPI0 ) Base Address + AT91C_BASE_SPI0 EQU( 0xFFFE0000 ); + -( SPI0 ) Base Address + AT91C_BASE_PDC_US1 EQU( 0xFFFC4100 ); + -( PDC_US1 ) Base Address + AT91C_BASE_US1 EQU( 0xFFFC4000 ); + -( US1 ) Base Address + AT91C_BASE_PDC_US0 EQU( 0xFFFC0100 ); + -( PDC_US0 ) Base Address + AT91C_BASE_US0 EQU( 0xFFFC0000 ); + -( US0 ) Base Address + AT91C_BASE_PDC_SSC EQU( 0xFFFD4100 ); + -( PDC_SSC ) Base Address + AT91C_BASE_SSC EQU( 0xFFFD4000 ); + -( SSC ) Base Address + AT91C_BASE_TWI EQU( 0xFFFB8000 ); + -( TWI ) Base Address + AT91C_BASE_PWMC_CH3 EQU( 0xFFFCC260 ); + -( PWMC_CH3 ) Base Address + AT91C_BASE_PWMC_CH2 EQU( 0xFFFCC240 ); + -( PWMC_CH2 ) Base Address + AT91C_BASE_PWMC_CH1 EQU( 0xFFFCC220 ); + -( PWMC_CH1 ) Base Address + AT91C_BASE_PWMC_CH0 EQU( 0xFFFCC200 ); + -( PWMC_CH0 ) Base Address + AT91C_BASE_PWMC EQU( 0xFFFCC000 ); + -( PWMC ) Base Address + AT91C_BASE_UDP EQU( 0xFFFB0000 ); + -( UDP ) Base Address + AT91C_BASE_TC0 EQU( 0xFFFA0000 ); + -( TC0 ) Base Address + AT91C_BASE_TC1 EQU( 0xFFFA0040 ); + -( TC1 ) Base Address + AT91C_BASE_TC2 EQU( 0xFFFA0080 ); + -( TC2 ) Base Address + AT91C_BASE_TCB EQU( 0xFFFA0000 ); + -( TCB ) Base Address + AT91C_BASE_CAN_MB0 EQU( 0xFFFD0200 ); + -( CAN_MB0 ) Base Address + AT91C_BASE_CAN_MB1 EQU( 0xFFFD0220 ); + -( CAN_MB1 ) Base Address + AT91C_BASE_CAN_MB2 EQU( 0xFFFD0240 ); + -( CAN_MB2 ) Base Address + AT91C_BASE_CAN_MB3 EQU( 0xFFFD0260 ); + -( CAN_MB3 ) Base Address + AT91C_BASE_CAN_MB4 EQU( 0xFFFD0280 ); + -( CAN_MB4 ) Base Address + AT91C_BASE_CAN_MB5 EQU( 0xFFFD02A0 ); + -( CAN_MB5 ) Base Address + AT91C_BASE_CAN_MB6 EQU( 0xFFFD02C0 ); + -( CAN_MB6 ) Base Address + AT91C_BASE_CAN_MB7 EQU( 0xFFFD02E0 ); + -( CAN_MB7 ) Base Address + AT91C_BASE_CAN EQU( 0xFFFD0000 ); + -( CAN ) Base Address + AT91C_BASE_EMAC EQU( 0xFFFDC000 ); + -( EMAC ) Base Address + AT91C_BASE_PDC_ADC EQU( 0xFFFD8100 ); + -( PDC_ADC ) Base Address + AT91C_BASE_ADC EQU( 0xFFFD8000 ); + -( ADC ) Base Address + AT91C_BASE_PDC_AES EQU( 0xFFFA4100 ); + -( PDC_AES ) Base Address + AT91C_BASE_AES EQU( 0xFFFA4000 ); + -( AES ) Base Address + AT91C_BASE_PDC_TDES EQU( 0xFFFA8100 ); + -( PDC_TDES ) Base Address + AT91C_BASE_TDES EQU( 0xFFFA8000 ); + -( TDES ) Base Address + +/* - ***************************************************************************** */ +/* - MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 */ +/* - ***************************************************************************** */ + AT91C_ISRAM EQU( 0x00200000 ); + -Internal SRAM base address + AT91C_ISRAM_SIZE EQU( 0x00010000 ); + -Internal SRAM size in byte( 64 Kbyte ) + AT91C_IFLASH EQU( 0x00100000 ); + -Internal ROM base address + AT91C_IFLASH_SIZE EQU( 0x00040000 ); + -Internal ROM size in byte( 256 Kbyte ) + + + +#endif /* AT91SAM7X256_H */ diff --git a/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c b/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c new file mode 100644 index 000000000..269d390cc --- /dev/null +++ b/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c @@ -0,0 +1,50 @@ +/** ---------------------------------------------------------------------------- */ +/** ATMEL Microcontroller Software Support - ROUSSET - */ +/** ---------------------------------------------------------------------------- */ +/** DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/** MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/** DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/** LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/** OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/** LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/** NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/** EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/** ---------------------------------------------------------------------------- */ +/** File Name : lib_AT91SAM7X256.h */ +/** Object : AT91SAM7X256 inlined functions */ +/** Generated : AT91 SW Application Group 05/20/2005 (16:22:29) */ +/** */ +/** CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// */ +/** CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005// */ +/** CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005// */ +/** CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004// */ +/** CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// */ +/** CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004// */ +/** CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// */ +/** CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003// */ +/** CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004// */ +/** CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005// */ +/** CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005// */ +/** CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// */ +/** CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// */ +/** CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004// */ +/** CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005// */ +/** CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005// */ +/** CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// */ +/** CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004// */ +/** CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// */ +/** CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003// */ +/** CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// */ +/** CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002// */ +/** ---------------------------------------------------------------------------- */ + + +#include "AT91SAM7X256.h" + + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_ConfigureIt */ +/** \brief Interrupt Handler Initialization */ +/**---------------------------------------------------------------------------- */ diff --git a/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h b/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h new file mode 100644 index 000000000..5de1aee3b --- /dev/null +++ b/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h @@ -0,0 +1,1396 @@ +/** ---------------------------------------------------------------------------- */ +/** ATMEL Microcontroller Software Support - ROUSSET - */ +/** ---------------------------------------------------------------------------- */ +/** DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/** MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/** DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/** LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/** OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/** LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/** NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/** EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/** ---------------------------------------------------------------------------- */ +/** File Name : lib_AT91SAM7X256.h */ +/** Object : AT91SAM7X256 inlined functions */ +/** Generated : AT91 SW Application Group 05/20/2005 (16:22:29) */ +/** */ +/** CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// */ +/** CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005// */ +/** CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005// */ +/** CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004// */ +/** CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// */ +/** CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004// */ +/** CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// */ +/** CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003// */ +/** CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004// */ +/** CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005// */ +/** CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005// */ +/** CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// */ +/** CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// */ +/** CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004// */ +/** CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005// */ +/** CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005// */ +/** CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// */ +/** CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004// */ +/** CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// */ +/** CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003// */ +/** CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// */ +/** CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002// */ +/** ---------------------------------------------------------------------------- */ + +#ifndef lib_AT91SAM7X256_H + #define lib_AT91SAM7X256_H + +/* ***************************************************************************** +* SOFTWARE API FOR AIC +***************************************************************************** */ + #define AT91C_AIC_BRANCH_OPCODE ( ( void ( * )() ) 0xE51FFF20 ) /* ldr, pc, [pc, #-&F20] */ + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_ConfigureIt */ +/** \brief Interrupt Handler Initialization */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_AIC_ConfigureIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id, /* \arg interrupt number to initialize */ + unsigned int priority, /* \arg priority to give to the interrupt */ + unsigned int src_type, /* \arg activation and sense of activation */ + void ( * newHandler )( void ) ) /* \arg address of the interrupt handler */ + { + unsigned int oldHandler; + unsigned int mask; + + oldHandler = pAic->AIC_SVR[ irq_id ]; + + mask = 0x1 << irq_id; + /** Disable the interrupt on the interrupt controller */ + pAic->AIC_IDCR = mask; + /** Save the interrupt handler routine pointer and the interrupt priority */ + pAic->AIC_SVR[ irq_id ] = ( unsigned int ) newHandler; + /** Store the Source Mode Register */ + pAic->AIC_SMR[ irq_id ] = src_type | priority; + /** Clear the interrupt on the interrupt controller */ + pAic->AIC_ICCR = mask; + + return oldHandler; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_EnableIt */ +/** \brief Enable corresponding IT number */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_AIC_EnableIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg interrupt number to initialize */ + { + /** Enable the interrupt on the interrupt controller */ + pAic->AIC_IECR = 0x1 << irq_id; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_DisableIt */ +/** \brief Disable corresponding IT number */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_AIC_DisableIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg interrupt number to initialize */ + { + unsigned int mask = 0x1 << irq_id; + + /** Disable the interrupt on the interrupt controller */ + pAic->AIC_IDCR = mask; + /** Clear the interrupt on the Interrupt Controller ( if one is pending ) */ + pAic->AIC_ICCR = mask; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_ClearIt */ +/** \brief Clear corresponding IT number */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_AIC_ClearIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg interrupt number to initialize */ + { + /** Clear the interrupt on the Interrupt Controller ( if one is pending ) */ + pAic->AIC_ICCR = ( 0x1 << irq_id ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_AcknowledgeIt */ +/** \brief Acknowledge corresponding IT number */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_AIC_AcknowledgeIt( AT91PS_AIC pAic ) /* \arg pointer to the AIC registers */ + { + pAic->AIC_EOICR = pAic->AIC_EOICR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_SetExceptionVector */ +/** \brief Configure vector handler */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_AIC_SetExceptionVector( unsigned int * pVector, /* \arg pointer to the AIC registers */ + void ( * Handler )() ) /* \arg Interrupt Handler */ + { + unsigned int oldVector = *pVector; + + if( ( unsigned int ) Handler == ( unsigned int ) AT91C_AIC_BRANCH_OPCODE ) + { + *pVector = ( unsigned int ) AT91C_AIC_BRANCH_OPCODE; + } + else + { + *pVector = ( ( ( ( ( unsigned int ) Handler ) - ( ( unsigned int ) pVector ) - 0x8 ) >> 2 ) & 0x00FFFFFF ) | 0xEA000000; + } + + return oldVector; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_Trig */ +/** \brief Trig an IT */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_AIC_Trig( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg interrupt number */ + { + pAic->AIC_ISCR = ( 0x1 << irq_id ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_IsActive */ +/** \brief Test if an IT is active */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_AIC_IsActive( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg Interrupt Number */ + { + return( pAic->AIC_ISR & ( 0x1 << irq_id ) ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_IsPending */ +/** \brief Test if an IT is pending */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_AIC_IsPending( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg Interrupt Number */ + { + return( pAic->AIC_IPR & ( 0x1 << irq_id ) ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_Open */ +/** \brief Set exception vectors and AIC registers to default values */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_AIC_Open( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + void ( * IrqHandler )(), /* \arg Default IRQ vector exception */ + void ( * FiqHandler )(), /* \arg Default FIQ vector exception */ + void ( * DefaultHandler )(), /* \arg Default Handler set in ISR */ + void ( * SpuriousHandler )(), /* \arg Default Spurious Handler */ + unsigned int protectMode ) /* \arg Debug Control Register */ + { + int i; + + /* Disable all interrupts and set IVR to the default handler */ + for( i = 0; i < 32; ++i ) + { + AT91F_AIC_DisableIt( pAic, i ); + AT91F_AIC_ConfigureIt( pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler ); + } + + /* Set the IRQ exception vector */ + AT91F_AIC_SetExceptionVector( ( unsigned int * ) 0x18, IrqHandler ); + /* Set the Fast Interrupt exception vector */ + AT91F_AIC_SetExceptionVector( ( unsigned int * ) 0x1C, FiqHandler ); + + pAic->AIC_SPU = ( unsigned int ) SpuriousHandler; + pAic->AIC_DCR = protectMode; + } + +/* ***************************************************************************** +* SOFTWARE API FOR PDC +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_SetNextRx */ +/** \brief Set the next receive transfer descriptor */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_SetNextRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ + char * address, /* \arg address to the next block to be received */ + unsigned int bytes ) /* \arg number of bytes to be received */ + { + pPDC->PDC_RNPR = ( unsigned int ) address; + pPDC->PDC_RNCR = bytes; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_SetNextTx */ +/** \brief Set the next transmit transfer descriptor */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_SetNextTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ + char * address, /* \arg address to the next block to be transmitted */ + unsigned int bytes ) /* \arg number of bytes to be transmitted */ + { + pPDC->PDC_TNPR = ( unsigned int ) address; + pPDC->PDC_TNCR = bytes; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_SetRx */ +/** \brief Set the receive transfer descriptor */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_SetRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ + char * address, /* \arg address to the next block to be received */ + unsigned int bytes ) /* \arg number of bytes to be received */ + { + pPDC->PDC_RPR = ( unsigned int ) address; + pPDC->PDC_RCR = bytes; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_SetTx */ +/** \brief Set the transmit transfer descriptor */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_SetTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ + char * address, /* \arg address to the next block to be transmitted */ + unsigned int bytes ) /* \arg number of bytes to be transmitted */ + { + pPDC->PDC_TPR = ( unsigned int ) address; + pPDC->PDC_TCR = bytes; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_EnableTx */ +/** \brief Enable transmit */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_EnableTx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + pPDC->PDC_PTCR = AT91C_PDC_TXTEN; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_EnableRx */ +/** \brief Enable receive */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_EnableRx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + pPDC->PDC_PTCR = AT91C_PDC_RXTEN; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_DisableTx */ +/** \brief Disable transmit */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_DisableTx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_DisableRx */ +/** \brief Disable receive */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_DisableRx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_IsTxEmpty */ +/** \brief Test if the current transfer descriptor has been sent */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PDC_IsTxEmpty( /* \return return 1 if transfer is complete */ + AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + return !( pPDC->PDC_TCR ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_IsNextTxEmpty */ +/** \brief Test if the next transfer descriptor has been moved to the current td */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PDC_IsNextTxEmpty( /* \return return 1 if transfer is complete */ + AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + return !( pPDC->PDC_TNCR ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_IsRxEmpty */ +/** \brief Test if the current transfer descriptor has been filled */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PDC_IsRxEmpty( /* \return return 1 if transfer is complete */ + AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + return !( pPDC->PDC_RCR ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_IsNextRxEmpty */ +/** \brief Test if the next transfer descriptor has been moved to the current td */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PDC_IsNextRxEmpty( /* \return return 1 if transfer is complete */ + AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + return !( pPDC->PDC_RNCR ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_Open */ +/** \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_Open( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + /** Disable the RX and TX PDC transfer requests */ + AT91F_PDC_DisableRx( pPDC ); + AT91F_PDC_DisableTx( pPDC ); + + /** Reset all Counter register Next buffer first */ + AT91F_PDC_SetNextTx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetNextRx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetTx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetRx( pPDC, ( char * ) 0, 0 ); + + /** Enable the RX and TX PDC transfer requests */ + AT91F_PDC_EnableRx( pPDC ); + AT91F_PDC_EnableTx( pPDC ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_Close */ +/** \brief Close PDC: disable TX and RX reset transfer descriptors */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_Close( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + /** Disable the RX and TX PDC transfer requests */ + AT91F_PDC_DisableRx( pPDC ); + AT91F_PDC_DisableTx( pPDC ); + + /** Reset all Counter register Next buffer first */ + AT91F_PDC_SetNextTx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetNextRx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetTx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetRx( pPDC, ( char * ) 0, 0 ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_SendFrame */ +/** \brief Close PDC: disable TX and RX reset transfer descriptors */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PDC_SendFrame( AT91PS_PDC pPDC, + char * pBuffer, + unsigned int szBuffer, + char * pNextBuffer, + unsigned int szNextBuffer ) + { + if( AT91F_PDC_IsTxEmpty( pPDC ) ) + { + /** Buffer and next buffer can be initialized */ + AT91F_PDC_SetTx( pPDC, pBuffer, szBuffer ); + AT91F_PDC_SetNextTx( pPDC, pNextBuffer, szNextBuffer ); + return 2; + } + else if( AT91F_PDC_IsNextTxEmpty( pPDC ) ) + { + /** Only one buffer can be initialized */ + AT91F_PDC_SetNextTx( pPDC, pBuffer, szBuffer ); + return 1; + } + else + { + /** All buffer are in use... */ + return 0; + } + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_ReceiveFrame */ +/** \brief Close PDC: disable TX and RX reset transfer descriptors */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PDC_ReceiveFrame( AT91PS_PDC pPDC, + char * pBuffer, + unsigned int szBuffer, + char * pNextBuffer, + unsigned int szNextBuffer ) + { + if( AT91F_PDC_IsRxEmpty( pPDC ) ) + { + /** Buffer and next buffer can be initialized */ + AT91F_PDC_SetRx( pPDC, pBuffer, szBuffer ); + AT91F_PDC_SetNextRx( pPDC, pNextBuffer, szNextBuffer ); + return 2; + } + else if( AT91F_PDC_IsNextRxEmpty( pPDC ) ) + { + /** Only one buffer can be initialized */ + AT91F_PDC_SetNextRx( pPDC, pBuffer, szBuffer ); + return 1; + } + else + { + /** All buffer are in use... */ + return 0; + } + } + +/* ***************************************************************************** +* SOFTWARE API FOR DBGU +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_DBGU_InterruptEnable */ +/** \brief Enable DBGU Interrupt */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_DBGU_InterruptEnable( AT91PS_DBGU pDbgu, /* \arg pointer to a DBGU controller */ + unsigned int flag ) /* \arg dbgu interrupt to be enabled */ + { + pDbgu->DBGU_IER = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_DBGU_InterruptDisable */ +/** \brief Disable DBGU Interrupt */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_DBGU_InterruptDisable( AT91PS_DBGU pDbgu, /* \arg pointer to a DBGU controller */ + unsigned int flag ) /* \arg dbgu interrupt to be disabled */ + { + pDbgu->DBGU_IDR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_DBGU_GetInterruptMaskStatus */ +/** \brief Return DBGU Interrupt Mask Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( /* \return DBGU Interrupt Mask Status */ + AT91PS_DBGU pDbgu ) /* \arg pointer to a DBGU controller */ + { + return pDbgu->DBGU_IMR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_DBGU_IsInterruptMasked */ +/** \brief Test if DBGU Interrupt is Masked */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_DBGU_IsInterruptMasked( AT91PS_DBGU pDbgu, /* \arg pointer to a DBGU controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_DBGU_GetInterruptMaskStatus( pDbgu ) & flag ); + } + +/* ***************************************************************************** +* SOFTWARE API FOR PIO +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgPeriph */ +/** \brief Enable pins to be derived by peripheral */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_CfgPeriph( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int periphAEnable, /* \arg PERIPH A to enable */ + unsigned int periphBEnable ) /* \arg PERIPH B to enable */ + + { + pPio->PIO_ASR = periphAEnable; + pPio->PIO_BSR = periphBEnable; + pPio->PIO_PDR = ( periphAEnable | periphBEnable ); /* Set in Periph mode */ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgOutput */ +/** \brief Enable PIO in output mode */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_CfgOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int pioEnable ) /* \arg PIO to be enabled */ + { + pPio->PIO_PER = pioEnable; /* Set in PIO mode */ + pPio->PIO_OER = pioEnable; /* Configure in Output */ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgInput */ +/** \brief Enable PIO in input mode */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_CfgInput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int inputEnable ) /* \arg PIO to be enabled */ + { + /* Disable output */ + pPio->PIO_ODR = inputEnable; + pPio->PIO_PER = inputEnable; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgOpendrain */ +/** \brief Configure PIO in open drain */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_CfgOpendrain( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int multiDrvEnable ) /* \arg pio to be configured in open drain */ + { + /* Configure the multi-drive option */ + pPio->PIO_MDDR = ~multiDrvEnable; + pPio->PIO_MDER = multiDrvEnable; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgPullup */ +/** \brief Enable pullup on PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_CfgPullup( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int pullupEnable ) /* \arg enable pullup on PIO */ + { + /* Connect or not Pullup */ + pPio->PIO_PPUDR = ~pullupEnable; + pPio->PIO_PPUER = pullupEnable; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgDirectDrive */ +/** \brief Enable direct drive on PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_CfgDirectDrive( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int directDrive ) /* \arg PIO to be configured with direct drive */ + + { + /* Configure the Direct Drive */ + pPio->PIO_OWDR = ~directDrive; + pPio->PIO_OWER = directDrive; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgInputFilter */ +/** \brief Enable input filter on input PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_CfgInputFilter( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int inputFilter ) /* \arg PIO to be configured with input filter */ + + { + /* Configure the Direct Drive */ + pPio->PIO_IFDR = ~inputFilter; + pPio->PIO_IFER = inputFilter; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetInput */ +/** \brief Return PIO input value */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetInput( /* \return PIO input */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { + return pPio->PIO_PDSR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsInputSet */ +/** \brief Test if PIO is input flag is active */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsInputSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetInput( pPio ) & flag ); + } + + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_SetOutput */ +/** \brief Set to 1 output PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_SetOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg output to be set */ + { + pPio->PIO_SODR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_ClearOutput */ +/** \brief Set to 0 output PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_ClearOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg output to be cleared */ + { + pPio->PIO_CODR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_ForceOutput */ +/** \brief Force output when Direct drive option is enabled */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_ForceOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg output to be forced */ + { + pPio->PIO_ODSR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_Enable */ +/** \brief Enable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_Enable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio to be enabled */ + { + pPio->PIO_PER = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_Disable */ +/** \brief Disable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_Disable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio to be disabled */ + { + pPio->PIO_PDR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetStatus */ +/** \brief Return PIO Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetStatus( /* \return PIO Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { + return pPio->PIO_PSR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsSet */ +/** \brief Test if PIO is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_OutputEnable */ +/** \brief Output Enable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_OutputEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio output to be enabled */ + { + pPio->PIO_OER = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_OutputDisable */ +/** \brief Output Enable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_OutputDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio output to be disabled */ + { + pPio->PIO_ODR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetOutputStatus */ +/** \brief Return PIO Output Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetOutputStatus( /* \return PIO Output Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { + return pPio->PIO_OSR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsOuputSet */ +/** \brief Test if PIO Output is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsOutputSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetOutputStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_InputFilterEnable */ +/** \brief Input Filter Enable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_InputFilterEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio input filter to be enabled */ + { + pPio->PIO_IFER = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_InputFilterDisable */ +/** \brief Input Filter Disable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_InputFilterDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio input filter to be disabled */ + { + pPio->PIO_IFDR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetInputFilterStatus */ +/** \brief Return PIO Input Filter Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetInputFilterStatus( /* \return PIO Input Filter Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { + return pPio->PIO_IFSR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsInputFilterSet */ +/** \brief Test if PIO Input filter is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsInputFilterSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetInputFilterStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetOutputDataStatus */ +/** \brief Return PIO Output Data Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetOutputDataStatus( /* \return PIO Output Data Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { + return pPio->PIO_ODSR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_InterruptEnable */ +/** \brief Enable PIO Interrupt */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_InterruptEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio interrupt to be enabled */ + { + pPio->PIO_IER = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_InterruptDisable */ +/** \brief Disable PIO Interrupt */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_InterruptDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio interrupt to be disabled */ + { + pPio->PIO_IDR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetInterruptMaskStatus */ +/** \brief Return PIO Interrupt Mask Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetInterruptMaskStatus( /* \return PIO Interrupt Mask Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { + return pPio->PIO_IMR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetInterruptStatus */ +/** \brief Return PIO Interrupt Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetInterruptStatus( /* \return PIO Interrupt Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { + return pPio->PIO_ISR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsInterruptMasked */ +/** \brief Test if PIO Interrupt is Masked */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsInterruptMasked( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetInterruptMaskStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsInterruptSet */ +/** \brief Test if PIO Interrupt is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsInterruptSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetInterruptStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_MultiDriverEnable */ +/** \brief Multi Driver Enable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_MultiDriverEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio to be enabled */ + { + pPio->PIO_MDER = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_MultiDriverDisable */ +/** \brief Multi Driver Disable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_MultiDriverDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio to be disabled */ + { + pPio->PIO_MDDR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetMultiDriverStatus */ +/** \brief Return PIO Multi Driver Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetMultiDriverStatus( /* \return PIO Multi Driver Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { + return pPio->PIO_MDSR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsMultiDriverSet */ +/** \brief Test if PIO MultiDriver is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsMultiDriverSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetMultiDriverStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_A_RegisterSelection */ +/** \brief PIO A Register Selection */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_A_RegisterSelection( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio A register selection */ + { + pPio->PIO_ASR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_B_RegisterSelection */ +/** \brief PIO B Register Selection */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_B_RegisterSelection( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio B register selection */ + { + pPio->PIO_BSR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_Get_AB_RegisterStatus */ +/** \brief Return PIO Interrupt Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( /* \return PIO AB Register Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { + return pPio->PIO_ABSR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsAB_RegisterSet */ +/** \brief Test if PIO AB Register is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsAB_RegisterSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_Get_AB_RegisterStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_OutputWriteEnable */ +/** \brief Output Write Enable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_OutputWriteEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio output write to be enabled */ + { + pPio->PIO_OWER = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_OutputWriteDisable */ +/** \brief Output Write Disable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_OutputWriteDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio output write to be disabled */ + { + pPio->PIO_OWDR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetOutputWriteStatus */ +/** \brief Return PIO Output Write Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetOutputWriteStatus( /* \return PIO Output Write Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { + return pPio->PIO_OWSR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsOutputWriteSet */ +/** \brief Test if PIO OutputWrite is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsOutputWriteSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetOutputWriteStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetCfgPullup */ +/** \brief Return PIO Configuration Pullup */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetCfgPullup( /* \return PIO Configuration Pullup */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { + return pPio->PIO_PPUSR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsOutputDataStatusSet */ +/** \brief Test if PIO Output Data Status is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsOutputDataStatusSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetOutputDataStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsCfgPullupStatusSet */ +/** \brief Test if PIO Configuration Pullup Status is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsCfgPullupStatusSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( ~AT91F_PIO_GetCfgPullup( pPio ) & flag ); + } + +/* ***************************************************************************** +* SOFTWARE API FOR PMC +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_CfgSysClkEnableReg */ +/** \brief Configure the System Clock Enable Register of the PMC controller */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_CfgSysClkEnableReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int mode ) + { + /** Write to the SCER register */ + pPMC->PMC_SCER = mode; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_CfgSysClkDisableReg */ +/** \brief Configure the System Clock Disable Register of the PMC controller */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_CfgSysClkDisableReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int mode ) + { + /** Write to the SCDR register */ + pPMC->PMC_SCDR = mode; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_GetSysClkStatusReg */ +/** \brief Return the System Clock Status Register of the PMC controller */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PMC_GetSysClkStatusReg( AT91PS_PMC pPMC /* pointer to a CAN controller */ + ) + { + return pPMC->PMC_SCSR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_EnablePeriphClock */ +/** \brief Enable peripheral clock */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_EnablePeriphClock( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int periphIds ) /* \arg IDs of peripherals to enable */ + { + pPMC->PMC_PCER = periphIds; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_DisablePeriphClock */ +/** \brief Disable peripheral clock */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_DisablePeriphClock( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int periphIds ) /* \arg IDs of peripherals to enable */ + { + pPMC->PMC_PCDR = periphIds; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_GetPeriphClock */ +/** \brief Get peripheral clock status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PMC_GetPeriphClock( AT91PS_PMC pPMC ) /* \arg pointer to PMC controller */ + { + return pPMC->PMC_PCSR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_CfgMainOscillatorReg */ +/** \brief Cfg the main oscillator */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_CKGR_CfgMainOscillatorReg( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */ + unsigned int mode ) + { + pCKGR->CKGR_MOR = mode; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_GetMainOscillatorReg */ +/** \brief Cfg the main oscillator */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_CKGR_GetMainOscillatorReg( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */ + { + return pCKGR->CKGR_MOR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_EnableMainOscillator */ +/** \brief Enable the main oscillator */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_CKGR_EnableMainOscillator( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */ + { + pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_DisableMainOscillator */ +/** \brief Disable the main oscillator */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_CKGR_DisableMainOscillator( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */ + { + pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_CfgMainOscStartUpTime */ +/** \brief Cfg MOR Register according to the main osc startup time */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_CKGR_CfgMainOscStartUpTime( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */ + unsigned int startup_time, /* \arg main osc startup time in microsecond (us) */ + unsigned int slowClock ) /* \arg slowClock in Hz */ + { + pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT; + pCKGR->CKGR_MOR |= ( ( slowClock * startup_time ) / ( 8 * 1000000 ) ) << 8; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_GetMainClockFreqReg */ +/** \brief Cfg the main oscillator */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_CKGR_GetMainClockFreqReg( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */ + { + return pCKGR->CKGR_MCFR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_GetMainClock */ +/** \brief Return Main clock in Hz */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_CKGR_GetMainClock( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */ + unsigned int slowClock ) /* \arg slowClock in Hz */ + { + return ( ( pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF ) * slowClock ) >> 4; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_CfgMCKReg */ +/** \brief Cfg Master Clock Register */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_CfgMCKReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int mode ) + { + pPMC->PMC_MCKR = mode; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_GetMCKReg */ +/** \brief Return Master Clock Register */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PMC_GetMCKReg( AT91PS_PMC pPMC ) /* \arg pointer to PMC controller */ + { + return pPMC->PMC_MCKR; + } + +/**------------------------------------------------------------------------------ */ +/** \fn AT91F_PMC_GetMasterClock */ +/** \brief Return master clock in Hz which corresponds to processor clock for ARM7 */ +/**------------------------------------------------------------------------------ */ + __inline unsigned int AT91F_PMC_GetMasterClock( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */ + unsigned int slowClock ) /* \arg slowClock in Hz */ + { + unsigned int reg = pPMC->PMC_MCKR; + unsigned int prescaler = ( 1 << ( ( reg & AT91C_PMC_PRES ) >> 2 ) ); + unsigned int pllDivider, pllMultiplier; + + switch( reg & AT91C_PMC_CSS ) + { + case AT91C_PMC_CSS_SLOW_CLK: /* Slow clock selected */ + return slowClock / prescaler; + + case AT91C_PMC_CSS_MAIN_CLK: /* Main clock is selected */ + return AT91F_CKGR_GetMainClock( pCKGR, slowClock ) / prescaler; + + case AT91C_PMC_CSS_PLL_CLK: /* PLLB clock is selected */ + reg = pCKGR->CKGR_PLLR; + pllDivider = ( reg & AT91C_CKGR_DIV ); + pllMultiplier = ( ( reg & AT91C_CKGR_MUL ) >> 16 ) + 1; + return AT91F_CKGR_GetMainClock( pCKGR, slowClock ) / pllDivider * pllMultiplier / prescaler; + } + + return 0; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_EnablePCK */ +/** \brief Enable peripheral clock */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_EnablePCK( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int pck, /* \arg Peripheral clock identifier 0 .. 7 */ + unsigned int mode ) + { + pPMC->PMC_PCKR[ pck ] = mode; + pPMC->PMC_SCER = ( 1 << pck ) << 8; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_DisablePCK */ +/** \brief Enable peripheral clock */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_DisablePCK( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int pck ) /* \arg Peripheral clock identifier 0 .. 7 */ + { + pPMC->PMC_SCDR = ( 1 << pck ) << 8; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_EnableIt */ +/** \brief Enable PMC interrupt */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_EnableIt( AT91PS_PMC pPMC, /* pointer to a PMC controller */ + unsigned int flag ) /* IT to be enabled */ + { + /** Write to the IER register */ + pPMC->PMC_IER = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_DisableIt */ +/** \brief Disable PMC interrupt */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_DisableIt( AT91PS_PMC pPMC, /* pointer to a PMC controller */ + unsigned int flag ) /* IT to be disabled */ + { + /** Write to the IDR register */ + pPMC->PMC_IDR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_GetStatus */ +/** \brief Return PMC Interrupt Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PMC_GetStatus( /* \return PMC Interrupt Status */ + AT91PS_PMC pPMC ) /* pointer to a PMC controller */ + { + return pPMC->PMC_SR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_GetInterruptMaskStatus */ +/** \brief Return PMC Interrupt Mask Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PMC_GetInterruptMaskStatus( /* \return PMC Interrupt Mask Status */ + AT91PS_PMC pPMC ) /* pointer to a PMC controller */ + { + return pPMC->PMC_IMR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_IsInterruptMasked */ +/** \brief Test if PMC Interrupt is Masked */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PMC_IsInterruptMasked( AT91PS_PMC pPMC, /* \arg pointer to a PMC controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PMC_GetInterruptMaskStatus( pPMC ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_IsStatusSet */ +/** \brief Test if PMC Status is Set */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PMC_IsStatusSet( AT91PS_PMC pPMC, /* \arg pointer to a PMC controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PMC_GetStatus( pPMC ) & flag ); + } /* ***************************************************************************** + * SOFTWARE API FOR RSTC + ***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_RSTSoftReset */ +/** \brief Start Software Reset */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_RSTSoftReset( AT91PS_RSTC pRSTC, + unsigned int reset ) + { + pRSTC->RSTC_RCR = ( 0xA5000000 | reset ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_RSTSetMode */ +/** \brief Set Reset Mode */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_RSTSetMode( AT91PS_RSTC pRSTC, + unsigned int mode ) + { + pRSTC->RSTC_RMR = ( 0xA5000000 | mode ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_RSTGetMode */ +/** \brief Get Reset Mode */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RSTGetMode( AT91PS_RSTC pRSTC ) + { + return( pRSTC->RSTC_RMR ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_RSTGetStatus */ +/** \brief Get Reset Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RSTGetStatus( AT91PS_RSTC pRSTC ) + { + return( pRSTC->RSTC_RSR ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_RSTIsSoftRstActive */ +/** \brief Return !=0 if software reset is still not completed */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RSTIsSoftRstActive( AT91PS_RSTC pRSTC ) + { + return( ( pRSTC->RSTC_RSR ) & AT91C_RSTC_SRCMP ); + } + +/* ***************************************************************************** +* SOFTWARE API FOR RTTC +***************************************************************************** */ +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_SetRTT_TimeBase() */ +/** \brief Set the RTT prescaler according to the TimeBase in ms */ +/**-------------------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RTTSetTimeBase( AT91PS_RTTC pRTTC, + unsigned int ms ) + { + if( ms > 2000 ) + { + return 1; /* AT91C_TIME_OUT_OF_RANGE */ + } + + pRTTC->RTTC_RTMR &= ~0xFFFF; + pRTTC->RTTC_RTMR |= ( ( ( ms << 15 ) / 1000 ) & 0xFFFF ); + return 0; + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTTSetPrescaler() */ +/** \brief Set the new prescaler value */ +/**-------------------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RTTSetPrescaler( AT91PS_RTTC pRTTC, + unsigned int rtpres ) + { + pRTTC->RTTC_RTMR &= ~0xFFFF; + pRTTC->RTTC_RTMR |= ( rtpres & 0xFFFF ); + return( pRTTC->RTTC_RTMR ); + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTTRestart() */ +/** \brief Restart the RTT prescaler */ +/**-------------------------------------------------------------------------------------- */ + __inline void AT91F_RTTRestart( AT91PS_RTTC pRTTC ) + { + pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST; + } + + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTT_SetAlarmINT() */ +/** \brief Enable RTT Alarm Interrupt */ +/**-------------------------------------------------------------------------------------- */ + __inline void AT91F_RTTSetAlarmINT( AT91PS_RTTC pRTTC ) + { + pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN; + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTT_ClearAlarmINT() */ +/** \brief Disable RTT Alarm Interrupt */ +/**-------------------------------------------------------------------------------------- */ + __inline void AT91F_RTTClearAlarmINT( AT91PS_RTTC pRTTC ) + { + pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN; + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTT_SetRttIncINT() */ +/** \brief Enable RTT INC Interrupt */ +/**-------------------------------------------------------------------------------------- */ + __inline void AT91F_RTTSetRttIncINT( AT91PS_RTTC pRTTC ) + { + pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN; + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTT_ClearRttIncINT() */ +/** \brief Disable RTT INC Interrupt */ +/**-------------------------------------------------------------------------------------- */ + __inline void AT91F_RTTClearRttIncINT( AT91PS_RTTC pRTTC ) + { + pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN; + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTT_SetAlarmValue() */ +/** \brief Set RTT Alarm Value */ +/**-------------------------------------------------------------------------------------- */ + __inline void AT91F_RTTSetAlarmValue( AT91PS_RTTC pRTTC, + unsigned int alarm ) + { + pRTTC->RTTC_RTAR = alarm; + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTT_GetAlarmValue() */ +/** \brief Get RTT Alarm Value */ +/**-------------------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RTTGetAlarmValue( AT91PS_RTTC pRTTC ) + { + return( pRTTC->RTTC_RTAR ); + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTTGetStatus() */ +/** \brief Read the RTT status */ +/**-------------------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RTTGetStatus( AT91PS_RTTC pRTTC ) + { + return( pRTTC->RTTC_RTSR ); + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTT_ReadValue() */ +/** \brief Read the RTT value */ +/**-------------------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RTTReadValue( AT91PS_RTTC pRTTC ) + { + register volatile unsigned int val1, val2; + + do + { + val1 = pRTTC->RTTC_RTVR; + val2 = pRTTC->RTTC_RTVR; + } + while( val1 != val2 ); + + return( val1 ); + } + +/* ***************************************************************************** +* SOFTWARE API FOR PITC +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PITInit */ +/** \brief System timer init : period in */ diff --git a/portable/GCC/ARM7_AT91SAM7S/port.c b/portable/GCC/ARM7_AT91SAM7S/port.c new file mode 100644 index 000000000..6750c45ee --- /dev/null +++ b/portable/GCC/ARM7_AT91SAM7S/port.c @@ -0,0 +1,209 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ARM7 port. +* +* Components that can be compiled to either ARM or THUMB mode are +* contained in this file. The ISR routines, which can only be compiled +* to ARM mode are contained in portISR.c. +*----------------------------------------------------------*/ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Processor constants. */ +#include "AT91SAM7X256.h" + +/* Constants required to setup the task context. */ +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) +#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 ) + +/* Constants required to setup the tick ISR. */ +#define portENABLE_TIMER ( ( uint8_t ) 0x01 ) +#define portPRESCALE_VALUE 0x00 +#define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 ) +#define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 ) + +/* Constants required to setup the PIT. */ +#define portPIT_CLOCK_DIVISOR ( ( uint32_t ) 16 ) +#define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_PERIOD_MS ) + +#define portINT_LEVEL_SENSITIVE 0 +#define portPIT_ENABLE ( ( uint16_t ) 0x1 << 24 ) +#define portPIT_INT_ENABLE ( ( uint16_t ) 0x1 << 25 ) +/*-----------------------------------------------------------*/ + +/* Setup the timer to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* + * The scheduler can only be started from ARM mode, so + * vPortISRStartFirstSTask() is defined in portISR.c. + */ +extern void vPortISRStartFirstTask( void ); + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + StackType_t * pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + /* To ensure asserts in tasks.c don't fail, although in this case the assert + * is not really required. */ + pxTopOfStack--; + + /* Setup the initial stack of the task. The stack is set exactly as + * expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which in this case is the + * start of the task. The offset is added to make the return address appear + * as it would within an IRQ ISR. */ + *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0x00000000; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + * R0. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The last thing onto the stack is the status register, which is set for + * system mode, with interrupts enabled. */ + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + + #ifdef THUMB_INTERWORK + { + /* We want the task to start in thumb mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + #endif + + pxTopOfStack--; + + /* Some optimisation levels use the stack differently to others. This + * means the interrupt flags cannot always be stored on the stack and will + * instead be stored in a variable, which is then saved as part of the + * tasks context. */ + *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortISRStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + * is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +/* + * Setup the timer 0 to generate the tick interrupts at the required frequency. + */ +static void prvSetupTimerInterrupt( void ) +{ + AT91PS_PITC pxPIT = AT91C_BASE_PITC; + + /* Setup the AIC for PIT interrupts. The interrupt routine chosen depends + * on whether the preemptive or cooperative scheduler is being used. */ + #if configUSE_PREEMPTION == 0 + extern void( vNonPreemptiveTick ) ( void ); + AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void ( * )( void ) )vNonPreemptiveTick ); + #else + extern void( vPreemptiveTick )( void ); + AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void ( * )( void ) )vPreemptiveTick ); + #endif + + /* Configure the PIT period. */ + pxPIT->PITC_PIMR = portPIT_ENABLE | portPIT_INT_ENABLE | portPIT_COUNTER_VALUE; + + /* Enable the interrupt. Global interrupts are disabled at this point so + * this is safe. */ + AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_SYS; +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM7_AT91SAM7S/portISR.c b/portable/GCC/ARM7_AT91SAM7S/portISR.c new file mode 100644 index 000000000..9e5ff6c98 --- /dev/null +++ b/portable/GCC/ARM7_AT91SAM7S/portISR.c @@ -0,0 +1,227 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/*----------------------------------------------------------- +* Components that can be compiled to either ARM or THUMB mode are +* contained in port.c The ISR routines, which can only be compiled +* to ARM mode, are contained in this file. +*----------------------------------------------------------*/ + +/* + * Changes from V3.2.4 + * + + The assembler statements are now included in a single asm block rather + + than each line having its own asm block. + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#include "AT91SAM7X256.h" + +/* Constants required to handle interrupts. */ +#define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 ) +#define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 ) + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) +volatile uint32_t ulCriticalNesting = 9999UL; + +/*-----------------------------------------------------------*/ + +/* ISR to handle manual context switches (from a call to taskYIELD()). */ +void vPortYieldProcessor( void ) __attribute__( ( interrupt( "SWI" ), naked ) ); + +/* + * The scheduler can only be started from ARM mode, hence the inclusion of this + * function here. + */ +void vPortISRStartFirstTask( void ); +/*-----------------------------------------------------------*/ + +void vPortISRStartFirstTask( void ) +{ + /* Simply start the scheduler. This is included here as it can only be + * called from ARM mode. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * Called by portYIELD() or taskYIELD() to manually force a context switch. + * + * When a context switch is performed from the task level the saved task + * context is made to look as if it occurred from within the tick ISR. This + * way the same restore context function can be used when restoring the context + * saved from the ISR or that saved from a call to vPortYieldProcessor. + */ +void vPortYieldProcessor( void ) +{ + /* Within an IRQ ISR the link register has an offset from the true return + * address, but an SWI ISR does not. Add the offset manually so the same + * ISR return code can be used in both cases. */ + __asm volatile ( "ADD LR, LR, #4" ); + + /* Perform the context switch. First save the context of the current task. */ + portSAVE_CONTEXT(); + + /* Find the highest priority task that is ready to run. */ + vTaskSwitchContext(); + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * The ISR used for the scheduler tick depends on whether the cooperative or + * the preemptive scheduler is being used. + */ + +#if configUSE_PREEMPTION == 0 + +/* The cooperative scheduler requires a normal IRQ service routine to + * simply increment the system tick. */ + void vNonPreemptiveTick( void ) __attribute__( ( interrupt( "IRQ" ) ) ); + void vNonPreemptiveTick( void ) + { + uint32_t ulDummy; + + /* Increment the tick count - which may wake some tasks but as the + * preemptive scheduler is not being used any woken task is not given + * processor time no matter what its priority. */ + xTaskIncrementTick(); + + /* Clear the PIT interrupt. */ + ulDummy = AT91C_BASE_PITC->PITC_PIVR; + + /* End the interrupt in the AIC. */ + AT91C_BASE_AIC->AIC_EOICR = ulDummy; + } + +#else /* if configUSE_PREEMPTION == 0 */ + +/* The preemptive scheduler is defined as "naked" as the full context is + * saved on entry as part of the context switch. */ + void vPreemptiveTick( void ) __attribute__( ( naked ) ); + void vPreemptiveTick( void ) + { + /* Save the context of the current task. */ + portSAVE_CONTEXT(); + + /* Increment the tick count - this may wake a task. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Find the highest priority task that is ready to run. */ + vTaskSwitchContext(); + } + + /* End the interrupt in the AIC. */ + AT91C_BASE_AIC->AIC_EOICR = AT91C_BASE_PITC->PITC_PIVR; + + portRESTORE_CONTEXT(); + } + +#endif /* if configUSE_PREEMPTION == 0 */ +/*-----------------------------------------------------------*/ + +/* + * The interrupt management utilities can only be called from ARM mode. When + * THUMB_INTERWORK is defined the utilities are defined as functions here to + * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then + * the utilities are defined as macros in portmacro.h - as per other ports. + */ +void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) ); +void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) ); + +void vPortDisableInterruptsFromThumb( void ) +{ + __asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ +} + +void vPortEnableInterruptsFromThumb( void ) +{ + __asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ +} + + +/* The code generated by the GCC compiler uses the stack in different ways at + * different optimisation levels. The interrupt flags can therefore not always + * be saved to the stack. Instead the critical section nesting level is stored + * in a variable, which is then saved as part of the stack context. */ +void vPortEnterCritical( void ) +{ + /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ + __asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ + + /* Now that interrupts are disabled, ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + * re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Enable interrupts as per portEXIT_CRITICAL(). */ + __asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ + } + } +} diff --git a/portable/GCC/ARM7_AT91SAM7S/portmacro.h b/portable/GCC/ARM7_AT91SAM7S/portmacro.h new file mode 100644 index 000000000..3f2242fa9 --- /dev/null +++ b/portable/GCC/ARM7_AT91SAM7S/portmacro.h @@ -0,0 +1,255 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * Changes from V3.2.3 + * + + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1. + + + + Changes from V3.2.4 + + + + Removed the use of the %0 parameter within the assembler macros and + + replaced them with hard coded registers. This will ensure the + + assembler does not select the link register as the temp register as + + was occasionally happening previously. + + + + The assembler statements are now included in a single asm block rather + + than each line having its own asm block. + + + + Changes from V4.5.0 + + + + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros + + and replaced them with portYIELD_FROM_ISR() macro. Application code + + should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT() + + macros as per the V4.5.1 demo code. + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE portLONG + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() __asm volatile ( "NOP" ); +/*-----------------------------------------------------------*/ + + +/* Scheduler utilities. */ + +/* + * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR + * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but + * are included here for efficiency. An attempt to call one from + * THUMB mode code will result in a compile time error. + */ + +#define portRESTORE_CONTEXT() \ + { \ + extern volatile void * volatile pxCurrentTCB; \ + extern volatile uint32_t ulCriticalNesting; \ + \ + /* Set the LR to the task stack. */ \ + __asm volatile ( \ + "LDR R0, =pxCurrentTCB \n\t" \ + "LDR R0, [R0] \n\t" \ + "LDR LR, [R0] \n\t" \ + \ + /* The critical nesting depth is the first item on the stack. */ \ + /* Load it into the ulCriticalNesting variable. */ \ + "LDR R0, =ulCriticalNesting \n\t" \ + "LDMFD LR!, {R1} \n\t" \ + "STR R1, [R0] \n\t" \ + \ + /* Get the SPSR from the stack. */ \ + "LDMFD LR!, {R0} \n\t" \ + "MSR SPSR, R0 \n\t" \ + \ + /* Restore all system mode registers for the task. */ \ + "LDMFD LR, {R0-R14}^ \n\t" \ + "NOP \n\t" \ + \ + /* Restore the return address. */ \ + "LDR LR, [LR, #+60] \n\t" \ + \ + /* And return - correcting the offset in the LR to obtain the */ \ + /* correct address. */ \ + "SUBS PC, LR, #4 \n\t" \ + ); \ + ( void ) ulCriticalNesting; \ + ( void ) pxCurrentTCB; \ + } +/*-----------------------------------------------------------*/ + +#define portSAVE_CONTEXT() \ + { \ + extern volatile void * volatile pxCurrentTCB; \ + extern volatile uint32_t ulCriticalNesting; \ + \ + /* Push R0 as we are going to use the register. */ \ + __asm volatile ( \ + "STMDB SP!, {R0} \n\t" \ + \ + /* Set R0 to point to the task stack pointer. */ \ + "STMDB SP,{SP}^ \n\t" \ + "NOP \n\t" \ + "SUB SP, SP, #4 \n\t" \ + "LDMIA SP!,{R0} \n\t" \ + \ + /* Push the return address onto the stack. */ \ + "STMDB R0!, {LR} \n\t" \ + \ + /* Now we have saved LR we can use it instead of R0. */ \ + "MOV LR, R0 \n\t" \ + \ + /* Pop R0 so we can save it onto the system mode stack. */ \ + "LDMIA SP!, {R0} \n\t" \ + \ + /* Push all the system mode registers onto the task stack. */ \ + "STMDB LR,{R0-LR}^ \n\t" \ + "NOP \n\t" \ + "SUB LR, LR, #60 \n\t" \ + \ + /* Push the SPSR onto the task stack. */ \ + "MRS R0, SPSR \n\t" \ + "STMDB LR!, {R0} \n\t" \ + \ + "LDR R0, =ulCriticalNesting \n\t" \ + "LDR R0, [R0] \n\t" \ + "STMDB LR!, {R0} \n\t" \ + \ + /* Store the new top of stack for the task. */ \ + "LDR R0, =pxCurrentTCB \n\t" \ + "LDR R0, [R0] \n\t" \ + "STR LR, [R0] \n\t" \ + ); \ + ( void ) ulCriticalNesting; \ + ( void ) pxCurrentTCB; \ + } + + +#define portYIELD_FROM_ISR() vTaskSwitchContext() +#define portYIELD() __asm volatile ( "SWI 0" ) +/*-----------------------------------------------------------*/ + + +/* Critical section management. */ + +/* + * The interrupt management utilities can only be called from ARM mode. When + * THUMB_INTERWORK is defined the utilities are defined as functions in + * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not + * defined then the utilities are defined as macros here - as per other ports. + */ + +#ifdef THUMB_INTERWORK + + extern void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) ); + extern void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) ); + + #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb() + #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb() + +#else + + #define portDISABLE_INTERRUPTS() \ + __asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ + + #define portENABLE_INTERRUPTS() \ + __asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ + +#endif /* THUMB_INTERWORK */ + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/ARM7_LPC2000/port.c b/portable/GCC/ARM7_LPC2000/port.c new file mode 100644 index 000000000..2c8268af5 --- /dev/null +++ b/portable/GCC/ARM7_LPC2000/port.c @@ -0,0 +1,222 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ARM7 port. +* +* Components that can be compiled to either ARM or THUMB mode are +* contained in this file. The ISR routines, which can only be compiled +* to ARM mode are contained in portISR.c. +*----------------------------------------------------------*/ + + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to setup the task context. */ +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) +#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 ) + +/* Constants required to setup the tick ISR. */ +#define portENABLE_TIMER ( ( uint8_t ) 0x01 ) +#define portPRESCALE_VALUE 0x00 +#define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 ) +#define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 ) + +/* Constants required to setup the VIC for the tick ISR. */ +#define portTIMER_VIC_CHANNEL ( ( uint32_t ) 0x0004 ) +#define portTIMER_VIC_CHANNEL_BIT ( ( uint32_t ) 0x0010 ) +#define portTIMER_VIC_ENABLE ( ( uint32_t ) 0x0020 ) + +/*-----------------------------------------------------------*/ + +/* Setup the timer to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* + * The scheduler can only be started from ARM mode, so + * vPortISRStartFirstSTask() is defined in portISR.c. + */ +extern void vPortISRStartFirstTask( void ); + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + StackType_t * pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + /* To ensure asserts in tasks.c don't fail, although in this case the assert + * is not really required. */ + pxTopOfStack--; + + /* Setup the initial stack of the task. The stack is set exactly as + * expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which in this case is the + * start of the task. The offset is added to make the return address appear + * as it would within an IRQ ISR. */ + *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + * R0. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The last thing onto the stack is the status register, which is set for + * system mode, with interrupts enabled. */ + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + + if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00 ) + { + /* We want the task to start in thumb mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + + pxTopOfStack--; + + /* Some optimisation levels use the stack differently to others. This + * means the interrupt flags cannot always be stored on the stack and will + * instead be stored in a variable, which is then saved as part of the + * tasks context. */ + *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortISRStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + * is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +/* + * Setup the timer 0 to generate the tick interrupts at the required frequency. + */ +static void prvSetupTimerInterrupt( void ) +{ + uint32_t ulCompareMatch; + + extern void( vTickISR )( void ); + + /* A 1ms tick does not require the use of the timer prescale. This is + * defaulted to zero but can be used if necessary. */ + T0_PR = portPRESCALE_VALUE; + + /* Calculate the match value required for our wanted tick rate. */ + ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ; + + /* Protect against divide by zero. Using an if() statement still results + * in a warning - hence the #if. */ + #if portPRESCALE_VALUE != 0 + { + ulCompareMatch /= ( portPRESCALE_VALUE + 1 ); + } + #endif + T0_MR0 = ulCompareMatch; + + /* Generate tick with timer 0 compare match. */ + T0_MCR = portRESET_COUNT_ON_MATCH | portINTERRUPT_ON_MATCH; + + /* Setup the VIC for the timer. */ + VICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT ); + VICIntEnable |= portTIMER_VIC_CHANNEL_BIT; + + /* The ISR installed depends on whether the preemptive or cooperative + * scheduler is being used. */ + + VICVectAddr0 = ( int32_t ) vTickISR; + VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE; + + /* Start the timer - interrupts are disabled when this function is called + * so it is okay to do this here. */ + T0_TCR = portENABLE_TIMER; +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM7_LPC2000/portISR.c b/portable/GCC/ARM7_LPC2000/portISR.c new file mode 100644 index 000000000..4255df713 --- /dev/null +++ b/portable/GCC/ARM7_LPC2000/portISR.c @@ -0,0 +1,216 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/*----------------------------------------------------------- +* Components that can be compiled to either ARM or THUMB mode are +* contained in port.c The ISR routines, which can only be compiled +* to ARM mode, are contained in this file. +*----------------------------------------------------------*/ + +/* + * Changes from V2.5.2 + * + + The critical section management functions have been changed. These no + + longer modify the stack and are safe to use at all optimisation levels. + + The functions are now also the same for both ARM and THUMB modes. + + + + Changes from V2.6.0 + + + + Removed the 'static' from the definition of vNonPreemptiveTick() to + + allow the demo to link when using the cooperative scheduler. + + + + Changes from V3.2.4 + + + + The assembler statements are now included in a single asm block rather + + than each line having its own asm block. + */ + + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* Constants required to handle interrupts. */ +#define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 ) +#define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 ) + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) +volatile uint32_t ulCriticalNesting = 9999UL; + +/*-----------------------------------------------------------*/ + +/* ISR to handle manual context switches (from a call to taskYIELD()). */ +void vPortYieldProcessor( void ) __attribute__( ( interrupt( "SWI" ), naked ) ); + +/* + * The scheduler can only be started from ARM mode, hence the inclusion of this + * function here. + */ +void vPortISRStartFirstTask( void ); +/*-----------------------------------------------------------*/ + +void vPortISRStartFirstTask( void ) +{ + /* Simply start the scheduler. This is included here as it can only be + * called from ARM mode. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * Called by portYIELD() or taskYIELD() to manually force a context switch. + * + * When a context switch is performed from the task level the saved task + * context is made to look as if it occurred from within the tick ISR. This + * way the same restore context function can be used when restoring the context + * saved from the ISR or that saved from a call to vPortYieldProcessor. + */ +void vPortYieldProcessor( void ) +{ + /* Within an IRQ ISR the link register has an offset from the true return + * address, but an SWI ISR does not. Add the offset manually so the same + * ISR return code can be used in both cases. */ + __asm volatile ( "ADD LR, LR, #4" ); + + /* Perform the context switch. First save the context of the current task. */ + portSAVE_CONTEXT(); + + /* Find the highest priority task that is ready to run. */ + __asm volatile ( "bl vTaskSwitchContext" ); + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * The ISR used for the scheduler tick. + */ +void vTickISR( void ) __attribute__( ( naked ) ); +void vTickISR( void ) +{ + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT(); + + /* Increment the RTOS tick count, then look for the highest priority + * task that is ready to run. */ + __asm volatile + ( + " bl xTaskIncrementTick \t\n" \ + " cmp r0, #0 \t\n" \ + " beq SkipContextSwitch \t\n" \ + " bl vTaskSwitchContext \t\n" \ + "SkipContextSwitch: \t\n" + ); + + /* Ready for the next interrupt. */ + T0_IR = portTIMER_MATCH_ISR_BIT; + VICVectAddr = portCLEAR_VIC_INTERRUPT; + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * The interrupt management utilities can only be called from ARM mode. When + * THUMB_INTERWORK is defined the utilities are defined as functions here to + * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then + * the utilities are defined as macros in portmacro.h - as per other ports. + */ +#ifdef THUMB_INTERWORK + + void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) ); + void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) ); + + void vPortDisableInterruptsFromThumb( void ) + { + __asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ + } + + void vPortEnableInterruptsFromThumb( void ) + { + __asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ + } + +#endif /* THUMB_INTERWORK */ + +/* The code generated by the GCC compiler uses the stack in different ways at + * different optimisation levels. The interrupt flags can therefore not always + * be saved to the stack. Instead the critical section nesting level is stored + * in a variable, which is then saved as part of the stack context. */ +void vPortEnterCritical( void ) +{ + /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ + __asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ + + /* Now that interrupts are disabled, ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + * re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Enable interrupts as per portEXIT_CRITICAL(). */ + __asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ + } + } +} diff --git a/portable/GCC/ARM7_LPC2000/portmacro.h b/portable/GCC/ARM7_LPC2000/portmacro.h new file mode 100644 index 000000000..8e82cc08e --- /dev/null +++ b/portable/GCC/ARM7_LPC2000/portmacro.h @@ -0,0 +1,232 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE portLONG + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() __asm volatile ( "NOP" ); +/*-----------------------------------------------------------*/ + + +/* Scheduler utilities. */ + +/* + * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR + * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but + * are included here for efficiency. An attempt to call one from + * THUMB mode code will result in a compile time error. + */ + +#define portRESTORE_CONTEXT() \ + { \ + extern volatile void * volatile pxCurrentTCB; \ + extern volatile uint32_t ulCriticalNesting; \ + \ + /* Set the LR to the task stack. */ \ + __asm volatile ( \ + "LDR R0, =pxCurrentTCB \n\t" \ + "LDR R0, [R0] \n\t" \ + "LDR LR, [R0] \n\t" \ + \ + /* The critical nesting depth is the first item on the stack. */ \ + /* Load it into the ulCriticalNesting variable. */ \ + "LDR R0, =ulCriticalNesting \n\t" \ + "LDMFD LR!, {R1} \n\t" \ + "STR R1, [R0] \n\t" \ + \ + /* Get the SPSR from the stack. */ \ + "LDMFD LR!, {R0} \n\t" \ + "MSR SPSR, R0 \n\t" \ + \ + /* Restore all system mode registers for the task. */ \ + "LDMFD LR, {R0-R14}^ \n\t" \ + "NOP \n\t" \ + \ + /* Restore the return address. */ \ + "LDR LR, [LR, #+60] \n\t" \ + \ + /* And return - correcting the offset in the LR to obtain the */ \ + /* correct address. */ \ + "SUBS PC, LR, #4 \n\t" \ + ); \ + ( void ) ulCriticalNesting; \ + ( void ) pxCurrentTCB; \ + } +/*-----------------------------------------------------------*/ + +#define portSAVE_CONTEXT() \ + { \ + extern volatile void * volatile pxCurrentTCB; \ + extern volatile uint32_t ulCriticalNesting; \ + \ + /* Push R0 as we are going to use the register. */ \ + __asm volatile ( \ + "STMDB SP!, {R0} \n\t" \ + \ + /* Set R0 to point to the task stack pointer. */ \ + "STMDB SP,{SP}^ \n\t" \ + "NOP \n\t" \ + "SUB SP, SP, #4 \n\t" \ + "LDMIA SP!,{R0} \n\t" \ + \ + /* Push the return address onto the stack. */ \ + "STMDB R0!, {LR} \n\t" \ + \ + /* Now we have saved LR we can use it instead of R0. */ \ + "MOV LR, R0 \n\t" \ + \ + /* Pop R0 so we can save it onto the system mode stack. */ \ + "LDMIA SP!, {R0} \n\t" \ + \ + /* Push all the system mode registers onto the task stack. */ \ + "STMDB LR,{R0-LR}^ \n\t" \ + "NOP \n\t" \ + "SUB LR, LR, #60 \n\t" \ + \ + /* Push the SPSR onto the task stack. */ \ + "MRS R0, SPSR \n\t" \ + "STMDB LR!, {R0} \n\t" \ + \ + "LDR R0, =ulCriticalNesting \n\t" \ + "LDR R0, [R0] \n\t" \ + "STMDB LR!, {R0} \n\t" \ + \ + /* Store the new top of stack for the task. */ \ + "LDR R0, =pxCurrentTCB \n\t" \ + "LDR R0, [R0] \n\t" \ + "STR LR, [R0] \n\t" \ + ); \ + ( void ) ulCriticalNesting; \ + ( void ) pxCurrentTCB; \ + } + +extern void vTaskSwitchContext( void ); +#define portYIELD_FROM_ISR() vTaskSwitchContext() +#define portYIELD() __asm volatile ( "SWI 0" ) +/*-----------------------------------------------------------*/ + + +/* Critical section management. */ + +/* + * The interrupt management utilities can only be called from ARM mode. When + * THUMB_INTERWORK is defined the utilities are defined as functions in + * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not + * defined then the utilities are defined as macros here - as per other ports. + */ + +#ifdef THUMB_INTERWORK + + extern void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) ); + extern void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) ); + + #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb() + #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb() + +#else + + #define portDISABLE_INTERRUPTS() \ + __asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ + + #define portENABLE_INTERRUPTS() \ + __asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ + +#endif /* THUMB_INTERWORK */ + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/ARM7_LPC23xx/port.c b/portable/GCC/ARM7_LPC23xx/port.c new file mode 100644 index 000000000..8ac1df709 --- /dev/null +++ b/portable/GCC/ARM7_LPC23xx/port.c @@ -0,0 +1,233 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ARM7 port. +* +* Components that can be compiled to either ARM or THUMB mode are +* contained in this file. The ISR routines, which can only be compiled +* to ARM mode are contained in portISR.c. +*----------------------------------------------------------*/ + + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to setup the task context. */ +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) +#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 ) + +/* Constants required to setup the tick ISR. */ +#define portENABLE_TIMER ( ( uint8_t ) 0x01 ) +#define portPRESCALE_VALUE 0x00 +#define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 ) +#define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 ) + +/* Constants required to setup the VIC for the tick ISR. */ +#define portTIMER_VIC_CHANNEL ( ( uint32_t ) 0x0004 ) +#define portTIMER_VIC_CHANNEL_BIT ( ( uint32_t ) 0x0010 ) +#define portTIMER_VIC_ENABLE ( ( uint32_t ) 0x0020 ) + +/*-----------------------------------------------------------*/ + +/* Setup the timer to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* + * The scheduler can only be started from ARM mode, so + * vPortISRStartFirstSTask() is defined in portISR.c. + */ +extern void vPortISRStartFirstTask( void ); + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + StackType_t * pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + /* To ensure asserts in tasks.c don't fail, although in this case the assert + * is not really required. */ + pxTopOfStack--; + + /* Setup the initial stack of the task. The stack is set exactly as + * expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which in this case is the + * start of the task. The offset is added to make the return address appear + * as it would within an IRQ ISR. */ + *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0x00000000; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + * R0. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The last thing onto the stack is the status register, which is set for + * system mode, with interrupts enabled. */ + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + + if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00 ) + { + /* We want the task to start in thumb mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + + pxTopOfStack--; + + /* Some optimisation levels use the stack differently to others. This + * means the interrupt flags cannot always be stored on the stack and will + * instead be stored in a variable, which is then saved as part of the + * tasks context. */ + *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortISRStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + * is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +/* + * Setup the timer 0 to generate the tick interrupts at the required frequency. + */ +static void prvSetupTimerInterrupt( void ) +{ + uint32_t ulCompareMatch; + + PCLKSEL0 = ( PCLKSEL0 & ( ~( 0x3 << 2 ) ) ) | ( 0x01 << 2 ); + T0TCR = 2; /* Stop and reset the timer */ + T0CTCR = 0; /* Timer mode */ + + /* A 1ms tick does not require the use of the timer prescale. This is + * defaulted to zero but can be used if necessary. */ + T0PR = portPRESCALE_VALUE; + + /* Calculate the match value required for our wanted tick rate. */ + ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ; + + /* Protect against divide by zero. Using an if() statement still results + * in a warning - hence the #if. */ + #if portPRESCALE_VALUE != 0 + { + ulCompareMatch /= ( portPRESCALE_VALUE + 1 ); + } + #endif + T0MR1 = ulCompareMatch; + + /* Generate tick with timer 0 compare match. */ + T0MCR = ( 3 << 3 ); /* Reset timer on match and generate interrupt */ + + /* Setup the VIC for the timer. */ + VICIntEnable = 0x00000010; + + /* The ISR installed depends on whether the preemptive or cooperative + * scheduler is being used. */ + #if configUSE_PREEMPTION == 1 + { + extern void( vPreemptiveTick )( void ); + VICVectAddr4 = ( int32_t ) vPreemptiveTick; + } + #else + { + extern void( vNonPreemptiveTick )( void ); + VICVectAddr4 = ( int32_t ) vNonPreemptiveTick; + } + #endif + + VICVectCntl4 = 1; + + /* Start the timer - interrupts are disabled when this function is called + * so it is okay to do this here. */ + T0TCR = portENABLE_TIMER; +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM7_LPC23xx/portISR.c b/portable/GCC/ARM7_LPC23xx/portISR.c new file mode 100644 index 000000000..1cf7c7dae --- /dev/null +++ b/portable/GCC/ARM7_LPC23xx/portISR.c @@ -0,0 +1,219 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/*----------------------------------------------------------- +* Components that can be compiled to either ARM or THUMB mode are +* contained in port.c The ISR routines, which can only be compiled +* to ARM mode, are contained in this file. +*----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to handle interrupts. */ +#define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 ) +#define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 ) + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) +volatile uint32_t ulCriticalNesting = 9999UL; + +/*-----------------------------------------------------------*/ + +/* ISR to handle manual context switches (from a call to taskYIELD()). */ +void vPortYieldProcessor( void ) __attribute__( ( interrupt( "SWI" ), naked ) ); + +/* + * The scheduler can only be started from ARM mode, hence the inclusion of this + * function here. + */ +void vPortISRStartFirstTask( void ); +/*-----------------------------------------------------------*/ + +void vPortISRStartFirstTask( void ) +{ + /* Simply start the scheduler. This is included here as it can only be + * called from ARM mode. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * Called by portYIELD() or taskYIELD() to manually force a context switch. + * + * When a context switch is performed from the task level the saved task + * context is made to look as if it occurred from within the tick ISR. This + * way the same restore context function can be used when restoring the context + * saved from the ISR or that saved from a call to vPortYieldProcessor. + */ +void vPortYieldProcessor( void ) +{ + /* Within an IRQ ISR the link register has an offset from the true return + * address, but an SWI ISR does not. Add the offset manually so the same + * ISR return code can be used in both cases. */ + __asm volatile ( "ADD LR, LR, #4" ); + + /* Perform the context switch. First save the context of the current task. */ + portSAVE_CONTEXT(); + + /* Find the highest priority task that is ready to run. */ + __asm volatile ( "bl vTaskSwitchContext" ); + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * The ISR used for the scheduler tick depends on whether the cooperative or + * the preemptive scheduler is being used. + */ + + +#if configUSE_PREEMPTION == 0 + +/* The cooperative scheduler requires a normal IRQ service routine to + * simply increment the system tick. */ + void vNonPreemptiveTick( void ) __attribute__( ( interrupt( "IRQ" ) ) ); + void vNonPreemptiveTick( void ) + { + xTaskIncrementTick(); + T0IR = 2; + VICVectAddr = portCLEAR_VIC_INTERRUPT; + } + +#else /* if configUSE_PREEMPTION == 0 */ + +/* The preemptive scheduler is defined as "naked" as the full context is + * saved on entry as part of the context switch. */ + void vPreemptiveTick( void ) __attribute__( ( naked ) ); + void vPreemptiveTick( void ) + { + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT(); + + /* Increment the RTOS tick count, then look for the highest priority + * task that is ready to run. */ + __asm volatile + ( + " bl xTaskIncrementTick \t\n" \ + " cmp r0, #0 \t\n" \ + " beq SkipContextSwitch \t\n" \ + " bl vTaskSwitchContext \t\n" \ + "SkipContextSwitch: \t\n" + ); + + /* Ready for the next interrupt. */ + T0IR = 2; + VICVectAddr = portCLEAR_VIC_INTERRUPT; + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT(); + } + +#endif /* if configUSE_PREEMPTION == 0 */ +/*-----------------------------------------------------------*/ + +/* + * The interrupt management utilities can only be called from ARM mode. When + * THUMB_INTERWORK is defined the utilities are defined as functions here to + * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then + * the utilities are defined as macros in portmacro.h - as per other ports. + */ +#ifdef THUMB_INTERWORK + + void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) ); + void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) ); + + void vPortDisableInterruptsFromThumb( void ) + { + __asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ + } + + void vPortEnableInterruptsFromThumb( void ) + { + __asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ + } + +#endif /* THUMB_INTERWORK */ + +/* The code generated by the GCC compiler uses the stack in different ways at + * different optimisation levels. The interrupt flags can therefore not always + * be saved to the stack. Instead the critical section nesting level is stored + * in a variable, which is then saved as part of the stack context. */ +void vPortEnterCritical( void ) +{ + /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ + __asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ + + /* Now that interrupts are disabled, ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + * re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Enable interrupts as per portEXIT_CRITICAL(). */ + __asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ + } + } +} diff --git a/portable/GCC/ARM7_LPC23xx/portmacro.h b/portable/GCC/ARM7_LPC23xx/portmacro.h new file mode 100644 index 000000000..3f2242fa9 --- /dev/null +++ b/portable/GCC/ARM7_LPC23xx/portmacro.h @@ -0,0 +1,255 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * Changes from V3.2.3 + * + + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1. + + + + Changes from V3.2.4 + + + + Removed the use of the %0 parameter within the assembler macros and + + replaced them with hard coded registers. This will ensure the + + assembler does not select the link register as the temp register as + + was occasionally happening previously. + + + + The assembler statements are now included in a single asm block rather + + than each line having its own asm block. + + + + Changes from V4.5.0 + + + + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros + + and replaced them with portYIELD_FROM_ISR() macro. Application code + + should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT() + + macros as per the V4.5.1 demo code. + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE portLONG + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() __asm volatile ( "NOP" ); +/*-----------------------------------------------------------*/ + + +/* Scheduler utilities. */ + +/* + * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR + * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but + * are included here for efficiency. An attempt to call one from + * THUMB mode code will result in a compile time error. + */ + +#define portRESTORE_CONTEXT() \ + { \ + extern volatile void * volatile pxCurrentTCB; \ + extern volatile uint32_t ulCriticalNesting; \ + \ + /* Set the LR to the task stack. */ \ + __asm volatile ( \ + "LDR R0, =pxCurrentTCB \n\t" \ + "LDR R0, [R0] \n\t" \ + "LDR LR, [R0] \n\t" \ + \ + /* The critical nesting depth is the first item on the stack. */ \ + /* Load it into the ulCriticalNesting variable. */ \ + "LDR R0, =ulCriticalNesting \n\t" \ + "LDMFD LR!, {R1} \n\t" \ + "STR R1, [R0] \n\t" \ + \ + /* Get the SPSR from the stack. */ \ + "LDMFD LR!, {R0} \n\t" \ + "MSR SPSR, R0 \n\t" \ + \ + /* Restore all system mode registers for the task. */ \ + "LDMFD LR, {R0-R14}^ \n\t" \ + "NOP \n\t" \ + \ + /* Restore the return address. */ \ + "LDR LR, [LR, #+60] \n\t" \ + \ + /* And return - correcting the offset in the LR to obtain the */ \ + /* correct address. */ \ + "SUBS PC, LR, #4 \n\t" \ + ); \ + ( void ) ulCriticalNesting; \ + ( void ) pxCurrentTCB; \ + } +/*-----------------------------------------------------------*/ + +#define portSAVE_CONTEXT() \ + { \ + extern volatile void * volatile pxCurrentTCB; \ + extern volatile uint32_t ulCriticalNesting; \ + \ + /* Push R0 as we are going to use the register. */ \ + __asm volatile ( \ + "STMDB SP!, {R0} \n\t" \ + \ + /* Set R0 to point to the task stack pointer. */ \ + "STMDB SP,{SP}^ \n\t" \ + "NOP \n\t" \ + "SUB SP, SP, #4 \n\t" \ + "LDMIA SP!,{R0} \n\t" \ + \ + /* Push the return address onto the stack. */ \ + "STMDB R0!, {LR} \n\t" \ + \ + /* Now we have saved LR we can use it instead of R0. */ \ + "MOV LR, R0 \n\t" \ + \ + /* Pop R0 so we can save it onto the system mode stack. */ \ + "LDMIA SP!, {R0} \n\t" \ + \ + /* Push all the system mode registers onto the task stack. */ \ + "STMDB LR,{R0-LR}^ \n\t" \ + "NOP \n\t" \ + "SUB LR, LR, #60 \n\t" \ + \ + /* Push the SPSR onto the task stack. */ \ + "MRS R0, SPSR \n\t" \ + "STMDB LR!, {R0} \n\t" \ + \ + "LDR R0, =ulCriticalNesting \n\t" \ + "LDR R0, [R0] \n\t" \ + "STMDB LR!, {R0} \n\t" \ + \ + /* Store the new top of stack for the task. */ \ + "LDR R0, =pxCurrentTCB \n\t" \ + "LDR R0, [R0] \n\t" \ + "STR LR, [R0] \n\t" \ + ); \ + ( void ) ulCriticalNesting; \ + ( void ) pxCurrentTCB; \ + } + + +#define portYIELD_FROM_ISR() vTaskSwitchContext() +#define portYIELD() __asm volatile ( "SWI 0" ) +/*-----------------------------------------------------------*/ + + +/* Critical section management. */ + +/* + * The interrupt management utilities can only be called from ARM mode. When + * THUMB_INTERWORK is defined the utilities are defined as functions in + * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not + * defined then the utilities are defined as macros here - as per other ports. + */ + +#ifdef THUMB_INTERWORK + + extern void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) ); + extern void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) ); + + #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb() + #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb() + +#else + + #define portDISABLE_INTERRUPTS() \ + __asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ + + #define portENABLE_INTERRUPTS() \ + __asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ + +#endif /* THUMB_INTERWORK */ + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/ARM_AARCH64/README.md b/portable/GCC/ARM_AARCH64/README.md new file mode 100644 index 000000000..60f670177 --- /dev/null +++ b/portable/GCC/ARM_AARCH64/README.md @@ -0,0 +1,23 @@ +# Armv8-A architecture support + +The Armv8-A architecture introduces the ability to use 64-bit and 32-bit +Execution states, known as AArch64 and AArch32 respectively. The AArch64 +Execution state supports the A64 instruction set. It holds addresses in 64-bit +registers and allows instructions in the base instruction set to use 64-bit +registers for their processing. + +The AArch32 Execution state is a 32-bit Execution state that preserves +backwards compatibility with the Armv7-A architecture, enhancing that profile +so that it can support some features included in the AArch64 state. It supports +the T32 and A32 instruction sets. Follow the +[link](https://developer.arm.com/Architectures/A-Profile%20Architecture) +for more information. + +## ARM_AARCH64 port + +This port adds support for Armv8-A architecture AArch64 execution state. +This port is generic and can be used as a starting point for Armv8-A +application processors. + +* ARM_AARCH64 + * Memory mapped interface to access Arm GIC registers diff --git a/portable/GCC/ARM_AARCH64/port.c b/portable/GCC/ARM_AARCH64/port.c new file mode 100644 index 000000000..7f080db74 --- /dev/null +++ b/portable/GCC/ARM_AARCH64/port.c @@ -0,0 +1,556 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS + #error "configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" +#endif + +#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET + #error "configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" +#endif + +#ifndef configUNIQUE_INTERRUPT_PRIORITIES + #error "configUNIQUE_INTERRUPT_PRIORITIES must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" +#endif + +#ifndef configSETUP_TICK_INTERRUPT + #error "configSETUP_TICK_INTERRUPT() must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" +#endif /* configSETUP_TICK_INTERRUPT */ + +#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" +#endif + +#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0 + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0" +#endif + +#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority" +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + /* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice." + #endif +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/* In case security extensions are implemented. */ +#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 ) + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )" +#endif + +/* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in + * portmacro.h. */ +#ifndef configCLEAR_TICK_INTERRUPT + #define configCLEAR_TICK_INTERRUPT() +#endif + +/* A critical section is exited when the critical section nesting count reaches + * this value. */ +#define portNO_CRITICAL_NESTING ( ( size_t ) 0 ) + +/* In all GICs 255 can be written to the priority mask register to unmask all + * (but the lowest) interrupt priority. */ +#define portUNMASK_VALUE ( 0xFFUL ) + +/* Tasks are not created with a floating point context, but can be given a + * floating point context after they have been created. A variable is stored as + * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task + * does not have an FPU context, or any other value if the task does have an FPU + * context. */ +#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) + +/* Constants required to setup the initial task context. */ +#define portSP_ELx ( ( StackType_t ) 0x01 ) +#define portSP_EL0 ( ( StackType_t ) 0x00 ) + +#if defined( GUEST ) + #define portEL1 ( ( StackType_t ) 0x04 ) + #define portINITIAL_PSTATE ( portEL1 | portSP_EL0 ) +#else + #define portEL3 ( ( StackType_t ) 0x0c ) + /* At the time of writing, the BSP only supports EL3. */ + #define portINITIAL_PSTATE ( portEL3 | portSP_EL0 ) +#endif + + +/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary + * point is zero. */ +#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 ) + +/* Masks all bits in the APSR other than the mode bits. */ +#define portAPSR_MODE_BITS_MASK ( 0x0C ) + +/* The I bit in the DAIF bits. */ +#define portDAIF_I ( 0x80 ) + +/* Macro to unmask all interrupt priorities. */ +#define portCLEAR_INTERRUPT_MASK() \ + { \ + portDISABLE_INTERRUPTS(); \ + portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \ + __asm volatile ( "DSB SY \n" \ + "ISB SY \n" ); \ + portENABLE_INTERRUPTS(); \ + } + +/* Hardware specifics used when sanity checking the configuration. */ +#define portINTERRUPT_PRIORITY_REGISTER_OFFSET 0x400UL +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portBIT_0_SET ( ( uint8_t ) 0x01 ) + +/* The space on the stack required to hold the FPU registers. + * There are 32 128-bit registers.*/ +#define portFPU_REGISTER_WORDS ( 32 * 2 ) + +/*-----------------------------------------------------------*/ + +/* + * Starts the first task executing. This function is necessarily written in + * assembly code so is implemented in portASM.s. + */ +extern void vPortRestoreTaskContext( void ); + +/*-----------------------------------------------------------*/ + +/* A variable is used to keep track of the critical section nesting. This + * variable has to be stored as part of the task context and must be initialised to + * a non zero value to ensure interrupts don't inadvertently become unmasked before + * the scheduler starts. As it is stored as part of the task context it will + * automatically be set to 0 when the first task is started. */ +volatile uint64_t ullCriticalNesting = 9999ULL; + +/* Saved as part of the task context. If ullPortTaskHasFPUContext is non-zero + * then floating point context must be saved and restored for the task. */ +uint64_t ullPortTaskHasFPUContext = pdFALSE; + +/* Set to 1 to pend a context switch from an ISR. */ +uint64_t ullPortYieldRequired = pdFALSE; + +/* Counts the interrupt nesting depth. A context switch is only performed if + * if the nesting depth is 0. */ +uint64_t ullPortInterruptNesting = 0; + +/* Used in the ASM code. */ +__attribute__( ( used ) ) const uint64_t ullICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS; +__attribute__( ( used ) ) const uint64_t ullICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS; +__attribute__( ( used ) ) const uint64_t ullICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS; +__attribute__( ( used ) ) const uint64_t ullMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Setup the initial stack of the task. The stack is set exactly as + * expected by the portRESTORE_CONTEXT() macro. */ + + /* First all the general purpose registers. */ + pxTopOfStack--; + *pxTopOfStack = 0x0101010101010101ULL; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + *pxTopOfStack = 0x0303030303030303ULL; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = 0x0202020202020202ULL; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = 0x0505050505050505ULL; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = 0x0404040404040404ULL; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = 0x0707070707070707ULL; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = 0x0606060606060606ULL; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = 0x0909090909090909ULL; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = 0x0808080808080808ULL; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = 0x1111111111111111ULL; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = 0x1010101010101010ULL; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = 0x1313131313131313ULL; /* R13 */ + pxTopOfStack--; + *pxTopOfStack = 0x1212121212121212ULL; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = 0x1515151515151515ULL; /* R15 */ + pxTopOfStack--; + *pxTopOfStack = 0x1414141414141414ULL; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = 0x1717171717171717ULL; /* R17 */ + pxTopOfStack--; + *pxTopOfStack = 0x1616161616161616ULL; /* R16 */ + pxTopOfStack--; + *pxTopOfStack = 0x1919191919191919ULL; /* R19 */ + pxTopOfStack--; + *pxTopOfStack = 0x1818181818181818ULL; /* R18 */ + pxTopOfStack--; + *pxTopOfStack = 0x2121212121212121ULL; /* R21 */ + pxTopOfStack--; + *pxTopOfStack = 0x2020202020202020ULL; /* R20 */ + pxTopOfStack--; + *pxTopOfStack = 0x2323232323232323ULL; /* R23 */ + pxTopOfStack--; + *pxTopOfStack = 0x2222222222222222ULL; /* R22 */ + pxTopOfStack--; + *pxTopOfStack = 0x2525252525252525ULL; /* R25 */ + pxTopOfStack--; + *pxTopOfStack = 0x2424242424242424ULL; /* R24 */ + pxTopOfStack--; + *pxTopOfStack = 0x2727272727272727ULL; /* R27 */ + pxTopOfStack--; + *pxTopOfStack = 0x2626262626262626ULL; /* R26 */ + pxTopOfStack--; + *pxTopOfStack = 0x2929292929292929ULL; /* R29 */ + pxTopOfStack--; + *pxTopOfStack = 0x2828282828282828ULL; /* R28 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x00; /* XZR - has no effect, used so there are an even number of registers. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x00; /* R30 - procedure call link register. */ + + pxTopOfStack--; + *pxTopOfStack = portINITIAL_PSTATE; + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* Exception return address. */ + + #if ( configUSE_TASK_FPU_SUPPORT == 1 ) + { + /* The task will start with a critical nesting count of 0 as interrupts are + * enabled. */ + pxTopOfStack--; + *pxTopOfStack = portNO_CRITICAL_NESTING; + + /* The task will start without a floating point context. A task that + * uses the floating point hardware must call vPortTaskUsesFPU() before + * executing any floating point instructions. */ + pxTopOfStack--; + *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT; + } + #elif ( configUSE_TASK_FPU_SUPPORT == 2 ) + { + /* The task will start with a floating point context. Leave enough + * space for the registers - and ensure they are initialised to 0. */ + pxTopOfStack -= portFPU_REGISTER_WORDS; + memset( pxTopOfStack, 0x00, portFPU_REGISTER_WORDS * sizeof( StackType_t ) ); + + /* The task will start with a critical nesting count of 0 as interrupts are + * enabled. */ + pxTopOfStack--; + *pxTopOfStack = portNO_CRITICAL_NESTING; + + pxTopOfStack--; + *pxTopOfStack = pdTRUE; + ullPortTaskHasFPUContext = pdTRUE; + } + #else /* if ( configUSE_TASK_FPU_SUPPORT == 1 ) */ + { + #error "Invalid configUSE_TASK_FPU_SUPPORT setting - configUSE_TASK_FPU_SUPPORT must be set to 1, 2, or left undefined." + } + #endif /* if ( configUSE_TASK_FPU_SUPPORT == 1 ) */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + uint32_t ulAPSR; + + #if ( configASSERT_DEFINED == 1 ) + { + volatile uint8_t ucOriginalPriority; + volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET ); + volatile uint8_t ucMaxPriorityValue; + + /* Determine how many priority bits are implemented in the GIC. + * + * Save the interrupt priority value that is about to be clobbered. */ + ucOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to + * all possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* Shift to the least significant bits. */ + while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET ) + { + ucMaxPriorityValue >>= ( uint8_t ) 0x01; + } + + /* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read + * value. */ + + configASSERT( ucMaxPriorityValue >= portLOWEST_INTERRUPT_PRIORITY ); + + + /* Restore the clobbered interrupt priority register to its original + * value. */ + *pucFirstUserPriorityRegister = ucOriginalPriority; + } + #endif /* configASSERT_DEFINED */ + + + /* At the time of writing, the BSP only supports EL3. */ + __asm volatile ( "MRS %0, CurrentEL" : "=r" ( ulAPSR ) ); + ulAPSR &= portAPSR_MODE_BITS_MASK; + + #if defined( GUEST ) + #warning "Building for execution as a guest under XEN. THIS IS NOT A FULLY TESTED PATH." + configASSERT( ulAPSR == portEL1 ); + + if( ulAPSR == portEL1 ) + #else + configASSERT( ulAPSR == portEL3 ); + + if( ulAPSR == portEL3 ) + #endif + { + /* Only continue if the binary point value is set to its lowest possible + * setting. See the comments in vPortValidateInterruptPriority() below for + * more information. */ + configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ); + + if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ) + { + /* Interrupts are turned off in the CPU itself to ensure a tick does + * not execute while the scheduler is being started. Interrupts are + * automatically turned back on in the CPU when the first task starts + * executing. */ + portDISABLE_INTERRUPTS(); + + /* Start the timer that generates the tick ISR. */ + configSETUP_TICK_INTERRUPT(); + + /* Start the first task executing. */ + vPortRestoreTaskContext(); + } + } + + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ullCriticalNesting == 1000ULL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + /* Mask interrupts up to the max syscall interrupt priority. */ + uxPortSetInterruptMask(); + + /* Now interrupts are disabled ullCriticalNesting can be accessed + * directly. Increment ullCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ + ullCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ + if( ullCriticalNesting == 1ULL ) + { + configASSERT( ullPortInterruptNesting == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + if( ullCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as the critical section is being + * exited. */ + ullCriticalNesting--; + + /* If the nesting level has reached zero then all interrupt + * priorities must be re-enabled. */ + if( ullCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Critical nesting has reached zero so all interrupt priorities + * should be unmasked. */ + portCLEAR_INTERRUPT_MASK(); + } + } +} +/*-----------------------------------------------------------*/ + +void FreeRTOS_Tick_Handler( void ) +{ + /* Must be the lowest possible priority. */ + #if !defined( QEMU ) + { + configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER == ( uint32_t ) ( portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ); + } + #endif + + /* Interrupts should not be enabled before this point. */ + #if ( configASSERT_DEFINED == 1 ) + { + uint32_t ulMaskBits; + + __asm volatile ( "mrs %0, daif" : "=r" ( ulMaskBits )::"memory" ); + configASSERT( ( ulMaskBits & portDAIF_I ) != 0 ); + } + #endif /* configASSERT_DEFINED */ + + /* Set interrupt mask before altering scheduler structures. The tick + * handler runs at the lowest priority, so interrupts cannot already be masked, + * so there is no need to save and restore the current mask value. It is + * necessary to turn off interrupts in the CPU itself while the ICCPMR is being + * updated. */ + portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); + __asm volatile ( "dsb sy \n" + "isb sy \n" ::: "memory" ); + + /* Ok to enable interrupts after the interrupt source has been cleared. */ + configCLEAR_TICK_INTERRUPT(); + portENABLE_INTERRUPTS(); + + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + ullPortYieldRequired = pdTRUE; + } + + /* Ensure all interrupt priorities are active again. */ + portCLEAR_INTERRUPT_MASK(); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_FPU_SUPPORT != 2 ) + + void vPortTaskUsesFPU( void ) + { + /* A task is registering the fact that it needs an FPU context. Set the + * FPU flag (which is saved as part of the task context). */ + ullPortTaskHasFPUContext = pdTRUE; + + /* Consider initialising the FPSR here - but probably not necessary in + * AArch64. */ + } + +#endif /* configUSE_TASK_FPU_SUPPORT */ +/*-----------------------------------------------------------*/ + +void vPortClearInterruptMask( UBaseType_t uxNewMaskValue ) +{ + if( uxNewMaskValue == pdFALSE ) + { + portCLEAR_INTERRUPT_MASK(); + } +} +/*-----------------------------------------------------------*/ + +UBaseType_t uxPortSetInterruptMask( void ) +{ + uint32_t ulReturn; + + /* Interrupt in the CPU must be turned off while the ICCPMR is being + * updated. */ + portDISABLE_INTERRUPTS(); + + if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ) + { + /* Interrupts were already masked. */ + ulReturn = pdTRUE; + } + else + { + ulReturn = pdFALSE; + portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); + __asm volatile ( "dsb sy \n" + "isb sy \n" ::: "memory" ); + } + + portENABLE_INTERRUPTS(); + + return ulReturn; +} +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. */ + configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ); + + /* Priority grouping: The interrupt controller (GIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * The priority grouping is configured by the GIC's binary point register + * (ICCBPR). Writing 0 to ICCBPR will ensure it is set to its lowest + * possible value (which may be above 0). */ + configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ); + } + +#endif /* configASSERT_DEFINED */ +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_AARCH64/portASM.S b/portable/GCC/ARM_AARCH64/portASM.S new file mode 100644 index 000000000..e684755bf --- /dev/null +++ b/portable/GCC/ARM_AARCH64/portASM.S @@ -0,0 +1,427 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + .text + + /* Variables and functions. */ + .extern ullMaxAPIPriorityMask + .extern pxCurrentTCB + .extern vTaskSwitchContext + .extern vApplicationIRQHandler + .extern ullPortInterruptNesting + .extern ullPortTaskHasFPUContext + .extern ullCriticalNesting + .extern ullPortYieldRequired + .extern ullICCEOIR + .extern ullICCIAR + .extern _freertos_vector_table + + .global FreeRTOS_IRQ_Handler + .global FreeRTOS_SWI_Handler + .global vPortRestoreTaskContext + + +.macro portSAVE_CONTEXT + + /* Switch to use the EL0 stack pointer. */ + MSR SPSEL, #0 + + /* Save the entire context. */ + STP X0, X1, [SP, #-0x10]! + STP X2, X3, [SP, #-0x10]! + STP X4, X5, [SP, #-0x10]! + STP X6, X7, [SP, #-0x10]! + STP X8, X9, [SP, #-0x10]! + STP X10, X11, [SP, #-0x10]! + STP X12, X13, [SP, #-0x10]! + STP X14, X15, [SP, #-0x10]! + STP X16, X17, [SP, #-0x10]! + STP X18, X19, [SP, #-0x10]! + STP X20, X21, [SP, #-0x10]! + STP X22, X23, [SP, #-0x10]! + STP X24, X25, [SP, #-0x10]! + STP X26, X27, [SP, #-0x10]! + STP X28, X29, [SP, #-0x10]! + STP X30, XZR, [SP, #-0x10]! + + /* Save the SPSR. */ +#if defined( GUEST ) + MRS X3, SPSR_EL1 + MRS X2, ELR_EL1 +#else + MRS X3, SPSR_EL3 + /* Save the ELR. */ + MRS X2, ELR_EL3 +#endif + + STP X2, X3, [SP, #-0x10]! + + /* Save the critical section nesting depth. */ + LDR X0, ullCriticalNestingConst + LDR X3, [X0] + + /* Save the FPU context indicator. */ + LDR X0, ullPortTaskHasFPUContextConst + LDR X2, [X0] + + /* Save the FPU context, if any (32 128-bit registers). */ + CMP X2, #0 + B.EQ 1f + STP Q0, Q1, [SP,#-0x20]! + STP Q2, Q3, [SP,#-0x20]! + STP Q4, Q5, [SP,#-0x20]! + STP Q6, Q7, [SP,#-0x20]! + STP Q8, Q9, [SP,#-0x20]! + STP Q10, Q11, [SP,#-0x20]! + STP Q12, Q13, [SP,#-0x20]! + STP Q14, Q15, [SP,#-0x20]! + STP Q16, Q17, [SP,#-0x20]! + STP Q18, Q19, [SP,#-0x20]! + STP Q20, Q21, [SP,#-0x20]! + STP Q22, Q23, [SP,#-0x20]! + STP Q24, Q25, [SP,#-0x20]! + STP Q26, Q27, [SP,#-0x20]! + STP Q28, Q29, [SP,#-0x20]! + STP Q30, Q31, [SP,#-0x20]! + +1: + /* Store the critical nesting count and FPU context indicator. */ + STP X2, X3, [SP, #-0x10]! + + LDR X0, pxCurrentTCBConst + LDR X1, [X0] + MOV X0, SP /* Move SP into X0 for saving. */ + STR X0, [X1] + + /* Switch to use the ELx stack pointer. */ + MSR SPSEL, #1 + + .endm + +; /**********************************************************************/ + +.macro portRESTORE_CONTEXT + + /* Switch to use the EL0 stack pointer. */ + MSR SPSEL, #0 + + /* Set the SP to point to the stack of the task being restored. */ + LDR X0, pxCurrentTCBConst + LDR X1, [X0] + LDR X0, [X1] + MOV SP, X0 + + LDP X2, X3, [SP], #0x10 /* Critical nesting and FPU context. */ + + /* Set the PMR register to be correct for the current critical nesting + depth. */ + LDR X0, ullCriticalNestingConst /* X0 holds the address of ullCriticalNesting. */ + MOV X1, #255 /* X1 holds the unmask value. */ + LDR X4, ullICCPMRConst /* X4 holds the address of the ICCPMR constant. */ + CMP X3, #0 + LDR X5, [X4] /* X5 holds the address of the ICCPMR register. */ + B.EQ 1f + LDR X6, ullMaxAPIPriorityMaskConst + LDR X1, [X6] /* X1 holds the mask value. */ +1: + STR W1, [X5] /* Write the mask value to ICCPMR. */ + DSB SY /* _RB_Barriers probably not required here. */ + ISB SY + STR X3, [X0] /* Restore the task's critical nesting count. */ + + /* Restore the FPU context indicator. */ + LDR X0, ullPortTaskHasFPUContextConst + STR X2, [X0] + + /* Restore the FPU context, if any. */ + CMP X2, #0 + B.EQ 1f + LDP Q30, Q31, [SP], #0x20 + LDP Q28, Q29, [SP], #0x20 + LDP Q26, Q27, [SP], #0x20 + LDP Q24, Q25, [SP], #0x20 + LDP Q22, Q23, [SP], #0x20 + LDP Q20, Q21, [SP], #0x20 + LDP Q18, Q19, [SP], #0x20 + LDP Q16, Q17, [SP], #0x20 + LDP Q14, Q15, [SP], #0x20 + LDP Q12, Q13, [SP], #0x20 + LDP Q10, Q11, [SP], #0x20 + LDP Q8, Q9, [SP], #0x20 + LDP Q6, Q7, [SP], #0x20 + LDP Q4, Q5, [SP], #0x20 + LDP Q2, Q3, [SP], #0x20 + LDP Q0, Q1, [SP], #0x20 +1: + LDP X2, X3, [SP], #0x10 /* SPSR and ELR. */ + +#if defined( GUEST ) + /* Restore the SPSR. */ + MSR SPSR_EL1, X3 + /* Restore the ELR. */ + MSR ELR_EL1, X2 +#else + /* Restore the SPSR. */ + MSR SPSR_EL3, X3 /*_RB_ Assumes started in EL3. */ + /* Restore the ELR. */ + MSR ELR_EL3, X2 +#endif + + LDP X30, XZR, [SP], #0x10 + LDP X28, X29, [SP], #0x10 + LDP X26, X27, [SP], #0x10 + LDP X24, X25, [SP], #0x10 + LDP X22, X23, [SP], #0x10 + LDP X20, X21, [SP], #0x10 + LDP X18, X19, [SP], #0x10 + LDP X16, X17, [SP], #0x10 + LDP X14, X15, [SP], #0x10 + LDP X12, X13, [SP], #0x10 + LDP X10, X11, [SP], #0x10 + LDP X8, X9, [SP], #0x10 + LDP X6, X7, [SP], #0x10 + LDP X4, X5, [SP], #0x10 + LDP X2, X3, [SP], #0x10 + LDP X0, X1, [SP], #0x10 + + /* Switch to use the ELx stack pointer. _RB_ Might not be required. */ + MSR SPSEL, #1 + + ERET + + .endm + + +/****************************************************************************** + * FreeRTOS_SWI_Handler handler is used to perform a context switch. + *****************************************************************************/ +.align 8 +.type FreeRTOS_SWI_Handler, %function +FreeRTOS_SWI_Handler: + /* Save the context of the current task and select a new task to run. */ + portSAVE_CONTEXT +#if defined( GUEST ) + MRS X0, ESR_EL1 +#else + MRS X0, ESR_EL3 +#endif + + LSR X1, X0, #26 + +#if defined( GUEST ) + CMP X1, #0x15 /* 0x15 = SVC instruction. */ +#else + CMP X1, #0x17 /* 0x17 = SMC instruction. */ +#endif + B.NE FreeRTOS_Abort + BL vTaskSwitchContext + + portRESTORE_CONTEXT + +FreeRTOS_Abort: + /* Full ESR is in X0, exception class code is in X1. */ + B . + +/****************************************************************************** + * vPortRestoreTaskContext is used to start the scheduler. + *****************************************************************************/ +.align 8 +.type vPortRestoreTaskContext, %function +vPortRestoreTaskContext: +.set freertos_vector_base, _freertos_vector_table + + /* Install the FreeRTOS interrupt handlers. */ + LDR X1, =freertos_vector_base +#if defined( GUEST ) + MSR VBAR_EL1, X1 +#else + MSR VBAR_EL3, X1 +#endif + DSB SY + ISB SY + + /* Start the first task. */ + portRESTORE_CONTEXT + + +/****************************************************************************** + * FreeRTOS_IRQ_Handler handles IRQ entry and exit. + *****************************************************************************/ +.align 8 +.type FreeRTOS_IRQ_Handler, %function +FreeRTOS_IRQ_Handler: + /* Save volatile registers. */ + STP X0, X1, [SP, #-0x10]! + STP X2, X3, [SP, #-0x10]! + STP X4, X5, [SP, #-0x10]! + STP X6, X7, [SP, #-0x10]! + STP X8, X9, [SP, #-0x10]! + STP X10, X11, [SP, #-0x10]! + STP X12, X13, [SP, #-0x10]! + STP X14, X15, [SP, #-0x10]! + STP X16, X17, [SP, #-0x10]! + STP X18, X19, [SP, #-0x10]! + STP X29, X30, [SP, #-0x10]! + + /* Save the SPSR and ELR. */ +#if defined( GUEST ) + MRS X3, SPSR_EL1 + MRS X2, ELR_EL1 +#else + MRS X3, SPSR_EL3 + MRS X2, ELR_EL3 +#endif + STP X2, X3, [SP, #-0x10]! + + /* Increment the interrupt nesting counter. */ + LDR X5, ullPortInterruptNestingConst + LDR X1, [X5] /* Old nesting count in X1. */ + ADD X6, X1, #1 + STR X6, [X5] /* Address of nesting count variable in X5. */ + + /* Maintain the interrupt nesting information across the function call. */ + STP X1, X5, [SP, #-0x10]! + + /* Read value from the interrupt acknowledge register, which is stored in W0 + for future parameter and interrupt clearing use. */ + LDR X2, ullICCIARConst + LDR X3, [X2] + LDR W0, [X3] /* ICCIAR in W0 as parameter. */ + + /* Maintain the ICCIAR value across the function call. */ + STP X0, X1, [SP, #-0x10]! + + /* Call the C handler. */ + BL vApplicationIRQHandler + + /* Disable interrupts. */ + MSR DAIFSET, #2 + DSB SY + ISB SY + + /* Restore the ICCIAR value. */ + LDP X0, X1, [SP], #0x10 + + /* End IRQ processing by writing ICCIAR to the EOI register. */ + LDR X4, ullICCEOIRConst + LDR X4, [X4] + STR W0, [X4] + + /* Restore the critical nesting count. */ + LDP X1, X5, [SP], #0x10 + STR X1, [X5] + + /* Has interrupt nesting unwound? */ + CMP X1, #0 + B.NE Exit_IRQ_No_Context_Switch + + /* Is a context switch required? */ + LDR X0, ullPortYieldRequiredConst + LDR X1, [X0] + CMP X1, #0 + B.EQ Exit_IRQ_No_Context_Switch + + /* Reset ullPortYieldRequired to 0. */ + MOV X2, #0 + STR X2, [X0] + + /* Restore volatile registers. */ + LDP X4, X5, [SP], #0x10 /* SPSR and ELR. */ +#if defined( GUEST ) + MSR SPSR_EL1, X5 + MSR ELR_EL1, X4 +#else + MSR SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */ + MSR ELR_EL3, X4 +#endif + DSB SY + ISB SY + + LDP X29, X30, [SP], #0x10 + LDP X18, X19, [SP], #0x10 + LDP X16, X17, [SP], #0x10 + LDP X14, X15, [SP], #0x10 + LDP X12, X13, [SP], #0x10 + LDP X10, X11, [SP], #0x10 + LDP X8, X9, [SP], #0x10 + LDP X6, X7, [SP], #0x10 + LDP X4, X5, [SP], #0x10 + LDP X2, X3, [SP], #0x10 + LDP X0, X1, [SP], #0x10 + + /* Save the context of the current task and select a new task to run. */ + portSAVE_CONTEXT + BL vTaskSwitchContext + portRESTORE_CONTEXT + +Exit_IRQ_No_Context_Switch: + /* Restore volatile registers. */ + LDP X4, X5, [SP], #0x10 /* SPSR and ELR. */ +#if defined( GUEST ) + MSR SPSR_EL1, X5 + MSR ELR_EL1, X4 +#else + MSR SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */ + MSR ELR_EL3, X4 +#endif + DSB SY + ISB SY + + LDP X29, X30, [SP], #0x10 + LDP X18, X19, [SP], #0x10 + LDP X16, X17, [SP], #0x10 + LDP X14, X15, [SP], #0x10 + LDP X12, X13, [SP], #0x10 + LDP X10, X11, [SP], #0x10 + LDP X8, X9, [SP], #0x10 + LDP X6, X7, [SP], #0x10 + LDP X4, X5, [SP], #0x10 + LDP X2, X3, [SP], #0x10 + LDP X0, X1, [SP], #0x10 + + ERET + + + + +.align 8 +pxCurrentTCBConst: .dword pxCurrentTCB +ullCriticalNestingConst: .dword ullCriticalNesting +ullPortTaskHasFPUContextConst: .dword ullPortTaskHasFPUContext + +ullICCPMRConst: .dword ullICCPMR +ullMaxAPIPriorityMaskConst: .dword ullMaxAPIPriorityMask +ullPortInterruptNestingConst: .dword ullPortInterruptNesting +ullPortYieldRequiredConst: .dword ullPortYieldRequired +ullICCIARConst: .dword ullICCIAR +ullICCEOIRConst: .dword ullICCEOIR +vApplicationIRQHandlerConst: .word vApplicationIRQHandler + + + +.end diff --git a/portable/GCC/ARM_AARCH64/portmacro.h b/portable/GCC/ARM_AARCH64/portmacro.h new file mode 100644 index 000000000..0091357ee --- /dev/null +++ b/portable/GCC/ARM_AARCH64/portmacro.h @@ -0,0 +1,224 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE size_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef portBASE_TYPE BaseType_t; +typedef uint64_t UBaseType_t; + +typedef uint64_t TickType_t; +#define portMAX_DELAY ( ( TickType_t ) 0xffffffffffffffff ) + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ +#define portTICK_TYPE_IS_ATOMIC 1 + +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 16 +#define portPOINTER_SIZE_TYPE uint64_t + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* Called at the end of an ISR that can cause a context switch. */ +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + { \ + extern uint64_t ullPortYieldRequired; \ + \ + if( xSwitchRequired != pdFALSE ) \ + { \ + ullPortYieldRequired = pdTRUE; \ + } \ + } + +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#if defined( GUEST ) + #define portYIELD() __asm volatile ( "SVC 0" ::: "memory" ) +#else + #define portYIELD() __asm volatile ( "SMC 0" ::: "memory" ) +#endif + +/*----------------------------------------------------------- +* Critical section control +*----------------------------------------------------------*/ + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +extern UBaseType_t uxPortSetInterruptMask( void ); +extern void vPortClearInterruptMask( UBaseType_t uxNewMaskValue ); +extern void vPortInstallFreeRTOSVectorTable( void ); + +#define portDISABLE_INTERRUPTS() \ + __asm volatile ( "MSR DAIFSET, #2" ::: "memory" ); \ + __asm volatile ( "DSB SY" ); \ + __asm volatile ( "ISB SY" ); + +#define portENABLE_INTERRUPTS() \ + __asm volatile ( "MSR DAIFCLR, #2" ::: "memory" ); \ + __asm volatile ( "DSB SY" ); \ + __asm volatile ( "ISB SY" ); + + +/* These macros do not globally disable/enable interrupts. They do mask off + * interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */ +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); +#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortClearInterruptMask( x ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not required for this port but included in case common demo code that uses these + * macros is used. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* Prototype of the FreeRTOS tick handler. This must be installed as the + * handler for whichever peripheral is used to generate the RTOS tick. */ +void FreeRTOS_Tick_Handler( void ); + +/* If configUSE_TASK_FPU_SUPPORT is set to 1 (or left undefined) then tasks are + * created without an FPU context and must call vPortTaskUsesFPU() to give + * themselves an FPU context before using any FPU instructions. If + * configUSE_TASK_FPU_SUPPORT is set to 2 then all tasks will have an FPU context + * by default. */ +#if ( configUSE_TASK_FPU_SUPPORT != 2 ) + void vPortTaskUsesFPU( void ); +#else + /* Each task has an FPU context already, so define this function away to + * nothing to prevent it from being called accidentally. */ + #define vPortTaskUsesFPU() +#endif +#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() + +#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL ) +#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL ) + +/* Architecture specific optimisations. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +#if ( configASSERT_DEFINED == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif /* configASSERT */ + +#define portNOP() __asm volatile ( "NOP" ) +#define portINLINE __inline + +/* The number of bits to shift for an interrupt priority is dependent on the + * number of bits implemented by the interrupt controller. */ +#if configUNIQUE_INTERRUPT_PRIORITIES == 16 + #define portPRIORITY_SHIFT 4 + #define portMAX_BINARY_POINT_VALUE 3 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 32 + #define portPRIORITY_SHIFT 3 + #define portMAX_BINARY_POINT_VALUE 2 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 64 + #define portPRIORITY_SHIFT 2 + #define portMAX_BINARY_POINT_VALUE 1 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 128 + #define portPRIORITY_SHIFT 1 + #define portMAX_BINARY_POINT_VALUE 0 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 256 + #define portPRIORITY_SHIFT 0 + #define portMAX_BINARY_POINT_VALUE 0 +#else /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */ + #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware +#endif /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */ + +/* Interrupt controller access addresses. */ +#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 ) +#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C ) +#define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 ) +#define portICCBPR_BINARY_POINT_OFFSET ( 0x08 ) +#define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 ) + +#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET ) +#define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) ) +#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ) +#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET ) +#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) +#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) ) +#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) ) + +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/ARM_AARCH64_SRE/README.md b/portable/GCC/ARM_AARCH64_SRE/README.md new file mode 100644 index 000000000..129b0e3ec --- /dev/null +++ b/portable/GCC/ARM_AARCH64_SRE/README.md @@ -0,0 +1,23 @@ +# Armv8-A architecture support + +The Armv8-A architecture introduces the ability to use 64-bit and 32-bit +Execution states, known as AArch64 and AArch32 respectively. The AArch64 +Execution state supports the A64 instruction set. It holds addresses in 64-bit +registers and allows instructions in the base instruction set to use 64-bit +registers for their processing. + +The AArch32 Execution state is a 32-bit Execution state that preserves +backwards compatibility with the Armv7-A architecture, enhancing that profile +so that it can support some features included in the AArch64 state. It supports +the T32 and A32 instruction sets. Follow the +[link](https://developer.arm.com/Architectures/A-Profile%20Architecture) +for more information. + +## ARM_AARCH64_SRE port + +This port adds support for Armv8-A architecture AArch64 execution state. +This port is generic and can be used as a starting point for Armv8-A +application processors. + +* ARM_AARCH64_SRE + * System Register interface to access Arm GIC registers diff --git a/portable/GCC/ARM_AARCH64_SRE/port.c b/portable/GCC/ARM_AARCH64_SRE/port.c new file mode 100644 index 000000000..ab9290d43 --- /dev/null +++ b/portable/GCC/ARM_AARCH64_SRE/port.c @@ -0,0 +1,524 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#ifndef configUNIQUE_INTERRUPT_PRIORITIES + #error "configUNIQUE_INTERRUPT_PRIORITIES must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" +#endif + +#ifndef configSETUP_TICK_INTERRUPT + #error "configSETUP_TICK_INTERRUPT() must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" +#endif /* configSETUP_TICK_INTERRUPT */ + +#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" +#endif + +#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0 + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0" +#endif + +#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority" +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + /* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice." + #endif +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/* In case security extensions are implemented. */ +#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 ) + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )" +#endif + +/* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in + * portmacro.h. */ +#ifndef configCLEAR_TICK_INTERRUPT + #define configCLEAR_TICK_INTERRUPT() +#endif + +/* A critical section is exited when the critical section nesting count reaches + * this value. */ +#define portNO_CRITICAL_NESTING ( ( size_t ) 0 ) + +/* In all GICs 255 can be written to the priority mask register to unmask all + * (but the lowest) interrupt priority. */ +#define portUNMASK_VALUE ( 0xFFUL ) + +/* Tasks are not created with a floating point context, but can be given a + * floating point context after they have been created. A variable is stored as + * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task + * does not have an FPU context, or any other value if the task does have an FPU + * context. */ +#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) + +/* Constants required to setup the initial task context. */ +#define portSP_ELx ( ( StackType_t ) 0x01 ) +#define portSP_EL0 ( ( StackType_t ) 0x00 ) + +#if defined( GUEST ) + #define portEL1 ( ( StackType_t ) 0x04 ) + #define portINITIAL_PSTATE ( portEL1 | portSP_EL0 ) +#else + #define portEL3 ( ( StackType_t ) 0x0c ) + /* At the time of writing, the BSP only supports EL3. */ + #define portINITIAL_PSTATE ( portEL3 | portSP_EL0 ) +#endif + +/* Masks all bits in the APSR other than the mode bits. */ +#define portAPSR_MODE_BITS_MASK ( 0x0C ) + +/* The I bit in the DAIF bits. */ +#define portDAIF_I ( 0x80 ) + +/* Macro to unmask all interrupt priorities. */ +/* s3_0_c4_c6_0 is ICC_PMR_EL1. */ +#define portCLEAR_INTERRUPT_MASK() \ + { \ + __asm volatile ( "MSR DAIFSET, #2 \n" \ + "DSB SY \n" \ + "ISB SY \n" \ + "MSR s3_0_c4_c6_0, %0 \n" \ + "DSB SY \n" \ + "ISB SY \n" \ + "MSR DAIFCLR, #2 \n" \ + "DSB SY \n" \ + "ISB SY \n" \ + ::"r" ( portUNMASK_VALUE ) ); \ + } + +/* The space on the stack required to hold the FPU registers. + * There are 32 128-bit plus 2 64-bit status registers.*/ +#define portFPU_REGISTER_WORDS ( (32 * 2) + 2 ) + +/*-----------------------------------------------------------*/ + +/* + * Starts the first task executing. This function is necessarily written in + * assembly code so is implemented in portASM.s. + */ +extern void vPortRestoreTaskContext( void ); + +/* + * If the application provides an implementation of vApplicationIRQHandler(), + * then it will get called directly without saving the FPU registers on + * interrupt entry, and this weak implementation of + * vApplicationFPUSafeIRQHandler() is just provided to remove linkage errors - + * it should never actually get called so its implementation contains a + * call to configASSERT() that will always fail. + * + * If the application provides its own implementation of + * vApplicationFPUSafeIRQHandler() then the implementation of + * vApplicationIRQHandler() provided in portASM.S will save the FPU registers + * before calling it. + * + * Therefore, if the application writer wants FPU registers to be saved on + * interrupt entry their IRQ handler must be called + * vApplicationFPUSafeIRQHandler(), and if the application writer does not want + * FPU registers to be saved on interrupt entry their IRQ handler must be + * called vApplicationIRQHandler(). + */ +void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR ) __attribute__((weak) ); + +/*-----------------------------------------------------------*/ + +/* A variable is used to keep track of the critical section nesting. This + * variable has to be stored as part of the task context and must be initialised to + * a non zero value to ensure interrupts don't inadvertently become unmasked before + * the scheduler starts. As it is stored as part of the task context it will + * automatically be set to 0 when the first task is started. */ +volatile uint64_t ullCriticalNesting = 9999ULL; + +/* Saved as part of the task context. If ullPortTaskHasFPUContext is non-zero + * then floating point context must be saved and restored for the task. */ +uint64_t ullPortTaskHasFPUContext = pdFALSE; + +/* Set to 1 to pend a context switch from an ISR. */ +uint64_t ullPortYieldRequired = pdFALSE; + +/* Counts the interrupt nesting depth. A context switch is only performed if + * if the nesting depth is 0. */ +uint64_t ullPortInterruptNesting = 0; + +/* Used in the ASM code. */ +__attribute__( ( used ) ) const uint64_t ullMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Setup the initial stack of the task. The stack is set exactly as + * expected by the portRESTORE_CONTEXT() macro. */ + + /* First all the general purpose registers. */ + pxTopOfStack--; + *pxTopOfStack = 0x0101010101010101ULL; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + *pxTopOfStack = 0x0303030303030303ULL; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = 0x0202020202020202ULL; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = 0x0505050505050505ULL; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = 0x0404040404040404ULL; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = 0x0707070707070707ULL; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = 0x0606060606060606ULL; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = 0x0909090909090909ULL; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = 0x0808080808080808ULL; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = 0x1111111111111111ULL; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = 0x1010101010101010ULL; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = 0x1313131313131313ULL; /* R13 */ + pxTopOfStack--; + *pxTopOfStack = 0x1212121212121212ULL; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = 0x1515151515151515ULL; /* R15 */ + pxTopOfStack--; + *pxTopOfStack = 0x1414141414141414ULL; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = 0x1717171717171717ULL; /* R17 */ + pxTopOfStack--; + *pxTopOfStack = 0x1616161616161616ULL; /* R16 */ + pxTopOfStack--; + *pxTopOfStack = 0x1919191919191919ULL; /* R19 */ + pxTopOfStack--; + *pxTopOfStack = 0x1818181818181818ULL; /* R18 */ + pxTopOfStack--; + *pxTopOfStack = 0x2121212121212121ULL; /* R21 */ + pxTopOfStack--; + *pxTopOfStack = 0x2020202020202020ULL; /* R20 */ + pxTopOfStack--; + *pxTopOfStack = 0x2323232323232323ULL; /* R23 */ + pxTopOfStack--; + *pxTopOfStack = 0x2222222222222222ULL; /* R22 */ + pxTopOfStack--; + *pxTopOfStack = 0x2525252525252525ULL; /* R25 */ + pxTopOfStack--; + *pxTopOfStack = 0x2424242424242424ULL; /* R24 */ + pxTopOfStack--; + *pxTopOfStack = 0x2727272727272727ULL; /* R27 */ + pxTopOfStack--; + *pxTopOfStack = 0x2626262626262626ULL; /* R26 */ + pxTopOfStack--; + *pxTopOfStack = 0x2929292929292929ULL; /* R29 */ + pxTopOfStack--; + *pxTopOfStack = 0x2828282828282828ULL; /* R28 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x00; /* XZR - has no effect, used so there are an even number of registers. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x00; /* R30 - procedure call link register. */ + + pxTopOfStack--; + *pxTopOfStack = portINITIAL_PSTATE; + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* Exception return address. */ + + #if ( configUSE_TASK_FPU_SUPPORT == 1 ) + { + /* The task will start with a critical nesting count of 0 as interrupts are + * enabled. */ + pxTopOfStack--; + *pxTopOfStack = portNO_CRITICAL_NESTING; + + /* The task will start without a floating point context. A task that + * uses the floating point hardware must call vPortTaskUsesFPU() before + * executing any floating point instructions. */ + pxTopOfStack--; + *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT; + } + #elif ( configUSE_TASK_FPU_SUPPORT == 2 ) + { + /* The task will start with a floating point context. Leave enough + * space for the registers - and ensure they are initialised to 0. */ + pxTopOfStack -= portFPU_REGISTER_WORDS; + memset( pxTopOfStack, 0x00, portFPU_REGISTER_WORDS * sizeof( StackType_t ) ); + + /* The task will start with a critical nesting count of 0 as interrupts are + * enabled. */ + pxTopOfStack--; + *pxTopOfStack = portNO_CRITICAL_NESTING; + + pxTopOfStack--; + *pxTopOfStack = pdTRUE; + ullPortTaskHasFPUContext = pdTRUE; + } + #else /* if ( configUSE_TASK_FPU_SUPPORT == 1 ) */ + { + #error "Invalid configUSE_TASK_FPU_SUPPORT setting - configUSE_TASK_FPU_SUPPORT must be set to 1, 2, or left undefined." + } + #endif /* if ( configUSE_TASK_FPU_SUPPORT == 1 ) */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + uint32_t ulAPSR; + + __asm volatile ( "MRS %0, CurrentEL" : "=r" ( ulAPSR ) ); + + ulAPSR &= portAPSR_MODE_BITS_MASK; + + #if defined( GUEST ) + configASSERT( ulAPSR == portEL1 ); + + if( ulAPSR == portEL1 ) + #else + configASSERT( ulAPSR == portEL3 ); + + if( ulAPSR == portEL3 ) + #endif + { + /* Interrupts are turned off in the CPU itself to ensure a tick does + * not execute while the scheduler is being started. Interrupts are + * automatically turned back on in the CPU when the first task starts + * executing. */ + portDISABLE_INTERRUPTS(); + + /* Start the timer that generates the tick ISR. */ + configSETUP_TICK_INTERRUPT(); + + /* Start the first task executing. */ + vPortRestoreTaskContext(); + } + + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ullCriticalNesting == 1000ULL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + /* Mask interrupts up to the max syscall interrupt priority. */ + uxPortSetInterruptMask(); + + /* Now interrupts are disabled ullCriticalNesting can be accessed + * directly. Increment ullCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ + ullCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ + if( ullCriticalNesting == 1ULL ) + { + configASSERT( ullPortInterruptNesting == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + if( ullCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as the critical section is being + * exited. */ + ullCriticalNesting--; + + /* If the nesting level has reached zero then all interrupt + * priorities must be re-enabled. */ + if( ullCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Critical nesting has reached zero so all interrupt priorities + * should be unmasked. */ + portCLEAR_INTERRUPT_MASK(); + } + } +} +/*-----------------------------------------------------------*/ + +void FreeRTOS_Tick_Handler( void ) +{ + /* Must be the lowest possible priority. */ + #if !defined( QEMU ) + { + uint64_t ullRunningInterruptPriority; + /* s3_0_c12_c11_3 is ICC_RPR_EL1. */ + __asm volatile ( "MRS %0, s3_0_c12_c11_3" : "=r" ( ullRunningInterruptPriority ) ); + configASSERT( ullRunningInterruptPriority == ( portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ); + } + #endif + + /* Interrupts should not be enabled before this point. */ + #if ( configASSERT_DEFINED == 1 ) + { + uint32_t ulMaskBits; + + __asm volatile ( "MRS %0, DAIF" : "=r" ( ulMaskBits )::"memory" ); + configASSERT( ( ulMaskBits & portDAIF_I ) != 0 ); + } + #endif /* configASSERT_DEFINED */ + + /* Set interrupt mask before altering scheduler structures. The tick + * handler runs at the lowest priority, so interrupts cannot already be masked, + * so there is no need to save and restore the current mask value. It is + * necessary to turn off interrupts in the CPU itself while the ICCPMR is being + * updated. */ + /* s3_0_c4_c6_0 is ICC_PMR_EL1. */ + __asm volatile ( "MSR s3_0_c4_c6_0, %0 \n" + "DSB SY \n" + "ISB SY \n" + ::"r" ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) : "memory" ); + + /* Ok to enable interrupts after the interrupt source has been cleared. */ + configCLEAR_TICK_INTERRUPT(); + portENABLE_INTERRUPTS(); + + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + ullPortYieldRequired = pdTRUE; + } + + /* Ensure all interrupt priorities are active again. */ + portCLEAR_INTERRUPT_MASK(); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_FPU_SUPPORT != 2 ) + +void vPortTaskUsesFPU( void ) +{ + /* A task is registering the fact that it needs an FPU context. Set the + * FPU flag (which is saved as part of the task context). */ + ullPortTaskHasFPUContext = pdTRUE; + + /* Consider initialising the FPSR here - but probably not necessary in + * AArch64. */ +} + +#endif /* configUSE_TASK_FPU_SUPPORT */ +/*-----------------------------------------------------------*/ + +void vPortClearInterruptMask( UBaseType_t uxNewMaskValue ) +{ + if( uxNewMaskValue == pdFALSE ) + { + portCLEAR_INTERRUPT_MASK(); + } +} +/*-----------------------------------------------------------*/ + +UBaseType_t uxPortSetInterruptMask( void ) +{ + uint32_t ulReturn; + uint64_t ullPMRValue; + + /* Interrupt in the CPU must be turned off while the ICCPMR is being + * updated. */ + portDISABLE_INTERRUPTS(); + /* s3_0_c4_c6_0 is ICC_PMR_EL1. */ + __asm volatile ( "MRS %0, s3_0_c4_c6_0" : "=r" ( ullPMRValue ) ); + + if( ullPMRValue == ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ) + { + /* Interrupts were already masked. */ + ulReturn = pdTRUE; + } + else + { + ulReturn = pdFALSE; + /* s3_0_c4_c6_0 is ICC_PMR_EL1. */ + __asm volatile ( "MSR s3_0_c4_c6_0, %0 \n" + "DSB SY \n" + "ISB SY \n" + ::"r" ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) : "memory" ); + } + + portENABLE_INTERRUPTS(); + + return ulReturn; +} +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. */ + uint64_t ullRunningInterruptPriority; + /* s3_0_c12_c11_3 is ICC_RPR_EL1. */ + __asm volatile ( "MRS %0, s3_0_c12_c11_3" : "=r" ( ullRunningInterruptPriority ) ); + + configASSERT( ullRunningInterruptPriority >= ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ); + } + +#endif /* configASSERT_DEFINED */ +/*-----------------------------------------------------------*/ + +void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR ) +{ + ( void ) ulICCIAR; + configASSERT( ( volatile void * ) NULL ); +} diff --git a/portable/GCC/ARM_AARCH64_SRE/portASM.S b/portable/GCC/ARM_AARCH64_SRE/portASM.S new file mode 100644 index 000000000..f1f59cd33 --- /dev/null +++ b/portable/GCC/ARM_AARCH64_SRE/portASM.S @@ -0,0 +1,503 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + .text + + /* Variables and functions. */ + .extern ullMaxAPIPriorityMask + .extern pxCurrentTCB + .extern vTaskSwitchContext + .extern vApplicationIRQHandler + .extern ullPortInterruptNesting + .extern ullPortTaskHasFPUContext + .extern ullCriticalNesting + .extern ullPortYieldRequired + .extern _freertos_vector_table + + .global FreeRTOS_IRQ_Handler + .global FreeRTOS_SWI_Handler + .global vPortRestoreTaskContext + + +.macro portSAVE_CONTEXT + + /* Switch to use the EL0 stack pointer. */ + MSR SPSEL, #0 + + /* Save the entire context. */ + STP X0, X1, [SP, #-0x10]! + STP X2, X3, [SP, #-0x10]! + STP X4, X5, [SP, #-0x10]! + STP X6, X7, [SP, #-0x10]! + STP X8, X9, [SP, #-0x10]! + STP X10, X11, [SP, #-0x10]! + STP X12, X13, [SP, #-0x10]! + STP X14, X15, [SP, #-0x10]! + STP X16, X17, [SP, #-0x10]! + STP X18, X19, [SP, #-0x10]! + STP X20, X21, [SP, #-0x10]! + STP X22, X23, [SP, #-0x10]! + STP X24, X25, [SP, #-0x10]! + STP X26, X27, [SP, #-0x10]! + STP X28, X29, [SP, #-0x10]! + STP X30, XZR, [SP, #-0x10]! + + /* Save the SPSR. */ +#if defined( GUEST ) + MRS X3, SPSR_EL1 + MRS X2, ELR_EL1 +#else + MRS X3, SPSR_EL3 + /* Save the ELR. */ + MRS X2, ELR_EL3 +#endif + + STP X2, X3, [SP, #-0x10]! + + /* Save the critical section nesting depth. */ + LDR X0, ullCriticalNestingConst + LDR X3, [X0] + + /* Save the FPU context indicator. */ + LDR X0, ullPortTaskHasFPUContextConst + LDR X2, [X0] + + /* Save the FPU context, if any (32 128-bit plus two 64-bit status registers). */ + CMP X2, #0 + B.EQ 1f + STP Q0, Q1, [SP,#-0x20]! + STP Q2, Q3, [SP,#-0x20]! + STP Q4, Q5, [SP,#-0x20]! + STP Q6, Q7, [SP,#-0x20]! + STP Q8, Q9, [SP,#-0x20]! + STP Q10, Q11, [SP,#-0x20]! + STP Q12, Q13, [SP,#-0x20]! + STP Q14, Q15, [SP,#-0x20]! + STP Q16, Q17, [SP,#-0x20]! + STP Q18, Q19, [SP,#-0x20]! + STP Q20, Q21, [SP,#-0x20]! + STP Q22, Q23, [SP,#-0x20]! + STP Q24, Q25, [SP,#-0x20]! + STP Q26, Q27, [SP,#-0x20]! + STP Q28, Q29, [SP,#-0x20]! + STP Q30, Q31, [SP,#-0x20]! + + /* Even though upper 32 bits of FPSR and FPCR are reserved, save and restore the whole 64 bits to keep 16-byte SP alignement. */ + MRS X9, FPSR + MRS X10, FPCR + STP X9, X10, [SP, #-0x10]! + +1: + /* Store the critical nesting count and FPU context indicator. */ + STP X2, X3, [SP, #-0x10]! + + LDR X0, pxCurrentTCBConst + LDR X1, [X0] + MOV X0, SP /* Move SP into X0 for saving. */ + STR X0, [X1] + + /* Switch to use the ELx stack pointer. */ + MSR SPSEL, #1 + + .endm + +; /**********************************************************************/ + +.macro portRESTORE_CONTEXT + + /* Switch to use the EL0 stack pointer. */ + MSR SPSEL, #0 + + /* Set the SP to point to the stack of the task being restored. */ + LDR X0, pxCurrentTCBConst + LDR X1, [X0] + LDR X0, [X1] + MOV SP, X0 + + LDP X2, X3, [SP], #0x10 /* Critical nesting and FPU context. */ + + /* Set the PMR register to be correct for the current critical nesting + depth. */ + LDR X0, ullCriticalNestingConst /* X0 holds the address of ullCriticalNesting. */ + MOV X1, #255 /* X1 holds the unmask value. */ + CMP X3, #0 + B.EQ 1f + LDR X6, ullMaxAPIPriorityMaskConst + LDR X1, [X6] /* X1 holds the mask value. */ +1: + MSR s3_0_c4_c6_0, X1 /* Write the mask value to ICCPMR. s3_0_c4_c6_0 is ICC_PMR_EL1. */ + DSB SY /* _RB_Barriers probably not required here. */ + ISB SY + STR X3, [X0] /* Restore the task's critical nesting count. */ + + /* Restore the FPU context indicator. */ + LDR X0, ullPortTaskHasFPUContextConst + STR X2, [X0] + + /* Restore the FPU context, if any. */ + CMP X2, #0 + B.EQ 1f + LDP X9, X10, [SP], #0x10 + LDP Q30, Q31, [SP], #0x20 + LDP Q28, Q29, [SP], #0x20 + LDP Q26, Q27, [SP], #0x20 + LDP Q24, Q25, [SP], #0x20 + LDP Q22, Q23, [SP], #0x20 + LDP Q20, Q21, [SP], #0x20 + LDP Q18, Q19, [SP], #0x20 + LDP Q16, Q17, [SP], #0x20 + LDP Q14, Q15, [SP], #0x20 + LDP Q12, Q13, [SP], #0x20 + LDP Q10, Q11, [SP], #0x20 + LDP Q8, Q9, [SP], #0x20 + LDP Q6, Q7, [SP], #0x20 + LDP Q4, Q5, [SP], #0x20 + LDP Q2, Q3, [SP], #0x20 + LDP Q0, Q1, [SP], #0x20 + MSR FPSR, X9 + MSR FPCR, X10 +1: + LDP X2, X3, [SP], #0x10 /* SPSR and ELR. */ + +#if defined( GUEST ) + /* Restore the SPSR. */ + MSR SPSR_EL1, X3 + /* Restore the ELR. */ + MSR ELR_EL1, X2 +#else + /* Restore the SPSR. */ + MSR SPSR_EL3, X3 /*_RB_ Assumes started in EL3. */ + /* Restore the ELR. */ + MSR ELR_EL3, X2 +#endif + + LDP X30, XZR, [SP], #0x10 + LDP X28, X29, [SP], #0x10 + LDP X26, X27, [SP], #0x10 + LDP X24, X25, [SP], #0x10 + LDP X22, X23, [SP], #0x10 + LDP X20, X21, [SP], #0x10 + LDP X18, X19, [SP], #0x10 + LDP X16, X17, [SP], #0x10 + LDP X14, X15, [SP], #0x10 + LDP X12, X13, [SP], #0x10 + LDP X10, X11, [SP], #0x10 + LDP X8, X9, [SP], #0x10 + LDP X6, X7, [SP], #0x10 + LDP X4, X5, [SP], #0x10 + LDP X2, X3, [SP], #0x10 + LDP X0, X1, [SP], #0x10 + + /* Switch to use the ELx stack pointer. _RB_ Might not be required. */ + MSR SPSEL, #1 + + ERET + + .endm + + +/****************************************************************************** + * FreeRTOS_SWI_Handler handler is used to perform a context switch. + *****************************************************************************/ +.align 8 +.type FreeRTOS_SWI_Handler, %function +FreeRTOS_SWI_Handler: + /* Save the context of the current task and select a new task to run. */ + portSAVE_CONTEXT +#if defined( GUEST ) + MRS X0, ESR_EL1 +#else + MRS X0, ESR_EL3 +#endif + + LSR X1, X0, #26 + +#if defined( GUEST ) + CMP X1, #0x15 /* 0x15 = SVC instruction. */ +#else + CMP X1, #0x17 /* 0x17 = SMC instruction. */ +#endif + B.NE FreeRTOS_Abort + BL vTaskSwitchContext + + portRESTORE_CONTEXT + +FreeRTOS_Abort: + /* Full ESR is in X0, exception class code is in X1. */ + B . + +/****************************************************************************** + * vPortRestoreTaskContext is used to start the scheduler. + *****************************************************************************/ +.align 8 +.type vPortRestoreTaskContext, %function +vPortRestoreTaskContext: +.set freertos_vector_base, _freertos_vector_table + + /* Install the FreeRTOS interrupt handlers. */ + LDR X1, =freertos_vector_base +#if defined( GUEST ) + MSR VBAR_EL1, X1 +#else + MSR VBAR_EL3, X1 +#endif + DSB SY + ISB SY + + /* Start the first task. */ + portRESTORE_CONTEXT + + +/****************************************************************************** + * FreeRTOS_IRQ_Handler handles IRQ entry and exit. + + * This handler is supposed to be used only for IRQs and never for FIQs. Per ARM + * GIC documentation [1], Group 0 interrupts are always signaled as FIQs. Since + * this handler is only for IRQs, We can safely assume Group 1 while accessing + * Interrupt Acknowledge and End Of Interrupt registers and therefore, use + * ICC_IAR1_EL1 and ICC_EOIR1_EL1. + * + * [1] https://developer.arm.com/documentation/198123/0300/Arm-CoreLink-GIC-fundamentals + *****************************************************************************/ +.align 8 +.type FreeRTOS_IRQ_Handler, %function +FreeRTOS_IRQ_Handler: + /* Save volatile registers. */ + STP X0, X1, [SP, #-0x10]! + STP X2, X3, [SP, #-0x10]! + STP X4, X5, [SP, #-0x10]! + STP X6, X7, [SP, #-0x10]! + STP X8, X9, [SP, #-0x10]! + STP X10, X11, [SP, #-0x10]! + STP X12, X13, [SP, #-0x10]! + STP X14, X15, [SP, #-0x10]! + STP X16, X17, [SP, #-0x10]! + STP X18, X19, [SP, #-0x10]! + STP X29, X30, [SP, #-0x10]! + + /* Save the SPSR and ELR. */ +#if defined( GUEST ) + MRS X3, SPSR_EL1 + MRS X2, ELR_EL1 +#else + MRS X3, SPSR_EL3 + MRS X2, ELR_EL3 +#endif + STP X2, X3, [SP, #-0x10]! + + /* Increment the interrupt nesting counter. */ + LDR X5, ullPortInterruptNestingConst + LDR X1, [X5] /* Old nesting count in X1. */ + ADD X6, X1, #1 + STR X6, [X5] /* Address of nesting count variable in X5. */ + + /* Maintain the interrupt nesting information across the function call. */ + STP X1, X5, [SP, #-0x10]! + + /* Read interrupt ID from the interrupt acknowledge register and store it + in X0 for future parameter and interrupt clearing use. */ + MRS X0, S3_0_C12_C12_0 /* S3_0_C12_C12_0 is ICC_IAR1_EL1. */ + + /* Maintain the interrupt ID value across the function call. */ + STP X0, X1, [SP, #-0x10]! + + /* Call the C handler. */ + BL vApplicationIRQHandler + + /* Disable interrupts. */ + MSR DAIFSET, #2 + DSB SY + ISB SY + + /* Restore the interrupt ID value. */ + LDP X0, X1, [SP], #0x10 + + /* End IRQ processing by writing interrupt ID value to the EOI register. */ + MSR S3_0_C12_C12_1, X0 /* S3_0_C12_C12_1 is ICC_EOIR1_EL1. */ + + /* Restore the critical nesting count. */ + LDP X1, X5, [SP], #0x10 + STR X1, [X5] + + /* Has interrupt nesting unwound? */ + CMP X1, #0 + B.NE Exit_IRQ_No_Context_Switch + + /* Is a context switch required? */ + LDR X0, ullPortYieldRequiredConst + LDR X1, [X0] + CMP X1, #0 + B.EQ Exit_IRQ_No_Context_Switch + + /* Reset ullPortYieldRequired to 0. */ + MOV X2, #0 + STR X2, [X0] + + /* Restore volatile registers. */ + LDP X4, X5, [SP], #0x10 /* SPSR and ELR. */ +#if defined( GUEST ) + MSR SPSR_EL1, X5 + MSR ELR_EL1, X4 +#else + MSR SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */ + MSR ELR_EL3, X4 +#endif + DSB SY + ISB SY + + LDP X29, X30, [SP], #0x10 + LDP X18, X19, [SP], #0x10 + LDP X16, X17, [SP], #0x10 + LDP X14, X15, [SP], #0x10 + LDP X12, X13, [SP], #0x10 + LDP X10, X11, [SP], #0x10 + LDP X8, X9, [SP], #0x10 + LDP X6, X7, [SP], #0x10 + LDP X4, X5, [SP], #0x10 + LDP X2, X3, [SP], #0x10 + LDP X0, X1, [SP], #0x10 + + /* Save the context of the current task and select a new task to run. */ + portSAVE_CONTEXT + BL vTaskSwitchContext + portRESTORE_CONTEXT + +Exit_IRQ_No_Context_Switch: + /* Restore volatile registers. */ + LDP X4, X5, [SP], #0x10 /* SPSR and ELR. */ +#if defined( GUEST ) + MSR SPSR_EL1, X5 + MSR ELR_EL1, X4 +#else + MSR SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */ + MSR ELR_EL3, X4 +#endif + DSB SY + ISB SY + + LDP X29, X30, [SP], #0x10 + LDP X18, X19, [SP], #0x10 + LDP X16, X17, [SP], #0x10 + LDP X14, X15, [SP], #0x10 + LDP X12, X13, [SP], #0x10 + LDP X10, X11, [SP], #0x10 + LDP X8, X9, [SP], #0x10 + LDP X6, X7, [SP], #0x10 + LDP X4, X5, [SP], #0x10 + LDP X2, X3, [SP], #0x10 + LDP X0, X1, [SP], #0x10 + + ERET + +/****************************************************************************** + * If the application provides an implementation of vApplicationIRQHandler(), + * then it will get called directly without saving the FPU registers on + * interrupt entry, and this weak implementation of + * vApplicationIRQHandler() will not get called. + * + * If the application provides its own implementation of + * vApplicationFPUSafeIRQHandler() then this implementation of + * vApplicationIRQHandler() will be called, save the FPU registers, and then + * call vApplicationFPUSafeIRQHandler(). + * + * Therefore, if the application writer wants FPU registers to be saved on + * interrupt entry their IRQ handler must be called + * vApplicationFPUSafeIRQHandler(), and if the application writer does not want + * FPU registers to be saved on interrupt entry their IRQ handler must be + * called vApplicationIRQHandler(). + *****************************************************************************/ + +.align 8 +.weak vApplicationIRQHandler +.type vApplicationIRQHandler, %function +vApplicationIRQHandler: + /* Save LR and FP on the stack */ + STP X29, X30, [SP, #-0x10]! + + /* Save FPU registers (32 128-bits + 2 64-bits configuration and status registers) */ + STP Q0, Q1, [SP,#-0x20]! + STP Q2, Q3, [SP,#-0x20]! + STP Q4, Q5, [SP,#-0x20]! + STP Q6, Q7, [SP,#-0x20]! + STP Q8, Q9, [SP,#-0x20]! + STP Q10, Q11, [SP,#-0x20]! + STP Q12, Q13, [SP,#-0x20]! + STP Q14, Q15, [SP,#-0x20]! + STP Q16, Q17, [SP,#-0x20]! + STP Q18, Q19, [SP,#-0x20]! + STP Q20, Q21, [SP,#-0x20]! + STP Q22, Q23, [SP,#-0x20]! + STP Q24, Q25, [SP,#-0x20]! + STP Q26, Q27, [SP,#-0x20]! + STP Q28, Q29, [SP,#-0x20]! + STP Q30, Q31, [SP,#-0x20]! + + /* Even though upper 32 bits of FPSR and FPCR are reserved, save and restore the whole 64 bits to keep 16-byte SP alignement. */ + MRS X9, FPSR + MRS X10, FPCR + STP X9, X10, [SP, #-0x10]! + + /* Call the C handler. */ + BL vApplicationFPUSafeIRQHandler + + /* Restore FPU registers */ + + LDP X9, X10, [SP], #0x10 + LDP Q30, Q31, [SP], #0x20 + LDP Q28, Q29, [SP], #0x20 + LDP Q26, Q27, [SP], #0x20 + LDP Q24, Q25, [SP], #0x20 + LDP Q22, Q23, [SP], #0x20 + LDP Q20, Q21, [SP], #0x20 + LDP Q18, Q19, [SP], #0x20 + LDP Q16, Q17, [SP], #0x20 + LDP Q14, Q15, [SP], #0x20 + LDP Q12, Q13, [SP], #0x20 + LDP Q10, Q11, [SP], #0x20 + LDP Q8, Q9, [SP], #0x20 + LDP Q6, Q7, [SP], #0x20 + LDP Q4, Q5, [SP], #0x20 + LDP Q2, Q3, [SP], #0x20 + LDP Q0, Q1, [SP], #0x20 + MSR FPSR, X9 + MSR FPCR, X10 + + /* Restore FP and LR */ + LDP X29, X30, [SP], #0x10 + RET + +.align 8 +pxCurrentTCBConst: .dword pxCurrentTCB +ullCriticalNestingConst: .dword ullCriticalNesting +ullPortTaskHasFPUContextConst: .dword ullPortTaskHasFPUContext + +ullMaxAPIPriorityMaskConst: .dword ullMaxAPIPriorityMask +ullPortInterruptNestingConst: .dword ullPortInterruptNesting +ullPortYieldRequiredConst: .dword ullPortYieldRequired + +.end diff --git a/portable/GCC/ARM_AARCH64_SRE/portmacro.h b/portable/GCC/ARM_AARCH64_SRE/portmacro.h new file mode 100644 index 000000000..5810741d2 --- /dev/null +++ b/portable/GCC/ARM_AARCH64_SRE/portmacro.h @@ -0,0 +1,209 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE size_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef portBASE_TYPE BaseType_t; +typedef uint64_t UBaseType_t; + +typedef uint64_t TickType_t; +#define portMAX_DELAY ( ( TickType_t ) 0xffffffffffffffff ) + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ +#define portTICK_TYPE_IS_ATOMIC 1 + +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 16 +#define portPOINTER_SIZE_TYPE uint64_t + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* Called at the end of an ISR that can cause a context switch. */ +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + { \ + extern uint64_t ullPortYieldRequired; \ + \ + if( xSwitchRequired != pdFALSE ) \ + { \ + ullPortYieldRequired = pdTRUE; \ + } \ + } + +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#if defined( GUEST ) + #define portYIELD() __asm volatile ( "SVC 0" ::: "memory" ) +#else + #define portYIELD() __asm volatile ( "SMC 0" ::: "memory" ) +#endif + +/*----------------------------------------------------------- +* Critical section control +*----------------------------------------------------------*/ + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +extern UBaseType_t uxPortSetInterruptMask( void ); +extern void vPortClearInterruptMask( UBaseType_t uxNewMaskValue ); +extern void vPortInstallFreeRTOSVectorTable( void ); + +#define portDISABLE_INTERRUPTS() \ + __asm volatile ( "MSR DAIFSET, #2" ::: "memory" ); \ + __asm volatile ( "DSB SY" ); \ + __asm volatile ( "ISB SY" ); + +#define portENABLE_INTERRUPTS() \ + __asm volatile ( "MSR DAIFCLR, #2" ::: "memory" ); \ + __asm volatile ( "DSB SY" ); \ + __asm volatile ( "ISB SY" ); + + +/* These macros do not globally disable/enable interrupts. They do mask off + * interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */ +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); +#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortClearInterruptMask( x ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not required for this port but included in case common demo code that uses these + * macros is used. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* Prototype of the FreeRTOS tick handler. This must be installed as the + * handler for whichever peripheral is used to generate the RTOS tick. */ +void FreeRTOS_Tick_Handler( void ); + +/* If configUSE_TASK_FPU_SUPPORT is set to 1 (or left undefined) then tasks are + * created without an FPU context and must call vPortTaskUsesFPU() to give + * themselves an FPU context before using any FPU instructions. If + * configUSE_TASK_FPU_SUPPORT is set to 2 then all tasks will have an FPU context + * by default. */ +#if ( configUSE_TASK_FPU_SUPPORT != 2 ) + void vPortTaskUsesFPU( void ); +#else + /* Each task has an FPU context already, so define this function away to + * nothing to prevent it from being called accidentally. */ + #define vPortTaskUsesFPU() +#endif +#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() + +#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL ) +#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL ) + +/* Architecture specific optimisations. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +#if ( configASSERT_DEFINED == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif /* configASSERT */ + +#define portNOP() __asm volatile ( "NOP" ) +#define portINLINE __inline + +/* The number of bits to shift for an interrupt priority is dependent on the + * number of bits implemented by the interrupt controller. */ +#if configUNIQUE_INTERRUPT_PRIORITIES == 16 + #define portPRIORITY_SHIFT 4 + #define portMAX_BINARY_POINT_VALUE 3 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 32 + #define portPRIORITY_SHIFT 3 + #define portMAX_BINARY_POINT_VALUE 2 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 64 + #define portPRIORITY_SHIFT 2 + #define portMAX_BINARY_POINT_VALUE 1 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 128 + #define portPRIORITY_SHIFT 1 + #define portMAX_BINARY_POINT_VALUE 0 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 256 + #define portPRIORITY_SHIFT 0 + #define portMAX_BINARY_POINT_VALUE 0 +#else /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */ + #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware +#endif /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */ + +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/ARM_CA53_64_BIT/README.md b/portable/GCC/ARM_CA53_64_BIT/README.md new file mode 100644 index 000000000..578b475d9 --- /dev/null +++ b/portable/GCC/ARM_CA53_64_BIT/README.md @@ -0,0 +1,16 @@ +# ARM_CA53_64_BIT port + +Initial port to support Armv8-A architecture in FreeRTOS kernel was written for +Arm Cortex-A53 processor. + +* ARM_CA53_64_BIT + * Memory mapped interface to access Arm GIC registers + +This port is generic and can be used as a starting point for other Armv8-A +application processors. Therefore, the port `ARM_CA53_64_BIT` is renamed as +`ARM_AARCH64`. The existing projects that use old port `ARM_CA53_64_BIT`, +should migrate to renamed port `ARM_AARCH64`. + +**NOTE** + +This port uses memory mapped interface to access Arm GIC registers. diff --git a/portable/GCC/ARM_CA53_64_BIT_SRE/README.md b/portable/GCC/ARM_CA53_64_BIT_SRE/README.md new file mode 100644 index 000000000..9951f81c8 --- /dev/null +++ b/portable/GCC/ARM_CA53_64_BIT_SRE/README.md @@ -0,0 +1,16 @@ +# ARM_CA53_64_BIT_SRE port + +Initial port to support Armv8-A architecture in FreeRTOS kernel was written for +Arm Cortex-A53 processor. + +* ARM_CA53_64_BIT_SRE + * System Register interface to access Arm GIC registers + +This port is generic and can be used as a starting point for other Armv8-A +application processors. Therefore, the port `ARM_AARCH64_SRE` is renamed as +`ARM_AARCH64_SRE`. The existing projects that use old port `ARM_AARCH64_SRE`, +should migrate to renamed port `ARM_AARCH64_SRE`. + +**NOTE** + +This port uses System Register interface to access Arm GIC registers. diff --git a/portable/GCC/ARM_CA9/port.c b/portable/GCC/ARM_CA9/port.c new file mode 100644 index 000000000..67bb0fc8c --- /dev/null +++ b/portable/GCC/ARM_CA9/port.c @@ -0,0 +1,577 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS + #error "configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" +#endif + +#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET + #error "configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" +#endif + +#ifndef configUNIQUE_INTERRUPT_PRIORITIES + #error "configUNIQUE_INTERRUPT_PRIORITIES must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" +#endif + +#ifndef configSETUP_TICK_INTERRUPT + #error "configSETUP_TICK_INTERRUPT() must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" +#endif /* configSETUP_TICK_INTERRUPT */ + +#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" +#endif + +#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0 + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0" +#endif + +#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority" +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + /* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice." + #endif +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/* In case security extensions are implemented. */ +#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 ) + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )" +#endif + +/* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in + * portmacro.h. */ +#ifndef configCLEAR_TICK_INTERRUPT + #define configCLEAR_TICK_INTERRUPT() +#endif + +/* A critical section is exited when the critical section nesting count reaches + * this value. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + +/* In all GICs 255 can be written to the priority mask register to unmask all + * (but the lowest) interrupt priority. */ +#define portUNMASK_VALUE ( 0xFFUL ) + +/* Tasks are not created with a floating point context, but can be given a + * floating point context after they have been created. A variable is stored as + * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task + * does not have an FPU context, or any other value if the task does have an FPU + * context. */ +#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) + +/* Constants required to setup the initial task context. */ +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portINTERRUPT_ENABLE_BIT ( 0x80UL ) +#define portTHUMB_MODE_ADDRESS ( 0x01UL ) + +/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary + * point is zero. */ +#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 ) + +/* Masks all bits in the APSR other than the mode bits. */ +#define portAPSR_MODE_BITS_MASK ( 0x1F ) + +/* The value of the mode bits in the APSR when the CPU is executing in user + * mode. */ +#define portAPSR_USER_MODE ( 0x10 ) + +/* The critical section macros only mask interrupts up to an application + * determined priority level. Sometimes it is necessary to turn interrupt off in + * the CPU itself before modifying certain hardware registers. */ +#define portCPU_IRQ_DISABLE() \ + __asm volatile ( "CPSID i" ::: "memory" ); \ + __asm volatile ( "DSB" ); \ + __asm volatile ( "ISB" ); + +#define portCPU_IRQ_ENABLE() \ + __asm volatile ( "CPSIE i" ::: "memory" ); \ + __asm volatile ( "DSB" ); \ + __asm volatile ( "ISB" ); + + +/* Macro to unmask all interrupt priorities. */ +#define portCLEAR_INTERRUPT_MASK() \ + { \ + portCPU_IRQ_DISABLE(); \ + portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \ + __asm volatile ( "DSB \n" \ + "ISB \n" ); \ + portCPU_IRQ_ENABLE(); \ + } + +#define portINTERRUPT_PRIORITY_REGISTER_OFFSET 0x400UL +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portBIT_0_SET ( ( uint8_t ) 0x01 ) + +/* Let the user override the pre-loading of the initial LR with the address of + * prvTaskExitError() in case it messes up unwinding of the stack in the + * debugger. */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/* The space on the stack required to hold the FPU registers. This is 32 64-bit + * registers, plus a 32-bit status register. */ +#define portFPU_REGISTER_WORDS ( ( 32 * 2 ) + 1 ) + +/*-----------------------------------------------------------*/ + +/* + * Starts the first task executing. This function is necessarily written in + * assembly code so is implemented in portASM.s. + */ +extern void vPortRestoreTaskContext( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/* + * If the application provides an implementation of vApplicationIRQHandler(), + * then it will get called directly without saving the FPU registers on + * interrupt entry, and this weak implementation of + * vApplicationFPUSafeIRQHandler() is just provided to remove linkage errors - + * it should never actually get called so its implementation contains a + * call to configASSERT() that will always fail. + * + * If the application provides its own implementation of + * vApplicationFPUSafeIRQHandler() then the implementation of + * vApplicationIRQHandler() provided in portASM.S will save the FPU registers + * before calling it. + * + * Therefore, if the application writer wants FPU registers to be saved on + * interrupt entry their IRQ handler must be called + * vApplicationFPUSafeIRQHandler(), and if the application writer does not want + * FPU registers to be saved on interrupt entry their IRQ handler must be + * called vApplicationIRQHandler(). + */ +void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR ) __attribute__( ( weak ) ); + +/*-----------------------------------------------------------*/ + +/* A variable is used to keep track of the critical section nesting. This + * variable has to be stored as part of the task context and must be initialised to + * a non zero value to ensure interrupts don't inadvertently become unmasked before + * the scheduler starts. As it is stored as part of the task context it will + * automatically be set to 0 when the first task is started. */ +volatile uint32_t ulCriticalNesting = 9999UL; + +/* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then + * a floating point context must be saved and restored for the task. */ +volatile uint32_t ulPortTaskHasFPUContext = pdFALSE; + +/* Set to 1 to pend a context switch from an ISR. */ +volatile uint32_t ulPortYieldRequired = pdFALSE; + +/* Counts the interrupt nesting depth. A context switch is only performed if + * if the nesting depth is 0. */ +volatile uint32_t ulPortInterruptNesting = 0UL; + +/* Used in the asm file. */ +__attribute__( ( used ) ) const uint32_t ulICCIARAddress = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS; +__attribute__( ( used ) ) const uint32_t ulICCEOIRAddress = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS; +__attribute__( ( used ) ) const uint32_t ulICCPMRAddress = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS; +__attribute__( ( used ) ) const uint32_t ulMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Setup the initial stack of the task. The stack is set exactly as + * expected by the portRESTORE_CONTEXT() macro. + * + * The fist real value on the stack is the status register, which is set for + * system mode, with interrupts enabled. A few NULLs are added first to ensure + * GDB does not try decoding a non-existent return address. */ + *pxTopOfStack = ( StackType_t ) NULL; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) NULL; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) NULL; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + + if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL ) + { + /* The task will start in THUMB mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + + pxTopOfStack--; + + /* Next the return address, which in this case is the start of the task. */ + *pxTopOfStack = ( StackType_t ) pxCode; + pxTopOfStack--; + + /* Next all the registers other than the stack pointer. */ + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The task will start with a critical nesting count of 0 as interrupts are + * enabled. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + + #if ( configUSE_TASK_FPU_SUPPORT == 1 ) + { + /* The task will start without a floating point context. A task that + * uses the floating point hardware must call vPortTaskUsesFPU() before + * executing any floating point instructions. */ + pxTopOfStack--; + *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT; + } + #elif ( configUSE_TASK_FPU_SUPPORT == 2 ) + { + /* The task will start with a floating point context. Leave enough + * space for the registers - and ensure they are initialised to 0. */ + pxTopOfStack -= portFPU_REGISTER_WORDS; + memset( pxTopOfStack, 0x00, portFPU_REGISTER_WORDS * sizeof( StackType_t ) ); + + pxTopOfStack--; + *pxTopOfStack = pdTRUE; + ulPortTaskHasFPUContext = pdTRUE; + } + #else /* if ( configUSE_TASK_FPU_SUPPORT == 1 ) */ + { + #error "Invalid configUSE_TASK_FPU_SUPPORT setting - configUSE_TASK_FPU_SUPPORT must be set to 1, 2, or left undefined." + } + #endif /* if ( configUSE_TASK_FPU_SUPPORT == 1 ) */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ + configASSERT( ulPortInterruptNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + uint32_t ulAPSR; + + #if ( configASSERT_DEFINED == 1 ) + { + volatile uint8_t ucOriginalPriority; + volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET ); + volatile uint8_t ucMaxPriorityValue; + + /* Determine how many priority bits are implemented in the GIC. + * + * Save the interrupt priority value that is about to be clobbered. */ + ucOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to + * all possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* Shift to the least significant bits. */ + while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET ) + { + ucMaxPriorityValue >>= ( uint8_t ) 0x01; + } + + /* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read + * value. */ + configASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY ); + + /* Restore the clobbered interrupt priority register to its original + * value. */ + *pucFirstUserPriorityRegister = ucOriginalPriority; + } + #endif /* configASSERT_DEFINED */ + + + /* Only continue if the CPU is not in User mode. The CPU must be in a + * Privileged mode for the scheduler to start. */ + __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR )::"memory" ); + ulAPSR &= portAPSR_MODE_BITS_MASK; + configASSERT( ulAPSR != portAPSR_USER_MODE ); + + if( ulAPSR != portAPSR_USER_MODE ) + { + /* Only continue if the binary point value is set to its lowest possible + * setting. See the comments in vPortValidateInterruptPriority() below for + * more information. */ + configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ); + + if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ) + { + /* Interrupts are turned off in the CPU itself to ensure tick does + * not execute while the scheduler is being started. Interrupts are + * automatically turned back on in the CPU when the first task starts + * executing. */ + portCPU_IRQ_DISABLE(); + + /* Start the timer that generates the tick ISR. */ + configSETUP_TICK_INTERRUPT(); + + /* Start the first task executing. */ + vPortRestoreTaskContext(); + } + } + + /* Will only get here if vTaskStartScheduler() was called with the CPU in + * a non-privileged mode or the binary point register was not set to its lowest + * possible value. prvTaskExitError() is referenced to prevent a compiler + * warning about it being defined but not referenced in the case that the user + * defines their own exit address. */ + ( void ) prvTaskExitError; + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + /* Mask interrupts up to the max syscall interrupt priority. */ + ulPortSetInterruptMask(); + + /* Now that interrupts are disabled, ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ + if( ulCriticalNesting == 1 ) + { + configASSERT( ulPortInterruptNesting == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as the critical section is being + * exited. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then all interrupt + * priorities must be re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Critical nesting has reached zero so all interrupt priorities + * should be unmasked. */ + portCLEAR_INTERRUPT_MASK(); + } + } +} +/*-----------------------------------------------------------*/ + +void FreeRTOS_Tick_Handler( void ) +{ + /* Set interrupt mask before altering scheduler structures. The tick + * handler runs at the lowest priority, so interrupts cannot already be masked, + * so there is no need to save and restore the current mask value. It is + * necessary to turn off interrupts in the CPU itself while the ICCPMR is being + * updated. */ + portCPU_IRQ_DISABLE(); + portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); + __asm volatile ( "dsb \n" + "isb \n" ::: "memory" ); + portCPU_IRQ_ENABLE(); + + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + ulPortYieldRequired = pdTRUE; + } + + /* Ensure all interrupt priorities are active again. */ + portCLEAR_INTERRUPT_MASK(); + configCLEAR_TICK_INTERRUPT(); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_FPU_SUPPORT != 2 ) + + void vPortTaskUsesFPU( void ) + { + uint32_t ulInitialFPSCR = 0; + + /* A task is registering the fact that it needs an FPU context. Set the + * FPU flag (which is saved as part of the task context). */ + ulPortTaskHasFPUContext = pdTRUE; + + /* Initialise the floating point status register. */ + __asm volatile ( "FMXR FPSCR, %0" ::"r" ( ulInitialFPSCR ) : "memory" ); + } + +#endif /* configUSE_TASK_FPU_SUPPORT */ +/*-----------------------------------------------------------*/ + +void vPortClearInterruptMask( uint32_t ulNewMaskValue ) +{ + if( ulNewMaskValue == pdFALSE ) + { + portCLEAR_INTERRUPT_MASK(); + } +} +/*-----------------------------------------------------------*/ + +uint32_t ulPortSetInterruptMask( void ) +{ + uint32_t ulReturn; + + /* Interrupt in the CPU must be turned off while the ICCPMR is being + * updated. */ + portCPU_IRQ_DISABLE(); + + if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ) + { + /* Interrupts were already masked. */ + ulReturn = pdTRUE; + } + else + { + ulReturn = pdFALSE; + portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); + __asm volatile ( "dsb \n" + "isb \n" ::: "memory" ); + } + + portCPU_IRQ_ENABLE(); + + return ulReturn; +} +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. */ + configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ); + + /* Priority grouping: The interrupt controller (GIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * The priority grouping is configured by the GIC's binary point register + * (ICCBPR). Writing 0 to ICCBPR will ensure it is set to its lowest + * possible value (which may be above 0). */ + configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ); + } + +#endif /* configASSERT_DEFINED */ +/*-----------------------------------------------------------*/ + +void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR ) +{ + ( void ) ulICCIAR; + configASSERT( ( volatile void * ) NULL ); +} diff --git a/portable/GCC/ARM_CA9/portASM.S b/portable/GCC/ARM_CA9/portASM.S new file mode 100644 index 000000000..5df123479 --- /dev/null +++ b/portable/GCC/ARM_CA9/portASM.S @@ -0,0 +1,332 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + .eabi_attribute Tag_ABI_align_preserved, 1 + .text + .arm + + .set SYS_MODE, 0x1f + .set SVC_MODE, 0x13 + .set IRQ_MODE, 0x12 + + /* Hardware registers addresses. */ + .extern ulICCIARAddress + .extern ulICCEOIRAddress + .extern ulICCPMRAddress + + /* Variables and functions. */ + .extern ulMaxAPIPriorityMask + .extern _freertos_vector_table + .extern pxCurrentTCB + .extern vTaskSwitchContext + .extern vApplicationIRQHandler + .extern ulPortInterruptNesting + .extern ulPortTaskHasFPUContext + + .global FreeRTOS_IRQ_Handler + .global FreeRTOS_SWI_Handler + .global vPortRestoreTaskContext + + + + +.macro portSAVE_CONTEXT + + /* Save the LR and SPSR onto the system mode stack before switching to + system mode to save the remaining system mode registers. */ + SRSDB sp!, #SYS_MODE + CPS #SYS_MODE + PUSH {R0-R12, R14} + + /* Push the critical nesting count. */ + LDR R2, ulCriticalNestingConst + LDR R1, [R2] + PUSH {R1} + + /* Does the task have a floating point context that needs saving? If + ulPortTaskHasFPUContext is 0 then no. */ + LDR R2, ulPortTaskHasFPUContextConst + LDR R3, [R2] + CMP R3, #0 + + /* Save the floating point context, if any. */ + FMRXNE R1, FPSCR + PUSHNE {R1} + VPUSHNE {D0-D15} + VPUSHNE {D16-D31} + + /* Save ulPortTaskHasFPUContext itself. */ + PUSH {R3} + + /* Save the stack pointer in the TCB. */ + LDR R0, pxCurrentTCBConst + LDR R1, [R0] + STR SP, [R1] + + .endm + +; /**********************************************************************/ + +.macro portRESTORE_CONTEXT + + /* Set the SP to point to the stack of the task being restored. */ + LDR R0, pxCurrentTCBConst + LDR R1, [R0] + LDR SP, [R1] + + /* Is there a floating point context to restore? If the restored + ulPortTaskHasFPUContext is zero then no. */ + LDR R0, ulPortTaskHasFPUContextConst + POP {R1} + STR R1, [R0] + CMP R1, #0 + + /* Restore the floating point context, if any. */ + VPOPNE {D16-D31} + VPOPNE {D0-D15} + POPNE {R0} + VMSRNE FPSCR, R0 + + /* Restore the critical section nesting depth. */ + LDR R0, ulCriticalNestingConst + POP {R1} + STR R1, [R0] + + /* Ensure the priority mask is correct for the critical nesting depth. */ + LDR R2, ulICCPMRConst + LDR R2, [R2] + CMP R1, #0 + MOVEQ R4, #255 + LDRNE R4, ulMaxAPIPriorityMaskConst + LDRNE R4, [R4] + STR R4, [R2] + + /* Restore all system mode registers other than the SP (which is already + being used). */ + POP {R0-R12, R14} + + /* Return to the task code, loading CPSR on the way. */ + RFEIA sp! + + .endm + + + + +/****************************************************************************** + * SVC handler is used to start the scheduler. + *****************************************************************************/ +.align 4 +.type FreeRTOS_SWI_Handler, %function +FreeRTOS_SWI_Handler: + /* Save the context of the current task and select a new task to run. */ + portSAVE_CONTEXT + + /* Ensure bit 2 of the stack pointer is clear. */ + MOV r2, sp + AND r2, r2, #4 + SUB sp, sp, r2 + + LDR R0, vTaskSwitchContextConst + BLX R0 + + portRESTORE_CONTEXT + + +/****************************************************************************** + * vPortRestoreTaskContext is used to start the scheduler. + *****************************************************************************/ +.type vPortRestoreTaskContext, %function +vPortRestoreTaskContext: + /* Switch to system mode. */ + CPS #SYS_MODE + portRESTORE_CONTEXT + +.align 4 +.type FreeRTOS_IRQ_Handler, %function +FreeRTOS_IRQ_Handler: + /* Return to the interrupted instruction. */ + SUB lr, lr, #4 + + /* Push the return address and SPSR. */ + PUSH {lr} + MRS lr, SPSR + PUSH {lr} + + /* Change to supervisor mode to allow reentry. */ + CPS #SVC_MODE + + /* Push used registers. */ + PUSH {r0-r4, r12} + + /* Increment nesting count. r3 holds the address of ulPortInterruptNesting + for future use. r1 holds the original ulPortInterruptNesting value for + future use. */ + LDR r3, ulPortInterruptNestingConst + LDR r1, [r3] + ADD r4, r1, #1 + STR r4, [r3] + + /* Read value from the interrupt acknowledge register, which is stored in r0 + for future parameter and interrupt clearing use. */ + LDR r2, ulICCIARConst + LDR r2, [r2] + LDR r0, [r2] + + /* Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for + future use. _RB_ Does this ever actually need to be done provided the start + of the stack is 8-byte aligned? */ + MOV r2, sp + AND r2, r2, #4 + SUB sp, sp, r2 + + /* Call the interrupt handler. r4 pushed to maintain alignment. */ + PUSH {r0-r4, lr} + LDR r1, vApplicationIRQHandlerConst + BLX r1 + POP {r0-r4, lr} + ADD sp, sp, r2 + + CPSID i + DSB + ISB + + /* Write the value read from ICCIAR to ICCEOIR. */ + LDR r4, ulICCEOIRConst + LDR r4, [r4] + STR r0, [r4] + + /* Restore the old nesting count. */ + STR r1, [r3] + + /* A context switch is never performed if the nesting count is not 0. */ + CMP r1, #0 + BNE exit_without_switch + + /* Did the interrupt request a context switch? r1 holds the address of + ulPortYieldRequired and r0 the value of ulPortYieldRequired for future + use. */ + LDR r1, =ulPortYieldRequired + LDR r0, [r1] + CMP r0, #0 + BNE switch_before_exit + +exit_without_switch: + /* No context switch. Restore used registers, LR_irq and SPSR before + returning. */ + POP {r0-r4, r12} + CPS #IRQ_MODE + POP {LR} + MSR SPSR_cxsf, LR + POP {LR} + MOVS PC, LR + +switch_before_exit: + /* A context switch is to be performed. Clear the context switch pending + flag. */ + MOV r0, #0 + STR r0, [r1] + + /* Restore used registers, LR-irq and SPSR before saving the context + to the task stack. */ + POP {r0-r4, r12} + CPS #IRQ_MODE + POP {LR} + MSR SPSR_cxsf, LR + POP {LR} + portSAVE_CONTEXT + + /* Call the function that selects the new task to execute. + vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD + instructions, or 8 byte aligned stack allocated data. LR does not need + saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. + Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for + future use. */ + MOV r2, sp + AND r2, r2, #4 + SUB sp, sp, r2 + + LDR R0, vTaskSwitchContextConst + BLX R0 + + /* Restore the context of, and branch to, the task selected to execute + next. */ + portRESTORE_CONTEXT + + +/****************************************************************************** + * If the application provides an implementation of vApplicationIRQHandler(), + * then it will get called directly without saving the FPU registers on + * interrupt entry, and this weak implementation of + * vApplicationIRQHandler() will not get called. + * + * If the application provides its own implementation of + * vApplicationFPUSafeIRQHandler() then this implementation of + * vApplicationIRQHandler() will be called, save the FPU registers, and then + * call vApplicationFPUSafeIRQHandler(). + * + * Therefore, if the application writer wants FPU registers to be saved on + * interrupt entry their IRQ handler must be called + * vApplicationFPUSafeIRQHandler(), and if the application writer does not want + * FPU registers to be saved on interrupt entry their IRQ handler must be + * called vApplicationIRQHandler(). + *****************************************************************************/ + +.align 4 +.weak vApplicationIRQHandler +.type vApplicationIRQHandler, %function +vApplicationIRQHandler: + PUSH {LR} + FMRX R1, FPSCR + VPUSH {D0-D7} + VPUSH {D16-D31} + PUSH {R1} + + LDR r1, vApplicationFPUSafeIRQHandlerConst + BLX r1 + + POP {R0} + VPOP {D16-D31} + VPOP {D0-D7} + VMSR FPSCR, R0 + + POP {PC} + + +ulICCIARConst: .word ulICCIARAddress +ulICCEOIRConst: .word ulICCEOIRAddress +ulICCPMRConst: .word ulICCPMRAddress +pxCurrentTCBConst: .word pxCurrentTCB +ulCriticalNestingConst: .word ulCriticalNesting +ulPortTaskHasFPUContextConst: .word ulPortTaskHasFPUContext +ulMaxAPIPriorityMaskConst: .word ulMaxAPIPriorityMask +vTaskSwitchContextConst: .word vTaskSwitchContext +vApplicationIRQHandlerConst: .word vApplicationIRQHandler +ulPortInterruptNestingConst: .word ulPortInterruptNesting +vApplicationFPUSafeIRQHandlerConst: .word vApplicationFPUSafeIRQHandler + +.end diff --git a/portable/GCC/ARM_CA9/portmacro.h b/portable/GCC/ARM_CA9/portmacro.h new file mode 100644 index 000000000..1ded79c8c --- /dev/null +++ b/portable/GCC/ARM_CA9/portmacro.h @@ -0,0 +1,212 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +typedef uint32_t TickType_t; +#define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ +#define portTICK_TYPE_IS_ATOMIC 1 + +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* Called at the end of an ISR that can cause a context switch. */ +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + { \ + extern uint32_t ulPortYieldRequired; \ + \ + if( xSwitchRequired != pdFALSE ) \ + { \ + ulPortYieldRequired = pdTRUE; \ + } \ + } + +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#define portYIELD() __asm volatile ( "SWI 0" ::: "memory" ); + + +/*----------------------------------------------------------- +* Critical section control +*----------------------------------------------------------*/ + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +extern uint32_t ulPortSetInterruptMask( void ); +extern void vPortClearInterruptMask( uint32_t ulNewMaskValue ); +extern void vPortInstallFreeRTOSVectorTable( void ); + +/* These macros do not globally disable/enable interrupts. They do mask off + * interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */ +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); +#define portDISABLE_INTERRUPTS() ulPortSetInterruptMask() +#define portENABLE_INTERRUPTS() vPortClearInterruptMask( 0 ) +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortClearInterruptMask( x ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not required for this port but included in case common demo code that uses these + * macros is used. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* Prototype of the FreeRTOS tick handler. This must be installed as the + * handler for whichever peripheral is used to generate the RTOS tick. */ +void FreeRTOS_Tick_Handler( void ); + +/* If configUSE_TASK_FPU_SUPPORT is set to 1 (or left undefined) then tasks are + * created without an FPU context and must call vPortTaskUsesFPU() to give + * themselves an FPU context before using any FPU instructions. If + * configUSE_TASK_FPU_SUPPORT is set to 2 then all tasks will have an FPU context + * by default. */ +#if ( configUSE_TASK_FPU_SUPPORT != 2 ) + void vPortTaskUsesFPU( void ); +#else + +/* Each task has an FPU context already, so define this function away to + * nothing to prevent it being called accidentally. */ + #define vPortTaskUsesFPU() +#endif +#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() + +#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL ) +#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL ) + +/* Architecture specific optimisations. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __builtin_clz( uxReadyPriorities ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +#if ( configASSERT_DEFINED == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif /* configASSERT */ + +#define portNOP() __asm volatile ( "NOP" ) +#define portINLINE __inline + +/* The number of bits to shift for an interrupt priority is dependent on the + * number of bits implemented by the interrupt controller. */ +#if configUNIQUE_INTERRUPT_PRIORITIES == 16 + #define portPRIORITY_SHIFT 4 + #define portMAX_BINARY_POINT_VALUE 3 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 32 + #define portPRIORITY_SHIFT 3 + #define portMAX_BINARY_POINT_VALUE 2 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 64 + #define portPRIORITY_SHIFT 2 + #define portMAX_BINARY_POINT_VALUE 1 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 128 + #define portPRIORITY_SHIFT 1 + #define portMAX_BINARY_POINT_VALUE 0 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 256 + #define portPRIORITY_SHIFT 0 + #define portMAX_BINARY_POINT_VALUE 0 +#else /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */ + #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware +#endif /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */ + +/* Interrupt controller access addresses. */ +#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 ) +#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C ) +#define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 ) +#define portICCBPR_BINARY_POINT_OFFSET ( 0x08 ) +#define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 ) + +#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET ) +#define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) ) +#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ) +#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET ) +#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) +#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) ) +#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) ) + +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/ARM_CM0/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM0/mpu_wrappers_v2_asm.c new file mode 100644 index 000000000..4f14482e2 --- /dev/null +++ b/portable/GCC/ARM_CM0/mpu_wrappers_v2_asm.c @@ -0,0 +1,2217 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" +#include "event_groups.h" +#include "stream_buffer.h" +#include "mpu_prototypes.h" +#include "mpu_syscall_numbers.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( INCLUDE_xTaskDelayUntil == 1 ) + + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskDelayUntilImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskDelayUntil_Unpriv \n" + " MPU_xTaskDelayUntil_Priv: \n" + " push {lr} \n" + " blx MPU_xTaskDelayUntilImpl \n" + " pop {pc} \n" + " MPU_xTaskDelayUntil_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskAbortDelayImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskAbortDelay_Unpriv \n" + " MPU_xTaskAbortDelay_Priv: \n" + " push {lr} \n" + " blx MPU_xTaskAbortDelayImpl \n" + " pop {pc} \n" + " MPU_xTaskAbortDelay_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskDelay == 1 ) + + void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskDelayImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vTaskDelay_Unpriv \n" + " MPU_vTaskDelay_Priv: \n" + " push {lr} \n" + " blx MPU_vTaskDelayImpl \n" + " pop {pc} \n" + " MPU_vTaskDelay_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskPriorityGet == 1 ) + + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskPriorityGetImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_uxTaskPriorityGet_Unpriv \n" + " MPU_uxTaskPriorityGet_Priv: \n" + " push {lr} \n" + " blx MPU_uxTaskPriorityGetImpl \n" + " pop {pc} \n" + " MPU_uxTaskPriorityGet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_eTaskGetState == 1 ) + + eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_eTaskGetStateImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_eTaskGetState_Unpriv \n" + " MPU_eTaskGetState_Priv: \n" + " push {lr} \n" + " blx MPU_eTaskGetStateImpl \n" + " pop {pc} \n" + " MPU_eTaskGetState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory" + ); + } + + #endif /* if ( INCLUDE_eTaskGetState == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskGetInfoImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vTaskGetInfo_Unpriv \n" + " MPU_vTaskGetInfo_Priv: \n" + " push {lr} \n" + " blx MPU_vTaskGetInfoImpl \n" + " pop {pc} \n" + " MPU_vTaskGetInfo_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory" + ); + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) + + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetIdleTaskHandleImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskGetIdleTaskHandle_Unpriv \n" + " MPU_xTaskGetIdleTaskHandle_Priv: \n" + " push {lr} \n" + " blx MPU_xTaskGetIdleTaskHandleImpl \n" + " pop {pc} \n" + " MPU_xTaskGetIdleTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + + void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSuspendImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vTaskSuspend_Unpriv \n" + " MPU_vTaskSuspend_Priv: \n" + " push {lr} \n" + " blx MPU_vTaskSuspendImpl \n" + " pop {pc} \n" + " MPU_vTaskSuspend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + + void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskResumeImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vTaskResume_Unpriv \n" + " MPU_vTaskResume_Priv: \n" + " push {lr} \n" + " blx MPU_vTaskResumeImpl \n" + " pop {pc} \n" + " MPU_vTaskResume_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + TickType_t MPU_xTaskGetTickCount( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetTickCountImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskGetTickCount_Unpriv \n" + " MPU_xTaskGetTickCount_Priv: \n" + " push {lr} \n" + " blx MPU_xTaskGetTickCountImpl \n" + " pop {pc} \n" + " MPU_xTaskGetTickCount_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetNumberOfTasksImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_uxTaskGetNumberOfTasks_Unpriv \n" + " MPU_uxTaskGetNumberOfTasks_Priv: \n" + " push {lr} \n" + " blx MPU_uxTaskGetNumberOfTasksImpl \n" + " pop {pc} \n" + " MPU_uxTaskGetNumberOfTasks_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetRunTimeCounterImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_ulTaskGetRunTimeCounter_Unpriv \n" + " MPU_ulTaskGetRunTimeCounter_Priv: \n" + " push {lr} \n" + " blx MPU_ulTaskGetRunTimeCounterImpl \n" + " pop {pc} \n" + " MPU_ulTaskGetRunTimeCounter_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetRunTimePercentImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_ulTaskGetRunTimePercent_Unpriv \n" + " MPU_ulTaskGetRunTimePercent_Priv: \n" + " push {lr} \n" + " blx MPU_ulTaskGetRunTimePercentImpl \n" + " pop {pc} \n" + " MPU_ulTaskGetRunTimePercent_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetIdleRunTimePercentImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv \n" + " MPU_ulTaskGetIdleRunTimePercent_Priv: \n" + " push {lr} \n" + " blx MPU_ulTaskGetIdleRunTimePercentImpl \n" + " pop {pc} \n" + " MPU_ulTaskGetIdleRunTimePercent_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetIdleRunTimeCounterImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv \n" + " MPU_ulTaskGetIdleRunTimeCounter_Priv: \n" + " push {lr} \n" + " blx MPU_ulTaskGetIdleRunTimeCounterImpl \n" + " pop {pc} \n" + " MPU_ulTaskGetIdleRunTimeCounter_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetApplicationTaskTagImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vTaskSetApplicationTaskTag_Unpriv \n" + " MPU_vTaskSetApplicationTaskTag_Priv: \n" + " push {lr} \n" + " blx MPU_vTaskSetApplicationTaskTagImpl \n" + " pop {pc} \n" + " MPU_vTaskSetApplicationTaskTag_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory" + ); + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetApplicationTaskTagImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskGetApplicationTaskTag_Unpriv \n" + " MPU_xTaskGetApplicationTaskTag_Priv: \n" + " push {lr} \n" + " blx MPU_xTaskGetApplicationTaskTagImpl \n" + " pop {pc} \n" + " MPU_xTaskGetApplicationTaskTag_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory" + ); + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetThreadLocalStoragePointerImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv \n" + " MPU_vTaskSetThreadLocalStoragePointer_Priv: \n" + " push {lr} \n" + " blx MPU_vTaskSetThreadLocalStoragePointerImpl \n" + " pop {pc} \n" + " MPU_vTaskSetThreadLocalStoragePointer_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory" + ); + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv \n" + " MPU_pvTaskGetThreadLocalStoragePointer_Priv: \n" + " push {lr} \n" + " blx MPU_pvTaskGetThreadLocalStoragePointerImpl \n" + " pop {pc} \n" + " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory" + ); + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetSystemStateImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_uxTaskGetSystemState_Unpriv \n" + " MPU_uxTaskGetSystemState_Priv: \n" + " push {lr} \n" + " blx MPU_uxTaskGetSystemStateImpl \n" + " pop {pc} \n" + " MPU_uxTaskGetSystemState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory" + ); + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) + + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetStackHighWaterMarkImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_uxTaskGetStackHighWaterMark_Unpriv \n" + " MPU_uxTaskGetStackHighWaterMark_Priv: \n" + " push {lr} \n" + " blx MPU_uxTaskGetStackHighWaterMarkImpl \n" + " pop {pc} \n" + " MPU_uxTaskGetStackHighWaterMark_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetStackHighWaterMark2Impl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv \n" + " MPU_uxTaskGetStackHighWaterMark2_Priv: \n" + " push {lr} \n" + " blx MPU_uxTaskGetStackHighWaterMark2Impl \n" + " pop {pc} \n" + " MPU_uxTaskGetStackHighWaterMark2_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) + + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetCurrentTaskHandleImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskGetCurrentTaskHandle_Unpriv \n" + " MPU_xTaskGetCurrentTaskHandle_Priv: \n" + " push {lr} \n" + " blx MPU_xTaskGetCurrentTaskHandleImpl \n" + " pop {pc} \n" + " MPU_xTaskGetCurrentTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory" + ); + } + + #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetSchedulerState == 1 ) + + BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetSchedulerStateImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskGetSchedulerState_Unpriv \n" + " MPU_xTaskGetSchedulerState_Priv: \n" + " push {lr} \n" + " blx MPU_xTaskGetSchedulerStateImpl \n" + " pop {pc} \n" + " MPU_xTaskGetSchedulerState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */ +/*-----------------------------------------------------------*/ + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetTimeOutStateImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vTaskSetTimeOutState_Unpriv \n" + " MPU_vTaskSetTimeOutState_Priv: \n" + " push {lr} \n" + " blx MPU_vTaskSetTimeOutStateImpl \n" + " pop {pc} \n" + " MPU_vTaskSetTimeOutState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskCheckForTimeOutImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskCheckForTimeOut_Unpriv \n" + " MPU_xTaskCheckForTimeOut_Priv: \n" + " push {lr} \n" + " blx MPU_xTaskCheckForTimeOutImpl \n" + " pop {pc} \n" + " MPU_xTaskCheckForTimeOut_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskGenericNotify_Unpriv \n" + " MPU_xTaskGenericNotify_Priv: \n" + " push {lr} \n" + " blx MPU_xTaskGenericNotifyImpl \n" + " pop {pc} \n" + " MPU_xTaskGenericNotify_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyWaitImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskGenericNotifyWait_Unpriv \n" + " MPU_xTaskGenericNotifyWait_Priv: \n" + " push {lr} \n" + " blx MPU_xTaskGenericNotifyWaitImpl \n" + " pop {pc} \n" + " MPU_xTaskGenericNotifyWait_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGenericNotifyTakeImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_ulTaskGenericNotifyTake_Unpriv \n" + " MPU_ulTaskGenericNotifyTake_Priv: \n" + " push {lr} \n" + " blx MPU_ulTaskGenericNotifyTakeImpl \n" + " pop {pc} \n" + " MPU_ulTaskGenericNotifyTake_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyStateClearImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskGenericNotifyStateClear_Unpriv \n" + " MPU_xTaskGenericNotifyStateClear_Priv: \n" + " push {lr} \n" + " blx MPU_xTaskGenericNotifyStateClearImpl \n" + " pop {pc} \n" + " MPU_xTaskGenericNotifyStateClear_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGenericNotifyValueClearImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_ulTaskGenericNotifyValueClear_Unpriv \n" + " MPU_ulTaskGenericNotifyValueClear_Priv: \n" + " push {lr} \n" + " blx MPU_ulTaskGenericNotifyValueClearImpl \n" + " pop {pc} \n" + " MPU_ulTaskGenericNotifyValueClear_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGenericSendImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xQueueGenericSend_Unpriv \n" + " MPU_xQueueGenericSend_Priv: \n" + " push {lr} \n" + " blx MPU_xQueueGenericSendImpl \n" + " pop {pc} \n" + " MPU_xQueueGenericSend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxQueueMessagesWaitingImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_uxQueueMessagesWaiting_Unpriv \n" + " MPU_uxQueueMessagesWaiting_Priv: \n" + " push {lr} \n" + " blx MPU_uxQueueMessagesWaitingImpl \n" + " pop {pc} \n" + " MPU_uxQueueMessagesWaiting_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxQueueSpacesAvailableImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_uxQueueSpacesAvailable_Unpriv \n" + " MPU_uxQueueSpacesAvailable_Priv: \n" + " push {lr} \n" + " blx MPU_uxQueueSpacesAvailableImpl \n" + " pop {pc} \n" + " MPU_uxQueueSpacesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueReceiveImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xQueueReceive_Unpriv \n" + " MPU_xQueueReceive_Priv: \n" + " push {lr} \n" + " blx MPU_xQueueReceiveImpl \n" + " pop {pc} \n" + " MPU_xQueueReceive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueuePeekImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xQueuePeek_Unpriv \n" + " MPU_xQueuePeek_Priv: \n" + " push {lr} \n" + " blx MPU_xQueuePeekImpl \n" + " pop {pc} \n" + " MPU_xQueuePeek_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueSemaphoreTakeImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xQueueSemaphoreTake_Unpriv \n" + " MPU_xQueueSemaphoreTake_Priv: \n" + " push {lr} \n" + " blx MPU_xQueueSemaphoreTakeImpl \n" + " pop {pc} \n" + " MPU_xQueueSemaphoreTake_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) + + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGetMutexHolderImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xQueueGetMutexHolder_Unpriv \n" + " MPU_xQueueGetMutexHolder_Priv: \n" + " push {lr} \n" + " blx MPU_xQueueGetMutexHolderImpl \n" + " pop {pc} \n" + " MPU_xQueueGetMutexHolder_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory" + ); + } + + #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueTakeMutexRecursiveImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xQueueTakeMutexRecursive_Unpriv \n" + " MPU_xQueueTakeMutexRecursive_Priv: \n" + " push {lr} \n" + " blx MPU_xQueueTakeMutexRecursiveImpl \n" + " pop {pc} \n" + " MPU_xQueueTakeMutexRecursive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory" + ); + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGiveMutexRecursiveImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xQueueGiveMutexRecursive_Unpriv \n" + " MPU_xQueueGiveMutexRecursive_Priv: \n" + " push {lr} \n" + " blx MPU_xQueueGiveMutexRecursiveImpl \n" + " pop {pc} \n" + " MPU_xQueueGiveMutexRecursive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory" + ); + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueSelectFromSetImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xQueueSelectFromSet_Unpriv \n" + " MPU_xQueueSelectFromSet_Priv: \n" + " push {lr} \n" + " blx MPU_xQueueSelectFromSetImpl \n" + " pop {pc} \n" + " MPU_xQueueSelectFromSet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory" + ); + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueAddToSetImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xQueueAddToSet_Unpriv \n" + " MPU_xQueueAddToSet_Priv: \n" + " push {lr} \n" + " blx MPU_xQueueAddToSetImpl \n" + " pop {pc} \n" + " MPU_xQueueAddToSet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory" + ); + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vQueueAddToRegistryImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vQueueAddToRegistry_Unpriv \n" + " MPU_vQueueAddToRegistry_Priv: \n" + " push {lr} \n" + " blx MPU_vQueueAddToRegistryImpl \n" + " pop {pc} \n" + " MPU_vQueueAddToRegistry_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vQueueUnregisterQueueImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vQueueUnregisterQueue_Unpriv \n" + " MPU_vQueueUnregisterQueue_Priv: \n" + " push {lr} \n" + " blx MPU_vQueueUnregisterQueueImpl \n" + " pop {pc} \n" + " MPU_vQueueUnregisterQueue_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pcQueueGetNameImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_pcQueueGetName_Unpriv \n" + " MPU_pcQueueGetName_Priv: \n" + " push {lr} \n" + " blx MPU_pcQueueGetNameImpl \n" + " pop {pc} \n" + " MPU_pcQueueGetName_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pvTimerGetTimerIDImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_pvTimerGetTimerID_Unpriv \n" + " MPU_pvTimerGetTimerID_Priv: \n" + " push {lr} \n" + " blx MPU_pvTimerGetTimerIDImpl \n" + " pop {pc} \n" + " MPU_pvTimerGetTimerID_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTimerSetTimerIDImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vTimerSetTimerID_Unpriv \n" + " MPU_vTimerSetTimerID_Priv: \n" + " push {lr} \n" + " blx MPU_vTimerSetTimerIDImpl \n" + " pop {pc} \n" + " MPU_vTimerSetTimerID_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerIsTimerActiveImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTimerIsTimerActive_Unpriv \n" + " MPU_xTimerIsTimerActive_Priv: \n" + " push {lr} \n" + " blx MPU_xTimerIsTimerActiveImpl \n" + " pop {pc} \n" + " MPU_xTimerIsTimerActive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv \n" + " MPU_xTimerGetTimerDaemonTaskHandle_Priv: \n" + " push {lr} \n" + " blx MPU_xTimerGetTimerDaemonTaskHandleImpl \n" + " pop {pc} \n" + " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGenericCommandFromTaskImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTimerGenericCommandFromTask_Unpriv \n" + " MPU_xTimerGenericCommandFromTask_Priv: \n" + " push {lr} \n" + " blx MPU_xTimerGenericCommandFromTaskImpl \n" + " pop {pc} \n" + " MPU_xTimerGenericCommandFromTask_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pcTimerGetNameImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_pcTimerGetName_Unpriv \n" + " MPU_pcTimerGetName_Priv: \n" + " push {lr} \n" + " blx MPU_pcTimerGetNameImpl \n" + " pop {pc} \n" + " MPU_pcTimerGetName_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTimerSetReloadModeImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vTimerSetReloadMode_Unpriv \n" + " MPU_vTimerSetReloadMode_Priv: \n" + " push {lr} \n" + " blx MPU_vTimerSetReloadModeImpl \n" + " pop {pc} \n" + " MPU_vTimerSetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetReloadModeImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTimerGetReloadMode_Unpriv \n" + " MPU_xTimerGetReloadMode_Priv: \n" + " push {lr} \n" + " blx MPU_xTimerGetReloadModeImpl \n" + " pop {pc} \n" + " MPU_xTimerGetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTimerGetReloadModeImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_uxTimerGetReloadMode_Unpriv \n" + " MPU_uxTimerGetReloadMode_Priv: \n" + " push {lr} \n" + " blx MPU_uxTimerGetReloadModeImpl \n" + " pop {pc} \n" + " MPU_uxTimerGetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetPeriodImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTimerGetPeriod_Unpriv \n" + " MPU_xTimerGetPeriod_Priv: \n" + " push {lr} \n" + " blx MPU_xTimerGetPeriodImpl \n" + " pop {pc} \n" + " MPU_xTimerGetPeriod_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetExpiryTimeImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTimerGetExpiryTime_Unpriv \n" + " MPU_xTimerGetExpiryTime_Priv: \n" + " push {lr} \n" + " blx MPU_xTimerGetExpiryTimeImpl \n" + " pop {pc} \n" + " MPU_xTimerGetExpiryTime_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupWaitBitsImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xEventGroupWaitBits_Unpriv \n" + " MPU_xEventGroupWaitBits_Priv: \n" + " push {lr} \n" + " blx MPU_xEventGroupWaitBitsImpl \n" + " pop {pc} \n" + " MPU_xEventGroupWaitBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupClearBitsImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xEventGroupClearBits_Unpriv \n" + " MPU_xEventGroupClearBits_Priv: \n" + " push {lr} \n" + " blx MPU_xEventGroupClearBitsImpl \n" + " pop {pc} \n" + " MPU_xEventGroupClearBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupSetBitsImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xEventGroupSetBits_Unpriv \n" + " MPU_xEventGroupSetBits_Priv: \n" + " push {lr} \n" + " blx MPU_xEventGroupSetBitsImpl \n" + " pop {pc} \n" + " MPU_xEventGroupSetBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupSyncImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xEventGroupSync_Unpriv \n" + " MPU_xEventGroupSync_Priv: \n" + " push {lr} \n" + " blx MPU_xEventGroupSyncImpl \n" + " pop {pc} \n" + " MPU_xEventGroupSync_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxEventGroupGetNumberImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_uxEventGroupGetNumber_Unpriv \n" + " MPU_uxEventGroupGetNumber_Priv: \n" + " push {lr} \n" + " blx MPU_uxEventGroupGetNumberImpl \n" + " pop {pc} \n" + " MPU_uxEventGroupGetNumber_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory" + ); + } + + #endif /*( configUSE_TRACE_FACILITY == 1 )*/ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vEventGroupSetNumberImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vEventGroupSetNumber_Unpriv \n" + " MPU_vEventGroupSetNumber_Priv: \n" + " push {lr} \n" + " blx MPU_vEventGroupSetNumberImpl \n" + " pop {pc} \n" + " MPU_vEventGroupSetNumber_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory" + ); + } + + #endif /*( configUSE_TRACE_FACILITY == 1 )*/ +/*-----------------------------------------------------------*/ + + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSendImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xStreamBufferSend_Unpriv \n" + " MPU_xStreamBufferSend_Priv: \n" + " push {lr} \n" + " blx MPU_xStreamBufferSendImpl \n" + " pop {pc} \n" + " MPU_xStreamBufferSend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferReceiveImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xStreamBufferReceive_Unpriv \n" + " MPU_xStreamBufferReceive_Priv: \n" + " push {lr} \n" + " blx MPU_xStreamBufferReceiveImpl \n" + " pop {pc} \n" + " MPU_xStreamBufferReceive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferIsFullImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xStreamBufferIsFull_Unpriv \n" + " MPU_xStreamBufferIsFull_Priv: \n" + " push {lr} \n" + " blx MPU_xStreamBufferIsFullImpl \n" + " pop {pc} \n" + " MPU_xStreamBufferIsFull_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferIsEmptyImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xStreamBufferIsEmpty_Unpriv \n" + " MPU_xStreamBufferIsEmpty_Priv: \n" + " push {lr} \n" + " blx MPU_xStreamBufferIsEmptyImpl \n" + " pop {pc} \n" + " MPU_xStreamBufferIsEmpty_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSpacesAvailableImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xStreamBufferSpacesAvailable_Unpriv \n" + " MPU_xStreamBufferSpacesAvailable_Priv: \n" + " push {lr} \n" + " blx MPU_xStreamBufferSpacesAvailableImpl \n" + " pop {pc} \n" + " MPU_xStreamBufferSpacesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferBytesAvailableImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xStreamBufferBytesAvailable_Unpriv \n" + " MPU_xStreamBufferBytesAvailable_Priv: \n" + " push {lr} \n" + " blx MPU_xStreamBufferBytesAvailableImpl \n" + " pop {pc} \n" + " MPU_xStreamBufferBytesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSetTriggerLevelImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xStreamBufferSetTriggerLevel_Unpriv \n" + " MPU_xStreamBufferSetTriggerLevel_Priv: \n" + " push {lr} \n" + " blx MPU_xStreamBufferSetTriggerLevelImpl \n" + " pop {pc} \n" + " MPU_xStreamBufferSetTriggerLevel_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferNextMessageLengthBytesImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv \n" + " MPU_xStreamBufferNextMessageLengthBytes_Priv: \n" + " push {lr} \n" + " blx MPU_xStreamBufferNextMessageLengthBytesImpl \n" + " pop {pc} \n" + " MPU_xStreamBufferNextMessageLengthBytes_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ diff --git a/portable/GCC/ARM_CM0/port.c b/portable/GCC/ARM_CM0/port.c new file mode 100644 index 000000000..fd3229a76 --- /dev/null +++ b/portable/GCC/ARM_CM0/port.c @@ -0,0 +1,1673 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2025 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU includes. */ +#include "mpu_wrappers.h" +#include "mpu_syscall_numbers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); + +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) + +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) + +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) + +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used during system call enter and exit. + */ +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) + +/*-----------------------------------------------------------*/ + +/** + * @brief Offsets in the stack to the parameters when inside the SVC handler. + */ +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) + +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RASR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +/* MPU Region Attribute and Size Register (RASR) bitmasks. */ +#define portMPU_RASR_AP_BITMASK ( 0x7UL << 24UL ) +#define portMPU_RASR_S_C_B_BITMASK ( 0x7UL ) +#define portMPU_RASR_S_C_B_LOCATION ( 16UL ) +#define portMPU_RASR_SIZE_BITMASK ( 0x1FUL << 1UL ) +#define portMPU_RASR_REGION_ENABLE_BITMASK ( 0x1UL ) + +/* MPU Region Base Address Register (RBAR) bitmasks. */ +#define portMPU_RBAR_ADDRESS_BITMASK ( 0xFFFFFF00UL ) +#define portMPU_RBAR_REGION_NUMBER_VALID_BITMASK ( 0x1UL << 4UL ) +#define portMPU_RBAR_REGION_NUMBER_BITMASK ( 0x0000000FUL ) + +/* MPU Control Register (MPU_CTRL) bitmasks. */ +#define portMPU_CTRL_ENABLE_BITMASK ( 0x1UL ) +#define portMPU_CTRL_PRIV_BACKGROUND_ENABLE_BITMASK ( 0x1UL << 2UL ) /* PRIVDEFENA bit. */ + +/* Expected value of the portMPU_TYPE register. */ +#define portEXPECTED_MPU_TYPE_VALUE ( 0x8UL << 8UL ) /* 8 DREGION unified. */ + +/* Extract first address of the MPU region as encoded in the + * RBAR (Region Base Address Register) value. */ +#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \ + ( ( rbar ) & portMPU_RBAR_ADDRESS_BITMASK ) + +/* Extract size of the MPU region as encoded in the + * RASR (Region Attribute and Size Register) value. */ +#define portEXTRACT_REGION_SIZE_FROM_RASR( rasr ) \ + ( 1 << ( ( ( ( rasr ) & portMPU_RASR_SIZE_BITMASK ) >> 1 )+ 1 ) ) + +/* Does addr lies within [start, end] address range? */ +#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \ + ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) ) + +/* Is the access request satisfied by the available permissions? */ +#define portIS_AUTHORIZED( accessRequest, permissions ) \ + ( ( ( permissions ) & ( accessRequest ) ) == accessRequest ) + +/* Max value that fits in a uint32_t type. */ +#define portUINT32_MAX ( ~( ( uint32_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) ) + +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) + +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +/** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> Reserved, 1. + */ +#define portINITIAL_EXC_RETURN ( 0xfffffffdUL ) + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. + */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; + +#endif /* configENABLE_MPU */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the system call stack so that upon returning from + * SVC, the system call stack is used. + * + * @param pulTaskStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + * @param ucSystemCallNumber The system call number of the system call. + */ + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Raise SVC for exiting from a system call. + */ + void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; + +#endif /* configENABLE_MPU == 1 */ + +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief This variable is set to pdTRUE when the scheduler is started. + */ + PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE; + +#endif + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + /** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + + /** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + + /** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; + +#endif /* configUSE_TICKLESS_IDLE */ + +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the cpsid instruction + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ + +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} + +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} + +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) + { + uint32_t ulRegionSize, ulReturnValue = 7UL; + + /* 256 is the smallest region size, 31 is the largest valid value for + * ulReturnValue. */ + for( ulRegionSize = 256UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) ) + { + if( ulActualSizeInBytes <= ulRegionSize ) + { + break; + } + else + { + ulReturnValue++; + } + } + + /* Shift the code by one before returning so it can be written directly + * into the the correct bit position of the attribute register. */ + return( ulReturnValue << 1UL ); + } + +#endif /* configENABLE_MPU */ + +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __FLASH_segment_start__; + extern uint32_t * __FLASH_segment_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + + #else /* if defined( __ARMCC_VERSION ) */ + + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __FLASH_segment_start__[]; + extern uint32_t __FLASH_segment_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + + #endif /* defined( __ARMCC_VERSION ) */ + + /* Ensure that the MPU is present. */ + configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ); + + /* Check that the MPU is present. */ + if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ) + { + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) | /* Base address. */ + ( portMPU_RBAR_REGION_NUMBER_VALID_BITMASK ) | + ( portPRIVILEGED_FLASH_REGION ) ); + + portMPU_RASR_REG = ( ( portMPU_REGION_PRIV_RO_UNPRIV_NA ) | + ( ( configS_C_B_FLASH & portMPU_RASR_S_C_B_BITMASK ) << portMPU_RASR_S_C_B_LOCATION ) | + ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __privileged_functions_start__ ) ) | + ( portMPU_RASR_REGION_ENABLE_BITMASK ) ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RBAR_REG = ( ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */ + ( portMPU_RBAR_REGION_NUMBER_VALID_BITMASK ) | + ( portUNPRIVILEGED_FLASH_REGION ) ); + + portMPU_RASR_REG = ( ( portMPU_REGION_PRIV_RO_UNPRIV_RO ) | + ( ( configS_C_B_FLASH & portMPU_RASR_S_C_B_BITMASK ) << portMPU_RASR_S_C_B_LOCATION ) | + ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) | + ( portMPU_RASR_REGION_ENABLE_BITMASK ) ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RBAR_REG = ( ( uint32_t ) __privileged_sram_start__ ) | /* Base address. */ + ( portMPU_RBAR_REGION_NUMBER_VALID_BITMASK ) | + ( portPRIVILEGED_RAM_REGION ); + + portMPU_RASR_REG = ( ( portMPU_REGION_PRIV_RW_UNPRIV_NA ) | + ( portMPU_REGION_EXECUTE_NEVER ) | + ( ( configS_C_B_SRAM & portMPU_RASR_S_C_B_BITMASK ) << portMPU_RASR_S_C_B_LOCATION ) | + prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_sram_end__ - ( uint32_t ) __privileged_sram_start__ ) | + ( portMPU_RASR_REGION_ENABLE_BITMASK ) ); + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_CTRL_PRIV_BACKGROUND_ENABLE_BITMASK | + portMPU_CTRL_ENABLE_BITMASK ); + } + } + +#endif /* configENABLE_MPU */ + +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} + +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} + +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} + +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} + +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + + #else + + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + + #endif /* defined( __ARMCC_VERSION ) */ + + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + uint32_t ulPC; + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ portOFFSET_TO_PC ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + case portSVC_START_SCHEDULER: + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + + case portSVC_RAISE_PRIVILEGE: + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + + case portSVC_YIELD: + vPortYield(); + break; + + #endif /* configENABLE_MPU == 1 */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} + +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ]; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulSystemCallStack; + uint32_t ulSystemCallLocation, i; + /* Hardware Saved Stack Frame Size upon Exception entry: + * Basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + */ + const uint32_t ulHardwareSavedExceptionFrameSize = 8; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + + #else + + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the system call section (i.e. application is + * not raising SVC directly). + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as + * it is non-NULL only during the execution of a system call (i.e. + * between system call enter and exit). + * 3. System call is not for a kernel API disabled by the configuration + * in FreeRTOSConfig.h. + * 4. We do not need to check that ucSystemCallNumber is within range + * because the assembly SVC handler checks that before calling + * this function. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) && + ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) ) + { + pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack; + + /* Make space on the system call stack for the stack frame. */ + pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulSystemCallStack[ i ] = pulTaskStack[ i ]; + } + + /* Store the value of the Link Register before the SVC was raised. + * It contains the address of the caller of the System Call entry + * point (i.e. the caller of the MPU_). We need to restore it + * when we exit from the system call. */ + pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; + + /* Use the pulSystemCallStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); + + /* Start executing the system call upon returning from this handler. */ + pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; + + /* Raise a request to exit from the system call upon finishing the + * system call. */ + pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; + + /* Remember the location where we should copy the stack frame when we exit from + * the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize; + + /* Record if the hardware used padding to force the stack pointer + * to be double word aligned. */ + if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK ) + { + pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG; + } + else + { + pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG ); + } + + /* We ensure in pxPortInitialiseStack that the system call stack is + * double word aligned and therefore, there is no need of padding. + * Clear the bit[9] of stacked xPSR. */ + pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + + /* Raise the privilege for the duration of the system call. */ + __asm volatile + ( + " .syntax unified \n" + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " bics r0, r1 \n" /* Clear nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */ + { + __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulTaskStack; + uint32_t ulSystemCallLocation, i; + /* Hardware Saved Stack Frame Size upon Exception entry: + * Basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + */ + const uint32_t ulHardwareSavedExceptionFrameSize = 8; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + + #else + + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the privileged code (i.e. application is not + * raising SVC directly). This SVC is only raised from + * vRequestSystemCallExit which is in the privileged code section. + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL - + * this means that we previously entered a system call and the + * application is not attempting to exit without entering a system + * call. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) ) + { + pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack; + + /* Make space on the task stack for the stack frame. */ + pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulTaskStack[ i ] = pulSystemCallStack[ i ]; + } + + /* Use the pulTaskStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) ); + + /* Return to the caller of the System Call entry point (i.e. the + * caller of the MPU_). */ + pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + + /* Ensure that LR has a valid value.*/ + pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + + /* If the hardware used padding to force the stack pointer + * to be double word aligned, set the stacked xPSR bit[9], + * otherwise clear it. */ + if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG ) + { + pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK; + } + else + { + pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + } + + /* This is not NULL only for the duration of the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; + + /* Drop the privilege before returning to the thread mode. */ + __asm volatile + ( + " .syntax unified \n" + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " orrs r0, r1 \n" /* Set nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xTaskIsPrivileged = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xTaskIsPrivileged = pdTRUE; + } + + return xTaskIsPrivileged; + } + +#endif /* configENABLE_MPU == 1 */ + +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged, + xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */ + { + xMPUSettings->ulContext[ 0 ] = 0x04040404; /* r4. */ + xMPUSettings->ulContext[ 1 ] = 0x05050505; /* r5. */ + xMPUSettings->ulContext[ 2 ] = 0x06060606; /* r6. */ + xMPUSettings->ulContext[ 3 ] = 0x07070707; /* r7. */ + xMPUSettings->ulContext[ 4 ] = 0x08080808; /* r8. */ + xMPUSettings->ulContext[ 5 ] = 0x09090909; /* r9. */ + xMPUSettings->ulContext[ 6 ] = 0x10101010; /* r10. */ + xMPUSettings->ulContext[ 7 ] = 0x11111111; /* r11. */ + + xMPUSettings->ulContext[ 8 ] = ( uint32_t ) pvParameters; /* r0. */ + xMPUSettings->ulContext[ 9 ] = 0x01010101; /* r1. */ + xMPUSettings->ulContext[ 10 ] = 0x02020202; /* r2. */ + xMPUSettings->ulContext[ 11 ] = 0x03030303; /* r3. */ + xMPUSettings->ulContext[ 12 ] = 0x12121212; /* r12. */ + xMPUSettings->ulContext[ 13 ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ + xMPUSettings->ulContext[ 14 ] = ( uint32_t ) pxCode; /* PC. */ + xMPUSettings->ulContext[ 15 ] = portINITIAL_XPSR; /* xPSR. */ + + xMPUSettings->ulContext[ 16 ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ + if( xRunPrivileged == pdTRUE ) + { + xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; + xMPUSettings->ulContext[ 17 ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */ + } + else + { + xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG ); + xMPUSettings->ulContext[ 17 ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */ + } + xMPUSettings->ulContext[ 18 ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + { + /* Ensure that the system call stack is double word aligned. */ + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + /* This is not NULL only for the duration of a system call. */ + xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL; + } + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + return &( xMPUSettings->ulContext[ 19 ] ); + } + +#else /* configENABLE_MPU */ + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ + { + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ + } + #endif /* portPRELOAD_REGISTERS */ + + return pxTopOfStack; + } + +#endif /* configENABLE_MPU */ + +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + { + xSchedulerRunning = pdTRUE; + } + #endif + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} + +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} + +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + configSTACK_DEPTH_TYPE uxStackDepth ) + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __SRAM_segment_start__; + extern uint32_t * __SRAM_segment_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __SRAM_segment_start__[]; + extern uint32_t __SRAM_segment_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + + #endif /* defined( __ARMCC_VERSION ) */ + + int32_t lIndex; + uint32_t ul; + + if( xRegions == NULL ) + { + /* No MPU regions are specified so allow access to all RAM. */ + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = + ( ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */ + ( portMPU_RBAR_REGION_NUMBER_VALID_BITMASK ) | + ( portSTACK_REGION ) ); /* Region number. */ + + xMPUSettings->xRegionsSettings[ 0 ].ulRASR = + ( ( portMPU_REGION_PRIV_RW_UNPRIV_RW ) | + ( portMPU_REGION_EXECUTE_NEVER ) | + ( ( configS_C_B_SRAM & portMPU_RASR_S_C_B_BITMASK ) << portMPU_RASR_S_C_B_LOCATION ) | + ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) | + ( portMPU_RASR_REGION_ENABLE_BITMASK ) ); + + + /* Invalidate user configurable regions. */ + for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ ) + { + xMPUSettings->xRegionsSettings[ ul ].ulRBAR = ( ( ul - 1UL ) | portMPU_RBAR_REGION_NUMBER_VALID_BITMASK ); + xMPUSettings->xRegionsSettings[ ul ].ulRASR = 0UL; + } + } + else + { + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that the + * stack region has already been configured. */ + if( uxStackDepth > 0 ) + { + /* Define the region that allows access to the stack. */ + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = + ( ( ( uint32_t ) pxBottomOfStack ) | + ( portMPU_RBAR_REGION_NUMBER_VALID_BITMASK ) | + ( portSTACK_REGION ) ); /* Region number. */ + + xMPUSettings->xRegionsSettings[ 0 ].ulRASR = + ( ( portMPU_REGION_PRIV_RW_UNPRIV_RW ) | + ( portMPU_REGION_EXECUTE_NEVER ) | + ( prvGetMPURegionSizeSetting( uxStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) | + ( ( configS_C_B_SRAM & portMPU_RASR_S_C_B_BITMASK ) << portMPU_RASR_S_C_B_LOCATION ) | + ( portMPU_RASR_REGION_ENABLE_BITMASK ) ); + } + + lIndex = 0; + + for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ ) + { + if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL ) + { + /* Translate the generic region definition contained in + * xRegions into the CM0+ specific MPU settings that are then + * stored in xMPUSettings. */ + xMPUSettings->xRegionsSettings[ ul ].ulRBAR = + ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) | + ( portMPU_RBAR_REGION_NUMBER_VALID_BITMASK ) | + ( ul - 1UL ); /* Region number. */ + + xMPUSettings->xRegionsSettings[ ul ].ulRASR = + ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) | + ( xRegions[ lIndex ].ulParameters ) | + ( portMPU_RASR_REGION_ENABLE_BITMASK ); + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ul ].ulRBAR = ( ( ul - 1UL ) | portMPU_RBAR_REGION_NUMBER_VALID_BITMASK ); + xMPUSettings->xRegionsSettings[ ul ].ulRASR = 0UL; + } + + lIndex++; + } + } +} + +#endif /* configENABLE_MPU */ + +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, + uint32_t ulBufferLength, + uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */ + + { + uint32_t i, ulBufferStartAddress, ulBufferEndAddress; + uint32_t ulRegionStart, ulRegionSize, ulRegionEnd; + uint32_t ulMPURegionAccessPermissions; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE ) + { + ulBufferStartAddress = ( uint32_t ) pvBuffer; + ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL ); + + for( i = 0; i < portTOTAL_NUM_REGIONS; i++ ) + { + /* Is the MPU region enabled? */ + if( ( xTaskMpuSettings->xRegionsSettings[ i ].ulRASR & + portMPU_RASR_REGION_ENABLE_BITMASK ) == portMPU_RASR_REGION_ENABLE_BITMASK ) + { + ulRegionStart = portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ); + ulRegionSize = portEXTRACT_REGION_SIZE_FROM_RASR( xTaskMpuSettings->xRegionsSettings[ i ].ulRASR ); + ulRegionEnd = ulRegionStart + ulRegionSize; + + if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress, + ulRegionStart, + ulRegionEnd ) && + portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress, + ulRegionStart, + ulRegionEnd ) ) + { + ulMPURegionAccessPermissions = xTaskMpuSettings->xRegionsSettings[ i ].ulRASR & + portMPU_RASR_AP_BITMASK; + + if( ulAccessRequested == tskMPU_READ_PERMISSION ) /* RO. */ + { + if( ( ulMPURegionAccessPermissions == portMPU_REGION_PRIV_RW_UNPRIV_RO ) || + ( ulMPURegionAccessPermissions == portMPU_REGION_PRIV_RO_UNPRIV_RO ) || + ( ulMPURegionAccessPermissions == portMPU_REGION_PRIV_RW_UNPRIV_RW ) ) + { + xAccessGranted = pdTRUE; + break; + } + } + else if( ( ulAccessRequested & tskMPU_WRITE_PERMISSION ) != 0UL ) /* W or RW. */ + { + if( ulMPURegionAccessPermissions == portMPU_REGION_PRIV_RW_UNPRIV_RW ) + { + xAccessGranted = pdTRUE; + break; + } + } + } + } + } + } + } + + return xAccessGranted; + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ + +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} + +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ + +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ + +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings; + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else + { + xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 ) + { + xAccessGranted = pdTRUE; + } + } + } + + return xAccessGranted; + } + + #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + ( void ) lInternalIndexOfKernelObject; + + /* If Access Control List feature is not used, all the tasks have + * access to all the kernel objects. */ + return pdTRUE; + } + + #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ + +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM0/portasm.c b/portable/GCC/ARM_CM0/portasm.c new file mode 100644 index 000000000..179a71546 --- /dev/null +++ b/portable/GCC/ARM_CM0/portasm.c @@ -0,0 +1,526 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION + * is defined correctly and privileged functions are placed in correct sections. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Portasm includes. */ +#include "portasm.h" + +/* System call numbers includes. */ +#include "mpu_syscall_numbers.h" + +/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the + * header files. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#if ( configENABLE_MPU == 1 ) + + void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .extern pxCurrentTCB \n" + " .syntax unified \n" + " \n" + " program_mpu_first_task: \n" + " \n" + " ldr r3, =pxCurrentTCB \n" /* r3 = &pxCurrentTCB. */ + " ldr r0, [r3] \n" /* r0 = pxCurrentTCB.*/ + " adds r0, #4 \n" /* r0 = Second item in the TCB which is xMPUSettings. */ + " \n" + " dmb \n" /* Complete outstanding transfers before disabling MPU. */ + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " movs r3, #1 \n" /* r3 = 1. */ + " bics r2, r3 \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */ + " str r2, [r1] \n" /* Disable MPU. */ + " \n" + " ldr r1, =0xe000ed9c \n" /* r1 = 0xe000ed9c [Location of RBAR]. */ + " ldr r2, =0xe000eda0 \n" /* r2 = 0xe000eda0 [Location of RASR]. */ + " \n" + " ldmia r0!, {r3-r4} \n" /* Read first set of RBAR/RASR registers from TCB. */ + " str r3, [r1] \n" /* Program RBAR. */ + " str r4, [r2] \n" /* Program RASR. */ + " \n" + " ldmia r0!, {r3-r4} \n" /* Read second set of RBAR/RASR registers from TCB. */ + " str r3, [r1] \n" /* Program RBAR. */ + " str r4, [r2] \n" /* Program RASR. */ + " \n" + " ldmia r0!, {r3-r4} \n" /* Read third set of RBAR/RASR registers from TCB. */ + " str r3, [r1] \n" /* Program RBAR. */ + " str r4, [r2] \n" /* Program RASR. */ + " \n" + " ldmia r0!, {r3-r4} \n" /* Read fourth set of RBAR/RASR registers from TCB. */ + " str r3, [r1] \n" /* Program RBAR. */ + " str r4, [r2] \n" /* Program RASR. */ + " \n" + " ldmia r0!, {r3-r4} \n" /* Read fifth set of RBAR/RASR registers from TCB. */ + " str r3, [r1] \n" /* Program RBAR. */ + " str r4, [r2] \n" /* Program RASR. */ + " \n" + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " movs r3, #1 \n" /* r3 = 1. */ + " orrs r2, r3 \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */ + " str r2, [r1] \n" /* Enable MPU. */ + " dsb \n" /* Force memory writes before continuing. */ + " \n" + " restore_context_first_task: \n" + " ldr r2, =pxCurrentTCB \n" /* r2 = &pxCurrentTCB. */ + " ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/ + " ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */ + " \n" + " restore_special_regs_first_task: \n" + " subs r1, #12 \n" + " ldmia r1!, {r2-r4} \n" /* r2 = original PSP, r3 = CONTROL, r4 = LR. */ + " subs r1, #12 \n" + " msr psp, r2 \n" + " msr control, r3 \n" + " mov lr, r4 \n" + " \n" + " restore_general_regs_first_task: \n" + " subs r1, #32 \n" + " ldmia r1!, {r4-r7} \n" /* r4-r7 contain half of the hardware saved context. */ + " stmia r2!, {r4-r7} \n" /* Copy half of the the hardware saved context on the task stack. */ + " ldmia r1!, {r4-r7} \n" /* r4-r7 contain rest half of the hardware saved context. */ + " stmia r2!, {r4-r7} \n" /* Copy rest half of the the hardware saved context on the task stack. */ + " subs r1, #48 \n" + " ldmia r1!, {r4-r7} \n" /* Restore r8-r11. */ + " mov r8, r4 \n" /* r8 = r4. */ + " mov r9, r5 \n" /* r9 = r5. */ + " mov r10, r6 \n" /* r10 = r6. */ + " mov r11, r7 \n" /* r11 = r7. */ + " subs r1, #32 \n" + " ldmia r1!, {r4-r7} \n" /* Restore r4-r7. */ + " subs r1, #16 \n" + " \n" + " restore_context_done_first_task: \n" + " str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */ + " bx lr \n" + " \n" + " .align 4 \n" + ::"i" ( portSVC_START_SCHEDULER ) : "memory" + ); + } + +#else /* configENABLE_MPU */ + + void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .extern pxCurrentTCB \n" + " .syntax unified \n" + " \n" + " ldr r2, =pxCurrentTCB \n" /* r2 = &pxCurrentTCB. */ + " ldr r1, [r2] \n" /* r1 = pxCurrentTCB.*/ + " ldr r0, [r1] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + " \n" + " ldm r0!, {r2} \n" /* Read from stack - r2 = EXC_RETURN. */ + " movs r1, #2 \n" /* r1 = 2. */ + " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */ + " adds r0, #32 \n" /* Discard everything up to r0. */ + " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */ + " isb \n" + " bx r2 \n" /* Finally, branch to EXC_RETURN. */ + " \n" + " .align 4 \n" + ); + } + +#endif /* configENABLE_MPU */ + +/*-----------------------------------------------------------*/ + +BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* r0 = CONTROL. */ + " movs r1, #1 \n" /* r1 = 1. */ + " tst r0, r1 \n" /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */ + " beq running_privileged \n" /* If the result of previous AND operation was 0, branch. */ + " movs r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + " bx lr \n" /* Return. */ + " running_privileged: \n" + " movs r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + " bx lr \n" /* Return. */ + " \n" + " .align 4 \n" + ::: "r0", "r1", "memory" + ); +} + +/*-----------------------------------------------------------*/ + +void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* Read the CONTROL register. */ + " movs r1, #1 \n" /* r1 = 1. */ + " bics r0, r1 \n" /* Clear the bit 0. */ + " msr control, r0 \n" /* Write back the new CONTROL value. */ + " bx lr \n" /* Return to the caller. */ + ::: "r0", "r1", "memory" + ); +} + +/*-----------------------------------------------------------*/ + +void vResetPrivilege( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* r0 = CONTROL. */ + " movs r1, #1 \n" /* r1 = 1. */ + " orrs r0, r1 \n" /* r0 = r0 | r1. */ + " msr control, r0 \n" /* CONTROL = r0. */ + " bx lr \n" /* Return to the caller. */ + ::: "r0", "r1", "memory" + ); +} + +/*-----------------------------------------------------------*/ + +void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + /* Don't reset the MSP stack as is done on CM3/4 devices. The reason is that + * the Vector Table Offset Register (VTOR) is optional in CM0+ architecture + * and therefore, may not be available on all the devices. */ + __asm volatile + ( + " .syntax unified \n" + " cpsie i \n" /* Globally enable interrupts. */ + " dsb \n" + " isb \n" + " svc %0 \n" /* System call to start the first task. */ + " nop \n" + " \n" + " .align 4 \n" + ::"i" ( portSVC_START_SCHEDULER ) : "memory" + ); +} + +/*-----------------------------------------------------------*/ + +uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, PRIMASK \n" + " cpsid i \n" + " bx lr \n" + ::: "memory" + ); +} + +/*-----------------------------------------------------------*/ + +void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " msr PRIMASK, r0 \n" + " bx lr \n" + ::: "memory" + ); +} + +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .extern pxCurrentTCB \n" + " .syntax unified \n" + " \n" + " ldr r2, =pxCurrentTCB \n" /* r2 = &( pxCurrentTCB ). */ + " ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */ + " ldr r1, [r0] \n" /* r1 = Location in TCB where the context should be saved. */ + " mrs r2, psp \n" /* r2 = PSP. */ + " \n" + " save_general_regs: \n" + " stmia r1!, {r4-r7} \n" /* Store r4-r7. */ + " mov r4, r8 \n" /* r4 = r8. */ + " mov r5, r9 \n" /* r5 = r9. */ + " mov r6, r10 \n" /* r6 = r10. */ + " mov r7, r11 \n" /* r7 = r11. */ + " stmia r1!, {r4-r7} \n" /* Store r8-r11. */ + " ldmia r2!, {r4-r7} \n" /* Copy half of the hardware saved context into r4-r7. */ + " stmia r1!, {r4-r7} \n" /* Store the hardware saved context. */ + " ldmia r2!, {r4-r7} \n" /* Copy rest half of the hardware saved context into r4-r7. */ + " stmia r1!, {r4-r7} \n" /* Store the hardware saved context. */ + " \n" + " save_special_regs: \n" + " mrs r2, psp \n" /* r2 = PSP. */ + " mrs r3, control \n" /* r3 = CONTROL. */ + " mov r4, lr \n" /* r4 = LR. */ + " stmia r1!, {r2-r4} \n" /* Store original PSP (after hardware has saved context), CONTROL and LR. */ + " str r1, [r0] \n" /* Save the location from where the context should be restored as the first member of TCB. */ + " \n" + " select_next_task: \n" + " cpsid i \n" + " bl vTaskSwitchContext \n" + " cpsie i \n" + " \n" + " program_mpu: \n" + " \n" + " ldr r2, =pxCurrentTCB \n" /* r2 = &( pxCurrentTCB ). */ + " ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */ + " adds r0, #4 \n" /* r0 = Second item in the TCB which is xMPUSettings. */ + " \n" + " dmb \n" /* Complete outstanding transfers before disabling MPU. */ + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " movs r3, #1 \n" /* r3 = 1. */ + " bics r2, r3 \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */ + " str r2, [r1] \n" /* Disable MPU */ + " \n" + " ldr r1, =0xe000ed9c \n" /* r1 = 0xe000ed9c [Location of RBAR]. */ + " ldr r2, =0xe000eda0 \n" /* r2 = 0xe000eda0 [Location of RASR]. */ + " \n" + " ldmia r0!, {r3-r4} \n" /* Read first set of RBAR/RASR registers from TCB. */ + " str r3, [r1] \n" /* Program RBAR. */ + " str r4, [r2] \n" /* Program RASR. */ + " \n" + " ldmia r0!, {r3-r4} \n" /* Read second set of RBAR/RASR registers from TCB. */ + " str r3, [r1] \n" /* Program RBAR. */ + " str r4, [r2] \n" /* Program RASR. */ + " \n" + " ldmia r0!, {r3-r4} \n" /* Read third set of RBAR/RASR registers from TCB. */ + " str r3, [r1] \n" /* Program RBAR. */ + " str r4, [r2] \n" /* Program RASR. */ + " \n" + " ldmia r0!, {r3-r4} \n" /* Read fourth set of RBAR/RASR registers from TCB. */ + " str r3, [r1] \n" /* Program RBAR. */ + " str r4, [r2] \n" /* Program RASR. */ + " \n" + " ldmia r0!, {r3-r4} \n" /* Read fifth set of RBAR/RASR registers from TCB. */ + " str r3, [r1] \n" /* Program RBAR. */ + " str r4, [r2] \n" /* Program RASR. */ + " \n" + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " movs r3, #1 \n" /* r3 = 1. */ + " orrs r2, r3 \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */ + " str r2, [r1] \n" /* Enable MPU. */ + " dsb \n" /* Force memory writes before continuing. */ + " \n" + " restore_context: \n" + " ldr r2, =pxCurrentTCB \n" /* r2 = &pxCurrentTCB. */ + " ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/ + " ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */ + " \n" + " restore_special_regs: \n" + " subs r1, #12 \n" + " ldmia r1!, {r2-r4} \n" /* r2 = original PSP, r3 = CONTROL, r4 = LR. */ + " subs r1, #12 \n" + " msr psp, r2 \n" + " msr control, r3 \n" + " mov lr, r4 \n" + " \n" + " restore_general_regs: \n" + " subs r1, #32 \n" + " ldmia r1!, {r4-r7} \n" /* r4-r7 contain half of the hardware saved context. */ + " stmia r2!, {r4-r7} \n" /* Copy half of the the hardware saved context on the task stack. */ + " ldmia r1!, {r4-r7} \n" /* r4-r7 contain rest half of the hardware saved context. */ + " stmia r2!, {r4-r7} \n" /* Copy rest half of the the hardware saved context on the task stack. */ + " subs r1, #48 \n" + " ldmia r1!, {r4-r7} \n" /* Restore r8-r11. */ + " mov r8, r4 \n" /* r8 = r4. */ + " mov r9, r5 \n" /* r9 = r5. */ + " mov r10, r6 \n" /* r10 = r6. */ + " mov r11, r7 \n" /* r11 = r7. */ + " subs r1, #32 \n" + " ldmia r1!, {r4-r7} \n" /* Restore r4-r7. */ + " subs r1, #16 \n" + " \n" + " restore_context_done: \n" + " str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */ + " bx lr \n" + " \n" + " .align 4 \n" + ); + } + +#else /* configENABLE_MPU */ + + void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .extern pxCurrentTCB \n" + " .syntax unified \n" + " \n" + " mrs r0, psp \n" /* Read PSP in r0. */ + " ldr r2, =pxCurrentTCB \n" /* r2 = &( pxCurrentTCB ). */ + " ldr r1, [r2] \n" /* r1 = pxCurrentTCB. */ + " subs r0, r0, #36 \n" /* Make space for LR and the remaining registers on the stack. */ + " str r0, [r1] \n" /* Save the new top of stack in TCB. */ + " \n" + " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */ + " stmia r0!, {r3-r7} \n" /* Store on the stack - LR and low registers that are not automatically saved. */ + " mov r4, r8 \n" /* r4 = r8. */ + " mov r5, r9 \n" /* r5 = r9. */ + " mov r6, r10 \n" /* r6 = r10. */ + " mov r7, r11 \n" /* r7 = r11. */ + " stmia r0!, {r4-r7} \n" /* Store the high registers that are not saved automatically. */ + " \n" + " cpsid i \n" + " bl vTaskSwitchContext \n" + " cpsie i \n" + " \n" + " ldr r2, =pxCurrentTCB \n" /* r2 = &( pxCurrentTCB ). */ + " ldr r1, [r2] \n" /* r1 = pxCurrentTCB. */ + " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ + " \n" + " adds r0, r0, #20 \n" /* Move to the high registers. */ + " ldmia r0!, {r4-r7} \n" /* Restore the high registers that are not automatically restored. */ + " mov r8, r4 \n" /* r8 = r4. */ + " mov r9, r5 \n" /* r9 = r5. */ + " mov r10, r6 \n" /* r10 = r6. */ + " mov r11, r7 \n" /* r11 = r7. */ + " msr psp, r0 \n" /* Remember the new top of stack for the task. */ + " subs r0, r0, #36 \n" /* Move to the starting of the saved context. */ + " ldmia r0!, {r3-r7} \n" /* Read from stack - r3 = LR and r4-r7 restored. */ + " bx r3 \n" + " \n" + " .align 4 \n" + ); + } + +#endif /* configENABLE_MPU */ + +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern vPortSVCHandler_C \n" + " .extern vSystemCallEnter \n" + " .extern vSystemCallExit \n" + " .extern pxCurrentTCB \n" + " \n" + " movs r0, #4 \n" + " mov r1, lr \n" + " tst r0, r1 \n" + " beq stack_on_msp \n" + " \n" + " stack_on_psp: \n" + " mrs r0, psp \n" + " b route_svc \n" + " \n" + " stack_on_msp: \n" + " mrs r0, msp \n" + " b route_svc \n" + " \n" + " route_svc: \n" + " ldr r3, [r0, #24] \n" + " subs r3, #2 \n" + " ldrb r2, [r3, #0] \n" + " ldr r3, =%0 \n" + " cmp r2, r3 \n" + " blt system_call_enter \n" + " ldr r3, =%1 \n" + " cmp r2, r3 \n" + " beq system_call_exit \n" + " ldr r3, =vPortSVCHandler_C \n" + " bx r3 \n" + " \n" + " system_call_enter: \n" + " push {lr} \n" + " bl vSystemCallEnter \n" + " pop {pc} \n" + " \n" + " system_call_exit: \n" + " push {lr} \n" + " bl vSystemCallExit \n" + " pop {pc} \n" + " \n" + " .align 4 \n" + " \n" + : /* No outputs. */ + : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT ) + : "r0", "r1", "r2", "r3", "memory" + ); + } + +#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern vPortSVCHandler_C \n" + " \n" + " movs r0, #4 \n" + " mov r1, lr \n" + " tst r0, r1 \n" + " beq stacking_used_msp \n" + " \n" + " stacking_used_psp: \n" + " mrs r0, psp \n" + " ldr r3, =vPortSVCHandler_C \n" + " bx r3 \n" + " \n" + " stacking_used_msp: \n" + " mrs r0, msp \n" + " ldr r3, =vPortSVCHandler_C \n" + " bx r3 \n" + " \n" + " .align 4 \n" + ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM0/portasm.h b/portable/GCC/ARM_CM0/portasm.h new file mode 100644 index 000000000..346507531 --- /dev/null +++ b/portable/GCC/ARM_CM0/portasm.h @@ -0,0 +1,99 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kernel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/portable/GCC/ARM_CM0/portmacro.h b/portable/GCC/ARM_CM0/portmacro.h new file mode 100644 index 000000000..5acb2dcd2 --- /dev/null +++ b/portable/GCC/ARM_CM0/portmacro.h @@ -0,0 +1,389 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. +#endif /* configENABLE_MPU */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M0+" +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() +#define portINLINE __inline +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif +#define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ +extern BaseType_t xPortIsInsideInterrupt( void ); + +extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + +extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; +extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + +extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; +extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + +#if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ +#if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) +#else + #define portPRIVILEGE_BIT ( 0x0UL ) +#endif /* configENABLE_MPU */ + +/* Shareable (S), Cacheable (C) and Bufferable (B) bits for flash region. */ +#ifndef configS_C_B_FLASH + #define configS_C_B_FLASH ( 0x07UL ) +#endif + +/* Shareable (S), Cacheable (C) and Bufferable (B) bits for RAM region. */ +#ifndef configS_C_B_SRAM + #define configS_C_B_SRAM ( 0x07UL ) +#endif + +/* MPU regions. */ +#define portPRIVILEGED_RAM_REGION ( 7UL ) +#define portPRIVILEGED_FLASH_REGION ( 6UL ) +#define portUNPRIVILEGED_FLASH_REGION ( 5UL ) +#define portSTACK_REGION ( 4UL ) +#define portFIRST_CONFIGURABLE_REGION ( 0UL ) +#define portLAST_CONFIGURABLE_REGION ( 3UL ) +#define portNUM_CONFIGURABLE_REGIONS ( 4UL ) +#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1UL ) /* Plus one to make space for the stack region. */ + +/* MPU region sizes. This information is encoded in the SIZE bits of the MPU + * Region Attribute and Size Register (RASR). */ +#define portMPU_REGION_SIZE_256B ( 0x07UL << 1UL ) +#define portMPU_REGION_SIZE_512B ( 0x08UL << 1UL ) +#define portMPU_REGION_SIZE_1KB ( 0x09UL << 1UL ) +#define portMPU_REGION_SIZE_2KB ( 0x0AUL << 1UL ) +#define portMPU_REGION_SIZE_4KB ( 0x0BUL << 1UL ) +#define portMPU_REGION_SIZE_8KB ( 0x0CUL << 1UL ) +#define portMPU_REGION_SIZE_16KB ( 0x0DUL << 1UL ) +#define portMPU_REGION_SIZE_32KB ( 0x0EUL << 1UL ) +#define portMPU_REGION_SIZE_64KB ( 0x0FUL << 1UL ) +#define portMPU_REGION_SIZE_128KB ( 0x10UL << 1UL ) +#define portMPU_REGION_SIZE_256KB ( 0x11UL << 1UL ) +#define portMPU_REGION_SIZE_512KB ( 0x12UL << 1UL ) +#define portMPU_REGION_SIZE_1MB ( 0x13UL << 1UL ) +#define portMPU_REGION_SIZE_2MB ( 0x14UL << 1UL ) +#define portMPU_REGION_SIZE_4MB ( 0x15UL << 1UL ) +#define portMPU_REGION_SIZE_8MB ( 0x16UL << 1UL ) +#define portMPU_REGION_SIZE_16MB ( 0x17UL << 1UL ) +#define portMPU_REGION_SIZE_32MB ( 0x18UL << 1UL ) +#define portMPU_REGION_SIZE_64MB ( 0x19UL << 1UL ) +#define portMPU_REGION_SIZE_128MB ( 0x1AUL << 1UL ) +#define portMPU_REGION_SIZE_256MB ( 0x1BUL << 1UL ) +#define portMPU_REGION_SIZE_512MB ( 0x1CUL << 1UL ) +#define portMPU_REGION_SIZE_1GB ( 0x1DUL << 1UL ) +#define portMPU_REGION_SIZE_2GB ( 0x1EUL << 1UL ) +#define portMPU_REGION_SIZE_4GB ( 0x1FUL << 1UL ) + +/* MPU memory types. This information is encoded in the S ( Shareable), C + * (Cacheable) and B (Bufferable) bits of the MPU Region Attribute and Size + * Register (RASR). */ +#define portMPU_REGION_STRONGLY_ORDERED_SHAREABLE ( 0x0UL << 16UL ) /* S=NA, C=0, B=0. */ +#define portMPU_REGION_DEVICE_SHAREABLE ( 0x1UL << 16UL ) /* S=NA, C=0, B=1. */ +#define portMPU_REGION_NORMAL_OIWTNOWA_NONSHARED ( 0x2UL << 16UL ) /* S=0, C=1, B=0. */ +#define portMPU_REGION_NORMAL_OIWTNOWA_SHARED ( 0x6UL << 16UL ) /* S=1, C=1, B=0. */ +#define portMPU_REGION_NORMAL_OIWBNOWA_NONSHARED ( 0x3UL << 16UL ) /* S=0, C=1, B=1.*/ +#define portMPU_REGION_NORMAL_OIWBNOWA_SHARED ( 0x7UL << 16UL ) /* S=1, C=1, B=1.*/ + +/* MPU access permissions. This information is encoded in the AP and XN bits of + * the MPU Region Attribute and Size Register (RASR). */ +#define portMPU_REGION_PRIV_NA_UNPRIV_NA ( 0x0UL << 24UL ) +#define portMPU_REGION_PRIV_RW_UNPRIV_NA ( 0x1UL << 24UL ) +#define portMPU_REGION_PRIV_RW_UNPRIV_RO ( 0x2UL << 24UL ) +#define portMPU_REGION_PRIV_RW_UNPRIV_RW ( 0x3UL << 24UL ) +#define portMPU_REGION_PRIV_RO_UNPRIV_NA ( 0x5UL << 24UL ) +#define portMPU_REGION_PRIV_RO_UNPRIV_RO ( 0x6UL << 24UL ) +#define portMPU_REGION_EXECUTE_NEVER ( 0x1UL << 28UL ) + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< MPU Region Base Address Register (RBAR) for the region. */ + uint32_t ulRASR; /**< MPU Region Attribute and Size Register (RASR) for the region. */ + } MPURegionSettings_t; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + #ifndef configSYSTEM_CALL_STACK_SIZE + #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. + #endif + + /** + * @brief System call stack. + */ + typedef struct SYSTEM_CALL_STACK_INFO + { + uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; + uint32_t * pulSystemCallStack; + uint32_t * pulTaskStack; + uint32_t ulLinkRegisterAtSystemCallEntry; + } xSYSTEM_CALL_STACK_INFO; + + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + /** + * @brief MPU settings as stored in the TCB. + */ + + /* + * +----------+-----------------+---------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+---------------+-----+ + * + * <---------><----------------><---------------><----> + * 8 8 3 1 + */ + #define CONTEXT_SIZE 20 + + /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) + + /* Size of an Access Control List (ACL) entry in bits. */ + #define portACL_ENTRY_SIZE_BITS ( 32U ) + + typedef struct MPU_SETTINGS + { + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + uint32_t ulContext[ CONTEXT_SIZE ]; + uint32_t ulTaskFlags; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo; + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ]; + #endif + #endif + } xMPU_SETTINGS; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief SVC numbers. + */ +#define portSVC_START_SCHEDULER 100 +#define portSVC_RAISE_PRIVILEGE 101 +#define portSVC_SYSTEM_CALL_EXIT 102 +#define portSVC_YIELD 103 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) +#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" ) +#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org website. + */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + + /** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + + /** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() + +#else + + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + extern BaseType_t xPortIsTaskPrivileged( void ); + + /** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c new file mode 100644 index 000000000..7a62caff0 --- /dev/null +++ b/portable/GCC/ARM_CM23/non_secure/mpu_wrappers_v2_asm.c @@ -0,0 +1,2125 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" +#include "event_groups.h" +#include "stream_buffer.h" +#include "mpu_prototypes.h" +#include "mpu_syscall_numbers.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( INCLUDE_xTaskDelayUntil == 1 ) + + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskDelayUntilImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskDelayUntil_Unpriv \n" + " MPU_xTaskDelayUntil_Priv: \n" + " b MPU_xTaskDelayUntilImpl \n" + " MPU_xTaskDelayUntil_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskAbortDelayImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskAbortDelay_Unpriv \n" + " MPU_xTaskAbortDelay_Priv: \n" + " b MPU_xTaskAbortDelayImpl \n" + " MPU_xTaskAbortDelay_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskDelay == 1 ) + + void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskDelayImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vTaskDelay_Unpriv \n" + " MPU_vTaskDelay_Priv: \n" + " b MPU_vTaskDelayImpl \n" + " MPU_vTaskDelay_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskPriorityGet == 1 ) + + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskPriorityGetImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_uxTaskPriorityGet_Unpriv \n" + " MPU_uxTaskPriorityGet_Priv: \n" + " b MPU_uxTaskPriorityGetImpl \n" + " MPU_uxTaskPriorityGet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_eTaskGetState == 1 ) + + eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_eTaskGetStateImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_eTaskGetState_Unpriv \n" + " MPU_eTaskGetState_Priv: \n" + " b MPU_eTaskGetStateImpl \n" + " MPU_eTaskGetState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory" + ); + } + + #endif /* if ( INCLUDE_eTaskGetState == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskGetInfoImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vTaskGetInfo_Unpriv \n" + " MPU_vTaskGetInfo_Priv: \n" + " b MPU_vTaskGetInfoImpl \n" + " MPU_vTaskGetInfo_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory" + ); + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) + + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetIdleTaskHandleImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskGetIdleTaskHandle_Unpriv \n" + " MPU_xTaskGetIdleTaskHandle_Priv: \n" + " b MPU_xTaskGetIdleTaskHandleImpl \n" + " MPU_xTaskGetIdleTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + + void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSuspendImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vTaskSuspend_Unpriv \n" + " MPU_vTaskSuspend_Priv: \n" + " b MPU_vTaskSuspendImpl \n" + " MPU_vTaskSuspend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + + void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskResumeImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vTaskResume_Unpriv \n" + " MPU_vTaskResume_Priv: \n" + " b MPU_vTaskResumeImpl \n" + " MPU_vTaskResume_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + TickType_t MPU_xTaskGetTickCount( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetTickCountImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskGetTickCount_Unpriv \n" + " MPU_xTaskGetTickCount_Priv: \n" + " b MPU_xTaskGetTickCountImpl \n" + " MPU_xTaskGetTickCount_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetNumberOfTasksImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_uxTaskGetNumberOfTasks_Unpriv \n" + " MPU_uxTaskGetNumberOfTasks_Priv: \n" + " b MPU_uxTaskGetNumberOfTasksImpl \n" + " MPU_uxTaskGetNumberOfTasks_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetRunTimeCounterImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_ulTaskGetRunTimeCounter_Unpriv \n" + " MPU_ulTaskGetRunTimeCounter_Priv: \n" + " b MPU_ulTaskGetRunTimeCounterImpl \n" + " MPU_ulTaskGetRunTimeCounter_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetRunTimePercentImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_ulTaskGetRunTimePercent_Unpriv \n" + " MPU_ulTaskGetRunTimePercent_Priv: \n" + " b MPU_ulTaskGetRunTimePercentImpl \n" + " MPU_ulTaskGetRunTimePercent_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetIdleRunTimePercentImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv \n" + " MPU_ulTaskGetIdleRunTimePercent_Priv: \n" + " b MPU_ulTaskGetIdleRunTimePercentImpl \n" + " MPU_ulTaskGetIdleRunTimePercent_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetIdleRunTimeCounterImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv \n" + " MPU_ulTaskGetIdleRunTimeCounter_Priv: \n" + " b MPU_ulTaskGetIdleRunTimeCounterImpl \n" + " MPU_ulTaskGetIdleRunTimeCounter_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetApplicationTaskTagImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vTaskSetApplicationTaskTag_Unpriv \n" + " MPU_vTaskSetApplicationTaskTag_Priv: \n" + " b MPU_vTaskSetApplicationTaskTagImpl \n" + " MPU_vTaskSetApplicationTaskTag_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory" + ); + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetApplicationTaskTagImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskGetApplicationTaskTag_Unpriv \n" + " MPU_xTaskGetApplicationTaskTag_Priv: \n" + " b MPU_xTaskGetApplicationTaskTagImpl \n" + " MPU_xTaskGetApplicationTaskTag_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory" + ); + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetThreadLocalStoragePointerImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv \n" + " MPU_vTaskSetThreadLocalStoragePointer_Priv: \n" + " b MPU_vTaskSetThreadLocalStoragePointerImpl \n" + " MPU_vTaskSetThreadLocalStoragePointer_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory" + ); + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv \n" + " MPU_pvTaskGetThreadLocalStoragePointer_Priv: \n" + " b MPU_pvTaskGetThreadLocalStoragePointerImpl \n" + " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory" + ); + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetSystemStateImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_uxTaskGetSystemState_Unpriv \n" + " MPU_uxTaskGetSystemState_Priv: \n" + " b MPU_uxTaskGetSystemStateImpl \n" + " MPU_uxTaskGetSystemState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory" + ); + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) + + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetStackHighWaterMarkImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_uxTaskGetStackHighWaterMark_Unpriv \n" + " MPU_uxTaskGetStackHighWaterMark_Priv: \n" + " b MPU_uxTaskGetStackHighWaterMarkImpl \n" + " MPU_uxTaskGetStackHighWaterMark_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetStackHighWaterMark2Impl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv \n" + " MPU_uxTaskGetStackHighWaterMark2_Priv: \n" + " b MPU_uxTaskGetStackHighWaterMark2Impl \n" + " MPU_uxTaskGetStackHighWaterMark2_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) + + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetCurrentTaskHandleImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskGetCurrentTaskHandle_Unpriv \n" + " MPU_xTaskGetCurrentTaskHandle_Priv: \n" + " b MPU_xTaskGetCurrentTaskHandleImpl \n" + " MPU_xTaskGetCurrentTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory" + ); + } + + #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetSchedulerState == 1 ) + + BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetSchedulerStateImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskGetSchedulerState_Unpriv \n" + " MPU_xTaskGetSchedulerState_Priv: \n" + " b MPU_xTaskGetSchedulerStateImpl \n" + " MPU_xTaskGetSchedulerState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */ +/*-----------------------------------------------------------*/ + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetTimeOutStateImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vTaskSetTimeOutState_Unpriv \n" + " MPU_vTaskSetTimeOutState_Priv: \n" + " b MPU_vTaskSetTimeOutStateImpl \n" + " MPU_vTaskSetTimeOutState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskCheckForTimeOutImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskCheckForTimeOut_Unpriv \n" + " MPU_xTaskCheckForTimeOut_Priv: \n" + " b MPU_xTaskCheckForTimeOutImpl \n" + " MPU_xTaskCheckForTimeOut_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskGenericNotify_Unpriv \n" + " MPU_xTaskGenericNotify_Priv: \n" + " b MPU_xTaskGenericNotifyImpl \n" + " MPU_xTaskGenericNotify_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyWaitImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskGenericNotifyWait_Unpriv \n" + " MPU_xTaskGenericNotifyWait_Priv: \n" + " b MPU_xTaskGenericNotifyWaitImpl \n" + " MPU_xTaskGenericNotifyWait_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGenericNotifyTakeImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_ulTaskGenericNotifyTake_Unpriv \n" + " MPU_ulTaskGenericNotifyTake_Priv: \n" + " b MPU_ulTaskGenericNotifyTakeImpl \n" + " MPU_ulTaskGenericNotifyTake_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyStateClearImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskGenericNotifyStateClear_Unpriv \n" + " MPU_xTaskGenericNotifyStateClear_Priv: \n" + " b MPU_xTaskGenericNotifyStateClearImpl \n" + " MPU_xTaskGenericNotifyStateClear_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGenericNotifyValueClearImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_ulTaskGenericNotifyValueClear_Unpriv \n" + " MPU_ulTaskGenericNotifyValueClear_Priv: \n" + " b MPU_ulTaskGenericNotifyValueClearImpl \n" + " MPU_ulTaskGenericNotifyValueClear_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGenericSendImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xQueueGenericSend_Unpriv \n" + " MPU_xQueueGenericSend_Priv: \n" + " b MPU_xQueueGenericSendImpl \n" + " MPU_xQueueGenericSend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxQueueMessagesWaitingImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_uxQueueMessagesWaiting_Unpriv \n" + " MPU_uxQueueMessagesWaiting_Priv: \n" + " b MPU_uxQueueMessagesWaitingImpl \n" + " MPU_uxQueueMessagesWaiting_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxQueueSpacesAvailableImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_uxQueueSpacesAvailable_Unpriv \n" + " MPU_uxQueueSpacesAvailable_Priv: \n" + " b MPU_uxQueueSpacesAvailableImpl \n" + " MPU_uxQueueSpacesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueReceiveImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xQueueReceive_Unpriv \n" + " MPU_xQueueReceive_Priv: \n" + " b MPU_xQueueReceiveImpl \n" + " MPU_xQueueReceive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueuePeekImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xQueuePeek_Unpriv \n" + " MPU_xQueuePeek_Priv: \n" + " b MPU_xQueuePeekImpl \n" + " MPU_xQueuePeek_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueSemaphoreTakeImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xQueueSemaphoreTake_Unpriv \n" + " MPU_xQueueSemaphoreTake_Priv: \n" + " b MPU_xQueueSemaphoreTakeImpl \n" + " MPU_xQueueSemaphoreTake_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) + + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGetMutexHolderImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xQueueGetMutexHolder_Unpriv \n" + " MPU_xQueueGetMutexHolder_Priv: \n" + " b MPU_xQueueGetMutexHolderImpl \n" + " MPU_xQueueGetMutexHolder_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory" + ); + } + + #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueTakeMutexRecursiveImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xQueueTakeMutexRecursive_Unpriv \n" + " MPU_xQueueTakeMutexRecursive_Priv: \n" + " b MPU_xQueueTakeMutexRecursiveImpl \n" + " MPU_xQueueTakeMutexRecursive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory" + ); + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGiveMutexRecursiveImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xQueueGiveMutexRecursive_Unpriv \n" + " MPU_xQueueGiveMutexRecursive_Priv: \n" + " b MPU_xQueueGiveMutexRecursiveImpl \n" + " MPU_xQueueGiveMutexRecursive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory" + ); + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueSelectFromSetImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xQueueSelectFromSet_Unpriv \n" + " MPU_xQueueSelectFromSet_Priv: \n" + " b MPU_xQueueSelectFromSetImpl \n" + " MPU_xQueueSelectFromSet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory" + ); + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueAddToSetImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xQueueAddToSet_Unpriv \n" + " MPU_xQueueAddToSet_Priv: \n" + " b MPU_xQueueAddToSetImpl \n" + " MPU_xQueueAddToSet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory" + ); + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vQueueAddToRegistryImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vQueueAddToRegistry_Unpriv \n" + " MPU_vQueueAddToRegistry_Priv: \n" + " b MPU_vQueueAddToRegistryImpl \n" + " MPU_vQueueAddToRegistry_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vQueueUnregisterQueueImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vQueueUnregisterQueue_Unpriv \n" + " MPU_vQueueUnregisterQueue_Priv: \n" + " b MPU_vQueueUnregisterQueueImpl \n" + " MPU_vQueueUnregisterQueue_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pcQueueGetNameImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_pcQueueGetName_Unpriv \n" + " MPU_pcQueueGetName_Priv: \n" + " b MPU_pcQueueGetNameImpl \n" + " MPU_pcQueueGetName_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pvTimerGetTimerIDImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_pvTimerGetTimerID_Unpriv \n" + " MPU_pvTimerGetTimerID_Priv: \n" + " b MPU_pvTimerGetTimerIDImpl \n" + " MPU_pvTimerGetTimerID_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTimerSetTimerIDImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vTimerSetTimerID_Unpriv \n" + " MPU_vTimerSetTimerID_Priv: \n" + " b MPU_vTimerSetTimerIDImpl \n" + " MPU_vTimerSetTimerID_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerIsTimerActiveImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTimerIsTimerActive_Unpriv \n" + " MPU_xTimerIsTimerActive_Priv: \n" + " b MPU_xTimerIsTimerActiveImpl \n" + " MPU_xTimerIsTimerActive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv \n" + " MPU_xTimerGetTimerDaemonTaskHandle_Priv: \n" + " b MPU_xTimerGetTimerDaemonTaskHandleImpl \n" + " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGenericCommandFromTaskImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTimerGenericCommandFromTask_Unpriv \n" + " MPU_xTimerGenericCommandFromTask_Priv: \n" + " b MPU_xTimerGenericCommandFromTaskImpl \n" + " MPU_xTimerGenericCommandFromTask_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pcTimerGetNameImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_pcTimerGetName_Unpriv \n" + " MPU_pcTimerGetName_Priv: \n" + " b MPU_pcTimerGetNameImpl \n" + " MPU_pcTimerGetName_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTimerSetReloadModeImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vTimerSetReloadMode_Unpriv \n" + " MPU_vTimerSetReloadMode_Priv: \n" + " b MPU_vTimerSetReloadModeImpl \n" + " MPU_vTimerSetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetReloadModeImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTimerGetReloadMode_Unpriv \n" + " MPU_xTimerGetReloadMode_Priv: \n" + " b MPU_xTimerGetReloadModeImpl \n" + " MPU_xTimerGetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTimerGetReloadModeImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_uxTimerGetReloadMode_Unpriv \n" + " MPU_uxTimerGetReloadMode_Priv: \n" + " b MPU_uxTimerGetReloadModeImpl \n" + " MPU_uxTimerGetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetPeriodImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTimerGetPeriod_Unpriv \n" + " MPU_xTimerGetPeriod_Priv: \n" + " b MPU_xTimerGetPeriodImpl \n" + " MPU_xTimerGetPeriod_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetExpiryTimeImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTimerGetExpiryTime_Unpriv \n" + " MPU_xTimerGetExpiryTime_Priv: \n" + " b MPU_xTimerGetExpiryTimeImpl \n" + " MPU_xTimerGetExpiryTime_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupWaitBitsImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xEventGroupWaitBits_Unpriv \n" + " MPU_xEventGroupWaitBits_Priv: \n" + " b MPU_xEventGroupWaitBitsImpl \n" + " MPU_xEventGroupWaitBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupClearBitsImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xEventGroupClearBits_Unpriv \n" + " MPU_xEventGroupClearBits_Priv: \n" + " b MPU_xEventGroupClearBitsImpl \n" + " MPU_xEventGroupClearBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupSetBitsImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xEventGroupSetBits_Unpriv \n" + " MPU_xEventGroupSetBits_Priv: \n" + " b MPU_xEventGroupSetBitsImpl \n" + " MPU_xEventGroupSetBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupSyncImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xEventGroupSync_Unpriv \n" + " MPU_xEventGroupSync_Priv: \n" + " b MPU_xEventGroupSyncImpl \n" + " MPU_xEventGroupSync_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxEventGroupGetNumberImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_uxEventGroupGetNumber_Unpriv \n" + " MPU_uxEventGroupGetNumber_Priv: \n" + " b MPU_uxEventGroupGetNumberImpl \n" + " MPU_uxEventGroupGetNumber_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory" + ); + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vEventGroupSetNumberImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vEventGroupSetNumber_Unpriv \n" + " MPU_vEventGroupSetNumber_Priv: \n" + " b MPU_vEventGroupSetNumberImpl \n" + " MPU_vEventGroupSetNumber_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory" + ); + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSendImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xStreamBufferSend_Unpriv \n" + " MPU_xStreamBufferSend_Priv: \n" + " b MPU_xStreamBufferSendImpl \n" + " MPU_xStreamBufferSend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferReceiveImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xStreamBufferReceive_Unpriv \n" + " MPU_xStreamBufferReceive_Priv: \n" + " b MPU_xStreamBufferReceiveImpl \n" + " MPU_xStreamBufferReceive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferIsFullImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xStreamBufferIsFull_Unpriv \n" + " MPU_xStreamBufferIsFull_Priv: \n" + " b MPU_xStreamBufferIsFullImpl \n" + " MPU_xStreamBufferIsFull_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferIsEmptyImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xStreamBufferIsEmpty_Unpriv \n" + " MPU_xStreamBufferIsEmpty_Priv: \n" + " b MPU_xStreamBufferIsEmptyImpl \n" + " MPU_xStreamBufferIsEmpty_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSpacesAvailableImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xStreamBufferSpacesAvailable_Unpriv \n" + " MPU_xStreamBufferSpacesAvailable_Priv: \n" + " b MPU_xStreamBufferSpacesAvailableImpl \n" + " MPU_xStreamBufferSpacesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferBytesAvailableImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xStreamBufferBytesAvailable_Unpriv \n" + " MPU_xStreamBufferBytesAvailable_Priv: \n" + " b MPU_xStreamBufferBytesAvailableImpl \n" + " MPU_xStreamBufferBytesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSetTriggerLevelImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xStreamBufferSetTriggerLevel_Unpriv \n" + " MPU_xStreamBufferSetTriggerLevel_Priv: \n" + " b MPU_xStreamBufferSetTriggerLevelImpl \n" + " MPU_xStreamBufferSetTriggerLevel_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferNextMessageLengthBytesImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv \n" + " MPU_xStreamBufferNextMessageLengthBytes_Priv: \n" + " b MPU_xStreamBufferNextMessageLengthBytesImpl \n" + " MPU_xStreamBufferNextMessageLengthBytes_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ diff --git a/portable/GCC/ARM_CM23/non_secure/port.c b/portable/GCC/ARM_CM23/non_secure/port.c new file mode 100644 index 000000000..76d2b2445 --- /dev/null +++ b/portable/GCC/ARM_CM23/non_secure/port.c @@ -0,0 +1,2280 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024-2025 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU includes. */ +#include "mpu_wrappers.h" +#include "mpu_syscall_numbers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration settings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to check the validity of an interrupt priority. + */ +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) ) +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used during system call enter and exit. + */ +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Offsets in the stack to the parameters when inside the SVC handler. + */ +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +#if ( portARMV8M_MINOR_VERSION >= 1 ) + + /* Enable Privileged eXecute Never MPU attribute for the selected memory + * region. */ + #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL ) +#endif /* portARMV8M_MINOR_VERSION >= 1 */ + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Extract first address of the MPU region as encoded in the + * RBAR (Region Base Address Register) value. */ +#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \ + ( ( rbar ) & portMPU_RBAR_ADDRESS_MASK ) + +/* Extract last address of the MPU region as encoded in the + * RLAR (Region Limit Address Register) value. */ +#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \ + ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK ) + +/* Does addr lies within [start, end] address range? */ +#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \ + ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) ) + +/* Is the access request satisfied by the available permissions? */ +#define portIS_AUTHORIZED( accessRequest, permissions ) \ + ( ( ( permissions ) & ( accessRequest ) ) == accessRequest ) + +/* Max value that fits in a uint32_t type. */ +#define portUINT32_MAX ( ~( ( uint32_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. + */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 + +/** + * @brief Constants required to check and configure PACBTI security feature implementation. + */ +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) ) + + #define portCONTROL_UPAC_EN ( 1UL << 7UL ) + #define portCONTROL_PAC_EN ( 1UL << 6UL ) + #define portCONTROL_UBTI_EN ( 1UL << 5UL ) + #define portCONTROL_BTI_EN ( 1UL << 4UL ) + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Extract MPU region's access permissions from the Region Base Address + * Register (RBAR) value. + * + * @param ulRBARValue RBAR value for the MPU region. + * + * @return uint32_t Access permissions. + */ + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + + /** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + /** + * @brief Configures PACBTI features. + * + * This function configures the Pointer Authentication, and Branch Target + * Identification security features as per the user configuration. It returns + * the value of the special purpose CONTROL register accordingly, and optionally + * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M + * architecture based) target supports PACBTI security feature. + * + * @param xWriteControlRegister Used to control whether the special purpose + * CONTROL register should be updated or not. + * + * @return CONTROL register value according to the configured PACBTI option. + */ + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the system call stack so that upon returning from + * SVC, the system call stack is used. + * + * @param pulTaskStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + * @param ucSystemCallNumber The system call number of the system call. + */ + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Raise SVC for exiting from a system call. + */ + void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief This variable is set to pdTRUE when the scheduler is started. + */ + PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + + /** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +/** + * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + /** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + + /** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + + /** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the cpsid instruction + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessPermissions = 0; + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_ONLY ) + { + ulAccessPermissions = tskMPU_READ_PERMISSION; + } + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_WRITE ) + { + ulAccessPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION ); + } + + return ulAccessPermissions; + } + +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } + +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ portOFFSET_TO_PC ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ]; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulSystemCallStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the system call section (i.e. application is + * not raising SVC directly). + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as + * it is non-NULL only during the execution of a system call (i.e. + * between system call enter and exit). + * 3. System call is not for a kernel API disabled by the configuration + * in FreeRTOSConfig.h. + * 4. We do not need to check that ucSystemCallNumber is within range + * because the assembly SVC handler checks that before calling + * this function. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) && + ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) ) + { + pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the system call stack for the stack frame. */ + pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulSystemCallStack[ i ] = pulTaskStack[ i ]; + } + + /* Store the value of the Link Register before the SVC was raised. + * It contains the address of the caller of the System Call entry + * point (i.e. the caller of the MPU_). We need to restore it + * when we exit from the system call. */ + pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; + + /* Store the value of the PSPLIM register before the SVC was raised. + * We need to restore it when we exit from the system call. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* Use the pulSystemCallStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif + + /* Start executing the system call upon returning from this handler. */ + pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; + + /* Raise a request to exit from the system call upon finishing the + * system call. */ + pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; + + /* Remember the location where we should copy the stack frame when we exit from + * the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize; + + /* Record if the hardware used padding to force the stack pointer + * to be double word aligned. */ + if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK ) + { + pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG; + } + else + { + pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG ); + } + + /* We ensure in pxPortInitialiseStack that the system call stack is + * double word aligned and therefore, there is no need of padding. + * Clear the bit[9] of stacked xPSR. */ + pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + + /* Raise the privilege for the duration of the system call. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " bics r0, r1 \n" /* Clear nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */ + { + __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulTaskStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the privileged code (i.e. application is not + * raising SVC directly). This SVC is only raised from + * vRequestSystemCallExit which is in the privileged code section. + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL - + * this means that we previously entered a system call and the + * application is not attempting to exit without entering a system + * call. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) ) + { + pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the task stack for the stack frame. */ + pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulTaskStack[ i ] = pulSystemCallStack[ i ]; + } + + /* Use the pulTaskStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) ); + + /* Return to the caller of the System Call entry point (i.e. the + * caller of the MPU_). */ + pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + /* Ensure that LR has a valid value.*/ + pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + + /* Restore the PSPLIM register to what it was at the time of + * system call entry. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* If the hardware used padding to force the stack pointer + * to be double word aligned, set the stacked xPSR bit[9], + * otherwise clear it. */ + if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG ) + { + pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK; + } + else + { + pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + } + + /* This is not NULL only for the duration of the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; + + /* Drop the privilege before returning to the thread mode. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " orrs r0, r1 \n" /* Set nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xTaskIsPrivileged = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xTaskIsPrivileged = pdTRUE; + } + + return xTaskIsPrivileged; + } + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged, + xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulIndex = 0; + uint32_t ulControl = 0x0; + + xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ + ulIndex++; + + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + ulIndex++; + + #if ( configENABLE_TRUSTZONE == 1 ) + { + xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */ + ulIndex++; + } + #endif /* configENABLE_TRUSTZONE */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + ulIndex++; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Check PACBTI security feature configuration before pushing the + * CONTROL register's value on task's TCB. */ + ulControl = prvConfigurePACBTI( pdFALSE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + if( xRunPrivileged == pdTRUE ) + { + xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + else + { + xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG ); + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ + ulIndex++; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + { + /* Ensure that the system call stack is double word aligned. */ + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) + + ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + /* This is not NULL only for the duration of a system call. */ + xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL; + } + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ]; + ulIndex++; + } + } + #endif /* configENABLE_PAC */ + + return &( xMPUSettings->ulContext[ ulIndex ] ); + } + +#else /* configENABLE_MPU */ + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ + { + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + pxTopOfStack--; + *pxTopOfStack = ulTaskPacKey[ i ]; + } + } + #endif /* configENABLE_PAC */ + + return pxTopOfStack; + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Set the CONTROL register value based on PACBTI security feature + * configuration before starting the first task. */ + ( void ) prvConfigurePACBTI( pdTRUE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + { + xSchedulerRunning = pdTRUE; + } + #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + configSTACK_DEPTH_TYPE uxStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( uxStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* PXN. */ + #if ( portARMV8M_MINOR_VERSION >= 1 ) + { + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ); + } + } + #endif /* portARMV8M_MINOR_VERSION >= 1 */ + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, + uint32_t ulBufferLength, + uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */ + + { + uint32_t i, ulBufferStartAddress, ulBufferEndAddress; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE ) + { + ulBufferStartAddress = ( uint32_t ) pvBuffer; + ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL ); + + for( i = 0; i < portTOTAL_NUM_REGIONS; i++ ) + { + /* Is the MPU region enabled? */ + if( ( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR & portMPU_RLAR_REGION_ENABLE ) == portMPU_RLAR_REGION_ENABLE ) + { + if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_AUTHORIZED( ulAccessRequested, + prvGetRegionAccessPermissions( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ) ) ) + { + xAccessGranted = pdTRUE; + break; + } + } + } + } + } + + return xAccessGranted; + } + +#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings; + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else + { + xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 ) + { + xAccessGranted = pdTRUE; + } + } + } + + return xAccessGranted; + } + + #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + ( void ) lInternalIndexOfKernelObject; + + /* If Access Control List feature is not used, all the tasks have + * access to all the kernel objects. */ + return pdTRUE; + } + + #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + { + uint32_t ulControl = 0x0; + + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); + + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; + + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM23/non_secure/portasm.c b/portable/GCC/ARM_CM23/non_secure/portasm.c new file mode 100644 index 000000000..978d35259 --- /dev/null +++ b/portable/GCC/ARM_CM23/non_secure/portasm.c @@ -0,0 +1,604 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION + * is defined correctly and privileged functions are placed in correct sections. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Portasm includes. */ +#include "portasm.h" + +/* System call numbers includes. */ +#include "mpu_syscall_numbers.h" + +/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the + * header files. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#if ( configENABLE_FPU == 1 ) + #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0. +#endif + +#if ( configENABLE_MPU == 1 ) + + void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " program_mpu_first_task: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r3] \n" /* r0 = pxCurrentTCB.*/ + " \n" + " dmb \n" /* Complete outstanding transfers before disabling MPU. */ + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " movs r3, #1 \n" /* r3 = 1. */ + " bics r2, r3 \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */ + " str r2, [r1] \n" /* Disable MPU. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */ + " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r1, [r2] \n" /* Program MAIR0. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */ + " \n" + " movs r3, #4 \n" /* r3 = 4. */ + " str r3, [r1] \n" /* Program RNR = 4. */ + " ldmia r0!, {r4-r5} \n" /* Read first set of RBAR/RLAR registers from TCB. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " stmia r2!, {r4-r5} \n" /* Write first set of RBAR/RLAR registers. */ + " movs r3, #5 \n" /* r3 = 5. */ + " str r3, [r1] \n" /* Program RNR = 5. */ + " ldmia r0!, {r4-r5} \n" /* Read second set of RBAR/RLAR registers from TCB. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " stmia r2!, {r4-r5} \n" /* Write second set of RBAR/RLAR registers. */ + " movs r3, #6 \n" /* r3 = 6. */ + " str r3, [r1] \n" /* Program RNR = 6. */ + " ldmia r0!, {r4-r5} \n" /* Read third set of RBAR/RLAR registers from TCB. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " stmia r2!, {r4-r5} \n" /* Write third set of RBAR/RLAR registers. */ + " movs r3, #7 \n" /* r3 = 6. */ + " str r3, [r1] \n" /* Program RNR = 7. */ + " ldmia r0!, {r4-r5} \n" /* Read fourth set of RBAR/RLAR registers from TCB. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " stmia r2!, {r4-r5} \n" /* Write fourth set of RBAR/RLAR registers. */ + " \n" + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " movs r3, #1 \n" /* r3 = 1. */ + " orrs r2, r3 \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */ + " str r2, [r1] \n" /* Enable MPU. */ + " dsb \n" /* Force memory writes before continuing. */ + " \n" + " restore_context_first_task: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* r1 = pxCurrentTCB.*/ + " ldr r2, [r1] \n" /* r2 = Location of saved context in TCB. */ + " \n" + " restore_special_regs_first_task: \n" + " subs r2, #20 \n" + " ldmia r2!, {r0, r3-r6} \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */ + " subs r2, #20 \n" + " msr psp, r3 \n" + " msr control, r5 \n" + " mov lr, r6 \n" + " ldr r4, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " str r0, [r4] \n" /* Restore xSecureContext. */ + " \n" + " restore_general_regs_first_task: \n" + " subs r2, #32 \n" + " ldmia r2!, {r4-r7} \n" /* r4-r7 contain half of the hardware saved context. */ + " stmia r3!, {r4-r7} \n" /* Copy half of the the hardware saved context on the task stack. */ + " ldmia r2!, {r4-r7} \n" /* r4-r7 contain rest half of the hardware saved context. */ + " stmia r3!, {r4-r7} \n" /* Copy rest half of the the hardware saved context on the task stack. */ + " subs r2, #48 \n" + " ldmia r2!, {r4-r7} \n" /* Restore r8-r11. */ + " mov r8, r4 \n" /* r8 = r4. */ + " mov r9, r5 \n" /* r9 = r5. */ + " mov r10, r6 \n" /* r10 = r6. */ + " mov r11, r7 \n" /* r11 = r7. */ + " subs r2, #32 \n" + " ldmia r2!, {r4-r7} \n" /* Restore r4-r7. */ + " subs r2, #16 \n" + " \n" + " restore_context_done_first_task: \n" + " str r2, [r1] \n" /* Save the location where the context should be saved next as the first member of TCB. */ + " bx lr \n" + ); + } + +#else /* configENABLE_MPU */ + + void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r3, [r2] \n" /* Read pxCurrentTCB. */ + " ldr r0, [r3] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + " \n" + " ldm r0!, {r1-r3} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */ + " ldr r4, =xSecureContext \n" + " str r1, [r4] \n" /* Set xSecureContext to this task's value for the same. */ + " movs r1, #2 \n" /* r1 = 2. */ + " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */ + " adds r0, #32 \n" /* Discard everything up to r0. */ + " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */ + " isb \n" + " bx r3 \n" /* Finally, branch to EXC_RETURN. */ + ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* r0 = CONTROL. */ + " movs r1, #1 \n" /* r1 = 1. */ + " tst r0, r1 \n" /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */ + " beq running_privileged \n" /* If the result of previous AND operation was 0, branch. */ + " movs r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + " bx lr \n" /* Return. */ + " running_privileged: \n" + " movs r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + " bx lr \n" /* Return. */ + ::: "r0", "r1", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* Read the CONTROL register. */ + " movs r1, #1 \n" /* r1 = 1. */ + " bics r0, r1 \n" /* Clear the bit 0. */ + " msr control, r0 \n" /* Write back the new CONTROL value. */ + " bx lr \n" /* Return to the caller. */ + ::: "r0", "r1", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vResetPrivilege( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* r0 = CONTROL. */ + " movs r1, #1 \n" /* r1 = 1. */ + " orrs r0, r1 \n" /* r0 = r0 | r1. */ + " msr control, r0 \n" /* CONTROL = r0. */ + " bx lr \n" /* Return to the caller. */ + ::: "r0", "r1", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r0, =0xe000ed08 \n" /* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */ + " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */ + " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */ + " cpsie i \n" /* Globally enable interrupts. */ + " dsb \n" + " isb \n" + " svc %0 \n" /* System call to start the first task. */ + " nop \n" + ::"i" ( portSVC_START_SCHEDULER ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, PRIMASK \n" + " cpsid i \n" + " bx lr \n" + ::: "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " msr PRIMASK, r0 \n" + " bx lr \n" + ::: "memory" + ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern SecureContext_SaveContext \n" + " .extern SecureContext_LoadContext \n" + " \n" + " ldr r3, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " ldr r0, [r3] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later.*/ + " ldr r2, [r1] \n" /* r2 = Location in TCB where the context should be saved. */ + " \n" + " cbz r0, save_ns_context \n" /* No secure context to save. */ + " save_s_context: \n" + " push {r0-r2, lr} \n" + " bl SecureContext_SaveContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r0-r3} \n" /* LR is now in r3. */ + " mov lr, r3 \n" /* Restore LR. */ + " \n" + " save_ns_context: \n" + " mov r3, lr \n" /* r3 = LR (EXC_RETURN). */ + " lsls r3, r3, #25 \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bmi save_special_regs \n" /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + " \n" + " save_general_regs: \n" + " mrs r3, psp \n" + " stmia r2!, {r4-r7} \n" /* Store r4-r7. */ + " mov r4, r8 \n" /* r4 = r8. */ + " mov r5, r9 \n" /* r5 = r9. */ + " mov r6, r10 \n" /* r6 = r10. */ + " mov r7, r11 \n" /* r7 = r11. */ + " stmia r2!, {r4-r7} \n" /* Store r8-r11. */ + " ldmia r3!, {r4-r7} \n" /* Copy half of the hardware saved context into r4-r7. */ + " stmia r2!, {r4-r7} \n" /* Store the hardware saved context. */ + " ldmia r3!, {r4-r7} \n" /* Copy rest half of the hardware saved context into r4-r7. */ + " stmia r2!, {r4-r7} \n" /* Store the hardware saved context. */ + " \n" + " save_special_regs: \n" + " mrs r3, psp \n" /* r3 = PSP. */ + " movs r4, #0 \n" /* r4 = 0. 0 is stored in the PSPLIM slot. */ + " mrs r5, control \n" /* r5 = CONTROL. */ + " mov r6, lr \n" /* r6 = LR. */ + " stmia r2!, {r0, r3-r6} \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ + " str r2, [r1] \n" /* Save the location from where the context should be restored as the first member of TCB. */ + " \n" + " select_next_task: \n" + " cpsid i \n" + " bl vTaskSwitchContext \n" + " cpsie i \n" + " \n" + " program_mpu: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r3] \n" /* r0 = pxCurrentTCB.*/ + " \n" + " dmb \n" /* Complete outstanding transfers before disabling MPU. */ + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " movs r3, #1 \n" /* r3 = 1. */ + " bics r2, r3 \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */ + " str r2, [r1] \n" /* Disable MPU. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */ + " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r1, [r2] \n" /* Program MAIR0. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */ + " \n" + " movs r3, #4 \n" /* r3 = 4. */ + " str r3, [r1] \n" /* Program RNR = 4. */ + " ldmia r0!, {r4-r5} \n" /* Read first set of RBAR/RLAR registers from TCB. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " stmia r2!, {r4-r5} \n" /* Write first set of RBAR/RLAR registers. */ + " movs r3, #5 \n" /* r3 = 5. */ + " str r3, [r1] \n" /* Program RNR = 5. */ + " ldmia r0!, {r4-r5} \n" /* Read second set of RBAR/RLAR registers from TCB. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " stmia r2!, {r4-r5} \n" /* Write second set of RBAR/RLAR registers. */ + " movs r3, #6 \n" /* r3 = 6. */ + " str r3, [r1] \n" /* Program RNR = 6. */ + " ldmia r0!, {r4-r5} \n" /* Read third set of RBAR/RLAR registers from TCB. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " stmia r2!, {r4-r5} \n" /* Write third set of RBAR/RLAR registers. */ + " movs r3, #7 \n" /* r3 = 6. */ + " str r3, [r1] \n" /* Program RNR = 7. */ + " ldmia r0!, {r4-r5} \n" /* Read fourth set of RBAR/RLAR registers from TCB. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " stmia r2!, {r4-r5} \n" /* Write fourth set of RBAR/RLAR registers. */ + " \n" + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " movs r3, #1 \n" /* r3 = 1. */ + " orrs r2, r3 \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */ + " str r2, [r1] \n" /* Enable MPU. */ + " dsb \n" /* Force memory writes before continuing. */ + " \n" + " restore_context: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* r1 = pxCurrentTCB.*/ + " ldr r2, [r1] \n" /* r2 = Location of saved context in TCB. */ + " \n" + " restore_special_regs: \n" + " subs r2, #20 \n" + " ldmia r2!, {r0, r3-r6} \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */ + " subs r2, #20 \n" + " msr psp, r3 \n" + " msr control, r5 \n" + " mov lr, r6 \n" + " ldr r4, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " str r0, [r4] \n" /* Restore xSecureContext. */ + " cbz r0, restore_ns_context \n" /* No secure context to restore. */ + " \n" + " restore_s_context: \n" + " push {r1-r3, lr} \n" + " bl SecureContext_LoadContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r1-r4} \n" /* LR is now in r4. */ + " mov lr, r4 \n" + " \n" + " restore_ns_context: \n" + " mov r0, lr \n" /* r0 = LR (EXC_RETURN). */ + " lsls r0, r0, #25 \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bmi restore_context_done \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + " \n" + " restore_general_regs: \n" + " subs r2, #32 \n" + " ldmia r2!, {r4-r7} \n" /* r4-r7 contain half of the hardware saved context. */ + " stmia r3!, {r4-r7} \n" /* Copy half of the the hardware saved context on the task stack. */ + " ldmia r2!, {r4-r7} \n" /* r4-r7 contain rest half of the hardware saved context. */ + " stmia r3!, {r4-r7} \n" /* Copy rest half of the the hardware saved context on the task stack. */ + " subs r2, #48 \n" + " ldmia r2!, {r4-r7} \n" /* Restore r8-r11. */ + " mov r8, r4 \n" /* r8 = r4. */ + " mov r9, r5 \n" /* r9 = r5. */ + " mov r10, r6 \n" /* r10 = r6. */ + " mov r11, r7 \n" /* r11 = r7. */ + " subs r2, #32 \n" + " ldmia r2!, {r4-r7} \n" /* Restore r4-r7. */ + " subs r2, #16 \n" + " \n" + " restore_context_done: \n" + " str r2, [r1] \n" /* Save the location where the context should be saved next as the first member of TCB. */ + " bx lr \n" + ); + } + +#else /* configENABLE_MPU */ + + void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern SecureContext_SaveContext \n" + " .extern SecureContext_LoadContext \n" + " \n" + " ldr r3, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " ldr r0, [r3] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later.*/ + " mrs r2, psp \n" /* Read PSP in r2. */ + " \n" + " cbz r0, save_ns_context \n" /* No secure context to save. */ + " push {r0-r2, r14} \n" + " bl SecureContext_SaveContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r0-r3} \n" /* LR is now in r3. */ + " mov lr, r3 \n" /* LR = r3. */ + " lsls r1, r3, #25 \n" /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bpl save_ns_context \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* Read pxCurrentTCB. */ + " subs r2, r2, #12 \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */ + " str r2, [r1] \n" /* Save the new top of stack in TCB. */ + " movs r1, #0 \n" /* r1 = 0. 0 is stored in the PSPLIM slot. */ + " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */ + " stmia r2!, {r0, r1, r3} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */ + " b select_next_task \n" + " \n" + " save_ns_context: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* Read pxCurrentTCB. */ + " subs r2, r2, #44 \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */ + " str r2, [r1] \n" /* Save the new top of stack in TCB. */ + " movs r1, #0 \n" /* r1 = 0. 0 is stored in the PSPLIM slot. */ + " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */ + " stmia r2!, {r0, r1, r3-r7} \n" /* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */ + " mov r4, r8 \n" /* r4 = r8. */ + " mov r5, r9 \n" /* r5 = r9. */ + " mov r6, r10 \n" /* r6 = r10. */ + " mov r7, r11 \n" /* r7 = r11. */ + " stmia r2!, {r4-r7} \n" /* Store the high registers that are not saved automatically. */ + " \n" + " select_next_task: \n" + " cpsid i \n" + " bl vTaskSwitchContext \n" + " cpsie i \n" + " \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* Read pxCurrentTCB. */ + " ldr r2, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */ + " \n" + " ldmia r2!, {r0, r1, r4} \n" /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */ + " mov lr, r4 \n" /* LR = r4. */ + " ldr r3, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " str r0, [r3] \n" /* Restore the task's xSecureContext. */ + " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */ + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* Read pxCurrentTCB. */ + " push {r2, r4} \n" + " bl SecureContext_LoadContext \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r2, r4} \n" + " mov lr, r4 \n" /* LR = r4. */ + " lsls r1, r4, #25 \n" /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bpl restore_ns_context \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + " msr psp, r2 \n" /* Remember the new top of stack for the task. */ + " bx lr \n" + " \n" + " restore_ns_context: \n" + " adds r2, r2, #16 \n" /* Move to the high registers. */ + " ldmia r2!, {r4-r7} \n" /* Restore the high registers that are not automatically restored. */ + " mov r8, r4 \n" /* r8 = r4. */ + " mov r9, r5 \n" /* r9 = r5. */ + " mov r10, r6 \n" /* r10 = r6. */ + " mov r11, r7 \n" /* r11 = r7. */ + " msr psp, r2 \n" /* Remember the new top of stack for the task. */ + " subs r2, r2, #32 \n" /* Go back to the low registers. */ + " ldmia r2!, {r4-r7} \n" /* Restore the low registers that are not automatically restored. */ + " bx lr \n" + ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + ".syntax unified \n" + ".extern vPortSVCHandler_C \n" + ".extern vSystemCallEnter \n" + ".extern vSystemCallExit \n" + " \n" + "movs r0, #4 \n" + "mov r1, lr \n" + "tst r0, r1 \n" + "beq stack_on_msp \n" + "stack_on_psp: \n" + " mrs r0, psp \n" + " b route_svc \n" + "stack_on_msp: \n" + " mrs r0, msp \n" + " b route_svc \n" + " \n" + "route_svc: \n" + " ldr r3, [r0, #24] \n" + " subs r3, #2 \n" + " ldrb r2, [r3, #0] \n" + " cmp r2, %0 \n" + " blt system_call_enter \n" + " cmp r2, %1 \n" + " beq system_call_exit \n" + " b vPortSVCHandler_C \n" + " \n" + "system_call_enter: \n" + " b vSystemCallEnter \n" + "system_call_exit: \n" + " b vSystemCallExit \n" + " \n" + : /* No outputs. */ + : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT ) + : "r0", "r1", "r2", "r3", "memory" + ); + } + +#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " movs r0, #4 \n" + " mov r1, lr \n" + " tst r0, r1 \n" + " beq stacking_used_msp \n" + " mrs r0, psp \n" + " ldr r2, =vPortSVCHandler_C \n" + " bx r2 \n" + " stacking_used_msp: \n" + " mrs r0, msp \n" + " ldr r2, =vPortSVCHandler_C \n" + " bx r2 \n" + ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " svc %0 \n" /* Secure context is allocated in the supervisor call. */ + " bx lr \n" /* Return. */ + ::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, [r0] \n" /* The first item in the TCB is the top of the stack. */ + " ldr r1, [r2] \n" /* The first item on the stack is the task's xSecureContext. */ + " cmp r1, #0 \n" /* Raise svc if task's xSecureContext is not NULL. */ + " bne free_secure_context \n" /* Branch if r1 != 0. */ + " bx lr \n" /* There is no secure context (xSecureContext is NULL). */ + " free_secure_context: \n" + " svc %0 \n" /* Secure context is freed in the supervisor call. */ + " bx lr \n" /* Return. */ + ::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory" + ); +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM23/non_secure/portasm.h b/portable/GCC/ARM_CM23/non_secure/portasm.h new file mode 100644 index 000000000..b7021b024 --- /dev/null +++ b/portable/GCC/ARM_CM23/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kernel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/portable/GCC/ARM_CM23/non_secure/portmacro.h b/portable/GCC/ARM_CM23/non_secure/portmacro.h new file mode 100644 index 000000000..e81b89228 --- /dev/null +++ b/portable/GCC/ARM_CM23/non_secure/portmacro.h @@ -0,0 +1,85 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M23" +#define portHAS_ARMV8M_MAIN_EXTENSION 0 +#define portARMV8M_MINOR_VERSION 0 +#define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +#if ( configTOTAL_MPU_REGIONS == 16 ) + #error 16 MPU regions are not yet supported for this port. +#endif + +#ifndef configENABLE_MVE + #define configENABLE_MVE 0 +#elif ( configENABLE_MVE != 0 ) + #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M23. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" ) +#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h new file mode 100644 index 000000000..f373bcad5 --- /dev/null +++ b/portable/GCC/ARM_CM23/non_secure/portmacrocommon.h @@ -0,0 +1,582 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACROCOMMON_H +#define PORTMACROCOMMON_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. +#endif /* configENABLE_FPU */ + +#ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. +#endif /* configENABLE_MPU */ + +#ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. +#endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() +#define portINLINE __inline +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif +#define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ +extern BaseType_t xPortIsInsideInterrupt( void ); + +extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + +extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; +extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + +extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; +extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + +#if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_PAC == 1 ) + + /** + * @brief Generates 128-bit task's random PAC key. + * + * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be + * filled with a 128-bit random number. + */ + void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); + +#endif /* configENABLE_PAC */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ +#if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) +#else + #define portPRIVILEGE_BIT ( 0x0UL ) +#endif /* configENABLE_MPU */ + +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ +#define portPRIVILEGED_FLASH_REGION ( 0UL ) +#define portUNPRIVILEGED_FLASH_REGION ( 1UL ) +#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) +#define portPRIVILEGED_RAM_REGION ( 3UL ) +#define portSTACK_REGION ( 4UL ) +#define portFIRST_CONFIGURABLE_REGION ( 5UL ) +#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) +#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) +#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ +#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ +#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ +#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ +#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ +#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ +#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ +#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) +#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) +#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + +#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) +#define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) +#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) +#define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + +#define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + #ifndef configSYSTEM_CALL_STACK_SIZE + #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. + #endif + + /** + * @brief System call stack. + */ + typedef struct SYSTEM_CALL_STACK_INFO + { + uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; + uint32_t * pulSystemCallStack; + uint32_t * pulSystemCallStackLimit; + uint32_t * pulTaskStack; + uint32_t ulLinkRegisterAtSystemCallEntry; + uint32_t ulStackLimitRegisterAtSystemCallEntry; + } xSYSTEM_CALL_STACK_INFO; + + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + /** + * @brief MPU settings as stored in the TCB. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><-----------><----> + * 16 17 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 71 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 17 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 55 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | | | PC, xPSR | EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><-----------><----> + * 16 17 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 70 + + #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + /* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 17 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 54 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+------------------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +----------+-----------------+------------------------------+------------+-----+ + * + * <---------><----------------><------------------------------><-----------><----> + * 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 38 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+----------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | PC, xPSR | EXC_RETURN | | | + * +----------+-----------------+----------------------+------------+-----+ + * + * <---------><----------------><----------------------><-----------><----> + * 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 37 + + #else /* #if( configENABLE_TRUSTZONE == 1 ) */ + + /* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) + + /* Size of an Access Control List (ACL) entry in bits. */ + #define portACL_ENTRY_SIZE_BITS ( 32U ) + + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + uint32_t ulContext[ MAX_CONTEXT_SIZE ]; + uint32_t ulTaskFlags; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo; + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ]; + #endif + #endif + } xMPU_SETTINGS; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Validate priority of ISRs that are allowed to call FreeRTOS + * system calls. + */ +#if ( configASSERT_DEFINED == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif +#endif + +/** + * @brief SVC numbers. + */ +#define portSVC_ALLOCATE_SECURE_CONTEXT 100 +#define portSVC_FREE_SECURE_CONTEXT 101 +#define portSVC_START_SCHEDULER 102 +#define portSVC_RAISE_PRIVILEGE 103 +#define portSVC_SYSTEM_CALL_EXIT 104 +#define portSVC_YIELD 105 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) +#endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() +#else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + extern BaseType_t xPortIsTaskPrivileged( void ); + +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACROCOMMON_H */ diff --git a/portable/GCC/ARM_CM23/secure/secure_context.c b/portable/GCC/ARM_CM23/secure/secure_context.c new file mode 100644 index 000000000..3aa335e63 --- /dev/null +++ b/portable/GCC/ARM_CM23/secure/secure_context.c @@ -0,0 +1,354 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Secure context includes. */ +#include "secure_context.h" + +/* Secure heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief CONTROL value for privileged tasks. + * + * Bit[0] - 0 --> Thread mode is privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_PRIVILEGED 0x02 + +/** + * @brief CONTROL value for un-privileged tasks. + * + * Bit[0] - 1 --> Thread mode is un-privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03 + +/** + * @brief Size of stack seal values in bytes. + */ +#define securecontextSTACK_SEAL_SIZE 8 + +/** + * @brief Stack seal value as recommended by ARM. + */ +#define securecontextSTACK_SEAL_VALUE 0xFEF5EDA5 + +/** + * @brief Maximum number of secure contexts. + */ +#ifndef secureconfigMAX_SECURE_CONTEXTS + #define secureconfigMAX_SECURE_CONTEXTS 8UL +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Pre-allocated array of secure contexts. + */ +SecureContext_t xSecureContexts[ secureconfigMAX_SECURE_CONTEXTS ]; +/*-----------------------------------------------------------*/ + +/** + * @brief Get a free secure context for a task from the secure context pool (xSecureContexts). + * + * This function ensures that only one secure context is allocated for a task. + * + * @param[in] pvTaskHandle The task handle for which the secure context is allocated. + * + * @return Index of a free secure context in the xSecureContexts array. + */ +static uint32_t ulGetSecureContext( void * pvTaskHandle ); + +/** + * @brief Return the secure context to the secure context pool (xSecureContexts). + * + * @param[in] ulSecureContextIndex Index of the context in the xSecureContexts array. + */ +static void vReturnSecureContext( uint32_t ulSecureContextIndex ); + +/* These are implemented in assembly. */ +extern void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ); +extern void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ); +/*-----------------------------------------------------------*/ + +static uint32_t ulGetSecureContext( void * pvTaskHandle ) +{ + /* Start with invalid index. */ + uint32_t i, ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + if( ( xSecureContexts[ i ].pucCurrentStackPointer == NULL ) && + ( xSecureContexts[ i ].pucStackLimit == NULL ) && + ( xSecureContexts[ i ].pucStackStart == NULL ) && + ( xSecureContexts[ i ].pvTaskHandle == NULL ) && + ( ulSecureContextIndex == secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = i; + } + else if( xSecureContexts[ i ].pvTaskHandle == pvTaskHandle ) + { + /* A task can only have one secure context. Do not allocate a second + * context for the same task. */ + ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + break; + } + } + + return ulSecureContextIndex; +} +/*-----------------------------------------------------------*/ + +static void vReturnSecureContext( uint32_t ulSecureContextIndex ) +{ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackStart = NULL; + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = NULL; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) +{ + uint32_t ulIPSR, i; + static uint32_t ulSecureContextsInitialized = 0; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ( ulIPSR != 0 ) && ( ulSecureContextsInitialized == 0 ) ) + { + /* Ensure to initialize secure contexts only once. */ + ulSecureContextsInitialized = 1; + + /* No stack for thread mode until a task's context is loaded. */ + secureportSET_PSPLIM( securecontextNO_STACK ); + secureportSET_PSP( securecontextNO_STACK ); + + /* Initialize all secure contexts. */ + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + xSecureContexts[ i ].pucCurrentStackPointer = NULL; + xSecureContexts[ i ].pucStackLimit = NULL; + xSecureContexts[ i ].pucStackStart = NULL; + xSecureContexts[ i ].pvTaskHandle = NULL; + } + + #if ( configENABLE_MPU == 1 ) + { + /* Configure thread mode to use PSP and to be unprivileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); + } + #else /* configENABLE_MPU */ + { + /* Configure thread mode to use PSP and to be privileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); + } + #endif /* configENABLE_MPU */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ) +#else /* configENABLE_MPU */ + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ) +#endif /* configENABLE_MPU */ +{ + uint8_t * pucStackMemory = NULL; + uint8_t * pucStackLimit; + uint32_t ulIPSR, ulSecureContextIndex; + SecureContextHandle_t xSecureContextHandle = securecontextINVALID_CONTEXT_ID; + + #if ( configENABLE_MPU == 1 ) + uint32_t * pulCurrentStackPointer = NULL; + #endif /* configENABLE_MPU */ + + /* Read the Interrupt Program Status Register (IPSR) and Process Stack Limit + * Register (PSPLIM) value. */ + secureportREAD_IPSR( ulIPSR ); + secureportREAD_PSPLIM( pucStackLimit ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. + * Also do nothing, if a secure context us already loaded. PSPLIM is set to + * securecontextNO_STACK when no secure context is loaded. */ + if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) ) + { + /* Obtain a free secure context. */ + ulSecureContextIndex = ulGetSecureContext( pvTaskHandle ); + + /* Were we able to get a free context? */ + if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS ) + { + /* Allocate the stack space. */ + pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + + if( pucStackMemory != NULL ) + { + /* Since stack grows down, the starting point will be the last + * location. Note that this location is next to the last + * allocated byte for stack (excluding the space for seal values) + * because the hardware decrements the stack pointer before + * writing i.e. if stack pointer is 0x2, a push operation will + * decrement the stack pointer to 0x1 and then write at 0x1. */ + xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize; + + /* Seal the created secure process stack. */ + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; + + /* The stack cannot go beyond this location. This value is + * programmed in the PSPLIM register on context switch.*/ + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = pucStackMemory; + + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle; + + #if ( configENABLE_MPU == 1 ) + { + /* Store the correct CONTROL value for the task on the stack. + * This value is programmed in the CONTROL register on + * context switch. */ + pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; + pulCurrentStackPointer--; + + if( ulIsTaskPrivileged ) + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; + } + else + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; + } + + /* Store the current stack pointer. This value is programmed in + * the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + } + #else /* configENABLE_MPU */ + { + /* Current SP is set to the starting of the stack. This + * value programmed in the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + } + #endif /* configENABLE_MPU */ + + /* Ensure to never return 0 as a valid context handle. */ + xSecureContextHandle = ulSecureContextIndex + 1UL; + } + } + } + + return xSecureContextHandle; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) +{ + uint32_t ulIPSR, ulSecureContextIndex; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* Only free if a valid context handle is passed. */ + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + /* Ensure that the secure context being deleted is associated with + * the task. */ + if( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) + { + /* Free the stack space. */ + vPortFree( xSecureContexts[ ulSecureContextIndex ].pucStackLimit ); + + /* Return the secure context back to the free secure contexts pool. */ + vReturnSecureContext( ulSecureContextIndex ); + } + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that no secure context is loaded and the task is loading it's + * own context. */ + if( ( pucStackLimit == securecontextNO_STACK ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_LoadContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that task's context is loaded and the task is saving it's own + * context. */ + if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_SaveContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM23/secure/secure_context.h b/portable/GCC/ARM_CM23/secure/secure_context.h new file mode 100644 index 000000000..e36a8e430 --- /dev/null +++ b/portable/GCC/ARM_CM23/secure/secure_context.h @@ -0,0 +1,138 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_CONTEXT_H__ +#define __SECURE_CONTEXT_H__ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" + +/** + * @brief PSP value when no secure context is loaded. + */ +#define securecontextNO_STACK 0x0 + +/** + * @brief Invalid context ID. + */ +#define securecontextINVALID_CONTEXT_ID 0UL +/*-----------------------------------------------------------*/ + +/** + * @brief Structure to represent a secure context. + * + * @note Since stack grows down, pucStackStart is the highest address while + * pucStackLimit is the first address of the allocated memory. + */ +typedef struct SecureContext +{ + uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */ + uint8_t * pucStackLimit; /**< Last location of the stack memory (PSPLIM). */ + uint8_t * pucStackStart; /**< First location of the stack memory. */ + void * pvTaskHandle; /**< Task handle of the task this context is associated with. */ +} SecureContext_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Opaque handle for a secure context. + */ +typedef uint32_t SecureContextHandle_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Initializes the secure context management system. + * + * PSP is set to NULL and therefore a task must allocate and load a context + * before calling any secure side function in the thread mode. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureContext_Init( void ); + +/** + * @brief Allocates a context on the secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] ulSecureStackSize Size of the stack to allocate on secure side. + * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise. + * + * @return Opaque context handle if context is successfully allocated, NULL + * otherwise. + */ +#if ( configENABLE_MPU == 1 ) + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ); +#else /* configENABLE_MPU */ + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ); +#endif /* configENABLE_MPU */ + +/** + * @brief Frees the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the + * context to be freed. + */ +void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); + +/** + * @brief Loads the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be loaded. + */ +void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); + +/** + * @brief Saves the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be saved. + */ +void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); + +#endif /* __SECURE_CONTEXT_H__ */ diff --git a/portable/GCC/ARM_CM23/secure/secure_context_port.c b/portable/GCC/ARM_CM23/secure/secure_context_port.c new file mode 100644 index 000000000..32559ad04 --- /dev/null +++ b/portable/GCC/ARM_CM23/secure/secure_context_port.c @@ -0,0 +1,99 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Secure context includes. */ +#include "secure_context.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +#if ( configENABLE_FPU == 1 ) + #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0. +#endif + +void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) ); +void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) ); + +void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) +{ + /* pxSecureContext value is in r0. */ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r1, ipsr \n" /* r1 = IPSR. */ + " cbz r1, load_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */ + " ldmia r0!, {r1, r2} \n" /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */ + " \n" + #if ( configENABLE_MPU == 1 ) + " ldmia r1!, {r3} \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */ + " msr control, r3 \n" /* CONTROL = r3. */ + #endif /* configENABLE_MPU */ + " \n" + " msr psplim, r2 \n" /* PSPLIM = r2. */ + " msr psp, r1 \n" /* PSP = r1. */ + " \n" + " load_ctx_therad_mode: \n" + " bx lr \n" + " \n" + ::: "r0", "r1", "r2" + ); +} +/*-----------------------------------------------------------*/ + +void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) +{ + /* pxSecureContext value is in r0. */ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r1, ipsr \n" /* r1 = IPSR. */ + " cbz r1, save_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */ + " mrs r1, psp \n" /* r1 = PSP. */ + " \n" + #if ( configENABLE_MPU == 1 ) + " mrs r2, control \n" /* r2 = CONTROL. */ + " subs r1, r1, #4 \n" /* Make space for the CONTROL value on the stack. */ + " str r1, [r0] \n" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */ + " stmia r1!, {r2} \n" /* Store CONTROL value on the stack. */ + #else /* configENABLE_MPU */ + " str r1, [r0] \n" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */ + #endif /* configENABLE_MPU */ + " \n" + " movs r1, %0 \n" /* r1 = securecontextNO_STACK. */ + " msr psplim, r1 \n" /* PSPLIM = securecontextNO_STACK. */ + " msr psp, r1 \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */ + " \n" + " save_ctx_therad_mode: \n" + " bx lr \n" + " \n" + ::"i" ( securecontextNO_STACK ) : "r1", "memory" + ); +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM23/secure/secure_heap.c b/portable/GCC/ARM_CM23/secure/secure_heap.c new file mode 100644 index 000000000..896b53e2d --- /dev/null +++ b/portable/GCC/ARM_CM23/secure/secure_heap.c @@ -0,0 +1,485 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Configuration includes. */ +#include "FreeRTOSConfig.h" + +/* Secure context heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Total heap size. + */ +#ifndef secureconfigTOTAL_HEAP_SIZE + #define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) ) +#endif + +/* No test marker by default. */ +#ifndef mtCOVERAGE_TEST_MARKER + #define mtCOVERAGE_TEST_MARKER() +#endif + +/* No tracing by default. */ +#ifndef traceMALLOC + #define traceMALLOC( pvReturn, xWantedSize ) +#endif + +/* No tracing by default. */ +#ifndef traceFREE + #define traceFREE( pv, xBlockSize ) +#endif + +/* Block sizes must not get too small. */ +#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) ) + +/* Assumes 8bit bytes! */ +#define secureheapBITS_PER_BYTE ( ( size_t ) 8 ) + +/* Max value that fits in a size_t type. */ +#define secureheapSIZE_MAX ( ~( ( size_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define secureheapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) ) + +/* MSB of the xBlockSize member of an BlockLink_t structure is used to track + * the allocation status of a block. When MSB of the xBlockSize member of + * an BlockLink_t structure is set then the block belongs to the application. + * When the bit is free the block is still part of the free heap space. */ +#define secureheapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) ) +#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 ) +#define secureheapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 ) +#define secureheapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK ) +#define secureheapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK ) +/*-----------------------------------------------------------*/ + +/* Allocate the memory for the heap. */ +#if ( configAPPLICATION_ALLOCATED_HEAP == 1 ) + +/* The application writer has already defined the array used for the RTOS +* heap - probably so it can be placed in a special segment or address. */ + extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#else /* configAPPLICATION_ALLOCATED_HEAP */ + static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#endif /* configAPPLICATION_ALLOCATED_HEAP */ + +/** + * @brief The linked list structure. + * + * This is used to link free blocks in order of their memory address. + */ +typedef struct A_BLOCK_LINK +{ + struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */ + size_t xBlockSize; /**< The size of the free block. */ +} BlockLink_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Called automatically to setup the required heap structures the first + * time pvPortMalloc() is called. + */ +static void prvHeapInit( void ); + +/** + * @brief Inserts a block of memory that is being freed into the correct + * position in the list of free memory blocks. + * + * The block being freed will be merged with the block in front it and/or the + * block behind it if the memory blocks are adjacent to each other. + * + * @param[in] pxBlockToInsert The block being freed. + */ +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ); +/*-----------------------------------------------------------*/ + +/** + * @brief The size of the structure placed at the beginning of each allocated + * memory block must by correctly byte aligned. + */ +static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + +/** + * @brief Create a couple of list links to mark the start and end of the list. + */ +static BlockLink_t xStart; +static BlockLink_t * pxEnd = NULL; + +/** + * @brief Keeps track of the number of free bytes remaining, but says nothing + * about fragmentation. + */ +static size_t xFreeBytesRemaining = 0U; +static size_t xMinimumEverFreeBytesRemaining = 0U; + +/*-----------------------------------------------------------*/ + +static void prvHeapInit( void ) +{ + BlockLink_t * pxFirstFreeBlock; + uint8_t * pucAlignedHeap; + size_t uxAddress; + size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE; + + /* Ensure the heap starts on a correctly aligned boundary. */ + uxAddress = ( size_t ) ucHeap; + + if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 ) + { + uxAddress += ( secureportBYTE_ALIGNMENT - 1 ); + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; + } + + pucAlignedHeap = ( uint8_t * ) uxAddress; + + /* xStart is used to hold a pointer to the first item in the list of free + * blocks. The void cast is used to prevent compiler warnings. */ + xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; + xStart.xBlockSize = ( size_t ) 0; + + /* pxEnd is used to mark the end of the list of free blocks and is inserted + * at the end of the heap space. */ + uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; + uxAddress -= xHeapStructSize; + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + pxEnd = ( void * ) uxAddress; + pxEnd->xBlockSize = 0; + pxEnd->pxNextFreeBlock = NULL; + + /* To start with there is a single free block that is sized to take up the + * entire heap space, minus the space taken by pxEnd. */ + pxFirstFreeBlock = ( void * ) pucAlignedHeap; + pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; + pxFirstFreeBlock->pxNextFreeBlock = pxEnd; + + /* Only one block exists - and it covers the entire usable heap space. */ + xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; +} +/*-----------------------------------------------------------*/ + +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) +{ + BlockLink_t * pxIterator; + uint8_t * puc; + + /* Iterate through the list until a block is found that has a higher address + * than the block being inserted. */ + for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) + { + /* Nothing to do here, just iterate to the right position. */ + } + + /* Do the block being inserted, and the block it is being inserted after + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxIterator; + + if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) + { + pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; + pxBlockToInsert = pxIterator; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Do the block being inserted, and the block it is being inserted before + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxBlockToInsert; + + if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) + { + if( pxIterator->pxNextFreeBlock != pxEnd ) + { + /* Form one big block from the two blocks. */ + pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxEnd; + } + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; + } + + /* If the block being inserted plugged a gap, so was merged with the block + * before and the block after, then it's pxNextFreeBlock pointer will have + * already been set, and should not be set here as that would make it point + * to itself. */ + if( pxIterator != pxBlockToInsert ) + { + pxIterator->pxNextFreeBlock = pxBlockToInsert; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} +/*-----------------------------------------------------------*/ + +void * pvPortMalloc( size_t xWantedSize ) +{ + BlockLink_t * pxBlock; + BlockLink_t * pxPreviousBlock; + BlockLink_t * pxNewBlockLink; + void * pvReturn = NULL; + size_t xAdditionalRequiredSize; + size_t xAllocatedBlockSize = 0; + + /* If this is the first call to malloc then the heap will require + * initialisation to setup the list of free blocks. */ + if( pxEnd == NULL ) + { + prvHeapInit(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xWantedSize > 0 ) + { + /* The wanted size must be increased so it can contain a BlockLink_t + * structure in addition to the requested amount of bytes. */ + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 ) + { + xWantedSize += xHeapStructSize; + + /* Ensure that blocks are always aligned to the required number + * of bytes. */ + if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 ) + { + /* Byte alignment required. */ + xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ); + + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 ) + { + xWantedSize += xAdditionalRequiredSize; + } + else + { + xWantedSize = 0; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + xWantedSize = 0; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Check the requested block size is not so large that the top bit is set. + * The top bit of the block size member of the BlockLink_t structure is used + * to determine who owns the block - the application or the kernel, so it + * must be free. */ + if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 ) + { + if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) + { + /* Traverse the list from the start (lowest address) block until + * one of adequate size is found. */ + pxPreviousBlock = &xStart; + pxBlock = xStart.pxNextFreeBlock; + + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + { + pxPreviousBlock = pxBlock; + pxBlock = pxBlock->pxNextFreeBlock; + } + + /* If the end marker was reached then a block of adequate size was + * not found. */ + if( pxBlock != pxEnd ) + { + /* Return the memory space pointed to - jumping over the + * BlockLink_t structure at its start. */ + pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); + + /* This block is being returned for use so must be taken out + * of the list of free blocks. */ + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + + /* If the block is larger than required it can be split into + * two. */ + if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE ) + { + /* This block is to be split into two. Create a new + * block following the number of bytes requested. The void + * cast is used to prevent byte alignment warnings from the + * compiler. */ + pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); + secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + + /* Calculate the sizes of two blocks split from the single + * block. */ + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + pxBlock->xBlockSize = xWantedSize; + + /* Insert the new block into the list of free blocks. */ + pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock; + pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xFreeBytesRemaining -= pxBlock->xBlockSize; + + if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) + { + xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xAllocatedBlockSize = pxBlock->xBlockSize; + + /* The block is being returned - it is allocated and owned by + * the application and has no "next" block. */ + secureheapALLOCATE_BLOCK( pxBlock ); + pxBlock->pxNextFreeBlock = NULL; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceMALLOC( pvReturn, xAllocatedBlockSize ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xAllocatedBlockSize; + + #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) + { + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */ + + secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 ); + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void * pv ) +{ + uint8_t * puc = ( uint8_t * ) pv; + BlockLink_t * pxLink; + + if( pv != NULL ) + { + /* The memory being freed will have an BlockLink_t structure immediately + * before it. */ + puc -= xHeapStructSize; + + /* This casting is to keep the compiler from issuing warnings. */ + pxLink = ( void * ) puc; + + /* Check the block is actually allocated. */ + secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ); + secureportASSERT( pxLink->pxNextFreeBlock == NULL ); + + if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ) + { + if( pxLink->pxNextFreeBlock == NULL ) + { + /* The block is being returned to the heap - it is no longer + * allocated. */ + secureheapFREE_BLOCK( pxLink ); + + secureportDISABLE_NON_SECURE_INTERRUPTS(); + { + /* Add this block to the list of free blocks. */ + xFreeBytesRemaining += pxLink->xBlockSize; + traceFREE( pv, pxLink->xBlockSize ); + prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); + } + secureportENABLE_NON_SECURE_INTERRUPTS(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } +} +/*-----------------------------------------------------------*/ + +size_t xPortGetFreeHeapSize( void ) +{ + return xFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +size_t xPortGetMinimumEverFreeHeapSize( void ) +{ + return xMinimumEverFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM23/secure/secure_heap.h b/portable/GCC/ARM_CM23/secure/secure_heap.h new file mode 100644 index 000000000..0e84a9d9d --- /dev/null +++ b/portable/GCC/ARM_CM23/secure/secure_heap.h @@ -0,0 +1,66 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_HEAP_H__ +#define __SECURE_HEAP_H__ + +/* Standard includes. */ +#include + +/** + * @brief Allocates memory from heap. + * + * @param[in] xWantedSize The size of the memory to be allocated. + * + * @return Pointer to the memory region if the allocation is successful, NULL + * otherwise. + */ +void * pvPortMalloc( size_t xWantedSize ); + +/** + * @brief Frees the previously allocated memory. + * + * @param[in] pv Pointer to the memory to be freed. + */ +void vPortFree( void * pv ); + +/** + * @brief Get the free heap size. + * + * @return Free heap size. + */ +size_t xPortGetFreeHeapSize( void ); + +/** + * @brief Get the minimum ever free heap size. + * + * @return Minimum ever free heap size. + */ +size_t xPortGetMinimumEverFreeHeapSize( void ); + +#endif /* __SECURE_HEAP_H__ */ diff --git a/portable/GCC/ARM_CM23/secure/secure_init.c b/portable/GCC/ARM_CM23/secure/secure_init.c new file mode 100644 index 000000000..c50d37668 --- /dev/null +++ b/portable/GCC/ARM_CM23/secure/secure_init.c @@ -0,0 +1,106 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Secure init includes. */ +#include "secure_init.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Constants required to manipulate the SCB. + */ +#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */ +#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL ) +#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS ) +#define secureinitSCB_AIRCR_PRIS_POS ( 14UL ) +#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS ) + +/** + * @brief Constants required to manipulate the FPU. + */ +#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define secureinitFPCCR_LSPENS_POS ( 29UL ) +#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS ) +#define secureinitFPCCR_TS_POS ( 26UL ) +#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS ) + +#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */ +#define secureinitNSACR_CP10_POS ( 10UL ) +#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS ) +#define secureinitNSACR_CP11_POS ( 11UL ) +#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS ) +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) | + ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) | + ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK ); + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is + * permitted. CP11 should be programmed to the same value as CP10. */ + *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK ); + + /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures + * that we can enable/disable lazy stacking in port.c file. */ + *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK ); + + /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP + * registers (S16-S31) are also pushed to stack on exception entry and + * restored on exception return. */ + *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK ); + } +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM23/secure/secure_init.h b/portable/GCC/ARM_CM23/secure/secure_init.h new file mode 100644 index 000000000..ebe04900f --- /dev/null +++ b/portable/GCC/ARM_CM23/secure/secure_init.h @@ -0,0 +1,54 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_INIT_H__ +#define __SECURE_INIT_H__ + +/** + * @brief De-prioritizes the non-secure exceptions. + * + * This is needed to ensure that the non-secure PendSV runs at the lowest + * priority. Context switch is done in the non-secure PendSV handler. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_DePrioritizeNSExceptions( void ); + +/** + * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access. + * + * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point + * Registers are not leaked to the non-secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_EnableNSFPUAccess( void ); + +#endif /* __SECURE_INIT_H__ */ diff --git a/portable/GCC/ARM_CM23/secure/secure_port_macros.h b/portable/GCC/ARM_CM23/secure/secure_port_macros.h new file mode 100644 index 000000000..a70da2c65 --- /dev/null +++ b/portable/GCC/ARM_CM23/secure/secure_port_macros.h @@ -0,0 +1,140 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_PORT_MACROS_H__ +#define __SECURE_PORT_MACROS_H__ + +/** + * @brief Byte alignment requirements. + */ +#define secureportBYTE_ALIGNMENT 8 +#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 ) + +/** + * @brief Macro to declare a function as non-secure callable. + */ +#if defined( __IAR_SYSTEMS_ICC__ ) + #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry __root +#else + #define secureportNON_SECURE_CALLABLE __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) ) +#endif + +/** + * @brief Set the secure PRIMASK value. + */ +#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Set the non-secure PRIMASK value. + */ +#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Read the PSP value in the given variable. + */ +#define secureportREAD_PSP( pucOutCurrentStackPointer ) \ + __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) ) + +/** + * @brief Set the PSP to the given value. + */ +#define secureportSET_PSP( pucCurrentStackPointer ) \ + __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) ) + +/** + * @brief Read the PSPLIM value in the given variable. + */ +#define secureportREAD_PSPLIM( pucOutStackLimit ) \ + __asm volatile ( "mrs %0, psplim" : "=r" ( pucOutStackLimit ) ) + +/** + * @brief Set the PSPLIM to the given value. + */ +#define secureportSET_PSPLIM( pucStackLimit ) \ + __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) ) + +/** + * @brief Set the NonSecure MSP to the given value. + */ +#define secureportSET_MSP_NS( pucMainStackPointer ) \ + __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) ) + +/** + * @brief Set the CONTROL register to the given value. + */ +#define secureportSET_CONTROL( ulControl ) \ + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" ) + +/** + * @brief Read the Interrupt Program Status Register (IPSR) value in the given + * variable. + */ +#define secureportREAD_IPSR( ulIPSR ) \ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) ) + +/** + * @brief PRIMASK value to enable interrupts. + */ +#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0 + +/** + * @brief PRIMASK value to disable interrupts. + */ +#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1 + +/** + * @brief Disable secure interrupts. + */ +#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Disable non-secure interrupts. + * + * This effectively disables context switches. + */ +#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Enable non-secure interrupts. + */ +#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL ) + +/** + * @brief Assert definition. + */ +#define secureportASSERT( x ) \ + if( ( x ) == 0 ) \ + { \ + secureportDISABLE_SECURE_INTERRUPTS(); \ + secureportDISABLE_NON_SECURE_INTERRUPTS(); \ + for( ; ; ) {; } \ + } + +#endif /* __SECURE_PORT_MACROS_H__ */ diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c new file mode 100644 index 000000000..7a62caff0 --- /dev/null +++ b/portable/GCC/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.c @@ -0,0 +1,2125 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" +#include "event_groups.h" +#include "stream_buffer.h" +#include "mpu_prototypes.h" +#include "mpu_syscall_numbers.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( INCLUDE_xTaskDelayUntil == 1 ) + + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskDelayUntilImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskDelayUntil_Unpriv \n" + " MPU_xTaskDelayUntil_Priv: \n" + " b MPU_xTaskDelayUntilImpl \n" + " MPU_xTaskDelayUntil_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskAbortDelayImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskAbortDelay_Unpriv \n" + " MPU_xTaskAbortDelay_Priv: \n" + " b MPU_xTaskAbortDelayImpl \n" + " MPU_xTaskAbortDelay_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskDelay == 1 ) + + void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskDelayImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vTaskDelay_Unpriv \n" + " MPU_vTaskDelay_Priv: \n" + " b MPU_vTaskDelayImpl \n" + " MPU_vTaskDelay_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskPriorityGet == 1 ) + + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskPriorityGetImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_uxTaskPriorityGet_Unpriv \n" + " MPU_uxTaskPriorityGet_Priv: \n" + " b MPU_uxTaskPriorityGetImpl \n" + " MPU_uxTaskPriorityGet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_eTaskGetState == 1 ) + + eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_eTaskGetStateImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_eTaskGetState_Unpriv \n" + " MPU_eTaskGetState_Priv: \n" + " b MPU_eTaskGetStateImpl \n" + " MPU_eTaskGetState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory" + ); + } + + #endif /* if ( INCLUDE_eTaskGetState == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskGetInfoImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vTaskGetInfo_Unpriv \n" + " MPU_vTaskGetInfo_Priv: \n" + " b MPU_vTaskGetInfoImpl \n" + " MPU_vTaskGetInfo_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory" + ); + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) + + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetIdleTaskHandleImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskGetIdleTaskHandle_Unpriv \n" + " MPU_xTaskGetIdleTaskHandle_Priv: \n" + " b MPU_xTaskGetIdleTaskHandleImpl \n" + " MPU_xTaskGetIdleTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + + void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSuspendImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vTaskSuspend_Unpriv \n" + " MPU_vTaskSuspend_Priv: \n" + " b MPU_vTaskSuspendImpl \n" + " MPU_vTaskSuspend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + + void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskResumeImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vTaskResume_Unpriv \n" + " MPU_vTaskResume_Priv: \n" + " b MPU_vTaskResumeImpl \n" + " MPU_vTaskResume_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + TickType_t MPU_xTaskGetTickCount( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetTickCountImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskGetTickCount_Unpriv \n" + " MPU_xTaskGetTickCount_Priv: \n" + " b MPU_xTaskGetTickCountImpl \n" + " MPU_xTaskGetTickCount_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetNumberOfTasksImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_uxTaskGetNumberOfTasks_Unpriv \n" + " MPU_uxTaskGetNumberOfTasks_Priv: \n" + " b MPU_uxTaskGetNumberOfTasksImpl \n" + " MPU_uxTaskGetNumberOfTasks_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetRunTimeCounterImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_ulTaskGetRunTimeCounter_Unpriv \n" + " MPU_ulTaskGetRunTimeCounter_Priv: \n" + " b MPU_ulTaskGetRunTimeCounterImpl \n" + " MPU_ulTaskGetRunTimeCounter_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetRunTimePercentImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_ulTaskGetRunTimePercent_Unpriv \n" + " MPU_ulTaskGetRunTimePercent_Priv: \n" + " b MPU_ulTaskGetRunTimePercentImpl \n" + " MPU_ulTaskGetRunTimePercent_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetIdleRunTimePercentImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv \n" + " MPU_ulTaskGetIdleRunTimePercent_Priv: \n" + " b MPU_ulTaskGetIdleRunTimePercentImpl \n" + " MPU_ulTaskGetIdleRunTimePercent_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetIdleRunTimeCounterImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv \n" + " MPU_ulTaskGetIdleRunTimeCounter_Priv: \n" + " b MPU_ulTaskGetIdleRunTimeCounterImpl \n" + " MPU_ulTaskGetIdleRunTimeCounter_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetApplicationTaskTagImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vTaskSetApplicationTaskTag_Unpriv \n" + " MPU_vTaskSetApplicationTaskTag_Priv: \n" + " b MPU_vTaskSetApplicationTaskTagImpl \n" + " MPU_vTaskSetApplicationTaskTag_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory" + ); + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetApplicationTaskTagImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskGetApplicationTaskTag_Unpriv \n" + " MPU_xTaskGetApplicationTaskTag_Priv: \n" + " b MPU_xTaskGetApplicationTaskTagImpl \n" + " MPU_xTaskGetApplicationTaskTag_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory" + ); + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetThreadLocalStoragePointerImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv \n" + " MPU_vTaskSetThreadLocalStoragePointer_Priv: \n" + " b MPU_vTaskSetThreadLocalStoragePointerImpl \n" + " MPU_vTaskSetThreadLocalStoragePointer_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory" + ); + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv \n" + " MPU_pvTaskGetThreadLocalStoragePointer_Priv: \n" + " b MPU_pvTaskGetThreadLocalStoragePointerImpl \n" + " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory" + ); + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetSystemStateImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_uxTaskGetSystemState_Unpriv \n" + " MPU_uxTaskGetSystemState_Priv: \n" + " b MPU_uxTaskGetSystemStateImpl \n" + " MPU_uxTaskGetSystemState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory" + ); + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) + + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetStackHighWaterMarkImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_uxTaskGetStackHighWaterMark_Unpriv \n" + " MPU_uxTaskGetStackHighWaterMark_Priv: \n" + " b MPU_uxTaskGetStackHighWaterMarkImpl \n" + " MPU_uxTaskGetStackHighWaterMark_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetStackHighWaterMark2Impl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv \n" + " MPU_uxTaskGetStackHighWaterMark2_Priv: \n" + " b MPU_uxTaskGetStackHighWaterMark2Impl \n" + " MPU_uxTaskGetStackHighWaterMark2_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) + + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetCurrentTaskHandleImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskGetCurrentTaskHandle_Unpriv \n" + " MPU_xTaskGetCurrentTaskHandle_Priv: \n" + " b MPU_xTaskGetCurrentTaskHandleImpl \n" + " MPU_xTaskGetCurrentTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory" + ); + } + + #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetSchedulerState == 1 ) + + BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetSchedulerStateImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskGetSchedulerState_Unpriv \n" + " MPU_xTaskGetSchedulerState_Priv: \n" + " b MPU_xTaskGetSchedulerStateImpl \n" + " MPU_xTaskGetSchedulerState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */ +/*-----------------------------------------------------------*/ + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetTimeOutStateImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vTaskSetTimeOutState_Unpriv \n" + " MPU_vTaskSetTimeOutState_Priv: \n" + " b MPU_vTaskSetTimeOutStateImpl \n" + " MPU_vTaskSetTimeOutState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskCheckForTimeOutImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskCheckForTimeOut_Unpriv \n" + " MPU_xTaskCheckForTimeOut_Priv: \n" + " b MPU_xTaskCheckForTimeOutImpl \n" + " MPU_xTaskCheckForTimeOut_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskGenericNotify_Unpriv \n" + " MPU_xTaskGenericNotify_Priv: \n" + " b MPU_xTaskGenericNotifyImpl \n" + " MPU_xTaskGenericNotify_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyWaitImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskGenericNotifyWait_Unpriv \n" + " MPU_xTaskGenericNotifyWait_Priv: \n" + " b MPU_xTaskGenericNotifyWaitImpl \n" + " MPU_xTaskGenericNotifyWait_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGenericNotifyTakeImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_ulTaskGenericNotifyTake_Unpriv \n" + " MPU_ulTaskGenericNotifyTake_Priv: \n" + " b MPU_ulTaskGenericNotifyTakeImpl \n" + " MPU_ulTaskGenericNotifyTake_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyStateClearImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTaskGenericNotifyStateClear_Unpriv \n" + " MPU_xTaskGenericNotifyStateClear_Priv: \n" + " b MPU_xTaskGenericNotifyStateClearImpl \n" + " MPU_xTaskGenericNotifyStateClear_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGenericNotifyValueClearImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_ulTaskGenericNotifyValueClear_Unpriv \n" + " MPU_ulTaskGenericNotifyValueClear_Priv: \n" + " b MPU_ulTaskGenericNotifyValueClearImpl \n" + " MPU_ulTaskGenericNotifyValueClear_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGenericSendImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xQueueGenericSend_Unpriv \n" + " MPU_xQueueGenericSend_Priv: \n" + " b MPU_xQueueGenericSendImpl \n" + " MPU_xQueueGenericSend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxQueueMessagesWaitingImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_uxQueueMessagesWaiting_Unpriv \n" + " MPU_uxQueueMessagesWaiting_Priv: \n" + " b MPU_uxQueueMessagesWaitingImpl \n" + " MPU_uxQueueMessagesWaiting_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxQueueSpacesAvailableImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_uxQueueSpacesAvailable_Unpriv \n" + " MPU_uxQueueSpacesAvailable_Priv: \n" + " b MPU_uxQueueSpacesAvailableImpl \n" + " MPU_uxQueueSpacesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueReceiveImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xQueueReceive_Unpriv \n" + " MPU_xQueueReceive_Priv: \n" + " b MPU_xQueueReceiveImpl \n" + " MPU_xQueueReceive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueuePeekImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xQueuePeek_Unpriv \n" + " MPU_xQueuePeek_Priv: \n" + " b MPU_xQueuePeekImpl \n" + " MPU_xQueuePeek_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueSemaphoreTakeImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xQueueSemaphoreTake_Unpriv \n" + " MPU_xQueueSemaphoreTake_Priv: \n" + " b MPU_xQueueSemaphoreTakeImpl \n" + " MPU_xQueueSemaphoreTake_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) + + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGetMutexHolderImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xQueueGetMutexHolder_Unpriv \n" + " MPU_xQueueGetMutexHolder_Priv: \n" + " b MPU_xQueueGetMutexHolderImpl \n" + " MPU_xQueueGetMutexHolder_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory" + ); + } + + #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueTakeMutexRecursiveImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xQueueTakeMutexRecursive_Unpriv \n" + " MPU_xQueueTakeMutexRecursive_Priv: \n" + " b MPU_xQueueTakeMutexRecursiveImpl \n" + " MPU_xQueueTakeMutexRecursive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory" + ); + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGiveMutexRecursiveImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xQueueGiveMutexRecursive_Unpriv \n" + " MPU_xQueueGiveMutexRecursive_Priv: \n" + " b MPU_xQueueGiveMutexRecursiveImpl \n" + " MPU_xQueueGiveMutexRecursive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory" + ); + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueSelectFromSetImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xQueueSelectFromSet_Unpriv \n" + " MPU_xQueueSelectFromSet_Priv: \n" + " b MPU_xQueueSelectFromSetImpl \n" + " MPU_xQueueSelectFromSet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory" + ); + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueAddToSetImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xQueueAddToSet_Unpriv \n" + " MPU_xQueueAddToSet_Priv: \n" + " b MPU_xQueueAddToSetImpl \n" + " MPU_xQueueAddToSet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory" + ); + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vQueueAddToRegistryImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vQueueAddToRegistry_Unpriv \n" + " MPU_vQueueAddToRegistry_Priv: \n" + " b MPU_vQueueAddToRegistryImpl \n" + " MPU_vQueueAddToRegistry_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vQueueUnregisterQueueImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vQueueUnregisterQueue_Unpriv \n" + " MPU_vQueueUnregisterQueue_Priv: \n" + " b MPU_vQueueUnregisterQueueImpl \n" + " MPU_vQueueUnregisterQueue_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pcQueueGetNameImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_pcQueueGetName_Unpriv \n" + " MPU_pcQueueGetName_Priv: \n" + " b MPU_pcQueueGetNameImpl \n" + " MPU_pcQueueGetName_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pvTimerGetTimerIDImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_pvTimerGetTimerID_Unpriv \n" + " MPU_pvTimerGetTimerID_Priv: \n" + " b MPU_pvTimerGetTimerIDImpl \n" + " MPU_pvTimerGetTimerID_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTimerSetTimerIDImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vTimerSetTimerID_Unpriv \n" + " MPU_vTimerSetTimerID_Priv: \n" + " b MPU_vTimerSetTimerIDImpl \n" + " MPU_vTimerSetTimerID_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerIsTimerActiveImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTimerIsTimerActive_Unpriv \n" + " MPU_xTimerIsTimerActive_Priv: \n" + " b MPU_xTimerIsTimerActiveImpl \n" + " MPU_xTimerIsTimerActive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv \n" + " MPU_xTimerGetTimerDaemonTaskHandle_Priv: \n" + " b MPU_xTimerGetTimerDaemonTaskHandleImpl \n" + " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGenericCommandFromTaskImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTimerGenericCommandFromTask_Unpriv \n" + " MPU_xTimerGenericCommandFromTask_Priv: \n" + " b MPU_xTimerGenericCommandFromTaskImpl \n" + " MPU_xTimerGenericCommandFromTask_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pcTimerGetNameImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_pcTimerGetName_Unpriv \n" + " MPU_pcTimerGetName_Priv: \n" + " b MPU_pcTimerGetNameImpl \n" + " MPU_pcTimerGetName_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTimerSetReloadModeImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vTimerSetReloadMode_Unpriv \n" + " MPU_vTimerSetReloadMode_Priv: \n" + " b MPU_vTimerSetReloadModeImpl \n" + " MPU_vTimerSetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetReloadModeImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTimerGetReloadMode_Unpriv \n" + " MPU_xTimerGetReloadMode_Priv: \n" + " b MPU_xTimerGetReloadModeImpl \n" + " MPU_xTimerGetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTimerGetReloadModeImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_uxTimerGetReloadMode_Unpriv \n" + " MPU_uxTimerGetReloadMode_Priv: \n" + " b MPU_uxTimerGetReloadModeImpl \n" + " MPU_uxTimerGetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetPeriodImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTimerGetPeriod_Unpriv \n" + " MPU_xTimerGetPeriod_Priv: \n" + " b MPU_xTimerGetPeriodImpl \n" + " MPU_xTimerGetPeriod_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetExpiryTimeImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xTimerGetExpiryTime_Unpriv \n" + " MPU_xTimerGetExpiryTime_Priv: \n" + " b MPU_xTimerGetExpiryTimeImpl \n" + " MPU_xTimerGetExpiryTime_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupWaitBitsImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xEventGroupWaitBits_Unpriv \n" + " MPU_xEventGroupWaitBits_Priv: \n" + " b MPU_xEventGroupWaitBitsImpl \n" + " MPU_xEventGroupWaitBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupClearBitsImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xEventGroupClearBits_Unpriv \n" + " MPU_xEventGroupClearBits_Priv: \n" + " b MPU_xEventGroupClearBitsImpl \n" + " MPU_xEventGroupClearBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupSetBitsImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xEventGroupSetBits_Unpriv \n" + " MPU_xEventGroupSetBits_Priv: \n" + " b MPU_xEventGroupSetBitsImpl \n" + " MPU_xEventGroupSetBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupSyncImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xEventGroupSync_Unpriv \n" + " MPU_xEventGroupSync_Priv: \n" + " b MPU_xEventGroupSyncImpl \n" + " MPU_xEventGroupSync_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxEventGroupGetNumberImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_uxEventGroupGetNumber_Unpriv \n" + " MPU_uxEventGroupGetNumber_Priv: \n" + " b MPU_uxEventGroupGetNumberImpl \n" + " MPU_uxEventGroupGetNumber_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory" + ); + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vEventGroupSetNumberImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_vEventGroupSetNumber_Unpriv \n" + " MPU_vEventGroupSetNumber_Priv: \n" + " b MPU_vEventGroupSetNumberImpl \n" + " MPU_vEventGroupSetNumber_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory" + ); + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSendImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xStreamBufferSend_Unpriv \n" + " MPU_xStreamBufferSend_Priv: \n" + " b MPU_xStreamBufferSendImpl \n" + " MPU_xStreamBufferSend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferReceiveImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xStreamBufferReceive_Unpriv \n" + " MPU_xStreamBufferReceive_Priv: \n" + " b MPU_xStreamBufferReceiveImpl \n" + " MPU_xStreamBufferReceive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferIsFullImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xStreamBufferIsFull_Unpriv \n" + " MPU_xStreamBufferIsFull_Priv: \n" + " b MPU_xStreamBufferIsFullImpl \n" + " MPU_xStreamBufferIsFull_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferIsEmptyImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xStreamBufferIsEmpty_Unpriv \n" + " MPU_xStreamBufferIsEmpty_Priv: \n" + " b MPU_xStreamBufferIsEmptyImpl \n" + " MPU_xStreamBufferIsEmpty_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSpacesAvailableImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xStreamBufferSpacesAvailable_Unpriv \n" + " MPU_xStreamBufferSpacesAvailable_Priv: \n" + " b MPU_xStreamBufferSpacesAvailableImpl \n" + " MPU_xStreamBufferSpacesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferBytesAvailableImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xStreamBufferBytesAvailable_Unpriv \n" + " MPU_xStreamBufferBytesAvailable_Priv: \n" + " b MPU_xStreamBufferBytesAvailableImpl \n" + " MPU_xStreamBufferBytesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSetTriggerLevelImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xStreamBufferSetTriggerLevel_Unpriv \n" + " MPU_xStreamBufferSetTriggerLevel_Priv: \n" + " b MPU_xStreamBufferSetTriggerLevelImpl \n" + " MPU_xStreamBufferSetTriggerLevel_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferNextMessageLengthBytesImpl \n" + " \n" + " push {r0, r1} \n" + " mrs r0, control \n" + " movs r1, #1 \n" + " tst r0, r1 \n" + " pop {r0, r1} \n" + " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv \n" + " MPU_xStreamBufferNextMessageLengthBytes_Priv: \n" + " b MPU_xStreamBufferNextMessageLengthBytesImpl \n" + " MPU_xStreamBufferNextMessageLengthBytes_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c new file mode 100644 index 000000000..76d2b2445 --- /dev/null +++ b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c @@ -0,0 +1,2280 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024-2025 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU includes. */ +#include "mpu_wrappers.h" +#include "mpu_syscall_numbers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration settings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to check the validity of an interrupt priority. + */ +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) ) +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used during system call enter and exit. + */ +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Offsets in the stack to the parameters when inside the SVC handler. + */ +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +#if ( portARMV8M_MINOR_VERSION >= 1 ) + + /* Enable Privileged eXecute Never MPU attribute for the selected memory + * region. */ + #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL ) +#endif /* portARMV8M_MINOR_VERSION >= 1 */ + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Extract first address of the MPU region as encoded in the + * RBAR (Region Base Address Register) value. */ +#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \ + ( ( rbar ) & portMPU_RBAR_ADDRESS_MASK ) + +/* Extract last address of the MPU region as encoded in the + * RLAR (Region Limit Address Register) value. */ +#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \ + ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK ) + +/* Does addr lies within [start, end] address range? */ +#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \ + ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) ) + +/* Is the access request satisfied by the available permissions? */ +#define portIS_AUTHORIZED( accessRequest, permissions ) \ + ( ( ( permissions ) & ( accessRequest ) ) == accessRequest ) + +/* Max value that fits in a uint32_t type. */ +#define portUINT32_MAX ( ~( ( uint32_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. + */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 + +/** + * @brief Constants required to check and configure PACBTI security feature implementation. + */ +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) ) + + #define portCONTROL_UPAC_EN ( 1UL << 7UL ) + #define portCONTROL_PAC_EN ( 1UL << 6UL ) + #define portCONTROL_UBTI_EN ( 1UL << 5UL ) + #define portCONTROL_BTI_EN ( 1UL << 4UL ) + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Extract MPU region's access permissions from the Region Base Address + * Register (RBAR) value. + * + * @param ulRBARValue RBAR value for the MPU region. + * + * @return uint32_t Access permissions. + */ + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + + /** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + /** + * @brief Configures PACBTI features. + * + * This function configures the Pointer Authentication, and Branch Target + * Identification security features as per the user configuration. It returns + * the value of the special purpose CONTROL register accordingly, and optionally + * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M + * architecture based) target supports PACBTI security feature. + * + * @param xWriteControlRegister Used to control whether the special purpose + * CONTROL register should be updated or not. + * + * @return CONTROL register value according to the configured PACBTI option. + */ + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the system call stack so that upon returning from + * SVC, the system call stack is used. + * + * @param pulTaskStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + * @param ucSystemCallNumber The system call number of the system call. + */ + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Raise SVC for exiting from a system call. + */ + void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief This variable is set to pdTRUE when the scheduler is started. + */ + PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + + /** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +/** + * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + /** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + + /** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + + /** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the cpsid instruction + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessPermissions = 0; + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_ONLY ) + { + ulAccessPermissions = tskMPU_READ_PERMISSION; + } + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_WRITE ) + { + ulAccessPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION ); + } + + return ulAccessPermissions; + } + +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } + +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ portOFFSET_TO_PC ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ]; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulSystemCallStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the system call section (i.e. application is + * not raising SVC directly). + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as + * it is non-NULL only during the execution of a system call (i.e. + * between system call enter and exit). + * 3. System call is not for a kernel API disabled by the configuration + * in FreeRTOSConfig.h. + * 4. We do not need to check that ucSystemCallNumber is within range + * because the assembly SVC handler checks that before calling + * this function. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) && + ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) ) + { + pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the system call stack for the stack frame. */ + pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulSystemCallStack[ i ] = pulTaskStack[ i ]; + } + + /* Store the value of the Link Register before the SVC was raised. + * It contains the address of the caller of the System Call entry + * point (i.e. the caller of the MPU_). We need to restore it + * when we exit from the system call. */ + pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; + + /* Store the value of the PSPLIM register before the SVC was raised. + * We need to restore it when we exit from the system call. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* Use the pulSystemCallStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif + + /* Start executing the system call upon returning from this handler. */ + pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; + + /* Raise a request to exit from the system call upon finishing the + * system call. */ + pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; + + /* Remember the location where we should copy the stack frame when we exit from + * the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize; + + /* Record if the hardware used padding to force the stack pointer + * to be double word aligned. */ + if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK ) + { + pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG; + } + else + { + pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG ); + } + + /* We ensure in pxPortInitialiseStack that the system call stack is + * double word aligned and therefore, there is no need of padding. + * Clear the bit[9] of stacked xPSR. */ + pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + + /* Raise the privilege for the duration of the system call. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " bics r0, r1 \n" /* Clear nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */ + { + __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulTaskStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the privileged code (i.e. application is not + * raising SVC directly). This SVC is only raised from + * vRequestSystemCallExit which is in the privileged code section. + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL - + * this means that we previously entered a system call and the + * application is not attempting to exit without entering a system + * call. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) ) + { + pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the task stack for the stack frame. */ + pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulTaskStack[ i ] = pulSystemCallStack[ i ]; + } + + /* Use the pulTaskStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) ); + + /* Return to the caller of the System Call entry point (i.e. the + * caller of the MPU_). */ + pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + /* Ensure that LR has a valid value.*/ + pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + + /* Restore the PSPLIM register to what it was at the time of + * system call entry. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* If the hardware used padding to force the stack pointer + * to be double word aligned, set the stacked xPSR bit[9], + * otherwise clear it. */ + if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG ) + { + pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK; + } + else + { + pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + } + + /* This is not NULL only for the duration of the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; + + /* Drop the privilege before returning to the thread mode. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " orrs r0, r1 \n" /* Set nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xTaskIsPrivileged = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xTaskIsPrivileged = pdTRUE; + } + + return xTaskIsPrivileged; + } + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged, + xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulIndex = 0; + uint32_t ulControl = 0x0; + + xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ + ulIndex++; + + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + ulIndex++; + + #if ( configENABLE_TRUSTZONE == 1 ) + { + xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */ + ulIndex++; + } + #endif /* configENABLE_TRUSTZONE */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + ulIndex++; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Check PACBTI security feature configuration before pushing the + * CONTROL register's value on task's TCB. */ + ulControl = prvConfigurePACBTI( pdFALSE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + if( xRunPrivileged == pdTRUE ) + { + xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + else + { + xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG ); + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ + ulIndex++; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + { + /* Ensure that the system call stack is double word aligned. */ + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) + + ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + /* This is not NULL only for the duration of a system call. */ + xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL; + } + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ]; + ulIndex++; + } + } + #endif /* configENABLE_PAC */ + + return &( xMPUSettings->ulContext[ ulIndex ] ); + } + +#else /* configENABLE_MPU */ + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ + { + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + pxTopOfStack--; + *pxTopOfStack = ulTaskPacKey[ i ]; + } + } + #endif /* configENABLE_PAC */ + + return pxTopOfStack; + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Set the CONTROL register value based on PACBTI security feature + * configuration before starting the first task. */ + ( void ) prvConfigurePACBTI( pdTRUE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + { + xSchedulerRunning = pdTRUE; + } + #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + configSTACK_DEPTH_TYPE uxStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( uxStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* PXN. */ + #if ( portARMV8M_MINOR_VERSION >= 1 ) + { + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ); + } + } + #endif /* portARMV8M_MINOR_VERSION >= 1 */ + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, + uint32_t ulBufferLength, + uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */ + + { + uint32_t i, ulBufferStartAddress, ulBufferEndAddress; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE ) + { + ulBufferStartAddress = ( uint32_t ) pvBuffer; + ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL ); + + for( i = 0; i < portTOTAL_NUM_REGIONS; i++ ) + { + /* Is the MPU region enabled? */ + if( ( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR & portMPU_RLAR_REGION_ENABLE ) == portMPU_RLAR_REGION_ENABLE ) + { + if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_AUTHORIZED( ulAccessRequested, + prvGetRegionAccessPermissions( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ) ) ) + { + xAccessGranted = pdTRUE; + break; + } + } + } + } + } + + return xAccessGranted; + } + +#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings; + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else + { + xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 ) + { + xAccessGranted = pdTRUE; + } + } + } + + return xAccessGranted; + } + + #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + ( void ) lInternalIndexOfKernelObject; + + /* If Access Control List feature is not used, all the tasks have + * access to all the kernel objects. */ + return pdTRUE; + } + + #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + { + uint32_t ulControl = 0x0; + + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); + + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; + + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c new file mode 100644 index 000000000..d215f8f73 --- /dev/null +++ b/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c @@ -0,0 +1,516 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION + * is defined correctly and privileged functions are placed in correct sections. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Portasm includes. */ +#include "portasm.h" + +/* System call numbers includes. */ +#include "mpu_syscall_numbers.h" + +/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the + * header files. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#if ( configENABLE_FPU == 1 ) + #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0. +#endif + +#if ( configENABLE_MPU == 1 ) + + void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " program_mpu_first_task: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r3] \n" /* r0 = pxCurrentTCB.*/ + " \n" + " dmb \n" /* Complete outstanding transfers before disabling MPU. */ + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " movs r3, #1 \n" /* r3 = 1. */ + " bics r2, r3 \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */ + " str r2, [r1] \n" /* Disable MPU. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */ + " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r1, [r2] \n" /* Program MAIR0. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */ + " \n" + " movs r3, #4 \n" /* r3 = 4. */ + " str r3, [r1] \n" /* Program RNR = 4. */ + " ldmia r0!, {r4-r5} \n" /* Read first set of RBAR/RLAR registers from TCB. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " stmia r2!, {r4-r5} \n" /* Write first set of RBAR/RLAR registers. */ + " movs r3, #5 \n" /* r3 = 5. */ + " str r3, [r1] \n" /* Program RNR = 5. */ + " ldmia r0!, {r4-r5} \n" /* Read second set of RBAR/RLAR registers from TCB. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " stmia r2!, {r4-r5} \n" /* Write second set of RBAR/RLAR registers. */ + " movs r3, #6 \n" /* r3 = 6. */ + " str r3, [r1] \n" /* Program RNR = 6. */ + " ldmia r0!, {r4-r5} \n" /* Read third set of RBAR/RLAR registers from TCB. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " stmia r2!, {r4-r5} \n" /* Write third set of RBAR/RLAR registers. */ + " movs r3, #7 \n" /* r3 = 6. */ + " str r3, [r1] \n" /* Program RNR = 7. */ + " ldmia r0!, {r4-r5} \n" /* Read fourth set of RBAR/RLAR registers from TCB. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " stmia r2!, {r4-r5} \n" /* Write fourth set of RBAR/RLAR registers. */ + " \n" + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " movs r3, #1 \n" /* r3 = 1. */ + " orrs r2, r3 \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */ + " str r2, [r1] \n" /* Enable MPU. */ + " dsb \n" /* Force memory writes before continuing. */ + " \n" + " restore_context_first_task: \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/ + " ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */ + " \n" + " restore_special_regs_first_task: \n" + " subs r1, #16 \n" + " ldmia r1!, {r2-r5} \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */ + " subs r1, #16 \n" + " msr psp, r2 \n" + #if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + " msr psplim, r3 \n" + #endif + " msr control, r4 \n" + " mov lr, r5 \n" + " \n" + " restore_general_regs_first_task: \n" + " subs r1, #32 \n" + " ldmia r1!, {r4-r7} \n" /* r4-r7 contain half of the hardware saved context. */ + " stmia r2!, {r4-r7} \n" /* Copy half of the the hardware saved context on the task stack. */ + " ldmia r1!, {r4-r7} \n" /* r4-r7 contain rest half of the hardware saved context. */ + " stmia r2!, {r4-r7} \n" /* Copy rest half of the the hardware saved context on the task stack. */ + " subs r1, #48 \n" + " ldmia r1!, {r4-r7} \n" /* Restore r8-r11. */ + " mov r8, r4 \n" /* r8 = r4. */ + " mov r9, r5 \n" /* r9 = r5. */ + " mov r10, r6 \n" /* r10 = r6. */ + " mov r11, r7 \n" /* r11 = r7. */ + " subs r1, #32 \n" + " ldmia r1!, {r4-r7} \n" /* Restore r4-r7. */ + " subs r1, #16 \n" + " \n" + " restore_context_done_first_task: \n" + " str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */ + " bx lr \n" + ); + } + +#else /* configENABLE_MPU */ + + void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + " ldr r0, [r1] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + " \n" + " ldm r0!, {r1-r2} \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */ + #if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + " msr psplim, r1 \n" /* Set this task's PSPLIM value. */ + #endif + " movs r1, #2 \n" /* r1 = 2. */ + " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */ + " adds r0, #32 \n" /* Discard everything up to r0. */ + " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */ + " isb \n" + " bx r2 \n" /* Finally, branch to EXC_RETURN. */ + ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* r0 = CONTROL. */ + " movs r1, #1 \n" /* r1 = 1. */ + " tst r0, r1 \n" /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */ + " beq running_privileged \n" /* If the result of previous AND operation was 0, branch. */ + " movs r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + " bx lr \n" /* Return. */ + " running_privileged: \n" + " movs r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + " bx lr \n" /* Return. */ + ::: "r0", "r1", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* Read the CONTROL register. */ + " movs r1, #1 \n" /* r1 = 1. */ + " bics r0, r1 \n" /* Clear the bit 0. */ + " msr control, r0 \n" /* Write back the new CONTROL value. */ + " bx lr \n" /* Return to the caller. */ + ::: "r0", "r1", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vResetPrivilege( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* r0 = CONTROL. */ + " movs r1, #1 \n" /* r1 = 1. */ + " orrs r0, r1 \n" /* r0 = r0 | r1. */ + " msr control, r0 \n" /* CONTROL = r0. */ + " bx lr \n" /* Return to the caller. */ + ::: "r0", "r1", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r0, =0xe000ed08 \n" /* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */ + " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */ + " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */ + " cpsie i \n" /* Globally enable interrupts. */ + " dsb \n" + " isb \n" + " svc %0 \n" /* System call to start the first task. */ + " nop \n" + ::"i" ( portSVC_START_SCHEDULER ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, PRIMASK \n" + " cpsid i \n" + " bx lr \n" + ::: "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " msr PRIMASK, r0 \n" + " bx lr \n" + ::: "memory" + ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */ + " ldr r1, [r0] \n" /* r1 = Location in TCB where the context should be saved. */ + " mrs r2, psp \n" /* r2 = PSP. */ + " \n" + " save_general_regs: \n" + " stmia r1!, {r4-r7} \n" /* Store r4-r7. */ + " mov r4, r8 \n" /* r4 = r8. */ + " mov r5, r9 \n" /* r5 = r9. */ + " mov r6, r10 \n" /* r6 = r10. */ + " mov r7, r11 \n" /* r7 = r11. */ + " stmia r1!, {r4-r7} \n" /* Store r8-r11. */ + " ldmia r2!, {r4-r7} \n" /* Copy half of the hardware saved context into r4-r7. */ + " stmia r1!, {r4-r7} \n" /* Store the hardware saved context. */ + " ldmia r2!, {r4-r7} \n" /* Copy rest half of the hardware saved context into r4-r7. */ + " stmia r1!, {r4-r7} \n" /* Store the hardware saved context. */ + " \n" + " save_special_regs: \n" + " mrs r2, psp \n" /* r2 = PSP. */ + #if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + " mrs r3, psplim \n" /* r3 = PSPLIM. */ + #else + " movs r3, #0 \n" /* r3 = 0. 0 is stored in the PSPLIM slot. */ + #endif + " mrs r4, control \n" /* r4 = CONTROL. */ + " mov r5, lr \n" /* r5 = LR. */ + " stmia r1!, {r2-r5} \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ + " str r1, [r0] \n" /* Save the location from where the context should be restored as the first member of TCB. */ + " \n" + " select_next_task: \n" + " cpsid i \n" + " bl vTaskSwitchContext \n" + " cpsie i \n" + " \n" + " program_mpu: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r3] \n" /* r0 = pxCurrentTCB.*/ + " \n" + " dmb \n" /* Complete outstanding transfers before disabling MPU. */ + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " movs r3, #1 \n" /* r3 = 1. */ + " bics r2, r3 \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */ + " str r2, [r1] \n" /* Disable MPU. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */ + " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r1, [r2] \n" /* Program MAIR0. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */ + " \n" + " movs r3, #4 \n" /* r3 = 4. */ + " str r3, [r1] \n" /* Program RNR = 4. */ + " ldmia r0!, {r4-r5} \n" /* Read first set of RBAR/RLAR registers from TCB. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " stmia r2!, {r4-r5} \n" /* Write first set of RBAR/RLAR registers. */ + " movs r3, #5 \n" /* r3 = 5. */ + " str r3, [r1] \n" /* Program RNR = 5. */ + " ldmia r0!, {r4-r5} \n" /* Read second set of RBAR/RLAR registers from TCB. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " stmia r2!, {r4-r5} \n" /* Write second set of RBAR/RLAR registers. */ + " movs r3, #6 \n" /* r3 = 6. */ + " str r3, [r1] \n" /* Program RNR = 6. */ + " ldmia r0!, {r4-r5} \n" /* Read third set of RBAR/RLAR registers from TCB. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " stmia r2!, {r4-r5} \n" /* Write third set of RBAR/RLAR registers. */ + " movs r3, #7 \n" /* r3 = 6. */ + " str r3, [r1] \n" /* Program RNR = 7. */ + " ldmia r0!, {r4-r5} \n" /* Read fourth set of RBAR/RLAR registers from TCB. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " stmia r2!, {r4-r5} \n" /* Write fourth set of RBAR/RLAR registers. */ + " \n" + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " movs r3, #1 \n" /* r3 = 1. */ + " orrs r2, r3 \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */ + " str r2, [r1] \n" /* Enable MPU. */ + " dsb \n" /* Force memory writes before continuing. */ + " \n" + " restore_context: \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/ + " ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */ + " \n" + " restore_special_regs: \n" + " subs r1, #16 \n" + " ldmia r1!, {r2-r5} \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */ + " subs r1, #16 \n" + " msr psp, r2 \n" + #if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + " msr psplim, r3 \n" + #endif + " msr control, r4 \n" + " mov lr, r5 \n" + " \n" + " restore_general_regs: \n" + " subs r1, #32 \n" + " ldmia r1!, {r4-r7} \n" /* r4-r7 contain half of the hardware saved context. */ + " stmia r2!, {r4-r7} \n" /* Copy half of the the hardware saved context on the task stack. */ + " ldmia r1!, {r4-r7} \n" /* r4-r7 contain rest half of the hardware saved context. */ + " stmia r2!, {r4-r7} \n" /* Copy rest half of the the hardware saved context on the task stack. */ + " subs r1, #48 \n" + " ldmia r1!, {r4-r7} \n" /* Restore r8-r11. */ + " mov r8, r4 \n" /* r8 = r4. */ + " mov r9, r5 \n" /* r9 = r5. */ + " mov r10, r6 \n" /* r10 = r6. */ + " mov r11, r7 \n" /* r11 = r7. */ + " subs r1, #32 \n" + " ldmia r1!, {r4-r7} \n" /* Restore r4-r7. */ + " subs r1, #16 \n" + " \n" + " restore_context_done: \n" + " str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */ + " bx lr \n" + ); + } + +#else /* configENABLE_MPU */ + + void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, psp \n" /* Read PSP in r0. */ + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + " subs r0, r0, #40 \n" /* Make space for PSPLIM, LR and the remaining registers on the stack. */ + " str r0, [r1] \n" /* Save the new top of stack in TCB. */ + #if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + " mrs r2, psplim \n" /* r2 = PSPLIM. */ + #else + " movs r2, #0 \n" /* r2 = 0. 0 is stored in the PSPLIM slot. */ + #endif + " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */ + " stmia r0!, {r2-r7} \n" /* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */ + " mov r4, r8 \n" /* r4 = r8. */ + " mov r5, r9 \n" /* r5 = r9. */ + " mov r6, r10 \n" /* r6 = r10. */ + " mov r7, r11 \n" /* r7 = r11. */ + " stmia r0!, {r4-r7} \n" /* Store the high registers that are not saved automatically. */ + " \n" + " cpsid i \n" + " bl vTaskSwitchContext \n" + " cpsie i \n" + " \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ + " \n" + " adds r0, r0, #24 \n" /* Move to the high registers. */ + " ldmia r0!, {r4-r7} \n" /* Restore the high registers that are not automatically restored. */ + " mov r8, r4 \n" /* r8 = r4. */ + " mov r9, r5 \n" /* r9 = r5. */ + " mov r10, r6 \n" /* r10 = r6. */ + " mov r11, r7 \n" /* r11 = r7. */ + " msr psp, r0 \n" /* Remember the new top of stack for the task. */ + " subs r0, r0, #40 \n" /* Move to the starting of the saved context. */ + " ldmia r0!, {r2-r7} \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */ + #if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */ + #endif + " bx r3 \n" + ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + ".syntax unified \n" + ".extern vPortSVCHandler_C \n" + ".extern vSystemCallEnter \n" + ".extern vSystemCallExit \n" + " \n" + "movs r0, #4 \n" + "mov r1, lr \n" + "tst r0, r1 \n" + "beq stack_on_msp \n" + "stack_on_psp: \n" + " mrs r0, psp \n" + " b route_svc \n" + "stack_on_msp: \n" + " mrs r0, msp \n" + " b route_svc \n" + " \n" + "route_svc: \n" + " ldr r3, [r0, #24] \n" + " subs r3, #2 \n" + " ldrb r2, [r3, #0] \n" + " cmp r2, %0 \n" + " blt system_call_enter \n" + " cmp r2, %1 \n" + " beq system_call_exit \n" + " b vPortSVCHandler_C \n" + " \n" + "system_call_enter: \n" + " b vSystemCallEnter \n" + "system_call_exit: \n" + " b vSystemCallExit \n" + " \n" + : /* No outputs. */ + : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT ) + : "r0", "r1", "r2", "r3", "memory" + ); + } + +#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " movs r0, #4 \n" + " mov r1, lr \n" + " tst r0, r1 \n" + " beq stacking_used_msp \n" + " mrs r0, psp \n" + " ldr r2, =vPortSVCHandler_C \n" + " bx r2 \n" + " stacking_used_msp: \n" + " mrs r0, msp \n" + " ldr r2, =vPortSVCHandler_C \n" + " bx r2 \n" + ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h b/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h new file mode 100644 index 000000000..b7021b024 --- /dev/null +++ b/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kernel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h new file mode 100644 index 000000000..e81b89228 --- /dev/null +++ b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h @@ -0,0 +1,85 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M23" +#define portHAS_ARMV8M_MAIN_EXTENSION 0 +#define portARMV8M_MINOR_VERSION 0 +#define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +#if ( configTOTAL_MPU_REGIONS == 16 ) + #error 16 MPU regions are not yet supported for this port. +#endif + +#ifndef configENABLE_MVE + #define configENABLE_MVE 0 +#elif ( configENABLE_MVE != 0 ) + #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M23. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" ) +#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h new file mode 100644 index 000000000..f373bcad5 --- /dev/null +++ b/portable/GCC/ARM_CM23_NTZ/non_secure/portmacrocommon.h @@ -0,0 +1,582 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACROCOMMON_H +#define PORTMACROCOMMON_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. +#endif /* configENABLE_FPU */ + +#ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. +#endif /* configENABLE_MPU */ + +#ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. +#endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() +#define portINLINE __inline +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif +#define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ +extern BaseType_t xPortIsInsideInterrupt( void ); + +extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + +extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; +extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + +extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; +extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + +#if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_PAC == 1 ) + + /** + * @brief Generates 128-bit task's random PAC key. + * + * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be + * filled with a 128-bit random number. + */ + void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); + +#endif /* configENABLE_PAC */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ +#if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) +#else + #define portPRIVILEGE_BIT ( 0x0UL ) +#endif /* configENABLE_MPU */ + +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ +#define portPRIVILEGED_FLASH_REGION ( 0UL ) +#define portUNPRIVILEGED_FLASH_REGION ( 1UL ) +#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) +#define portPRIVILEGED_RAM_REGION ( 3UL ) +#define portSTACK_REGION ( 4UL ) +#define portFIRST_CONFIGURABLE_REGION ( 5UL ) +#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) +#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) +#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ +#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ +#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ +#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ +#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ +#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ +#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ +#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) +#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) +#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + +#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) +#define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) +#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) +#define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + +#define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + #ifndef configSYSTEM_CALL_STACK_SIZE + #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. + #endif + + /** + * @brief System call stack. + */ + typedef struct SYSTEM_CALL_STACK_INFO + { + uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; + uint32_t * pulSystemCallStack; + uint32_t * pulSystemCallStackLimit; + uint32_t * pulTaskStack; + uint32_t ulLinkRegisterAtSystemCallEntry; + uint32_t ulStackLimitRegisterAtSystemCallEntry; + } xSYSTEM_CALL_STACK_INFO; + + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + /** + * @brief MPU settings as stored in the TCB. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><-----------><----> + * 16 17 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 71 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 17 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 55 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | | | PC, xPSR | EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><-----------><----> + * 16 17 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 70 + + #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + /* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 17 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 54 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+------------------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +----------+-----------------+------------------------------+------------+-----+ + * + * <---------><----------------><------------------------------><-----------><----> + * 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 38 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+----------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | PC, xPSR | EXC_RETURN | | | + * +----------+-----------------+----------------------+------------+-----+ + * + * <---------><----------------><----------------------><-----------><----> + * 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 37 + + #else /* #if( configENABLE_TRUSTZONE == 1 ) */ + + /* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) + + /* Size of an Access Control List (ACL) entry in bits. */ + #define portACL_ENTRY_SIZE_BITS ( 32U ) + + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + uint32_t ulContext[ MAX_CONTEXT_SIZE ]; + uint32_t ulTaskFlags; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo; + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ]; + #endif + #endif + } xMPU_SETTINGS; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Validate priority of ISRs that are allowed to call FreeRTOS + * system calls. + */ +#if ( configASSERT_DEFINED == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif +#endif + +/** + * @brief SVC numbers. + */ +#define portSVC_ALLOCATE_SECURE_CONTEXT 100 +#define portSVC_FREE_SECURE_CONTEXT 101 +#define portSVC_START_SCHEDULER 102 +#define portSVC_RAISE_PRIVILEGE 103 +#define portSVC_SYSTEM_CALL_EXIT 104 +#define portSVC_YIELD 105 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) +#endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() +#else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + extern BaseType_t xPortIsTaskPrivileged( void ); + +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACROCOMMON_H */ diff --git a/portable/GCC/ARM_CM3/port.c b/portable/GCC/ARM_CM3/port.c new file mode 100644 index 000000000..f2a6a1e83 --- /dev/null +++ b/portable/GCC/ARM_CM3/port.c @@ -0,0 +1,822 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ARM CM3 port. +*----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Prototype of all Interrupt Service Routines (ISRs). */ +typedef void ( * portISR_t )( void ); + +/* Constants required to manipulate the core. Registers first... */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +/* ...then bits in the registers. */ +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) + +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL ) +#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL ) + +/* Constants used to check the installation of the FreeRTOS interrupt handlers. */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xE000ED08 ) ) +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) + +/* Constants required to check the validity of an interrupt priority. */ +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) + +/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */ +#define portVECTACTIVE_MASK ( 0xFFUL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000UL ) + +/* The systick is a 24-bit counter. */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/* A fiddle factor to estimate the number of SysTick counts that would have + * occurred while the SysTick counter is stopped during tickless idle + * calculations. */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) + +/* For strict compliance with the Cortex-M spec the task start address should + * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */ +#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL ) + +/* Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/* Let the user override the pre-loading of the initial LR with the address of + * prvTaskExitError() in case it messes up unwinding of the stack in the + * debugger. */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ); + +/* + * Exception handlers. + */ +void xPortPendSVHandler( void ) __attribute__( ( naked ) ); +void xPortSysTickHandler( void ); +void vPortSVCHandler( void ) __attribute__( ( naked ) ); + +/* + * Start first task is a separate function so it can be tested in isolation. + */ +static void prvPortStartFirstTask( void ) __attribute__( ( naked ) ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* Each task maintains its own interrupt status in the critical nesting + * variable. */ +static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +/* + * The number of SysTick increments that make up one tick period. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulTimerCountsForOneTick = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * The maximum number of tick periods that can be suppressed is limited by the + * 24 bit resolution of the SysTick timer. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t xMaximumPossibleSuppressedTicks = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Compensate for the CPU cycles that pass while the SysTick is stopped (low + * power functionality only. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( configASSERT_DEFINED == 1 ) + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16; +#endif /* configASSERT_DEFINED */ + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ + configASSERT( uxCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being defined + * but never called. ulDummy is used purely to quieten other warnings + * about code appearing after this function is called - making ulDummy + * volatile makes the compiler think the function could return and + * therefore not output an 'unreachable code' warning for code that appears + * after it. */ + } +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler( void ) +{ + __asm volatile ( + " ldr r3, =pxCurrentTCB \n" /* Restore the context. */ + " ldr r1, [r3] \n" /* Get the pxCurrentTCB address. */ + " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */ + " ldmia r0!, {r4-r11} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */ + " msr psp, r0 \n" /* Restore the task stack pointer. */ + " isb \n" + " mov r0, #0 \n" + " msr basepri, r0 \n" + " orr r14, #0xd \n" + " bx r14 \n" + " \n" + " .ltorg \n" + ); +} +/*-----------------------------------------------------------*/ + +static void prvPortStartFirstTask( void ) +{ + __asm volatile ( + " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n" + " ldr r0, [r0] \n" + " msr msp, r0 \n" /* Set the msp back to the start of the stack. */ + " cpsie i \n" /* Globally enable interrupts. */ + " cpsie f \n" + " dsb \n" + " isb \n" + " svc 0 \n" /* System call to start first task. */ + " nop \n" + " .ltorg \n" + ); +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions vPortSVCHandler and + * xPortPendSVHandler for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * vPortSVCHandler and xPortPendSVHandler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( configASSERT_DEFINED == 1 ) + { + volatile uint8_t ucOriginalPriority; + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * Save the interrupt priority value that is about to be clobbered. */ + ucOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to all + * possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + + /* Restore the clobbered interrupt priority register to its original + * value. */ + *pucFirstUserPriorityRegister = ucOriginalPriority; + } + #endif /* configASSERT_DEFINED */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + /* Start the first task. */ + prvPortStartFirstTask(); + + /* Should never get here as the tasks will now be executing! Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimisation does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ + if( uxCriticalNesting == 1 ) + { + configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void xPortPendSVHandler( void ) +{ + /* This is a naked function. */ + + __asm volatile + ( + " mrs r0, psp \n" + " isb \n" + " \n" + " ldr r3, =pxCurrentTCB \n" /* Get the location of the current TCB. */ + " ldr r2, [r3] \n" + " \n" + " stmdb r0!, {r4-r11} \n" /* Save the remaining registers. */ + " str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */ + " \n" + " stmdb sp!, {r3, r14} \n" + " mov r0, %0 \n" + " msr basepri, r0 \n" + " bl vTaskSwitchContext \n" + " mov r0, #0 \n" + " msr basepri, r0 \n" + " ldmia sp!, {r3, r14} \n" + " \n" /* Restore the context, including the critical nesting count. */ + " ldr r1, [r3] \n" + " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */ + " ldmia r0!, {r4-r11} \n" /* Pop the registers. */ + " msr psp, r0 \n" + " isb \n" + " bx r14 \n" + " \n" + " .ltorg \n" + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + /* The SysTick runs at the lowest interrupt priority, so when this interrupt + * executes all interrupts must be unmasked. There is therefore no need to + * save and then restore the interrupt mask value as its value is already + * known. */ + portDISABLE_INTERRUPTS(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + + /* A context switch is required. Context switching is performed in + * the PendSV interrupt. Pend the PendSV interrupt. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + portENABLE_INTERRUPTS(); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the cpsid instruction + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and clear the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); +} +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* configASSERT_DEFINED */ diff --git a/portable/GCC/ARM_CM3/portmacro.h b/portable/GCC/ARM_CM3/portmacro.h new file mode 100644 index 000000000..75dbcfa6c --- /dev/null +++ b/portable/GCC/ARM_CM3/portmacro.h @@ -0,0 +1,265 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/* Scheduler utilities. */ +#define portYIELD() \ + { \ + /* Set a PendSV to request a context switch. */ \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + \ + /* Barriers are normally not required but do ensure the code is completely \ + * within the specified behaviour for the architecture. */ \ + __asm volatile ( "dsb" ::: "memory" ); \ + __asm volatile ( "isb" ); \ + } + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portYIELD(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x ) +#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() +#define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not necessary for to use this port. They are defined so the common demo files + * (which build with all the ports) will build. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +/* Tickless idle/low power functionality. */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specific optimisations. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + +/* Generic helper function. */ + __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint8_t ucReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ucReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif + +/* portNOP() is not required by this port. */ +#define portNOP() + +#define portINLINE __inline + +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif + +/*-----------------------------------------------------------*/ + +portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} + +/*-----------------------------------------------------------*/ + +portFORCE_INLINE static void vPortRaiseBASEPRI( void ) +{ + uint32_t ulNewBASEPRI; + + __asm volatile + ( + " mov %0, %1 \n" \ + " msr basepri, %0 \n" \ + " isb \n" \ + " dsb \n" \ + : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); +} + +/*-----------------------------------------------------------*/ + +portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void ) +{ + uint32_t ulOriginalBASEPRI, ulNewBASEPRI; + + __asm volatile + ( + " mrs %0, basepri \n" \ + " mov %1, %2 \n" \ + " msr basepri, %1 \n" \ + " isb \n" \ + " dsb \n" \ + : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); + + /* This return will not be reached but is necessary to prevent compiler + * warnings. */ + return ulOriginalBASEPRI; +} +/*-----------------------------------------------------------*/ + +portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) +{ + __asm volatile + ( + " msr basepri, %0 " ::"r" ( ulNewMaskValue ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c new file mode 100644 index 000000000..33410a0c3 --- /dev/null +++ b/portable/GCC/ARM_CM33/non_secure/mpu_wrappers_v2_asm.c @@ -0,0 +1,2056 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" +#include "event_groups.h" +#include "stream_buffer.h" +#include "mpu_prototypes.h" +#include "mpu_syscall_numbers.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( INCLUDE_xTaskDelayUntil == 1 ) + + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskDelayUntilImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskDelayUntil_Unpriv \n" + " MPU_xTaskDelayUntil_Priv: \n" + " b MPU_xTaskDelayUntilImpl \n" + " MPU_xTaskDelayUntil_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskAbortDelayImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskAbortDelay_Unpriv \n" + " MPU_xTaskAbortDelay_Priv: \n" + " b MPU_xTaskAbortDelayImpl \n" + " MPU_xTaskAbortDelay_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskDelay == 1 ) + + void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskDelayImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskDelay_Unpriv \n" + " MPU_vTaskDelay_Priv: \n" + " b MPU_vTaskDelayImpl \n" + " MPU_vTaskDelay_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskPriorityGet == 1 ) + + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskPriorityGetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskPriorityGet_Unpriv \n" + " MPU_uxTaskPriorityGet_Priv: \n" + " b MPU_uxTaskPriorityGetImpl \n" + " MPU_uxTaskPriorityGet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_eTaskGetState == 1 ) + + eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_eTaskGetStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_eTaskGetState_Unpriv \n" + " MPU_eTaskGetState_Priv: \n" + " b MPU_eTaskGetStateImpl \n" + " MPU_eTaskGetState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory" + ); + } + + #endif /* if ( INCLUDE_eTaskGetState == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskGetInfoImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskGetInfo_Unpriv \n" + " MPU_vTaskGetInfo_Priv: \n" + " b MPU_vTaskGetInfoImpl \n" + " MPU_vTaskGetInfo_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory" + ); + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) + + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetIdleTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetIdleTaskHandle_Unpriv \n" + " MPU_xTaskGetIdleTaskHandle_Priv: \n" + " b MPU_xTaskGetIdleTaskHandleImpl \n" + " MPU_xTaskGetIdleTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + + void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSuspendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSuspend_Unpriv \n" + " MPU_vTaskSuspend_Priv: \n" + " b MPU_vTaskSuspendImpl \n" + " MPU_vTaskSuspend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + + void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskResumeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskResume_Unpriv \n" + " MPU_vTaskResume_Priv: \n" + " b MPU_vTaskResumeImpl \n" + " MPU_vTaskResume_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + TickType_t MPU_xTaskGetTickCount( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetTickCountImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetTickCount_Unpriv \n" + " MPU_xTaskGetTickCount_Priv: \n" + " b MPU_xTaskGetTickCountImpl \n" + " MPU_xTaskGetTickCount_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetNumberOfTasksImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetNumberOfTasks_Unpriv \n" + " MPU_uxTaskGetNumberOfTasks_Priv: \n" + " b MPU_uxTaskGetNumberOfTasksImpl \n" + " MPU_uxTaskGetNumberOfTasks_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetRunTimeCounterImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetRunTimeCounter_Unpriv \n" + " MPU_ulTaskGetRunTimeCounter_Priv: \n" + " b MPU_ulTaskGetRunTimeCounterImpl \n" + " MPU_ulTaskGetRunTimeCounter_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetRunTimePercentImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetRunTimePercent_Unpriv \n" + " MPU_ulTaskGetRunTimePercent_Priv: \n" + " b MPU_ulTaskGetRunTimePercentImpl \n" + " MPU_ulTaskGetRunTimePercent_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetIdleRunTimePercentImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv \n" + " MPU_ulTaskGetIdleRunTimePercent_Priv: \n" + " b MPU_ulTaskGetIdleRunTimePercentImpl \n" + " MPU_ulTaskGetIdleRunTimePercent_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetIdleRunTimeCounterImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv \n" + " MPU_ulTaskGetIdleRunTimeCounter_Priv: \n" + " b MPU_ulTaskGetIdleRunTimeCounterImpl \n" + " MPU_ulTaskGetIdleRunTimeCounter_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetApplicationTaskTagImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetApplicationTaskTag_Unpriv \n" + " MPU_vTaskSetApplicationTaskTag_Priv: \n" + " b MPU_vTaskSetApplicationTaskTagImpl \n" + " MPU_vTaskSetApplicationTaskTag_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory" + ); + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetApplicationTaskTagImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetApplicationTaskTag_Unpriv \n" + " MPU_xTaskGetApplicationTaskTag_Priv: \n" + " b MPU_xTaskGetApplicationTaskTagImpl \n" + " MPU_xTaskGetApplicationTaskTag_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory" + ); + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetThreadLocalStoragePointerImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv \n" + " MPU_vTaskSetThreadLocalStoragePointer_Priv: \n" + " b MPU_vTaskSetThreadLocalStoragePointerImpl \n" + " MPU_vTaskSetThreadLocalStoragePointer_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory" + ); + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv \n" + " MPU_pvTaskGetThreadLocalStoragePointer_Priv: \n" + " b MPU_pvTaskGetThreadLocalStoragePointerImpl \n" + " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory" + ); + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetSystemStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetSystemState_Unpriv \n" + " MPU_uxTaskGetSystemState_Priv: \n" + " b MPU_uxTaskGetSystemStateImpl \n" + " MPU_uxTaskGetSystemState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory" + ); + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) + + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetStackHighWaterMarkImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetStackHighWaterMark_Unpriv \n" + " MPU_uxTaskGetStackHighWaterMark_Priv: \n" + " b MPU_uxTaskGetStackHighWaterMarkImpl \n" + " MPU_uxTaskGetStackHighWaterMark_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetStackHighWaterMark2Impl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv \n" + " MPU_uxTaskGetStackHighWaterMark2_Priv: \n" + " b MPU_uxTaskGetStackHighWaterMark2Impl \n" + " MPU_uxTaskGetStackHighWaterMark2_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) + + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetCurrentTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetCurrentTaskHandle_Unpriv \n" + " MPU_xTaskGetCurrentTaskHandle_Priv: \n" + " b MPU_xTaskGetCurrentTaskHandleImpl \n" + " MPU_xTaskGetCurrentTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory" + ); + } + + #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetSchedulerState == 1 ) + + BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetSchedulerStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetSchedulerState_Unpriv \n" + " MPU_xTaskGetSchedulerState_Priv: \n" + " b MPU_xTaskGetSchedulerStateImpl \n" + " MPU_xTaskGetSchedulerState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */ +/*-----------------------------------------------------------*/ + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetTimeOutStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetTimeOutState_Unpriv \n" + " MPU_vTaskSetTimeOutState_Priv: \n" + " b MPU_vTaskSetTimeOutStateImpl \n" + " MPU_vTaskSetTimeOutState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskCheckForTimeOutImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskCheckForTimeOut_Unpriv \n" + " MPU_xTaskCheckForTimeOut_Priv: \n" + " b MPU_xTaskCheckForTimeOutImpl \n" + " MPU_xTaskCheckForTimeOut_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotify_Unpriv \n" + " MPU_xTaskGenericNotify_Priv: \n" + " b MPU_xTaskGenericNotifyImpl \n" + " MPU_xTaskGenericNotify_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyWaitImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotifyWait_Unpriv \n" + " MPU_xTaskGenericNotifyWait_Priv: \n" + " b MPU_xTaskGenericNotifyWaitImpl \n" + " MPU_xTaskGenericNotifyWait_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGenericNotifyTakeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGenericNotifyTake_Unpriv \n" + " MPU_ulTaskGenericNotifyTake_Priv: \n" + " b MPU_ulTaskGenericNotifyTakeImpl \n" + " MPU_ulTaskGenericNotifyTake_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyStateClearImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotifyStateClear_Unpriv \n" + " MPU_xTaskGenericNotifyStateClear_Priv: \n" + " b MPU_xTaskGenericNotifyStateClearImpl \n" + " MPU_xTaskGenericNotifyStateClear_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGenericNotifyValueClearImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGenericNotifyValueClear_Unpriv \n" + " MPU_ulTaskGenericNotifyValueClear_Priv: \n" + " b MPU_ulTaskGenericNotifyValueClearImpl \n" + " MPU_ulTaskGenericNotifyValueClear_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGenericSendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGenericSend_Unpriv \n" + " MPU_xQueueGenericSend_Priv: \n" + " b MPU_xQueueGenericSendImpl \n" + " MPU_xQueueGenericSend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxQueueMessagesWaitingImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxQueueMessagesWaiting_Unpriv \n" + " MPU_uxQueueMessagesWaiting_Priv: \n" + " b MPU_uxQueueMessagesWaitingImpl \n" + " MPU_uxQueueMessagesWaiting_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxQueueSpacesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxQueueSpacesAvailable_Unpriv \n" + " MPU_uxQueueSpacesAvailable_Priv: \n" + " b MPU_uxQueueSpacesAvailableImpl \n" + " MPU_uxQueueSpacesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueReceiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueReceive_Unpriv \n" + " MPU_xQueueReceive_Priv: \n" + " b MPU_xQueueReceiveImpl \n" + " MPU_xQueueReceive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueuePeekImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueuePeek_Unpriv \n" + " MPU_xQueuePeek_Priv: \n" + " b MPU_xQueuePeekImpl \n" + " MPU_xQueuePeek_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueSemaphoreTakeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueSemaphoreTake_Unpriv \n" + " MPU_xQueueSemaphoreTake_Priv: \n" + " b MPU_xQueueSemaphoreTakeImpl \n" + " MPU_xQueueSemaphoreTake_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) + + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGetMutexHolderImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGetMutexHolder_Unpriv \n" + " MPU_xQueueGetMutexHolder_Priv: \n" + " b MPU_xQueueGetMutexHolderImpl \n" + " MPU_xQueueGetMutexHolder_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory" + ); + } + + #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueTakeMutexRecursiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueTakeMutexRecursive_Unpriv \n" + " MPU_xQueueTakeMutexRecursive_Priv: \n" + " b MPU_xQueueTakeMutexRecursiveImpl \n" + " MPU_xQueueTakeMutexRecursive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory" + ); + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGiveMutexRecursiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGiveMutexRecursive_Unpriv \n" + " MPU_xQueueGiveMutexRecursive_Priv: \n" + " b MPU_xQueueGiveMutexRecursiveImpl \n" + " MPU_xQueueGiveMutexRecursive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory" + ); + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueSelectFromSetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueSelectFromSet_Unpriv \n" + " MPU_xQueueSelectFromSet_Priv: \n" + " b MPU_xQueueSelectFromSetImpl \n" + " MPU_xQueueSelectFromSet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory" + ); + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueAddToSetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueAddToSet_Unpriv \n" + " MPU_xQueueAddToSet_Priv: \n" + " b MPU_xQueueAddToSetImpl \n" + " MPU_xQueueAddToSet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory" + ); + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vQueueAddToRegistryImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vQueueAddToRegistry_Unpriv \n" + " MPU_vQueueAddToRegistry_Priv: \n" + " b MPU_vQueueAddToRegistryImpl \n" + " MPU_vQueueAddToRegistry_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vQueueUnregisterQueueImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vQueueUnregisterQueue_Unpriv \n" + " MPU_vQueueUnregisterQueue_Priv: \n" + " b MPU_vQueueUnregisterQueueImpl \n" + " MPU_vQueueUnregisterQueue_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pcQueueGetNameImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pcQueueGetName_Unpriv \n" + " MPU_pcQueueGetName_Priv: \n" + " b MPU_pcQueueGetNameImpl \n" + " MPU_pcQueueGetName_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pvTimerGetTimerIDImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pvTimerGetTimerID_Unpriv \n" + " MPU_pvTimerGetTimerID_Priv: \n" + " b MPU_pvTimerGetTimerIDImpl \n" + " MPU_pvTimerGetTimerID_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTimerSetTimerIDImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTimerSetTimerID_Unpriv \n" + " MPU_vTimerSetTimerID_Priv: \n" + " b MPU_vTimerSetTimerIDImpl \n" + " MPU_vTimerSetTimerID_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerIsTimerActiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerIsTimerActive_Unpriv \n" + " MPU_xTimerIsTimerActive_Priv: \n" + " b MPU_xTimerIsTimerActiveImpl \n" + " MPU_xTimerIsTimerActive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv \n" + " MPU_xTimerGetTimerDaemonTaskHandle_Priv: \n" + " b MPU_xTimerGetTimerDaemonTaskHandleImpl \n" + " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGenericCommandFromTaskImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGenericCommandFromTask_Unpriv \n" + " MPU_xTimerGenericCommandFromTask_Priv: \n" + " b MPU_xTimerGenericCommandFromTaskImpl \n" + " MPU_xTimerGenericCommandFromTask_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pcTimerGetNameImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pcTimerGetName_Unpriv \n" + " MPU_pcTimerGetName_Priv: \n" + " b MPU_pcTimerGetNameImpl \n" + " MPU_pcTimerGetName_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTimerSetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTimerSetReloadMode_Unpriv \n" + " MPU_vTimerSetReloadMode_Priv: \n" + " b MPU_vTimerSetReloadModeImpl \n" + " MPU_vTimerSetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetReloadMode_Unpriv \n" + " MPU_xTimerGetReloadMode_Priv: \n" + " b MPU_xTimerGetReloadModeImpl \n" + " MPU_xTimerGetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTimerGetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTimerGetReloadMode_Unpriv \n" + " MPU_uxTimerGetReloadMode_Priv: \n" + " b MPU_uxTimerGetReloadModeImpl \n" + " MPU_uxTimerGetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetPeriodImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetPeriod_Unpriv \n" + " MPU_xTimerGetPeriod_Priv: \n" + " b MPU_xTimerGetPeriodImpl \n" + " MPU_xTimerGetPeriod_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetExpiryTimeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetExpiryTime_Unpriv \n" + " MPU_xTimerGetExpiryTime_Priv: \n" + " b MPU_xTimerGetExpiryTimeImpl \n" + " MPU_xTimerGetExpiryTime_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupWaitBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupWaitBits_Unpriv \n" + " MPU_xEventGroupWaitBits_Priv: \n" + " b MPU_xEventGroupWaitBitsImpl \n" + " MPU_xEventGroupWaitBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupClearBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupClearBits_Unpriv \n" + " MPU_xEventGroupClearBits_Priv: \n" + " b MPU_xEventGroupClearBitsImpl \n" + " MPU_xEventGroupClearBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupSetBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupSetBits_Unpriv \n" + " MPU_xEventGroupSetBits_Priv: \n" + " b MPU_xEventGroupSetBitsImpl \n" + " MPU_xEventGroupSetBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ + +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupSyncImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupSync_Unpriv \n" + " MPU_xEventGroupSync_Priv: \n" + " b MPU_xEventGroupSyncImpl \n" + " MPU_xEventGroupSync_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxEventGroupGetNumberImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxEventGroupGetNumber_Unpriv \n" + " MPU_uxEventGroupGetNumber_Priv: \n" + " b MPU_uxEventGroupGetNumberImpl \n" + " MPU_uxEventGroupGetNumber_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory" + ); + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vEventGroupSetNumberImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vEventGroupSetNumber_Unpriv \n" + " MPU_vEventGroupSetNumber_Priv: \n" + " b MPU_vEventGroupSetNumberImpl \n" + " MPU_vEventGroupSetNumber_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory" + ); + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferSend_Unpriv \n" + " MPU_xStreamBufferSend_Priv: \n" + " b MPU_xStreamBufferSendImpl \n" + " MPU_xStreamBufferSend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferReceiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferReceive_Unpriv \n" + " MPU_xStreamBufferReceive_Priv: \n" + " b MPU_xStreamBufferReceiveImpl \n" + " MPU_xStreamBufferReceive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferIsFullImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferIsFull_Unpriv \n" + " MPU_xStreamBufferIsFull_Priv: \n" + " b MPU_xStreamBufferIsFullImpl \n" + " MPU_xStreamBufferIsFull_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferIsEmptyImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferIsEmpty_Unpriv \n" + " MPU_xStreamBufferIsEmpty_Priv: \n" + " b MPU_xStreamBufferIsEmptyImpl \n" + " MPU_xStreamBufferIsEmpty_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSpacesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferSpacesAvailable_Unpriv \n" + " MPU_xStreamBufferSpacesAvailable_Priv: \n" + " b MPU_xStreamBufferSpacesAvailableImpl \n" + " MPU_xStreamBufferSpacesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferBytesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferBytesAvailable_Unpriv \n" + " MPU_xStreamBufferBytesAvailable_Priv: \n" + " b MPU_xStreamBufferBytesAvailableImpl \n" + " MPU_xStreamBufferBytesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSetTriggerLevelImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferSetTriggerLevel_Unpriv \n" + " MPU_xStreamBufferSetTriggerLevel_Priv: \n" + " b MPU_xStreamBufferSetTriggerLevelImpl \n" + " MPU_xStreamBufferSetTriggerLevel_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferNextMessageLengthBytesImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv \n" + " MPU_xStreamBufferNextMessageLengthBytes_Priv: \n" + " b MPU_xStreamBufferNextMessageLengthBytesImpl \n" + " MPU_xStreamBufferNextMessageLengthBytes_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ diff --git a/portable/GCC/ARM_CM33/non_secure/port.c b/portable/GCC/ARM_CM33/non_secure/port.c new file mode 100644 index 000000000..76d2b2445 --- /dev/null +++ b/portable/GCC/ARM_CM33/non_secure/port.c @@ -0,0 +1,2280 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024-2025 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU includes. */ +#include "mpu_wrappers.h" +#include "mpu_syscall_numbers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration settings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to check the validity of an interrupt priority. + */ +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) ) +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used during system call enter and exit. + */ +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Offsets in the stack to the parameters when inside the SVC handler. + */ +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +#if ( portARMV8M_MINOR_VERSION >= 1 ) + + /* Enable Privileged eXecute Never MPU attribute for the selected memory + * region. */ + #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL ) +#endif /* portARMV8M_MINOR_VERSION >= 1 */ + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Extract first address of the MPU region as encoded in the + * RBAR (Region Base Address Register) value. */ +#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \ + ( ( rbar ) & portMPU_RBAR_ADDRESS_MASK ) + +/* Extract last address of the MPU region as encoded in the + * RLAR (Region Limit Address Register) value. */ +#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \ + ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK ) + +/* Does addr lies within [start, end] address range? */ +#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \ + ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) ) + +/* Is the access request satisfied by the available permissions? */ +#define portIS_AUTHORIZED( accessRequest, permissions ) \ + ( ( ( permissions ) & ( accessRequest ) ) == accessRequest ) + +/* Max value that fits in a uint32_t type. */ +#define portUINT32_MAX ( ~( ( uint32_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. + */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 + +/** + * @brief Constants required to check and configure PACBTI security feature implementation. + */ +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) ) + + #define portCONTROL_UPAC_EN ( 1UL << 7UL ) + #define portCONTROL_PAC_EN ( 1UL << 6UL ) + #define portCONTROL_UBTI_EN ( 1UL << 5UL ) + #define portCONTROL_BTI_EN ( 1UL << 4UL ) + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Extract MPU region's access permissions from the Region Base Address + * Register (RBAR) value. + * + * @param ulRBARValue RBAR value for the MPU region. + * + * @return uint32_t Access permissions. + */ + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + + /** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + /** + * @brief Configures PACBTI features. + * + * This function configures the Pointer Authentication, and Branch Target + * Identification security features as per the user configuration. It returns + * the value of the special purpose CONTROL register accordingly, and optionally + * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M + * architecture based) target supports PACBTI security feature. + * + * @param xWriteControlRegister Used to control whether the special purpose + * CONTROL register should be updated or not. + * + * @return CONTROL register value according to the configured PACBTI option. + */ + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the system call stack so that upon returning from + * SVC, the system call stack is used. + * + * @param pulTaskStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + * @param ucSystemCallNumber The system call number of the system call. + */ + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Raise SVC for exiting from a system call. + */ + void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief This variable is set to pdTRUE when the scheduler is started. + */ + PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + + /** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +/** + * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + /** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + + /** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + + /** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the cpsid instruction + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessPermissions = 0; + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_ONLY ) + { + ulAccessPermissions = tskMPU_READ_PERMISSION; + } + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_WRITE ) + { + ulAccessPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION ); + } + + return ulAccessPermissions; + } + +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } + +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ portOFFSET_TO_PC ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ]; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulSystemCallStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the system call section (i.e. application is + * not raising SVC directly). + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as + * it is non-NULL only during the execution of a system call (i.e. + * between system call enter and exit). + * 3. System call is not for a kernel API disabled by the configuration + * in FreeRTOSConfig.h. + * 4. We do not need to check that ucSystemCallNumber is within range + * because the assembly SVC handler checks that before calling + * this function. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) && + ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) ) + { + pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the system call stack for the stack frame. */ + pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulSystemCallStack[ i ] = pulTaskStack[ i ]; + } + + /* Store the value of the Link Register before the SVC was raised. + * It contains the address of the caller of the System Call entry + * point (i.e. the caller of the MPU_). We need to restore it + * when we exit from the system call. */ + pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; + + /* Store the value of the PSPLIM register before the SVC was raised. + * We need to restore it when we exit from the system call. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* Use the pulSystemCallStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif + + /* Start executing the system call upon returning from this handler. */ + pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; + + /* Raise a request to exit from the system call upon finishing the + * system call. */ + pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; + + /* Remember the location where we should copy the stack frame when we exit from + * the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize; + + /* Record if the hardware used padding to force the stack pointer + * to be double word aligned. */ + if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK ) + { + pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG; + } + else + { + pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG ); + } + + /* We ensure in pxPortInitialiseStack that the system call stack is + * double word aligned and therefore, there is no need of padding. + * Clear the bit[9] of stacked xPSR. */ + pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + + /* Raise the privilege for the duration of the system call. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " bics r0, r1 \n" /* Clear nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */ + { + __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulTaskStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the privileged code (i.e. application is not + * raising SVC directly). This SVC is only raised from + * vRequestSystemCallExit which is in the privileged code section. + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL - + * this means that we previously entered a system call and the + * application is not attempting to exit without entering a system + * call. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) ) + { + pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the task stack for the stack frame. */ + pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulTaskStack[ i ] = pulSystemCallStack[ i ]; + } + + /* Use the pulTaskStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) ); + + /* Return to the caller of the System Call entry point (i.e. the + * caller of the MPU_). */ + pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + /* Ensure that LR has a valid value.*/ + pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + + /* Restore the PSPLIM register to what it was at the time of + * system call entry. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* If the hardware used padding to force the stack pointer + * to be double word aligned, set the stacked xPSR bit[9], + * otherwise clear it. */ + if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG ) + { + pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK; + } + else + { + pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + } + + /* This is not NULL only for the duration of the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; + + /* Drop the privilege before returning to the thread mode. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " orrs r0, r1 \n" /* Set nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xTaskIsPrivileged = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xTaskIsPrivileged = pdTRUE; + } + + return xTaskIsPrivileged; + } + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged, + xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulIndex = 0; + uint32_t ulControl = 0x0; + + xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ + ulIndex++; + + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + ulIndex++; + + #if ( configENABLE_TRUSTZONE == 1 ) + { + xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */ + ulIndex++; + } + #endif /* configENABLE_TRUSTZONE */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + ulIndex++; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Check PACBTI security feature configuration before pushing the + * CONTROL register's value on task's TCB. */ + ulControl = prvConfigurePACBTI( pdFALSE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + if( xRunPrivileged == pdTRUE ) + { + xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + else + { + xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG ); + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ + ulIndex++; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + { + /* Ensure that the system call stack is double word aligned. */ + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) + + ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + /* This is not NULL only for the duration of a system call. */ + xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL; + } + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ]; + ulIndex++; + } + } + #endif /* configENABLE_PAC */ + + return &( xMPUSettings->ulContext[ ulIndex ] ); + } + +#else /* configENABLE_MPU */ + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ + { + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + pxTopOfStack--; + *pxTopOfStack = ulTaskPacKey[ i ]; + } + } + #endif /* configENABLE_PAC */ + + return pxTopOfStack; + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Set the CONTROL register value based on PACBTI security feature + * configuration before starting the first task. */ + ( void ) prvConfigurePACBTI( pdTRUE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + { + xSchedulerRunning = pdTRUE; + } + #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + configSTACK_DEPTH_TYPE uxStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( uxStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* PXN. */ + #if ( portARMV8M_MINOR_VERSION >= 1 ) + { + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ); + } + } + #endif /* portARMV8M_MINOR_VERSION >= 1 */ + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, + uint32_t ulBufferLength, + uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */ + + { + uint32_t i, ulBufferStartAddress, ulBufferEndAddress; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE ) + { + ulBufferStartAddress = ( uint32_t ) pvBuffer; + ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL ); + + for( i = 0; i < portTOTAL_NUM_REGIONS; i++ ) + { + /* Is the MPU region enabled? */ + if( ( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR & portMPU_RLAR_REGION_ENABLE ) == portMPU_RLAR_REGION_ENABLE ) + { + if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_AUTHORIZED( ulAccessRequested, + prvGetRegionAccessPermissions( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ) ) ) + { + xAccessGranted = pdTRUE; + break; + } + } + } + } + } + + return xAccessGranted; + } + +#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings; + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else + { + xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 ) + { + xAccessGranted = pdTRUE; + } + } + } + + return xAccessGranted; + } + + #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + ( void ) lInternalIndexOfKernelObject; + + /* If Access Control List feature is not used, all the tasks have + * access to all the kernel objects. */ + return pdTRUE; + } + + #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + { + uint32_t ulControl = 0x0; + + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); + + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; + + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM33/non_secure/portasm.c b/portable/GCC/ARM_CM33/non_secure/portasm.c new file mode 100644 index 000000000..0ebbe48a4 --- /dev/null +++ b/portable/GCC/ARM_CM33/non_secure/portasm.c @@ -0,0 +1,621 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION + * is defined correctly and privileged functions are placed in correct sections. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Portasm includes. */ +#include "portasm.h" + +/* System call numbers includes. */ +#include "mpu_syscall_numbers.h" + +/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the + * header files. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#if ( configENABLE_MPU == 1 ) + + void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " program_mpu_first_task: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r3] \n" /* r0 = pxCurrentTCB. */ + " \n" + " dmb \n" /* Complete outstanding transfers before disabling MPU. */ + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + " str r2, [r1] \n" /* Disable MPU. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */ + " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r1, [r2] \n" /* Program MAIR0. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " \n" + " movs r3, #4 \n" /* r3 = 4. */ + " str r3, [r1] \n" /* Program RNR = 4. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + " \n" + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " orr r2, #1 \n" /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */ + " str r2, [r1] \n" /* Enable MPU. */ + " dsb \n" /* Force memory writes before continuing. */ + " \n" + " restore_context_first_task: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* r1 = pxCurrentTCB.*/ + " ldr r2, [r1] \n" /* r2 = Location of saved context in TCB. */ + " \n" + " restore_special_regs_first_task: \n" + #if ( configENABLE_PAC == 1 ) + " ldmdb r2!, {r3-r6} \n" /* Read task's dedicated PAC key from the task's context. */ + " msr PAC_KEY_P_0, r3 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_1, r4 \n" + " msr PAC_KEY_P_2, r5 \n" + " msr PAC_KEY_P_3, r6 \n" + " clrm {r3-r6} \n" /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + " ldmdb r2!, {r0, r3-r5, lr} \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */ + " msr psp, r3 \n" + " msr psplim, r4 \n" + " msr control, r5 \n" + " ldr r4, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " str r0, [r4] \n" /* Restore xSecureContext. */ + " \n" + " restore_general_regs_first_task: \n" + " ldmdb r2!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */ + " stmia r3!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */ + " ldmdb r2!, {r4-r11} \n" /* r4-r11 restored. */ + " \n" + " restore_context_done_first_task: \n" + " str r2, [r1] \n" /* Save the location where the context should be saved next as the first member of TCB. */ + " mov r0, #0 \n" + " msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */ + " bx lr \n" + ); + } + +#else /* configENABLE_MPU */ + + void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r3, [r2] \n" /* Read pxCurrentTCB. */ + " ldr r0, [r3] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + " \n" + #if ( configENABLE_PAC == 1 ) + " ldmia r0!, {r1-r4} \n" /* Read task's dedicated PAC key from stack. */ + " msr PAC_KEY_P_3, r1 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_2, r2 \n" + " msr PAC_KEY_P_1, r3 \n" + " msr PAC_KEY_P_0, r4 \n" + " clrm {r1-r4} \n" /* Clear r1-r4. */ + #endif /* configENABLE_PAC */ + " \n" + " ldm r0!, {r1-r3} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */ + " ldr r4, =xSecureContext \n" + " str r1, [r4] \n" /* Set xSecureContext to this task's value for the same. */ + " msr psplim, r2 \n" /* Set this task's PSPLIM value. */ + " mrs r1, control \n" /* Obtain current control register value. */ + " orrs r1, r1, #2 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */ + " msr control, r1 \n" /* Write back the new control register value. */ + " adds r0, #32 \n" /* Discard everything up to r0. */ + " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */ + " isb \n" + " mov r0, #0 \n" + " msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */ + " bx r3 \n" /* Finally, branch to EXC_RETURN. */ + ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* r0 = CONTROL. */ + " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + " ite ne \n" + " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + " bx lr \n" /* Return. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* Read the CONTROL register. */ + " bic r0, #1 \n" /* Clear the bit 0. */ + " msr control, r0 \n" /* Write back the new CONTROL value. */ + " bx lr \n" /* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vResetPrivilege( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* r0 = CONTROL. */ + " orr r0, #1 \n" /* r0 = r0 | 1. */ + " msr control, r0 \n" /* CONTROL = r0. */ + " bx lr \n" /* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r0, =0xe000ed08 \n" /* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */ + " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */ + " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */ + " cpsie i \n" /* Globally enable interrupts. */ + " cpsie f \n" + " dsb \n" + " isb \n" + " svc %0 \n" /* System call to start the first task. */ + " nop \n" + ::"i" ( portSVC_START_SCHEDULER ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, basepri \n" /* r0 = basepri. Return original basepri value. */ + " mov r1, %0 \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r1 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bx lr \n" /* Return. */ + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " msr basepri, r0 \n" /* basepri = ulMask. */ + " dsb \n" + " isb \n" + " bx lr \n" /* Return. */ + ::: "memory" + ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern SecureContext_SaveContext \n" + " .extern SecureContext_LoadContext \n" + " \n" + " ldr r3, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " ldr r0, [r3] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */ + " ldr r2, [r1] \n" /* r2 = Location in TCB where the context should be saved. */ + " \n" + " cbz r0, save_ns_context \n" /* No secure context to save. */ + " save_s_context: \n" + " push {r0-r2, lr} \n" + " bl SecureContext_SaveContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r0-r2, lr} \n" + " \n" + " save_ns_context: \n" + " mov r3, lr \n" /* r3 = LR (EXC_RETURN). */ + " lsls r3, r3, #25 \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bmi save_special_regs \n" /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + " \n" + " save_general_regs: \n" + " mrs r3, psp \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " add r3, r3, #0x20 \n" /* Move r3 to location where s0 is saved. */ + " tst lr, #0x10 \n" + " ittt eq \n" + " vstmiaeq r2!, {s16-s31} \n" /* Store s16-s31. */ + " vldmiaeq r3, {s0-s16} \n" /* Copy hardware saved FP context into s0-s16. */ + " vstmiaeq r2!, {s0-s16} \n" /* Store hardware saved FP context. */ + " sub r3, r3, #0x20 \n" /* Set r3 back to the location of hardware saved context. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " stmia r2!, {r4-r11} \n" /* Store r4-r11. */ + " ldmia r3, {r4-r11} \n" /* Copy the hardware saved context into r4-r11. */ + " stmia r2!, {r4-r11} \n" /* Store the hardware saved context. */ + " \n" + " save_special_regs: \n" + " mrs r3, psp \n" /* r3 = PSP. */ + " mrs r4, psplim \n" /* r4 = PSPLIM. */ + " mrs r5, control \n" /* r5 = CONTROL. */ + " stmia r2!, {r0, r3-r5, lr} \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ + #if ( configENABLE_PAC == 1 ) + " mrs r3, PAC_KEY_P_0 \n" /* Read task's dedicated PAC key from the PAC key registers. */ + " mrs r4, PAC_KEY_P_1 \n" + " mrs r5, PAC_KEY_P_2 \n" + " mrs r6, PAC_KEY_P_3 \n" + " stmia r2!, {r3-r6} \n" /* Store the task's dedicated PAC key on the task's context. */ + " clrm {r3-r6} \n" /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + " str r2, [r1] \n" /* Save the location from where the context should be restored as the first member of TCB. */ + " \n" + " select_next_task: \n" + " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bl vTaskSwitchContext \n" + " mov r0, #0 \n" /* r0 = 0. */ + " msr basepri, r0 \n" /* Enable interrupts. */ + " \n" + " program_mpu: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r3] \n" /* r0 = pxCurrentTCB.*/ + " \n" + " dmb \n" /* Complete outstanding transfers before disabling MPU. */ + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + " str r2, [r1] \n" /* Disable MPU. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */ + " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r1, [r2] \n" /* Program MAIR0. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " \n" + " movs r3, #4 \n" /* r3 = 4. */ + " str r3, [r1] \n" /* Program RNR = 4. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + " \n" + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " orr r2, #1 \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */ + " str r2, [r1] \n" /* Enable MPU. */ + " dsb \n" /* Force memory writes before continuing. */ + " \n" + " restore_context: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* r1 = pxCurrentTCB.*/ + " ldr r2, [r1] \n" /* r2 = Location of saved context in TCB. */ + " \n" + " restore_special_regs: \n" + #if ( configENABLE_PAC == 1 ) + " ldmdb r2!, {r3-r6} \n" /* Read task's dedicated PAC key from the task's context. */ + " msr PAC_KEY_P_0, r3 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_1, r4 \n" + " msr PAC_KEY_P_2, r5 \n" + " msr PAC_KEY_P_3, r6 \n" + " clrm {r3-r6} \n" /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + " ldmdb r2!, {r0, r3-r5, lr} \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */ + " msr psp, r3 \n" + " msr psplim, r4 \n" + " msr control, r5 \n" + " ldr r4, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " str r0, [r4] \n" /* Restore xSecureContext. */ + " cbz r0, restore_ns_context \n" /* No secure context to restore. */ + " \n" + " restore_s_context: \n" + " push {r1-r3, lr} \n" + " bl SecureContext_LoadContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r1-r3, lr} \n" + " \n" + " restore_ns_context: \n" + " mov r0, lr \n" /* r0 = LR (EXC_RETURN). */ + " lsls r0, r0, #25 \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bmi restore_context_done \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + " \n" + " restore_general_regs: \n" + " ldmdb r2!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */ + " stmia r3!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */ + " ldmdb r2!, {r4-r11} \n" /* r4-r11 restored. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" + " ittt eq \n" + " vldmdbeq r2!, {s0-s16} \n" /* s0-s16 contain hardware saved FP context. */ + " vstmiaeq r3!, {s0-s16} \n" /* Copy hardware saved FP context on the task stack. */ + " vldmdbeq r2!, {s16-s31} \n" /* Restore s16-s31. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + " restore_context_done: \n" + " str r2, [r1] \n" /* Save the location where the context should be saved next as the first member of TCB. */ + " bx lr \n" + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); + } + +#else /* configENABLE_MPU */ + + void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern SecureContext_SaveContext \n" + " .extern SecureContext_LoadContext \n" + " \n" + " ldr r3, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " ldr r0, [r3] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */ + " mrs r2, psp \n" /* Read PSP in r2. */ + " \n" + " cbz r0, save_ns_context \n" /* No secure context to save. */ + " save_s_context: \n" + " push {r0-r2, lr} \n" + " bl SecureContext_SaveContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r0-r2, lr} \n" + " \n" + " save_ns_context: \n" + " mov r3, lr \n" /* r3 = LR (EXC_RETURN). */ + " lsls r3, r3, #25 \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bmi save_special_regs \n" /* If r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used. */ + " \n" + " save_general_regs: \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vstmdbeq r2!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " stmdb r2!, {r4-r11} \n" /* Store the registers that are not saved automatically. */ + " \n" + " save_special_regs: \n" + " mrs r3, psplim \n" /* r3 = PSPLIM. */ + " stmdb r2!, {r0, r3, lr} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */ + #if ( configENABLE_PAC == 1 ) + " mrs r3, PAC_KEY_P_3 \n" /* Read task's dedicated PAC key from the PAC key registers. */ + " mrs r4, PAC_KEY_P_2 \n" + " mrs r5, PAC_KEY_P_1 \n" + " mrs r6, PAC_KEY_P_0 \n" + " stmdb r2!, {r3-r6} \n" /* Store the task's dedicated PAC key on the stack. */ + " clrm {r3-r6} \n" /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + " \n" + " str r2, [r1] \n" /* Save the new top of stack in TCB. */ + " \n" + " select_next_task: \n" + " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bl vTaskSwitchContext \n" + " mov r0, #0 \n" /* r0 = 0. */ + " msr basepri, r0 \n" /* Enable interrupts. */ + " \n" + " restore_context: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* Read pxCurrentTCB. */ + " ldr r2, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */ + " \n" + " restore_special_regs: \n" + #if ( configENABLE_PAC == 1 ) + " ldmia r2!, {r3-r6} \n" /* Read task's dedicated PAC key from stack. */ + " msr PAC_KEY_P_3, r3 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_2, r4 \n" + " msr PAC_KEY_P_1, r5 \n" + " msr PAC_KEY_P_0, r6 \n" + " clrm {r3-r6} \n" /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + " ldmia r2!, {r0, r3, lr} \n" /* Read from stack - r0 = xSecureContext, r3 = PSPLIM and LR restored. */ + " msr psplim, r3 \n" /* Restore the PSPLIM register value for the task. */ + " ldr r3, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " str r0, [r3] \n" /* Restore the task's xSecureContext. */ + " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */ + " \n" + " restore_s_context: \n" + " push {r1-r3, lr} \n" + " bl SecureContext_LoadContext \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r1-r3, lr} \n" + " \n" + " restore_ns_context: \n" + " mov r0, lr \n" /* r0 = LR (EXC_RETURN). */ + " lsls r0, r0, #25 \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bmi restore_context_done \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + " \n" + " restore_general_regs: \n" + " ldmia r2!, {r4-r11} \n" /* Restore the registers that are not automatically restored. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vldmiaeq r2!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + " restore_context_done: \n" + " msr psp, r2 \n" /* Remember the new top of stack for the task. */ + " bx lr \n" + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + ".syntax unified \n" + ".extern vPortSVCHandler_C \n" + ".extern vSystemCallEnter \n" + ".extern vSystemCallExit \n" + " \n" + "tst lr, #4 \n" + "ite eq \n" + "mrseq r0, msp \n" + "mrsne r0, psp \n" + " \n" + "ldr r1, [r0, #24] \n" + "ldrb r2, [r1, #-2] \n" + "cmp r2, %0 \n" + "blt syscall_enter \n" + "cmp r2, %1 \n" + "beq syscall_exit \n" + "b vPortSVCHandler_C \n" + " \n" + "syscall_enter: \n" + " mov r1, lr \n" + " b vSystemCallEnter \n" + " \n" + "syscall_exit: \n" + " mov r1, lr \n" + " b vSystemCallExit \n" + " \n" + : /* No outputs. */ + : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT ) + : "r0", "r1", "r2", "memory" + ); + } + +#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " tst lr, #4 \n" + " ite eq \n" + " mrseq r0, msp \n" + " mrsne r0, psp \n" + " ldr r1, =vPortSVCHandler_C \n" + " bx r1 \n" + ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " svc %0 \n" /* Secure context is allocated in the supervisor call. */ + " bx lr \n" /* Return. */ + ::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, [r0] \n" /* The first item in the TCB is the top of the stack. */ + " ldr r1, [r2] \n" /* The first item on the stack is the task's xSecureContext. */ + " cmp r1, #0 \n" /* Raise svc if task's xSecureContext is not NULL. */ + " it ne \n" + " svcne %0 \n" /* Secure context is freed in the supervisor call. */ + " bx lr \n" /* Return. */ + ::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory" + ); +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM33/non_secure/portasm.h b/portable/GCC/ARM_CM33/non_secure/portasm.h new file mode 100644 index 000000000..b7021b024 --- /dev/null +++ b/portable/GCC/ARM_CM33/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kernel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/portable/GCC/ARM_CM33/non_secure/portmacro.h b/portable/GCC/ARM_CM33/non_secure/portmacro.h new file mode 100644 index 000000000..2d435ca0b --- /dev/null +++ b/portable/GCC/ARM_CM33/non_secure/portmacro.h @@ -0,0 +1,81 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M33" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portARMV8M_MINOR_VERSION 0 +#define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +#ifndef configENABLE_MVE + #define configENABLE_MVE 0 +#elif ( configENABLE_MVE != 0 ) + #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M33. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h new file mode 100644 index 000000000..f373bcad5 --- /dev/null +++ b/portable/GCC/ARM_CM33/non_secure/portmacrocommon.h @@ -0,0 +1,582 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACROCOMMON_H +#define PORTMACROCOMMON_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. +#endif /* configENABLE_FPU */ + +#ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. +#endif /* configENABLE_MPU */ + +#ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. +#endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() +#define portINLINE __inline +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif +#define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ +extern BaseType_t xPortIsInsideInterrupt( void ); + +extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + +extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; +extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + +extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; +extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + +#if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_PAC == 1 ) + + /** + * @brief Generates 128-bit task's random PAC key. + * + * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be + * filled with a 128-bit random number. + */ + void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); + +#endif /* configENABLE_PAC */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ +#if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) +#else + #define portPRIVILEGE_BIT ( 0x0UL ) +#endif /* configENABLE_MPU */ + +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ +#define portPRIVILEGED_FLASH_REGION ( 0UL ) +#define portUNPRIVILEGED_FLASH_REGION ( 1UL ) +#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) +#define portPRIVILEGED_RAM_REGION ( 3UL ) +#define portSTACK_REGION ( 4UL ) +#define portFIRST_CONFIGURABLE_REGION ( 5UL ) +#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) +#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) +#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ +#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ +#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ +#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ +#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ +#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ +#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ +#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) +#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) +#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + +#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) +#define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) +#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) +#define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + +#define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + #ifndef configSYSTEM_CALL_STACK_SIZE + #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. + #endif + + /** + * @brief System call stack. + */ + typedef struct SYSTEM_CALL_STACK_INFO + { + uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; + uint32_t * pulSystemCallStack; + uint32_t * pulSystemCallStackLimit; + uint32_t * pulTaskStack; + uint32_t ulLinkRegisterAtSystemCallEntry; + uint32_t ulStackLimitRegisterAtSystemCallEntry; + } xSYSTEM_CALL_STACK_INFO; + + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + /** + * @brief MPU settings as stored in the TCB. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><-----------><----> + * 16 17 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 71 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 17 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 55 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | | | PC, xPSR | EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><-----------><----> + * 16 17 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 70 + + #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + /* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 17 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 54 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+------------------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +----------+-----------------+------------------------------+------------+-----+ + * + * <---------><----------------><------------------------------><-----------><----> + * 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 38 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+----------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | PC, xPSR | EXC_RETURN | | | + * +----------+-----------------+----------------------+------------+-----+ + * + * <---------><----------------><----------------------><-----------><----> + * 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 37 + + #else /* #if( configENABLE_TRUSTZONE == 1 ) */ + + /* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) + + /* Size of an Access Control List (ACL) entry in bits. */ + #define portACL_ENTRY_SIZE_BITS ( 32U ) + + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + uint32_t ulContext[ MAX_CONTEXT_SIZE ]; + uint32_t ulTaskFlags; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo; + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ]; + #endif + #endif + } xMPU_SETTINGS; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Validate priority of ISRs that are allowed to call FreeRTOS + * system calls. + */ +#if ( configASSERT_DEFINED == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif +#endif + +/** + * @brief SVC numbers. + */ +#define portSVC_ALLOCATE_SECURE_CONTEXT 100 +#define portSVC_FREE_SECURE_CONTEXT 101 +#define portSVC_START_SCHEDULER 102 +#define portSVC_RAISE_PRIVILEGE 103 +#define portSVC_SYSTEM_CALL_EXIT 104 +#define portSVC_YIELD 105 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) +#endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() +#else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + extern BaseType_t xPortIsTaskPrivileged( void ); + +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACROCOMMON_H */ diff --git a/portable/GCC/ARM_CM33/secure/secure_context.c b/portable/GCC/ARM_CM33/secure/secure_context.c new file mode 100644 index 000000000..3aa335e63 --- /dev/null +++ b/portable/GCC/ARM_CM33/secure/secure_context.c @@ -0,0 +1,354 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Secure context includes. */ +#include "secure_context.h" + +/* Secure heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief CONTROL value for privileged tasks. + * + * Bit[0] - 0 --> Thread mode is privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_PRIVILEGED 0x02 + +/** + * @brief CONTROL value for un-privileged tasks. + * + * Bit[0] - 1 --> Thread mode is un-privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03 + +/** + * @brief Size of stack seal values in bytes. + */ +#define securecontextSTACK_SEAL_SIZE 8 + +/** + * @brief Stack seal value as recommended by ARM. + */ +#define securecontextSTACK_SEAL_VALUE 0xFEF5EDA5 + +/** + * @brief Maximum number of secure contexts. + */ +#ifndef secureconfigMAX_SECURE_CONTEXTS + #define secureconfigMAX_SECURE_CONTEXTS 8UL +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Pre-allocated array of secure contexts. + */ +SecureContext_t xSecureContexts[ secureconfigMAX_SECURE_CONTEXTS ]; +/*-----------------------------------------------------------*/ + +/** + * @brief Get a free secure context for a task from the secure context pool (xSecureContexts). + * + * This function ensures that only one secure context is allocated for a task. + * + * @param[in] pvTaskHandle The task handle for which the secure context is allocated. + * + * @return Index of a free secure context in the xSecureContexts array. + */ +static uint32_t ulGetSecureContext( void * pvTaskHandle ); + +/** + * @brief Return the secure context to the secure context pool (xSecureContexts). + * + * @param[in] ulSecureContextIndex Index of the context in the xSecureContexts array. + */ +static void vReturnSecureContext( uint32_t ulSecureContextIndex ); + +/* These are implemented in assembly. */ +extern void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ); +extern void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ); +/*-----------------------------------------------------------*/ + +static uint32_t ulGetSecureContext( void * pvTaskHandle ) +{ + /* Start with invalid index. */ + uint32_t i, ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + if( ( xSecureContexts[ i ].pucCurrentStackPointer == NULL ) && + ( xSecureContexts[ i ].pucStackLimit == NULL ) && + ( xSecureContexts[ i ].pucStackStart == NULL ) && + ( xSecureContexts[ i ].pvTaskHandle == NULL ) && + ( ulSecureContextIndex == secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = i; + } + else if( xSecureContexts[ i ].pvTaskHandle == pvTaskHandle ) + { + /* A task can only have one secure context. Do not allocate a second + * context for the same task. */ + ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + break; + } + } + + return ulSecureContextIndex; +} +/*-----------------------------------------------------------*/ + +static void vReturnSecureContext( uint32_t ulSecureContextIndex ) +{ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackStart = NULL; + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = NULL; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) +{ + uint32_t ulIPSR, i; + static uint32_t ulSecureContextsInitialized = 0; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ( ulIPSR != 0 ) && ( ulSecureContextsInitialized == 0 ) ) + { + /* Ensure to initialize secure contexts only once. */ + ulSecureContextsInitialized = 1; + + /* No stack for thread mode until a task's context is loaded. */ + secureportSET_PSPLIM( securecontextNO_STACK ); + secureportSET_PSP( securecontextNO_STACK ); + + /* Initialize all secure contexts. */ + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + xSecureContexts[ i ].pucCurrentStackPointer = NULL; + xSecureContexts[ i ].pucStackLimit = NULL; + xSecureContexts[ i ].pucStackStart = NULL; + xSecureContexts[ i ].pvTaskHandle = NULL; + } + + #if ( configENABLE_MPU == 1 ) + { + /* Configure thread mode to use PSP and to be unprivileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); + } + #else /* configENABLE_MPU */ + { + /* Configure thread mode to use PSP and to be privileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); + } + #endif /* configENABLE_MPU */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ) +#else /* configENABLE_MPU */ + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ) +#endif /* configENABLE_MPU */ +{ + uint8_t * pucStackMemory = NULL; + uint8_t * pucStackLimit; + uint32_t ulIPSR, ulSecureContextIndex; + SecureContextHandle_t xSecureContextHandle = securecontextINVALID_CONTEXT_ID; + + #if ( configENABLE_MPU == 1 ) + uint32_t * pulCurrentStackPointer = NULL; + #endif /* configENABLE_MPU */ + + /* Read the Interrupt Program Status Register (IPSR) and Process Stack Limit + * Register (PSPLIM) value. */ + secureportREAD_IPSR( ulIPSR ); + secureportREAD_PSPLIM( pucStackLimit ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. + * Also do nothing, if a secure context us already loaded. PSPLIM is set to + * securecontextNO_STACK when no secure context is loaded. */ + if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) ) + { + /* Obtain a free secure context. */ + ulSecureContextIndex = ulGetSecureContext( pvTaskHandle ); + + /* Were we able to get a free context? */ + if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS ) + { + /* Allocate the stack space. */ + pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + + if( pucStackMemory != NULL ) + { + /* Since stack grows down, the starting point will be the last + * location. Note that this location is next to the last + * allocated byte for stack (excluding the space for seal values) + * because the hardware decrements the stack pointer before + * writing i.e. if stack pointer is 0x2, a push operation will + * decrement the stack pointer to 0x1 and then write at 0x1. */ + xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize; + + /* Seal the created secure process stack. */ + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; + + /* The stack cannot go beyond this location. This value is + * programmed in the PSPLIM register on context switch.*/ + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = pucStackMemory; + + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle; + + #if ( configENABLE_MPU == 1 ) + { + /* Store the correct CONTROL value for the task on the stack. + * This value is programmed in the CONTROL register on + * context switch. */ + pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; + pulCurrentStackPointer--; + + if( ulIsTaskPrivileged ) + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; + } + else + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; + } + + /* Store the current stack pointer. This value is programmed in + * the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + } + #else /* configENABLE_MPU */ + { + /* Current SP is set to the starting of the stack. This + * value programmed in the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + } + #endif /* configENABLE_MPU */ + + /* Ensure to never return 0 as a valid context handle. */ + xSecureContextHandle = ulSecureContextIndex + 1UL; + } + } + } + + return xSecureContextHandle; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) +{ + uint32_t ulIPSR, ulSecureContextIndex; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* Only free if a valid context handle is passed. */ + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + /* Ensure that the secure context being deleted is associated with + * the task. */ + if( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) + { + /* Free the stack space. */ + vPortFree( xSecureContexts[ ulSecureContextIndex ].pucStackLimit ); + + /* Return the secure context back to the free secure contexts pool. */ + vReturnSecureContext( ulSecureContextIndex ); + } + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that no secure context is loaded and the task is loading it's + * own context. */ + if( ( pucStackLimit == securecontextNO_STACK ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_LoadContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that task's context is loaded and the task is saving it's own + * context. */ + if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_SaveContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM33/secure/secure_context.h b/portable/GCC/ARM_CM33/secure/secure_context.h new file mode 100644 index 000000000..e36a8e430 --- /dev/null +++ b/portable/GCC/ARM_CM33/secure/secure_context.h @@ -0,0 +1,138 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_CONTEXT_H__ +#define __SECURE_CONTEXT_H__ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" + +/** + * @brief PSP value when no secure context is loaded. + */ +#define securecontextNO_STACK 0x0 + +/** + * @brief Invalid context ID. + */ +#define securecontextINVALID_CONTEXT_ID 0UL +/*-----------------------------------------------------------*/ + +/** + * @brief Structure to represent a secure context. + * + * @note Since stack grows down, pucStackStart is the highest address while + * pucStackLimit is the first address of the allocated memory. + */ +typedef struct SecureContext +{ + uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */ + uint8_t * pucStackLimit; /**< Last location of the stack memory (PSPLIM). */ + uint8_t * pucStackStart; /**< First location of the stack memory. */ + void * pvTaskHandle; /**< Task handle of the task this context is associated with. */ +} SecureContext_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Opaque handle for a secure context. + */ +typedef uint32_t SecureContextHandle_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Initializes the secure context management system. + * + * PSP is set to NULL and therefore a task must allocate and load a context + * before calling any secure side function in the thread mode. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureContext_Init( void ); + +/** + * @brief Allocates a context on the secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] ulSecureStackSize Size of the stack to allocate on secure side. + * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise. + * + * @return Opaque context handle if context is successfully allocated, NULL + * otherwise. + */ +#if ( configENABLE_MPU == 1 ) + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ); +#else /* configENABLE_MPU */ + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ); +#endif /* configENABLE_MPU */ + +/** + * @brief Frees the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the + * context to be freed. + */ +void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); + +/** + * @brief Loads the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be loaded. + */ +void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); + +/** + * @brief Saves the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be saved. + */ +void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); + +#endif /* __SECURE_CONTEXT_H__ */ diff --git a/portable/GCC/ARM_CM33/secure/secure_context_port.c b/portable/GCC/ARM_CM33/secure/secure_context_port.c new file mode 100644 index 000000000..2d3d9439d --- /dev/null +++ b/portable/GCC/ARM_CM33/secure/secure_context_port.c @@ -0,0 +1,97 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Secure context includes. */ +#include "secure_context.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) ); +void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) ); + +void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) +{ + /* pxSecureContext value is in r0. */ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r1, ipsr \n" /* r1 = IPSR. */ + " cbz r1, load_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */ + " ldmia r0!, {r1, r2} \n" /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */ + " \n" + #if ( configENABLE_MPU == 1 ) + " ldmia r1!, {r3} \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */ + " msr control, r3 \n" /* CONTROL = r3. */ + #endif /* configENABLE_MPU */ + " \n" + " msr psplim, r2 \n" /* PSPLIM = r2. */ + " msr psp, r1 \n" /* PSP = r1. */ + " \n" + " load_ctx_therad_mode: \n" + " bx lr \n" + " \n" + ::: "r0", "r1", "r2" + ); +} +/*-----------------------------------------------------------*/ + +void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) +{ + /* pxSecureContext value is in r0. */ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r1, ipsr \n" /* r1 = IPSR. */ + " cbz r1, save_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */ + " mrs r1, psp \n" /* r1 = PSP. */ + " \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " vstmdb r1!, {s0} \n" /* Trigger the deferred stacking of FPU registers. */ + " vldmia r1!, {s0} \n" /* Nullify the effect of the previous statement. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + #if ( configENABLE_MPU == 1 ) + " mrs r2, control \n" /* r2 = CONTROL. */ + " stmdb r1!, {r2} \n" /* Store CONTROL value on the stack. */ + #endif /* configENABLE_MPU */ + " \n" + " str r1, [r0] \n" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */ + " movs r1, %0 \n" /* r1 = securecontextNO_STACK. */ + " msr psplim, r1 \n" /* PSPLIM = securecontextNO_STACK. */ + " msr psp, r1 \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */ + " \n" + " save_ctx_therad_mode: \n" + " bx lr \n" + " \n" + ::"i" ( securecontextNO_STACK ) : "r1", "memory" + ); +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM33/secure/secure_heap.c b/portable/GCC/ARM_CM33/secure/secure_heap.c new file mode 100644 index 000000000..896b53e2d --- /dev/null +++ b/portable/GCC/ARM_CM33/secure/secure_heap.c @@ -0,0 +1,485 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Configuration includes. */ +#include "FreeRTOSConfig.h" + +/* Secure context heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Total heap size. + */ +#ifndef secureconfigTOTAL_HEAP_SIZE + #define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) ) +#endif + +/* No test marker by default. */ +#ifndef mtCOVERAGE_TEST_MARKER + #define mtCOVERAGE_TEST_MARKER() +#endif + +/* No tracing by default. */ +#ifndef traceMALLOC + #define traceMALLOC( pvReturn, xWantedSize ) +#endif + +/* No tracing by default. */ +#ifndef traceFREE + #define traceFREE( pv, xBlockSize ) +#endif + +/* Block sizes must not get too small. */ +#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) ) + +/* Assumes 8bit bytes! */ +#define secureheapBITS_PER_BYTE ( ( size_t ) 8 ) + +/* Max value that fits in a size_t type. */ +#define secureheapSIZE_MAX ( ~( ( size_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define secureheapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) ) + +/* MSB of the xBlockSize member of an BlockLink_t structure is used to track + * the allocation status of a block. When MSB of the xBlockSize member of + * an BlockLink_t structure is set then the block belongs to the application. + * When the bit is free the block is still part of the free heap space. */ +#define secureheapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) ) +#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 ) +#define secureheapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 ) +#define secureheapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK ) +#define secureheapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK ) +/*-----------------------------------------------------------*/ + +/* Allocate the memory for the heap. */ +#if ( configAPPLICATION_ALLOCATED_HEAP == 1 ) + +/* The application writer has already defined the array used for the RTOS +* heap - probably so it can be placed in a special segment or address. */ + extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#else /* configAPPLICATION_ALLOCATED_HEAP */ + static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#endif /* configAPPLICATION_ALLOCATED_HEAP */ + +/** + * @brief The linked list structure. + * + * This is used to link free blocks in order of their memory address. + */ +typedef struct A_BLOCK_LINK +{ + struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */ + size_t xBlockSize; /**< The size of the free block. */ +} BlockLink_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Called automatically to setup the required heap structures the first + * time pvPortMalloc() is called. + */ +static void prvHeapInit( void ); + +/** + * @brief Inserts a block of memory that is being freed into the correct + * position in the list of free memory blocks. + * + * The block being freed will be merged with the block in front it and/or the + * block behind it if the memory blocks are adjacent to each other. + * + * @param[in] pxBlockToInsert The block being freed. + */ +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ); +/*-----------------------------------------------------------*/ + +/** + * @brief The size of the structure placed at the beginning of each allocated + * memory block must by correctly byte aligned. + */ +static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + +/** + * @brief Create a couple of list links to mark the start and end of the list. + */ +static BlockLink_t xStart; +static BlockLink_t * pxEnd = NULL; + +/** + * @brief Keeps track of the number of free bytes remaining, but says nothing + * about fragmentation. + */ +static size_t xFreeBytesRemaining = 0U; +static size_t xMinimumEverFreeBytesRemaining = 0U; + +/*-----------------------------------------------------------*/ + +static void prvHeapInit( void ) +{ + BlockLink_t * pxFirstFreeBlock; + uint8_t * pucAlignedHeap; + size_t uxAddress; + size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE; + + /* Ensure the heap starts on a correctly aligned boundary. */ + uxAddress = ( size_t ) ucHeap; + + if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 ) + { + uxAddress += ( secureportBYTE_ALIGNMENT - 1 ); + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; + } + + pucAlignedHeap = ( uint8_t * ) uxAddress; + + /* xStart is used to hold a pointer to the first item in the list of free + * blocks. The void cast is used to prevent compiler warnings. */ + xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; + xStart.xBlockSize = ( size_t ) 0; + + /* pxEnd is used to mark the end of the list of free blocks and is inserted + * at the end of the heap space. */ + uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; + uxAddress -= xHeapStructSize; + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + pxEnd = ( void * ) uxAddress; + pxEnd->xBlockSize = 0; + pxEnd->pxNextFreeBlock = NULL; + + /* To start with there is a single free block that is sized to take up the + * entire heap space, minus the space taken by pxEnd. */ + pxFirstFreeBlock = ( void * ) pucAlignedHeap; + pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; + pxFirstFreeBlock->pxNextFreeBlock = pxEnd; + + /* Only one block exists - and it covers the entire usable heap space. */ + xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; +} +/*-----------------------------------------------------------*/ + +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) +{ + BlockLink_t * pxIterator; + uint8_t * puc; + + /* Iterate through the list until a block is found that has a higher address + * than the block being inserted. */ + for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) + { + /* Nothing to do here, just iterate to the right position. */ + } + + /* Do the block being inserted, and the block it is being inserted after + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxIterator; + + if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) + { + pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; + pxBlockToInsert = pxIterator; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Do the block being inserted, and the block it is being inserted before + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxBlockToInsert; + + if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) + { + if( pxIterator->pxNextFreeBlock != pxEnd ) + { + /* Form one big block from the two blocks. */ + pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxEnd; + } + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; + } + + /* If the block being inserted plugged a gap, so was merged with the block + * before and the block after, then it's pxNextFreeBlock pointer will have + * already been set, and should not be set here as that would make it point + * to itself. */ + if( pxIterator != pxBlockToInsert ) + { + pxIterator->pxNextFreeBlock = pxBlockToInsert; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} +/*-----------------------------------------------------------*/ + +void * pvPortMalloc( size_t xWantedSize ) +{ + BlockLink_t * pxBlock; + BlockLink_t * pxPreviousBlock; + BlockLink_t * pxNewBlockLink; + void * pvReturn = NULL; + size_t xAdditionalRequiredSize; + size_t xAllocatedBlockSize = 0; + + /* If this is the first call to malloc then the heap will require + * initialisation to setup the list of free blocks. */ + if( pxEnd == NULL ) + { + prvHeapInit(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xWantedSize > 0 ) + { + /* The wanted size must be increased so it can contain a BlockLink_t + * structure in addition to the requested amount of bytes. */ + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 ) + { + xWantedSize += xHeapStructSize; + + /* Ensure that blocks are always aligned to the required number + * of bytes. */ + if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 ) + { + /* Byte alignment required. */ + xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ); + + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 ) + { + xWantedSize += xAdditionalRequiredSize; + } + else + { + xWantedSize = 0; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + xWantedSize = 0; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Check the requested block size is not so large that the top bit is set. + * The top bit of the block size member of the BlockLink_t structure is used + * to determine who owns the block - the application or the kernel, so it + * must be free. */ + if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 ) + { + if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) + { + /* Traverse the list from the start (lowest address) block until + * one of adequate size is found. */ + pxPreviousBlock = &xStart; + pxBlock = xStart.pxNextFreeBlock; + + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + { + pxPreviousBlock = pxBlock; + pxBlock = pxBlock->pxNextFreeBlock; + } + + /* If the end marker was reached then a block of adequate size was + * not found. */ + if( pxBlock != pxEnd ) + { + /* Return the memory space pointed to - jumping over the + * BlockLink_t structure at its start. */ + pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); + + /* This block is being returned for use so must be taken out + * of the list of free blocks. */ + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + + /* If the block is larger than required it can be split into + * two. */ + if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE ) + { + /* This block is to be split into two. Create a new + * block following the number of bytes requested. The void + * cast is used to prevent byte alignment warnings from the + * compiler. */ + pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); + secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + + /* Calculate the sizes of two blocks split from the single + * block. */ + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + pxBlock->xBlockSize = xWantedSize; + + /* Insert the new block into the list of free blocks. */ + pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock; + pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xFreeBytesRemaining -= pxBlock->xBlockSize; + + if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) + { + xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xAllocatedBlockSize = pxBlock->xBlockSize; + + /* The block is being returned - it is allocated and owned by + * the application and has no "next" block. */ + secureheapALLOCATE_BLOCK( pxBlock ); + pxBlock->pxNextFreeBlock = NULL; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceMALLOC( pvReturn, xAllocatedBlockSize ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xAllocatedBlockSize; + + #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) + { + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */ + + secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 ); + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void * pv ) +{ + uint8_t * puc = ( uint8_t * ) pv; + BlockLink_t * pxLink; + + if( pv != NULL ) + { + /* The memory being freed will have an BlockLink_t structure immediately + * before it. */ + puc -= xHeapStructSize; + + /* This casting is to keep the compiler from issuing warnings. */ + pxLink = ( void * ) puc; + + /* Check the block is actually allocated. */ + secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ); + secureportASSERT( pxLink->pxNextFreeBlock == NULL ); + + if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ) + { + if( pxLink->pxNextFreeBlock == NULL ) + { + /* The block is being returned to the heap - it is no longer + * allocated. */ + secureheapFREE_BLOCK( pxLink ); + + secureportDISABLE_NON_SECURE_INTERRUPTS(); + { + /* Add this block to the list of free blocks. */ + xFreeBytesRemaining += pxLink->xBlockSize; + traceFREE( pv, pxLink->xBlockSize ); + prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); + } + secureportENABLE_NON_SECURE_INTERRUPTS(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } +} +/*-----------------------------------------------------------*/ + +size_t xPortGetFreeHeapSize( void ) +{ + return xFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +size_t xPortGetMinimumEverFreeHeapSize( void ) +{ + return xMinimumEverFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM33/secure/secure_heap.h b/portable/GCC/ARM_CM33/secure/secure_heap.h new file mode 100644 index 000000000..0e84a9d9d --- /dev/null +++ b/portable/GCC/ARM_CM33/secure/secure_heap.h @@ -0,0 +1,66 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_HEAP_H__ +#define __SECURE_HEAP_H__ + +/* Standard includes. */ +#include + +/** + * @brief Allocates memory from heap. + * + * @param[in] xWantedSize The size of the memory to be allocated. + * + * @return Pointer to the memory region if the allocation is successful, NULL + * otherwise. + */ +void * pvPortMalloc( size_t xWantedSize ); + +/** + * @brief Frees the previously allocated memory. + * + * @param[in] pv Pointer to the memory to be freed. + */ +void vPortFree( void * pv ); + +/** + * @brief Get the free heap size. + * + * @return Free heap size. + */ +size_t xPortGetFreeHeapSize( void ); + +/** + * @brief Get the minimum ever free heap size. + * + * @return Minimum ever free heap size. + */ +size_t xPortGetMinimumEverFreeHeapSize( void ); + +#endif /* __SECURE_HEAP_H__ */ diff --git a/portable/GCC/ARM_CM33/secure/secure_init.c b/portable/GCC/ARM_CM33/secure/secure_init.c new file mode 100644 index 000000000..c50d37668 --- /dev/null +++ b/portable/GCC/ARM_CM33/secure/secure_init.c @@ -0,0 +1,106 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Secure init includes. */ +#include "secure_init.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Constants required to manipulate the SCB. + */ +#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */ +#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL ) +#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS ) +#define secureinitSCB_AIRCR_PRIS_POS ( 14UL ) +#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS ) + +/** + * @brief Constants required to manipulate the FPU. + */ +#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define secureinitFPCCR_LSPENS_POS ( 29UL ) +#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS ) +#define secureinitFPCCR_TS_POS ( 26UL ) +#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS ) + +#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */ +#define secureinitNSACR_CP10_POS ( 10UL ) +#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS ) +#define secureinitNSACR_CP11_POS ( 11UL ) +#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS ) +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) | + ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) | + ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK ); + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is + * permitted. CP11 should be programmed to the same value as CP10. */ + *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK ); + + /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures + * that we can enable/disable lazy stacking in port.c file. */ + *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK ); + + /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP + * registers (S16-S31) are also pushed to stack on exception entry and + * restored on exception return. */ + *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK ); + } +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM33/secure/secure_init.h b/portable/GCC/ARM_CM33/secure/secure_init.h new file mode 100644 index 000000000..ebe04900f --- /dev/null +++ b/portable/GCC/ARM_CM33/secure/secure_init.h @@ -0,0 +1,54 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_INIT_H__ +#define __SECURE_INIT_H__ + +/** + * @brief De-prioritizes the non-secure exceptions. + * + * This is needed to ensure that the non-secure PendSV runs at the lowest + * priority. Context switch is done in the non-secure PendSV handler. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_DePrioritizeNSExceptions( void ); + +/** + * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access. + * + * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point + * Registers are not leaked to the non-secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_EnableNSFPUAccess( void ); + +#endif /* __SECURE_INIT_H__ */ diff --git a/portable/GCC/ARM_CM33/secure/secure_port_macros.h b/portable/GCC/ARM_CM33/secure/secure_port_macros.h new file mode 100644 index 000000000..a70da2c65 --- /dev/null +++ b/portable/GCC/ARM_CM33/secure/secure_port_macros.h @@ -0,0 +1,140 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_PORT_MACROS_H__ +#define __SECURE_PORT_MACROS_H__ + +/** + * @brief Byte alignment requirements. + */ +#define secureportBYTE_ALIGNMENT 8 +#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 ) + +/** + * @brief Macro to declare a function as non-secure callable. + */ +#if defined( __IAR_SYSTEMS_ICC__ ) + #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry __root +#else + #define secureportNON_SECURE_CALLABLE __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) ) +#endif + +/** + * @brief Set the secure PRIMASK value. + */ +#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Set the non-secure PRIMASK value. + */ +#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Read the PSP value in the given variable. + */ +#define secureportREAD_PSP( pucOutCurrentStackPointer ) \ + __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) ) + +/** + * @brief Set the PSP to the given value. + */ +#define secureportSET_PSP( pucCurrentStackPointer ) \ + __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) ) + +/** + * @brief Read the PSPLIM value in the given variable. + */ +#define secureportREAD_PSPLIM( pucOutStackLimit ) \ + __asm volatile ( "mrs %0, psplim" : "=r" ( pucOutStackLimit ) ) + +/** + * @brief Set the PSPLIM to the given value. + */ +#define secureportSET_PSPLIM( pucStackLimit ) \ + __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) ) + +/** + * @brief Set the NonSecure MSP to the given value. + */ +#define secureportSET_MSP_NS( pucMainStackPointer ) \ + __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) ) + +/** + * @brief Set the CONTROL register to the given value. + */ +#define secureportSET_CONTROL( ulControl ) \ + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" ) + +/** + * @brief Read the Interrupt Program Status Register (IPSR) value in the given + * variable. + */ +#define secureportREAD_IPSR( ulIPSR ) \ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) ) + +/** + * @brief PRIMASK value to enable interrupts. + */ +#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0 + +/** + * @brief PRIMASK value to disable interrupts. + */ +#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1 + +/** + * @brief Disable secure interrupts. + */ +#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Disable non-secure interrupts. + * + * This effectively disables context switches. + */ +#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Enable non-secure interrupts. + */ +#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL ) + +/** + * @brief Assert definition. + */ +#define secureportASSERT( x ) \ + if( ( x ) == 0 ) \ + { \ + secureportDISABLE_SECURE_INTERRUPTS(); \ + secureportDISABLE_NON_SECURE_INTERRUPTS(); \ + for( ; ; ) {; } \ + } + +#endif /* __SECURE_PORT_MACROS_H__ */ diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c new file mode 100644 index 000000000..4b984932d --- /dev/null +++ b/portable/GCC/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.c @@ -0,0 +1,2055 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" +#include "event_groups.h" +#include "stream_buffer.h" +#include "mpu_prototypes.h" +#include "mpu_syscall_numbers.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( INCLUDE_xTaskDelayUntil == 1 ) + + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskDelayUntilImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskDelayUntil_Unpriv \n" + " MPU_xTaskDelayUntil_Priv: \n" + " b MPU_xTaskDelayUntilImpl \n" + " MPU_xTaskDelayUntil_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskAbortDelayImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskAbortDelay_Unpriv \n" + " MPU_xTaskAbortDelay_Priv: \n" + " b MPU_xTaskAbortDelayImpl \n" + " MPU_xTaskAbortDelay_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskDelay == 1 ) + + void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskDelayImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskDelay_Unpriv \n" + " MPU_vTaskDelay_Priv: \n" + " b MPU_vTaskDelayImpl \n" + " MPU_vTaskDelay_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskPriorityGet == 1 ) + + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskPriorityGetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskPriorityGet_Unpriv \n" + " MPU_uxTaskPriorityGet_Priv: \n" + " b MPU_uxTaskPriorityGetImpl \n" + " MPU_uxTaskPriorityGet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_eTaskGetState == 1 ) + + eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_eTaskGetStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_eTaskGetState_Unpriv \n" + " MPU_eTaskGetState_Priv: \n" + " b MPU_eTaskGetStateImpl \n" + " MPU_eTaskGetState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory" + ); + } + + #endif /* if ( INCLUDE_eTaskGetState == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskGetInfoImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskGetInfo_Unpriv \n" + " MPU_vTaskGetInfo_Priv: \n" + " b MPU_vTaskGetInfoImpl \n" + " MPU_vTaskGetInfo_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory" + ); + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) + + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetIdleTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetIdleTaskHandle_Unpriv \n" + " MPU_xTaskGetIdleTaskHandle_Priv: \n" + " b MPU_xTaskGetIdleTaskHandleImpl \n" + " MPU_xTaskGetIdleTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + + void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSuspendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSuspend_Unpriv \n" + " MPU_vTaskSuspend_Priv: \n" + " b MPU_vTaskSuspendImpl \n" + " MPU_vTaskSuspend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + + void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskResumeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskResume_Unpriv \n" + " MPU_vTaskResume_Priv: \n" + " b MPU_vTaskResumeImpl \n" + " MPU_vTaskResume_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + TickType_t MPU_xTaskGetTickCount( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetTickCountImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetTickCount_Unpriv \n" + " MPU_xTaskGetTickCount_Priv: \n" + " b MPU_xTaskGetTickCountImpl \n" + " MPU_xTaskGetTickCount_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetNumberOfTasksImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetNumberOfTasks_Unpriv \n" + " MPU_uxTaskGetNumberOfTasks_Priv: \n" + " b MPU_uxTaskGetNumberOfTasksImpl \n" + " MPU_uxTaskGetNumberOfTasks_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetRunTimeCounterImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetRunTimeCounter_Unpriv \n" + " MPU_ulTaskGetRunTimeCounter_Priv: \n" + " b MPU_ulTaskGetRunTimeCounterImpl \n" + " MPU_ulTaskGetRunTimeCounter_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetRunTimePercentImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetRunTimePercent_Unpriv \n" + " MPU_ulTaskGetRunTimePercent_Priv: \n" + " b MPU_ulTaskGetRunTimePercentImpl \n" + " MPU_ulTaskGetRunTimePercent_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetIdleRunTimePercentImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv \n" + " MPU_ulTaskGetIdleRunTimePercent_Priv: \n" + " b MPU_ulTaskGetIdleRunTimePercentImpl \n" + " MPU_ulTaskGetIdleRunTimePercent_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetIdleRunTimeCounterImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv \n" + " MPU_ulTaskGetIdleRunTimeCounter_Priv: \n" + " b MPU_ulTaskGetIdleRunTimeCounterImpl \n" + " MPU_ulTaskGetIdleRunTimeCounter_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetApplicationTaskTagImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetApplicationTaskTag_Unpriv \n" + " MPU_vTaskSetApplicationTaskTag_Priv: \n" + " b MPU_vTaskSetApplicationTaskTagImpl \n" + " MPU_vTaskSetApplicationTaskTag_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory" + ); + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetApplicationTaskTagImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetApplicationTaskTag_Unpriv \n" + " MPU_xTaskGetApplicationTaskTag_Priv: \n" + " b MPU_xTaskGetApplicationTaskTagImpl \n" + " MPU_xTaskGetApplicationTaskTag_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory" + ); + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetThreadLocalStoragePointerImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv \n" + " MPU_vTaskSetThreadLocalStoragePointer_Priv: \n" + " b MPU_vTaskSetThreadLocalStoragePointerImpl \n" + " MPU_vTaskSetThreadLocalStoragePointer_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory" + ); + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv \n" + " MPU_pvTaskGetThreadLocalStoragePointer_Priv: \n" + " b MPU_pvTaskGetThreadLocalStoragePointerImpl \n" + " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory" + ); + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetSystemStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetSystemState_Unpriv \n" + " MPU_uxTaskGetSystemState_Priv: \n" + " b MPU_uxTaskGetSystemStateImpl \n" + " MPU_uxTaskGetSystemState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory" + ); + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) + + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetStackHighWaterMarkImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetStackHighWaterMark_Unpriv \n" + " MPU_uxTaskGetStackHighWaterMark_Priv: \n" + " b MPU_uxTaskGetStackHighWaterMarkImpl \n" + " MPU_uxTaskGetStackHighWaterMark_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetStackHighWaterMark2Impl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv \n" + " MPU_uxTaskGetStackHighWaterMark2_Priv: \n" + " b MPU_uxTaskGetStackHighWaterMark2Impl \n" + " MPU_uxTaskGetStackHighWaterMark2_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) + + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetCurrentTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetCurrentTaskHandle_Unpriv \n" + " MPU_xTaskGetCurrentTaskHandle_Priv: \n" + " b MPU_xTaskGetCurrentTaskHandleImpl \n" + " MPU_xTaskGetCurrentTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory" + ); + } + + #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetSchedulerState == 1 ) + + BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetSchedulerStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetSchedulerState_Unpriv \n" + " MPU_xTaskGetSchedulerState_Priv: \n" + " b MPU_xTaskGetSchedulerStateImpl \n" + " MPU_xTaskGetSchedulerState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */ +/*-----------------------------------------------------------*/ + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetTimeOutStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetTimeOutState_Unpriv \n" + " MPU_vTaskSetTimeOutState_Priv: \n" + " b MPU_vTaskSetTimeOutStateImpl \n" + " MPU_vTaskSetTimeOutState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskCheckForTimeOutImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskCheckForTimeOut_Unpriv \n" + " MPU_xTaskCheckForTimeOut_Priv: \n" + " b MPU_xTaskCheckForTimeOutImpl \n" + " MPU_xTaskCheckForTimeOut_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotify_Unpriv \n" + " MPU_xTaskGenericNotify_Priv: \n" + " b MPU_xTaskGenericNotifyImpl \n" + " MPU_xTaskGenericNotify_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyWaitImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotifyWait_Unpriv \n" + " MPU_xTaskGenericNotifyWait_Priv: \n" + " b MPU_xTaskGenericNotifyWaitImpl \n" + " MPU_xTaskGenericNotifyWait_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGenericNotifyTakeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGenericNotifyTake_Unpriv \n" + " MPU_ulTaskGenericNotifyTake_Priv: \n" + " b MPU_ulTaskGenericNotifyTakeImpl \n" + " MPU_ulTaskGenericNotifyTake_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyStateClearImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotifyStateClear_Unpriv \n" + " MPU_xTaskGenericNotifyStateClear_Priv: \n" + " b MPU_xTaskGenericNotifyStateClearImpl \n" + " MPU_xTaskGenericNotifyStateClear_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGenericNotifyValueClearImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGenericNotifyValueClear_Unpriv \n" + " MPU_ulTaskGenericNotifyValueClear_Priv: \n" + " b MPU_ulTaskGenericNotifyValueClearImpl \n" + " MPU_ulTaskGenericNotifyValueClear_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGenericSendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGenericSend_Unpriv \n" + " MPU_xQueueGenericSend_Priv: \n" + " b MPU_xQueueGenericSendImpl \n" + " MPU_xQueueGenericSend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxQueueMessagesWaitingImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxQueueMessagesWaiting_Unpriv \n" + " MPU_uxQueueMessagesWaiting_Priv: \n" + " b MPU_uxQueueMessagesWaitingImpl \n" + " MPU_uxQueueMessagesWaiting_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxQueueSpacesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxQueueSpacesAvailable_Unpriv \n" + " MPU_uxQueueSpacesAvailable_Priv: \n" + " b MPU_uxQueueSpacesAvailableImpl \n" + " MPU_uxQueueSpacesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueReceiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueReceive_Unpriv \n" + " MPU_xQueueReceive_Priv: \n" + " b MPU_xQueueReceiveImpl \n" + " MPU_xQueueReceive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueuePeekImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueuePeek_Unpriv \n" + " MPU_xQueuePeek_Priv: \n" + " b MPU_xQueuePeekImpl \n" + " MPU_xQueuePeek_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueSemaphoreTakeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueSemaphoreTake_Unpriv \n" + " MPU_xQueueSemaphoreTake_Priv: \n" + " b MPU_xQueueSemaphoreTakeImpl \n" + " MPU_xQueueSemaphoreTake_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) + + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGetMutexHolderImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGetMutexHolder_Unpriv \n" + " MPU_xQueueGetMutexHolder_Priv: \n" + " b MPU_xQueueGetMutexHolderImpl \n" + " MPU_xQueueGetMutexHolder_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory" + ); + } + + #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueTakeMutexRecursiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueTakeMutexRecursive_Unpriv \n" + " MPU_xQueueTakeMutexRecursive_Priv: \n" + " b MPU_xQueueTakeMutexRecursiveImpl \n" + " MPU_xQueueTakeMutexRecursive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory" + ); + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGiveMutexRecursiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGiveMutexRecursive_Unpriv \n" + " MPU_xQueueGiveMutexRecursive_Priv: \n" + " b MPU_xQueueGiveMutexRecursiveImpl \n" + " MPU_xQueueGiveMutexRecursive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory" + ); + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueSelectFromSetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueSelectFromSet_Unpriv \n" + " MPU_xQueueSelectFromSet_Priv: \n" + " b MPU_xQueueSelectFromSetImpl \n" + " MPU_xQueueSelectFromSet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory" + ); + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueAddToSetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueAddToSet_Unpriv \n" + " MPU_xQueueAddToSet_Priv: \n" + " b MPU_xQueueAddToSetImpl \n" + " MPU_xQueueAddToSet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory" + ); + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vQueueAddToRegistryImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vQueueAddToRegistry_Unpriv \n" + " MPU_vQueueAddToRegistry_Priv: \n" + " b MPU_vQueueAddToRegistryImpl \n" + " MPU_vQueueAddToRegistry_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vQueueUnregisterQueueImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vQueueUnregisterQueue_Unpriv \n" + " MPU_vQueueUnregisterQueue_Priv: \n" + " b MPU_vQueueUnregisterQueueImpl \n" + " MPU_vQueueUnregisterQueue_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pcQueueGetNameImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pcQueueGetName_Unpriv \n" + " MPU_pcQueueGetName_Priv: \n" + " b MPU_pcQueueGetNameImpl \n" + " MPU_pcQueueGetName_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pvTimerGetTimerIDImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pvTimerGetTimerID_Unpriv \n" + " MPU_pvTimerGetTimerID_Priv: \n" + " b MPU_pvTimerGetTimerIDImpl \n" + " MPU_pvTimerGetTimerID_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTimerSetTimerIDImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTimerSetTimerID_Unpriv \n" + " MPU_vTimerSetTimerID_Priv: \n" + " b MPU_vTimerSetTimerIDImpl \n" + " MPU_vTimerSetTimerID_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerIsTimerActiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerIsTimerActive_Unpriv \n" + " MPU_xTimerIsTimerActive_Priv: \n" + " b MPU_xTimerIsTimerActiveImpl \n" + " MPU_xTimerIsTimerActive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv \n" + " MPU_xTimerGetTimerDaemonTaskHandle_Priv: \n" + " b MPU_xTimerGetTimerDaemonTaskHandleImpl \n" + " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGenericCommandFromTaskImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGenericCommandFromTask_Unpriv \n" + " MPU_xTimerGenericCommandFromTask_Priv: \n" + " b MPU_xTimerGenericCommandFromTaskImpl \n" + " MPU_xTimerGenericCommandFromTask_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pcTimerGetNameImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pcTimerGetName_Unpriv \n" + " MPU_pcTimerGetName_Priv: \n" + " b MPU_pcTimerGetNameImpl \n" + " MPU_pcTimerGetName_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTimerSetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTimerSetReloadMode_Unpriv \n" + " MPU_vTimerSetReloadMode_Priv: \n" + " b MPU_vTimerSetReloadModeImpl \n" + " MPU_vTimerSetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetReloadMode_Unpriv \n" + " MPU_xTimerGetReloadMode_Priv: \n" + " b MPU_xTimerGetReloadModeImpl \n" + " MPU_xTimerGetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTimerGetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTimerGetReloadMode_Unpriv \n" + " MPU_uxTimerGetReloadMode_Priv: \n" + " b MPU_uxTimerGetReloadModeImpl \n" + " MPU_uxTimerGetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetPeriodImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetPeriod_Unpriv \n" + " MPU_xTimerGetPeriod_Priv: \n" + " b MPU_xTimerGetPeriodImpl \n" + " MPU_xTimerGetPeriod_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetExpiryTimeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetExpiryTime_Unpriv \n" + " MPU_xTimerGetExpiryTime_Priv: \n" + " b MPU_xTimerGetExpiryTimeImpl \n" + " MPU_xTimerGetExpiryTime_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupWaitBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupWaitBits_Unpriv \n" + " MPU_xEventGroupWaitBits_Priv: \n" + " b MPU_xEventGroupWaitBitsImpl \n" + " MPU_xEventGroupWaitBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupClearBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupClearBits_Unpriv \n" + " MPU_xEventGroupClearBits_Priv: \n" + " b MPU_xEventGroupClearBitsImpl \n" + " MPU_xEventGroupClearBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupSetBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupSetBits_Unpriv \n" + " MPU_xEventGroupSetBits_Priv: \n" + " b MPU_xEventGroupSetBitsImpl \n" + " MPU_xEventGroupSetBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupSyncImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupSync_Unpriv \n" + " MPU_xEventGroupSync_Priv: \n" + " b MPU_xEventGroupSyncImpl \n" + " MPU_xEventGroupSync_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxEventGroupGetNumberImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxEventGroupGetNumber_Unpriv \n" + " MPU_uxEventGroupGetNumber_Priv: \n" + " b MPU_uxEventGroupGetNumberImpl \n" + " MPU_uxEventGroupGetNumber_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory" + ); + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vEventGroupSetNumberImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vEventGroupSetNumber_Unpriv \n" + " MPU_vEventGroupSetNumber_Priv: \n" + " b MPU_vEventGroupSetNumberImpl \n" + " MPU_vEventGroupSetNumber_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory" + ); + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferSend_Unpriv \n" + " MPU_xStreamBufferSend_Priv: \n" + " b MPU_xStreamBufferSendImpl \n" + " MPU_xStreamBufferSend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferReceiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferReceive_Unpriv \n" + " MPU_xStreamBufferReceive_Priv: \n" + " b MPU_xStreamBufferReceiveImpl \n" + " MPU_xStreamBufferReceive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferIsFullImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferIsFull_Unpriv \n" + " MPU_xStreamBufferIsFull_Priv: \n" + " b MPU_xStreamBufferIsFullImpl \n" + " MPU_xStreamBufferIsFull_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferIsEmptyImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferIsEmpty_Unpriv \n" + " MPU_xStreamBufferIsEmpty_Priv: \n" + " b MPU_xStreamBufferIsEmptyImpl \n" + " MPU_xStreamBufferIsEmpty_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSpacesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferSpacesAvailable_Unpriv \n" + " MPU_xStreamBufferSpacesAvailable_Priv: \n" + " b MPU_xStreamBufferSpacesAvailableImpl \n" + " MPU_xStreamBufferSpacesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferBytesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferBytesAvailable_Unpriv \n" + " MPU_xStreamBufferBytesAvailable_Priv: \n" + " b MPU_xStreamBufferBytesAvailableImpl \n" + " MPU_xStreamBufferBytesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSetTriggerLevelImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferSetTriggerLevel_Unpriv \n" + " MPU_xStreamBufferSetTriggerLevel_Priv: \n" + " b MPU_xStreamBufferSetTriggerLevelImpl \n" + " MPU_xStreamBufferSetTriggerLevel_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferNextMessageLengthBytesImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv \n" + " MPU_xStreamBufferNextMessageLengthBytes_Priv: \n" + " b MPU_xStreamBufferNextMessageLengthBytesImpl \n" + " MPU_xStreamBufferNextMessageLengthBytes_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c new file mode 100644 index 000000000..76d2b2445 --- /dev/null +++ b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c @@ -0,0 +1,2280 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024-2025 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU includes. */ +#include "mpu_wrappers.h" +#include "mpu_syscall_numbers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration settings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to check the validity of an interrupt priority. + */ +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) ) +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used during system call enter and exit. + */ +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Offsets in the stack to the parameters when inside the SVC handler. + */ +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +#if ( portARMV8M_MINOR_VERSION >= 1 ) + + /* Enable Privileged eXecute Never MPU attribute for the selected memory + * region. */ + #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL ) +#endif /* portARMV8M_MINOR_VERSION >= 1 */ + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Extract first address of the MPU region as encoded in the + * RBAR (Region Base Address Register) value. */ +#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \ + ( ( rbar ) & portMPU_RBAR_ADDRESS_MASK ) + +/* Extract last address of the MPU region as encoded in the + * RLAR (Region Limit Address Register) value. */ +#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \ + ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK ) + +/* Does addr lies within [start, end] address range? */ +#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \ + ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) ) + +/* Is the access request satisfied by the available permissions? */ +#define portIS_AUTHORIZED( accessRequest, permissions ) \ + ( ( ( permissions ) & ( accessRequest ) ) == accessRequest ) + +/* Max value that fits in a uint32_t type. */ +#define portUINT32_MAX ( ~( ( uint32_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. + */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 + +/** + * @brief Constants required to check and configure PACBTI security feature implementation. + */ +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) ) + + #define portCONTROL_UPAC_EN ( 1UL << 7UL ) + #define portCONTROL_PAC_EN ( 1UL << 6UL ) + #define portCONTROL_UBTI_EN ( 1UL << 5UL ) + #define portCONTROL_BTI_EN ( 1UL << 4UL ) + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Extract MPU region's access permissions from the Region Base Address + * Register (RBAR) value. + * + * @param ulRBARValue RBAR value for the MPU region. + * + * @return uint32_t Access permissions. + */ + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + + /** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + /** + * @brief Configures PACBTI features. + * + * This function configures the Pointer Authentication, and Branch Target + * Identification security features as per the user configuration. It returns + * the value of the special purpose CONTROL register accordingly, and optionally + * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M + * architecture based) target supports PACBTI security feature. + * + * @param xWriteControlRegister Used to control whether the special purpose + * CONTROL register should be updated or not. + * + * @return CONTROL register value according to the configured PACBTI option. + */ + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the system call stack so that upon returning from + * SVC, the system call stack is used. + * + * @param pulTaskStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + * @param ucSystemCallNumber The system call number of the system call. + */ + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Raise SVC for exiting from a system call. + */ + void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief This variable is set to pdTRUE when the scheduler is started. + */ + PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + + /** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +/** + * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + /** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + + /** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + + /** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the cpsid instruction + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessPermissions = 0; + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_ONLY ) + { + ulAccessPermissions = tskMPU_READ_PERMISSION; + } + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_WRITE ) + { + ulAccessPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION ); + } + + return ulAccessPermissions; + } + +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } + +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ portOFFSET_TO_PC ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ]; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulSystemCallStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the system call section (i.e. application is + * not raising SVC directly). + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as + * it is non-NULL only during the execution of a system call (i.e. + * between system call enter and exit). + * 3. System call is not for a kernel API disabled by the configuration + * in FreeRTOSConfig.h. + * 4. We do not need to check that ucSystemCallNumber is within range + * because the assembly SVC handler checks that before calling + * this function. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) && + ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) ) + { + pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the system call stack for the stack frame. */ + pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulSystemCallStack[ i ] = pulTaskStack[ i ]; + } + + /* Store the value of the Link Register before the SVC was raised. + * It contains the address of the caller of the System Call entry + * point (i.e. the caller of the MPU_). We need to restore it + * when we exit from the system call. */ + pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; + + /* Store the value of the PSPLIM register before the SVC was raised. + * We need to restore it when we exit from the system call. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* Use the pulSystemCallStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif + + /* Start executing the system call upon returning from this handler. */ + pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; + + /* Raise a request to exit from the system call upon finishing the + * system call. */ + pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; + + /* Remember the location where we should copy the stack frame when we exit from + * the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize; + + /* Record if the hardware used padding to force the stack pointer + * to be double word aligned. */ + if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK ) + { + pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG; + } + else + { + pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG ); + } + + /* We ensure in pxPortInitialiseStack that the system call stack is + * double word aligned and therefore, there is no need of padding. + * Clear the bit[9] of stacked xPSR. */ + pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + + /* Raise the privilege for the duration of the system call. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " bics r0, r1 \n" /* Clear nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */ + { + __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulTaskStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the privileged code (i.e. application is not + * raising SVC directly). This SVC is only raised from + * vRequestSystemCallExit which is in the privileged code section. + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL - + * this means that we previously entered a system call and the + * application is not attempting to exit without entering a system + * call. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) ) + { + pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the task stack for the stack frame. */ + pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulTaskStack[ i ] = pulSystemCallStack[ i ]; + } + + /* Use the pulTaskStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) ); + + /* Return to the caller of the System Call entry point (i.e. the + * caller of the MPU_). */ + pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + /* Ensure that LR has a valid value.*/ + pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + + /* Restore the PSPLIM register to what it was at the time of + * system call entry. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* If the hardware used padding to force the stack pointer + * to be double word aligned, set the stacked xPSR bit[9], + * otherwise clear it. */ + if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG ) + { + pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK; + } + else + { + pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + } + + /* This is not NULL only for the duration of the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; + + /* Drop the privilege before returning to the thread mode. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " orrs r0, r1 \n" /* Set nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xTaskIsPrivileged = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xTaskIsPrivileged = pdTRUE; + } + + return xTaskIsPrivileged; + } + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged, + xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulIndex = 0; + uint32_t ulControl = 0x0; + + xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ + ulIndex++; + + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + ulIndex++; + + #if ( configENABLE_TRUSTZONE == 1 ) + { + xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */ + ulIndex++; + } + #endif /* configENABLE_TRUSTZONE */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + ulIndex++; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Check PACBTI security feature configuration before pushing the + * CONTROL register's value on task's TCB. */ + ulControl = prvConfigurePACBTI( pdFALSE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + if( xRunPrivileged == pdTRUE ) + { + xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + else + { + xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG ); + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ + ulIndex++; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + { + /* Ensure that the system call stack is double word aligned. */ + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) + + ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + /* This is not NULL only for the duration of a system call. */ + xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL; + } + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ]; + ulIndex++; + } + } + #endif /* configENABLE_PAC */ + + return &( xMPUSettings->ulContext[ ulIndex ] ); + } + +#else /* configENABLE_MPU */ + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ + { + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + pxTopOfStack--; + *pxTopOfStack = ulTaskPacKey[ i ]; + } + } + #endif /* configENABLE_PAC */ + + return pxTopOfStack; + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Set the CONTROL register value based on PACBTI security feature + * configuration before starting the first task. */ + ( void ) prvConfigurePACBTI( pdTRUE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + { + xSchedulerRunning = pdTRUE; + } + #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + configSTACK_DEPTH_TYPE uxStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( uxStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* PXN. */ + #if ( portARMV8M_MINOR_VERSION >= 1 ) + { + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ); + } + } + #endif /* portARMV8M_MINOR_VERSION >= 1 */ + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, + uint32_t ulBufferLength, + uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */ + + { + uint32_t i, ulBufferStartAddress, ulBufferEndAddress; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE ) + { + ulBufferStartAddress = ( uint32_t ) pvBuffer; + ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL ); + + for( i = 0; i < portTOTAL_NUM_REGIONS; i++ ) + { + /* Is the MPU region enabled? */ + if( ( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR & portMPU_RLAR_REGION_ENABLE ) == portMPU_RLAR_REGION_ENABLE ) + { + if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_AUTHORIZED( ulAccessRequested, + prvGetRegionAccessPermissions( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ) ) ) + { + xAccessGranted = pdTRUE; + break; + } + } + } + } + } + + return xAccessGranted; + } + +#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings; + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else + { + xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 ) + { + xAccessGranted = pdTRUE; + } + } + } + + return xAccessGranted; + } + + #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + ( void ) lInternalIndexOfKernelObject; + + /* If Access Control List feature is not used, all the tasks have + * access to all the kernel objects. */ + return pdTRUE; + } + + #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + { + uint32_t ulControl = 0x0; + + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); + + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; + + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c new file mode 100644 index 000000000..bc7bb6071 --- /dev/null +++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c @@ -0,0 +1,524 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION + * is defined correctly and privileged functions are placed in correct sections. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Portasm includes. */ +#include "portasm.h" + +/* System call numbers includes. */ +#include "mpu_syscall_numbers.h" + +/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the + * header files. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#if ( configENABLE_MPU == 1 ) + + void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " program_mpu_first_task: \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */ + " \n" + " dmb \n" /* Complete outstanding transfers before disabling MPU. */ + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + " str r2, [r1] \n" /* Disable MPU. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */ + " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r1, [r2] \n" /* Program MAIR0. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " \n" + " movs r3, #4 \n" /* r3 = 4. */ + " str r3, [r1] \n" /* Program RNR = 4. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + " \n" + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " orr r2, #1 \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */ + " str r2, [r1] \n" /* Enable MPU. */ + " dsb \n" /* Force memory writes before continuing. */ + " \n" + " restore_context_first_task: \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/ + " ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */ + " \n" + " restore_special_regs_first_task: \n" + #if ( configENABLE_PAC == 1 ) + " ldmdb r1!, {r2-r5} \n" /* Read task's dedicated PAC key from the task's context. */ + " msr PAC_KEY_P_0, r2 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_1, r3 \n" + " msr PAC_KEY_P_2, r4 \n" + " msr PAC_KEY_P_3, r5 \n" + " clrm {r2-r5} \n" /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + " ldmdb r1!, {r2-r4, lr} \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */ + " msr psp, r2 \n" + " msr psplim, r3 \n" + " msr control, r4 \n" + " \n" + " restore_general_regs_first_task: \n" + " ldmdb r1!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */ + " stmia r2!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */ + " ldmdb r1!, {r4-r11} \n" /* r4-r11 restored. */ + " \n" + " restore_context_done_first_task: \n" + " str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */ + " mov r0, #0 \n" + " msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */ + " bx lr \n" + ); + } + +#else /* configENABLE_MPU */ + + void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + " ldr r0, [r1] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + " \n" + #if ( configENABLE_PAC == 1 ) + " ldmia r0!, {r1-r4} \n" /* Read task's dedicated PAC key from stack. */ + " msr PAC_KEY_P_3, r1 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_2, r2 \n" + " msr PAC_KEY_P_1, r3 \n" + " msr PAC_KEY_P_0, r4 \n" + " clrm {r1-r4} \n" /* Clear r1-r4. */ + #endif /* configENABLE_PAC */ + " \n" + " ldm r0!, {r1-r2} \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */ + " msr psplim, r1 \n" /* Set this task's PSPLIM value. */ + " mrs r1, control \n" /* Obtain current control register value. */ + " orrs r1, r1, #2 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */ + " msr control, r1 \n" /* Write back the new control register value. */ + " adds r0, #32 \n" /* Discard everything up to r0. */ + " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */ + " isb \n" + " mov r0, #0 \n" + " msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */ + " bx r2 \n" /* Finally, branch to EXC_RETURN. */ + ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* r0 = CONTROL. */ + " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + " ite ne \n" + " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + " bx lr \n" /* Return. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* Read the CONTROL register. */ + " bic r0, #1 \n" /* Clear the bit 0. */ + " msr control, r0 \n" /* Write back the new CONTROL value. */ + " bx lr \n" /* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vResetPrivilege( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* r0 = CONTROL. */ + " orr r0, #1 \n" /* r0 = r0 | 1. */ + " msr control, r0 \n" /* CONTROL = r0. */ + " bx lr \n" /* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r0, =0xe000ed08 \n" /* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */ + " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */ + " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */ + " cpsie i \n" /* Globally enable interrupts. */ + " cpsie f \n" + " dsb \n" + " isb \n" + " svc %0 \n" /* System call to start the first task. */ + " nop \n" + ::"i" ( portSVC_START_SCHEDULER ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, basepri \n" /* r0 = basepri. Return original basepri value. */ + " mov r1, %0 \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r1 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bx lr \n" /* Return. */ + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " msr basepri, r0 \n" /* basepri = ulMask. */ + " dsb \n" + " isb \n" + " bx lr \n" /* Return. */ + ::: "memory" + ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */ + " ldr r1, [r0] \n" /* r1 = Location in TCB where the context should be saved. */ + " mrs r2, psp \n" /* r2 = PSP. */ + " \n" + " save_general_regs: \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " add r2, r2, #0x20 \n" /* Move r2 to location where s0 is saved. */ + " tst lr, #0x10 \n" + " ittt eq \n" + " vstmiaeq r1!, {s16-s31} \n" /* Store s16-s31. */ + " vldmiaeq r2, {s0-s16} \n" /* Copy hardware saved FP context into s0-s16. */ + " vstmiaeq r1!, {s0-s16} \n" /* Store hardware saved FP context. */ + " sub r2, r2, #0x20 \n" /* Set r2 back to the location of hardware saved context. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " stmia r1!, {r4-r11} \n" /* Store r4-r11. */ + " ldmia r2, {r4-r11} \n" /* Copy the hardware saved context into r4-r11. */ + " stmia r1!, {r4-r11} \n" /* Store the hardware saved context. */ + " \n" + " save_special_regs: \n" + " mrs r3, psplim \n" /* r3 = PSPLIM. */ + " mrs r4, control \n" /* r4 = CONTROL. */ + " stmia r1!, {r2-r4, lr} \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ + #if ( configENABLE_PAC == 1 ) + " mrs r2, PAC_KEY_P_0 \n" /* Read task's dedicated PAC key from the PAC key registers. */ + " mrs r3, PAC_KEY_P_1 \n" + " mrs r4, PAC_KEY_P_2 \n" + " mrs r5, PAC_KEY_P_3 \n" + " stmia r1!, {r2-r5} \n" /* Store the task's dedicated PAC key on the task's context. */ + " clrm {r2-r5} \n" /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + " str r1, [r0] \n" /* Save the location from where the context should be restored as the first member of TCB. */ + " \n" + " select_next_task: \n" + " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bl vTaskSwitchContext \n" + " mov r0, #0 \n" /* r0 = 0. */ + " msr basepri, r0 \n" /* Enable interrupts. */ + " \n" + " program_mpu: \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */ + " \n" + " dmb \n" /* Complete outstanding transfers before disabling MPU. */ + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + " str r2, [r1] \n" /* Disable MPU. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */ + " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r1, [r2] \n" /* Program MAIR0. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " \n" + " movs r3, #4 \n" /* r3 = 4. */ + " str r3, [r1] \n" /* Program RNR = 4. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + " \n" + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " orr r2, #1 \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */ + " str r2, [r1] \n" /* Enable MPU. */ + " dsb \n" /* Force memory writes before continuing. */ + " \n" + " restore_context: \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/ + " ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */ + " \n" + " restore_special_regs: \n" + #if ( configENABLE_PAC == 1 ) + " ldmdb r1!, {r2-r5} \n" /* Read task's dedicated PAC key from the task's context. */ + " msr PAC_KEY_P_0, r2 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_1, r3 \n" + " msr PAC_KEY_P_2, r4 \n" + " msr PAC_KEY_P_3, r5 \n" + " clrm {r2-r5} \n" /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + " ldmdb r1!, {r2-r4, lr} \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */ + " msr psp, r2 \n" + " msr psplim, r3 \n" + " msr control, r4 \n" + " \n" + " restore_general_regs: \n" + " ldmdb r1!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */ + " stmia r2!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */ + " ldmdb r1!, {r4-r11} \n" /* r4-r11 restored. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" + " ittt eq \n" + " vldmdbeq r1!, {s0-s16} \n" /* s0-s16 contain hardware saved FP context. */ + " vstmiaeq r2!, {s0-s16} \n" /* Copy hardware saved FP context on the task stack. */ + " vldmdbeq r1!, {s16-s31} \n" /* Restore s16-s31. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + " restore_context_done: \n" + " str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */ + " bx lr \n" + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); + } + +#else /* configENABLE_MPU */ + + void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, psp \n" /* Read PSP in r0. */ + " \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vstmdbeq r0!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + " mrs r2, psplim \n" /* r2 = PSPLIM. */ + " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */ + " stmdb r0!, {r2-r11} \n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */ + " \n" + #if ( configENABLE_PAC == 1 ) + " mrs r1, PAC_KEY_P_3 \n" /* Read task's dedicated PAC key from the PAC key registers. */ + " mrs r2, PAC_KEY_P_2 \n" + " mrs r3, PAC_KEY_P_1 \n" + " mrs r4, PAC_KEY_P_0 \n" + " stmdb r0!, {r1-r4} \n" /* Store the task's dedicated PAC key on the stack. */ + " clrm {r1-r4} \n" /* Clear r1-r4. */ + #endif /* configENABLE_PAC */ + " \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + " str r0, [r1] \n" /* Save the new top of stack in TCB. */ + " \n" + " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bl vTaskSwitchContext \n" + " mov r0, #0 \n" /* r0 = 0. */ + " msr basepri, r0 \n" /* Enable interrupts. */ + " \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ + " \n" + #if ( configENABLE_PAC == 1 ) + " ldmia r0!, {r2-r5} \n" /* Read task's dedicated PAC key from stack. */ + " msr PAC_KEY_P_3, r2 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_2, r3 \n" + " msr PAC_KEY_P_1, r4 \n" + " msr PAC_KEY_P_0, r5 \n" + " clrm {r2-r5} \n" /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + " \n" + " ldmia r0!, {r2-r11} \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */ + " \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst r3, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vldmiaeq r0!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */ + " msr psp, r0 \n" /* Remember the new top of stack for the task. */ + " bx r3 \n" + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + ".syntax unified \n" + ".extern vPortSVCHandler_C \n" + ".extern vSystemCallEnter \n" + ".extern vSystemCallExit \n" + " \n" + "tst lr, #4 \n" + "ite eq \n" + "mrseq r0, msp \n" + "mrsne r0, psp \n" + " \n" + "ldr r1, [r0, #24] \n" + "ldrb r2, [r1, #-2] \n" + "cmp r2, %0 \n" + "blt syscall_enter \n" + "cmp r2, %1 \n" + "beq syscall_exit \n" + "b vPortSVCHandler_C \n" + " \n" + "syscall_enter: \n" + " mov r1, lr \n" + " b vSystemCallEnter \n" + " \n" + "syscall_exit: \n" + " mov r1, lr \n" + " b vSystemCallExit \n" + " \n" + : /* No outputs. */ + : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT ) + : "r0", "r1", "r2", "memory" + ); + } + +#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " tst lr, #4 \n" + " ite eq \n" + " mrseq r0, msp \n" + " mrsne r0, psp \n" + " ldr r1, =vPortSVCHandler_C \n" + " bx r1 \n" + ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h b/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h new file mode 100644 index 000000000..b7021b024 --- /dev/null +++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kernel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h new file mode 100644 index 000000000..2d435ca0b --- /dev/null +++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h @@ -0,0 +1,81 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M33" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portARMV8M_MINOR_VERSION 0 +#define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +#ifndef configENABLE_MVE + #define configENABLE_MVE 0 +#elif ( configENABLE_MVE != 0 ) + #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M33. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h new file mode 100644 index 000000000..f373bcad5 --- /dev/null +++ b/portable/GCC/ARM_CM33_NTZ/non_secure/portmacrocommon.h @@ -0,0 +1,582 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACROCOMMON_H +#define PORTMACROCOMMON_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. +#endif /* configENABLE_FPU */ + +#ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. +#endif /* configENABLE_MPU */ + +#ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. +#endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() +#define portINLINE __inline +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif +#define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ +extern BaseType_t xPortIsInsideInterrupt( void ); + +extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + +extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; +extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + +extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; +extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + +#if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_PAC == 1 ) + + /** + * @brief Generates 128-bit task's random PAC key. + * + * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be + * filled with a 128-bit random number. + */ + void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); + +#endif /* configENABLE_PAC */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ +#if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) +#else + #define portPRIVILEGE_BIT ( 0x0UL ) +#endif /* configENABLE_MPU */ + +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ +#define portPRIVILEGED_FLASH_REGION ( 0UL ) +#define portUNPRIVILEGED_FLASH_REGION ( 1UL ) +#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) +#define portPRIVILEGED_RAM_REGION ( 3UL ) +#define portSTACK_REGION ( 4UL ) +#define portFIRST_CONFIGURABLE_REGION ( 5UL ) +#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) +#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) +#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ +#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ +#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ +#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ +#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ +#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ +#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ +#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) +#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) +#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + +#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) +#define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) +#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) +#define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + +#define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + #ifndef configSYSTEM_CALL_STACK_SIZE + #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. + #endif + + /** + * @brief System call stack. + */ + typedef struct SYSTEM_CALL_STACK_INFO + { + uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; + uint32_t * pulSystemCallStack; + uint32_t * pulSystemCallStackLimit; + uint32_t * pulTaskStack; + uint32_t ulLinkRegisterAtSystemCallEntry; + uint32_t ulStackLimitRegisterAtSystemCallEntry; + } xSYSTEM_CALL_STACK_INFO; + + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + /** + * @brief MPU settings as stored in the TCB. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><-----------><----> + * 16 17 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 71 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 17 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 55 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | | | PC, xPSR | EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><-----------><----> + * 16 17 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 70 + + #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + /* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 17 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 54 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+------------------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +----------+-----------------+------------------------------+------------+-----+ + * + * <---------><----------------><------------------------------><-----------><----> + * 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 38 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+----------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | PC, xPSR | EXC_RETURN | | | + * +----------+-----------------+----------------------+------------+-----+ + * + * <---------><----------------><----------------------><-----------><----> + * 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 37 + + #else /* #if( configENABLE_TRUSTZONE == 1 ) */ + + /* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) + + /* Size of an Access Control List (ACL) entry in bits. */ + #define portACL_ENTRY_SIZE_BITS ( 32U ) + + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + uint32_t ulContext[ MAX_CONTEXT_SIZE ]; + uint32_t ulTaskFlags; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo; + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ]; + #endif + #endif + } xMPU_SETTINGS; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Validate priority of ISRs that are allowed to call FreeRTOS + * system calls. + */ +#if ( configASSERT_DEFINED == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif +#endif + +/** + * @brief SVC numbers. + */ +#define portSVC_ALLOCATE_SECURE_CONTEXT 100 +#define portSVC_FREE_SECURE_CONTEXT 101 +#define portSVC_START_SCHEDULER 102 +#define portSVC_RAISE_PRIVILEGE 103 +#define portSVC_SYSTEM_CALL_EXIT 104 +#define portSVC_YIELD 105 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) +#endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() +#else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + extern BaseType_t xPortIsTaskPrivileged( void ); + +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACROCOMMON_H */ diff --git a/portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c new file mode 100644 index 000000000..33410a0c3 --- /dev/null +++ b/portable/GCC/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.c @@ -0,0 +1,2056 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" +#include "event_groups.h" +#include "stream_buffer.h" +#include "mpu_prototypes.h" +#include "mpu_syscall_numbers.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( INCLUDE_xTaskDelayUntil == 1 ) + + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskDelayUntilImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskDelayUntil_Unpriv \n" + " MPU_xTaskDelayUntil_Priv: \n" + " b MPU_xTaskDelayUntilImpl \n" + " MPU_xTaskDelayUntil_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskAbortDelayImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskAbortDelay_Unpriv \n" + " MPU_xTaskAbortDelay_Priv: \n" + " b MPU_xTaskAbortDelayImpl \n" + " MPU_xTaskAbortDelay_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskDelay == 1 ) + + void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskDelayImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskDelay_Unpriv \n" + " MPU_vTaskDelay_Priv: \n" + " b MPU_vTaskDelayImpl \n" + " MPU_vTaskDelay_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskPriorityGet == 1 ) + + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskPriorityGetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskPriorityGet_Unpriv \n" + " MPU_uxTaskPriorityGet_Priv: \n" + " b MPU_uxTaskPriorityGetImpl \n" + " MPU_uxTaskPriorityGet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_eTaskGetState == 1 ) + + eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_eTaskGetStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_eTaskGetState_Unpriv \n" + " MPU_eTaskGetState_Priv: \n" + " b MPU_eTaskGetStateImpl \n" + " MPU_eTaskGetState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory" + ); + } + + #endif /* if ( INCLUDE_eTaskGetState == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskGetInfoImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskGetInfo_Unpriv \n" + " MPU_vTaskGetInfo_Priv: \n" + " b MPU_vTaskGetInfoImpl \n" + " MPU_vTaskGetInfo_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory" + ); + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) + + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetIdleTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetIdleTaskHandle_Unpriv \n" + " MPU_xTaskGetIdleTaskHandle_Priv: \n" + " b MPU_xTaskGetIdleTaskHandleImpl \n" + " MPU_xTaskGetIdleTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + + void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSuspendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSuspend_Unpriv \n" + " MPU_vTaskSuspend_Priv: \n" + " b MPU_vTaskSuspendImpl \n" + " MPU_vTaskSuspend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + + void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskResumeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskResume_Unpriv \n" + " MPU_vTaskResume_Priv: \n" + " b MPU_vTaskResumeImpl \n" + " MPU_vTaskResume_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + TickType_t MPU_xTaskGetTickCount( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetTickCountImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetTickCount_Unpriv \n" + " MPU_xTaskGetTickCount_Priv: \n" + " b MPU_xTaskGetTickCountImpl \n" + " MPU_xTaskGetTickCount_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetNumberOfTasksImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetNumberOfTasks_Unpriv \n" + " MPU_uxTaskGetNumberOfTasks_Priv: \n" + " b MPU_uxTaskGetNumberOfTasksImpl \n" + " MPU_uxTaskGetNumberOfTasks_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetRunTimeCounterImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetRunTimeCounter_Unpriv \n" + " MPU_ulTaskGetRunTimeCounter_Priv: \n" + " b MPU_ulTaskGetRunTimeCounterImpl \n" + " MPU_ulTaskGetRunTimeCounter_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetRunTimePercentImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetRunTimePercent_Unpriv \n" + " MPU_ulTaskGetRunTimePercent_Priv: \n" + " b MPU_ulTaskGetRunTimePercentImpl \n" + " MPU_ulTaskGetRunTimePercent_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetIdleRunTimePercentImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv \n" + " MPU_ulTaskGetIdleRunTimePercent_Priv: \n" + " b MPU_ulTaskGetIdleRunTimePercentImpl \n" + " MPU_ulTaskGetIdleRunTimePercent_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetIdleRunTimeCounterImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv \n" + " MPU_ulTaskGetIdleRunTimeCounter_Priv: \n" + " b MPU_ulTaskGetIdleRunTimeCounterImpl \n" + " MPU_ulTaskGetIdleRunTimeCounter_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetApplicationTaskTagImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetApplicationTaskTag_Unpriv \n" + " MPU_vTaskSetApplicationTaskTag_Priv: \n" + " b MPU_vTaskSetApplicationTaskTagImpl \n" + " MPU_vTaskSetApplicationTaskTag_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory" + ); + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetApplicationTaskTagImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetApplicationTaskTag_Unpriv \n" + " MPU_xTaskGetApplicationTaskTag_Priv: \n" + " b MPU_xTaskGetApplicationTaskTagImpl \n" + " MPU_xTaskGetApplicationTaskTag_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory" + ); + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetThreadLocalStoragePointerImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv \n" + " MPU_vTaskSetThreadLocalStoragePointer_Priv: \n" + " b MPU_vTaskSetThreadLocalStoragePointerImpl \n" + " MPU_vTaskSetThreadLocalStoragePointer_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory" + ); + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv \n" + " MPU_pvTaskGetThreadLocalStoragePointer_Priv: \n" + " b MPU_pvTaskGetThreadLocalStoragePointerImpl \n" + " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory" + ); + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetSystemStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetSystemState_Unpriv \n" + " MPU_uxTaskGetSystemState_Priv: \n" + " b MPU_uxTaskGetSystemStateImpl \n" + " MPU_uxTaskGetSystemState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory" + ); + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) + + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetStackHighWaterMarkImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetStackHighWaterMark_Unpriv \n" + " MPU_uxTaskGetStackHighWaterMark_Priv: \n" + " b MPU_uxTaskGetStackHighWaterMarkImpl \n" + " MPU_uxTaskGetStackHighWaterMark_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetStackHighWaterMark2Impl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv \n" + " MPU_uxTaskGetStackHighWaterMark2_Priv: \n" + " b MPU_uxTaskGetStackHighWaterMark2Impl \n" + " MPU_uxTaskGetStackHighWaterMark2_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) + + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetCurrentTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetCurrentTaskHandle_Unpriv \n" + " MPU_xTaskGetCurrentTaskHandle_Priv: \n" + " b MPU_xTaskGetCurrentTaskHandleImpl \n" + " MPU_xTaskGetCurrentTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory" + ); + } + + #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetSchedulerState == 1 ) + + BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetSchedulerStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetSchedulerState_Unpriv \n" + " MPU_xTaskGetSchedulerState_Priv: \n" + " b MPU_xTaskGetSchedulerStateImpl \n" + " MPU_xTaskGetSchedulerState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */ +/*-----------------------------------------------------------*/ + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetTimeOutStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetTimeOutState_Unpriv \n" + " MPU_vTaskSetTimeOutState_Priv: \n" + " b MPU_vTaskSetTimeOutStateImpl \n" + " MPU_vTaskSetTimeOutState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskCheckForTimeOutImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskCheckForTimeOut_Unpriv \n" + " MPU_xTaskCheckForTimeOut_Priv: \n" + " b MPU_xTaskCheckForTimeOutImpl \n" + " MPU_xTaskCheckForTimeOut_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotify_Unpriv \n" + " MPU_xTaskGenericNotify_Priv: \n" + " b MPU_xTaskGenericNotifyImpl \n" + " MPU_xTaskGenericNotify_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyWaitImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotifyWait_Unpriv \n" + " MPU_xTaskGenericNotifyWait_Priv: \n" + " b MPU_xTaskGenericNotifyWaitImpl \n" + " MPU_xTaskGenericNotifyWait_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGenericNotifyTakeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGenericNotifyTake_Unpriv \n" + " MPU_ulTaskGenericNotifyTake_Priv: \n" + " b MPU_ulTaskGenericNotifyTakeImpl \n" + " MPU_ulTaskGenericNotifyTake_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyStateClearImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotifyStateClear_Unpriv \n" + " MPU_xTaskGenericNotifyStateClear_Priv: \n" + " b MPU_xTaskGenericNotifyStateClearImpl \n" + " MPU_xTaskGenericNotifyStateClear_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGenericNotifyValueClearImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGenericNotifyValueClear_Unpriv \n" + " MPU_ulTaskGenericNotifyValueClear_Priv: \n" + " b MPU_ulTaskGenericNotifyValueClearImpl \n" + " MPU_ulTaskGenericNotifyValueClear_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGenericSendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGenericSend_Unpriv \n" + " MPU_xQueueGenericSend_Priv: \n" + " b MPU_xQueueGenericSendImpl \n" + " MPU_xQueueGenericSend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxQueueMessagesWaitingImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxQueueMessagesWaiting_Unpriv \n" + " MPU_uxQueueMessagesWaiting_Priv: \n" + " b MPU_uxQueueMessagesWaitingImpl \n" + " MPU_uxQueueMessagesWaiting_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxQueueSpacesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxQueueSpacesAvailable_Unpriv \n" + " MPU_uxQueueSpacesAvailable_Priv: \n" + " b MPU_uxQueueSpacesAvailableImpl \n" + " MPU_uxQueueSpacesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueReceiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueReceive_Unpriv \n" + " MPU_xQueueReceive_Priv: \n" + " b MPU_xQueueReceiveImpl \n" + " MPU_xQueueReceive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueuePeekImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueuePeek_Unpriv \n" + " MPU_xQueuePeek_Priv: \n" + " b MPU_xQueuePeekImpl \n" + " MPU_xQueuePeek_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueSemaphoreTakeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueSemaphoreTake_Unpriv \n" + " MPU_xQueueSemaphoreTake_Priv: \n" + " b MPU_xQueueSemaphoreTakeImpl \n" + " MPU_xQueueSemaphoreTake_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) + + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGetMutexHolderImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGetMutexHolder_Unpriv \n" + " MPU_xQueueGetMutexHolder_Priv: \n" + " b MPU_xQueueGetMutexHolderImpl \n" + " MPU_xQueueGetMutexHolder_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory" + ); + } + + #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueTakeMutexRecursiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueTakeMutexRecursive_Unpriv \n" + " MPU_xQueueTakeMutexRecursive_Priv: \n" + " b MPU_xQueueTakeMutexRecursiveImpl \n" + " MPU_xQueueTakeMutexRecursive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory" + ); + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGiveMutexRecursiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGiveMutexRecursive_Unpriv \n" + " MPU_xQueueGiveMutexRecursive_Priv: \n" + " b MPU_xQueueGiveMutexRecursiveImpl \n" + " MPU_xQueueGiveMutexRecursive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory" + ); + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueSelectFromSetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueSelectFromSet_Unpriv \n" + " MPU_xQueueSelectFromSet_Priv: \n" + " b MPU_xQueueSelectFromSetImpl \n" + " MPU_xQueueSelectFromSet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory" + ); + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueAddToSetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueAddToSet_Unpriv \n" + " MPU_xQueueAddToSet_Priv: \n" + " b MPU_xQueueAddToSetImpl \n" + " MPU_xQueueAddToSet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory" + ); + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vQueueAddToRegistryImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vQueueAddToRegistry_Unpriv \n" + " MPU_vQueueAddToRegistry_Priv: \n" + " b MPU_vQueueAddToRegistryImpl \n" + " MPU_vQueueAddToRegistry_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vQueueUnregisterQueueImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vQueueUnregisterQueue_Unpriv \n" + " MPU_vQueueUnregisterQueue_Priv: \n" + " b MPU_vQueueUnregisterQueueImpl \n" + " MPU_vQueueUnregisterQueue_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pcQueueGetNameImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pcQueueGetName_Unpriv \n" + " MPU_pcQueueGetName_Priv: \n" + " b MPU_pcQueueGetNameImpl \n" + " MPU_pcQueueGetName_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pvTimerGetTimerIDImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pvTimerGetTimerID_Unpriv \n" + " MPU_pvTimerGetTimerID_Priv: \n" + " b MPU_pvTimerGetTimerIDImpl \n" + " MPU_pvTimerGetTimerID_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTimerSetTimerIDImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTimerSetTimerID_Unpriv \n" + " MPU_vTimerSetTimerID_Priv: \n" + " b MPU_vTimerSetTimerIDImpl \n" + " MPU_vTimerSetTimerID_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerIsTimerActiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerIsTimerActive_Unpriv \n" + " MPU_xTimerIsTimerActive_Priv: \n" + " b MPU_xTimerIsTimerActiveImpl \n" + " MPU_xTimerIsTimerActive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv \n" + " MPU_xTimerGetTimerDaemonTaskHandle_Priv: \n" + " b MPU_xTimerGetTimerDaemonTaskHandleImpl \n" + " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGenericCommandFromTaskImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGenericCommandFromTask_Unpriv \n" + " MPU_xTimerGenericCommandFromTask_Priv: \n" + " b MPU_xTimerGenericCommandFromTaskImpl \n" + " MPU_xTimerGenericCommandFromTask_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pcTimerGetNameImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pcTimerGetName_Unpriv \n" + " MPU_pcTimerGetName_Priv: \n" + " b MPU_pcTimerGetNameImpl \n" + " MPU_pcTimerGetName_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTimerSetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTimerSetReloadMode_Unpriv \n" + " MPU_vTimerSetReloadMode_Priv: \n" + " b MPU_vTimerSetReloadModeImpl \n" + " MPU_vTimerSetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetReloadMode_Unpriv \n" + " MPU_xTimerGetReloadMode_Priv: \n" + " b MPU_xTimerGetReloadModeImpl \n" + " MPU_xTimerGetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTimerGetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTimerGetReloadMode_Unpriv \n" + " MPU_uxTimerGetReloadMode_Priv: \n" + " b MPU_uxTimerGetReloadModeImpl \n" + " MPU_uxTimerGetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetPeriodImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetPeriod_Unpriv \n" + " MPU_xTimerGetPeriod_Priv: \n" + " b MPU_xTimerGetPeriodImpl \n" + " MPU_xTimerGetPeriod_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetExpiryTimeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetExpiryTime_Unpriv \n" + " MPU_xTimerGetExpiryTime_Priv: \n" + " b MPU_xTimerGetExpiryTimeImpl \n" + " MPU_xTimerGetExpiryTime_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupWaitBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupWaitBits_Unpriv \n" + " MPU_xEventGroupWaitBits_Priv: \n" + " b MPU_xEventGroupWaitBitsImpl \n" + " MPU_xEventGroupWaitBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupClearBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupClearBits_Unpriv \n" + " MPU_xEventGroupClearBits_Priv: \n" + " b MPU_xEventGroupClearBitsImpl \n" + " MPU_xEventGroupClearBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupSetBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupSetBits_Unpriv \n" + " MPU_xEventGroupSetBits_Priv: \n" + " b MPU_xEventGroupSetBitsImpl \n" + " MPU_xEventGroupSetBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ + +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupSyncImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupSync_Unpriv \n" + " MPU_xEventGroupSync_Priv: \n" + " b MPU_xEventGroupSyncImpl \n" + " MPU_xEventGroupSync_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxEventGroupGetNumberImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxEventGroupGetNumber_Unpriv \n" + " MPU_uxEventGroupGetNumber_Priv: \n" + " b MPU_uxEventGroupGetNumberImpl \n" + " MPU_uxEventGroupGetNumber_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory" + ); + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vEventGroupSetNumberImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vEventGroupSetNumber_Unpriv \n" + " MPU_vEventGroupSetNumber_Priv: \n" + " b MPU_vEventGroupSetNumberImpl \n" + " MPU_vEventGroupSetNumber_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory" + ); + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferSend_Unpriv \n" + " MPU_xStreamBufferSend_Priv: \n" + " b MPU_xStreamBufferSendImpl \n" + " MPU_xStreamBufferSend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferReceiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferReceive_Unpriv \n" + " MPU_xStreamBufferReceive_Priv: \n" + " b MPU_xStreamBufferReceiveImpl \n" + " MPU_xStreamBufferReceive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferIsFullImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferIsFull_Unpriv \n" + " MPU_xStreamBufferIsFull_Priv: \n" + " b MPU_xStreamBufferIsFullImpl \n" + " MPU_xStreamBufferIsFull_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferIsEmptyImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferIsEmpty_Unpriv \n" + " MPU_xStreamBufferIsEmpty_Priv: \n" + " b MPU_xStreamBufferIsEmptyImpl \n" + " MPU_xStreamBufferIsEmpty_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSpacesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferSpacesAvailable_Unpriv \n" + " MPU_xStreamBufferSpacesAvailable_Priv: \n" + " b MPU_xStreamBufferSpacesAvailableImpl \n" + " MPU_xStreamBufferSpacesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferBytesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferBytesAvailable_Unpriv \n" + " MPU_xStreamBufferBytesAvailable_Priv: \n" + " b MPU_xStreamBufferBytesAvailableImpl \n" + " MPU_xStreamBufferBytesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSetTriggerLevelImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferSetTriggerLevel_Unpriv \n" + " MPU_xStreamBufferSetTriggerLevel_Priv: \n" + " b MPU_xStreamBufferSetTriggerLevelImpl \n" + " MPU_xStreamBufferSetTriggerLevel_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferNextMessageLengthBytesImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv \n" + " MPU_xStreamBufferNextMessageLengthBytes_Priv: \n" + " b MPU_xStreamBufferNextMessageLengthBytesImpl \n" + " MPU_xStreamBufferNextMessageLengthBytes_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ diff --git a/portable/GCC/ARM_CM35P/non_secure/port.c b/portable/GCC/ARM_CM35P/non_secure/port.c new file mode 100644 index 000000000..76d2b2445 --- /dev/null +++ b/portable/GCC/ARM_CM35P/non_secure/port.c @@ -0,0 +1,2280 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024-2025 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU includes. */ +#include "mpu_wrappers.h" +#include "mpu_syscall_numbers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration settings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to check the validity of an interrupt priority. + */ +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) ) +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used during system call enter and exit. + */ +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Offsets in the stack to the parameters when inside the SVC handler. + */ +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +#if ( portARMV8M_MINOR_VERSION >= 1 ) + + /* Enable Privileged eXecute Never MPU attribute for the selected memory + * region. */ + #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL ) +#endif /* portARMV8M_MINOR_VERSION >= 1 */ + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Extract first address of the MPU region as encoded in the + * RBAR (Region Base Address Register) value. */ +#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \ + ( ( rbar ) & portMPU_RBAR_ADDRESS_MASK ) + +/* Extract last address of the MPU region as encoded in the + * RLAR (Region Limit Address Register) value. */ +#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \ + ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK ) + +/* Does addr lies within [start, end] address range? */ +#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \ + ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) ) + +/* Is the access request satisfied by the available permissions? */ +#define portIS_AUTHORIZED( accessRequest, permissions ) \ + ( ( ( permissions ) & ( accessRequest ) ) == accessRequest ) + +/* Max value that fits in a uint32_t type. */ +#define portUINT32_MAX ( ~( ( uint32_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. + */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 + +/** + * @brief Constants required to check and configure PACBTI security feature implementation. + */ +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) ) + + #define portCONTROL_UPAC_EN ( 1UL << 7UL ) + #define portCONTROL_PAC_EN ( 1UL << 6UL ) + #define portCONTROL_UBTI_EN ( 1UL << 5UL ) + #define portCONTROL_BTI_EN ( 1UL << 4UL ) + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Extract MPU region's access permissions from the Region Base Address + * Register (RBAR) value. + * + * @param ulRBARValue RBAR value for the MPU region. + * + * @return uint32_t Access permissions. + */ + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + + /** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + /** + * @brief Configures PACBTI features. + * + * This function configures the Pointer Authentication, and Branch Target + * Identification security features as per the user configuration. It returns + * the value of the special purpose CONTROL register accordingly, and optionally + * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M + * architecture based) target supports PACBTI security feature. + * + * @param xWriteControlRegister Used to control whether the special purpose + * CONTROL register should be updated or not. + * + * @return CONTROL register value according to the configured PACBTI option. + */ + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the system call stack so that upon returning from + * SVC, the system call stack is used. + * + * @param pulTaskStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + * @param ucSystemCallNumber The system call number of the system call. + */ + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Raise SVC for exiting from a system call. + */ + void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief This variable is set to pdTRUE when the scheduler is started. + */ + PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + + /** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +/** + * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + /** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + + /** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + + /** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the cpsid instruction + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessPermissions = 0; + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_ONLY ) + { + ulAccessPermissions = tskMPU_READ_PERMISSION; + } + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_WRITE ) + { + ulAccessPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION ); + } + + return ulAccessPermissions; + } + +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } + +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ portOFFSET_TO_PC ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ]; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulSystemCallStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the system call section (i.e. application is + * not raising SVC directly). + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as + * it is non-NULL only during the execution of a system call (i.e. + * between system call enter and exit). + * 3. System call is not for a kernel API disabled by the configuration + * in FreeRTOSConfig.h. + * 4. We do not need to check that ucSystemCallNumber is within range + * because the assembly SVC handler checks that before calling + * this function. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) && + ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) ) + { + pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the system call stack for the stack frame. */ + pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulSystemCallStack[ i ] = pulTaskStack[ i ]; + } + + /* Store the value of the Link Register before the SVC was raised. + * It contains the address of the caller of the System Call entry + * point (i.e. the caller of the MPU_). We need to restore it + * when we exit from the system call. */ + pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; + + /* Store the value of the PSPLIM register before the SVC was raised. + * We need to restore it when we exit from the system call. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* Use the pulSystemCallStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif + + /* Start executing the system call upon returning from this handler. */ + pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; + + /* Raise a request to exit from the system call upon finishing the + * system call. */ + pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; + + /* Remember the location where we should copy the stack frame when we exit from + * the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize; + + /* Record if the hardware used padding to force the stack pointer + * to be double word aligned. */ + if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK ) + { + pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG; + } + else + { + pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG ); + } + + /* We ensure in pxPortInitialiseStack that the system call stack is + * double word aligned and therefore, there is no need of padding. + * Clear the bit[9] of stacked xPSR. */ + pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + + /* Raise the privilege for the duration of the system call. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " bics r0, r1 \n" /* Clear nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */ + { + __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulTaskStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the privileged code (i.e. application is not + * raising SVC directly). This SVC is only raised from + * vRequestSystemCallExit which is in the privileged code section. + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL - + * this means that we previously entered a system call and the + * application is not attempting to exit without entering a system + * call. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) ) + { + pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the task stack for the stack frame. */ + pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulTaskStack[ i ] = pulSystemCallStack[ i ]; + } + + /* Use the pulTaskStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) ); + + /* Return to the caller of the System Call entry point (i.e. the + * caller of the MPU_). */ + pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + /* Ensure that LR has a valid value.*/ + pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + + /* Restore the PSPLIM register to what it was at the time of + * system call entry. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* If the hardware used padding to force the stack pointer + * to be double word aligned, set the stacked xPSR bit[9], + * otherwise clear it. */ + if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG ) + { + pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK; + } + else + { + pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + } + + /* This is not NULL only for the duration of the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; + + /* Drop the privilege before returning to the thread mode. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " orrs r0, r1 \n" /* Set nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xTaskIsPrivileged = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xTaskIsPrivileged = pdTRUE; + } + + return xTaskIsPrivileged; + } + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged, + xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulIndex = 0; + uint32_t ulControl = 0x0; + + xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ + ulIndex++; + + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + ulIndex++; + + #if ( configENABLE_TRUSTZONE == 1 ) + { + xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */ + ulIndex++; + } + #endif /* configENABLE_TRUSTZONE */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + ulIndex++; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Check PACBTI security feature configuration before pushing the + * CONTROL register's value on task's TCB. */ + ulControl = prvConfigurePACBTI( pdFALSE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + if( xRunPrivileged == pdTRUE ) + { + xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + else + { + xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG ); + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ + ulIndex++; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + { + /* Ensure that the system call stack is double word aligned. */ + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) + + ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + /* This is not NULL only for the duration of a system call. */ + xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL; + } + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ]; + ulIndex++; + } + } + #endif /* configENABLE_PAC */ + + return &( xMPUSettings->ulContext[ ulIndex ] ); + } + +#else /* configENABLE_MPU */ + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ + { + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + pxTopOfStack--; + *pxTopOfStack = ulTaskPacKey[ i ]; + } + } + #endif /* configENABLE_PAC */ + + return pxTopOfStack; + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Set the CONTROL register value based on PACBTI security feature + * configuration before starting the first task. */ + ( void ) prvConfigurePACBTI( pdTRUE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + { + xSchedulerRunning = pdTRUE; + } + #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + configSTACK_DEPTH_TYPE uxStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( uxStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* PXN. */ + #if ( portARMV8M_MINOR_VERSION >= 1 ) + { + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ); + } + } + #endif /* portARMV8M_MINOR_VERSION >= 1 */ + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, + uint32_t ulBufferLength, + uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */ + + { + uint32_t i, ulBufferStartAddress, ulBufferEndAddress; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE ) + { + ulBufferStartAddress = ( uint32_t ) pvBuffer; + ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL ); + + for( i = 0; i < portTOTAL_NUM_REGIONS; i++ ) + { + /* Is the MPU region enabled? */ + if( ( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR & portMPU_RLAR_REGION_ENABLE ) == portMPU_RLAR_REGION_ENABLE ) + { + if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_AUTHORIZED( ulAccessRequested, + prvGetRegionAccessPermissions( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ) ) ) + { + xAccessGranted = pdTRUE; + break; + } + } + } + } + } + + return xAccessGranted; + } + +#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings; + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else + { + xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 ) + { + xAccessGranted = pdTRUE; + } + } + } + + return xAccessGranted; + } + + #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + ( void ) lInternalIndexOfKernelObject; + + /* If Access Control List feature is not used, all the tasks have + * access to all the kernel objects. */ + return pdTRUE; + } + + #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + { + uint32_t ulControl = 0x0; + + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); + + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; + + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM35P/non_secure/portasm.c b/portable/GCC/ARM_CM35P/non_secure/portasm.c new file mode 100644 index 000000000..0ebbe48a4 --- /dev/null +++ b/portable/GCC/ARM_CM35P/non_secure/portasm.c @@ -0,0 +1,621 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION + * is defined correctly and privileged functions are placed in correct sections. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Portasm includes. */ +#include "portasm.h" + +/* System call numbers includes. */ +#include "mpu_syscall_numbers.h" + +/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the + * header files. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#if ( configENABLE_MPU == 1 ) + + void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " program_mpu_first_task: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r3] \n" /* r0 = pxCurrentTCB. */ + " \n" + " dmb \n" /* Complete outstanding transfers before disabling MPU. */ + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + " str r2, [r1] \n" /* Disable MPU. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */ + " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r1, [r2] \n" /* Program MAIR0. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " \n" + " movs r3, #4 \n" /* r3 = 4. */ + " str r3, [r1] \n" /* Program RNR = 4. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + " \n" + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " orr r2, #1 \n" /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */ + " str r2, [r1] \n" /* Enable MPU. */ + " dsb \n" /* Force memory writes before continuing. */ + " \n" + " restore_context_first_task: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* r1 = pxCurrentTCB.*/ + " ldr r2, [r1] \n" /* r2 = Location of saved context in TCB. */ + " \n" + " restore_special_regs_first_task: \n" + #if ( configENABLE_PAC == 1 ) + " ldmdb r2!, {r3-r6} \n" /* Read task's dedicated PAC key from the task's context. */ + " msr PAC_KEY_P_0, r3 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_1, r4 \n" + " msr PAC_KEY_P_2, r5 \n" + " msr PAC_KEY_P_3, r6 \n" + " clrm {r3-r6} \n" /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + " ldmdb r2!, {r0, r3-r5, lr} \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */ + " msr psp, r3 \n" + " msr psplim, r4 \n" + " msr control, r5 \n" + " ldr r4, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " str r0, [r4] \n" /* Restore xSecureContext. */ + " \n" + " restore_general_regs_first_task: \n" + " ldmdb r2!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */ + " stmia r3!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */ + " ldmdb r2!, {r4-r11} \n" /* r4-r11 restored. */ + " \n" + " restore_context_done_first_task: \n" + " str r2, [r1] \n" /* Save the location where the context should be saved next as the first member of TCB. */ + " mov r0, #0 \n" + " msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */ + " bx lr \n" + ); + } + +#else /* configENABLE_MPU */ + + void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r3, [r2] \n" /* Read pxCurrentTCB. */ + " ldr r0, [r3] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + " \n" + #if ( configENABLE_PAC == 1 ) + " ldmia r0!, {r1-r4} \n" /* Read task's dedicated PAC key from stack. */ + " msr PAC_KEY_P_3, r1 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_2, r2 \n" + " msr PAC_KEY_P_1, r3 \n" + " msr PAC_KEY_P_0, r4 \n" + " clrm {r1-r4} \n" /* Clear r1-r4. */ + #endif /* configENABLE_PAC */ + " \n" + " ldm r0!, {r1-r3} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */ + " ldr r4, =xSecureContext \n" + " str r1, [r4] \n" /* Set xSecureContext to this task's value for the same. */ + " msr psplim, r2 \n" /* Set this task's PSPLIM value. */ + " mrs r1, control \n" /* Obtain current control register value. */ + " orrs r1, r1, #2 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */ + " msr control, r1 \n" /* Write back the new control register value. */ + " adds r0, #32 \n" /* Discard everything up to r0. */ + " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */ + " isb \n" + " mov r0, #0 \n" + " msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */ + " bx r3 \n" /* Finally, branch to EXC_RETURN. */ + ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* r0 = CONTROL. */ + " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + " ite ne \n" + " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + " bx lr \n" /* Return. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* Read the CONTROL register. */ + " bic r0, #1 \n" /* Clear the bit 0. */ + " msr control, r0 \n" /* Write back the new CONTROL value. */ + " bx lr \n" /* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vResetPrivilege( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* r0 = CONTROL. */ + " orr r0, #1 \n" /* r0 = r0 | 1. */ + " msr control, r0 \n" /* CONTROL = r0. */ + " bx lr \n" /* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r0, =0xe000ed08 \n" /* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */ + " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */ + " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */ + " cpsie i \n" /* Globally enable interrupts. */ + " cpsie f \n" + " dsb \n" + " isb \n" + " svc %0 \n" /* System call to start the first task. */ + " nop \n" + ::"i" ( portSVC_START_SCHEDULER ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, basepri \n" /* r0 = basepri. Return original basepri value. */ + " mov r1, %0 \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r1 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bx lr \n" /* Return. */ + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " msr basepri, r0 \n" /* basepri = ulMask. */ + " dsb \n" + " isb \n" + " bx lr \n" /* Return. */ + ::: "memory" + ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern SecureContext_SaveContext \n" + " .extern SecureContext_LoadContext \n" + " \n" + " ldr r3, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " ldr r0, [r3] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */ + " ldr r2, [r1] \n" /* r2 = Location in TCB where the context should be saved. */ + " \n" + " cbz r0, save_ns_context \n" /* No secure context to save. */ + " save_s_context: \n" + " push {r0-r2, lr} \n" + " bl SecureContext_SaveContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r0-r2, lr} \n" + " \n" + " save_ns_context: \n" + " mov r3, lr \n" /* r3 = LR (EXC_RETURN). */ + " lsls r3, r3, #25 \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bmi save_special_regs \n" /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + " \n" + " save_general_regs: \n" + " mrs r3, psp \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " add r3, r3, #0x20 \n" /* Move r3 to location where s0 is saved. */ + " tst lr, #0x10 \n" + " ittt eq \n" + " vstmiaeq r2!, {s16-s31} \n" /* Store s16-s31. */ + " vldmiaeq r3, {s0-s16} \n" /* Copy hardware saved FP context into s0-s16. */ + " vstmiaeq r2!, {s0-s16} \n" /* Store hardware saved FP context. */ + " sub r3, r3, #0x20 \n" /* Set r3 back to the location of hardware saved context. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " stmia r2!, {r4-r11} \n" /* Store r4-r11. */ + " ldmia r3, {r4-r11} \n" /* Copy the hardware saved context into r4-r11. */ + " stmia r2!, {r4-r11} \n" /* Store the hardware saved context. */ + " \n" + " save_special_regs: \n" + " mrs r3, psp \n" /* r3 = PSP. */ + " mrs r4, psplim \n" /* r4 = PSPLIM. */ + " mrs r5, control \n" /* r5 = CONTROL. */ + " stmia r2!, {r0, r3-r5, lr} \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ + #if ( configENABLE_PAC == 1 ) + " mrs r3, PAC_KEY_P_0 \n" /* Read task's dedicated PAC key from the PAC key registers. */ + " mrs r4, PAC_KEY_P_1 \n" + " mrs r5, PAC_KEY_P_2 \n" + " mrs r6, PAC_KEY_P_3 \n" + " stmia r2!, {r3-r6} \n" /* Store the task's dedicated PAC key on the task's context. */ + " clrm {r3-r6} \n" /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + " str r2, [r1] \n" /* Save the location from where the context should be restored as the first member of TCB. */ + " \n" + " select_next_task: \n" + " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bl vTaskSwitchContext \n" + " mov r0, #0 \n" /* r0 = 0. */ + " msr basepri, r0 \n" /* Enable interrupts. */ + " \n" + " program_mpu: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r3] \n" /* r0 = pxCurrentTCB.*/ + " \n" + " dmb \n" /* Complete outstanding transfers before disabling MPU. */ + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + " str r2, [r1] \n" /* Disable MPU. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */ + " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r1, [r2] \n" /* Program MAIR0. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " \n" + " movs r3, #4 \n" /* r3 = 4. */ + " str r3, [r1] \n" /* Program RNR = 4. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + " \n" + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " orr r2, #1 \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */ + " str r2, [r1] \n" /* Enable MPU. */ + " dsb \n" /* Force memory writes before continuing. */ + " \n" + " restore_context: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* r1 = pxCurrentTCB.*/ + " ldr r2, [r1] \n" /* r2 = Location of saved context in TCB. */ + " \n" + " restore_special_regs: \n" + #if ( configENABLE_PAC == 1 ) + " ldmdb r2!, {r3-r6} \n" /* Read task's dedicated PAC key from the task's context. */ + " msr PAC_KEY_P_0, r3 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_1, r4 \n" + " msr PAC_KEY_P_2, r5 \n" + " msr PAC_KEY_P_3, r6 \n" + " clrm {r3-r6} \n" /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + " ldmdb r2!, {r0, r3-r5, lr} \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */ + " msr psp, r3 \n" + " msr psplim, r4 \n" + " msr control, r5 \n" + " ldr r4, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " str r0, [r4] \n" /* Restore xSecureContext. */ + " cbz r0, restore_ns_context \n" /* No secure context to restore. */ + " \n" + " restore_s_context: \n" + " push {r1-r3, lr} \n" + " bl SecureContext_LoadContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r1-r3, lr} \n" + " \n" + " restore_ns_context: \n" + " mov r0, lr \n" /* r0 = LR (EXC_RETURN). */ + " lsls r0, r0, #25 \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bmi restore_context_done \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + " \n" + " restore_general_regs: \n" + " ldmdb r2!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */ + " stmia r3!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */ + " ldmdb r2!, {r4-r11} \n" /* r4-r11 restored. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" + " ittt eq \n" + " vldmdbeq r2!, {s0-s16} \n" /* s0-s16 contain hardware saved FP context. */ + " vstmiaeq r3!, {s0-s16} \n" /* Copy hardware saved FP context on the task stack. */ + " vldmdbeq r2!, {s16-s31} \n" /* Restore s16-s31. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + " restore_context_done: \n" + " str r2, [r1] \n" /* Save the location where the context should be saved next as the first member of TCB. */ + " bx lr \n" + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); + } + +#else /* configENABLE_MPU */ + + void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern SecureContext_SaveContext \n" + " .extern SecureContext_LoadContext \n" + " \n" + " ldr r3, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " ldr r0, [r3] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */ + " mrs r2, psp \n" /* Read PSP in r2. */ + " \n" + " cbz r0, save_ns_context \n" /* No secure context to save. */ + " save_s_context: \n" + " push {r0-r2, lr} \n" + " bl SecureContext_SaveContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r0-r2, lr} \n" + " \n" + " save_ns_context: \n" + " mov r3, lr \n" /* r3 = LR (EXC_RETURN). */ + " lsls r3, r3, #25 \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bmi save_special_regs \n" /* If r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used. */ + " \n" + " save_general_regs: \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vstmdbeq r2!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " stmdb r2!, {r4-r11} \n" /* Store the registers that are not saved automatically. */ + " \n" + " save_special_regs: \n" + " mrs r3, psplim \n" /* r3 = PSPLIM. */ + " stmdb r2!, {r0, r3, lr} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */ + #if ( configENABLE_PAC == 1 ) + " mrs r3, PAC_KEY_P_3 \n" /* Read task's dedicated PAC key from the PAC key registers. */ + " mrs r4, PAC_KEY_P_2 \n" + " mrs r5, PAC_KEY_P_1 \n" + " mrs r6, PAC_KEY_P_0 \n" + " stmdb r2!, {r3-r6} \n" /* Store the task's dedicated PAC key on the stack. */ + " clrm {r3-r6} \n" /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + " \n" + " str r2, [r1] \n" /* Save the new top of stack in TCB. */ + " \n" + " select_next_task: \n" + " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bl vTaskSwitchContext \n" + " mov r0, #0 \n" /* r0 = 0. */ + " msr basepri, r0 \n" /* Enable interrupts. */ + " \n" + " restore_context: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* Read pxCurrentTCB. */ + " ldr r2, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */ + " \n" + " restore_special_regs: \n" + #if ( configENABLE_PAC == 1 ) + " ldmia r2!, {r3-r6} \n" /* Read task's dedicated PAC key from stack. */ + " msr PAC_KEY_P_3, r3 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_2, r4 \n" + " msr PAC_KEY_P_1, r5 \n" + " msr PAC_KEY_P_0, r6 \n" + " clrm {r3-r6} \n" /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + " ldmia r2!, {r0, r3, lr} \n" /* Read from stack - r0 = xSecureContext, r3 = PSPLIM and LR restored. */ + " msr psplim, r3 \n" /* Restore the PSPLIM register value for the task. */ + " ldr r3, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " str r0, [r3] \n" /* Restore the task's xSecureContext. */ + " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */ + " \n" + " restore_s_context: \n" + " push {r1-r3, lr} \n" + " bl SecureContext_LoadContext \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r1-r3, lr} \n" + " \n" + " restore_ns_context: \n" + " mov r0, lr \n" /* r0 = LR (EXC_RETURN). */ + " lsls r0, r0, #25 \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bmi restore_context_done \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + " \n" + " restore_general_regs: \n" + " ldmia r2!, {r4-r11} \n" /* Restore the registers that are not automatically restored. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vldmiaeq r2!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + " restore_context_done: \n" + " msr psp, r2 \n" /* Remember the new top of stack for the task. */ + " bx lr \n" + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + ".syntax unified \n" + ".extern vPortSVCHandler_C \n" + ".extern vSystemCallEnter \n" + ".extern vSystemCallExit \n" + " \n" + "tst lr, #4 \n" + "ite eq \n" + "mrseq r0, msp \n" + "mrsne r0, psp \n" + " \n" + "ldr r1, [r0, #24] \n" + "ldrb r2, [r1, #-2] \n" + "cmp r2, %0 \n" + "blt syscall_enter \n" + "cmp r2, %1 \n" + "beq syscall_exit \n" + "b vPortSVCHandler_C \n" + " \n" + "syscall_enter: \n" + " mov r1, lr \n" + " b vSystemCallEnter \n" + " \n" + "syscall_exit: \n" + " mov r1, lr \n" + " b vSystemCallExit \n" + " \n" + : /* No outputs. */ + : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT ) + : "r0", "r1", "r2", "memory" + ); + } + +#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " tst lr, #4 \n" + " ite eq \n" + " mrseq r0, msp \n" + " mrsne r0, psp \n" + " ldr r1, =vPortSVCHandler_C \n" + " bx r1 \n" + ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " svc %0 \n" /* Secure context is allocated in the supervisor call. */ + " bx lr \n" /* Return. */ + ::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, [r0] \n" /* The first item in the TCB is the top of the stack. */ + " ldr r1, [r2] \n" /* The first item on the stack is the task's xSecureContext. */ + " cmp r1, #0 \n" /* Raise svc if task's xSecureContext is not NULL. */ + " it ne \n" + " svcne %0 \n" /* Secure context is freed in the supervisor call. */ + " bx lr \n" /* Return. */ + ::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory" + ); +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM35P/non_secure/portasm.h b/portable/GCC/ARM_CM35P/non_secure/portasm.h new file mode 100644 index 000000000..b7021b024 --- /dev/null +++ b/portable/GCC/ARM_CM35P/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kernel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/portable/GCC/ARM_CM35P/non_secure/portmacro.h b/portable/GCC/ARM_CM35P/non_secure/portmacro.h new file mode 100644 index 000000000..b886287ac --- /dev/null +++ b/portable/GCC/ARM_CM35P/non_secure/portmacro.h @@ -0,0 +1,81 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M35P" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portARMV8M_MINOR_VERSION 0 +#define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +#ifndef configENABLE_MVE + #define configENABLE_MVE 0 +#elif ( configENABLE_MVE != 0 ) + #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M35. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h new file mode 100644 index 000000000..f373bcad5 --- /dev/null +++ b/portable/GCC/ARM_CM35P/non_secure/portmacrocommon.h @@ -0,0 +1,582 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACROCOMMON_H +#define PORTMACROCOMMON_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. +#endif /* configENABLE_FPU */ + +#ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. +#endif /* configENABLE_MPU */ + +#ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. +#endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() +#define portINLINE __inline +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif +#define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ +extern BaseType_t xPortIsInsideInterrupt( void ); + +extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + +extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; +extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + +extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; +extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + +#if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_PAC == 1 ) + + /** + * @brief Generates 128-bit task's random PAC key. + * + * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be + * filled with a 128-bit random number. + */ + void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); + +#endif /* configENABLE_PAC */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ +#if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) +#else + #define portPRIVILEGE_BIT ( 0x0UL ) +#endif /* configENABLE_MPU */ + +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ +#define portPRIVILEGED_FLASH_REGION ( 0UL ) +#define portUNPRIVILEGED_FLASH_REGION ( 1UL ) +#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) +#define portPRIVILEGED_RAM_REGION ( 3UL ) +#define portSTACK_REGION ( 4UL ) +#define portFIRST_CONFIGURABLE_REGION ( 5UL ) +#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) +#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) +#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ +#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ +#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ +#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ +#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ +#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ +#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ +#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) +#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) +#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + +#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) +#define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) +#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) +#define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + +#define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + #ifndef configSYSTEM_CALL_STACK_SIZE + #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. + #endif + + /** + * @brief System call stack. + */ + typedef struct SYSTEM_CALL_STACK_INFO + { + uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; + uint32_t * pulSystemCallStack; + uint32_t * pulSystemCallStackLimit; + uint32_t * pulTaskStack; + uint32_t ulLinkRegisterAtSystemCallEntry; + uint32_t ulStackLimitRegisterAtSystemCallEntry; + } xSYSTEM_CALL_STACK_INFO; + + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + /** + * @brief MPU settings as stored in the TCB. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><-----------><----> + * 16 17 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 71 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 17 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 55 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | | | PC, xPSR | EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><-----------><----> + * 16 17 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 70 + + #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + /* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 17 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 54 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+------------------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +----------+-----------------+------------------------------+------------+-----+ + * + * <---------><----------------><------------------------------><-----------><----> + * 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 38 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+----------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | PC, xPSR | EXC_RETURN | | | + * +----------+-----------------+----------------------+------------+-----+ + * + * <---------><----------------><----------------------><-----------><----> + * 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 37 + + #else /* #if( configENABLE_TRUSTZONE == 1 ) */ + + /* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) + + /* Size of an Access Control List (ACL) entry in bits. */ + #define portACL_ENTRY_SIZE_BITS ( 32U ) + + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + uint32_t ulContext[ MAX_CONTEXT_SIZE ]; + uint32_t ulTaskFlags; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo; + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ]; + #endif + #endif + } xMPU_SETTINGS; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Validate priority of ISRs that are allowed to call FreeRTOS + * system calls. + */ +#if ( configASSERT_DEFINED == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif +#endif + +/** + * @brief SVC numbers. + */ +#define portSVC_ALLOCATE_SECURE_CONTEXT 100 +#define portSVC_FREE_SECURE_CONTEXT 101 +#define portSVC_START_SCHEDULER 102 +#define portSVC_RAISE_PRIVILEGE 103 +#define portSVC_SYSTEM_CALL_EXIT 104 +#define portSVC_YIELD 105 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) +#endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() +#else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + extern BaseType_t xPortIsTaskPrivileged( void ); + +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACROCOMMON_H */ diff --git a/portable/GCC/ARM_CM35P/secure/secure_context.c b/portable/GCC/ARM_CM35P/secure/secure_context.c new file mode 100644 index 000000000..3aa335e63 --- /dev/null +++ b/portable/GCC/ARM_CM35P/secure/secure_context.c @@ -0,0 +1,354 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Secure context includes. */ +#include "secure_context.h" + +/* Secure heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief CONTROL value for privileged tasks. + * + * Bit[0] - 0 --> Thread mode is privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_PRIVILEGED 0x02 + +/** + * @brief CONTROL value for un-privileged tasks. + * + * Bit[0] - 1 --> Thread mode is un-privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03 + +/** + * @brief Size of stack seal values in bytes. + */ +#define securecontextSTACK_SEAL_SIZE 8 + +/** + * @brief Stack seal value as recommended by ARM. + */ +#define securecontextSTACK_SEAL_VALUE 0xFEF5EDA5 + +/** + * @brief Maximum number of secure contexts. + */ +#ifndef secureconfigMAX_SECURE_CONTEXTS + #define secureconfigMAX_SECURE_CONTEXTS 8UL +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Pre-allocated array of secure contexts. + */ +SecureContext_t xSecureContexts[ secureconfigMAX_SECURE_CONTEXTS ]; +/*-----------------------------------------------------------*/ + +/** + * @brief Get a free secure context for a task from the secure context pool (xSecureContexts). + * + * This function ensures that only one secure context is allocated for a task. + * + * @param[in] pvTaskHandle The task handle for which the secure context is allocated. + * + * @return Index of a free secure context in the xSecureContexts array. + */ +static uint32_t ulGetSecureContext( void * pvTaskHandle ); + +/** + * @brief Return the secure context to the secure context pool (xSecureContexts). + * + * @param[in] ulSecureContextIndex Index of the context in the xSecureContexts array. + */ +static void vReturnSecureContext( uint32_t ulSecureContextIndex ); + +/* These are implemented in assembly. */ +extern void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ); +extern void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ); +/*-----------------------------------------------------------*/ + +static uint32_t ulGetSecureContext( void * pvTaskHandle ) +{ + /* Start with invalid index. */ + uint32_t i, ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + if( ( xSecureContexts[ i ].pucCurrentStackPointer == NULL ) && + ( xSecureContexts[ i ].pucStackLimit == NULL ) && + ( xSecureContexts[ i ].pucStackStart == NULL ) && + ( xSecureContexts[ i ].pvTaskHandle == NULL ) && + ( ulSecureContextIndex == secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = i; + } + else if( xSecureContexts[ i ].pvTaskHandle == pvTaskHandle ) + { + /* A task can only have one secure context. Do not allocate a second + * context for the same task. */ + ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + break; + } + } + + return ulSecureContextIndex; +} +/*-----------------------------------------------------------*/ + +static void vReturnSecureContext( uint32_t ulSecureContextIndex ) +{ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackStart = NULL; + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = NULL; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) +{ + uint32_t ulIPSR, i; + static uint32_t ulSecureContextsInitialized = 0; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ( ulIPSR != 0 ) && ( ulSecureContextsInitialized == 0 ) ) + { + /* Ensure to initialize secure contexts only once. */ + ulSecureContextsInitialized = 1; + + /* No stack for thread mode until a task's context is loaded. */ + secureportSET_PSPLIM( securecontextNO_STACK ); + secureportSET_PSP( securecontextNO_STACK ); + + /* Initialize all secure contexts. */ + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + xSecureContexts[ i ].pucCurrentStackPointer = NULL; + xSecureContexts[ i ].pucStackLimit = NULL; + xSecureContexts[ i ].pucStackStart = NULL; + xSecureContexts[ i ].pvTaskHandle = NULL; + } + + #if ( configENABLE_MPU == 1 ) + { + /* Configure thread mode to use PSP and to be unprivileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); + } + #else /* configENABLE_MPU */ + { + /* Configure thread mode to use PSP and to be privileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); + } + #endif /* configENABLE_MPU */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ) +#else /* configENABLE_MPU */ + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ) +#endif /* configENABLE_MPU */ +{ + uint8_t * pucStackMemory = NULL; + uint8_t * pucStackLimit; + uint32_t ulIPSR, ulSecureContextIndex; + SecureContextHandle_t xSecureContextHandle = securecontextINVALID_CONTEXT_ID; + + #if ( configENABLE_MPU == 1 ) + uint32_t * pulCurrentStackPointer = NULL; + #endif /* configENABLE_MPU */ + + /* Read the Interrupt Program Status Register (IPSR) and Process Stack Limit + * Register (PSPLIM) value. */ + secureportREAD_IPSR( ulIPSR ); + secureportREAD_PSPLIM( pucStackLimit ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. + * Also do nothing, if a secure context us already loaded. PSPLIM is set to + * securecontextNO_STACK when no secure context is loaded. */ + if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) ) + { + /* Obtain a free secure context. */ + ulSecureContextIndex = ulGetSecureContext( pvTaskHandle ); + + /* Were we able to get a free context? */ + if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS ) + { + /* Allocate the stack space. */ + pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + + if( pucStackMemory != NULL ) + { + /* Since stack grows down, the starting point will be the last + * location. Note that this location is next to the last + * allocated byte for stack (excluding the space for seal values) + * because the hardware decrements the stack pointer before + * writing i.e. if stack pointer is 0x2, a push operation will + * decrement the stack pointer to 0x1 and then write at 0x1. */ + xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize; + + /* Seal the created secure process stack. */ + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; + + /* The stack cannot go beyond this location. This value is + * programmed in the PSPLIM register on context switch.*/ + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = pucStackMemory; + + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle; + + #if ( configENABLE_MPU == 1 ) + { + /* Store the correct CONTROL value for the task on the stack. + * This value is programmed in the CONTROL register on + * context switch. */ + pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; + pulCurrentStackPointer--; + + if( ulIsTaskPrivileged ) + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; + } + else + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; + } + + /* Store the current stack pointer. This value is programmed in + * the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + } + #else /* configENABLE_MPU */ + { + /* Current SP is set to the starting of the stack. This + * value programmed in the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + } + #endif /* configENABLE_MPU */ + + /* Ensure to never return 0 as a valid context handle. */ + xSecureContextHandle = ulSecureContextIndex + 1UL; + } + } + } + + return xSecureContextHandle; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) +{ + uint32_t ulIPSR, ulSecureContextIndex; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* Only free if a valid context handle is passed. */ + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + /* Ensure that the secure context being deleted is associated with + * the task. */ + if( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) + { + /* Free the stack space. */ + vPortFree( xSecureContexts[ ulSecureContextIndex ].pucStackLimit ); + + /* Return the secure context back to the free secure contexts pool. */ + vReturnSecureContext( ulSecureContextIndex ); + } + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that no secure context is loaded and the task is loading it's + * own context. */ + if( ( pucStackLimit == securecontextNO_STACK ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_LoadContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that task's context is loaded and the task is saving it's own + * context. */ + if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_SaveContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM35P/secure/secure_context.h b/portable/GCC/ARM_CM35P/secure/secure_context.h new file mode 100644 index 000000000..e36a8e430 --- /dev/null +++ b/portable/GCC/ARM_CM35P/secure/secure_context.h @@ -0,0 +1,138 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_CONTEXT_H__ +#define __SECURE_CONTEXT_H__ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" + +/** + * @brief PSP value when no secure context is loaded. + */ +#define securecontextNO_STACK 0x0 + +/** + * @brief Invalid context ID. + */ +#define securecontextINVALID_CONTEXT_ID 0UL +/*-----------------------------------------------------------*/ + +/** + * @brief Structure to represent a secure context. + * + * @note Since stack grows down, pucStackStart is the highest address while + * pucStackLimit is the first address of the allocated memory. + */ +typedef struct SecureContext +{ + uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */ + uint8_t * pucStackLimit; /**< Last location of the stack memory (PSPLIM). */ + uint8_t * pucStackStart; /**< First location of the stack memory. */ + void * pvTaskHandle; /**< Task handle of the task this context is associated with. */ +} SecureContext_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Opaque handle for a secure context. + */ +typedef uint32_t SecureContextHandle_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Initializes the secure context management system. + * + * PSP is set to NULL and therefore a task must allocate and load a context + * before calling any secure side function in the thread mode. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureContext_Init( void ); + +/** + * @brief Allocates a context on the secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] ulSecureStackSize Size of the stack to allocate on secure side. + * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise. + * + * @return Opaque context handle if context is successfully allocated, NULL + * otherwise. + */ +#if ( configENABLE_MPU == 1 ) + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ); +#else /* configENABLE_MPU */ + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ); +#endif /* configENABLE_MPU */ + +/** + * @brief Frees the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the + * context to be freed. + */ +void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); + +/** + * @brief Loads the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be loaded. + */ +void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); + +/** + * @brief Saves the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be saved. + */ +void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); + +#endif /* __SECURE_CONTEXT_H__ */ diff --git a/portable/GCC/ARM_CM35P/secure/secure_context_port.c b/portable/GCC/ARM_CM35P/secure/secure_context_port.c new file mode 100644 index 000000000..2d3d9439d --- /dev/null +++ b/portable/GCC/ARM_CM35P/secure/secure_context_port.c @@ -0,0 +1,97 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Secure context includes. */ +#include "secure_context.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) ); +void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) ); + +void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) +{ + /* pxSecureContext value is in r0. */ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r1, ipsr \n" /* r1 = IPSR. */ + " cbz r1, load_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */ + " ldmia r0!, {r1, r2} \n" /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */ + " \n" + #if ( configENABLE_MPU == 1 ) + " ldmia r1!, {r3} \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */ + " msr control, r3 \n" /* CONTROL = r3. */ + #endif /* configENABLE_MPU */ + " \n" + " msr psplim, r2 \n" /* PSPLIM = r2. */ + " msr psp, r1 \n" /* PSP = r1. */ + " \n" + " load_ctx_therad_mode: \n" + " bx lr \n" + " \n" + ::: "r0", "r1", "r2" + ); +} +/*-----------------------------------------------------------*/ + +void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) +{ + /* pxSecureContext value is in r0. */ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r1, ipsr \n" /* r1 = IPSR. */ + " cbz r1, save_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */ + " mrs r1, psp \n" /* r1 = PSP. */ + " \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " vstmdb r1!, {s0} \n" /* Trigger the deferred stacking of FPU registers. */ + " vldmia r1!, {s0} \n" /* Nullify the effect of the previous statement. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + #if ( configENABLE_MPU == 1 ) + " mrs r2, control \n" /* r2 = CONTROL. */ + " stmdb r1!, {r2} \n" /* Store CONTROL value on the stack. */ + #endif /* configENABLE_MPU */ + " \n" + " str r1, [r0] \n" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */ + " movs r1, %0 \n" /* r1 = securecontextNO_STACK. */ + " msr psplim, r1 \n" /* PSPLIM = securecontextNO_STACK. */ + " msr psp, r1 \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */ + " \n" + " save_ctx_therad_mode: \n" + " bx lr \n" + " \n" + ::"i" ( securecontextNO_STACK ) : "r1", "memory" + ); +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM35P/secure/secure_heap.c b/portable/GCC/ARM_CM35P/secure/secure_heap.c new file mode 100644 index 000000000..896b53e2d --- /dev/null +++ b/portable/GCC/ARM_CM35P/secure/secure_heap.c @@ -0,0 +1,485 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Configuration includes. */ +#include "FreeRTOSConfig.h" + +/* Secure context heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Total heap size. + */ +#ifndef secureconfigTOTAL_HEAP_SIZE + #define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) ) +#endif + +/* No test marker by default. */ +#ifndef mtCOVERAGE_TEST_MARKER + #define mtCOVERAGE_TEST_MARKER() +#endif + +/* No tracing by default. */ +#ifndef traceMALLOC + #define traceMALLOC( pvReturn, xWantedSize ) +#endif + +/* No tracing by default. */ +#ifndef traceFREE + #define traceFREE( pv, xBlockSize ) +#endif + +/* Block sizes must not get too small. */ +#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) ) + +/* Assumes 8bit bytes! */ +#define secureheapBITS_PER_BYTE ( ( size_t ) 8 ) + +/* Max value that fits in a size_t type. */ +#define secureheapSIZE_MAX ( ~( ( size_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define secureheapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) ) + +/* MSB of the xBlockSize member of an BlockLink_t structure is used to track + * the allocation status of a block. When MSB of the xBlockSize member of + * an BlockLink_t structure is set then the block belongs to the application. + * When the bit is free the block is still part of the free heap space. */ +#define secureheapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) ) +#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 ) +#define secureheapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 ) +#define secureheapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK ) +#define secureheapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK ) +/*-----------------------------------------------------------*/ + +/* Allocate the memory for the heap. */ +#if ( configAPPLICATION_ALLOCATED_HEAP == 1 ) + +/* The application writer has already defined the array used for the RTOS +* heap - probably so it can be placed in a special segment or address. */ + extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#else /* configAPPLICATION_ALLOCATED_HEAP */ + static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#endif /* configAPPLICATION_ALLOCATED_HEAP */ + +/** + * @brief The linked list structure. + * + * This is used to link free blocks in order of their memory address. + */ +typedef struct A_BLOCK_LINK +{ + struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */ + size_t xBlockSize; /**< The size of the free block. */ +} BlockLink_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Called automatically to setup the required heap structures the first + * time pvPortMalloc() is called. + */ +static void prvHeapInit( void ); + +/** + * @brief Inserts a block of memory that is being freed into the correct + * position in the list of free memory blocks. + * + * The block being freed will be merged with the block in front it and/or the + * block behind it if the memory blocks are adjacent to each other. + * + * @param[in] pxBlockToInsert The block being freed. + */ +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ); +/*-----------------------------------------------------------*/ + +/** + * @brief The size of the structure placed at the beginning of each allocated + * memory block must by correctly byte aligned. + */ +static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + +/** + * @brief Create a couple of list links to mark the start and end of the list. + */ +static BlockLink_t xStart; +static BlockLink_t * pxEnd = NULL; + +/** + * @brief Keeps track of the number of free bytes remaining, but says nothing + * about fragmentation. + */ +static size_t xFreeBytesRemaining = 0U; +static size_t xMinimumEverFreeBytesRemaining = 0U; + +/*-----------------------------------------------------------*/ + +static void prvHeapInit( void ) +{ + BlockLink_t * pxFirstFreeBlock; + uint8_t * pucAlignedHeap; + size_t uxAddress; + size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE; + + /* Ensure the heap starts on a correctly aligned boundary. */ + uxAddress = ( size_t ) ucHeap; + + if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 ) + { + uxAddress += ( secureportBYTE_ALIGNMENT - 1 ); + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; + } + + pucAlignedHeap = ( uint8_t * ) uxAddress; + + /* xStart is used to hold a pointer to the first item in the list of free + * blocks. The void cast is used to prevent compiler warnings. */ + xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; + xStart.xBlockSize = ( size_t ) 0; + + /* pxEnd is used to mark the end of the list of free blocks and is inserted + * at the end of the heap space. */ + uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; + uxAddress -= xHeapStructSize; + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + pxEnd = ( void * ) uxAddress; + pxEnd->xBlockSize = 0; + pxEnd->pxNextFreeBlock = NULL; + + /* To start with there is a single free block that is sized to take up the + * entire heap space, minus the space taken by pxEnd. */ + pxFirstFreeBlock = ( void * ) pucAlignedHeap; + pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; + pxFirstFreeBlock->pxNextFreeBlock = pxEnd; + + /* Only one block exists - and it covers the entire usable heap space. */ + xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; +} +/*-----------------------------------------------------------*/ + +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) +{ + BlockLink_t * pxIterator; + uint8_t * puc; + + /* Iterate through the list until a block is found that has a higher address + * than the block being inserted. */ + for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) + { + /* Nothing to do here, just iterate to the right position. */ + } + + /* Do the block being inserted, and the block it is being inserted after + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxIterator; + + if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) + { + pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; + pxBlockToInsert = pxIterator; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Do the block being inserted, and the block it is being inserted before + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxBlockToInsert; + + if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) + { + if( pxIterator->pxNextFreeBlock != pxEnd ) + { + /* Form one big block from the two blocks. */ + pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxEnd; + } + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; + } + + /* If the block being inserted plugged a gap, so was merged with the block + * before and the block after, then it's pxNextFreeBlock pointer will have + * already been set, and should not be set here as that would make it point + * to itself. */ + if( pxIterator != pxBlockToInsert ) + { + pxIterator->pxNextFreeBlock = pxBlockToInsert; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} +/*-----------------------------------------------------------*/ + +void * pvPortMalloc( size_t xWantedSize ) +{ + BlockLink_t * pxBlock; + BlockLink_t * pxPreviousBlock; + BlockLink_t * pxNewBlockLink; + void * pvReturn = NULL; + size_t xAdditionalRequiredSize; + size_t xAllocatedBlockSize = 0; + + /* If this is the first call to malloc then the heap will require + * initialisation to setup the list of free blocks. */ + if( pxEnd == NULL ) + { + prvHeapInit(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xWantedSize > 0 ) + { + /* The wanted size must be increased so it can contain a BlockLink_t + * structure in addition to the requested amount of bytes. */ + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 ) + { + xWantedSize += xHeapStructSize; + + /* Ensure that blocks are always aligned to the required number + * of bytes. */ + if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 ) + { + /* Byte alignment required. */ + xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ); + + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 ) + { + xWantedSize += xAdditionalRequiredSize; + } + else + { + xWantedSize = 0; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + xWantedSize = 0; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Check the requested block size is not so large that the top bit is set. + * The top bit of the block size member of the BlockLink_t structure is used + * to determine who owns the block - the application or the kernel, so it + * must be free. */ + if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 ) + { + if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) + { + /* Traverse the list from the start (lowest address) block until + * one of adequate size is found. */ + pxPreviousBlock = &xStart; + pxBlock = xStart.pxNextFreeBlock; + + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + { + pxPreviousBlock = pxBlock; + pxBlock = pxBlock->pxNextFreeBlock; + } + + /* If the end marker was reached then a block of adequate size was + * not found. */ + if( pxBlock != pxEnd ) + { + /* Return the memory space pointed to - jumping over the + * BlockLink_t structure at its start. */ + pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); + + /* This block is being returned for use so must be taken out + * of the list of free blocks. */ + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + + /* If the block is larger than required it can be split into + * two. */ + if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE ) + { + /* This block is to be split into two. Create a new + * block following the number of bytes requested. The void + * cast is used to prevent byte alignment warnings from the + * compiler. */ + pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); + secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + + /* Calculate the sizes of two blocks split from the single + * block. */ + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + pxBlock->xBlockSize = xWantedSize; + + /* Insert the new block into the list of free blocks. */ + pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock; + pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xFreeBytesRemaining -= pxBlock->xBlockSize; + + if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) + { + xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xAllocatedBlockSize = pxBlock->xBlockSize; + + /* The block is being returned - it is allocated and owned by + * the application and has no "next" block. */ + secureheapALLOCATE_BLOCK( pxBlock ); + pxBlock->pxNextFreeBlock = NULL; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceMALLOC( pvReturn, xAllocatedBlockSize ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xAllocatedBlockSize; + + #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) + { + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */ + + secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 ); + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void * pv ) +{ + uint8_t * puc = ( uint8_t * ) pv; + BlockLink_t * pxLink; + + if( pv != NULL ) + { + /* The memory being freed will have an BlockLink_t structure immediately + * before it. */ + puc -= xHeapStructSize; + + /* This casting is to keep the compiler from issuing warnings. */ + pxLink = ( void * ) puc; + + /* Check the block is actually allocated. */ + secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ); + secureportASSERT( pxLink->pxNextFreeBlock == NULL ); + + if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ) + { + if( pxLink->pxNextFreeBlock == NULL ) + { + /* The block is being returned to the heap - it is no longer + * allocated. */ + secureheapFREE_BLOCK( pxLink ); + + secureportDISABLE_NON_SECURE_INTERRUPTS(); + { + /* Add this block to the list of free blocks. */ + xFreeBytesRemaining += pxLink->xBlockSize; + traceFREE( pv, pxLink->xBlockSize ); + prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); + } + secureportENABLE_NON_SECURE_INTERRUPTS(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } +} +/*-----------------------------------------------------------*/ + +size_t xPortGetFreeHeapSize( void ) +{ + return xFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +size_t xPortGetMinimumEverFreeHeapSize( void ) +{ + return xMinimumEverFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM35P/secure/secure_heap.h b/portable/GCC/ARM_CM35P/secure/secure_heap.h new file mode 100644 index 000000000..0e84a9d9d --- /dev/null +++ b/portable/GCC/ARM_CM35P/secure/secure_heap.h @@ -0,0 +1,66 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_HEAP_H__ +#define __SECURE_HEAP_H__ + +/* Standard includes. */ +#include + +/** + * @brief Allocates memory from heap. + * + * @param[in] xWantedSize The size of the memory to be allocated. + * + * @return Pointer to the memory region if the allocation is successful, NULL + * otherwise. + */ +void * pvPortMalloc( size_t xWantedSize ); + +/** + * @brief Frees the previously allocated memory. + * + * @param[in] pv Pointer to the memory to be freed. + */ +void vPortFree( void * pv ); + +/** + * @brief Get the free heap size. + * + * @return Free heap size. + */ +size_t xPortGetFreeHeapSize( void ); + +/** + * @brief Get the minimum ever free heap size. + * + * @return Minimum ever free heap size. + */ +size_t xPortGetMinimumEverFreeHeapSize( void ); + +#endif /* __SECURE_HEAP_H__ */ diff --git a/portable/GCC/ARM_CM35P/secure/secure_init.c b/portable/GCC/ARM_CM35P/secure/secure_init.c new file mode 100644 index 000000000..c50d37668 --- /dev/null +++ b/portable/GCC/ARM_CM35P/secure/secure_init.c @@ -0,0 +1,106 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Secure init includes. */ +#include "secure_init.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Constants required to manipulate the SCB. + */ +#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */ +#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL ) +#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS ) +#define secureinitSCB_AIRCR_PRIS_POS ( 14UL ) +#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS ) + +/** + * @brief Constants required to manipulate the FPU. + */ +#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define secureinitFPCCR_LSPENS_POS ( 29UL ) +#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS ) +#define secureinitFPCCR_TS_POS ( 26UL ) +#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS ) + +#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */ +#define secureinitNSACR_CP10_POS ( 10UL ) +#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS ) +#define secureinitNSACR_CP11_POS ( 11UL ) +#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS ) +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) | + ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) | + ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK ); + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is + * permitted. CP11 should be programmed to the same value as CP10. */ + *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK ); + + /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures + * that we can enable/disable lazy stacking in port.c file. */ + *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK ); + + /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP + * registers (S16-S31) are also pushed to stack on exception entry and + * restored on exception return. */ + *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK ); + } +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM35P/secure/secure_init.h b/portable/GCC/ARM_CM35P/secure/secure_init.h new file mode 100644 index 000000000..ebe04900f --- /dev/null +++ b/portable/GCC/ARM_CM35P/secure/secure_init.h @@ -0,0 +1,54 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_INIT_H__ +#define __SECURE_INIT_H__ + +/** + * @brief De-prioritizes the non-secure exceptions. + * + * This is needed to ensure that the non-secure PendSV runs at the lowest + * priority. Context switch is done in the non-secure PendSV handler. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_DePrioritizeNSExceptions( void ); + +/** + * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access. + * + * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point + * Registers are not leaked to the non-secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_EnableNSFPUAccess( void ); + +#endif /* __SECURE_INIT_H__ */ diff --git a/portable/GCC/ARM_CM35P/secure/secure_port_macros.h b/portable/GCC/ARM_CM35P/secure/secure_port_macros.h new file mode 100644 index 000000000..a70da2c65 --- /dev/null +++ b/portable/GCC/ARM_CM35P/secure/secure_port_macros.h @@ -0,0 +1,140 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_PORT_MACROS_H__ +#define __SECURE_PORT_MACROS_H__ + +/** + * @brief Byte alignment requirements. + */ +#define secureportBYTE_ALIGNMENT 8 +#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 ) + +/** + * @brief Macro to declare a function as non-secure callable. + */ +#if defined( __IAR_SYSTEMS_ICC__ ) + #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry __root +#else + #define secureportNON_SECURE_CALLABLE __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) ) +#endif + +/** + * @brief Set the secure PRIMASK value. + */ +#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Set the non-secure PRIMASK value. + */ +#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Read the PSP value in the given variable. + */ +#define secureportREAD_PSP( pucOutCurrentStackPointer ) \ + __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) ) + +/** + * @brief Set the PSP to the given value. + */ +#define secureportSET_PSP( pucCurrentStackPointer ) \ + __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) ) + +/** + * @brief Read the PSPLIM value in the given variable. + */ +#define secureportREAD_PSPLIM( pucOutStackLimit ) \ + __asm volatile ( "mrs %0, psplim" : "=r" ( pucOutStackLimit ) ) + +/** + * @brief Set the PSPLIM to the given value. + */ +#define secureportSET_PSPLIM( pucStackLimit ) \ + __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) ) + +/** + * @brief Set the NonSecure MSP to the given value. + */ +#define secureportSET_MSP_NS( pucMainStackPointer ) \ + __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) ) + +/** + * @brief Set the CONTROL register to the given value. + */ +#define secureportSET_CONTROL( ulControl ) \ + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" ) + +/** + * @brief Read the Interrupt Program Status Register (IPSR) value in the given + * variable. + */ +#define secureportREAD_IPSR( ulIPSR ) \ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) ) + +/** + * @brief PRIMASK value to enable interrupts. + */ +#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0 + +/** + * @brief PRIMASK value to disable interrupts. + */ +#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1 + +/** + * @brief Disable secure interrupts. + */ +#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Disable non-secure interrupts. + * + * This effectively disables context switches. + */ +#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Enable non-secure interrupts. + */ +#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL ) + +/** + * @brief Assert definition. + */ +#define secureportASSERT( x ) \ + if( ( x ) == 0 ) \ + { \ + secureportDISABLE_SECURE_INTERRUPTS(); \ + secureportDISABLE_NON_SECURE_INTERRUPTS(); \ + for( ; ; ) {; } \ + } + +#endif /* __SECURE_PORT_MACROS_H__ */ diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c new file mode 100644 index 000000000..4b984932d --- /dev/null +++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.c @@ -0,0 +1,2055 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" +#include "event_groups.h" +#include "stream_buffer.h" +#include "mpu_prototypes.h" +#include "mpu_syscall_numbers.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( INCLUDE_xTaskDelayUntil == 1 ) + + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskDelayUntilImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskDelayUntil_Unpriv \n" + " MPU_xTaskDelayUntil_Priv: \n" + " b MPU_xTaskDelayUntilImpl \n" + " MPU_xTaskDelayUntil_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskAbortDelayImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskAbortDelay_Unpriv \n" + " MPU_xTaskAbortDelay_Priv: \n" + " b MPU_xTaskAbortDelayImpl \n" + " MPU_xTaskAbortDelay_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskDelay == 1 ) + + void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskDelayImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskDelay_Unpriv \n" + " MPU_vTaskDelay_Priv: \n" + " b MPU_vTaskDelayImpl \n" + " MPU_vTaskDelay_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskPriorityGet == 1 ) + + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskPriorityGetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskPriorityGet_Unpriv \n" + " MPU_uxTaskPriorityGet_Priv: \n" + " b MPU_uxTaskPriorityGetImpl \n" + " MPU_uxTaskPriorityGet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_eTaskGetState == 1 ) + + eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_eTaskGetStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_eTaskGetState_Unpriv \n" + " MPU_eTaskGetState_Priv: \n" + " b MPU_eTaskGetStateImpl \n" + " MPU_eTaskGetState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory" + ); + } + + #endif /* if ( INCLUDE_eTaskGetState == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskGetInfoImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskGetInfo_Unpriv \n" + " MPU_vTaskGetInfo_Priv: \n" + " b MPU_vTaskGetInfoImpl \n" + " MPU_vTaskGetInfo_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory" + ); + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) + + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetIdleTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetIdleTaskHandle_Unpriv \n" + " MPU_xTaskGetIdleTaskHandle_Priv: \n" + " b MPU_xTaskGetIdleTaskHandleImpl \n" + " MPU_xTaskGetIdleTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + + void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSuspendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSuspend_Unpriv \n" + " MPU_vTaskSuspend_Priv: \n" + " b MPU_vTaskSuspendImpl \n" + " MPU_vTaskSuspend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + + void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskResumeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskResume_Unpriv \n" + " MPU_vTaskResume_Priv: \n" + " b MPU_vTaskResumeImpl \n" + " MPU_vTaskResume_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + TickType_t MPU_xTaskGetTickCount( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetTickCountImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetTickCount_Unpriv \n" + " MPU_xTaskGetTickCount_Priv: \n" + " b MPU_xTaskGetTickCountImpl \n" + " MPU_xTaskGetTickCount_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetNumberOfTasksImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetNumberOfTasks_Unpriv \n" + " MPU_uxTaskGetNumberOfTasks_Priv: \n" + " b MPU_uxTaskGetNumberOfTasksImpl \n" + " MPU_uxTaskGetNumberOfTasks_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetRunTimeCounterImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetRunTimeCounter_Unpriv \n" + " MPU_ulTaskGetRunTimeCounter_Priv: \n" + " b MPU_ulTaskGetRunTimeCounterImpl \n" + " MPU_ulTaskGetRunTimeCounter_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetRunTimePercentImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetRunTimePercent_Unpriv \n" + " MPU_ulTaskGetRunTimePercent_Priv: \n" + " b MPU_ulTaskGetRunTimePercentImpl \n" + " MPU_ulTaskGetRunTimePercent_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetIdleRunTimePercentImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv \n" + " MPU_ulTaskGetIdleRunTimePercent_Priv: \n" + " b MPU_ulTaskGetIdleRunTimePercentImpl \n" + " MPU_ulTaskGetIdleRunTimePercent_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetIdleRunTimeCounterImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv \n" + " MPU_ulTaskGetIdleRunTimeCounter_Priv: \n" + " b MPU_ulTaskGetIdleRunTimeCounterImpl \n" + " MPU_ulTaskGetIdleRunTimeCounter_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetApplicationTaskTagImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetApplicationTaskTag_Unpriv \n" + " MPU_vTaskSetApplicationTaskTag_Priv: \n" + " b MPU_vTaskSetApplicationTaskTagImpl \n" + " MPU_vTaskSetApplicationTaskTag_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory" + ); + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetApplicationTaskTagImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetApplicationTaskTag_Unpriv \n" + " MPU_xTaskGetApplicationTaskTag_Priv: \n" + " b MPU_xTaskGetApplicationTaskTagImpl \n" + " MPU_xTaskGetApplicationTaskTag_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory" + ); + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetThreadLocalStoragePointerImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv \n" + " MPU_vTaskSetThreadLocalStoragePointer_Priv: \n" + " b MPU_vTaskSetThreadLocalStoragePointerImpl \n" + " MPU_vTaskSetThreadLocalStoragePointer_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory" + ); + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv \n" + " MPU_pvTaskGetThreadLocalStoragePointer_Priv: \n" + " b MPU_pvTaskGetThreadLocalStoragePointerImpl \n" + " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory" + ); + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetSystemStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetSystemState_Unpriv \n" + " MPU_uxTaskGetSystemState_Priv: \n" + " b MPU_uxTaskGetSystemStateImpl \n" + " MPU_uxTaskGetSystemState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory" + ); + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) + + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetStackHighWaterMarkImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetStackHighWaterMark_Unpriv \n" + " MPU_uxTaskGetStackHighWaterMark_Priv: \n" + " b MPU_uxTaskGetStackHighWaterMarkImpl \n" + " MPU_uxTaskGetStackHighWaterMark_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetStackHighWaterMark2Impl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv \n" + " MPU_uxTaskGetStackHighWaterMark2_Priv: \n" + " b MPU_uxTaskGetStackHighWaterMark2Impl \n" + " MPU_uxTaskGetStackHighWaterMark2_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) + + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetCurrentTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetCurrentTaskHandle_Unpriv \n" + " MPU_xTaskGetCurrentTaskHandle_Priv: \n" + " b MPU_xTaskGetCurrentTaskHandleImpl \n" + " MPU_xTaskGetCurrentTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory" + ); + } + + #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetSchedulerState == 1 ) + + BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetSchedulerStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetSchedulerState_Unpriv \n" + " MPU_xTaskGetSchedulerState_Priv: \n" + " b MPU_xTaskGetSchedulerStateImpl \n" + " MPU_xTaskGetSchedulerState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */ +/*-----------------------------------------------------------*/ + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetTimeOutStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetTimeOutState_Unpriv \n" + " MPU_vTaskSetTimeOutState_Priv: \n" + " b MPU_vTaskSetTimeOutStateImpl \n" + " MPU_vTaskSetTimeOutState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskCheckForTimeOutImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskCheckForTimeOut_Unpriv \n" + " MPU_xTaskCheckForTimeOut_Priv: \n" + " b MPU_xTaskCheckForTimeOutImpl \n" + " MPU_xTaskCheckForTimeOut_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotify_Unpriv \n" + " MPU_xTaskGenericNotify_Priv: \n" + " b MPU_xTaskGenericNotifyImpl \n" + " MPU_xTaskGenericNotify_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyWaitImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotifyWait_Unpriv \n" + " MPU_xTaskGenericNotifyWait_Priv: \n" + " b MPU_xTaskGenericNotifyWaitImpl \n" + " MPU_xTaskGenericNotifyWait_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGenericNotifyTakeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGenericNotifyTake_Unpriv \n" + " MPU_ulTaskGenericNotifyTake_Priv: \n" + " b MPU_ulTaskGenericNotifyTakeImpl \n" + " MPU_ulTaskGenericNotifyTake_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyStateClearImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotifyStateClear_Unpriv \n" + " MPU_xTaskGenericNotifyStateClear_Priv: \n" + " b MPU_xTaskGenericNotifyStateClearImpl \n" + " MPU_xTaskGenericNotifyStateClear_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGenericNotifyValueClearImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGenericNotifyValueClear_Unpriv \n" + " MPU_ulTaskGenericNotifyValueClear_Priv: \n" + " b MPU_ulTaskGenericNotifyValueClearImpl \n" + " MPU_ulTaskGenericNotifyValueClear_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGenericSendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGenericSend_Unpriv \n" + " MPU_xQueueGenericSend_Priv: \n" + " b MPU_xQueueGenericSendImpl \n" + " MPU_xQueueGenericSend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxQueueMessagesWaitingImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxQueueMessagesWaiting_Unpriv \n" + " MPU_uxQueueMessagesWaiting_Priv: \n" + " b MPU_uxQueueMessagesWaitingImpl \n" + " MPU_uxQueueMessagesWaiting_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxQueueSpacesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxQueueSpacesAvailable_Unpriv \n" + " MPU_uxQueueSpacesAvailable_Priv: \n" + " b MPU_uxQueueSpacesAvailableImpl \n" + " MPU_uxQueueSpacesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueReceiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueReceive_Unpriv \n" + " MPU_xQueueReceive_Priv: \n" + " b MPU_xQueueReceiveImpl \n" + " MPU_xQueueReceive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueuePeekImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueuePeek_Unpriv \n" + " MPU_xQueuePeek_Priv: \n" + " b MPU_xQueuePeekImpl \n" + " MPU_xQueuePeek_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueSemaphoreTakeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueSemaphoreTake_Unpriv \n" + " MPU_xQueueSemaphoreTake_Priv: \n" + " b MPU_xQueueSemaphoreTakeImpl \n" + " MPU_xQueueSemaphoreTake_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) + + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGetMutexHolderImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGetMutexHolder_Unpriv \n" + " MPU_xQueueGetMutexHolder_Priv: \n" + " b MPU_xQueueGetMutexHolderImpl \n" + " MPU_xQueueGetMutexHolder_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory" + ); + } + + #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueTakeMutexRecursiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueTakeMutexRecursive_Unpriv \n" + " MPU_xQueueTakeMutexRecursive_Priv: \n" + " b MPU_xQueueTakeMutexRecursiveImpl \n" + " MPU_xQueueTakeMutexRecursive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory" + ); + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGiveMutexRecursiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGiveMutexRecursive_Unpriv \n" + " MPU_xQueueGiveMutexRecursive_Priv: \n" + " b MPU_xQueueGiveMutexRecursiveImpl \n" + " MPU_xQueueGiveMutexRecursive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory" + ); + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueSelectFromSetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueSelectFromSet_Unpriv \n" + " MPU_xQueueSelectFromSet_Priv: \n" + " b MPU_xQueueSelectFromSetImpl \n" + " MPU_xQueueSelectFromSet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory" + ); + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueAddToSetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueAddToSet_Unpriv \n" + " MPU_xQueueAddToSet_Priv: \n" + " b MPU_xQueueAddToSetImpl \n" + " MPU_xQueueAddToSet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory" + ); + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vQueueAddToRegistryImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vQueueAddToRegistry_Unpriv \n" + " MPU_vQueueAddToRegistry_Priv: \n" + " b MPU_vQueueAddToRegistryImpl \n" + " MPU_vQueueAddToRegistry_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vQueueUnregisterQueueImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vQueueUnregisterQueue_Unpriv \n" + " MPU_vQueueUnregisterQueue_Priv: \n" + " b MPU_vQueueUnregisterQueueImpl \n" + " MPU_vQueueUnregisterQueue_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pcQueueGetNameImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pcQueueGetName_Unpriv \n" + " MPU_pcQueueGetName_Priv: \n" + " b MPU_pcQueueGetNameImpl \n" + " MPU_pcQueueGetName_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pvTimerGetTimerIDImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pvTimerGetTimerID_Unpriv \n" + " MPU_pvTimerGetTimerID_Priv: \n" + " b MPU_pvTimerGetTimerIDImpl \n" + " MPU_pvTimerGetTimerID_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTimerSetTimerIDImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTimerSetTimerID_Unpriv \n" + " MPU_vTimerSetTimerID_Priv: \n" + " b MPU_vTimerSetTimerIDImpl \n" + " MPU_vTimerSetTimerID_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerIsTimerActiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerIsTimerActive_Unpriv \n" + " MPU_xTimerIsTimerActive_Priv: \n" + " b MPU_xTimerIsTimerActiveImpl \n" + " MPU_xTimerIsTimerActive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv \n" + " MPU_xTimerGetTimerDaemonTaskHandle_Priv: \n" + " b MPU_xTimerGetTimerDaemonTaskHandleImpl \n" + " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGenericCommandFromTaskImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGenericCommandFromTask_Unpriv \n" + " MPU_xTimerGenericCommandFromTask_Priv: \n" + " b MPU_xTimerGenericCommandFromTaskImpl \n" + " MPU_xTimerGenericCommandFromTask_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pcTimerGetNameImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pcTimerGetName_Unpriv \n" + " MPU_pcTimerGetName_Priv: \n" + " b MPU_pcTimerGetNameImpl \n" + " MPU_pcTimerGetName_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTimerSetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTimerSetReloadMode_Unpriv \n" + " MPU_vTimerSetReloadMode_Priv: \n" + " b MPU_vTimerSetReloadModeImpl \n" + " MPU_vTimerSetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetReloadMode_Unpriv \n" + " MPU_xTimerGetReloadMode_Priv: \n" + " b MPU_xTimerGetReloadModeImpl \n" + " MPU_xTimerGetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTimerGetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTimerGetReloadMode_Unpriv \n" + " MPU_uxTimerGetReloadMode_Priv: \n" + " b MPU_uxTimerGetReloadModeImpl \n" + " MPU_uxTimerGetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetPeriodImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetPeriod_Unpriv \n" + " MPU_xTimerGetPeriod_Priv: \n" + " b MPU_xTimerGetPeriodImpl \n" + " MPU_xTimerGetPeriod_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetExpiryTimeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetExpiryTime_Unpriv \n" + " MPU_xTimerGetExpiryTime_Priv: \n" + " b MPU_xTimerGetExpiryTimeImpl \n" + " MPU_xTimerGetExpiryTime_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupWaitBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupWaitBits_Unpriv \n" + " MPU_xEventGroupWaitBits_Priv: \n" + " b MPU_xEventGroupWaitBitsImpl \n" + " MPU_xEventGroupWaitBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupClearBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupClearBits_Unpriv \n" + " MPU_xEventGroupClearBits_Priv: \n" + " b MPU_xEventGroupClearBitsImpl \n" + " MPU_xEventGroupClearBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupSetBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupSetBits_Unpriv \n" + " MPU_xEventGroupSetBits_Priv: \n" + " b MPU_xEventGroupSetBitsImpl \n" + " MPU_xEventGroupSetBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupSyncImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupSync_Unpriv \n" + " MPU_xEventGroupSync_Priv: \n" + " b MPU_xEventGroupSyncImpl \n" + " MPU_xEventGroupSync_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxEventGroupGetNumberImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxEventGroupGetNumber_Unpriv \n" + " MPU_uxEventGroupGetNumber_Priv: \n" + " b MPU_uxEventGroupGetNumberImpl \n" + " MPU_uxEventGroupGetNumber_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory" + ); + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vEventGroupSetNumberImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vEventGroupSetNumber_Unpriv \n" + " MPU_vEventGroupSetNumber_Priv: \n" + " b MPU_vEventGroupSetNumberImpl \n" + " MPU_vEventGroupSetNumber_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory" + ); + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferSend_Unpriv \n" + " MPU_xStreamBufferSend_Priv: \n" + " b MPU_xStreamBufferSendImpl \n" + " MPU_xStreamBufferSend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferReceiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferReceive_Unpriv \n" + " MPU_xStreamBufferReceive_Priv: \n" + " b MPU_xStreamBufferReceiveImpl \n" + " MPU_xStreamBufferReceive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferIsFullImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferIsFull_Unpriv \n" + " MPU_xStreamBufferIsFull_Priv: \n" + " b MPU_xStreamBufferIsFullImpl \n" + " MPU_xStreamBufferIsFull_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferIsEmptyImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferIsEmpty_Unpriv \n" + " MPU_xStreamBufferIsEmpty_Priv: \n" + " b MPU_xStreamBufferIsEmptyImpl \n" + " MPU_xStreamBufferIsEmpty_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSpacesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferSpacesAvailable_Unpriv \n" + " MPU_xStreamBufferSpacesAvailable_Priv: \n" + " b MPU_xStreamBufferSpacesAvailableImpl \n" + " MPU_xStreamBufferSpacesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferBytesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferBytesAvailable_Unpriv \n" + " MPU_xStreamBufferBytesAvailable_Priv: \n" + " b MPU_xStreamBufferBytesAvailableImpl \n" + " MPU_xStreamBufferBytesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSetTriggerLevelImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferSetTriggerLevel_Unpriv \n" + " MPU_xStreamBufferSetTriggerLevel_Priv: \n" + " b MPU_xStreamBufferSetTriggerLevelImpl \n" + " MPU_xStreamBufferSetTriggerLevel_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferNextMessageLengthBytesImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv \n" + " MPU_xStreamBufferNextMessageLengthBytes_Priv: \n" + " b MPU_xStreamBufferNextMessageLengthBytesImpl \n" + " MPU_xStreamBufferNextMessageLengthBytes_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c new file mode 100644 index 000000000..76d2b2445 --- /dev/null +++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c @@ -0,0 +1,2280 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024-2025 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU includes. */ +#include "mpu_wrappers.h" +#include "mpu_syscall_numbers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration settings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to check the validity of an interrupt priority. + */ +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) ) +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used during system call enter and exit. + */ +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Offsets in the stack to the parameters when inside the SVC handler. + */ +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +#if ( portARMV8M_MINOR_VERSION >= 1 ) + + /* Enable Privileged eXecute Never MPU attribute for the selected memory + * region. */ + #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL ) +#endif /* portARMV8M_MINOR_VERSION >= 1 */ + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Extract first address of the MPU region as encoded in the + * RBAR (Region Base Address Register) value. */ +#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \ + ( ( rbar ) & portMPU_RBAR_ADDRESS_MASK ) + +/* Extract last address of the MPU region as encoded in the + * RLAR (Region Limit Address Register) value. */ +#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \ + ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK ) + +/* Does addr lies within [start, end] address range? */ +#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \ + ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) ) + +/* Is the access request satisfied by the available permissions? */ +#define portIS_AUTHORIZED( accessRequest, permissions ) \ + ( ( ( permissions ) & ( accessRequest ) ) == accessRequest ) + +/* Max value that fits in a uint32_t type. */ +#define portUINT32_MAX ( ~( ( uint32_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. + */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 + +/** + * @brief Constants required to check and configure PACBTI security feature implementation. + */ +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) ) + + #define portCONTROL_UPAC_EN ( 1UL << 7UL ) + #define portCONTROL_PAC_EN ( 1UL << 6UL ) + #define portCONTROL_UBTI_EN ( 1UL << 5UL ) + #define portCONTROL_BTI_EN ( 1UL << 4UL ) + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Extract MPU region's access permissions from the Region Base Address + * Register (RBAR) value. + * + * @param ulRBARValue RBAR value for the MPU region. + * + * @return uint32_t Access permissions. + */ + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + + /** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + /** + * @brief Configures PACBTI features. + * + * This function configures the Pointer Authentication, and Branch Target + * Identification security features as per the user configuration. It returns + * the value of the special purpose CONTROL register accordingly, and optionally + * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M + * architecture based) target supports PACBTI security feature. + * + * @param xWriteControlRegister Used to control whether the special purpose + * CONTROL register should be updated or not. + * + * @return CONTROL register value according to the configured PACBTI option. + */ + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the system call stack so that upon returning from + * SVC, the system call stack is used. + * + * @param pulTaskStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + * @param ucSystemCallNumber The system call number of the system call. + */ + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Raise SVC for exiting from a system call. + */ + void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief This variable is set to pdTRUE when the scheduler is started. + */ + PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + + /** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +/** + * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + /** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + + /** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + + /** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the cpsid instruction + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessPermissions = 0; + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_ONLY ) + { + ulAccessPermissions = tskMPU_READ_PERMISSION; + } + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_WRITE ) + { + ulAccessPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION ); + } + + return ulAccessPermissions; + } + +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } + +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ portOFFSET_TO_PC ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ]; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulSystemCallStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the system call section (i.e. application is + * not raising SVC directly). + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as + * it is non-NULL only during the execution of a system call (i.e. + * between system call enter and exit). + * 3. System call is not for a kernel API disabled by the configuration + * in FreeRTOSConfig.h. + * 4. We do not need to check that ucSystemCallNumber is within range + * because the assembly SVC handler checks that before calling + * this function. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) && + ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) ) + { + pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the system call stack for the stack frame. */ + pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulSystemCallStack[ i ] = pulTaskStack[ i ]; + } + + /* Store the value of the Link Register before the SVC was raised. + * It contains the address of the caller of the System Call entry + * point (i.e. the caller of the MPU_). We need to restore it + * when we exit from the system call. */ + pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; + + /* Store the value of the PSPLIM register before the SVC was raised. + * We need to restore it when we exit from the system call. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* Use the pulSystemCallStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif + + /* Start executing the system call upon returning from this handler. */ + pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; + + /* Raise a request to exit from the system call upon finishing the + * system call. */ + pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; + + /* Remember the location where we should copy the stack frame when we exit from + * the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize; + + /* Record if the hardware used padding to force the stack pointer + * to be double word aligned. */ + if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK ) + { + pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG; + } + else + { + pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG ); + } + + /* We ensure in pxPortInitialiseStack that the system call stack is + * double word aligned and therefore, there is no need of padding. + * Clear the bit[9] of stacked xPSR. */ + pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + + /* Raise the privilege for the duration of the system call. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " bics r0, r1 \n" /* Clear nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */ + { + __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulTaskStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the privileged code (i.e. application is not + * raising SVC directly). This SVC is only raised from + * vRequestSystemCallExit which is in the privileged code section. + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL - + * this means that we previously entered a system call and the + * application is not attempting to exit without entering a system + * call. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) ) + { + pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the task stack for the stack frame. */ + pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulTaskStack[ i ] = pulSystemCallStack[ i ]; + } + + /* Use the pulTaskStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) ); + + /* Return to the caller of the System Call entry point (i.e. the + * caller of the MPU_). */ + pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + /* Ensure that LR has a valid value.*/ + pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + + /* Restore the PSPLIM register to what it was at the time of + * system call entry. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* If the hardware used padding to force the stack pointer + * to be double word aligned, set the stacked xPSR bit[9], + * otherwise clear it. */ + if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG ) + { + pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK; + } + else + { + pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + } + + /* This is not NULL only for the duration of the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; + + /* Drop the privilege before returning to the thread mode. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " orrs r0, r1 \n" /* Set nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xTaskIsPrivileged = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xTaskIsPrivileged = pdTRUE; + } + + return xTaskIsPrivileged; + } + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged, + xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulIndex = 0; + uint32_t ulControl = 0x0; + + xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ + ulIndex++; + + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + ulIndex++; + + #if ( configENABLE_TRUSTZONE == 1 ) + { + xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */ + ulIndex++; + } + #endif /* configENABLE_TRUSTZONE */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + ulIndex++; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Check PACBTI security feature configuration before pushing the + * CONTROL register's value on task's TCB. */ + ulControl = prvConfigurePACBTI( pdFALSE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + if( xRunPrivileged == pdTRUE ) + { + xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + else + { + xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG ); + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ + ulIndex++; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + { + /* Ensure that the system call stack is double word aligned. */ + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) + + ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + /* This is not NULL only for the duration of a system call. */ + xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL; + } + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ]; + ulIndex++; + } + } + #endif /* configENABLE_PAC */ + + return &( xMPUSettings->ulContext[ ulIndex ] ); + } + +#else /* configENABLE_MPU */ + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ + { + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + pxTopOfStack--; + *pxTopOfStack = ulTaskPacKey[ i ]; + } + } + #endif /* configENABLE_PAC */ + + return pxTopOfStack; + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Set the CONTROL register value based on PACBTI security feature + * configuration before starting the first task. */ + ( void ) prvConfigurePACBTI( pdTRUE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + { + xSchedulerRunning = pdTRUE; + } + #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + configSTACK_DEPTH_TYPE uxStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( uxStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* PXN. */ + #if ( portARMV8M_MINOR_VERSION >= 1 ) + { + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ); + } + } + #endif /* portARMV8M_MINOR_VERSION >= 1 */ + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, + uint32_t ulBufferLength, + uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */ + + { + uint32_t i, ulBufferStartAddress, ulBufferEndAddress; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE ) + { + ulBufferStartAddress = ( uint32_t ) pvBuffer; + ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL ); + + for( i = 0; i < portTOTAL_NUM_REGIONS; i++ ) + { + /* Is the MPU region enabled? */ + if( ( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR & portMPU_RLAR_REGION_ENABLE ) == portMPU_RLAR_REGION_ENABLE ) + { + if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_AUTHORIZED( ulAccessRequested, + prvGetRegionAccessPermissions( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ) ) ) + { + xAccessGranted = pdTRUE; + break; + } + } + } + } + } + + return xAccessGranted; + } + +#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings; + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else + { + xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 ) + { + xAccessGranted = pdTRUE; + } + } + } + + return xAccessGranted; + } + + #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + ( void ) lInternalIndexOfKernelObject; + + /* If Access Control List feature is not used, all the tasks have + * access to all the kernel objects. */ + return pdTRUE; + } + + #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + { + uint32_t ulControl = 0x0; + + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); + + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; + + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c new file mode 100644 index 000000000..bc7bb6071 --- /dev/null +++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c @@ -0,0 +1,524 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION + * is defined correctly and privileged functions are placed in correct sections. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Portasm includes. */ +#include "portasm.h" + +/* System call numbers includes. */ +#include "mpu_syscall_numbers.h" + +/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the + * header files. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#if ( configENABLE_MPU == 1 ) + + void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " program_mpu_first_task: \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */ + " \n" + " dmb \n" /* Complete outstanding transfers before disabling MPU. */ + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + " str r2, [r1] \n" /* Disable MPU. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */ + " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r1, [r2] \n" /* Program MAIR0. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " \n" + " movs r3, #4 \n" /* r3 = 4. */ + " str r3, [r1] \n" /* Program RNR = 4. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + " \n" + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " orr r2, #1 \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */ + " str r2, [r1] \n" /* Enable MPU. */ + " dsb \n" /* Force memory writes before continuing. */ + " \n" + " restore_context_first_task: \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/ + " ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */ + " \n" + " restore_special_regs_first_task: \n" + #if ( configENABLE_PAC == 1 ) + " ldmdb r1!, {r2-r5} \n" /* Read task's dedicated PAC key from the task's context. */ + " msr PAC_KEY_P_0, r2 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_1, r3 \n" + " msr PAC_KEY_P_2, r4 \n" + " msr PAC_KEY_P_3, r5 \n" + " clrm {r2-r5} \n" /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + " ldmdb r1!, {r2-r4, lr} \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */ + " msr psp, r2 \n" + " msr psplim, r3 \n" + " msr control, r4 \n" + " \n" + " restore_general_regs_first_task: \n" + " ldmdb r1!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */ + " stmia r2!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */ + " ldmdb r1!, {r4-r11} \n" /* r4-r11 restored. */ + " \n" + " restore_context_done_first_task: \n" + " str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */ + " mov r0, #0 \n" + " msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */ + " bx lr \n" + ); + } + +#else /* configENABLE_MPU */ + + void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + " ldr r0, [r1] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + " \n" + #if ( configENABLE_PAC == 1 ) + " ldmia r0!, {r1-r4} \n" /* Read task's dedicated PAC key from stack. */ + " msr PAC_KEY_P_3, r1 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_2, r2 \n" + " msr PAC_KEY_P_1, r3 \n" + " msr PAC_KEY_P_0, r4 \n" + " clrm {r1-r4} \n" /* Clear r1-r4. */ + #endif /* configENABLE_PAC */ + " \n" + " ldm r0!, {r1-r2} \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */ + " msr psplim, r1 \n" /* Set this task's PSPLIM value. */ + " mrs r1, control \n" /* Obtain current control register value. */ + " orrs r1, r1, #2 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */ + " msr control, r1 \n" /* Write back the new control register value. */ + " adds r0, #32 \n" /* Discard everything up to r0. */ + " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */ + " isb \n" + " mov r0, #0 \n" + " msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */ + " bx r2 \n" /* Finally, branch to EXC_RETURN. */ + ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* r0 = CONTROL. */ + " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + " ite ne \n" + " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + " bx lr \n" /* Return. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* Read the CONTROL register. */ + " bic r0, #1 \n" /* Clear the bit 0. */ + " msr control, r0 \n" /* Write back the new CONTROL value. */ + " bx lr \n" /* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vResetPrivilege( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* r0 = CONTROL. */ + " orr r0, #1 \n" /* r0 = r0 | 1. */ + " msr control, r0 \n" /* CONTROL = r0. */ + " bx lr \n" /* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r0, =0xe000ed08 \n" /* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */ + " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */ + " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */ + " cpsie i \n" /* Globally enable interrupts. */ + " cpsie f \n" + " dsb \n" + " isb \n" + " svc %0 \n" /* System call to start the first task. */ + " nop \n" + ::"i" ( portSVC_START_SCHEDULER ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, basepri \n" /* r0 = basepri. Return original basepri value. */ + " mov r1, %0 \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r1 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bx lr \n" /* Return. */ + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " msr basepri, r0 \n" /* basepri = ulMask. */ + " dsb \n" + " isb \n" + " bx lr \n" /* Return. */ + ::: "memory" + ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */ + " ldr r1, [r0] \n" /* r1 = Location in TCB where the context should be saved. */ + " mrs r2, psp \n" /* r2 = PSP. */ + " \n" + " save_general_regs: \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " add r2, r2, #0x20 \n" /* Move r2 to location where s0 is saved. */ + " tst lr, #0x10 \n" + " ittt eq \n" + " vstmiaeq r1!, {s16-s31} \n" /* Store s16-s31. */ + " vldmiaeq r2, {s0-s16} \n" /* Copy hardware saved FP context into s0-s16. */ + " vstmiaeq r1!, {s0-s16} \n" /* Store hardware saved FP context. */ + " sub r2, r2, #0x20 \n" /* Set r2 back to the location of hardware saved context. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " stmia r1!, {r4-r11} \n" /* Store r4-r11. */ + " ldmia r2, {r4-r11} \n" /* Copy the hardware saved context into r4-r11. */ + " stmia r1!, {r4-r11} \n" /* Store the hardware saved context. */ + " \n" + " save_special_regs: \n" + " mrs r3, psplim \n" /* r3 = PSPLIM. */ + " mrs r4, control \n" /* r4 = CONTROL. */ + " stmia r1!, {r2-r4, lr} \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ + #if ( configENABLE_PAC == 1 ) + " mrs r2, PAC_KEY_P_0 \n" /* Read task's dedicated PAC key from the PAC key registers. */ + " mrs r3, PAC_KEY_P_1 \n" + " mrs r4, PAC_KEY_P_2 \n" + " mrs r5, PAC_KEY_P_3 \n" + " stmia r1!, {r2-r5} \n" /* Store the task's dedicated PAC key on the task's context. */ + " clrm {r2-r5} \n" /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + " str r1, [r0] \n" /* Save the location from where the context should be restored as the first member of TCB. */ + " \n" + " select_next_task: \n" + " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bl vTaskSwitchContext \n" + " mov r0, #0 \n" /* r0 = 0. */ + " msr basepri, r0 \n" /* Enable interrupts. */ + " \n" + " program_mpu: \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */ + " \n" + " dmb \n" /* Complete outstanding transfers before disabling MPU. */ + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + " str r2, [r1] \n" /* Disable MPU. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */ + " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r1, [r2] \n" /* Program MAIR0. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " \n" + " movs r3, #4 \n" /* r3 = 4. */ + " str r3, [r1] \n" /* Program RNR = 4. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + " \n" + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " orr r2, #1 \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */ + " str r2, [r1] \n" /* Enable MPU. */ + " dsb \n" /* Force memory writes before continuing. */ + " \n" + " restore_context: \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/ + " ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */ + " \n" + " restore_special_regs: \n" + #if ( configENABLE_PAC == 1 ) + " ldmdb r1!, {r2-r5} \n" /* Read task's dedicated PAC key from the task's context. */ + " msr PAC_KEY_P_0, r2 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_1, r3 \n" + " msr PAC_KEY_P_2, r4 \n" + " msr PAC_KEY_P_3, r5 \n" + " clrm {r2-r5} \n" /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + " ldmdb r1!, {r2-r4, lr} \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */ + " msr psp, r2 \n" + " msr psplim, r3 \n" + " msr control, r4 \n" + " \n" + " restore_general_regs: \n" + " ldmdb r1!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */ + " stmia r2!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */ + " ldmdb r1!, {r4-r11} \n" /* r4-r11 restored. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" + " ittt eq \n" + " vldmdbeq r1!, {s0-s16} \n" /* s0-s16 contain hardware saved FP context. */ + " vstmiaeq r2!, {s0-s16} \n" /* Copy hardware saved FP context on the task stack. */ + " vldmdbeq r1!, {s16-s31} \n" /* Restore s16-s31. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + " restore_context_done: \n" + " str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */ + " bx lr \n" + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); + } + +#else /* configENABLE_MPU */ + + void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, psp \n" /* Read PSP in r0. */ + " \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vstmdbeq r0!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + " mrs r2, psplim \n" /* r2 = PSPLIM. */ + " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */ + " stmdb r0!, {r2-r11} \n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */ + " \n" + #if ( configENABLE_PAC == 1 ) + " mrs r1, PAC_KEY_P_3 \n" /* Read task's dedicated PAC key from the PAC key registers. */ + " mrs r2, PAC_KEY_P_2 \n" + " mrs r3, PAC_KEY_P_1 \n" + " mrs r4, PAC_KEY_P_0 \n" + " stmdb r0!, {r1-r4} \n" /* Store the task's dedicated PAC key on the stack. */ + " clrm {r1-r4} \n" /* Clear r1-r4. */ + #endif /* configENABLE_PAC */ + " \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + " str r0, [r1] \n" /* Save the new top of stack in TCB. */ + " \n" + " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bl vTaskSwitchContext \n" + " mov r0, #0 \n" /* r0 = 0. */ + " msr basepri, r0 \n" /* Enable interrupts. */ + " \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ + " \n" + #if ( configENABLE_PAC == 1 ) + " ldmia r0!, {r2-r5} \n" /* Read task's dedicated PAC key from stack. */ + " msr PAC_KEY_P_3, r2 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_2, r3 \n" + " msr PAC_KEY_P_1, r4 \n" + " msr PAC_KEY_P_0, r5 \n" + " clrm {r2-r5} \n" /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + " \n" + " ldmia r0!, {r2-r11} \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */ + " \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst r3, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vldmiaeq r0!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */ + " msr psp, r0 \n" /* Remember the new top of stack for the task. */ + " bx r3 \n" + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + ".syntax unified \n" + ".extern vPortSVCHandler_C \n" + ".extern vSystemCallEnter \n" + ".extern vSystemCallExit \n" + " \n" + "tst lr, #4 \n" + "ite eq \n" + "mrseq r0, msp \n" + "mrsne r0, psp \n" + " \n" + "ldr r1, [r0, #24] \n" + "ldrb r2, [r1, #-2] \n" + "cmp r2, %0 \n" + "blt syscall_enter \n" + "cmp r2, %1 \n" + "beq syscall_exit \n" + "b vPortSVCHandler_C \n" + " \n" + "syscall_enter: \n" + " mov r1, lr \n" + " b vSystemCallEnter \n" + " \n" + "syscall_exit: \n" + " mov r1, lr \n" + " b vSystemCallExit \n" + " \n" + : /* No outputs. */ + : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT ) + : "r0", "r1", "r2", "memory" + ); + } + +#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " tst lr, #4 \n" + " ite eq \n" + " mrseq r0, msp \n" + " mrsne r0, psp \n" + " ldr r1, =vPortSVCHandler_C \n" + " bx r1 \n" + ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.h b/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.h new file mode 100644 index 000000000..b7021b024 --- /dev/null +++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kernel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h new file mode 100644 index 000000000..b886287ac --- /dev/null +++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacro.h @@ -0,0 +1,81 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M35P" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portARMV8M_MINOR_VERSION 0 +#define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +#ifndef configENABLE_MVE + #define configENABLE_MVE 0 +#elif ( configENABLE_MVE != 0 ) + #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M35. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h new file mode 100644 index 000000000..f373bcad5 --- /dev/null +++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/portmacrocommon.h @@ -0,0 +1,582 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACROCOMMON_H +#define PORTMACROCOMMON_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. +#endif /* configENABLE_FPU */ + +#ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. +#endif /* configENABLE_MPU */ + +#ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. +#endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() +#define portINLINE __inline +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif +#define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ +extern BaseType_t xPortIsInsideInterrupt( void ); + +extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + +extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; +extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + +extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; +extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + +#if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_PAC == 1 ) + + /** + * @brief Generates 128-bit task's random PAC key. + * + * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be + * filled with a 128-bit random number. + */ + void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); + +#endif /* configENABLE_PAC */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ +#if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) +#else + #define portPRIVILEGE_BIT ( 0x0UL ) +#endif /* configENABLE_MPU */ + +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ +#define portPRIVILEGED_FLASH_REGION ( 0UL ) +#define portUNPRIVILEGED_FLASH_REGION ( 1UL ) +#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) +#define portPRIVILEGED_RAM_REGION ( 3UL ) +#define portSTACK_REGION ( 4UL ) +#define portFIRST_CONFIGURABLE_REGION ( 5UL ) +#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) +#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) +#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ +#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ +#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ +#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ +#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ +#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ +#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ +#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) +#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) +#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + +#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) +#define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) +#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) +#define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + +#define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + #ifndef configSYSTEM_CALL_STACK_SIZE + #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. + #endif + + /** + * @brief System call stack. + */ + typedef struct SYSTEM_CALL_STACK_INFO + { + uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; + uint32_t * pulSystemCallStack; + uint32_t * pulSystemCallStackLimit; + uint32_t * pulTaskStack; + uint32_t ulLinkRegisterAtSystemCallEntry; + uint32_t ulStackLimitRegisterAtSystemCallEntry; + } xSYSTEM_CALL_STACK_INFO; + + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + /** + * @brief MPU settings as stored in the TCB. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><-----------><----> + * 16 17 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 71 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 17 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 55 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | | | PC, xPSR | EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><-----------><----> + * 16 17 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 70 + + #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + /* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 17 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 54 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+------------------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +----------+-----------------+------------------------------+------------+-----+ + * + * <---------><----------------><------------------------------><-----------><----> + * 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 38 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+----------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | PC, xPSR | EXC_RETURN | | | + * +----------+-----------------+----------------------+------------+-----+ + * + * <---------><----------------><----------------------><-----------><----> + * 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 37 + + #else /* #if( configENABLE_TRUSTZONE == 1 ) */ + + /* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) + + /* Size of an Access Control List (ACL) entry in bits. */ + #define portACL_ENTRY_SIZE_BITS ( 32U ) + + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + uint32_t ulContext[ MAX_CONTEXT_SIZE ]; + uint32_t ulTaskFlags; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo; + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ]; + #endif + #endif + } xMPU_SETTINGS; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Validate priority of ISRs that are allowed to call FreeRTOS + * system calls. + */ +#if ( configASSERT_DEFINED == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif +#endif + +/** + * @brief SVC numbers. + */ +#define portSVC_ALLOCATE_SECURE_CONTEXT 100 +#define portSVC_FREE_SECURE_CONTEXT 101 +#define portSVC_START_SCHEDULER 102 +#define portSVC_RAISE_PRIVILEGE 103 +#define portSVC_SYSTEM_CALL_EXIT 104 +#define portSVC_YIELD 105 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) +#endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() +#else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + extern BaseType_t xPortIsTaskPrivileged( void ); + +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACROCOMMON_H */ diff --git a/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c new file mode 100644 index 000000000..428e6e84a --- /dev/null +++ b/portable/GCC/ARM_CM3_MPU/mpu_wrappers_v2_asm.c @@ -0,0 +1,2067 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" +#include "event_groups.h" +#include "stream_buffer.h" +#include "mpu_prototypes.h" +#include "mpu_syscall_numbers.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE +/*-----------------------------------------------------------*/ + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + #if ( INCLUDE_xTaskDelayUntil == 1 ) + + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskDelayUntilImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskDelayUntil_Unpriv \n" + " MPU_xTaskDelayUntil_Priv: \n" + " b MPU_xTaskDelayUntilImpl \n" + " MPU_xTaskDelayUntil_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskAbortDelayImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskAbortDelay_Unpriv \n" + " MPU_xTaskAbortDelay_Priv: \n" + " b MPU_xTaskAbortDelayImpl \n" + " MPU_xTaskAbortDelay_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskDelay == 1 ) + + void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskDelayImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskDelay_Unpriv \n" + " MPU_vTaskDelay_Priv: \n" + " b MPU_vTaskDelayImpl \n" + " MPU_vTaskDelay_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskPriorityGet == 1 ) + + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskPriorityGetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskPriorityGet_Unpriv \n" + " MPU_uxTaskPriorityGet_Priv: \n" + " b MPU_uxTaskPriorityGetImpl \n" + " MPU_uxTaskPriorityGet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_eTaskGetState == 1 ) + + eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_eTaskGetStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_eTaskGetState_Unpriv \n" + " MPU_eTaskGetState_Priv: \n" + " b MPU_eTaskGetStateImpl \n" + " MPU_eTaskGetState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory" + ); + } + + #endif /* if ( INCLUDE_eTaskGetState == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskGetInfoImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskGetInfo_Unpriv \n" + " MPU_vTaskGetInfo_Priv: \n" + " b MPU_vTaskGetInfoImpl \n" + " MPU_vTaskGetInfo_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory" + ); + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) + + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetIdleTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetIdleTaskHandle_Unpriv \n" + " MPU_xTaskGetIdleTaskHandle_Priv: \n" + " b MPU_xTaskGetIdleTaskHandleImpl \n" + " MPU_xTaskGetIdleTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + + void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSuspendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSuspend_Unpriv \n" + " MPU_vTaskSuspend_Priv: \n" + " b MPU_vTaskSuspendImpl \n" + " MPU_vTaskSuspend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + + void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskResumeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskResume_Unpriv \n" + " MPU_vTaskResume_Priv: \n" + " b MPU_vTaskResumeImpl \n" + " MPU_vTaskResume_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + TickType_t MPU_xTaskGetTickCount( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetTickCountImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetTickCount_Unpriv \n" + " MPU_xTaskGetTickCount_Priv: \n" + " b MPU_xTaskGetTickCountImpl \n" + " MPU_xTaskGetTickCount_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetNumberOfTasksImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetNumberOfTasks_Unpriv \n" + " MPU_uxTaskGetNumberOfTasks_Priv: \n" + " b MPU_uxTaskGetNumberOfTasksImpl \n" + " MPU_uxTaskGetNumberOfTasks_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetRunTimeCounterImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetRunTimeCounter_Unpriv \n" + " MPU_ulTaskGetRunTimeCounter_Priv: \n" + " b MPU_ulTaskGetRunTimeCounterImpl \n" + " MPU_ulTaskGetRunTimeCounter_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetRunTimePercentImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetRunTimePercent_Unpriv \n" + " MPU_ulTaskGetRunTimePercent_Priv: \n" + " b MPU_ulTaskGetRunTimePercentImpl \n" + " MPU_ulTaskGetRunTimePercent_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetIdleRunTimePercentImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv \n" + " MPU_ulTaskGetIdleRunTimePercent_Priv: \n" + " b MPU_ulTaskGetIdleRunTimePercentImpl \n" + " MPU_ulTaskGetIdleRunTimePercent_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetIdleRunTimeCounterImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv \n" + " MPU_ulTaskGetIdleRunTimeCounter_Priv: \n" + " b MPU_ulTaskGetIdleRunTimeCounterImpl \n" + " MPU_ulTaskGetIdleRunTimeCounter_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetApplicationTaskTagImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetApplicationTaskTag_Unpriv \n" + " MPU_vTaskSetApplicationTaskTag_Priv: \n" + " b MPU_vTaskSetApplicationTaskTagImpl \n" + " MPU_vTaskSetApplicationTaskTag_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory" + ); + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetApplicationTaskTagImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetApplicationTaskTag_Unpriv \n" + " MPU_xTaskGetApplicationTaskTag_Priv: \n" + " b MPU_xTaskGetApplicationTaskTagImpl \n" + " MPU_xTaskGetApplicationTaskTag_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory" + ); + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetThreadLocalStoragePointerImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv \n" + " MPU_vTaskSetThreadLocalStoragePointer_Priv: \n" + " b MPU_vTaskSetThreadLocalStoragePointerImpl \n" + " MPU_vTaskSetThreadLocalStoragePointer_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory" + ); + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv \n" + " MPU_pvTaskGetThreadLocalStoragePointer_Priv: \n" + " b MPU_pvTaskGetThreadLocalStoragePointerImpl \n" + " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory" + ); + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetSystemStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetSystemState_Unpriv \n" + " MPU_uxTaskGetSystemState_Priv: \n" + " b MPU_uxTaskGetSystemStateImpl \n" + " MPU_uxTaskGetSystemState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory" + ); + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) + + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetStackHighWaterMarkImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetStackHighWaterMark_Unpriv \n" + " MPU_uxTaskGetStackHighWaterMark_Priv: \n" + " b MPU_uxTaskGetStackHighWaterMarkImpl \n" + " MPU_uxTaskGetStackHighWaterMark_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetStackHighWaterMark2Impl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv \n" + " MPU_uxTaskGetStackHighWaterMark2_Priv: \n" + " b MPU_uxTaskGetStackHighWaterMark2Impl \n" + " MPU_uxTaskGetStackHighWaterMark2_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) + + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetCurrentTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetCurrentTaskHandle_Unpriv \n" + " MPU_xTaskGetCurrentTaskHandle_Priv: \n" + " b MPU_xTaskGetCurrentTaskHandleImpl \n" + " MPU_xTaskGetCurrentTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory" + ); + } + + #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetSchedulerState == 1 ) + + BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetSchedulerStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetSchedulerState_Unpriv \n" + " MPU_xTaskGetSchedulerState_Priv: \n" + " b MPU_xTaskGetSchedulerStateImpl \n" + " MPU_xTaskGetSchedulerState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */ +/*-----------------------------------------------------------*/ + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetTimeOutStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetTimeOutState_Unpriv \n" + " MPU_vTaskSetTimeOutState_Priv: \n" + " b MPU_vTaskSetTimeOutStateImpl \n" + " MPU_vTaskSetTimeOutState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskCheckForTimeOutImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskCheckForTimeOut_Unpriv \n" + " MPU_xTaskCheckForTimeOut_Priv: \n" + " b MPU_xTaskCheckForTimeOutImpl \n" + " MPU_xTaskCheckForTimeOut_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotify_Unpriv \n" + " MPU_xTaskGenericNotify_Priv: \n" + " b MPU_xTaskGenericNotifyImpl \n" + " MPU_xTaskGenericNotify_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyWaitImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotifyWait_Unpriv \n" + " MPU_xTaskGenericNotifyWait_Priv: \n" + " b MPU_xTaskGenericNotifyWaitImpl \n" + " MPU_xTaskGenericNotifyWait_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGenericNotifyTakeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGenericNotifyTake_Unpriv \n" + " MPU_ulTaskGenericNotifyTake_Priv: \n" + " b MPU_ulTaskGenericNotifyTakeImpl \n" + " MPU_ulTaskGenericNotifyTake_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyStateClearImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotifyStateClear_Unpriv \n" + " MPU_xTaskGenericNotifyStateClear_Priv: \n" + " b MPU_xTaskGenericNotifyStateClearImpl \n" + " MPU_xTaskGenericNotifyStateClear_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGenericNotifyValueClearImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGenericNotifyValueClear_Unpriv \n" + " MPU_ulTaskGenericNotifyValueClear_Priv: \n" + " b MPU_ulTaskGenericNotifyValueClearImpl \n" + " MPU_ulTaskGenericNotifyValueClear_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGenericSendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGenericSend_Unpriv \n" + " MPU_xQueueGenericSend_Priv: \n" + " b MPU_xQueueGenericSendImpl \n" + " MPU_xQueueGenericSend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxQueueMessagesWaitingImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxQueueMessagesWaiting_Unpriv \n" + " MPU_uxQueueMessagesWaiting_Priv: \n" + " b MPU_uxQueueMessagesWaitingImpl \n" + " MPU_uxQueueMessagesWaiting_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxQueueSpacesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxQueueSpacesAvailable_Unpriv \n" + " MPU_uxQueueSpacesAvailable_Priv: \n" + " b MPU_uxQueueSpacesAvailableImpl \n" + " MPU_uxQueueSpacesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueReceiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueReceive_Unpriv \n" + " MPU_xQueueReceive_Priv: \n" + " b MPU_xQueueReceiveImpl \n" + " MPU_xQueueReceive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueuePeekImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueuePeek_Unpriv \n" + " MPU_xQueuePeek_Priv: \n" + " b MPU_xQueuePeekImpl \n" + " MPU_xQueuePeek_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueSemaphoreTakeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueSemaphoreTake_Unpriv \n" + " MPU_xQueueSemaphoreTake_Priv: \n" + " b MPU_xQueueSemaphoreTakeImpl \n" + " MPU_xQueueSemaphoreTake_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) + + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGetMutexHolderImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGetMutexHolder_Unpriv \n" + " MPU_xQueueGetMutexHolder_Priv: \n" + " b MPU_xQueueGetMutexHolderImpl \n" + " MPU_xQueueGetMutexHolder_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory" + ); + } + + #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueTakeMutexRecursiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueTakeMutexRecursive_Unpriv \n" + " MPU_xQueueTakeMutexRecursive_Priv: \n" + " b MPU_xQueueTakeMutexRecursiveImpl \n" + " MPU_xQueueTakeMutexRecursive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory" + ); + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGiveMutexRecursiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGiveMutexRecursive_Unpriv \n" + " MPU_xQueueGiveMutexRecursive_Priv: \n" + " b MPU_xQueueGiveMutexRecursiveImpl \n" + " MPU_xQueueGiveMutexRecursive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory" + ); + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueSelectFromSetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueSelectFromSet_Unpriv \n" + " MPU_xQueueSelectFromSet_Priv: \n" + " b MPU_xQueueSelectFromSetImpl \n" + " MPU_xQueueSelectFromSet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory" + ); + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueAddToSetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueAddToSet_Unpriv \n" + " MPU_xQueueAddToSet_Priv: \n" + " b MPU_xQueueAddToSetImpl \n" + " MPU_xQueueAddToSet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory" + ); + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vQueueAddToRegistryImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vQueueAddToRegistry_Unpriv \n" + " MPU_vQueueAddToRegistry_Priv: \n" + " b MPU_vQueueAddToRegistryImpl \n" + " MPU_vQueueAddToRegistry_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vQueueUnregisterQueueImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vQueueUnregisterQueue_Unpriv \n" + " MPU_vQueueUnregisterQueue_Priv: \n" + " b MPU_vQueueUnregisterQueueImpl \n" + " MPU_vQueueUnregisterQueue_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pcQueueGetNameImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pcQueueGetName_Unpriv \n" + " MPU_pcQueueGetName_Priv: \n" + " b MPU_pcQueueGetNameImpl \n" + " MPU_pcQueueGetName_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pvTimerGetTimerIDImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pvTimerGetTimerID_Unpriv \n" + " MPU_pvTimerGetTimerID_Priv: \n" + " b MPU_pvTimerGetTimerIDImpl \n" + " MPU_pvTimerGetTimerID_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTimerSetTimerIDImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTimerSetTimerID_Unpriv \n" + " MPU_vTimerSetTimerID_Priv: \n" + " b MPU_vTimerSetTimerIDImpl \n" + " MPU_vTimerSetTimerID_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerIsTimerActiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerIsTimerActive_Unpriv \n" + " MPU_xTimerIsTimerActive_Priv: \n" + " b MPU_xTimerIsTimerActiveImpl \n" + " MPU_xTimerIsTimerActive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv \n" + " MPU_xTimerGetTimerDaemonTaskHandle_Priv: \n" + " b MPU_xTimerGetTimerDaemonTaskHandleImpl \n" + " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGenericCommandFromTaskImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGenericCommandFromTask_Unpriv \n" + " MPU_xTimerGenericCommandFromTask_Priv: \n" + " b MPU_xTimerGenericCommandFromTaskImpl \n" + " MPU_xTimerGenericCommandFromTask_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pcTimerGetNameImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pcTimerGetName_Unpriv \n" + " MPU_pcTimerGetName_Priv: \n" + " b MPU_pcTimerGetNameImpl \n" + " MPU_pcTimerGetName_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTimerSetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTimerSetReloadMode_Unpriv \n" + " MPU_vTimerSetReloadMode_Priv: \n" + " b MPU_vTimerSetReloadModeImpl \n" + " MPU_vTimerSetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetReloadMode_Unpriv \n" + " MPU_xTimerGetReloadMode_Priv: \n" + " b MPU_xTimerGetReloadModeImpl \n" + " MPU_xTimerGetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTimerGetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTimerGetReloadMode_Unpriv \n" + " MPU_uxTimerGetReloadMode_Priv: \n" + " b MPU_uxTimerGetReloadModeImpl \n" + " MPU_uxTimerGetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetPeriodImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetPeriod_Unpriv \n" + " MPU_xTimerGetPeriod_Priv: \n" + " b MPU_xTimerGetPeriodImpl \n" + " MPU_xTimerGetPeriod_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetExpiryTimeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetExpiryTime_Unpriv \n" + " MPU_xTimerGetExpiryTime_Priv: \n" + " b MPU_xTimerGetExpiryTimeImpl \n" + " MPU_xTimerGetExpiryTime_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupWaitBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " bne MPU_xEventGroupWaitBits_Unpriv \n" + " MPU_xEventGroupWaitBits_Priv: \n" + " pop {r0} \n" + " b MPU_xEventGroupWaitBitsImpl \n" + " MPU_xEventGroupWaitBits_Unpriv: \n" + " pop {r0} \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupClearBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " bne MPU_xEventGroupClearBits_Unpriv \n" + " MPU_xEventGroupClearBits_Priv: \n" + " pop {r0} \n" + " b MPU_xEventGroupClearBitsImpl \n" + " MPU_xEventGroupClearBits_Unpriv: \n" + " pop {r0} \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupSetBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " bne MPU_xEventGroupSetBits_Unpriv \n" + " MPU_xEventGroupSetBits_Priv: \n" + " pop {r0} \n" + " b MPU_xEventGroupSetBitsImpl \n" + " MPU_xEventGroupSetBits_Unpriv: \n" + " pop {r0} \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupSyncImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " bne MPU_xEventGroupSync_Unpriv \n" + " MPU_xEventGroupSync_Priv: \n" + " pop {r0} \n" + " b MPU_xEventGroupSyncImpl \n" + " MPU_xEventGroupSync_Unpriv: \n" + " pop {r0} \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxEventGroupGetNumberImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxEventGroupGetNumber_Unpriv \n" + " MPU_uxEventGroupGetNumber_Priv: \n" + " b MPU_uxEventGroupGetNumberImpl \n" + " MPU_uxEventGroupGetNumber_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory" + ); + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vEventGroupSetNumberImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vEventGroupSetNumber_Unpriv \n" + " MPU_vEventGroupSetNumber_Priv: \n" + " b MPU_vEventGroupSetNumberImpl \n" + " MPU_vEventGroupSetNumber_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory" + ); + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " bne MPU_xStreamBufferSend_Unpriv \n" + " MPU_xStreamBufferSend_Priv: \n" + " pop {r0} \n" + " b MPU_xStreamBufferSendImpl \n" + " MPU_xStreamBufferSend_Unpriv: \n" + " pop {r0} \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferReceiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " bne MPU_xStreamBufferReceive_Unpriv \n" + " MPU_xStreamBufferReceive_Priv: \n" + " pop {r0} \n" + " b MPU_xStreamBufferReceiveImpl \n" + " MPU_xStreamBufferReceive_Unpriv: \n" + " pop {r0} \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferIsFullImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " bne MPU_xStreamBufferIsFull_Unpriv \n" + " MPU_xStreamBufferIsFull_Priv: \n" + " pop {r0} \n" + " b MPU_xStreamBufferIsFullImpl \n" + " MPU_xStreamBufferIsFull_Unpriv: \n" + " pop {r0} \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferIsEmptyImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " bne MPU_xStreamBufferIsEmpty_Unpriv \n" + " MPU_xStreamBufferIsEmpty_Priv: \n" + " pop {r0} \n" + " b MPU_xStreamBufferIsEmptyImpl \n" + " MPU_xStreamBufferIsEmpty_Unpriv: \n" + " pop {r0} \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSpacesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " bne MPU_xStreamBufferSpacesAvailable_Unpriv \n" + " MPU_xStreamBufferSpacesAvailable_Priv: \n" + " pop {r0} \n" + " b MPU_xStreamBufferSpacesAvailableImpl \n" + " MPU_xStreamBufferSpacesAvailable_Unpriv: \n" + " pop {r0} \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferBytesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " bne MPU_xStreamBufferBytesAvailable_Unpriv \n" + " MPU_xStreamBufferBytesAvailable_Priv: \n" + " pop {r0} \n" + " b MPU_xStreamBufferBytesAvailableImpl \n" + " MPU_xStreamBufferBytesAvailable_Unpriv: \n" + " pop {r0} \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSetTriggerLevelImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " bne MPU_xStreamBufferSetTriggerLevel_Unpriv \n" + " MPU_xStreamBufferSetTriggerLevel_Priv: \n" + " pop {r0} \n" + " b MPU_xStreamBufferSetTriggerLevelImpl \n" + " MPU_xStreamBufferSetTriggerLevel_Unpriv: \n" + " pop {r0} \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferNextMessageLengthBytesImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv \n" + " MPU_xStreamBufferNextMessageLengthBytes_Priv: \n" + " pop {r0} \n" + " b MPU_xStreamBufferNextMessageLengthBytesImpl \n" + " MPU_xStreamBufferNextMessageLengthBytes_Unpriv: \n" + " pop {r0} \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + +#endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ diff --git a/portable/GCC/ARM_CM3_MPU/port.c b/portable/GCC/ARM_CM3_MPU/port.c new file mode 100644 index 000000000..8c4dd7800 --- /dev/null +++ b/portable/GCC/ARM_CM3_MPU/port.c @@ -0,0 +1,1583 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2025 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ARM CM3 MPU port. +*----------------------------------------------------------*/ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "mpu_syscall_numbers.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK ( 1UL << 2UL ) +#else + +/* The way the SysTick is clocked is not modified in case it is not the same + * as the core. */ + #define portNVIC_SYSTICK_CLK ( 0 ) +#endif + +#ifndef configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS + #warning "configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS is not defined. We recommend defining it to 0 in FreeRTOSConfig.h for better security." + #define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS 1 +#endif + +/* Prototype of all Interrupt Service Routines (ISRs). */ +typedef void ( * portISR_t )( void ); + +/* Constants required to access and manipulate the NVIC. */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) ) +#define portNVIC_SYS_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) +#define portNVIC_MEM_FAULT_ENABLE ( 1UL << 16UL ) + +/* Constants required to access and manipulate the MPU. */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_REGION_BASE_ADDRESS_REG ( *( ( volatile uint32_t * ) 0xe000ed9C ) ) +#define portMPU_REGION_ATTRIBUTE_REG ( *( ( volatile uint32_t * ) 0xe000edA0 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */ +#define portMPU_ENABLE ( 0x01UL ) +#define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL ) +#define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL ) +#define portMPU_REGION_VALID ( 0x10UL ) +#define portMPU_REGION_ENABLE ( 0x01UL ) +#define portPERIPHERALS_START_ADDRESS 0x40000000UL +#define portPERIPHERALS_END_ADDRESS 0x5FFFFFFFUL + +/* Constants required to access and manipulate the SysTick. */ +#define portNVIC_SYSTICK_INT ( 0x00000002UL ) +#define portNVIC_SYSTICK_ENABLE ( 0x00000001UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL ) +#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) +#define portINITIAL_EXC_RETURN ( 0xfffffffdUL ) +#define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 ) +#define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 ) + +/* Constants used to check the installation of the FreeRTOS interrupt handlers. */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xE000ED08 ) ) +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) + +/* Constants required to check the validity of an interrupt priority. */ +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) + +/* Constants used during system call enter and exit. */ +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) + +/* Offsets in the stack to the parameters when inside the SVC handler. */ +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) + +/* For strict compliance with the Cortex-M spec the task start address should + * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */ +#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL ) + +/* Does addr lie within [start, end] address range? */ +#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \ + ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) ) + +/* Is the access request satisfied by the available permissions? */ +#define portIS_AUTHORIZED( accessRequest, permissions ) \ + ( ( ( permissions ) & ( accessRequest ) ) == accessRequest ) + +/* Max value that fits in a uint32_t type. */ +#define portUINT32_MAX ( ~( ( uint32_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) ) +/*-----------------------------------------------------------*/ + +/* + * Configure a number of standard MPU regions that are used by all tasks. + */ +static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; + +/* + * Return the smallest MPU region size that a given number of bytes will fit + * into. The region size is returned as the value that should be programmed + * into the region attribute register for that region. + */ +static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION; + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ); + +/* + * Standard FreeRTOS exception handlers. + */ +void xPortPendSVHandler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; +void xPortSysTickHandler( void ) __attribute__( ( optimize( "3" ) ) ) PRIVILEGED_FUNCTION; +void vPortSVCHandler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/* + * Starts the scheduler by restoring the context of the first task to run. + */ +static void prvRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/* + * C portion of the SVC handler. The SVC handler is split between an asm entry + * and a C wrapper for simplicity of coding and maintenance. + */ +void vSVCHandler_C( uint32_t * pulRegisters ) __attribute__( ( noinline ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Make a task unprivileged. + */ +void vPortSwitchToUserMode( void ); + +/** + * @brief Enter critical section. + */ +#if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) + void vPortEnterCritical( void ) FREERTOS_SYSTEM_CALL; +#else + void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; +#endif + +/** + * @brief Exit from critical section. + */ +#if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) + void vPortExitCritical( void ) FREERTOS_SYSTEM_CALL; +#else + void vPortExitCritical( void ) PRIVILEGED_FUNCTION; +#endif + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + +/** + * @brief Sets up the system call stack so that upon returning from + * SVC, the system call stack is used. + * + * @param pulTaskStack The current SP when the SVC was raised. + * @param ucSystemCallNumber The system call number of the system call. + */ + void vSystemCallEnter( uint32_t * pulTaskStack, + uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION; + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + +/** + * @brief Raise SVC for exiting from a system call. + */ + void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + +/** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + */ + void vSystemCallExit( uint32_t * pulSystemCallStack ) PRIVILEGED_FUNCTION; + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ +BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; +/*-----------------------------------------------------------*/ + +/* Each task maintains its own interrupt status in the critical nesting + * variable. Note this is not saved as part of the task context as context + * switches can only occur when uxCriticalNesting is zero. */ +static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + +/* + * This variable is set to pdTRUE when the scheduler is started. + */ + PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE; + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/* + * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( configASSERT_DEFINED == 1 ) + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16; +#endif /* configASSERT_DEFINED */ +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged, + xMPU_SETTINGS * xMPUSettings ) +{ + if( xRunPrivileged == pdTRUE ) + { + xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; + xMPUSettings->ulContext[ 0 ] = portINITIAL_CONTROL_IF_PRIVILEGED; + } + else + { + xMPUSettings->ulTaskFlags &= ( ~( portTASK_IS_PRIVILEGED_FLAG ) ); + xMPUSettings->ulContext[ 0 ] = portINITIAL_CONTROL_IF_UNPRIVILEGED; + } + + xMPUSettings->ulContext[ 1 ] = 0x04040404; /* r4. */ + xMPUSettings->ulContext[ 2 ] = 0x05050505; /* r5. */ + xMPUSettings->ulContext[ 3 ] = 0x06060606; /* r6. */ + xMPUSettings->ulContext[ 4 ] = 0x07070707; /* r7. */ + xMPUSettings->ulContext[ 5 ] = 0x08080808; /* r8. */ + xMPUSettings->ulContext[ 6 ] = 0x09090909; /* r9. */ + xMPUSettings->ulContext[ 7 ] = 0x10101010; /* r10. */ + xMPUSettings->ulContext[ 8 ] = 0x11111111; /* r11. */ + xMPUSettings->ulContext[ 9 ] = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ + + xMPUSettings->ulContext[ 10 ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ + xMPUSettings->ulContext[ 11 ] = ( uint32_t ) pvParameters; /* r0. */ + xMPUSettings->ulContext[ 12 ] = 0x01010101; /* r1. */ + xMPUSettings->ulContext[ 13 ] = 0x02020202; /* r2. */ + xMPUSettings->ulContext[ 14 ] = 0x03030303; /* r3. */ + xMPUSettings->ulContext[ 15 ] = 0x12121212; /* r12. */ + xMPUSettings->ulContext[ 16 ] = 0; /* LR. */ + xMPUSettings->ulContext[ 17 ] = ( ( uint32_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC. */ + xMPUSettings->ulContext[ 18 ] = portINITIAL_XPSR; /* xPSR. */ + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + { + /* Ensure that the system call stack is double word aligned. */ + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + /* This is not NULL only for the duration of a system call. */ + xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL; + } + #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + return &( xMPUSettings->ulContext[ 19 ] ); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + void vPortSVCHandler( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + ".syntax unified \n" + ".extern vSVCHandler_C \n" + ".extern vSystemCallEnter \n" + ".extern vSystemCallExit \n" + " \n" + "tst lr, #4 \n" + "ite eq \n" + "mrseq r0, msp \n" + "mrsne r0, psp \n" + " \n" + "ldr r2, [r0, #24] \n" + "ldrb r1, [r2, #-2] \n" + "cmp r1, %0 \n" + "blt vSystemCallEnter \n" + "cmp r1, %1 \n" + "beq vSystemCallExit \n" + "b vSVCHandler_C \n" + " \n" + : /* No outputs. */ + : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT ) + : "r0", "r1", "r2", "memory" + ); + } + +#else /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + void vPortSVCHandler( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */ + { + /* Assumes psp was in use. */ + __asm volatile + ( + #ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */ + " tst lr, #4 \n" + " ite eq \n" + " mrseq r0, msp \n" + " mrsne r0, psp \n" + #else + " mrs r0, psp \n" + #endif + " b %0 \n" + ::"i" ( vSVCHandler_C ) : "r0", "memory" + ); + } + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */ +{ + uint8_t ucSVCNumber; + uint32_t ulPC; + + #if ( ( configUSE_MPU_WRAPPERS_V1 == 1 ) && ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + #endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 1 ) && ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) ) */ + + /* The stack contains: r0, r1, r2, r3, r12, LR, PC and xPSR. The first + * argument (r0) is pulParam[ 0 ]. */ + ulPC = pulParam[ portOFFSET_TO_PC ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + case portSVC_START_SCHEDULER: + prvRestoreContextOfFirstTask(); + break; + + case portSVC_YIELD: + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required + * but do ensure the code is completely + * within the specified behaviour for the + * architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); + + break; + + #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) + #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) + case portSVC_RAISE_PRIVILEGE: /* Only raise the privilege, if the + * svc was raised from any of the + * system calls. */ + + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + __asm volatile + ( + " mrs r1, control \n" /* Obtain current control value. */ + " bic r1, #1 \n" /* Set privilege bit. */ + " msr control, r1 \n" /* Write back new control value. */ + ::: "r1", "memory" + ); + } + + break; + #else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */ + case portSVC_RAISE_PRIVILEGE: + __asm volatile + ( + " mrs r1, control \n" /* Obtain current control value. */ + " bic r1, #1 \n" /* Set privilege bit. */ + " msr control, r1 \n" /* Write back new control value. */ + ::: "r1", "memory" + ); + break; + #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */ + #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + default: /* Unknown SVC call. */ + break; + } +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + void vSystemCallEnter( uint32_t * pulTaskStack, + uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ]; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulSystemCallStack; + uint32_t ulSystemCallLocation, i; + /* Hardware Saved Stack Frame Size upon Exception entry: + * Basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + */ + const uint32_t ulHardwareSavedExceptionFrameSize = 8; + + #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the system call section (i.e. application is + * not raising SVC directly). + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as + * it is non-NULL only during the execution of a system call (i.e. + * between system call enter and exit). + * 3. System call is not for a kernel API disabled by the configuration + * in FreeRTOSConfig.h. + * 4. We do not need to check that ucSystemCallNumber is within range + * because the assembly SVC handler checks that before calling + * this function. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) && + ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) ) + { + pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack; + + /* Make space on the system call stack for the stack frame. */ + pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulSystemCallStack[ i ] = pulTaskStack[ i ]; + } + + /* Use the pulSystemCallStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); + + /* Raise the privilege for the duration of the system call. */ + __asm volatile ( + " mrs r1, control \n" /* Obtain current control value. */ + " bic r1, #1 \n" /* Clear nPRIV bit. */ + " msr control, r1 \n" /* Write back new control value. */ + ::: "r1", "memory" + ); + + /* Remember the location where we should copy the stack frame when we exit from + * the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize; + + /* Store the value of the Link Register before the SVC was raised. + * It contains the address of the caller of the System Call entry + * point (i.e. the caller of the MPU_). We need to restore it + * when we exit from the system call. */ + pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; + + /* Start executing the system call upon returning from this handler. */ + pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; + /* Raise a request to exit from the system call upon finishing the + * system call. */ + pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; + + /* Record if the hardware used padding to force the stack pointer + * to be double word aligned. */ + if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK ) + { + pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG; + } + else + { + pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG ); + } + + /* We ensure in pxPortInitialiseStack that the system call stack is + * double word aligned and therefore, there is no need of padding. + * Clear the bit[9] of stacked xPSR. */ + pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + } + } + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */ + { + __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" ); + } + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + void vSystemCallExit( uint32_t * pulSystemCallStack ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulTaskStack; + uint32_t ulSystemCallLocation, i; + /* Hardware Saved Stack Frame Size upon Exception entry: + * Basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + */ + const uint32_t ulHardwareSavedExceptionFrameSize = 8; + + #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the privileged code (i.e. application is not + * raising SVC directly). This SVC is only raised from + * vRequestSystemCallExit which is in the privileged code section. + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL - + * this means that we previously entered a system call and the + * application is not attempting to exit without entering a system + * call. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) ) + { + pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack; + + /* Make space on the task stack for the stack frame. */ + pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulTaskStack[ i ] = pulSystemCallStack[ i ]; + } + + /* Use the pulTaskStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) ); + + /* Drop the privilege before returning to the thread mode. */ + __asm volatile ( + " mrs r1, control \n" /* Obtain current control value. */ + " orr r1, #1 \n" /* Set nPRIV bit. */ + " msr control, r1 \n" /* Write back new control value. */ + ::: "r1", "memory" + ); + + /* Return to the caller of the System Call entry point (i.e. the + * caller of the MPU_). */ + pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + /* Ensure that LR has a valid value.*/ + pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + + /* If the hardware used padding to force the stack pointer + * to be double word aligned, set the stacked xPSR bit[9], + * otherwise clear it. */ + if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG ) + { + pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK; + } + else + { + pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + } + + /* This is not NULL only for the duration of the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; + } + } + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */ +{ + BaseType_t xTaskIsPrivileged = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xTaskIsPrivileged = pdTRUE; + } + + return xTaskIsPrivileged; +} +/*-----------------------------------------------------------*/ + +static void prvRestoreContextOfFirstTask( void ) +{ + __asm volatile + ( + " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n" + " ldr r0, [r0] \n" + " msr msp, r0 \n" /* Set the msp back to the start of the stack. */ + " \n" + /*------------ Program MPU. ------------ */ + " ldr r3, =pxCurrentTCB \n" /* r3 = =pxCurrentTCB. */ + " ldr r2, [r3] \n" /* r2 = pxCurrentTCB. */ + " add r2, r2, #4 \n" /* r2 = Second item in the TCB which is xMPUSettings. */ + " \n" + " dmb \n" /* Complete outstanding transfers before disabling MPU. */ + " ldr r0, =0xe000ed94 \n" /* MPU_CTRL register. */ + " ldr r3, [r0] \n" /* Read the value of MPU_CTRL. */ + " bic r3, #1 \n" /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */ + " str r3, [r0] \n" /* Disable MPU. */ + " \n" + " ldr r0, =0xe000ed9c \n" /* Region Base Address register. */ + " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */ + " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */ + " \n" + " ldr r0, =0xe000ed94 \n" /* MPU_CTRL register. */ + " ldr r3, [r0] \n" /* Read the value of MPU_CTRL. */ + " orr r3, #1 \n" /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */ + " str r3, [r0] \n" /* Enable MPU. */ + " dsb \n" /* Force memory writes before continuing. */ + " \n" + /*---------- Restore Context. ---------- */ + " ldr r3, =pxCurrentTCB \n" /* r3 = =pxCurrentTCB. */ + " ldr r2, [r3] \n" /* r2 = pxCurrentTCB. */ + " ldr r1, [r2] \n" /* r1 = Location of saved context in TCB. */ + " \n" + " ldmdb r1!, {r0, r4-r11} \n" /* r0 contains PSP after the hardware had saved context. r4-r11 contain hardware saved context. */ + " msr psp, r0 \n" + " stmia r0, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */ + " ldmdb r1!, {r3-r11, lr} \n" /* r3 contains CONTROL register. r4-r11 and LR restored. */ + " msr control, r3 \n" + " str r1, [r2] \n" /* Save the location where the context should be saved next as the first member of TCB. */ + " \n" + " mov r0, #0 \n" + " msr basepri, r0 \n" + " bx lr \n" + " \n" + " .ltorg \n" /* Assemble current literal pool to avoid offset-out-of-bound errors with lto. */ + ); +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions vPortSVCHandler and + * xPortPendSVHandler for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * vPortSVCHandler and xPortPendSVHandler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( configASSERT_DEFINED == 1 ) + { + volatile uint8_t ucOriginalPriority; + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions + * to ensure interrupt entry is as fast and simple as possible. + * + * Save the interrupt priority value that is about to be clobbered. */ + ucOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to all + * possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + + /* Restore the clobbered interrupt priority register to its original + * value. */ + *pucFirstUserPriorityRegister = ucOriginalPriority; + } + #endif /* configASSERT_DEFINED */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + + /* Configure the regions in the MPU that are common to all tasks. */ + prvSetupMPU(); + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + { + xSchedulerRunning = pdTRUE; + } + #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + /* Start the first task. */ + __asm volatile ( + " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n" + " ldr r0, [r0] \n" + " msr msp, r0 \n" /* Set the msp back to the start of the stack. */ + " cpsie i \n" /* Globally enable interrupts. */ + " cpsie f \n" + " dsb \n" + " isb \n" + " svc %0 \n" /* System call to start first task. */ + " nop \n" + " .ltorg \n" + ::"i" ( portSVC_START_SCHEDULER ) : "memory" ); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + #if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + } + #else /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + #endif /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */ +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + #if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + } + #else /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */ + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + #endif /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */ +} +/*-----------------------------------------------------------*/ + +void xPortPendSVHandler( void ) +{ + /* This is a naked function. */ + + __asm volatile + ( + " ldr r3, =pxCurrentTCB \n" /* r3 = =pxCurrentTCB. */ + " ldr r2, [r3] \n" /* r2 = pxCurrentTCB. */ + " ldr r1, [r2] \n" /* r1 = Location where the context should be saved. */ + " \n" + /*------------ Save Context. ----------- */ + " mrs r3, control \n" + " mrs r0, psp \n" + " isb \n" + " \n" + " stmia r1!, {r3-r11, lr} \n" /* Store CONTROL register, r4-r11 and LR. */ + " ldmia r0, {r4-r11} \n" /* Copy hardware saved context into r4-r11. */ + " stmia r1!, {r0, r4-r11} \n" /* Store original PSP (after hardware has saved context) and the hardware saved context. */ + " str r1, [r2] \n" /* Save the location from where the context should be restored as the first member of TCB. */ + " \n" + /*---------- Select next task. --------- */ + " mov r0, %0 \n" + " msr basepri, r0 \n" + " dsb \n" + " isb \n" + " bl vTaskSwitchContext \n" + " mov r0, #0 \n" + " msr basepri, r0 \n" + " \n" + /*------------ Program MPU. ------------ */ + " ldr r3, =pxCurrentTCB \n" /* r3 = =pxCurrentTCB. */ + " ldr r2, [r3] \n" /* r2 = pxCurrentTCB. */ + " add r2, r2, #4 \n" /* r2 = Second item in the TCB which is xMPUSettings. */ + " \n" + " dmb \n" /* Complete outstanding transfers before disabling MPU. */ + " ldr r0, =0xe000ed94 \n" /* MPU_CTRL register. */ + " ldr r3, [r0] \n" /* Read the value of MPU_CTRL. */ + " bic r3, #1 \n" /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */ + " str r3, [r0] \n" /* Disable MPU. */ + " \n" + " ldr r0, =0xe000ed9c \n" /* Region Base Address register. */ + " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */ + " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */ + " \n" + " ldr r0, =0xe000ed94 \n" /* MPU_CTRL register. */ + " ldr r3, [r0] \n" /* Read the value of MPU_CTRL. */ + " orr r3, #1 \n" /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */ + " str r3, [r0] \n" /* Enable MPU. */ + " dsb \n" /* Force memory writes before continuing. */ + " \n" + /*---------- Restore Context. ---------- */ + " ldr r3, =pxCurrentTCB \n" /* r3 = =pxCurrentTCB. */ + " ldr r2, [r3] \n" /* r2 = pxCurrentTCB. */ + " ldr r1, [r2] \n" /* r1 = Location of saved context in TCB. */ + " \n" + " ldmdb r1!, {r0, r4-r11} \n" /* r0 contains PSP after the hardware had saved context. r4-r11 contain hardware saved context. */ + " msr psp, r0 \n" + " stmia r0, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */ + " ldmdb r1!, {r3-r11, lr} \n" /* r3 contains CONTROL register. r4-r11 and LR restored. */ + " msr control, r3 \n" + " \n" + " str r1, [r2] \n" /* Save the location where the context should be saved next as the first member of TCB. */ + " bx lr \n" + " \n" + " .ltorg \n" /* Assemble current literal pool to avoid offset-out-of-bound errors with lto. */ + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + uint32_t ulDummy; + + ulDummy = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy ); +} +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) +{ + /* Stop and clear the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE ); +} +/*-----------------------------------------------------------*/ + +static void prvSetupMPU( void ) +{ + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __FLASH_segment_start__; + extern uint32_t * __FLASH_segment_end__; + extern uint32_t * __privileged_data_start__; + extern uint32_t * __privileged_data_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __FLASH_segment_start__[]; + extern uint32_t __FLASH_segment_end__[]; + extern uint32_t __privileged_data_start__[]; + extern uint32_t __privileged_data_end__[]; + #endif /* if defined( __ARMCC_VERSION ) */ + + /* Ensure that the device has the expected MPU type */ + configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ); + + /* Check the expected MPU is present. */ + if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ) + { + /* First setup the unprivileged flash for unprivileged read only access. */ + portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */ + ( portMPU_REGION_VALID ) | + ( portUNPRIVILEGED_FLASH_REGION ); + + portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) | + ( portMPU_REGION_CACHEABLE_BUFFERABLE ) | + ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) | + ( portMPU_REGION_ENABLE ); + + /* Setup the privileged flash for privileged only access. This is where + * the kernel code is * placed. */ + portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_functions_start__ ) | /* Base address. */ + ( portMPU_REGION_VALID ) | + ( portPRIVILEGED_FLASH_REGION ); + + portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) | + ( portMPU_REGION_CACHEABLE_BUFFERABLE ) | + ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __privileged_functions_start__ ) ) | + ( portMPU_REGION_ENABLE ); + + /* Setup the privileged data RAM region. This is where the kernel data + * is placed. */ + portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */ + ( portMPU_REGION_VALID ) | + ( portPRIVILEGED_RAM_REGION ); + + portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_CACHEABLE_BUFFERABLE ) | + ( portMPU_REGION_EXECUTE_NEVER ) | + prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) | + ( portMPU_REGION_ENABLE ); + + /* By default allow everything to access the general peripherals. The + * system peripherals and registers are protected. */ + portMPU_REGION_BASE_ADDRESS_REG = ( portPERIPHERALS_START_ADDRESS ) | + ( portMPU_REGION_VALID ) | + ( portGENERAL_PERIPHERALS_REGION ); + + portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) | + ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) | + ( portMPU_REGION_ENABLE ); + + /* Enable the memory fault exception. */ + portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE; + + /* Enable the MPU with the background region configured. */ + portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE ); + } +} +/*-----------------------------------------------------------*/ + +static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) +{ + uint32_t ulRegionSize, ulReturnValue = 4; + + /* 32 is the smallest region size, 31 is the largest valid value for + * ulReturnValue. */ + for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) ) + { + if( ulActualSizeInBytes <= ulRegionSize ) + { + break; + } + else + { + ulReturnValue++; + } + } + + /* Shift the code by one before returning so it can be written directly + * into the the correct bit position of the attribute register. */ + return( ulReturnValue << 1UL ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " mrs r0, control \n" /* r0 = CONTROL. */ + " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + " ite ne \n" + " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + " bx lr \n" /* Return. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vResetPrivilege( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " mrs r0, control \n" /* r0 = CONTROL. */ + " orr r0, #1 \n" /* r0 = r0 | 1. */ + " msr control, r0 \n" /* CONTROL = r0. */ + " bx lr \n" /* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vPortSwitchToUserMode( void ) +{ + /* Load the current task's MPU settings from its TCB. */ + xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); + + /* Mark the task as unprivileged. */ + xTaskMpuSettings->ulTaskFlags &= ( ~( portTASK_IS_PRIVILEGED_FLAG ) ); + + /* Lower the processor's privilege level. */ + vResetPrivilege(); +} +/*-----------------------------------------------------------*/ + +void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + configSTACK_DEPTH_TYPE uxStackDepth ) +{ + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __SRAM_segment_start__; + extern uint32_t * __SRAM_segment_end__; + extern uint32_t * __privileged_data_start__; + extern uint32_t * __privileged_data_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __SRAM_segment_start__[]; + extern uint32_t __SRAM_segment_end__[]; + extern uint32_t __privileged_data_start__[]; + extern uint32_t __privileged_data_end__[]; + #endif /* if defined( __ARMCC_VERSION ) */ + + int32_t lIndex; + uint32_t ul; + + if( xRegions == NULL ) + { + /* No MPU regions are specified so allow access to all RAM. */ + xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress = + ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */ + ( portMPU_REGION_VALID ) | + ( portSTACK_REGION ); /* Region number. */ + + xMPUSettings->xRegion[ 0 ].ulRegionAttribute = + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_CACHEABLE_BUFFERABLE ) | + ( portMPU_REGION_EXECUTE_NEVER ) | + ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) | + ( portMPU_REGION_ENABLE ); + + xMPUSettings->xRegionSettings[ 0 ].ulRegionStartAddress = ( uint32_t ) __SRAM_segment_start__; + xMPUSettings->xRegionSettings[ 0 ].ulRegionEndAddress = ( uint32_t ) __SRAM_segment_end__; + xMPUSettings->xRegionSettings[ 0 ].ulRegionPermissions = ( tskMPU_READ_PERMISSION | + tskMPU_WRITE_PERMISSION ); + + /* Invalidate user configurable regions. */ + for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ ) + { + xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID ); + xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL; + xMPUSettings->xRegionSettings[ ul ].ulRegionStartAddress = 0UL; + xMPUSettings->xRegionSettings[ ul ].ulRegionEndAddress = 0UL; + xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = 0UL; + } + } + else + { + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that the + * stack region has already been configured. */ + if( uxStackDepth > 0 ) + { + /* Define the region that allows access to the stack. */ + xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress = + ( ( uint32_t ) pxBottomOfStack ) | + ( portMPU_REGION_VALID ) | + ( portSTACK_REGION ); /* Region number. */ + + xMPUSettings->xRegion[ 0 ].ulRegionAttribute = + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ) | + ( prvGetMPURegionSizeSetting ( ( uint32_t ) ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) ) ) | + ( portMPU_REGION_CACHEABLE_BUFFERABLE ) | + ( portMPU_REGION_ENABLE ); + xMPUSettings->xRegionSettings[ 0 ].ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + xMPUSettings->xRegionSettings[ 0 ].ulRegionEndAddress = ( uint32_t ) ( ( uint32_t ) ( pxBottomOfStack ) + + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1UL ); + xMPUSettings->xRegionSettings[ 0 ].ulRegionPermissions = ( tskMPU_READ_PERMISSION | + tskMPU_WRITE_PERMISSION ); + } + + lIndex = 0; + + for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ ) + { + if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL ) + { + /* Translate the generic region definition contained in + * xRegions into the CM3 specific MPU settings that are then + * stored in xMPUSettings. */ + xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = + ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) | + ( portMPU_REGION_VALID ) | + ( ul - 1UL ); /* Region number. */ + + xMPUSettings->xRegion[ ul ].ulRegionAttribute = + ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) | + ( xRegions[ lIndex ].ulParameters ) | + ( portMPU_REGION_ENABLE ); + + xMPUSettings->xRegionSettings[ ul ].ulRegionStartAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress; + xMPUSettings->xRegionSettings[ ul ].ulRegionEndAddress = ( uint32_t ) ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1UL ); + xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = 0UL; + + if( ( ( xRegions[ lIndex ].ulParameters & portMPU_REGION_READ_ONLY ) == portMPU_REGION_READ_ONLY ) || + ( ( xRegions[ lIndex ].ulParameters & portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ) == portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ) ) + { + xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = tskMPU_READ_PERMISSION; + } + + if( ( xRegions[ lIndex ].ulParameters & portMPU_REGION_READ_WRITE ) == portMPU_REGION_READ_WRITE ) + { + xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION ); + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID ); + xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL; + xMPUSettings->xRegionSettings[ ul ].ulRegionStartAddress = 0UL; + xMPUSettings->xRegionSettings[ ul ].ulRegionEndAddress = 0UL; + xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = 0UL; + } + + lIndex++; + } + } +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, + uint32_t ulBufferLength, + uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */ + + { + uint32_t i, ulBufferStartAddress, ulBufferEndAddress; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE ) + { + ulBufferStartAddress = ( uint32_t ) pvBuffer; + ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL ); + + for( i = 0; i < portTOTAL_NUM_REGIONS_IN_TCB; i++ ) + { + if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress, + xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress, + xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) && + portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress, + xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress, + xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) && + portIS_AUTHORIZED( ulAccessRequested, xTaskMpuSettings->xRegionSettings[ i ].ulRegionPermissions ) ) + { + xAccessGranted = pdTRUE; + break; + } + } + } + } + + return xAccessGranted; + } + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* configASSERT_DEFINED */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings; + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else + { + xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 ) + { + xAccessGranted = pdTRUE; + } + } + } + + return xAccessGranted; + } + + #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + ( void ) lInternalIndexOfKernelObject; + + /* If Access Control List feature is not used, all the tasks have + * access to all the kernel objects. */ + return pdTRUE; + } + + #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM3_MPU/portmacro.h b/portable/GCC/ARM_CM3_MPU/portmacro.h new file mode 100644 index 000000000..a2e6883c0 --- /dev/null +++ b/portable/GCC/ARM_CM3_MPU/portmacro.h @@ -0,0 +1,395 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* MPU specific constants. */ +#define portUSING_MPU_WRAPPERS 1 +#define portPRIVILEGE_BIT ( 0x80000000UL ) + +#define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL ) +#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL ) +#define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL ) +#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL ) +#define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ( 0x02UL << 24UL ) +#define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL ) +#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL ) + +#define portSTACK_REGION ( 3UL ) +#define portGENERAL_PERIPHERALS_REGION ( 4UL ) +#define portUNPRIVILEGED_FLASH_REGION ( 5UL ) +#define portPRIVILEGED_FLASH_REGION ( 6UL ) +#define portPRIVILEGED_RAM_REGION ( 7UL ) +#define portFIRST_CONFIGURABLE_REGION ( 0UL ) +#define portLAST_CONFIGURABLE_REGION ( 2UL ) +#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) +#define portTOTAL_NUM_REGIONS_IN_TCB ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +typedef struct MPU_REGION_REGISTERS +{ + uint32_t ulRegionBaseAddress; + uint32_t ulRegionAttribute; +} xMPU_REGION_REGISTERS; + +typedef struct MPU_REGION_SETTINGS +{ + uint32_t ulRegionStartAddress; + uint32_t ulRegionEndAddress; + uint32_t ulRegionPermissions; +} xMPU_REGION_SETTINGS; + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + #ifndef configSYSTEM_CALL_STACK_SIZE + #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. + #endif + + typedef struct SYSTEM_CALL_STACK_INFO + { + uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; + uint32_t * pulSystemCallStack; + uint32_t * pulTaskStack; + uint32_t ulLinkRegisterAtSystemCallEntry; + } xSYSTEM_CALL_STACK_INFO; + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/* + * +------------------------------+-------------------------------+-----+ + * | CONTROL, r4-r11, EXC_RETURN | PSP, r0-r3, r12, LR, PC, xPSR | | + * +------------------------------+-------------------------------+-----+ + * + * <-----------------------------><-------------------------------><----> + * 10 9 1 + */ +#define MAX_CONTEXT_SIZE ( 20 ) + +/* Size of an Access Control List (ACL) entry in bits. */ +#define portACL_ENTRY_SIZE_BITS ( 32U ) + +/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ +#define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) +#define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) + +typedef struct MPU_SETTINGS +{ + xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS_IN_TCB ]; + xMPU_REGION_SETTINGS xRegionSettings[ portTOTAL_NUM_REGIONS_IN_TCB ]; + uint32_t ulContext[ MAX_CONTEXT_SIZE ]; + uint32_t ulTaskFlags; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo; + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ]; + #endif + #endif +} xMPU_SETTINGS; + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/* SVC numbers for various services. */ +#define portSVC_START_SCHEDULER 100 +#define portSVC_YIELD 101 +#define portSVC_RAISE_PRIVILEGE 102 +#define portSVC_SYSTEM_CALL_EXIT 103 + +/* Scheduler utilities. */ + +#define portYIELD() __asm volatile ( " SVC %0 \n" ::"i" ( portSVC_YIELD ) : "memory" ) +#define portYIELD_WITHIN_API() \ + { \ + /* Set a PendSV to request a context switch. */ \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + \ + /* Barriers are normally not required but do ensure the code is completely \ + * within the specified behaviour for the architecture. */ \ + __asm volatile ( "dsb" ::: "memory" ); \ + __asm volatile ( "isb" ); \ + } + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x ) +#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() +#define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not necessary for to use this port. They are defined so the common demo files + * (which build with all the ports) will build. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +/* Architecture specific optimisations. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + +/* Generic helper function. */ + __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint8_t ucReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ucReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif + +/* portNOP() is not required by this port. */ +#define portNOP() + +#define portINLINE __inline + +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif +/*-----------------------------------------------------------*/ + +extern BaseType_t xIsPrivileged( void ); +extern void vResetPrivilege( void ); +extern void vPortSwitchToUserMode( void ); + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +#define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + */ +#define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ +#define portRESET_PRIVILEGE() vResetPrivilege() + +/** + * @brief Make a task unprivileged. + * + * It must be called from privileged tasks only. Calling it from unprivileged + * task will result in a memory protection fault. + */ +#define portSWITCH_TO_USER_MODE() vPortSwitchToUserMode() +/*-----------------------------------------------------------*/ + +extern BaseType_t xPortIsTaskPrivileged( void ); + +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ +#define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() +/*-----------------------------------------------------------*/ + +portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} + +/*-----------------------------------------------------------*/ + +portFORCE_INLINE static void vPortRaiseBASEPRI( void ) +{ + uint32_t ulNewBASEPRI; + + __asm volatile + ( + " mov %0, %1 \n" \ + " msr basepri, %0 \n" \ + " isb \n" \ + " dsb \n" \ + : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); +} + +/*-----------------------------------------------------------*/ + +portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void ) +{ + uint32_t ulOriginalBASEPRI, ulNewBASEPRI; + + __asm volatile + ( + " mrs %0, basepri \n" \ + " mov %1, %2 \n" \ + " msr basepri, %1 \n" \ + " isb \n" \ + " dsb \n" \ + : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); + + /* This return will not be reached but is necessary to prevent compiler + * warnings. */ + return ulOriginalBASEPRI; +} +/*-----------------------------------------------------------*/ + +portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) +{ + __asm volatile + ( + " msr basepri, %0 " ::"r" ( ulNewMaskValue ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) + +#ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY + #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. *www.FreeRTOS.org/FreeRTOS-V10.3.x.html" + #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0 +#endif +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/ARM_CM4F/port.c b/portable/GCC/ARM_CM4F/port.c new file mode 100644 index 000000000..e6b481b1d --- /dev/null +++ b/portable/GCC/ARM_CM4F/port.c @@ -0,0 +1,907 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ARM CM4F port. +*----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#ifndef __ARM_FP + #error This port can only be used when the project options are configured to enable hardware floating point support. +#endif + +/* Prototype of all Interrupt Service Routines (ISRs). */ +typedef void ( * portISR_t )( void ); + +/* Constants required to manipulate the core. Registers first... */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +/* ...then bits in the registers. */ +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) + +/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7 + * r0p1 port. */ +#define portCPUID ( *( ( volatile uint32_t * ) 0xE000ed00 ) ) +#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL ) +#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL ) + +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL ) +#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL ) + +/* Constants used to check the installation of the FreeRTOS interrupt handlers. */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xE000ED08 ) ) +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) + +/* Constants required to check the validity of an interrupt priority. */ +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) + +/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */ +#define portVECTACTIVE_MASK ( 0xFFUL ) + +/* Constants required to manipulate the VFP. */ +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */ +#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) +#define portINITIAL_EXC_RETURN ( 0xfffffffd ) + +/* The systick is a 24-bit counter. */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/* For strict compliance with the Cortex-M spec the task start address should + * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */ +#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL ) + +/* A fiddle factor to estimate the number of SysTick counts that would have + * occurred while the SysTick counter is stopped during tickless idle + * calculations. */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) + +/* Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/* Let the user override the pre-loading of the initial LR with the address of + * prvTaskExitError() in case it messes up unwinding of the stack in the + * debugger. */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ); + +/* + * Exception handlers. + */ +void xPortPendSVHandler( void ) __attribute__( ( naked ) ); +void xPortSysTickHandler( void ); +void vPortSVCHandler( void ) __attribute__( ( naked ) ); + +/* + * Start first task is a separate function so it can be tested in isolation. + */ +static void prvPortStartFirstTask( void ) __attribute__( ( naked ) ); + +/* + * Function to enable the VFP. + */ +static void vPortEnableVFP( void ) __attribute__( ( naked ) ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* Each task maintains its own interrupt status in the critical nesting + * variable. */ +static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +/* + * The number of SysTick increments that make up one tick period. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulTimerCountsForOneTick = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * The maximum number of tick periods that can be suppressed is limited by the + * 24 bit resolution of the SysTick timer. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t xMaximumPossibleSuppressedTicks = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Compensate for the CPU cycles that pass while the SysTick is stopped (low + * power functionality only. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( configASSERT_DEFINED == 1 ) + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16; +#endif /* configASSERT_DEFINED */ + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + + /* Offset added to account for the way the MCU uses the stack on entry/exit + * of interrupts, and to ensure alignment. */ + pxTopOfStack--; + + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + + /* Save code space by skipping register initialisation. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + + /* A save method is being used that requires each task to maintain its + * own exec return value. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; + + pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ + configASSERT( uxCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being defined + * but never called. ulDummy is used purely to quieten other warnings + * about code appearing after this function is called - making ulDummy + * volatile makes the compiler think the function could return and + * therefore not output an 'unreachable code' warning for code that appears + * after it. */ + } +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler( void ) +{ + __asm volatile ( + " ldr r3, =pxCurrentTCB \n" /* Restore the context. */ + " ldr r1, [r3] \n" /* Get the pxCurrentTCB address. */ + " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */ + " ldmia r0!, {r4-r11, r14} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */ + " msr psp, r0 \n" /* Restore the task stack pointer. */ + " isb \n" + " mov r0, #0 \n" + " msr basepri, r0 \n" + " bx r14 \n" + " \n" + " .ltorg \n" + ); +} +/*-----------------------------------------------------------*/ + +static void prvPortStartFirstTask( void ) +{ + /* Start the first task. This also clears the bit that indicates the FPU is + * in use in case the FPU was used before the scheduler was started - which + * would otherwise result in the unnecessary leaving of space in the SVC stack + * for lazy saving of FPU registers. */ + __asm volatile ( + " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n" + " ldr r0, [r0] \n" + " msr msp, r0 \n" /* Set the msp back to the start of the stack. */ + " mov r0, #0 \n" /* Clear the bit that indicates the FPU is in use, see comment above. */ + " msr control, r0 \n" + " cpsie i \n" /* Globally enable interrupts. */ + " cpsie f \n" + " dsb \n" + " isb \n" + " svc 0 \n" /* System call to start first task. */ + " nop \n" + " .ltorg \n" + ); +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + /* This port can be used on all revisions of the Cortex-M7 core other than + * the r0p1 parts. r0p1 parts should use the port from the + * /source/portable/GCC/ARM_CM7/r0p1 directory. */ + configASSERT( portCPUID != portCORTEX_M7_r0p1_ID ); + configASSERT( portCPUID != portCORTEX_M7_r0p0_ID ); + + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions vPortSVCHandler and + * xPortPendSVHandler for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * vPortSVCHandler and xPortPendSVHandler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( configASSERT_DEFINED == 1 ) + { + volatile uint8_t ucOriginalPriority; + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * Save the interrupt priority value that is about to be clobbered. */ + ucOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to all + * possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + + /* Restore the clobbered interrupt priority register to its original + * value. */ + *pucFirstUserPriorityRegister = ucOriginalPriority; + } + #endif /* configASSERT_DEFINED */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + /* Ensure the VFP is enabled - it should be anyway. */ + vPortEnableVFP(); + + /* Lazy save always. */ + *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; + + /* Start the first task. */ + prvPortStartFirstTask(); + + /* Should never get here as the tasks will now be executing! Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimisation does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ + if( uxCriticalNesting == 1 ) + { + configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void xPortPendSVHandler( void ) +{ + /* This is a naked function. */ + + __asm volatile + ( + " mrs r0, psp \n" + " isb \n" + " \n" + " ldr r3, =pxCurrentTCB \n" /* Get the location of the current TCB. */ + " ldr r2, [r3] \n" + " \n" + " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, push high vfp registers. */ + " it eq \n" + " vstmdbeq r0!, {s16-s31} \n" + " \n" + " stmdb r0!, {r4-r11, r14} \n" /* Save the core registers. */ + " str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */ + " \n" + " stmdb sp!, {r0, r3} \n" + " mov r0, %0 \n" + " msr basepri, r0 \n" + " dsb \n" + " isb \n" + " bl vTaskSwitchContext \n" + " mov r0, #0 \n" + " msr basepri, r0 \n" + " ldmia sp!, {r0, r3} \n" + " \n" + " ldr r1, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. */ + " ldr r0, [r1] \n" + " \n" + " ldmia r0!, {r4-r11, r14} \n" /* Pop the core registers. */ + " \n" + " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, pop the high vfp registers too. */ + " it eq \n" + " vldmiaeq r0!, {s16-s31} \n" + " \n" + " msr psp, r0 \n" + " isb \n" + " \n" + #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */ + #if WORKAROUND_PMU_CM001 == 1 + " push { r14 } \n" + " pop { pc } \n" + #endif + #endif + " \n" + " bx r14 \n" + " \n" + " .ltorg \n" + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + /* The SysTick runs at the lowest interrupt priority, so when this interrupt + * executes all interrupts must be unmasked. There is therefore no need to + * save and then restore the interrupt mask value as its value is already + * known. */ + portDISABLE_INTERRUPTS(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + + /* A context switch is required. Context switching is performed in + * the PendSV interrupt. Pend the PendSV interrupt. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + portENABLE_INTERRUPTS(); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the cpsid instruction + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } + +#endif /* #if configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and clear the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); +} +/*-----------------------------------------------------------*/ + +/* This is a naked function. */ +static void vPortEnableVFP( void ) +{ + __asm volatile + ( + " ldr.w r0, =0xE000ED88 \n" /* The FPU enable bits are in the CPACR. */ + " ldr r1, [r0] \n" + " \n" + " orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */ + " str r1, [r0] \n" + " bx r14 \n" + " .ltorg \n" + ); +} +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* configASSERT_DEFINED */ diff --git a/portable/GCC/ARM_CM4F/portmacro.h b/portable/GCC/ARM_CM4F/portmacro.h new file mode 100644 index 000000000..0a91d7c92 --- /dev/null +++ b/portable/GCC/ARM_CM4F/portmacro.h @@ -0,0 +1,266 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_64_BITS ) + typedef uint64_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffffffffffULL +#else /* if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) */ + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif /* if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) */ +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/* Scheduler utilities. */ +#define portYIELD() \ + { \ + /* Set a PendSV to request a context switch. */ \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + \ + /* Barriers are normally not required but do ensure the code is completely \ + * within the specified behaviour for the architecture. */ \ + __asm volatile ( "dsb" ::: "memory" ); \ + __asm volatile ( "isb" ); \ + } + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portYIELD(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x ) +#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() +#define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not necessary for to use this port. They are defined so the common demo files + * (which build with all the ports) will build. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +/* Tickless idle/low power functionality. */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specific optimisations. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + +/* Generic helper function. */ + __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint8_t ucReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ucReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif + +/* portNOP() is not required by this port. */ +#define portNOP() + +#define portINLINE __inline + +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif + +portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} + +/*-----------------------------------------------------------*/ + +portFORCE_INLINE static void vPortRaiseBASEPRI( void ) +{ + uint32_t ulNewBASEPRI; + + __asm volatile + ( + " mov %0, %1 \n" \ + " msr basepri, %0 \n" \ + " isb \n" \ + " dsb \n" \ + : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); +} + +/*-----------------------------------------------------------*/ + +portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void ) +{ + uint32_t ulOriginalBASEPRI, ulNewBASEPRI; + + __asm volatile + ( + " mrs %0, basepri \n" \ + " mov %1, %2 \n" \ + " msr basepri, %1 \n" \ + " isb \n" \ + " dsb \n" \ + : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); + + /* This return will not be reached but is necessary to prevent compiler + * warnings. */ + return ulOriginalBASEPRI; +} +/*-----------------------------------------------------------*/ + +portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) +{ + __asm volatile + ( + " msr basepri, %0 " ::"r" ( ulNewMaskValue ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c new file mode 100644 index 000000000..428e6e84a --- /dev/null +++ b/portable/GCC/ARM_CM4_MPU/mpu_wrappers_v2_asm.c @@ -0,0 +1,2067 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" +#include "event_groups.h" +#include "stream_buffer.h" +#include "mpu_prototypes.h" +#include "mpu_syscall_numbers.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE +/*-----------------------------------------------------------*/ + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + #if ( INCLUDE_xTaskDelayUntil == 1 ) + + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskDelayUntilImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskDelayUntil_Unpriv \n" + " MPU_xTaskDelayUntil_Priv: \n" + " b MPU_xTaskDelayUntilImpl \n" + " MPU_xTaskDelayUntil_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskAbortDelayImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskAbortDelay_Unpriv \n" + " MPU_xTaskAbortDelay_Priv: \n" + " b MPU_xTaskAbortDelayImpl \n" + " MPU_xTaskAbortDelay_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskDelay == 1 ) + + void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskDelayImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskDelay_Unpriv \n" + " MPU_vTaskDelay_Priv: \n" + " b MPU_vTaskDelayImpl \n" + " MPU_vTaskDelay_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskPriorityGet == 1 ) + + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskPriorityGetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskPriorityGet_Unpriv \n" + " MPU_uxTaskPriorityGet_Priv: \n" + " b MPU_uxTaskPriorityGetImpl \n" + " MPU_uxTaskPriorityGet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_eTaskGetState == 1 ) + + eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_eTaskGetStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_eTaskGetState_Unpriv \n" + " MPU_eTaskGetState_Priv: \n" + " b MPU_eTaskGetStateImpl \n" + " MPU_eTaskGetState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory" + ); + } + + #endif /* if ( INCLUDE_eTaskGetState == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskGetInfoImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskGetInfo_Unpriv \n" + " MPU_vTaskGetInfo_Priv: \n" + " b MPU_vTaskGetInfoImpl \n" + " MPU_vTaskGetInfo_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory" + ); + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) + + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetIdleTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetIdleTaskHandle_Unpriv \n" + " MPU_xTaskGetIdleTaskHandle_Priv: \n" + " b MPU_xTaskGetIdleTaskHandleImpl \n" + " MPU_xTaskGetIdleTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + + void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSuspendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSuspend_Unpriv \n" + " MPU_vTaskSuspend_Priv: \n" + " b MPU_vTaskSuspendImpl \n" + " MPU_vTaskSuspend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + + void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskResumeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskResume_Unpriv \n" + " MPU_vTaskResume_Priv: \n" + " b MPU_vTaskResumeImpl \n" + " MPU_vTaskResume_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + TickType_t MPU_xTaskGetTickCount( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetTickCountImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetTickCount_Unpriv \n" + " MPU_xTaskGetTickCount_Priv: \n" + " b MPU_xTaskGetTickCountImpl \n" + " MPU_xTaskGetTickCount_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetNumberOfTasksImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetNumberOfTasks_Unpriv \n" + " MPU_uxTaskGetNumberOfTasks_Priv: \n" + " b MPU_uxTaskGetNumberOfTasksImpl \n" + " MPU_uxTaskGetNumberOfTasks_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetRunTimeCounterImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetRunTimeCounter_Unpriv \n" + " MPU_ulTaskGetRunTimeCounter_Priv: \n" + " b MPU_ulTaskGetRunTimeCounterImpl \n" + " MPU_ulTaskGetRunTimeCounter_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetRunTimePercentImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetRunTimePercent_Unpriv \n" + " MPU_ulTaskGetRunTimePercent_Priv: \n" + " b MPU_ulTaskGetRunTimePercentImpl \n" + " MPU_ulTaskGetRunTimePercent_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetIdleRunTimePercentImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv \n" + " MPU_ulTaskGetIdleRunTimePercent_Priv: \n" + " b MPU_ulTaskGetIdleRunTimePercentImpl \n" + " MPU_ulTaskGetIdleRunTimePercent_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetIdleRunTimeCounterImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv \n" + " MPU_ulTaskGetIdleRunTimeCounter_Priv: \n" + " b MPU_ulTaskGetIdleRunTimeCounterImpl \n" + " MPU_ulTaskGetIdleRunTimeCounter_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetApplicationTaskTagImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetApplicationTaskTag_Unpriv \n" + " MPU_vTaskSetApplicationTaskTag_Priv: \n" + " b MPU_vTaskSetApplicationTaskTagImpl \n" + " MPU_vTaskSetApplicationTaskTag_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory" + ); + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetApplicationTaskTagImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetApplicationTaskTag_Unpriv \n" + " MPU_xTaskGetApplicationTaskTag_Priv: \n" + " b MPU_xTaskGetApplicationTaskTagImpl \n" + " MPU_xTaskGetApplicationTaskTag_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory" + ); + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetThreadLocalStoragePointerImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv \n" + " MPU_vTaskSetThreadLocalStoragePointer_Priv: \n" + " b MPU_vTaskSetThreadLocalStoragePointerImpl \n" + " MPU_vTaskSetThreadLocalStoragePointer_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory" + ); + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv \n" + " MPU_pvTaskGetThreadLocalStoragePointer_Priv: \n" + " b MPU_pvTaskGetThreadLocalStoragePointerImpl \n" + " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory" + ); + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetSystemStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetSystemState_Unpriv \n" + " MPU_uxTaskGetSystemState_Priv: \n" + " b MPU_uxTaskGetSystemStateImpl \n" + " MPU_uxTaskGetSystemState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory" + ); + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) + + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetStackHighWaterMarkImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetStackHighWaterMark_Unpriv \n" + " MPU_uxTaskGetStackHighWaterMark_Priv: \n" + " b MPU_uxTaskGetStackHighWaterMarkImpl \n" + " MPU_uxTaskGetStackHighWaterMark_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetStackHighWaterMark2Impl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv \n" + " MPU_uxTaskGetStackHighWaterMark2_Priv: \n" + " b MPU_uxTaskGetStackHighWaterMark2Impl \n" + " MPU_uxTaskGetStackHighWaterMark2_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) + + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetCurrentTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetCurrentTaskHandle_Unpriv \n" + " MPU_xTaskGetCurrentTaskHandle_Priv: \n" + " b MPU_xTaskGetCurrentTaskHandleImpl \n" + " MPU_xTaskGetCurrentTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory" + ); + } + + #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetSchedulerState == 1 ) + + BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetSchedulerStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetSchedulerState_Unpriv \n" + " MPU_xTaskGetSchedulerState_Priv: \n" + " b MPU_xTaskGetSchedulerStateImpl \n" + " MPU_xTaskGetSchedulerState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */ +/*-----------------------------------------------------------*/ + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetTimeOutStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetTimeOutState_Unpriv \n" + " MPU_vTaskSetTimeOutState_Priv: \n" + " b MPU_vTaskSetTimeOutStateImpl \n" + " MPU_vTaskSetTimeOutState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskCheckForTimeOutImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskCheckForTimeOut_Unpriv \n" + " MPU_xTaskCheckForTimeOut_Priv: \n" + " b MPU_xTaskCheckForTimeOutImpl \n" + " MPU_xTaskCheckForTimeOut_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotify_Unpriv \n" + " MPU_xTaskGenericNotify_Priv: \n" + " b MPU_xTaskGenericNotifyImpl \n" + " MPU_xTaskGenericNotify_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyWaitImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotifyWait_Unpriv \n" + " MPU_xTaskGenericNotifyWait_Priv: \n" + " b MPU_xTaskGenericNotifyWaitImpl \n" + " MPU_xTaskGenericNotifyWait_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGenericNotifyTakeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGenericNotifyTake_Unpriv \n" + " MPU_ulTaskGenericNotifyTake_Priv: \n" + " b MPU_ulTaskGenericNotifyTakeImpl \n" + " MPU_ulTaskGenericNotifyTake_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyStateClearImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotifyStateClear_Unpriv \n" + " MPU_xTaskGenericNotifyStateClear_Priv: \n" + " b MPU_xTaskGenericNotifyStateClearImpl \n" + " MPU_xTaskGenericNotifyStateClear_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGenericNotifyValueClearImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGenericNotifyValueClear_Unpriv \n" + " MPU_ulTaskGenericNotifyValueClear_Priv: \n" + " b MPU_ulTaskGenericNotifyValueClearImpl \n" + " MPU_ulTaskGenericNotifyValueClear_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGenericSendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGenericSend_Unpriv \n" + " MPU_xQueueGenericSend_Priv: \n" + " b MPU_xQueueGenericSendImpl \n" + " MPU_xQueueGenericSend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxQueueMessagesWaitingImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxQueueMessagesWaiting_Unpriv \n" + " MPU_uxQueueMessagesWaiting_Priv: \n" + " b MPU_uxQueueMessagesWaitingImpl \n" + " MPU_uxQueueMessagesWaiting_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxQueueSpacesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxQueueSpacesAvailable_Unpriv \n" + " MPU_uxQueueSpacesAvailable_Priv: \n" + " b MPU_uxQueueSpacesAvailableImpl \n" + " MPU_uxQueueSpacesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueReceiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueReceive_Unpriv \n" + " MPU_xQueueReceive_Priv: \n" + " b MPU_xQueueReceiveImpl \n" + " MPU_xQueueReceive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueuePeekImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueuePeek_Unpriv \n" + " MPU_xQueuePeek_Priv: \n" + " b MPU_xQueuePeekImpl \n" + " MPU_xQueuePeek_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueSemaphoreTakeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueSemaphoreTake_Unpriv \n" + " MPU_xQueueSemaphoreTake_Priv: \n" + " b MPU_xQueueSemaphoreTakeImpl \n" + " MPU_xQueueSemaphoreTake_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) + + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGetMutexHolderImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGetMutexHolder_Unpriv \n" + " MPU_xQueueGetMutexHolder_Priv: \n" + " b MPU_xQueueGetMutexHolderImpl \n" + " MPU_xQueueGetMutexHolder_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory" + ); + } + + #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueTakeMutexRecursiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueTakeMutexRecursive_Unpriv \n" + " MPU_xQueueTakeMutexRecursive_Priv: \n" + " b MPU_xQueueTakeMutexRecursiveImpl \n" + " MPU_xQueueTakeMutexRecursive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory" + ); + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGiveMutexRecursiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGiveMutexRecursive_Unpriv \n" + " MPU_xQueueGiveMutexRecursive_Priv: \n" + " b MPU_xQueueGiveMutexRecursiveImpl \n" + " MPU_xQueueGiveMutexRecursive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory" + ); + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueSelectFromSetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueSelectFromSet_Unpriv \n" + " MPU_xQueueSelectFromSet_Priv: \n" + " b MPU_xQueueSelectFromSetImpl \n" + " MPU_xQueueSelectFromSet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory" + ); + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueAddToSetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueAddToSet_Unpriv \n" + " MPU_xQueueAddToSet_Priv: \n" + " b MPU_xQueueAddToSetImpl \n" + " MPU_xQueueAddToSet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory" + ); + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vQueueAddToRegistryImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vQueueAddToRegistry_Unpriv \n" + " MPU_vQueueAddToRegistry_Priv: \n" + " b MPU_vQueueAddToRegistryImpl \n" + " MPU_vQueueAddToRegistry_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vQueueUnregisterQueueImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vQueueUnregisterQueue_Unpriv \n" + " MPU_vQueueUnregisterQueue_Priv: \n" + " b MPU_vQueueUnregisterQueueImpl \n" + " MPU_vQueueUnregisterQueue_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pcQueueGetNameImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pcQueueGetName_Unpriv \n" + " MPU_pcQueueGetName_Priv: \n" + " b MPU_pcQueueGetNameImpl \n" + " MPU_pcQueueGetName_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pvTimerGetTimerIDImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pvTimerGetTimerID_Unpriv \n" + " MPU_pvTimerGetTimerID_Priv: \n" + " b MPU_pvTimerGetTimerIDImpl \n" + " MPU_pvTimerGetTimerID_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTimerSetTimerIDImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTimerSetTimerID_Unpriv \n" + " MPU_vTimerSetTimerID_Priv: \n" + " b MPU_vTimerSetTimerIDImpl \n" + " MPU_vTimerSetTimerID_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerIsTimerActiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerIsTimerActive_Unpriv \n" + " MPU_xTimerIsTimerActive_Priv: \n" + " b MPU_xTimerIsTimerActiveImpl \n" + " MPU_xTimerIsTimerActive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv \n" + " MPU_xTimerGetTimerDaemonTaskHandle_Priv: \n" + " b MPU_xTimerGetTimerDaemonTaskHandleImpl \n" + " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGenericCommandFromTaskImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGenericCommandFromTask_Unpriv \n" + " MPU_xTimerGenericCommandFromTask_Priv: \n" + " b MPU_xTimerGenericCommandFromTaskImpl \n" + " MPU_xTimerGenericCommandFromTask_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pcTimerGetNameImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pcTimerGetName_Unpriv \n" + " MPU_pcTimerGetName_Priv: \n" + " b MPU_pcTimerGetNameImpl \n" + " MPU_pcTimerGetName_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTimerSetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTimerSetReloadMode_Unpriv \n" + " MPU_vTimerSetReloadMode_Priv: \n" + " b MPU_vTimerSetReloadModeImpl \n" + " MPU_vTimerSetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetReloadMode_Unpriv \n" + " MPU_xTimerGetReloadMode_Priv: \n" + " b MPU_xTimerGetReloadModeImpl \n" + " MPU_xTimerGetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTimerGetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTimerGetReloadMode_Unpriv \n" + " MPU_uxTimerGetReloadMode_Priv: \n" + " b MPU_uxTimerGetReloadModeImpl \n" + " MPU_uxTimerGetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetPeriodImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetPeriod_Unpriv \n" + " MPU_xTimerGetPeriod_Priv: \n" + " b MPU_xTimerGetPeriodImpl \n" + " MPU_xTimerGetPeriod_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetExpiryTimeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetExpiryTime_Unpriv \n" + " MPU_xTimerGetExpiryTime_Priv: \n" + " b MPU_xTimerGetExpiryTimeImpl \n" + " MPU_xTimerGetExpiryTime_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupWaitBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " bne MPU_xEventGroupWaitBits_Unpriv \n" + " MPU_xEventGroupWaitBits_Priv: \n" + " pop {r0} \n" + " b MPU_xEventGroupWaitBitsImpl \n" + " MPU_xEventGroupWaitBits_Unpriv: \n" + " pop {r0} \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupClearBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " bne MPU_xEventGroupClearBits_Unpriv \n" + " MPU_xEventGroupClearBits_Priv: \n" + " pop {r0} \n" + " b MPU_xEventGroupClearBitsImpl \n" + " MPU_xEventGroupClearBits_Unpriv: \n" + " pop {r0} \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupSetBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " bne MPU_xEventGroupSetBits_Unpriv \n" + " MPU_xEventGroupSetBits_Priv: \n" + " pop {r0} \n" + " b MPU_xEventGroupSetBitsImpl \n" + " MPU_xEventGroupSetBits_Unpriv: \n" + " pop {r0} \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupSyncImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " bne MPU_xEventGroupSync_Unpriv \n" + " MPU_xEventGroupSync_Priv: \n" + " pop {r0} \n" + " b MPU_xEventGroupSyncImpl \n" + " MPU_xEventGroupSync_Unpriv: \n" + " pop {r0} \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxEventGroupGetNumberImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxEventGroupGetNumber_Unpriv \n" + " MPU_uxEventGroupGetNumber_Priv: \n" + " b MPU_uxEventGroupGetNumberImpl \n" + " MPU_uxEventGroupGetNumber_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory" + ); + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vEventGroupSetNumberImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vEventGroupSetNumber_Unpriv \n" + " MPU_vEventGroupSetNumber_Priv: \n" + " b MPU_vEventGroupSetNumberImpl \n" + " MPU_vEventGroupSetNumber_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory" + ); + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " bne MPU_xStreamBufferSend_Unpriv \n" + " MPU_xStreamBufferSend_Priv: \n" + " pop {r0} \n" + " b MPU_xStreamBufferSendImpl \n" + " MPU_xStreamBufferSend_Unpriv: \n" + " pop {r0} \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferReceiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " bne MPU_xStreamBufferReceive_Unpriv \n" + " MPU_xStreamBufferReceive_Priv: \n" + " pop {r0} \n" + " b MPU_xStreamBufferReceiveImpl \n" + " MPU_xStreamBufferReceive_Unpriv: \n" + " pop {r0} \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferIsFullImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " bne MPU_xStreamBufferIsFull_Unpriv \n" + " MPU_xStreamBufferIsFull_Priv: \n" + " pop {r0} \n" + " b MPU_xStreamBufferIsFullImpl \n" + " MPU_xStreamBufferIsFull_Unpriv: \n" + " pop {r0} \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferIsEmptyImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " bne MPU_xStreamBufferIsEmpty_Unpriv \n" + " MPU_xStreamBufferIsEmpty_Priv: \n" + " pop {r0} \n" + " b MPU_xStreamBufferIsEmptyImpl \n" + " MPU_xStreamBufferIsEmpty_Unpriv: \n" + " pop {r0} \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSpacesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " bne MPU_xStreamBufferSpacesAvailable_Unpriv \n" + " MPU_xStreamBufferSpacesAvailable_Priv: \n" + " pop {r0} \n" + " b MPU_xStreamBufferSpacesAvailableImpl \n" + " MPU_xStreamBufferSpacesAvailable_Unpriv: \n" + " pop {r0} \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferBytesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " bne MPU_xStreamBufferBytesAvailable_Unpriv \n" + " MPU_xStreamBufferBytesAvailable_Priv: \n" + " pop {r0} \n" + " b MPU_xStreamBufferBytesAvailableImpl \n" + " MPU_xStreamBufferBytesAvailable_Unpriv: \n" + " pop {r0} \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSetTriggerLevelImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " bne MPU_xStreamBufferSetTriggerLevel_Unpriv \n" + " MPU_xStreamBufferSetTriggerLevel_Priv: \n" + " pop {r0} \n" + " b MPU_xStreamBufferSetTriggerLevelImpl \n" + " MPU_xStreamBufferSetTriggerLevel_Unpriv: \n" + " pop {r0} \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferNextMessageLengthBytesImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv \n" + " MPU_xStreamBufferNextMessageLengthBytes_Priv: \n" + " pop {r0} \n" + " b MPU_xStreamBufferNextMessageLengthBytesImpl \n" + " MPU_xStreamBufferNextMessageLengthBytes_Unpriv: \n" + " pop {r0} \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + +#endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ diff --git a/portable/GCC/ARM_CM4_MPU/port.c b/portable/GCC/ARM_CM4_MPU/port.c new file mode 100644 index 000000000..79f5e76d5 --- /dev/null +++ b/portable/GCC/ARM_CM4_MPU/port.c @@ -0,0 +1,1728 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2025 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ARM CM4 MPU port. +*----------------------------------------------------------*/ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "mpu_syscall_numbers.h" + +#ifndef __ARM_FP + #error This port can only be used when the project options are configured to enable hardware floating point support. +#endif + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK ( 1UL << 2UL ) +#else + +/* The way the SysTick is clocked is not modified in case it is not the same + * as the core. */ + #define portNVIC_SYSTICK_CLK ( 0 ) +#endif + +#ifndef configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS + #warning "configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS is not defined. We recommend defining it to 0 in FreeRTOSConfig.h for better security." + #define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS 1 +#endif + +/* Prototype of all Interrupt Service Routines (ISRs). */ +typedef void ( * portISR_t )( void ); + +/* Constants required to access and manipulate the NVIC. */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) ) +#define portNVIC_SYS_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) +#define portNVIC_MEM_FAULT_ENABLE ( 1UL << 16UL ) + +/* Constants used to detect Cortex-M7 r0p0 and r0p1 cores, and ensure + * that a work around is active for errata 837070. */ +#define portCPUID ( *( ( volatile uint32_t * ) 0xE000ed00 ) ) +#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL ) +#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL ) + +/* Constants required to access and manipulate the MPU. */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_REGION_BASE_ADDRESS_REG ( *( ( volatile uint32_t * ) 0xe000ed9C ) ) +#define portMPU_REGION_ATTRIBUTE_REG ( *( ( volatile uint32_t * ) 0xe000edA0 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) +#define portMPU_ENABLE ( 0x01UL ) +#define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL ) +#define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL ) +#define portMPU_REGION_VALID ( 0x10UL ) +#define portMPU_REGION_ENABLE ( 0x01UL ) +#define portPERIPHERALS_START_ADDRESS 0x40000000UL +#define portPERIPHERALS_END_ADDRESS 0x5FFFFFFFUL + +/* Constants required to access and manipulate the SysTick. */ +#define portNVIC_SYSTICK_INT ( 0x00000002UL ) +#define portNVIC_SYSTICK_ENABLE ( 0x00000001UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL ) +#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL ) + +/* Constants required to manipulate the VFP. */ +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34UL ) /* Floating point context control register. */ +#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000UL ) +#define portINITIAL_EXC_RETURN ( 0xfffffffdUL ) +#define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 ) +#define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 ) + +/* Constants used to check the installation of the FreeRTOS interrupt handlers. */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xE000ED08 ) ) +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) + +/* Constants required to check the validity of an interrupt priority. */ +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) + +/* Constants used during system call enter and exit. */ +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) + +/* Offsets in the stack to the parameters when inside the SVC handler. */ +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) + + +/* For strict compliance with the Cortex-M spec the task start address should + * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */ +#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL ) + +/* Does addr lie within [start, end] address range? */ +#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \ + ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) ) + +/* Is the access request satisfied by the available permissions? */ +#define portIS_AUTHORIZED( accessRequest, permissions ) \ + ( ( ( permissions ) & ( accessRequest ) ) == accessRequest ) + +/* Max value that fits in a uint32_t type. */ +#define portUINT32_MAX ( ~( ( uint32_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) ) +/*-----------------------------------------------------------*/ + +/* + * Configure a number of standard MPU regions that are used by all tasks. + */ +static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; + +/* + * Return the smallest MPU region size that a given number of bytes will fit + * into. The region size is returned as the value that should be programmed + * into the region attribute register for that region. + */ +static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION; + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ); + +/* + * Standard FreeRTOS exception handlers. + */ +void xPortPendSVHandler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; +void xPortSysTickHandler( void ) PRIVILEGED_FUNCTION; +void vPortSVCHandler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/* + * Starts the scheduler by restoring the context of the first task to run. + */ +static void prvRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/* + * C portion of the SVC handler. The SVC handler is split between an asm entry + * and a C wrapper for simplicity of coding and maintenance. + */ +void vSVCHandler_C( uint32_t * pulRegisters ) __attribute__( ( noinline ) ) PRIVILEGED_FUNCTION; + +/* + * Function to enable the VFP. + */ +static void vPortEnableVFP( void ) __attribute__( ( naked ) ); + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Make a task unprivileged. + */ +void vPortSwitchToUserMode( void ); + +/** + * @brief Enter critical section. + */ +#if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) + void vPortEnterCritical( void ) FREERTOS_SYSTEM_CALL; +#else + void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; +#endif + +/** + * @brief Exit from critical section. + */ +#if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) + void vPortExitCritical( void ) FREERTOS_SYSTEM_CALL; +#else + void vPortExitCritical( void ) PRIVILEGED_FUNCTION; +#endif + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + +/** + * @brief Sets up the system call stack so that upon returning from + * SVC, the system call stack is used. + * + * @param pulTaskStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + * @param ucSystemCallNumber The system call number of the system call. + */ + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION; + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + +/** + * @brief Raise SVC for exiting from a system call. + */ + void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + +/** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) PRIVILEGED_FUNCTION; + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ +BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; +/*-----------------------------------------------------------*/ + +/* Each task maintains its own interrupt status in the critical nesting + * variable. Note this is not saved as part of the task context as context + * switches can only occur when uxCriticalNesting is zero. */ +static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + +/* + * This variable is set to pdTRUE when the scheduler is started. + */ + PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE; + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/* + * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( configASSERT_DEFINED == 1 ) + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16; +#endif /* configASSERT_DEFINED */ + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged, + xMPU_SETTINGS * xMPUSettings ) +{ + if( xRunPrivileged == pdTRUE ) + { + xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; + xMPUSettings->ulContext[ 0 ] = portINITIAL_CONTROL_IF_PRIVILEGED; + } + else + { + xMPUSettings->ulTaskFlags &= ( ~( portTASK_IS_PRIVILEGED_FLAG ) ); + xMPUSettings->ulContext[ 0 ] = portINITIAL_CONTROL_IF_UNPRIVILEGED; + } + + xMPUSettings->ulContext[ 1 ] = 0x04040404; /* r4. */ + xMPUSettings->ulContext[ 2 ] = 0x05050505; /* r5. */ + xMPUSettings->ulContext[ 3 ] = 0x06060606; /* r6. */ + xMPUSettings->ulContext[ 4 ] = 0x07070707; /* r7. */ + xMPUSettings->ulContext[ 5 ] = 0x08080808; /* r8. */ + xMPUSettings->ulContext[ 6 ] = 0x09090909; /* r9. */ + xMPUSettings->ulContext[ 7 ] = 0x10101010; /* r10. */ + xMPUSettings->ulContext[ 8 ] = 0x11111111; /* r11. */ + xMPUSettings->ulContext[ 9 ] = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ + + xMPUSettings->ulContext[ 10 ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ + xMPUSettings->ulContext[ 11 ] = ( uint32_t ) pvParameters; /* r0. */ + xMPUSettings->ulContext[ 12 ] = 0x01010101; /* r1. */ + xMPUSettings->ulContext[ 13 ] = 0x02020202; /* r2. */ + xMPUSettings->ulContext[ 14 ] = 0x03030303; /* r3. */ + xMPUSettings->ulContext[ 15 ] = 0x12121212; /* r12. */ + xMPUSettings->ulContext[ 16 ] = 0; /* LR. */ + xMPUSettings->ulContext[ 17 ] = ( ( uint32_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC. */ + xMPUSettings->ulContext[ 18 ] = portINITIAL_XPSR; /* xPSR. */ + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + { + /* Ensure that the system call stack is double word aligned. */ + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + /* This is not NULL only for the duration of a system call. */ + xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL; + } + #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + return &( xMPUSettings->ulContext[ 19 ] ); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + void vPortSVCHandler( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + ".syntax unified \n" + ".extern vSVCHandler_C \n" + ".extern vSystemCallEnter \n" + ".extern vSystemCallExit \n" + " \n" + "tst lr, #4 \n" + "ite eq \n" + "mrseq r0, msp \n" + "mrsne r0, psp \n" + " \n" + "ldr r1, [r0, #24] \n" + "ldrb r2, [r1, #-2] \n" + "cmp r2, %0 \n" + "blt syscall_enter \n" + "cmp r2, %1 \n" + "beq syscall_exit \n" + "b vSVCHandler_C \n" + " \n" + "syscall_enter: \n" + " mov r1, lr \n" + " b vSystemCallEnter \n" + " \n" + "syscall_exit: \n" + " mov r1, lr \n" + " b vSystemCallExit \n" + " \n" + : /* No outputs. */ + : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT ) + : "r0", "r1", "r2", "memory" + ); + } + +#else /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + void vPortSVCHandler( void ) + { + /* Assumes psp was in use. */ + __asm volatile + ( + #ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */ + " tst lr, #4 \n" + " ite eq \n" + " mrseq r0, msp \n" + " mrsne r0, psp \n" + #else + " mrs r0, psp \n" + #endif + " b %0 \n" + ::"i" ( vSVCHandler_C ) : "r0", "memory" + ); + } + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +void vSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */ +{ + uint8_t ucSVCNumber; + uint32_t ulPC; + + #if ( ( configUSE_MPU_WRAPPERS_V1 == 1 ) && ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + #endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 1 ) && ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) ) */ + + /* The stack contains: r0, r1, r2, r3, r12, LR, PC and xPSR. The first + * argument (r0) is pulParam[ 0 ]. */ + ulPC = pulParam[ portOFFSET_TO_PC ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + case portSVC_START_SCHEDULER: + prvRestoreContextOfFirstTask(); + break; + + case portSVC_YIELD: + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required + * but do ensure the code is completely + * within the specified behaviour for the + * architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); + + break; + + #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) + #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) + case portSVC_RAISE_PRIVILEGE: /* Only raise the privilege, if the + * svc was raised from any of the + * system calls. */ + + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + __asm volatile + ( + " mrs r1, control \n" /* Obtain current control value. */ + " bic r1, #1 \n" /* Set privilege bit. */ + " msr control, r1 \n" /* Write back new control value. */ + ::: "r1", "memory" + ); + } + + break; + #else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */ + case portSVC_RAISE_PRIVILEGE: + __asm volatile + ( + " mrs r1, control \n" /* Obtain current control value. */ + " bic r1, #1 \n" /* Set privilege bit. */ + " msr control, r1 \n" /* Write back new control value. */ + ::: "r1", "memory" + ); + break; + #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */ + #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + default: /* Unknown SVC call. */ + break; + } +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ]; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulSystemCallStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the system call section (i.e. application is + * not raising SVC directly). + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as + * it is non-NULL only during the execution of a system call (i.e. + * between system call enter and exit). + * 3. System call is not for a kernel API disabled by the configuration + * in FreeRTOSConfig.h. + * 4. We do not need to check that ucSystemCallNumber is within range + * because the assembly SVC handler checks that before calling + * this function. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) && + ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) ) + { + pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + + /* Make space on the system call stack for the stack frame. */ + pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulSystemCallStack[ i ] = pulTaskStack[ i ]; + } + + /* Use the pulSystemCallStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); + + /* Raise the privilege for the duration of the system call. */ + __asm volatile ( + " mrs r1, control \n" /* Obtain current control value. */ + " bic r1, #1 \n" /* Clear nPRIV bit. */ + " msr control, r1 \n" /* Write back new control value. */ + ::: "r1", "memory" + ); + + /* Remember the location where we should copy the stack frame when we exit from + * the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize; + + /* Store the value of the Link Register before the SVC was raised. + * It contains the address of the caller of the System Call entry + * point (i.e. the caller of the MPU_). We need to restore it + * when we exit from the system call. */ + pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; + + /* Start executing the system call upon returning from this handler. */ + pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; + /* Raise a request to exit from the system call upon finishing the + * system call. */ + pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; + + /* Record if the hardware used padding to force the stack pointer + * to be double word aligned. */ + if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK ) + { + pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG; + } + else + { + pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG ); + } + + /* We ensure in pxPortInitialiseStack that the system call stack is + * double word aligned and therefore, there is no need of padding. + * Clear the bit[9] of stacked xPSR. */ + pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + } + } + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */ + { + __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" ); + } + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulTaskStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the privileged code (i.e. application is not + * raising SVC directly). This SVC is only raised from + * vRequestSystemCallExit which is in the privileged code section. + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL - + * this means that we previously entered a system call and the + * application is not attempting to exit without entering a system + * call. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) ) + { + pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + + /* Make space on the task stack for the stack frame. */ + pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulTaskStack[ i ] = pulSystemCallStack[ i ]; + } + + /* Use the pulTaskStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) ); + + /* Drop the privilege before returning to the thread mode. */ + __asm volatile ( + " mrs r1, control \n" /* Obtain current control value. */ + " orr r1, #1 \n" /* Set nPRIV bit. */ + " msr control, r1 \n" /* Write back new control value. */ + ::: "r1", "memory" + ); + + /* Return to the caller of the System Call entry point (i.e. the + * caller of the MPU_). */ + pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + /* Ensure that LR has a valid value.*/ + pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + + /* If the hardware used padding to force the stack pointer + * to be double word aligned, set the stacked xPSR bit[9], + * otherwise clear it. */ + if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG ) + { + pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK; + } + else + { + pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + } + + /* This is not NULL only for the duration of the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; + } + } + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */ +{ + BaseType_t xTaskIsPrivileged = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xTaskIsPrivileged = pdTRUE; + } + + return xTaskIsPrivileged; +} +/*-----------------------------------------------------------*/ + +static void prvRestoreContextOfFirstTask( void ) +{ + __asm volatile + ( + " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n" + " ldr r0, [r0] \n" + " msr msp, r0 \n" /* Set the msp back to the start of the stack. */ + " \n" + /*------------ Program MPU. ------------ */ + " ldr r3, =pxCurrentTCB \n" /* r3 = =pxCurrentTCB. */ + " ldr r2, [r3] \n" /* r2 = pxCurrentTCB. */ + " add r2, r2, #4 \n" /* r2 = Second item in the TCB which is xMPUSettings. */ + " \n" + " dmb \n" /* Complete outstanding transfers before disabling MPU. */ + " ldr r0, =0xe000ed94 \n" /* MPU_CTRL register. */ + " ldr r3, [r0] \n" /* Read the value of MPU_CTRL. */ + " bic r3, #1 \n" /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */ + " str r3, [r0] \n" /* Disable MPU. */ + " \n" + " ldr r0, =0xe000ed9c \n" /* Region Base Address register. */ + " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */ + " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 4 - 8]. */ + " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 4 - 8]. */ + " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 9 - 12]. */ + " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 9 - 12]. */ + #endif /* configTOTAL_MPU_REGIONS == 16. */ + " \n" + " ldr r0, =0xe000ed94 \n" /* MPU_CTRL register. */ + " ldr r3, [r0] \n" /* Read the value of MPU_CTRL. */ + " orr r3, #1 \n" /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */ + " str r3, [r0] \n" /* Enable MPU. */ + " dsb \n" /* Force memory writes before continuing. */ + " \n" + /*---------- Restore Context. ---------- */ + " ldr r3, =pxCurrentTCB \n" /* r3 = =pxCurrentTCB. */ + " ldr r2, [r3] \n" /* r2 = pxCurrentTCB. */ + " ldr r1, [r2] \n" /* r1 = Location of saved context in TCB. */ + " \n" + " ldmdb r1!, {r0, r4-r11} \n" /* r0 contains PSP after the hardware had saved context. r4-r11 contain hardware saved context. */ + " msr psp, r0 \n" + " stmia r0, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */ + " ldmdb r1!, {r3-r11, lr} \n" /* r3 contains CONTROL register. r4-r11 and LR restored. */ + " msr control, r3 \n" + " str r1, [r2] \n" /* Save the location where the context should be saved next as the first member of TCB. */ + " \n" + " mov r0, #0 \n" + " msr basepri, r0 \n" + " bx lr \n" + " \n" + " .ltorg \n" /* Assemble current literal pool to avoid offset-out-of-bound errors with lto. */ + ); +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + /* Errata 837070 workaround must only be enabled on Cortex-M7 r0p0 + * and r0p1 cores. */ + #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) + configASSERT( ( portCPUID == portCORTEX_M7_r0p1_ID ) || ( portCPUID == portCORTEX_M7_r0p0_ID ) ); + #else + + /* When using this port on a Cortex-M7 r0p0 or r0p1 core, define + * configENABLE_ERRATA_837070_WORKAROUND to 1 in your + * FreeRTOSConfig.h. */ + configASSERT( portCPUID != portCORTEX_M7_r0p1_ID ); + configASSERT( portCPUID != portCORTEX_M7_r0p0_ID ); + #endif + + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions vPortSVCHandler and + * xPortPendSVHandler for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * vPortSVCHandler and xPortPendSVHandler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( configASSERT_DEFINED == 1 ) + { + volatile uint8_t ucOriginalPriority; + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * Save the interrupt priority value that is about to be clobbered. */ + ucOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to all + * possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + + /* Restore the clobbered interrupt priority register to its original + * value. */ + *pucFirstUserPriorityRegister = ucOriginalPriority; + } + #endif /* configASSERT_DEFINED */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + /* Configure the regions in the MPU that are common to all tasks. */ + prvSetupMPU(); + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + { + xSchedulerRunning = pdTRUE; + } + #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + /* Ensure the VFP is enabled - it should be anyway. */ + vPortEnableVFP(); + + /* Lazy save always. */ + *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; + + /* Start the first task. This also clears the bit that indicates the FPU is + * in use in case the FPU was used before the scheduler was started - which + * would otherwise result in the unnecessary leaving of space in the SVC stack + * for lazy saving of FPU registers. */ + __asm volatile ( + " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n" + " ldr r0, [r0] \n" + " msr msp, r0 \n" /* Set the msp back to the start of the stack. */ + " mov r0, #0 \n" /* Clear the bit that indicates the FPU is in use, see comment above. */ + " msr control, r0 \n" + " cpsie i \n" /* Globally enable interrupts. */ + " cpsie f \n" + " dsb \n" + " isb \n" + " svc %0 \n" /* System call to start first task. */ + " nop \n" + " .ltorg \n" + ::"i" ( portSVC_START_SCHEDULER ) : "memory" ); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + #if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + } + #else /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + #endif /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */ +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + #if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + } + #else /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */ + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + #endif /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */ +} +/*-----------------------------------------------------------*/ + +void xPortPendSVHandler( void ) +{ + /* This is a naked function. */ + + __asm volatile + ( + " ldr r3, =pxCurrentTCB \n" /* r3 = =pxCurrentTCB. */ + " ldr r2, [r3] \n" /* r2 = pxCurrentTCB. */ + " ldr r1, [r2] \n" /* r1 = Location where the context should be saved. */ + " \n" + /*------------ Save Context. ----------- */ + " mrs r3, control \n" + " mrs r0, psp \n" + " isb \n" + " \n" + " add r0, r0, #0x20 \n" /* Move r0 to location where s0 is saved. */ + " tst lr, #0x10 \n" + " ittt eq \n" + " vstmiaeq r1!, {s16-s31} \n" /* Store s16-s31. */ + " vldmiaeq r0, {s0-s16} \n" /* Copy hardware saved FP context into s0-s16. */ + " vstmiaeq r1!, {s0-s16} \n" /* Store hardware saved FP context. */ + " sub r0, r0, #0x20 \n" /* Set r0 back to the location of hardware saved context. */ + " \n" + " stmia r1!, {r3-r11, lr} \n" /* Store CONTROL register, r4-r11 and LR. */ + " ldmia r0, {r4-r11} \n" /* Copy hardware saved context into r4-r11. */ + " stmia r1!, {r0, r4-r11} \n" /* Store original PSP (after hardware has saved context) and the hardware saved context. */ + " str r1, [r2] \n" /* Save the location from where the context should be restored as the first member of TCB. */ + " \n" + /*---------- Select next task. --------- */ + " mov r0, %0 \n" + #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) + " cpsid i \n" /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */ + #endif + " msr basepri, r0 \n" + " dsb \n" + " isb \n" + #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) + " cpsie i \n" /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */ + #endif + " bl vTaskSwitchContext \n" + " mov r0, #0 \n" + " msr basepri, r0 \n" + " \n" + /*------------ Program MPU. ------------ */ + " ldr r3, =pxCurrentTCB \n" /* r3 = =pxCurrentTCB. */ + " ldr r2, [r3] \n" /* r2 = pxCurrentTCB. */ + " add r2, r2, #4 \n" /* r2 = Second item in the TCB which is xMPUSettings. */ + " \n" + " dmb \n" /* Complete outstanding transfers before disabling MPU. */ + " ldr r0, =0xe000ed94 \n" /* MPU_CTRL register. */ + " ldr r3, [r0] \n" /* Read the value of MPU_CTRL. */ + " bic r3, #1 \n" /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */ + " str r3, [r0] \n" /* Disable MPU. */ + " \n" + " ldr r0, =0xe000ed9c \n" /* Region Base Address register. */ + " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */ + " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */ + " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 4 - 7]. */ + " ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */ + " stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */ + #endif /* configTOTAL_MPU_REGIONS == 16. */ + " \n" + " ldr r0, =0xe000ed94 \n" /* MPU_CTRL register. */ + " ldr r3, [r0] \n" /* Read the value of MPU_CTRL. */ + " orr r3, #1 \n" /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */ + " str r3, [r0] \n" /* Enable MPU. */ + " dsb \n" /* Force memory writes before continuing. */ + " \n" + /*---------- Restore Context. ---------- */ + " ldr r3, =pxCurrentTCB \n" /* r3 = =pxCurrentTCB. */ + " ldr r2, [r3] \n" /* r2 = pxCurrentTCB. */ + " ldr r1, [r2] \n" /* r1 = Location of saved context in TCB. */ + " \n" + " ldmdb r1!, {r0, r4-r11} \n" /* r0 contains PSP after the hardware had saved context. r4-r11 contain hardware saved context. */ + " msr psp, r0 \n" + " stmia r0!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */ + " ldmdb r1!, {r3-r11, lr} \n" /* r3 contains CONTROL register. r4-r11 and LR restored. */ + " msr control, r3 \n" + + " tst lr, #0x10 \n" + " ittt eq \n" + " vldmdbeq r1!, {s0-s16} \n" /* s0-s16 contain hardware saved FP context. */ + " vstmiaeq r0!, {s0-s16} \n" /* Copy hardware saved FP context on the task stack. */ + " vldmdbeq r1!, {s16-s31} \n" /* Restore s16-s31. */ + + " str r1, [r2] \n" /* Save the location where the context should be saved next as the first member of TCB. */ + " bx lr \n" + " \n" + " .ltorg \n" /* Assemble the current literal pool to avoid offset-out-of-bound errors with lto. */ + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + uint32_t ulDummy; + + ulDummy = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy ); +} +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) +{ + /* Stop and clear the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE ); +} +/*-----------------------------------------------------------*/ + +/* This is a naked function. */ +static void vPortEnableVFP( void ) +{ + __asm volatile + ( + " ldr.w r0, =0xE000ED88 \n" /* The FPU enable bits are in the CPACR. */ + " ldr r1, [r0] \n" + " \n" + " orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */ + " str r1, [r0] \n" + " bx r14 \n" + " .ltorg \n" + ); +} +/*-----------------------------------------------------------*/ + +static void prvSetupMPU( void ) +{ + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __FLASH_segment_start__; + extern uint32_t * __FLASH_segment_end__; + extern uint32_t * __privileged_data_start__; + extern uint32_t * __privileged_data_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __FLASH_segment_start__[]; + extern uint32_t __FLASH_segment_end__[]; + extern uint32_t __privileged_data_start__[]; + extern uint32_t __privileged_data_end__[]; + #endif /* if defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */ + configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ); + + /* Check the expected MPU is present. */ + if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ) + { + /* First setup the unprivileged flash for unprivileged read only access. */ + portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */ + ( portMPU_REGION_VALID ) | + ( portUNPRIVILEGED_FLASH_REGION ); + + portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) | + ( ( configTEX_S_C_B_FLASH & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) | + ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) | + ( portMPU_REGION_ENABLE ); + + /* Setup the privileged flash for privileged only access. This is where + * the kernel code is placed. */ + portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_functions_start__ ) | /* Base address. */ + ( portMPU_REGION_VALID ) | + ( portPRIVILEGED_FLASH_REGION ); + + portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) | + ( ( configTEX_S_C_B_FLASH & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) | + ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __privileged_functions_start__ ) ) | + ( portMPU_REGION_ENABLE ); + + /* Setup the privileged data RAM region. This is where the kernel data + * is placed. */ + portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */ + ( portMPU_REGION_VALID ) | + ( portPRIVILEGED_RAM_REGION ); + + portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ) | + ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) | + prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) | + ( portMPU_REGION_ENABLE ); + + /* By default allow everything to access the general peripherals. The + * system peripherals and registers are protected. */ + portMPU_REGION_BASE_ADDRESS_REG = ( portPERIPHERALS_START_ADDRESS ) | + ( portMPU_REGION_VALID ) | + ( portGENERAL_PERIPHERALS_REGION ); + + portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) | + ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) | + ( portMPU_REGION_ENABLE ); + + /* Enable the memory fault exception. */ + portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE; + + /* Enable the MPU with the background region configured. */ + portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE ); + } +} +/*-----------------------------------------------------------*/ + +static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) +{ + uint32_t ulRegionSize, ulReturnValue = 4; + + /* 32 is the smallest region size, 31 is the largest valid value for + * ulReturnValue. */ + for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) ) + { + if( ulActualSizeInBytes <= ulRegionSize ) + { + break; + } + else + { + ulReturnValue++; + } + } + + /* Shift the code by one before returning so it can be written directly + * into the the correct bit position of the attribute register. */ + return( ulReturnValue << 1UL ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " mrs r0, control \n" /* r0 = CONTROL. */ + " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + " ite ne \n" + " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + " bx lr \n" /* Return. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vResetPrivilege( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " mrs r0, control \n" /* r0 = CONTROL. */ + " orr r0, #1 \n" /* r0 = r0 | 1. */ + " msr control, r0 \n" /* CONTROL = r0. */ + " bx lr \n" /* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vPortSwitchToUserMode( void ) +{ + /* Load the current task's MPU settings from its TCB. */ + xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); + + /* Mark the task as unprivileged. */ + xTaskMpuSettings->ulTaskFlags &= ( ~( portTASK_IS_PRIVILEGED_FLAG ) ); + + /* Lower the processor's privilege level. */ + vResetPrivilege(); +} +/*-----------------------------------------------------------*/ + +void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + configSTACK_DEPTH_TYPE uxStackDepth ) +{ + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __SRAM_segment_start__; + extern uint32_t * __SRAM_segment_end__; + extern uint32_t * __privileged_data_start__; + extern uint32_t * __privileged_data_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __SRAM_segment_start__[]; + extern uint32_t __SRAM_segment_end__[]; + extern uint32_t __privileged_data_start__[]; + extern uint32_t __privileged_data_end__[]; + #endif /* if defined( __ARMCC_VERSION ) */ + + int32_t lIndex; + uint32_t ul; + + if( xRegions == NULL ) + { + /* No MPU regions are specified so allow access to all RAM. */ + xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress = + ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */ + ( portMPU_REGION_VALID ) | + ( portSTACK_REGION ); /* Region number. */ + + xMPUSettings->xRegion[ 0 ].ulRegionAttribute = + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ) | + ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) | + ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) | + ( portMPU_REGION_ENABLE ); + + xMPUSettings->xRegionSettings[ 0 ].ulRegionStartAddress = ( uint32_t ) __SRAM_segment_start__; + xMPUSettings->xRegionSettings[ 0 ].ulRegionEndAddress = ( uint32_t ) __SRAM_segment_end__; + xMPUSettings->xRegionSettings[ 0 ].ulRegionPermissions = ( tskMPU_READ_PERMISSION | + tskMPU_WRITE_PERMISSION ); + + /* Invalidate user configurable regions. */ + for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ ) + { + xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID ); + xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL; + xMPUSettings->xRegionSettings[ ul ].ulRegionStartAddress = 0UL; + xMPUSettings->xRegionSettings[ ul ].ulRegionEndAddress = 0UL; + xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = 0UL; + } + } + else + { + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that the + * stack region has already been configured. */ + if( uxStackDepth > 0 ) + { + /* Define the region that allows access to the stack. */ + xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress = + ( ( uint32_t ) pxBottomOfStack ) | + ( portMPU_REGION_VALID ) | + ( portSTACK_REGION ); /* Region number. */ + + xMPUSettings->xRegion[ 0 ].ulRegionAttribute = + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ) | + ( prvGetMPURegionSizeSetting( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) ) | + ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) | + ( portMPU_REGION_ENABLE ); + + xMPUSettings->xRegionSettings[ 0 ].ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + xMPUSettings->xRegionSettings[ 0 ].ulRegionEndAddress = ( uint32_t ) ( ( uint32_t ) ( pxBottomOfStack ) + + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1UL ); + xMPUSettings->xRegionSettings[ 0 ].ulRegionPermissions = ( tskMPU_READ_PERMISSION | + tskMPU_WRITE_PERMISSION ); + } + + lIndex = 0; + + for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ ) + { + if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL ) + { + /* Translate the generic region definition contained in + * xRegions into the CM4 specific MPU settings that are then + * stored in xMPUSettings. */ + xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = + ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) | + ( portMPU_REGION_VALID ) | + ( ul - 1UL ); /* Region number. */ + + xMPUSettings->xRegion[ ul ].ulRegionAttribute = + ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) | + ( xRegions[ lIndex ].ulParameters ) | + ( portMPU_REGION_ENABLE ); + + xMPUSettings->xRegionSettings[ ul ].ulRegionStartAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress; + xMPUSettings->xRegionSettings[ ul ].ulRegionEndAddress = ( uint32_t ) ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1UL ); + xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = 0UL; + + if( ( ( xRegions[ lIndex ].ulParameters & portMPU_REGION_READ_ONLY ) == portMPU_REGION_READ_ONLY ) || + ( ( xRegions[ lIndex ].ulParameters & portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ) == portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ) ) + { + xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = tskMPU_READ_PERMISSION; + } + + if( ( xRegions[ lIndex ].ulParameters & portMPU_REGION_READ_WRITE ) == portMPU_REGION_READ_WRITE ) + { + xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION ); + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID ); + xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL; + xMPUSettings->xRegionSettings[ ul ].ulRegionStartAddress = 0UL; + xMPUSettings->xRegionSettings[ ul ].ulRegionEndAddress = 0UL; + xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = 0UL; + } + + lIndex++; + } + } +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, + uint32_t ulBufferLength, + uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */ + + { + uint32_t i, ulBufferStartAddress, ulBufferEndAddress; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE ) + { + ulBufferStartAddress = ( uint32_t ) pvBuffer; + ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL ); + + for( i = 0; i < portTOTAL_NUM_REGIONS_IN_TCB; i++ ) + { + if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress, + xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress, + xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) && + portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress, + xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress, + xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) && + portIS_AUTHORIZED( ulAccessRequested, xTaskMpuSettings->xRegionSettings[ i ].ulRegionPermissions ) ) + { + xAccessGranted = pdTRUE; + break; + } + } + } + } + + return xAccessGranted; + } + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* configASSERT_DEFINED */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings; + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else + { + xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 ) + { + xAccessGranted = pdTRUE; + } + } + } + + return xAccessGranted; + } + + #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + ( void ) lInternalIndexOfKernelObject; + + /* If Access Control List feature is not used, all the tasks have + * access to all the kernel objects. */ + return pdTRUE; + } + + #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM4_MPU/portmacro.h b/portable/GCC/ARM_CM4_MPU/portmacro.h new file mode 100644 index 000000000..581b09d5c --- /dev/null +++ b/portable/GCC/ARM_CM4_MPU/portmacro.h @@ -0,0 +1,502 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error "configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width." +#endif + +/* Errata 837070 workaround must be enabled on Cortex-M7 r0p0 + * and r0p1 cores. */ +#ifndef configENABLE_ERRATA_837070_WORKAROUND + #define configENABLE_ERRATA_837070_WORKAROUND 0 +#endif +/*-----------------------------------------------------------*/ + +/* MPU specific constants. */ +#define portUSING_MPU_WRAPPERS 1 +#define portPRIVILEGE_BIT ( 0x80000000UL ) + +#define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL ) +#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL ) +#define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL ) +#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL ) +#define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ( 0x02UL << 24UL ) +#define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL ) +#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL ) + +/* Location of the TEX,S,C,B bits in the MPU Region Attribute and Size + * Register (RASR). */ +#define portMPU_RASR_TEX_S_C_B_LOCATION ( 16UL ) +#define portMPU_RASR_TEX_S_C_B_MASK ( 0x3FUL ) + +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* + * The TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits define the + * memory type, and where necessary the cacheable and shareable properties + * of the memory region. + * + * The TEX, C, and B bits together indicate the memory type of the region, + * and: + * - For Normal memory, the cacheable properties of the region. + * - For Device memory, whether the region is shareable. + * + * For Normal memory regions, the S bit indicates whether the region is + * shareable. For Strongly-ordered and Device memory, the S bit is ignored. + * + * See the following two tables for setting TEX, S, C and B bits for + * unprivileged flash, privileged flash and privileged RAM regions. + * + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | TEX | C | B | Memory type | Description or Normal region cacheability | Shareable? | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 000 | 0 | 0 | Strongly-ordered | Strongly ordered | Shareable | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 000 | 0 | 1 | Device | Shared device | Shareable | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 000 | 1 | 0 | Normal | Outer and inner write-through; no write allocate | S bit | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 000 | 1 | 1 | Normal | Outer and inner write-back; no write allocate | S bit | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 001 | 0 | 0 | Normal | Outer and inner Non-cacheable | S bit | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 001 | 0 | 1 | Reserved | Reserved | Reserved | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 001 | 1 | 0 | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 001 | 1 | 1 | Normal | Outer and inner write-back; write and read allocate | S bit | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 010 | 0 | 0 | Device | Non-shared device | Not shareable | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 010 | 0 | 1 | Reserved | Reserved | Reserved | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 010 | 1 | X | Reserved | Reserved | Reserved | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 011 | X | X | Reserved | Reserved | Reserved | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 1BB | A | A | Normal | Cached memory, with AA and BB indicating the inner and | Reserved | + | | | | | outer cacheability rules that must be exported on the | | + | | | | | bus. See the table below for the cacheability policy | | + | | | | | encoding. memory, BB=Outer policy, AA=Inner policy. | | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | + +-----------------------------------------+----------------------------------------+ + | AA or BB subfield of {TEX,C,B} encoding | Cacheability policy | + +-----------------------------------------+----------------------------------------+ + | 00 | Non-cacheable | + +-----------------------------------------+----------------------------------------+ + | 01 | Write-back, write and read allocate | + +-----------------------------------------+----------------------------------------+ + | 10 | Write-through, no write allocate | + +-----------------------------------------+----------------------------------------+ + | 11 | Write-back, no write allocate | + +-----------------------------------------+----------------------------------------+ + */ + +/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for flash + * region. */ +#ifndef configTEX_S_C_B_FLASH + /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */ + #define configTEX_S_C_B_FLASH ( 0x07UL ) +#endif + +/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for RAM + * region. */ +#ifndef configTEX_S_C_B_SRAM + /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */ + #define configTEX_S_C_B_SRAM ( 0x07UL ) +#endif + +#define portSTACK_REGION ( configTOTAL_MPU_REGIONS - 5UL ) +#define portGENERAL_PERIPHERALS_REGION ( configTOTAL_MPU_REGIONS - 4UL ) +#define portUNPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 3UL ) +#define portPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 2UL ) +#define portPRIVILEGED_RAM_REGION ( configTOTAL_MPU_REGIONS - 1UL ) +#define portFIRST_CONFIGURABLE_REGION ( 0UL ) +#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 6UL ) +#define portNUM_CONFIGURABLE_REGIONS ( configTOTAL_MPU_REGIONS - 5UL ) +#define portTOTAL_NUM_REGIONS_IN_TCB ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus 1 to create space for the stack region. */ + +typedef struct MPU_REGION_REGISTERS +{ + uint32_t ulRegionBaseAddress; + uint32_t ulRegionAttribute; +} xMPU_REGION_REGISTERS; + +typedef struct MPU_REGION_SETTINGS +{ + uint32_t ulRegionStartAddress; + uint32_t ulRegionEndAddress; + uint32_t ulRegionPermissions; +} xMPU_REGION_SETTINGS; + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + #ifndef configSYSTEM_CALL_STACK_SIZE + #error "configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2." + #endif + + typedef struct SYSTEM_CALL_STACK_INFO + { + uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; + uint32_t * pulSystemCallStack; + uint32_t * pulTaskStack; + uint32_t ulLinkRegisterAtSystemCallEntry; + } xSYSTEM_CALL_STACK_INFO; + +#endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + +/* + * +---------+---------------+-----------------+-----------------+-----+ + * | s16-s31 | s0-s15, FPSCR | CONTROL, r4-r11 | PSP, r0-r3, r12 | | + * | | | EXC_RETURN | LR, PC, xPSR | | + * +---------+---------------+-----------------+-----------------+-----+ + * + * <--------><---------------><----------------><----------------><----> + * 16 17 10 9 1 + */ +#define MAX_CONTEXT_SIZE ( 53 ) + +/* Size of an Access Control List (ACL) entry in bits. */ +#define portACL_ENTRY_SIZE_BITS ( 32U ) + +/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ +#define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) +#define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) + +typedef struct MPU_SETTINGS +{ + xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS_IN_TCB ]; + xMPU_REGION_SETTINGS xRegionSettings[ portTOTAL_NUM_REGIONS_IN_TCB ]; + uint32_t ulContext[ MAX_CONTEXT_SIZE ]; + uint32_t ulTaskFlags; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo; + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ]; + #endif + #endif +} xMPU_SETTINGS; + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/* SVC numbers for various services. */ +#define portSVC_START_SCHEDULER 100 +#define portSVC_YIELD 101 +#define portSVC_RAISE_PRIVILEGE 102 +#define portSVC_SYSTEM_CALL_EXIT 103 + +/* Scheduler utilities. */ + +#define portYIELD() __asm volatile ( " SVC %0 \n" ::"i" ( portSVC_YIELD ) : "memory" ) +#define portYIELD_WITHIN_API() \ + { \ + /* Set a PendSV to request a context switch. */ \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + \ + /* Barriers are normally not required but do ensure the code is completely \ + * within the specified behaviour for the architecture. */ \ + __asm volatile ( "dsb" ::: "memory" ); \ + __asm volatile ( "isb" ); \ + } + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x ) +#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() +#define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not necessary for to use this port. They are defined so the common demo files + * (which build with all the ports) will build. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +/* Architecture specific optimisations. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + +/* Generic helper function. */ + __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint8_t ucReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ucReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice." + #endif + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif + +/* portNOP() is not required by this port. */ +#define portNOP() + +#define portINLINE __inline + +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif +/*-----------------------------------------------------------*/ + +extern BaseType_t xIsPrivileged( void ); +extern void vResetPrivilege( void ); +extern void vPortSwitchToUserMode( void ); + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +#define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + */ +#define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ +#define portRESET_PRIVILEGE() vResetPrivilege() + +/** + * @brief Make a task unprivileged. + * + * It must be called from privileged tasks only. Calling it from unprivileged + * task will result in a memory protection fault. + */ +#define portSWITCH_TO_USER_MODE() vPortSwitchToUserMode() +/*-----------------------------------------------------------*/ + +extern BaseType_t xPortIsTaskPrivileged( void ); + +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ +#define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() +/*-----------------------------------------------------------*/ + +portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} + +/*-----------------------------------------------------------*/ + +portFORCE_INLINE static void vPortRaiseBASEPRI( void ) +{ + uint32_t ulNewBASEPRI; + + __asm volatile + ( + " mov %0, %1 \n" + #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) + " cpsid i \n" /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */ + #endif + " msr basepri, %0 \n" + " isb \n" + " dsb \n" + #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) + " cpsie i \n" /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */ + #endif + : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); +} + +/*-----------------------------------------------------------*/ + +portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void ) +{ + uint32_t ulOriginalBASEPRI, ulNewBASEPRI; + + __asm volatile + ( + " mrs %0, basepri \n" + " mov %1, %2 \n" + #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) + " cpsid i \n" /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */ + #endif + " msr basepri, %1 \n" + " isb \n" + " dsb \n" + #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) + " cpsie i \n" /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */ + #endif + : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); + + /* This return will not be reached but is necessary to prevent compiler + * warnings. */ + return ulOriginalBASEPRI; +} +/*-----------------------------------------------------------*/ + +portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) +{ + __asm volatile + ( + " msr basepri, %0 " ::"r" ( ulNewMaskValue ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) + +#ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY + #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. www.FreeRTOS.org/FreeRTOS-V10.3.x.html" + #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0 +#endif +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ + #ifdef __cplusplus + } + #endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/ARM_CM52/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM52/non_secure/mpu_wrappers_v2_asm.c new file mode 100644 index 000000000..33410a0c3 --- /dev/null +++ b/portable/GCC/ARM_CM52/non_secure/mpu_wrappers_v2_asm.c @@ -0,0 +1,2056 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" +#include "event_groups.h" +#include "stream_buffer.h" +#include "mpu_prototypes.h" +#include "mpu_syscall_numbers.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( INCLUDE_xTaskDelayUntil == 1 ) + + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskDelayUntilImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskDelayUntil_Unpriv \n" + " MPU_xTaskDelayUntil_Priv: \n" + " b MPU_xTaskDelayUntilImpl \n" + " MPU_xTaskDelayUntil_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskAbortDelayImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskAbortDelay_Unpriv \n" + " MPU_xTaskAbortDelay_Priv: \n" + " b MPU_xTaskAbortDelayImpl \n" + " MPU_xTaskAbortDelay_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskDelay == 1 ) + + void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskDelayImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskDelay_Unpriv \n" + " MPU_vTaskDelay_Priv: \n" + " b MPU_vTaskDelayImpl \n" + " MPU_vTaskDelay_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskPriorityGet == 1 ) + + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskPriorityGetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskPriorityGet_Unpriv \n" + " MPU_uxTaskPriorityGet_Priv: \n" + " b MPU_uxTaskPriorityGetImpl \n" + " MPU_uxTaskPriorityGet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_eTaskGetState == 1 ) + + eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_eTaskGetStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_eTaskGetState_Unpriv \n" + " MPU_eTaskGetState_Priv: \n" + " b MPU_eTaskGetStateImpl \n" + " MPU_eTaskGetState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory" + ); + } + + #endif /* if ( INCLUDE_eTaskGetState == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskGetInfoImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskGetInfo_Unpriv \n" + " MPU_vTaskGetInfo_Priv: \n" + " b MPU_vTaskGetInfoImpl \n" + " MPU_vTaskGetInfo_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory" + ); + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) + + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetIdleTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetIdleTaskHandle_Unpriv \n" + " MPU_xTaskGetIdleTaskHandle_Priv: \n" + " b MPU_xTaskGetIdleTaskHandleImpl \n" + " MPU_xTaskGetIdleTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + + void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSuspendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSuspend_Unpriv \n" + " MPU_vTaskSuspend_Priv: \n" + " b MPU_vTaskSuspendImpl \n" + " MPU_vTaskSuspend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + + void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskResumeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskResume_Unpriv \n" + " MPU_vTaskResume_Priv: \n" + " b MPU_vTaskResumeImpl \n" + " MPU_vTaskResume_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + TickType_t MPU_xTaskGetTickCount( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetTickCountImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetTickCount_Unpriv \n" + " MPU_xTaskGetTickCount_Priv: \n" + " b MPU_xTaskGetTickCountImpl \n" + " MPU_xTaskGetTickCount_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetNumberOfTasksImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetNumberOfTasks_Unpriv \n" + " MPU_uxTaskGetNumberOfTasks_Priv: \n" + " b MPU_uxTaskGetNumberOfTasksImpl \n" + " MPU_uxTaskGetNumberOfTasks_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetRunTimeCounterImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetRunTimeCounter_Unpriv \n" + " MPU_ulTaskGetRunTimeCounter_Priv: \n" + " b MPU_ulTaskGetRunTimeCounterImpl \n" + " MPU_ulTaskGetRunTimeCounter_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetRunTimePercentImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetRunTimePercent_Unpriv \n" + " MPU_ulTaskGetRunTimePercent_Priv: \n" + " b MPU_ulTaskGetRunTimePercentImpl \n" + " MPU_ulTaskGetRunTimePercent_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetIdleRunTimePercentImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv \n" + " MPU_ulTaskGetIdleRunTimePercent_Priv: \n" + " b MPU_ulTaskGetIdleRunTimePercentImpl \n" + " MPU_ulTaskGetIdleRunTimePercent_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetIdleRunTimeCounterImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv \n" + " MPU_ulTaskGetIdleRunTimeCounter_Priv: \n" + " b MPU_ulTaskGetIdleRunTimeCounterImpl \n" + " MPU_ulTaskGetIdleRunTimeCounter_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetApplicationTaskTagImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetApplicationTaskTag_Unpriv \n" + " MPU_vTaskSetApplicationTaskTag_Priv: \n" + " b MPU_vTaskSetApplicationTaskTagImpl \n" + " MPU_vTaskSetApplicationTaskTag_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory" + ); + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetApplicationTaskTagImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetApplicationTaskTag_Unpriv \n" + " MPU_xTaskGetApplicationTaskTag_Priv: \n" + " b MPU_xTaskGetApplicationTaskTagImpl \n" + " MPU_xTaskGetApplicationTaskTag_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory" + ); + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetThreadLocalStoragePointerImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv \n" + " MPU_vTaskSetThreadLocalStoragePointer_Priv: \n" + " b MPU_vTaskSetThreadLocalStoragePointerImpl \n" + " MPU_vTaskSetThreadLocalStoragePointer_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory" + ); + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv \n" + " MPU_pvTaskGetThreadLocalStoragePointer_Priv: \n" + " b MPU_pvTaskGetThreadLocalStoragePointerImpl \n" + " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory" + ); + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetSystemStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetSystemState_Unpriv \n" + " MPU_uxTaskGetSystemState_Priv: \n" + " b MPU_uxTaskGetSystemStateImpl \n" + " MPU_uxTaskGetSystemState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory" + ); + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) + + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetStackHighWaterMarkImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetStackHighWaterMark_Unpriv \n" + " MPU_uxTaskGetStackHighWaterMark_Priv: \n" + " b MPU_uxTaskGetStackHighWaterMarkImpl \n" + " MPU_uxTaskGetStackHighWaterMark_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetStackHighWaterMark2Impl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv \n" + " MPU_uxTaskGetStackHighWaterMark2_Priv: \n" + " b MPU_uxTaskGetStackHighWaterMark2Impl \n" + " MPU_uxTaskGetStackHighWaterMark2_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) + + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetCurrentTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetCurrentTaskHandle_Unpriv \n" + " MPU_xTaskGetCurrentTaskHandle_Priv: \n" + " b MPU_xTaskGetCurrentTaskHandleImpl \n" + " MPU_xTaskGetCurrentTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory" + ); + } + + #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetSchedulerState == 1 ) + + BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetSchedulerStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetSchedulerState_Unpriv \n" + " MPU_xTaskGetSchedulerState_Priv: \n" + " b MPU_xTaskGetSchedulerStateImpl \n" + " MPU_xTaskGetSchedulerState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */ +/*-----------------------------------------------------------*/ + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetTimeOutStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetTimeOutState_Unpriv \n" + " MPU_vTaskSetTimeOutState_Priv: \n" + " b MPU_vTaskSetTimeOutStateImpl \n" + " MPU_vTaskSetTimeOutState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskCheckForTimeOutImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskCheckForTimeOut_Unpriv \n" + " MPU_xTaskCheckForTimeOut_Priv: \n" + " b MPU_xTaskCheckForTimeOutImpl \n" + " MPU_xTaskCheckForTimeOut_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotify_Unpriv \n" + " MPU_xTaskGenericNotify_Priv: \n" + " b MPU_xTaskGenericNotifyImpl \n" + " MPU_xTaskGenericNotify_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyWaitImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotifyWait_Unpriv \n" + " MPU_xTaskGenericNotifyWait_Priv: \n" + " b MPU_xTaskGenericNotifyWaitImpl \n" + " MPU_xTaskGenericNotifyWait_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGenericNotifyTakeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGenericNotifyTake_Unpriv \n" + " MPU_ulTaskGenericNotifyTake_Priv: \n" + " b MPU_ulTaskGenericNotifyTakeImpl \n" + " MPU_ulTaskGenericNotifyTake_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyStateClearImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotifyStateClear_Unpriv \n" + " MPU_xTaskGenericNotifyStateClear_Priv: \n" + " b MPU_xTaskGenericNotifyStateClearImpl \n" + " MPU_xTaskGenericNotifyStateClear_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGenericNotifyValueClearImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGenericNotifyValueClear_Unpriv \n" + " MPU_ulTaskGenericNotifyValueClear_Priv: \n" + " b MPU_ulTaskGenericNotifyValueClearImpl \n" + " MPU_ulTaskGenericNotifyValueClear_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGenericSendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGenericSend_Unpriv \n" + " MPU_xQueueGenericSend_Priv: \n" + " b MPU_xQueueGenericSendImpl \n" + " MPU_xQueueGenericSend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxQueueMessagesWaitingImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxQueueMessagesWaiting_Unpriv \n" + " MPU_uxQueueMessagesWaiting_Priv: \n" + " b MPU_uxQueueMessagesWaitingImpl \n" + " MPU_uxQueueMessagesWaiting_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxQueueSpacesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxQueueSpacesAvailable_Unpriv \n" + " MPU_uxQueueSpacesAvailable_Priv: \n" + " b MPU_uxQueueSpacesAvailableImpl \n" + " MPU_uxQueueSpacesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueReceiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueReceive_Unpriv \n" + " MPU_xQueueReceive_Priv: \n" + " b MPU_xQueueReceiveImpl \n" + " MPU_xQueueReceive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueuePeekImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueuePeek_Unpriv \n" + " MPU_xQueuePeek_Priv: \n" + " b MPU_xQueuePeekImpl \n" + " MPU_xQueuePeek_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueSemaphoreTakeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueSemaphoreTake_Unpriv \n" + " MPU_xQueueSemaphoreTake_Priv: \n" + " b MPU_xQueueSemaphoreTakeImpl \n" + " MPU_xQueueSemaphoreTake_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) + + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGetMutexHolderImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGetMutexHolder_Unpriv \n" + " MPU_xQueueGetMutexHolder_Priv: \n" + " b MPU_xQueueGetMutexHolderImpl \n" + " MPU_xQueueGetMutexHolder_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory" + ); + } + + #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueTakeMutexRecursiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueTakeMutexRecursive_Unpriv \n" + " MPU_xQueueTakeMutexRecursive_Priv: \n" + " b MPU_xQueueTakeMutexRecursiveImpl \n" + " MPU_xQueueTakeMutexRecursive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory" + ); + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGiveMutexRecursiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGiveMutexRecursive_Unpriv \n" + " MPU_xQueueGiveMutexRecursive_Priv: \n" + " b MPU_xQueueGiveMutexRecursiveImpl \n" + " MPU_xQueueGiveMutexRecursive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory" + ); + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueSelectFromSetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueSelectFromSet_Unpriv \n" + " MPU_xQueueSelectFromSet_Priv: \n" + " b MPU_xQueueSelectFromSetImpl \n" + " MPU_xQueueSelectFromSet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory" + ); + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueAddToSetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueAddToSet_Unpriv \n" + " MPU_xQueueAddToSet_Priv: \n" + " b MPU_xQueueAddToSetImpl \n" + " MPU_xQueueAddToSet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory" + ); + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vQueueAddToRegistryImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vQueueAddToRegistry_Unpriv \n" + " MPU_vQueueAddToRegistry_Priv: \n" + " b MPU_vQueueAddToRegistryImpl \n" + " MPU_vQueueAddToRegistry_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vQueueUnregisterQueueImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vQueueUnregisterQueue_Unpriv \n" + " MPU_vQueueUnregisterQueue_Priv: \n" + " b MPU_vQueueUnregisterQueueImpl \n" + " MPU_vQueueUnregisterQueue_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pcQueueGetNameImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pcQueueGetName_Unpriv \n" + " MPU_pcQueueGetName_Priv: \n" + " b MPU_pcQueueGetNameImpl \n" + " MPU_pcQueueGetName_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pvTimerGetTimerIDImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pvTimerGetTimerID_Unpriv \n" + " MPU_pvTimerGetTimerID_Priv: \n" + " b MPU_pvTimerGetTimerIDImpl \n" + " MPU_pvTimerGetTimerID_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTimerSetTimerIDImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTimerSetTimerID_Unpriv \n" + " MPU_vTimerSetTimerID_Priv: \n" + " b MPU_vTimerSetTimerIDImpl \n" + " MPU_vTimerSetTimerID_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerIsTimerActiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerIsTimerActive_Unpriv \n" + " MPU_xTimerIsTimerActive_Priv: \n" + " b MPU_xTimerIsTimerActiveImpl \n" + " MPU_xTimerIsTimerActive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv \n" + " MPU_xTimerGetTimerDaemonTaskHandle_Priv: \n" + " b MPU_xTimerGetTimerDaemonTaskHandleImpl \n" + " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGenericCommandFromTaskImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGenericCommandFromTask_Unpriv \n" + " MPU_xTimerGenericCommandFromTask_Priv: \n" + " b MPU_xTimerGenericCommandFromTaskImpl \n" + " MPU_xTimerGenericCommandFromTask_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pcTimerGetNameImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pcTimerGetName_Unpriv \n" + " MPU_pcTimerGetName_Priv: \n" + " b MPU_pcTimerGetNameImpl \n" + " MPU_pcTimerGetName_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTimerSetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTimerSetReloadMode_Unpriv \n" + " MPU_vTimerSetReloadMode_Priv: \n" + " b MPU_vTimerSetReloadModeImpl \n" + " MPU_vTimerSetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetReloadMode_Unpriv \n" + " MPU_xTimerGetReloadMode_Priv: \n" + " b MPU_xTimerGetReloadModeImpl \n" + " MPU_xTimerGetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTimerGetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTimerGetReloadMode_Unpriv \n" + " MPU_uxTimerGetReloadMode_Priv: \n" + " b MPU_uxTimerGetReloadModeImpl \n" + " MPU_uxTimerGetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetPeriodImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetPeriod_Unpriv \n" + " MPU_xTimerGetPeriod_Priv: \n" + " b MPU_xTimerGetPeriodImpl \n" + " MPU_xTimerGetPeriod_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetExpiryTimeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetExpiryTime_Unpriv \n" + " MPU_xTimerGetExpiryTime_Priv: \n" + " b MPU_xTimerGetExpiryTimeImpl \n" + " MPU_xTimerGetExpiryTime_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupWaitBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupWaitBits_Unpriv \n" + " MPU_xEventGroupWaitBits_Priv: \n" + " b MPU_xEventGroupWaitBitsImpl \n" + " MPU_xEventGroupWaitBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupClearBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupClearBits_Unpriv \n" + " MPU_xEventGroupClearBits_Priv: \n" + " b MPU_xEventGroupClearBitsImpl \n" + " MPU_xEventGroupClearBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupSetBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupSetBits_Unpriv \n" + " MPU_xEventGroupSetBits_Priv: \n" + " b MPU_xEventGroupSetBitsImpl \n" + " MPU_xEventGroupSetBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ + +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupSyncImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupSync_Unpriv \n" + " MPU_xEventGroupSync_Priv: \n" + " b MPU_xEventGroupSyncImpl \n" + " MPU_xEventGroupSync_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxEventGroupGetNumberImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxEventGroupGetNumber_Unpriv \n" + " MPU_uxEventGroupGetNumber_Priv: \n" + " b MPU_uxEventGroupGetNumberImpl \n" + " MPU_uxEventGroupGetNumber_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory" + ); + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vEventGroupSetNumberImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vEventGroupSetNumber_Unpriv \n" + " MPU_vEventGroupSetNumber_Priv: \n" + " b MPU_vEventGroupSetNumberImpl \n" + " MPU_vEventGroupSetNumber_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory" + ); + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferSend_Unpriv \n" + " MPU_xStreamBufferSend_Priv: \n" + " b MPU_xStreamBufferSendImpl \n" + " MPU_xStreamBufferSend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferReceiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferReceive_Unpriv \n" + " MPU_xStreamBufferReceive_Priv: \n" + " b MPU_xStreamBufferReceiveImpl \n" + " MPU_xStreamBufferReceive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferIsFullImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferIsFull_Unpriv \n" + " MPU_xStreamBufferIsFull_Priv: \n" + " b MPU_xStreamBufferIsFullImpl \n" + " MPU_xStreamBufferIsFull_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferIsEmptyImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferIsEmpty_Unpriv \n" + " MPU_xStreamBufferIsEmpty_Priv: \n" + " b MPU_xStreamBufferIsEmptyImpl \n" + " MPU_xStreamBufferIsEmpty_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSpacesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferSpacesAvailable_Unpriv \n" + " MPU_xStreamBufferSpacesAvailable_Priv: \n" + " b MPU_xStreamBufferSpacesAvailableImpl \n" + " MPU_xStreamBufferSpacesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferBytesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferBytesAvailable_Unpriv \n" + " MPU_xStreamBufferBytesAvailable_Priv: \n" + " b MPU_xStreamBufferBytesAvailableImpl \n" + " MPU_xStreamBufferBytesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSetTriggerLevelImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferSetTriggerLevel_Unpriv \n" + " MPU_xStreamBufferSetTriggerLevel_Priv: \n" + " b MPU_xStreamBufferSetTriggerLevelImpl \n" + " MPU_xStreamBufferSetTriggerLevel_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferNextMessageLengthBytesImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv \n" + " MPU_xStreamBufferNextMessageLengthBytes_Priv: \n" + " b MPU_xStreamBufferNextMessageLengthBytesImpl \n" + " MPU_xStreamBufferNextMessageLengthBytes_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ diff --git a/portable/GCC/ARM_CM52/non_secure/port.c b/portable/GCC/ARM_CM52/non_secure/port.c new file mode 100644 index 000000000..76d2b2445 --- /dev/null +++ b/portable/GCC/ARM_CM52/non_secure/port.c @@ -0,0 +1,2280 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024-2025 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU includes. */ +#include "mpu_wrappers.h" +#include "mpu_syscall_numbers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration settings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to check the validity of an interrupt priority. + */ +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) ) +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used during system call enter and exit. + */ +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Offsets in the stack to the parameters when inside the SVC handler. + */ +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +#if ( portARMV8M_MINOR_VERSION >= 1 ) + + /* Enable Privileged eXecute Never MPU attribute for the selected memory + * region. */ + #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL ) +#endif /* portARMV8M_MINOR_VERSION >= 1 */ + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Extract first address of the MPU region as encoded in the + * RBAR (Region Base Address Register) value. */ +#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \ + ( ( rbar ) & portMPU_RBAR_ADDRESS_MASK ) + +/* Extract last address of the MPU region as encoded in the + * RLAR (Region Limit Address Register) value. */ +#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \ + ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK ) + +/* Does addr lies within [start, end] address range? */ +#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \ + ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) ) + +/* Is the access request satisfied by the available permissions? */ +#define portIS_AUTHORIZED( accessRequest, permissions ) \ + ( ( ( permissions ) & ( accessRequest ) ) == accessRequest ) + +/* Max value that fits in a uint32_t type. */ +#define portUINT32_MAX ( ~( ( uint32_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. + */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 + +/** + * @brief Constants required to check and configure PACBTI security feature implementation. + */ +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) ) + + #define portCONTROL_UPAC_EN ( 1UL << 7UL ) + #define portCONTROL_PAC_EN ( 1UL << 6UL ) + #define portCONTROL_UBTI_EN ( 1UL << 5UL ) + #define portCONTROL_BTI_EN ( 1UL << 4UL ) + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Extract MPU region's access permissions from the Region Base Address + * Register (RBAR) value. + * + * @param ulRBARValue RBAR value for the MPU region. + * + * @return uint32_t Access permissions. + */ + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + + /** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + /** + * @brief Configures PACBTI features. + * + * This function configures the Pointer Authentication, and Branch Target + * Identification security features as per the user configuration. It returns + * the value of the special purpose CONTROL register accordingly, and optionally + * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M + * architecture based) target supports PACBTI security feature. + * + * @param xWriteControlRegister Used to control whether the special purpose + * CONTROL register should be updated or not. + * + * @return CONTROL register value according to the configured PACBTI option. + */ + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the system call stack so that upon returning from + * SVC, the system call stack is used. + * + * @param pulTaskStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + * @param ucSystemCallNumber The system call number of the system call. + */ + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Raise SVC for exiting from a system call. + */ + void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief This variable is set to pdTRUE when the scheduler is started. + */ + PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + + /** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +/** + * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + /** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + + /** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + + /** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the cpsid instruction + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessPermissions = 0; + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_ONLY ) + { + ulAccessPermissions = tskMPU_READ_PERMISSION; + } + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_WRITE ) + { + ulAccessPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION ); + } + + return ulAccessPermissions; + } + +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } + +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ portOFFSET_TO_PC ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ]; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulSystemCallStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the system call section (i.e. application is + * not raising SVC directly). + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as + * it is non-NULL only during the execution of a system call (i.e. + * between system call enter and exit). + * 3. System call is not for a kernel API disabled by the configuration + * in FreeRTOSConfig.h. + * 4. We do not need to check that ucSystemCallNumber is within range + * because the assembly SVC handler checks that before calling + * this function. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) && + ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) ) + { + pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the system call stack for the stack frame. */ + pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulSystemCallStack[ i ] = pulTaskStack[ i ]; + } + + /* Store the value of the Link Register before the SVC was raised. + * It contains the address of the caller of the System Call entry + * point (i.e. the caller of the MPU_). We need to restore it + * when we exit from the system call. */ + pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; + + /* Store the value of the PSPLIM register before the SVC was raised. + * We need to restore it when we exit from the system call. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* Use the pulSystemCallStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif + + /* Start executing the system call upon returning from this handler. */ + pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; + + /* Raise a request to exit from the system call upon finishing the + * system call. */ + pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; + + /* Remember the location where we should copy the stack frame when we exit from + * the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize; + + /* Record if the hardware used padding to force the stack pointer + * to be double word aligned. */ + if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK ) + { + pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG; + } + else + { + pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG ); + } + + /* We ensure in pxPortInitialiseStack that the system call stack is + * double word aligned and therefore, there is no need of padding. + * Clear the bit[9] of stacked xPSR. */ + pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + + /* Raise the privilege for the duration of the system call. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " bics r0, r1 \n" /* Clear nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */ + { + __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulTaskStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the privileged code (i.e. application is not + * raising SVC directly). This SVC is only raised from + * vRequestSystemCallExit which is in the privileged code section. + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL - + * this means that we previously entered a system call and the + * application is not attempting to exit without entering a system + * call. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) ) + { + pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the task stack for the stack frame. */ + pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulTaskStack[ i ] = pulSystemCallStack[ i ]; + } + + /* Use the pulTaskStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) ); + + /* Return to the caller of the System Call entry point (i.e. the + * caller of the MPU_). */ + pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + /* Ensure that LR has a valid value.*/ + pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + + /* Restore the PSPLIM register to what it was at the time of + * system call entry. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* If the hardware used padding to force the stack pointer + * to be double word aligned, set the stacked xPSR bit[9], + * otherwise clear it. */ + if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG ) + { + pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK; + } + else + { + pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + } + + /* This is not NULL only for the duration of the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; + + /* Drop the privilege before returning to the thread mode. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " orrs r0, r1 \n" /* Set nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xTaskIsPrivileged = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xTaskIsPrivileged = pdTRUE; + } + + return xTaskIsPrivileged; + } + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged, + xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulIndex = 0; + uint32_t ulControl = 0x0; + + xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ + ulIndex++; + + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + ulIndex++; + + #if ( configENABLE_TRUSTZONE == 1 ) + { + xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */ + ulIndex++; + } + #endif /* configENABLE_TRUSTZONE */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + ulIndex++; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Check PACBTI security feature configuration before pushing the + * CONTROL register's value on task's TCB. */ + ulControl = prvConfigurePACBTI( pdFALSE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + if( xRunPrivileged == pdTRUE ) + { + xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + else + { + xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG ); + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ + ulIndex++; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + { + /* Ensure that the system call stack is double word aligned. */ + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) + + ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + /* This is not NULL only for the duration of a system call. */ + xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL; + } + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ]; + ulIndex++; + } + } + #endif /* configENABLE_PAC */ + + return &( xMPUSettings->ulContext[ ulIndex ] ); + } + +#else /* configENABLE_MPU */ + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ + { + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + pxTopOfStack--; + *pxTopOfStack = ulTaskPacKey[ i ]; + } + } + #endif /* configENABLE_PAC */ + + return pxTopOfStack; + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Set the CONTROL register value based on PACBTI security feature + * configuration before starting the first task. */ + ( void ) prvConfigurePACBTI( pdTRUE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + { + xSchedulerRunning = pdTRUE; + } + #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + configSTACK_DEPTH_TYPE uxStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( uxStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* PXN. */ + #if ( portARMV8M_MINOR_VERSION >= 1 ) + { + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ); + } + } + #endif /* portARMV8M_MINOR_VERSION >= 1 */ + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, + uint32_t ulBufferLength, + uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */ + + { + uint32_t i, ulBufferStartAddress, ulBufferEndAddress; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE ) + { + ulBufferStartAddress = ( uint32_t ) pvBuffer; + ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL ); + + for( i = 0; i < portTOTAL_NUM_REGIONS; i++ ) + { + /* Is the MPU region enabled? */ + if( ( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR & portMPU_RLAR_REGION_ENABLE ) == portMPU_RLAR_REGION_ENABLE ) + { + if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_AUTHORIZED( ulAccessRequested, + prvGetRegionAccessPermissions( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ) ) ) + { + xAccessGranted = pdTRUE; + break; + } + } + } + } + } + + return xAccessGranted; + } + +#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings; + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else + { + xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 ) + { + xAccessGranted = pdTRUE; + } + } + } + + return xAccessGranted; + } + + #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + ( void ) lInternalIndexOfKernelObject; + + /* If Access Control List feature is not used, all the tasks have + * access to all the kernel objects. */ + return pdTRUE; + } + + #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + { + uint32_t ulControl = 0x0; + + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); + + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; + + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM52/non_secure/portasm.c b/portable/GCC/ARM_CM52/non_secure/portasm.c new file mode 100644 index 000000000..0ebbe48a4 --- /dev/null +++ b/portable/GCC/ARM_CM52/non_secure/portasm.c @@ -0,0 +1,621 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION + * is defined correctly and privileged functions are placed in correct sections. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Portasm includes. */ +#include "portasm.h" + +/* System call numbers includes. */ +#include "mpu_syscall_numbers.h" + +/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the + * header files. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#if ( configENABLE_MPU == 1 ) + + void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " program_mpu_first_task: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r3] \n" /* r0 = pxCurrentTCB. */ + " \n" + " dmb \n" /* Complete outstanding transfers before disabling MPU. */ + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + " str r2, [r1] \n" /* Disable MPU. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */ + " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r1, [r2] \n" /* Program MAIR0. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " \n" + " movs r3, #4 \n" /* r3 = 4. */ + " str r3, [r1] \n" /* Program RNR = 4. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + " \n" + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " orr r2, #1 \n" /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */ + " str r2, [r1] \n" /* Enable MPU. */ + " dsb \n" /* Force memory writes before continuing. */ + " \n" + " restore_context_first_task: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* r1 = pxCurrentTCB.*/ + " ldr r2, [r1] \n" /* r2 = Location of saved context in TCB. */ + " \n" + " restore_special_regs_first_task: \n" + #if ( configENABLE_PAC == 1 ) + " ldmdb r2!, {r3-r6} \n" /* Read task's dedicated PAC key from the task's context. */ + " msr PAC_KEY_P_0, r3 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_1, r4 \n" + " msr PAC_KEY_P_2, r5 \n" + " msr PAC_KEY_P_3, r6 \n" + " clrm {r3-r6} \n" /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + " ldmdb r2!, {r0, r3-r5, lr} \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */ + " msr psp, r3 \n" + " msr psplim, r4 \n" + " msr control, r5 \n" + " ldr r4, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " str r0, [r4] \n" /* Restore xSecureContext. */ + " \n" + " restore_general_regs_first_task: \n" + " ldmdb r2!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */ + " stmia r3!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */ + " ldmdb r2!, {r4-r11} \n" /* r4-r11 restored. */ + " \n" + " restore_context_done_first_task: \n" + " str r2, [r1] \n" /* Save the location where the context should be saved next as the first member of TCB. */ + " mov r0, #0 \n" + " msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */ + " bx lr \n" + ); + } + +#else /* configENABLE_MPU */ + + void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r3, [r2] \n" /* Read pxCurrentTCB. */ + " ldr r0, [r3] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + " \n" + #if ( configENABLE_PAC == 1 ) + " ldmia r0!, {r1-r4} \n" /* Read task's dedicated PAC key from stack. */ + " msr PAC_KEY_P_3, r1 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_2, r2 \n" + " msr PAC_KEY_P_1, r3 \n" + " msr PAC_KEY_P_0, r4 \n" + " clrm {r1-r4} \n" /* Clear r1-r4. */ + #endif /* configENABLE_PAC */ + " \n" + " ldm r0!, {r1-r3} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */ + " ldr r4, =xSecureContext \n" + " str r1, [r4] \n" /* Set xSecureContext to this task's value for the same. */ + " msr psplim, r2 \n" /* Set this task's PSPLIM value. */ + " mrs r1, control \n" /* Obtain current control register value. */ + " orrs r1, r1, #2 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */ + " msr control, r1 \n" /* Write back the new control register value. */ + " adds r0, #32 \n" /* Discard everything up to r0. */ + " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */ + " isb \n" + " mov r0, #0 \n" + " msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */ + " bx r3 \n" /* Finally, branch to EXC_RETURN. */ + ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* r0 = CONTROL. */ + " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + " ite ne \n" + " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + " bx lr \n" /* Return. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* Read the CONTROL register. */ + " bic r0, #1 \n" /* Clear the bit 0. */ + " msr control, r0 \n" /* Write back the new CONTROL value. */ + " bx lr \n" /* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vResetPrivilege( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* r0 = CONTROL. */ + " orr r0, #1 \n" /* r0 = r0 | 1. */ + " msr control, r0 \n" /* CONTROL = r0. */ + " bx lr \n" /* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r0, =0xe000ed08 \n" /* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */ + " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */ + " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */ + " cpsie i \n" /* Globally enable interrupts. */ + " cpsie f \n" + " dsb \n" + " isb \n" + " svc %0 \n" /* System call to start the first task. */ + " nop \n" + ::"i" ( portSVC_START_SCHEDULER ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, basepri \n" /* r0 = basepri. Return original basepri value. */ + " mov r1, %0 \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r1 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bx lr \n" /* Return. */ + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " msr basepri, r0 \n" /* basepri = ulMask. */ + " dsb \n" + " isb \n" + " bx lr \n" /* Return. */ + ::: "memory" + ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern SecureContext_SaveContext \n" + " .extern SecureContext_LoadContext \n" + " \n" + " ldr r3, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " ldr r0, [r3] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */ + " ldr r2, [r1] \n" /* r2 = Location in TCB where the context should be saved. */ + " \n" + " cbz r0, save_ns_context \n" /* No secure context to save. */ + " save_s_context: \n" + " push {r0-r2, lr} \n" + " bl SecureContext_SaveContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r0-r2, lr} \n" + " \n" + " save_ns_context: \n" + " mov r3, lr \n" /* r3 = LR (EXC_RETURN). */ + " lsls r3, r3, #25 \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bmi save_special_regs \n" /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + " \n" + " save_general_regs: \n" + " mrs r3, psp \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " add r3, r3, #0x20 \n" /* Move r3 to location where s0 is saved. */ + " tst lr, #0x10 \n" + " ittt eq \n" + " vstmiaeq r2!, {s16-s31} \n" /* Store s16-s31. */ + " vldmiaeq r3, {s0-s16} \n" /* Copy hardware saved FP context into s0-s16. */ + " vstmiaeq r2!, {s0-s16} \n" /* Store hardware saved FP context. */ + " sub r3, r3, #0x20 \n" /* Set r3 back to the location of hardware saved context. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " stmia r2!, {r4-r11} \n" /* Store r4-r11. */ + " ldmia r3, {r4-r11} \n" /* Copy the hardware saved context into r4-r11. */ + " stmia r2!, {r4-r11} \n" /* Store the hardware saved context. */ + " \n" + " save_special_regs: \n" + " mrs r3, psp \n" /* r3 = PSP. */ + " mrs r4, psplim \n" /* r4 = PSPLIM. */ + " mrs r5, control \n" /* r5 = CONTROL. */ + " stmia r2!, {r0, r3-r5, lr} \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ + #if ( configENABLE_PAC == 1 ) + " mrs r3, PAC_KEY_P_0 \n" /* Read task's dedicated PAC key from the PAC key registers. */ + " mrs r4, PAC_KEY_P_1 \n" + " mrs r5, PAC_KEY_P_2 \n" + " mrs r6, PAC_KEY_P_3 \n" + " stmia r2!, {r3-r6} \n" /* Store the task's dedicated PAC key on the task's context. */ + " clrm {r3-r6} \n" /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + " str r2, [r1] \n" /* Save the location from where the context should be restored as the first member of TCB. */ + " \n" + " select_next_task: \n" + " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bl vTaskSwitchContext \n" + " mov r0, #0 \n" /* r0 = 0. */ + " msr basepri, r0 \n" /* Enable interrupts. */ + " \n" + " program_mpu: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r3] \n" /* r0 = pxCurrentTCB.*/ + " \n" + " dmb \n" /* Complete outstanding transfers before disabling MPU. */ + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + " str r2, [r1] \n" /* Disable MPU. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */ + " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r1, [r2] \n" /* Program MAIR0. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " \n" + " movs r3, #4 \n" /* r3 = 4. */ + " str r3, [r1] \n" /* Program RNR = 4. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + " \n" + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " orr r2, #1 \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */ + " str r2, [r1] \n" /* Enable MPU. */ + " dsb \n" /* Force memory writes before continuing. */ + " \n" + " restore_context: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* r1 = pxCurrentTCB.*/ + " ldr r2, [r1] \n" /* r2 = Location of saved context in TCB. */ + " \n" + " restore_special_regs: \n" + #if ( configENABLE_PAC == 1 ) + " ldmdb r2!, {r3-r6} \n" /* Read task's dedicated PAC key from the task's context. */ + " msr PAC_KEY_P_0, r3 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_1, r4 \n" + " msr PAC_KEY_P_2, r5 \n" + " msr PAC_KEY_P_3, r6 \n" + " clrm {r3-r6} \n" /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + " ldmdb r2!, {r0, r3-r5, lr} \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */ + " msr psp, r3 \n" + " msr psplim, r4 \n" + " msr control, r5 \n" + " ldr r4, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " str r0, [r4] \n" /* Restore xSecureContext. */ + " cbz r0, restore_ns_context \n" /* No secure context to restore. */ + " \n" + " restore_s_context: \n" + " push {r1-r3, lr} \n" + " bl SecureContext_LoadContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r1-r3, lr} \n" + " \n" + " restore_ns_context: \n" + " mov r0, lr \n" /* r0 = LR (EXC_RETURN). */ + " lsls r0, r0, #25 \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bmi restore_context_done \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + " \n" + " restore_general_regs: \n" + " ldmdb r2!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */ + " stmia r3!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */ + " ldmdb r2!, {r4-r11} \n" /* r4-r11 restored. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" + " ittt eq \n" + " vldmdbeq r2!, {s0-s16} \n" /* s0-s16 contain hardware saved FP context. */ + " vstmiaeq r3!, {s0-s16} \n" /* Copy hardware saved FP context on the task stack. */ + " vldmdbeq r2!, {s16-s31} \n" /* Restore s16-s31. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + " restore_context_done: \n" + " str r2, [r1] \n" /* Save the location where the context should be saved next as the first member of TCB. */ + " bx lr \n" + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); + } + +#else /* configENABLE_MPU */ + + void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern SecureContext_SaveContext \n" + " .extern SecureContext_LoadContext \n" + " \n" + " ldr r3, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " ldr r0, [r3] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */ + " mrs r2, psp \n" /* Read PSP in r2. */ + " \n" + " cbz r0, save_ns_context \n" /* No secure context to save. */ + " save_s_context: \n" + " push {r0-r2, lr} \n" + " bl SecureContext_SaveContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r0-r2, lr} \n" + " \n" + " save_ns_context: \n" + " mov r3, lr \n" /* r3 = LR (EXC_RETURN). */ + " lsls r3, r3, #25 \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bmi save_special_regs \n" /* If r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used. */ + " \n" + " save_general_regs: \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vstmdbeq r2!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " stmdb r2!, {r4-r11} \n" /* Store the registers that are not saved automatically. */ + " \n" + " save_special_regs: \n" + " mrs r3, psplim \n" /* r3 = PSPLIM. */ + " stmdb r2!, {r0, r3, lr} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */ + #if ( configENABLE_PAC == 1 ) + " mrs r3, PAC_KEY_P_3 \n" /* Read task's dedicated PAC key from the PAC key registers. */ + " mrs r4, PAC_KEY_P_2 \n" + " mrs r5, PAC_KEY_P_1 \n" + " mrs r6, PAC_KEY_P_0 \n" + " stmdb r2!, {r3-r6} \n" /* Store the task's dedicated PAC key on the stack. */ + " clrm {r3-r6} \n" /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + " \n" + " str r2, [r1] \n" /* Save the new top of stack in TCB. */ + " \n" + " select_next_task: \n" + " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bl vTaskSwitchContext \n" + " mov r0, #0 \n" /* r0 = 0. */ + " msr basepri, r0 \n" /* Enable interrupts. */ + " \n" + " restore_context: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* Read pxCurrentTCB. */ + " ldr r2, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */ + " \n" + " restore_special_regs: \n" + #if ( configENABLE_PAC == 1 ) + " ldmia r2!, {r3-r6} \n" /* Read task's dedicated PAC key from stack. */ + " msr PAC_KEY_P_3, r3 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_2, r4 \n" + " msr PAC_KEY_P_1, r5 \n" + " msr PAC_KEY_P_0, r6 \n" + " clrm {r3-r6} \n" /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + " ldmia r2!, {r0, r3, lr} \n" /* Read from stack - r0 = xSecureContext, r3 = PSPLIM and LR restored. */ + " msr psplim, r3 \n" /* Restore the PSPLIM register value for the task. */ + " ldr r3, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " str r0, [r3] \n" /* Restore the task's xSecureContext. */ + " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */ + " \n" + " restore_s_context: \n" + " push {r1-r3, lr} \n" + " bl SecureContext_LoadContext \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r1-r3, lr} \n" + " \n" + " restore_ns_context: \n" + " mov r0, lr \n" /* r0 = LR (EXC_RETURN). */ + " lsls r0, r0, #25 \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bmi restore_context_done \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + " \n" + " restore_general_regs: \n" + " ldmia r2!, {r4-r11} \n" /* Restore the registers that are not automatically restored. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vldmiaeq r2!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + " restore_context_done: \n" + " msr psp, r2 \n" /* Remember the new top of stack for the task. */ + " bx lr \n" + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + ".syntax unified \n" + ".extern vPortSVCHandler_C \n" + ".extern vSystemCallEnter \n" + ".extern vSystemCallExit \n" + " \n" + "tst lr, #4 \n" + "ite eq \n" + "mrseq r0, msp \n" + "mrsne r0, psp \n" + " \n" + "ldr r1, [r0, #24] \n" + "ldrb r2, [r1, #-2] \n" + "cmp r2, %0 \n" + "blt syscall_enter \n" + "cmp r2, %1 \n" + "beq syscall_exit \n" + "b vPortSVCHandler_C \n" + " \n" + "syscall_enter: \n" + " mov r1, lr \n" + " b vSystemCallEnter \n" + " \n" + "syscall_exit: \n" + " mov r1, lr \n" + " b vSystemCallExit \n" + " \n" + : /* No outputs. */ + : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT ) + : "r0", "r1", "r2", "memory" + ); + } + +#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " tst lr, #4 \n" + " ite eq \n" + " mrseq r0, msp \n" + " mrsne r0, psp \n" + " ldr r1, =vPortSVCHandler_C \n" + " bx r1 \n" + ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " svc %0 \n" /* Secure context is allocated in the supervisor call. */ + " bx lr \n" /* Return. */ + ::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, [r0] \n" /* The first item in the TCB is the top of the stack. */ + " ldr r1, [r2] \n" /* The first item on the stack is the task's xSecureContext. */ + " cmp r1, #0 \n" /* Raise svc if task's xSecureContext is not NULL. */ + " it ne \n" + " svcne %0 \n" /* Secure context is freed in the supervisor call. */ + " bx lr \n" /* Return. */ + ::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory" + ); +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM52/non_secure/portasm.h b/portable/GCC/ARM_CM52/non_secure/portasm.h new file mode 100644 index 000000000..b7021b024 --- /dev/null +++ b/portable/GCC/ARM_CM52/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kernel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/portable/GCC/ARM_CM52/non_secure/portmacro.h b/portable/GCC/ARM_CM52/non_secure/portmacro.h new file mode 100644 index 000000000..1041a03bd --- /dev/null +++ b/portable/GCC/ARM_CM52/non_secure/portmacro.h @@ -0,0 +1,80 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (c) 2025 Arm Technology (China) Co., Ltd.All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_MVE + #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE. +#endif /* configENABLE_MVE */ +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M52" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portARMV8M_MINOR_VERSION 1 +#define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/ARM_CM52/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM52/non_secure/portmacrocommon.h new file mode 100644 index 000000000..f373bcad5 --- /dev/null +++ b/portable/GCC/ARM_CM52/non_secure/portmacrocommon.h @@ -0,0 +1,582 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACROCOMMON_H +#define PORTMACROCOMMON_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. +#endif /* configENABLE_FPU */ + +#ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. +#endif /* configENABLE_MPU */ + +#ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. +#endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() +#define portINLINE __inline +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif +#define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ +extern BaseType_t xPortIsInsideInterrupt( void ); + +extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + +extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; +extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + +extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; +extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + +#if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_PAC == 1 ) + + /** + * @brief Generates 128-bit task's random PAC key. + * + * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be + * filled with a 128-bit random number. + */ + void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); + +#endif /* configENABLE_PAC */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ +#if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) +#else + #define portPRIVILEGE_BIT ( 0x0UL ) +#endif /* configENABLE_MPU */ + +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ +#define portPRIVILEGED_FLASH_REGION ( 0UL ) +#define portUNPRIVILEGED_FLASH_REGION ( 1UL ) +#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) +#define portPRIVILEGED_RAM_REGION ( 3UL ) +#define portSTACK_REGION ( 4UL ) +#define portFIRST_CONFIGURABLE_REGION ( 5UL ) +#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) +#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) +#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ +#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ +#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ +#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ +#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ +#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ +#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ +#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) +#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) +#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + +#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) +#define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) +#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) +#define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + +#define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + #ifndef configSYSTEM_CALL_STACK_SIZE + #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. + #endif + + /** + * @brief System call stack. + */ + typedef struct SYSTEM_CALL_STACK_INFO + { + uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; + uint32_t * pulSystemCallStack; + uint32_t * pulSystemCallStackLimit; + uint32_t * pulTaskStack; + uint32_t ulLinkRegisterAtSystemCallEntry; + uint32_t ulStackLimitRegisterAtSystemCallEntry; + } xSYSTEM_CALL_STACK_INFO; + + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + /** + * @brief MPU settings as stored in the TCB. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><-----------><----> + * 16 17 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 71 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 17 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 55 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | | | PC, xPSR | EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><-----------><----> + * 16 17 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 70 + + #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + /* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 17 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 54 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+------------------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +----------+-----------------+------------------------------+------------+-----+ + * + * <---------><----------------><------------------------------><-----------><----> + * 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 38 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+----------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | PC, xPSR | EXC_RETURN | | | + * +----------+-----------------+----------------------+------------+-----+ + * + * <---------><----------------><----------------------><-----------><----> + * 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 37 + + #else /* #if( configENABLE_TRUSTZONE == 1 ) */ + + /* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) + + /* Size of an Access Control List (ACL) entry in bits. */ + #define portACL_ENTRY_SIZE_BITS ( 32U ) + + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + uint32_t ulContext[ MAX_CONTEXT_SIZE ]; + uint32_t ulTaskFlags; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo; + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ]; + #endif + #endif + } xMPU_SETTINGS; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Validate priority of ISRs that are allowed to call FreeRTOS + * system calls. + */ +#if ( configASSERT_DEFINED == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif +#endif + +/** + * @brief SVC numbers. + */ +#define portSVC_ALLOCATE_SECURE_CONTEXT 100 +#define portSVC_FREE_SECURE_CONTEXT 101 +#define portSVC_START_SCHEDULER 102 +#define portSVC_RAISE_PRIVILEGE 103 +#define portSVC_SYSTEM_CALL_EXIT 104 +#define portSVC_YIELD 105 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) +#endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() +#else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + extern BaseType_t xPortIsTaskPrivileged( void ); + +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACROCOMMON_H */ diff --git a/portable/GCC/ARM_CM52/secure/secure_context.c b/portable/GCC/ARM_CM52/secure/secure_context.c new file mode 100644 index 000000000..3aa335e63 --- /dev/null +++ b/portable/GCC/ARM_CM52/secure/secure_context.c @@ -0,0 +1,354 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Secure context includes. */ +#include "secure_context.h" + +/* Secure heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief CONTROL value for privileged tasks. + * + * Bit[0] - 0 --> Thread mode is privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_PRIVILEGED 0x02 + +/** + * @brief CONTROL value for un-privileged tasks. + * + * Bit[0] - 1 --> Thread mode is un-privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03 + +/** + * @brief Size of stack seal values in bytes. + */ +#define securecontextSTACK_SEAL_SIZE 8 + +/** + * @brief Stack seal value as recommended by ARM. + */ +#define securecontextSTACK_SEAL_VALUE 0xFEF5EDA5 + +/** + * @brief Maximum number of secure contexts. + */ +#ifndef secureconfigMAX_SECURE_CONTEXTS + #define secureconfigMAX_SECURE_CONTEXTS 8UL +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Pre-allocated array of secure contexts. + */ +SecureContext_t xSecureContexts[ secureconfigMAX_SECURE_CONTEXTS ]; +/*-----------------------------------------------------------*/ + +/** + * @brief Get a free secure context for a task from the secure context pool (xSecureContexts). + * + * This function ensures that only one secure context is allocated for a task. + * + * @param[in] pvTaskHandle The task handle for which the secure context is allocated. + * + * @return Index of a free secure context in the xSecureContexts array. + */ +static uint32_t ulGetSecureContext( void * pvTaskHandle ); + +/** + * @brief Return the secure context to the secure context pool (xSecureContexts). + * + * @param[in] ulSecureContextIndex Index of the context in the xSecureContexts array. + */ +static void vReturnSecureContext( uint32_t ulSecureContextIndex ); + +/* These are implemented in assembly. */ +extern void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ); +extern void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ); +/*-----------------------------------------------------------*/ + +static uint32_t ulGetSecureContext( void * pvTaskHandle ) +{ + /* Start with invalid index. */ + uint32_t i, ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + if( ( xSecureContexts[ i ].pucCurrentStackPointer == NULL ) && + ( xSecureContexts[ i ].pucStackLimit == NULL ) && + ( xSecureContexts[ i ].pucStackStart == NULL ) && + ( xSecureContexts[ i ].pvTaskHandle == NULL ) && + ( ulSecureContextIndex == secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = i; + } + else if( xSecureContexts[ i ].pvTaskHandle == pvTaskHandle ) + { + /* A task can only have one secure context. Do not allocate a second + * context for the same task. */ + ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + break; + } + } + + return ulSecureContextIndex; +} +/*-----------------------------------------------------------*/ + +static void vReturnSecureContext( uint32_t ulSecureContextIndex ) +{ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackStart = NULL; + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = NULL; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) +{ + uint32_t ulIPSR, i; + static uint32_t ulSecureContextsInitialized = 0; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ( ulIPSR != 0 ) && ( ulSecureContextsInitialized == 0 ) ) + { + /* Ensure to initialize secure contexts only once. */ + ulSecureContextsInitialized = 1; + + /* No stack for thread mode until a task's context is loaded. */ + secureportSET_PSPLIM( securecontextNO_STACK ); + secureportSET_PSP( securecontextNO_STACK ); + + /* Initialize all secure contexts. */ + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + xSecureContexts[ i ].pucCurrentStackPointer = NULL; + xSecureContexts[ i ].pucStackLimit = NULL; + xSecureContexts[ i ].pucStackStart = NULL; + xSecureContexts[ i ].pvTaskHandle = NULL; + } + + #if ( configENABLE_MPU == 1 ) + { + /* Configure thread mode to use PSP and to be unprivileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); + } + #else /* configENABLE_MPU */ + { + /* Configure thread mode to use PSP and to be privileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); + } + #endif /* configENABLE_MPU */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ) +#else /* configENABLE_MPU */ + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ) +#endif /* configENABLE_MPU */ +{ + uint8_t * pucStackMemory = NULL; + uint8_t * pucStackLimit; + uint32_t ulIPSR, ulSecureContextIndex; + SecureContextHandle_t xSecureContextHandle = securecontextINVALID_CONTEXT_ID; + + #if ( configENABLE_MPU == 1 ) + uint32_t * pulCurrentStackPointer = NULL; + #endif /* configENABLE_MPU */ + + /* Read the Interrupt Program Status Register (IPSR) and Process Stack Limit + * Register (PSPLIM) value. */ + secureportREAD_IPSR( ulIPSR ); + secureportREAD_PSPLIM( pucStackLimit ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. + * Also do nothing, if a secure context us already loaded. PSPLIM is set to + * securecontextNO_STACK when no secure context is loaded. */ + if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) ) + { + /* Obtain a free secure context. */ + ulSecureContextIndex = ulGetSecureContext( pvTaskHandle ); + + /* Were we able to get a free context? */ + if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS ) + { + /* Allocate the stack space. */ + pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + + if( pucStackMemory != NULL ) + { + /* Since stack grows down, the starting point will be the last + * location. Note that this location is next to the last + * allocated byte for stack (excluding the space for seal values) + * because the hardware decrements the stack pointer before + * writing i.e. if stack pointer is 0x2, a push operation will + * decrement the stack pointer to 0x1 and then write at 0x1. */ + xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize; + + /* Seal the created secure process stack. */ + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; + + /* The stack cannot go beyond this location. This value is + * programmed in the PSPLIM register on context switch.*/ + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = pucStackMemory; + + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle; + + #if ( configENABLE_MPU == 1 ) + { + /* Store the correct CONTROL value for the task on the stack. + * This value is programmed in the CONTROL register on + * context switch. */ + pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; + pulCurrentStackPointer--; + + if( ulIsTaskPrivileged ) + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; + } + else + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; + } + + /* Store the current stack pointer. This value is programmed in + * the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + } + #else /* configENABLE_MPU */ + { + /* Current SP is set to the starting of the stack. This + * value programmed in the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + } + #endif /* configENABLE_MPU */ + + /* Ensure to never return 0 as a valid context handle. */ + xSecureContextHandle = ulSecureContextIndex + 1UL; + } + } + } + + return xSecureContextHandle; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) +{ + uint32_t ulIPSR, ulSecureContextIndex; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* Only free if a valid context handle is passed. */ + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + /* Ensure that the secure context being deleted is associated with + * the task. */ + if( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) + { + /* Free the stack space. */ + vPortFree( xSecureContexts[ ulSecureContextIndex ].pucStackLimit ); + + /* Return the secure context back to the free secure contexts pool. */ + vReturnSecureContext( ulSecureContextIndex ); + } + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that no secure context is loaded and the task is loading it's + * own context. */ + if( ( pucStackLimit == securecontextNO_STACK ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_LoadContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that task's context is loaded and the task is saving it's own + * context. */ + if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_SaveContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM52/secure/secure_context.h b/portable/GCC/ARM_CM52/secure/secure_context.h new file mode 100644 index 000000000..e36a8e430 --- /dev/null +++ b/portable/GCC/ARM_CM52/secure/secure_context.h @@ -0,0 +1,138 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_CONTEXT_H__ +#define __SECURE_CONTEXT_H__ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" + +/** + * @brief PSP value when no secure context is loaded. + */ +#define securecontextNO_STACK 0x0 + +/** + * @brief Invalid context ID. + */ +#define securecontextINVALID_CONTEXT_ID 0UL +/*-----------------------------------------------------------*/ + +/** + * @brief Structure to represent a secure context. + * + * @note Since stack grows down, pucStackStart is the highest address while + * pucStackLimit is the first address of the allocated memory. + */ +typedef struct SecureContext +{ + uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */ + uint8_t * pucStackLimit; /**< Last location of the stack memory (PSPLIM). */ + uint8_t * pucStackStart; /**< First location of the stack memory. */ + void * pvTaskHandle; /**< Task handle of the task this context is associated with. */ +} SecureContext_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Opaque handle for a secure context. + */ +typedef uint32_t SecureContextHandle_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Initializes the secure context management system. + * + * PSP is set to NULL and therefore a task must allocate and load a context + * before calling any secure side function in the thread mode. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureContext_Init( void ); + +/** + * @brief Allocates a context on the secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] ulSecureStackSize Size of the stack to allocate on secure side. + * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise. + * + * @return Opaque context handle if context is successfully allocated, NULL + * otherwise. + */ +#if ( configENABLE_MPU == 1 ) + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ); +#else /* configENABLE_MPU */ + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ); +#endif /* configENABLE_MPU */ + +/** + * @brief Frees the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the + * context to be freed. + */ +void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); + +/** + * @brief Loads the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be loaded. + */ +void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); + +/** + * @brief Saves the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be saved. + */ +void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); + +#endif /* __SECURE_CONTEXT_H__ */ diff --git a/portable/GCC/ARM_CM52/secure/secure_context_port.c b/portable/GCC/ARM_CM52/secure/secure_context_port.c new file mode 100644 index 000000000..2d3d9439d --- /dev/null +++ b/portable/GCC/ARM_CM52/secure/secure_context_port.c @@ -0,0 +1,97 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Secure context includes. */ +#include "secure_context.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) ); +void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) ); + +void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) +{ + /* pxSecureContext value is in r0. */ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r1, ipsr \n" /* r1 = IPSR. */ + " cbz r1, load_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */ + " ldmia r0!, {r1, r2} \n" /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */ + " \n" + #if ( configENABLE_MPU == 1 ) + " ldmia r1!, {r3} \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */ + " msr control, r3 \n" /* CONTROL = r3. */ + #endif /* configENABLE_MPU */ + " \n" + " msr psplim, r2 \n" /* PSPLIM = r2. */ + " msr psp, r1 \n" /* PSP = r1. */ + " \n" + " load_ctx_therad_mode: \n" + " bx lr \n" + " \n" + ::: "r0", "r1", "r2" + ); +} +/*-----------------------------------------------------------*/ + +void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) +{ + /* pxSecureContext value is in r0. */ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r1, ipsr \n" /* r1 = IPSR. */ + " cbz r1, save_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */ + " mrs r1, psp \n" /* r1 = PSP. */ + " \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " vstmdb r1!, {s0} \n" /* Trigger the deferred stacking of FPU registers. */ + " vldmia r1!, {s0} \n" /* Nullify the effect of the previous statement. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + #if ( configENABLE_MPU == 1 ) + " mrs r2, control \n" /* r2 = CONTROL. */ + " stmdb r1!, {r2} \n" /* Store CONTROL value on the stack. */ + #endif /* configENABLE_MPU */ + " \n" + " str r1, [r0] \n" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */ + " movs r1, %0 \n" /* r1 = securecontextNO_STACK. */ + " msr psplim, r1 \n" /* PSPLIM = securecontextNO_STACK. */ + " msr psp, r1 \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */ + " \n" + " save_ctx_therad_mode: \n" + " bx lr \n" + " \n" + ::"i" ( securecontextNO_STACK ) : "r1", "memory" + ); +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM52/secure/secure_heap.c b/portable/GCC/ARM_CM52/secure/secure_heap.c new file mode 100644 index 000000000..896b53e2d --- /dev/null +++ b/portable/GCC/ARM_CM52/secure/secure_heap.c @@ -0,0 +1,485 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Configuration includes. */ +#include "FreeRTOSConfig.h" + +/* Secure context heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Total heap size. + */ +#ifndef secureconfigTOTAL_HEAP_SIZE + #define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) ) +#endif + +/* No test marker by default. */ +#ifndef mtCOVERAGE_TEST_MARKER + #define mtCOVERAGE_TEST_MARKER() +#endif + +/* No tracing by default. */ +#ifndef traceMALLOC + #define traceMALLOC( pvReturn, xWantedSize ) +#endif + +/* No tracing by default. */ +#ifndef traceFREE + #define traceFREE( pv, xBlockSize ) +#endif + +/* Block sizes must not get too small. */ +#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) ) + +/* Assumes 8bit bytes! */ +#define secureheapBITS_PER_BYTE ( ( size_t ) 8 ) + +/* Max value that fits in a size_t type. */ +#define secureheapSIZE_MAX ( ~( ( size_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define secureheapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) ) + +/* MSB of the xBlockSize member of an BlockLink_t structure is used to track + * the allocation status of a block. When MSB of the xBlockSize member of + * an BlockLink_t structure is set then the block belongs to the application. + * When the bit is free the block is still part of the free heap space. */ +#define secureheapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) ) +#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 ) +#define secureheapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 ) +#define secureheapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK ) +#define secureheapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK ) +/*-----------------------------------------------------------*/ + +/* Allocate the memory for the heap. */ +#if ( configAPPLICATION_ALLOCATED_HEAP == 1 ) + +/* The application writer has already defined the array used for the RTOS +* heap - probably so it can be placed in a special segment or address. */ + extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#else /* configAPPLICATION_ALLOCATED_HEAP */ + static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#endif /* configAPPLICATION_ALLOCATED_HEAP */ + +/** + * @brief The linked list structure. + * + * This is used to link free blocks in order of their memory address. + */ +typedef struct A_BLOCK_LINK +{ + struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */ + size_t xBlockSize; /**< The size of the free block. */ +} BlockLink_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Called automatically to setup the required heap structures the first + * time pvPortMalloc() is called. + */ +static void prvHeapInit( void ); + +/** + * @brief Inserts a block of memory that is being freed into the correct + * position in the list of free memory blocks. + * + * The block being freed will be merged with the block in front it and/or the + * block behind it if the memory blocks are adjacent to each other. + * + * @param[in] pxBlockToInsert The block being freed. + */ +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ); +/*-----------------------------------------------------------*/ + +/** + * @brief The size of the structure placed at the beginning of each allocated + * memory block must by correctly byte aligned. + */ +static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + +/** + * @brief Create a couple of list links to mark the start and end of the list. + */ +static BlockLink_t xStart; +static BlockLink_t * pxEnd = NULL; + +/** + * @brief Keeps track of the number of free bytes remaining, but says nothing + * about fragmentation. + */ +static size_t xFreeBytesRemaining = 0U; +static size_t xMinimumEverFreeBytesRemaining = 0U; + +/*-----------------------------------------------------------*/ + +static void prvHeapInit( void ) +{ + BlockLink_t * pxFirstFreeBlock; + uint8_t * pucAlignedHeap; + size_t uxAddress; + size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE; + + /* Ensure the heap starts on a correctly aligned boundary. */ + uxAddress = ( size_t ) ucHeap; + + if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 ) + { + uxAddress += ( secureportBYTE_ALIGNMENT - 1 ); + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; + } + + pucAlignedHeap = ( uint8_t * ) uxAddress; + + /* xStart is used to hold a pointer to the first item in the list of free + * blocks. The void cast is used to prevent compiler warnings. */ + xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; + xStart.xBlockSize = ( size_t ) 0; + + /* pxEnd is used to mark the end of the list of free blocks and is inserted + * at the end of the heap space. */ + uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; + uxAddress -= xHeapStructSize; + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + pxEnd = ( void * ) uxAddress; + pxEnd->xBlockSize = 0; + pxEnd->pxNextFreeBlock = NULL; + + /* To start with there is a single free block that is sized to take up the + * entire heap space, minus the space taken by pxEnd. */ + pxFirstFreeBlock = ( void * ) pucAlignedHeap; + pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; + pxFirstFreeBlock->pxNextFreeBlock = pxEnd; + + /* Only one block exists - and it covers the entire usable heap space. */ + xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; +} +/*-----------------------------------------------------------*/ + +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) +{ + BlockLink_t * pxIterator; + uint8_t * puc; + + /* Iterate through the list until a block is found that has a higher address + * than the block being inserted. */ + for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) + { + /* Nothing to do here, just iterate to the right position. */ + } + + /* Do the block being inserted, and the block it is being inserted after + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxIterator; + + if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) + { + pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; + pxBlockToInsert = pxIterator; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Do the block being inserted, and the block it is being inserted before + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxBlockToInsert; + + if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) + { + if( pxIterator->pxNextFreeBlock != pxEnd ) + { + /* Form one big block from the two blocks. */ + pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxEnd; + } + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; + } + + /* If the block being inserted plugged a gap, so was merged with the block + * before and the block after, then it's pxNextFreeBlock pointer will have + * already been set, and should not be set here as that would make it point + * to itself. */ + if( pxIterator != pxBlockToInsert ) + { + pxIterator->pxNextFreeBlock = pxBlockToInsert; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} +/*-----------------------------------------------------------*/ + +void * pvPortMalloc( size_t xWantedSize ) +{ + BlockLink_t * pxBlock; + BlockLink_t * pxPreviousBlock; + BlockLink_t * pxNewBlockLink; + void * pvReturn = NULL; + size_t xAdditionalRequiredSize; + size_t xAllocatedBlockSize = 0; + + /* If this is the first call to malloc then the heap will require + * initialisation to setup the list of free blocks. */ + if( pxEnd == NULL ) + { + prvHeapInit(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xWantedSize > 0 ) + { + /* The wanted size must be increased so it can contain a BlockLink_t + * structure in addition to the requested amount of bytes. */ + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 ) + { + xWantedSize += xHeapStructSize; + + /* Ensure that blocks are always aligned to the required number + * of bytes. */ + if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 ) + { + /* Byte alignment required. */ + xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ); + + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 ) + { + xWantedSize += xAdditionalRequiredSize; + } + else + { + xWantedSize = 0; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + xWantedSize = 0; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Check the requested block size is not so large that the top bit is set. + * The top bit of the block size member of the BlockLink_t structure is used + * to determine who owns the block - the application or the kernel, so it + * must be free. */ + if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 ) + { + if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) + { + /* Traverse the list from the start (lowest address) block until + * one of adequate size is found. */ + pxPreviousBlock = &xStart; + pxBlock = xStart.pxNextFreeBlock; + + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + { + pxPreviousBlock = pxBlock; + pxBlock = pxBlock->pxNextFreeBlock; + } + + /* If the end marker was reached then a block of adequate size was + * not found. */ + if( pxBlock != pxEnd ) + { + /* Return the memory space pointed to - jumping over the + * BlockLink_t structure at its start. */ + pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); + + /* This block is being returned for use so must be taken out + * of the list of free blocks. */ + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + + /* If the block is larger than required it can be split into + * two. */ + if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE ) + { + /* This block is to be split into two. Create a new + * block following the number of bytes requested. The void + * cast is used to prevent byte alignment warnings from the + * compiler. */ + pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); + secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + + /* Calculate the sizes of two blocks split from the single + * block. */ + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + pxBlock->xBlockSize = xWantedSize; + + /* Insert the new block into the list of free blocks. */ + pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock; + pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xFreeBytesRemaining -= pxBlock->xBlockSize; + + if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) + { + xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xAllocatedBlockSize = pxBlock->xBlockSize; + + /* The block is being returned - it is allocated and owned by + * the application and has no "next" block. */ + secureheapALLOCATE_BLOCK( pxBlock ); + pxBlock->pxNextFreeBlock = NULL; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceMALLOC( pvReturn, xAllocatedBlockSize ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xAllocatedBlockSize; + + #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) + { + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */ + + secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 ); + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void * pv ) +{ + uint8_t * puc = ( uint8_t * ) pv; + BlockLink_t * pxLink; + + if( pv != NULL ) + { + /* The memory being freed will have an BlockLink_t structure immediately + * before it. */ + puc -= xHeapStructSize; + + /* This casting is to keep the compiler from issuing warnings. */ + pxLink = ( void * ) puc; + + /* Check the block is actually allocated. */ + secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ); + secureportASSERT( pxLink->pxNextFreeBlock == NULL ); + + if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ) + { + if( pxLink->pxNextFreeBlock == NULL ) + { + /* The block is being returned to the heap - it is no longer + * allocated. */ + secureheapFREE_BLOCK( pxLink ); + + secureportDISABLE_NON_SECURE_INTERRUPTS(); + { + /* Add this block to the list of free blocks. */ + xFreeBytesRemaining += pxLink->xBlockSize; + traceFREE( pv, pxLink->xBlockSize ); + prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); + } + secureportENABLE_NON_SECURE_INTERRUPTS(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } +} +/*-----------------------------------------------------------*/ + +size_t xPortGetFreeHeapSize( void ) +{ + return xFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +size_t xPortGetMinimumEverFreeHeapSize( void ) +{ + return xMinimumEverFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM52/secure/secure_heap.h b/portable/GCC/ARM_CM52/secure/secure_heap.h new file mode 100644 index 000000000..0e84a9d9d --- /dev/null +++ b/portable/GCC/ARM_CM52/secure/secure_heap.h @@ -0,0 +1,66 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_HEAP_H__ +#define __SECURE_HEAP_H__ + +/* Standard includes. */ +#include + +/** + * @brief Allocates memory from heap. + * + * @param[in] xWantedSize The size of the memory to be allocated. + * + * @return Pointer to the memory region if the allocation is successful, NULL + * otherwise. + */ +void * pvPortMalloc( size_t xWantedSize ); + +/** + * @brief Frees the previously allocated memory. + * + * @param[in] pv Pointer to the memory to be freed. + */ +void vPortFree( void * pv ); + +/** + * @brief Get the free heap size. + * + * @return Free heap size. + */ +size_t xPortGetFreeHeapSize( void ); + +/** + * @brief Get the minimum ever free heap size. + * + * @return Minimum ever free heap size. + */ +size_t xPortGetMinimumEverFreeHeapSize( void ); + +#endif /* __SECURE_HEAP_H__ */ diff --git a/portable/GCC/ARM_CM52/secure/secure_init.c b/portable/GCC/ARM_CM52/secure/secure_init.c new file mode 100644 index 000000000..c50d37668 --- /dev/null +++ b/portable/GCC/ARM_CM52/secure/secure_init.c @@ -0,0 +1,106 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Secure init includes. */ +#include "secure_init.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Constants required to manipulate the SCB. + */ +#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */ +#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL ) +#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS ) +#define secureinitSCB_AIRCR_PRIS_POS ( 14UL ) +#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS ) + +/** + * @brief Constants required to manipulate the FPU. + */ +#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define secureinitFPCCR_LSPENS_POS ( 29UL ) +#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS ) +#define secureinitFPCCR_TS_POS ( 26UL ) +#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS ) + +#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */ +#define secureinitNSACR_CP10_POS ( 10UL ) +#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS ) +#define secureinitNSACR_CP11_POS ( 11UL ) +#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS ) +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) | + ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) | + ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK ); + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is + * permitted. CP11 should be programmed to the same value as CP10. */ + *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK ); + + /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures + * that we can enable/disable lazy stacking in port.c file. */ + *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK ); + + /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP + * registers (S16-S31) are also pushed to stack on exception entry and + * restored on exception return. */ + *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK ); + } +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM52/secure/secure_init.h b/portable/GCC/ARM_CM52/secure/secure_init.h new file mode 100644 index 000000000..ebe04900f --- /dev/null +++ b/portable/GCC/ARM_CM52/secure/secure_init.h @@ -0,0 +1,54 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_INIT_H__ +#define __SECURE_INIT_H__ + +/** + * @brief De-prioritizes the non-secure exceptions. + * + * This is needed to ensure that the non-secure PendSV runs at the lowest + * priority. Context switch is done in the non-secure PendSV handler. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_DePrioritizeNSExceptions( void ); + +/** + * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access. + * + * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point + * Registers are not leaked to the non-secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_EnableNSFPUAccess( void ); + +#endif /* __SECURE_INIT_H__ */ diff --git a/portable/GCC/ARM_CM52/secure/secure_port_macros.h b/portable/GCC/ARM_CM52/secure/secure_port_macros.h new file mode 100644 index 000000000..a70da2c65 --- /dev/null +++ b/portable/GCC/ARM_CM52/secure/secure_port_macros.h @@ -0,0 +1,140 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_PORT_MACROS_H__ +#define __SECURE_PORT_MACROS_H__ + +/** + * @brief Byte alignment requirements. + */ +#define secureportBYTE_ALIGNMENT 8 +#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 ) + +/** + * @brief Macro to declare a function as non-secure callable. + */ +#if defined( __IAR_SYSTEMS_ICC__ ) + #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry __root +#else + #define secureportNON_SECURE_CALLABLE __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) ) +#endif + +/** + * @brief Set the secure PRIMASK value. + */ +#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Set the non-secure PRIMASK value. + */ +#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Read the PSP value in the given variable. + */ +#define secureportREAD_PSP( pucOutCurrentStackPointer ) \ + __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) ) + +/** + * @brief Set the PSP to the given value. + */ +#define secureportSET_PSP( pucCurrentStackPointer ) \ + __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) ) + +/** + * @brief Read the PSPLIM value in the given variable. + */ +#define secureportREAD_PSPLIM( pucOutStackLimit ) \ + __asm volatile ( "mrs %0, psplim" : "=r" ( pucOutStackLimit ) ) + +/** + * @brief Set the PSPLIM to the given value. + */ +#define secureportSET_PSPLIM( pucStackLimit ) \ + __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) ) + +/** + * @brief Set the NonSecure MSP to the given value. + */ +#define secureportSET_MSP_NS( pucMainStackPointer ) \ + __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) ) + +/** + * @brief Set the CONTROL register to the given value. + */ +#define secureportSET_CONTROL( ulControl ) \ + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" ) + +/** + * @brief Read the Interrupt Program Status Register (IPSR) value in the given + * variable. + */ +#define secureportREAD_IPSR( ulIPSR ) \ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) ) + +/** + * @brief PRIMASK value to enable interrupts. + */ +#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0 + +/** + * @brief PRIMASK value to disable interrupts. + */ +#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1 + +/** + * @brief Disable secure interrupts. + */ +#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Disable non-secure interrupts. + * + * This effectively disables context switches. + */ +#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Enable non-secure interrupts. + */ +#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL ) + +/** + * @brief Assert definition. + */ +#define secureportASSERT( x ) \ + if( ( x ) == 0 ) \ + { \ + secureportDISABLE_SECURE_INTERRUPTS(); \ + secureportDISABLE_NON_SECURE_INTERRUPTS(); \ + for( ; ; ) {; } \ + } + +#endif /* __SECURE_PORT_MACROS_H__ */ diff --git a/portable/GCC/ARM_CM52_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM52_NTZ/non_secure/mpu_wrappers_v2_asm.c new file mode 100644 index 000000000..4b984932d --- /dev/null +++ b/portable/GCC/ARM_CM52_NTZ/non_secure/mpu_wrappers_v2_asm.c @@ -0,0 +1,2055 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" +#include "event_groups.h" +#include "stream_buffer.h" +#include "mpu_prototypes.h" +#include "mpu_syscall_numbers.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( INCLUDE_xTaskDelayUntil == 1 ) + + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskDelayUntilImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskDelayUntil_Unpriv \n" + " MPU_xTaskDelayUntil_Priv: \n" + " b MPU_xTaskDelayUntilImpl \n" + " MPU_xTaskDelayUntil_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskAbortDelayImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskAbortDelay_Unpriv \n" + " MPU_xTaskAbortDelay_Priv: \n" + " b MPU_xTaskAbortDelayImpl \n" + " MPU_xTaskAbortDelay_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskDelay == 1 ) + + void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskDelayImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskDelay_Unpriv \n" + " MPU_vTaskDelay_Priv: \n" + " b MPU_vTaskDelayImpl \n" + " MPU_vTaskDelay_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskPriorityGet == 1 ) + + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskPriorityGetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskPriorityGet_Unpriv \n" + " MPU_uxTaskPriorityGet_Priv: \n" + " b MPU_uxTaskPriorityGetImpl \n" + " MPU_uxTaskPriorityGet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_eTaskGetState == 1 ) + + eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_eTaskGetStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_eTaskGetState_Unpriv \n" + " MPU_eTaskGetState_Priv: \n" + " b MPU_eTaskGetStateImpl \n" + " MPU_eTaskGetState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory" + ); + } + + #endif /* if ( INCLUDE_eTaskGetState == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskGetInfoImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskGetInfo_Unpriv \n" + " MPU_vTaskGetInfo_Priv: \n" + " b MPU_vTaskGetInfoImpl \n" + " MPU_vTaskGetInfo_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory" + ); + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) + + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetIdleTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetIdleTaskHandle_Unpriv \n" + " MPU_xTaskGetIdleTaskHandle_Priv: \n" + " b MPU_xTaskGetIdleTaskHandleImpl \n" + " MPU_xTaskGetIdleTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + + void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSuspendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSuspend_Unpriv \n" + " MPU_vTaskSuspend_Priv: \n" + " b MPU_vTaskSuspendImpl \n" + " MPU_vTaskSuspend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + + void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskResumeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskResume_Unpriv \n" + " MPU_vTaskResume_Priv: \n" + " b MPU_vTaskResumeImpl \n" + " MPU_vTaskResume_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + TickType_t MPU_xTaskGetTickCount( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetTickCountImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetTickCount_Unpriv \n" + " MPU_xTaskGetTickCount_Priv: \n" + " b MPU_xTaskGetTickCountImpl \n" + " MPU_xTaskGetTickCount_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetNumberOfTasksImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetNumberOfTasks_Unpriv \n" + " MPU_uxTaskGetNumberOfTasks_Priv: \n" + " b MPU_uxTaskGetNumberOfTasksImpl \n" + " MPU_uxTaskGetNumberOfTasks_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetRunTimeCounterImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetRunTimeCounter_Unpriv \n" + " MPU_ulTaskGetRunTimeCounter_Priv: \n" + " b MPU_ulTaskGetRunTimeCounterImpl \n" + " MPU_ulTaskGetRunTimeCounter_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetRunTimePercentImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetRunTimePercent_Unpriv \n" + " MPU_ulTaskGetRunTimePercent_Priv: \n" + " b MPU_ulTaskGetRunTimePercentImpl \n" + " MPU_ulTaskGetRunTimePercent_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetIdleRunTimePercentImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv \n" + " MPU_ulTaskGetIdleRunTimePercent_Priv: \n" + " b MPU_ulTaskGetIdleRunTimePercentImpl \n" + " MPU_ulTaskGetIdleRunTimePercent_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetIdleRunTimeCounterImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv \n" + " MPU_ulTaskGetIdleRunTimeCounter_Priv: \n" + " b MPU_ulTaskGetIdleRunTimeCounterImpl \n" + " MPU_ulTaskGetIdleRunTimeCounter_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetApplicationTaskTagImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetApplicationTaskTag_Unpriv \n" + " MPU_vTaskSetApplicationTaskTag_Priv: \n" + " b MPU_vTaskSetApplicationTaskTagImpl \n" + " MPU_vTaskSetApplicationTaskTag_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory" + ); + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetApplicationTaskTagImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetApplicationTaskTag_Unpriv \n" + " MPU_xTaskGetApplicationTaskTag_Priv: \n" + " b MPU_xTaskGetApplicationTaskTagImpl \n" + " MPU_xTaskGetApplicationTaskTag_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory" + ); + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetThreadLocalStoragePointerImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv \n" + " MPU_vTaskSetThreadLocalStoragePointer_Priv: \n" + " b MPU_vTaskSetThreadLocalStoragePointerImpl \n" + " MPU_vTaskSetThreadLocalStoragePointer_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory" + ); + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv \n" + " MPU_pvTaskGetThreadLocalStoragePointer_Priv: \n" + " b MPU_pvTaskGetThreadLocalStoragePointerImpl \n" + " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory" + ); + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetSystemStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetSystemState_Unpriv \n" + " MPU_uxTaskGetSystemState_Priv: \n" + " b MPU_uxTaskGetSystemStateImpl \n" + " MPU_uxTaskGetSystemState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory" + ); + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) + + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetStackHighWaterMarkImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetStackHighWaterMark_Unpriv \n" + " MPU_uxTaskGetStackHighWaterMark_Priv: \n" + " b MPU_uxTaskGetStackHighWaterMarkImpl \n" + " MPU_uxTaskGetStackHighWaterMark_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetStackHighWaterMark2Impl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv \n" + " MPU_uxTaskGetStackHighWaterMark2_Priv: \n" + " b MPU_uxTaskGetStackHighWaterMark2Impl \n" + " MPU_uxTaskGetStackHighWaterMark2_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) + + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetCurrentTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetCurrentTaskHandle_Unpriv \n" + " MPU_xTaskGetCurrentTaskHandle_Priv: \n" + " b MPU_xTaskGetCurrentTaskHandleImpl \n" + " MPU_xTaskGetCurrentTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory" + ); + } + + #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetSchedulerState == 1 ) + + BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetSchedulerStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetSchedulerState_Unpriv \n" + " MPU_xTaskGetSchedulerState_Priv: \n" + " b MPU_xTaskGetSchedulerStateImpl \n" + " MPU_xTaskGetSchedulerState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */ +/*-----------------------------------------------------------*/ + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetTimeOutStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetTimeOutState_Unpriv \n" + " MPU_vTaskSetTimeOutState_Priv: \n" + " b MPU_vTaskSetTimeOutStateImpl \n" + " MPU_vTaskSetTimeOutState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskCheckForTimeOutImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskCheckForTimeOut_Unpriv \n" + " MPU_xTaskCheckForTimeOut_Priv: \n" + " b MPU_xTaskCheckForTimeOutImpl \n" + " MPU_xTaskCheckForTimeOut_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotify_Unpriv \n" + " MPU_xTaskGenericNotify_Priv: \n" + " b MPU_xTaskGenericNotifyImpl \n" + " MPU_xTaskGenericNotify_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyWaitImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotifyWait_Unpriv \n" + " MPU_xTaskGenericNotifyWait_Priv: \n" + " b MPU_xTaskGenericNotifyWaitImpl \n" + " MPU_xTaskGenericNotifyWait_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGenericNotifyTakeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGenericNotifyTake_Unpriv \n" + " MPU_ulTaskGenericNotifyTake_Priv: \n" + " b MPU_ulTaskGenericNotifyTakeImpl \n" + " MPU_ulTaskGenericNotifyTake_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyStateClearImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotifyStateClear_Unpriv \n" + " MPU_xTaskGenericNotifyStateClear_Priv: \n" + " b MPU_xTaskGenericNotifyStateClearImpl \n" + " MPU_xTaskGenericNotifyStateClear_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGenericNotifyValueClearImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGenericNotifyValueClear_Unpriv \n" + " MPU_ulTaskGenericNotifyValueClear_Priv: \n" + " b MPU_ulTaskGenericNotifyValueClearImpl \n" + " MPU_ulTaskGenericNotifyValueClear_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGenericSendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGenericSend_Unpriv \n" + " MPU_xQueueGenericSend_Priv: \n" + " b MPU_xQueueGenericSendImpl \n" + " MPU_xQueueGenericSend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxQueueMessagesWaitingImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxQueueMessagesWaiting_Unpriv \n" + " MPU_uxQueueMessagesWaiting_Priv: \n" + " b MPU_uxQueueMessagesWaitingImpl \n" + " MPU_uxQueueMessagesWaiting_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxQueueSpacesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxQueueSpacesAvailable_Unpriv \n" + " MPU_uxQueueSpacesAvailable_Priv: \n" + " b MPU_uxQueueSpacesAvailableImpl \n" + " MPU_uxQueueSpacesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueReceiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueReceive_Unpriv \n" + " MPU_xQueueReceive_Priv: \n" + " b MPU_xQueueReceiveImpl \n" + " MPU_xQueueReceive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueuePeekImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueuePeek_Unpriv \n" + " MPU_xQueuePeek_Priv: \n" + " b MPU_xQueuePeekImpl \n" + " MPU_xQueuePeek_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueSemaphoreTakeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueSemaphoreTake_Unpriv \n" + " MPU_xQueueSemaphoreTake_Priv: \n" + " b MPU_xQueueSemaphoreTakeImpl \n" + " MPU_xQueueSemaphoreTake_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) + + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGetMutexHolderImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGetMutexHolder_Unpriv \n" + " MPU_xQueueGetMutexHolder_Priv: \n" + " b MPU_xQueueGetMutexHolderImpl \n" + " MPU_xQueueGetMutexHolder_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory" + ); + } + + #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueTakeMutexRecursiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueTakeMutexRecursive_Unpriv \n" + " MPU_xQueueTakeMutexRecursive_Priv: \n" + " b MPU_xQueueTakeMutexRecursiveImpl \n" + " MPU_xQueueTakeMutexRecursive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory" + ); + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGiveMutexRecursiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGiveMutexRecursive_Unpriv \n" + " MPU_xQueueGiveMutexRecursive_Priv: \n" + " b MPU_xQueueGiveMutexRecursiveImpl \n" + " MPU_xQueueGiveMutexRecursive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory" + ); + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueSelectFromSetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueSelectFromSet_Unpriv \n" + " MPU_xQueueSelectFromSet_Priv: \n" + " b MPU_xQueueSelectFromSetImpl \n" + " MPU_xQueueSelectFromSet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory" + ); + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueAddToSetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueAddToSet_Unpriv \n" + " MPU_xQueueAddToSet_Priv: \n" + " b MPU_xQueueAddToSetImpl \n" + " MPU_xQueueAddToSet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory" + ); + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vQueueAddToRegistryImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vQueueAddToRegistry_Unpriv \n" + " MPU_vQueueAddToRegistry_Priv: \n" + " b MPU_vQueueAddToRegistryImpl \n" + " MPU_vQueueAddToRegistry_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vQueueUnregisterQueueImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vQueueUnregisterQueue_Unpriv \n" + " MPU_vQueueUnregisterQueue_Priv: \n" + " b MPU_vQueueUnregisterQueueImpl \n" + " MPU_vQueueUnregisterQueue_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pcQueueGetNameImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pcQueueGetName_Unpriv \n" + " MPU_pcQueueGetName_Priv: \n" + " b MPU_pcQueueGetNameImpl \n" + " MPU_pcQueueGetName_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pvTimerGetTimerIDImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pvTimerGetTimerID_Unpriv \n" + " MPU_pvTimerGetTimerID_Priv: \n" + " b MPU_pvTimerGetTimerIDImpl \n" + " MPU_pvTimerGetTimerID_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTimerSetTimerIDImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTimerSetTimerID_Unpriv \n" + " MPU_vTimerSetTimerID_Priv: \n" + " b MPU_vTimerSetTimerIDImpl \n" + " MPU_vTimerSetTimerID_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerIsTimerActiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerIsTimerActive_Unpriv \n" + " MPU_xTimerIsTimerActive_Priv: \n" + " b MPU_xTimerIsTimerActiveImpl \n" + " MPU_xTimerIsTimerActive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv \n" + " MPU_xTimerGetTimerDaemonTaskHandle_Priv: \n" + " b MPU_xTimerGetTimerDaemonTaskHandleImpl \n" + " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGenericCommandFromTaskImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGenericCommandFromTask_Unpriv \n" + " MPU_xTimerGenericCommandFromTask_Priv: \n" + " b MPU_xTimerGenericCommandFromTaskImpl \n" + " MPU_xTimerGenericCommandFromTask_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pcTimerGetNameImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pcTimerGetName_Unpriv \n" + " MPU_pcTimerGetName_Priv: \n" + " b MPU_pcTimerGetNameImpl \n" + " MPU_pcTimerGetName_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTimerSetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTimerSetReloadMode_Unpriv \n" + " MPU_vTimerSetReloadMode_Priv: \n" + " b MPU_vTimerSetReloadModeImpl \n" + " MPU_vTimerSetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetReloadMode_Unpriv \n" + " MPU_xTimerGetReloadMode_Priv: \n" + " b MPU_xTimerGetReloadModeImpl \n" + " MPU_xTimerGetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTimerGetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTimerGetReloadMode_Unpriv \n" + " MPU_uxTimerGetReloadMode_Priv: \n" + " b MPU_uxTimerGetReloadModeImpl \n" + " MPU_uxTimerGetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetPeriodImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetPeriod_Unpriv \n" + " MPU_xTimerGetPeriod_Priv: \n" + " b MPU_xTimerGetPeriodImpl \n" + " MPU_xTimerGetPeriod_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetExpiryTimeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetExpiryTime_Unpriv \n" + " MPU_xTimerGetExpiryTime_Priv: \n" + " b MPU_xTimerGetExpiryTimeImpl \n" + " MPU_xTimerGetExpiryTime_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupWaitBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupWaitBits_Unpriv \n" + " MPU_xEventGroupWaitBits_Priv: \n" + " b MPU_xEventGroupWaitBitsImpl \n" + " MPU_xEventGroupWaitBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupClearBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupClearBits_Unpriv \n" + " MPU_xEventGroupClearBits_Priv: \n" + " b MPU_xEventGroupClearBitsImpl \n" + " MPU_xEventGroupClearBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupSetBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupSetBits_Unpriv \n" + " MPU_xEventGroupSetBits_Priv: \n" + " b MPU_xEventGroupSetBitsImpl \n" + " MPU_xEventGroupSetBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupSyncImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupSync_Unpriv \n" + " MPU_xEventGroupSync_Priv: \n" + " b MPU_xEventGroupSyncImpl \n" + " MPU_xEventGroupSync_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxEventGroupGetNumberImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxEventGroupGetNumber_Unpriv \n" + " MPU_uxEventGroupGetNumber_Priv: \n" + " b MPU_uxEventGroupGetNumberImpl \n" + " MPU_uxEventGroupGetNumber_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory" + ); + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vEventGroupSetNumberImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vEventGroupSetNumber_Unpriv \n" + " MPU_vEventGroupSetNumber_Priv: \n" + " b MPU_vEventGroupSetNumberImpl \n" + " MPU_vEventGroupSetNumber_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory" + ); + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferSend_Unpriv \n" + " MPU_xStreamBufferSend_Priv: \n" + " b MPU_xStreamBufferSendImpl \n" + " MPU_xStreamBufferSend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferReceiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferReceive_Unpriv \n" + " MPU_xStreamBufferReceive_Priv: \n" + " b MPU_xStreamBufferReceiveImpl \n" + " MPU_xStreamBufferReceive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferIsFullImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferIsFull_Unpriv \n" + " MPU_xStreamBufferIsFull_Priv: \n" + " b MPU_xStreamBufferIsFullImpl \n" + " MPU_xStreamBufferIsFull_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferIsEmptyImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferIsEmpty_Unpriv \n" + " MPU_xStreamBufferIsEmpty_Priv: \n" + " b MPU_xStreamBufferIsEmptyImpl \n" + " MPU_xStreamBufferIsEmpty_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSpacesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferSpacesAvailable_Unpriv \n" + " MPU_xStreamBufferSpacesAvailable_Priv: \n" + " b MPU_xStreamBufferSpacesAvailableImpl \n" + " MPU_xStreamBufferSpacesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferBytesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferBytesAvailable_Unpriv \n" + " MPU_xStreamBufferBytesAvailable_Priv: \n" + " b MPU_xStreamBufferBytesAvailableImpl \n" + " MPU_xStreamBufferBytesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSetTriggerLevelImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferSetTriggerLevel_Unpriv \n" + " MPU_xStreamBufferSetTriggerLevel_Priv: \n" + " b MPU_xStreamBufferSetTriggerLevelImpl \n" + " MPU_xStreamBufferSetTriggerLevel_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferNextMessageLengthBytesImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv \n" + " MPU_xStreamBufferNextMessageLengthBytes_Priv: \n" + " b MPU_xStreamBufferNextMessageLengthBytesImpl \n" + " MPU_xStreamBufferNextMessageLengthBytes_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ diff --git a/portable/GCC/ARM_CM52_NTZ/non_secure/port.c b/portable/GCC/ARM_CM52_NTZ/non_secure/port.c new file mode 100644 index 000000000..76d2b2445 --- /dev/null +++ b/portable/GCC/ARM_CM52_NTZ/non_secure/port.c @@ -0,0 +1,2280 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024-2025 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU includes. */ +#include "mpu_wrappers.h" +#include "mpu_syscall_numbers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration settings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to check the validity of an interrupt priority. + */ +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) ) +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used during system call enter and exit. + */ +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Offsets in the stack to the parameters when inside the SVC handler. + */ +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +#if ( portARMV8M_MINOR_VERSION >= 1 ) + + /* Enable Privileged eXecute Never MPU attribute for the selected memory + * region. */ + #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL ) +#endif /* portARMV8M_MINOR_VERSION >= 1 */ + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Extract first address of the MPU region as encoded in the + * RBAR (Region Base Address Register) value. */ +#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \ + ( ( rbar ) & portMPU_RBAR_ADDRESS_MASK ) + +/* Extract last address of the MPU region as encoded in the + * RLAR (Region Limit Address Register) value. */ +#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \ + ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK ) + +/* Does addr lies within [start, end] address range? */ +#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \ + ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) ) + +/* Is the access request satisfied by the available permissions? */ +#define portIS_AUTHORIZED( accessRequest, permissions ) \ + ( ( ( permissions ) & ( accessRequest ) ) == accessRequest ) + +/* Max value that fits in a uint32_t type. */ +#define portUINT32_MAX ( ~( ( uint32_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. + */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 + +/** + * @brief Constants required to check and configure PACBTI security feature implementation. + */ +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) ) + + #define portCONTROL_UPAC_EN ( 1UL << 7UL ) + #define portCONTROL_PAC_EN ( 1UL << 6UL ) + #define portCONTROL_UBTI_EN ( 1UL << 5UL ) + #define portCONTROL_BTI_EN ( 1UL << 4UL ) + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Extract MPU region's access permissions from the Region Base Address + * Register (RBAR) value. + * + * @param ulRBARValue RBAR value for the MPU region. + * + * @return uint32_t Access permissions. + */ + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + + /** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + /** + * @brief Configures PACBTI features. + * + * This function configures the Pointer Authentication, and Branch Target + * Identification security features as per the user configuration. It returns + * the value of the special purpose CONTROL register accordingly, and optionally + * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M + * architecture based) target supports PACBTI security feature. + * + * @param xWriteControlRegister Used to control whether the special purpose + * CONTROL register should be updated or not. + * + * @return CONTROL register value according to the configured PACBTI option. + */ + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the system call stack so that upon returning from + * SVC, the system call stack is used. + * + * @param pulTaskStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + * @param ucSystemCallNumber The system call number of the system call. + */ + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Raise SVC for exiting from a system call. + */ + void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief This variable is set to pdTRUE when the scheduler is started. + */ + PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + + /** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +/** + * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + /** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + + /** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + + /** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the cpsid instruction + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessPermissions = 0; + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_ONLY ) + { + ulAccessPermissions = tskMPU_READ_PERMISSION; + } + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_WRITE ) + { + ulAccessPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION ); + } + + return ulAccessPermissions; + } + +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } + +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ portOFFSET_TO_PC ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ]; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulSystemCallStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the system call section (i.e. application is + * not raising SVC directly). + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as + * it is non-NULL only during the execution of a system call (i.e. + * between system call enter and exit). + * 3. System call is not for a kernel API disabled by the configuration + * in FreeRTOSConfig.h. + * 4. We do not need to check that ucSystemCallNumber is within range + * because the assembly SVC handler checks that before calling + * this function. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) && + ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) ) + { + pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the system call stack for the stack frame. */ + pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulSystemCallStack[ i ] = pulTaskStack[ i ]; + } + + /* Store the value of the Link Register before the SVC was raised. + * It contains the address of the caller of the System Call entry + * point (i.e. the caller of the MPU_). We need to restore it + * when we exit from the system call. */ + pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; + + /* Store the value of the PSPLIM register before the SVC was raised. + * We need to restore it when we exit from the system call. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* Use the pulSystemCallStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif + + /* Start executing the system call upon returning from this handler. */ + pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; + + /* Raise a request to exit from the system call upon finishing the + * system call. */ + pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; + + /* Remember the location where we should copy the stack frame when we exit from + * the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize; + + /* Record if the hardware used padding to force the stack pointer + * to be double word aligned. */ + if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK ) + { + pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG; + } + else + { + pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG ); + } + + /* We ensure in pxPortInitialiseStack that the system call stack is + * double word aligned and therefore, there is no need of padding. + * Clear the bit[9] of stacked xPSR. */ + pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + + /* Raise the privilege for the duration of the system call. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " bics r0, r1 \n" /* Clear nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */ + { + __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulTaskStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the privileged code (i.e. application is not + * raising SVC directly). This SVC is only raised from + * vRequestSystemCallExit which is in the privileged code section. + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL - + * this means that we previously entered a system call and the + * application is not attempting to exit without entering a system + * call. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) ) + { + pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the task stack for the stack frame. */ + pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulTaskStack[ i ] = pulSystemCallStack[ i ]; + } + + /* Use the pulTaskStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) ); + + /* Return to the caller of the System Call entry point (i.e. the + * caller of the MPU_). */ + pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + /* Ensure that LR has a valid value.*/ + pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + + /* Restore the PSPLIM register to what it was at the time of + * system call entry. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* If the hardware used padding to force the stack pointer + * to be double word aligned, set the stacked xPSR bit[9], + * otherwise clear it. */ + if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG ) + { + pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK; + } + else + { + pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + } + + /* This is not NULL only for the duration of the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; + + /* Drop the privilege before returning to the thread mode. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " orrs r0, r1 \n" /* Set nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xTaskIsPrivileged = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xTaskIsPrivileged = pdTRUE; + } + + return xTaskIsPrivileged; + } + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged, + xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulIndex = 0; + uint32_t ulControl = 0x0; + + xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ + ulIndex++; + + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + ulIndex++; + + #if ( configENABLE_TRUSTZONE == 1 ) + { + xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */ + ulIndex++; + } + #endif /* configENABLE_TRUSTZONE */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + ulIndex++; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Check PACBTI security feature configuration before pushing the + * CONTROL register's value on task's TCB. */ + ulControl = prvConfigurePACBTI( pdFALSE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + if( xRunPrivileged == pdTRUE ) + { + xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + else + { + xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG ); + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ + ulIndex++; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + { + /* Ensure that the system call stack is double word aligned. */ + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) + + ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + /* This is not NULL only for the duration of a system call. */ + xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL; + } + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ]; + ulIndex++; + } + } + #endif /* configENABLE_PAC */ + + return &( xMPUSettings->ulContext[ ulIndex ] ); + } + +#else /* configENABLE_MPU */ + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ + { + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + pxTopOfStack--; + *pxTopOfStack = ulTaskPacKey[ i ]; + } + } + #endif /* configENABLE_PAC */ + + return pxTopOfStack; + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Set the CONTROL register value based on PACBTI security feature + * configuration before starting the first task. */ + ( void ) prvConfigurePACBTI( pdTRUE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + { + xSchedulerRunning = pdTRUE; + } + #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + configSTACK_DEPTH_TYPE uxStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( uxStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* PXN. */ + #if ( portARMV8M_MINOR_VERSION >= 1 ) + { + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ); + } + } + #endif /* portARMV8M_MINOR_VERSION >= 1 */ + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, + uint32_t ulBufferLength, + uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */ + + { + uint32_t i, ulBufferStartAddress, ulBufferEndAddress; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE ) + { + ulBufferStartAddress = ( uint32_t ) pvBuffer; + ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL ); + + for( i = 0; i < portTOTAL_NUM_REGIONS; i++ ) + { + /* Is the MPU region enabled? */ + if( ( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR & portMPU_RLAR_REGION_ENABLE ) == portMPU_RLAR_REGION_ENABLE ) + { + if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_AUTHORIZED( ulAccessRequested, + prvGetRegionAccessPermissions( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ) ) ) + { + xAccessGranted = pdTRUE; + break; + } + } + } + } + } + + return xAccessGranted; + } + +#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings; + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else + { + xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 ) + { + xAccessGranted = pdTRUE; + } + } + } + + return xAccessGranted; + } + + #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + ( void ) lInternalIndexOfKernelObject; + + /* If Access Control List feature is not used, all the tasks have + * access to all the kernel objects. */ + return pdTRUE; + } + + #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + { + uint32_t ulControl = 0x0; + + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); + + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; + + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM52_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM52_NTZ/non_secure/portasm.c new file mode 100644 index 000000000..bc7bb6071 --- /dev/null +++ b/portable/GCC/ARM_CM52_NTZ/non_secure/portasm.c @@ -0,0 +1,524 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION + * is defined correctly and privileged functions are placed in correct sections. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Portasm includes. */ +#include "portasm.h" + +/* System call numbers includes. */ +#include "mpu_syscall_numbers.h" + +/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the + * header files. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#if ( configENABLE_MPU == 1 ) + + void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " program_mpu_first_task: \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */ + " \n" + " dmb \n" /* Complete outstanding transfers before disabling MPU. */ + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + " str r2, [r1] \n" /* Disable MPU. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */ + " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r1, [r2] \n" /* Program MAIR0. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " \n" + " movs r3, #4 \n" /* r3 = 4. */ + " str r3, [r1] \n" /* Program RNR = 4. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + " \n" + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " orr r2, #1 \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */ + " str r2, [r1] \n" /* Enable MPU. */ + " dsb \n" /* Force memory writes before continuing. */ + " \n" + " restore_context_first_task: \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/ + " ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */ + " \n" + " restore_special_regs_first_task: \n" + #if ( configENABLE_PAC == 1 ) + " ldmdb r1!, {r2-r5} \n" /* Read task's dedicated PAC key from the task's context. */ + " msr PAC_KEY_P_0, r2 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_1, r3 \n" + " msr PAC_KEY_P_2, r4 \n" + " msr PAC_KEY_P_3, r5 \n" + " clrm {r2-r5} \n" /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + " ldmdb r1!, {r2-r4, lr} \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */ + " msr psp, r2 \n" + " msr psplim, r3 \n" + " msr control, r4 \n" + " \n" + " restore_general_regs_first_task: \n" + " ldmdb r1!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */ + " stmia r2!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */ + " ldmdb r1!, {r4-r11} \n" /* r4-r11 restored. */ + " \n" + " restore_context_done_first_task: \n" + " str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */ + " mov r0, #0 \n" + " msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */ + " bx lr \n" + ); + } + +#else /* configENABLE_MPU */ + + void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + " ldr r0, [r1] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + " \n" + #if ( configENABLE_PAC == 1 ) + " ldmia r0!, {r1-r4} \n" /* Read task's dedicated PAC key from stack. */ + " msr PAC_KEY_P_3, r1 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_2, r2 \n" + " msr PAC_KEY_P_1, r3 \n" + " msr PAC_KEY_P_0, r4 \n" + " clrm {r1-r4} \n" /* Clear r1-r4. */ + #endif /* configENABLE_PAC */ + " \n" + " ldm r0!, {r1-r2} \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */ + " msr psplim, r1 \n" /* Set this task's PSPLIM value. */ + " mrs r1, control \n" /* Obtain current control register value. */ + " orrs r1, r1, #2 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */ + " msr control, r1 \n" /* Write back the new control register value. */ + " adds r0, #32 \n" /* Discard everything up to r0. */ + " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */ + " isb \n" + " mov r0, #0 \n" + " msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */ + " bx r2 \n" /* Finally, branch to EXC_RETURN. */ + ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* r0 = CONTROL. */ + " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + " ite ne \n" + " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + " bx lr \n" /* Return. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* Read the CONTROL register. */ + " bic r0, #1 \n" /* Clear the bit 0. */ + " msr control, r0 \n" /* Write back the new CONTROL value. */ + " bx lr \n" /* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vResetPrivilege( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* r0 = CONTROL. */ + " orr r0, #1 \n" /* r0 = r0 | 1. */ + " msr control, r0 \n" /* CONTROL = r0. */ + " bx lr \n" /* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r0, =0xe000ed08 \n" /* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */ + " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */ + " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */ + " cpsie i \n" /* Globally enable interrupts. */ + " cpsie f \n" + " dsb \n" + " isb \n" + " svc %0 \n" /* System call to start the first task. */ + " nop \n" + ::"i" ( portSVC_START_SCHEDULER ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, basepri \n" /* r0 = basepri. Return original basepri value. */ + " mov r1, %0 \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r1 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bx lr \n" /* Return. */ + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " msr basepri, r0 \n" /* basepri = ulMask. */ + " dsb \n" + " isb \n" + " bx lr \n" /* Return. */ + ::: "memory" + ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */ + " ldr r1, [r0] \n" /* r1 = Location in TCB where the context should be saved. */ + " mrs r2, psp \n" /* r2 = PSP. */ + " \n" + " save_general_regs: \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " add r2, r2, #0x20 \n" /* Move r2 to location where s0 is saved. */ + " tst lr, #0x10 \n" + " ittt eq \n" + " vstmiaeq r1!, {s16-s31} \n" /* Store s16-s31. */ + " vldmiaeq r2, {s0-s16} \n" /* Copy hardware saved FP context into s0-s16. */ + " vstmiaeq r1!, {s0-s16} \n" /* Store hardware saved FP context. */ + " sub r2, r2, #0x20 \n" /* Set r2 back to the location of hardware saved context. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " stmia r1!, {r4-r11} \n" /* Store r4-r11. */ + " ldmia r2, {r4-r11} \n" /* Copy the hardware saved context into r4-r11. */ + " stmia r1!, {r4-r11} \n" /* Store the hardware saved context. */ + " \n" + " save_special_regs: \n" + " mrs r3, psplim \n" /* r3 = PSPLIM. */ + " mrs r4, control \n" /* r4 = CONTROL. */ + " stmia r1!, {r2-r4, lr} \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ + #if ( configENABLE_PAC == 1 ) + " mrs r2, PAC_KEY_P_0 \n" /* Read task's dedicated PAC key from the PAC key registers. */ + " mrs r3, PAC_KEY_P_1 \n" + " mrs r4, PAC_KEY_P_2 \n" + " mrs r5, PAC_KEY_P_3 \n" + " stmia r1!, {r2-r5} \n" /* Store the task's dedicated PAC key on the task's context. */ + " clrm {r2-r5} \n" /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + " str r1, [r0] \n" /* Save the location from where the context should be restored as the first member of TCB. */ + " \n" + " select_next_task: \n" + " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bl vTaskSwitchContext \n" + " mov r0, #0 \n" /* r0 = 0. */ + " msr basepri, r0 \n" /* Enable interrupts. */ + " \n" + " program_mpu: \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */ + " \n" + " dmb \n" /* Complete outstanding transfers before disabling MPU. */ + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + " str r2, [r1] \n" /* Disable MPU. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */ + " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r1, [r2] \n" /* Program MAIR0. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " \n" + " movs r3, #4 \n" /* r3 = 4. */ + " str r3, [r1] \n" /* Program RNR = 4. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + " \n" + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " orr r2, #1 \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */ + " str r2, [r1] \n" /* Enable MPU. */ + " dsb \n" /* Force memory writes before continuing. */ + " \n" + " restore_context: \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/ + " ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */ + " \n" + " restore_special_regs: \n" + #if ( configENABLE_PAC == 1 ) + " ldmdb r1!, {r2-r5} \n" /* Read task's dedicated PAC key from the task's context. */ + " msr PAC_KEY_P_0, r2 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_1, r3 \n" + " msr PAC_KEY_P_2, r4 \n" + " msr PAC_KEY_P_3, r5 \n" + " clrm {r2-r5} \n" /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + " ldmdb r1!, {r2-r4, lr} \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */ + " msr psp, r2 \n" + " msr psplim, r3 \n" + " msr control, r4 \n" + " \n" + " restore_general_regs: \n" + " ldmdb r1!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */ + " stmia r2!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */ + " ldmdb r1!, {r4-r11} \n" /* r4-r11 restored. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" + " ittt eq \n" + " vldmdbeq r1!, {s0-s16} \n" /* s0-s16 contain hardware saved FP context. */ + " vstmiaeq r2!, {s0-s16} \n" /* Copy hardware saved FP context on the task stack. */ + " vldmdbeq r1!, {s16-s31} \n" /* Restore s16-s31. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + " restore_context_done: \n" + " str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */ + " bx lr \n" + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); + } + +#else /* configENABLE_MPU */ + + void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, psp \n" /* Read PSP in r0. */ + " \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vstmdbeq r0!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + " mrs r2, psplim \n" /* r2 = PSPLIM. */ + " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */ + " stmdb r0!, {r2-r11} \n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */ + " \n" + #if ( configENABLE_PAC == 1 ) + " mrs r1, PAC_KEY_P_3 \n" /* Read task's dedicated PAC key from the PAC key registers. */ + " mrs r2, PAC_KEY_P_2 \n" + " mrs r3, PAC_KEY_P_1 \n" + " mrs r4, PAC_KEY_P_0 \n" + " stmdb r0!, {r1-r4} \n" /* Store the task's dedicated PAC key on the stack. */ + " clrm {r1-r4} \n" /* Clear r1-r4. */ + #endif /* configENABLE_PAC */ + " \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + " str r0, [r1] \n" /* Save the new top of stack in TCB. */ + " \n" + " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bl vTaskSwitchContext \n" + " mov r0, #0 \n" /* r0 = 0. */ + " msr basepri, r0 \n" /* Enable interrupts. */ + " \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ + " \n" + #if ( configENABLE_PAC == 1 ) + " ldmia r0!, {r2-r5} \n" /* Read task's dedicated PAC key from stack. */ + " msr PAC_KEY_P_3, r2 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_2, r3 \n" + " msr PAC_KEY_P_1, r4 \n" + " msr PAC_KEY_P_0, r5 \n" + " clrm {r2-r5} \n" /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + " \n" + " ldmia r0!, {r2-r11} \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */ + " \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst r3, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vldmiaeq r0!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */ + " msr psp, r0 \n" /* Remember the new top of stack for the task. */ + " bx r3 \n" + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + ".syntax unified \n" + ".extern vPortSVCHandler_C \n" + ".extern vSystemCallEnter \n" + ".extern vSystemCallExit \n" + " \n" + "tst lr, #4 \n" + "ite eq \n" + "mrseq r0, msp \n" + "mrsne r0, psp \n" + " \n" + "ldr r1, [r0, #24] \n" + "ldrb r2, [r1, #-2] \n" + "cmp r2, %0 \n" + "blt syscall_enter \n" + "cmp r2, %1 \n" + "beq syscall_exit \n" + "b vPortSVCHandler_C \n" + " \n" + "syscall_enter: \n" + " mov r1, lr \n" + " b vSystemCallEnter \n" + " \n" + "syscall_exit: \n" + " mov r1, lr \n" + " b vSystemCallExit \n" + " \n" + : /* No outputs. */ + : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT ) + : "r0", "r1", "r2", "memory" + ); + } + +#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " tst lr, #4 \n" + " ite eq \n" + " mrseq r0, msp \n" + " mrsne r0, psp \n" + " ldr r1, =vPortSVCHandler_C \n" + " bx r1 \n" + ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM52_NTZ/non_secure/portasm.h b/portable/GCC/ARM_CM52_NTZ/non_secure/portasm.h new file mode 100644 index 000000000..b7021b024 --- /dev/null +++ b/portable/GCC/ARM_CM52_NTZ/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kernel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/portable/GCC/ARM_CM52_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM52_NTZ/non_secure/portmacro.h new file mode 100644 index 000000000..1041a03bd --- /dev/null +++ b/portable/GCC/ARM_CM52_NTZ/non_secure/portmacro.h @@ -0,0 +1,80 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (c) 2025 Arm Technology (China) Co., Ltd.All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_MVE + #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE. +#endif /* configENABLE_MVE */ +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M52" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portARMV8M_MINOR_VERSION 1 +#define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/ARM_CM52_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM52_NTZ/non_secure/portmacrocommon.h new file mode 100644 index 000000000..f373bcad5 --- /dev/null +++ b/portable/GCC/ARM_CM52_NTZ/non_secure/portmacrocommon.h @@ -0,0 +1,582 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACROCOMMON_H +#define PORTMACROCOMMON_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. +#endif /* configENABLE_FPU */ + +#ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. +#endif /* configENABLE_MPU */ + +#ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. +#endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() +#define portINLINE __inline +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif +#define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ +extern BaseType_t xPortIsInsideInterrupt( void ); + +extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + +extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; +extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + +extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; +extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + +#if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_PAC == 1 ) + + /** + * @brief Generates 128-bit task's random PAC key. + * + * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be + * filled with a 128-bit random number. + */ + void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); + +#endif /* configENABLE_PAC */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ +#if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) +#else + #define portPRIVILEGE_BIT ( 0x0UL ) +#endif /* configENABLE_MPU */ + +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ +#define portPRIVILEGED_FLASH_REGION ( 0UL ) +#define portUNPRIVILEGED_FLASH_REGION ( 1UL ) +#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) +#define portPRIVILEGED_RAM_REGION ( 3UL ) +#define portSTACK_REGION ( 4UL ) +#define portFIRST_CONFIGURABLE_REGION ( 5UL ) +#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) +#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) +#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ +#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ +#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ +#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ +#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ +#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ +#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ +#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) +#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) +#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + +#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) +#define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) +#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) +#define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + +#define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + #ifndef configSYSTEM_CALL_STACK_SIZE + #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. + #endif + + /** + * @brief System call stack. + */ + typedef struct SYSTEM_CALL_STACK_INFO + { + uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; + uint32_t * pulSystemCallStack; + uint32_t * pulSystemCallStackLimit; + uint32_t * pulTaskStack; + uint32_t ulLinkRegisterAtSystemCallEntry; + uint32_t ulStackLimitRegisterAtSystemCallEntry; + } xSYSTEM_CALL_STACK_INFO; + + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + /** + * @brief MPU settings as stored in the TCB. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><-----------><----> + * 16 17 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 71 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 17 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 55 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | | | PC, xPSR | EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><-----------><----> + * 16 17 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 70 + + #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + /* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 17 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 54 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+------------------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +----------+-----------------+------------------------------+------------+-----+ + * + * <---------><----------------><------------------------------><-----------><----> + * 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 38 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+----------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | PC, xPSR | EXC_RETURN | | | + * +----------+-----------------+----------------------+------------+-----+ + * + * <---------><----------------><----------------------><-----------><----> + * 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 37 + + #else /* #if( configENABLE_TRUSTZONE == 1 ) */ + + /* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) + + /* Size of an Access Control List (ACL) entry in bits. */ + #define portACL_ENTRY_SIZE_BITS ( 32U ) + + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + uint32_t ulContext[ MAX_CONTEXT_SIZE ]; + uint32_t ulTaskFlags; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo; + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ]; + #endif + #endif + } xMPU_SETTINGS; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Validate priority of ISRs that are allowed to call FreeRTOS + * system calls. + */ +#if ( configASSERT_DEFINED == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif +#endif + +/** + * @brief SVC numbers. + */ +#define portSVC_ALLOCATE_SECURE_CONTEXT 100 +#define portSVC_FREE_SECURE_CONTEXT 101 +#define portSVC_START_SCHEDULER 102 +#define portSVC_RAISE_PRIVILEGE 103 +#define portSVC_SYSTEM_CALL_EXIT 104 +#define portSVC_YIELD 105 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) +#endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() +#else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + extern BaseType_t xPortIsTaskPrivileged( void ); + +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACROCOMMON_H */ diff --git a/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c new file mode 100644 index 000000000..33410a0c3 --- /dev/null +++ b/portable/GCC/ARM_CM55/non_secure/mpu_wrappers_v2_asm.c @@ -0,0 +1,2056 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" +#include "event_groups.h" +#include "stream_buffer.h" +#include "mpu_prototypes.h" +#include "mpu_syscall_numbers.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( INCLUDE_xTaskDelayUntil == 1 ) + + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskDelayUntilImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskDelayUntil_Unpriv \n" + " MPU_xTaskDelayUntil_Priv: \n" + " b MPU_xTaskDelayUntilImpl \n" + " MPU_xTaskDelayUntil_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskAbortDelayImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskAbortDelay_Unpriv \n" + " MPU_xTaskAbortDelay_Priv: \n" + " b MPU_xTaskAbortDelayImpl \n" + " MPU_xTaskAbortDelay_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskDelay == 1 ) + + void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskDelayImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskDelay_Unpriv \n" + " MPU_vTaskDelay_Priv: \n" + " b MPU_vTaskDelayImpl \n" + " MPU_vTaskDelay_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskPriorityGet == 1 ) + + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskPriorityGetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskPriorityGet_Unpriv \n" + " MPU_uxTaskPriorityGet_Priv: \n" + " b MPU_uxTaskPriorityGetImpl \n" + " MPU_uxTaskPriorityGet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_eTaskGetState == 1 ) + + eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_eTaskGetStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_eTaskGetState_Unpriv \n" + " MPU_eTaskGetState_Priv: \n" + " b MPU_eTaskGetStateImpl \n" + " MPU_eTaskGetState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory" + ); + } + + #endif /* if ( INCLUDE_eTaskGetState == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskGetInfoImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskGetInfo_Unpriv \n" + " MPU_vTaskGetInfo_Priv: \n" + " b MPU_vTaskGetInfoImpl \n" + " MPU_vTaskGetInfo_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory" + ); + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) + + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetIdleTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetIdleTaskHandle_Unpriv \n" + " MPU_xTaskGetIdleTaskHandle_Priv: \n" + " b MPU_xTaskGetIdleTaskHandleImpl \n" + " MPU_xTaskGetIdleTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + + void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSuspendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSuspend_Unpriv \n" + " MPU_vTaskSuspend_Priv: \n" + " b MPU_vTaskSuspendImpl \n" + " MPU_vTaskSuspend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + + void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskResumeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskResume_Unpriv \n" + " MPU_vTaskResume_Priv: \n" + " b MPU_vTaskResumeImpl \n" + " MPU_vTaskResume_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + TickType_t MPU_xTaskGetTickCount( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetTickCountImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetTickCount_Unpriv \n" + " MPU_xTaskGetTickCount_Priv: \n" + " b MPU_xTaskGetTickCountImpl \n" + " MPU_xTaskGetTickCount_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetNumberOfTasksImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetNumberOfTasks_Unpriv \n" + " MPU_uxTaskGetNumberOfTasks_Priv: \n" + " b MPU_uxTaskGetNumberOfTasksImpl \n" + " MPU_uxTaskGetNumberOfTasks_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetRunTimeCounterImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetRunTimeCounter_Unpriv \n" + " MPU_ulTaskGetRunTimeCounter_Priv: \n" + " b MPU_ulTaskGetRunTimeCounterImpl \n" + " MPU_ulTaskGetRunTimeCounter_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetRunTimePercentImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetRunTimePercent_Unpriv \n" + " MPU_ulTaskGetRunTimePercent_Priv: \n" + " b MPU_ulTaskGetRunTimePercentImpl \n" + " MPU_ulTaskGetRunTimePercent_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetIdleRunTimePercentImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv \n" + " MPU_ulTaskGetIdleRunTimePercent_Priv: \n" + " b MPU_ulTaskGetIdleRunTimePercentImpl \n" + " MPU_ulTaskGetIdleRunTimePercent_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetIdleRunTimeCounterImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv \n" + " MPU_ulTaskGetIdleRunTimeCounter_Priv: \n" + " b MPU_ulTaskGetIdleRunTimeCounterImpl \n" + " MPU_ulTaskGetIdleRunTimeCounter_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetApplicationTaskTagImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetApplicationTaskTag_Unpriv \n" + " MPU_vTaskSetApplicationTaskTag_Priv: \n" + " b MPU_vTaskSetApplicationTaskTagImpl \n" + " MPU_vTaskSetApplicationTaskTag_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory" + ); + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetApplicationTaskTagImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetApplicationTaskTag_Unpriv \n" + " MPU_xTaskGetApplicationTaskTag_Priv: \n" + " b MPU_xTaskGetApplicationTaskTagImpl \n" + " MPU_xTaskGetApplicationTaskTag_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory" + ); + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetThreadLocalStoragePointerImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv \n" + " MPU_vTaskSetThreadLocalStoragePointer_Priv: \n" + " b MPU_vTaskSetThreadLocalStoragePointerImpl \n" + " MPU_vTaskSetThreadLocalStoragePointer_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory" + ); + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv \n" + " MPU_pvTaskGetThreadLocalStoragePointer_Priv: \n" + " b MPU_pvTaskGetThreadLocalStoragePointerImpl \n" + " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory" + ); + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetSystemStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetSystemState_Unpriv \n" + " MPU_uxTaskGetSystemState_Priv: \n" + " b MPU_uxTaskGetSystemStateImpl \n" + " MPU_uxTaskGetSystemState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory" + ); + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) + + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetStackHighWaterMarkImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetStackHighWaterMark_Unpriv \n" + " MPU_uxTaskGetStackHighWaterMark_Priv: \n" + " b MPU_uxTaskGetStackHighWaterMarkImpl \n" + " MPU_uxTaskGetStackHighWaterMark_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetStackHighWaterMark2Impl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv \n" + " MPU_uxTaskGetStackHighWaterMark2_Priv: \n" + " b MPU_uxTaskGetStackHighWaterMark2Impl \n" + " MPU_uxTaskGetStackHighWaterMark2_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) + + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetCurrentTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetCurrentTaskHandle_Unpriv \n" + " MPU_xTaskGetCurrentTaskHandle_Priv: \n" + " b MPU_xTaskGetCurrentTaskHandleImpl \n" + " MPU_xTaskGetCurrentTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory" + ); + } + + #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetSchedulerState == 1 ) + + BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetSchedulerStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetSchedulerState_Unpriv \n" + " MPU_xTaskGetSchedulerState_Priv: \n" + " b MPU_xTaskGetSchedulerStateImpl \n" + " MPU_xTaskGetSchedulerState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */ +/*-----------------------------------------------------------*/ + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetTimeOutStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetTimeOutState_Unpriv \n" + " MPU_vTaskSetTimeOutState_Priv: \n" + " b MPU_vTaskSetTimeOutStateImpl \n" + " MPU_vTaskSetTimeOutState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskCheckForTimeOutImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskCheckForTimeOut_Unpriv \n" + " MPU_xTaskCheckForTimeOut_Priv: \n" + " b MPU_xTaskCheckForTimeOutImpl \n" + " MPU_xTaskCheckForTimeOut_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotify_Unpriv \n" + " MPU_xTaskGenericNotify_Priv: \n" + " b MPU_xTaskGenericNotifyImpl \n" + " MPU_xTaskGenericNotify_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyWaitImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotifyWait_Unpriv \n" + " MPU_xTaskGenericNotifyWait_Priv: \n" + " b MPU_xTaskGenericNotifyWaitImpl \n" + " MPU_xTaskGenericNotifyWait_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGenericNotifyTakeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGenericNotifyTake_Unpriv \n" + " MPU_ulTaskGenericNotifyTake_Priv: \n" + " b MPU_ulTaskGenericNotifyTakeImpl \n" + " MPU_ulTaskGenericNotifyTake_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyStateClearImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotifyStateClear_Unpriv \n" + " MPU_xTaskGenericNotifyStateClear_Priv: \n" + " b MPU_xTaskGenericNotifyStateClearImpl \n" + " MPU_xTaskGenericNotifyStateClear_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGenericNotifyValueClearImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGenericNotifyValueClear_Unpriv \n" + " MPU_ulTaskGenericNotifyValueClear_Priv: \n" + " b MPU_ulTaskGenericNotifyValueClearImpl \n" + " MPU_ulTaskGenericNotifyValueClear_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGenericSendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGenericSend_Unpriv \n" + " MPU_xQueueGenericSend_Priv: \n" + " b MPU_xQueueGenericSendImpl \n" + " MPU_xQueueGenericSend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxQueueMessagesWaitingImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxQueueMessagesWaiting_Unpriv \n" + " MPU_uxQueueMessagesWaiting_Priv: \n" + " b MPU_uxQueueMessagesWaitingImpl \n" + " MPU_uxQueueMessagesWaiting_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxQueueSpacesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxQueueSpacesAvailable_Unpriv \n" + " MPU_uxQueueSpacesAvailable_Priv: \n" + " b MPU_uxQueueSpacesAvailableImpl \n" + " MPU_uxQueueSpacesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueReceiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueReceive_Unpriv \n" + " MPU_xQueueReceive_Priv: \n" + " b MPU_xQueueReceiveImpl \n" + " MPU_xQueueReceive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueuePeekImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueuePeek_Unpriv \n" + " MPU_xQueuePeek_Priv: \n" + " b MPU_xQueuePeekImpl \n" + " MPU_xQueuePeek_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueSemaphoreTakeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueSemaphoreTake_Unpriv \n" + " MPU_xQueueSemaphoreTake_Priv: \n" + " b MPU_xQueueSemaphoreTakeImpl \n" + " MPU_xQueueSemaphoreTake_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) + + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGetMutexHolderImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGetMutexHolder_Unpriv \n" + " MPU_xQueueGetMutexHolder_Priv: \n" + " b MPU_xQueueGetMutexHolderImpl \n" + " MPU_xQueueGetMutexHolder_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory" + ); + } + + #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueTakeMutexRecursiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueTakeMutexRecursive_Unpriv \n" + " MPU_xQueueTakeMutexRecursive_Priv: \n" + " b MPU_xQueueTakeMutexRecursiveImpl \n" + " MPU_xQueueTakeMutexRecursive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory" + ); + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGiveMutexRecursiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGiveMutexRecursive_Unpriv \n" + " MPU_xQueueGiveMutexRecursive_Priv: \n" + " b MPU_xQueueGiveMutexRecursiveImpl \n" + " MPU_xQueueGiveMutexRecursive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory" + ); + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueSelectFromSetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueSelectFromSet_Unpriv \n" + " MPU_xQueueSelectFromSet_Priv: \n" + " b MPU_xQueueSelectFromSetImpl \n" + " MPU_xQueueSelectFromSet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory" + ); + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueAddToSetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueAddToSet_Unpriv \n" + " MPU_xQueueAddToSet_Priv: \n" + " b MPU_xQueueAddToSetImpl \n" + " MPU_xQueueAddToSet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory" + ); + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vQueueAddToRegistryImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vQueueAddToRegistry_Unpriv \n" + " MPU_vQueueAddToRegistry_Priv: \n" + " b MPU_vQueueAddToRegistryImpl \n" + " MPU_vQueueAddToRegistry_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vQueueUnregisterQueueImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vQueueUnregisterQueue_Unpriv \n" + " MPU_vQueueUnregisterQueue_Priv: \n" + " b MPU_vQueueUnregisterQueueImpl \n" + " MPU_vQueueUnregisterQueue_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pcQueueGetNameImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pcQueueGetName_Unpriv \n" + " MPU_pcQueueGetName_Priv: \n" + " b MPU_pcQueueGetNameImpl \n" + " MPU_pcQueueGetName_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pvTimerGetTimerIDImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pvTimerGetTimerID_Unpriv \n" + " MPU_pvTimerGetTimerID_Priv: \n" + " b MPU_pvTimerGetTimerIDImpl \n" + " MPU_pvTimerGetTimerID_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTimerSetTimerIDImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTimerSetTimerID_Unpriv \n" + " MPU_vTimerSetTimerID_Priv: \n" + " b MPU_vTimerSetTimerIDImpl \n" + " MPU_vTimerSetTimerID_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerIsTimerActiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerIsTimerActive_Unpriv \n" + " MPU_xTimerIsTimerActive_Priv: \n" + " b MPU_xTimerIsTimerActiveImpl \n" + " MPU_xTimerIsTimerActive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv \n" + " MPU_xTimerGetTimerDaemonTaskHandle_Priv: \n" + " b MPU_xTimerGetTimerDaemonTaskHandleImpl \n" + " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGenericCommandFromTaskImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGenericCommandFromTask_Unpriv \n" + " MPU_xTimerGenericCommandFromTask_Priv: \n" + " b MPU_xTimerGenericCommandFromTaskImpl \n" + " MPU_xTimerGenericCommandFromTask_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pcTimerGetNameImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pcTimerGetName_Unpriv \n" + " MPU_pcTimerGetName_Priv: \n" + " b MPU_pcTimerGetNameImpl \n" + " MPU_pcTimerGetName_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTimerSetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTimerSetReloadMode_Unpriv \n" + " MPU_vTimerSetReloadMode_Priv: \n" + " b MPU_vTimerSetReloadModeImpl \n" + " MPU_vTimerSetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetReloadMode_Unpriv \n" + " MPU_xTimerGetReloadMode_Priv: \n" + " b MPU_xTimerGetReloadModeImpl \n" + " MPU_xTimerGetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTimerGetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTimerGetReloadMode_Unpriv \n" + " MPU_uxTimerGetReloadMode_Priv: \n" + " b MPU_uxTimerGetReloadModeImpl \n" + " MPU_uxTimerGetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetPeriodImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetPeriod_Unpriv \n" + " MPU_xTimerGetPeriod_Priv: \n" + " b MPU_xTimerGetPeriodImpl \n" + " MPU_xTimerGetPeriod_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetExpiryTimeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetExpiryTime_Unpriv \n" + " MPU_xTimerGetExpiryTime_Priv: \n" + " b MPU_xTimerGetExpiryTimeImpl \n" + " MPU_xTimerGetExpiryTime_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupWaitBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupWaitBits_Unpriv \n" + " MPU_xEventGroupWaitBits_Priv: \n" + " b MPU_xEventGroupWaitBitsImpl \n" + " MPU_xEventGroupWaitBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupClearBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupClearBits_Unpriv \n" + " MPU_xEventGroupClearBits_Priv: \n" + " b MPU_xEventGroupClearBitsImpl \n" + " MPU_xEventGroupClearBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupSetBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupSetBits_Unpriv \n" + " MPU_xEventGroupSetBits_Priv: \n" + " b MPU_xEventGroupSetBitsImpl \n" + " MPU_xEventGroupSetBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ + +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupSyncImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupSync_Unpriv \n" + " MPU_xEventGroupSync_Priv: \n" + " b MPU_xEventGroupSyncImpl \n" + " MPU_xEventGroupSync_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxEventGroupGetNumberImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxEventGroupGetNumber_Unpriv \n" + " MPU_uxEventGroupGetNumber_Priv: \n" + " b MPU_uxEventGroupGetNumberImpl \n" + " MPU_uxEventGroupGetNumber_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory" + ); + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vEventGroupSetNumberImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vEventGroupSetNumber_Unpriv \n" + " MPU_vEventGroupSetNumber_Priv: \n" + " b MPU_vEventGroupSetNumberImpl \n" + " MPU_vEventGroupSetNumber_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory" + ); + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferSend_Unpriv \n" + " MPU_xStreamBufferSend_Priv: \n" + " b MPU_xStreamBufferSendImpl \n" + " MPU_xStreamBufferSend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferReceiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferReceive_Unpriv \n" + " MPU_xStreamBufferReceive_Priv: \n" + " b MPU_xStreamBufferReceiveImpl \n" + " MPU_xStreamBufferReceive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferIsFullImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferIsFull_Unpriv \n" + " MPU_xStreamBufferIsFull_Priv: \n" + " b MPU_xStreamBufferIsFullImpl \n" + " MPU_xStreamBufferIsFull_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferIsEmptyImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferIsEmpty_Unpriv \n" + " MPU_xStreamBufferIsEmpty_Priv: \n" + " b MPU_xStreamBufferIsEmptyImpl \n" + " MPU_xStreamBufferIsEmpty_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSpacesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferSpacesAvailable_Unpriv \n" + " MPU_xStreamBufferSpacesAvailable_Priv: \n" + " b MPU_xStreamBufferSpacesAvailableImpl \n" + " MPU_xStreamBufferSpacesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferBytesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferBytesAvailable_Unpriv \n" + " MPU_xStreamBufferBytesAvailable_Priv: \n" + " b MPU_xStreamBufferBytesAvailableImpl \n" + " MPU_xStreamBufferBytesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSetTriggerLevelImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferSetTriggerLevel_Unpriv \n" + " MPU_xStreamBufferSetTriggerLevel_Priv: \n" + " b MPU_xStreamBufferSetTriggerLevelImpl \n" + " MPU_xStreamBufferSetTriggerLevel_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferNextMessageLengthBytesImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv \n" + " MPU_xStreamBufferNextMessageLengthBytes_Priv: \n" + " b MPU_xStreamBufferNextMessageLengthBytesImpl \n" + " MPU_xStreamBufferNextMessageLengthBytes_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ diff --git a/portable/GCC/ARM_CM55/non_secure/port.c b/portable/GCC/ARM_CM55/non_secure/port.c new file mode 100644 index 000000000..76d2b2445 --- /dev/null +++ b/portable/GCC/ARM_CM55/non_secure/port.c @@ -0,0 +1,2280 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024-2025 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU includes. */ +#include "mpu_wrappers.h" +#include "mpu_syscall_numbers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration settings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to check the validity of an interrupt priority. + */ +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) ) +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used during system call enter and exit. + */ +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Offsets in the stack to the parameters when inside the SVC handler. + */ +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +#if ( portARMV8M_MINOR_VERSION >= 1 ) + + /* Enable Privileged eXecute Never MPU attribute for the selected memory + * region. */ + #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL ) +#endif /* portARMV8M_MINOR_VERSION >= 1 */ + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Extract first address of the MPU region as encoded in the + * RBAR (Region Base Address Register) value. */ +#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \ + ( ( rbar ) & portMPU_RBAR_ADDRESS_MASK ) + +/* Extract last address of the MPU region as encoded in the + * RLAR (Region Limit Address Register) value. */ +#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \ + ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK ) + +/* Does addr lies within [start, end] address range? */ +#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \ + ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) ) + +/* Is the access request satisfied by the available permissions? */ +#define portIS_AUTHORIZED( accessRequest, permissions ) \ + ( ( ( permissions ) & ( accessRequest ) ) == accessRequest ) + +/* Max value that fits in a uint32_t type. */ +#define portUINT32_MAX ( ~( ( uint32_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. + */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 + +/** + * @brief Constants required to check and configure PACBTI security feature implementation. + */ +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) ) + + #define portCONTROL_UPAC_EN ( 1UL << 7UL ) + #define portCONTROL_PAC_EN ( 1UL << 6UL ) + #define portCONTROL_UBTI_EN ( 1UL << 5UL ) + #define portCONTROL_BTI_EN ( 1UL << 4UL ) + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Extract MPU region's access permissions from the Region Base Address + * Register (RBAR) value. + * + * @param ulRBARValue RBAR value for the MPU region. + * + * @return uint32_t Access permissions. + */ + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + + /** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + /** + * @brief Configures PACBTI features. + * + * This function configures the Pointer Authentication, and Branch Target + * Identification security features as per the user configuration. It returns + * the value of the special purpose CONTROL register accordingly, and optionally + * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M + * architecture based) target supports PACBTI security feature. + * + * @param xWriteControlRegister Used to control whether the special purpose + * CONTROL register should be updated or not. + * + * @return CONTROL register value according to the configured PACBTI option. + */ + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the system call stack so that upon returning from + * SVC, the system call stack is used. + * + * @param pulTaskStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + * @param ucSystemCallNumber The system call number of the system call. + */ + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Raise SVC for exiting from a system call. + */ + void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief This variable is set to pdTRUE when the scheduler is started. + */ + PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + + /** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +/** + * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + /** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + + /** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + + /** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the cpsid instruction + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessPermissions = 0; + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_ONLY ) + { + ulAccessPermissions = tskMPU_READ_PERMISSION; + } + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_WRITE ) + { + ulAccessPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION ); + } + + return ulAccessPermissions; + } + +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } + +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ portOFFSET_TO_PC ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ]; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulSystemCallStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the system call section (i.e. application is + * not raising SVC directly). + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as + * it is non-NULL only during the execution of a system call (i.e. + * between system call enter and exit). + * 3. System call is not for a kernel API disabled by the configuration + * in FreeRTOSConfig.h. + * 4. We do not need to check that ucSystemCallNumber is within range + * because the assembly SVC handler checks that before calling + * this function. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) && + ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) ) + { + pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the system call stack for the stack frame. */ + pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulSystemCallStack[ i ] = pulTaskStack[ i ]; + } + + /* Store the value of the Link Register before the SVC was raised. + * It contains the address of the caller of the System Call entry + * point (i.e. the caller of the MPU_). We need to restore it + * when we exit from the system call. */ + pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; + + /* Store the value of the PSPLIM register before the SVC was raised. + * We need to restore it when we exit from the system call. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* Use the pulSystemCallStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif + + /* Start executing the system call upon returning from this handler. */ + pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; + + /* Raise a request to exit from the system call upon finishing the + * system call. */ + pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; + + /* Remember the location where we should copy the stack frame when we exit from + * the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize; + + /* Record if the hardware used padding to force the stack pointer + * to be double word aligned. */ + if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK ) + { + pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG; + } + else + { + pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG ); + } + + /* We ensure in pxPortInitialiseStack that the system call stack is + * double word aligned and therefore, there is no need of padding. + * Clear the bit[9] of stacked xPSR. */ + pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + + /* Raise the privilege for the duration of the system call. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " bics r0, r1 \n" /* Clear nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */ + { + __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulTaskStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the privileged code (i.e. application is not + * raising SVC directly). This SVC is only raised from + * vRequestSystemCallExit which is in the privileged code section. + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL - + * this means that we previously entered a system call and the + * application is not attempting to exit without entering a system + * call. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) ) + { + pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the task stack for the stack frame. */ + pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulTaskStack[ i ] = pulSystemCallStack[ i ]; + } + + /* Use the pulTaskStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) ); + + /* Return to the caller of the System Call entry point (i.e. the + * caller of the MPU_). */ + pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + /* Ensure that LR has a valid value.*/ + pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + + /* Restore the PSPLIM register to what it was at the time of + * system call entry. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* If the hardware used padding to force the stack pointer + * to be double word aligned, set the stacked xPSR bit[9], + * otherwise clear it. */ + if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG ) + { + pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK; + } + else + { + pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + } + + /* This is not NULL only for the duration of the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; + + /* Drop the privilege before returning to the thread mode. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " orrs r0, r1 \n" /* Set nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xTaskIsPrivileged = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xTaskIsPrivileged = pdTRUE; + } + + return xTaskIsPrivileged; + } + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged, + xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulIndex = 0; + uint32_t ulControl = 0x0; + + xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ + ulIndex++; + + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + ulIndex++; + + #if ( configENABLE_TRUSTZONE == 1 ) + { + xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */ + ulIndex++; + } + #endif /* configENABLE_TRUSTZONE */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + ulIndex++; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Check PACBTI security feature configuration before pushing the + * CONTROL register's value on task's TCB. */ + ulControl = prvConfigurePACBTI( pdFALSE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + if( xRunPrivileged == pdTRUE ) + { + xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + else + { + xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG ); + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ + ulIndex++; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + { + /* Ensure that the system call stack is double word aligned. */ + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) + + ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + /* This is not NULL only for the duration of a system call. */ + xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL; + } + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ]; + ulIndex++; + } + } + #endif /* configENABLE_PAC */ + + return &( xMPUSettings->ulContext[ ulIndex ] ); + } + +#else /* configENABLE_MPU */ + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ + { + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + pxTopOfStack--; + *pxTopOfStack = ulTaskPacKey[ i ]; + } + } + #endif /* configENABLE_PAC */ + + return pxTopOfStack; + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Set the CONTROL register value based on PACBTI security feature + * configuration before starting the first task. */ + ( void ) prvConfigurePACBTI( pdTRUE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + { + xSchedulerRunning = pdTRUE; + } + #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + configSTACK_DEPTH_TYPE uxStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( uxStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* PXN. */ + #if ( portARMV8M_MINOR_VERSION >= 1 ) + { + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ); + } + } + #endif /* portARMV8M_MINOR_VERSION >= 1 */ + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, + uint32_t ulBufferLength, + uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */ + + { + uint32_t i, ulBufferStartAddress, ulBufferEndAddress; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE ) + { + ulBufferStartAddress = ( uint32_t ) pvBuffer; + ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL ); + + for( i = 0; i < portTOTAL_NUM_REGIONS; i++ ) + { + /* Is the MPU region enabled? */ + if( ( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR & portMPU_RLAR_REGION_ENABLE ) == portMPU_RLAR_REGION_ENABLE ) + { + if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_AUTHORIZED( ulAccessRequested, + prvGetRegionAccessPermissions( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ) ) ) + { + xAccessGranted = pdTRUE; + break; + } + } + } + } + } + + return xAccessGranted; + } + +#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings; + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else + { + xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 ) + { + xAccessGranted = pdTRUE; + } + } + } + + return xAccessGranted; + } + + #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + ( void ) lInternalIndexOfKernelObject; + + /* If Access Control List feature is not used, all the tasks have + * access to all the kernel objects. */ + return pdTRUE; + } + + #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + { + uint32_t ulControl = 0x0; + + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); + + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; + + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM55/non_secure/portasm.c b/portable/GCC/ARM_CM55/non_secure/portasm.c new file mode 100644 index 000000000..0ebbe48a4 --- /dev/null +++ b/portable/GCC/ARM_CM55/non_secure/portasm.c @@ -0,0 +1,621 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION + * is defined correctly and privileged functions are placed in correct sections. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Portasm includes. */ +#include "portasm.h" + +/* System call numbers includes. */ +#include "mpu_syscall_numbers.h" + +/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the + * header files. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#if ( configENABLE_MPU == 1 ) + + void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " program_mpu_first_task: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r3] \n" /* r0 = pxCurrentTCB. */ + " \n" + " dmb \n" /* Complete outstanding transfers before disabling MPU. */ + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + " str r2, [r1] \n" /* Disable MPU. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */ + " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r1, [r2] \n" /* Program MAIR0. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " \n" + " movs r3, #4 \n" /* r3 = 4. */ + " str r3, [r1] \n" /* Program RNR = 4. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + " \n" + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " orr r2, #1 \n" /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */ + " str r2, [r1] \n" /* Enable MPU. */ + " dsb \n" /* Force memory writes before continuing. */ + " \n" + " restore_context_first_task: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* r1 = pxCurrentTCB.*/ + " ldr r2, [r1] \n" /* r2 = Location of saved context in TCB. */ + " \n" + " restore_special_regs_first_task: \n" + #if ( configENABLE_PAC == 1 ) + " ldmdb r2!, {r3-r6} \n" /* Read task's dedicated PAC key from the task's context. */ + " msr PAC_KEY_P_0, r3 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_1, r4 \n" + " msr PAC_KEY_P_2, r5 \n" + " msr PAC_KEY_P_3, r6 \n" + " clrm {r3-r6} \n" /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + " ldmdb r2!, {r0, r3-r5, lr} \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */ + " msr psp, r3 \n" + " msr psplim, r4 \n" + " msr control, r5 \n" + " ldr r4, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " str r0, [r4] \n" /* Restore xSecureContext. */ + " \n" + " restore_general_regs_first_task: \n" + " ldmdb r2!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */ + " stmia r3!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */ + " ldmdb r2!, {r4-r11} \n" /* r4-r11 restored. */ + " \n" + " restore_context_done_first_task: \n" + " str r2, [r1] \n" /* Save the location where the context should be saved next as the first member of TCB. */ + " mov r0, #0 \n" + " msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */ + " bx lr \n" + ); + } + +#else /* configENABLE_MPU */ + + void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r3, [r2] \n" /* Read pxCurrentTCB. */ + " ldr r0, [r3] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + " \n" + #if ( configENABLE_PAC == 1 ) + " ldmia r0!, {r1-r4} \n" /* Read task's dedicated PAC key from stack. */ + " msr PAC_KEY_P_3, r1 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_2, r2 \n" + " msr PAC_KEY_P_1, r3 \n" + " msr PAC_KEY_P_0, r4 \n" + " clrm {r1-r4} \n" /* Clear r1-r4. */ + #endif /* configENABLE_PAC */ + " \n" + " ldm r0!, {r1-r3} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */ + " ldr r4, =xSecureContext \n" + " str r1, [r4] \n" /* Set xSecureContext to this task's value for the same. */ + " msr psplim, r2 \n" /* Set this task's PSPLIM value. */ + " mrs r1, control \n" /* Obtain current control register value. */ + " orrs r1, r1, #2 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */ + " msr control, r1 \n" /* Write back the new control register value. */ + " adds r0, #32 \n" /* Discard everything up to r0. */ + " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */ + " isb \n" + " mov r0, #0 \n" + " msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */ + " bx r3 \n" /* Finally, branch to EXC_RETURN. */ + ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* r0 = CONTROL. */ + " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + " ite ne \n" + " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + " bx lr \n" /* Return. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* Read the CONTROL register. */ + " bic r0, #1 \n" /* Clear the bit 0. */ + " msr control, r0 \n" /* Write back the new CONTROL value. */ + " bx lr \n" /* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vResetPrivilege( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* r0 = CONTROL. */ + " orr r0, #1 \n" /* r0 = r0 | 1. */ + " msr control, r0 \n" /* CONTROL = r0. */ + " bx lr \n" /* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r0, =0xe000ed08 \n" /* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */ + " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */ + " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */ + " cpsie i \n" /* Globally enable interrupts. */ + " cpsie f \n" + " dsb \n" + " isb \n" + " svc %0 \n" /* System call to start the first task. */ + " nop \n" + ::"i" ( portSVC_START_SCHEDULER ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, basepri \n" /* r0 = basepri. Return original basepri value. */ + " mov r1, %0 \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r1 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bx lr \n" /* Return. */ + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " msr basepri, r0 \n" /* basepri = ulMask. */ + " dsb \n" + " isb \n" + " bx lr \n" /* Return. */ + ::: "memory" + ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern SecureContext_SaveContext \n" + " .extern SecureContext_LoadContext \n" + " \n" + " ldr r3, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " ldr r0, [r3] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */ + " ldr r2, [r1] \n" /* r2 = Location in TCB where the context should be saved. */ + " \n" + " cbz r0, save_ns_context \n" /* No secure context to save. */ + " save_s_context: \n" + " push {r0-r2, lr} \n" + " bl SecureContext_SaveContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r0-r2, lr} \n" + " \n" + " save_ns_context: \n" + " mov r3, lr \n" /* r3 = LR (EXC_RETURN). */ + " lsls r3, r3, #25 \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bmi save_special_regs \n" /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + " \n" + " save_general_regs: \n" + " mrs r3, psp \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " add r3, r3, #0x20 \n" /* Move r3 to location where s0 is saved. */ + " tst lr, #0x10 \n" + " ittt eq \n" + " vstmiaeq r2!, {s16-s31} \n" /* Store s16-s31. */ + " vldmiaeq r3, {s0-s16} \n" /* Copy hardware saved FP context into s0-s16. */ + " vstmiaeq r2!, {s0-s16} \n" /* Store hardware saved FP context. */ + " sub r3, r3, #0x20 \n" /* Set r3 back to the location of hardware saved context. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " stmia r2!, {r4-r11} \n" /* Store r4-r11. */ + " ldmia r3, {r4-r11} \n" /* Copy the hardware saved context into r4-r11. */ + " stmia r2!, {r4-r11} \n" /* Store the hardware saved context. */ + " \n" + " save_special_regs: \n" + " mrs r3, psp \n" /* r3 = PSP. */ + " mrs r4, psplim \n" /* r4 = PSPLIM. */ + " mrs r5, control \n" /* r5 = CONTROL. */ + " stmia r2!, {r0, r3-r5, lr} \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ + #if ( configENABLE_PAC == 1 ) + " mrs r3, PAC_KEY_P_0 \n" /* Read task's dedicated PAC key from the PAC key registers. */ + " mrs r4, PAC_KEY_P_1 \n" + " mrs r5, PAC_KEY_P_2 \n" + " mrs r6, PAC_KEY_P_3 \n" + " stmia r2!, {r3-r6} \n" /* Store the task's dedicated PAC key on the task's context. */ + " clrm {r3-r6} \n" /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + " str r2, [r1] \n" /* Save the location from where the context should be restored as the first member of TCB. */ + " \n" + " select_next_task: \n" + " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bl vTaskSwitchContext \n" + " mov r0, #0 \n" /* r0 = 0. */ + " msr basepri, r0 \n" /* Enable interrupts. */ + " \n" + " program_mpu: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r3] \n" /* r0 = pxCurrentTCB.*/ + " \n" + " dmb \n" /* Complete outstanding transfers before disabling MPU. */ + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + " str r2, [r1] \n" /* Disable MPU. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */ + " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r1, [r2] \n" /* Program MAIR0. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " \n" + " movs r3, #4 \n" /* r3 = 4. */ + " str r3, [r1] \n" /* Program RNR = 4. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + " \n" + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " orr r2, #1 \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */ + " str r2, [r1] \n" /* Enable MPU. */ + " dsb \n" /* Force memory writes before continuing. */ + " \n" + " restore_context: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* r1 = pxCurrentTCB.*/ + " ldr r2, [r1] \n" /* r2 = Location of saved context in TCB. */ + " \n" + " restore_special_regs: \n" + #if ( configENABLE_PAC == 1 ) + " ldmdb r2!, {r3-r6} \n" /* Read task's dedicated PAC key from the task's context. */ + " msr PAC_KEY_P_0, r3 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_1, r4 \n" + " msr PAC_KEY_P_2, r5 \n" + " msr PAC_KEY_P_3, r6 \n" + " clrm {r3-r6} \n" /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + " ldmdb r2!, {r0, r3-r5, lr} \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */ + " msr psp, r3 \n" + " msr psplim, r4 \n" + " msr control, r5 \n" + " ldr r4, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " str r0, [r4] \n" /* Restore xSecureContext. */ + " cbz r0, restore_ns_context \n" /* No secure context to restore. */ + " \n" + " restore_s_context: \n" + " push {r1-r3, lr} \n" + " bl SecureContext_LoadContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r1-r3, lr} \n" + " \n" + " restore_ns_context: \n" + " mov r0, lr \n" /* r0 = LR (EXC_RETURN). */ + " lsls r0, r0, #25 \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bmi restore_context_done \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + " \n" + " restore_general_regs: \n" + " ldmdb r2!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */ + " stmia r3!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */ + " ldmdb r2!, {r4-r11} \n" /* r4-r11 restored. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" + " ittt eq \n" + " vldmdbeq r2!, {s0-s16} \n" /* s0-s16 contain hardware saved FP context. */ + " vstmiaeq r3!, {s0-s16} \n" /* Copy hardware saved FP context on the task stack. */ + " vldmdbeq r2!, {s16-s31} \n" /* Restore s16-s31. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + " restore_context_done: \n" + " str r2, [r1] \n" /* Save the location where the context should be saved next as the first member of TCB. */ + " bx lr \n" + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); + } + +#else /* configENABLE_MPU */ + + void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern SecureContext_SaveContext \n" + " .extern SecureContext_LoadContext \n" + " \n" + " ldr r3, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " ldr r0, [r3] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */ + " mrs r2, psp \n" /* Read PSP in r2. */ + " \n" + " cbz r0, save_ns_context \n" /* No secure context to save. */ + " save_s_context: \n" + " push {r0-r2, lr} \n" + " bl SecureContext_SaveContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r0-r2, lr} \n" + " \n" + " save_ns_context: \n" + " mov r3, lr \n" /* r3 = LR (EXC_RETURN). */ + " lsls r3, r3, #25 \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bmi save_special_regs \n" /* If r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used. */ + " \n" + " save_general_regs: \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vstmdbeq r2!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " stmdb r2!, {r4-r11} \n" /* Store the registers that are not saved automatically. */ + " \n" + " save_special_regs: \n" + " mrs r3, psplim \n" /* r3 = PSPLIM. */ + " stmdb r2!, {r0, r3, lr} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */ + #if ( configENABLE_PAC == 1 ) + " mrs r3, PAC_KEY_P_3 \n" /* Read task's dedicated PAC key from the PAC key registers. */ + " mrs r4, PAC_KEY_P_2 \n" + " mrs r5, PAC_KEY_P_1 \n" + " mrs r6, PAC_KEY_P_0 \n" + " stmdb r2!, {r3-r6} \n" /* Store the task's dedicated PAC key on the stack. */ + " clrm {r3-r6} \n" /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + " \n" + " str r2, [r1] \n" /* Save the new top of stack in TCB. */ + " \n" + " select_next_task: \n" + " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bl vTaskSwitchContext \n" + " mov r0, #0 \n" /* r0 = 0. */ + " msr basepri, r0 \n" /* Enable interrupts. */ + " \n" + " restore_context: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* Read pxCurrentTCB. */ + " ldr r2, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */ + " \n" + " restore_special_regs: \n" + #if ( configENABLE_PAC == 1 ) + " ldmia r2!, {r3-r6} \n" /* Read task's dedicated PAC key from stack. */ + " msr PAC_KEY_P_3, r3 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_2, r4 \n" + " msr PAC_KEY_P_1, r5 \n" + " msr PAC_KEY_P_0, r6 \n" + " clrm {r3-r6} \n" /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + " ldmia r2!, {r0, r3, lr} \n" /* Read from stack - r0 = xSecureContext, r3 = PSPLIM and LR restored. */ + " msr psplim, r3 \n" /* Restore the PSPLIM register value for the task. */ + " ldr r3, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " str r0, [r3] \n" /* Restore the task's xSecureContext. */ + " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */ + " \n" + " restore_s_context: \n" + " push {r1-r3, lr} \n" + " bl SecureContext_LoadContext \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r1-r3, lr} \n" + " \n" + " restore_ns_context: \n" + " mov r0, lr \n" /* r0 = LR (EXC_RETURN). */ + " lsls r0, r0, #25 \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bmi restore_context_done \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + " \n" + " restore_general_regs: \n" + " ldmia r2!, {r4-r11} \n" /* Restore the registers that are not automatically restored. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vldmiaeq r2!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + " restore_context_done: \n" + " msr psp, r2 \n" /* Remember the new top of stack for the task. */ + " bx lr \n" + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + ".syntax unified \n" + ".extern vPortSVCHandler_C \n" + ".extern vSystemCallEnter \n" + ".extern vSystemCallExit \n" + " \n" + "tst lr, #4 \n" + "ite eq \n" + "mrseq r0, msp \n" + "mrsne r0, psp \n" + " \n" + "ldr r1, [r0, #24] \n" + "ldrb r2, [r1, #-2] \n" + "cmp r2, %0 \n" + "blt syscall_enter \n" + "cmp r2, %1 \n" + "beq syscall_exit \n" + "b vPortSVCHandler_C \n" + " \n" + "syscall_enter: \n" + " mov r1, lr \n" + " b vSystemCallEnter \n" + " \n" + "syscall_exit: \n" + " mov r1, lr \n" + " b vSystemCallExit \n" + " \n" + : /* No outputs. */ + : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT ) + : "r0", "r1", "r2", "memory" + ); + } + +#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " tst lr, #4 \n" + " ite eq \n" + " mrseq r0, msp \n" + " mrsne r0, psp \n" + " ldr r1, =vPortSVCHandler_C \n" + " bx r1 \n" + ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " svc %0 \n" /* Secure context is allocated in the supervisor call. */ + " bx lr \n" /* Return. */ + ::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, [r0] \n" /* The first item in the TCB is the top of the stack. */ + " ldr r1, [r2] \n" /* The first item on the stack is the task's xSecureContext. */ + " cmp r1, #0 \n" /* Raise svc if task's xSecureContext is not NULL. */ + " it ne \n" + " svcne %0 \n" /* Secure context is freed in the supervisor call. */ + " bx lr \n" /* Return. */ + ::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory" + ); +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM55/non_secure/portasm.h b/portable/GCC/ARM_CM55/non_secure/portasm.h new file mode 100644 index 000000000..b7021b024 --- /dev/null +++ b/portable/GCC/ARM_CM55/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kernel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/portable/GCC/ARM_CM55/non_secure/portmacro.h b/portable/GCC/ARM_CM55/non_secure/portmacro.h new file mode 100644 index 000000000..c6a179c52 --- /dev/null +++ b/portable/GCC/ARM_CM55/non_secure/portmacro.h @@ -0,0 +1,79 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_MVE + #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE. +#endif /* configENABLE_MVE */ +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M55" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portARMV8M_MINOR_VERSION 1 +#define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h new file mode 100644 index 000000000..f373bcad5 --- /dev/null +++ b/portable/GCC/ARM_CM55/non_secure/portmacrocommon.h @@ -0,0 +1,582 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACROCOMMON_H +#define PORTMACROCOMMON_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. +#endif /* configENABLE_FPU */ + +#ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. +#endif /* configENABLE_MPU */ + +#ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. +#endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() +#define portINLINE __inline +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif +#define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ +extern BaseType_t xPortIsInsideInterrupt( void ); + +extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + +extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; +extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + +extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; +extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + +#if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_PAC == 1 ) + + /** + * @brief Generates 128-bit task's random PAC key. + * + * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be + * filled with a 128-bit random number. + */ + void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); + +#endif /* configENABLE_PAC */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ +#if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) +#else + #define portPRIVILEGE_BIT ( 0x0UL ) +#endif /* configENABLE_MPU */ + +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ +#define portPRIVILEGED_FLASH_REGION ( 0UL ) +#define portUNPRIVILEGED_FLASH_REGION ( 1UL ) +#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) +#define portPRIVILEGED_RAM_REGION ( 3UL ) +#define portSTACK_REGION ( 4UL ) +#define portFIRST_CONFIGURABLE_REGION ( 5UL ) +#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) +#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) +#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ +#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ +#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ +#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ +#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ +#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ +#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ +#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) +#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) +#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + +#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) +#define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) +#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) +#define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + +#define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + #ifndef configSYSTEM_CALL_STACK_SIZE + #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. + #endif + + /** + * @brief System call stack. + */ + typedef struct SYSTEM_CALL_STACK_INFO + { + uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; + uint32_t * pulSystemCallStack; + uint32_t * pulSystemCallStackLimit; + uint32_t * pulTaskStack; + uint32_t ulLinkRegisterAtSystemCallEntry; + uint32_t ulStackLimitRegisterAtSystemCallEntry; + } xSYSTEM_CALL_STACK_INFO; + + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + /** + * @brief MPU settings as stored in the TCB. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><-----------><----> + * 16 17 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 71 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 17 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 55 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | | | PC, xPSR | EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><-----------><----> + * 16 17 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 70 + + #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + /* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 17 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 54 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+------------------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +----------+-----------------+------------------------------+------------+-----+ + * + * <---------><----------------><------------------------------><-----------><----> + * 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 38 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+----------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | PC, xPSR | EXC_RETURN | | | + * +----------+-----------------+----------------------+------------+-----+ + * + * <---------><----------------><----------------------><-----------><----> + * 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 37 + + #else /* #if( configENABLE_TRUSTZONE == 1 ) */ + + /* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) + + /* Size of an Access Control List (ACL) entry in bits. */ + #define portACL_ENTRY_SIZE_BITS ( 32U ) + + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + uint32_t ulContext[ MAX_CONTEXT_SIZE ]; + uint32_t ulTaskFlags; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo; + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ]; + #endif + #endif + } xMPU_SETTINGS; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Validate priority of ISRs that are allowed to call FreeRTOS + * system calls. + */ +#if ( configASSERT_DEFINED == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif +#endif + +/** + * @brief SVC numbers. + */ +#define portSVC_ALLOCATE_SECURE_CONTEXT 100 +#define portSVC_FREE_SECURE_CONTEXT 101 +#define portSVC_START_SCHEDULER 102 +#define portSVC_RAISE_PRIVILEGE 103 +#define portSVC_SYSTEM_CALL_EXIT 104 +#define portSVC_YIELD 105 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) +#endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() +#else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + extern BaseType_t xPortIsTaskPrivileged( void ); + +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACROCOMMON_H */ diff --git a/portable/GCC/ARM_CM55/secure/secure_context.c b/portable/GCC/ARM_CM55/secure/secure_context.c new file mode 100644 index 000000000..3aa335e63 --- /dev/null +++ b/portable/GCC/ARM_CM55/secure/secure_context.c @@ -0,0 +1,354 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Secure context includes. */ +#include "secure_context.h" + +/* Secure heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief CONTROL value for privileged tasks. + * + * Bit[0] - 0 --> Thread mode is privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_PRIVILEGED 0x02 + +/** + * @brief CONTROL value for un-privileged tasks. + * + * Bit[0] - 1 --> Thread mode is un-privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03 + +/** + * @brief Size of stack seal values in bytes. + */ +#define securecontextSTACK_SEAL_SIZE 8 + +/** + * @brief Stack seal value as recommended by ARM. + */ +#define securecontextSTACK_SEAL_VALUE 0xFEF5EDA5 + +/** + * @brief Maximum number of secure contexts. + */ +#ifndef secureconfigMAX_SECURE_CONTEXTS + #define secureconfigMAX_SECURE_CONTEXTS 8UL +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Pre-allocated array of secure contexts. + */ +SecureContext_t xSecureContexts[ secureconfigMAX_SECURE_CONTEXTS ]; +/*-----------------------------------------------------------*/ + +/** + * @brief Get a free secure context for a task from the secure context pool (xSecureContexts). + * + * This function ensures that only one secure context is allocated for a task. + * + * @param[in] pvTaskHandle The task handle for which the secure context is allocated. + * + * @return Index of a free secure context in the xSecureContexts array. + */ +static uint32_t ulGetSecureContext( void * pvTaskHandle ); + +/** + * @brief Return the secure context to the secure context pool (xSecureContexts). + * + * @param[in] ulSecureContextIndex Index of the context in the xSecureContexts array. + */ +static void vReturnSecureContext( uint32_t ulSecureContextIndex ); + +/* These are implemented in assembly. */ +extern void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ); +extern void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ); +/*-----------------------------------------------------------*/ + +static uint32_t ulGetSecureContext( void * pvTaskHandle ) +{ + /* Start with invalid index. */ + uint32_t i, ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + if( ( xSecureContexts[ i ].pucCurrentStackPointer == NULL ) && + ( xSecureContexts[ i ].pucStackLimit == NULL ) && + ( xSecureContexts[ i ].pucStackStart == NULL ) && + ( xSecureContexts[ i ].pvTaskHandle == NULL ) && + ( ulSecureContextIndex == secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = i; + } + else if( xSecureContexts[ i ].pvTaskHandle == pvTaskHandle ) + { + /* A task can only have one secure context. Do not allocate a second + * context for the same task. */ + ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + break; + } + } + + return ulSecureContextIndex; +} +/*-----------------------------------------------------------*/ + +static void vReturnSecureContext( uint32_t ulSecureContextIndex ) +{ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackStart = NULL; + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = NULL; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) +{ + uint32_t ulIPSR, i; + static uint32_t ulSecureContextsInitialized = 0; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ( ulIPSR != 0 ) && ( ulSecureContextsInitialized == 0 ) ) + { + /* Ensure to initialize secure contexts only once. */ + ulSecureContextsInitialized = 1; + + /* No stack for thread mode until a task's context is loaded. */ + secureportSET_PSPLIM( securecontextNO_STACK ); + secureportSET_PSP( securecontextNO_STACK ); + + /* Initialize all secure contexts. */ + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + xSecureContexts[ i ].pucCurrentStackPointer = NULL; + xSecureContexts[ i ].pucStackLimit = NULL; + xSecureContexts[ i ].pucStackStart = NULL; + xSecureContexts[ i ].pvTaskHandle = NULL; + } + + #if ( configENABLE_MPU == 1 ) + { + /* Configure thread mode to use PSP and to be unprivileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); + } + #else /* configENABLE_MPU */ + { + /* Configure thread mode to use PSP and to be privileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); + } + #endif /* configENABLE_MPU */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ) +#else /* configENABLE_MPU */ + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ) +#endif /* configENABLE_MPU */ +{ + uint8_t * pucStackMemory = NULL; + uint8_t * pucStackLimit; + uint32_t ulIPSR, ulSecureContextIndex; + SecureContextHandle_t xSecureContextHandle = securecontextINVALID_CONTEXT_ID; + + #if ( configENABLE_MPU == 1 ) + uint32_t * pulCurrentStackPointer = NULL; + #endif /* configENABLE_MPU */ + + /* Read the Interrupt Program Status Register (IPSR) and Process Stack Limit + * Register (PSPLIM) value. */ + secureportREAD_IPSR( ulIPSR ); + secureportREAD_PSPLIM( pucStackLimit ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. + * Also do nothing, if a secure context us already loaded. PSPLIM is set to + * securecontextNO_STACK when no secure context is loaded. */ + if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) ) + { + /* Obtain a free secure context. */ + ulSecureContextIndex = ulGetSecureContext( pvTaskHandle ); + + /* Were we able to get a free context? */ + if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS ) + { + /* Allocate the stack space. */ + pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + + if( pucStackMemory != NULL ) + { + /* Since stack grows down, the starting point will be the last + * location. Note that this location is next to the last + * allocated byte for stack (excluding the space for seal values) + * because the hardware decrements the stack pointer before + * writing i.e. if stack pointer is 0x2, a push operation will + * decrement the stack pointer to 0x1 and then write at 0x1. */ + xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize; + + /* Seal the created secure process stack. */ + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; + + /* The stack cannot go beyond this location. This value is + * programmed in the PSPLIM register on context switch.*/ + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = pucStackMemory; + + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle; + + #if ( configENABLE_MPU == 1 ) + { + /* Store the correct CONTROL value for the task on the stack. + * This value is programmed in the CONTROL register on + * context switch. */ + pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; + pulCurrentStackPointer--; + + if( ulIsTaskPrivileged ) + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; + } + else + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; + } + + /* Store the current stack pointer. This value is programmed in + * the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + } + #else /* configENABLE_MPU */ + { + /* Current SP is set to the starting of the stack. This + * value programmed in the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + } + #endif /* configENABLE_MPU */ + + /* Ensure to never return 0 as a valid context handle. */ + xSecureContextHandle = ulSecureContextIndex + 1UL; + } + } + } + + return xSecureContextHandle; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) +{ + uint32_t ulIPSR, ulSecureContextIndex; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* Only free if a valid context handle is passed. */ + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + /* Ensure that the secure context being deleted is associated with + * the task. */ + if( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) + { + /* Free the stack space. */ + vPortFree( xSecureContexts[ ulSecureContextIndex ].pucStackLimit ); + + /* Return the secure context back to the free secure contexts pool. */ + vReturnSecureContext( ulSecureContextIndex ); + } + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that no secure context is loaded and the task is loading it's + * own context. */ + if( ( pucStackLimit == securecontextNO_STACK ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_LoadContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that task's context is loaded and the task is saving it's own + * context. */ + if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_SaveContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM55/secure/secure_context.h b/portable/GCC/ARM_CM55/secure/secure_context.h new file mode 100644 index 000000000..e36a8e430 --- /dev/null +++ b/portable/GCC/ARM_CM55/secure/secure_context.h @@ -0,0 +1,138 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_CONTEXT_H__ +#define __SECURE_CONTEXT_H__ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" + +/** + * @brief PSP value when no secure context is loaded. + */ +#define securecontextNO_STACK 0x0 + +/** + * @brief Invalid context ID. + */ +#define securecontextINVALID_CONTEXT_ID 0UL +/*-----------------------------------------------------------*/ + +/** + * @brief Structure to represent a secure context. + * + * @note Since stack grows down, pucStackStart is the highest address while + * pucStackLimit is the first address of the allocated memory. + */ +typedef struct SecureContext +{ + uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */ + uint8_t * pucStackLimit; /**< Last location of the stack memory (PSPLIM). */ + uint8_t * pucStackStart; /**< First location of the stack memory. */ + void * pvTaskHandle; /**< Task handle of the task this context is associated with. */ +} SecureContext_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Opaque handle for a secure context. + */ +typedef uint32_t SecureContextHandle_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Initializes the secure context management system. + * + * PSP is set to NULL and therefore a task must allocate and load a context + * before calling any secure side function in the thread mode. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureContext_Init( void ); + +/** + * @brief Allocates a context on the secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] ulSecureStackSize Size of the stack to allocate on secure side. + * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise. + * + * @return Opaque context handle if context is successfully allocated, NULL + * otherwise. + */ +#if ( configENABLE_MPU == 1 ) + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ); +#else /* configENABLE_MPU */ + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ); +#endif /* configENABLE_MPU */ + +/** + * @brief Frees the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the + * context to be freed. + */ +void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); + +/** + * @brief Loads the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be loaded. + */ +void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); + +/** + * @brief Saves the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be saved. + */ +void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); + +#endif /* __SECURE_CONTEXT_H__ */ diff --git a/portable/GCC/ARM_CM55/secure/secure_context_port.c b/portable/GCC/ARM_CM55/secure/secure_context_port.c new file mode 100644 index 000000000..2d3d9439d --- /dev/null +++ b/portable/GCC/ARM_CM55/secure/secure_context_port.c @@ -0,0 +1,97 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Secure context includes. */ +#include "secure_context.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) ); +void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) ); + +void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) +{ + /* pxSecureContext value is in r0. */ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r1, ipsr \n" /* r1 = IPSR. */ + " cbz r1, load_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */ + " ldmia r0!, {r1, r2} \n" /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */ + " \n" + #if ( configENABLE_MPU == 1 ) + " ldmia r1!, {r3} \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */ + " msr control, r3 \n" /* CONTROL = r3. */ + #endif /* configENABLE_MPU */ + " \n" + " msr psplim, r2 \n" /* PSPLIM = r2. */ + " msr psp, r1 \n" /* PSP = r1. */ + " \n" + " load_ctx_therad_mode: \n" + " bx lr \n" + " \n" + ::: "r0", "r1", "r2" + ); +} +/*-----------------------------------------------------------*/ + +void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) +{ + /* pxSecureContext value is in r0. */ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r1, ipsr \n" /* r1 = IPSR. */ + " cbz r1, save_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */ + " mrs r1, psp \n" /* r1 = PSP. */ + " \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " vstmdb r1!, {s0} \n" /* Trigger the deferred stacking of FPU registers. */ + " vldmia r1!, {s0} \n" /* Nullify the effect of the previous statement. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + #if ( configENABLE_MPU == 1 ) + " mrs r2, control \n" /* r2 = CONTROL. */ + " stmdb r1!, {r2} \n" /* Store CONTROL value on the stack. */ + #endif /* configENABLE_MPU */ + " \n" + " str r1, [r0] \n" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */ + " movs r1, %0 \n" /* r1 = securecontextNO_STACK. */ + " msr psplim, r1 \n" /* PSPLIM = securecontextNO_STACK. */ + " msr psp, r1 \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */ + " \n" + " save_ctx_therad_mode: \n" + " bx lr \n" + " \n" + ::"i" ( securecontextNO_STACK ) : "r1", "memory" + ); +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM55/secure/secure_heap.c b/portable/GCC/ARM_CM55/secure/secure_heap.c new file mode 100644 index 000000000..896b53e2d --- /dev/null +++ b/portable/GCC/ARM_CM55/secure/secure_heap.c @@ -0,0 +1,485 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Configuration includes. */ +#include "FreeRTOSConfig.h" + +/* Secure context heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Total heap size. + */ +#ifndef secureconfigTOTAL_HEAP_SIZE + #define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) ) +#endif + +/* No test marker by default. */ +#ifndef mtCOVERAGE_TEST_MARKER + #define mtCOVERAGE_TEST_MARKER() +#endif + +/* No tracing by default. */ +#ifndef traceMALLOC + #define traceMALLOC( pvReturn, xWantedSize ) +#endif + +/* No tracing by default. */ +#ifndef traceFREE + #define traceFREE( pv, xBlockSize ) +#endif + +/* Block sizes must not get too small. */ +#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) ) + +/* Assumes 8bit bytes! */ +#define secureheapBITS_PER_BYTE ( ( size_t ) 8 ) + +/* Max value that fits in a size_t type. */ +#define secureheapSIZE_MAX ( ~( ( size_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define secureheapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) ) + +/* MSB of the xBlockSize member of an BlockLink_t structure is used to track + * the allocation status of a block. When MSB of the xBlockSize member of + * an BlockLink_t structure is set then the block belongs to the application. + * When the bit is free the block is still part of the free heap space. */ +#define secureheapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) ) +#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 ) +#define secureheapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 ) +#define secureheapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK ) +#define secureheapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK ) +/*-----------------------------------------------------------*/ + +/* Allocate the memory for the heap. */ +#if ( configAPPLICATION_ALLOCATED_HEAP == 1 ) + +/* The application writer has already defined the array used for the RTOS +* heap - probably so it can be placed in a special segment or address. */ + extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#else /* configAPPLICATION_ALLOCATED_HEAP */ + static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#endif /* configAPPLICATION_ALLOCATED_HEAP */ + +/** + * @brief The linked list structure. + * + * This is used to link free blocks in order of their memory address. + */ +typedef struct A_BLOCK_LINK +{ + struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */ + size_t xBlockSize; /**< The size of the free block. */ +} BlockLink_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Called automatically to setup the required heap structures the first + * time pvPortMalloc() is called. + */ +static void prvHeapInit( void ); + +/** + * @brief Inserts a block of memory that is being freed into the correct + * position in the list of free memory blocks. + * + * The block being freed will be merged with the block in front it and/or the + * block behind it if the memory blocks are adjacent to each other. + * + * @param[in] pxBlockToInsert The block being freed. + */ +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ); +/*-----------------------------------------------------------*/ + +/** + * @brief The size of the structure placed at the beginning of each allocated + * memory block must by correctly byte aligned. + */ +static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + +/** + * @brief Create a couple of list links to mark the start and end of the list. + */ +static BlockLink_t xStart; +static BlockLink_t * pxEnd = NULL; + +/** + * @brief Keeps track of the number of free bytes remaining, but says nothing + * about fragmentation. + */ +static size_t xFreeBytesRemaining = 0U; +static size_t xMinimumEverFreeBytesRemaining = 0U; + +/*-----------------------------------------------------------*/ + +static void prvHeapInit( void ) +{ + BlockLink_t * pxFirstFreeBlock; + uint8_t * pucAlignedHeap; + size_t uxAddress; + size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE; + + /* Ensure the heap starts on a correctly aligned boundary. */ + uxAddress = ( size_t ) ucHeap; + + if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 ) + { + uxAddress += ( secureportBYTE_ALIGNMENT - 1 ); + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; + } + + pucAlignedHeap = ( uint8_t * ) uxAddress; + + /* xStart is used to hold a pointer to the first item in the list of free + * blocks. The void cast is used to prevent compiler warnings. */ + xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; + xStart.xBlockSize = ( size_t ) 0; + + /* pxEnd is used to mark the end of the list of free blocks and is inserted + * at the end of the heap space. */ + uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; + uxAddress -= xHeapStructSize; + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + pxEnd = ( void * ) uxAddress; + pxEnd->xBlockSize = 0; + pxEnd->pxNextFreeBlock = NULL; + + /* To start with there is a single free block that is sized to take up the + * entire heap space, minus the space taken by pxEnd. */ + pxFirstFreeBlock = ( void * ) pucAlignedHeap; + pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; + pxFirstFreeBlock->pxNextFreeBlock = pxEnd; + + /* Only one block exists - and it covers the entire usable heap space. */ + xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; +} +/*-----------------------------------------------------------*/ + +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) +{ + BlockLink_t * pxIterator; + uint8_t * puc; + + /* Iterate through the list until a block is found that has a higher address + * than the block being inserted. */ + for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) + { + /* Nothing to do here, just iterate to the right position. */ + } + + /* Do the block being inserted, and the block it is being inserted after + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxIterator; + + if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) + { + pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; + pxBlockToInsert = pxIterator; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Do the block being inserted, and the block it is being inserted before + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxBlockToInsert; + + if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) + { + if( pxIterator->pxNextFreeBlock != pxEnd ) + { + /* Form one big block from the two blocks. */ + pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxEnd; + } + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; + } + + /* If the block being inserted plugged a gap, so was merged with the block + * before and the block after, then it's pxNextFreeBlock pointer will have + * already been set, and should not be set here as that would make it point + * to itself. */ + if( pxIterator != pxBlockToInsert ) + { + pxIterator->pxNextFreeBlock = pxBlockToInsert; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} +/*-----------------------------------------------------------*/ + +void * pvPortMalloc( size_t xWantedSize ) +{ + BlockLink_t * pxBlock; + BlockLink_t * pxPreviousBlock; + BlockLink_t * pxNewBlockLink; + void * pvReturn = NULL; + size_t xAdditionalRequiredSize; + size_t xAllocatedBlockSize = 0; + + /* If this is the first call to malloc then the heap will require + * initialisation to setup the list of free blocks. */ + if( pxEnd == NULL ) + { + prvHeapInit(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xWantedSize > 0 ) + { + /* The wanted size must be increased so it can contain a BlockLink_t + * structure in addition to the requested amount of bytes. */ + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 ) + { + xWantedSize += xHeapStructSize; + + /* Ensure that blocks are always aligned to the required number + * of bytes. */ + if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 ) + { + /* Byte alignment required. */ + xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ); + + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 ) + { + xWantedSize += xAdditionalRequiredSize; + } + else + { + xWantedSize = 0; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + xWantedSize = 0; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Check the requested block size is not so large that the top bit is set. + * The top bit of the block size member of the BlockLink_t structure is used + * to determine who owns the block - the application or the kernel, so it + * must be free. */ + if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 ) + { + if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) + { + /* Traverse the list from the start (lowest address) block until + * one of adequate size is found. */ + pxPreviousBlock = &xStart; + pxBlock = xStart.pxNextFreeBlock; + + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + { + pxPreviousBlock = pxBlock; + pxBlock = pxBlock->pxNextFreeBlock; + } + + /* If the end marker was reached then a block of adequate size was + * not found. */ + if( pxBlock != pxEnd ) + { + /* Return the memory space pointed to - jumping over the + * BlockLink_t structure at its start. */ + pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); + + /* This block is being returned for use so must be taken out + * of the list of free blocks. */ + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + + /* If the block is larger than required it can be split into + * two. */ + if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE ) + { + /* This block is to be split into two. Create a new + * block following the number of bytes requested. The void + * cast is used to prevent byte alignment warnings from the + * compiler. */ + pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); + secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + + /* Calculate the sizes of two blocks split from the single + * block. */ + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + pxBlock->xBlockSize = xWantedSize; + + /* Insert the new block into the list of free blocks. */ + pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock; + pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xFreeBytesRemaining -= pxBlock->xBlockSize; + + if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) + { + xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xAllocatedBlockSize = pxBlock->xBlockSize; + + /* The block is being returned - it is allocated and owned by + * the application and has no "next" block. */ + secureheapALLOCATE_BLOCK( pxBlock ); + pxBlock->pxNextFreeBlock = NULL; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceMALLOC( pvReturn, xAllocatedBlockSize ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xAllocatedBlockSize; + + #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) + { + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */ + + secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 ); + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void * pv ) +{ + uint8_t * puc = ( uint8_t * ) pv; + BlockLink_t * pxLink; + + if( pv != NULL ) + { + /* The memory being freed will have an BlockLink_t structure immediately + * before it. */ + puc -= xHeapStructSize; + + /* This casting is to keep the compiler from issuing warnings. */ + pxLink = ( void * ) puc; + + /* Check the block is actually allocated. */ + secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ); + secureportASSERT( pxLink->pxNextFreeBlock == NULL ); + + if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ) + { + if( pxLink->pxNextFreeBlock == NULL ) + { + /* The block is being returned to the heap - it is no longer + * allocated. */ + secureheapFREE_BLOCK( pxLink ); + + secureportDISABLE_NON_SECURE_INTERRUPTS(); + { + /* Add this block to the list of free blocks. */ + xFreeBytesRemaining += pxLink->xBlockSize; + traceFREE( pv, pxLink->xBlockSize ); + prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); + } + secureportENABLE_NON_SECURE_INTERRUPTS(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } +} +/*-----------------------------------------------------------*/ + +size_t xPortGetFreeHeapSize( void ) +{ + return xFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +size_t xPortGetMinimumEverFreeHeapSize( void ) +{ + return xMinimumEverFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM55/secure/secure_heap.h b/portable/GCC/ARM_CM55/secure/secure_heap.h new file mode 100644 index 000000000..0e84a9d9d --- /dev/null +++ b/portable/GCC/ARM_CM55/secure/secure_heap.h @@ -0,0 +1,66 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_HEAP_H__ +#define __SECURE_HEAP_H__ + +/* Standard includes. */ +#include + +/** + * @brief Allocates memory from heap. + * + * @param[in] xWantedSize The size of the memory to be allocated. + * + * @return Pointer to the memory region if the allocation is successful, NULL + * otherwise. + */ +void * pvPortMalloc( size_t xWantedSize ); + +/** + * @brief Frees the previously allocated memory. + * + * @param[in] pv Pointer to the memory to be freed. + */ +void vPortFree( void * pv ); + +/** + * @brief Get the free heap size. + * + * @return Free heap size. + */ +size_t xPortGetFreeHeapSize( void ); + +/** + * @brief Get the minimum ever free heap size. + * + * @return Minimum ever free heap size. + */ +size_t xPortGetMinimumEverFreeHeapSize( void ); + +#endif /* __SECURE_HEAP_H__ */ diff --git a/portable/GCC/ARM_CM55/secure/secure_init.c b/portable/GCC/ARM_CM55/secure/secure_init.c new file mode 100644 index 000000000..c50d37668 --- /dev/null +++ b/portable/GCC/ARM_CM55/secure/secure_init.c @@ -0,0 +1,106 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Secure init includes. */ +#include "secure_init.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Constants required to manipulate the SCB. + */ +#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */ +#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL ) +#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS ) +#define secureinitSCB_AIRCR_PRIS_POS ( 14UL ) +#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS ) + +/** + * @brief Constants required to manipulate the FPU. + */ +#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define secureinitFPCCR_LSPENS_POS ( 29UL ) +#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS ) +#define secureinitFPCCR_TS_POS ( 26UL ) +#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS ) + +#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */ +#define secureinitNSACR_CP10_POS ( 10UL ) +#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS ) +#define secureinitNSACR_CP11_POS ( 11UL ) +#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS ) +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) | + ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) | + ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK ); + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is + * permitted. CP11 should be programmed to the same value as CP10. */ + *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK ); + + /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures + * that we can enable/disable lazy stacking in port.c file. */ + *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK ); + + /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP + * registers (S16-S31) are also pushed to stack on exception entry and + * restored on exception return. */ + *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK ); + } +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM55/secure/secure_init.h b/portable/GCC/ARM_CM55/secure/secure_init.h new file mode 100644 index 000000000..ebe04900f --- /dev/null +++ b/portable/GCC/ARM_CM55/secure/secure_init.h @@ -0,0 +1,54 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_INIT_H__ +#define __SECURE_INIT_H__ + +/** + * @brief De-prioritizes the non-secure exceptions. + * + * This is needed to ensure that the non-secure PendSV runs at the lowest + * priority. Context switch is done in the non-secure PendSV handler. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_DePrioritizeNSExceptions( void ); + +/** + * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access. + * + * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point + * Registers are not leaked to the non-secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_EnableNSFPUAccess( void ); + +#endif /* __SECURE_INIT_H__ */ diff --git a/portable/GCC/ARM_CM55/secure/secure_port_macros.h b/portable/GCC/ARM_CM55/secure/secure_port_macros.h new file mode 100644 index 000000000..a70da2c65 --- /dev/null +++ b/portable/GCC/ARM_CM55/secure/secure_port_macros.h @@ -0,0 +1,140 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_PORT_MACROS_H__ +#define __SECURE_PORT_MACROS_H__ + +/** + * @brief Byte alignment requirements. + */ +#define secureportBYTE_ALIGNMENT 8 +#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 ) + +/** + * @brief Macro to declare a function as non-secure callable. + */ +#if defined( __IAR_SYSTEMS_ICC__ ) + #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry __root +#else + #define secureportNON_SECURE_CALLABLE __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) ) +#endif + +/** + * @brief Set the secure PRIMASK value. + */ +#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Set the non-secure PRIMASK value. + */ +#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Read the PSP value in the given variable. + */ +#define secureportREAD_PSP( pucOutCurrentStackPointer ) \ + __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) ) + +/** + * @brief Set the PSP to the given value. + */ +#define secureportSET_PSP( pucCurrentStackPointer ) \ + __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) ) + +/** + * @brief Read the PSPLIM value in the given variable. + */ +#define secureportREAD_PSPLIM( pucOutStackLimit ) \ + __asm volatile ( "mrs %0, psplim" : "=r" ( pucOutStackLimit ) ) + +/** + * @brief Set the PSPLIM to the given value. + */ +#define secureportSET_PSPLIM( pucStackLimit ) \ + __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) ) + +/** + * @brief Set the NonSecure MSP to the given value. + */ +#define secureportSET_MSP_NS( pucMainStackPointer ) \ + __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) ) + +/** + * @brief Set the CONTROL register to the given value. + */ +#define secureportSET_CONTROL( ulControl ) \ + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" ) + +/** + * @brief Read the Interrupt Program Status Register (IPSR) value in the given + * variable. + */ +#define secureportREAD_IPSR( ulIPSR ) \ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) ) + +/** + * @brief PRIMASK value to enable interrupts. + */ +#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0 + +/** + * @brief PRIMASK value to disable interrupts. + */ +#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1 + +/** + * @brief Disable secure interrupts. + */ +#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Disable non-secure interrupts. + * + * This effectively disables context switches. + */ +#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Enable non-secure interrupts. + */ +#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL ) + +/** + * @brief Assert definition. + */ +#define secureportASSERT( x ) \ + if( ( x ) == 0 ) \ + { \ + secureportDISABLE_SECURE_INTERRUPTS(); \ + secureportDISABLE_NON_SECURE_INTERRUPTS(); \ + for( ; ; ) {; } \ + } + +#endif /* __SECURE_PORT_MACROS_H__ */ diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c new file mode 100644 index 000000000..4b984932d --- /dev/null +++ b/portable/GCC/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.c @@ -0,0 +1,2055 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" +#include "event_groups.h" +#include "stream_buffer.h" +#include "mpu_prototypes.h" +#include "mpu_syscall_numbers.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( INCLUDE_xTaskDelayUntil == 1 ) + + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskDelayUntilImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskDelayUntil_Unpriv \n" + " MPU_xTaskDelayUntil_Priv: \n" + " b MPU_xTaskDelayUntilImpl \n" + " MPU_xTaskDelayUntil_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskAbortDelayImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskAbortDelay_Unpriv \n" + " MPU_xTaskAbortDelay_Priv: \n" + " b MPU_xTaskAbortDelayImpl \n" + " MPU_xTaskAbortDelay_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskDelay == 1 ) + + void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskDelayImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskDelay_Unpriv \n" + " MPU_vTaskDelay_Priv: \n" + " b MPU_vTaskDelayImpl \n" + " MPU_vTaskDelay_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskPriorityGet == 1 ) + + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskPriorityGetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskPriorityGet_Unpriv \n" + " MPU_uxTaskPriorityGet_Priv: \n" + " b MPU_uxTaskPriorityGetImpl \n" + " MPU_uxTaskPriorityGet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_eTaskGetState == 1 ) + + eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_eTaskGetStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_eTaskGetState_Unpriv \n" + " MPU_eTaskGetState_Priv: \n" + " b MPU_eTaskGetStateImpl \n" + " MPU_eTaskGetState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory" + ); + } + + #endif /* if ( INCLUDE_eTaskGetState == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskGetInfoImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskGetInfo_Unpriv \n" + " MPU_vTaskGetInfo_Priv: \n" + " b MPU_vTaskGetInfoImpl \n" + " MPU_vTaskGetInfo_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory" + ); + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) + + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetIdleTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetIdleTaskHandle_Unpriv \n" + " MPU_xTaskGetIdleTaskHandle_Priv: \n" + " b MPU_xTaskGetIdleTaskHandleImpl \n" + " MPU_xTaskGetIdleTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + + void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSuspendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSuspend_Unpriv \n" + " MPU_vTaskSuspend_Priv: \n" + " b MPU_vTaskSuspendImpl \n" + " MPU_vTaskSuspend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + + void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskResumeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskResume_Unpriv \n" + " MPU_vTaskResume_Priv: \n" + " b MPU_vTaskResumeImpl \n" + " MPU_vTaskResume_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + TickType_t MPU_xTaskGetTickCount( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetTickCountImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetTickCount_Unpriv \n" + " MPU_xTaskGetTickCount_Priv: \n" + " b MPU_xTaskGetTickCountImpl \n" + " MPU_xTaskGetTickCount_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetNumberOfTasksImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetNumberOfTasks_Unpriv \n" + " MPU_uxTaskGetNumberOfTasks_Priv: \n" + " b MPU_uxTaskGetNumberOfTasksImpl \n" + " MPU_uxTaskGetNumberOfTasks_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetRunTimeCounterImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetRunTimeCounter_Unpriv \n" + " MPU_ulTaskGetRunTimeCounter_Priv: \n" + " b MPU_ulTaskGetRunTimeCounterImpl \n" + " MPU_ulTaskGetRunTimeCounter_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetRunTimePercentImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetRunTimePercent_Unpriv \n" + " MPU_ulTaskGetRunTimePercent_Priv: \n" + " b MPU_ulTaskGetRunTimePercentImpl \n" + " MPU_ulTaskGetRunTimePercent_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetIdleRunTimePercentImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv \n" + " MPU_ulTaskGetIdleRunTimePercent_Priv: \n" + " b MPU_ulTaskGetIdleRunTimePercentImpl \n" + " MPU_ulTaskGetIdleRunTimePercent_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetIdleRunTimeCounterImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv \n" + " MPU_ulTaskGetIdleRunTimeCounter_Priv: \n" + " b MPU_ulTaskGetIdleRunTimeCounterImpl \n" + " MPU_ulTaskGetIdleRunTimeCounter_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetApplicationTaskTagImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetApplicationTaskTag_Unpriv \n" + " MPU_vTaskSetApplicationTaskTag_Priv: \n" + " b MPU_vTaskSetApplicationTaskTagImpl \n" + " MPU_vTaskSetApplicationTaskTag_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory" + ); + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetApplicationTaskTagImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetApplicationTaskTag_Unpriv \n" + " MPU_xTaskGetApplicationTaskTag_Priv: \n" + " b MPU_xTaskGetApplicationTaskTagImpl \n" + " MPU_xTaskGetApplicationTaskTag_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory" + ); + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetThreadLocalStoragePointerImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv \n" + " MPU_vTaskSetThreadLocalStoragePointer_Priv: \n" + " b MPU_vTaskSetThreadLocalStoragePointerImpl \n" + " MPU_vTaskSetThreadLocalStoragePointer_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory" + ); + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv \n" + " MPU_pvTaskGetThreadLocalStoragePointer_Priv: \n" + " b MPU_pvTaskGetThreadLocalStoragePointerImpl \n" + " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory" + ); + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetSystemStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetSystemState_Unpriv \n" + " MPU_uxTaskGetSystemState_Priv: \n" + " b MPU_uxTaskGetSystemStateImpl \n" + " MPU_uxTaskGetSystemState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory" + ); + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) + + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetStackHighWaterMarkImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetStackHighWaterMark_Unpriv \n" + " MPU_uxTaskGetStackHighWaterMark_Priv: \n" + " b MPU_uxTaskGetStackHighWaterMarkImpl \n" + " MPU_uxTaskGetStackHighWaterMark_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetStackHighWaterMark2Impl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv \n" + " MPU_uxTaskGetStackHighWaterMark2_Priv: \n" + " b MPU_uxTaskGetStackHighWaterMark2Impl \n" + " MPU_uxTaskGetStackHighWaterMark2_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) + + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetCurrentTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetCurrentTaskHandle_Unpriv \n" + " MPU_xTaskGetCurrentTaskHandle_Priv: \n" + " b MPU_xTaskGetCurrentTaskHandleImpl \n" + " MPU_xTaskGetCurrentTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory" + ); + } + + #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetSchedulerState == 1 ) + + BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetSchedulerStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetSchedulerState_Unpriv \n" + " MPU_xTaskGetSchedulerState_Priv: \n" + " b MPU_xTaskGetSchedulerStateImpl \n" + " MPU_xTaskGetSchedulerState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */ +/*-----------------------------------------------------------*/ + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetTimeOutStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetTimeOutState_Unpriv \n" + " MPU_vTaskSetTimeOutState_Priv: \n" + " b MPU_vTaskSetTimeOutStateImpl \n" + " MPU_vTaskSetTimeOutState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskCheckForTimeOutImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskCheckForTimeOut_Unpriv \n" + " MPU_xTaskCheckForTimeOut_Priv: \n" + " b MPU_xTaskCheckForTimeOutImpl \n" + " MPU_xTaskCheckForTimeOut_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotify_Unpriv \n" + " MPU_xTaskGenericNotify_Priv: \n" + " b MPU_xTaskGenericNotifyImpl \n" + " MPU_xTaskGenericNotify_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyWaitImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotifyWait_Unpriv \n" + " MPU_xTaskGenericNotifyWait_Priv: \n" + " b MPU_xTaskGenericNotifyWaitImpl \n" + " MPU_xTaskGenericNotifyWait_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGenericNotifyTakeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGenericNotifyTake_Unpriv \n" + " MPU_ulTaskGenericNotifyTake_Priv: \n" + " b MPU_ulTaskGenericNotifyTakeImpl \n" + " MPU_ulTaskGenericNotifyTake_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyStateClearImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotifyStateClear_Unpriv \n" + " MPU_xTaskGenericNotifyStateClear_Priv: \n" + " b MPU_xTaskGenericNotifyStateClearImpl \n" + " MPU_xTaskGenericNotifyStateClear_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGenericNotifyValueClearImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGenericNotifyValueClear_Unpriv \n" + " MPU_ulTaskGenericNotifyValueClear_Priv: \n" + " b MPU_ulTaskGenericNotifyValueClearImpl \n" + " MPU_ulTaskGenericNotifyValueClear_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGenericSendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGenericSend_Unpriv \n" + " MPU_xQueueGenericSend_Priv: \n" + " b MPU_xQueueGenericSendImpl \n" + " MPU_xQueueGenericSend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxQueueMessagesWaitingImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxQueueMessagesWaiting_Unpriv \n" + " MPU_uxQueueMessagesWaiting_Priv: \n" + " b MPU_uxQueueMessagesWaitingImpl \n" + " MPU_uxQueueMessagesWaiting_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxQueueSpacesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxQueueSpacesAvailable_Unpriv \n" + " MPU_uxQueueSpacesAvailable_Priv: \n" + " b MPU_uxQueueSpacesAvailableImpl \n" + " MPU_uxQueueSpacesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueReceiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueReceive_Unpriv \n" + " MPU_xQueueReceive_Priv: \n" + " b MPU_xQueueReceiveImpl \n" + " MPU_xQueueReceive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueuePeekImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueuePeek_Unpriv \n" + " MPU_xQueuePeek_Priv: \n" + " b MPU_xQueuePeekImpl \n" + " MPU_xQueuePeek_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueSemaphoreTakeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueSemaphoreTake_Unpriv \n" + " MPU_xQueueSemaphoreTake_Priv: \n" + " b MPU_xQueueSemaphoreTakeImpl \n" + " MPU_xQueueSemaphoreTake_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) + + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGetMutexHolderImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGetMutexHolder_Unpriv \n" + " MPU_xQueueGetMutexHolder_Priv: \n" + " b MPU_xQueueGetMutexHolderImpl \n" + " MPU_xQueueGetMutexHolder_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory" + ); + } + + #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueTakeMutexRecursiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueTakeMutexRecursive_Unpriv \n" + " MPU_xQueueTakeMutexRecursive_Priv: \n" + " b MPU_xQueueTakeMutexRecursiveImpl \n" + " MPU_xQueueTakeMutexRecursive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory" + ); + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGiveMutexRecursiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGiveMutexRecursive_Unpriv \n" + " MPU_xQueueGiveMutexRecursive_Priv: \n" + " b MPU_xQueueGiveMutexRecursiveImpl \n" + " MPU_xQueueGiveMutexRecursive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory" + ); + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueSelectFromSetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueSelectFromSet_Unpriv \n" + " MPU_xQueueSelectFromSet_Priv: \n" + " b MPU_xQueueSelectFromSetImpl \n" + " MPU_xQueueSelectFromSet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory" + ); + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueAddToSetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueAddToSet_Unpriv \n" + " MPU_xQueueAddToSet_Priv: \n" + " b MPU_xQueueAddToSetImpl \n" + " MPU_xQueueAddToSet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory" + ); + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vQueueAddToRegistryImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vQueueAddToRegistry_Unpriv \n" + " MPU_vQueueAddToRegistry_Priv: \n" + " b MPU_vQueueAddToRegistryImpl \n" + " MPU_vQueueAddToRegistry_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vQueueUnregisterQueueImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vQueueUnregisterQueue_Unpriv \n" + " MPU_vQueueUnregisterQueue_Priv: \n" + " b MPU_vQueueUnregisterQueueImpl \n" + " MPU_vQueueUnregisterQueue_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pcQueueGetNameImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pcQueueGetName_Unpriv \n" + " MPU_pcQueueGetName_Priv: \n" + " b MPU_pcQueueGetNameImpl \n" + " MPU_pcQueueGetName_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pvTimerGetTimerIDImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pvTimerGetTimerID_Unpriv \n" + " MPU_pvTimerGetTimerID_Priv: \n" + " b MPU_pvTimerGetTimerIDImpl \n" + " MPU_pvTimerGetTimerID_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTimerSetTimerIDImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTimerSetTimerID_Unpriv \n" + " MPU_vTimerSetTimerID_Priv: \n" + " b MPU_vTimerSetTimerIDImpl \n" + " MPU_vTimerSetTimerID_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerIsTimerActiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerIsTimerActive_Unpriv \n" + " MPU_xTimerIsTimerActive_Priv: \n" + " b MPU_xTimerIsTimerActiveImpl \n" + " MPU_xTimerIsTimerActive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv \n" + " MPU_xTimerGetTimerDaemonTaskHandle_Priv: \n" + " b MPU_xTimerGetTimerDaemonTaskHandleImpl \n" + " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGenericCommandFromTaskImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGenericCommandFromTask_Unpriv \n" + " MPU_xTimerGenericCommandFromTask_Priv: \n" + " b MPU_xTimerGenericCommandFromTaskImpl \n" + " MPU_xTimerGenericCommandFromTask_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pcTimerGetNameImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pcTimerGetName_Unpriv \n" + " MPU_pcTimerGetName_Priv: \n" + " b MPU_pcTimerGetNameImpl \n" + " MPU_pcTimerGetName_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTimerSetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTimerSetReloadMode_Unpriv \n" + " MPU_vTimerSetReloadMode_Priv: \n" + " b MPU_vTimerSetReloadModeImpl \n" + " MPU_vTimerSetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetReloadMode_Unpriv \n" + " MPU_xTimerGetReloadMode_Priv: \n" + " b MPU_xTimerGetReloadModeImpl \n" + " MPU_xTimerGetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTimerGetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTimerGetReloadMode_Unpriv \n" + " MPU_uxTimerGetReloadMode_Priv: \n" + " b MPU_uxTimerGetReloadModeImpl \n" + " MPU_uxTimerGetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetPeriodImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetPeriod_Unpriv \n" + " MPU_xTimerGetPeriod_Priv: \n" + " b MPU_xTimerGetPeriodImpl \n" + " MPU_xTimerGetPeriod_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetExpiryTimeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetExpiryTime_Unpriv \n" + " MPU_xTimerGetExpiryTime_Priv: \n" + " b MPU_xTimerGetExpiryTimeImpl \n" + " MPU_xTimerGetExpiryTime_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupWaitBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupWaitBits_Unpriv \n" + " MPU_xEventGroupWaitBits_Priv: \n" + " b MPU_xEventGroupWaitBitsImpl \n" + " MPU_xEventGroupWaitBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupClearBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupClearBits_Unpriv \n" + " MPU_xEventGroupClearBits_Priv: \n" + " b MPU_xEventGroupClearBitsImpl \n" + " MPU_xEventGroupClearBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupSetBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupSetBits_Unpriv \n" + " MPU_xEventGroupSetBits_Priv: \n" + " b MPU_xEventGroupSetBitsImpl \n" + " MPU_xEventGroupSetBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupSyncImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupSync_Unpriv \n" + " MPU_xEventGroupSync_Priv: \n" + " b MPU_xEventGroupSyncImpl \n" + " MPU_xEventGroupSync_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxEventGroupGetNumberImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxEventGroupGetNumber_Unpriv \n" + " MPU_uxEventGroupGetNumber_Priv: \n" + " b MPU_uxEventGroupGetNumberImpl \n" + " MPU_uxEventGroupGetNumber_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory" + ); + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vEventGroupSetNumberImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vEventGroupSetNumber_Unpriv \n" + " MPU_vEventGroupSetNumber_Priv: \n" + " b MPU_vEventGroupSetNumberImpl \n" + " MPU_vEventGroupSetNumber_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory" + ); + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferSend_Unpriv \n" + " MPU_xStreamBufferSend_Priv: \n" + " b MPU_xStreamBufferSendImpl \n" + " MPU_xStreamBufferSend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferReceiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferReceive_Unpriv \n" + " MPU_xStreamBufferReceive_Priv: \n" + " b MPU_xStreamBufferReceiveImpl \n" + " MPU_xStreamBufferReceive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferIsFullImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferIsFull_Unpriv \n" + " MPU_xStreamBufferIsFull_Priv: \n" + " b MPU_xStreamBufferIsFullImpl \n" + " MPU_xStreamBufferIsFull_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferIsEmptyImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferIsEmpty_Unpriv \n" + " MPU_xStreamBufferIsEmpty_Priv: \n" + " b MPU_xStreamBufferIsEmptyImpl \n" + " MPU_xStreamBufferIsEmpty_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSpacesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferSpacesAvailable_Unpriv \n" + " MPU_xStreamBufferSpacesAvailable_Priv: \n" + " b MPU_xStreamBufferSpacesAvailableImpl \n" + " MPU_xStreamBufferSpacesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferBytesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferBytesAvailable_Unpriv \n" + " MPU_xStreamBufferBytesAvailable_Priv: \n" + " b MPU_xStreamBufferBytesAvailableImpl \n" + " MPU_xStreamBufferBytesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSetTriggerLevelImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferSetTriggerLevel_Unpriv \n" + " MPU_xStreamBufferSetTriggerLevel_Priv: \n" + " b MPU_xStreamBufferSetTriggerLevelImpl \n" + " MPU_xStreamBufferSetTriggerLevel_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferNextMessageLengthBytesImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv \n" + " MPU_xStreamBufferNextMessageLengthBytes_Priv: \n" + " b MPU_xStreamBufferNextMessageLengthBytesImpl \n" + " MPU_xStreamBufferNextMessageLengthBytes_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c new file mode 100644 index 000000000..76d2b2445 --- /dev/null +++ b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c @@ -0,0 +1,2280 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024-2025 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU includes. */ +#include "mpu_wrappers.h" +#include "mpu_syscall_numbers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration settings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to check the validity of an interrupt priority. + */ +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) ) +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used during system call enter and exit. + */ +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Offsets in the stack to the parameters when inside the SVC handler. + */ +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +#if ( portARMV8M_MINOR_VERSION >= 1 ) + + /* Enable Privileged eXecute Never MPU attribute for the selected memory + * region. */ + #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL ) +#endif /* portARMV8M_MINOR_VERSION >= 1 */ + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Extract first address of the MPU region as encoded in the + * RBAR (Region Base Address Register) value. */ +#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \ + ( ( rbar ) & portMPU_RBAR_ADDRESS_MASK ) + +/* Extract last address of the MPU region as encoded in the + * RLAR (Region Limit Address Register) value. */ +#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \ + ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK ) + +/* Does addr lies within [start, end] address range? */ +#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \ + ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) ) + +/* Is the access request satisfied by the available permissions? */ +#define portIS_AUTHORIZED( accessRequest, permissions ) \ + ( ( ( permissions ) & ( accessRequest ) ) == accessRequest ) + +/* Max value that fits in a uint32_t type. */ +#define portUINT32_MAX ( ~( ( uint32_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. + */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 + +/** + * @brief Constants required to check and configure PACBTI security feature implementation. + */ +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) ) + + #define portCONTROL_UPAC_EN ( 1UL << 7UL ) + #define portCONTROL_PAC_EN ( 1UL << 6UL ) + #define portCONTROL_UBTI_EN ( 1UL << 5UL ) + #define portCONTROL_BTI_EN ( 1UL << 4UL ) + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Extract MPU region's access permissions from the Region Base Address + * Register (RBAR) value. + * + * @param ulRBARValue RBAR value for the MPU region. + * + * @return uint32_t Access permissions. + */ + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + + /** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + /** + * @brief Configures PACBTI features. + * + * This function configures the Pointer Authentication, and Branch Target + * Identification security features as per the user configuration. It returns + * the value of the special purpose CONTROL register accordingly, and optionally + * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M + * architecture based) target supports PACBTI security feature. + * + * @param xWriteControlRegister Used to control whether the special purpose + * CONTROL register should be updated or not. + * + * @return CONTROL register value according to the configured PACBTI option. + */ + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the system call stack so that upon returning from + * SVC, the system call stack is used. + * + * @param pulTaskStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + * @param ucSystemCallNumber The system call number of the system call. + */ + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Raise SVC for exiting from a system call. + */ + void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief This variable is set to pdTRUE when the scheduler is started. + */ + PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + + /** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +/** + * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + /** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + + /** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + + /** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the cpsid instruction + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessPermissions = 0; + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_ONLY ) + { + ulAccessPermissions = tskMPU_READ_PERMISSION; + } + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_WRITE ) + { + ulAccessPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION ); + } + + return ulAccessPermissions; + } + +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } + +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ portOFFSET_TO_PC ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ]; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulSystemCallStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the system call section (i.e. application is + * not raising SVC directly). + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as + * it is non-NULL only during the execution of a system call (i.e. + * between system call enter and exit). + * 3. System call is not for a kernel API disabled by the configuration + * in FreeRTOSConfig.h. + * 4. We do not need to check that ucSystemCallNumber is within range + * because the assembly SVC handler checks that before calling + * this function. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) && + ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) ) + { + pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the system call stack for the stack frame. */ + pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulSystemCallStack[ i ] = pulTaskStack[ i ]; + } + + /* Store the value of the Link Register before the SVC was raised. + * It contains the address of the caller of the System Call entry + * point (i.e. the caller of the MPU_). We need to restore it + * when we exit from the system call. */ + pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; + + /* Store the value of the PSPLIM register before the SVC was raised. + * We need to restore it when we exit from the system call. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* Use the pulSystemCallStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif + + /* Start executing the system call upon returning from this handler. */ + pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; + + /* Raise a request to exit from the system call upon finishing the + * system call. */ + pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; + + /* Remember the location where we should copy the stack frame when we exit from + * the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize; + + /* Record if the hardware used padding to force the stack pointer + * to be double word aligned. */ + if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK ) + { + pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG; + } + else + { + pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG ); + } + + /* We ensure in pxPortInitialiseStack that the system call stack is + * double word aligned and therefore, there is no need of padding. + * Clear the bit[9] of stacked xPSR. */ + pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + + /* Raise the privilege for the duration of the system call. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " bics r0, r1 \n" /* Clear nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */ + { + __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulTaskStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the privileged code (i.e. application is not + * raising SVC directly). This SVC is only raised from + * vRequestSystemCallExit which is in the privileged code section. + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL - + * this means that we previously entered a system call and the + * application is not attempting to exit without entering a system + * call. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) ) + { + pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the task stack for the stack frame. */ + pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulTaskStack[ i ] = pulSystemCallStack[ i ]; + } + + /* Use the pulTaskStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) ); + + /* Return to the caller of the System Call entry point (i.e. the + * caller of the MPU_). */ + pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + /* Ensure that LR has a valid value.*/ + pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + + /* Restore the PSPLIM register to what it was at the time of + * system call entry. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* If the hardware used padding to force the stack pointer + * to be double word aligned, set the stacked xPSR bit[9], + * otherwise clear it. */ + if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG ) + { + pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK; + } + else + { + pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + } + + /* This is not NULL only for the duration of the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; + + /* Drop the privilege before returning to the thread mode. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " orrs r0, r1 \n" /* Set nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xTaskIsPrivileged = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xTaskIsPrivileged = pdTRUE; + } + + return xTaskIsPrivileged; + } + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged, + xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulIndex = 0; + uint32_t ulControl = 0x0; + + xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ + ulIndex++; + + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + ulIndex++; + + #if ( configENABLE_TRUSTZONE == 1 ) + { + xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */ + ulIndex++; + } + #endif /* configENABLE_TRUSTZONE */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + ulIndex++; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Check PACBTI security feature configuration before pushing the + * CONTROL register's value on task's TCB. */ + ulControl = prvConfigurePACBTI( pdFALSE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + if( xRunPrivileged == pdTRUE ) + { + xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + else + { + xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG ); + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ + ulIndex++; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + { + /* Ensure that the system call stack is double word aligned. */ + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) + + ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + /* This is not NULL only for the duration of a system call. */ + xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL; + } + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ]; + ulIndex++; + } + } + #endif /* configENABLE_PAC */ + + return &( xMPUSettings->ulContext[ ulIndex ] ); + } + +#else /* configENABLE_MPU */ + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ + { + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + pxTopOfStack--; + *pxTopOfStack = ulTaskPacKey[ i ]; + } + } + #endif /* configENABLE_PAC */ + + return pxTopOfStack; + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Set the CONTROL register value based on PACBTI security feature + * configuration before starting the first task. */ + ( void ) prvConfigurePACBTI( pdTRUE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + { + xSchedulerRunning = pdTRUE; + } + #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + configSTACK_DEPTH_TYPE uxStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( uxStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* PXN. */ + #if ( portARMV8M_MINOR_VERSION >= 1 ) + { + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ); + } + } + #endif /* portARMV8M_MINOR_VERSION >= 1 */ + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, + uint32_t ulBufferLength, + uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */ + + { + uint32_t i, ulBufferStartAddress, ulBufferEndAddress; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE ) + { + ulBufferStartAddress = ( uint32_t ) pvBuffer; + ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL ); + + for( i = 0; i < portTOTAL_NUM_REGIONS; i++ ) + { + /* Is the MPU region enabled? */ + if( ( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR & portMPU_RLAR_REGION_ENABLE ) == portMPU_RLAR_REGION_ENABLE ) + { + if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_AUTHORIZED( ulAccessRequested, + prvGetRegionAccessPermissions( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ) ) ) + { + xAccessGranted = pdTRUE; + break; + } + } + } + } + } + + return xAccessGranted; + } + +#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings; + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else + { + xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 ) + { + xAccessGranted = pdTRUE; + } + } + } + + return xAccessGranted; + } + + #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + ( void ) lInternalIndexOfKernelObject; + + /* If Access Control List feature is not used, all the tasks have + * access to all the kernel objects. */ + return pdTRUE; + } + + #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + { + uint32_t ulControl = 0x0; + + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); + + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; + + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c new file mode 100644 index 000000000..bc7bb6071 --- /dev/null +++ b/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c @@ -0,0 +1,524 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION + * is defined correctly and privileged functions are placed in correct sections. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Portasm includes. */ +#include "portasm.h" + +/* System call numbers includes. */ +#include "mpu_syscall_numbers.h" + +/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the + * header files. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#if ( configENABLE_MPU == 1 ) + + void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " program_mpu_first_task: \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */ + " \n" + " dmb \n" /* Complete outstanding transfers before disabling MPU. */ + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + " str r2, [r1] \n" /* Disable MPU. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */ + " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r1, [r2] \n" /* Program MAIR0. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " \n" + " movs r3, #4 \n" /* r3 = 4. */ + " str r3, [r1] \n" /* Program RNR = 4. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + " \n" + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " orr r2, #1 \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */ + " str r2, [r1] \n" /* Enable MPU. */ + " dsb \n" /* Force memory writes before continuing. */ + " \n" + " restore_context_first_task: \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/ + " ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */ + " \n" + " restore_special_regs_first_task: \n" + #if ( configENABLE_PAC == 1 ) + " ldmdb r1!, {r2-r5} \n" /* Read task's dedicated PAC key from the task's context. */ + " msr PAC_KEY_P_0, r2 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_1, r3 \n" + " msr PAC_KEY_P_2, r4 \n" + " msr PAC_KEY_P_3, r5 \n" + " clrm {r2-r5} \n" /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + " ldmdb r1!, {r2-r4, lr} \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */ + " msr psp, r2 \n" + " msr psplim, r3 \n" + " msr control, r4 \n" + " \n" + " restore_general_regs_first_task: \n" + " ldmdb r1!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */ + " stmia r2!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */ + " ldmdb r1!, {r4-r11} \n" /* r4-r11 restored. */ + " \n" + " restore_context_done_first_task: \n" + " str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */ + " mov r0, #0 \n" + " msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */ + " bx lr \n" + ); + } + +#else /* configENABLE_MPU */ + + void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + " ldr r0, [r1] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + " \n" + #if ( configENABLE_PAC == 1 ) + " ldmia r0!, {r1-r4} \n" /* Read task's dedicated PAC key from stack. */ + " msr PAC_KEY_P_3, r1 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_2, r2 \n" + " msr PAC_KEY_P_1, r3 \n" + " msr PAC_KEY_P_0, r4 \n" + " clrm {r1-r4} \n" /* Clear r1-r4. */ + #endif /* configENABLE_PAC */ + " \n" + " ldm r0!, {r1-r2} \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */ + " msr psplim, r1 \n" /* Set this task's PSPLIM value. */ + " mrs r1, control \n" /* Obtain current control register value. */ + " orrs r1, r1, #2 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */ + " msr control, r1 \n" /* Write back the new control register value. */ + " adds r0, #32 \n" /* Discard everything up to r0. */ + " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */ + " isb \n" + " mov r0, #0 \n" + " msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */ + " bx r2 \n" /* Finally, branch to EXC_RETURN. */ + ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* r0 = CONTROL. */ + " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + " ite ne \n" + " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + " bx lr \n" /* Return. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* Read the CONTROL register. */ + " bic r0, #1 \n" /* Clear the bit 0. */ + " msr control, r0 \n" /* Write back the new CONTROL value. */ + " bx lr \n" /* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vResetPrivilege( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* r0 = CONTROL. */ + " orr r0, #1 \n" /* r0 = r0 | 1. */ + " msr control, r0 \n" /* CONTROL = r0. */ + " bx lr \n" /* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r0, =0xe000ed08 \n" /* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */ + " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */ + " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */ + " cpsie i \n" /* Globally enable interrupts. */ + " cpsie f \n" + " dsb \n" + " isb \n" + " svc %0 \n" /* System call to start the first task. */ + " nop \n" + ::"i" ( portSVC_START_SCHEDULER ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, basepri \n" /* r0 = basepri. Return original basepri value. */ + " mov r1, %0 \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r1 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bx lr \n" /* Return. */ + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " msr basepri, r0 \n" /* basepri = ulMask. */ + " dsb \n" + " isb \n" + " bx lr \n" /* Return. */ + ::: "memory" + ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */ + " ldr r1, [r0] \n" /* r1 = Location in TCB where the context should be saved. */ + " mrs r2, psp \n" /* r2 = PSP. */ + " \n" + " save_general_regs: \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " add r2, r2, #0x20 \n" /* Move r2 to location where s0 is saved. */ + " tst lr, #0x10 \n" + " ittt eq \n" + " vstmiaeq r1!, {s16-s31} \n" /* Store s16-s31. */ + " vldmiaeq r2, {s0-s16} \n" /* Copy hardware saved FP context into s0-s16. */ + " vstmiaeq r1!, {s0-s16} \n" /* Store hardware saved FP context. */ + " sub r2, r2, #0x20 \n" /* Set r2 back to the location of hardware saved context. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " stmia r1!, {r4-r11} \n" /* Store r4-r11. */ + " ldmia r2, {r4-r11} \n" /* Copy the hardware saved context into r4-r11. */ + " stmia r1!, {r4-r11} \n" /* Store the hardware saved context. */ + " \n" + " save_special_regs: \n" + " mrs r3, psplim \n" /* r3 = PSPLIM. */ + " mrs r4, control \n" /* r4 = CONTROL. */ + " stmia r1!, {r2-r4, lr} \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ + #if ( configENABLE_PAC == 1 ) + " mrs r2, PAC_KEY_P_0 \n" /* Read task's dedicated PAC key from the PAC key registers. */ + " mrs r3, PAC_KEY_P_1 \n" + " mrs r4, PAC_KEY_P_2 \n" + " mrs r5, PAC_KEY_P_3 \n" + " stmia r1!, {r2-r5} \n" /* Store the task's dedicated PAC key on the task's context. */ + " clrm {r2-r5} \n" /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + " str r1, [r0] \n" /* Save the location from where the context should be restored as the first member of TCB. */ + " \n" + " select_next_task: \n" + " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bl vTaskSwitchContext \n" + " mov r0, #0 \n" /* r0 = 0. */ + " msr basepri, r0 \n" /* Enable interrupts. */ + " \n" + " program_mpu: \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */ + " \n" + " dmb \n" /* Complete outstanding transfers before disabling MPU. */ + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + " str r2, [r1] \n" /* Disable MPU. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */ + " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r1, [r2] \n" /* Program MAIR0. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " \n" + " movs r3, #4 \n" /* r3 = 4. */ + " str r3, [r1] \n" /* Program RNR = 4. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + " \n" + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " orr r2, #1 \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */ + " str r2, [r1] \n" /* Enable MPU. */ + " dsb \n" /* Force memory writes before continuing. */ + " \n" + " restore_context: \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/ + " ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */ + " \n" + " restore_special_regs: \n" + #if ( configENABLE_PAC == 1 ) + " ldmdb r1!, {r2-r5} \n" /* Read task's dedicated PAC key from the task's context. */ + " msr PAC_KEY_P_0, r2 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_1, r3 \n" + " msr PAC_KEY_P_2, r4 \n" + " msr PAC_KEY_P_3, r5 \n" + " clrm {r2-r5} \n" /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + " ldmdb r1!, {r2-r4, lr} \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */ + " msr psp, r2 \n" + " msr psplim, r3 \n" + " msr control, r4 \n" + " \n" + " restore_general_regs: \n" + " ldmdb r1!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */ + " stmia r2!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */ + " ldmdb r1!, {r4-r11} \n" /* r4-r11 restored. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" + " ittt eq \n" + " vldmdbeq r1!, {s0-s16} \n" /* s0-s16 contain hardware saved FP context. */ + " vstmiaeq r2!, {s0-s16} \n" /* Copy hardware saved FP context on the task stack. */ + " vldmdbeq r1!, {s16-s31} \n" /* Restore s16-s31. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + " restore_context_done: \n" + " str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */ + " bx lr \n" + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); + } + +#else /* configENABLE_MPU */ + + void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, psp \n" /* Read PSP in r0. */ + " \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vstmdbeq r0!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + " mrs r2, psplim \n" /* r2 = PSPLIM. */ + " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */ + " stmdb r0!, {r2-r11} \n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */ + " \n" + #if ( configENABLE_PAC == 1 ) + " mrs r1, PAC_KEY_P_3 \n" /* Read task's dedicated PAC key from the PAC key registers. */ + " mrs r2, PAC_KEY_P_2 \n" + " mrs r3, PAC_KEY_P_1 \n" + " mrs r4, PAC_KEY_P_0 \n" + " stmdb r0!, {r1-r4} \n" /* Store the task's dedicated PAC key on the stack. */ + " clrm {r1-r4} \n" /* Clear r1-r4. */ + #endif /* configENABLE_PAC */ + " \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + " str r0, [r1] \n" /* Save the new top of stack in TCB. */ + " \n" + " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bl vTaskSwitchContext \n" + " mov r0, #0 \n" /* r0 = 0. */ + " msr basepri, r0 \n" /* Enable interrupts. */ + " \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ + " \n" + #if ( configENABLE_PAC == 1 ) + " ldmia r0!, {r2-r5} \n" /* Read task's dedicated PAC key from stack. */ + " msr PAC_KEY_P_3, r2 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_2, r3 \n" + " msr PAC_KEY_P_1, r4 \n" + " msr PAC_KEY_P_0, r5 \n" + " clrm {r2-r5} \n" /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + " \n" + " ldmia r0!, {r2-r11} \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */ + " \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst r3, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vldmiaeq r0!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */ + " msr psp, r0 \n" /* Remember the new top of stack for the task. */ + " bx r3 \n" + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + ".syntax unified \n" + ".extern vPortSVCHandler_C \n" + ".extern vSystemCallEnter \n" + ".extern vSystemCallExit \n" + " \n" + "tst lr, #4 \n" + "ite eq \n" + "mrseq r0, msp \n" + "mrsne r0, psp \n" + " \n" + "ldr r1, [r0, #24] \n" + "ldrb r2, [r1, #-2] \n" + "cmp r2, %0 \n" + "blt syscall_enter \n" + "cmp r2, %1 \n" + "beq syscall_exit \n" + "b vPortSVCHandler_C \n" + " \n" + "syscall_enter: \n" + " mov r1, lr \n" + " b vSystemCallEnter \n" + " \n" + "syscall_exit: \n" + " mov r1, lr \n" + " b vSystemCallExit \n" + " \n" + : /* No outputs. */ + : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT ) + : "r0", "r1", "r2", "memory" + ); + } + +#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " tst lr, #4 \n" + " ite eq \n" + " mrseq r0, msp \n" + " mrsne r0, psp \n" + " ldr r1, =vPortSVCHandler_C \n" + " bx r1 \n" + ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.h b/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.h new file mode 100644 index 000000000..b7021b024 --- /dev/null +++ b/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kernel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h new file mode 100644 index 000000000..c6a179c52 --- /dev/null +++ b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacro.h @@ -0,0 +1,79 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_MVE + #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE. +#endif /* configENABLE_MVE */ +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M55" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portARMV8M_MINOR_VERSION 1 +#define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h new file mode 100644 index 000000000..f373bcad5 --- /dev/null +++ b/portable/GCC/ARM_CM55_NTZ/non_secure/portmacrocommon.h @@ -0,0 +1,582 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACROCOMMON_H +#define PORTMACROCOMMON_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. +#endif /* configENABLE_FPU */ + +#ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. +#endif /* configENABLE_MPU */ + +#ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. +#endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() +#define portINLINE __inline +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif +#define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ +extern BaseType_t xPortIsInsideInterrupt( void ); + +extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + +extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; +extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + +extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; +extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + +#if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_PAC == 1 ) + + /** + * @brief Generates 128-bit task's random PAC key. + * + * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be + * filled with a 128-bit random number. + */ + void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); + +#endif /* configENABLE_PAC */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ +#if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) +#else + #define portPRIVILEGE_BIT ( 0x0UL ) +#endif /* configENABLE_MPU */ + +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ +#define portPRIVILEGED_FLASH_REGION ( 0UL ) +#define portUNPRIVILEGED_FLASH_REGION ( 1UL ) +#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) +#define portPRIVILEGED_RAM_REGION ( 3UL ) +#define portSTACK_REGION ( 4UL ) +#define portFIRST_CONFIGURABLE_REGION ( 5UL ) +#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) +#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) +#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ +#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ +#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ +#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ +#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ +#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ +#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ +#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) +#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) +#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + +#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) +#define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) +#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) +#define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + +#define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + #ifndef configSYSTEM_CALL_STACK_SIZE + #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. + #endif + + /** + * @brief System call stack. + */ + typedef struct SYSTEM_CALL_STACK_INFO + { + uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; + uint32_t * pulSystemCallStack; + uint32_t * pulSystemCallStackLimit; + uint32_t * pulTaskStack; + uint32_t ulLinkRegisterAtSystemCallEntry; + uint32_t ulStackLimitRegisterAtSystemCallEntry; + } xSYSTEM_CALL_STACK_INFO; + + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + /** + * @brief MPU settings as stored in the TCB. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><-----------><----> + * 16 17 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 71 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 17 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 55 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | | | PC, xPSR | EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><-----------><----> + * 16 17 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 70 + + #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + /* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 17 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 54 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+------------------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +----------+-----------------+------------------------------+------------+-----+ + * + * <---------><----------------><------------------------------><-----------><----> + * 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 38 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+----------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | PC, xPSR | EXC_RETURN | | | + * +----------+-----------------+----------------------+------------+-----+ + * + * <---------><----------------><----------------------><-----------><----> + * 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 37 + + #else /* #if( configENABLE_TRUSTZONE == 1 ) */ + + /* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) + + /* Size of an Access Control List (ACL) entry in bits. */ + #define portACL_ENTRY_SIZE_BITS ( 32U ) + + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + uint32_t ulContext[ MAX_CONTEXT_SIZE ]; + uint32_t ulTaskFlags; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo; + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ]; + #endif + #endif + } xMPU_SETTINGS; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Validate priority of ISRs that are allowed to call FreeRTOS + * system calls. + */ +#if ( configASSERT_DEFINED == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif +#endif + +/** + * @brief SVC numbers. + */ +#define portSVC_ALLOCATE_SECURE_CONTEXT 100 +#define portSVC_FREE_SECURE_CONTEXT 101 +#define portSVC_START_SCHEDULER 102 +#define portSVC_RAISE_PRIVILEGE 103 +#define portSVC_SYSTEM_CALL_EXIT 104 +#define portSVC_YIELD 105 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) +#endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() +#else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + extern BaseType_t xPortIsTaskPrivileged( void ); + +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACROCOMMON_H */ diff --git a/portable/GCC/ARM_CM7/ReadMe.txt b/portable/GCC/ARM_CM7/ReadMe.txt new file mode 100644 index 000000000..90be0b216 --- /dev/null +++ b/portable/GCC/ARM_CM7/ReadMe.txt @@ -0,0 +1,18 @@ +There are two options for running FreeRTOS on ARM Cortex-M7 microcontrollers. +The best option depends on the revision of the ARM Cortex-M7 core in use. The +revision is specified by an 'r' number, and a 'p' number, so will look something +like 'r0p1'. Check the documentation for the microcontroller in use to find the +revision of the Cortex-M7 core used in that microcontroller. If in doubt, use +the FreeRTOS port provided specifically for r0p1 revisions, as that can be used +with all core revisions. + +The first option is to use the ARM Cortex-M4F port, and the second option is to +use the Cortex-M7 r0p1 port - the latter containing a minor errata workaround. + +If the revision of the ARM Cortex-M7 core is not r0p1 then either option can be +used, but it is recommended to use the FreeRTOS ARM Cortex-M4F port located in +the /FreeRTOS/Source/portable/GCC/ARM_CM4F directory. + +If the revision of the ARM Cortex-M7 core is r0p1 then use the FreeRTOS ARM +Cortex-M7 r0p1 port located in the /FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 +directory. diff --git a/portable/GCC/ARM_CM7/r0p1/port.c b/portable/GCC/ARM_CM7/r0p1/port.c new file mode 100644 index 000000000..6586980f4 --- /dev/null +++ b/portable/GCC/ARM_CM7/r0p1/port.c @@ -0,0 +1,897 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ARM CM7 port. +*----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#ifndef __ARM_FP + #error This port can only be used when the project options are configured to enable hardware floating point support. +#endif + +/* Prototype of all Interrupt Service Routines (ISRs). */ +typedef void ( * portISR_t )( void ); + +/* Constants required to manipulate the core. Registers first... */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +/* ...then bits in the registers. */ +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) + +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL ) +#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL ) + +/* Constants used to check the installation of the FreeRTOS interrupt handlers. */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xE000ED08 ) ) +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) + +/* Constants required to check the validity of an interrupt priority. */ +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) + +/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */ +#define portVECTACTIVE_MASK ( 0xFFUL ) + +/* Constants required to manipulate the VFP. */ +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */ +#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) +#define portINITIAL_EXC_RETURN ( 0xfffffffd ) + +/* The systick is a 24-bit counter. */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/* For strict compliance with the Cortex-M spec the task start address should + * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */ +#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL ) + +/* A fiddle factor to estimate the number of SysTick counts that would have + * occurred while the SysTick counter is stopped during tickless idle + * calculations. */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) + +/* Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/* Let the user override the pre-loading of the initial LR with the address of + * prvTaskExitError() in case it messes up unwinding of the stack in the + * debugger. */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ); + +/* + * Exception handlers. + */ +void xPortPendSVHandler( void ) __attribute__( ( naked ) ); +void xPortSysTickHandler( void ); +void vPortSVCHandler( void ) __attribute__( ( naked ) ); + +/* + * Start first task is a separate function so it can be tested in isolation. + */ +static void prvPortStartFirstTask( void ) __attribute__( ( naked ) ); + +/* + * Function to enable the VFP. + */ +static void vPortEnableVFP( void ) __attribute__( ( naked ) ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* Each task maintains its own interrupt status in the critical nesting + * variable. */ +static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +/* + * The number of SysTick increments that make up one tick period. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulTimerCountsForOneTick = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * The maximum number of tick periods that can be suppressed is limited by the + * 24 bit resolution of the SysTick timer. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t xMaximumPossibleSuppressedTicks = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Compensate for the CPU cycles that pass while the SysTick is stopped (low + * power functionality only. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( configASSERT_DEFINED == 1 ) + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16; +#endif /* configASSERT_DEFINED */ + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + + /* Offset added to account for the way the MCU uses the stack on entry/exit + * of interrupts, and to ensure alignment. */ + pxTopOfStack--; + + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + + /* Save code space by skipping register initialisation. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + + /* A save method is being used that requires each task to maintain its + * own exec return value. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; + + pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ + configASSERT( uxCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being defined + * but never called. ulDummy is used purely to quieten other warnings + * about code appearing after this function is called - making ulDummy + * volatile makes the compiler think the function could return and + * therefore not output an 'unreachable code' warning for code that appears + * after it. */ + } +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler( void ) +{ + __asm volatile ( + " ldr r3, =pxCurrentTCB \n" /* Restore the context. */ + " ldr r1, [r3] \n" /* Get the pxCurrentTCB address. */ + " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */ + " ldmia r0!, {r4-r11, r14} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */ + " msr psp, r0 \n" /* Restore the task stack pointer. */ + " isb \n" + " mov r0, #0 \n" + " msr basepri, r0 \n" + " bx r14 \n" + " \n" + " .ltorg \n" + ); +} +/*-----------------------------------------------------------*/ + +static void prvPortStartFirstTask( void ) +{ + /* Start the first task. This also clears the bit that indicates the FPU is + * in use in case the FPU was used before the scheduler was started - which + * would otherwise result in the unnecessary leaving of space in the SVC stack + * for lazy saving of FPU registers. */ + __asm volatile ( + " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n" + " ldr r0, [r0] \n" + " msr msp, r0 \n" /* Set the msp back to the start of the stack. */ + " mov r0, #0 \n" /* Clear the bit that indicates the FPU is in use, see comment above. */ + " msr control, r0 \n" + " cpsie i \n" /* Globally enable interrupts. */ + " cpsie f \n" + " dsb \n" + " isb \n" + " svc 0 \n" /* System call to start first task. */ + " nop \n" + " .ltorg \n" + ); +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions vPortSVCHandler and + * xPortPendSVHandler for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * vPortSVCHandler and xPortPendSVHandler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( configASSERT_DEFINED == 1 ) + { + volatile uint8_t ucOriginalPriority; + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * Save the interrupt priority value that is about to be clobbered. */ + ucOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to all + * possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + + /* Restore the clobbered interrupt priority register to its original + * value. */ + *pucFirstUserPriorityRegister = ucOriginalPriority; + } + #endif /* configASSERT_DEFINED */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + /* Ensure the VFP is enabled - it should be anyway. */ + vPortEnableVFP(); + + /* Lazy save always. */ + *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; + + /* Start the first task. */ + prvPortStartFirstTask(); + + /* Should never get here as the tasks will now be executing! Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimisation does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ + if( uxCriticalNesting == 1 ) + { + configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void xPortPendSVHandler( void ) +{ + /* This is a naked function. */ + + __asm volatile + ( + " mrs r0, psp \n" + " isb \n" + " \n" + " ldr r3, =pxCurrentTCB \n" /* Get the location of the current TCB. */ + " ldr r2, [r3] \n" + " \n" + " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, push high vfp registers. */ + " it eq \n" + " vstmdbeq r0!, {s16-s31} \n" + " \n" + " stmdb r0!, {r4-r11, r14} \n" /* Save the core registers. */ + " str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */ + " \n" + " stmdb sp!, {r0, r3} \n" + " mov r0, %0 \n" + " cpsid i \n" /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */ + " msr basepri, r0 \n" + " dsb \n" + " isb \n" + " cpsie i \n" /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */ + " bl vTaskSwitchContext \n" + " mov r0, #0 \n" + " msr basepri, r0 \n" + " ldmia sp!, {r0, r3} \n" + " \n" + " ldr r1, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. */ + " ldr r0, [r1] \n" + " \n" + " ldmia r0!, {r4-r11, r14} \n" /* Pop the core registers. */ + " \n" + " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, pop the high vfp registers too. */ + " it eq \n" + " vldmiaeq r0!, {s16-s31} \n" + " \n" + " msr psp, r0 \n" + " isb \n" + " \n" + #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */ + #if WORKAROUND_PMU_CM001 == 1 + " push { r14 } \n" + " pop { pc } \n" + #endif + #endif + " \n" + " bx r14 \n" + " \n" + " .ltorg \n" + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + /* The SysTick runs at the lowest interrupt priority, so when this interrupt + * executes all interrupts must be unmasked. There is therefore no need to + * save and then restore the interrupt mask value as its value is already + * known. */ + portDISABLE_INTERRUPTS(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + + /* A context switch is required. Context switching is performed in + * the PendSV interrupt. Pend the PendSV interrupt. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + portENABLE_INTERRUPTS(); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the cpsid instruction + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } + +#endif /* #if configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and clear the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); +} +/*-----------------------------------------------------------*/ + +/* This is a naked function. */ +static void vPortEnableVFP( void ) +{ + __asm volatile + ( + " ldr.w r0, =0xE000ED88 \n" /* The FPU enable bits are in the CPACR. */ + " ldr r1, [r0] \n" + " \n" + " orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */ + " str r1, [r0] \n" + " bx r14 \n" + " .ltorg \n" + ); +} +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* configASSERT_DEFINED */ diff --git a/portable/GCC/ARM_CM7/r0p1/portmacro.h b/portable/GCC/ARM_CM7/r0p1/portmacro.h new file mode 100644 index 000000000..4bc490b98 --- /dev/null +++ b/portable/GCC/ARM_CM7/r0p1/portmacro.h @@ -0,0 +1,267 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/* Scheduler utilities. */ +#define portYIELD() \ + { \ + /* Set a PendSV to request a context switch. */ \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + \ + /* Barriers are normally not required but do ensure the code is completely \ + * within the specified behaviour for the architecture. */ \ + __asm volatile ( "dsb" ::: "memory" ); \ + __asm volatile ( "isb" ); \ + } + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portYIELD(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x ) +#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() +#define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not necessary for to use this port. They are defined so the common demo files + * (which build with all the ports) will build. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +/* Tickless idle/low power functionality. */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specific optimisations. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + +/* Generic helper function. */ + __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint8_t ucReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ucReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif + +/* portNOP() is not required by this port. */ +#define portNOP() + +#define portINLINE __inline + +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif + +portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} + +/*-----------------------------------------------------------*/ + +portFORCE_INLINE static void vPortRaiseBASEPRI( void ) +{ + uint32_t ulNewBASEPRI; + + __asm volatile + ( + " mov %0, %1 \n" \ + " cpsid i \n" \ + " msr basepri, %0 \n" \ + " isb \n" \ + " dsb \n" \ + " cpsie i \n" \ + : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); +} + +/*-----------------------------------------------------------*/ + +portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void ) +{ + uint32_t ulOriginalBASEPRI, ulNewBASEPRI; + + __asm volatile + ( + " mrs %0, basepri \n" \ + " mov %1, %2 \n" \ + " cpsid i \n" \ + " msr basepri, %1 \n" \ + " isb \n" \ + " dsb \n" \ + " cpsie i \n" \ + : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); + + /* This return will not be reached but is necessary to prevent compiler + * warnings. */ + return ulOriginalBASEPRI; +} +/*-----------------------------------------------------------*/ + +portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) +{ + __asm volatile + ( + " msr basepri, %0 " ::"r" ( ulNewMaskValue ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c new file mode 100644 index 000000000..33410a0c3 --- /dev/null +++ b/portable/GCC/ARM_CM85/non_secure/mpu_wrappers_v2_asm.c @@ -0,0 +1,2056 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" +#include "event_groups.h" +#include "stream_buffer.h" +#include "mpu_prototypes.h" +#include "mpu_syscall_numbers.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( INCLUDE_xTaskDelayUntil == 1 ) + + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskDelayUntilImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskDelayUntil_Unpriv \n" + " MPU_xTaskDelayUntil_Priv: \n" + " b MPU_xTaskDelayUntilImpl \n" + " MPU_xTaskDelayUntil_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskAbortDelayImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskAbortDelay_Unpriv \n" + " MPU_xTaskAbortDelay_Priv: \n" + " b MPU_xTaskAbortDelayImpl \n" + " MPU_xTaskAbortDelay_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskDelay == 1 ) + + void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskDelayImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskDelay_Unpriv \n" + " MPU_vTaskDelay_Priv: \n" + " b MPU_vTaskDelayImpl \n" + " MPU_vTaskDelay_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskPriorityGet == 1 ) + + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskPriorityGetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskPriorityGet_Unpriv \n" + " MPU_uxTaskPriorityGet_Priv: \n" + " b MPU_uxTaskPriorityGetImpl \n" + " MPU_uxTaskPriorityGet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_eTaskGetState == 1 ) + + eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_eTaskGetStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_eTaskGetState_Unpriv \n" + " MPU_eTaskGetState_Priv: \n" + " b MPU_eTaskGetStateImpl \n" + " MPU_eTaskGetState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory" + ); + } + + #endif /* if ( INCLUDE_eTaskGetState == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskGetInfoImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskGetInfo_Unpriv \n" + " MPU_vTaskGetInfo_Priv: \n" + " b MPU_vTaskGetInfoImpl \n" + " MPU_vTaskGetInfo_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory" + ); + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) + + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetIdleTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetIdleTaskHandle_Unpriv \n" + " MPU_xTaskGetIdleTaskHandle_Priv: \n" + " b MPU_xTaskGetIdleTaskHandleImpl \n" + " MPU_xTaskGetIdleTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + + void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSuspendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSuspend_Unpriv \n" + " MPU_vTaskSuspend_Priv: \n" + " b MPU_vTaskSuspendImpl \n" + " MPU_vTaskSuspend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + + void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskResumeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskResume_Unpriv \n" + " MPU_vTaskResume_Priv: \n" + " b MPU_vTaskResumeImpl \n" + " MPU_vTaskResume_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + TickType_t MPU_xTaskGetTickCount( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetTickCountImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetTickCount_Unpriv \n" + " MPU_xTaskGetTickCount_Priv: \n" + " b MPU_xTaskGetTickCountImpl \n" + " MPU_xTaskGetTickCount_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetNumberOfTasksImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetNumberOfTasks_Unpriv \n" + " MPU_uxTaskGetNumberOfTasks_Priv: \n" + " b MPU_uxTaskGetNumberOfTasksImpl \n" + " MPU_uxTaskGetNumberOfTasks_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetRunTimeCounterImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetRunTimeCounter_Unpriv \n" + " MPU_ulTaskGetRunTimeCounter_Priv: \n" + " b MPU_ulTaskGetRunTimeCounterImpl \n" + " MPU_ulTaskGetRunTimeCounter_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetRunTimePercentImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetRunTimePercent_Unpriv \n" + " MPU_ulTaskGetRunTimePercent_Priv: \n" + " b MPU_ulTaskGetRunTimePercentImpl \n" + " MPU_ulTaskGetRunTimePercent_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetIdleRunTimePercentImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv \n" + " MPU_ulTaskGetIdleRunTimePercent_Priv: \n" + " b MPU_ulTaskGetIdleRunTimePercentImpl \n" + " MPU_ulTaskGetIdleRunTimePercent_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetIdleRunTimeCounterImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv \n" + " MPU_ulTaskGetIdleRunTimeCounter_Priv: \n" + " b MPU_ulTaskGetIdleRunTimeCounterImpl \n" + " MPU_ulTaskGetIdleRunTimeCounter_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetApplicationTaskTagImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetApplicationTaskTag_Unpriv \n" + " MPU_vTaskSetApplicationTaskTag_Priv: \n" + " b MPU_vTaskSetApplicationTaskTagImpl \n" + " MPU_vTaskSetApplicationTaskTag_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory" + ); + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetApplicationTaskTagImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetApplicationTaskTag_Unpriv \n" + " MPU_xTaskGetApplicationTaskTag_Priv: \n" + " b MPU_xTaskGetApplicationTaskTagImpl \n" + " MPU_xTaskGetApplicationTaskTag_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory" + ); + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetThreadLocalStoragePointerImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv \n" + " MPU_vTaskSetThreadLocalStoragePointer_Priv: \n" + " b MPU_vTaskSetThreadLocalStoragePointerImpl \n" + " MPU_vTaskSetThreadLocalStoragePointer_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory" + ); + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv \n" + " MPU_pvTaskGetThreadLocalStoragePointer_Priv: \n" + " b MPU_pvTaskGetThreadLocalStoragePointerImpl \n" + " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory" + ); + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetSystemStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetSystemState_Unpriv \n" + " MPU_uxTaskGetSystemState_Priv: \n" + " b MPU_uxTaskGetSystemStateImpl \n" + " MPU_uxTaskGetSystemState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory" + ); + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) + + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetStackHighWaterMarkImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetStackHighWaterMark_Unpriv \n" + " MPU_uxTaskGetStackHighWaterMark_Priv: \n" + " b MPU_uxTaskGetStackHighWaterMarkImpl \n" + " MPU_uxTaskGetStackHighWaterMark_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetStackHighWaterMark2Impl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv \n" + " MPU_uxTaskGetStackHighWaterMark2_Priv: \n" + " b MPU_uxTaskGetStackHighWaterMark2Impl \n" + " MPU_uxTaskGetStackHighWaterMark2_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) + + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetCurrentTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetCurrentTaskHandle_Unpriv \n" + " MPU_xTaskGetCurrentTaskHandle_Priv: \n" + " b MPU_xTaskGetCurrentTaskHandleImpl \n" + " MPU_xTaskGetCurrentTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory" + ); + } + + #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetSchedulerState == 1 ) + + BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetSchedulerStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetSchedulerState_Unpriv \n" + " MPU_xTaskGetSchedulerState_Priv: \n" + " b MPU_xTaskGetSchedulerStateImpl \n" + " MPU_xTaskGetSchedulerState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */ +/*-----------------------------------------------------------*/ + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetTimeOutStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetTimeOutState_Unpriv \n" + " MPU_vTaskSetTimeOutState_Priv: \n" + " b MPU_vTaskSetTimeOutStateImpl \n" + " MPU_vTaskSetTimeOutState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskCheckForTimeOutImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskCheckForTimeOut_Unpriv \n" + " MPU_xTaskCheckForTimeOut_Priv: \n" + " b MPU_xTaskCheckForTimeOutImpl \n" + " MPU_xTaskCheckForTimeOut_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotify_Unpriv \n" + " MPU_xTaskGenericNotify_Priv: \n" + " b MPU_xTaskGenericNotifyImpl \n" + " MPU_xTaskGenericNotify_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyWaitImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotifyWait_Unpriv \n" + " MPU_xTaskGenericNotifyWait_Priv: \n" + " b MPU_xTaskGenericNotifyWaitImpl \n" + " MPU_xTaskGenericNotifyWait_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGenericNotifyTakeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGenericNotifyTake_Unpriv \n" + " MPU_ulTaskGenericNotifyTake_Priv: \n" + " b MPU_ulTaskGenericNotifyTakeImpl \n" + " MPU_ulTaskGenericNotifyTake_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyStateClearImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotifyStateClear_Unpriv \n" + " MPU_xTaskGenericNotifyStateClear_Priv: \n" + " b MPU_xTaskGenericNotifyStateClearImpl \n" + " MPU_xTaskGenericNotifyStateClear_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGenericNotifyValueClearImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGenericNotifyValueClear_Unpriv \n" + " MPU_ulTaskGenericNotifyValueClear_Priv: \n" + " b MPU_ulTaskGenericNotifyValueClearImpl \n" + " MPU_ulTaskGenericNotifyValueClear_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGenericSendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGenericSend_Unpriv \n" + " MPU_xQueueGenericSend_Priv: \n" + " b MPU_xQueueGenericSendImpl \n" + " MPU_xQueueGenericSend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxQueueMessagesWaitingImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxQueueMessagesWaiting_Unpriv \n" + " MPU_uxQueueMessagesWaiting_Priv: \n" + " b MPU_uxQueueMessagesWaitingImpl \n" + " MPU_uxQueueMessagesWaiting_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxQueueSpacesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxQueueSpacesAvailable_Unpriv \n" + " MPU_uxQueueSpacesAvailable_Priv: \n" + " b MPU_uxQueueSpacesAvailableImpl \n" + " MPU_uxQueueSpacesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueReceiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueReceive_Unpriv \n" + " MPU_xQueueReceive_Priv: \n" + " b MPU_xQueueReceiveImpl \n" + " MPU_xQueueReceive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueuePeekImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueuePeek_Unpriv \n" + " MPU_xQueuePeek_Priv: \n" + " b MPU_xQueuePeekImpl \n" + " MPU_xQueuePeek_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueSemaphoreTakeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueSemaphoreTake_Unpriv \n" + " MPU_xQueueSemaphoreTake_Priv: \n" + " b MPU_xQueueSemaphoreTakeImpl \n" + " MPU_xQueueSemaphoreTake_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) + + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGetMutexHolderImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGetMutexHolder_Unpriv \n" + " MPU_xQueueGetMutexHolder_Priv: \n" + " b MPU_xQueueGetMutexHolderImpl \n" + " MPU_xQueueGetMutexHolder_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory" + ); + } + + #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueTakeMutexRecursiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueTakeMutexRecursive_Unpriv \n" + " MPU_xQueueTakeMutexRecursive_Priv: \n" + " b MPU_xQueueTakeMutexRecursiveImpl \n" + " MPU_xQueueTakeMutexRecursive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory" + ); + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGiveMutexRecursiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGiveMutexRecursive_Unpriv \n" + " MPU_xQueueGiveMutexRecursive_Priv: \n" + " b MPU_xQueueGiveMutexRecursiveImpl \n" + " MPU_xQueueGiveMutexRecursive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory" + ); + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueSelectFromSetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueSelectFromSet_Unpriv \n" + " MPU_xQueueSelectFromSet_Priv: \n" + " b MPU_xQueueSelectFromSetImpl \n" + " MPU_xQueueSelectFromSet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory" + ); + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueAddToSetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueAddToSet_Unpriv \n" + " MPU_xQueueAddToSet_Priv: \n" + " b MPU_xQueueAddToSetImpl \n" + " MPU_xQueueAddToSet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory" + ); + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vQueueAddToRegistryImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vQueueAddToRegistry_Unpriv \n" + " MPU_vQueueAddToRegistry_Priv: \n" + " b MPU_vQueueAddToRegistryImpl \n" + " MPU_vQueueAddToRegistry_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vQueueUnregisterQueueImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vQueueUnregisterQueue_Unpriv \n" + " MPU_vQueueUnregisterQueue_Priv: \n" + " b MPU_vQueueUnregisterQueueImpl \n" + " MPU_vQueueUnregisterQueue_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pcQueueGetNameImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pcQueueGetName_Unpriv \n" + " MPU_pcQueueGetName_Priv: \n" + " b MPU_pcQueueGetNameImpl \n" + " MPU_pcQueueGetName_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pvTimerGetTimerIDImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pvTimerGetTimerID_Unpriv \n" + " MPU_pvTimerGetTimerID_Priv: \n" + " b MPU_pvTimerGetTimerIDImpl \n" + " MPU_pvTimerGetTimerID_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTimerSetTimerIDImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTimerSetTimerID_Unpriv \n" + " MPU_vTimerSetTimerID_Priv: \n" + " b MPU_vTimerSetTimerIDImpl \n" + " MPU_vTimerSetTimerID_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerIsTimerActiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerIsTimerActive_Unpriv \n" + " MPU_xTimerIsTimerActive_Priv: \n" + " b MPU_xTimerIsTimerActiveImpl \n" + " MPU_xTimerIsTimerActive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv \n" + " MPU_xTimerGetTimerDaemonTaskHandle_Priv: \n" + " b MPU_xTimerGetTimerDaemonTaskHandleImpl \n" + " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGenericCommandFromTaskImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGenericCommandFromTask_Unpriv \n" + " MPU_xTimerGenericCommandFromTask_Priv: \n" + " b MPU_xTimerGenericCommandFromTaskImpl \n" + " MPU_xTimerGenericCommandFromTask_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pcTimerGetNameImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pcTimerGetName_Unpriv \n" + " MPU_pcTimerGetName_Priv: \n" + " b MPU_pcTimerGetNameImpl \n" + " MPU_pcTimerGetName_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTimerSetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTimerSetReloadMode_Unpriv \n" + " MPU_vTimerSetReloadMode_Priv: \n" + " b MPU_vTimerSetReloadModeImpl \n" + " MPU_vTimerSetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetReloadMode_Unpriv \n" + " MPU_xTimerGetReloadMode_Priv: \n" + " b MPU_xTimerGetReloadModeImpl \n" + " MPU_xTimerGetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTimerGetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTimerGetReloadMode_Unpriv \n" + " MPU_uxTimerGetReloadMode_Priv: \n" + " b MPU_uxTimerGetReloadModeImpl \n" + " MPU_uxTimerGetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetPeriodImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetPeriod_Unpriv \n" + " MPU_xTimerGetPeriod_Priv: \n" + " b MPU_xTimerGetPeriodImpl \n" + " MPU_xTimerGetPeriod_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetExpiryTimeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetExpiryTime_Unpriv \n" + " MPU_xTimerGetExpiryTime_Priv: \n" + " b MPU_xTimerGetExpiryTimeImpl \n" + " MPU_xTimerGetExpiryTime_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupWaitBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupWaitBits_Unpriv \n" + " MPU_xEventGroupWaitBits_Priv: \n" + " b MPU_xEventGroupWaitBitsImpl \n" + " MPU_xEventGroupWaitBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupClearBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupClearBits_Unpriv \n" + " MPU_xEventGroupClearBits_Priv: \n" + " b MPU_xEventGroupClearBitsImpl \n" + " MPU_xEventGroupClearBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupSetBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupSetBits_Unpriv \n" + " MPU_xEventGroupSetBits_Priv: \n" + " b MPU_xEventGroupSetBitsImpl \n" + " MPU_xEventGroupSetBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ + +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupSyncImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupSync_Unpriv \n" + " MPU_xEventGroupSync_Priv: \n" + " b MPU_xEventGroupSyncImpl \n" + " MPU_xEventGroupSync_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxEventGroupGetNumberImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxEventGroupGetNumber_Unpriv \n" + " MPU_uxEventGroupGetNumber_Priv: \n" + " b MPU_uxEventGroupGetNumberImpl \n" + " MPU_uxEventGroupGetNumber_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory" + ); + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vEventGroupSetNumberImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vEventGroupSetNumber_Unpriv \n" + " MPU_vEventGroupSetNumber_Priv: \n" + " b MPU_vEventGroupSetNumberImpl \n" + " MPU_vEventGroupSetNumber_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory" + ); + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferSend_Unpriv \n" + " MPU_xStreamBufferSend_Priv: \n" + " b MPU_xStreamBufferSendImpl \n" + " MPU_xStreamBufferSend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferReceiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferReceive_Unpriv \n" + " MPU_xStreamBufferReceive_Priv: \n" + " b MPU_xStreamBufferReceiveImpl \n" + " MPU_xStreamBufferReceive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferIsFullImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferIsFull_Unpriv \n" + " MPU_xStreamBufferIsFull_Priv: \n" + " b MPU_xStreamBufferIsFullImpl \n" + " MPU_xStreamBufferIsFull_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferIsEmptyImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferIsEmpty_Unpriv \n" + " MPU_xStreamBufferIsEmpty_Priv: \n" + " b MPU_xStreamBufferIsEmptyImpl \n" + " MPU_xStreamBufferIsEmpty_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSpacesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferSpacesAvailable_Unpriv \n" + " MPU_xStreamBufferSpacesAvailable_Priv: \n" + " b MPU_xStreamBufferSpacesAvailableImpl \n" + " MPU_xStreamBufferSpacesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferBytesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferBytesAvailable_Unpriv \n" + " MPU_xStreamBufferBytesAvailable_Priv: \n" + " b MPU_xStreamBufferBytesAvailableImpl \n" + " MPU_xStreamBufferBytesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSetTriggerLevelImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferSetTriggerLevel_Unpriv \n" + " MPU_xStreamBufferSetTriggerLevel_Priv: \n" + " b MPU_xStreamBufferSetTriggerLevelImpl \n" + " MPU_xStreamBufferSetTriggerLevel_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferNextMessageLengthBytesImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv \n" + " MPU_xStreamBufferNextMessageLengthBytes_Priv: \n" + " b MPU_xStreamBufferNextMessageLengthBytesImpl \n" + " MPU_xStreamBufferNextMessageLengthBytes_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ diff --git a/portable/GCC/ARM_CM85/non_secure/port.c b/portable/GCC/ARM_CM85/non_secure/port.c new file mode 100644 index 000000000..76d2b2445 --- /dev/null +++ b/portable/GCC/ARM_CM85/non_secure/port.c @@ -0,0 +1,2280 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024-2025 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU includes. */ +#include "mpu_wrappers.h" +#include "mpu_syscall_numbers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration settings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to check the validity of an interrupt priority. + */ +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) ) +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used during system call enter and exit. + */ +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Offsets in the stack to the parameters when inside the SVC handler. + */ +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +#if ( portARMV8M_MINOR_VERSION >= 1 ) + + /* Enable Privileged eXecute Never MPU attribute for the selected memory + * region. */ + #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL ) +#endif /* portARMV8M_MINOR_VERSION >= 1 */ + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Extract first address of the MPU region as encoded in the + * RBAR (Region Base Address Register) value. */ +#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \ + ( ( rbar ) & portMPU_RBAR_ADDRESS_MASK ) + +/* Extract last address of the MPU region as encoded in the + * RLAR (Region Limit Address Register) value. */ +#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \ + ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK ) + +/* Does addr lies within [start, end] address range? */ +#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \ + ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) ) + +/* Is the access request satisfied by the available permissions? */ +#define portIS_AUTHORIZED( accessRequest, permissions ) \ + ( ( ( permissions ) & ( accessRequest ) ) == accessRequest ) + +/* Max value that fits in a uint32_t type. */ +#define portUINT32_MAX ( ~( ( uint32_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. + */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 + +/** + * @brief Constants required to check and configure PACBTI security feature implementation. + */ +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) ) + + #define portCONTROL_UPAC_EN ( 1UL << 7UL ) + #define portCONTROL_PAC_EN ( 1UL << 6UL ) + #define portCONTROL_UBTI_EN ( 1UL << 5UL ) + #define portCONTROL_BTI_EN ( 1UL << 4UL ) + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Extract MPU region's access permissions from the Region Base Address + * Register (RBAR) value. + * + * @param ulRBARValue RBAR value for the MPU region. + * + * @return uint32_t Access permissions. + */ + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + + /** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + /** + * @brief Configures PACBTI features. + * + * This function configures the Pointer Authentication, and Branch Target + * Identification security features as per the user configuration. It returns + * the value of the special purpose CONTROL register accordingly, and optionally + * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M + * architecture based) target supports PACBTI security feature. + * + * @param xWriteControlRegister Used to control whether the special purpose + * CONTROL register should be updated or not. + * + * @return CONTROL register value according to the configured PACBTI option. + */ + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the system call stack so that upon returning from + * SVC, the system call stack is used. + * + * @param pulTaskStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + * @param ucSystemCallNumber The system call number of the system call. + */ + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Raise SVC for exiting from a system call. + */ + void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief This variable is set to pdTRUE when the scheduler is started. + */ + PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + + /** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +/** + * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + /** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + + /** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + + /** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the cpsid instruction + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessPermissions = 0; + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_ONLY ) + { + ulAccessPermissions = tskMPU_READ_PERMISSION; + } + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_WRITE ) + { + ulAccessPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION ); + } + + return ulAccessPermissions; + } + +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } + +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ portOFFSET_TO_PC ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ]; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulSystemCallStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the system call section (i.e. application is + * not raising SVC directly). + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as + * it is non-NULL only during the execution of a system call (i.e. + * between system call enter and exit). + * 3. System call is not for a kernel API disabled by the configuration + * in FreeRTOSConfig.h. + * 4. We do not need to check that ucSystemCallNumber is within range + * because the assembly SVC handler checks that before calling + * this function. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) && + ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) ) + { + pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the system call stack for the stack frame. */ + pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulSystemCallStack[ i ] = pulTaskStack[ i ]; + } + + /* Store the value of the Link Register before the SVC was raised. + * It contains the address of the caller of the System Call entry + * point (i.e. the caller of the MPU_). We need to restore it + * when we exit from the system call. */ + pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; + + /* Store the value of the PSPLIM register before the SVC was raised. + * We need to restore it when we exit from the system call. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* Use the pulSystemCallStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif + + /* Start executing the system call upon returning from this handler. */ + pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; + + /* Raise a request to exit from the system call upon finishing the + * system call. */ + pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; + + /* Remember the location where we should copy the stack frame when we exit from + * the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize; + + /* Record if the hardware used padding to force the stack pointer + * to be double word aligned. */ + if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK ) + { + pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG; + } + else + { + pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG ); + } + + /* We ensure in pxPortInitialiseStack that the system call stack is + * double word aligned and therefore, there is no need of padding. + * Clear the bit[9] of stacked xPSR. */ + pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + + /* Raise the privilege for the duration of the system call. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " bics r0, r1 \n" /* Clear nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */ + { + __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulTaskStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the privileged code (i.e. application is not + * raising SVC directly). This SVC is only raised from + * vRequestSystemCallExit which is in the privileged code section. + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL - + * this means that we previously entered a system call and the + * application is not attempting to exit without entering a system + * call. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) ) + { + pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the task stack for the stack frame. */ + pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulTaskStack[ i ] = pulSystemCallStack[ i ]; + } + + /* Use the pulTaskStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) ); + + /* Return to the caller of the System Call entry point (i.e. the + * caller of the MPU_). */ + pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + /* Ensure that LR has a valid value.*/ + pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + + /* Restore the PSPLIM register to what it was at the time of + * system call entry. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* If the hardware used padding to force the stack pointer + * to be double word aligned, set the stacked xPSR bit[9], + * otherwise clear it. */ + if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG ) + { + pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK; + } + else + { + pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + } + + /* This is not NULL only for the duration of the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; + + /* Drop the privilege before returning to the thread mode. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " orrs r0, r1 \n" /* Set nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xTaskIsPrivileged = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xTaskIsPrivileged = pdTRUE; + } + + return xTaskIsPrivileged; + } + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged, + xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulIndex = 0; + uint32_t ulControl = 0x0; + + xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ + ulIndex++; + + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + ulIndex++; + + #if ( configENABLE_TRUSTZONE == 1 ) + { + xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */ + ulIndex++; + } + #endif /* configENABLE_TRUSTZONE */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + ulIndex++; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Check PACBTI security feature configuration before pushing the + * CONTROL register's value on task's TCB. */ + ulControl = prvConfigurePACBTI( pdFALSE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + if( xRunPrivileged == pdTRUE ) + { + xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + else + { + xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG ); + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ + ulIndex++; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + { + /* Ensure that the system call stack is double word aligned. */ + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) + + ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + /* This is not NULL only for the duration of a system call. */ + xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL; + } + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ]; + ulIndex++; + } + } + #endif /* configENABLE_PAC */ + + return &( xMPUSettings->ulContext[ ulIndex ] ); + } + +#else /* configENABLE_MPU */ + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ + { + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + pxTopOfStack--; + *pxTopOfStack = ulTaskPacKey[ i ]; + } + } + #endif /* configENABLE_PAC */ + + return pxTopOfStack; + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Set the CONTROL register value based on PACBTI security feature + * configuration before starting the first task. */ + ( void ) prvConfigurePACBTI( pdTRUE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + { + xSchedulerRunning = pdTRUE; + } + #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + configSTACK_DEPTH_TYPE uxStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( uxStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* PXN. */ + #if ( portARMV8M_MINOR_VERSION >= 1 ) + { + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ); + } + } + #endif /* portARMV8M_MINOR_VERSION >= 1 */ + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, + uint32_t ulBufferLength, + uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */ + + { + uint32_t i, ulBufferStartAddress, ulBufferEndAddress; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE ) + { + ulBufferStartAddress = ( uint32_t ) pvBuffer; + ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL ); + + for( i = 0; i < portTOTAL_NUM_REGIONS; i++ ) + { + /* Is the MPU region enabled? */ + if( ( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR & portMPU_RLAR_REGION_ENABLE ) == portMPU_RLAR_REGION_ENABLE ) + { + if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_AUTHORIZED( ulAccessRequested, + prvGetRegionAccessPermissions( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ) ) ) + { + xAccessGranted = pdTRUE; + break; + } + } + } + } + } + + return xAccessGranted; + } + +#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings; + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else + { + xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 ) + { + xAccessGranted = pdTRUE; + } + } + } + + return xAccessGranted; + } + + #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + ( void ) lInternalIndexOfKernelObject; + + /* If Access Control List feature is not used, all the tasks have + * access to all the kernel objects. */ + return pdTRUE; + } + + #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + { + uint32_t ulControl = 0x0; + + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); + + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; + + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM85/non_secure/portasm.c b/portable/GCC/ARM_CM85/non_secure/portasm.c new file mode 100644 index 000000000..0ebbe48a4 --- /dev/null +++ b/portable/GCC/ARM_CM85/non_secure/portasm.c @@ -0,0 +1,621 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION + * is defined correctly and privileged functions are placed in correct sections. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Portasm includes. */ +#include "portasm.h" + +/* System call numbers includes. */ +#include "mpu_syscall_numbers.h" + +/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the + * header files. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#if ( configENABLE_MPU == 1 ) + + void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " program_mpu_first_task: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r3] \n" /* r0 = pxCurrentTCB. */ + " \n" + " dmb \n" /* Complete outstanding transfers before disabling MPU. */ + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + " str r2, [r1] \n" /* Disable MPU. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */ + " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r1, [r2] \n" /* Program MAIR0. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " \n" + " movs r3, #4 \n" /* r3 = 4. */ + " str r3, [r1] \n" /* Program RNR = 4. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + " \n" + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " orr r2, #1 \n" /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */ + " str r2, [r1] \n" /* Enable MPU. */ + " dsb \n" /* Force memory writes before continuing. */ + " \n" + " restore_context_first_task: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* r1 = pxCurrentTCB.*/ + " ldr r2, [r1] \n" /* r2 = Location of saved context in TCB. */ + " \n" + " restore_special_regs_first_task: \n" + #if ( configENABLE_PAC == 1 ) + " ldmdb r2!, {r3-r6} \n" /* Read task's dedicated PAC key from the task's context. */ + " msr PAC_KEY_P_0, r3 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_1, r4 \n" + " msr PAC_KEY_P_2, r5 \n" + " msr PAC_KEY_P_3, r6 \n" + " clrm {r3-r6} \n" /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + " ldmdb r2!, {r0, r3-r5, lr} \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */ + " msr psp, r3 \n" + " msr psplim, r4 \n" + " msr control, r5 \n" + " ldr r4, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " str r0, [r4] \n" /* Restore xSecureContext. */ + " \n" + " restore_general_regs_first_task: \n" + " ldmdb r2!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */ + " stmia r3!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */ + " ldmdb r2!, {r4-r11} \n" /* r4-r11 restored. */ + " \n" + " restore_context_done_first_task: \n" + " str r2, [r1] \n" /* Save the location where the context should be saved next as the first member of TCB. */ + " mov r0, #0 \n" + " msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */ + " bx lr \n" + ); + } + +#else /* configENABLE_MPU */ + + void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r3, [r2] \n" /* Read pxCurrentTCB. */ + " ldr r0, [r3] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + " \n" + #if ( configENABLE_PAC == 1 ) + " ldmia r0!, {r1-r4} \n" /* Read task's dedicated PAC key from stack. */ + " msr PAC_KEY_P_3, r1 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_2, r2 \n" + " msr PAC_KEY_P_1, r3 \n" + " msr PAC_KEY_P_0, r4 \n" + " clrm {r1-r4} \n" /* Clear r1-r4. */ + #endif /* configENABLE_PAC */ + " \n" + " ldm r0!, {r1-r3} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */ + " ldr r4, =xSecureContext \n" + " str r1, [r4] \n" /* Set xSecureContext to this task's value for the same. */ + " msr psplim, r2 \n" /* Set this task's PSPLIM value. */ + " mrs r1, control \n" /* Obtain current control register value. */ + " orrs r1, r1, #2 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */ + " msr control, r1 \n" /* Write back the new control register value. */ + " adds r0, #32 \n" /* Discard everything up to r0. */ + " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */ + " isb \n" + " mov r0, #0 \n" + " msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */ + " bx r3 \n" /* Finally, branch to EXC_RETURN. */ + ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* r0 = CONTROL. */ + " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + " ite ne \n" + " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + " bx lr \n" /* Return. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* Read the CONTROL register. */ + " bic r0, #1 \n" /* Clear the bit 0. */ + " msr control, r0 \n" /* Write back the new CONTROL value. */ + " bx lr \n" /* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vResetPrivilege( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* r0 = CONTROL. */ + " orr r0, #1 \n" /* r0 = r0 | 1. */ + " msr control, r0 \n" /* CONTROL = r0. */ + " bx lr \n" /* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r0, =0xe000ed08 \n" /* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */ + " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */ + " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */ + " cpsie i \n" /* Globally enable interrupts. */ + " cpsie f \n" + " dsb \n" + " isb \n" + " svc %0 \n" /* System call to start the first task. */ + " nop \n" + ::"i" ( portSVC_START_SCHEDULER ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, basepri \n" /* r0 = basepri. Return original basepri value. */ + " mov r1, %0 \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r1 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bx lr \n" /* Return. */ + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " msr basepri, r0 \n" /* basepri = ulMask. */ + " dsb \n" + " isb \n" + " bx lr \n" /* Return. */ + ::: "memory" + ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern SecureContext_SaveContext \n" + " .extern SecureContext_LoadContext \n" + " \n" + " ldr r3, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " ldr r0, [r3] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */ + " ldr r2, [r1] \n" /* r2 = Location in TCB where the context should be saved. */ + " \n" + " cbz r0, save_ns_context \n" /* No secure context to save. */ + " save_s_context: \n" + " push {r0-r2, lr} \n" + " bl SecureContext_SaveContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r0-r2, lr} \n" + " \n" + " save_ns_context: \n" + " mov r3, lr \n" /* r3 = LR (EXC_RETURN). */ + " lsls r3, r3, #25 \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bmi save_special_regs \n" /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + " \n" + " save_general_regs: \n" + " mrs r3, psp \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " add r3, r3, #0x20 \n" /* Move r3 to location where s0 is saved. */ + " tst lr, #0x10 \n" + " ittt eq \n" + " vstmiaeq r2!, {s16-s31} \n" /* Store s16-s31. */ + " vldmiaeq r3, {s0-s16} \n" /* Copy hardware saved FP context into s0-s16. */ + " vstmiaeq r2!, {s0-s16} \n" /* Store hardware saved FP context. */ + " sub r3, r3, #0x20 \n" /* Set r3 back to the location of hardware saved context. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " stmia r2!, {r4-r11} \n" /* Store r4-r11. */ + " ldmia r3, {r4-r11} \n" /* Copy the hardware saved context into r4-r11. */ + " stmia r2!, {r4-r11} \n" /* Store the hardware saved context. */ + " \n" + " save_special_regs: \n" + " mrs r3, psp \n" /* r3 = PSP. */ + " mrs r4, psplim \n" /* r4 = PSPLIM. */ + " mrs r5, control \n" /* r5 = CONTROL. */ + " stmia r2!, {r0, r3-r5, lr} \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ + #if ( configENABLE_PAC == 1 ) + " mrs r3, PAC_KEY_P_0 \n" /* Read task's dedicated PAC key from the PAC key registers. */ + " mrs r4, PAC_KEY_P_1 \n" + " mrs r5, PAC_KEY_P_2 \n" + " mrs r6, PAC_KEY_P_3 \n" + " stmia r2!, {r3-r6} \n" /* Store the task's dedicated PAC key on the task's context. */ + " clrm {r3-r6} \n" /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + " str r2, [r1] \n" /* Save the location from where the context should be restored as the first member of TCB. */ + " \n" + " select_next_task: \n" + " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bl vTaskSwitchContext \n" + " mov r0, #0 \n" /* r0 = 0. */ + " msr basepri, r0 \n" /* Enable interrupts. */ + " \n" + " program_mpu: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r3] \n" /* r0 = pxCurrentTCB.*/ + " \n" + " dmb \n" /* Complete outstanding transfers before disabling MPU. */ + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + " str r2, [r1] \n" /* Disable MPU. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */ + " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r1, [r2] \n" /* Program MAIR0. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " \n" + " movs r3, #4 \n" /* r3 = 4. */ + " str r3, [r1] \n" /* Program RNR = 4. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + " \n" + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " orr r2, #1 \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */ + " str r2, [r1] \n" /* Enable MPU. */ + " dsb \n" /* Force memory writes before continuing. */ + " \n" + " restore_context: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* r1 = pxCurrentTCB.*/ + " ldr r2, [r1] \n" /* r2 = Location of saved context in TCB. */ + " \n" + " restore_special_regs: \n" + #if ( configENABLE_PAC == 1 ) + " ldmdb r2!, {r3-r6} \n" /* Read task's dedicated PAC key from the task's context. */ + " msr PAC_KEY_P_0, r3 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_1, r4 \n" + " msr PAC_KEY_P_2, r5 \n" + " msr PAC_KEY_P_3, r6 \n" + " clrm {r3-r6} \n" /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + " ldmdb r2!, {r0, r3-r5, lr} \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */ + " msr psp, r3 \n" + " msr psplim, r4 \n" + " msr control, r5 \n" + " ldr r4, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " str r0, [r4] \n" /* Restore xSecureContext. */ + " cbz r0, restore_ns_context \n" /* No secure context to restore. */ + " \n" + " restore_s_context: \n" + " push {r1-r3, lr} \n" + " bl SecureContext_LoadContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r1-r3, lr} \n" + " \n" + " restore_ns_context: \n" + " mov r0, lr \n" /* r0 = LR (EXC_RETURN). */ + " lsls r0, r0, #25 \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bmi restore_context_done \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + " \n" + " restore_general_regs: \n" + " ldmdb r2!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */ + " stmia r3!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */ + " ldmdb r2!, {r4-r11} \n" /* r4-r11 restored. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" + " ittt eq \n" + " vldmdbeq r2!, {s0-s16} \n" /* s0-s16 contain hardware saved FP context. */ + " vstmiaeq r3!, {s0-s16} \n" /* Copy hardware saved FP context on the task stack. */ + " vldmdbeq r2!, {s16-s31} \n" /* Restore s16-s31. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + " restore_context_done: \n" + " str r2, [r1] \n" /* Save the location where the context should be saved next as the first member of TCB. */ + " bx lr \n" + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); + } + +#else /* configENABLE_MPU */ + + void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern SecureContext_SaveContext \n" + " .extern SecureContext_LoadContext \n" + " \n" + " ldr r3, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " ldr r0, [r3] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */ + " mrs r2, psp \n" /* Read PSP in r2. */ + " \n" + " cbz r0, save_ns_context \n" /* No secure context to save. */ + " save_s_context: \n" + " push {r0-r2, lr} \n" + " bl SecureContext_SaveContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r0-r2, lr} \n" + " \n" + " save_ns_context: \n" + " mov r3, lr \n" /* r3 = LR (EXC_RETURN). */ + " lsls r3, r3, #25 \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bmi save_special_regs \n" /* If r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used. */ + " \n" + " save_general_regs: \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vstmdbeq r2!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " stmdb r2!, {r4-r11} \n" /* Store the registers that are not saved automatically. */ + " \n" + " save_special_regs: \n" + " mrs r3, psplim \n" /* r3 = PSPLIM. */ + " stmdb r2!, {r0, r3, lr} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */ + #if ( configENABLE_PAC == 1 ) + " mrs r3, PAC_KEY_P_3 \n" /* Read task's dedicated PAC key from the PAC key registers. */ + " mrs r4, PAC_KEY_P_2 \n" + " mrs r5, PAC_KEY_P_1 \n" + " mrs r6, PAC_KEY_P_0 \n" + " stmdb r2!, {r3-r6} \n" /* Store the task's dedicated PAC key on the stack. */ + " clrm {r3-r6} \n" /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + " \n" + " str r2, [r1] \n" /* Save the new top of stack in TCB. */ + " \n" + " select_next_task: \n" + " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bl vTaskSwitchContext \n" + " mov r0, #0 \n" /* r0 = 0. */ + " msr basepri, r0 \n" /* Enable interrupts. */ + " \n" + " restore_context: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* Read pxCurrentTCB. */ + " ldr r2, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */ + " \n" + " restore_special_regs: \n" + #if ( configENABLE_PAC == 1 ) + " ldmia r2!, {r3-r6} \n" /* Read task's dedicated PAC key from stack. */ + " msr PAC_KEY_P_3, r3 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_2, r4 \n" + " msr PAC_KEY_P_1, r5 \n" + " msr PAC_KEY_P_0, r6 \n" + " clrm {r3-r6} \n" /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + " ldmia r2!, {r0, r3, lr} \n" /* Read from stack - r0 = xSecureContext, r3 = PSPLIM and LR restored. */ + " msr psplim, r3 \n" /* Restore the PSPLIM register value for the task. */ + " ldr r3, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " str r0, [r3] \n" /* Restore the task's xSecureContext. */ + " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */ + " \n" + " restore_s_context: \n" + " push {r1-r3, lr} \n" + " bl SecureContext_LoadContext \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r1-r3, lr} \n" + " \n" + " restore_ns_context: \n" + " mov r0, lr \n" /* r0 = LR (EXC_RETURN). */ + " lsls r0, r0, #25 \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bmi restore_context_done \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + " \n" + " restore_general_regs: \n" + " ldmia r2!, {r4-r11} \n" /* Restore the registers that are not automatically restored. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vldmiaeq r2!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + " restore_context_done: \n" + " msr psp, r2 \n" /* Remember the new top of stack for the task. */ + " bx lr \n" + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + ".syntax unified \n" + ".extern vPortSVCHandler_C \n" + ".extern vSystemCallEnter \n" + ".extern vSystemCallExit \n" + " \n" + "tst lr, #4 \n" + "ite eq \n" + "mrseq r0, msp \n" + "mrsne r0, psp \n" + " \n" + "ldr r1, [r0, #24] \n" + "ldrb r2, [r1, #-2] \n" + "cmp r2, %0 \n" + "blt syscall_enter \n" + "cmp r2, %1 \n" + "beq syscall_exit \n" + "b vPortSVCHandler_C \n" + " \n" + "syscall_enter: \n" + " mov r1, lr \n" + " b vSystemCallEnter \n" + " \n" + "syscall_exit: \n" + " mov r1, lr \n" + " b vSystemCallExit \n" + " \n" + : /* No outputs. */ + : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT ) + : "r0", "r1", "r2", "memory" + ); + } + +#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " tst lr, #4 \n" + " ite eq \n" + " mrseq r0, msp \n" + " mrsne r0, psp \n" + " ldr r1, =vPortSVCHandler_C \n" + " bx r1 \n" + ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " svc %0 \n" /* Secure context is allocated in the supervisor call. */ + " bx lr \n" /* Return. */ + ::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, [r0] \n" /* The first item in the TCB is the top of the stack. */ + " ldr r1, [r2] \n" /* The first item on the stack is the task's xSecureContext. */ + " cmp r1, #0 \n" /* Raise svc if task's xSecureContext is not NULL. */ + " it ne \n" + " svcne %0 \n" /* Secure context is freed in the supervisor call. */ + " bx lr \n" /* Return. */ + ::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory" + ); +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM85/non_secure/portasm.h b/portable/GCC/ARM_CM85/non_secure/portasm.h new file mode 100644 index 000000000..b7021b024 --- /dev/null +++ b/portable/GCC/ARM_CM85/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kernel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/portable/GCC/ARM_CM85/non_secure/portmacro.h b/portable/GCC/ARM_CM85/non_secure/portmacro.h new file mode 100644 index 000000000..7e14f2696 --- /dev/null +++ b/portable/GCC/ARM_CM85/non_secure/portmacro.h @@ -0,0 +1,79 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_MVE + #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE. +#endif /* configENABLE_MVE */ +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M85" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portARMV8M_MINOR_VERSION 1 +#define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h new file mode 100644 index 000000000..f373bcad5 --- /dev/null +++ b/portable/GCC/ARM_CM85/non_secure/portmacrocommon.h @@ -0,0 +1,582 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACROCOMMON_H +#define PORTMACROCOMMON_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. +#endif /* configENABLE_FPU */ + +#ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. +#endif /* configENABLE_MPU */ + +#ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. +#endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() +#define portINLINE __inline +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif +#define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ +extern BaseType_t xPortIsInsideInterrupt( void ); + +extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + +extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; +extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + +extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; +extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + +#if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_PAC == 1 ) + + /** + * @brief Generates 128-bit task's random PAC key. + * + * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be + * filled with a 128-bit random number. + */ + void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); + +#endif /* configENABLE_PAC */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ +#if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) +#else + #define portPRIVILEGE_BIT ( 0x0UL ) +#endif /* configENABLE_MPU */ + +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ +#define portPRIVILEGED_FLASH_REGION ( 0UL ) +#define portUNPRIVILEGED_FLASH_REGION ( 1UL ) +#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) +#define portPRIVILEGED_RAM_REGION ( 3UL ) +#define portSTACK_REGION ( 4UL ) +#define portFIRST_CONFIGURABLE_REGION ( 5UL ) +#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) +#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) +#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ +#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ +#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ +#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ +#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ +#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ +#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ +#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) +#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) +#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + +#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) +#define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) +#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) +#define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + +#define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + #ifndef configSYSTEM_CALL_STACK_SIZE + #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. + #endif + + /** + * @brief System call stack. + */ + typedef struct SYSTEM_CALL_STACK_INFO + { + uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; + uint32_t * pulSystemCallStack; + uint32_t * pulSystemCallStackLimit; + uint32_t * pulTaskStack; + uint32_t ulLinkRegisterAtSystemCallEntry; + uint32_t ulStackLimitRegisterAtSystemCallEntry; + } xSYSTEM_CALL_STACK_INFO; + + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + /** + * @brief MPU settings as stored in the TCB. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><-----------><----> + * 16 17 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 71 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 17 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 55 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | | | PC, xPSR | EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><-----------><----> + * 16 17 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 70 + + #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + /* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 17 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 54 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+------------------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +----------+-----------------+------------------------------+------------+-----+ + * + * <---------><----------------><------------------------------><-----------><----> + * 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 38 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+----------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | PC, xPSR | EXC_RETURN | | | + * +----------+-----------------+----------------------+------------+-----+ + * + * <---------><----------------><----------------------><-----------><----> + * 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 37 + + #else /* #if( configENABLE_TRUSTZONE == 1 ) */ + + /* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) + + /* Size of an Access Control List (ACL) entry in bits. */ + #define portACL_ENTRY_SIZE_BITS ( 32U ) + + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + uint32_t ulContext[ MAX_CONTEXT_SIZE ]; + uint32_t ulTaskFlags; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo; + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ]; + #endif + #endif + } xMPU_SETTINGS; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Validate priority of ISRs that are allowed to call FreeRTOS + * system calls. + */ +#if ( configASSERT_DEFINED == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif +#endif + +/** + * @brief SVC numbers. + */ +#define portSVC_ALLOCATE_SECURE_CONTEXT 100 +#define portSVC_FREE_SECURE_CONTEXT 101 +#define portSVC_START_SCHEDULER 102 +#define portSVC_RAISE_PRIVILEGE 103 +#define portSVC_SYSTEM_CALL_EXIT 104 +#define portSVC_YIELD 105 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) +#endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() +#else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + extern BaseType_t xPortIsTaskPrivileged( void ); + +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACROCOMMON_H */ diff --git a/portable/GCC/ARM_CM85/secure/secure_context.c b/portable/GCC/ARM_CM85/secure/secure_context.c new file mode 100644 index 000000000..3aa335e63 --- /dev/null +++ b/portable/GCC/ARM_CM85/secure/secure_context.c @@ -0,0 +1,354 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Secure context includes. */ +#include "secure_context.h" + +/* Secure heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief CONTROL value for privileged tasks. + * + * Bit[0] - 0 --> Thread mode is privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_PRIVILEGED 0x02 + +/** + * @brief CONTROL value for un-privileged tasks. + * + * Bit[0] - 1 --> Thread mode is un-privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03 + +/** + * @brief Size of stack seal values in bytes. + */ +#define securecontextSTACK_SEAL_SIZE 8 + +/** + * @brief Stack seal value as recommended by ARM. + */ +#define securecontextSTACK_SEAL_VALUE 0xFEF5EDA5 + +/** + * @brief Maximum number of secure contexts. + */ +#ifndef secureconfigMAX_SECURE_CONTEXTS + #define secureconfigMAX_SECURE_CONTEXTS 8UL +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Pre-allocated array of secure contexts. + */ +SecureContext_t xSecureContexts[ secureconfigMAX_SECURE_CONTEXTS ]; +/*-----------------------------------------------------------*/ + +/** + * @brief Get a free secure context for a task from the secure context pool (xSecureContexts). + * + * This function ensures that only one secure context is allocated for a task. + * + * @param[in] pvTaskHandle The task handle for which the secure context is allocated. + * + * @return Index of a free secure context in the xSecureContexts array. + */ +static uint32_t ulGetSecureContext( void * pvTaskHandle ); + +/** + * @brief Return the secure context to the secure context pool (xSecureContexts). + * + * @param[in] ulSecureContextIndex Index of the context in the xSecureContexts array. + */ +static void vReturnSecureContext( uint32_t ulSecureContextIndex ); + +/* These are implemented in assembly. */ +extern void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ); +extern void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ); +/*-----------------------------------------------------------*/ + +static uint32_t ulGetSecureContext( void * pvTaskHandle ) +{ + /* Start with invalid index. */ + uint32_t i, ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + if( ( xSecureContexts[ i ].pucCurrentStackPointer == NULL ) && + ( xSecureContexts[ i ].pucStackLimit == NULL ) && + ( xSecureContexts[ i ].pucStackStart == NULL ) && + ( xSecureContexts[ i ].pvTaskHandle == NULL ) && + ( ulSecureContextIndex == secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = i; + } + else if( xSecureContexts[ i ].pvTaskHandle == pvTaskHandle ) + { + /* A task can only have one secure context. Do not allocate a second + * context for the same task. */ + ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + break; + } + } + + return ulSecureContextIndex; +} +/*-----------------------------------------------------------*/ + +static void vReturnSecureContext( uint32_t ulSecureContextIndex ) +{ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackStart = NULL; + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = NULL; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) +{ + uint32_t ulIPSR, i; + static uint32_t ulSecureContextsInitialized = 0; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ( ulIPSR != 0 ) && ( ulSecureContextsInitialized == 0 ) ) + { + /* Ensure to initialize secure contexts only once. */ + ulSecureContextsInitialized = 1; + + /* No stack for thread mode until a task's context is loaded. */ + secureportSET_PSPLIM( securecontextNO_STACK ); + secureportSET_PSP( securecontextNO_STACK ); + + /* Initialize all secure contexts. */ + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + xSecureContexts[ i ].pucCurrentStackPointer = NULL; + xSecureContexts[ i ].pucStackLimit = NULL; + xSecureContexts[ i ].pucStackStart = NULL; + xSecureContexts[ i ].pvTaskHandle = NULL; + } + + #if ( configENABLE_MPU == 1 ) + { + /* Configure thread mode to use PSP and to be unprivileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); + } + #else /* configENABLE_MPU */ + { + /* Configure thread mode to use PSP and to be privileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); + } + #endif /* configENABLE_MPU */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ) +#else /* configENABLE_MPU */ + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ) +#endif /* configENABLE_MPU */ +{ + uint8_t * pucStackMemory = NULL; + uint8_t * pucStackLimit; + uint32_t ulIPSR, ulSecureContextIndex; + SecureContextHandle_t xSecureContextHandle = securecontextINVALID_CONTEXT_ID; + + #if ( configENABLE_MPU == 1 ) + uint32_t * pulCurrentStackPointer = NULL; + #endif /* configENABLE_MPU */ + + /* Read the Interrupt Program Status Register (IPSR) and Process Stack Limit + * Register (PSPLIM) value. */ + secureportREAD_IPSR( ulIPSR ); + secureportREAD_PSPLIM( pucStackLimit ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. + * Also do nothing, if a secure context us already loaded. PSPLIM is set to + * securecontextNO_STACK when no secure context is loaded. */ + if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) ) + { + /* Obtain a free secure context. */ + ulSecureContextIndex = ulGetSecureContext( pvTaskHandle ); + + /* Were we able to get a free context? */ + if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS ) + { + /* Allocate the stack space. */ + pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + + if( pucStackMemory != NULL ) + { + /* Since stack grows down, the starting point will be the last + * location. Note that this location is next to the last + * allocated byte for stack (excluding the space for seal values) + * because the hardware decrements the stack pointer before + * writing i.e. if stack pointer is 0x2, a push operation will + * decrement the stack pointer to 0x1 and then write at 0x1. */ + xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize; + + /* Seal the created secure process stack. */ + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; + + /* The stack cannot go beyond this location. This value is + * programmed in the PSPLIM register on context switch.*/ + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = pucStackMemory; + + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle; + + #if ( configENABLE_MPU == 1 ) + { + /* Store the correct CONTROL value for the task on the stack. + * This value is programmed in the CONTROL register on + * context switch. */ + pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; + pulCurrentStackPointer--; + + if( ulIsTaskPrivileged ) + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; + } + else + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; + } + + /* Store the current stack pointer. This value is programmed in + * the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + } + #else /* configENABLE_MPU */ + { + /* Current SP is set to the starting of the stack. This + * value programmed in the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + } + #endif /* configENABLE_MPU */ + + /* Ensure to never return 0 as a valid context handle. */ + xSecureContextHandle = ulSecureContextIndex + 1UL; + } + } + } + + return xSecureContextHandle; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) +{ + uint32_t ulIPSR, ulSecureContextIndex; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* Only free if a valid context handle is passed. */ + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + /* Ensure that the secure context being deleted is associated with + * the task. */ + if( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) + { + /* Free the stack space. */ + vPortFree( xSecureContexts[ ulSecureContextIndex ].pucStackLimit ); + + /* Return the secure context back to the free secure contexts pool. */ + vReturnSecureContext( ulSecureContextIndex ); + } + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that no secure context is loaded and the task is loading it's + * own context. */ + if( ( pucStackLimit == securecontextNO_STACK ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_LoadContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that task's context is loaded and the task is saving it's own + * context. */ + if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_SaveContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM85/secure/secure_context.h b/portable/GCC/ARM_CM85/secure/secure_context.h new file mode 100644 index 000000000..e36a8e430 --- /dev/null +++ b/portable/GCC/ARM_CM85/secure/secure_context.h @@ -0,0 +1,138 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_CONTEXT_H__ +#define __SECURE_CONTEXT_H__ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" + +/** + * @brief PSP value when no secure context is loaded. + */ +#define securecontextNO_STACK 0x0 + +/** + * @brief Invalid context ID. + */ +#define securecontextINVALID_CONTEXT_ID 0UL +/*-----------------------------------------------------------*/ + +/** + * @brief Structure to represent a secure context. + * + * @note Since stack grows down, pucStackStart is the highest address while + * pucStackLimit is the first address of the allocated memory. + */ +typedef struct SecureContext +{ + uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */ + uint8_t * pucStackLimit; /**< Last location of the stack memory (PSPLIM). */ + uint8_t * pucStackStart; /**< First location of the stack memory. */ + void * pvTaskHandle; /**< Task handle of the task this context is associated with. */ +} SecureContext_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Opaque handle for a secure context. + */ +typedef uint32_t SecureContextHandle_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Initializes the secure context management system. + * + * PSP is set to NULL and therefore a task must allocate and load a context + * before calling any secure side function in the thread mode. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureContext_Init( void ); + +/** + * @brief Allocates a context on the secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] ulSecureStackSize Size of the stack to allocate on secure side. + * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise. + * + * @return Opaque context handle if context is successfully allocated, NULL + * otherwise. + */ +#if ( configENABLE_MPU == 1 ) + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ); +#else /* configENABLE_MPU */ + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ); +#endif /* configENABLE_MPU */ + +/** + * @brief Frees the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the + * context to be freed. + */ +void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); + +/** + * @brief Loads the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be loaded. + */ +void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); + +/** + * @brief Saves the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be saved. + */ +void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); + +#endif /* __SECURE_CONTEXT_H__ */ diff --git a/portable/GCC/ARM_CM85/secure/secure_context_port.c b/portable/GCC/ARM_CM85/secure/secure_context_port.c new file mode 100644 index 000000000..2d3d9439d --- /dev/null +++ b/portable/GCC/ARM_CM85/secure/secure_context_port.c @@ -0,0 +1,97 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Secure context includes. */ +#include "secure_context.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) ); +void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) ); + +void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) +{ + /* pxSecureContext value is in r0. */ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r1, ipsr \n" /* r1 = IPSR. */ + " cbz r1, load_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */ + " ldmia r0!, {r1, r2} \n" /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */ + " \n" + #if ( configENABLE_MPU == 1 ) + " ldmia r1!, {r3} \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */ + " msr control, r3 \n" /* CONTROL = r3. */ + #endif /* configENABLE_MPU */ + " \n" + " msr psplim, r2 \n" /* PSPLIM = r2. */ + " msr psp, r1 \n" /* PSP = r1. */ + " \n" + " load_ctx_therad_mode: \n" + " bx lr \n" + " \n" + ::: "r0", "r1", "r2" + ); +} +/*-----------------------------------------------------------*/ + +void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) +{ + /* pxSecureContext value is in r0. */ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r1, ipsr \n" /* r1 = IPSR. */ + " cbz r1, save_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */ + " mrs r1, psp \n" /* r1 = PSP. */ + " \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " vstmdb r1!, {s0} \n" /* Trigger the deferred stacking of FPU registers. */ + " vldmia r1!, {s0} \n" /* Nullify the effect of the previous statement. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + #if ( configENABLE_MPU == 1 ) + " mrs r2, control \n" /* r2 = CONTROL. */ + " stmdb r1!, {r2} \n" /* Store CONTROL value on the stack. */ + #endif /* configENABLE_MPU */ + " \n" + " str r1, [r0] \n" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */ + " movs r1, %0 \n" /* r1 = securecontextNO_STACK. */ + " msr psplim, r1 \n" /* PSPLIM = securecontextNO_STACK. */ + " msr psp, r1 \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */ + " \n" + " save_ctx_therad_mode: \n" + " bx lr \n" + " \n" + ::"i" ( securecontextNO_STACK ) : "r1", "memory" + ); +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM85/secure/secure_heap.c b/portable/GCC/ARM_CM85/secure/secure_heap.c new file mode 100644 index 000000000..896b53e2d --- /dev/null +++ b/portable/GCC/ARM_CM85/secure/secure_heap.c @@ -0,0 +1,485 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Configuration includes. */ +#include "FreeRTOSConfig.h" + +/* Secure context heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Total heap size. + */ +#ifndef secureconfigTOTAL_HEAP_SIZE + #define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) ) +#endif + +/* No test marker by default. */ +#ifndef mtCOVERAGE_TEST_MARKER + #define mtCOVERAGE_TEST_MARKER() +#endif + +/* No tracing by default. */ +#ifndef traceMALLOC + #define traceMALLOC( pvReturn, xWantedSize ) +#endif + +/* No tracing by default. */ +#ifndef traceFREE + #define traceFREE( pv, xBlockSize ) +#endif + +/* Block sizes must not get too small. */ +#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) ) + +/* Assumes 8bit bytes! */ +#define secureheapBITS_PER_BYTE ( ( size_t ) 8 ) + +/* Max value that fits in a size_t type. */ +#define secureheapSIZE_MAX ( ~( ( size_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define secureheapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) ) + +/* MSB of the xBlockSize member of an BlockLink_t structure is used to track + * the allocation status of a block. When MSB of the xBlockSize member of + * an BlockLink_t structure is set then the block belongs to the application. + * When the bit is free the block is still part of the free heap space. */ +#define secureheapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) ) +#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 ) +#define secureheapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 ) +#define secureheapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK ) +#define secureheapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK ) +/*-----------------------------------------------------------*/ + +/* Allocate the memory for the heap. */ +#if ( configAPPLICATION_ALLOCATED_HEAP == 1 ) + +/* The application writer has already defined the array used for the RTOS +* heap - probably so it can be placed in a special segment or address. */ + extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#else /* configAPPLICATION_ALLOCATED_HEAP */ + static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#endif /* configAPPLICATION_ALLOCATED_HEAP */ + +/** + * @brief The linked list structure. + * + * This is used to link free blocks in order of their memory address. + */ +typedef struct A_BLOCK_LINK +{ + struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */ + size_t xBlockSize; /**< The size of the free block. */ +} BlockLink_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Called automatically to setup the required heap structures the first + * time pvPortMalloc() is called. + */ +static void prvHeapInit( void ); + +/** + * @brief Inserts a block of memory that is being freed into the correct + * position in the list of free memory blocks. + * + * The block being freed will be merged with the block in front it and/or the + * block behind it if the memory blocks are adjacent to each other. + * + * @param[in] pxBlockToInsert The block being freed. + */ +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ); +/*-----------------------------------------------------------*/ + +/** + * @brief The size of the structure placed at the beginning of each allocated + * memory block must by correctly byte aligned. + */ +static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + +/** + * @brief Create a couple of list links to mark the start and end of the list. + */ +static BlockLink_t xStart; +static BlockLink_t * pxEnd = NULL; + +/** + * @brief Keeps track of the number of free bytes remaining, but says nothing + * about fragmentation. + */ +static size_t xFreeBytesRemaining = 0U; +static size_t xMinimumEverFreeBytesRemaining = 0U; + +/*-----------------------------------------------------------*/ + +static void prvHeapInit( void ) +{ + BlockLink_t * pxFirstFreeBlock; + uint8_t * pucAlignedHeap; + size_t uxAddress; + size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE; + + /* Ensure the heap starts on a correctly aligned boundary. */ + uxAddress = ( size_t ) ucHeap; + + if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 ) + { + uxAddress += ( secureportBYTE_ALIGNMENT - 1 ); + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; + } + + pucAlignedHeap = ( uint8_t * ) uxAddress; + + /* xStart is used to hold a pointer to the first item in the list of free + * blocks. The void cast is used to prevent compiler warnings. */ + xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; + xStart.xBlockSize = ( size_t ) 0; + + /* pxEnd is used to mark the end of the list of free blocks and is inserted + * at the end of the heap space. */ + uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; + uxAddress -= xHeapStructSize; + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + pxEnd = ( void * ) uxAddress; + pxEnd->xBlockSize = 0; + pxEnd->pxNextFreeBlock = NULL; + + /* To start with there is a single free block that is sized to take up the + * entire heap space, minus the space taken by pxEnd. */ + pxFirstFreeBlock = ( void * ) pucAlignedHeap; + pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; + pxFirstFreeBlock->pxNextFreeBlock = pxEnd; + + /* Only one block exists - and it covers the entire usable heap space. */ + xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; +} +/*-----------------------------------------------------------*/ + +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) +{ + BlockLink_t * pxIterator; + uint8_t * puc; + + /* Iterate through the list until a block is found that has a higher address + * than the block being inserted. */ + for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) + { + /* Nothing to do here, just iterate to the right position. */ + } + + /* Do the block being inserted, and the block it is being inserted after + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxIterator; + + if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) + { + pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; + pxBlockToInsert = pxIterator; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Do the block being inserted, and the block it is being inserted before + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxBlockToInsert; + + if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) + { + if( pxIterator->pxNextFreeBlock != pxEnd ) + { + /* Form one big block from the two blocks. */ + pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxEnd; + } + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; + } + + /* If the block being inserted plugged a gap, so was merged with the block + * before and the block after, then it's pxNextFreeBlock pointer will have + * already been set, and should not be set here as that would make it point + * to itself. */ + if( pxIterator != pxBlockToInsert ) + { + pxIterator->pxNextFreeBlock = pxBlockToInsert; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} +/*-----------------------------------------------------------*/ + +void * pvPortMalloc( size_t xWantedSize ) +{ + BlockLink_t * pxBlock; + BlockLink_t * pxPreviousBlock; + BlockLink_t * pxNewBlockLink; + void * pvReturn = NULL; + size_t xAdditionalRequiredSize; + size_t xAllocatedBlockSize = 0; + + /* If this is the first call to malloc then the heap will require + * initialisation to setup the list of free blocks. */ + if( pxEnd == NULL ) + { + prvHeapInit(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xWantedSize > 0 ) + { + /* The wanted size must be increased so it can contain a BlockLink_t + * structure in addition to the requested amount of bytes. */ + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 ) + { + xWantedSize += xHeapStructSize; + + /* Ensure that blocks are always aligned to the required number + * of bytes. */ + if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 ) + { + /* Byte alignment required. */ + xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ); + + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 ) + { + xWantedSize += xAdditionalRequiredSize; + } + else + { + xWantedSize = 0; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + xWantedSize = 0; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Check the requested block size is not so large that the top bit is set. + * The top bit of the block size member of the BlockLink_t structure is used + * to determine who owns the block - the application or the kernel, so it + * must be free. */ + if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 ) + { + if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) + { + /* Traverse the list from the start (lowest address) block until + * one of adequate size is found. */ + pxPreviousBlock = &xStart; + pxBlock = xStart.pxNextFreeBlock; + + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + { + pxPreviousBlock = pxBlock; + pxBlock = pxBlock->pxNextFreeBlock; + } + + /* If the end marker was reached then a block of adequate size was + * not found. */ + if( pxBlock != pxEnd ) + { + /* Return the memory space pointed to - jumping over the + * BlockLink_t structure at its start. */ + pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); + + /* This block is being returned for use so must be taken out + * of the list of free blocks. */ + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + + /* If the block is larger than required it can be split into + * two. */ + if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE ) + { + /* This block is to be split into two. Create a new + * block following the number of bytes requested. The void + * cast is used to prevent byte alignment warnings from the + * compiler. */ + pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); + secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + + /* Calculate the sizes of two blocks split from the single + * block. */ + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + pxBlock->xBlockSize = xWantedSize; + + /* Insert the new block into the list of free blocks. */ + pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock; + pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xFreeBytesRemaining -= pxBlock->xBlockSize; + + if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) + { + xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xAllocatedBlockSize = pxBlock->xBlockSize; + + /* The block is being returned - it is allocated and owned by + * the application and has no "next" block. */ + secureheapALLOCATE_BLOCK( pxBlock ); + pxBlock->pxNextFreeBlock = NULL; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceMALLOC( pvReturn, xAllocatedBlockSize ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xAllocatedBlockSize; + + #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) + { + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */ + + secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 ); + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void * pv ) +{ + uint8_t * puc = ( uint8_t * ) pv; + BlockLink_t * pxLink; + + if( pv != NULL ) + { + /* The memory being freed will have an BlockLink_t structure immediately + * before it. */ + puc -= xHeapStructSize; + + /* This casting is to keep the compiler from issuing warnings. */ + pxLink = ( void * ) puc; + + /* Check the block is actually allocated. */ + secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ); + secureportASSERT( pxLink->pxNextFreeBlock == NULL ); + + if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ) + { + if( pxLink->pxNextFreeBlock == NULL ) + { + /* The block is being returned to the heap - it is no longer + * allocated. */ + secureheapFREE_BLOCK( pxLink ); + + secureportDISABLE_NON_SECURE_INTERRUPTS(); + { + /* Add this block to the list of free blocks. */ + xFreeBytesRemaining += pxLink->xBlockSize; + traceFREE( pv, pxLink->xBlockSize ); + prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); + } + secureportENABLE_NON_SECURE_INTERRUPTS(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } +} +/*-----------------------------------------------------------*/ + +size_t xPortGetFreeHeapSize( void ) +{ + return xFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +size_t xPortGetMinimumEverFreeHeapSize( void ) +{ + return xMinimumEverFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM85/secure/secure_heap.h b/portable/GCC/ARM_CM85/secure/secure_heap.h new file mode 100644 index 000000000..0e84a9d9d --- /dev/null +++ b/portable/GCC/ARM_CM85/secure/secure_heap.h @@ -0,0 +1,66 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_HEAP_H__ +#define __SECURE_HEAP_H__ + +/* Standard includes. */ +#include + +/** + * @brief Allocates memory from heap. + * + * @param[in] xWantedSize The size of the memory to be allocated. + * + * @return Pointer to the memory region if the allocation is successful, NULL + * otherwise. + */ +void * pvPortMalloc( size_t xWantedSize ); + +/** + * @brief Frees the previously allocated memory. + * + * @param[in] pv Pointer to the memory to be freed. + */ +void vPortFree( void * pv ); + +/** + * @brief Get the free heap size. + * + * @return Free heap size. + */ +size_t xPortGetFreeHeapSize( void ); + +/** + * @brief Get the minimum ever free heap size. + * + * @return Minimum ever free heap size. + */ +size_t xPortGetMinimumEverFreeHeapSize( void ); + +#endif /* __SECURE_HEAP_H__ */ diff --git a/portable/GCC/ARM_CM85/secure/secure_init.c b/portable/GCC/ARM_CM85/secure/secure_init.c new file mode 100644 index 000000000..c50d37668 --- /dev/null +++ b/portable/GCC/ARM_CM85/secure/secure_init.c @@ -0,0 +1,106 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Secure init includes. */ +#include "secure_init.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Constants required to manipulate the SCB. + */ +#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */ +#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL ) +#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS ) +#define secureinitSCB_AIRCR_PRIS_POS ( 14UL ) +#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS ) + +/** + * @brief Constants required to manipulate the FPU. + */ +#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define secureinitFPCCR_LSPENS_POS ( 29UL ) +#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS ) +#define secureinitFPCCR_TS_POS ( 26UL ) +#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS ) + +#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */ +#define secureinitNSACR_CP10_POS ( 10UL ) +#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS ) +#define secureinitNSACR_CP11_POS ( 11UL ) +#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS ) +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) | + ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) | + ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK ); + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is + * permitted. CP11 should be programmed to the same value as CP10. */ + *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK ); + + /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures + * that we can enable/disable lazy stacking in port.c file. */ + *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK ); + + /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP + * registers (S16-S31) are also pushed to stack on exception entry and + * restored on exception return. */ + *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK ); + } +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM85/secure/secure_init.h b/portable/GCC/ARM_CM85/secure/secure_init.h new file mode 100644 index 000000000..ebe04900f --- /dev/null +++ b/portable/GCC/ARM_CM85/secure/secure_init.h @@ -0,0 +1,54 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_INIT_H__ +#define __SECURE_INIT_H__ + +/** + * @brief De-prioritizes the non-secure exceptions. + * + * This is needed to ensure that the non-secure PendSV runs at the lowest + * priority. Context switch is done in the non-secure PendSV handler. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_DePrioritizeNSExceptions( void ); + +/** + * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access. + * + * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point + * Registers are not leaked to the non-secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_EnableNSFPUAccess( void ); + +#endif /* __SECURE_INIT_H__ */ diff --git a/portable/GCC/ARM_CM85/secure/secure_port_macros.h b/portable/GCC/ARM_CM85/secure/secure_port_macros.h new file mode 100644 index 000000000..a70da2c65 --- /dev/null +++ b/portable/GCC/ARM_CM85/secure/secure_port_macros.h @@ -0,0 +1,140 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_PORT_MACROS_H__ +#define __SECURE_PORT_MACROS_H__ + +/** + * @brief Byte alignment requirements. + */ +#define secureportBYTE_ALIGNMENT 8 +#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 ) + +/** + * @brief Macro to declare a function as non-secure callable. + */ +#if defined( __IAR_SYSTEMS_ICC__ ) + #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry __root +#else + #define secureportNON_SECURE_CALLABLE __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) ) +#endif + +/** + * @brief Set the secure PRIMASK value. + */ +#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Set the non-secure PRIMASK value. + */ +#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Read the PSP value in the given variable. + */ +#define secureportREAD_PSP( pucOutCurrentStackPointer ) \ + __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) ) + +/** + * @brief Set the PSP to the given value. + */ +#define secureportSET_PSP( pucCurrentStackPointer ) \ + __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) ) + +/** + * @brief Read the PSPLIM value in the given variable. + */ +#define secureportREAD_PSPLIM( pucOutStackLimit ) \ + __asm volatile ( "mrs %0, psplim" : "=r" ( pucOutStackLimit ) ) + +/** + * @brief Set the PSPLIM to the given value. + */ +#define secureportSET_PSPLIM( pucStackLimit ) \ + __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) ) + +/** + * @brief Set the NonSecure MSP to the given value. + */ +#define secureportSET_MSP_NS( pucMainStackPointer ) \ + __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) ) + +/** + * @brief Set the CONTROL register to the given value. + */ +#define secureportSET_CONTROL( ulControl ) \ + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" ) + +/** + * @brief Read the Interrupt Program Status Register (IPSR) value in the given + * variable. + */ +#define secureportREAD_IPSR( ulIPSR ) \ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) ) + +/** + * @brief PRIMASK value to enable interrupts. + */ +#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0 + +/** + * @brief PRIMASK value to disable interrupts. + */ +#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1 + +/** + * @brief Disable secure interrupts. + */ +#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Disable non-secure interrupts. + * + * This effectively disables context switches. + */ +#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Enable non-secure interrupts. + */ +#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL ) + +/** + * @brief Assert definition. + */ +#define secureportASSERT( x ) \ + if( ( x ) == 0 ) \ + { \ + secureportDISABLE_SECURE_INTERRUPTS(); \ + secureportDISABLE_NON_SECURE_INTERRUPTS(); \ + for( ; ; ) {; } \ + } + +#endif /* __SECURE_PORT_MACROS_H__ */ diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c new file mode 100644 index 000000000..4b984932d --- /dev/null +++ b/portable/GCC/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.c @@ -0,0 +1,2055 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" +#include "event_groups.h" +#include "stream_buffer.h" +#include "mpu_prototypes.h" +#include "mpu_syscall_numbers.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( INCLUDE_xTaskDelayUntil == 1 ) + + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskDelayUntilImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskDelayUntil_Unpriv \n" + " MPU_xTaskDelayUntil_Priv: \n" + " b MPU_xTaskDelayUntilImpl \n" + " MPU_xTaskDelayUntil_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskAbortDelayImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskAbortDelay_Unpriv \n" + " MPU_xTaskAbortDelay_Priv: \n" + " b MPU_xTaskAbortDelayImpl \n" + " MPU_xTaskAbortDelay_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskDelay == 1 ) + + void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskDelayImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskDelay_Unpriv \n" + " MPU_vTaskDelay_Priv: \n" + " b MPU_vTaskDelayImpl \n" + " MPU_vTaskDelay_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskPriorityGet == 1 ) + + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskPriorityGetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskPriorityGet_Unpriv \n" + " MPU_uxTaskPriorityGet_Priv: \n" + " b MPU_uxTaskPriorityGetImpl \n" + " MPU_uxTaskPriorityGet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_eTaskGetState == 1 ) + + eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_eTaskGetStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_eTaskGetState_Unpriv \n" + " MPU_eTaskGetState_Priv: \n" + " b MPU_eTaskGetStateImpl \n" + " MPU_eTaskGetState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory" + ); + } + + #endif /* if ( INCLUDE_eTaskGetState == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskGetInfoImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskGetInfo_Unpriv \n" + " MPU_vTaskGetInfo_Priv: \n" + " b MPU_vTaskGetInfoImpl \n" + " MPU_vTaskGetInfo_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory" + ); + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) + + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetIdleTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetIdleTaskHandle_Unpriv \n" + " MPU_xTaskGetIdleTaskHandle_Priv: \n" + " b MPU_xTaskGetIdleTaskHandleImpl \n" + " MPU_xTaskGetIdleTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + + void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSuspendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSuspend_Unpriv \n" + " MPU_vTaskSuspend_Priv: \n" + " b MPU_vTaskSuspendImpl \n" + " MPU_vTaskSuspend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + + void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskResumeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskResume_Unpriv \n" + " MPU_vTaskResume_Priv: \n" + " b MPU_vTaskResumeImpl \n" + " MPU_vTaskResume_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + TickType_t MPU_xTaskGetTickCount( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetTickCountImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetTickCount_Unpriv \n" + " MPU_xTaskGetTickCount_Priv: \n" + " b MPU_xTaskGetTickCountImpl \n" + " MPU_xTaskGetTickCount_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetNumberOfTasksImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetNumberOfTasks_Unpriv \n" + " MPU_uxTaskGetNumberOfTasks_Priv: \n" + " b MPU_uxTaskGetNumberOfTasksImpl \n" + " MPU_uxTaskGetNumberOfTasks_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetRunTimeCounterImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetRunTimeCounter_Unpriv \n" + " MPU_ulTaskGetRunTimeCounter_Priv: \n" + " b MPU_ulTaskGetRunTimeCounterImpl \n" + " MPU_ulTaskGetRunTimeCounter_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetRunTimePercentImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetRunTimePercent_Unpriv \n" + " MPU_ulTaskGetRunTimePercent_Priv: \n" + " b MPU_ulTaskGetRunTimePercentImpl \n" + " MPU_ulTaskGetRunTimePercent_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetIdleRunTimePercentImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv \n" + " MPU_ulTaskGetIdleRunTimePercent_Priv: \n" + " b MPU_ulTaskGetIdleRunTimePercentImpl \n" + " MPU_ulTaskGetIdleRunTimePercent_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetIdleRunTimeCounterImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv \n" + " MPU_ulTaskGetIdleRunTimeCounter_Priv: \n" + " b MPU_ulTaskGetIdleRunTimeCounterImpl \n" + " MPU_ulTaskGetIdleRunTimeCounter_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetApplicationTaskTagImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetApplicationTaskTag_Unpriv \n" + " MPU_vTaskSetApplicationTaskTag_Priv: \n" + " b MPU_vTaskSetApplicationTaskTagImpl \n" + " MPU_vTaskSetApplicationTaskTag_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory" + ); + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetApplicationTaskTagImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetApplicationTaskTag_Unpriv \n" + " MPU_xTaskGetApplicationTaskTag_Priv: \n" + " b MPU_xTaskGetApplicationTaskTagImpl \n" + " MPU_xTaskGetApplicationTaskTag_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory" + ); + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetThreadLocalStoragePointerImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv \n" + " MPU_vTaskSetThreadLocalStoragePointer_Priv: \n" + " b MPU_vTaskSetThreadLocalStoragePointerImpl \n" + " MPU_vTaskSetThreadLocalStoragePointer_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory" + ); + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv \n" + " MPU_pvTaskGetThreadLocalStoragePointer_Priv: \n" + " b MPU_pvTaskGetThreadLocalStoragePointerImpl \n" + " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory" + ); + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetSystemStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetSystemState_Unpriv \n" + " MPU_uxTaskGetSystemState_Priv: \n" + " b MPU_uxTaskGetSystemStateImpl \n" + " MPU_uxTaskGetSystemState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory" + ); + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) + + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetStackHighWaterMarkImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetStackHighWaterMark_Unpriv \n" + " MPU_uxTaskGetStackHighWaterMark_Priv: \n" + " b MPU_uxTaskGetStackHighWaterMarkImpl \n" + " MPU_uxTaskGetStackHighWaterMark_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetStackHighWaterMark2Impl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv \n" + " MPU_uxTaskGetStackHighWaterMark2_Priv: \n" + " b MPU_uxTaskGetStackHighWaterMark2Impl \n" + " MPU_uxTaskGetStackHighWaterMark2_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) + + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetCurrentTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetCurrentTaskHandle_Unpriv \n" + " MPU_xTaskGetCurrentTaskHandle_Priv: \n" + " b MPU_xTaskGetCurrentTaskHandleImpl \n" + " MPU_xTaskGetCurrentTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory" + ); + } + + #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetSchedulerState == 1 ) + + BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetSchedulerStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetSchedulerState_Unpriv \n" + " MPU_xTaskGetSchedulerState_Priv: \n" + " b MPU_xTaskGetSchedulerStateImpl \n" + " MPU_xTaskGetSchedulerState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */ +/*-----------------------------------------------------------*/ + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetTimeOutStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetTimeOutState_Unpriv \n" + " MPU_vTaskSetTimeOutState_Priv: \n" + " b MPU_vTaskSetTimeOutStateImpl \n" + " MPU_vTaskSetTimeOutState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskCheckForTimeOutImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskCheckForTimeOut_Unpriv \n" + " MPU_xTaskCheckForTimeOut_Priv: \n" + " b MPU_xTaskCheckForTimeOutImpl \n" + " MPU_xTaskCheckForTimeOut_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotify_Unpriv \n" + " MPU_xTaskGenericNotify_Priv: \n" + " b MPU_xTaskGenericNotifyImpl \n" + " MPU_xTaskGenericNotify_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyWaitImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotifyWait_Unpriv \n" + " MPU_xTaskGenericNotifyWait_Priv: \n" + " b MPU_xTaskGenericNotifyWaitImpl \n" + " MPU_xTaskGenericNotifyWait_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGenericNotifyTakeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGenericNotifyTake_Unpriv \n" + " MPU_ulTaskGenericNotifyTake_Priv: \n" + " b MPU_ulTaskGenericNotifyTakeImpl \n" + " MPU_ulTaskGenericNotifyTake_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyStateClearImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotifyStateClear_Unpriv \n" + " MPU_xTaskGenericNotifyStateClear_Priv: \n" + " b MPU_xTaskGenericNotifyStateClearImpl \n" + " MPU_xTaskGenericNotifyStateClear_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGenericNotifyValueClearImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGenericNotifyValueClear_Unpriv \n" + " MPU_ulTaskGenericNotifyValueClear_Priv: \n" + " b MPU_ulTaskGenericNotifyValueClearImpl \n" + " MPU_ulTaskGenericNotifyValueClear_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGenericSendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGenericSend_Unpriv \n" + " MPU_xQueueGenericSend_Priv: \n" + " b MPU_xQueueGenericSendImpl \n" + " MPU_xQueueGenericSend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxQueueMessagesWaitingImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxQueueMessagesWaiting_Unpriv \n" + " MPU_uxQueueMessagesWaiting_Priv: \n" + " b MPU_uxQueueMessagesWaitingImpl \n" + " MPU_uxQueueMessagesWaiting_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxQueueSpacesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxQueueSpacesAvailable_Unpriv \n" + " MPU_uxQueueSpacesAvailable_Priv: \n" + " b MPU_uxQueueSpacesAvailableImpl \n" + " MPU_uxQueueSpacesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueReceiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueReceive_Unpriv \n" + " MPU_xQueueReceive_Priv: \n" + " b MPU_xQueueReceiveImpl \n" + " MPU_xQueueReceive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueuePeekImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueuePeek_Unpriv \n" + " MPU_xQueuePeek_Priv: \n" + " b MPU_xQueuePeekImpl \n" + " MPU_xQueuePeek_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueSemaphoreTakeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueSemaphoreTake_Unpriv \n" + " MPU_xQueueSemaphoreTake_Priv: \n" + " b MPU_xQueueSemaphoreTakeImpl \n" + " MPU_xQueueSemaphoreTake_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) + + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGetMutexHolderImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGetMutexHolder_Unpriv \n" + " MPU_xQueueGetMutexHolder_Priv: \n" + " b MPU_xQueueGetMutexHolderImpl \n" + " MPU_xQueueGetMutexHolder_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory" + ); + } + + #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueTakeMutexRecursiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueTakeMutexRecursive_Unpriv \n" + " MPU_xQueueTakeMutexRecursive_Priv: \n" + " b MPU_xQueueTakeMutexRecursiveImpl \n" + " MPU_xQueueTakeMutexRecursive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory" + ); + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGiveMutexRecursiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGiveMutexRecursive_Unpriv \n" + " MPU_xQueueGiveMutexRecursive_Priv: \n" + " b MPU_xQueueGiveMutexRecursiveImpl \n" + " MPU_xQueueGiveMutexRecursive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory" + ); + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueSelectFromSetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueSelectFromSet_Unpriv \n" + " MPU_xQueueSelectFromSet_Priv: \n" + " b MPU_xQueueSelectFromSetImpl \n" + " MPU_xQueueSelectFromSet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory" + ); + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueAddToSetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueAddToSet_Unpriv \n" + " MPU_xQueueAddToSet_Priv: \n" + " b MPU_xQueueAddToSetImpl \n" + " MPU_xQueueAddToSet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory" + ); + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vQueueAddToRegistryImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vQueueAddToRegistry_Unpriv \n" + " MPU_vQueueAddToRegistry_Priv: \n" + " b MPU_vQueueAddToRegistryImpl \n" + " MPU_vQueueAddToRegistry_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vQueueUnregisterQueueImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vQueueUnregisterQueue_Unpriv \n" + " MPU_vQueueUnregisterQueue_Priv: \n" + " b MPU_vQueueUnregisterQueueImpl \n" + " MPU_vQueueUnregisterQueue_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pcQueueGetNameImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pcQueueGetName_Unpriv \n" + " MPU_pcQueueGetName_Priv: \n" + " b MPU_pcQueueGetNameImpl \n" + " MPU_pcQueueGetName_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pvTimerGetTimerIDImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pvTimerGetTimerID_Unpriv \n" + " MPU_pvTimerGetTimerID_Priv: \n" + " b MPU_pvTimerGetTimerIDImpl \n" + " MPU_pvTimerGetTimerID_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTimerSetTimerIDImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTimerSetTimerID_Unpriv \n" + " MPU_vTimerSetTimerID_Priv: \n" + " b MPU_vTimerSetTimerIDImpl \n" + " MPU_vTimerSetTimerID_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerIsTimerActiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerIsTimerActive_Unpriv \n" + " MPU_xTimerIsTimerActive_Priv: \n" + " b MPU_xTimerIsTimerActiveImpl \n" + " MPU_xTimerIsTimerActive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv \n" + " MPU_xTimerGetTimerDaemonTaskHandle_Priv: \n" + " b MPU_xTimerGetTimerDaemonTaskHandleImpl \n" + " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGenericCommandFromTaskImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGenericCommandFromTask_Unpriv \n" + " MPU_xTimerGenericCommandFromTask_Priv: \n" + " b MPU_xTimerGenericCommandFromTaskImpl \n" + " MPU_xTimerGenericCommandFromTask_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pcTimerGetNameImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pcTimerGetName_Unpriv \n" + " MPU_pcTimerGetName_Priv: \n" + " b MPU_pcTimerGetNameImpl \n" + " MPU_pcTimerGetName_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTimerSetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTimerSetReloadMode_Unpriv \n" + " MPU_vTimerSetReloadMode_Priv: \n" + " b MPU_vTimerSetReloadModeImpl \n" + " MPU_vTimerSetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetReloadMode_Unpriv \n" + " MPU_xTimerGetReloadMode_Priv: \n" + " b MPU_xTimerGetReloadModeImpl \n" + " MPU_xTimerGetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTimerGetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTimerGetReloadMode_Unpriv \n" + " MPU_uxTimerGetReloadMode_Priv: \n" + " b MPU_uxTimerGetReloadModeImpl \n" + " MPU_uxTimerGetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetPeriodImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetPeriod_Unpriv \n" + " MPU_xTimerGetPeriod_Priv: \n" + " b MPU_xTimerGetPeriodImpl \n" + " MPU_xTimerGetPeriod_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetExpiryTimeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetExpiryTime_Unpriv \n" + " MPU_xTimerGetExpiryTime_Priv: \n" + " b MPU_xTimerGetExpiryTimeImpl \n" + " MPU_xTimerGetExpiryTime_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupWaitBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupWaitBits_Unpriv \n" + " MPU_xEventGroupWaitBits_Priv: \n" + " b MPU_xEventGroupWaitBitsImpl \n" + " MPU_xEventGroupWaitBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupClearBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupClearBits_Unpriv \n" + " MPU_xEventGroupClearBits_Priv: \n" + " b MPU_xEventGroupClearBitsImpl \n" + " MPU_xEventGroupClearBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupSetBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupSetBits_Unpriv \n" + " MPU_xEventGroupSetBits_Priv: \n" + " b MPU_xEventGroupSetBitsImpl \n" + " MPU_xEventGroupSetBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupSyncImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupSync_Unpriv \n" + " MPU_xEventGroupSync_Priv: \n" + " b MPU_xEventGroupSyncImpl \n" + " MPU_xEventGroupSync_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxEventGroupGetNumberImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxEventGroupGetNumber_Unpriv \n" + " MPU_uxEventGroupGetNumber_Priv: \n" + " b MPU_uxEventGroupGetNumberImpl \n" + " MPU_uxEventGroupGetNumber_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory" + ); + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vEventGroupSetNumberImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vEventGroupSetNumber_Unpriv \n" + " MPU_vEventGroupSetNumber_Priv: \n" + " b MPU_vEventGroupSetNumberImpl \n" + " MPU_vEventGroupSetNumber_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory" + ); + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferSend_Unpriv \n" + " MPU_xStreamBufferSend_Priv: \n" + " b MPU_xStreamBufferSendImpl \n" + " MPU_xStreamBufferSend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferReceiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferReceive_Unpriv \n" + " MPU_xStreamBufferReceive_Priv: \n" + " b MPU_xStreamBufferReceiveImpl \n" + " MPU_xStreamBufferReceive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferIsFullImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferIsFull_Unpriv \n" + " MPU_xStreamBufferIsFull_Priv: \n" + " b MPU_xStreamBufferIsFullImpl \n" + " MPU_xStreamBufferIsFull_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferIsEmptyImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferIsEmpty_Unpriv \n" + " MPU_xStreamBufferIsEmpty_Priv: \n" + " b MPU_xStreamBufferIsEmptyImpl \n" + " MPU_xStreamBufferIsEmpty_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSpacesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferSpacesAvailable_Unpriv \n" + " MPU_xStreamBufferSpacesAvailable_Priv: \n" + " b MPU_xStreamBufferSpacesAvailableImpl \n" + " MPU_xStreamBufferSpacesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferBytesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferBytesAvailable_Unpriv \n" + " MPU_xStreamBufferBytesAvailable_Priv: \n" + " b MPU_xStreamBufferBytesAvailableImpl \n" + " MPU_xStreamBufferBytesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSetTriggerLevelImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferSetTriggerLevel_Unpriv \n" + " MPU_xStreamBufferSetTriggerLevel_Priv: \n" + " b MPU_xStreamBufferSetTriggerLevelImpl \n" + " MPU_xStreamBufferSetTriggerLevel_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferNextMessageLengthBytesImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv \n" + " MPU_xStreamBufferNextMessageLengthBytes_Priv: \n" + " b MPU_xStreamBufferNextMessageLengthBytesImpl \n" + " MPU_xStreamBufferNextMessageLengthBytes_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c new file mode 100644 index 000000000..76d2b2445 --- /dev/null +++ b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c @@ -0,0 +1,2280 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024-2025 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU includes. */ +#include "mpu_wrappers.h" +#include "mpu_syscall_numbers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration settings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to check the validity of an interrupt priority. + */ +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) ) +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used during system call enter and exit. + */ +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Offsets in the stack to the parameters when inside the SVC handler. + */ +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +#if ( portARMV8M_MINOR_VERSION >= 1 ) + + /* Enable Privileged eXecute Never MPU attribute for the selected memory + * region. */ + #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL ) +#endif /* portARMV8M_MINOR_VERSION >= 1 */ + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Extract first address of the MPU region as encoded in the + * RBAR (Region Base Address Register) value. */ +#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \ + ( ( rbar ) & portMPU_RBAR_ADDRESS_MASK ) + +/* Extract last address of the MPU region as encoded in the + * RLAR (Region Limit Address Register) value. */ +#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \ + ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK ) + +/* Does addr lies within [start, end] address range? */ +#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \ + ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) ) + +/* Is the access request satisfied by the available permissions? */ +#define portIS_AUTHORIZED( accessRequest, permissions ) \ + ( ( ( permissions ) & ( accessRequest ) ) == accessRequest ) + +/* Max value that fits in a uint32_t type. */ +#define portUINT32_MAX ( ~( ( uint32_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. + */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 + +/** + * @brief Constants required to check and configure PACBTI security feature implementation. + */ +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) ) + + #define portCONTROL_UPAC_EN ( 1UL << 7UL ) + #define portCONTROL_PAC_EN ( 1UL << 6UL ) + #define portCONTROL_UBTI_EN ( 1UL << 5UL ) + #define portCONTROL_BTI_EN ( 1UL << 4UL ) + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Extract MPU region's access permissions from the Region Base Address + * Register (RBAR) value. + * + * @param ulRBARValue RBAR value for the MPU region. + * + * @return uint32_t Access permissions. + */ + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + + /** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + /** + * @brief Configures PACBTI features. + * + * This function configures the Pointer Authentication, and Branch Target + * Identification security features as per the user configuration. It returns + * the value of the special purpose CONTROL register accordingly, and optionally + * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M + * architecture based) target supports PACBTI security feature. + * + * @param xWriteControlRegister Used to control whether the special purpose + * CONTROL register should be updated or not. + * + * @return CONTROL register value according to the configured PACBTI option. + */ + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the system call stack so that upon returning from + * SVC, the system call stack is used. + * + * @param pulTaskStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + * @param ucSystemCallNumber The system call number of the system call. + */ + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Raise SVC for exiting from a system call. + */ + void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief This variable is set to pdTRUE when the scheduler is started. + */ + PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + + /** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +/** + * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + /** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + + /** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + + /** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the cpsid instruction + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessPermissions = 0; + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_ONLY ) + { + ulAccessPermissions = tskMPU_READ_PERMISSION; + } + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_WRITE ) + { + ulAccessPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION ); + } + + return ulAccessPermissions; + } + +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } + +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ portOFFSET_TO_PC ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ]; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulSystemCallStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the system call section (i.e. application is + * not raising SVC directly). + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as + * it is non-NULL only during the execution of a system call (i.e. + * between system call enter and exit). + * 3. System call is not for a kernel API disabled by the configuration + * in FreeRTOSConfig.h. + * 4. We do not need to check that ucSystemCallNumber is within range + * because the assembly SVC handler checks that before calling + * this function. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) && + ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) ) + { + pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the system call stack for the stack frame. */ + pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulSystemCallStack[ i ] = pulTaskStack[ i ]; + } + + /* Store the value of the Link Register before the SVC was raised. + * It contains the address of the caller of the System Call entry + * point (i.e. the caller of the MPU_). We need to restore it + * when we exit from the system call. */ + pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; + + /* Store the value of the PSPLIM register before the SVC was raised. + * We need to restore it when we exit from the system call. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* Use the pulSystemCallStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif + + /* Start executing the system call upon returning from this handler. */ + pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; + + /* Raise a request to exit from the system call upon finishing the + * system call. */ + pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; + + /* Remember the location where we should copy the stack frame when we exit from + * the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize; + + /* Record if the hardware used padding to force the stack pointer + * to be double word aligned. */ + if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK ) + { + pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG; + } + else + { + pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG ); + } + + /* We ensure in pxPortInitialiseStack that the system call stack is + * double word aligned and therefore, there is no need of padding. + * Clear the bit[9] of stacked xPSR. */ + pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + + /* Raise the privilege for the duration of the system call. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " bics r0, r1 \n" /* Clear nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */ + { + __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulTaskStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the privileged code (i.e. application is not + * raising SVC directly). This SVC is only raised from + * vRequestSystemCallExit which is in the privileged code section. + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL - + * this means that we previously entered a system call and the + * application is not attempting to exit without entering a system + * call. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) ) + { + pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the task stack for the stack frame. */ + pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulTaskStack[ i ] = pulSystemCallStack[ i ]; + } + + /* Use the pulTaskStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) ); + + /* Return to the caller of the System Call entry point (i.e. the + * caller of the MPU_). */ + pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + /* Ensure that LR has a valid value.*/ + pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + + /* Restore the PSPLIM register to what it was at the time of + * system call entry. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* If the hardware used padding to force the stack pointer + * to be double word aligned, set the stacked xPSR bit[9], + * otherwise clear it. */ + if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG ) + { + pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK; + } + else + { + pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + } + + /* This is not NULL only for the duration of the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; + + /* Drop the privilege before returning to the thread mode. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " orrs r0, r1 \n" /* Set nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xTaskIsPrivileged = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xTaskIsPrivileged = pdTRUE; + } + + return xTaskIsPrivileged; + } + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged, + xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulIndex = 0; + uint32_t ulControl = 0x0; + + xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ + ulIndex++; + + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + ulIndex++; + + #if ( configENABLE_TRUSTZONE == 1 ) + { + xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */ + ulIndex++; + } + #endif /* configENABLE_TRUSTZONE */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + ulIndex++; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Check PACBTI security feature configuration before pushing the + * CONTROL register's value on task's TCB. */ + ulControl = prvConfigurePACBTI( pdFALSE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + if( xRunPrivileged == pdTRUE ) + { + xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + else + { + xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG ); + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ + ulIndex++; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + { + /* Ensure that the system call stack is double word aligned. */ + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) + + ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + /* This is not NULL only for the duration of a system call. */ + xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL; + } + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ]; + ulIndex++; + } + } + #endif /* configENABLE_PAC */ + + return &( xMPUSettings->ulContext[ ulIndex ] ); + } + +#else /* configENABLE_MPU */ + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ + { + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + pxTopOfStack--; + *pxTopOfStack = ulTaskPacKey[ i ]; + } + } + #endif /* configENABLE_PAC */ + + return pxTopOfStack; + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Set the CONTROL register value based on PACBTI security feature + * configuration before starting the first task. */ + ( void ) prvConfigurePACBTI( pdTRUE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + { + xSchedulerRunning = pdTRUE; + } + #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + configSTACK_DEPTH_TYPE uxStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( uxStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* PXN. */ + #if ( portARMV8M_MINOR_VERSION >= 1 ) + { + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ); + } + } + #endif /* portARMV8M_MINOR_VERSION >= 1 */ + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, + uint32_t ulBufferLength, + uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */ + + { + uint32_t i, ulBufferStartAddress, ulBufferEndAddress; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE ) + { + ulBufferStartAddress = ( uint32_t ) pvBuffer; + ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL ); + + for( i = 0; i < portTOTAL_NUM_REGIONS; i++ ) + { + /* Is the MPU region enabled? */ + if( ( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR & portMPU_RLAR_REGION_ENABLE ) == portMPU_RLAR_REGION_ENABLE ) + { + if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_AUTHORIZED( ulAccessRequested, + prvGetRegionAccessPermissions( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ) ) ) + { + xAccessGranted = pdTRUE; + break; + } + } + } + } + } + + return xAccessGranted; + } + +#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings; + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else + { + xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 ) + { + xAccessGranted = pdTRUE; + } + } + } + + return xAccessGranted; + } + + #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + ( void ) lInternalIndexOfKernelObject; + + /* If Access Control List feature is not used, all the tasks have + * access to all the kernel objects. */ + return pdTRUE; + } + + #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + { + uint32_t ulControl = 0x0; + + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); + + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; + + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c b/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c new file mode 100644 index 000000000..bc7bb6071 --- /dev/null +++ b/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c @@ -0,0 +1,524 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION + * is defined correctly and privileged functions are placed in correct sections. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Portasm includes. */ +#include "portasm.h" + +/* System call numbers includes. */ +#include "mpu_syscall_numbers.h" + +/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the + * header files. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#if ( configENABLE_MPU == 1 ) + + void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " program_mpu_first_task: \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */ + " \n" + " dmb \n" /* Complete outstanding transfers before disabling MPU. */ + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + " str r2, [r1] \n" /* Disable MPU. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */ + " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r1, [r2] \n" /* Program MAIR0. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " \n" + " movs r3, #4 \n" /* r3 = 4. */ + " str r3, [r1] \n" /* Program RNR = 4. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + " \n" + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " orr r2, #1 \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */ + " str r2, [r1] \n" /* Enable MPU. */ + " dsb \n" /* Force memory writes before continuing. */ + " \n" + " restore_context_first_task: \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/ + " ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */ + " \n" + " restore_special_regs_first_task: \n" + #if ( configENABLE_PAC == 1 ) + " ldmdb r1!, {r2-r5} \n" /* Read task's dedicated PAC key from the task's context. */ + " msr PAC_KEY_P_0, r2 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_1, r3 \n" + " msr PAC_KEY_P_2, r4 \n" + " msr PAC_KEY_P_3, r5 \n" + " clrm {r2-r5} \n" /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + " ldmdb r1!, {r2-r4, lr} \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */ + " msr psp, r2 \n" + " msr psplim, r3 \n" + " msr control, r4 \n" + " \n" + " restore_general_regs_first_task: \n" + " ldmdb r1!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */ + " stmia r2!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */ + " ldmdb r1!, {r4-r11} \n" /* r4-r11 restored. */ + " \n" + " restore_context_done_first_task: \n" + " str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */ + " mov r0, #0 \n" + " msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */ + " bx lr \n" + ); + } + +#else /* configENABLE_MPU */ + + void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + " ldr r0, [r1] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + " \n" + #if ( configENABLE_PAC == 1 ) + " ldmia r0!, {r1-r4} \n" /* Read task's dedicated PAC key from stack. */ + " msr PAC_KEY_P_3, r1 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_2, r2 \n" + " msr PAC_KEY_P_1, r3 \n" + " msr PAC_KEY_P_0, r4 \n" + " clrm {r1-r4} \n" /* Clear r1-r4. */ + #endif /* configENABLE_PAC */ + " \n" + " ldm r0!, {r1-r2} \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */ + " msr psplim, r1 \n" /* Set this task's PSPLIM value. */ + " mrs r1, control \n" /* Obtain current control register value. */ + " orrs r1, r1, #2 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */ + " msr control, r1 \n" /* Write back the new control register value. */ + " adds r0, #32 \n" /* Discard everything up to r0. */ + " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */ + " isb \n" + " mov r0, #0 \n" + " msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */ + " bx r2 \n" /* Finally, branch to EXC_RETURN. */ + ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* r0 = CONTROL. */ + " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + " ite ne \n" + " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + " bx lr \n" /* Return. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* Read the CONTROL register. */ + " bic r0, #1 \n" /* Clear the bit 0. */ + " msr control, r0 \n" /* Write back the new CONTROL value. */ + " bx lr \n" /* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vResetPrivilege( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* r0 = CONTROL. */ + " orr r0, #1 \n" /* r0 = r0 | 1. */ + " msr control, r0 \n" /* CONTROL = r0. */ + " bx lr \n" /* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r0, =0xe000ed08 \n" /* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */ + " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */ + " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */ + " cpsie i \n" /* Globally enable interrupts. */ + " cpsie f \n" + " dsb \n" + " isb \n" + " svc %0 \n" /* System call to start the first task. */ + " nop \n" + ::"i" ( portSVC_START_SCHEDULER ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, basepri \n" /* r0 = basepri. Return original basepri value. */ + " mov r1, %0 \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r1 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bx lr \n" /* Return. */ + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " msr basepri, r0 \n" /* basepri = ulMask. */ + " dsb \n" + " isb \n" + " bx lr \n" /* Return. */ + ::: "memory" + ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */ + " ldr r1, [r0] \n" /* r1 = Location in TCB where the context should be saved. */ + " mrs r2, psp \n" /* r2 = PSP. */ + " \n" + " save_general_regs: \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " add r2, r2, #0x20 \n" /* Move r2 to location where s0 is saved. */ + " tst lr, #0x10 \n" + " ittt eq \n" + " vstmiaeq r1!, {s16-s31} \n" /* Store s16-s31. */ + " vldmiaeq r2, {s0-s16} \n" /* Copy hardware saved FP context into s0-s16. */ + " vstmiaeq r1!, {s0-s16} \n" /* Store hardware saved FP context. */ + " sub r2, r2, #0x20 \n" /* Set r2 back to the location of hardware saved context. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " stmia r1!, {r4-r11} \n" /* Store r4-r11. */ + " ldmia r2, {r4-r11} \n" /* Copy the hardware saved context into r4-r11. */ + " stmia r1!, {r4-r11} \n" /* Store the hardware saved context. */ + " \n" + " save_special_regs: \n" + " mrs r3, psplim \n" /* r3 = PSPLIM. */ + " mrs r4, control \n" /* r4 = CONTROL. */ + " stmia r1!, {r2-r4, lr} \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ + #if ( configENABLE_PAC == 1 ) + " mrs r2, PAC_KEY_P_0 \n" /* Read task's dedicated PAC key from the PAC key registers. */ + " mrs r3, PAC_KEY_P_1 \n" + " mrs r4, PAC_KEY_P_2 \n" + " mrs r5, PAC_KEY_P_3 \n" + " stmia r1!, {r2-r5} \n" /* Store the task's dedicated PAC key on the task's context. */ + " clrm {r2-r5} \n" /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + " str r1, [r0] \n" /* Save the location from where the context should be restored as the first member of TCB. */ + " \n" + " select_next_task: \n" + " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bl vTaskSwitchContext \n" + " mov r0, #0 \n" /* r0 = 0. */ + " msr basepri, r0 \n" /* Enable interrupts. */ + " \n" + " program_mpu: \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */ + " \n" + " dmb \n" /* Complete outstanding transfers before disabling MPU. */ + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + " str r2, [r1] \n" /* Disable MPU. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */ + " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r1, [r2] \n" /* Program MAIR0. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " \n" + " movs r3, #4 \n" /* r3 = 4. */ + " str r3, [r1] \n" /* Program RNR = 4. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + " \n" + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " orr r2, #1 \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */ + " str r2, [r1] \n" /* Enable MPU. */ + " dsb \n" /* Force memory writes before continuing. */ + " \n" + " restore_context: \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/ + " ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */ + " \n" + " restore_special_regs: \n" + #if ( configENABLE_PAC == 1 ) + " ldmdb r1!, {r2-r5} \n" /* Read task's dedicated PAC key from the task's context. */ + " msr PAC_KEY_P_0, r2 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_1, r3 \n" + " msr PAC_KEY_P_2, r4 \n" + " msr PAC_KEY_P_3, r5 \n" + " clrm {r2-r5} \n" /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + " ldmdb r1!, {r2-r4, lr} \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */ + " msr psp, r2 \n" + " msr psplim, r3 \n" + " msr control, r4 \n" + " \n" + " restore_general_regs: \n" + " ldmdb r1!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */ + " stmia r2!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */ + " ldmdb r1!, {r4-r11} \n" /* r4-r11 restored. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" + " ittt eq \n" + " vldmdbeq r1!, {s0-s16} \n" /* s0-s16 contain hardware saved FP context. */ + " vstmiaeq r2!, {s0-s16} \n" /* Copy hardware saved FP context on the task stack. */ + " vldmdbeq r1!, {s16-s31} \n" /* Restore s16-s31. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + " restore_context_done: \n" + " str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */ + " bx lr \n" + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); + } + +#else /* configENABLE_MPU */ + + void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, psp \n" /* Read PSP in r0. */ + " \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vstmdbeq r0!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + " mrs r2, psplim \n" /* r2 = PSPLIM. */ + " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */ + " stmdb r0!, {r2-r11} \n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */ + " \n" + #if ( configENABLE_PAC == 1 ) + " mrs r1, PAC_KEY_P_3 \n" /* Read task's dedicated PAC key from the PAC key registers. */ + " mrs r2, PAC_KEY_P_2 \n" + " mrs r3, PAC_KEY_P_1 \n" + " mrs r4, PAC_KEY_P_0 \n" + " stmdb r0!, {r1-r4} \n" /* Store the task's dedicated PAC key on the stack. */ + " clrm {r1-r4} \n" /* Clear r1-r4. */ + #endif /* configENABLE_PAC */ + " \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + " str r0, [r1] \n" /* Save the new top of stack in TCB. */ + " \n" + " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bl vTaskSwitchContext \n" + " mov r0, #0 \n" /* r0 = 0. */ + " msr basepri, r0 \n" /* Enable interrupts. */ + " \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ + " \n" + #if ( configENABLE_PAC == 1 ) + " ldmia r0!, {r2-r5} \n" /* Read task's dedicated PAC key from stack. */ + " msr PAC_KEY_P_3, r2 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_2, r3 \n" + " msr PAC_KEY_P_1, r4 \n" + " msr PAC_KEY_P_0, r5 \n" + " clrm {r2-r5} \n" /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + " \n" + " ldmia r0!, {r2-r11} \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */ + " \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst r3, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vldmiaeq r0!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */ + " msr psp, r0 \n" /* Remember the new top of stack for the task. */ + " bx r3 \n" + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + ".syntax unified \n" + ".extern vPortSVCHandler_C \n" + ".extern vSystemCallEnter \n" + ".extern vSystemCallExit \n" + " \n" + "tst lr, #4 \n" + "ite eq \n" + "mrseq r0, msp \n" + "mrsne r0, psp \n" + " \n" + "ldr r1, [r0, #24] \n" + "ldrb r2, [r1, #-2] \n" + "cmp r2, %0 \n" + "blt syscall_enter \n" + "cmp r2, %1 \n" + "beq syscall_exit \n" + "b vPortSVCHandler_C \n" + " \n" + "syscall_enter: \n" + " mov r1, lr \n" + " b vSystemCallEnter \n" + " \n" + "syscall_exit: \n" + " mov r1, lr \n" + " b vSystemCallExit \n" + " \n" + : /* No outputs. */ + : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT ) + : "r0", "r1", "r2", "memory" + ); + } + +#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " tst lr, #4 \n" + " ite eq \n" + " mrseq r0, msp \n" + " mrsne r0, psp \n" + " ldr r1, =vPortSVCHandler_C \n" + " bx r1 \n" + ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.h b/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.h new file mode 100644 index 000000000..b7021b024 --- /dev/null +++ b/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kernel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h new file mode 100644 index 000000000..7e14f2696 --- /dev/null +++ b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacro.h @@ -0,0 +1,79 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_MVE + #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE. +#endif /* configENABLE_MVE */ +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M85" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portARMV8M_MINOR_VERSION 1 +#define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h new file mode 100644 index 000000000..f373bcad5 --- /dev/null +++ b/portable/GCC/ARM_CM85_NTZ/non_secure/portmacrocommon.h @@ -0,0 +1,582 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACROCOMMON_H +#define PORTMACROCOMMON_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. +#endif /* configENABLE_FPU */ + +#ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. +#endif /* configENABLE_MPU */ + +#ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. +#endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() +#define portINLINE __inline +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif +#define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ +extern BaseType_t xPortIsInsideInterrupt( void ); + +extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + +extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; +extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + +extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; +extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + +#if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_PAC == 1 ) + + /** + * @brief Generates 128-bit task's random PAC key. + * + * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be + * filled with a 128-bit random number. + */ + void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); + +#endif /* configENABLE_PAC */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ +#if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) +#else + #define portPRIVILEGE_BIT ( 0x0UL ) +#endif /* configENABLE_MPU */ + +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ +#define portPRIVILEGED_FLASH_REGION ( 0UL ) +#define portUNPRIVILEGED_FLASH_REGION ( 1UL ) +#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) +#define portPRIVILEGED_RAM_REGION ( 3UL ) +#define portSTACK_REGION ( 4UL ) +#define portFIRST_CONFIGURABLE_REGION ( 5UL ) +#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) +#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) +#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ +#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ +#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ +#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ +#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ +#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ +#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ +#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) +#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) +#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + +#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) +#define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) +#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) +#define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + +#define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + #ifndef configSYSTEM_CALL_STACK_SIZE + #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. + #endif + + /** + * @brief System call stack. + */ + typedef struct SYSTEM_CALL_STACK_INFO + { + uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; + uint32_t * pulSystemCallStack; + uint32_t * pulSystemCallStackLimit; + uint32_t * pulTaskStack; + uint32_t ulLinkRegisterAtSystemCallEntry; + uint32_t ulStackLimitRegisterAtSystemCallEntry; + } xSYSTEM_CALL_STACK_INFO; + + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + /** + * @brief MPU settings as stored in the TCB. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><-----------><----> + * 16 17 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 71 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 17 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 55 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | | | PC, xPSR | EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><-----------><----> + * 16 17 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 70 + + #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + /* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 17 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 54 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+------------------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +----------+-----------------+------------------------------+------------+-----+ + * + * <---------><----------------><------------------------------><-----------><----> + * 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 38 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+----------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | PC, xPSR | EXC_RETURN | | | + * +----------+-----------------+----------------------+------------+-----+ + * + * <---------><----------------><----------------------><-----------><----> + * 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 37 + + #else /* #if( configENABLE_TRUSTZONE == 1 ) */ + + /* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) + + /* Size of an Access Control List (ACL) entry in bits. */ + #define portACL_ENTRY_SIZE_BITS ( 32U ) + + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + uint32_t ulContext[ MAX_CONTEXT_SIZE ]; + uint32_t ulTaskFlags; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo; + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ]; + #endif + #endif + } xMPU_SETTINGS; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Validate priority of ISRs that are allowed to call FreeRTOS + * system calls. + */ +#if ( configASSERT_DEFINED == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif +#endif + +/** + * @brief SVC numbers. + */ +#define portSVC_ALLOCATE_SECURE_CONTEXT 100 +#define portSVC_FREE_SECURE_CONTEXT 101 +#define portSVC_START_SCHEDULER 102 +#define portSVC_RAISE_PRIVILEGE 103 +#define portSVC_SYSTEM_CALL_EXIT 104 +#define portSVC_YIELD 105 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) +#endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() +#else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + extern BaseType_t xPortIsTaskPrivileged( void ); + +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACROCOMMON_H */ diff --git a/portable/GCC/ARM_CR5/port.c b/portable/GCC/ARM_CR5/port.c new file mode 100644 index 000000000..72658e8d7 --- /dev/null +++ b/portable/GCC/ARM_CR5/port.c @@ -0,0 +1,691 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS + #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. Refer to Cortex-A equivalent: http: /*www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */ +#endif + +#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET + #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. Refer to Cortex-A equivalent: http: /*www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */ +#endif + +#ifndef configUNIQUE_INTERRUPT_PRIORITIES + #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. Refer to Cortex-A equivalent: http: /*www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */ +#endif + +#ifndef configSETUP_TICK_INTERRUPT + #error configSETUP_TICK_INTERRUPT() must be defined. Refer to Cortex-A equivalent: http: /*www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */ +#endif /* configSETUP_TICK_INTERRUPT */ + +#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY + #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. Refer to Cortex-A equivalent: http: /*www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */ +#endif + +#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0 + #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0 +#endif + +#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES + #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + /* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/* In case security extensions are implemented. */ +#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 ) + #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 ) +#endif + +/* + * __ARM_FP is defined by the c preprocessor when FPU support is enabled, + * usually with the -mfpu= argument and -mfloat-abi=. + * + * Note: Some implementations of the c standard library may use FPU registers + * for generic memory operations (memcpy, etc). + * When setting configUSE_TASK_FPU_SUPPORT == 1, care must be taken to + * ensure that the FPU registers are not used without an FPU context. + */ +#if ( configUSE_TASK_FPU_SUPPORT == 0 ) + #ifdef __ARM_FP + #error __ARM_FP is defined, so configUSE_TASK_FPU_SUPPORT must be set to either to 1 or 2. + #endif /* __ARM_FP */ +#elif ( configUSE_TASK_FPU_SUPPORT == 1 ) || ( configUSE_TASK_FPU_SUPPORT == 2 ) + #ifndef __ARM_FP + #error __ARM_FP is not defined, so configUSE_TASK_FPU_SUPPORT must be set to 0. + #endif /* __ARM_FP */ +#endif /* configUSE_TASK_FPU_SUPPORT */ + +/* + * Some vendor specific files default configCLEAR_TICK_INTERRUPT() in + * portmacro.h. + */ +#ifndef configCLEAR_TICK_INTERRUPT + #define configCLEAR_TICK_INTERRUPT() +#endif + +/* + * A critical section is exited when the critical section nesting count reaches + * this value. + */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + +/* + * In all GICs 255 can be written to the priority mask register to unmask all + * (but the lowest) interrupt priority. + */ +#define portUNMASK_VALUE ( 0xFFUL ) + +/* + * Tasks are not created with a floating point context, but can be given a + * floating point context after they have been created. A variable is stored as + * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task + * does not have an FPU context, or any other value if the task does have an FPU + * context. + */ +#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) + +/* Constants required to setup the initial task context. */ +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portINTERRUPT_ENABLE_BIT ( 0x80UL ) +#define portTHUMB_MODE_ADDRESS ( 0x01UL ) + +/* + * Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary + * point is zero. + */ +#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 ) + +/* Masks all bits in the APSR other than the mode bits. */ +#define portAPSR_MODE_BITS_MASK ( 0x1F ) + +/* The value of the mode bits in the APSR when the CPU is executing in user + * mode. */ +#define portAPSR_USER_MODE ( 0x10 ) + +/* The critical section macros only mask interrupts up to an application + * determined priority level. Sometimes it is necessary to turn interrupt off in + * the CPU itself before modifying certain hardware registers. */ +#define portCPU_IRQ_DISABLE() \ + __asm volatile ( "CPSID i" ::: "memory" ); \ + __asm volatile ( "DSB" ); \ + __asm volatile ( "ISB" ); + +#define portCPU_IRQ_ENABLE() \ + __asm volatile ( "CPSIE i" ::: "memory" ); \ + __asm volatile ( "DSB" ); \ + __asm volatile ( "ISB" ); + + +/* Macro to unmask all interrupt priorities. */ +#define portCLEAR_INTERRUPT_MASK() \ + { \ + portCPU_IRQ_DISABLE(); \ + portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \ + __asm volatile ( "DSB \n" \ + "ISB \n" ); \ + portCPU_IRQ_ENABLE(); \ + } + +#define portINTERRUPT_PRIORITY_REGISTER_OFFSET 0x400UL +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portBIT_0_SET ( ( uint8_t ) 0x01 ) + +/* + * Let the user override the pre-loading of the initial LR with the address of + * prvTaskExitError() in case is messes up unwinding of the stack in the + * debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +#if ( configUSE_TASK_FPU_SUPPORT != 0 ) + +/* + * The space on the stack required to hold the FPU registers. + * + * The ARM Cortex R5 processor implements the VFPv3-D16 FPU + * architecture. This includes only 16 double-precision registers, + * instead of 32 as is in VFPv3. The register bank can be viewed + * either as sixteen 64-bit double-word registers (D0-D15) or + * thirty-two 32-bit single-word registers (S0-S31), in both cases + * the size of the bank remains the same. The FPU has also a 32-bit + * status register. + */ + #define portFPU_REGISTER_WORDS ( ( 16 * 2 ) + 1 ) +#endif /* configUSE_TASK_FPU_SUPPORT != 0 */ + +/*-----------------------------------------------------------*/ + +/* + * Starts the first task executing. This function is necessarily written in + * assembly code so is implemented in portASM.s. + */ +extern void vPortRestoreTaskContext( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +#if ( configUSE_TASK_FPU_SUPPORT != 0 ) + +/* + * If the application provides an implementation of vApplicationIRQHandler(), + * then it will get called directly without saving the FPU registers on + * interrupt entry, and this weak implementation of + * vApplicationFPUSafeIRQHandler() is just provided to remove linkage errors - + * it should never actually get called so its implementation contains a + * call to configASSERT() that will always fail. + * + * If the application provides its own implementation of + * vApplicationFPUSafeIRQHandler() then the implementation of + * vApplicationIRQHandler() provided in portASM.S will save the FPU registers + * before calling it. + * + * Therefore, if the application writer wants FPU registers to be saved on + * interrupt entry their IRQ handler must be called + * vApplicationFPUSafeIRQHandler(), and if the application writer does not want + * FPU registers to be saved on interrupt entry their IRQ handler must be + * called vApplicationIRQHandler(). + */ + void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR ) __attribute__( ( weak ) ); +#endif /* configUSE_TASK_FPU_SUPPORT != 0 */ + +/*-----------------------------------------------------------*/ + +/* + * A variable is used to keep track of the critical section nesting. This + * variable has to be stored as part of the task context and must be initialised to + * a non zero value to ensure interrupts don't inadvertently become unmasked before + * the scheduler starts. As it is stored as part of the task context it will + * automatically be set to 0 when the first task is started. + */ +volatile uint32_t ulCriticalNesting = 9999UL; + +#if ( configUSE_TASK_FPU_SUPPORT != 0 ) + +/* + * Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then + * a floating point context must be saved and restored for the task. + */ + uint32_t ulPortTaskHasFPUContext = pdFALSE; +#endif /* configUSE_TASK_FPU_SUPPORT != 0 */ + +/* Set to 1 to pend a context switch from an ISR. */ +uint32_t ulPortYieldRequired = pdFALSE; + +/* + * Counts the interrupt nesting depth. A context switch is only performed if + * if the nesting depth is 0. + */ +uint32_t ulPortInterruptNesting = 0UL; + +/* Used in asm code. */ +__attribute__( ( used ) ) const uint32_t ulICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS; +__attribute__( ( used ) ) const uint32_t ulICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS; +__attribute__( ( used ) ) const uint32_t ulICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS; +__attribute__( ( used ) ) const uint32_t ulMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* + * Setup the initial stack of the task. The stack is set exactly as + * expected by the portRESTORE_CONTEXT() macro. + * + * The fist real value on the stack is the status register, which is set for + * system mode, with interrupts enabled. A few NULLs are added first to ensure + * GDB does not try decoding a non-existent return address. + */ + *pxTopOfStack = ( StackType_t ) NULL; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) NULL; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) NULL; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + + if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL ) + { + /* The task will start in THUMB mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + + pxTopOfStack--; + + /* Next the return address, which in this case is the start of the task. */ + *pxTopOfStack = ( StackType_t ) pxCode; + pxTopOfStack--; + + /* Next all the registers other than the stack pointer. */ + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + + /* + * The task will start with a critical nesting count of 0 as interrupts are + * enabled. + */ + pxTopOfStack--; + *pxTopOfStack = portNO_CRITICAL_NESTING; + + #if ( configUSE_TASK_FPU_SUPPORT == 1 ) + { + /* + * The task will start without a floating point context. + * A task that uses the floating point hardware must call + * vPortTaskUsesFPU() before executing any floating point + * instructions. + */ + pxTopOfStack--; + *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT; + } + #elif ( configUSE_TASK_FPU_SUPPORT == 2 ) + { + /* + * The task will start with a floating point context. Leave enough + * space for the registers and ensure they are initialized to 0. + */ + pxTopOfStack -= portFPU_REGISTER_WORDS; + memset( pxTopOfStack, 0x00, portFPU_REGISTER_WORDS * sizeof( StackType_t ) ); + + pxTopOfStack--; + *pxTopOfStack = pdTRUE; + ulPortTaskHasFPUContext = pdTRUE; + } + #elif ( configUSE_TASK_FPU_SUPPORT != 0 ) + { + #error Invalid configUSE_TASK_FPU_SUPPORT setting - configUSE_TASK_FPU_SUPPORT must be set to 0, 1, or 2. + } + #endif /* configUSE_TASK_FPU_SUPPORT */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* + * A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. + */ + configASSERT( ulPortInterruptNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_FPU_SUPPORT != 0 ) + + void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR ) /* __attribute__( ( weak ) ) */ + { + ( void ) ulICCIAR; + configASSERT( ( volatile void * ) NULL ); + } + +#endif /* configUSE_TASK_FPU_SUPPORT != 0 */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + uint32_t ulAPSR, ulCycles = 8; /* 8 bits per byte. */ + + #if ( configASSERT_DEFINED == 1 ) + { + volatile uint8_t ucOriginalPriority; + volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET ); + volatile uint8_t ucMaxPriorityValue; + + /* + * Determine how many priority bits are implemented in the GIC. + * Save the interrupt priority value that is about to be clobbered. + */ + ucOriginalPriority = *pucFirstUserPriorityRegister; + + /* + * Determine the number of priority bits available. First write to + * all possible bits. + */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* Shift to the least significant bits. */ + while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET ) + { + ucMaxPriorityValue >>= ( uint8_t ) 0x01; + + /* + * If ulCycles reaches 0 then ucMaxPriorityValue must have been + * read as 0, indicating a misconfiguration. + */ + ulCycles--; + + if( ulCycles == 0 ) + { + break; + } + } + + /* + * Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read + * value. + */ + configASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY ); + + /* + * Restore the clobbered interrupt priority register to its original + * value. + */ + *pucFirstUserPriorityRegister = ucOriginalPriority; + } + #endif /* configASSERT_DEFINED */ + + /* + * Only continue if the CPU is not in User mode. The CPU must be in a + * Privileged mode for the scheduler to start. + */ + __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR )::"memory" ); + ulAPSR &= portAPSR_MODE_BITS_MASK; + configASSERT( ulAPSR != portAPSR_USER_MODE ); + + if( ulAPSR != portAPSR_USER_MODE ) + { + /* + * Only continue if the binary point value is set to its lowest possible + * setting. See the comments in vPortValidateInterruptPriority() below for + * more information. + */ + configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ); + + if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ) + { + /* + * Interrupts are turned off in the CPU itself to ensure tick does + * not execute while the scheduler is being started. Interrupts are + * automatically turned back on in the CPU when the first task starts + * executing. + */ + portCPU_IRQ_DISABLE(); + + /* Start the timer that generates the tick ISR. */ + configSETUP_TICK_INTERRUPT(); + + /* Start the first task executing. */ + vPortRestoreTaskContext(); + } + } + + /* + * Will only get here if vTaskStartScheduler() was called with the CPU in + * a non-privileged mode or the binary point register was not set to its lowest + * possible value. prvTaskExitError() is referenced to prevent a compiler + * warning about it being defined but not referenced in the case that the user + * defines their own exit address. + */ + ( void ) prvTaskExitError; + + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* + * Not implemented in ports where there is nothing to return to. + * Artificially force an assert. + */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + /* Mask interrupts up to the max syscall interrupt priority. */ + ulPortSetInterruptMask(); + + /* + * Now that interrupts are disabled, ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. + */ + ulCriticalNesting++; + + /* + * This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. + */ + if( ulCriticalNesting == 1 ) + { + configASSERT( ulPortInterruptNesting == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as the critical section is being exited. */ + ulCriticalNesting--; + + /* + * If the nesting level has reached zero then all interrupt + * priorities must be re-enabled. + */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* + * Critical nesting has reached zero so all interrupt priorities + * should be unmasked. + */ + portCLEAR_INTERRUPT_MASK(); + } + } +} +/*-----------------------------------------------------------*/ + +void FreeRTOS_Tick_Handler( void ) +{ + /* + * Set interrupt mask before altering scheduler structures. The tick + * handler runs at the lowest priority, so interrupts cannot already be masked, + * so there is no need to save and restore the current mask value. It is + * necessary to turn off interrupts in the CPU itself while the ICCPMR is being + * updated. + */ + portCPU_IRQ_DISABLE(); + portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); + __asm volatile ( "dsb \n" + "isb \n" ::: "memory" ); + portCPU_IRQ_ENABLE(); + + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + ulPortYieldRequired = pdTRUE; + } + + /* Ensure all interrupt priorities are active again. */ + portCLEAR_INTERRUPT_MASK(); + configCLEAR_TICK_INTERRUPT(); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_FPU_SUPPORT == 1 ) + + void vPortTaskUsesFPU( void ) + { + uint32_t ulInitialFPSCR = 0; + + /* + * A task is registering the fact that it needs an FPU context. Set the + * FPU flag (which is saved as part of the task context). + */ + ulPortTaskHasFPUContext = pdTRUE; + + /* Initialise the floating point status register. */ + __asm volatile ( "FMXR FPSCR, %0" ::"r" ( ulInitialFPSCR ) : "memory" ); + } + +#endif /* configUSE_TASK_FPU_SUPPORT == 1 */ +/*-----------------------------------------------------------*/ + +void vPortClearInterruptMask( uint32_t ulNewMaskValue ) +{ + if( ulNewMaskValue == pdFALSE ) + { + portCLEAR_INTERRUPT_MASK(); + } +} +/*-----------------------------------------------------------*/ + +uint32_t ulPortSetInterruptMask( void ) +{ + uint32_t ulReturn; + + /* Interrupts must be masked while ICCPMR is updated. */ + portCPU_IRQ_DISABLE(); + + if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ) + { + /* Interrupts were already masked. */ + ulReturn = pdTRUE; + } + else + { + ulReturn = pdFALSE; + portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); + __asm volatile ( "dsb \n" + "isb \n" ::: "memory" ); + } + + portCPU_IRQ_ENABLE(); + + return ulReturn; +} +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + /* + * The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + */ + + configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ); + + /* + * Priority grouping: The interrupt controller (GIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * The priority grouping is configured by the GIC's binary point register + * (ICCBPR). Writing 0 to ICCBPR will ensure it is set to its lowest + * possible value (which may be above 0). + */ + configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ); + } + +#endif /* configASSERT_DEFINED */ +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CR5/portASM.S b/portable/GCC/ARM_CR5/portASM.S new file mode 100644 index 000000000..3c39ef1b6 --- /dev/null +++ b/portable/GCC/ARM_CR5/portASM.S @@ -0,0 +1,337 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + .text + .arm + + .set SYS_MODE, 0x1f + .set SVC_MODE, 0x13 + .set IRQ_MODE, 0x12 + + /* Hardware registers. */ + .extern ulICCIAR + .extern ulICCEOIR + .extern ulICCPMR + + /* Variables and functions. */ + .extern ulMaxAPIPriorityMask + .extern _freertos_vector_table + .extern pxCurrentTCB + .extern vTaskSwitchContext + .extern vApplicationIRQHandler + .extern ulPortInterruptNesting + +#if defined( __ARM_FP ) + .extern ulPortTaskHasFPUContext +#endif /* __ARM_FP */ + + .global FreeRTOS_IRQ_Handler + .global FreeRTOS_SWI_Handler + .global vPortRestoreTaskContext + +.macro portSAVE_CONTEXT + + /* Save the LR and SPSR onto the system mode stack before switching to + system mode to save the remaining system mode registers. */ + SRSDB sp!, #SYS_MODE + CPS #SYS_MODE + PUSH {R0-R12, R14} + + /* Push the critical nesting count. */ + LDR R2, ulCriticalNestingConst + LDR R1, [R2] + PUSH {R1} + + #if defined( __ARM_FP ) + /* Does the task have a floating point context that needs saving? If + ulPortTaskHasFPUContext is 0 then no. */ + LDR R2, ulPortTaskHasFPUContextConst + LDR R3, [R2] + CMP R3, #0 + + /* Save the floating point context, if any. */ + FMRXNE R1, FPSCR + PUSHNE {R1} + VPUSHNE {D0-D15} + + /* Save ulPortTaskHasFPUContext itself. */ + PUSH {R3} + #endif /* __ARM_FP */ + + /* Save the stack pointer in the TCB. */ + LDR R0, pxCurrentTCBConst + LDR R1, [R0] + STR SP, [R1] + + .endm + +; /**********************************************************************/ + +.macro portRESTORE_CONTEXT + + /* Set the SP to point to the stack of the task being restored. */ + LDR R0, pxCurrentTCBConst + LDR R1, [R0] + LDR SP, [R1] + + #if defined( __ARM_FP ) + /* + * Is there a floating point context to restore? If the restored + * ulPortTaskHasFPUContext is zero then no. + */ + LDR R0, ulPortTaskHasFPUContextConst + POP {R1} + STR R1, [R0] + CMP R1, #0 + + /* Restore the floating point context, if any. */ + VPOPNE {D0-D15} + POPNE {R0} + VMSRNE FPSCR, R0 + #endif /* __ARM_FP */ + + /* Restore the critical section nesting depth. */ + LDR R0, ulCriticalNestingConst + POP {R1} + STR R1, [R0] + + /* Ensure the priority mask is correct for the critical nesting depth. */ + LDR R2, ulICCPMRConst + LDR R2, [R2] + CMP R1, #0 + MOVEQ R4, #255 + LDRNE R4, ulMaxAPIPriorityMaskConst + LDRNE R4, [R4] + STR R4, [R2] + + /* Restore all system mode registers other than the SP (which is already + being used). */ + POP {R0-R12, R14} + + /* Return to the task code, loading CPSR on the way. */ + RFEIA sp! + + .endm + + +/****************************************************************************** + * SVC handler is used to start the scheduler. + *****************************************************************************/ +.align 4 +.type FreeRTOS_SWI_Handler, %function +FreeRTOS_SWI_Handler: + /* Save the context of the current task and select a new task to run. */ + portSAVE_CONTEXT + + /* Ensure bit 2 of the stack pointer is clear. */ + MOV r2, sp + AND r2, r2, #4 + SUB sp, sp, r2 + + LDR R0, vTaskSwitchContextConst + BLX R0 + + portRESTORE_CONTEXT + + +/****************************************************************************** + * vPortRestoreTaskContext is used to start the scheduler. + *****************************************************************************/ +.type vPortRestoreTaskContext, %function +vPortRestoreTaskContext: + /* Switch to system mode. */ + CPS #SYS_MODE + portRESTORE_CONTEXT + +.align 4 +.type FreeRTOS_IRQ_Handler, %function +FreeRTOS_IRQ_Handler: + + /* Return to the interrupted instruction. */ + SUB lr, lr, #4 + + /* Push the return address and SPSR. */ + PUSH {lr} + MRS lr, SPSR + PUSH {lr} + + /* Change to supervisor mode to allow reentry. */ + CPS #SVC_MODE + + /* Push used registers. */ + PUSH {r0-r4, r12} + + /* Increment nesting count. r3 holds the address of ulPortInterruptNesting + for future use. r1 holds the original ulPortInterruptNesting value for + future use. */ + LDR r3, ulPortInterruptNestingConst + LDR r1, [r3] + ADD r4, r1, #1 + STR r4, [r3] + + /* Read value from the interrupt acknowledge register, which is stored in r0 + for future parameter and interrupt clearing use. */ + LDR r2, ulICCIARConst + LDR r2, [r2] + LDR r0, [r2] + + /* Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for + future use. _RB_ Is this ever needed provided the start of the stack is + alligned on an 8-byte boundary? */ + MOV r2, sp + AND r2, r2, #4 + SUB sp, sp, r2 + + /* Call the interrupt handler. */ + PUSH {r0-r4, lr} + LDR r1, vApplicationIRQHandlerConst + BLX r1 + POP {r0-r4, lr} + ADD sp, sp, r2 + + CPSID i + DSB + ISB + + /* Write the value read from ICCIAR to ICCEOIR. */ + LDR r4, ulICCEOIRConst + LDR r4, [r4] + STR r0, [r4] + + /* Restore the old nesting count. */ + STR r1, [r3] + + /* A context switch is never performed if the nesting count is not 0. */ + CMP r1, #0 + BNE exit_without_switch + + /* Did the interrupt request a context switch? r1 holds the address of + ulPortYieldRequired and r0 the value of ulPortYieldRequired for future + use. */ + LDR r1, =ulPortYieldRequired + LDR r0, [r1] + CMP r0, #0 + BNE switch_before_exit + +exit_without_switch: + /* No context switch. Restore used registers, LR_irq and SPSR before + returning. */ + POP {r0-r4, r12} + CPS #IRQ_MODE + POP {LR} + MSR SPSR_cxsf, LR + POP {LR} + MOVS PC, LR + +switch_before_exit: + /* A context switch is to be performed. Clear the context switch pending + flag. */ + MOV r0, #0 + STR r0, [r1] + + /* Restore used registers, LR-irq and SPSR before saving the context + to the task stack. */ + POP {r0-r4, r12} + CPS #IRQ_MODE + POP {LR} + MSR SPSR_cxsf, LR + POP {LR} + portSAVE_CONTEXT + + /* Ensure bit 2 of the stack pointer is clear. */ + MOV r2, sp + AND r2, r2, #4 + SUB sp, sp, r2 + + /* Call the function that selects the new task to execute. + vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD + instructions, or 8 byte aligned stack allocated data. LR does not need + saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */ + LDR R0, vTaskSwitchContextConst + BLX R0 + + /* Restore the context of, and branch to, the task selected to execute + next. */ + portRESTORE_CONTEXT + +/****************************************************************************** + * If the application provides an implementation of vApplicationIRQHandler(), + * then it will get called directly without saving the FPU registers on + * interrupt entry, and this weak implementation of + * vApplicationIRQHandler() will not get called. + * + * If the application provides its own implementation of + * vApplicationFPUSafeIRQHandler() then this implementation of + * vApplicationIRQHandler() will be called, save the FPU registers, and then + * call vApplicationFPUSafeIRQHandler(). + * + * Therefore, if the application writer wants FPU registers to be saved on + * interrupt entry their IRQ handler must be called + * vApplicationFPUSafeIRQHandler(), and if the application writer does not want + * FPU registers to be saved on interrupt entry their IRQ handler must be + * called vApplicationIRQHandler(). + *****************************************************************************/ +.align 4 +.weak vApplicationIRQHandler +.type vApplicationIRQHandler, %function +vApplicationIRQHandler: + + PUSH {LR} + + #if defined( __ARM_FP ) + FMRX R1, FPSCR + VPUSH {D0-D15} + PUSH {R1} + + LDR r1, vApplicationFPUSafeIRQHandlerConst + BLX r1 + + POP {R0} + VPOP {D0-D15} + VMSR FPSCR, R0 + #endif /* __ARM_FP */ + + POP {PC} + +ulICCIARConst: .word ulICCIAR +ulICCEOIRConst: .word ulICCEOIR +ulICCPMRConst: .word ulICCPMR +pxCurrentTCBConst: .word pxCurrentTCB +ulCriticalNestingConst: .word ulCriticalNesting + +#if defined( __ARM_FP ) + ulPortTaskHasFPUContextConst: .word ulPortTaskHasFPUContext + vApplicationFPUSafeIRQHandlerConst: .word vApplicationFPUSafeIRQHandler +#endif /* __ARM_FP */ + +ulMaxAPIPriorityMaskConst: .word ulMaxAPIPriorityMask +vTaskSwitchContextConst: .word vTaskSwitchContext +vApplicationIRQHandlerConst: .word vApplicationIRQHandler +ulPortInterruptNestingConst: .word ulPortInterruptNesting + +.end diff --git a/portable/GCC/ARM_CR5/portmacro.h b/portable/GCC/ARM_CR5/portmacro.h new file mode 100644 index 000000000..35336e569 --- /dev/null +++ b/portable/GCC/ARM_CR5/portmacro.h @@ -0,0 +1,220 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +typedef uint32_t TickType_t; +#define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* Called at the end of an ISR that can cause a context switch. */ +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + { \ + extern uint32_t ulPortYieldRequired; \ + \ + if( xSwitchRequired != pdFALSE ) \ + { \ + ulPortYieldRequired = pdTRUE; \ + } \ + } + +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#define portYIELD() __asm volatile ( "SWI 0" ::: "memory" ); + + +/*----------------------------------------------------------- +* Critical section control +*----------------------------------------------------------*/ + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +extern uint32_t ulPortSetInterruptMask( void ); +extern void vPortClearInterruptMask( uint32_t ulNewMaskValue ); +extern void vPortInstallFreeRTOSVectorTable( void ); + +/* + * These macros do not globally disable/enable interrupts. They do mask off + * interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. + */ +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); +#define portDISABLE_INTERRUPTS() ulPortSetInterruptMask() +#define portENABLE_INTERRUPTS() vPortClearInterruptMask( 0 ) +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortClearInterruptMask( x ) + +/*-----------------------------------------------------------*/ + +/* + * Task function macros as described on the FreeRTOS.org WEB site. These are + * not required for this port but included in case common demo code that uses these + * macros is used. + */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* + * Prototype of the FreeRTOS tick handler. This must be installed as the + * handler for whichever peripheral is used to generate the RTOS tick. + */ +void FreeRTOS_Tick_Handler( void ); + +/* + * If configUSE_TASK_FPU_SUPPORT is set to 1, then tasks are created without an + * FPU context and must call vPortTaskUsesFPU() to allocate an FPU context + * prior to any FPU instructions. If configUSE_TASK_FPU_SUPPORT is set to 2, + * then all tasks have an FPU context allocated by default. + */ +#if ( configUSE_TASK_FPU_SUPPORT == 1 ) + void vPortTaskUsesFPU( void ); + #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() +#elif ( configUSE_TASK_FPU_SUPPORT == 2 ) + +/* + * Each task has an FPU context already, so define this function away to + * prevent it being called accidentally. + */ + #define vPortTaskUsesFPU() + #define portTASK_USES_FLOATING_POINT() +#endif /* configUSE_TASK_FPU_SUPPORT */ + +#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL ) +#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL ) + +/* Architecture specific optimisations. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +#if ( configASSERT_DEFINED == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif /* configASSERT */ + +#define portNOP() __asm volatile ( "NOP" ) + + +/* + * The number of bits to shift for an interrupt priority is dependent on the + * number of bits implemented by the interrupt controller. + */ +#if configUNIQUE_INTERRUPT_PRIORITIES == 16 + #define portPRIORITY_SHIFT 4 + #define portMAX_BINARY_POINT_VALUE 3 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 32 + #define portPRIORITY_SHIFT 3 + #define portMAX_BINARY_POINT_VALUE 2 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 64 + #define portPRIORITY_SHIFT 2 + #define portMAX_BINARY_POINT_VALUE 1 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 128 + #define portPRIORITY_SHIFT 1 + #define portMAX_BINARY_POINT_VALUE 0 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 256 + #define portPRIORITY_SHIFT 0 + #define portMAX_BINARY_POINT_VALUE 0 +#else /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */ + #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware +#endif /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */ + +/* Interrupt controller access addresses. */ +#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 ) +#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C ) +#define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 ) +#define portICCBPR_BINARY_POINT_OFFSET ( 0x08 ) +#define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 ) + +#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET ) +#define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) ) +#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ) +#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET ) +#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) +#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) ) +#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) ) + +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } /* extern C */ +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/ARM_CR82/README.md b/portable/GCC/ARM_CR82/README.md new file mode 100644 index 000000000..4b63bf904 --- /dev/null +++ b/portable/GCC/ARM_CR82/README.md @@ -0,0 +1,48 @@ +# Arm Cortex-R82 FreeRTOS Kernel Port + +# Overview + +- This directory contains the FreeRTOS Kernel port for Arm Cortex-R82 based on Armv8-R AArch64 architecture. +- It provides the portable layer required by the kernel to run on this architecture. + +# Supported toolchains + +The port is supported and tested on the following toolchains: + + * Arm Compiler for Embedded v6.23 (armclang). + * Arm GNU toolchain v14.2. + +# Cache Coherency + +- This port assumes the hardware or model is fully cache coherent. +- The port does not perform cache maintenance for shared buffers. +- If your hardware or model doesn't support full cache coherency, you must handle cache clean/invalidate operations, memory attributes, and any additional barriers in your BSP/application (especially around shared-memory regions). + +# MPU Support + +- This port supports the FreeRTOS MPU on both single-core and SMP (multi-core) configurations. Enable via `configENABLE_MPU = 1`; the port programs MPU regions per task on each active core. + +- Minimum MPU granularity and alignment: 64 bytes. Ensure any user‑defined region base and size are 64‑byte aligned. + +# SMP Multicore Bring-up + +For SMP systems using this port, the application only needs to start the scheduler on the primary core and issue an SVC from each secondary core once they are online. The kernel coordinates the rest and ensures all cores are properly managed. + +- Developer-facing summary: call `vTaskStartScheduler()` on the primary core; each secondary core, in its **reset handler**, performs its local init and then issues an SVC (immediate value `106`) to hand off to the kernel. The port will bring all cores under the scheduler. + +Primary core flow: + +1. Perform core-specific and shared initialization (e.g., set EL1 stack pointer, zero-initialize `.bss`). +2. Jump to `main()`, create user tasks, optionally pin tasks to specific cores. +3. Call `vTaskStartScheduler()` which invokes `xPortStartScheduler()`. +4. `xPortStartScheduler()` configures the primary core tick timer and signals secondary cores that shared init is complete using the `ucPrimaryCoreInitDoneFlag` variable. +5. Wait until all secondary cores report as brought up. +6. Once all cores are up, call `vPortRestoreContext()` to schedule the first task on the primary core. + +Secondary core flow (to be done in each core’s reset handler): + +1. Perform core-specific initialization (e.g., set EL1 stack pointer). +2. Wait for the primary core's signal that shared initialization is complete (i.e., `ucPrimaryCoreInitDoneFlag` set to 1). +3. Update `VBAR_EL1` from the boot vector table to the FreeRTOS vector table. +4. Initialize the GIC redistributor and enable SGIs so interrupts from the primary core are receivable; signal the primary that this secondary is online and ready by setting the its flag in the `ucSecondaryCoresReadyFlags` array. +5. Issue an SVC with immediate value `106` (i.e., `portSVC_START_FIRST_TASK`) to enter `FreeRTOS_SWI_Handler`, which will call `vPortRestoreContext()` based on the SVC number to start scheduling on this core. diff --git a/portable/GCC/ARM_CR82/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_CR82/mpu_wrappers_v2_asm.c new file mode 100644 index 000000000..2d08949d2 --- /dev/null +++ b/portable/GCC/ARM_CR82/mpu_wrappers_v2_asm.c @@ -0,0 +1,944 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2025 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" +#include "event_groups.h" +#include "stream_buffer.h" +#include "mpu_prototypes.h" +#include "mpu_syscall_numbers.h" +#include "portmacro.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#if ( configENABLE_MPU == 1 ) + + /* + * Common single-SVC dispatch: wrappers do only one SVC. + * The SVC handler decides whether to tail-call the implementation directly + * (privileged) or set up full system-call state (unprivileged). + */ + #define FREERTOS_MPU_SVC_DISPATCH( xSystemCallNumber ) \ + __asm volatile ( \ + "svc %0 \n" \ + : \ + : "i" ( xSystemCallNumber ) \ + : "memory" \ + ); + + #if ( INCLUDE_xTaskDelayUntil == 1 ) + + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_xTaskDelayUntil ); + } + + #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_xTaskAbortDelay ); + } + + #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskDelay == 1 ) + + void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_vTaskDelay ); + } + + #endif /* if ( INCLUDE_vTaskDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskPriorityGet == 1 ) + + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_uxTaskPriorityGet ); + } + + #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_eTaskGetState == 1 ) + + eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_eTaskGetState ); + } + + #endif /* if ( INCLUDE_eTaskGetState == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_vTaskGetInfo ); + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) + + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_xTaskGetIdleTaskHandle ); + } + + #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + + void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_vTaskSuspend ); + } + +/*-----------------------------------------------------------*/ + + void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_vTaskResume ); + } + + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + TickType_t MPU_xTaskGetTickCount( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_xTaskGetTickCount ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_uxTaskGetNumberOfTasks ); + } +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_ulTaskGetRunTimeCounter ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_ulTaskGetRunTimePercent ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ); + } + +/*-----------------------------------------------------------*/ + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_vTaskSetApplicationTaskTag ); + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_xTaskGetApplicationTaskTag ); + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ); + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ); + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_uxTaskGetSystemState ); + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) + + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_uxTaskGetStackHighWaterMark ); + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ); + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) + + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_xTaskGetCurrentTaskHandle ); + } + + #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetSchedulerState == 1 ) + + BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_xTaskGetSchedulerState ); + } + + #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */ +/*-----------------------------------------------------------*/ + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_vTaskSetTimeOutState ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_xTaskCheckForTimeOut ); + } +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_xTaskGenericNotify ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_xTaskGenericNotifyWait ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_ulTaskGenericNotifyTake ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_xTaskGenericNotifyStateClear ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_ulTaskGenericNotifyValueClear ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_xQueueGenericSend ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_uxQueueMessagesWaiting ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_uxQueueSpacesAvailable ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_xQueueReceive ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_xQueuePeek ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_xQueueSemaphoreTake ); + } +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) + + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_xQueueGetMutexHolder ); + } + + #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_xQueueTakeMutexRecursive ); + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_xQueueGiveMutexRecursive ); + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_xQueueSelectFromSet ); + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_xQueueAddToSet ); + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_vQueueAddToRegistry ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_vQueueUnregisterQueue ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_pcQueueGetName ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_pvTimerGetTimerID ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_vTimerSetTimerID ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_xTimerIsTimerActive ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_xTimerGenericCommandFromTask ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_pcTimerGetName ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_vTimerSetReloadMode ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_xTimerGetReloadMode ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_uxTimerGetReloadMode ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_xTimerGetPeriod ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_xTimerGetExpiryTime ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_xEventGroupWaitBits ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_xEventGroupClearBits ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_xEventGroupSetBits ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_xEventGroupSync ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_uxEventGroupGetNumber ); + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_vEventGroupSetNumber ); + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_xStreamBufferSend ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_xStreamBufferReceive ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_xStreamBufferIsFull ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_xStreamBufferIsEmpty ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_xStreamBufferSpacesAvailable ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_xStreamBufferBytesAvailable ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_xStreamBufferSetTriggerLevel ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + FREERTOS_MPU_SVC_DISPATCH( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + +#endif /* ( configENABLE_MPU == 1 ) */ diff --git a/portable/GCC/ARM_CR82/port.c b/portable/GCC/ARM_CR82/port.c new file mode 100644 index 000000000..5030a528e --- /dev/null +++ b/portable/GCC/ARM_CR82/port.c @@ -0,0 +1,1786 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2025-2026 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU includes. */ +#include "mpu_wrappers.h" +#include "mpu_syscall_numbers.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS + #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. Refer to Cortex-A equivalent: /* https://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors */ +#endif + +#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET + #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. Refer to Cortex-A equivalent: /* https://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors */ +#endif + +#ifndef configUNIQUE_INTERRUPT_PRIORITIES + #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. Refer to Cortex-A equivalent: /* https://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors */ +#endif + +#ifndef configSETUP_TICK_INTERRUPT + #error configSETUP_TICK_INTERRUPT() must be defined. Refer to Cortex-A equivalent: /* https://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors */ +#endif /* configSETUP_TICK_INTERRUPT */ + +#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY + #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. Refer to Cortex-A equivalent: /* https://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors */ +#endif + +#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0 + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0" +#endif + +#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority" +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + /* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice." + #endif +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/* In case security extensions are implemented. */ +#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 ) + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )" +#endif + +#ifndef configCLEAR_TICK_INTERRUPT + #error configCLEAR_TICK_INTERRUPT must be defined in FreeRTOSConfig.h to clear which ever interrupt was used to generate the tick interrupt. +#endif + +#if configNUMBER_OF_CORES < 1 + #error configNUMBER_OF_CORES must be set to 1 or greater. If the application is not using multiple cores then set configNUMBER_OF_CORES to 1. +#endif /* configNUMBER_OF_CORES < 1 */ + +#ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. +#endif /* #if ( configENABLE_MPU == 1 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 != 0) ) + #error Arm Cortex-R82 port supports only MPU Wrapper V2. +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 != 0) */ + +/* A critical section is exited when the critical section nesting count reaches + * this value. */ +#define portNO_CRITICAL_NESTING ( ( size_t ) 0 ) + +/* Macro to unmask all interrupt priorities. */ +#define portCLEAR_INTERRUPT_PRIORITIES_MASK() __asm volatile ( "SVC %0" : : "i" ( portSVC_UNMASK_ALL_INTERRUPTS ) : "memory" ) + +/* Macro to unmask all interrupt priorities from EL1. */ +#define portCLEAR_INTERRUPT_PRIORITIES_MASK_FROM_EL1() \ +{ \ + __asm volatile ( \ + " MSR DAIFSET, # 2 \n" \ + " DSB SY \n" \ + " ISB SY \n" \ + " MOV X0, %0 \n" \ + " MSR ICC_PMR_EL1, X0 \n" \ + " DSB SY \n" \ + " ISB SY \n" \ + " MSR DAIFCLR, # 2 \n" \ + " DSB SY \n" \ + " ISB SY \n" \ + : \ + : "i" ( portUNMASK_VALUE ) \ + ); \ +} + +/* Tasks are not created with a floating point context, but can be given a + * floating point context after they have been created. A variable is stored as + * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task + * does not have an FPU context, or any other value if the task does have an FPU + * context. */ +#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) + +/* Constants required to setup the initial task context. */ +#define portSP_ELx ( ( StackType_t ) 0x01 ) +#define portSP_EL0 ( ( StackType_t ) 0x00 ) +#define portEL1 ( ( StackType_t ) 0x04 ) +#define portEL0 ( ( StackType_t ) 0x00 ) + +#define portINITIAL_PSTATE_EL0 ( portEL0 | portSP_EL0 ) +#define portINITIAL_PSTATE_EL1 ( portEL1 | portSP_EL0 ) + +/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary + * point is zero. */ +#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 ) + +/* Masks all bits in the APSR other than the mode bits. */ +#define portAPSR_MODE_BITS_MASK ( 0x0C ) + +/* The I bit in the DAIF bits. */ +#define portDAIF_I ( 0x80 ) + +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portBIT_0_SET ( ( uint8_t ) 0x01 ) + +/* The space on the stack required to hold the FPU registers. + * There are 32 128-bit plus 2 64-bit status registers. */ +#define portFPU_REGISTER_WORDS ( ( 32 * 2 ) + 2 ) + +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Setup the Memory Protection Unit (MPU). + */ + PRIVILEGED_FUNCTION void vSetupMPU( void ); + + /** + * @brief Enable the Memory Protection Unit (MPU). + */ + PRIVILEGED_FUNCTION void vEnableMPU( void ); + + /** + * @brief Called from an ISR and returns the core ID the code is executing on. + * + * @return uint8_t The core ID. + */ + PRIVILEGED_FUNCTION uint8_t ucPortGetCoreIDFromIsr( void ); + + /** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + PRIVILEGED_FUNCTION BaseType_t xPortIsTaskPrivileged( void ); + + /** + * @brief Extract MPU region's access permissions from the Protection Region Base Address Register + * (PRBAR_EL1) value. + * + * @param ullPrbarEl1Value PRBAR_EL1 value for the MPU region. + * + * @return uint32_t Access permissions. + */ + PRIVILEGED_FUNCTION static uint32_t prvGetRegionAccessPermissions( uint64_t ullPrbarEl1Value ); + + /** + * @brief Does the necessary work to enter a system call. + * + * @param pullPrivilegedOnlyTaskStack The task's privileged SP when the SVC was raised. + * @param ucSystemCallNumber The system call number of the system call. + */ + PRIVILEGED_FUNCTION void vSystemCallEnter( uint64_t * pullPrivilegedOnlyTaskStack, + uint8_t ucSystemCallNumber ); + + /** + * @brief Raise SVC for exiting from a system call. + */ + PRIVILEGED_FUNCTION __attribute__( ( naked ) ) void vRequestSystemCallExit( void ); + + /** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param ullSystemCallReturnValue The actual system call return value. + */ + PRIVILEGED_FUNCTION void vSystemCallExit( uint64_t ullSystemCallReturnValue ); + +#endif /* #if ( configENABLE_MPU == 1 ) */ + +/* + * Starts the first task executing. This function is necessarily written in + * assembly code so is implemented in portASM.s. + */ +extern void vPortRestoreTaskContext( void ); +extern void vGIC_EnableIRQ( uint32_t ulInterruptID ); +extern void vGIC_SetPriority( uint32_t ulInterruptID, uint32_t ulPriority ); +extern void vGIC_PowerUpRedistributor( void ); +extern void vGIC_EnableCPUInterface( void ); + +/*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES == 1 ) + + PRIVILEGED_DATA volatile uint64_t ullCriticalNesting = 0ULL; + + /* Saved as part of the task context. If ullPortTaskHasFPUContext is non-zero + * then floating point context must be saved and restored for the task. */ + PRIVILEGED_DATA uint64_t ullPortTaskHasFPUContext = pdFALSE; + + /* Set to 1 to pend a context switch from an ISR. */ + PRIVILEGED_DATA uint64_t ullPortYieldRequired = pdFALSE; + + /* Counts the interrupt nesting depth. A context switch is only performed if + * if the nesting depth is 0. */ + PRIVILEGED_DATA uint64_t ullPortInterruptNesting = 0; + +#else /* #if ( configNUMBER_OF_CORES == 1 ) */ + PRIVILEGED_DATA volatile uint64_t ullCriticalNestings[ configNUMBER_OF_CORES ] = { 0 }; + + /* Flags to check if the secondary cores are ready. */ + PRIVILEGED_DATA volatile uint8_t ucSecondaryCoresReadyFlags[ configNUMBER_OF_CORES - 1 ] = { 0 }; + + /* Flag to signal that the primary core has done all the shared initialisations. */ + PRIVILEGED_DATA volatile uint8_t ucPrimaryCoreInitDoneFlag = 0; + + /* Saved as part of the task context. If ullPortTaskHasFPUContext is non-zero + * then floating point context must be saved and restored for the task. */ + PRIVILEGED_DATA uint64_t ullPortTaskHasFPUContext[ configNUMBER_OF_CORES ] = { pdFALSE }; + + /* Set to 1 to pend a context switch from an ISR. */ + PRIVILEGED_DATA uint64_t ullPortYieldRequired[ configNUMBER_OF_CORES ] = { pdFALSE }; + + /* Counts the interrupt nesting depth. A context switch is only performed if + * if the nesting depth is 0. */ + PRIVILEGED_DATA uint64_t ullPortInterruptNestings[ configNUMBER_OF_CORES ] = { 0 }; + +#endif /* #if ( configNUMBER_OF_CORES == 1 ) */ + +#if ( configENABLE_MPU == 1 ) + /* Set to pdTRUE when the scheduler is started. */ + PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE; +#endif /* ( configENABLE_MPU == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged, + xMPU_SETTINGS * xMPUSettings ) + { + uint32_t ulIndex = 0; + + /* Layout must match portRESTORE_CONTEXT pop order (descending stack): + * 1) FPU flag, 2) Critical nesting, 3) Optional FPU save area, + * 4) ELR (PC), 5) SPSR (PSTATE), 6) GPRs in restore order pairs. + */ + + /* 1) FPU flag and 2) Critical nesting. */ + #if ( configUSE_TASK_FPU_SUPPORT == portTASK_NO_FPU_CONTEXT_BY_DEFAULT ) + xMPUSettings->ullContext[ ulIndex++ ] = portNO_FLOATING_POINT_CONTEXT; /* FPU flag */ + xMPUSettings->ullContext[ ulIndex++ ] = portNO_CRITICAL_NESTING; /* Critical nesting */ + #elif ( configUSE_TASK_FPU_SUPPORT == portTASK_HAVE_FPU_CONTEXT_BY_DEFAULT ) + xMPUSettings->ullContext[ ulIndex++ ] = pdTRUE; /* FPU flag */ + xMPUSettings->ullContext[ ulIndex++ ] = portNO_CRITICAL_NESTING; /* Critical nesting */ + #if ( configNUMBER_OF_CORES == 1 ) + ullPortTaskHasFPUContext = pdTRUE; + #else + ullPortTaskHasFPUContext[ portGET_CORE_ID() ] = pdTRUE; + #endif + #else + #error "Invalid configUSE_TASK_FPU_SUPPORT setting - must be 1 or 2." + #endif + + /* 3) Optional FPU save area immediately after the flag+critical pair. */ + #if ( configUSE_TASK_FPU_SUPPORT == portTASK_HAVE_FPU_CONTEXT_BY_DEFAULT ) + memset( &xMPUSettings->ullContext[ ulIndex ], 0x00, portFPU_REGISTER_WORDS * sizeof( StackType_t ) ); + ulIndex += portFPU_REGISTER_WORDS; + #endif + + /* 4) ELR (PC) and 5) SPSR (PSTATE). */ + xMPUSettings->ullContext[ ulIndex++ ] = ( StackType_t ) pxCode; /* ELR */ + + if( xRunPrivileged == pdTRUE ) + { + xMPUSettings->ullContext[ ulIndex++ ] = portINITIAL_PSTATE_EL1; /* SPSR */ + } + else + { + xMPUSettings->ullContext[ ulIndex++ ] = portINITIAL_PSTATE_EL0; /* SPSR */ + } + + /* 6) General-purpose registers in the order expected by restoreallgpregisters. */ + xMPUSettings->ullContext[ ulIndex++ ] = ( StackType_t ) 0x00; /* X30 (LR) */ + xMPUSettings->ullContext[ ulIndex++ ] = ( StackType_t ) 0x00; /* XZR (dummy) */ + + xMPUSettings->ullContext[ ulIndex++ ] = 0x2828282828282828ULL; /* X28 */ + xMPUSettings->ullContext[ ulIndex++ ] = 0x2929292929292929ULL; /* X29 */ + + xMPUSettings->ullContext[ ulIndex++ ] = 0x2626262626262626ULL; /* X26 */ + xMPUSettings->ullContext[ ulIndex++ ] = 0x2727272727272727ULL; /* X27 */ + + xMPUSettings->ullContext[ ulIndex++ ] = 0x2424242424242424ULL; /* X24 */ + xMPUSettings->ullContext[ ulIndex++ ] = 0x2525252525252525ULL; /* X25 */ + + xMPUSettings->ullContext[ ulIndex++ ] = 0x2222222222222222ULL; /* X22 */ + xMPUSettings->ullContext[ ulIndex++ ] = 0x2323232323232323ULL; /* X23 */ + + xMPUSettings->ullContext[ ulIndex++ ] = 0x2020202020202020ULL; /* X20 */ + xMPUSettings->ullContext[ ulIndex++ ] = 0x2121212121212121ULL; /* X21 */ + + xMPUSettings->ullContext[ ulIndex++ ] = 0x1818181818181818ULL; /* X18 */ + xMPUSettings->ullContext[ ulIndex++ ] = 0x1919191919191919ULL; /* X19 */ + + xMPUSettings->ullContext[ ulIndex++ ] = 0x1616161616161616ULL; /* X16 */ + xMPUSettings->ullContext[ ulIndex++ ] = 0x1717171717171717ULL; /* X17 */ + + xMPUSettings->ullContext[ ulIndex++ ] = 0x1414141414141414ULL; /* X14 */ + xMPUSettings->ullContext[ ulIndex++ ] = 0x1515151515151515ULL; /* X15 */ + + xMPUSettings->ullContext[ ulIndex++ ] = 0x1212121212121212ULL; /* X12 */ + xMPUSettings->ullContext[ ulIndex++ ] = 0x1313131313131313ULL; /* X13 */ + + xMPUSettings->ullContext[ ulIndex++ ] = 0x1010101010101010ULL; /* X10 */ + xMPUSettings->ullContext[ ulIndex++ ] = 0x1111111111111111ULL; /* X11 */ + + xMPUSettings->ullContext[ ulIndex++ ] = 0x0808080808080808ULL; /* X8 */ + xMPUSettings->ullContext[ ulIndex++ ] = 0x0909090909090909ULL; /* X9 */ + + xMPUSettings->ullContext[ ulIndex++ ] = 0x0606060606060606ULL; /* X6 */ + xMPUSettings->ullContext[ ulIndex++ ] = 0x0707070707070707ULL; /* X7 */ + + xMPUSettings->ullContext[ ulIndex++ ] = 0x0404040404040404ULL; /* X4 */ + xMPUSettings->ullContext[ ulIndex++ ] = 0x0505050505050505ULL; /* X5 */ + + xMPUSettings->ullContext[ ulIndex++ ] = 0x0202020202020202ULL; /* X2 */ + xMPUSettings->ullContext[ ulIndex++ ] = 0x0303030303030303ULL; /* X3 */ + + xMPUSettings->ullContext[ ulIndex++ ] = ( StackType_t ) pvParameters; /* X0 */ + xMPUSettings->ullContext[ ulIndex++ ] = 0x0101010101010101ULL; /* X1 */ + + if( xRunPrivileged == pdTRUE ) + { + xMPUSettings->ullTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; + } + else + { + xMPUSettings->ullTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG ); + } + + xMPUSettings->ullTaskUnprivilegedSP = ( ( uint64_t ) pxTopOfStack & portMPU_PRBAR_EL1_ADDRESS_MASK ); + + return &( xMPUSettings->ullContext[ 0 ] ); + } + +#else /* #if ( configENABLE_MPU == 1 ) */ + + /* + * See header file for description. + */ + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) + { + /* Setup the initial stack of the task. The stack is set exactly as + * expected by the portRESTORE_CONTEXT() macro. */ + + /* First all the general purpose registers. */ + pxTopOfStack--; + *pxTopOfStack = 0x0101010101010101ULL; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + *pxTopOfStack = 0x0303030303030303ULL; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = 0x0202020202020202ULL; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = 0x0505050505050505ULL; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = 0x0404040404040404ULL; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = 0x0707070707070707ULL; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = 0x0606060606060606ULL; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = 0x0909090909090909ULL; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = 0x0808080808080808ULL; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = 0x1111111111111111ULL; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = 0x1010101010101010ULL; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = 0x1313131313131313ULL; /* R13 */ + pxTopOfStack--; + *pxTopOfStack = 0x1212121212121212ULL; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = 0x1515151515151515ULL; /* R15 */ + pxTopOfStack--; + *pxTopOfStack = 0x1414141414141414ULL; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = 0x1717171717171717ULL; /* R17 */ + pxTopOfStack--; + *pxTopOfStack = 0x1616161616161616ULL; /* R16 */ + pxTopOfStack--; + *pxTopOfStack = 0x1919191919191919ULL; /* R19 */ + pxTopOfStack--; + *pxTopOfStack = 0x1818181818181818ULL; /* R18 */ + pxTopOfStack--; + *pxTopOfStack = 0x2121212121212121ULL; /* R21 */ + pxTopOfStack--; + *pxTopOfStack = 0x2020202020202020ULL; /* R20 */ + pxTopOfStack--; + *pxTopOfStack = 0x2323232323232323ULL; /* R23 */ + pxTopOfStack--; + *pxTopOfStack = 0x2222222222222222ULL; /* R22 */ + pxTopOfStack--; + *pxTopOfStack = 0x2525252525252525ULL; /* R25 */ + pxTopOfStack--; + *pxTopOfStack = 0x2424242424242424ULL; /* R24 */ + pxTopOfStack--; + *pxTopOfStack = 0x2727272727272727ULL; /* R27 */ + pxTopOfStack--; + *pxTopOfStack = 0x2626262626262626ULL; /* R26 */ + pxTopOfStack--; + *pxTopOfStack = 0x2929292929292929ULL; /* R29 */ + pxTopOfStack--; + *pxTopOfStack = 0x2828282828282828ULL; /* R28 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x00; /* XZR - has no effect, used so there are an even number of registers. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x00; /* R30 - procedure call link register. */ + + pxTopOfStack--; + *pxTopOfStack = portINITIAL_PSTATE_EL0; + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* Exception return address. */ + + #if ( configUSE_TASK_FPU_SUPPORT == portTASK_NO_FPU_CONTEXT_BY_DEFAULT ) + { + /* The task will start with a critical nesting count of 0 as interrupts are + * enabled. */ + pxTopOfStack--; + *pxTopOfStack = portNO_CRITICAL_NESTING; + + /* The task will start without a floating point context. A task that + * uses the floating point hardware must call vPortTaskUsesFPU() before + * executing any floating point instructions. */ + pxTopOfStack--; + *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT; + } + #elif ( configUSE_TASK_FPU_SUPPORT == portTASK_HAVE_FPU_CONTEXT_BY_DEFAULT ) + { + /* The task will start with a floating point context. Leave enough + * space for the registers - and ensure they are initialised to 0. */ + pxTopOfStack -= portFPU_REGISTER_WORDS; + memset( pxTopOfStack, 0x00, portFPU_REGISTER_WORDS * sizeof( StackType_t ) ); + + /* The task will start with a critical nesting count of 0 as interrupts are + * enabled. */ + pxTopOfStack--; + *pxTopOfStack = portNO_CRITICAL_NESTING; + + pxTopOfStack--; + *pxTopOfStack = pdTRUE; + #if ( configNUMBER_OF_CORES == 1 ) + ullPortTaskHasFPUContext = pdTRUE; + #else + ullPortTaskHasFPUContext[ portGET_CORE_ID() ] = pdTRUE; + #endif + } + #else /* if ( configUSE_TASK_FPU_SUPPORT == portTASK_NO_FPU_CONTEXT_BY_DEFAULT ) */ + { + #error "Invalid configUSE_TASK_FPU_SUPPORT setting - configUSE_TASK_FPU_SUPPORT must be set to 1, 2, or left undefined." + } + #endif /* if ( configUSE_TASK_FPU_SUPPORT == portTASK_NO_FPU_CONTEXT_BY_DEFAULT ) */ + + return pxTopOfStack; + + } + +#endif /* #if ( configENABLE_MPU == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Store a task's MPU settings in its TCB. + * + * @ingroup Task Context + * @ingroup MPU Control + * + * @param xMPUSettings The MPU settings in TCB. + * @param xRegions The MPU regions requested by the task. + * @param pxBottomOfStack The base address of the task's Stack. + * @param xStackDepth The length of the task's stack. + */ + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + StackType_t xStackDepth ) /* PRIVILEGED_FUNCTION */ + { + uint64_t ullRegionStartAddress, ullRegionEndAddress; + uint8_t ucIndex = 0, ucRegionNumber; + + #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint64_t * __privileged_sram_start__; + extern uint64_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint64_t __privileged_sram_start__[]; + extern uint64_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR_EL1. */ + xMPUSettings->ullMairEl1 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_EL1_ATTR0_POS ) & portMPU_MAIR_EL1_ATTR0_MASK ); + xMPUSettings->ullMairEl1 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_EL1_ATTR1_POS ) & portMPU_MAIR_EL1_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( xStackDepth > 0 ) + { + ullRegionStartAddress = ( uint64_t ) pxBottomOfStack; + ullRegionEndAddress = ( uint64_t ) pxBottomOfStack + ( xStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because this + * region is already protected using an MPU region and ARMv8-R does + * not allow overlapping MPU regions. + */ + if( ( ullRegionStartAddress >= ( uint64_t ) __privileged_sram_start__ ) && + ( ullRegionEndAddress <= ( uint64_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ portSTACK_REGION_INDEX ].ullPrbarEl1 = 0; + xMPUSettings->xRegionsSettings[ portSTACK_REGION_INDEX ].ullPrlarEl1 = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ullRegionStartAddress &= portMPU_PRBAR_EL1_ADDRESS_MASK; + ullRegionEndAddress &= portMPU_PRLAR_EL1_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ portSTACK_REGION_INDEX ].ullPrbarEl1 = ( ullRegionStartAddress ) | + ( portMPU_REGION_INNER_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ portSTACK_REGION_INDEX ].ullPrlarEl1 = ( ullRegionEndAddress ) | + ( portMPU_PRLAR_EL1_ATTR_INDEX0 ) | + ( portMPU_PRLAR_EL1_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ucRegionNumber = 1; ucRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ucRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. + * The minimum region size is 64 Bytes. + */ + if( xRegions != NULL ) + { + /* Configure the region only if the base address is non-NULL. + * The user may choose to use only a subset of the available MPU regions. + * This check prevents undefined regions (i.e. regions with a NULL base + * address) from being configured and from triggering the size-check + * assertion below. + */ + if ( xRegions[ ucIndex ].pvBaseAddress != NULL ) + { + configASSERT( xRegions[ ucIndex ].ulLengthInBytes >= 64UL ); + + uint64_t ullPrbarEl1RegValue, ullPrlarEl1RegValue; + + /* Translate the generic region definition contained in xRegions + * into the ARMv8-R specific MPU settings that are then stored in + * xMPUSettings. + */ + ullRegionStartAddress = ( ( uint64_t ) xRegions[ ucIndex ].pvBaseAddress ) & portMPU_PRBAR_EL1_ADDRESS_MASK; + ullRegionEndAddress = ( uint64_t ) xRegions[ ucIndex ].pvBaseAddress + xRegions[ ucIndex ].ulLengthInBytes - 1; + ullRegionEndAddress &= portMPU_PRLAR_EL1_ADDRESS_MASK; + + /* Checks for overlaps with another user defined regions and stack region, which are already configured. */ + for( uint8_t ucUserRegionNumber = 0; ucUserRegionNumber < portNUM_CONFIGURABLE_REGIONS; ucUserRegionNumber++ ) + { + /* Check for overlap. */ + if( ( portIS_ADDRESS_WITHIN_RANGE( ullRegionStartAddress, + ( xMPUSettings->xRegionsSettings[ ucUserRegionNumber ].ullPrbarEl1 & portMPU_PRBAR_EL1_ADDRESS_MASK ), + ( xMPUSettings->xRegionsSettings[ ucUserRegionNumber ].ullPrlarEl1 & portMPU_PRLAR_EL1_ADDRESS_MASK ) ) || + ( portIS_ADDRESS_WITHIN_RANGE( ullRegionEndAddress, + ( xMPUSettings->xRegionsSettings[ ucUserRegionNumber ].ullPrbarEl1 & portMPU_PRBAR_EL1_ADDRESS_MASK ), + ( xMPUSettings->xRegionsSettings[ ucUserRegionNumber ].ullPrlarEl1 & portMPU_PRLAR_EL1_ADDRESS_MASK ) ) ) ) ) + { + /* Overlap detected - assert. */ + configASSERT( NULL ); + } + } + + /* Checks for overlaps with kernel programmed regions which are already programmed as part of vSetupMPU. */ + for (uint8_t ucProgrammedRegionIndex = 0; ucProgrammedRegionIndex < 4; ucProgrammedRegionIndex++) + { + __asm volatile ( "msr PRSELR_EL1, %0" : : "r" ( ( uint64_t ) ucProgrammedRegionIndex ) ); + + __asm volatile ( "mrs %0, PRBAR_EL1" : "=r" ( ullPrbarEl1RegValue ) ); + ullPrbarEl1RegValue &= portMPU_PRBAR_EL1_ADDRESS_MASK; + + __asm volatile ( "mrs %0, PRLAR_EL1" : "=r" ( ullPrlarEl1RegValue ) ); + ullPrlarEl1RegValue &= portMPU_PRLAR_EL1_ADDRESS_MASK; + + /* Check for overlap. */ + if( ( portIS_ADDRESS_WITHIN_RANGE( ullRegionStartAddress, + ullPrbarEl1RegValue, + ullPrlarEl1RegValue ) ) || + ( portIS_ADDRESS_WITHIN_RANGE( ullRegionEndAddress, + ullPrbarEl1RegValue, + ullPrlarEl1RegValue ) ) ) + { + /* Overlap detected - assert. */ + configASSERT( NULL ); + } + } + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ucRegionNumber ].ullPrbarEl1 = ( ullRegionStartAddress ); + + /* RO/RW. */ + if( ( xRegions[ ucIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ucRegionNumber ].ullPrbarEl1 |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ucRegionNumber ].ullPrbarEl1 |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ ucIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ucRegionNumber ].ullPrbarEl1 |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* SH. */ + if( ( xRegions[ ucIndex ].ulParameters & tskMPU_REGION_INNER_SHAREABLE ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ucRegionNumber ].ullPrbarEl1 |= ( portMPU_REGION_INNER_SHAREABLE ); + } + else if( ( xRegions[ ucIndex ].ulParameters & tskMPU_REGION_OUTER_SHAREABLE ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ucRegionNumber ].ullPrbarEl1 |= ( portMPU_REGION_OUTER_SHAREABLE ); + } + else + { + xMPUSettings->xRegionsSettings[ ucRegionNumber ].ullPrbarEl1 |= ( portMPU_REGION_NON_SHAREABLE ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ucRegionNumber ].ullPrlarEl1 = ( ullRegionEndAddress ) | + ( portMPU_PRLAR_EL1_REGION_ENABLE ); + + /* Normal memory/ Device memory. */ + if( ( xRegions[ ucIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR_EL1 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ucRegionNumber ].ullPrlarEl1 |= portMPU_PRLAR_EL1_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR_EL1 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ucRegionNumber ].ullPrlarEl1 |= portMPU_PRLAR_EL1_ATTR_INDEX0; + } + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ucRegionNumber ].ullPrbarEl1 = 0UL; + xMPUSettings->xRegionsSettings[ ucRegionNumber ].ullPrlarEl1 = 0UL; + } + + ucIndex++; + } + + } + /*-----------------------------------------------------------*/ + + void vSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. + */ + extern uint64_t * __privileged_functions_start__; + extern uint64_t * __privileged_functions_end__; + extern uint64_t * __syscalls_flash_start__; + extern uint64_t * __syscalls_flash_end__; + extern uint64_t * __unprivileged_flash_start__; + extern uint64_t * __unprivileged_flash_end__; + extern uint64_t * __privileged_sram_start__; + extern uint64_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint64_t __privileged_functions_start__[]; + extern uint64_t __privileged_functions_end__[]; + extern uint64_t __syscalls_flash_start__[]; + extern uint64_t __syscalls_flash_end__[]; + extern uint64_t __unprivileged_flash_start__[]; + extern uint64_t __unprivileged_flash_end__[]; + extern uint64_t __privileged_sram_start__[]; + extern uint64_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 16 or 32. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 16 ) || ( configTOTAL_MPU_REGIONS == 32 ) ); + + /* MAIR_EL1 - Index 0. */ + uint64_t ullMairEl1RegValue = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_EL1_ATTR0_POS ) & portMPU_MAIR_EL1_ATTR0_MASK ); + /* MAIR_EL1 - Index 1. */ + ullMairEl1RegValue |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_EL1_ATTR1_POS ) & portMPU_MAIR_EL1_ATTR1_MASK ); + + __asm volatile ( "msr MAIR_EL1, %0" : : "r" ( ullMairEl1RegValue ) ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. + */ + uint64_t ullPrselrEl1RegValue = portPRIVILEGED_FLASH_REGION; + __asm volatile ( "msr PRSELR_EL1, %0" : : "r" ( ullPrselrEl1RegValue ) ); + + uint64_t ullPrbarEl1RegValue = ( ( ( uint64_t ) __privileged_functions_start__ ) & portMPU_PRBAR_EL1_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + __asm volatile ( "msr PRBAR_EL1, %0" : : "r" ( ullPrbarEl1RegValue ) ); + + uint64_t ullPrlarEl1RegValue = ( ( ( uint64_t ) __privileged_functions_end__ ) & portMPU_PRLAR_EL1_ADDRESS_MASK ) | + ( portMPU_PRLAR_EL1_ATTR_INDEX0 ) | + ( portMPU_PRLAR_EL1_REGION_ENABLE ); + __asm volatile ( "msr PRLAR_EL1, %0" : : "r" ( ullPrlarEl1RegValue ) ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. + */ + ullPrselrEl1RegValue = portUNPRIVILEGED_FLASH_REGION; + __asm volatile ( "msr PRSELR_EL1, %0" : : "r" ( ullPrselrEl1RegValue ) ); + + ullPrbarEl1RegValue = ( ( ( uint64_t ) __unprivileged_flash_start__ ) & portMPU_PRBAR_EL1_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + __asm volatile ( "msr PRBAR_EL1, %0" : : "r" ( ullPrbarEl1RegValue ) ); + + ullPrlarEl1RegValue = ( ( ( uint64_t ) __unprivileged_flash_end__ ) & portMPU_PRLAR_EL1_ADDRESS_MASK ) | + ( portMPU_PRLAR_EL1_ATTR_INDEX0 ) | + ( portMPU_PRLAR_EL1_REGION_ENABLE ); + __asm volatile ( "msr PRLAR_EL1, %0" : : "r" ( ullPrlarEl1RegValue ) ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. + */ + ullPrselrEl1RegValue = portUNPRIVILEGED_SYSCALLS_REGION; + __asm volatile ( "msr PRSELR_EL1, %0" : : "r" ( ullPrselrEl1RegValue ) ); + + ullPrbarEl1RegValue = ( ( ( uint64_t ) __syscalls_flash_start__ ) & portMPU_PRBAR_EL1_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + __asm volatile ( "msr PRBAR_EL1, %0" : : "r" ( ullPrbarEl1RegValue ) ); + + ullPrlarEl1RegValue = ( ( ( uint64_t ) __syscalls_flash_end__ ) & portMPU_PRLAR_EL1_ADDRESS_MASK ) | + ( portMPU_PRLAR_EL1_ATTR_INDEX0 ) | + ( portMPU_PRLAR_EL1_REGION_ENABLE ); + __asm volatile ( "msr PRLAR_EL1, %0" : : "r" ( ullPrlarEl1RegValue ) ); + + /* Setup RAM containing kernel data for privileged access only. */ + ullPrselrEl1RegValue = portPRIVILEGED_RAM_REGION; + __asm volatile ( "msr PRSELR_EL1, %0" : : "r" ( ullPrselrEl1RegValue ) ); + + ullPrbarEl1RegValue = ( ( ( uint64_t ) __privileged_sram_start__ ) & portMPU_PRBAR_EL1_ADDRESS_MASK ) | + ( portMPU_REGION_INNER_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + __asm volatile ( "msr PRBAR_EL1, %0" : : "r" ( ullPrbarEl1RegValue ) ); + + ullPrlarEl1RegValue = ( ( ( uint64_t ) __privileged_sram_end__ ) & portMPU_PRLAR_EL1_ADDRESS_MASK ) | + ( portMPU_PRLAR_EL1_ATTR_INDEX0 ) | + ( portMPU_PRLAR_EL1_REGION_ENABLE ); + __asm volatile ( "msr PRLAR_EL1, %0" : : "r" ( ullPrlarEl1RegValue ) ); + } + /*-----------------------------------------------------------*/ + + void vEnableMPU( void ) /* PRIVILEGED_FUNCTION */ + { + uint64_t ullSctlrEl1RegValue; + + __asm volatile ( "mrs %0, SCTLR_EL1" : "=r" ( ullSctlrEl1RegValue ) ); + /* Enable the MPU. Also enable privileged access to the + * background region. + */ + ullSctlrEl1RegValue |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + __asm volatile ( "msr SCTLR_EL1, %0" : : "r" ( ullSctlrEl1RegValue ) ); + + /* Ensure the write to SCTLR_EL1 is committed before + * returning. + */ + __asm volatile ( "isb" ); + } + /*-----------------------------------------------------------*/ + + BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xTaskIsPrivileged = pdFALSE; + + #if ( configNUMBER_OF_CORES == 1 ) + extern TaskHandle_t pxCurrentTCB; + xMPU_SETTINGS * pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + #else + extern TaskHandle_t pxCurrentTCBs[ configNUMBER_OF_CORES ]; + xMPU_SETTINGS * pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCBs[ portGET_CORE_ID_FROM_ISR() ] ); + #endif + + if( ( pxMpuSettings->ullTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xTaskIsPrivileged = pdTRUE; + } + + return xTaskIsPrivileged; + } + /*-----------------------------------------------------------*/ + + static uint32_t prvGetRegionAccessPermissions( uint64_t ullPrbarEl1Value ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessPermissions = 0; + + if( ( ullPrbarEl1Value & portMPU_PRBAR_EL1_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_ONLY ) + { + ulAccessPermissions = tskMPU_READ_PERMISSION; + } + + if( ( ullPrbarEl1Value & portMPU_PRBAR_EL1_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_WRITE ) + { + ulAccessPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION ); + } + + return ulAccessPermissions; + } + /*-----------------------------------------------------------*/ + + BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, + uint32_t ulBufferLength, + uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */ + + { + uint32_t i; + uint64_t ullBufferStartAddress, ullBufferEndAddress; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else if( ( xTaskMpuSettings->ullTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( portADD_UINT64_WILL_OVERFLOW( ( ( uint64_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE ) + { + ullBufferStartAddress = ( uint64_t ) pvBuffer; + ullBufferEndAddress = ( ( ( uint64_t ) pvBuffer ) + ulBufferLength - 1UL ); + + for( i = 0; i < portTOTAL_NUM_REGIONS; i++ ) + { + /* Is the MPU region enabled? */ + if( ( xTaskMpuSettings->xRegionsSettings[ i ].ullPrlarEl1 & portMPU_PRLAR_EL1_REGION_ENABLE ) == portMPU_PRLAR_EL1_REGION_ENABLE ) + { + if( portIS_ADDRESS_WITHIN_RANGE( ullBufferStartAddress, + portEXTRACT_FIRST_ADDRESS_FROM_PRBAR_EL1( xTaskMpuSettings->xRegionsSettings[ i ].ullPrbarEl1 ), + portEXTRACT_LAST_ADDRESS_FROM_PRLAR_EL1( xTaskMpuSettings->xRegionsSettings[ i ].ullPrlarEl1 ) ) && + portIS_ADDRESS_WITHIN_RANGE( ullBufferEndAddress, + portEXTRACT_FIRST_ADDRESS_FROM_PRBAR_EL1( xTaskMpuSettings->xRegionsSettings[ i ].ullPrbarEl1 ), + portEXTRACT_LAST_ADDRESS_FROM_PRLAR_EL1( xTaskMpuSettings->xRegionsSettings[ i ].ullPrlarEl1 ) ) && + portIS_AUTHORIZED( ulAccessRequested, + prvGetRegionAccessPermissions( xTaskMpuSettings->xRegionsSettings[ i ].ullPrbarEl1 ) ) ) + { + xAccessGranted = pdTRUE; + break; + } + } + } + } + } + + return xAccessGranted; + } + /*-----------------------------------------------------------*/ + + void vSystemCallEnter( uint64_t * pullPrivilegedOnlyTaskStack, + uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */ + { + #if ( configNUMBER_OF_CORES == 1 ) + extern TaskHandle_t pxCurrentTCB; + #else + extern TaskHandle_t pxCurrentTCBs[ configNUMBER_OF_CORES ]; + #endif + extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ]; + xMPU_SETTINGS * pxMpuSettings; + uint64_t ullSystemCallLocation; /* Address where SVC was raised. */ + __asm volatile ( "MRS %0, ELR_EL1" : "=r" ( ullSystemCallLocation ) ); + + #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. + */ + extern uint64_t * __syscalls_flash_start__; + extern uint64_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint64_t __syscalls_flash_start__[]; + extern uint64_t __syscalls_flash_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + #if ( configNUMBER_OF_CORES == 1 ) + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + #else + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCBs[ portGET_CORE_ID_FROM_ISR() ] ); + #endif + + /* Checks: + * 1. SVC is raised from the system call section (i.e. application is + * not raising SVC directly). + * 2. We do not need to check that ucSystemCallNumber is within range + * because the assembly SVC handler checks that before calling + * this function. + */ + if( ( ullSystemCallLocation >= ( uint64_t ) __syscalls_flash_start__ ) && + ( ullSystemCallLocation <= ( uint64_t ) __syscalls_flash_end__ ) && + ( uxSystemCallImplementations[ ucSystemCallNumber ] != 0 ) ) + { + /* Store the value of the Link Register before the SVC was raised. + * It contains the address of the caller of the System Call entry + * point (i.e. the caller of the MPU_). We need to restore it + * when we exit from the system call. + */ + pxMpuSettings->xSystemCallInfo.ullLinkRegisterAtSystemCallEntry = pullPrivilegedOnlyTaskStack[ portOFFSET_TO_LR ]; + + /* Capture user-mode SP at system call entry. */ + uint64_t ullUserSpAtEntry; + __asm volatile ( "MRS %0, SP_EL0" : "=r" ( ullUserSpAtEntry ) ); + pxMpuSettings->xSystemCallInfo.ullUserSPAtSystemCallEntry = ullUserSpAtEntry; + + /* Setup the MPU_ inputs, the system call stack, and SPSR. */ + __asm volatile ( + "MOV X0, %0 \n" + "MOV X1, %1 \n" + "MOV X2, %2 \n" + "MOV X3, %3 \n" + "MSR ELR_EL1, %4 \n" + "MSR SP_EL0, %5 \n" + "MSR SPSR_EL1, %6 \n" + : + : "r" ( pullPrivilegedOnlyTaskStack[ portOFFSET_TO_X0 ] ), + "r" ( pullPrivilegedOnlyTaskStack[ portOFFSET_TO_X1 ] ), + "r" ( pullPrivilegedOnlyTaskStack[ portOFFSET_TO_X2 ] ), + "r" ( pullPrivilegedOnlyTaskStack[ portOFFSET_TO_X3 ] ), + "r" ( ( uint64_t ) uxSystemCallImplementations[ ucSystemCallNumber ] ), + "r" ( &( pxMpuSettings->ullContext[ MAX_CONTEXT_SIZE + configSYSTEM_CALL_STACK_SIZE ] ) ), + "r" ( portINITIAL_PSTATE_EL1 ) + : "memory", "x0", "x1", "x2", "x3" + ); + } + } + /*-----------------------------------------------------------*/ + + void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */ + { + __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" ); + } + /*-----------------------------------------------------------*/ + + void vSystemCallExit( uint64_t ullSystemCallReturnValue ) /* PRIVILEGED_FUNCTION */ + { + #if ( configNUMBER_OF_CORES == 1 ) + extern TaskHandle_t pxCurrentTCB; + #else + extern TaskHandle_t pxCurrentTCBs[ configNUMBER_OF_CORES ]; + #endif + xMPU_SETTINGS * pxMpuSettings; + uint64_t ullSystemCallLocation; /* Address where SVC was raised. */ + __asm volatile ( "MRS %0, ELR_EL1" : "=r" ( ullSystemCallLocation ) ); + + #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint64_t * __privileged_functions_start__; + extern uint64_t * __privileged_functions_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint64_t __privileged_functions_start__[]; + extern uint64_t __privileged_functions_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + #if ( configNUMBER_OF_CORES == 1 ) + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + #else + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCBs[ portGET_CORE_ID_FROM_ISR() ] ); + #endif + + /* Check: + * SVC is raised from the privileged code (i.e. application is not + * raising SVC directly). This SVC is only raised from + * vRequestSystemCallExit which is in the privileged code section. + */ + if( ( ullSystemCallLocation >= ( uint64_t ) __privileged_functions_start__ ) && + ( ullSystemCallLocation <= ( uint64_t ) __privileged_functions_end__ ) ) + { + __asm volatile ( + "MSR ELR_EL1, %0 \n" /* Return to the MPU_ caller. */ + "MSR SP_EL0, %1 \n" /* Restore user SP saved at syscall entry. */ + "MSR SPSR_EL1, %3 \n" /* Ensure return to EL0. */ + "MOV X0, %2 \n" /* Move the system call return value to X0. */ + : + : "r" ( pxMpuSettings->xSystemCallInfo.ullLinkRegisterAtSystemCallEntry ), + "r" ( pxMpuSettings->xSystemCallInfo.ullUserSPAtSystemCallEntry ), + "r" ( ullSystemCallReturnValue ), + "r" ( ( uint64_t ) portINITIAL_PSTATE_EL0 ) + : "memory" + ); + } + } + /*-----------------------------------------------------------*/ + + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + + void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + /* Calculate the Access Control List entry index and bit position + * within that entry. */ + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + /* Set the bit corresponding to the kernel object to grant access. */ + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit ); + } + /*-----------------------------------------------------------*/ + + void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + /* Calculate the Access Control List entry index and bit position + * within that entry. */ + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + /* Clear the bit corresponding to the kernel object to revoke access. */ + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit ); + } + /*-----------------------------------------------------------*/ + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings; + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else + { + xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + if( ( xTaskMpuSettings->ullTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 ) + { + xAccessGranted = pdTRUE; + } + } + } + + return xAccessGranted; + } + /*-----------------------------------------------------------*/ + #else /* configENABLE_ACCESS_CONTROL_LIST == 1 */ + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + ( void ) lInternalIndexOfKernelObject; + + /* If Access Control List feature is not used, all the tasks have + * access to all the kernel objects. */ + return pdTRUE; + } + /*-----------------------------------------------------------*/ + + #endif /* configENABLE_ACCESS_CONTROL_LIST == 1 */ + +#endif /* #if ( configENABLE_MPU == 1 ) */ + +BaseType_t xPortStartScheduler( void ) +{ + uint64_t ullAPSR; + + #if ( configASSERT_DEFINED == 1 ) + { + volatile uint8_t ucOriginalPriority; + volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET ); + volatile uint8_t ucMaxPriorityValue; + + /* Determine how many priority bits are implemented in the GIC. + * + * Save the interrupt priority value that is about to be clobbered. */ + ucOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to + * all possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* Shift to the least significant bits. */ + while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET ) + { + ucMaxPriorityValue >>= ( uint8_t ) 0x01; + } + + /* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read + * value. */ + configASSERT( ucMaxPriorityValue >= portLOWEST_INTERRUPT_PRIORITY ); + + + /* Restore the clobbered interrupt priority register to its original + * value. */ + *pucFirstUserPriorityRegister = ucOriginalPriority; + } + #endif /* configASSERT_DEFINED */ + + __asm volatile ( "MRS %0, CurrentEL" : "=r" ( ullAPSR ) ); + ullAPSR &= portAPSR_MODE_BITS_MASK; + + configASSERT( ullAPSR == portEL1 ); + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + vSetupMPU(); + } + #endif /* #if ( configENABLE_MPU == 1 ) */ + + /* Interrupts are turned off in the CPU itself to ensure a tick does + * not execute while the scheduler is being started. Interrupts are + * automatically turned back on in the CPU when the first task starts + * executing. */ + __asm volatile ( "MSR DAIFSET, #2\n" + "DSB SY\n" + "ISB SY\n" ::: "memory" ); + #if ( configNUMBER_OF_CORES > 1 ) + /* Start the timer that generates the tick ISR. */ + configSETUP_TICK_INTERRUPT(); + ucPrimaryCoreInitDoneFlag = 1; + __asm volatile ( "SEV \n" + "DSB SY \n" + "ISB SY \n" + ::: "memory" ); + /* Hold the primary core here until all the secondary cores are ready, this would be achieved only when + * all elements of ucSecondaryCoresReadyFlags are set. + */ + while( 1 ) + { + BaseType_t xAllCoresReady = pdTRUE; + for( uint8_t ucCoreID = 0; ucCoreID < ( configNUMBER_OF_CORES - 1 ); ucCoreID++ ) + { + if( ucSecondaryCoresReadyFlags[ ucCoreID ] != pdTRUE ) + { + xAllCoresReady = pdFALSE; + break; + } + } + + if ( xAllCoresReady == pdTRUE ) + { + break; + } + } + #else /* if ( configNUMBER_OF_CORES > 1 ) */ + /* Start the timer that generates the tick ISR. */ + configSETUP_TICK_INTERRUPT(); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + + #if ( configENABLE_MPU == 1 ) + xSchedulerRunning = pdTRUE; + + /* Enable the Memory Protection Unit (MPU) + * MPU is only enabled after the primary and secondary handshakes + * are done as to prevent inconsistent MPU regions attributes across + * different cores resulting in unupdated values of the handshake + * flags. + */ + vEnableMPU(); + #endif /* #if ( configENABLE_MPU == 1 ) */ + + /* Start the first task executing. */ + vPortRestoreTaskContext(); + + return 0; +} + +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Stub implementation for ports where there is nothing to return to + * Artificially force an assert. */ + configASSERT( NULL ); +} + +/*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES == 1 ) + PRIVILEGED_FUNCTION void vPortEnterCritical( void ) + { + /* Mask interrupts up to the max syscall interrupt priority. */ + uxPortSetInterruptMask(); + + /* Now interrupts are disabled ullCriticalNesting can be accessed + * directly. Increment ullCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ + ullCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ + if( ullCriticalNesting == 1ULL ) + { + configASSERT( ullPortInterruptNesting == 0 ); + } + } + +/*-----------------------------------------------------------*/ + + PRIVILEGED_FUNCTION void vPortExitCritical( void ) + { + if( ullCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as the critical section is being + * exited. */ + ullCriticalNesting--; + + /* If the nesting level has reached zero then all interrupt + * priorities must be re-enabled. */ + if( ullCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Critical nesting has reached zero so all interrupt priorities + * should be unmasked. */ + portCLEAR_INTERRUPT_PRIORITIES_MASK(); + } + } + } +#endif /* if ( configNUMBER_OF_CORES == 1 ) */ + +/*-----------------------------------------------------------*/ + +void FreeRTOS_Tick_Handler( void ) +{ + /* Must be the lowest possible priority. */ + uint64_t ullRunningInterruptPriority; + __asm volatile ( "MRS %0, ICC_RPR_EL1" : "=r" ( ullRunningInterruptPriority ) ); + + configASSERT( ullRunningInterruptPriority == ( portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ); + + /* Interrupts should not be enabled before this point. */ + #if ( configASSERT_DEFINED == 1 ) + { + uint64_t ullMaskBits; + + __asm volatile ( "MRS %0, DAIF" : "=r" ( ullMaskBits )::"memory" ); + configASSERT( ( ullMaskBits & portDAIF_I ) != 0 ); + } + #endif /* configASSERT_DEFINED */ + + /* Set interrupt mask before altering scheduler structures. The tick + * interrupt runs at the lowest priority, so interrupts cannot already be masked, + * so there is no need to save and restore the current mask value. It is + * necessary to turn off interrupts in the CPU itself while the ICCPMR is being + * updated. + */ + UBaseType_t uxInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + + #if ( configNUMBER_OF_CORES > 1 ) + UBaseType_t x = portENTER_CRITICAL_FROM_ISR(); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + #if ( configNUMBER_OF_CORES == 1 ) + ullPortYieldRequired = pdTRUE; + #else + ullPortYieldRequired[ portGET_CORE_ID_FROM_ISR() ] = pdTRUE; + #endif + } + #if ( configNUMBER_OF_CORES > 1 ) + portEXIT_CRITICAL_FROM_ISR(x); + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + + /* Ensure all interrupt priorities are active again. */ + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxInterruptStatus ); + + /* Ok to enable interrupts after the interrupt source has been cleared. */ + configCLEAR_TICK_INTERRUPT(); +} + +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_FPU_SUPPORT == portTASK_NO_FPU_CONTEXT_BY_DEFAULT ) + + void vPortTaskUsesFPU( void ) + { + /* A task is registering the fact that it needs an FPU context. Set the + * FPU flag (which is saved as part of the task context). */ + #if ( configNUMBER_OF_CORES == 1 ) + ullPortTaskHasFPUContext = pdTRUE; + #else + ullPortTaskHasFPUContext[ portGET_CORE_ID() ] = pdTRUE; + #endif + + /* Consider initialising the FPSR here - but probably not necessary in + * AArch64. */ + } + +#endif /* configUSE_TASK_FPU_SUPPORT */ + +/*-----------------------------------------------------------*/ + +void vPortClearInterruptMask( UBaseType_t uxNewMaskValue ) +{ + if( uxNewMaskValue == portUNMASK_VALUE ) + { + /* Unmask all interrupt priorities. */ + portCLEAR_INTERRUPT_PRIORITIES_MASK(); + } + else + { + __asm volatile ( + "SVC %0 \n" + : + : "i" ( portSVC_UNMASK_INTERRUPTS ) + : "memory" + ); + } +} + +void vPortClearInterruptMaskFromISR( UBaseType_t uxNewMaskValue ) +{ + __asm volatile ( + "MSR DAIFSET, #2 \n" + "DSB SY \n" + "ISB SY \n" + "MSR ICC_PMR_EL1, %0 \n" + "DSB SY \n" + "ISB SY \n" + "MSR DAIFCLR, #2 \n" + "DSB SY \n" + "ISB SY \n" + : + : "r" ( uxNewMaskValue ) + ); +} +/*-----------------------------------------------------------*/ + +UBaseType_t uxPortSetInterruptMask( void ) +{ + UBaseType_t ullPMRValue; + + /* Use SVC so this can be called safely from EL0 tasks. */ + __asm volatile ( + "svc %1 \n" + "mov %0, x0 \n" + : "=r" ( ullPMRValue ) + : "i" ( portSVC_MASK_ALL_INTERRUPTS ) + : "x0", "memory" + ); + + return ullPMRValue; +} + +/* EL1/ISR variant to avoid SVC from interrupt context. */ +UBaseType_t uxPortSetInterruptMaskFromISR( void ) +{ + UBaseType_t ullPMRValue; + + __asm volatile ( "MRS %0, ICC_PMR_EL1" : "=r" ( ullPMRValue ) ); + + if( ullPMRValue != ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ) + { + __asm volatile ( "MSR DAIFSET, #2 \n" + "DSB SY \n" + "ISB SY \n" + "MSR ICC_PMR_EL1, %0 \n" + "DSB SY \n" + "ISB SY \n" + "MSR DAIFCLR, #2 \n" + "DSB SY \n" + "ISB SY \n" + ::"r" ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) : "memory" ); + } + + return ullPMRValue; +} + +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. */ + uint64_t ullRunningInterruptPriority; + __asm volatile ( "MRS %0, ICC_RPR_EL1" : "=r" ( ullRunningInterruptPriority ) ); + configASSERT( ullRunningInterruptPriority >= ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ); + } + +#endif /* configASSERT_DEFINED */ + +/*-----------------------------------------------------------*/ + +/* + * If the application provides an implementation of vApplicationIRQHandler(), + * then it will get called directly without saving the FPU registers on + * interrupt entry, and this weak implementation of + * vApplicationFPUSafeIRQHandler() is just provided to remove linkage errors - + * it should never actually get called so its implementation contains a + * call to configASSERT() that will always fail. + * + * If the application provides its own implementation of + * vApplicationFPUSafeIRQHandler() then the implementation of + * vApplicationIRQHandler() provided in portASM.S will save the FPU registers + * before calling it. + * + * Therefore, if the application writer wants FPU registers to be saved on + * interrupt entry their IRQ handler must be called + * vApplicationFPUSafeIRQHandler(), and if the application writer does not want + * FPU registers to be saved on interrupt entry their IRQ handler must be + * called vApplicationIRQHandler(). + */ + __attribute__( ( weak ) ) void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR ) +{ + ( void ) ulICCIAR; + configASSERT( ( volatile void * ) NULL ); +} + +/*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + + /* Which core owns the lock? Keep in privileged, shareable RAM. */ + PRIVILEGED_DATA volatile uint64_t ullOwnedByCore[ portMAX_CORE_COUNT ]; + /* Lock count a core owns. */ + PRIVILEGED_DATA volatile uint64_t ullRecursionCountByLock[ eLockCount ]; + /* Index 0 is used for ISR lock and Index 1 is used for task lock. */ + PRIVILEGED_DATA uint32_t ulGateWord[ eLockCount ]; + + void vInterruptCore( uint32_t ulInterruptID, uint8_t ucCoreID ) + { + uint64_t ulRegVal = 0; + uint32_t ulCoreMask = ( 1UL << ucCoreID ); + ulRegVal |= ( (ulCoreMask & 0xFFFF) | ( ( ulInterruptID & 0xF ) << 24U ) ); + __asm volatile ( + "str x0, [ sp, #-0x10 ]! \n" + "mov x0, %0 \n" + "svc %1 \n" + "ldr x0, [ sp ], # 0x10 \n" + : + : "r" ( ulRegVal ), "i" ( portSVC_INTERRUPT_CORE ) + : "memory", "w1" + ); + } + +/*-----------------------------------------------------------*/ + + static inline void prvSpinUnlock( uint32_t * ulLock ) + { + /* Conservative unlock: preserve original barriers for broad HW/FVP. */ + __asm volatile ( + "dmb sy \n" + "mov w1, #0 \n" + "str w1, [%x0] \n" + "sev \n" + "dsb sy \n" + "isb sy \n" + : + : "r" ( ulLock ) + : "memory", "w1" + ); + } + +/*-----------------------------------------------------------*/ + + static inline uint32_t prvSpinTrylock( uint32_t * ulLock ) + { + /* + * Conservative LDXR/STXR trylock: + * - Return 1 immediately if busy, clearing exclusive state (CLREX). + * - Retry STXR only on spurious failure when observed free. + * - DMB on success to preserve expected acquire semantics. + */ + register uint32_t ulRet; + __asm volatile ( + "1: \n" + "ldxr w1, [%x1] \n" + "cbnz w1, 2f \n" /* Busy -> return 1 */ + "mov w2, #1 \n" + "stxr w3, w2, [%x1] \n" /* w3 = status */ + "cbnz w3, 1b \n" /* Retry on STXR failure */ + "dmb sy \n" /* Acquire barrier on success */ + "mov %w0, #0 \n" /* Success */ + "b 3f \n" + "2: \n" + "clrex \n" /* Clear monitor when busy */ + "mov %w0, #1 \n" /* Busy */ + "3: \n" + : "=r" ( ulRet ) + : "r" ( ulLock ) + : "memory", "w1", "w2", "w3" + ); + + return ulRet; + } + +/*-----------------------------------------------------------*/ + + /* Read 64b value shared between cores. */ + static inline uint64_t prvGet64( volatile uint64_t * x ) + { + __asm( "dsb sy" ); + return *x; + } + +/*-----------------------------------------------------------*/ + + /* Write 64b value shared between cores. */ + static inline void prvSet64( volatile uint64_t * x, + uint64_t value ) + { + *x = value; + __asm( "dsb sy" ); + } + +/*-----------------------------------------------------------*/ + + void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ) + { + /* Validate the core ID and lock number. */ + configASSERT( ucCoreID < portMAX_CORE_COUNT ); + configASSERT( eLockNum < eLockCount ); + + uint32_t ulLockBit = 1u << eLockNum; + + /* Lock acquire */ + if( uxAcquire ) + { + /* Check if spinlock is available. + * If spinlock is not available check if the core owns the lock. + * If the core owns the lock wait increment the lock count by the core. + * If core does not own the lock wait for the spinlock. + */ + if( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + /* Check if the core owns the spinlock. */ + if( prvGet64( &ullOwnedByCore[ ucCoreID ] ) & ulLockBit ) + { + configASSERT( prvGet64( &ullRecursionCountByLock[ eLockNum ] ) != 255u ); + prvSet64( &ullRecursionCountByLock[ eLockNum ], ( prvGet64( &ullRecursionCountByLock[ eLockNum ] ) + 1 ) ); + return; + } + + /* Preload the gate word into the cache. */ + uint32_t dummy = ulGateWord[ eLockNum ]; + dummy++; + + while( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 ) + { + /* Follow Arm's recommended way of sleeping + * sevl is used to prime the wait loop. + * The first wfe wakes immediately because sevl has set the flag. + * Check the lock, if it's not available, issue a second wfe to sleep. + * This guarantees the core actually goes to sleep. + */ + __asm volatile ( + "sevl \n" + "1: wfe \n" + "ldr w2, [%x0] \n" + "cbnz w2, 1b \n" + : + : "r" ( &ulGateWord[ eLockNum ] ) + : "memory", "w2" + ); + } + } + + /* Add barrier to ensure lock is taken before we proceed. */ + __asm__ __volatile__ ( "dmb sy" ::: "memory" ); + + /* Assert the lock count is 0 when the spinlock is free and is acquired. */ + configASSERT( prvGet64( &ullRecursionCountByLock[ eLockNum ] ) == 0 ); + + /* Set lock count as 1. */ + prvSet64( &ullRecursionCountByLock[ eLockNum ], 1 ); + /* Set ullOwnedByCore. */ + prvSet64( &ullOwnedByCore[ ucCoreID ], ( prvGet64( &ullOwnedByCore[ ucCoreID ] ) | ulLockBit ) ); + } + /* Lock release. */ + else + { + /* Assert the lock is not free already. */ + configASSERT( ( prvGet64( &ullOwnedByCore[ ucCoreID ] ) & ulLockBit ) != 0 ); + configASSERT( prvGet64( &ullRecursionCountByLock[ eLockNum ] ) != 0 ); + + /* Reduce ullRecursionCountByLock by 1. */ + prvSet64( &ullRecursionCountByLock[ eLockNum ], ( prvGet64( &ullRecursionCountByLock[ eLockNum ] ) - 1 ) ); + + if( !prvGet64( &ullRecursionCountByLock[ eLockNum ] ) ) + { + prvSet64( &ullOwnedByCore[ ucCoreID ], ( prvGet64( &ullOwnedByCore[ ucCoreID ] ) & ~ulLockBit ) ); + prvSpinUnlock( &ulGateWord[ eLockNum ] ); + /* Add barrier to ensure lock status is reflected before we proceed. */ + __asm__ __volatile__ ( "dmb sy" ::: "memory" ); + } + } + } + +/*-----------------------------------------------------------*/ + + uint8_t ucPortGetCoreID( void ) + { + /* Use SVC to obtain the core ID in a way that is safe when called + * from EL0 tasks. ISRs and EL1 code should use + * ucPortGetCoreIDFromIsr()/portGET_CORE_ID_FROM_ISR(). + */ + uint8_t ucCoreID; + __asm volatile ( + "svc %1 \n" + "mov %w0, w0 \n" + : "=r" ( ucCoreID ) + : "i" ( portSVC_GET_CORE_ID ) + : "x0", "memory" + ); + return ucCoreID; + } + +/*-----------------------------------------------------------*/ + + uint8_t ucPortGetCoreIDFromIsr ( void ) /* PRIVILEGED_FUNCTION */ + { + uint64_t ullMpidrEl1; + __asm volatile ( "MRS %0, MPIDR_EL1" : "=r" ( ullMpidrEl1 ) ); + + return ( uint8_t ) ( ullMpidrEl1 & 0xff ); + } + +/*------------------------------------------------------------*/ + void FreeRTOS_SGI_Handler( void ) + { + /* Must be the lowest possible priority. */ + uint64_t ullRunningInterruptPriority; + __asm volatile ( "MRS %0, ICC_RPR_EL1" : "=r" ( ullRunningInterruptPriority ) ); + + configASSERT( ullRunningInterruptPriority == ( portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ); + /* Interrupts should not be enabled before this point. */ + #if ( configASSERT_DEFINED == 1 ) + { + uint64_t ullMaskBits; + + __asm volatile ( "mrs %0, DAIF" : "=r" ( ullMaskBits )::"memory" ); + configASSERT( ( ullMaskBits & portDAIF_I ) != 0 ); + } + #endif /* configASSERT_DEFINED */ + + /* Set interrupt mask before altering scheduler structures. The SGI + * interrupt runs at the lowest priority, so interrupts cannot already be masked, + * so there is no need to save and restore the current mask value. It is + * necessary to turn off interrupts in the CPU itself while the ICCPMR is being + * updated. + */ + UBaseType_t uxInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + + UBaseType_t uxSavedInterruptStatus = portENTER_CRITICAL_FROM_ISR(); + #if ( configNUMBER_OF_CORES == 1 ) + ullPortYieldRequired = pdTRUE; + #else + ullPortYieldRequired[ portGET_CORE_ID_FROM_ISR() ] = pdTRUE; + #endif + portEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxInterruptStatus ); + } + +/*-----------------------------------------------------------*/ + +#endif /* if( configNUMBER_OF_CORES > 1 ) */ diff --git a/portable/GCC/ARM_CR82/portASM.S b/portable/GCC/ARM_CR82/portASM.S new file mode 100644 index 000000000..12233481f --- /dev/null +++ b/portable/GCC/ARM_CR82/portASM.S @@ -0,0 +1,1159 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2025-2026 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * This file is tailored for ARM Cortex-R82 with SMP enabled. + * It includes macros and functions for saving/restoring task context, + * handling interrupts, and supporting multi-core operations. + */ + +#include "FreeRTOSConfig.h" +#include "portmacro.h" + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION + * is defined correctly and privileged functions are placed in correct sections. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* System call numbers includes. */ +#include "mpu_syscall_numbers.h" + +/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the + * header files. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +.text + +/* Variables and functions. */ +#if ( configNUMBER_OF_CORES == 1 ) + .extern pxCurrentTCB + .extern ullCriticalNesting + .extern ullPortInterruptNesting +#else /* #if ( configNUMBER_OF_CORES == 1 ) */ + .extern pxCurrentTCBs + .extern ullCriticalNestings + .extern ullPortInterruptNestings +#endif + .extern vTaskSwitchContext + .extern vApplicationIRQHandler + .extern ullPortTaskHasFPUContext + .extern ullPortYieldRequired + .extern _freertos_vector_table + +#if ( configENABLE_MPU == 1 ) + .extern xPortIsTaskPrivileged + .extern vSystemCallEnter + .extern vSystemCallExit + .extern vRequestSystemCallExit + .extern uxSystemCallImplementations +#endif /* #if ( configENABLE_MPU == 1 ) */ + + .global FreeRTOS_IRQ_Handler + .global FreeRTOS_SWI_Handler + .global vPortSaveTaskContext + .global vPortRestoreTaskContext + +#if ( configENABLE_MPU == 1 ) + + .macro portLOAD_MPU_REGIONS_ADDRESSES +MOV X3, # portSTACK_REGION /* Task's first programmed region is its stack region as the first four MPU regions are already programmed.*/ +MOV X4, # configTOTAL_MPU_REGIONS - 1 /* Upper limit = configTOTAL_MPU_REGIONS - 1 */ +1 : + CMP X3, X4 /* Compare i with ( configTOTAL_MPU_REGIONS - 1 ) */ + B.GT 2f /* if i > ( configTOTAL_MPU_REGIONS - 1 ), exit loop */ + MSR PRSELR_EL1, X3 /* Program PRSELR_EL1. */ + ISB /* Ensure PRSELR selection takes effect before registers access. */ + LDP X1, X2, [ X0 ], # 0x10 /* Retrieve ullPrbarEl1 and ullPrlarEl1r */ + MSR PRBAR_EL1, X1 /* Program PRBAR_EL1. */ + MSR PRLAR_EL1, X2 /* Program PRLAR_EL1. */ + ADD X3, X3, # 1 /* i++ */ + B 1b +2 : + DSB SY + ISB + .endm + + .macro portSTORE_MPU_REGIONS_ADDRESSES +MOV X3, # portSTACK_REGION /* Task's first programmed region is its stack region as the first four MPU regions are already programmed.*/ +MOV X4, # configTOTAL_MPU_REGIONS - 1 /* Upper limit = configTOTAL_MPU_REGIONS - 1 */ +1 : + CMP X3, X4 /* Compare i with ( configTOTAL_MPU_REGIONS - 1 ) */ + B.GT 2f /* if i > ( configTOTAL_MPU_REGIONS - 1 ), exit loop */ + MSR PRSELR_EL1, X3 /* Program PRSELR_EL1. */ + ISB /* Ensure PRSELR selection takes effect before registers access. */ + MRS X1, PRBAR_EL1 /* Retrieve PRBAR_EL1. */ + MRS X2, PRLAR_EL1 /* Retrieve PRLAR_EL1. */ + STP X1, X2, [ X0 ], # 0x10 /* Store PRBAR_EL1 and PRLAR_EL1 in ullPrbarEl1 and ullPrlarEl1r */ + ADD X3, X3, # 1 /* i++ */ + B 1b +2 : + /* No additional barrier required after reading PR* registers. */ + .endm + +#endif /* #if ( configENABLE_MPU == 1 ) */ + +/*-----------------------------------------------------------*/ + + .macro savefuncontextgpregs +/* Save function context general-purpose registers. */ +STP X0, X1, [ SP, # - 0x10 ] ! +STP X2, X3, [ SP, # - 0x10 ] ! +STP X4, X5, [ SP, # - 0x10 ] ! +STP X6, X7, [ SP, # - 0x10 ] ! +STP X8, X9, [ SP, # - 0x10 ] ! +STP X10, X11, [ SP, # - 0x10 ] ! +STP X12, X13, [ SP, # - 0x10 ] ! +STP X14, X15, [ SP, # - 0x10 ] ! +STP X16, X17, [ SP, # - 0x10 ] ! +STP X18, X29, [ SP, # - 0x10 ] ! +STR X30, [ SP, # - 0x10 ] ! + .endm + +/*-----------------------------------------------------------*/ + + .macro savesyscallcontextgpregs +/* Save system call context general-purpose registers. */ +STP X4, X5, [ SP, # - 0x10 ] ! +STP X6, X7, [ SP, # - 0x10 ] ! +STP X8, X9, [ SP, # - 0x10 ] ! +STP X10, X11, [ SP, # - 0x10 ] ! +STP X12, X13, [ SP, # - 0x10 ] ! +STP X14, X15, [ SP, # - 0x10 ] ! +STP X16, X17, [ SP, # - 0x10 ] ! +STP X18, X29, [ SP, # - 0x10 ] ! + .endm + +/*-----------------------------------------------------------*/ + + .macro restorefuncontextgpregs +/* Restore function context general-purpose registers. */ +LDR X30, [ SP ], # 0x10 +LDP X18, X29, [ SP ], # 0x10 +LDP X16, X17, [ SP ], # 0x10 +LDP X14, X15, [ SP ], # 0x10 +LDP X12, X13, [ SP ], # 0x10 +LDP X10, X11, [ SP ], # 0x10 +LDP X8, X9, [ SP ], # 0x10 +LDP X6, X7, [ SP ], # 0x10 +LDP X4, X5, [ SP ], # 0x10 +LDP X2, X3, [ SP ], # 0x10 +LDP X0, X1, [ SP ], # 0x10 + .endm + +/*-----------------------------------------------------------*/ + + .macro restorefuncontextgpregexceptx0 +/* Restore function context general-purpose registers while discarding old X0. */ +LDR X30, [ SP ], # 0x10 +LDP X18, X29, [ SP ], # 0x10 +LDP X16, X17, [ SP ], # 0x10 +LDP X14, X15, [ SP ], # 0x10 +LDP X12, X13, [ SP ], # 0x10 +LDP X10, X11, [ SP ], # 0x10 +LDP X8, X9, [ SP ], # 0x10 +LDP X6, X7, [ SP ], # 0x10 +LDP X4, X5, [ SP ], # 0x10 +LDP X2, X3, [ SP ], # 0x10 +LDP XZR, X1, [ SP ], # 0x10 + .endm + +/*-----------------------------------------------------------*/ + + .macro restoresyscallcontextgpregs +/* Restore system call context general-purpose registers. */ +LDP X18, X29, [ SP ], # 0x10 +LDP X16, X17, [ SP ], # 0x10 +LDP X14, X15, [ SP ], # 0x10 +LDP X12, X13, [ SP ], # 0x10 +LDP X10, X11, [ SP ], # 0x10 +LDP X8, X9, [ SP ], # 0x10 +LDP X6, X7, [ SP ], # 0x10 +LDP X4, X5, [ SP ], # 0x10 + .endm +/*-----------------------------------------------------------*/ + + .macro saveallgpregisters +/* Save all general-purpose registers on stack. */ +STP X0, X1, [ SP, # - 0x10 ] ! +STP X2, X3, [ SP, # - 0x10 ] ! +STP X4, X5, [ SP, # - 0x10 ] ! +STP X6, X7, [ SP, # - 0x10 ] ! +STP X8, X9, [ SP, # - 0x10 ] ! +STP X10, X11, [ SP, # - 0x10 ] ! +STP X12, X13, [ SP, # - 0x10 ] ! +STP X14, X15, [ SP, # - 0x10 ] ! +STP X16, X17, [ SP, # - 0x10 ] ! +STP X18, X19, [ SP, # - 0x10 ] ! +STP X20, X21, [ SP, # - 0x10 ] ! +STP X22, X23, [ SP, # - 0x10 ] ! +STP X24, X25, [ SP, # - 0x10 ] ! +STP X26, X27, [ SP, # - 0x10 ] ! +STP X28, X29, [ SP, # - 0x10 ] ! +STP X30, XZR, [ SP, # - 0x10 ] ! + .endm + +/*-----------------------------------------------------------*/ + + .macro restoreallgpregisters +/* Restore all general-purpose registers from stack. */ +LDP X30, XZR, [ SP ], # 0x10 +LDP X28, X29, [ SP ], # 0x10 +LDP X26, X27, [ SP ], # 0x10 +LDP X24, X25, [ SP ], # 0x10 +LDP X22, X23, [ SP ], # 0x10 +LDP X20, X21, [ SP ], # 0x10 +LDP X18, X19, [ SP ], # 0x10 +LDP X16, X17, [ SP ], # 0x10 +LDP X14, X15, [ SP ], # 0x10 +LDP X12, X13, [ SP ], # 0x10 +LDP X10, X11, [ SP ], # 0x10 +LDP X8, X9, [ SP ], # 0x10 +LDP X6, X7, [ SP ], # 0x10 +LDP X4, X5, [ SP ], # 0x10 +LDP X2, X3, [ SP ], # 0x10 +LDP X0, X1, [ SP ], # 0x10 + .endm + +/*-----------------------------------------------------------*/ + + .macro savefloatregisters +/* Save floating-point registers and configuration/status registers. */ +STP Q0, Q1, [ SP, # - 0x20 ] ! +STP Q2, Q3, [ SP, # - 0x20 ] ! +STP Q4, Q5, [ SP, # - 0x20 ] ! +STP Q6, Q7, [ SP, # - 0x20 ] ! +STP Q8, Q9, [ SP, # - 0x20 ] ! +STP Q10, Q11, [ SP, # - 0x20 ] ! +STP Q12, Q13, [ SP, # - 0x20 ] ! +STP Q14, Q15, [ SP, # - 0x20 ] ! +STP Q16, Q17, [ SP, # - 0x20 ] ! +STP Q18, Q19, [ SP, # - 0x20 ] ! +STP Q20, Q21, [ SP, # - 0x20 ] ! +STP Q22, Q23, [ SP, # - 0x20 ] ! +STP Q24, Q25, [ SP, # - 0x20 ] ! +STP Q26, Q27, [ SP, # - 0x20 ] ! +STP Q28, Q29, [ SP, # - 0x20 ] ! +STP Q30, Q31, [ SP, # - 0x20 ] ! +MRS X9, FPSR +MRS X10, FPCR +STP W9, W10, [ SP, # - 0x10 ] ! + .endm + +/*-----------------------------------------------------------*/ + + .macro restorefloatregisters +/* Restore floating-point registers and configuration/status registers. */ +LDP W9, W10, [ SP ], # 0x10 +MSR FPSR, X9 +MSR FPCR, X10 +LDP Q30, Q31, [ SP ], # 0x20 +LDP Q28, Q29, [ SP ], # 0x20 +LDP Q26, Q27, [ SP ], # 0x20 +LDP Q24, Q25, [ SP ], # 0x20 +LDP Q22, Q23, [ SP ], # 0x20 +LDP Q20, Q21, [ SP ], # 0x20 +LDP Q18, Q19, [ SP ], # 0x20 +LDP Q16, Q17, [ SP ], # 0x20 +LDP Q14, Q15, [ SP ], # 0x20 +LDP Q12, Q13, [ SP ], # 0x20 +LDP Q10, Q11, [ SP ], # 0x20 +LDP Q8, Q9, [ SP ], # 0x20 +LDP Q6, Q7, [ SP ], # 0x20 +LDP Q4, Q5, [ SP ], # 0x20 +LDP Q2, Q3, [ SP ], # 0x20 +LDP Q0, Q1, [ SP ], # 0x20 + .endm + +/*-----------------------------------------------------------*/ + + .macro portSAVE_CONTEXT + +#if ( configENABLE_MPU == 1 ) + /* Switch to use the EL1 stack pointer. */ + MSR SPSEL, # 1 + + /* Store X0-X4 as they are being used to save the user allocated task stack and to program the MPU */ + STP X0, X1, [ SP, # - 0x10 ] ! + STP X2, X3, [ SP, # - 0x10 ] ! + STR X4, [ SP, # - 0x10 ] ! + + /* Switch to use the EL0 stack pointer. */ + MSR SPSEL, # 0 + + /* Store user allocated task stack and use ullContext as the SP */ + #if ( configNUMBER_OF_CORES == 1 ) + adrp X0, pxCurrentTCB + add X0, X0, :lo12:pxCurrentTCB /* X0 = &pxCurrentTCB */ + #else + adrp X0, pxCurrentTCBs + add X0, X0, :lo12:pxCurrentTCBs /* X0 = &pxCurrentTCBs */ + /* Get the core ID to index the TCB correctly. */ + MRS X2, MPIDR_EL1 /* Read the Multiprocessor Affinity Register */ + AND X2, X2, # 0xff /* Extract Aff0 which contains the core ID */ + LSL X2, X2, # 3 /* Scale the core ID to the size of a pointer (64-bit system) */ + ADD X0, X0, X2 /* Add the offset for the current core's TCB pointer */ + #endif + LDR X1, [ X0 ] + ADD X1, X1, #8 /* X1 = X1 + 8, X1 now points to ullTaskUnprivilegedSP in TCB. */ + MOV X0, SP + STR X0, [ X1 ] /* Save ullTaskUnprivilegedSP on task's TCB */ + SUB X1, X1, #8 /* X1 = X1 - 8, X1 now points to pxTopOfStack in TCB. */ + LDR X1, [ X1 ] + MOV SP, X1 /* Use pxTopOfStack ( ullContext ) as the SP. */ + + savefuncontextgpregs + #if ( configNUMBER_OF_CORES > 1 ) + MRS X1, ELR_EL1 /* Save ELR_EL1 before calling xPortIsTaskPrivileged which would change its value in case of multicore */ + STR X1, [ SP, # - 0x10 ] ! + #endif + BL xPortIsTaskPrivileged + #if ( configNUMBER_OF_CORES > 1 ) + LDR X1, [ SP ], # 0x10 + MSR ELR_EL1, X1 + #endif + CBNZ X0, 3f /* If task is privileged, skip saving MPU context. */ + #if ( configNUMBER_OF_CORES == 1 ) + adrp X0, pxCurrentTCB + add X0, X0, :lo12:pxCurrentTCB /* X0 = &pxCurrentTCB */ + #else + adrp X0, pxCurrentTCBs + add X0, X0, :lo12:pxCurrentTCBs /* X0 = &pxCurrentTCBs */ + /* Get the core ID to index the TCB correctly. */ + MRS X2, MPIDR_EL1 /* Read the Multiprocessor Affinity Register */ + AND X2, X2, # 0xff /* Extract Aff0 which contains the core ID */ + LSL X2, X2, # 3 /* Scale the core ID to the size of a pointer (64-bit system) */ + ADD X0, X0, X2 /* Add the offset for the current core's TCB pointer */ + #endif + LDR X0, [ X0 ] + + ADD X0, X0, #16 /* X0 = X0 + 16. X0 now points to MAIR_EL1 in TCB. */ + MRS X1, MAIR_EL1 /* X1 = MAIR_EL1. */ + STR X1, [ X0 ], # 0x8 /* Store MAIR_EL1 in TCB, X0 = X0 + 8. */ + + portSTORE_MPU_REGIONS_ADDRESSES /* Store MPU region addresses onto TCB. */ + +3 : + restorefuncontextgpregs + MSR SPSEL, # 1 + + /* Restore X0-X4. */ + LDR X4, [ SP ], # 0x10 + LDP X2, X3, [ SP ], # 0x10 + LDP X0, X1, [ SP ], # 0x10 +#endif /* #if ( configENABLE_MPU == 1 ) */ + +MSR SPSEL, # 0 + +/* Save the entire context. */ +saveallgpregisters + +/* Save the SPSR and ELR values. */ +MRS X3, SPSR_EL1 +MRS X2, ELR_EL1 + +STP X2, X3, [ SP, # - 0x10 ] ! + +/* Save the critical section nesting depth. */ +#if ( configNUMBER_OF_CORES == 1 ) + adrp X0, ullCriticalNesting + add X0, X0, :lo12:ullCriticalNesting /* X0 = &ullCriticalNesting */ +#else + adrp X0, ullCriticalNestings + add X0, X0, :lo12:ullCriticalNestings /* X0 = &ullCriticalNestings */ + /* Calculate per-core index using MPIDR_EL1 for SMP support. */ + MRS X1, MPIDR_EL1 /* Read the Multiprocessor Affinity Register. */ + AND X1, X1, # 0xff /* Extract Aff0 (core ID). */ + LSL X1, X1, # 3 /* Multiply core ID by pointer size (8 bytes). */ + ADD X0, X0, X1 /* Add offset to base address. */ +#endif + +LDR X3, [ X0 ] + +/* Save the FPU context indicator. */ +adrp X0, ullPortTaskHasFPUContext +add X0, X0, :lo12:ullPortTaskHasFPUContext /* X0 = &ullPortTaskHasFPUContext */ + +#if ( configNUMBER_OF_CORES > 1 ) + ADD X0, X0, X1 /* Add to the base of the FPU array. */ +#endif +LDR X2, [ X0 ] + +/* Save the FPU context, if any (32 128-bit registers). */ +CBZ X2, 4f /* FPU context not present, skip saving FPU registers. */ +savefloatregisters + +4 : +/* Store the critical nesting count and FPU context indicator. */ +STP X2, X3, [ SP, # - 0x10 ] ! + +#if ( configNUMBER_OF_CORES == 1 ) + adrp X0, pxCurrentTCB + add X0, X0, :lo12:pxCurrentTCB /* X0 = &pxCurrentTCB */ +#else + adrp X0, pxCurrentTCBs + add X0, X0, :lo12:pxCurrentTCBs /* X0 = &pxCurrentTCBs */ + MRS X1, MPIDR_EL1 /* Read Multiprocessor Affinity Register .*/ + AND X1, X1, # 0xff /* Extract core ID. */ + LSL X1, X1, # 3 /* Multiply core ID by pointer size. */ + ADD X0, X0, X1 /* Offset for current core's TCB pointer. */ +#endif + +LDR X1, [ X0 ] +MOV X0, SP +STR X0, [ X1 ] /* Save pxTopOfStack on the TCB. */ + +/* Switch to use the EL1 stack pointer. */ +MSR SPSEL, # 1 + .endm + +/*-----------------------------------------------------------*/ + + .macro portRESTORE_CONTEXT + +#if ( configENABLE_MPU == 1 ) + /* Switch to use the EL1 stack pointer. */ + MSR SPSEL, # 1 + + savefuncontextgpregs + BL xPortIsTaskPrivileged + CBNZ X0, 3f /* If task is privileged, skip restoring MPU context. */ + + /* Switch to use the EL0 stack pointer. */ + MSR SPSEL, # 0 + #if ( configNUMBER_OF_CORES == 1 ) + adrp X0, pxCurrentTCB + add X0, X0, :lo12:pxCurrentTCB /* X0 = &pxCurrentTCB */ + #else + adrp X0, pxCurrentTCBs + add X0, X0, :lo12:pxCurrentTCBs /* X0 = &pxCurrentTCBs */ + /* Get the core ID to index the TCB correctly. */ + MRS X2, MPIDR_EL1 /* Read the Multiprocessor Affinity Register */ + AND X2, X2, # 0xff /* Extract Aff0 which contains the core ID */ + LSL X2, X2, # 3 /* Scale the core ID to the size of a pointer (64-bit system) */ + + ADD X0, X0, X2 /* Add the offset for the current core's TCB pointer */ + #endif + LDR X0, [ X0 ] + + DMB SY /* Complete outstanding transfers before disabling MPU. */ + MRS X1, SCTLR_EL1 /* X1 = SCTLR_EL1 */ + BIC X1, X1, # (1 << 0) /* Clears bit 0 of X1 */ + MSR SCTLR_EL1, X1 /* Disable MPU. */ + + ADD X0, X0, #16 /* X0 = X0 + 16. X0 now points to MAIR_EL1 in TCB. */ + LDR X1, [ X0 ], # 0x8 /* X1 = *X0 i.e. X1 = MAIR_EL1, X0 = X0 + 8. */ + MSR MAIR_EL1, X1 /* Program MAIR_EL1. */ + + portLOAD_MPU_REGIONS_ADDRESSES /* Load MPU region addresses from TCB. */ + MRS X1, SCTLR_EL1 /* X1 = SCTLR_EL1 */ + ORR X1, X1, # (1 << 0) /* Sets bit 0 of X1 */ + MSR SCTLR_EL1, X1 /* Enable MPU. */ + DSB SY /* Force memory writes before continuing. */ + +3 : + MSR SPSEL, # 1 + restorefuncontextgpregs +#endif /* #if ( configENABLE_MPU == 1 ) */ + + /* Switch to use the EL0 stack pointer. */ + MSR SPSEL, # 0 + + #if ( configNUMBER_OF_CORES == 1 ) + adrp X0, pxCurrentTCB + add X0, X0, :lo12:pxCurrentTCB /* X0 = &pxCurrentTCB */ + #else + adrp X0, pxCurrentTCBs + add X0, X0, :lo12:pxCurrentTCBs /* X0 = &pxCurrentTCBs */ + /* Get the core ID to index the TCB correctly. */ + MRS X2, MPIDR_EL1 /* Read the Multiprocessor Affinity Register */ + AND X2, X2, # 0xff /* Extract Aff0 which contains the core ID */ + LSL X2, X2, # 3 /* Scale the core ID to the size of a pointer (64-bit system) */ + ADD X0, X0, X2 /* Add the offset for the current core's TCB pointer */ + #endif + LDR X1, [ X0 ] + LDR X0, [ X1 ] /* X0 = Location of saved context in TCB. */ + MOV SP, X0 + LDP X2, X3, [ SP ], # 0x10 /* Retrieve critical nesting and FPU indicator */ + + #if ( configNUMBER_OF_CORES == 1 ) + adrp X0, ullCriticalNesting + add X0, X0, :lo12:ullCriticalNesting /* X0 = &ullCriticalNesting */ + #else + adrp X0, ullCriticalNestings + add X0, X0, :lo12:ullCriticalNestings /* X0 = &ullCriticalNestings */ + /* Calculate offset for current core's ullCriticalNesting */ + MRS X1, MPIDR_EL1 /* Read Multiprocessor Affinity Register */ + AND X1, X1, # 0xff /* Extract Aff0, which contains the core ID */ + LSL X1, X1, # 3 /* Scale core ID to the size of a pointer (assuming 64-bit system) */ + ADD X0, X0, X1 /* Add offset for the current core's ullCriticalNesting */ + #endif + + MOV X1, # 255 /* Default mask */ + CBZ X3, 4f + MOV X1, # portMAX_API_PRIORITY_MASK + +4: + MSR ICC_PMR_EL1, X1 /* Set interrupt mask */ + DSB SY + ISB SY + STR X3, [ X0 ] /* Restore critical nesting */ + /* Restore the FPU context indicator. */ + adrp X0, ullPortTaskHasFPUContext + add X0, X0, :lo12:ullPortTaskHasFPUContext /* X0 = &ullPortTaskHasFPUContext */ + #if ( configNUMBER_OF_CORES > 1 ) + MRS X1, MPIDR_EL1 /* Read Multiprocessor Affinity Register */ + AND X1, X1, # 0xff /* Extract Aff0, which contains the core ID */ + LSL X1, X1, # 3 /* Scale core ID to the size of a pointer (assuming 64-bit system) */ + ADD X0, X0, X1 /* Add to the base of the FPU array */ + #endif + STR X2, [ X0 ] + /* Restore the FPU context, if any. */ + CBZ X2, 5f + restorefloatregisters + +5: + LDP X2, X3, [ SP ], # 0x10 /* Restore SPSR and ELR */ + + MSR SPSR_EL1, X3 + MSR ELR_EL1, X2 + restoreallgpregisters + +#if ( configENABLE_MPU == 1 ) + /* Save pxTopOfStack ( ullContext ) on the task's TCB and set SP_EL0 to ullTaskUnprivilegedSP. */ + MSR SPSEL, # 1 + STP X8, X9, [ SP, # - 0x10 ] ! + STR X10, [ SP, # - 0x10 ] ! + #if ( configNUMBER_OF_CORES == 1 ) + adrp X8, pxCurrentTCB + add X8, X8, :lo12:pxCurrentTCB /* X8 = &pxCurrentTCB */ + #else + adrp X8, pxCurrentTCBs + add X8, X8, :lo12:pxCurrentTCBs /* X8 = &pxCurrentTCBs */ + /* Get the core ID to index the TCB correctly. */ + MRS X10, MPIDR_EL1 /* Read the Multiprocessor Affinity Register */ + AND X10, X10, # 0xff /* Extract Aff0 which contains the core ID */ + LSL X10, X10, # 3 /* Scale the core ID to the size of a pointer (64-bit system) */ + ADD X8, X8, X10 /* Add the offset for the current core's TCB pointer */ + #endif + LDR X9, [ X8 ] + MRS X8, SP_EL0 + STR X8, [ X9 ] /* Store pxTopOfStack on task's TCB */ + ADD X9, X9, #8 /* X9 = X9 + 8. X1 now points to ullTaskUnprivilegedSP in TCB. */ + LDR X9, [ X9 ] + MSR SP_EL0, X9 /* Use ullTaskUnprivilegedSP as SP_EL0. */ + LDR X10, [ SP ], # 0x10 + LDP X8, X9, [ SP ], # 0x10 +#endif /* #if ( configENABLE_MPU == 1 ) */ + + /* Switch to use the EL1 stack pointer. */ + MSR SPSEL, # 1 + .endm + +/*-----------------------------------------------------------*/ + +/****************************************************************************** + * FreeRTOS_SWI_Handler handler is used to perform a context switch. + *****************************************************************************/ + .align 8 + .type FreeRTOS_SWI_Handler, % function +FreeRTOS_SWI_Handler: +/* Save X0-X5 temporarily as they are used in the handler. */ +STP X0, X1, [SP, #-0x10]! +STP X2, X3, [SP, #-0x10]! +STP X4, X5, [SP, #-0x10]! + +MRS X4, ELR_EL1 /* Save exception return address. */ +MRS X5, SPSR_EL1 /* Save program status register address. */ + +/* Decide action based on SVC immediate without corrupting any task context. */ +MRS X0, ESR_EL1 + +/* Extract exception class. */ +LSR X1, X0, # 26 +CMP X1, # 0x15 /* 0x15 = SVC instruction. */ +B.NE FreeRTOS_Abort + +/* Extract SVC immediate from ISS[15:0]. */ +AND X2, X0, # 0xFFFF + +/* portSVC_YIELD: yield from a running task. */ +CMP X2, # portSVC_YIELD +B.EQ FreeRTOS_Yield + +/* portSVC_START_FIRST_TASK: start first task on this core without saving any prior context. */ +CMP X2, # portSVC_START_FIRST_TASK +B.EQ Start_First_Task + +1: +/* portSVC_DISABLE_INTERRUPTS: disable IRQs (DAIF.I) in SPSR_EL1 without touching task context. */ +CMP X2, # portSVC_DISABLE_INTERRUPTS +B.NE 2f +ORR X5, X5, # (1 << portPSTATE_I_BIT) /* Set I bit in SPSR_EL1 */ +MSR ELR_EL1, X4 +MSR SPSR_EL1, X5 +LDP X4, X5, [SP], #0x10 +LDP X2, X3, [SP], #0x10 +LDP X0, X1, [SP], #0x10 +DSB SY +ISB SY +ERET + +2: +/* portSVC_ENABLE_INTERRUPTS: enable IRQs (DAIF.I clear) in SPSR_EL1 without touching task context. */ +CMP X2, # portSVC_ENABLE_INTERRUPTS +B.NE 3f +BIC X5, X5, # (1 << portPSTATE_I_BIT) /* Clear I bit in SPSR_EL1 */ +MSR ELR_EL1, X4 +MSR SPSR_EL1, X5 +LDP X4, X5, [SP], #0x10 +LDP X2, X3, [SP], #0x10 +LDP X0, X1, [SP], #0x10 +ERET + +3: +/* portSVC_GET_CORE_ID: return core ID in X0 (Aff0 of MPIDR_EL1). */ +CMP X2, # portSVC_GET_CORE_ID +B.NE 4f +MRS X0, MPIDR_EL1 +AND X0, X0, # 0xff +MSR SPSR_EL1, X5 +/* Restore X5-X1 while discarding old X0. */ +LDP X4, X5, [SP], #0x10 +LDP X2, X3, [ SP ], # 0x10 +LDP XZR, X1, [ SP ], # 0x10 +ERET + +4: +/* portSVC_MASK_ALL_INTERRUPTS: set ICC_PMR_EL1 to max API mask and return previous-mask-equal flag in X0. */ +CMP X2, # portSVC_MASK_ALL_INTERRUPTS +B.NE 5f +/* Read current PMR and compare. */ +MRS X0, ICC_PMR_EL1 +CMP X0, # portMAX_API_PRIORITY_MASK +B.EQ 41f +/* Disable IRQs while updating PMR. */ +MSR DAIFSET, # 2 +DSB SY +ISB SY +/* Write new PMR value. */ +MOV X1, # portMAX_API_PRIORITY_MASK +MSR ICC_PMR_EL1, X1 +DSB SY +ISB SY +/* Re-enable IRQs. */ +MSR DAIFCLR, # 2 +DSB SY +ISB SY +MSR ELR_EL1, X4 +MSR SPSR_EL1, X5 + +41: +/* Restore X5-X1 while discarding old X0. */ +LDP X4, X5, [ SP ], # 0x10 +LDP X2, X3, [ SP ], # 0x10 +LDP XZR, X1, [ SP ], # 0x10 +ERET + +5: +/* portSVC_UNMASK_ALL_INTERRUPTS: set ICC_PMR_EL1 to portUNMASK_VALUE to unmask all interrupts. */ +CMP X2, # portSVC_UNMASK_ALL_INTERRUPTS +B.NE 6f +/* Disable IRQs while updating PMR. */ +MSR DAIFSET, # 2 +DSB SY +ISB SY +MOV X0, #portUNMASK_VALUE /* Unmask all interrupts. */ +MSR ICC_PMR_EL1, X0 +DSB SY +ISB SY +/* Re-enable IRQs. */ +MSR DAIFCLR, # 2 +DSB SY +ISB SY +MSR ELR_EL1, X4 +MSR SPSR_EL1, X5 +LDP X4, X5, [SP], #0x10 +LDP X2, X3, [SP], #0x10 +LDP X0, X1, [SP], #0x10 +ERET + +6: +/* portSVC_UNMASK_INTERRUPTS: set ICC_PMR_EL1 to uxNewMaskValue stored in X0. */ +CMP X2, # portSVC_UNMASK_INTERRUPTS +B.NE 7f +/* Disable IRQs while updating PMR. */ +MSR DAIFSET, # 2 +DSB SY +ISB SY +LDR X0, [ SP, # 0x20 ] /* Original X0 */ +MSR ICC_PMR_EL1, X0 +DSB SY +ISB SY +/* Re-enable IRQs. */ +MSR DAIFCLR, # 2 +DSB SY +ISB SY +MSR ELR_EL1, X4 +MSR SPSR_EL1, X5 +LDP X4, X5, [SP], #0x10 +LDP X2, X3, [SP], #0x10 +LDP X0, X1, [SP], #0x10 +ERET + +7: +#if ( configENABLE_MPU == 1 ) + /* portSVC_CHECK_PRIVILEGE: Check if the task is a privileged task */ + CMP X2, # portSVC_CHECK_PRIVILEGE + B.NE 8f + savefuncontextgpregs + BL xPortIsTaskPrivileged + restorefuncontextgpregexceptx0 /* xPortIsTaskPrivileged() return value is stored in X0. */ + MSR ELR_EL1, X4 + MSR SPSR_EL1, X5 + /* Restore X5-X1 while discarding old X0. */ + LDP X4, X5, [ SP ], # 0x10 + LDP X2, X3, [ SP ], # 0x10 + LDP XZR, X1, [ SP ], # 0x10 + ERET +#endif /* #if ( configENABLE_MPU == 1 ) */ + +8: +/* portSVC_SAVE_TASK_CONTEXT: Save task's context */ +CMP X2, # portSVC_SAVE_TASK_CONTEXT +B.NE 9f +MSR ELR_EL1, X4 +MSR SPSR_EL1, X5 +/* Restore X5-X0. */ +LDP X4, X5, [ SP ], # 0x10 +LDP X2, X3, [ SP ], # 0x10 +LDP X0, X1, [ SP ], # 0x10 +portSAVE_CONTEXT +ERET + +9: +/* portSVC_RESTORE_CONTEXT: Restore task's context */ +CMP X2, # portSVC_RESTORE_CONTEXT +B.NE 10f +MSR ELR_EL1, X4 +MSR SPSR_EL1, X5 +/* Restore X5-X0. */ +LDP X4, X5, [ SP ], # 0x10 +LDP X2, X3, [ SP ], # 0x10 +LDP X0, X1, [ SP ], # 0x10 +portRESTORE_CONTEXT +ERET + +10: +/* portSVC_DELETE_CURRENT_TASK: Delete current task */ +CMP X2, # portSVC_DELETE_CURRENT_TASK +B.NE 11f +/* Restore X5-X0. */ +LDP X4, X5, [ SP ], #0x10 +LDP X2, X3, [ SP ], # 0x10 +LDP X0, X1, [ SP ], # 0x10 +#if ( configNUMBER_OF_CORES == 1 ) + adrp X0, pxCurrentTCB + add X0, X0, :lo12:pxCurrentTCB /* X0 = &pxCurrentTCB */ +#else + adrp X0, pxCurrentTCBs + add X0, X0, :lo12:pxCurrentTCBs /* X0 = &pxCurrentTCBs */ + /* Get the core ID to index the TCB correctly. */ + MRS X1, MPIDR_EL1 /* Read the Multiprocessor Affinity Register */ + AND X1, X1, # 0xff /* Extract Aff0 which contains the core ID */ + LSL X1, X1, # 3 /* Scale the core ID to the size of a pointer (64-bit system) */ + ADD X0, X0, X1 /* Add the offset for the current core's TCB pointer */ +#endif +LDR X0, [ X0 ] /* X0 = pxCurrentTCB */ +B vTaskDelete + +11: +/* portSVC_INTERRUPT_CORE: Interrupt core */ +CMP X2, # portSVC_INTERRUPT_CORE +B.NE 12f +LDR X0, [ SP, # 0x20 ] /* Original X0 */ +MSR ICC_SGI1R_EL1, X0 /* X0 contains the value to write to ICC_SGI1R_EL1 */ +MSR ELR_EL1, X4 +MSR SPSR_EL1, X5 +/* Restore X5-X0. */ +LDP X4, X5, [SP], #0x10 +LDP X2, X3, [ SP ], # 0x10 +LDP X0, X1, [ SP ], # 0x10 +ERET + +12: +#if ( configENABLE_MPU == 1 ) + /* ---------- SystemCallEnter? ---------------------------------*/ + LDR X3, =NUM_SYSTEM_CALLS + CMP X2, X3 + BLO 121f /* imm 0 … NUM_SYSCALLS-1 */ + + /* ---------- SystemCallExit? ----------------------------------*/ + LDR X3, =portSVC_SYSTEM_CALL_EXIT + CMP X2, X3 + BEQ 122f + +/* ---------- SystemCallEnter -------------------------------------*/ +121: + /* If calling task is privileged, directly tail-call the implementation at EL1. */ + savefuncontextgpregs + BL xPortIsTaskPrivileged + restorefuncontextgpregexceptx0 /* X0 holds pdTRUE if privileged */ + CBNZ X0, priv_path + + /* Unprivileged tasks path */ + #if ( configNUMBER_OF_CORES == 1 ) + adrp X0, pxCurrentTCB + add X0, X0, :lo12:pxCurrentTCB /* X0 = &pxCurrentTCB */ + #else + adrp X0, pxCurrentTCBs + add X0, X0, :lo12:pxCurrentTCBs /* X0 = &pxCurrentTCBs */ + /* Get the core ID to index the TCB correctly. */ + MRS X1, MPIDR_EL1 /* Read the Multiprocessor Affinity Register */ + AND X1, X1, # 0xff /* Extract Aff0 which contains the core ID */ + LSL X1, X1, # 3 /* Scale the core ID to the size of a pointer (64-bit system) */ + ADD X0, X0, X1 /* Add the offset for the current core's TCB pointer */ + #endif + LDR X0, [ X0 ] + LDR X0, [ X0 ] /* X0 = Location of saved context in TCB. */ + + /* Save inputs (X0-X3) and LR (X30) + * onto the current task's context to be used by the system call implementation. + */ + STR X30, [ X0, # ( portOFFSET_TO_LR * 8 ) ] + + /* Read original X0, X1, X2, and X3 from the EL1 stack without modifying SP, and store. + * [SP+0x20] -> X0, [SP+0x28] -> X1, [SP+0x10] -> X2, [SP+0x18] -> X3. */ + LDR X1, [ SP, # 0x20 ] /* Original X0 */ + STR X1, [ X0, # ( portOFFSET_TO_X0 * 8 ) ] + LDR X1, [ SP, # 0x28 ] /* Original X1 */ + STR X1, [ X0, # ( portOFFSET_TO_X1 * 8 ) ] + LDR X1, [ SP, # 0x10 ] /* Original X2 */ + STR X1, [ X0, # ( portOFFSET_TO_X2 * 8 ) ] + LDR X1, [ SP, # 0x18 ] /* Original X3 */ + STR X1, [ X0, # ( portOFFSET_TO_X3 * 8 ) ] + + /* Restore X2-X5 to their original values, discard X1 and X0 as they contain system call number + * and location of task's saved context in TCB. + */ + MOV X1, X2 /* Pass system call */ + LDP X4, X5, [ SP ], #0x10 + LDP X2, X3, [ SP ], #0x10 + ADD SP, SP, #0x10 /* Discard X0 and X1 */ + + savesyscallcontextgpregs + BL vSystemCallEnter /* returns after programming ELR/SPSR/SP_EL0 and args */ + /* Set LR for the syscall implementation to point to vRequestSystemCallExit. */ + adrp X30, vRequestSystemCallExit + add X30, X30, :lo12:vRequestSystemCallExit + restoresyscallcontextgpregs + ERET + +priv_path: + /* Load implementation address: uxSystemCallImplementations[X2] (64-bit entries). */ + adrp X3, uxSystemCallImplementations + add X3, X3, :lo12:uxSystemCallImplementations + LSL X2, X2, #3 /* Multiply index by size of pointer (8 bytes). */ + ADD X3, X3, X2 /* X3 = &uxSystemCallImplementations[X2] */ + LDR X3, [ X3 ] /* X3 = uxSystemCallImplementations[X2] */ + /* Return from exception directly to implementation; preserve original LR and registers. */ + MSR ELR_EL1, X3 + MSR SPSR_EL1, X5 + /* Restore X5-X0. */ + LDP X4, X5, [ SP ], #0x10 + LDP X2, X3, [ SP ], #0x10 + LDP X0, X1, [ SP ], #0x10 + ERET + + /* ---------- SystemCallExit -----------------------------------*/ +122: + LDR X0, [ SP, # 0x20 ] /* Restore X0 without changing SP as it contains system call return value */ + savefuncontextgpregs + BL vSystemCallExit + restorefuncontextgpregexceptx0 + /* Restore X5-X1 while discarding old X0. */ + LDP X4, X5, [ SP ], #0x10 + LDP X2, X3, [ SP ], #0x10 + LDP XZR, X1, [ SP ], #0x10 + ERET +#endif /* #if ( configENABLE_MPU == 1 ) */ + +/* ---------- Unexpected EC – just hang in place ---------------------------*/ +FreeRTOS_Abort: +B FreeRTOS_Abort + +FreeRTOS_Yield: +MSR SPSR_EL1, X5 + +/* Check if the task is in a critical section by inspecting ullCriticalNesting. */ +#if ( configNUMBER_OF_CORES > 1 ) + adrp X0, ullCriticalNestings + add X0, X0, :lo12:ullCriticalNestings /* X0 = &ullCriticalNestings */ + MRS X1, MPIDR_EL1 /* Read the Multiprocessor Affinity Register. */ + AND X1, X1, # 0xff /* Extract Aff0 (core ID). */ + LSL X1, X1, # 3 /* Multiply core ID by pointer size (8 bytes). */ + ADD X0, X0, X1 /* Add offset to base address. */ + LDR X1, [ X0 ] /* Load ullCriticalNesting for this core. */ + CBNZ X1, Skip_Context_Switch /* Skip context switch if in a critical section. */ +#endif + +/* Restore X5-X0 to their original values before saving full context. */ +LDP X4, X5, [SP], #0x10 +LDP X2, X3, [SP], #0x10 +LDP X0, X1, [SP], #0x10 +portSAVE_CONTEXT +savefuncontextgpregs +#if ( configNUMBER_OF_CORES > 1 ) + MRS x0, mpidr_el1 + AND x0, x0, 255 +#endif +BL vTaskSwitchContext +restorefuncontextgpregs +portRESTORE_CONTEXT +ERET + +Skip_Context_Switch: +/* Restore X5-X0 to their original values. */ +LDP X4, X5, [SP], #0x10 +LDP X2, X3, [SP], #0x10 +LDP X0, X1, [SP], #0x10 +ERET + +Start_First_Task: + /* Restore X5-X0 to their original values. */ + LDP X4, X5, [SP], #0x10 + LDP X2, X3, [SP], #0x10 + LDP X0, X1, [SP], #0x10 + portRESTORE_CONTEXT + ERET + +/****************************************************************************** + * vPortSaveTaskContext is used to save the task's context into its stack. + *****************************************************************************/ + .align 8 + .type vPortSaveTaskContext, % function +vPortSaveTaskContext: +portSAVE_CONTEXT +RET + +/****************************************************************************** + * vPortRestoreTaskContext is used to start the scheduler. + *****************************************************************************/ + .align 8 + .type vPortRestoreTaskContext, % function +vPortRestoreTaskContext: +.set freertos_vector_base, _freertos_vector_table +/* Install the FreeRTOS interrupt handlers. */ +LDR X1, = freertos_vector_base +MSR VBAR_EL1, X1 +DSB SY +ISB SY +/* Start the first task. */ +portRESTORE_CONTEXT +ERET + +/****************************************************************************** + * FreeRTOS_IRQ_Handler handles IRQ entry and exit. + * + * This handler is supposed to be used only for IRQs and never for FIQs. Per ARM + * GIC documentation [1], Group 0 interrupts are always signaled as FIQs. Since + * this handler is only for IRQs, We can safely assume Group 1 while accessing + * Interrupt Acknowledge and End Of Interrupt registers and therefore, use + * ICC_IAR1_EL1 and ICC_EOIR1_EL1. + * + * [1] https://developer.arm.com/documentation/198123/0300/Arm-CoreLink-GIC-fundamentals + *****************************************************************************/ + .align 8 + .type FreeRTOS_IRQ_Handler, % function +FreeRTOS_IRQ_Handler: +/* Save volatile registers. */ +saveallgpregisters +savefloatregisters + +/* Save the SPSR and ELR. */ +MRS X3, SPSR_EL1 +MRS X2, ELR_EL1 + +STP X2, X3, [ SP, # - 0x10 ] ! + +/* Increment the interrupt nesting counter. */ +#if ( configNUMBER_OF_CORES == 1 ) + adrp X5, ullPortInterruptNesting + add X5, X5, :lo12:ullPortInterruptNesting /* X5 = &ullPortInterruptNesting */ +#else + adrp X5, ullPortInterruptNestings + add X5, X5, :lo12:ullPortInterruptNestings /* X5 = &ullPortInterruptNestings */ + MRS X2, MPIDR_EL1 /* Read Multiprocessor Affinity Register. */ + AND X2, X2, # 0xff /* Extract Aff0, which contains the core ID. */ + LSL X2, X2, # 3 /* Scale core ID to the size of a pointer (assuming 64-bit system). */ + + /* Calculate offset for the current core's ullPortYieldRequired and load its address. */ + ADD X5, X5, X2 /* Add offset for the current core's ullPortYieldRequired. */ +#endif +LDR X1, [ X5 ] /* Old nesting count in X1. */ +ADD X6, X1, # 1 +STR X6, [ X5 ] /* Address of nesting count variable in X5. */ + +/* Maintain the interrupt nesting information across the function call. */ +STP X1, X5, [ SP, # - 0x10 ] ! + +/* Read interrupt ID from the interrupt acknowledge register and store it + * in X0 for future parameter and interrupt clearing use. */ +MRS X0, ICC_IAR1_EL1 + +/* Maintain the interrupt ID value across the function call. */ +STP X0, X1, [ SP, # - 0x10 ] ! + +savefuncontextgpregs +/* Call the C handler. */ +BL vApplicationIRQHandler +restorefuncontextgpregs + +/* Disable interrupts. */ +MSR DAIFSET, # 2 +DSB SY +ISB SY + +/* Restore the interrupt ID value. */ +LDP X0, X1, [ SP ], # 0x10 + +/* End IRQ processing by writing interrupt ID value to the EOI register. */ +MSR ICC_EOIR1_EL1, X0 + +/* Restore the critical nesting count. */ +LDP X1, X5, [ SP ], # 0x10 + +STR X1, [ X5 ] + +/* Has interrupt nesting unwound? */ +CMP X1, # 0 +B.NE Exit_IRQ_No_Context_Switch + +/* Is a context switch required? */ +adrp X0, ullPortYieldRequired +add X0, X0, :lo12:ullPortYieldRequired /* X0 = &ullPortYieldRequired */ +#if ( configNUMBER_OF_CORES > 1 ) + MRS X2, MPIDR_EL1 /* Read Multiprocessor Affinity Register. */ + AND X2, X2, # 0xff /* Extract Aff0, which contains the core ID. */ + LSL X2, X2, # 3 /* Scale core ID to the size of a pointer (assuming 64-bit system). */ +/* Calculate offset for the current core's ullPortYieldRequired and load its address. */ + ADD X0, X0, X2 /* Add offset for the current core's ullPortYieldRequired. */ +#endif +LDR X1, [ X0 ] +CMP X1, # 0 +B.EQ Exit_IRQ_No_Context_Switch + +/* Check if the task is in a critical section by inspecting ullCriticalNesting. */ +#if ( configNUMBER_OF_CORES > 1 ) + adrp X0, ullCriticalNestings + add X0, X0, :lo12:ullCriticalNestings /* X0 = &ullCriticalNestings */ + MRS X1, MPIDR_EL1 /* Read the Multiprocessor Affinity Register. */ + AND X1, X1, # 0xff /* Extract Aff0 (core ID). */ + LSL X1, X1, # 3 /* Multiply core ID by pointer size (8 bytes). */ + ADD X0, X0, X1 /* Add offset to base address. */ + LDR X1, [ X0 ] /* Load ullCriticalNesting for this core. */ + CBNZ X1, Exit_IRQ_No_Context_Switch /* Skip context switch if in a critical section. */ +#endif + +/* Reset ullPortYieldRequired to 0. */ +MOV X2, # 0 +STR X2, [ X0 ] + +/* Restore volatile registers. */ +LDP X4, X5, [ SP ], # 0x10 /* SPSR and ELR. */ + +MSR SPSR_EL1, X5 +MSR ELR_EL1, X4 +DSB SY +ISB SY + +restorefloatregisters +restoreallgpregisters + +/* Save the context of the current task and select a new task to run. */ +portSAVE_CONTEXT +#if configNUMBER_OF_CORES > 1 + MRS x0, mpidr_el1 + AND x0, x0, 255 +#endif +savefuncontextgpregs +BL vTaskSwitchContext +restorefuncontextgpregs +portRESTORE_CONTEXT +ERET + +Exit_IRQ_No_Context_Switch: +/* Restore volatile registers. */ +LDP X4, X5, [ SP ], # 0x10 /* SPSR and ELR. */ + +MSR SPSR_EL1, X5 +MSR ELR_EL1, X4 +DSB SY +ISB SY + +restorefloatregisters +restoreallgpregisters + +ERET + +/****************************************************************************** + * If the application provides an implementation of vApplicationIRQHandler(), + * then it will get called directly without saving the FPU registers on + * interrupt entry, and this weak implementation of + * vApplicationIRQHandler() will not get called. + * + * If the application provides its own implementation of + * vApplicationFPUSafeIRQHandler() then this implementation of + * vApplicationIRQHandler() will be called, save the FPU registers, and then + * call vApplicationFPUSafeIRQHandler(). + * + * Therefore, if the application writer wants FPU registers to be saved on + * interrupt entry their IRQ handler must be called + * vApplicationFPUSafeIRQHandler(), and if the application writer does not want + * FPU registers to be saved on interrupt entry their IRQ handler must be + * called vApplicationIRQHandler(). + *****************************************************************************/ + + .align 8 + .weak vApplicationIRQHandler + .type vApplicationIRQHandler, % function +vApplicationIRQHandler: + +/* Save FPU registers (32 128-bits + 2 64-bits configuration and status registers). */ +savefloatregisters + +savefuncontextgpregs +/* Call the C handler. */ +BL vApplicationFPUSafeIRQHandler +restorefuncontextgpregs + +/* Restore FPU registers. */ +restorefloatregisters + +RET + .end diff --git a/portable/GCC/ARM_CR82/portmacro.h b/portable/GCC/ARM_CR82/portmacro.h new file mode 100644 index 000000000..0df69921c --- /dev/null +++ b/portable/GCC/ARM_CR82/portmacro.h @@ -0,0 +1,541 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2025-2026 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE size_t +#define portBASE_TYPE long + +#if !defined(__ASSEMBLER__) + typedef portSTACK_TYPE StackType_t; + typedef portBASE_TYPE BaseType_t; + typedef uint64_t UBaseType_t; + + typedef uint64_t TickType_t; + #define portMAX_DELAY ( ( TickType_t ) 0xffffffffffffffff ) +#endif /* if !defined(__ASSEMBLER__) */ + +/* 64-bit tick type on a 64-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ +#define portTICK_TYPE_IS_ATOMIC 1 + +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 16 +#define portPOINTER_SIZE_TYPE uint64_t + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +#if !defined(__ASSEMBLER__) + /* Called at the end of an ISR that can cause a context switch. */ + #if ( configNUMBER_OF_CORES == 1 ) + #define portEND_SWITCHING_ISR( xSwitchRequired ) \ + { \ + extern uint64_t ullPortYieldRequired; \ + \ + if( xSwitchRequired != pdFALSE ) \ + { \ + ullPortYieldRequired = pdTRUE; \ + } \ + } + #else + #define portEND_SWITCHING_ISR( xSwitchRequired ) \ + { \ + extern uint64_t ullPortYieldRequired[ configNUMBER_OF_CORES ]; \ + \ + if( xSwitchRequired != pdFALSE ) \ + { \ + ullPortYieldRequired[ portGET_CORE_ID() ] = pdTRUE; \ + } \ + } + #endif /* if ( configNUMBER_OF_CORES == 1 ) */ +#endif /* if !defined(__ASSEMBLER__) */ + +/** + * @brief SVC numbers. + */ + +#define portSVC_SYSTEM_CALL_EXIT 104 +#define portSVC_YIELD 105 +#define portSVC_START_FIRST_TASK 106 +#define portSVC_DISABLE_INTERRUPTS 107 +#define portSVC_ENABLE_INTERRUPTS 108 +#define portSVC_GET_CORE_ID 109 +#define portSVC_MASK_ALL_INTERRUPTS 110 +#define portSVC_UNMASK_ALL_INTERRUPTS 111 +#define portSVC_UNMASK_INTERRUPTS 112 +#define portSVC_CHECK_PRIVILEGE 113 +#define portSVC_SAVE_TASK_CONTEXT 114 +#define portSVC_RESTORE_CONTEXT 115 +#define portSVC_DELETE_CURRENT_TASK 116 +#define portSVC_INTERRUPT_CORE 117 + +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#define portYIELD() __asm volatile ( "SVC %0" : : "i" ( portSVC_YIELD ) : "memory" ) + +/*----------------------------------------------------------- +* Critical section control +*----------------------------------------------------------*/ + +#if !defined(__ASSEMBLER__) + extern UBaseType_t vTaskEnterCriticalFromISR( void ); + extern void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus ); + extern UBaseType_t uxPortSetInterruptMask( void ); + extern UBaseType_t uxPortSetInterruptMaskFromISR( void ); + extern void vPortClearInterruptMask( UBaseType_t uxNewMaskValue ); + extern void vPortClearInterruptMaskFromISR( UBaseType_t uxNewMaskValue ); + extern void vInterruptCore( uint32_t ulInterruptID, uint8_t ucCoreID ); +#endif /* if !defined(__ASSEMBLER__) */ + +/* Use SVC so this is safe from EL0. EL1 sites in the port use direct MSR. */ +#define portDISABLE_INTERRUPTS() __asm volatile ( "SVC %0" : : "i" ( portSVC_DISABLE_INTERRUPTS ) : "memory" ) + +#define portENABLE_INTERRUPTS() __asm volatile ( "SVC %0" : : "i" ( portSVC_ENABLE_INTERRUPTS ) : "memory" ) + +/* In all GICs 255 can be written to the priority mask register to unmask all + * (but the lowest) interrupt priority. */ +#define portUNMASK_VALUE ( 0xFFUL ) + +#if !defined(__ASSEMBLER__) + /* These macros do not globally disable/enable interrupts. They do mask off + * interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */ + #if ( configNUMBER_OF_CORES == 1 ) + extern void vPortEnterCritical( void ); + extern void vPortExitCritical( void ); + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() + #else + #define portENTER_CRITICAL() vTaskEnterCritical() + #define portEXIT_CRITICAL() vTaskExitCritical() + #endif + #define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortClearInterruptMaskFromISR( x ) + #define portENTER_CRITICAL_FROM_ISR() vTaskEnterCriticalFromISR() + #define portEXIT_CRITICAL_FROM_ISR( x ) vTaskExitCriticalFromISR( x ) +#endif /* if !defined(__ASSEMBLER__) */ + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not required for this port but included in case common demo code that uses these + * macros is used. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +#if !defined(__ASSEMBLER__) + /* Prototype of the FreeRTOS tick handler. This must be installed as the + * handler for whichever peripheral is used to generate the RTOS tick. */ + void FreeRTOS_Tick_Handler( void ); +#endif /* if !defined(__ASSEMBLER__) */ + +#define portTASK_NO_FPU_CONTEXT_BY_DEFAULT ( 1U ) +#define portTASK_HAVE_FPU_CONTEXT_BY_DEFAULT ( 2U ) + +/* If configUSE_TASK_FPU_SUPPORT is set to portTASK_NO_FPU_CONTEXT_BY_DEFAULT (1U) + * (or left undefined) then tasks are created without an FPU context and + * must call vPortTaskUsesFPU() to give themselves an FPU context before + * using any FPU instructions. If configUSE_TASK_FPU_SUPPORT is set to + * portTASK_HAVE_FPU_CONTEXT_BY_DEFAULT (2U) then all tasks will have an FPU context + * by default. */ +#if ( configUSE_TASK_FPU_SUPPORT == portTASK_NO_FPU_CONTEXT_BY_DEFAULT ) + void vPortTaskUsesFPU( void ); +#else +/* Each task has an FPU context already, so define this function away to + * nothing to prevent it from being called accidentally. */ + #define vPortTaskUsesFPU() +#endif + +#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() + +#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL ) +#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL ) + +/* Architecture specific optimisations. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + + /* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +#if ( configASSERT_DEFINED == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif /* configASSERT */ + +#define portNOP() __asm volatile ( "NOP" ) +#define portINLINE __inline + +/* The number of bits to shift for an interrupt priority is dependent on the + * number of bits implemented by the interrupt controller. */ +#if configUNIQUE_INTERRUPT_PRIORITIES == 16 + #define portPRIORITY_SHIFT 4 + #define portMAX_BINARY_POINT_VALUE 3 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 32 + #define portPRIORITY_SHIFT 3 + #define portMAX_BINARY_POINT_VALUE 2 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 64 + #define portPRIORITY_SHIFT 2 + #define portMAX_BINARY_POINT_VALUE 1 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 128 + #define portPRIORITY_SHIFT 1 + #define portMAX_BINARY_POINT_VALUE 0 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 256 + #define portPRIORITY_SHIFT 0 + #define portMAX_BINARY_POINT_VALUE 0 +#else /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */ + #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware +#endif /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */ + +#define portINTERRUPT_PRIORITY_REGISTER_OFFSET ( 0x400U ) +#define portYIELD_CORE_INT_ID ( 0x0U ) +#define portMAX_API_PRIORITY_MASK ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) + +#if ( configNUMBER_OF_CORES > 1 ) + + #if !defined(__ASSEMBLER__) + typedef enum + { + eIsrLock = 0, + eTaskLock, + eLockCount + } ePortRTOSLock; + + extern volatile uint64_t ullCriticalNestings[ configNUMBER_OF_CORES ]; + extern void vPortRecursiveLock( uint8_t ucCoreID, + ePortRTOSLock eLockNum, + BaseType_t uxAcquire ); + extern uint8_t ucPortGetCoreID( void ); + extern uint8_t ucPortGetCoreIDFromIsr( void ); + #endif /* if !defined(__ASSEMBLER__) */ + + #define portSET_INTERRUPT_MASK() uxPortSetInterruptMask() + #define portCLEAR_INTERRUPT_MASK( x ) vPortClearInterruptMask( x ) + + #define portMAX_CORE_COUNT configNUMBER_OF_CORES + #define portGET_CORE_ID() ucPortGetCoreID() + #define portGET_CORE_ID_FROM_ISR() ucPortGetCoreIDFromIsr() + + /* Use SGI 0 as the yield core interrupt. */ + #define portYIELD_CORE( xCoreID ) vInterruptCore( portYIELD_CORE_INT_ID, ( uint8_t ) xCoreID ) + + #define portRELEASE_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdFALSE ) + #define portGET_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdTRUE ) + + #define portRELEASE_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdFALSE ) + #define portGET_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdTRUE ) + #define portGET_CRITICAL_NESTING_COUNT( xCoreID ) ( ullCriticalNestings[ ( uint8_t ) xCoreID ] ) + #define portSET_CRITICAL_NESTING_COUNT( xCoreID, x ) ( ullCriticalNestings[ ( uint8_t ) xCoreID ] = ( x ) ) + #define portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ullCriticalNestings[ ( uint8_t ) xCoreID ]++ ) + #define portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ullCriticalNestings[ ( uint8_t ) xCoreID ]-- ) + +#endif /* configNUMBER_OF_CORES > 1 */ + +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) + +/** + * @brief MPU specific constants. + */ +#if ( configENABLE_MPU == 1 ) + + #if !defined(__ASSEMBLER__) + extern BaseType_t xPortIsTaskPrivileged( void ); + #endif /* if !defined(__ASSEMBLER__) */ + + /* Device memory attributes used in MAIR_EL1 registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00. + */ + #define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) + #define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) + #define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) + #define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) + + /* MPU settings that can be overridden in FreeRTOSConfig.h. */ + #ifndef configTOTAL_MPU_REGIONS + #define configTOTAL_MPU_REGIONS ( 16UL ) + #endif + + #define portPRIVILEGED_FLASH_REGION ( 0ULL ) /* Privileged flash region number. */ + #define portUNPRIVILEGED_FLASH_REGION ( 1ULL ) /* Unprivileged flash region number. */ + #define portUNPRIVILEGED_SYSCALLS_REGION ( 2ULL ) /* Unprivileged syscalls region number. */ + #define portPRIVILEGED_RAM_REGION ( 3ULL ) /* Privileged RAM region number. */ + #define portSTACK_REGION ( 4ULL ) /* Stack region number. */ + #define portSTACK_REGION_INDEX ( 0ULL ) /* Stack region index in the xRegionSettings array. */ + #define portFIRST_CONFIGURABLE_REGION ( 5ULL ) /* First user configurable region number. */ + #define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) + #define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) + #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + #define portACL_ENTRY_SIZE_BITS ( 32UL ) + #endif /* configENABLE_ACCESS_CONTROL_LIST == 1 */ + + #if !defined(__ASSEMBLER__) + /** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint64_t ullPrbarEl1; /**< PRBAR_EL1 for the region. */ + uint64_t ullPrlarEl1; /**< PRLAR_EL1 for the region. */ + } MPURegionSettings_t; + + #ifndef configSYSTEM_CALL_STACK_SIZE + #define configSYSTEM_CALL_STACK_SIZE 128 /* must be defined to the desired size of the system call stack in words for using MPU wrappers v2. */ + #endif + + /** + * @brief System call info. + */ + typedef struct SYSTEM_CALL_INFO + { + /* Used to save both the user-mode stack pointer (SP_EL0) and link register (X30) + * at system call entry so they can be restored or referenced safely even if the task + * switches out while executing the system call. + */ + uint64_t ullLinkRegisterAtSystemCallEntry; + uint64_t ullUserSPAtSystemCallEntry; + } xSYSTEM_CALL_INFO; + #endif /* if !defined(__ASSEMBLER__) */ + + /** + * @brief Task context as stored in the TCB. + */ + #if ( configENABLE_FPU == 1 ) + /* + * +-----------+------------+--------------------------------+-------------+------------------+ + * | Q0-Q31 | FPSR, FPCR | CRITICAL_NESTING, FPU_CONTEXT | X0-X30, XZR | INIT_PSTATE, PC | + * +-----------+------------+--------------------------------+-------------+------------------+ + * + * <-----------><-----------><-------------------------------><------------><-----------------> + * 64 2 2 32 2 + */ + #define MAX_CONTEXT_SIZE 102 + + #else /* #if ( configENABLE_FPU == 1 ) */ + /* + * +--------------------------------+-------------+------------------+ + * | CRITICAL_NESTING, FPU_CONTEXT | X0-X30, XZR | INIT_PSTATE, PC | + * +--------------------------------+-------------+------------------+ + * <-------------------------------><------------><------------------> + * 2 32 2 + */ + #define MAX_CONTEXT_SIZE 36 + #endif /* #if ( configENABLE_FPU == 1 ) */ + + #if !defined(__ASSEMBLER__) + typedef struct MPU_SETTINGS + { + uint64_t ullTaskUnprivilegedSP; /* Task's unprivileged user stack pointer. */ + uint64_t ullMairEl1; /* MAIR_EL1 for the task containing attributes. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /* Settings for tasks' regions. */ + uint64_t ullContext[ MAX_CONTEXT_SIZE + configSYSTEM_CALL_STACK_SIZE ]; /* Task's saved context. */ + uint64_t ullTaskFlags; + + xSYSTEM_CALL_INFO xSystemCallInfo; + + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ]; + #endif /* configENABLE_ACCESS_CONTROL_LIST */ + } xMPU_SETTINGS; + #endif /* if !defined(__ASSEMBLER__) */ + + #define portUSING_MPU_WRAPPERS ( 1 ) + #define portPRIVILEGE_BIT ( 0x80000000UL ) + + /* Normal memory attributes used in MAIR_EL1 registers. */ + #define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ + #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + + #define portMPU_MAIR_EL1_ATTR0_POS ( 0UL ) + #define portMPU_MAIR_EL1_ATTR0_MASK ( 0x00000000000000ffULL ) + + #define portMPU_MAIR_EL1_ATTR1_POS ( 8UL ) + #define portMPU_MAIR_EL1_ATTR1_MASK ( 0x000000000000ff00ULL ) + + #define portMPU_MAIR_EL1_ATTR2_POS ( 16UL ) + #define portMPU_MAIR_EL1_ATTR2_MASK ( 0x0000000000ff0000ULL ) + + #define portMPU_MAIR_EL1_ATTR3_POS ( 24UL ) + #define portMPU_MAIR_EL1_ATTR3_MASK ( 0x00000000ff000000ULL ) + + #define portMPU_MAIR_EL1_ATTR4_POS ( 32UL ) + #define portMPU_MAIR_EL1_ATTR4_MASK ( 0x000000ff00000000ULL ) + + #define portMPU_MAIR_EL1_ATTR5_POS ( 40UL ) + #define portMPU_MAIR_EL1_ATTR5_MASK ( 0x0000ff0000000000ULL ) + + #define portMPU_MAIR_EL1_ATTR6_POS ( 48UL ) + #define portMPU_MAIR_EL1_ATTR6_MASK ( 0x00ff000000000000ULL ) + + #define portMPU_MAIR_EL1_ATTR7_POS ( 56UL ) + #define portMPU_MAIR_EL1_ATTR7_MASK ( 0xff00000000000000ULL ) + + #define portMPU_PRBAR_EL1_ADDRESS_MASK ( 0x0000FFFFFFFFFFC0ULL ) + #define portMPU_PRLAR_EL1_ADDRESS_MASK ( 0x0000FFFFFFFFFFC0ULL ) + #define portMPU_PRBAR_EL1_ACCESS_PERMISSIONS_MASK ( 3ULL<< 2ULL ) + + #define portMPU_REGION_NON_SHAREABLE ( 0ULL << 4ULL ) + #define portMPU_REGION_OUTER_SHAREABLE ( 2ULL << 4ULL ) + #define portMPU_REGION_INNER_SHAREABLE ( 3ULL << 4ULL ) + + #define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0ULL << 2ULL ) + #define portMPU_REGION_READ_WRITE ( 1ULL << 2ULL ) + #define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2ULL << 2ULL ) + #define portMPU_REGION_READ_ONLY ( 3ULL << 2ULL ) + + #define portMPU_REGION_EXECUTE_NEVER ( 1ULL << 1ULL ) + + #define portMPU_PRLAR_EL1_ATTR_INDEX0 ( 0ULL << 1ULL ) + #define portMPU_PRLAR_EL1_ATTR_INDEX1 ( 1ULL << 1ULL ) + #define portMPU_PRLAR_EL1_ATTR_INDEX2 ( 2ULL << 1ULL ) + #define portMPU_PRLAR_EL1_ATTR_INDEX3 ( 3ULL << 1ULL ) + #define portMPU_PRLAR_EL1_ATTR_INDEX4 ( 4ULL << 1ULL ) + #define portMPU_PRLAR_EL1_ATTR_INDEX5 ( 5ULL << 1ULL ) + #define portMPU_PRLAR_EL1_ATTR_INDEX6 ( 6ULL << 1ULL ) + #define portMPU_PRLAR_EL1_ATTR_INDEX7 ( 7ULL << 1ULL ) + + #define portMPU_PRLAR_EL1_REGION_ENABLE ( 1ULL ) + + #define portMPU_ENABLE_BIT ( 1ULL << 0ULL ) + #define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1ULL << 17ULL ) + + /* Max value that fits in a uint64_t type. */ + #define portUINT64_MAX ( ~( ( uint64_t ) 0 ) ) + #define portADD_UINT64_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT64_MAX - ( b ) ) ) + + /* Extract first address of the MPU region as encoded in the + * PRBAR_EL1 register value. */ + #define portEXTRACT_FIRST_ADDRESS_FROM_PRBAR_EL1( prbar_el1 ) \ + ( ( prbar_el1 ) & portMPU_PRBAR_EL1_ADDRESS_MASK ) + + /* Extract last address of the MPU region as encoded in the + * PRLAR_EL1 register value. */ + #define portEXTRACT_LAST_ADDRESS_FROM_PRLAR_EL1( prlar_el1 ) \ + ( ( ( prlar_el1 ) & portMPU_PRLAR_EL1_ADDRESS_MASK ) | ~portMPU_PRLAR_EL1_ADDRESS_MASK ) + + /* Does addr lies within [start, end] address range? */ + #define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \ + ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) ) + + /* Is the access request satisfied by the available permissions? */ + #define portIS_AUTHORIZED( accessRequest, permissions ) \ + ( ( ( permissions ) & ( accessRequest ) ) == accessRequest ) + + /** + * @brief Offsets in the task's stack (context). + */ + #if ( configUSE_TASK_FPU_SUPPORT == portTASK_HAVE_FPU_CONTEXT_BY_DEFAULT ) + #define portOFFSET_TO_PC ( 68 ) + #define portOFFSET_TO_LR ( 70 ) + #define portOFFSET_TO_X0 ( 100 ) + #define portOFFSET_TO_X1 ( 101 ) + #define portOFFSET_TO_X2 ( 98 ) + #define portOFFSET_TO_X3 ( 99 ) + #else + #define portOFFSET_TO_PC ( 2 ) + #define portOFFSET_TO_LR ( 4 ) + #define portOFFSET_TO_X0 ( 34 ) + #define portOFFSET_TO_X1 ( 35 ) + #define portOFFSET_TO_X2 ( 32 ) + #define portOFFSET_TO_X3 ( 33 ) + #endif + + /** + * @brief Flag used to mark that a Task is privileged. + * + * @ingroup Port Privilege + */ + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) + + /** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() + +#else + + #define portPRIVILEGE_BIT ( 0x0UL ) + +#endif /* #if ( configENABLE_MPU == 1 ) */ + +#define portPSTATE_I_BIT ( 0x7 ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/ARM_CRx_MPU/mpu_wrappers_v2_asm.S b/portable/GCC/ARM_CRx_MPU/mpu_wrappers_v2_asm.S new file mode 100644 index 000000000..caf31ff76 --- /dev/null +++ b/portable/GCC/ARM_CRx_MPU/mpu_wrappers_v2_asm.S @@ -0,0 +1,867 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* ----------------------------------------------------------------------------------- */ + + .arm + .syntax unified + .section freertos_system_calls, "ax" + +#define FREERTOS_ASSEMBLY + #include "FreeRTOSConfig.h" + #include "portmacro_asm.h" + #include "mpu_syscall_numbers.h" +#undef FREERTOS_ASSEMBLY + +/* ----------------------- Start of Port Specific System Calls ----------------------- */ + +/* + * void vPortYield( void ); + */ +.align 4 +.global vPortYield +.type vPortYield, %function +vPortYield: + SVC #portSVC_YIELD + BX LR + +/* ----------------------------------------------------------------------------------- */ + +/* + * void vPortSystemCallExit( void ); + */ +.align 4 +.global vPortSystemCallExit +.type vPortSystemCallExit, %function +vPortSystemCallExit: + SVC #portSVC_SYSTEM_CALL_EXIT + BX LR + +/* ----------------------------------------------------------------------------------- */ + +/* + * BaseType_t xPortIsPrivileged( void ); + * + * According to the Procedure Call Standard for the ARM Architecture (AAPCS): + * - Return value must be in R0. + */ +.align 4 +.global xPortIsPrivileged +.type xPortIsPrivileged, %function +xPortIsPrivileged: + MRS R0, CPSR /* R0 = CPSR. */ + AND R0, R0, #0x1F /* R0 = R0 & 0x1F. Extract mode bits.*/ + CMP R0, #USER_MODE /* If R0 == #USER_MODE. */ + MOVEQ R0, #0x0 /* Then, set R0 to 0 to indicate that the processer is not privileged. */ + MOVNE R0, #0x01 /* Otherwise, set R0 to 1 to indicate that the processer is privileged. */ + BX LR + +/* ----------------------------------------------------------------------------------- */ + +/* + * UBaseType_t ulPortCountLeadingZeros( UBaseType_t ulBitmap ); + * + * According to the Procedure Call Standard for the ARM Architecture (AAPCS): + * - Parameter ulBitmap is passed in R0. + * - Return value must be in R0. + */ +.align 4 +.weak ulPortCountLeadingZeros +.type ulPortCountLeadingZeros, %function +ulPortCountLeadingZeros: + CLZ R0, R0 + BX LR + +/* ------------------- End of Port Specific System Calls ------------------- */ + +.macro INVOKE_SYSTEM_CALL systemCallNumber, systemCallImpl + PUSH {R0} + MRS R0, CPSR + AND R0, R0, #0x1F + CMP R0, #USER_MODE + POP {R0} + SVCEQ \systemCallNumber + B \systemCallImpl +.endm + +/* ----------------------------------------------------------------------------------- */ + +.extern MPU_xTaskGetTickCountImpl +.align 4 +.global MPU_xTaskGetTickCount +.type MPU_xTaskGetTickCount, function +MPU_xTaskGetTickCount: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTaskGetTickCount, MPU_xTaskGetTickCountImpl + +/* ----------------------------------------------------------------------------------- */ + +.extern MPU_uxTaskGetNumberOfTasksImpl +.align 4 +.global MPU_uxTaskGetNumberOfTasks +.type MPU_uxTaskGetNumberOfTasks, function +MPU_uxTaskGetNumberOfTasks: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_uxTaskGetNumberOfTasks, MPU_uxTaskGetNumberOfTasksImpl + +/* ----------------------------------------------------------------------------------- */ + +.extern MPU_vTaskSetTimeOutStateImpl +.align 4 +.global MPU_vTaskSetTimeOutState +.type MPU_vTaskSetTimeOutState, function +MPU_vTaskSetTimeOutState: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_vTaskSetTimeOutState, MPU_vTaskSetTimeOutStateImpl + +/* ----------------------------------------------------------------------------------- */ + +.extern MPU_xTaskCheckForTimeOutImpl +.align 4 +.global MPU_xTaskCheckForTimeOut +.type MPU_xTaskCheckForTimeOut, function +MPU_xTaskCheckForTimeOut: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTaskCheckForTimeOut, MPU_xTaskCheckForTimeOutImpl + +/* ----------------------------------------------------------------------------------- */ + +.extern MPU_xQueueGenericSendImpl +.align 4 +.global MPU_xQueueGenericSend +.type MPU_xQueueGenericSend, function +MPU_xQueueGenericSend: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_xQueueGenericSend, MPU_xQueueGenericSendImpl + +/* ----------------------------------------------------------------------------------- */ + +.extern MPU_uxQueueMessagesWaitingImpl +.align 4 +.global MPU_uxQueueMessagesWaiting +.type MPU_uxQueueMessagesWaiting, function +MPU_uxQueueMessagesWaiting: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_uxQueueMessagesWaiting, MPU_uxQueueMessagesWaitingImpl + +/* ----------------------------------------------------------------------------------- */ + +.extern MPU_uxQueueSpacesAvailableImpl +.align 4 +.global MPU_uxQueueSpacesAvailable +.type MPU_uxQueueSpacesAvailable, function +MPU_uxQueueSpacesAvailable: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_uxQueueSpacesAvailable, MPU_uxQueueSpacesAvailableImpl + +/* ----------------------------------------------------------------------------------- */ + +.extern MPU_xQueueReceiveImpl +.align 4 +.global MPU_xQueueReceive +.type MPU_xQueueReceive, function +MPU_xQueueReceive: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_xQueueReceive, MPU_xQueueReceiveImpl + +/* ----------------------------------------------------------------------------------- */ + +.extern MPU_xQueuePeekImpl +.align 4 +.global MPU_xQueuePeek +.type MPU_xQueuePeek, function +MPU_xQueuePeek: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_xQueuePeek, MPU_xQueuePeekImpl + +/* ----------------------------------------------------------------------------------- */ + +.extern MPU_xQueueSemaphoreTakeImpl +.align 4 +.global MPU_xQueueSemaphoreTake +.type MPU_xQueueSemaphoreTake, function +MPU_xQueueSemaphoreTake: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_xQueueSemaphoreTake, MPU_xQueueSemaphoreTakeImpl + +/* ----------------------------------------------------------------------------------- */ + +#if ( configUSE_EVENT_GROUPS == 1 ) + + .extern MPU_xEventGroupWaitBitsImpl + .align 4 + .global MPU_xEventGroupWaitBitsEntry + .type MPU_xEventGroupWaitBitsEntry, function + MPU_xEventGroupWaitBitsEntry: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_xEventGroupWaitBits, MPU_xEventGroupWaitBitsImpl + + /* ----------------------------------------------------------------------------------- */ + + .extern MPU_xEventGroupClearBitsImpl + .align 4 + .global MPU_xEventGroupClearBits + .type MPU_xEventGroupClearBits, function + MPU_xEventGroupClearBits: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_xEventGroupClearBits, MPU_xEventGroupClearBitsImpl + + /* ----------------------------------------------------------------------------------- */ + + .extern MPU_xEventGroupSetBitsImpl + .align 4 + .global MPU_xEventGroupSetBits + .type MPU_xEventGroupSetBits, function + MPU_xEventGroupSetBits: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_xEventGroupSetBits, MPU_xEventGroupSetBitsImpl + + /* ----------------------------------------------------------------------------------- */ + + .extern MPU_xEventGroupSyncImpl + .align 4 + .global MPU_xEventGroupSync + .type MPU_xEventGroupSync, function + MPU_xEventGroupSync: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_xEventGroupSync, MPU_xEventGroupSyncImpl + +#endif /* if ( configUSE_EVENT_GROUPS == 1 ) */ + +/* ----------------------------------------------------------------------------------- */ + +#if ( configUSE_STREAM_BUFFERS == 1 ) + + .extern MPU_xStreamBufferSendImpl + .align 4 + .global MPU_xStreamBufferSend + .type MPU_xStreamBufferSend, function + MPU_xStreamBufferSend: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_xStreamBufferSend, MPU_xStreamBufferSendImpl + + /* ----------------------------------------------------------------------------------- */ + + .extern MPU_xStreamBufferReceiveImpl + .align 4 + .global MPU_xStreamBufferReceive + .type MPU_xStreamBufferReceive, function + MPU_xStreamBufferReceive: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_xStreamBufferReceive, MPU_xStreamBufferReceiveImpl + + /* ----------------------------------------------------------------------------------- */ + + .extern MPU_xStreamBufferIsFullImpl + .align 4 + .global MPU_xStreamBufferIsFull + .type MPU_xStreamBufferIsFull, function + MPU_xStreamBufferIsFull: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_xStreamBufferIsFull, MPU_xStreamBufferIsFullImpl + + /* ----------------------------------------------------------------------------------- */ + + .extern MPU_xStreamBufferIsEmptyImpl + .align 4 + .global MPU_xStreamBufferIsEmpty + .type MPU_xStreamBufferIsEmpty, function + MPU_xStreamBufferIsEmpty: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_xStreamBufferIsEmpty, MPU_xStreamBufferIsEmptyImpl + + /* ----------------------------------------------------------------------------------- */ + + .extern MPU_xStreamBufferSpacesAvailableImpl + .align 4 + .global MPU_xStreamBufferSpacesAvailable + .type MPU_xStreamBufferSpacesAvailable, function + MPU_xStreamBufferSpacesAvailable: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_xStreamBufferSpacesAvailable, MPU_xStreamBufferSpacesAvailableImpl + + /* ----------------------------------------------------------------------------------- */ + + .extern MPU_xStreamBufferBytesAvailableImpl + .align 4 + .global MPU_xStreamBufferBytesAvailable + .type MPU_xStreamBufferBytesAvailable, function + MPU_xStreamBufferBytesAvailable: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_xStreamBufferBytesAvailable, MPU_xStreamBufferBytesAvailableImpl + + /* ----------------------------------------------------------------------------------- */ + + .extern MPU_xStreamBufferSetTriggerLevelImpl + .align 4 + .global MPU_xStreamBufferSetTriggerLevel + .type MPU_xStreamBufferSetTriggerLevel, function + MPU_xStreamBufferSetTriggerLevel: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_xStreamBufferSetTriggerLevel, MPU_xStreamBufferSetTriggerLevelImpl + + /* ----------------------------------------------------------------------------------- */ + + .extern MPU_xStreamBufferNextMessageLengthBytesImpl + .align 4 + .global MPU_xStreamBufferNextMessageLengthBytes + .type MPU_xStreamBufferNextMessageLengthBytes, function + MPU_xStreamBufferNextMessageLengthBytes: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes, MPU_xStreamBufferNextMessageLengthBytesImpl + +#endif /* if ( configUSE_STREAM_BUFFERS == 1 ) */ + +/* ----------------------------------------------------------------------------------- */ + +#if ( ( INCLUDE_xTaskDelayUntil == 1 ) || ( INCLUDE_vTaskDelayUntil == 1 ) ) + + .extern MPU_xTaskDelayUntilImpl + .align 4 + .global MPU_xTaskDelayUntil + .type MPU_xTaskDelayUntil, function + MPU_xTaskDelayUntil: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTaskDelayUntil, MPU_xTaskDelayUntilImpl + +#endif /* if ( ( INCLUDE_xTaskDelayUntil == 1 ) || ( INCLUDE_vTaskDelayUntil == 1 ) ) */ + +/* ----------------------------------------------------------------------------------- */ + +#if ( INCLUDE_xTaskAbortDelay == 1 ) + + .extern MPU_xTaskAbortDelayImpl + .align 4 + .global MPU_xTaskAbortDelay + .type MPU_xTaskAbortDelay, function + MPU_xTaskAbortDelay: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTaskAbortDelay, MPU_xTaskAbortDelayImpl + +#endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */ + +/* ------------------------------------------------------------------------------- */ + +#if ( INCLUDE_vTaskDelay == 1 ) + + .extern MPU_vTaskDelayImpl + .align 4 + .global MPU_vTaskDelay + .type MPU_vTaskDelay, function + MPU_vTaskDelay: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_vTaskDelay, MPU_vTaskDelayImpl + +#endif /* if ( INCLUDE_vTaskDelay == 1 ) */ + +/* ------------------------------------------------------------------------------- */ + +#if ( INCLUDE_uxTaskPriorityGet == 1 ) + + .extern MPU_uxTaskPriorityGetImpl + .align 4 + .global MPU_uxTaskPriorityGet + .type MPU_uxTaskPriorityGet, function + MPU_uxTaskPriorityGet: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_uxTaskPriorityGet, MPU_uxTaskPriorityGetImpl + +#endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */ + +/* ------------------------------------------------------------------------------- */ + +#if ( INCLUDE_eTaskGetState == 1 ) + + .extern MPU_eTaskGetStateImpl + .align 4 + .global MPU_eTaskGetState + .type MPU_eTaskGetState, function + MPU_eTaskGetState: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_eTaskGetState, MPU_eTaskGetStateImpl + +#endif /* if ( INCLUDE_eTaskGetState == 1 ) */ + +/* ------------------------------------------------------------------------------- */ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + .extern MPU_vTaskGetInfoImpl + .align 4 + .global MPU_vTaskGetInfo + .type MPU_vTaskGetInfo, function + MPU_vTaskGetInfo: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_vTaskGetInfo, MPU_vTaskGetInfoImpl + + /* ------------------------------------------------------------------------------- */ + + .extern MPU_uxTaskGetSystemStateImpl + .align 4 + .global MPU_uxTaskGetSystemState + .type MPU_uxTaskGetSystemState, function + MPU_uxTaskGetSystemState: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_uxTaskGetSystemState, MPU_uxTaskGetSystemStateImpl + +#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ + +/* ------------------------------------------------------------------------------- */ + +#if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + .extern MPU_uxEventGroupGetNumberImpl + .align 4 + .global MPU_uxEventGroupGetNumber + .type MPU_uxEventGroupGetNumber, function + MPU_uxEventGroupGetNumber: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_uxEventGroupGetNumber, MPU_uxEventGroupGetNumberImpl + + /* ------------------------------------------------------------------------------- */ + + + + .extern MPU_vEventGroupSetNumberImpl + .align 4 + .global MPU_vEventGroupSetNumber + .type MPU_vEventGroupSetNumber, function + MPU_vEventGroupSetNumber: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_vEventGroupSetNumber, MPU_vEventGroupSetNumberImpl + + /* ------------------------------------------------------------------------------- */ + +#endif /* if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ + +/* ------------------------------------------------------------------------------- */ + +#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) + + .extern MPU_xTaskGetIdleTaskHandleImpl + .align 4 + .global MPU_xTaskGetIdleTaskHandle + .type MPU_xTaskGetIdleTaskHandle, function + MPU_xTaskGetIdleTaskHandle: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTaskGetIdleTaskHandle, MPU_xTaskGetIdleTaskHandleImpl + + +#endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */ + +/* ------------------------------------------------------------------------------- */ + +#if ( INCLUDE_vTaskSuspend == 1 ) + + .extern MPU_vTaskSuspendImpl + .align 4 + .global MPU_vTaskSuspend + .type MPU_vTaskSuspend, function + MPU_vTaskSuspend: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_vTaskSuspend, MPU_vTaskSuspendImpl + + /* ------------------------------------------------------------------------------- */ + + .extern MPU_vTaskResumeImpl + .align 4 + .global MPU_vTaskResume + .type MPU_vTaskResume, function + MPU_vTaskResume: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_vTaskResume, MPU_vTaskResumeImpl + + /* ------------------------------------------------------------------------------- */ + +#endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ + +/* ------------------------------------------------------------------------------- */ + +#if ( configGENERATE_RUN_TIME_STATS == 1 ) + + .extern MPU_ulTaskGetRunTimeCounterImpl + .align 4 + .global MPU_ulTaskGetRunTimeCounter + .type MPU_ulTaskGetRunTimeCounter, function + MPU_ulTaskGetRunTimeCounter: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_ulTaskGetRunTimeCounter, MPU_ulTaskGetRunTimeCounterImpl + + /* ------------------------------------------------------------------------------- */ + + .extern MPU_ulTaskGetRunTimePercentImpl + .align 4 + .global MPU_ulTaskGetRunTimePercent + .type MPU_ulTaskGetRunTimePercent, function + MPU_ulTaskGetRunTimePercent: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_ulTaskGetRunTimePercent, MPU_ulTaskGetRunTimePercentImpl + + /* ------------------------------------------------------------------------------- */ + + #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) + + .extern MPU_ulTaskGetIdleRunTimePercentImpl + .align 4 + .global MPU_ulTaskGetIdleRunTimePercent + .type MPU_ulTaskGetIdleRunTimePercent, function + MPU_ulTaskGetIdleRunTimePercent: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_ulTaskGetIdleRunTimePercent, MPU_ulTaskGetIdleRunTimePercentImpl + + /* --------------------------------------------------------------------------- */ + + .extern MPU_ulTaskGetIdleRunTimeCounterImpl + .align 4 + .global MPU_ulTaskGetIdleRunTimeCounter + .type MPU_ulTaskGetIdleRunTimeCounter, function + MPU_ulTaskGetIdleRunTimeCounter: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter, MPU_ulTaskGetIdleRunTimeCounterImpl + + /* --------------------------------------------------------------------------- */ + + #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */ + +#endif /* if ( configGENERATE_RUN_TIME_STATS == 1 )*/ + +/* --------------------------------------------------------------------------- */ + +#if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + .extern MPU_vTaskSetApplicationTaskTagImpl + .align 4 + .global MPU_vTaskSetApplicationTaskTag + .type MPU_vTaskSetApplicationTaskTag, function + MPU_vTaskSetApplicationTaskTag: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_vTaskSetApplicationTaskTag, MPU_vTaskSetApplicationTaskTagImpl + + /* ------------------------------------------------------------------------------- */ + + .extern MPU_xTaskGetApplicationTaskTagImpl + .align 4 + .global MPU_xTaskGetApplicationTaskTag + .type MPU_xTaskGetApplicationTaskTag, function + MPU_xTaskGetApplicationTaskTag: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTaskGetApplicationTaskTag, MPU_xTaskGetApplicationTaskTagImpl + + /* ------------------------------------------------------------------------------- */ + +#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ + +/* ------------------------------------------------------------------------------- */ + +#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + .extern MPU_vTaskSetThreadLocalStoragePointerImpl + .align 4 + .global MPU_vTaskSetThreadLocalStoragePointer + .type MPU_vTaskSetThreadLocalStoragePointer, function + MPU_vTaskSetThreadLocalStoragePointer: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer, MPU_vTaskSetThreadLocalStoragePointerImpl + + /* ------------------------------------------------------------------------------- */ + + .extern MPU_pvTaskGetThreadLocalStoragePointerImpl + .align 4 + .global MPU_pvTaskGetThreadLocalStoragePointer + .type MPU_pvTaskGetThreadLocalStoragePointer, function + MPU_pvTaskGetThreadLocalStoragePointer: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer, MPU_pvTaskGetThreadLocalStoragePointerImpl + + /* ------------------------------------------------------------------------------- */ + +#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ + +/* ------------------------------------------------------------------------------- */ + +#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) + + .extern MPU_uxTaskGetStackHighWaterMarkImpl + .align 4 + .global MPU_uxTaskGetStackHighWaterMark + .type MPU_uxTaskGetStackHighWaterMark, function + MPU_uxTaskGetStackHighWaterMark: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_uxTaskGetStackHighWaterMark, MPU_uxTaskGetStackHighWaterMarkImpl + +#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */ + +/* ------------------------------------------------------------------------------- */ + +#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) + + .extern MPU_uxTaskGetStackHighWaterMark2Impl + .align 4 + .global MPU_uxTaskGetStackHighWaterMark2 + .type MPU_uxTaskGetStackHighWaterMark2, function + MPU_uxTaskGetStackHighWaterMark2: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_uxTaskGetStackHighWaterMark2, MPU_uxTaskGetStackHighWaterMark2Impl + +#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */ + +/* ------------------------------------------------------------------------------- */ + +#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) + + .extern MPU_xTaskGetCurrentTaskHandleImpl + .align 4 + .global MPU_xTaskGetCurrentTaskHandle + .type MPU_xTaskGetCurrentTaskHandle, function + MPU_xTaskGetCurrentTaskHandle: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTaskGetCurrentTaskHandle, MPU_xTaskGetCurrentTaskHandleImpl + +#endif /* if( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */ + +/* ------------------------------------------------------------------------------- */ + +#if ( INCLUDE_xTaskGetSchedulerState == 1 ) + + .extern MPU_xTaskGetSchedulerStateImpl + .align 4 + .global MPU_xTaskGetSchedulerState + .type MPU_xTaskGetSchedulerState, function + MPU_xTaskGetSchedulerState: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTaskGetSchedulerState, MPU_xTaskGetSchedulerStateImpl + + +#endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */ + +/* ------------------------------------------------------------------------------- */ + +#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) + + .extern MPU_xQueueGetMutexHolderImpl + .align 4 + .global MPU_xQueueGetMutexHolder + .type MPU_xQueueGetMutexHolder, function + MPU_xQueueGetMutexHolder: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_xQueueGetMutexHolder, MPU_xQueueGetMutexHolderImpl + +#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */ + +/* ------------------------------------------------------------------------------- */ + +#if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + .extern MPU_xQueueTakeMutexRecursiveImpl + .align 4 + .global MPU_xQueueTakeMutexRecursive + .type MPU_xQueueTakeMutexRecursive, function + MPU_xQueueTakeMutexRecursive: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_xQueueTakeMutexRecursive, MPU_xQueueTakeMutexRecursiveImpl + + /* ------------------------------------------------------------------------------- */ + + .extern MPU_xQueueGiveMutexRecursiveImpl + .align 4 + .global MPU_xQueueGiveMutexRecursive + .type MPU_xQueueGiveMutexRecursive, function + MPU_xQueueGiveMutexRecursive: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_xQueueGiveMutexRecursive, MPU_xQueueGiveMutexRecursiveImpl + + /* ------------------------------------------------------------------------------- */ + +#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ + +/* ------------------------------------------------------------------------------- */ + +#if ( configUSE_QUEUE_SETS == 1 ) + + .extern MPU_xQueueSelectFromSetImpl + .align 4 + .global MPU_xQueueSelectFromSet + .type MPU_xQueueSelectFromSet, function + MPU_xQueueSelectFromSet: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_xQueueSelectFromSet, MPU_xQueueSelectFromSetImpl + + /* ------------------------------------------------------------------------------- */ + + .extern MPU_xQueueAddToSetImpl + .align 4 + .global MPU_xQueueAddToSet + .type MPU_xQueueAddToSet, function + MPU_xQueueAddToSet: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_xQueueAddToSet, MPU_xQueueAddToSetImpl + + /* ------------------------------------------------------------------------------- */ + +#endif /* if ( configUSE_QUEUE_SETS == 1 ) */ + +/* ------------------------------------------------------------------------------- */ + +#if ( configQUEUE_REGISTRY_SIZE > 0 ) + + .extern MPU_vQueueAddToRegistryImpl + .align 4 + .global MPU_vQueueAddToRegistry + .type MPU_vQueueAddToRegistry, function + MPU_vQueueAddToRegistry: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_vQueueAddToRegistry, MPU_vQueueAddToRegistryImpl + + /* ------------------------------------------------------------------------------- */ + + .extern MPU_vQueueUnregisterQueueImpl + .align 4 + .global MPU_vQueueUnregisterQueue + .type MPU_vQueueUnregisterQueue, function + MPU_vQueueUnregisterQueue: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_vQueueUnregisterQueue, MPU_vQueueUnregisterQueueImpl + + /* ------------------------------------------------------------------------------- */ + + .extern MPU_pcQueueGetNameImpl + .align 4 + .global MPU_pcQueueGetName + .type MPU_pcQueueGetName, function + MPU_pcQueueGetName: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_pcQueueGetName, MPU_pcQueueGetNameImpl + + /* ------------------------------------------------------------------------------- */ + +#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ + +/* ------------------------------------------------------------------------------- */ + +#if ( configUSE_TIMERS == 1 ) + + .extern MPU_pvTimerGetTimerIDImpl + .align 4 + .global MPU_pvTimerGetTimerID + .type MPU_pvTimerGetTimerID, function + MPU_pvTimerGetTimerID: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_pvTimerGetTimerID, MPU_pvTimerGetTimerIDImpl + + /* ------------------------------------------------------------------------------- */ + + .extern MPU_vTimerSetTimerIDImpl + .align 4 + .global MPU_vTimerSetTimerID + .type MPU_vTimerSetTimerID, function + MPU_vTimerSetTimerID: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_vTimerSetTimerID, MPU_vTimerSetTimerIDImpl + + /* ------------------------------------------------------------------------------- */ + + .extern MPU_xTimerIsTimerActiveImpl + .align 4 + .global MPU_xTimerIsTimerActive + .type MPU_xTimerIsTimerActive, function + MPU_xTimerIsTimerActive: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTimerIsTimerActive, MPU_xTimerIsTimerActiveImpl + + /* ------------------------------------------------------------------------------- */ + + .extern MPU_xTimerGetTimerDaemonTaskHandleImpl + .align 4 + .global MPU_xTimerGetTimerDaemonTaskHandle + .type MPU_xTimerGetTimerDaemonTaskHandle, function + MPU_xTimerGetTimerDaemonTaskHandle: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle, MPU_xTimerGetTimerDaemonTaskHandleImpl + + /* ------------------------------------------------------------------------------- */ + + .extern MPU_xTimerGenericCommandFromTaskImpl + .align 4 + .global MPU_xTimerGenericCommandFromTaskEntry + .type MPU_xTimerGenericCommandFromTaskEntry, function + MPU_xTimerGenericCommandFromTaskEntry: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTimerGenericCommandFromTask, MPU_xTimerGenericCommandFromTaskImpl + + /* ------------------------------------------------------------------------------- */ + + .extern MPU_pcTimerGetNameImpl + .align 4 + .global MPU_pcTimerGetName + .type MPU_pcTimerGetName, function + MPU_pcTimerGetName: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_pcTimerGetName, MPU_pcTimerGetNameImpl + + /* ------------------------------------------------------------------------------- */ + + .extern MPU_vTimerSetReloadModeImpl + .align 4 + .global MPU_vTimerSetReloadMode + .type MPU_vTimerSetReloadMode, function + MPU_vTimerSetReloadMode: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_vTimerSetReloadMode, MPU_vTimerSetReloadModeImpl + + /* ------------------------------------------------------------------------------- */ + + .extern MPU_xTimerGetReloadModeImpl + .align 4 + .global MPU_xTimerGetReloadMode + .type MPU_xTimerGetReloadMode, function + MPU_xTimerGetReloadMode: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTimerGetReloadMode, MPU_xTimerGetReloadModeImpl + + /* ------------------------------------------------------------------------------- */ + + .extern MPU_uxTimerGetReloadModeImpl + .align 4 + .global MPU_uxTimerGetReloadMode + .type MPU_uxTimerGetReloadMode, function + MPU_uxTimerGetReloadMode: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_uxTimerGetReloadMode, MPU_uxTimerGetReloadModeImpl + + /* ------------------------------------------------------------------------------- */ + + .extern MPU_xTimerGetPeriodImpl + .align 4 + .global MPU_xTimerGetPeriod + .type MPU_xTimerGetPeriod, function + MPU_xTimerGetPeriod: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTimerGetPeriod, MPU_xTimerGetPeriodImpl + + /* ------------------------------------------------------------------------------- */ + + .extern MPU_xTimerGetExpiryTimeImpl + .align 4 + .global MPU_xTimerGetExpiryTime + .type MPU_xTimerGetExpiryTime, function + MPU_xTimerGetExpiryTime: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTimerGetExpiryTime, MPU_xTimerGetExpiryTimeImpl + + /* ------------------------------------------------------------------------------- */ + +#endif /* if ( configUSE_TIMERS == 1 ) */ + +/* ------------------------------------------------------------------------------- */ + +#if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + .extern MPU_xTaskGenericNotifyImpl + .align 4 + .global MPU_xTaskGenericNotifyEntry + .type MPU_xTaskGenericNotifyEntry, function + MPU_xTaskGenericNotifyEntry: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTaskGenericNotify, MPU_xTaskGenericNotifyImpl + + /* ------------------------------------------------------------------------------- */ + + .extern MPU_xTaskGenericNotifyWaitImpl + .align 4 + .global MPU_xTaskGenericNotifyWaitEntry + .type MPU_xTaskGenericNotifyWaitEntry, function + MPU_xTaskGenericNotifyWaitEntry: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTaskGenericNotifyWait, MPU_xTaskGenericNotifyWaitImpl + + /* ------------------------------------------------------------------------------- */ + + .extern MPU_ulTaskGenericNotifyTakeImpl + .align 4 + .global MPU_ulTaskGenericNotifyTake + .type MPU_ulTaskGenericNotifyTake, function + MPU_ulTaskGenericNotifyTake: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_ulTaskGenericNotifyTake, MPU_ulTaskGenericNotifyTakeImpl + + /* ------------------------------------------------------------------------------- */ + + .extern MPU_xTaskGenericNotifyStateClearImpl + .align 4 + .global MPU_xTaskGenericNotifyStateClear + .type MPU_xTaskGenericNotifyStateClear, function + MPU_xTaskGenericNotifyStateClear: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTaskGenericNotifyStateClear, MPU_xTaskGenericNotifyStateClearImpl + + /* ------------------------------------------------------------------------------- */ + + .extern MPU_ulTaskGenericNotifyValueClearImpl + .align 4 + .global MPU_ulTaskGenericNotifyValueClear + .type MPU_ulTaskGenericNotifyValueClear, function + MPU_ulTaskGenericNotifyValueClear: + INVOKE_SYSTEM_CALL #SYSTEM_CALL_ulTaskGenericNotifyValueClear, MPU_ulTaskGenericNotifyValueClearImpl + + /* ------------------------------------------------------------------------------- */ + +#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ + +/* ------------------------------------------------------------------------------- */ + +.end diff --git a/portable/GCC/ARM_CRx_MPU/port.c b/portable/GCC/ARM_CRx_MPU/port.c new file mode 100644 index 000000000..56ff38384 --- /dev/null +++ b/portable/GCC/ARM_CRx_MPU/port.c @@ -0,0 +1,845 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#ifndef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE +#endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "portmacro.h" +#include "task.h" +#include "mpu_syscall_numbers.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Max value that fits in a uint32_t type. */ +#define portUINT32_MAX ( ~( ( uint32_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) ) +/* ----------------------------------------------------------------------------------- */ + +/** + * @brief Variable used to keep track of critical section nesting. + * + * @ingroup Critical Sections + * + * This variable is stored as part of the task context and must be initialised + * to a non zero value to ensure interrupts don't inadvertently become unmasked + * before the scheduler starts. As it is stored as part of the task context, it + * will be set to 0 when the first task is started. + */ +PRIVILEGED_DATA volatile UBaseType_t ulCriticalNesting = 0xFFFF; + +/** + * @brief Set to 1 to pend a context switch from an ISR. + * + * @ingroup Interrupt Management + */ +PRIVILEGED_DATA volatile UBaseType_t ulPortYieldRequired = pdFALSE; + +/** + * @brief Interrupt nesting depth, used to count the number of interrupts to unwind. + * + * @ingroup Interrupt Management + */ +PRIVILEGED_DATA volatile UBaseType_t ulPortInterruptNesting = 0UL; + +/** + * @brief Variable to track whether or not the scheduler has been started. + * + * @ingroup Scheduler + * + * This is the port specific version of the xSchedulerRunning in tasks.c. + */ +PRIVILEGED_DATA static BaseType_t prvPortSchedulerRunning = pdFALSE; + +/* -------------------------- Private Function Declarations -------------------------- */ + +/** + * @brief Determine if the given MPU region settings authorizes the requested + * access to the given buffer. + * + * @ingroup Task Context + * @ingroup MPU Control + * + * @param xTaskMPURegion MPU region settings. + * @param ulBufferStart Start address of the given buffer. + * @param ulBufferLength Length of the given buffer. + * @param ulAccessRequested Access requested. + * + * @return pdTRUE if MPU region settings authorizes the requested access to the + * given buffer, pdFALSE otherwise. + */ +PRIVILEGED_FUNCTION static BaseType_t prvMPURegionAuthorizesBuffer( const xMPU_REGION_REGISTERS * xTaskMPURegion, + const uint32_t ulBufferStart, + const uint32_t ulBufferLength, + const uint32_t ulAccessRequested ); + +/** + * @brief Determine the smallest MPU Region Size Encoding for the given MPU + * region size. + * + * @ingroup MPU Control + * + * @param ulActualMPURegionSize MPU region size in bytes. + * + * @return The smallest MPU Region Size Encoding for the given MPU region size. + */ +PRIVILEGED_FUNCTION static uint32_t prvGetMPURegionSizeEncoding( uint32_t ulActualMPURegionSize ); + +/** + * @brief Set up MPU. + * + * @ingroup MPU Control + */ +PRIVILEGED_FUNCTION static void prvSetupMPU( void ); + +/* -------------------------- Exported Function Declarations -------------------------- */ + +/** + * @brief Enter critical section. + * + * @ingroup Critical Section + */ +PRIVILEGED_FUNCTION void vPortEnterCritical( void ); + +/** + * @brief Exit critical section. + * + * @ingroup Critical Section + */ +PRIVILEGED_FUNCTION void vPortExitCritical( void ); + +/* ----------------------------------------------------------------------------------- */ + +/** + * @brief Setup a FreeRTOS task's initial context. + * + * @ingroup Task Context + * + * @param pxTopOfStack Top of stack. + * @param pxCode The task function. + * @param pvParameters Argument passed to the task function. + * @param xRunPrivileged Marks if the task is privileged. + * @param xMPUSettings MPU settings of the task. + * + * @return Location where to restore the task's context from. + */ +/* PRIVILEGED_FUNCTION */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged, + xMPU_SETTINGS * xMPUSettings ) +{ + /* Setup the initial context of the task. The context is set exactly as + * expected by the portRESTORE_CONTEXT() macro. */ + UBaseType_t ulIndex = CONTEXT_SIZE - 1U; + + xSYSTEM_CALL_STACK_INFO * xSysCallInfo = NULL; + + if( xRunPrivileged == pdTRUE ) + { + xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; + /* Current Program Status Register (CPSR). */ + xMPUSettings->ulContext[ ulIndex ] = SYS_MODE; + } + else + { + xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG ); + /* Current Program Status Register (CPSR). */ + xMPUSettings->ulContext[ ulIndex ] = USER_MODE; + } + + if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x0UL ) + { + /* The task will cause the processor to start in THUMB state, set the + * Thumb state bit in the CPSR. */ + xMPUSettings->ulContext[ ulIndex ] |= portTHUMB_MODE_BIT; + } + + ulIndex--; + + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) pxCode; /* PC. */ + ulIndex--; + + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + ulIndex--; + + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) pxTopOfStack; /* SP. */ + ulIndex--; + + /* General Purpose Registers. */ + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0x12121212; /* R12. */ + ulIndex--; + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0x11111111; /* R11. */ + ulIndex--; + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0x10101010; /* R10. */ + ulIndex--; + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0x09090909; /* R9. */ + ulIndex--; + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0x08080808; /* R8. */ + ulIndex--; + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0x07070707; /* R7. */ + ulIndex--; + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0x06060606; /* R6. */ + ulIndex--; + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0x05050505; /* R5. */ + ulIndex--; + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0x04040404; /* R4. */ + ulIndex--; + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0x03030303; /* R3. */ + ulIndex--; + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0x02020202; /* R2. */ + ulIndex--; + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0x01010101; /* R1. */ + ulIndex--; + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) pvParameters; /* R0. */ + ulIndex--; + + #if( portENABLE_FPU == 1 ) + { + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD0000015; /* S31. */ + ulIndex--; + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD1500000; /* S30. */ + ulIndex--; + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD0000014; /* S29. */ + ulIndex--; + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD1400000; /* S28. */ + ulIndex--; + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD0000013; /* S27. */ + ulIndex--; + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD1300000; /* S26. */ + ulIndex--; + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD0000012; /* S25. */ + ulIndex--; + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD1200000; /* S24. */ + ulIndex--; + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD0000011; /* S23. */ + ulIndex--; + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD1100000; /* S22. */ + ulIndex--; + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD0000010; /* S21. */ + ulIndex--; + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD1000000; /* S20. */ + ulIndex--; + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD0000009; /* S19. */ + ulIndex--; + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD9000000; /* S18. */ + ulIndex--; + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD0000008; /* S17. */ + ulIndex--; + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD8000000; /* S16. */ + ulIndex--; + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD0000007; /* S15. */ + ulIndex--; + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD7000000; /* S14. */ + ulIndex--; + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD0000006; /* S13. */ + ulIndex--; + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD6000000; /* S12. */ + ulIndex--; + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD0000005; /* S11. */ + ulIndex--; + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD5000000; /* S10. */ + ulIndex--; + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD0000004; /* S9. */ + ulIndex--; + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD4000000; /* S8. */ + ulIndex--; + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD0000003; /* S7. */ + ulIndex--; + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD3000000; /* S6. */ + ulIndex--; + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD0000002; /* S5. */ + ulIndex--; + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD2000000; /* S4. */ + ulIndex--; + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD0000001; /* S3. */ + ulIndex--; + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD1000000; /* S2. */ + ulIndex--; + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD0000000; /* S1. */ + ulIndex--; + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0xD0000000; /* S0. */ + ulIndex--; + + xMPUSettings->ulContext[ ulIndex ] = ( StackType_t ) 0x00000000; /* FPSR. */ + ulIndex--; + } + #endif /* portENABLE_FPU */ + + /* The task will start with a critical nesting count of 0. */ + xMPUSettings->ulContext[ ulIndex ] = portNO_CRITICAL_NESTING; + + /* Ensure that the system call stack is double word aligned. */ + xSysCallInfo = &( xMPUSettings->xSystemCallStackInfo ); + xSysCallInfo->pulSystemCallStackPointer = &( xSysCallInfo->ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1U ] ); + xSysCallInfo->pulSystemCallStackPointer = ( uint32_t * ) ( ( ( uint32_t ) ( xSysCallInfo->pulSystemCallStackPointer ) ) & + ( ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ) ); + + /* This is not NULL only for the duration of a system call. */ + xSysCallInfo->pulTaskStackPointer = NULL; + + /* Set the System Call to return to vPortSystemCallExit. */ + xSysCallInfo->pulSystemCallExitAddress = ( uint32_t * ) ( &vPortSystemCallExit ); + + /* Return the address where this task's context should be restored from. */ + return &( xMPUSettings->ulContext[ ulIndex ] ); +} + +/* ----------------------------------------------------------------------------------- */ + +/** + * @brief Store a FreeRTOS task's MPU settings in its TCB. + * + * @ingroup Task Context + * @ingroup MPU Control + * + * @param xMPUSettings The MPU settings in TCB. + * @param xRegions The updated MPU settings requested by the task. + * @param pxBottomOfStack The base address of the task's Stack. + * @param ulStackDepth The length of the task's stack. + */ +/* PRIVILEGED_FUNCTION */ +void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + uint32_t ulStackDepth ) +{ + #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __SRAM_segment_start__; + extern uint32_t * __SRAM_segment_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __SRAM_segment_start__[]; + extern uint32_t __SRAM_segment_end__[]; + #endif /* if defined( __ARMCC_VERSION ) */ + + uint32_t ulIndex = 0x0; + uint32_t ulRegionLength; + uint32_t ulRegionLengthEncoded; + uint32_t ulRegionLengthDecoded; + + if( xRegions == NULL ) + { + /* No MPU regions are specified so allow access to all of the RAM. */ + ulRegionLength = ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__; + ulRegionLengthEncoded = prvGetMPURegionSizeEncoding( ulRegionLength ); + ulRegionLength |= portMPU_REGION_ENABLE; + + /* MPU Settings is zero'd out in the TCB before this function is called. + * We, therefore, do not need to explicitly zero out unused MPU regions + * in xMPUSettings. */ + ulIndex = portSTACK_REGION; + + xMPUSettings->xRegion[ ulIndex ].ulRegionBaseAddress = ( uint32_t ) __SRAM_segment_start__; + xMPUSettings->xRegion[ ulIndex ].ulRegionSize = ( ulRegionLengthEncoded | + portMPU_REGION_ENABLE ); + xMPUSettings->xRegion[ ulIndex ].ulRegionAttribute = ( portMPU_REGION_PRIV_RW_USER_RW_NOEXEC | + portMPU_REGION_NORMAL_OIWTNOWA_SHARED ); + } + else + { + for( ulIndex = 0UL; ulIndex < portNUM_CONFIGURABLE_REGIONS; ulIndex++ ) + { + /* If a length has been provided, the region is in use. */ + if( ( xRegions[ ulIndex ] ).ulLengthInBytes > 0UL ) + { + ulRegionLength = xRegions[ ulIndex ].ulLengthInBytes; + ulRegionLengthEncoded = prvGetMPURegionSizeEncoding( ulRegionLength ); + + /* MPU region base address must be aligned to the region size + * boundary. */ + ulRegionLengthDecoded = 2UL << ( ulRegionLengthEncoded >> 1UL ); + configASSERT( ( ( ( uint32_t ) xRegions[ ulIndex ].pvBaseAddress ) % ( ulRegionLengthDecoded ) ) == 0UL ); + + xMPUSettings->xRegion[ ulIndex ].ulRegionBaseAddress = ( uint32_t ) xRegions[ ulIndex ].pvBaseAddress; + xMPUSettings->xRegion[ ulIndex ].ulRegionSize = ( ulRegionLengthEncoded | + portMPU_REGION_ENABLE ); + xMPUSettings->xRegion[ ulIndex ].ulRegionAttribute = xRegions[ ulIndex ].ulParameters; + } + else + { + xMPUSettings->xRegion[ ulIndex ].ulRegionBaseAddress = 0x0UL; + xMPUSettings->xRegion[ ulIndex ].ulRegionSize = 0x0UL; + xMPUSettings->xRegion[ ulIndex ].ulRegionAttribute = 0x0UL; + } + } + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that the + * stack region has already been configured. */ + if( ulStackDepth != 0x0UL ) + { + ulRegionLengthEncoded = prvGetMPURegionSizeEncoding( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ); + + /* MPU region base address must be aligned to the region size + * boundary. */ + ulRegionLengthDecoded = 2UL << ( ulRegionLengthEncoded >> 1UL ); + configASSERT( ( ( uint32_t ) pxBottomOfStack % ( ulRegionLengthDecoded ) ) == 0U ); + + ulIndex = portSTACK_REGION; + xMPUSettings->xRegion[ ulIndex ].ulRegionBaseAddress = ( uint32_t ) pxBottomOfStack; + xMPUSettings->xRegion[ ulIndex ].ulRegionSize = ( ulRegionLengthEncoded | + portMPU_REGION_ENABLE ); + xMPUSettings->xRegion[ ulIndex ].ulRegionAttribute = ( portMPU_REGION_PRIV_RW_USER_RW_NOEXEC | + portMPU_REGION_NORMAL_OIWTNOWA_SHARED ); + } + } +} + +/* ----------------------------------------------------------------------------------- */ + +/* PRIVILEGED_FUNCTION */ +BaseType_t xPortIsTaskPrivileged( void ) +{ + BaseType_t xTaskIsPrivileged = pdFALSE; + + /* Calling task's MPU settings. */ + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xTaskIsPrivileged = pdTRUE; + } + + return xTaskIsPrivileged; +} + +/* ----------------------------------------------------------------------------------- */ + +/* PRIVILEGED_FUNCTION */ +BaseType_t xPortStartScheduler( void ) +{ + /* Start the timer that generates the tick ISR. */ + configSETUP_TICK_INTERRUPT(); + + /* Configure MPU regions that are common to all tasks. */ + prvSetupMPU(); + + prvPortSchedulerRunning = pdTRUE; + + /* Load the context of the first task. */ + vPortStartFirstTask(); + + /* Will only get here if vTaskStartScheduler() was called with the CPU in + * a non-privileged mode or the binary point register was not set to its lowest + * possible value. prvTaskExitError() is referenced to prevent a compiler + * warning about it being defined but not referenced in the case that the user + * defines their own exit address. */ + ( void ) prvTaskExitError(); + return pdFALSE; +} + +/* ----------------------------------------------------------------------------------- */ + +/* PRIVILEGED_FUNCTION */ +static uint32_t prvGetMPURegionSizeEncoding( uint32_t ulActualMPURegionSize ) +{ + uint32_t ulRegionSize, ulReturnValue = 4U; + + /* 32 bytes is the smallest valid region for Cortex R4 and R5 CPUs. */ + for( ulRegionSize = 0x20UL; ulReturnValue < 0x1FUL; ( ulRegionSize <<= 1UL ) ) + { + if( ulActualMPURegionSize <= ulRegionSize ) + { + break; + } + else + { + ulReturnValue++; + } + } + + /* Shift the code by one before returning so it can be written directly + * into the the correct bit position of the attribute register. */ + return ulReturnValue << 1UL; +} + +/* ----------------------------------------------------------------------------------- */ + +/* PRIVILEGED_FUNCTION */ +static void prvSetupMPU( void ) +{ +#if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code. */ + /* Sections used for FLASH. */ + extern uint32_t * __FLASH_segment_start__; + extern uint32_t * __FLASH_segment_end__; + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + + /* Sections used for RAM. */ + extern uint32_t * __SRAM_segment_start__; + extern uint32_t * __SRAM_segment_end__; + extern uint32_t * __privileged_data_start__; + extern uint32_t * __privileged_data_end__; +#else + /* Declaration when these variable are exported from linker scripts. */ + /* Sections used for FLASH. */ + extern uint32_t __FLASH_segment_start__[]; + extern uint32_t __FLASH_segment_end__[]; + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + + /* Sections used for RAM. */ + extern uint32_t __SRAM_segment_start__[]; + extern uint32_t __SRAM_segment_end__[]; + extern uint32_t __privileged_data_start__[]; + extern uint32_t __privileged_data_end__[]; +#endif /* if defined( __ARMCC_VERSION ) */ + + uint32_t ulRegionLength; + uint32_t ulRegionLengthEncoded; + + /* Disable the MPU before programming it. */ + vMPUDisable(); + + /* Priv: RX, Unpriv: RX for entire Flash. */ + ulRegionLength = ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__; + ulRegionLengthEncoded = prvGetMPURegionSizeEncoding( ulRegionLength ); + vMPUSetRegion( portUNPRIVILEGED_FLASH_REGION, + ( uint32_t ) __FLASH_segment_start__, + ( ulRegionLengthEncoded | portMPU_REGION_ENABLE ), + ( portMPU_REGION_PRIV_RO_USER_RO_EXEC | + portMPU_REGION_NORMAL_OIWTNOWA_SHARED ) ); + + /* Priv: RX, Unpriv: No access for privileged functions. */ + ulRegionLength = ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __privileged_functions_start__; + ulRegionLengthEncoded = prvGetMPURegionSizeEncoding( ulRegionLength ); + vMPUSetRegion( portPRIVILEGED_FLASH_REGION, + ( uint32_t ) __privileged_functions_start__, + ( ulRegionLengthEncoded | portMPU_REGION_ENABLE ), + ( portMPU_REGION_PRIV_RO_USER_NA_EXEC | + portMPU_REGION_NORMAL_OIWTNOWA_SHARED ) ); + + /* Priv: RW, Unpriv: No Access for privileged data. */ + ulRegionLength = ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__; + ulRegionLengthEncoded = prvGetMPURegionSizeEncoding( ulRegionLength ); + vMPUSetRegion( portPRIVILEGED_RAM_REGION, + ( uint32_t ) __privileged_data_start__, + ( ulRegionLengthEncoded | portMPU_REGION_ENABLE ), + ( portMPU_REGION_PRIV_RW_USER_NA_NOEXEC | + portMPU_REGION_PRIV_RW_USER_NA_NOEXEC ) ); + + /* Enable the MPU background region - it allows privileged operating modes + * access to unmapped regions of memory without generating a fault. */ + vMPUEnableBackgroundRegion(); + + /* After setting default regions, enable the MPU. */ + vMPUEnable(); +} + +/* ----------------------------------------------------------------------------------- */ + +/* PRIVILEGED_FUNCTION */ +static BaseType_t prvMPURegionAuthorizesBuffer( const xMPU_REGION_REGISTERS * xTaskMPURegion, + const uint32_t ulBufferStart, + const uint32_t ulBufferLength, + const uint32_t ulAccessRequested ) +{ + BaseType_t xAccessGranted = pdFALSE; + uint32_t ulBufferEnd; + uint32_t ulMPURegionLength; + uint32_t ulMPURegionStart; + uint32_t ulMPURegionEnd; + uint32_t ulMPURegionAccessPermissions; + + if( portADD_UINT32_WILL_OVERFLOW( ulBufferStart, ( ulBufferLength - 1UL ) ) == pdFALSE ) + { + ulBufferEnd = ulBufferStart + ulBufferLength - 1UL; + ulMPURegionLength = 2UL << ( xTaskMPURegion->ulRegionSize >> 1UL ); + ulMPURegionStart = xTaskMPURegion->ulRegionBaseAddress; + ulMPURegionEnd = xTaskMPURegion->ulRegionBaseAddress + ulMPURegionLength - 1UL; + + if( ( ulBufferStart >= ulMPURegionStart ) && + ( ulBufferEnd <= ulMPURegionEnd ) && + ( ulBufferStart <= ulBufferEnd ) ) + { + ulMPURegionAccessPermissions = xTaskMPURegion->ulRegionAttribute & portMPU_REGION_AP_BITMASK; + + if( ulAccessRequested == tskMPU_READ_PERMISSION ) /* RO. */ + { + if( ( ulMPURegionAccessPermissions == portMPU_REGION_PRIV_RW_USER_RO ) || + ( ulMPURegionAccessPermissions == portMPU_REGION_PRIV_RO_USER_RO ) || + ( ulMPURegionAccessPermissions == portMPU_REGION_PRIV_RW_USER_RW ) ) + + { + xAccessGranted = pdTRUE; + } + } + else if( ( ulAccessRequested & tskMPU_WRITE_PERMISSION ) != 0UL ) /* W or RW. */ + { + if( ulMPURegionAccessPermissions == portMPU_REGION_PRIV_RW_USER_RW ) + { + xAccessGranted = pdTRUE; + } + } + } + } + + return xAccessGranted; +} + +/* ----------------------------------------------------------------------------------- */ + +/* PRIVILEGED_FUNCTION */ +BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, + uint32_t ulBufferLength, + uint32_t ulAccessRequested ) +{ + BaseType_t xAccessGranted = pdFALSE; + uint32_t ulRegionIndex; + xMPU_SETTINGS * xTaskMPUSettings = NULL; + + if( prvPortSchedulerRunning == pdFALSE ) + { + /* Grant access to all the memory before the scheduler is started. It is + * necessary because there is no task running yet and therefore, we + * cannot use the permissions of any task. */ + xAccessGranted = pdTRUE; + } + else + { + /* Calling task's MPU settings. */ + xTaskMPUSettings = xTaskGetMPUSettings( NULL ); + + if( ( xTaskMPUSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + /* Privileged tasks have access to all the memory. */ + xAccessGranted = pdTRUE; + } + else + { + for( ulRegionIndex = 0x0UL; ulRegionIndex < portTOTAL_NUM_REGIONS_IN_TCB; ulRegionIndex++ ) + { + xAccessGranted = prvMPURegionAuthorizesBuffer( &( xTaskMPUSettings->xRegion[ ulRegionIndex ] ), + ( uint32_t ) pvBuffer, + ulBufferLength, + ulAccessRequested ); + + if( xAccessGranted == pdTRUE ) + { + break; + } + } + } + } + + return xAccessGranted; +} + +/* ----------------------------------------------------------------------------------- */ + +#if( configENABLE_ACCESS_CONTROL_LIST == 1 ) + +/* PRIVILEGED_FUNCTION */ +BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) +{ + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings; + + if( prvPortSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else + { + /* Calling task's MPU settings. */ + xTaskMpuSettings = xTaskGetMPUSettings( NULL ); + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject + / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject + % portACL_ENTRY_SIZE_BITS ); + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( ( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] ) & + ( 1U << ulAccessControlListEntryBit ) ) != 0UL ) + { + xAccessGranted = pdTRUE; + } + } + } + + return xAccessGranted; +} + +#else + +/* PRIVILEGED_FUNCTION */ +BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) +{ + ( void ) lInternalIndexOfKernelObject; + + /* If Access Control List feature is not used, all the tasks have + * access to all the kernel objects. */ + return pdTRUE; +} + +#endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + +/* ----------------------------------------------------------------------------------- */ + +#if( configENABLE_ACCESS_CONTROL_LIST == 1 ) + +/* PRIVILEGED_FUNCTION */ +void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) +{ + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject + / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject + % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit ); +} + +#endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + +/* ----------------------------------------------------------------------------------- */ + +#if( configENABLE_ACCESS_CONTROL_LIST == 1 ) + +/* PRIVILEGED_FUNCTION */ +void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) +{ + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject + / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject + % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit ); +} + +#endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + +/* ----------------------------------------------------------------------------------- */ + +void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ + configASSERT( ulPortInterruptNesting == ~0UL ); + + for( ;; ) + { + } +} + +/* ----------------------------------------------------------------------------------- */ + +void vPortEndScheduler( void ) +{ + prvPortSchedulerRunning = pdFALSE; + + /* Not implemented in this port. Artificially force an assert. */ + configASSERT( prvPortSchedulerRunning == pdTRUE ); +} + +/* ----------------------------------------------------------------------------------- */ + +/* PRIVILEGED_FUNCTION */ +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + + /* Now that interrupts are disabled, ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert + * if the critical nesting count is 1 to protect against recursive calls if + * the assert function also uses a critical section. */ + if( ulCriticalNesting == 1 ) + { + configASSERT( ulPortInterruptNesting == 0 ); + } +} +/* ----------------------------------------------------------------------------------- */ + +/* PRIVILEGED_FUNCTION */ +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as the critical section is being + * exited. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then all interrupt + * priorities must be re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Critical nesting has reached zero so all interrupt priorities + * should be unmasked. */ + portENABLE_INTERRUPTS(); + } + } +} +/* ----------------------------------------------------------------------------------- */ diff --git a/portable/GCC/ARM_CRx_MPU/portASM.S b/portable/GCC/ARM_CRx_MPU/portASM.S new file mode 100644 index 000000000..2b6f22ef2 --- /dev/null +++ b/portable/GCC/ARM_CRx_MPU/portASM.S @@ -0,0 +1,498 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + .arm + .syntax unified + .section privileged_functions, "ax" + +#define FREERTOS_ASSEMBLY + #include "portmacro_asm.h" + #include "mpu_syscall_numbers.h" +#undef FREERTOS_ASSEMBLY + + /* External FreeRTOS-Kernel variables. */ + .extern pxCurrentTCB + .extern uxSystemCallImplementations + .extern ulPortInterruptNesting + .extern ulPortYieldRequired + + /* External Llnker script variables. */ + .extern __syscalls_flash_start__ + .extern __syscalls_flash_end__ + + /* External FreeRTOS-Kernel functions. */ + .extern vTaskSwitchContext + .extern vApplicationIRQHandler + +/* ----------------------------------------------------------------------------------- */ + +/* Save the context of a FreeRTOS Task. */ +.macro portSAVE_CONTEXT + DSB + ISB + /* Push R0 and LR to the stack for current mode. */ + PUSH { R0, LR } + + LDR LR, =pxCurrentTCB /* LR = &( pxCurrentTCB ). */ + LDR LR, [LR] /* LR = pxCurrentTCB. */ + LDR LR, [LR] /* LR = pxTopOfStack i.e. the address where to store the task context. */ + + LDR R0, =ulCriticalNesting /* R0 = &( ulCriticalNesting ). */ + LDR R0, [R0] /* R0 = ulCriticalNesting. */ + STM LR!, { R0 } /* Store ulCriticalNesting. ! increments LR after storing. */ + +#if ( portENABLE_FPU == 1 ) + VMRS R0, FPSCR /* R0 = FPSCR. */ + STM LR!, { R0 } /* Store FPSCR. */ + VSTM LR!, { D0-D15 } /* Store D0-D15. */ +#endif /* ( portENABLE_FPU == 1 ) */ + + POP { R0 } /* Restore R0 to pre-exception value. */ + /* STM (user registers) - In a PL1 mode other than System mode, STM (user + * registers) instruction stores multiple User mode registers to + * consecutive memory locations using an address from a base register. The + * processor reads the base register value normally, using the current mode + * to determine the correct Banked version of the register. This instruction + * cannot writeback to the base register. + * + * The following can be derived from the above description: + * - The macro portSAVE_CONTEXT MUST be called from a PL1 mode other than + * the System mode. + * - Base register LR of the current mode will be used which contains the + * location to store the context. + * - It will store R0-R14 of User mode i.e. pre-exception SP(R13) and LR(R14) + * will be stored. */ + STM LR, { R0-R14 }^ + ADD LR, LR, #60 /* R0-R14 - Total 155 register, each 4 byte wide. */ + + POP { R0 } /* Pre-exception PC is in R0. */ + MRS R1, SPSR /* R1 = Pre-exception CPSR. */ + STM LR!, { R0-R1 } /* Store pre-exception PC and CPSR. */ + +.endm + +/* ----------------------------------------------------------------------------------- */ + +/* Restore the context of a FreeRTOS Task. */ +.macro portRESTORE_CONTEXT + /* Load the pointer to the current task's Task Control Block (TCB). */ + LDR LR, =pxCurrentTCB /* LR = &( pxCurrentTCB ). */ + LDR LR, [LR] /* LR = pxCurrentTCB. */ + ADD R1, LR, #0x4 /* R1 now points to the xMPUSettings in TCB. */ + LDR LR, [LR] /* LR = pxTopOfStack i.e. the address where to restore the task context from. */ + + /* When creating a loop label in a macro it has to be a numeric label. + * for( R5 = portFIRST_CONFIGURABLE_REGION ; R5 <= portNUM_CONFIGURABLE_REGIONS ; R5++ ) */ + MOV R5, #portFIRST_CONFIGURABLE_REGION + 123: + LDMIA R1!, { R2-R4 } /* R2 = ulRegionSize, R3 = ulRegionAttribute, R4 = ulRegionBaseAddress. */ + + MCR p15, #0, R5, c6, c2, #0 /* MPU Region Number Register. */ + MCR p15, #0, R4, c6, c1, #0 /* MPU Region Base Address Register. */ + MCR p15, #0, R3, c6, c1, #4 /* MPU Region Access Control Register. */ + MCR p15, #0, R2, c6, c1, #2 /* MPU Region Size and Enable Register. */ + + ADD R5, R5, #1 + CMP R5, #portNUM_CONFIGURABLE_REGIONS + BLE 123b + + LDR R1, =ulCriticalNesting /* R1 = &( ulCriticalNesting ). */ + LDM LR!, { R2 } /* R2 = Stored ulCriticalNesting. */ + STR R2, [R1] /* Restore ulCriticalNesting. */ + +#if ( portENABLE_FPU == 1 ) + LDM LR!, { R1 } /* R1 = Stored FPSCR. */ + VMSR FPSCR, R1 /* Restore FPSCR. */ + VLDM LR!, { D0-D15 } /* Restore D0-D15. */ +#endif /* portENABLE_FPU*/ + + /* LDM (User registers) - In a PL1 mode other than System mode, LDM (User + * registers) loads multiple User mode registers from consecutive memory + * locations using an address from a base register. The registers loaded + * cannot include the PC. The processor reads the base register value + * normally, using the current mode to determine the correct Banked version + * of the register. This instruction cannot writeback to the base register. + * + * The following can be derived from the above description: + * - The macro portRESTORE_CONTEXT MUST be called from a PL1 mode other than + * the System mode. + * - Base register LR of the current mode will be used which contains the + * location to restore the context from. + * - It will restore R0-R14 of User mode i.e. SP(R13) and LR(R14) of User + * mode will be restored. + */ + LDM LR, { R0-R14 }^ + ADD LR, LR, #60 /* R0-R14 - Total 155 register, each 4 byte wide. */ + + RFE LR /* Restore PC and CPSR from the context. */ + +.endm + +/* ----------------------------------------------------------------------------------- */ + +/* + * void vPortStartFirstTask( void ); + */ +.align 4 +.global vPortStartFirstTask +.type vPortStartFirstTask, %function +vPortStartFirstTask: + /* This function is called from System Mode to start the FreeRTOS-Kernel. + * As described in the portRESTORE_CONTEXT macro, portRESTORE_CONTEXT cannot + * be called from the System mode. We, therefore, switch to the Supervisor + * mode before calling portRESTORE_CONTEXT. */ + CPS #SVC_MODE + portRESTORE_CONTEXT + +/* ----------------------------------------------------------------------------------- */ + +.align 4 +.global FreeRTOS_SVC_Handler +.type FreeRTOS_SVC_Handler, %function +FreeRTOS_SVC_Handler: + PUSH { R11-R12 } + + /* ------------------------- Caller Flash Location Check ------------------------- */ + + LDR R11, =__syscalls_flash_start__ + LDR R12, =__syscalls_flash_end__ + CMP LR, R11 /* If SVC instruction address is less than __syscalls_flash_start__, exit. */ + BLT svcHandlerExit + CMP LR, R12 /* If SVC instruction address is greater than __syscalls_flash_end__, exit. */ + BGT svcHandlerExit + + /* ---------------------------- Get Caller SVC Number ---------------------------- */ + + MRS R11, SPSR /* LR = CPSR at the time of SVC. */ + TST R11, #0x20 /* Check Thumb bit (5) in CPSR. */ + LDRHNE R11, [LR, #-0x2] /* If Thumb, load halfword. */ + BICNE R11, R11, #0xFF00 /* And extract immidiate field (i.e. SVC number). */ + LDREQ R11, [LR, #-0x4] /* If ARM, load word. */ + BICEQ R11, R11, #0xFF000000 /* And extract immidiate field (i.e. SVC number). */ + + /* --------------------------------- SVC Routing --------------------------------- */ + + /* If SVC Number < #NUM_SYSTEM_CALLS, go to svcSystemCallEnter. */ + CMP R11, #NUM_SYSTEM_CALLS + BLT svcSystemCallEnter + + /* If SVC Number == #portSVC_SYSTEM_CALL_EXIT, go to svcSystemCallExit. */ + CMP R11, #portSVC_SYSTEM_CALL_EXIT + BEQ svcSystemCallExit + + /* If SVC Number == #portSVC_YIELD, go to svcPortYield. */ + CMP R11, #portSVC_YIELD + BEQ svcPortYield + +svcHandlerExit: + POP { R11-R12 } + MOVS PC, LR /* Copies the SPSR into the CPSR, performing the mode swap. */ + +svcPortYield: + POP { R11-R12 } + portSAVE_CONTEXT + BL vTaskSwitchContext + portRESTORE_CONTEXT + +svcSystemCallExit: + LDR R11, =pxCurrentTCB /* R11 = &( pxCurrentTCB ). */ + LDR R11, [R11] /* R11 = pxCurrentTCB. */ + ADD R11, R11, #portSYSTEM_CALL_INFO_OFFSET /* R11 now points to xSystemCallStackInfo in TCB. */ + + /* Restore the user mode SP and LR. */ + LDM R11, { R13-R14 }^ + + AND R12, R12, #0x0 /* R12 = 0. */ + STR R12, [R11] /* xSystemCallStackInfo.pulTaskStackPointer = NULL. */ + STR R12, [R11, #0x4] /* xSystemCallStackInfo.pulLinkRegisterAtSystemCallEntry = NULL. */ + + LDMDB R11, { R12 } /* R12 = ulTaskFlags. */ + + TST R12, #portTASK_IS_PRIVILEGED_FLAG + /* If the task is privileged, we can exit now. */ + BNE svcHandlerExit + /* Otherwise, we need to switch back to User mode. */ + MRS R12, SPSR + BIC R12, R12, #0x0F + MSR SPSR_cxsf, R12 + + B svcHandlerExit + +svcSystemCallEnter: + LDR R12, =uxSystemCallImplementations /* R12 = uxSystemCallImplementations. */ + /* R12 = uxSystemCallImplementations[ R12 + ( R11 << 2 ) ]. + * R12 now contains the address of the system call impl function. */ + LDR R12, [R12, R11, lsl #2] + + /* If R12 == NULL, exit. */ + CMP R12, #0x0 + BEQ svcHandlerExit + + /* It is okay to clobber LR here because we do not need to return to the + * SVC enter location anymore. LR now contains the address of the system + * call impl function. */ + MOV LR, R12 + + LDR R11, =pxCurrentTCB /* R11 = &( pxCurrentTCB ). */ + LDR R11, [R11] /* R11 = pxCurrentTCB. */ + ADD R11, R11, #portSYSTEM_CALL_INFO_OFFSET /* R11 now points to xSystemCallStackInfo in TCB. */ + + /* Store User mode SP and LR in xSystemCallStackInfo.pulTaskStackPointer and + * xSystemCallStackInfo.pulLinkRegisterAtSystemCallEntry. */ + STM R11, { R13-R14 }^ + ADD R11, R11, 0x8 + + /* Load User mode SP an LR with xSystemCallStackInfo.pulSystemCallStackPointer + * and xSystemCallStackInfo.pulSystemCallExitAddress. */ + LDM R11, { R13-R14 }^ + + /* Change to SYS_MODE for the System Call. */ + MRS R12, SPSR + ORR R12, R12, #SYS_MODE + MSR SPSR_cxsf, R12 + + B svcHandlerExit + +/* ----------------------------------------------------------------------------------- */ + +/* + * void vPortDisableInterrupts( void ); + */ +.align 4 +.global vPortDisableInterrupts +.type vPortDisableInterrupts, %function +vPortDisableInterrupts: + CPSID I + BX LR + +/* ----------------------------------------------------------------------------------- */ + +/* + * void vPortEnableInterrupts( void ); + */ +.align 4 +.global vPortEnableInterrupts +.type vPortEnableInterrupts, %function +vPortEnableInterrupts: + CPSIE I + BX LR + +/* ----------------------------------------------------------------------------------- */ + +/* + * void vMPUSetRegion( uint32_t ulRegionNumber, + * uint32_t ulBaseAddress, + * uint32_t ulRegionSize, + * uint32_t ulRegionPermissions ); + * + * According to the Procedure Call Standard for the ARM Architecture (AAPCS), + * paramters are passed in the following registers: + * R0 = ulRegionNumber. + * R1 = ulBaseAddress. + * R2 = ulRegionSize. + * R3 = ulRegionPermissions. + */ +.align 4 +.global vMPUSetRegion +.type vMPUSetRegion, %function +vMPUSetRegion: + AND R0, R0, #0x0F /* R0 = R0 & 0x0F. Max possible region number is 15. */ + + MCR p15, #0, R0, c6, c2, #0 /* MPU Region Number Register. */ + MCR p15, #0, R1, c6, c1, #0 /* MPU Region Base Address Register. */ + MCR p15, #0, R3, c6, c1, #4 /* MPU Region Access Control Register. */ + MCR p15, #0, R2, c6, c1, #2 /* MPU Region Size and Enable Register. */ + + BX LR + +/* ----------------------------------------------------------------------------------- */ + +/* + * void vMPUEnable( void ); + */ +.align 4 +.global vMPUEnable +.type vMPUEnable, %function +vMPUEnable: + PUSH { R0 } + + MRC p15, #0, R0, c1, c0, #0 /* R0 = System Control Register (SCTLR). */ + ORR R0, R0, #0x1 /* R0 = R0 | 0x1. Set the M bit in SCTLR. */ + DSB + MCR p15, #0, R0, c1, c0, #0 /* SCTLR = R0. */ + ISB + + POP { R0 } + BX LR + +/* ----------------------------------------------------------------------------------- */ + +/* + * void vMPUDisable( void ); + */ +.align 4 +.global vMPUDisable +.type vMPUDisable, %function +vMPUDisable: + PUSH { R0 } + + MRC p15, #0, R0, c1, c0, #0 /* R0 = System Control Register (SCTLR). */ + BIC R0, R0, #1 /* R0 = R0 & ~0x1. Clear the M bit in SCTLR. */ + /* Wait for all pending data accesses to complete. */ + DSB + MCR p15, #0, R0, c1, c0, #0 /* SCTLR = R0. */ + /* Flush the pipeline and prefetch buffer(s) in the processor to ensure that + * all following instructions are fetched from cache or memory. */ + ISB + + POP { R0 } + BX LR + +/* ----------------------------------------------------------------------------------- */ + +/* + * void vMPUEnableBackgroundRegion( void ); + */ +.align 4 +.global vMPUEnableBackgroundRegion +.type vMPUEnableBackgroundRegion, %function +vMPUEnableBackgroundRegion: + PUSH { R0 } + + MRC p15, #0, R0, c1, c0, #0 /* R0 = System Control Register (SCTLR). */ + ORR R0, R0, #0x20000 /* R0 = R0 | 0x20000. Set the BR bit in SCTLR. */ + MCR p15, #0, R0, c1, c0, #0 /* SCTLR = R0. */ + + POP { R0 } + BX LR + +/* ----------------------------------------------------------------------------------- */ + +/* + * void vMPUDisableBackgroundRegion( void ); + */ +.align 4 +.global vMPUDisableBackgroundRegion +.type vMPUDisableBackgroundRegion, %function +vMPUDisableBackgroundRegion: + PUSH { R0 } + + MRC p15, 0, R0, c1, c0, 0 /* R0 = System Control Register (SCTLR). */ + BIC R0, R0, #0x20000 /* R0 = R0 & ~0x20000. Clear the BR bit in SCTLR. */ + MCR p15, 0, R0, c1, c0, 0 /* SCTLR = R0. */ + + POP { R0 } + BX LR + +/* ----------------------------------------------------------------------------------- */ + +.align 4 +.global FreeRTOS_IRQ_Handler +.type FreeRTOS_IRQ_Handler, %function +FreeRTOS_IRQ_Handler: + SUB LR, LR, #4 /* Return to the interrupted instruction. */ + SRSDB SP!, #IRQ_MODE /* Save return state (i.e. SPSR_irq and LR_irq) to the IRQ stack. */ + + /* Change to supervisor mode to allow reentry. It is necessary to ensure + * that a BL instruction within the interrupt handler code does not + * overwrite LR_irq. */ + CPS #SVC_MODE + + PUSH { R0-R3, R12 } /* Push AAPCS callee saved registers. */ + + /* Update interrupt nesting count. */ + LDR R0, =ulPortInterruptNesting /* R0 = &( ulPortInterruptNesting ). */ + LDR R1, [R0] /* R1 = ulPortInterruptNesting. */ + ADD R2, R1, #1 /* R2 = R1 + 1. */ + STR R2, [R0] /* Store the updated nesting count. */ + + /* Call the application provided IRQ handler. */ + PUSH { R0-R3, LR } + BL vApplicationIRQHandler + POP { R0-R3, LR } + + /* Disable IRQs incase vApplicationIRQHandler enabled them for re-entry. */ + CPSID I + DSB + ISB + + /* Restore the old interrupt nesting count. R0 holds the address of + * ulPortInterruptNesting and R1 holds original value of + * ulPortInterruptNesting. */ + STR R1, [R0] + + /* Context switch is only performed when interrupt nesting count is 0. */ + CMP R1, #0 + BNE exit_without_switch + + /* Check ulPortInterruptNesting to see if the interrupt requested a context + * switch. */ + LDR R1, =ulPortYieldRequired /* R1 = &( ulPortYieldRequired ). */ + LDR R0, [R1] /* R0 = ulPortYieldRequired. */ + /* If ulPortYieldRequired != 0, goto switch_before_exit. */ + CMP R0, #0 + BNE switch_before_exit + +exit_without_switch: + POP { R0-R3, R12 } /* Restore AAPCS callee saved registers. */ + CPS #IRQ_MODE + RFE SP! + +switch_before_exit: + /* A context switch is to be performed. Clear ulPortYieldRequired. R1 holds + * the address of ulPortYieldRequired. */ + MOV R0, #0 + STR R0, [R1] + + /* Restore AAPCS callee saved registers, SPSR_irq and LR_irq before saving + * the task context. */ + POP { R0-R3, R12 } + CPS #IRQ_MODE + /* The contents of the IRQ stack at this point is the following: + * +----------+ + * SP+4 | SPSR_irq | + * +----------+ + * SP | LR_irq | + * +----------+ + */ + LDMIB SP!, { LR } + MSR SPSR_cxsf, LR + LDMDB SP, { LR } + ADD SP, SP, 0x4 + portSAVE_CONTEXT + + /* Call the function that selects the new task to execute. */ + BLX vTaskSwitchContext + + /* Restore the context of, and branch to, the task selected to execute + * next. */ + portRESTORE_CONTEXT + +/* ----------------------------------------------------------------------------------- */ + +.end diff --git a/portable/GCC/ARM_CRx_MPU/portmacro.h b/portable/GCC/ARM_CRx_MPU/portmacro.h new file mode 100644 index 000000000..1eb8f0162 --- /dev/null +++ b/portable/GCC/ARM_CRx_MPU/portmacro.h @@ -0,0 +1,529 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/** + * @brief Functions, Defines, and Structs for use in the ARM_CRx_MPU FreeRTOS-Port + * @file portmacro.h + * @note The settings in this file configure FreeRTOS correctly for the given + * hardware and compiler. These settings should not be altered. + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Include stdint for integer types of specific bit widths. */ +#include + +/* ------------------------------ FreeRTOS Config Check ------------------------------ */ + +#ifndef configSYSTEM_CALL_STACK_SIZE + #error "Define configSYSTEM_CALL_STACK_SIZE to a length, in bytes, " \ + "to use when an unprivileged task makes a FreeRTOS Kernel call. " +#endif /* configSYSTEM_CALL_STACK_SIZE */ + +#if( configUSE_MPU_WRAPPERS_V1 == 1 ) + #error This port is usable with MPU wrappers V2 only. +#endif /* configUSE_MPU_WRAPPERS_V1 */ + +#ifndef configSETUP_TICK_INTERRUPT + #error "configSETUP_TICK_INTERRUPT() must be defined in FreeRTOSConfig.h " \ + "to call the function that sets up the tick interrupt." +#endif /* configSETUP_TICK_INTERRUPT */ + +/* ----------------------------------------------------------------------------------- */ + +#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + + /* Check the configuration. */ + #if( configMAX_PRIORITIES > 32 ) + #error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when " \ + "configMAX_PRIORITIES is less than or equal to 32. " \ + "It is very rare that a system requires more than 10 to 15 difference " \ + "priorities as tasks that share a priority will time slice." + #endif /* ( configMAX_PRIORITIES > 32 ) */ + + /** + * @brief Mark that a task of the given priority is ready. + * + * @ingroup Scheduler + * + * @param[in] uxPriority Priority of the task that is ready. + * @param[in] uxTopReadyPriority Bitmap of the ready tasks priorities. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxTopReadyPriority ) \ + ( uxTopReadyPriority ) |= ( 1UL << ( uxPriority ) ) + + /** + * @brief Mark that a task of the given priority is no longer ready. + * + * @ingroup Scheduler + * + * @param[in] uxPriority Priority of the task that is no longer ready. + * @param[in] uxTopReadyPriority Bitmap of the ready tasks priorities. + */ + #define portRESET_READY_PRIORITY( uxPriority, uxTopReadyPriority ) \ + ( uxTopReadyPriority ) &= ~( 1UL << ( uxPriority ) ) + + /** + * @brief Determine the highest priority ready task's priority. + * + * @ingroup Scheduler + * + * @param[in] uxTopReadyPriority Bitmap of the ready tasks priorities. + * @param[in] uxTopPriority The highest priority ready task's priority. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxTopReadyPriority ) \ + ( uxTopPriority ) = ( 31UL - ulPortCountLeadingZeros( ( uxTopReadyPriority ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/* ------------------------------ Port Type Definitions ------------------------------ */ + +#include "portmacro_asm.h" + +/** + * @brief Critical section nesting value. + * + * @ingroup Critical Sections + * + * @note A task exits critical section and enables IRQs when its nesting count + * reaches this value. + */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0x0 ) + +/** + * @brief Bit in Current Program Status Register (CPSR) to indicate that CPU is + * in Thumb State. + * + * @ingroup Task Context + */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) + +/** + * @brief Bitmask to check if an address is of Thumb Code. + * + * @ingroup Task Context + */ +#define portTHUMB_MODE_ADDRESS ( 0x01UL ) + +/** + * @brief Data type used to represent a stack word. + * + * @ingroup Port Interface Specifications + */ +typedef uint32_t StackType_t; + +/** + * @brief Signed data type equal to the data word operating size of the CPU. + * + * @ingroup Port Interface Specifications + */ +typedef int32_t BaseType_t; + +/** + * @brief Unsigned data type equal to the data word operating size of the CPU. + * + * @ingroup Port Interface Specifications + */ +typedef uint32_t UBaseType_t; + +/** + * @brief Data type used for the FreeRTOS Tick Counter. + * + * @note Using 32-bit tick type on a 32-bit architecture ensures that reads of + * the tick count do not need to be guarded with a critical section. + */ +typedef uint32_t TickType_t; + +/** + * @brief Marks the direction the stack grows on the targeted CPU. + * + * @ingroup Port Interface Specifications + */ +#define portSTACK_GROWTH ( -1 ) + +/** + * @brief Specifies stack pointer alignment requirements of the target CPU. + * + * @ingroup Port Interface Specifications + */ +#define portBYTE_ALIGNMENT 8U + +/** + * @brief Task function prototype macro as described on FreeRTOS.org. + * + * @ingroup Port Interface Specifications + * + * @note This is not required for this port but included in case common demo + * code uses it. + */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) \ + void vFunction( void * pvParameters ) + +/** + * @brief Task function prototype macro as described on FreeRTOS.org. + * + * @ingroup Port Interface Specifications + * + * @note This is not required for this port but included in case common demo + * code uses it. + */ +#define portTASK_FUNCTION( vFunction, pvParameters ) \ + void vFunction( void * pvParameters ) + +/** + * @brief The no-op ARM assembly instruction. + * + * @ingroup Port Interface Specifications + */ +#define portNOP() __asm volatile( "NOP" ) + +/** + * @brief The inline GCC label. + * + * @ingroup Port Interface Specifications + */ +#define portINLINE __inline + +/** + * @brief The memory access synchronization barrier. + * + * @ingroup Port Interface Specifications + */ +#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" ) + +/** + * @brief Ensure a symbol isn't removed from the compilation unit. + * + * @ingroup Port Interface Specifications + */ +#define portDONT_DISCARD __attribute__( ( used ) ) + +/** + * @brief Defines if the tick count can be accessed atomically. + * + * @ingroup System Clock + */ +#define portTICK_TYPE_IS_ATOMIC 1 + +/** + * @brief The number of milliseconds between system ticks. + * + * @ingroup System Clock + */ +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000UL / configTICK_RATE_HZ ) + +/** + * @brief The largest possible delay value for any FreeRTOS API. + * + * @ingroup System Clock + */ +#define portMAX_DELAY ( TickType_t ) 0xFFFFFFFFUL + +/* ----------------------------- Port Assembly Functions ----------------------------- */ + +/** + * @brief FreeRTOS Supervisor Call (SVC) Handler. + * + * @ingroup Scheduler + */ +void FreeRTOS_SVC_Handler( void ); + +/** + * @brief FreeRTOS Interrupt Handler. + * + * @ingroup Scheduler + */ +void FreeRTOS_IRQ_Handler( void ); + +/** + * @brief Yield the CPU. + * + * @ingroup Scheduler + */ +void vPortYield( void ); + +#define portYIELD() vPortYield() + +/** + * @brief Enable interrupts. + * + * @ingroup Interrupt Management + */ +void vPortEnableInterrupts( void ); + +#define portENABLE_INTERRUPTS() vPortEnableInterrupts() + +/** + * @brief Disable interrupts. + * + * @ingroup Interrupt Management + */ +void vPortDisableInterrupts( void ); + +#define portDISABLE_INTERRUPTS() vPortDisableInterrupts() + +/** + * @brief Exit from a FreeRTO System Call. + * + * @ingroup Port Privilege + */ +void vPortSystemCallExit( void ); + +/** + * @brief Start executing first task. + * + * @ingroup Scheduler + */ +void vPortStartFirstTask( void ); + +/** + * @brief Enable the onboard MPU. + * + * @ingroup MPU Control + */ +void vMPUEnable( void ); + +/** + * @brief Disable the onboard MPU. + * + * @ingroup MPU Control + */ +void vMPUDisable( void ); + +/** + * @brief Enable the MPU Background Region. + * + * @ingroup MPU Control + */ +void vMPUEnableBackgroundRegion( void ); + +/** + * @brief Disable the MPU Background Region. + * + * @ingroup MPU Control + */ +void vMPUDisableBackgroundRegion( void ); + +/** + * @brief Set permissions for an MPU Region. + * + * @ingroup MPU Control + * + * @param[in] ulRegionNumber The MPU Region Number to set permissions for. + * @param[in] ulBaseAddress The base address of the MPU Region. + * @param[in] ulRegionSize The size of the MPU Region in bytes. + * @param[in] ulRegionPermissions The permissions associated with the MPU Region. + * + * @note This is an internal function and assumes that the inputs to this + * function are checked before calling this function. + */ +void vMPUSetRegion( uint32_t ulRegionNumber, + uint32_t ulBaseAddress, + uint32_t ulRegionSize, + uint32_t ulRegionPermissions ); + +/* ------------------------------- Port.c Declarations ------------------------------- */ + +/** + * @brief Enter critical section. + * + * @ingroup Critical Section + */ +void vPortEnterCritical( void ); + +#define portENTER_CRITICAL() vPortEnterCritical() + +/** + * @brief Exit critical section. + * + * @ingroup Critical Section + */ +void vPortExitCritical( void ); + +#define portEXIT_CRITICAL() vPortExitCritical() + +/** + * @brief Checks whether or not the processor is privileged. + * + * @ingroup Port Privilege + * + * @note The processor privilege level is determined by checking the + * mode bits [4:0] of the Current Program Status Register (CPSR). + * + * @return pdTRUE, if the processor is privileged, pdFALSE otherwise. + */ +BaseType_t xPortIsPrivileged( void ); + +#define portIS_PRIVILEGED() xPortIsPrivileged() + +/** + * @brief Checks whether or not a task is privileged. + * + * @ingroup Port Privilege + * + * @note A task's privilege level is associated with the task and is different from + * the processor's privilege level returned by xPortIsPrivileged. For example, + * the processor is privileged when an unprivileged task executes a system call. + * + * @return pdTRUE if the task is privileged, pdFALSE otherwise. + */ +BaseType_t xPortIsTaskPrivileged( void ); + +#define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() + +/** + * @brief Default return address for tasks. + * + * @ingroup Task Context + * + * @note This function is used as the default return address for tasks if + * configTASK_RETURN_ADDRESS is not defined in FreeRTOSConfig.h. + */ +void prvTaskExitError( void ); + +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif /* configTASK_RETURN_ADDRESS */ + +/** + * @brief Returns the number of leading zeros in a 32 bit variable. + * + * @param[in] ulBitmap 32-Bit number to count leading zeros in. + * + * @return The number of leading zeros in ulBitmap. + */ +UBaseType_t ulPortCountLeadingZeros( UBaseType_t ulBitmap ); + +/** + * @brief End the FreeRTOS scheduler. + * + * Not implemented on this port. + * + * @ingroup Scheduler + */ +void vPortEndScheduler( void ); + +/* --------------------------------- MPU Definitions --------------------------------- */ + +/** + * @brief Mark that this port utilizes the onboard ARM MPU. + * + * @ingroup MPU Control + */ +#define portUSING_MPU_WRAPPERS 1 + +/** + * @brief Used to mark if a task should be created as a privileged task. + * + * @ingroup Task Context + * @ingroup MPU Control + * + * @note A privileged task is created by performing a bitwise OR of this value and + * the task priority. For example, to create a privileged task at priority 2, the + * uxPriority parameter should be set to ( 2 | portPRIVILEGE_BIT ). + */ +#define portPRIVILEGE_BIT ( 0x80000000UL ) + +/** + * @brief Size of an Access Control List (ACL) entry in bits. + */ +#define portACL_ENTRY_SIZE_BITS ( 32UL ) + +/** + * @brief Structure to hold the MPU Register Values. + * + * @struct xMPU_REGION_REGISTERS + * + * @ingroup MPU Control + * + * @note The ordering of this struct MUST be in sync with the ordering in + * portRESTORE_CONTEXT. + */ +typedef struct MPU_REGION_REGISTERS +{ + uint32_t ulRegionSize; /* Information for MPU Region Size and Enable Register. */ + uint32_t ulRegionAttribute; /* Information for MPU Region Access Control Register. */ + uint32_t ulRegionBaseAddress; /* Information for MPU Region Base Address Register. */ +} xMPU_REGION_REGISTERS; + +/** + * @brief Structure to hold per-task System Call Stack information. + * + * @struct xSYSTEM_CALL_STACK_INFO + * + * @ingroup Port Privilege + * + * @note The ordering of this structure MUST be in sync with the assembly code + * of the port. + */ +typedef struct SYSTEM_CALL_STACK_INFO +{ + uint32_t * pulTaskStackPointer; /**< Stack Pointer of the task when it made a FreeRTOS System Call. */ + uint32_t * pulLinkRegisterAtSystemCallEntry; /**< Link Register of the task when it made a FreeRTOS System Call. */ + uint32_t * pulSystemCallStackPointer; /**< Stack Pointer to use for executing a FreeRTOS System Call. */ + uint32_t * pulSystemCallExitAddress; /**< System call exit address. */ + uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; /**< Buffer to be used as stack when performing a FreeRTOS System Call. */ +} xSYSTEM_CALL_STACK_INFO; + +/** + * @brief Per-Task MPU settings structure stored in the TCB. + * @struct xMPU_SETTINGS + * + * @ingroup MPU Control + * @ingroup Task Context + * @ingroup Port Privilege + * + * @note The ordering of this structure MUST be in sync with the assembly code + * of the port. + */ +typedef struct MPU_SETTINGS +{ + xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS_IN_TCB ]; + uint32_t ulTaskFlags; + xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo; + uint32_t ulContext[ CONTEXT_SIZE ]; /**< Buffer used to store task context. */ + + #if( configENABLE_ACCESS_CONTROL_LIST == 1 ) + uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE + / portACL_ENTRY_SIZE_BITS ) + + 1UL ]; + #endif +} xMPU_SETTINGS; + +#ifdef __cplusplus +} /* extern C */ +#endif + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/ARM_CRx_MPU/portmacro_asm.h b/portable/GCC/ARM_CRx_MPU/portmacro_asm.h new file mode 100644 index 000000000..c9573e419 --- /dev/null +++ b/portable/GCC/ARM_CRx_MPU/portmacro_asm.h @@ -0,0 +1,279 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_ASM_H +#define PORTMACRO_ASM_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "FreeRTOSConfig.h" + +#ifndef configTOTAL_MPU_REGIONS + #error "Set configTOTAL_MPU_REGIONS to the number of MPU regions in FreeRTOSConfig.h" +#elif( configTOTAL_MPU_REGIONS == 12 ) + #define portMPU_TOTAL_REGIONS ( 12UL ) +#elif( configTOTAL_MPU_REGIONS == 16 ) + #define portMPU_TOTAL_REGIONS ( 16UL ) +#else + #error "Set configTOTAL_MPU_REGIONS to the number of MPU regions in FreeRTOSConfig.h" +#endif /* configTOTAL_MPU_REGIONS */ + +/* + * The application write can disable Floating Point Unit (FPU) support by + * setting configENABLE_FPU to 0. Floating point context stored in TCB + * comprises of 32 floating point registers (D0-D31) and FPSCR register. + * Disabling FPU, therefore, reduces the per-task RAM usage by + * ( 32 + 1 ) * 4 = 132 bytes per task. + * + * BE CAREFUL DISABLING THIS: Certain standard library APIs try to optimize + * themselves by using the floating point registers. If the FPU support is + * disabled, the use of such APIs may result in memory corruption. + */ +#ifndef configENABLE_FPU + #define configENABLE_FPU 1 +#endif /* configENABLE_FPU */ + +#define portENABLE_FPU configENABLE_FPU + +/* On the ArmV7-R Architecture the Operating mode of the Processor is set + * using the Current Program Status Register (CPSR) Mode bits, [4:0]. The only + * unprivileged mode is User Mode. + * + * Additional information about the Processor Modes can be found here: + * https://developer.arm.com/documentation/ddi0406/cb/System-Level-Architecture/The-System-Level-Programmers--Model/ARM-processor-modes-and-ARM-core-registers/ARM-processor-modes?lang=en + * + */ + +/** + * @brief CPSR bits for various processor modes. + * + * @ingroup Port Privilege + */ +#define USER_MODE 0x10U +#define FIQ_MODE 0x11U +#define IRQ_MODE 0x12U +#define SVC_MODE 0x13U +#define MON_MODE 0x16U +#define ABT_MODE 0x17U +#define HYP_MODE 0x1AU +#define UND_MODE 0x1BU +#define SYS_MODE 0x1FU + +/** + * @brief Flag used to mark that a FreeRTOS Task is privileged. + * + * @ingroup Port Privilege + */ +#define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) + +/** + * @brief SVC numbers for various scheduler operations. + * + * @ingroup Scheduler + * + * @note These value must not be used in mpu_syscall_numbers.h. + */ +#define portSVC_YIELD 0x0100U +#define portSVC_SYSTEM_CALL_EXIT 0x0104U + +/** + * @brief Macros required to manipulate MPU. + * + * Further information about MPU can be found in Arm's documentation + * https://developer.arm.com/documentation/ddi0363/g/System-Control/Register-descriptions/c6--MPU-memory-region-programming-registers + * + */ + +/* MPU sub-region disable settings. This information is encoded in the MPU + * Region Size and Enable Register. */ +#define portMPU_SUBREGION_0_DISABLE ( 0x1UL << 8UL ) +#define portMPU_SUBREGION_1_DISABLE ( 0x1UL << 9UL ) +#define portMPU_SUBREGION_2_DISABLE ( 0x1UL << 10UL ) +#define portMPU_SUBREGION_3_DISABLE ( 0x1UL << 11UL ) +#define portMPU_SUBREGION_4_DISABLE ( 0x1UL << 12UL ) +#define portMPU_SUBREGION_5_DISABLE ( 0x1UL << 13UL ) +#define portMPU_SUBREGION_6_DISABLE ( 0x1UL << 14UL ) +#define portMPU_SUBREGION_7_DISABLE ( 0x1UL << 15UL ) + +/* Default MPU regions. */ +#define portFIRST_CONFIGURABLE_REGION ( 0 ) +#define portLAST_CONFIGURABLE_REGION ( portMPU_TOTAL_REGIONS - 5UL ) +#define portSTACK_REGION ( portMPU_TOTAL_REGIONS - 4UL ) +#define portUNPRIVILEGED_FLASH_REGION ( portMPU_TOTAL_REGIONS - 3UL ) +#define portPRIVILEGED_FLASH_REGION ( portMPU_TOTAL_REGIONS - 2UL ) +#define portPRIVILEGED_RAM_REGION ( portMPU_TOTAL_REGIONS - 1UL ) +#define portNUM_CONFIGURABLE_REGIONS \ + ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1UL ) +/* Plus one to make space for the stack region. */ +#define portTOTAL_NUM_REGIONS_IN_TCB ( portNUM_CONFIGURABLE_REGIONS + 1UL ) + +/* MPU region sizes. This information is encoded in the MPU Region Size and + * Enable Register. */ +#define portMPU_REGION_SIZE_32B ( 0x04UL << 1UL ) +#define portMPU_REGION_SIZE_64B ( 0x05UL << 1UL ) +#define portMPU_REGION_SIZE_128B ( 0x06UL << 1UL ) +#define portMPU_REGION_SIZE_256B ( 0x07UL << 1UL ) +#define portMPU_REGION_SIZE_512B ( 0x08UL << 1UL ) +#define portMPU_REGION_SIZE_1KB ( 0x09UL << 1UL ) +#define portMPU_REGION_SIZE_2KB ( 0x0AUL << 1UL ) +#define portMPU_REGION_SIZE_4KB ( 0x0BUL << 1UL ) +#define portMPU_REGION_SIZE_8KB ( 0x0CUL << 1UL ) +#define portMPU_REGION_SIZE_16KB ( 0x0DUL << 1UL ) +#define portMPU_REGION_SIZE_32KB ( 0x0EUL << 1UL ) +#define portMPU_REGION_SIZE_64KB ( 0x0FUL << 1UL ) +#define portMPU_REGION_SIZE_128KB ( 0x10UL << 1UL ) +#define portMPU_REGION_SIZE_256KB ( 0x11UL << 1UL ) +#define portMPU_REGION_SIZE_512KB ( 0x12UL << 1UL ) +#define portMPU_REGION_SIZE_1MB ( 0x13UL << 1UL ) +#define portMPU_REGION_SIZE_2MB ( 0x14UL << 1UL ) +#define portMPU_REGION_SIZE_4MB ( 0x15UL << 1UL ) +#define portMPU_REGION_SIZE_8MB ( 0x16UL << 1UL ) +#define portMPU_REGION_SIZE_16MB ( 0x17UL << 1UL ) +#define portMPU_REGION_SIZE_32MB ( 0x18UL << 1UL ) +#define portMPU_REGION_SIZE_64MB ( 0x19UL << 1UL ) +#define portMPU_REGION_SIZE_128MB ( 0x1AUL << 1UL ) +#define portMPU_REGION_SIZE_256MB ( 0x1BUL << 1UL ) +#define portMPU_REGION_SIZE_512MB ( 0x1CUL << 1UL ) +#define portMPU_REGION_SIZE_1GB ( 0x1DUL << 1UL ) +#define portMPU_REGION_SIZE_2GB ( 0x1EUL << 1UL ) +#define portMPU_REGION_SIZE_4GB ( 0x1FUL << 1UL ) + +/* MPU memory types. This information is encoded in the TEX, S, C and B bits + * of the MPU Region Access Control Register. */ +#define portMPU_REGION_STRONGLY_ORDERED_SHAREABLE ( 0x00UL ) /* TEX=000, S=NA, C=0, B=0. */ +#define portMPU_REGION_DEVICE_SHAREABLE ( 0x01UL ) /* TEX=000, S=NA, C=0, B=1. */ +#define portMPU_REGION_NORMAL_OIWTNOWA_NONSHARED ( 0x02UL ) /* TEX=000, S=0, C=1, B=0. */ +#define portMPU_REGION_NORMAL_OIWTNOWA_SHARED ( 0x06UL ) /* TEX=000, S=1, C=1, B=0. */ +#define portMPU_REGION_NORMAL_OIWBNOWA_NONSHARED ( 0x03UL ) /* TEX=000, S=0, C=1, B=1. */ +#define portMPU_REGION_NORMAL_OIWBNOWA_SHARED ( 0x07UL ) /* TEX=000, S=1, C=1, B=1. */ +#define portMPU_REGION_NORMAL_OINC_NONSHARED ( 0x08UL ) /* TEX=001, S=0, C=0, B=0. */ +#define portMPU_REGION_NORMAL_OINC_SHARED ( 0x0CUL ) /* TEX=001, S=1, C=0, B=0. */ +#define portMPU_REGION_NORMAL_OIWBWA_NONSHARED ( 0x0BUL ) /* TEX=001, S=0, C=1, B=1. */ +#define portMPU_REGION_NORMAL_OIWBWA_SHARED ( 0x0FUL ) /* TEX=001, S=1, C=1, B=1. */ +#define portMPU_REGION_DEVICE_NONSHAREABLE ( 0x10UL ) /* TEX=010, S=NA, C=0, B=0. */ + +/* MPU access permissions. This information is encoded in the XN and AP bits of + * the MPU Region Access Control Register. */ +#define portMPU_REGION_AP_BITMASK ( 0x07UL << 8UL ) +#define portMPU_REGION_XN_BITMASK ( 0x01UL << 12UL ) + +#define portMPU_REGION_PRIV_NA_USER_NA ( 0x00UL << 8UL ) +#define portMPU_REGION_PRIV_NA_USER_NA_EXEC ( portMPU_REGION_PRIV_NA_USER_NA ) /* Priv: X, Unpriv: X. */ +#define portMPU_REGION_PRIV_NA_USER_NA_NOEXEC ( portMPU_REGION_PRIV_NA_USER_NA | \ + portMPU_REGION_XN_BITMASK ) /* Priv: No Access, Unpriv: No Access. */ + +#define portMPU_REGION_PRIV_RW_USER_NA ( 0x01UL << 8UL ) +#define portMPU_REGION_PRIV_RW_USER_NA_EXEC ( portMPU_REGION_PRIV_RW_USER_NA ) /* Priv: RWX, Unpriv: X. */ +#define portMPU_REGION_PRIV_RW_USER_NA_NOEXEC ( portMPU_REGION_PRIV_RW_USER_NA | \ + portMPU_REGION_XN_BITMASK ) /* Priv: RW, Unpriv: No access. */ + +#define portMPU_REGION_PRIV_RW_USER_RO ( 0x02UL << 8UL ) +#define portMPU_REGION_PRIV_RW_USER_RO_EXEC ( portMPU_REGION_PRIV_RW_USER_RO ) /* Priv: RWX, Unpriv: RX. */ +#define portMPU_REGION_PRIV_RW_USER_RO_NOEXEC ( portMPU_REGION_PRIV_RW_USER_RO | \ + portMPU_REGION_XN_BITMASK ) /* Priv: RW, Unpriv: R. */ + +#define portMPU_REGION_PRIV_RW_USER_RW ( 0x03UL << 8UL ) +#define portMPU_REGION_PRIV_RW_USER_RW_EXEC ( portMPU_REGION_PRIV_RW_USER_RW ) /* Priv: RWX, Unpriv: RWX. */ +#define portMPU_REGION_PRIV_RW_USER_RW_NOEXEC ( portMPU_REGION_PRIV_RW_USER_RW | \ + portMPU_REGION_XN_BITMASK ) /* Priv: RW, Unpriv: RW. */ + +#define portMPU_REGION_PRIV_RO_USER_NA ( 0x05UL << 8UL ) +#define portMPU_REGION_PRIV_RO_USER_NA_EXEC ( portMPU_REGION_PRIV_RO_USER_NA ) /* Priv: RX, Unpriv: X. */ +#define portMPU_REGION_PRIV_RO_USER_NA_NOEXEC ( portMPU_REGION_PRIV_RO_USER_NA | \ + portMPU_REGION_XN_BITMASK ) /* Priv: R, Unpriv: No access. */ + +#define portMPU_REGION_PRIV_RO_USER_RO ( 0x06UL << 8UL ) +#define portMPU_REGION_PRIV_RO_USER_RO_EXEC ( portMPU_REGION_PRIV_RO_USER_RO ) /* Priv: RX, Unpriv: RX. */ +#define portMPU_REGION_PRIV_RO_USER_RO_NOEXEC ( portMPU_REGION_PRIV_RO_USER_RO | \ + portMPU_REGION_XN_BITMASK ) /* Priv: R, Unpriv: R. */ + +/* MPU region management. */ +#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 12UL ) +#define portMPU_REGION_ENABLE ( 0x01UL ) + +/** + * @brief The size (in words) of a task context. + * + * An array of this size is allocated in TCB where a task's context is saved + * when it is switched out. + * + * Information about Floating Point Unit (FPU): + * https://developer.arm.com/documentation/den0042/a/Floating-Point + * + * Additional information related to the Cortex R4-F's FPU Implementation: + * https://developer.arm.com/documentation/ddi0363/e/fpu-programmer-s-model + * + * Additional information related to the Cortex R5-F's FPU Implementation: + * https://developer.arm.com/documentation/ddi0460/d/FPU-Programmers-Model + * + * Additional information related to the ArmV7-R CPSR: + * https://developer.arm.com/documentation/ddi0406/cb/Application-Level-Architecture/Application-Level-Programmers--Model/The-Application-Program-Status-Register--APSR-?lang=en + * + * Additional information related to the GPRs: + * https://developer.arm.com/documentation/ddi0406/cb/System-Level-Architecture/The-System-Level-Programmers--Model/ARM-processor-modes-and-ARM-core-registers/ARM-core-registers?lang=en + * + */ + +#if( portENABLE_FPU == 1 ) + /* + * +-------------------+-------+----------+--------+----------+----------+----------+------+ + * | ulCriticalNesting | FPSCR | S0-S31 | R0-R12 | SP (R13) | LR (R14) | PC (R15) | CPSR | + * +-------------------+-------+----------+--------+----------+----------+----------+------+ + * + * <------------------><------><---------><--------><---------><--------><----------><-----> + * 1 1 32 13 1 1 1 1 + */ + #define CONTEXT_SIZE 51U +#else + /* + * +-------------------+--------+----------+----------+----------+------+ + * | ulCriticalNesting | R0-R12 | SP (R13) | LR (R14) | PC (R15) | CPSR | + * +-------------------+--------+----------+----------+----------+------+ + * + * <------------------><--------><---------><--------><----------><-----> + * 1 13 1 1 1 1 + */ + #define CONTEXT_SIZE 18U +#endif /* CONTEXT_SIZE */ + +/** + * @brief Offset of xSystemCallStackInfo from the start of a TCB. + */ +#define portSYSTEM_CALL_INFO_OFFSET \ + ( ( 1U /* pxTopOfStack. */ + \ + ( portTOTAL_NUM_REGIONS_IN_TCB * 3U ) + \ + 1U /* ulTaskFlags. */ \ + ) * 4U ) + +#ifdef __cplusplus +} /* extern C */ +#endif + +#endif /* PORTMACRO_ASM_H */ diff --git a/portable/GCC/ARM_CRx_No_GIC/port.c b/portable/GCC/ARM_CRx_No_GIC/port.c new file mode 100644 index 000000000..81b16dcf6 --- /dev/null +++ b/portable/GCC/ARM_CRx_No_GIC/port.c @@ -0,0 +1,361 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + /* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +#ifndef configSETUP_TICK_INTERRUPT + #error configSETUP_TICK_INTERRUPT() must be defined in FreeRTOSConfig.h to call the function that sets up the tick interrupt. +#endif + +#ifndef configCLEAR_TICK_INTERRUPT + #error configCLEAR_TICK_INTERRUPT must be defined in FreeRTOSConfig.h to clear which ever interrupt was used to generate the tick interrupt. +#endif + +/* A critical section is exited when the critical section nesting count reaches + * this value. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + +/* Tasks are not created with a floating point context, but can be given a + * floating point context after they have been created. A variable is stored as + * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task + * does not have an FPU context, or any other value if the task does have an FPU + * context. */ +#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) + +/* Constants required to setup the initial task context. */ +#ifdef __ARMEB__ + #define portINITIAL_SPSR ( ( StackType_t ) 0x21f ) /* System mode, ARM mode, IRQ enabled FIQ enabled, Big-endian. */ +#else + #define portINITIAL_SPSR ( ( StackType_t ) 0x01f ) /* System mode, ARM mode, IRQ enabled FIQ enabled, Little-endian. */ +#endif +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portTHUMB_MODE_ADDRESS ( 0x01UL ) + +/* Masks all bits in the APSR other than the mode bits. */ +#define portAPSR_MODE_BITS_MASK ( 0x1F ) + +/* The value of the mode bits in the APSR when the CPU is executing in user + * mode. */ +#define portAPSR_USER_MODE ( 0x10 ) + +/* Let the user override the pre-loading of the initial LR with the address of + * prvTaskExitError() in case it messes up unwinding of the stack in the + * debugger. */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/* The space on the stack required to hold the FPU registers. */ +#if ( configFPU_D32 == 1 ) + #define portFPU_REGISTER_WORDS ( ( 32 * 2 ) + 1 ) /* D0-D31 and FPSCR. */ +#else + #define portFPU_REGISTER_WORDS ( ( 16 * 2 ) + 1 ) /* D0-D15 and FPSCR. */ +#endif /* configFPU_D32 */ + +/*-----------------------------------------------------------*/ + +/* + * These functions are necessarily written in assembly code, so are implemented + * in portASM.S. + */ +extern void vPortRestoreTaskContext( void ); +extern void vPortInitialiseFPSCR( void ); +extern uint32_t ulReadAPSR( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* A variable is used to keep track of the critical section nesting. This + * variable has to be stored as part of the task context and must be initialised to + * a non zero value to ensure interrupts don't inadvertently become unmasked before + * the scheduler starts. As it is stored as part of the task context it will + * automatically be set to 0 when the first task is started. */ +volatile uint32_t ulCriticalNesting = 9999UL; + +/* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then + * a floating point context must be saved and restored for the task. */ +volatile uint32_t ulPortTaskHasFPUContext = pdFALSE; + +/* Set to 1 to pend a context switch from an ISR. */ +volatile uint32_t ulPortYieldRequired = pdFALSE; + +/* Counts the interrupt nesting depth. A context switch is only performed if + * if the nesting depth is 0. */ +volatile uint32_t ulPortInterruptNesting = 0UL; + +/* Used in the asm file to clear an interrupt. */ +__attribute__( ( used ) ) const uint32_t ulICCEOIR = configEOI_ADDRESS; + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Setup the initial stack of the task. The stack is set exactly as + * expected by the portRESTORE_CONTEXT() macro. + * + * The fist real value on the stack is the status register, which is set for + * system mode, with interrupts enabled. A few NULLs are added first to ensure + * GDB does not try decoding a non-existent return address. */ + *pxTopOfStack = ( StackType_t ) NULL; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) NULL; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) NULL; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + + if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL ) + { + /* The task will start in THUMB mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + + pxTopOfStack--; + + /* Next the return address, which in this case is the start of the task. */ + *pxTopOfStack = ( StackType_t ) pxCode; + pxTopOfStack--; + + /* Next all the registers other than the stack pointer. */ + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The task will start with a critical nesting count of 0 as interrupts are + * enabled. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + + #if ( configUSE_TASK_FPU_SUPPORT == 1 ) + { + /* The task will start without a floating point context. A task that uses + * the floating point hardware must call vPortTaskUsesFPU() before executing + * any floating point instructions. */ + pxTopOfStack--; + *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT; + } + #elif ( configUSE_TASK_FPU_SUPPORT == 2 ) + { + /* The task will start with a floating point context. Leave enough + * space for the registers - and ensure they are initialised to 0. */ + pxTopOfStack -= portFPU_REGISTER_WORDS; + memset( pxTopOfStack, 0x00, portFPU_REGISTER_WORDS * sizeof( StackType_t ) ); + + /* Initialise the slot containing ulPortTaskHasFPUContext to true as + * the task starts with a floating point context. */ + pxTopOfStack--; + *pxTopOfStack = pdTRUE; + ulPortTaskHasFPUContext = pdTRUE; + } + #else + { + #error "Invalid configUSE_TASK_FPU_SUPPORT value - configUSE_TASK_FPU_SUPPORT must be set to 1, 2, or left undefined." + } + #endif /* if ( configUSE_TASK_FPU_SUPPORT == 1 ) */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ + configASSERT( ulPortInterruptNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + uint32_t ulAPSR; + + /* Only continue if the CPU is not in User mode. The CPU must be in a + * Privileged mode for the scheduler to start. */ + ulAPSR = ulReadAPSR(); + + ulAPSR &= portAPSR_MODE_BITS_MASK; + configASSERT( ulAPSR != portAPSR_USER_MODE ); + + if( ulAPSR != portAPSR_USER_MODE ) + { + /* Start the timer that generates the tick ISR. */ + portDISABLE_INTERRUPTS(); + configSETUP_TICK_INTERRUPT(); + + /* Start the first task executing. */ + vPortRestoreTaskContext(); + } + + /* Will only get here if vTaskStartScheduler() was called with the CPU in + * a non-privileged mode or the binary point register was not set to its lowest + * possible value. prvTaskExitError() is referenced to prevent a compiler + * warning about it being defined but not referenced in the case that the user + * defines their own exit address. */ + ( void ) prvTaskExitError; + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + + /* Now that interrupts are disabled, ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ + if( ulCriticalNesting == 1 ) + { + configASSERT( ulPortInterruptNesting == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as the critical section is being + * exited. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then all interrupt + * priorities must be re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Critical nesting has reached zero so all interrupt priorities + * should be unmasked. */ + portENABLE_INTERRUPTS(); + } + } +} +/*-----------------------------------------------------------*/ + +void FreeRTOS_Tick_Handler( void ) +{ + uint32_t ulInterruptStatus; + + ulInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + ulPortYieldRequired = pdTRUE; + } + + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulInterruptStatus ); + + configCLEAR_TICK_INTERRUPT(); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_FPU_SUPPORT != 2 ) + + void vPortTaskUsesFPU( void ) + { + /* A task is registering the fact that it needs an FPU context. Set the + * FPU flag (which is saved as part of the task context). */ + ulPortTaskHasFPUContext = pdTRUE; + + /* Initialise the floating point status register. */ + vPortInitialiseFPSCR(); + } + +#endif /* configUSE_TASK_FPU_SUPPORT */ +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_CRx_No_GIC/portASM.S b/portable/GCC/ARM_CRx_No_GIC/portASM.S new file mode 100644 index 000000000..de9845e0f --- /dev/null +++ b/portable/GCC/ARM_CRx_No_GIC/portASM.S @@ -0,0 +1,434 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + .text + .arm + .syntax unified + + .set SYS_MODE, 0x1f + .set SVC_MODE, 0x13 + .set IRQ_MODE, 0x12 + .set CPSR_I_BIT, 0x80 + + /* Variables and functions. */ + .extern pxCurrentTCB + .extern vTaskSwitchContext + .extern vApplicationIRQHandler + .extern vApplicationFPUSafeIRQHandler + .extern ulPortInterruptNesting + .extern ulPortTaskHasFPUContext + .extern ulICCEOIR + .extern ulPortYieldRequired + + .global FreeRTOS_IRQ_Handler + .global FreeRTOS_SVC_Handler + .global vPortRestoreTaskContext + .global vPortInitialiseFPSCR + .global ulReadAPSR + .global vPortYield + .global vPortEnableInterrupts + .global vPortDisableInterrupts + .global ulPortSetInterruptMaskFromISR + .global ulPortCountLeadingZeros + + .weak vApplicationSVCHandler +/*-----------------------------------------------------------*/ + +.macro portSAVE_CONTEXT + + /* Save the LR and SPSR onto the system mode stack before switching to + * system mode to save the remaining system mode registers. */ + SRSDB SP!, #SYS_MODE + CPS #SYS_MODE + PUSH {R0-R12, R14} + + /* Push the critical nesting count. */ + LDR R2, =ulCriticalNesting + LDR R1, [R2] + PUSH {R1} + + /* Does the task have a floating point context that needs saving? If + * ulPortTaskHasFPUContext is 0 then no. */ + LDR R2, =ulPortTaskHasFPUContext + LDR R3, [R2] + CMP R3, #0 + + /* Save the floating point context, if any. */ + VMRSNE R1, FPSCR + VPUSHNE {D0-D15} +#if configFPU_D32 == 1 + VPUSHNE {D16-D31} +#endif /* configFPU_D32 */ + PUSHNE {R1} + + /* Save ulPortTaskHasFPUContext itself. */ + PUSH {R3} + + /* Save the stack pointer in the TCB. */ + LDR R0, =pxCurrentTCB + LDR R1, [R0] + STR SP, [R1] + + .endm + +/*-----------------------------------------------------------*/ + +.macro portRESTORE_CONTEXT + + /* Set the SP to point to the stack of the task being restored. */ + LDR R0, =pxCurrentTCB + LDR R1, [R0] + LDR SP, [R1] + + /* Is there a floating point context to restore? If the restored + * ulPortTaskHasFPUContext is zero then no. */ + LDR R0, =ulPortTaskHasFPUContext + POP {R1} + STR R1, [R0] + CMP R1, #0 + + /* Restore the floating point context, if any. */ + POPNE {R0} +#if configFPU_D32 == 1 + VPOPNE {D16-D31} +#endif /* configFPU_D32 */ + VPOPNE {D0-D15} + VMSRNE FPSCR, R0 + + /* Restore the critical section nesting depth. */ + LDR R0, =ulCriticalNesting + POP {R1} + STR R1, [R0] + + /* Restore all system mode registers other than the SP (which is already + being used). */ + POP {R0-R12, R14} + + /* Return to the task code, loading CPSR on the way. */ + RFEIA SP! + + .endm + +/*-----------------------------------------------------------*/ + +/* + * void vPortRestoreTaskContext( void ); + * + * vPortRestoreTaskContext is used to start the scheduler. + */ +.align 4 +.type vPortRestoreTaskContext, %function +vPortRestoreTaskContext: + /* Switch to system mode. */ + CPS #SYS_MODE + portRESTORE_CONTEXT + +/*-----------------------------------------------------------*/ + +/* + * void vPortInitialiseFPSCR( void ); + * + * vPortInitialiseFPSCR is used to initialize the FPSCR register. + */ +.align 4 +.type vPortInitialiseFPSCR, %function +vPortInitialiseFPSCR: + MOV R0, #0 + VMSR FPSCR, R0 + BX LR + +/*-----------------------------------------------------------*/ + +/* + * uint32_t ulReadAPSR( void ); + * + * ulReadAPSR is used to read the value of APSR context. + */ +.align 4 +.type ulReadAPSR, %function +ulReadAPSR: + MRS R0, APSR + BX LR + +/*-----------------------------------------------------------*/ + +/* + * void vPortYield( void ); + */ +.align 4 +.type vPortYield, %function +vPortYield: + SVC 0 + ISB + BX LR + +/*-----------------------------------------------------------*/ + +/* + * void vPortEnableInterrupts( void ); + */ +.align 4 +.type vPortEnableInterrupts, %function +vPortEnableInterrupts: + CPSIE I + BX LR + +/*-----------------------------------------------------------*/ + +/* + * void vPortDisableInterrupts( void ); + */ +.align 4 +.type vPortDisableInterrupts, %function +vPortDisableInterrupts: + CPSID I + DSB + ISB + BX LR + +/*-----------------------------------------------------------*/ + +/* + * uint32_t ulPortSetInterruptMaskFromISR( void ); + */ +.align 4 +.type ulPortSetInterruptMaskFromISR, %function +ulPortSetInterruptMaskFromISR: + MRS R0, CPSR + AND R0, R0, #CPSR_I_BIT + CPSID I + DSB + ISB + BX LR + +/*-----------------------------------------------------------*/ + +/* + * void vApplicationSVCHandler( uint32_t ulSvcNumber ); + */ +.align 4 +.type vApplicationSVCHandler, %function +vApplicationSVCHandler: + B vApplicationSVCHandler + +/*-----------------------------------------------------------*/ + +/* If the application provides an implementation of vApplicationIRQHandler(), + * then it will get called directly without saving the FPU registers on + * interrupt entry, and this weak implementation of vApplicationIRQHandler() + * will not get called. + * + * If the application provides its own implementation of + * vApplicationFPUSafeIRQHandler() then this implementation of + * vApplicationIRQHandler() will be called, save the FPU registers, and then + * call vApplicationFPUSafeIRQHandler(). + * + * Therefore, if the application writer wants FPU registers to be saved on + * interrupt entry, their IRQ handler must be called + * vApplicationFPUSafeIRQHandler(), and if the application writer does not want + * FPU registers to be saved on interrupt entry their IRQ handler must be + * called vApplicationIRQHandler(). + */ +.align 4 +.weak vApplicationIRQHandler +.type vApplicationIRQHandler, %function +vApplicationIRQHandler: + PUSH {LR} + + VMRS R1, FPSCR + VPUSH {D0-D7} + PUSH {R1} + + BLX vApplicationFPUSafeIRQHandler + + POP {R0} + VPOP {D0-D7} + VMSR FPSCR, R0 + + POP {PC} + +/*-----------------------------------------------------------*/ + +.align 4 +.weak vApplicationFPUSafeIRQHandler +.type vApplicationFPUSafeIRQHandler, %function +vApplicationFPUSafeIRQHandler: + B vApplicationFPUSafeIRQHandler + +/*-----------------------------------------------------------*/ + +/* + * UBaseType_t ulPortCountLeadingZeros( UBaseType_t ulBitmap ); + * + * According to the Procedure Call Standard for the ARM Architecture (AAPCS): + * - Parameter ulBitmap is passed in R0. + * - Return value must be in R0. + */ +.align 4 +.type ulPortCountLeadingZeros, %function +ulPortCountLeadingZeros: + CLZ R0, R0 + BX LR + +/*-----------------------------------------------------------*/ + +/* + * SVC handler is used to yield. + */ +.align 4 +.type FreeRTOS_SVC_Handler, %function +FreeRTOS_SVC_Handler: + PUSH { R0-R1 } + + /* ---------------------------- Get Caller SVC Number ---------------------------- */ + MRS R0, SPSR /* R0 = CPSR at the time of SVC. */ + TST R0, #0x20 /* Check Thumb bit (5) in CPSR. */ + LDRHNE R0, [LR, #-0x2] /* If Thumb, load halfword. */ + BICNE R0, R0, #0xFF00 /* And extract immidiate field (i.e. SVC number). */ + LDREQ R0, [LR, #-0x4] /* If ARM, load word. */ + BICEQ R0, R0, #0xFF000000 /* And extract immidiate field (i.e. SVC number). */ + + /* --------------------------------- SVC Routing --------------------------------- */ + CMP R0, #0 + BEQ svcPortYield + BNE svcApplicationCall + +svcPortYield: + POP { R0-R1 } + portSAVE_CONTEXT + BLX vTaskSwitchContext + portRESTORE_CONTEXT + +svcApplicationCall: + POP { R0-R1 } + portSAVE_CONTEXT + BLX vApplicationSVCHandler + portRESTORE_CONTEXT + +/*-----------------------------------------------------------*/ + +.align 4 +.type FreeRTOS_IRQ_Handler, %function +FreeRTOS_IRQ_Handler: + /* Return to the interrupted instruction. */ + SUB LR, LR, #4 + + /* Push the return address and SPSR. */ + PUSH {LR} + MRS LR, SPSR + PUSH {LR} + + /* Change to supervisor mode to allow reentry. */ + CPS #SVC_MODE + + /* Push used registers. */ + PUSH {R0-R3, R12} + + /* Increment nesting count. r3 holds the address of ulPortInterruptNesting + * for future use. r1 holds the original ulPortInterruptNesting value for + * future use. */ + LDR R3, =ulPortInterruptNesting + LDR R1, [R3] + ADD R0, R1, #1 + STR R0, [R3] + + /* Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for + * future use. */ + MOV R0, SP + AND R2, R0, #4 + SUB SP, SP, R2 + + /* Call the interrupt handler. */ + PUSH {R0-R3, LR} + BLX vApplicationIRQHandler + POP {R0-R3, LR} + ADD SP, SP, R2 + + /* Disable IRQs incase vApplicationIRQHandler enabled them for re-entry. */ + CPSID i + DSB + ISB + + /* Write to the EOI register. */ + LDR R0, =ulICCEOIR + LDR R2, [R0] + STR R0, [R2] + + /* Restore the old nesting count. */ + STR R1, [R3] + + /* A context switch is never performed if the nesting count is not 0. */ + CMP R1, #0 + BNE exit_without_switch + + /* Did the interrupt request a context switch? r1 holds the address of + * ulPortYieldRequired and r0 the value of ulPortYieldRequired for future + * use. */ + LDR R1, =ulPortYieldRequired + LDR R0, [R1] + CMP R0, #0 + BNE switch_before_exit + +exit_without_switch: + /* No context switch. Restore used registers, LR_irq and SPSR before + * returning. */ + POP {R0-R3, R12} + CPS #IRQ_MODE + POP {LR} + MSR SPSR_cxsf, LR + POP {LR} + MOVS PC, LR + +switch_before_exit: + /* A context switch is to be performed. Clear the context switch pending + * flag. */ + MOV R0, #0 + STR R0, [R1] + + /* Restore used registers, LR-irq and SPSR before saving the context + * to the task stack. */ + POP {R0-R3, R12} + CPS #IRQ_MODE + POP {LR} + MSR SPSR_cxsf, LR + POP {LR} + portSAVE_CONTEXT + + /* Call the function that selects the new task to execute. + * vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD + * instructions, or 8 byte aligned stack allocated data. LR does not need + * saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */ + BLX vTaskSwitchContext + + /* Restore the context of, and branch to, the task selected to execute + * next. */ + portRESTORE_CONTEXT + +/*-----------------------------------------------------------*/ + +.end diff --git a/portable/GCC/ARM_CRx_No_GIC/portmacro.h b/portable/GCC/ARM_CRx_No_GIC/portmacro.h new file mode 100644 index 000000000..b29bd9be1 --- /dev/null +++ b/portable/GCC/ARM_CRx_No_GIC/portmacro.h @@ -0,0 +1,185 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +typedef uint32_t TickType_t; +#define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ +#define portTICK_TYPE_IS_ATOMIC 1 + +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* Called at the end of an ISR that can cause a context switch. */ +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + { \ + extern volatile uint32_t ulPortYieldRequired; \ + \ + if( xSwitchRequired != pdFALSE ) \ + { \ + ulPortYieldRequired = pdTRUE; \ + } \ + } + +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) + +void vPortYield( void ); + +#define portYIELD() vPortYield(); + +/*-----------------------------------------------------------*/ + +/* + * Critical section management. + */ + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +extern void vPortEnableInterrupts( void ); +extern void vPortDisableInterrupts( void ); +extern uint32_t ulPortSetInterruptMaskFromISR( void ); + +/* In the absence of a priority mask register, these functions and macros + * globally enable and disable interrupts. */ +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); +#define portENABLE_INTERRUPTS() vPortEnableInterrupts(); +#define portDISABLE_INTERRUPTS() vPortDisableInterrupts(); +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMaskFromISR(); +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) do { if( x == 0 ) portENABLE_INTERRUPTS(); } while( 0 ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not required for this port but included in case common demo code that uses these + * macros is used. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* Tickless idle/low power functionality. */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif + +/* Prototype of the FreeRTOS tick handler. This must be installed as the + * handler for whichever peripheral is used to generate the RTOS tick. */ +void FreeRTOS_Tick_Handler( void ); + +/** + * @brief Returns the number of leading zeros in a 32 bit variable. + * + * @param[in] ulBitmap 32-Bit number to count leading zeros in. + * + * @return The number of leading zeros in ulBitmap. + */ +UBaseType_t ulPortCountLeadingZeros( UBaseType_t ulBitmap ); + +/* If configUSE_TASK_FPU_SUPPORT is set to 1 (or left undefined) then tasks are + * created without an FPU context and must call vPortTaskUsesFPU() to give + * themselves an FPU context before using any FPU instructions. If + * configUSE_TASK_FPU_SUPPORT is set to 2 then all tasks will have an FPU + * context by default. */ +#if ( configUSE_TASK_FPU_SUPPORT != 2 ) + void vPortTaskUsesFPU( void ); +#else + /* Each task has an FPU context already, so define this function as a + * no-op. */ + #define vPortTaskUsesFPU() +#endif +#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() + +#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL ) +#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL ) + +/* Architecture specific optimisations. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + + /* Store, clear and get the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxTopReadyPriority ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +#define portNOP() __asm volatile ( "NOP" ) +#define portINLINE __inline +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/ARM_STAR_MC3/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_STAR_MC3/non_secure/mpu_wrappers_v2_asm.c new file mode 100644 index 000000000..33410a0c3 --- /dev/null +++ b/portable/GCC/ARM_STAR_MC3/non_secure/mpu_wrappers_v2_asm.c @@ -0,0 +1,2056 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" +#include "event_groups.h" +#include "stream_buffer.h" +#include "mpu_prototypes.h" +#include "mpu_syscall_numbers.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( INCLUDE_xTaskDelayUntil == 1 ) + + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskDelayUntilImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskDelayUntil_Unpriv \n" + " MPU_xTaskDelayUntil_Priv: \n" + " b MPU_xTaskDelayUntilImpl \n" + " MPU_xTaskDelayUntil_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskAbortDelayImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskAbortDelay_Unpriv \n" + " MPU_xTaskAbortDelay_Priv: \n" + " b MPU_xTaskAbortDelayImpl \n" + " MPU_xTaskAbortDelay_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskDelay == 1 ) + + void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskDelayImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskDelay_Unpriv \n" + " MPU_vTaskDelay_Priv: \n" + " b MPU_vTaskDelayImpl \n" + " MPU_vTaskDelay_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskPriorityGet == 1 ) + + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskPriorityGetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskPriorityGet_Unpriv \n" + " MPU_uxTaskPriorityGet_Priv: \n" + " b MPU_uxTaskPriorityGetImpl \n" + " MPU_uxTaskPriorityGet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_eTaskGetState == 1 ) + + eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_eTaskGetStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_eTaskGetState_Unpriv \n" + " MPU_eTaskGetState_Priv: \n" + " b MPU_eTaskGetStateImpl \n" + " MPU_eTaskGetState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory" + ); + } + + #endif /* if ( INCLUDE_eTaskGetState == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskGetInfoImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskGetInfo_Unpriv \n" + " MPU_vTaskGetInfo_Priv: \n" + " b MPU_vTaskGetInfoImpl \n" + " MPU_vTaskGetInfo_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory" + ); + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) + + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetIdleTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetIdleTaskHandle_Unpriv \n" + " MPU_xTaskGetIdleTaskHandle_Priv: \n" + " b MPU_xTaskGetIdleTaskHandleImpl \n" + " MPU_xTaskGetIdleTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + + void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSuspendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSuspend_Unpriv \n" + " MPU_vTaskSuspend_Priv: \n" + " b MPU_vTaskSuspendImpl \n" + " MPU_vTaskSuspend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + + void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskResumeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskResume_Unpriv \n" + " MPU_vTaskResume_Priv: \n" + " b MPU_vTaskResumeImpl \n" + " MPU_vTaskResume_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + TickType_t MPU_xTaskGetTickCount( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetTickCountImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetTickCount_Unpriv \n" + " MPU_xTaskGetTickCount_Priv: \n" + " b MPU_xTaskGetTickCountImpl \n" + " MPU_xTaskGetTickCount_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetNumberOfTasksImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetNumberOfTasks_Unpriv \n" + " MPU_uxTaskGetNumberOfTasks_Priv: \n" + " b MPU_uxTaskGetNumberOfTasksImpl \n" + " MPU_uxTaskGetNumberOfTasks_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetRunTimeCounterImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetRunTimeCounter_Unpriv \n" + " MPU_ulTaskGetRunTimeCounter_Priv: \n" + " b MPU_ulTaskGetRunTimeCounterImpl \n" + " MPU_ulTaskGetRunTimeCounter_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetRunTimePercentImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetRunTimePercent_Unpriv \n" + " MPU_ulTaskGetRunTimePercent_Priv: \n" + " b MPU_ulTaskGetRunTimePercentImpl \n" + " MPU_ulTaskGetRunTimePercent_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetIdleRunTimePercentImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv \n" + " MPU_ulTaskGetIdleRunTimePercent_Priv: \n" + " b MPU_ulTaskGetIdleRunTimePercentImpl \n" + " MPU_ulTaskGetIdleRunTimePercent_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetIdleRunTimeCounterImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv \n" + " MPU_ulTaskGetIdleRunTimeCounter_Priv: \n" + " b MPU_ulTaskGetIdleRunTimeCounterImpl \n" + " MPU_ulTaskGetIdleRunTimeCounter_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetApplicationTaskTagImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetApplicationTaskTag_Unpriv \n" + " MPU_vTaskSetApplicationTaskTag_Priv: \n" + " b MPU_vTaskSetApplicationTaskTagImpl \n" + " MPU_vTaskSetApplicationTaskTag_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory" + ); + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetApplicationTaskTagImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetApplicationTaskTag_Unpriv \n" + " MPU_xTaskGetApplicationTaskTag_Priv: \n" + " b MPU_xTaskGetApplicationTaskTagImpl \n" + " MPU_xTaskGetApplicationTaskTag_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory" + ); + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetThreadLocalStoragePointerImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv \n" + " MPU_vTaskSetThreadLocalStoragePointer_Priv: \n" + " b MPU_vTaskSetThreadLocalStoragePointerImpl \n" + " MPU_vTaskSetThreadLocalStoragePointer_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory" + ); + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv \n" + " MPU_pvTaskGetThreadLocalStoragePointer_Priv: \n" + " b MPU_pvTaskGetThreadLocalStoragePointerImpl \n" + " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory" + ); + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetSystemStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetSystemState_Unpriv \n" + " MPU_uxTaskGetSystemState_Priv: \n" + " b MPU_uxTaskGetSystemStateImpl \n" + " MPU_uxTaskGetSystemState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory" + ); + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) + + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetStackHighWaterMarkImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetStackHighWaterMark_Unpriv \n" + " MPU_uxTaskGetStackHighWaterMark_Priv: \n" + " b MPU_uxTaskGetStackHighWaterMarkImpl \n" + " MPU_uxTaskGetStackHighWaterMark_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetStackHighWaterMark2Impl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv \n" + " MPU_uxTaskGetStackHighWaterMark2_Priv: \n" + " b MPU_uxTaskGetStackHighWaterMark2Impl \n" + " MPU_uxTaskGetStackHighWaterMark2_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) + + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetCurrentTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetCurrentTaskHandle_Unpriv \n" + " MPU_xTaskGetCurrentTaskHandle_Priv: \n" + " b MPU_xTaskGetCurrentTaskHandleImpl \n" + " MPU_xTaskGetCurrentTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory" + ); + } + + #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetSchedulerState == 1 ) + + BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetSchedulerStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetSchedulerState_Unpriv \n" + " MPU_xTaskGetSchedulerState_Priv: \n" + " b MPU_xTaskGetSchedulerStateImpl \n" + " MPU_xTaskGetSchedulerState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */ +/*-----------------------------------------------------------*/ + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetTimeOutStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetTimeOutState_Unpriv \n" + " MPU_vTaskSetTimeOutState_Priv: \n" + " b MPU_vTaskSetTimeOutStateImpl \n" + " MPU_vTaskSetTimeOutState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskCheckForTimeOutImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskCheckForTimeOut_Unpriv \n" + " MPU_xTaskCheckForTimeOut_Priv: \n" + " b MPU_xTaskCheckForTimeOutImpl \n" + " MPU_xTaskCheckForTimeOut_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotify_Unpriv \n" + " MPU_xTaskGenericNotify_Priv: \n" + " b MPU_xTaskGenericNotifyImpl \n" + " MPU_xTaskGenericNotify_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyWaitImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotifyWait_Unpriv \n" + " MPU_xTaskGenericNotifyWait_Priv: \n" + " b MPU_xTaskGenericNotifyWaitImpl \n" + " MPU_xTaskGenericNotifyWait_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGenericNotifyTakeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGenericNotifyTake_Unpriv \n" + " MPU_ulTaskGenericNotifyTake_Priv: \n" + " b MPU_ulTaskGenericNotifyTakeImpl \n" + " MPU_ulTaskGenericNotifyTake_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyStateClearImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotifyStateClear_Unpriv \n" + " MPU_xTaskGenericNotifyStateClear_Priv: \n" + " b MPU_xTaskGenericNotifyStateClearImpl \n" + " MPU_xTaskGenericNotifyStateClear_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGenericNotifyValueClearImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGenericNotifyValueClear_Unpriv \n" + " MPU_ulTaskGenericNotifyValueClear_Priv: \n" + " b MPU_ulTaskGenericNotifyValueClearImpl \n" + " MPU_ulTaskGenericNotifyValueClear_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGenericSendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGenericSend_Unpriv \n" + " MPU_xQueueGenericSend_Priv: \n" + " b MPU_xQueueGenericSendImpl \n" + " MPU_xQueueGenericSend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxQueueMessagesWaitingImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxQueueMessagesWaiting_Unpriv \n" + " MPU_uxQueueMessagesWaiting_Priv: \n" + " b MPU_uxQueueMessagesWaitingImpl \n" + " MPU_uxQueueMessagesWaiting_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxQueueSpacesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxQueueSpacesAvailable_Unpriv \n" + " MPU_uxQueueSpacesAvailable_Priv: \n" + " b MPU_uxQueueSpacesAvailableImpl \n" + " MPU_uxQueueSpacesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueReceiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueReceive_Unpriv \n" + " MPU_xQueueReceive_Priv: \n" + " b MPU_xQueueReceiveImpl \n" + " MPU_xQueueReceive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueuePeekImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueuePeek_Unpriv \n" + " MPU_xQueuePeek_Priv: \n" + " b MPU_xQueuePeekImpl \n" + " MPU_xQueuePeek_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueSemaphoreTakeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueSemaphoreTake_Unpriv \n" + " MPU_xQueueSemaphoreTake_Priv: \n" + " b MPU_xQueueSemaphoreTakeImpl \n" + " MPU_xQueueSemaphoreTake_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) + + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGetMutexHolderImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGetMutexHolder_Unpriv \n" + " MPU_xQueueGetMutexHolder_Priv: \n" + " b MPU_xQueueGetMutexHolderImpl \n" + " MPU_xQueueGetMutexHolder_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory" + ); + } + + #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueTakeMutexRecursiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueTakeMutexRecursive_Unpriv \n" + " MPU_xQueueTakeMutexRecursive_Priv: \n" + " b MPU_xQueueTakeMutexRecursiveImpl \n" + " MPU_xQueueTakeMutexRecursive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory" + ); + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGiveMutexRecursiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGiveMutexRecursive_Unpriv \n" + " MPU_xQueueGiveMutexRecursive_Priv: \n" + " b MPU_xQueueGiveMutexRecursiveImpl \n" + " MPU_xQueueGiveMutexRecursive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory" + ); + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueSelectFromSetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueSelectFromSet_Unpriv \n" + " MPU_xQueueSelectFromSet_Priv: \n" + " b MPU_xQueueSelectFromSetImpl \n" + " MPU_xQueueSelectFromSet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory" + ); + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueAddToSetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueAddToSet_Unpriv \n" + " MPU_xQueueAddToSet_Priv: \n" + " b MPU_xQueueAddToSetImpl \n" + " MPU_xQueueAddToSet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory" + ); + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vQueueAddToRegistryImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vQueueAddToRegistry_Unpriv \n" + " MPU_vQueueAddToRegistry_Priv: \n" + " b MPU_vQueueAddToRegistryImpl \n" + " MPU_vQueueAddToRegistry_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vQueueUnregisterQueueImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vQueueUnregisterQueue_Unpriv \n" + " MPU_vQueueUnregisterQueue_Priv: \n" + " b MPU_vQueueUnregisterQueueImpl \n" + " MPU_vQueueUnregisterQueue_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pcQueueGetNameImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pcQueueGetName_Unpriv \n" + " MPU_pcQueueGetName_Priv: \n" + " b MPU_pcQueueGetNameImpl \n" + " MPU_pcQueueGetName_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pvTimerGetTimerIDImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pvTimerGetTimerID_Unpriv \n" + " MPU_pvTimerGetTimerID_Priv: \n" + " b MPU_pvTimerGetTimerIDImpl \n" + " MPU_pvTimerGetTimerID_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTimerSetTimerIDImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTimerSetTimerID_Unpriv \n" + " MPU_vTimerSetTimerID_Priv: \n" + " b MPU_vTimerSetTimerIDImpl \n" + " MPU_vTimerSetTimerID_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerIsTimerActiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerIsTimerActive_Unpriv \n" + " MPU_xTimerIsTimerActive_Priv: \n" + " b MPU_xTimerIsTimerActiveImpl \n" + " MPU_xTimerIsTimerActive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv \n" + " MPU_xTimerGetTimerDaemonTaskHandle_Priv: \n" + " b MPU_xTimerGetTimerDaemonTaskHandleImpl \n" + " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGenericCommandFromTaskImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGenericCommandFromTask_Unpriv \n" + " MPU_xTimerGenericCommandFromTask_Priv: \n" + " b MPU_xTimerGenericCommandFromTaskImpl \n" + " MPU_xTimerGenericCommandFromTask_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pcTimerGetNameImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pcTimerGetName_Unpriv \n" + " MPU_pcTimerGetName_Priv: \n" + " b MPU_pcTimerGetNameImpl \n" + " MPU_pcTimerGetName_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTimerSetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTimerSetReloadMode_Unpriv \n" + " MPU_vTimerSetReloadMode_Priv: \n" + " b MPU_vTimerSetReloadModeImpl \n" + " MPU_vTimerSetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetReloadMode_Unpriv \n" + " MPU_xTimerGetReloadMode_Priv: \n" + " b MPU_xTimerGetReloadModeImpl \n" + " MPU_xTimerGetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTimerGetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTimerGetReloadMode_Unpriv \n" + " MPU_uxTimerGetReloadMode_Priv: \n" + " b MPU_uxTimerGetReloadModeImpl \n" + " MPU_uxTimerGetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetPeriodImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetPeriod_Unpriv \n" + " MPU_xTimerGetPeriod_Priv: \n" + " b MPU_xTimerGetPeriodImpl \n" + " MPU_xTimerGetPeriod_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetExpiryTimeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetExpiryTime_Unpriv \n" + " MPU_xTimerGetExpiryTime_Priv: \n" + " b MPU_xTimerGetExpiryTimeImpl \n" + " MPU_xTimerGetExpiryTime_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupWaitBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupWaitBits_Unpriv \n" + " MPU_xEventGroupWaitBits_Priv: \n" + " b MPU_xEventGroupWaitBitsImpl \n" + " MPU_xEventGroupWaitBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupClearBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupClearBits_Unpriv \n" + " MPU_xEventGroupClearBits_Priv: \n" + " b MPU_xEventGroupClearBitsImpl \n" + " MPU_xEventGroupClearBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupSetBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupSetBits_Unpriv \n" + " MPU_xEventGroupSetBits_Priv: \n" + " b MPU_xEventGroupSetBitsImpl \n" + " MPU_xEventGroupSetBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ + +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupSyncImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupSync_Unpriv \n" + " MPU_xEventGroupSync_Priv: \n" + " b MPU_xEventGroupSyncImpl \n" + " MPU_xEventGroupSync_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxEventGroupGetNumberImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxEventGroupGetNumber_Unpriv \n" + " MPU_uxEventGroupGetNumber_Priv: \n" + " b MPU_uxEventGroupGetNumberImpl \n" + " MPU_uxEventGroupGetNumber_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory" + ); + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vEventGroupSetNumberImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vEventGroupSetNumber_Unpriv \n" + " MPU_vEventGroupSetNumber_Priv: \n" + " b MPU_vEventGroupSetNumberImpl \n" + " MPU_vEventGroupSetNumber_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory" + ); + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferSend_Unpriv \n" + " MPU_xStreamBufferSend_Priv: \n" + " b MPU_xStreamBufferSendImpl \n" + " MPU_xStreamBufferSend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferReceiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferReceive_Unpriv \n" + " MPU_xStreamBufferReceive_Priv: \n" + " b MPU_xStreamBufferReceiveImpl \n" + " MPU_xStreamBufferReceive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferIsFullImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferIsFull_Unpriv \n" + " MPU_xStreamBufferIsFull_Priv: \n" + " b MPU_xStreamBufferIsFullImpl \n" + " MPU_xStreamBufferIsFull_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferIsEmptyImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferIsEmpty_Unpriv \n" + " MPU_xStreamBufferIsEmpty_Priv: \n" + " b MPU_xStreamBufferIsEmptyImpl \n" + " MPU_xStreamBufferIsEmpty_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSpacesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferSpacesAvailable_Unpriv \n" + " MPU_xStreamBufferSpacesAvailable_Priv: \n" + " b MPU_xStreamBufferSpacesAvailableImpl \n" + " MPU_xStreamBufferSpacesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferBytesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferBytesAvailable_Unpriv \n" + " MPU_xStreamBufferBytesAvailable_Priv: \n" + " b MPU_xStreamBufferBytesAvailableImpl \n" + " MPU_xStreamBufferBytesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSetTriggerLevelImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferSetTriggerLevel_Unpriv \n" + " MPU_xStreamBufferSetTriggerLevel_Priv: \n" + " b MPU_xStreamBufferSetTriggerLevelImpl \n" + " MPU_xStreamBufferSetTriggerLevel_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferNextMessageLengthBytesImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv \n" + " MPU_xStreamBufferNextMessageLengthBytes_Priv: \n" + " b MPU_xStreamBufferNextMessageLengthBytesImpl \n" + " MPU_xStreamBufferNextMessageLengthBytes_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ diff --git a/portable/GCC/ARM_STAR_MC3/non_secure/port.c b/portable/GCC/ARM_STAR_MC3/non_secure/port.c new file mode 100644 index 000000000..76d2b2445 --- /dev/null +++ b/portable/GCC/ARM_STAR_MC3/non_secure/port.c @@ -0,0 +1,2280 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024-2025 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU includes. */ +#include "mpu_wrappers.h" +#include "mpu_syscall_numbers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration settings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to check the validity of an interrupt priority. + */ +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) ) +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used during system call enter and exit. + */ +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Offsets in the stack to the parameters when inside the SVC handler. + */ +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +#if ( portARMV8M_MINOR_VERSION >= 1 ) + + /* Enable Privileged eXecute Never MPU attribute for the selected memory + * region. */ + #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL ) +#endif /* portARMV8M_MINOR_VERSION >= 1 */ + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Extract first address of the MPU region as encoded in the + * RBAR (Region Base Address Register) value. */ +#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \ + ( ( rbar ) & portMPU_RBAR_ADDRESS_MASK ) + +/* Extract last address of the MPU region as encoded in the + * RLAR (Region Limit Address Register) value. */ +#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \ + ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK ) + +/* Does addr lies within [start, end] address range? */ +#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \ + ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) ) + +/* Is the access request satisfied by the available permissions? */ +#define portIS_AUTHORIZED( accessRequest, permissions ) \ + ( ( ( permissions ) & ( accessRequest ) ) == accessRequest ) + +/* Max value that fits in a uint32_t type. */ +#define portUINT32_MAX ( ~( ( uint32_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. + */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 + +/** + * @brief Constants required to check and configure PACBTI security feature implementation. + */ +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) ) + + #define portCONTROL_UPAC_EN ( 1UL << 7UL ) + #define portCONTROL_PAC_EN ( 1UL << 6UL ) + #define portCONTROL_UBTI_EN ( 1UL << 5UL ) + #define portCONTROL_BTI_EN ( 1UL << 4UL ) + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Extract MPU region's access permissions from the Region Base Address + * Register (RBAR) value. + * + * @param ulRBARValue RBAR value for the MPU region. + * + * @return uint32_t Access permissions. + */ + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + + /** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + /** + * @brief Configures PACBTI features. + * + * This function configures the Pointer Authentication, and Branch Target + * Identification security features as per the user configuration. It returns + * the value of the special purpose CONTROL register accordingly, and optionally + * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M + * architecture based) target supports PACBTI security feature. + * + * @param xWriteControlRegister Used to control whether the special purpose + * CONTROL register should be updated or not. + * + * @return CONTROL register value according to the configured PACBTI option. + */ + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the system call stack so that upon returning from + * SVC, the system call stack is used. + * + * @param pulTaskStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + * @param ucSystemCallNumber The system call number of the system call. + */ + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Raise SVC for exiting from a system call. + */ + void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief This variable is set to pdTRUE when the scheduler is started. + */ + PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + + /** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +/** + * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + /** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + + /** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + + /** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the cpsid instruction + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessPermissions = 0; + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_ONLY ) + { + ulAccessPermissions = tskMPU_READ_PERMISSION; + } + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_WRITE ) + { + ulAccessPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION ); + } + + return ulAccessPermissions; + } + +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } + +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ portOFFSET_TO_PC ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ]; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulSystemCallStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the system call section (i.e. application is + * not raising SVC directly). + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as + * it is non-NULL only during the execution of a system call (i.e. + * between system call enter and exit). + * 3. System call is not for a kernel API disabled by the configuration + * in FreeRTOSConfig.h. + * 4. We do not need to check that ucSystemCallNumber is within range + * because the assembly SVC handler checks that before calling + * this function. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) && + ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) ) + { + pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the system call stack for the stack frame. */ + pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulSystemCallStack[ i ] = pulTaskStack[ i ]; + } + + /* Store the value of the Link Register before the SVC was raised. + * It contains the address of the caller of the System Call entry + * point (i.e. the caller of the MPU_). We need to restore it + * when we exit from the system call. */ + pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; + + /* Store the value of the PSPLIM register before the SVC was raised. + * We need to restore it when we exit from the system call. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* Use the pulSystemCallStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif + + /* Start executing the system call upon returning from this handler. */ + pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; + + /* Raise a request to exit from the system call upon finishing the + * system call. */ + pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; + + /* Remember the location where we should copy the stack frame when we exit from + * the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize; + + /* Record if the hardware used padding to force the stack pointer + * to be double word aligned. */ + if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK ) + { + pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG; + } + else + { + pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG ); + } + + /* We ensure in pxPortInitialiseStack that the system call stack is + * double word aligned and therefore, there is no need of padding. + * Clear the bit[9] of stacked xPSR. */ + pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + + /* Raise the privilege for the duration of the system call. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " bics r0, r1 \n" /* Clear nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */ + { + __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulTaskStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the privileged code (i.e. application is not + * raising SVC directly). This SVC is only raised from + * vRequestSystemCallExit which is in the privileged code section. + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL - + * this means that we previously entered a system call and the + * application is not attempting to exit without entering a system + * call. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) ) + { + pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the task stack for the stack frame. */ + pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulTaskStack[ i ] = pulSystemCallStack[ i ]; + } + + /* Use the pulTaskStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) ); + + /* Return to the caller of the System Call entry point (i.e. the + * caller of the MPU_). */ + pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + /* Ensure that LR has a valid value.*/ + pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + + /* Restore the PSPLIM register to what it was at the time of + * system call entry. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* If the hardware used padding to force the stack pointer + * to be double word aligned, set the stacked xPSR bit[9], + * otherwise clear it. */ + if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG ) + { + pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK; + } + else + { + pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + } + + /* This is not NULL only for the duration of the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; + + /* Drop the privilege before returning to the thread mode. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " orrs r0, r1 \n" /* Set nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xTaskIsPrivileged = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xTaskIsPrivileged = pdTRUE; + } + + return xTaskIsPrivileged; + } + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged, + xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulIndex = 0; + uint32_t ulControl = 0x0; + + xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ + ulIndex++; + + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + ulIndex++; + + #if ( configENABLE_TRUSTZONE == 1 ) + { + xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */ + ulIndex++; + } + #endif /* configENABLE_TRUSTZONE */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + ulIndex++; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Check PACBTI security feature configuration before pushing the + * CONTROL register's value on task's TCB. */ + ulControl = prvConfigurePACBTI( pdFALSE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + if( xRunPrivileged == pdTRUE ) + { + xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + else + { + xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG ); + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ + ulIndex++; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + { + /* Ensure that the system call stack is double word aligned. */ + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) + + ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + /* This is not NULL only for the duration of a system call. */ + xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL; + } + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ]; + ulIndex++; + } + } + #endif /* configENABLE_PAC */ + + return &( xMPUSettings->ulContext[ ulIndex ] ); + } + +#else /* configENABLE_MPU */ + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ + { + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + pxTopOfStack--; + *pxTopOfStack = ulTaskPacKey[ i ]; + } + } + #endif /* configENABLE_PAC */ + + return pxTopOfStack; + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Set the CONTROL register value based on PACBTI security feature + * configuration before starting the first task. */ + ( void ) prvConfigurePACBTI( pdTRUE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + { + xSchedulerRunning = pdTRUE; + } + #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + configSTACK_DEPTH_TYPE uxStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( uxStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* PXN. */ + #if ( portARMV8M_MINOR_VERSION >= 1 ) + { + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ); + } + } + #endif /* portARMV8M_MINOR_VERSION >= 1 */ + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, + uint32_t ulBufferLength, + uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */ + + { + uint32_t i, ulBufferStartAddress, ulBufferEndAddress; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE ) + { + ulBufferStartAddress = ( uint32_t ) pvBuffer; + ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL ); + + for( i = 0; i < portTOTAL_NUM_REGIONS; i++ ) + { + /* Is the MPU region enabled? */ + if( ( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR & portMPU_RLAR_REGION_ENABLE ) == portMPU_RLAR_REGION_ENABLE ) + { + if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_AUTHORIZED( ulAccessRequested, + prvGetRegionAccessPermissions( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ) ) ) + { + xAccessGranted = pdTRUE; + break; + } + } + } + } + } + + return xAccessGranted; + } + +#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings; + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else + { + xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 ) + { + xAccessGranted = pdTRUE; + } + } + } + + return xAccessGranted; + } + + #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + ( void ) lInternalIndexOfKernelObject; + + /* If Access Control List feature is not used, all the tasks have + * access to all the kernel objects. */ + return pdTRUE; + } + + #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + { + uint32_t ulControl = 0x0; + + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); + + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; + + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_STAR_MC3/non_secure/portasm.c b/portable/GCC/ARM_STAR_MC3/non_secure/portasm.c new file mode 100644 index 000000000..0ebbe48a4 --- /dev/null +++ b/portable/GCC/ARM_STAR_MC3/non_secure/portasm.c @@ -0,0 +1,621 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION + * is defined correctly and privileged functions are placed in correct sections. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Portasm includes. */ +#include "portasm.h" + +/* System call numbers includes. */ +#include "mpu_syscall_numbers.h" + +/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the + * header files. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#if ( configENABLE_MPU == 1 ) + + void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " program_mpu_first_task: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r3] \n" /* r0 = pxCurrentTCB. */ + " \n" + " dmb \n" /* Complete outstanding transfers before disabling MPU. */ + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + " str r2, [r1] \n" /* Disable MPU. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */ + " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r1, [r2] \n" /* Program MAIR0. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " \n" + " movs r3, #4 \n" /* r3 = 4. */ + " str r3, [r1] \n" /* Program RNR = 4. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + " \n" + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " orr r2, #1 \n" /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */ + " str r2, [r1] \n" /* Enable MPU. */ + " dsb \n" /* Force memory writes before continuing. */ + " \n" + " restore_context_first_task: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* r1 = pxCurrentTCB.*/ + " ldr r2, [r1] \n" /* r2 = Location of saved context in TCB. */ + " \n" + " restore_special_regs_first_task: \n" + #if ( configENABLE_PAC == 1 ) + " ldmdb r2!, {r3-r6} \n" /* Read task's dedicated PAC key from the task's context. */ + " msr PAC_KEY_P_0, r3 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_1, r4 \n" + " msr PAC_KEY_P_2, r5 \n" + " msr PAC_KEY_P_3, r6 \n" + " clrm {r3-r6} \n" /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + " ldmdb r2!, {r0, r3-r5, lr} \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */ + " msr psp, r3 \n" + " msr psplim, r4 \n" + " msr control, r5 \n" + " ldr r4, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " str r0, [r4] \n" /* Restore xSecureContext. */ + " \n" + " restore_general_regs_first_task: \n" + " ldmdb r2!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */ + " stmia r3!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */ + " ldmdb r2!, {r4-r11} \n" /* r4-r11 restored. */ + " \n" + " restore_context_done_first_task: \n" + " str r2, [r1] \n" /* Save the location where the context should be saved next as the first member of TCB. */ + " mov r0, #0 \n" + " msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */ + " bx lr \n" + ); + } + +#else /* configENABLE_MPU */ + + void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r3, [r2] \n" /* Read pxCurrentTCB. */ + " ldr r0, [r3] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + " \n" + #if ( configENABLE_PAC == 1 ) + " ldmia r0!, {r1-r4} \n" /* Read task's dedicated PAC key from stack. */ + " msr PAC_KEY_P_3, r1 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_2, r2 \n" + " msr PAC_KEY_P_1, r3 \n" + " msr PAC_KEY_P_0, r4 \n" + " clrm {r1-r4} \n" /* Clear r1-r4. */ + #endif /* configENABLE_PAC */ + " \n" + " ldm r0!, {r1-r3} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */ + " ldr r4, =xSecureContext \n" + " str r1, [r4] \n" /* Set xSecureContext to this task's value for the same. */ + " msr psplim, r2 \n" /* Set this task's PSPLIM value. */ + " mrs r1, control \n" /* Obtain current control register value. */ + " orrs r1, r1, #2 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */ + " msr control, r1 \n" /* Write back the new control register value. */ + " adds r0, #32 \n" /* Discard everything up to r0. */ + " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */ + " isb \n" + " mov r0, #0 \n" + " msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */ + " bx r3 \n" /* Finally, branch to EXC_RETURN. */ + ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* r0 = CONTROL. */ + " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + " ite ne \n" + " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + " bx lr \n" /* Return. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* Read the CONTROL register. */ + " bic r0, #1 \n" /* Clear the bit 0. */ + " msr control, r0 \n" /* Write back the new CONTROL value. */ + " bx lr \n" /* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vResetPrivilege( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* r0 = CONTROL. */ + " orr r0, #1 \n" /* r0 = r0 | 1. */ + " msr control, r0 \n" /* CONTROL = r0. */ + " bx lr \n" /* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r0, =0xe000ed08 \n" /* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */ + " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */ + " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */ + " cpsie i \n" /* Globally enable interrupts. */ + " cpsie f \n" + " dsb \n" + " isb \n" + " svc %0 \n" /* System call to start the first task. */ + " nop \n" + ::"i" ( portSVC_START_SCHEDULER ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, basepri \n" /* r0 = basepri. Return original basepri value. */ + " mov r1, %0 \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r1 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bx lr \n" /* Return. */ + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " msr basepri, r0 \n" /* basepri = ulMask. */ + " dsb \n" + " isb \n" + " bx lr \n" /* Return. */ + ::: "memory" + ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern SecureContext_SaveContext \n" + " .extern SecureContext_LoadContext \n" + " \n" + " ldr r3, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " ldr r0, [r3] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */ + " ldr r2, [r1] \n" /* r2 = Location in TCB where the context should be saved. */ + " \n" + " cbz r0, save_ns_context \n" /* No secure context to save. */ + " save_s_context: \n" + " push {r0-r2, lr} \n" + " bl SecureContext_SaveContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r0-r2, lr} \n" + " \n" + " save_ns_context: \n" + " mov r3, lr \n" /* r3 = LR (EXC_RETURN). */ + " lsls r3, r3, #25 \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bmi save_special_regs \n" /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + " \n" + " save_general_regs: \n" + " mrs r3, psp \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " add r3, r3, #0x20 \n" /* Move r3 to location where s0 is saved. */ + " tst lr, #0x10 \n" + " ittt eq \n" + " vstmiaeq r2!, {s16-s31} \n" /* Store s16-s31. */ + " vldmiaeq r3, {s0-s16} \n" /* Copy hardware saved FP context into s0-s16. */ + " vstmiaeq r2!, {s0-s16} \n" /* Store hardware saved FP context. */ + " sub r3, r3, #0x20 \n" /* Set r3 back to the location of hardware saved context. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " stmia r2!, {r4-r11} \n" /* Store r4-r11. */ + " ldmia r3, {r4-r11} \n" /* Copy the hardware saved context into r4-r11. */ + " stmia r2!, {r4-r11} \n" /* Store the hardware saved context. */ + " \n" + " save_special_regs: \n" + " mrs r3, psp \n" /* r3 = PSP. */ + " mrs r4, psplim \n" /* r4 = PSPLIM. */ + " mrs r5, control \n" /* r5 = CONTROL. */ + " stmia r2!, {r0, r3-r5, lr} \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ + #if ( configENABLE_PAC == 1 ) + " mrs r3, PAC_KEY_P_0 \n" /* Read task's dedicated PAC key from the PAC key registers. */ + " mrs r4, PAC_KEY_P_1 \n" + " mrs r5, PAC_KEY_P_2 \n" + " mrs r6, PAC_KEY_P_3 \n" + " stmia r2!, {r3-r6} \n" /* Store the task's dedicated PAC key on the task's context. */ + " clrm {r3-r6} \n" /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + " str r2, [r1] \n" /* Save the location from where the context should be restored as the first member of TCB. */ + " \n" + " select_next_task: \n" + " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bl vTaskSwitchContext \n" + " mov r0, #0 \n" /* r0 = 0. */ + " msr basepri, r0 \n" /* Enable interrupts. */ + " \n" + " program_mpu: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r3] \n" /* r0 = pxCurrentTCB.*/ + " \n" + " dmb \n" /* Complete outstanding transfers before disabling MPU. */ + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + " str r2, [r1] \n" /* Disable MPU. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */ + " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r1, [r2] \n" /* Program MAIR0. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " \n" + " movs r3, #4 \n" /* r3 = 4. */ + " str r3, [r1] \n" /* Program RNR = 4. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + " \n" + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " orr r2, #1 \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */ + " str r2, [r1] \n" /* Enable MPU. */ + " dsb \n" /* Force memory writes before continuing. */ + " \n" + " restore_context: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* r1 = pxCurrentTCB.*/ + " ldr r2, [r1] \n" /* r2 = Location of saved context in TCB. */ + " \n" + " restore_special_regs: \n" + #if ( configENABLE_PAC == 1 ) + " ldmdb r2!, {r3-r6} \n" /* Read task's dedicated PAC key from the task's context. */ + " msr PAC_KEY_P_0, r3 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_1, r4 \n" + " msr PAC_KEY_P_2, r5 \n" + " msr PAC_KEY_P_3, r6 \n" + " clrm {r3-r6} \n" /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + " ldmdb r2!, {r0, r3-r5, lr} \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */ + " msr psp, r3 \n" + " msr psplim, r4 \n" + " msr control, r5 \n" + " ldr r4, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " str r0, [r4] \n" /* Restore xSecureContext. */ + " cbz r0, restore_ns_context \n" /* No secure context to restore. */ + " \n" + " restore_s_context: \n" + " push {r1-r3, lr} \n" + " bl SecureContext_LoadContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r1-r3, lr} \n" + " \n" + " restore_ns_context: \n" + " mov r0, lr \n" /* r0 = LR (EXC_RETURN). */ + " lsls r0, r0, #25 \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bmi restore_context_done \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + " \n" + " restore_general_regs: \n" + " ldmdb r2!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */ + " stmia r3!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */ + " ldmdb r2!, {r4-r11} \n" /* r4-r11 restored. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" + " ittt eq \n" + " vldmdbeq r2!, {s0-s16} \n" /* s0-s16 contain hardware saved FP context. */ + " vstmiaeq r3!, {s0-s16} \n" /* Copy hardware saved FP context on the task stack. */ + " vldmdbeq r2!, {s16-s31} \n" /* Restore s16-s31. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + " restore_context_done: \n" + " str r2, [r1] \n" /* Save the location where the context should be saved next as the first member of TCB. */ + " bx lr \n" + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); + } + +#else /* configENABLE_MPU */ + + void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern SecureContext_SaveContext \n" + " .extern SecureContext_LoadContext \n" + " \n" + " ldr r3, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " ldr r0, [r3] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */ + " mrs r2, psp \n" /* Read PSP in r2. */ + " \n" + " cbz r0, save_ns_context \n" /* No secure context to save. */ + " save_s_context: \n" + " push {r0-r2, lr} \n" + " bl SecureContext_SaveContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r0-r2, lr} \n" + " \n" + " save_ns_context: \n" + " mov r3, lr \n" /* r3 = LR (EXC_RETURN). */ + " lsls r3, r3, #25 \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bmi save_special_regs \n" /* If r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used. */ + " \n" + " save_general_regs: \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vstmdbeq r2!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " stmdb r2!, {r4-r11} \n" /* Store the registers that are not saved automatically. */ + " \n" + " save_special_regs: \n" + " mrs r3, psplim \n" /* r3 = PSPLIM. */ + " stmdb r2!, {r0, r3, lr} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */ + #if ( configENABLE_PAC == 1 ) + " mrs r3, PAC_KEY_P_3 \n" /* Read task's dedicated PAC key from the PAC key registers. */ + " mrs r4, PAC_KEY_P_2 \n" + " mrs r5, PAC_KEY_P_1 \n" + " mrs r6, PAC_KEY_P_0 \n" + " stmdb r2!, {r3-r6} \n" /* Store the task's dedicated PAC key on the stack. */ + " clrm {r3-r6} \n" /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + " \n" + " str r2, [r1] \n" /* Save the new top of stack in TCB. */ + " \n" + " select_next_task: \n" + " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bl vTaskSwitchContext \n" + " mov r0, #0 \n" /* r0 = 0. */ + " msr basepri, r0 \n" /* Enable interrupts. */ + " \n" + " restore_context: \n" + " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r3] \n" /* Read pxCurrentTCB. */ + " ldr r2, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */ + " \n" + " restore_special_regs: \n" + #if ( configENABLE_PAC == 1 ) + " ldmia r2!, {r3-r6} \n" /* Read task's dedicated PAC key from stack. */ + " msr PAC_KEY_P_3, r3 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_2, r4 \n" + " msr PAC_KEY_P_1, r5 \n" + " msr PAC_KEY_P_0, r6 \n" + " clrm {r3-r6} \n" /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + " ldmia r2!, {r0, r3, lr} \n" /* Read from stack - r0 = xSecureContext, r3 = PSPLIM and LR restored. */ + " msr psplim, r3 \n" /* Restore the PSPLIM register value for the task. */ + " ldr r3, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + " str r0, [r3] \n" /* Restore the task's xSecureContext. */ + " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */ + " \n" + " restore_s_context: \n" + " push {r1-r3, lr} \n" + " bl SecureContext_LoadContext \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + " pop {r1-r3, lr} \n" + " \n" + " restore_ns_context: \n" + " mov r0, lr \n" /* r0 = LR (EXC_RETURN). */ + " lsls r0, r0, #25 \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + " bmi restore_context_done \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + " \n" + " restore_general_regs: \n" + " ldmia r2!, {r4-r11} \n" /* Restore the registers that are not automatically restored. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vldmiaeq r2!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + " restore_context_done: \n" + " msr psp, r2 \n" /* Remember the new top of stack for the task. */ + " bx lr \n" + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + ".syntax unified \n" + ".extern vPortSVCHandler_C \n" + ".extern vSystemCallEnter \n" + ".extern vSystemCallExit \n" + " \n" + "tst lr, #4 \n" + "ite eq \n" + "mrseq r0, msp \n" + "mrsne r0, psp \n" + " \n" + "ldr r1, [r0, #24] \n" + "ldrb r2, [r1, #-2] \n" + "cmp r2, %0 \n" + "blt syscall_enter \n" + "cmp r2, %1 \n" + "beq syscall_exit \n" + "b vPortSVCHandler_C \n" + " \n" + "syscall_enter: \n" + " mov r1, lr \n" + " b vSystemCallEnter \n" + " \n" + "syscall_exit: \n" + " mov r1, lr \n" + " b vSystemCallExit \n" + " \n" + : /* No outputs. */ + : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT ) + : "r0", "r1", "r2", "memory" + ); + } + +#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " tst lr, #4 \n" + " ite eq \n" + " mrseq r0, msp \n" + " mrsne r0, psp \n" + " ldr r1, =vPortSVCHandler_C \n" + " bx r1 \n" + ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " svc %0 \n" /* Secure context is allocated in the supervisor call. */ + " bx lr \n" /* Return. */ + ::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, [r0] \n" /* The first item in the TCB is the top of the stack. */ + " ldr r1, [r2] \n" /* The first item on the stack is the task's xSecureContext. */ + " cmp r1, #0 \n" /* Raise svc if task's xSecureContext is not NULL. */ + " it ne \n" + " svcne %0 \n" /* Secure context is freed in the supervisor call. */ + " bx lr \n" /* Return. */ + ::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory" + ); +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_STAR_MC3/non_secure/portasm.h b/portable/GCC/ARM_STAR_MC3/non_secure/portasm.h new file mode 100644 index 000000000..b7021b024 --- /dev/null +++ b/portable/GCC/ARM_STAR_MC3/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kernel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/portable/GCC/ARM_STAR_MC3/non_secure/portmacro.h b/portable/GCC/ARM_STAR_MC3/non_secure/portmacro.h new file mode 100644 index 000000000..99538ef82 --- /dev/null +++ b/portable/GCC/ARM_STAR_MC3/non_secure/portmacro.h @@ -0,0 +1,80 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (c) 2026 Arm Technology (China) Co., Ltd.All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_MVE + #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE. +#endif /* configENABLE_MVE */ +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "STAR-MC3" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portARMV8M_MINOR_VERSION 1 +#define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/ARM_STAR_MC3/non_secure/portmacrocommon.h b/portable/GCC/ARM_STAR_MC3/non_secure/portmacrocommon.h new file mode 100644 index 000000000..f373bcad5 --- /dev/null +++ b/portable/GCC/ARM_STAR_MC3/non_secure/portmacrocommon.h @@ -0,0 +1,582 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACROCOMMON_H +#define PORTMACROCOMMON_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. +#endif /* configENABLE_FPU */ + +#ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. +#endif /* configENABLE_MPU */ + +#ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. +#endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() +#define portINLINE __inline +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif +#define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ +extern BaseType_t xPortIsInsideInterrupt( void ); + +extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + +extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; +extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + +extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; +extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + +#if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_PAC == 1 ) + + /** + * @brief Generates 128-bit task's random PAC key. + * + * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be + * filled with a 128-bit random number. + */ + void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); + +#endif /* configENABLE_PAC */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ +#if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) +#else + #define portPRIVILEGE_BIT ( 0x0UL ) +#endif /* configENABLE_MPU */ + +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ +#define portPRIVILEGED_FLASH_REGION ( 0UL ) +#define portUNPRIVILEGED_FLASH_REGION ( 1UL ) +#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) +#define portPRIVILEGED_RAM_REGION ( 3UL ) +#define portSTACK_REGION ( 4UL ) +#define portFIRST_CONFIGURABLE_REGION ( 5UL ) +#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) +#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) +#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ +#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ +#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ +#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ +#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ +#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ +#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ +#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) +#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) +#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + +#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) +#define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) +#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) +#define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + +#define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + #ifndef configSYSTEM_CALL_STACK_SIZE + #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. + #endif + + /** + * @brief System call stack. + */ + typedef struct SYSTEM_CALL_STACK_INFO + { + uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; + uint32_t * pulSystemCallStack; + uint32_t * pulSystemCallStackLimit; + uint32_t * pulTaskStack; + uint32_t ulLinkRegisterAtSystemCallEntry; + uint32_t ulStackLimitRegisterAtSystemCallEntry; + } xSYSTEM_CALL_STACK_INFO; + + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + /** + * @brief MPU settings as stored in the TCB. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><-----------><----> + * 16 17 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 71 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 17 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 55 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | | | PC, xPSR | EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><-----------><----> + * 16 17 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 70 + + #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + /* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 17 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 54 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+------------------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +----------+-----------------+------------------------------+------------+-----+ + * + * <---------><----------------><------------------------------><-----------><----> + * 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 38 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+----------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | PC, xPSR | EXC_RETURN | | | + * +----------+-----------------+----------------------+------------+-----+ + * + * <---------><----------------><----------------------><-----------><----> + * 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 37 + + #else /* #if( configENABLE_TRUSTZONE == 1 ) */ + + /* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) + + /* Size of an Access Control List (ACL) entry in bits. */ + #define portACL_ENTRY_SIZE_BITS ( 32U ) + + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + uint32_t ulContext[ MAX_CONTEXT_SIZE ]; + uint32_t ulTaskFlags; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo; + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ]; + #endif + #endif + } xMPU_SETTINGS; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Validate priority of ISRs that are allowed to call FreeRTOS + * system calls. + */ +#if ( configASSERT_DEFINED == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif +#endif + +/** + * @brief SVC numbers. + */ +#define portSVC_ALLOCATE_SECURE_CONTEXT 100 +#define portSVC_FREE_SECURE_CONTEXT 101 +#define portSVC_START_SCHEDULER 102 +#define portSVC_RAISE_PRIVILEGE 103 +#define portSVC_SYSTEM_CALL_EXIT 104 +#define portSVC_YIELD 105 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) +#endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() +#else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + extern BaseType_t xPortIsTaskPrivileged( void ); + +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACROCOMMON_H */ diff --git a/portable/GCC/ARM_STAR_MC3/secure/secure_context.c b/portable/GCC/ARM_STAR_MC3/secure/secure_context.c new file mode 100644 index 000000000..3aa335e63 --- /dev/null +++ b/portable/GCC/ARM_STAR_MC3/secure/secure_context.c @@ -0,0 +1,354 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Secure context includes. */ +#include "secure_context.h" + +/* Secure heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief CONTROL value for privileged tasks. + * + * Bit[0] - 0 --> Thread mode is privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_PRIVILEGED 0x02 + +/** + * @brief CONTROL value for un-privileged tasks. + * + * Bit[0] - 1 --> Thread mode is un-privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03 + +/** + * @brief Size of stack seal values in bytes. + */ +#define securecontextSTACK_SEAL_SIZE 8 + +/** + * @brief Stack seal value as recommended by ARM. + */ +#define securecontextSTACK_SEAL_VALUE 0xFEF5EDA5 + +/** + * @brief Maximum number of secure contexts. + */ +#ifndef secureconfigMAX_SECURE_CONTEXTS + #define secureconfigMAX_SECURE_CONTEXTS 8UL +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Pre-allocated array of secure contexts. + */ +SecureContext_t xSecureContexts[ secureconfigMAX_SECURE_CONTEXTS ]; +/*-----------------------------------------------------------*/ + +/** + * @brief Get a free secure context for a task from the secure context pool (xSecureContexts). + * + * This function ensures that only one secure context is allocated for a task. + * + * @param[in] pvTaskHandle The task handle for which the secure context is allocated. + * + * @return Index of a free secure context in the xSecureContexts array. + */ +static uint32_t ulGetSecureContext( void * pvTaskHandle ); + +/** + * @brief Return the secure context to the secure context pool (xSecureContexts). + * + * @param[in] ulSecureContextIndex Index of the context in the xSecureContexts array. + */ +static void vReturnSecureContext( uint32_t ulSecureContextIndex ); + +/* These are implemented in assembly. */ +extern void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ); +extern void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ); +/*-----------------------------------------------------------*/ + +static uint32_t ulGetSecureContext( void * pvTaskHandle ) +{ + /* Start with invalid index. */ + uint32_t i, ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + if( ( xSecureContexts[ i ].pucCurrentStackPointer == NULL ) && + ( xSecureContexts[ i ].pucStackLimit == NULL ) && + ( xSecureContexts[ i ].pucStackStart == NULL ) && + ( xSecureContexts[ i ].pvTaskHandle == NULL ) && + ( ulSecureContextIndex == secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = i; + } + else if( xSecureContexts[ i ].pvTaskHandle == pvTaskHandle ) + { + /* A task can only have one secure context. Do not allocate a second + * context for the same task. */ + ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + break; + } + } + + return ulSecureContextIndex; +} +/*-----------------------------------------------------------*/ + +static void vReturnSecureContext( uint32_t ulSecureContextIndex ) +{ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackStart = NULL; + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = NULL; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) +{ + uint32_t ulIPSR, i; + static uint32_t ulSecureContextsInitialized = 0; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ( ulIPSR != 0 ) && ( ulSecureContextsInitialized == 0 ) ) + { + /* Ensure to initialize secure contexts only once. */ + ulSecureContextsInitialized = 1; + + /* No stack for thread mode until a task's context is loaded. */ + secureportSET_PSPLIM( securecontextNO_STACK ); + secureportSET_PSP( securecontextNO_STACK ); + + /* Initialize all secure contexts. */ + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + xSecureContexts[ i ].pucCurrentStackPointer = NULL; + xSecureContexts[ i ].pucStackLimit = NULL; + xSecureContexts[ i ].pucStackStart = NULL; + xSecureContexts[ i ].pvTaskHandle = NULL; + } + + #if ( configENABLE_MPU == 1 ) + { + /* Configure thread mode to use PSP and to be unprivileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); + } + #else /* configENABLE_MPU */ + { + /* Configure thread mode to use PSP and to be privileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); + } + #endif /* configENABLE_MPU */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ) +#else /* configENABLE_MPU */ + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ) +#endif /* configENABLE_MPU */ +{ + uint8_t * pucStackMemory = NULL; + uint8_t * pucStackLimit; + uint32_t ulIPSR, ulSecureContextIndex; + SecureContextHandle_t xSecureContextHandle = securecontextINVALID_CONTEXT_ID; + + #if ( configENABLE_MPU == 1 ) + uint32_t * pulCurrentStackPointer = NULL; + #endif /* configENABLE_MPU */ + + /* Read the Interrupt Program Status Register (IPSR) and Process Stack Limit + * Register (PSPLIM) value. */ + secureportREAD_IPSR( ulIPSR ); + secureportREAD_PSPLIM( pucStackLimit ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. + * Also do nothing, if a secure context us already loaded. PSPLIM is set to + * securecontextNO_STACK when no secure context is loaded. */ + if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) ) + { + /* Obtain a free secure context. */ + ulSecureContextIndex = ulGetSecureContext( pvTaskHandle ); + + /* Were we able to get a free context? */ + if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS ) + { + /* Allocate the stack space. */ + pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + + if( pucStackMemory != NULL ) + { + /* Since stack grows down, the starting point will be the last + * location. Note that this location is next to the last + * allocated byte for stack (excluding the space for seal values) + * because the hardware decrements the stack pointer before + * writing i.e. if stack pointer is 0x2, a push operation will + * decrement the stack pointer to 0x1 and then write at 0x1. */ + xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize; + + /* Seal the created secure process stack. */ + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; + + /* The stack cannot go beyond this location. This value is + * programmed in the PSPLIM register on context switch.*/ + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = pucStackMemory; + + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle; + + #if ( configENABLE_MPU == 1 ) + { + /* Store the correct CONTROL value for the task on the stack. + * This value is programmed in the CONTROL register on + * context switch. */ + pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; + pulCurrentStackPointer--; + + if( ulIsTaskPrivileged ) + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; + } + else + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; + } + + /* Store the current stack pointer. This value is programmed in + * the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + } + #else /* configENABLE_MPU */ + { + /* Current SP is set to the starting of the stack. This + * value programmed in the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + } + #endif /* configENABLE_MPU */ + + /* Ensure to never return 0 as a valid context handle. */ + xSecureContextHandle = ulSecureContextIndex + 1UL; + } + } + } + + return xSecureContextHandle; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) +{ + uint32_t ulIPSR, ulSecureContextIndex; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* Only free if a valid context handle is passed. */ + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + /* Ensure that the secure context being deleted is associated with + * the task. */ + if( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) + { + /* Free the stack space. */ + vPortFree( xSecureContexts[ ulSecureContextIndex ].pucStackLimit ); + + /* Return the secure context back to the free secure contexts pool. */ + vReturnSecureContext( ulSecureContextIndex ); + } + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that no secure context is loaded and the task is loading it's + * own context. */ + if( ( pucStackLimit == securecontextNO_STACK ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_LoadContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that task's context is loaded and the task is saving it's own + * context. */ + if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_SaveContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_STAR_MC3/secure/secure_context.h b/portable/GCC/ARM_STAR_MC3/secure/secure_context.h new file mode 100644 index 000000000..e36a8e430 --- /dev/null +++ b/portable/GCC/ARM_STAR_MC3/secure/secure_context.h @@ -0,0 +1,138 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_CONTEXT_H__ +#define __SECURE_CONTEXT_H__ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" + +/** + * @brief PSP value when no secure context is loaded. + */ +#define securecontextNO_STACK 0x0 + +/** + * @brief Invalid context ID. + */ +#define securecontextINVALID_CONTEXT_ID 0UL +/*-----------------------------------------------------------*/ + +/** + * @brief Structure to represent a secure context. + * + * @note Since stack grows down, pucStackStart is the highest address while + * pucStackLimit is the first address of the allocated memory. + */ +typedef struct SecureContext +{ + uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */ + uint8_t * pucStackLimit; /**< Last location of the stack memory (PSPLIM). */ + uint8_t * pucStackStart; /**< First location of the stack memory. */ + void * pvTaskHandle; /**< Task handle of the task this context is associated with. */ +} SecureContext_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Opaque handle for a secure context. + */ +typedef uint32_t SecureContextHandle_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Initializes the secure context management system. + * + * PSP is set to NULL and therefore a task must allocate and load a context + * before calling any secure side function in the thread mode. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureContext_Init( void ); + +/** + * @brief Allocates a context on the secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] ulSecureStackSize Size of the stack to allocate on secure side. + * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise. + * + * @return Opaque context handle if context is successfully allocated, NULL + * otherwise. + */ +#if ( configENABLE_MPU == 1 ) + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ); +#else /* configENABLE_MPU */ + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ); +#endif /* configENABLE_MPU */ + +/** + * @brief Frees the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the + * context to be freed. + */ +void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); + +/** + * @brief Loads the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be loaded. + */ +void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); + +/** + * @brief Saves the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be saved. + */ +void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); + +#endif /* __SECURE_CONTEXT_H__ */ diff --git a/portable/GCC/ARM_STAR_MC3/secure/secure_context_port.c b/portable/GCC/ARM_STAR_MC3/secure/secure_context_port.c new file mode 100644 index 000000000..2d3d9439d --- /dev/null +++ b/portable/GCC/ARM_STAR_MC3/secure/secure_context_port.c @@ -0,0 +1,97 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Secure context includes. */ +#include "secure_context.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) ); +void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) ); + +void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) +{ + /* pxSecureContext value is in r0. */ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r1, ipsr \n" /* r1 = IPSR. */ + " cbz r1, load_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */ + " ldmia r0!, {r1, r2} \n" /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */ + " \n" + #if ( configENABLE_MPU == 1 ) + " ldmia r1!, {r3} \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */ + " msr control, r3 \n" /* CONTROL = r3. */ + #endif /* configENABLE_MPU */ + " \n" + " msr psplim, r2 \n" /* PSPLIM = r2. */ + " msr psp, r1 \n" /* PSP = r1. */ + " \n" + " load_ctx_therad_mode: \n" + " bx lr \n" + " \n" + ::: "r0", "r1", "r2" + ); +} +/*-----------------------------------------------------------*/ + +void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) +{ + /* pxSecureContext value is in r0. */ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r1, ipsr \n" /* r1 = IPSR. */ + " cbz r1, save_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */ + " mrs r1, psp \n" /* r1 = PSP. */ + " \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " vstmdb r1!, {s0} \n" /* Trigger the deferred stacking of FPU registers. */ + " vldmia r1!, {s0} \n" /* Nullify the effect of the previous statement. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + #if ( configENABLE_MPU == 1 ) + " mrs r2, control \n" /* r2 = CONTROL. */ + " stmdb r1!, {r2} \n" /* Store CONTROL value on the stack. */ + #endif /* configENABLE_MPU */ + " \n" + " str r1, [r0] \n" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */ + " movs r1, %0 \n" /* r1 = securecontextNO_STACK. */ + " msr psplim, r1 \n" /* PSPLIM = securecontextNO_STACK. */ + " msr psp, r1 \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */ + " \n" + " save_ctx_therad_mode: \n" + " bx lr \n" + " \n" + ::"i" ( securecontextNO_STACK ) : "r1", "memory" + ); +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_STAR_MC3/secure/secure_heap.c b/portable/GCC/ARM_STAR_MC3/secure/secure_heap.c new file mode 100644 index 000000000..896b53e2d --- /dev/null +++ b/portable/GCC/ARM_STAR_MC3/secure/secure_heap.c @@ -0,0 +1,485 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Configuration includes. */ +#include "FreeRTOSConfig.h" + +/* Secure context heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Total heap size. + */ +#ifndef secureconfigTOTAL_HEAP_SIZE + #define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) ) +#endif + +/* No test marker by default. */ +#ifndef mtCOVERAGE_TEST_MARKER + #define mtCOVERAGE_TEST_MARKER() +#endif + +/* No tracing by default. */ +#ifndef traceMALLOC + #define traceMALLOC( pvReturn, xWantedSize ) +#endif + +/* No tracing by default. */ +#ifndef traceFREE + #define traceFREE( pv, xBlockSize ) +#endif + +/* Block sizes must not get too small. */ +#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) ) + +/* Assumes 8bit bytes! */ +#define secureheapBITS_PER_BYTE ( ( size_t ) 8 ) + +/* Max value that fits in a size_t type. */ +#define secureheapSIZE_MAX ( ~( ( size_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define secureheapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) ) + +/* MSB of the xBlockSize member of an BlockLink_t structure is used to track + * the allocation status of a block. When MSB of the xBlockSize member of + * an BlockLink_t structure is set then the block belongs to the application. + * When the bit is free the block is still part of the free heap space. */ +#define secureheapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) ) +#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 ) +#define secureheapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 ) +#define secureheapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK ) +#define secureheapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK ) +/*-----------------------------------------------------------*/ + +/* Allocate the memory for the heap. */ +#if ( configAPPLICATION_ALLOCATED_HEAP == 1 ) + +/* The application writer has already defined the array used for the RTOS +* heap - probably so it can be placed in a special segment or address. */ + extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#else /* configAPPLICATION_ALLOCATED_HEAP */ + static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#endif /* configAPPLICATION_ALLOCATED_HEAP */ + +/** + * @brief The linked list structure. + * + * This is used to link free blocks in order of their memory address. + */ +typedef struct A_BLOCK_LINK +{ + struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */ + size_t xBlockSize; /**< The size of the free block. */ +} BlockLink_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Called automatically to setup the required heap structures the first + * time pvPortMalloc() is called. + */ +static void prvHeapInit( void ); + +/** + * @brief Inserts a block of memory that is being freed into the correct + * position in the list of free memory blocks. + * + * The block being freed will be merged with the block in front it and/or the + * block behind it if the memory blocks are adjacent to each other. + * + * @param[in] pxBlockToInsert The block being freed. + */ +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ); +/*-----------------------------------------------------------*/ + +/** + * @brief The size of the structure placed at the beginning of each allocated + * memory block must by correctly byte aligned. + */ +static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + +/** + * @brief Create a couple of list links to mark the start and end of the list. + */ +static BlockLink_t xStart; +static BlockLink_t * pxEnd = NULL; + +/** + * @brief Keeps track of the number of free bytes remaining, but says nothing + * about fragmentation. + */ +static size_t xFreeBytesRemaining = 0U; +static size_t xMinimumEverFreeBytesRemaining = 0U; + +/*-----------------------------------------------------------*/ + +static void prvHeapInit( void ) +{ + BlockLink_t * pxFirstFreeBlock; + uint8_t * pucAlignedHeap; + size_t uxAddress; + size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE; + + /* Ensure the heap starts on a correctly aligned boundary. */ + uxAddress = ( size_t ) ucHeap; + + if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 ) + { + uxAddress += ( secureportBYTE_ALIGNMENT - 1 ); + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; + } + + pucAlignedHeap = ( uint8_t * ) uxAddress; + + /* xStart is used to hold a pointer to the first item in the list of free + * blocks. The void cast is used to prevent compiler warnings. */ + xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; + xStart.xBlockSize = ( size_t ) 0; + + /* pxEnd is used to mark the end of the list of free blocks and is inserted + * at the end of the heap space. */ + uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; + uxAddress -= xHeapStructSize; + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + pxEnd = ( void * ) uxAddress; + pxEnd->xBlockSize = 0; + pxEnd->pxNextFreeBlock = NULL; + + /* To start with there is a single free block that is sized to take up the + * entire heap space, minus the space taken by pxEnd. */ + pxFirstFreeBlock = ( void * ) pucAlignedHeap; + pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; + pxFirstFreeBlock->pxNextFreeBlock = pxEnd; + + /* Only one block exists - and it covers the entire usable heap space. */ + xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; +} +/*-----------------------------------------------------------*/ + +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) +{ + BlockLink_t * pxIterator; + uint8_t * puc; + + /* Iterate through the list until a block is found that has a higher address + * than the block being inserted. */ + for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) + { + /* Nothing to do here, just iterate to the right position. */ + } + + /* Do the block being inserted, and the block it is being inserted after + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxIterator; + + if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) + { + pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; + pxBlockToInsert = pxIterator; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Do the block being inserted, and the block it is being inserted before + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxBlockToInsert; + + if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) + { + if( pxIterator->pxNextFreeBlock != pxEnd ) + { + /* Form one big block from the two blocks. */ + pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxEnd; + } + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; + } + + /* If the block being inserted plugged a gap, so was merged with the block + * before and the block after, then it's pxNextFreeBlock pointer will have + * already been set, and should not be set here as that would make it point + * to itself. */ + if( pxIterator != pxBlockToInsert ) + { + pxIterator->pxNextFreeBlock = pxBlockToInsert; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} +/*-----------------------------------------------------------*/ + +void * pvPortMalloc( size_t xWantedSize ) +{ + BlockLink_t * pxBlock; + BlockLink_t * pxPreviousBlock; + BlockLink_t * pxNewBlockLink; + void * pvReturn = NULL; + size_t xAdditionalRequiredSize; + size_t xAllocatedBlockSize = 0; + + /* If this is the first call to malloc then the heap will require + * initialisation to setup the list of free blocks. */ + if( pxEnd == NULL ) + { + prvHeapInit(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xWantedSize > 0 ) + { + /* The wanted size must be increased so it can contain a BlockLink_t + * structure in addition to the requested amount of bytes. */ + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 ) + { + xWantedSize += xHeapStructSize; + + /* Ensure that blocks are always aligned to the required number + * of bytes. */ + if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 ) + { + /* Byte alignment required. */ + xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ); + + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 ) + { + xWantedSize += xAdditionalRequiredSize; + } + else + { + xWantedSize = 0; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + xWantedSize = 0; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Check the requested block size is not so large that the top bit is set. + * The top bit of the block size member of the BlockLink_t structure is used + * to determine who owns the block - the application or the kernel, so it + * must be free. */ + if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 ) + { + if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) + { + /* Traverse the list from the start (lowest address) block until + * one of adequate size is found. */ + pxPreviousBlock = &xStart; + pxBlock = xStart.pxNextFreeBlock; + + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + { + pxPreviousBlock = pxBlock; + pxBlock = pxBlock->pxNextFreeBlock; + } + + /* If the end marker was reached then a block of adequate size was + * not found. */ + if( pxBlock != pxEnd ) + { + /* Return the memory space pointed to - jumping over the + * BlockLink_t structure at its start. */ + pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); + + /* This block is being returned for use so must be taken out + * of the list of free blocks. */ + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + + /* If the block is larger than required it can be split into + * two. */ + if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE ) + { + /* This block is to be split into two. Create a new + * block following the number of bytes requested. The void + * cast is used to prevent byte alignment warnings from the + * compiler. */ + pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); + secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + + /* Calculate the sizes of two blocks split from the single + * block. */ + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + pxBlock->xBlockSize = xWantedSize; + + /* Insert the new block into the list of free blocks. */ + pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock; + pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xFreeBytesRemaining -= pxBlock->xBlockSize; + + if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) + { + xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xAllocatedBlockSize = pxBlock->xBlockSize; + + /* The block is being returned - it is allocated and owned by + * the application and has no "next" block. */ + secureheapALLOCATE_BLOCK( pxBlock ); + pxBlock->pxNextFreeBlock = NULL; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceMALLOC( pvReturn, xAllocatedBlockSize ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xAllocatedBlockSize; + + #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) + { + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */ + + secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 ); + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void * pv ) +{ + uint8_t * puc = ( uint8_t * ) pv; + BlockLink_t * pxLink; + + if( pv != NULL ) + { + /* The memory being freed will have an BlockLink_t structure immediately + * before it. */ + puc -= xHeapStructSize; + + /* This casting is to keep the compiler from issuing warnings. */ + pxLink = ( void * ) puc; + + /* Check the block is actually allocated. */ + secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ); + secureportASSERT( pxLink->pxNextFreeBlock == NULL ); + + if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ) + { + if( pxLink->pxNextFreeBlock == NULL ) + { + /* The block is being returned to the heap - it is no longer + * allocated. */ + secureheapFREE_BLOCK( pxLink ); + + secureportDISABLE_NON_SECURE_INTERRUPTS(); + { + /* Add this block to the list of free blocks. */ + xFreeBytesRemaining += pxLink->xBlockSize; + traceFREE( pv, pxLink->xBlockSize ); + prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); + } + secureportENABLE_NON_SECURE_INTERRUPTS(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } +} +/*-----------------------------------------------------------*/ + +size_t xPortGetFreeHeapSize( void ) +{ + return xFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +size_t xPortGetMinimumEverFreeHeapSize( void ) +{ + return xMinimumEverFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_STAR_MC3/secure/secure_heap.h b/portable/GCC/ARM_STAR_MC3/secure/secure_heap.h new file mode 100644 index 000000000..0e84a9d9d --- /dev/null +++ b/portable/GCC/ARM_STAR_MC3/secure/secure_heap.h @@ -0,0 +1,66 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_HEAP_H__ +#define __SECURE_HEAP_H__ + +/* Standard includes. */ +#include + +/** + * @brief Allocates memory from heap. + * + * @param[in] xWantedSize The size of the memory to be allocated. + * + * @return Pointer to the memory region if the allocation is successful, NULL + * otherwise. + */ +void * pvPortMalloc( size_t xWantedSize ); + +/** + * @brief Frees the previously allocated memory. + * + * @param[in] pv Pointer to the memory to be freed. + */ +void vPortFree( void * pv ); + +/** + * @brief Get the free heap size. + * + * @return Free heap size. + */ +size_t xPortGetFreeHeapSize( void ); + +/** + * @brief Get the minimum ever free heap size. + * + * @return Minimum ever free heap size. + */ +size_t xPortGetMinimumEverFreeHeapSize( void ); + +#endif /* __SECURE_HEAP_H__ */ diff --git a/portable/GCC/ARM_STAR_MC3/secure/secure_init.c b/portable/GCC/ARM_STAR_MC3/secure/secure_init.c new file mode 100644 index 000000000..c50d37668 --- /dev/null +++ b/portable/GCC/ARM_STAR_MC3/secure/secure_init.c @@ -0,0 +1,106 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Secure init includes. */ +#include "secure_init.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Constants required to manipulate the SCB. + */ +#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */ +#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL ) +#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS ) +#define secureinitSCB_AIRCR_PRIS_POS ( 14UL ) +#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS ) + +/** + * @brief Constants required to manipulate the FPU. + */ +#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define secureinitFPCCR_LSPENS_POS ( 29UL ) +#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS ) +#define secureinitFPCCR_TS_POS ( 26UL ) +#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS ) + +#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */ +#define secureinitNSACR_CP10_POS ( 10UL ) +#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS ) +#define secureinitNSACR_CP11_POS ( 11UL ) +#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS ) +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) | + ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) | + ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK ); + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is + * permitted. CP11 should be programmed to the same value as CP10. */ + *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK ); + + /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures + * that we can enable/disable lazy stacking in port.c file. */ + *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK ); + + /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP + * registers (S16-S31) are also pushed to stack on exception entry and + * restored on exception return. */ + *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK ); + } +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_STAR_MC3/secure/secure_init.h b/portable/GCC/ARM_STAR_MC3/secure/secure_init.h new file mode 100644 index 000000000..ebe04900f --- /dev/null +++ b/portable/GCC/ARM_STAR_MC3/secure/secure_init.h @@ -0,0 +1,54 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_INIT_H__ +#define __SECURE_INIT_H__ + +/** + * @brief De-prioritizes the non-secure exceptions. + * + * This is needed to ensure that the non-secure PendSV runs at the lowest + * priority. Context switch is done in the non-secure PendSV handler. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_DePrioritizeNSExceptions( void ); + +/** + * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access. + * + * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point + * Registers are not leaked to the non-secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_EnableNSFPUAccess( void ); + +#endif /* __SECURE_INIT_H__ */ diff --git a/portable/GCC/ARM_STAR_MC3/secure/secure_port_macros.h b/portable/GCC/ARM_STAR_MC3/secure/secure_port_macros.h new file mode 100644 index 000000000..a70da2c65 --- /dev/null +++ b/portable/GCC/ARM_STAR_MC3/secure/secure_port_macros.h @@ -0,0 +1,140 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_PORT_MACROS_H__ +#define __SECURE_PORT_MACROS_H__ + +/** + * @brief Byte alignment requirements. + */ +#define secureportBYTE_ALIGNMENT 8 +#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 ) + +/** + * @brief Macro to declare a function as non-secure callable. + */ +#if defined( __IAR_SYSTEMS_ICC__ ) + #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry __root +#else + #define secureportNON_SECURE_CALLABLE __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) ) +#endif + +/** + * @brief Set the secure PRIMASK value. + */ +#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Set the non-secure PRIMASK value. + */ +#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Read the PSP value in the given variable. + */ +#define secureportREAD_PSP( pucOutCurrentStackPointer ) \ + __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) ) + +/** + * @brief Set the PSP to the given value. + */ +#define secureportSET_PSP( pucCurrentStackPointer ) \ + __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) ) + +/** + * @brief Read the PSPLIM value in the given variable. + */ +#define secureportREAD_PSPLIM( pucOutStackLimit ) \ + __asm volatile ( "mrs %0, psplim" : "=r" ( pucOutStackLimit ) ) + +/** + * @brief Set the PSPLIM to the given value. + */ +#define secureportSET_PSPLIM( pucStackLimit ) \ + __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) ) + +/** + * @brief Set the NonSecure MSP to the given value. + */ +#define secureportSET_MSP_NS( pucMainStackPointer ) \ + __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) ) + +/** + * @brief Set the CONTROL register to the given value. + */ +#define secureportSET_CONTROL( ulControl ) \ + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" ) + +/** + * @brief Read the Interrupt Program Status Register (IPSR) value in the given + * variable. + */ +#define secureportREAD_IPSR( ulIPSR ) \ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) ) + +/** + * @brief PRIMASK value to enable interrupts. + */ +#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0 + +/** + * @brief PRIMASK value to disable interrupts. + */ +#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1 + +/** + * @brief Disable secure interrupts. + */ +#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Disable non-secure interrupts. + * + * This effectively disables context switches. + */ +#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Enable non-secure interrupts. + */ +#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL ) + +/** + * @brief Assert definition. + */ +#define secureportASSERT( x ) \ + if( ( x ) == 0 ) \ + { \ + secureportDISABLE_SECURE_INTERRUPTS(); \ + secureportDISABLE_NON_SECURE_INTERRUPTS(); \ + for( ; ; ) {; } \ + } + +#endif /* __SECURE_PORT_MACROS_H__ */ diff --git a/portable/GCC/ARM_STAR_MC3_NTZ/non_secure/mpu_wrappers_v2_asm.c b/portable/GCC/ARM_STAR_MC3_NTZ/non_secure/mpu_wrappers_v2_asm.c new file mode 100644 index 000000000..4b984932d --- /dev/null +++ b/portable/GCC/ARM_STAR_MC3_NTZ/non_secure/mpu_wrappers_v2_asm.c @@ -0,0 +1,2055 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" +#include "event_groups.h" +#include "stream_buffer.h" +#include "mpu_prototypes.h" +#include "mpu_syscall_numbers.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( INCLUDE_xTaskDelayUntil == 1 ) + + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskDelayUntilImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskDelayUntil_Unpriv \n" + " MPU_xTaskDelayUntil_Priv: \n" + " b MPU_xTaskDelayUntilImpl \n" + " MPU_xTaskDelayUntil_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskDelayUntil ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskAbortDelayImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskAbortDelay_Unpriv \n" + " MPU_xTaskAbortDelay_Priv: \n" + " b MPU_xTaskAbortDelayImpl \n" + " MPU_xTaskAbortDelay_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskAbortDelay ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskDelay == 1 ) + + void MPU_vTaskDelay( const TickType_t xTicksToDelay ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskDelayImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskDelay_Unpriv \n" + " MPU_vTaskDelay_Priv: \n" + " b MPU_vTaskDelayImpl \n" + " MPU_vTaskDelay_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskDelay ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskDelay == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskPriorityGet == 1 ) + + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskPriorityGetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskPriorityGet_Unpriv \n" + " MPU_uxTaskPriorityGet_Priv: \n" + " b MPU_uxTaskPriorityGetImpl \n" + " MPU_uxTaskPriorityGet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskPriorityGet ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_eTaskGetState == 1 ) + + eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_eTaskGetStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_eTaskGetState_Unpriv \n" + " MPU_eTaskGetState_Priv: \n" + " b MPU_eTaskGetStateImpl \n" + " MPU_eTaskGetState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_eTaskGetState ) : "memory" + ); + } + + #endif /* if ( INCLUDE_eTaskGetState == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskGetInfoImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskGetInfo_Unpriv \n" + " MPU_vTaskGetInfo_Priv: \n" + " b MPU_vTaskGetInfoImpl \n" + " MPU_vTaskGetInfo_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskGetInfo ) : "memory" + ); + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) + + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetIdleTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetIdleTaskHandle_Unpriv \n" + " MPU_xTaskGetIdleTaskHandle_Priv: \n" + " b MPU_xTaskGetIdleTaskHandleImpl \n" + " MPU_xTaskGetIdleTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetIdleTaskHandle ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + + void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSuspendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSuspend_Unpriv \n" + " MPU_vTaskSuspend_Priv: \n" + " b MPU_vTaskSuspendImpl \n" + " MPU_vTaskSuspend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSuspend ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_vTaskSuspend == 1 ) + + void MPU_vTaskResume( TaskHandle_t xTaskToResume ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskResumeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskResume_Unpriv \n" + " MPU_vTaskResume_Priv: \n" + " b MPU_vTaskResumeImpl \n" + " MPU_vTaskResume_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskResume ) : "memory" + ); + } + + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + + TickType_t MPU_xTaskGetTickCount( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTaskGetTickCount( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetTickCountImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetTickCount_Unpriv \n" + " MPU_xTaskGetTickCount_Priv: \n" + " b MPU_xTaskGetTickCountImpl \n" + " MPU_xTaskGetTickCount_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetTickCount ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetNumberOfTasksImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetNumberOfTasks_Unpriv \n" + " MPU_uxTaskGetNumberOfTasks_Priv: \n" + " b MPU_uxTaskGetNumberOfTasksImpl \n" + " MPU_uxTaskGetNumberOfTasks_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetNumberOfTasks ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetRunTimeCounterImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetRunTimeCounter_Unpriv \n" + " MPU_ulTaskGetRunTimeCounter_Priv: \n" + " b MPU_ulTaskGetRunTimeCounterImpl \n" + " MPU_ulTaskGetRunTimeCounter_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetRunTimeCounter ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetRunTimePercentImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetRunTimePercent_Unpriv \n" + " MPU_ulTaskGetRunTimePercent_Priv: \n" + " b MPU_ulTaskGetRunTimePercentImpl \n" + " MPU_ulTaskGetRunTimePercent_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetRunTimePercent ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetIdleRunTimePercentImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetIdleRunTimePercent_Unpriv \n" + " MPU_ulTaskGetIdleRunTimePercent_Priv: \n" + " b MPU_ulTaskGetIdleRunTimePercentImpl \n" + " MPU_ulTaskGetIdleRunTimePercent_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimePercent ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGetIdleRunTimeCounterImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv \n" + " MPU_ulTaskGetIdleRunTimeCounter_Priv: \n" + " b MPU_ulTaskGetIdleRunTimeCounterImpl \n" + " MPU_ulTaskGetIdleRunTimeCounter_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGetIdleRunTimeCounter ) : "memory" + ); + } + + #endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetApplicationTaskTagImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetApplicationTaskTag_Unpriv \n" + " MPU_vTaskSetApplicationTaskTag_Priv: \n" + " b MPU_vTaskSetApplicationTaskTagImpl \n" + " MPU_vTaskSetApplicationTaskTag_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetApplicationTaskTag ) : "memory" + ); + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetApplicationTaskTagImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetApplicationTaskTag_Unpriv \n" + " MPU_xTaskGetApplicationTaskTag_Priv: \n" + " b MPU_xTaskGetApplicationTaskTagImpl \n" + " MPU_xTaskGetApplicationTaskTag_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetApplicationTaskTag ) : "memory" + ); + } + + #endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetThreadLocalStoragePointerImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv \n" + " MPU_vTaskSetThreadLocalStoragePointer_Priv: \n" + " b MPU_vTaskSetThreadLocalStoragePointerImpl \n" + " MPU_vTaskSetThreadLocalStoragePointer_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetThreadLocalStoragePointer ) : "memory" + ); + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pvTaskGetThreadLocalStoragePointerImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv \n" + " MPU_pvTaskGetThreadLocalStoragePointer_Priv: \n" + " b MPU_pvTaskGetThreadLocalStoragePointerImpl \n" + " MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer ) : "memory" + ); + } + + #endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetSystemStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetSystemState_Unpriv \n" + " MPU_uxTaskGetSystemState_Priv: \n" + " b MPU_uxTaskGetSystemStateImpl \n" + " MPU_uxTaskGetSystemState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetSystemState ) : "memory" + ); + } + + #endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) + + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetStackHighWaterMarkImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetStackHighWaterMark_Unpriv \n" + " MPU_uxTaskGetStackHighWaterMark_Priv: \n" + " b MPU_uxTaskGetStackHighWaterMarkImpl \n" + " MPU_uxTaskGetStackHighWaterMark_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTaskGetStackHighWaterMark2Impl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTaskGetStackHighWaterMark2_Unpriv \n" + " MPU_uxTaskGetStackHighWaterMark2_Priv: \n" + " b MPU_uxTaskGetStackHighWaterMark2Impl \n" + " MPU_uxTaskGetStackHighWaterMark2_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTaskGetStackHighWaterMark2 ) : "memory" + ); + } + + #endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) + + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetCurrentTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetCurrentTaskHandle_Unpriv \n" + " MPU_xTaskGetCurrentTaskHandle_Priv: \n" + " b MPU_xTaskGetCurrentTaskHandleImpl \n" + " MPU_xTaskGetCurrentTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetCurrentTaskHandle ) : "memory" + ); + } + + #endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTaskGetSchedulerState == 1 ) + + BaseType_t MPU_xTaskGetSchedulerState( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGetSchedulerState( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGetSchedulerStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGetSchedulerState_Unpriv \n" + " MPU_xTaskGetSchedulerState_Priv: \n" + " b MPU_xTaskGetSchedulerStateImpl \n" + " MPU_xTaskGetSchedulerState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGetSchedulerState ) : "memory" + ); + } + + #endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */ +/*-----------------------------------------------------------*/ + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTaskSetTimeOutStateImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTaskSetTimeOutState_Unpriv \n" + " MPU_vTaskSetTimeOutState_Priv: \n" + " b MPU_vTaskSetTimeOutStateImpl \n" + " MPU_vTaskSetTimeOutState_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTaskSetTimeOutState ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskCheckForTimeOutImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskCheckForTimeOut_Unpriv \n" + " MPU_xTaskCheckForTimeOut_Priv: \n" + " b MPU_xTaskCheckForTimeOutImpl \n" + " MPU_xTaskCheckForTimeOut_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskCheckForTimeOut ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotify_Unpriv \n" + " MPU_xTaskGenericNotify_Priv: \n" + " b MPU_xTaskGenericNotifyImpl \n" + " MPU_xTaskGenericNotify_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotify ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyWaitImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotifyWait_Unpriv \n" + " MPU_xTaskGenericNotifyWait_Priv: \n" + " b MPU_xTaskGenericNotifyWaitImpl \n" + " MPU_xTaskGenericNotifyWait_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotifyWait ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGenericNotifyTakeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGenericNotifyTake_Unpriv \n" + " MPU_ulTaskGenericNotifyTake_Priv: \n" + " b MPU_ulTaskGenericNotifyTakeImpl \n" + " MPU_ulTaskGenericNotifyTake_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyTake ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTaskGenericNotifyStateClearImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTaskGenericNotifyStateClear_Unpriv \n" + " MPU_xTaskGenericNotifyStateClear_Priv: \n" + " b MPU_xTaskGenericNotifyStateClearImpl \n" + " MPU_xTaskGenericNotifyStateClear_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTaskGenericNotifyStateClear ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_ulTaskGenericNotifyValueClearImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_ulTaskGenericNotifyValueClear_Unpriv \n" + " MPU_ulTaskGenericNotifyValueClear_Priv: \n" + " b MPU_ulTaskGenericNotifyValueClearImpl \n" + " MPU_ulTaskGenericNotifyValueClear_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_ulTaskGenericNotifyValueClear ) : "memory" + ); + } + + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGenericSendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGenericSend_Unpriv \n" + " MPU_xQueueGenericSend_Priv: \n" + " b MPU_xQueueGenericSendImpl \n" + " MPU_xQueueGenericSend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGenericSend ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxQueueMessagesWaitingImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxQueueMessagesWaiting_Unpriv \n" + " MPU_uxQueueMessagesWaiting_Priv: \n" + " b MPU_uxQueueMessagesWaitingImpl \n" + " MPU_uxQueueMessagesWaiting_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxQueueMessagesWaiting ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxQueueSpacesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxQueueSpacesAvailable_Unpriv \n" + " MPU_uxQueueSpacesAvailable_Priv: \n" + " b MPU_uxQueueSpacesAvailableImpl \n" + " MPU_uxQueueSpacesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxQueueSpacesAvailable ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueReceiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueReceive_Unpriv \n" + " MPU_xQueueReceive_Priv: \n" + " b MPU_xQueueReceiveImpl \n" + " MPU_xQueueReceive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueReceive ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueuePeekImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueuePeek_Unpriv \n" + " MPU_xQueuePeek_Priv: \n" + " b MPU_xQueuePeekImpl \n" + " MPU_xQueuePeek_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueuePeek ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueSemaphoreTakeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueSemaphoreTake_Unpriv \n" + " MPU_xQueueSemaphoreTake_Priv: \n" + " b MPU_xQueueSemaphoreTakeImpl \n" + " MPU_xQueueSemaphoreTake_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueSemaphoreTake ) : "memory" + ); + } +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) + + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGetMutexHolderImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGetMutexHolder_Unpriv \n" + " MPU_xQueueGetMutexHolder_Priv: \n" + " b MPU_xQueueGetMutexHolderImpl \n" + " MPU_xQueueGetMutexHolder_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGetMutexHolder ) : "memory" + ); + } + + #endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueTakeMutexRecursiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueTakeMutexRecursive_Unpriv \n" + " MPU_xQueueTakeMutexRecursive_Priv: \n" + " b MPU_xQueueTakeMutexRecursiveImpl \n" + " MPU_xQueueTakeMutexRecursive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueTakeMutexRecursive ) : "memory" + ); + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueGiveMutexRecursiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueGiveMutexRecursive_Unpriv \n" + " MPU_xQueueGiveMutexRecursive_Priv: \n" + " b MPU_xQueueGiveMutexRecursiveImpl \n" + " MPU_xQueueGiveMutexRecursive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueGiveMutexRecursive ) : "memory" + ); + } + + #endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueSelectFromSetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueSelectFromSet_Unpriv \n" + " MPU_xQueueSelectFromSet_Priv: \n" + " b MPU_xQueueSelectFromSetImpl \n" + " MPU_xQueueSelectFromSet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueSelectFromSet ) : "memory" + ); + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_QUEUE_SETS == 1 ) + + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xQueueAddToSetImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xQueueAddToSet_Unpriv \n" + " MPU_xQueueAddToSet_Priv: \n" + " b MPU_xQueueAddToSetImpl \n" + " MPU_xQueueAddToSet_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xQueueAddToSet ) : "memory" + ); + } + + #endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vQueueAddToRegistryImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vQueueAddToRegistry_Unpriv \n" + " MPU_vQueueAddToRegistry_Priv: \n" + " b MPU_vQueueAddToRegistryImpl \n" + " MPU_vQueueAddToRegistry_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vQueueAddToRegistry ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vQueueUnregisterQueueImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vQueueUnregisterQueue_Unpriv \n" + " MPU_vQueueUnregisterQueue_Priv: \n" + " b MPU_vQueueUnregisterQueueImpl \n" + " MPU_vQueueUnregisterQueue_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vQueueUnregisterQueue ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pcQueueGetNameImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pcQueueGetName_Unpriv \n" + " MPU_pcQueueGetName_Priv: \n" + " b MPU_pcQueueGetNameImpl \n" + " MPU_pcQueueGetName_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pcQueueGetName ) : "memory" + ); + } + + #endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pvTimerGetTimerIDImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pvTimerGetTimerID_Unpriv \n" + " MPU_pvTimerGetTimerID_Priv: \n" + " b MPU_pvTimerGetTimerIDImpl \n" + " MPU_pvTimerGetTimerID_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pvTimerGetTimerID ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTimerSetTimerIDImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTimerSetTimerID_Unpriv \n" + " MPU_vTimerSetTimerID_Priv: \n" + " b MPU_vTimerSetTimerIDImpl \n" + " MPU_vTimerSetTimerID_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTimerSetTimerID ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerIsTimerActiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerIsTimerActive_Unpriv \n" + " MPU_xTimerIsTimerActive_Priv: \n" + " b MPU_xTimerIsTimerActiveImpl \n" + " MPU_xTimerIsTimerActive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerIsTimerActive ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetTimerDaemonTaskHandleImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv \n" + " MPU_xTimerGetTimerDaemonTaskHandle_Priv: \n" + " b MPU_xTimerGetTimerDaemonTaskHandleImpl \n" + " MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGenericCommandFromTaskImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGenericCommandFromTask_Unpriv \n" + " MPU_xTimerGenericCommandFromTask_Priv: \n" + " b MPU_xTimerGenericCommandFromTaskImpl \n" + " MPU_xTimerGenericCommandFromTask_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGenericCommandFromTask ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_pcTimerGetNameImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_pcTimerGetName_Unpriv \n" + " MPU_pcTimerGetName_Priv: \n" + " b MPU_pcTimerGetNameImpl \n" + " MPU_pcTimerGetName_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_pcTimerGetName ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vTimerSetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vTimerSetReloadMode_Unpriv \n" + " MPU_vTimerSetReloadMode_Priv: \n" + " b MPU_vTimerSetReloadModeImpl \n" + " MPU_vTimerSetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vTimerSetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetReloadMode_Unpriv \n" + " MPU_xTimerGetReloadMode_Priv: \n" + " b MPU_xTimerGetReloadModeImpl \n" + " MPU_xTimerGetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxTimerGetReloadModeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxTimerGetReloadMode_Unpriv \n" + " MPU_uxTimerGetReloadMode_Priv: \n" + " b MPU_uxTimerGetReloadModeImpl \n" + " MPU_uxTimerGetReloadMode_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxTimerGetReloadMode ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetPeriodImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetPeriod_Unpriv \n" + " MPU_xTimerGetPeriod_Priv: \n" + " b MPU_xTimerGetPeriodImpl \n" + " MPU_xTimerGetPeriod_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetPeriod ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TIMERS == 1 ) + + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xTimerGetExpiryTimeImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xTimerGetExpiryTime_Unpriv \n" + " MPU_xTimerGetExpiryTime_Priv: \n" + " b MPU_xTimerGetExpiryTimeImpl \n" + " MPU_xTimerGetExpiryTime_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xTimerGetExpiryTime ) : "memory" + ); + } + + #endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupWaitBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupWaitBits_Unpriv \n" + " MPU_xEventGroupWaitBits_Priv: \n" + " b MPU_xEventGroupWaitBitsImpl \n" + " MPU_xEventGroupWaitBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupWaitBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupClearBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupClearBits_Unpriv \n" + " MPU_xEventGroupClearBits_Priv: \n" + " b MPU_xEventGroupClearBitsImpl \n" + " MPU_xEventGroupClearBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupClearBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupSetBitsImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupSetBits_Unpriv \n" + " MPU_xEventGroupSetBits_Priv: \n" + " b MPU_xEventGroupSetBitsImpl \n" + " MPU_xEventGroupSetBits_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupSetBits ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_EVENT_GROUPS == 1 ) + + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xEventGroupSyncImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xEventGroupSync_Unpriv \n" + " MPU_xEventGroupSync_Priv: \n" + " b MPU_xEventGroupSyncImpl \n" + " MPU_xEventGroupSync_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xEventGroupSync ) : "memory" + ); + } + + #endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_uxEventGroupGetNumberImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_uxEventGroupGetNumber_Unpriv \n" + " MPU_uxEventGroupGetNumber_Priv: \n" + " b MPU_uxEventGroupGetNumberImpl \n" + " MPU_uxEventGroupGetNumber_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_uxEventGroupGetNumber ) : "memory" + ); + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_vEventGroupSetNumberImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_vEventGroupSetNumber_Unpriv \n" + " MPU_vEventGroupSetNumber_Priv: \n" + " b MPU_vEventGroupSetNumberImpl \n" + " MPU_vEventGroupSetNumber_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_vEventGroupSetNumber ) : "memory" + ); + } + + #endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSendImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferSend_Unpriv \n" + " MPU_xStreamBufferSend_Priv: \n" + " b MPU_xStreamBufferSendImpl \n" + " MPU_xStreamBufferSend_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSend ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferReceiveImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferReceive_Unpriv \n" + " MPU_xStreamBufferReceive_Priv: \n" + " b MPU_xStreamBufferReceiveImpl \n" + " MPU_xStreamBufferReceive_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferReceive ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferIsFullImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferIsFull_Unpriv \n" + " MPU_xStreamBufferIsFull_Priv: \n" + " b MPU_xStreamBufferIsFullImpl \n" + " MPU_xStreamBufferIsFull_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferIsFull ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferIsEmptyImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferIsEmpty_Unpriv \n" + " MPU_xStreamBufferIsEmpty_Priv: \n" + " b MPU_xStreamBufferIsEmptyImpl \n" + " MPU_xStreamBufferIsEmpty_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferIsEmpty ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSpacesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferSpacesAvailable_Unpriv \n" + " MPU_xStreamBufferSpacesAvailable_Priv: \n" + " b MPU_xStreamBufferSpacesAvailableImpl \n" + " MPU_xStreamBufferSpacesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSpacesAvailable ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferBytesAvailableImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferBytesAvailable_Unpriv \n" + " MPU_xStreamBufferBytesAvailable_Priv: \n" + " b MPU_xStreamBufferBytesAvailableImpl \n" + " MPU_xStreamBufferBytesAvailable_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferBytesAvailable ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferSetTriggerLevelImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferSetTriggerLevel_Unpriv \n" + " MPU_xStreamBufferSetTriggerLevel_Priv: \n" + " b MPU_xStreamBufferSetTriggerLevelImpl \n" + " MPU_xStreamBufferSetTriggerLevel_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferSetTriggerLevel ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_STREAM_BUFFERS == 1 ) + + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) __attribute__( ( naked ) ) FREERTOS_SYSTEM_CALL; + + size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* __attribute__ (( naked )) FREERTOS_SYSTEM_CALL */ + { + __asm volatile + ( + " .syntax unified \n" + " .extern MPU_xStreamBufferNextMessageLengthBytesImpl \n" + " \n" + " push {r0} \n" + " mrs r0, control \n" + " tst r0, #1 \n" + " pop {r0} \n" + " bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv \n" + " MPU_xStreamBufferNextMessageLengthBytes_Priv: \n" + " b MPU_xStreamBufferNextMessageLengthBytesImpl \n" + " MPU_xStreamBufferNextMessageLengthBytes_Unpriv: \n" + " svc %0 \n" + " \n" + : : "i" ( SYSTEM_CALL_xStreamBufferNextMessageLengthBytes ) : "memory" + ); + } + + #endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ diff --git a/portable/GCC/ARM_STAR_MC3_NTZ/non_secure/port.c b/portable/GCC/ARM_STAR_MC3_NTZ/non_secure/port.c new file mode 100644 index 000000000..76d2b2445 --- /dev/null +++ b/portable/GCC/ARM_STAR_MC3_NTZ/non_secure/port.c @@ -0,0 +1,2280 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024-2025 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU includes. */ +#include "mpu_wrappers.h" +#include "mpu_syscall_numbers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration settings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to check the validity of an interrupt priority. + */ +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) ) +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used during system call enter and exit. + */ +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Offsets in the stack to the parameters when inside the SVC handler. + */ +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +#if ( portARMV8M_MINOR_VERSION >= 1 ) + + /* Enable Privileged eXecute Never MPU attribute for the selected memory + * region. */ + #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL ) +#endif /* portARMV8M_MINOR_VERSION >= 1 */ + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Extract first address of the MPU region as encoded in the + * RBAR (Region Base Address Register) value. */ +#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \ + ( ( rbar ) & portMPU_RBAR_ADDRESS_MASK ) + +/* Extract last address of the MPU region as encoded in the + * RLAR (Region Limit Address Register) value. */ +#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \ + ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK ) + +/* Does addr lies within [start, end] address range? */ +#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \ + ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) ) + +/* Is the access request satisfied by the available permissions? */ +#define portIS_AUTHORIZED( accessRequest, permissions ) \ + ( ( ( permissions ) & ( accessRequest ) ) == accessRequest ) + +/* Max value that fits in a uint32_t type. */ +#define portUINT32_MAX ( ~( ( uint32_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. + */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 + +/** + * @brief Constants required to check and configure PACBTI security feature implementation. + */ +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) ) + + #define portCONTROL_UPAC_EN ( 1UL << 7UL ) + #define portCONTROL_PAC_EN ( 1UL << 6UL ) + #define portCONTROL_UBTI_EN ( 1UL << 5UL ) + #define portCONTROL_BTI_EN ( 1UL << 4UL ) + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Extract MPU region's access permissions from the Region Base Address + * Register (RBAR) value. + * + * @param ulRBARValue RBAR value for the MPU region. + * + * @return uint32_t Access permissions. + */ + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + + /** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + /** + * @brief Configures PACBTI features. + * + * This function configures the Pointer Authentication, and Branch Target + * Identification security features as per the user configuration. It returns + * the value of the special purpose CONTROL register accordingly, and optionally + * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M + * architecture based) target supports PACBTI security feature. + * + * @param xWriteControlRegister Used to control whether the special purpose + * CONTROL register should be updated or not. + * + * @return CONTROL register value according to the configured PACBTI option. + */ + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the system call stack so that upon returning from + * SVC, the system call stack is used. + * + * @param pulTaskStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + * @param ucSystemCallNumber The system call number of the system call. + */ + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Raise SVC for exiting from a system call. + */ + void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief This variable is set to pdTRUE when the scheduler is started. + */ + PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + + /** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +/** + * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + /** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + + /** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + + /** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the cpsid instruction + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessPermissions = 0; + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_ONLY ) + { + ulAccessPermissions = tskMPU_READ_PERMISSION; + } + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_WRITE ) + { + ulAccessPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION ); + } + + return ulAccessPermissions; + } + +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } + +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ portOFFSET_TO_PC ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ]; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulSystemCallStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the system call section (i.e. application is + * not raising SVC directly). + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as + * it is non-NULL only during the execution of a system call (i.e. + * between system call enter and exit). + * 3. System call is not for a kernel API disabled by the configuration + * in FreeRTOSConfig.h. + * 4. We do not need to check that ucSystemCallNumber is within range + * because the assembly SVC handler checks that before calling + * this function. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) && + ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) ) + { + pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the system call stack for the stack frame. */ + pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulSystemCallStack[ i ] = pulTaskStack[ i ]; + } + + /* Store the value of the Link Register before the SVC was raised. + * It contains the address of the caller of the System Call entry + * point (i.e. the caller of the MPU_). We need to restore it + * when we exit from the system call. */ + pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; + + /* Store the value of the PSPLIM register before the SVC was raised. + * We need to restore it when we exit from the system call. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* Use the pulSystemCallStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif + + /* Start executing the system call upon returning from this handler. */ + pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; + + /* Raise a request to exit from the system call upon finishing the + * system call. */ + pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; + + /* Remember the location where we should copy the stack frame when we exit from + * the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize; + + /* Record if the hardware used padding to force the stack pointer + * to be double word aligned. */ + if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK ) + { + pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG; + } + else + { + pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG ); + } + + /* We ensure in pxPortInitialiseStack that the system call stack is + * double word aligned and therefore, there is no need of padding. + * Clear the bit[9] of stacked xPSR. */ + pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + + /* Raise the privilege for the duration of the system call. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " bics r0, r1 \n" /* Clear nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */ + { + __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulTaskStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the privileged code (i.e. application is not + * raising SVC directly). This SVC is only raised from + * vRequestSystemCallExit which is in the privileged code section. + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL - + * this means that we previously entered a system call and the + * application is not attempting to exit without entering a system + * call. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) ) + { + pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the task stack for the stack frame. */ + pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulTaskStack[ i ] = pulSystemCallStack[ i ]; + } + + /* Use the pulTaskStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) ); + + /* Return to the caller of the System Call entry point (i.e. the + * caller of the MPU_). */ + pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + /* Ensure that LR has a valid value.*/ + pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + + /* Restore the PSPLIM register to what it was at the time of + * system call entry. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* If the hardware used padding to force the stack pointer + * to be double word aligned, set the stacked xPSR bit[9], + * otherwise clear it. */ + if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG ) + { + pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK; + } + else + { + pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + } + + /* This is not NULL only for the duration of the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; + + /* Drop the privilege before returning to the thread mode. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " orrs r0, r1 \n" /* Set nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xTaskIsPrivileged = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xTaskIsPrivileged = pdTRUE; + } + + return xTaskIsPrivileged; + } + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged, + xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulIndex = 0; + uint32_t ulControl = 0x0; + + xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ + ulIndex++; + + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + ulIndex++; + + #if ( configENABLE_TRUSTZONE == 1 ) + { + xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */ + ulIndex++; + } + #endif /* configENABLE_TRUSTZONE */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + ulIndex++; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Check PACBTI security feature configuration before pushing the + * CONTROL register's value on task's TCB. */ + ulControl = prvConfigurePACBTI( pdFALSE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + if( xRunPrivileged == pdTRUE ) + { + xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + else + { + xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG ); + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ + ulIndex++; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + { + /* Ensure that the system call stack is double word aligned. */ + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) + + ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + /* This is not NULL only for the duration of a system call. */ + xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL; + } + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ]; + ulIndex++; + } + } + #endif /* configENABLE_PAC */ + + return &( xMPUSettings->ulContext[ ulIndex ] ); + } + +#else /* configENABLE_MPU */ + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ + { + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + pxTopOfStack--; + *pxTopOfStack = ulTaskPacKey[ i ]; + } + } + #endif /* configENABLE_PAC */ + + return pxTopOfStack; + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Set the CONTROL register value based on PACBTI security feature + * configuration before starting the first task. */ + ( void ) prvConfigurePACBTI( pdTRUE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + { + xSchedulerRunning = pdTRUE; + } + #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + configSTACK_DEPTH_TYPE uxStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( uxStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* PXN. */ + #if ( portARMV8M_MINOR_VERSION >= 1 ) + { + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ); + } + } + #endif /* portARMV8M_MINOR_VERSION >= 1 */ + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, + uint32_t ulBufferLength, + uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */ + + { + uint32_t i, ulBufferStartAddress, ulBufferEndAddress; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE ) + { + ulBufferStartAddress = ( uint32_t ) pvBuffer; + ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL ); + + for( i = 0; i < portTOTAL_NUM_REGIONS; i++ ) + { + /* Is the MPU region enabled? */ + if( ( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR & portMPU_RLAR_REGION_ENABLE ) == portMPU_RLAR_REGION_ENABLE ) + { + if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_AUTHORIZED( ulAccessRequested, + prvGetRegionAccessPermissions( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ) ) ) + { + xAccessGranted = pdTRUE; + break; + } + } + } + } + } + + return xAccessGranted; + } + +#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings; + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else + { + xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 ) + { + xAccessGranted = pdTRUE; + } + } + } + + return xAccessGranted; + } + + #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + ( void ) lInternalIndexOfKernelObject; + + /* If Access Control List feature is not used, all the tasks have + * access to all the kernel objects. */ + return pdTRUE; + } + + #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + { + uint32_t ulControl = 0x0; + + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); + + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; + + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_STAR_MC3_NTZ/non_secure/portasm.c b/portable/GCC/ARM_STAR_MC3_NTZ/non_secure/portasm.c new file mode 100644 index 000000000..bc7bb6071 --- /dev/null +++ b/portable/GCC/ARM_STAR_MC3_NTZ/non_secure/portasm.c @@ -0,0 +1,524 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION + * is defined correctly and privileged functions are placed in correct sections. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Portasm includes. */ +#include "portasm.h" + +/* System call numbers includes. */ +#include "mpu_syscall_numbers.h" + +/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the + * header files. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#if ( configENABLE_MPU == 1 ) + + void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " program_mpu_first_task: \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */ + " \n" + " dmb \n" /* Complete outstanding transfers before disabling MPU. */ + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + " str r2, [r1] \n" /* Disable MPU. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */ + " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r1, [r2] \n" /* Program MAIR0. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " \n" + " movs r3, #4 \n" /* r3 = 4. */ + " str r3, [r1] \n" /* Program RNR = 4. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + " \n" + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " orr r2, #1 \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */ + " str r2, [r1] \n" /* Enable MPU. */ + " dsb \n" /* Force memory writes before continuing. */ + " \n" + " restore_context_first_task: \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/ + " ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */ + " \n" + " restore_special_regs_first_task: \n" + #if ( configENABLE_PAC == 1 ) + " ldmdb r1!, {r2-r5} \n" /* Read task's dedicated PAC key from the task's context. */ + " msr PAC_KEY_P_0, r2 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_1, r3 \n" + " msr PAC_KEY_P_2, r4 \n" + " msr PAC_KEY_P_3, r5 \n" + " clrm {r2-r5} \n" /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + " ldmdb r1!, {r2-r4, lr} \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */ + " msr psp, r2 \n" + " msr psplim, r3 \n" + " msr control, r4 \n" + " \n" + " restore_general_regs_first_task: \n" + " ldmdb r1!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */ + " stmia r2!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */ + " ldmdb r1!, {r4-r11} \n" /* r4-r11 restored. */ + " \n" + " restore_context_done_first_task: \n" + " str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */ + " mov r0, #0 \n" + " msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */ + " bx lr \n" + ); + } + +#else /* configENABLE_MPU */ + + void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + " ldr r0, [r1] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + " \n" + #if ( configENABLE_PAC == 1 ) + " ldmia r0!, {r1-r4} \n" /* Read task's dedicated PAC key from stack. */ + " msr PAC_KEY_P_3, r1 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_2, r2 \n" + " msr PAC_KEY_P_1, r3 \n" + " msr PAC_KEY_P_0, r4 \n" + " clrm {r1-r4} \n" /* Clear r1-r4. */ + #endif /* configENABLE_PAC */ + " \n" + " ldm r0!, {r1-r2} \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */ + " msr psplim, r1 \n" /* Set this task's PSPLIM value. */ + " mrs r1, control \n" /* Obtain current control register value. */ + " orrs r1, r1, #2 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */ + " msr control, r1 \n" /* Write back the new control register value. */ + " adds r0, #32 \n" /* Discard everything up to r0. */ + " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */ + " isb \n" + " mov r0, #0 \n" + " msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */ + " bx r2 \n" /* Finally, branch to EXC_RETURN. */ + ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* r0 = CONTROL. */ + " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + " ite ne \n" + " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + " bx lr \n" /* Return. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* Read the CONTROL register. */ + " bic r0, #1 \n" /* Clear the bit 0. */ + " msr control, r0 \n" /* Write back the new CONTROL value. */ + " bx lr \n" /* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vResetPrivilege( void ) /* __attribute__ (( naked )) */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, control \n" /* r0 = CONTROL. */ + " orr r0, #1 \n" /* r0 = r0 | 1. */ + " msr control, r0 \n" /* CONTROL = r0. */ + " bx lr \n" /* Return to the caller. */ + ::: "r0", "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r0, =0xe000ed08 \n" /* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */ + " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */ + " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */ + " cpsie i \n" /* Globally enable interrupts. */ + " cpsie f \n" + " dsb \n" + " isb \n" + " svc %0 \n" /* System call to start the first task. */ + " nop \n" + ::"i" ( portSVC_START_SCHEDULER ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, basepri \n" /* r0 = basepri. Return original basepri value. */ + " mov r1, %0 \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " msr basepri, r1 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bx lr \n" /* Return. */ + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */ +{ + __asm volatile + ( + " .syntax unified \n" + " \n" + " msr basepri, r0 \n" /* basepri = ulMask. */ + " dsb \n" + " isb \n" + " bx lr \n" /* Return. */ + ::: "memory" + ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */ + " ldr r1, [r0] \n" /* r1 = Location in TCB where the context should be saved. */ + " mrs r2, psp \n" /* r2 = PSP. */ + " \n" + " save_general_regs: \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " add r2, r2, #0x20 \n" /* Move r2 to location where s0 is saved. */ + " tst lr, #0x10 \n" + " ittt eq \n" + " vstmiaeq r1!, {s16-s31} \n" /* Store s16-s31. */ + " vldmiaeq r2, {s0-s16} \n" /* Copy hardware saved FP context into s0-s16. */ + " vstmiaeq r1!, {s0-s16} \n" /* Store hardware saved FP context. */ + " sub r2, r2, #0x20 \n" /* Set r2 back to the location of hardware saved context. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " stmia r1!, {r4-r11} \n" /* Store r4-r11. */ + " ldmia r2, {r4-r11} \n" /* Copy the hardware saved context into r4-r11. */ + " stmia r1!, {r4-r11} \n" /* Store the hardware saved context. */ + " \n" + " save_special_regs: \n" + " mrs r3, psplim \n" /* r3 = PSPLIM. */ + " mrs r4, control \n" /* r4 = CONTROL. */ + " stmia r1!, {r2-r4, lr} \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ + #if ( configENABLE_PAC == 1 ) + " mrs r2, PAC_KEY_P_0 \n" /* Read task's dedicated PAC key from the PAC key registers. */ + " mrs r3, PAC_KEY_P_1 \n" + " mrs r4, PAC_KEY_P_2 \n" + " mrs r5, PAC_KEY_P_3 \n" + " stmia r1!, {r2-r5} \n" /* Store the task's dedicated PAC key on the task's context. */ + " clrm {r2-r5} \n" /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + " str r1, [r0] \n" /* Save the location from where the context should be restored as the first member of TCB. */ + " \n" + " select_next_task: \n" + " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bl vTaskSwitchContext \n" + " mov r0, #0 \n" /* r0 = 0. */ + " msr basepri, r0 \n" /* Enable interrupts. */ + " \n" + " program_mpu: \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */ + " \n" + " dmb \n" /* Complete outstanding transfers before disabling MPU. */ + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + " str r2, [r1] \n" /* Disable MPU. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */ + " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */ + " str r1, [r2] \n" /* Program MAIR0. */ + " \n" + " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */ + " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */ + " \n" + " movs r3, #4 \n" /* r3 = 4. */ + " str r3, [r1] \n" /* Program RNR = 4. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " \n" + #if ( configTOTAL_MPU_REGIONS == 16 ) + " movs r3, #8 \n" /* r3 = 8. */ + " str r3, [r1] \n" /* Program RNR = 8. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + " movs r3, #12 \n" /* r3 = 12. */ + " str r3, [r1] \n" /* Program RNR = 12. */ + " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */ + " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + " \n" + " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */ + " orr r2, #1 \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */ + " str r2, [r1] \n" /* Enable MPU. */ + " dsb \n" /* Force memory writes before continuing. */ + " \n" + " restore_context: \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/ + " ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */ + " \n" + " restore_special_regs: \n" + #if ( configENABLE_PAC == 1 ) + " ldmdb r1!, {r2-r5} \n" /* Read task's dedicated PAC key from the task's context. */ + " msr PAC_KEY_P_0, r2 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_1, r3 \n" + " msr PAC_KEY_P_2, r4 \n" + " msr PAC_KEY_P_3, r5 \n" + " clrm {r2-r5} \n" /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + " ldmdb r1!, {r2-r4, lr} \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */ + " msr psp, r2 \n" + " msr psplim, r3 \n" + " msr control, r4 \n" + " \n" + " restore_general_regs: \n" + " ldmdb r1!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */ + " stmia r2!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */ + " ldmdb r1!, {r4-r11} \n" /* r4-r11 restored. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" + " ittt eq \n" + " vldmdbeq r1!, {s0-s16} \n" /* s0-s16 contain hardware saved FP context. */ + " vstmiaeq r2!, {s0-s16} \n" /* Copy hardware saved FP context on the task stack. */ + " vldmdbeq r1!, {s16-s31} \n" /* Restore s16-s31. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + " restore_context_done: \n" + " str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */ + " bx lr \n" + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); + } + +#else /* configENABLE_MPU */ + + void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " mrs r0, psp \n" /* Read PSP in r0. */ + " \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vstmdbeq r0!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + " mrs r2, psplim \n" /* r2 = PSPLIM. */ + " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */ + " stmdb r0!, {r2-r11} \n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */ + " \n" + #if ( configENABLE_PAC == 1 ) + " mrs r1, PAC_KEY_P_3 \n" /* Read task's dedicated PAC key from the PAC key registers. */ + " mrs r2, PAC_KEY_P_2 \n" + " mrs r3, PAC_KEY_P_1 \n" + " mrs r4, PAC_KEY_P_0 \n" + " stmdb r0!, {r1-r4} \n" /* Store the task's dedicated PAC key on the stack. */ + " clrm {r1-r4} \n" /* Clear r1-r4. */ + #endif /* configENABLE_PAC */ + " \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + " str r0, [r1] \n" /* Save the new top of stack in TCB. */ + " \n" + " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */ + " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + " dsb \n" + " isb \n" + " bl vTaskSwitchContext \n" + " mov r0, #0 \n" /* r0 = 0. */ + " msr basepri, r0 \n" /* Enable interrupts. */ + " \n" + " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + " ldr r1, [r2] \n" /* Read pxCurrentTCB. */ + " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ + " \n" + #if ( configENABLE_PAC == 1 ) + " ldmia r0!, {r2-r5} \n" /* Read task's dedicated PAC key from stack. */ + " msr PAC_KEY_P_3, r2 \n" /* Write the task's dedicated PAC key to the PAC key registers. */ + " msr PAC_KEY_P_2, r3 \n" + " msr PAC_KEY_P_1, r4 \n" + " msr PAC_KEY_P_0, r5 \n" + " clrm {r2-r5} \n" /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + " \n" + " ldmia r0!, {r2-r11} \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */ + " \n" + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + " tst r3, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + " it eq \n" + " vldmiaeq r0!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + " \n" + " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */ + " msr psp, r0 \n" /* Remember the new top of stack for the task. */ + " bx r3 \n" + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + ".syntax unified \n" + ".extern vPortSVCHandler_C \n" + ".extern vSystemCallEnter \n" + ".extern vSystemCallExit \n" + " \n" + "tst lr, #4 \n" + "ite eq \n" + "mrseq r0, msp \n" + "mrsne r0, psp \n" + " \n" + "ldr r1, [r0, #24] \n" + "ldrb r2, [r1, #-2] \n" + "cmp r2, %0 \n" + "blt syscall_enter \n" + "cmp r2, %1 \n" + "beq syscall_exit \n" + "b vPortSVCHandler_C \n" + " \n" + "syscall_enter: \n" + " mov r1, lr \n" + " b vSystemCallEnter \n" + " \n" + "syscall_exit: \n" + " mov r1, lr \n" + " b vSystemCallExit \n" + " \n" + : /* No outputs. */ + : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT ) + : "r0", "r1", "r2", "memory" + ); + } + +#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */ + { + __asm volatile + ( + " .syntax unified \n" + " \n" + " tst lr, #4 \n" + " ite eq \n" + " mrseq r0, msp \n" + " mrsne r0, psp \n" + " ldr r1, =vPortSVCHandler_C \n" + " bx r1 \n" + ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/ARM_STAR_MC3_NTZ/non_secure/portasm.h b/portable/GCC/ARM_STAR_MC3_NTZ/non_secure/portasm.h new file mode 100644 index 000000000..b7021b024 --- /dev/null +++ b/portable/GCC/ARM_STAR_MC3_NTZ/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kernel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/portable/GCC/ARM_STAR_MC3_NTZ/non_secure/portmacro.h b/portable/GCC/ARM_STAR_MC3_NTZ/non_secure/portmacro.h new file mode 100644 index 000000000..99538ef82 --- /dev/null +++ b/portable/GCC/ARM_STAR_MC3_NTZ/non_secure/portmacro.h @@ -0,0 +1,80 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (c) 2026 Arm Technology (China) Co., Ltd.All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_MVE + #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE. +#endif /* configENABLE_MVE */ +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "STAR-MC3" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portARMV8M_MINOR_VERSION 1 +#define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/ARM_STAR_MC3_NTZ/non_secure/portmacrocommon.h b/portable/GCC/ARM_STAR_MC3_NTZ/non_secure/portmacrocommon.h new file mode 100644 index 000000000..f373bcad5 --- /dev/null +++ b/portable/GCC/ARM_STAR_MC3_NTZ/non_secure/portmacrocommon.h @@ -0,0 +1,582 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACROCOMMON_H +#define PORTMACROCOMMON_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. +#endif /* configENABLE_FPU */ + +#ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. +#endif /* configENABLE_MPU */ + +#ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. +#endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() +#define portINLINE __inline +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif +#define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ +extern BaseType_t xPortIsInsideInterrupt( void ); + +extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + +extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; +extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + +extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; +extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + +#if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_PAC == 1 ) + + /** + * @brief Generates 128-bit task's random PAC key. + * + * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be + * filled with a 128-bit random number. + */ + void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); + +#endif /* configENABLE_PAC */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ +#if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) +#else + #define portPRIVILEGE_BIT ( 0x0UL ) +#endif /* configENABLE_MPU */ + +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ +#define portPRIVILEGED_FLASH_REGION ( 0UL ) +#define portUNPRIVILEGED_FLASH_REGION ( 1UL ) +#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) +#define portPRIVILEGED_RAM_REGION ( 3UL ) +#define portSTACK_REGION ( 4UL ) +#define portFIRST_CONFIGURABLE_REGION ( 5UL ) +#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) +#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) +#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ +#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ +#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ +#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ +#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ +#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ +#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ +#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) +#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) +#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + +#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) +#define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) +#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) +#define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + +#define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + #ifndef configSYSTEM_CALL_STACK_SIZE + #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. + #endif + + /** + * @brief System call stack. + */ + typedef struct SYSTEM_CALL_STACK_INFO + { + uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; + uint32_t * pulSystemCallStack; + uint32_t * pulSystemCallStackLimit; + uint32_t * pulTaskStack; + uint32_t ulLinkRegisterAtSystemCallEntry; + uint32_t ulStackLimitRegisterAtSystemCallEntry; + } xSYSTEM_CALL_STACK_INFO; + + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + /** + * @brief MPU settings as stored in the TCB. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><-----------><----> + * 16 17 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 71 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 17 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 55 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | | | PC, xPSR | EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><-----------><----> + * 16 17 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 70 + + #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + /* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 17 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 54 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+------------------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +----------+-----------------+------------------------------+------------+-----+ + * + * <---------><----------------><------------------------------><-----------><----> + * 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 38 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+----------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | PC, xPSR | EXC_RETURN | | | + * +----------+-----------------+----------------------+------------+-----+ + * + * <---------><----------------><----------------------><-----------><----> + * 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 37 + + #else /* #if( configENABLE_TRUSTZONE == 1 ) */ + + /* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) + + /* Size of an Access Control List (ACL) entry in bits. */ + #define portACL_ENTRY_SIZE_BITS ( 32U ) + + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + uint32_t ulContext[ MAX_CONTEXT_SIZE ]; + uint32_t ulTaskFlags; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo; + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ]; + #endif + #endif + } xMPU_SETTINGS; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Validate priority of ISRs that are allowed to call FreeRTOS + * system calls. + */ +#if ( configASSERT_DEFINED == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif +#endif + +/** + * @brief SVC numbers. + */ +#define portSVC_ALLOCATE_SECURE_CONTEXT 100 +#define portSVC_FREE_SECURE_CONTEXT 101 +#define portSVC_START_SCHEDULER 102 +#define portSVC_RAISE_PRIVILEGE 103 +#define portSVC_SYSTEM_CALL_EXIT 104 +#define portSVC_YIELD 105 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) +#endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() +#else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + extern BaseType_t xPortIsTaskPrivileged( void ); + +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACROCOMMON_H */ diff --git a/portable/GCC/ATMega323/port.c b/portable/GCC/ATMega323/port.c new file mode 100644 index 000000000..ff80a8b81 --- /dev/null +++ b/portable/GCC/ATMega323/port.c @@ -0,0 +1,428 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * + * Changes from V2.6.0 + * + + AVR port - Replaced the inb() and outb() functions with direct memory + + access. This allows the port to be built with the 20050414 build of + + WinAVR. + */ + +#include +#include + +#include "FreeRTOS.h" +#include "task.h" + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the AVR port. +*----------------------------------------------------------*/ + +/* Start tasks with interrupts enables. */ +#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x80 ) + +/* Hardware constants for timer 1. */ +#define portCLEAR_COUNTER_ON_MATCH ( ( uint8_t ) 0x08 ) +#define portPRESCALE_64 ( ( uint8_t ) 0x03 ) +#define portCLOCK_PRESCALER ( ( uint32_t ) 64 ) +#define portCOMPARE_MATCH_A_INTERRUPT_ENABLE ( ( uint8_t ) 0x10 ) + +/*-----------------------------------------------------------*/ + +/* We require the address of the pxCurrentTCB variable, but don't want to know + * any details of its type. */ +typedef void TCB_t; +extern volatile TCB_t * volatile pxCurrentTCB; + +/*-----------------------------------------------------------*/ + +/* + * Macro to save all the general purpose registers, the save the stack pointer + * into the TCB. + * + * The first thing we do is save the flags then disable interrupts. This is to + * guard our stack against having a context switch interrupt after we have already + * pushed the registers onto the stack - causing the 32 registers to be on the + * stack twice. + * + * r1 is set to zero as the compiler expects it to be thus, however some + * of the math routines make use of R1. + * + * The interrupts will have been disabled during the call to portSAVE_CONTEXT() + * so we need not worry about reading/writing to the stack pointer. + */ + +#define portSAVE_CONTEXT() \ + asm volatile ( "push r0 \n\t" \ + "in r0, __SREG__ \n\t" \ + "cli \n\t" \ + "push r0 \n\t" \ + "push r1 \n\t" \ + "clr r1 \n\t" \ + "push r2 \n\t" \ + "push r3 \n\t" \ + "push r4 \n\t" \ + "push r5 \n\t" \ + "push r6 \n\t" \ + "push r7 \n\t" \ + "push r8 \n\t" \ + "push r9 \n\t" \ + "push r10 \n\t" \ + "push r11 \n\t" \ + "push r12 \n\t" \ + "push r13 \n\t" \ + "push r14 \n\t" \ + "push r15 \n\t" \ + "push r16 \n\t" \ + "push r17 \n\t" \ + "push r18 \n\t" \ + "push r19 \n\t" \ + "push r20 \n\t" \ + "push r21 \n\t" \ + "push r22 \n\t" \ + "push r23 \n\t" \ + "push r24 \n\t" \ + "push r25 \n\t" \ + "push r26 \n\t" \ + "push r27 \n\t" \ + "push r28 \n\t" \ + "push r29 \n\t" \ + "push r30 \n\t" \ + "push r31 \n\t" \ + "lds r26, pxCurrentTCB \n\t" \ + "lds r27, pxCurrentTCB + 1 \n\t" \ + "in r0, 0x3d \n\t" \ + "st x+, r0 \n\t" \ + "in r0, 0x3e \n\t" \ + "st x+, r0 \n\t" \ + ); + +/* + * Opposite to portSAVE_CONTEXT(). Interrupts will have been disabled during + * the context save so we can write to the stack pointer. + */ + +#define portRESTORE_CONTEXT() \ + asm volatile ( "lds r26, pxCurrentTCB \n\t" \ + "lds r27, pxCurrentTCB + 1 \n\t" \ + "ld r28, x+ \n\t" \ + "out __SP_L__, r28 \n\t" \ + "ld r29, x+ \n\t" \ + "out __SP_H__, r29 \n\t" \ + "pop r31 \n\t" \ + "pop r30 \n\t" \ + "pop r29 \n\t" \ + "pop r28 \n\t" \ + "pop r27 \n\t" \ + "pop r26 \n\t" \ + "pop r25 \n\t" \ + "pop r24 \n\t" \ + "pop r23 \n\t" \ + "pop r22 \n\t" \ + "pop r21 \n\t" \ + "pop r20 \n\t" \ + "pop r19 \n\t" \ + "pop r18 \n\t" \ + "pop r17 \n\t" \ + "pop r16 \n\t" \ + "pop r15 \n\t" \ + "pop r14 \n\t" \ + "pop r13 \n\t" \ + "pop r12 \n\t" \ + "pop r11 \n\t" \ + "pop r10 \n\t" \ + "pop r9 \n\t" \ + "pop r8 \n\t" \ + "pop r7 \n\t" \ + "pop r6 \n\t" \ + "pop r5 \n\t" \ + "pop r4 \n\t" \ + "pop r3 \n\t" \ + "pop r2 \n\t" \ + "pop r1 \n\t" \ + "pop r0 \n\t" \ + "out __SREG__, r0 \n\t" \ + "pop r0 \n\t" \ + ); + +/*-----------------------------------------------------------*/ + +/* + * Perform hardware setup to enable ticks from timer 1, compare match A. + */ +static void prvSetupTimerInterrupt( void ); +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + uint16_t usAddress; + + /* Place a few bytes of known values on the bottom of the stack. + * This is just useful for debugging. */ + + *pxTopOfStack = 0x11; + pxTopOfStack--; + *pxTopOfStack = 0x22; + pxTopOfStack--; + *pxTopOfStack = 0x33; + pxTopOfStack--; + + /* Simulate how the stack would look after a call to vPortYield() generated by + * the compiler. */ + + /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */ + + /* The start of the task code will be popped off the stack last, so place + * it on first. */ + usAddress = ( uint16_t ) pxCode; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + usAddress >>= 8; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + /* Next simulate the stack as if after a call to portSAVE_CONTEXT(). + * portSAVE_CONTEXT places the flags on the stack immediately after r0 + * to ensure the interrupts get disabled as soon as possible, and so ensuring + * the stack use is minimal should a context switch interrupt occur. */ + *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */ + pxTopOfStack--; + *pxTopOfStack = portFLAGS_INT_ENABLED; + pxTopOfStack--; + + + /* Now the remaining registers. The compiler expects R1 to be 0. */ + *pxTopOfStack = ( StackType_t ) 0x00; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x13; /* R13 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x14; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x15; /* R15 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x16; /* R16 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x17; /* R17 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x18; /* R18 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x19; /* R19 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x20; /* R20 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x21; /* R21 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x22; /* R22 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x23; /* R23 */ + pxTopOfStack--; + + /* Place the parameter on the stack in the expected location. */ + usAddress = ( uint16_t ) pvParameters; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + usAddress >>= 8; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0x26; /* R26 X */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x27; /* R27 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x28; /* R28 Y */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x29; /* R29 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x30; /* R30 Z */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x031; /* R31 */ + pxTopOfStack--; + + /*lint +e950 +e611 +e923 */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Setup the hardware to generate the tick. */ + prvSetupTimerInterrupt(); + + /* Restore the context of the first task that is going to run. */ + portRESTORE_CONTEXT(); + + /* Simulate a function call end as generated by the compiler. We will now + * jump to the start of the task the context of which we have just restored. */ + asm volatile ( "ret" ); + + /* Should not get here. */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the AVR port will get stopped. If required simply + * disable the tick interrupt here. */ +} +/*-----------------------------------------------------------*/ + +/* + * Manual context switch. The first thing we do is save the registers so we + * can use a naked attribute. + */ +void vPortYield( void ) __attribute__( ( naked ) ); +void vPortYield( void ) +{ + portSAVE_CONTEXT(); + vTaskSwitchContext(); + portRESTORE_CONTEXT(); + + asm volatile ( "ret" ); +} +/*-----------------------------------------------------------*/ + +/* + * Context switch function used by the tick. This must be identical to + * vPortYield() from the call to vTaskSwitchContext() onwards. The only + * difference from vPortYield() is the tick count is incremented as the + * call comes from the tick ISR. + */ +void vPortYieldFromTick( void ) __attribute__( ( naked ) ); +void vPortYieldFromTick( void ) +{ + portSAVE_CONTEXT(); + + if( xTaskIncrementTick() != pdFALSE ) + { + vTaskSwitchContext(); + } + + portRESTORE_CONTEXT(); + + asm volatile ( "ret" ); +} +/*-----------------------------------------------------------*/ + +/* + * Setup timer 1 compare match A to generate a tick interrupt. + */ +static void prvSetupTimerInterrupt( void ) +{ + uint32_t ulCompareMatch; + uint8_t ucHighByte, ucLowByte; + + /* Using 16bit timer 1 to generate the tick. Correct fuses must be + * selected for the configCPU_CLOCK_HZ clock. */ + + ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ; + + /* We only have 16 bits so have to scale to get our required tick rate. */ + ulCompareMatch /= portCLOCK_PRESCALER; + + /* Adjust for correct value. */ + ulCompareMatch -= ( uint32_t ) 1; + + /* Setup compare match value for compare match A. Interrupts are disabled + * before this is called so we need not worry here. */ + ucLowByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff ); + ulCompareMatch >>= 8; + ucHighByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff ); + OCR1AH = ucHighByte; + OCR1AL = ucLowByte; + + /* Setup clock source and compare match behaviour. */ + ucLowByte = portCLEAR_COUNTER_ON_MATCH | portPRESCALE_64; + TCCR1B = ucLowByte; + + /* Enable the interrupt - this is okay as interrupt are currently globally + * disabled. */ + ucLowByte = TIMSK; + ucLowByte |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE; + TIMSK = ucLowByte; +} +/*-----------------------------------------------------------*/ + +#if configUSE_PREEMPTION == 1 + +/* + * Tick ISR for preemptive scheduler. We can use a naked attribute as + * the context is saved at the start of vPortYieldFromTick(). The tick + * count is incremented after the context is saved. + */ + void TIMER1_COMPA_vect( void ) __attribute__( ( signal, naked ) ); + void TIMER1_COMPA_vect( void ) + { + vPortYieldFromTick(); + asm volatile ( "reti" ); + } +#else + +/* + * Tick ISR for the cooperative scheduler. All this does is increment the + * tick count. We don't need to switch context, this can only be done by + * manual calls to taskYIELD(); + */ + void TIMER1_COMPA_vect( void ) __attribute__( ( signal ) ); + void TIMER1_COMPA_vect( void ) + { + xTaskIncrementTick(); + } +#endif /* if configUSE_PREEMPTION == 1 */ diff --git a/portable/GCC/ATMega323/portmacro.h b/portable/GCC/ATMega323/portmacro.h new file mode 100644 index 000000000..6ed5e4295 --- /dev/null +++ b/portable/GCC/ATMega323/portmacro.h @@ -0,0 +1,117 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * Changes from V1.2.3 + * + + portCPU_CLOCK_HZ definition changed to 8MHz base 10, previously it + + base 16. + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE uint8_t +#define portBASE_TYPE char + +#define portPOINTER_SIZE_TYPE uint16_t + +typedef portSTACK_TYPE StackType_t; +typedef signed char BaseType_t; +typedef unsigned char UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +#define portENTER_CRITICAL() \ + asm volatile ( "in __tmp_reg__, __SREG__" ::); \ + asm volatile ( "cli" ::); \ + asm volatile ( "push __tmp_reg__" ::) + +#define portEXIT_CRITICAL() \ + asm volatile ( "pop __tmp_reg__" ::); \ + asm volatile ( "out __SREG__, __tmp_reg__" ::) + +#define portDISABLE_INTERRUPTS() asm volatile ( "cli" ::); +#define portENABLE_INTERRUPTS() asm volatile ( "sei" ::); +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 1 +#define portNOP() asm volatile ( "nop" ); +/*-----------------------------------------------------------*/ + +/* Kernel utilities. */ +extern void vPortYield( void ) __attribute__( ( naked ) ); +#define portYIELD() vPortYield() +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/AVR32_UC3/exception.S b/portable/GCC/AVR32_UC3/exception.S new file mode 100644 index 000000000..4e1b29703 --- /dev/null +++ b/portable/GCC/AVR32_UC3/exception.S @@ -0,0 +1,327 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT AND BSD-3-Clause + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Exception and interrupt vectors. + * + * This file maps all events supported by an AVR32UC. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: All AVR32UC devices with an INTC module can be used. + * - AppNote: + * + * \author Atmel Corporation (Now Microchip): + * https://www.microchip.com \n + * Support and FAQ: https://www.microchip.com/support/ + * + ******************************************************************************/ + +/* + * Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include +#include "intc.h" + + +//! @{ +//! \verbatim + + + .section .exception, "ax", @progbits + + +// Start of Exception Vector Table. + + // EVBA must be aligned with a power of two strictly greater than the EVBA- + // relative offset of the last vector. + .balign 0x200 + + // Export symbol. + .global _evba + .type _evba, @function +_evba: + + .org 0x000 + // Unrecoverable Exception. +_handle_Unrecoverable_Exception: + rjmp $ + + .org 0x004 + // TLB Multiple Hit: UNUSED IN AVR32UC. +_handle_TLB_Multiple_Hit: + rjmp $ + + .org 0x008 + // Bus Error Data Fetch. +_handle_Bus_Error_Data_Fetch: + rjmp $ + + .org 0x00C + // Bus Error Instruction Fetch. +_handle_Bus_Error_Instruction_Fetch: + rjmp $ + + .org 0x010 + // NMI. +_handle_NMI: + rjmp $ + + .org 0x014 + // Instruction Address. +_handle_Instruction_Address: + rjmp $ + + .org 0x018 + // ITLB Protection. +_handle_ITLB_Protection: + rjmp $ + + .org 0x01C + // Breakpoint. +_handle_Breakpoint: + rjmp $ + + .org 0x020 + // Illegal Opcode. +_handle_Illegal_Opcode: + rjmp $ + + .org 0x024 + // Unimplemented Instruction. +_handle_Unimplemented_Instruction: + rjmp $ + + .org 0x028 + // Privilege Violation. +_handle_Privilege_Violation: + rjmp $ + + .org 0x02C + // Floating-Point: UNUSED IN AVR32UC. +_handle_Floating_Point: + rjmp $ + + .org 0x030 + // Coprocessor Absent: UNUSED IN AVR32UC. +_handle_Coprocessor_Absent: + rjmp $ + + .org 0x034 + // Data Address (Read). +_handle_Data_Address_Read: + rjmp $ + + .org 0x038 + // Data Address (Write). +_handle_Data_Address_Write: + rjmp $ + + .org 0x03C + // DTLB Protection (Read). +_handle_DTLB_Protection_Read: + rjmp $ + + .org 0x040 + // DTLB Protection (Write). +_handle_DTLB_Protection_Write: + rjmp $ + + .org 0x044 + // DTLB Modified: UNUSED IN AVR32UC. +_handle_DTLB_Modified: + rjmp $ + + .org 0x050 + // ITLB Miss: UNUSED IN AVR32UC. +_handle_ITLB_Miss: + rjmp $ + + .org 0x060 + // DTLB Miss (Read): UNUSED IN AVR32UC. +_handle_DTLB_Miss_Read: + rjmp $ + + .org 0x070 + // DTLB Miss (Write): UNUSED IN AVR32UC. +_handle_DTLB_Miss_Write: + rjmp $ + + .org 0x100 + // Supervisor Call. +_handle_Supervisor_Call: + lda.w pc, SCALLYield + + +// Interrupt support. +// The interrupt controller must provide the offset address relative to EVBA. +// Important note: +// All interrupts call a C function named _get_interrupt_handler. +// This function will read group and interrupt line number to then return in +// R12 a pointer to a user-provided interrupt handler. + + .balign 4 + +_int0: + // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the + // CPU upon interrupt entry. +#if 1 // B1832: interrupt stack changed to exception stack if exception is detected. + mfsr r12, AVR32_SR + bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE + cp.w r12, 0b110 + brlo _int0_normal + lddsp r12, sp[0 * 4] + stdsp sp[6 * 4], r12 + lddsp r12, sp[1 * 4] + stdsp sp[7 * 4], r12 + lddsp r12, sp[3 * 4] + sub sp, -6 * 4 + rete +_int0_normal: +#endif + mov r12, 0 // Pass the int_lev parameter to the _get_interrupt_handler function. + call _get_interrupt_handler + cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. + movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. + rete // If this was a spurious interrupt (R12 == NULL), return from event handler. + +_int1: + // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the + // CPU upon interrupt entry. +#if 1 // B1832: interrupt stack changed to exception stack if exception is detected. + mfsr r12, AVR32_SR + bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE + cp.w r12, 0b110 + brlo _int1_normal + lddsp r12, sp[0 * 4] + stdsp sp[6 * 4], r12 + lddsp r12, sp[1 * 4] + stdsp sp[7 * 4], r12 + lddsp r12, sp[3 * 4] + sub sp, -6 * 4 + rete +_int1_normal: +#endif + mov r12, 1 // Pass the int_lev parameter to the _get_interrupt_handler function. + call _get_interrupt_handler + cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. + movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. + rete // If this was a spurious interrupt (R12 == NULL), return from event handler. + +_int2: + // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the + // CPU upon interrupt entry. +#if 1 // B1832: interrupt stack changed to exception stack if exception is detected. + mfsr r12, AVR32_SR + bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE + cp.w r12, 0b110 + brlo _int2_normal + lddsp r12, sp[0 * 4] + stdsp sp[6 * 4], r12 + lddsp r12, sp[1 * 4] + stdsp sp[7 * 4], r12 + lddsp r12, sp[3 * 4] + sub sp, -6 * 4 + rete +_int2_normal: +#endif + mov r12, 2 // Pass the int_lev parameter to the _get_interrupt_handler function. + call _get_interrupt_handler + cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. + movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. + rete // If this was a spurious interrupt (R12 == NULL), return from event handler. + +_int3: + // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the + // CPU upon interrupt entry. +#if 1 // B1832: interrupt stack changed to exception stack if exception is detected. + mfsr r12, AVR32_SR + bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE + cp.w r12, 0b110 + brlo _int3_normal + lddsp r12, sp[0 * 4] + stdsp sp[6 * 4], r12 + lddsp r12, sp[1 * 4] + stdsp sp[7 * 4], r12 + lddsp r12, sp[3 * 4] + sub sp, -6 * 4 + rete +_int3_normal: +#endif + mov r12, 3 // Pass the int_lev parameter to the _get_interrupt_handler function. + call _get_interrupt_handler + cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. + movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. + rete // If this was a spurious interrupt (R12 == NULL), return from event handler. + + +// Constant data area. + + .balign 4 + + // Values to store in the interrupt priority registers for the various interrupt priority levels. + // The interrupt priority registers contain the interrupt priority level and + // the EVBA-relative interrupt vector offset. + .global ipr_val + .type ipr_val, @object +ipr_val: + .word (INT0 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int0 - _evba),\ + (INT1 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int1 - _evba),\ + (INT2 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int2 - _evba),\ + (INT3 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int3 - _evba) + + +//! \endverbatim +//! @} diff --git a/portable/GCC/AVR32_UC3/port.c b/portable/GCC/AVR32_UC3/port.c new file mode 100644 index 000000000..984ef56a0 --- /dev/null +++ b/portable/GCC/AVR32_UC3/port.c @@ -0,0 +1,473 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT AND BSD-3-Clause + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*This file has been prepared for Doxygen automatic documentation generation.*/ + +/*! \file ********************************************************************* + * + * \brief FreeRTOS port source for AVR32 UC3. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation (Now Microchip): + * https://www.microchip.com \n + * Support and FAQ: https://www.microchip.com/support/ + * + *****************************************************************************/ + +/* + * Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* Standard includes. */ +#include +#include +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* AVR32 UC3 includes. */ +#include +#include "gpio.h" +#if ( configTICK_USE_TC == 1 ) + #include "tc.h" +#endif + + +/* Constants required to setup the task context. */ +#define portINITIAL_SR ( ( StackType_t ) 0x00400000 ) /* AVR32 : [M2:M0]=001 I1M=0 I0M=0, GM=0 */ +#define portINSTRUCTION_SIZE ( ( StackType_t ) 0 ) + +/* Each task maintains its own critical nesting variable. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) +volatile uint32_t ulCriticalNesting = 9999UL; + +#if ( configTICK_USE_TC == 0 ) + static void prvScheduleNextTick( void ); +#else + static void prvClearTcInt( void ); +#endif + +/* Setup the timer to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/*-----------------------------------------------------------*/ + +/* + * Low-level initialization routine called during startup, before the main + * function. + * This version comes in replacement to the default one provided by Newlib. + * Newlib's _init_startup only calls init_exceptions, but Newlib's exception + * vectors are not compatible with the SCALL management in the current FreeRTOS + * port. More low-level initializations are besides added here. + */ +void _init_startup( void ) +{ + /* Import the Exception Vector Base Address. */ + extern void _evba; + + #if configHEAP_INIT + extern void __heap_start__; + extern void __heap_end__; + BaseType_t * pxMem; + #endif + + /* Load the Exception Vector Base Address in the corresponding system register. */ + Set_system_register( AVR32_EVBA, ( int ) &_evba ); + + /* Enable exceptions. */ + ENABLE_ALL_EXCEPTIONS(); + + /* Initialize interrupt handling. */ + INTC_init_interrupts(); + + #if configHEAP_INIT + /* Initialize the heap used by malloc. */ + for( pxMem = &__heap_start__; pxMem < ( BaseType_t * ) &__heap_end__; ) + { + *pxMem++ = 0xA5A5A5A5; + } + #endif + + /* Give the used CPU clock frequency to Newlib, so it can work properly. */ + set_cpu_hz( configCPU_CLOCK_HZ ); + + /* Code section present if and only if the debug trace is activated. */ + #if configDBG + { + static const gpio_map_t DBG_USART_GPIO_MAP = + { + { configDBG_USART_RX_PIN, configDBG_USART_RX_FUNCTION }, + { configDBG_USART_TX_PIN, configDBG_USART_TX_FUNCTION } + }; + + /* Initialize the USART used for the debug trace with the configured parameters. */ + set_usart_base( ( void * ) configDBG_USART ); + gpio_enable_module( DBG_USART_GPIO_MAP, + sizeof( DBG_USART_GPIO_MAP ) / sizeof( DBG_USART_GPIO_MAP[ 0 ] ) ); + usart_init( configDBG_USART_BAUDRATE ); + } + #endif /* if configDBG */ +} +/*-----------------------------------------------------------*/ + +/* + * malloc, realloc and free are meant to be called through respectively + * pvPortMalloc, pvPortRealloc and vPortFree. + * The latter functions call the former ones from within sections where tasks + * are suspended, so the latter functions are task-safe. __malloc_lock and + * __malloc_unlock use the same mechanism to also keep the former functions + * task-safe as they may be called directly from Newlib's functions. + * However, all these functions are interrupt-unsafe and SHALL THEREFORE NOT BE + * CALLED FROM WITHIN AN INTERRUPT, because __malloc_lock and __malloc_unlock do + * not call portENTER_CRITICAL and portEXIT_CRITICAL in order not to disable + * interrupts during memory allocation management as this may be a very time- + * consuming process. + */ + +/* + * Lock routine called by Newlib on malloc / realloc / free entry to guarantee a + * safe section as memory allocation management uses global data. + * See the aforementioned details. + */ +void __malloc_lock( struct _reent * ptr ) +{ + vTaskSuspendAll(); +} + +/* + * Unlock routine called by Newlib on malloc / realloc / free exit to guarantee + * a safe section as memory allocation management uses global data. + * See the aforementioned details. + */ +void __malloc_unlock( struct _reent * ptr ) +{ + xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +/* Added as there is no such function in FreeRTOS. */ +void * pvPortRealloc( void * pv, + size_t xWantedSize ) +{ + void * pvReturn; + + vTaskSuspendAll(); + { + pvReturn = realloc( pv, xWantedSize ); + } + xTaskResumeAll(); + + return pvReturn; +} +/*-----------------------------------------------------------*/ + +/* The cooperative scheduler requires a normal IRQ service routine to + * simply increment the system tick. */ + +/* The preemptive scheduler is defined as "naked" as the full context is saved + * on entry as part of the context switch. */ +__attribute__( ( __naked__ ) ) static void vTick( void ) +{ + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT_OS_INT(); + + #if ( configTICK_USE_TC == 1 ) + /* Clear the interrupt flag. */ + prvClearTcInt(); + #else + + /* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ) + * clock cycles from now. */ + prvScheduleNextTick(); + #endif + + /* Because FreeRTOS is not supposed to run with nested interrupts, put all OS + * calls in a critical section . */ + portENTER_CRITICAL(); + xTaskIncrementTick(); + portEXIT_CRITICAL(); + + /* Restore the context of the "elected task". */ + portRESTORE_CONTEXT_OS_INT(); +} +/*-----------------------------------------------------------*/ + +__attribute__( ( __naked__ ) ) void SCALLYield( void ) +{ + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT_SCALL(); + vTaskSwitchContext(); + portRESTORE_CONTEXT_SCALL(); +} +/*-----------------------------------------------------------*/ + +/* The code generated by the GCC compiler uses the stack in different ways at + * different optimisation levels. The interrupt flags can therefore not always + * be saved to the stack. Instead the critical section nesting level is stored + * in a variable, which is then saved as part of the stack context. */ +__attribute__( ( __noinline__ ) ) void vPortEnterCritical( void ) +{ + /* Disable interrupts */ + portDISABLE_INTERRUPTS(); + + /* Now that interrupts are disabled, ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +__attribute__( ( __noinline__ ) ) void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + ulCriticalNesting--; + + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Enable all interrupt/exception. */ + portENABLE_INTERRUPTS(); + } + } +} +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Setup the initial stack of the task. The stack is set exactly as + * expected by the portRESTORE_CONTEXT() macro. */ + + /* When the task starts, it will expect to find the function parameter in R12. */ + pxTopOfStack--; + *pxTopOfStack-- = ( StackType_t ) 0x08080808; /* R8 */ + *pxTopOfStack-- = ( StackType_t ) 0x09090909; /* R9 */ + *pxTopOfStack-- = ( StackType_t ) 0x0A0A0A0A; /* R10 */ + *pxTopOfStack-- = ( StackType_t ) 0x0B0B0B0B; /* R11 */ + *pxTopOfStack-- = ( StackType_t ) pvParameters; /* R12 */ + *pxTopOfStack-- = ( StackType_t ) 0xDEADBEEF; /* R14/LR */ + *pxTopOfStack-- = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; /* R15/PC */ + *pxTopOfStack-- = ( StackType_t ) portINITIAL_SR; /* SR */ + *pxTopOfStack-- = ( StackType_t ) 0xFF0000FF; /* R0 */ + *pxTopOfStack-- = ( StackType_t ) 0x01010101; /* R1 */ + *pxTopOfStack-- = ( StackType_t ) 0x02020202; /* R2 */ + *pxTopOfStack-- = ( StackType_t ) 0x03030303; /* R3 */ + *pxTopOfStack-- = ( StackType_t ) 0x04040404; /* R4 */ + *pxTopOfStack-- = ( StackType_t ) 0x05050505; /* R5 */ + *pxTopOfStack-- = ( StackType_t ) 0x06060606; /* R6 */ + *pxTopOfStack-- = ( StackType_t ) 0x07070707; /* R7 */ + *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_NESTING; /* ulCriticalNesting */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + portRESTORE_CONTEXT(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the AVR32 port will require this function as there + * is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +/* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ) + * clock cycles from now. */ +#if ( configTICK_USE_TC == 0 ) + static void prvScheduleFirstTick( void ) + { + uint32_t lCycles; + + lCycles = Get_system_register( AVR32_COUNT ); + lCycles += ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ); + + /* If lCycles ends up to be 0, make it 1 so that the COMPARE and exception */ + /* generation feature does not get disabled. */ + if( 0 == lCycles ) + { + lCycles++; + } + + Set_system_register( AVR32_COMPARE, lCycles ); + } + + __attribute__( ( __noinline__ ) ) static void prvScheduleNextTick( void ) + { + uint32_t lCycles, lCount; + + lCycles = Get_system_register( AVR32_COMPARE ); + lCycles += ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ); + + /* If lCycles ends up to be 0, make it 1 so that the COMPARE and exception */ + /* generation feature does not get disabled. */ + if( 0 == lCycles ) + { + lCycles++; + } + + lCount = Get_system_register( AVR32_COUNT ); + + if( lCycles < lCount ) + { /* We missed a tick, recover for the next. */ + lCycles += ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ); + } + + Set_system_register( AVR32_COMPARE, lCycles ); + } +#else /* if ( configTICK_USE_TC == 0 ) */ + __attribute__( ( __noinline__ ) ) static void prvClearTcInt( void ) + { + AVR32_TC.channel[ configTICK_TC_CHANNEL ].sr; + } +#endif /* if ( configTICK_USE_TC == 0 ) */ +/*-----------------------------------------------------------*/ + +/* Setup the timer to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ) +{ + #if ( configTICK_USE_TC == 1 ) + volatile avr32_tc_t * tc = &AVR32_TC; + + /* Options for waveform generation. */ + tc_waveform_opt_t waveform_opt = + { + .channel = configTICK_TC_CHANNEL, /* Channel selection. */ + + .bswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOB. */ + .beevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOB. */ + .bcpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOB. */ + .bcpb = TC_EVT_EFFECT_NOOP, /* RB compare effect on TIOB. */ + + .aswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOA. */ + .aeevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOA. */ + .acpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOA: toggle. */ + .acpa = TC_EVT_EFFECT_NOOP, /* RA compare effect on TIOA: toggle (other possibilities are none, set and clear). */ + + .wavsel = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER, /* Waveform selection: Up mode without automatic trigger on RC compare. */ + .enetrg = FALSE, /* External event trigger enable. */ + .eevt = 0, /* External event selection. */ + .eevtedg = TC_SEL_NO_EDGE, /* External event edge selection. */ + .cpcdis = FALSE, /* Counter disable when RC compare. */ + .cpcstop = FALSE, /* Counter clock stopped with RC compare. */ + + .burst = FALSE, /* Burst signal selection. */ + .clki = FALSE, /* Clock inversion. */ + .tcclks = TC_CLOCK_SOURCE_TC2 /* Internal source clock 2. */ + }; + + tc_interrupt_t tc_interrupt = + { + .etrgs = 0, + .ldrbs = 0, + .ldras = 0, + .cpcs = 1, + .cpbs = 0, + .cpas = 0, + .lovrs = 0, + .covfs = 0, + }; + #endif /* if ( configTICK_USE_TC == 1 ) */ + + /* Disable all interrupt/exception. */ + portDISABLE_INTERRUPTS(); + + /* Register the compare interrupt handler to the interrupt controller and + * enable the compare interrupt. */ + + #if ( configTICK_USE_TC == 1 ) + { + INTC_register_interrupt( &vTick, configTICK_TC_IRQ, INT0 ); + + /* Initialize the timer/counter. */ + tc_init_waveform( tc, &waveform_opt ); + + /* Set the compare triggers. + * Remember TC counter is 16-bits, so counting second is not possible! + * That's why we configure it to count ms. */ + tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4 ) / configTICK_RATE_HZ ); + + tc_configure_interrupts( tc, configTICK_TC_CHANNEL, &tc_interrupt ); + + /* Start the timer/counter. */ + tc_start( tc, configTICK_TC_CHANNEL ); + } + #else /* if ( configTICK_USE_TC == 1 ) */ + { + INTC_register_interrupt( &vTick, AVR32_CORE_COMPARE_IRQ, INT0 ); + prvScheduleFirstTick(); + } + #endif /* if ( configTICK_USE_TC == 1 ) */ +} diff --git a/portable/GCC/AVR32_UC3/portmacro.h b/portable/GCC/AVR32_UC3/portmacro.h new file mode 100644 index 000000000..d96a629b5 --- /dev/null +++ b/portable/GCC/AVR32_UC3/portmacro.h @@ -0,0 +1,704 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT AND BSD-3-Clause + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*This file has been prepared for Doxygen automatic documentation generation.*/ + +/*! \file ********************************************************************* + * + * \brief FreeRTOS port source for AVR32 UC3. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation (Now Microchip): + * https://www.microchip.com \n + * Support and FAQ: https://www.microchip.com/support/ + * + *****************************************************************************/ + +/* + * Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ +#include +#include "intc.h" +#include "compiler.h" + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#define TASK_DELAY_MS( x ) ( ( x ) / portTICK_PERIOD_MS ) +#define TASK_DELAY_S( x ) ( ( x ) * 1000 / portTICK_PERIOD_MS ) +#define TASK_DELAY_MIN( x ) ( ( x ) * 60 * 1000 / portTICK_PERIOD_MS ) + +#define configTICK_TC_IRQ ATPASTE2( AVR32_TC_IRQ, configTICK_TC_CHANNEL ) + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +#define portNOP() { __asm__ __volatile__ ( "nop" ); } +/*-----------------------------------------------------------*/ + + +/*-----------------------------------------------------------*/ + +/* INTC-specific. */ +#define DISABLE_ALL_EXCEPTIONS() Disable_global_exception() +#define ENABLE_ALL_EXCEPTIONS() Enable_global_exception() + +#define DISABLE_ALL_INTERRUPTS() Disable_global_interrupt() +#define ENABLE_ALL_INTERRUPTS() Enable_global_interrupt() + +#define DISABLE_INT_LEVEL( int_lev ) Disable_interrupt_level( int_lev ) +#define ENABLE_INT_LEVEL( int_lev ) Enable_interrupt_level( int_lev ) + + +/* + * Debug trace. + * Activated if and only if configDBG is nonzero. + * Prints a formatted string to stdout. + * The current source file name and line number are output with a colon before + * the formatted string. + * A carriage return and a linefeed are appended to the output. + * stdout is redirected to the USART configured by configDBG_USART. + * The parameters are the same as for the standard printf function. + * There is no return value. + * SHALL NOT BE CALLED FROM WITHIN AN INTERRUPT as fputs and printf use malloc, + * which is interrupt-unsafe with the current __malloc_lock and __malloc_unlock. + */ +#if configDBG + #define portDBG_TRACE( ... ) \ + { \ + fputs( __FILE__ ":" ASTRINGZ( __LINE__ ) ": ", stdout ); \ + printf( __VA_ARGS__ ); \ + fputs( "\r\n", stdout ); \ + } +#else + #define portDBG_TRACE( ... ) +#endif + + +/* Critical section management. */ +#define portDISABLE_INTERRUPTS() DISABLE_ALL_INTERRUPTS() +#define portENABLE_INTERRUPTS() ENABLE_ALL_INTERRUPTS() + + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); + + +/* Added as there is no such function in FreeRTOS. */ +extern void * pvPortRealloc( void * pv, + size_t xSize ); +/*-----------------------------------------------------------*/ + + +/*=============================================================================================*/ + +/* + * Restore Context for cases other than INTi. + */ +#define portRESTORE_CONTEXT() \ + { \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void * volatile pxCurrentTCB; \ + \ + __asm__ __volatile__ ( \ + /* Set SP to point to new stack */ \ + "mov r8, LO(%[pxCurrentTCB]) \n\t" \ + "orh r8, HI(%[pxCurrentTCB]) \n\t" \ + "ld.w r0, r8[0] \n\t" \ + "ld.w sp, r0[0] \n\t" \ + \ + /* Restore ulCriticalNesting variable */ \ + "ld.w r0, sp++ \n\t" \ + "mov r8, LO(%[ulCriticalNesting]) \n\t" \ + "orh r8, HI(%[ulCriticalNesting]) \n\t" \ + "st.w r8[0], r0 \n\t" \ + \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t" \ + /* R0-R7 should not be used below this line */ \ + /* Skip PC and SR (will do it at the end) */ \ + "sub sp, -2*4 \n\t" \ + /* Restore R8..R12 and LR */ \ + "ldm sp++, r8-r12, lr \n\t" \ + /* Restore SR */ \ + "ld.w r0, sp[-8*4]\n\t" /* R0 is modified, is restored later. */ \ + "mtsr %[SR], r0 \n\t" \ + /* Restore r0 */ \ + "ld.w r0, sp[-9*4] \n\t" \ + /* Restore PC */ \ + "ld.w pc, sp[-7*4]" /* Get PC from stack - PC is the 7th register saved */ \ + : \ + :[ ulCriticalNesting ] "i" ( &ulCriticalNesting ), \ + [ pxCurrentTCB ] "i" ( &pxCurrentTCB ), \ + [ SR ] "i" ( AVR32_SR ) \ + ); \ + } + + +/* + * portSAVE_CONTEXT_INT() and portRESTORE_CONTEXT_INT(): for INT0..3 exceptions. + * portSAVE_CONTEXT_SCALL() and portRESTORE_CONTEXT_SCALL(): for the scall exception. + * + * Had to make different versions because registers saved on the system stack + * are not the same between INT0..3 exceptions and the scall exception. + */ + +/* Task context stack layout: */ +/* R8 (*) */ +/* R9 (*) */ +/* R10 (*) */ +/* R11 (*) */ +/* R12 (*) */ +/* R14/LR (*) */ +/* R15/PC (*) */ +/* SR (*) */ +/* R0 */ +/* R1 */ +/* R2 */ +/* R3 */ +/* R4 */ +/* R5 */ +/* R6 */ +/* R7 */ +/* ulCriticalNesting */ +/* (*) automatically done for INT0..INT3, but not for SCALL */ + +/* + * The ISR used for the scheduler tick depends on whether the cooperative or + * the preemptive scheduler is being used. + */ +#if configUSE_PREEMPTION == 0 + +/* + * portSAVE_CONTEXT_OS_INT() for OS Tick exception. + */ + #define portSAVE_CONTEXT_OS_INT() \ + { \ + /* Save R0..R7 */ \ + __asm__ __volatile__ ( "stm --sp, r0-r7" ); \ + \ + /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ + /* there is also no context save. */ \ + } + +/* + * portRESTORE_CONTEXT_OS_INT() for Tick exception. + */ + #define portRESTORE_CONTEXT_OS_INT() \ + { \ + __asm__ __volatile__ ( \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7\n\t" \ + \ + /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ + /* there is also no context restore. */ \ + "rete" \ + ); \ + } + +#else /* if configUSE_PREEMPTION == 0 */ + +/* + * portSAVE_CONTEXT_OS_INT() for OS Tick exception. + */ + #define portSAVE_CONTEXT_OS_INT() \ + { \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void * volatile pxCurrentTCB; \ + \ + /* When we come here */ \ + /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \ + \ + __asm__ __volatile__ ( \ + /* Save R0..R7 */ \ + "stm --sp, r0-r7 \n\t" \ + \ + /* Save ulCriticalNesting variable - R0 is overwritten */ \ + "mov r8, LO(%[ulCriticalNesting])\n\t" \ + "orh r8, HI(%[ulCriticalNesting])\n\t" \ + "ld.w r0, r8[0] \n\t" \ + "st.w --sp, r0 \n\t" \ + \ + /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ + /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ + /* level and allow other lower interrupt level to occur). */ \ + /* In this case we don't want to do a task switch because we don't know what the stack */ \ + /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \ + /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \ + /* will just be restoring the interrupt handler, no way!!! */ \ + /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \ + "ld.w r0, sp[9*4]\n\t" /* Read SR in stack */ \ + "bfextu r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */ \ + "cp.w r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */ \ + "brhi LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE] \n\t" \ + \ + /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \ + /* NOTE: we don't enter a critical section here because all interrupt handlers */ \ + /* MUST perform a SAVE_CONTEXT/RESTORE_CONTEXT in the same way as */ \ + /* portSAVE_CONTEXT_OS_INT/port_RESTORE_CONTEXT_OS_INT if they call OS functions. */ \ + /* => all interrupt handlers must use portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR. */ \ + "mov r8, LO(%[pxCurrentTCB])\n\t" \ + "orh r8, HI(%[pxCurrentTCB])\n\t" \ + "ld.w r0, r8[0]\n\t" \ + "st.w r0[0], sp\n" \ + \ + "LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE]:" \ + : \ + :[ ulCriticalNesting ] "i" ( &ulCriticalNesting ), \ + [ pxCurrentTCB ] "i" ( &pxCurrentTCB ), \ + [ LINE ] "i" ( __LINE__ ) \ + ); \ + } + +/* + * portRESTORE_CONTEXT_OS_INT() for Tick exception. + */ + #define portRESTORE_CONTEXT_OS_INT() \ + { \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void * volatile pxCurrentTCB; \ + \ + /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ + /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ + /* level and allow other lower interrupt level to occur). */ \ + /* In this case we don't want to do a task switch because we don't know what the stack */ \ + /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \ + /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \ + /* will just be restoring the interrupt handler, no way!!! */ \ + __asm__ __volatile__ ( \ + "ld.w r0, sp[9*4]\n\t" /* Read SR in stack */ \ + "bfextu r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */ \ + "cp.w r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */ \ + "brhi LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]" \ + : \ + :[ LINE ] "i" ( __LINE__ ) \ + ); \ + \ + /* Else */ \ + /* because it is here safe, always call vTaskSwitchContext() since an OS tick occurred. */ \ + /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */ \ + portENTER_CRITICAL(); \ + vTaskSwitchContext(); \ + portEXIT_CRITICAL(); \ + \ + /* Restore all registers */ \ + \ + __asm__ __volatile__ ( \ + /* Set SP to point to new stack */ \ + "mov r8, LO(%[pxCurrentTCB]) \n\t" \ + "orh r8, HI(%[pxCurrentTCB]) \n\t" \ + "ld.w r0, r8[0] \n\t" \ + "ld.w sp, r0[0] \n" \ + \ + "LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]: \n\t" \ + \ + /* Restore ulCriticalNesting variable */ \ + "ld.w r0, sp++ \n\t" \ + "mov r8, LO(%[ulCriticalNesting]) \n\t" \ + "orh r8, HI(%[ulCriticalNesting]) \n\t" \ + "st.w r8[0], r0 \n\t" \ + \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t" \ + \ + /* Now, the stack should be R8..R12, LR, PC and SR */ \ + "rete" \ + : \ + :[ ulCriticalNesting ] "i" ( &ulCriticalNesting ), \ + [ pxCurrentTCB ] "i" ( &pxCurrentTCB ), \ + [ LINE ] "i" ( __LINE__ ) \ + ); \ + } + +#endif /* if configUSE_PREEMPTION == 0 */ + + +/* + * portSAVE_CONTEXT_SCALL() for SupervisorCALL exception. + * + * NOTE: taskYIELD()(== SCALL) MUST NOT be called in a mode > supervisor mode. + * + */ +#define portSAVE_CONTEXT_SCALL() \ + { \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void * volatile pxCurrentTCB; \ + \ + /* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */ \ + /* If SR[M2:M0] == 001 */ \ + /* PC and SR are on the stack. */ \ + /* Else (other modes) */ \ + /* Nothing on the stack. */ \ + \ + /* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */ \ + /* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */ \ + /* in an interrupt|exception handler. */ \ + \ + __asm__ __volatile__ ( \ + /* in order to save R0-R7 */ \ + "sub sp, 6*4 \n\t" \ + /* Save R0..R7 */ \ + "stm --sp, r0-r7 \n\t" \ + \ + /* in order to save R8-R12 and LR */ \ + /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \ + "sub r7, sp,-16*4 \n\t" \ + /* Copy PC and SR in other places in the stack. */ \ + "ld.w r0, r7[-2*4] \n\t" /* Read SR */ \ + "st.w r7[-8*4], r0 \n\t" /* Copy SR */ \ + "ld.w r0, r7[-1*4] \n\t" /* Read PC */ \ + "st.w r7[-7*4], r0 \n\t" /* Copy PC */ \ + \ + /* Save R8..R12 and LR on the stack. */ \ + "stm --r7, r8-r12, lr \n\t" \ + \ + /* Arriving here we have the following stack organizations: */ \ + /* R8..R12, LR, PC, SR, R0..R7. */ \ + \ + /* Now we can finalize the save. */ \ + \ + /* Save ulCriticalNesting variable - R0 is overwritten */ \ + "mov r8, LO(%[ulCriticalNesting]) \n\t" \ + "orh r8, HI(%[ulCriticalNesting]) \n\t" \ + "ld.w r0, r8[0] \n\t" \ + "st.w --sp, r0" \ + : \ + :[ ulCriticalNesting ] "i" ( &ulCriticalNesting ) \ + ); \ + \ + /* Disable the its which may cause a context switch (i.e. cause a change of */ \ + /* pxCurrentTCB). */ \ + /* Basically, all accesses to the pxCurrentTCB structure should be put in a */ \ + /* critical section because it is a global structure. */ \ + portENTER_CRITICAL(); \ + \ + /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \ + __asm__ __volatile__ ( \ + "mov r8, LO(%[pxCurrentTCB]) \n\t" \ + "orh r8, HI(%[pxCurrentTCB]) \n\t" \ + "ld.w r0, r8[0] \n\t" \ + "st.w r0[0], sp" \ + : \ + :[ pxCurrentTCB ] "i" ( &pxCurrentTCB ) \ + ); \ + } + +/* + * portRESTORE_CONTEXT() for SupervisorCALL exception. + */ +#define portRESTORE_CONTEXT_SCALL() \ + { \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void * volatile pxCurrentTCB; \ + \ + /* Restore all registers */ \ + \ + /* Set SP to point to new stack */ \ + __asm__ __volatile__ ( \ + "mov r8, LO(%[pxCurrentTCB]) \n\t" \ + "orh r8, HI(%[pxCurrentTCB]) \n\t" \ + "ld.w r0, r8[0] \n\t" \ + "ld.w sp, r0[0]" \ + : \ + :[ pxCurrentTCB ] "i" ( &pxCurrentTCB ) \ + ); \ + \ + /* Leave pxCurrentTCB variable access critical section */ \ + portEXIT_CRITICAL(); \ + \ + __asm__ __volatile__ ( \ + /* Restore ulCriticalNesting variable */ \ + "ld.w r0, sp++ \n\t" \ + "mov r8, LO(%[ulCriticalNesting]) \n\t" \ + "orh r8, HI(%[ulCriticalNesting]) \n\t" \ + "st.w r8[0], r0 \n\t" \ + \ + /* skip PC and SR */ \ + /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \ + "sub r7, sp, -10*4 \n\t" \ + /* Restore r8-r12 and LR */ \ + "ldm r7++, r8-r12, lr \n\t" \ + \ + /* RETS will take care of the extra PC and SR restore. */ \ + /* So, we have to prepare the stack for this. */ \ + "ld.w r0, r7[-8*4] \n\t" /* Read SR */ \ + "st.w r7[-2*4], r0 \n\t" /* Copy SR */ \ + "ld.w r0, r7[-7*4] \n\t" /* Read PC */ \ + "st.w r7[-1*4], r0 \n\t" /* Copy PC */ \ + \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t" \ + \ + "sub sp, -6*4 \n\t" \ + \ + "rets" \ + : \ + :[ ulCriticalNesting ] "i" ( &ulCriticalNesting ) \ + ); \ + } + + +/* + * The ISR used depends on whether the cooperative or + * the preemptive scheduler is being used. + */ +#if configUSE_PREEMPTION == 0 + +/* + * ISR entry and exit macros. These are only required if a task switch + * is required from the ISR. + */ + #define portENTER_SWITCHING_ISR() \ + { \ + /* Save R0..R7 */ \ + __asm__ __volatile__ ( "stm --sp, r0-r7" ); \ + \ + /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ + /* there is also no context save. */ \ + } + +/* + * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1 + */ + #define portEXIT_SWITCHING_ISR() \ + { \ + __asm__ __volatile__ ( \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t" \ + \ + /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ + /* there is also no context restore. */ \ + "rete" \ + ); \ + } + +#else /* if configUSE_PREEMPTION == 0 */ + +/* + * ISR entry and exit macros. These are only required if a task switch + * is required from the ISR. + */ + #define portENTER_SWITCHING_ISR() \ + { \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void * volatile pxCurrentTCB; \ + \ + /* When we come here */ \ + /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \ + \ + __asm__ __volatile__ ( \ + /* Save R0..R7 */ \ + "stm --sp, r0-r7 \n\t" \ + \ + /* Save ulCriticalNesting variable - R0 is overwritten */ \ + "mov r8, LO(%[ulCriticalNesting]) \n\t" \ + "orh r8, HI(%[ulCriticalNesting]) \n\t" \ + "ld.w r0, r8[0] \n\t" \ + "st.w --sp, r0 \n\t" \ + \ + /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ + /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ + /* level and allow other lower interrupt level to occur). */ \ + /* In this case we don't want to do a task switch because we don't know what the stack */ \ + /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \ + /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \ + /* will just be restoring the interrupt handler, no way!!! */ \ + /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \ + "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */ \ + "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */ \ + "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */ \ + "brhi LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE] \n\t" \ + \ + /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \ + "mov r8, LO(%[pxCurrentTCB]) \n\t" \ + "orh r8, HI(%[pxCurrentTCB]) \n\t" \ + "ld.w r0, r8[0] \n\t" \ + "st.w r0[0], sp \n" \ + \ + "LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE]:" \ + : \ + :[ ulCriticalNesting ] "i" ( &ulCriticalNesting ), \ + [ pxCurrentTCB ] "i" ( &pxCurrentTCB ), \ + [ LINE ] "i" ( __LINE__ ) \ + ); \ + } + +/* + * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1 + */ + #define portEXIT_SWITCHING_ISR() \ + { \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void * volatile pxCurrentTCB; \ + \ + __asm__ __volatile__ ( \ + /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ + /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ + /* level and allow other lower interrupt level to occur). */ \ + /* In this case it's of no use to switch context and restore a new SP because we purposely */ \ + /* did not previously save SP in its TCB. */ \ + "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */ \ + "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */ \ + "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */ \ + "brhi LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE] \n\t" \ + \ + /* If a switch is required then we just need to call */ \ + /* vTaskSwitchContext() as the context has already been */ \ + /* saved. */ \ + "cp.w r12, 1 \n\t" /* Check if Switch context is required. */ \ + "brne LABEL_ISR_RESTORE_CONTEXT_%[LINE]" \ + : \ + :[ LINE ] "i" ( __LINE__ ) \ + ); \ + \ + /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */ \ + portENTER_CRITICAL(); \ + vTaskSwitchContext(); \ + portEXIT_CRITICAL(); \ + \ + __asm__ __volatile__ ( \ + "LABEL_ISR_RESTORE_CONTEXT_%[LINE]: \n\t" \ + /* Restore the context of which ever task is now the highest */ \ + /* priority that is ready to run. */ \ + \ + /* Restore all registers */ \ + \ + /* Set SP to point to new stack */ \ + "mov r8, LO(%[pxCurrentTCB]) \n\t" \ + "orh r8, HI(%[pxCurrentTCB]) \n\t" \ + "ld.w r0, r8[0] \n\t" \ + "ld.w sp, r0[0] \n" \ + \ + "LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE]: \n\t" \ + \ + /* Restore ulCriticalNesting variable */ \ + "ld.w r0, sp++ \n\t" \ + "mov r8, LO(%[ulCriticalNesting]) \n\t" \ + "orh r8, HI(%[ulCriticalNesting]) \n\t" \ + "st.w r8[0], r0 \n\t" \ + \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t" \ + \ + /* Now, the stack should be R8..R12, LR, PC and SR */ \ + "rete" \ + : \ + :[ ulCriticalNesting ] "i" ( &ulCriticalNesting ), \ + [ pxCurrentTCB ] "i" ( &pxCurrentTCB ), \ + [ LINE ] "i" ( __LINE__ ) \ + ); \ + } + +#endif /* if configUSE_PREEMPTION == 0 */ + + +#define portYIELD() { __asm__ __volatile__ ( "scall" ); } + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/AVR_AVRDx/README.md b/portable/GCC/AVR_AVRDx/README.md new file mode 100644 index 000000000..af5856aba --- /dev/null +++ b/portable/GCC/AVR_AVRDx/README.md @@ -0,0 +1 @@ +This port has been moved to `portable/ThirdParty/Partner-Supported-Ports/GCC/AVR_AVRDx` directory. diff --git a/portable/GCC/AVR_Mega0/README.md b/portable/GCC/AVR_Mega0/README.md new file mode 100644 index 000000000..c83311f71 --- /dev/null +++ b/portable/GCC/AVR_Mega0/README.md @@ -0,0 +1 @@ +This port has been moved to `portable/ThirdParty/Partner-Supported-Ports/GCC/AVR_Mega0` directory. diff --git a/portable/GCC/CORTUS_APS3/port.c b/portable/GCC/CORTUS_APS3/port.c new file mode 100644 index 000000000..8ea06df16 --- /dev/null +++ b/portable/GCC/CORTUS_APS3/port.c @@ -0,0 +1,148 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Machine includes */ +#include +#include +/*-----------------------------------------------------------*/ + +/* The initial PSR has the Previous Interrupt Enabled (PIEN) flag set. */ +#define portINITIAL_PSR ( 0x00020000 ) + +/*-----------------------------------------------------------*/ + +/* + * Perform any hardware configuration necessary to generate the tick interrupt. + */ +static void prvSetupTimerInterrupt( void ); +/*-----------------------------------------------------------*/ + +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Make space on the stack for the context - this leaves a couple of spaces + * empty. */ + pxTopOfStack -= 20; + + /* Fill the registers with known values to assist debugging. */ + pxTopOfStack[ 16 ] = 0; + pxTopOfStack[ 15 ] = portINITIAL_PSR; + pxTopOfStack[ 14 ] = ( uint32_t ) pxCode; + pxTopOfStack[ 13 ] = 0x00000000UL; /* R15. */ + pxTopOfStack[ 12 ] = 0x00000000UL; /* R14. */ + pxTopOfStack[ 11 ] = 0x0d0d0d0dUL; + pxTopOfStack[ 10 ] = 0x0c0c0c0cUL; + pxTopOfStack[ 9 ] = 0x0b0b0b0bUL; + pxTopOfStack[ 8 ] = 0x0a0a0a0aUL; + pxTopOfStack[ 7 ] = 0x09090909UL; + pxTopOfStack[ 6 ] = 0x08080808UL; + pxTopOfStack[ 5 ] = 0x07070707UL; + pxTopOfStack[ 4 ] = 0x06060606UL; + pxTopOfStack[ 3 ] = 0x05050505UL; + pxTopOfStack[ 2 ] = 0x04040404UL; + pxTopOfStack[ 1 ] = 0x03030303UL; + pxTopOfStack[ 0 ] = ( uint32_t ) pvParameters; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Set-up the timer interrupt. */ + prvSetupTimerInterrupt(); + + /* Integrated Interrupt Controller: Enable all interrupts. */ + ic->ien = 1; + + /* Restore callee saved registers. */ + portRESTORE_CONTEXT(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ + /* Enable timer interrupts */ + counter1->reload = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1; + counter1->value = counter1->reload; + counter1->mask = 1; + + /* Set the IRQ Handler priority and enable it. */ + irq[ IRQ_COUNTER1 ].ien = 1; +} +/*-----------------------------------------------------------*/ + +/* Trap 31 handler. */ +void interrupt31_handler( void ) __attribute__( ( naked ) ); +void interrupt31_handler( void ) +{ + portSAVE_CONTEXT(); + __asm volatile ( "call vTaskSwitchContext" ); + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +static void prvProcessTick( void ) __attribute__( ( noinline ) ); +static void prvProcessTick( void ) +{ + if( xTaskIncrementTick() != pdFALSE ) + { + vTaskSwitchContext(); + } + + /* Clear the Tick Interrupt. */ + counter1->expired = 0; +} +/*-----------------------------------------------------------*/ + +/* Timer 1 interrupt handler, used for tick interrupt. */ +void interrupt7_handler( void ) __attribute__( ( naked ) ); +void interrupt7_handler( void ) +{ + portSAVE_CONTEXT(); + prvProcessTick(); + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Nothing to do. Unlikely to want to end. */ +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/CORTUS_APS3/portmacro.h b/portable/GCC/CORTUS_APS3/portmacro.h new file mode 100644 index 000000000..a18af0f6f --- /dev/null +++ b/portable/GCC/CORTUS_APS3/portmacro.h @@ -0,0 +1,159 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +#include + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +#define portNOP() __asm__ volatile ( "mov r0, r0" ) +#define portCRITICAL_NESTING_IN_TCB 1 +#define portIRQ_TRAP_YIELD 31 +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +extern void vPortYield( void ); + +/*---------------------------------------------------------------------------*/ + +#define portYIELD() asm __volatile__ ( " trap #%0 " : : "i" ( portIRQ_TRAP_YIELD ) : "memory" ) +/*---------------------------------------------------------------------------*/ + +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() +/*---------------------------------------------------------------------------*/ + +/* Critical section management. */ +#define portDISABLE_INTERRUPTS() cpu_int_disable() +#define portENABLE_INTERRUPTS() cpu_int_enable() + +/*---------------------------------------------------------------------------*/ + +#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) do { if( xHigherPriorityTaskWoken != pdFALSE ) vTaskSwitchContext( ); } while( 0 ) + +/*---------------------------------------------------------------------------*/ + +#define portSAVE_CONTEXT() \ + asm __volatile__ \ + ( \ + "sub r1, #68 \n" /* Make space on the stack for the context. */ \ + "std r2, [r1] + 0 \n" \ + "stq r4, [r1] + 8 \n" \ + "stq r8, [r1] + 24 \n" \ + "stq r12, [r1] + 40 \n" \ + "mov r6, rtt \n" \ + "mov r7, psr \n" \ + "std r6, [r1] + 56 \n" \ + "movhi r2, #16384 \n" /* Set the pointer to the IC. */ \ + "ldub r3, [r2] + 2 \n" /* Load the current interrupt mask. */ \ + "st r3, [r1]+ 64 \n" /* Store the interrupt mask on the stack. */ \ + "ld r2, [r0]+short(pxCurrentTCB) \n" /* Load the pointer to the TCB. */ \ + "st r1, [r2] \n" /* Save the stack pointer into the TCB. */ \ + "mov r14, r1 \n" /* Compiler expects r14 to be set to the function stack. */ \ + ); +/*---------------------------------------------------------------------------*/ + +#define portRESTORE_CONTEXT() \ + asm __volatile__ ( \ + "ld r2, [r0]+short(pxCurrentTCB) \n" /* Load the TCB to find the stack pointer and context. */ \ + "ld r1, [r2] \n" \ + "movhi r2, #16384 \n" /* Set the pointer to the IC. */ \ + "ld r3, [r1] + 64 \n" /* Load the previous interrupt mask. */ \ + "stb r3, [r2] + 2 \n" /* Set the current interrupt mask to be the previous. */ \ + "ldd r6, [r1] + 56 \n" /* Restore context. */ \ + "mov rtt, r6 \n" \ + "mov psr, r7 \n" \ + "ldd r2, [r1] + 0 \n" \ + "ldq r4, [r1] + 8 \n" \ + "ldq r8, [r1] + 24 \n" \ + "ldq r12, [r1] + 40 \n" \ + "add r1, #68 \n" \ + "rti \n" \ + ); + +/*---------------------------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*---------------------------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/ColdFire_V2/port.c b/portable/GCC/ColdFire_V2/port.c new file mode 100644 index 000000000..e3bbb6b9e --- /dev/null +++ b/portable/GCC/ColdFire_V2/port.c @@ -0,0 +1,133 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#define portINITIAL_FORMAT_VECTOR ( ( StackType_t ) 0x4000 ) + +/* Supervisor mode set. */ +#define portINITIAL_STATUS_REGISTER ( ( StackType_t ) 0x2000 ) + +/* Used to keep track of the number of nested calls to taskENTER_CRITICAL(). This + * will be set to 0 prior to the first task being started. */ +static uint32_t ulCriticalNesting = 0x9999UL; + +/*-----------------------------------------------------------*/ + +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + *pxTopOfStack = ( StackType_t ) pvParameters; + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0xDEADBEEF; + pxTopOfStack--; + + /* Exception stack frame starts with the return address. */ + *pxTopOfStack = ( StackType_t ) pxCode; + pxTopOfStack--; + + *pxTopOfStack = ( portINITIAL_FORMAT_VECTOR << 16UL ) | ( portINITIAL_STATUS_REGISTER ); + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0x0; /*FP*/ + pxTopOfStack -= 14; /* A5 to D0. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + extern void vPortStartFirstTask( void ); + + ulCriticalNesting = 0UL; + + /* Configure the interrupts used by this port. */ + vApplicationSetupInterrupts(); + + /* Start the first task executing. */ + vPortStartFirstTask(); + + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented as there is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + if( ulCriticalNesting == 0UL ) + { + /* Guard against context switches being pended simultaneously with a + * critical section being entered. */ + do + { + portDISABLE_INTERRUPTS(); + + if( MCF_INTC0_INTFRCL == 0UL ) + { + break; + } + + portENABLE_INTERRUPTS(); + } while( 1 ); + } + + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void vPortYieldHandler( void ) +{ + uint32_t ulSavedInterruptMask; + + ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR(); + /* Note this will clear all forced interrupts - this is done for speed. */ + MCF_INTC0_INTFRCL = 0; + vTaskSwitchContext(); + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask ); +} diff --git a/portable/GCC/ColdFire_V2/portasm.S b/portable/GCC/ColdFire_V2/portasm.S new file mode 100644 index 000000000..4b746ca22 --- /dev/null +++ b/portable/GCC/ColdFire_V2/portasm.S @@ -0,0 +1,119 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * Purpose: Lowest level routines for all ColdFire processors. + * + * Notes: + * + * ulPortSetIPL() and mcf5xxx_wr_cacr() copied with permission from FreeScale + * supplied source files. + */ + + .global ulPortSetIPL + .global mcf5xxx_wr_cacr + .global __cs3_isr_interrupt_80 + .global vPortStartFirstTask + + .text + +.macro portSAVE_CONTEXT + + lea.l (-60, %sp), %sp + movem.l %d0-%fp, (%sp) + move.l pxCurrentTCB, %a0 + move.l %sp, (%a0) + + .endm + +.macro portRESTORE_CONTEXT + + move.l pxCurrentTCB, %a0 + move.l (%a0), %sp + movem.l (%sp), %d0-%fp + lea.l %sp@(60), %sp + rte + + .endm + +/********************************************************************/ +/* + * This routines changes the IPL to the value passed into the routine. + * It also returns the old IPL value back. + * Calling convention from C: + * old_ipl = asm_set_ipl(new_ipl); + * For the Diab Data C compiler, it passes return value thru D0. + * Note that only the least significant three bits of the passed + * value are used. + */ + +ulPortSetIPL: + link A6,#-8 + movem.l D6-D7,(SP) + + move.w SR,D7 /* current sr */ + + move.l D7,D0 /* prepare return value */ + andi.l #0x0700,D0 /* mask out IPL */ + lsr.l #8,D0 /* IPL */ + + move.l 8(A6),D6 /* get argument */ + andi.l #0x07,D6 /* least significant three bits */ + lsl.l #8,D6 /* move over to make mask */ + + andi.l #0x0000F8FF,D7 /* zero out current IPL */ + or.l D6,D7 /* place new IPL in sr */ + move.w D7,SR + + movem.l (SP),D6-D7 + lea 8(SP),SP + unlk A6 + rts +/********************************************************************/ + +mcf5xxx_wr_cacr: + move.l 4(sp),d0 + .long 0x4e7b0002 /* movec d0,cacr */ + nop + rts + +/********************************************************************/ + +/* Yield interrupt. */ +__cs3_isr_interrupt_80: + portSAVE_CONTEXT + jsr vPortYieldHandler + portRESTORE_CONTEXT + +/********************************************************************/ + + +vPortStartFirstTask: + portRESTORE_CONTEXT + + .end diff --git a/portable/GCC/ColdFire_V2/portmacro.h b/portable/GCC/ColdFire_V2/portmacro.h new file mode 100644 index 000000000..95381ab36 --- /dev/null +++ b/portable/GCC/ColdFire_V2/portmacro.h @@ -0,0 +1,129 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 4 +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +/*-----------------------------------------------------------*/ +uint32_t ulPortSetIPL( uint32_t ); +#define portDISABLE_INTERRUPTS() ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#define portENABLE_INTERRUPTS() ulPortSetIPL( 0 ) + + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() + +extern UBaseType_t uxPortSetInterruptMaskFromISR( void ); +extern void vPortClearInterruptMaskFromISR( UBaseType_t ); +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) ulPortSetIPL( uxSavedStatusRegister ) + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +#define portNOP() asm volatile ( "nop" ) + +/* Note this will overwrite all other bits in the force register, it is done this way for speed. */ +#define portYIELD() MCF_INTC0_INTFRCL = ( 1UL << configYIELD_INTERRUPT_VECTOR ); portNOP(); portNOP() + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) __attribute__( ( noreturn ) ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portYIELD(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) + + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/H8S2329/port.c b/portable/GCC/H8S2329/port.c new file mode 100644 index 000000000..f8693b37b --- /dev/null +++ b/portable/GCC/H8S2329/port.c @@ -0,0 +1,304 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the H8S port. +*----------------------------------------------------------*/ + + +/*-----------------------------------------------------------*/ + +/* When the task starts interrupts should be enabled. */ +#define portINITIAL_CCR ( ( StackType_t ) 0x00 ) + +/* Hardware specific constants used to generate the RTOS tick from the TPU. */ +#define portCLEAR_ON_TGRA_COMPARE_MATCH ( ( uint8_t ) 0x20 ) +#define portCLOCK_DIV_64 ( ( uint8_t ) 0x03 ) +#define portCLOCK_DIV ( ( uint32_t ) 64 ) +#define portTGRA_INTERRUPT_ENABLE ( ( uint8_t ) 0x01 ) +#define portTIMER_CHANNEL ( ( uint8_t ) 0x02 ) +#define portMSTP13 ( ( uint16_t ) 0x2000 ) + +/* + * Setup TPU channel one for the RTOS tick at the requested frequency. + */ +static void prvSetupTimerInterrupt( void ); + +/* + * The ISR used by portYIELD(). This is installed as a trap handler. + */ +void vPortYield( void ) __attribute__( ( saveall, interrupt_handler ) ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + uint32_t ulValue; + + /* This requires an even address. */ + ulValue = ( uint32_t ) pxTopOfStack; + + if( ulValue & 1UL ) + { + pxTopOfStack = pxTopOfStack - 1; + } + + /* Place a few bytes of known values on the bottom of the stack. + * This is just useful for debugging. */ + pxTopOfStack--; + *pxTopOfStack = 0xaa; + pxTopOfStack--; + *pxTopOfStack = 0xbb; + pxTopOfStack--; + *pxTopOfStack = 0xcc; + pxTopOfStack--; + *pxTopOfStack = 0xdd; + + /* The initial stack mimics an interrupt stack. First there is the program + * counter (24 bits). */ + ulValue = ( uint32_t ) pxCode; + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) ( ulValue & 0xff ); + pxTopOfStack--; + ulValue >>= 8UL; + *pxTopOfStack = ( StackType_t ) ( ulValue & 0xff ); + pxTopOfStack--; + ulValue >>= 8UL; + *pxTopOfStack = ( StackType_t ) ( ulValue & 0xff ); + + /* Followed by the CCR. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_CCR; + + /* Next all the general purpose registers - with the parameters being passed + * in ER0. The parameter order must match that used by the compiler when the + * "saveall" function attribute is used. */ + + /* ER6 */ + pxTopOfStack--; + *pxTopOfStack = 0x66; + pxTopOfStack--; + *pxTopOfStack = 0x66; + pxTopOfStack--; + *pxTopOfStack = 0x66; + pxTopOfStack--; + *pxTopOfStack = 0x66; + + /* ER0 */ + ulValue = ( uint32_t ) pvParameters; + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) ( ulValue & 0xff ); + pxTopOfStack--; + ulValue >>= 8UL; + *pxTopOfStack = ( StackType_t ) ( ulValue & 0xff ); + pxTopOfStack--; + ulValue >>= 8UL; + *pxTopOfStack = ( StackType_t ) ( ulValue & 0xff ); + pxTopOfStack--; + ulValue >>= 8UL; + *pxTopOfStack = ( StackType_t ) ( ulValue & 0xff ); + + /* ER1 */ + pxTopOfStack--; + *pxTopOfStack = 0x11; + pxTopOfStack--; + *pxTopOfStack = 0x11; + pxTopOfStack--; + *pxTopOfStack = 0x11; + pxTopOfStack--; + *pxTopOfStack = 0x11; + + /* ER2 */ + pxTopOfStack--; + *pxTopOfStack = 0x22; + pxTopOfStack--; + *pxTopOfStack = 0x22; + pxTopOfStack--; + *pxTopOfStack = 0x22; + pxTopOfStack--; + *pxTopOfStack = 0x22; + + /* ER3 */ + pxTopOfStack--; + *pxTopOfStack = 0x33; + pxTopOfStack--; + *pxTopOfStack = 0x33; + pxTopOfStack--; + *pxTopOfStack = 0x33; + pxTopOfStack--; + *pxTopOfStack = 0x33; + + /* ER4 */ + pxTopOfStack--; + *pxTopOfStack = 0x44; + pxTopOfStack--; + *pxTopOfStack = 0x44; + pxTopOfStack--; + *pxTopOfStack = 0x44; + pxTopOfStack--; + *pxTopOfStack = 0x44; + + /* ER5 */ + pxTopOfStack--; + *pxTopOfStack = 0x55; + pxTopOfStack--; + *pxTopOfStack = 0x55; + pxTopOfStack--; + *pxTopOfStack = 0x55; + pxTopOfStack--; + *pxTopOfStack = 0x55; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + extern void * pxCurrentTCB; + + /* Setup the hardware to generate the tick. */ + prvSetupTimerInterrupt(); + + /* Restore the context of the first task that is going to run. This + * mirrors the function epilogue code generated by the compiler when the + * "saveall" function attribute is used. */ + asm volatile ( + "MOV.L @_pxCurrentTCB, ER6 \n\t" + "MOV.L @ER6, ER7 \n\t" + "LDM.L @SP+, (ER4-ER5) \n\t" + "LDM.L @SP+, (ER0-ER3) \n\t" + "MOV.L @ER7+, ER6 \n\t" + "RTE \n\t" + ); + + ( void ) pxCurrentTCB; + + /* Should not get here. */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the h8 port will get stopped. */ +} +/*-----------------------------------------------------------*/ + +/* + * Manual context switch. This is a trap handler. The "saveall" function + * attribute is used so the context is saved by the compiler prologue. All + * we have to do is save the stack pointer. + */ +void vPortYield( void ) +{ + portSAVE_STACK_POINTER(); + vTaskSwitchContext(); + portRESTORE_STACK_POINTER(); +} +/*-----------------------------------------------------------*/ + +/* + * The interrupt handler installed for the RTOS tick depends on whether the + * preemptive or cooperative scheduler is being used. + */ +#if ( configUSE_PREEMPTION == 1 ) + +/* + * The preemptive scheduler is used so the ISR calls vTaskSwitchContext(). + * The function prologue saves the context so all we have to do is save + * the stack pointer. + */ + void vTickISR( void ) __attribute__( ( saveall, interrupt_handler ) ); + void vTickISR( void ) + { + portSAVE_STACK_POINTER(); + + if( xTaskIncrementTick() != pdFALSE ) + { + vTaskSwitchContext(); + } + + /* Clear the interrupt. */ + TSR1 &= ~0x01; + + portRESTORE_STACK_POINTER(); + } + +#else /* if ( configUSE_PREEMPTION == 1 ) */ + +/* + * The cooperative scheduler is being used so all we have to do is + * periodically increment the tick. This can just be a normal ISR and + * the "saveall" attribute is not required. + */ + void vTickISR( void ) __attribute__( ( interrupt_handler ) ); + void vTickISR( void ) + { + xTaskIncrementTick(); + + /* Clear the interrupt. */ + TSR1 &= ~0x01; + } + +#endif /* if ( configUSE_PREEMPTION == 1 ) */ +/*-----------------------------------------------------------*/ + +/* + * Setup timer 1 compare match to generate a tick interrupt. + */ +static void prvSetupTimerInterrupt( void ) +{ + const uint32_t ulCompareMatch = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) / portCLOCK_DIV; + + /* Turn the module on. */ + MSTPCR &= ~portMSTP13; + + /* Configure timer 1. */ + TCR1 = portCLEAR_ON_TGRA_COMPARE_MATCH | portCLOCK_DIV_64; + + /* Configure the compare match value for a tick of configTICK_RATE_HZ. */ + TGR1A = ulCompareMatch; + + /* Start the timer and enable the interrupt - we can do this here as + * interrupts are globally disabled when this function is called. */ + TIER1 |= portTGRA_INTERRUPT_ENABLE; + TSTR |= portTIMER_CHANNEL; +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/H8S2329/portmacro.h b/portable/GCC/H8S2329/portmacro.h new file mode 100644 index 000000000..a954d4335 --- /dev/null +++ b/portable/GCC/H8S2329/portmacro.h @@ -0,0 +1,145 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint8_t +#define portBASE_TYPE char + +typedef portSTACK_TYPE StackType_t; +typedef signed char BaseType_t; +typedef unsigned char UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 2 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portYIELD() asm volatile ( "TRAPA #0" ) +#define portNOP() asm volatile ( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +#define portENABLE_INTERRUPTS() asm volatile ( "ANDC #0x7F, CCR" ); +#define portDISABLE_INTERRUPTS() asm volatile ( "ORC #0x80, CCR" ); + +/* Push the CCR then disable interrupts. */ +#define portENTER_CRITICAL() \ + asm volatile ( "STC CCR, @-ER7" ); \ + portDISABLE_INTERRUPTS(); + +/* Pop the CCR to set the interrupt masking back to its previous state. */ +#define portEXIT_CRITICAL() asm volatile ( "LDC @ER7+, CCR" ); +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* Context switch macros. These macros are very simple as the context + * is saved simply by selecting the saveall attribute of the context switch + * interrupt service routines. These macros save and restore the stack + * pointer to the TCB. */ + +#define portSAVE_STACK_POINTER() \ + extern void * pxCurrentTCB; \ + \ + asm volatile ( \ + "MOV.L @_pxCurrentTCB, ER5 \n\t" \ + "MOV.L ER7, @ER5 \n\t" \ + ); \ + ( void ) pxCurrentTCB; + + +#define portRESTORE_STACK_POINTER() \ + extern void * pxCurrentTCB; \ + \ + asm volatile ( \ + "MOV.L @_pxCurrentTCB, ER5 \n\t" \ + "MOV.L @ER5, ER7 \n\t" \ + ); \ + ( void ) pxCurrentTCB; + +/*-----------------------------------------------------------*/ + +/* Macros to allow a context switch from within an application ISR. */ + +#define portENTER_SWITCHING_ISR() portSAVE_STACK_POINTER(); { +#define portEXIT_SWITCHING_ISR( x ) \ + if( x ) \ + { \ + extern void vTaskSwitchContext( void ); \ + vTaskSwitchContext(); \ + } \ +} \ + portRESTORE_STACK_POINTER(); +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/HCS12/port.c b/portable/GCC/HCS12/port.c new file mode 100644 index 000000000..4355a3f11 --- /dev/null +++ b/portable/GCC/HCS12/port.c @@ -0,0 +1,239 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* GCC/HCS12 port by Jefferson L Smith, 2005 */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Port includes */ +#include + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the HCS12 port. +*----------------------------------------------------------*/ + + +/* + * Configure a timer to generate the RTOS tick at the frequency specified + * within FreeRTOSConfig.h. + */ +static void prvSetupTimerInterrupt( void ); + +/* NOTE: Interrupt service routines must be in non-banked memory - as does the + * scheduler startup function. */ +#define ATTR_NEAR __attribute__( ( near ) ) + +/* Manual context switch function. This is the SWI ISR. */ +/* __attribute__((interrupt)) */ +void ATTR_NEAR vPortYield( void ); + +/* Tick context switch function. This is the timer ISR. */ +/* __attribute__((interrupt)) */ +void ATTR_NEAR vPortTickInterrupt( void ); + +/* Function in non-banked memory which actually switches to first task. */ +BaseType_t ATTR_NEAR xStartSchedulerNear( void ); + +/* Calls to portENTER_CRITICAL() can be nested. When they are nested the + * critical section should not be left (i.e. interrupts should not be re-enabled) + * until the nesting depth reaches 0. This variable simply tracks the nesting + * depth. Each task maintains it's own critical nesting depth variable so + * uxCriticalNesting is saved and restored from the task stack during a context + * switch. */ +volatile UBaseType_t uxCriticalNesting = 0x80; /* un-initialized */ + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Setup the initial stack of the task. The stack is set exactly as + * expected by the portRESTORE_CONTEXT() macro. In this case the stack as + * expected by the HCS12 RTI instruction. */ + + + /* The address of the task function is placed in the stack byte at a time. */ + *pxTopOfStack = ( StackType_t ) *( ( ( StackType_t * ) ( &pxCode ) ) + 1 ); + *--pxTopOfStack = ( StackType_t ) *( ( ( StackType_t * ) ( &pxCode ) ) + 0 ); + + /* Next are all the registers that form part of the task context. */ + + /* Y register */ + *--pxTopOfStack = ( StackType_t ) 0xff; + *--pxTopOfStack = ( StackType_t ) 0xee; + + /* X register */ + *--pxTopOfStack = ( StackType_t ) 0xdd; + *--pxTopOfStack = ( StackType_t ) 0xcc; + + /* A register contains parameter high byte. */ + *--pxTopOfStack = ( StackType_t ) *( ( ( StackType_t * ) ( &pvParameters ) ) + 0 ); + + /* B register contains parameter low byte. */ + *--pxTopOfStack = ( StackType_t ) *( ( ( StackType_t * ) ( &pvParameters ) ) + 1 ); + + /* CCR: Note that when the task starts interrupts will be enabled since + * "I" bit of CCR is cleared */ + *--pxTopOfStack = ( StackType_t ) 0x80; /* keeps Stop disabled (MCU default) */ + + /* tmp softregs used by GCC. Values right now don't matter. */ + __asm( "\n\ + movw _.frame, 2,-%0 \n\ + movw _.tmp, 2,-%0 \n\ + movw _.z, 2,-%0 \n\ + movw _.xy, 2,-%0 \n\ + ;movw _.d2, 2,-%0 \n\ + ;movw _.d1, 2,-%0 \n\ + " : "=A" ( pxTopOfStack ) : "0" ( pxTopOfStack ) ); + + #ifdef BANKED_MODEL + /* The page of the task. */ + *--pxTopOfStack = 0x30; /* can only directly start in PPAGE 0x30 */ + #endif + + /* The critical nesting depth is initialised with 0 (meaning not in + * a critical section). */ + *--pxTopOfStack = ( StackType_t ) 0x00; + + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the HCS12 port will get stopped. */ +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ + /* Enable hardware RTI timer */ + /* Ignores configTICK_RATE_HZ */ + RTICTL = 0x50; /* 16 MHz xtal: 976.56 Hz, 1024mS */ + CRGINT |= 0x80; /* RTIE */ +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* xPortStartScheduler() does not start the scheduler directly because + * the header file containing the xPortStartScheduler() prototype is part + * of the common kernel code, and therefore cannot use the CODE_SEG pragma. + * Instead it simply calls the locally defined xNearStartScheduler() - + * which does use the CODE_SEG pragma. */ + + int16_t register d; + + __asm( "jmp xStartSchedulerNear ; will never return" : "=d" ( d ) ); + return d; +} +/*-----------------------------------------------------------*/ + +BaseType_t xStartSchedulerNear( void ) +{ + /* Configure the timer that will generate the RTOS tick. Interrupts are + * disabled when this function is called. */ + prvSetupTimerInterrupt(); + + /* Restore the context of the first task. */ + portRESTORE_CONTEXT(); + + portISR_TAIL(); + + /* Should not get here! */ + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +/* + * Context switch functions. These are interrupt service routines. + */ + +/* + * Manual context switch forced by calling portYIELD(). This is the SWI + * handler. + */ +void vPortYield( void ) +{ + portISR_HEAD(); + + /* NOTE: This is the trap routine (swi) although not defined as a trap. + * It will fill the stack the same way as an ISR in order to mix preemtion + * and cooperative yield. */ + + portSAVE_CONTEXT(); + vTaskSwitchContext(); + portRESTORE_CONTEXT(); + + portISR_TAIL(); +} +/*-----------------------------------------------------------*/ + +/* + * RTOS tick interrupt service routine. If the cooperative scheduler is + * being used then this simply increments the tick count. If the + * preemptive scheduler is being used a context switch can occur. + */ +void vPortTickInterrupt( void ) +{ + portISR_HEAD(); + + /* Clear tick timer flag */ + CRGFLG = 0x80; + + #if configUSE_PREEMPTION == 1 + { + /* A context switch might happen so save the context. */ + portSAVE_CONTEXT(); + + /* Increment the tick ... */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* A context switch is necessary. */ + vTaskSwitchContext(); + } + + /* Restore the context of a task - which may be a different task + * to that interrupted. */ + portRESTORE_CONTEXT(); + } + #else /* if configUSE_PREEMPTION == 1 */ + { + xTaskIncrementTick(); + } + #endif /* if configUSE_PREEMPTION == 1 */ + + portISR_TAIL(); +} diff --git a/portable/GCC/HCS12/portmacro.h b/portable/GCC/HCS12/portmacro.h new file mode 100644 index 000000000..4d02ad54e --- /dev/null +++ b/portable/GCC/HCS12/portmacro.h @@ -0,0 +1,253 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint8_t +#define portBASE_TYPE char + +typedef portSTACK_TYPE StackType_t; +typedef signed char BaseType_t; +typedef unsigned char UBaseType_t; + + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 1 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portYIELD() __asm( "swi" ); +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +#define portENABLE_INTERRUPTS() __asm( "cli" ) +#define portDISABLE_INTERRUPTS() __asm( "sei" ) + +/* + * Disable interrupts before incrementing the count of critical section nesting. + * The nesting count is maintained so we know when interrupts should be + * re-enabled. Once interrupts are disabled the nesting count can be accessed + * directly. Each task maintains its own nesting count. + */ +#define portENTER_CRITICAL() \ + { \ + extern volatile UBaseType_t uxCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + uxCriticalNesting++; \ + } + +/* + * Interrupts are disabled so we can access the nesting count directly. If the + * nesting is found to be 0 (no nesting) then we are leaving the critical + * section and interrupts can be re-enabled. + */ +#define portEXIT_CRITICAL() \ + { \ + extern volatile UBaseType_t uxCriticalNesting; \ + \ + uxCriticalNesting--; \ + if( uxCriticalNesting == 0 ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* + * These macros are very simple as the processor automatically saves and + * restores its registers as interrupts are entered and exited. In + * addition to the (automatically stacked) registers we also stack the + * critical nesting count. Each task maintains its own critical nesting + * count as it is legitimate for a task to yield from within a critical + * section. If the banked memory model is being used then the PPAGE + * register is also stored as part of the tasks context. + */ + +#ifdef BANKED_MODEL + +/* + * Load the stack pointer for the task, then pull the critical nesting + * count and PPAGE register from the stack. The remains of the + * context are restored by the RTI instruction. + */ + #define portRESTORE_CONTEXT() \ + { \ + __asm( " \n\ + .globl pxCurrentTCB ; void * \n\ + .globl uxCriticalNesting ; char \n\ + \n\ + ldx pxCurrentTCB \n\ + lds 0,x ; Stack \n\ + \n\ + movb 1,sp+,uxCriticalNesting \n\ + movb 1,sp+,0x30 ; PPAGE \n\ + " ); \ + } + +/* + * By the time this macro is called the processor has already stacked the + * registers. Simply stack the nesting count and PPAGE value, then save + * the task stack pointer. + */ + #define portSAVE_CONTEXT() \ + { \ + __asm( " \n\ + .globl pxCurrentTCB ; void * \n\ + .globl uxCriticalNesting ; char \n\ + \n\ + movb 0x30, 1,-sp ; PPAGE \n\ + movb uxCriticalNesting, 1,-sp \n\ + \n\ + ldx pxCurrentTCB \n\ + sts 0,x ; Stack \n\ + " ); \ + } +#else /* ifdef BANKED_MODEL */ + +/* + * These macros are as per the BANKED versions above, but without saving + * and restoring the PPAGE register. + */ + + #define portRESTORE_CONTEXT() \ + { \ + __asm( " \n\ + .globl pxCurrentTCB ; void * \n\ + .globl uxCriticalNesting ; char \n\ + \n\ + ldx pxCurrentTCB \n\ + lds 0,x ; Stack \n\ + \n\ + movb 1,sp+,uxCriticalNesting \n\ + " ); \ + } + + #define portSAVE_CONTEXT() \ + { \ + __asm( " \n\ + .globl pxCurrentTCB ; void * \n\ + .globl uxCriticalNesting ; char \n\ + \n\ + movb uxCriticalNesting, 1,-sp \n\ + \n\ + ldx pxCurrentTCB \n\ + sts 0,x ; Stack \n\ + " ); \ + } +#endif /* ifdef BANKED_MODEL */ + +/* + * Utility macros to save/restore correct software registers for GCC. This is + * useful when GCC does not generate appropriate ISR head/tail code. + */ +#define portISR_HEAD() \ + { \ + __asm( " \n\ + movw _.frame, 2,-sp \n\ + movw _.tmp, 2,-sp \n\ + movw _.z, 2,-sp \n\ + movw _.xy, 2,-sp \n\ + ;movw _.d2, 2,-sp \n\ + ;movw _.d1, 2,-sp \n\ + " ); \ + } + +#define portISR_TAIL() \ + { \ + __asm( " \n\ + movw 2,sp+, _.xy \n\ + movw 2,sp+, _.z \n\ + movw 2,sp+, _.tmp \n\ + movw 2,sp+, _.frame \n\ + ;movw 2,sp+, _.d1 \n\ + ;movw 2,sp+, _.d2 \n\ + rti \n\ + " ); \ + } + +/* + * Utility macro to call macros above in correct order in order to perform a + * task switch from within a standard ISR. This macro can only be used if + * the ISR does not use any local (stack) variables. If the ISR uses stack + * variables portYIELD() should be used in it's place. + */ + +#define portTASK_SWITCH_FROM_ISR() \ + portSAVE_CONTEXT(); \ + vTaskSwitchContext(); \ + portRESTORE_CONTEXT(); + + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/IA32_flat/ISR_Support.h b/portable/GCC/IA32_flat/ISR_Support.h new file mode 100644 index 000000000..18e10bf91 --- /dev/null +++ b/portable/GCC/IA32_flat/ISR_Support.h @@ -0,0 +1,128 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + .extern ulTopOfSystemStack + .extern ulInterruptNesting + +/*-----------------------------------------------------------*/ + +.macro portFREERTOS_INTERRUPT_ENTRY + + /* Save general purpose registers. */ + pusha + + /* If ulInterruptNesting is zero the rest of the task context will need + saving and a stack switch might be required. */ + movl ulInterruptNesting, %eax + test %eax, %eax + jne 2f + + /* Interrupts are not nested, so save the rest of the task context. */ + .if configSUPPORT_FPU == 1 + + /* If the task has a buffer allocated to save the FPU context then + save the FPU context now. */ + movl pucPortTaskFPUContextBuffer, %eax + test %eax, %eax + je 1f + fnsave ( %eax ) /* Save FLOP context into ucTempFPUBuffer array. */ + fwait + + 1: + /* Save the address of the FPU context, if any. */ + push pucPortTaskFPUContextBuffer + + .endif /* configSUPPORT_FPU */ + + /* Find the TCB. */ + movl pxCurrentTCB, %eax + + /* Stack location is first item in the TCB. */ + movl %esp, (%eax) + + /* Switch stacks. */ + movl ulTopOfSystemStack, %esp + movl %esp, %ebp + + 2: + /* Increment nesting count. */ + add $1, ulInterruptNesting + +.endm +/*-----------------------------------------------------------*/ + +.macro portINTERRUPT_EPILOGUE + + cli + sub $1, ulInterruptNesting + + /* If the nesting has unwound to zero. */ + movl ulInterruptNesting, %eax + test %eax, %eax + jne 2f + + /* If a yield was requested then select a new TCB now. */ + movl ulPortYieldPending, %eax + test %eax, %eax + je 1f + movl $0, ulPortYieldPending + call vTaskSwitchContext + + 1: + /* Stack location is first item in the TCB. */ + movl pxCurrentTCB, %eax + movl (%eax), %esp + + .if configSUPPORT_FPU == 1 + + /* Restore address of task's FPU context buffer. */ + pop pucPortTaskFPUContextBuffer + + /* If the task has a buffer allocated in which its FPU context is saved, + then restore it now. */ + movl pucPortTaskFPUContextBuffer, %eax + test %eax, %eax + je 1f + frstor ( %eax ) + 1: + .endif + + 2: + popa + +.endm +/*-----------------------------------------------------------*/ + +.macro portFREERTOS_INTERRUPT_EXIT + + portINTERRUPT_EPILOGUE + /* EOI. */ + movl $0x00, (0xFEE000B0) + iret + +.endm diff --git a/portable/GCC/IA32_flat/port.c b/portable/GCC/IA32_flat/port.c new file mode 100644 index 000000000..682cce951 --- /dev/null +++ b/portable/GCC/IA32_flat/port.c @@ -0,0 +1,688 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + /* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +#if ( configISR_STACK_SIZE < ( configMINIMAL_STACK_SIZE * 2 ) ) + #warning configISR_STACK_SIZE is probably too small! +#endif /* ( configISR_STACK_SIZE < configMINIMAL_STACK_SIZE * 2 ) */ + +#if ( ( configMAX_API_CALL_INTERRUPT_PRIORITY > portMAX_PRIORITY ) || ( configMAX_API_CALL_INTERRUPT_PRIORITY < 2 ) ) + #error configMAX_API_CALL_INTERRUPT_PRIORITY must be between 2 and 15 +#endif + +#if ( ( configSUPPORT_FPU == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) ) + #error configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 to use this port with an FPU +#endif + +/* A critical section is exited when the critical section nesting count reaches + * this value. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + +/* Tasks are not created with a floating point context, but can be given a + * floating point context after they have been created. A variable is stored as + * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task + * does not have an FPU context, or any other value if the task does have an FPU + * context. */ +#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) + +/* Only the IF bit is set so tasks start with interrupts enabled. */ +#define portINITIAL_EFLAGS ( 0x200UL ) + +/* Error interrupts are at the highest priority vectors. */ +#define portAPIC_LVT_ERROR_VECTOR ( 0xfe ) +#define portAPIC_SPURIOUS_INT_VECTOR ( 0xff ) + +/* EFLAGS bits. */ +#define portEFLAGS_IF ( 0x200UL ) + +/* FPU context size if FSAVE is used. */ +#define portFPU_CONTEXT_SIZE_BYTES 108 + +/* The expected size of each entry in the IDT. Used to check structure packing + * is set correctly. */ +#define portEXPECTED_IDT_ENTRY_SIZE 8 + +/* Default flags setting for entries in the IDT. */ +#define portIDT_FLAGS ( 0x8E ) + +/* This is the lowest possible ISR vector available to application code. */ +#define portAPIC_MIN_ALLOWABLE_VECTOR ( 0x20 ) + +/* If configASSERT() is defined then the system stack is filled with this value + * to allow for a crude stack overflow check. */ +#define portSTACK_WORD ( 0xecececec ) +/*-----------------------------------------------------------*/ + +/* + * Starts the first task executing. + */ +extern void vPortStartFirstTask( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/* + * Complete one descriptor in the IDT. + */ +static void prvSetInterruptGate( uint8_t ucNumber, + ISR_Handler_t pxHandlerFunction, + uint8_t ucFlags ); + +/* + * The default handler installed in each IDT position. + */ +extern void vPortCentralInterruptWrapper( void ); + +/* + * Handler for portYIELD(). + */ +extern void vPortYieldCall( void ); + +/* + * Configure the APIC to generate the RTOS tick. + */ +static void prvSetupTimerInterrupt( void ); + +/* + * Tick interrupt handler. + */ +extern void vPortTimerHandler( void ); + +/* + * Check an interrupt vector is not too high, too low, in use by FreeRTOS, or + * already in use by the application. + */ +static BaseType_t prvCheckValidityOfVectorNumber( uint32_t ulVectorNumber ); + +/*-----------------------------------------------------------*/ + +/* A variable is used to keep track of the critical section nesting. This + * variable must be initialised to a non zero value to ensure interrupts don't + * inadvertently become unmasked before the scheduler starts. It is set to zero + * before the first task starts executing. */ +volatile uint32_t ulCriticalNesting = 9999UL; + +/* A structure used to map the various fields of an IDT entry into separate + * structure members. */ +struct IDTEntry +{ + uint16_t usISRLow; /* Low 16 bits of handler address. */ + uint16_t usSegmentSelector; /* Flat model means this is not changed. */ + uint8_t ucZero; /* Must be set to zero. */ + uint8_t ucFlags; /* Flags for this entry. */ + uint16_t usISRHigh; /* High 16 bits of handler address. */ +} +__attribute__( ( packed ) ); +typedef struct IDTEntry IDTEntry_t; + + +/* Use to pass the location of the IDT to the CPU. */ +struct IDTPointer +{ + uint16_t usTableLimit; + uint32_t ulTableBase; /* The address of the first entry in xInterruptDescriptorTable. */ +} +__attribute__( ( __packed__ ) ); +typedef struct IDTPointer IDTPointer_t; + +/* The IDT itself. */ +static __attribute__( ( aligned( 32 ) ) ) IDTEntry_t xInterruptDescriptorTable[ portNUM_VECTORS ]; + +#if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 ) + +/* A table in which application defined interrupt handlers are stored. These + * are called by the central interrupt handler if a common interrupt entry + * point it used. */ +static ISR_Handler_t xInterruptHandlerTable[ portNUM_VECTORS ] = { NULL }; + +#endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */ + +#if ( configSUPPORT_FPU == 1 ) + +/* Saved as part of the task context. If pucPortTaskFPUContextBuffer is NULL + * then the task does not have an FPU context. If pucPortTaskFPUContextBuffer is + * not NULL then it points to a buffer into which the FPU context can be saved. */ + uint8_t * pucPortTaskFPUContextBuffer __attribute__( ( used ) ) = pdFALSE; + +#endif /* configSUPPORT_FPU */ + +/* The stack used by interrupt handlers. */ +static uint32_t ulSystemStack[ configISR_STACK_SIZE ] __attribute__( ( used ) ) = { 0 }; + +/* Don't use the very top of the system stack so the return address + * appears as 0 if the debugger tries to unwind the stack. */ +volatile uint32_t ulTopOfSystemStack __attribute__( ( used ) ) = ( uint32_t ) &( ulSystemStack[ configISR_STACK_SIZE - 5 ] ); + +/* If a yield is requested from an interrupt or from a critical section then + * the yield is not performed immediately, and ulPortYieldPending is set to pdTRUE + * instead to indicate the yield should be performed at the end of the interrupt + * when the critical section is exited. */ +volatile uint32_t ulPortYieldPending __attribute__( ( used ) ) = pdFALSE; + +/* Counts the interrupt nesting depth. Used to know when to switch to the + * interrupt/system stack and when to save/restore a complete context. */ +volatile uint32_t ulInterruptNesting __attribute__( ( used ) ) = 0; + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + uint32_t ulCodeSegment; + + /* Setup the initial stack as expected by the portFREERTOS_INTERRUPT_EXIT macro. */ + + *pxTopOfStack = 0x00; + pxTopOfStack--; + *pxTopOfStack = 0x00; + pxTopOfStack--; + + /* Parameters first. */ + *pxTopOfStack = ( StackType_t ) pvParameters; + pxTopOfStack--; + + /* There is nothing to return to so assert if attempting to use the return + * address. */ + *pxTopOfStack = ( StackType_t ) prvTaskExitError; + pxTopOfStack--; + + /* iret used to start the task pops up to here. */ + *pxTopOfStack = portINITIAL_EFLAGS; + pxTopOfStack--; + + /* CS */ + __asm volatile ( "movl %%cs, %0" : "=r" ( ulCodeSegment ) ); + *pxTopOfStack = ulCodeSegment; + pxTopOfStack--; + + /* First instruction in the task. */ + *pxTopOfStack = ( StackType_t ) pxCode; + pxTopOfStack--; + + /* General purpose registers as expected by a POPA instruction. */ + *pxTopOfStack = 0xEA; + pxTopOfStack--; + + *pxTopOfStack = 0xEC; + pxTopOfStack--; + + *pxTopOfStack = 0xED1; /* EDX */ + pxTopOfStack--; + + *pxTopOfStack = 0xEB1; /* EBX */ + pxTopOfStack--; + + /* Hole for ESP. */ + pxTopOfStack--; + + *pxTopOfStack = 0x00; /* EBP */ + pxTopOfStack--; + + *pxTopOfStack = 0xE5; /* ESI */ + pxTopOfStack--; + + *pxTopOfStack = 0xeeeeeeee; /* EDI */ + + #if ( configSUPPORT_FPU == 1 ) + { + pxTopOfStack--; + + /* Buffer for FPU context, which is initialised to NULL as tasks are not + * created with an FPU context. */ + *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT; + } + #endif /* configSUPPORT_FPU */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvSetInterruptGate( uint8_t ucNumber, + ISR_Handler_t pxHandlerFunction, + uint8_t ucFlags ) +{ + uint16_t usCodeSegment; + uint32_t ulBase = ( uint32_t ) pxHandlerFunction; + + xInterruptDescriptorTable[ ucNumber ].usISRLow = ( uint16_t ) ( ulBase & USHRT_MAX ); + xInterruptDescriptorTable[ ucNumber ].usISRHigh = ( uint16_t ) ( ( ulBase >> 16UL ) & USHRT_MAX ); + + /* When the flat model is used the CS will never change. */ + __asm volatile ( "mov %%cs, %0" : "=r" ( usCodeSegment ) ); + xInterruptDescriptorTable[ ucNumber ].usSegmentSelector = usCodeSegment; + xInterruptDescriptorTable[ ucNumber ].ucZero = 0; + xInterruptDescriptorTable[ ucNumber ].ucFlags = ucFlags; +} +/*-----------------------------------------------------------*/ + +void vPortSetupIDT( void ) +{ + uint32_t ulNum; + IDTPointer_t xIDT; + + #if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 ) + { + for( ulNum = 0; ulNum < portNUM_VECTORS; ulNum++ ) + { + /* If a handler has not already been installed on this vector. */ + if( ( xInterruptDescriptorTable[ ulNum ].usISRLow == 0x00 ) && ( xInterruptDescriptorTable[ ulNum ].usISRHigh == 0x00 ) ) + { + prvSetInterruptGate( ( uint8_t ) ulNum, vPortCentralInterruptWrapper, portIDT_FLAGS ); + } + } + } + #endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */ + + /* Set IDT address. */ + xIDT.ulTableBase = ( uint32_t ) xInterruptDescriptorTable; + xIDT.usTableLimit = sizeof( xInterruptDescriptorTable ) - 1; + + /* Set IDT in CPU. */ + __asm volatile ( "lidt %0" ::"m" ( xIDT ) ); +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ + extern void vPortAPICErrorHandlerWrapper( void ); + extern void vPortAPICSpuriousHandler( void ); + + /* Initialise LAPIC to a well known state. */ + portAPIC_LDR = 0xFFFFFFFF; + portAPIC_LDR = ( ( portAPIC_LDR & 0x00FFFFFF ) | 0x00000001 ); + portAPIC_LVT_TIMER = portAPIC_DISABLE; + portAPIC_LVT_PERF = portAPIC_NMI; + portAPIC_LVT_LINT0 = portAPIC_DISABLE; + portAPIC_LVT_LINT1 = portAPIC_DISABLE; + portAPIC_TASK_PRIORITY = 0; + + /* Install APIC timer ISR vector. */ + prvSetInterruptGate( ( uint8_t ) portAPIC_TIMER_INT_VECTOR, vPortTimerHandler, portIDT_FLAGS ); + + /* Install API error handler. */ + prvSetInterruptGate( ( uint8_t ) portAPIC_LVT_ERROR_VECTOR, vPortAPICErrorHandlerWrapper, portIDT_FLAGS ); + + /* Install Yield handler. */ + prvSetInterruptGate( ( uint8_t ) portAPIC_YIELD_INT_VECTOR, vPortYieldCall, portIDT_FLAGS ); + + /* Install spurious interrupt vector. */ + prvSetInterruptGate( ( uint8_t ) portAPIC_SPURIOUS_INT_VECTOR, vPortAPICSpuriousHandler, portIDT_FLAGS ); + + /* Enable the APIC, mapping the spurious interrupt at the same time. */ + portAPIC_SPURIOUS_INT = portAPIC_SPURIOUS_INT_VECTOR | portAPIC_ENABLE_BIT; + + /* Set timer error vector. */ + portAPIC_LVT_ERROR = portAPIC_LVT_ERROR_VECTOR; + + /* Set the interrupt frequency. */ + portAPIC_TMRDIV = portAPIC_DIV_16; + portAPIC_TIMER_INITIAL_COUNT = ( ( configCPU_CLOCK_HZ >> 4UL ) / configTICK_RATE_HZ ) - 1UL; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + BaseType_t xWord; + + /* Some versions of GCC require the -mno-ms-bitfields command line option + * for packing to work. */ + configASSERT( sizeof( struct IDTEntry ) == portEXPECTED_IDT_ENTRY_SIZE ); + + /* Fill part of the system stack with a known value to help detect stack + * overflow. A few zeros are left so GDB doesn't get confused unwinding + * the stack. */ + for( xWord = 0; xWord < configISR_STACK_SIZE - 20; xWord++ ) + { + ulSystemStack[ xWord ] = portSTACK_WORD; + } + + /* Initialise Interrupt Descriptor Table (IDT). */ + vPortSetupIDT(); + + /* Initialise LAPIC and install system handlers. */ + prvSetupTimerInterrupt(); + + /* Make sure the stack used by interrupts is aligned. */ + ulTopOfSystemStack &= ~portBYTE_ALIGNMENT_MASK; + + ulCriticalNesting = 0; + + /* Enable LAPIC Counter.*/ + portAPIC_LVT_TIMER = portAPIC_TIMER_PERIODIC | portAPIC_TIMER_INT_VECTOR; + + /* Sometimes needed. */ + portAPIC_TMRDIV = portAPIC_DIV_16; + + /* Should not return from the following function as the scheduler will then + * be executing the tasks. */ + vPortStartFirstTask(); + + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + if( ulCriticalNesting == 0 ) + { + #if ( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY ) + { + __asm volatile ( "cli" ); + } + #else + { + portAPIC_TASK_PRIORITY = portMAX_API_CALL_PRIORITY; + configASSERT( portAPIC_TASK_PRIORITY == portMAX_API_CALL_PRIORITY ); + } + #endif + } + + /* Now that interrupts are disabled, ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as the critical section is being + * exited. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then all interrupt + * priorities must be re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Critical nesting has reached zero so all interrupt priorities + * should be unmasked. */ + #if ( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY ) + { + __asm volatile ( "sti" ); + } + #else + { + portAPIC_TASK_PRIORITY = 0; + } + #endif + + /* If a yield was pended from within the critical section then + * perform the yield now. */ + if( ulPortYieldPending != pdFALSE ) + { + ulPortYieldPending = pdFALSE; + __asm volatile ( portYIELD_INTERRUPT ); + } + } + } +} +/*-----------------------------------------------------------*/ + +uint32_t ulPortSetInterruptMask( void ) +{ + volatile uint32_t ulOriginalMask; + + /* Set mask to max syscall priority. */ + #if ( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY ) + { + /* Return whether interrupts were already enabled or not. Pop adjusts + * the stack first. */ + __asm volatile ( "pushf \t\n" + "pop %0 \t\n" + "cli " + : "=rm" ( ulOriginalMask )::"memory" ); + + ulOriginalMask &= portEFLAGS_IF; + } + #else + { + /* Return original mask. */ + ulOriginalMask = portAPIC_TASK_PRIORITY; + portAPIC_TASK_PRIORITY = portMAX_API_CALL_PRIORITY; + configASSERT( portAPIC_TASK_PRIORITY == portMAX_API_CALL_PRIORITY ); + } + #endif /* if ( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY ) */ + + return ulOriginalMask; +} +/*-----------------------------------------------------------*/ + +void vPortClearInterruptMask( uint32_t ulNewMaskValue ) +{ + #if ( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY ) + { + if( ulNewMaskValue != pdFALSE ) + { + __asm volatile ( "sti" ); + } + } + #else + { + portAPIC_TASK_PRIORITY = ulNewMaskValue; + configASSERT( portAPIC_TASK_PRIORITY == ulNewMaskValue ); + } + #endif /* if ( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY ) */ +} +/*-----------------------------------------------------------*/ + +#if ( configSUPPORT_FPU == 1 ) + + void vPortTaskUsesFPU( void ) + { + /* A task is registering the fact that it needs an FPU context. Allocate a + * buffer into which the context can be saved. */ + pucPortTaskFPUContextBuffer = ( uint8_t * ) pvPortMalloc( portFPU_CONTEXT_SIZE_BYTES ); + configASSERT( pucPortTaskFPUContextBuffer ); + + /* Initialise the floating point registers. */ + __asm volatile ( "fninit" ); + } + +#endif /* configSUPPORT_FPU */ +/*-----------------------------------------------------------*/ + +void vPortAPICErrorHandler( void ) +{ +/* Variable to hold the APIC error status for viewing in the debugger. */ + volatile uint32_t ulErrorStatus = 0; + + portAPIC_ERROR_STATUS = 0; + ulErrorStatus = portAPIC_ERROR_STATUS; + ( void ) ulErrorStatus; + + /* Force an assert. */ + configASSERT( ulCriticalNesting == ~0UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 ) + + void vPortCentralInterruptHandler( uint32_t ulVector ) + { + if( ulVector < portNUM_VECTORS ) + { + if( xInterruptHandlerTable[ ulVector ] != NULL ) + { + ( xInterruptHandlerTable[ ulVector ] )(); + } + } + + /* Check for a system stack overflow. */ + configASSERT( ulSystemStack[ 10 ] == portSTACK_WORD ); + configASSERT( ulSystemStack[ 12 ] == portSTACK_WORD ); + configASSERT( ulSystemStack[ 14 ] == portSTACK_WORD ); + } + +#endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 ) + + BaseType_t xPortRegisterCInterruptHandler( ISR_Handler_t pxHandler, + uint32_t ulVectorNumber ) + { + BaseType_t xReturn; + + xReturn = prvCheckValidityOfVectorNumber( ulVectorNumber ); + + if( xReturn != pdFAIL ) + { + /* Save the handler passed in by the application in the vector number + * passed in. The addresses are then called from the central interrupt + * handler. */ + xInterruptHandlerTable[ ulVectorNumber ] = pxHandler; + } + + return xReturn; + } + +#endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortInstallInterruptHandler( ISR_Handler_t pxHandler, + uint32_t ulVectorNumber ) +{ + BaseType_t xReturn; + + xReturn = prvCheckValidityOfVectorNumber( ulVectorNumber ); + + if( xReturn != pdFAIL ) + { + taskENTER_CRITICAL(); + { + /* Update the IDT to include the application defined handler. */ + prvSetInterruptGate( ( uint8_t ) ulVectorNumber, ( ISR_Handler_t ) pxHandler, portIDT_FLAGS ); + } + taskEXIT_CRITICAL(); + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvCheckValidityOfVectorNumber( uint32_t ulVectorNumber ) +{ + BaseType_t xReturn; + + /* Check validity of vector number. */ + if( ulVectorNumber >= portNUM_VECTORS ) + { + /* Too high. */ + xReturn = pdFAIL; + } + else if( ulVectorNumber < portAPIC_MIN_ALLOWABLE_VECTOR ) + { + /* Too low. */ + xReturn = pdFAIL; + } + else if( ulVectorNumber == portAPIC_TIMER_INT_VECTOR ) + { + /* In use by FreeRTOS. */ + xReturn = pdFAIL; + } + else if( ulVectorNumber == portAPIC_YIELD_INT_VECTOR ) + { + /* In use by FreeRTOS. */ + xReturn = pdFAIL; + } + else if( ulVectorNumber == portAPIC_LVT_ERROR_VECTOR ) + { + /* In use by FreeRTOS. */ + xReturn = pdFAIL; + } + else if( ulVectorNumber == portAPIC_SPURIOUS_INT_VECTOR ) + { + /* In use by FreeRTOS. */ + xReturn = pdFAIL; + } +#if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 ) + else if( xInterruptHandlerTable[ ulVectorNumber ] != NULL ) + { + /* Already in use by the application. */ + xReturn = pdFAIL; + } +#endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */ + else + { + xReturn = pdPASS; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void vGenerateYieldInterrupt( void ) +{ + __asm volatile ( portYIELD_INTERRUPT ); +} diff --git a/portable/GCC/IA32_flat/portASM.S b/portable/GCC/IA32_flat/portASM.S new file mode 100644 index 000000000..c01b32bce --- /dev/null +++ b/portable/GCC/IA32_flat/portASM.S @@ -0,0 +1,268 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +.file "portASM.S" +#include "FreeRTOSConfig.h" +#include "ISR_Support.h" + + .extern pxCurrentTCB + .extern vTaskSwitchContext + .extern vPortCentralInterruptHandler + .extern xTaskIncrementTick + .extern vPortAPICErrorHandler + .extern pucPortTaskFPUContextBuffer + .extern ulPortYieldPending + + .global vPortStartFirstTask + .global vPortCentralInterruptWrapper + .global vPortAPICErrorHandlerWrapper + .global vPortTimerHandler + .global vPortYieldCall + .global vPortAPICSpuriousHandler + + .text + +/*-----------------------------------------------------------*/ + +.align 4 +.func vPortYieldCall +vPortYieldCall: + /* Save general purpose registers. */ + pusha + + .if configSUPPORT_FPU == 1 + + /* If the task has a buffer allocated to save the FPU context then save + the FPU context now. */ + movl pucPortTaskFPUContextBuffer, %eax + test %eax, %eax + je 1f + fnsave ( %eax ) + fwait + + 1: + + /* Save the address of the FPU context, if any. */ + push pucPortTaskFPUContextBuffer + + .endif /* configSUPPORT_FPU */ + + /* Find the TCB. */ + movl pxCurrentTCB, %eax + + /* Stack location is first item in the TCB. */ + movl %esp, (%eax) + + call vTaskSwitchContext + + /* Find the location of pxCurrentTCB again - a callee saved register could + be used in place of eax to prevent this second load, but that then relies + on the compiler and other asm code. */ + movl pxCurrentTCB, %eax + movl (%eax), %esp + + .if configSUPPORT_FPU == 1 + + /* Restore address of task's FPU context buffer. */ + pop pucPortTaskFPUContextBuffer + + /* If the task has a buffer allocated in which its FPU context is saved, + then restore it now. */ + movl pucPortTaskFPUContextBuffer, %eax + test %eax, %eax + je 1f + frstor ( %eax ) + 1: + .endif + + popa + iret + +.endfunc +/*-----------------------------------------------------------*/ + +.align 4 +.func vPortStartFirstTask +vPortStartFirstTask: + + /* Find the TCB. */ + movl pxCurrentTCB, %eax + + /* Stack location is first item in the TCB. */ + movl (%eax), %esp + + /* Restore FPU context flag. */ + .if configSUPPORT_FPU == 1 + + pop pucPortTaskFPUContextBuffer + + .endif /* configSUPPORT_FPU */ + + /* Restore general purpose registers. */ + popa + iret +.endfunc +/*-----------------------------------------------------------*/ + +.align 4 +.func vPortAPICErrorHandlerWrapper +vPortAPICErrorHandlerWrapper: + pusha + call vPortAPICErrorHandler + popa + /* EOI. */ + movl $0x00, (0xFEE000B0) + iret +.endfunc +/*-----------------------------------------------------------*/ + +.align 4 +.func vPortTimerHandler +vPortTimerHandler: + + /* Save general purpose registers. */ + pusha + + /* Interrupts are not nested, so save the rest of the task context. */ + .if configSUPPORT_FPU == 1 + + /* If the task has a buffer allocated to save the FPU context then save the + FPU context now. */ + movl pucPortTaskFPUContextBuffer, %eax + test %eax, %eax + je 1f + fnsave ( %eax ) /* Save FLOP context into ucTempFPUBuffer array. */ + fwait + + 1: + /* Save the address of the FPU context, if any. */ + push pucPortTaskFPUContextBuffer + + .endif /* configSUPPORT_FPU */ + + /* Find the TCB. */ + movl pxCurrentTCB, %eax + + /* Stack location is first item in the TCB. */ + movl %esp, (%eax) + + /* Switch stacks. */ + movl ulTopOfSystemStack, %esp + movl %esp, %ebp + + /* Increment nesting count. */ + add $1, ulInterruptNesting + + call xTaskIncrementTick + + sti + + /* Is a switch to another task required? */ + test %eax, %eax + je _skip_context_switch + cli + call vTaskSwitchContext + +_skip_context_switch: + cli + + /* Decrement the variable used to determine if a switch to a system + stack is necessary. */ + sub $1, ulInterruptNesting + + /* Stack location is first item in the TCB. */ + movl pxCurrentTCB, %eax + movl (%eax), %esp + + .if configSUPPORT_FPU == 1 + + /* Restore address of task's FPU context buffer. */ + pop pucPortTaskFPUContextBuffer + + /* If the task has a buffer allocated in which its FPU context is saved, + then restore it now. */ + movl pucPortTaskFPUContextBuffer, %eax + test %eax, %eax + je 1f + frstor ( %eax ) + 1: + .endif + + popa + + /* EOI. */ + movl $0x00, (0xFEE000B0) + iret + +.endfunc +/*-----------------------------------------------------------*/ + +.if configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 + + .align 4 + .func vPortCentralInterruptWrapper + vPortCentralInterruptWrapper: + + portFREERTOS_INTERRUPT_ENTRY + + movl $0xFEE00170, %eax /* Highest In Service Register (ISR) long word. */ + movl $8, %ecx /* Loop counter. */ + + next_isr_long_word: + test %ecx, %ecx /* Loop counter reached 0? */ + je wrapper_epilogue /* Looked at all ISR registers without finding a bit set. */ + sub $1, %ecx /* Sub 1 from loop counter. */ + movl (%eax), %ebx /* Load next ISR long word. */ + sub $0x10, %eax /* Point to next ISR long word in case no bits are set in the current long word. */ + test %ebx, %ebx /* Are there any bits set? */ + je next_isr_long_word /* Look at next ISR long word if no bits were set. */ + sti + bsr %ebx, %ebx /* A bit was set, which one? */ + movl $32, %eax /* Destination operand for following multiplication. */ + mul %ecx /* Calculate base vector for current register, 32 vectors per register. */ + add %ebx, %eax /* Add bit offset into register to get final vector number. */ + push %eax /* Vector number is function parameter. */ + call vPortCentralInterruptHandler + pop %eax /* Remove parameter. */ + + wrapper_epilogue: + portFREERTOS_INTERRUPT_EXIT + + .endfunc + +.endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */ +/*-----------------------------------------------------------*/ + +.align 4 +.func vPortAPISpuriousHandler +vPortAPICSpuriousHandler: + iret + +.endfunc + +.end diff --git a/portable/GCC/IA32_flat/portmacro.h b/portable/GCC/IA32_flat/portmacro.h new file mode 100644 index 000000000..085250e04 --- /dev/null +++ b/portable/GCC/IA32_flat/portmacro.h @@ -0,0 +1,302 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +typedef uint32_t TickType_t; +#define portMAX_DELAY ( ( TickType_t ) 0xffffffffUL ) + +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 32 + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* The interrupt priority (for vectors 16 to 255) is determined using vector/16. + * The quotient is rounded to the nearest integer with 1 being the lowest priority + * and 15 is the highest. Therefore the following two interrupts are at the lowest + * priority. *NOTE 1* If the yield vector is changed then it must also be changed + * in the portYIELD_INTERRUPT definition immediately below. */ +#define portAPIC_TIMER_INT_VECTOR ( 0x21 ) +#define portAPIC_YIELD_INT_VECTOR ( 0x20 ) + +/* Build yield interrupt instruction. */ +#define portYIELD_INTERRUPT "int $0x20" + +/* APIC register addresses. */ +#define portAPIC_EOI ( *( ( volatile uint32_t * ) 0xFEE000B0UL ) ) + +/* APIC bit definitions. */ +#define portAPIC_ENABLE_BIT ( 1UL << 8UL ) +#define portAPIC_TIMER_PERIODIC ( 1UL << 17UL ) +#define portAPIC_DISABLE ( 1UL << 16UL ) +#define portAPIC_NMI ( 4 << 8 ) +#define portAPIC_DIV_16 ( 0x03 ) + +/* Define local API register addresses. */ +#define portAPIC_ID_REGISTER ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x20UL ) ) ) +#define portAPIC_SPURIOUS_INT ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0xF0UL ) ) ) +#define portAPIC_LVT_TIMER ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x320UL ) ) ) +#define portAPIC_TIMER_INITIAL_COUNT ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x380UL ) ) ) +#define portAPIC_TIMER_CURRENT_COUNT ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x390UL ) ) ) +#define portAPIC_TASK_PRIORITY ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x80UL ) ) ) +#define portAPIC_LVT_ERROR ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x370UL ) ) ) +#define portAPIC_ERROR_STATUS ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x280UL ) ) ) +#define portAPIC_LDR ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0xD0UL ) ) ) +#define portAPIC_TMRDIV ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x3E0UL ) ) ) +#define portAPIC_LVT_PERF ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x340UL ) ) ) +#define portAPIC_LVT_LINT0 ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x350UL ) ) ) +#define portAPIC_LVT_LINT1 ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x360UL ) ) ) + +/* Don't yield if inside a critical section - instead hold the yield pending + * so it is performed when the critical section is exited. */ +#define portYIELD() \ + { \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile uint32_t ulPortYieldPending; \ + if( ulCriticalNesting != 0 ) \ + { \ + ulPortYieldPending = pdTRUE; \ + } \ + else \ + { \ + __asm volatile ( portYIELD_INTERRUPT ); \ + } \ + } + +/* Called at the end of an ISR that can cause a context switch - pend a yield if + * xSwitchRequired is not false. */ +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + { \ + extern volatile uint32_t ulPortYieldPending; \ + if( xSwitchRequired != pdFALSE ) \ + { \ + ulPortYieldPending = 1; \ + } \ + } + +/* Same as portEND_SWITCHING_ISR() - take your pick which name to use. */ +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) + +/*----------------------------------------------------------- +* Critical section control +*----------------------------------------------------------*/ + +/* Critical sections for use in interrupts. */ +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortClearInterruptMask( x ) + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +extern uint32_t ulPortSetInterruptMask( void ); +extern void vPortClearInterruptMask( uint32_t ulNewMaskValue ); + +/* These macros do not globally disable/enable interrupts. They do mask off + * interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */ +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +#define portDISABLE_INTERRUPTS() __asm volatile ( "cli" ) +#define portENABLE_INTERRUPTS() __asm volatile ( "sti" ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not required for this port but included in case common demo code that uses these + * macros is used. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* Architecture specific optimisations. */ +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + +/* Store/clear the ready priorities in a bit map. */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) \ + __asm volatile ( "bsr %1, %0\n\t" \ + : "=r" ( uxTopPriority ) : "rm" ( uxReadyPriorities ) : "cc" ) + + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +#define portNOP() __asm volatile ( "NOP" ) + +/*----------------------------------------------------------- +* Misc +*----------------------------------------------------------*/ + +#define portNUM_VECTORS 256 +#define portMAX_PRIORITY 15 +typedef void ( * ISR_Handler_t ) ( void ); + +/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU() + * before any floating point instructions are executed. */ +#ifndef configSUPPORT_FPU + #define configSUPPORT_FPU 0 +#endif + +#if configSUPPORT_FPU == 1 + void vPortTaskUsesFPU( void ); + #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() +#endif + +/* See the comments under the configUSE_COMMON_INTERRUPT_ENTRY_POINT definition + * below. */ +BaseType_t xPortRegisterCInterruptHandler( ISR_Handler_t pxHandler, + uint32_t ulVectorNumber ); +BaseType_t xPortInstallInterruptHandler( ISR_Handler_t pxHandler, + uint32_t ulVectorNumber ); + +#ifndef configAPIC_BASE + +/* configAPIC_BASE_ADDRESS sets the base address of the local APIC. It can + * be overridden in FreeRTOSConfig.h should it not be constant. */ + #define configAPIC_BASE 0xFEE00000UL +#endif + +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + +/* The FreeRTOS scheduling algorithm selects the task that will enter the + * Running state. configUSE_PORT_OPTIMISED_TASK_SELECTION is used to set how + * that is done. + * + * If configUSE_PORT_OPTIMISED_TASK_SELECTION is set to 0 then the task to + * enter the Running state is selected using a portable algorithm written in + * C. This is the slowest method, but the algorithm does not restrict the + * maximum number of unique RTOS task priorities that are available. + * + * If configUSE_PORT_OPTIMISED_TASK_SELECTION is set to 1 then the task to + * enter the Running state is selected using a single assembly instruction. + * This is the fastest method, but restricts the maximum number of unique RTOS + * task priorities to 32 (the same task priority can be assigned to any number + * of RTOS tasks). */ + #warning configUSE_PORT_OPTIMISED_TASK_SELECTION was not defined in FreeRTOSConfig.h and has been defaulted to 1 + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#ifndef configUSE_COMMON_INTERRUPT_ENTRY_POINT + +/* There are two ways of implementing interrupt handlers: + * + * 1) As standard C functions - + * + * This method can only be used if configUSE_COMMON_INTERRUPT_ENTRY_POINT + * is set to 1. The C function is installed using + * xPortRegisterCInterruptHandler(). + * + * This is the simplest of the two methods but incurs a slightly longer + * interrupt entry time. + * + * 2) By using an assembly stub that wraps the handler in the FreeRTOS + * portFREERTOS_INTERRUPT_ENTRY and portFREERTOS_INTERRUPT_EXIT macros. + * + * This method can always be used. It is slightly more complex than + * method 1 but benefits from a faster interrupt entry time. */ + #warning configUSE_COMMON_INTERRUPT_ENTRY_POINT was not defined in FreeRTOSConfig.h and has been defaulted to 1. + #define configUSE_COMMON_INTERRUPT_ENTRY_POINT 1 +#endif + +#ifndef configISR_STACK_SIZE + +/* Interrupt entry code will switch the stack in use to a dedicated system + * stack. + * + * configISR_STACK_SIZE defines the number of 32-bit values that can be stored + * on the system stack, and must be large enough to hold a potentially nested + * interrupt stack frame. */ + + #error configISR_STACK_SIZE was not defined in FreeRTOSConfig.h. +#endif + +#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY + +/* Interrupt safe FreeRTOS functions (those that end in "FromISR" must not + * be called from an interrupt that has a priority above that set by + * configMAX_API_CALL_INTERRUPT_PRIORITY. */ + #warning configMAX_API_CALL_INTERRUPT_PRIORITY was not defined in FreeRTOSConfig.h and has been defaulted to 10 + #define configMAX_API_CALL_INTERRUPT_PRIORITY 10 +#endif + +#ifndef configSUPPORT_FPU + #warning configSUPPORT_FPU was not defined in FreeRTOSConfig.h and has been defaulted to 0 + #define configSUPPORT_FPU 0 +#endif + +/* The value written to the task priority register to raise the interrupt mask + * to the maximum from which FreeRTOS API calls can be made. */ +#define portAPIC_PRIORITY_SHIFT ( 4UL ) +#define portAPIC_MAX_SUB_PRIORITY ( 0x0fUL ) +#define portMAX_API_CALL_PRIORITY ( ( configMAX_API_CALL_INTERRUPT_PRIORITY << portAPIC_PRIORITY_SHIFT ) | portAPIC_MAX_SUB_PRIORITY ) + +/* Asserts if interrupt safe FreeRTOS functions are called from a priority + * above the max system call interrupt priority. */ +#define portAPIC_PROCESSOR_PRIORITY ( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0xA0UL ) ) ) +#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( portAPIC_PROCESSOR_PRIORITY ) <= ( portMAX_API_CALL_PRIORITY ) ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/MCF5235/readme.md b/portable/GCC/MCF5235/readme.md new file mode 100644 index 000000000..ebf6ea603 --- /dev/null +++ b/portable/GCC/MCF5235/readme.md @@ -0,0 +1,2 @@ +The MCF5235 port is deprecated. The last FreeRTOS version that includes this port is 10.4.3. + diff --git a/portable/GCC/MSP430F449/port.c b/portable/GCC/MSP430F449/port.c new file mode 100644 index 000000000..48a1a7921 --- /dev/null +++ b/portable/GCC/MSP430F449/port.c @@ -0,0 +1,335 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * Changes from V2.5.2 + * + + usCriticalNesting now has a volatile qualifier. + */ + +/* Standard includes. */ +#include +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the MSP430 port. +*----------------------------------------------------------*/ + +/* Constants required for hardware setup. The tick ISR runs off the ACLK, + * not the MCLK. */ +#define portACLK_FREQUENCY_HZ ( ( TickType_t ) 32768 ) +#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 ) +#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x08 ) + +/* We require the address of the pxCurrentTCB variable, but don't want to know + * any details of its type. */ +typedef void TCB_t; +extern volatile TCB_t * volatile pxCurrentTCB; + +/* Most ports implement critical sections by placing the interrupt flags on + * the stack before disabling interrupts. Exiting the critical section is then + * simply a case of popping the flags from the stack. As mspgcc does not use + * a frame pointer this cannot be done as modifying the stack will clobber all + * the stack variables. Instead each task maintains a count of the critical + * section nesting depth. Each time a critical section is entered the count is + * incremented. Each time a critical section is left the count is decremented - + * with interrupts only being re-enabled if the count is zero. + * + * usCriticalNesting will get set to zero when the scheduler starts, but must + * not be initialised to zero as this will cause problems during the startup + * sequence. */ +volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING; +/*-----------------------------------------------------------*/ + +/* + * Macro to save a task context to the task stack. This simply pushes all the + * general purpose msp430 registers onto the stack, followed by the + * usCriticalNesting value used by the task. Finally the resultant stack + * pointer value is saved into the task control block so it can be retrieved + * the next time the task executes. + */ +#define portSAVE_CONTEXT() \ + asm volatile ( "push r4 \n\t" \ + "push r5 \n\t" \ + "push r6 \n\t" \ + "push r7 \n\t" \ + "push r8 \n\t" \ + "push r9 \n\t" \ + "push r10 \n\t" \ + "push r11 \n\t" \ + "push r12 \n\t" \ + "push r13 \n\t" \ + "push r14 \n\t" \ + "push r15 \n\t" \ + "mov.w usCriticalNesting, r14 \n\t" \ + "push r14 \n\t" \ + "mov.w pxCurrentTCB, r12 \n\t" \ + "mov.w r1, @r12 \n\t" \ + ); + +/* + * Macro to restore a task context from the task stack. This is effectively + * the reverse of portSAVE_CONTEXT(). First the stack pointer value is + * loaded from the task control block. Next the value for usCriticalNesting + * used by the task is retrieved from the stack - followed by the value of all + * the general purpose msp430 registers. + * + * The bic instruction ensures there are no low power bits set in the status + * register that is about to be popped from the stack. + */ +#define portRESTORE_CONTEXT() \ + asm volatile ( "mov.w pxCurrentTCB, r12 \n\t" \ + "mov.w @r12, r1 \n\t" \ + "pop r15 \n\t" \ + "mov.w r15, usCriticalNesting \n\t" \ + "pop r15 \n\t" \ + "pop r14 \n\t" \ + "pop r13 \n\t" \ + "pop r12 \n\t" \ + "pop r11 \n\t" \ + "pop r10 \n\t" \ + "pop r9 \n\t" \ + "pop r8 \n\t" \ + "pop r7 \n\t" \ + "pop r6 \n\t" \ + "pop r5 \n\t" \ + "pop r4 \n\t" \ + "bic #(0xf0),0(r1) \n\t" \ + "reti \n\t" \ + ); +/*-----------------------------------------------------------*/ + +/* + * Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but + * could have alternatively used the watchdog timer or timer 1. + */ +static void prvSetupTimerInterrupt( void ); +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See the header file portable.h. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* + * Place a few bytes of known values on the bottom of the stack. + * This is just useful for debugging and can be included if required. + * + * pxTopOfStack = ( StackType_t ) 0x1111; + * pxTopOfStack--; + * pxTopOfStack = ( StackType_t ) 0x2222; + * pxTopOfStack--; + * pxTopOfStack = ( StackType_t ) 0x3333; + * pxTopOfStack--; + */ + + /* The msp430 automatically pushes the PC then SR onto the stack before + * executing an ISR. We want the stack to look just as if this has happened + * so place a pointer to the start of the task on the stack first - followed + * by the flags we want the task to use when it starts up. */ + *pxTopOfStack = ( StackType_t ) pxCode; + pxTopOfStack--; + *pxTopOfStack = portFLAGS_INT_ENABLED; + pxTopOfStack--; + + /* Next the general purpose registers. */ + *pxTopOfStack = ( StackType_t ) 0x4444; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x5555; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x6666; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x7777; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x8888; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x9999; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xaaaa; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xbbbb; + pxTopOfStack--; +#ifdef __MSPGCC__ + *pxTopOfStack = ( StackType_t ) 0xcccc; +#else + /* The MSP430 EABI expects the function parameter in R12. */ + *pxTopOfStack = ( StackType_t ) pvParameters; +#endif + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xdddd; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xeeee; + pxTopOfStack--; +#ifdef __MSPGCC__ + /* The mspgcc ABI expects the function parameter in R15. */ + *pxTopOfStack = ( StackType_t ) pvParameters; +#else + *pxTopOfStack = ( StackType_t ) 0xffff; +#endif + pxTopOfStack--; + + /* The code generated by the mspgcc compiler does not maintain separate + * stack and frame pointers. The portENTER_CRITICAL macro cannot therefore + * use the stack as per other ports. Instead a variable is used to keep + * track of the critical section nesting. This variable has to be stored + * as part of the task context and is initially set to zero. */ + *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING; + + /* Return a pointer to the top of the stack we have generated so this can + * be stored in the task control block for the task. */ + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Setup the hardware to generate the tick. Interrupts are disabled when + * this function is called. */ + prvSetupTimerInterrupt(); + + /* Restore the context of the first task that is going to run. */ + portRESTORE_CONTEXT(); + + /* Should not get here as the tasks are now running! */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the MSP430 port will get stopped. If required simply + * disable the tick interrupt here. */ +} +/*-----------------------------------------------------------*/ + +/* + * Manual context switch called by portYIELD or taskYIELD. + * + * The first thing we do is save the registers so we can use a naked attribute. + */ +void vPortYield( void ) __attribute__( ( naked ) ); +void vPortYield( void ) +{ + /* We want the stack of the task being saved to look exactly as if the task + * was saved during a pre-emptive RTOS tick ISR. Before calling an ISR the + * msp430 places the status register onto the stack. As this is a function + * call and not an ISR we have to do this manually. */ + asm volatile ( "push r2" ); + _DINT(); + + /* Save the context of the current task. */ + portSAVE_CONTEXT(); + + /* Switch to the highest priority task that is ready to run. */ + vTaskSwitchContext(); + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * Hardware initialisation to generate the RTOS tick. This uses timer 0 + * but could alternatively use the watchdog timer or timer 1. + */ +static void prvSetupTimerInterrupt( void ) +{ + /* Ensure the timer is stopped. */ + TACTL = 0; + + /* Run the timer of the ACLK. */ + TACTL = TASSEL_1; + + /* Clear everything to start with. */ + TACTL |= TACLR; + + /* Set the compare match value according to the tick rate we want. */ + TACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ; + + /* Enable the interrupts. */ + TACCTL0 = CCIE; + + /* Start up clean. */ + TACTL |= TACLR; + + /* Up mode. */ + TACTL |= MC_1; +} +/*-----------------------------------------------------------*/ + +/* + * The interrupt service routine used depends on whether the pre-emptive + * scheduler is being used or not. + */ + +#if configUSE_PREEMPTION == 1 + +/* + * Tick ISR for preemptive scheduler. We can use a naked attribute as + * the context is saved at the start of vPortYieldFromTick(). The tick + * count is incremented after the context is saved. + */ + interrupt( TIMERA0_VECTOR ) void prvTickISR( void ) __attribute__( ( naked ) ); + interrupt( TIMERA0_VECTOR ) void prvTickISR( void ) + { + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT(); + + /* Increment the tick count then switch to the highest priority task + * that is ready to run. */ + if( xTaskIncrementTick() != pdFALSE ) + { + vTaskSwitchContext(); + } + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT(); + } + +#else /* if configUSE_PREEMPTION == 1 */ + +/* + * Tick ISR for the cooperative scheduler. All this does is increment the + * tick count. We don't need to switch context, this can only be done by + * manual calls to taskYIELD(); + */ + interrupt( TIMERA0_VECTOR ) void prvTickISR( void ); + interrupt( TIMERA0_VECTOR ) void prvTickISR( void ) + { + xTaskIncrementTick(); + } +#endif /* if configUSE_PREEMPTION == 1 */ diff --git a/portable/GCC/MSP430F449/portmacro.h b/portable/GCC/MSP430F449/portmacro.h new file mode 100644 index 000000000..de2014683 --- /dev/null +++ b/portable/GCC/MSP430F449/portmacro.h @@ -0,0 +1,139 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE uint16_t +#define portBASE_TYPE short +#define portPOINTER_SIZE_TYPE uint16_t + +typedef portSTACK_TYPE StackType_t; +typedef short BaseType_t; +typedef unsigned short UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Interrupt control macros. */ +#define portDISABLE_INTERRUPTS() asm volatile ( "DINT" ); asm volatile ( "NOP" ) +#define portENABLE_INTERRUPTS() asm volatile ( "EINT" ); asm volatile ( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Critical section control macros. */ +#define portNO_CRITICAL_SECTION_NESTING ( ( uint16_t ) 0 ) + +#define portENTER_CRITICAL() \ + { \ + extern volatile uint16_t usCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + \ + /* Now that interrupts are disabled, ulCriticalNesting can be accessed */ \ + /* directly. Increment ulCriticalNesting to keep a count of how many */ \ + /* times portENTER_CRITICAL() has been called. */ \ + usCriticalNesting++; \ + } + +#define portEXIT_CRITICAL() \ + { \ + extern volatile uint16_t usCriticalNesting; \ + \ + if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ + { \ + /* Decrement the nesting count as we are leaving a critical section. */ \ + usCriticalNesting--; \ + \ + /* If the nesting level has reached zero then interrupts should be */ \ + /* re-enabled. */ \ + if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } \ + } +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +extern void vPortYield( void ) __attribute__( ( naked ) ); +#define portYIELD() vPortYield() +#define portNOP() asm volatile ( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 2 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + +/* GCC used to define these but doesn't any more */ +#define interrupt(vector) __attribute__((__interrupt__(vector))) +#define wakeup __attribute__((__wakeup__)) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/MicroBlaze/port.c b/portable/GCC/MicroBlaze/port.c new file mode 100644 index 000000000..fb8b410be --- /dev/null +++ b/portable/GCC/MicroBlaze/port.c @@ -0,0 +1,334 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the MicroBlaze port. +*----------------------------------------------------------*/ + + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Standard includes. */ +#include + +/* Hardware includes. */ +#include +#include +#include + +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) + #error configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 to use this port. +#endif + +/* Tasks are started with interrupts enabled. */ +#define portINITIAL_MSR_STATE ( ( StackType_t ) 0x02 ) + +/* Tasks are started with a critical section nesting of 0 - however prior + * to the scheduler being commenced we don't want the critical nesting level + * to reach zero, so it is initialised to a high value. */ +#define portINITIAL_NESTING_VALUE ( 0xff ) + +/* Our hardware setup only uses one counter. */ +#define portCOUNTER_0 0 + +/* The stack used by the ISR is filled with a known value to assist in + * debugging. */ +#define portISR_STACK_FILL_VALUE 0x55555555 + +/* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task + * maintains it's own count, so this variable is saved as part of the task + * context. */ +volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE; + +/* To limit the amount of stack required by each task, this port uses a + * separate stack for interrupts. */ +uint32_t * pulISRStack; + +/*-----------------------------------------------------------*/ + +/* + * Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but + * could have alternatively used the watchdog timer or timer 1. + */ +static void prvSetupTimerInterrupt( void ); +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been made. + * + * See the header file portable.h. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + extern void * _SDA2_BASE_; + extern void * _SDA_BASE_; + const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_; + const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_; + + /* Place a few bytes of known values on the bottom of the stack. + * This is essential for the Microblaze port and these lines must + * not be omitted. The parameter value will overwrite the + * 0x22222222 value during the function prologue. */ + *pxTopOfStack = ( StackType_t ) 0x11111111; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x22222222; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x33333333; + pxTopOfStack--; + + /* First stack an initial value for the critical section nesting. This + * is initialised to zero as tasks are started with interrupts enabled. */ + *pxTopOfStack = ( StackType_t ) 0x00; /* R0. */ + + /* Place an initial value for all the general purpose registers. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) ulR2; /* R2 - small data area. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03; /* R3. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04; /* R4. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R5 contains the function call parameters. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06; /* R6. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07; /* R7. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08; /* R8. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09; /* R9. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x0a; /* R10. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x0b; /* R11. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x0c; /* R12. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) ulR13; /* R13 - small data read write area. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* R14. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x0f; /* R15. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10; /* R16. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11; /* R17. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12; /* R18. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x13; /* R19. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x14; /* R20. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x15; /* R21. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x16; /* R22. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x17; /* R23. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x18; /* R24. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x19; /* R25. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x1a; /* R26. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x1b; /* R27. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x1c; /* R28. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x1d; /* R29. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x1e; /* R30. */ + pxTopOfStack--; + + /* The MSR is stacked between R30 and R31. */ + *pxTopOfStack = portINITIAL_MSR_STATE; + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0x1f; /* R31. */ + pxTopOfStack--; + + /* Return a pointer to the top of the stack we have generated so this can + * be stored in the task control block for the task. */ + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + extern void( __FreeRTOS_interrupt_Handler )( void ); + extern void( vStartFirstTask )( void ); + + + /* Setup the FreeRTOS interrupt handler. Code copied from crt0.s. */ + asm volatile ( "la r6, r0, __FreeRTOS_interrupt_handler \n\t" \ + "sw r6, r1, r0 \n\t" \ + "lhu r7, r1, r0 \n\t" \ + "shi r7, r0, 0x12 \n\t" \ + "shi r6, r0, 0x16 " ); + + /* Setup the hardware to generate the tick. Interrupts are disabled when + * this function is called. */ + prvSetupTimerInterrupt(); + + /* Allocate the stack to be used by the interrupt handler. */ + pulISRStack = ( uint32_t * ) pvPortMalloc( configMINIMAL_STACK_SIZE * sizeof( StackType_t ) ); + + /* Restore the context of the first task that is going to run. */ + if( pulISRStack != NULL ) + { + /* Fill the ISR stack with a known value to facilitate debugging. */ + memset( pulISRStack, portISR_STACK_FILL_VALUE, configMINIMAL_STACK_SIZE * sizeof( StackType_t ) ); + pulISRStack += ( configMINIMAL_STACK_SIZE - 1 ); + + /* Kick off the first task. */ + vStartFirstTask(); + } + + /* Should not get here as the tasks are now running! */ + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented. */ +} +/*-----------------------------------------------------------*/ + +/* + * Manual context switch called by portYIELD or taskYIELD. + */ +void vPortYield( void ) +{ + extern void VPortYieldASM( void ); + + /* Perform the context switch in a critical section to assure it is + * not interrupted by the tick ISR. It is not a problem to do this as + * each task maintains it's own interrupt status. */ + portENTER_CRITICAL(); + + /* Jump directly to the yield function to ensure there is no + * compiler generated prologue code. */ + asm volatile ( "bralid r14, VPortYieldASM \n\t" \ + "or r0, r0, r0 \n\t" ); + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +/* + * Hardware initialisation to generate the RTOS tick. + */ +static void prvSetupTimerInterrupt( void ) +{ + XTmrCtr xTimer; + const uint32_t ulCounterValue = configCPU_CLOCK_HZ / configTICK_RATE_HZ; + UBaseType_t uxMask; + + /* The OPB timer1 is used to generate the tick. Use the provided library + * functions to enable the timer and set the tick frequency. */ + XTmrCtr_mDisable( XPAR_OPB_TIMER_1_BASEADDR, XPAR_OPB_TIMER_1_DEVICE_ID ); + XTmrCtr_Initialize( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID ); + XTmrCtr_mSetLoadReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCounterValue ); + XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_LOAD_MASK | XTC_CSR_INT_occurred_MASK ); + + /* Set the timer interrupt enable bit while maintaining the other bit + * states. */ + uxMask = XIntc_In32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ) ); + uxMask |= XPAR_OPB_TIMER_1_INTERRUPT_MASK; + XIntc_Out32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ), ( uxMask ) ); + + XTmrCtr_Start( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID ); + XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK | XTC_CSR_INT_occurred_MASK ); + XIntc_mAckIntr( XPAR_INTC_SINGLE_BASEADDR, 1 ); +} +/*-----------------------------------------------------------*/ + +/* + * The interrupt handler placed in the interrupt vector when the scheduler is + * started. The task context has already been saved when this is called. + * This handler determines the interrupt source and calls the relevant + * peripheral handler. + */ +void vTaskISRHandler( void ) +{ + static uint32_t ulPending; + + /* Which interrupts are pending? */ + ulPending = XIntc_In32( ( XPAR_INTC_SINGLE_BASEADDR + XIN_IVR_OFFSET ) ); + + if( ulPending < XPAR_INTC_MAX_NUM_INTR_INPUTS ) + { + static XIntc_VectorTableEntry * pxTablePtr; + static XIntc_Config * pxConfig; + static uint32_t ulInterruptMask; + + ulInterruptMask = ( uint32_t ) 1 << ulPending; + + /* Get the configuration data using the device ID */ + pxConfig = &XIntc_ConfigTable[ ( uint32_t ) XPAR_INTC_SINGLE_DEVICE_ID ]; + + pxTablePtr = &( pxConfig->HandlerTable[ ulPending ] ); + + if( pxConfig->AckBeforeService & ( ulInterruptMask ) ) + { + XIntc_mAckIntr( pxConfig->BaseAddress, ulInterruptMask ); + pxTablePtr->Handler( pxTablePtr->CallBackRef ); + } + else + { + pxTablePtr->Handler( pxTablePtr->CallBackRef ); + XIntc_mAckIntr( pxConfig->BaseAddress, ulInterruptMask ); + } + } +} +/*-----------------------------------------------------------*/ + +/* + * Handler for the timer interrupt. + */ +void vTickISR( void * pvBaseAddress ) +{ + uint32_t ulCSR; + + /* Increment the RTOS tick - this might cause a task to unblock. */ + if( xTaskIncrementTick() != pdFALSE ) + { + vTaskSwitchContext(); + } + + /* Clear the timer interrupt */ + ulCSR = XTmrCtr_mGetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, 0 ); + XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCSR ); +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/MicroBlaze/portasm.s b/portable/GCC/MicroBlaze/portasm.s new file mode 100644 index 000000000..b9c1dc8b3 --- /dev/null +++ b/portable/GCC/MicroBlaze/portasm.s @@ -0,0 +1,194 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + .extern pxCurrentTCB + .extern vTaskISRHandler + .extern vTaskSwitchContext + .extern uxCriticalNesting + .extern pulISRStack + + .global __FreeRTOS_interrupt_handler + .global VPortYieldASM + .global vStartFirstTask + + +.macro portSAVE_CONTEXT + /* Make room for the context on the stack. */ + addik r1, r1, -132 + /* Save r31 so it can then be used. */ + swi r31, r1, 4 + /* Copy the msr into r31 - this is stacked later. */ + mfs r31, rmsr + /* Stack general registers. */ + swi r30, r1, 12 + swi r29, r1, 16 + swi r28, r1, 20 + swi r27, r1, 24 + swi r26, r1, 28 + swi r25, r1, 32 + swi r24, r1, 36 + swi r23, r1, 40 + swi r22, r1, 44 + swi r21, r1, 48 + swi r20, r1, 52 + swi r19, r1, 56 + swi r18, r1, 60 + swi r17, r1, 64 + swi r16, r1, 68 + swi r15, r1, 72 + swi r13, r1, 80 + swi r12, r1, 84 + swi r11, r1, 88 + swi r10, r1, 92 + swi r9, r1, 96 + swi r8, r1, 100 + swi r7, r1, 104 + swi r6, r1, 108 + swi r5, r1, 112 + swi r4, r1, 116 + swi r3, r1, 120 + swi r2, r1, 124 + /* Stack the critical section nesting value. */ + lwi r3, r0, uxCriticalNesting + swi r3, r1, 128 + /* Save the top of stack value to the TCB. */ + lwi r3, r0, pxCurrentTCB + sw r1, r0, r3 + + .endm + +.macro portRESTORE_CONTEXT + /* Load the top of stack value from the TCB. */ + lwi r3, r0, pxCurrentTCB + lw r1, r0, r3 + /* Restore the general registers. */ + lwi r31, r1, 4 + lwi r30, r1, 12 + lwi r29, r1, 16 + lwi r28, r1, 20 + lwi r27, r1, 24 + lwi r26, r1, 28 + lwi r25, r1, 32 + lwi r24, r1, 36 + lwi r23, r1, 40 + lwi r22, r1, 44 + lwi r21, r1, 48 + lwi r20, r1, 52 + lwi r19, r1, 56 + lwi r18, r1, 60 + lwi r17, r1, 64 + lwi r16, r1, 68 + lwi r15, r1, 72 + lwi r14, r1, 76 + lwi r13, r1, 80 + lwi r12, r1, 84 + lwi r11, r1, 88 + lwi r10, r1, 92 + lwi r9, r1, 96 + lwi r8, r1, 100 + lwi r7, r1, 104 + lwi r6, r1, 108 + lwi r5, r1, 112 + lwi r4, r1, 116 + lwi r2, r1, 124 + + /* Load the critical nesting value. */ + lwi r3, r1, 128 + swi r3, r0, uxCriticalNesting + + /* Obtain the MSR value from the stack. */ + lwi r3, r1, 8 + + /* Are interrupts enabled in the MSR? If so return using an return from + interrupt instruction to ensure interrupts are enabled only once the task + is running again. */ + andi r3, r3, 2 + beqid r3, 36 + or r0, r0, r0 + + /* Reload the rmsr from the stack, clear the enable interrupt bit in the + value before saving back to rmsr register, then return enabling interrupts + as we return. */ + lwi r3, r1, 8 + andi r3, r3, ~2 + mts rmsr, r3 + lwi r3, r1, 120 + addik r1, r1, 132 + rtid r14, 0 + or r0, r0, r0 + + /* Reload the rmsr from the stack, place it in the rmsr register, and + return without enabling interrupts. */ + lwi r3, r1, 8 + mts rmsr, r3 + lwi r3, r1, 120 + addik r1, r1, 132 + rtsd r14, 0 + or r0, r0, r0 + + .endm + + .text + .align 2 + + +__FreeRTOS_interrupt_handler: + portSAVE_CONTEXT + /* Entered via an interrupt so interrupts must be enabled in msr. */ + ori r31, r31, 2 + /* Stack msr. */ + swi r31, r1, 8 + /* Stack the return address. As we entered via an interrupt we do + not need to modify the return address prior to stacking. */ + swi r14, r1, 76 + /* Now switch to use the ISR stack. */ + lwi r3, r0, pulISRStack + add r1, r3, r0 + bralid r15, vTaskISRHandler + or r0, r0, r0 + portRESTORE_CONTEXT + + +VPortYieldASM: + portSAVE_CONTEXT + /* Stack msr. */ + swi r31, r1, 8 + /* Modify the return address so we return to the instruction after the + exception. */ + addi r14, r14, 8 + swi r14, r1, 76 + /* Now switch to use the ISR stack. */ + lwi r3, r0, pulISRStack + add r1, r3, r0 + bralid r15, vTaskSwitchContext + or r0, r0, r0 + portRESTORE_CONTEXT + +vStartFirstTask: + portRESTORE_CONTEXT + + diff --git a/portable/GCC/MicroBlaze/portmacro.h b/portable/GCC/MicroBlaze/portmacro.h new file mode 100644 index 000000000..a81e07cde --- /dev/null +++ b/portable/GCC/MicroBlaze/portmacro.h @@ -0,0 +1,135 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Interrupt control macros. */ +void microblaze_disable_interrupts( void ); +void microblaze_enable_interrupts( void ); +#define portDISABLE_INTERRUPTS() microblaze_disable_interrupts() +#define portENABLE_INTERRUPTS() microblaze_enable_interrupts() +/*-----------------------------------------------------------*/ + +/* Critical section macros. */ +void vPortEnterCritical( void ); +void vPortExitCritical( void ); +#define portENTER_CRITICAL() \ + { \ + extern UBaseType_t uxCriticalNesting; \ + microblaze_disable_interrupts(); \ + uxCriticalNesting++; \ + } + +#define portEXIT_CRITICAL() \ + { \ + extern UBaseType_t uxCriticalNesting; \ + /* Interrupts are disabled, so we can */ \ + /* access the variable directly. */ \ + uxCriticalNesting--; \ + if( uxCriticalNesting == 0 ) \ + { \ + /* The nesting has unwound and we \ + * can enable interrupts again. */ \ + portENABLE_INTERRUPTS(); \ + } \ + } + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +void vPortYield( void ); +#define portYIELD() vPortYield() + +void vTaskSwitchContext(); +#define portYIELD_FROM_ISR() vTaskSwitchContext() +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 4 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() asm volatile ( "NOP" ) +#define portMEMORY_BARRIER() asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/MicroBlazeV8/port.c b/portable/GCC/MicroBlazeV8/port.c new file mode 100644 index 000000000..1557af645 --- /dev/null +++ b/portable/GCC/MicroBlazeV8/port.c @@ -0,0 +1,457 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the MicroBlaze port. +*----------------------------------------------------------*/ + + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Standard includes. */ +#include + +/* Hardware includes. */ +#include +#include +#include + +/* Tasks are started with a critical section nesting of 0 - however, prior to + * the scheduler being commenced interrupts should not be enabled, so the critical + * nesting variable is initialised to a non-zero value. */ +#define portINITIAL_NESTING_VALUE ( 0xff ) + +/* The bit within the MSR register that enabled/disables interrupts and + * exceptions respectively. */ +#define portMSR_IE ( 0x02U ) +#define portMSR_EE ( 0x100U ) + +/* If the floating point unit is included in the MicroBlaze build, then the + * FSR register is saved as part of the task context. portINITIAL_FSR is the value + * given to the FSR register when the initial context is set up for a task being + * created. */ +#define portINITIAL_FSR ( 0U ) +/*-----------------------------------------------------------*/ + +/* + * Initialise the interrupt controller instance. + */ +static int32_t prvInitialiseInterruptController( void ); + +/* Ensure the interrupt controller instance variable is initialised before it is + * used, and that the initialisation only happens once. + */ +static int32_t prvEnsureInterruptControllerIsInitialised( void ); + +/*-----------------------------------------------------------*/ + +/* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task + * maintains its own count, so this variable is saved as part of the task + * context. */ +volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE; + +/* This port uses a separate stack for interrupts. This prevents the stack of + * every task needing to be large enough to hold an entire interrupt stack on top + * of the task stack. */ +uint32_t * pulISRStack; + +/* If an interrupt requests a context switch, then ulTaskSwitchRequested will + * get set to 1. ulTaskSwitchRequested is inspected just before the main interrupt + * handler exits. If, at that time, ulTaskSwitchRequested is set to 1, the kernel + * will call vTaskSwitchContext() to ensure the task that runs immediately after + * the interrupt exists is the highest priority task that is able to run. This is + * an unusual mechanism, but is used for this port because a single interrupt can + * cause the servicing of multiple peripherals - and it is inefficient to call + * vTaskSwitchContext() multiple times as each peripheral is serviced. */ +volatile uint32_t ulTaskSwitchRequested = 0UL; + +/* The instance of the interrupt controller used by this port. This is required + * by the Xilinx library API functions. */ +static XIntc xInterruptControllerInstance; + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been made. + * + * See the portable.h header file. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + extern void * _SDA2_BASE_; + extern void * _SDA_BASE_; + const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_; + const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_; + + /* Place a few bytes of known values on the bottom of the stack. + * This is essential for the Microblaze port and these lines must + * not be omitted. */ + *pxTopOfStack = ( StackType_t ) 0x00000000; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x00000000; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x00000000; + pxTopOfStack--; + + #if ( XPAR_MICROBLAZE_USE_FPU != 0 ) + /* The FSR value placed in the initial task context is just 0. */ + *pxTopOfStack = portINITIAL_FSR; + pxTopOfStack--; + #endif + + /* The MSR value placed in the initial task context should have interrupts + * disabled. Each task will enable interrupts automatically when it enters + * the running state for the first time. */ + *pxTopOfStack = mfmsr() & ~portMSR_IE; + + #if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) + { + /* Ensure exceptions are enabled for the task. */ + *pxTopOfStack |= portMSR_EE; + } + #endif + + pxTopOfStack--; + + /* First stack an initial value for the critical section nesting. This + * is initialised to zero. */ + *pxTopOfStack = ( StackType_t ) 0x00; + + /* R0 is always zero. */ + /* R1 is the SP. */ + + /* Place an initial value for all the general purpose registers. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) ulR2; /* R2 - read only small data area. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03; /* R3 - return values and temporaries. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04; /* R4 - return values and temporaries. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R5 contains the function call parameters. */ + + #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06; /* R6 - other parameters and temporaries. Used as the return address from vPortTaskEntryPoint. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07; /* R7 - other parameters and temporaries. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08; /* R8 - other parameters and temporaries. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09; /* R9 - other parameters and temporaries. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x0a; /* R10 - other parameters and temporaries. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x0b; /* R11 - temporaries. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x0c; /* R12 - temporaries. */ + pxTopOfStack--; + #else /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */ + pxTopOfStack -= 8; + #endif /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */ + + *pxTopOfStack = ( StackType_t ) ulR13; /* R13 - read/write small data area. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* R14 - return address for interrupt. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) NULL; /* R15 - return address for subroutine. */ + + #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10; /* R16 - return address for trap (debugger). */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11; /* R17 - return address for exceptions, if configured. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12; /* R18 - reserved for assembler and compiler temporaries. */ + pxTopOfStack--; + #else + pxTopOfStack -= 4; + #endif + + *pxTopOfStack = ( StackType_t ) 0x00; /* R19 - must be saved across function calls. Callee-save. Seems to be interpreted as the frame pointer. */ + + #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x14; /* R20 - reserved for storing a pointer to the Global Offset Table (GOT) in Position Independent Code (PIC). Non-volatile in non-PIC code. Must be saved across function calls. Callee-save. Not used by FreeRTOS. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x15; /* R21 - must be saved across function calls. Callee-save. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x16; /* R22 - must be saved across function calls. Callee-save. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x17; /* R23 - must be saved across function calls. Callee-save. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x18; /* R24 - must be saved across function calls. Callee-save. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x19; /* R25 - must be saved across function calls. Callee-save. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x1a; /* R26 - must be saved across function calls. Callee-save. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x1b; /* R27 - must be saved across function calls. Callee-save. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x1c; /* R28 - must be saved across function calls. Callee-save. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x1d; /* R29 - must be saved across function calls. Callee-save. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x1e; /* R30 - must be saved across function calls. Callee-save. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x1f; /* R31 - must be saved across function calls. Callee-save. */ + pxTopOfStack--; + #else /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */ + pxTopOfStack -= 13; + #endif /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */ + + /* Return a pointer to the top of the stack that has been generated so this + * can be stored in the task control block for the task. */ + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + extern void( vPortStartFirstTask )( void ); + extern uint32_t _stack[]; + + /* Setup the hardware to generate the tick. Interrupts are disabled when + * this function is called. + * + * This port uses an application defined callback function to install the tick + * interrupt handler because the kernel will run on lots of different + * MicroBlaze and FPGA configurations - not all of which will have the same + * timer peripherals defined or available. An example definition of + * vApplicationSetupTimerInterrupt() is provided in the official demo + * application that accompanies this port. */ + vApplicationSetupTimerInterrupt(); + + /* Reuse the stack from main() as the stack for the interrupts/exceptions. */ + pulISRStack = ( uint32_t * ) _stack; + + /* Ensure there is enough space for the functions called from the interrupt + * service routines to write back into the stack frame of the caller. */ + pulISRStack -= 2; + + /* Restore the context of the first task that is going to run. From here + * on, the created tasks will be executing. */ + vPortStartFirstTask(); + + /* Should not get here as the tasks are now running! */ + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +/* + * Manual context switch called by portYIELD or taskYIELD. + */ +void vPortYield( void ) +{ + extern void VPortYieldASM( void ); + + /* Perform the context switch in a critical section to assure it is + * not interrupted by the tick ISR. It is not a problem to do this as + * each task maintains its own interrupt status. */ + portENTER_CRITICAL(); + { + /* Jump directly to the yield function to ensure there is no + * compiler generated prologue code. */ + asm volatile ( "bralid r14, VPortYieldASM \n\t" \ + "or r0, r0, r0 \n\t" ); + } + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +void vPortEnableInterrupt( uint8_t ucInterruptID ) +{ + int32_t lReturn; + + /* An API function is provided to enable an interrupt in the interrupt + * controller because the interrupt controller instance variable is private + * to this file. */ + lReturn = prvEnsureInterruptControllerIsInitialised(); + + if( lReturn == pdPASS ) + { + XIntc_Enable( &xInterruptControllerInstance, ucInterruptID ); + } + + configASSERT( lReturn ); +} +/*-----------------------------------------------------------*/ + +void vPortDisableInterrupt( uint8_t ucInterruptID ) +{ + int32_t lReturn; + + /* An API function is provided to disable an interrupt in the interrupt + * controller because the interrupt controller instance variable is private + * to this file. */ + lReturn = prvEnsureInterruptControllerIsInitialised(); + + if( lReturn == pdPASS ) + { + XIntc_Disable( &xInterruptControllerInstance, ucInterruptID ); + } + + configASSERT( lReturn ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, + XInterruptHandler pxHandler, + void * pvCallBackRef ) +{ + int32_t lReturn; + + /* An API function is provided to install an interrupt handler because the + * interrupt controller instance variable is private to this file. */ + + lReturn = prvEnsureInterruptControllerIsInitialised(); + + if( lReturn == pdPASS ) + { + lReturn = XIntc_Connect( &xInterruptControllerInstance, ucInterruptID, pxHandler, pvCallBackRef ); + } + + if( lReturn == XST_SUCCESS ) + { + lReturn = pdPASS; + } + + configASSERT( lReturn == pdPASS ); + + return lReturn; +} +/*-----------------------------------------------------------*/ + +static int32_t prvEnsureInterruptControllerIsInitialised( void ) +{ + static int32_t lInterruptControllerInitialised = pdFALSE; + int32_t lReturn; + + /* Ensure the interrupt controller instance variable is initialised before + * it is used, and that the initialisation only happens once. */ + if( lInterruptControllerInitialised != pdTRUE ) + { + lReturn = prvInitialiseInterruptController(); + + if( lReturn == pdPASS ) + { + lInterruptControllerInitialised = pdTRUE; + } + } + else + { + lReturn = pdPASS; + } + + return lReturn; +} +/*-----------------------------------------------------------*/ + +/* + * Handler for the timer interrupt. This is the handler that the application + * defined callback function vApplicationSetupTimerInterrupt() should install. + */ +void vPortTickISR( void * pvUnused ) +{ + extern void vApplicationClearTimerInterrupt( void ); + + /* Ensure the unused parameter does not generate a compiler warning. */ + ( void ) pvUnused; + + /* This port uses an application defined callback function to clear the tick + * interrupt because the kernel will run on lots of different MicroBlaze and + * FPGA configurations - not all of which will have the same timer peripherals + * defined or available. An example definition of + * vApplicationClearTimerInterrupt() is provided in the official demo + * application that accompanies this port. */ + vApplicationClearTimerInterrupt(); + + /* Increment the RTOS tick - this might cause a task to unblock. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Force vTaskSwitchContext() to be called as the interrupt exits. */ + ulTaskSwitchRequested = 1; + } +} +/*-----------------------------------------------------------*/ + +static int32_t prvInitialiseInterruptController( void ) +{ + int32_t lStatus; + + lStatus = XIntc_Initialize( &xInterruptControllerInstance, configINTERRUPT_CONTROLLER_TO_USE ); + + if( lStatus == XST_SUCCESS ) + { + /* Initialise the exception table. */ + Xil_ExceptionInit(); + + /* Service all pending interrupts each time the handler is entered. */ + XIntc_SetIntrSvcOption( xInterruptControllerInstance.BaseAddress, XIN_SVC_ALL_ISRS_OPTION ); + + /* Install exception handlers if the MicroBlaze is configured to handle + * exceptions, and the application defined constant + * configINSTALL_EXCEPTION_HANDLERS is set to 1. */ + #if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) + { + vPortExceptionsInstallHandlers(); + } + #endif /* MICROBLAZE_EXCEPTIONS_ENABLED */ + + /* Start the interrupt controller. Interrupts are enabled when the + * scheduler starts. */ + lStatus = XIntc_Start( &xInterruptControllerInstance, XIN_REAL_MODE ); + + if( lStatus == XST_SUCCESS ) + { + lStatus = pdPASS; + } + else + { + lStatus = pdFAIL; + } + } + + configASSERT( lStatus == pdPASS ); + + return lStatus; +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/MicroBlazeV8/port_exceptions.c b/portable/GCC/MicroBlazeV8/port_exceptions.c new file mode 100644 index 000000000..281a328b4 --- /dev/null +++ b/portable/GCC/MicroBlazeV8/port_exceptions.c @@ -0,0 +1,278 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Hardware includes. */ +#include +#include + +/* The Xilinx library defined exception entry point stacks a number of + * registers. These definitions are offsets from the stack pointer to the various + * stacked register values. */ +#define portexR3_STACK_OFFSET 4 +#define portexR4_STACK_OFFSET 5 +#define portexR5_STACK_OFFSET 6 +#define portexR6_STACK_OFFSET 7 +#define portexR7_STACK_OFFSET 8 +#define portexR8_STACK_OFFSET 9 +#define portexR9_STACK_OFFSET 10 +#define portexR10_STACK_OFFSET 11 +#define portexR11_STACK_OFFSET 12 +#define portexR12_STACK_OFFSET 13 +#define portexR15_STACK_OFFSET 16 +#define portexR18_STACK_OFFSET 19 +#define portexMSR_STACK_OFFSET 20 +#define portexR19_STACK_OFFSET -1 + +/* This is defined to equal the size, in bytes, of the stack frame generated by + * the Xilinx standard library exception entry point. It is required to determine + * the stack pointer value prior to the exception being entered. */ +#define portexASM_HANDLER_STACK_FRAME_SIZE 84UL + +/* The number of bytes a MicroBlaze instruction consumes. */ +#define portexINSTRUCTION_SIZE 4 + +/* Exclude this entire file if the MicroBlaze is not configured to handle + * exceptions, or the application defined configuration constant + * configINSTALL_EXCEPTION_HANDLERS is not set to 1. */ +#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) + +/* This variable is set in the exception entry code, before + * vPortExceptionHandler is called. */ + uint32_t * pulStackPointerOnFunctionEntry = NULL; + +/* This is the structure that is filled with the MicroBlaze context as it + * existed immediately prior to the exception occurrence. A pointer to this + * structure is passed into the vApplicationExceptionRegisterDump() callback + * function, if one is defined. */ + static xPortRegisterDump xRegisterDump; + +/* This is the FreeRTOS exception handler that is installed for all exception + * types. It is called from vPortExceptionHandlerEntry() - which is itself defined + * in portasm.S. */ + void vPortExceptionHandler( void * pvExceptionID ); + extern void vPortExceptionHandlerEntry( void * pvExceptionID ); + +/*-----------------------------------------------------------*/ + +/* vApplicationExceptionRegisterDump() is a callback function that the + * application can optionally define to receive a populated xPortRegisterDump + * structure. If the application chooses not to define a version of + * vApplicationExceptionRegisterDump() then this weekly defined default + * implementation will be called instead. */ + extern void vApplicationExceptionRegisterDump( xPortRegisterDump * xRegisterDump ) __attribute__( ( weak ) ); + void vApplicationExceptionRegisterDump( xPortRegisterDump * xRegisterDump ) + { + ( void ) xRegisterDump; + + for( ; ; ) + { + portNOP(); + } + } +/*-----------------------------------------------------------*/ + + void vPortExceptionHandler( void * pvExceptionID ) + { + extern void * pxCurrentTCB; + + /* Fill an xPortRegisterDump structure with the MicroBlaze context as it + * was immediately before the exception occurrence. */ + + /* First fill in the name and handle of the task that was in the Running + * state when the exception occurred. */ + xRegisterDump.xCurrentTaskHandle = pxCurrentTCB; + xRegisterDump.pcCurrentTaskName = pcTaskGetName( NULL ); + + configASSERT( pulStackPointerOnFunctionEntry ); + + /* Obtain the values of registers that were stacked prior to this function + * being called, and may have changed since they were stacked. */ + xRegisterDump.ulR3 = pulStackPointerOnFunctionEntry[ portexR3_STACK_OFFSET ]; + xRegisterDump.ulR4 = pulStackPointerOnFunctionEntry[ portexR4_STACK_OFFSET ]; + xRegisterDump.ulR5 = pulStackPointerOnFunctionEntry[ portexR5_STACK_OFFSET ]; + xRegisterDump.ulR6 = pulStackPointerOnFunctionEntry[ portexR6_STACK_OFFSET ]; + xRegisterDump.ulR7 = pulStackPointerOnFunctionEntry[ portexR7_STACK_OFFSET ]; + xRegisterDump.ulR8 = pulStackPointerOnFunctionEntry[ portexR8_STACK_OFFSET ]; + xRegisterDump.ulR9 = pulStackPointerOnFunctionEntry[ portexR9_STACK_OFFSET ]; + xRegisterDump.ulR10 = pulStackPointerOnFunctionEntry[ portexR10_STACK_OFFSET ]; + xRegisterDump.ulR11 = pulStackPointerOnFunctionEntry[ portexR11_STACK_OFFSET ]; + xRegisterDump.ulR12 = pulStackPointerOnFunctionEntry[ portexR12_STACK_OFFSET ]; + xRegisterDump.ulR15_return_address_from_subroutine = pulStackPointerOnFunctionEntry[ portexR15_STACK_OFFSET ]; + xRegisterDump.ulR18 = pulStackPointerOnFunctionEntry[ portexR18_STACK_OFFSET ]; + xRegisterDump.ulR19 = pulStackPointerOnFunctionEntry[ portexR19_STACK_OFFSET ]; + xRegisterDump.ulMSR = pulStackPointerOnFunctionEntry[ portexMSR_STACK_OFFSET ]; + + /* Obtain the value of all other registers. */ + xRegisterDump.ulR2_small_data_area = mfgpr( R2 ); + xRegisterDump.ulR13_read_write_small_data_area = mfgpr( R13 ); + xRegisterDump.ulR14_return_address_from_interrupt = mfgpr( R14 ); + xRegisterDump.ulR16_return_address_from_trap = mfgpr( R16 ); + xRegisterDump.ulR17_return_address_from_exceptions = mfgpr( R17 ); + xRegisterDump.ulR20 = mfgpr( R20 ); + xRegisterDump.ulR21 = mfgpr( R21 ); + xRegisterDump.ulR22 = mfgpr( R22 ); + xRegisterDump.ulR23 = mfgpr( R23 ); + xRegisterDump.ulR24 = mfgpr( R24 ); + xRegisterDump.ulR25 = mfgpr( R25 ); + xRegisterDump.ulR26 = mfgpr( R26 ); + xRegisterDump.ulR27 = mfgpr( R27 ); + xRegisterDump.ulR28 = mfgpr( R28 ); + xRegisterDump.ulR29 = mfgpr( R29 ); + xRegisterDump.ulR30 = mfgpr( R30 ); + xRegisterDump.ulR31 = mfgpr( R31 ); + xRegisterDump.ulR1_SP = ( ( uint32_t ) pulStackPointerOnFunctionEntry ) + portexASM_HANDLER_STACK_FRAME_SIZE; + xRegisterDump.ulEAR = mfear(); + xRegisterDump.ulESR = mfesr(); + xRegisterDump.ulEDR = mfedr(); + + /* Move the saved program counter back to the instruction that was executed + * when the exception occurred. This is only valid for certain types of + * exception. */ + xRegisterDump.ulPC = xRegisterDump.ulR17_return_address_from_exceptions - portexINSTRUCTION_SIZE; + + #if ( XPAR_MICROBLAZE_USE_FPU != 0 ) + { + xRegisterDump.ulFSR = mffsr(); + } + #else + { + xRegisterDump.ulFSR = 0UL; + } + #endif + + /* Also fill in a string that describes what type of exception this is. + * The string uses the same ID names as defined in the MicroBlaze standard + * library exception header files. */ + switch( ( uint32_t ) pvExceptionID ) + { + case XEXC_ID_FSL: + xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FSL"; + break; + + case XEXC_ID_UNALIGNED_ACCESS: + xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_UNALIGNED_ACCESS"; + break; + + case XEXC_ID_ILLEGAL_OPCODE: + xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_ILLEGAL_OPCODE"; + break; + + case XEXC_ID_M_AXI_I_EXCEPTION: + xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_I_EXCEPTION or XEXC_ID_IPLB_EXCEPTION"; + break; + + case XEXC_ID_M_AXI_D_EXCEPTION: + xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_D_EXCEPTION or XEXC_ID_DPLB_EXCEPTION"; + break; + + case XEXC_ID_DIV_BY_ZERO: + xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_DIV_BY_ZERO"; + break; + + case XEXC_ID_STACK_VIOLATION: + xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_STACK_VIOLATION or XEXC_ID_MMU"; + break; + + #if ( XPAR_MICROBLAZE_USE_FPU != 0 ) + case XEXC_ID_FPU: + xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FPU see ulFSR value"; + break; + #endif /* XPAR_MICROBLAZE_USE_FPU */ + } + + /* vApplicationExceptionRegisterDump() is a callback function that the + * application can optionally define to receive the populated xPortRegisterDump + * structure. If the application chooses not to define a version of + * vApplicationExceptionRegisterDump() then the weekly defined default + * implementation within this file will be called instead. */ + vApplicationExceptionRegisterDump( &xRegisterDump ); + + /* Must not attempt to leave this function! */ + for( ; ; ) + { + portNOP(); + } + } +/*-----------------------------------------------------------*/ + + void vPortExceptionsInstallHandlers( void ) + { + static uint32_t ulHandlersAlreadyInstalled = pdFALSE; + + if( ulHandlersAlreadyInstalled == pdFALSE ) + { + ulHandlersAlreadyInstalled = pdTRUE; + + #if XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS == 1 + microblaze_register_exception_handler( XEXC_ID_UNALIGNED_ACCESS, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_UNALIGNED_ACCESS ); + #endif /* XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS*/ + + #if XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_ILLEGAL_OPCODE, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_ILLEGAL_OPCODE ); + #endif /* XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION */ + + #if XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_M_AXI_I_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_I_EXCEPTION ); + #endif /* XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION */ + + #if XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_M_AXI_D_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_D_EXCEPTION ); + #endif /* XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION */ + + #if XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_IPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_IPLB_EXCEPTION ); + #endif /* XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION */ + + #if XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_DPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DPLB_EXCEPTION ); + #endif /* XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION */ + + #if XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_DIV_BY_ZERO, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DIV_BY_ZERO ); + #endif /* XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION */ + + #if XPAR_MICROBLAZE_FPU_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_FPU, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FPU ); + #endif /* XPAR_MICROBLAZE_FPU_EXCEPTION */ + + #if XPAR_MICROBLAZE_FSL_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_FSL, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FSL ); + #endif /* XPAR_MICROBLAZE_FSL_EXCEPTION */ + + microblaze_enable_exceptions(); + } + } + +/* Exclude the entire file if the MicroBlaze is not configured to handle + * exceptions, or the application defined configuration item + * configINSTALL_EXCEPTION_HANDLERS is not set to 1. */ +#endif /* ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */ diff --git a/portable/GCC/MicroBlazeV8/portasm.S b/portable/GCC/MicroBlazeV8/portasm.S new file mode 100644 index 000000000..36829767d --- /dev/null +++ b/portable/GCC/MicroBlazeV8/portasm.S @@ -0,0 +1,326 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" + +/* Xilinx library includes. */ +#include "microblaze_exceptions_g.h" +#include "xparameters.h" + +/* The context is oversized to allow functions called from the ISR to write +back into the caller stack. */ +#if( XPAR_MICROBLAZE_USE_FPU != 0 ) + #define portCONTEXT_SIZE 136 + #define portMINUS_CONTEXT_SIZE -136 +#else + #define portCONTEXT_SIZE 132 + #define portMINUS_CONTEXT_SIZE -132 +#endif + +/* Offsets from the stack pointer at which saved registers are placed. */ +#define portR31_OFFSET 4 +#define portR30_OFFSET 8 +#define portR29_OFFSET 12 +#define portR28_OFFSET 16 +#define portR27_OFFSET 20 +#define portR26_OFFSET 24 +#define portR25_OFFSET 28 +#define portR24_OFFSET 32 +#define portR23_OFFSET 36 +#define portR22_OFFSET 40 +#define portR21_OFFSET 44 +#define portR20_OFFSET 48 +#define portR19_OFFSET 52 +#define portR18_OFFSET 56 +#define portR17_OFFSET 60 +#define portR16_OFFSET 64 +#define portR15_OFFSET 68 +#define portR14_OFFSET 72 +#define portR13_OFFSET 76 +#define portR12_OFFSET 80 +#define portR11_OFFSET 84 +#define portR10_OFFSET 88 +#define portR9_OFFSET 92 +#define portR8_OFFSET 96 +#define portR7_OFFSET 100 +#define portR6_OFFSET 104 +#define portR5_OFFSET 108 +#define portR4_OFFSET 112 +#define portR3_OFFSET 116 +#define portR2_OFFSET 120 +#define portCRITICAL_NESTING_OFFSET 124 +#define portMSR_OFFSET 128 +#define portFSR_OFFSET 132 + + .extern pxCurrentTCB + .extern XIntc_DeviceInterruptHandler + .extern vTaskSwitchContext + .extern uxCriticalNesting + .extern pulISRStack + .extern ulTaskSwitchRequested + .extern vPortExceptionHandler + .extern pulStackPointerOnFunctionEntry + + .global _interrupt_handler + .global VPortYieldASM + .global vPortStartFirstTask + .global vPortExceptionHandlerEntry + + +.macro portSAVE_CONTEXT + + /* Make room for the context on the stack. */ + addik r1, r1, portMINUS_CONTEXT_SIZE + + /* Stack general registers. */ + swi r31, r1, portR31_OFFSET + swi r30, r1, portR30_OFFSET + swi r29, r1, portR29_OFFSET + swi r28, r1, portR28_OFFSET + swi r27, r1, portR27_OFFSET + swi r26, r1, portR26_OFFSET + swi r25, r1, portR25_OFFSET + swi r24, r1, portR24_OFFSET + swi r23, r1, portR23_OFFSET + swi r22, r1, portR22_OFFSET + swi r21, r1, portR21_OFFSET + swi r20, r1, portR20_OFFSET + swi r19, r1, portR19_OFFSET + swi r18, r1, portR18_OFFSET + swi r17, r1, portR17_OFFSET + swi r16, r1, portR16_OFFSET + swi r15, r1, portR15_OFFSET + /* R14 is saved later as it needs adjustment if a yield is performed. */ + swi r13, r1, portR13_OFFSET + swi r12, r1, portR12_OFFSET + swi r11, r1, portR11_OFFSET + swi r10, r1, portR10_OFFSET + swi r9, r1, portR9_OFFSET + swi r8, r1, portR8_OFFSET + swi r7, r1, portR7_OFFSET + swi r6, r1, portR6_OFFSET + swi r5, r1, portR5_OFFSET + swi r4, r1, portR4_OFFSET + swi r3, r1, portR3_OFFSET + swi r2, r1, portR2_OFFSET + + /* Stack the critical section nesting value. */ + lwi r18, r0, uxCriticalNesting + swi r18, r1, portCRITICAL_NESTING_OFFSET + + /* Stack MSR. */ + mfs r18, rmsr + swi r18, r1, portMSR_OFFSET + + #if( XPAR_MICROBLAZE_USE_FPU != 0 ) + /* Stack FSR. */ + mfs r18, rfsr + swi r18, r1, portFSR_OFFSET + #endif + + /* Save the top of stack value to the TCB. */ + lwi r3, r0, pxCurrentTCB + sw r1, r0, r3 + + .endm + +.macro portRESTORE_CONTEXT + + /* Load the top of stack value from the TCB. */ + lwi r18, r0, pxCurrentTCB + lw r1, r0, r18 + + /* Restore the general registers. */ + lwi r31, r1, portR31_OFFSET + lwi r30, r1, portR30_OFFSET + lwi r29, r1, portR29_OFFSET + lwi r28, r1, portR28_OFFSET + lwi r27, r1, portR27_OFFSET + lwi r26, r1, portR26_OFFSET + lwi r25, r1, portR25_OFFSET + lwi r24, r1, portR24_OFFSET + lwi r23, r1, portR23_OFFSET + lwi r22, r1, portR22_OFFSET + lwi r21, r1, portR21_OFFSET + lwi r20, r1, portR20_OFFSET + lwi r19, r1, portR19_OFFSET + lwi r17, r1, portR17_OFFSET + lwi r16, r1, portR16_OFFSET + lwi r15, r1, portR15_OFFSET + lwi r14, r1, portR14_OFFSET + lwi r13, r1, portR13_OFFSET + lwi r12, r1, portR12_OFFSET + lwi r11, r1, portR11_OFFSET + lwi r10, r1, portR10_OFFSET + lwi r9, r1, portR9_OFFSET + lwi r8, r1, portR8_OFFSET + lwi r7, r1, portR7_OFFSET + lwi r6, r1, portR6_OFFSET + lwi r5, r1, portR5_OFFSET + lwi r4, r1, portR4_OFFSET + lwi r3, r1, portR3_OFFSET + lwi r2, r1, portR2_OFFSET + + /* Reload the rmsr from the stack. */ + lwi r18, r1, portMSR_OFFSET + mts rmsr, r18 + + #if( XPAR_MICROBLAZE_USE_FPU != 0 ) + /* Reload the FSR from the stack. */ + lwi r18, r1, portFSR_OFFSET + mts rfsr, r18 + #endif + + /* Load the critical nesting value. */ + lwi r18, r1, portCRITICAL_NESTING_OFFSET + swi r18, r0, uxCriticalNesting + + /* Test the critical nesting value. If it is non zero then the task last + exited the running state using a yield. If it is zero, then the task + last exited the running state through an interrupt. */ + xori r18, r18, 0 + bnei r18, exit_from_yield + + /* r18 was being used as a temporary. Now restore its true value from the + stack. */ + lwi r18, r1, portR18_OFFSET + + /* Remove the stack frame. */ + addik r1, r1, portCONTEXT_SIZE + + /* Return using rtid so interrupts are re-enabled as this function is + exited. */ + rtid r14, 0 + or r0, r0, r0 + + .endm + +/* This function is used to exit portRESTORE_CONTEXT() if the task being +returned to last left the Running state by calling taskYIELD() (rather than +being preempted by an interrupt). */ + .text + .align 4 +exit_from_yield: + + /* r18 was being used as a temporary. Now restore its true value from the + stack. */ + lwi r18, r1, portR18_OFFSET + + /* Remove the stack frame. */ + addik r1, r1, portCONTEXT_SIZE + + /* Return to the task. */ + rtsd r14, 0 + or r0, r0, r0 + + + .text + .align 4 +_interrupt_handler: + + portSAVE_CONTEXT + + /* Stack the return address. */ + swi r14, r1, portR14_OFFSET + + /* Switch to the ISR stack. */ + lwi r1, r0, pulISRStack + + /* The parameter to the interrupt handler. */ + ori r5, r0, configINTERRUPT_CONTROLLER_TO_USE + + /* Execute any pending interrupts. */ + bralid r15, XIntc_DeviceInterruptHandler + or r0, r0, r0 + + /* See if a new task should be selected to execute. */ + lwi r18, r0, ulTaskSwitchRequested + or r18, r18, r0 + + /* If ulTaskSwitchRequested is already zero, then jump straight to + restoring the task that is already in the Running state. */ + beqi r18, task_switch_not_requested + + /* Set ulTaskSwitchRequested back to zero as a task switch is about to be + performed. */ + swi r0, r0, ulTaskSwitchRequested + + /* ulTaskSwitchRequested was not 0 when tested. Select the next task to + execute. */ + bralid r15, vTaskSwitchContext + or r0, r0, r0 + +task_switch_not_requested: + + /* Restore the context of the next task scheduled to execute. */ + portRESTORE_CONTEXT + + + .text + .align 4 +VPortYieldASM: + + portSAVE_CONTEXT + + /* Modify the return address so a return is done to the instruction after + the call to VPortYieldASM. */ + addi r14, r14, 8 + swi r14, r1, portR14_OFFSET + + /* Switch to use the ISR stack. */ + lwi r1, r0, pulISRStack + + /* Select the next task to execute. */ + bralid r15, vTaskSwitchContext + or r0, r0, r0 + + /* Restore the context of the next task scheduled to execute. */ + portRESTORE_CONTEXT + + .text + .align 4 +vPortStartFirstTask: + + portRESTORE_CONTEXT + + + +#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) + + .text + .align 4 +vPortExceptionHandlerEntry: + + /* Take a copy of the stack pointer before vPortExecptionHandler is called, + storing its value prior to the function stack frame being created. */ + swi r1, r0, pulStackPointerOnFunctionEntry + bralid r15, vPortExceptionHandler + or r0, r0, r0 + +#endif /* ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */ diff --git a/portable/GCC/MicroBlazeV8/portmacro.h b/portable/GCC/MicroBlazeV8/portmacro.h new file mode 100644 index 000000000..d23214ea4 --- /dev/null +++ b/portable/GCC/MicroBlazeV8/portmacro.h @@ -0,0 +1,382 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/* BSP includes. */ +#include +#include + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Interrupt control macros and functions. */ +void microblaze_disable_interrupts( void ); +void microblaze_enable_interrupts( void ); +#define portDISABLE_INTERRUPTS() microblaze_disable_interrupts() +#define portENABLE_INTERRUPTS() microblaze_enable_interrupts() +/*-----------------------------------------------------------*/ + +/* Critical section macros. */ +void vPortEnterCritical( void ); +void vPortExitCritical( void ); +#define portENTER_CRITICAL() \ + { \ + extern volatile UBaseType_t uxCriticalNesting; \ + microblaze_disable_interrupts(); \ + uxCriticalNesting++; \ + } + +#define portEXIT_CRITICAL() \ + { \ + extern volatile UBaseType_t uxCriticalNesting; \ + /* Interrupts are disabled, so we can */ \ + /* access the variable directly. */ \ + uxCriticalNesting--; \ + if( uxCriticalNesting == 0 ) \ + { \ + /* The nesting has unwound and we \ + * can enable interrupts again. */ \ + portENABLE_INTERRUPTS(); \ + } \ + } + +/*-----------------------------------------------------------*/ + +/* The yield macro maps directly to the vPortYield() function. */ +void vPortYield( void ); +#define portYIELD() vPortYield() + +/* portYIELD_FROM_ISR() does not directly call vTaskSwitchContext(), but instead + * sets a flag to say that a yield has been requested. The interrupt exit code + * then checks this flag, and calls vTaskSwitchContext() before restoring a task + * context, if the flag is not false. This is done to prevent multiple calls to + * vTaskSwitchContext() being made from a single interrupt, as a single interrupt + * can result in multiple peripherals being serviced. */ +extern volatile uint32_t ulTaskSwitchRequested; +#define portYIELD_FROM_ISR( x ) \ + do { if( ( x ) != pdFALSE ) ulTaskSwitchRequested = 1; } \ + while( 0 ) + +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/* Generic helper function. */ + __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint8_t ucReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) ); + + return ucReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 4 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() asm volatile ( "NOP" ) +#define portMEMORY_BARRIER() asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +/* The following structure is used by the FreeRTOS exception handler. It is + * filled with the MicroBlaze context as it was at the time the exception occurred. + * This is done as an aid to debugging exception occurrences. */ +typedef struct PORT_REGISTER_DUMP +{ + /* The following structure members hold the values of the MicroBlaze + * registers at the time the exception was raised. */ + uint32_t ulR1_SP; + uint32_t ulR2_small_data_area; + uint32_t ulR3; + uint32_t ulR4; + uint32_t ulR5; + uint32_t ulR6; + uint32_t ulR7; + uint32_t ulR8; + uint32_t ulR9; + uint32_t ulR10; + uint32_t ulR11; + uint32_t ulR12; + uint32_t ulR13_read_write_small_data_area; + uint32_t ulR14_return_address_from_interrupt; + uint32_t ulR15_return_address_from_subroutine; + uint32_t ulR16_return_address_from_trap; + uint32_t ulR17_return_address_from_exceptions; /* The exception entry code will copy the BTR into R17 if the exception occurred in the delay slot of a branch instruction. */ + uint32_t ulR18; + uint32_t ulR19; + uint32_t ulR20; + uint32_t ulR21; + uint32_t ulR22; + uint32_t ulR23; + uint32_t ulR24; + uint32_t ulR25; + uint32_t ulR26; + uint32_t ulR27; + uint32_t ulR28; + uint32_t ulR29; + uint32_t ulR30; + uint32_t ulR31; + uint32_t ulPC; + uint32_t ulESR; + uint32_t ulMSR; + uint32_t ulEAR; + uint32_t ulFSR; + uint32_t ulEDR; + + /* A human readable description of the exception cause. The strings used + * are the same as the #define constant names found in the + * microblaze_exceptions_i.h header file */ + int8_t * pcExceptionCause; + + /* The human readable name of the task that was running at the time the + * exception occurred. This is the name that was given to the task when the + * task was created using the FreeRTOS xTaskCreate() API function. */ + char * pcCurrentTaskName; + + /* The handle of the task that was running a the time the exception + * occurred. */ + void * xCurrentTaskHandle; +} xPortRegisterDump; + + +/* + * Installs pxHandler as the interrupt handler for the peripheral specified by + * the ucInterruptID parameter. + * + * ucInterruptID: + * + * The ID of the peripheral that will have pxHandler assigned as its interrupt + * handler. Peripheral IDs are defined in the xparameters.h header file, which + * is itself part of the BSP project. For example, in the official demo + * application for this port, xparameters.h defines the following IDs for the + * four possible interrupt sources: + * + * XPAR_INTC_0_UARTLITE_1_VEC_ID - for the UARTlite peripheral. + * XPAR_INTC_0_TMRCTR_0_VEC_ID - for the AXI Timer 0 peripheral. + * XPAR_INTC_0_EMACLITE_0_VEC_ID - for the Ethernet lite peripheral. + * XPAR_INTC_0_GPIO_1_VEC_ID - for the button inputs. + * + * + * pxHandler: + * + * A pointer to the interrupt handler function itself. This must be a void + * function that takes a (void *) parameter. + * + * + * pvCallBackRef: + * + * The parameter passed into the handler function. In many cases this will not + * be used and can be NULL. Some times it is used to pass in a reference to + * the peripheral instance variable, so it can be accessed from inside the + * handler function. + * + * + * pdPASS is returned if the function executes successfully. Any other value + * being returned indicates that the function did not execute correctly. + */ +BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, + XInterruptHandler pxHandler, + void * pvCallBackRef ); + + +/* + * Enables the interrupt, within the interrupt controller, for the peripheral + * specified by the ucInterruptID parameter. + * + * ucInterruptID: + * + * The ID of the peripheral that will have its interrupt enabled in the + * interrupt controller. Peripheral IDs are defined in the xparameters.h header + * file, which is itself part of the BSP project. For example, in the official + * demo application for this port, xparameters.h defines the following IDs for + * the four possible interrupt sources: + * + * XPAR_INTC_0_UARTLITE_1_VEC_ID - for the UARTlite peripheral. + * XPAR_INTC_0_TMRCTR_0_VEC_ID - for the AXI Timer 0 peripheral. + * XPAR_INTC_0_EMACLITE_0_VEC_ID - for the Ethernet lite peripheral. + * XPAR_INTC_0_GPIO_1_VEC_ID - for the button inputs. + * + */ +void vPortEnableInterrupt( uint8_t ucInterruptID ); + +/* + * Disables the interrupt, within the interrupt controller, for the peripheral + * specified by the ucInterruptID parameter. + * + * ucInterruptID: + * + * The ID of the peripheral that will have its interrupt disabled in the + * interrupt controller. Peripheral IDs are defined in the xparameters.h header + * file, which is itself part of the BSP project. For example, in the official + * demo application for this port, xparameters.h defines the following IDs for + * the four possible interrupt sources: + * + * XPAR_INTC_0_UARTLITE_1_VEC_ID - for the UARTlite peripheral. + * XPAR_INTC_0_TMRCTR_0_VEC_ID - for the AXI Timer 0 peripheral. + * XPAR_INTC_0_EMACLITE_0_VEC_ID - for the Ethernet lite peripheral. + * XPAR_INTC_0_GPIO_1_VEC_ID - for the button inputs. + * + */ +void vPortDisableInterrupt( uint8_t ucInterruptID ); + +/* + * This is an application defined callback function used to install the tick + * interrupt handler. It is provided as an application callback because the + * kernel will run on lots of different MicroBlaze and FPGA configurations - not + * all of which will have the same timer peripherals defined or available. This + * example uses the AXI Timer 0. If that is available on your hardware platform + * then this example callback implementation should not require modification. + * The name of the interrupt handler that should be installed is vPortTickISR(), + * which the function below declares as an extern. + */ +void vApplicationSetupTimerInterrupt( void ); + +/* + * This is an application defined callback function used to clear whichever + * interrupt was installed by the the vApplicationSetupTimerInterrupt() callback + * function - in this case the interrupt generated by the AXI timer. It is + * provided as an application callback because the kernel will run on lots of + * different MicroBlaze and FPGA configurations - not all of which will have the + * same timer peripherals defined or available. This example uses the AXI Timer 0. + * If that is available on your hardware platform then this example callback + * implementation should not require modification provided the example definition + * of vApplicationSetupTimerInterrupt() is also not modified. + */ +void vApplicationClearTimerInterrupt( void ); + +/* + * vPortExceptionsInstallHandlers() is only available when the MicroBlaze + * is configured to include exception functionality, and + * configINSTALL_EXCEPTION_HANDLERS is set to 1 in FreeRTOSConfig.h. + * + * vPortExceptionsInstallHandlers() installs the FreeRTOS exception handler + * for every possible exception cause. + * + * vPortExceptionsInstallHandlers() can be called explicitly from application + * code. After that is done, the default FreeRTOS exception handler that will + * have been installed can be replaced for any specific exception cause by using + * the standard Xilinx library function microblaze_register_exception_handler(). + * + * If vPortExceptionsInstallHandlers() is not called explicitly by the + * application, it will be called automatically by the kernel the first time + * xPortInstallInterruptHandler() is called. At that time, any exception + * handlers that may have already been installed will be replaced. + * + * See the description of vApplicationExceptionRegisterDump() for information + * on the processing performed by the FreeRTOS exception handler. + */ +void vPortExceptionsInstallHandlers( void ); + +/* + * The FreeRTOS exception handler fills an xPortRegisterDump structure (defined + * in portmacro.h) with the MicroBlaze context, as it was at the time the + * exception occurred. The exception handler then calls + * vApplicationExceptionRegisterDump(), passing in the completed + * xPortRegisterDump structure as its parameter. + * + * The FreeRTOS kernel provides its own implementation of + * vApplicationExceptionRegisterDump(), but the kernel provided implementation + * is declared as being 'weak'. The weak definition allows the application + * writer to provide their own implementation, should they wish to use the + * register dump information. For example, an implementation could be provided + * that wrote the register dump data to a display, or a UART port. + */ +void vApplicationExceptionRegisterDump( xPortRegisterDump * xRegisterDump ); + + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/MicroBlazeV9/port.c b/portable/GCC/MicroBlazeV9/port.c new file mode 100644 index 000000000..7a94ece00 --- /dev/null +++ b/portable/GCC/MicroBlazeV9/port.c @@ -0,0 +1,545 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the MicroBlaze port. +*----------------------------------------------------------*/ + + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Standard includes. */ +#include + +/* Hardware includes. */ +#include +#include +#include +#include + +/* Tasks are started with a critical section nesting of 0 - however, prior to + * the scheduler being commenced interrupts should not be enabled, so the critical + * nesting variable is initialised to a non-zero value. */ +#define portINITIAL_NESTING_VALUE ( 0xff ) + +/* The bit within the MSR register that enabled/disables interrupts and + * exceptions respectively. */ +#define portMSR_IE ( 0x02U ) +#define portMSR_EE ( 0x100U ) + +/* If the floating point unit is included in the MicroBlaze build, then the + * FSR register is saved as part of the task context. portINITIAL_FSR is the value + * given to the FSR register when the initial context is set up for a task being + * created. */ +#define portINITIAL_FSR ( 0U ) +/* + * Global counter used for calculation of run time statistics of tasks. + * Defined only when the relevant option is turned on + */ +#if (configGENERATE_RUN_TIME_STATS==1) + volatile uint32_t ulHighFrequencyTimerTicks; +#endif + +/*-----------------------------------------------------------*/ + +/* + * Initialise the interrupt controller instance. + */ +static int32_t prvInitialiseInterruptController( void ); + +/* Ensure the interrupt controller instance variable is initialised before it is + * used, and that the initialisation only happens once. + */ +static int32_t prvEnsureInterruptControllerIsInitialised( void ); + +/*-----------------------------------------------------------*/ + +/* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task + * maintains its own count, so this variable is saved as part of the task + * context. */ +volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE; + +/* This port uses a separate stack for interrupts. This prevents the stack of + * every task needing to be large enough to hold an entire interrupt stack on top + * of the task stack. */ +uint32_t * pulISRStack; + +/* If an interrupt requests a context switch, then ulTaskSwitchRequested will + * get set to 1. ulTaskSwitchRequested is inspected just before the main interrupt + * handler exits. If, at that time, ulTaskSwitchRequested is set to 1, the kernel + * will call vTaskSwitchContext() to ensure the task that runs immediately after + * the interrupt exists is the highest priority task that is able to run. This is + * an unusual mechanism, but is used for this port because a single interrupt can + * cause the servicing of multiple peripherals - and it is inefficient to call + * vTaskSwitchContext() multiple times as each peripheral is serviced. */ +volatile uint32_t ulTaskSwitchRequested = 0UL; + +/* The instance of the interrupt controller used by this port. This is required + * by the Xilinx library API functions. */ +static XIntc xInterruptControllerInstance; + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been made. + * + * See the portable.h header file. + */ +#if ( portHAS_STACK_OVERFLOW_CHECKING == 1 ) + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +#else + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +#endif +{ + extern void *_SDA2_BASE_; + extern void *_SDA_BASE_; + const UINTPTR ulR2 = ( UINTPTR ) &_SDA2_BASE_; + const UINTPTR ulR13 = ( UINTPTR ) &_SDA_BASE_; + + extern void _start1( void ); + + /* Place a few bytes of known values on the bottom of the stack. + * This is essential for the Microblaze port and these lines must + * not be omitted. */ + *pxTopOfStack = ( StackType_t ) 0x00000000; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x00000000; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x00000000; + pxTopOfStack--; + + #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 ) + /* Store the stack limits. */ + *pxTopOfStack = ( StackType_t ) ( pxTopOfStack + 3 ); + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; + pxTopOfStack--; + #endif + + #if ( XPAR_MICROBLAZE_USE_FPU != 0 ) + /* The FSR value placed in the initial task context is just 0. */ + *pxTopOfStack = portINITIAL_FSR; + pxTopOfStack--; + #endif + + /* The MSR value placed in the initial task context should have interrupts + * disabled. Each task will enable interrupts automatically when it enters + * the running state for the first time. */ + *pxTopOfStack = mfmsr() & ~portMSR_IE; + + #if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) + { + /* Ensure exceptions are enabled for the task. */ + *pxTopOfStack |= portMSR_EE; + } + #endif + + pxTopOfStack--; + + /* First stack an initial value for the critical section nesting. This + * is initialised to zero. */ + *pxTopOfStack = ( StackType_t ) 0x00; + + /* R0 is always zero. */ + /* R1 is the SP. */ + + /* Place an initial value for all the general purpose registers. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) ulR2; /* R2 - read only small data area. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03; /* R3 - return values and temporaries. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04; /* R4 - return values and temporaries. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R5 contains the function call parameters. */ + + #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06; /* R6 - other parameters and temporaries. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07; /* R7 - other parameters and temporaries. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) NULL; /* R8 - other parameters and temporaries. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09; /* R9 - other parameters and temporaries. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x0a; /* R10 - other parameters and temporaries. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x0b; /* R11 - temporaries. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x0c; /* R12 - temporaries. */ + pxTopOfStack--; + #else /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */ + pxTopOfStack -= 8; + #endif /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */ + + *pxTopOfStack = ( StackType_t ) ulR13; /* R13 - read/write small data area. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* R14 - return address for interrupt. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) _start1; /* R15 - return address for subroutine. */ + + #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10; /* R16 - return address for trap (debugger). */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11; /* R17 - return address for exceptions, if configured. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12; /* R18 - reserved for assembler and compiler temporaries. */ + pxTopOfStack--; + #else + pxTopOfStack -= 4; + #endif + + *pxTopOfStack = ( StackType_t ) 0x00; /* R19 - must be saved across function calls. Callee-save. Seems to be interpreted as the frame pointer. */ + + #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x14; /* R20 - reserved for storing a pointer to the Global Offset Table (GOT) in Position Independent Code (PIC). Non-volatile in non-PIC code. Must be saved across function calls. Callee-save. Not used by FreeRTOS. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x15; /* R21 - must be saved across function calls. Callee-save. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x16; /* R22 - must be saved across function calls. Callee-save. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x17; /* R23 - must be saved across function calls. Callee-save. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x18; /* R24 - must be saved across function calls. Callee-save. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x19; /* R25 - must be saved across function calls. Callee-save. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x1a; /* R26 - must be saved across function calls. Callee-save. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x1b; /* R27 - must be saved across function calls. Callee-save. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x1c; /* R28 - must be saved across function calls. Callee-save. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x1d; /* R29 - must be saved across function calls. Callee-save. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x1e; /* R30 - must be saved across function calls. Callee-save. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x1f; /* R31 - must be saved across function calls. Callee-save. */ + pxTopOfStack--; + #else /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */ + pxTopOfStack -= 13; + #endif /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */ + + /* Return a pointer to the top of the stack that has been generated so this + * can be stored in the task control block for the task. */ + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + extern void ( vPortStartFirstTask )( void ); + extern UINTPTR _stack[]; + + /* Setup the hardware to generate the tick. Interrupts are disabled when + * this function is called. + * + * This port uses an application defined callback function to install the tick + * interrupt handler because the kernel will run on lots of different + * MicroBlaze and FPGA configurations - not all of which will have the same + * timer peripherals defined or available. An example definition of + * vApplicationSetupTimerInterrupt() is provided in the official demo + * application that accompanies this port. */ + vApplicationSetupTimerInterrupt(); + + /* Reuse the stack from main() as the stack for the interrupts/exceptions. */ + pulISRStack = ( UINTPTR * ) _stack; + + /* Ensure there is enough space for the functions called from the interrupt + * service routines to write back into the stack frame of the caller. */ + pulISRStack -= 2; + + /* Restore the context of the first task that is going to run. From here + * on, the created tasks will be executing. */ + vPortStartFirstTask(); + + /* Should not get here as the tasks are now running! */ + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +/* + * Manual context switch called by portYIELD or taskYIELD. + */ +void vPortYield( void ) +{ + extern void VPortYieldASM( void ); + + /* Perform the context switch in a critical section to assure it is + * not interrupted by the tick ISR. It is not a problem to do this as + * each task maintains its own interrupt status. */ + portENTER_CRITICAL(); + { + /* Jump directly to the yield function to ensure there is no + * compiler generated prologue code. */ + #ifdef __arch64__ + asm volatile ( "brealid r14, VPortYieldASM \n\t" \ + "or r0, r0, r0 \n\t" ); + #else + asm volatile ( "bralid r14, VPortYieldASM \n\t" \ + "or r0, r0, r0 \n\t" ); + #endif + } + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +void vPortEnableInterrupt( uint8_t ucInterruptID ) +{ + int32_t lReturn; + + /* An API function is provided to enable an interrupt in the interrupt + * controller because the interrupt controller instance variable is private + * to this file. */ + lReturn = prvEnsureInterruptControllerIsInitialised(); + + if( lReturn == pdPASS ) + { + /* Critical section protects read/modify/writer operation inside + * XIntc_Enable(). */ + portENTER_CRITICAL(); + { + XIntc_Enable( &xInterruptControllerInstance, ucInterruptID ); + } + portEXIT_CRITICAL(); + } + + configASSERT( lReturn == pdPASS ); +} +/*-----------------------------------------------------------*/ + +void vPortDisableInterrupt( uint8_t ucInterruptID ) +{ + int32_t lReturn; + + /* An API function is provided to disable an interrupt in the interrupt + * controller because the interrupt controller instance variable is private + * to this file. */ + lReturn = prvEnsureInterruptControllerIsInitialised(); + + if( lReturn == pdPASS ) + { + XIntc_Disable( &xInterruptControllerInstance, ucInterruptID ); + } + + configASSERT( lReturn == pdPASS ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, + XInterruptHandler pxHandler, + void * pvCallBackRef ) +{ + int32_t lReturn; + + /* An API function is provided to install an interrupt handler because the + * interrupt controller instance variable is private to this file. */ + + lReturn = prvEnsureInterruptControllerIsInitialised(); + + if( lReturn == pdPASS ) + { + lReturn = XIntc_Connect( &xInterruptControllerInstance, ucInterruptID, pxHandler, pvCallBackRef ); + } + + if( lReturn == XST_SUCCESS ) + { + lReturn = pdPASS; + } + + configASSERT( lReturn == pdPASS ); + + return lReturn; +} +/*-----------------------------------------------------------*/ + +void vPortRemoveInterruptHandler( uint8_t ucInterruptID ) +{ + int32_t lReturn; + + /* An API function is provided to remove an interrupt handler because the + * interrupt controller instance variable is private to this file. */ + + lReturn = prvEnsureInterruptControllerIsInitialised(); + + if( lReturn == pdPASS ) + { + XIntc_Disconnect( &xInterruptControllerInstance, ucInterruptID ); + } + + configASSERT( lReturn == pdPASS ); +} +/*-----------------------------------------------------------*/ + +static int32_t prvEnsureInterruptControllerIsInitialised( void ) +{ + static int32_t lInterruptControllerInitialised = pdFALSE; + int32_t lReturn; + + /* Ensure the interrupt controller instance variable is initialised before + * it is used, and that the initialisation only happens once. */ + if( lInterruptControllerInitialised != pdTRUE ) + { + lReturn = prvInitialiseInterruptController(); + + if( lReturn == pdPASS ) + { + lInterruptControllerInitialised = pdTRUE; + } + } + else + { + lReturn = pdPASS; + } + + return lReturn; +} +/*-----------------------------------------------------------*/ + +/* + * Handler for the timer interrupt. This is the handler that the application + * defined callback function vApplicationSetupTimerInterrupt() should install. + */ +void vPortTickISR( void * pvUnused ) +{ + extern void vApplicationClearTimerInterrupt( void ); + + /* Ensure the unused parameter does not generate a compiler warning. */ + ( void ) pvUnused; + + /* The Xilinx implementation of generating run time task stats uses the same timer used for generating + * FreeRTOS ticks. In case user decides to generate run time stats the tick handler is called more + * frequently (10 times faster). The timer ick handler uses logic to handle the same. It handles + * the FreeRTOS tick once per 10 interrupts. + * For handling generation of run time stats, it increments a pre-defined counter every time the + * interrupt handler executes. */ +#if (configGENERATE_RUN_TIME_STATS == 1) + ulHighFrequencyTimerTicks++; + if (!(ulHighFrequencyTimerTicks % 10)) +#endif + { + /* This port uses an application defined callback function to clear the tick + * interrupt because the kernel will run on lots of different MicroBlaze and + * FPGA configurations - not all of which will have the same timer peripherals + * defined or available. An example definition of + * vApplicationClearTimerInterrupt() is provided in the official demo + * application that accompanies this port. */ + vApplicationClearTimerInterrupt(); + + /* Increment the RTOS tick - this might cause a task to unblock. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Force vTaskSwitchContext() to be called as the interrupt exits. */ + ulTaskSwitchRequested = 1; + } + } +} +/*-----------------------------------------------------------*/ + +static int32_t prvInitialiseInterruptController( void ) +{ + int32_t lStatus; + + lStatus = XIntc_Initialize( &xInterruptControllerInstance, configINTERRUPT_CONTROLLER_TO_USE ); + + if( lStatus == XST_SUCCESS ) + { + /* Initialise the exception table. */ + Xil_ExceptionInit(); + + /* Service all pending interrupts each time the handler is entered. */ + XIntc_SetIntrSvcOption( xInterruptControllerInstance.BaseAddress, XIN_SVC_ALL_ISRS_OPTION ); + + /* Install exception handlers if the MicroBlaze is configured to handle + * exceptions, and the application defined constant + * configINSTALL_EXCEPTION_HANDLERS is set to 1. */ + #if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) + { + vPortExceptionsInstallHandlers(); + } + #endif /* MICROBLAZE_EXCEPTIONS_ENABLED */ + + /* Start the interrupt controller. Interrupts are enabled when the + * scheduler starts. */ + lStatus = XIntc_Start( &xInterruptControllerInstance, XIN_REAL_MODE ); + + if( lStatus == XST_SUCCESS ) + { + lStatus = pdPASS; + } + else + { + lStatus = pdFAIL; + } + } + + configASSERT( lStatus == pdPASS ); + + return lStatus; +} + +#if( configGENERATE_RUN_TIME_STATS == 1 ) +/* + * For Xilinx implementation this is a dummy function that does a redundant operation + * of zeroing out the global counter. + * It is called by FreeRTOS kernel. + */ +void xCONFIGURE_TIMER_FOR_RUN_TIME_STATS (void) +{ + ulHighFrequencyTimerTicks = 0; +} +/* + * For Xilinx implementation this function returns the global counter used for + * run time task stats calculation. + * It is called by FreeRTOS kernel task handling logic. + */ +uint32_t xGET_RUN_TIME_COUNTER_VALUE (void) +{ + return ulHighFrequencyTimerTicks; +} +#endif +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/MicroBlazeV9/port_exceptions.c b/portable/GCC/MicroBlazeV9/port_exceptions.c new file mode 100644 index 000000000..21dd28844 --- /dev/null +++ b/portable/GCC/MicroBlazeV9/port_exceptions.c @@ -0,0 +1,277 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Hardware includes. */ +#include +#include + +/* The Xilinx library defined exception entry point stacks a number of + * registers. These definitions are offsets from the stack pointer to the various + * stacked register values. */ +#define portexR3_STACK_OFFSET 4 +#define portexR4_STACK_OFFSET 5 +#define portexR5_STACK_OFFSET 6 +#define portexR6_STACK_OFFSET 7 +#define portexR7_STACK_OFFSET 8 +#define portexR8_STACK_OFFSET 9 +#define portexR9_STACK_OFFSET 10 +#define portexR10_STACK_OFFSET 11 +#define portexR11_STACK_OFFSET 12 +#define portexR12_STACK_OFFSET 13 +#define portexR15_STACK_OFFSET 16 +#define portexR18_STACK_OFFSET 19 +#define portexMSR_STACK_OFFSET 20 +#define portexR19_STACK_OFFSET -1 + +/* This is defined to equal the size, in bytes, of the stack frame generated by + * the Xilinx standard library exception entry point. It is required to determine + * the stack pointer value prior to the exception being entered. */ +#define portexASM_HANDLER_STACK_FRAME_SIZE 84UL + +/* The number of bytes a MicroBlaze instruction consumes. */ +#define portexINSTRUCTION_SIZE 4 + +/* Exclude this entire file if the MicroBlaze is not configured to handle + * exceptions, or the application defined configuration constant + * configINSTALL_EXCEPTION_HANDLERS is not set to 1. */ +#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) + +/* This variable is set in the exception entry code, before + * vPortExceptionHandler is called. */ + UINTPTR *pulStackPointerOnFunctionEntry = NULL; + +/* This is the structure that is filled with the MicroBlaze context as it + * existed immediately prior to the exception occurrence. A pointer to this + * structure is passed into the vApplicationExceptionRegisterDump() callback + * function, if one is defined. */ + static xPortRegisterDump xRegisterDump; + +/* This is the FreeRTOS exception handler that is installed for all exception + * types. It is called from vPortExceptionHandlerEntry() - which is itself defined + * in portasm.S. */ + void vPortExceptionHandler( void * pvExceptionID ); + extern void vPortExceptionHandlerEntry( void * pvExceptionID ); +/*-----------------------------------------------------------*/ + +/* vApplicationExceptionRegisterDump() is a callback function that the + * application can optionally define to receive a populated xPortRegisterDump + * structure. If the application chooses not to define a version of + * vApplicationExceptionRegisterDump() then this weekly defined default + * implementation will be called instead. */ + extern void vApplicationExceptionRegisterDump( xPortRegisterDump * xRegisterDump ) __attribute__( ( weak ) ); + void vApplicationExceptionRegisterDump( xPortRegisterDump * xRegisterDump ) + { + ( void ) xRegisterDump; + + for( ; ; ) + { + portNOP(); + } + } +/*-----------------------------------------------------------*/ + + void vPortExceptionHandler( void * pvExceptionID ) + { + extern void * pxCurrentTCB; + + /* Fill an xPortRegisterDump structure with the MicroBlaze context as it + * was immediately before the exception occurrence. */ + + /* First fill in the name and handle of the task that was in the Running + * state when the exception occurred. */ + xRegisterDump.xCurrentTaskHandle = pxCurrentTCB; + xRegisterDump.pcCurrentTaskName = pcTaskGetName( NULL ); + + configASSERT( pulStackPointerOnFunctionEntry ); + + /* Obtain the values of registers that were stacked prior to this function + * being called, and may have changed since they were stacked. */ + xRegisterDump.ulR3 = pulStackPointerOnFunctionEntry[ portexR3_STACK_OFFSET ]; + xRegisterDump.ulR4 = pulStackPointerOnFunctionEntry[ portexR4_STACK_OFFSET ]; + xRegisterDump.ulR5 = pulStackPointerOnFunctionEntry[ portexR5_STACK_OFFSET ]; + xRegisterDump.ulR6 = pulStackPointerOnFunctionEntry[ portexR6_STACK_OFFSET ]; + xRegisterDump.ulR7 = pulStackPointerOnFunctionEntry[ portexR7_STACK_OFFSET ]; + xRegisterDump.ulR8 = pulStackPointerOnFunctionEntry[ portexR8_STACK_OFFSET ]; + xRegisterDump.ulR9 = pulStackPointerOnFunctionEntry[ portexR9_STACK_OFFSET ]; + xRegisterDump.ulR10 = pulStackPointerOnFunctionEntry[ portexR10_STACK_OFFSET ]; + xRegisterDump.ulR11 = pulStackPointerOnFunctionEntry[ portexR11_STACK_OFFSET ]; + xRegisterDump.ulR12 = pulStackPointerOnFunctionEntry[ portexR12_STACK_OFFSET ]; + xRegisterDump.ulR15_return_address_from_subroutine = pulStackPointerOnFunctionEntry[ portexR15_STACK_OFFSET ]; + xRegisterDump.ulR18 = pulStackPointerOnFunctionEntry[ portexR18_STACK_OFFSET ]; + xRegisterDump.ulR19 = pulStackPointerOnFunctionEntry[ portexR19_STACK_OFFSET ]; + xRegisterDump.ulMSR = pulStackPointerOnFunctionEntry[ portexMSR_STACK_OFFSET ]; + + /* Obtain the value of all other registers. */ + xRegisterDump.ulR2_small_data_area = mfgpr( R2 ); + xRegisterDump.ulR13_read_write_small_data_area = mfgpr( R13 ); + xRegisterDump.ulR14_return_address_from_interrupt = mfgpr( R14 ); + xRegisterDump.ulR16_return_address_from_trap = mfgpr( R16 ); + xRegisterDump.ulR17_return_address_from_exceptions = mfgpr( R17 ); + xRegisterDump.ulR20 = mfgpr( R20 ); + xRegisterDump.ulR21 = mfgpr( R21 ); + xRegisterDump.ulR22 = mfgpr( R22 ); + xRegisterDump.ulR23 = mfgpr( R23 ); + xRegisterDump.ulR24 = mfgpr( R24 ); + xRegisterDump.ulR25 = mfgpr( R25 ); + xRegisterDump.ulR26 = mfgpr( R26 ); + xRegisterDump.ulR27 = mfgpr( R27 ); + xRegisterDump.ulR28 = mfgpr( R28 ); + xRegisterDump.ulR29 = mfgpr( R29 ); + xRegisterDump.ulR30 = mfgpr( R30 ); + xRegisterDump.ulR31 = mfgpr( R31 ); + xRegisterDump.ulR1_SP = ( ( UINTPTR ) pulStackPointerOnFunctionEntry ) + portexASM_HANDLER_STACK_FRAME_SIZE; + xRegisterDump.ulEAR = mfear(); + xRegisterDump.ulESR = mfesr(); + xRegisterDump.ulEDR = mfedr(); + + /* Move the saved program counter back to the instruction that was executed + * when the exception occurred. This is only valid for certain types of + * exception. */ + xRegisterDump.ulPC = xRegisterDump.ulR17_return_address_from_exceptions - portexINSTRUCTION_SIZE; + + #if ( XPAR_MICROBLAZE_USE_FPU != 0 ) + { + xRegisterDump.ulFSR = mffsr(); + } + #else + { + xRegisterDump.ulFSR = 0UL; + } + #endif + + /* Also fill in a string that describes what type of exception this is. + * The string uses the same ID names as defined in the MicroBlaze standard + * library exception header files. */ + switch( ( uint32_t ) pvExceptionID ) + { + case XEXC_ID_FSL: + xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FSL"; + break; + + case XEXC_ID_UNALIGNED_ACCESS: + xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_UNALIGNED_ACCESS"; + break; + + case XEXC_ID_ILLEGAL_OPCODE: + xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_ILLEGAL_OPCODE"; + break; + + case XEXC_ID_M_AXI_I_EXCEPTION: + xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_I_EXCEPTION or XEXC_ID_IPLB_EXCEPTION"; + break; + + case XEXC_ID_M_AXI_D_EXCEPTION: + xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_D_EXCEPTION or XEXC_ID_DPLB_EXCEPTION"; + break; + + case XEXC_ID_DIV_BY_ZERO: + xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_DIV_BY_ZERO"; + break; + + case XEXC_ID_STACK_VIOLATION: + xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_STACK_VIOLATION or XEXC_ID_MMU"; + break; + + #if ( XPAR_MICROBLAZE_USE_FPU != 0 ) + case XEXC_ID_FPU: + xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FPU see ulFSR value"; + break; + #endif /* XPAR_MICROBLAZE_USE_FPU */ + } + + /* vApplicationExceptionRegisterDump() is a callback function that the + * application can optionally define to receive the populated xPortRegisterDump + * structure. If the application chooses not to define a version of + * vApplicationExceptionRegisterDump() then the weekly defined default + * implementation within this file will be called instead. */ + vApplicationExceptionRegisterDump( &xRegisterDump ); + + /* Must not attempt to leave this function! */ + for( ; ; ) + { + portNOP(); + } + } +/*-----------------------------------------------------------*/ + + void vPortExceptionsInstallHandlers( void ) + { + static uint32_t ulHandlersAlreadyInstalled = pdFALSE; + + if( ulHandlersAlreadyInstalled == pdFALSE ) + { + ulHandlersAlreadyInstalled = pdTRUE; + + #if XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS == 1 + microblaze_register_exception_handler( XEXC_ID_UNALIGNED_ACCESS, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_UNALIGNED_ACCESS ); + #endif /* XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS*/ + + #if XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_ILLEGAL_OPCODE, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_ILLEGAL_OPCODE ); + #endif /* XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION */ + + #if XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_M_AXI_I_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_I_EXCEPTION ); + #endif /* XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION */ + + #if XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_M_AXI_D_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_D_EXCEPTION ); + #endif /* XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION */ + + #if XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_IPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_IPLB_EXCEPTION ); + #endif /* XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION */ + + #if XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_DPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DPLB_EXCEPTION ); + #endif /* XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION */ + + #if XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_DIV_BY_ZERO, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DIV_BY_ZERO ); + #endif /* XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION */ + + #if XPAR_MICROBLAZE_FPU_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_FPU, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FPU ); + #endif /* XPAR_MICROBLAZE_FPU_EXCEPTION */ + + #if XPAR_MICROBLAZE_FSL_EXCEPTION == 1 + microblaze_register_exception_handler( XEXC_ID_FSL, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FSL ); + #endif /* XPAR_MICROBLAZE_FSL_EXCEPTION */ + + microblaze_enable_exceptions(); + } + } + +/* Exclude the entire file if the MicroBlaze is not configured to handle + * exceptions, or the application defined configuration item + * configINSTALL_EXCEPTION_HANDLERS is not set to 1. */ +#endif /* ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */ diff --git a/portable/GCC/MicroBlazeV9/portasm.S b/portable/GCC/MicroBlazeV9/portasm.S new file mode 100644 index 000000000..7480e76ed --- /dev/null +++ b/portable/GCC/MicroBlazeV9/portasm.S @@ -0,0 +1,433 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" + +/* Xilinx library includes. */ +#include "microblaze_exceptions_g.h" +#include "xparameters.h" + +#include "microblaze_instructions.h" +/* The context is oversized to allow functions called from the ISR to write +back into the caller stack. */ +#if defined (__arch64__) +#if( XPAR_MICROBLAZE_USE_FPU != 0 ) + #define portCONTEXT_SIZE 272 + #define portMINUS_CONTEXT_SIZE -272 +#else + #define portCONTEXT_SIZE 264 + #define portMINUS_CONTEXT_SIZE -264 +#endif +#else +#if( XPAR_MICROBLAZE_USE_FPU != 0 ) + #define portCONTEXT_SIZE 136 + #define portMINUS_CONTEXT_SIZE -136 +#else + #define portCONTEXT_SIZE 132 + #define portMINUS_CONTEXT_SIZE -132 +#endif +#endif + +/* Offsets from the stack pointer at which saved registers are placed. */ +#if defined (__arch64__) +#define portR31_OFFSET 8 +#define portR30_OFFSET 16 +#define portR29_OFFSET 24 +#define portR28_OFFSET 32 +#define portR27_OFFSET 40 +#define portR26_OFFSET 48 +#define portR25_OFFSET 56 +#define portR24_OFFSET 64 +#define portR23_OFFSET 72 +#define portR22_OFFSET 80 +#define portR21_OFFSET 88 +#define portR20_OFFSET 96 +#define portR19_OFFSET 104 +#define portR18_OFFSET 112 +#define portR17_OFFSET 120 +#define portR16_OFFSET 128 +#define portR15_OFFSET 136 +#define portR14_OFFSET 144 +#define portR13_OFFSET 152 +#define portR12_OFFSET 160 +#define portR11_OFFSET 168 +#define portR10_OFFSET 176 +#define portR9_OFFSET 184 +#define portR8_OFFSET 192 +#define portR7_OFFSET 200 +#define portR6_OFFSET 208 +#define portR5_OFFSET 216 +#define portR4_OFFSET 224 +#define portR3_OFFSET 232 +#define portR2_OFFSET 240 +#define portCRITICAL_NESTING_OFFSET 248 +#define portMSR_OFFSET 256 +#define portFSR_OFFSET 264 +#else +#define portR31_OFFSET 4 +#define portR30_OFFSET 8 +#define portR29_OFFSET 12 +#define portR28_OFFSET 16 +#define portR27_OFFSET 20 +#define portR26_OFFSET 24 +#define portR25_OFFSET 28 +#define portR24_OFFSET 32 +#define portR23_OFFSET 36 +#define portR22_OFFSET 40 +#define portR21_OFFSET 44 +#define portR20_OFFSET 48 +#define portR19_OFFSET 52 +#define portR18_OFFSET 56 +#define portR17_OFFSET 60 +#define portR16_OFFSET 64 +#define portR15_OFFSET 68 +#define portR14_OFFSET 72 +#define portR13_OFFSET 76 +#define portR12_OFFSET 80 +#define portR11_OFFSET 84 +#define portR10_OFFSET 88 +#define portR9_OFFSET 92 +#define portR8_OFFSET 96 +#define portR7_OFFSET 100 +#define portR6_OFFSET 104 +#define portR5_OFFSET 108 +#define portR4_OFFSET 112 +#define portR3_OFFSET 116 +#define portR2_OFFSET 120 +#define portCRITICAL_NESTING_OFFSET 124 +#define portMSR_OFFSET 128 +#define portFSR_OFFSET 132 + +#endif + + .extern pxCurrentTCB + .extern XIntc_DeviceInterruptHandler + .extern vTaskSwitchContext + .extern uxCriticalNesting + .extern pulISRStack + .extern ulTaskSwitchRequested + .extern vPortExceptionHandler + .extern pulStackPointerOnFunctionEntry + + .global _interrupt_handler + .global VPortYieldASM + .global vPortStartFirstTask + .global vPortExceptionHandlerEntry + + +.macro portSAVE_CONTEXT + + /* Make room for the context on the stack. */ + ADDLIK r1, r1, portMINUS_CONTEXT_SIZE + + /* Stack general registers. */ + SI r31, r1, portR31_OFFSET + SI r30, r1, portR30_OFFSET + SI r29, r1, portR29_OFFSET + SI r28, r1, portR28_OFFSET + SI r27, r1, portR27_OFFSET + SI r26, r1, portR26_OFFSET + SI r25, r1, portR25_OFFSET + SI r24, r1, portR24_OFFSET + SI r23, r1, portR23_OFFSET + SI r22, r1, portR22_OFFSET + SI r21, r1, portR21_OFFSET + SI r20, r1, portR20_OFFSET + SI r19, r1, portR19_OFFSET + SI r18, r1, portR18_OFFSET + SI r17, r1, portR17_OFFSET + SI r16, r1, portR16_OFFSET + SI r15, r1, portR15_OFFSET + /* R14 is saved later as it needs adjustment if a yield is performed. */ + SI r13, r1, portR13_OFFSET + SI r12, r1, portR12_OFFSET + SI r11, r1, portR11_OFFSET + SI r10, r1, portR10_OFFSET + SI r9, r1, portR9_OFFSET + SI r8, r1, portR8_OFFSET + SI r7, r1, portR7_OFFSET + SI r6, r1, portR6_OFFSET + SI r5, r1, portR5_OFFSET + SI r4, r1, portR4_OFFSET + SI r3, r1, portR3_OFFSET + SI r2, r1, portR2_OFFSET + + /* Stack the critical section nesting value. */ + LI r18, r0, uxCriticalNesting + SI r18, r1, portCRITICAL_NESTING_OFFSET + + /* Stack MSR. */ + mfs r18, rmsr + SI r18, r1, portMSR_OFFSET + + #if( XPAR_MICROBLAZE_USE_FPU != 0 ) + /* Stack FSR. */ + mfs r18, rfsr + SI r18, r1, portFSR_OFFSET + #endif + +#if( XPAR_MICROBLAZE_USE_STACK_PROTECTION ) + /* Save the stack limits */ + mfs r18, rslr + swi r18, r1, portSLR_OFFSET + mfs r18, rshr + swi r18, r1, portSHR_OFFSET +#endif + + /* Save the top of stack value to the TCB. */ + LI r3, r0, pxCurrentTCB + STORE r1, r0, r3 + + .endm + +.macro portRESTORE_CONTEXT + + /* Load the top of stack value from the TCB. */ + LI r18, r0, pxCurrentTCB + LOAD r1, r0, r18 + +#if( XPAR_MICROBLAZE_USE_STACK_PROTECTION ) + /* Restore the stack limits -- must not load from r1 (Stack Pointer) + because if the address of load or store instruction is out of range, + it will trigger Stack Protection Violation exception. */ + or r18, r0, r1 + lwi r12, r18, portSLR_OFFSET + mts rslr, r12 + lwi r12, r18, portSHR_OFFSET + mts rshr, r12 +#endif + + /* Restore the general registers. */ + LI r31, r1, portR31_OFFSET + LI r30, r1, portR30_OFFSET + LI r29, r1, portR29_OFFSET + LI r28, r1, portR28_OFFSET + LI r27, r1, portR27_OFFSET + LI r26, r1, portR26_OFFSET + LI r25, r1, portR25_OFFSET + LI r24, r1, portR24_OFFSET + LI r23, r1, portR23_OFFSET + LI r22, r1, portR22_OFFSET + LI r21, r1, portR21_OFFSET + LI r20, r1, portR20_OFFSET + LI r19, r1, portR19_OFFSET + LI r17, r1, portR17_OFFSET + LI r16, r1, portR16_OFFSET + LI r15, r1, portR15_OFFSET + LI r14, r1, portR14_OFFSET + LI r13, r1, portR13_OFFSET + LI r12, r1, portR12_OFFSET + LI r11, r1, portR11_OFFSET + LI r10, r1, portR10_OFFSET + LI r9, r1, portR9_OFFSET + LI r8, r1, portR8_OFFSET + LI r7, r1, portR7_OFFSET + LI r6, r1, portR6_OFFSET + LI r5, r1, portR5_OFFSET + LI r4, r1, portR4_OFFSET + LI r3, r1, portR3_OFFSET + LI r2, r1, portR2_OFFSET + + /* Reload the rmsr from the stack. */ + LI r18, r1, portMSR_OFFSET + mts rmsr, r18 + + #if( XPAR_MICROBLAZE_USE_FPU != 0 ) + /* Reload the FSR from the stack. */ + LI r18, r1, portFSR_OFFSET + mts rfsr, r18 + #endif + + /* Load the critical nesting value. */ + LI r18, r1, portCRITICAL_NESTING_OFFSET + SI r18, r0, uxCriticalNesting + + /* Test the critical nesting value. If it is non zero then the task last + exited the running state using a yield. If it is zero, then the task + last exited the running state through an interrupt. */ + XORI r18, r18, 0 + BNEI r18, exit_from_yield + + /* r18 was being used as a temporary. Now restore its true value from the + stack. */ + LI r18, r1, portR18_OFFSET + + /* Remove the stack frame. */ + ADDLIK r1, r1, portCONTEXT_SIZE + + /* Return using rtid so interrupts are re-enabled as this function is + exited. */ + rtid r14, 0 + OR r0, r0, r0 + + .endm + +/* This function is used to exit portRESTORE_CONTEXT() if the task being +returned to last left the Running state by calling taskYIELD() (rather than +being preempted by an interrupt). */ + .text +#ifdef __arch64__ + .align 8 +#else + .align 4 +#endif + +exit_from_yield: + + /* r18 was being used as a temporary. Now restore its true value from the + stack. */ + LI r18, r1, portR18_OFFSET + + /* Remove the stack frame. */ + ADDLIK r1, r1, portCONTEXT_SIZE + + /* Return to the task. */ + rtsd r14, 0 + OR r0, r0, r0 + + + .text + +#ifdef __arch64__ + .align 8 +#else + .align 4 +#endif + +_interrupt_handler: + + portSAVE_CONTEXT + + /* Stack the return address. */ + SI r14, r1, portR14_OFFSET + + /* Switch to the ISR stack. */ + LI r1, r0, pulISRStack + +#if( XPAR_MICROBLAZE_USE_STACK_PROTECTION ) + ori r18, r0, _stack_end + mts rslr, r18 + ori r18, r0, _stack + mts rshr, r18 +#endif + + /* The parameter to the interrupt handler. */ + ORI r5, r0, configINTERRUPT_CONTROLLER_TO_USE + + /* Execute any pending interrupts. */ + BRALID r15, XIntc_DeviceInterruptHandler + OR r0, r0, r0 + + /* See if a new task should be selected to execute. */ + LI r18, r0, ulTaskSwitchRequested + OR r18, r18, r0 + + /* If ulTaskSwitchRequested is already zero, then jump straight to + restoring the task that is already in the Running state. */ + BEQI r18, task_switch_not_requested + + /* Set ulTaskSwitchRequested back to zero as a task switch is about to be + performed. */ + SI r0, r0, ulTaskSwitchRequested + + /* ulTaskSwitchRequested was not 0 when tested. Select the next task to + execute. */ + BRALID r15, vTaskSwitchContext + OR r0, r0, r0 + +task_switch_not_requested: + + /* Restore the context of the next task scheduled to execute. */ + portRESTORE_CONTEXT + + + .text +#ifdef __arch64__ + .align 8 +#else + .align 4 +#endif + +VPortYieldASM: + + portSAVE_CONTEXT + + /* Modify the return address so a return is done to the instruction after + the call to VPortYieldASM. */ + ADDI r14, r14, 8 + SI r14, r1, portR14_OFFSET + + /* Switch to use the ISR stack. */ + LI r1, r0, pulISRStack + +#if( XPAR_MICROBLAZE_USE_STACK_PROTECTION ) + ori r18, r0, _stack_end + mts rslr, r18 + ori r18, r0, _stack + mts rshr, r18 +#endif + + /* Select the next task to execute. */ + BRALID r15, vTaskSwitchContext + OR r0, r0, r0 + + /* Restore the context of the next task scheduled to execute. */ + portRESTORE_CONTEXT + + .text +#ifdef __arch64__ + .align 8 +#else + .align 4 +#endif + +vPortStartFirstTask: + + portRESTORE_CONTEXT + + + +#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) + + .text +#ifdef __arch64__ + .align 8 +#else + .align 4 +#endif + +vPortExceptionHandlerEntry: + + /* Take a copy of the stack pointer before vPortExecptionHandler is called, + storing its value prior to the function stack frame being created. */ + SI r1, r0, pulStackPointerOnFunctionEntry + BRALID r15, vPortExceptionHandler + OR r0, r0, r0 + +#endif /* ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */ diff --git a/portable/GCC/MicroBlazeV9/portmacro.h b/portable/GCC/MicroBlazeV9/portmacro.h new file mode 100644 index 000000000..1fb9c8259 --- /dev/null +++ b/portable/GCC/MicroBlazeV9/portmacro.h @@ -0,0 +1,397 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/* BSP includes. */ +#include +#include + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#ifdef __arch64__ + #define portSTACK_TYPE size_t + typedef uint64_t UBaseType_t; +#else + #define portSTACK_TYPE uint32_t + typedef unsigned long UBaseType_t; +#endif +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; + + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Interrupt control macros and functions. */ +void microblaze_disable_interrupts( void ); +void microblaze_enable_interrupts( void ); +#define portDISABLE_INTERRUPTS() microblaze_disable_interrupts() +#define portENABLE_INTERRUPTS() microblaze_enable_interrupts() +/*-----------------------------------------------------------*/ + +/* Critical section macros. */ +void vPortEnterCritical( void ); +void vPortExitCritical( void ); +#define portENTER_CRITICAL() \ + { \ + extern volatile UBaseType_t uxCriticalNesting; \ + microblaze_disable_interrupts(); \ + uxCriticalNesting++; \ + } + +#define portEXIT_CRITICAL() \ + { \ + extern volatile UBaseType_t uxCriticalNesting; \ + /* Interrupts are disabled, so we can */ \ + /* access the variable directly. */ \ + uxCriticalNesting--; \ + if( uxCriticalNesting == 0 ) \ + { \ + /* The nesting has unwound and we \ + * can enable interrupts again. */ \ + portENABLE_INTERRUPTS(); \ + } \ + } + +/*-----------------------------------------------------------*/ + +/* The yield macro maps directly to the vPortYield() function. */ +void vPortYield( void ); +#define portYIELD() vPortYield() + +/* portYIELD_FROM_ISR() does not directly call vTaskSwitchContext(), but instead + * sets a flag to say that a yield has been requested. The interrupt exit code + * then checks this flag, and calls vTaskSwitchContext() before restoring a task + * context, if the flag is not false. This is done to prevent multiple calls to + * vTaskSwitchContext() being made from a single interrupt, as a single interrupt + * can result in multiple peripherals being serviced. */ +extern volatile uint32_t ulTaskSwitchRequested; +#define portYIELD_FROM_ISR( x ) \ + do { if( ( x ) != pdFALSE ) ulTaskSwitchRequested = 1; } \ + while( 0 ) + +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/* Generic helper function. */ + __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint8_t ucReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) ); + + return ucReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#ifdef __arch64__ + #define portBYTE_ALIGNMENT 8 +#else + #define portBYTE_ALIGNMENT 4 +#endif +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() asm volatile ( "NOP" ) +#define portMEMORY_BARRIER() asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + +#if ( XPAR_MICROBLAZE_USE_STACK_PROTECTION ) + #define portHAS_STACK_OVERFLOW_CHECKING 1 +#endif +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +/* The following structure is used by the FreeRTOS exception handler. It is + * filled with the MicroBlaze context as it was at the time the exception occurred. + * This is done as an aid to debugging exception occurrences. */ +typedef struct PORT_REGISTER_DUMP +{ + /* The following structure members hold the values of the MicroBlaze + * registers at the time the exception was raised. */ + UINTPTR ulR1_SP; + UINTPTR ulR2_small_data_area; + UINTPTR ulR3; + UINTPTR ulR4; + UINTPTR ulR5; + UINTPTR ulR6; + UINTPTR ulR7; + UINTPTR ulR8; + UINTPTR ulR9; + UINTPTR ulR10; + UINTPTR ulR11; + UINTPTR ulR12; + UINTPTR ulR13_read_write_small_data_area; + UINTPTR ulR14_return_address_from_interrupt; + UINTPTR ulR15_return_address_from_subroutine; + UINTPTR ulR16_return_address_from_trap; + UINTPTR ulR17_return_address_from_exceptions; /* The exception entry code will copy the BTR into R17 if the exception occurred in the delay slot of a branch instruction. */ + UINTPTR ulR18; + UINTPTR ulR19; + UINTPTR ulR20; + UINTPTR ulR21; + UINTPTR ulR22; + UINTPTR ulR23; + UINTPTR ulR24; + UINTPTR ulR25; + UINTPTR ulR26; + UINTPTR ulR27; + UINTPTR ulR28; + UINTPTR ulR29; + UINTPTR ulR30; + UINTPTR ulR31; + UINTPTR ulPC; + UINTPTR ulESR; + UINTPTR ulMSR; + UINTPTR ulEAR; + UINTPTR ulFSR; + UINTPTR ulEDR; + + /* A human readable description of the exception cause. The strings used + * are the same as the #define constant names found in the + * microblaze_exceptions_i.h header file */ + int8_t * pcExceptionCause; + + /* The human readable name of the task that was running at the time the + * exception occurred. This is the name that was given to the task when the + * task was created using the FreeRTOS xTaskCreate() API function. */ + char * pcCurrentTaskName; + + /* The handle of the task that was running a the time the exception + * occurred. */ + void * xCurrentTaskHandle; +} xPortRegisterDump; + + +/* + * Installs pxHandler as the interrupt handler for the peripheral specified by + * the ucInterruptID parameter. + * + * ucInterruptID: + * + * The ID of the peripheral that will have pxHandler assigned as its interrupt + * handler. Peripheral IDs are defined in the xparameters.h header file, which + * is itself part of the BSP project. For example, in the official demo + * application for this port, xparameters.h defines the following IDs for the + * four possible interrupt sources: + * + * XPAR_INTC_0_UARTLITE_1_VEC_ID - for the UARTlite peripheral. + * XPAR_INTC_0_TMRCTR_0_VEC_ID - for the AXI Timer 0 peripheral. + * XPAR_INTC_0_EMACLITE_0_VEC_ID - for the Ethernet lite peripheral. + * XPAR_INTC_0_GPIO_1_VEC_ID - for the button inputs. + * + * + * pxHandler: + * + * A pointer to the interrupt handler function itself. This must be a void + * function that takes a (void *) parameter. + * + * + * pvCallBackRef: + * + * The parameter passed into the handler function. In many cases this will not + * be used and can be NULL. Some times it is used to pass in a reference to + * the peripheral instance variable, so it can be accessed from inside the + * handler function. + * + * + * pdPASS is returned if the function executes successfully. Any other value + * being returned indicates that the function did not execute correctly. + */ +BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, + XInterruptHandler pxHandler, + void * pvCallBackRef ); + + +/* + * Enables the interrupt, within the interrupt controller, for the peripheral + * specified by the ucInterruptID parameter. + * + * ucInterruptID: + * + * The ID of the peripheral that will have its interrupt enabled in the + * interrupt controller. Peripheral IDs are defined in the xparameters.h header + * file, which is itself part of the BSP project. For example, in the official + * demo application for this port, xparameters.h defines the following IDs for + * the four possible interrupt sources: + * + * XPAR_INTC_0_UARTLITE_1_VEC_ID - for the UARTlite peripheral. + * XPAR_INTC_0_TMRCTR_0_VEC_ID - for the AXI Timer 0 peripheral. + * XPAR_INTC_0_EMACLITE_0_VEC_ID - for the Ethernet lite peripheral. + * XPAR_INTC_0_GPIO_1_VEC_ID - for the button inputs. + * + */ +void vPortEnableInterrupt( uint8_t ucInterruptID ); + +/* + * Disables the interrupt, within the interrupt controller, for the peripheral + * specified by the ucInterruptID parameter. + * + * ucInterruptID: + * + * The ID of the peripheral that will have its interrupt disabled in the + * interrupt controller. Peripheral IDs are defined in the xparameters.h header + * file, which is itself part of the BSP project. For example, in the official + * demo application for this port, xparameters.h defines the following IDs for + * the four possible interrupt sources: + * + * XPAR_INTC_0_UARTLITE_1_VEC_ID - for the UARTlite peripheral. + * XPAR_INTC_0_TMRCTR_0_VEC_ID - for the AXI Timer 0 peripheral. + * XPAR_INTC_0_EMACLITE_0_VEC_ID - for the Ethernet lite peripheral. + * XPAR_INTC_0_GPIO_1_VEC_ID - for the button inputs. + * + */ +void vPortDisableInterrupt( uint8_t ucInterruptID ); + +/* + * This is an application defined callback function used to install the tick + * interrupt handler. It is provided as an application callback because the + * kernel will run on lots of different MicroBlaze and FPGA configurations - not + * all of which will have the same timer peripherals defined or available. This + * example uses the AXI Timer 0. If that is available on your hardware platform + * then this example callback implementation should not require modification. + * The name of the interrupt handler that should be installed is vPortTickISR(), + * which the function below declares as an extern. + */ +void vApplicationSetupTimerInterrupt( void ); + +/* + * This is an application defined callback function used to clear whichever + * interrupt was installed by the the vApplicationSetupTimerInterrupt() callback + * function - in this case the interrupt generated by the AXI timer. It is + * provided as an application callback because the kernel will run on lots of + * different MicroBlaze and FPGA configurations - not all of which will have the + * same timer peripherals defined or available. This example uses the AXI Timer 0. + * If that is available on your hardware platform then this example callback + * implementation should not require modification provided the example definition + * of vApplicationSetupTimerInterrupt() is also not modified. + */ +void vApplicationClearTimerInterrupt( void ); + +/* + * vPortExceptionsInstallHandlers() is only available when the MicroBlaze + * is configured to include exception functionality, and + * configINSTALL_EXCEPTION_HANDLERS is set to 1 in FreeRTOSConfig.h. + * + * vPortExceptionsInstallHandlers() installs the FreeRTOS exception handler + * for every possible exception cause. + * + * vPortExceptionsInstallHandlers() can be called explicitly from application + * code. After that is done, the default FreeRTOS exception handler that will + * have been installed can be replaced for any specific exception cause by using + * the standard Xilinx library function microblaze_register_exception_handler(). + * + * If vPortExceptionsInstallHandlers() is not called explicitly by the + * application, it will be called automatically by the kernel the first time + * xPortInstallInterruptHandler() is called. At that time, any exception + * handlers that may have already been installed will be replaced. + * + * See the description of vApplicationExceptionRegisterDump() for information + * on the processing performed by the FreeRTOS exception handler. + */ +void vPortExceptionsInstallHandlers( void ); + +/* + * The FreeRTOS exception handler fills an xPortRegisterDump structure (defined + * in portmacro.h) with the MicroBlaze context, as it was at the time the + * exception occurred. The exception handler then calls + * vApplicationExceptionRegisterDump(), passing in the completed + * xPortRegisterDump structure as its parameter. + * + * The FreeRTOS kernel provides its own implementation of + * vApplicationExceptionRegisterDump(), but the kernel provided implementation + * is declared as being 'weak'. The weak definition allows the application + * writer to provide their own implementation, should they wish to use the + * register dump information. For example, an implementation could be provided + * that wrote the register dump data to a display, or a UART port. + */ +void vApplicationExceptionRegisterDump( xPortRegisterDump * xRegisterDump ); + + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ \ No newline at end of file diff --git a/portable/GCC/NiosII/port.c b/portable/GCC/NiosII/port.c new file mode 100644 index 000000000..974c7d121 --- /dev/null +++ b/portable/GCC/NiosII/port.c @@ -0,0 +1,216 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the NIOS2 port. +*----------------------------------------------------------*/ + +/* Standard Includes. */ +#include +#include + +/* Altera includes. */ +#include "sys/alt_irq.h" +#include "sys/alt_exceptions.h" +#include "altera_avalon_timer_regs.h" +#include "priv/alt_irq_table.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Interrupts are enabled. */ +#define portINITIAL_ESTATUS ( StackType_t ) 0x01 + +int _alt_ic_isr_register( alt_u32 ic_id, + alt_u32 irq, + alt_isr_func isr, + void * isr_context, + void * flags ); +/*-----------------------------------------------------------*/ + +/* + * Setup the timer to generate the tick interrupts. + */ +static void prvSetupTimerInterrupt( void ); + +/* + * Call back for the alarm function. + */ +void vPortSysTickHandler( void * context ); + +/*-----------------------------------------------------------*/ + +static void prvReadGp( uint32_t * ulValue ) +{ + asm ( "stw gp, (%0)" ::"r" ( ulValue ) ); +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + StackType_t * pxFramePointer = pxTopOfStack - 1; + StackType_t xGlobalPointer; + + prvReadGp( &xGlobalPointer ); + + /* End of stack marker. */ + *pxTopOfStack = 0xdeadbeef; + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) pxFramePointer; + pxTopOfStack--; + + *pxTopOfStack = xGlobalPointer; + + /* Space for R23 to R16. */ + pxTopOfStack -= 9; + + *pxTopOfStack = ( StackType_t ) pxCode; + pxTopOfStack--; + + *pxTopOfStack = portINITIAL_ESTATUS; + + /* Space for R15 to R5. */ + pxTopOfStack -= 12; + + *pxTopOfStack = ( StackType_t ) pvParameters; + + /* Space for R3 to R1, muldiv and RA. */ + pxTopOfStack -= 5; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + asm volatile ( " movia r2, restore_sp_from_pxCurrentTCB \n" + " jmp r2 " ); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the NIOS2 port will require this function as there + * is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +void prvSetupTimerInterrupt( void ) +{ + /* Try to register the interrupt handler. */ + if( -EINVAL == _alt_ic_isr_register( SYS_CLK_IRQ_INTERRUPT_CONTROLLER_ID, SYS_CLK_IRQ, vPortSysTickHandler, 0x0, 0x0 ) ) + { + /* Failed to install the Interrupt Handler. */ + asm ( "break" ); + } + else + { + /* Configure SysTick to interrupt at the requested rate. */ + IOWR_ALTERA_AVALON_TIMER_CONTROL( SYS_CLK_BASE, ALTERA_AVALON_TIMER_CONTROL_STOP_MSK ); + IOWR_ALTERA_AVALON_TIMER_PERIODL( SYS_CLK_BASE, ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) & 0xFFFF ); + IOWR_ALTERA_AVALON_TIMER_PERIODH( SYS_CLK_BASE, ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) >> 16 ); + IOWR_ALTERA_AVALON_TIMER_CONTROL( SYS_CLK_BASE, ALTERA_AVALON_TIMER_CONTROL_CONT_MSK | ALTERA_AVALON_TIMER_CONTROL_START_MSK | ALTERA_AVALON_TIMER_CONTROL_ITO_MSK ); + } + + /* Clear any already pending interrupts generated by the Timer. */ + IOWR_ALTERA_AVALON_TIMER_STATUS( SYS_CLK_BASE, ~ALTERA_AVALON_TIMER_STATUS_TO_MSK ); +} +/*-----------------------------------------------------------*/ + +void vPortSysTickHandler( void * context ) +{ + /* Increment the kernel tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + vTaskSwitchContext(); + } + + /* Clear the interrupt. */ + IOWR_ALTERA_AVALON_TIMER_STATUS( SYS_CLK_BASE, ~ALTERA_AVALON_TIMER_STATUS_TO_MSK ); +} +/*-----------------------------------------------------------*/ + +/** This function is a re-implementation of the Altera provided function. + * The function is re-implemented to prevent it from enabling an interrupt + * when it is registered. Interrupts should only be enabled after the FreeRTOS.org + * kernel has its scheduler started so that contexts are saved and switched + * correctly. + */ +int _alt_ic_isr_register( alt_u32 ic_id, + alt_u32 irq, + alt_isr_func isr, + void * isr_context, + void * flags ) +{ + int rc = -EINVAL; + alt_irq_context status; + int id = irq; /* IRQ interpreted as the interrupt ID. */ + + if( id < ALT_NIRQ ) + { + /* + * interrupts are disabled while the handler tables are updated to ensure + * that an interrupt doesn't occur while the tables are in an inconsistent + * state. + */ + + status = alt_irq_disable_all(); + + alt_irq[ id ].handler = isr; + alt_irq[ id ].context = isr_context; + + rc = ( isr ) ? alt_ic_irq_enable( ic_id, id ) : alt_ic_irq_disable( ic_id, id ); + + /* alt_irq_enable_all(status); This line is removed to prevent the interrupt from being immediately enabled. */ + } + + return rc; +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/NiosII/port_asm.S b/portable/GCC/NiosII/port_asm.S new file mode 100644 index 000000000..1485ab3fc --- /dev/null +++ b/portable/GCC/NiosII/port_asm.S @@ -0,0 +1,139 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +.extern vTaskSwitchContext + +.set noat + +# Exported to start the first task. +.globl restore_sp_from_pxCurrentTCB + +# Entry point for exceptions. +.section .exceptions.entry.user, "xa" + +# Save the entire context of a task. +save_context: + addi sp, sp, -116 # Create space on the stack. + stw ra, 0(sp) + # Leave a gap for muldiv 0 + stw at, 8(sp) + stw r2, 12(sp) + stw r3, 16(sp) + stw r4, 20(sp) + stw r5, 24(sp) + stw r6, 28(sp) + stw r7, 32(sp) + stw r8, 36(sp) + stw r9, 40(sp) + stw r10, 44(sp) + stw r11, 48(sp) + stw r12, 52(sp) + stw r13, 56(sp) + stw r14, 60(sp) + stw r15, 64(sp) + rdctl r5, estatus # Save the eStatus + stw r5, 68(sp) + addi r15, ea, -4 # Instruction that caused exception + stw r15, 72(sp) # Save as EA + stw r16, 76(sp) # Save the remaining registers + stw r17, 80(sp) + stw r18, 84(sp) + stw r19, 88(sp) + stw r20, 92(sp) + stw r21, 96(sp) + stw r22, 100(sp) + stw r23, 104(sp) + stw gp, 108(sp) + stw fp, 112(sp) + +save_sp_to_pxCurrentTCB: + movia et, pxCurrentTCB # Load the address of the pxCurrentTCB pointer + ldw et, (et) # Load the value of the pxCurrentTCB pointer + stw sp, (et) # Store the stack pointer into the top of the TCB + + br irq_test_user # skip the section .exceptions.entry + + .section .exceptions.irqtest, "xa" +irq_test_user: + + .section .exceptions.exit.user, "xa" +restore_sp_from_pxCurrentTCB: + movia et, pxCurrentTCB # Load the address of the pxCurrentTCB pointer + ldw et, (et) # Load the value of the pxCurrentTCB pointer + ldw sp, (et) # Load the stack pointer with the top value of the TCB + +restore_context: + ldw ra, 0(sp) # Restore the registers. + # Leave a gap for muldiv 0. + ldw at, 8(sp) + ldw r2, 12(sp) + ldw r3, 16(sp) + ldw r4, 20(sp) + ldw r5, 24(sp) + ldw r6, 28(sp) + ldw r7, 32(sp) + ldw r8, 36(sp) + ldw r9, 40(sp) + ldw r10, 44(sp) + ldw r11, 48(sp) + ldw r12, 52(sp) + ldw r13, 56(sp) + ldw r14, 60(sp) + ldw r15, 64(sp) + ldw et, 68(sp) # Load the eStatus + wrctl estatus, et # Write the eStatus + ldw ea, 72(sp) # Load the Program Counter + ldw r16, 76(sp) + ldw r17, 80(sp) + ldw r18, 84(sp) + ldw r19, 88(sp) + ldw r20, 92(sp) + ldw r21, 96(sp) + ldw r22, 100(sp) + ldw r23, 104(sp) + ldw gp, 108(sp) + ldw fp, 112(sp) + addi sp, sp, 116 # Release stack space + + eret # Return to address ea, loading eStatus into Status. + + .section .exceptions.soft, "xa" +soft_exceptions: + movhi r3, 0x003b /* upper half of trap opcode */ + ori r3, r3, 0x683a /* lower half of trap opcode */ + beq r2, r3, call_scheduler + br exceptions_unknown_user # its something else + +call_scheduler: + stw ea, 72(sp) # EA is PC+4 so will skip over instruction causing exception + movia r15, vTaskSwitchContext # Pick the next context - use long call version in place of "call" + callr r15 + br restore_sp_from_pxCurrentTCB # Switch in the task context and restore. + + .section .exceptions.unknown.user +exceptions_unknown_user: diff --git a/portable/GCC/NiosII/portmacro.h b/portable/GCC/NiosII/portmacro.h new file mode 100644 index 000000000..957f4db79 --- /dev/null +++ b/portable/GCC/NiosII/portmacro.h @@ -0,0 +1,126 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +#include "sys/alt_irq.h" + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +#define portNOP() asm volatile ( "NOP" ) +#define portCRITICAL_NESTING_IN_TCB 1 +/*-----------------------------------------------------------*/ + +extern void vTaskSwitchContext( void ); +#define portYIELD() asm volatile ( "trap" ); +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + vTaskSwitchContext(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) + +/* Include the port_asm.S file where the Context saving/restoring is defined. */ +__asm__ ( "\n\t.globl save_context" ); + +/*-----------------------------------------------------------*/ + +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); + +#define portDISABLE_INTERRUPTS() alt_irq_disable_all() +#define portENABLE_INTERRUPTS() alt_irq_enable_all( 0x01 ); +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/PPC405_Xilinx/FPU_Macros.h b/portable/GCC/PPC405_Xilinx/FPU_Macros.h new file mode 100644 index 000000000..8446c9ae1 --- /dev/null +++ b/portable/GCC/PPC405_Xilinx/FPU_Macros.h @@ -0,0 +1,45 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* When switching out a task, if the task tag contains a buffer address then + * save the flop context into the buffer. */ +#define traceTASK_SWITCHED_OUT() \ + if( pxCurrentTCB->pxTaskTag != NULL ) \ + { \ + extern void vPortSaveFPURegisters( void * ); \ + vPortSaveFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) ); \ + } + +/* When switching in a task, if the task tag contains a buffer address then + * load the flop context from the buffer. */ +#define traceTASK_SWITCHED_IN() \ + if( pxCurrentTCB->pxTaskTag != NULL ) \ + { \ + extern void vPortRestoreFPURegisters( void * ); \ + vPortRestoreFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) ); \ + } diff --git a/portable/GCC/PPC405_Xilinx/port.c b/portable/GCC/PPC405_Xilinx/port.c new file mode 100644 index 000000000..c815cf265 --- /dev/null +++ b/portable/GCC/PPC405_Xilinx/port.c @@ -0,0 +1,267 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the PPC405 port. +*----------------------------------------------------------*/ + + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Library includes. */ +#include "xtime_l.h" +#include "xintc.h" +#include "xintc_i.h" + +/*-----------------------------------------------------------*/ + +/* Definitions to set the initial MSR of each task. */ +#define portCRITICAL_INTERRUPT_ENABLE ( 1UL << 17UL ) +#define portEXTERNAL_INTERRUPT_ENABLE ( 1UL << 15UL ) +#define portMACHINE_CHECK_ENABLE ( 1UL << 12UL ) + +#if configUSE_FPU == 1 + #define portAPU_PRESENT ( 1UL << 25UL ) + #define portFCM_FPU_PRESENT ( 1UL << 13UL ) +#else + #define portAPU_PRESENT ( 0UL ) + #define portFCM_FPU_PRESENT ( 0UL ) +#endif + +#define portINITIAL_MSR ( portCRITICAL_INTERRUPT_ENABLE | portEXTERNAL_INTERRUPT_ENABLE | portMACHINE_CHECK_ENABLE | portAPU_PRESENT | portFCM_FPU_PRESENT ) + + +extern const unsigned _SDA_BASE_; +extern const unsigned _SDA2_BASE_; + +/*-----------------------------------------------------------*/ + +/* + * Setup the system timer to generate the tick interrupt. + */ +static void prvSetupTimerInterrupt( void ); + +/* + * The handler for the tick interrupt - defined in portasm.s. + */ +extern void vPortTickISR( void ); + +/* + * The handler for the yield function - defined in portasm.s. + */ +extern void vPortYield( void ); + +/* + * Function to start the scheduler running by starting the highest + * priority task that has thus far been created. + */ +extern void vPortStartFirstTask( void ); + +/*-----------------------------------------------------------*/ + +/* Structure used to hold the state of the interrupt controller. */ +static XIntc xInterruptController; + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if the task had been + * interrupted. + * + * See the header file portable.h. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Place a known value at the bottom of the stack for debugging. */ + *pxTopOfStack = 0xDEADBEEF; + pxTopOfStack--; + + /* EABI stack frame. */ + pxTopOfStack -= 20; /* Previous backchain and LR, R31 to R4 inclusive. */ + + /* Parameters in R13. */ + *pxTopOfStack = ( StackType_t ) &_SDA_BASE_; /* address of the first small data area */ + pxTopOfStack -= 10; + + /* Parameters in R3. */ + *pxTopOfStack = ( StackType_t ) pvParameters; + pxTopOfStack--; + + /* Parameters in R2. */ + *pxTopOfStack = ( StackType_t ) &_SDA2_BASE_; /* address of the second small data area */ + pxTopOfStack--; + + /* R1 is the stack pointer so is omitted. */ + + *pxTopOfStack = 0x10000001UL; /* R0. */ + pxTopOfStack--; + *pxTopOfStack = 0x00000000UL; /* USPRG0. */ + pxTopOfStack--; + *pxTopOfStack = 0x00000000UL; /* CR. */ + pxTopOfStack--; + *pxTopOfStack = 0x00000000UL; /* XER. */ + pxTopOfStack--; + *pxTopOfStack = 0x00000000UL; /* CTR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) vPortEndScheduler; /* LR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* SRR0. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_MSR; /* SRR1. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) vPortEndScheduler; /* Next LR. */ + pxTopOfStack--; + *pxTopOfStack = 0x00000000UL; /* Backchain. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + prvSetupTimerInterrupt(); + XExc_RegisterHandler( XEXC_ID_SYSTEM_CALL, ( XExceptionHandler ) vPortYield, ( void * ) 0 ); + vPortStartFirstTask(); + + /* Should not get here as the tasks are now running! */ + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented. */ + for( ; ; ) + { + } +} +/*-----------------------------------------------------------*/ + +/* + * Hardware initialisation to generate the RTOS tick. + */ +static void prvSetupTimerInterrupt( void ) +{ + const uint32_t ulInterval = ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL ); + + XTime_PITClearInterrupt(); + XTime_FITClearInterrupt(); + XTime_WDTClearInterrupt(); + XTime_WDTDisableInterrupt(); + XTime_FITDisableInterrupt(); + + XExc_RegisterHandler( XEXC_ID_PIT_INT, ( XExceptionHandler ) vPortTickISR, ( void * ) 0 ); + + XTime_PITEnableAutoReload(); + XTime_PITSetInterval( ulInterval ); + XTime_PITEnableInterrupt(); +} +/*-----------------------------------------------------------*/ + +void vPortISRHandler( void * pvNullDoNotUse ) +{ + uint32_t ulInterruptStatus, ulInterruptMask = 1UL; + BaseType_t xInterruptNumber; + XIntc_Config * pxInterruptController; + XIntc_VectorTableEntry * pxTable; + + /* Just to remove compiler warning. */ + ( void ) pvNullDoNotUse; + + /* Get the configuration by using the device ID - in this case it is + * assumed that only one interrupt controller is being used. */ + pxInterruptController = &XIntc_ConfigTable[ XPAR_XPS_INTC_0_DEVICE_ID ]; + + /* Which interrupts are pending? */ + ulInterruptStatus = XIntc_mGetIntrStatus( pxInterruptController->BaseAddress ); + + for( xInterruptNumber = 0; xInterruptNumber < XPAR_INTC_MAX_NUM_INTR_INPUTS; xInterruptNumber++ ) + { + if( ulInterruptStatus & 0x01UL ) + { + /* Clear the pending interrupt. */ + XIntc_mAckIntr( pxInterruptController->BaseAddress, ulInterruptMask ); + + /* Call the registered handler. */ + pxTable = &( pxInterruptController->HandlerTable[ xInterruptNumber ] ); + pxTable->Handler( pxTable->CallBackRef ); + } + + /* Check the next interrupt. */ + ulInterruptMask <<= 0x01UL; + ulInterruptStatus >>= 0x01UL; + + /* Have we serviced all interrupts? */ + if( ulInterruptStatus == 0UL ) + { + break; + } + } +} +/*-----------------------------------------------------------*/ + +void vPortSetupInterruptController( void ) +{ + extern void vPortISRWrapper( void ); + + /* Perform all library calls necessary to initialise the exception table + * and interrupt controller. This assumes only one interrupt controller is in + * use. */ + XExc_mDisableExceptions( XEXC_NON_CRITICAL ); + XExc_Init(); + + /* The library functions save the context - we then jump to a wrapper to + * save the stack into the TCB. The wrapper then calls the handler defined + * above. */ + XExc_RegisterHandler( XEXC_ID_NON_CRITICAL_INT, ( XExceptionHandler ) vPortISRWrapper, NULL ); + XIntc_Initialize( &xInterruptController, XPAR_XPS_INTC_0_DEVICE_ID ); + XIntc_Start( &xInterruptController, XIN_REAL_MODE ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, + XInterruptHandler pxHandler, + void * pvCallBackRef ) +{ + BaseType_t xReturn = pdFAIL; + + /* This function is defined here so the scope of xInterruptController can + * remain within this file. */ + + if( XST_SUCCESS == XIntc_Connect( &xInterruptController, ucInterruptID, pxHandler, pvCallBackRef ) ) + { + XIntc_Enable( &xInterruptController, ucInterruptID ); + xReturn = pdPASS; + } + + return xReturn; +} diff --git a/portable/GCC/PPC405_Xilinx/portasm.S b/portable/GCC/PPC405_Xilinx/portasm.S new file mode 100644 index 000000000..db3e3b916 --- /dev/null +++ b/portable/GCC/PPC405_Xilinx/portasm.S @@ -0,0 +1,381 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include "FreeRTOSConfig.h" + + .extern pxCurrentTCB + .extern vTaskSwitchContext + .extern xTaskIncrementTick + .extern vPortISRHandler + + .global vPortStartFirstTask + .global vPortYield + .global vPortTickISR + .global vPortISRWrapper + .global vPortSaveFPURegisters + .global vPortRestoreFPURegisters + +.set BChainField, 0 +.set NextLRField, BChainField + 4 +.set MSRField, NextLRField + 4 +.set PCField, MSRField + 4 +.set LRField, PCField + 4 +.set CTRField, LRField + 4 +.set XERField, CTRField + 4 +.set CRField, XERField + 4 +.set USPRG0Field, CRField + 4 +.set r0Field, USPRG0Field + 4 +.set r2Field, r0Field + 4 +.set r3r31Field, r2Field + 4 +.set IFrameSize, r3r31Field + ( ( 31 - 3 ) + 1 ) * 4 + + +.macro portSAVE_STACK_POINTER_AND_LR + + /* Get the address of the TCB. */ + xor R0, R0, R0 + addis R2, R0, pxCurrentTCB@ha + lwz R2, pxCurrentTCB@l( R2 ) + + /* Store the stack pointer into the TCB */ + stw SP, 0( R2 ) + + /* Save the link register */ + stwu R1, -24( R1 ) + mflr R0 + stw R31, 20( R1 ) + stw R0, 28( R1 ) + mr R31, r1 + +.endm + +.macro portRESTORE_STACK_POINTER_AND_LR + + /* Restore the link register */ + lwz R11, 0( R1 ) + lwz R0, 4( R11 ) + mtlr R0 + lwz R31, -4( R11 ) + mr R1, R11 + + /* Get the address of the TCB. */ + xor R0, R0, R0 + addis SP, R0, pxCurrentTCB@ha + lwz SP, pxCurrentTCB@l( R1 ) + + /* Get the task stack pointer from the TCB. */ + lwz SP, 0( SP ) + +.endm + + +vPortStartFirstTask: + + /* Get the address of the TCB. */ + xor R0, R0, R0 + addis SP, R0, pxCurrentTCB@ha + lwz SP, pxCurrentTCB@l( SP ) + + /* Get the task stack pointer from the TCB. */ + lwz SP, 0( SP ) + + /* Restore MSR register to SRR1. */ + lwz R0, MSRField(R1) + mtsrr1 R0 + + /* Restore current PC location to SRR0. */ + lwz R0, PCField(R1) + mtsrr0 R0 + + /* Save USPRG0 register */ + lwz R0, USPRG0Field(R1) + mtspr 0x100,R0 + + /* Restore Condition register */ + lwz R0, CRField(R1) + mtcr R0 + + /* Restore Fixed Point Exception register */ + lwz R0, XERField(R1) + mtxer R0 + + /* Restore Counter register */ + lwz R0, CTRField(R1) + mtctr R0 + + /* Restore Link register */ + lwz R0, LRField(R1) + mtlr R0 + + /* Restore remaining GPR registers. */ + lmw R3,r3r31Field(R1) + + /* Restore r0 and r2. */ + lwz R0, r0Field(R1) + lwz R2, r2Field(R1) + + /* Remove frame from stack */ + addi R1,R1,IFrameSize + + /* Return into the first task */ + rfi + + + +vPortYield: + + portSAVE_STACK_POINTER_AND_LR + bl vTaskSwitchContext + portRESTORE_STACK_POINTER_AND_LR + blr + +vPortTickISR: + + portSAVE_STACK_POINTER_AND_LR + bl xTaskIncrementTick + + #if configUSE_PREEMPTION == 1 + bl vTaskSwitchContext + #endif + + /* Clear the interrupt */ + lis R0, 2048 + mttsr R0 + + portRESTORE_STACK_POINTER_AND_LR + blr + +vPortISRWrapper: + + portSAVE_STACK_POINTER_AND_LR + bl vPortISRHandler + portRESTORE_STACK_POINTER_AND_LR + blr + +#if configUSE_FPU == 1 + +vPortSaveFPURegisters: + + /* Enable APU and mark FPU as present. */ + mfmsr r0 + xor r30, r30, r30 + oris r30, r30, 512 + ori r30, r30, 8192 + or r0, r0, r30 + mtmsr r0 + +#ifdef USE_DP_FPU + + /* Buffer address is in r3. Save each flop register into an offset from + this buffer address. */ + stfd f0, 0(r3) + stfd f1, 8(r3) + stfd f2, 16(r3) + stfd f3, 24(r3) + stfd f4, 32(r3) + stfd f5, 40(r3) + stfd f6, 48(r3) + stfd f7, 56(r3) + stfd f8, 64(r3) + stfd f9, 72(r3) + stfd f10, 80(r3) + stfd f11, 88(r3) + stfd f12, 96(r3) + stfd f13, 104(r3) + stfd f14, 112(r3) + stfd f15, 120(r3) + stfd f16, 128(r3) + stfd f17, 136(r3) + stfd f18, 144(r3) + stfd f19, 152(r3) + stfd f20, 160(r3) + stfd f21, 168(r3) + stfd f22, 176(r3) + stfd f23, 184(r3) + stfd f24, 192(r3) + stfd f25, 200(r3) + stfd f26, 208(r3) + stfd f27, 216(r3) + stfd f28, 224(r3) + stfd f29, 232(r3) + stfd f30, 240(r3) + stfd f31, 248(r3) + + /* Also save the FPSCR. */ + mffs f31 + stfs f31, 256(r3) + +#else + + /* Buffer address is in r3. Save each flop register into an offset from + this buffer address. */ + stfs f0, 0(r3) + stfs f1, 4(r3) + stfs f2, 8(r3) + stfs f3, 12(r3) + stfs f4, 16(r3) + stfs f5, 20(r3) + stfs f6, 24(r3) + stfs f7, 28(r3) + stfs f8, 32(r3) + stfs f9, 36(r3) + stfs f10, 40(r3) + stfs f11, 44(r3) + stfs f12, 48(r3) + stfs f13, 52(r3) + stfs f14, 56(r3) + stfs f15, 60(r3) + stfs f16, 64(r3) + stfs f17, 68(r3) + stfs f18, 72(r3) + stfs f19, 76(r3) + stfs f20, 80(r3) + stfs f21, 84(r3) + stfs f22, 88(r3) + stfs f23, 92(r3) + stfs f24, 96(r3) + stfs f25, 100(r3) + stfs f26, 104(r3) + stfs f27, 108(r3) + stfs f28, 112(r3) + stfs f29, 116(r3) + stfs f30, 120(r3) + stfs f31, 124(r3) + + /* Also save the FPSCR. */ + mffs f31 + stfs f31, 128(r3) + +#endif + + blr + +#endif /* configUSE_FPU. */ + + +#if configUSE_FPU == 1 + +vPortRestoreFPURegisters: + + /* Enable APU and mark FPU as present. */ + mfmsr r0 + xor r30, r30, r30 + oris r30, r30, 512 + ori r30, r30, 8192 + or r0, r0, r30 + mtmsr r0 + +#ifdef USE_DP_FPU + + /* Buffer address is in r3. Restore each flop register from an offset + into this buffer. + + First the FPSCR. */ + lfs f31, 256(r3) + mtfsf f31, 7 + + lfd f0, 0(r3) + lfd f1, 8(r3) + lfd f2, 16(r3) + lfd f3, 24(r3) + lfd f4, 32(r3) + lfd f5, 40(r3) + lfd f6, 48(r3) + lfd f7, 56(r3) + lfd f8, 64(r3) + lfd f9, 72(r3) + lfd f10, 80(r3) + lfd f11, 88(r3) + lfd f12, 96(r3) + lfd f13, 104(r3) + lfd f14, 112(r3) + lfd f15, 120(r3) + lfd f16, 128(r3) + lfd f17, 136(r3) + lfd f18, 144(r3) + lfd f19, 152(r3) + lfd f20, 160(r3) + lfd f21, 168(r3) + lfd f22, 176(r3) + lfd f23, 184(r3) + lfd f24, 192(r3) + lfd f25, 200(r3) + lfd f26, 208(r3) + lfd f27, 216(r3) + lfd f28, 224(r3) + lfd f29, 232(r3) + lfd f30, 240(r3) + lfd f31, 248(r3) + +#else + + /* Buffer address is in r3. Restore each flop register from an offset + into this buffer. + + First the FPSCR. */ + lfs f31, 128(r3) + mtfsf f31, 7 + + lfs f0, 0(r3) + lfs f1, 4(r3) + lfs f2, 8(r3) + lfs f3, 12(r3) + lfs f4, 16(r3) + lfs f5, 20(r3) + lfs f6, 24(r3) + lfs f7, 28(r3) + lfs f8, 32(r3) + lfs f9, 36(r3) + lfs f10, 40(r3) + lfs f11, 44(r3) + lfs f12, 48(r3) + lfs f13, 52(r3) + lfs f14, 56(r3) + lfs f15, 60(r3) + lfs f16, 64(r3) + lfs f17, 68(r3) + lfs f18, 72(r3) + lfs f19, 76(r3) + lfs f20, 80(r3) + lfs f21, 84(r3) + lfs f22, 88(r3) + lfs f23, 92(r3) + lfs f24, 96(r3) + lfs f25, 100(r3) + lfs f26, 104(r3) + lfs f27, 108(r3) + lfs f28, 112(r3) + lfs f29, 116(r3) + lfs f30, 120(r3) + lfs f31, 124(r3) + +#endif + + blr + +#endif /* configUSE_FPU. */ diff --git a/portable/GCC/PPC405_Xilinx/portmacro.h b/portable/GCC/PPC405_Xilinx/portmacro.h new file mode 100644 index 000000000..128d75c37 --- /dev/null +++ b/portable/GCC/PPC405_Xilinx/portmacro.h @@ -0,0 +1,126 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#include "xexception_l.h" + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* This port uses the critical nesting count from the TCB rather than + * maintaining a separate value and then saving this value in the task stack. */ +#define portCRITICAL_NESTING_IN_TCB 1 + +/* Interrupt control macros. */ +#define portDISABLE_INTERRUPTS() XExc_mDisableExceptions( XEXC_NON_CRITICAL ); +#define portENABLE_INTERRUPTS() XExc_mEnableExceptions( XEXC_NON_CRITICAL ); + +/*-----------------------------------------------------------*/ + +/* Critical section macros. */ +void vTaskEnterCritical( void ); +void vTaskExitCritical( void ); +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +void vPortYield( void ); +#define portYIELD() asm volatile ( "SC \n\t NOP" ) +#define portYIELD_FROM_ISR() vTaskSwitchContext() + +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 8 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() asm volatile ( "NOP" ) + +/* There are 32 * 32bit floating point registers, plus the FPSCR to save. */ +#define portNO_FLOP_REGISTERS_TO_SAVE ( 32 + 1 ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* Port specific interrupt handling functions. */ +void vPortSetupInterruptController( void ); +BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, + XInterruptHandler pxHandler, + void * pvCallBackRef ); + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/PPC440_Xilinx/FPU_Macros.h b/portable/GCC/PPC440_Xilinx/FPU_Macros.h new file mode 100644 index 000000000..8446c9ae1 --- /dev/null +++ b/portable/GCC/PPC440_Xilinx/FPU_Macros.h @@ -0,0 +1,45 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* When switching out a task, if the task tag contains a buffer address then + * save the flop context into the buffer. */ +#define traceTASK_SWITCHED_OUT() \ + if( pxCurrentTCB->pxTaskTag != NULL ) \ + { \ + extern void vPortSaveFPURegisters( void * ); \ + vPortSaveFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) ); \ + } + +/* When switching in a task, if the task tag contains a buffer address then + * load the flop context from the buffer. */ +#define traceTASK_SWITCHED_IN() \ + if( pxCurrentTCB->pxTaskTag != NULL ) \ + { \ + extern void vPortRestoreFPURegisters( void * ); \ + vPortRestoreFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) ); \ + } diff --git a/portable/GCC/PPC440_Xilinx/port.c b/portable/GCC/PPC440_Xilinx/port.c new file mode 100644 index 000000000..a17c25918 --- /dev/null +++ b/portable/GCC/PPC440_Xilinx/port.c @@ -0,0 +1,267 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the PPC440 port. +*----------------------------------------------------------*/ + + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Library includes. */ +#include "xtime_l.h" +#include "xintc.h" +#include "xintc_i.h" + +/*-----------------------------------------------------------*/ + +/* Definitions to set the initial MSR of each task. */ +#define portCRITICAL_INTERRUPT_ENABLE ( 1UL << 17UL ) +#define portEXTERNAL_INTERRUPT_ENABLE ( 1UL << 15UL ) +#define portMACHINE_CHECK_ENABLE ( 1UL << 12UL ) + +#if configUSE_FPU == 1 + #define portAPU_PRESENT ( 1UL << 25UL ) + #define portFCM_FPU_PRESENT ( 1UL << 13UL ) +#else + #define portAPU_PRESENT ( 0UL ) + #define portFCM_FPU_PRESENT ( 0UL ) +#endif + +#define portINITIAL_MSR ( portCRITICAL_INTERRUPT_ENABLE | portEXTERNAL_INTERRUPT_ENABLE | portMACHINE_CHECK_ENABLE | portAPU_PRESENT | portFCM_FPU_PRESENT ) + + +extern const unsigned _SDA_BASE_; +extern const unsigned _SDA2_BASE_; + +/*-----------------------------------------------------------*/ + +/* + * Setup the system timer to generate the tick interrupt. + */ +static void prvSetupTimerInterrupt( void ); + +/* + * The handler for the tick interrupt - defined in portasm.s. + */ +extern void vPortTickISR( void ); + +/* + * The handler for the yield function - defined in portasm.s. + */ +extern void vPortYield( void ); + +/* + * Function to start the scheduler running by starting the highest + * priority task that has thus far been created. + */ +extern void vPortStartFirstTask( void ); + +/*-----------------------------------------------------------*/ + +/* Structure used to hold the state of the interrupt controller. */ +static XIntc xInterruptController; + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if the task had been + * interrupted. + * + * See the header file portable.h. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Place a known value at the bottom of the stack for debugging. */ + *pxTopOfStack = 0xDEADBEEF; + pxTopOfStack--; + + /* EABI stack frame. */ + pxTopOfStack -= 20; /* Previous backchain and LR, R31 to R4 inclusive. */ + + /* Parameters in R13. */ + *pxTopOfStack = ( StackType_t ) &_SDA_BASE_; /* address of the first small data area */ + pxTopOfStack -= 10; + + /* Parameters in R3. */ + *pxTopOfStack = ( StackType_t ) pvParameters; + pxTopOfStack--; + + /* Parameters in R2. */ + *pxTopOfStack = ( StackType_t ) &_SDA2_BASE_; /* address of the second small data area */ + pxTopOfStack--; + + /* R1 is the stack pointer so is omitted. */ + + *pxTopOfStack = 0x10000001UL; /* R0. */ + pxTopOfStack--; + *pxTopOfStack = 0x00000000UL; /* USPRG0. */ + pxTopOfStack--; + *pxTopOfStack = 0x00000000UL; /* CR. */ + pxTopOfStack--; + *pxTopOfStack = 0x00000000UL; /* XER. */ + pxTopOfStack--; + *pxTopOfStack = 0x00000000UL; /* CTR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) vPortEndScheduler; /* LR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* SRR0. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_MSR; /* SRR1. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) vPortEndScheduler; /* Next LR. */ + pxTopOfStack--; + *pxTopOfStack = 0x00000000UL; /* Backchain. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + prvSetupTimerInterrupt(); + XExc_RegisterHandler( XEXC_ID_SYSTEM_CALL, ( XExceptionHandler ) vPortYield, ( void * ) 0 ); + vPortStartFirstTask(); + + /* Should not get here as the tasks are now running! */ + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented. */ + for( ; ; ) + { + } +} +/*-----------------------------------------------------------*/ + +/* + * Hardware initialisation to generate the RTOS tick. + */ +static void prvSetupTimerInterrupt( void ) +{ + const uint32_t ulInterval = ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL ); + + XTime_DECClearInterrupt(); + XTime_FITClearInterrupt(); + XTime_WDTClearInterrupt(); + XTime_WDTDisableInterrupt(); + XTime_FITDisableInterrupt(); + + XExc_RegisterHandler( XEXC_ID_DEC_INT, ( XExceptionHandler ) vPortTickISR, ( void * ) 0 ); + + XTime_DECEnableAutoReload(); + XTime_DECSetInterval( ulInterval ); + XTime_DECEnableInterrupt(); +} +/*-----------------------------------------------------------*/ + +void vPortISRHandler( void * pvNullDoNotUse ) +{ + uint32_t ulInterruptStatus, ulInterruptMask = 1UL; + BaseType_t xInterruptNumber; + XIntc_Config * pxInterruptController; + XIntc_VectorTableEntry * pxTable; + + /* Just to remove compiler warning. */ + ( void ) pvNullDoNotUse; + + /* Get the configuration by using the device ID - in this case it is + * assumed that only one interrupt controller is being used. */ + pxInterruptController = &XIntc_ConfigTable[ XPAR_XPS_INTC_0_DEVICE_ID ]; + + /* Which interrupts are pending? */ + ulInterruptStatus = XIntc_mGetIntrStatus( pxInterruptController->BaseAddress ); + + for( xInterruptNumber = 0; xInterruptNumber < XPAR_INTC_MAX_NUM_INTR_INPUTS; xInterruptNumber++ ) + { + if( ulInterruptStatus & 0x01UL ) + { + /* Clear the pending interrupt. */ + XIntc_mAckIntr( pxInterruptController->BaseAddress, ulInterruptMask ); + + /* Call the registered handler. */ + pxTable = &( pxInterruptController->HandlerTable[ xInterruptNumber ] ); + pxTable->Handler( pxTable->CallBackRef ); + } + + /* Check the next interrupt. */ + ulInterruptMask <<= 0x01UL; + ulInterruptStatus >>= 0x01UL; + + /* Have we serviced all interrupts? */ + if( ulInterruptStatus == 0UL ) + { + break; + } + } +} +/*-----------------------------------------------------------*/ + +void vPortSetupInterruptController( void ) +{ + extern void vPortISRWrapper( void ); + + /* Perform all library calls necessary to initialise the exception table + * and interrupt controller. This assumes only one interrupt controller is in + * use. */ + XExc_mDisableExceptions( XEXC_NON_CRITICAL ); + XExc_Init(); + + /* The library functions save the context - we then jump to a wrapper to + * save the stack into the TCB. The wrapper then calls the handler defined + * above. */ + XExc_RegisterHandler( XEXC_ID_NON_CRITICAL_INT, ( XExceptionHandler ) vPortISRWrapper, NULL ); + XIntc_Initialize( &xInterruptController, XPAR_XPS_INTC_0_DEVICE_ID ); + XIntc_Start( &xInterruptController, XIN_REAL_MODE ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, + XInterruptHandler pxHandler, + void * pvCallBackRef ) +{ + BaseType_t xReturn = pdFAIL; + + /* This function is defined here so the scope of xInterruptController can + * remain within this file. */ + + if( XST_SUCCESS == XIntc_Connect( &xInterruptController, ucInterruptID, pxHandler, pvCallBackRef ) ) + { + XIntc_Enable( &xInterruptController, ucInterruptID ); + xReturn = pdPASS; + } + + return xReturn; +} diff --git a/portable/GCC/PPC440_Xilinx/portasm.S b/portable/GCC/PPC440_Xilinx/portasm.S new file mode 100644 index 000000000..db3e3b916 --- /dev/null +++ b/portable/GCC/PPC440_Xilinx/portasm.S @@ -0,0 +1,381 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include "FreeRTOSConfig.h" + + .extern pxCurrentTCB + .extern vTaskSwitchContext + .extern xTaskIncrementTick + .extern vPortISRHandler + + .global vPortStartFirstTask + .global vPortYield + .global vPortTickISR + .global vPortISRWrapper + .global vPortSaveFPURegisters + .global vPortRestoreFPURegisters + +.set BChainField, 0 +.set NextLRField, BChainField + 4 +.set MSRField, NextLRField + 4 +.set PCField, MSRField + 4 +.set LRField, PCField + 4 +.set CTRField, LRField + 4 +.set XERField, CTRField + 4 +.set CRField, XERField + 4 +.set USPRG0Field, CRField + 4 +.set r0Field, USPRG0Field + 4 +.set r2Field, r0Field + 4 +.set r3r31Field, r2Field + 4 +.set IFrameSize, r3r31Field + ( ( 31 - 3 ) + 1 ) * 4 + + +.macro portSAVE_STACK_POINTER_AND_LR + + /* Get the address of the TCB. */ + xor R0, R0, R0 + addis R2, R0, pxCurrentTCB@ha + lwz R2, pxCurrentTCB@l( R2 ) + + /* Store the stack pointer into the TCB */ + stw SP, 0( R2 ) + + /* Save the link register */ + stwu R1, -24( R1 ) + mflr R0 + stw R31, 20( R1 ) + stw R0, 28( R1 ) + mr R31, r1 + +.endm + +.macro portRESTORE_STACK_POINTER_AND_LR + + /* Restore the link register */ + lwz R11, 0( R1 ) + lwz R0, 4( R11 ) + mtlr R0 + lwz R31, -4( R11 ) + mr R1, R11 + + /* Get the address of the TCB. */ + xor R0, R0, R0 + addis SP, R0, pxCurrentTCB@ha + lwz SP, pxCurrentTCB@l( R1 ) + + /* Get the task stack pointer from the TCB. */ + lwz SP, 0( SP ) + +.endm + + +vPortStartFirstTask: + + /* Get the address of the TCB. */ + xor R0, R0, R0 + addis SP, R0, pxCurrentTCB@ha + lwz SP, pxCurrentTCB@l( SP ) + + /* Get the task stack pointer from the TCB. */ + lwz SP, 0( SP ) + + /* Restore MSR register to SRR1. */ + lwz R0, MSRField(R1) + mtsrr1 R0 + + /* Restore current PC location to SRR0. */ + lwz R0, PCField(R1) + mtsrr0 R0 + + /* Save USPRG0 register */ + lwz R0, USPRG0Field(R1) + mtspr 0x100,R0 + + /* Restore Condition register */ + lwz R0, CRField(R1) + mtcr R0 + + /* Restore Fixed Point Exception register */ + lwz R0, XERField(R1) + mtxer R0 + + /* Restore Counter register */ + lwz R0, CTRField(R1) + mtctr R0 + + /* Restore Link register */ + lwz R0, LRField(R1) + mtlr R0 + + /* Restore remaining GPR registers. */ + lmw R3,r3r31Field(R1) + + /* Restore r0 and r2. */ + lwz R0, r0Field(R1) + lwz R2, r2Field(R1) + + /* Remove frame from stack */ + addi R1,R1,IFrameSize + + /* Return into the first task */ + rfi + + + +vPortYield: + + portSAVE_STACK_POINTER_AND_LR + bl vTaskSwitchContext + portRESTORE_STACK_POINTER_AND_LR + blr + +vPortTickISR: + + portSAVE_STACK_POINTER_AND_LR + bl xTaskIncrementTick + + #if configUSE_PREEMPTION == 1 + bl vTaskSwitchContext + #endif + + /* Clear the interrupt */ + lis R0, 2048 + mttsr R0 + + portRESTORE_STACK_POINTER_AND_LR + blr + +vPortISRWrapper: + + portSAVE_STACK_POINTER_AND_LR + bl vPortISRHandler + portRESTORE_STACK_POINTER_AND_LR + blr + +#if configUSE_FPU == 1 + +vPortSaveFPURegisters: + + /* Enable APU and mark FPU as present. */ + mfmsr r0 + xor r30, r30, r30 + oris r30, r30, 512 + ori r30, r30, 8192 + or r0, r0, r30 + mtmsr r0 + +#ifdef USE_DP_FPU + + /* Buffer address is in r3. Save each flop register into an offset from + this buffer address. */ + stfd f0, 0(r3) + stfd f1, 8(r3) + stfd f2, 16(r3) + stfd f3, 24(r3) + stfd f4, 32(r3) + stfd f5, 40(r3) + stfd f6, 48(r3) + stfd f7, 56(r3) + stfd f8, 64(r3) + stfd f9, 72(r3) + stfd f10, 80(r3) + stfd f11, 88(r3) + stfd f12, 96(r3) + stfd f13, 104(r3) + stfd f14, 112(r3) + stfd f15, 120(r3) + stfd f16, 128(r3) + stfd f17, 136(r3) + stfd f18, 144(r3) + stfd f19, 152(r3) + stfd f20, 160(r3) + stfd f21, 168(r3) + stfd f22, 176(r3) + stfd f23, 184(r3) + stfd f24, 192(r3) + stfd f25, 200(r3) + stfd f26, 208(r3) + stfd f27, 216(r3) + stfd f28, 224(r3) + stfd f29, 232(r3) + stfd f30, 240(r3) + stfd f31, 248(r3) + + /* Also save the FPSCR. */ + mffs f31 + stfs f31, 256(r3) + +#else + + /* Buffer address is in r3. Save each flop register into an offset from + this buffer address. */ + stfs f0, 0(r3) + stfs f1, 4(r3) + stfs f2, 8(r3) + stfs f3, 12(r3) + stfs f4, 16(r3) + stfs f5, 20(r3) + stfs f6, 24(r3) + stfs f7, 28(r3) + stfs f8, 32(r3) + stfs f9, 36(r3) + stfs f10, 40(r3) + stfs f11, 44(r3) + stfs f12, 48(r3) + stfs f13, 52(r3) + stfs f14, 56(r3) + stfs f15, 60(r3) + stfs f16, 64(r3) + stfs f17, 68(r3) + stfs f18, 72(r3) + stfs f19, 76(r3) + stfs f20, 80(r3) + stfs f21, 84(r3) + stfs f22, 88(r3) + stfs f23, 92(r3) + stfs f24, 96(r3) + stfs f25, 100(r3) + stfs f26, 104(r3) + stfs f27, 108(r3) + stfs f28, 112(r3) + stfs f29, 116(r3) + stfs f30, 120(r3) + stfs f31, 124(r3) + + /* Also save the FPSCR. */ + mffs f31 + stfs f31, 128(r3) + +#endif + + blr + +#endif /* configUSE_FPU. */ + + +#if configUSE_FPU == 1 + +vPortRestoreFPURegisters: + + /* Enable APU and mark FPU as present. */ + mfmsr r0 + xor r30, r30, r30 + oris r30, r30, 512 + ori r30, r30, 8192 + or r0, r0, r30 + mtmsr r0 + +#ifdef USE_DP_FPU + + /* Buffer address is in r3. Restore each flop register from an offset + into this buffer. + + First the FPSCR. */ + lfs f31, 256(r3) + mtfsf f31, 7 + + lfd f0, 0(r3) + lfd f1, 8(r3) + lfd f2, 16(r3) + lfd f3, 24(r3) + lfd f4, 32(r3) + lfd f5, 40(r3) + lfd f6, 48(r3) + lfd f7, 56(r3) + lfd f8, 64(r3) + lfd f9, 72(r3) + lfd f10, 80(r3) + lfd f11, 88(r3) + lfd f12, 96(r3) + lfd f13, 104(r3) + lfd f14, 112(r3) + lfd f15, 120(r3) + lfd f16, 128(r3) + lfd f17, 136(r3) + lfd f18, 144(r3) + lfd f19, 152(r3) + lfd f20, 160(r3) + lfd f21, 168(r3) + lfd f22, 176(r3) + lfd f23, 184(r3) + lfd f24, 192(r3) + lfd f25, 200(r3) + lfd f26, 208(r3) + lfd f27, 216(r3) + lfd f28, 224(r3) + lfd f29, 232(r3) + lfd f30, 240(r3) + lfd f31, 248(r3) + +#else + + /* Buffer address is in r3. Restore each flop register from an offset + into this buffer. + + First the FPSCR. */ + lfs f31, 128(r3) + mtfsf f31, 7 + + lfs f0, 0(r3) + lfs f1, 4(r3) + lfs f2, 8(r3) + lfs f3, 12(r3) + lfs f4, 16(r3) + lfs f5, 20(r3) + lfs f6, 24(r3) + lfs f7, 28(r3) + lfs f8, 32(r3) + lfs f9, 36(r3) + lfs f10, 40(r3) + lfs f11, 44(r3) + lfs f12, 48(r3) + lfs f13, 52(r3) + lfs f14, 56(r3) + lfs f15, 60(r3) + lfs f16, 64(r3) + lfs f17, 68(r3) + lfs f18, 72(r3) + lfs f19, 76(r3) + lfs f20, 80(r3) + lfs f21, 84(r3) + lfs f22, 88(r3) + lfs f23, 92(r3) + lfs f24, 96(r3) + lfs f25, 100(r3) + lfs f26, 104(r3) + lfs f27, 108(r3) + lfs f28, 112(r3) + lfs f29, 116(r3) + lfs f30, 120(r3) + lfs f31, 124(r3) + +#endif + + blr + +#endif /* configUSE_FPU. */ diff --git a/portable/GCC/PPC440_Xilinx/portmacro.h b/portable/GCC/PPC440_Xilinx/portmacro.h new file mode 100644 index 000000000..128d75c37 --- /dev/null +++ b/portable/GCC/PPC440_Xilinx/portmacro.h @@ -0,0 +1,126 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#include "xexception_l.h" + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* This port uses the critical nesting count from the TCB rather than + * maintaining a separate value and then saving this value in the task stack. */ +#define portCRITICAL_NESTING_IN_TCB 1 + +/* Interrupt control macros. */ +#define portDISABLE_INTERRUPTS() XExc_mDisableExceptions( XEXC_NON_CRITICAL ); +#define portENABLE_INTERRUPTS() XExc_mEnableExceptions( XEXC_NON_CRITICAL ); + +/*-----------------------------------------------------------*/ + +/* Critical section macros. */ +void vTaskEnterCritical( void ); +void vTaskExitCritical( void ); +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +void vPortYield( void ); +#define portYIELD() asm volatile ( "SC \n\t NOP" ) +#define portYIELD_FROM_ISR() vTaskSwitchContext() + +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 8 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() asm volatile ( "NOP" ) + +/* There are 32 * 32bit floating point registers, plus the FPSCR to save. */ +#define portNO_FLOP_REGISTERS_TO_SAVE ( 32 + 1 ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* Port specific interrupt handling functions. */ +void vPortSetupInterruptController( void ); +BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, + XInterruptHandler pxHandler, + void * pvCallBackRef ); + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/RISC-V/Documentation.url b/portable/GCC/RISC-V/Documentation.url new file mode 100644 index 000000000..5546f8707 --- /dev/null +++ b/portable/GCC/RISC-V/Documentation.url @@ -0,0 +1,5 @@ +[{000214A0-0000-0000-C000-000000000046}] +Prop3=19,11 +[InternetShortcut] +IDList= +URL=https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html diff --git a/portable/GCC/RISC-V/chip_extensions.cmake b/portable/GCC/RISC-V/chip_extensions.cmake new file mode 100644 index 000000000..c0d2c0d86 --- /dev/null +++ b/portable/GCC/RISC-V/chip_extensions.cmake @@ -0,0 +1,19 @@ +if( FREERTOS_PORT STREQUAL "GCC_RISC_V_GENERIC" ) + set( VALID_CHIP_EXTENSIONS + "Pulpino_Vega_RV32M1RM" + "RISCV_MTIME_CLINT_no_extensions" + "RISCV_no_extensions" + "RV32I_CLINT_no_extensions" ) + + if( ( NOT FREERTOS_RISCV_EXTENSION ) OR ( NOT ( ${FREERTOS_RISCV_EXTENSION} IN_LIST VALID_CHIP_EXTENSIONS ) ) ) + message(FATAL_ERROR + "FREERTOS_RISCV_EXTENSION \"${FREERTOS_RISCV_EXTENSION}\" is not set or unsupported.\n" + "Please specify it from top-level CMake file (example):\n" + " set(FREERTOS_RISCV_EXTENSION RISCV_MTIME_CLINT_no_extensions CACHE STRING \"\")\n" + " or from CMake command line option:\n" + " -DFREERTOS_RISCV_EXTENSION=RISCV_MTIME_CLINT_no_extensions\n" + "\n" + " Available extension options:\n" + " ${VALID_CHIP_EXTENSIONS} \n") + endif() +endif() diff --git a/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h b/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h new file mode 100644 index 000000000..4d8a5fb53 --- /dev/null +++ b/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h @@ -0,0 +1,108 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * The FreeRTOS kernel's RISC-V port is split between the the code that is + * common across all currently supported RISC-V chips (implementations of the + * RISC-V ISA), and code that tailors the port to a specific RISC-V chip: + * + * + FreeRTOS\Source\portable\GCC\RISC-V\portASM.S contains the code that + * is common to all currently supported RISC-V chips. There is only one + * portASM.S file because the same file is built for all RISC-V target chips. + * + * + Header files called freertos_risc_v_chip_specific_extensions.h contain the + * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V + * chip. There are multiple freertos_risc_v_chip_specific_extensions.h files + * as there are multiple RISC-V chip implementations. + * + * !!!NOTE!!! + * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h + * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the + * compiler's!) include path. For example, if the chip in use includes a core + * local interrupter (CLINT) and does not include any chip specific register + * extensions then add the path below to the assembler's include path: + * FreeRTOS\Source\portable\GCC\RISC-V\chip_specific_extensions\RV32I_CLINT_no_extensions + * + */ + +/* + * This freertos_risc_v_chip_specific_extensions.h is for use with Pulpino Ri5cy + * devices, developed and tested using the Vega board RV32M1RM. + */ + +#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__ +#define __FREERTOS_RISC_V_EXTENSIONS_H__ + +#define portasmHAS_MTIME 0 + +/* Constants to define the additional registers found on the Pulpino RI5KY. */ +#define lpstart0 0x7b0 +#define lpend0 0x7b1 +#define lpcount0 0x7b2 +#define lpstart1 0x7b4 +#define lpend1 0x7b5 +#define lpcount1 0x7b6 + +/* Six additional registers to save and restore, as per the #defines above. */ +#define portasmADDITIONAL_CONTEXT_SIZE 6 /* Must be even number on 32-bit cores. */ + +/* Save additional registers found on the Pulpino. */ +.macro portasmSAVE_ADDITIONAL_REGISTERS +addi sp, sp, -( portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE ) /* Make room for the additional registers. */ +csrr t0, lpstart0 /* Load additional registers into accessible temporary registers. */ +csrr t1, lpend0 +csrr t2, lpcount0 +csrr t3, lpstart1 +csrr t4, lpend1 +csrr t5, lpcount1 +sw t0, 1 * portWORD_SIZE( sp ) +sw t1, 2 * portWORD_SIZE( sp ) +sw t2, 3 * portWORD_SIZE( sp ) +sw t3, 4 * portWORD_SIZE( sp ) +sw t4, 5 * portWORD_SIZE( sp ) +sw t5, 6 * portWORD_SIZE( sp ) + .endm + +/* Restore the additional registers found on the Pulpino. */ + .macro portasmRESTORE_ADDITIONAL_REGISTERS +lw t0, 1 * portWORD_SIZE( sp ) /* Load additional registers into accessible temporary registers. */ +lw t1, 2 * portWORD_SIZE( sp ) +lw t2, 3 * portWORD_SIZE( sp ) +lw t3, 4 * portWORD_SIZE( sp ) +lw t4, 5 * portWORD_SIZE( sp ) +lw t5, 6 * portWORD_SIZE( sp ) +csrw lpstart0, t0 +csrw lpend0, t1 +csrw lpcount0, t2 +csrw lpstart1, t3 +csrw lpend1, t4 +csrw lpcount1, t5 +addi sp, sp, ( portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE ) /* Remove space added for additional registers. */ + .endm + +#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */ diff --git a/portable/GCC/RISC-V/chip_specific_extensions/RISCV_MTIME_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h b/portable/GCC/RISC-V/chip_specific_extensions/RISCV_MTIME_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h new file mode 100644 index 000000000..3be456cb4 --- /dev/null +++ b/portable/GCC/RISC-V/chip_specific_extensions/RISCV_MTIME_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h @@ -0,0 +1,69 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * The FreeRTOS kernel's RISC-V port is split between the the code that is + * common across all currently supported RISC-V chips (implementations of the + * RISC-V ISA), and code that tailors the port to a specific RISC-V chip: + * + * + FreeRTOS\Source\portable\GCC\RISC-V\portASM.S contains the code that + * is common to all currently supported RISC-V chips. There is only one + * portASM.S file because the same file is built for all RISC-V target chips. + * + * + Header files called freertos_risc_v_chip_specific_extensions.h contain the + * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V + * chip. There are multiple freertos_risc_v_chip_specific_extensions.h files + * as there are multiple RISC-V chip implementations. + * + * !!!NOTE!!! + * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h + * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the + * compiler's!) include path. For example, if the chip in use includes a core + * local interrupter (CLINT) and does not include any chip specific register + * extensions then add the path below to the assembler's include path: + * FreeRTOS\Source\portable\GCC\RISC-V\chip_specific_extensions\RISCV_MTIME_CLINT_no_extensions + * + */ + + +#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__ +#define __FREERTOS_RISC_V_EXTENSIONS_H__ + +#define portasmHAS_SIFIVE_CLINT 1 +#define portasmHAS_MTIME 1 +#define portasmADDITIONAL_CONTEXT_SIZE 0 + +.macro portasmSAVE_ADDITIONAL_REGISTERS +/* No additional registers to save, so this macro does nothing. */ + .endm + + .macro portasmRESTORE_ADDITIONAL_REGISTERS +/* No additional registers to restore, so this macro does nothing. */ + .endm + +#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */ diff --git a/portable/GCC/RISC-V/chip_specific_extensions/RISCV_no_extensions/freertos_risc_v_chip_specific_extensions.h b/portable/GCC/RISC-V/chip_specific_extensions/RISCV_no_extensions/freertos_risc_v_chip_specific_extensions.h new file mode 100644 index 000000000..9f93824bd --- /dev/null +++ b/portable/GCC/RISC-V/chip_specific_extensions/RISCV_no_extensions/freertos_risc_v_chip_specific_extensions.h @@ -0,0 +1,69 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * The FreeRTOS kernel's RISC-V port is split between the the code that is + * common across all currently supported RISC-V chips (implementations of the + * RISC-V ISA), and code that tailors the port to a specific RISC-V chip: + * + * + FreeRTOS\Source\portable\GCC\RISC-V\portASM.S contains the code that + * is common to all currently supported RISC-V chips. There is only one + * portASM.S file because the same file is built for all RISC-V target chips. + * + * + Header files called freertos_risc_v_chip_specific_extensions.h contain the + * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V + * chip. There are multiple freertos_risc_v_chip_specific_extensions.h files + * as there are multiple RISC-V chip implementations. + * + * !!!NOTE!!! + * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h + * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the + * compiler's!) include path. For example, if the chip in use includes a core + * local interrupter (CLINT) and does not include any chip specific register + * extensions then add the path below to the assembler's include path: + * FreeRTOS\Source\portable\GCC\RISC-V\chip_specific_extensions\RISCV_MTIME_CLINT_no_extensions + * + */ + + +#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__ +#define __FREERTOS_RISC_V_EXTENSIONS_H__ + +#define portasmHAS_SIFIVE_CLINT 0 +#define portasmHAS_MTIME 0 +#define portasmADDITIONAL_CONTEXT_SIZE 0 + +.macro portasmSAVE_ADDITIONAL_REGISTERS +/* No additional registers to save, so this macro does nothing. */ + .endm + + .macro portasmRESTORE_ADDITIONAL_REGISTERS +/* No additional registers to restore, so this macro does nothing. */ + .endm + +#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */ diff --git a/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h b/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h new file mode 100644 index 000000000..5b9ef4c06 --- /dev/null +++ b/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h @@ -0,0 +1,69 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * The FreeRTOS kernel's RISC-V port is split between the the code that is + * common across all currently supported RISC-V chips (implementations of the + * RISC-V ISA), and code that tailors the port to a specific RISC-V chip: + * + * + FreeRTOS\Source\portable\GCC\RISC-V\portASM.S contains the code that + * is common to all currently supported RISC-V chips. There is only one + * portASM.S file because the same file is built for all RISC-V target chips. + * + * + Header files called freertos_risc_v_chip_specific_extensions.h contain the + * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V + * chip. There are multiple freertos_risc_v_chip_specific_extensions.h files + * as there are multiple RISC-V chip implementations. + * + * !!!NOTE!!! + * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h + * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the + * compiler's!) include path. For example, if the chip in use includes a core + * local interrupter (CLINT) and does not include any chip specific register + * extensions then add the path below to the assembler's include path: + * FreeRTOS\Source\portable\GCC\RISC-V\chip_specific_extensions\RV32I_CLINT_no_extensions + * + */ + + +#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__ +#define __FREERTOS_RISC_V_EXTENSIONS_H__ + +#define portasmHAS_SIFIVE_CLINT 1 +#define portasmHAS_MTIME 1 +#define portasmADDITIONAL_CONTEXT_SIZE 0 /* Must be even number on 32-bit cores. */ + +.macro portasmSAVE_ADDITIONAL_REGISTERS +/* No additional registers to save, so this macro does nothing. */ + .endm + + .macro portasmRESTORE_ADDITIONAL_REGISTERS +/* No additional registers to restore, so this macro does nothing. */ + .endm + +#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */ diff --git a/portable/GCC/RISC-V/chip_specific_extensions/readme.txt b/portable/GCC/RISC-V/chip_specific_extensions/readme.txt new file mode 100644 index 000000000..3e83157d7 --- /dev/null +++ b/portable/GCC/RISC-V/chip_specific_extensions/readme.txt @@ -0,0 +1,23 @@ +/* + * The FreeRTOS kernel's RISC-V port is split between the the code that is + * common across all currently supported RISC-V chips (implementations of the + * RISC-V ISA), and code that tailors the port to a specific RISC-V chip: + * + * + FreeRTOS\Source\portable\GCC\RISC-V\portASM.S contains the code that + * is common to all currently supported RISC-V chips. There is only one + * portASM.S file because the same file is built for all RISC-V target chips. + * + * + Header files called freertos_risc_v_chip_specific_extensions.h contain the + * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V + * chip. There are multiple freertos_risc_v_chip_specific_extensions.h files + * as there are multiple RISC-V chip implementations. + * + * !!!NOTE!!! + * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h + * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the + * compiler's!) include path. For example, if the chip in use includes a core + * local interrupter (CLINT) and does not include any chip specific register + * extensions then add the path below to the assembler's include path: + * FreeRTOS\Source\portable\GCC\RISC-V\chip_specific_extensions\RV32I_CLINT_no_extensions + * + */ diff --git a/portable/GCC/RISC-V/port.c b/portable/GCC/RISC-V/port.c new file mode 100644 index 000000000..8fe7a25d5 --- /dev/null +++ b/portable/GCC/RISC-V/port.c @@ -0,0 +1,208 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the RISC-V port. + *----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "portmacro.h" + +/* Standard includes. */ +#include "string.h" + +#ifdef configCLINT_BASE_ADDRESS + #warning "The configCLINT_BASE_ADDRESS constant has been deprecated. configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS are currently being derived from the (possibly 0) configCLINT_BASE_ADDRESS setting. Please update to define configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS directly in place of configCLINT_BASE_ADDRESS. See www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html" +#endif + +#ifndef configMTIME_BASE_ADDRESS + #warning "configMTIME_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtime register then set configMTIME_BASE_ADDRESS to the mapped address. Otherwise set configMTIME_BASE_ADDRESS to 0. See www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html" +#endif + +#ifndef configMTIMECMP_BASE_ADDRESS + #warning "configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtimecmp register then set configMTIMECMP_BASE_ADDRESS to the mapped address. Otherwise set configMTIMECMP_BASE_ADDRESS to 0. See www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html" +#endif + +/* Let the user override the pre-loading of the initial RA. */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS 0 +#endif + +/* The stack used by interrupt service routines. Set configISR_STACK_SIZE_WORDS + * to use a statically allocated array as the interrupt stack. Alternative leave + * configISR_STACK_SIZE_WORDS undefined and update the linker script so that a + * linker variable names __freertos_irq_stack_top has the same value as the top + * of the stack used by main. Using the linker script method will repurpose the + * stack that was used by main before the scheduler was started for use as the + * interrupt stack after the scheduler has started. */ +#ifdef configISR_STACK_SIZE_WORDS +static __attribute__( ( aligned( 16 ) ) ) StackType_t xISRStack[ configISR_STACK_SIZE_WORDS ] = { 0 }; +const StackType_t xISRStackTop = ( StackType_t ) &( xISRStack[ configISR_STACK_SIZE_WORDS & ~portBYTE_ALIGNMENT_MASK ] ); + +/* Don't use 0xa5 as the stack fill bytes as that is used by the kernel for + * the task stacks, and so will legitimately appear in many positions within + * the ISR stack. */ + #define portISR_STACK_FILL_BYTE 0xee +#else + extern const uint32_t __freertos_irq_stack_top[]; + const StackType_t xISRStackTop = ( StackType_t ) __freertos_irq_stack_top; +#endif + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) __attribute__( ( weak ) ); + +/*-----------------------------------------------------------*/ + +/* Used to program the machine timer compare register. */ +uint64_t ullNextTime = 0ULL; +const uint64_t * pullNextTime = &ullNextTime; +const size_t uxTimerIncrementsForOneTick = ( size_t ) ( ( configCPU_CLOCK_HZ ) / ( configTICK_RATE_HZ ) ); /* Assumes increment won't go over 32-bits. */ +UBaseType_t const ullMachineTimerCompareRegisterBase = configMTIMECMP_BASE_ADDRESS; +volatile uint64_t * pullMachineTimerCompareRegister = NULL; + +/* Holds the critical nesting value - deliberately non-zero at start up to + * ensure interrupts are not accidentally enabled before the scheduler starts. */ +size_t xCriticalNesting = ( size_t ) 0xaaaaaaaa; +size_t * pxCriticalNesting = &xCriticalNesting; + +/* Used to catch tasks that attempt to return from their implementing function. */ +size_t xTaskReturnAddress = ( size_t ) portTASK_RETURN_ADDRESS; + +/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task + * stack checking. A problem in the ISR stack will trigger an assert, not call + * the stack overflow hook function (because the stack overflow hook is specific + * to a task stack, not the ISR stack). */ +#if defined( configISR_STACK_SIZE_WORDS ) && ( configCHECK_FOR_STACK_OVERFLOW > 2 ) + #warning "This path not tested, or even compiled yet." + + static const uint8_t ucExpectedStackBytes[] = + { + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE + }; \ + + #define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) ) +#else /* if defined( configISR_STACK_SIZE_WORDS ) && ( configCHECK_FOR_STACK_OVERFLOW > 2 ) */ + /* Define the function away. */ + #define portCHECK_ISR_STACK() +#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */ + +/*-----------------------------------------------------------*/ + +#if ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) + + void vPortSetupTimerInterrupt( void ) + { + uint32_t ulCurrentTimeHigh, ulCurrentTimeLow; + volatile uint32_t * const pulTimeHigh = ( volatile uint32_t * const ) ( ( configMTIME_BASE_ADDRESS ) + 4UL ); /* 8-byte type so high 32-bit word is 4 bytes up. */ + volatile uint32_t * const pulTimeLow = ( volatile uint32_t * const ) ( configMTIME_BASE_ADDRESS ); + volatile uint32_t ulHartId; + + __asm volatile ( "csrr %0, mhartid" : "=r" ( ulHartId ) ); + + pullMachineTimerCompareRegister = ( volatile uint64_t * ) ( ullMachineTimerCompareRegisterBase + ( ulHartId * sizeof( uint64_t ) ) ); + + do + { + ulCurrentTimeHigh = *pulTimeHigh; + ulCurrentTimeLow = *pulTimeLow; + } while( ulCurrentTimeHigh != *pulTimeHigh ); + + ullNextTime = ( uint64_t ) ulCurrentTimeHigh; + ullNextTime <<= 32ULL; /* High 4-byte word is 32-bits up. */ + ullNextTime |= ( uint64_t ) ulCurrentTimeLow; + ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick; + *pullMachineTimerCompareRegister = ullNextTime; + + /* Prepare the time to use after the next tick interrupt. */ + ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick; + } + +#endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIME_BASE_ADDRESS != 0 ) */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + extern void xPortStartFirstTask( void ); + + #if ( configASSERT_DEFINED == 1 ) + { + /* Check alignment of the interrupt stack - which is the same as the + * stack that was being used by main() prior to the scheduler being + * started. */ + configASSERT( ( xISRStackTop & portBYTE_ALIGNMENT_MASK ) == 0 ); + + #ifdef configISR_STACK_SIZE_WORDS + { + memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) ); + } + #endif /* configISR_STACK_SIZE_WORDS */ + } + #endif /* configASSERT_DEFINED */ + + /* If there is a CLINT then it is ok to use the default implementation + * in this file, otherwise vPortSetupTimerInterrupt() must be implemented to + * configure whichever clock is to be used to generate the tick interrupt. */ + vPortSetupTimerInterrupt(); + + #if ( ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) ) + { + /* Enable mtime and external interrupts. 1<<7 for timer interrupt, + * 1<<11 for external interrupt. _RB_ What happens here when mtime is + * not present as with pulpino? */ + __asm volatile ( "csrs mie, %0" ::"r" ( 0x880 ) ); + } + #endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) */ + + xPortStartFirstTask(); + + /* Should not get here as after calling xPortStartFirstTask() only tasks + * should be executing. */ + return pdFAIL; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented. */ + for( ; ; ) + { + } +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/RISC-V/portASM.S b/portable/GCC/RISC-V/portASM.S new file mode 100644 index 000000000..9d36d78f9 --- /dev/null +++ b/portable/GCC/RISC-V/portASM.S @@ -0,0 +1,406 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * The FreeRTOS kernel's RISC-V port is split between the the code that is + * common across all currently supported RISC-V chips (implementations of the + * RISC-V ISA), and code which tailors the port to a specific RISC-V chip: + * + * + The code that is common to all RISC-V chips is implemented in + * FreeRTOS\Source\portable\GCC\RISC-V\portASM.S. There is only one + * portASM.S file because the same file is used no matter which RISC-V chip is + * in use. + * + * + The code that tailors the kernel's RISC-V port to a specific RISC-V + * chip is implemented in freertos_risc_v_chip_specific_extensions.h. There + * is one freertos_risc_v_chip_specific_extensions.h that can be used with any + * RISC-V chip that both includes a standard CLINT and does not add to the + * base set of RISC-V registers. There are additional + * freertos_risc_v_chip_specific_extensions.h files for RISC-V implementations + * that do not include a standard CLINT or do add to the base set of RISC-V + * registers. + * + * CARE MUST BE TAKEN TO INCLDUE THE CORRECT + * freertos_risc_v_chip_specific_extensions.h HEADER FILE FOR THE CHIP + * IN USE. To include the correct freertos_risc_v_chip_specific_extensions.h + * header file ensure the path to the correct header file is in the assembler's + * include path. + * + * This freertos_risc_v_chip_specific_extensions.h is for use on RISC-V chips + * that include a standard CLINT and do not add to the base set of RISC-V + * registers. + * + */ + +#include "portContext.h" + +/* Check the freertos_risc_v_chip_specific_extensions.h and/or command line +definitions. */ +#if defined( portasmHAS_CLINT ) && defined( portasmHAS_MTIME ) + #error The portasmHAS_CLINT constant has been deprecated. Please replace it with portasmHAS_MTIME. portasmHAS_CLINT and portasmHAS_MTIME cannot both be defined at once. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html +#endif + +#ifdef portasmHAS_CLINT + #warning The portasmHAS_CLINT constant has been deprecated. Please replace it with portasmHAS_MTIME and portasmHAS_SIFIVE_CLINT. For now portasmHAS_MTIME and portasmHAS_SIFIVE_CLINT are derived from portasmHAS_CLINT. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html + #define portasmHAS_MTIME portasmHAS_CLINT + #define portasmHAS_SIFIVE_CLINT portasmHAS_CLINT +#endif + +#ifndef portasmHAS_MTIME + #error freertos_risc_v_chip_specific_extensions.h must define portasmHAS_MTIME to either 1 (MTIME clock present) or 0 (MTIME clock not present). See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html +#endif + +#ifndef portasmHAS_SIFIVE_CLINT + #define portasmHAS_SIFIVE_CLINT 0 +#endif + +.global xPortStartFirstTask +.global pxPortInitialiseStack +.global freertos_risc_v_trap_handler +.global freertos_risc_v_exception_handler +.global freertos_risc_v_interrupt_handler +.global freertos_risc_v_mtimer_interrupt_handler + +.extern vTaskSwitchContext +.extern xTaskIncrementTick +.extern pullMachineTimerCompareRegister +.extern pullNextTime +.extern uxTimerIncrementsForOneTick /* size_t type so 32-bit on 32-bit core and 64-bits on 64-bit core. */ +.extern xTaskReturnAddress + +.weak freertos_risc_v_application_exception_handler +.weak freertos_risc_v_application_interrupt_handler +/*-----------------------------------------------------------*/ + +.macro portUPDATE_MTIMER_COMPARE_REGISTER + load_x a0, pullMachineTimerCompareRegister /* Load address of compare register into a0. */ + load_x a1, pullNextTime /* Load the address of ullNextTime into a1. */ + + #if( __riscv_xlen == 32 ) + + /* Update the 64-bit mtimer compare match value in two 32-bit writes. */ + li a4, -1 + lw a2, 0(a1) /* Load the low word of ullNextTime into a2. */ + lw a3, 4(a1) /* Load the high word of ullNextTime into a3. */ + sw a4, 0(a0) /* Low word no smaller than old value to start with - will be overwritten below. */ + sw a3, 4(a0) /* Store high word of ullNextTime into compare register. No smaller than new value. */ + sw a2, 0(a0) /* Store low word of ullNextTime into compare register. */ + lw t0, uxTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */ + add a4, t0, a2 /* Add the low word of ullNextTime to the timer increments for one tick (assumes timer increment for one tick fits in 32-bits). */ + sltu t1, a4, a2 /* See if the sum of low words overflowed (what about the zero case?). */ + add t2, a3, t1 /* Add overflow to high word of ullNextTime. */ + sw a4, 0(a1) /* Store new low word of ullNextTime. */ + sw t2, 4(a1) /* Store new high word of ullNextTime. */ + + #endif /* __riscv_xlen == 32 */ + + #if( __riscv_xlen == 64 ) + + /* Update the 64-bit mtimer compare match value. */ + ld t2, 0(a1) /* Load ullNextTime into t2. */ + sd t2, 0(a0) /* Store ullNextTime into compare register. */ + ld t0, uxTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */ + add t4, t0, t2 /* Add ullNextTime to the timer increments for one tick. */ + sd t4, 0(a1) /* Store ullNextTime. */ + + #endif /* __riscv_xlen == 64 */ + .endm +/*-----------------------------------------------------------*/ + +/* + * Unlike other ports pxPortInitialiseStack() is written in assembly code as it + * needs access to the portasmADDITIONAL_CONTEXT_SIZE constant. The prototype + * for the function is as per the other ports: + * StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ); + * + * As per the standard RISC-V ABI pxTopOfStack is passed in in a0, pxCode in + * a1, and pvParameters in a2. The new top of stack is passed out in a0. + * + * RISC-V maps registers to ABI names as follows (X1 to X31 integer registers + * for the 'I' profile, X1 to X15 for the 'E' profile, currently I assumed). + * + * Register ABI Name Description Saver + * x0 zero Hard-wired zero - + * x1 ra Return address Caller + * x2 sp Stack pointer Callee + * x3 gp Global pointer - + * x4 tp Thread pointer - + * x5-7 t0-2 Temporaries Caller + * x8 s0/fp Saved register/Frame pointer Callee + * x9 s1 Saved register Callee + * x10-11 a0-1 Function Arguments/return values Caller + * x12-17 a2-7 Function arguments Caller + * x18-27 s2-11 Saved registers Callee + * x28-31 t3-6 Temporaries Caller + * + * The RISC-V context is saved to FreeRTOS tasks in the following stack frame, + * where the global and thread pointers are currently assumed to be constant so + * are not saved: + * + * xCriticalNesting + * x31 + * x30 + * x29 + * x28 + * x27 + * x26 + * x25 + * x24 + * x23 + * x22 + * x21 + * x20 + * x19 + * x18 + * x17 + * x16 + * x15 + * x14 + * x13 + * x12 + * x11 + * pvParameters + * x9 + * x8 + * x7 + * x6 + * x5 + * portTASK_RETURN_ADDRESS + * [FPU registers (when enabled/available) go here] + * [VPU registers (when enabled/available) go here] + * mstatus + * [chip specific registers go here] + * pxCode + */ +pxPortInitialiseStack: + addi a0, a0, -portWORD_SIZE /* Space for critical nesting count. */ + store_x x0, 0(a0) /* Critical nesting count starts at 0 for every task. */ + +#ifdef __riscv_32e + addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x10-x15. */ +#else + addi a0, a0, -(22 * portWORD_SIZE) /* Space for registers x10-x31. */ +#endif + store_x a2, 0(a0) /* Task parameters (pvParameters parameter) goes into register x10/a0 on the stack. */ + + addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x5-x9 + taskReturnAddress (register x1). */ + load_x t0, xTaskReturnAddress + store_x t0, 0(a0) /* Return address onto the stack. */ + + csrr t0, mstatus /* Obtain current mstatus value. */ + andi t0, t0, ~0x8 /* Ensure interrupts are disabled when the stack is restored within an ISR. Required when a task is created after the scheduler has been started, otherwise interrupts would be disabled anyway. */ + addi t1, x0, 0x188 /* Generate the value 0x1880, which are the MPIE=1 and MPP=M_Mode in mstatus. */ + slli t1, t1, 4 + or t0, t0, t1 /* Set MPIE and MPP bits in mstatus value. */ + +#if( configENABLE_FPU == 1 ) + /* Mark the FPU as clean in the mstatus value. */ + li t1, ~MSTATUS_FS_MASK + and t0, t0, t1 + li t1, MSTATUS_FS_CLEAN + or t0, t0, t1 +#endif + +#if( configENABLE_VPU == 1 ) + /* Mark the VPU as clean in the mstatus value. */ + li t1, ~MSTATUS_VS_MASK + and t0, t0, t1 + li t1, MSTATUS_VS_CLEAN + or t0, t0, t1 +#endif + + addi a0, a0, -portWORD_SIZE + store_x t0, 0(a0) /* mstatus onto the stack. */ + + addi t0, x0, portasmADDITIONAL_CONTEXT_SIZE /* The number of chip specific additional registers. */ +chip_specific_stack_frame: /* First add any chip specific registers to the stack frame being created. */ + beq t0, x0, 1f /* No more chip specific registers to save. */ + addi a0, a0, -portWORD_SIZE /* Make space for chip specific register. */ + store_x x0, 0(a0) /* Give the chip specific register an initial value of zero. */ + addi t0, t0, -1 /* Decrement the count of chip specific registers remaining. */ + j chip_specific_stack_frame /* Until no more chip specific registers. */ +1: + + addi a0, a0, -portWORD_SIZE + store_x a1, 0(a0) /* mret value (pxCode parameter) onto the stack. */ + ret +/*-----------------------------------------------------------*/ + +xPortStartFirstTask: + load_x sp, pxCurrentTCB /* Load pxCurrentTCB. */ + load_x sp, 0( sp ) /* Read sp from first TCB member. */ + + load_x x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */ + + portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */ + + load_x x5, 1 * portWORD_SIZE( sp ) /* Initial mstatus into x5 (t0). */ + addi x5, x5, 0x08 /* Set MIE bit so the first task starts with interrupts enabled - required as returns with ret not eret. */ + csrw mstatus, x5 /* Interrupts enabled from here! */ + + load_x x7, 5 * portWORD_SIZE( sp ) /* t2 */ + load_x x8, 6 * portWORD_SIZE( sp ) /* s0/fp */ + load_x x9, 7 * portWORD_SIZE( sp ) /* s1 */ + load_x x10, 8 * portWORD_SIZE( sp ) /* a0 */ + load_x x11, 9 * portWORD_SIZE( sp ) /* a1 */ + load_x x12, 10 * portWORD_SIZE( sp ) /* a2 */ + load_x x13, 11 * portWORD_SIZE( sp ) /* a3 */ + load_x x14, 12 * portWORD_SIZE( sp ) /* a4 */ + load_x x15, 13 * portWORD_SIZE( sp ) /* a5 */ +#ifndef __riscv_32e + load_x x16, 14 * portWORD_SIZE( sp ) /* a6 */ + load_x x17, 15 * portWORD_SIZE( sp ) /* a7 */ + load_x x18, 16 * portWORD_SIZE( sp ) /* s2 */ + load_x x19, 17 * portWORD_SIZE( sp ) /* s3 */ + load_x x20, 18 * portWORD_SIZE( sp ) /* s4 */ + load_x x21, 19 * portWORD_SIZE( sp ) /* s5 */ + load_x x22, 20 * portWORD_SIZE( sp ) /* s6 */ + load_x x23, 21 * portWORD_SIZE( sp ) /* s7 */ + load_x x24, 22 * portWORD_SIZE( sp ) /* s8 */ + load_x x25, 23 * portWORD_SIZE( sp ) /* s9 */ + load_x x26, 24 * portWORD_SIZE( sp ) /* s10 */ + load_x x27, 25 * portWORD_SIZE( sp ) /* s11 */ + load_x x28, 26 * portWORD_SIZE( sp ) /* t3 */ + load_x x29, 27 * portWORD_SIZE( sp ) /* t4 */ + load_x x30, 28 * portWORD_SIZE( sp ) /* t5 */ + load_x x31, 29 * portWORD_SIZE( sp ) /* t6 */ +#endif + + load_x x5, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Obtain xCriticalNesting value for this task from task's stack. */ + load_x x6, pxCriticalNesting /* Load the address of xCriticalNesting into x6. */ + store_x x5, 0( x6 ) /* Restore the critical nesting value for this task. */ + + load_x x5, 3 * portWORD_SIZE( sp ) /* Initial x5 (t0) value. */ + load_x x6, 4 * portWORD_SIZE( sp ) /* Initial x6 (t1) value. */ + + addi sp, sp, portCONTEXT_SIZE + ret +/*-----------------------------------------------------------*/ + +freertos_risc_v_application_exception_handler: + csrr t0, mcause /* For viewing in the debugger only. */ + csrr t1, mepc /* For viewing in the debugger only */ + csrr t2, mstatus /* For viewing in the debugger only */ + j . +/*-----------------------------------------------------------*/ + +freertos_risc_v_application_interrupt_handler: + csrr t0, mcause /* For viewing in the debugger only. */ + csrr t1, mepc /* For viewing in the debugger only */ + csrr t2, mstatus /* For viewing in the debugger only */ + j . +/*-----------------------------------------------------------*/ + +.section .text.freertos_risc_v_exception_handler +freertos_risc_v_exception_handler: + portcontextSAVE_EXCEPTION_CONTEXT + /* a0 now contains mcause. */ + li t0, 11 /* 11 == environment call. */ + bne a0, t0, other_exception /* Not an M environment call, so some other exception. */ + call vTaskSwitchContext + portcontextRESTORE_CONTEXT + +other_exception: + call freertos_risc_v_application_exception_handler + portcontextRESTORE_CONTEXT +/*-----------------------------------------------------------*/ + +.section .text.freertos_risc_v_interrupt_handler +freertos_risc_v_interrupt_handler: + portcontextSAVE_INTERRUPT_CONTEXT + call freertos_risc_v_application_interrupt_handler + portcontextRESTORE_CONTEXT +/*-----------------------------------------------------------*/ + +.section .text.freertos_risc_v_mtimer_interrupt_handler +freertos_risc_v_mtimer_interrupt_handler: + portcontextSAVE_INTERRUPT_CONTEXT + portUPDATE_MTIMER_COMPARE_REGISTER + call xTaskIncrementTick + beqz a0, exit_without_context_switch /* Don't switch context if incrementing tick didn't unblock a task. */ + call vTaskSwitchContext +exit_without_context_switch: + portcontextRESTORE_CONTEXT +/*-----------------------------------------------------------*/ + +.section .text.freertos_risc_v_trap_handler +.align 8 +freertos_risc_v_trap_handler: + portcontextSAVE_CONTEXT_INTERNAL + + csrr a0, mcause + csrr a1, mepc + + bge a0, x0, synchronous_exception + +asynchronous_interrupt: + store_x a1, 0( sp ) /* Asynchronous interrupt so save unmodified exception return address. */ + load_x sp, xISRStackTop /* Switch to ISR stack. */ + j handle_interrupt + +synchronous_exception: + addi a1, a1, 4 /* Synchronous so update exception return address to the instruction after the instruction that generated the exeption. */ + store_x a1, 0( sp ) /* Save updated exception return address. */ + load_x sp, xISRStackTop /* Switch to ISR stack. */ + j handle_exception + +handle_interrupt: +#if( portasmHAS_MTIME != 0 ) + + test_if_mtimer: /* If there is a CLINT then the mtimer is used to generate the tick interrupt. */ + addi t0, x0, 1 + slli t0, t0, __riscv_xlen - 1 /* LSB is already set, shift into MSB. Shift 31 on 32-bit or 63 on 64-bit cores. */ + addi t1, t0, 7 /* 0x8000[]0007 == machine timer interrupt. */ + bne a0, t1, application_interrupt_handler + + portUPDATE_MTIMER_COMPARE_REGISTER + call xTaskIncrementTick + beqz a0, processed_source /* Don't switch context if incrementing tick didn't unblock a task. */ + call vTaskSwitchContext + j processed_source + +#endif /* portasmHAS_MTIME */ + +application_interrupt_handler: + call freertos_risc_v_application_interrupt_handler + j processed_source + +handle_exception: + /* a0 contains mcause. */ + li t0, 11 /* 11 == environment call. */ + bne a0, t0, application_exception_handler /* Not an M environment call, so some other exception. */ + call vTaskSwitchContext + j processed_source + +application_exception_handler: + call freertos_risc_v_application_exception_handler + j processed_source /* No other exceptions handled yet. */ + +processed_source: + portcontextRESTORE_CONTEXT +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/RISC-V/portContext.h b/portable/GCC/RISC-V/portContext.h new file mode 100644 index 000000000..0869a82b6 --- /dev/null +++ b/portable/GCC/RISC-V/portContext.h @@ -0,0 +1,468 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTCONTEXT_H +#define PORTCONTEXT_H + +#ifndef configENABLE_FPU + #define configENABLE_FPU 0 +#endif + +#ifndef configENABLE_VPU + #define configENABLE_VPU 0 +#endif + +#if __riscv_xlen == 64 + #define portWORD_SIZE 8 + #define store_x sd + #define load_x ld +#elif __riscv_xlen == 32 + #define store_x sw + #define load_x lw + #define portWORD_SIZE 4 +#else + #error Assembler did not define __riscv_xlen +#endif + +#include "freertos_risc_v_chip_specific_extensions.h" + +/* Only the standard core registers are stored by default. Any additional + * registers must be saved by the portasmSAVE_ADDITIONAL_REGISTERS and + * portasmRESTORE_ADDITIONAL_REGISTERS macros - which can be defined in a chip + * specific version of freertos_risc_v_chip_specific_extensions.h. See the + * notes at the top of portASM.S file. */ +#ifdef __riscv_32e + #define portCONTEXT_SIZE ( 15 * portWORD_SIZE ) + #define portCRITICAL_NESTING_OFFSET 14 +#else + #define portCONTEXT_SIZE ( 31 * portWORD_SIZE ) + #define portCRITICAL_NESTING_OFFSET 30 +#endif + +#if ( configENABLE_FPU == 1 ) + /* Bit [14:13] in the mstatus encode the status of FPU state which is one of + * the following values: + * 1. Value: 0, Meaning: Off. + * 2. Value: 1, Meaning: Initial. + * 3. Value: 2, Meaning: Clean. + * 4. Value: 3, Meaning: Dirty. + */ + #define MSTATUS_FS_MASK 0x6000 + #define MSTATUS_FS_INITIAL 0x2000 + #define MSTATUS_FS_CLEAN 0x4000 + #define MSTATUS_FS_DIRTY 0x6000 + #define MSTATUS_FS_OFFSET 13 + + #ifdef __riscv_fdiv + #if __riscv_flen == 32 + #define load_f flw + #define store_f fsw + #elif __riscv_flen == 64 + #define load_f fld + #define store_f fsd + #else + #error Assembler did not define __riscv_flen + #endif + + #define portFPU_REG_SIZE ( __riscv_flen / 8 ) + #define portFPU_REG_COUNT 33 /* 32 Floating point registers plus one CSR. */ + #define portFPU_REG_OFFSET( regIndex ) ( ( 2 * portWORD_SIZE ) + ( regIndex * portFPU_REG_SIZE ) ) + #define portFPU_CONTEXT_SIZE ( portFPU_REG_SIZE * portFPU_REG_COUNT ) + #else + #error configENABLE_FPU must not be set to 1 if the hardware does not have FPU + #endif +#endif + +#if ( configENABLE_VPU == 1 ) + /* Bit [10:9] in the mstatus encode the status of VPU state which is one of + * the following values: + * 1. Value: 0, Meaning: Off. + * 2. Value: 1, Meaning: Initial. + * 3. Value: 2, Meaning: Clean. + * 4. Value: 3, Meaning: Dirty. + */ + #define MSTATUS_VS_MASK 0x600 + #define MSTATUS_VS_INITIAL 0x200 + #define MSTATUS_VS_CLEAN 0x400 + #define MSTATUS_VS_DIRTY 0x600 + #define MSTATUS_VS_OFFSET 9 + + #ifndef __riscv_vector + #error configENABLE_VPU must not be set to 1 if the hardware does not have VPU + #endif +#endif +/*-----------------------------------------------------------*/ + +.extern pxCurrentTCB +.extern xISRStackTop +.extern xCriticalNesting +.extern pxCriticalNesting +/*-----------------------------------------------------------*/ + + .macro portcontexSAVE_FPU_CONTEXT +addi sp, sp, -( portFPU_CONTEXT_SIZE ) +/* Store the FPU registers. */ +store_f f0, portFPU_REG_OFFSET( 0 )( sp ) +store_f f1, portFPU_REG_OFFSET( 1 )( sp ) +store_f f2, portFPU_REG_OFFSET( 2 )( sp ) +store_f f3, portFPU_REG_OFFSET( 3 )( sp ) +store_f f4, portFPU_REG_OFFSET( 4 )( sp ) +store_f f5, portFPU_REG_OFFSET( 5 )( sp ) +store_f f6, portFPU_REG_OFFSET( 6 )( sp ) +store_f f7, portFPU_REG_OFFSET( 7 )( sp ) +store_f f8, portFPU_REG_OFFSET( 8 )( sp ) +store_f f9, portFPU_REG_OFFSET( 9 )( sp ) +store_f f10, portFPU_REG_OFFSET( 10 )( sp ) +store_f f11, portFPU_REG_OFFSET( 11 )( sp ) +store_f f12, portFPU_REG_OFFSET( 12 )( sp ) +store_f f13, portFPU_REG_OFFSET( 13 )( sp ) +store_f f14, portFPU_REG_OFFSET( 14 )( sp ) +store_f f15, portFPU_REG_OFFSET( 15 )( sp ) +store_f f16, portFPU_REG_OFFSET( 16 )( sp ) +store_f f17, portFPU_REG_OFFSET( 17 )( sp ) +store_f f18, portFPU_REG_OFFSET( 18 )( sp ) +store_f f19, portFPU_REG_OFFSET( 19 )( sp ) +store_f f20, portFPU_REG_OFFSET( 20 )( sp ) +store_f f21, portFPU_REG_OFFSET( 21 )( sp ) +store_f f22, portFPU_REG_OFFSET( 22 )( sp ) +store_f f23, portFPU_REG_OFFSET( 23 )( sp ) +store_f f24, portFPU_REG_OFFSET( 24 )( sp ) +store_f f25, portFPU_REG_OFFSET( 25 )( sp ) +store_f f26, portFPU_REG_OFFSET( 26 )( sp ) +store_f f27, portFPU_REG_OFFSET( 27 )( sp ) +store_f f28, portFPU_REG_OFFSET( 28 )( sp ) +store_f f29, portFPU_REG_OFFSET( 29 )( sp ) +store_f f30, portFPU_REG_OFFSET( 30 )( sp ) +store_f f31, portFPU_REG_OFFSET( 31 )( sp ) +csrr t0, fcsr +store_x t0, portFPU_REG_OFFSET( 32 )( sp ) + .endm +/*-----------------------------------------------------------*/ + + .macro portcontextRESTORE_FPU_CONTEXT +/* Restore the FPU registers. */ +load_f f0, portFPU_REG_OFFSET( 0 )( sp ) +load_f f1, portFPU_REG_OFFSET( 1 )( sp ) +load_f f2, portFPU_REG_OFFSET( 2 )( sp ) +load_f f3, portFPU_REG_OFFSET( 3 )( sp ) +load_f f4, portFPU_REG_OFFSET( 4 )( sp ) +load_f f5, portFPU_REG_OFFSET( 5 )( sp ) +load_f f6, portFPU_REG_OFFSET( 6 )( sp ) +load_f f7, portFPU_REG_OFFSET( 7 )( sp ) +load_f f8, portFPU_REG_OFFSET( 8 )( sp ) +load_f f9, portFPU_REG_OFFSET( 9 )( sp ) +load_f f10, portFPU_REG_OFFSET( 10 )( sp ) +load_f f11, portFPU_REG_OFFSET( 11 )( sp ) +load_f f12, portFPU_REG_OFFSET( 12 )( sp ) +load_f f13, portFPU_REG_OFFSET( 13 )( sp ) +load_f f14, portFPU_REG_OFFSET( 14 )( sp ) +load_f f15, portFPU_REG_OFFSET( 15 )( sp ) +load_f f16, portFPU_REG_OFFSET( 16 )( sp ) +load_f f17, portFPU_REG_OFFSET( 17 )( sp ) +load_f f18, portFPU_REG_OFFSET( 18 )( sp ) +load_f f19, portFPU_REG_OFFSET( 19 )( sp ) +load_f f20, portFPU_REG_OFFSET( 20 )( sp ) +load_f f21, portFPU_REG_OFFSET( 21 )( sp ) +load_f f22, portFPU_REG_OFFSET( 22 )( sp ) +load_f f23, portFPU_REG_OFFSET( 23 )( sp ) +load_f f24, portFPU_REG_OFFSET( 24 )( sp ) +load_f f25, portFPU_REG_OFFSET( 25 )( sp ) +load_f f26, portFPU_REG_OFFSET( 26 )( sp ) +load_f f27, portFPU_REG_OFFSET( 27 )( sp ) +load_f f28, portFPU_REG_OFFSET( 28 )( sp ) +load_f f29, portFPU_REG_OFFSET( 29 )( sp ) +load_f f30, portFPU_REG_OFFSET( 30 )( sp ) +load_f f31, portFPU_REG_OFFSET( 31 )( sp ) +load_x t0, portFPU_REG_OFFSET( 32 )( sp ) +csrw fcsr, t0 +addi sp, sp, ( portFPU_CONTEXT_SIZE ) + .endm +/*-----------------------------------------------------------*/ + + .macro portcontexSAVE_VPU_CONTEXT +/* Un-reserve the space reserved for mstatus and epc. */ +add sp, sp, ( 2 * portWORD_SIZE ) + +csrr t0, vlenb /* t0 = vlenb. vlenb is the length of each vector register in bytes. */ +slli t0, t0, 3 /* t0 = vlenb * 8. t0 now contains the space required to store 8 vector registers. */ +neg t0, t0 + +/* Store the vector registers in group of 8. */ +add sp, sp, t0 +vs8r.v v24, (sp) /* Store v24-v31. */ +add sp, sp, t0 +vs8r.v v16, (sp) /* Store v16-v23. */ +add sp, sp, t0 +vs8r.v v8, (sp) /* Store v8-v15. */ +add sp, sp, t0 +vs8r.v v0, (sp) /* Store v0-v7. */ + +/* Store the VPU CSRs. */ +addi sp, sp, -( 4 * portWORD_SIZE ) +csrr t0, vstart +store_x t0, 0 * portWORD_SIZE( sp ) +csrr t0, vcsr +store_x t0, 1 * portWORD_SIZE( sp ) +csrr t0, vl +store_x t0, 2 * portWORD_SIZE( sp ) +csrr t0, vtype +store_x t0, 3 * portWORD_SIZE( sp ) + +/* Re-reserve the space for mstatus and epc. */ +add sp, sp, -( 2 * portWORD_SIZE ) + .endm +/*-----------------------------------------------------------*/ + + .macro portcontextRESTORE_VPU_CONTEXT +/* Un-reserve the space reserved for mstatus and epc. */ +add sp, sp, ( 2 * portWORD_SIZE ) + +/* Restore the VPU CSRs. */ +load_x t0, 0 * portWORD_SIZE( sp ) +csrw vstart, t0 +load_x t0, 1 * portWORD_SIZE( sp ) +csrw vcsr, t0 +load_x t0, 2 * portWORD_SIZE( sp ) +load_x t1, 3 * portWORD_SIZE( sp ) +vsetvl x0, t0, t1 /* vlen and vtype can only be updated by using vset*vl* instructions. */ +addi sp, sp, ( 4 * portWORD_SIZE ) + +csrr t0, vlenb /* t0 = vlenb. vlenb is the length of each vector register in bytes. */ +slli t0, t0, 3 /* t0 = vlenb * 8. t0 now contains the space required to store 8 vector registers. */ + +/* Restore the vector registers. */ +vl8r.v v0, (sp) /* Restore v0-v7. */ +add sp, sp, t0 +vl8r.v v8, (sp) /* Restore v8-v15. */ +add sp, sp, t0 +vl8r.v v16, (sp) /* Restore v16-v23. */ +add sp, sp, t0 +vl8r.v v24, (sp) /* Restore v23-v31. */ +add sp, sp, t0 + +/* Re-reserve the space for mstatus and epc. */ +add sp, sp, -( 2 * portWORD_SIZE ) + .endm +/*-----------------------------------------------------------*/ + + .macro portcontextSAVE_CONTEXT_INTERNAL +addi sp, sp, -portCONTEXT_SIZE +store_x x1, 2 * portWORD_SIZE( sp ) +store_x x5, 3 * portWORD_SIZE( sp ) +store_x x6, 4 * portWORD_SIZE( sp ) +store_x x7, 5 * portWORD_SIZE( sp ) +store_x x8, 6 * portWORD_SIZE( sp ) +store_x x9, 7 * portWORD_SIZE( sp ) +store_x x10, 8 * portWORD_SIZE( sp ) +store_x x11, 9 * portWORD_SIZE( sp ) +store_x x12, 10 * portWORD_SIZE( sp ) +store_x x13, 11 * portWORD_SIZE( sp ) +store_x x14, 12 * portWORD_SIZE( sp ) +store_x x15, 13 * portWORD_SIZE( sp ) +#ifndef __riscv_32e + store_x x16, 14 * portWORD_SIZE( sp ) + store_x x17, 15 * portWORD_SIZE( sp ) + store_x x18, 16 * portWORD_SIZE( sp ) + store_x x19, 17 * portWORD_SIZE( sp ) + store_x x20, 18 * portWORD_SIZE( sp ) + store_x x21, 19 * portWORD_SIZE( sp ) + store_x x22, 20 * portWORD_SIZE( sp ) + store_x x23, 21 * portWORD_SIZE( sp ) + store_x x24, 22 * portWORD_SIZE( sp ) + store_x x25, 23 * portWORD_SIZE( sp ) + store_x x26, 24 * portWORD_SIZE( sp ) + store_x x27, 25 * portWORD_SIZE( sp ) + store_x x28, 26 * portWORD_SIZE( sp ) + store_x x29, 27 * portWORD_SIZE( sp ) + store_x x30, 28 * portWORD_SIZE( sp ) + store_x x31, 29 * portWORD_SIZE( sp ) +#endif /* ifndef __riscv_32e */ + +load_x t0, xCriticalNesting /* Load the value of xCriticalNesting into t0. */ +store_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Store the critical nesting value to the stack. */ + +#if( configENABLE_FPU == 1 ) + csrr t0, mstatus + srl t1, t0, MSTATUS_FS_OFFSET + andi t1, t1, 3 + addi t2, x0, 3 + bne t1, t2, 1f /* If FPU status is not dirty, do not save FPU registers. */ + + portcontexSAVE_FPU_CONTEXT +1: +#endif + +#if( configENABLE_VPU == 1 ) + csrr t0, mstatus + srl t1, t0, MSTATUS_VS_OFFSET + andi t1, t1, 3 + addi t2, x0, 3 + bne t1, t2, 2f /* If VPU status is not dirty, do not save VPU registers. */ + + portcontexSAVE_VPU_CONTEXT +2: +#endif + +csrr t0, mstatus +store_x t0, 1 * portWORD_SIZE( sp ) + +portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */ + +#if( configENABLE_FPU == 1 ) + /* Mark the FPU as clean, if it was dirty and we saved FPU registers. */ + srl t1, t0, MSTATUS_FS_OFFSET + andi t1, t1, 3 + addi t2, x0, 3 + bne t1, t2, 3f + + li t1, ~MSTATUS_FS_MASK + and t0, t0, t1 + li t1, MSTATUS_FS_CLEAN + or t0, t0, t1 + csrw mstatus, t0 +3: +#endif + +#if( configENABLE_VPU == 1 ) + /* Mark the VPU as clean, if it was dirty and we saved VPU registers. */ + srl t1, t0, MSTATUS_VS_OFFSET + andi t1, t1, 3 + addi t2, x0, 3 + bne t1, t2, 4f + + li t1, ~MSTATUS_VS_MASK + and t0, t0, t1 + li t1, MSTATUS_VS_CLEAN + or t0, t0, t1 + csrw mstatus, t0 +4: +#endif + +load_x t0, pxCurrentTCB /* Load pxCurrentTCB. */ +store_x sp, 0 ( t0 ) /* Write sp to first TCB member. */ + + .endm +/*-----------------------------------------------------------*/ + + .macro portcontextSAVE_EXCEPTION_CONTEXT +portcontextSAVE_CONTEXT_INTERNAL +csrr a0, mcause +csrr a1, mepc +addi a1, a1, 4 /* Synchronous so update exception return address to the instruction after the instruction that generated the exception. */ +store_x a1, 0 ( sp ) /* Save updated exception return address. */ +load_x sp, xISRStackTop /* Switch to ISR stack. */ + .endm +/*-----------------------------------------------------------*/ + + .macro portcontextSAVE_INTERRUPT_CONTEXT +portcontextSAVE_CONTEXT_INTERNAL +csrr a0, mcause +csrr a1, mepc +store_x a1, 0 ( sp ) /* Asynchronous interrupt so save unmodified exception return address. */ +load_x sp, xISRStackTop /* Switch to ISR stack. */ + .endm +/*-----------------------------------------------------------*/ + + .macro portcontextRESTORE_CONTEXT +load_x t1, pxCurrentTCB /* Load pxCurrentTCB. */ +load_x sp, 0 ( t1 ) /* Read sp from first TCB member. */ + +/* Load mepc with the address of the instruction in the task to run next. */ +load_x t0, 0 ( sp ) +csrw mepc, t0 + +/* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */ +portasmRESTORE_ADDITIONAL_REGISTERS + +/* Restore mstatus register. It is important to use t3 (and not t0) here as t3 + * is not clobbered by portcontextRESTORE_VPU_CONTEXT and + * portcontextRESTORE_FPU_CONTEXT. */ +load_x t3, 1 * portWORD_SIZE( sp ) +csrw mstatus, t3 + +#if( configENABLE_VPU == 1 ) + srl t1, t3, MSTATUS_VS_OFFSET + andi t1, t1, 3 + addi t2, x0, 3 + bne t1, t2, 5f /* If VPU status is not dirty, do not restore VPU registers. */ + + portcontextRESTORE_VPU_CONTEXT +5: +#endif /* ifdef portasmSTORE_VPU_CONTEXT */ + +#if( configENABLE_FPU == 1 ) + srl t1, t3, MSTATUS_FS_OFFSET + andi t1, t1, 3 + addi t2, x0, 3 + bne t1, t2, 6f /* If FPU status is not dirty, do not restore FPU registers. */ + + portcontextRESTORE_FPU_CONTEXT +6: +#endif /* ifdef portasmSTORE_FPU_CONTEXT */ + +load_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Obtain xCriticalNesting value for this task from task's stack. */ +load_x t1, pxCriticalNesting /* Load the address of xCriticalNesting into t1. */ +store_x t0, 0 ( t1 ) /* Restore the critical nesting value for this task. */ + +load_x x1, 2 * portWORD_SIZE( sp ) +load_x x5, 3 * portWORD_SIZE( sp ) +load_x x6, 4 * portWORD_SIZE( sp ) +load_x x7, 5 * portWORD_SIZE( sp ) +load_x x8, 6 * portWORD_SIZE( sp ) +load_x x9, 7 * portWORD_SIZE( sp ) +load_x x10, 8 * portWORD_SIZE( sp ) +load_x x11, 9 * portWORD_SIZE( sp ) +load_x x12, 10 * portWORD_SIZE( sp ) +load_x x13, 11 * portWORD_SIZE( sp ) +load_x x14, 12 * portWORD_SIZE( sp ) +load_x x15, 13 * portWORD_SIZE( sp ) +#ifndef __riscv_32e + load_x x16, 14 * portWORD_SIZE( sp ) + load_x x17, 15 * portWORD_SIZE( sp ) + load_x x18, 16 * portWORD_SIZE( sp ) + load_x x19, 17 * portWORD_SIZE( sp ) + load_x x20, 18 * portWORD_SIZE( sp ) + load_x x21, 19 * portWORD_SIZE( sp ) + load_x x22, 20 * portWORD_SIZE( sp ) + load_x x23, 21 * portWORD_SIZE( sp ) + load_x x24, 22 * portWORD_SIZE( sp ) + load_x x25, 23 * portWORD_SIZE( sp ) + load_x x26, 24 * portWORD_SIZE( sp ) + load_x x27, 25 * portWORD_SIZE( sp ) + load_x x28, 26 * portWORD_SIZE( sp ) + load_x x29, 27 * portWORD_SIZE( sp ) + load_x x30, 28 * portWORD_SIZE( sp ) + load_x x31, 29 * portWORD_SIZE( sp ) +#endif /* ifndef __riscv_32e */ +addi sp, sp, portCONTEXT_SIZE + +mret + .endm +/*-----------------------------------------------------------*/ + +#endif /* PORTCONTEXT_H */ diff --git a/portable/GCC/RISC-V/portmacro.h b/portable/GCC/RISC-V/portmacro.h new file mode 100644 index 000000000..a516a2467 --- /dev/null +++ b/portable/GCC/RISC-V/portmacro.h @@ -0,0 +1,206 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#if __riscv_xlen == 64 + #define portSTACK_TYPE uint64_t + #define portBASE_TYPE int64_t + #define portUBASE_TYPE uint64_t + #define portMAX_DELAY ( TickType_t ) 0xffffffffffffffffUL + #define portPOINTER_SIZE_TYPE uint64_t +#elif __riscv_xlen == 32 + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE int32_t + #define portUBASE_TYPE uint32_t + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#else /* if __riscv_xlen == 64 */ + #error "Assembler did not define __riscv_xlen" +#endif /* if __riscv_xlen == 64 */ + +typedef portSTACK_TYPE StackType_t; +typedef portBASE_TYPE BaseType_t; +typedef portUBASE_TYPE UBaseType_t; +typedef portUBASE_TYPE TickType_t; + +/* Legacy type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ +#define portTICK_TYPE_IS_ATOMIC 1 +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#ifdef __riscv_32e + #define portBYTE_ALIGNMENT 8 /* RV32E uses RISC-V EABI with reduced stack alignment requirements */ +#else + #define portBYTE_ALIGNMENT 16 +#endif +/*-----------------------------------------------------------*/ + +/* Scheduler utilities. */ +extern void vTaskSwitchContext( void ); +#define portYIELD() __asm volatile ( "ecall" ); +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + vTaskSwitchContext(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +#define portCRITICAL_NESTING_IN_TCB 0 + +#define portDISABLE_INTERRUPTS() __asm volatile ( "csrc mstatus, 8" ) +#define portENABLE_INTERRUPTS() __asm volatile ( "csrs mstatus, 8" ) + +extern size_t xCriticalNesting; +#define portENTER_CRITICAL() \ + { \ + portDISABLE_INTERRUPTS(); \ + xCriticalNesting++; \ + } + +#define portEXIT_CRITICAL() \ + { \ + xCriticalNesting--; \ + if( xCriticalNesting == 0 ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } + +/*-----------------------------------------------------------*/ + +/* Architecture specific optimisations. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice." + #endif + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - __builtin_clz( uxReadyPriorities ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not necessary for to use this port. They are defined so the common demo + * files (which build with all the ports) will build. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/*-----------------------------------------------------------*/ + +#define portNOP() __asm volatile ( " nop " ) +#define portINLINE __inline + +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif + +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* configCLINT_BASE_ADDRESS is a legacy definition that was replaced by the + * configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS definitions. For + * backward compatibility derive the newer definitions from the old if the old + * definition is found. */ +#if defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS ) && ( configCLINT_BASE_ADDRESS == 0 ) + +/* Legacy case where configCLINT_BASE_ADDRESS was defined as 0 to indicate + * there was no CLINT. Equivalent now is to set the MTIME and MTIMECMP + * addresses to 0. */ + #define configMTIME_BASE_ADDRESS ( 0 ) + #define configMTIMECMP_BASE_ADDRESS ( 0 ) +#elif defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS ) + +/* Legacy case where configCLINT_BASE_ADDRESS was set to the base address of + * the CLINT. Equivalent now is to derive the MTIME and MTIMECMP addresses + * from the CLINT address. */ + #define configMTIME_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0xBFF8UL ) + #define configMTIMECMP_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0x4000UL ) +#elif !defined( configMTIME_BASE_ADDRESS ) || !defined( configMTIMECMP_BASE_ADDRESS ) + #error "configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. Set them to zero if there is no MTIME (machine time) clock. See www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html" +#endif /* if defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS ) && ( configCLINT_BASE_ADDRESS == 0 ) */ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/RISC-V/readme.txt b/portable/GCC/RISC-V/readme.txt new file mode 100644 index 000000000..3e83157d7 --- /dev/null +++ b/portable/GCC/RISC-V/readme.txt @@ -0,0 +1,23 @@ +/* + * The FreeRTOS kernel's RISC-V port is split between the the code that is + * common across all currently supported RISC-V chips (implementations of the + * RISC-V ISA), and code that tailors the port to a specific RISC-V chip: + * + * + FreeRTOS\Source\portable\GCC\RISC-V\portASM.S contains the code that + * is common to all currently supported RISC-V chips. There is only one + * portASM.S file because the same file is built for all RISC-V target chips. + * + * + Header files called freertos_risc_v_chip_specific_extensions.h contain the + * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V + * chip. There are multiple freertos_risc_v_chip_specific_extensions.h files + * as there are multiple RISC-V chip implementations. + * + * !!!NOTE!!! + * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h + * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the + * compiler's!) include path. For example, if the chip in use includes a core + * local interrupter (CLINT) and does not include any chip specific register + * extensions then add the path below to the assembler's include path: + * FreeRTOS\Source\portable\GCC\RISC-V\chip_specific_extensions\RV32I_CLINT_no_extensions + * + */ diff --git a/portable/GCC/RL78/isr_support.h b/portable/GCC/RL78/isr_support.h new file mode 100644 index 000000000..788718089 --- /dev/null +++ b/portable/GCC/RL78/isr_support.h @@ -0,0 +1,127 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Variables used by scheduler */ +.extern _pxCurrentTCB + .extern _usCriticalNesting + +/* + * portSAVE_CONTEXT MACRO + * Saves the context of the general purpose registers, CS and ES (only in far + * memory mode) registers the usCriticalNesting Value and the Stack Pointer + * of the active Task onto the task stack + */ + .macro portSAVE_CONTEXT + +SEL RB0 + +/* Save AX Register to stack. */ +PUSH AX +PUSH HL +/* Save CS register. */ +MOV A, CS +XCH A, X +/* Save ES register. */ +MOV A, ES +PUSH AX +/* Save the remaining general purpose registers from bank 0. */ +PUSH DE +PUSH BC +/* Save the other register banks - only necessary in the GCC port. */ +SEL RB1 +PUSH AX +PUSH BC +PUSH DE +PUSH HL +SEL RB2 +PUSH AX +PUSH BC +PUSH DE +PUSH HL +/* Registers in bank 3 are for ISR use only so don't need saving. */ +SEL RB0 +/* Save the usCriticalNesting value. */ +MOVW AX, !_usCriticalNesting +PUSH AX +/* Save the Stack pointer. */ +MOVW AX, !_pxCurrentTCB +MOVW HL, AX +MOVW AX, SP +MOVW[ HL ], AX +/* Switch stack pointers. */ +movw sp, # _stack /* Set stack pointer */ + + .endm + + +/* + * portRESTORE_CONTEXT MACRO + * Restores the task Stack Pointer then use this to restore usCriticalNesting, + * general purpose registers and the CS and ES (only in far memory mode) + * of the selected task from the task stack + */ + .macro portRESTORE_CONTEXT MACRO +SEL RB0 +/* Restore the Stack pointer. */ +MOVW AX, !_pxCurrentTCB +MOVW HL, AX +MOVW AX, [ HL ] +MOVW SP, AX +/* Restore usCriticalNesting value. */ +POP AX +MOVW !_usCriticalNesting, AX + +/* Restore the alternative register banks - only necessary in the GCC + * port. Register bank 3 is dedicated for interrupts use so is not saved or + * restored. */ +SEL RB2 +POP HL +POP DE +POP BC +POP AX +SEL RB1 +POP HL +POP DE +POP BC +POP AX +SEL RB0 +/* Restore the necessary general purpose registers. */ +POP BC +POP DE +/* Restore the ES register. */ +POP AX +MOV ES, A +/* Restore the CS register. */ +XCH A, X +MOV CS, A +/* Restore general purpose register HL. */ +POP HL +/* Restore AX. */ +POP AX + + .endm diff --git a/portable/GCC/RL78/port.c b/portable/GCC/RL78/port.c new file mode 100644 index 000000000..7dad2b12b --- /dev/null +++ b/portable/GCC/RL78/port.c @@ -0,0 +1,213 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* The critical nesting value is initialised to a non zero value to ensure + * interrupts don't accidentally become enabled before the scheduler is started. */ +#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 ) + +/* Initial PSW value allocated to a newly created task. + * 11000110 + * ||||||||-------------- Fill byte + * |||||||--------------- Carry Flag cleared + * |||||----------------- In-service priority Flags set to low level + * ||||------------------ Register bank Select 0 Flag cleared + * |||------------------- Auxiliary Carry Flag cleared + * ||-------------------- Register bank Select 1 Flag cleared + * |--------------------- Zero Flag set + * ---------------------- Global Interrupt Flag set (enabled) + */ +#define portPSW ( 0xc6UL ) + +/* Each task maintains a count of the critical section nesting depth. Each time + * a critical section is entered the count is incremented. Each time a critical + * section is exited the count is decremented - with interrupts only being + * re-enabled if the count is zero. + * + * usCriticalNesting will get set to zero when the scheduler starts, but must + * not be initialised to zero as that could cause problems during the startup + * sequence. */ +volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING; + +/*-----------------------------------------------------------*/ + +/* + * Sets up the periodic ISR used for the RTOS tick. + */ +__attribute__( ( weak ) ) void vApplicationSetupTimerInterrupt( void ); + +/* + * Starts the scheduler by loading the context of the first task to run. + * (defined in portasm.S). + */ +extern void vPortStartFirstTask( void ); + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See the header file portable.h. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + uint32_t * pulLocal; + + /* Stack type and pointers to the stack type are both 2 bytes. */ + + /* Parameters are passed in on the stack, and written using a 32bit value + * hence a space is left for the second two bytes. */ + pxTopOfStack--; + + /* Write in the parameter value. */ + pulLocal = ( uint32_t * ) pxTopOfStack; + *pulLocal = ( StackType_t ) pvParameters; + pxTopOfStack--; + + /* The return address, leaving space for the first two bytes of the + * 32-bit value. */ + pxTopOfStack--; + pulLocal = ( uint32_t * ) pxTopOfStack; + *pulLocal = ( uint32_t ) 0; + pxTopOfStack--; + + /* The start address / PSW value is also written in as a 32bit value, + * so leave a space for the second two bytes. */ + pxTopOfStack--; + + /* Task function start address combined with the PSW. */ + pulLocal = ( uint32_t * ) pxTopOfStack; + *pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) ); + pxTopOfStack--; + + /* An initial value for the AX register. */ + *pxTopOfStack = ( StackType_t ) 0x1111; + pxTopOfStack--; + + /* An initial value for the HL register. */ + *pxTopOfStack = ( StackType_t ) 0x2222; + pxTopOfStack--; + + /* CS and ES registers. */ + *pxTopOfStack = ( StackType_t ) 0x0F00; + pxTopOfStack--; + + /* The remaining general purpose registers bank 0 (DE and BC) and the other + * two register banks...register bank 3 is dedicated for use by interrupts so + * is not saved as part of the task context. */ + pxTopOfStack -= 10; + + /* Finally the critical section nesting count is set to zero when the task + * first starts. */ + *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING; + + /* Return a pointer to the top of the stack that has been generated so it + * can be stored in the task control block for the task. */ + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Setup the hardware to generate the tick. Interrupts are disabled when + * this function is called. */ + vApplicationSetupTimerInterrupt(); + + /* Restore the context of the first task that is going to run. */ + vPortStartFirstTask(); + + /* Execution should not reach here as the tasks are now running! */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the RL78 port will get stopped. */ +} +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vApplicationSetupTimerInterrupt( void ) +{ + const uint16_t usClockHz = 15000UL; /* Internal clock. */ + const uint16_t usCompareMatch = ( usClockHz / configTICK_RATE_HZ ) + 1UL; + + /* Use the internal 15K clock. */ + OSMC = ( unsigned char ) 0x16; + + #ifdef RTCEN + { + /* Supply the interval timer clock. */ + RTCEN = ( unsigned char ) 1U; + + /* Disable INTIT interrupt. */ + ITMK = ( unsigned char ) 1; + + /* Disable ITMC operation. */ + ITMC = ( unsigned char ) 0x0000; + + /* Clear INIT interrupt. */ + ITIF = ( unsigned char ) 0; + + /* Set interval and enable interrupt operation. */ + ITMC = usCompareMatch | 0x8000U; + + /* Enable INTIT interrupt. */ + ITMK = ( unsigned char ) 0; + } + #endif /* ifdef RTCEN */ + + #ifdef TMKAEN + { + /* Supply the interval timer clock. */ + TMKAEN = ( unsigned char ) 1U; + + /* Disable INTIT interrupt. */ + TMKAMK = ( unsigned char ) 1; + + /* Disable ITMC operation. */ + ITMC = ( unsigned char ) 0x0000; + + /* Clear INIT interrupt. */ + TMKAIF = ( unsigned char ) 0; + + /* Set interval and enable interrupt operation. */ + ITMC = usCompareMatch | 0x8000U; + + /* Enable INTIT interrupt. */ + TMKAMK = ( unsigned char ) 0; + } + #endif /* ifdef TMKAEN */ +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/RL78/portasm.S b/portable/GCC/RL78/portasm.S new file mode 100644 index 000000000..2f24db972 --- /dev/null +++ b/portable/GCC/RL78/portasm.S @@ -0,0 +1,80 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include "FreeRTOSConfig.h" +#include "ISR_Support.h" + + .global _vPortYield + .global _vPortStartFirstTask + .global _vPortTickISR + + .extern _vTaskSwitchContext + .extern _xTaskIncrementTick + + .text + .align 2 + +/* FreeRTOS yield handler. This is installed as the BRK software interrupt +handler. */ +_vPortYield: + /* Save the context of the current task. */ + portSAVE_CONTEXT + /* Call the scheduler to select the next task. */ + call !!_vTaskSwitchContext + /* Restore the context of the next task to run. */ + portRESTORE_CONTEXT + retb + + +/* Starts the scheduler by restoring the context of the task that will execute +first. */ + .align 2 +_vPortStartFirstTask: + /* Restore the context of whichever task will execute first. */ + portRESTORE_CONTEXT + /* An interrupt stack frame is used so the task is started using RETI. */ + reti + +/* FreeRTOS tick handler. This is installed as the interval timer interrupt +handler. */ + .align 2 +_vPortTickISR: + + /* Save the context of the currently executing task. */ + portSAVE_CONTEXT + /* Call the RTOS tick function. */ + call !!_xTaskIncrementTick +#if configUSE_PREEMPTION == 1 + /* Select the next task to run. */ + call !!_vTaskSwitchContext +#endif + /* Retore the context of whichever task will run next. */ + portRESTORE_CONTEXT + reti + + .end diff --git a/portable/GCC/RL78/portmacro.h b/portable/GCC/RL78/portmacro.h new file mode 100644 index 000000000..730cf50a3 --- /dev/null +++ b/portable/GCC/RL78/portmacro.h @@ -0,0 +1,134 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ + +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint16_t +#define portBASE_TYPE short +#define portPOINTER_SIZE_TYPE uint16_t + +typedef portSTACK_TYPE StackType_t; +typedef short BaseType_t; +typedef unsigned short UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Interrupt control macros. */ +#define portDISABLE_INTERRUPTS() __asm volatile ( "DI" ) +#define portENABLE_INTERRUPTS() __asm volatile ( "EI" ) +/*-----------------------------------------------------------*/ + +/* Critical section control macros. */ +#define portNO_CRITICAL_SECTION_NESTING ( ( unsigned short ) 0 ) + +#define portENTER_CRITICAL() \ + { \ + extern volatile uint16_t usCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + \ + /* Now that interrupts are disabled, ulCriticalNesting can be accessed */ \ + /* directly. Increment ulCriticalNesting to keep a count of how many */ \ + /* times portENTER_CRITICAL() has been called. */ \ + usCriticalNesting++; \ + } + +#define portEXIT_CRITICAL() \ + { \ + extern volatile uint16_t usCriticalNesting; \ + \ + if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ + { \ + /* Decrement the nesting count as we are leaving a critical section. */ \ + usCriticalNesting--; \ + \ + /* If the nesting level has reached zero then interrupts should be */ \ + /* re-enabled. */ \ + if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } \ + } +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +#define portYIELD() __asm volatile ( "BRK" ) +#ifndef configREQUIRE_ASM_ISR_WRAPPER + #define configREQUIRE_ASM_ISR_WRAPPER 1 +#endif +#if( configREQUIRE_ASM_ISR_WRAPPER == 1 ) + /* You must implement an assembly ISR wrapper (see the below for details) if you need an ISR to cause a context switch. + * https://www.freertos.org/Documentation/02-Kernel/03-Supported-devices/04-Demos/Renesas/RTOS_RL78_IAR_Demos#writing-interrupt-service-routines */ + #define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) do { if( xHigherPriorityTaskWoken != pdFALSE ) vTaskSwitchContext(); } while( 0 ) +#else + /* You must not implement an assembly ISR wrapper even if you need an ISR to cause a context switch. + * The portYIELD, which is similar to role of an assembly ISR wrapper, runs only when a context switch is required. */ + #define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) do { if( xHigherPriorityTaskWoken != pdFALSE ) portYIELD(); } while( 0 ) +#endif +#define portNOP() __asm volatile ( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 2 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/RX100/port.c b/portable/GCC/RX100/port.c new file mode 100644 index 000000000..854587d44 --- /dev/null +++ b/portable/GCC/RX100/port.c @@ -0,0 +1,714 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the SH2A port. +*----------------------------------------------------------*/ + +/* Standard C includes. */ +#include "limits.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Library includes. */ +#include "string.h" + +/* Hardware specifics. */ +#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 ) + + #include "platform.h" + +#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + + #include "iodefine.h" + +#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ +/*-----------------------------------------------------------*/ + +/* Tasks should start with interrupts enabled and in Supervisor mode, therefore + * PSW is set with U and I set, and PM and IPL clear. */ +#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) + +/* The peripheral clock is divided by this value before being supplying the + * CMT. */ +#if ( configUSE_TICKLESS_IDLE == 0 ) + /* If tickless idle is not used then the divisor can be fixed. */ + #define portCLOCK_DIVISOR 8UL +#elif ( configPERIPHERAL_CLOCK_HZ >= 12000000 ) + #define portCLOCK_DIVISOR 512UL +#elif ( configPERIPHERAL_CLOCK_HZ >= 6000000 ) + #define portCLOCK_DIVISOR 128UL +#elif ( configPERIPHERAL_CLOCK_HZ >= 1000000 ) + #define portCLOCK_DIVISOR 32UL +#else + #define portCLOCK_DIVISOR 8UL +#endif + +/* These macros allow a critical section to be added around the call to + * xTaskIncrementTick(), which is only ever called from interrupts at the kernel + * priority - ie a known priority. Therefore these local macros are a slight + * optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros, + * which would require the old IPL to be read first and stored in a local variable. */ +#define portDISABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) +#define portENABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i" ( configKERNEL_INTERRUPT_PRIORITY ) ) + +/* Keys required to lock and unlock access to certain system registers + * respectively. */ +#define portUNLOCK_KEY 0xA50B +#define portLOCK_KEY 0xA500 + +/*-----------------------------------------------------------*/ + +/* + * Function to start the first task executing - written in asm code as direct + * access to registers is required. + */ +static void prvStartFirstTask( void ) __attribute__( ( naked ) ); + +/* + * Software interrupt handler. Performs the actual context switch (saving and + * restoring of registers). Written in asm code as direct register access is + * required. + */ +#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 ) + + R_BSP_PRAGMA_INTERRUPT( vPortSoftwareInterruptISR, VECT( ICU, SWINT ) ) + R_BSP_ATTRIB_INTERRUPT void vPortSoftwareInterruptISR( void ) __attribute__( ( naked ) ); + +#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + + void vPortSoftwareInterruptISR( void ) __attribute__( ( naked ) ); + +#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + +/* + * The tick ISR handler. The peripheral used is configured by the application + * via a hook/callback function. + */ +#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 ) + + R_BSP_PRAGMA_INTERRUPT( vPortTickISR, _VECT( configTICK_VECTOR ) ) + R_BSP_ATTRIB_INTERRUPT void vPortTickISR( void ); /* Do not add __attribute__( ( interrupt ) ). */ + +#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + + void vPortTickISR( void ) __attribute__( ( interrupt ) ); + +#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + +/* + * Sets up the periodic ISR used for the RTOS tick using the CMT. + * The application writer can define configSETUP_TICK_INTERRUPT() (in + * FreeRTOSConfig.h) such that their own tick interrupt configuration is used + * in place of prvSetupTimerInterrupt(). + */ +static void prvSetupTimerInterrupt( void ); +#ifndef configSETUP_TICK_INTERRUPT + +/* The user has not provided their own tick interrupt configuration so use + * the definition in this file (which uses the interval timer). */ + #define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt() +#endif /* configSETUP_TICK_INTERRUPT */ + +/* + * Called after the sleep mode registers have been configured, prvSleep() + * executes the pre and post sleep macros, and actually calls the wait + * instruction. + */ +#if configUSE_TICKLESS_IDLE == 1 + static void prvSleep( TickType_t xExpectedIdleTime ); +#endif /* configUSE_TICKLESS_IDLE */ + +/*-----------------------------------------------------------*/ + +/* Used in the context save and restore code. */ +extern void * pxCurrentTCB; + +/* Calculate how many clock increments make up a single tick period. */ +static const uint32_t ulMatchValueForOneTick = ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ ); + +#if configUSE_TICKLESS_IDLE == 1 + +/* Holds the maximum number of ticks that can be suppressed - which is + * basically how far into the future an interrupt can be generated. Set + * during initialisation. This is the maximum possible value that the + * compare match register can hold divided by ulMatchValueForOneTick. */ + static const TickType_t xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ ); + +/* Flag set from the tick interrupt to allow the sleep processing to know if + * sleep mode was exited because of a tick interrupt, or an interrupt + * generated by something else. */ + static volatile uint32_t ulTickFlag = pdFALSE; + +/* The CMT counter is stopped temporarily each time it is re-programmed. + * The following constant offsets the CMT counter match value by the number of + * CMT counts that would typically be missed while the counter was stopped to + * compensate for the lost time. The large difference between the divided CMT + * clock and the CPU clock means it is likely ulStoppedTimerCompensation will + * equal zero - and be optimised away. */ + static const uint32_t ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) ); + +#endif /* if configUSE_TICKLESS_IDLE == 1 */ + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Offset to end up on 8 byte boundary. */ + pxTopOfStack--; + + /* R0 is not included as it is the stack pointer. */ + *pxTopOfStack = 0x00; + pxTopOfStack--; + *pxTopOfStack = 0x00; + pxTopOfStack--; + *pxTopOfStack = portINITIAL_PSW; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; + + /* When debugging it can be useful if every register is set to a known + * value. Otherwise code space can be saved by just setting the registers + * that need to be set. */ + #ifdef USE_FULL_REGISTER_INITIALISATION + { + pxTopOfStack--; + *pxTopOfStack = 0x12345678; /* r15. */ + pxTopOfStack--; + *pxTopOfStack = 0xaaaabbbb; + pxTopOfStack--; + *pxTopOfStack = 0xdddddddd; + pxTopOfStack--; + *pxTopOfStack = 0xcccccccc; + pxTopOfStack--; + *pxTopOfStack = 0xbbbbbbbb; + pxTopOfStack--; + *pxTopOfStack = 0xaaaaaaaa; + pxTopOfStack--; + *pxTopOfStack = 0x99999999; + pxTopOfStack--; + *pxTopOfStack = 0x88888888; + pxTopOfStack--; + *pxTopOfStack = 0x77777777; + pxTopOfStack--; + *pxTopOfStack = 0x66666666; + pxTopOfStack--; + *pxTopOfStack = 0x55555555; + pxTopOfStack--; + *pxTopOfStack = 0x44444444; + pxTopOfStack--; + *pxTopOfStack = 0x33333333; + pxTopOfStack--; + *pxTopOfStack = 0x22222222; + pxTopOfStack--; + } + #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ + { + /* Leave space for the registers that will get popped from the stack + * when the task first starts executing. */ + pxTopOfStack -= 15; + } + #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */ + + *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = 0x12345678; /* Accumulator. */ + pxTopOfStack--; + *pxTopOfStack = 0x87654321; /* Accumulator. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Use pxCurrentTCB just so it does not get optimised away. */ + if( pxCurrentTCB != NULL ) + { + /* Call an application function to set up the timer that will generate + * the tick interrupt. This way the application can decide which + * peripheral to use. If tickless mode is used then the default + * implementation defined in this file (which uses CMT0) should not be + * overridden. */ + configSETUP_TICK_INTERRUPT(); + + /* Enable the software interrupt. */ + _IEN( _ICU_SWINT ) = 1; + + /* Ensure the software interrupt is clear. */ + _IR( _ICU_SWINT ) = 0; + + /* Ensure the software interrupt is set to the kernel priority. */ + _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the first task. */ + prvStartFirstTask(); + } + + /* Execution should not reach here as the tasks are now running! + * prvSetupTimerInterrupt() is called here to prevent the compiler outputting + * a warning about a statically declared function not being referenced in the + * case that the application writer has provided their own tick interrupt + * configuration routine (and defined configSETUP_TICK_INTERRUPT() such that + * their own routine will be called in place of prvSetupTimerInterrupt()). */ + prvSetupTimerInterrupt(); + + /* Should not get here. */ + return pdFAIL; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( pxCurrentTCB == NULL ); +} +/*-----------------------------------------------------------*/ + +static void prvStartFirstTask( void ) +{ + __asm volatile + ( + + /* When starting the scheduler there is nothing that needs moving to the + * interrupt stack because the function is not called from an interrupt. + * Just ensure the current stack is the user stack. */ + "SETPSW U \n" \ + + + /* Obtain the location of the stack associated with which ever task + * pxCurrentTCB is currently pointing to. */ + "MOV.L #_pxCurrentTCB, R15 \n" \ + "MOV.L [R15], R15 \n" \ + "MOV.L [R15], R0 \n" \ + + + /* Restore the registers from the stack of the task pointed to by + * pxCurrentTCB. */ + "POP R15 \n" \ + + /* Accumulator low 32 bits. */ + "MVTACLO R15 \n" \ + "POP R15 \n" \ + + /* Accumulator high 32 bits. */ + "MVTACHI R15 \n" \ + + /* R1 to R15 - R0 is not included as it is the SP. */ + "POPM R1-R15 \n" \ + + /* This pops the remaining registers. */ + "RTE \n" \ + "NOP \n" \ + "NOP \n" + ); +} +/*-----------------------------------------------------------*/ + +void vPortSoftwareInterruptISR( void ) +{ + __asm volatile + ( + /* Re-enable interrupts. */ + "SETPSW I \n" \ + + + /* Move the data that was automatically pushed onto the interrupt stack when + * the interrupt occurred from the interrupt stack to the user stack. + * + * R15 is saved before it is clobbered. */ + "PUSH.L R15 \n" \ + + /* Read the user stack pointer. */ + "MVFC USP, R15 \n" \ + + /* Move the address down to the data being moved. */ + "SUB #12, R15 \n" \ + "MVTC R15, USP \n" \ + + /* Copy the data across, R15, then PC, then PSW. */ + "MOV.L [ R0 ], [ R15 ] \n" \ + "MOV.L 4[ R0 ], 4[ R15 ] \n" \ + "MOV.L 8[ R0 ], 8[ R15 ] \n" \ + + /* Move the interrupt stack pointer to its new correct position. */ + "ADD #12, R0 \n" \ + + /* All the rest of the registers are saved directly to the user stack. */ + "SETPSW U \n" \ + + /* Save the rest of the general registers (R15 has been saved already). */ + "PUSHM R1-R14 \n" \ + + /* Save the accumulator. */ + "MVFACHI R15 \n" \ + "PUSH.L R15 \n" \ + + /* Middle word. */ + "MVFACMI R15 \n" \ + + /* Shifted left as it is restored to the low order word. */ + "SHLL #16, R15 \n" \ + "PUSH.L R15 \n" \ + + /* Save the stack pointer to the TCB. */ + "MOV.L #_pxCurrentTCB, R15 \n" \ + "MOV.L [ R15 ], R15 \n" \ + "MOV.L R0, [ R15 ] \n" \ + + + /* Ensure the interrupt mask is set to the syscall priority while the kernel + * structures are being accessed. */ + "MVTIPL %0 \n" \ + + /* Select the next task to run. */ + "BSR.A _vTaskSwitchContext \n" \ + + /* Reset the interrupt mask as no more data structure access is required. */ + "MVTIPL %1 \n" \ + + + /* Load the stack pointer of the task that is now selected as the Running + * state task from its TCB. */ + "MOV.L #_pxCurrentTCB,R15 \n" \ + "MOV.L [ R15 ], R15 \n" \ + "MOV.L [ R15 ], R0 \n" \ + + + /* Restore the context of the new task. The PSW (Program Status Word) and + * PC will be popped by the RTE instruction. */ + "POP R15 \n" \ + "MVTACLO R15 \n" \ + "POP R15 \n" \ + "MVTACHI R15 \n" \ + "POPM R1-R15 \n" \ + "RTE \n" \ + "NOP \n" \ + "NOP " + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ), "i" ( configKERNEL_INTERRUPT_PRIORITY ) + ); +} +/*-----------------------------------------------------------*/ + +void vPortTickISR( void ) +{ + /* Re-enabled interrupts. */ + __asm volatile ( "SETPSW I" ); + + /* Increment the tick, and perform any processing the new tick value + * necessitates. Ensure IPL is at the max syscall value first. */ + portDISABLE_INTERRUPTS_FROM_KERNEL_ISR(); + { + if( xTaskIncrementTick() != pdFALSE ) + { + taskYIELD(); + } + } + portENABLE_INTERRUPTS_FROM_KERNEL_ISR(); + + #if configUSE_TICKLESS_IDLE == 1 + { + /* The CPU woke because of a tick. */ + ulTickFlag = pdTRUE; + + /* If this is the first tick since exiting tickless mode then the CMT + * compare match value needs resetting. */ + CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick; + } + #endif +} +/*-----------------------------------------------------------*/ + +uint32_t ulPortGetIPL( void ) +{ + __asm volatile + ( + "MVFC PSW, R1 \n" \ + "SHLR #24, R1 \n" \ + "RTS " + ); + + /* This will never get executed, but keeps the compiler from complaining. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortSetIPL( uint32_t ulNewIPL ) +{ + __asm volatile + ( + "PUSH R5 \n" \ + "MVFC PSW, R5 \n" \ + "SHLL #24, R1 \n" \ + "AND #-0F000001H, R5 \n" \ + "OR R1, R5 \n" \ + "MVTC R5, PSW \n" \ + "POP R5 \n" \ + "RTS " + ); +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ + /* Unlock. */ + SYSTEM.PRCR.WORD = portUNLOCK_KEY; + + /* Enable CMT0. */ + MSTP( CMT0 ) = 0; + + /* Lock again. */ + SYSTEM.PRCR.WORD = portLOCK_KEY; + + /* Interrupt on compare match. */ + CMT0.CMCR.BIT.CMIE = 1; + + /* Set the compare match value. */ + CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick; + + /* Divide the PCLK. */ + #if portCLOCK_DIVISOR == 512 + { + CMT0.CMCR.BIT.CKS = 3; + } + #elif portCLOCK_DIVISOR == 128 + { + CMT0.CMCR.BIT.CKS = 2; + } + #elif portCLOCK_DIVISOR == 32 + { + CMT0.CMCR.BIT.CKS = 1; + } + #elif portCLOCK_DIVISOR == 8 + { + CMT0.CMCR.BIT.CKS = 0; + } + #else /* if portCLOCK_DIVISOR == 512 */ + { + #error Invalid portCLOCK_DIVISOR setting + } + #endif /* if portCLOCK_DIVISOR == 512 */ + + /* Enable the interrupt... */ + _IEN( _CMT0_CMI0 ) = 1; + + /* ...and set its priority to the application defined kernel priority. */ + _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the timer. */ + CMT.CMSTR0.BIT.STR0 = 1; +} +/*-----------------------------------------------------------*/ + +#if configUSE_TICKLESS_IDLE == 1 + + static void prvSleep( TickType_t xExpectedIdleTime ) + { + /* Allow the application to define some pre-sleep processing. */ + configPRE_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING() + * means the application defined code has already executed the WAIT + * instruction. */ + if( xExpectedIdleTime > 0 ) + { + __asm volatile ( "WAIT" ); + } + + /* Allow the application to define some post sleep processing. */ + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if configUSE_TICKLESS_IDLE == 1 + + void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount; + eSleepModeStatus eSleepAction; + + /* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */ + + /* Make sure the CMT reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Calculate the reload value required to wait xExpectedIdleTime tick + * periods. */ + ulMatchValue = ulMatchValueForOneTick * xExpectedIdleTime; + + if( ulMatchValue > ulStoppedTimerCompensation ) + { + /* Compensate for the fact that the CMT is going to be stopped + * momentarily. */ + ulMatchValue -= ulStoppedTimerCompensation; + } + + /* Stop the CMT momentarily. The time the CMT is stopped for is + * accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + CMT.CMSTR0.BIT.STR0 = 0; + + while( CMT.CMSTR0.BIT.STR0 == 1 ) + { + /* Nothing to do here. */ + } + + /* Critical section using the global interrupt bit as the i bit is + * automatically reset by the WAIT instruction. */ + __asm volatile ( "CLRPSW i" ); + + /* The tick flag is set to false before sleeping. If it is true when + * sleep mode is exited then sleep mode was probably exited because the + * tick was suppressed for the entire xExpectedIdleTime period. */ + ulTickFlag = pdFALSE; + + /* If a context switch is pending then abandon the low power entry as + * the context switch might have been pended by an external interrupt that + * requires processing. */ + eSleepAction = eTaskConfirmSleepModeStatus(); + + if( eSleepAction == eAbortSleep ) + { + /* Restart tick. */ + CMT.CMSTR0.BIT.STR0 = 1; + __asm volatile ( "SETPSW i" ); + } + else if( eSleepAction == eNoTasksWaitingTimeout ) + { + /* Protection off. */ + SYSTEM.PRCR.WORD = portUNLOCK_KEY; + + /* Ready for software standby with all clocks stopped. */ + SYSTEM.SBYCR.BIT.SSBY = 1; + + /* Protection on. */ + SYSTEM.PRCR.WORD = portLOCK_KEY; + + /* Sleep until something happens. Calling prvSleep() will + * automatically reset the i bit in the PSW. */ + prvSleep( xExpectedIdleTime ); + + /* Restart the CMT. */ + CMT.CMSTR0.BIT.STR0 = 1; + } + else + { + /* Protection off. */ + SYSTEM.PRCR.WORD = portUNLOCK_KEY; + + /* Ready for deep sleep mode. */ + SYSTEM.MSTPCRC.BIT.DSLPE = 1; + SYSTEM.MSTPCRA.BIT.MSTPA28 = 1; + SYSTEM.SBYCR.BIT.SSBY = 0; + + /* Protection on. */ + SYSTEM.PRCR.WORD = portLOCK_KEY; + + /* Adjust the match value to take into account that the current + * time slice is already partially complete. */ + ulMatchValue -= ( uint32_t ) CMT0.CMCNT; + CMT0.CMCOR = ( uint16_t ) ulMatchValue; + + /* Restart the CMT to count up to the new match value. */ + CMT0.CMCNT = 0; + CMT.CMSTR0.BIT.STR0 = 1; + + /* Sleep until something happens. Calling prvSleep() will + * automatically reset the i bit in the PSW. */ + prvSleep( xExpectedIdleTime ); + + /* Stop CMT. Again, the time the SysTick is stopped for is + * accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + CMT.CMSTR0.BIT.STR0 = 0; + + while( CMT.CMSTR0.BIT.STR0 == 1 ) + { + /* Nothing to do here. */ + } + + ulCurrentCount = ( uint32_t ) CMT0.CMCNT; + + if( ulTickFlag != pdFALSE ) + { + /* The tick interrupt has already executed, although because + * this function is called with the scheduler suspended the actual + * tick processing will not occur until after this function has + * exited. Reset the match value with whatever remains of this + * tick period. */ + ulMatchValue = ulMatchValueForOneTick - ulCurrentCount; + CMT0.CMCOR = ( uint16_t ) ulMatchValue; + + /* The tick interrupt handler will already have pended the tick + * processing in the kernel. As the pending tick will be + * processed as soon as this function exits, the tick value + * maintained by the tick is stepped forward by one less than the + * time spent sleeping. The actual stepping of the tick appears + * later in this function. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. + * How many complete tick periods passed while the processor was + * sleeping? */ + ulCompleteTickPeriods = ulCurrentCount / ulMatchValueForOneTick; + + /* The match value is set to whatever fraction of a single tick + * period remains. */ + ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick ); + CMT0.CMCOR = ( uint16_t ) ulMatchValue; + } + + /* Restart the CMT so it runs up to the match value. The match value + * will get set to the value required to generate exactly one tick period + * the next time the CMT interrupt executes. */ + CMT0.CMCNT = 0; + CMT.CMSTR0.BIT.STR0 = 1; + + /* Wind the tick forward by the number of tick periods that the CPU + * remained in a low power state. */ + vTaskStepTick( ulCompleteTickPeriods ); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ diff --git a/portable/GCC/RX100/portmacro.h b/portable/GCC/RX100/portmacro.h new file mode 100644 index 000000000..052ee0be3 --- /dev/null +++ b/portable/GCC/RX100/portmacro.h @@ -0,0 +1,158 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* When the FIT configurator or the Smart Configurator is used, platform.h has to be + * used. */ +#ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H + #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0 +#endif + +/* Type definitions - these are a bit legacy and not really used now, other than + * portSTACK_TYPE and portBASE_TYPE. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() __asm volatile ( "NOP" ) + +/* Save clobbered register, set ITU SWINR (at address 0x872E0), read the value + * back to ensure it is set before continuing, then restore the clobbered + * register. */ +#define portYIELD() \ + __asm volatile \ + ( \ + "MOV.L #0x872E0, r5 \n\t" \ + "MOV.B #1, [r5] \n\t" \ + "MOV.L [r5], r5 \n\t" \ + ::: "r5" \ + ) + +#define portYIELD_FROM_ISR( x ) do { if( x != pdFALSE ) { portYIELD(); } } while( 0 ) + +/* These macros should not be called directly, but through the + * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is + * performed if configASSERT() is defined to ensure an assertion handler does not + * inadvertently attempt to lower the IPL when the call to assert was triggered + * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY + * when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API + * functions are those that end in FromISR. FreeRTOS maintains a separate + * interrupt API to ensure API function and interrupt entry is as fast and as + * simple as possible. */ +#define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0" ) +#if ( configASSERT_DEFINED == 1 ) + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) + #define portDISABLE_INTERRUPTS() if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile( "MVTIPL %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) +#else + #define portDISABLE_INTERRUPTS() __asm volatile ( "MVTIPL %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) +#endif + +/* Critical nesting counts are stored in the TCB. */ +#define portCRITICAL_NESTING_IN_TCB ( 1 ) + +/* The critical nesting functions defined within tasks.c. */ +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() + +/* As this port allows interrupt nesting... */ +uint32_t ulPortGetIPL( void ) __attribute__( ( naked ) ); +void vPortSetIPL( uint32_t ulNewIPL ) __attribute__( ( naked ) ); +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus ) + +/* Tickless idle/low power functionality. */ +#if configUSE_TICKLESS_IDLE == 1 + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif +#endif + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/RX100/readme.txt b/portable/GCC/RX100/readme.txt new file mode 100644 index 000000000..8dbc983fd --- /dev/null +++ b/portable/GCC/RX100/readme.txt @@ -0,0 +1,71 @@ +The following table shows which port is recommended to be used. + + +RX MCU Group CPU FPU FPU Port Layer + Core (Single (Double CC-RX GNURX ICCRX (*6) + Type Precision) Precision) + +RX110 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX111 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX113 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX130 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX13T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 + +RX210 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX21A RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX220 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX230,RX231 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23E-A RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23W RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24U RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 + +RX610 RXv1 Yes --- N/A (*4) N/A (*4) N/A (*4) +RX62N,RX621 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX630 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX634 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63N,RX631 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX64M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX65N,RX651 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX66N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX62T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX62G RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX66T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +RX71M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX72M RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +Notes: + +*1: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is not used, please define configSETUP_TICK_INTERRUPT() (in FreeRTOSConfig.h) and provide +the configuration function. Please be aware that port.c is hard coded to use CMT0 though it seems to be +configured to use any CMTn according to the definition of configTICK_VECTOR (in FreeRTOSConfig.h). + +*2: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is used, please modify port.c for the configuration. Please be aware that port.c is +hard coded to use CMT0 though it seems to be configured to use any CMTn according to the definition of +configTICK_VECTOR (in FreeRTOSConfig.h). + +*3: RX100 ports are also available. + +*4: RX600 ports use MVTIPL instruction but RX610 MCUs don't support this instruction. + +*5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h. + +#define configUSE_TASK_DPFPU_SUPPORT 0 + +*6: PriorityDefinitions.h has to be provided for port_asm.s in case of other than RX700v3_DPFPU port. +It contains two definitions of interrupt priority like the following. + +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + + +For more information about Renesas RX MCUs, please visit the following URL: + +https://www.renesas.com/products/microcontrollers-microprocessors/rx.html diff --git a/portable/GCC/RX200/port.c b/portable/GCC/RX200/port.c new file mode 100644 index 000000000..e58c96d13 --- /dev/null +++ b/portable/GCC/RX200/port.c @@ -0,0 +1,445 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the SH2A port. +*----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Library includes. */ +#include "string.h" + +/* Hardware specifics. */ +#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 ) + + #include "platform.h" + +#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + + #include "iodefine.h" + +#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + +/*-----------------------------------------------------------*/ + +/* Tasks should start with interrupts enabled and in Supervisor mode, therefore + * PSW is set with U and I set, and PM and IPL clear. */ +#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) +#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 ) + +/* These macros allow a critical section to be added around the call to + * xTaskIncrementTick(), which is only ever called from interrupts at the kernel + * priority - ie a known priority. Therefore these local macros are a slight + * optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros, + * which would require the old IPL to be read first and stored in a local variable. */ +#define portMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) +#define portUNMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i" ( configKERNEL_INTERRUPT_PRIORITY ) ) + +/*-----------------------------------------------------------*/ + +/* + * Function to start the first task executing - written in asm code as direct + * access to registers is required. + */ +static void prvStartFirstTask( void ) __attribute__( ( naked ) ); + + +/* + * Software interrupt handler. Performs the actual context switch (saving and + * restoring of registers). Written in asm code as direct register access is + * required. + */ +#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 ) + + R_BSP_PRAGMA_INTERRUPT( vSoftwareInterruptISR, VECT( ICU, SWINT ) ) + R_BSP_ATTRIB_INTERRUPT void vSoftwareInterruptISR( void ) __attribute__( ( naked ) ); + +#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + + void vSoftwareInterruptISR( void ) __attribute__( ( naked ) ); + +#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + +/* + * The tick ISR handler. The peripheral used is configured by the application + * via a hook/callback function. + */ +#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 ) + + R_BSP_PRAGMA_INTERRUPT( vTickISR, _VECT( configTICK_VECTOR ) ) + R_BSP_ATTRIB_INTERRUPT void vTickISR( void ); /* Do not add __attribute__( ( interrupt ) ). */ + +#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + + void vTickISR( void ) __attribute__( ( interrupt ) ); + +#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + +/*-----------------------------------------------------------*/ + +extern void * pxCurrentTCB; + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* R0 is not included as it is the stack pointer. */ + + *pxTopOfStack = 0x00; + pxTopOfStack--; + *pxTopOfStack = portINITIAL_PSW; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; + + /* When debugging it can be useful if every register is set to a known + * value. Otherwise code space can be saved by just setting the registers + * that need to be set. */ + #ifdef USE_FULL_REGISTER_INITIALISATION + { + pxTopOfStack--; + *pxTopOfStack = 0xffffffff; /* r15. */ + pxTopOfStack--; + *pxTopOfStack = 0xeeeeeeee; + pxTopOfStack--; + *pxTopOfStack = 0xdddddddd; + pxTopOfStack--; + *pxTopOfStack = 0xcccccccc; + pxTopOfStack--; + *pxTopOfStack = 0xbbbbbbbb; + pxTopOfStack--; + *pxTopOfStack = 0xaaaaaaaa; + pxTopOfStack--; + *pxTopOfStack = 0x99999999; + pxTopOfStack--; + *pxTopOfStack = 0x88888888; + pxTopOfStack--; + *pxTopOfStack = 0x77777777; + pxTopOfStack--; + *pxTopOfStack = 0x66666666; + pxTopOfStack--; + *pxTopOfStack = 0x55555555; + pxTopOfStack--; + *pxTopOfStack = 0x44444444; + pxTopOfStack--; + *pxTopOfStack = 0x33333333; + pxTopOfStack--; + *pxTopOfStack = 0x22222222; + pxTopOfStack--; + } + #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ + { + pxTopOfStack -= 15; + } + #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */ + + *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_FPSW; + pxTopOfStack--; + *pxTopOfStack = 0x11111111; /* Accumulator 0. */ + pxTopOfStack--; + *pxTopOfStack = 0x22222222; /* Accumulator 0. */ + pxTopOfStack--; + *pxTopOfStack = 0x33333333; /* Accumulator 0. */ + pxTopOfStack--; + *pxTopOfStack = 0x44444444; /* Accumulator 1. */ + pxTopOfStack--; + *pxTopOfStack = 0x55555555; /* Accumulator 1. */ + pxTopOfStack--; + *pxTopOfStack = 0x66666666; /* Accumulator 1. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + extern void vApplicationSetupTimerInterrupt( void ); + + /* Use pxCurrentTCB just so it does not get optimised away. */ + if( pxCurrentTCB != NULL ) + { + /* Call an application function to set up the timer that will generate the + * tick interrupt. This way the application can decide which peripheral to + * use. A demo application is provided to show a suitable example. */ + vApplicationSetupTimerInterrupt(); + + /* Enable the software interrupt. */ + _IEN( _ICU_SWINT ) = 1; + + /* Ensure the software interrupt is clear. */ + _IR( _ICU_SWINT ) = 0; + + /* Ensure the software interrupt is set to the kernel priority. */ + _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the first task. */ + prvStartFirstTask(); + } + + /* Should not get here. */ + return pdFAIL; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( pxCurrentTCB == NULL ); +} +/*-----------------------------------------------------------*/ + +static void prvStartFirstTask( void ) +{ + __asm volatile + ( + + /* When starting the scheduler there is nothing that needs moving to the + * interrupt stack because the function is not called from an interrupt. + * Just ensure the current stack is the user stack. */ + "SETPSW U \n" \ + + + /* Obtain the location of the stack associated with which ever task + * pxCurrentTCB is currently pointing to. */ + "MOV.L #_pxCurrentTCB, R15 \n" \ + "MOV.L [R15], R15 \n" \ + "MOV.L [R15], R0 \n" \ + + + /* Restore the registers from the stack of the task pointed to by + * pxCurrentTCB. */ + "POP R15 \n" \ + + /* Accumulator low 32 bits. */ + "MVTACLO R15, A0 \n" \ + "POP R15 \n" \ + + /* Accumulator high 32 bits. */ + "MVTACHI R15, A0 \n" \ + "POP R15 \n" \ + + /* Accumulator guard. */ + "MVTACGU R15, A0 \n" \ + "POP R15 \n" \ + + /* Accumulator low 32 bits. */ + "MVTACLO R15, A1 \n" \ + "POP R15 \n" \ + + /* Accumulator high 32 bits. */ + "MVTACHI R15, A1 \n" \ + "POP R15 \n" \ + + /* Accumulator guard. */ + "MVTACGU R15, A1 \n" \ + "POP R15 \n" \ + + /* Floating point status word. */ + "MVTC R15, FPSW \n" \ + + /* R1 to R15 - R0 is not included as it is the SP. */ + "POPM R1-R15 \n" \ + + /* This pops the remaining registers. */ + "RTE \n" \ + "NOP \n" \ + "NOP \n" + ); +} +/*-----------------------------------------------------------*/ + +void vSoftwareInterruptISR( void ) +{ + __asm volatile + ( + /* Re-enable interrupts. */ + "SETPSW I \n" \ + + + /* Move the data that was automatically pushed onto the interrupt stack when + * the interrupt occurred from the interrupt stack to the user stack. + * + * R15 is saved before it is clobbered. */ + "PUSH.L R15 \n" \ + + /* Read the user stack pointer. */ + "MVFC USP, R15 \n" \ + + /* Move the address down to the data being moved. */ + "SUB #12, R15 \n" \ + "MVTC R15, USP \n" \ + + /* Copy the data across, R15, then PC, then PSW. */ + "MOV.L [ R0 ], [ R15 ] \n" \ + "MOV.L 4[ R0 ], 4[ R15 ] \n" \ + "MOV.L 8[ R0 ], 8[ R15 ] \n" \ + + /* Move the interrupt stack pointer to its new correct position. */ + "ADD #12, R0 \n" \ + + /* All the rest of the registers are saved directly to the user stack. */ + "SETPSW U \n" \ + + /* Save the rest of the general registers (R15 has been saved already). */ + "PUSHM R1-R14 \n" \ + + /* Save the FPSW and accumulator. */ + "MVFC FPSW, R15 \n" \ + "PUSH.L R15 \n" \ + "MVFACGU #0, A1, R15 \n" \ + "PUSH.L R15 \n" \ + "MVFACHI #0, A1, R15 \n" \ + "PUSH.L R15 \n" \ + /* Low order word. */ + "MVFACLO #0, A1, R15 \n" \ + "PUSH.L R15 \n" \ + "MVFACGU #0, A0, R15 \n" \ + "PUSH.L R15 \n" \ + "MVFACHI #0, A0, R15 \n" \ + "PUSH.L R15 \n" \ + /* Low order word. */ + "MVFACLO #0, A0, R15 \n" \ + "PUSH.L R15 \n" \ + + /* Save the stack pointer to the TCB. */ + "MOV.L #_pxCurrentTCB, R15 \n" \ + "MOV.L [ R15 ], R15 \n" \ + "MOV.L R0, [ R15 ] \n" \ + + + /* Ensure the interrupt mask is set to the syscall priority while the kernel + * structures are being accessed. */ + "MVTIPL %0 \n" \ + + /* Select the next task to run. */ + "BSR.A _vTaskSwitchContext \n" \ + + /* Reset the interrupt mask as no more data structure access is required. */ + "MVTIPL %1 \n" \ + + + /* Load the stack pointer of the task that is now selected as the Running + * state task from its TCB. */ + "MOV.L #_pxCurrentTCB,R15 \n" \ + "MOV.L [ R15 ], R15 \n" \ + "MOV.L [ R15 ], R0 \n" \ + + + /* Restore the context of the new task. The PSW (Program Status Word) and + * PC will be popped by the RTE instruction. */ + "POP R15 \n" \ + + /* Accumulator low 32 bits. */ + "MVTACLO R15, A0 \n" \ + "POP R15 \n" \ + + /* Accumulator high 32 bits. */ + "MVTACHI R15, A0 \n" \ + "POP R15 \n" \ + + /* Accumulator guard. */ + "MVTACGU R15, A0 \n" \ + "POP R15 \n" \ + + /* Accumulator low 32 bits. */ + "MVTACLO R15, A1 \n" \ + "POP R15 \n" \ + + /* Accumulator high 32 bits. */ + "MVTACHI R15, A1 \n" \ + "POP R15 \n" \ + + /* Accumulator guard. */ + "MVTACGU R15, A1 \n" \ + "POP R15 \n" \ + "MVTC R15, FPSW \n" \ + "POPM R1-R15 \n" \ + "RTE \n" \ + "NOP \n" \ + "NOP " + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ), "i" ( configKERNEL_INTERRUPT_PRIORITY ) + ); +} +/*-----------------------------------------------------------*/ + +void vTickISR( void ) +{ + /* Re-enabled interrupts. */ + __asm volatile ( "SETPSW I" ); + + /* Increment the tick, and perform any processing the new tick value + * necessitates. Ensure IPL is at the max syscall value first. */ + portMASK_INTERRUPTS_FROM_KERNEL_ISR(); + { + if( xTaskIncrementTick() != pdFALSE ) + { + taskYIELD(); + } + } + portUNMASK_INTERRUPTS_FROM_KERNEL_ISR(); +} +/*-----------------------------------------------------------*/ + +uint32_t ulPortGetIPL( void ) +{ + __asm volatile + ( + "MVFC PSW, R1 \n" \ + "SHLR #24, R1 \n" \ + "RTS " + ); + + /* This will never get executed, but keeps the compiler from complaining. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortSetIPL( uint32_t ulNewIPL ) +{ + __asm volatile + ( + "PUSH R5 \n" \ + "MVFC PSW, R5 \n" \ + "SHLL #24, R1 \n" \ + "AND #-0F000001H, R5 \n" \ + "OR R1, R5 \n" \ + "MVTC R5, PSW \n" \ + "POP R5 \n" \ + "RTS " + ); +} diff --git a/portable/GCC/RX200/portmacro.h b/portable/GCC/RX200/portmacro.h new file mode 100644 index 000000000..16e41bc61 --- /dev/null +++ b/portable/GCC/RX200/portmacro.h @@ -0,0 +1,152 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* When the FIT configurator or the Smart Configurator is used, platform.h has to be + * used. */ +#ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H + #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0 +#endif + +/* Type definitions - these are a bit legacy and not really used now, other than + * portSTACK_TYPE and portBASE_TYPE. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() __asm volatile ( "NOP" ) + +/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;" + * where portITU_SWINTR is the location of the software interrupt register + * (0x000872E0). Don't rely on the assembler to select a register, so instead + * save and restore clobbered registers manually. */ +#define portYIELD() \ + __asm volatile \ + ( \ + "PUSH.L R10 \n" \ + "MOV.L #0x872E0, R10 \n" \ + "MOV.B #0x1, [R10] \n" \ + "MOV.L [R10], R10 \n" \ + "POP R10 \n" \ + ) + +#define portYIELD_FROM_ISR( x ) if( x != pdFALSE ) portYIELD( ) + +/* These macros should not be called directly, but through the + * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is + * performed if configASSERT() is defined to ensure an assertion handler does not + * inadvertently attempt to lower the IPL when the call to assert was triggered + * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY + * when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API + * functions are those that end in FromISR. FreeRTOS maintains a separate + * interrupt API to ensure API function and interrupt entry is as fast and as + * simple as possible. */ +#define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0" ) +#if ( configASSERT_DEFINED == 1 ) + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) + #define portDISABLE_INTERRUPTS() if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile( "MVTIPL %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) +#else + #define portDISABLE_INTERRUPTS() __asm volatile ( "MVTIPL %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) +#endif + +/* Critical nesting counts are stored in the TCB. */ +#define portCRITICAL_NESTING_IN_TCB ( 1 ) + +/* The critical nesting functions defined within tasks.c. */ +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() + +/* As this port allows interrupt nesting... */ +uint32_t ulPortGetIPL( void ) __attribute__( ( naked ) ); +void vPortSetIPL( uint32_t ulNewIPL ) __attribute__( ( naked ) ); +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/RX600/port.c b/portable/GCC/RX600/port.c new file mode 100644 index 000000000..9e6a7b443 --- /dev/null +++ b/portable/GCC/RX600/port.c @@ -0,0 +1,399 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the SH2A port. +*----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Library includes. */ +#include "string.h" + +/* Hardware specifics. */ +#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 ) + + #include "platform.h" + +#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + + #include "iodefine.h" + +#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + + +/*-----------------------------------------------------------*/ + +/* Tasks should start with interrupts enabled and in Supervisor mode, therefore + * PSW is set with U and I set, and PM and IPL clear. */ +#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) +#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 ) + +/* These macros allow a critical section to be added around the call to + * xTaskIncrementTick(), which is only ever called from interrupts at the kernel + * priority - ie a known priority. Therefore these local macros are a slight + * optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros, + * which would require the old IPL to be read first and stored in a local variable. */ +#define portDISABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) +#define portENABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i" ( configKERNEL_INTERRUPT_PRIORITY ) ) + +/*-----------------------------------------------------------*/ + +/* + * Function to start the first task executing - written in asm code as direct + * access to registers is required. + */ +static void prvStartFirstTask( void ) __attribute__( ( naked ) ); + +/* + * Software interrupt handler. Performs the actual context switch (saving and + * restoring of registers). Written in asm code as direct register access is + * required. + */ +#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 ) + + R_BSP_PRAGMA_INTERRUPT( vSoftwareInterruptISR, VECT( ICU, SWINT ) ) + R_BSP_ATTRIB_INTERRUPT void vSoftwareInterruptISR( void ) __attribute__( ( naked ) ); + +#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + + void vSoftwareInterruptISR( void ) __attribute__( ( naked ) ); + +#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + +/* + * The tick ISR handler. The peripheral used is configured by the application + * via a hook/callback function. + */ +#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 ) + + R_BSP_PRAGMA_INTERRUPT( vTickISR, _VECT( configTICK_VECTOR ) ) + R_BSP_ATTRIB_INTERRUPT void vTickISR( void ); /* Do not add __attribute__( ( interrupt ) ). */ + +#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + + void vTickISR( void ) __attribute__( ( interrupt ) ); + +#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + +/*-----------------------------------------------------------*/ + +extern void * pxCurrentTCB; + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* R0 is not included as it is the stack pointer. */ + + *pxTopOfStack = 0x00; + pxTopOfStack--; + *pxTopOfStack = portINITIAL_PSW; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; + + /* When debugging it can be useful if every register is set to a known + * value. Otherwise code space can be saved by just setting the registers + * that need to be set. */ + #ifdef USE_FULL_REGISTER_INITIALISATION + { + pxTopOfStack--; + *pxTopOfStack = 0xffffffff; /* r15. */ + pxTopOfStack--; + *pxTopOfStack = 0xeeeeeeee; + pxTopOfStack--; + *pxTopOfStack = 0xdddddddd; + pxTopOfStack--; + *pxTopOfStack = 0xcccccccc; + pxTopOfStack--; + *pxTopOfStack = 0xbbbbbbbb; + pxTopOfStack--; + *pxTopOfStack = 0xaaaaaaaa; + pxTopOfStack--; + *pxTopOfStack = 0x99999999; + pxTopOfStack--; + *pxTopOfStack = 0x88888888; + pxTopOfStack--; + *pxTopOfStack = 0x77777777; + pxTopOfStack--; + *pxTopOfStack = 0x66666666; + pxTopOfStack--; + *pxTopOfStack = 0x55555555; + pxTopOfStack--; + *pxTopOfStack = 0x44444444; + pxTopOfStack--; + *pxTopOfStack = 0x33333333; + pxTopOfStack--; + *pxTopOfStack = 0x22222222; + pxTopOfStack--; + } + #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ + { + pxTopOfStack -= 15; + } + #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */ + + *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_FPSW; + pxTopOfStack--; + *pxTopOfStack = 0x12345678; /* Accumulator. */ + pxTopOfStack--; + *pxTopOfStack = 0x87654321; /* Accumulator. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + extern void vApplicationSetupTimerInterrupt( void ); + + /* Use pxCurrentTCB just so it does not get optimised away. */ + if( pxCurrentTCB != NULL ) + { + /* Call an application function to set up the timer that will generate the + * tick interrupt. This way the application can decide which peripheral to + * use. A demo application is provided to show a suitable example. */ + vApplicationSetupTimerInterrupt(); + + /* Enable the software interrupt. */ + _IEN( _ICU_SWINT ) = 1; + + /* Ensure the software interrupt is clear. */ + _IR( _ICU_SWINT ) = 0; + + /* Ensure the software interrupt is set to the kernel priority. */ + _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the first task. */ + prvStartFirstTask(); + } + + /* Should not get here. */ + return pdFAIL; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( pxCurrentTCB == NULL ); +} +/*-----------------------------------------------------------*/ + +static void prvStartFirstTask( void ) +{ + __asm volatile + ( + + /* When starting the scheduler there is nothing that needs moving to the + * interrupt stack because the function is not called from an interrupt. + * Just ensure the current stack is the user stack. */ + "SETPSW U \n" \ + + + /* Obtain the location of the stack associated with which ever task + * pxCurrentTCB is currently pointing to. */ + "MOV.L #_pxCurrentTCB, R15 \n" \ + "MOV.L [R15], R15 \n" \ + "MOV.L [R15], R0 \n" \ + + + /* Restore the registers from the stack of the task pointed to by + * pxCurrentTCB. */ + "POP R15 \n" \ + + /* Accumulator low 32 bits. */ + "MVTACLO R15 \n" \ + "POP R15 \n" \ + + /* Accumulator high 32 bits. */ + "MVTACHI R15 \n" \ + "POP R15 \n" \ + + /* Floating point status word. */ + "MVTC R15, FPSW \n" \ + + /* R1 to R15 - R0 is not included as it is the SP. */ + "POPM R1-R15 \n" \ + + /* This pops the remaining registers. */ + "RTE \n" \ + "NOP \n" \ + "NOP \n" + ); +} +/*-----------------------------------------------------------*/ + +void vSoftwareInterruptISR( void ) +{ + __asm volatile + ( + /* Re-enable interrupts. */ + "SETPSW I \n" \ + + + /* Move the data that was automatically pushed onto the interrupt stack when + * the interrupt occurred from the interrupt stack to the user stack. + * + * R15 is saved before it is clobbered. */ + "PUSH.L R15 \n" \ + + /* Read the user stack pointer. */ + "MVFC USP, R15 \n" \ + + /* Move the address down to the data being moved. */ + "SUB #12, R15 \n" \ + "MVTC R15, USP \n" \ + + /* Copy the data across, R15, then PC, then PSW. */ + "MOV.L [ R0 ], [ R15 ] \n" \ + "MOV.L 4[ R0 ], 4[ R15 ] \n" \ + "MOV.L 8[ R0 ], 8[ R15 ] \n" \ + + /* Move the interrupt stack pointer to its new correct position. */ + "ADD #12, R0 \n" \ + + /* All the rest of the registers are saved directly to the user stack. */ + "SETPSW U \n" \ + + /* Save the rest of the general registers (R15 has been saved already). */ + "PUSHM R1-R14 \n" \ + + /* Save the FPSW and accumulator. */ + "MVFC FPSW, R15 \n" \ + "PUSH.L R15 \n" \ + "MVFACHI R15 \n" \ + "PUSH.L R15 \n" \ + + /* Middle word. */ + "MVFACMI R15 \n" \ + + /* Shifted left as it is restored to the low order word. */ + "SHLL #16, R15 \n" \ + "PUSH.L R15 \n" \ + + /* Save the stack pointer to the TCB. */ + "MOV.L #_pxCurrentTCB, R15 \n" \ + "MOV.L [ R15 ], R15 \n" \ + "MOV.L R0, [ R15 ] \n" \ + + + /* Ensure the interrupt mask is set to the syscall priority while the kernel + * structures are being accessed. */ + "MVTIPL %0 \n" \ + + /* Select the next task to run. */ + "BSR.A _vTaskSwitchContext \n" \ + + /* Reset the interrupt mask as no more data structure access is required. */ + "MVTIPL %1 \n" \ + + + /* Load the stack pointer of the task that is now selected as the Running + * state task from its TCB. */ + "MOV.L #_pxCurrentTCB,R15 \n" \ + "MOV.L [ R15 ], R15 \n" \ + "MOV.L [ R15 ], R0 \n" \ + + + /* Restore the context of the new task. The PSW (Program Status Word) and + * PC will be popped by the RTE instruction. */ + "POP R15 \n" \ + "MVTACLO R15 \n" \ + "POP R15 \n" \ + "MVTACHI R15 \n" \ + "POP R15 \n" \ + "MVTC R15, FPSW \n" \ + "POPM R1-R15 \n" \ + "RTE \n" \ + "NOP \n" \ + "NOP " + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ), "i" ( configKERNEL_INTERRUPT_PRIORITY ) + ); +} +/*-----------------------------------------------------------*/ + +void vTickISR( void ) +{ + /* Re-enabled interrupts. */ + __asm volatile ( "SETPSW I" ); + + /* Increment the tick, and perform any processing the new tick value + * necessitates. Ensure IPL is at the max syscall value first. */ + portDISABLE_INTERRUPTS_FROM_KERNEL_ISR(); + { + if( xTaskIncrementTick() != pdFALSE ) + { + taskYIELD(); + } + } + portENABLE_INTERRUPTS_FROM_KERNEL_ISR(); +} +/*-----------------------------------------------------------*/ + +uint32_t ulPortGetIPL( void ) +{ + __asm volatile + ( + "MVFC PSW, R1 \n" \ + "SHLR #24, R1 \n" \ + "RTS " + ); + + /* This will never get executed, but keeps the compiler from complaining. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortSetIPL( uint32_t ulNewIPL ) +{ + /* Avoid compiler warning about unreferenced parameter. */ + ( void ) ulNewIPL; + + __asm volatile + ( + "PUSH R5 \n" \ + "MVFC PSW, R5 \n" \ + "SHLL #24, R1 \n" \ + "AND #-0F000001H, R5 \n" \ + "OR R1, R5 \n" \ + "MVTC R5, PSW \n" \ + "POP R5 \n" \ + "RTS " + ); +} diff --git a/portable/GCC/RX600/portmacro.h b/portable/GCC/RX600/portmacro.h new file mode 100644 index 000000000..187b2b5bd --- /dev/null +++ b/portable/GCC/RX600/portmacro.h @@ -0,0 +1,152 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* When the FIT configurator or the Smart Configurator is used, platform.h has to be + * used. */ +#ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H + #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0 +#endif + +/* Type definitions - these are a bit legacy and not really used now, other than + * portSTACK_TYPE and portBASE_TYPE. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() __asm volatile ( "NOP" ) + +/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;" + * where portITU_SWINTR is the location of the software interrupt register + * (0x000872E0). Don't rely on the assembler to select a register, so instead + * save and restore clobbered registers manually. */ +#define portYIELD() \ + __asm volatile \ + ( \ + "PUSH.L R10 \n" \ + "MOV.L #0x872E0, R10 \n" \ + "MOV.B #0x1, [R10] \n" \ + "MOV.L [R10], R10 \n" \ + "POP R10 \n" \ + ) + +#define portYIELD_FROM_ISR( x ) do { if( x != pdFALSE ) portYIELD( ); } while( 0 ) + +/* These macros should not be called directly, but through the + * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is + * performed if configASSERT() is defined to ensure an assertion handler does not + * inadvertently attempt to lower the IPL when the call to assert was triggered + * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY + * when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API + * functions are those that end in FromISR. FreeRTOS maintains a separate + * interrupt API to ensure API function and interrupt entry is as fast and as + * simple as possible. */ +#define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0" ) +#if ( configASSERT_DEFINED == 1 ) + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) + #define portDISABLE_INTERRUPTS() if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile( "MVTIPL %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) +#else + #define portDISABLE_INTERRUPTS() __asm volatile ( "MVTIPL %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) +#endif + +/* Critical nesting counts are stored in the TCB. */ +#define portCRITICAL_NESTING_IN_TCB ( 1 ) + +/* The critical nesting functions defined within tasks.c. */ +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() + +/* As this port allows interrupt nesting... */ +uint32_t ulPortGetIPL( void ) __attribute__( ( naked ) ); +void vPortSetIPL( uint32_t ulNewIPL ) __attribute__( ( naked ) ); +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/RX600/readme.txt b/portable/GCC/RX600/readme.txt new file mode 100644 index 000000000..8dbc983fd --- /dev/null +++ b/portable/GCC/RX600/readme.txt @@ -0,0 +1,71 @@ +The following table shows which port is recommended to be used. + + +RX MCU Group CPU FPU FPU Port Layer + Core (Single (Double CC-RX GNURX ICCRX (*6) + Type Precision) Precision) + +RX110 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX111 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX113 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX130 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX13T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 + +RX210 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX21A RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX220 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX230,RX231 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23E-A RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23W RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24U RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 + +RX610 RXv1 Yes --- N/A (*4) N/A (*4) N/A (*4) +RX62N,RX621 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX630 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX634 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63N,RX631 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX64M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX65N,RX651 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX66N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX62T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX62G RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX66T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +RX71M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX72M RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +Notes: + +*1: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is not used, please define configSETUP_TICK_INTERRUPT() (in FreeRTOSConfig.h) and provide +the configuration function. Please be aware that port.c is hard coded to use CMT0 though it seems to be +configured to use any CMTn according to the definition of configTICK_VECTOR (in FreeRTOSConfig.h). + +*2: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is used, please modify port.c for the configuration. Please be aware that port.c is +hard coded to use CMT0 though it seems to be configured to use any CMTn according to the definition of +configTICK_VECTOR (in FreeRTOSConfig.h). + +*3: RX100 ports are also available. + +*4: RX600 ports use MVTIPL instruction but RX610 MCUs don't support this instruction. + +*5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h. + +#define configUSE_TASK_DPFPU_SUPPORT 0 + +*6: PriorityDefinitions.h has to be provided for port_asm.s in case of other than RX700v3_DPFPU port. +It contains two definitions of interrupt priority like the following. + +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + + +For more information about Renesas RX MCUs, please visit the following URL: + +https://www.renesas.com/products/microcontrollers-microprocessors/rx.html diff --git a/portable/GCC/RX600v2/port.c b/portable/GCC/RX600v2/port.c new file mode 100644 index 000000000..c31d2c65c --- /dev/null +++ b/portable/GCC/RX600v2/port.c @@ -0,0 +1,442 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the SH2A port. +*----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Library includes. */ +#include "string.h" + +/* Hardware specifics. */ +#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 ) + + #include "platform.h" + +#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + + #include "iodefine.h" + +#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + +/*-----------------------------------------------------------*/ + +/* Tasks should start with interrupts enabled and in Supervisor mode, therefore + * PSW is set with U and I set, and PM and IPL clear. */ +#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) +#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 ) + +/* These macros allow a critical section to be added around the call to + * xTaskIncrementTick(), which is only ever called from interrupts at the kernel + * priority - ie a known priority. Therefore these local macros are a slight + * optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros, + * which would require the old IPL to be read first and stored in a local variable. */ +#define portMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) +#define portUNMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i" ( configKERNEL_INTERRUPT_PRIORITY ) ) + +/*-----------------------------------------------------------*/ + +/* + * Function to start the first task executing - written in asm code as direct + * access to registers is required. + */ +static void prvStartFirstTask( void ) __attribute__( ( naked ) ); + +/* + * Software interrupt handler. Performs the actual context switch (saving and + * restoring of registers). Written in asm code as direct register access is + * required. + */ +#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 ) + R_BSP_PRAGMA_INTERRUPT( vSoftwareInterruptISR, VECT( ICU, SWINT ) ) + R_BSP_ATTRIB_INTERRUPT void vSoftwareInterruptISR( void ) __attribute__( ( naked ) ); +#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + void vSoftwareInterruptISR( void ) __attribute__( ( naked ) ); +#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + +/* + * The tick ISR handler. The peripheral used is configured by the application + * via a hook/callback function. + */ +#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 ) + + R_BSP_PRAGMA_INTERRUPT( vTickISR, _VECT( configTICK_VECTOR ) ) + R_BSP_ATTRIB_INTERRUPT void vTickISR( void ); /* Do not add __attribute__( ( interrupt ) ). */ + +#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + + void vTickISR( void ) __attribute__( ( interrupt ) ); + +#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ +/*-----------------------------------------------------------*/ + +extern void * pxCurrentTCB; + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* R0 is not included as it is the stack pointer. */ + + *pxTopOfStack = 0x00; + pxTopOfStack--; + *pxTopOfStack = portINITIAL_PSW; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; + + /* When debugging it can be useful if every register is set to a known + * value. Otherwise code space can be saved by just setting the registers + * that need to be set. */ + #ifdef USE_FULL_REGISTER_INITIALISATION + { + pxTopOfStack--; + *pxTopOfStack = 0xffffffff; /* r15. */ + pxTopOfStack--; + *pxTopOfStack = 0xeeeeeeee; + pxTopOfStack--; + *pxTopOfStack = 0xdddddddd; + pxTopOfStack--; + *pxTopOfStack = 0xcccccccc; + pxTopOfStack--; + *pxTopOfStack = 0xbbbbbbbb; + pxTopOfStack--; + *pxTopOfStack = 0xaaaaaaaa; + pxTopOfStack--; + *pxTopOfStack = 0x99999999; + pxTopOfStack--; + *pxTopOfStack = 0x88888888; + pxTopOfStack--; + *pxTopOfStack = 0x77777777; + pxTopOfStack--; + *pxTopOfStack = 0x66666666; + pxTopOfStack--; + *pxTopOfStack = 0x55555555; + pxTopOfStack--; + *pxTopOfStack = 0x44444444; + pxTopOfStack--; + *pxTopOfStack = 0x33333333; + pxTopOfStack--; + *pxTopOfStack = 0x22222222; + pxTopOfStack--; + } + #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ + { + pxTopOfStack -= 15; + } + #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */ + + *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_FPSW; + pxTopOfStack--; + *pxTopOfStack = 0x11111111; /* Accumulator 0. */ + pxTopOfStack--; + *pxTopOfStack = 0x22222222; /* Accumulator 0. */ + pxTopOfStack--; + *pxTopOfStack = 0x33333333; /* Accumulator 0. */ + pxTopOfStack--; + *pxTopOfStack = 0x44444444; /* Accumulator 1. */ + pxTopOfStack--; + *pxTopOfStack = 0x55555555; /* Accumulator 1. */ + pxTopOfStack--; + *pxTopOfStack = 0x66666666; /* Accumulator 1. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + extern void vApplicationSetupTimerInterrupt( void ); + + /* Use pxCurrentTCB just so it does not get optimised away. */ + if( pxCurrentTCB != NULL ) + { + /* Call an application function to set up the timer that will generate the + * tick interrupt. This way the application can decide which peripheral to + * use. A demo application is provided to show a suitable example. */ + vApplicationSetupTimerInterrupt(); + + /* Enable the software interrupt. */ + _IEN( _ICU_SWINT ) = 1; + + /* Ensure the software interrupt is clear. */ + _IR( _ICU_SWINT ) = 0; + + /* Ensure the software interrupt is set to the kernel priority. */ + _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the first task. */ + prvStartFirstTask(); + } + + /* Should not get here. */ + return pdFAIL; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( pxCurrentTCB == NULL ); +} +/*-----------------------------------------------------------*/ + +static void prvStartFirstTask( void ) +{ + __asm volatile + ( + + /* When starting the scheduler there is nothing that needs moving to the + * interrupt stack because the function is not called from an interrupt. + * Just ensure the current stack is the user stack. */ + "SETPSW U \n" \ + + + /* Obtain the location of the stack associated with which ever task + * pxCurrentTCB is currently pointing to. */ + "MOV.L #_pxCurrentTCB, R15 \n" \ + "MOV.L [R15], R15 \n" \ + "MOV.L [R15], R0 \n" \ + + + /* Restore the registers from the stack of the task pointed to by + * pxCurrentTCB. */ + "POP R15 \n" \ + + /* Accumulator low 32 bits. */ + "MVTACLO R15, A0 \n" \ + "POP R15 \n" \ + + /* Accumulator high 32 bits. */ + "MVTACHI R15, A0 \n" \ + "POP R15 \n" \ + + /* Accumulator guard. */ + "MVTACGU R15, A0 \n" \ + "POP R15 \n" \ + + /* Accumulator low 32 bits. */ + "MVTACLO R15, A1 \n" \ + "POP R15 \n" \ + + /* Accumulator high 32 bits. */ + "MVTACHI R15, A1 \n" \ + "POP R15 \n" \ + + /* Accumulator guard. */ + "MVTACGU R15, A1 \n" \ + "POP R15 \n" \ + + /* Floating point status word. */ + "MVTC R15, FPSW \n" \ + + /* R1 to R15 - R0 is not included as it is the SP. */ + "POPM R1-R15 \n" \ + + /* This pops the remaining registers. */ + "RTE \n" \ + "NOP \n" \ + "NOP \n" + ); +} +/*-----------------------------------------------------------*/ + +void vSoftwareInterruptISR( void ) +{ + __asm volatile + ( + /* Re-enable interrupts. */ + "SETPSW I \n" \ + + + /* Move the data that was automatically pushed onto the interrupt stack when + * the interrupt occurred from the interrupt stack to the user stack. + * + * R15 is saved before it is clobbered. */ + "PUSH.L R15 \n" \ + + /* Read the user stack pointer. */ + "MVFC USP, R15 \n" \ + + /* Move the address down to the data being moved. */ + "SUB #12, R15 \n" \ + "MVTC R15, USP \n" \ + + /* Copy the data across, R15, then PC, then PSW. */ + "MOV.L [ R0 ], [ R15 ] \n" \ + "MOV.L 4[ R0 ], 4[ R15 ] \n" \ + "MOV.L 8[ R0 ], 8[ R15 ] \n" \ + + /* Move the interrupt stack pointer to its new correct position. */ + "ADD #12, R0 \n" \ + + /* All the rest of the registers are saved directly to the user stack. */ + "SETPSW U \n" \ + + /* Save the rest of the general registers (R15 has been saved already). */ + "PUSHM R1-R14 \n" \ + + /* Save the FPSW and accumulator. */ + "MVFC FPSW, R15 \n" \ + "PUSH.L R15 \n" \ + "MVFACGU #0, A1, R15 \n" \ + "PUSH.L R15 \n" \ + "MVFACHI #0, A1, R15 \n" \ + "PUSH.L R15 \n" \ + /* Low order word. */ + "MVFACLO #0, A1, R15 \n" \ + "PUSH.L R15 \n" \ + "MVFACGU #0, A0, R15 \n" \ + "PUSH.L R15 \n" \ + "MVFACHI #0, A0, R15 \n" \ + "PUSH.L R15 \n" \ + /* Low order word. */ + "MVFACLO #0, A0, R15 \n" \ + "PUSH.L R15 \n" \ + + /* Save the stack pointer to the TCB. */ + "MOV.L #_pxCurrentTCB, R15 \n" \ + "MOV.L [ R15 ], R15 \n" \ + "MOV.L R0, [ R15 ] \n" \ + + + /* Ensure the interrupt mask is set to the syscall priority while the kernel + * structures are being accessed. */ + "MVTIPL %0 \n" \ + + /* Select the next task to run. */ + "BSR.A _vTaskSwitchContext \n" \ + + /* Reset the interrupt mask as no more data structure access is required. */ + "MVTIPL %1 \n" \ + + + /* Load the stack pointer of the task that is now selected as the Running + * state task from its TCB. */ + "MOV.L #_pxCurrentTCB,R15 \n" \ + "MOV.L [ R15 ], R15 \n" \ + "MOV.L [ R15 ], R0 \n" \ + + + /* Restore the context of the new task. The PSW (Program Status Word) and + * PC will be popped by the RTE instruction. */ + "POP R15 \n" \ + + /* Accumulator low 32 bits. */ + "MVTACLO R15, A0 \n" \ + "POP R15 \n" \ + + /* Accumulator high 32 bits. */ + "MVTACHI R15, A0 \n" \ + "POP R15 \n" \ + + /* Accumulator guard. */ + "MVTACGU R15, A0 \n" \ + "POP R15 \n" \ + + /* Accumulator low 32 bits. */ + "MVTACLO R15, A1 \n" \ + "POP R15 \n" \ + + /* Accumulator high 32 bits. */ + "MVTACHI R15, A1 \n" \ + "POP R15 \n" \ + + /* Accumulator guard. */ + "MVTACGU R15, A1 \n" \ + "POP R15 \n" \ + "MVTC R15, FPSW \n" \ + "POPM R1-R15 \n" \ + "RTE \n" \ + "NOP \n" \ + "NOP " + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ), "i" ( configKERNEL_INTERRUPT_PRIORITY ) + ); +} +/*-----------------------------------------------------------*/ + +void vTickISR( void ) +{ + /* Re-enabled interrupts. */ + __asm volatile ( "SETPSW I" ); + + /* Increment the tick, and perform any processing the new tick value + * necessitates. Ensure IPL is at the max syscall value first. */ + portMASK_INTERRUPTS_FROM_KERNEL_ISR(); + { + if( xTaskIncrementTick() != pdFALSE ) + { + taskYIELD(); + } + } + portUNMASK_INTERRUPTS_FROM_KERNEL_ISR(); +} +/*-----------------------------------------------------------*/ + +uint32_t ulPortGetIPL( void ) +{ + __asm volatile + ( + "MVFC PSW, R1 \n" \ + "SHLR #24, R1 \n" \ + "RTS " + ); + + /* This will never get executed, but keeps the compiler from complaining. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortSetIPL( uint32_t ulNewIPL ) +{ + /* Avoid compiler warning about unreferenced parameter. */ + ( void ) ulNewIPL; + + __asm volatile + ( + "PUSH R5 \n" \ + "MVFC PSW, R5 \n" \ + "SHLL #24, R1 \n" \ + "AND #-0F000001H, R5 \n" \ + "OR R1, R5 \n" \ + "MVTC R5, PSW \n" \ + "POP R5 \n" \ + "RTS " + ); +} diff --git a/portable/GCC/RX600v2/portmacro.h b/portable/GCC/RX600v2/portmacro.h new file mode 100644 index 000000000..187b2b5bd --- /dev/null +++ b/portable/GCC/RX600v2/portmacro.h @@ -0,0 +1,152 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* When the FIT configurator or the Smart Configurator is used, platform.h has to be + * used. */ +#ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H + #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0 +#endif + +/* Type definitions - these are a bit legacy and not really used now, other than + * portSTACK_TYPE and portBASE_TYPE. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() __asm volatile ( "NOP" ) + +/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;" + * where portITU_SWINTR is the location of the software interrupt register + * (0x000872E0). Don't rely on the assembler to select a register, so instead + * save and restore clobbered registers manually. */ +#define portYIELD() \ + __asm volatile \ + ( \ + "PUSH.L R10 \n" \ + "MOV.L #0x872E0, R10 \n" \ + "MOV.B #0x1, [R10] \n" \ + "MOV.L [R10], R10 \n" \ + "POP R10 \n" \ + ) + +#define portYIELD_FROM_ISR( x ) do { if( x != pdFALSE ) portYIELD( ); } while( 0 ) + +/* These macros should not be called directly, but through the + * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is + * performed if configASSERT() is defined to ensure an assertion handler does not + * inadvertently attempt to lower the IPL when the call to assert was triggered + * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY + * when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API + * functions are those that end in FromISR. FreeRTOS maintains a separate + * interrupt API to ensure API function and interrupt entry is as fast and as + * simple as possible. */ +#define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0" ) +#if ( configASSERT_DEFINED == 1 ) + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) + #define portDISABLE_INTERRUPTS() if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile( "MVTIPL %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) +#else + #define portDISABLE_INTERRUPTS() __asm volatile ( "MVTIPL %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) +#endif + +/* Critical nesting counts are stored in the TCB. */ +#define portCRITICAL_NESTING_IN_TCB ( 1 ) + +/* The critical nesting functions defined within tasks.c. */ +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() + +/* As this port allows interrupt nesting... */ +uint32_t ulPortGetIPL( void ) __attribute__( ( naked ) ); +void vPortSetIPL( uint32_t ulNewIPL ) __attribute__( ( naked ) ); +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/RX600v2/readme.txt b/portable/GCC/RX600v2/readme.txt new file mode 100644 index 000000000..8dbc983fd --- /dev/null +++ b/portable/GCC/RX600v2/readme.txt @@ -0,0 +1,71 @@ +The following table shows which port is recommended to be used. + + +RX MCU Group CPU FPU FPU Port Layer + Core (Single (Double CC-RX GNURX ICCRX (*6) + Type Precision) Precision) + +RX110 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX111 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX113 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX130 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX13T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 + +RX210 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX21A RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX220 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX230,RX231 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23E-A RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23W RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24U RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 + +RX610 RXv1 Yes --- N/A (*4) N/A (*4) N/A (*4) +RX62N,RX621 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX630 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX634 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63N,RX631 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX64M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX65N,RX651 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX66N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX62T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX62G RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX66T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +RX71M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX72M RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +Notes: + +*1: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is not used, please define configSETUP_TICK_INTERRUPT() (in FreeRTOSConfig.h) and provide +the configuration function. Please be aware that port.c is hard coded to use CMT0 though it seems to be +configured to use any CMTn according to the definition of configTICK_VECTOR (in FreeRTOSConfig.h). + +*2: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is used, please modify port.c for the configuration. Please be aware that port.c is +hard coded to use CMT0 though it seems to be configured to use any CMTn according to the definition of +configTICK_VECTOR (in FreeRTOSConfig.h). + +*3: RX100 ports are also available. + +*4: RX600 ports use MVTIPL instruction but RX610 MCUs don't support this instruction. + +*5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h. + +#define configUSE_TASK_DPFPU_SUPPORT 0 + +*6: PriorityDefinitions.h has to be provided for port_asm.s in case of other than RX700v3_DPFPU port. +It contains two definitions of interrupt priority like the following. + +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + + +For more information about Renesas RX MCUs, please visit the following URL: + +https://www.renesas.com/products/microcontrollers-microprocessors/rx.html diff --git a/portable/GCC/RX700v3_DPFPU/port.c b/portable/GCC/RX700v3_DPFPU/port.c new file mode 100644 index 000000000..8ed1bcfa4 --- /dev/null +++ b/portable/GCC/RX700v3_DPFPU/port.c @@ -0,0 +1,619 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the RXv3 DPFPU port. +*----------------------------------------------------------*/ + +#warning Testing for DFPU support in this port is not yet complete + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Library includes. */ +#include "string.h" + +/* Hardware specifics. */ +#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 ) + + #include "platform.h" + +#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + + #include "iodefine.h" + +#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + +/*-----------------------------------------------------------*/ + +/* Tasks should start with interrupts enabled and in Supervisor mode, therefore + * PSW is set with U and I set, and PM and IPL clear. */ +#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) +#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 ) +#define portINITIAL_DPSW ( ( StackType_t ) 0x00000100 ) +#define portINITIAL_DCMR ( ( StackType_t ) 0x00000000 ) +#define portINITIAL_DECNT ( ( StackType_t ) 0x00000001 ) + +/* Tasks are not created with a DPFPU context, but can be given a DPFPU context + * after they have been created. A variable is stored as part of the tasks context + * that holds portNO_DPFPU_CONTEXT if the task does not have a DPFPU context, or + * any other value if the task does have a DPFPU context. */ +#define portNO_DPFPU_CONTEXT ( ( StackType_t ) 0 ) +#define portHAS_DPFPU_CONTEXT ( ( StackType_t ) 1 ) + +/* The space on the stack required to hold the DPFPU data registers. This is 16 + * 64-bit registers. */ +#define portDPFPU_DATA_REGISTER_WORDS ( 16 * 2 ) + +/* These macros allow a critical section to be added around the call to + * xTaskIncrementTick(), which is only ever called from interrupts at the kernel + * priority - ie a known priority. Therefore these local macros are a slight + * optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros, + * which would require the old IPL to be read first and stored in a local variable. */ +#define portMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) +#define portUNMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i" ( configKERNEL_INTERRUPT_PRIORITY ) ) + +/*-----------------------------------------------------------*/ + +/* + * Function to start the first task executing - written in asm code as direct + * access to registers is required. + */ +static void prvStartFirstTask( void ) __attribute__( ( naked ) ); + +/* + * Software interrupt handler. Performs the actual context switch (saving and + * restoring of registers). Written in asm code as direct register access is + * required. + */ +#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 ) + + R_BSP_PRAGMA_INTERRUPT( vSoftwareInterruptISR, VECT( ICU, SWINT ) ) + R_BSP_ATTRIB_INTERRUPT void vSoftwareInterruptISR( void ) __attribute__( ( naked ) ); + +#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + + void vSoftwareInterruptISR( void ) __attribute__( ( naked ) ); + +#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + +/* + * The tick ISR handler. The peripheral used is configured by the application + * via a hook/callback function. + */ +#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 ) + + R_BSP_PRAGMA_INTERRUPT( vTickISR, _VECT( configTICK_VECTOR ) ) + R_BSP_ATTRIB_INTERRUPT void vTickISR( void ); /* Do not add __attribute__( ( interrupt ) ). */ + +#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + + void vTickISR( void ) __attribute__( ( interrupt ) ); + +#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + +/*-----------------------------------------------------------*/ + +/* Saved as part of the task context. If ulPortTaskHasDPFPUContext is non-zero + * then a DPFPU context must be saved and restored for the task. */ +#if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) + + StackType_t ulPortTaskHasDPFPUContext = portNO_DPFPU_CONTEXT; + +#endif /* configUSE_TASK_DPFPU_SUPPORT */ + +/* This is accessed by the inline assembler functions so is file scope for + * convenience. */ +extern void * pxCurrentTCB; +extern void vTaskSwitchContext( void ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* R0 is not included as it is the stack pointer. */ + + *pxTopOfStack = 0x00; + pxTopOfStack--; + *pxTopOfStack = portINITIAL_PSW; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; + + /* When debugging it can be useful if every register is set to a known + * value. Otherwise code space can be saved by just setting the registers + * that need to be set. */ + #ifdef USE_FULL_REGISTER_INITIALISATION + { + pxTopOfStack--; + *pxTopOfStack = 0xffffffff; /* r15. */ + pxTopOfStack--; + *pxTopOfStack = 0xeeeeeeee; + pxTopOfStack--; + *pxTopOfStack = 0xdddddddd; + pxTopOfStack--; + *pxTopOfStack = 0xcccccccc; + pxTopOfStack--; + *pxTopOfStack = 0xbbbbbbbb; + pxTopOfStack--; + *pxTopOfStack = 0xaaaaaaaa; + pxTopOfStack--; + *pxTopOfStack = 0x99999999; + pxTopOfStack--; + *pxTopOfStack = 0x88888888; + pxTopOfStack--; + *pxTopOfStack = 0x77777777; + pxTopOfStack--; + *pxTopOfStack = 0x66666666; + pxTopOfStack--; + *pxTopOfStack = 0x55555555; + pxTopOfStack--; + *pxTopOfStack = 0x44444444; + pxTopOfStack--; + *pxTopOfStack = 0x33333333; + pxTopOfStack--; + *pxTopOfStack = 0x22222222; + pxTopOfStack--; + } + #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ + { + pxTopOfStack -= 15; + } + #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */ + + *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_FPSW; + pxTopOfStack--; + *pxTopOfStack = 0x11111111; /* Accumulator 1. */ + pxTopOfStack--; + *pxTopOfStack = 0x22222222; /* Accumulator 1. */ + pxTopOfStack--; + *pxTopOfStack = 0x33333333; /* Accumulator 1. */ + pxTopOfStack--; + *pxTopOfStack = 0x44444444; /* Accumulator 0. */ + pxTopOfStack--; + *pxTopOfStack = 0x55555555; /* Accumulator 0. */ + pxTopOfStack--; + *pxTopOfStack = 0x66666666; /* Accumulator 0. */ + + #if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) + { + /* The task will start without a DPFPU context. A task that + * uses the DPFPU hardware must call vPortTaskUsesDPFPU() before + * executing any floating point instructions. */ + pxTopOfStack--; + *pxTopOfStack = portNO_DPFPU_CONTEXT; + } + #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 ) + { + /* The task will start with a DPFPU context. Leave enough + * space for the registers - and ensure they are initialised if desired. */ + #ifdef USE_FULL_REGISTER_INITIALISATION + { + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 1515.1515; /* DR15. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 1414.1414; /* DR14. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 1313.1313; /* DR13. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 1212.1212; /* DR12. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 1111.1111; /* DR11. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 1010.1010; /* DR10. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 909.0909; /* DR9. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 808.0808; /* DR8. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 707.0707; /* DR7. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 606.0606; /* DR6. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 505.0505; /* DR5. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 404.0404; /* DR4. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 303.0303; /* DR3. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 202.0202; /* DR2. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 101.0101; /* DR1. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 9876.54321; /* DR0. */ + } + #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ + { + pxTopOfStack -= portDPFPU_DATA_REGISTER_WORDS; + memset( pxTopOfStack, 0x00, portDPFPU_DATA_REGISTER_WORDS * sizeof( StackType_t ) ); + } + #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_DECNT; /* DECNT. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_DCMR; /* DCMR. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_DPSW; /* DPSW. */ + } + #elif ( configUSE_TASK_DPFPU_SUPPORT == 0 ) + { + /* Omit DPFPU support. */ + } + #else /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */ + { + #error Invalid configUSE_TASK_DPFPU_SUPPORT setting - configUSE_TASK_DPFPU_SUPPORT must be set to 0, 1, 2, or left undefined. + } + #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) + + void vPortTaskUsesDPFPU( void ) + { + /* A task is registering the fact that it needs a DPFPU context. Set the + * DPFPU flag (which is saved as part of the task context). */ + ulPortTaskHasDPFPUContext = portHAS_DPFPU_CONTEXT; + } + +#endif /* configUSE_TASK_DPFPU_SUPPORT */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + extern void vApplicationSetupTimerInterrupt( void ); + + /* Use pxCurrentTCB just so it does not get optimised away. */ + if( pxCurrentTCB != NULL ) + { + /* Call an application function to set up the timer that will generate the + * tick interrupt. This way the application can decide which peripheral to + * use. A demo application is provided to show a suitable example. */ + vApplicationSetupTimerInterrupt(); + + /* Enable the software interrupt. */ + _IEN( _ICU_SWINT ) = 1; + + /* Ensure the software interrupt is clear. */ + _IR( _ICU_SWINT ) = 0; + + /* Ensure the software interrupt is set to the kernel priority. */ + _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the first task. */ + prvStartFirstTask(); + } + + /* Should not get here. */ + return pdFAIL; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( pxCurrentTCB == NULL ); +} +/*-----------------------------------------------------------*/ + +static void prvStartFirstTask( void ) +{ + __asm volatile + ( + + /* When starting the scheduler there is nothing that needs moving to the + * interrupt stack because the function is not called from an interrupt. + * Just ensure the current stack is the user stack. */ + "SETPSW U \n" \ + + + /* Obtain the location of the stack associated with which ever task + * pxCurrentTCB is currently pointing to. */ + "MOV.L #_pxCurrentTCB, R15 \n" \ + "MOV.L [R15], R15 \n" \ + "MOV.L [R15], R0 \n" \ + + + /* Restore the registers from the stack of the task pointed to by + * pxCurrentTCB. */ + + #if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) + + /* The restored ulPortTaskHasDPFPUContext is to be zero here. + * So, it is never necessary to restore the DPFPU context here. */ + "POP R15 \n" \ + "MOV.L #_ulPortTaskHasDPFPUContext, R14 \n" \ + "MOV.L R15, [R14] \n" \ + + #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 ) + /* Restore the DPFPU context. */ + "DPOPM.L DPSW-DECNT \n" \ + "DPOPM.D DR0-DR15 \n" \ + + #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */ + + "POP R15 \n" \ + + /* Accumulator low 32 bits. */ + "MVTACLO R15, A0 \n" \ + "POP R15 \n" \ + + /* Accumulator high 32 bits. */ + "MVTACHI R15, A0 \n" \ + "POP R15 \n" \ + + /* Accumulator guard. */ + "MVTACGU R15, A0 \n" \ + "POP R15 \n" \ + + /* Accumulator low 32 bits. */ + "MVTACLO R15, A1 \n" \ + "POP R15 \n" \ + + /* Accumulator high 32 bits. */ + "MVTACHI R15, A1 \n" \ + "POP R15 \n" \ + + /* Accumulator guard. */ + "MVTACGU R15, A1 \n" \ + "POP R15 \n" \ + + /* Floating point status word. */ + "MVTC R15, FPSW \n" \ + + /* R1 to R15 - R0 is not included as it is the SP. */ + "POPM R1-R15 \n" \ + + /* This pops the remaining registers. */ + "RTE \n" \ + "NOP \n" \ + "NOP \n" + ); +} +/*-----------------------------------------------------------*/ + +void vSoftwareInterruptISR( void ) +{ + __asm volatile + ( + /* Re-enable interrupts. */ + "SETPSW I \n" \ + + + /* Move the data that was automatically pushed onto the interrupt stack when + * the interrupt occurred from the interrupt stack to the user stack. + * + * R15 is saved before it is clobbered. */ + "PUSH.L R15 \n" \ + + /* Read the user stack pointer. */ + "MVFC USP, R15 \n" \ + + /* Move the address down to the data being moved. */ + "SUB #12, R15 \n" \ + "MVTC R15, USP \n" \ + + /* Copy the data across, R15, then PC, then PSW. */ + "MOV.L [ R0 ], [ R15 ] \n" \ + "MOV.L 4[ R0 ], 4[ R15 ] \n" \ + "MOV.L 8[ R0 ], 8[ R15 ] \n" \ + + /* Move the interrupt stack pointer to its new correct position. */ + "ADD #12, R0 \n" \ + + /* All the rest of the registers are saved directly to the user stack. */ + "SETPSW U \n" \ + + /* Save the rest of the general registers (R15 has been saved already). */ + "PUSHM R1-R14 \n" \ + + /* Save the FPSW and accumulators. */ + "MVFC FPSW, R15 \n" \ + "PUSH.L R15 \n" \ + "MVFACGU #0, A1, R15 \n" \ + "PUSH.L R15 \n" \ + "MVFACHI #0, A1, R15 \n" \ + "PUSH.L R15 \n" \ + "MVFACLO #0, A1, R15 \n" /* Low order word. */ \ + "PUSH.L R15 \n" \ + "MVFACGU #0, A0, R15 \n" \ + "PUSH.L R15 \n" \ + "MVFACHI #0, A0, R15 \n" \ + "PUSH.L R15 \n" \ + "MVFACLO #0, A0, R15 \n" /* Low order word. */ \ + "PUSH.L R15 \n" \ + + #if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) + + /* Does the task have a DPFPU context that needs saving? If + * ulPortTaskHasDPFPUContext is 0 then no. */ + "MOV.L #_ulPortTaskHasDPFPUContext, R15 \n" \ + "MOV.L [R15], R15 \n" \ + "CMP #0, R15 \n" \ + + /* Save the DPFPU context, if any. */ + "BEQ.B ?+ \n" \ + "DPUSHM.D DR0-DR15 \n" \ + "DPUSHM.L DPSW-DECNT \n" \ + "?: \n" \ + + /* Save ulPortTaskHasDPFPUContext itself. */ + "PUSH.L R15 \n" \ + + #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 ) + /* Save the DPFPU context, always. */ + "DPUSHM.D DR0-DR15 \n" \ + "DPUSHM.L DPSW-DECNT \n" \ + + #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */ + + + /* Save the stack pointer to the TCB. */ + "MOV.L #_pxCurrentTCB, R15 \n" \ + "MOV.L [ R15 ], R15 \n" \ + "MOV.L R0, [ R15 ] \n" \ + + + /* Ensure the interrupt mask is set to the syscall priority while the kernel + * structures are being accessed. */ + "MVTIPL %0 \n" \ + + /* Select the next task to run. */ + "BSR.A _vTaskSwitchContext \n" \ + + /* Reset the interrupt mask as no more data structure access is required. */ + "MVTIPL %1 \n" \ + + + /* Load the stack pointer of the task that is now selected as the Running + * state task from its TCB. */ + "MOV.L #_pxCurrentTCB,R15 \n" \ + "MOV.L [ R15 ], R15 \n" \ + "MOV.L [ R15 ], R0 \n" \ + + + /* Restore the context of the new task. The PSW (Program Status Word) and + * PC will be popped by the RTE instruction. */ + + #if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) + + /* Is there a DPFPU context to restore? If the restored + * ulPortTaskHasDPFPUContext is zero then no. */ + "POP R15 \n" \ + "MOV.L #_ulPortTaskHasDPFPUContext, R14 \n" \ + "MOV.L R15, [R14] \n" \ + "CMP #0, R15 \n" \ + + /* Restore the DPFPU context, if any. */ + "BEQ.B ?+ \n" \ + "DPOPM.L DPSW-DECNT \n" \ + "DPOPM.D DR0-DR15 \n" \ + "?: \n" \ + + #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 ) + /* Restore the DPFPU context, always. */ + "DPOPM.L DPSW-DECNT \n" \ + "DPOPM.D DR0-DR15 \n" \ + + #endif /* if( configUSE_TASK_DPFPU_SUPPORT == 1 ) */ + + "POP R15 \n" \ + + /* Accumulator low 32 bits. */ + "MVTACLO R15, A0 \n" \ + "POP R15 \n" \ + + /* Accumulator high 32 bits. */ + "MVTACHI R15, A0 \n" \ + "POP R15 \n" \ + + /* Accumulator guard. */ + "MVTACGU R15, A0 \n" \ + "POP R15 \n" \ + + /* Accumulator low 32 bits. */ + "MVTACLO R15, A1 \n" \ + "POP R15 \n" \ + + /* Accumulator high 32 bits. */ + "MVTACHI R15, A1 \n" \ + "POP R15 \n" \ + + /* Accumulator guard. */ + "MVTACGU R15, A1 \n" \ + "POP R15 \n" \ + "MVTC R15, FPSW \n" \ + "POPM R1-R15 \n" \ + "RTE \n" \ + "NOP \n" \ + "NOP " + ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ), "i" ( configKERNEL_INTERRUPT_PRIORITY ) + ); +} +/*-----------------------------------------------------------*/ + +void vTickISR( void ) +{ + /* Re-enabled interrupts. */ + __asm volatile ( "SETPSW I" ); + + /* Increment the tick, and perform any processing the new tick value + * necessitates. Ensure IPL is at the max syscall value first. */ + portMASK_INTERRUPTS_FROM_KERNEL_ISR(); + { + if( xTaskIncrementTick() != pdFALSE ) + { + taskYIELD(); + } + } + portUNMASK_INTERRUPTS_FROM_KERNEL_ISR(); +} +/*-----------------------------------------------------------*/ + +uint32_t ulPortGetIPL( void ) +{ + __asm volatile + ( + "MVFC PSW, R1 \n" \ + "SHLR #24, R1 \n" \ + "RTS " + ); + + /* This will never get executed, but keeps the compiler from complaining. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortSetIPL( uint32_t ulNewIPL ) +{ + /* Avoid compiler warning about unreferenced parameter. */ + ( void ) ulNewIPL; + + __asm volatile + ( + "PUSH R5 \n" \ + "MVFC PSW, R5 \n" \ + "SHLL #24, R1 \n" \ + "AND #-0F000001H, R5 \n" \ + "OR R1, R5 \n" \ + "MVTC R5, PSW \n" \ + "POP R5 \n" \ + "RTS " + ); +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/RX700v3_DPFPU/portmacro.h b/portable/GCC/RX700v3_DPFPU/portmacro.h new file mode 100644 index 000000000..bbfd24f90 --- /dev/null +++ b/portable/GCC/RX700v3_DPFPU/portmacro.h @@ -0,0 +1,196 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* When the FIT configurator or the Smart Configurator is used, platform.h has to be + * used. */ +#ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H + #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0 +#endif + +/* If configUSE_TASK_DPFPU_SUPPORT is set to 1 (or undefined) then each task will + * be created without a DPFPU context, and a task must call vTaskUsesDPFPU() before + * making use of any DPFPU registers. If configUSE_TASK_DPFPU_SUPPORT is set to 2 then + * tasks are created with a DPFPU context by default, and calling vTaskUsesDPFPU() has + * no effect. If configUSE_TASK_DPFPU_SUPPORT is set to 0 then tasks never take care + * of any DPFPU context (even if DPFPU registers are used). */ +#ifndef configUSE_TASK_DPFPU_SUPPORT + #define configUSE_TASK_DPFPU_SUPPORT 1 +#endif + +/*-----------------------------------------------------------*/ + +/* Type definitions - these are a bit legacy and not really used now, other than + * portSTACK_TYPE and portBASE_TYPE. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif + +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() __asm volatile ( "NOP" ) + +/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;" + * where portITU_SWINTR is the location of the software interrupt register + * (0x000872E0). Don't rely on the assembler to select a register, so instead + * save and restore clobbered registers manually. */ +#define portYIELD() \ + __asm volatile \ + ( \ + "PUSH.L R10 \n" \ + "MOV.L #0x872E0, R10 \n" \ + "MOV.B #0x1, [R10] \n" \ + "CMP [R10].UB, R10 \n" \ + "POP R10 \n" \ + ::: "cc" \ + ) + +#define portYIELD_FROM_ISR( x ) do { if( ( x ) != pdFALSE ) portYIELD( ); } while( 0 ) + +/* Workaround to reduce errors/warnings caused by e2 studio CDT's INDEXER and CODAN. */ +#ifdef __CDT_PARSER__ + #ifndef __asm + #define __asm asm + #endif + #ifndef __attribute__ + #define __attribute__( ... ) + #endif +#endif + +/* These macros should not be called directly, but through the + * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is + * performed if configASSERT() is defined to ensure an assertion handler does not + * inadvertently attempt to lower the IPL when the call to assert was triggered + * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY + * when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API + * functions are those that end in FromISR. FreeRTOS maintains a separate + * interrupt API to ensure API function and interrupt entry is as fast and as + * simple as possible. */ +#define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0" ) +#if ( configASSERT_DEFINED == 1 ) + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) + #define portDISABLE_INTERRUPTS() if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile( "MVTIPL %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) +#else + #define portDISABLE_INTERRUPTS() __asm volatile ( "MVTIPL %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) +#endif + +/* Critical nesting counts are stored in the TCB. */ +#define portCRITICAL_NESTING_IN_TCB ( 1 ) + +/* The critical nesting functions defined within tasks.c. */ +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() + +/* As this port allows interrupt nesting... */ +uint32_t ulPortGetIPL( void ) __attribute__( ( naked ) ); +void vPortSetIPL( uint32_t ulNewIPL ) __attribute__( ( naked ) ); +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/*-----------------------------------------------------------*/ + +/* If configUSE_TASK_DPFPU_SUPPORT is set to 1 (or left undefined) then tasks are + * created without a DPFPU context and must call vPortTaskUsesDPFPU() to give + * themselves a DPFPU context before using any DPFPU instructions. If + * configUSE_TASK_DPFPU_SUPPORT is set to 2 then all tasks will have a DPFPU context + * by default. */ +#if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) + void vPortTaskUsesDPFPU( void ); +#else + +/* Each task has a DPFPU context already, so define this function away to + * nothing to prevent it being called accidentally. */ + #define vPortTaskUsesDPFPU() +#endif +#define portTASK_USES_DPFPU() vPortTaskUsesDPFPU() + +/* Definition to allow compatibility with existing FreeRTOS Demo using flop.c. */ +#define portTASK_USES_FLOATING_POINT() vPortTaskUsesDPFPU() + +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/RX700v3_DPFPU/readme.txt b/portable/GCC/RX700v3_DPFPU/readme.txt new file mode 100644 index 000000000..8dbc983fd --- /dev/null +++ b/portable/GCC/RX700v3_DPFPU/readme.txt @@ -0,0 +1,71 @@ +The following table shows which port is recommended to be used. + + +RX MCU Group CPU FPU FPU Port Layer + Core (Single (Double CC-RX GNURX ICCRX (*6) + Type Precision) Precision) + +RX110 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX111 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX113 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX130 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX13T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 + +RX210 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX21A RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX220 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX230,RX231 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23E-A RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23W RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24U RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 + +RX610 RXv1 Yes --- N/A (*4) N/A (*4) N/A (*4) +RX62N,RX621 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX630 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX634 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63N,RX631 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX64M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX65N,RX651 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX66N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX62T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX62G RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX66T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +RX71M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX72M RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +Notes: + +*1: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is not used, please define configSETUP_TICK_INTERRUPT() (in FreeRTOSConfig.h) and provide +the configuration function. Please be aware that port.c is hard coded to use CMT0 though it seems to be +configured to use any CMTn according to the definition of configTICK_VECTOR (in FreeRTOSConfig.h). + +*2: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is used, please modify port.c for the configuration. Please be aware that port.c is +hard coded to use CMT0 though it seems to be configured to use any CMTn according to the definition of +configTICK_VECTOR (in FreeRTOSConfig.h). + +*3: RX100 ports are also available. + +*4: RX600 ports use MVTIPL instruction but RX610 MCUs don't support this instruction. + +*5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h. + +#define configUSE_TASK_DPFPU_SUPPORT 0 + +*6: PriorityDefinitions.h has to be provided for port_asm.s in case of other than RX700v3_DPFPU port. +It contains two definitions of interrupt priority like the following. + +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + + +For more information about Renesas RX MCUs, please visit the following URL: + +https://www.renesas.com/products/microcontrollers-microprocessors/rx.html diff --git a/portable/GCC/STR75x/port.c b/portable/GCC/STR75x/port.c new file mode 100644 index 000000000..941b72b5f --- /dev/null +++ b/portable/GCC/STR75x/port.c @@ -0,0 +1,193 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ST STR75x ARM7 +* port. +*----------------------------------------------------------*/ + +/* Library includes. */ +#include "75x_tb.h" +#include "75x_eic.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to setup the initial stack. */ +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + +/* Prescale used on the timer clock when calculating the tick period. */ +#define portPRESCALE 20 + + +/*-----------------------------------------------------------*/ + +/* Setup the TB to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + StackType_t * pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + /* To ensure asserts in tasks.c don't fail, although in this case the assert + * is not really required. */ + pxTopOfStack--; + + /* Setup the initial stack of the task. The stack is set exactly as + * expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which in this case is the + * start of the task. The offset is added to make the return address appear + * as it would within an IRQ ISR. */ + *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + * R0. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The status register is set for system mode, with interrupts enabled. */ + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + + #ifdef THUMB_INTERWORK + { + /* We want the task to start in thumb mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + #endif + + pxTopOfStack--; + + /* Interrupt flags cannot always be stored on the stack and will + * instead be stored in a variable, which is then saved as part of the + * tasks context. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + extern void vPortISRStartFirstTask( void ); + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortISRStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + * is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ + EIC_IRQInitTypeDef EIC_IRQInitStructure; + TB_InitTypeDef TB_InitStructure; + + /* Setup the EIC for the TB. */ + EIC_IRQInitStructure.EIC_IRQChannelCmd = ENABLE; + EIC_IRQInitStructure.EIC_IRQChannel = TB_IRQChannel; + EIC_IRQInitStructure.EIC_IRQChannelPriority = 1; + EIC_IRQInit( &EIC_IRQInitStructure ); + + /* Setup the TB for the generation of the tick interrupt. */ + TB_InitStructure.TB_Mode = TB_Mode_Timing; + TB_InitStructure.TB_CounterMode = TB_CounterMode_Down; + TB_InitStructure.TB_Prescaler = portPRESCALE - 1; + TB_InitStructure.TB_AutoReload = ( ( configCPU_CLOCK_HZ / portPRESCALE ) / configTICK_RATE_HZ ); + TB_Init( &TB_InitStructure ); + + /* Enable TB Update interrupt */ + TB_ITConfig( TB_IT_Update, ENABLE ); + + /* Clear TB Update interrupt pending bit */ + TB_ClearITPendingBit( TB_IT_Update ); + + /* Enable TB */ + TB_Cmd( ENABLE ); +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/STR75x/portISR.c b/portable/GCC/STR75x/portISR.c new file mode 100644 index 000000000..110c22a80 --- /dev/null +++ b/portable/GCC/STR75x/portISR.c @@ -0,0 +1,178 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/*----------------------------------------------------------- +* Components that can be compiled to either ARM or THUMB mode are +* contained in port.c The ISR routines, which can only be compiled +* to ARM mode, are contained in this file. +*----------------------------------------------------------*/ + +/* + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + +volatile uint32_t ulCriticalNesting = 9999UL; + +/*-----------------------------------------------------------*/ + +/* + * The scheduler can only be started from ARM mode, hence the inclusion of this + * function here. + */ +void vPortISRStartFirstTask( void ); +/*-----------------------------------------------------------*/ + +void vPortISRStartFirstTask( void ) +{ + /* Simply start the scheduler. This is included here as it can only be + * called from ARM mode. */ + asm volatile ( \ + "LDR R0, =pxCurrentTCB \n\t" \ + "LDR R0, [R0] \n\t" \ + "LDR LR, [R0] \n\t" \ + \ + /* The critical nesting depth is the first item on the stack. */ \ + /* Load it into the ulCriticalNesting variable. */ \ + "LDR R0, =ulCriticalNesting \n\t" \ + "LDMFD LR!, {R1} \n\t" \ + "STR R1, [R0] \n\t" \ + \ + /* Get the SPSR from the stack. */ \ + "LDMFD LR!, {R0} \n\t" \ + "MSR SPSR, R0 \n\t" \ + \ + /* Restore all system mode registers for the task. */ \ + "LDMFD LR, {R0-R14}^ \n\t" \ + "NOP \n\t" \ + \ + /* Restore the return address. */ \ + "LDR LR, [LR, #+60] \n\t" \ + \ + /* And return - correcting the offset in the LR to obtain the */ \ + /* correct address. */ \ + "SUBS PC, LR, #4 \n\t" \ + ); +} +/*-----------------------------------------------------------*/ + +void vPortTickISR( void ) +{ + /* Increment the RTOS tick count, then look for the highest priority + * task that is ready to run. */ + if( xTaskIncrementTick() != pdFALSE ) + { + vTaskSwitchContext(); + } + + /* Ready for the next interrupt. */ + TB_ClearITPendingBit( TB_IT_Update ); +} + +/*-----------------------------------------------------------*/ + +/* + * The interrupt management utilities can only be called from ARM mode. When + * THUMB_INTERWORK is defined the utilities are defined as functions here to + * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then + * the utilities are defined as macros in portmacro.h - as per other ports. + */ +#ifdef THUMB_INTERWORK + + void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) ); + void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) ); + + void vPortDisableInterruptsFromThumb( void ) + { + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ + } + + void vPortEnableInterruptsFromThumb( void ) + { + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0} \n\t" /* Pop R0. */ + "BX R14" ); /* Return back to thumb. */ + } + +#endif /* THUMB_INTERWORK */ +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ + + /* Now that interrupts are disabled, ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + * re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Enable interrupts as per portEXIT_CRITICAL(). */ + asm volatile ( + "STMDB SP!, {R0} \n\t" /* Push R0. */ + "MRS R0, CPSR \n\t" /* Get CPSR. */ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ + "LDMIA SP!, {R0}" ); /* Pop R0. */ + } + } +} diff --git a/portable/GCC/STR75x/portmacro.h b/portable/GCC/STR75x/portmacro.h new file mode 100644 index 000000000..81a30dcb3 --- /dev/null +++ b/portable/GCC/STR75x/portmacro.h @@ -0,0 +1,152 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portYIELD() asm volatile ( "SWI 0" ) +#define portNOP() asm volatile ( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ + +/* + * The interrupt management utilities can only be called from ARM mode. When + * THUMB_INTERWORK is defined the utilities are defined as functions in + * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not + * defined then the utilities are defined as macros here - as per other ports. + */ + +#ifdef THUMB_INTERWORK + + extern void vPortDisableInterruptsFromThumb( void ) __attribute__( ( naked ) ); + extern void vPortEnableInterruptsFromThumb( void ) __attribute__( ( naked ) ); + + #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb() + #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb() + +#else + + #define portDISABLE_INTERRUPTS() \ + asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ + + #define portENABLE_INTERRUPTS() \ + asm volatile ( \ + "STMDB SP!, {R0} \n\t" /* Push R0. */ \ + "MRS R0, CPSR \n\t" /* Get CPSR. */ \ + "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \ + "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ + "LDMIA SP!, {R0} " ) /* Pop R0. */ + +#endif /* THUMB_INTERWORK */ + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + { \ + extern void vTaskSwitchContext( void ); \ + \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + vTaskSwitchContext(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/TriCore_1782/port.c b/portable/GCC/TriCore_1782/port.c new file mode 100644 index 000000000..1579d8e72 --- /dev/null +++ b/portable/GCC/TriCore_1782/port.c @@ -0,0 +1,547 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include +#include + +/* TriCore specific includes. */ +#include +#include +#include +#include + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "list.h" + +#if configCHECK_FOR_STACK_OVERFLOW > 0 + #error "Stack checking cannot be used with this port, as, unlike most ports, the pxTopOfStack member of the TCB is consumed CSA. CSA starvation, loosely equivalent to stack overflow, will result in a trap exception." + /* The stack pointer is accessible using portCSA_TO_ADDRESS( portCSA_TO_ADDRESS( pxCurrentTCB->pxTopOfStack )[ 0 ] )[ 2 ]; */ +#endif /* configCHECK_FOR_STACK_OVERFLOW */ + + +/*-----------------------------------------------------------*/ + +/* System register Definitions. */ +#define portSYSTEM_PROGRAM_STATUS_WORD ( 0x000008FFUL ) /* Supervisor Mode, MPU Register Set 0 and Call Depth Counting disabled. */ +#define portINITIAL_PRIVILEGED_PROGRAM_STATUS_WORD ( 0x000014FFUL ) /* IO Level 1, MPU Register Set 1 and Call Depth Counting disabled. */ +#define portINITIAL_UNPRIVILEGED_PROGRAM_STATUS_WORD ( 0x000010FFUL ) /* IO Level 0, MPU Register Set 1 and Call Depth Counting disabled. */ +#define portINITIAL_PCXI_UPPER_CONTEXT_WORD ( 0x00C00000UL ) /* The lower 20 bits identify the CSA address. */ +#define portINITIAL_SYSCON ( 0x00000000UL ) /* MPU Disable. */ + +/* CSA manipulation macros. */ +#define portCSA_FCX_MASK ( 0x000FFFFFUL ) + +/* OS Interrupt and Trap mechanisms. */ +#define portRESTORE_PSW_MASK ( ~( 0x000000FFUL ) ) +#define portSYSCALL_TRAP ( 6 ) + +/* Each CSA contains 16 words of data. */ +#define portNUM_WORDS_IN_CSA ( 16 ) + +/* The interrupt enable bit in the PCP_SRC register. */ +#define portENABLE_CPU_INTERRUPT ( 1U << 12U ) +/*-----------------------------------------------------------*/ + +/* + * Perform any hardware configuration necessary to generate the tick interrupt. + */ +static void prvSystemTickHandler( int ) __attribute__( ( longcall ) ); +static void prvSetupTimerInterrupt( void ); + +/* + * Trap handler for yields. + */ +static void prvTrapYield( int iTrapIdentification ); + +/* + * Priority 1 interrupt handler for yields pended from an interrupt. + */ +static void prvInterruptYield( int iTrapIdentification ); + +/*-----------------------------------------------------------*/ + +/* This reference is required by the save/restore context macros. */ +extern volatile uint32_t * pxCurrentTCB; + +/* Precalculate the compare match value at compile time. */ +static const uint32_t ulCompareMatchValue = ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ ); + +/*-----------------------------------------------------------*/ + +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + uint32_t * pulUpperCSA = NULL; + uint32_t * pulLowerCSA = NULL; + + /* 16 Address Registers (4 Address registers are global), 16 Data + * Registers, and 3 System Registers. + * + * There are 3 registers that track the CSAs. + * FCX points to the head of globally free set of CSAs. + * PCX for the task needs to point to Lower->Upper->NULL arrangement. + * LCX points to the last free CSA so that corrective action can be taken. + * + * Need two CSAs to store the context of a task. + * The upper context contains D8-D15, A10-A15, PSW and PCXI->NULL. + * The lower context contains D0-D7, A2-A7, A11 and PCXI->UpperContext. + * The pxCurrentTCB->pxTopOfStack points to the Lower Context RSLCX matching the initial BISR. + * The Lower Context points to the Upper Context ready for the return from the interrupt handler. + * + * The Real stack pointer for the task is stored in the A10 which is restored + * with the upper context. */ + + /* Have to disable interrupts here because the CSAs are going to be + * manipulated. */ + portENTER_CRITICAL(); + { + /* DSync to ensure that buffering is not a problem. */ + _dsync(); + + /* Consume two free CSAs. */ + pulLowerCSA = portCSA_TO_ADDRESS( __MFCR( $FCX ) ); + + if( NULL != pulLowerCSA ) + { + /* The Lower Links to the Upper. */ + pulUpperCSA = portCSA_TO_ADDRESS( pulLowerCSA[ 0 ] ); + } + + /* Check that we have successfully reserved two CSAs. */ + if( ( NULL != pulLowerCSA ) && ( NULL != pulUpperCSA ) ) + { + /* Remove the two consumed CSAs from the free CSA list. */ + _disable(); + _dsync(); + _mtcr( $FCX, pulUpperCSA[ 0 ] ); + _isync(); + _enable(); + } + else + { + /* Simply trigger a context list depletion trap. */ + _svlcx(); + } + } + portEXIT_CRITICAL(); + + /* Clear the upper CSA. */ + memset( pulUpperCSA, 0, portNUM_WORDS_IN_CSA * sizeof( uint32_t ) ); + + /* Upper Context. */ + pulUpperCSA[ 2 ] = ( uint32_t ) pxTopOfStack; /* A10; Stack Return aka Stack Pointer */ + pulUpperCSA[ 1 ] = portSYSTEM_PROGRAM_STATUS_WORD; /* PSW */ + + /* Clear the lower CSA. */ + memset( pulLowerCSA, 0, portNUM_WORDS_IN_CSA * sizeof( uint32_t ) ); + + /* Lower Context. */ + pulLowerCSA[ 8 ] = ( uint32_t ) pvParameters; /* A4; Address Type Parameter Register */ + pulLowerCSA[ 1 ] = ( uint32_t ) pxCode; /* A11; Return Address aka RA */ + + /* PCXI pointing to the Upper context. */ + pulLowerCSA[ 0 ] = ( portINITIAL_PCXI_UPPER_CONTEXT_WORD | ( uint32_t ) portADDRESS_TO_CSA( pulUpperCSA ) ); + + /* Save the link to the CSA in the top of stack. */ + pxTopOfStack = ( uint32_t * ) portADDRESS_TO_CSA( pulLowerCSA ); + + /* DSync to ensure that buffering is not a problem. */ + _dsync(); + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +int32_t xPortStartScheduler( void ) +{ + extern void vTrapInstallHandlers( void ); + uint32_t ulMFCR = 0UL; + uint32_t * pulUpperCSA = NULL; + uint32_t * pulLowerCSA = NULL; + + /* Interrupts at or below configMAX_SYSCALL_INTERRUPT_PRIORITY are disable + * when this function is called. */ + + /* Set-up the timer interrupt. */ + prvSetupTimerInterrupt(); + + /* Install the Trap Handlers. */ + vTrapInstallHandlers(); + + /* Install the Syscall Handler for yield calls. */ + if( 0 == _install_trap_handler( portSYSCALL_TRAP, prvTrapYield ) ) + { + /* Failed to install the yield handler, force an assert. */ + configASSERT( ( ( volatile void * ) NULL ) ); + } + + /* Enable then install the priority 1 interrupt for pending context + * switches from an ISR. See mod_SRC in the TriCore manual. */ + CPU_SRC0.reg = ( portENABLE_CPU_INTERRUPT ) | ( configKERNEL_YIELD_PRIORITY ); + + if( 0 == _install_int_handler( configKERNEL_YIELD_PRIORITY, prvInterruptYield, 0 ) ) + { + /* Failed to install the yield handler, force an assert. */ + configASSERT( ( ( volatile void * ) NULL ) ); + } + + _disable(); + + /* Load the initial SYSCON. */ + _mtcr( $SYSCON, portINITIAL_SYSCON ); + _isync(); + + /* ENDINIT has already been applied in the 'cstart.c' code. */ + + /* Clear the PSW.CDC to enable the use of an RFE without it generating an + * exception because this code is not genuinely in an exception. */ + ulMFCR = __MFCR( $PSW ); + ulMFCR &= portRESTORE_PSW_MASK; + _dsync(); + _mtcr( $PSW, ulMFCR ); + _isync(); + + /* Finally, perform the equivalent of a portRESTORE_CONTEXT() */ + pulLowerCSA = portCSA_TO_ADDRESS( ( *pxCurrentTCB ) ); + pulUpperCSA = portCSA_TO_ADDRESS( pulLowerCSA[ 0 ] ); + _dsync(); + _mtcr( $PCXI, *pxCurrentTCB ); + _isync(); + _nop(); + _rslcx(); + _nop(); + + /* Return to the first task selected to execute. */ + __asm volatile ( "rfe" ); + + /* Will not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ + /* Set-up the clock divider. */ + unlock_wdtcon(); + { + /* Wait until access to Endint protected register is enabled. */ + while( 0 != ( WDT_CON0.reg & 0x1UL ) ) + { + } + + /* RMC == 1 so STM Clock == FPI */ + STM_CLC.reg = ( 1UL << 8 ); + } + lock_wdtcon(); + + /* Determine how many bits are used without changing other bits in the CMCON register. */ + STM_CMCON.reg &= ~( 0x1fUL ); + STM_CMCON.reg |= ( 0x1fUL - __CLZ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ ) ); + + /* Take into account the current time so a tick doesn't happen immediately. */ + STM_CMP0.reg = ulCompareMatchValue + STM_TIM0.reg; + + if( 0 != _install_int_handler( configKERNEL_INTERRUPT_PRIORITY, prvSystemTickHandler, 0 ) ) + { + /* Set-up the interrupt. */ + STM_SRC0.reg = ( configKERNEL_INTERRUPT_PRIORITY | 0x00005000UL ); + + /* Enable the Interrupt. */ + STM_ISRR.reg &= ~( 0x03UL ); + STM_ISRR.reg |= 0x1UL; + STM_ISRR.reg &= ~( 0x07UL ); + STM_ICR.reg |= 0x1UL; + } + else + { + /* Failed to install the Tick Interrupt. */ + configASSERT( ( ( volatile void * ) NULL ) ); + } +} +/*-----------------------------------------------------------*/ + +static void prvSystemTickHandler( int iArg ) +{ + uint32_t ulSavedInterruptMask; + uint32_t * pxUpperCSA = NULL; + uint32_t xUpperCSA = 0UL; + extern volatile uint32_t * pxCurrentTCB; + int32_t lYieldRequired; + + /* Just to avoid compiler warnings about unused parameters. */ + ( void ) iArg; + + /* Clear the interrupt source. */ + STM_ISRR.reg = 1UL; + + /* Reload the Compare Match register for X ticks into the future. + * + * If critical section or interrupt nesting budgets are exceeded, then + * it is possible that the calculated next compare match value is in the + * past. If this occurs (unlikely), it is possible that the resulting + * time slippage will exceed a single tick period. Any adverse effect of + * this is time bounded by the fact that only the first n bits of the 56 bit + * STM timer are being used for a compare match, so another compare match + * will occur after an overflow in just those n bits (not the entire 56 bits). + * As an example, if the peripheral clock is 75MHz, and the tick rate is 1KHz, + * a missed tick could result in the next tick interrupt occurring within a + * time that is 1.7 times the desired period. The fact that this is greater + * than a single tick period is an effect of using a timer that cannot be + * automatically reset, in hardware, by the occurrence of a tick interrupt. + * Changing the tick source to a timer that has an automatic reset on compare + * match (such as a GPTA timer) will reduce the maximum possible additional + * period to exactly 1 times the desired period. */ + STM_CMP0.reg += ulCompareMatchValue; + + /* Kernel API calls require Critical Sections. */ + ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR(); + { + /* Increment the Tick. */ + lYieldRequired = xTaskIncrementTick(); + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask ); + + if( lYieldRequired != pdFALSE ) + { + /* Save the context of a task. + * The upper context is automatically saved when entering a trap or interrupt. + * Need to save the lower context as well and copy the PCXI CSA ID into + * pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the + * TCB of a task. + * + * Call vTaskSwitchContext to select the next task, note that this changes the + * value of pxCurrentTCB so that it needs to be reloaded. + * + * Call vPortSetMPURegisterSetOne to change the MPU mapping for the task + * that has just been switched in. + * + * Load the context of the task. + * Need to restore the lower context by loading the CSA from + * pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack). + * In the Interrupt handler post-amble, RSLCX will restore the lower context + * of the task. RFE will restore the upper context of the task, jump to the + * return address and restore the previous state of interrupts being + * enabled/disabled. */ + _disable(); + _dsync(); + xUpperCSA = __MFCR( $PCXI ); + pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA ); + *pxCurrentTCB = pxUpperCSA[ 0 ]; + vTaskSwitchContext(); + pxUpperCSA[ 0 ] = *pxCurrentTCB; + CPU_SRC0.bits.SETR = 0; + _isync(); + } +} +/*-----------------------------------------------------------*/ + +/* + * When a task is deleted, it is yielded permanently until the IDLE task + * has an opportunity to reclaim the memory that that task was using. + * Typically, the memory used by a task is the TCB and Stack but in the + * TriCore this includes the CSAs that were consumed as part of the Call + * Stack. These CSAs can only be returned to the Globally Free Pool when + * they are not part of the current Call Stack, hence, delaying the + * reclamation until the IDLE task is freeing the task's other resources. + * This function uses the head of the linked list of CSAs (from when the + * task yielded for the last time) and finds the tail (the very bottom of + * the call stack) and inserts this list at the head of the Free list, + * attaching the existing Free List to the tail of the reclaimed call stack. + * + * NOTE: the IDLE task needs processing time to complete this function + * and in heavily loaded systems, the Free CSAs may be consumed faster + * than they can be freed assuming that tasks are being spawned and + * deleted frequently. + */ +void vPortReclaimCSA( uint32_t * pxTCB ) +{ + uint32_t pxHeadCSA, pxTailCSA, pxFreeCSA; + uint32_t * pulNextCSA; + + /* A pointer to the first CSA in the list of CSAs consumed by the task is + * stored in the first element of the tasks TCB structure (where the stack + * pointer would be on a traditional stack based architecture). */ + pxHeadCSA = ( *pxTCB ) & portCSA_FCX_MASK; + + /* Mask off everything in the CSA link field other than the address. If + * the address is NULL, then the CSA is not linking anywhere and there is + * nothing to do. */ + pxTailCSA = pxHeadCSA; + + /* Convert the link value to contain just a raw address and store this + * in a local variable. */ + pulNextCSA = portCSA_TO_ADDRESS( pxTailCSA ); + + /* Iterate over the CSAs that were consumed as part of the task. The + * first field in the CSA is the pointer to then next CSA. Mask off + * everything in the pointer to the next CSA, other than the link address. + * If this is NULL, then the CSA currently being pointed to is the last in + * the chain. */ + while( 0UL != ( pulNextCSA[ 0 ] & portCSA_FCX_MASK ) ) + { + /* Clear all bits of the pointer to the next in the chain, other + * than the address bits themselves. */ + pulNextCSA[ 0 ] = pulNextCSA[ 0 ] & portCSA_FCX_MASK; + + /* Move the pointer to point to the next CSA in the list. */ + pxTailCSA = pulNextCSA[ 0 ]; + + /* Update the local pointer to the CSA. */ + pulNextCSA = portCSA_TO_ADDRESS( pxTailCSA ); + } + + _disable(); + { + /* Look up the current free CSA head. */ + _dsync(); + pxFreeCSA = __MFCR( $FCX ); + + /* Join the current Free onto the Tail of what is being reclaimed. */ + portCSA_TO_ADDRESS( pxTailCSA )[ 0 ] = pxFreeCSA; + + /* Move the head of the reclaimed into the Free. */ + _dsync(); + _mtcr( $FCX, pxHeadCSA ); + _isync(); + } + _enable(); +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Nothing to do. Unlikely to want to end. */ +} +/*-----------------------------------------------------------*/ + +static void prvTrapYield( int iTrapIdentification ) +{ + uint32_t * pxUpperCSA = NULL; + uint32_t xUpperCSA = 0UL; + extern volatile uint32_t * pxCurrentTCB; + + switch( iTrapIdentification ) + { + case portSYSCALL_TASK_YIELD: + + /* Save the context of a task. + * The upper context is automatically saved when entering a trap or interrupt. + * Need to save the lower context as well and copy the PCXI CSA ID into + * pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the + * TCB of a task. + * + * Call vTaskSwitchContext to select the next task, note that this changes the + * value of pxCurrentTCB so that it needs to be reloaded. + * + * Call vPortSetMPURegisterSetOne to change the MPU mapping for the task + * that has just been switched in. + * + * Load the context of the task. + * Need to restore the lower context by loading the CSA from + * pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack). + * In the Interrupt handler post-amble, RSLCX will restore the lower context + * of the task. RFE will restore the upper context of the task, jump to the + * return address and restore the previous state of interrupts being + * enabled/disabled. */ + _disable(); + _dsync(); + xUpperCSA = __MFCR( $PCXI ); + pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA ); + *pxCurrentTCB = pxUpperCSA[ 0 ]; + vTaskSwitchContext(); + pxUpperCSA[ 0 ] = *pxCurrentTCB; + CPU_SRC0.bits.SETR = 0; + _isync(); + break; + + default: + /* Unimplemented trap called. */ + configASSERT( ( ( volatile void * ) NULL ) ); + break; + } +} +/*-----------------------------------------------------------*/ + +static void prvInterruptYield( int iId ) +{ + uint32_t * pxUpperCSA = NULL; + uint32_t xUpperCSA = 0UL; + extern volatile uint32_t * pxCurrentTCB; + + /* Just to remove compiler warnings. */ + ( void ) iId; + + /* Save the context of a task. + * The upper context is automatically saved when entering a trap or interrupt. + * Need to save the lower context as well and copy the PCXI CSA ID into + * pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the + * TCB of a task. + * + * Call vTaskSwitchContext to select the next task, note that this changes the + * value of pxCurrentTCB so that it needs to be reloaded. + * + * Call vPortSetMPURegisterSetOne to change the MPU mapping for the task + * that has just been switched in. + * + * Load the context of the task. + * Need to restore the lower context by loading the CSA from + * pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack). + * In the Interrupt handler post-amble, RSLCX will restore the lower context + * of the task. RFE will restore the upper context of the task, jump to the + * return address and restore the previous state of interrupts being + * enabled/disabled. */ + _disable(); + _dsync(); + xUpperCSA = __MFCR( $PCXI ); + pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA ); + *pxCurrentTCB = pxUpperCSA[ 0 ]; + vTaskSwitchContext(); + pxUpperCSA[ 0 ] = *pxCurrentTCB; + CPU_SRC0.bits.SETR = 0; + _isync(); +} +/*-----------------------------------------------------------*/ + +uint32_t uxPortSetInterruptMaskFromISR( void ) +{ + uint32_t uxReturn = 0UL; + + _disable(); + uxReturn = __MFCR( $ICR ); + _mtcr( $ICR, ( ( uxReturn & ~portCCPN_MASK ) | configMAX_SYSCALL_INTERRUPT_PRIORITY ) ); + _isync(); + _enable(); + + /* Return just the interrupt mask bits. */ + return( uxReturn & portCCPN_MASK ); +} +/*-----------------------------------------------------------*/ diff --git a/portable/GCC/TriCore_1782/portmacro.h b/portable/GCC/TriCore_1782/portmacro.h new file mode 100644 index 000000000..c1e0b14d5 --- /dev/null +++ b/portable/GCC/TriCore_1782/portmacro.h @@ -0,0 +1,186 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/* System Includes. */ +#include +#include + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*---------------------------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +#define portNOP() __asm volatile ( " nop " ) +#define portCRITICAL_NESTING_IN_TCB 1 +#define portRESTORE_FIRST_TASK_PRIORITY_LEVEL 1 + + +/*---------------------------------------------------------------------------*/ + +typedef struct MPU_SETTINGS +{ + uint32_t ulNotUsed; +} xMPU_SETTINGS; + +/* Define away the instruction from the Restore Context Macro. */ +#define portPRIVILEGE_BIT 0x0UL + +#define portCCPN_MASK ( 0x000000FFUL ) + +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() +/*---------------------------------------------------------------------------*/ + +/* CSA Manipulation. */ +#define portCSA_TO_ADDRESS( pCSA ) ( ( uint32_t * ) ( ( ( ( pCSA ) & 0x000F0000 ) << 12 ) | ( ( ( pCSA ) & 0x0000FFFF ) << 6 ) ) ) +#define portADDRESS_TO_CSA( pAddress ) ( ( uint32_t ) ( ( ( ( ( uint32_t ) ( pAddress ) ) & 0xF0000000 ) >> 12 ) | ( ( ( uint32_t ) ( pAddress ) & 0x003FFFC0 ) >> 6 ) ) ) +/*---------------------------------------------------------------------------*/ + +#define portYIELD() _syscall( 0 ) +/* Port Restore is implicit in the platform when the function is returned from the original PSW is automatically replaced. */ +#define portSYSCALL_TASK_YIELD 0 +#define portSYSCALL_RAISE_PRIORITY 1 +/*---------------------------------------------------------------------------*/ + +/* Critical section management. */ + +/* Set ICR.CCPN to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ +#define portDISABLE_INTERRUPTS() \ + { \ + uint32_t ulICR; \ + _disable(); \ + ulICR = __MFCR( $ICR ); /* Get current ICR value. */ \ + ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \ + ulICR |= configMAX_SYSCALL_INTERRUPT_PRIORITY; /* Set mask bits to required priority mask. */ \ + _mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \ + _isync(); \ + _enable(); \ + } + +/* Clear ICR.CCPN to allow all interrupt priorities. */ +#define portENABLE_INTERRUPTS() \ + { \ + uint32_t ulICR; \ + _disable(); \ + ulICR = __MFCR( $ICR ); /* Get current ICR value. */ \ + ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \ + _mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \ + _isync(); \ + _enable(); \ + } + +/* Set ICR.CCPN to uxSavedMaskValue. */ +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedMaskValue ) \ + { \ + uint32_t ulICR; \ + _disable(); \ + ulICR = __MFCR( $ICR ); /* Get current ICR value. */ \ + ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \ + ulICR |= uxSavedMaskValue; /* Set mask bits to previously saved mask value. */ \ + _mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \ + _isync(); \ + _enable(); \ + } + + +/* Set ICR.CCPN to configMAX_SYSCALL_INTERRUPT_PRIORITY */ +extern uint32_t uxPortSetInterruptMaskFromISR( void ); +#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR() + +/* Pend a priority 1 interrupt, which will take care of the context switch. */ +#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) do { if( xHigherPriorityTaskWoken != pdFALSE ) { CPU_SRC0.bits.SETR = 1; _isync(); } } while( 0 ) + +/*---------------------------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*---------------------------------------------------------------------------*/ + +/* + * Port specific clean up macro required to free the CSAs that were consumed by + * a task that has since been deleted. + */ +void vPortReclaimCSA( uint32_t * pxTCB ); +#define portCLEAN_UP_TCB( pxTCB ) vPortReclaimCSA( ( uint32_t * ) ( pxTCB ) ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/GCC/TriCore_1782/porttrap.c b/portable/GCC/TriCore_1782/porttrap.c new file mode 100644 index 000000000..f0600d754 --- /dev/null +++ b/portable/GCC/TriCore_1782/porttrap.c @@ -0,0 +1,282 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Kernel includes. */ +#include "FreeRTOS.h" + +/* Machine includes */ +#include +#include +#include +/*---------------------------------------------------------------------------*/ + +/* + * This reference is required by the Save/Restore Context Macros. + */ +extern volatile uint32_t * pxCurrentTCB; +/*-----------------------------------------------------------*/ + +/* + * This file contains base definitions for all of the possible traps in the system. + * It is suggested to provide implementations for all of the traps but for + * the time being they simply trigger a DEBUG instruction so that it is easy + * to see what caused a particular trap. + * + * Trap Class 6, the SYSCALL, is used exclusively by the operating system. + */ + +/* The Trap Classes. */ +#define portMMU_TRAP 0 +#define portIPT_TRAP 1 +#define portIE_TRAP 2 +#define portCM_TRAP 3 +#define portSBP_TRAP 4 +#define portASSERT_TRAP 5 +#define portNMI_TRAP 7 + +/* MMU Trap Identifications. */ +#define portTIN_MMU_VIRTUAL_ADDRESS_FILL 0 +#define portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION 1 + +/* Internal Protection Trap Identifications. */ +#define portTIN_IPT_PRIVILEGED_INSTRUCTION 1 +#define portTIN_IPT_MEMORY_PROTECTION_READ 2 +#define portTIN_IPT_MEMORY_PROTECTION_WRITE 3 +#define portTIN_IPT_MEMORY_PROTECTION_EXECUTION 4 +#define portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS 5 +#define portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS 6 +#define portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION 7 + +/* Instruction Error Trap Identifications. */ +#define portTIN_IE_ILLEGAL_OPCODE 1 +#define portTIN_IE_UNIMPLEMENTED_OPCODE 2 +#define portTIN_IE_INVALID_OPERAND 3 +#define portTIN_IE_DATA_ADDRESS_ALIGNMENT 4 +#define portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS 5 + +/* Context Management Trap Identifications. */ +#define portTIN_CM_FREE_CONTEXT_LIST_DEPLETION 1 +#define portTIN_CM_CALL_DEPTH_OVERFLOW 2 +#define portTIN_CM_CALL_DEPTH_UNDEFLOW 3 +#define portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW 4 +#define portTIN_CM_CALL_STACK_UNDERFLOW 5 +#define portTIN_CM_CONTEXT_TYPE 6 +#define portTIN_CM_NESTING_ERROR 7 + +/* System Bus and Peripherals Trap Identifications. */ +#define portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR 1 +#define portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR 2 +#define portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR 3 +#define portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR 4 +#define portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR 5 +#define portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR 6 + +/* Assertion Trap Identifications. */ +#define portTIN_ASSERT_ARITHMETIC_OVERFLOW 1 +#define portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW 2 + +/* Non-maskable Interrupt Trap Identifications. */ +#define portTIN_NMI_NON_MASKABLE_INTERRUPT 0 +/*---------------------------------------------------------------------------*/ + +void vMMUTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) ); +void vInternalProtectionTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) ); +void vInstructionErrorTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) ); +void vContextManagementTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) ); +void vSystemBusAndPeripheralsTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) ); +void vAssertionTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) ); +void vNonMaskableInterruptTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) ); +/*---------------------------------------------------------------------------*/ + +void vTrapInstallHandlers( void ) +{ + if( 0 == _install_trap_handler( portMMU_TRAP, vMMUTrap ) ) + { + _debug(); + } + + if( 0 == _install_trap_handler( portIPT_TRAP, vInternalProtectionTrap ) ) + { + _debug(); + } + + if( 0 == _install_trap_handler( portIE_TRAP, vInstructionErrorTrap ) ) + { + _debug(); + } + + if( 0 == _install_trap_handler( portCM_TRAP, vContextManagementTrap ) ) + { + _debug(); + } + + if( 0 == _install_trap_handler( portSBP_TRAP, vSystemBusAndPeripheralsTrap ) ) + { + _debug(); + } + + if( 0 == _install_trap_handler( portASSERT_TRAP, vAssertionTrap ) ) + { + _debug(); + } + + if( 0 == _install_trap_handler( portNMI_TRAP, vNonMaskableInterruptTrap ) ) + { + _debug(); + } +} +/*-----------------------------------------------------------*/ + +void vMMUTrap( int iTrapIdentification ) +{ + switch( iTrapIdentification ) + { + case portTIN_MMU_VIRTUAL_ADDRESS_FILL: + case portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION: + default: + _debug(); + break; + } +} +/*---------------------------------------------------------------------------*/ + +void vInternalProtectionTrap( int iTrapIdentification ) +{ + /* Deliberate fall through to default. */ + switch( iTrapIdentification ) + { + case portTIN_IPT_PRIVILEGED_INSTRUCTION: + /* Instruction is not allowed at current execution level, eg DISABLE at User-0. */ + + case portTIN_IPT_MEMORY_PROTECTION_READ: + /* Load word using invalid address. */ + + case portTIN_IPT_MEMORY_PROTECTION_WRITE: + /* Store Word using invalid address. */ + + case portTIN_IPT_MEMORY_PROTECTION_EXECUTION: + /* PC jumped to an address outside of the valid range. */ + + case portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS: + /* Access to a peripheral denied at current execution level. */ + + case portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS: + /* NULL Pointer. */ + + case portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION: + /* Tried to modify a global address pointer register. */ + + default: + + pxCurrentTCB[ 0 ] = __MFCR( $PCXI ); + _debug(); + break; + } +} +/*---------------------------------------------------------------------------*/ + +void vInstructionErrorTrap( int iTrapIdentification ) +{ + /* Deliberate fall through to default. */ + switch( iTrapIdentification ) + { + case portTIN_IE_ILLEGAL_OPCODE: + case portTIN_IE_UNIMPLEMENTED_OPCODE: + case portTIN_IE_INVALID_OPERAND: + case portTIN_IE_DATA_ADDRESS_ALIGNMENT: + case portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS: + default: + _debug(); + break; + } +} +/*---------------------------------------------------------------------------*/ + +void vContextManagementTrap( int iTrapIdentification ) +{ + /* Deliberate fall through to default. */ + switch( iTrapIdentification ) + { + case portTIN_CM_FREE_CONTEXT_LIST_DEPLETION: + case portTIN_CM_CALL_DEPTH_OVERFLOW: + case portTIN_CM_CALL_DEPTH_UNDEFLOW: + case portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW: + case portTIN_CM_CALL_STACK_UNDERFLOW: + case portTIN_CM_CONTEXT_TYPE: + case portTIN_CM_NESTING_ERROR: + default: + _debug(); + break; + } +} +/*---------------------------------------------------------------------------*/ + +void vSystemBusAndPeripheralsTrap( int iTrapIdentification ) +{ + /* Deliberate fall through to default. */ + switch( iTrapIdentification ) + { + case portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR: + case portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR: + case portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR: + case portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR: + case portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR: + case portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR: + default: + _debug(); + break; + } +} +/*---------------------------------------------------------------------------*/ + +void vAssertionTrap( int iTrapIdentification ) +{ + /* Deliberate fall through to default. */ + switch( iTrapIdentification ) + { + case portTIN_ASSERT_ARITHMETIC_OVERFLOW: + case portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW: + default: + _debug(); + break; + } +} +/*---------------------------------------------------------------------------*/ + +void vNonMaskableInterruptTrap( int iTrapIdentification ) +{ + /* Deliberate fall through to default. */ + switch( iTrapIdentification ) + { + case portTIN_NMI_NON_MASKABLE_INTERRUPT: + default: + _debug(); + break; + } +} +/*---------------------------------------------------------------------------*/ diff --git a/portable/IAR/78K0R/ISR_Support.h b/portable/IAR/78K0R/ISR_Support.h new file mode 100644 index 000000000..b5a1f4d1d --- /dev/null +++ b/portable/IAR/78K0R/ISR_Support.h @@ -0,0 +1,112 @@ +; /* + * ; * FreeRTOS Kernel + * ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * ; * + * ; * SPDX-License-Identifier: MIT + * ; * + * ; * Permission is hereby granted, free of charge, to any person obtaining a copy of + * ; * this software and associated documentation files (the "Software"), to deal in + * ; * the Software without restriction, including without limitation the rights to + * ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * ; * the Software, and to permit persons to whom the Software is furnished to do so, + * ; * subject to the following conditions: + * ; * + * ; * The above copyright notice and this permission notice shall be included in all + * ; * copies or substantial portions of the Software. + * ; * + * ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * ; * + * ; * https://www.FreeRTOS.org + * ; * https://github.com/FreeRTOS + * ; * + * ; */ + +#include "FreeRTOSConfig.h" + +; +Variables used by scheduler +; +------------------------------------------------------------------------------ +EXTERN pxCurrentTCB +EXTERN usCriticalNesting + +; +------------------------------------------------------------------------------ +; +portSAVE_CONTEXT MACRO +; +Saves the context of the general purpose registers, CS and ES( only in far + ; + memory mode ) registers the usCriticalNesting Value and the Stack Pointer +; +of the active Task onto the task stack +; +------------------------------------------------------------------------------ +portSAVE_CONTEXT MACRO + +PUSH AX; +Save AX Register to stack. + PUSH HL +MOV A, CS; +Save CS register. + XCH A, X +MOV A, ES; +Save ES register. + PUSH AX +PUSH DE; +Save the remaining general purpose registers. + PUSH BC +MOVW AX, usCriticalNesting; +Save the usCriticalNesting value. + PUSH AX +MOVW AX, pxCurrentTCB; +Save the Stack pointer. + MOVW HL, AX +MOVW AX, SP + MOVW[ HL ], AX + ENDM +; +------------------------------------------------------------------------------ + +; +------------------------------------------------------------------------------ +; +portRESTORE_CONTEXT MACRO +; +Restores the task Stack Pointer then use this to restore usCriticalNesting, +; +general purpose registers and the CS and ES( only in far memory mode ) +; +of the selected task from the task stack +; +------------------------------------------------------------------------------ +portRESTORE_CONTEXT MACRO +MOVW AX, pxCurrentTCB; +Restore the Stack pointer. + MOVW HL, AX +MOVW AX, [ HL ] +MOVW SP, AX +POP AX; +Restore usCriticalNesting value. + MOVW usCriticalNesting, AX +POP BC; +Restore the necessary general purpose registers. + POP DE +POP AX; +Restore the ES register. + MOV ES, A +XCH A, X; +Restore the CS register. + MOV CS, A +POP HL; +Restore general purpose register HL. + POP AX; +Restore AX. + ENDM +; +------------------------------------------------------------------------------ diff --git a/portable/IAR/78K0R/port.c b/portable/IAR/78K0R/port.c new file mode 100644 index 000000000..3183b89ab --- /dev/null +++ b/portable/IAR/78K0R/port.c @@ -0,0 +1,227 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* The critical nesting value is initialised to a non zero value to ensure + * interrupts don't accidentally become enabled before the scheduler is started. */ +#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 ) + +/* Initial PSW value allocated to a newly created task. + * 1100011000000000 + * ||||||||-------------- Fill byte + * |||||||--------------- Carry Flag cleared + * |||||----------------- In-service priority Flags set to low level + * ||||------------------ Register bank Select 0 Flag cleared + * |||------------------- Auxiliary Carry Flag cleared + * ||-------------------- Register bank Select 1 Flag cleared + * |--------------------- Zero Flag set + * ---------------------- Global Interrupt Flag set (enabled) + */ +#define portPSW ( 0xc6UL ) + +/* We require the address of the pxCurrentTCB variable, but don't want to know + * any details of its type. */ +typedef void TCB_t; +extern volatile TCB_t * volatile pxCurrentTCB; + +/* Most ports implement critical sections by placing the interrupt flags on + * the stack before disabling interrupts. Exiting the critical section is then + * simply a case of popping the flags from the stack. As 78K0 IAR does not use + * a frame pointer this cannot be done as modifying the stack will clobber all + * the stack variables. Instead each task maintains a count of the critical + * section nesting depth. Each time a critical section is entered the count is + * incremented. Each time a critical section is left the count is decremented - + * with interrupts only being re-enabled if the count is zero. + * + * usCriticalNesting will get set to zero when the scheduler starts, but must + * not be initialised to zero as this will cause problems during the startup + * sequence. */ +volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING; +/*-----------------------------------------------------------*/ + +/* + * Sets up the periodic ISR used for the RTOS tick. + */ +static void prvSetupTimerInterrupt( void ); +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See the header file portable.h. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + uint32_t * pulLocal; + + #if configMEMORY_MODE == 1 + { + /* Parameters are passed in on the stack, and written using a 32bit value + * hence a space is left for the second two bytes. */ + pxTopOfStack--; + + /* Write in the parameter value. */ + pulLocal = ( uint32_t * ) pxTopOfStack; + *pulLocal = ( uint32_t ) pvParameters; + pxTopOfStack--; + + /* These values are just spacers. The return address of the function + * would normally be written here. */ + *pxTopOfStack = ( StackType_t ) 0xcdcd; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xcdcd; + pxTopOfStack--; + + /* The start address / PSW value is also written in as a 32bit value, + * so leave a space for the second two bytes. */ + pxTopOfStack--; + + /* Task function start address combined with the PSW. */ + pulLocal = ( uint32_t * ) pxTopOfStack; + *pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) ); + pxTopOfStack--; + + /* An initial value for the AX register. */ + *pxTopOfStack = ( StackType_t ) 0x1111; + pxTopOfStack--; + } + #else /* if configMEMORY_MODE == 1 */ + { + /* Task function address is written to the stack first. As it is + * written as a 32bit value a space is left on the stack for the second + * two bytes. */ + pxTopOfStack--; + + /* Task function start address combined with the PSW. */ + pulLocal = ( uint32_t * ) pxTopOfStack; + *pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) ); + pxTopOfStack--; + + /* The parameter is passed in AX. */ + *pxTopOfStack = ( StackType_t ) pvParameters; + pxTopOfStack--; + } + #endif /* if configMEMORY_MODE == 1 */ + + /* An initial value for the HL register. */ + *pxTopOfStack = ( StackType_t ) 0x2222; + pxTopOfStack--; + + /* CS and ES registers. */ + *pxTopOfStack = ( StackType_t ) 0x0F00; + pxTopOfStack--; + + /* Finally the remaining general purpose registers DE and BC */ + *pxTopOfStack = ( StackType_t ) 0xDEDE; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xBCBC; + pxTopOfStack--; + + /* Finally the critical section nesting count is set to zero when the task + * first starts. */ + *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING; + + /* Return a pointer to the top of the stack we have generated so this can + * be stored in the task control block for the task. */ + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Setup the hardware to generate the tick. Interrupts are disabled when + * this function is called. */ + prvSetupTimerInterrupt(); + + /* Restore the context of the first task that is going to run. */ + vPortStart(); + + /* Should not get here as the tasks are now running! */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the 78K0R port will get stopped. If required simply + * disable the tick interrupt here. */ +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ + /* Setup channel 5 of the TAU to generate the tick interrupt. */ + + /* First the Timer Array Unit has to be enabled. */ + TAU0EN = 1; + + /* To configure the Timer Array Unit all Channels have to first be stopped. */ + TT0 = 0xff; + + /* Interrupt of Timer Array Unit Channel 5 is disabled to set the interrupt + * priority. */ + TMMK05 = 1; + + /* Clear Timer Array Unit Channel 5 interrupt flag. */ + TMIF05 = 0; + + /* Set Timer Array Unit Channel 5 interrupt priority */ + TMPR005 = 0; + TMPR105 = 0; + + /* Set Timer Array Unit Channel 5 Mode as interval timer. */ + TMR05 = 0x0000; + + /* Set the compare match value according to the tick rate we want. */ + TDR05 = ( TickType_t ) ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ); + + /* Set Timer Array Unit Channel 5 output mode */ + TOM0 &= ~0x0020; + + /* Set Timer Array Unit Channel 5 output level */ + TOL0 &= ~0x0020; + + /* Set Timer Array Unit Channel 5 output enable */ + TOE0 &= ~0x0020; + + /* Interrupt of Timer Array Unit Channel 5 enabled */ + TMMK05 = 0; + + /* Start Timer Array Unit Channel 5.*/ + TS0 |= 0x0020; +} +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/78K0R/portasm.s26 b/portable/IAR/78K0R/portasm.s26 new file mode 100644 index 000000000..1cddc0caf --- /dev/null +++ b/portable/IAR/78K0R/portasm.s26 @@ -0,0 +1,139 @@ +;/* +; * FreeRTOS Kernel +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + +#include "ISR_Support.h" +;------------------------------------------------------------------------------ + +#if __CORE__ != __78K0R__ + #error "This file is only for 78K0R Devices" +#endif + +#define CS 0xFFFFC +#define ES 0xFFFFD + +; Functions implemented in this file +;------------------------------------------------------------------------------ + PUBLIC vPortYield + PUBLIC vPortStart + +; Functions used by scheduler +;------------------------------------------------------------------------------ + EXTERN vTaskSwitchContext + EXTERN xTaskIncrementTick + +; Tick ISR Prototype +;------------------------------------------------------------------------------ +; EXTERN ?CL78K0R_V2_L00 + + PUBWEAK `??MD_INTTM05??INTVEC 68` + PUBLIC MD_INTTM05 + +MD_INTTM05 SYMBOL "MD_INTTM05" +`??MD_INTTM05??INTVEC 68` SYMBOL "??INTVEC 68", MD_INTTM05 + + + +;------------------------------------------------------------------------------ +; Yield to another task. Implemented as a software interrupt. The return +; address and PSW will have been saved to the stack automatically before +; this code runs. +; +; Input: NONE +; +; Call: CALL vPortYield +; +; Output: NONE +; +;------------------------------------------------------------------------------ + RSEG CODE:CODE +vPortYield: + portSAVE_CONTEXT ; Save the context of the current task. + call vTaskSwitchContext ; Call the scheduler to select the next task. + portRESTORE_CONTEXT ; Restore the context of the next task to run. + retb + + +;------------------------------------------------------------------------------ +; Restore the context of the first task that is going to run. +; +; Input: NONE +; +; Call: CALL vPortStart +; +; Output: NONE +; +;------------------------------------------------------------------------------ + RSEG CODE:CODE +vPortStart: + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + reti ; An interrupt stack frame is used so the task + ; is started using a RETI instruction. + +;------------------------------------------------------------------------------ +; Perform the necessary steps of the Tick Count Increment and Task Switch +; depending on the chosen kernel configuration +; +; Input: NONE +; +; Call: ISR +; +; Output: NONE +; +;------------------------------------------------------------------------------ + +MD_INTTM05: + + portSAVE_CONTEXT ; Save the context of the current task. + call xTaskIncrementTick ; Call the timer tick function. +#if configUSE_PREEMPTION == 1 + call vTaskSwitchContext ; Call the scheduler to select the next task. +#endif + portRESTORE_CONTEXT ; Restore the context of the next task to run. + reti + + + +; REQUIRE ?CL78K0R_V2_L00 + COMMON INTVEC:CODE:ROOT(1) ; Set ISR location to the Interrupt vector table. + ORG 68 +`??MD_INTTM05??INTVEC 68`: + DW MD_INTTM05 + + COMMON INTVEC:CODE:ROOT(1) ; Set ISR location to the Interrupt vector table. + ORG 126 +`??vPortYield??INTVEC 126`: + DW vPortYield + + ; Set value for the usCriticalNesting. + RSEG NEAR_ID:CONST:SORT:NOROOT(1) +`?`: + DW 10 + +;#endif + + END diff --git a/portable/IAR/78K0R/portmacro.h b/portable/IAR/78K0R/portmacro.h new file mode 100644 index 000000000..e0ac8fb02 --- /dev/null +++ b/portable/IAR/78K0R/portmacro.h @@ -0,0 +1,151 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ + +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint16_t +#define portBASE_TYPE short + +typedef portSTACK_TYPE StackType_t; +typedef short BaseType_t; +typedef unsigned short UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef unsigned int TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Interrupt control macros. */ +#define portDISABLE_INTERRUPTS() __asm( "DI" ) +#define portENABLE_INTERRUPTS() __asm( "EI" ) +/*-----------------------------------------------------------*/ + +/* Critical section control macros. */ +#define portNO_CRITICAL_SECTION_NESTING ( ( uint16_t ) 0 ) + +#define portENTER_CRITICAL() \ + { \ + extern volatile uint16_t usCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + \ + /* Now that interrupts are disabled, ulCriticalNesting can be accessed */ \ + /* directly. Increment ulCriticalNesting to keep a count of how many */ \ + /* times portENTER_CRITICAL() has been called. */ \ + usCriticalNesting++; \ + } + +#define portEXIT_CRITICAL() \ + { \ + extern volatile uint16_t usCriticalNesting; \ + \ + if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ + { \ + /* Decrement the nesting count as we are leaving a critical section. */ \ + usCriticalNesting--; \ + \ + /* If the nesting level has reached zero then interrupts should be */ \ + /* re-enabled. */ \ + if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } \ + } +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +extern void vPortStart( void ); +#define portYIELD() __asm( "BRK" ) +#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) do { if( xHigherPriorityTaskWoken ) vTaskSwitchContext( ); } while( 0 ) +#define portNOP() __asm( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 2 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + + +static __interrupt void P0_isr( void ); + +/* --------------------------------------------------------------------------*/ +/* Option-bytes and security ID */ +/* --------------------------------------------------------------------------*/ +#define OPT_BYTES_SIZE 4 +#define SECU_ID_SIZE 10 +#define WATCHDOG_DISABLED 0x00 +#define LVI_ENABLED 0xFE +#define LVI_DISABLED 0xFF +#define RESERVED_FF 0xFF +#define OCD_DISABLED 0x04 +#define OCD_ENABLED 0x81 +#define OCD_ENABLED_ERASE 0x80 + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/IAR/ARM_CA5_No_GIC/port.c b/portable/IAR/ARM_CA5_No_GIC/port.c new file mode 100644 index 000000000..31afbb567 --- /dev/null +++ b/portable/IAR/ARM_CA5_No_GIC/port.c @@ -0,0 +1,304 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* IAR includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + /* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +#ifndef configSETUP_TICK_INTERRUPT + #error configSETUP_TICK_INTERRUPT() must be defined in FreeRTOSConfig.h to call the function that sets up the tick interrupt. A default that uses the PIT is provided in the official demo application. +#endif + +#ifndef configCLEAR_TICK_INTERRUPT + #error configCLEAR_TICK_INTERRUPT must be defined in FreeRTOSConfig.h to clear which ever interrupt was used to generate the tick interrupt. A default that uses the PIT is provided in the official demo application. +#endif + +/* A critical section is exited when the critical section nesting count reaches + * this value. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + +/* Tasks are not created with a floating point context, but can be given a + * floating point context after they have been created. A variable is stored as + * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task + * does not have an FPU context, or any other value if the task does have an FPU + * context. */ +#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) + +/* Constants required to setup the initial task context. */ +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portTHUMB_MODE_ADDRESS ( 0x01UL ) + +/* Masks all bits in the APSR other than the mode bits. */ +#define portAPSR_MODE_BITS_MASK ( 0x1F ) + +/* The value of the mode bits in the APSR when the CPU is executing in user + * mode. */ +#define portAPSR_USER_MODE ( 0x10 ) + +/*-----------------------------------------------------------*/ + +/* + * Starts the first task executing. This function is necessarily written in + * assembly code so is implemented in portASM.s. + */ +extern void vPortRestoreTaskContext( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* A variable is used to keep track of the critical section nesting. This + * variable has to be stored as part of the task context and must be initialised to + * a non zero value to ensure interrupts don't inadvertently become unmasked before + * the scheduler starts. As it is stored as part of the task context it will + * automatically be set to 0 when the first task is started. */ +volatile uint32_t ulCriticalNesting = 9999UL; + +/* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero + * then a floating point context must be saved and restored for the task. */ +uint32_t ulPortTaskHasFPUContext = pdFALSE; + +/* Set to 1 to pend a context switch from an ISR. */ +uint32_t ulPortYieldRequired = pdFALSE; + +/* Counts the interrupt nesting depth. A context switch is only performed if + * if the nesting depth is 0. */ +uint32_t ulPortInterruptNesting = 0UL; + + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Setup the initial stack of the task. The stack is set exactly as + * expected by the portRESTORE_CONTEXT() macro. + * + * The fist real value on the stack is the status register, which is set for + * system mode, with interrupts enabled. A few NULLs are added first to ensure + * GDB does not try decoding a non-existent return address. */ + *pxTopOfStack = NULL; + pxTopOfStack--; + *pxTopOfStack = NULL; + pxTopOfStack--; + *pxTopOfStack = NULL; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + + if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL ) + { + /* The task will start in THUMB mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + + pxTopOfStack--; + + /* Next the return address, which in this case is the start of the task. */ + *pxTopOfStack = ( StackType_t ) pxCode; + pxTopOfStack--; + + /* Next all the registers other than the stack pointer. */ + *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The task will start with a critical nesting count of 0 as interrupts are + * enabled. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + pxTopOfStack--; + + /* The task will start without a floating point context. A task that uses + * the floating point hardware must call vPortTaskUsesFPU() before executing + * any floating point instructions. */ + *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ + configASSERT( ulPortInterruptNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + uint32_t ulAPSR; + + /* Only continue if the CPU is not in User mode. The CPU must be in a + * Privileged mode for the scheduler to start. */ + __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) ); + + ulAPSR &= portAPSR_MODE_BITS_MASK; + configASSERT( ulAPSR != portAPSR_USER_MODE ); + + if( ulAPSR != portAPSR_USER_MODE ) + { + /* Start the timer that generates the tick ISR. */ + configSETUP_TICK_INTERRUPT(); + vPortRestoreTaskContext(); + } + + /* Will only get here if vTaskStartScheduler() was called with the CPU in + * a non-privileged mode or the binary point register was not set to its lowest + * possible value. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + + /* Now that interrupts are disabled, ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ + if( ulCriticalNesting == 1 ) + { + configASSERT( ulPortInterruptNesting == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as the critical section is being + * exited. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then all interrupt + * priorities must be re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Critical nesting has reached zero so all interrupt priorities + * should be unmasked. */ + portENABLE_INTERRUPTS(); + } + } +} +/*-----------------------------------------------------------*/ + +void FreeRTOS_Tick_Handler( void ) +{ + portDISABLE_INTERRUPTS(); + + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + ulPortYieldRequired = pdTRUE; + } + + portENABLE_INTERRUPTS(); + configCLEAR_TICK_INTERRUPT(); +} +/*-----------------------------------------------------------*/ + +void vPortTaskUsesFPU( void ) +{ + uint32_t ulInitialFPSCR = 0; + + /* A task is registering the fact that it needs an FPU context. Set the + * FPU flag (which is saved as part of the task context). */ + ulPortTaskHasFPUContext = pdTRUE; + + /* Initialise the floating point status register. */ + __asm( "FMXR FPSCR, %0" ::"r" ( ulInitialFPSCR ) ); +} +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/ARM_CA5_No_GIC/portASM.h b/portable/IAR/ARM_CA5_No_GIC/portASM.h new file mode 100644 index 000000000..c3f9978d2 --- /dev/null +++ b/portable/IAR/ARM_CA5_No_GIC/portASM.h @@ -0,0 +1,109 @@ +;/* +; * FreeRTOS Kernel +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + + EXTERN vTaskSwitchContext + EXTERN ulCriticalNesting + EXTERN pxCurrentTCB + EXTERN ulPortTaskHasFPUContext + EXTERN ulAsmAPIPriorityMask + +portSAVE_CONTEXT macro + + ; Save the LR and SPSR onto the system mode stack before switching to + ; system mode to save the remaining system mode registers + SRSDB sp!, #SYS_MODE + CPS #SYS_MODE + PUSH {R0-R12, R14} + + ; Push the critical nesting count + LDR R2, =ulCriticalNesting + LDR R1, [R2] + PUSH {R1} + + ; Does the task have a floating point context that needs saving? If + ; ulPortTaskHasFPUContext is 0 then no. + LDR R2, =ulPortTaskHasFPUContext + LDR R3, [R2] + CMP R3, #0 + + ; Save the floating point context, if any + FMRXNE R1, FPSCR + VPUSHNE {D0-D15} +#if configFPU_D32 == 1 + VPUSHNE {D16-D31} +#endif ; configFPU_D32 + PUSHNE {R1} + + ; Save ulPortTaskHasFPUContext itself + PUSH {R3} + + ; Save the stack pointer in the TCB + LDR R0, =pxCurrentTCB + LDR R1, [R0] + STR SP, [R1] + + endm + +; /**********************************************************************/ + +portRESTORE_CONTEXT macro + + ; Set the SP to point to the stack of the task being restored. + LDR R0, =pxCurrentTCB + LDR R1, [R0] + LDR SP, [R1] + + ; Is there a floating point context to restore? If the restored + ; ulPortTaskHasFPUContext is zero then no. + LDR R0, =ulPortTaskHasFPUContext + POP {R1} + STR R1, [R0] + CMP R1, #0 + + ; Restore the floating point context, if any + POPNE {R0} +#if configFPU_D32 == 1 + VPOPNE {D16-D31} +#endif ; configFPU_D32 + VPOPNE {D0-D15} + VMSRNE FPSCR, R0 + + ; Restore the critical section nesting depth + LDR R0, =ulCriticalNesting + POP {R1} + STR R1, [R0] + + ; Restore all system mode registers other than the SP (which is already + ; being used) + POP {R0-R12, R14} + + ; Return to the task code, loading CPSR on the way. CPSR has the interrupt + ; enable bit set appropriately for the task about to execute. + RFEIA sp! + + endm diff --git a/portable/IAR/ARM_CA5_No_GIC/portASM.s b/portable/IAR/ARM_CA5_No_GIC/portASM.s new file mode 100644 index 000000000..dcfaa6043 --- /dev/null +++ b/portable/IAR/ARM_CA5_No_GIC/portASM.s @@ -0,0 +1,173 @@ +;/* +; * FreeRTOS Kernel +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + + INCLUDE FreeRTOSConfig.h + INCLUDE portmacro.h + + EXTERN vTaskSwitchContext + EXTERN ulPortYieldRequired + EXTERN ulPortInterruptNesting + EXTERN vApplicationIRQHandler + + PUBLIC FreeRTOS_SWI_Handler + PUBLIC FreeRTOS_IRQ_Handler + PUBLIC vPortRestoreTaskContext + +SYS_MODE EQU 0x1f +SVC_MODE EQU 0x13 +IRQ_MODE EQU 0x12 + + SECTION .text:CODE:ROOT(2) + ARM + + INCLUDE portASM.h + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; SVC handler is used to yield a task. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +FreeRTOS_SWI_Handler + + PRESERVE8 + + ; Save the context of the current task and select a new task to run. + portSAVE_CONTEXT + LDR R0, =vTaskSwitchContext + BLX R0 + portRESTORE_CONTEXT + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; vPortRestoreTaskContext is used to start the scheduler. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortRestoreTaskContext + + PRESERVE8 + + ; Switch to system mode + CPS #SYS_MODE + portRESTORE_CONTEXT + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; IRQ interrupt handler used when individual priorities cannot be masked +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +FreeRTOS_IRQ_Handler + + PRESERVE8 + + ; Return to the interrupted instruction. + SUB lr, lr, #4 + + ; Push the return address and SPSR + PUSH {lr} + MRS lr, SPSR + PUSH {lr} + + ; Change to supervisor mode to allow reentry. + CPS #SVC_MODE + + ; Push used registers. + PUSH {r0-r4, r12} + + ; Increment nesting count. r3 holds the address of ulPortInterruptNesting + ; for future use. r1 holds the original ulPortInterruptNesting value for + ; future use. + LDR r3, =ulPortInterruptNesting + LDR r1, [r3] + ADD r4, r1, #1 + STR r4, [r3] + + ; Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for + ; future use. + MOV r2, sp + AND r2, r2, #4 + SUB sp, sp, r2 + + PUSH {r0-r4, lr} + + ; Call the port part specific handler. + LDR r0, =vApplicationIRQHandler + BLX r0 + POP {r0-r4, lr} + ADD sp, sp, r2 + + CPSID i + + ; Write to the EOI register. + LDR r4, =configEOI_ADDRESS + STR r0, [r4] + + ; Restore the old nesting count + STR r1, [r3] + + ; A context switch is never performed if the nesting count is not 0. + CMP r1, #0 + BNE exit_without_switch + + ; Did the interrupt request a context switch? r1 holds the address of + ; ulPortYieldRequired and r0 the value of ulPortYieldRequired for future + ; use. + LDR r1, =ulPortYieldRequired + LDR r0, [r1] + CMP r0, #0 + BNE switch_before_exit + +exit_without_switch + ; No context switch. Restore used registers, LR_irq and SPSR before + ; returning. + POP {r0-r4, r12} + CPS #IRQ_MODE + POP {LR} + MSR SPSR_cxsf, LR + POP {LR} + MOVS PC, LR + +switch_before_exit + ; A context switch is to be performed. Clear the context switch pending + ; flag. + MOV r0, #0 + STR r0, [r1] + + ; Restore used registers, LR-irq and SPSR before saving the context + ; to the task stack. + POP {r0-r4, r12} + CPS #IRQ_MODE + POP {LR} + MSR SPSR_cxsf, LR + POP {LR} + portSAVE_CONTEXT + + ; Call the function that selects the new task to execute. + ; vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD + ; instructions, or 8 byte aligned stack allocated data. LR does not need + ; saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. + LDR r0, =vTaskSwitchContext + BLX r0 + + ; Restore the context of, and branch to, the task selected to execute next. + portRESTORE_CONTEXT + + END diff --git a/portable/IAR/ARM_CA5_No_GIC/portmacro.h b/portable/IAR/ARM_CA5_No_GIC/portmacro.h new file mode 100644 index 000000000..8d5caeb8a --- /dev/null +++ b/portable/IAR/ARM_CA5_No_GIC/portmacro.h @@ -0,0 +1,167 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/* IAR includes. */ +#ifdef __ICCARM__ + + #include + + + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* Called at the end of an ISR that can cause a context switch. */ + #define portEND_SWITCHING_ISR( xSwitchRequired ) \ + { \ + extern uint32_t ulPortYieldRequired; \ + \ + if( xSwitchRequired != pdFALSE ) \ + { \ + ulPortYieldRequired = pdTRUE; \ + } \ + } + + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) + #define portYIELD() __asm volatile ( "SWI 0" ); __ISB() + + +/*----------------------------------------------------------- +* Critical section control +*----------------------------------------------------------*/ + + extern void vPortEnterCritical( void ); + extern void vPortExitCritical( void ); + extern uint32_t ulPortSetInterruptMask( void ); + extern void vPortClearInterruptMask( uint32_t ulNewMaskValue ); + + #define portENTER_CRITICAL() vPortEnterCritical(); + #define portEXIT_CRITICAL() vPortExitCritical(); + #define portDISABLE_INTERRUPTS() __disable_irq(); __DSB(); __ISB() /* No priority mask register so global disable is used. */ + #define portENABLE_INTERRUPTS() __enable_irq() + #define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_state(); __disable_irq() /* No priority mask register so global disable is used. */ + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) __set_interrupt_state( x ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not required for this port but included in case common demo code that uses these + * macros is used. */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* Prototype of the FreeRTOS tick handler. This must be installed as the + * handler for whichever peripheral is used to generate the RTOS tick. */ + void FreeRTOS_Tick_Handler( void ); + +/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU() + * before any floating point instructions are executed. */ + void vPortTaskUsesFPU( void ); + #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() + +/* Architecture specific optimisations. */ + #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #endif + + #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __CLZ( uxReadyPriorities ) ) + + #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + + #define portNOP() __asm volatile ( "NOP" ) + +/* Suppress warnings that are generated by the IAR tools, but cannot be + * fixed in the source code because to do so would cause other compilers to + * generate warnings. */ + #pragma diag_suppress=Pe191 + #pragma diag_suppress=Pa082 + +#endif /* __ICCARM__ */ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/IAR/ARM_CA9/port.c b/portable/IAR/ARM_CA9/port.c new file mode 100644 index 000000000..66852f9a7 --- /dev/null +++ b/portable/IAR/ARM_CA9/port.c @@ -0,0 +1,446 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* IAR includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS + #error "configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" +#endif + +#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET + #error "configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" +#endif + +#ifndef configUNIQUE_INTERRUPT_PRIORITIES + #error "configUNIQUE_INTERRUPT_PRIORITIES must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" +#endif + +#ifndef configSETUP_TICK_INTERRUPT + #error "configSETUP_TICK_INTERRUPT() must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" +#endif /* configSETUP_TICK_INTERRUPT */ + +#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" +#endif + +#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0 + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0" +#endif + +#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority" +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + /* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice." + #endif +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/* In case security extensions are implemented. */ +#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 ) + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )" +#endif + +#ifndef configCLEAR_TICK_INTERRUPT + #define configCLEAR_TICK_INTERRUPT() +#endif + +/* A critical section is exited when the critical section nesting count reaches + * this value. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + +/* In all GICs 255 can be written to the priority mask register to unmask all + * (but the lowest) interrupt priority. */ +#define portUNMASK_VALUE ( 0xFFUL ) + +/* Tasks are not created with a floating point context, but can be given a + * floating point context after they have been created. A variable is stored as + * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task + * does not have an FPU context, or any other value if the task does have an FPU + * context. */ +#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) + +/* Constants required to setup the initial task context. */ +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portTHUMB_MODE_ADDRESS ( 0x01UL ) + +/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary + * point is zero. */ +#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 ) + +/* Masks all bits in the APSR other than the mode bits. */ +#define portAPSR_MODE_BITS_MASK ( 0x1F ) + +/* The value of the mode bits in the APSR when the CPU is executing in user + * mode. */ +#define portAPSR_USER_MODE ( 0x10 ) + +/* Macro to unmask all interrupt priorities. */ +#define portCLEAR_INTERRUPT_MASK() \ + { \ + __disable_irq(); \ + portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \ + __asm( "DSB \n" \ + "ISB \n" ); \ + __enable_irq(); \ + } + +/*-----------------------------------------------------------*/ + +/* + * Starts the first task executing. This function is necessarily written in + * assembly code so is implemented in portASM.s. + */ +extern void vPortRestoreTaskContext( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* A variable is used to keep track of the critical section nesting. This + * variable has to be stored as part of the task context and must be initialised to + * a non zero value to ensure interrupts don't inadvertently become unmasked before + * the scheduler starts. As it is stored as part of the task context it will + * automatically be set to 0 when the first task is started. */ +volatile uint32_t ulCriticalNesting = 9999UL; + +/* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero + * then a floating point context must be saved and restored for the task. */ +uint32_t ulPortTaskHasFPUContext = pdFALSE; + +/* Set to 1 to pend a context switch from an ISR. */ +uint32_t ulPortYieldRequired = pdFALSE; + +/* Counts the interrupt nesting depth. A context switch is only performed if + * if the nesting depth is 0. */ +uint32_t ulPortInterruptNesting = 0UL; + + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Setup the initial stack of the task. The stack is set exactly as + * expected by the portRESTORE_CONTEXT() macro. + * + * The fist real value on the stack is the status register, which is set for + * system mode, with interrupts enabled. A few NULLs are added first to ensure + * GDB does not try decoding a non-existent return address. */ + *pxTopOfStack = NULL; + pxTopOfStack--; + *pxTopOfStack = NULL; + pxTopOfStack--; + *pxTopOfStack = NULL; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + + if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL ) + { + /* The task will start in THUMB mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + + pxTopOfStack--; + + /* Next the return address, which in this case is the start of the task. */ + *pxTopOfStack = ( StackType_t ) pxCode; + pxTopOfStack--; + + /* Next all the registers other than the stack pointer. */ + *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The task will start with a critical nesting count of 0 as interrupts are + * enabled. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + pxTopOfStack--; + + /* The task will start without a floating point context. A task that uses + * the floating point hardware must call vPortTaskUsesFPU() before executing + * any floating point instructions. */ + *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ + configASSERT( ulPortInterruptNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + uint32_t ulAPSR; + + /* Only continue if the CPU is not in User mode. The CPU must be in a + * Privileged mode for the scheduler to start. */ + __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) ); + + ulAPSR &= portAPSR_MODE_BITS_MASK; + configASSERT( ulAPSR != portAPSR_USER_MODE ); + + if( ulAPSR != portAPSR_USER_MODE ) + { + /* Only continue if the binary point value is set to its lowest possible + * setting. See the comments in vPortValidateInterruptPriority() below for + * more information. */ + configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ); + + if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ) + { + /* Start the timer that generates the tick ISR. */ + configSETUP_TICK_INTERRUPT(); + + __enable_irq(); + vPortRestoreTaskContext(); + } + } + + /* Will only get here if vTaskStartScheduler() was called with the CPU in + * a non-privileged mode or the binary point register was not set to its lowest + * possible value. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ + ulPortSetInterruptMask(); + + /* Now that interrupts are disabled, ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ + if( ulCriticalNesting == 1 ) + { + configASSERT( ulPortInterruptNesting == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as the critical section is being + * exited. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then all interrupt + * priorities must be re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Critical nesting has reached zero so all interrupt priorities + * should be unmasked. */ + portCLEAR_INTERRUPT_MASK(); + } + } +} +/*-----------------------------------------------------------*/ + +void FreeRTOS_Tick_Handler( void ) +{ + /* Set interrupt mask before altering scheduler structures. The tick + * handler runs at the lowest priority, so interrupts cannot already be masked, + * so there is no need to save and restore the current mask value. */ + __disable_irq(); + portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); + __asm( "DSB \n" + "ISB \n" ); + __enable_irq(); + + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + ulPortYieldRequired = pdTRUE; + } + + /* Ensure all interrupt priorities are active again. */ + portCLEAR_INTERRUPT_MASK(); + configCLEAR_TICK_INTERRUPT(); +} +/*-----------------------------------------------------------*/ + +void vPortTaskUsesFPU( void ) +{ + uint32_t ulInitialFPSCR = 0; + + /* A task is registering the fact that it needs an FPU context. Set the + * FPU flag (which is saved as part of the task context). */ + ulPortTaskHasFPUContext = pdTRUE; + + /* Initialise the floating point status register. */ + __asm( "FMXR FPSCR, %0" ::"r" ( ulInitialFPSCR ) ); +} +/*-----------------------------------------------------------*/ + +void vPortClearInterruptMask( uint32_t ulNewMaskValue ) +{ + if( ulNewMaskValue == pdFALSE ) + { + portCLEAR_INTERRUPT_MASK(); + } +} +/*-----------------------------------------------------------*/ + +uint32_t ulPortSetInterruptMask( void ) +{ + uint32_t ulReturn; + + __disable_irq(); + + if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ) + { + /* Interrupts were already masked. */ + ulReturn = pdTRUE; + } + else + { + ulReturn = pdFALSE; + portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); + __asm( "DSB \n" + "ISB \n" ); + } + + __enable_irq(); + + return ulReturn; +} +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ); + + /* Priority grouping: The interrupt controller (GIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * The priority grouping is configured by the GIC's binary point register + * (ICCBPR). Writing 0 to ICCBPR will ensure it is set to its lowest + * possible value (which may be above 0). */ + configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ); + } + +#endif /* configASSERT_DEFINED */ diff --git a/portable/IAR/ARM_CA9/portASM.h b/portable/IAR/ARM_CA9/portASM.h new file mode 100644 index 000000000..181530b67 --- /dev/null +++ b/portable/IAR/ARM_CA9/portASM.h @@ -0,0 +1,111 @@ +;/* +; * FreeRTOS Kernel +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + + EXTERN vTaskSwitchContext + EXTERN ulCriticalNesting + EXTERN pxCurrentTCB + EXTERN ulPortTaskHasFPUContext + EXTERN ulAsmAPIPriorityMask + +portSAVE_CONTEXT macro + + ; Save the LR and SPSR onto the system mode stack before switching to + ; system mode to save the remaining system mode registers + SRSDB sp!, #SYS_MODE + CPS #SYS_MODE + PUSH {R0-R12, R14} + + ; Push the critical nesting count + LDR R2, =ulCriticalNesting + LDR R1, [R2] + PUSH {R1} + + ; Does the task have a floating point context that needs saving? If + ; ulPortTaskHasFPUContext is 0 then no. + LDR R2, =ulPortTaskHasFPUContext + LDR R3, [R2] + CMP R3, #0 + + ; Save the floating point context, if any + FMRXNE R1, FPSCR + VPUSHNE {D0-D15} + VPUSHNE {D16-D31} + PUSHNE {R1} + + ; Save ulPortTaskHasFPUContext itself + PUSH {R3} + + ; Save the stack pointer in the TCB + LDR R0, =pxCurrentTCB + LDR R1, [R0] + STR SP, [R1] + + endm + +; /**********************************************************************/ + +portRESTORE_CONTEXT macro + + ; Set the SP to point to the stack of the task being restored. + LDR R0, =pxCurrentTCB + LDR R1, [R0] + LDR SP, [R1] + + ; Is there a floating point context to restore? If the restored + ; ulPortTaskHasFPUContext is zero then no. + LDR R0, =ulPortTaskHasFPUContext + POP {R1} + STR R1, [R0] + CMP R1, #0 + + ; Restore the floating point context, if any + POPNE {R0} + VPOPNE {D16-D31} + VPOPNE {D0-D15} + VMSRNE FPSCR, R0 + + ; Restore the critical section nesting depth + LDR R0, =ulCriticalNesting + POP {R1} + STR R1, [R0] + + ; Ensure the priority mask is correct for the critical nesting depth + LDR R2, =portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS + CMP R1, #0 + MOVEQ R4, #255 + LDRNE R4, =( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) + STR R4, [r2] + + ; Restore all system mode registers other than the SP (which is already + ; being used) + POP {R0-R12, R14} + + ; Return to the task code, loading CPSR on the way. + RFEIA sp! + + endm diff --git a/portable/IAR/ARM_CA9/portASM.s b/portable/IAR/ARM_CA9/portASM.s new file mode 100644 index 000000000..d7d07995f --- /dev/null +++ b/portable/IAR/ARM_CA9/portASM.s @@ -0,0 +1,174 @@ +;/* +; * FreeRTOS Kernel +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + + INCLUDE FreeRTOSConfig.h + INCLUDE portmacro.h + + EXTERN vApplicationIRQHandler + EXTERN vTaskSwitchContext + EXTERN ulPortYieldRequired + EXTERN ulPortInterruptNesting + + PUBLIC FreeRTOS_SWI_Handler + PUBLIC FreeRTOS_IRQ_Handler + PUBLIC vPortRestoreTaskContext + +SYS_MODE EQU 0x1f +SVC_MODE EQU 0x13 +IRQ_MODE EQU 0x12 + + + SECTION .text:CODE:ROOT(2) + ARM + + INCLUDE portASM.h + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; SVC handler is used to yield a task. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +FreeRTOS_SWI_Handler + + PRESERVE8 + + ; Save the context of the current task and select a new task to run. + portSAVE_CONTEXT + LDR R0, =vTaskSwitchContext + BLX R0 + portRESTORE_CONTEXT + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; vPortRestoreTaskContext is used to start the scheduler. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortRestoreTaskContext + ; Switch to system mode + CPS #SYS_MODE + portRESTORE_CONTEXT + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; PL390 GIC interrupt handler +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +FreeRTOS_IRQ_Handler + + ; Return to the interrupted instruction. + SUB lr, lr, #4 + + ; Push the return address and SPSR + PUSH {lr} + MRS lr, SPSR + PUSH {lr} + + ; Change to supervisor mode to allow reentry. + CPS #SVC_MODE + + ; Push used registers. + PUSH {r0-r4, r12} + + ; Increment nesting count. r3 holds the address of ulPortInterruptNesting + ; for future use. r1 holds the original ulPortInterruptNesting value for + ; future use. + LDR r3, =ulPortInterruptNesting + LDR r1, [r3] + ADD r4, r1, #1 + STR r4, [r3] + + ; Read value from the interrupt acknowledge register, which is stored in r0 + ; for future parameter and interrupt clearing use. + LDR r2, =portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS + LDR r0, [r2] + + ; Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for + ; future use. _RB_ Is this ever necessary if start of stack is 8-byte aligned? + MOV r2, sp + AND r2, r2, #4 + SUB sp, sp, r2 + + ; Call the interrupt handler. r4 is pushed to maintain alignment. + PUSH {r0-r4, lr} + LDR r1, =vApplicationIRQHandler + BLX r1 + POP {r0-r4, lr} + ADD sp, sp, r2 + + CPSID i + + ; Write the value read from ICCIAR to ICCEOIR + LDR r4, =portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS + STR r0, [r4] + + ; Restore the old nesting count + STR r1, [r3] + + ; A context switch is never performed if the nesting count is not 0 + CMP r1, #0 + BNE exit_without_switch + + ; Did the interrupt request a context switch? r1 holds the address of + ; ulPortYieldRequired and r0 the value of ulPortYieldRequired for future + ; use. + LDR r1, =ulPortYieldRequired + LDR r0, [r1] + CMP r0, #0 + BNE switch_before_exit + +exit_without_switch + ; No context switch. Restore used registers, LR_irq and SPSR before + ; returning. + POP {r0-r4, r12} + CPS #IRQ_MODE + POP {LR} + MSR SPSR_cxsf, LR + POP {LR} + MOVS PC, LR + +switch_before_exit + ; A context switch is to be performed. Clear the context switch pending + ; flag. + MOV r0, #0 + STR r0, [r1] + + ; Restore used registers, LR-irq and SPSR before saving the context + ; to the task stack. + POP {r0-r4, r12} + CPS #IRQ_MODE + POP {LR} + MSR SPSR_cxsf, LR + POP {LR} + portSAVE_CONTEXT + + ; Call the function that selects the new task to execute. + ; vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD + ; instructions, or 8 byte aligned stack allocated data. LR does not need + ; saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. + LDR r0, =vTaskSwitchContext + BLX r0 + + ; Restore the context of, and branch to, the task selected to execute next. + portRESTORE_CONTEXT + + + END diff --git a/portable/IAR/ARM_CA9/portmacro.h b/portable/IAR/ARM_CA9/portmacro.h new file mode 100644 index 000000000..f1cb124a2 --- /dev/null +++ b/portable/IAR/ARM_CA9/portmacro.h @@ -0,0 +1,212 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/* IAR includes. */ +#ifdef __ICCARM__ + + #include + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* Called at the end of an ISR that can cause a context switch. */ + #define portEND_SWITCHING_ISR( xSwitchRequired ) \ + { \ + extern uint32_t ulPortYieldRequired; \ + \ + if( xSwitchRequired != pdFALSE ) \ + { \ + ulPortYieldRequired = pdTRUE; \ + } \ + } + + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) + #define portYIELD() __asm( "SWI 0" ); + + +/*----------------------------------------------------------- +* Critical section control +*----------------------------------------------------------*/ + + extern void vPortEnterCritical( void ); + extern void vPortExitCritical( void ); + extern uint32_t ulPortSetInterruptMask( void ); + extern void vPortClearInterruptMask( uint32_t ulNewMaskValue ); + +/* These macros do not globally disable/enable interrupts. They do mask off + * interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */ + #define portENTER_CRITICAL() vPortEnterCritical(); + #define portEXIT_CRITICAL() vPortExitCritical(); + #define portDISABLE_INTERRUPTS() ulPortSetInterruptMask() + #define portENABLE_INTERRUPTS() vPortClearInterruptMask( 0 ) + #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortClearInterruptMask( x ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not required for this port but included in case common demo code that uses these + * macros is used. */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* Prototype of the FreeRTOS tick handler. This must be installed as the + * handler for whichever peripheral is used to generate the RTOS tick. */ + void FreeRTOS_Tick_Handler( void ); + +/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU() + * before any floating point instructions are executed. */ + void vPortTaskUsesFPU( void ); + #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() + + #define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL ) + #define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL ) + +/* Architecture specific optimisations. */ + #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #endif + + #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __CLZ( uxReadyPriorities ) ) + + #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + + #if ( configASSERT_DEFINED == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif /* configASSERT */ + + #define portNOP() __asm volatile ( "NOP" ) + +/* Suppress warnings that are generated by the IAR tools, but cannot be + * fixed in the source code because to do so would cause other compilers to + * generate warnings. */ + #pragma diag_suppress=Pe191 + #pragma diag_suppress=Pa082 + +#endif /* __ICCARM__ */ + + +/* The number of bits to shift for an interrupt priority is dependent on the + * number of bits implemented by the interrupt controller. */ +#if configUNIQUE_INTERRUPT_PRIORITIES == 16 + #define portPRIORITY_SHIFT 4 + #define portMAX_BINARY_POINT_VALUE 3 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 32 + #define portPRIORITY_SHIFT 3 + #define portMAX_BINARY_POINT_VALUE 2 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 64 + #define portPRIORITY_SHIFT 2 + #define portMAX_BINARY_POINT_VALUE 1 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 128 + #define portPRIORITY_SHIFT 1 + #define portMAX_BINARY_POINT_VALUE 0 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 256 + #define portPRIORITY_SHIFT 0 + #define portMAX_BINARY_POINT_VALUE 0 +#else /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */ + #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware +#endif /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */ + +/* Interrupt controller access addresses. */ +#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 ) +#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C ) +#define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 ) +#define portICCBPR_BINARY_POINT_OFFSET ( 0x08 ) +#define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 ) + +#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET ) +#define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) ) +#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ) +#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET ) +#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) +#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) ) +#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/IAR/ARM_CM0/port.c b/portable/IAR/ARM_CM0/port.c new file mode 100644 index 000000000..6f5ec0ad5 --- /dev/null +++ b/portable/IAR/ARM_CM0/port.c @@ -0,0 +1,543 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ARM CM0 port. +*----------------------------------------------------------*/ + +/* IAR includes. */ +#include "intrinsics.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Prototype of all Interrupt Service Routines (ISRs). */ +typedef void ( * portISR_t )( void ); + +/* Constants required to manipulate the NVIC. */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) + +/* Constants used to check the installation of the FreeRTOS interrupt handlers. */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portVECTOR_INDEX_PENDSV ( 14 ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) + +/* Each task maintains its own interrupt status in the critical nesting + * variable. */ +static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +/* The systick is a 24-bit counter. */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/* A fiddle factor to estimate the number of SysTick counts that would have + * occurred while the SysTick counter is stopped during tickless idle + * calculations. */ +#ifndef portMISSED_COUNTS_FACTOR + #define portMISSED_COUNTS_FACTOR ( 94UL ) +#endif + +/* The number of SysTick increments that make up one tick period. */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulTimerCountsForOneTick = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* The maximum number of tick periods that can be suppressed is limited by the + * 24 bit resolution of the SysTick timer. */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t xMaximumPossibleSuppressedTicks = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* Compensate for the CPU cycles that pass while the SysTick is stopped (low + * power functionality only. */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ); + +/* + * Exception handlers. + */ +void xPortSysTickHandler( void ); + +/* + * Start first task is a separate function so it can be tested in isolation. + */ +extern void vPortStartFirstTask( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/* + * FreeRTOS handlers implemented in assembly. + */ +extern void xPortPendSVHandler( void ); +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack -= 8; /* R11..R4. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ + configASSERT( uxCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the function xPortPendSVHandler for PendSV + * interrupt. + * 2. Indirect Routing - Install separate handler for PendSV interrupt and + * route program control from that handler to xPortPendSVHandler function. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + /* Point pxVectorTable to the interrupt vector table. Systems without + * a VTOR register provide the value zero in the VTOR register and + * the vector table itself is located at the address 0x00000000. */ + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handler for PendSV interrupt. We do not check the installation of the + * SysTick handler because the application may choose to drive the RTOS + * tick using a timer other than the SysTick timer by overriding the + * weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handler. For help installing the FreeRTOS handler, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + /* Make PendSV and SysTick the lowest priority interrupts. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortYield( void ) +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET; + + /* Barriers are normally not required but do ensure the code is completely + * within the specified behaviour for the architecture. */ + __DSB(); + __ISB(); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + __DSB(); + __ISB(); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET; + } + else + { + traceISR_EXIT(); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +__weak void vPortSetupTimerInterrupt( void ) +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __disable_interrupt(); + __DSB(); + __ISB(); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the __disable_interrupt() + * call above. */ + __enable_interrupt(); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __DSB(); + __WFI(); + __ISB(); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the __disable_interrupt() call above. */ + __enable_interrupt(); + __DSB(); + __ISB(); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __disable_interrupt(); + __DSB(); + __ISB(); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __enable_interrupt(); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ diff --git a/portable/IAR/ARM_CM0/portasm.s b/portable/IAR/ARM_CM0/portasm.s new file mode 100644 index 000000000..6c19a1749 --- /dev/null +++ b/portable/IAR/ARM_CM0/portasm.s @@ -0,0 +1,132 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include + + RSEG CODE:CODE(2) + thumb + + EXTERN vPortYieldFromISR + EXTERN pxCurrentTCB + EXTERN vTaskSwitchContext + + PUBLIC vSetMSP + PUBLIC xPortPendSVHandler + PUBLIC vPortSVCHandler + PUBLIC vPortStartFirstTask + PUBLIC ulSetInterruptMaskFromISR + PUBLIC vClearInterruptMaskFromISR + +/*-----------------------------------------------------------*/ + +vSetMSP + msr msp, r0 + bx lr + +/*-----------------------------------------------------------*/ + +xPortPendSVHandler: + mrs r0, psp + + ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */ + ldr r2, [r3] + + subs r0, r0, #32 /* Make space for the remaining low registers. */ + str r0, [r2] /* Save the new top of stack. */ + stmia r0!, {r4-r7} /* Store the low registers that are not saved automatically. */ + mov r4, r8 /* Store the high registers. */ + mov r5, r9 + mov r6, r10 + mov r7, r11 + stmia r0!, {r4-r7} + + push {r3, r14} + cpsid i + bl vTaskSwitchContext + cpsie i + pop {r2, r3} /* lr goes in r3. r2 now holds tcb pointer. */ + + ldr r1, [r2] + ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */ + adds r0, r0, #16 /* Move to the high registers. */ + ldmia r0!, {r4-r7} /* Pop the high registers. */ + mov r8, r4 + mov r9, r5 + mov r10, r6 + mov r11, r7 + + msr psp, r0 /* Remember the new top of stack for the task. */ + + subs r0, r0, #32 /* Go back for the low registers that are not automatically restored. */ + ldmia r0!, {r4-r7} /* Pop low registers. */ + + bx r3 + +/*-----------------------------------------------------------*/ + +vPortSVCHandler; + /* This function is no longer used, but retained for backward + * compatibility. */ + bx lr + +/*-----------------------------------------------------------*/ + +vPortStartFirstTask + /* Don't reset the MSP stack as is done on CM3/4 devices. The vector table + * in some CM0 devices cannot be modified and thus may not hold the + * application's initial MSP value. */ + + ldr r3, =pxCurrentTCB /* Obtain location of pxCurrentTCB. */ + ldr r1, [r3] + ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + movs r0, #2 /* Switch to the psp stack. */ + msr CONTROL, r0 + isb + pop {r0-r5} /* Pop the registers that are saved automatically. */ + mov lr, r5 /* lr is now in r5. */ + pop {r3} /* The return address is now in r3. */ + pop {r2} /* Pop and discard the XPSR. */ + cpsie i /* The first task has its context and interrupts can be enabled. */ + bx r3 /* Jump to the user defined task code. */ + +/*-----------------------------------------------------------*/ + +ulSetInterruptMaskFromISR + mrs r0, PRIMASK + cpsid i + bx lr + +/*-----------------------------------------------------------*/ + +vClearInterruptMaskFromISR + msr PRIMASK, r0 + bx lr + + END diff --git a/portable/IAR/ARM_CM0/portmacro.h b/portable/IAR/ARM_CM0/portmacro.h new file mode 100644 index 000000000..a097db9df --- /dev/null +++ b/portable/IAR/ARM_CM0/portmacro.h @@ -0,0 +1,177 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +/*-----------------------------------------------------------*/ + + +/* Scheduler utilities. */ +extern void vPortYield( void ); +#define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 ) +#define portNVIC_PENDSVSET 0x10000000 +#define portYIELD() vPortYield() +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + + +/* Critical section management. */ + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +extern uint32_t ulSetInterruptMaskFromISR( void ); +extern void vClearInterruptMaskFromISR( uint32_t ulMask ); + +#define portDISABLE_INTERRUPTS() __asm volatile ( "cpsid i" ) +#define portENABLE_INTERRUPTS() __asm volatile ( "cpsie i" ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMaskFromISR( x ) + +/*-----------------------------------------------------------*/ + +/* Tickless idle/low power functionality. */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +#define portNOP() + +#define portINLINE __inline + +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif + +/*-----------------------------------------------------------*/ + +portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} + +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ +#pragma diag_suppress=Pa082 + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/IAR/ARM_CM23/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM23/non_secure/mpu_wrappers_v2_asm.S new file mode 100644 index 000000000..9289bcbc2 --- /dev/null +++ b/portable/IAR/ARM_CM23/non_secure/mpu_wrappers_v2_asm.S @@ -0,0 +1,1312 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + + SECTION freertos_system_calls:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +#include "FreeRTOSConfig.h" +#include "mpu_syscall_numbers.h" + +#ifndef configUSE_MPU_WRAPPERS_V1 + #define configUSE_MPU_WRAPPERS_V1 0 +#endif + +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + PUBLIC MPU_xTaskDelayUntil +MPU_xTaskDelayUntil: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTaskDelayUntil_Unpriv + MPU_xTaskDelayUntil_Priv: + b MPU_xTaskDelayUntilImpl + MPU_xTaskDelayUntil_Unpriv: + svc #SYSTEM_CALL_xTaskDelayUntil +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskAbortDelay +MPU_xTaskAbortDelay: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTaskAbortDelay_Unpriv + MPU_xTaskAbortDelay_Priv: + b MPU_xTaskAbortDelayImpl + MPU_xTaskAbortDelay_Unpriv: + svc #SYSTEM_CALL_xTaskAbortDelay +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskDelay +MPU_vTaskDelay: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vTaskDelay_Unpriv + MPU_vTaskDelay_Priv: + b MPU_vTaskDelayImpl + MPU_vTaskDelay_Unpriv: + svc #SYSTEM_CALL_vTaskDelay +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskPriorityGet +MPU_uxTaskPriorityGet: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_uxTaskPriorityGet_Unpriv + MPU_uxTaskPriorityGet_Priv: + b MPU_uxTaskPriorityGetImpl + MPU_uxTaskPriorityGet_Unpriv: + svc #SYSTEM_CALL_uxTaskPriorityGet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_eTaskGetState +MPU_eTaskGetState: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_eTaskGetState_Unpriv + MPU_eTaskGetState_Priv: + b MPU_eTaskGetStateImpl + MPU_eTaskGetState_Unpriv: + svc #SYSTEM_CALL_eTaskGetState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskGetInfo +MPU_vTaskGetInfo: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vTaskGetInfo_Unpriv + MPU_vTaskGetInfo_Priv: + b MPU_vTaskGetInfoImpl + MPU_vTaskGetInfo_Unpriv: + svc #SYSTEM_CALL_vTaskGetInfo +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetIdleTaskHandle +MPU_xTaskGetIdleTaskHandle: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTaskGetIdleTaskHandle_Unpriv + MPU_xTaskGetIdleTaskHandle_Priv: + b MPU_xTaskGetIdleTaskHandleImpl + MPU_xTaskGetIdleTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTaskGetIdleTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSuspend +MPU_vTaskSuspend: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vTaskSuspend_Unpriv + MPU_vTaskSuspend_Priv: + b MPU_vTaskSuspendImpl + MPU_vTaskSuspend_Unpriv: + svc #SYSTEM_CALL_vTaskSuspend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskResume +MPU_vTaskResume: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vTaskResume_Unpriv + MPU_vTaskResume_Priv: + b MPU_vTaskResumeImpl + MPU_vTaskResume_Unpriv: + svc #SYSTEM_CALL_vTaskResume +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetTickCount +MPU_xTaskGetTickCount: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTaskGetTickCount_Unpriv + MPU_xTaskGetTickCount_Priv: + b MPU_xTaskGetTickCountImpl + MPU_xTaskGetTickCount_Unpriv: + svc #SYSTEM_CALL_xTaskGetTickCount +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetNumberOfTasks +MPU_uxTaskGetNumberOfTasks: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_uxTaskGetNumberOfTasks_Unpriv + MPU_uxTaskGetNumberOfTasks_Priv: + b MPU_uxTaskGetNumberOfTasksImpl + MPU_uxTaskGetNumberOfTasks_Unpriv: + svc #SYSTEM_CALL_uxTaskGetNumberOfTasks +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetRunTimeCounter +MPU_ulTaskGetRunTimeCounter: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_ulTaskGetRunTimeCounter_Unpriv + MPU_ulTaskGetRunTimeCounter_Priv: + b MPU_ulTaskGetRunTimeCounterImpl + MPU_ulTaskGetRunTimeCounter_Unpriv: + svc #SYSTEM_CALL_ulTaskGetRunTimeCounter +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetRunTimePercent +MPU_ulTaskGetRunTimePercent: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_ulTaskGetRunTimePercent_Unpriv + MPU_ulTaskGetRunTimePercent_Priv: + b MPU_ulTaskGetRunTimePercentImpl + MPU_ulTaskGetRunTimePercent_Unpriv: + svc #SYSTEM_CALL_ulTaskGetRunTimePercent +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetIdleRunTimePercent +MPU_ulTaskGetIdleRunTimePercent: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_ulTaskGetIdleRunTimePercent_Unpriv + MPU_ulTaskGetIdleRunTimePercent_Priv: + b MPU_ulTaskGetIdleRunTimePercentImpl + MPU_ulTaskGetIdleRunTimePercent_Unpriv: + svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetIdleRunTimeCounter +MPU_ulTaskGetIdleRunTimeCounter: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv + MPU_ulTaskGetIdleRunTimeCounter_Priv: + b MPU_ulTaskGetIdleRunTimeCounterImpl + MPU_ulTaskGetIdleRunTimeCounter_Unpriv: + svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetApplicationTaskTag +MPU_vTaskSetApplicationTaskTag: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vTaskSetApplicationTaskTag_Unpriv + MPU_vTaskSetApplicationTaskTag_Priv: + b MPU_vTaskSetApplicationTaskTagImpl + MPU_vTaskSetApplicationTaskTag_Unpriv: + svc #SYSTEM_CALL_vTaskSetApplicationTaskTag +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetApplicationTaskTag +MPU_xTaskGetApplicationTaskTag: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTaskGetApplicationTaskTag_Unpriv + MPU_xTaskGetApplicationTaskTag_Priv: + b MPU_xTaskGetApplicationTaskTagImpl + MPU_xTaskGetApplicationTaskTag_Unpriv: + svc #SYSTEM_CALL_xTaskGetApplicationTaskTag +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetThreadLocalStoragePointer +MPU_vTaskSetThreadLocalStoragePointer: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv + MPU_vTaskSetThreadLocalStoragePointer_Priv: + b MPU_vTaskSetThreadLocalStoragePointerImpl + MPU_vTaskSetThreadLocalStoragePointer_Unpriv: + svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pvTaskGetThreadLocalStoragePointer +MPU_pvTaskGetThreadLocalStoragePointer: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv + MPU_pvTaskGetThreadLocalStoragePointer_Priv: + b MPU_pvTaskGetThreadLocalStoragePointerImpl + MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: + svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetSystemState +MPU_uxTaskGetSystemState: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_uxTaskGetSystemState_Unpriv + MPU_uxTaskGetSystemState_Priv: + b MPU_uxTaskGetSystemStateImpl + MPU_uxTaskGetSystemState_Unpriv: + svc #SYSTEM_CALL_uxTaskGetSystemState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetStackHighWaterMark +MPU_uxTaskGetStackHighWaterMark: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_uxTaskGetStackHighWaterMark_Unpriv + MPU_uxTaskGetStackHighWaterMark_Priv: + b MPU_uxTaskGetStackHighWaterMarkImpl + MPU_uxTaskGetStackHighWaterMark_Unpriv: + svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetStackHighWaterMark2 +MPU_uxTaskGetStackHighWaterMark2: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_uxTaskGetStackHighWaterMark2_Unpriv + MPU_uxTaskGetStackHighWaterMark2_Priv: + b MPU_uxTaskGetStackHighWaterMark2Impl + MPU_uxTaskGetStackHighWaterMark2_Unpriv: + svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2 +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetCurrentTaskHandle +MPU_xTaskGetCurrentTaskHandle: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTaskGetCurrentTaskHandle_Unpriv + MPU_xTaskGetCurrentTaskHandle_Priv: + b MPU_xTaskGetCurrentTaskHandleImpl + MPU_xTaskGetCurrentTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetSchedulerState +MPU_xTaskGetSchedulerState: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTaskGetSchedulerState_Unpriv + MPU_xTaskGetSchedulerState_Priv: + b MPU_xTaskGetSchedulerStateImpl + MPU_xTaskGetSchedulerState_Unpriv: + svc #SYSTEM_CALL_xTaskGetSchedulerState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetTimeOutState +MPU_vTaskSetTimeOutState: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vTaskSetTimeOutState_Unpriv + MPU_vTaskSetTimeOutState_Priv: + b MPU_vTaskSetTimeOutStateImpl + MPU_vTaskSetTimeOutState_Unpriv: + svc #SYSTEM_CALL_vTaskSetTimeOutState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskCheckForTimeOut +MPU_xTaskCheckForTimeOut: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTaskCheckForTimeOut_Unpriv + MPU_xTaskCheckForTimeOut_Priv: + b MPU_xTaskCheckForTimeOutImpl + MPU_xTaskCheckForTimeOut_Unpriv: + svc #SYSTEM_CALL_xTaskCheckForTimeOut +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyEntry +MPU_xTaskGenericNotifyEntry: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTaskGenericNotify_Unpriv + MPU_xTaskGenericNotify_Priv: + b MPU_xTaskGenericNotifyImpl + MPU_xTaskGenericNotify_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotify +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyWaitEntry +MPU_xTaskGenericNotifyWaitEntry: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTaskGenericNotifyWait_Unpriv + MPU_xTaskGenericNotifyWait_Priv: + b MPU_xTaskGenericNotifyWaitImpl + MPU_xTaskGenericNotifyWait_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotifyWait +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGenericNotifyTake +MPU_ulTaskGenericNotifyTake: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_ulTaskGenericNotifyTake_Unpriv + MPU_ulTaskGenericNotifyTake_Priv: + b MPU_ulTaskGenericNotifyTakeImpl + MPU_ulTaskGenericNotifyTake_Unpriv: + svc #SYSTEM_CALL_ulTaskGenericNotifyTake +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyStateClear +MPU_xTaskGenericNotifyStateClear: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTaskGenericNotifyStateClear_Unpriv + MPU_xTaskGenericNotifyStateClear_Priv: + b MPU_xTaskGenericNotifyStateClearImpl + MPU_xTaskGenericNotifyStateClear_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotifyStateClear +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGenericNotifyValueClear +MPU_ulTaskGenericNotifyValueClear: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_ulTaskGenericNotifyValueClear_Unpriv + MPU_ulTaskGenericNotifyValueClear_Priv: + b MPU_ulTaskGenericNotifyValueClearImpl + MPU_ulTaskGenericNotifyValueClear_Unpriv: + svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGenericSend +MPU_xQueueGenericSend: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xQueueGenericSend_Unpriv + MPU_xQueueGenericSend_Priv: + b MPU_xQueueGenericSendImpl + MPU_xQueueGenericSend_Unpriv: + svc #SYSTEM_CALL_xQueueGenericSend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxQueueMessagesWaiting +MPU_uxQueueMessagesWaiting: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_uxQueueMessagesWaiting_Unpriv + MPU_uxQueueMessagesWaiting_Priv: + b MPU_uxQueueMessagesWaitingImpl + MPU_uxQueueMessagesWaiting_Unpriv: + svc #SYSTEM_CALL_uxQueueMessagesWaiting +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxQueueSpacesAvailable +MPU_uxQueueSpacesAvailable: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_uxQueueSpacesAvailable_Unpriv + MPU_uxQueueSpacesAvailable_Priv: + b MPU_uxQueueSpacesAvailableImpl + MPU_uxQueueSpacesAvailable_Unpriv: + svc #SYSTEM_CALL_uxQueueSpacesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueReceive +MPU_xQueueReceive: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xQueueReceive_Unpriv + MPU_xQueueReceive_Priv: + b MPU_xQueueReceiveImpl + MPU_xQueueReceive_Unpriv: + svc #SYSTEM_CALL_xQueueReceive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueuePeek +MPU_xQueuePeek: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xQueuePeek_Unpriv + MPU_xQueuePeek_Priv: + b MPU_xQueuePeekImpl + MPU_xQueuePeek_Unpriv: + svc #SYSTEM_CALL_xQueuePeek +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueSemaphoreTake +MPU_xQueueSemaphoreTake: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xQueueSemaphoreTake_Unpriv + MPU_xQueueSemaphoreTake_Priv: + b MPU_xQueueSemaphoreTakeImpl + MPU_xQueueSemaphoreTake_Unpriv: + svc #SYSTEM_CALL_xQueueSemaphoreTake +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGetMutexHolder +MPU_xQueueGetMutexHolder: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xQueueGetMutexHolder_Unpriv + MPU_xQueueGetMutexHolder_Priv: + b MPU_xQueueGetMutexHolderImpl + MPU_xQueueGetMutexHolder_Unpriv: + svc #SYSTEM_CALL_xQueueGetMutexHolder +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueTakeMutexRecursive +MPU_xQueueTakeMutexRecursive: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xQueueTakeMutexRecursive_Unpriv + MPU_xQueueTakeMutexRecursive_Priv: + b MPU_xQueueTakeMutexRecursiveImpl + MPU_xQueueTakeMutexRecursive_Unpriv: + svc #SYSTEM_CALL_xQueueTakeMutexRecursive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGiveMutexRecursive +MPU_xQueueGiveMutexRecursive: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xQueueGiveMutexRecursive_Unpriv + MPU_xQueueGiveMutexRecursive_Priv: + b MPU_xQueueGiveMutexRecursiveImpl + MPU_xQueueGiveMutexRecursive_Unpriv: + svc #SYSTEM_CALL_xQueueGiveMutexRecursive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueSelectFromSet +MPU_xQueueSelectFromSet: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xQueueSelectFromSet_Unpriv + MPU_xQueueSelectFromSet_Priv: + b MPU_xQueueSelectFromSetImpl + MPU_xQueueSelectFromSet_Unpriv: + svc #SYSTEM_CALL_xQueueSelectFromSet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueAddToSet +MPU_xQueueAddToSet: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xQueueAddToSet_Unpriv + MPU_xQueueAddToSet_Priv: + b MPU_xQueueAddToSetImpl + MPU_xQueueAddToSet_Unpriv: + svc #SYSTEM_CALL_xQueueAddToSet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vQueueAddToRegistry +MPU_vQueueAddToRegistry: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vQueueAddToRegistry_Unpriv + MPU_vQueueAddToRegistry_Priv: + b MPU_vQueueAddToRegistryImpl + MPU_vQueueAddToRegistry_Unpriv: + svc #SYSTEM_CALL_vQueueAddToRegistry +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vQueueUnregisterQueue +MPU_vQueueUnregisterQueue: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vQueueUnregisterQueue_Unpriv + MPU_vQueueUnregisterQueue_Priv: + b MPU_vQueueUnregisterQueueImpl + MPU_vQueueUnregisterQueue_Unpriv: + svc #SYSTEM_CALL_vQueueUnregisterQueue +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pcQueueGetName +MPU_pcQueueGetName: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_pcQueueGetName_Unpriv + MPU_pcQueueGetName_Priv: + b MPU_pcQueueGetNameImpl + MPU_pcQueueGetName_Unpriv: + svc #SYSTEM_CALL_pcQueueGetName +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pvTimerGetTimerID +MPU_pvTimerGetTimerID: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_pvTimerGetTimerID_Unpriv + MPU_pvTimerGetTimerID_Priv: + b MPU_pvTimerGetTimerIDImpl + MPU_pvTimerGetTimerID_Unpriv: + svc #SYSTEM_CALL_pvTimerGetTimerID +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTimerSetTimerID +MPU_vTimerSetTimerID: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vTimerSetTimerID_Unpriv + MPU_vTimerSetTimerID_Priv: + b MPU_vTimerSetTimerIDImpl + MPU_vTimerSetTimerID_Unpriv: + svc #SYSTEM_CALL_vTimerSetTimerID +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerIsTimerActive +MPU_xTimerIsTimerActive: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTimerIsTimerActive_Unpriv + MPU_xTimerIsTimerActive_Priv: + b MPU_xTimerIsTimerActiveImpl + MPU_xTimerIsTimerActive_Unpriv: + svc #SYSTEM_CALL_xTimerIsTimerActive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetTimerDaemonTaskHandle +MPU_xTimerGetTimerDaemonTaskHandle: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv + MPU_xTimerGetTimerDaemonTaskHandle_Priv: + b MPU_xTimerGetTimerDaemonTaskHandleImpl + MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGenericCommandFromTaskEntry +MPU_xTimerGenericCommandFromTaskEntry: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTimerGenericCommandFromTask_Unpriv + MPU_xTimerGenericCommandFromTask_Priv: + b MPU_xTimerGenericCommandFromTaskImpl + MPU_xTimerGenericCommandFromTask_Unpriv: + svc #SYSTEM_CALL_xTimerGenericCommandFromTask +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pcTimerGetName +MPU_pcTimerGetName: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_pcTimerGetName_Unpriv + MPU_pcTimerGetName_Priv: + b MPU_pcTimerGetNameImpl + MPU_pcTimerGetName_Unpriv: + svc #SYSTEM_CALL_pcTimerGetName +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTimerSetReloadMode +MPU_vTimerSetReloadMode: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vTimerSetReloadMode_Unpriv + MPU_vTimerSetReloadMode_Priv: + b MPU_vTimerSetReloadModeImpl + MPU_vTimerSetReloadMode_Unpriv: + svc #SYSTEM_CALL_vTimerSetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetReloadMode +MPU_xTimerGetReloadMode: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTimerGetReloadMode_Unpriv + MPU_xTimerGetReloadMode_Priv: + b MPU_xTimerGetReloadModeImpl + MPU_xTimerGetReloadMode_Unpriv: + svc #SYSTEM_CALL_xTimerGetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTimerGetReloadMode +MPU_uxTimerGetReloadMode: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_uxTimerGetReloadMode_Unpriv + MPU_uxTimerGetReloadMode_Priv: + b MPU_uxTimerGetReloadModeImpl + MPU_uxTimerGetReloadMode_Unpriv: + svc #SYSTEM_CALL_uxTimerGetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetPeriod +MPU_xTimerGetPeriod: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTimerGetPeriod_Unpriv + MPU_xTimerGetPeriod_Priv: + b MPU_xTimerGetPeriodImpl + MPU_xTimerGetPeriod_Unpriv: + svc #SYSTEM_CALL_xTimerGetPeriod +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetExpiryTime +MPU_xTimerGetExpiryTime: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTimerGetExpiryTime_Unpriv + MPU_xTimerGetExpiryTime_Priv: + b MPU_xTimerGetExpiryTimeImpl + MPU_xTimerGetExpiryTime_Unpriv: + svc #SYSTEM_CALL_xTimerGetExpiryTime +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupWaitBitsEntry +MPU_xEventGroupWaitBitsEntry: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xEventGroupWaitBits_Unpriv + MPU_xEventGroupWaitBits_Priv: + b MPU_xEventGroupWaitBitsImpl + MPU_xEventGroupWaitBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupWaitBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupClearBits +MPU_xEventGroupClearBits: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xEventGroupClearBits_Unpriv + MPU_xEventGroupClearBits_Priv: + b MPU_xEventGroupClearBitsImpl + MPU_xEventGroupClearBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupClearBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupSetBits +MPU_xEventGroupSetBits: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xEventGroupSetBits_Unpriv + MPU_xEventGroupSetBits_Priv: + b MPU_xEventGroupSetBitsImpl + MPU_xEventGroupSetBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupSetBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupSync +MPU_xEventGroupSync: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xEventGroupSync_Unpriv + MPU_xEventGroupSync_Priv: + b MPU_xEventGroupSyncImpl + MPU_xEventGroupSync_Unpriv: + svc #SYSTEM_CALL_xEventGroupSync +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxEventGroupGetNumber +MPU_uxEventGroupGetNumber: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_uxEventGroupGetNumber_Unpriv + MPU_uxEventGroupGetNumber_Priv: + b MPU_uxEventGroupGetNumberImpl + MPU_uxEventGroupGetNumber_Unpriv: + svc #SYSTEM_CALL_uxEventGroupGetNumber +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vEventGroupSetNumber +MPU_vEventGroupSetNumber: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vEventGroupSetNumber_Unpriv + MPU_vEventGroupSetNumber_Priv: + b MPU_vEventGroupSetNumberImpl + MPU_vEventGroupSetNumber_Unpriv: + svc #SYSTEM_CALL_vEventGroupSetNumber +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSend +MPU_xStreamBufferSend: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xStreamBufferSend_Unpriv + MPU_xStreamBufferSend_Priv: + b MPU_xStreamBufferSendImpl + MPU_xStreamBufferSend_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferReceive +MPU_xStreamBufferReceive: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xStreamBufferReceive_Unpriv + MPU_xStreamBufferReceive_Priv: + b MPU_xStreamBufferReceiveImpl + MPU_xStreamBufferReceive_Unpriv: + svc #SYSTEM_CALL_xStreamBufferReceive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferIsFull +MPU_xStreamBufferIsFull: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xStreamBufferIsFull_Unpriv + MPU_xStreamBufferIsFull_Priv: + b MPU_xStreamBufferIsFullImpl + MPU_xStreamBufferIsFull_Unpriv: + svc #SYSTEM_CALL_xStreamBufferIsFull +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferIsEmpty +MPU_xStreamBufferIsEmpty: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xStreamBufferIsEmpty_Unpriv + MPU_xStreamBufferIsEmpty_Priv: + b MPU_xStreamBufferIsEmptyImpl + MPU_xStreamBufferIsEmpty_Unpriv: + svc #SYSTEM_CALL_xStreamBufferIsEmpty +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSpacesAvailable +MPU_xStreamBufferSpacesAvailable: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xStreamBufferSpacesAvailable_Unpriv + MPU_xStreamBufferSpacesAvailable_Priv: + b MPU_xStreamBufferSpacesAvailableImpl + MPU_xStreamBufferSpacesAvailable_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSpacesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferBytesAvailable +MPU_xStreamBufferBytesAvailable: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xStreamBufferBytesAvailable_Unpriv + MPU_xStreamBufferBytesAvailable_Priv: + b MPU_xStreamBufferBytesAvailableImpl + MPU_xStreamBufferBytesAvailable_Unpriv: + svc #SYSTEM_CALL_xStreamBufferBytesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSetTriggerLevel +MPU_xStreamBufferSetTriggerLevel: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xStreamBufferSetTriggerLevel_Unpriv + MPU_xStreamBufferSetTriggerLevel_Priv: + b MPU_xStreamBufferSetTriggerLevelImpl + MPU_xStreamBufferSetTriggerLevel_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferNextMessageLengthBytes +MPU_xStreamBufferNextMessageLengthBytes: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv + MPU_xStreamBufferNextMessageLengthBytes_Priv: + b MPU_xStreamBufferNextMessageLengthBytesImpl + MPU_xStreamBufferNextMessageLengthBytes_Unpriv: + svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes +/*-----------------------------------------------------------*/ + +/* Default weak implementations in case one is not available from + * mpu_wrappers because of config options. */ + + PUBWEAK MPU_xTaskDelayUntilImpl +MPU_xTaskDelayUntilImpl: + b MPU_xTaskDelayUntilImpl + + PUBWEAK MPU_xTaskAbortDelayImpl +MPU_xTaskAbortDelayImpl: + b MPU_xTaskAbortDelayImpl + + PUBWEAK MPU_vTaskDelayImpl +MPU_vTaskDelayImpl: + b MPU_vTaskDelayImpl + + PUBWEAK MPU_uxTaskPriorityGetImpl +MPU_uxTaskPriorityGetImpl: + b MPU_uxTaskPriorityGetImpl + + PUBWEAK MPU_eTaskGetStateImpl +MPU_eTaskGetStateImpl: + b MPU_eTaskGetStateImpl + + PUBWEAK MPU_vTaskGetInfoImpl +MPU_vTaskGetInfoImpl: + b MPU_vTaskGetInfoImpl + + PUBWEAK MPU_xTaskGetIdleTaskHandleImpl +MPU_xTaskGetIdleTaskHandleImpl: + b MPU_xTaskGetIdleTaskHandleImpl + + PUBWEAK MPU_vTaskSuspendImpl +MPU_vTaskSuspendImpl: + b MPU_vTaskSuspendImpl + + PUBWEAK MPU_vTaskResumeImpl +MPU_vTaskResumeImpl: + b MPU_vTaskResumeImpl + + PUBWEAK MPU_xTaskGetTickCountImpl +MPU_xTaskGetTickCountImpl: + b MPU_xTaskGetTickCountImpl + + PUBWEAK MPU_uxTaskGetNumberOfTasksImpl +MPU_uxTaskGetNumberOfTasksImpl: + b MPU_uxTaskGetNumberOfTasksImpl + + PUBWEAK MPU_ulTaskGetRunTimeCounterImpl +MPU_ulTaskGetRunTimeCounterImpl: + b MPU_ulTaskGetRunTimeCounterImpl + + PUBWEAK MPU_ulTaskGetRunTimePercentImpl +MPU_ulTaskGetRunTimePercentImpl: + b MPU_ulTaskGetRunTimePercentImpl + + PUBWEAK MPU_ulTaskGetIdleRunTimePercentImpl +MPU_ulTaskGetIdleRunTimePercentImpl: + b MPU_ulTaskGetIdleRunTimePercentImpl + + PUBWEAK MPU_ulTaskGetIdleRunTimeCounterImpl +MPU_ulTaskGetIdleRunTimeCounterImpl: + b MPU_ulTaskGetIdleRunTimeCounterImpl + + PUBWEAK MPU_vTaskSetApplicationTaskTagImpl +MPU_vTaskSetApplicationTaskTagImpl: + b MPU_vTaskSetApplicationTaskTagImpl + + PUBWEAK MPU_xTaskGetApplicationTaskTagImpl +MPU_xTaskGetApplicationTaskTagImpl: + b MPU_xTaskGetApplicationTaskTagImpl + + PUBWEAK MPU_vTaskSetThreadLocalStoragePointerImpl +MPU_vTaskSetThreadLocalStoragePointerImpl: + b MPU_vTaskSetThreadLocalStoragePointerImpl + + PUBWEAK MPU_pvTaskGetThreadLocalStoragePointerImpl +MPU_pvTaskGetThreadLocalStoragePointerImpl: + b MPU_pvTaskGetThreadLocalStoragePointerImpl + + PUBWEAK MPU_uxTaskGetSystemStateImpl +MPU_uxTaskGetSystemStateImpl: + b MPU_uxTaskGetSystemStateImpl + + PUBWEAK MPU_uxTaskGetStackHighWaterMarkImpl +MPU_uxTaskGetStackHighWaterMarkImpl: + b MPU_uxTaskGetStackHighWaterMarkImpl + + PUBWEAK MPU_uxTaskGetStackHighWaterMark2Impl +MPU_uxTaskGetStackHighWaterMark2Impl: + b MPU_uxTaskGetStackHighWaterMark2Impl + + PUBWEAK MPU_xTaskGetCurrentTaskHandleImpl +MPU_xTaskGetCurrentTaskHandleImpl: + b MPU_xTaskGetCurrentTaskHandleImpl + + PUBWEAK MPU_xTaskGetSchedulerStateImpl +MPU_xTaskGetSchedulerStateImpl: + b MPU_xTaskGetSchedulerStateImpl + + PUBWEAK MPU_vTaskSetTimeOutStateImpl +MPU_vTaskSetTimeOutStateImpl: + b MPU_vTaskSetTimeOutStateImpl + + PUBWEAK MPU_xTaskCheckForTimeOutImpl +MPU_xTaskCheckForTimeOutImpl: + b MPU_xTaskCheckForTimeOutImpl + + PUBWEAK MPU_xTaskGenericNotifyImpl +MPU_xTaskGenericNotifyImpl: + b MPU_xTaskGenericNotifyImpl + + PUBWEAK MPU_xTaskGenericNotifyWaitImpl +MPU_xTaskGenericNotifyWaitImpl: + b MPU_xTaskGenericNotifyWaitImpl + + PUBWEAK MPU_ulTaskGenericNotifyTakeImpl +MPU_ulTaskGenericNotifyTakeImpl: + b MPU_ulTaskGenericNotifyTakeImpl + + PUBWEAK MPU_xTaskGenericNotifyStateClearImpl +MPU_xTaskGenericNotifyStateClearImpl: + b MPU_xTaskGenericNotifyStateClearImpl + + PUBWEAK MPU_ulTaskGenericNotifyValueClearImpl +MPU_ulTaskGenericNotifyValueClearImpl: + b MPU_ulTaskGenericNotifyValueClearImpl + + PUBWEAK MPU_xQueueGenericSendImpl +MPU_xQueueGenericSendImpl: + b MPU_xQueueGenericSendImpl + + PUBWEAK MPU_uxQueueMessagesWaitingImpl +MPU_uxQueueMessagesWaitingImpl: + b MPU_uxQueueMessagesWaitingImpl + + PUBWEAK MPU_uxQueueSpacesAvailableImpl +MPU_uxQueueSpacesAvailableImpl: + b MPU_uxQueueSpacesAvailableImpl + + PUBWEAK MPU_xQueueReceiveImpl +MPU_xQueueReceiveImpl: + b MPU_xQueueReceiveImpl + + PUBWEAK MPU_xQueuePeekImpl +MPU_xQueuePeekImpl: + b MPU_xQueuePeekImpl + + PUBWEAK MPU_xQueueSemaphoreTakeImpl +MPU_xQueueSemaphoreTakeImpl: + b MPU_xQueueSemaphoreTakeImpl + + PUBWEAK MPU_xQueueGetMutexHolderImpl +MPU_xQueueGetMutexHolderImpl: + b MPU_xQueueGetMutexHolderImpl + + PUBWEAK MPU_xQueueTakeMutexRecursiveImpl +MPU_xQueueTakeMutexRecursiveImpl: + b MPU_xQueueTakeMutexRecursiveImpl + + PUBWEAK MPU_xQueueGiveMutexRecursiveImpl +MPU_xQueueGiveMutexRecursiveImpl: + b MPU_xQueueGiveMutexRecursiveImpl + + PUBWEAK MPU_xQueueSelectFromSetImpl +MPU_xQueueSelectFromSetImpl: + b MPU_xQueueSelectFromSetImpl + + PUBWEAK MPU_xQueueAddToSetImpl +MPU_xQueueAddToSetImpl: + b MPU_xQueueAddToSetImpl + + PUBWEAK MPU_vQueueAddToRegistryImpl +MPU_vQueueAddToRegistryImpl: + b MPU_vQueueAddToRegistryImpl + + PUBWEAK MPU_vQueueUnregisterQueueImpl +MPU_vQueueUnregisterQueueImpl: + b MPU_vQueueUnregisterQueueImpl + + PUBWEAK MPU_pcQueueGetNameImpl +MPU_pcQueueGetNameImpl: + b MPU_pcQueueGetNameImpl + + PUBWEAK MPU_pvTimerGetTimerIDImpl +MPU_pvTimerGetTimerIDImpl: + b MPU_pvTimerGetTimerIDImpl + + PUBWEAK MPU_vTimerSetTimerIDImpl +MPU_vTimerSetTimerIDImpl: + b MPU_vTimerSetTimerIDImpl + + PUBWEAK MPU_xTimerIsTimerActiveImpl +MPU_xTimerIsTimerActiveImpl: + b MPU_xTimerIsTimerActiveImpl + + PUBWEAK MPU_xTimerGetTimerDaemonTaskHandleImpl +MPU_xTimerGetTimerDaemonTaskHandleImpl: + b MPU_xTimerGetTimerDaemonTaskHandleImpl + + PUBWEAK MPU_xTimerGenericCommandFromTaskImpl +MPU_xTimerGenericCommandFromTaskImpl: + b MPU_xTimerGenericCommandFromTaskImpl + + PUBWEAK MPU_pcTimerGetNameImpl +MPU_pcTimerGetNameImpl: + b MPU_pcTimerGetNameImpl + + PUBWEAK MPU_vTimerSetReloadModeImpl +MPU_vTimerSetReloadModeImpl: + b MPU_vTimerSetReloadModeImpl + + PUBWEAK MPU_xTimerGetReloadModeImpl +MPU_xTimerGetReloadModeImpl: + b MPU_xTimerGetReloadModeImpl + + PUBWEAK MPU_uxTimerGetReloadModeImpl +MPU_uxTimerGetReloadModeImpl: + b MPU_uxTimerGetReloadModeImpl + + PUBWEAK MPU_xTimerGetPeriodImpl +MPU_xTimerGetPeriodImpl: + b MPU_xTimerGetPeriodImpl + + PUBWEAK MPU_xTimerGetExpiryTimeImpl +MPU_xTimerGetExpiryTimeImpl: + b MPU_xTimerGetExpiryTimeImpl + + PUBWEAK MPU_xEventGroupWaitBitsImpl +MPU_xEventGroupWaitBitsImpl: + b MPU_xEventGroupWaitBitsImpl + + PUBWEAK MPU_xEventGroupClearBitsImpl +MPU_xEventGroupClearBitsImpl: + b MPU_xEventGroupClearBitsImpl + + PUBWEAK MPU_xEventGroupSetBitsImpl +MPU_xEventGroupSetBitsImpl: + b MPU_xEventGroupSetBitsImpl + + PUBWEAK MPU_xEventGroupSyncImpl +MPU_xEventGroupSyncImpl: + b MPU_xEventGroupSyncImpl + + PUBWEAK MPU_uxEventGroupGetNumberImpl +MPU_uxEventGroupGetNumberImpl: + b MPU_uxEventGroupGetNumberImpl + + PUBWEAK MPU_vEventGroupSetNumberImpl +MPU_vEventGroupSetNumberImpl: + b MPU_vEventGroupSetNumberImpl + + PUBWEAK MPU_xStreamBufferSendImpl +MPU_xStreamBufferSendImpl: + b MPU_xStreamBufferSendImpl + + PUBWEAK MPU_xStreamBufferReceiveImpl +MPU_xStreamBufferReceiveImpl: + b MPU_xStreamBufferReceiveImpl + + PUBWEAK MPU_xStreamBufferIsFullImpl +MPU_xStreamBufferIsFullImpl: + b MPU_xStreamBufferIsFullImpl + + PUBWEAK MPU_xStreamBufferIsEmptyImpl +MPU_xStreamBufferIsEmptyImpl: + b MPU_xStreamBufferIsEmptyImpl + + PUBWEAK MPU_xStreamBufferSpacesAvailableImpl +MPU_xStreamBufferSpacesAvailableImpl: + b MPU_xStreamBufferSpacesAvailableImpl + + PUBWEAK MPU_xStreamBufferBytesAvailableImpl +MPU_xStreamBufferBytesAvailableImpl: + b MPU_xStreamBufferBytesAvailableImpl + + PUBWEAK MPU_xStreamBufferSetTriggerLevelImpl +MPU_xStreamBufferSetTriggerLevelImpl: + b MPU_xStreamBufferSetTriggerLevelImpl + + PUBWEAK MPU_xStreamBufferNextMessageLengthBytesImpl +MPU_xStreamBufferNextMessageLengthBytesImpl: + b MPU_xStreamBufferNextMessageLengthBytesImpl + +/*-----------------------------------------------------------*/ + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + END diff --git a/portable/IAR/ARM_CM23/non_secure/port.c b/portable/IAR/ARM_CM23/non_secure/port.c new file mode 100644 index 000000000..76d2b2445 --- /dev/null +++ b/portable/IAR/ARM_CM23/non_secure/port.c @@ -0,0 +1,2280 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024-2025 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU includes. */ +#include "mpu_wrappers.h" +#include "mpu_syscall_numbers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration settings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to check the validity of an interrupt priority. + */ +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) ) +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used during system call enter and exit. + */ +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Offsets in the stack to the parameters when inside the SVC handler. + */ +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +#if ( portARMV8M_MINOR_VERSION >= 1 ) + + /* Enable Privileged eXecute Never MPU attribute for the selected memory + * region. */ + #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL ) +#endif /* portARMV8M_MINOR_VERSION >= 1 */ + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Extract first address of the MPU region as encoded in the + * RBAR (Region Base Address Register) value. */ +#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \ + ( ( rbar ) & portMPU_RBAR_ADDRESS_MASK ) + +/* Extract last address of the MPU region as encoded in the + * RLAR (Region Limit Address Register) value. */ +#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \ + ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK ) + +/* Does addr lies within [start, end] address range? */ +#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \ + ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) ) + +/* Is the access request satisfied by the available permissions? */ +#define portIS_AUTHORIZED( accessRequest, permissions ) \ + ( ( ( permissions ) & ( accessRequest ) ) == accessRequest ) + +/* Max value that fits in a uint32_t type. */ +#define portUINT32_MAX ( ~( ( uint32_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. + */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 + +/** + * @brief Constants required to check and configure PACBTI security feature implementation. + */ +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) ) + + #define portCONTROL_UPAC_EN ( 1UL << 7UL ) + #define portCONTROL_PAC_EN ( 1UL << 6UL ) + #define portCONTROL_UBTI_EN ( 1UL << 5UL ) + #define portCONTROL_BTI_EN ( 1UL << 4UL ) + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Extract MPU region's access permissions from the Region Base Address + * Register (RBAR) value. + * + * @param ulRBARValue RBAR value for the MPU region. + * + * @return uint32_t Access permissions. + */ + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + + /** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + /** + * @brief Configures PACBTI features. + * + * This function configures the Pointer Authentication, and Branch Target + * Identification security features as per the user configuration. It returns + * the value of the special purpose CONTROL register accordingly, and optionally + * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M + * architecture based) target supports PACBTI security feature. + * + * @param xWriteControlRegister Used to control whether the special purpose + * CONTROL register should be updated or not. + * + * @return CONTROL register value according to the configured PACBTI option. + */ + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the system call stack so that upon returning from + * SVC, the system call stack is used. + * + * @param pulTaskStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + * @param ucSystemCallNumber The system call number of the system call. + */ + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Raise SVC for exiting from a system call. + */ + void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief This variable is set to pdTRUE when the scheduler is started. + */ + PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + + /** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +/** + * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + /** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + + /** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + + /** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the cpsid instruction + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessPermissions = 0; + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_ONLY ) + { + ulAccessPermissions = tskMPU_READ_PERMISSION; + } + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_WRITE ) + { + ulAccessPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION ); + } + + return ulAccessPermissions; + } + +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } + +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ portOFFSET_TO_PC ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ]; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulSystemCallStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the system call section (i.e. application is + * not raising SVC directly). + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as + * it is non-NULL only during the execution of a system call (i.e. + * between system call enter and exit). + * 3. System call is not for a kernel API disabled by the configuration + * in FreeRTOSConfig.h. + * 4. We do not need to check that ucSystemCallNumber is within range + * because the assembly SVC handler checks that before calling + * this function. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) && + ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) ) + { + pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the system call stack for the stack frame. */ + pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulSystemCallStack[ i ] = pulTaskStack[ i ]; + } + + /* Store the value of the Link Register before the SVC was raised. + * It contains the address of the caller of the System Call entry + * point (i.e. the caller of the MPU_). We need to restore it + * when we exit from the system call. */ + pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; + + /* Store the value of the PSPLIM register before the SVC was raised. + * We need to restore it when we exit from the system call. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* Use the pulSystemCallStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif + + /* Start executing the system call upon returning from this handler. */ + pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; + + /* Raise a request to exit from the system call upon finishing the + * system call. */ + pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; + + /* Remember the location where we should copy the stack frame when we exit from + * the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize; + + /* Record if the hardware used padding to force the stack pointer + * to be double word aligned. */ + if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK ) + { + pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG; + } + else + { + pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG ); + } + + /* We ensure in pxPortInitialiseStack that the system call stack is + * double word aligned and therefore, there is no need of padding. + * Clear the bit[9] of stacked xPSR. */ + pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + + /* Raise the privilege for the duration of the system call. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " bics r0, r1 \n" /* Clear nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */ + { + __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulTaskStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the privileged code (i.e. application is not + * raising SVC directly). This SVC is only raised from + * vRequestSystemCallExit which is in the privileged code section. + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL - + * this means that we previously entered a system call and the + * application is not attempting to exit without entering a system + * call. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) ) + { + pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the task stack for the stack frame. */ + pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulTaskStack[ i ] = pulSystemCallStack[ i ]; + } + + /* Use the pulTaskStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) ); + + /* Return to the caller of the System Call entry point (i.e. the + * caller of the MPU_). */ + pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + /* Ensure that LR has a valid value.*/ + pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + + /* Restore the PSPLIM register to what it was at the time of + * system call entry. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* If the hardware used padding to force the stack pointer + * to be double word aligned, set the stacked xPSR bit[9], + * otherwise clear it. */ + if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG ) + { + pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK; + } + else + { + pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + } + + /* This is not NULL only for the duration of the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; + + /* Drop the privilege before returning to the thread mode. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " orrs r0, r1 \n" /* Set nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xTaskIsPrivileged = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xTaskIsPrivileged = pdTRUE; + } + + return xTaskIsPrivileged; + } + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged, + xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulIndex = 0; + uint32_t ulControl = 0x0; + + xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ + ulIndex++; + + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + ulIndex++; + + #if ( configENABLE_TRUSTZONE == 1 ) + { + xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */ + ulIndex++; + } + #endif /* configENABLE_TRUSTZONE */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + ulIndex++; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Check PACBTI security feature configuration before pushing the + * CONTROL register's value on task's TCB. */ + ulControl = prvConfigurePACBTI( pdFALSE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + if( xRunPrivileged == pdTRUE ) + { + xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + else + { + xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG ); + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ + ulIndex++; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + { + /* Ensure that the system call stack is double word aligned. */ + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) + + ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + /* This is not NULL only for the duration of a system call. */ + xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL; + } + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ]; + ulIndex++; + } + } + #endif /* configENABLE_PAC */ + + return &( xMPUSettings->ulContext[ ulIndex ] ); + } + +#else /* configENABLE_MPU */ + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ + { + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + pxTopOfStack--; + *pxTopOfStack = ulTaskPacKey[ i ]; + } + } + #endif /* configENABLE_PAC */ + + return pxTopOfStack; + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Set the CONTROL register value based on PACBTI security feature + * configuration before starting the first task. */ + ( void ) prvConfigurePACBTI( pdTRUE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + { + xSchedulerRunning = pdTRUE; + } + #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + configSTACK_DEPTH_TYPE uxStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( uxStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* PXN. */ + #if ( portARMV8M_MINOR_VERSION >= 1 ) + { + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ); + } + } + #endif /* portARMV8M_MINOR_VERSION >= 1 */ + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, + uint32_t ulBufferLength, + uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */ + + { + uint32_t i, ulBufferStartAddress, ulBufferEndAddress; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE ) + { + ulBufferStartAddress = ( uint32_t ) pvBuffer; + ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL ); + + for( i = 0; i < portTOTAL_NUM_REGIONS; i++ ) + { + /* Is the MPU region enabled? */ + if( ( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR & portMPU_RLAR_REGION_ENABLE ) == portMPU_RLAR_REGION_ENABLE ) + { + if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_AUTHORIZED( ulAccessRequested, + prvGetRegionAccessPermissions( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ) ) ) + { + xAccessGranted = pdTRUE; + break; + } + } + } + } + } + + return xAccessGranted; + } + +#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings; + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else + { + xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 ) + { + xAccessGranted = pdTRUE; + } + } + } + + return xAccessGranted; + } + + #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + ( void ) lInternalIndexOfKernelObject; + + /* If Access Control List feature is not used, all the tasks have + * access to all the kernel objects. */ + return pdTRUE; + } + + #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + { + uint32_t ulControl = 0x0; + + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); + + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; + + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/ARM_CM23/non_secure/portasm.h b/portable/IAR/ARM_CM23/non_secure/portasm.h new file mode 100644 index 000000000..b7021b024 --- /dev/null +++ b/portable/IAR/ARM_CM23/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kernel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/portable/IAR/ARM_CM23/non_secure/portasm.s b/portable/IAR/ARM_CM23/non_secure/portasm.s new file mode 100644 index 000000000..6817abd7a --- /dev/null +++ b/portable/IAR/ARM_CM23/non_secure/portasm.s @@ -0,0 +1,525 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" + +/* System call numbers includes. */ +#include "mpu_syscall_numbers.h" + +#ifndef configUSE_MPU_WRAPPERS_V1 + #define configUSE_MPU_WRAPPERS_V1 0 +#endif + + + EXTERN pxCurrentTCB + EXTERN xSecureContext + EXTERN vTaskSwitchContext + EXTERN vPortSVCHandler_C + EXTERN SecureContext_SaveContext + EXTERN SecureContext_LoadContext +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + EXTERN vSystemCallEnter + EXTERN vSystemCallExit +#endif + + PUBLIC xIsPrivileged + PUBLIC vResetPrivilege + PUBLIC vPortAllocateSecureContext + PUBLIC vRestoreContextOfFirstTask + PUBLIC vRaisePrivilege + PUBLIC vStartFirstTask + PUBLIC ulSetInterruptMask + PUBLIC vClearInterruptMask + PUBLIC PendSV_Handler + PUBLIC SVC_Handler + PUBLIC vPortFreeSecureContext + +#if ( configENABLE_FPU == 1 ) + #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0. +#endif +/*-----------------------------------------------------------*/ + +/*---------------- Unprivileged Functions -------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION .text:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +xIsPrivileged: + mrs r0, control /* r0 = CONTROL. */ + movs r1, #1 /* r1 = 1. */ + tst r0, r1 /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */ + beq running_privileged /* If the result of previous AND operation was 0, branch. */ + movs r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + bx lr /* Return. */ + running_privileged: + movs r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vResetPrivilege: + mrs r0, control /* r0 = CONTROL. */ + movs r1, #1 /* r1 = 1. */ + orrs r0, r1 /* r0 = r0 | r1. */ + msr control, r0 /* CONTROL = r0. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vPortAllocateSecureContext: + svc 100 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 100. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +/*----------------- Privileged Functions --------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION privileged_functions:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +vRestoreContextOfFirstTask: + program_mpu_first_task: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r3] /* r0 = pxCurrentTCB.*/ + + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + movs r3, #1 /* r3 = 1. */ + bics r2, r3 /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */ + str r2, [r1] /* Disable MPU. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r1, [r2] /* Program MAIR0. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */ + + movs r3, #4 /* r3 = 4. */ + str r3, [r1] /* Program RNR = 4. */ + ldmia r0!, {r4-r5} /* Read first set of RBAR/RLAR registers from TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + stmia r2!, {r4-r5} /* Write first set of RBAR/RLAR registers. */ + movs r3, #5 /* r3 = 5. */ + str r3, [r1] /* Program RNR = 5. */ + ldmia r0!, {r4-r5} /* Read second set of RBAR/RLAR registers from TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + stmia r2!, {r4-r5} /* Write second set of RBAR/RLAR registers. */ + movs r3, #6 /* r3 = 6. */ + str r3, [r1] /* Program RNR = 6. */ + ldmia r0!, {r4-r5} /* Read third set of RBAR/RLAR registers from TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + stmia r2!, {r4-r5} /* Write third set of RBAR/RLAR registers. */ + movs r3, #7 /* r3 = 6. */ + str r3, [r1] /* Program RNR = 7. */ + ldmia r0!, {r4-r5} /* Read fourth set of RBAR/RLAR registers from TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + stmia r2!, {r4-r5} /* Write fourth set of RBAR/RLAR registers. */ + + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + movs r3, #1 /* r3 = 1. */ + orrs r2, r3 /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */ + str r2, [r1] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + + restore_context_first_task: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* r1 = pxCurrentTCB.*/ + ldr r2, [r1] /* r2 = Location of saved context in TCB. */ + + restore_special_regs_first_task: + subs r2, #20 + ldmia r2!, {r0, r3-r6} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */ + subs r2, #20 + msr psp, r3 + msr control, r5 + mov lr, r6 + ldr r4, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + str r0, [r4] /* Restore xSecureContext. */ + + restore_general_regs_first_task: + subs r2, #32 + ldmia r2!, {r4-r7} /* r4-r7 contain half of the hardware saved context. */ + stmia r3!, {r4-r7} /* Copy half of the the hardware saved context on the task stack. */ + ldmia r2!, {r4-r7} /* r4-r7 contain rest half of the hardware saved context. */ + stmia r3!, {r4-r7} /* Copy rest half of the the hardware saved context on the task stack. */ + subs r2, #48 + ldmia r2!, {r4-r7} /* Restore r8-r11. */ + mov r8, r4 /* r8 = r4. */ + mov r9, r5 /* r9 = r5. */ + mov r10, r6 /* r10 = r6. */ + mov r11, r7 /* r11 = r7. */ + subs r2, #32 + ldmia r2!, {r4-r7} /* Restore r4-r7. */ + subs r2, #16 + + restore_context_done_first_task: + str r2, [r1] /* Save the location where the context should be saved next as the first member of TCB. */ + bx lr + +#else /* configENABLE_MPU */ + +vRestoreContextOfFirstTask: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r3, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + + ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */ + ldr r4, =xSecureContext + str r1, [r4] /* Set xSecureContext to this task's value for the same. */ + movs r1, #2 /* r1 = 2. */ + msr CONTROL, r1 /* Switch to use PSP in the thread mode. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + bx r3 /* Finally, branch to EXC_RETURN. */ + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +vRaisePrivilege: + mrs r0, control /* Read the CONTROL register. */ + movs r1, #1 /* r1 = 1. */ + bics r0, r1 /* Clear the bit 0. */ + msr control, r0 /* Write back the new CONTROL value. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vStartFirstTask: + ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */ + ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */ + ldr r0, [r0] /* The first entry in vector table is stack pointer. */ + msr msp, r0 /* Set the MSP back to the start of the stack. */ + cpsie i /* Globally enable interrupts. */ + dsb + isb + svc 102 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */ +/*-----------------------------------------------------------*/ + +ulSetInterruptMask: + mrs r0, PRIMASK + cpsid i + bx lr +/*-----------------------------------------------------------*/ + +vClearInterruptMask: + msr PRIMASK, r0 + bx lr +/*-----------------------------------------------------------*/ +#if ( configENABLE_MPU == 1 ) + +PendSV_Handler: + ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + ldr r0, [r3] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later.*/ + ldr r2, [r1] /* r2 = Location in TCB where the context should be saved. */ + + cbz r0, save_ns_context /* No secure context to save. */ + save_s_context: + push {r0-r2, lr} + bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r0-r3} /* LR is now in r3. */ + mov lr, r3 /* Restore LR. */ + + save_ns_context: + mov r3, lr /* r3 = LR (EXC_RETURN). */ + lsls r3, r3, #25 /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bmi save_special_regs /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + + save_general_regs: + mrs r3, psp + stmia r2!, {r4-r7} /* Store r4-r7. */ + mov r4, r8 /* r4 = r8. */ + mov r5, r9 /* r5 = r9. */ + mov r6, r10 /* r6 = r10. */ + mov r7, r11 /* r7 = r11. */ + stmia r2!, {r4-r7} /* Store r8-r11. */ + ldmia r3!, {r4-r7} /* Copy half of the hardware saved context into r4-r7. */ + stmia r2!, {r4-r7} /* Store the hardware saved context. */ + ldmia r3!, {r4-r7} /* Copy rest half of the hardware saved context into r4-r7. */ + stmia r2!, {r4-r7} /* Store the hardware saved context. */ + + save_special_regs: + mrs r3, psp /* r3 = PSP. */ + movs r4, #0 /* r4 = 0. 0 is stored in the PSPLIM slot. */ + mrs r5, control /* r5 = CONTROL. */ + mov r6, lr /* r6 = LR. */ + stmia r2!, {r0, r3-r6} /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ + str r2, [r1] /* Save the location from where the context should be restored as the first member of TCB. */ + + select_next_task: + cpsid i + bl vTaskSwitchContext + cpsie i + + program_mpu: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r3] /* r0 = pxCurrentTCB.*/ + + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + movs r3, #1 /* r3 = 1. */ + bics r2, r3 /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */ + str r2, [r1] /* Disable MPU. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r1, [r2] /* Program MAIR0. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */ + + movs r3, #4 /* r3 = 4. */ + str r3, [r1] /* Program RNR = 4. */ + ldmia r0!, {r4-r5} /* Read first set of RBAR/RLAR registers from TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + stmia r2!, {r4-r5} /* Write first set of RBAR/RLAR registers. */ + movs r3, #5 /* r3 = 5. */ + str r3, [r1] /* Program RNR = 5. */ + ldmia r0!, {r4-r5} /* Read second set of RBAR/RLAR registers from TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + stmia r2!, {r4-r5} /* Write second set of RBAR/RLAR registers. */ + movs r3, #6 /* r3 = 6. */ + str r3, [r1] /* Program RNR = 6. */ + ldmia r0!, {r4-r5} /* Read third set of RBAR/RLAR registers from TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + stmia r2!, {r4-r5} /* Write third set of RBAR/RLAR registers. */ + movs r3, #7 /* r3 = 6. */ + str r3, [r1] /* Program RNR = 7. */ + ldmia r0!, {r4-r5} /* Read fourth set of RBAR/RLAR registers from TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + stmia r2!, {r4-r5} /* Write fourth set of RBAR/RLAR registers. */ + + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + movs r3, #1 /* r3 = 1. */ + orrs r2, r3 /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */ + str r2, [r1] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + + restore_context: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* r1 = pxCurrentTCB.*/ + ldr r2, [r1] /* r2 = Location of saved context in TCB. */ + + restore_special_regs: + subs r2, #20 + ldmia r2!, {r0, r3-r6} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */ + subs r2, #20 + msr psp, r3 + msr control, r5 + mov lr, r6 + ldr r4, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + str r0, [r4] /* Restore xSecureContext. */ + cbz r0, restore_ns_context /* No secure context to restore. */ + + restore_s_context: + push {r1-r3, lr} + bl SecureContext_LoadContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r1-r4} /* LR is now in r4. */ + mov lr, r4 + + restore_ns_context: + mov r0, lr /* r0 = LR (EXC_RETURN). */ + lsls r0, r0, #25 /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bmi restore_context_done /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + + restore_general_regs: + subs r2, #32 + ldmia r2!, {r4-r7} /* r4-r7 contain half of the hardware saved context. */ + stmia r3!, {r4-r7} /* Copy half of the the hardware saved context on the task stack. */ + ldmia r2!, {r4-r7} /* r4-r7 contain rest half of the hardware saved context. */ + stmia r3!, {r4-r7} /* Copy rest half of the the hardware saved context on the task stack. */ + subs r2, #48 + ldmia r2!, {r4-r7} /* Restore r8-r11. */ + mov r8, r4 /* r8 = r4. */ + mov r9, r5 /* r9 = r5. */ + mov r10, r6 /* r10 = r6. */ + mov r11, r7 /* r11 = r7. */ + subs r2, #32 + ldmia r2!, {r4-r7} /* Restore r4-r7. */ + subs r2, #16 + + restore_context_done: + str r2, [r1] /* Save the location where the context should be saved next as the first member of TCB. */ + bx lr + +#else /* configENABLE_MPU */ + +PendSV_Handler: + ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + ldr r0, [r3] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */ + mrs r2, psp /* Read PSP in r2. */ + + cbz r0, save_ns_context /* No secure context to save. */ + push {r0-r2, r14} + bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r0-r3} /* LR is now in r3. */ + mov lr, r3 /* LR = r3. */ + lsls r1, r3, #25 /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bpl save_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB. */ + + subs r2, r2, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */ + str r2, [r1] /* Save the new top of stack in TCB. */ + movs r1, #0 /* r1 = 0. 0 is stored in the PSPLIM slot. */ + mov r3, lr /* r3 = LR/EXC_RETURN. */ + stmia r2!, {r0, r1, r3} /* Store xSecureContext, PSPLIM and LR on the stack. */ + + b select_next_task + + save_ns_context: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB. */ + subs r2, r2, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */ + str r2, [r1] /* Save the new top of stack in TCB. */ + movs r1, #0 /* r1 = 0. 0 is stored in the PSPLIM slot. */ + mov r3, lr /* r3 = LR/EXC_RETURN. */ + stmia r2!, {r0, r1, r3-r7} /* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */ + mov r4, r8 /* r4 = r8. */ + mov r5, r9 /* r5 = r9. */ + mov r6, r10 /* r6 = r10. */ + mov r7, r11 /* r7 = r11. */ + stmia r2!, {r4-r7} /* Store the high registers that are not saved automatically. */ + + select_next_task: + cpsid i + bl vTaskSwitchContext + cpsie i + + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB. */ + ldr r2, [r1] /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */ + + ldmia r2!, {r0, r1, r4} /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */ + mov lr, r4 /* LR = r4. */ + ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + str r0, [r3] /* Restore the task's xSecureContext. */ + cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */ + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB. */ + push {r2, r4} + bl SecureContext_LoadContext /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r2, r4} + mov lr, r4 /* LR = r4. */ + lsls r1, r4, #25 /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bpl restore_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + msr psp, r2 /* Remember the new top of stack for the task. */ + bx lr + + restore_ns_context: + adds r2, r2, #16 /* Move to the high registers. */ + ldmia r2!, {r4-r7} /* Restore the high registers that are not automatically restored. */ + mov r8, r4 /* r8 = r4. */ + mov r9, r5 /* r9 = r5. */ + mov r10, r6 /* r10 = r6. */ + mov r11, r7 /* r11 = r7. */ + msr psp, r2 /* Remember the new top of stack for the task. */ + subs r2, r2, #32 /* Go back to the low registers. */ + ldmia r2!, {r4-r7} /* Restore the low registers that are not automatically restored. */ + bx lr + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + +SVC_Handler: + movs r0, #4 + mov r1, lr + tst r0, r1 + beq stack_on_msp + stack_on_psp: + mrs r0, psp + b route_svc + stack_on_msp: + mrs r0, msp + b route_svc + + route_svc: + ldr r3, [r0, #24] + subs r3, #2 + ldrb r2, [r3, #0] + cmp r2, #NUM_SYSTEM_CALLS + blt system_call_enter + cmp r2, #104 /* portSVC_SYSTEM_CALL_EXIT. */ + beq system_call_exit + b vPortSVCHandler_C + + system_call_enter: + b vSystemCallEnter + system_call_exit: + b vSystemCallExit + +#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +SVC_Handler: + movs r0, #4 + mov r1, lr + tst r0, r1 + beq stacking_used_msp + mrs r0, psp + b vPortSVCHandler_C + stacking_used_msp: + mrs r0, msp + b vPortSVCHandler_C + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +vPortFreeSecureContext: + ldr r2, [r0] /* The first item in the TCB is the top of the stack. */ + ldr r1, [r2] /* The first item on the stack is the task's xSecureContext. */ + cmp r1, #0 /* Raise svc if task's xSecureContext is not NULL. */ + bne free_secure_context /* Branch if r1 != 0. */ + bx lr /* There is no secure context (xSecureContext is NULL). */ + free_secure_context: + svc 101 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 101. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + + END diff --git a/portable/IAR/ARM_CM23/non_secure/portmacro.h b/portable/IAR/ARM_CM23/non_secure/portmacro.h new file mode 100644 index 000000000..9d6c3368e --- /dev/null +++ b/portable/IAR/ARM_CM23/non_secure/portmacro.h @@ -0,0 +1,92 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M23" +#define portHAS_ARMV8M_MAIN_EXTENSION 0 +#define portARMV8M_MINOR_VERSION 0 +#define portDONT_DISCARD __root +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +#if ( configTOTAL_MPU_REGIONS == 16 ) + #error 16 MPU regions are not yet supported for this port. +#endif + +#ifndef configENABLE_MVE + #define configENABLE_MVE 0 +#elif ( configENABLE_MVE != 0 ) + #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M23. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" ) +#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ +#pragma diag_suppress=Be006 +#pragma diag_suppress=Pa082 +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h new file mode 100644 index 000000000..f373bcad5 --- /dev/null +++ b/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h @@ -0,0 +1,582 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACROCOMMON_H +#define PORTMACROCOMMON_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. +#endif /* configENABLE_FPU */ + +#ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. +#endif /* configENABLE_MPU */ + +#ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. +#endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() +#define portINLINE __inline +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif +#define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ +extern BaseType_t xPortIsInsideInterrupt( void ); + +extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + +extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; +extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + +extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; +extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + +#if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_PAC == 1 ) + + /** + * @brief Generates 128-bit task's random PAC key. + * + * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be + * filled with a 128-bit random number. + */ + void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); + +#endif /* configENABLE_PAC */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ +#if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) +#else + #define portPRIVILEGE_BIT ( 0x0UL ) +#endif /* configENABLE_MPU */ + +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ +#define portPRIVILEGED_FLASH_REGION ( 0UL ) +#define portUNPRIVILEGED_FLASH_REGION ( 1UL ) +#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) +#define portPRIVILEGED_RAM_REGION ( 3UL ) +#define portSTACK_REGION ( 4UL ) +#define portFIRST_CONFIGURABLE_REGION ( 5UL ) +#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) +#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) +#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ +#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ +#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ +#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ +#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ +#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ +#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ +#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) +#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) +#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + +#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) +#define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) +#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) +#define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + +#define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + #ifndef configSYSTEM_CALL_STACK_SIZE + #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. + #endif + + /** + * @brief System call stack. + */ + typedef struct SYSTEM_CALL_STACK_INFO + { + uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; + uint32_t * pulSystemCallStack; + uint32_t * pulSystemCallStackLimit; + uint32_t * pulTaskStack; + uint32_t ulLinkRegisterAtSystemCallEntry; + uint32_t ulStackLimitRegisterAtSystemCallEntry; + } xSYSTEM_CALL_STACK_INFO; + + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + /** + * @brief MPU settings as stored in the TCB. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><-----------><----> + * 16 17 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 71 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 17 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 55 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | | | PC, xPSR | EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><-----------><----> + * 16 17 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 70 + + #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + /* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 17 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 54 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+------------------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +----------+-----------------+------------------------------+------------+-----+ + * + * <---------><----------------><------------------------------><-----------><----> + * 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 38 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+----------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | PC, xPSR | EXC_RETURN | | | + * +----------+-----------------+----------------------+------------+-----+ + * + * <---------><----------------><----------------------><-----------><----> + * 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 37 + + #else /* #if( configENABLE_TRUSTZONE == 1 ) */ + + /* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) + + /* Size of an Access Control List (ACL) entry in bits. */ + #define portACL_ENTRY_SIZE_BITS ( 32U ) + + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + uint32_t ulContext[ MAX_CONTEXT_SIZE ]; + uint32_t ulTaskFlags; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo; + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ]; + #endif + #endif + } xMPU_SETTINGS; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Validate priority of ISRs that are allowed to call FreeRTOS + * system calls. + */ +#if ( configASSERT_DEFINED == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif +#endif + +/** + * @brief SVC numbers. + */ +#define portSVC_ALLOCATE_SECURE_CONTEXT 100 +#define portSVC_FREE_SECURE_CONTEXT 101 +#define portSVC_START_SCHEDULER 102 +#define portSVC_RAISE_PRIVILEGE 103 +#define portSVC_SYSTEM_CALL_EXIT 104 +#define portSVC_YIELD 105 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) +#endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() +#else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + extern BaseType_t xPortIsTaskPrivileged( void ); + +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACROCOMMON_H */ diff --git a/portable/IAR/ARM_CM23/secure/secure_context.c b/portable/IAR/ARM_CM23/secure/secure_context.c new file mode 100644 index 000000000..3aa335e63 --- /dev/null +++ b/portable/IAR/ARM_CM23/secure/secure_context.c @@ -0,0 +1,354 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Secure context includes. */ +#include "secure_context.h" + +/* Secure heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief CONTROL value for privileged tasks. + * + * Bit[0] - 0 --> Thread mode is privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_PRIVILEGED 0x02 + +/** + * @brief CONTROL value for un-privileged tasks. + * + * Bit[0] - 1 --> Thread mode is un-privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03 + +/** + * @brief Size of stack seal values in bytes. + */ +#define securecontextSTACK_SEAL_SIZE 8 + +/** + * @brief Stack seal value as recommended by ARM. + */ +#define securecontextSTACK_SEAL_VALUE 0xFEF5EDA5 + +/** + * @brief Maximum number of secure contexts. + */ +#ifndef secureconfigMAX_SECURE_CONTEXTS + #define secureconfigMAX_SECURE_CONTEXTS 8UL +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Pre-allocated array of secure contexts. + */ +SecureContext_t xSecureContexts[ secureconfigMAX_SECURE_CONTEXTS ]; +/*-----------------------------------------------------------*/ + +/** + * @brief Get a free secure context for a task from the secure context pool (xSecureContexts). + * + * This function ensures that only one secure context is allocated for a task. + * + * @param[in] pvTaskHandle The task handle for which the secure context is allocated. + * + * @return Index of a free secure context in the xSecureContexts array. + */ +static uint32_t ulGetSecureContext( void * pvTaskHandle ); + +/** + * @brief Return the secure context to the secure context pool (xSecureContexts). + * + * @param[in] ulSecureContextIndex Index of the context in the xSecureContexts array. + */ +static void vReturnSecureContext( uint32_t ulSecureContextIndex ); + +/* These are implemented in assembly. */ +extern void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ); +extern void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ); +/*-----------------------------------------------------------*/ + +static uint32_t ulGetSecureContext( void * pvTaskHandle ) +{ + /* Start with invalid index. */ + uint32_t i, ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + if( ( xSecureContexts[ i ].pucCurrentStackPointer == NULL ) && + ( xSecureContexts[ i ].pucStackLimit == NULL ) && + ( xSecureContexts[ i ].pucStackStart == NULL ) && + ( xSecureContexts[ i ].pvTaskHandle == NULL ) && + ( ulSecureContextIndex == secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = i; + } + else if( xSecureContexts[ i ].pvTaskHandle == pvTaskHandle ) + { + /* A task can only have one secure context. Do not allocate a second + * context for the same task. */ + ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + break; + } + } + + return ulSecureContextIndex; +} +/*-----------------------------------------------------------*/ + +static void vReturnSecureContext( uint32_t ulSecureContextIndex ) +{ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackStart = NULL; + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = NULL; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) +{ + uint32_t ulIPSR, i; + static uint32_t ulSecureContextsInitialized = 0; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ( ulIPSR != 0 ) && ( ulSecureContextsInitialized == 0 ) ) + { + /* Ensure to initialize secure contexts only once. */ + ulSecureContextsInitialized = 1; + + /* No stack for thread mode until a task's context is loaded. */ + secureportSET_PSPLIM( securecontextNO_STACK ); + secureportSET_PSP( securecontextNO_STACK ); + + /* Initialize all secure contexts. */ + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + xSecureContexts[ i ].pucCurrentStackPointer = NULL; + xSecureContexts[ i ].pucStackLimit = NULL; + xSecureContexts[ i ].pucStackStart = NULL; + xSecureContexts[ i ].pvTaskHandle = NULL; + } + + #if ( configENABLE_MPU == 1 ) + { + /* Configure thread mode to use PSP and to be unprivileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); + } + #else /* configENABLE_MPU */ + { + /* Configure thread mode to use PSP and to be privileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); + } + #endif /* configENABLE_MPU */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ) +#else /* configENABLE_MPU */ + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ) +#endif /* configENABLE_MPU */ +{ + uint8_t * pucStackMemory = NULL; + uint8_t * pucStackLimit; + uint32_t ulIPSR, ulSecureContextIndex; + SecureContextHandle_t xSecureContextHandle = securecontextINVALID_CONTEXT_ID; + + #if ( configENABLE_MPU == 1 ) + uint32_t * pulCurrentStackPointer = NULL; + #endif /* configENABLE_MPU */ + + /* Read the Interrupt Program Status Register (IPSR) and Process Stack Limit + * Register (PSPLIM) value. */ + secureportREAD_IPSR( ulIPSR ); + secureportREAD_PSPLIM( pucStackLimit ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. + * Also do nothing, if a secure context us already loaded. PSPLIM is set to + * securecontextNO_STACK when no secure context is loaded. */ + if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) ) + { + /* Obtain a free secure context. */ + ulSecureContextIndex = ulGetSecureContext( pvTaskHandle ); + + /* Were we able to get a free context? */ + if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS ) + { + /* Allocate the stack space. */ + pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + + if( pucStackMemory != NULL ) + { + /* Since stack grows down, the starting point will be the last + * location. Note that this location is next to the last + * allocated byte for stack (excluding the space for seal values) + * because the hardware decrements the stack pointer before + * writing i.e. if stack pointer is 0x2, a push operation will + * decrement the stack pointer to 0x1 and then write at 0x1. */ + xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize; + + /* Seal the created secure process stack. */ + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; + + /* The stack cannot go beyond this location. This value is + * programmed in the PSPLIM register on context switch.*/ + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = pucStackMemory; + + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle; + + #if ( configENABLE_MPU == 1 ) + { + /* Store the correct CONTROL value for the task on the stack. + * This value is programmed in the CONTROL register on + * context switch. */ + pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; + pulCurrentStackPointer--; + + if( ulIsTaskPrivileged ) + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; + } + else + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; + } + + /* Store the current stack pointer. This value is programmed in + * the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + } + #else /* configENABLE_MPU */ + { + /* Current SP is set to the starting of the stack. This + * value programmed in the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + } + #endif /* configENABLE_MPU */ + + /* Ensure to never return 0 as a valid context handle. */ + xSecureContextHandle = ulSecureContextIndex + 1UL; + } + } + } + + return xSecureContextHandle; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) +{ + uint32_t ulIPSR, ulSecureContextIndex; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* Only free if a valid context handle is passed. */ + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + /* Ensure that the secure context being deleted is associated with + * the task. */ + if( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) + { + /* Free the stack space. */ + vPortFree( xSecureContexts[ ulSecureContextIndex ].pucStackLimit ); + + /* Return the secure context back to the free secure contexts pool. */ + vReturnSecureContext( ulSecureContextIndex ); + } + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that no secure context is loaded and the task is loading it's + * own context. */ + if( ( pucStackLimit == securecontextNO_STACK ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_LoadContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that task's context is loaded and the task is saving it's own + * context. */ + if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_SaveContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/ARM_CM23/secure/secure_context.h b/portable/IAR/ARM_CM23/secure/secure_context.h new file mode 100644 index 000000000..e36a8e430 --- /dev/null +++ b/portable/IAR/ARM_CM23/secure/secure_context.h @@ -0,0 +1,138 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_CONTEXT_H__ +#define __SECURE_CONTEXT_H__ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" + +/** + * @brief PSP value when no secure context is loaded. + */ +#define securecontextNO_STACK 0x0 + +/** + * @brief Invalid context ID. + */ +#define securecontextINVALID_CONTEXT_ID 0UL +/*-----------------------------------------------------------*/ + +/** + * @brief Structure to represent a secure context. + * + * @note Since stack grows down, pucStackStart is the highest address while + * pucStackLimit is the first address of the allocated memory. + */ +typedef struct SecureContext +{ + uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */ + uint8_t * pucStackLimit; /**< Last location of the stack memory (PSPLIM). */ + uint8_t * pucStackStart; /**< First location of the stack memory. */ + void * pvTaskHandle; /**< Task handle of the task this context is associated with. */ +} SecureContext_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Opaque handle for a secure context. + */ +typedef uint32_t SecureContextHandle_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Initializes the secure context management system. + * + * PSP is set to NULL and therefore a task must allocate and load a context + * before calling any secure side function in the thread mode. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureContext_Init( void ); + +/** + * @brief Allocates a context on the secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] ulSecureStackSize Size of the stack to allocate on secure side. + * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise. + * + * @return Opaque context handle if context is successfully allocated, NULL + * otherwise. + */ +#if ( configENABLE_MPU == 1 ) + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ); +#else /* configENABLE_MPU */ + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ); +#endif /* configENABLE_MPU */ + +/** + * @brief Frees the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the + * context to be freed. + */ +void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); + +/** + * @brief Loads the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be loaded. + */ +void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); + +/** + * @brief Saves the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be saved. + */ +void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); + +#endif /* __SECURE_CONTEXT_H__ */ diff --git a/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s b/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s new file mode 100644 index 000000000..f70e89115 --- /dev/null +++ b/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s @@ -0,0 +1,88 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + SECTION .text:CODE:NOROOT(2) + THUMB + +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" + + PUBLIC SecureContext_LoadContextAsm + PUBLIC SecureContext_SaveContextAsm + +#if ( configENABLE_FPU == 1 ) + #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0. +#endif +/*-----------------------------------------------------------*/ + +SecureContext_LoadContextAsm: + /* pxSecureContext value is in r0. */ + mrs r1, ipsr /* r1 = IPSR. */ + cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */ + ldmia r0!, {r1, r2} /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */ + +#if ( configENABLE_MPU == 1 ) + ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL. */ + msr control, r3 /* CONTROL = r3. */ +#endif /* configENABLE_MPU */ + + msr psplim, r2 /* PSPLIM = r2. */ + msr psp, r1 /* PSP = r1. */ + + load_ctx_therad_mode: + bx lr +/*-----------------------------------------------------------*/ + +SecureContext_SaveContextAsm: + /* pxSecureContext value is in r0. */ + mrs r1, ipsr /* r1 = IPSR. */ + cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */ + mrs r1, psp /* r1 = PSP. */ + +#if ( configENABLE_MPU == 1 ) + mrs r2, control /* r2 = CONTROL. */ + subs r1, r1, #4 /* Make space for the CONTROL value on the stack. */ + str r1, [r0] /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */ + stmia r1!, {r2} /* Store CONTROL value on the stack. */ +#else /* configENABLE_MPU */ + str r1, [r0] /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */ +#endif /* configENABLE_MPU */ + + movs r1, #0 /* r1 = securecontextNO_STACK. */ + msr psplim, r1 /* PSPLIM = securecontextNO_STACK. */ + msr psp, r1 /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */ + + save_ctx_therad_mode: + bx lr +/*-----------------------------------------------------------*/ + + END diff --git a/portable/IAR/ARM_CM23/secure/secure_heap.c b/portable/IAR/ARM_CM23/secure/secure_heap.c new file mode 100644 index 000000000..896b53e2d --- /dev/null +++ b/portable/IAR/ARM_CM23/secure/secure_heap.c @@ -0,0 +1,485 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Configuration includes. */ +#include "FreeRTOSConfig.h" + +/* Secure context heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Total heap size. + */ +#ifndef secureconfigTOTAL_HEAP_SIZE + #define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) ) +#endif + +/* No test marker by default. */ +#ifndef mtCOVERAGE_TEST_MARKER + #define mtCOVERAGE_TEST_MARKER() +#endif + +/* No tracing by default. */ +#ifndef traceMALLOC + #define traceMALLOC( pvReturn, xWantedSize ) +#endif + +/* No tracing by default. */ +#ifndef traceFREE + #define traceFREE( pv, xBlockSize ) +#endif + +/* Block sizes must not get too small. */ +#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) ) + +/* Assumes 8bit bytes! */ +#define secureheapBITS_PER_BYTE ( ( size_t ) 8 ) + +/* Max value that fits in a size_t type. */ +#define secureheapSIZE_MAX ( ~( ( size_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define secureheapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) ) + +/* MSB of the xBlockSize member of an BlockLink_t structure is used to track + * the allocation status of a block. When MSB of the xBlockSize member of + * an BlockLink_t structure is set then the block belongs to the application. + * When the bit is free the block is still part of the free heap space. */ +#define secureheapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) ) +#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 ) +#define secureheapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 ) +#define secureheapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK ) +#define secureheapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK ) +/*-----------------------------------------------------------*/ + +/* Allocate the memory for the heap. */ +#if ( configAPPLICATION_ALLOCATED_HEAP == 1 ) + +/* The application writer has already defined the array used for the RTOS +* heap - probably so it can be placed in a special segment or address. */ + extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#else /* configAPPLICATION_ALLOCATED_HEAP */ + static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#endif /* configAPPLICATION_ALLOCATED_HEAP */ + +/** + * @brief The linked list structure. + * + * This is used to link free blocks in order of their memory address. + */ +typedef struct A_BLOCK_LINK +{ + struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */ + size_t xBlockSize; /**< The size of the free block. */ +} BlockLink_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Called automatically to setup the required heap structures the first + * time pvPortMalloc() is called. + */ +static void prvHeapInit( void ); + +/** + * @brief Inserts a block of memory that is being freed into the correct + * position in the list of free memory blocks. + * + * The block being freed will be merged with the block in front it and/or the + * block behind it if the memory blocks are adjacent to each other. + * + * @param[in] pxBlockToInsert The block being freed. + */ +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ); +/*-----------------------------------------------------------*/ + +/** + * @brief The size of the structure placed at the beginning of each allocated + * memory block must by correctly byte aligned. + */ +static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + +/** + * @brief Create a couple of list links to mark the start and end of the list. + */ +static BlockLink_t xStart; +static BlockLink_t * pxEnd = NULL; + +/** + * @brief Keeps track of the number of free bytes remaining, but says nothing + * about fragmentation. + */ +static size_t xFreeBytesRemaining = 0U; +static size_t xMinimumEverFreeBytesRemaining = 0U; + +/*-----------------------------------------------------------*/ + +static void prvHeapInit( void ) +{ + BlockLink_t * pxFirstFreeBlock; + uint8_t * pucAlignedHeap; + size_t uxAddress; + size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE; + + /* Ensure the heap starts on a correctly aligned boundary. */ + uxAddress = ( size_t ) ucHeap; + + if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 ) + { + uxAddress += ( secureportBYTE_ALIGNMENT - 1 ); + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; + } + + pucAlignedHeap = ( uint8_t * ) uxAddress; + + /* xStart is used to hold a pointer to the first item in the list of free + * blocks. The void cast is used to prevent compiler warnings. */ + xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; + xStart.xBlockSize = ( size_t ) 0; + + /* pxEnd is used to mark the end of the list of free blocks and is inserted + * at the end of the heap space. */ + uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; + uxAddress -= xHeapStructSize; + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + pxEnd = ( void * ) uxAddress; + pxEnd->xBlockSize = 0; + pxEnd->pxNextFreeBlock = NULL; + + /* To start with there is a single free block that is sized to take up the + * entire heap space, minus the space taken by pxEnd. */ + pxFirstFreeBlock = ( void * ) pucAlignedHeap; + pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; + pxFirstFreeBlock->pxNextFreeBlock = pxEnd; + + /* Only one block exists - and it covers the entire usable heap space. */ + xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; +} +/*-----------------------------------------------------------*/ + +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) +{ + BlockLink_t * pxIterator; + uint8_t * puc; + + /* Iterate through the list until a block is found that has a higher address + * than the block being inserted. */ + for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) + { + /* Nothing to do here, just iterate to the right position. */ + } + + /* Do the block being inserted, and the block it is being inserted after + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxIterator; + + if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) + { + pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; + pxBlockToInsert = pxIterator; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Do the block being inserted, and the block it is being inserted before + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxBlockToInsert; + + if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) + { + if( pxIterator->pxNextFreeBlock != pxEnd ) + { + /* Form one big block from the two blocks. */ + pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxEnd; + } + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; + } + + /* If the block being inserted plugged a gap, so was merged with the block + * before and the block after, then it's pxNextFreeBlock pointer will have + * already been set, and should not be set here as that would make it point + * to itself. */ + if( pxIterator != pxBlockToInsert ) + { + pxIterator->pxNextFreeBlock = pxBlockToInsert; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} +/*-----------------------------------------------------------*/ + +void * pvPortMalloc( size_t xWantedSize ) +{ + BlockLink_t * pxBlock; + BlockLink_t * pxPreviousBlock; + BlockLink_t * pxNewBlockLink; + void * pvReturn = NULL; + size_t xAdditionalRequiredSize; + size_t xAllocatedBlockSize = 0; + + /* If this is the first call to malloc then the heap will require + * initialisation to setup the list of free blocks. */ + if( pxEnd == NULL ) + { + prvHeapInit(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xWantedSize > 0 ) + { + /* The wanted size must be increased so it can contain a BlockLink_t + * structure in addition to the requested amount of bytes. */ + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 ) + { + xWantedSize += xHeapStructSize; + + /* Ensure that blocks are always aligned to the required number + * of bytes. */ + if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 ) + { + /* Byte alignment required. */ + xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ); + + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 ) + { + xWantedSize += xAdditionalRequiredSize; + } + else + { + xWantedSize = 0; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + xWantedSize = 0; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Check the requested block size is not so large that the top bit is set. + * The top bit of the block size member of the BlockLink_t structure is used + * to determine who owns the block - the application or the kernel, so it + * must be free. */ + if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 ) + { + if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) + { + /* Traverse the list from the start (lowest address) block until + * one of adequate size is found. */ + pxPreviousBlock = &xStart; + pxBlock = xStart.pxNextFreeBlock; + + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + { + pxPreviousBlock = pxBlock; + pxBlock = pxBlock->pxNextFreeBlock; + } + + /* If the end marker was reached then a block of adequate size was + * not found. */ + if( pxBlock != pxEnd ) + { + /* Return the memory space pointed to - jumping over the + * BlockLink_t structure at its start. */ + pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); + + /* This block is being returned for use so must be taken out + * of the list of free blocks. */ + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + + /* If the block is larger than required it can be split into + * two. */ + if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE ) + { + /* This block is to be split into two. Create a new + * block following the number of bytes requested. The void + * cast is used to prevent byte alignment warnings from the + * compiler. */ + pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); + secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + + /* Calculate the sizes of two blocks split from the single + * block. */ + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + pxBlock->xBlockSize = xWantedSize; + + /* Insert the new block into the list of free blocks. */ + pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock; + pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xFreeBytesRemaining -= pxBlock->xBlockSize; + + if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) + { + xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xAllocatedBlockSize = pxBlock->xBlockSize; + + /* The block is being returned - it is allocated and owned by + * the application and has no "next" block. */ + secureheapALLOCATE_BLOCK( pxBlock ); + pxBlock->pxNextFreeBlock = NULL; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceMALLOC( pvReturn, xAllocatedBlockSize ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xAllocatedBlockSize; + + #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) + { + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */ + + secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 ); + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void * pv ) +{ + uint8_t * puc = ( uint8_t * ) pv; + BlockLink_t * pxLink; + + if( pv != NULL ) + { + /* The memory being freed will have an BlockLink_t structure immediately + * before it. */ + puc -= xHeapStructSize; + + /* This casting is to keep the compiler from issuing warnings. */ + pxLink = ( void * ) puc; + + /* Check the block is actually allocated. */ + secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ); + secureportASSERT( pxLink->pxNextFreeBlock == NULL ); + + if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ) + { + if( pxLink->pxNextFreeBlock == NULL ) + { + /* The block is being returned to the heap - it is no longer + * allocated. */ + secureheapFREE_BLOCK( pxLink ); + + secureportDISABLE_NON_SECURE_INTERRUPTS(); + { + /* Add this block to the list of free blocks. */ + xFreeBytesRemaining += pxLink->xBlockSize; + traceFREE( pv, pxLink->xBlockSize ); + prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); + } + secureportENABLE_NON_SECURE_INTERRUPTS(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } +} +/*-----------------------------------------------------------*/ + +size_t xPortGetFreeHeapSize( void ) +{ + return xFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +size_t xPortGetMinimumEverFreeHeapSize( void ) +{ + return xMinimumEverFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/ARM_CM23/secure/secure_heap.h b/portable/IAR/ARM_CM23/secure/secure_heap.h new file mode 100644 index 000000000..0e84a9d9d --- /dev/null +++ b/portable/IAR/ARM_CM23/secure/secure_heap.h @@ -0,0 +1,66 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_HEAP_H__ +#define __SECURE_HEAP_H__ + +/* Standard includes. */ +#include + +/** + * @brief Allocates memory from heap. + * + * @param[in] xWantedSize The size of the memory to be allocated. + * + * @return Pointer to the memory region if the allocation is successful, NULL + * otherwise. + */ +void * pvPortMalloc( size_t xWantedSize ); + +/** + * @brief Frees the previously allocated memory. + * + * @param[in] pv Pointer to the memory to be freed. + */ +void vPortFree( void * pv ); + +/** + * @brief Get the free heap size. + * + * @return Free heap size. + */ +size_t xPortGetFreeHeapSize( void ); + +/** + * @brief Get the minimum ever free heap size. + * + * @return Minimum ever free heap size. + */ +size_t xPortGetMinimumEverFreeHeapSize( void ); + +#endif /* __SECURE_HEAP_H__ */ diff --git a/portable/IAR/ARM_CM23/secure/secure_init.c b/portable/IAR/ARM_CM23/secure/secure_init.c new file mode 100644 index 000000000..c50d37668 --- /dev/null +++ b/portable/IAR/ARM_CM23/secure/secure_init.c @@ -0,0 +1,106 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Secure init includes. */ +#include "secure_init.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Constants required to manipulate the SCB. + */ +#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */ +#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL ) +#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS ) +#define secureinitSCB_AIRCR_PRIS_POS ( 14UL ) +#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS ) + +/** + * @brief Constants required to manipulate the FPU. + */ +#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define secureinitFPCCR_LSPENS_POS ( 29UL ) +#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS ) +#define secureinitFPCCR_TS_POS ( 26UL ) +#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS ) + +#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */ +#define secureinitNSACR_CP10_POS ( 10UL ) +#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS ) +#define secureinitNSACR_CP11_POS ( 11UL ) +#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS ) +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) | + ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) | + ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK ); + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is + * permitted. CP11 should be programmed to the same value as CP10. */ + *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK ); + + /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures + * that we can enable/disable lazy stacking in port.c file. */ + *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK ); + + /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP + * registers (S16-S31) are also pushed to stack on exception entry and + * restored on exception return. */ + *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK ); + } +} +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/ARM_CM23/secure/secure_init.h b/portable/IAR/ARM_CM23/secure/secure_init.h new file mode 100644 index 000000000..ebe04900f --- /dev/null +++ b/portable/IAR/ARM_CM23/secure/secure_init.h @@ -0,0 +1,54 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_INIT_H__ +#define __SECURE_INIT_H__ + +/** + * @brief De-prioritizes the non-secure exceptions. + * + * This is needed to ensure that the non-secure PendSV runs at the lowest + * priority. Context switch is done in the non-secure PendSV handler. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_DePrioritizeNSExceptions( void ); + +/** + * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access. + * + * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point + * Registers are not leaked to the non-secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_EnableNSFPUAccess( void ); + +#endif /* __SECURE_INIT_H__ */ diff --git a/portable/IAR/ARM_CM23/secure/secure_port_macros.h b/portable/IAR/ARM_CM23/secure/secure_port_macros.h new file mode 100644 index 000000000..a70da2c65 --- /dev/null +++ b/portable/IAR/ARM_CM23/secure/secure_port_macros.h @@ -0,0 +1,140 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_PORT_MACROS_H__ +#define __SECURE_PORT_MACROS_H__ + +/** + * @brief Byte alignment requirements. + */ +#define secureportBYTE_ALIGNMENT 8 +#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 ) + +/** + * @brief Macro to declare a function as non-secure callable. + */ +#if defined( __IAR_SYSTEMS_ICC__ ) + #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry __root +#else + #define secureportNON_SECURE_CALLABLE __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) ) +#endif + +/** + * @brief Set the secure PRIMASK value. + */ +#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Set the non-secure PRIMASK value. + */ +#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Read the PSP value in the given variable. + */ +#define secureportREAD_PSP( pucOutCurrentStackPointer ) \ + __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) ) + +/** + * @brief Set the PSP to the given value. + */ +#define secureportSET_PSP( pucCurrentStackPointer ) \ + __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) ) + +/** + * @brief Read the PSPLIM value in the given variable. + */ +#define secureportREAD_PSPLIM( pucOutStackLimit ) \ + __asm volatile ( "mrs %0, psplim" : "=r" ( pucOutStackLimit ) ) + +/** + * @brief Set the PSPLIM to the given value. + */ +#define secureportSET_PSPLIM( pucStackLimit ) \ + __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) ) + +/** + * @brief Set the NonSecure MSP to the given value. + */ +#define secureportSET_MSP_NS( pucMainStackPointer ) \ + __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) ) + +/** + * @brief Set the CONTROL register to the given value. + */ +#define secureportSET_CONTROL( ulControl ) \ + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" ) + +/** + * @brief Read the Interrupt Program Status Register (IPSR) value in the given + * variable. + */ +#define secureportREAD_IPSR( ulIPSR ) \ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) ) + +/** + * @brief PRIMASK value to enable interrupts. + */ +#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0 + +/** + * @brief PRIMASK value to disable interrupts. + */ +#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1 + +/** + * @brief Disable secure interrupts. + */ +#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Disable non-secure interrupts. + * + * This effectively disables context switches. + */ +#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Enable non-secure interrupts. + */ +#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL ) + +/** + * @brief Assert definition. + */ +#define secureportASSERT( x ) \ + if( ( x ) == 0 ) \ + { \ + secureportDISABLE_SECURE_INTERRUPTS(); \ + secureportDISABLE_NON_SECURE_INTERRUPTS(); \ + for( ; ; ) {; } \ + } + +#endif /* __SECURE_PORT_MACROS_H__ */ diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.S new file mode 100644 index 000000000..9289bcbc2 --- /dev/null +++ b/portable/IAR/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.S @@ -0,0 +1,1312 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + + SECTION freertos_system_calls:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +#include "FreeRTOSConfig.h" +#include "mpu_syscall_numbers.h" + +#ifndef configUSE_MPU_WRAPPERS_V1 + #define configUSE_MPU_WRAPPERS_V1 0 +#endif + +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + PUBLIC MPU_xTaskDelayUntil +MPU_xTaskDelayUntil: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTaskDelayUntil_Unpriv + MPU_xTaskDelayUntil_Priv: + b MPU_xTaskDelayUntilImpl + MPU_xTaskDelayUntil_Unpriv: + svc #SYSTEM_CALL_xTaskDelayUntil +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskAbortDelay +MPU_xTaskAbortDelay: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTaskAbortDelay_Unpriv + MPU_xTaskAbortDelay_Priv: + b MPU_xTaskAbortDelayImpl + MPU_xTaskAbortDelay_Unpriv: + svc #SYSTEM_CALL_xTaskAbortDelay +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskDelay +MPU_vTaskDelay: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vTaskDelay_Unpriv + MPU_vTaskDelay_Priv: + b MPU_vTaskDelayImpl + MPU_vTaskDelay_Unpriv: + svc #SYSTEM_CALL_vTaskDelay +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskPriorityGet +MPU_uxTaskPriorityGet: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_uxTaskPriorityGet_Unpriv + MPU_uxTaskPriorityGet_Priv: + b MPU_uxTaskPriorityGetImpl + MPU_uxTaskPriorityGet_Unpriv: + svc #SYSTEM_CALL_uxTaskPriorityGet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_eTaskGetState +MPU_eTaskGetState: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_eTaskGetState_Unpriv + MPU_eTaskGetState_Priv: + b MPU_eTaskGetStateImpl + MPU_eTaskGetState_Unpriv: + svc #SYSTEM_CALL_eTaskGetState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskGetInfo +MPU_vTaskGetInfo: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vTaskGetInfo_Unpriv + MPU_vTaskGetInfo_Priv: + b MPU_vTaskGetInfoImpl + MPU_vTaskGetInfo_Unpriv: + svc #SYSTEM_CALL_vTaskGetInfo +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetIdleTaskHandle +MPU_xTaskGetIdleTaskHandle: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTaskGetIdleTaskHandle_Unpriv + MPU_xTaskGetIdleTaskHandle_Priv: + b MPU_xTaskGetIdleTaskHandleImpl + MPU_xTaskGetIdleTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTaskGetIdleTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSuspend +MPU_vTaskSuspend: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vTaskSuspend_Unpriv + MPU_vTaskSuspend_Priv: + b MPU_vTaskSuspendImpl + MPU_vTaskSuspend_Unpriv: + svc #SYSTEM_CALL_vTaskSuspend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskResume +MPU_vTaskResume: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vTaskResume_Unpriv + MPU_vTaskResume_Priv: + b MPU_vTaskResumeImpl + MPU_vTaskResume_Unpriv: + svc #SYSTEM_CALL_vTaskResume +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetTickCount +MPU_xTaskGetTickCount: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTaskGetTickCount_Unpriv + MPU_xTaskGetTickCount_Priv: + b MPU_xTaskGetTickCountImpl + MPU_xTaskGetTickCount_Unpriv: + svc #SYSTEM_CALL_xTaskGetTickCount +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetNumberOfTasks +MPU_uxTaskGetNumberOfTasks: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_uxTaskGetNumberOfTasks_Unpriv + MPU_uxTaskGetNumberOfTasks_Priv: + b MPU_uxTaskGetNumberOfTasksImpl + MPU_uxTaskGetNumberOfTasks_Unpriv: + svc #SYSTEM_CALL_uxTaskGetNumberOfTasks +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetRunTimeCounter +MPU_ulTaskGetRunTimeCounter: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_ulTaskGetRunTimeCounter_Unpriv + MPU_ulTaskGetRunTimeCounter_Priv: + b MPU_ulTaskGetRunTimeCounterImpl + MPU_ulTaskGetRunTimeCounter_Unpriv: + svc #SYSTEM_CALL_ulTaskGetRunTimeCounter +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetRunTimePercent +MPU_ulTaskGetRunTimePercent: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_ulTaskGetRunTimePercent_Unpriv + MPU_ulTaskGetRunTimePercent_Priv: + b MPU_ulTaskGetRunTimePercentImpl + MPU_ulTaskGetRunTimePercent_Unpriv: + svc #SYSTEM_CALL_ulTaskGetRunTimePercent +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetIdleRunTimePercent +MPU_ulTaskGetIdleRunTimePercent: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_ulTaskGetIdleRunTimePercent_Unpriv + MPU_ulTaskGetIdleRunTimePercent_Priv: + b MPU_ulTaskGetIdleRunTimePercentImpl + MPU_ulTaskGetIdleRunTimePercent_Unpriv: + svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetIdleRunTimeCounter +MPU_ulTaskGetIdleRunTimeCounter: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv + MPU_ulTaskGetIdleRunTimeCounter_Priv: + b MPU_ulTaskGetIdleRunTimeCounterImpl + MPU_ulTaskGetIdleRunTimeCounter_Unpriv: + svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetApplicationTaskTag +MPU_vTaskSetApplicationTaskTag: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vTaskSetApplicationTaskTag_Unpriv + MPU_vTaskSetApplicationTaskTag_Priv: + b MPU_vTaskSetApplicationTaskTagImpl + MPU_vTaskSetApplicationTaskTag_Unpriv: + svc #SYSTEM_CALL_vTaskSetApplicationTaskTag +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetApplicationTaskTag +MPU_xTaskGetApplicationTaskTag: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTaskGetApplicationTaskTag_Unpriv + MPU_xTaskGetApplicationTaskTag_Priv: + b MPU_xTaskGetApplicationTaskTagImpl + MPU_xTaskGetApplicationTaskTag_Unpriv: + svc #SYSTEM_CALL_xTaskGetApplicationTaskTag +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetThreadLocalStoragePointer +MPU_vTaskSetThreadLocalStoragePointer: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv + MPU_vTaskSetThreadLocalStoragePointer_Priv: + b MPU_vTaskSetThreadLocalStoragePointerImpl + MPU_vTaskSetThreadLocalStoragePointer_Unpriv: + svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pvTaskGetThreadLocalStoragePointer +MPU_pvTaskGetThreadLocalStoragePointer: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv + MPU_pvTaskGetThreadLocalStoragePointer_Priv: + b MPU_pvTaskGetThreadLocalStoragePointerImpl + MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: + svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetSystemState +MPU_uxTaskGetSystemState: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_uxTaskGetSystemState_Unpriv + MPU_uxTaskGetSystemState_Priv: + b MPU_uxTaskGetSystemStateImpl + MPU_uxTaskGetSystemState_Unpriv: + svc #SYSTEM_CALL_uxTaskGetSystemState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetStackHighWaterMark +MPU_uxTaskGetStackHighWaterMark: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_uxTaskGetStackHighWaterMark_Unpriv + MPU_uxTaskGetStackHighWaterMark_Priv: + b MPU_uxTaskGetStackHighWaterMarkImpl + MPU_uxTaskGetStackHighWaterMark_Unpriv: + svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetStackHighWaterMark2 +MPU_uxTaskGetStackHighWaterMark2: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_uxTaskGetStackHighWaterMark2_Unpriv + MPU_uxTaskGetStackHighWaterMark2_Priv: + b MPU_uxTaskGetStackHighWaterMark2Impl + MPU_uxTaskGetStackHighWaterMark2_Unpriv: + svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2 +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetCurrentTaskHandle +MPU_xTaskGetCurrentTaskHandle: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTaskGetCurrentTaskHandle_Unpriv + MPU_xTaskGetCurrentTaskHandle_Priv: + b MPU_xTaskGetCurrentTaskHandleImpl + MPU_xTaskGetCurrentTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetSchedulerState +MPU_xTaskGetSchedulerState: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTaskGetSchedulerState_Unpriv + MPU_xTaskGetSchedulerState_Priv: + b MPU_xTaskGetSchedulerStateImpl + MPU_xTaskGetSchedulerState_Unpriv: + svc #SYSTEM_CALL_xTaskGetSchedulerState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetTimeOutState +MPU_vTaskSetTimeOutState: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vTaskSetTimeOutState_Unpriv + MPU_vTaskSetTimeOutState_Priv: + b MPU_vTaskSetTimeOutStateImpl + MPU_vTaskSetTimeOutState_Unpriv: + svc #SYSTEM_CALL_vTaskSetTimeOutState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskCheckForTimeOut +MPU_xTaskCheckForTimeOut: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTaskCheckForTimeOut_Unpriv + MPU_xTaskCheckForTimeOut_Priv: + b MPU_xTaskCheckForTimeOutImpl + MPU_xTaskCheckForTimeOut_Unpriv: + svc #SYSTEM_CALL_xTaskCheckForTimeOut +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyEntry +MPU_xTaskGenericNotifyEntry: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTaskGenericNotify_Unpriv + MPU_xTaskGenericNotify_Priv: + b MPU_xTaskGenericNotifyImpl + MPU_xTaskGenericNotify_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotify +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyWaitEntry +MPU_xTaskGenericNotifyWaitEntry: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTaskGenericNotifyWait_Unpriv + MPU_xTaskGenericNotifyWait_Priv: + b MPU_xTaskGenericNotifyWaitImpl + MPU_xTaskGenericNotifyWait_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotifyWait +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGenericNotifyTake +MPU_ulTaskGenericNotifyTake: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_ulTaskGenericNotifyTake_Unpriv + MPU_ulTaskGenericNotifyTake_Priv: + b MPU_ulTaskGenericNotifyTakeImpl + MPU_ulTaskGenericNotifyTake_Unpriv: + svc #SYSTEM_CALL_ulTaskGenericNotifyTake +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyStateClear +MPU_xTaskGenericNotifyStateClear: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTaskGenericNotifyStateClear_Unpriv + MPU_xTaskGenericNotifyStateClear_Priv: + b MPU_xTaskGenericNotifyStateClearImpl + MPU_xTaskGenericNotifyStateClear_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotifyStateClear +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGenericNotifyValueClear +MPU_ulTaskGenericNotifyValueClear: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_ulTaskGenericNotifyValueClear_Unpriv + MPU_ulTaskGenericNotifyValueClear_Priv: + b MPU_ulTaskGenericNotifyValueClearImpl + MPU_ulTaskGenericNotifyValueClear_Unpriv: + svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGenericSend +MPU_xQueueGenericSend: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xQueueGenericSend_Unpriv + MPU_xQueueGenericSend_Priv: + b MPU_xQueueGenericSendImpl + MPU_xQueueGenericSend_Unpriv: + svc #SYSTEM_CALL_xQueueGenericSend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxQueueMessagesWaiting +MPU_uxQueueMessagesWaiting: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_uxQueueMessagesWaiting_Unpriv + MPU_uxQueueMessagesWaiting_Priv: + b MPU_uxQueueMessagesWaitingImpl + MPU_uxQueueMessagesWaiting_Unpriv: + svc #SYSTEM_CALL_uxQueueMessagesWaiting +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxQueueSpacesAvailable +MPU_uxQueueSpacesAvailable: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_uxQueueSpacesAvailable_Unpriv + MPU_uxQueueSpacesAvailable_Priv: + b MPU_uxQueueSpacesAvailableImpl + MPU_uxQueueSpacesAvailable_Unpriv: + svc #SYSTEM_CALL_uxQueueSpacesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueReceive +MPU_xQueueReceive: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xQueueReceive_Unpriv + MPU_xQueueReceive_Priv: + b MPU_xQueueReceiveImpl + MPU_xQueueReceive_Unpriv: + svc #SYSTEM_CALL_xQueueReceive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueuePeek +MPU_xQueuePeek: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xQueuePeek_Unpriv + MPU_xQueuePeek_Priv: + b MPU_xQueuePeekImpl + MPU_xQueuePeek_Unpriv: + svc #SYSTEM_CALL_xQueuePeek +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueSemaphoreTake +MPU_xQueueSemaphoreTake: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xQueueSemaphoreTake_Unpriv + MPU_xQueueSemaphoreTake_Priv: + b MPU_xQueueSemaphoreTakeImpl + MPU_xQueueSemaphoreTake_Unpriv: + svc #SYSTEM_CALL_xQueueSemaphoreTake +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGetMutexHolder +MPU_xQueueGetMutexHolder: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xQueueGetMutexHolder_Unpriv + MPU_xQueueGetMutexHolder_Priv: + b MPU_xQueueGetMutexHolderImpl + MPU_xQueueGetMutexHolder_Unpriv: + svc #SYSTEM_CALL_xQueueGetMutexHolder +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueTakeMutexRecursive +MPU_xQueueTakeMutexRecursive: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xQueueTakeMutexRecursive_Unpriv + MPU_xQueueTakeMutexRecursive_Priv: + b MPU_xQueueTakeMutexRecursiveImpl + MPU_xQueueTakeMutexRecursive_Unpriv: + svc #SYSTEM_CALL_xQueueTakeMutexRecursive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGiveMutexRecursive +MPU_xQueueGiveMutexRecursive: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xQueueGiveMutexRecursive_Unpriv + MPU_xQueueGiveMutexRecursive_Priv: + b MPU_xQueueGiveMutexRecursiveImpl + MPU_xQueueGiveMutexRecursive_Unpriv: + svc #SYSTEM_CALL_xQueueGiveMutexRecursive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueSelectFromSet +MPU_xQueueSelectFromSet: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xQueueSelectFromSet_Unpriv + MPU_xQueueSelectFromSet_Priv: + b MPU_xQueueSelectFromSetImpl + MPU_xQueueSelectFromSet_Unpriv: + svc #SYSTEM_CALL_xQueueSelectFromSet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueAddToSet +MPU_xQueueAddToSet: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xQueueAddToSet_Unpriv + MPU_xQueueAddToSet_Priv: + b MPU_xQueueAddToSetImpl + MPU_xQueueAddToSet_Unpriv: + svc #SYSTEM_CALL_xQueueAddToSet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vQueueAddToRegistry +MPU_vQueueAddToRegistry: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vQueueAddToRegistry_Unpriv + MPU_vQueueAddToRegistry_Priv: + b MPU_vQueueAddToRegistryImpl + MPU_vQueueAddToRegistry_Unpriv: + svc #SYSTEM_CALL_vQueueAddToRegistry +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vQueueUnregisterQueue +MPU_vQueueUnregisterQueue: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vQueueUnregisterQueue_Unpriv + MPU_vQueueUnregisterQueue_Priv: + b MPU_vQueueUnregisterQueueImpl + MPU_vQueueUnregisterQueue_Unpriv: + svc #SYSTEM_CALL_vQueueUnregisterQueue +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pcQueueGetName +MPU_pcQueueGetName: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_pcQueueGetName_Unpriv + MPU_pcQueueGetName_Priv: + b MPU_pcQueueGetNameImpl + MPU_pcQueueGetName_Unpriv: + svc #SYSTEM_CALL_pcQueueGetName +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pvTimerGetTimerID +MPU_pvTimerGetTimerID: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_pvTimerGetTimerID_Unpriv + MPU_pvTimerGetTimerID_Priv: + b MPU_pvTimerGetTimerIDImpl + MPU_pvTimerGetTimerID_Unpriv: + svc #SYSTEM_CALL_pvTimerGetTimerID +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTimerSetTimerID +MPU_vTimerSetTimerID: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vTimerSetTimerID_Unpriv + MPU_vTimerSetTimerID_Priv: + b MPU_vTimerSetTimerIDImpl + MPU_vTimerSetTimerID_Unpriv: + svc #SYSTEM_CALL_vTimerSetTimerID +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerIsTimerActive +MPU_xTimerIsTimerActive: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTimerIsTimerActive_Unpriv + MPU_xTimerIsTimerActive_Priv: + b MPU_xTimerIsTimerActiveImpl + MPU_xTimerIsTimerActive_Unpriv: + svc #SYSTEM_CALL_xTimerIsTimerActive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetTimerDaemonTaskHandle +MPU_xTimerGetTimerDaemonTaskHandle: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv + MPU_xTimerGetTimerDaemonTaskHandle_Priv: + b MPU_xTimerGetTimerDaemonTaskHandleImpl + MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGenericCommandFromTaskEntry +MPU_xTimerGenericCommandFromTaskEntry: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTimerGenericCommandFromTask_Unpriv + MPU_xTimerGenericCommandFromTask_Priv: + b MPU_xTimerGenericCommandFromTaskImpl + MPU_xTimerGenericCommandFromTask_Unpriv: + svc #SYSTEM_CALL_xTimerGenericCommandFromTask +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pcTimerGetName +MPU_pcTimerGetName: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_pcTimerGetName_Unpriv + MPU_pcTimerGetName_Priv: + b MPU_pcTimerGetNameImpl + MPU_pcTimerGetName_Unpriv: + svc #SYSTEM_CALL_pcTimerGetName +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTimerSetReloadMode +MPU_vTimerSetReloadMode: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vTimerSetReloadMode_Unpriv + MPU_vTimerSetReloadMode_Priv: + b MPU_vTimerSetReloadModeImpl + MPU_vTimerSetReloadMode_Unpriv: + svc #SYSTEM_CALL_vTimerSetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetReloadMode +MPU_xTimerGetReloadMode: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTimerGetReloadMode_Unpriv + MPU_xTimerGetReloadMode_Priv: + b MPU_xTimerGetReloadModeImpl + MPU_xTimerGetReloadMode_Unpriv: + svc #SYSTEM_CALL_xTimerGetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTimerGetReloadMode +MPU_uxTimerGetReloadMode: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_uxTimerGetReloadMode_Unpriv + MPU_uxTimerGetReloadMode_Priv: + b MPU_uxTimerGetReloadModeImpl + MPU_uxTimerGetReloadMode_Unpriv: + svc #SYSTEM_CALL_uxTimerGetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetPeriod +MPU_xTimerGetPeriod: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTimerGetPeriod_Unpriv + MPU_xTimerGetPeriod_Priv: + b MPU_xTimerGetPeriodImpl + MPU_xTimerGetPeriod_Unpriv: + svc #SYSTEM_CALL_xTimerGetPeriod +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetExpiryTime +MPU_xTimerGetExpiryTime: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xTimerGetExpiryTime_Unpriv + MPU_xTimerGetExpiryTime_Priv: + b MPU_xTimerGetExpiryTimeImpl + MPU_xTimerGetExpiryTime_Unpriv: + svc #SYSTEM_CALL_xTimerGetExpiryTime +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupWaitBitsEntry +MPU_xEventGroupWaitBitsEntry: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xEventGroupWaitBits_Unpriv + MPU_xEventGroupWaitBits_Priv: + b MPU_xEventGroupWaitBitsImpl + MPU_xEventGroupWaitBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupWaitBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupClearBits +MPU_xEventGroupClearBits: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xEventGroupClearBits_Unpriv + MPU_xEventGroupClearBits_Priv: + b MPU_xEventGroupClearBitsImpl + MPU_xEventGroupClearBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupClearBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupSetBits +MPU_xEventGroupSetBits: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xEventGroupSetBits_Unpriv + MPU_xEventGroupSetBits_Priv: + b MPU_xEventGroupSetBitsImpl + MPU_xEventGroupSetBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupSetBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupSync +MPU_xEventGroupSync: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xEventGroupSync_Unpriv + MPU_xEventGroupSync_Priv: + b MPU_xEventGroupSyncImpl + MPU_xEventGroupSync_Unpriv: + svc #SYSTEM_CALL_xEventGroupSync +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxEventGroupGetNumber +MPU_uxEventGroupGetNumber: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_uxEventGroupGetNumber_Unpriv + MPU_uxEventGroupGetNumber_Priv: + b MPU_uxEventGroupGetNumberImpl + MPU_uxEventGroupGetNumber_Unpriv: + svc #SYSTEM_CALL_uxEventGroupGetNumber +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vEventGroupSetNumber +MPU_vEventGroupSetNumber: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_vEventGroupSetNumber_Unpriv + MPU_vEventGroupSetNumber_Priv: + b MPU_vEventGroupSetNumberImpl + MPU_vEventGroupSetNumber_Unpriv: + svc #SYSTEM_CALL_vEventGroupSetNumber +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSend +MPU_xStreamBufferSend: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xStreamBufferSend_Unpriv + MPU_xStreamBufferSend_Priv: + b MPU_xStreamBufferSendImpl + MPU_xStreamBufferSend_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferReceive +MPU_xStreamBufferReceive: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xStreamBufferReceive_Unpriv + MPU_xStreamBufferReceive_Priv: + b MPU_xStreamBufferReceiveImpl + MPU_xStreamBufferReceive_Unpriv: + svc #SYSTEM_CALL_xStreamBufferReceive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferIsFull +MPU_xStreamBufferIsFull: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xStreamBufferIsFull_Unpriv + MPU_xStreamBufferIsFull_Priv: + b MPU_xStreamBufferIsFullImpl + MPU_xStreamBufferIsFull_Unpriv: + svc #SYSTEM_CALL_xStreamBufferIsFull +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferIsEmpty +MPU_xStreamBufferIsEmpty: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xStreamBufferIsEmpty_Unpriv + MPU_xStreamBufferIsEmpty_Priv: + b MPU_xStreamBufferIsEmptyImpl + MPU_xStreamBufferIsEmpty_Unpriv: + svc #SYSTEM_CALL_xStreamBufferIsEmpty +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSpacesAvailable +MPU_xStreamBufferSpacesAvailable: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xStreamBufferSpacesAvailable_Unpriv + MPU_xStreamBufferSpacesAvailable_Priv: + b MPU_xStreamBufferSpacesAvailableImpl + MPU_xStreamBufferSpacesAvailable_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSpacesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferBytesAvailable +MPU_xStreamBufferBytesAvailable: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xStreamBufferBytesAvailable_Unpriv + MPU_xStreamBufferBytesAvailable_Priv: + b MPU_xStreamBufferBytesAvailableImpl + MPU_xStreamBufferBytesAvailable_Unpriv: + svc #SYSTEM_CALL_xStreamBufferBytesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSetTriggerLevel +MPU_xStreamBufferSetTriggerLevel: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xStreamBufferSetTriggerLevel_Unpriv + MPU_xStreamBufferSetTriggerLevel_Priv: + b MPU_xStreamBufferSetTriggerLevelImpl + MPU_xStreamBufferSetTriggerLevel_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferNextMessageLengthBytes +MPU_xStreamBufferNextMessageLengthBytes: + push {r0, r1} + mrs r0, control + movs r1, #1 + tst r0, r1 + pop {r0, r1} + bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv + MPU_xStreamBufferNextMessageLengthBytes_Priv: + b MPU_xStreamBufferNextMessageLengthBytesImpl + MPU_xStreamBufferNextMessageLengthBytes_Unpriv: + svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes +/*-----------------------------------------------------------*/ + +/* Default weak implementations in case one is not available from + * mpu_wrappers because of config options. */ + + PUBWEAK MPU_xTaskDelayUntilImpl +MPU_xTaskDelayUntilImpl: + b MPU_xTaskDelayUntilImpl + + PUBWEAK MPU_xTaskAbortDelayImpl +MPU_xTaskAbortDelayImpl: + b MPU_xTaskAbortDelayImpl + + PUBWEAK MPU_vTaskDelayImpl +MPU_vTaskDelayImpl: + b MPU_vTaskDelayImpl + + PUBWEAK MPU_uxTaskPriorityGetImpl +MPU_uxTaskPriorityGetImpl: + b MPU_uxTaskPriorityGetImpl + + PUBWEAK MPU_eTaskGetStateImpl +MPU_eTaskGetStateImpl: + b MPU_eTaskGetStateImpl + + PUBWEAK MPU_vTaskGetInfoImpl +MPU_vTaskGetInfoImpl: + b MPU_vTaskGetInfoImpl + + PUBWEAK MPU_xTaskGetIdleTaskHandleImpl +MPU_xTaskGetIdleTaskHandleImpl: + b MPU_xTaskGetIdleTaskHandleImpl + + PUBWEAK MPU_vTaskSuspendImpl +MPU_vTaskSuspendImpl: + b MPU_vTaskSuspendImpl + + PUBWEAK MPU_vTaskResumeImpl +MPU_vTaskResumeImpl: + b MPU_vTaskResumeImpl + + PUBWEAK MPU_xTaskGetTickCountImpl +MPU_xTaskGetTickCountImpl: + b MPU_xTaskGetTickCountImpl + + PUBWEAK MPU_uxTaskGetNumberOfTasksImpl +MPU_uxTaskGetNumberOfTasksImpl: + b MPU_uxTaskGetNumberOfTasksImpl + + PUBWEAK MPU_ulTaskGetRunTimeCounterImpl +MPU_ulTaskGetRunTimeCounterImpl: + b MPU_ulTaskGetRunTimeCounterImpl + + PUBWEAK MPU_ulTaskGetRunTimePercentImpl +MPU_ulTaskGetRunTimePercentImpl: + b MPU_ulTaskGetRunTimePercentImpl + + PUBWEAK MPU_ulTaskGetIdleRunTimePercentImpl +MPU_ulTaskGetIdleRunTimePercentImpl: + b MPU_ulTaskGetIdleRunTimePercentImpl + + PUBWEAK MPU_ulTaskGetIdleRunTimeCounterImpl +MPU_ulTaskGetIdleRunTimeCounterImpl: + b MPU_ulTaskGetIdleRunTimeCounterImpl + + PUBWEAK MPU_vTaskSetApplicationTaskTagImpl +MPU_vTaskSetApplicationTaskTagImpl: + b MPU_vTaskSetApplicationTaskTagImpl + + PUBWEAK MPU_xTaskGetApplicationTaskTagImpl +MPU_xTaskGetApplicationTaskTagImpl: + b MPU_xTaskGetApplicationTaskTagImpl + + PUBWEAK MPU_vTaskSetThreadLocalStoragePointerImpl +MPU_vTaskSetThreadLocalStoragePointerImpl: + b MPU_vTaskSetThreadLocalStoragePointerImpl + + PUBWEAK MPU_pvTaskGetThreadLocalStoragePointerImpl +MPU_pvTaskGetThreadLocalStoragePointerImpl: + b MPU_pvTaskGetThreadLocalStoragePointerImpl + + PUBWEAK MPU_uxTaskGetSystemStateImpl +MPU_uxTaskGetSystemStateImpl: + b MPU_uxTaskGetSystemStateImpl + + PUBWEAK MPU_uxTaskGetStackHighWaterMarkImpl +MPU_uxTaskGetStackHighWaterMarkImpl: + b MPU_uxTaskGetStackHighWaterMarkImpl + + PUBWEAK MPU_uxTaskGetStackHighWaterMark2Impl +MPU_uxTaskGetStackHighWaterMark2Impl: + b MPU_uxTaskGetStackHighWaterMark2Impl + + PUBWEAK MPU_xTaskGetCurrentTaskHandleImpl +MPU_xTaskGetCurrentTaskHandleImpl: + b MPU_xTaskGetCurrentTaskHandleImpl + + PUBWEAK MPU_xTaskGetSchedulerStateImpl +MPU_xTaskGetSchedulerStateImpl: + b MPU_xTaskGetSchedulerStateImpl + + PUBWEAK MPU_vTaskSetTimeOutStateImpl +MPU_vTaskSetTimeOutStateImpl: + b MPU_vTaskSetTimeOutStateImpl + + PUBWEAK MPU_xTaskCheckForTimeOutImpl +MPU_xTaskCheckForTimeOutImpl: + b MPU_xTaskCheckForTimeOutImpl + + PUBWEAK MPU_xTaskGenericNotifyImpl +MPU_xTaskGenericNotifyImpl: + b MPU_xTaskGenericNotifyImpl + + PUBWEAK MPU_xTaskGenericNotifyWaitImpl +MPU_xTaskGenericNotifyWaitImpl: + b MPU_xTaskGenericNotifyWaitImpl + + PUBWEAK MPU_ulTaskGenericNotifyTakeImpl +MPU_ulTaskGenericNotifyTakeImpl: + b MPU_ulTaskGenericNotifyTakeImpl + + PUBWEAK MPU_xTaskGenericNotifyStateClearImpl +MPU_xTaskGenericNotifyStateClearImpl: + b MPU_xTaskGenericNotifyStateClearImpl + + PUBWEAK MPU_ulTaskGenericNotifyValueClearImpl +MPU_ulTaskGenericNotifyValueClearImpl: + b MPU_ulTaskGenericNotifyValueClearImpl + + PUBWEAK MPU_xQueueGenericSendImpl +MPU_xQueueGenericSendImpl: + b MPU_xQueueGenericSendImpl + + PUBWEAK MPU_uxQueueMessagesWaitingImpl +MPU_uxQueueMessagesWaitingImpl: + b MPU_uxQueueMessagesWaitingImpl + + PUBWEAK MPU_uxQueueSpacesAvailableImpl +MPU_uxQueueSpacesAvailableImpl: + b MPU_uxQueueSpacesAvailableImpl + + PUBWEAK MPU_xQueueReceiveImpl +MPU_xQueueReceiveImpl: + b MPU_xQueueReceiveImpl + + PUBWEAK MPU_xQueuePeekImpl +MPU_xQueuePeekImpl: + b MPU_xQueuePeekImpl + + PUBWEAK MPU_xQueueSemaphoreTakeImpl +MPU_xQueueSemaphoreTakeImpl: + b MPU_xQueueSemaphoreTakeImpl + + PUBWEAK MPU_xQueueGetMutexHolderImpl +MPU_xQueueGetMutexHolderImpl: + b MPU_xQueueGetMutexHolderImpl + + PUBWEAK MPU_xQueueTakeMutexRecursiveImpl +MPU_xQueueTakeMutexRecursiveImpl: + b MPU_xQueueTakeMutexRecursiveImpl + + PUBWEAK MPU_xQueueGiveMutexRecursiveImpl +MPU_xQueueGiveMutexRecursiveImpl: + b MPU_xQueueGiveMutexRecursiveImpl + + PUBWEAK MPU_xQueueSelectFromSetImpl +MPU_xQueueSelectFromSetImpl: + b MPU_xQueueSelectFromSetImpl + + PUBWEAK MPU_xQueueAddToSetImpl +MPU_xQueueAddToSetImpl: + b MPU_xQueueAddToSetImpl + + PUBWEAK MPU_vQueueAddToRegistryImpl +MPU_vQueueAddToRegistryImpl: + b MPU_vQueueAddToRegistryImpl + + PUBWEAK MPU_vQueueUnregisterQueueImpl +MPU_vQueueUnregisterQueueImpl: + b MPU_vQueueUnregisterQueueImpl + + PUBWEAK MPU_pcQueueGetNameImpl +MPU_pcQueueGetNameImpl: + b MPU_pcQueueGetNameImpl + + PUBWEAK MPU_pvTimerGetTimerIDImpl +MPU_pvTimerGetTimerIDImpl: + b MPU_pvTimerGetTimerIDImpl + + PUBWEAK MPU_vTimerSetTimerIDImpl +MPU_vTimerSetTimerIDImpl: + b MPU_vTimerSetTimerIDImpl + + PUBWEAK MPU_xTimerIsTimerActiveImpl +MPU_xTimerIsTimerActiveImpl: + b MPU_xTimerIsTimerActiveImpl + + PUBWEAK MPU_xTimerGetTimerDaemonTaskHandleImpl +MPU_xTimerGetTimerDaemonTaskHandleImpl: + b MPU_xTimerGetTimerDaemonTaskHandleImpl + + PUBWEAK MPU_xTimerGenericCommandFromTaskImpl +MPU_xTimerGenericCommandFromTaskImpl: + b MPU_xTimerGenericCommandFromTaskImpl + + PUBWEAK MPU_pcTimerGetNameImpl +MPU_pcTimerGetNameImpl: + b MPU_pcTimerGetNameImpl + + PUBWEAK MPU_vTimerSetReloadModeImpl +MPU_vTimerSetReloadModeImpl: + b MPU_vTimerSetReloadModeImpl + + PUBWEAK MPU_xTimerGetReloadModeImpl +MPU_xTimerGetReloadModeImpl: + b MPU_xTimerGetReloadModeImpl + + PUBWEAK MPU_uxTimerGetReloadModeImpl +MPU_uxTimerGetReloadModeImpl: + b MPU_uxTimerGetReloadModeImpl + + PUBWEAK MPU_xTimerGetPeriodImpl +MPU_xTimerGetPeriodImpl: + b MPU_xTimerGetPeriodImpl + + PUBWEAK MPU_xTimerGetExpiryTimeImpl +MPU_xTimerGetExpiryTimeImpl: + b MPU_xTimerGetExpiryTimeImpl + + PUBWEAK MPU_xEventGroupWaitBitsImpl +MPU_xEventGroupWaitBitsImpl: + b MPU_xEventGroupWaitBitsImpl + + PUBWEAK MPU_xEventGroupClearBitsImpl +MPU_xEventGroupClearBitsImpl: + b MPU_xEventGroupClearBitsImpl + + PUBWEAK MPU_xEventGroupSetBitsImpl +MPU_xEventGroupSetBitsImpl: + b MPU_xEventGroupSetBitsImpl + + PUBWEAK MPU_xEventGroupSyncImpl +MPU_xEventGroupSyncImpl: + b MPU_xEventGroupSyncImpl + + PUBWEAK MPU_uxEventGroupGetNumberImpl +MPU_uxEventGroupGetNumberImpl: + b MPU_uxEventGroupGetNumberImpl + + PUBWEAK MPU_vEventGroupSetNumberImpl +MPU_vEventGroupSetNumberImpl: + b MPU_vEventGroupSetNumberImpl + + PUBWEAK MPU_xStreamBufferSendImpl +MPU_xStreamBufferSendImpl: + b MPU_xStreamBufferSendImpl + + PUBWEAK MPU_xStreamBufferReceiveImpl +MPU_xStreamBufferReceiveImpl: + b MPU_xStreamBufferReceiveImpl + + PUBWEAK MPU_xStreamBufferIsFullImpl +MPU_xStreamBufferIsFullImpl: + b MPU_xStreamBufferIsFullImpl + + PUBWEAK MPU_xStreamBufferIsEmptyImpl +MPU_xStreamBufferIsEmptyImpl: + b MPU_xStreamBufferIsEmptyImpl + + PUBWEAK MPU_xStreamBufferSpacesAvailableImpl +MPU_xStreamBufferSpacesAvailableImpl: + b MPU_xStreamBufferSpacesAvailableImpl + + PUBWEAK MPU_xStreamBufferBytesAvailableImpl +MPU_xStreamBufferBytesAvailableImpl: + b MPU_xStreamBufferBytesAvailableImpl + + PUBWEAK MPU_xStreamBufferSetTriggerLevelImpl +MPU_xStreamBufferSetTriggerLevelImpl: + b MPU_xStreamBufferSetTriggerLevelImpl + + PUBWEAK MPU_xStreamBufferNextMessageLengthBytesImpl +MPU_xStreamBufferNextMessageLengthBytesImpl: + b MPU_xStreamBufferNextMessageLengthBytesImpl + +/*-----------------------------------------------------------*/ + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + END diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c new file mode 100644 index 000000000..76d2b2445 --- /dev/null +++ b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c @@ -0,0 +1,2280 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024-2025 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU includes. */ +#include "mpu_wrappers.h" +#include "mpu_syscall_numbers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration settings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to check the validity of an interrupt priority. + */ +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) ) +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used during system call enter and exit. + */ +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Offsets in the stack to the parameters when inside the SVC handler. + */ +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +#if ( portARMV8M_MINOR_VERSION >= 1 ) + + /* Enable Privileged eXecute Never MPU attribute for the selected memory + * region. */ + #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL ) +#endif /* portARMV8M_MINOR_VERSION >= 1 */ + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Extract first address of the MPU region as encoded in the + * RBAR (Region Base Address Register) value. */ +#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \ + ( ( rbar ) & portMPU_RBAR_ADDRESS_MASK ) + +/* Extract last address of the MPU region as encoded in the + * RLAR (Region Limit Address Register) value. */ +#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \ + ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK ) + +/* Does addr lies within [start, end] address range? */ +#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \ + ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) ) + +/* Is the access request satisfied by the available permissions? */ +#define portIS_AUTHORIZED( accessRequest, permissions ) \ + ( ( ( permissions ) & ( accessRequest ) ) == accessRequest ) + +/* Max value that fits in a uint32_t type. */ +#define portUINT32_MAX ( ~( ( uint32_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. + */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 + +/** + * @brief Constants required to check and configure PACBTI security feature implementation. + */ +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) ) + + #define portCONTROL_UPAC_EN ( 1UL << 7UL ) + #define portCONTROL_PAC_EN ( 1UL << 6UL ) + #define portCONTROL_UBTI_EN ( 1UL << 5UL ) + #define portCONTROL_BTI_EN ( 1UL << 4UL ) + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Extract MPU region's access permissions from the Region Base Address + * Register (RBAR) value. + * + * @param ulRBARValue RBAR value for the MPU region. + * + * @return uint32_t Access permissions. + */ + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + + /** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + /** + * @brief Configures PACBTI features. + * + * This function configures the Pointer Authentication, and Branch Target + * Identification security features as per the user configuration. It returns + * the value of the special purpose CONTROL register accordingly, and optionally + * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M + * architecture based) target supports PACBTI security feature. + * + * @param xWriteControlRegister Used to control whether the special purpose + * CONTROL register should be updated or not. + * + * @return CONTROL register value according to the configured PACBTI option. + */ + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the system call stack so that upon returning from + * SVC, the system call stack is used. + * + * @param pulTaskStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + * @param ucSystemCallNumber The system call number of the system call. + */ + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Raise SVC for exiting from a system call. + */ + void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief This variable is set to pdTRUE when the scheduler is started. + */ + PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + + /** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +/** + * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + /** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + + /** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + + /** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the cpsid instruction + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessPermissions = 0; + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_ONLY ) + { + ulAccessPermissions = tskMPU_READ_PERMISSION; + } + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_WRITE ) + { + ulAccessPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION ); + } + + return ulAccessPermissions; + } + +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } + +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ portOFFSET_TO_PC ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ]; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulSystemCallStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the system call section (i.e. application is + * not raising SVC directly). + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as + * it is non-NULL only during the execution of a system call (i.e. + * between system call enter and exit). + * 3. System call is not for a kernel API disabled by the configuration + * in FreeRTOSConfig.h. + * 4. We do not need to check that ucSystemCallNumber is within range + * because the assembly SVC handler checks that before calling + * this function. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) && + ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) ) + { + pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the system call stack for the stack frame. */ + pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulSystemCallStack[ i ] = pulTaskStack[ i ]; + } + + /* Store the value of the Link Register before the SVC was raised. + * It contains the address of the caller of the System Call entry + * point (i.e. the caller of the MPU_). We need to restore it + * when we exit from the system call. */ + pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; + + /* Store the value of the PSPLIM register before the SVC was raised. + * We need to restore it when we exit from the system call. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* Use the pulSystemCallStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif + + /* Start executing the system call upon returning from this handler. */ + pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; + + /* Raise a request to exit from the system call upon finishing the + * system call. */ + pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; + + /* Remember the location where we should copy the stack frame when we exit from + * the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize; + + /* Record if the hardware used padding to force the stack pointer + * to be double word aligned. */ + if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK ) + { + pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG; + } + else + { + pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG ); + } + + /* We ensure in pxPortInitialiseStack that the system call stack is + * double word aligned and therefore, there is no need of padding. + * Clear the bit[9] of stacked xPSR. */ + pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + + /* Raise the privilege for the duration of the system call. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " bics r0, r1 \n" /* Clear nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */ + { + __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulTaskStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the privileged code (i.e. application is not + * raising SVC directly). This SVC is only raised from + * vRequestSystemCallExit which is in the privileged code section. + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL - + * this means that we previously entered a system call and the + * application is not attempting to exit without entering a system + * call. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) ) + { + pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the task stack for the stack frame. */ + pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulTaskStack[ i ] = pulSystemCallStack[ i ]; + } + + /* Use the pulTaskStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) ); + + /* Return to the caller of the System Call entry point (i.e. the + * caller of the MPU_). */ + pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + /* Ensure that LR has a valid value.*/ + pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + + /* Restore the PSPLIM register to what it was at the time of + * system call entry. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* If the hardware used padding to force the stack pointer + * to be double word aligned, set the stacked xPSR bit[9], + * otherwise clear it. */ + if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG ) + { + pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK; + } + else + { + pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + } + + /* This is not NULL only for the duration of the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; + + /* Drop the privilege before returning to the thread mode. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " orrs r0, r1 \n" /* Set nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xTaskIsPrivileged = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xTaskIsPrivileged = pdTRUE; + } + + return xTaskIsPrivileged; + } + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged, + xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulIndex = 0; + uint32_t ulControl = 0x0; + + xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ + ulIndex++; + + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + ulIndex++; + + #if ( configENABLE_TRUSTZONE == 1 ) + { + xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */ + ulIndex++; + } + #endif /* configENABLE_TRUSTZONE */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + ulIndex++; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Check PACBTI security feature configuration before pushing the + * CONTROL register's value on task's TCB. */ + ulControl = prvConfigurePACBTI( pdFALSE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + if( xRunPrivileged == pdTRUE ) + { + xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + else + { + xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG ); + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ + ulIndex++; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + { + /* Ensure that the system call stack is double word aligned. */ + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) + + ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + /* This is not NULL only for the duration of a system call. */ + xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL; + } + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ]; + ulIndex++; + } + } + #endif /* configENABLE_PAC */ + + return &( xMPUSettings->ulContext[ ulIndex ] ); + } + +#else /* configENABLE_MPU */ + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ + { + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + pxTopOfStack--; + *pxTopOfStack = ulTaskPacKey[ i ]; + } + } + #endif /* configENABLE_PAC */ + + return pxTopOfStack; + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Set the CONTROL register value based on PACBTI security feature + * configuration before starting the first task. */ + ( void ) prvConfigurePACBTI( pdTRUE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + { + xSchedulerRunning = pdTRUE; + } + #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + configSTACK_DEPTH_TYPE uxStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( uxStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* PXN. */ + #if ( portARMV8M_MINOR_VERSION >= 1 ) + { + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ); + } + } + #endif /* portARMV8M_MINOR_VERSION >= 1 */ + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, + uint32_t ulBufferLength, + uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */ + + { + uint32_t i, ulBufferStartAddress, ulBufferEndAddress; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE ) + { + ulBufferStartAddress = ( uint32_t ) pvBuffer; + ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL ); + + for( i = 0; i < portTOTAL_NUM_REGIONS; i++ ) + { + /* Is the MPU region enabled? */ + if( ( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR & portMPU_RLAR_REGION_ENABLE ) == portMPU_RLAR_REGION_ENABLE ) + { + if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_AUTHORIZED( ulAccessRequested, + prvGetRegionAccessPermissions( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ) ) ) + { + xAccessGranted = pdTRUE; + break; + } + } + } + } + } + + return xAccessGranted; + } + +#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings; + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else + { + xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 ) + { + xAccessGranted = pdTRUE; + } + } + } + + return xAccessGranted; + } + + #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + ( void ) lInternalIndexOfKernelObject; + + /* If Access Control List feature is not used, all the tasks have + * access to all the kernel objects. */ + return pdTRUE; + } + + #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + { + uint32_t ulControl = 0x0; + + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); + + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; + + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h b/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h new file mode 100644 index 000000000..b7021b024 --- /dev/null +++ b/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kernel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s b/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s new file mode 100644 index 000000000..bfe9eee4b --- /dev/null +++ b/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s @@ -0,0 +1,456 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" + +/* System call numbers includes. */ +#include "mpu_syscall_numbers.h" + +#ifndef configUSE_MPU_WRAPPERS_V1 + #define configUSE_MPU_WRAPPERS_V1 0 +#endif + +#ifndef configRUN_FREERTOS_SECURE_ONLY + #define configRUN_FREERTOS_SECURE_ONLY 0 +#endif + + EXTERN pxCurrentTCB + EXTERN vTaskSwitchContext + EXTERN vPortSVCHandler_C +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + EXTERN vSystemCallEnter + EXTERN vSystemCallExit +#endif + + PUBLIC xIsPrivileged + PUBLIC vResetPrivilege + PUBLIC vRestoreContextOfFirstTask + PUBLIC vRaisePrivilege + PUBLIC vStartFirstTask + PUBLIC ulSetInterruptMask + PUBLIC vClearInterruptMask + PUBLIC PendSV_Handler + PUBLIC SVC_Handler + +#if ( configENABLE_FPU == 1 ) + #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0. +#endif +/*-----------------------------------------------------------*/ + +/*---------------- Unprivileged Functions -------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION .text:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +xIsPrivileged: + mrs r0, control /* r0 = CONTROL. */ + movs r1, #1 /* r1 = 1. */ + tst r0, r1 /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */ + beq running_privileged /* If the result of previous AND operation was 0, branch. */ + movs r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + bx lr /* Return. */ + running_privileged: + movs r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + bx lr /* Return. */ + +/*-----------------------------------------------------------*/ + +vResetPrivilege: + mrs r0, control /* r0 = CONTROL. */ + movs r1, #1 /* r1 = 1. */ + orrs r0, r1 /* r0 = r0 | r1. */ + msr control, r0 /* CONTROL = r0. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +/*----------------- Privileged Functions --------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION privileged_functions:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +vRestoreContextOfFirstTask: + program_mpu_first_task: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r3] /* r0 = pxCurrentTCB.*/ + + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + movs r3, #1 /* r3 = 1. */ + bics r2, r3 /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */ + str r2, [r1] /* Disable MPU. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r1, [r2] /* Program MAIR0. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */ + + movs r3, #4 /* r3 = 4. */ + str r3, [r1] /* Program RNR = 4. */ + ldmia r0!, {r4-r5} /* Read first set of RBAR/RLAR registers from TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + stmia r2!, {r4-r5} /* Write first set of RBAR/RLAR registers. */ + movs r3, #5 /* r3 = 5. */ + str r3, [r1] /* Program RNR = 5. */ + ldmia r0!, {r4-r5} /* Read second set of RBAR/RLAR registers from TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + stmia r2!, {r4-r5} /* Write second set of RBAR/RLAR registers. */ + movs r3, #6 /* r3 = 6. */ + str r3, [r1] /* Program RNR = 6. */ + ldmia r0!, {r4-r5} /* Read third set of RBAR/RLAR registers from TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + stmia r2!, {r4-r5} /* Write third set of RBAR/RLAR registers. */ + movs r3, #7 /* r3 = 6. */ + str r3, [r1] /* Program RNR = 7. */ + ldmia r0!, {r4-r5} /* Read fourth set of RBAR/RLAR registers from TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + stmia r2!, {r4-r5} /* Write fourth set of RBAR/RLAR registers. */ + + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + movs r3, #1 /* r3 = 1. */ + orrs r2, r3 /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */ + str r2, [r1] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + + restore_context_first_task: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r2] /* r0 = pxCurrentTCB.*/ + ldr r1, [r0] /* r1 = Location of saved context in TCB. */ + + restore_special_regs_first_task: + subs r1, #16 + ldmia r1!, {r2-r5} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */ + subs r1, #16 + msr psp, r2 + #if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + msr psplim, r3 + #endif + msr control, r4 + mov lr, r5 + + restore_general_regs_first_task: + subs r1, #32 + ldmia r1!, {r4-r7} /* r4-r7 contain half of the hardware saved context. */ + stmia r2!, {r4-r7} /* Copy half of the the hardware saved context on the task stack. */ + ldmia r1!, {r4-r7} /* r4-r7 contain rest half of the hardware saved context. */ + stmia r2!, {r4-r7} /* Copy rest half of the the hardware saved context on the task stack. */ + subs r1, #48 + ldmia r1!, {r4-r7} /* Restore r8-r11. */ + mov r8, r4 /* r8 = r4. */ + mov r9, r5 /* r9 = r5. */ + mov r10, r6 /* r10 = r6. */ + mov r11, r7 /* r11 = r7. */ + subs r1, #32 + ldmia r1!, {r4-r7} /* Restore r4-r7. */ + subs r1, #16 + + restore_context_done_first_task: + str r1, [r0] /* Save the location where the context should be saved next as the first member of TCB. */ + bx lr + +#else /* configENABLE_MPU */ + +vRestoreContextOfFirstTask: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + + ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */ +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + msr psplim, r1 /* Set this task's PSPLIM value. */ +#endif + movs r1, #2 /* r1 = 2. */ + msr CONTROL, r1 /* Switch to use PSP in the thread mode. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + bx r2 /* Finally, branch to EXC_RETURN. */ + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +vRaisePrivilege: + mrs r0, control /* Read the CONTROL register. */ + movs r1, #1 /* r1 = 1. */ + bics r0, r1 /* Clear the bit 0. */ + msr control, r0 /* Write back the new CONTROL value. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vStartFirstTask: + ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */ + ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */ + ldr r0, [r0] /* The first entry in vector table is stack pointer. */ + msr msp, r0 /* Set the MSP back to the start of the stack. */ + cpsie i /* Globally enable interrupts. */ + dsb + isb + svc 102 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */ + nop +/*-----------------------------------------------------------*/ + +ulSetInterruptMask: + mrs r0, PRIMASK + cpsid i + bx lr +/*-----------------------------------------------------------*/ + +vClearInterruptMask: + msr PRIMASK, r0 + bx lr +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +PendSV_Handler: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r2] /* r0 = pxCurrentTCB. */ + ldr r1, [r0] /* r1 = Location in TCB where the context should be saved. */ + mrs r2, psp /* r2 = PSP. */ + + save_general_regs: + stmia r1!, {r4-r7} /* Store r4-r7. */ + mov r4, r8 /* r4 = r8. */ + mov r5, r9 /* r5 = r9. */ + mov r6, r10 /* r6 = r10. */ + mov r7, r11 /* r7 = r11. */ + stmia r1!, {r4-r7} /* Store r8-r11. */ + ldmia r2!, {r4-r7} /* Copy half of the hardware saved context into r4-r7. */ + stmia r1!, {r4-r7} /* Store the hardware saved context. */ + ldmia r2!, {r4-r7} /* Copy rest half of the hardware saved context into r4-r7. */ + stmia r1!, {r4-r7} /* Store the hardware saved context. */ + + save_special_regs: + mrs r2, psp /* r2 = PSP. */ + #if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + mrs r3, psplim /* r3 = PSPLIM. */ + #else + movs r3, #0 /* r3 = 0. 0 is stored in the PSPLIM slot. */ + #endif + mrs r4, control /* r4 = CONTROL. */ + mov r5, lr /* r5 = LR. */ + stmia r1!, {r2-r5} /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ + str r1, [r0] /* Save the location from where the context should be restored as the first member of TCB. */ + + select_next_task: + cpsid i + bl vTaskSwitchContext + cpsie i + + program_mpu: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r3] /* r0 = pxCurrentTCB.*/ + + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + movs r3, #1 /* r3 = 1. */ + bics r2, r3 /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */ + str r2, [r1] /* Disable MPU. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r1, [r2] /* Program MAIR0. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */ + + movs r3, #4 /* r3 = 4. */ + str r3, [r1] /* Program RNR = 4. */ + ldmia r0!, {r4-r5} /* Read first set of RBAR/RLAR registers from TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + stmia r2!, {r4-r5} /* Write first set of RBAR/RLAR registers. */ + movs r3, #5 /* r3 = 5. */ + str r3, [r1] /* Program RNR = 5. */ + ldmia r0!, {r4-r5} /* Read second set of RBAR/RLAR registers from TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + stmia r2!, {r4-r5} /* Write second set of RBAR/RLAR registers. */ + movs r3, #6 /* r3 = 6. */ + str r3, [r1] /* Program RNR = 6. */ + ldmia r0!, {r4-r5} /* Read third set of RBAR/RLAR registers from TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + stmia r2!, {r4-r5} /* Write third set of RBAR/RLAR registers. */ + movs r3, #7 /* r3 = 6. */ + str r3, [r1] /* Program RNR = 7. */ + ldmia r0!, {r4-r5} /* Read fourth set of RBAR/RLAR registers from TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + stmia r2!, {r4-r5} /* Write fourth set of RBAR/RLAR registers. */ + + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + movs r3, #1 /* r3 = 1. */ + orrs r2, r3 /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */ + str r2, [r1] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + + restore_context: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r2] /* r0 = pxCurrentTCB.*/ + ldr r1, [r0] /* r1 = Location of saved context in TCB. */ + + restore_special_regs: + subs r1, #16 + ldmia r1!, {r2-r5} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */ + subs r1, #16 + msr psp, r2 + #if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + msr psplim, r3 + #endif + msr control, r4 + mov lr, r5 + + restore_general_regs: + subs r1, #32 + ldmia r1!, {r4-r7} /* r4-r7 contain half of the hardware saved context. */ + stmia r2!, {r4-r7} /* Copy half of the the hardware saved context on the task stack. */ + ldmia r1!, {r4-r7} /* r4-r7 contain rest half of the hardware saved context. */ + stmia r2!, {r4-r7} /* Copy rest half of the the hardware saved context on the task stack. */ + subs r1, #48 + ldmia r1!, {r4-r7} /* Restore r8-r11. */ + mov r8, r4 /* r8 = r4. */ + mov r9, r5 /* r9 = r5. */ + mov r10, r6 /* r10 = r6. */ + mov r11, r7 /* r11 = r7. */ + subs r1, #32 + ldmia r1!, {r4-r7} /* Restore r4-r7. */ + subs r1, #16 + + restore_context_done: + str r1, [r0] /* Save the location where the context should be saved next as the first member of TCB. */ + bx lr + +#else /* configENABLE_MPU */ + +PendSV_Handler: + mrs r0, psp /* Read PSP in r0. */ + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + + subs r0, r0, #40 /* Make space for PSPLIM, LR and the remaining registers on the stack. */ + str r0, [r1] /* Save the new top of stack in TCB. */ +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + mrs r2, psplim /* r2 = PSPLIM. */ +#else + movs r2, #0 /* r0 = 0. 0 is stored in the PSPLIM slot. */ +#endif + mov r3, lr /* r3 = LR/EXC_RETURN. */ + stmia r0!, {r2-r7} /* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */ + mov r4, r8 /* r4 = r8. */ + mov r5, r9 /* r5 = r9. */ + mov r6, r10 /* r6 = r10. */ + mov r7, r11 /* r7 = r11. */ + stmia r0!, {r4-r7} /* Store the high registers that are not saved automatically. */ + + cpsid i + bl vTaskSwitchContext + cpsie i + + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ + + adds r0, r0, #24 /* Move to the high registers. */ + ldmia r0!, {r4-r7} /* Restore the high registers that are not automatically restored. */ + mov r8, r4 /* r8 = r4. */ + mov r9, r5 /* r9 = r5. */ + mov r10, r6 /* r10 = r6. */ + mov r11, r7 /* r11 = r7. */ + msr psp, r0 /* Remember the new top of stack for the task. */ + subs r0, r0, #40 /* Move to the starting of the saved context. */ + ldmia r0!, {r2-r7} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */ +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + msr psplim, r2 /* Restore the PSPLIM register value for the task. */ +#endif + bx r3 + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + +SVC_Handler: + movs r0, #4 + mov r1, lr + tst r0, r1 + beq stack_on_msp + stack_on_psp: + mrs r0, psp + b route_svc + stack_on_msp: + mrs r0, msp + b route_svc + + route_svc: + ldr r3, [r0, #24] + subs r3, #2 + ldrb r2, [r3, #0] + cmp r2, #NUM_SYSTEM_CALLS + blt system_call_enter + cmp r2, #104 /* portSVC_SYSTEM_CALL_EXIT. */ + beq system_call_exit + b vPortSVCHandler_C + + system_call_enter: + b vSystemCallEnter + system_call_exit: + b vSystemCallExit + +#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +SVC_Handler: + movs r0, #4 + mov r1, lr + tst r0, r1 + beq stacking_used_msp + mrs r0, psp + b vPortSVCHandler_C + stacking_used_msp: + mrs r0, msp + b vPortSVCHandler_C + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + + END diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h new file mode 100644 index 000000000..9d6c3368e --- /dev/null +++ b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h @@ -0,0 +1,92 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M23" +#define portHAS_ARMV8M_MAIN_EXTENSION 0 +#define portARMV8M_MINOR_VERSION 0 +#define portDONT_DISCARD __root +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +#if ( configTOTAL_MPU_REGIONS == 16 ) + #error 16 MPU regions are not yet supported for this port. +#endif + +#ifndef configENABLE_MVE + #define configENABLE_MVE 0 +#elif ( configENABLE_MVE != 0 ) + #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M23. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" ) +#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ +#pragma diag_suppress=Be006 +#pragma diag_suppress=Pa082 +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h new file mode 100644 index 000000000..f373bcad5 --- /dev/null +++ b/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h @@ -0,0 +1,582 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACROCOMMON_H +#define PORTMACROCOMMON_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. +#endif /* configENABLE_FPU */ + +#ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. +#endif /* configENABLE_MPU */ + +#ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. +#endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() +#define portINLINE __inline +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif +#define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ +extern BaseType_t xPortIsInsideInterrupt( void ); + +extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + +extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; +extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + +extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; +extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + +#if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_PAC == 1 ) + + /** + * @brief Generates 128-bit task's random PAC key. + * + * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be + * filled with a 128-bit random number. + */ + void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); + +#endif /* configENABLE_PAC */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ +#if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) +#else + #define portPRIVILEGE_BIT ( 0x0UL ) +#endif /* configENABLE_MPU */ + +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ +#define portPRIVILEGED_FLASH_REGION ( 0UL ) +#define portUNPRIVILEGED_FLASH_REGION ( 1UL ) +#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) +#define portPRIVILEGED_RAM_REGION ( 3UL ) +#define portSTACK_REGION ( 4UL ) +#define portFIRST_CONFIGURABLE_REGION ( 5UL ) +#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) +#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) +#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ +#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ +#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ +#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ +#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ +#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ +#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ +#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) +#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) +#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + +#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) +#define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) +#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) +#define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + +#define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + #ifndef configSYSTEM_CALL_STACK_SIZE + #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. + #endif + + /** + * @brief System call stack. + */ + typedef struct SYSTEM_CALL_STACK_INFO + { + uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; + uint32_t * pulSystemCallStack; + uint32_t * pulSystemCallStackLimit; + uint32_t * pulTaskStack; + uint32_t ulLinkRegisterAtSystemCallEntry; + uint32_t ulStackLimitRegisterAtSystemCallEntry; + } xSYSTEM_CALL_STACK_INFO; + + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + /** + * @brief MPU settings as stored in the TCB. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><-----------><----> + * 16 17 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 71 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 17 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 55 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | | | PC, xPSR | EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><-----------><----> + * 16 17 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 70 + + #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + /* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 17 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 54 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+------------------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +----------+-----------------+------------------------------+------------+-----+ + * + * <---------><----------------><------------------------------><-----------><----> + * 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 38 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+----------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | PC, xPSR | EXC_RETURN | | | + * +----------+-----------------+----------------------+------------+-----+ + * + * <---------><----------------><----------------------><-----------><----> + * 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 37 + + #else /* #if( configENABLE_TRUSTZONE == 1 ) */ + + /* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) + + /* Size of an Access Control List (ACL) entry in bits. */ + #define portACL_ENTRY_SIZE_BITS ( 32U ) + + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + uint32_t ulContext[ MAX_CONTEXT_SIZE ]; + uint32_t ulTaskFlags; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo; + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ]; + #endif + #endif + } xMPU_SETTINGS; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Validate priority of ISRs that are allowed to call FreeRTOS + * system calls. + */ +#if ( configASSERT_DEFINED == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif +#endif + +/** + * @brief SVC numbers. + */ +#define portSVC_ALLOCATE_SECURE_CONTEXT 100 +#define portSVC_FREE_SECURE_CONTEXT 101 +#define portSVC_START_SCHEDULER 102 +#define portSVC_RAISE_PRIVILEGE 103 +#define portSVC_SYSTEM_CALL_EXIT 104 +#define portSVC_YIELD 105 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) +#endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() +#else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + extern BaseType_t xPortIsTaskPrivileged( void ); + +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACROCOMMON_H */ diff --git a/portable/IAR/ARM_CM3/port.c b/portable/IAR/ARM_CM3/port.c new file mode 100644 index 000000000..ef590cf95 --- /dev/null +++ b/portable/IAR/ARM_CM3/port.c @@ -0,0 +1,732 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ARM CM3 port. +*----------------------------------------------------------*/ + +/* IAR includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#if ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) + #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ +#endif + +/* Prototype of all Interrupt Service Routines (ISRs). */ +typedef void ( * portISR_t )( void ); + +/* Constants required to manipulate the core. Registers first... */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +/* ...then bits in the registers. */ +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) + +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL ) +#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL ) + +/* Constants used to check the installation of the FreeRTOS interrupt handlers. */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xE000ED08 ) ) +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) + +/* Constants required to check the validity of an interrupt priority. */ +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) + +/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */ +#define portVECTACTIVE_MASK ( 0xFFUL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) + +/* The systick is a 24-bit counter. */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/* A fiddle factor to estimate the number of SysTick counts that would have + * occurred while the SysTick counter is stopped during tickless idle + * calculations. */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) + +/* For strict compliance with the Cortex-M spec the task start address should + * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */ +#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL ) + +/* Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ); + +/* + * Exception handlers. + */ +void xPortSysTickHandler( void ); + +/* + * Start first task is a separate function so it can be tested in isolation. + */ +extern void vPortStartFirstTask( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/* + * FreeRTOS handlers implemented in assembly. + */ +extern void vPortSVCHandler( void ); +extern void xPortPendSVHandler( void ); +/*-----------------------------------------------------------*/ + +/* Each task maintains its own interrupt status in the critical nesting + * variable. */ +static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +/* + * The number of SysTick increments that make up one tick period. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulTimerCountsForOneTick = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * The maximum number of tick periods that can be suppressed is limited by the + * 24 bit resolution of the SysTick timer. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t xMaximumPossibleSuppressedTicks = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Compensate for the CPU cycles that pass while the SysTick is stopped (low + * power functionality only. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( configASSERT_DEFINED == 1 ) + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16; +#endif /* configASSERT_DEFINED */ + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ + configASSERT( uxCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions vPortSVCHandler and + * xPortPendSVHandler for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * vPortSVCHandler and xPortPendSVHandler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( configASSERT_DEFINED == 1 ) + { + volatile uint8_t ucOriginalPriority; + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * Save the interrupt priority value that is about to be clobbered. */ + ucOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to all + * possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + + /* Restore the clobbered interrupt priority register to its original + * value. */ + *pucFirstUserPriorityRegister = ucOriginalPriority; + } + #endif /* configASSERT_DEFINED */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ + if( uxCriticalNesting == 1 ) + { + configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + /* The SysTick runs at the lowest interrupt priority, so when this interrupt + * executes all interrupts must be unmasked. There is therefore no need to + * save and then restore the interrupt mask value as its value is already + * known. */ + portDISABLE_INTERRUPTS(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + + /* A context switch is required. Context switching is performed in + * the PendSV interrupt. Pend the PendSV interrupt. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + portENABLE_INTERRUPTS(); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __disable_interrupt(); + __DSB(); + __ISB(); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the __disable_interrupt() + * call above. */ + __enable_interrupt(); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __DSB(); + __WFI(); + __ISB(); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the __disable_interrupt() call above. */ + __enable_interrupt(); + __DSB(); + __ISB(); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __disable_interrupt(); + __DSB(); + __ISB(); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __enable_interrupt(); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +__weak void vPortSetupTimerInterrupt( void ) +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and clear the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); +} +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* configASSERT_DEFINED */ diff --git a/portable/IAR/ARM_CM3/portasm.s b/portable/IAR/ARM_CM3/portasm.s new file mode 100644 index 000000000..7b2afde98 --- /dev/null +++ b/portable/IAR/ARM_CM3/portasm.s @@ -0,0 +1,104 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include + + RSEG CODE:CODE(2) + thumb + + EXTERN pxCurrentTCB + EXTERN vTaskSwitchContext + + PUBLIC xPortPendSVHandler + PUBLIC vPortSVCHandler + PUBLIC vPortStartFirstTask + + + +/*-----------------------------------------------------------*/ + +xPortPendSVHandler: + mrs r0, psp + isb + ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */ + ldr r2, [r3] + + stmdb r0!, {r4-r11} /* Save the remaining registers. */ + str r0, [r2] /* Save the new top of stack into the first member of the TCB. */ + + stmdb sp!, {r3, r14} + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 + dsb + isb + bl vTaskSwitchContext + mov r0, #0 + msr basepri, r0 + ldmia sp!, {r3, r14} + + ldr r1, [r3] + ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */ + ldmia r0!, {r4-r11} /* Pop the registers. */ + msr psp, r0 + isb + bx r14 + + +/*-----------------------------------------------------------*/ + +vPortSVCHandler: + /* Get the location of the current TCB. */ + ldr r3, =pxCurrentTCB + ldr r1, [r3] + ldr r0, [r1] + /* Pop the core registers. */ + ldmia r0!, {r4-r11} + msr psp, r0 + isb + mov r0, #0 + msr basepri, r0 + orr r14, r14, #13 + bx r14 + +/*-----------------------------------------------------------*/ + +vPortStartFirstTask + /* Use the NVIC offset register to locate the stack. */ + ldr r0, =0xE000ED08 + ldr r0, [r0] + ldr r0, [r0] + /* Set the msp back to the start of the stack. */ + msr msp, r0 + /* Call SVC to start the first task, ensuring interrupts are enabled. */ + cpsie i + cpsie f + dsb + isb + svc 0 + + END diff --git a/portable/IAR/ARM_CM3/portmacro.h b/portable/IAR/ARM_CM3/portmacro.h new file mode 100644 index 000000000..f49c618c4 --- /dev/null +++ b/portable/IAR/ARM_CM3/portmacro.h @@ -0,0 +1,226 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* IAR includes. */ +#include + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +/*-----------------------------------------------------------*/ + +/* Compiler directives. */ +#define portWEAK_SYMBOL __attribute__( ( weak ) ) + +/*-----------------------------------------------------------*/ + + +/* Scheduler utilities. */ +#define portYIELD() \ + { \ + /* Set a PendSV to request a context switch. */ \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + __DSB(); \ + __ISB(); \ + } + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portYIELD(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) + +/*-----------------------------------------------------------*/ + +/* Architecture specific optimisations. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portDISABLE_INTERRUPTS() \ + { \ + __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \ + __DSB(); \ + __ISB(); \ + } + +#define portENABLE_INTERRUPTS() __set_BASEPRI( 0 ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +#define portSET_INTERRUPT_MASK_FROM_ISR() __get_BASEPRI(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) __set_BASEPRI( x ) +/*-----------------------------------------------------------*/ + +/* Tickless idle/low power functionality. */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not necessary for to use this port. They are defined so the common demo files + * (which build with all the ports) will build. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif + +/* portNOP() is not required by this port. */ +#define portNOP() + +#define portINLINE __inline + +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif + +/*-----------------------------------------------------------*/ + +portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} + +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ +#pragma diag_suppress=Pe191 +#pragma diag_suppress=Pa082 + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/IAR/ARM_CM33/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM33/non_secure/mpu_wrappers_v2_asm.S new file mode 100644 index 000000000..d2cb78e92 --- /dev/null +++ b/portable/IAR/ARM_CM33/non_secure/mpu_wrappers_v2_asm.S @@ -0,0 +1,1242 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + + SECTION freertos_system_calls:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +#include "FreeRTOSConfig.h" +#include "mpu_syscall_numbers.h" + +#ifndef configUSE_MPU_WRAPPERS_V1 + #define configUSE_MPU_WRAPPERS_V1 0 +#endif + +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + PUBLIC MPU_xTaskDelayUntil +MPU_xTaskDelayUntil: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskDelayUntil_Unpriv + MPU_xTaskDelayUntil_Priv: + b MPU_xTaskDelayUntilImpl + MPU_xTaskDelayUntil_Unpriv: + svc #SYSTEM_CALL_xTaskDelayUntil +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskAbortDelay +MPU_xTaskAbortDelay: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskAbortDelay_Unpriv + MPU_xTaskAbortDelay_Priv: + b MPU_xTaskAbortDelayImpl + MPU_xTaskAbortDelay_Unpriv: + svc #SYSTEM_CALL_xTaskAbortDelay +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskDelay +MPU_vTaskDelay: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskDelay_Unpriv + MPU_vTaskDelay_Priv: + b MPU_vTaskDelayImpl + MPU_vTaskDelay_Unpriv: + svc #SYSTEM_CALL_vTaskDelay +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskPriorityGet +MPU_uxTaskPriorityGet: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskPriorityGet_Unpriv + MPU_uxTaskPriorityGet_Priv: + b MPU_uxTaskPriorityGetImpl + MPU_uxTaskPriorityGet_Unpriv: + svc #SYSTEM_CALL_uxTaskPriorityGet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_eTaskGetState +MPU_eTaskGetState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_eTaskGetState_Unpriv + MPU_eTaskGetState_Priv: + b MPU_eTaskGetStateImpl + MPU_eTaskGetState_Unpriv: + svc #SYSTEM_CALL_eTaskGetState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskGetInfo +MPU_vTaskGetInfo: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskGetInfo_Unpriv + MPU_vTaskGetInfo_Priv: + b MPU_vTaskGetInfoImpl + MPU_vTaskGetInfo_Unpriv: + svc #SYSTEM_CALL_vTaskGetInfo +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetIdleTaskHandle +MPU_xTaskGetIdleTaskHandle: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetIdleTaskHandle_Unpriv + MPU_xTaskGetIdleTaskHandle_Priv: + b MPU_xTaskGetIdleTaskHandleImpl + MPU_xTaskGetIdleTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTaskGetIdleTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSuspend +MPU_vTaskSuspend: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSuspend_Unpriv + MPU_vTaskSuspend_Priv: + b MPU_vTaskSuspendImpl + MPU_vTaskSuspend_Unpriv: + svc #SYSTEM_CALL_vTaskSuspend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskResume +MPU_vTaskResume: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskResume_Unpriv + MPU_vTaskResume_Priv: + b MPU_vTaskResumeImpl + MPU_vTaskResume_Unpriv: + svc #SYSTEM_CALL_vTaskResume +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetTickCount +MPU_xTaskGetTickCount: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetTickCount_Unpriv + MPU_xTaskGetTickCount_Priv: + b MPU_xTaskGetTickCountImpl + MPU_xTaskGetTickCount_Unpriv: + svc #SYSTEM_CALL_xTaskGetTickCount +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetNumberOfTasks +MPU_uxTaskGetNumberOfTasks: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetNumberOfTasks_Unpriv + MPU_uxTaskGetNumberOfTasks_Priv: + b MPU_uxTaskGetNumberOfTasksImpl + MPU_uxTaskGetNumberOfTasks_Unpriv: + svc #SYSTEM_CALL_uxTaskGetNumberOfTasks +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetRunTimeCounter +MPU_ulTaskGetRunTimeCounter: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetRunTimeCounter_Unpriv + MPU_ulTaskGetRunTimeCounter_Priv: + b MPU_ulTaskGetRunTimeCounterImpl + MPU_ulTaskGetRunTimeCounter_Unpriv: + svc #SYSTEM_CALL_ulTaskGetRunTimeCounter +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetRunTimePercent +MPU_ulTaskGetRunTimePercent: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetRunTimePercent_Unpriv + MPU_ulTaskGetRunTimePercent_Priv: + b MPU_ulTaskGetRunTimePercentImpl + MPU_ulTaskGetRunTimePercent_Unpriv: + svc #SYSTEM_CALL_ulTaskGetRunTimePercent +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetIdleRunTimePercent +MPU_ulTaskGetIdleRunTimePercent: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetIdleRunTimePercent_Unpriv + MPU_ulTaskGetIdleRunTimePercent_Priv: + b MPU_ulTaskGetIdleRunTimePercentImpl + MPU_ulTaskGetIdleRunTimePercent_Unpriv: + svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetIdleRunTimeCounter +MPU_ulTaskGetIdleRunTimeCounter: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv + MPU_ulTaskGetIdleRunTimeCounter_Priv: + b MPU_ulTaskGetIdleRunTimeCounterImpl + MPU_ulTaskGetIdleRunTimeCounter_Unpriv: + svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetApplicationTaskTag +MPU_vTaskSetApplicationTaskTag: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetApplicationTaskTag_Unpriv + MPU_vTaskSetApplicationTaskTag_Priv: + b MPU_vTaskSetApplicationTaskTagImpl + MPU_vTaskSetApplicationTaskTag_Unpriv: + svc #SYSTEM_CALL_vTaskSetApplicationTaskTag +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetApplicationTaskTag +MPU_xTaskGetApplicationTaskTag: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetApplicationTaskTag_Unpriv + MPU_xTaskGetApplicationTaskTag_Priv: + b MPU_xTaskGetApplicationTaskTagImpl + MPU_xTaskGetApplicationTaskTag_Unpriv: + svc #SYSTEM_CALL_xTaskGetApplicationTaskTag +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetThreadLocalStoragePointer +MPU_vTaskSetThreadLocalStoragePointer: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv + MPU_vTaskSetThreadLocalStoragePointer_Priv: + b MPU_vTaskSetThreadLocalStoragePointerImpl + MPU_vTaskSetThreadLocalStoragePointer_Unpriv: + svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pvTaskGetThreadLocalStoragePointer +MPU_pvTaskGetThreadLocalStoragePointer: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv + MPU_pvTaskGetThreadLocalStoragePointer_Priv: + b MPU_pvTaskGetThreadLocalStoragePointerImpl + MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: + svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetSystemState +MPU_uxTaskGetSystemState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetSystemState_Unpriv + MPU_uxTaskGetSystemState_Priv: + b MPU_uxTaskGetSystemStateImpl + MPU_uxTaskGetSystemState_Unpriv: + svc #SYSTEM_CALL_uxTaskGetSystemState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetStackHighWaterMark +MPU_uxTaskGetStackHighWaterMark: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetStackHighWaterMark_Unpriv + MPU_uxTaskGetStackHighWaterMark_Priv: + b MPU_uxTaskGetStackHighWaterMarkImpl + MPU_uxTaskGetStackHighWaterMark_Unpriv: + svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetStackHighWaterMark2 +MPU_uxTaskGetStackHighWaterMark2: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetStackHighWaterMark2_Unpriv + MPU_uxTaskGetStackHighWaterMark2_Priv: + b MPU_uxTaskGetStackHighWaterMark2Impl + MPU_uxTaskGetStackHighWaterMark2_Unpriv: + svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2 +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetCurrentTaskHandle +MPU_xTaskGetCurrentTaskHandle: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetCurrentTaskHandle_Unpriv + MPU_xTaskGetCurrentTaskHandle_Priv: + b MPU_xTaskGetCurrentTaskHandleImpl + MPU_xTaskGetCurrentTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetSchedulerState +MPU_xTaskGetSchedulerState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetSchedulerState_Unpriv + MPU_xTaskGetSchedulerState_Priv: + b MPU_xTaskGetSchedulerStateImpl + MPU_xTaskGetSchedulerState_Unpriv: + svc #SYSTEM_CALL_xTaskGetSchedulerState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetTimeOutState +MPU_vTaskSetTimeOutState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetTimeOutState_Unpriv + MPU_vTaskSetTimeOutState_Priv: + b MPU_vTaskSetTimeOutStateImpl + MPU_vTaskSetTimeOutState_Unpriv: + svc #SYSTEM_CALL_vTaskSetTimeOutState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskCheckForTimeOut +MPU_xTaskCheckForTimeOut: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskCheckForTimeOut_Unpriv + MPU_xTaskCheckForTimeOut_Priv: + b MPU_xTaskCheckForTimeOutImpl + MPU_xTaskCheckForTimeOut_Unpriv: + svc #SYSTEM_CALL_xTaskCheckForTimeOut +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyEntry +MPU_xTaskGenericNotifyEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotify_Unpriv + MPU_xTaskGenericNotify_Priv: + b MPU_xTaskGenericNotifyImpl + MPU_xTaskGenericNotify_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotify +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyWaitEntry +MPU_xTaskGenericNotifyWaitEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotifyWait_Unpriv + MPU_xTaskGenericNotifyWait_Priv: + b MPU_xTaskGenericNotifyWaitImpl + MPU_xTaskGenericNotifyWait_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotifyWait +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGenericNotifyTake +MPU_ulTaskGenericNotifyTake: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGenericNotifyTake_Unpriv + MPU_ulTaskGenericNotifyTake_Priv: + b MPU_ulTaskGenericNotifyTakeImpl + MPU_ulTaskGenericNotifyTake_Unpriv: + svc #SYSTEM_CALL_ulTaskGenericNotifyTake +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyStateClear +MPU_xTaskGenericNotifyStateClear: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotifyStateClear_Unpriv + MPU_xTaskGenericNotifyStateClear_Priv: + b MPU_xTaskGenericNotifyStateClearImpl + MPU_xTaskGenericNotifyStateClear_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotifyStateClear +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGenericNotifyValueClear +MPU_ulTaskGenericNotifyValueClear: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGenericNotifyValueClear_Unpriv + MPU_ulTaskGenericNotifyValueClear_Priv: + b MPU_ulTaskGenericNotifyValueClearImpl + MPU_ulTaskGenericNotifyValueClear_Unpriv: + svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGenericSend +MPU_xQueueGenericSend: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGenericSend_Unpriv + MPU_xQueueGenericSend_Priv: + b MPU_xQueueGenericSendImpl + MPU_xQueueGenericSend_Unpriv: + svc #SYSTEM_CALL_xQueueGenericSend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxQueueMessagesWaiting +MPU_uxQueueMessagesWaiting: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxQueueMessagesWaiting_Unpriv + MPU_uxQueueMessagesWaiting_Priv: + b MPU_uxQueueMessagesWaitingImpl + MPU_uxQueueMessagesWaiting_Unpriv: + svc #SYSTEM_CALL_uxQueueMessagesWaiting +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxQueueSpacesAvailable +MPU_uxQueueSpacesAvailable: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxQueueSpacesAvailable_Unpriv + MPU_uxQueueSpacesAvailable_Priv: + b MPU_uxQueueSpacesAvailableImpl + MPU_uxQueueSpacesAvailable_Unpriv: + svc #SYSTEM_CALL_uxQueueSpacesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueReceive +MPU_xQueueReceive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueReceive_Unpriv + MPU_xQueueReceive_Priv: + b MPU_xQueueReceiveImpl + MPU_xQueueReceive_Unpriv: + svc #SYSTEM_CALL_xQueueReceive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueuePeek +MPU_xQueuePeek: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueuePeek_Unpriv + MPU_xQueuePeek_Priv: + b MPU_xQueuePeekImpl + MPU_xQueuePeek_Unpriv: + svc #SYSTEM_CALL_xQueuePeek +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueSemaphoreTake +MPU_xQueueSemaphoreTake: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueSemaphoreTake_Unpriv + MPU_xQueueSemaphoreTake_Priv: + b MPU_xQueueSemaphoreTakeImpl + MPU_xQueueSemaphoreTake_Unpriv: + svc #SYSTEM_CALL_xQueueSemaphoreTake +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGetMutexHolder +MPU_xQueueGetMutexHolder: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGetMutexHolder_Unpriv + MPU_xQueueGetMutexHolder_Priv: + b MPU_xQueueGetMutexHolderImpl + MPU_xQueueGetMutexHolder_Unpriv: + svc #SYSTEM_CALL_xQueueGetMutexHolder +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueTakeMutexRecursive +MPU_xQueueTakeMutexRecursive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueTakeMutexRecursive_Unpriv + MPU_xQueueTakeMutexRecursive_Priv: + b MPU_xQueueTakeMutexRecursiveImpl + MPU_xQueueTakeMutexRecursive_Unpriv: + svc #SYSTEM_CALL_xQueueTakeMutexRecursive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGiveMutexRecursive +MPU_xQueueGiveMutexRecursive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGiveMutexRecursive_Unpriv + MPU_xQueueGiveMutexRecursive_Priv: + b MPU_xQueueGiveMutexRecursiveImpl + MPU_xQueueGiveMutexRecursive_Unpriv: + svc #SYSTEM_CALL_xQueueGiveMutexRecursive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueSelectFromSet +MPU_xQueueSelectFromSet: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueSelectFromSet_Unpriv + MPU_xQueueSelectFromSet_Priv: + b MPU_xQueueSelectFromSetImpl + MPU_xQueueSelectFromSet_Unpriv: + svc #SYSTEM_CALL_xQueueSelectFromSet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueAddToSet +MPU_xQueueAddToSet: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueAddToSet_Unpriv + MPU_xQueueAddToSet_Priv: + b MPU_xQueueAddToSetImpl + MPU_xQueueAddToSet_Unpriv: + svc #SYSTEM_CALL_xQueueAddToSet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vQueueAddToRegistry +MPU_vQueueAddToRegistry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vQueueAddToRegistry_Unpriv + MPU_vQueueAddToRegistry_Priv: + b MPU_vQueueAddToRegistryImpl + MPU_vQueueAddToRegistry_Unpriv: + svc #SYSTEM_CALL_vQueueAddToRegistry +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vQueueUnregisterQueue +MPU_vQueueUnregisterQueue: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vQueueUnregisterQueue_Unpriv + MPU_vQueueUnregisterQueue_Priv: + b MPU_vQueueUnregisterQueueImpl + MPU_vQueueUnregisterQueue_Unpriv: + svc #SYSTEM_CALL_vQueueUnregisterQueue +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pcQueueGetName +MPU_pcQueueGetName: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pcQueueGetName_Unpriv + MPU_pcQueueGetName_Priv: + b MPU_pcQueueGetNameImpl + MPU_pcQueueGetName_Unpriv: + svc #SYSTEM_CALL_pcQueueGetName +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pvTimerGetTimerID +MPU_pvTimerGetTimerID: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pvTimerGetTimerID_Unpriv + MPU_pvTimerGetTimerID_Priv: + b MPU_pvTimerGetTimerIDImpl + MPU_pvTimerGetTimerID_Unpriv: + svc #SYSTEM_CALL_pvTimerGetTimerID +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTimerSetTimerID +MPU_vTimerSetTimerID: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTimerSetTimerID_Unpriv + MPU_vTimerSetTimerID_Priv: + b MPU_vTimerSetTimerIDImpl + MPU_vTimerSetTimerID_Unpriv: + svc #SYSTEM_CALL_vTimerSetTimerID +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerIsTimerActive +MPU_xTimerIsTimerActive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerIsTimerActive_Unpriv + MPU_xTimerIsTimerActive_Priv: + b MPU_xTimerIsTimerActiveImpl + MPU_xTimerIsTimerActive_Unpriv: + svc #SYSTEM_CALL_xTimerIsTimerActive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetTimerDaemonTaskHandle +MPU_xTimerGetTimerDaemonTaskHandle: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv + MPU_xTimerGetTimerDaemonTaskHandle_Priv: + b MPU_xTimerGetTimerDaemonTaskHandleImpl + MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGenericCommandFromTaskEntry +MPU_xTimerGenericCommandFromTaskEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGenericCommandFromTask_Unpriv + MPU_xTimerGenericCommandFromTask_Priv: + b MPU_xTimerGenericCommandFromTaskImpl + MPU_xTimerGenericCommandFromTask_Unpriv: + svc #SYSTEM_CALL_xTimerGenericCommandFromTask +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pcTimerGetName +MPU_pcTimerGetName: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pcTimerGetName_Unpriv + MPU_pcTimerGetName_Priv: + b MPU_pcTimerGetNameImpl + MPU_pcTimerGetName_Unpriv: + svc #SYSTEM_CALL_pcTimerGetName +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTimerSetReloadMode +MPU_vTimerSetReloadMode: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTimerSetReloadMode_Unpriv + MPU_vTimerSetReloadMode_Priv: + b MPU_vTimerSetReloadModeImpl + MPU_vTimerSetReloadMode_Unpriv: + svc #SYSTEM_CALL_vTimerSetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetReloadMode +MPU_xTimerGetReloadMode: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetReloadMode_Unpriv + MPU_xTimerGetReloadMode_Priv: + b MPU_xTimerGetReloadModeImpl + MPU_xTimerGetReloadMode_Unpriv: + svc #SYSTEM_CALL_xTimerGetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTimerGetReloadMode +MPU_uxTimerGetReloadMode: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTimerGetReloadMode_Unpriv + MPU_uxTimerGetReloadMode_Priv: + b MPU_uxTimerGetReloadModeImpl + MPU_uxTimerGetReloadMode_Unpriv: + svc #SYSTEM_CALL_uxTimerGetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetPeriod +MPU_xTimerGetPeriod: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetPeriod_Unpriv + MPU_xTimerGetPeriod_Priv: + b MPU_xTimerGetPeriodImpl + MPU_xTimerGetPeriod_Unpriv: + svc #SYSTEM_CALL_xTimerGetPeriod +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetExpiryTime +MPU_xTimerGetExpiryTime: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetExpiryTime_Unpriv + MPU_xTimerGetExpiryTime_Priv: + b MPU_xTimerGetExpiryTimeImpl + MPU_xTimerGetExpiryTime_Unpriv: + svc #SYSTEM_CALL_xTimerGetExpiryTime +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupWaitBitsEntry +MPU_xEventGroupWaitBitsEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupWaitBits_Unpriv + MPU_xEventGroupWaitBits_Priv: + b MPU_xEventGroupWaitBitsImpl + MPU_xEventGroupWaitBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupWaitBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupClearBits +MPU_xEventGroupClearBits: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupClearBits_Unpriv + MPU_xEventGroupClearBits_Priv: + b MPU_xEventGroupClearBitsImpl + MPU_xEventGroupClearBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupClearBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupSetBits +MPU_xEventGroupSetBits: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupSetBits_Unpriv + MPU_xEventGroupSetBits_Priv: + b MPU_xEventGroupSetBitsImpl + MPU_xEventGroupSetBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupSetBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupSync +MPU_xEventGroupSync: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupSync_Unpriv + MPU_xEventGroupSync_Priv: + b MPU_xEventGroupSyncImpl + MPU_xEventGroupSync_Unpriv: + svc #SYSTEM_CALL_xEventGroupSync +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxEventGroupGetNumber +MPU_uxEventGroupGetNumber: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxEventGroupGetNumber_Unpriv + MPU_uxEventGroupGetNumber_Priv: + b MPU_uxEventGroupGetNumberImpl + MPU_uxEventGroupGetNumber_Unpriv: + svc #SYSTEM_CALL_uxEventGroupGetNumber +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vEventGroupSetNumber +MPU_vEventGroupSetNumber: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vEventGroupSetNumber_Unpriv + MPU_vEventGroupSetNumber_Priv: + b MPU_vEventGroupSetNumberImpl + MPU_vEventGroupSetNumber_Unpriv: + svc #SYSTEM_CALL_vEventGroupSetNumber +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSend +MPU_xStreamBufferSend: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSend_Unpriv + MPU_xStreamBufferSend_Priv: + b MPU_xStreamBufferSendImpl + MPU_xStreamBufferSend_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferReceive +MPU_xStreamBufferReceive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferReceive_Unpriv + MPU_xStreamBufferReceive_Priv: + b MPU_xStreamBufferReceiveImpl + MPU_xStreamBufferReceive_Unpriv: + svc #SYSTEM_CALL_xStreamBufferReceive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferIsFull +MPU_xStreamBufferIsFull: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferIsFull_Unpriv + MPU_xStreamBufferIsFull_Priv: + b MPU_xStreamBufferIsFullImpl + MPU_xStreamBufferIsFull_Unpriv: + svc #SYSTEM_CALL_xStreamBufferIsFull +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferIsEmpty +MPU_xStreamBufferIsEmpty: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferIsEmpty_Unpriv + MPU_xStreamBufferIsEmpty_Priv: + b MPU_xStreamBufferIsEmptyImpl + MPU_xStreamBufferIsEmpty_Unpriv: + svc #SYSTEM_CALL_xStreamBufferIsEmpty +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSpacesAvailable +MPU_xStreamBufferSpacesAvailable: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSpacesAvailable_Unpriv + MPU_xStreamBufferSpacesAvailable_Priv: + b MPU_xStreamBufferSpacesAvailableImpl + MPU_xStreamBufferSpacesAvailable_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSpacesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferBytesAvailable +MPU_xStreamBufferBytesAvailable: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferBytesAvailable_Unpriv + MPU_xStreamBufferBytesAvailable_Priv: + b MPU_xStreamBufferBytesAvailableImpl + MPU_xStreamBufferBytesAvailable_Unpriv: + svc #SYSTEM_CALL_xStreamBufferBytesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSetTriggerLevel +MPU_xStreamBufferSetTriggerLevel: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSetTriggerLevel_Unpriv + MPU_xStreamBufferSetTriggerLevel_Priv: + b MPU_xStreamBufferSetTriggerLevelImpl + MPU_xStreamBufferSetTriggerLevel_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferNextMessageLengthBytes +MPU_xStreamBufferNextMessageLengthBytes: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv + MPU_xStreamBufferNextMessageLengthBytes_Priv: + b MPU_xStreamBufferNextMessageLengthBytesImpl + MPU_xStreamBufferNextMessageLengthBytes_Unpriv: + svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes +/*-----------------------------------------------------------*/ + +/* Default weak implementations in case one is not available from + * mpu_wrappers because of config options. */ + + PUBWEAK MPU_xTaskDelayUntilImpl +MPU_xTaskDelayUntilImpl: + b MPU_xTaskDelayUntilImpl + + PUBWEAK MPU_xTaskAbortDelayImpl +MPU_xTaskAbortDelayImpl: + b MPU_xTaskAbortDelayImpl + + PUBWEAK MPU_vTaskDelayImpl +MPU_vTaskDelayImpl: + b MPU_vTaskDelayImpl + + PUBWEAK MPU_uxTaskPriorityGetImpl +MPU_uxTaskPriorityGetImpl: + b MPU_uxTaskPriorityGetImpl + + PUBWEAK MPU_eTaskGetStateImpl +MPU_eTaskGetStateImpl: + b MPU_eTaskGetStateImpl + + PUBWEAK MPU_vTaskGetInfoImpl +MPU_vTaskGetInfoImpl: + b MPU_vTaskGetInfoImpl + + PUBWEAK MPU_xTaskGetIdleTaskHandleImpl +MPU_xTaskGetIdleTaskHandleImpl: + b MPU_xTaskGetIdleTaskHandleImpl + + PUBWEAK MPU_vTaskSuspendImpl +MPU_vTaskSuspendImpl: + b MPU_vTaskSuspendImpl + + PUBWEAK MPU_vTaskResumeImpl +MPU_vTaskResumeImpl: + b MPU_vTaskResumeImpl + + PUBWEAK MPU_xTaskGetTickCountImpl +MPU_xTaskGetTickCountImpl: + b MPU_xTaskGetTickCountImpl + + PUBWEAK MPU_uxTaskGetNumberOfTasksImpl +MPU_uxTaskGetNumberOfTasksImpl: + b MPU_uxTaskGetNumberOfTasksImpl + + PUBWEAK MPU_ulTaskGetRunTimeCounterImpl +MPU_ulTaskGetRunTimeCounterImpl: + b MPU_ulTaskGetRunTimeCounterImpl + + PUBWEAK MPU_ulTaskGetRunTimePercentImpl +MPU_ulTaskGetRunTimePercentImpl: + b MPU_ulTaskGetRunTimePercentImpl + + PUBWEAK MPU_ulTaskGetIdleRunTimePercentImpl +MPU_ulTaskGetIdleRunTimePercentImpl: + b MPU_ulTaskGetIdleRunTimePercentImpl + + PUBWEAK MPU_ulTaskGetIdleRunTimeCounterImpl +MPU_ulTaskGetIdleRunTimeCounterImpl: + b MPU_ulTaskGetIdleRunTimeCounterImpl + + PUBWEAK MPU_vTaskSetApplicationTaskTagImpl +MPU_vTaskSetApplicationTaskTagImpl: + b MPU_vTaskSetApplicationTaskTagImpl + + PUBWEAK MPU_xTaskGetApplicationTaskTagImpl +MPU_xTaskGetApplicationTaskTagImpl: + b MPU_xTaskGetApplicationTaskTagImpl + + PUBWEAK MPU_vTaskSetThreadLocalStoragePointerImpl +MPU_vTaskSetThreadLocalStoragePointerImpl: + b MPU_vTaskSetThreadLocalStoragePointerImpl + + PUBWEAK MPU_pvTaskGetThreadLocalStoragePointerImpl +MPU_pvTaskGetThreadLocalStoragePointerImpl: + b MPU_pvTaskGetThreadLocalStoragePointerImpl + + PUBWEAK MPU_uxTaskGetSystemStateImpl +MPU_uxTaskGetSystemStateImpl: + b MPU_uxTaskGetSystemStateImpl + + PUBWEAK MPU_uxTaskGetStackHighWaterMarkImpl +MPU_uxTaskGetStackHighWaterMarkImpl: + b MPU_uxTaskGetStackHighWaterMarkImpl + + PUBWEAK MPU_uxTaskGetStackHighWaterMark2Impl +MPU_uxTaskGetStackHighWaterMark2Impl: + b MPU_uxTaskGetStackHighWaterMark2Impl + + PUBWEAK MPU_xTaskGetCurrentTaskHandleImpl +MPU_xTaskGetCurrentTaskHandleImpl: + b MPU_xTaskGetCurrentTaskHandleImpl + + PUBWEAK MPU_xTaskGetSchedulerStateImpl +MPU_xTaskGetSchedulerStateImpl: + b MPU_xTaskGetSchedulerStateImpl + + PUBWEAK MPU_vTaskSetTimeOutStateImpl +MPU_vTaskSetTimeOutStateImpl: + b MPU_vTaskSetTimeOutStateImpl + + PUBWEAK MPU_xTaskCheckForTimeOutImpl +MPU_xTaskCheckForTimeOutImpl: + b MPU_xTaskCheckForTimeOutImpl + + PUBWEAK MPU_xTaskGenericNotifyImpl +MPU_xTaskGenericNotifyImpl: + b MPU_xTaskGenericNotifyImpl + + PUBWEAK MPU_xTaskGenericNotifyWaitImpl +MPU_xTaskGenericNotifyWaitImpl: + b MPU_xTaskGenericNotifyWaitImpl + + PUBWEAK MPU_ulTaskGenericNotifyTakeImpl +MPU_ulTaskGenericNotifyTakeImpl: + b MPU_ulTaskGenericNotifyTakeImpl + + PUBWEAK MPU_xTaskGenericNotifyStateClearImpl +MPU_xTaskGenericNotifyStateClearImpl: + b MPU_xTaskGenericNotifyStateClearImpl + + PUBWEAK MPU_ulTaskGenericNotifyValueClearImpl +MPU_ulTaskGenericNotifyValueClearImpl: + b MPU_ulTaskGenericNotifyValueClearImpl + + PUBWEAK MPU_xQueueGenericSendImpl +MPU_xQueueGenericSendImpl: + b MPU_xQueueGenericSendImpl + + PUBWEAK MPU_uxQueueMessagesWaitingImpl +MPU_uxQueueMessagesWaitingImpl: + b MPU_uxQueueMessagesWaitingImpl + + PUBWEAK MPU_uxQueueSpacesAvailableImpl +MPU_uxQueueSpacesAvailableImpl: + b MPU_uxQueueSpacesAvailableImpl + + PUBWEAK MPU_xQueueReceiveImpl +MPU_xQueueReceiveImpl: + b MPU_xQueueReceiveImpl + + PUBWEAK MPU_xQueuePeekImpl +MPU_xQueuePeekImpl: + b MPU_xQueuePeekImpl + + PUBWEAK MPU_xQueueSemaphoreTakeImpl +MPU_xQueueSemaphoreTakeImpl: + b MPU_xQueueSemaphoreTakeImpl + + PUBWEAK MPU_xQueueGetMutexHolderImpl +MPU_xQueueGetMutexHolderImpl: + b MPU_xQueueGetMutexHolderImpl + + PUBWEAK MPU_xQueueTakeMutexRecursiveImpl +MPU_xQueueTakeMutexRecursiveImpl: + b MPU_xQueueTakeMutexRecursiveImpl + + PUBWEAK MPU_xQueueGiveMutexRecursiveImpl +MPU_xQueueGiveMutexRecursiveImpl: + b MPU_xQueueGiveMutexRecursiveImpl + + PUBWEAK MPU_xQueueSelectFromSetImpl +MPU_xQueueSelectFromSetImpl: + b MPU_xQueueSelectFromSetImpl + + PUBWEAK MPU_xQueueAddToSetImpl +MPU_xQueueAddToSetImpl: + b MPU_xQueueAddToSetImpl + + PUBWEAK MPU_vQueueAddToRegistryImpl +MPU_vQueueAddToRegistryImpl: + b MPU_vQueueAddToRegistryImpl + + PUBWEAK MPU_vQueueUnregisterQueueImpl +MPU_vQueueUnregisterQueueImpl: + b MPU_vQueueUnregisterQueueImpl + + PUBWEAK MPU_pcQueueGetNameImpl +MPU_pcQueueGetNameImpl: + b MPU_pcQueueGetNameImpl + + PUBWEAK MPU_pvTimerGetTimerIDImpl +MPU_pvTimerGetTimerIDImpl: + b MPU_pvTimerGetTimerIDImpl + + PUBWEAK MPU_vTimerSetTimerIDImpl +MPU_vTimerSetTimerIDImpl: + b MPU_vTimerSetTimerIDImpl + + PUBWEAK MPU_xTimerIsTimerActiveImpl +MPU_xTimerIsTimerActiveImpl: + b MPU_xTimerIsTimerActiveImpl + + PUBWEAK MPU_xTimerGetTimerDaemonTaskHandleImpl +MPU_xTimerGetTimerDaemonTaskHandleImpl: + b MPU_xTimerGetTimerDaemonTaskHandleImpl + + PUBWEAK MPU_xTimerGenericCommandFromTaskImpl +MPU_xTimerGenericCommandFromTaskImpl: + b MPU_xTimerGenericCommandFromTaskImpl + + PUBWEAK MPU_pcTimerGetNameImpl +MPU_pcTimerGetNameImpl: + b MPU_pcTimerGetNameImpl + + PUBWEAK MPU_vTimerSetReloadModeImpl +MPU_vTimerSetReloadModeImpl: + b MPU_vTimerSetReloadModeImpl + + PUBWEAK MPU_xTimerGetReloadModeImpl +MPU_xTimerGetReloadModeImpl: + b MPU_xTimerGetReloadModeImpl + + PUBWEAK MPU_uxTimerGetReloadModeImpl +MPU_uxTimerGetReloadModeImpl: + b MPU_uxTimerGetReloadModeImpl + + PUBWEAK MPU_xTimerGetPeriodImpl +MPU_xTimerGetPeriodImpl: + b MPU_xTimerGetPeriodImpl + + PUBWEAK MPU_xTimerGetExpiryTimeImpl +MPU_xTimerGetExpiryTimeImpl: + b MPU_xTimerGetExpiryTimeImpl + + PUBWEAK MPU_xEventGroupWaitBitsImpl +MPU_xEventGroupWaitBitsImpl: + b MPU_xEventGroupWaitBitsImpl + + PUBWEAK MPU_xEventGroupClearBitsImpl +MPU_xEventGroupClearBitsImpl: + b MPU_xEventGroupClearBitsImpl + + PUBWEAK MPU_xEventGroupSetBitsImpl +MPU_xEventGroupSetBitsImpl: + b MPU_xEventGroupSetBitsImpl + + PUBWEAK MPU_xEventGroupSyncImpl +MPU_xEventGroupSyncImpl: + b MPU_xEventGroupSyncImpl + + PUBWEAK MPU_uxEventGroupGetNumberImpl +MPU_uxEventGroupGetNumberImpl: + b MPU_uxEventGroupGetNumberImpl + + PUBWEAK MPU_vEventGroupSetNumberImpl +MPU_vEventGroupSetNumberImpl: + b MPU_vEventGroupSetNumberImpl + + PUBWEAK MPU_xStreamBufferSendImpl +MPU_xStreamBufferSendImpl: + b MPU_xStreamBufferSendImpl + + PUBWEAK MPU_xStreamBufferReceiveImpl +MPU_xStreamBufferReceiveImpl: + b MPU_xStreamBufferReceiveImpl + + PUBWEAK MPU_xStreamBufferIsFullImpl +MPU_xStreamBufferIsFullImpl: + b MPU_xStreamBufferIsFullImpl + + PUBWEAK MPU_xStreamBufferIsEmptyImpl +MPU_xStreamBufferIsEmptyImpl: + b MPU_xStreamBufferIsEmptyImpl + + PUBWEAK MPU_xStreamBufferSpacesAvailableImpl +MPU_xStreamBufferSpacesAvailableImpl: + b MPU_xStreamBufferSpacesAvailableImpl + + PUBWEAK MPU_xStreamBufferBytesAvailableImpl +MPU_xStreamBufferBytesAvailableImpl: + b MPU_xStreamBufferBytesAvailableImpl + + PUBWEAK MPU_xStreamBufferSetTriggerLevelImpl +MPU_xStreamBufferSetTriggerLevelImpl: + b MPU_xStreamBufferSetTriggerLevelImpl + + PUBWEAK MPU_xStreamBufferNextMessageLengthBytesImpl +MPU_xStreamBufferNextMessageLengthBytesImpl: + b MPU_xStreamBufferNextMessageLengthBytesImpl + +/*-----------------------------------------------------------*/ + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + END diff --git a/portable/IAR/ARM_CM33/non_secure/port.c b/portable/IAR/ARM_CM33/non_secure/port.c new file mode 100644 index 000000000..76d2b2445 --- /dev/null +++ b/portable/IAR/ARM_CM33/non_secure/port.c @@ -0,0 +1,2280 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024-2025 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU includes. */ +#include "mpu_wrappers.h" +#include "mpu_syscall_numbers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration settings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to check the validity of an interrupt priority. + */ +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) ) +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used during system call enter and exit. + */ +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Offsets in the stack to the parameters when inside the SVC handler. + */ +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +#if ( portARMV8M_MINOR_VERSION >= 1 ) + + /* Enable Privileged eXecute Never MPU attribute for the selected memory + * region. */ + #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL ) +#endif /* portARMV8M_MINOR_VERSION >= 1 */ + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Extract first address of the MPU region as encoded in the + * RBAR (Region Base Address Register) value. */ +#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \ + ( ( rbar ) & portMPU_RBAR_ADDRESS_MASK ) + +/* Extract last address of the MPU region as encoded in the + * RLAR (Region Limit Address Register) value. */ +#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \ + ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK ) + +/* Does addr lies within [start, end] address range? */ +#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \ + ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) ) + +/* Is the access request satisfied by the available permissions? */ +#define portIS_AUTHORIZED( accessRequest, permissions ) \ + ( ( ( permissions ) & ( accessRequest ) ) == accessRequest ) + +/* Max value that fits in a uint32_t type. */ +#define portUINT32_MAX ( ~( ( uint32_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. + */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 + +/** + * @brief Constants required to check and configure PACBTI security feature implementation. + */ +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) ) + + #define portCONTROL_UPAC_EN ( 1UL << 7UL ) + #define portCONTROL_PAC_EN ( 1UL << 6UL ) + #define portCONTROL_UBTI_EN ( 1UL << 5UL ) + #define portCONTROL_BTI_EN ( 1UL << 4UL ) + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Extract MPU region's access permissions from the Region Base Address + * Register (RBAR) value. + * + * @param ulRBARValue RBAR value for the MPU region. + * + * @return uint32_t Access permissions. + */ + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + + /** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + /** + * @brief Configures PACBTI features. + * + * This function configures the Pointer Authentication, and Branch Target + * Identification security features as per the user configuration. It returns + * the value of the special purpose CONTROL register accordingly, and optionally + * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M + * architecture based) target supports PACBTI security feature. + * + * @param xWriteControlRegister Used to control whether the special purpose + * CONTROL register should be updated or not. + * + * @return CONTROL register value according to the configured PACBTI option. + */ + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the system call stack so that upon returning from + * SVC, the system call stack is used. + * + * @param pulTaskStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + * @param ucSystemCallNumber The system call number of the system call. + */ + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Raise SVC for exiting from a system call. + */ + void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief This variable is set to pdTRUE when the scheduler is started. + */ + PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + + /** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +/** + * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + /** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + + /** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + + /** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the cpsid instruction + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessPermissions = 0; + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_ONLY ) + { + ulAccessPermissions = tskMPU_READ_PERMISSION; + } + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_WRITE ) + { + ulAccessPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION ); + } + + return ulAccessPermissions; + } + +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } + +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ portOFFSET_TO_PC ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ]; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulSystemCallStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the system call section (i.e. application is + * not raising SVC directly). + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as + * it is non-NULL only during the execution of a system call (i.e. + * between system call enter and exit). + * 3. System call is not for a kernel API disabled by the configuration + * in FreeRTOSConfig.h. + * 4. We do not need to check that ucSystemCallNumber is within range + * because the assembly SVC handler checks that before calling + * this function. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) && + ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) ) + { + pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the system call stack for the stack frame. */ + pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulSystemCallStack[ i ] = pulTaskStack[ i ]; + } + + /* Store the value of the Link Register before the SVC was raised. + * It contains the address of the caller of the System Call entry + * point (i.e. the caller of the MPU_). We need to restore it + * when we exit from the system call. */ + pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; + + /* Store the value of the PSPLIM register before the SVC was raised. + * We need to restore it when we exit from the system call. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* Use the pulSystemCallStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif + + /* Start executing the system call upon returning from this handler. */ + pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; + + /* Raise a request to exit from the system call upon finishing the + * system call. */ + pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; + + /* Remember the location where we should copy the stack frame when we exit from + * the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize; + + /* Record if the hardware used padding to force the stack pointer + * to be double word aligned. */ + if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK ) + { + pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG; + } + else + { + pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG ); + } + + /* We ensure in pxPortInitialiseStack that the system call stack is + * double word aligned and therefore, there is no need of padding. + * Clear the bit[9] of stacked xPSR. */ + pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + + /* Raise the privilege for the duration of the system call. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " bics r0, r1 \n" /* Clear nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */ + { + __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulTaskStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the privileged code (i.e. application is not + * raising SVC directly). This SVC is only raised from + * vRequestSystemCallExit which is in the privileged code section. + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL - + * this means that we previously entered a system call and the + * application is not attempting to exit without entering a system + * call. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) ) + { + pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the task stack for the stack frame. */ + pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulTaskStack[ i ] = pulSystemCallStack[ i ]; + } + + /* Use the pulTaskStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) ); + + /* Return to the caller of the System Call entry point (i.e. the + * caller of the MPU_). */ + pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + /* Ensure that LR has a valid value.*/ + pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + + /* Restore the PSPLIM register to what it was at the time of + * system call entry. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* If the hardware used padding to force the stack pointer + * to be double word aligned, set the stacked xPSR bit[9], + * otherwise clear it. */ + if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG ) + { + pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK; + } + else + { + pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + } + + /* This is not NULL only for the duration of the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; + + /* Drop the privilege before returning to the thread mode. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " orrs r0, r1 \n" /* Set nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xTaskIsPrivileged = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xTaskIsPrivileged = pdTRUE; + } + + return xTaskIsPrivileged; + } + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged, + xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulIndex = 0; + uint32_t ulControl = 0x0; + + xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ + ulIndex++; + + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + ulIndex++; + + #if ( configENABLE_TRUSTZONE == 1 ) + { + xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */ + ulIndex++; + } + #endif /* configENABLE_TRUSTZONE */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + ulIndex++; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Check PACBTI security feature configuration before pushing the + * CONTROL register's value on task's TCB. */ + ulControl = prvConfigurePACBTI( pdFALSE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + if( xRunPrivileged == pdTRUE ) + { + xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + else + { + xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG ); + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ + ulIndex++; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + { + /* Ensure that the system call stack is double word aligned. */ + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) + + ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + /* This is not NULL only for the duration of a system call. */ + xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL; + } + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ]; + ulIndex++; + } + } + #endif /* configENABLE_PAC */ + + return &( xMPUSettings->ulContext[ ulIndex ] ); + } + +#else /* configENABLE_MPU */ + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ + { + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + pxTopOfStack--; + *pxTopOfStack = ulTaskPacKey[ i ]; + } + } + #endif /* configENABLE_PAC */ + + return pxTopOfStack; + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Set the CONTROL register value based on PACBTI security feature + * configuration before starting the first task. */ + ( void ) prvConfigurePACBTI( pdTRUE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + { + xSchedulerRunning = pdTRUE; + } + #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + configSTACK_DEPTH_TYPE uxStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( uxStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* PXN. */ + #if ( portARMV8M_MINOR_VERSION >= 1 ) + { + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ); + } + } + #endif /* portARMV8M_MINOR_VERSION >= 1 */ + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, + uint32_t ulBufferLength, + uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */ + + { + uint32_t i, ulBufferStartAddress, ulBufferEndAddress; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE ) + { + ulBufferStartAddress = ( uint32_t ) pvBuffer; + ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL ); + + for( i = 0; i < portTOTAL_NUM_REGIONS; i++ ) + { + /* Is the MPU region enabled? */ + if( ( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR & portMPU_RLAR_REGION_ENABLE ) == portMPU_RLAR_REGION_ENABLE ) + { + if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_AUTHORIZED( ulAccessRequested, + prvGetRegionAccessPermissions( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ) ) ) + { + xAccessGranted = pdTRUE; + break; + } + } + } + } + } + + return xAccessGranted; + } + +#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings; + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else + { + xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 ) + { + xAccessGranted = pdTRUE; + } + } + } + + return xAccessGranted; + } + + #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + ( void ) lInternalIndexOfKernelObject; + + /* If Access Control List feature is not used, all the tasks have + * access to all the kernel objects. */ + return pdTRUE; + } + + #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + { + uint32_t ulControl = 0x0; + + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); + + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; + + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/ARM_CM33/non_secure/portasm.h b/portable/IAR/ARM_CM33/non_secure/portasm.h new file mode 100644 index 000000000..b7021b024 --- /dev/null +++ b/portable/IAR/ARM_CM33/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kernel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/portable/IAR/ARM_CM33/non_secure/portasm.s b/portable/IAR/ARM_CM33/non_secure/portasm.s new file mode 100644 index 000000000..8d5988819 --- /dev/null +++ b/portable/IAR/ARM_CM33/non_secure/portasm.s @@ -0,0 +1,543 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" + +/* System call numbers includes. */ +#include "mpu_syscall_numbers.h" + +#ifndef configUSE_MPU_WRAPPERS_V1 + #define configUSE_MPU_WRAPPERS_V1 0 +#endif + + EXTERN pxCurrentTCB + EXTERN xSecureContext + EXTERN vTaskSwitchContext + EXTERN vPortSVCHandler_C + EXTERN SecureContext_SaveContext + EXTERN SecureContext_LoadContext +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + EXTERN vSystemCallEnter + EXTERN vSystemCallExit +#endif + + PUBLIC xIsPrivileged + PUBLIC vResetPrivilege + PUBLIC vPortAllocateSecureContext + PUBLIC vRestoreContextOfFirstTask + PUBLIC vRaisePrivilege + PUBLIC vStartFirstTask + PUBLIC ulSetInterruptMask + PUBLIC vClearInterruptMask + PUBLIC PendSV_Handler + PUBLIC SVC_Handler + PUBLIC vPortFreeSecureContext +/*-----------------------------------------------------------*/ + +/*---------------- Unprivileged Functions -------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION .text:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +xIsPrivileged: + mrs r0, control /* r0 = CONTROL. */ + tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + ite ne + movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vResetPrivilege: + mrs r0, control /* r0 = CONTROL. */ + orr r0, r0, #1 /* r0 = r0 | 1. */ + msr control, r0 /* CONTROL = r0. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vPortAllocateSecureContext: + svc 100 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 100. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +/*----------------- Privileged Functions --------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION privileged_functions:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +vRestoreContextOfFirstTask: + program_mpu_first_task: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r3] /* r0 = pxCurrentTCB. */ + + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + str r2, [r1] /* Disable MPU. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r1, [r2] /* Program MAIR0. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + + movs r3, #4 /* r3 = 4. */ + str r3, [r1] /* Program RNR = 4. */ + ldmia r0!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + #if ( configTOTAL_MPU_REGIONS == 16 ) + movs r3, #8 /* r3 = 8. */ + str r3, [r1] /* Program RNR = 8. */ + ldmia r0!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + movs r3, #12 /* r3 = 12. */ + str r3, [r1] /* Program RNR = 12. */ + ldmia r0!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + orr r2, #1 /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */ + str r2, [r1] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + + restore_context_first_task: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* r1 = pxCurrentTCB.*/ + ldr r2, [r1] /* r2 = Location of saved context in TCB. */ + + restore_special_regs_first_task: + #if ( configENABLE_PAC == 1 ) + ldmdb r2!, {r3-r6} /* Read task's dedicated PAC key from the task's context. */ + msr PAC_KEY_P_0, r3 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_1, r4 + msr PAC_KEY_P_2, r5 + msr PAC_KEY_P_3, r6 + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + ldmdb r2!, {r0, r3-r5, lr} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */ + msr psp, r3 + msr psplim, r4 + msr control, r5 + ldr r4, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + str r0, [r4] /* Restore xSecureContext. */ + + restore_general_regs_first_task: + ldmdb r2!, {r4-r11} /* r4-r11 contain hardware saved context. */ + stmia r3!, {r4-r11} /* Copy the hardware saved context on the task stack. */ + ldmdb r2!, {r4-r11} /* r4-r11 restored. */ + + restore_context_done_first_task: + str r2, [r1] /* Save the location where the context should be saved next as the first member of TCB. */ + mov r0, #0 + msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ + bx lr + +#else /* configENABLE_MPU */ + +vRestoreContextOfFirstTask: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r3, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + +#if ( configENABLE_PAC == 1 ) + ldmia r0!, {r1-r4} /* Read task's dedicated PAC key from stack. */ + msr PAC_KEY_P_3, r1 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_2, r2 + msr PAC_KEY_P_1, r3 + msr PAC_KEY_P_0, r4 + clrm {r1-r4} /* Clear r1-r4. */ +#endif /* configENABLE_PAC */ + + ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */ + ldr r4, =xSecureContext + str r1, [r4] /* Set xSecureContext to this task's value for the same. */ + msr psplim, r2 /* Set this task's PSPLIM value. */ + mrs r1, control /* Obtain current control register value. */ + orrs r1, r1, #2 /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */ + msr control, r1 /* Write back the new control register value. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + mov r0, #0 + msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ + bx r3 /* Finally, branch to EXC_RETURN. */ + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +vRaisePrivilege: + mrs r0, control /* Read the CONTROL register. */ + bic r0, r0, #1 /* Clear the bit 0. */ + msr control, r0 /* Write back the new CONTROL value. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vStartFirstTask: + ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */ + ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */ + ldr r0, [r0] /* The first entry in vector table is stack pointer. */ + msr msp, r0 /* Set the MSP back to the start of the stack. */ + cpsie i /* Globally enable interrupts. */ + cpsie f + dsb + isb + svc 102 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */ +/*-----------------------------------------------------------*/ + +ulSetInterruptMask: + mrs r0, basepri /* r0 = basepri. Return original basepri value. */ + mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r1 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vClearInterruptMask: + msr basepri, r0 /* basepri = ulMask. */ + dsb + isb + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +PendSV_Handler: + ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + ldr r0, [r3] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */ + ldr r2, [r1] /* r2 = Location in TCB where the context should be saved. */ + + cbz r0, save_ns_context /* No secure context to save. */ + save_s_context: + push {r0-r2, lr} + bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r0-r2, lr} + + save_ns_context: + mov r3, lr /* r3 = LR (EXC_RETURN). */ + lsls r3, r3, #25 /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bmi save_special_regs /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + + save_general_regs: + mrs r3, psp + + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + add r3, r3, #0x20 /* Move r3 to location where s0 is saved. */ + tst lr, #0x10 + ittt eq + vstmiaeq r2!, {s16-s31} /* Store s16-s31. */ + vldmiaeq r3, {s0-s16} /* Copy hardware saved FP context into s0-s16. */ + vstmiaeq r2!, {s0-s16} /* Store hardware saved FP context. */ + sub r3, r3, #0x20 /* Set r3 back to the location of hardware saved context. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + + stmia r2!, {r4-r11} /* Store r4-r11. */ + ldmia r3, {r4-r11} /* Copy the hardware saved context into r4-r11. */ + stmia r2!, {r4-r11} /* Store the hardware saved context. */ + + save_special_regs: + mrs r3, psp /* r3 = PSP. */ + mrs r4, psplim /* r4 = PSPLIM. */ + mrs r5, control /* r5 = CONTROL. */ + stmia r2!, {r0, r3-r5, lr} /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ + #if ( configENABLE_PAC == 1 ) + mrs r3, PAC_KEY_P_0 /* Read task's dedicated PAC key from the PAC key registers. */ + mrs r4, PAC_KEY_P_1 + mrs r5, PAC_KEY_P_2 + mrs r6, PAC_KEY_P_3 + stmia r2!, {r3-r6} /* Store the task's dedicated PAC key on the task's context. */ + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + + str r2, [r1] /* Save the location from where the context should be restored as the first member of TCB. */ + + select_next_task: + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bl vTaskSwitchContext + mov r0, #0 /* r0 = 0. */ + msr basepri, r0 /* Enable interrupts. */ + + program_mpu: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r3] /* r0 = pxCurrentTCB.*/ + + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + str r2, [r1] /* Disable MPU. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r1, [r2] /* Program MAIR0. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + + movs r3, #4 /* r3 = 4. */ + str r3, [r1] /* Program RNR = 4. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + #if ( configTOTAL_MPU_REGIONS == 16 ) + movs r3, #8 /* r3 = 8. */ + str r3, [r1] /* Program RNR = 8. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + movs r3, #12 /* r3 = 12. */ + str r3, [r1] /* Program RNR = 12. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + orr r2, #1 /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */ + str r2, [r1] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + + restore_context: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* r1 = pxCurrentTCB.*/ + ldr r2, [r1] /* r2 = Location of saved context in TCB. */ + + restore_special_regs: + #if ( configENABLE_PAC == 1 ) + ldmdb r2!, {r3-r6} /* Read task's dedicated PAC key from the task's context. */ + msr PAC_KEY_P_0, r3 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_1, r4 + msr PAC_KEY_P_2, r5 + msr PAC_KEY_P_3, r6 + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + ldmdb r2!, {r0, r3-r5, lr} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */ + msr psp, r3 + msr psplim, r4 + msr control, r5 + ldr r4, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + str r0, [r4] /* Restore xSecureContext. */ + cbz r0, restore_ns_context /* No secure context to restore. */ + + restore_s_context: + push {r1-r3, lr} + bl SecureContext_LoadContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r1-r3, lr} + + restore_ns_context: + mov r0, lr /* r0 = LR (EXC_RETURN). */ + lsls r0, r0, #25 /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bmi restore_context_done /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + + restore_general_regs: + ldmdb r2!, {r4-r11} /* r4-r11 contain hardware saved context. */ + stmia r3!, {r4-r11} /* Copy the hardware saved context on the task stack. */ + ldmdb r2!, {r4-r11} /* r4-r11 restored. */ + + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 + ittt eq + vldmdbeq r2!, {s0-s16} /* s0-s16 contain hardware saved FP context. */ + vstmiaeq r3!, {s0-s16} /* Copy hardware saved FP context on the task stack. */ + vldmdbeq r2!, {s16-s31} /* Restore s16-s31. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + + restore_context_done: + str r2, [r1] /* Save the location where the context should be saved next as the first member of TCB. */ + bx lr + +#else /* configENABLE_MPU */ + +PendSV_Handler: + ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + ldr r0, [r3] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */ + mrs r2, psp /* Read PSP in r2. */ + + cbz r0, save_ns_context /* No secure context to save. */ + save_s_context: + push {r0-r2, lr} + bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r0-r2, lr} + + save_ns_context: + mov r3, lr /* r3 = LR. */ + lsls r3, r3, #25 /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bmi save_special_regs /* If r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used. */ + + save_general_regs: + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + it eq + vstmdbeq r2!, {s16-s31} /* Store the additional FP context registers which are not saved automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + stmdb r2!, {r4-r11} /* Store the registers that are not saved automatically. */ + + save_special_regs: + mrs r3, psplim /* r3 = PSPLIM. */ + stmdb r2!, {r0, r3, lr} /* Store xSecureContext, PSPLIM and LR on the stack. */ + #if ( configENABLE_PAC == 1 ) + mrs r3, PAC_KEY_P_3 /* Read task's dedicated PAC key from the PAC key registers. */ + mrs r4, PAC_KEY_P_2 + mrs r5, PAC_KEY_P_1 + mrs r6, PAC_KEY_P_0 + stmdb r2!, {r3-r6} /* Store the task's dedicated PAC key on the stack. */ + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + + str r2, [r1] /* Save the new top of stack in TCB. */ + + select_next_task: + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bl vTaskSwitchContext + mov r0, #0 /* r0 = 0. */ + msr basepri, r0 /* Enable interrupts. */ + + restore_context: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB. */ + ldr r2, [r1] /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */ + + restore_special_regs: + #if ( configENABLE_PAC == 1 ) + ldmia r2!, {r3-r6} /* Read task's dedicated PAC key from stack. */ + msr PAC_KEY_P_3, r3 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_2, r4 + msr PAC_KEY_P_1, r5 + msr PAC_KEY_P_0, r6 + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + ldmia r2!, {r0, r3, lr} http://files.iar.com/ftp/pub/box/bxarm-9.60.3.deb/* Read from stack - r0 = xSecureContext, r3 = PSPLIM and LR restored. */ + msr psplim, r3 /* Restore the PSPLIM register value for the task. */ + ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + str r0, [r3] /* Restore the task's xSecureContext. */ + cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */ + + restore_s_context: + push {r1-r3, lr} + bl SecureContext_LoadContext /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r1-r3, lr} + + restore_ns_context: + mov r0, lr /* r0 = LR (EXC_RETURN). */ + lsls r0, r0, #25 /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bmi restore_context_done /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + + restore_general_regs: + ldmia r2!, {r4-r11} /* Restore the registers that are not automatically restored. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + it eq + vldmiaeq r2!, {s16-s31} /* Restore the additional FP context registers which are not restored automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + + restore_context_done: + msr psp, r2 /* Remember the new top of stack for the task. */ + bx lr + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + +SVC_Handler: + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + + ldr r1, [r0, #24] + ldrb r2, [r1, #-2] + cmp r2, #NUM_SYSTEM_CALLS + blt syscall_enter + cmp r2, #104 /* portSVC_SYSTEM_CALL_EXIT. */ + beq syscall_exit + b vPortSVCHandler_C + + syscall_enter: + mov r1, lr + b vSystemCallEnter + + syscall_exit: + mov r1, lr + b vSystemCallExit + +#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +SVC_Handler: + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + b vPortSVCHandler_C + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +vPortFreeSecureContext: + /* r0 = uint32_t *pulTCB. */ + ldr r2, [r0] /* The first item in the TCB is the top of the stack. */ + ldr r1, [r2] /* The first item on the stack is the task's xSecureContext. */ + cmp r1, #0 /* Raise svc if task's xSecureContext is not NULL. */ + it ne + svcne 101 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 101. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + + END diff --git a/portable/IAR/ARM_CM33/non_secure/portmacro.h b/portable/IAR/ARM_CM33/non_secure/portmacro.h new file mode 100644 index 000000000..53b668b5b --- /dev/null +++ b/portable/IAR/ARM_CM33/non_secure/portmacro.h @@ -0,0 +1,88 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M33" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portARMV8M_MINOR_VERSION 0 +#define portDONT_DISCARD __root +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +#ifndef configENABLE_MVE + #define configENABLE_MVE 0 +#elif ( configENABLE_MVE != 0 ) + #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M33. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ +#pragma diag_suppress=Be006 +#pragma diag_suppress=Pa082 +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h new file mode 100644 index 000000000..f373bcad5 --- /dev/null +++ b/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h @@ -0,0 +1,582 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACROCOMMON_H +#define PORTMACROCOMMON_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. +#endif /* configENABLE_FPU */ + +#ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. +#endif /* configENABLE_MPU */ + +#ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. +#endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() +#define portINLINE __inline +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif +#define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ +extern BaseType_t xPortIsInsideInterrupt( void ); + +extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + +extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; +extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + +extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; +extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + +#if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_PAC == 1 ) + + /** + * @brief Generates 128-bit task's random PAC key. + * + * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be + * filled with a 128-bit random number. + */ + void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); + +#endif /* configENABLE_PAC */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ +#if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) +#else + #define portPRIVILEGE_BIT ( 0x0UL ) +#endif /* configENABLE_MPU */ + +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ +#define portPRIVILEGED_FLASH_REGION ( 0UL ) +#define portUNPRIVILEGED_FLASH_REGION ( 1UL ) +#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) +#define portPRIVILEGED_RAM_REGION ( 3UL ) +#define portSTACK_REGION ( 4UL ) +#define portFIRST_CONFIGURABLE_REGION ( 5UL ) +#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) +#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) +#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ +#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ +#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ +#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ +#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ +#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ +#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ +#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) +#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) +#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + +#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) +#define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) +#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) +#define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + +#define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + #ifndef configSYSTEM_CALL_STACK_SIZE + #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. + #endif + + /** + * @brief System call stack. + */ + typedef struct SYSTEM_CALL_STACK_INFO + { + uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; + uint32_t * pulSystemCallStack; + uint32_t * pulSystemCallStackLimit; + uint32_t * pulTaskStack; + uint32_t ulLinkRegisterAtSystemCallEntry; + uint32_t ulStackLimitRegisterAtSystemCallEntry; + } xSYSTEM_CALL_STACK_INFO; + + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + /** + * @brief MPU settings as stored in the TCB. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><-----------><----> + * 16 17 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 71 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 17 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 55 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | | | PC, xPSR | EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><-----------><----> + * 16 17 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 70 + + #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + /* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 17 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 54 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+------------------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +----------+-----------------+------------------------------+------------+-----+ + * + * <---------><----------------><------------------------------><-----------><----> + * 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 38 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+----------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | PC, xPSR | EXC_RETURN | | | + * +----------+-----------------+----------------------+------------+-----+ + * + * <---------><----------------><----------------------><-----------><----> + * 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 37 + + #else /* #if( configENABLE_TRUSTZONE == 1 ) */ + + /* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) + + /* Size of an Access Control List (ACL) entry in bits. */ + #define portACL_ENTRY_SIZE_BITS ( 32U ) + + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + uint32_t ulContext[ MAX_CONTEXT_SIZE ]; + uint32_t ulTaskFlags; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo; + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ]; + #endif + #endif + } xMPU_SETTINGS; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Validate priority of ISRs that are allowed to call FreeRTOS + * system calls. + */ +#if ( configASSERT_DEFINED == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif +#endif + +/** + * @brief SVC numbers. + */ +#define portSVC_ALLOCATE_SECURE_CONTEXT 100 +#define portSVC_FREE_SECURE_CONTEXT 101 +#define portSVC_START_SCHEDULER 102 +#define portSVC_RAISE_PRIVILEGE 103 +#define portSVC_SYSTEM_CALL_EXIT 104 +#define portSVC_YIELD 105 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) +#endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() +#else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + extern BaseType_t xPortIsTaskPrivileged( void ); + +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACROCOMMON_H */ diff --git a/portable/IAR/ARM_CM33/secure/secure_context.c b/portable/IAR/ARM_CM33/secure/secure_context.c new file mode 100644 index 000000000..3aa335e63 --- /dev/null +++ b/portable/IAR/ARM_CM33/secure/secure_context.c @@ -0,0 +1,354 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Secure context includes. */ +#include "secure_context.h" + +/* Secure heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief CONTROL value for privileged tasks. + * + * Bit[0] - 0 --> Thread mode is privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_PRIVILEGED 0x02 + +/** + * @brief CONTROL value for un-privileged tasks. + * + * Bit[0] - 1 --> Thread mode is un-privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03 + +/** + * @brief Size of stack seal values in bytes. + */ +#define securecontextSTACK_SEAL_SIZE 8 + +/** + * @brief Stack seal value as recommended by ARM. + */ +#define securecontextSTACK_SEAL_VALUE 0xFEF5EDA5 + +/** + * @brief Maximum number of secure contexts. + */ +#ifndef secureconfigMAX_SECURE_CONTEXTS + #define secureconfigMAX_SECURE_CONTEXTS 8UL +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Pre-allocated array of secure contexts. + */ +SecureContext_t xSecureContexts[ secureconfigMAX_SECURE_CONTEXTS ]; +/*-----------------------------------------------------------*/ + +/** + * @brief Get a free secure context for a task from the secure context pool (xSecureContexts). + * + * This function ensures that only one secure context is allocated for a task. + * + * @param[in] pvTaskHandle The task handle for which the secure context is allocated. + * + * @return Index of a free secure context in the xSecureContexts array. + */ +static uint32_t ulGetSecureContext( void * pvTaskHandle ); + +/** + * @brief Return the secure context to the secure context pool (xSecureContexts). + * + * @param[in] ulSecureContextIndex Index of the context in the xSecureContexts array. + */ +static void vReturnSecureContext( uint32_t ulSecureContextIndex ); + +/* These are implemented in assembly. */ +extern void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ); +extern void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ); +/*-----------------------------------------------------------*/ + +static uint32_t ulGetSecureContext( void * pvTaskHandle ) +{ + /* Start with invalid index. */ + uint32_t i, ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + if( ( xSecureContexts[ i ].pucCurrentStackPointer == NULL ) && + ( xSecureContexts[ i ].pucStackLimit == NULL ) && + ( xSecureContexts[ i ].pucStackStart == NULL ) && + ( xSecureContexts[ i ].pvTaskHandle == NULL ) && + ( ulSecureContextIndex == secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = i; + } + else if( xSecureContexts[ i ].pvTaskHandle == pvTaskHandle ) + { + /* A task can only have one secure context. Do not allocate a second + * context for the same task. */ + ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + break; + } + } + + return ulSecureContextIndex; +} +/*-----------------------------------------------------------*/ + +static void vReturnSecureContext( uint32_t ulSecureContextIndex ) +{ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackStart = NULL; + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = NULL; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) +{ + uint32_t ulIPSR, i; + static uint32_t ulSecureContextsInitialized = 0; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ( ulIPSR != 0 ) && ( ulSecureContextsInitialized == 0 ) ) + { + /* Ensure to initialize secure contexts only once. */ + ulSecureContextsInitialized = 1; + + /* No stack for thread mode until a task's context is loaded. */ + secureportSET_PSPLIM( securecontextNO_STACK ); + secureportSET_PSP( securecontextNO_STACK ); + + /* Initialize all secure contexts. */ + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + xSecureContexts[ i ].pucCurrentStackPointer = NULL; + xSecureContexts[ i ].pucStackLimit = NULL; + xSecureContexts[ i ].pucStackStart = NULL; + xSecureContexts[ i ].pvTaskHandle = NULL; + } + + #if ( configENABLE_MPU == 1 ) + { + /* Configure thread mode to use PSP and to be unprivileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); + } + #else /* configENABLE_MPU */ + { + /* Configure thread mode to use PSP and to be privileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); + } + #endif /* configENABLE_MPU */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ) +#else /* configENABLE_MPU */ + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ) +#endif /* configENABLE_MPU */ +{ + uint8_t * pucStackMemory = NULL; + uint8_t * pucStackLimit; + uint32_t ulIPSR, ulSecureContextIndex; + SecureContextHandle_t xSecureContextHandle = securecontextINVALID_CONTEXT_ID; + + #if ( configENABLE_MPU == 1 ) + uint32_t * pulCurrentStackPointer = NULL; + #endif /* configENABLE_MPU */ + + /* Read the Interrupt Program Status Register (IPSR) and Process Stack Limit + * Register (PSPLIM) value. */ + secureportREAD_IPSR( ulIPSR ); + secureportREAD_PSPLIM( pucStackLimit ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. + * Also do nothing, if a secure context us already loaded. PSPLIM is set to + * securecontextNO_STACK when no secure context is loaded. */ + if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) ) + { + /* Obtain a free secure context. */ + ulSecureContextIndex = ulGetSecureContext( pvTaskHandle ); + + /* Were we able to get a free context? */ + if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS ) + { + /* Allocate the stack space. */ + pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + + if( pucStackMemory != NULL ) + { + /* Since stack grows down, the starting point will be the last + * location. Note that this location is next to the last + * allocated byte for stack (excluding the space for seal values) + * because the hardware decrements the stack pointer before + * writing i.e. if stack pointer is 0x2, a push operation will + * decrement the stack pointer to 0x1 and then write at 0x1. */ + xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize; + + /* Seal the created secure process stack. */ + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; + + /* The stack cannot go beyond this location. This value is + * programmed in the PSPLIM register on context switch.*/ + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = pucStackMemory; + + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle; + + #if ( configENABLE_MPU == 1 ) + { + /* Store the correct CONTROL value for the task on the stack. + * This value is programmed in the CONTROL register on + * context switch. */ + pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; + pulCurrentStackPointer--; + + if( ulIsTaskPrivileged ) + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; + } + else + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; + } + + /* Store the current stack pointer. This value is programmed in + * the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + } + #else /* configENABLE_MPU */ + { + /* Current SP is set to the starting of the stack. This + * value programmed in the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + } + #endif /* configENABLE_MPU */ + + /* Ensure to never return 0 as a valid context handle. */ + xSecureContextHandle = ulSecureContextIndex + 1UL; + } + } + } + + return xSecureContextHandle; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) +{ + uint32_t ulIPSR, ulSecureContextIndex; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* Only free if a valid context handle is passed. */ + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + /* Ensure that the secure context being deleted is associated with + * the task. */ + if( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) + { + /* Free the stack space. */ + vPortFree( xSecureContexts[ ulSecureContextIndex ].pucStackLimit ); + + /* Return the secure context back to the free secure contexts pool. */ + vReturnSecureContext( ulSecureContextIndex ); + } + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that no secure context is loaded and the task is loading it's + * own context. */ + if( ( pucStackLimit == securecontextNO_STACK ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_LoadContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that task's context is loaded and the task is saving it's own + * context. */ + if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_SaveContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/ARM_CM33/secure/secure_context.h b/portable/IAR/ARM_CM33/secure/secure_context.h new file mode 100644 index 000000000..e36a8e430 --- /dev/null +++ b/portable/IAR/ARM_CM33/secure/secure_context.h @@ -0,0 +1,138 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_CONTEXT_H__ +#define __SECURE_CONTEXT_H__ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" + +/** + * @brief PSP value when no secure context is loaded. + */ +#define securecontextNO_STACK 0x0 + +/** + * @brief Invalid context ID. + */ +#define securecontextINVALID_CONTEXT_ID 0UL +/*-----------------------------------------------------------*/ + +/** + * @brief Structure to represent a secure context. + * + * @note Since stack grows down, pucStackStart is the highest address while + * pucStackLimit is the first address of the allocated memory. + */ +typedef struct SecureContext +{ + uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */ + uint8_t * pucStackLimit; /**< Last location of the stack memory (PSPLIM). */ + uint8_t * pucStackStart; /**< First location of the stack memory. */ + void * pvTaskHandle; /**< Task handle of the task this context is associated with. */ +} SecureContext_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Opaque handle for a secure context. + */ +typedef uint32_t SecureContextHandle_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Initializes the secure context management system. + * + * PSP is set to NULL and therefore a task must allocate and load a context + * before calling any secure side function in the thread mode. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureContext_Init( void ); + +/** + * @brief Allocates a context on the secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] ulSecureStackSize Size of the stack to allocate on secure side. + * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise. + * + * @return Opaque context handle if context is successfully allocated, NULL + * otherwise. + */ +#if ( configENABLE_MPU == 1 ) + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ); +#else /* configENABLE_MPU */ + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ); +#endif /* configENABLE_MPU */ + +/** + * @brief Frees the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the + * context to be freed. + */ +void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); + +/** + * @brief Loads the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be loaded. + */ +void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); + +/** + * @brief Saves the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be saved. + */ +void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); + +#endif /* __SECURE_CONTEXT_H__ */ diff --git a/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s b/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s new file mode 100644 index 000000000..27a8f3933 --- /dev/null +++ b/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s @@ -0,0 +1,86 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + SECTION .text:CODE:NOROOT(2) + THUMB + +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" + + PUBLIC SecureContext_LoadContextAsm + PUBLIC SecureContext_SaveContextAsm +/*-----------------------------------------------------------*/ + +SecureContext_LoadContextAsm: + /* pxSecureContext value is in r0. */ + mrs r1, ipsr /* r1 = IPSR. */ + cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */ + ldmia r0!, {r1, r2} /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */ + +#if ( configENABLE_MPU == 1 ) + ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL. */ + msr control, r3 /* CONTROL = r3. */ +#endif /* configENABLE_MPU */ + + msr psplim, r2 /* PSPLIM = r2. */ + msr psp, r1 /* PSP = r1. */ + + load_ctx_therad_mode: + bx lr +/*-----------------------------------------------------------*/ + +SecureContext_SaveContextAsm: + /* pxSecureContext value is in r0. */ + mrs r1, ipsr /* r1 = IPSR. */ + cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */ + mrs r1, psp /* r1 = PSP. */ + +#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + vstmdb r1!, {s0} /* Trigger the deferred stacking of FPU registers. */ + vldmia r1!, {s0} /* Nullify the effect of the previous statement. */ +#endif /* configENABLE_FPU || configENABLE_MVE */ + +#if ( configENABLE_MPU == 1 ) + mrs r2, control /* r2 = CONTROL. */ + stmdb r1!, {r2} /* Store CONTROL value on the stack. */ +#endif /* configENABLE_MPU */ + + str r1, [r0] /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */ + movs r1, #0 /* r1 = securecontextNO_STACK. */ + msr psplim, r1 /* PSPLIM = securecontextNO_STACK. */ + msr psp, r1 /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */ + + save_ctx_therad_mode: + bx lr +/*-----------------------------------------------------------*/ + + END diff --git a/portable/IAR/ARM_CM33/secure/secure_heap.c b/portable/IAR/ARM_CM33/secure/secure_heap.c new file mode 100644 index 000000000..896b53e2d --- /dev/null +++ b/portable/IAR/ARM_CM33/secure/secure_heap.c @@ -0,0 +1,485 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Configuration includes. */ +#include "FreeRTOSConfig.h" + +/* Secure context heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Total heap size. + */ +#ifndef secureconfigTOTAL_HEAP_SIZE + #define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) ) +#endif + +/* No test marker by default. */ +#ifndef mtCOVERAGE_TEST_MARKER + #define mtCOVERAGE_TEST_MARKER() +#endif + +/* No tracing by default. */ +#ifndef traceMALLOC + #define traceMALLOC( pvReturn, xWantedSize ) +#endif + +/* No tracing by default. */ +#ifndef traceFREE + #define traceFREE( pv, xBlockSize ) +#endif + +/* Block sizes must not get too small. */ +#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) ) + +/* Assumes 8bit bytes! */ +#define secureheapBITS_PER_BYTE ( ( size_t ) 8 ) + +/* Max value that fits in a size_t type. */ +#define secureheapSIZE_MAX ( ~( ( size_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define secureheapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) ) + +/* MSB of the xBlockSize member of an BlockLink_t structure is used to track + * the allocation status of a block. When MSB of the xBlockSize member of + * an BlockLink_t structure is set then the block belongs to the application. + * When the bit is free the block is still part of the free heap space. */ +#define secureheapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) ) +#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 ) +#define secureheapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 ) +#define secureheapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK ) +#define secureheapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK ) +/*-----------------------------------------------------------*/ + +/* Allocate the memory for the heap. */ +#if ( configAPPLICATION_ALLOCATED_HEAP == 1 ) + +/* The application writer has already defined the array used for the RTOS +* heap - probably so it can be placed in a special segment or address. */ + extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#else /* configAPPLICATION_ALLOCATED_HEAP */ + static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#endif /* configAPPLICATION_ALLOCATED_HEAP */ + +/** + * @brief The linked list structure. + * + * This is used to link free blocks in order of their memory address. + */ +typedef struct A_BLOCK_LINK +{ + struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */ + size_t xBlockSize; /**< The size of the free block. */ +} BlockLink_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Called automatically to setup the required heap structures the first + * time pvPortMalloc() is called. + */ +static void prvHeapInit( void ); + +/** + * @brief Inserts a block of memory that is being freed into the correct + * position in the list of free memory blocks. + * + * The block being freed will be merged with the block in front it and/or the + * block behind it if the memory blocks are adjacent to each other. + * + * @param[in] pxBlockToInsert The block being freed. + */ +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ); +/*-----------------------------------------------------------*/ + +/** + * @brief The size of the structure placed at the beginning of each allocated + * memory block must by correctly byte aligned. + */ +static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + +/** + * @brief Create a couple of list links to mark the start and end of the list. + */ +static BlockLink_t xStart; +static BlockLink_t * pxEnd = NULL; + +/** + * @brief Keeps track of the number of free bytes remaining, but says nothing + * about fragmentation. + */ +static size_t xFreeBytesRemaining = 0U; +static size_t xMinimumEverFreeBytesRemaining = 0U; + +/*-----------------------------------------------------------*/ + +static void prvHeapInit( void ) +{ + BlockLink_t * pxFirstFreeBlock; + uint8_t * pucAlignedHeap; + size_t uxAddress; + size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE; + + /* Ensure the heap starts on a correctly aligned boundary. */ + uxAddress = ( size_t ) ucHeap; + + if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 ) + { + uxAddress += ( secureportBYTE_ALIGNMENT - 1 ); + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; + } + + pucAlignedHeap = ( uint8_t * ) uxAddress; + + /* xStart is used to hold a pointer to the first item in the list of free + * blocks. The void cast is used to prevent compiler warnings. */ + xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; + xStart.xBlockSize = ( size_t ) 0; + + /* pxEnd is used to mark the end of the list of free blocks and is inserted + * at the end of the heap space. */ + uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; + uxAddress -= xHeapStructSize; + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + pxEnd = ( void * ) uxAddress; + pxEnd->xBlockSize = 0; + pxEnd->pxNextFreeBlock = NULL; + + /* To start with there is a single free block that is sized to take up the + * entire heap space, minus the space taken by pxEnd. */ + pxFirstFreeBlock = ( void * ) pucAlignedHeap; + pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; + pxFirstFreeBlock->pxNextFreeBlock = pxEnd; + + /* Only one block exists - and it covers the entire usable heap space. */ + xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; +} +/*-----------------------------------------------------------*/ + +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) +{ + BlockLink_t * pxIterator; + uint8_t * puc; + + /* Iterate through the list until a block is found that has a higher address + * than the block being inserted. */ + for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) + { + /* Nothing to do here, just iterate to the right position. */ + } + + /* Do the block being inserted, and the block it is being inserted after + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxIterator; + + if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) + { + pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; + pxBlockToInsert = pxIterator; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Do the block being inserted, and the block it is being inserted before + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxBlockToInsert; + + if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) + { + if( pxIterator->pxNextFreeBlock != pxEnd ) + { + /* Form one big block from the two blocks. */ + pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxEnd; + } + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; + } + + /* If the block being inserted plugged a gap, so was merged with the block + * before and the block after, then it's pxNextFreeBlock pointer will have + * already been set, and should not be set here as that would make it point + * to itself. */ + if( pxIterator != pxBlockToInsert ) + { + pxIterator->pxNextFreeBlock = pxBlockToInsert; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} +/*-----------------------------------------------------------*/ + +void * pvPortMalloc( size_t xWantedSize ) +{ + BlockLink_t * pxBlock; + BlockLink_t * pxPreviousBlock; + BlockLink_t * pxNewBlockLink; + void * pvReturn = NULL; + size_t xAdditionalRequiredSize; + size_t xAllocatedBlockSize = 0; + + /* If this is the first call to malloc then the heap will require + * initialisation to setup the list of free blocks. */ + if( pxEnd == NULL ) + { + prvHeapInit(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xWantedSize > 0 ) + { + /* The wanted size must be increased so it can contain a BlockLink_t + * structure in addition to the requested amount of bytes. */ + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 ) + { + xWantedSize += xHeapStructSize; + + /* Ensure that blocks are always aligned to the required number + * of bytes. */ + if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 ) + { + /* Byte alignment required. */ + xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ); + + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 ) + { + xWantedSize += xAdditionalRequiredSize; + } + else + { + xWantedSize = 0; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + xWantedSize = 0; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Check the requested block size is not so large that the top bit is set. + * The top bit of the block size member of the BlockLink_t structure is used + * to determine who owns the block - the application or the kernel, so it + * must be free. */ + if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 ) + { + if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) + { + /* Traverse the list from the start (lowest address) block until + * one of adequate size is found. */ + pxPreviousBlock = &xStart; + pxBlock = xStart.pxNextFreeBlock; + + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + { + pxPreviousBlock = pxBlock; + pxBlock = pxBlock->pxNextFreeBlock; + } + + /* If the end marker was reached then a block of adequate size was + * not found. */ + if( pxBlock != pxEnd ) + { + /* Return the memory space pointed to - jumping over the + * BlockLink_t structure at its start. */ + pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); + + /* This block is being returned for use so must be taken out + * of the list of free blocks. */ + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + + /* If the block is larger than required it can be split into + * two. */ + if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE ) + { + /* This block is to be split into two. Create a new + * block following the number of bytes requested. The void + * cast is used to prevent byte alignment warnings from the + * compiler. */ + pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); + secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + + /* Calculate the sizes of two blocks split from the single + * block. */ + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + pxBlock->xBlockSize = xWantedSize; + + /* Insert the new block into the list of free blocks. */ + pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock; + pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xFreeBytesRemaining -= pxBlock->xBlockSize; + + if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) + { + xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xAllocatedBlockSize = pxBlock->xBlockSize; + + /* The block is being returned - it is allocated and owned by + * the application and has no "next" block. */ + secureheapALLOCATE_BLOCK( pxBlock ); + pxBlock->pxNextFreeBlock = NULL; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceMALLOC( pvReturn, xAllocatedBlockSize ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xAllocatedBlockSize; + + #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) + { + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */ + + secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 ); + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void * pv ) +{ + uint8_t * puc = ( uint8_t * ) pv; + BlockLink_t * pxLink; + + if( pv != NULL ) + { + /* The memory being freed will have an BlockLink_t structure immediately + * before it. */ + puc -= xHeapStructSize; + + /* This casting is to keep the compiler from issuing warnings. */ + pxLink = ( void * ) puc; + + /* Check the block is actually allocated. */ + secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ); + secureportASSERT( pxLink->pxNextFreeBlock == NULL ); + + if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ) + { + if( pxLink->pxNextFreeBlock == NULL ) + { + /* The block is being returned to the heap - it is no longer + * allocated. */ + secureheapFREE_BLOCK( pxLink ); + + secureportDISABLE_NON_SECURE_INTERRUPTS(); + { + /* Add this block to the list of free blocks. */ + xFreeBytesRemaining += pxLink->xBlockSize; + traceFREE( pv, pxLink->xBlockSize ); + prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); + } + secureportENABLE_NON_SECURE_INTERRUPTS(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } +} +/*-----------------------------------------------------------*/ + +size_t xPortGetFreeHeapSize( void ) +{ + return xFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +size_t xPortGetMinimumEverFreeHeapSize( void ) +{ + return xMinimumEverFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/ARM_CM33/secure/secure_heap.h b/portable/IAR/ARM_CM33/secure/secure_heap.h new file mode 100644 index 000000000..0e84a9d9d --- /dev/null +++ b/portable/IAR/ARM_CM33/secure/secure_heap.h @@ -0,0 +1,66 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_HEAP_H__ +#define __SECURE_HEAP_H__ + +/* Standard includes. */ +#include + +/** + * @brief Allocates memory from heap. + * + * @param[in] xWantedSize The size of the memory to be allocated. + * + * @return Pointer to the memory region if the allocation is successful, NULL + * otherwise. + */ +void * pvPortMalloc( size_t xWantedSize ); + +/** + * @brief Frees the previously allocated memory. + * + * @param[in] pv Pointer to the memory to be freed. + */ +void vPortFree( void * pv ); + +/** + * @brief Get the free heap size. + * + * @return Free heap size. + */ +size_t xPortGetFreeHeapSize( void ); + +/** + * @brief Get the minimum ever free heap size. + * + * @return Minimum ever free heap size. + */ +size_t xPortGetMinimumEverFreeHeapSize( void ); + +#endif /* __SECURE_HEAP_H__ */ diff --git a/portable/IAR/ARM_CM33/secure/secure_init.c b/portable/IAR/ARM_CM33/secure/secure_init.c new file mode 100644 index 000000000..c50d37668 --- /dev/null +++ b/portable/IAR/ARM_CM33/secure/secure_init.c @@ -0,0 +1,106 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Secure init includes. */ +#include "secure_init.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Constants required to manipulate the SCB. + */ +#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */ +#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL ) +#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS ) +#define secureinitSCB_AIRCR_PRIS_POS ( 14UL ) +#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS ) + +/** + * @brief Constants required to manipulate the FPU. + */ +#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define secureinitFPCCR_LSPENS_POS ( 29UL ) +#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS ) +#define secureinitFPCCR_TS_POS ( 26UL ) +#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS ) + +#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */ +#define secureinitNSACR_CP10_POS ( 10UL ) +#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS ) +#define secureinitNSACR_CP11_POS ( 11UL ) +#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS ) +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) | + ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) | + ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK ); + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is + * permitted. CP11 should be programmed to the same value as CP10. */ + *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK ); + + /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures + * that we can enable/disable lazy stacking in port.c file. */ + *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK ); + + /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP + * registers (S16-S31) are also pushed to stack on exception entry and + * restored on exception return. */ + *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK ); + } +} +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/ARM_CM33/secure/secure_init.h b/portable/IAR/ARM_CM33/secure/secure_init.h new file mode 100644 index 000000000..ebe04900f --- /dev/null +++ b/portable/IAR/ARM_CM33/secure/secure_init.h @@ -0,0 +1,54 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_INIT_H__ +#define __SECURE_INIT_H__ + +/** + * @brief De-prioritizes the non-secure exceptions. + * + * This is needed to ensure that the non-secure PendSV runs at the lowest + * priority. Context switch is done in the non-secure PendSV handler. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_DePrioritizeNSExceptions( void ); + +/** + * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access. + * + * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point + * Registers are not leaked to the non-secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_EnableNSFPUAccess( void ); + +#endif /* __SECURE_INIT_H__ */ diff --git a/portable/IAR/ARM_CM33/secure/secure_port_macros.h b/portable/IAR/ARM_CM33/secure/secure_port_macros.h new file mode 100644 index 000000000..a70da2c65 --- /dev/null +++ b/portable/IAR/ARM_CM33/secure/secure_port_macros.h @@ -0,0 +1,140 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_PORT_MACROS_H__ +#define __SECURE_PORT_MACROS_H__ + +/** + * @brief Byte alignment requirements. + */ +#define secureportBYTE_ALIGNMENT 8 +#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 ) + +/** + * @brief Macro to declare a function as non-secure callable. + */ +#if defined( __IAR_SYSTEMS_ICC__ ) + #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry __root +#else + #define secureportNON_SECURE_CALLABLE __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) ) +#endif + +/** + * @brief Set the secure PRIMASK value. + */ +#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Set the non-secure PRIMASK value. + */ +#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Read the PSP value in the given variable. + */ +#define secureportREAD_PSP( pucOutCurrentStackPointer ) \ + __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) ) + +/** + * @brief Set the PSP to the given value. + */ +#define secureportSET_PSP( pucCurrentStackPointer ) \ + __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) ) + +/** + * @brief Read the PSPLIM value in the given variable. + */ +#define secureportREAD_PSPLIM( pucOutStackLimit ) \ + __asm volatile ( "mrs %0, psplim" : "=r" ( pucOutStackLimit ) ) + +/** + * @brief Set the PSPLIM to the given value. + */ +#define secureportSET_PSPLIM( pucStackLimit ) \ + __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) ) + +/** + * @brief Set the NonSecure MSP to the given value. + */ +#define secureportSET_MSP_NS( pucMainStackPointer ) \ + __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) ) + +/** + * @brief Set the CONTROL register to the given value. + */ +#define secureportSET_CONTROL( ulControl ) \ + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" ) + +/** + * @brief Read the Interrupt Program Status Register (IPSR) value in the given + * variable. + */ +#define secureportREAD_IPSR( ulIPSR ) \ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) ) + +/** + * @brief PRIMASK value to enable interrupts. + */ +#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0 + +/** + * @brief PRIMASK value to disable interrupts. + */ +#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1 + +/** + * @brief Disable secure interrupts. + */ +#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Disable non-secure interrupts. + * + * This effectively disables context switches. + */ +#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Enable non-secure interrupts. + */ +#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL ) + +/** + * @brief Assert definition. + */ +#define secureportASSERT( x ) \ + if( ( x ) == 0 ) \ + { \ + secureportDISABLE_SECURE_INTERRUPTS(); \ + secureportDISABLE_NON_SECURE_INTERRUPTS(); \ + for( ; ; ) {; } \ + } + +#endif /* __SECURE_PORT_MACROS_H__ */ diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S new file mode 100644 index 000000000..d2cb78e92 --- /dev/null +++ b/portable/IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S @@ -0,0 +1,1242 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + + SECTION freertos_system_calls:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +#include "FreeRTOSConfig.h" +#include "mpu_syscall_numbers.h" + +#ifndef configUSE_MPU_WRAPPERS_V1 + #define configUSE_MPU_WRAPPERS_V1 0 +#endif + +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + PUBLIC MPU_xTaskDelayUntil +MPU_xTaskDelayUntil: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskDelayUntil_Unpriv + MPU_xTaskDelayUntil_Priv: + b MPU_xTaskDelayUntilImpl + MPU_xTaskDelayUntil_Unpriv: + svc #SYSTEM_CALL_xTaskDelayUntil +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskAbortDelay +MPU_xTaskAbortDelay: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskAbortDelay_Unpriv + MPU_xTaskAbortDelay_Priv: + b MPU_xTaskAbortDelayImpl + MPU_xTaskAbortDelay_Unpriv: + svc #SYSTEM_CALL_xTaskAbortDelay +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskDelay +MPU_vTaskDelay: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskDelay_Unpriv + MPU_vTaskDelay_Priv: + b MPU_vTaskDelayImpl + MPU_vTaskDelay_Unpriv: + svc #SYSTEM_CALL_vTaskDelay +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskPriorityGet +MPU_uxTaskPriorityGet: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskPriorityGet_Unpriv + MPU_uxTaskPriorityGet_Priv: + b MPU_uxTaskPriorityGetImpl + MPU_uxTaskPriorityGet_Unpriv: + svc #SYSTEM_CALL_uxTaskPriorityGet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_eTaskGetState +MPU_eTaskGetState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_eTaskGetState_Unpriv + MPU_eTaskGetState_Priv: + b MPU_eTaskGetStateImpl + MPU_eTaskGetState_Unpriv: + svc #SYSTEM_CALL_eTaskGetState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskGetInfo +MPU_vTaskGetInfo: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskGetInfo_Unpriv + MPU_vTaskGetInfo_Priv: + b MPU_vTaskGetInfoImpl + MPU_vTaskGetInfo_Unpriv: + svc #SYSTEM_CALL_vTaskGetInfo +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetIdleTaskHandle +MPU_xTaskGetIdleTaskHandle: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetIdleTaskHandle_Unpriv + MPU_xTaskGetIdleTaskHandle_Priv: + b MPU_xTaskGetIdleTaskHandleImpl + MPU_xTaskGetIdleTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTaskGetIdleTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSuspend +MPU_vTaskSuspend: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSuspend_Unpriv + MPU_vTaskSuspend_Priv: + b MPU_vTaskSuspendImpl + MPU_vTaskSuspend_Unpriv: + svc #SYSTEM_CALL_vTaskSuspend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskResume +MPU_vTaskResume: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskResume_Unpriv + MPU_vTaskResume_Priv: + b MPU_vTaskResumeImpl + MPU_vTaskResume_Unpriv: + svc #SYSTEM_CALL_vTaskResume +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetTickCount +MPU_xTaskGetTickCount: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetTickCount_Unpriv + MPU_xTaskGetTickCount_Priv: + b MPU_xTaskGetTickCountImpl + MPU_xTaskGetTickCount_Unpriv: + svc #SYSTEM_CALL_xTaskGetTickCount +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetNumberOfTasks +MPU_uxTaskGetNumberOfTasks: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetNumberOfTasks_Unpriv + MPU_uxTaskGetNumberOfTasks_Priv: + b MPU_uxTaskGetNumberOfTasksImpl + MPU_uxTaskGetNumberOfTasks_Unpriv: + svc #SYSTEM_CALL_uxTaskGetNumberOfTasks +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetRunTimeCounter +MPU_ulTaskGetRunTimeCounter: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetRunTimeCounter_Unpriv + MPU_ulTaskGetRunTimeCounter_Priv: + b MPU_ulTaskGetRunTimeCounterImpl + MPU_ulTaskGetRunTimeCounter_Unpriv: + svc #SYSTEM_CALL_ulTaskGetRunTimeCounter +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetRunTimePercent +MPU_ulTaskGetRunTimePercent: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetRunTimePercent_Unpriv + MPU_ulTaskGetRunTimePercent_Priv: + b MPU_ulTaskGetRunTimePercentImpl + MPU_ulTaskGetRunTimePercent_Unpriv: + svc #SYSTEM_CALL_ulTaskGetRunTimePercent +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetIdleRunTimePercent +MPU_ulTaskGetIdleRunTimePercent: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetIdleRunTimePercent_Unpriv + MPU_ulTaskGetIdleRunTimePercent_Priv: + b MPU_ulTaskGetIdleRunTimePercentImpl + MPU_ulTaskGetIdleRunTimePercent_Unpriv: + svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetIdleRunTimeCounter +MPU_ulTaskGetIdleRunTimeCounter: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv + MPU_ulTaskGetIdleRunTimeCounter_Priv: + b MPU_ulTaskGetIdleRunTimeCounterImpl + MPU_ulTaskGetIdleRunTimeCounter_Unpriv: + svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetApplicationTaskTag +MPU_vTaskSetApplicationTaskTag: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetApplicationTaskTag_Unpriv + MPU_vTaskSetApplicationTaskTag_Priv: + b MPU_vTaskSetApplicationTaskTagImpl + MPU_vTaskSetApplicationTaskTag_Unpriv: + svc #SYSTEM_CALL_vTaskSetApplicationTaskTag +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetApplicationTaskTag +MPU_xTaskGetApplicationTaskTag: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetApplicationTaskTag_Unpriv + MPU_xTaskGetApplicationTaskTag_Priv: + b MPU_xTaskGetApplicationTaskTagImpl + MPU_xTaskGetApplicationTaskTag_Unpriv: + svc #SYSTEM_CALL_xTaskGetApplicationTaskTag +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetThreadLocalStoragePointer +MPU_vTaskSetThreadLocalStoragePointer: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv + MPU_vTaskSetThreadLocalStoragePointer_Priv: + b MPU_vTaskSetThreadLocalStoragePointerImpl + MPU_vTaskSetThreadLocalStoragePointer_Unpriv: + svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pvTaskGetThreadLocalStoragePointer +MPU_pvTaskGetThreadLocalStoragePointer: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv + MPU_pvTaskGetThreadLocalStoragePointer_Priv: + b MPU_pvTaskGetThreadLocalStoragePointerImpl + MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: + svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetSystemState +MPU_uxTaskGetSystemState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetSystemState_Unpriv + MPU_uxTaskGetSystemState_Priv: + b MPU_uxTaskGetSystemStateImpl + MPU_uxTaskGetSystemState_Unpriv: + svc #SYSTEM_CALL_uxTaskGetSystemState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetStackHighWaterMark +MPU_uxTaskGetStackHighWaterMark: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetStackHighWaterMark_Unpriv + MPU_uxTaskGetStackHighWaterMark_Priv: + b MPU_uxTaskGetStackHighWaterMarkImpl + MPU_uxTaskGetStackHighWaterMark_Unpriv: + svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetStackHighWaterMark2 +MPU_uxTaskGetStackHighWaterMark2: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetStackHighWaterMark2_Unpriv + MPU_uxTaskGetStackHighWaterMark2_Priv: + b MPU_uxTaskGetStackHighWaterMark2Impl + MPU_uxTaskGetStackHighWaterMark2_Unpriv: + svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2 +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetCurrentTaskHandle +MPU_xTaskGetCurrentTaskHandle: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetCurrentTaskHandle_Unpriv + MPU_xTaskGetCurrentTaskHandle_Priv: + b MPU_xTaskGetCurrentTaskHandleImpl + MPU_xTaskGetCurrentTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetSchedulerState +MPU_xTaskGetSchedulerState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetSchedulerState_Unpriv + MPU_xTaskGetSchedulerState_Priv: + b MPU_xTaskGetSchedulerStateImpl + MPU_xTaskGetSchedulerState_Unpriv: + svc #SYSTEM_CALL_xTaskGetSchedulerState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetTimeOutState +MPU_vTaskSetTimeOutState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetTimeOutState_Unpriv + MPU_vTaskSetTimeOutState_Priv: + b MPU_vTaskSetTimeOutStateImpl + MPU_vTaskSetTimeOutState_Unpriv: + svc #SYSTEM_CALL_vTaskSetTimeOutState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskCheckForTimeOut +MPU_xTaskCheckForTimeOut: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskCheckForTimeOut_Unpriv + MPU_xTaskCheckForTimeOut_Priv: + b MPU_xTaskCheckForTimeOutImpl + MPU_xTaskCheckForTimeOut_Unpriv: + svc #SYSTEM_CALL_xTaskCheckForTimeOut +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyEntry +MPU_xTaskGenericNotifyEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotify_Unpriv + MPU_xTaskGenericNotify_Priv: + b MPU_xTaskGenericNotifyImpl + MPU_xTaskGenericNotify_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotify +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyWaitEntry +MPU_xTaskGenericNotifyWaitEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotifyWait_Unpriv + MPU_xTaskGenericNotifyWait_Priv: + b MPU_xTaskGenericNotifyWaitImpl + MPU_xTaskGenericNotifyWait_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotifyWait +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGenericNotifyTake +MPU_ulTaskGenericNotifyTake: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGenericNotifyTake_Unpriv + MPU_ulTaskGenericNotifyTake_Priv: + b MPU_ulTaskGenericNotifyTakeImpl + MPU_ulTaskGenericNotifyTake_Unpriv: + svc #SYSTEM_CALL_ulTaskGenericNotifyTake +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyStateClear +MPU_xTaskGenericNotifyStateClear: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotifyStateClear_Unpriv + MPU_xTaskGenericNotifyStateClear_Priv: + b MPU_xTaskGenericNotifyStateClearImpl + MPU_xTaskGenericNotifyStateClear_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotifyStateClear +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGenericNotifyValueClear +MPU_ulTaskGenericNotifyValueClear: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGenericNotifyValueClear_Unpriv + MPU_ulTaskGenericNotifyValueClear_Priv: + b MPU_ulTaskGenericNotifyValueClearImpl + MPU_ulTaskGenericNotifyValueClear_Unpriv: + svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGenericSend +MPU_xQueueGenericSend: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGenericSend_Unpriv + MPU_xQueueGenericSend_Priv: + b MPU_xQueueGenericSendImpl + MPU_xQueueGenericSend_Unpriv: + svc #SYSTEM_CALL_xQueueGenericSend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxQueueMessagesWaiting +MPU_uxQueueMessagesWaiting: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxQueueMessagesWaiting_Unpriv + MPU_uxQueueMessagesWaiting_Priv: + b MPU_uxQueueMessagesWaitingImpl + MPU_uxQueueMessagesWaiting_Unpriv: + svc #SYSTEM_CALL_uxQueueMessagesWaiting +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxQueueSpacesAvailable +MPU_uxQueueSpacesAvailable: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxQueueSpacesAvailable_Unpriv + MPU_uxQueueSpacesAvailable_Priv: + b MPU_uxQueueSpacesAvailableImpl + MPU_uxQueueSpacesAvailable_Unpriv: + svc #SYSTEM_CALL_uxQueueSpacesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueReceive +MPU_xQueueReceive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueReceive_Unpriv + MPU_xQueueReceive_Priv: + b MPU_xQueueReceiveImpl + MPU_xQueueReceive_Unpriv: + svc #SYSTEM_CALL_xQueueReceive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueuePeek +MPU_xQueuePeek: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueuePeek_Unpriv + MPU_xQueuePeek_Priv: + b MPU_xQueuePeekImpl + MPU_xQueuePeek_Unpriv: + svc #SYSTEM_CALL_xQueuePeek +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueSemaphoreTake +MPU_xQueueSemaphoreTake: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueSemaphoreTake_Unpriv + MPU_xQueueSemaphoreTake_Priv: + b MPU_xQueueSemaphoreTakeImpl + MPU_xQueueSemaphoreTake_Unpriv: + svc #SYSTEM_CALL_xQueueSemaphoreTake +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGetMutexHolder +MPU_xQueueGetMutexHolder: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGetMutexHolder_Unpriv + MPU_xQueueGetMutexHolder_Priv: + b MPU_xQueueGetMutexHolderImpl + MPU_xQueueGetMutexHolder_Unpriv: + svc #SYSTEM_CALL_xQueueGetMutexHolder +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueTakeMutexRecursive +MPU_xQueueTakeMutexRecursive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueTakeMutexRecursive_Unpriv + MPU_xQueueTakeMutexRecursive_Priv: + b MPU_xQueueTakeMutexRecursiveImpl + MPU_xQueueTakeMutexRecursive_Unpriv: + svc #SYSTEM_CALL_xQueueTakeMutexRecursive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGiveMutexRecursive +MPU_xQueueGiveMutexRecursive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGiveMutexRecursive_Unpriv + MPU_xQueueGiveMutexRecursive_Priv: + b MPU_xQueueGiveMutexRecursiveImpl + MPU_xQueueGiveMutexRecursive_Unpriv: + svc #SYSTEM_CALL_xQueueGiveMutexRecursive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueSelectFromSet +MPU_xQueueSelectFromSet: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueSelectFromSet_Unpriv + MPU_xQueueSelectFromSet_Priv: + b MPU_xQueueSelectFromSetImpl + MPU_xQueueSelectFromSet_Unpriv: + svc #SYSTEM_CALL_xQueueSelectFromSet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueAddToSet +MPU_xQueueAddToSet: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueAddToSet_Unpriv + MPU_xQueueAddToSet_Priv: + b MPU_xQueueAddToSetImpl + MPU_xQueueAddToSet_Unpriv: + svc #SYSTEM_CALL_xQueueAddToSet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vQueueAddToRegistry +MPU_vQueueAddToRegistry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vQueueAddToRegistry_Unpriv + MPU_vQueueAddToRegistry_Priv: + b MPU_vQueueAddToRegistryImpl + MPU_vQueueAddToRegistry_Unpriv: + svc #SYSTEM_CALL_vQueueAddToRegistry +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vQueueUnregisterQueue +MPU_vQueueUnregisterQueue: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vQueueUnregisterQueue_Unpriv + MPU_vQueueUnregisterQueue_Priv: + b MPU_vQueueUnregisterQueueImpl + MPU_vQueueUnregisterQueue_Unpriv: + svc #SYSTEM_CALL_vQueueUnregisterQueue +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pcQueueGetName +MPU_pcQueueGetName: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pcQueueGetName_Unpriv + MPU_pcQueueGetName_Priv: + b MPU_pcQueueGetNameImpl + MPU_pcQueueGetName_Unpriv: + svc #SYSTEM_CALL_pcQueueGetName +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pvTimerGetTimerID +MPU_pvTimerGetTimerID: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pvTimerGetTimerID_Unpriv + MPU_pvTimerGetTimerID_Priv: + b MPU_pvTimerGetTimerIDImpl + MPU_pvTimerGetTimerID_Unpriv: + svc #SYSTEM_CALL_pvTimerGetTimerID +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTimerSetTimerID +MPU_vTimerSetTimerID: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTimerSetTimerID_Unpriv + MPU_vTimerSetTimerID_Priv: + b MPU_vTimerSetTimerIDImpl + MPU_vTimerSetTimerID_Unpriv: + svc #SYSTEM_CALL_vTimerSetTimerID +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerIsTimerActive +MPU_xTimerIsTimerActive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerIsTimerActive_Unpriv + MPU_xTimerIsTimerActive_Priv: + b MPU_xTimerIsTimerActiveImpl + MPU_xTimerIsTimerActive_Unpriv: + svc #SYSTEM_CALL_xTimerIsTimerActive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetTimerDaemonTaskHandle +MPU_xTimerGetTimerDaemonTaskHandle: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv + MPU_xTimerGetTimerDaemonTaskHandle_Priv: + b MPU_xTimerGetTimerDaemonTaskHandleImpl + MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGenericCommandFromTaskEntry +MPU_xTimerGenericCommandFromTaskEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGenericCommandFromTask_Unpriv + MPU_xTimerGenericCommandFromTask_Priv: + b MPU_xTimerGenericCommandFromTaskImpl + MPU_xTimerGenericCommandFromTask_Unpriv: + svc #SYSTEM_CALL_xTimerGenericCommandFromTask +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pcTimerGetName +MPU_pcTimerGetName: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pcTimerGetName_Unpriv + MPU_pcTimerGetName_Priv: + b MPU_pcTimerGetNameImpl + MPU_pcTimerGetName_Unpriv: + svc #SYSTEM_CALL_pcTimerGetName +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTimerSetReloadMode +MPU_vTimerSetReloadMode: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTimerSetReloadMode_Unpriv + MPU_vTimerSetReloadMode_Priv: + b MPU_vTimerSetReloadModeImpl + MPU_vTimerSetReloadMode_Unpriv: + svc #SYSTEM_CALL_vTimerSetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetReloadMode +MPU_xTimerGetReloadMode: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetReloadMode_Unpriv + MPU_xTimerGetReloadMode_Priv: + b MPU_xTimerGetReloadModeImpl + MPU_xTimerGetReloadMode_Unpriv: + svc #SYSTEM_CALL_xTimerGetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTimerGetReloadMode +MPU_uxTimerGetReloadMode: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTimerGetReloadMode_Unpriv + MPU_uxTimerGetReloadMode_Priv: + b MPU_uxTimerGetReloadModeImpl + MPU_uxTimerGetReloadMode_Unpriv: + svc #SYSTEM_CALL_uxTimerGetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetPeriod +MPU_xTimerGetPeriod: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetPeriod_Unpriv + MPU_xTimerGetPeriod_Priv: + b MPU_xTimerGetPeriodImpl + MPU_xTimerGetPeriod_Unpriv: + svc #SYSTEM_CALL_xTimerGetPeriod +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetExpiryTime +MPU_xTimerGetExpiryTime: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetExpiryTime_Unpriv + MPU_xTimerGetExpiryTime_Priv: + b MPU_xTimerGetExpiryTimeImpl + MPU_xTimerGetExpiryTime_Unpriv: + svc #SYSTEM_CALL_xTimerGetExpiryTime +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupWaitBitsEntry +MPU_xEventGroupWaitBitsEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupWaitBits_Unpriv + MPU_xEventGroupWaitBits_Priv: + b MPU_xEventGroupWaitBitsImpl + MPU_xEventGroupWaitBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupWaitBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupClearBits +MPU_xEventGroupClearBits: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupClearBits_Unpriv + MPU_xEventGroupClearBits_Priv: + b MPU_xEventGroupClearBitsImpl + MPU_xEventGroupClearBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupClearBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupSetBits +MPU_xEventGroupSetBits: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupSetBits_Unpriv + MPU_xEventGroupSetBits_Priv: + b MPU_xEventGroupSetBitsImpl + MPU_xEventGroupSetBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupSetBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupSync +MPU_xEventGroupSync: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupSync_Unpriv + MPU_xEventGroupSync_Priv: + b MPU_xEventGroupSyncImpl + MPU_xEventGroupSync_Unpriv: + svc #SYSTEM_CALL_xEventGroupSync +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxEventGroupGetNumber +MPU_uxEventGroupGetNumber: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxEventGroupGetNumber_Unpriv + MPU_uxEventGroupGetNumber_Priv: + b MPU_uxEventGroupGetNumberImpl + MPU_uxEventGroupGetNumber_Unpriv: + svc #SYSTEM_CALL_uxEventGroupGetNumber +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vEventGroupSetNumber +MPU_vEventGroupSetNumber: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vEventGroupSetNumber_Unpriv + MPU_vEventGroupSetNumber_Priv: + b MPU_vEventGroupSetNumberImpl + MPU_vEventGroupSetNumber_Unpriv: + svc #SYSTEM_CALL_vEventGroupSetNumber +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSend +MPU_xStreamBufferSend: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSend_Unpriv + MPU_xStreamBufferSend_Priv: + b MPU_xStreamBufferSendImpl + MPU_xStreamBufferSend_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferReceive +MPU_xStreamBufferReceive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferReceive_Unpriv + MPU_xStreamBufferReceive_Priv: + b MPU_xStreamBufferReceiveImpl + MPU_xStreamBufferReceive_Unpriv: + svc #SYSTEM_CALL_xStreamBufferReceive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferIsFull +MPU_xStreamBufferIsFull: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferIsFull_Unpriv + MPU_xStreamBufferIsFull_Priv: + b MPU_xStreamBufferIsFullImpl + MPU_xStreamBufferIsFull_Unpriv: + svc #SYSTEM_CALL_xStreamBufferIsFull +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferIsEmpty +MPU_xStreamBufferIsEmpty: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferIsEmpty_Unpriv + MPU_xStreamBufferIsEmpty_Priv: + b MPU_xStreamBufferIsEmptyImpl + MPU_xStreamBufferIsEmpty_Unpriv: + svc #SYSTEM_CALL_xStreamBufferIsEmpty +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSpacesAvailable +MPU_xStreamBufferSpacesAvailable: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSpacesAvailable_Unpriv + MPU_xStreamBufferSpacesAvailable_Priv: + b MPU_xStreamBufferSpacesAvailableImpl + MPU_xStreamBufferSpacesAvailable_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSpacesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferBytesAvailable +MPU_xStreamBufferBytesAvailable: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferBytesAvailable_Unpriv + MPU_xStreamBufferBytesAvailable_Priv: + b MPU_xStreamBufferBytesAvailableImpl + MPU_xStreamBufferBytesAvailable_Unpriv: + svc #SYSTEM_CALL_xStreamBufferBytesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSetTriggerLevel +MPU_xStreamBufferSetTriggerLevel: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSetTriggerLevel_Unpriv + MPU_xStreamBufferSetTriggerLevel_Priv: + b MPU_xStreamBufferSetTriggerLevelImpl + MPU_xStreamBufferSetTriggerLevel_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferNextMessageLengthBytes +MPU_xStreamBufferNextMessageLengthBytes: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv + MPU_xStreamBufferNextMessageLengthBytes_Priv: + b MPU_xStreamBufferNextMessageLengthBytesImpl + MPU_xStreamBufferNextMessageLengthBytes_Unpriv: + svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes +/*-----------------------------------------------------------*/ + +/* Default weak implementations in case one is not available from + * mpu_wrappers because of config options. */ + + PUBWEAK MPU_xTaskDelayUntilImpl +MPU_xTaskDelayUntilImpl: + b MPU_xTaskDelayUntilImpl + + PUBWEAK MPU_xTaskAbortDelayImpl +MPU_xTaskAbortDelayImpl: + b MPU_xTaskAbortDelayImpl + + PUBWEAK MPU_vTaskDelayImpl +MPU_vTaskDelayImpl: + b MPU_vTaskDelayImpl + + PUBWEAK MPU_uxTaskPriorityGetImpl +MPU_uxTaskPriorityGetImpl: + b MPU_uxTaskPriorityGetImpl + + PUBWEAK MPU_eTaskGetStateImpl +MPU_eTaskGetStateImpl: + b MPU_eTaskGetStateImpl + + PUBWEAK MPU_vTaskGetInfoImpl +MPU_vTaskGetInfoImpl: + b MPU_vTaskGetInfoImpl + + PUBWEAK MPU_xTaskGetIdleTaskHandleImpl +MPU_xTaskGetIdleTaskHandleImpl: + b MPU_xTaskGetIdleTaskHandleImpl + + PUBWEAK MPU_vTaskSuspendImpl +MPU_vTaskSuspendImpl: + b MPU_vTaskSuspendImpl + + PUBWEAK MPU_vTaskResumeImpl +MPU_vTaskResumeImpl: + b MPU_vTaskResumeImpl + + PUBWEAK MPU_xTaskGetTickCountImpl +MPU_xTaskGetTickCountImpl: + b MPU_xTaskGetTickCountImpl + + PUBWEAK MPU_uxTaskGetNumberOfTasksImpl +MPU_uxTaskGetNumberOfTasksImpl: + b MPU_uxTaskGetNumberOfTasksImpl + + PUBWEAK MPU_ulTaskGetRunTimeCounterImpl +MPU_ulTaskGetRunTimeCounterImpl: + b MPU_ulTaskGetRunTimeCounterImpl + + PUBWEAK MPU_ulTaskGetRunTimePercentImpl +MPU_ulTaskGetRunTimePercentImpl: + b MPU_ulTaskGetRunTimePercentImpl + + PUBWEAK MPU_ulTaskGetIdleRunTimePercentImpl +MPU_ulTaskGetIdleRunTimePercentImpl: + b MPU_ulTaskGetIdleRunTimePercentImpl + + PUBWEAK MPU_ulTaskGetIdleRunTimeCounterImpl +MPU_ulTaskGetIdleRunTimeCounterImpl: + b MPU_ulTaskGetIdleRunTimeCounterImpl + + PUBWEAK MPU_vTaskSetApplicationTaskTagImpl +MPU_vTaskSetApplicationTaskTagImpl: + b MPU_vTaskSetApplicationTaskTagImpl + + PUBWEAK MPU_xTaskGetApplicationTaskTagImpl +MPU_xTaskGetApplicationTaskTagImpl: + b MPU_xTaskGetApplicationTaskTagImpl + + PUBWEAK MPU_vTaskSetThreadLocalStoragePointerImpl +MPU_vTaskSetThreadLocalStoragePointerImpl: + b MPU_vTaskSetThreadLocalStoragePointerImpl + + PUBWEAK MPU_pvTaskGetThreadLocalStoragePointerImpl +MPU_pvTaskGetThreadLocalStoragePointerImpl: + b MPU_pvTaskGetThreadLocalStoragePointerImpl + + PUBWEAK MPU_uxTaskGetSystemStateImpl +MPU_uxTaskGetSystemStateImpl: + b MPU_uxTaskGetSystemStateImpl + + PUBWEAK MPU_uxTaskGetStackHighWaterMarkImpl +MPU_uxTaskGetStackHighWaterMarkImpl: + b MPU_uxTaskGetStackHighWaterMarkImpl + + PUBWEAK MPU_uxTaskGetStackHighWaterMark2Impl +MPU_uxTaskGetStackHighWaterMark2Impl: + b MPU_uxTaskGetStackHighWaterMark2Impl + + PUBWEAK MPU_xTaskGetCurrentTaskHandleImpl +MPU_xTaskGetCurrentTaskHandleImpl: + b MPU_xTaskGetCurrentTaskHandleImpl + + PUBWEAK MPU_xTaskGetSchedulerStateImpl +MPU_xTaskGetSchedulerStateImpl: + b MPU_xTaskGetSchedulerStateImpl + + PUBWEAK MPU_vTaskSetTimeOutStateImpl +MPU_vTaskSetTimeOutStateImpl: + b MPU_vTaskSetTimeOutStateImpl + + PUBWEAK MPU_xTaskCheckForTimeOutImpl +MPU_xTaskCheckForTimeOutImpl: + b MPU_xTaskCheckForTimeOutImpl + + PUBWEAK MPU_xTaskGenericNotifyImpl +MPU_xTaskGenericNotifyImpl: + b MPU_xTaskGenericNotifyImpl + + PUBWEAK MPU_xTaskGenericNotifyWaitImpl +MPU_xTaskGenericNotifyWaitImpl: + b MPU_xTaskGenericNotifyWaitImpl + + PUBWEAK MPU_ulTaskGenericNotifyTakeImpl +MPU_ulTaskGenericNotifyTakeImpl: + b MPU_ulTaskGenericNotifyTakeImpl + + PUBWEAK MPU_xTaskGenericNotifyStateClearImpl +MPU_xTaskGenericNotifyStateClearImpl: + b MPU_xTaskGenericNotifyStateClearImpl + + PUBWEAK MPU_ulTaskGenericNotifyValueClearImpl +MPU_ulTaskGenericNotifyValueClearImpl: + b MPU_ulTaskGenericNotifyValueClearImpl + + PUBWEAK MPU_xQueueGenericSendImpl +MPU_xQueueGenericSendImpl: + b MPU_xQueueGenericSendImpl + + PUBWEAK MPU_uxQueueMessagesWaitingImpl +MPU_uxQueueMessagesWaitingImpl: + b MPU_uxQueueMessagesWaitingImpl + + PUBWEAK MPU_uxQueueSpacesAvailableImpl +MPU_uxQueueSpacesAvailableImpl: + b MPU_uxQueueSpacesAvailableImpl + + PUBWEAK MPU_xQueueReceiveImpl +MPU_xQueueReceiveImpl: + b MPU_xQueueReceiveImpl + + PUBWEAK MPU_xQueuePeekImpl +MPU_xQueuePeekImpl: + b MPU_xQueuePeekImpl + + PUBWEAK MPU_xQueueSemaphoreTakeImpl +MPU_xQueueSemaphoreTakeImpl: + b MPU_xQueueSemaphoreTakeImpl + + PUBWEAK MPU_xQueueGetMutexHolderImpl +MPU_xQueueGetMutexHolderImpl: + b MPU_xQueueGetMutexHolderImpl + + PUBWEAK MPU_xQueueTakeMutexRecursiveImpl +MPU_xQueueTakeMutexRecursiveImpl: + b MPU_xQueueTakeMutexRecursiveImpl + + PUBWEAK MPU_xQueueGiveMutexRecursiveImpl +MPU_xQueueGiveMutexRecursiveImpl: + b MPU_xQueueGiveMutexRecursiveImpl + + PUBWEAK MPU_xQueueSelectFromSetImpl +MPU_xQueueSelectFromSetImpl: + b MPU_xQueueSelectFromSetImpl + + PUBWEAK MPU_xQueueAddToSetImpl +MPU_xQueueAddToSetImpl: + b MPU_xQueueAddToSetImpl + + PUBWEAK MPU_vQueueAddToRegistryImpl +MPU_vQueueAddToRegistryImpl: + b MPU_vQueueAddToRegistryImpl + + PUBWEAK MPU_vQueueUnregisterQueueImpl +MPU_vQueueUnregisterQueueImpl: + b MPU_vQueueUnregisterQueueImpl + + PUBWEAK MPU_pcQueueGetNameImpl +MPU_pcQueueGetNameImpl: + b MPU_pcQueueGetNameImpl + + PUBWEAK MPU_pvTimerGetTimerIDImpl +MPU_pvTimerGetTimerIDImpl: + b MPU_pvTimerGetTimerIDImpl + + PUBWEAK MPU_vTimerSetTimerIDImpl +MPU_vTimerSetTimerIDImpl: + b MPU_vTimerSetTimerIDImpl + + PUBWEAK MPU_xTimerIsTimerActiveImpl +MPU_xTimerIsTimerActiveImpl: + b MPU_xTimerIsTimerActiveImpl + + PUBWEAK MPU_xTimerGetTimerDaemonTaskHandleImpl +MPU_xTimerGetTimerDaemonTaskHandleImpl: + b MPU_xTimerGetTimerDaemonTaskHandleImpl + + PUBWEAK MPU_xTimerGenericCommandFromTaskImpl +MPU_xTimerGenericCommandFromTaskImpl: + b MPU_xTimerGenericCommandFromTaskImpl + + PUBWEAK MPU_pcTimerGetNameImpl +MPU_pcTimerGetNameImpl: + b MPU_pcTimerGetNameImpl + + PUBWEAK MPU_vTimerSetReloadModeImpl +MPU_vTimerSetReloadModeImpl: + b MPU_vTimerSetReloadModeImpl + + PUBWEAK MPU_xTimerGetReloadModeImpl +MPU_xTimerGetReloadModeImpl: + b MPU_xTimerGetReloadModeImpl + + PUBWEAK MPU_uxTimerGetReloadModeImpl +MPU_uxTimerGetReloadModeImpl: + b MPU_uxTimerGetReloadModeImpl + + PUBWEAK MPU_xTimerGetPeriodImpl +MPU_xTimerGetPeriodImpl: + b MPU_xTimerGetPeriodImpl + + PUBWEAK MPU_xTimerGetExpiryTimeImpl +MPU_xTimerGetExpiryTimeImpl: + b MPU_xTimerGetExpiryTimeImpl + + PUBWEAK MPU_xEventGroupWaitBitsImpl +MPU_xEventGroupWaitBitsImpl: + b MPU_xEventGroupWaitBitsImpl + + PUBWEAK MPU_xEventGroupClearBitsImpl +MPU_xEventGroupClearBitsImpl: + b MPU_xEventGroupClearBitsImpl + + PUBWEAK MPU_xEventGroupSetBitsImpl +MPU_xEventGroupSetBitsImpl: + b MPU_xEventGroupSetBitsImpl + + PUBWEAK MPU_xEventGroupSyncImpl +MPU_xEventGroupSyncImpl: + b MPU_xEventGroupSyncImpl + + PUBWEAK MPU_uxEventGroupGetNumberImpl +MPU_uxEventGroupGetNumberImpl: + b MPU_uxEventGroupGetNumberImpl + + PUBWEAK MPU_vEventGroupSetNumberImpl +MPU_vEventGroupSetNumberImpl: + b MPU_vEventGroupSetNumberImpl + + PUBWEAK MPU_xStreamBufferSendImpl +MPU_xStreamBufferSendImpl: + b MPU_xStreamBufferSendImpl + + PUBWEAK MPU_xStreamBufferReceiveImpl +MPU_xStreamBufferReceiveImpl: + b MPU_xStreamBufferReceiveImpl + + PUBWEAK MPU_xStreamBufferIsFullImpl +MPU_xStreamBufferIsFullImpl: + b MPU_xStreamBufferIsFullImpl + + PUBWEAK MPU_xStreamBufferIsEmptyImpl +MPU_xStreamBufferIsEmptyImpl: + b MPU_xStreamBufferIsEmptyImpl + + PUBWEAK MPU_xStreamBufferSpacesAvailableImpl +MPU_xStreamBufferSpacesAvailableImpl: + b MPU_xStreamBufferSpacesAvailableImpl + + PUBWEAK MPU_xStreamBufferBytesAvailableImpl +MPU_xStreamBufferBytesAvailableImpl: + b MPU_xStreamBufferBytesAvailableImpl + + PUBWEAK MPU_xStreamBufferSetTriggerLevelImpl +MPU_xStreamBufferSetTriggerLevelImpl: + b MPU_xStreamBufferSetTriggerLevelImpl + + PUBWEAK MPU_xStreamBufferNextMessageLengthBytesImpl +MPU_xStreamBufferNextMessageLengthBytesImpl: + b MPU_xStreamBufferNextMessageLengthBytesImpl + +/*-----------------------------------------------------------*/ + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + END diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c new file mode 100644 index 000000000..76d2b2445 --- /dev/null +++ b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c @@ -0,0 +1,2280 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024-2025 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU includes. */ +#include "mpu_wrappers.h" +#include "mpu_syscall_numbers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration settings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to check the validity of an interrupt priority. + */ +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) ) +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used during system call enter and exit. + */ +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Offsets in the stack to the parameters when inside the SVC handler. + */ +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +#if ( portARMV8M_MINOR_VERSION >= 1 ) + + /* Enable Privileged eXecute Never MPU attribute for the selected memory + * region. */ + #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL ) +#endif /* portARMV8M_MINOR_VERSION >= 1 */ + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Extract first address of the MPU region as encoded in the + * RBAR (Region Base Address Register) value. */ +#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \ + ( ( rbar ) & portMPU_RBAR_ADDRESS_MASK ) + +/* Extract last address of the MPU region as encoded in the + * RLAR (Region Limit Address Register) value. */ +#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \ + ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK ) + +/* Does addr lies within [start, end] address range? */ +#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \ + ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) ) + +/* Is the access request satisfied by the available permissions? */ +#define portIS_AUTHORIZED( accessRequest, permissions ) \ + ( ( ( permissions ) & ( accessRequest ) ) == accessRequest ) + +/* Max value that fits in a uint32_t type. */ +#define portUINT32_MAX ( ~( ( uint32_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. + */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 + +/** + * @brief Constants required to check and configure PACBTI security feature implementation. + */ +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) ) + + #define portCONTROL_UPAC_EN ( 1UL << 7UL ) + #define portCONTROL_PAC_EN ( 1UL << 6UL ) + #define portCONTROL_UBTI_EN ( 1UL << 5UL ) + #define portCONTROL_BTI_EN ( 1UL << 4UL ) + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Extract MPU region's access permissions from the Region Base Address + * Register (RBAR) value. + * + * @param ulRBARValue RBAR value for the MPU region. + * + * @return uint32_t Access permissions. + */ + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + + /** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + /** + * @brief Configures PACBTI features. + * + * This function configures the Pointer Authentication, and Branch Target + * Identification security features as per the user configuration. It returns + * the value of the special purpose CONTROL register accordingly, and optionally + * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M + * architecture based) target supports PACBTI security feature. + * + * @param xWriteControlRegister Used to control whether the special purpose + * CONTROL register should be updated or not. + * + * @return CONTROL register value according to the configured PACBTI option. + */ + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the system call stack so that upon returning from + * SVC, the system call stack is used. + * + * @param pulTaskStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + * @param ucSystemCallNumber The system call number of the system call. + */ + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Raise SVC for exiting from a system call. + */ + void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief This variable is set to pdTRUE when the scheduler is started. + */ + PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + + /** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +/** + * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + /** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + + /** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + + /** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the cpsid instruction + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessPermissions = 0; + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_ONLY ) + { + ulAccessPermissions = tskMPU_READ_PERMISSION; + } + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_WRITE ) + { + ulAccessPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION ); + } + + return ulAccessPermissions; + } + +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } + +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ portOFFSET_TO_PC ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ]; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulSystemCallStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the system call section (i.e. application is + * not raising SVC directly). + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as + * it is non-NULL only during the execution of a system call (i.e. + * between system call enter and exit). + * 3. System call is not for a kernel API disabled by the configuration + * in FreeRTOSConfig.h. + * 4. We do not need to check that ucSystemCallNumber is within range + * because the assembly SVC handler checks that before calling + * this function. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) && + ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) ) + { + pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the system call stack for the stack frame. */ + pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulSystemCallStack[ i ] = pulTaskStack[ i ]; + } + + /* Store the value of the Link Register before the SVC was raised. + * It contains the address of the caller of the System Call entry + * point (i.e. the caller of the MPU_). We need to restore it + * when we exit from the system call. */ + pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; + + /* Store the value of the PSPLIM register before the SVC was raised. + * We need to restore it when we exit from the system call. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* Use the pulSystemCallStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif + + /* Start executing the system call upon returning from this handler. */ + pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; + + /* Raise a request to exit from the system call upon finishing the + * system call. */ + pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; + + /* Remember the location where we should copy the stack frame when we exit from + * the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize; + + /* Record if the hardware used padding to force the stack pointer + * to be double word aligned. */ + if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK ) + { + pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG; + } + else + { + pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG ); + } + + /* We ensure in pxPortInitialiseStack that the system call stack is + * double word aligned and therefore, there is no need of padding. + * Clear the bit[9] of stacked xPSR. */ + pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + + /* Raise the privilege for the duration of the system call. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " bics r0, r1 \n" /* Clear nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */ + { + __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulTaskStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the privileged code (i.e. application is not + * raising SVC directly). This SVC is only raised from + * vRequestSystemCallExit which is in the privileged code section. + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL - + * this means that we previously entered a system call and the + * application is not attempting to exit without entering a system + * call. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) ) + { + pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the task stack for the stack frame. */ + pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulTaskStack[ i ] = pulSystemCallStack[ i ]; + } + + /* Use the pulTaskStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) ); + + /* Return to the caller of the System Call entry point (i.e. the + * caller of the MPU_). */ + pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + /* Ensure that LR has a valid value.*/ + pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + + /* Restore the PSPLIM register to what it was at the time of + * system call entry. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* If the hardware used padding to force the stack pointer + * to be double word aligned, set the stacked xPSR bit[9], + * otherwise clear it. */ + if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG ) + { + pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK; + } + else + { + pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + } + + /* This is not NULL only for the duration of the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; + + /* Drop the privilege before returning to the thread mode. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " orrs r0, r1 \n" /* Set nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xTaskIsPrivileged = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xTaskIsPrivileged = pdTRUE; + } + + return xTaskIsPrivileged; + } + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged, + xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulIndex = 0; + uint32_t ulControl = 0x0; + + xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ + ulIndex++; + + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + ulIndex++; + + #if ( configENABLE_TRUSTZONE == 1 ) + { + xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */ + ulIndex++; + } + #endif /* configENABLE_TRUSTZONE */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + ulIndex++; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Check PACBTI security feature configuration before pushing the + * CONTROL register's value on task's TCB. */ + ulControl = prvConfigurePACBTI( pdFALSE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + if( xRunPrivileged == pdTRUE ) + { + xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + else + { + xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG ); + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ + ulIndex++; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + { + /* Ensure that the system call stack is double word aligned. */ + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) + + ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + /* This is not NULL only for the duration of a system call. */ + xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL; + } + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ]; + ulIndex++; + } + } + #endif /* configENABLE_PAC */ + + return &( xMPUSettings->ulContext[ ulIndex ] ); + } + +#else /* configENABLE_MPU */ + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ + { + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + pxTopOfStack--; + *pxTopOfStack = ulTaskPacKey[ i ]; + } + } + #endif /* configENABLE_PAC */ + + return pxTopOfStack; + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Set the CONTROL register value based on PACBTI security feature + * configuration before starting the first task. */ + ( void ) prvConfigurePACBTI( pdTRUE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + { + xSchedulerRunning = pdTRUE; + } + #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + configSTACK_DEPTH_TYPE uxStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( uxStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* PXN. */ + #if ( portARMV8M_MINOR_VERSION >= 1 ) + { + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ); + } + } + #endif /* portARMV8M_MINOR_VERSION >= 1 */ + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, + uint32_t ulBufferLength, + uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */ + + { + uint32_t i, ulBufferStartAddress, ulBufferEndAddress; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE ) + { + ulBufferStartAddress = ( uint32_t ) pvBuffer; + ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL ); + + for( i = 0; i < portTOTAL_NUM_REGIONS; i++ ) + { + /* Is the MPU region enabled? */ + if( ( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR & portMPU_RLAR_REGION_ENABLE ) == portMPU_RLAR_REGION_ENABLE ) + { + if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_AUTHORIZED( ulAccessRequested, + prvGetRegionAccessPermissions( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ) ) ) + { + xAccessGranted = pdTRUE; + break; + } + } + } + } + } + + return xAccessGranted; + } + +#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings; + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else + { + xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 ) + { + xAccessGranted = pdTRUE; + } + } + } + + return xAccessGranted; + } + + #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + ( void ) lInternalIndexOfKernelObject; + + /* If Access Control List feature is not used, all the tasks have + * access to all the kernel objects. */ + return pdTRUE; + } + + #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + { + uint32_t ulControl = 0x0; + + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); + + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; + + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h b/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h new file mode 100644 index 000000000..b7021b024 --- /dev/null +++ b/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kernel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s b/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s new file mode 100644 index 000000000..ba6e8e915 --- /dev/null +++ b/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s @@ -0,0 +1,456 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" + +/* System call numbers includes. */ +#include "mpu_syscall_numbers.h" + +#ifndef configUSE_MPU_WRAPPERS_V1 + #define configUSE_MPU_WRAPPERS_V1 0 +#endif + + EXTERN pxCurrentTCB + EXTERN vTaskSwitchContext + EXTERN vPortSVCHandler_C +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + EXTERN vSystemCallEnter + EXTERN vSystemCallExit +#endif + + PUBLIC xIsPrivileged + PUBLIC vResetPrivilege + PUBLIC vRestoreContextOfFirstTask + PUBLIC vRaisePrivilege + PUBLIC vStartFirstTask + PUBLIC ulSetInterruptMask + PUBLIC vClearInterruptMask + PUBLIC PendSV_Handler + PUBLIC SVC_Handler +/*-----------------------------------------------------------*/ + +/*---------------- Unprivileged Functions -------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION .text:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +xIsPrivileged: + mrs r0, control /* r0 = CONTROL. */ + tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + ite ne + movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vResetPrivilege: + mrs r0, control /* r0 = CONTROL. */ + orr r0, r0, #1 /* r0 = r0 | 1. */ + msr control, r0 /* CONTROL = r0. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +/*----------------- Privileged Functions --------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION privileged_functions:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +vRestoreContextOfFirstTask: + program_mpu_first_task: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r2] /* r0 = pxCurrentTCB. */ + + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + str r2, [r1] /* Disable MPU. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r1, [r2] /* Program MAIR0. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + + movs r3, #4 /* r3 = 4. */ + str r3, [r1] /* Program RNR = 4. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + #if ( configTOTAL_MPU_REGIONS == 16 ) + movs r3, #8 /* r3 = 8. */ + str r3, [r1] /* Program RNR = 8. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + movs r3, #12 /* r3 = 12. */ + str r3, [r1] /* Program RNR = 12. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + orr r2, #1 /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */ + str r2, [r1] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + + restore_context_first_task: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r2] /* r0 = pxCurrentTCB.*/ + ldr r1, [r0] /* r1 = Location of saved context in TCB. */ + + restore_special_regs_first_task: + #if ( configENABLE_PAC == 1 ) + ldmdb r1!, {r2-r5} /* Read task's dedicated PAC key from the task's context. */ + msr PAC_KEY_P_0, r2 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_1, r3 + msr PAC_KEY_P_2, r4 + msr PAC_KEY_P_3, r5 + clrm {r2-r5} /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + ldmdb r1!, {r2-r4, lr} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */ + msr psp, r2 + msr psplim, r3 + msr control, r4 + + restore_general_regs_first_task: + ldmdb r1!, {r4-r11} /* r4-r11 contain hardware saved context. */ + stmia r2!, {r4-r11} /* Copy the hardware saved context on the task stack. */ + ldmdb r1!, {r4-r11} /* r4-r11 restored. */ + + restore_context_done_first_task: + str r1, [r0] /* Save the location where the context should be saved next as the first member of TCB. */ + mov r0, #0 + msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ + bx lr + +#else /* configENABLE_MPU */ + +vRestoreContextOfFirstTask: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + +#if ( configENABLE_PAC == 1 ) + ldmia r0!, {r1-r4} /* Read task's dedicated PAC key from stack. */ + msr PAC_KEY_P_3, r1 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_2, r2 + msr PAC_KEY_P_1, r3 + msr PAC_KEY_P_0, r4 + clrm {r1-r4} /* Clear r1-r4. */ +#endif /* configENABLE_PAC */ + + ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */ + msr psplim, r1 /* Set this task's PSPLIM value. */ + mrs r1, control /* Obtain current control register value. */ + orrs r1, r1, #2 /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */ + msr control, r1 /* Write back the new control register value. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + mov r0, #0 + msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ + bx r2 /* Finally, branch to EXC_RETURN. */ + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +vRaisePrivilege: + mrs r0, control /* Read the CONTROL register. */ + bic r0, r0, #1 /* Clear the bit 0. */ + msr control, r0 /* Write back the new CONTROL value. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vStartFirstTask: + ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */ + ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */ + ldr r0, [r0] /* The first entry in vector table is stack pointer. */ + msr msp, r0 /* Set the MSP back to the start of the stack. */ + cpsie i /* Globally enable interrupts. */ + cpsie f + dsb + isb + svc 102 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */ +/*-----------------------------------------------------------*/ + +ulSetInterruptMask: + mrs r0, basepri /* r0 = basepri. Return original basepri value. */ + mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r1 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vClearInterruptMask: + msr basepri, r0 /* basepri = ulMask. */ + dsb + isb + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +PendSV_Handler: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r2] /* r0 = pxCurrentTCB. */ + ldr r1, [r0] /* r1 = Location in TCB where the context should be saved. */ + mrs r2, psp /* r2 = PSP. */ + + save_general_regs: + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + add r2, r2, #0x20 /* Move r2 to location where s0 is saved. */ + tst lr, #0x10 + ittt eq + vstmiaeq r1!, {s16-s31} /* Store s16-s31. */ + vldmiaeq r2, {s0-s16} /* Copy hardware saved FP context into s0-s16. */ + vstmiaeq r1!, {s0-s16} /* Store hardware saved FP context. */ + sub r2, r2, #0x20 /* Set r2 back to the location of hardware saved context. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + stmia r1!, {r4-r11} /* Store r4-r11. */ + ldmia r2, {r4-r11} /* Copy the hardware saved context into r4-r11. */ + stmia r1!, {r4-r11} /* Store the hardware saved context. */ + + save_special_regs: + mrs r3, psplim /* r3 = PSPLIM. */ + mrs r4, control /* r4 = CONTROL. */ + stmia r1!, {r2-r4, lr} /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ + #if ( configENABLE_PAC == 1 ) + mrs r2, PAC_KEY_P_0 /* Read task's dedicated PAC key from the PAC key registers. */ + mrs r3, PAC_KEY_P_1 + mrs r4, PAC_KEY_P_2 + mrs r5, PAC_KEY_P_3 + stmia r1!, {r2-r5} /* Store the task's dedicated PAC key on the task's context. */ + clrm {r2-r5} /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + + str r1, [r0] /* Save the location from where the context should be restored as the first member of TCB. */ + + select_next_task: + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bl vTaskSwitchContext + mov r0, #0 /* r0 = 0. */ + msr basepri, r0 /* Enable interrupts. */ + + program_mpu: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r2] /* r0 = pxCurrentTCB. */ + + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + str r2, [r1] /* Disable MPU. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r1, [r2] /* Program MAIR0. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + + movs r3, #4 /* r3 = 4. */ + str r3, [r1] /* Program RNR = 4. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + #if ( configTOTAL_MPU_REGIONS == 16 ) + movs r3, #8 /* r3 = 8. */ + str r3, [r1] /* Program RNR = 8. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + movs r3, #12 /* r3 = 12. */ + str r3, [r1] /* Program RNR = 12. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + orr r2, #1 /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */ + str r2, [r1] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + + restore_context: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r2] /* r0 = pxCurrentTCB.*/ + ldr r1, [r0] /* r1 = Location of saved context in TCB. */ + + restore_special_regs: + #if ( configENABLE_PAC == 1 ) + ldmdb r1!, {r2-r5} /* Read task's dedicated PAC key from the task's context. */ + msr PAC_KEY_P_0, r2 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_1, r3 + msr PAC_KEY_P_2, r4 + msr PAC_KEY_P_3, r5 + clrm {r2-r5} /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + ldmdb r1!, {r2-r4, lr} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */ + msr psp, r2 + msr psplim, r3 + msr control, r4 + + restore_general_regs: + ldmdb r1!, {r4-r11} /* r4-r11 contain hardware saved context. */ + stmia r2!, {r4-r11} /* Copy the hardware saved context on the task stack. */ + ldmdb r1!, {r4-r11} /* r4-r11 restored. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 + ittt eq + vldmdbeq r1!, {s0-s16} /* s0-s16 contain hardware saved FP context. */ + vstmiaeq r2!, {s0-s16} /* Copy hardware saved FP context on the task stack. */ + vldmdbeq r1!, {s16-s31} /* Restore s16-s31. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + + restore_context_done: + str r1, [r0] /* Save the location where the context should be saved next as the first member of TCB. */ + bx lr + +#else /* configENABLE_MPU */ + +PendSV_Handler: + mrs r0, psp /* Read PSP in r0. */ +#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + it eq + vstmdbeq r0!, {s16-s31} /* Store the additional FP context registers which are not saved automatically. */ +#endif /* configENABLE_FPU || configENABLE_MVE */ + + mrs r2, psplim /* r2 = PSPLIM. */ + mov r3, lr /* r3 = LR/EXC_RETURN. */ + stmdb r0!, {r2-r11} /* Store on the stack - PSPLIM, LR and registers that are not automatically. */ + +#if ( configENABLE_PAC == 1 ) + mrs r1, PAC_KEY_P_3 /* Read task's dedicated PAC key from the PAC key registers. */ + mrs r2, PAC_KEY_P_2 + mrs r3, PAC_KEY_P_1 + mrs r4, PAC_KEY_P_0 + stmdb r0!, {r1-r4} /* Store the task's dedicated PAC key on the stack. */ + clrm {r1-r4} /* Clear r1-r4. */ +#endif /* configENABLE_PAC */ + + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + str r0, [r1] /* Save the new top of stack in TCB. */ + + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bl vTaskSwitchContext + mov r0, #0 /* r0 = 0. */ + msr basepri, r0 /* Enable interrupts. */ + + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ + +#if ( configENABLE_PAC == 1 ) + ldmia r0!, {r2-r5} /* Read task's dedicated PAC key from stack. */ + msr PAC_KEY_P_3, r2 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_2, r3 + msr PAC_KEY_P_1, r4 + msr PAC_KEY_P_0, r5 + clrm {r2-r5} /* Clear r2-r5. */ +#endif /* configENABLE_PAC */ + + ldmia r0!, {r2-r11} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */ + +#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst r3, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + it eq + vldmiaeq r0!, {s16-s31} /* Restore the additional FP context registers which are not restored automatically. */ +#endif /* configENABLE_FPU || configENABLE_MVE */ + + msr psplim, r2 /* Restore the PSPLIM register value for the task. */ + msr psp, r0 /* Remember the new top of stack for the task. */ + bx r3 + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + +SVC_Handler: + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + + ldr r1, [r0, #24] + ldrb r2, [r1, #-2] + cmp r2, #NUM_SYSTEM_CALLS + blt syscall_enter + cmp r2, #104 /* portSVC_SYSTEM_CALL_EXIT. */ + beq syscall_exit + b vPortSVCHandler_C + + syscall_enter: + mov r1, lr + b vSystemCallEnter + + syscall_exit: + mov r1, lr + b vSystemCallExit + +#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +SVC_Handler: + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + b vPortSVCHandler_C + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + + END diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h new file mode 100644 index 000000000..53b668b5b --- /dev/null +++ b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h @@ -0,0 +1,88 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M33" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portARMV8M_MINOR_VERSION 0 +#define portDONT_DISCARD __root +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +#ifndef configENABLE_MVE + #define configENABLE_MVE 0 +#elif ( configENABLE_MVE != 0 ) + #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M33. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ +#pragma diag_suppress=Be006 +#pragma diag_suppress=Pa082 +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h new file mode 100644 index 000000000..f373bcad5 --- /dev/null +++ b/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h @@ -0,0 +1,582 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACROCOMMON_H +#define PORTMACROCOMMON_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. +#endif /* configENABLE_FPU */ + +#ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. +#endif /* configENABLE_MPU */ + +#ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. +#endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() +#define portINLINE __inline +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif +#define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ +extern BaseType_t xPortIsInsideInterrupt( void ); + +extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + +extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; +extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + +extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; +extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + +#if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_PAC == 1 ) + + /** + * @brief Generates 128-bit task's random PAC key. + * + * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be + * filled with a 128-bit random number. + */ + void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); + +#endif /* configENABLE_PAC */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ +#if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) +#else + #define portPRIVILEGE_BIT ( 0x0UL ) +#endif /* configENABLE_MPU */ + +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ +#define portPRIVILEGED_FLASH_REGION ( 0UL ) +#define portUNPRIVILEGED_FLASH_REGION ( 1UL ) +#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) +#define portPRIVILEGED_RAM_REGION ( 3UL ) +#define portSTACK_REGION ( 4UL ) +#define portFIRST_CONFIGURABLE_REGION ( 5UL ) +#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) +#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) +#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ +#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ +#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ +#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ +#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ +#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ +#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ +#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) +#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) +#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + +#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) +#define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) +#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) +#define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + +#define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + #ifndef configSYSTEM_CALL_STACK_SIZE + #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. + #endif + + /** + * @brief System call stack. + */ + typedef struct SYSTEM_CALL_STACK_INFO + { + uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; + uint32_t * pulSystemCallStack; + uint32_t * pulSystemCallStackLimit; + uint32_t * pulTaskStack; + uint32_t ulLinkRegisterAtSystemCallEntry; + uint32_t ulStackLimitRegisterAtSystemCallEntry; + } xSYSTEM_CALL_STACK_INFO; + + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + /** + * @brief MPU settings as stored in the TCB. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><-----------><----> + * 16 17 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 71 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 17 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 55 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | | | PC, xPSR | EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><-----------><----> + * 16 17 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 70 + + #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + /* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 17 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 54 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+------------------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +----------+-----------------+------------------------------+------------+-----+ + * + * <---------><----------------><------------------------------><-----------><----> + * 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 38 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+----------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | PC, xPSR | EXC_RETURN | | | + * +----------+-----------------+----------------------+------------+-----+ + * + * <---------><----------------><----------------------><-----------><----> + * 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 37 + + #else /* #if( configENABLE_TRUSTZONE == 1 ) */ + + /* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) + + /* Size of an Access Control List (ACL) entry in bits. */ + #define portACL_ENTRY_SIZE_BITS ( 32U ) + + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + uint32_t ulContext[ MAX_CONTEXT_SIZE ]; + uint32_t ulTaskFlags; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo; + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ]; + #endif + #endif + } xMPU_SETTINGS; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Validate priority of ISRs that are allowed to call FreeRTOS + * system calls. + */ +#if ( configASSERT_DEFINED == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif +#endif + +/** + * @brief SVC numbers. + */ +#define portSVC_ALLOCATE_SECURE_CONTEXT 100 +#define portSVC_FREE_SECURE_CONTEXT 101 +#define portSVC_START_SCHEDULER 102 +#define portSVC_RAISE_PRIVILEGE 103 +#define portSVC_SYSTEM_CALL_EXIT 104 +#define portSVC_YIELD 105 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) +#endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() +#else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + extern BaseType_t xPortIsTaskPrivileged( void ); + +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACROCOMMON_H */ diff --git a/portable/IAR/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.S new file mode 100644 index 000000000..d2cb78e92 --- /dev/null +++ b/portable/IAR/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.S @@ -0,0 +1,1242 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + + SECTION freertos_system_calls:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +#include "FreeRTOSConfig.h" +#include "mpu_syscall_numbers.h" + +#ifndef configUSE_MPU_WRAPPERS_V1 + #define configUSE_MPU_WRAPPERS_V1 0 +#endif + +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + PUBLIC MPU_xTaskDelayUntil +MPU_xTaskDelayUntil: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskDelayUntil_Unpriv + MPU_xTaskDelayUntil_Priv: + b MPU_xTaskDelayUntilImpl + MPU_xTaskDelayUntil_Unpriv: + svc #SYSTEM_CALL_xTaskDelayUntil +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskAbortDelay +MPU_xTaskAbortDelay: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskAbortDelay_Unpriv + MPU_xTaskAbortDelay_Priv: + b MPU_xTaskAbortDelayImpl + MPU_xTaskAbortDelay_Unpriv: + svc #SYSTEM_CALL_xTaskAbortDelay +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskDelay +MPU_vTaskDelay: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskDelay_Unpriv + MPU_vTaskDelay_Priv: + b MPU_vTaskDelayImpl + MPU_vTaskDelay_Unpriv: + svc #SYSTEM_CALL_vTaskDelay +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskPriorityGet +MPU_uxTaskPriorityGet: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskPriorityGet_Unpriv + MPU_uxTaskPriorityGet_Priv: + b MPU_uxTaskPriorityGetImpl + MPU_uxTaskPriorityGet_Unpriv: + svc #SYSTEM_CALL_uxTaskPriorityGet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_eTaskGetState +MPU_eTaskGetState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_eTaskGetState_Unpriv + MPU_eTaskGetState_Priv: + b MPU_eTaskGetStateImpl + MPU_eTaskGetState_Unpriv: + svc #SYSTEM_CALL_eTaskGetState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskGetInfo +MPU_vTaskGetInfo: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskGetInfo_Unpriv + MPU_vTaskGetInfo_Priv: + b MPU_vTaskGetInfoImpl + MPU_vTaskGetInfo_Unpriv: + svc #SYSTEM_CALL_vTaskGetInfo +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetIdleTaskHandle +MPU_xTaskGetIdleTaskHandle: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetIdleTaskHandle_Unpriv + MPU_xTaskGetIdleTaskHandle_Priv: + b MPU_xTaskGetIdleTaskHandleImpl + MPU_xTaskGetIdleTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTaskGetIdleTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSuspend +MPU_vTaskSuspend: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSuspend_Unpriv + MPU_vTaskSuspend_Priv: + b MPU_vTaskSuspendImpl + MPU_vTaskSuspend_Unpriv: + svc #SYSTEM_CALL_vTaskSuspend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskResume +MPU_vTaskResume: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskResume_Unpriv + MPU_vTaskResume_Priv: + b MPU_vTaskResumeImpl + MPU_vTaskResume_Unpriv: + svc #SYSTEM_CALL_vTaskResume +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetTickCount +MPU_xTaskGetTickCount: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetTickCount_Unpriv + MPU_xTaskGetTickCount_Priv: + b MPU_xTaskGetTickCountImpl + MPU_xTaskGetTickCount_Unpriv: + svc #SYSTEM_CALL_xTaskGetTickCount +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetNumberOfTasks +MPU_uxTaskGetNumberOfTasks: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetNumberOfTasks_Unpriv + MPU_uxTaskGetNumberOfTasks_Priv: + b MPU_uxTaskGetNumberOfTasksImpl + MPU_uxTaskGetNumberOfTasks_Unpriv: + svc #SYSTEM_CALL_uxTaskGetNumberOfTasks +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetRunTimeCounter +MPU_ulTaskGetRunTimeCounter: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetRunTimeCounter_Unpriv + MPU_ulTaskGetRunTimeCounter_Priv: + b MPU_ulTaskGetRunTimeCounterImpl + MPU_ulTaskGetRunTimeCounter_Unpriv: + svc #SYSTEM_CALL_ulTaskGetRunTimeCounter +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetRunTimePercent +MPU_ulTaskGetRunTimePercent: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetRunTimePercent_Unpriv + MPU_ulTaskGetRunTimePercent_Priv: + b MPU_ulTaskGetRunTimePercentImpl + MPU_ulTaskGetRunTimePercent_Unpriv: + svc #SYSTEM_CALL_ulTaskGetRunTimePercent +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetIdleRunTimePercent +MPU_ulTaskGetIdleRunTimePercent: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetIdleRunTimePercent_Unpriv + MPU_ulTaskGetIdleRunTimePercent_Priv: + b MPU_ulTaskGetIdleRunTimePercentImpl + MPU_ulTaskGetIdleRunTimePercent_Unpriv: + svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetIdleRunTimeCounter +MPU_ulTaskGetIdleRunTimeCounter: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv + MPU_ulTaskGetIdleRunTimeCounter_Priv: + b MPU_ulTaskGetIdleRunTimeCounterImpl + MPU_ulTaskGetIdleRunTimeCounter_Unpriv: + svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetApplicationTaskTag +MPU_vTaskSetApplicationTaskTag: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetApplicationTaskTag_Unpriv + MPU_vTaskSetApplicationTaskTag_Priv: + b MPU_vTaskSetApplicationTaskTagImpl + MPU_vTaskSetApplicationTaskTag_Unpriv: + svc #SYSTEM_CALL_vTaskSetApplicationTaskTag +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetApplicationTaskTag +MPU_xTaskGetApplicationTaskTag: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetApplicationTaskTag_Unpriv + MPU_xTaskGetApplicationTaskTag_Priv: + b MPU_xTaskGetApplicationTaskTagImpl + MPU_xTaskGetApplicationTaskTag_Unpriv: + svc #SYSTEM_CALL_xTaskGetApplicationTaskTag +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetThreadLocalStoragePointer +MPU_vTaskSetThreadLocalStoragePointer: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv + MPU_vTaskSetThreadLocalStoragePointer_Priv: + b MPU_vTaskSetThreadLocalStoragePointerImpl + MPU_vTaskSetThreadLocalStoragePointer_Unpriv: + svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pvTaskGetThreadLocalStoragePointer +MPU_pvTaskGetThreadLocalStoragePointer: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv + MPU_pvTaskGetThreadLocalStoragePointer_Priv: + b MPU_pvTaskGetThreadLocalStoragePointerImpl + MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: + svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetSystemState +MPU_uxTaskGetSystemState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetSystemState_Unpriv + MPU_uxTaskGetSystemState_Priv: + b MPU_uxTaskGetSystemStateImpl + MPU_uxTaskGetSystemState_Unpriv: + svc #SYSTEM_CALL_uxTaskGetSystemState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetStackHighWaterMark +MPU_uxTaskGetStackHighWaterMark: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetStackHighWaterMark_Unpriv + MPU_uxTaskGetStackHighWaterMark_Priv: + b MPU_uxTaskGetStackHighWaterMarkImpl + MPU_uxTaskGetStackHighWaterMark_Unpriv: + svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetStackHighWaterMark2 +MPU_uxTaskGetStackHighWaterMark2: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetStackHighWaterMark2_Unpriv + MPU_uxTaskGetStackHighWaterMark2_Priv: + b MPU_uxTaskGetStackHighWaterMark2Impl + MPU_uxTaskGetStackHighWaterMark2_Unpriv: + svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2 +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetCurrentTaskHandle +MPU_xTaskGetCurrentTaskHandle: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetCurrentTaskHandle_Unpriv + MPU_xTaskGetCurrentTaskHandle_Priv: + b MPU_xTaskGetCurrentTaskHandleImpl + MPU_xTaskGetCurrentTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetSchedulerState +MPU_xTaskGetSchedulerState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetSchedulerState_Unpriv + MPU_xTaskGetSchedulerState_Priv: + b MPU_xTaskGetSchedulerStateImpl + MPU_xTaskGetSchedulerState_Unpriv: + svc #SYSTEM_CALL_xTaskGetSchedulerState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetTimeOutState +MPU_vTaskSetTimeOutState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetTimeOutState_Unpriv + MPU_vTaskSetTimeOutState_Priv: + b MPU_vTaskSetTimeOutStateImpl + MPU_vTaskSetTimeOutState_Unpriv: + svc #SYSTEM_CALL_vTaskSetTimeOutState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskCheckForTimeOut +MPU_xTaskCheckForTimeOut: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskCheckForTimeOut_Unpriv + MPU_xTaskCheckForTimeOut_Priv: + b MPU_xTaskCheckForTimeOutImpl + MPU_xTaskCheckForTimeOut_Unpriv: + svc #SYSTEM_CALL_xTaskCheckForTimeOut +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyEntry +MPU_xTaskGenericNotifyEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotify_Unpriv + MPU_xTaskGenericNotify_Priv: + b MPU_xTaskGenericNotifyImpl + MPU_xTaskGenericNotify_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotify +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyWaitEntry +MPU_xTaskGenericNotifyWaitEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotifyWait_Unpriv + MPU_xTaskGenericNotifyWait_Priv: + b MPU_xTaskGenericNotifyWaitImpl + MPU_xTaskGenericNotifyWait_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotifyWait +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGenericNotifyTake +MPU_ulTaskGenericNotifyTake: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGenericNotifyTake_Unpriv + MPU_ulTaskGenericNotifyTake_Priv: + b MPU_ulTaskGenericNotifyTakeImpl + MPU_ulTaskGenericNotifyTake_Unpriv: + svc #SYSTEM_CALL_ulTaskGenericNotifyTake +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyStateClear +MPU_xTaskGenericNotifyStateClear: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotifyStateClear_Unpriv + MPU_xTaskGenericNotifyStateClear_Priv: + b MPU_xTaskGenericNotifyStateClearImpl + MPU_xTaskGenericNotifyStateClear_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotifyStateClear +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGenericNotifyValueClear +MPU_ulTaskGenericNotifyValueClear: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGenericNotifyValueClear_Unpriv + MPU_ulTaskGenericNotifyValueClear_Priv: + b MPU_ulTaskGenericNotifyValueClearImpl + MPU_ulTaskGenericNotifyValueClear_Unpriv: + svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGenericSend +MPU_xQueueGenericSend: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGenericSend_Unpriv + MPU_xQueueGenericSend_Priv: + b MPU_xQueueGenericSendImpl + MPU_xQueueGenericSend_Unpriv: + svc #SYSTEM_CALL_xQueueGenericSend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxQueueMessagesWaiting +MPU_uxQueueMessagesWaiting: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxQueueMessagesWaiting_Unpriv + MPU_uxQueueMessagesWaiting_Priv: + b MPU_uxQueueMessagesWaitingImpl + MPU_uxQueueMessagesWaiting_Unpriv: + svc #SYSTEM_CALL_uxQueueMessagesWaiting +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxQueueSpacesAvailable +MPU_uxQueueSpacesAvailable: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxQueueSpacesAvailable_Unpriv + MPU_uxQueueSpacesAvailable_Priv: + b MPU_uxQueueSpacesAvailableImpl + MPU_uxQueueSpacesAvailable_Unpriv: + svc #SYSTEM_CALL_uxQueueSpacesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueReceive +MPU_xQueueReceive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueReceive_Unpriv + MPU_xQueueReceive_Priv: + b MPU_xQueueReceiveImpl + MPU_xQueueReceive_Unpriv: + svc #SYSTEM_CALL_xQueueReceive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueuePeek +MPU_xQueuePeek: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueuePeek_Unpriv + MPU_xQueuePeek_Priv: + b MPU_xQueuePeekImpl + MPU_xQueuePeek_Unpriv: + svc #SYSTEM_CALL_xQueuePeek +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueSemaphoreTake +MPU_xQueueSemaphoreTake: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueSemaphoreTake_Unpriv + MPU_xQueueSemaphoreTake_Priv: + b MPU_xQueueSemaphoreTakeImpl + MPU_xQueueSemaphoreTake_Unpriv: + svc #SYSTEM_CALL_xQueueSemaphoreTake +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGetMutexHolder +MPU_xQueueGetMutexHolder: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGetMutexHolder_Unpriv + MPU_xQueueGetMutexHolder_Priv: + b MPU_xQueueGetMutexHolderImpl + MPU_xQueueGetMutexHolder_Unpriv: + svc #SYSTEM_CALL_xQueueGetMutexHolder +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueTakeMutexRecursive +MPU_xQueueTakeMutexRecursive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueTakeMutexRecursive_Unpriv + MPU_xQueueTakeMutexRecursive_Priv: + b MPU_xQueueTakeMutexRecursiveImpl + MPU_xQueueTakeMutexRecursive_Unpriv: + svc #SYSTEM_CALL_xQueueTakeMutexRecursive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGiveMutexRecursive +MPU_xQueueGiveMutexRecursive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGiveMutexRecursive_Unpriv + MPU_xQueueGiveMutexRecursive_Priv: + b MPU_xQueueGiveMutexRecursiveImpl + MPU_xQueueGiveMutexRecursive_Unpriv: + svc #SYSTEM_CALL_xQueueGiveMutexRecursive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueSelectFromSet +MPU_xQueueSelectFromSet: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueSelectFromSet_Unpriv + MPU_xQueueSelectFromSet_Priv: + b MPU_xQueueSelectFromSetImpl + MPU_xQueueSelectFromSet_Unpriv: + svc #SYSTEM_CALL_xQueueSelectFromSet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueAddToSet +MPU_xQueueAddToSet: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueAddToSet_Unpriv + MPU_xQueueAddToSet_Priv: + b MPU_xQueueAddToSetImpl + MPU_xQueueAddToSet_Unpriv: + svc #SYSTEM_CALL_xQueueAddToSet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vQueueAddToRegistry +MPU_vQueueAddToRegistry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vQueueAddToRegistry_Unpriv + MPU_vQueueAddToRegistry_Priv: + b MPU_vQueueAddToRegistryImpl + MPU_vQueueAddToRegistry_Unpriv: + svc #SYSTEM_CALL_vQueueAddToRegistry +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vQueueUnregisterQueue +MPU_vQueueUnregisterQueue: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vQueueUnregisterQueue_Unpriv + MPU_vQueueUnregisterQueue_Priv: + b MPU_vQueueUnregisterQueueImpl + MPU_vQueueUnregisterQueue_Unpriv: + svc #SYSTEM_CALL_vQueueUnregisterQueue +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pcQueueGetName +MPU_pcQueueGetName: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pcQueueGetName_Unpriv + MPU_pcQueueGetName_Priv: + b MPU_pcQueueGetNameImpl + MPU_pcQueueGetName_Unpriv: + svc #SYSTEM_CALL_pcQueueGetName +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pvTimerGetTimerID +MPU_pvTimerGetTimerID: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pvTimerGetTimerID_Unpriv + MPU_pvTimerGetTimerID_Priv: + b MPU_pvTimerGetTimerIDImpl + MPU_pvTimerGetTimerID_Unpriv: + svc #SYSTEM_CALL_pvTimerGetTimerID +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTimerSetTimerID +MPU_vTimerSetTimerID: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTimerSetTimerID_Unpriv + MPU_vTimerSetTimerID_Priv: + b MPU_vTimerSetTimerIDImpl + MPU_vTimerSetTimerID_Unpriv: + svc #SYSTEM_CALL_vTimerSetTimerID +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerIsTimerActive +MPU_xTimerIsTimerActive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerIsTimerActive_Unpriv + MPU_xTimerIsTimerActive_Priv: + b MPU_xTimerIsTimerActiveImpl + MPU_xTimerIsTimerActive_Unpriv: + svc #SYSTEM_CALL_xTimerIsTimerActive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetTimerDaemonTaskHandle +MPU_xTimerGetTimerDaemonTaskHandle: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv + MPU_xTimerGetTimerDaemonTaskHandle_Priv: + b MPU_xTimerGetTimerDaemonTaskHandleImpl + MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGenericCommandFromTaskEntry +MPU_xTimerGenericCommandFromTaskEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGenericCommandFromTask_Unpriv + MPU_xTimerGenericCommandFromTask_Priv: + b MPU_xTimerGenericCommandFromTaskImpl + MPU_xTimerGenericCommandFromTask_Unpriv: + svc #SYSTEM_CALL_xTimerGenericCommandFromTask +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pcTimerGetName +MPU_pcTimerGetName: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pcTimerGetName_Unpriv + MPU_pcTimerGetName_Priv: + b MPU_pcTimerGetNameImpl + MPU_pcTimerGetName_Unpriv: + svc #SYSTEM_CALL_pcTimerGetName +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTimerSetReloadMode +MPU_vTimerSetReloadMode: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTimerSetReloadMode_Unpriv + MPU_vTimerSetReloadMode_Priv: + b MPU_vTimerSetReloadModeImpl + MPU_vTimerSetReloadMode_Unpriv: + svc #SYSTEM_CALL_vTimerSetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetReloadMode +MPU_xTimerGetReloadMode: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetReloadMode_Unpriv + MPU_xTimerGetReloadMode_Priv: + b MPU_xTimerGetReloadModeImpl + MPU_xTimerGetReloadMode_Unpriv: + svc #SYSTEM_CALL_xTimerGetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTimerGetReloadMode +MPU_uxTimerGetReloadMode: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTimerGetReloadMode_Unpriv + MPU_uxTimerGetReloadMode_Priv: + b MPU_uxTimerGetReloadModeImpl + MPU_uxTimerGetReloadMode_Unpriv: + svc #SYSTEM_CALL_uxTimerGetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetPeriod +MPU_xTimerGetPeriod: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetPeriod_Unpriv + MPU_xTimerGetPeriod_Priv: + b MPU_xTimerGetPeriodImpl + MPU_xTimerGetPeriod_Unpriv: + svc #SYSTEM_CALL_xTimerGetPeriod +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetExpiryTime +MPU_xTimerGetExpiryTime: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetExpiryTime_Unpriv + MPU_xTimerGetExpiryTime_Priv: + b MPU_xTimerGetExpiryTimeImpl + MPU_xTimerGetExpiryTime_Unpriv: + svc #SYSTEM_CALL_xTimerGetExpiryTime +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupWaitBitsEntry +MPU_xEventGroupWaitBitsEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupWaitBits_Unpriv + MPU_xEventGroupWaitBits_Priv: + b MPU_xEventGroupWaitBitsImpl + MPU_xEventGroupWaitBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupWaitBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupClearBits +MPU_xEventGroupClearBits: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupClearBits_Unpriv + MPU_xEventGroupClearBits_Priv: + b MPU_xEventGroupClearBitsImpl + MPU_xEventGroupClearBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupClearBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupSetBits +MPU_xEventGroupSetBits: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupSetBits_Unpriv + MPU_xEventGroupSetBits_Priv: + b MPU_xEventGroupSetBitsImpl + MPU_xEventGroupSetBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupSetBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupSync +MPU_xEventGroupSync: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupSync_Unpriv + MPU_xEventGroupSync_Priv: + b MPU_xEventGroupSyncImpl + MPU_xEventGroupSync_Unpriv: + svc #SYSTEM_CALL_xEventGroupSync +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxEventGroupGetNumber +MPU_uxEventGroupGetNumber: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxEventGroupGetNumber_Unpriv + MPU_uxEventGroupGetNumber_Priv: + b MPU_uxEventGroupGetNumberImpl + MPU_uxEventGroupGetNumber_Unpriv: + svc #SYSTEM_CALL_uxEventGroupGetNumber +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vEventGroupSetNumber +MPU_vEventGroupSetNumber: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vEventGroupSetNumber_Unpriv + MPU_vEventGroupSetNumber_Priv: + b MPU_vEventGroupSetNumberImpl + MPU_vEventGroupSetNumber_Unpriv: + svc #SYSTEM_CALL_vEventGroupSetNumber +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSend +MPU_xStreamBufferSend: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSend_Unpriv + MPU_xStreamBufferSend_Priv: + b MPU_xStreamBufferSendImpl + MPU_xStreamBufferSend_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferReceive +MPU_xStreamBufferReceive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferReceive_Unpriv + MPU_xStreamBufferReceive_Priv: + b MPU_xStreamBufferReceiveImpl + MPU_xStreamBufferReceive_Unpriv: + svc #SYSTEM_CALL_xStreamBufferReceive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferIsFull +MPU_xStreamBufferIsFull: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferIsFull_Unpriv + MPU_xStreamBufferIsFull_Priv: + b MPU_xStreamBufferIsFullImpl + MPU_xStreamBufferIsFull_Unpriv: + svc #SYSTEM_CALL_xStreamBufferIsFull +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferIsEmpty +MPU_xStreamBufferIsEmpty: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferIsEmpty_Unpriv + MPU_xStreamBufferIsEmpty_Priv: + b MPU_xStreamBufferIsEmptyImpl + MPU_xStreamBufferIsEmpty_Unpriv: + svc #SYSTEM_CALL_xStreamBufferIsEmpty +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSpacesAvailable +MPU_xStreamBufferSpacesAvailable: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSpacesAvailable_Unpriv + MPU_xStreamBufferSpacesAvailable_Priv: + b MPU_xStreamBufferSpacesAvailableImpl + MPU_xStreamBufferSpacesAvailable_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSpacesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferBytesAvailable +MPU_xStreamBufferBytesAvailable: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferBytesAvailable_Unpriv + MPU_xStreamBufferBytesAvailable_Priv: + b MPU_xStreamBufferBytesAvailableImpl + MPU_xStreamBufferBytesAvailable_Unpriv: + svc #SYSTEM_CALL_xStreamBufferBytesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSetTriggerLevel +MPU_xStreamBufferSetTriggerLevel: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSetTriggerLevel_Unpriv + MPU_xStreamBufferSetTriggerLevel_Priv: + b MPU_xStreamBufferSetTriggerLevelImpl + MPU_xStreamBufferSetTriggerLevel_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferNextMessageLengthBytes +MPU_xStreamBufferNextMessageLengthBytes: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv + MPU_xStreamBufferNextMessageLengthBytes_Priv: + b MPU_xStreamBufferNextMessageLengthBytesImpl + MPU_xStreamBufferNextMessageLengthBytes_Unpriv: + svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes +/*-----------------------------------------------------------*/ + +/* Default weak implementations in case one is not available from + * mpu_wrappers because of config options. */ + + PUBWEAK MPU_xTaskDelayUntilImpl +MPU_xTaskDelayUntilImpl: + b MPU_xTaskDelayUntilImpl + + PUBWEAK MPU_xTaskAbortDelayImpl +MPU_xTaskAbortDelayImpl: + b MPU_xTaskAbortDelayImpl + + PUBWEAK MPU_vTaskDelayImpl +MPU_vTaskDelayImpl: + b MPU_vTaskDelayImpl + + PUBWEAK MPU_uxTaskPriorityGetImpl +MPU_uxTaskPriorityGetImpl: + b MPU_uxTaskPriorityGetImpl + + PUBWEAK MPU_eTaskGetStateImpl +MPU_eTaskGetStateImpl: + b MPU_eTaskGetStateImpl + + PUBWEAK MPU_vTaskGetInfoImpl +MPU_vTaskGetInfoImpl: + b MPU_vTaskGetInfoImpl + + PUBWEAK MPU_xTaskGetIdleTaskHandleImpl +MPU_xTaskGetIdleTaskHandleImpl: + b MPU_xTaskGetIdleTaskHandleImpl + + PUBWEAK MPU_vTaskSuspendImpl +MPU_vTaskSuspendImpl: + b MPU_vTaskSuspendImpl + + PUBWEAK MPU_vTaskResumeImpl +MPU_vTaskResumeImpl: + b MPU_vTaskResumeImpl + + PUBWEAK MPU_xTaskGetTickCountImpl +MPU_xTaskGetTickCountImpl: + b MPU_xTaskGetTickCountImpl + + PUBWEAK MPU_uxTaskGetNumberOfTasksImpl +MPU_uxTaskGetNumberOfTasksImpl: + b MPU_uxTaskGetNumberOfTasksImpl + + PUBWEAK MPU_ulTaskGetRunTimeCounterImpl +MPU_ulTaskGetRunTimeCounterImpl: + b MPU_ulTaskGetRunTimeCounterImpl + + PUBWEAK MPU_ulTaskGetRunTimePercentImpl +MPU_ulTaskGetRunTimePercentImpl: + b MPU_ulTaskGetRunTimePercentImpl + + PUBWEAK MPU_ulTaskGetIdleRunTimePercentImpl +MPU_ulTaskGetIdleRunTimePercentImpl: + b MPU_ulTaskGetIdleRunTimePercentImpl + + PUBWEAK MPU_ulTaskGetIdleRunTimeCounterImpl +MPU_ulTaskGetIdleRunTimeCounterImpl: + b MPU_ulTaskGetIdleRunTimeCounterImpl + + PUBWEAK MPU_vTaskSetApplicationTaskTagImpl +MPU_vTaskSetApplicationTaskTagImpl: + b MPU_vTaskSetApplicationTaskTagImpl + + PUBWEAK MPU_xTaskGetApplicationTaskTagImpl +MPU_xTaskGetApplicationTaskTagImpl: + b MPU_xTaskGetApplicationTaskTagImpl + + PUBWEAK MPU_vTaskSetThreadLocalStoragePointerImpl +MPU_vTaskSetThreadLocalStoragePointerImpl: + b MPU_vTaskSetThreadLocalStoragePointerImpl + + PUBWEAK MPU_pvTaskGetThreadLocalStoragePointerImpl +MPU_pvTaskGetThreadLocalStoragePointerImpl: + b MPU_pvTaskGetThreadLocalStoragePointerImpl + + PUBWEAK MPU_uxTaskGetSystemStateImpl +MPU_uxTaskGetSystemStateImpl: + b MPU_uxTaskGetSystemStateImpl + + PUBWEAK MPU_uxTaskGetStackHighWaterMarkImpl +MPU_uxTaskGetStackHighWaterMarkImpl: + b MPU_uxTaskGetStackHighWaterMarkImpl + + PUBWEAK MPU_uxTaskGetStackHighWaterMark2Impl +MPU_uxTaskGetStackHighWaterMark2Impl: + b MPU_uxTaskGetStackHighWaterMark2Impl + + PUBWEAK MPU_xTaskGetCurrentTaskHandleImpl +MPU_xTaskGetCurrentTaskHandleImpl: + b MPU_xTaskGetCurrentTaskHandleImpl + + PUBWEAK MPU_xTaskGetSchedulerStateImpl +MPU_xTaskGetSchedulerStateImpl: + b MPU_xTaskGetSchedulerStateImpl + + PUBWEAK MPU_vTaskSetTimeOutStateImpl +MPU_vTaskSetTimeOutStateImpl: + b MPU_vTaskSetTimeOutStateImpl + + PUBWEAK MPU_xTaskCheckForTimeOutImpl +MPU_xTaskCheckForTimeOutImpl: + b MPU_xTaskCheckForTimeOutImpl + + PUBWEAK MPU_xTaskGenericNotifyImpl +MPU_xTaskGenericNotifyImpl: + b MPU_xTaskGenericNotifyImpl + + PUBWEAK MPU_xTaskGenericNotifyWaitImpl +MPU_xTaskGenericNotifyWaitImpl: + b MPU_xTaskGenericNotifyWaitImpl + + PUBWEAK MPU_ulTaskGenericNotifyTakeImpl +MPU_ulTaskGenericNotifyTakeImpl: + b MPU_ulTaskGenericNotifyTakeImpl + + PUBWEAK MPU_xTaskGenericNotifyStateClearImpl +MPU_xTaskGenericNotifyStateClearImpl: + b MPU_xTaskGenericNotifyStateClearImpl + + PUBWEAK MPU_ulTaskGenericNotifyValueClearImpl +MPU_ulTaskGenericNotifyValueClearImpl: + b MPU_ulTaskGenericNotifyValueClearImpl + + PUBWEAK MPU_xQueueGenericSendImpl +MPU_xQueueGenericSendImpl: + b MPU_xQueueGenericSendImpl + + PUBWEAK MPU_uxQueueMessagesWaitingImpl +MPU_uxQueueMessagesWaitingImpl: + b MPU_uxQueueMessagesWaitingImpl + + PUBWEAK MPU_uxQueueSpacesAvailableImpl +MPU_uxQueueSpacesAvailableImpl: + b MPU_uxQueueSpacesAvailableImpl + + PUBWEAK MPU_xQueueReceiveImpl +MPU_xQueueReceiveImpl: + b MPU_xQueueReceiveImpl + + PUBWEAK MPU_xQueuePeekImpl +MPU_xQueuePeekImpl: + b MPU_xQueuePeekImpl + + PUBWEAK MPU_xQueueSemaphoreTakeImpl +MPU_xQueueSemaphoreTakeImpl: + b MPU_xQueueSemaphoreTakeImpl + + PUBWEAK MPU_xQueueGetMutexHolderImpl +MPU_xQueueGetMutexHolderImpl: + b MPU_xQueueGetMutexHolderImpl + + PUBWEAK MPU_xQueueTakeMutexRecursiveImpl +MPU_xQueueTakeMutexRecursiveImpl: + b MPU_xQueueTakeMutexRecursiveImpl + + PUBWEAK MPU_xQueueGiveMutexRecursiveImpl +MPU_xQueueGiveMutexRecursiveImpl: + b MPU_xQueueGiveMutexRecursiveImpl + + PUBWEAK MPU_xQueueSelectFromSetImpl +MPU_xQueueSelectFromSetImpl: + b MPU_xQueueSelectFromSetImpl + + PUBWEAK MPU_xQueueAddToSetImpl +MPU_xQueueAddToSetImpl: + b MPU_xQueueAddToSetImpl + + PUBWEAK MPU_vQueueAddToRegistryImpl +MPU_vQueueAddToRegistryImpl: + b MPU_vQueueAddToRegistryImpl + + PUBWEAK MPU_vQueueUnregisterQueueImpl +MPU_vQueueUnregisterQueueImpl: + b MPU_vQueueUnregisterQueueImpl + + PUBWEAK MPU_pcQueueGetNameImpl +MPU_pcQueueGetNameImpl: + b MPU_pcQueueGetNameImpl + + PUBWEAK MPU_pvTimerGetTimerIDImpl +MPU_pvTimerGetTimerIDImpl: + b MPU_pvTimerGetTimerIDImpl + + PUBWEAK MPU_vTimerSetTimerIDImpl +MPU_vTimerSetTimerIDImpl: + b MPU_vTimerSetTimerIDImpl + + PUBWEAK MPU_xTimerIsTimerActiveImpl +MPU_xTimerIsTimerActiveImpl: + b MPU_xTimerIsTimerActiveImpl + + PUBWEAK MPU_xTimerGetTimerDaemonTaskHandleImpl +MPU_xTimerGetTimerDaemonTaskHandleImpl: + b MPU_xTimerGetTimerDaemonTaskHandleImpl + + PUBWEAK MPU_xTimerGenericCommandFromTaskImpl +MPU_xTimerGenericCommandFromTaskImpl: + b MPU_xTimerGenericCommandFromTaskImpl + + PUBWEAK MPU_pcTimerGetNameImpl +MPU_pcTimerGetNameImpl: + b MPU_pcTimerGetNameImpl + + PUBWEAK MPU_vTimerSetReloadModeImpl +MPU_vTimerSetReloadModeImpl: + b MPU_vTimerSetReloadModeImpl + + PUBWEAK MPU_xTimerGetReloadModeImpl +MPU_xTimerGetReloadModeImpl: + b MPU_xTimerGetReloadModeImpl + + PUBWEAK MPU_uxTimerGetReloadModeImpl +MPU_uxTimerGetReloadModeImpl: + b MPU_uxTimerGetReloadModeImpl + + PUBWEAK MPU_xTimerGetPeriodImpl +MPU_xTimerGetPeriodImpl: + b MPU_xTimerGetPeriodImpl + + PUBWEAK MPU_xTimerGetExpiryTimeImpl +MPU_xTimerGetExpiryTimeImpl: + b MPU_xTimerGetExpiryTimeImpl + + PUBWEAK MPU_xEventGroupWaitBitsImpl +MPU_xEventGroupWaitBitsImpl: + b MPU_xEventGroupWaitBitsImpl + + PUBWEAK MPU_xEventGroupClearBitsImpl +MPU_xEventGroupClearBitsImpl: + b MPU_xEventGroupClearBitsImpl + + PUBWEAK MPU_xEventGroupSetBitsImpl +MPU_xEventGroupSetBitsImpl: + b MPU_xEventGroupSetBitsImpl + + PUBWEAK MPU_xEventGroupSyncImpl +MPU_xEventGroupSyncImpl: + b MPU_xEventGroupSyncImpl + + PUBWEAK MPU_uxEventGroupGetNumberImpl +MPU_uxEventGroupGetNumberImpl: + b MPU_uxEventGroupGetNumberImpl + + PUBWEAK MPU_vEventGroupSetNumberImpl +MPU_vEventGroupSetNumberImpl: + b MPU_vEventGroupSetNumberImpl + + PUBWEAK MPU_xStreamBufferSendImpl +MPU_xStreamBufferSendImpl: + b MPU_xStreamBufferSendImpl + + PUBWEAK MPU_xStreamBufferReceiveImpl +MPU_xStreamBufferReceiveImpl: + b MPU_xStreamBufferReceiveImpl + + PUBWEAK MPU_xStreamBufferIsFullImpl +MPU_xStreamBufferIsFullImpl: + b MPU_xStreamBufferIsFullImpl + + PUBWEAK MPU_xStreamBufferIsEmptyImpl +MPU_xStreamBufferIsEmptyImpl: + b MPU_xStreamBufferIsEmptyImpl + + PUBWEAK MPU_xStreamBufferSpacesAvailableImpl +MPU_xStreamBufferSpacesAvailableImpl: + b MPU_xStreamBufferSpacesAvailableImpl + + PUBWEAK MPU_xStreamBufferBytesAvailableImpl +MPU_xStreamBufferBytesAvailableImpl: + b MPU_xStreamBufferBytesAvailableImpl + + PUBWEAK MPU_xStreamBufferSetTriggerLevelImpl +MPU_xStreamBufferSetTriggerLevelImpl: + b MPU_xStreamBufferSetTriggerLevelImpl + + PUBWEAK MPU_xStreamBufferNextMessageLengthBytesImpl +MPU_xStreamBufferNextMessageLengthBytesImpl: + b MPU_xStreamBufferNextMessageLengthBytesImpl + +/*-----------------------------------------------------------*/ + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + END diff --git a/portable/IAR/ARM_CM35P/non_secure/port.c b/portable/IAR/ARM_CM35P/non_secure/port.c new file mode 100644 index 000000000..76d2b2445 --- /dev/null +++ b/portable/IAR/ARM_CM35P/non_secure/port.c @@ -0,0 +1,2280 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024-2025 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU includes. */ +#include "mpu_wrappers.h" +#include "mpu_syscall_numbers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration settings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to check the validity of an interrupt priority. + */ +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) ) +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used during system call enter and exit. + */ +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Offsets in the stack to the parameters when inside the SVC handler. + */ +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +#if ( portARMV8M_MINOR_VERSION >= 1 ) + + /* Enable Privileged eXecute Never MPU attribute for the selected memory + * region. */ + #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL ) +#endif /* portARMV8M_MINOR_VERSION >= 1 */ + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Extract first address of the MPU region as encoded in the + * RBAR (Region Base Address Register) value. */ +#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \ + ( ( rbar ) & portMPU_RBAR_ADDRESS_MASK ) + +/* Extract last address of the MPU region as encoded in the + * RLAR (Region Limit Address Register) value. */ +#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \ + ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK ) + +/* Does addr lies within [start, end] address range? */ +#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \ + ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) ) + +/* Is the access request satisfied by the available permissions? */ +#define portIS_AUTHORIZED( accessRequest, permissions ) \ + ( ( ( permissions ) & ( accessRequest ) ) == accessRequest ) + +/* Max value that fits in a uint32_t type. */ +#define portUINT32_MAX ( ~( ( uint32_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. + */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 + +/** + * @brief Constants required to check and configure PACBTI security feature implementation. + */ +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) ) + + #define portCONTROL_UPAC_EN ( 1UL << 7UL ) + #define portCONTROL_PAC_EN ( 1UL << 6UL ) + #define portCONTROL_UBTI_EN ( 1UL << 5UL ) + #define portCONTROL_BTI_EN ( 1UL << 4UL ) + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Extract MPU region's access permissions from the Region Base Address + * Register (RBAR) value. + * + * @param ulRBARValue RBAR value for the MPU region. + * + * @return uint32_t Access permissions. + */ + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + + /** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + /** + * @brief Configures PACBTI features. + * + * This function configures the Pointer Authentication, and Branch Target + * Identification security features as per the user configuration. It returns + * the value of the special purpose CONTROL register accordingly, and optionally + * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M + * architecture based) target supports PACBTI security feature. + * + * @param xWriteControlRegister Used to control whether the special purpose + * CONTROL register should be updated or not. + * + * @return CONTROL register value according to the configured PACBTI option. + */ + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the system call stack so that upon returning from + * SVC, the system call stack is used. + * + * @param pulTaskStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + * @param ucSystemCallNumber The system call number of the system call. + */ + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Raise SVC for exiting from a system call. + */ + void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief This variable is set to pdTRUE when the scheduler is started. + */ + PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + + /** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +/** + * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + /** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + + /** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + + /** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the cpsid instruction + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessPermissions = 0; + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_ONLY ) + { + ulAccessPermissions = tskMPU_READ_PERMISSION; + } + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_WRITE ) + { + ulAccessPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION ); + } + + return ulAccessPermissions; + } + +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } + +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ portOFFSET_TO_PC ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ]; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulSystemCallStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the system call section (i.e. application is + * not raising SVC directly). + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as + * it is non-NULL only during the execution of a system call (i.e. + * between system call enter and exit). + * 3. System call is not for a kernel API disabled by the configuration + * in FreeRTOSConfig.h. + * 4. We do not need to check that ucSystemCallNumber is within range + * because the assembly SVC handler checks that before calling + * this function. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) && + ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) ) + { + pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the system call stack for the stack frame. */ + pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulSystemCallStack[ i ] = pulTaskStack[ i ]; + } + + /* Store the value of the Link Register before the SVC was raised. + * It contains the address of the caller of the System Call entry + * point (i.e. the caller of the MPU_). We need to restore it + * when we exit from the system call. */ + pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; + + /* Store the value of the PSPLIM register before the SVC was raised. + * We need to restore it when we exit from the system call. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* Use the pulSystemCallStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif + + /* Start executing the system call upon returning from this handler. */ + pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; + + /* Raise a request to exit from the system call upon finishing the + * system call. */ + pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; + + /* Remember the location where we should copy the stack frame when we exit from + * the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize; + + /* Record if the hardware used padding to force the stack pointer + * to be double word aligned. */ + if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK ) + { + pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG; + } + else + { + pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG ); + } + + /* We ensure in pxPortInitialiseStack that the system call stack is + * double word aligned and therefore, there is no need of padding. + * Clear the bit[9] of stacked xPSR. */ + pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + + /* Raise the privilege for the duration of the system call. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " bics r0, r1 \n" /* Clear nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */ + { + __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulTaskStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the privileged code (i.e. application is not + * raising SVC directly). This SVC is only raised from + * vRequestSystemCallExit which is in the privileged code section. + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL - + * this means that we previously entered a system call and the + * application is not attempting to exit without entering a system + * call. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) ) + { + pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the task stack for the stack frame. */ + pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulTaskStack[ i ] = pulSystemCallStack[ i ]; + } + + /* Use the pulTaskStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) ); + + /* Return to the caller of the System Call entry point (i.e. the + * caller of the MPU_). */ + pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + /* Ensure that LR has a valid value.*/ + pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + + /* Restore the PSPLIM register to what it was at the time of + * system call entry. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* If the hardware used padding to force the stack pointer + * to be double word aligned, set the stacked xPSR bit[9], + * otherwise clear it. */ + if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG ) + { + pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK; + } + else + { + pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + } + + /* This is not NULL only for the duration of the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; + + /* Drop the privilege before returning to the thread mode. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " orrs r0, r1 \n" /* Set nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xTaskIsPrivileged = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xTaskIsPrivileged = pdTRUE; + } + + return xTaskIsPrivileged; + } + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged, + xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulIndex = 0; + uint32_t ulControl = 0x0; + + xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ + ulIndex++; + + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + ulIndex++; + + #if ( configENABLE_TRUSTZONE == 1 ) + { + xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */ + ulIndex++; + } + #endif /* configENABLE_TRUSTZONE */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + ulIndex++; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Check PACBTI security feature configuration before pushing the + * CONTROL register's value on task's TCB. */ + ulControl = prvConfigurePACBTI( pdFALSE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + if( xRunPrivileged == pdTRUE ) + { + xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + else + { + xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG ); + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ + ulIndex++; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + { + /* Ensure that the system call stack is double word aligned. */ + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) + + ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + /* This is not NULL only for the duration of a system call. */ + xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL; + } + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ]; + ulIndex++; + } + } + #endif /* configENABLE_PAC */ + + return &( xMPUSettings->ulContext[ ulIndex ] ); + } + +#else /* configENABLE_MPU */ + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ + { + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + pxTopOfStack--; + *pxTopOfStack = ulTaskPacKey[ i ]; + } + } + #endif /* configENABLE_PAC */ + + return pxTopOfStack; + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Set the CONTROL register value based on PACBTI security feature + * configuration before starting the first task. */ + ( void ) prvConfigurePACBTI( pdTRUE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + { + xSchedulerRunning = pdTRUE; + } + #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + configSTACK_DEPTH_TYPE uxStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( uxStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* PXN. */ + #if ( portARMV8M_MINOR_VERSION >= 1 ) + { + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ); + } + } + #endif /* portARMV8M_MINOR_VERSION >= 1 */ + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, + uint32_t ulBufferLength, + uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */ + + { + uint32_t i, ulBufferStartAddress, ulBufferEndAddress; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE ) + { + ulBufferStartAddress = ( uint32_t ) pvBuffer; + ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL ); + + for( i = 0; i < portTOTAL_NUM_REGIONS; i++ ) + { + /* Is the MPU region enabled? */ + if( ( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR & portMPU_RLAR_REGION_ENABLE ) == portMPU_RLAR_REGION_ENABLE ) + { + if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_AUTHORIZED( ulAccessRequested, + prvGetRegionAccessPermissions( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ) ) ) + { + xAccessGranted = pdTRUE; + break; + } + } + } + } + } + + return xAccessGranted; + } + +#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings; + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else + { + xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 ) + { + xAccessGranted = pdTRUE; + } + } + } + + return xAccessGranted; + } + + #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + ( void ) lInternalIndexOfKernelObject; + + /* If Access Control List feature is not used, all the tasks have + * access to all the kernel objects. */ + return pdTRUE; + } + + #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + { + uint32_t ulControl = 0x0; + + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); + + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; + + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/ARM_CM35P/non_secure/portasm.h b/portable/IAR/ARM_CM35P/non_secure/portasm.h new file mode 100644 index 000000000..b7021b024 --- /dev/null +++ b/portable/IAR/ARM_CM35P/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kernel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/portable/IAR/ARM_CM35P/non_secure/portasm.s b/portable/IAR/ARM_CM35P/non_secure/portasm.s new file mode 100644 index 000000000..8d5988819 --- /dev/null +++ b/portable/IAR/ARM_CM35P/non_secure/portasm.s @@ -0,0 +1,543 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" + +/* System call numbers includes. */ +#include "mpu_syscall_numbers.h" + +#ifndef configUSE_MPU_WRAPPERS_V1 + #define configUSE_MPU_WRAPPERS_V1 0 +#endif + + EXTERN pxCurrentTCB + EXTERN xSecureContext + EXTERN vTaskSwitchContext + EXTERN vPortSVCHandler_C + EXTERN SecureContext_SaveContext + EXTERN SecureContext_LoadContext +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + EXTERN vSystemCallEnter + EXTERN vSystemCallExit +#endif + + PUBLIC xIsPrivileged + PUBLIC vResetPrivilege + PUBLIC vPortAllocateSecureContext + PUBLIC vRestoreContextOfFirstTask + PUBLIC vRaisePrivilege + PUBLIC vStartFirstTask + PUBLIC ulSetInterruptMask + PUBLIC vClearInterruptMask + PUBLIC PendSV_Handler + PUBLIC SVC_Handler + PUBLIC vPortFreeSecureContext +/*-----------------------------------------------------------*/ + +/*---------------- Unprivileged Functions -------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION .text:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +xIsPrivileged: + mrs r0, control /* r0 = CONTROL. */ + tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + ite ne + movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vResetPrivilege: + mrs r0, control /* r0 = CONTROL. */ + orr r0, r0, #1 /* r0 = r0 | 1. */ + msr control, r0 /* CONTROL = r0. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vPortAllocateSecureContext: + svc 100 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 100. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +/*----------------- Privileged Functions --------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION privileged_functions:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +vRestoreContextOfFirstTask: + program_mpu_first_task: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r3] /* r0 = pxCurrentTCB. */ + + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + str r2, [r1] /* Disable MPU. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r1, [r2] /* Program MAIR0. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + + movs r3, #4 /* r3 = 4. */ + str r3, [r1] /* Program RNR = 4. */ + ldmia r0!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + #if ( configTOTAL_MPU_REGIONS == 16 ) + movs r3, #8 /* r3 = 8. */ + str r3, [r1] /* Program RNR = 8. */ + ldmia r0!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + movs r3, #12 /* r3 = 12. */ + str r3, [r1] /* Program RNR = 12. */ + ldmia r0!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + orr r2, #1 /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */ + str r2, [r1] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + + restore_context_first_task: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* r1 = pxCurrentTCB.*/ + ldr r2, [r1] /* r2 = Location of saved context in TCB. */ + + restore_special_regs_first_task: + #if ( configENABLE_PAC == 1 ) + ldmdb r2!, {r3-r6} /* Read task's dedicated PAC key from the task's context. */ + msr PAC_KEY_P_0, r3 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_1, r4 + msr PAC_KEY_P_2, r5 + msr PAC_KEY_P_3, r6 + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + ldmdb r2!, {r0, r3-r5, lr} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */ + msr psp, r3 + msr psplim, r4 + msr control, r5 + ldr r4, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + str r0, [r4] /* Restore xSecureContext. */ + + restore_general_regs_first_task: + ldmdb r2!, {r4-r11} /* r4-r11 contain hardware saved context. */ + stmia r3!, {r4-r11} /* Copy the hardware saved context on the task stack. */ + ldmdb r2!, {r4-r11} /* r4-r11 restored. */ + + restore_context_done_first_task: + str r2, [r1] /* Save the location where the context should be saved next as the first member of TCB. */ + mov r0, #0 + msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ + bx lr + +#else /* configENABLE_MPU */ + +vRestoreContextOfFirstTask: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r3, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + +#if ( configENABLE_PAC == 1 ) + ldmia r0!, {r1-r4} /* Read task's dedicated PAC key from stack. */ + msr PAC_KEY_P_3, r1 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_2, r2 + msr PAC_KEY_P_1, r3 + msr PAC_KEY_P_0, r4 + clrm {r1-r4} /* Clear r1-r4. */ +#endif /* configENABLE_PAC */ + + ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */ + ldr r4, =xSecureContext + str r1, [r4] /* Set xSecureContext to this task's value for the same. */ + msr psplim, r2 /* Set this task's PSPLIM value. */ + mrs r1, control /* Obtain current control register value. */ + orrs r1, r1, #2 /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */ + msr control, r1 /* Write back the new control register value. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + mov r0, #0 + msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ + bx r3 /* Finally, branch to EXC_RETURN. */ + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +vRaisePrivilege: + mrs r0, control /* Read the CONTROL register. */ + bic r0, r0, #1 /* Clear the bit 0. */ + msr control, r0 /* Write back the new CONTROL value. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vStartFirstTask: + ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */ + ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */ + ldr r0, [r0] /* The first entry in vector table is stack pointer. */ + msr msp, r0 /* Set the MSP back to the start of the stack. */ + cpsie i /* Globally enable interrupts. */ + cpsie f + dsb + isb + svc 102 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */ +/*-----------------------------------------------------------*/ + +ulSetInterruptMask: + mrs r0, basepri /* r0 = basepri. Return original basepri value. */ + mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r1 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vClearInterruptMask: + msr basepri, r0 /* basepri = ulMask. */ + dsb + isb + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +PendSV_Handler: + ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + ldr r0, [r3] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */ + ldr r2, [r1] /* r2 = Location in TCB where the context should be saved. */ + + cbz r0, save_ns_context /* No secure context to save. */ + save_s_context: + push {r0-r2, lr} + bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r0-r2, lr} + + save_ns_context: + mov r3, lr /* r3 = LR (EXC_RETURN). */ + lsls r3, r3, #25 /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bmi save_special_regs /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + + save_general_regs: + mrs r3, psp + + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + add r3, r3, #0x20 /* Move r3 to location where s0 is saved. */ + tst lr, #0x10 + ittt eq + vstmiaeq r2!, {s16-s31} /* Store s16-s31. */ + vldmiaeq r3, {s0-s16} /* Copy hardware saved FP context into s0-s16. */ + vstmiaeq r2!, {s0-s16} /* Store hardware saved FP context. */ + sub r3, r3, #0x20 /* Set r3 back to the location of hardware saved context. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + + stmia r2!, {r4-r11} /* Store r4-r11. */ + ldmia r3, {r4-r11} /* Copy the hardware saved context into r4-r11. */ + stmia r2!, {r4-r11} /* Store the hardware saved context. */ + + save_special_regs: + mrs r3, psp /* r3 = PSP. */ + mrs r4, psplim /* r4 = PSPLIM. */ + mrs r5, control /* r5 = CONTROL. */ + stmia r2!, {r0, r3-r5, lr} /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ + #if ( configENABLE_PAC == 1 ) + mrs r3, PAC_KEY_P_0 /* Read task's dedicated PAC key from the PAC key registers. */ + mrs r4, PAC_KEY_P_1 + mrs r5, PAC_KEY_P_2 + mrs r6, PAC_KEY_P_3 + stmia r2!, {r3-r6} /* Store the task's dedicated PAC key on the task's context. */ + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + + str r2, [r1] /* Save the location from where the context should be restored as the first member of TCB. */ + + select_next_task: + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bl vTaskSwitchContext + mov r0, #0 /* r0 = 0. */ + msr basepri, r0 /* Enable interrupts. */ + + program_mpu: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r3] /* r0 = pxCurrentTCB.*/ + + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + str r2, [r1] /* Disable MPU. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r1, [r2] /* Program MAIR0. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + + movs r3, #4 /* r3 = 4. */ + str r3, [r1] /* Program RNR = 4. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + #if ( configTOTAL_MPU_REGIONS == 16 ) + movs r3, #8 /* r3 = 8. */ + str r3, [r1] /* Program RNR = 8. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + movs r3, #12 /* r3 = 12. */ + str r3, [r1] /* Program RNR = 12. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + orr r2, #1 /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */ + str r2, [r1] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + + restore_context: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* r1 = pxCurrentTCB.*/ + ldr r2, [r1] /* r2 = Location of saved context in TCB. */ + + restore_special_regs: + #if ( configENABLE_PAC == 1 ) + ldmdb r2!, {r3-r6} /* Read task's dedicated PAC key from the task's context. */ + msr PAC_KEY_P_0, r3 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_1, r4 + msr PAC_KEY_P_2, r5 + msr PAC_KEY_P_3, r6 + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + ldmdb r2!, {r0, r3-r5, lr} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */ + msr psp, r3 + msr psplim, r4 + msr control, r5 + ldr r4, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + str r0, [r4] /* Restore xSecureContext. */ + cbz r0, restore_ns_context /* No secure context to restore. */ + + restore_s_context: + push {r1-r3, lr} + bl SecureContext_LoadContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r1-r3, lr} + + restore_ns_context: + mov r0, lr /* r0 = LR (EXC_RETURN). */ + lsls r0, r0, #25 /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bmi restore_context_done /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + + restore_general_regs: + ldmdb r2!, {r4-r11} /* r4-r11 contain hardware saved context. */ + stmia r3!, {r4-r11} /* Copy the hardware saved context on the task stack. */ + ldmdb r2!, {r4-r11} /* r4-r11 restored. */ + + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 + ittt eq + vldmdbeq r2!, {s0-s16} /* s0-s16 contain hardware saved FP context. */ + vstmiaeq r3!, {s0-s16} /* Copy hardware saved FP context on the task stack. */ + vldmdbeq r2!, {s16-s31} /* Restore s16-s31. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + + restore_context_done: + str r2, [r1] /* Save the location where the context should be saved next as the first member of TCB. */ + bx lr + +#else /* configENABLE_MPU */ + +PendSV_Handler: + ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + ldr r0, [r3] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */ + mrs r2, psp /* Read PSP in r2. */ + + cbz r0, save_ns_context /* No secure context to save. */ + save_s_context: + push {r0-r2, lr} + bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r0-r2, lr} + + save_ns_context: + mov r3, lr /* r3 = LR. */ + lsls r3, r3, #25 /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bmi save_special_regs /* If r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used. */ + + save_general_regs: + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + it eq + vstmdbeq r2!, {s16-s31} /* Store the additional FP context registers which are not saved automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + stmdb r2!, {r4-r11} /* Store the registers that are not saved automatically. */ + + save_special_regs: + mrs r3, psplim /* r3 = PSPLIM. */ + stmdb r2!, {r0, r3, lr} /* Store xSecureContext, PSPLIM and LR on the stack. */ + #if ( configENABLE_PAC == 1 ) + mrs r3, PAC_KEY_P_3 /* Read task's dedicated PAC key from the PAC key registers. */ + mrs r4, PAC_KEY_P_2 + mrs r5, PAC_KEY_P_1 + mrs r6, PAC_KEY_P_0 + stmdb r2!, {r3-r6} /* Store the task's dedicated PAC key on the stack. */ + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + + str r2, [r1] /* Save the new top of stack in TCB. */ + + select_next_task: + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bl vTaskSwitchContext + mov r0, #0 /* r0 = 0. */ + msr basepri, r0 /* Enable interrupts. */ + + restore_context: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB. */ + ldr r2, [r1] /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */ + + restore_special_regs: + #if ( configENABLE_PAC == 1 ) + ldmia r2!, {r3-r6} /* Read task's dedicated PAC key from stack. */ + msr PAC_KEY_P_3, r3 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_2, r4 + msr PAC_KEY_P_1, r5 + msr PAC_KEY_P_0, r6 + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + ldmia r2!, {r0, r3, lr} http://files.iar.com/ftp/pub/box/bxarm-9.60.3.deb/* Read from stack - r0 = xSecureContext, r3 = PSPLIM and LR restored. */ + msr psplim, r3 /* Restore the PSPLIM register value for the task. */ + ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + str r0, [r3] /* Restore the task's xSecureContext. */ + cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */ + + restore_s_context: + push {r1-r3, lr} + bl SecureContext_LoadContext /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r1-r3, lr} + + restore_ns_context: + mov r0, lr /* r0 = LR (EXC_RETURN). */ + lsls r0, r0, #25 /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bmi restore_context_done /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + + restore_general_regs: + ldmia r2!, {r4-r11} /* Restore the registers that are not automatically restored. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + it eq + vldmiaeq r2!, {s16-s31} /* Restore the additional FP context registers which are not restored automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + + restore_context_done: + msr psp, r2 /* Remember the new top of stack for the task. */ + bx lr + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + +SVC_Handler: + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + + ldr r1, [r0, #24] + ldrb r2, [r1, #-2] + cmp r2, #NUM_SYSTEM_CALLS + blt syscall_enter + cmp r2, #104 /* portSVC_SYSTEM_CALL_EXIT. */ + beq syscall_exit + b vPortSVCHandler_C + + syscall_enter: + mov r1, lr + b vSystemCallEnter + + syscall_exit: + mov r1, lr + b vSystemCallExit + +#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +SVC_Handler: + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + b vPortSVCHandler_C + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +vPortFreeSecureContext: + /* r0 = uint32_t *pulTCB. */ + ldr r2, [r0] /* The first item in the TCB is the top of the stack. */ + ldr r1, [r2] /* The first item on the stack is the task's xSecureContext. */ + cmp r1, #0 /* Raise svc if task's xSecureContext is not NULL. */ + it ne + svcne 101 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 101. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + + END diff --git a/portable/IAR/ARM_CM35P/non_secure/portmacro.h b/portable/IAR/ARM_CM35P/non_secure/portmacro.h new file mode 100644 index 000000000..6e543efb5 --- /dev/null +++ b/portable/IAR/ARM_CM35P/non_secure/portmacro.h @@ -0,0 +1,88 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M35P" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portARMV8M_MINOR_VERSION 0 +#define portDONT_DISCARD __root +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +#ifndef configENABLE_MVE + #define configENABLE_MVE 0 +#elif ( configENABLE_MVE != 0 ) + #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M35. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ +#pragma diag_suppress=Be006 +#pragma diag_suppress=Pa082 +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h new file mode 100644 index 000000000..f373bcad5 --- /dev/null +++ b/portable/IAR/ARM_CM35P/non_secure/portmacrocommon.h @@ -0,0 +1,582 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACROCOMMON_H +#define PORTMACROCOMMON_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. +#endif /* configENABLE_FPU */ + +#ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. +#endif /* configENABLE_MPU */ + +#ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. +#endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() +#define portINLINE __inline +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif +#define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ +extern BaseType_t xPortIsInsideInterrupt( void ); + +extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + +extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; +extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + +extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; +extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + +#if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_PAC == 1 ) + + /** + * @brief Generates 128-bit task's random PAC key. + * + * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be + * filled with a 128-bit random number. + */ + void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); + +#endif /* configENABLE_PAC */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ +#if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) +#else + #define portPRIVILEGE_BIT ( 0x0UL ) +#endif /* configENABLE_MPU */ + +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ +#define portPRIVILEGED_FLASH_REGION ( 0UL ) +#define portUNPRIVILEGED_FLASH_REGION ( 1UL ) +#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) +#define portPRIVILEGED_RAM_REGION ( 3UL ) +#define portSTACK_REGION ( 4UL ) +#define portFIRST_CONFIGURABLE_REGION ( 5UL ) +#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) +#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) +#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ +#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ +#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ +#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ +#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ +#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ +#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ +#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) +#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) +#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + +#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) +#define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) +#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) +#define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + +#define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + #ifndef configSYSTEM_CALL_STACK_SIZE + #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. + #endif + + /** + * @brief System call stack. + */ + typedef struct SYSTEM_CALL_STACK_INFO + { + uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; + uint32_t * pulSystemCallStack; + uint32_t * pulSystemCallStackLimit; + uint32_t * pulTaskStack; + uint32_t ulLinkRegisterAtSystemCallEntry; + uint32_t ulStackLimitRegisterAtSystemCallEntry; + } xSYSTEM_CALL_STACK_INFO; + + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + /** + * @brief MPU settings as stored in the TCB. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><-----------><----> + * 16 17 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 71 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 17 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 55 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | | | PC, xPSR | EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><-----------><----> + * 16 17 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 70 + + #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + /* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 17 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 54 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+------------------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +----------+-----------------+------------------------------+------------+-----+ + * + * <---------><----------------><------------------------------><-----------><----> + * 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 38 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+----------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | PC, xPSR | EXC_RETURN | | | + * +----------+-----------------+----------------------+------------+-----+ + * + * <---------><----------------><----------------------><-----------><----> + * 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 37 + + #else /* #if( configENABLE_TRUSTZONE == 1 ) */ + + /* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) + + /* Size of an Access Control List (ACL) entry in bits. */ + #define portACL_ENTRY_SIZE_BITS ( 32U ) + + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + uint32_t ulContext[ MAX_CONTEXT_SIZE ]; + uint32_t ulTaskFlags; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo; + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ]; + #endif + #endif + } xMPU_SETTINGS; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Validate priority of ISRs that are allowed to call FreeRTOS + * system calls. + */ +#if ( configASSERT_DEFINED == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif +#endif + +/** + * @brief SVC numbers. + */ +#define portSVC_ALLOCATE_SECURE_CONTEXT 100 +#define portSVC_FREE_SECURE_CONTEXT 101 +#define portSVC_START_SCHEDULER 102 +#define portSVC_RAISE_PRIVILEGE 103 +#define portSVC_SYSTEM_CALL_EXIT 104 +#define portSVC_YIELD 105 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) +#endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() +#else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + extern BaseType_t xPortIsTaskPrivileged( void ); + +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACROCOMMON_H */ diff --git a/portable/IAR/ARM_CM35P/secure/secure_context.c b/portable/IAR/ARM_CM35P/secure/secure_context.c new file mode 100644 index 000000000..3aa335e63 --- /dev/null +++ b/portable/IAR/ARM_CM35P/secure/secure_context.c @@ -0,0 +1,354 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Secure context includes. */ +#include "secure_context.h" + +/* Secure heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief CONTROL value for privileged tasks. + * + * Bit[0] - 0 --> Thread mode is privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_PRIVILEGED 0x02 + +/** + * @brief CONTROL value for un-privileged tasks. + * + * Bit[0] - 1 --> Thread mode is un-privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03 + +/** + * @brief Size of stack seal values in bytes. + */ +#define securecontextSTACK_SEAL_SIZE 8 + +/** + * @brief Stack seal value as recommended by ARM. + */ +#define securecontextSTACK_SEAL_VALUE 0xFEF5EDA5 + +/** + * @brief Maximum number of secure contexts. + */ +#ifndef secureconfigMAX_SECURE_CONTEXTS + #define secureconfigMAX_SECURE_CONTEXTS 8UL +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Pre-allocated array of secure contexts. + */ +SecureContext_t xSecureContexts[ secureconfigMAX_SECURE_CONTEXTS ]; +/*-----------------------------------------------------------*/ + +/** + * @brief Get a free secure context for a task from the secure context pool (xSecureContexts). + * + * This function ensures that only one secure context is allocated for a task. + * + * @param[in] pvTaskHandle The task handle for which the secure context is allocated. + * + * @return Index of a free secure context in the xSecureContexts array. + */ +static uint32_t ulGetSecureContext( void * pvTaskHandle ); + +/** + * @brief Return the secure context to the secure context pool (xSecureContexts). + * + * @param[in] ulSecureContextIndex Index of the context in the xSecureContexts array. + */ +static void vReturnSecureContext( uint32_t ulSecureContextIndex ); + +/* These are implemented in assembly. */ +extern void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ); +extern void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ); +/*-----------------------------------------------------------*/ + +static uint32_t ulGetSecureContext( void * pvTaskHandle ) +{ + /* Start with invalid index. */ + uint32_t i, ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + if( ( xSecureContexts[ i ].pucCurrentStackPointer == NULL ) && + ( xSecureContexts[ i ].pucStackLimit == NULL ) && + ( xSecureContexts[ i ].pucStackStart == NULL ) && + ( xSecureContexts[ i ].pvTaskHandle == NULL ) && + ( ulSecureContextIndex == secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = i; + } + else if( xSecureContexts[ i ].pvTaskHandle == pvTaskHandle ) + { + /* A task can only have one secure context. Do not allocate a second + * context for the same task. */ + ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + break; + } + } + + return ulSecureContextIndex; +} +/*-----------------------------------------------------------*/ + +static void vReturnSecureContext( uint32_t ulSecureContextIndex ) +{ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackStart = NULL; + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = NULL; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) +{ + uint32_t ulIPSR, i; + static uint32_t ulSecureContextsInitialized = 0; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ( ulIPSR != 0 ) && ( ulSecureContextsInitialized == 0 ) ) + { + /* Ensure to initialize secure contexts only once. */ + ulSecureContextsInitialized = 1; + + /* No stack for thread mode until a task's context is loaded. */ + secureportSET_PSPLIM( securecontextNO_STACK ); + secureportSET_PSP( securecontextNO_STACK ); + + /* Initialize all secure contexts. */ + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + xSecureContexts[ i ].pucCurrentStackPointer = NULL; + xSecureContexts[ i ].pucStackLimit = NULL; + xSecureContexts[ i ].pucStackStart = NULL; + xSecureContexts[ i ].pvTaskHandle = NULL; + } + + #if ( configENABLE_MPU == 1 ) + { + /* Configure thread mode to use PSP and to be unprivileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); + } + #else /* configENABLE_MPU */ + { + /* Configure thread mode to use PSP and to be privileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); + } + #endif /* configENABLE_MPU */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ) +#else /* configENABLE_MPU */ + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ) +#endif /* configENABLE_MPU */ +{ + uint8_t * pucStackMemory = NULL; + uint8_t * pucStackLimit; + uint32_t ulIPSR, ulSecureContextIndex; + SecureContextHandle_t xSecureContextHandle = securecontextINVALID_CONTEXT_ID; + + #if ( configENABLE_MPU == 1 ) + uint32_t * pulCurrentStackPointer = NULL; + #endif /* configENABLE_MPU */ + + /* Read the Interrupt Program Status Register (IPSR) and Process Stack Limit + * Register (PSPLIM) value. */ + secureportREAD_IPSR( ulIPSR ); + secureportREAD_PSPLIM( pucStackLimit ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. + * Also do nothing, if a secure context us already loaded. PSPLIM is set to + * securecontextNO_STACK when no secure context is loaded. */ + if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) ) + { + /* Obtain a free secure context. */ + ulSecureContextIndex = ulGetSecureContext( pvTaskHandle ); + + /* Were we able to get a free context? */ + if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS ) + { + /* Allocate the stack space. */ + pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + + if( pucStackMemory != NULL ) + { + /* Since stack grows down, the starting point will be the last + * location. Note that this location is next to the last + * allocated byte for stack (excluding the space for seal values) + * because the hardware decrements the stack pointer before + * writing i.e. if stack pointer is 0x2, a push operation will + * decrement the stack pointer to 0x1 and then write at 0x1. */ + xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize; + + /* Seal the created secure process stack. */ + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; + + /* The stack cannot go beyond this location. This value is + * programmed in the PSPLIM register on context switch.*/ + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = pucStackMemory; + + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle; + + #if ( configENABLE_MPU == 1 ) + { + /* Store the correct CONTROL value for the task on the stack. + * This value is programmed in the CONTROL register on + * context switch. */ + pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; + pulCurrentStackPointer--; + + if( ulIsTaskPrivileged ) + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; + } + else + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; + } + + /* Store the current stack pointer. This value is programmed in + * the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + } + #else /* configENABLE_MPU */ + { + /* Current SP is set to the starting of the stack. This + * value programmed in the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + } + #endif /* configENABLE_MPU */ + + /* Ensure to never return 0 as a valid context handle. */ + xSecureContextHandle = ulSecureContextIndex + 1UL; + } + } + } + + return xSecureContextHandle; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) +{ + uint32_t ulIPSR, ulSecureContextIndex; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* Only free if a valid context handle is passed. */ + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + /* Ensure that the secure context being deleted is associated with + * the task. */ + if( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) + { + /* Free the stack space. */ + vPortFree( xSecureContexts[ ulSecureContextIndex ].pucStackLimit ); + + /* Return the secure context back to the free secure contexts pool. */ + vReturnSecureContext( ulSecureContextIndex ); + } + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that no secure context is loaded and the task is loading it's + * own context. */ + if( ( pucStackLimit == securecontextNO_STACK ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_LoadContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that task's context is loaded and the task is saving it's own + * context. */ + if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_SaveContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/ARM_CM35P/secure/secure_context.h b/portable/IAR/ARM_CM35P/secure/secure_context.h new file mode 100644 index 000000000..e36a8e430 --- /dev/null +++ b/portable/IAR/ARM_CM35P/secure/secure_context.h @@ -0,0 +1,138 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_CONTEXT_H__ +#define __SECURE_CONTEXT_H__ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" + +/** + * @brief PSP value when no secure context is loaded. + */ +#define securecontextNO_STACK 0x0 + +/** + * @brief Invalid context ID. + */ +#define securecontextINVALID_CONTEXT_ID 0UL +/*-----------------------------------------------------------*/ + +/** + * @brief Structure to represent a secure context. + * + * @note Since stack grows down, pucStackStart is the highest address while + * pucStackLimit is the first address of the allocated memory. + */ +typedef struct SecureContext +{ + uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */ + uint8_t * pucStackLimit; /**< Last location of the stack memory (PSPLIM). */ + uint8_t * pucStackStart; /**< First location of the stack memory. */ + void * pvTaskHandle; /**< Task handle of the task this context is associated with. */ +} SecureContext_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Opaque handle for a secure context. + */ +typedef uint32_t SecureContextHandle_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Initializes the secure context management system. + * + * PSP is set to NULL and therefore a task must allocate and load a context + * before calling any secure side function in the thread mode. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureContext_Init( void ); + +/** + * @brief Allocates a context on the secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] ulSecureStackSize Size of the stack to allocate on secure side. + * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise. + * + * @return Opaque context handle if context is successfully allocated, NULL + * otherwise. + */ +#if ( configENABLE_MPU == 1 ) + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ); +#else /* configENABLE_MPU */ + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ); +#endif /* configENABLE_MPU */ + +/** + * @brief Frees the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the + * context to be freed. + */ +void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); + +/** + * @brief Loads the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be loaded. + */ +void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); + +/** + * @brief Saves the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be saved. + */ +void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); + +#endif /* __SECURE_CONTEXT_H__ */ diff --git a/portable/IAR/ARM_CM35P/secure/secure_context_port_asm.s b/portable/IAR/ARM_CM35P/secure/secure_context_port_asm.s new file mode 100644 index 000000000..27a8f3933 --- /dev/null +++ b/portable/IAR/ARM_CM35P/secure/secure_context_port_asm.s @@ -0,0 +1,86 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + SECTION .text:CODE:NOROOT(2) + THUMB + +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" + + PUBLIC SecureContext_LoadContextAsm + PUBLIC SecureContext_SaveContextAsm +/*-----------------------------------------------------------*/ + +SecureContext_LoadContextAsm: + /* pxSecureContext value is in r0. */ + mrs r1, ipsr /* r1 = IPSR. */ + cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */ + ldmia r0!, {r1, r2} /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */ + +#if ( configENABLE_MPU == 1 ) + ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL. */ + msr control, r3 /* CONTROL = r3. */ +#endif /* configENABLE_MPU */ + + msr psplim, r2 /* PSPLIM = r2. */ + msr psp, r1 /* PSP = r1. */ + + load_ctx_therad_mode: + bx lr +/*-----------------------------------------------------------*/ + +SecureContext_SaveContextAsm: + /* pxSecureContext value is in r0. */ + mrs r1, ipsr /* r1 = IPSR. */ + cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */ + mrs r1, psp /* r1 = PSP. */ + +#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + vstmdb r1!, {s0} /* Trigger the deferred stacking of FPU registers. */ + vldmia r1!, {s0} /* Nullify the effect of the previous statement. */ +#endif /* configENABLE_FPU || configENABLE_MVE */ + +#if ( configENABLE_MPU == 1 ) + mrs r2, control /* r2 = CONTROL. */ + stmdb r1!, {r2} /* Store CONTROL value on the stack. */ +#endif /* configENABLE_MPU */ + + str r1, [r0] /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */ + movs r1, #0 /* r1 = securecontextNO_STACK. */ + msr psplim, r1 /* PSPLIM = securecontextNO_STACK. */ + msr psp, r1 /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */ + + save_ctx_therad_mode: + bx lr +/*-----------------------------------------------------------*/ + + END diff --git a/portable/IAR/ARM_CM35P/secure/secure_heap.c b/portable/IAR/ARM_CM35P/secure/secure_heap.c new file mode 100644 index 000000000..896b53e2d --- /dev/null +++ b/portable/IAR/ARM_CM35P/secure/secure_heap.c @@ -0,0 +1,485 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Configuration includes. */ +#include "FreeRTOSConfig.h" + +/* Secure context heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Total heap size. + */ +#ifndef secureconfigTOTAL_HEAP_SIZE + #define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) ) +#endif + +/* No test marker by default. */ +#ifndef mtCOVERAGE_TEST_MARKER + #define mtCOVERAGE_TEST_MARKER() +#endif + +/* No tracing by default. */ +#ifndef traceMALLOC + #define traceMALLOC( pvReturn, xWantedSize ) +#endif + +/* No tracing by default. */ +#ifndef traceFREE + #define traceFREE( pv, xBlockSize ) +#endif + +/* Block sizes must not get too small. */ +#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) ) + +/* Assumes 8bit bytes! */ +#define secureheapBITS_PER_BYTE ( ( size_t ) 8 ) + +/* Max value that fits in a size_t type. */ +#define secureheapSIZE_MAX ( ~( ( size_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define secureheapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) ) + +/* MSB of the xBlockSize member of an BlockLink_t structure is used to track + * the allocation status of a block. When MSB of the xBlockSize member of + * an BlockLink_t structure is set then the block belongs to the application. + * When the bit is free the block is still part of the free heap space. */ +#define secureheapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) ) +#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 ) +#define secureheapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 ) +#define secureheapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK ) +#define secureheapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK ) +/*-----------------------------------------------------------*/ + +/* Allocate the memory for the heap. */ +#if ( configAPPLICATION_ALLOCATED_HEAP == 1 ) + +/* The application writer has already defined the array used for the RTOS +* heap - probably so it can be placed in a special segment or address. */ + extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#else /* configAPPLICATION_ALLOCATED_HEAP */ + static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#endif /* configAPPLICATION_ALLOCATED_HEAP */ + +/** + * @brief The linked list structure. + * + * This is used to link free blocks in order of their memory address. + */ +typedef struct A_BLOCK_LINK +{ + struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */ + size_t xBlockSize; /**< The size of the free block. */ +} BlockLink_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Called automatically to setup the required heap structures the first + * time pvPortMalloc() is called. + */ +static void prvHeapInit( void ); + +/** + * @brief Inserts a block of memory that is being freed into the correct + * position in the list of free memory blocks. + * + * The block being freed will be merged with the block in front it and/or the + * block behind it if the memory blocks are adjacent to each other. + * + * @param[in] pxBlockToInsert The block being freed. + */ +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ); +/*-----------------------------------------------------------*/ + +/** + * @brief The size of the structure placed at the beginning of each allocated + * memory block must by correctly byte aligned. + */ +static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + +/** + * @brief Create a couple of list links to mark the start and end of the list. + */ +static BlockLink_t xStart; +static BlockLink_t * pxEnd = NULL; + +/** + * @brief Keeps track of the number of free bytes remaining, but says nothing + * about fragmentation. + */ +static size_t xFreeBytesRemaining = 0U; +static size_t xMinimumEverFreeBytesRemaining = 0U; + +/*-----------------------------------------------------------*/ + +static void prvHeapInit( void ) +{ + BlockLink_t * pxFirstFreeBlock; + uint8_t * pucAlignedHeap; + size_t uxAddress; + size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE; + + /* Ensure the heap starts on a correctly aligned boundary. */ + uxAddress = ( size_t ) ucHeap; + + if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 ) + { + uxAddress += ( secureportBYTE_ALIGNMENT - 1 ); + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; + } + + pucAlignedHeap = ( uint8_t * ) uxAddress; + + /* xStart is used to hold a pointer to the first item in the list of free + * blocks. The void cast is used to prevent compiler warnings. */ + xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; + xStart.xBlockSize = ( size_t ) 0; + + /* pxEnd is used to mark the end of the list of free blocks and is inserted + * at the end of the heap space. */ + uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; + uxAddress -= xHeapStructSize; + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + pxEnd = ( void * ) uxAddress; + pxEnd->xBlockSize = 0; + pxEnd->pxNextFreeBlock = NULL; + + /* To start with there is a single free block that is sized to take up the + * entire heap space, minus the space taken by pxEnd. */ + pxFirstFreeBlock = ( void * ) pucAlignedHeap; + pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; + pxFirstFreeBlock->pxNextFreeBlock = pxEnd; + + /* Only one block exists - and it covers the entire usable heap space. */ + xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; +} +/*-----------------------------------------------------------*/ + +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) +{ + BlockLink_t * pxIterator; + uint8_t * puc; + + /* Iterate through the list until a block is found that has a higher address + * than the block being inserted. */ + for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) + { + /* Nothing to do here, just iterate to the right position. */ + } + + /* Do the block being inserted, and the block it is being inserted after + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxIterator; + + if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) + { + pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; + pxBlockToInsert = pxIterator; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Do the block being inserted, and the block it is being inserted before + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxBlockToInsert; + + if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) + { + if( pxIterator->pxNextFreeBlock != pxEnd ) + { + /* Form one big block from the two blocks. */ + pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxEnd; + } + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; + } + + /* If the block being inserted plugged a gap, so was merged with the block + * before and the block after, then it's pxNextFreeBlock pointer will have + * already been set, and should not be set here as that would make it point + * to itself. */ + if( pxIterator != pxBlockToInsert ) + { + pxIterator->pxNextFreeBlock = pxBlockToInsert; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} +/*-----------------------------------------------------------*/ + +void * pvPortMalloc( size_t xWantedSize ) +{ + BlockLink_t * pxBlock; + BlockLink_t * pxPreviousBlock; + BlockLink_t * pxNewBlockLink; + void * pvReturn = NULL; + size_t xAdditionalRequiredSize; + size_t xAllocatedBlockSize = 0; + + /* If this is the first call to malloc then the heap will require + * initialisation to setup the list of free blocks. */ + if( pxEnd == NULL ) + { + prvHeapInit(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xWantedSize > 0 ) + { + /* The wanted size must be increased so it can contain a BlockLink_t + * structure in addition to the requested amount of bytes. */ + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 ) + { + xWantedSize += xHeapStructSize; + + /* Ensure that blocks are always aligned to the required number + * of bytes. */ + if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 ) + { + /* Byte alignment required. */ + xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ); + + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 ) + { + xWantedSize += xAdditionalRequiredSize; + } + else + { + xWantedSize = 0; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + xWantedSize = 0; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Check the requested block size is not so large that the top bit is set. + * The top bit of the block size member of the BlockLink_t structure is used + * to determine who owns the block - the application or the kernel, so it + * must be free. */ + if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 ) + { + if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) + { + /* Traverse the list from the start (lowest address) block until + * one of adequate size is found. */ + pxPreviousBlock = &xStart; + pxBlock = xStart.pxNextFreeBlock; + + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + { + pxPreviousBlock = pxBlock; + pxBlock = pxBlock->pxNextFreeBlock; + } + + /* If the end marker was reached then a block of adequate size was + * not found. */ + if( pxBlock != pxEnd ) + { + /* Return the memory space pointed to - jumping over the + * BlockLink_t structure at its start. */ + pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); + + /* This block is being returned for use so must be taken out + * of the list of free blocks. */ + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + + /* If the block is larger than required it can be split into + * two. */ + if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE ) + { + /* This block is to be split into two. Create a new + * block following the number of bytes requested. The void + * cast is used to prevent byte alignment warnings from the + * compiler. */ + pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); + secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + + /* Calculate the sizes of two blocks split from the single + * block. */ + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + pxBlock->xBlockSize = xWantedSize; + + /* Insert the new block into the list of free blocks. */ + pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock; + pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xFreeBytesRemaining -= pxBlock->xBlockSize; + + if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) + { + xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xAllocatedBlockSize = pxBlock->xBlockSize; + + /* The block is being returned - it is allocated and owned by + * the application and has no "next" block. */ + secureheapALLOCATE_BLOCK( pxBlock ); + pxBlock->pxNextFreeBlock = NULL; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceMALLOC( pvReturn, xAllocatedBlockSize ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xAllocatedBlockSize; + + #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) + { + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */ + + secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 ); + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void * pv ) +{ + uint8_t * puc = ( uint8_t * ) pv; + BlockLink_t * pxLink; + + if( pv != NULL ) + { + /* The memory being freed will have an BlockLink_t structure immediately + * before it. */ + puc -= xHeapStructSize; + + /* This casting is to keep the compiler from issuing warnings. */ + pxLink = ( void * ) puc; + + /* Check the block is actually allocated. */ + secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ); + secureportASSERT( pxLink->pxNextFreeBlock == NULL ); + + if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ) + { + if( pxLink->pxNextFreeBlock == NULL ) + { + /* The block is being returned to the heap - it is no longer + * allocated. */ + secureheapFREE_BLOCK( pxLink ); + + secureportDISABLE_NON_SECURE_INTERRUPTS(); + { + /* Add this block to the list of free blocks. */ + xFreeBytesRemaining += pxLink->xBlockSize; + traceFREE( pv, pxLink->xBlockSize ); + prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); + } + secureportENABLE_NON_SECURE_INTERRUPTS(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } +} +/*-----------------------------------------------------------*/ + +size_t xPortGetFreeHeapSize( void ) +{ + return xFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +size_t xPortGetMinimumEverFreeHeapSize( void ) +{ + return xMinimumEverFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/ARM_CM35P/secure/secure_heap.h b/portable/IAR/ARM_CM35P/secure/secure_heap.h new file mode 100644 index 000000000..0e84a9d9d --- /dev/null +++ b/portable/IAR/ARM_CM35P/secure/secure_heap.h @@ -0,0 +1,66 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_HEAP_H__ +#define __SECURE_HEAP_H__ + +/* Standard includes. */ +#include + +/** + * @brief Allocates memory from heap. + * + * @param[in] xWantedSize The size of the memory to be allocated. + * + * @return Pointer to the memory region if the allocation is successful, NULL + * otherwise. + */ +void * pvPortMalloc( size_t xWantedSize ); + +/** + * @brief Frees the previously allocated memory. + * + * @param[in] pv Pointer to the memory to be freed. + */ +void vPortFree( void * pv ); + +/** + * @brief Get the free heap size. + * + * @return Free heap size. + */ +size_t xPortGetFreeHeapSize( void ); + +/** + * @brief Get the minimum ever free heap size. + * + * @return Minimum ever free heap size. + */ +size_t xPortGetMinimumEverFreeHeapSize( void ); + +#endif /* __SECURE_HEAP_H__ */ diff --git a/portable/IAR/ARM_CM35P/secure/secure_init.c b/portable/IAR/ARM_CM35P/secure/secure_init.c new file mode 100644 index 000000000..c50d37668 --- /dev/null +++ b/portable/IAR/ARM_CM35P/secure/secure_init.c @@ -0,0 +1,106 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Secure init includes. */ +#include "secure_init.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Constants required to manipulate the SCB. + */ +#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */ +#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL ) +#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS ) +#define secureinitSCB_AIRCR_PRIS_POS ( 14UL ) +#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS ) + +/** + * @brief Constants required to manipulate the FPU. + */ +#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define secureinitFPCCR_LSPENS_POS ( 29UL ) +#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS ) +#define secureinitFPCCR_TS_POS ( 26UL ) +#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS ) + +#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */ +#define secureinitNSACR_CP10_POS ( 10UL ) +#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS ) +#define secureinitNSACR_CP11_POS ( 11UL ) +#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS ) +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) | + ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) | + ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK ); + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is + * permitted. CP11 should be programmed to the same value as CP10. */ + *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK ); + + /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures + * that we can enable/disable lazy stacking in port.c file. */ + *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK ); + + /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP + * registers (S16-S31) are also pushed to stack on exception entry and + * restored on exception return. */ + *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK ); + } +} +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/ARM_CM35P/secure/secure_init.h b/portable/IAR/ARM_CM35P/secure/secure_init.h new file mode 100644 index 000000000..ebe04900f --- /dev/null +++ b/portable/IAR/ARM_CM35P/secure/secure_init.h @@ -0,0 +1,54 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_INIT_H__ +#define __SECURE_INIT_H__ + +/** + * @brief De-prioritizes the non-secure exceptions. + * + * This is needed to ensure that the non-secure PendSV runs at the lowest + * priority. Context switch is done in the non-secure PendSV handler. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_DePrioritizeNSExceptions( void ); + +/** + * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access. + * + * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point + * Registers are not leaked to the non-secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_EnableNSFPUAccess( void ); + +#endif /* __SECURE_INIT_H__ */ diff --git a/portable/IAR/ARM_CM35P/secure/secure_port_macros.h b/portable/IAR/ARM_CM35P/secure/secure_port_macros.h new file mode 100644 index 000000000..a70da2c65 --- /dev/null +++ b/portable/IAR/ARM_CM35P/secure/secure_port_macros.h @@ -0,0 +1,140 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_PORT_MACROS_H__ +#define __SECURE_PORT_MACROS_H__ + +/** + * @brief Byte alignment requirements. + */ +#define secureportBYTE_ALIGNMENT 8 +#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 ) + +/** + * @brief Macro to declare a function as non-secure callable. + */ +#if defined( __IAR_SYSTEMS_ICC__ ) + #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry __root +#else + #define secureportNON_SECURE_CALLABLE __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) ) +#endif + +/** + * @brief Set the secure PRIMASK value. + */ +#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Set the non-secure PRIMASK value. + */ +#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Read the PSP value in the given variable. + */ +#define secureportREAD_PSP( pucOutCurrentStackPointer ) \ + __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) ) + +/** + * @brief Set the PSP to the given value. + */ +#define secureportSET_PSP( pucCurrentStackPointer ) \ + __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) ) + +/** + * @brief Read the PSPLIM value in the given variable. + */ +#define secureportREAD_PSPLIM( pucOutStackLimit ) \ + __asm volatile ( "mrs %0, psplim" : "=r" ( pucOutStackLimit ) ) + +/** + * @brief Set the PSPLIM to the given value. + */ +#define secureportSET_PSPLIM( pucStackLimit ) \ + __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) ) + +/** + * @brief Set the NonSecure MSP to the given value. + */ +#define secureportSET_MSP_NS( pucMainStackPointer ) \ + __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) ) + +/** + * @brief Set the CONTROL register to the given value. + */ +#define secureportSET_CONTROL( ulControl ) \ + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" ) + +/** + * @brief Read the Interrupt Program Status Register (IPSR) value in the given + * variable. + */ +#define secureportREAD_IPSR( ulIPSR ) \ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) ) + +/** + * @brief PRIMASK value to enable interrupts. + */ +#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0 + +/** + * @brief PRIMASK value to disable interrupts. + */ +#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1 + +/** + * @brief Disable secure interrupts. + */ +#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Disable non-secure interrupts. + * + * This effectively disables context switches. + */ +#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Enable non-secure interrupts. + */ +#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL ) + +/** + * @brief Assert definition. + */ +#define secureportASSERT( x ) \ + if( ( x ) == 0 ) \ + { \ + secureportDISABLE_SECURE_INTERRUPTS(); \ + secureportDISABLE_NON_SECURE_INTERRUPTS(); \ + for( ; ; ) {; } \ + } + +#endif /* __SECURE_PORT_MACROS_H__ */ diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.S new file mode 100644 index 000000000..d2cb78e92 --- /dev/null +++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.S @@ -0,0 +1,1242 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + + SECTION freertos_system_calls:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +#include "FreeRTOSConfig.h" +#include "mpu_syscall_numbers.h" + +#ifndef configUSE_MPU_WRAPPERS_V1 + #define configUSE_MPU_WRAPPERS_V1 0 +#endif + +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + PUBLIC MPU_xTaskDelayUntil +MPU_xTaskDelayUntil: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskDelayUntil_Unpriv + MPU_xTaskDelayUntil_Priv: + b MPU_xTaskDelayUntilImpl + MPU_xTaskDelayUntil_Unpriv: + svc #SYSTEM_CALL_xTaskDelayUntil +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskAbortDelay +MPU_xTaskAbortDelay: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskAbortDelay_Unpriv + MPU_xTaskAbortDelay_Priv: + b MPU_xTaskAbortDelayImpl + MPU_xTaskAbortDelay_Unpriv: + svc #SYSTEM_CALL_xTaskAbortDelay +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskDelay +MPU_vTaskDelay: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskDelay_Unpriv + MPU_vTaskDelay_Priv: + b MPU_vTaskDelayImpl + MPU_vTaskDelay_Unpriv: + svc #SYSTEM_CALL_vTaskDelay +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskPriorityGet +MPU_uxTaskPriorityGet: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskPriorityGet_Unpriv + MPU_uxTaskPriorityGet_Priv: + b MPU_uxTaskPriorityGetImpl + MPU_uxTaskPriorityGet_Unpriv: + svc #SYSTEM_CALL_uxTaskPriorityGet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_eTaskGetState +MPU_eTaskGetState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_eTaskGetState_Unpriv + MPU_eTaskGetState_Priv: + b MPU_eTaskGetStateImpl + MPU_eTaskGetState_Unpriv: + svc #SYSTEM_CALL_eTaskGetState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskGetInfo +MPU_vTaskGetInfo: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskGetInfo_Unpriv + MPU_vTaskGetInfo_Priv: + b MPU_vTaskGetInfoImpl + MPU_vTaskGetInfo_Unpriv: + svc #SYSTEM_CALL_vTaskGetInfo +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetIdleTaskHandle +MPU_xTaskGetIdleTaskHandle: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetIdleTaskHandle_Unpriv + MPU_xTaskGetIdleTaskHandle_Priv: + b MPU_xTaskGetIdleTaskHandleImpl + MPU_xTaskGetIdleTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTaskGetIdleTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSuspend +MPU_vTaskSuspend: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSuspend_Unpriv + MPU_vTaskSuspend_Priv: + b MPU_vTaskSuspendImpl + MPU_vTaskSuspend_Unpriv: + svc #SYSTEM_CALL_vTaskSuspend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskResume +MPU_vTaskResume: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskResume_Unpriv + MPU_vTaskResume_Priv: + b MPU_vTaskResumeImpl + MPU_vTaskResume_Unpriv: + svc #SYSTEM_CALL_vTaskResume +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetTickCount +MPU_xTaskGetTickCount: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetTickCount_Unpriv + MPU_xTaskGetTickCount_Priv: + b MPU_xTaskGetTickCountImpl + MPU_xTaskGetTickCount_Unpriv: + svc #SYSTEM_CALL_xTaskGetTickCount +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetNumberOfTasks +MPU_uxTaskGetNumberOfTasks: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetNumberOfTasks_Unpriv + MPU_uxTaskGetNumberOfTasks_Priv: + b MPU_uxTaskGetNumberOfTasksImpl + MPU_uxTaskGetNumberOfTasks_Unpriv: + svc #SYSTEM_CALL_uxTaskGetNumberOfTasks +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetRunTimeCounter +MPU_ulTaskGetRunTimeCounter: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetRunTimeCounter_Unpriv + MPU_ulTaskGetRunTimeCounter_Priv: + b MPU_ulTaskGetRunTimeCounterImpl + MPU_ulTaskGetRunTimeCounter_Unpriv: + svc #SYSTEM_CALL_ulTaskGetRunTimeCounter +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetRunTimePercent +MPU_ulTaskGetRunTimePercent: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetRunTimePercent_Unpriv + MPU_ulTaskGetRunTimePercent_Priv: + b MPU_ulTaskGetRunTimePercentImpl + MPU_ulTaskGetRunTimePercent_Unpriv: + svc #SYSTEM_CALL_ulTaskGetRunTimePercent +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetIdleRunTimePercent +MPU_ulTaskGetIdleRunTimePercent: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetIdleRunTimePercent_Unpriv + MPU_ulTaskGetIdleRunTimePercent_Priv: + b MPU_ulTaskGetIdleRunTimePercentImpl + MPU_ulTaskGetIdleRunTimePercent_Unpriv: + svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetIdleRunTimeCounter +MPU_ulTaskGetIdleRunTimeCounter: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv + MPU_ulTaskGetIdleRunTimeCounter_Priv: + b MPU_ulTaskGetIdleRunTimeCounterImpl + MPU_ulTaskGetIdleRunTimeCounter_Unpriv: + svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetApplicationTaskTag +MPU_vTaskSetApplicationTaskTag: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetApplicationTaskTag_Unpriv + MPU_vTaskSetApplicationTaskTag_Priv: + b MPU_vTaskSetApplicationTaskTagImpl + MPU_vTaskSetApplicationTaskTag_Unpriv: + svc #SYSTEM_CALL_vTaskSetApplicationTaskTag +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetApplicationTaskTag +MPU_xTaskGetApplicationTaskTag: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetApplicationTaskTag_Unpriv + MPU_xTaskGetApplicationTaskTag_Priv: + b MPU_xTaskGetApplicationTaskTagImpl + MPU_xTaskGetApplicationTaskTag_Unpriv: + svc #SYSTEM_CALL_xTaskGetApplicationTaskTag +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetThreadLocalStoragePointer +MPU_vTaskSetThreadLocalStoragePointer: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv + MPU_vTaskSetThreadLocalStoragePointer_Priv: + b MPU_vTaskSetThreadLocalStoragePointerImpl + MPU_vTaskSetThreadLocalStoragePointer_Unpriv: + svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pvTaskGetThreadLocalStoragePointer +MPU_pvTaskGetThreadLocalStoragePointer: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv + MPU_pvTaskGetThreadLocalStoragePointer_Priv: + b MPU_pvTaskGetThreadLocalStoragePointerImpl + MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: + svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetSystemState +MPU_uxTaskGetSystemState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetSystemState_Unpriv + MPU_uxTaskGetSystemState_Priv: + b MPU_uxTaskGetSystemStateImpl + MPU_uxTaskGetSystemState_Unpriv: + svc #SYSTEM_CALL_uxTaskGetSystemState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetStackHighWaterMark +MPU_uxTaskGetStackHighWaterMark: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetStackHighWaterMark_Unpriv + MPU_uxTaskGetStackHighWaterMark_Priv: + b MPU_uxTaskGetStackHighWaterMarkImpl + MPU_uxTaskGetStackHighWaterMark_Unpriv: + svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetStackHighWaterMark2 +MPU_uxTaskGetStackHighWaterMark2: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetStackHighWaterMark2_Unpriv + MPU_uxTaskGetStackHighWaterMark2_Priv: + b MPU_uxTaskGetStackHighWaterMark2Impl + MPU_uxTaskGetStackHighWaterMark2_Unpriv: + svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2 +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetCurrentTaskHandle +MPU_xTaskGetCurrentTaskHandle: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetCurrentTaskHandle_Unpriv + MPU_xTaskGetCurrentTaskHandle_Priv: + b MPU_xTaskGetCurrentTaskHandleImpl + MPU_xTaskGetCurrentTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetSchedulerState +MPU_xTaskGetSchedulerState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetSchedulerState_Unpriv + MPU_xTaskGetSchedulerState_Priv: + b MPU_xTaskGetSchedulerStateImpl + MPU_xTaskGetSchedulerState_Unpriv: + svc #SYSTEM_CALL_xTaskGetSchedulerState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetTimeOutState +MPU_vTaskSetTimeOutState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetTimeOutState_Unpriv + MPU_vTaskSetTimeOutState_Priv: + b MPU_vTaskSetTimeOutStateImpl + MPU_vTaskSetTimeOutState_Unpriv: + svc #SYSTEM_CALL_vTaskSetTimeOutState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskCheckForTimeOut +MPU_xTaskCheckForTimeOut: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskCheckForTimeOut_Unpriv + MPU_xTaskCheckForTimeOut_Priv: + b MPU_xTaskCheckForTimeOutImpl + MPU_xTaskCheckForTimeOut_Unpriv: + svc #SYSTEM_CALL_xTaskCheckForTimeOut +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyEntry +MPU_xTaskGenericNotifyEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotify_Unpriv + MPU_xTaskGenericNotify_Priv: + b MPU_xTaskGenericNotifyImpl + MPU_xTaskGenericNotify_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotify +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyWaitEntry +MPU_xTaskGenericNotifyWaitEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotifyWait_Unpriv + MPU_xTaskGenericNotifyWait_Priv: + b MPU_xTaskGenericNotifyWaitImpl + MPU_xTaskGenericNotifyWait_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotifyWait +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGenericNotifyTake +MPU_ulTaskGenericNotifyTake: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGenericNotifyTake_Unpriv + MPU_ulTaskGenericNotifyTake_Priv: + b MPU_ulTaskGenericNotifyTakeImpl + MPU_ulTaskGenericNotifyTake_Unpriv: + svc #SYSTEM_CALL_ulTaskGenericNotifyTake +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyStateClear +MPU_xTaskGenericNotifyStateClear: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotifyStateClear_Unpriv + MPU_xTaskGenericNotifyStateClear_Priv: + b MPU_xTaskGenericNotifyStateClearImpl + MPU_xTaskGenericNotifyStateClear_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotifyStateClear +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGenericNotifyValueClear +MPU_ulTaskGenericNotifyValueClear: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGenericNotifyValueClear_Unpriv + MPU_ulTaskGenericNotifyValueClear_Priv: + b MPU_ulTaskGenericNotifyValueClearImpl + MPU_ulTaskGenericNotifyValueClear_Unpriv: + svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGenericSend +MPU_xQueueGenericSend: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGenericSend_Unpriv + MPU_xQueueGenericSend_Priv: + b MPU_xQueueGenericSendImpl + MPU_xQueueGenericSend_Unpriv: + svc #SYSTEM_CALL_xQueueGenericSend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxQueueMessagesWaiting +MPU_uxQueueMessagesWaiting: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxQueueMessagesWaiting_Unpriv + MPU_uxQueueMessagesWaiting_Priv: + b MPU_uxQueueMessagesWaitingImpl + MPU_uxQueueMessagesWaiting_Unpriv: + svc #SYSTEM_CALL_uxQueueMessagesWaiting +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxQueueSpacesAvailable +MPU_uxQueueSpacesAvailable: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxQueueSpacesAvailable_Unpriv + MPU_uxQueueSpacesAvailable_Priv: + b MPU_uxQueueSpacesAvailableImpl + MPU_uxQueueSpacesAvailable_Unpriv: + svc #SYSTEM_CALL_uxQueueSpacesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueReceive +MPU_xQueueReceive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueReceive_Unpriv + MPU_xQueueReceive_Priv: + b MPU_xQueueReceiveImpl + MPU_xQueueReceive_Unpriv: + svc #SYSTEM_CALL_xQueueReceive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueuePeek +MPU_xQueuePeek: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueuePeek_Unpriv + MPU_xQueuePeek_Priv: + b MPU_xQueuePeekImpl + MPU_xQueuePeek_Unpriv: + svc #SYSTEM_CALL_xQueuePeek +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueSemaphoreTake +MPU_xQueueSemaphoreTake: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueSemaphoreTake_Unpriv + MPU_xQueueSemaphoreTake_Priv: + b MPU_xQueueSemaphoreTakeImpl + MPU_xQueueSemaphoreTake_Unpriv: + svc #SYSTEM_CALL_xQueueSemaphoreTake +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGetMutexHolder +MPU_xQueueGetMutexHolder: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGetMutexHolder_Unpriv + MPU_xQueueGetMutexHolder_Priv: + b MPU_xQueueGetMutexHolderImpl + MPU_xQueueGetMutexHolder_Unpriv: + svc #SYSTEM_CALL_xQueueGetMutexHolder +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueTakeMutexRecursive +MPU_xQueueTakeMutexRecursive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueTakeMutexRecursive_Unpriv + MPU_xQueueTakeMutexRecursive_Priv: + b MPU_xQueueTakeMutexRecursiveImpl + MPU_xQueueTakeMutexRecursive_Unpriv: + svc #SYSTEM_CALL_xQueueTakeMutexRecursive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGiveMutexRecursive +MPU_xQueueGiveMutexRecursive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGiveMutexRecursive_Unpriv + MPU_xQueueGiveMutexRecursive_Priv: + b MPU_xQueueGiveMutexRecursiveImpl + MPU_xQueueGiveMutexRecursive_Unpriv: + svc #SYSTEM_CALL_xQueueGiveMutexRecursive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueSelectFromSet +MPU_xQueueSelectFromSet: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueSelectFromSet_Unpriv + MPU_xQueueSelectFromSet_Priv: + b MPU_xQueueSelectFromSetImpl + MPU_xQueueSelectFromSet_Unpriv: + svc #SYSTEM_CALL_xQueueSelectFromSet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueAddToSet +MPU_xQueueAddToSet: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueAddToSet_Unpriv + MPU_xQueueAddToSet_Priv: + b MPU_xQueueAddToSetImpl + MPU_xQueueAddToSet_Unpriv: + svc #SYSTEM_CALL_xQueueAddToSet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vQueueAddToRegistry +MPU_vQueueAddToRegistry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vQueueAddToRegistry_Unpriv + MPU_vQueueAddToRegistry_Priv: + b MPU_vQueueAddToRegistryImpl + MPU_vQueueAddToRegistry_Unpriv: + svc #SYSTEM_CALL_vQueueAddToRegistry +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vQueueUnregisterQueue +MPU_vQueueUnregisterQueue: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vQueueUnregisterQueue_Unpriv + MPU_vQueueUnregisterQueue_Priv: + b MPU_vQueueUnregisterQueueImpl + MPU_vQueueUnregisterQueue_Unpriv: + svc #SYSTEM_CALL_vQueueUnregisterQueue +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pcQueueGetName +MPU_pcQueueGetName: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pcQueueGetName_Unpriv + MPU_pcQueueGetName_Priv: + b MPU_pcQueueGetNameImpl + MPU_pcQueueGetName_Unpriv: + svc #SYSTEM_CALL_pcQueueGetName +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pvTimerGetTimerID +MPU_pvTimerGetTimerID: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pvTimerGetTimerID_Unpriv + MPU_pvTimerGetTimerID_Priv: + b MPU_pvTimerGetTimerIDImpl + MPU_pvTimerGetTimerID_Unpriv: + svc #SYSTEM_CALL_pvTimerGetTimerID +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTimerSetTimerID +MPU_vTimerSetTimerID: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTimerSetTimerID_Unpriv + MPU_vTimerSetTimerID_Priv: + b MPU_vTimerSetTimerIDImpl + MPU_vTimerSetTimerID_Unpriv: + svc #SYSTEM_CALL_vTimerSetTimerID +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerIsTimerActive +MPU_xTimerIsTimerActive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerIsTimerActive_Unpriv + MPU_xTimerIsTimerActive_Priv: + b MPU_xTimerIsTimerActiveImpl + MPU_xTimerIsTimerActive_Unpriv: + svc #SYSTEM_CALL_xTimerIsTimerActive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetTimerDaemonTaskHandle +MPU_xTimerGetTimerDaemonTaskHandle: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv + MPU_xTimerGetTimerDaemonTaskHandle_Priv: + b MPU_xTimerGetTimerDaemonTaskHandleImpl + MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGenericCommandFromTaskEntry +MPU_xTimerGenericCommandFromTaskEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGenericCommandFromTask_Unpriv + MPU_xTimerGenericCommandFromTask_Priv: + b MPU_xTimerGenericCommandFromTaskImpl + MPU_xTimerGenericCommandFromTask_Unpriv: + svc #SYSTEM_CALL_xTimerGenericCommandFromTask +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pcTimerGetName +MPU_pcTimerGetName: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pcTimerGetName_Unpriv + MPU_pcTimerGetName_Priv: + b MPU_pcTimerGetNameImpl + MPU_pcTimerGetName_Unpriv: + svc #SYSTEM_CALL_pcTimerGetName +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTimerSetReloadMode +MPU_vTimerSetReloadMode: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTimerSetReloadMode_Unpriv + MPU_vTimerSetReloadMode_Priv: + b MPU_vTimerSetReloadModeImpl + MPU_vTimerSetReloadMode_Unpriv: + svc #SYSTEM_CALL_vTimerSetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetReloadMode +MPU_xTimerGetReloadMode: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetReloadMode_Unpriv + MPU_xTimerGetReloadMode_Priv: + b MPU_xTimerGetReloadModeImpl + MPU_xTimerGetReloadMode_Unpriv: + svc #SYSTEM_CALL_xTimerGetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTimerGetReloadMode +MPU_uxTimerGetReloadMode: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTimerGetReloadMode_Unpriv + MPU_uxTimerGetReloadMode_Priv: + b MPU_uxTimerGetReloadModeImpl + MPU_uxTimerGetReloadMode_Unpriv: + svc #SYSTEM_CALL_uxTimerGetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetPeriod +MPU_xTimerGetPeriod: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetPeriod_Unpriv + MPU_xTimerGetPeriod_Priv: + b MPU_xTimerGetPeriodImpl + MPU_xTimerGetPeriod_Unpriv: + svc #SYSTEM_CALL_xTimerGetPeriod +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetExpiryTime +MPU_xTimerGetExpiryTime: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetExpiryTime_Unpriv + MPU_xTimerGetExpiryTime_Priv: + b MPU_xTimerGetExpiryTimeImpl + MPU_xTimerGetExpiryTime_Unpriv: + svc #SYSTEM_CALL_xTimerGetExpiryTime +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupWaitBitsEntry +MPU_xEventGroupWaitBitsEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupWaitBits_Unpriv + MPU_xEventGroupWaitBits_Priv: + b MPU_xEventGroupWaitBitsImpl + MPU_xEventGroupWaitBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupWaitBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupClearBits +MPU_xEventGroupClearBits: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupClearBits_Unpriv + MPU_xEventGroupClearBits_Priv: + b MPU_xEventGroupClearBitsImpl + MPU_xEventGroupClearBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupClearBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupSetBits +MPU_xEventGroupSetBits: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupSetBits_Unpriv + MPU_xEventGroupSetBits_Priv: + b MPU_xEventGroupSetBitsImpl + MPU_xEventGroupSetBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupSetBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupSync +MPU_xEventGroupSync: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupSync_Unpriv + MPU_xEventGroupSync_Priv: + b MPU_xEventGroupSyncImpl + MPU_xEventGroupSync_Unpriv: + svc #SYSTEM_CALL_xEventGroupSync +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxEventGroupGetNumber +MPU_uxEventGroupGetNumber: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxEventGroupGetNumber_Unpriv + MPU_uxEventGroupGetNumber_Priv: + b MPU_uxEventGroupGetNumberImpl + MPU_uxEventGroupGetNumber_Unpriv: + svc #SYSTEM_CALL_uxEventGroupGetNumber +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vEventGroupSetNumber +MPU_vEventGroupSetNumber: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vEventGroupSetNumber_Unpriv + MPU_vEventGroupSetNumber_Priv: + b MPU_vEventGroupSetNumberImpl + MPU_vEventGroupSetNumber_Unpriv: + svc #SYSTEM_CALL_vEventGroupSetNumber +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSend +MPU_xStreamBufferSend: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSend_Unpriv + MPU_xStreamBufferSend_Priv: + b MPU_xStreamBufferSendImpl + MPU_xStreamBufferSend_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferReceive +MPU_xStreamBufferReceive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferReceive_Unpriv + MPU_xStreamBufferReceive_Priv: + b MPU_xStreamBufferReceiveImpl + MPU_xStreamBufferReceive_Unpriv: + svc #SYSTEM_CALL_xStreamBufferReceive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferIsFull +MPU_xStreamBufferIsFull: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferIsFull_Unpriv + MPU_xStreamBufferIsFull_Priv: + b MPU_xStreamBufferIsFullImpl + MPU_xStreamBufferIsFull_Unpriv: + svc #SYSTEM_CALL_xStreamBufferIsFull +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferIsEmpty +MPU_xStreamBufferIsEmpty: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferIsEmpty_Unpriv + MPU_xStreamBufferIsEmpty_Priv: + b MPU_xStreamBufferIsEmptyImpl + MPU_xStreamBufferIsEmpty_Unpriv: + svc #SYSTEM_CALL_xStreamBufferIsEmpty +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSpacesAvailable +MPU_xStreamBufferSpacesAvailable: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSpacesAvailable_Unpriv + MPU_xStreamBufferSpacesAvailable_Priv: + b MPU_xStreamBufferSpacesAvailableImpl + MPU_xStreamBufferSpacesAvailable_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSpacesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferBytesAvailable +MPU_xStreamBufferBytesAvailable: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferBytesAvailable_Unpriv + MPU_xStreamBufferBytesAvailable_Priv: + b MPU_xStreamBufferBytesAvailableImpl + MPU_xStreamBufferBytesAvailable_Unpriv: + svc #SYSTEM_CALL_xStreamBufferBytesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSetTriggerLevel +MPU_xStreamBufferSetTriggerLevel: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSetTriggerLevel_Unpriv + MPU_xStreamBufferSetTriggerLevel_Priv: + b MPU_xStreamBufferSetTriggerLevelImpl + MPU_xStreamBufferSetTriggerLevel_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferNextMessageLengthBytes +MPU_xStreamBufferNextMessageLengthBytes: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv + MPU_xStreamBufferNextMessageLengthBytes_Priv: + b MPU_xStreamBufferNextMessageLengthBytesImpl + MPU_xStreamBufferNextMessageLengthBytes_Unpriv: + svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes +/*-----------------------------------------------------------*/ + +/* Default weak implementations in case one is not available from + * mpu_wrappers because of config options. */ + + PUBWEAK MPU_xTaskDelayUntilImpl +MPU_xTaskDelayUntilImpl: + b MPU_xTaskDelayUntilImpl + + PUBWEAK MPU_xTaskAbortDelayImpl +MPU_xTaskAbortDelayImpl: + b MPU_xTaskAbortDelayImpl + + PUBWEAK MPU_vTaskDelayImpl +MPU_vTaskDelayImpl: + b MPU_vTaskDelayImpl + + PUBWEAK MPU_uxTaskPriorityGetImpl +MPU_uxTaskPriorityGetImpl: + b MPU_uxTaskPriorityGetImpl + + PUBWEAK MPU_eTaskGetStateImpl +MPU_eTaskGetStateImpl: + b MPU_eTaskGetStateImpl + + PUBWEAK MPU_vTaskGetInfoImpl +MPU_vTaskGetInfoImpl: + b MPU_vTaskGetInfoImpl + + PUBWEAK MPU_xTaskGetIdleTaskHandleImpl +MPU_xTaskGetIdleTaskHandleImpl: + b MPU_xTaskGetIdleTaskHandleImpl + + PUBWEAK MPU_vTaskSuspendImpl +MPU_vTaskSuspendImpl: + b MPU_vTaskSuspendImpl + + PUBWEAK MPU_vTaskResumeImpl +MPU_vTaskResumeImpl: + b MPU_vTaskResumeImpl + + PUBWEAK MPU_xTaskGetTickCountImpl +MPU_xTaskGetTickCountImpl: + b MPU_xTaskGetTickCountImpl + + PUBWEAK MPU_uxTaskGetNumberOfTasksImpl +MPU_uxTaskGetNumberOfTasksImpl: + b MPU_uxTaskGetNumberOfTasksImpl + + PUBWEAK MPU_ulTaskGetRunTimeCounterImpl +MPU_ulTaskGetRunTimeCounterImpl: + b MPU_ulTaskGetRunTimeCounterImpl + + PUBWEAK MPU_ulTaskGetRunTimePercentImpl +MPU_ulTaskGetRunTimePercentImpl: + b MPU_ulTaskGetRunTimePercentImpl + + PUBWEAK MPU_ulTaskGetIdleRunTimePercentImpl +MPU_ulTaskGetIdleRunTimePercentImpl: + b MPU_ulTaskGetIdleRunTimePercentImpl + + PUBWEAK MPU_ulTaskGetIdleRunTimeCounterImpl +MPU_ulTaskGetIdleRunTimeCounterImpl: + b MPU_ulTaskGetIdleRunTimeCounterImpl + + PUBWEAK MPU_vTaskSetApplicationTaskTagImpl +MPU_vTaskSetApplicationTaskTagImpl: + b MPU_vTaskSetApplicationTaskTagImpl + + PUBWEAK MPU_xTaskGetApplicationTaskTagImpl +MPU_xTaskGetApplicationTaskTagImpl: + b MPU_xTaskGetApplicationTaskTagImpl + + PUBWEAK MPU_vTaskSetThreadLocalStoragePointerImpl +MPU_vTaskSetThreadLocalStoragePointerImpl: + b MPU_vTaskSetThreadLocalStoragePointerImpl + + PUBWEAK MPU_pvTaskGetThreadLocalStoragePointerImpl +MPU_pvTaskGetThreadLocalStoragePointerImpl: + b MPU_pvTaskGetThreadLocalStoragePointerImpl + + PUBWEAK MPU_uxTaskGetSystemStateImpl +MPU_uxTaskGetSystemStateImpl: + b MPU_uxTaskGetSystemStateImpl + + PUBWEAK MPU_uxTaskGetStackHighWaterMarkImpl +MPU_uxTaskGetStackHighWaterMarkImpl: + b MPU_uxTaskGetStackHighWaterMarkImpl + + PUBWEAK MPU_uxTaskGetStackHighWaterMark2Impl +MPU_uxTaskGetStackHighWaterMark2Impl: + b MPU_uxTaskGetStackHighWaterMark2Impl + + PUBWEAK MPU_xTaskGetCurrentTaskHandleImpl +MPU_xTaskGetCurrentTaskHandleImpl: + b MPU_xTaskGetCurrentTaskHandleImpl + + PUBWEAK MPU_xTaskGetSchedulerStateImpl +MPU_xTaskGetSchedulerStateImpl: + b MPU_xTaskGetSchedulerStateImpl + + PUBWEAK MPU_vTaskSetTimeOutStateImpl +MPU_vTaskSetTimeOutStateImpl: + b MPU_vTaskSetTimeOutStateImpl + + PUBWEAK MPU_xTaskCheckForTimeOutImpl +MPU_xTaskCheckForTimeOutImpl: + b MPU_xTaskCheckForTimeOutImpl + + PUBWEAK MPU_xTaskGenericNotifyImpl +MPU_xTaskGenericNotifyImpl: + b MPU_xTaskGenericNotifyImpl + + PUBWEAK MPU_xTaskGenericNotifyWaitImpl +MPU_xTaskGenericNotifyWaitImpl: + b MPU_xTaskGenericNotifyWaitImpl + + PUBWEAK MPU_ulTaskGenericNotifyTakeImpl +MPU_ulTaskGenericNotifyTakeImpl: + b MPU_ulTaskGenericNotifyTakeImpl + + PUBWEAK MPU_xTaskGenericNotifyStateClearImpl +MPU_xTaskGenericNotifyStateClearImpl: + b MPU_xTaskGenericNotifyStateClearImpl + + PUBWEAK MPU_ulTaskGenericNotifyValueClearImpl +MPU_ulTaskGenericNotifyValueClearImpl: + b MPU_ulTaskGenericNotifyValueClearImpl + + PUBWEAK MPU_xQueueGenericSendImpl +MPU_xQueueGenericSendImpl: + b MPU_xQueueGenericSendImpl + + PUBWEAK MPU_uxQueueMessagesWaitingImpl +MPU_uxQueueMessagesWaitingImpl: + b MPU_uxQueueMessagesWaitingImpl + + PUBWEAK MPU_uxQueueSpacesAvailableImpl +MPU_uxQueueSpacesAvailableImpl: + b MPU_uxQueueSpacesAvailableImpl + + PUBWEAK MPU_xQueueReceiveImpl +MPU_xQueueReceiveImpl: + b MPU_xQueueReceiveImpl + + PUBWEAK MPU_xQueuePeekImpl +MPU_xQueuePeekImpl: + b MPU_xQueuePeekImpl + + PUBWEAK MPU_xQueueSemaphoreTakeImpl +MPU_xQueueSemaphoreTakeImpl: + b MPU_xQueueSemaphoreTakeImpl + + PUBWEAK MPU_xQueueGetMutexHolderImpl +MPU_xQueueGetMutexHolderImpl: + b MPU_xQueueGetMutexHolderImpl + + PUBWEAK MPU_xQueueTakeMutexRecursiveImpl +MPU_xQueueTakeMutexRecursiveImpl: + b MPU_xQueueTakeMutexRecursiveImpl + + PUBWEAK MPU_xQueueGiveMutexRecursiveImpl +MPU_xQueueGiveMutexRecursiveImpl: + b MPU_xQueueGiveMutexRecursiveImpl + + PUBWEAK MPU_xQueueSelectFromSetImpl +MPU_xQueueSelectFromSetImpl: + b MPU_xQueueSelectFromSetImpl + + PUBWEAK MPU_xQueueAddToSetImpl +MPU_xQueueAddToSetImpl: + b MPU_xQueueAddToSetImpl + + PUBWEAK MPU_vQueueAddToRegistryImpl +MPU_vQueueAddToRegistryImpl: + b MPU_vQueueAddToRegistryImpl + + PUBWEAK MPU_vQueueUnregisterQueueImpl +MPU_vQueueUnregisterQueueImpl: + b MPU_vQueueUnregisterQueueImpl + + PUBWEAK MPU_pcQueueGetNameImpl +MPU_pcQueueGetNameImpl: + b MPU_pcQueueGetNameImpl + + PUBWEAK MPU_pvTimerGetTimerIDImpl +MPU_pvTimerGetTimerIDImpl: + b MPU_pvTimerGetTimerIDImpl + + PUBWEAK MPU_vTimerSetTimerIDImpl +MPU_vTimerSetTimerIDImpl: + b MPU_vTimerSetTimerIDImpl + + PUBWEAK MPU_xTimerIsTimerActiveImpl +MPU_xTimerIsTimerActiveImpl: + b MPU_xTimerIsTimerActiveImpl + + PUBWEAK MPU_xTimerGetTimerDaemonTaskHandleImpl +MPU_xTimerGetTimerDaemonTaskHandleImpl: + b MPU_xTimerGetTimerDaemonTaskHandleImpl + + PUBWEAK MPU_xTimerGenericCommandFromTaskImpl +MPU_xTimerGenericCommandFromTaskImpl: + b MPU_xTimerGenericCommandFromTaskImpl + + PUBWEAK MPU_pcTimerGetNameImpl +MPU_pcTimerGetNameImpl: + b MPU_pcTimerGetNameImpl + + PUBWEAK MPU_vTimerSetReloadModeImpl +MPU_vTimerSetReloadModeImpl: + b MPU_vTimerSetReloadModeImpl + + PUBWEAK MPU_xTimerGetReloadModeImpl +MPU_xTimerGetReloadModeImpl: + b MPU_xTimerGetReloadModeImpl + + PUBWEAK MPU_uxTimerGetReloadModeImpl +MPU_uxTimerGetReloadModeImpl: + b MPU_uxTimerGetReloadModeImpl + + PUBWEAK MPU_xTimerGetPeriodImpl +MPU_xTimerGetPeriodImpl: + b MPU_xTimerGetPeriodImpl + + PUBWEAK MPU_xTimerGetExpiryTimeImpl +MPU_xTimerGetExpiryTimeImpl: + b MPU_xTimerGetExpiryTimeImpl + + PUBWEAK MPU_xEventGroupWaitBitsImpl +MPU_xEventGroupWaitBitsImpl: + b MPU_xEventGroupWaitBitsImpl + + PUBWEAK MPU_xEventGroupClearBitsImpl +MPU_xEventGroupClearBitsImpl: + b MPU_xEventGroupClearBitsImpl + + PUBWEAK MPU_xEventGroupSetBitsImpl +MPU_xEventGroupSetBitsImpl: + b MPU_xEventGroupSetBitsImpl + + PUBWEAK MPU_xEventGroupSyncImpl +MPU_xEventGroupSyncImpl: + b MPU_xEventGroupSyncImpl + + PUBWEAK MPU_uxEventGroupGetNumberImpl +MPU_uxEventGroupGetNumberImpl: + b MPU_uxEventGroupGetNumberImpl + + PUBWEAK MPU_vEventGroupSetNumberImpl +MPU_vEventGroupSetNumberImpl: + b MPU_vEventGroupSetNumberImpl + + PUBWEAK MPU_xStreamBufferSendImpl +MPU_xStreamBufferSendImpl: + b MPU_xStreamBufferSendImpl + + PUBWEAK MPU_xStreamBufferReceiveImpl +MPU_xStreamBufferReceiveImpl: + b MPU_xStreamBufferReceiveImpl + + PUBWEAK MPU_xStreamBufferIsFullImpl +MPU_xStreamBufferIsFullImpl: + b MPU_xStreamBufferIsFullImpl + + PUBWEAK MPU_xStreamBufferIsEmptyImpl +MPU_xStreamBufferIsEmptyImpl: + b MPU_xStreamBufferIsEmptyImpl + + PUBWEAK MPU_xStreamBufferSpacesAvailableImpl +MPU_xStreamBufferSpacesAvailableImpl: + b MPU_xStreamBufferSpacesAvailableImpl + + PUBWEAK MPU_xStreamBufferBytesAvailableImpl +MPU_xStreamBufferBytesAvailableImpl: + b MPU_xStreamBufferBytesAvailableImpl + + PUBWEAK MPU_xStreamBufferSetTriggerLevelImpl +MPU_xStreamBufferSetTriggerLevelImpl: + b MPU_xStreamBufferSetTriggerLevelImpl + + PUBWEAK MPU_xStreamBufferNextMessageLengthBytesImpl +MPU_xStreamBufferNextMessageLengthBytesImpl: + b MPU_xStreamBufferNextMessageLengthBytesImpl + +/*-----------------------------------------------------------*/ + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + END diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c new file mode 100644 index 000000000..76d2b2445 --- /dev/null +++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c @@ -0,0 +1,2280 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024-2025 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU includes. */ +#include "mpu_wrappers.h" +#include "mpu_syscall_numbers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration settings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to check the validity of an interrupt priority. + */ +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) ) +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used during system call enter and exit. + */ +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Offsets in the stack to the parameters when inside the SVC handler. + */ +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +#if ( portARMV8M_MINOR_VERSION >= 1 ) + + /* Enable Privileged eXecute Never MPU attribute for the selected memory + * region. */ + #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL ) +#endif /* portARMV8M_MINOR_VERSION >= 1 */ + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Extract first address of the MPU region as encoded in the + * RBAR (Region Base Address Register) value. */ +#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \ + ( ( rbar ) & portMPU_RBAR_ADDRESS_MASK ) + +/* Extract last address of the MPU region as encoded in the + * RLAR (Region Limit Address Register) value. */ +#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \ + ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK ) + +/* Does addr lies within [start, end] address range? */ +#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \ + ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) ) + +/* Is the access request satisfied by the available permissions? */ +#define portIS_AUTHORIZED( accessRequest, permissions ) \ + ( ( ( permissions ) & ( accessRequest ) ) == accessRequest ) + +/* Max value that fits in a uint32_t type. */ +#define portUINT32_MAX ( ~( ( uint32_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. + */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 + +/** + * @brief Constants required to check and configure PACBTI security feature implementation. + */ +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) ) + + #define portCONTROL_UPAC_EN ( 1UL << 7UL ) + #define portCONTROL_PAC_EN ( 1UL << 6UL ) + #define portCONTROL_UBTI_EN ( 1UL << 5UL ) + #define portCONTROL_BTI_EN ( 1UL << 4UL ) + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Extract MPU region's access permissions from the Region Base Address + * Register (RBAR) value. + * + * @param ulRBARValue RBAR value for the MPU region. + * + * @return uint32_t Access permissions. + */ + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + + /** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + /** + * @brief Configures PACBTI features. + * + * This function configures the Pointer Authentication, and Branch Target + * Identification security features as per the user configuration. It returns + * the value of the special purpose CONTROL register accordingly, and optionally + * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M + * architecture based) target supports PACBTI security feature. + * + * @param xWriteControlRegister Used to control whether the special purpose + * CONTROL register should be updated or not. + * + * @return CONTROL register value according to the configured PACBTI option. + */ + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the system call stack so that upon returning from + * SVC, the system call stack is used. + * + * @param pulTaskStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + * @param ucSystemCallNumber The system call number of the system call. + */ + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Raise SVC for exiting from a system call. + */ + void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief This variable is set to pdTRUE when the scheduler is started. + */ + PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + + /** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +/** + * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + /** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + + /** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + + /** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the cpsid instruction + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessPermissions = 0; + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_ONLY ) + { + ulAccessPermissions = tskMPU_READ_PERMISSION; + } + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_WRITE ) + { + ulAccessPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION ); + } + + return ulAccessPermissions; + } + +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } + +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ portOFFSET_TO_PC ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ]; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulSystemCallStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the system call section (i.e. application is + * not raising SVC directly). + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as + * it is non-NULL only during the execution of a system call (i.e. + * between system call enter and exit). + * 3. System call is not for a kernel API disabled by the configuration + * in FreeRTOSConfig.h. + * 4. We do not need to check that ucSystemCallNumber is within range + * because the assembly SVC handler checks that before calling + * this function. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) && + ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) ) + { + pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the system call stack for the stack frame. */ + pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulSystemCallStack[ i ] = pulTaskStack[ i ]; + } + + /* Store the value of the Link Register before the SVC was raised. + * It contains the address of the caller of the System Call entry + * point (i.e. the caller of the MPU_). We need to restore it + * when we exit from the system call. */ + pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; + + /* Store the value of the PSPLIM register before the SVC was raised. + * We need to restore it when we exit from the system call. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* Use the pulSystemCallStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif + + /* Start executing the system call upon returning from this handler. */ + pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; + + /* Raise a request to exit from the system call upon finishing the + * system call. */ + pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; + + /* Remember the location where we should copy the stack frame when we exit from + * the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize; + + /* Record if the hardware used padding to force the stack pointer + * to be double word aligned. */ + if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK ) + { + pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG; + } + else + { + pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG ); + } + + /* We ensure in pxPortInitialiseStack that the system call stack is + * double word aligned and therefore, there is no need of padding. + * Clear the bit[9] of stacked xPSR. */ + pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + + /* Raise the privilege for the duration of the system call. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " bics r0, r1 \n" /* Clear nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */ + { + __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulTaskStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the privileged code (i.e. application is not + * raising SVC directly). This SVC is only raised from + * vRequestSystemCallExit which is in the privileged code section. + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL - + * this means that we previously entered a system call and the + * application is not attempting to exit without entering a system + * call. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) ) + { + pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the task stack for the stack frame. */ + pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulTaskStack[ i ] = pulSystemCallStack[ i ]; + } + + /* Use the pulTaskStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) ); + + /* Return to the caller of the System Call entry point (i.e. the + * caller of the MPU_). */ + pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + /* Ensure that LR has a valid value.*/ + pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + + /* Restore the PSPLIM register to what it was at the time of + * system call entry. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* If the hardware used padding to force the stack pointer + * to be double word aligned, set the stacked xPSR bit[9], + * otherwise clear it. */ + if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG ) + { + pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK; + } + else + { + pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + } + + /* This is not NULL only for the duration of the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; + + /* Drop the privilege before returning to the thread mode. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " orrs r0, r1 \n" /* Set nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xTaskIsPrivileged = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xTaskIsPrivileged = pdTRUE; + } + + return xTaskIsPrivileged; + } + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged, + xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulIndex = 0; + uint32_t ulControl = 0x0; + + xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ + ulIndex++; + + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + ulIndex++; + + #if ( configENABLE_TRUSTZONE == 1 ) + { + xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */ + ulIndex++; + } + #endif /* configENABLE_TRUSTZONE */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + ulIndex++; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Check PACBTI security feature configuration before pushing the + * CONTROL register's value on task's TCB. */ + ulControl = prvConfigurePACBTI( pdFALSE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + if( xRunPrivileged == pdTRUE ) + { + xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + else + { + xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG ); + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ + ulIndex++; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + { + /* Ensure that the system call stack is double word aligned. */ + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) + + ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + /* This is not NULL only for the duration of a system call. */ + xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL; + } + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ]; + ulIndex++; + } + } + #endif /* configENABLE_PAC */ + + return &( xMPUSettings->ulContext[ ulIndex ] ); + } + +#else /* configENABLE_MPU */ + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ + { + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + pxTopOfStack--; + *pxTopOfStack = ulTaskPacKey[ i ]; + } + } + #endif /* configENABLE_PAC */ + + return pxTopOfStack; + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Set the CONTROL register value based on PACBTI security feature + * configuration before starting the first task. */ + ( void ) prvConfigurePACBTI( pdTRUE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + { + xSchedulerRunning = pdTRUE; + } + #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + configSTACK_DEPTH_TYPE uxStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( uxStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* PXN. */ + #if ( portARMV8M_MINOR_VERSION >= 1 ) + { + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ); + } + } + #endif /* portARMV8M_MINOR_VERSION >= 1 */ + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, + uint32_t ulBufferLength, + uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */ + + { + uint32_t i, ulBufferStartAddress, ulBufferEndAddress; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE ) + { + ulBufferStartAddress = ( uint32_t ) pvBuffer; + ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL ); + + for( i = 0; i < portTOTAL_NUM_REGIONS; i++ ) + { + /* Is the MPU region enabled? */ + if( ( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR & portMPU_RLAR_REGION_ENABLE ) == portMPU_RLAR_REGION_ENABLE ) + { + if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_AUTHORIZED( ulAccessRequested, + prvGetRegionAccessPermissions( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ) ) ) + { + xAccessGranted = pdTRUE; + break; + } + } + } + } + } + + return xAccessGranted; + } + +#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings; + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else + { + xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 ) + { + xAccessGranted = pdTRUE; + } + } + } + + return xAccessGranted; + } + + #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + ( void ) lInternalIndexOfKernelObject; + + /* If Access Control List feature is not used, all the tasks have + * access to all the kernel objects. */ + return pdTRUE; + } + + #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + { + uint32_t ulControl = 0x0; + + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); + + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; + + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.h b/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.h new file mode 100644 index 000000000..b7021b024 --- /dev/null +++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kernel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.s b/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.s new file mode 100644 index 000000000..ba6e8e915 --- /dev/null +++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.s @@ -0,0 +1,456 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" + +/* System call numbers includes. */ +#include "mpu_syscall_numbers.h" + +#ifndef configUSE_MPU_WRAPPERS_V1 + #define configUSE_MPU_WRAPPERS_V1 0 +#endif + + EXTERN pxCurrentTCB + EXTERN vTaskSwitchContext + EXTERN vPortSVCHandler_C +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + EXTERN vSystemCallEnter + EXTERN vSystemCallExit +#endif + + PUBLIC xIsPrivileged + PUBLIC vResetPrivilege + PUBLIC vRestoreContextOfFirstTask + PUBLIC vRaisePrivilege + PUBLIC vStartFirstTask + PUBLIC ulSetInterruptMask + PUBLIC vClearInterruptMask + PUBLIC PendSV_Handler + PUBLIC SVC_Handler +/*-----------------------------------------------------------*/ + +/*---------------- Unprivileged Functions -------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION .text:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +xIsPrivileged: + mrs r0, control /* r0 = CONTROL. */ + tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + ite ne + movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vResetPrivilege: + mrs r0, control /* r0 = CONTROL. */ + orr r0, r0, #1 /* r0 = r0 | 1. */ + msr control, r0 /* CONTROL = r0. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +/*----------------- Privileged Functions --------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION privileged_functions:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +vRestoreContextOfFirstTask: + program_mpu_first_task: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r2] /* r0 = pxCurrentTCB. */ + + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + str r2, [r1] /* Disable MPU. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r1, [r2] /* Program MAIR0. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + + movs r3, #4 /* r3 = 4. */ + str r3, [r1] /* Program RNR = 4. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + #if ( configTOTAL_MPU_REGIONS == 16 ) + movs r3, #8 /* r3 = 8. */ + str r3, [r1] /* Program RNR = 8. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + movs r3, #12 /* r3 = 12. */ + str r3, [r1] /* Program RNR = 12. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + orr r2, #1 /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */ + str r2, [r1] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + + restore_context_first_task: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r2] /* r0 = pxCurrentTCB.*/ + ldr r1, [r0] /* r1 = Location of saved context in TCB. */ + + restore_special_regs_first_task: + #if ( configENABLE_PAC == 1 ) + ldmdb r1!, {r2-r5} /* Read task's dedicated PAC key from the task's context. */ + msr PAC_KEY_P_0, r2 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_1, r3 + msr PAC_KEY_P_2, r4 + msr PAC_KEY_P_3, r5 + clrm {r2-r5} /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + ldmdb r1!, {r2-r4, lr} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */ + msr psp, r2 + msr psplim, r3 + msr control, r4 + + restore_general_regs_first_task: + ldmdb r1!, {r4-r11} /* r4-r11 contain hardware saved context. */ + stmia r2!, {r4-r11} /* Copy the hardware saved context on the task stack. */ + ldmdb r1!, {r4-r11} /* r4-r11 restored. */ + + restore_context_done_first_task: + str r1, [r0] /* Save the location where the context should be saved next as the first member of TCB. */ + mov r0, #0 + msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ + bx lr + +#else /* configENABLE_MPU */ + +vRestoreContextOfFirstTask: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + +#if ( configENABLE_PAC == 1 ) + ldmia r0!, {r1-r4} /* Read task's dedicated PAC key from stack. */ + msr PAC_KEY_P_3, r1 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_2, r2 + msr PAC_KEY_P_1, r3 + msr PAC_KEY_P_0, r4 + clrm {r1-r4} /* Clear r1-r4. */ +#endif /* configENABLE_PAC */ + + ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */ + msr psplim, r1 /* Set this task's PSPLIM value. */ + mrs r1, control /* Obtain current control register value. */ + orrs r1, r1, #2 /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */ + msr control, r1 /* Write back the new control register value. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + mov r0, #0 + msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ + bx r2 /* Finally, branch to EXC_RETURN. */ + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +vRaisePrivilege: + mrs r0, control /* Read the CONTROL register. */ + bic r0, r0, #1 /* Clear the bit 0. */ + msr control, r0 /* Write back the new CONTROL value. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vStartFirstTask: + ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */ + ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */ + ldr r0, [r0] /* The first entry in vector table is stack pointer. */ + msr msp, r0 /* Set the MSP back to the start of the stack. */ + cpsie i /* Globally enable interrupts. */ + cpsie f + dsb + isb + svc 102 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */ +/*-----------------------------------------------------------*/ + +ulSetInterruptMask: + mrs r0, basepri /* r0 = basepri. Return original basepri value. */ + mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r1 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vClearInterruptMask: + msr basepri, r0 /* basepri = ulMask. */ + dsb + isb + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +PendSV_Handler: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r2] /* r0 = pxCurrentTCB. */ + ldr r1, [r0] /* r1 = Location in TCB where the context should be saved. */ + mrs r2, psp /* r2 = PSP. */ + + save_general_regs: + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + add r2, r2, #0x20 /* Move r2 to location where s0 is saved. */ + tst lr, #0x10 + ittt eq + vstmiaeq r1!, {s16-s31} /* Store s16-s31. */ + vldmiaeq r2, {s0-s16} /* Copy hardware saved FP context into s0-s16. */ + vstmiaeq r1!, {s0-s16} /* Store hardware saved FP context. */ + sub r2, r2, #0x20 /* Set r2 back to the location of hardware saved context. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + stmia r1!, {r4-r11} /* Store r4-r11. */ + ldmia r2, {r4-r11} /* Copy the hardware saved context into r4-r11. */ + stmia r1!, {r4-r11} /* Store the hardware saved context. */ + + save_special_regs: + mrs r3, psplim /* r3 = PSPLIM. */ + mrs r4, control /* r4 = CONTROL. */ + stmia r1!, {r2-r4, lr} /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ + #if ( configENABLE_PAC == 1 ) + mrs r2, PAC_KEY_P_0 /* Read task's dedicated PAC key from the PAC key registers. */ + mrs r3, PAC_KEY_P_1 + mrs r4, PAC_KEY_P_2 + mrs r5, PAC_KEY_P_3 + stmia r1!, {r2-r5} /* Store the task's dedicated PAC key on the task's context. */ + clrm {r2-r5} /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + + str r1, [r0] /* Save the location from where the context should be restored as the first member of TCB. */ + + select_next_task: + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bl vTaskSwitchContext + mov r0, #0 /* r0 = 0. */ + msr basepri, r0 /* Enable interrupts. */ + + program_mpu: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r2] /* r0 = pxCurrentTCB. */ + + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + str r2, [r1] /* Disable MPU. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r1, [r2] /* Program MAIR0. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + + movs r3, #4 /* r3 = 4. */ + str r3, [r1] /* Program RNR = 4. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + #if ( configTOTAL_MPU_REGIONS == 16 ) + movs r3, #8 /* r3 = 8. */ + str r3, [r1] /* Program RNR = 8. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + movs r3, #12 /* r3 = 12. */ + str r3, [r1] /* Program RNR = 12. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + orr r2, #1 /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */ + str r2, [r1] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + + restore_context: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r2] /* r0 = pxCurrentTCB.*/ + ldr r1, [r0] /* r1 = Location of saved context in TCB. */ + + restore_special_regs: + #if ( configENABLE_PAC == 1 ) + ldmdb r1!, {r2-r5} /* Read task's dedicated PAC key from the task's context. */ + msr PAC_KEY_P_0, r2 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_1, r3 + msr PAC_KEY_P_2, r4 + msr PAC_KEY_P_3, r5 + clrm {r2-r5} /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + ldmdb r1!, {r2-r4, lr} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */ + msr psp, r2 + msr psplim, r3 + msr control, r4 + + restore_general_regs: + ldmdb r1!, {r4-r11} /* r4-r11 contain hardware saved context. */ + stmia r2!, {r4-r11} /* Copy the hardware saved context on the task stack. */ + ldmdb r1!, {r4-r11} /* r4-r11 restored. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 + ittt eq + vldmdbeq r1!, {s0-s16} /* s0-s16 contain hardware saved FP context. */ + vstmiaeq r2!, {s0-s16} /* Copy hardware saved FP context on the task stack. */ + vldmdbeq r1!, {s16-s31} /* Restore s16-s31. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + + restore_context_done: + str r1, [r0] /* Save the location where the context should be saved next as the first member of TCB. */ + bx lr + +#else /* configENABLE_MPU */ + +PendSV_Handler: + mrs r0, psp /* Read PSP in r0. */ +#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + it eq + vstmdbeq r0!, {s16-s31} /* Store the additional FP context registers which are not saved automatically. */ +#endif /* configENABLE_FPU || configENABLE_MVE */ + + mrs r2, psplim /* r2 = PSPLIM. */ + mov r3, lr /* r3 = LR/EXC_RETURN. */ + stmdb r0!, {r2-r11} /* Store on the stack - PSPLIM, LR and registers that are not automatically. */ + +#if ( configENABLE_PAC == 1 ) + mrs r1, PAC_KEY_P_3 /* Read task's dedicated PAC key from the PAC key registers. */ + mrs r2, PAC_KEY_P_2 + mrs r3, PAC_KEY_P_1 + mrs r4, PAC_KEY_P_0 + stmdb r0!, {r1-r4} /* Store the task's dedicated PAC key on the stack. */ + clrm {r1-r4} /* Clear r1-r4. */ +#endif /* configENABLE_PAC */ + + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + str r0, [r1] /* Save the new top of stack in TCB. */ + + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bl vTaskSwitchContext + mov r0, #0 /* r0 = 0. */ + msr basepri, r0 /* Enable interrupts. */ + + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ + +#if ( configENABLE_PAC == 1 ) + ldmia r0!, {r2-r5} /* Read task's dedicated PAC key from stack. */ + msr PAC_KEY_P_3, r2 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_2, r3 + msr PAC_KEY_P_1, r4 + msr PAC_KEY_P_0, r5 + clrm {r2-r5} /* Clear r2-r5. */ +#endif /* configENABLE_PAC */ + + ldmia r0!, {r2-r11} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */ + +#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst r3, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + it eq + vldmiaeq r0!, {s16-s31} /* Restore the additional FP context registers which are not restored automatically. */ +#endif /* configENABLE_FPU || configENABLE_MVE */ + + msr psplim, r2 /* Restore the PSPLIM register value for the task. */ + msr psp, r0 /* Remember the new top of stack for the task. */ + bx r3 + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + +SVC_Handler: + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + + ldr r1, [r0, #24] + ldrb r2, [r1, #-2] + cmp r2, #NUM_SYSTEM_CALLS + blt syscall_enter + cmp r2, #104 /* portSVC_SYSTEM_CALL_EXIT. */ + beq syscall_exit + b vPortSVCHandler_C + + syscall_enter: + mov r1, lr + b vSystemCallEnter + + syscall_exit: + mov r1, lr + b vSystemCallExit + +#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +SVC_Handler: + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + b vPortSVCHandler_C + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + + END diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h new file mode 100644 index 000000000..6e543efb5 --- /dev/null +++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacro.h @@ -0,0 +1,88 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M35P" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portARMV8M_MINOR_VERSION 0 +#define portDONT_DISCARD __root +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +#ifndef configENABLE_MVE + #define configENABLE_MVE 0 +#elif ( configENABLE_MVE != 0 ) + #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M35. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ +#pragma diag_suppress=Be006 +#pragma diag_suppress=Pa082 +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h new file mode 100644 index 000000000..f373bcad5 --- /dev/null +++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/portmacrocommon.h @@ -0,0 +1,582 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACROCOMMON_H +#define PORTMACROCOMMON_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. +#endif /* configENABLE_FPU */ + +#ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. +#endif /* configENABLE_MPU */ + +#ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. +#endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() +#define portINLINE __inline +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif +#define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ +extern BaseType_t xPortIsInsideInterrupt( void ); + +extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + +extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; +extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + +extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; +extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + +#if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_PAC == 1 ) + + /** + * @brief Generates 128-bit task's random PAC key. + * + * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be + * filled with a 128-bit random number. + */ + void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); + +#endif /* configENABLE_PAC */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ +#if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) +#else + #define portPRIVILEGE_BIT ( 0x0UL ) +#endif /* configENABLE_MPU */ + +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ +#define portPRIVILEGED_FLASH_REGION ( 0UL ) +#define portUNPRIVILEGED_FLASH_REGION ( 1UL ) +#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) +#define portPRIVILEGED_RAM_REGION ( 3UL ) +#define portSTACK_REGION ( 4UL ) +#define portFIRST_CONFIGURABLE_REGION ( 5UL ) +#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) +#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) +#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ +#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ +#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ +#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ +#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ +#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ +#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ +#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) +#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) +#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + +#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) +#define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) +#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) +#define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + +#define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + #ifndef configSYSTEM_CALL_STACK_SIZE + #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. + #endif + + /** + * @brief System call stack. + */ + typedef struct SYSTEM_CALL_STACK_INFO + { + uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; + uint32_t * pulSystemCallStack; + uint32_t * pulSystemCallStackLimit; + uint32_t * pulTaskStack; + uint32_t ulLinkRegisterAtSystemCallEntry; + uint32_t ulStackLimitRegisterAtSystemCallEntry; + } xSYSTEM_CALL_STACK_INFO; + + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + /** + * @brief MPU settings as stored in the TCB. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><-----------><----> + * 16 17 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 71 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 17 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 55 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | | | PC, xPSR | EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><-----------><----> + * 16 17 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 70 + + #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + /* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 17 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 54 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+------------------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +----------+-----------------+------------------------------+------------+-----+ + * + * <---------><----------------><------------------------------><-----------><----> + * 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 38 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+----------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | PC, xPSR | EXC_RETURN | | | + * +----------+-----------------+----------------------+------------+-----+ + * + * <---------><----------------><----------------------><-----------><----> + * 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 37 + + #else /* #if( configENABLE_TRUSTZONE == 1 ) */ + + /* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) + + /* Size of an Access Control List (ACL) entry in bits. */ + #define portACL_ENTRY_SIZE_BITS ( 32U ) + + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + uint32_t ulContext[ MAX_CONTEXT_SIZE ]; + uint32_t ulTaskFlags; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo; + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ]; + #endif + #endif + } xMPU_SETTINGS; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Validate priority of ISRs that are allowed to call FreeRTOS + * system calls. + */ +#if ( configASSERT_DEFINED == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif +#endif + +/** + * @brief SVC numbers. + */ +#define portSVC_ALLOCATE_SECURE_CONTEXT 100 +#define portSVC_FREE_SECURE_CONTEXT 101 +#define portSVC_START_SCHEDULER 102 +#define portSVC_RAISE_PRIVILEGE 103 +#define portSVC_SYSTEM_CALL_EXIT 104 +#define portSVC_YIELD 105 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) +#endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() +#else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + extern BaseType_t xPortIsTaskPrivileged( void ); + +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACROCOMMON_H */ diff --git a/portable/IAR/ARM_CM4F/port.c b/portable/IAR/ARM_CM4F/port.c new file mode 100644 index 000000000..b96329a05 --- /dev/null +++ b/portable/IAR/ARM_CM4F/port.c @@ -0,0 +1,776 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ARM CM4F port. +*----------------------------------------------------------*/ + +/* IAR includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#ifndef __ARMVFP__ + #error This port can only be used when the project options are configured to enable hardware floating point support. +#endif + +#if ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) + #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ +#endif + +/* Prototype of all Interrupt Service Routines (ISRs). */ +typedef void ( * portISR_t )( void ); + +/* Constants required to manipulate the core. Registers first... */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +/* ...then bits in the registers. */ +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) + +/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7 + * r0p1 port. */ +#define portCPUID ( *( ( volatile uint32_t * ) 0xE000ed00 ) ) +#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL ) +#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL ) + +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL ) +#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL ) + +/* Constants used to check the installation of the FreeRTOS interrupt handlers. */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xE000ED08 ) ) +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) + +/* Constants required to check the validity of an interrupt priority. */ +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) + +/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */ +#define portVECTACTIVE_MASK ( 0xFFUL ) + +/* Constants required to manipulate the VFP. */ +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */ +#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) +#define portINITIAL_EXC_RETURN ( 0xfffffffd ) + +/* The systick is a 24-bit counter. */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/* A fiddle factor to estimate the number of SysTick counts that would have + * occurred while the SysTick counter is stopped during tickless idle + * calculations. */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) + +/* For strict compliance with the Cortex-M spec the task start address should + * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */ +#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL ) + +/* Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ); + +/* + * Exception handlers. + */ +void xPortSysTickHandler( void ); + +/* + * Start first task is a separate function so it can be tested in isolation. + */ +extern void vPortStartFirstTask( void ); + +/* + * Turn the VFP on. + */ +extern void vPortEnableVFP( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/* + * FreeRTOS handlers implemented in assembly. + */ +extern void vPortSVCHandler( void ); +extern void xPortPendSVHandler( void ); +/*-----------------------------------------------------------*/ + +/* Each task maintains its own interrupt status in the critical nesting + * variable. */ +static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +/* + * The number of SysTick increments that make up one tick period. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulTimerCountsForOneTick = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * The maximum number of tick periods that can be suppressed is limited by the + * 24 bit resolution of the SysTick timer. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t xMaximumPossibleSuppressedTicks = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Compensate for the CPU cycles that pass while the SysTick is stopped (low + * power functionality only. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( configASSERT_DEFINED == 1 ) + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16; +#endif /* configASSERT_DEFINED */ + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + + /* Offset added to account for the way the MCU uses the stack on entry/exit + * of interrupts, and to ensure alignment. */ + pxTopOfStack--; + + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */ + + /* Save code space by skipping register initialisation. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + + /* A save method is being used that requires each task to maintain its + * own exec return value. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; + + pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ + configASSERT( uxCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + /* This port can be used on all revisions of the Cortex-M7 core other than + * the r0p1 parts. r0p1 parts should use the port from the + * /source/portable/GCC/ARM_CM7/r0p1 directory. */ + configASSERT( portCPUID != portCORTEX_M7_r0p1_ID ); + configASSERT( portCPUID != portCORTEX_M7_r0p0_ID ); + + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions vPortSVCHandler and + * xPortPendSVHandler for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * vPortSVCHandler and xPortPendSVHandler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( configASSERT_DEFINED == 1 ) + { + volatile uint8_t ucOriginalPriority; + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * Save the interrupt priority value that is about to be clobbered. */ + ucOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to all + * possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + + /* Restore the clobbered interrupt priority register to its original + * value. */ + *pucFirstUserPriorityRegister = ucOriginalPriority; + } + #endif /* configASSERT_DEFINED */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + /* Ensure the VFP is enabled - it should be anyway. */ + vPortEnableVFP(); + + /* Lazy save always. */ + *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ + if( uxCriticalNesting == 1 ) + { + configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + /* The SysTick runs at the lowest interrupt priority, so when this interrupt + * executes all interrupts must be unmasked. There is therefore no need to + * save and then restore the interrupt mask value as its value is already + * known. */ + portDISABLE_INTERRUPTS(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + + /* A context switch is required. Context switching is performed in + * the PendSV interrupt. Pend the PendSV interrupt. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + portENABLE_INTERRUPTS(); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __disable_interrupt(); + __DSB(); + __ISB(); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the __disable_interrupt() + * call above. */ + __enable_interrupt(); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __DSB(); + __WFI(); + __ISB(); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the __disable_interrupt() call above. */ + __enable_interrupt(); + __DSB(); + __ISB(); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __disable_interrupt(); + __DSB(); + __ISB(); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __enable_interrupt(); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +__weak void vPortSetupTimerInterrupt( void ) +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and clear the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); +} +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* configASSERT_DEFINED */ diff --git a/portable/IAR/ARM_CM4F/portasm.s b/portable/IAR/ARM_CM4F/portasm.s new file mode 100644 index 000000000..a2e8c3009 --- /dev/null +++ b/portable/IAR/ARM_CM4F/portasm.s @@ -0,0 +1,149 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include + + RSEG CODE:CODE(2) + thumb + + EXTERN pxCurrentTCB + EXTERN vTaskSwitchContext + + PUBLIC xPortPendSVHandler + PUBLIC vPortSVCHandler + PUBLIC vPortStartFirstTask + PUBLIC vPortEnableVFP + + +/*-----------------------------------------------------------*/ + +xPortPendSVHandler: + mrs r0, psp + isb + /* Get the location of the current TCB. */ + ldr r3, =pxCurrentTCB + ldr r2, [r3] + + /* Is the task using the FPU context? If so, push high vfp registers. */ + tst r14, #0x10 + it eq + vstmdbeq r0!, {s16-s31} + + /* Save the core registers. */ + stmdb r0!, {r4-r11, r14} + + /* Save the new top of stack into the first member of the TCB. */ + str r0, [r2] + + stmdb sp!, {r0, r3} + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 + dsb + isb + bl vTaskSwitchContext + mov r0, #0 + msr basepri, r0 + ldmia sp!, {r0, r3} + + /* The first item in pxCurrentTCB is the task top of stack. */ + ldr r1, [r3] + ldr r0, [r1] + + /* Pop the core registers. */ + ldmia r0!, {r4-r11, r14} + + /* Is the task using the FPU context? If so, pop the high vfp registers + too. */ + tst r14, #0x10 + it eq + vldmiaeq r0!, {s16-s31} + + msr psp, r0 + isb + #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */ + #if WORKAROUND_PMU_CM001 == 1 + push { r14 } + pop { pc } + #endif + #endif + + bx r14 + + +/*-----------------------------------------------------------*/ + +vPortSVCHandler: + /* Get the location of the current TCB. */ + ldr r3, =pxCurrentTCB + ldr r1, [r3] + ldr r0, [r1] + /* Pop the core registers. */ + ldmia r0!, {r4-r11, r14} + msr psp, r0 + isb + mov r0, #0 + msr basepri, r0 + bx r14 + +/*-----------------------------------------------------------*/ + +vPortStartFirstTask + /* Use the NVIC offset register to locate the stack. */ + ldr r0, =0xE000ED08 + ldr r0, [r0] + ldr r0, [r0] + /* Set the msp back to the start of the stack. */ + msr msp, r0 + /* Clear the bit that indicates the FPU is in use in case the FPU was used + before the scheduler was started - which would otherwise result in the + unnecessary leaving of space in the SVC stack for lazy saving of FPU + registers. */ + mov r0, #0 + msr control, r0 + /* Call SVC to start the first task. */ + cpsie i + cpsie f + dsb + isb + svc 0 + +/*-----------------------------------------------------------*/ + +vPortEnableVFP: + /* The FPU enable bits are in the CPACR. */ + ldr.w r0, =0xE000ED88 + ldr r1, [r0] + + /* Enable CP10 and CP11 coprocessors, then save back. */ + orr r1, r1, #( 0xf << 20 ) + str r1, [r0] + bx r14 + + + + END diff --git a/portable/IAR/ARM_CM4F/portmacro.h b/portable/IAR/ARM_CM4F/portmacro.h new file mode 100644 index 000000000..f3d8ace9d --- /dev/null +++ b/portable/IAR/ARM_CM4F/portmacro.h @@ -0,0 +1,225 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* IAR includes. */ +#include + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +/*-----------------------------------------------------------*/ + +/* Compiler directives. */ +#define portWEAK_SYMBOL __attribute__( ( weak ) ) + +/*-----------------------------------------------------------*/ + + +/* Scheduler utilities. */ +#define portYIELD() \ + { \ + /* Set a PendSV to request a context switch. */ \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + __DSB(); \ + __ISB(); \ + } + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portYIELD(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) + +/*-----------------------------------------------------------*/ + +/* Architecture specific optimisations. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portDISABLE_INTERRUPTS() \ + { \ + __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \ + __DSB(); \ + __ISB(); \ + } + +#define portENABLE_INTERRUPTS() __set_BASEPRI( 0 ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +#define portSET_INTERRUPT_MASK_FROM_ISR() __get_BASEPRI(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) __set_BASEPRI( x ) +/*-----------------------------------------------------------*/ + +/* Tickless idle/low power functionality. */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not necessary for to use this port. They are defined so the common demo files + * (which build with all the ports) will build. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif + +/* portNOP() is not required by this port. */ +#define portNOP() + +#define portINLINE __inline + +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif + +/*-----------------------------------------------------------*/ + +portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} + +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ +#pragma diag_suppress=Pe191 +#pragma diag_suppress=Pa082 + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/IAR/ARM_CM4F_MPU/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM4F_MPU/mpu_wrappers_v2_asm.S new file mode 100644 index 000000000..f01c01d42 --- /dev/null +++ b/portable/IAR/ARM_CM4F_MPU/mpu_wrappers_v2_asm.S @@ -0,0 +1,1246 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Including FreeRTOSConfig.h here will cause build errors if the header file + * contains code not understood by the assembler - for example the 'extern' keyword. + * To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so + * the code is included in C files but excluded by the preprocessor in assembly + * files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" +#include "mpu_syscall_numbers.h" + + SECTION freertos_system_calls:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +#ifndef configUSE_MPU_WRAPPERS_V1 + #define configUSE_MPU_WRAPPERS_V1 0 +#endif + +/*-----------------------------------------------------------*/ + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + PUBLIC MPU_xTaskDelayUntil +MPU_xTaskDelayUntil: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskDelayUntil_Unpriv + MPU_xTaskDelayUntil_Priv: + b MPU_xTaskDelayUntilImpl + MPU_xTaskDelayUntil_Unpriv: + svc #SYSTEM_CALL_xTaskDelayUntil +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskAbortDelay +MPU_xTaskAbortDelay: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskAbortDelay_Unpriv + MPU_xTaskAbortDelay_Priv: + b MPU_xTaskAbortDelayImpl + MPU_xTaskAbortDelay_Unpriv: + svc #SYSTEM_CALL_xTaskAbortDelay +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskDelay +MPU_vTaskDelay: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskDelay_Unpriv + MPU_vTaskDelay_Priv: + b MPU_vTaskDelayImpl + MPU_vTaskDelay_Unpriv: + svc #SYSTEM_CALL_vTaskDelay +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskPriorityGet +MPU_uxTaskPriorityGet: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskPriorityGet_Unpriv + MPU_uxTaskPriorityGet_Priv: + b MPU_uxTaskPriorityGetImpl + MPU_uxTaskPriorityGet_Unpriv: + svc #SYSTEM_CALL_uxTaskPriorityGet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_eTaskGetState +MPU_eTaskGetState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_eTaskGetState_Unpriv + MPU_eTaskGetState_Priv: + b MPU_eTaskGetStateImpl + MPU_eTaskGetState_Unpriv: + svc #SYSTEM_CALL_eTaskGetState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskGetInfo +MPU_vTaskGetInfo: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskGetInfo_Unpriv + MPU_vTaskGetInfo_Priv: + b MPU_vTaskGetInfoImpl + MPU_vTaskGetInfo_Unpriv: + svc #SYSTEM_CALL_vTaskGetInfo +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetIdleTaskHandle +MPU_xTaskGetIdleTaskHandle: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetIdleTaskHandle_Unpriv + MPU_xTaskGetIdleTaskHandle_Priv: + b MPU_xTaskGetIdleTaskHandleImpl + MPU_xTaskGetIdleTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTaskGetIdleTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSuspend +MPU_vTaskSuspend: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSuspend_Unpriv + MPU_vTaskSuspend_Priv: + b MPU_vTaskSuspendImpl + MPU_vTaskSuspend_Unpriv: + svc #SYSTEM_CALL_vTaskSuspend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskResume +MPU_vTaskResume: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskResume_Unpriv + MPU_vTaskResume_Priv: + b MPU_vTaskResumeImpl + MPU_vTaskResume_Unpriv: + svc #SYSTEM_CALL_vTaskResume +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetTickCount +MPU_xTaskGetTickCount: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetTickCount_Unpriv + MPU_xTaskGetTickCount_Priv: + b MPU_xTaskGetTickCountImpl + MPU_xTaskGetTickCount_Unpriv: + svc #SYSTEM_CALL_xTaskGetTickCount +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetNumberOfTasks +MPU_uxTaskGetNumberOfTasks: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetNumberOfTasks_Unpriv + MPU_uxTaskGetNumberOfTasks_Priv: + b MPU_uxTaskGetNumberOfTasksImpl + MPU_uxTaskGetNumberOfTasks_Unpriv: + svc #SYSTEM_CALL_uxTaskGetNumberOfTasks +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetRunTimeCounter +MPU_ulTaskGetRunTimeCounter: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetRunTimeCounter_Unpriv + MPU_ulTaskGetRunTimeCounter_Priv: + b MPU_ulTaskGetRunTimeCounterImpl + MPU_ulTaskGetRunTimeCounter_Unpriv: + svc #SYSTEM_CALL_ulTaskGetRunTimeCounter +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetRunTimePercent +MPU_ulTaskGetRunTimePercent: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetRunTimePercent_Unpriv + MPU_ulTaskGetRunTimePercent_Priv: + b MPU_ulTaskGetRunTimePercentImpl + MPU_ulTaskGetRunTimePercent_Unpriv: + svc #SYSTEM_CALL_ulTaskGetRunTimePercent +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetIdleRunTimePercent +MPU_ulTaskGetIdleRunTimePercent: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetIdleRunTimePercent_Unpriv + MPU_ulTaskGetIdleRunTimePercent_Priv: + b MPU_ulTaskGetIdleRunTimePercentImpl + MPU_ulTaskGetIdleRunTimePercent_Unpriv: + svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetIdleRunTimeCounter +MPU_ulTaskGetIdleRunTimeCounter: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv + MPU_ulTaskGetIdleRunTimeCounter_Priv: + b MPU_ulTaskGetIdleRunTimeCounterImpl + MPU_ulTaskGetIdleRunTimeCounter_Unpriv: + svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetApplicationTaskTag +MPU_vTaskSetApplicationTaskTag: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetApplicationTaskTag_Unpriv + MPU_vTaskSetApplicationTaskTag_Priv: + b MPU_vTaskSetApplicationTaskTagImpl + MPU_vTaskSetApplicationTaskTag_Unpriv: + svc #SYSTEM_CALL_vTaskSetApplicationTaskTag +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetApplicationTaskTag +MPU_xTaskGetApplicationTaskTag: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetApplicationTaskTag_Unpriv + MPU_xTaskGetApplicationTaskTag_Priv: + b MPU_xTaskGetApplicationTaskTagImpl + MPU_xTaskGetApplicationTaskTag_Unpriv: + svc #SYSTEM_CALL_xTaskGetApplicationTaskTag +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetThreadLocalStoragePointer +MPU_vTaskSetThreadLocalStoragePointer: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv + MPU_vTaskSetThreadLocalStoragePointer_Priv: + b MPU_vTaskSetThreadLocalStoragePointerImpl + MPU_vTaskSetThreadLocalStoragePointer_Unpriv: + svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pvTaskGetThreadLocalStoragePointer +MPU_pvTaskGetThreadLocalStoragePointer: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv + MPU_pvTaskGetThreadLocalStoragePointer_Priv: + b MPU_pvTaskGetThreadLocalStoragePointerImpl + MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: + svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetSystemState +MPU_uxTaskGetSystemState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetSystemState_Unpriv + MPU_uxTaskGetSystemState_Priv: + b MPU_uxTaskGetSystemStateImpl + MPU_uxTaskGetSystemState_Unpriv: + svc #SYSTEM_CALL_uxTaskGetSystemState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetStackHighWaterMark +MPU_uxTaskGetStackHighWaterMark: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetStackHighWaterMark_Unpriv + MPU_uxTaskGetStackHighWaterMark_Priv: + b MPU_uxTaskGetStackHighWaterMarkImpl + MPU_uxTaskGetStackHighWaterMark_Unpriv: + svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetStackHighWaterMark2 +MPU_uxTaskGetStackHighWaterMark2: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetStackHighWaterMark2_Unpriv + MPU_uxTaskGetStackHighWaterMark2_Priv: + b MPU_uxTaskGetStackHighWaterMark2Impl + MPU_uxTaskGetStackHighWaterMark2_Unpriv: + svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2 +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetCurrentTaskHandle +MPU_xTaskGetCurrentTaskHandle: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetCurrentTaskHandle_Unpriv + MPU_xTaskGetCurrentTaskHandle_Priv: + b MPU_xTaskGetCurrentTaskHandleImpl + MPU_xTaskGetCurrentTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetSchedulerState +MPU_xTaskGetSchedulerState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetSchedulerState_Unpriv + MPU_xTaskGetSchedulerState_Priv: + b MPU_xTaskGetSchedulerStateImpl + MPU_xTaskGetSchedulerState_Unpriv: + svc #SYSTEM_CALL_xTaskGetSchedulerState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetTimeOutState +MPU_vTaskSetTimeOutState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetTimeOutState_Unpriv + MPU_vTaskSetTimeOutState_Priv: + b MPU_vTaskSetTimeOutStateImpl + MPU_vTaskSetTimeOutState_Unpriv: + svc #SYSTEM_CALL_vTaskSetTimeOutState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskCheckForTimeOut +MPU_xTaskCheckForTimeOut: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskCheckForTimeOut_Unpriv + MPU_xTaskCheckForTimeOut_Priv: + b MPU_xTaskCheckForTimeOutImpl + MPU_xTaskCheckForTimeOut_Unpriv: + svc #SYSTEM_CALL_xTaskCheckForTimeOut +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyEntry +MPU_xTaskGenericNotifyEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotify_Unpriv + MPU_xTaskGenericNotify_Priv: + b MPU_xTaskGenericNotifyImpl + MPU_xTaskGenericNotify_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotify +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyWaitEntry +MPU_xTaskGenericNotifyWaitEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotifyWait_Unpriv + MPU_xTaskGenericNotifyWait_Priv: + b MPU_xTaskGenericNotifyWaitImpl + MPU_xTaskGenericNotifyWait_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotifyWait +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGenericNotifyTake +MPU_ulTaskGenericNotifyTake: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGenericNotifyTake_Unpriv + MPU_ulTaskGenericNotifyTake_Priv: + b MPU_ulTaskGenericNotifyTakeImpl + MPU_ulTaskGenericNotifyTake_Unpriv: + svc #SYSTEM_CALL_ulTaskGenericNotifyTake +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyStateClear +MPU_xTaskGenericNotifyStateClear: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotifyStateClear_Unpriv + MPU_xTaskGenericNotifyStateClear_Priv: + b MPU_xTaskGenericNotifyStateClearImpl + MPU_xTaskGenericNotifyStateClear_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotifyStateClear +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGenericNotifyValueClear +MPU_ulTaskGenericNotifyValueClear: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGenericNotifyValueClear_Unpriv + MPU_ulTaskGenericNotifyValueClear_Priv: + b MPU_ulTaskGenericNotifyValueClearImpl + MPU_ulTaskGenericNotifyValueClear_Unpriv: + svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGenericSend +MPU_xQueueGenericSend: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGenericSend_Unpriv + MPU_xQueueGenericSend_Priv: + b MPU_xQueueGenericSendImpl + MPU_xQueueGenericSend_Unpriv: + svc #SYSTEM_CALL_xQueueGenericSend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxQueueMessagesWaiting +MPU_uxQueueMessagesWaiting: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxQueueMessagesWaiting_Unpriv + MPU_uxQueueMessagesWaiting_Priv: + b MPU_uxQueueMessagesWaitingImpl + MPU_uxQueueMessagesWaiting_Unpriv: + svc #SYSTEM_CALL_uxQueueMessagesWaiting +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxQueueSpacesAvailable +MPU_uxQueueSpacesAvailable: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxQueueSpacesAvailable_Unpriv + MPU_uxQueueSpacesAvailable_Priv: + b MPU_uxQueueSpacesAvailableImpl + MPU_uxQueueSpacesAvailable_Unpriv: + svc #SYSTEM_CALL_uxQueueSpacesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueReceive +MPU_xQueueReceive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueReceive_Unpriv + MPU_xQueueReceive_Priv: + b MPU_xQueueReceiveImpl + MPU_xQueueReceive_Unpriv: + svc #SYSTEM_CALL_xQueueReceive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueuePeek +MPU_xQueuePeek: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueuePeek_Unpriv + MPU_xQueuePeek_Priv: + b MPU_xQueuePeekImpl + MPU_xQueuePeek_Unpriv: + svc #SYSTEM_CALL_xQueuePeek +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueSemaphoreTake +MPU_xQueueSemaphoreTake: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueSemaphoreTake_Unpriv + MPU_xQueueSemaphoreTake_Priv: + b MPU_xQueueSemaphoreTakeImpl + MPU_xQueueSemaphoreTake_Unpriv: + svc #SYSTEM_CALL_xQueueSemaphoreTake +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGetMutexHolder +MPU_xQueueGetMutexHolder: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGetMutexHolder_Unpriv + MPU_xQueueGetMutexHolder_Priv: + b MPU_xQueueGetMutexHolderImpl + MPU_xQueueGetMutexHolder_Unpriv: + svc #SYSTEM_CALL_xQueueGetMutexHolder +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueTakeMutexRecursive +MPU_xQueueTakeMutexRecursive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueTakeMutexRecursive_Unpriv + MPU_xQueueTakeMutexRecursive_Priv: + b MPU_xQueueTakeMutexRecursiveImpl + MPU_xQueueTakeMutexRecursive_Unpriv: + svc #SYSTEM_CALL_xQueueTakeMutexRecursive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGiveMutexRecursive +MPU_xQueueGiveMutexRecursive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGiveMutexRecursive_Unpriv + MPU_xQueueGiveMutexRecursive_Priv: + b MPU_xQueueGiveMutexRecursiveImpl + MPU_xQueueGiveMutexRecursive_Unpriv: + svc #SYSTEM_CALL_xQueueGiveMutexRecursive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueSelectFromSet +MPU_xQueueSelectFromSet: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueSelectFromSet_Unpriv + MPU_xQueueSelectFromSet_Priv: + b MPU_xQueueSelectFromSetImpl + MPU_xQueueSelectFromSet_Unpriv: + svc #SYSTEM_CALL_xQueueSelectFromSet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueAddToSet +MPU_xQueueAddToSet: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueAddToSet_Unpriv + MPU_xQueueAddToSet_Priv: + b MPU_xQueueAddToSetImpl + MPU_xQueueAddToSet_Unpriv: + svc #SYSTEM_CALL_xQueueAddToSet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vQueueAddToRegistry +MPU_vQueueAddToRegistry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vQueueAddToRegistry_Unpriv + MPU_vQueueAddToRegistry_Priv: + b MPU_vQueueAddToRegistryImpl + MPU_vQueueAddToRegistry_Unpriv: + svc #SYSTEM_CALL_vQueueAddToRegistry +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vQueueUnregisterQueue +MPU_vQueueUnregisterQueue: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vQueueUnregisterQueue_Unpriv + MPU_vQueueUnregisterQueue_Priv: + b MPU_vQueueUnregisterQueueImpl + MPU_vQueueUnregisterQueue_Unpriv: + svc #SYSTEM_CALL_vQueueUnregisterQueue +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pcQueueGetName +MPU_pcQueueGetName: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pcQueueGetName_Unpriv + MPU_pcQueueGetName_Priv: + b MPU_pcQueueGetNameImpl + MPU_pcQueueGetName_Unpriv: + svc #SYSTEM_CALL_pcQueueGetName +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pvTimerGetTimerID +MPU_pvTimerGetTimerID: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pvTimerGetTimerID_Unpriv + MPU_pvTimerGetTimerID_Priv: + b MPU_pvTimerGetTimerIDImpl + MPU_pvTimerGetTimerID_Unpriv: + svc #SYSTEM_CALL_pvTimerGetTimerID +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTimerSetTimerID +MPU_vTimerSetTimerID: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTimerSetTimerID_Unpriv + MPU_vTimerSetTimerID_Priv: + b MPU_vTimerSetTimerIDImpl + MPU_vTimerSetTimerID_Unpriv: + svc #SYSTEM_CALL_vTimerSetTimerID +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerIsTimerActive +MPU_xTimerIsTimerActive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerIsTimerActive_Unpriv + MPU_xTimerIsTimerActive_Priv: + b MPU_xTimerIsTimerActiveImpl + MPU_xTimerIsTimerActive_Unpriv: + svc #SYSTEM_CALL_xTimerIsTimerActive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetTimerDaemonTaskHandle +MPU_xTimerGetTimerDaemonTaskHandle: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv + MPU_xTimerGetTimerDaemonTaskHandle_Priv: + b MPU_xTimerGetTimerDaemonTaskHandleImpl + MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGenericCommandFromTaskEntry +MPU_xTimerGenericCommandFromTaskEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGenericCommandFromTask_Unpriv + MPU_xTimerGenericCommandFromTask_Priv: + b MPU_xTimerGenericCommandFromTaskImpl + MPU_xTimerGenericCommandFromTask_Unpriv: + svc #SYSTEM_CALL_xTimerGenericCommandFromTask +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pcTimerGetName +MPU_pcTimerGetName: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pcTimerGetName_Unpriv + MPU_pcTimerGetName_Priv: + b MPU_pcTimerGetNameImpl + MPU_pcTimerGetName_Unpriv: + svc #SYSTEM_CALL_pcTimerGetName +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTimerSetReloadMode +MPU_vTimerSetReloadMode: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTimerSetReloadMode_Unpriv + MPU_vTimerSetReloadMode_Priv: + b MPU_vTimerSetReloadModeImpl + MPU_vTimerSetReloadMode_Unpriv: + svc #SYSTEM_CALL_vTimerSetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetReloadMode +MPU_xTimerGetReloadMode: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetReloadMode_Unpriv + MPU_xTimerGetReloadMode_Priv: + b MPU_xTimerGetReloadModeImpl + MPU_xTimerGetReloadMode_Unpriv: + svc #SYSTEM_CALL_xTimerGetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTimerGetReloadMode +MPU_uxTimerGetReloadMode: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTimerGetReloadMode_Unpriv + MPU_uxTimerGetReloadMode_Priv: + b MPU_uxTimerGetReloadModeImpl + MPU_uxTimerGetReloadMode_Unpriv: + svc #SYSTEM_CALL_uxTimerGetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetPeriod +MPU_xTimerGetPeriod: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetPeriod_Unpriv + MPU_xTimerGetPeriod_Priv: + b MPU_xTimerGetPeriodImpl + MPU_xTimerGetPeriod_Unpriv: + svc #SYSTEM_CALL_xTimerGetPeriod +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetExpiryTime +MPU_xTimerGetExpiryTime: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetExpiryTime_Unpriv + MPU_xTimerGetExpiryTime_Priv: + b MPU_xTimerGetExpiryTimeImpl + MPU_xTimerGetExpiryTime_Unpriv: + svc #SYSTEM_CALL_xTimerGetExpiryTime +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupWaitBitsEntry +MPU_xEventGroupWaitBitsEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupWaitBits_Unpriv + MPU_xEventGroupWaitBits_Priv: + b MPU_xEventGroupWaitBitsImpl + MPU_xEventGroupWaitBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupWaitBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupClearBits +MPU_xEventGroupClearBits: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupClearBits_Unpriv + MPU_xEventGroupClearBits_Priv: + b MPU_xEventGroupClearBitsImpl + MPU_xEventGroupClearBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupClearBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupSetBits +MPU_xEventGroupSetBits: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupSetBits_Unpriv + MPU_xEventGroupSetBits_Priv: + b MPU_xEventGroupSetBitsImpl + MPU_xEventGroupSetBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupSetBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupSync +MPU_xEventGroupSync: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupSync_Unpriv + MPU_xEventGroupSync_Priv: + b MPU_xEventGroupSyncImpl + MPU_xEventGroupSync_Unpriv: + svc #SYSTEM_CALL_xEventGroupSync +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxEventGroupGetNumber +MPU_uxEventGroupGetNumber: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxEventGroupGetNumber_Unpriv + MPU_uxEventGroupGetNumber_Priv: + b MPU_uxEventGroupGetNumberImpl + MPU_uxEventGroupGetNumber_Unpriv: + svc #SYSTEM_CALL_uxEventGroupGetNumber +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vEventGroupSetNumber +MPU_vEventGroupSetNumber: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vEventGroupSetNumber_Unpriv + MPU_vEventGroupSetNumber_Priv: + b MPU_vEventGroupSetNumberImpl + MPU_vEventGroupSetNumber_Unpriv: + svc #SYSTEM_CALL_vEventGroupSetNumber +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSend +MPU_xStreamBufferSend: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSend_Unpriv + MPU_xStreamBufferSend_Priv: + b MPU_xStreamBufferSendImpl + MPU_xStreamBufferSend_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferReceive +MPU_xStreamBufferReceive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferReceive_Unpriv + MPU_xStreamBufferReceive_Priv: + b MPU_xStreamBufferReceiveImpl + MPU_xStreamBufferReceive_Unpriv: + svc #SYSTEM_CALL_xStreamBufferReceive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferIsFull +MPU_xStreamBufferIsFull: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferIsFull_Unpriv + MPU_xStreamBufferIsFull_Priv: + b MPU_xStreamBufferIsFullImpl + MPU_xStreamBufferIsFull_Unpriv: + svc #SYSTEM_CALL_xStreamBufferIsFull +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferIsEmpty +MPU_xStreamBufferIsEmpty: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferIsEmpty_Unpriv + MPU_xStreamBufferIsEmpty_Priv: + b MPU_xStreamBufferIsEmptyImpl + MPU_xStreamBufferIsEmpty_Unpriv: + svc #SYSTEM_CALL_xStreamBufferIsEmpty +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSpacesAvailable +MPU_xStreamBufferSpacesAvailable: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSpacesAvailable_Unpriv + MPU_xStreamBufferSpacesAvailable_Priv: + b MPU_xStreamBufferSpacesAvailableImpl + MPU_xStreamBufferSpacesAvailable_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSpacesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferBytesAvailable +MPU_xStreamBufferBytesAvailable: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferBytesAvailable_Unpriv + MPU_xStreamBufferBytesAvailable_Priv: + b MPU_xStreamBufferBytesAvailableImpl + MPU_xStreamBufferBytesAvailable_Unpriv: + svc #SYSTEM_CALL_xStreamBufferBytesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSetTriggerLevel +MPU_xStreamBufferSetTriggerLevel: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSetTriggerLevel_Unpriv + MPU_xStreamBufferSetTriggerLevel_Priv: + b MPU_xStreamBufferSetTriggerLevelImpl + MPU_xStreamBufferSetTriggerLevel_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferNextMessageLengthBytes +MPU_xStreamBufferNextMessageLengthBytes: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv + MPU_xStreamBufferNextMessageLengthBytes_Priv: + b MPU_xStreamBufferNextMessageLengthBytesImpl + MPU_xStreamBufferNextMessageLengthBytes_Unpriv: + svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes +/*-----------------------------------------------------------*/ + +/* Default weak implementations in case one is not available from + * mpu_wrappers because of config options. */ + + PUBWEAK MPU_xTaskDelayUntilImpl +MPU_xTaskDelayUntilImpl: + b MPU_xTaskDelayUntilImpl + + PUBWEAK MPU_xTaskAbortDelayImpl +MPU_xTaskAbortDelayImpl: + b MPU_xTaskAbortDelayImpl + + PUBWEAK MPU_vTaskDelayImpl +MPU_vTaskDelayImpl: + b MPU_vTaskDelayImpl + + PUBWEAK MPU_uxTaskPriorityGetImpl +MPU_uxTaskPriorityGetImpl: + b MPU_uxTaskPriorityGetImpl + + PUBWEAK MPU_eTaskGetStateImpl +MPU_eTaskGetStateImpl: + b MPU_eTaskGetStateImpl + + PUBWEAK MPU_vTaskGetInfoImpl +MPU_vTaskGetInfoImpl: + b MPU_vTaskGetInfoImpl + + PUBWEAK MPU_xTaskGetIdleTaskHandleImpl +MPU_xTaskGetIdleTaskHandleImpl: + b MPU_xTaskGetIdleTaskHandleImpl + + PUBWEAK MPU_vTaskSuspendImpl +MPU_vTaskSuspendImpl: + b MPU_vTaskSuspendImpl + + PUBWEAK MPU_vTaskResumeImpl +MPU_vTaskResumeImpl: + b MPU_vTaskResumeImpl + + PUBWEAK MPU_xTaskGetTickCountImpl +MPU_xTaskGetTickCountImpl: + b MPU_xTaskGetTickCountImpl + + PUBWEAK MPU_uxTaskGetNumberOfTasksImpl +MPU_uxTaskGetNumberOfTasksImpl: + b MPU_uxTaskGetNumberOfTasksImpl + + PUBWEAK MPU_ulTaskGetRunTimeCounterImpl +MPU_ulTaskGetRunTimeCounterImpl: + b MPU_ulTaskGetRunTimeCounterImpl + + PUBWEAK MPU_ulTaskGetRunTimePercentImpl +MPU_ulTaskGetRunTimePercentImpl: + b MPU_ulTaskGetRunTimePercentImpl + + PUBWEAK MPU_ulTaskGetIdleRunTimePercentImpl +MPU_ulTaskGetIdleRunTimePercentImpl: + b MPU_ulTaskGetIdleRunTimePercentImpl + + PUBWEAK MPU_ulTaskGetIdleRunTimeCounterImpl +MPU_ulTaskGetIdleRunTimeCounterImpl: + b MPU_ulTaskGetIdleRunTimeCounterImpl + + PUBWEAK MPU_vTaskSetApplicationTaskTagImpl +MPU_vTaskSetApplicationTaskTagImpl: + b MPU_vTaskSetApplicationTaskTagImpl + + PUBWEAK MPU_xTaskGetApplicationTaskTagImpl +MPU_xTaskGetApplicationTaskTagImpl: + b MPU_xTaskGetApplicationTaskTagImpl + + PUBWEAK MPU_vTaskSetThreadLocalStoragePointerImpl +MPU_vTaskSetThreadLocalStoragePointerImpl: + b MPU_vTaskSetThreadLocalStoragePointerImpl + + PUBWEAK MPU_pvTaskGetThreadLocalStoragePointerImpl +MPU_pvTaskGetThreadLocalStoragePointerImpl: + b MPU_pvTaskGetThreadLocalStoragePointerImpl + + PUBWEAK MPU_uxTaskGetSystemStateImpl +MPU_uxTaskGetSystemStateImpl: + b MPU_uxTaskGetSystemStateImpl + + PUBWEAK MPU_uxTaskGetStackHighWaterMarkImpl +MPU_uxTaskGetStackHighWaterMarkImpl: + b MPU_uxTaskGetStackHighWaterMarkImpl + + PUBWEAK MPU_uxTaskGetStackHighWaterMark2Impl +MPU_uxTaskGetStackHighWaterMark2Impl: + b MPU_uxTaskGetStackHighWaterMark2Impl + + PUBWEAK MPU_xTaskGetCurrentTaskHandleImpl +MPU_xTaskGetCurrentTaskHandleImpl: + b MPU_xTaskGetCurrentTaskHandleImpl + + PUBWEAK MPU_xTaskGetSchedulerStateImpl +MPU_xTaskGetSchedulerStateImpl: + b MPU_xTaskGetSchedulerStateImpl + + PUBWEAK MPU_vTaskSetTimeOutStateImpl +MPU_vTaskSetTimeOutStateImpl: + b MPU_vTaskSetTimeOutStateImpl + + PUBWEAK MPU_xTaskCheckForTimeOutImpl +MPU_xTaskCheckForTimeOutImpl: + b MPU_xTaskCheckForTimeOutImpl + + PUBWEAK MPU_xTaskGenericNotifyImpl +MPU_xTaskGenericNotifyImpl: + b MPU_xTaskGenericNotifyImpl + + PUBWEAK MPU_xTaskGenericNotifyWaitImpl +MPU_xTaskGenericNotifyWaitImpl: + b MPU_xTaskGenericNotifyWaitImpl + + PUBWEAK MPU_ulTaskGenericNotifyTakeImpl +MPU_ulTaskGenericNotifyTakeImpl: + b MPU_ulTaskGenericNotifyTakeImpl + + PUBWEAK MPU_xTaskGenericNotifyStateClearImpl +MPU_xTaskGenericNotifyStateClearImpl: + b MPU_xTaskGenericNotifyStateClearImpl + + PUBWEAK MPU_ulTaskGenericNotifyValueClearImpl +MPU_ulTaskGenericNotifyValueClearImpl: + b MPU_ulTaskGenericNotifyValueClearImpl + + PUBWEAK MPU_xQueueGenericSendImpl +MPU_xQueueGenericSendImpl: + b MPU_xQueueGenericSendImpl + + PUBWEAK MPU_uxQueueMessagesWaitingImpl +MPU_uxQueueMessagesWaitingImpl: + b MPU_uxQueueMessagesWaitingImpl + + PUBWEAK MPU_uxQueueSpacesAvailableImpl +MPU_uxQueueSpacesAvailableImpl: + b MPU_uxQueueSpacesAvailableImpl + + PUBWEAK MPU_xQueueReceiveImpl +MPU_xQueueReceiveImpl: + b MPU_xQueueReceiveImpl + + PUBWEAK MPU_xQueuePeekImpl +MPU_xQueuePeekImpl: + b MPU_xQueuePeekImpl + + PUBWEAK MPU_xQueueSemaphoreTakeImpl +MPU_xQueueSemaphoreTakeImpl: + b MPU_xQueueSemaphoreTakeImpl + + PUBWEAK MPU_xQueueGetMutexHolderImpl +MPU_xQueueGetMutexHolderImpl: + b MPU_xQueueGetMutexHolderImpl + + PUBWEAK MPU_xQueueTakeMutexRecursiveImpl +MPU_xQueueTakeMutexRecursiveImpl: + b MPU_xQueueTakeMutexRecursiveImpl + + PUBWEAK MPU_xQueueGiveMutexRecursiveImpl +MPU_xQueueGiveMutexRecursiveImpl: + b MPU_xQueueGiveMutexRecursiveImpl + + PUBWEAK MPU_xQueueSelectFromSetImpl +MPU_xQueueSelectFromSetImpl: + b MPU_xQueueSelectFromSetImpl + + PUBWEAK MPU_xQueueAddToSetImpl +MPU_xQueueAddToSetImpl: + b MPU_xQueueAddToSetImpl + + PUBWEAK MPU_vQueueAddToRegistryImpl +MPU_vQueueAddToRegistryImpl: + b MPU_vQueueAddToRegistryImpl + + PUBWEAK MPU_vQueueUnregisterQueueImpl +MPU_vQueueUnregisterQueueImpl: + b MPU_vQueueUnregisterQueueImpl + + PUBWEAK MPU_pcQueueGetNameImpl +MPU_pcQueueGetNameImpl: + b MPU_pcQueueGetNameImpl + + PUBWEAK MPU_pvTimerGetTimerIDImpl +MPU_pvTimerGetTimerIDImpl: + b MPU_pvTimerGetTimerIDImpl + + PUBWEAK MPU_vTimerSetTimerIDImpl +MPU_vTimerSetTimerIDImpl: + b MPU_vTimerSetTimerIDImpl + + PUBWEAK MPU_xTimerIsTimerActiveImpl +MPU_xTimerIsTimerActiveImpl: + b MPU_xTimerIsTimerActiveImpl + + PUBWEAK MPU_xTimerGetTimerDaemonTaskHandleImpl +MPU_xTimerGetTimerDaemonTaskHandleImpl: + b MPU_xTimerGetTimerDaemonTaskHandleImpl + + PUBWEAK MPU_xTimerGenericCommandFromTaskImpl +MPU_xTimerGenericCommandFromTaskImpl: + b MPU_xTimerGenericCommandFromTaskImpl + + PUBWEAK MPU_pcTimerGetNameImpl +MPU_pcTimerGetNameImpl: + b MPU_pcTimerGetNameImpl + + PUBWEAK MPU_vTimerSetReloadModeImpl +MPU_vTimerSetReloadModeImpl: + b MPU_vTimerSetReloadModeImpl + + PUBWEAK MPU_xTimerGetReloadModeImpl +MPU_xTimerGetReloadModeImpl: + b MPU_xTimerGetReloadModeImpl + + PUBWEAK MPU_uxTimerGetReloadModeImpl +MPU_uxTimerGetReloadModeImpl: + b MPU_uxTimerGetReloadModeImpl + + PUBWEAK MPU_xTimerGetPeriodImpl +MPU_xTimerGetPeriodImpl: + b MPU_xTimerGetPeriodImpl + + PUBWEAK MPU_xTimerGetExpiryTimeImpl +MPU_xTimerGetExpiryTimeImpl: + b MPU_xTimerGetExpiryTimeImpl + + PUBWEAK MPU_xEventGroupWaitBitsImpl +MPU_xEventGroupWaitBitsImpl: + b MPU_xEventGroupWaitBitsImpl + + PUBWEAK MPU_xEventGroupClearBitsImpl +MPU_xEventGroupClearBitsImpl: + b MPU_xEventGroupClearBitsImpl + + PUBWEAK MPU_xEventGroupSetBitsImpl +MPU_xEventGroupSetBitsImpl: + b MPU_xEventGroupSetBitsImpl + + PUBWEAK MPU_xEventGroupSyncImpl +MPU_xEventGroupSyncImpl: + b MPU_xEventGroupSyncImpl + + PUBWEAK MPU_uxEventGroupGetNumberImpl +MPU_uxEventGroupGetNumberImpl: + b MPU_uxEventGroupGetNumberImpl + + PUBWEAK MPU_vEventGroupSetNumberImpl +MPU_vEventGroupSetNumberImpl: + b MPU_vEventGroupSetNumberImpl + + PUBWEAK MPU_xStreamBufferSendImpl +MPU_xStreamBufferSendImpl: + b MPU_xStreamBufferSendImpl + + PUBWEAK MPU_xStreamBufferReceiveImpl +MPU_xStreamBufferReceiveImpl: + b MPU_xStreamBufferReceiveImpl + + PUBWEAK MPU_xStreamBufferIsFullImpl +MPU_xStreamBufferIsFullImpl: + b MPU_xStreamBufferIsFullImpl + + PUBWEAK MPU_xStreamBufferIsEmptyImpl +MPU_xStreamBufferIsEmptyImpl: + b MPU_xStreamBufferIsEmptyImpl + + PUBWEAK MPU_xStreamBufferSpacesAvailableImpl +MPU_xStreamBufferSpacesAvailableImpl: + b MPU_xStreamBufferSpacesAvailableImpl + + PUBWEAK MPU_xStreamBufferBytesAvailableImpl +MPU_xStreamBufferBytesAvailableImpl: + b MPU_xStreamBufferBytesAvailableImpl + + PUBWEAK MPU_xStreamBufferSetTriggerLevelImpl +MPU_xStreamBufferSetTriggerLevelImpl: + b MPU_xStreamBufferSetTriggerLevelImpl + + PUBWEAK MPU_xStreamBufferNextMessageLengthBytesImpl +MPU_xStreamBufferNextMessageLengthBytesImpl: + b MPU_xStreamBufferNextMessageLengthBytesImpl + +/*-----------------------------------------------------------*/ + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + END diff --git a/portable/IAR/ARM_CM4F_MPU/port.c b/portable/IAR/ARM_CM4F_MPU/port.c new file mode 100644 index 000000000..720138f08 --- /dev/null +++ b/portable/IAR/ARM_CM4F_MPU/port.c @@ -0,0 +1,1465 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2025 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ARM CM4F MPU port. +*----------------------------------------------------------*/ + +/* IAR includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "mpu_syscall_numbers.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#ifndef __ARMVFP__ + #error This port can only be used when the project options are configured to enable hardware floating point support. +#endif + +#if ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) + #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ +#endif + +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#else + +/* The way the SysTick is clocked is not modified in case it is not the same + * as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 0 ) +#endif + +#ifndef configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS + #warning "configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS is not defined. We recommend defining it to 0 in FreeRTOSConfig.h for better security." + #define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS 1 +#endif + +/* Prototype of all Interrupt Service Routines (ISRs). */ +typedef void ( * portISR_t )( void ); + +/* Constants required to manipulate the core. Registers first... */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) ) +#define portNVIC_SYS_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) +#define portNVIC_MEM_FAULT_ENABLE ( 1UL << 16UL ) + +/* Constants required to access and manipulate the MPU. */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_REGION_BASE_ADDRESS_REG ( *( ( volatile uint32_t * ) 0xe000ed9C ) ) +#define portMPU_REGION_ATTRIBUTE_REG ( *( ( volatile uint32_t * ) 0xe000edA0 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) +#define portMPU_ENABLE ( 0x01UL ) +#define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL ) +#define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL ) +#define portMPU_REGION_VALID ( 0x10UL ) +#define portMPU_REGION_ENABLE ( 0x01UL ) +#define portPERIPHERALS_START_ADDRESS 0x40000000UL +#define portPERIPHERALS_END_ADDRESS 0x5FFFFFFFUL + +/* ...then bits in the registers. */ +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) + +/* Constants used to detect Cortex-M7 r0p0 and r0p1 cores, and ensure + * that a work around is active for errata 837070. */ +#define portCPUID ( *( ( volatile uint32_t * ) 0xE000ed00 ) ) +#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL ) +#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL ) + +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL ) +#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL ) + +/* Constants used to check the installation of the FreeRTOS interrupt handlers. */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xE000ED08 ) ) +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) + +/* Constants required to check the validity of an interrupt priority. */ +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) + +/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */ +#define portVECTACTIVE_MASK ( 0xFFUL ) + +/* Constants required to manipulate the VFP. */ +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */ +#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) +#define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 ) +#define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 ) + +/* Constants used during system call enter and exit. */ +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) + +/* Offsets in the stack to the parameters when inside the SVC handler. */ +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) + +/* The systick is a 24-bit counter. */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/* A fiddle factor to estimate the number of SysTick counts that would have + * occurred while the SysTick counter is stopped during tickless idle + * calculations. */ +#define portMISSED_COUNTS_FACTOR ( 45UL ) + +/* For strict compliance with the Cortex-M spec the task start address should + * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */ +#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL ) + +/* Does addr lie within [start, end] address range? */ +#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \ + ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) ) + +/* Is the access request satisfied by the available permissions? */ +#define portIS_AUTHORIZED( accessRequest, permissions ) \ + ( ( ( permissions ) & ( accessRequest ) ) == accessRequest ) + +/* Max value that fits in a uint32_t type. */ +#define portUINT32_MAX ( ~( ( uint32_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) ) +/*-----------------------------------------------------------*/ + +/* + * Configure a number of standard MPU regions that are used by all tasks. + */ +static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; + +/* + * Return the smallest MPU region size that a given number of bytes will fit + * into. The region size is returned as the value that should be programmed + * into the region attribute register for that region. + */ +static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION; + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ); + +/* + * Exception handlers. + */ +void xPortSysTickHandler( void ) PRIVILEGED_FUNCTION; + +/* + * Start first task is a separate function so it can be tested in isolation. + */ +extern void vPortStartFirstTask( void ) PRIVILEGED_FUNCTION; + +/* + * Turn the VFP on. + */ +extern void vPortEnableVFP( void ); + +/* + * The C portion of the SVC handler. + */ +void vPortSVCHandler_C( uint32_t * pulParam ) PRIVILEGED_FUNCTION; + +/* + * Called from the SVC handler used to start the scheduler. + */ +extern void vPortRestoreContextOfFirstTask( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +#if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) + void vPortEnterCritical( void ) FREERTOS_SYSTEM_CALL; +#else + void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; +#endif + +/** + * @brief Exit from critical section. + */ +#if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) + void vPortExitCritical( void ) FREERTOS_SYSTEM_CALL; +#else + void vPortExitCritical( void ) PRIVILEGED_FUNCTION; +#endif + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + +/** + * @brief Sets up the system call stack so that upon returning from + * SVC, the system call stack is used. + * + * @param pulTaskStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + * @param ucSystemCallNumber The system call number of the system call. + */ + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION; + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + +/** + * @brief Raise SVC for exiting from a system call. + */ + void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + +/** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) PRIVILEGED_FUNCTION; + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ +BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Make a task unprivileged. + */ +void vPortSwitchToUserMode( void ); + +/* + * FreeRTOS handlers implemented in assembly. + */ +extern void vPortSVCHandler( void ) PRIVILEGED_FUNCTION; +extern void xPortPendSVHandler( void ) PRIVILEGED_FUNCTION; +/*-----------------------------------------------------------*/ + +/* Each task maintains its own interrupt status in the critical nesting + * variable. */ +static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + +/* + * This variable is set to pdTRUE when the scheduler is started. + */ + PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE; + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/* + * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( configASSERT_DEFINED == 1 ) + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16; +#endif /* configASSERT_DEFINED */ + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged, + xMPU_SETTINGS * xMPUSettings ) +{ + if( xRunPrivileged == pdTRUE ) + { + xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; + xMPUSettings->ulContext[ 0 ] = portINITIAL_CONTROL_IF_PRIVILEGED; + } + else + { + xMPUSettings->ulTaskFlags &= ( ~( portTASK_IS_PRIVILEGED_FLAG ) ); + xMPUSettings->ulContext[ 0 ] = portINITIAL_CONTROL_IF_UNPRIVILEGED; + } + + xMPUSettings->ulContext[ 1 ] = 0x04040404; /* r4. */ + xMPUSettings->ulContext[ 2 ] = 0x05050505; /* r5. */ + xMPUSettings->ulContext[ 3 ] = 0x06060606; /* r6. */ + xMPUSettings->ulContext[ 4 ] = 0x07070707; /* r7. */ + xMPUSettings->ulContext[ 5 ] = 0x08080808; /* r8. */ + xMPUSettings->ulContext[ 6 ] = 0x09090909; /* r9. */ + xMPUSettings->ulContext[ 7 ] = 0x10101010; /* r10. */ + xMPUSettings->ulContext[ 8 ] = 0x11111111; /* r11. */ + xMPUSettings->ulContext[ 9 ] = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ + + xMPUSettings->ulContext[ 10 ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ + xMPUSettings->ulContext[ 11 ] = ( uint32_t ) pvParameters; /* r0. */ + xMPUSettings->ulContext[ 12 ] = 0x01010101; /* r1. */ + xMPUSettings->ulContext[ 13 ] = 0x02020202; /* r2. */ + xMPUSettings->ulContext[ 14 ] = 0x03030303; /* r3. */ + xMPUSettings->ulContext[ 15 ] = 0x12121212; /* r12. */ + xMPUSettings->ulContext[ 16 ] = 0; /* LR. */ + xMPUSettings->ulContext[ 17 ] = ( ( uint32_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC. */ + xMPUSettings->ulContext[ 18 ] = portINITIAL_XPSR; /* xPSR. */ + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + { + /* Ensure that the system call stack is double word aligned. */ + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + /* This is not NULL only for the duration of a system call. */ + xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL; + } + #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + return &( xMPUSettings->ulContext[ 19 ] ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulParam ) /* PRIVILEGED_FUNCTION */ +{ + uint8_t ucSVCNumber; + uint32_t ulPC; + + #if ( ( configUSE_MPU_WRAPPERS_V1 == 1 ) && ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) ) + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 1 ) && ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) ) */ + + /* The stack contains: r0, r1, r2, r3, r12, LR, PC and xPSR. The first + * argument (r0) is pulParam[ 0 ]. */ + ulPC = pulParam[ portOFFSET_TO_PC ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + case portSVC_START_SCHEDULER: + vPortRestoreContextOfFirstTask(); + break; + + case portSVC_YIELD: + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required + * but do ensure the code is completely + * within the specified behaviour for the + * architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); + + break; + + #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) + #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) + case portSVC_RAISE_PRIVILEGE: /* Only raise the privilege, if the + * svc was raised from any of the + * system calls. */ + + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + __asm volatile + ( + " mrs r1, control \n" /* Obtain current control value. */ + " bic r1, r1, #1 \n" /* Set privilege bit. */ + " msr control, r1 \n" /* Write back new control value. */ + ::: "r1", "memory" + ); + } + + break; + #else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */ + case portSVC_RAISE_PRIVILEGE: + __asm volatile + ( + " mrs r1, control \n" /* Obtain current control value. */ + " bic r1, r1, #1 \n" /* Set privilege bit. */ + " msr control, r1 \n" /* Write back new control value. */ + ::: "r1", "memory" + ); + break; + #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */ + #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + default: /* Unknown SVC call. */ + break; + } +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ]; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulSystemCallStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the system call section (i.e. application is + * not raising SVC directly). + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as + * it is non-NULL only during the execution of a system call (i.e. + * between system call enter and exit). + * 3. System call is not for a kernel API disabled by the configuration + * in FreeRTOSConfig.h. + * 4. We do not need to check that ucSystemCallNumber is within range + * because the assembly SVC handler checks that before calling + * this function. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) && + ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) ) + { + pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + + /* Make space on the system call stack for the stack frame. */ + pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulSystemCallStack[ i ] = pulTaskStack[ i ]; + } + + /* Use the pulSystemCallStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); + + /* Raise the privilege for the duration of the system call. */ + __asm volatile ( + " mrs r1, control \n" /* Obtain current control value. */ + " bic r1, #1 \n" /* Clear nPRIV bit. */ + " msr control, r1 \n" /* Write back new control value. */ + ::: "r1", "memory" + ); + + /* Remember the location where we should copy the stack frame when we exit from + * the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize; + + /* Store the value of the Link Register before the SVC was raised. + * It contains the address of the caller of the System Call entry + * point (i.e. the caller of the MPU_). We need to restore it + * when we exit from the system call. */ + pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; + + + /* Start executing the system call upon returning from this handler. */ + pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; + /* Raise a request to exit from the system call upon finishing the + * system call. */ + pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; + + /* Record if the hardware used padding to force the stack pointer + * to be double word aligned. */ + if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK ) + { + pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG; + } + else + { + pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG ); + } + + /* We ensure in pxPortInitialiseStack that the system call stack is + * double word aligned and therefore, there is no need of padding. + * Clear the bit[9] of stacked xPSR. */ + pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + } + } + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */ + { + __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" ); + } + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulTaskStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the privileged code (i.e. application is not + * raising SVC directly). This SVC is only raised from + * vRequestSystemCallExit which is in the privileged code section. + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL - + * this means that we previously entered a system call and the + * application is not attempting to exit without entering a system + * call. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) ) + { + pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + + /* Make space on the task stack for the stack frame. */ + pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulTaskStack[ i ] = pulSystemCallStack[ i ]; + } + + /* Use the pulTaskStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) ); + + /* Drop the privilege before returning to the thread mode. */ + __asm volatile ( + " mrs r1, control \n" /* Obtain current control value. */ + " orr r1, #1 \n" /* Set nPRIV bit. */ + " msr control, r1 \n" /* Write back new control value. */ + ::: "r1", "memory" + ); + + /* Return to the caller of the System Call entry point (i.e. the + * caller of the MPU_). */ + pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + /* Ensure that LR has a valid value.*/ + pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + + /* If the hardware used padding to force the stack pointer + * to be double word aligned, set the stacked xPSR bit[9], + * otherwise clear it. */ + if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG ) + { + pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK; + } + else + { + pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + } + + /* This is not NULL only for the duration of the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; + } + } + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */ +{ + BaseType_t xTaskIsPrivileged = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xTaskIsPrivileged = pdTRUE; + } + + return xTaskIsPrivileged; +} +/*-----------------------------------------------------------*/ + +void vPortSwitchToUserMode( void ) +{ + /* Load the current task's MPU settings from its TCB. */ + xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); + + /* Mark the task as unprivileged. */ + xTaskMpuSettings->ulTaskFlags &= ( ~( portTASK_IS_PRIVILEGED_FLAG ) ); + + /* Lower the processor's privilege level. */ + vResetPrivilege(); +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + /* Errata 837070 workaround must only be enabled on Cortex-M7 r0p0 + * and r0p1 cores. */ + #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) + configASSERT( ( portCPUID == portCORTEX_M7_r0p1_ID ) || ( portCPUID == portCORTEX_M7_r0p0_ID ) ); + #else + + /* When using this port on a Cortex-M7 r0p0 or r0p1 core, define + * configENABLE_ERRATA_837070_WORKAROUND to 1 in your + * FreeRTOSConfig.h. */ + configASSERT( portCPUID != portCORTEX_M7_r0p1_ID ); + configASSERT( portCPUID != portCORTEX_M7_r0p0_ID ); + #endif + + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions vPortSVCHandler and + * xPortPendSVHandler for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * vPortSVCHandler and xPortPendSVHandler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( configASSERT_DEFINED == 1 ) + { + volatile uint8_t ucOriginalPriority; + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * Save the interrupt priority value that is about to be clobbered. */ + ucOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to all + * possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + + /* Restore the clobbered interrupt priority register to its original + * value. */ + *pucFirstUserPriorityRegister = ucOriginalPriority; + } + #endif /* configASSERT_DEFINED */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + /* Configure the regions in the MPU that are common to all tasks. */ + prvSetupMPU(); + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + { + xSchedulerRunning = pdTRUE; + } + #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + /* Ensure the VFP is enabled - it should be anyway. */ + vPortEnableVFP(); + + /* Lazy save always. */ + *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + #if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ + if( uxCriticalNesting == 1 ) + { + configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); + } + + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ + if( uxCriticalNesting == 1 ) + { + configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); + } + } + #else /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ + if( uxCriticalNesting == 1 ) + { + configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); + } + #endif /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */ +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + #if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + } + #else /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */ + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + #endif /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */ +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + /* The SysTick runs at the lowest interrupt priority, so when this interrupt + * executes all interrupts must be unmasked. There is therefore no need to + * save and then restore the interrupt mask value as its value is already + * known. */ + portDISABLE_INTERRUPTS(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + + /* A context switch is required. Context switching is performed in + * the PendSV interrupt. Pend the PendSV interrupt. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + portENABLE_INTERRUPTS(); +} +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +__weak void vPortSetupTimerInterrupt( void ) +{ + /* Stop and clear the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); +} +/*-----------------------------------------------------------*/ + +static void prvSetupMPU( void ) +{ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __FLASH_segment_start__[]; + extern uint32_t __FLASH_segment_end__[]; + extern uint32_t __privileged_data_start__[]; + extern uint32_t __privileged_data_end__[]; + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */ + configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ); + + /* Check the expected MPU is present. */ + if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ) + { + /* First setup the unprivileged flash for unprivileged read only access. */ + portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */ + ( portMPU_REGION_VALID ) | + ( portUNPRIVILEGED_FLASH_REGION ); + + portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) | + ( ( configTEX_S_C_B_FLASH & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) | + ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) | + ( portMPU_REGION_ENABLE ); + + /* Setup the privileged flash for privileged only access. This is where + * the kernel code is placed. */ + portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_functions_start__ ) | /* Base address. */ + ( portMPU_REGION_VALID ) | + ( portPRIVILEGED_FLASH_REGION ); + + portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) | + ( ( configTEX_S_C_B_FLASH & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) | + ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __privileged_functions_start__ ) ) | + ( portMPU_REGION_ENABLE ); + + /* Setup the privileged data RAM region. This is where the kernel data + * is placed. */ + portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */ + ( portMPU_REGION_VALID ) | + ( portPRIVILEGED_RAM_REGION ); + + portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ) | + ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) | + prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) | + ( portMPU_REGION_ENABLE ); + + /* By default allow everything to access the general peripherals. The + * system peripherals and registers are protected. */ + portMPU_REGION_BASE_ADDRESS_REG = ( portPERIPHERALS_START_ADDRESS ) | + ( portMPU_REGION_VALID ) | + ( portGENERAL_PERIPHERALS_REGION ); + + portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) | + ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) | + ( portMPU_REGION_ENABLE ); + + /* Enable the memory fault exception. */ + portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE; + + /* Enable the MPU with the background region configured. */ + portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE ); + } +} +/*-----------------------------------------------------------*/ + +static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) +{ + uint32_t ulRegionSize, ulReturnValue = 4; + + /* 32 is the smallest region size, 31 is the largest valid value for + * ulReturnValue. */ + for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) ) + { + if( ulActualSizeInBytes <= ulRegionSize ) + { + break; + } + else + { + ulReturnValue++; + } + } + + /* Shift the code by one before returning so it can be written directly + * into the the correct bit position of the attribute register. */ + return( ulReturnValue << 1UL ); +} +/*-----------------------------------------------------------*/ + +void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + configSTACK_DEPTH_TYPE uxStackDepth ) +{ + extern uint32_t __SRAM_segment_start__[]; + extern uint32_t __SRAM_segment_end__[]; + extern uint32_t __privileged_data_start__[]; + extern uint32_t __privileged_data_end__[]; + int32_t lIndex; + uint32_t ul; + + if( xRegions == NULL ) + { + /* No MPU regions are specified so allow access to all RAM. */ + xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress = + ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */ + ( portMPU_REGION_VALID ) | + ( portSTACK_REGION ); /* Region number. */ + + xMPUSettings->xRegion[ 0 ].ulRegionAttribute = + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ) | + ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) | + ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) | + ( portMPU_REGION_ENABLE ); + + xMPUSettings->xRegionSettings[ 0 ].ulRegionStartAddress = ( uint32_t ) __SRAM_segment_start__; + xMPUSettings->xRegionSettings[ 0 ].ulRegionEndAddress = ( uint32_t ) __SRAM_segment_end__; + xMPUSettings->xRegionSettings[ 0 ].ulRegionPermissions = ( tskMPU_READ_PERMISSION | + tskMPU_WRITE_PERMISSION ); + + /* Invalidate user configurable regions. */ + for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ ) + { + xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID ); + xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL; + xMPUSettings->xRegionSettings[ ul ].ulRegionStartAddress = 0UL; + xMPUSettings->xRegionSettings[ ul ].ulRegionEndAddress = 0UL; + xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = 0UL; + } + } + else + { + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that the + * stack region has already been configured. */ + if( uxStackDepth > 0 ) + { + /* Define the region that allows access to the stack. */ + xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress = + ( ( uint32_t ) pxBottomOfStack ) | + ( portMPU_REGION_VALID ) | + ( portSTACK_REGION ); /* Region number. */ + + xMPUSettings->xRegion[ 0 ].ulRegionAttribute = + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ) | + ( prvGetMPURegionSizeSetting( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) ) | + ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) | + ( portMPU_REGION_ENABLE ); + + xMPUSettings->xRegionSettings[ 0 ].ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + xMPUSettings->xRegionSettings[ 0 ].ulRegionEndAddress = ( uint32_t ) ( ( uint32_t ) ( pxBottomOfStack ) + + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1UL ); + xMPUSettings->xRegionSettings[ 0 ].ulRegionPermissions = ( tskMPU_READ_PERMISSION | + tskMPU_WRITE_PERMISSION ); + } + + lIndex = 0; + + for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ ) + { + if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL ) + { + /* Translate the generic region definition contained in + * xRegions into the CM4 specific MPU settings that are then + * stored in xMPUSettings. */ + xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = + ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) | + ( portMPU_REGION_VALID ) | + ( ul - 1UL ); /* Region number. */ + + xMPUSettings->xRegion[ ul ].ulRegionAttribute = + ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) | + ( xRegions[ lIndex ].ulParameters ) | + ( portMPU_REGION_ENABLE ); + + xMPUSettings->xRegionSettings[ ul ].ulRegionStartAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress; + xMPUSettings->xRegionSettings[ ul ].ulRegionEndAddress = ( uint32_t ) ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1UL ); + xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = 0UL; + + if( ( ( xRegions[ lIndex ].ulParameters & portMPU_REGION_READ_ONLY ) == portMPU_REGION_READ_ONLY ) || + ( ( xRegions[ lIndex ].ulParameters & portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ) == portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ) ) + { + xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = tskMPU_READ_PERMISSION; + } + + if( ( xRegions[ lIndex ].ulParameters & portMPU_REGION_READ_WRITE ) == portMPU_REGION_READ_WRITE ) + { + xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION ); + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID ); + xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL; + xMPUSettings->xRegionSettings[ ul ].ulRegionStartAddress = 0UL; + xMPUSettings->xRegionSettings[ ul ].ulRegionEndAddress = 0UL; + xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = 0UL; + } + + lIndex++; + } + } +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, + uint32_t ulBufferLength, + uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */ + + { + uint32_t i, ulBufferStartAddress, ulBufferEndAddress; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE ) + { + ulBufferStartAddress = ( uint32_t ) pvBuffer; + ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL ); + + for( i = 0; i < portTOTAL_NUM_REGIONS_IN_TCB; i++ ) + { + if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress, + xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress, + xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) && + portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress, + xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress, + xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) && + portIS_AUTHORIZED( ulAccessRequested, xTaskMpuSettings->xRegionSettings[ i ].ulRegionPermissions ) ) + { + xAccessGranted = pdTRUE; + break; + } + } + } + } + + return xAccessGranted; + } + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + + +#if ( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* configASSERT_DEFINED */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings; + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else + { + xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 ) + { + xAccessGranted = pdTRUE; + } + } + } + + return xAccessGranted; + } + + #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + ( void ) lInternalIndexOfKernelObject; + + /* If Access Control List feature is not used, all the tasks have + * access to all the kernel objects. */ + return pdTRUE; + } + + #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/ARM_CM4F_MPU/portasm.s b/portable/IAR/ARM_CM4F_MPU/portasm.s new file mode 100644 index 000000000..9ce0e14d8 --- /dev/null +++ b/portable/IAR/ARM_CM4F_MPU/portasm.s @@ -0,0 +1,306 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include +#include + + RSEG CODE:CODE(2) + thumb + + EXTERN pxCurrentTCB + EXTERN vTaskSwitchContext + EXTERN vPortSVCHandler_C + EXTERN vSystemCallEnter + EXTERN vSystemCallExit + + PUBLIC xPortPendSVHandler + PUBLIC vPortSVCHandler + PUBLIC vPortStartFirstTask + PUBLIC vPortEnableVFP + PUBLIC vPortRestoreContextOfFirstTask + PUBLIC xIsPrivileged + PUBLIC vResetPrivilege + +/*-----------------------------------------------------------*/ + +#ifndef configUSE_MPU_WRAPPERS_V1 + #define configUSE_MPU_WRAPPERS_V1 0 +#endif + +/* Errata 837070 workaround must be enabled on Cortex-M7 r0p0 + * and r0p1 cores. */ +#ifndef configENABLE_ERRATA_837070_WORKAROUND + #define configENABLE_ERRATA_837070_WORKAROUND 0 +#endif + +/* These must be in sync with portmacro.h. */ +#define portSVC_START_SCHEDULER 100 +#define portSVC_SYSTEM_CALL_EXIT 103 +/*-----------------------------------------------------------*/ + +xPortPendSVHandler: + + ldr r3, =pxCurrentTCB + ldr r2, [r3] /* r2 = pxCurrentTCB. */ + ldr r1, [r2] /* r1 = Location where the context should be saved. */ + + /*------------ Save Context. ----------- */ + mrs r3, control + mrs r0, psp + isb + + add r0, r0, #0x20 /* Move r0 to location where s0 is saved. */ + tst lr, #0x10 + ittt eq + vstmiaeq r1!, {s16-s31} /* Store s16-s31. */ + vldmiaeq r0, {s0-s16} /* Copy hardware saved FP context into s0-s16. */ + vstmiaeq r1!, {s0-s16} /* Store hardware saved FP context. */ + sub r0, r0, #0x20 /* Set r0 back to the location of hardware saved context. */ + + stmia r1!, {r3-r11, lr} /* Store CONTROL register, r4-r11 and LR. */ + ldmia r0, {r4-r11} /* Copy hardware saved context into r4-r11. */ + stmia r1!, {r0, r4-r11} /* Store original PSP (after hardware has saved context) and the hardware saved context. */ + str r1, [r2] /* Save the location from where the context should be restored as the first member of TCB. */ + + /*---------- Select next task. --------- */ + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY +#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) + cpsid i /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */ +#endif + msr basepri, r0 + dsb + isb +#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) + cpsie i /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */ +#endif + bl vTaskSwitchContext + mov r0, #0 + msr basepri, r0 + + /*------------ Program MPU. ------------ */ + ldr r3, =pxCurrentTCB + ldr r2, [r3] /* r2 = pxCurrentTCB. */ + add r2, r2, #4 /* r2 = Second item in the TCB which is xMPUSettings. */ + + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r0, =0xe000ed94 /* MPU_CTRL register. */ + ldr r3, [r0] /* Read the value of MPU_CTRL. */ + bic r3, #1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */ + str r3, [r0] /* Disable MPU. */ + + ldr r0, =0xe000ed9c /* Region Base Address register. */ + ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */ + stmia r0, {r4-r11} /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */ + +#ifdef configTOTAL_MPU_REGIONS + #if ( configTOTAL_MPU_REGIONS == 16 ) + ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */ + stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 4 - 7]. */ + ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */ + stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */ + #endif /* configTOTAL_MPU_REGIONS == 16. */ +#endif + + ldr r0, =0xe000ed94 /* MPU_CTRL register. */ + ldr r3, [r0] /* Read the value of MPU_CTRL. */ + orr r3, #1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */ + str r3, [r0] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + + /*---------- Restore Context. ---------- */ + ldr r3, =pxCurrentTCB + ldr r2, [r3] /* r2 = pxCurrentTCB. */ + ldr r1, [r2] /* r1 = Location of saved context in TCB. */ + + ldmdb r1!, {r0, r4-r11} /* r0 contains PSP after the hardware had saved context. r4-r11 contain hardware saved context. */ + msr psp, r0 + stmia r0!, {r4-r11} /* Copy the hardware saved context on the task stack. */ + ldmdb r1!, {r3-r11, lr} /* r3 contains CONTROL register. r4-r11 and LR restored. */ + msr control, r3 + + tst lr, #0x10 + ittt eq + vldmdbeq r1!, {s0-s16} /* s0-s16 contain hardware saved FP context. */ + vstmiaeq r0!, {s0-s16} /* Copy hardware saved FP context on the task stack. */ + vldmdbeq r1!, {s16-s31} /* Restore s16-s31. */ + + str r1, [r2] /* Save the location where the context should be saved next as the first member of TCB. */ + bx lr + +/*-----------------------------------------------------------*/ + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + +vPortSVCHandler: + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + + ldr r1, [r0, #24] + ldrb r2, [r1, #-2] + cmp r2, #NUM_SYSTEM_CALLS + blt syscall_enter + cmp r2, #portSVC_SYSTEM_CALL_EXIT + beq syscall_exit + b vPortSVCHandler_C + + syscall_enter: + mov r1, lr + b vSystemCallEnter + + syscall_exit: + mov r1, lr + b vSystemCallExit + +#else /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +vPortSVCHandler: + #ifndef USE_PROCESS_STACK + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + #else + mrs r0, psp + #endif + b vPortSVCHandler_C + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +vPortStartFirstTask: + /* Use the NVIC offset register to locate the stack. */ + ldr r0, =0xE000ED08 + ldr r0, [r0] + ldr r0, [r0] + /* Set the msp back to the start of the stack. */ + msr msp, r0 + /* Clear the bit that indicates the FPU is in use in case the FPU was used + before the scheduler was started - which would otherwise result in the + unnecessary leaving of space in the SVC stack for lazy saving of FPU + registers. */ + mov r0, #0 + msr control, r0 + /* Call SVC to start the first task. */ + cpsie i + cpsie f + dsb + isb + svc #portSVC_START_SCHEDULER + +/*-----------------------------------------------------------*/ + +vPortRestoreContextOfFirstTask: + ldr r0, =0xE000ED08 /* Use the NVIC offset register to locate the stack. */ + ldr r0, [r0] + ldr r0, [r0] + msr msp, r0 /* Set the msp back to the start of the stack. */ + + /*------------ Program MPU. ------------ */ + ldr r3, =pxCurrentTCB + ldr r2, [r3] /* r2 = pxCurrentTCB. */ + add r2, r2, #4 /* r2 = Second item in the TCB which is xMPUSettings. */ + + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r0, =0xe000ed94 /* MPU_CTRL register. */ + ldr r3, [r0] /* Read the value of MPU_CTRL. */ + bic r3, #1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */ + str r3, [r0] /* Disable MPU. */ + + ldr r0, =0xe000ed9c /* Region Base Address register. */ + ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */ + stmia r0, {r4-r11} /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */ + +#ifdef configTOTAL_MPU_REGIONS + #if ( configTOTAL_MPU_REGIONS == 16 ) + ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */ + stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 4 - 7]. */ + ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */ + stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */ + #endif /* configTOTAL_MPU_REGIONS == 16. */ +#endif + + ldr r0, =0xe000ed94 /* MPU_CTRL register. */ + ldr r3, [r0] /* Read the value of MPU_CTRL. */ + orr r3, #1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */ + str r3, [r0] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + + /*---------- Restore Context. ---------- */ + ldr r3, =pxCurrentTCB + ldr r2, [r3] /* r2 = pxCurrentTCB. */ + ldr r1, [r2] /* r1 = Location of saved context in TCB. */ + + ldmdb r1!, {r0, r4-r11} /* r0 contains PSP after the hardware had saved context. r4-r11 contain hardware saved context. */ + msr psp, r0 + stmia r0, {r4-r11} /* Copy the hardware saved context on the task stack. */ + ldmdb r1!, {r3-r11, lr} /* r3 contains CONTROL register. r4-r11 and LR restored. */ + msr control, r3 + str r1, [r2] /* Save the location where the context should be saved next as the first member of TCB. */ + + mov r0, #0 + msr basepri, r0 + bx lr + +/*-----------------------------------------------------------*/ + +vPortEnableVFP: + /* The FPU enable bits are in the CPACR. */ + ldr.w r0, =0xE000ED88 + ldr r1, [r0] + + /* Enable CP10 and CP11 coprocessors, then save back. */ + orr r1, r1, #( 0xf << 20 ) + str r1, [r0] + bx r14 + +/*-----------------------------------------------------------*/ + +xIsPrivileged: + mrs r0, control /* r0 = CONTROL. */ + tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + ite ne + movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vResetPrivilege: + mrs r0, control /* r0 = CONTROL. */ + orr r0, r0, #1 /* r0 = r0 | 1. */ + msr control, r0 /* CONTROL = r0. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + + END diff --git a/portable/IAR/ARM_CM4F_MPU/portmacro.h b/portable/IAR/ARM_CM4F_MPU/portmacro.h new file mode 100644 index 000000000..6b7600c15 --- /dev/null +++ b/portable/IAR/ARM_CM4F_MPU/portmacro.h @@ -0,0 +1,457 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* IAR includes. */ +#include + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error "configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width." +#endif + +/* Errata 837070 workaround must be enabled on Cortex-M7 r0p0 + * and r0p1 cores. */ +#ifndef configENABLE_ERRATA_837070_WORKAROUND + #define configENABLE_ERRATA_837070_WORKAROUND 0 +#endif +/*-----------------------------------------------------------*/ + +/* MPU specific constants. */ +#define portUSING_MPU_WRAPPERS 1 +#define portPRIVILEGE_BIT ( 0x80000000UL ) + +#define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL ) +#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL ) +#define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL ) +#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL ) +#define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ( 0x02UL << 24UL ) +#define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL ) +#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL ) + +/* Location of the TEX,S,C,B bits in the MPU Region Attribute and Size + * Register (RASR). */ +#define portMPU_RASR_TEX_S_C_B_LOCATION ( 16UL ) +#define portMPU_RASR_TEX_S_C_B_MASK ( 0x3FUL ) + +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* + * The TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits define the + * memory type, and where necessary the cacheable and shareable properties + * of the memory region. + * + * The TEX, C, and B bits together indicate the memory type of the region, + * and: + * - For Normal memory, the cacheable properties of the region. + * - For Device memory, whether the region is shareable. + * + * For Normal memory regions, the S bit indicates whether the region is + * shareable. For Strongly-ordered and Device memory, the S bit is ignored. + * + * See the following two tables for setting TEX, S, C and B bits for + * unprivileged flash, privileged flash and privileged RAM regions. + * + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | TEX | C | B | Memory type | Description or Normal region cacheability | Shareable? | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 000 | 0 | 0 | Strongly-ordered | Strongly ordered | Shareable | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 000 | 0 | 1 | Device | Shared device | Shareable | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 000 | 1 | 0 | Normal | Outer and inner write-through; no write allocate | S bit | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 000 | 1 | 1 | Normal | Outer and inner write-back; no write allocate | S bit | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 001 | 0 | 0 | Normal | Outer and inner Non-cacheable | S bit | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 001 | 0 | 1 | Reserved | Reserved | Reserved | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 001 | 1 | 0 | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 001 | 1 | 1 | Normal | Outer and inner write-back; write and read allocate | S bit | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 010 | 0 | 0 | Device | Non-shared device | Not shareable | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 010 | 0 | 1 | Reserved | Reserved | Reserved | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 010 | 1 | X | Reserved | Reserved | Reserved | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 011 | X | X | Reserved | Reserved | Reserved | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 1BB | A | A | Normal | Cached memory, with AA and BB indicating the inner and | Reserved | + | | | | | outer cacheability rules that must be exported on the | | + | | | | | bus. See the table below for the cacheability policy | | + | | | | | encoding. memory, BB=Outer policy, AA=Inner policy. | | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | + +-----------------------------------------+----------------------------------------+ + | AA or BB subfield of {TEX,C,B} encoding | Cacheability policy | + +-----------------------------------------+----------------------------------------+ + | 00 | Non-cacheable | + +-----------------------------------------+----------------------------------------+ + | 01 | Write-back, write and read allocate | + +-----------------------------------------+----------------------------------------+ + | 10 | Write-through, no write allocate | + +-----------------------------------------+----------------------------------------+ + | 11 | Write-back, no write allocate | + +-----------------------------------------+----------------------------------------+ + */ + +/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for flash + * region. */ +#ifndef configTEX_S_C_B_FLASH + /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */ + #define configTEX_S_C_B_FLASH ( 0x07UL ) +#endif + +/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for RAM + * region. */ +#ifndef configTEX_S_C_B_SRAM + /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */ + #define configTEX_S_C_B_SRAM ( 0x07UL ) +#endif + +#define portSTACK_REGION ( configTOTAL_MPU_REGIONS - 5UL ) +#define portGENERAL_PERIPHERALS_REGION ( configTOTAL_MPU_REGIONS - 4UL ) +#define portUNPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 3UL ) +#define portPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 2UL ) +#define portPRIVILEGED_RAM_REGION ( configTOTAL_MPU_REGIONS - 1UL ) +#define portFIRST_CONFIGURABLE_REGION ( 0UL ) +#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 6UL ) +#define portNUM_CONFIGURABLE_REGIONS ( configTOTAL_MPU_REGIONS - 5UL ) +#define portTOTAL_NUM_REGIONS_IN_TCB ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus 1 to create space for the stack region. */ + +typedef struct MPU_REGION_REGISTERS +{ + uint32_t ulRegionBaseAddress; + uint32_t ulRegionAttribute; +} xMPU_REGION_REGISTERS; + +typedef struct MPU_REGION_SETTINGS +{ + uint32_t ulRegionStartAddress; + uint32_t ulRegionEndAddress; + uint32_t ulRegionPermissions; +} xMPU_REGION_SETTINGS; + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + #ifndef configSYSTEM_CALL_STACK_SIZE + #error "configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2." + #endif + + typedef struct SYSTEM_CALL_STACK_INFO + { + uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; + uint32_t * pulSystemCallStack; + uint32_t * pulTaskStack; + uint32_t ulLinkRegisterAtSystemCallEntry; + } xSYSTEM_CALL_STACK_INFO; + +#endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + +/* + * +---------+---------------+-----------------+-----------------+-----+ + * | s16-s31 | s0-s15, FPSCR | CONTROL, r4-r11 | PSP, r0-r3, r12 | | + * | | | EXC_RETURN | LR, PC, xPSR | | + * +---------+---------------+-----------------+-----------------+-----+ + * + * <--------><---------------><----------------><----------------><----> + * 16 17 10 9 1 + */ +#define MAX_CONTEXT_SIZE ( 53 ) + +/* Size of an Access Control List (ACL) entry in bits. */ +#define portACL_ENTRY_SIZE_BITS ( 32U ) + +/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ +#define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) +#define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) + +typedef struct MPU_SETTINGS +{ + xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS_IN_TCB ]; + xMPU_REGION_SETTINGS xRegionSettings[ portTOTAL_NUM_REGIONS_IN_TCB ]; + uint32_t ulContext[ MAX_CONTEXT_SIZE ]; + uint32_t ulTaskFlags; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo; + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ]; + #endif + #endif +} xMPU_SETTINGS; + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +/*-----------------------------------------------------------*/ + +/* SVC numbers for various services. */ +#define portSVC_START_SCHEDULER 100 +#define portSVC_YIELD 101 +#define portSVC_RAISE_PRIVILEGE 102 +#define portSVC_SYSTEM_CALL_EXIT 103 + +/* Scheduler utilities. */ + +#define portYIELD() __asm volatile ( " SVC %0 \n" ::"i" ( portSVC_YIELD ) : "memory" ) +#define portYIELD_WITHIN_API() \ + { \ + /* Set a PendSV to request a context switch. */ \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + __DSB(); \ + __ISB(); \ + } + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portYIELD_WITHIN_API(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/* Architecture specific optimisations. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice." + #endif + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) + #define portDISABLE_INTERRUPTS() \ + { \ + __disable_interrupt(); \ + __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \ + __DSB(); \ + __ISB(); \ + __enable_interrupt(); \ + } +#else + #define portDISABLE_INTERRUPTS() \ + { \ + __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \ + __DSB(); \ + __ISB(); \ + } +#endif /* if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) */ + +#define portENABLE_INTERRUPTS() __set_BASEPRI( 0 ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +#define portSET_INTERRUPT_MASK_FROM_ISR() __get_BASEPRI(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) __set_BASEPRI( x ) +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not necessary for to use this port. They are defined so the common demo files + * (which build with all the ports) will build. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif + +/* portNOP() is not required by this port. */ +#define portNOP() + +#define portINLINE __inline + +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif + +/*-----------------------------------------------------------*/ + +portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} + + +/*-----------------------------------------------------------*/ + +extern BaseType_t xIsPrivileged( void ); +extern void vResetPrivilege( void ); +extern void vPortSwitchToUserMode( void ); + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +#define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + */ +#define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ +#define portRESET_PRIVILEGE() vResetPrivilege() + +/** + * @brief Make a task unprivileged. + * + * It must be called from privileged tasks only. Calling it from unprivileged + * task will result in a memory protection fault. + */ +#define portSWITCH_TO_USER_MODE() vPortSwitchToUserMode() +/*-----------------------------------------------------------*/ + +extern BaseType_t xPortIsTaskPrivileged( void ); + +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ +#define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() +/*-----------------------------------------------------------*/ + +#ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY + #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. www.FreeRTOS.org/FreeRTOS-V10.3.x.html" + #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0 +#endif +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ +#pragma diag_suppress=Pe191 +#pragma diag_suppress=Pa082 +#pragma diag_suppress=Be006 +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/IAR/ARM_CM52/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM52/non_secure/mpu_wrappers_v2_asm.S new file mode 100644 index 000000000..d2cb78e92 --- /dev/null +++ b/portable/IAR/ARM_CM52/non_secure/mpu_wrappers_v2_asm.S @@ -0,0 +1,1242 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + + SECTION freertos_system_calls:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +#include "FreeRTOSConfig.h" +#include "mpu_syscall_numbers.h" + +#ifndef configUSE_MPU_WRAPPERS_V1 + #define configUSE_MPU_WRAPPERS_V1 0 +#endif + +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + PUBLIC MPU_xTaskDelayUntil +MPU_xTaskDelayUntil: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskDelayUntil_Unpriv + MPU_xTaskDelayUntil_Priv: + b MPU_xTaskDelayUntilImpl + MPU_xTaskDelayUntil_Unpriv: + svc #SYSTEM_CALL_xTaskDelayUntil +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskAbortDelay +MPU_xTaskAbortDelay: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskAbortDelay_Unpriv + MPU_xTaskAbortDelay_Priv: + b MPU_xTaskAbortDelayImpl + MPU_xTaskAbortDelay_Unpriv: + svc #SYSTEM_CALL_xTaskAbortDelay +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskDelay +MPU_vTaskDelay: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskDelay_Unpriv + MPU_vTaskDelay_Priv: + b MPU_vTaskDelayImpl + MPU_vTaskDelay_Unpriv: + svc #SYSTEM_CALL_vTaskDelay +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskPriorityGet +MPU_uxTaskPriorityGet: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskPriorityGet_Unpriv + MPU_uxTaskPriorityGet_Priv: + b MPU_uxTaskPriorityGetImpl + MPU_uxTaskPriorityGet_Unpriv: + svc #SYSTEM_CALL_uxTaskPriorityGet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_eTaskGetState +MPU_eTaskGetState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_eTaskGetState_Unpriv + MPU_eTaskGetState_Priv: + b MPU_eTaskGetStateImpl + MPU_eTaskGetState_Unpriv: + svc #SYSTEM_CALL_eTaskGetState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskGetInfo +MPU_vTaskGetInfo: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskGetInfo_Unpriv + MPU_vTaskGetInfo_Priv: + b MPU_vTaskGetInfoImpl + MPU_vTaskGetInfo_Unpriv: + svc #SYSTEM_CALL_vTaskGetInfo +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetIdleTaskHandle +MPU_xTaskGetIdleTaskHandle: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetIdleTaskHandle_Unpriv + MPU_xTaskGetIdleTaskHandle_Priv: + b MPU_xTaskGetIdleTaskHandleImpl + MPU_xTaskGetIdleTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTaskGetIdleTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSuspend +MPU_vTaskSuspend: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSuspend_Unpriv + MPU_vTaskSuspend_Priv: + b MPU_vTaskSuspendImpl + MPU_vTaskSuspend_Unpriv: + svc #SYSTEM_CALL_vTaskSuspend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskResume +MPU_vTaskResume: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskResume_Unpriv + MPU_vTaskResume_Priv: + b MPU_vTaskResumeImpl + MPU_vTaskResume_Unpriv: + svc #SYSTEM_CALL_vTaskResume +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetTickCount +MPU_xTaskGetTickCount: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetTickCount_Unpriv + MPU_xTaskGetTickCount_Priv: + b MPU_xTaskGetTickCountImpl + MPU_xTaskGetTickCount_Unpriv: + svc #SYSTEM_CALL_xTaskGetTickCount +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetNumberOfTasks +MPU_uxTaskGetNumberOfTasks: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetNumberOfTasks_Unpriv + MPU_uxTaskGetNumberOfTasks_Priv: + b MPU_uxTaskGetNumberOfTasksImpl + MPU_uxTaskGetNumberOfTasks_Unpriv: + svc #SYSTEM_CALL_uxTaskGetNumberOfTasks +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetRunTimeCounter +MPU_ulTaskGetRunTimeCounter: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetRunTimeCounter_Unpriv + MPU_ulTaskGetRunTimeCounter_Priv: + b MPU_ulTaskGetRunTimeCounterImpl + MPU_ulTaskGetRunTimeCounter_Unpriv: + svc #SYSTEM_CALL_ulTaskGetRunTimeCounter +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetRunTimePercent +MPU_ulTaskGetRunTimePercent: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetRunTimePercent_Unpriv + MPU_ulTaskGetRunTimePercent_Priv: + b MPU_ulTaskGetRunTimePercentImpl + MPU_ulTaskGetRunTimePercent_Unpriv: + svc #SYSTEM_CALL_ulTaskGetRunTimePercent +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetIdleRunTimePercent +MPU_ulTaskGetIdleRunTimePercent: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetIdleRunTimePercent_Unpriv + MPU_ulTaskGetIdleRunTimePercent_Priv: + b MPU_ulTaskGetIdleRunTimePercentImpl + MPU_ulTaskGetIdleRunTimePercent_Unpriv: + svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetIdleRunTimeCounter +MPU_ulTaskGetIdleRunTimeCounter: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv + MPU_ulTaskGetIdleRunTimeCounter_Priv: + b MPU_ulTaskGetIdleRunTimeCounterImpl + MPU_ulTaskGetIdleRunTimeCounter_Unpriv: + svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetApplicationTaskTag +MPU_vTaskSetApplicationTaskTag: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetApplicationTaskTag_Unpriv + MPU_vTaskSetApplicationTaskTag_Priv: + b MPU_vTaskSetApplicationTaskTagImpl + MPU_vTaskSetApplicationTaskTag_Unpriv: + svc #SYSTEM_CALL_vTaskSetApplicationTaskTag +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetApplicationTaskTag +MPU_xTaskGetApplicationTaskTag: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetApplicationTaskTag_Unpriv + MPU_xTaskGetApplicationTaskTag_Priv: + b MPU_xTaskGetApplicationTaskTagImpl + MPU_xTaskGetApplicationTaskTag_Unpriv: + svc #SYSTEM_CALL_xTaskGetApplicationTaskTag +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetThreadLocalStoragePointer +MPU_vTaskSetThreadLocalStoragePointer: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv + MPU_vTaskSetThreadLocalStoragePointer_Priv: + b MPU_vTaskSetThreadLocalStoragePointerImpl + MPU_vTaskSetThreadLocalStoragePointer_Unpriv: + svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pvTaskGetThreadLocalStoragePointer +MPU_pvTaskGetThreadLocalStoragePointer: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv + MPU_pvTaskGetThreadLocalStoragePointer_Priv: + b MPU_pvTaskGetThreadLocalStoragePointerImpl + MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: + svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetSystemState +MPU_uxTaskGetSystemState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetSystemState_Unpriv + MPU_uxTaskGetSystemState_Priv: + b MPU_uxTaskGetSystemStateImpl + MPU_uxTaskGetSystemState_Unpriv: + svc #SYSTEM_CALL_uxTaskGetSystemState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetStackHighWaterMark +MPU_uxTaskGetStackHighWaterMark: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetStackHighWaterMark_Unpriv + MPU_uxTaskGetStackHighWaterMark_Priv: + b MPU_uxTaskGetStackHighWaterMarkImpl + MPU_uxTaskGetStackHighWaterMark_Unpriv: + svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetStackHighWaterMark2 +MPU_uxTaskGetStackHighWaterMark2: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetStackHighWaterMark2_Unpriv + MPU_uxTaskGetStackHighWaterMark2_Priv: + b MPU_uxTaskGetStackHighWaterMark2Impl + MPU_uxTaskGetStackHighWaterMark2_Unpriv: + svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2 +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetCurrentTaskHandle +MPU_xTaskGetCurrentTaskHandle: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetCurrentTaskHandle_Unpriv + MPU_xTaskGetCurrentTaskHandle_Priv: + b MPU_xTaskGetCurrentTaskHandleImpl + MPU_xTaskGetCurrentTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetSchedulerState +MPU_xTaskGetSchedulerState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetSchedulerState_Unpriv + MPU_xTaskGetSchedulerState_Priv: + b MPU_xTaskGetSchedulerStateImpl + MPU_xTaskGetSchedulerState_Unpriv: + svc #SYSTEM_CALL_xTaskGetSchedulerState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetTimeOutState +MPU_vTaskSetTimeOutState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetTimeOutState_Unpriv + MPU_vTaskSetTimeOutState_Priv: + b MPU_vTaskSetTimeOutStateImpl + MPU_vTaskSetTimeOutState_Unpriv: + svc #SYSTEM_CALL_vTaskSetTimeOutState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskCheckForTimeOut +MPU_xTaskCheckForTimeOut: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskCheckForTimeOut_Unpriv + MPU_xTaskCheckForTimeOut_Priv: + b MPU_xTaskCheckForTimeOutImpl + MPU_xTaskCheckForTimeOut_Unpriv: + svc #SYSTEM_CALL_xTaskCheckForTimeOut +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyEntry +MPU_xTaskGenericNotifyEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotify_Unpriv + MPU_xTaskGenericNotify_Priv: + b MPU_xTaskGenericNotifyImpl + MPU_xTaskGenericNotify_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotify +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyWaitEntry +MPU_xTaskGenericNotifyWaitEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotifyWait_Unpriv + MPU_xTaskGenericNotifyWait_Priv: + b MPU_xTaskGenericNotifyWaitImpl + MPU_xTaskGenericNotifyWait_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotifyWait +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGenericNotifyTake +MPU_ulTaskGenericNotifyTake: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGenericNotifyTake_Unpriv + MPU_ulTaskGenericNotifyTake_Priv: + b MPU_ulTaskGenericNotifyTakeImpl + MPU_ulTaskGenericNotifyTake_Unpriv: + svc #SYSTEM_CALL_ulTaskGenericNotifyTake +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyStateClear +MPU_xTaskGenericNotifyStateClear: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotifyStateClear_Unpriv + MPU_xTaskGenericNotifyStateClear_Priv: + b MPU_xTaskGenericNotifyStateClearImpl + MPU_xTaskGenericNotifyStateClear_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotifyStateClear +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGenericNotifyValueClear +MPU_ulTaskGenericNotifyValueClear: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGenericNotifyValueClear_Unpriv + MPU_ulTaskGenericNotifyValueClear_Priv: + b MPU_ulTaskGenericNotifyValueClearImpl + MPU_ulTaskGenericNotifyValueClear_Unpriv: + svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGenericSend +MPU_xQueueGenericSend: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGenericSend_Unpriv + MPU_xQueueGenericSend_Priv: + b MPU_xQueueGenericSendImpl + MPU_xQueueGenericSend_Unpriv: + svc #SYSTEM_CALL_xQueueGenericSend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxQueueMessagesWaiting +MPU_uxQueueMessagesWaiting: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxQueueMessagesWaiting_Unpriv + MPU_uxQueueMessagesWaiting_Priv: + b MPU_uxQueueMessagesWaitingImpl + MPU_uxQueueMessagesWaiting_Unpriv: + svc #SYSTEM_CALL_uxQueueMessagesWaiting +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxQueueSpacesAvailable +MPU_uxQueueSpacesAvailable: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxQueueSpacesAvailable_Unpriv + MPU_uxQueueSpacesAvailable_Priv: + b MPU_uxQueueSpacesAvailableImpl + MPU_uxQueueSpacesAvailable_Unpriv: + svc #SYSTEM_CALL_uxQueueSpacesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueReceive +MPU_xQueueReceive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueReceive_Unpriv + MPU_xQueueReceive_Priv: + b MPU_xQueueReceiveImpl + MPU_xQueueReceive_Unpriv: + svc #SYSTEM_CALL_xQueueReceive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueuePeek +MPU_xQueuePeek: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueuePeek_Unpriv + MPU_xQueuePeek_Priv: + b MPU_xQueuePeekImpl + MPU_xQueuePeek_Unpriv: + svc #SYSTEM_CALL_xQueuePeek +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueSemaphoreTake +MPU_xQueueSemaphoreTake: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueSemaphoreTake_Unpriv + MPU_xQueueSemaphoreTake_Priv: + b MPU_xQueueSemaphoreTakeImpl + MPU_xQueueSemaphoreTake_Unpriv: + svc #SYSTEM_CALL_xQueueSemaphoreTake +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGetMutexHolder +MPU_xQueueGetMutexHolder: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGetMutexHolder_Unpriv + MPU_xQueueGetMutexHolder_Priv: + b MPU_xQueueGetMutexHolderImpl + MPU_xQueueGetMutexHolder_Unpriv: + svc #SYSTEM_CALL_xQueueGetMutexHolder +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueTakeMutexRecursive +MPU_xQueueTakeMutexRecursive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueTakeMutexRecursive_Unpriv + MPU_xQueueTakeMutexRecursive_Priv: + b MPU_xQueueTakeMutexRecursiveImpl + MPU_xQueueTakeMutexRecursive_Unpriv: + svc #SYSTEM_CALL_xQueueTakeMutexRecursive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGiveMutexRecursive +MPU_xQueueGiveMutexRecursive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGiveMutexRecursive_Unpriv + MPU_xQueueGiveMutexRecursive_Priv: + b MPU_xQueueGiveMutexRecursiveImpl + MPU_xQueueGiveMutexRecursive_Unpriv: + svc #SYSTEM_CALL_xQueueGiveMutexRecursive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueSelectFromSet +MPU_xQueueSelectFromSet: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueSelectFromSet_Unpriv + MPU_xQueueSelectFromSet_Priv: + b MPU_xQueueSelectFromSetImpl + MPU_xQueueSelectFromSet_Unpriv: + svc #SYSTEM_CALL_xQueueSelectFromSet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueAddToSet +MPU_xQueueAddToSet: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueAddToSet_Unpriv + MPU_xQueueAddToSet_Priv: + b MPU_xQueueAddToSetImpl + MPU_xQueueAddToSet_Unpriv: + svc #SYSTEM_CALL_xQueueAddToSet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vQueueAddToRegistry +MPU_vQueueAddToRegistry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vQueueAddToRegistry_Unpriv + MPU_vQueueAddToRegistry_Priv: + b MPU_vQueueAddToRegistryImpl + MPU_vQueueAddToRegistry_Unpriv: + svc #SYSTEM_CALL_vQueueAddToRegistry +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vQueueUnregisterQueue +MPU_vQueueUnregisterQueue: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vQueueUnregisterQueue_Unpriv + MPU_vQueueUnregisterQueue_Priv: + b MPU_vQueueUnregisterQueueImpl + MPU_vQueueUnregisterQueue_Unpriv: + svc #SYSTEM_CALL_vQueueUnregisterQueue +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pcQueueGetName +MPU_pcQueueGetName: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pcQueueGetName_Unpriv + MPU_pcQueueGetName_Priv: + b MPU_pcQueueGetNameImpl + MPU_pcQueueGetName_Unpriv: + svc #SYSTEM_CALL_pcQueueGetName +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pvTimerGetTimerID +MPU_pvTimerGetTimerID: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pvTimerGetTimerID_Unpriv + MPU_pvTimerGetTimerID_Priv: + b MPU_pvTimerGetTimerIDImpl + MPU_pvTimerGetTimerID_Unpriv: + svc #SYSTEM_CALL_pvTimerGetTimerID +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTimerSetTimerID +MPU_vTimerSetTimerID: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTimerSetTimerID_Unpriv + MPU_vTimerSetTimerID_Priv: + b MPU_vTimerSetTimerIDImpl + MPU_vTimerSetTimerID_Unpriv: + svc #SYSTEM_CALL_vTimerSetTimerID +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerIsTimerActive +MPU_xTimerIsTimerActive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerIsTimerActive_Unpriv + MPU_xTimerIsTimerActive_Priv: + b MPU_xTimerIsTimerActiveImpl + MPU_xTimerIsTimerActive_Unpriv: + svc #SYSTEM_CALL_xTimerIsTimerActive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetTimerDaemonTaskHandle +MPU_xTimerGetTimerDaemonTaskHandle: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv + MPU_xTimerGetTimerDaemonTaskHandle_Priv: + b MPU_xTimerGetTimerDaemonTaskHandleImpl + MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGenericCommandFromTaskEntry +MPU_xTimerGenericCommandFromTaskEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGenericCommandFromTask_Unpriv + MPU_xTimerGenericCommandFromTask_Priv: + b MPU_xTimerGenericCommandFromTaskImpl + MPU_xTimerGenericCommandFromTask_Unpriv: + svc #SYSTEM_CALL_xTimerGenericCommandFromTask +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pcTimerGetName +MPU_pcTimerGetName: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pcTimerGetName_Unpriv + MPU_pcTimerGetName_Priv: + b MPU_pcTimerGetNameImpl + MPU_pcTimerGetName_Unpriv: + svc #SYSTEM_CALL_pcTimerGetName +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTimerSetReloadMode +MPU_vTimerSetReloadMode: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTimerSetReloadMode_Unpriv + MPU_vTimerSetReloadMode_Priv: + b MPU_vTimerSetReloadModeImpl + MPU_vTimerSetReloadMode_Unpriv: + svc #SYSTEM_CALL_vTimerSetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetReloadMode +MPU_xTimerGetReloadMode: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetReloadMode_Unpriv + MPU_xTimerGetReloadMode_Priv: + b MPU_xTimerGetReloadModeImpl + MPU_xTimerGetReloadMode_Unpriv: + svc #SYSTEM_CALL_xTimerGetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTimerGetReloadMode +MPU_uxTimerGetReloadMode: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTimerGetReloadMode_Unpriv + MPU_uxTimerGetReloadMode_Priv: + b MPU_uxTimerGetReloadModeImpl + MPU_uxTimerGetReloadMode_Unpriv: + svc #SYSTEM_CALL_uxTimerGetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetPeriod +MPU_xTimerGetPeriod: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetPeriod_Unpriv + MPU_xTimerGetPeriod_Priv: + b MPU_xTimerGetPeriodImpl + MPU_xTimerGetPeriod_Unpriv: + svc #SYSTEM_CALL_xTimerGetPeriod +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetExpiryTime +MPU_xTimerGetExpiryTime: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetExpiryTime_Unpriv + MPU_xTimerGetExpiryTime_Priv: + b MPU_xTimerGetExpiryTimeImpl + MPU_xTimerGetExpiryTime_Unpriv: + svc #SYSTEM_CALL_xTimerGetExpiryTime +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupWaitBitsEntry +MPU_xEventGroupWaitBitsEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupWaitBits_Unpriv + MPU_xEventGroupWaitBits_Priv: + b MPU_xEventGroupWaitBitsImpl + MPU_xEventGroupWaitBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupWaitBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupClearBits +MPU_xEventGroupClearBits: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupClearBits_Unpriv + MPU_xEventGroupClearBits_Priv: + b MPU_xEventGroupClearBitsImpl + MPU_xEventGroupClearBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupClearBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupSetBits +MPU_xEventGroupSetBits: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupSetBits_Unpriv + MPU_xEventGroupSetBits_Priv: + b MPU_xEventGroupSetBitsImpl + MPU_xEventGroupSetBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupSetBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupSync +MPU_xEventGroupSync: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupSync_Unpriv + MPU_xEventGroupSync_Priv: + b MPU_xEventGroupSyncImpl + MPU_xEventGroupSync_Unpriv: + svc #SYSTEM_CALL_xEventGroupSync +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxEventGroupGetNumber +MPU_uxEventGroupGetNumber: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxEventGroupGetNumber_Unpriv + MPU_uxEventGroupGetNumber_Priv: + b MPU_uxEventGroupGetNumberImpl + MPU_uxEventGroupGetNumber_Unpriv: + svc #SYSTEM_CALL_uxEventGroupGetNumber +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vEventGroupSetNumber +MPU_vEventGroupSetNumber: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vEventGroupSetNumber_Unpriv + MPU_vEventGroupSetNumber_Priv: + b MPU_vEventGroupSetNumberImpl + MPU_vEventGroupSetNumber_Unpriv: + svc #SYSTEM_CALL_vEventGroupSetNumber +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSend +MPU_xStreamBufferSend: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSend_Unpriv + MPU_xStreamBufferSend_Priv: + b MPU_xStreamBufferSendImpl + MPU_xStreamBufferSend_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferReceive +MPU_xStreamBufferReceive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferReceive_Unpriv + MPU_xStreamBufferReceive_Priv: + b MPU_xStreamBufferReceiveImpl + MPU_xStreamBufferReceive_Unpriv: + svc #SYSTEM_CALL_xStreamBufferReceive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferIsFull +MPU_xStreamBufferIsFull: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferIsFull_Unpriv + MPU_xStreamBufferIsFull_Priv: + b MPU_xStreamBufferIsFullImpl + MPU_xStreamBufferIsFull_Unpriv: + svc #SYSTEM_CALL_xStreamBufferIsFull +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferIsEmpty +MPU_xStreamBufferIsEmpty: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferIsEmpty_Unpriv + MPU_xStreamBufferIsEmpty_Priv: + b MPU_xStreamBufferIsEmptyImpl + MPU_xStreamBufferIsEmpty_Unpriv: + svc #SYSTEM_CALL_xStreamBufferIsEmpty +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSpacesAvailable +MPU_xStreamBufferSpacesAvailable: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSpacesAvailable_Unpriv + MPU_xStreamBufferSpacesAvailable_Priv: + b MPU_xStreamBufferSpacesAvailableImpl + MPU_xStreamBufferSpacesAvailable_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSpacesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferBytesAvailable +MPU_xStreamBufferBytesAvailable: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferBytesAvailable_Unpriv + MPU_xStreamBufferBytesAvailable_Priv: + b MPU_xStreamBufferBytesAvailableImpl + MPU_xStreamBufferBytesAvailable_Unpriv: + svc #SYSTEM_CALL_xStreamBufferBytesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSetTriggerLevel +MPU_xStreamBufferSetTriggerLevel: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSetTriggerLevel_Unpriv + MPU_xStreamBufferSetTriggerLevel_Priv: + b MPU_xStreamBufferSetTriggerLevelImpl + MPU_xStreamBufferSetTriggerLevel_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferNextMessageLengthBytes +MPU_xStreamBufferNextMessageLengthBytes: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv + MPU_xStreamBufferNextMessageLengthBytes_Priv: + b MPU_xStreamBufferNextMessageLengthBytesImpl + MPU_xStreamBufferNextMessageLengthBytes_Unpriv: + svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes +/*-----------------------------------------------------------*/ + +/* Default weak implementations in case one is not available from + * mpu_wrappers because of config options. */ + + PUBWEAK MPU_xTaskDelayUntilImpl +MPU_xTaskDelayUntilImpl: + b MPU_xTaskDelayUntilImpl + + PUBWEAK MPU_xTaskAbortDelayImpl +MPU_xTaskAbortDelayImpl: + b MPU_xTaskAbortDelayImpl + + PUBWEAK MPU_vTaskDelayImpl +MPU_vTaskDelayImpl: + b MPU_vTaskDelayImpl + + PUBWEAK MPU_uxTaskPriorityGetImpl +MPU_uxTaskPriorityGetImpl: + b MPU_uxTaskPriorityGetImpl + + PUBWEAK MPU_eTaskGetStateImpl +MPU_eTaskGetStateImpl: + b MPU_eTaskGetStateImpl + + PUBWEAK MPU_vTaskGetInfoImpl +MPU_vTaskGetInfoImpl: + b MPU_vTaskGetInfoImpl + + PUBWEAK MPU_xTaskGetIdleTaskHandleImpl +MPU_xTaskGetIdleTaskHandleImpl: + b MPU_xTaskGetIdleTaskHandleImpl + + PUBWEAK MPU_vTaskSuspendImpl +MPU_vTaskSuspendImpl: + b MPU_vTaskSuspendImpl + + PUBWEAK MPU_vTaskResumeImpl +MPU_vTaskResumeImpl: + b MPU_vTaskResumeImpl + + PUBWEAK MPU_xTaskGetTickCountImpl +MPU_xTaskGetTickCountImpl: + b MPU_xTaskGetTickCountImpl + + PUBWEAK MPU_uxTaskGetNumberOfTasksImpl +MPU_uxTaskGetNumberOfTasksImpl: + b MPU_uxTaskGetNumberOfTasksImpl + + PUBWEAK MPU_ulTaskGetRunTimeCounterImpl +MPU_ulTaskGetRunTimeCounterImpl: + b MPU_ulTaskGetRunTimeCounterImpl + + PUBWEAK MPU_ulTaskGetRunTimePercentImpl +MPU_ulTaskGetRunTimePercentImpl: + b MPU_ulTaskGetRunTimePercentImpl + + PUBWEAK MPU_ulTaskGetIdleRunTimePercentImpl +MPU_ulTaskGetIdleRunTimePercentImpl: + b MPU_ulTaskGetIdleRunTimePercentImpl + + PUBWEAK MPU_ulTaskGetIdleRunTimeCounterImpl +MPU_ulTaskGetIdleRunTimeCounterImpl: + b MPU_ulTaskGetIdleRunTimeCounterImpl + + PUBWEAK MPU_vTaskSetApplicationTaskTagImpl +MPU_vTaskSetApplicationTaskTagImpl: + b MPU_vTaskSetApplicationTaskTagImpl + + PUBWEAK MPU_xTaskGetApplicationTaskTagImpl +MPU_xTaskGetApplicationTaskTagImpl: + b MPU_xTaskGetApplicationTaskTagImpl + + PUBWEAK MPU_vTaskSetThreadLocalStoragePointerImpl +MPU_vTaskSetThreadLocalStoragePointerImpl: + b MPU_vTaskSetThreadLocalStoragePointerImpl + + PUBWEAK MPU_pvTaskGetThreadLocalStoragePointerImpl +MPU_pvTaskGetThreadLocalStoragePointerImpl: + b MPU_pvTaskGetThreadLocalStoragePointerImpl + + PUBWEAK MPU_uxTaskGetSystemStateImpl +MPU_uxTaskGetSystemStateImpl: + b MPU_uxTaskGetSystemStateImpl + + PUBWEAK MPU_uxTaskGetStackHighWaterMarkImpl +MPU_uxTaskGetStackHighWaterMarkImpl: + b MPU_uxTaskGetStackHighWaterMarkImpl + + PUBWEAK MPU_uxTaskGetStackHighWaterMark2Impl +MPU_uxTaskGetStackHighWaterMark2Impl: + b MPU_uxTaskGetStackHighWaterMark2Impl + + PUBWEAK MPU_xTaskGetCurrentTaskHandleImpl +MPU_xTaskGetCurrentTaskHandleImpl: + b MPU_xTaskGetCurrentTaskHandleImpl + + PUBWEAK MPU_xTaskGetSchedulerStateImpl +MPU_xTaskGetSchedulerStateImpl: + b MPU_xTaskGetSchedulerStateImpl + + PUBWEAK MPU_vTaskSetTimeOutStateImpl +MPU_vTaskSetTimeOutStateImpl: + b MPU_vTaskSetTimeOutStateImpl + + PUBWEAK MPU_xTaskCheckForTimeOutImpl +MPU_xTaskCheckForTimeOutImpl: + b MPU_xTaskCheckForTimeOutImpl + + PUBWEAK MPU_xTaskGenericNotifyImpl +MPU_xTaskGenericNotifyImpl: + b MPU_xTaskGenericNotifyImpl + + PUBWEAK MPU_xTaskGenericNotifyWaitImpl +MPU_xTaskGenericNotifyWaitImpl: + b MPU_xTaskGenericNotifyWaitImpl + + PUBWEAK MPU_ulTaskGenericNotifyTakeImpl +MPU_ulTaskGenericNotifyTakeImpl: + b MPU_ulTaskGenericNotifyTakeImpl + + PUBWEAK MPU_xTaskGenericNotifyStateClearImpl +MPU_xTaskGenericNotifyStateClearImpl: + b MPU_xTaskGenericNotifyStateClearImpl + + PUBWEAK MPU_ulTaskGenericNotifyValueClearImpl +MPU_ulTaskGenericNotifyValueClearImpl: + b MPU_ulTaskGenericNotifyValueClearImpl + + PUBWEAK MPU_xQueueGenericSendImpl +MPU_xQueueGenericSendImpl: + b MPU_xQueueGenericSendImpl + + PUBWEAK MPU_uxQueueMessagesWaitingImpl +MPU_uxQueueMessagesWaitingImpl: + b MPU_uxQueueMessagesWaitingImpl + + PUBWEAK MPU_uxQueueSpacesAvailableImpl +MPU_uxQueueSpacesAvailableImpl: + b MPU_uxQueueSpacesAvailableImpl + + PUBWEAK MPU_xQueueReceiveImpl +MPU_xQueueReceiveImpl: + b MPU_xQueueReceiveImpl + + PUBWEAK MPU_xQueuePeekImpl +MPU_xQueuePeekImpl: + b MPU_xQueuePeekImpl + + PUBWEAK MPU_xQueueSemaphoreTakeImpl +MPU_xQueueSemaphoreTakeImpl: + b MPU_xQueueSemaphoreTakeImpl + + PUBWEAK MPU_xQueueGetMutexHolderImpl +MPU_xQueueGetMutexHolderImpl: + b MPU_xQueueGetMutexHolderImpl + + PUBWEAK MPU_xQueueTakeMutexRecursiveImpl +MPU_xQueueTakeMutexRecursiveImpl: + b MPU_xQueueTakeMutexRecursiveImpl + + PUBWEAK MPU_xQueueGiveMutexRecursiveImpl +MPU_xQueueGiveMutexRecursiveImpl: + b MPU_xQueueGiveMutexRecursiveImpl + + PUBWEAK MPU_xQueueSelectFromSetImpl +MPU_xQueueSelectFromSetImpl: + b MPU_xQueueSelectFromSetImpl + + PUBWEAK MPU_xQueueAddToSetImpl +MPU_xQueueAddToSetImpl: + b MPU_xQueueAddToSetImpl + + PUBWEAK MPU_vQueueAddToRegistryImpl +MPU_vQueueAddToRegistryImpl: + b MPU_vQueueAddToRegistryImpl + + PUBWEAK MPU_vQueueUnregisterQueueImpl +MPU_vQueueUnregisterQueueImpl: + b MPU_vQueueUnregisterQueueImpl + + PUBWEAK MPU_pcQueueGetNameImpl +MPU_pcQueueGetNameImpl: + b MPU_pcQueueGetNameImpl + + PUBWEAK MPU_pvTimerGetTimerIDImpl +MPU_pvTimerGetTimerIDImpl: + b MPU_pvTimerGetTimerIDImpl + + PUBWEAK MPU_vTimerSetTimerIDImpl +MPU_vTimerSetTimerIDImpl: + b MPU_vTimerSetTimerIDImpl + + PUBWEAK MPU_xTimerIsTimerActiveImpl +MPU_xTimerIsTimerActiveImpl: + b MPU_xTimerIsTimerActiveImpl + + PUBWEAK MPU_xTimerGetTimerDaemonTaskHandleImpl +MPU_xTimerGetTimerDaemonTaskHandleImpl: + b MPU_xTimerGetTimerDaemonTaskHandleImpl + + PUBWEAK MPU_xTimerGenericCommandFromTaskImpl +MPU_xTimerGenericCommandFromTaskImpl: + b MPU_xTimerGenericCommandFromTaskImpl + + PUBWEAK MPU_pcTimerGetNameImpl +MPU_pcTimerGetNameImpl: + b MPU_pcTimerGetNameImpl + + PUBWEAK MPU_vTimerSetReloadModeImpl +MPU_vTimerSetReloadModeImpl: + b MPU_vTimerSetReloadModeImpl + + PUBWEAK MPU_xTimerGetReloadModeImpl +MPU_xTimerGetReloadModeImpl: + b MPU_xTimerGetReloadModeImpl + + PUBWEAK MPU_uxTimerGetReloadModeImpl +MPU_uxTimerGetReloadModeImpl: + b MPU_uxTimerGetReloadModeImpl + + PUBWEAK MPU_xTimerGetPeriodImpl +MPU_xTimerGetPeriodImpl: + b MPU_xTimerGetPeriodImpl + + PUBWEAK MPU_xTimerGetExpiryTimeImpl +MPU_xTimerGetExpiryTimeImpl: + b MPU_xTimerGetExpiryTimeImpl + + PUBWEAK MPU_xEventGroupWaitBitsImpl +MPU_xEventGroupWaitBitsImpl: + b MPU_xEventGroupWaitBitsImpl + + PUBWEAK MPU_xEventGroupClearBitsImpl +MPU_xEventGroupClearBitsImpl: + b MPU_xEventGroupClearBitsImpl + + PUBWEAK MPU_xEventGroupSetBitsImpl +MPU_xEventGroupSetBitsImpl: + b MPU_xEventGroupSetBitsImpl + + PUBWEAK MPU_xEventGroupSyncImpl +MPU_xEventGroupSyncImpl: + b MPU_xEventGroupSyncImpl + + PUBWEAK MPU_uxEventGroupGetNumberImpl +MPU_uxEventGroupGetNumberImpl: + b MPU_uxEventGroupGetNumberImpl + + PUBWEAK MPU_vEventGroupSetNumberImpl +MPU_vEventGroupSetNumberImpl: + b MPU_vEventGroupSetNumberImpl + + PUBWEAK MPU_xStreamBufferSendImpl +MPU_xStreamBufferSendImpl: + b MPU_xStreamBufferSendImpl + + PUBWEAK MPU_xStreamBufferReceiveImpl +MPU_xStreamBufferReceiveImpl: + b MPU_xStreamBufferReceiveImpl + + PUBWEAK MPU_xStreamBufferIsFullImpl +MPU_xStreamBufferIsFullImpl: + b MPU_xStreamBufferIsFullImpl + + PUBWEAK MPU_xStreamBufferIsEmptyImpl +MPU_xStreamBufferIsEmptyImpl: + b MPU_xStreamBufferIsEmptyImpl + + PUBWEAK MPU_xStreamBufferSpacesAvailableImpl +MPU_xStreamBufferSpacesAvailableImpl: + b MPU_xStreamBufferSpacesAvailableImpl + + PUBWEAK MPU_xStreamBufferBytesAvailableImpl +MPU_xStreamBufferBytesAvailableImpl: + b MPU_xStreamBufferBytesAvailableImpl + + PUBWEAK MPU_xStreamBufferSetTriggerLevelImpl +MPU_xStreamBufferSetTriggerLevelImpl: + b MPU_xStreamBufferSetTriggerLevelImpl + + PUBWEAK MPU_xStreamBufferNextMessageLengthBytesImpl +MPU_xStreamBufferNextMessageLengthBytesImpl: + b MPU_xStreamBufferNextMessageLengthBytesImpl + +/*-----------------------------------------------------------*/ + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + END diff --git a/portable/IAR/ARM_CM52/non_secure/port.c b/portable/IAR/ARM_CM52/non_secure/port.c new file mode 100644 index 000000000..76d2b2445 --- /dev/null +++ b/portable/IAR/ARM_CM52/non_secure/port.c @@ -0,0 +1,2280 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024-2025 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU includes. */ +#include "mpu_wrappers.h" +#include "mpu_syscall_numbers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration settings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to check the validity of an interrupt priority. + */ +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) ) +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used during system call enter and exit. + */ +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Offsets in the stack to the parameters when inside the SVC handler. + */ +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +#if ( portARMV8M_MINOR_VERSION >= 1 ) + + /* Enable Privileged eXecute Never MPU attribute for the selected memory + * region. */ + #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL ) +#endif /* portARMV8M_MINOR_VERSION >= 1 */ + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Extract first address of the MPU region as encoded in the + * RBAR (Region Base Address Register) value. */ +#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \ + ( ( rbar ) & portMPU_RBAR_ADDRESS_MASK ) + +/* Extract last address of the MPU region as encoded in the + * RLAR (Region Limit Address Register) value. */ +#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \ + ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK ) + +/* Does addr lies within [start, end] address range? */ +#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \ + ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) ) + +/* Is the access request satisfied by the available permissions? */ +#define portIS_AUTHORIZED( accessRequest, permissions ) \ + ( ( ( permissions ) & ( accessRequest ) ) == accessRequest ) + +/* Max value that fits in a uint32_t type. */ +#define portUINT32_MAX ( ~( ( uint32_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. + */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 + +/** + * @brief Constants required to check and configure PACBTI security feature implementation. + */ +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) ) + + #define portCONTROL_UPAC_EN ( 1UL << 7UL ) + #define portCONTROL_PAC_EN ( 1UL << 6UL ) + #define portCONTROL_UBTI_EN ( 1UL << 5UL ) + #define portCONTROL_BTI_EN ( 1UL << 4UL ) + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Extract MPU region's access permissions from the Region Base Address + * Register (RBAR) value. + * + * @param ulRBARValue RBAR value for the MPU region. + * + * @return uint32_t Access permissions. + */ + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + + /** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + /** + * @brief Configures PACBTI features. + * + * This function configures the Pointer Authentication, and Branch Target + * Identification security features as per the user configuration. It returns + * the value of the special purpose CONTROL register accordingly, and optionally + * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M + * architecture based) target supports PACBTI security feature. + * + * @param xWriteControlRegister Used to control whether the special purpose + * CONTROL register should be updated or not. + * + * @return CONTROL register value according to the configured PACBTI option. + */ + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the system call stack so that upon returning from + * SVC, the system call stack is used. + * + * @param pulTaskStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + * @param ucSystemCallNumber The system call number of the system call. + */ + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Raise SVC for exiting from a system call. + */ + void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief This variable is set to pdTRUE when the scheduler is started. + */ + PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + + /** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +/** + * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + /** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + + /** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + + /** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the cpsid instruction + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessPermissions = 0; + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_ONLY ) + { + ulAccessPermissions = tskMPU_READ_PERMISSION; + } + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_WRITE ) + { + ulAccessPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION ); + } + + return ulAccessPermissions; + } + +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } + +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ portOFFSET_TO_PC ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ]; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulSystemCallStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the system call section (i.e. application is + * not raising SVC directly). + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as + * it is non-NULL only during the execution of a system call (i.e. + * between system call enter and exit). + * 3. System call is not for a kernel API disabled by the configuration + * in FreeRTOSConfig.h. + * 4. We do not need to check that ucSystemCallNumber is within range + * because the assembly SVC handler checks that before calling + * this function. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) && + ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) ) + { + pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the system call stack for the stack frame. */ + pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulSystemCallStack[ i ] = pulTaskStack[ i ]; + } + + /* Store the value of the Link Register before the SVC was raised. + * It contains the address of the caller of the System Call entry + * point (i.e. the caller of the MPU_). We need to restore it + * when we exit from the system call. */ + pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; + + /* Store the value of the PSPLIM register before the SVC was raised. + * We need to restore it when we exit from the system call. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* Use the pulSystemCallStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif + + /* Start executing the system call upon returning from this handler. */ + pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; + + /* Raise a request to exit from the system call upon finishing the + * system call. */ + pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; + + /* Remember the location where we should copy the stack frame when we exit from + * the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize; + + /* Record if the hardware used padding to force the stack pointer + * to be double word aligned. */ + if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK ) + { + pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG; + } + else + { + pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG ); + } + + /* We ensure in pxPortInitialiseStack that the system call stack is + * double word aligned and therefore, there is no need of padding. + * Clear the bit[9] of stacked xPSR. */ + pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + + /* Raise the privilege for the duration of the system call. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " bics r0, r1 \n" /* Clear nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */ + { + __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulTaskStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the privileged code (i.e. application is not + * raising SVC directly). This SVC is only raised from + * vRequestSystemCallExit which is in the privileged code section. + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL - + * this means that we previously entered a system call and the + * application is not attempting to exit without entering a system + * call. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) ) + { + pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the task stack for the stack frame. */ + pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulTaskStack[ i ] = pulSystemCallStack[ i ]; + } + + /* Use the pulTaskStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) ); + + /* Return to the caller of the System Call entry point (i.e. the + * caller of the MPU_). */ + pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + /* Ensure that LR has a valid value.*/ + pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + + /* Restore the PSPLIM register to what it was at the time of + * system call entry. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* If the hardware used padding to force the stack pointer + * to be double word aligned, set the stacked xPSR bit[9], + * otherwise clear it. */ + if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG ) + { + pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK; + } + else + { + pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + } + + /* This is not NULL only for the duration of the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; + + /* Drop the privilege before returning to the thread mode. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " orrs r0, r1 \n" /* Set nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xTaskIsPrivileged = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xTaskIsPrivileged = pdTRUE; + } + + return xTaskIsPrivileged; + } + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged, + xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulIndex = 0; + uint32_t ulControl = 0x0; + + xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ + ulIndex++; + + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + ulIndex++; + + #if ( configENABLE_TRUSTZONE == 1 ) + { + xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */ + ulIndex++; + } + #endif /* configENABLE_TRUSTZONE */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + ulIndex++; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Check PACBTI security feature configuration before pushing the + * CONTROL register's value on task's TCB. */ + ulControl = prvConfigurePACBTI( pdFALSE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + if( xRunPrivileged == pdTRUE ) + { + xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + else + { + xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG ); + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ + ulIndex++; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + { + /* Ensure that the system call stack is double word aligned. */ + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) + + ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + /* This is not NULL only for the duration of a system call. */ + xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL; + } + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ]; + ulIndex++; + } + } + #endif /* configENABLE_PAC */ + + return &( xMPUSettings->ulContext[ ulIndex ] ); + } + +#else /* configENABLE_MPU */ + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ + { + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + pxTopOfStack--; + *pxTopOfStack = ulTaskPacKey[ i ]; + } + } + #endif /* configENABLE_PAC */ + + return pxTopOfStack; + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Set the CONTROL register value based on PACBTI security feature + * configuration before starting the first task. */ + ( void ) prvConfigurePACBTI( pdTRUE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + { + xSchedulerRunning = pdTRUE; + } + #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + configSTACK_DEPTH_TYPE uxStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( uxStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* PXN. */ + #if ( portARMV8M_MINOR_VERSION >= 1 ) + { + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ); + } + } + #endif /* portARMV8M_MINOR_VERSION >= 1 */ + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, + uint32_t ulBufferLength, + uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */ + + { + uint32_t i, ulBufferStartAddress, ulBufferEndAddress; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE ) + { + ulBufferStartAddress = ( uint32_t ) pvBuffer; + ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL ); + + for( i = 0; i < portTOTAL_NUM_REGIONS; i++ ) + { + /* Is the MPU region enabled? */ + if( ( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR & portMPU_RLAR_REGION_ENABLE ) == portMPU_RLAR_REGION_ENABLE ) + { + if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_AUTHORIZED( ulAccessRequested, + prvGetRegionAccessPermissions( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ) ) ) + { + xAccessGranted = pdTRUE; + break; + } + } + } + } + } + + return xAccessGranted; + } + +#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings; + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else + { + xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 ) + { + xAccessGranted = pdTRUE; + } + } + } + + return xAccessGranted; + } + + #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + ( void ) lInternalIndexOfKernelObject; + + /* If Access Control List feature is not used, all the tasks have + * access to all the kernel objects. */ + return pdTRUE; + } + + #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + { + uint32_t ulControl = 0x0; + + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); + + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; + + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/ARM_CM52/non_secure/portasm.h b/portable/IAR/ARM_CM52/non_secure/portasm.h new file mode 100644 index 000000000..b7021b024 --- /dev/null +++ b/portable/IAR/ARM_CM52/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kernel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/portable/IAR/ARM_CM52/non_secure/portasm.s b/portable/IAR/ARM_CM52/non_secure/portasm.s new file mode 100644 index 000000000..8d5988819 --- /dev/null +++ b/portable/IAR/ARM_CM52/non_secure/portasm.s @@ -0,0 +1,543 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" + +/* System call numbers includes. */ +#include "mpu_syscall_numbers.h" + +#ifndef configUSE_MPU_WRAPPERS_V1 + #define configUSE_MPU_WRAPPERS_V1 0 +#endif + + EXTERN pxCurrentTCB + EXTERN xSecureContext + EXTERN vTaskSwitchContext + EXTERN vPortSVCHandler_C + EXTERN SecureContext_SaveContext + EXTERN SecureContext_LoadContext +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + EXTERN vSystemCallEnter + EXTERN vSystemCallExit +#endif + + PUBLIC xIsPrivileged + PUBLIC vResetPrivilege + PUBLIC vPortAllocateSecureContext + PUBLIC vRestoreContextOfFirstTask + PUBLIC vRaisePrivilege + PUBLIC vStartFirstTask + PUBLIC ulSetInterruptMask + PUBLIC vClearInterruptMask + PUBLIC PendSV_Handler + PUBLIC SVC_Handler + PUBLIC vPortFreeSecureContext +/*-----------------------------------------------------------*/ + +/*---------------- Unprivileged Functions -------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION .text:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +xIsPrivileged: + mrs r0, control /* r0 = CONTROL. */ + tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + ite ne + movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vResetPrivilege: + mrs r0, control /* r0 = CONTROL. */ + orr r0, r0, #1 /* r0 = r0 | 1. */ + msr control, r0 /* CONTROL = r0. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vPortAllocateSecureContext: + svc 100 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 100. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +/*----------------- Privileged Functions --------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION privileged_functions:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +vRestoreContextOfFirstTask: + program_mpu_first_task: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r3] /* r0 = pxCurrentTCB. */ + + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + str r2, [r1] /* Disable MPU. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r1, [r2] /* Program MAIR0. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + + movs r3, #4 /* r3 = 4. */ + str r3, [r1] /* Program RNR = 4. */ + ldmia r0!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + #if ( configTOTAL_MPU_REGIONS == 16 ) + movs r3, #8 /* r3 = 8. */ + str r3, [r1] /* Program RNR = 8. */ + ldmia r0!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + movs r3, #12 /* r3 = 12. */ + str r3, [r1] /* Program RNR = 12. */ + ldmia r0!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + orr r2, #1 /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */ + str r2, [r1] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + + restore_context_first_task: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* r1 = pxCurrentTCB.*/ + ldr r2, [r1] /* r2 = Location of saved context in TCB. */ + + restore_special_regs_first_task: + #if ( configENABLE_PAC == 1 ) + ldmdb r2!, {r3-r6} /* Read task's dedicated PAC key from the task's context. */ + msr PAC_KEY_P_0, r3 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_1, r4 + msr PAC_KEY_P_2, r5 + msr PAC_KEY_P_3, r6 + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + ldmdb r2!, {r0, r3-r5, lr} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */ + msr psp, r3 + msr psplim, r4 + msr control, r5 + ldr r4, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + str r0, [r4] /* Restore xSecureContext. */ + + restore_general_regs_first_task: + ldmdb r2!, {r4-r11} /* r4-r11 contain hardware saved context. */ + stmia r3!, {r4-r11} /* Copy the hardware saved context on the task stack. */ + ldmdb r2!, {r4-r11} /* r4-r11 restored. */ + + restore_context_done_first_task: + str r2, [r1] /* Save the location where the context should be saved next as the first member of TCB. */ + mov r0, #0 + msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ + bx lr + +#else /* configENABLE_MPU */ + +vRestoreContextOfFirstTask: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r3, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + +#if ( configENABLE_PAC == 1 ) + ldmia r0!, {r1-r4} /* Read task's dedicated PAC key from stack. */ + msr PAC_KEY_P_3, r1 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_2, r2 + msr PAC_KEY_P_1, r3 + msr PAC_KEY_P_0, r4 + clrm {r1-r4} /* Clear r1-r4. */ +#endif /* configENABLE_PAC */ + + ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */ + ldr r4, =xSecureContext + str r1, [r4] /* Set xSecureContext to this task's value for the same. */ + msr psplim, r2 /* Set this task's PSPLIM value. */ + mrs r1, control /* Obtain current control register value. */ + orrs r1, r1, #2 /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */ + msr control, r1 /* Write back the new control register value. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + mov r0, #0 + msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ + bx r3 /* Finally, branch to EXC_RETURN. */ + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +vRaisePrivilege: + mrs r0, control /* Read the CONTROL register. */ + bic r0, r0, #1 /* Clear the bit 0. */ + msr control, r0 /* Write back the new CONTROL value. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vStartFirstTask: + ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */ + ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */ + ldr r0, [r0] /* The first entry in vector table is stack pointer. */ + msr msp, r0 /* Set the MSP back to the start of the stack. */ + cpsie i /* Globally enable interrupts. */ + cpsie f + dsb + isb + svc 102 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */ +/*-----------------------------------------------------------*/ + +ulSetInterruptMask: + mrs r0, basepri /* r0 = basepri. Return original basepri value. */ + mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r1 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vClearInterruptMask: + msr basepri, r0 /* basepri = ulMask. */ + dsb + isb + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +PendSV_Handler: + ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + ldr r0, [r3] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */ + ldr r2, [r1] /* r2 = Location in TCB where the context should be saved. */ + + cbz r0, save_ns_context /* No secure context to save. */ + save_s_context: + push {r0-r2, lr} + bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r0-r2, lr} + + save_ns_context: + mov r3, lr /* r3 = LR (EXC_RETURN). */ + lsls r3, r3, #25 /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bmi save_special_regs /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + + save_general_regs: + mrs r3, psp + + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + add r3, r3, #0x20 /* Move r3 to location where s0 is saved. */ + tst lr, #0x10 + ittt eq + vstmiaeq r2!, {s16-s31} /* Store s16-s31. */ + vldmiaeq r3, {s0-s16} /* Copy hardware saved FP context into s0-s16. */ + vstmiaeq r2!, {s0-s16} /* Store hardware saved FP context. */ + sub r3, r3, #0x20 /* Set r3 back to the location of hardware saved context. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + + stmia r2!, {r4-r11} /* Store r4-r11. */ + ldmia r3, {r4-r11} /* Copy the hardware saved context into r4-r11. */ + stmia r2!, {r4-r11} /* Store the hardware saved context. */ + + save_special_regs: + mrs r3, psp /* r3 = PSP. */ + mrs r4, psplim /* r4 = PSPLIM. */ + mrs r5, control /* r5 = CONTROL. */ + stmia r2!, {r0, r3-r5, lr} /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ + #if ( configENABLE_PAC == 1 ) + mrs r3, PAC_KEY_P_0 /* Read task's dedicated PAC key from the PAC key registers. */ + mrs r4, PAC_KEY_P_1 + mrs r5, PAC_KEY_P_2 + mrs r6, PAC_KEY_P_3 + stmia r2!, {r3-r6} /* Store the task's dedicated PAC key on the task's context. */ + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + + str r2, [r1] /* Save the location from where the context should be restored as the first member of TCB. */ + + select_next_task: + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bl vTaskSwitchContext + mov r0, #0 /* r0 = 0. */ + msr basepri, r0 /* Enable interrupts. */ + + program_mpu: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r3] /* r0 = pxCurrentTCB.*/ + + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + str r2, [r1] /* Disable MPU. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r1, [r2] /* Program MAIR0. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + + movs r3, #4 /* r3 = 4. */ + str r3, [r1] /* Program RNR = 4. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + #if ( configTOTAL_MPU_REGIONS == 16 ) + movs r3, #8 /* r3 = 8. */ + str r3, [r1] /* Program RNR = 8. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + movs r3, #12 /* r3 = 12. */ + str r3, [r1] /* Program RNR = 12. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + orr r2, #1 /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */ + str r2, [r1] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + + restore_context: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* r1 = pxCurrentTCB.*/ + ldr r2, [r1] /* r2 = Location of saved context in TCB. */ + + restore_special_regs: + #if ( configENABLE_PAC == 1 ) + ldmdb r2!, {r3-r6} /* Read task's dedicated PAC key from the task's context. */ + msr PAC_KEY_P_0, r3 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_1, r4 + msr PAC_KEY_P_2, r5 + msr PAC_KEY_P_3, r6 + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + ldmdb r2!, {r0, r3-r5, lr} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */ + msr psp, r3 + msr psplim, r4 + msr control, r5 + ldr r4, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + str r0, [r4] /* Restore xSecureContext. */ + cbz r0, restore_ns_context /* No secure context to restore. */ + + restore_s_context: + push {r1-r3, lr} + bl SecureContext_LoadContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r1-r3, lr} + + restore_ns_context: + mov r0, lr /* r0 = LR (EXC_RETURN). */ + lsls r0, r0, #25 /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bmi restore_context_done /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + + restore_general_regs: + ldmdb r2!, {r4-r11} /* r4-r11 contain hardware saved context. */ + stmia r3!, {r4-r11} /* Copy the hardware saved context on the task stack. */ + ldmdb r2!, {r4-r11} /* r4-r11 restored. */ + + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 + ittt eq + vldmdbeq r2!, {s0-s16} /* s0-s16 contain hardware saved FP context. */ + vstmiaeq r3!, {s0-s16} /* Copy hardware saved FP context on the task stack. */ + vldmdbeq r2!, {s16-s31} /* Restore s16-s31. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + + restore_context_done: + str r2, [r1] /* Save the location where the context should be saved next as the first member of TCB. */ + bx lr + +#else /* configENABLE_MPU */ + +PendSV_Handler: + ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + ldr r0, [r3] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */ + mrs r2, psp /* Read PSP in r2. */ + + cbz r0, save_ns_context /* No secure context to save. */ + save_s_context: + push {r0-r2, lr} + bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r0-r2, lr} + + save_ns_context: + mov r3, lr /* r3 = LR. */ + lsls r3, r3, #25 /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bmi save_special_regs /* If r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used. */ + + save_general_regs: + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + it eq + vstmdbeq r2!, {s16-s31} /* Store the additional FP context registers which are not saved automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + stmdb r2!, {r4-r11} /* Store the registers that are not saved automatically. */ + + save_special_regs: + mrs r3, psplim /* r3 = PSPLIM. */ + stmdb r2!, {r0, r3, lr} /* Store xSecureContext, PSPLIM and LR on the stack. */ + #if ( configENABLE_PAC == 1 ) + mrs r3, PAC_KEY_P_3 /* Read task's dedicated PAC key from the PAC key registers. */ + mrs r4, PAC_KEY_P_2 + mrs r5, PAC_KEY_P_1 + mrs r6, PAC_KEY_P_0 + stmdb r2!, {r3-r6} /* Store the task's dedicated PAC key on the stack. */ + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + + str r2, [r1] /* Save the new top of stack in TCB. */ + + select_next_task: + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bl vTaskSwitchContext + mov r0, #0 /* r0 = 0. */ + msr basepri, r0 /* Enable interrupts. */ + + restore_context: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB. */ + ldr r2, [r1] /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */ + + restore_special_regs: + #if ( configENABLE_PAC == 1 ) + ldmia r2!, {r3-r6} /* Read task's dedicated PAC key from stack. */ + msr PAC_KEY_P_3, r3 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_2, r4 + msr PAC_KEY_P_1, r5 + msr PAC_KEY_P_0, r6 + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + ldmia r2!, {r0, r3, lr} http://files.iar.com/ftp/pub/box/bxarm-9.60.3.deb/* Read from stack - r0 = xSecureContext, r3 = PSPLIM and LR restored. */ + msr psplim, r3 /* Restore the PSPLIM register value for the task. */ + ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + str r0, [r3] /* Restore the task's xSecureContext. */ + cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */ + + restore_s_context: + push {r1-r3, lr} + bl SecureContext_LoadContext /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r1-r3, lr} + + restore_ns_context: + mov r0, lr /* r0 = LR (EXC_RETURN). */ + lsls r0, r0, #25 /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bmi restore_context_done /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + + restore_general_regs: + ldmia r2!, {r4-r11} /* Restore the registers that are not automatically restored. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + it eq + vldmiaeq r2!, {s16-s31} /* Restore the additional FP context registers which are not restored automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + + restore_context_done: + msr psp, r2 /* Remember the new top of stack for the task. */ + bx lr + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + +SVC_Handler: + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + + ldr r1, [r0, #24] + ldrb r2, [r1, #-2] + cmp r2, #NUM_SYSTEM_CALLS + blt syscall_enter + cmp r2, #104 /* portSVC_SYSTEM_CALL_EXIT. */ + beq syscall_exit + b vPortSVCHandler_C + + syscall_enter: + mov r1, lr + b vSystemCallEnter + + syscall_exit: + mov r1, lr + b vSystemCallExit + +#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +SVC_Handler: + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + b vPortSVCHandler_C + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +vPortFreeSecureContext: + /* r0 = uint32_t *pulTCB. */ + ldr r2, [r0] /* The first item in the TCB is the top of the stack. */ + ldr r1, [r2] /* The first item on the stack is the task's xSecureContext. */ + cmp r1, #0 /* Raise svc if task's xSecureContext is not NULL. */ + it ne + svcne 101 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 101. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + + END diff --git a/portable/IAR/ARM_CM52/non_secure/portmacro.h b/portable/IAR/ARM_CM52/non_secure/portmacro.h new file mode 100644 index 000000000..19de84eb8 --- /dev/null +++ b/portable/IAR/ARM_CM52/non_secure/portmacro.h @@ -0,0 +1,87 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (c) 2025 Arm Technology (China) Co., Ltd.All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_MVE + #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE. +#endif /* configENABLE_MVE */ +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M52" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portARMV8M_MINOR_VERSION 1 +#define portDONT_DISCARD __root +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ +#pragma diag_suppress=Be006 +#pragma diag_suppress=Pa082 +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/IAR/ARM_CM52/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM52/non_secure/portmacrocommon.h new file mode 100644 index 000000000..f373bcad5 --- /dev/null +++ b/portable/IAR/ARM_CM52/non_secure/portmacrocommon.h @@ -0,0 +1,582 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACROCOMMON_H +#define PORTMACROCOMMON_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. +#endif /* configENABLE_FPU */ + +#ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. +#endif /* configENABLE_MPU */ + +#ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. +#endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() +#define portINLINE __inline +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif +#define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ +extern BaseType_t xPortIsInsideInterrupt( void ); + +extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + +extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; +extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + +extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; +extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + +#if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_PAC == 1 ) + + /** + * @brief Generates 128-bit task's random PAC key. + * + * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be + * filled with a 128-bit random number. + */ + void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); + +#endif /* configENABLE_PAC */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ +#if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) +#else + #define portPRIVILEGE_BIT ( 0x0UL ) +#endif /* configENABLE_MPU */ + +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ +#define portPRIVILEGED_FLASH_REGION ( 0UL ) +#define portUNPRIVILEGED_FLASH_REGION ( 1UL ) +#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) +#define portPRIVILEGED_RAM_REGION ( 3UL ) +#define portSTACK_REGION ( 4UL ) +#define portFIRST_CONFIGURABLE_REGION ( 5UL ) +#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) +#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) +#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ +#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ +#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ +#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ +#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ +#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ +#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ +#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) +#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) +#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + +#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) +#define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) +#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) +#define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + +#define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + #ifndef configSYSTEM_CALL_STACK_SIZE + #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. + #endif + + /** + * @brief System call stack. + */ + typedef struct SYSTEM_CALL_STACK_INFO + { + uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; + uint32_t * pulSystemCallStack; + uint32_t * pulSystemCallStackLimit; + uint32_t * pulTaskStack; + uint32_t ulLinkRegisterAtSystemCallEntry; + uint32_t ulStackLimitRegisterAtSystemCallEntry; + } xSYSTEM_CALL_STACK_INFO; + + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + /** + * @brief MPU settings as stored in the TCB. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><-----------><----> + * 16 17 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 71 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 17 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 55 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | | | PC, xPSR | EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><-----------><----> + * 16 17 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 70 + + #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + /* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 17 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 54 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+------------------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +----------+-----------------+------------------------------+------------+-----+ + * + * <---------><----------------><------------------------------><-----------><----> + * 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 38 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+----------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | PC, xPSR | EXC_RETURN | | | + * +----------+-----------------+----------------------+------------+-----+ + * + * <---------><----------------><----------------------><-----------><----> + * 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 37 + + #else /* #if( configENABLE_TRUSTZONE == 1 ) */ + + /* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) + + /* Size of an Access Control List (ACL) entry in bits. */ + #define portACL_ENTRY_SIZE_BITS ( 32U ) + + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + uint32_t ulContext[ MAX_CONTEXT_SIZE ]; + uint32_t ulTaskFlags; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo; + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ]; + #endif + #endif + } xMPU_SETTINGS; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Validate priority of ISRs that are allowed to call FreeRTOS + * system calls. + */ +#if ( configASSERT_DEFINED == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif +#endif + +/** + * @brief SVC numbers. + */ +#define portSVC_ALLOCATE_SECURE_CONTEXT 100 +#define portSVC_FREE_SECURE_CONTEXT 101 +#define portSVC_START_SCHEDULER 102 +#define portSVC_RAISE_PRIVILEGE 103 +#define portSVC_SYSTEM_CALL_EXIT 104 +#define portSVC_YIELD 105 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) +#endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() +#else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + extern BaseType_t xPortIsTaskPrivileged( void ); + +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACROCOMMON_H */ diff --git a/portable/IAR/ARM_CM52/secure/secure_context.c b/portable/IAR/ARM_CM52/secure/secure_context.c new file mode 100644 index 000000000..3aa335e63 --- /dev/null +++ b/portable/IAR/ARM_CM52/secure/secure_context.c @@ -0,0 +1,354 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Secure context includes. */ +#include "secure_context.h" + +/* Secure heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief CONTROL value for privileged tasks. + * + * Bit[0] - 0 --> Thread mode is privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_PRIVILEGED 0x02 + +/** + * @brief CONTROL value for un-privileged tasks. + * + * Bit[0] - 1 --> Thread mode is un-privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03 + +/** + * @brief Size of stack seal values in bytes. + */ +#define securecontextSTACK_SEAL_SIZE 8 + +/** + * @brief Stack seal value as recommended by ARM. + */ +#define securecontextSTACK_SEAL_VALUE 0xFEF5EDA5 + +/** + * @brief Maximum number of secure contexts. + */ +#ifndef secureconfigMAX_SECURE_CONTEXTS + #define secureconfigMAX_SECURE_CONTEXTS 8UL +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Pre-allocated array of secure contexts. + */ +SecureContext_t xSecureContexts[ secureconfigMAX_SECURE_CONTEXTS ]; +/*-----------------------------------------------------------*/ + +/** + * @brief Get a free secure context for a task from the secure context pool (xSecureContexts). + * + * This function ensures that only one secure context is allocated for a task. + * + * @param[in] pvTaskHandle The task handle for which the secure context is allocated. + * + * @return Index of a free secure context in the xSecureContexts array. + */ +static uint32_t ulGetSecureContext( void * pvTaskHandle ); + +/** + * @brief Return the secure context to the secure context pool (xSecureContexts). + * + * @param[in] ulSecureContextIndex Index of the context in the xSecureContexts array. + */ +static void vReturnSecureContext( uint32_t ulSecureContextIndex ); + +/* These are implemented in assembly. */ +extern void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ); +extern void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ); +/*-----------------------------------------------------------*/ + +static uint32_t ulGetSecureContext( void * pvTaskHandle ) +{ + /* Start with invalid index. */ + uint32_t i, ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + if( ( xSecureContexts[ i ].pucCurrentStackPointer == NULL ) && + ( xSecureContexts[ i ].pucStackLimit == NULL ) && + ( xSecureContexts[ i ].pucStackStart == NULL ) && + ( xSecureContexts[ i ].pvTaskHandle == NULL ) && + ( ulSecureContextIndex == secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = i; + } + else if( xSecureContexts[ i ].pvTaskHandle == pvTaskHandle ) + { + /* A task can only have one secure context. Do not allocate a second + * context for the same task. */ + ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + break; + } + } + + return ulSecureContextIndex; +} +/*-----------------------------------------------------------*/ + +static void vReturnSecureContext( uint32_t ulSecureContextIndex ) +{ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackStart = NULL; + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = NULL; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) +{ + uint32_t ulIPSR, i; + static uint32_t ulSecureContextsInitialized = 0; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ( ulIPSR != 0 ) && ( ulSecureContextsInitialized == 0 ) ) + { + /* Ensure to initialize secure contexts only once. */ + ulSecureContextsInitialized = 1; + + /* No stack for thread mode until a task's context is loaded. */ + secureportSET_PSPLIM( securecontextNO_STACK ); + secureportSET_PSP( securecontextNO_STACK ); + + /* Initialize all secure contexts. */ + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + xSecureContexts[ i ].pucCurrentStackPointer = NULL; + xSecureContexts[ i ].pucStackLimit = NULL; + xSecureContexts[ i ].pucStackStart = NULL; + xSecureContexts[ i ].pvTaskHandle = NULL; + } + + #if ( configENABLE_MPU == 1 ) + { + /* Configure thread mode to use PSP and to be unprivileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); + } + #else /* configENABLE_MPU */ + { + /* Configure thread mode to use PSP and to be privileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); + } + #endif /* configENABLE_MPU */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ) +#else /* configENABLE_MPU */ + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ) +#endif /* configENABLE_MPU */ +{ + uint8_t * pucStackMemory = NULL; + uint8_t * pucStackLimit; + uint32_t ulIPSR, ulSecureContextIndex; + SecureContextHandle_t xSecureContextHandle = securecontextINVALID_CONTEXT_ID; + + #if ( configENABLE_MPU == 1 ) + uint32_t * pulCurrentStackPointer = NULL; + #endif /* configENABLE_MPU */ + + /* Read the Interrupt Program Status Register (IPSR) and Process Stack Limit + * Register (PSPLIM) value. */ + secureportREAD_IPSR( ulIPSR ); + secureportREAD_PSPLIM( pucStackLimit ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. + * Also do nothing, if a secure context us already loaded. PSPLIM is set to + * securecontextNO_STACK when no secure context is loaded. */ + if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) ) + { + /* Obtain a free secure context. */ + ulSecureContextIndex = ulGetSecureContext( pvTaskHandle ); + + /* Were we able to get a free context? */ + if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS ) + { + /* Allocate the stack space. */ + pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + + if( pucStackMemory != NULL ) + { + /* Since stack grows down, the starting point will be the last + * location. Note that this location is next to the last + * allocated byte for stack (excluding the space for seal values) + * because the hardware decrements the stack pointer before + * writing i.e. if stack pointer is 0x2, a push operation will + * decrement the stack pointer to 0x1 and then write at 0x1. */ + xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize; + + /* Seal the created secure process stack. */ + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; + + /* The stack cannot go beyond this location. This value is + * programmed in the PSPLIM register on context switch.*/ + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = pucStackMemory; + + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle; + + #if ( configENABLE_MPU == 1 ) + { + /* Store the correct CONTROL value for the task on the stack. + * This value is programmed in the CONTROL register on + * context switch. */ + pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; + pulCurrentStackPointer--; + + if( ulIsTaskPrivileged ) + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; + } + else + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; + } + + /* Store the current stack pointer. This value is programmed in + * the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + } + #else /* configENABLE_MPU */ + { + /* Current SP is set to the starting of the stack. This + * value programmed in the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + } + #endif /* configENABLE_MPU */ + + /* Ensure to never return 0 as a valid context handle. */ + xSecureContextHandle = ulSecureContextIndex + 1UL; + } + } + } + + return xSecureContextHandle; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) +{ + uint32_t ulIPSR, ulSecureContextIndex; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* Only free if a valid context handle is passed. */ + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + /* Ensure that the secure context being deleted is associated with + * the task. */ + if( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) + { + /* Free the stack space. */ + vPortFree( xSecureContexts[ ulSecureContextIndex ].pucStackLimit ); + + /* Return the secure context back to the free secure contexts pool. */ + vReturnSecureContext( ulSecureContextIndex ); + } + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that no secure context is loaded and the task is loading it's + * own context. */ + if( ( pucStackLimit == securecontextNO_STACK ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_LoadContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that task's context is loaded and the task is saving it's own + * context. */ + if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_SaveContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/ARM_CM52/secure/secure_context.h b/portable/IAR/ARM_CM52/secure/secure_context.h new file mode 100644 index 000000000..e36a8e430 --- /dev/null +++ b/portable/IAR/ARM_CM52/secure/secure_context.h @@ -0,0 +1,138 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_CONTEXT_H__ +#define __SECURE_CONTEXT_H__ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" + +/** + * @brief PSP value when no secure context is loaded. + */ +#define securecontextNO_STACK 0x0 + +/** + * @brief Invalid context ID. + */ +#define securecontextINVALID_CONTEXT_ID 0UL +/*-----------------------------------------------------------*/ + +/** + * @brief Structure to represent a secure context. + * + * @note Since stack grows down, pucStackStart is the highest address while + * pucStackLimit is the first address of the allocated memory. + */ +typedef struct SecureContext +{ + uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */ + uint8_t * pucStackLimit; /**< Last location of the stack memory (PSPLIM). */ + uint8_t * pucStackStart; /**< First location of the stack memory. */ + void * pvTaskHandle; /**< Task handle of the task this context is associated with. */ +} SecureContext_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Opaque handle for a secure context. + */ +typedef uint32_t SecureContextHandle_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Initializes the secure context management system. + * + * PSP is set to NULL and therefore a task must allocate and load a context + * before calling any secure side function in the thread mode. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureContext_Init( void ); + +/** + * @brief Allocates a context on the secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] ulSecureStackSize Size of the stack to allocate on secure side. + * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise. + * + * @return Opaque context handle if context is successfully allocated, NULL + * otherwise. + */ +#if ( configENABLE_MPU == 1 ) + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ); +#else /* configENABLE_MPU */ + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ); +#endif /* configENABLE_MPU */ + +/** + * @brief Frees the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the + * context to be freed. + */ +void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); + +/** + * @brief Loads the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be loaded. + */ +void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); + +/** + * @brief Saves the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be saved. + */ +void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); + +#endif /* __SECURE_CONTEXT_H__ */ diff --git a/portable/IAR/ARM_CM52/secure/secure_context_port_asm.s b/portable/IAR/ARM_CM52/secure/secure_context_port_asm.s new file mode 100644 index 000000000..27a8f3933 --- /dev/null +++ b/portable/IAR/ARM_CM52/secure/secure_context_port_asm.s @@ -0,0 +1,86 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + SECTION .text:CODE:NOROOT(2) + THUMB + +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" + + PUBLIC SecureContext_LoadContextAsm + PUBLIC SecureContext_SaveContextAsm +/*-----------------------------------------------------------*/ + +SecureContext_LoadContextAsm: + /* pxSecureContext value is in r0. */ + mrs r1, ipsr /* r1 = IPSR. */ + cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */ + ldmia r0!, {r1, r2} /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */ + +#if ( configENABLE_MPU == 1 ) + ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL. */ + msr control, r3 /* CONTROL = r3. */ +#endif /* configENABLE_MPU */ + + msr psplim, r2 /* PSPLIM = r2. */ + msr psp, r1 /* PSP = r1. */ + + load_ctx_therad_mode: + bx lr +/*-----------------------------------------------------------*/ + +SecureContext_SaveContextAsm: + /* pxSecureContext value is in r0. */ + mrs r1, ipsr /* r1 = IPSR. */ + cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */ + mrs r1, psp /* r1 = PSP. */ + +#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + vstmdb r1!, {s0} /* Trigger the deferred stacking of FPU registers. */ + vldmia r1!, {s0} /* Nullify the effect of the previous statement. */ +#endif /* configENABLE_FPU || configENABLE_MVE */ + +#if ( configENABLE_MPU == 1 ) + mrs r2, control /* r2 = CONTROL. */ + stmdb r1!, {r2} /* Store CONTROL value on the stack. */ +#endif /* configENABLE_MPU */ + + str r1, [r0] /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */ + movs r1, #0 /* r1 = securecontextNO_STACK. */ + msr psplim, r1 /* PSPLIM = securecontextNO_STACK. */ + msr psp, r1 /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */ + + save_ctx_therad_mode: + bx lr +/*-----------------------------------------------------------*/ + + END diff --git a/portable/IAR/ARM_CM52/secure/secure_heap.c b/portable/IAR/ARM_CM52/secure/secure_heap.c new file mode 100644 index 000000000..896b53e2d --- /dev/null +++ b/portable/IAR/ARM_CM52/secure/secure_heap.c @@ -0,0 +1,485 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Configuration includes. */ +#include "FreeRTOSConfig.h" + +/* Secure context heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Total heap size. + */ +#ifndef secureconfigTOTAL_HEAP_SIZE + #define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) ) +#endif + +/* No test marker by default. */ +#ifndef mtCOVERAGE_TEST_MARKER + #define mtCOVERAGE_TEST_MARKER() +#endif + +/* No tracing by default. */ +#ifndef traceMALLOC + #define traceMALLOC( pvReturn, xWantedSize ) +#endif + +/* No tracing by default. */ +#ifndef traceFREE + #define traceFREE( pv, xBlockSize ) +#endif + +/* Block sizes must not get too small. */ +#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) ) + +/* Assumes 8bit bytes! */ +#define secureheapBITS_PER_BYTE ( ( size_t ) 8 ) + +/* Max value that fits in a size_t type. */ +#define secureheapSIZE_MAX ( ~( ( size_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define secureheapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) ) + +/* MSB of the xBlockSize member of an BlockLink_t structure is used to track + * the allocation status of a block. When MSB of the xBlockSize member of + * an BlockLink_t structure is set then the block belongs to the application. + * When the bit is free the block is still part of the free heap space. */ +#define secureheapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) ) +#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 ) +#define secureheapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 ) +#define secureheapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK ) +#define secureheapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK ) +/*-----------------------------------------------------------*/ + +/* Allocate the memory for the heap. */ +#if ( configAPPLICATION_ALLOCATED_HEAP == 1 ) + +/* The application writer has already defined the array used for the RTOS +* heap - probably so it can be placed in a special segment or address. */ + extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#else /* configAPPLICATION_ALLOCATED_HEAP */ + static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#endif /* configAPPLICATION_ALLOCATED_HEAP */ + +/** + * @brief The linked list structure. + * + * This is used to link free blocks in order of their memory address. + */ +typedef struct A_BLOCK_LINK +{ + struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */ + size_t xBlockSize; /**< The size of the free block. */ +} BlockLink_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Called automatically to setup the required heap structures the first + * time pvPortMalloc() is called. + */ +static void prvHeapInit( void ); + +/** + * @brief Inserts a block of memory that is being freed into the correct + * position in the list of free memory blocks. + * + * The block being freed will be merged with the block in front it and/or the + * block behind it if the memory blocks are adjacent to each other. + * + * @param[in] pxBlockToInsert The block being freed. + */ +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ); +/*-----------------------------------------------------------*/ + +/** + * @brief The size of the structure placed at the beginning of each allocated + * memory block must by correctly byte aligned. + */ +static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + +/** + * @brief Create a couple of list links to mark the start and end of the list. + */ +static BlockLink_t xStart; +static BlockLink_t * pxEnd = NULL; + +/** + * @brief Keeps track of the number of free bytes remaining, but says nothing + * about fragmentation. + */ +static size_t xFreeBytesRemaining = 0U; +static size_t xMinimumEverFreeBytesRemaining = 0U; + +/*-----------------------------------------------------------*/ + +static void prvHeapInit( void ) +{ + BlockLink_t * pxFirstFreeBlock; + uint8_t * pucAlignedHeap; + size_t uxAddress; + size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE; + + /* Ensure the heap starts on a correctly aligned boundary. */ + uxAddress = ( size_t ) ucHeap; + + if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 ) + { + uxAddress += ( secureportBYTE_ALIGNMENT - 1 ); + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; + } + + pucAlignedHeap = ( uint8_t * ) uxAddress; + + /* xStart is used to hold a pointer to the first item in the list of free + * blocks. The void cast is used to prevent compiler warnings. */ + xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; + xStart.xBlockSize = ( size_t ) 0; + + /* pxEnd is used to mark the end of the list of free blocks and is inserted + * at the end of the heap space. */ + uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; + uxAddress -= xHeapStructSize; + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + pxEnd = ( void * ) uxAddress; + pxEnd->xBlockSize = 0; + pxEnd->pxNextFreeBlock = NULL; + + /* To start with there is a single free block that is sized to take up the + * entire heap space, minus the space taken by pxEnd. */ + pxFirstFreeBlock = ( void * ) pucAlignedHeap; + pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; + pxFirstFreeBlock->pxNextFreeBlock = pxEnd; + + /* Only one block exists - and it covers the entire usable heap space. */ + xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; +} +/*-----------------------------------------------------------*/ + +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) +{ + BlockLink_t * pxIterator; + uint8_t * puc; + + /* Iterate through the list until a block is found that has a higher address + * than the block being inserted. */ + for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) + { + /* Nothing to do here, just iterate to the right position. */ + } + + /* Do the block being inserted, and the block it is being inserted after + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxIterator; + + if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) + { + pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; + pxBlockToInsert = pxIterator; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Do the block being inserted, and the block it is being inserted before + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxBlockToInsert; + + if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) + { + if( pxIterator->pxNextFreeBlock != pxEnd ) + { + /* Form one big block from the two blocks. */ + pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxEnd; + } + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; + } + + /* If the block being inserted plugged a gap, so was merged with the block + * before and the block after, then it's pxNextFreeBlock pointer will have + * already been set, and should not be set here as that would make it point + * to itself. */ + if( pxIterator != pxBlockToInsert ) + { + pxIterator->pxNextFreeBlock = pxBlockToInsert; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} +/*-----------------------------------------------------------*/ + +void * pvPortMalloc( size_t xWantedSize ) +{ + BlockLink_t * pxBlock; + BlockLink_t * pxPreviousBlock; + BlockLink_t * pxNewBlockLink; + void * pvReturn = NULL; + size_t xAdditionalRequiredSize; + size_t xAllocatedBlockSize = 0; + + /* If this is the first call to malloc then the heap will require + * initialisation to setup the list of free blocks. */ + if( pxEnd == NULL ) + { + prvHeapInit(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xWantedSize > 0 ) + { + /* The wanted size must be increased so it can contain a BlockLink_t + * structure in addition to the requested amount of bytes. */ + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 ) + { + xWantedSize += xHeapStructSize; + + /* Ensure that blocks are always aligned to the required number + * of bytes. */ + if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 ) + { + /* Byte alignment required. */ + xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ); + + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 ) + { + xWantedSize += xAdditionalRequiredSize; + } + else + { + xWantedSize = 0; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + xWantedSize = 0; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Check the requested block size is not so large that the top bit is set. + * The top bit of the block size member of the BlockLink_t structure is used + * to determine who owns the block - the application or the kernel, so it + * must be free. */ + if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 ) + { + if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) + { + /* Traverse the list from the start (lowest address) block until + * one of adequate size is found. */ + pxPreviousBlock = &xStart; + pxBlock = xStart.pxNextFreeBlock; + + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + { + pxPreviousBlock = pxBlock; + pxBlock = pxBlock->pxNextFreeBlock; + } + + /* If the end marker was reached then a block of adequate size was + * not found. */ + if( pxBlock != pxEnd ) + { + /* Return the memory space pointed to - jumping over the + * BlockLink_t structure at its start. */ + pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); + + /* This block is being returned for use so must be taken out + * of the list of free blocks. */ + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + + /* If the block is larger than required it can be split into + * two. */ + if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE ) + { + /* This block is to be split into two. Create a new + * block following the number of bytes requested. The void + * cast is used to prevent byte alignment warnings from the + * compiler. */ + pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); + secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + + /* Calculate the sizes of two blocks split from the single + * block. */ + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + pxBlock->xBlockSize = xWantedSize; + + /* Insert the new block into the list of free blocks. */ + pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock; + pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xFreeBytesRemaining -= pxBlock->xBlockSize; + + if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) + { + xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xAllocatedBlockSize = pxBlock->xBlockSize; + + /* The block is being returned - it is allocated and owned by + * the application and has no "next" block. */ + secureheapALLOCATE_BLOCK( pxBlock ); + pxBlock->pxNextFreeBlock = NULL; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceMALLOC( pvReturn, xAllocatedBlockSize ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xAllocatedBlockSize; + + #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) + { + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */ + + secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 ); + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void * pv ) +{ + uint8_t * puc = ( uint8_t * ) pv; + BlockLink_t * pxLink; + + if( pv != NULL ) + { + /* The memory being freed will have an BlockLink_t structure immediately + * before it. */ + puc -= xHeapStructSize; + + /* This casting is to keep the compiler from issuing warnings. */ + pxLink = ( void * ) puc; + + /* Check the block is actually allocated. */ + secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ); + secureportASSERT( pxLink->pxNextFreeBlock == NULL ); + + if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ) + { + if( pxLink->pxNextFreeBlock == NULL ) + { + /* The block is being returned to the heap - it is no longer + * allocated. */ + secureheapFREE_BLOCK( pxLink ); + + secureportDISABLE_NON_SECURE_INTERRUPTS(); + { + /* Add this block to the list of free blocks. */ + xFreeBytesRemaining += pxLink->xBlockSize; + traceFREE( pv, pxLink->xBlockSize ); + prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); + } + secureportENABLE_NON_SECURE_INTERRUPTS(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } +} +/*-----------------------------------------------------------*/ + +size_t xPortGetFreeHeapSize( void ) +{ + return xFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +size_t xPortGetMinimumEverFreeHeapSize( void ) +{ + return xMinimumEverFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/ARM_CM52/secure/secure_heap.h b/portable/IAR/ARM_CM52/secure/secure_heap.h new file mode 100644 index 000000000..0e84a9d9d --- /dev/null +++ b/portable/IAR/ARM_CM52/secure/secure_heap.h @@ -0,0 +1,66 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_HEAP_H__ +#define __SECURE_HEAP_H__ + +/* Standard includes. */ +#include + +/** + * @brief Allocates memory from heap. + * + * @param[in] xWantedSize The size of the memory to be allocated. + * + * @return Pointer to the memory region if the allocation is successful, NULL + * otherwise. + */ +void * pvPortMalloc( size_t xWantedSize ); + +/** + * @brief Frees the previously allocated memory. + * + * @param[in] pv Pointer to the memory to be freed. + */ +void vPortFree( void * pv ); + +/** + * @brief Get the free heap size. + * + * @return Free heap size. + */ +size_t xPortGetFreeHeapSize( void ); + +/** + * @brief Get the minimum ever free heap size. + * + * @return Minimum ever free heap size. + */ +size_t xPortGetMinimumEverFreeHeapSize( void ); + +#endif /* __SECURE_HEAP_H__ */ diff --git a/portable/IAR/ARM_CM52/secure/secure_init.c b/portable/IAR/ARM_CM52/secure/secure_init.c new file mode 100644 index 000000000..c50d37668 --- /dev/null +++ b/portable/IAR/ARM_CM52/secure/secure_init.c @@ -0,0 +1,106 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Secure init includes. */ +#include "secure_init.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Constants required to manipulate the SCB. + */ +#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */ +#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL ) +#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS ) +#define secureinitSCB_AIRCR_PRIS_POS ( 14UL ) +#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS ) + +/** + * @brief Constants required to manipulate the FPU. + */ +#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define secureinitFPCCR_LSPENS_POS ( 29UL ) +#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS ) +#define secureinitFPCCR_TS_POS ( 26UL ) +#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS ) + +#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */ +#define secureinitNSACR_CP10_POS ( 10UL ) +#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS ) +#define secureinitNSACR_CP11_POS ( 11UL ) +#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS ) +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) | + ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) | + ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK ); + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is + * permitted. CP11 should be programmed to the same value as CP10. */ + *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK ); + + /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures + * that we can enable/disable lazy stacking in port.c file. */ + *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK ); + + /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP + * registers (S16-S31) are also pushed to stack on exception entry and + * restored on exception return. */ + *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK ); + } +} +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/ARM_CM52/secure/secure_init.h b/portable/IAR/ARM_CM52/secure/secure_init.h new file mode 100644 index 000000000..ebe04900f --- /dev/null +++ b/portable/IAR/ARM_CM52/secure/secure_init.h @@ -0,0 +1,54 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_INIT_H__ +#define __SECURE_INIT_H__ + +/** + * @brief De-prioritizes the non-secure exceptions. + * + * This is needed to ensure that the non-secure PendSV runs at the lowest + * priority. Context switch is done in the non-secure PendSV handler. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_DePrioritizeNSExceptions( void ); + +/** + * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access. + * + * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point + * Registers are not leaked to the non-secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_EnableNSFPUAccess( void ); + +#endif /* __SECURE_INIT_H__ */ diff --git a/portable/IAR/ARM_CM52/secure/secure_port_macros.h b/portable/IAR/ARM_CM52/secure/secure_port_macros.h new file mode 100644 index 000000000..a70da2c65 --- /dev/null +++ b/portable/IAR/ARM_CM52/secure/secure_port_macros.h @@ -0,0 +1,140 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_PORT_MACROS_H__ +#define __SECURE_PORT_MACROS_H__ + +/** + * @brief Byte alignment requirements. + */ +#define secureportBYTE_ALIGNMENT 8 +#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 ) + +/** + * @brief Macro to declare a function as non-secure callable. + */ +#if defined( __IAR_SYSTEMS_ICC__ ) + #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry __root +#else + #define secureportNON_SECURE_CALLABLE __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) ) +#endif + +/** + * @brief Set the secure PRIMASK value. + */ +#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Set the non-secure PRIMASK value. + */ +#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Read the PSP value in the given variable. + */ +#define secureportREAD_PSP( pucOutCurrentStackPointer ) \ + __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) ) + +/** + * @brief Set the PSP to the given value. + */ +#define secureportSET_PSP( pucCurrentStackPointer ) \ + __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) ) + +/** + * @brief Read the PSPLIM value in the given variable. + */ +#define secureportREAD_PSPLIM( pucOutStackLimit ) \ + __asm volatile ( "mrs %0, psplim" : "=r" ( pucOutStackLimit ) ) + +/** + * @brief Set the PSPLIM to the given value. + */ +#define secureportSET_PSPLIM( pucStackLimit ) \ + __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) ) + +/** + * @brief Set the NonSecure MSP to the given value. + */ +#define secureportSET_MSP_NS( pucMainStackPointer ) \ + __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) ) + +/** + * @brief Set the CONTROL register to the given value. + */ +#define secureportSET_CONTROL( ulControl ) \ + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" ) + +/** + * @brief Read the Interrupt Program Status Register (IPSR) value in the given + * variable. + */ +#define secureportREAD_IPSR( ulIPSR ) \ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) ) + +/** + * @brief PRIMASK value to enable interrupts. + */ +#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0 + +/** + * @brief PRIMASK value to disable interrupts. + */ +#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1 + +/** + * @brief Disable secure interrupts. + */ +#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Disable non-secure interrupts. + * + * This effectively disables context switches. + */ +#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Enable non-secure interrupts. + */ +#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL ) + +/** + * @brief Assert definition. + */ +#define secureportASSERT( x ) \ + if( ( x ) == 0 ) \ + { \ + secureportDISABLE_SECURE_INTERRUPTS(); \ + secureportDISABLE_NON_SECURE_INTERRUPTS(); \ + for( ; ; ) {; } \ + } + +#endif /* __SECURE_PORT_MACROS_H__ */ diff --git a/portable/IAR/ARM_CM52_NTZ/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM52_NTZ/non_secure/mpu_wrappers_v2_asm.S new file mode 100644 index 000000000..d2cb78e92 --- /dev/null +++ b/portable/IAR/ARM_CM52_NTZ/non_secure/mpu_wrappers_v2_asm.S @@ -0,0 +1,1242 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + + SECTION freertos_system_calls:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +#include "FreeRTOSConfig.h" +#include "mpu_syscall_numbers.h" + +#ifndef configUSE_MPU_WRAPPERS_V1 + #define configUSE_MPU_WRAPPERS_V1 0 +#endif + +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + PUBLIC MPU_xTaskDelayUntil +MPU_xTaskDelayUntil: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskDelayUntil_Unpriv + MPU_xTaskDelayUntil_Priv: + b MPU_xTaskDelayUntilImpl + MPU_xTaskDelayUntil_Unpriv: + svc #SYSTEM_CALL_xTaskDelayUntil +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskAbortDelay +MPU_xTaskAbortDelay: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskAbortDelay_Unpriv + MPU_xTaskAbortDelay_Priv: + b MPU_xTaskAbortDelayImpl + MPU_xTaskAbortDelay_Unpriv: + svc #SYSTEM_CALL_xTaskAbortDelay +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskDelay +MPU_vTaskDelay: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskDelay_Unpriv + MPU_vTaskDelay_Priv: + b MPU_vTaskDelayImpl + MPU_vTaskDelay_Unpriv: + svc #SYSTEM_CALL_vTaskDelay +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskPriorityGet +MPU_uxTaskPriorityGet: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskPriorityGet_Unpriv + MPU_uxTaskPriorityGet_Priv: + b MPU_uxTaskPriorityGetImpl + MPU_uxTaskPriorityGet_Unpriv: + svc #SYSTEM_CALL_uxTaskPriorityGet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_eTaskGetState +MPU_eTaskGetState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_eTaskGetState_Unpriv + MPU_eTaskGetState_Priv: + b MPU_eTaskGetStateImpl + MPU_eTaskGetState_Unpriv: + svc #SYSTEM_CALL_eTaskGetState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskGetInfo +MPU_vTaskGetInfo: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskGetInfo_Unpriv + MPU_vTaskGetInfo_Priv: + b MPU_vTaskGetInfoImpl + MPU_vTaskGetInfo_Unpriv: + svc #SYSTEM_CALL_vTaskGetInfo +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetIdleTaskHandle +MPU_xTaskGetIdleTaskHandle: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetIdleTaskHandle_Unpriv + MPU_xTaskGetIdleTaskHandle_Priv: + b MPU_xTaskGetIdleTaskHandleImpl + MPU_xTaskGetIdleTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTaskGetIdleTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSuspend +MPU_vTaskSuspend: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSuspend_Unpriv + MPU_vTaskSuspend_Priv: + b MPU_vTaskSuspendImpl + MPU_vTaskSuspend_Unpriv: + svc #SYSTEM_CALL_vTaskSuspend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskResume +MPU_vTaskResume: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskResume_Unpriv + MPU_vTaskResume_Priv: + b MPU_vTaskResumeImpl + MPU_vTaskResume_Unpriv: + svc #SYSTEM_CALL_vTaskResume +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetTickCount +MPU_xTaskGetTickCount: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetTickCount_Unpriv + MPU_xTaskGetTickCount_Priv: + b MPU_xTaskGetTickCountImpl + MPU_xTaskGetTickCount_Unpriv: + svc #SYSTEM_CALL_xTaskGetTickCount +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetNumberOfTasks +MPU_uxTaskGetNumberOfTasks: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetNumberOfTasks_Unpriv + MPU_uxTaskGetNumberOfTasks_Priv: + b MPU_uxTaskGetNumberOfTasksImpl + MPU_uxTaskGetNumberOfTasks_Unpriv: + svc #SYSTEM_CALL_uxTaskGetNumberOfTasks +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetRunTimeCounter +MPU_ulTaskGetRunTimeCounter: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetRunTimeCounter_Unpriv + MPU_ulTaskGetRunTimeCounter_Priv: + b MPU_ulTaskGetRunTimeCounterImpl + MPU_ulTaskGetRunTimeCounter_Unpriv: + svc #SYSTEM_CALL_ulTaskGetRunTimeCounter +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetRunTimePercent +MPU_ulTaskGetRunTimePercent: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetRunTimePercent_Unpriv + MPU_ulTaskGetRunTimePercent_Priv: + b MPU_ulTaskGetRunTimePercentImpl + MPU_ulTaskGetRunTimePercent_Unpriv: + svc #SYSTEM_CALL_ulTaskGetRunTimePercent +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetIdleRunTimePercent +MPU_ulTaskGetIdleRunTimePercent: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetIdleRunTimePercent_Unpriv + MPU_ulTaskGetIdleRunTimePercent_Priv: + b MPU_ulTaskGetIdleRunTimePercentImpl + MPU_ulTaskGetIdleRunTimePercent_Unpriv: + svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetIdleRunTimeCounter +MPU_ulTaskGetIdleRunTimeCounter: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv + MPU_ulTaskGetIdleRunTimeCounter_Priv: + b MPU_ulTaskGetIdleRunTimeCounterImpl + MPU_ulTaskGetIdleRunTimeCounter_Unpriv: + svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetApplicationTaskTag +MPU_vTaskSetApplicationTaskTag: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetApplicationTaskTag_Unpriv + MPU_vTaskSetApplicationTaskTag_Priv: + b MPU_vTaskSetApplicationTaskTagImpl + MPU_vTaskSetApplicationTaskTag_Unpriv: + svc #SYSTEM_CALL_vTaskSetApplicationTaskTag +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetApplicationTaskTag +MPU_xTaskGetApplicationTaskTag: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetApplicationTaskTag_Unpriv + MPU_xTaskGetApplicationTaskTag_Priv: + b MPU_xTaskGetApplicationTaskTagImpl + MPU_xTaskGetApplicationTaskTag_Unpriv: + svc #SYSTEM_CALL_xTaskGetApplicationTaskTag +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetThreadLocalStoragePointer +MPU_vTaskSetThreadLocalStoragePointer: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv + MPU_vTaskSetThreadLocalStoragePointer_Priv: + b MPU_vTaskSetThreadLocalStoragePointerImpl + MPU_vTaskSetThreadLocalStoragePointer_Unpriv: + svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pvTaskGetThreadLocalStoragePointer +MPU_pvTaskGetThreadLocalStoragePointer: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv + MPU_pvTaskGetThreadLocalStoragePointer_Priv: + b MPU_pvTaskGetThreadLocalStoragePointerImpl + MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: + svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetSystemState +MPU_uxTaskGetSystemState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetSystemState_Unpriv + MPU_uxTaskGetSystemState_Priv: + b MPU_uxTaskGetSystemStateImpl + MPU_uxTaskGetSystemState_Unpriv: + svc #SYSTEM_CALL_uxTaskGetSystemState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetStackHighWaterMark +MPU_uxTaskGetStackHighWaterMark: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetStackHighWaterMark_Unpriv + MPU_uxTaskGetStackHighWaterMark_Priv: + b MPU_uxTaskGetStackHighWaterMarkImpl + MPU_uxTaskGetStackHighWaterMark_Unpriv: + svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetStackHighWaterMark2 +MPU_uxTaskGetStackHighWaterMark2: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetStackHighWaterMark2_Unpriv + MPU_uxTaskGetStackHighWaterMark2_Priv: + b MPU_uxTaskGetStackHighWaterMark2Impl + MPU_uxTaskGetStackHighWaterMark2_Unpriv: + svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2 +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetCurrentTaskHandle +MPU_xTaskGetCurrentTaskHandle: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetCurrentTaskHandle_Unpriv + MPU_xTaskGetCurrentTaskHandle_Priv: + b MPU_xTaskGetCurrentTaskHandleImpl + MPU_xTaskGetCurrentTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetSchedulerState +MPU_xTaskGetSchedulerState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetSchedulerState_Unpriv + MPU_xTaskGetSchedulerState_Priv: + b MPU_xTaskGetSchedulerStateImpl + MPU_xTaskGetSchedulerState_Unpriv: + svc #SYSTEM_CALL_xTaskGetSchedulerState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetTimeOutState +MPU_vTaskSetTimeOutState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetTimeOutState_Unpriv + MPU_vTaskSetTimeOutState_Priv: + b MPU_vTaskSetTimeOutStateImpl + MPU_vTaskSetTimeOutState_Unpriv: + svc #SYSTEM_CALL_vTaskSetTimeOutState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskCheckForTimeOut +MPU_xTaskCheckForTimeOut: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskCheckForTimeOut_Unpriv + MPU_xTaskCheckForTimeOut_Priv: + b MPU_xTaskCheckForTimeOutImpl + MPU_xTaskCheckForTimeOut_Unpriv: + svc #SYSTEM_CALL_xTaskCheckForTimeOut +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyEntry +MPU_xTaskGenericNotifyEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotify_Unpriv + MPU_xTaskGenericNotify_Priv: + b MPU_xTaskGenericNotifyImpl + MPU_xTaskGenericNotify_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotify +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyWaitEntry +MPU_xTaskGenericNotifyWaitEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotifyWait_Unpriv + MPU_xTaskGenericNotifyWait_Priv: + b MPU_xTaskGenericNotifyWaitImpl + MPU_xTaskGenericNotifyWait_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotifyWait +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGenericNotifyTake +MPU_ulTaskGenericNotifyTake: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGenericNotifyTake_Unpriv + MPU_ulTaskGenericNotifyTake_Priv: + b MPU_ulTaskGenericNotifyTakeImpl + MPU_ulTaskGenericNotifyTake_Unpriv: + svc #SYSTEM_CALL_ulTaskGenericNotifyTake +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyStateClear +MPU_xTaskGenericNotifyStateClear: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotifyStateClear_Unpriv + MPU_xTaskGenericNotifyStateClear_Priv: + b MPU_xTaskGenericNotifyStateClearImpl + MPU_xTaskGenericNotifyStateClear_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotifyStateClear +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGenericNotifyValueClear +MPU_ulTaskGenericNotifyValueClear: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGenericNotifyValueClear_Unpriv + MPU_ulTaskGenericNotifyValueClear_Priv: + b MPU_ulTaskGenericNotifyValueClearImpl + MPU_ulTaskGenericNotifyValueClear_Unpriv: + svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGenericSend +MPU_xQueueGenericSend: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGenericSend_Unpriv + MPU_xQueueGenericSend_Priv: + b MPU_xQueueGenericSendImpl + MPU_xQueueGenericSend_Unpriv: + svc #SYSTEM_CALL_xQueueGenericSend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxQueueMessagesWaiting +MPU_uxQueueMessagesWaiting: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxQueueMessagesWaiting_Unpriv + MPU_uxQueueMessagesWaiting_Priv: + b MPU_uxQueueMessagesWaitingImpl + MPU_uxQueueMessagesWaiting_Unpriv: + svc #SYSTEM_CALL_uxQueueMessagesWaiting +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxQueueSpacesAvailable +MPU_uxQueueSpacesAvailable: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxQueueSpacesAvailable_Unpriv + MPU_uxQueueSpacesAvailable_Priv: + b MPU_uxQueueSpacesAvailableImpl + MPU_uxQueueSpacesAvailable_Unpriv: + svc #SYSTEM_CALL_uxQueueSpacesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueReceive +MPU_xQueueReceive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueReceive_Unpriv + MPU_xQueueReceive_Priv: + b MPU_xQueueReceiveImpl + MPU_xQueueReceive_Unpriv: + svc #SYSTEM_CALL_xQueueReceive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueuePeek +MPU_xQueuePeek: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueuePeek_Unpriv + MPU_xQueuePeek_Priv: + b MPU_xQueuePeekImpl + MPU_xQueuePeek_Unpriv: + svc #SYSTEM_CALL_xQueuePeek +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueSemaphoreTake +MPU_xQueueSemaphoreTake: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueSemaphoreTake_Unpriv + MPU_xQueueSemaphoreTake_Priv: + b MPU_xQueueSemaphoreTakeImpl + MPU_xQueueSemaphoreTake_Unpriv: + svc #SYSTEM_CALL_xQueueSemaphoreTake +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGetMutexHolder +MPU_xQueueGetMutexHolder: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGetMutexHolder_Unpriv + MPU_xQueueGetMutexHolder_Priv: + b MPU_xQueueGetMutexHolderImpl + MPU_xQueueGetMutexHolder_Unpriv: + svc #SYSTEM_CALL_xQueueGetMutexHolder +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueTakeMutexRecursive +MPU_xQueueTakeMutexRecursive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueTakeMutexRecursive_Unpriv + MPU_xQueueTakeMutexRecursive_Priv: + b MPU_xQueueTakeMutexRecursiveImpl + MPU_xQueueTakeMutexRecursive_Unpriv: + svc #SYSTEM_CALL_xQueueTakeMutexRecursive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGiveMutexRecursive +MPU_xQueueGiveMutexRecursive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGiveMutexRecursive_Unpriv + MPU_xQueueGiveMutexRecursive_Priv: + b MPU_xQueueGiveMutexRecursiveImpl + MPU_xQueueGiveMutexRecursive_Unpriv: + svc #SYSTEM_CALL_xQueueGiveMutexRecursive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueSelectFromSet +MPU_xQueueSelectFromSet: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueSelectFromSet_Unpriv + MPU_xQueueSelectFromSet_Priv: + b MPU_xQueueSelectFromSetImpl + MPU_xQueueSelectFromSet_Unpriv: + svc #SYSTEM_CALL_xQueueSelectFromSet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueAddToSet +MPU_xQueueAddToSet: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueAddToSet_Unpriv + MPU_xQueueAddToSet_Priv: + b MPU_xQueueAddToSetImpl + MPU_xQueueAddToSet_Unpriv: + svc #SYSTEM_CALL_xQueueAddToSet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vQueueAddToRegistry +MPU_vQueueAddToRegistry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vQueueAddToRegistry_Unpriv + MPU_vQueueAddToRegistry_Priv: + b MPU_vQueueAddToRegistryImpl + MPU_vQueueAddToRegistry_Unpriv: + svc #SYSTEM_CALL_vQueueAddToRegistry +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vQueueUnregisterQueue +MPU_vQueueUnregisterQueue: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vQueueUnregisterQueue_Unpriv + MPU_vQueueUnregisterQueue_Priv: + b MPU_vQueueUnregisterQueueImpl + MPU_vQueueUnregisterQueue_Unpriv: + svc #SYSTEM_CALL_vQueueUnregisterQueue +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pcQueueGetName +MPU_pcQueueGetName: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pcQueueGetName_Unpriv + MPU_pcQueueGetName_Priv: + b MPU_pcQueueGetNameImpl + MPU_pcQueueGetName_Unpriv: + svc #SYSTEM_CALL_pcQueueGetName +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pvTimerGetTimerID +MPU_pvTimerGetTimerID: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pvTimerGetTimerID_Unpriv + MPU_pvTimerGetTimerID_Priv: + b MPU_pvTimerGetTimerIDImpl + MPU_pvTimerGetTimerID_Unpriv: + svc #SYSTEM_CALL_pvTimerGetTimerID +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTimerSetTimerID +MPU_vTimerSetTimerID: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTimerSetTimerID_Unpriv + MPU_vTimerSetTimerID_Priv: + b MPU_vTimerSetTimerIDImpl + MPU_vTimerSetTimerID_Unpriv: + svc #SYSTEM_CALL_vTimerSetTimerID +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerIsTimerActive +MPU_xTimerIsTimerActive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerIsTimerActive_Unpriv + MPU_xTimerIsTimerActive_Priv: + b MPU_xTimerIsTimerActiveImpl + MPU_xTimerIsTimerActive_Unpriv: + svc #SYSTEM_CALL_xTimerIsTimerActive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetTimerDaemonTaskHandle +MPU_xTimerGetTimerDaemonTaskHandle: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv + MPU_xTimerGetTimerDaemonTaskHandle_Priv: + b MPU_xTimerGetTimerDaemonTaskHandleImpl + MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGenericCommandFromTaskEntry +MPU_xTimerGenericCommandFromTaskEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGenericCommandFromTask_Unpriv + MPU_xTimerGenericCommandFromTask_Priv: + b MPU_xTimerGenericCommandFromTaskImpl + MPU_xTimerGenericCommandFromTask_Unpriv: + svc #SYSTEM_CALL_xTimerGenericCommandFromTask +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pcTimerGetName +MPU_pcTimerGetName: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pcTimerGetName_Unpriv + MPU_pcTimerGetName_Priv: + b MPU_pcTimerGetNameImpl + MPU_pcTimerGetName_Unpriv: + svc #SYSTEM_CALL_pcTimerGetName +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTimerSetReloadMode +MPU_vTimerSetReloadMode: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTimerSetReloadMode_Unpriv + MPU_vTimerSetReloadMode_Priv: + b MPU_vTimerSetReloadModeImpl + MPU_vTimerSetReloadMode_Unpriv: + svc #SYSTEM_CALL_vTimerSetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetReloadMode +MPU_xTimerGetReloadMode: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetReloadMode_Unpriv + MPU_xTimerGetReloadMode_Priv: + b MPU_xTimerGetReloadModeImpl + MPU_xTimerGetReloadMode_Unpriv: + svc #SYSTEM_CALL_xTimerGetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTimerGetReloadMode +MPU_uxTimerGetReloadMode: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTimerGetReloadMode_Unpriv + MPU_uxTimerGetReloadMode_Priv: + b MPU_uxTimerGetReloadModeImpl + MPU_uxTimerGetReloadMode_Unpriv: + svc #SYSTEM_CALL_uxTimerGetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetPeriod +MPU_xTimerGetPeriod: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetPeriod_Unpriv + MPU_xTimerGetPeriod_Priv: + b MPU_xTimerGetPeriodImpl + MPU_xTimerGetPeriod_Unpriv: + svc #SYSTEM_CALL_xTimerGetPeriod +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetExpiryTime +MPU_xTimerGetExpiryTime: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetExpiryTime_Unpriv + MPU_xTimerGetExpiryTime_Priv: + b MPU_xTimerGetExpiryTimeImpl + MPU_xTimerGetExpiryTime_Unpriv: + svc #SYSTEM_CALL_xTimerGetExpiryTime +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupWaitBitsEntry +MPU_xEventGroupWaitBitsEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupWaitBits_Unpriv + MPU_xEventGroupWaitBits_Priv: + b MPU_xEventGroupWaitBitsImpl + MPU_xEventGroupWaitBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupWaitBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupClearBits +MPU_xEventGroupClearBits: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupClearBits_Unpriv + MPU_xEventGroupClearBits_Priv: + b MPU_xEventGroupClearBitsImpl + MPU_xEventGroupClearBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupClearBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupSetBits +MPU_xEventGroupSetBits: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupSetBits_Unpriv + MPU_xEventGroupSetBits_Priv: + b MPU_xEventGroupSetBitsImpl + MPU_xEventGroupSetBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupSetBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupSync +MPU_xEventGroupSync: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupSync_Unpriv + MPU_xEventGroupSync_Priv: + b MPU_xEventGroupSyncImpl + MPU_xEventGroupSync_Unpriv: + svc #SYSTEM_CALL_xEventGroupSync +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxEventGroupGetNumber +MPU_uxEventGroupGetNumber: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxEventGroupGetNumber_Unpriv + MPU_uxEventGroupGetNumber_Priv: + b MPU_uxEventGroupGetNumberImpl + MPU_uxEventGroupGetNumber_Unpriv: + svc #SYSTEM_CALL_uxEventGroupGetNumber +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vEventGroupSetNumber +MPU_vEventGroupSetNumber: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vEventGroupSetNumber_Unpriv + MPU_vEventGroupSetNumber_Priv: + b MPU_vEventGroupSetNumberImpl + MPU_vEventGroupSetNumber_Unpriv: + svc #SYSTEM_CALL_vEventGroupSetNumber +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSend +MPU_xStreamBufferSend: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSend_Unpriv + MPU_xStreamBufferSend_Priv: + b MPU_xStreamBufferSendImpl + MPU_xStreamBufferSend_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferReceive +MPU_xStreamBufferReceive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferReceive_Unpriv + MPU_xStreamBufferReceive_Priv: + b MPU_xStreamBufferReceiveImpl + MPU_xStreamBufferReceive_Unpriv: + svc #SYSTEM_CALL_xStreamBufferReceive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferIsFull +MPU_xStreamBufferIsFull: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferIsFull_Unpriv + MPU_xStreamBufferIsFull_Priv: + b MPU_xStreamBufferIsFullImpl + MPU_xStreamBufferIsFull_Unpriv: + svc #SYSTEM_CALL_xStreamBufferIsFull +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferIsEmpty +MPU_xStreamBufferIsEmpty: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferIsEmpty_Unpriv + MPU_xStreamBufferIsEmpty_Priv: + b MPU_xStreamBufferIsEmptyImpl + MPU_xStreamBufferIsEmpty_Unpriv: + svc #SYSTEM_CALL_xStreamBufferIsEmpty +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSpacesAvailable +MPU_xStreamBufferSpacesAvailable: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSpacesAvailable_Unpriv + MPU_xStreamBufferSpacesAvailable_Priv: + b MPU_xStreamBufferSpacesAvailableImpl + MPU_xStreamBufferSpacesAvailable_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSpacesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferBytesAvailable +MPU_xStreamBufferBytesAvailable: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferBytesAvailable_Unpriv + MPU_xStreamBufferBytesAvailable_Priv: + b MPU_xStreamBufferBytesAvailableImpl + MPU_xStreamBufferBytesAvailable_Unpriv: + svc #SYSTEM_CALL_xStreamBufferBytesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSetTriggerLevel +MPU_xStreamBufferSetTriggerLevel: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSetTriggerLevel_Unpriv + MPU_xStreamBufferSetTriggerLevel_Priv: + b MPU_xStreamBufferSetTriggerLevelImpl + MPU_xStreamBufferSetTriggerLevel_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferNextMessageLengthBytes +MPU_xStreamBufferNextMessageLengthBytes: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv + MPU_xStreamBufferNextMessageLengthBytes_Priv: + b MPU_xStreamBufferNextMessageLengthBytesImpl + MPU_xStreamBufferNextMessageLengthBytes_Unpriv: + svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes +/*-----------------------------------------------------------*/ + +/* Default weak implementations in case one is not available from + * mpu_wrappers because of config options. */ + + PUBWEAK MPU_xTaskDelayUntilImpl +MPU_xTaskDelayUntilImpl: + b MPU_xTaskDelayUntilImpl + + PUBWEAK MPU_xTaskAbortDelayImpl +MPU_xTaskAbortDelayImpl: + b MPU_xTaskAbortDelayImpl + + PUBWEAK MPU_vTaskDelayImpl +MPU_vTaskDelayImpl: + b MPU_vTaskDelayImpl + + PUBWEAK MPU_uxTaskPriorityGetImpl +MPU_uxTaskPriorityGetImpl: + b MPU_uxTaskPriorityGetImpl + + PUBWEAK MPU_eTaskGetStateImpl +MPU_eTaskGetStateImpl: + b MPU_eTaskGetStateImpl + + PUBWEAK MPU_vTaskGetInfoImpl +MPU_vTaskGetInfoImpl: + b MPU_vTaskGetInfoImpl + + PUBWEAK MPU_xTaskGetIdleTaskHandleImpl +MPU_xTaskGetIdleTaskHandleImpl: + b MPU_xTaskGetIdleTaskHandleImpl + + PUBWEAK MPU_vTaskSuspendImpl +MPU_vTaskSuspendImpl: + b MPU_vTaskSuspendImpl + + PUBWEAK MPU_vTaskResumeImpl +MPU_vTaskResumeImpl: + b MPU_vTaskResumeImpl + + PUBWEAK MPU_xTaskGetTickCountImpl +MPU_xTaskGetTickCountImpl: + b MPU_xTaskGetTickCountImpl + + PUBWEAK MPU_uxTaskGetNumberOfTasksImpl +MPU_uxTaskGetNumberOfTasksImpl: + b MPU_uxTaskGetNumberOfTasksImpl + + PUBWEAK MPU_ulTaskGetRunTimeCounterImpl +MPU_ulTaskGetRunTimeCounterImpl: + b MPU_ulTaskGetRunTimeCounterImpl + + PUBWEAK MPU_ulTaskGetRunTimePercentImpl +MPU_ulTaskGetRunTimePercentImpl: + b MPU_ulTaskGetRunTimePercentImpl + + PUBWEAK MPU_ulTaskGetIdleRunTimePercentImpl +MPU_ulTaskGetIdleRunTimePercentImpl: + b MPU_ulTaskGetIdleRunTimePercentImpl + + PUBWEAK MPU_ulTaskGetIdleRunTimeCounterImpl +MPU_ulTaskGetIdleRunTimeCounterImpl: + b MPU_ulTaskGetIdleRunTimeCounterImpl + + PUBWEAK MPU_vTaskSetApplicationTaskTagImpl +MPU_vTaskSetApplicationTaskTagImpl: + b MPU_vTaskSetApplicationTaskTagImpl + + PUBWEAK MPU_xTaskGetApplicationTaskTagImpl +MPU_xTaskGetApplicationTaskTagImpl: + b MPU_xTaskGetApplicationTaskTagImpl + + PUBWEAK MPU_vTaskSetThreadLocalStoragePointerImpl +MPU_vTaskSetThreadLocalStoragePointerImpl: + b MPU_vTaskSetThreadLocalStoragePointerImpl + + PUBWEAK MPU_pvTaskGetThreadLocalStoragePointerImpl +MPU_pvTaskGetThreadLocalStoragePointerImpl: + b MPU_pvTaskGetThreadLocalStoragePointerImpl + + PUBWEAK MPU_uxTaskGetSystemStateImpl +MPU_uxTaskGetSystemStateImpl: + b MPU_uxTaskGetSystemStateImpl + + PUBWEAK MPU_uxTaskGetStackHighWaterMarkImpl +MPU_uxTaskGetStackHighWaterMarkImpl: + b MPU_uxTaskGetStackHighWaterMarkImpl + + PUBWEAK MPU_uxTaskGetStackHighWaterMark2Impl +MPU_uxTaskGetStackHighWaterMark2Impl: + b MPU_uxTaskGetStackHighWaterMark2Impl + + PUBWEAK MPU_xTaskGetCurrentTaskHandleImpl +MPU_xTaskGetCurrentTaskHandleImpl: + b MPU_xTaskGetCurrentTaskHandleImpl + + PUBWEAK MPU_xTaskGetSchedulerStateImpl +MPU_xTaskGetSchedulerStateImpl: + b MPU_xTaskGetSchedulerStateImpl + + PUBWEAK MPU_vTaskSetTimeOutStateImpl +MPU_vTaskSetTimeOutStateImpl: + b MPU_vTaskSetTimeOutStateImpl + + PUBWEAK MPU_xTaskCheckForTimeOutImpl +MPU_xTaskCheckForTimeOutImpl: + b MPU_xTaskCheckForTimeOutImpl + + PUBWEAK MPU_xTaskGenericNotifyImpl +MPU_xTaskGenericNotifyImpl: + b MPU_xTaskGenericNotifyImpl + + PUBWEAK MPU_xTaskGenericNotifyWaitImpl +MPU_xTaskGenericNotifyWaitImpl: + b MPU_xTaskGenericNotifyWaitImpl + + PUBWEAK MPU_ulTaskGenericNotifyTakeImpl +MPU_ulTaskGenericNotifyTakeImpl: + b MPU_ulTaskGenericNotifyTakeImpl + + PUBWEAK MPU_xTaskGenericNotifyStateClearImpl +MPU_xTaskGenericNotifyStateClearImpl: + b MPU_xTaskGenericNotifyStateClearImpl + + PUBWEAK MPU_ulTaskGenericNotifyValueClearImpl +MPU_ulTaskGenericNotifyValueClearImpl: + b MPU_ulTaskGenericNotifyValueClearImpl + + PUBWEAK MPU_xQueueGenericSendImpl +MPU_xQueueGenericSendImpl: + b MPU_xQueueGenericSendImpl + + PUBWEAK MPU_uxQueueMessagesWaitingImpl +MPU_uxQueueMessagesWaitingImpl: + b MPU_uxQueueMessagesWaitingImpl + + PUBWEAK MPU_uxQueueSpacesAvailableImpl +MPU_uxQueueSpacesAvailableImpl: + b MPU_uxQueueSpacesAvailableImpl + + PUBWEAK MPU_xQueueReceiveImpl +MPU_xQueueReceiveImpl: + b MPU_xQueueReceiveImpl + + PUBWEAK MPU_xQueuePeekImpl +MPU_xQueuePeekImpl: + b MPU_xQueuePeekImpl + + PUBWEAK MPU_xQueueSemaphoreTakeImpl +MPU_xQueueSemaphoreTakeImpl: + b MPU_xQueueSemaphoreTakeImpl + + PUBWEAK MPU_xQueueGetMutexHolderImpl +MPU_xQueueGetMutexHolderImpl: + b MPU_xQueueGetMutexHolderImpl + + PUBWEAK MPU_xQueueTakeMutexRecursiveImpl +MPU_xQueueTakeMutexRecursiveImpl: + b MPU_xQueueTakeMutexRecursiveImpl + + PUBWEAK MPU_xQueueGiveMutexRecursiveImpl +MPU_xQueueGiveMutexRecursiveImpl: + b MPU_xQueueGiveMutexRecursiveImpl + + PUBWEAK MPU_xQueueSelectFromSetImpl +MPU_xQueueSelectFromSetImpl: + b MPU_xQueueSelectFromSetImpl + + PUBWEAK MPU_xQueueAddToSetImpl +MPU_xQueueAddToSetImpl: + b MPU_xQueueAddToSetImpl + + PUBWEAK MPU_vQueueAddToRegistryImpl +MPU_vQueueAddToRegistryImpl: + b MPU_vQueueAddToRegistryImpl + + PUBWEAK MPU_vQueueUnregisterQueueImpl +MPU_vQueueUnregisterQueueImpl: + b MPU_vQueueUnregisterQueueImpl + + PUBWEAK MPU_pcQueueGetNameImpl +MPU_pcQueueGetNameImpl: + b MPU_pcQueueGetNameImpl + + PUBWEAK MPU_pvTimerGetTimerIDImpl +MPU_pvTimerGetTimerIDImpl: + b MPU_pvTimerGetTimerIDImpl + + PUBWEAK MPU_vTimerSetTimerIDImpl +MPU_vTimerSetTimerIDImpl: + b MPU_vTimerSetTimerIDImpl + + PUBWEAK MPU_xTimerIsTimerActiveImpl +MPU_xTimerIsTimerActiveImpl: + b MPU_xTimerIsTimerActiveImpl + + PUBWEAK MPU_xTimerGetTimerDaemonTaskHandleImpl +MPU_xTimerGetTimerDaemonTaskHandleImpl: + b MPU_xTimerGetTimerDaemonTaskHandleImpl + + PUBWEAK MPU_xTimerGenericCommandFromTaskImpl +MPU_xTimerGenericCommandFromTaskImpl: + b MPU_xTimerGenericCommandFromTaskImpl + + PUBWEAK MPU_pcTimerGetNameImpl +MPU_pcTimerGetNameImpl: + b MPU_pcTimerGetNameImpl + + PUBWEAK MPU_vTimerSetReloadModeImpl +MPU_vTimerSetReloadModeImpl: + b MPU_vTimerSetReloadModeImpl + + PUBWEAK MPU_xTimerGetReloadModeImpl +MPU_xTimerGetReloadModeImpl: + b MPU_xTimerGetReloadModeImpl + + PUBWEAK MPU_uxTimerGetReloadModeImpl +MPU_uxTimerGetReloadModeImpl: + b MPU_uxTimerGetReloadModeImpl + + PUBWEAK MPU_xTimerGetPeriodImpl +MPU_xTimerGetPeriodImpl: + b MPU_xTimerGetPeriodImpl + + PUBWEAK MPU_xTimerGetExpiryTimeImpl +MPU_xTimerGetExpiryTimeImpl: + b MPU_xTimerGetExpiryTimeImpl + + PUBWEAK MPU_xEventGroupWaitBitsImpl +MPU_xEventGroupWaitBitsImpl: + b MPU_xEventGroupWaitBitsImpl + + PUBWEAK MPU_xEventGroupClearBitsImpl +MPU_xEventGroupClearBitsImpl: + b MPU_xEventGroupClearBitsImpl + + PUBWEAK MPU_xEventGroupSetBitsImpl +MPU_xEventGroupSetBitsImpl: + b MPU_xEventGroupSetBitsImpl + + PUBWEAK MPU_xEventGroupSyncImpl +MPU_xEventGroupSyncImpl: + b MPU_xEventGroupSyncImpl + + PUBWEAK MPU_uxEventGroupGetNumberImpl +MPU_uxEventGroupGetNumberImpl: + b MPU_uxEventGroupGetNumberImpl + + PUBWEAK MPU_vEventGroupSetNumberImpl +MPU_vEventGroupSetNumberImpl: + b MPU_vEventGroupSetNumberImpl + + PUBWEAK MPU_xStreamBufferSendImpl +MPU_xStreamBufferSendImpl: + b MPU_xStreamBufferSendImpl + + PUBWEAK MPU_xStreamBufferReceiveImpl +MPU_xStreamBufferReceiveImpl: + b MPU_xStreamBufferReceiveImpl + + PUBWEAK MPU_xStreamBufferIsFullImpl +MPU_xStreamBufferIsFullImpl: + b MPU_xStreamBufferIsFullImpl + + PUBWEAK MPU_xStreamBufferIsEmptyImpl +MPU_xStreamBufferIsEmptyImpl: + b MPU_xStreamBufferIsEmptyImpl + + PUBWEAK MPU_xStreamBufferSpacesAvailableImpl +MPU_xStreamBufferSpacesAvailableImpl: + b MPU_xStreamBufferSpacesAvailableImpl + + PUBWEAK MPU_xStreamBufferBytesAvailableImpl +MPU_xStreamBufferBytesAvailableImpl: + b MPU_xStreamBufferBytesAvailableImpl + + PUBWEAK MPU_xStreamBufferSetTriggerLevelImpl +MPU_xStreamBufferSetTriggerLevelImpl: + b MPU_xStreamBufferSetTriggerLevelImpl + + PUBWEAK MPU_xStreamBufferNextMessageLengthBytesImpl +MPU_xStreamBufferNextMessageLengthBytesImpl: + b MPU_xStreamBufferNextMessageLengthBytesImpl + +/*-----------------------------------------------------------*/ + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + END diff --git a/portable/IAR/ARM_CM52_NTZ/non_secure/port.c b/portable/IAR/ARM_CM52_NTZ/non_secure/port.c new file mode 100644 index 000000000..76d2b2445 --- /dev/null +++ b/portable/IAR/ARM_CM52_NTZ/non_secure/port.c @@ -0,0 +1,2280 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024-2025 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU includes. */ +#include "mpu_wrappers.h" +#include "mpu_syscall_numbers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration settings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to check the validity of an interrupt priority. + */ +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) ) +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used during system call enter and exit. + */ +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Offsets in the stack to the parameters when inside the SVC handler. + */ +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +#if ( portARMV8M_MINOR_VERSION >= 1 ) + + /* Enable Privileged eXecute Never MPU attribute for the selected memory + * region. */ + #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL ) +#endif /* portARMV8M_MINOR_VERSION >= 1 */ + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Extract first address of the MPU region as encoded in the + * RBAR (Region Base Address Register) value. */ +#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \ + ( ( rbar ) & portMPU_RBAR_ADDRESS_MASK ) + +/* Extract last address of the MPU region as encoded in the + * RLAR (Region Limit Address Register) value. */ +#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \ + ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK ) + +/* Does addr lies within [start, end] address range? */ +#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \ + ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) ) + +/* Is the access request satisfied by the available permissions? */ +#define portIS_AUTHORIZED( accessRequest, permissions ) \ + ( ( ( permissions ) & ( accessRequest ) ) == accessRequest ) + +/* Max value that fits in a uint32_t type. */ +#define portUINT32_MAX ( ~( ( uint32_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. + */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 + +/** + * @brief Constants required to check and configure PACBTI security feature implementation. + */ +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) ) + + #define portCONTROL_UPAC_EN ( 1UL << 7UL ) + #define portCONTROL_PAC_EN ( 1UL << 6UL ) + #define portCONTROL_UBTI_EN ( 1UL << 5UL ) + #define portCONTROL_BTI_EN ( 1UL << 4UL ) + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Extract MPU region's access permissions from the Region Base Address + * Register (RBAR) value. + * + * @param ulRBARValue RBAR value for the MPU region. + * + * @return uint32_t Access permissions. + */ + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + + /** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + /** + * @brief Configures PACBTI features. + * + * This function configures the Pointer Authentication, and Branch Target + * Identification security features as per the user configuration. It returns + * the value of the special purpose CONTROL register accordingly, and optionally + * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M + * architecture based) target supports PACBTI security feature. + * + * @param xWriteControlRegister Used to control whether the special purpose + * CONTROL register should be updated or not. + * + * @return CONTROL register value according to the configured PACBTI option. + */ + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the system call stack so that upon returning from + * SVC, the system call stack is used. + * + * @param pulTaskStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + * @param ucSystemCallNumber The system call number of the system call. + */ + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Raise SVC for exiting from a system call. + */ + void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief This variable is set to pdTRUE when the scheduler is started. + */ + PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + + /** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +/** + * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + /** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + + /** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + + /** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the cpsid instruction + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessPermissions = 0; + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_ONLY ) + { + ulAccessPermissions = tskMPU_READ_PERMISSION; + } + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_WRITE ) + { + ulAccessPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION ); + } + + return ulAccessPermissions; + } + +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } + +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ portOFFSET_TO_PC ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ]; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulSystemCallStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the system call section (i.e. application is + * not raising SVC directly). + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as + * it is non-NULL only during the execution of a system call (i.e. + * between system call enter and exit). + * 3. System call is not for a kernel API disabled by the configuration + * in FreeRTOSConfig.h. + * 4. We do not need to check that ucSystemCallNumber is within range + * because the assembly SVC handler checks that before calling + * this function. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) && + ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) ) + { + pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the system call stack for the stack frame. */ + pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulSystemCallStack[ i ] = pulTaskStack[ i ]; + } + + /* Store the value of the Link Register before the SVC was raised. + * It contains the address of the caller of the System Call entry + * point (i.e. the caller of the MPU_). We need to restore it + * when we exit from the system call. */ + pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; + + /* Store the value of the PSPLIM register before the SVC was raised. + * We need to restore it when we exit from the system call. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* Use the pulSystemCallStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif + + /* Start executing the system call upon returning from this handler. */ + pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; + + /* Raise a request to exit from the system call upon finishing the + * system call. */ + pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; + + /* Remember the location where we should copy the stack frame when we exit from + * the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize; + + /* Record if the hardware used padding to force the stack pointer + * to be double word aligned. */ + if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK ) + { + pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG; + } + else + { + pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG ); + } + + /* We ensure in pxPortInitialiseStack that the system call stack is + * double word aligned and therefore, there is no need of padding. + * Clear the bit[9] of stacked xPSR. */ + pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + + /* Raise the privilege for the duration of the system call. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " bics r0, r1 \n" /* Clear nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */ + { + __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulTaskStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the privileged code (i.e. application is not + * raising SVC directly). This SVC is only raised from + * vRequestSystemCallExit which is in the privileged code section. + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL - + * this means that we previously entered a system call and the + * application is not attempting to exit without entering a system + * call. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) ) + { + pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the task stack for the stack frame. */ + pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulTaskStack[ i ] = pulSystemCallStack[ i ]; + } + + /* Use the pulTaskStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) ); + + /* Return to the caller of the System Call entry point (i.e. the + * caller of the MPU_). */ + pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + /* Ensure that LR has a valid value.*/ + pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + + /* Restore the PSPLIM register to what it was at the time of + * system call entry. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* If the hardware used padding to force the stack pointer + * to be double word aligned, set the stacked xPSR bit[9], + * otherwise clear it. */ + if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG ) + { + pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK; + } + else + { + pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + } + + /* This is not NULL only for the duration of the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; + + /* Drop the privilege before returning to the thread mode. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " orrs r0, r1 \n" /* Set nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xTaskIsPrivileged = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xTaskIsPrivileged = pdTRUE; + } + + return xTaskIsPrivileged; + } + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged, + xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulIndex = 0; + uint32_t ulControl = 0x0; + + xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ + ulIndex++; + + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + ulIndex++; + + #if ( configENABLE_TRUSTZONE == 1 ) + { + xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */ + ulIndex++; + } + #endif /* configENABLE_TRUSTZONE */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + ulIndex++; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Check PACBTI security feature configuration before pushing the + * CONTROL register's value on task's TCB. */ + ulControl = prvConfigurePACBTI( pdFALSE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + if( xRunPrivileged == pdTRUE ) + { + xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + else + { + xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG ); + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ + ulIndex++; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + { + /* Ensure that the system call stack is double word aligned. */ + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) + + ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + /* This is not NULL only for the duration of a system call. */ + xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL; + } + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ]; + ulIndex++; + } + } + #endif /* configENABLE_PAC */ + + return &( xMPUSettings->ulContext[ ulIndex ] ); + } + +#else /* configENABLE_MPU */ + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ + { + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + pxTopOfStack--; + *pxTopOfStack = ulTaskPacKey[ i ]; + } + } + #endif /* configENABLE_PAC */ + + return pxTopOfStack; + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Set the CONTROL register value based on PACBTI security feature + * configuration before starting the first task. */ + ( void ) prvConfigurePACBTI( pdTRUE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + { + xSchedulerRunning = pdTRUE; + } + #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + configSTACK_DEPTH_TYPE uxStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( uxStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* PXN. */ + #if ( portARMV8M_MINOR_VERSION >= 1 ) + { + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ); + } + } + #endif /* portARMV8M_MINOR_VERSION >= 1 */ + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, + uint32_t ulBufferLength, + uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */ + + { + uint32_t i, ulBufferStartAddress, ulBufferEndAddress; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE ) + { + ulBufferStartAddress = ( uint32_t ) pvBuffer; + ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL ); + + for( i = 0; i < portTOTAL_NUM_REGIONS; i++ ) + { + /* Is the MPU region enabled? */ + if( ( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR & portMPU_RLAR_REGION_ENABLE ) == portMPU_RLAR_REGION_ENABLE ) + { + if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_AUTHORIZED( ulAccessRequested, + prvGetRegionAccessPermissions( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ) ) ) + { + xAccessGranted = pdTRUE; + break; + } + } + } + } + } + + return xAccessGranted; + } + +#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings; + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else + { + xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 ) + { + xAccessGranted = pdTRUE; + } + } + } + + return xAccessGranted; + } + + #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + ( void ) lInternalIndexOfKernelObject; + + /* If Access Control List feature is not used, all the tasks have + * access to all the kernel objects. */ + return pdTRUE; + } + + #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + { + uint32_t ulControl = 0x0; + + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); + + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; + + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/ARM_CM52_NTZ/non_secure/portasm.h b/portable/IAR/ARM_CM52_NTZ/non_secure/portasm.h new file mode 100644 index 000000000..b7021b024 --- /dev/null +++ b/portable/IAR/ARM_CM52_NTZ/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kernel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/portable/IAR/ARM_CM52_NTZ/non_secure/portasm.s b/portable/IAR/ARM_CM52_NTZ/non_secure/portasm.s new file mode 100644 index 000000000..ba6e8e915 --- /dev/null +++ b/portable/IAR/ARM_CM52_NTZ/non_secure/portasm.s @@ -0,0 +1,456 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" + +/* System call numbers includes. */ +#include "mpu_syscall_numbers.h" + +#ifndef configUSE_MPU_WRAPPERS_V1 + #define configUSE_MPU_WRAPPERS_V1 0 +#endif + + EXTERN pxCurrentTCB + EXTERN vTaskSwitchContext + EXTERN vPortSVCHandler_C +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + EXTERN vSystemCallEnter + EXTERN vSystemCallExit +#endif + + PUBLIC xIsPrivileged + PUBLIC vResetPrivilege + PUBLIC vRestoreContextOfFirstTask + PUBLIC vRaisePrivilege + PUBLIC vStartFirstTask + PUBLIC ulSetInterruptMask + PUBLIC vClearInterruptMask + PUBLIC PendSV_Handler + PUBLIC SVC_Handler +/*-----------------------------------------------------------*/ + +/*---------------- Unprivileged Functions -------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION .text:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +xIsPrivileged: + mrs r0, control /* r0 = CONTROL. */ + tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + ite ne + movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vResetPrivilege: + mrs r0, control /* r0 = CONTROL. */ + orr r0, r0, #1 /* r0 = r0 | 1. */ + msr control, r0 /* CONTROL = r0. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +/*----------------- Privileged Functions --------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION privileged_functions:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +vRestoreContextOfFirstTask: + program_mpu_first_task: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r2] /* r0 = pxCurrentTCB. */ + + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + str r2, [r1] /* Disable MPU. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r1, [r2] /* Program MAIR0. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + + movs r3, #4 /* r3 = 4. */ + str r3, [r1] /* Program RNR = 4. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + #if ( configTOTAL_MPU_REGIONS == 16 ) + movs r3, #8 /* r3 = 8. */ + str r3, [r1] /* Program RNR = 8. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + movs r3, #12 /* r3 = 12. */ + str r3, [r1] /* Program RNR = 12. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + orr r2, #1 /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */ + str r2, [r1] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + + restore_context_first_task: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r2] /* r0 = pxCurrentTCB.*/ + ldr r1, [r0] /* r1 = Location of saved context in TCB. */ + + restore_special_regs_first_task: + #if ( configENABLE_PAC == 1 ) + ldmdb r1!, {r2-r5} /* Read task's dedicated PAC key from the task's context. */ + msr PAC_KEY_P_0, r2 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_1, r3 + msr PAC_KEY_P_2, r4 + msr PAC_KEY_P_3, r5 + clrm {r2-r5} /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + ldmdb r1!, {r2-r4, lr} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */ + msr psp, r2 + msr psplim, r3 + msr control, r4 + + restore_general_regs_first_task: + ldmdb r1!, {r4-r11} /* r4-r11 contain hardware saved context. */ + stmia r2!, {r4-r11} /* Copy the hardware saved context on the task stack. */ + ldmdb r1!, {r4-r11} /* r4-r11 restored. */ + + restore_context_done_first_task: + str r1, [r0] /* Save the location where the context should be saved next as the first member of TCB. */ + mov r0, #0 + msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ + bx lr + +#else /* configENABLE_MPU */ + +vRestoreContextOfFirstTask: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + +#if ( configENABLE_PAC == 1 ) + ldmia r0!, {r1-r4} /* Read task's dedicated PAC key from stack. */ + msr PAC_KEY_P_3, r1 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_2, r2 + msr PAC_KEY_P_1, r3 + msr PAC_KEY_P_0, r4 + clrm {r1-r4} /* Clear r1-r4. */ +#endif /* configENABLE_PAC */ + + ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */ + msr psplim, r1 /* Set this task's PSPLIM value. */ + mrs r1, control /* Obtain current control register value. */ + orrs r1, r1, #2 /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */ + msr control, r1 /* Write back the new control register value. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + mov r0, #0 + msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ + bx r2 /* Finally, branch to EXC_RETURN. */ + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +vRaisePrivilege: + mrs r0, control /* Read the CONTROL register. */ + bic r0, r0, #1 /* Clear the bit 0. */ + msr control, r0 /* Write back the new CONTROL value. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vStartFirstTask: + ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */ + ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */ + ldr r0, [r0] /* The first entry in vector table is stack pointer. */ + msr msp, r0 /* Set the MSP back to the start of the stack. */ + cpsie i /* Globally enable interrupts. */ + cpsie f + dsb + isb + svc 102 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */ +/*-----------------------------------------------------------*/ + +ulSetInterruptMask: + mrs r0, basepri /* r0 = basepri. Return original basepri value. */ + mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r1 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vClearInterruptMask: + msr basepri, r0 /* basepri = ulMask. */ + dsb + isb + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +PendSV_Handler: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r2] /* r0 = pxCurrentTCB. */ + ldr r1, [r0] /* r1 = Location in TCB where the context should be saved. */ + mrs r2, psp /* r2 = PSP. */ + + save_general_regs: + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + add r2, r2, #0x20 /* Move r2 to location where s0 is saved. */ + tst lr, #0x10 + ittt eq + vstmiaeq r1!, {s16-s31} /* Store s16-s31. */ + vldmiaeq r2, {s0-s16} /* Copy hardware saved FP context into s0-s16. */ + vstmiaeq r1!, {s0-s16} /* Store hardware saved FP context. */ + sub r2, r2, #0x20 /* Set r2 back to the location of hardware saved context. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + stmia r1!, {r4-r11} /* Store r4-r11. */ + ldmia r2, {r4-r11} /* Copy the hardware saved context into r4-r11. */ + stmia r1!, {r4-r11} /* Store the hardware saved context. */ + + save_special_regs: + mrs r3, psplim /* r3 = PSPLIM. */ + mrs r4, control /* r4 = CONTROL. */ + stmia r1!, {r2-r4, lr} /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ + #if ( configENABLE_PAC == 1 ) + mrs r2, PAC_KEY_P_0 /* Read task's dedicated PAC key from the PAC key registers. */ + mrs r3, PAC_KEY_P_1 + mrs r4, PAC_KEY_P_2 + mrs r5, PAC_KEY_P_3 + stmia r1!, {r2-r5} /* Store the task's dedicated PAC key on the task's context. */ + clrm {r2-r5} /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + + str r1, [r0] /* Save the location from where the context should be restored as the first member of TCB. */ + + select_next_task: + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bl vTaskSwitchContext + mov r0, #0 /* r0 = 0. */ + msr basepri, r0 /* Enable interrupts. */ + + program_mpu: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r2] /* r0 = pxCurrentTCB. */ + + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + str r2, [r1] /* Disable MPU. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r1, [r2] /* Program MAIR0. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + + movs r3, #4 /* r3 = 4. */ + str r3, [r1] /* Program RNR = 4. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + #if ( configTOTAL_MPU_REGIONS == 16 ) + movs r3, #8 /* r3 = 8. */ + str r3, [r1] /* Program RNR = 8. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + movs r3, #12 /* r3 = 12. */ + str r3, [r1] /* Program RNR = 12. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + orr r2, #1 /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */ + str r2, [r1] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + + restore_context: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r2] /* r0 = pxCurrentTCB.*/ + ldr r1, [r0] /* r1 = Location of saved context in TCB. */ + + restore_special_regs: + #if ( configENABLE_PAC == 1 ) + ldmdb r1!, {r2-r5} /* Read task's dedicated PAC key from the task's context. */ + msr PAC_KEY_P_0, r2 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_1, r3 + msr PAC_KEY_P_2, r4 + msr PAC_KEY_P_3, r5 + clrm {r2-r5} /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + ldmdb r1!, {r2-r4, lr} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */ + msr psp, r2 + msr psplim, r3 + msr control, r4 + + restore_general_regs: + ldmdb r1!, {r4-r11} /* r4-r11 contain hardware saved context. */ + stmia r2!, {r4-r11} /* Copy the hardware saved context on the task stack. */ + ldmdb r1!, {r4-r11} /* r4-r11 restored. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 + ittt eq + vldmdbeq r1!, {s0-s16} /* s0-s16 contain hardware saved FP context. */ + vstmiaeq r2!, {s0-s16} /* Copy hardware saved FP context on the task stack. */ + vldmdbeq r1!, {s16-s31} /* Restore s16-s31. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + + restore_context_done: + str r1, [r0] /* Save the location where the context should be saved next as the first member of TCB. */ + bx lr + +#else /* configENABLE_MPU */ + +PendSV_Handler: + mrs r0, psp /* Read PSP in r0. */ +#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + it eq + vstmdbeq r0!, {s16-s31} /* Store the additional FP context registers which are not saved automatically. */ +#endif /* configENABLE_FPU || configENABLE_MVE */ + + mrs r2, psplim /* r2 = PSPLIM. */ + mov r3, lr /* r3 = LR/EXC_RETURN. */ + stmdb r0!, {r2-r11} /* Store on the stack - PSPLIM, LR and registers that are not automatically. */ + +#if ( configENABLE_PAC == 1 ) + mrs r1, PAC_KEY_P_3 /* Read task's dedicated PAC key from the PAC key registers. */ + mrs r2, PAC_KEY_P_2 + mrs r3, PAC_KEY_P_1 + mrs r4, PAC_KEY_P_0 + stmdb r0!, {r1-r4} /* Store the task's dedicated PAC key on the stack. */ + clrm {r1-r4} /* Clear r1-r4. */ +#endif /* configENABLE_PAC */ + + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + str r0, [r1] /* Save the new top of stack in TCB. */ + + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bl vTaskSwitchContext + mov r0, #0 /* r0 = 0. */ + msr basepri, r0 /* Enable interrupts. */ + + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ + +#if ( configENABLE_PAC == 1 ) + ldmia r0!, {r2-r5} /* Read task's dedicated PAC key from stack. */ + msr PAC_KEY_P_3, r2 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_2, r3 + msr PAC_KEY_P_1, r4 + msr PAC_KEY_P_0, r5 + clrm {r2-r5} /* Clear r2-r5. */ +#endif /* configENABLE_PAC */ + + ldmia r0!, {r2-r11} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */ + +#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst r3, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + it eq + vldmiaeq r0!, {s16-s31} /* Restore the additional FP context registers which are not restored automatically. */ +#endif /* configENABLE_FPU || configENABLE_MVE */ + + msr psplim, r2 /* Restore the PSPLIM register value for the task. */ + msr psp, r0 /* Remember the new top of stack for the task. */ + bx r3 + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + +SVC_Handler: + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + + ldr r1, [r0, #24] + ldrb r2, [r1, #-2] + cmp r2, #NUM_SYSTEM_CALLS + blt syscall_enter + cmp r2, #104 /* portSVC_SYSTEM_CALL_EXIT. */ + beq syscall_exit + b vPortSVCHandler_C + + syscall_enter: + mov r1, lr + b vSystemCallEnter + + syscall_exit: + mov r1, lr + b vSystemCallExit + +#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +SVC_Handler: + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + b vPortSVCHandler_C + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + + END diff --git a/portable/IAR/ARM_CM52_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM52_NTZ/non_secure/portmacro.h new file mode 100644 index 000000000..19de84eb8 --- /dev/null +++ b/portable/IAR/ARM_CM52_NTZ/non_secure/portmacro.h @@ -0,0 +1,87 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (c) 2025 Arm Technology (China) Co., Ltd.All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_MVE + #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE. +#endif /* configENABLE_MVE */ +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M52" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portARMV8M_MINOR_VERSION 1 +#define portDONT_DISCARD __root +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ +#pragma diag_suppress=Be006 +#pragma diag_suppress=Pa082 +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/IAR/ARM_CM52_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM52_NTZ/non_secure/portmacrocommon.h new file mode 100644 index 000000000..f373bcad5 --- /dev/null +++ b/portable/IAR/ARM_CM52_NTZ/non_secure/portmacrocommon.h @@ -0,0 +1,582 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACROCOMMON_H +#define PORTMACROCOMMON_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. +#endif /* configENABLE_FPU */ + +#ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. +#endif /* configENABLE_MPU */ + +#ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. +#endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() +#define portINLINE __inline +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif +#define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ +extern BaseType_t xPortIsInsideInterrupt( void ); + +extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + +extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; +extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + +extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; +extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + +#if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_PAC == 1 ) + + /** + * @brief Generates 128-bit task's random PAC key. + * + * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be + * filled with a 128-bit random number. + */ + void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); + +#endif /* configENABLE_PAC */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ +#if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) +#else + #define portPRIVILEGE_BIT ( 0x0UL ) +#endif /* configENABLE_MPU */ + +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ +#define portPRIVILEGED_FLASH_REGION ( 0UL ) +#define portUNPRIVILEGED_FLASH_REGION ( 1UL ) +#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) +#define portPRIVILEGED_RAM_REGION ( 3UL ) +#define portSTACK_REGION ( 4UL ) +#define portFIRST_CONFIGURABLE_REGION ( 5UL ) +#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) +#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) +#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ +#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ +#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ +#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ +#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ +#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ +#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ +#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) +#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) +#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + +#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) +#define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) +#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) +#define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + +#define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + #ifndef configSYSTEM_CALL_STACK_SIZE + #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. + #endif + + /** + * @brief System call stack. + */ + typedef struct SYSTEM_CALL_STACK_INFO + { + uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; + uint32_t * pulSystemCallStack; + uint32_t * pulSystemCallStackLimit; + uint32_t * pulTaskStack; + uint32_t ulLinkRegisterAtSystemCallEntry; + uint32_t ulStackLimitRegisterAtSystemCallEntry; + } xSYSTEM_CALL_STACK_INFO; + + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + /** + * @brief MPU settings as stored in the TCB. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><-----------><----> + * 16 17 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 71 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 17 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 55 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | | | PC, xPSR | EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><-----------><----> + * 16 17 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 70 + + #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + /* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 17 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 54 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+------------------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +----------+-----------------+------------------------------+------------+-----+ + * + * <---------><----------------><------------------------------><-----------><----> + * 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 38 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+----------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | PC, xPSR | EXC_RETURN | | | + * +----------+-----------------+----------------------+------------+-----+ + * + * <---------><----------------><----------------------><-----------><----> + * 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 37 + + #else /* #if( configENABLE_TRUSTZONE == 1 ) */ + + /* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) + + /* Size of an Access Control List (ACL) entry in bits. */ + #define portACL_ENTRY_SIZE_BITS ( 32U ) + + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + uint32_t ulContext[ MAX_CONTEXT_SIZE ]; + uint32_t ulTaskFlags; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo; + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ]; + #endif + #endif + } xMPU_SETTINGS; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Validate priority of ISRs that are allowed to call FreeRTOS + * system calls. + */ +#if ( configASSERT_DEFINED == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif +#endif + +/** + * @brief SVC numbers. + */ +#define portSVC_ALLOCATE_SECURE_CONTEXT 100 +#define portSVC_FREE_SECURE_CONTEXT 101 +#define portSVC_START_SCHEDULER 102 +#define portSVC_RAISE_PRIVILEGE 103 +#define portSVC_SYSTEM_CALL_EXIT 104 +#define portSVC_YIELD 105 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) +#endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() +#else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + extern BaseType_t xPortIsTaskPrivileged( void ); + +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACROCOMMON_H */ diff --git a/portable/IAR/ARM_CM55/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM55/non_secure/mpu_wrappers_v2_asm.S new file mode 100644 index 000000000..d2cb78e92 --- /dev/null +++ b/portable/IAR/ARM_CM55/non_secure/mpu_wrappers_v2_asm.S @@ -0,0 +1,1242 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + + SECTION freertos_system_calls:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +#include "FreeRTOSConfig.h" +#include "mpu_syscall_numbers.h" + +#ifndef configUSE_MPU_WRAPPERS_V1 + #define configUSE_MPU_WRAPPERS_V1 0 +#endif + +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + PUBLIC MPU_xTaskDelayUntil +MPU_xTaskDelayUntil: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskDelayUntil_Unpriv + MPU_xTaskDelayUntil_Priv: + b MPU_xTaskDelayUntilImpl + MPU_xTaskDelayUntil_Unpriv: + svc #SYSTEM_CALL_xTaskDelayUntil +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskAbortDelay +MPU_xTaskAbortDelay: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskAbortDelay_Unpriv + MPU_xTaskAbortDelay_Priv: + b MPU_xTaskAbortDelayImpl + MPU_xTaskAbortDelay_Unpriv: + svc #SYSTEM_CALL_xTaskAbortDelay +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskDelay +MPU_vTaskDelay: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskDelay_Unpriv + MPU_vTaskDelay_Priv: + b MPU_vTaskDelayImpl + MPU_vTaskDelay_Unpriv: + svc #SYSTEM_CALL_vTaskDelay +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskPriorityGet +MPU_uxTaskPriorityGet: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskPriorityGet_Unpriv + MPU_uxTaskPriorityGet_Priv: + b MPU_uxTaskPriorityGetImpl + MPU_uxTaskPriorityGet_Unpriv: + svc #SYSTEM_CALL_uxTaskPriorityGet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_eTaskGetState +MPU_eTaskGetState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_eTaskGetState_Unpriv + MPU_eTaskGetState_Priv: + b MPU_eTaskGetStateImpl + MPU_eTaskGetState_Unpriv: + svc #SYSTEM_CALL_eTaskGetState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskGetInfo +MPU_vTaskGetInfo: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskGetInfo_Unpriv + MPU_vTaskGetInfo_Priv: + b MPU_vTaskGetInfoImpl + MPU_vTaskGetInfo_Unpriv: + svc #SYSTEM_CALL_vTaskGetInfo +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetIdleTaskHandle +MPU_xTaskGetIdleTaskHandle: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetIdleTaskHandle_Unpriv + MPU_xTaskGetIdleTaskHandle_Priv: + b MPU_xTaskGetIdleTaskHandleImpl + MPU_xTaskGetIdleTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTaskGetIdleTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSuspend +MPU_vTaskSuspend: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSuspend_Unpriv + MPU_vTaskSuspend_Priv: + b MPU_vTaskSuspendImpl + MPU_vTaskSuspend_Unpriv: + svc #SYSTEM_CALL_vTaskSuspend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskResume +MPU_vTaskResume: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskResume_Unpriv + MPU_vTaskResume_Priv: + b MPU_vTaskResumeImpl + MPU_vTaskResume_Unpriv: + svc #SYSTEM_CALL_vTaskResume +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetTickCount +MPU_xTaskGetTickCount: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetTickCount_Unpriv + MPU_xTaskGetTickCount_Priv: + b MPU_xTaskGetTickCountImpl + MPU_xTaskGetTickCount_Unpriv: + svc #SYSTEM_CALL_xTaskGetTickCount +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetNumberOfTasks +MPU_uxTaskGetNumberOfTasks: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetNumberOfTasks_Unpriv + MPU_uxTaskGetNumberOfTasks_Priv: + b MPU_uxTaskGetNumberOfTasksImpl + MPU_uxTaskGetNumberOfTasks_Unpriv: + svc #SYSTEM_CALL_uxTaskGetNumberOfTasks +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetRunTimeCounter +MPU_ulTaskGetRunTimeCounter: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetRunTimeCounter_Unpriv + MPU_ulTaskGetRunTimeCounter_Priv: + b MPU_ulTaskGetRunTimeCounterImpl + MPU_ulTaskGetRunTimeCounter_Unpriv: + svc #SYSTEM_CALL_ulTaskGetRunTimeCounter +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetRunTimePercent +MPU_ulTaskGetRunTimePercent: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetRunTimePercent_Unpriv + MPU_ulTaskGetRunTimePercent_Priv: + b MPU_ulTaskGetRunTimePercentImpl + MPU_ulTaskGetRunTimePercent_Unpriv: + svc #SYSTEM_CALL_ulTaskGetRunTimePercent +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetIdleRunTimePercent +MPU_ulTaskGetIdleRunTimePercent: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetIdleRunTimePercent_Unpriv + MPU_ulTaskGetIdleRunTimePercent_Priv: + b MPU_ulTaskGetIdleRunTimePercentImpl + MPU_ulTaskGetIdleRunTimePercent_Unpriv: + svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetIdleRunTimeCounter +MPU_ulTaskGetIdleRunTimeCounter: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv + MPU_ulTaskGetIdleRunTimeCounter_Priv: + b MPU_ulTaskGetIdleRunTimeCounterImpl + MPU_ulTaskGetIdleRunTimeCounter_Unpriv: + svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetApplicationTaskTag +MPU_vTaskSetApplicationTaskTag: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetApplicationTaskTag_Unpriv + MPU_vTaskSetApplicationTaskTag_Priv: + b MPU_vTaskSetApplicationTaskTagImpl + MPU_vTaskSetApplicationTaskTag_Unpriv: + svc #SYSTEM_CALL_vTaskSetApplicationTaskTag +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetApplicationTaskTag +MPU_xTaskGetApplicationTaskTag: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetApplicationTaskTag_Unpriv + MPU_xTaskGetApplicationTaskTag_Priv: + b MPU_xTaskGetApplicationTaskTagImpl + MPU_xTaskGetApplicationTaskTag_Unpriv: + svc #SYSTEM_CALL_xTaskGetApplicationTaskTag +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetThreadLocalStoragePointer +MPU_vTaskSetThreadLocalStoragePointer: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv + MPU_vTaskSetThreadLocalStoragePointer_Priv: + b MPU_vTaskSetThreadLocalStoragePointerImpl + MPU_vTaskSetThreadLocalStoragePointer_Unpriv: + svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pvTaskGetThreadLocalStoragePointer +MPU_pvTaskGetThreadLocalStoragePointer: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv + MPU_pvTaskGetThreadLocalStoragePointer_Priv: + b MPU_pvTaskGetThreadLocalStoragePointerImpl + MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: + svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetSystemState +MPU_uxTaskGetSystemState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetSystemState_Unpriv + MPU_uxTaskGetSystemState_Priv: + b MPU_uxTaskGetSystemStateImpl + MPU_uxTaskGetSystemState_Unpriv: + svc #SYSTEM_CALL_uxTaskGetSystemState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetStackHighWaterMark +MPU_uxTaskGetStackHighWaterMark: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetStackHighWaterMark_Unpriv + MPU_uxTaskGetStackHighWaterMark_Priv: + b MPU_uxTaskGetStackHighWaterMarkImpl + MPU_uxTaskGetStackHighWaterMark_Unpriv: + svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetStackHighWaterMark2 +MPU_uxTaskGetStackHighWaterMark2: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetStackHighWaterMark2_Unpriv + MPU_uxTaskGetStackHighWaterMark2_Priv: + b MPU_uxTaskGetStackHighWaterMark2Impl + MPU_uxTaskGetStackHighWaterMark2_Unpriv: + svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2 +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetCurrentTaskHandle +MPU_xTaskGetCurrentTaskHandle: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetCurrentTaskHandle_Unpriv + MPU_xTaskGetCurrentTaskHandle_Priv: + b MPU_xTaskGetCurrentTaskHandleImpl + MPU_xTaskGetCurrentTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetSchedulerState +MPU_xTaskGetSchedulerState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetSchedulerState_Unpriv + MPU_xTaskGetSchedulerState_Priv: + b MPU_xTaskGetSchedulerStateImpl + MPU_xTaskGetSchedulerState_Unpriv: + svc #SYSTEM_CALL_xTaskGetSchedulerState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetTimeOutState +MPU_vTaskSetTimeOutState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetTimeOutState_Unpriv + MPU_vTaskSetTimeOutState_Priv: + b MPU_vTaskSetTimeOutStateImpl + MPU_vTaskSetTimeOutState_Unpriv: + svc #SYSTEM_CALL_vTaskSetTimeOutState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskCheckForTimeOut +MPU_xTaskCheckForTimeOut: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskCheckForTimeOut_Unpriv + MPU_xTaskCheckForTimeOut_Priv: + b MPU_xTaskCheckForTimeOutImpl + MPU_xTaskCheckForTimeOut_Unpriv: + svc #SYSTEM_CALL_xTaskCheckForTimeOut +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyEntry +MPU_xTaskGenericNotifyEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotify_Unpriv + MPU_xTaskGenericNotify_Priv: + b MPU_xTaskGenericNotifyImpl + MPU_xTaskGenericNotify_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotify +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyWaitEntry +MPU_xTaskGenericNotifyWaitEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotifyWait_Unpriv + MPU_xTaskGenericNotifyWait_Priv: + b MPU_xTaskGenericNotifyWaitImpl + MPU_xTaskGenericNotifyWait_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotifyWait +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGenericNotifyTake +MPU_ulTaskGenericNotifyTake: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGenericNotifyTake_Unpriv + MPU_ulTaskGenericNotifyTake_Priv: + b MPU_ulTaskGenericNotifyTakeImpl + MPU_ulTaskGenericNotifyTake_Unpriv: + svc #SYSTEM_CALL_ulTaskGenericNotifyTake +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyStateClear +MPU_xTaskGenericNotifyStateClear: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotifyStateClear_Unpriv + MPU_xTaskGenericNotifyStateClear_Priv: + b MPU_xTaskGenericNotifyStateClearImpl + MPU_xTaskGenericNotifyStateClear_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotifyStateClear +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGenericNotifyValueClear +MPU_ulTaskGenericNotifyValueClear: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGenericNotifyValueClear_Unpriv + MPU_ulTaskGenericNotifyValueClear_Priv: + b MPU_ulTaskGenericNotifyValueClearImpl + MPU_ulTaskGenericNotifyValueClear_Unpriv: + svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGenericSend +MPU_xQueueGenericSend: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGenericSend_Unpriv + MPU_xQueueGenericSend_Priv: + b MPU_xQueueGenericSendImpl + MPU_xQueueGenericSend_Unpriv: + svc #SYSTEM_CALL_xQueueGenericSend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxQueueMessagesWaiting +MPU_uxQueueMessagesWaiting: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxQueueMessagesWaiting_Unpriv + MPU_uxQueueMessagesWaiting_Priv: + b MPU_uxQueueMessagesWaitingImpl + MPU_uxQueueMessagesWaiting_Unpriv: + svc #SYSTEM_CALL_uxQueueMessagesWaiting +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxQueueSpacesAvailable +MPU_uxQueueSpacesAvailable: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxQueueSpacesAvailable_Unpriv + MPU_uxQueueSpacesAvailable_Priv: + b MPU_uxQueueSpacesAvailableImpl + MPU_uxQueueSpacesAvailable_Unpriv: + svc #SYSTEM_CALL_uxQueueSpacesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueReceive +MPU_xQueueReceive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueReceive_Unpriv + MPU_xQueueReceive_Priv: + b MPU_xQueueReceiveImpl + MPU_xQueueReceive_Unpriv: + svc #SYSTEM_CALL_xQueueReceive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueuePeek +MPU_xQueuePeek: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueuePeek_Unpriv + MPU_xQueuePeek_Priv: + b MPU_xQueuePeekImpl + MPU_xQueuePeek_Unpriv: + svc #SYSTEM_CALL_xQueuePeek +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueSemaphoreTake +MPU_xQueueSemaphoreTake: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueSemaphoreTake_Unpriv + MPU_xQueueSemaphoreTake_Priv: + b MPU_xQueueSemaphoreTakeImpl + MPU_xQueueSemaphoreTake_Unpriv: + svc #SYSTEM_CALL_xQueueSemaphoreTake +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGetMutexHolder +MPU_xQueueGetMutexHolder: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGetMutexHolder_Unpriv + MPU_xQueueGetMutexHolder_Priv: + b MPU_xQueueGetMutexHolderImpl + MPU_xQueueGetMutexHolder_Unpriv: + svc #SYSTEM_CALL_xQueueGetMutexHolder +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueTakeMutexRecursive +MPU_xQueueTakeMutexRecursive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueTakeMutexRecursive_Unpriv + MPU_xQueueTakeMutexRecursive_Priv: + b MPU_xQueueTakeMutexRecursiveImpl + MPU_xQueueTakeMutexRecursive_Unpriv: + svc #SYSTEM_CALL_xQueueTakeMutexRecursive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGiveMutexRecursive +MPU_xQueueGiveMutexRecursive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGiveMutexRecursive_Unpriv + MPU_xQueueGiveMutexRecursive_Priv: + b MPU_xQueueGiveMutexRecursiveImpl + MPU_xQueueGiveMutexRecursive_Unpriv: + svc #SYSTEM_CALL_xQueueGiveMutexRecursive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueSelectFromSet +MPU_xQueueSelectFromSet: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueSelectFromSet_Unpriv + MPU_xQueueSelectFromSet_Priv: + b MPU_xQueueSelectFromSetImpl + MPU_xQueueSelectFromSet_Unpriv: + svc #SYSTEM_CALL_xQueueSelectFromSet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueAddToSet +MPU_xQueueAddToSet: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueAddToSet_Unpriv + MPU_xQueueAddToSet_Priv: + b MPU_xQueueAddToSetImpl + MPU_xQueueAddToSet_Unpriv: + svc #SYSTEM_CALL_xQueueAddToSet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vQueueAddToRegistry +MPU_vQueueAddToRegistry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vQueueAddToRegistry_Unpriv + MPU_vQueueAddToRegistry_Priv: + b MPU_vQueueAddToRegistryImpl + MPU_vQueueAddToRegistry_Unpriv: + svc #SYSTEM_CALL_vQueueAddToRegistry +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vQueueUnregisterQueue +MPU_vQueueUnregisterQueue: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vQueueUnregisterQueue_Unpriv + MPU_vQueueUnregisterQueue_Priv: + b MPU_vQueueUnregisterQueueImpl + MPU_vQueueUnregisterQueue_Unpriv: + svc #SYSTEM_CALL_vQueueUnregisterQueue +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pcQueueGetName +MPU_pcQueueGetName: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pcQueueGetName_Unpriv + MPU_pcQueueGetName_Priv: + b MPU_pcQueueGetNameImpl + MPU_pcQueueGetName_Unpriv: + svc #SYSTEM_CALL_pcQueueGetName +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pvTimerGetTimerID +MPU_pvTimerGetTimerID: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pvTimerGetTimerID_Unpriv + MPU_pvTimerGetTimerID_Priv: + b MPU_pvTimerGetTimerIDImpl + MPU_pvTimerGetTimerID_Unpriv: + svc #SYSTEM_CALL_pvTimerGetTimerID +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTimerSetTimerID +MPU_vTimerSetTimerID: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTimerSetTimerID_Unpriv + MPU_vTimerSetTimerID_Priv: + b MPU_vTimerSetTimerIDImpl + MPU_vTimerSetTimerID_Unpriv: + svc #SYSTEM_CALL_vTimerSetTimerID +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerIsTimerActive +MPU_xTimerIsTimerActive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerIsTimerActive_Unpriv + MPU_xTimerIsTimerActive_Priv: + b MPU_xTimerIsTimerActiveImpl + MPU_xTimerIsTimerActive_Unpriv: + svc #SYSTEM_CALL_xTimerIsTimerActive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetTimerDaemonTaskHandle +MPU_xTimerGetTimerDaemonTaskHandle: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv + MPU_xTimerGetTimerDaemonTaskHandle_Priv: + b MPU_xTimerGetTimerDaemonTaskHandleImpl + MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGenericCommandFromTaskEntry +MPU_xTimerGenericCommandFromTaskEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGenericCommandFromTask_Unpriv + MPU_xTimerGenericCommandFromTask_Priv: + b MPU_xTimerGenericCommandFromTaskImpl + MPU_xTimerGenericCommandFromTask_Unpriv: + svc #SYSTEM_CALL_xTimerGenericCommandFromTask +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pcTimerGetName +MPU_pcTimerGetName: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pcTimerGetName_Unpriv + MPU_pcTimerGetName_Priv: + b MPU_pcTimerGetNameImpl + MPU_pcTimerGetName_Unpriv: + svc #SYSTEM_CALL_pcTimerGetName +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTimerSetReloadMode +MPU_vTimerSetReloadMode: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTimerSetReloadMode_Unpriv + MPU_vTimerSetReloadMode_Priv: + b MPU_vTimerSetReloadModeImpl + MPU_vTimerSetReloadMode_Unpriv: + svc #SYSTEM_CALL_vTimerSetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetReloadMode +MPU_xTimerGetReloadMode: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetReloadMode_Unpriv + MPU_xTimerGetReloadMode_Priv: + b MPU_xTimerGetReloadModeImpl + MPU_xTimerGetReloadMode_Unpriv: + svc #SYSTEM_CALL_xTimerGetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTimerGetReloadMode +MPU_uxTimerGetReloadMode: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTimerGetReloadMode_Unpriv + MPU_uxTimerGetReloadMode_Priv: + b MPU_uxTimerGetReloadModeImpl + MPU_uxTimerGetReloadMode_Unpriv: + svc #SYSTEM_CALL_uxTimerGetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetPeriod +MPU_xTimerGetPeriod: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetPeriod_Unpriv + MPU_xTimerGetPeriod_Priv: + b MPU_xTimerGetPeriodImpl + MPU_xTimerGetPeriod_Unpriv: + svc #SYSTEM_CALL_xTimerGetPeriod +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetExpiryTime +MPU_xTimerGetExpiryTime: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetExpiryTime_Unpriv + MPU_xTimerGetExpiryTime_Priv: + b MPU_xTimerGetExpiryTimeImpl + MPU_xTimerGetExpiryTime_Unpriv: + svc #SYSTEM_CALL_xTimerGetExpiryTime +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupWaitBitsEntry +MPU_xEventGroupWaitBitsEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupWaitBits_Unpriv + MPU_xEventGroupWaitBits_Priv: + b MPU_xEventGroupWaitBitsImpl + MPU_xEventGroupWaitBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupWaitBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupClearBits +MPU_xEventGroupClearBits: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupClearBits_Unpriv + MPU_xEventGroupClearBits_Priv: + b MPU_xEventGroupClearBitsImpl + MPU_xEventGroupClearBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupClearBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupSetBits +MPU_xEventGroupSetBits: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupSetBits_Unpriv + MPU_xEventGroupSetBits_Priv: + b MPU_xEventGroupSetBitsImpl + MPU_xEventGroupSetBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupSetBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupSync +MPU_xEventGroupSync: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupSync_Unpriv + MPU_xEventGroupSync_Priv: + b MPU_xEventGroupSyncImpl + MPU_xEventGroupSync_Unpriv: + svc #SYSTEM_CALL_xEventGroupSync +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxEventGroupGetNumber +MPU_uxEventGroupGetNumber: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxEventGroupGetNumber_Unpriv + MPU_uxEventGroupGetNumber_Priv: + b MPU_uxEventGroupGetNumberImpl + MPU_uxEventGroupGetNumber_Unpriv: + svc #SYSTEM_CALL_uxEventGroupGetNumber +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vEventGroupSetNumber +MPU_vEventGroupSetNumber: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vEventGroupSetNumber_Unpriv + MPU_vEventGroupSetNumber_Priv: + b MPU_vEventGroupSetNumberImpl + MPU_vEventGroupSetNumber_Unpriv: + svc #SYSTEM_CALL_vEventGroupSetNumber +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSend +MPU_xStreamBufferSend: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSend_Unpriv + MPU_xStreamBufferSend_Priv: + b MPU_xStreamBufferSendImpl + MPU_xStreamBufferSend_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferReceive +MPU_xStreamBufferReceive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferReceive_Unpriv + MPU_xStreamBufferReceive_Priv: + b MPU_xStreamBufferReceiveImpl + MPU_xStreamBufferReceive_Unpriv: + svc #SYSTEM_CALL_xStreamBufferReceive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferIsFull +MPU_xStreamBufferIsFull: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferIsFull_Unpriv + MPU_xStreamBufferIsFull_Priv: + b MPU_xStreamBufferIsFullImpl + MPU_xStreamBufferIsFull_Unpriv: + svc #SYSTEM_CALL_xStreamBufferIsFull +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferIsEmpty +MPU_xStreamBufferIsEmpty: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferIsEmpty_Unpriv + MPU_xStreamBufferIsEmpty_Priv: + b MPU_xStreamBufferIsEmptyImpl + MPU_xStreamBufferIsEmpty_Unpriv: + svc #SYSTEM_CALL_xStreamBufferIsEmpty +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSpacesAvailable +MPU_xStreamBufferSpacesAvailable: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSpacesAvailable_Unpriv + MPU_xStreamBufferSpacesAvailable_Priv: + b MPU_xStreamBufferSpacesAvailableImpl + MPU_xStreamBufferSpacesAvailable_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSpacesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferBytesAvailable +MPU_xStreamBufferBytesAvailable: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferBytesAvailable_Unpriv + MPU_xStreamBufferBytesAvailable_Priv: + b MPU_xStreamBufferBytesAvailableImpl + MPU_xStreamBufferBytesAvailable_Unpriv: + svc #SYSTEM_CALL_xStreamBufferBytesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSetTriggerLevel +MPU_xStreamBufferSetTriggerLevel: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSetTriggerLevel_Unpriv + MPU_xStreamBufferSetTriggerLevel_Priv: + b MPU_xStreamBufferSetTriggerLevelImpl + MPU_xStreamBufferSetTriggerLevel_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferNextMessageLengthBytes +MPU_xStreamBufferNextMessageLengthBytes: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv + MPU_xStreamBufferNextMessageLengthBytes_Priv: + b MPU_xStreamBufferNextMessageLengthBytesImpl + MPU_xStreamBufferNextMessageLengthBytes_Unpriv: + svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes +/*-----------------------------------------------------------*/ + +/* Default weak implementations in case one is not available from + * mpu_wrappers because of config options. */ + + PUBWEAK MPU_xTaskDelayUntilImpl +MPU_xTaskDelayUntilImpl: + b MPU_xTaskDelayUntilImpl + + PUBWEAK MPU_xTaskAbortDelayImpl +MPU_xTaskAbortDelayImpl: + b MPU_xTaskAbortDelayImpl + + PUBWEAK MPU_vTaskDelayImpl +MPU_vTaskDelayImpl: + b MPU_vTaskDelayImpl + + PUBWEAK MPU_uxTaskPriorityGetImpl +MPU_uxTaskPriorityGetImpl: + b MPU_uxTaskPriorityGetImpl + + PUBWEAK MPU_eTaskGetStateImpl +MPU_eTaskGetStateImpl: + b MPU_eTaskGetStateImpl + + PUBWEAK MPU_vTaskGetInfoImpl +MPU_vTaskGetInfoImpl: + b MPU_vTaskGetInfoImpl + + PUBWEAK MPU_xTaskGetIdleTaskHandleImpl +MPU_xTaskGetIdleTaskHandleImpl: + b MPU_xTaskGetIdleTaskHandleImpl + + PUBWEAK MPU_vTaskSuspendImpl +MPU_vTaskSuspendImpl: + b MPU_vTaskSuspendImpl + + PUBWEAK MPU_vTaskResumeImpl +MPU_vTaskResumeImpl: + b MPU_vTaskResumeImpl + + PUBWEAK MPU_xTaskGetTickCountImpl +MPU_xTaskGetTickCountImpl: + b MPU_xTaskGetTickCountImpl + + PUBWEAK MPU_uxTaskGetNumberOfTasksImpl +MPU_uxTaskGetNumberOfTasksImpl: + b MPU_uxTaskGetNumberOfTasksImpl + + PUBWEAK MPU_ulTaskGetRunTimeCounterImpl +MPU_ulTaskGetRunTimeCounterImpl: + b MPU_ulTaskGetRunTimeCounterImpl + + PUBWEAK MPU_ulTaskGetRunTimePercentImpl +MPU_ulTaskGetRunTimePercentImpl: + b MPU_ulTaskGetRunTimePercentImpl + + PUBWEAK MPU_ulTaskGetIdleRunTimePercentImpl +MPU_ulTaskGetIdleRunTimePercentImpl: + b MPU_ulTaskGetIdleRunTimePercentImpl + + PUBWEAK MPU_ulTaskGetIdleRunTimeCounterImpl +MPU_ulTaskGetIdleRunTimeCounterImpl: + b MPU_ulTaskGetIdleRunTimeCounterImpl + + PUBWEAK MPU_vTaskSetApplicationTaskTagImpl +MPU_vTaskSetApplicationTaskTagImpl: + b MPU_vTaskSetApplicationTaskTagImpl + + PUBWEAK MPU_xTaskGetApplicationTaskTagImpl +MPU_xTaskGetApplicationTaskTagImpl: + b MPU_xTaskGetApplicationTaskTagImpl + + PUBWEAK MPU_vTaskSetThreadLocalStoragePointerImpl +MPU_vTaskSetThreadLocalStoragePointerImpl: + b MPU_vTaskSetThreadLocalStoragePointerImpl + + PUBWEAK MPU_pvTaskGetThreadLocalStoragePointerImpl +MPU_pvTaskGetThreadLocalStoragePointerImpl: + b MPU_pvTaskGetThreadLocalStoragePointerImpl + + PUBWEAK MPU_uxTaskGetSystemStateImpl +MPU_uxTaskGetSystemStateImpl: + b MPU_uxTaskGetSystemStateImpl + + PUBWEAK MPU_uxTaskGetStackHighWaterMarkImpl +MPU_uxTaskGetStackHighWaterMarkImpl: + b MPU_uxTaskGetStackHighWaterMarkImpl + + PUBWEAK MPU_uxTaskGetStackHighWaterMark2Impl +MPU_uxTaskGetStackHighWaterMark2Impl: + b MPU_uxTaskGetStackHighWaterMark2Impl + + PUBWEAK MPU_xTaskGetCurrentTaskHandleImpl +MPU_xTaskGetCurrentTaskHandleImpl: + b MPU_xTaskGetCurrentTaskHandleImpl + + PUBWEAK MPU_xTaskGetSchedulerStateImpl +MPU_xTaskGetSchedulerStateImpl: + b MPU_xTaskGetSchedulerStateImpl + + PUBWEAK MPU_vTaskSetTimeOutStateImpl +MPU_vTaskSetTimeOutStateImpl: + b MPU_vTaskSetTimeOutStateImpl + + PUBWEAK MPU_xTaskCheckForTimeOutImpl +MPU_xTaskCheckForTimeOutImpl: + b MPU_xTaskCheckForTimeOutImpl + + PUBWEAK MPU_xTaskGenericNotifyImpl +MPU_xTaskGenericNotifyImpl: + b MPU_xTaskGenericNotifyImpl + + PUBWEAK MPU_xTaskGenericNotifyWaitImpl +MPU_xTaskGenericNotifyWaitImpl: + b MPU_xTaskGenericNotifyWaitImpl + + PUBWEAK MPU_ulTaskGenericNotifyTakeImpl +MPU_ulTaskGenericNotifyTakeImpl: + b MPU_ulTaskGenericNotifyTakeImpl + + PUBWEAK MPU_xTaskGenericNotifyStateClearImpl +MPU_xTaskGenericNotifyStateClearImpl: + b MPU_xTaskGenericNotifyStateClearImpl + + PUBWEAK MPU_ulTaskGenericNotifyValueClearImpl +MPU_ulTaskGenericNotifyValueClearImpl: + b MPU_ulTaskGenericNotifyValueClearImpl + + PUBWEAK MPU_xQueueGenericSendImpl +MPU_xQueueGenericSendImpl: + b MPU_xQueueGenericSendImpl + + PUBWEAK MPU_uxQueueMessagesWaitingImpl +MPU_uxQueueMessagesWaitingImpl: + b MPU_uxQueueMessagesWaitingImpl + + PUBWEAK MPU_uxQueueSpacesAvailableImpl +MPU_uxQueueSpacesAvailableImpl: + b MPU_uxQueueSpacesAvailableImpl + + PUBWEAK MPU_xQueueReceiveImpl +MPU_xQueueReceiveImpl: + b MPU_xQueueReceiveImpl + + PUBWEAK MPU_xQueuePeekImpl +MPU_xQueuePeekImpl: + b MPU_xQueuePeekImpl + + PUBWEAK MPU_xQueueSemaphoreTakeImpl +MPU_xQueueSemaphoreTakeImpl: + b MPU_xQueueSemaphoreTakeImpl + + PUBWEAK MPU_xQueueGetMutexHolderImpl +MPU_xQueueGetMutexHolderImpl: + b MPU_xQueueGetMutexHolderImpl + + PUBWEAK MPU_xQueueTakeMutexRecursiveImpl +MPU_xQueueTakeMutexRecursiveImpl: + b MPU_xQueueTakeMutexRecursiveImpl + + PUBWEAK MPU_xQueueGiveMutexRecursiveImpl +MPU_xQueueGiveMutexRecursiveImpl: + b MPU_xQueueGiveMutexRecursiveImpl + + PUBWEAK MPU_xQueueSelectFromSetImpl +MPU_xQueueSelectFromSetImpl: + b MPU_xQueueSelectFromSetImpl + + PUBWEAK MPU_xQueueAddToSetImpl +MPU_xQueueAddToSetImpl: + b MPU_xQueueAddToSetImpl + + PUBWEAK MPU_vQueueAddToRegistryImpl +MPU_vQueueAddToRegistryImpl: + b MPU_vQueueAddToRegistryImpl + + PUBWEAK MPU_vQueueUnregisterQueueImpl +MPU_vQueueUnregisterQueueImpl: + b MPU_vQueueUnregisterQueueImpl + + PUBWEAK MPU_pcQueueGetNameImpl +MPU_pcQueueGetNameImpl: + b MPU_pcQueueGetNameImpl + + PUBWEAK MPU_pvTimerGetTimerIDImpl +MPU_pvTimerGetTimerIDImpl: + b MPU_pvTimerGetTimerIDImpl + + PUBWEAK MPU_vTimerSetTimerIDImpl +MPU_vTimerSetTimerIDImpl: + b MPU_vTimerSetTimerIDImpl + + PUBWEAK MPU_xTimerIsTimerActiveImpl +MPU_xTimerIsTimerActiveImpl: + b MPU_xTimerIsTimerActiveImpl + + PUBWEAK MPU_xTimerGetTimerDaemonTaskHandleImpl +MPU_xTimerGetTimerDaemonTaskHandleImpl: + b MPU_xTimerGetTimerDaemonTaskHandleImpl + + PUBWEAK MPU_xTimerGenericCommandFromTaskImpl +MPU_xTimerGenericCommandFromTaskImpl: + b MPU_xTimerGenericCommandFromTaskImpl + + PUBWEAK MPU_pcTimerGetNameImpl +MPU_pcTimerGetNameImpl: + b MPU_pcTimerGetNameImpl + + PUBWEAK MPU_vTimerSetReloadModeImpl +MPU_vTimerSetReloadModeImpl: + b MPU_vTimerSetReloadModeImpl + + PUBWEAK MPU_xTimerGetReloadModeImpl +MPU_xTimerGetReloadModeImpl: + b MPU_xTimerGetReloadModeImpl + + PUBWEAK MPU_uxTimerGetReloadModeImpl +MPU_uxTimerGetReloadModeImpl: + b MPU_uxTimerGetReloadModeImpl + + PUBWEAK MPU_xTimerGetPeriodImpl +MPU_xTimerGetPeriodImpl: + b MPU_xTimerGetPeriodImpl + + PUBWEAK MPU_xTimerGetExpiryTimeImpl +MPU_xTimerGetExpiryTimeImpl: + b MPU_xTimerGetExpiryTimeImpl + + PUBWEAK MPU_xEventGroupWaitBitsImpl +MPU_xEventGroupWaitBitsImpl: + b MPU_xEventGroupWaitBitsImpl + + PUBWEAK MPU_xEventGroupClearBitsImpl +MPU_xEventGroupClearBitsImpl: + b MPU_xEventGroupClearBitsImpl + + PUBWEAK MPU_xEventGroupSetBitsImpl +MPU_xEventGroupSetBitsImpl: + b MPU_xEventGroupSetBitsImpl + + PUBWEAK MPU_xEventGroupSyncImpl +MPU_xEventGroupSyncImpl: + b MPU_xEventGroupSyncImpl + + PUBWEAK MPU_uxEventGroupGetNumberImpl +MPU_uxEventGroupGetNumberImpl: + b MPU_uxEventGroupGetNumberImpl + + PUBWEAK MPU_vEventGroupSetNumberImpl +MPU_vEventGroupSetNumberImpl: + b MPU_vEventGroupSetNumberImpl + + PUBWEAK MPU_xStreamBufferSendImpl +MPU_xStreamBufferSendImpl: + b MPU_xStreamBufferSendImpl + + PUBWEAK MPU_xStreamBufferReceiveImpl +MPU_xStreamBufferReceiveImpl: + b MPU_xStreamBufferReceiveImpl + + PUBWEAK MPU_xStreamBufferIsFullImpl +MPU_xStreamBufferIsFullImpl: + b MPU_xStreamBufferIsFullImpl + + PUBWEAK MPU_xStreamBufferIsEmptyImpl +MPU_xStreamBufferIsEmptyImpl: + b MPU_xStreamBufferIsEmptyImpl + + PUBWEAK MPU_xStreamBufferSpacesAvailableImpl +MPU_xStreamBufferSpacesAvailableImpl: + b MPU_xStreamBufferSpacesAvailableImpl + + PUBWEAK MPU_xStreamBufferBytesAvailableImpl +MPU_xStreamBufferBytesAvailableImpl: + b MPU_xStreamBufferBytesAvailableImpl + + PUBWEAK MPU_xStreamBufferSetTriggerLevelImpl +MPU_xStreamBufferSetTriggerLevelImpl: + b MPU_xStreamBufferSetTriggerLevelImpl + + PUBWEAK MPU_xStreamBufferNextMessageLengthBytesImpl +MPU_xStreamBufferNextMessageLengthBytesImpl: + b MPU_xStreamBufferNextMessageLengthBytesImpl + +/*-----------------------------------------------------------*/ + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + END diff --git a/portable/IAR/ARM_CM55/non_secure/port.c b/portable/IAR/ARM_CM55/non_secure/port.c new file mode 100644 index 000000000..76d2b2445 --- /dev/null +++ b/portable/IAR/ARM_CM55/non_secure/port.c @@ -0,0 +1,2280 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024-2025 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU includes. */ +#include "mpu_wrappers.h" +#include "mpu_syscall_numbers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration settings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to check the validity of an interrupt priority. + */ +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) ) +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used during system call enter and exit. + */ +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Offsets in the stack to the parameters when inside the SVC handler. + */ +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +#if ( portARMV8M_MINOR_VERSION >= 1 ) + + /* Enable Privileged eXecute Never MPU attribute for the selected memory + * region. */ + #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL ) +#endif /* portARMV8M_MINOR_VERSION >= 1 */ + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Extract first address of the MPU region as encoded in the + * RBAR (Region Base Address Register) value. */ +#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \ + ( ( rbar ) & portMPU_RBAR_ADDRESS_MASK ) + +/* Extract last address of the MPU region as encoded in the + * RLAR (Region Limit Address Register) value. */ +#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \ + ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK ) + +/* Does addr lies within [start, end] address range? */ +#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \ + ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) ) + +/* Is the access request satisfied by the available permissions? */ +#define portIS_AUTHORIZED( accessRequest, permissions ) \ + ( ( ( permissions ) & ( accessRequest ) ) == accessRequest ) + +/* Max value that fits in a uint32_t type. */ +#define portUINT32_MAX ( ~( ( uint32_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. + */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 + +/** + * @brief Constants required to check and configure PACBTI security feature implementation. + */ +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) ) + + #define portCONTROL_UPAC_EN ( 1UL << 7UL ) + #define portCONTROL_PAC_EN ( 1UL << 6UL ) + #define portCONTROL_UBTI_EN ( 1UL << 5UL ) + #define portCONTROL_BTI_EN ( 1UL << 4UL ) + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Extract MPU region's access permissions from the Region Base Address + * Register (RBAR) value. + * + * @param ulRBARValue RBAR value for the MPU region. + * + * @return uint32_t Access permissions. + */ + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + + /** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + /** + * @brief Configures PACBTI features. + * + * This function configures the Pointer Authentication, and Branch Target + * Identification security features as per the user configuration. It returns + * the value of the special purpose CONTROL register accordingly, and optionally + * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M + * architecture based) target supports PACBTI security feature. + * + * @param xWriteControlRegister Used to control whether the special purpose + * CONTROL register should be updated or not. + * + * @return CONTROL register value according to the configured PACBTI option. + */ + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the system call stack so that upon returning from + * SVC, the system call stack is used. + * + * @param pulTaskStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + * @param ucSystemCallNumber The system call number of the system call. + */ + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Raise SVC for exiting from a system call. + */ + void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief This variable is set to pdTRUE when the scheduler is started. + */ + PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + + /** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +/** + * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + /** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + + /** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + + /** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the cpsid instruction + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessPermissions = 0; + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_ONLY ) + { + ulAccessPermissions = tskMPU_READ_PERMISSION; + } + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_WRITE ) + { + ulAccessPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION ); + } + + return ulAccessPermissions; + } + +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } + +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ portOFFSET_TO_PC ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ]; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulSystemCallStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the system call section (i.e. application is + * not raising SVC directly). + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as + * it is non-NULL only during the execution of a system call (i.e. + * between system call enter and exit). + * 3. System call is not for a kernel API disabled by the configuration + * in FreeRTOSConfig.h. + * 4. We do not need to check that ucSystemCallNumber is within range + * because the assembly SVC handler checks that before calling + * this function. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) && + ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) ) + { + pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the system call stack for the stack frame. */ + pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulSystemCallStack[ i ] = pulTaskStack[ i ]; + } + + /* Store the value of the Link Register before the SVC was raised. + * It contains the address of the caller of the System Call entry + * point (i.e. the caller of the MPU_). We need to restore it + * when we exit from the system call. */ + pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; + + /* Store the value of the PSPLIM register before the SVC was raised. + * We need to restore it when we exit from the system call. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* Use the pulSystemCallStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif + + /* Start executing the system call upon returning from this handler. */ + pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; + + /* Raise a request to exit from the system call upon finishing the + * system call. */ + pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; + + /* Remember the location where we should copy the stack frame when we exit from + * the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize; + + /* Record if the hardware used padding to force the stack pointer + * to be double word aligned. */ + if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK ) + { + pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG; + } + else + { + pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG ); + } + + /* We ensure in pxPortInitialiseStack that the system call stack is + * double word aligned and therefore, there is no need of padding. + * Clear the bit[9] of stacked xPSR. */ + pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + + /* Raise the privilege for the duration of the system call. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " bics r0, r1 \n" /* Clear nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */ + { + __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulTaskStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the privileged code (i.e. application is not + * raising SVC directly). This SVC is only raised from + * vRequestSystemCallExit which is in the privileged code section. + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL - + * this means that we previously entered a system call and the + * application is not attempting to exit without entering a system + * call. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) ) + { + pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the task stack for the stack frame. */ + pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulTaskStack[ i ] = pulSystemCallStack[ i ]; + } + + /* Use the pulTaskStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) ); + + /* Return to the caller of the System Call entry point (i.e. the + * caller of the MPU_). */ + pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + /* Ensure that LR has a valid value.*/ + pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + + /* Restore the PSPLIM register to what it was at the time of + * system call entry. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* If the hardware used padding to force the stack pointer + * to be double word aligned, set the stacked xPSR bit[9], + * otherwise clear it. */ + if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG ) + { + pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK; + } + else + { + pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + } + + /* This is not NULL only for the duration of the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; + + /* Drop the privilege before returning to the thread mode. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " orrs r0, r1 \n" /* Set nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xTaskIsPrivileged = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xTaskIsPrivileged = pdTRUE; + } + + return xTaskIsPrivileged; + } + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged, + xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulIndex = 0; + uint32_t ulControl = 0x0; + + xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ + ulIndex++; + + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + ulIndex++; + + #if ( configENABLE_TRUSTZONE == 1 ) + { + xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */ + ulIndex++; + } + #endif /* configENABLE_TRUSTZONE */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + ulIndex++; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Check PACBTI security feature configuration before pushing the + * CONTROL register's value on task's TCB. */ + ulControl = prvConfigurePACBTI( pdFALSE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + if( xRunPrivileged == pdTRUE ) + { + xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + else + { + xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG ); + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ + ulIndex++; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + { + /* Ensure that the system call stack is double word aligned. */ + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) + + ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + /* This is not NULL only for the duration of a system call. */ + xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL; + } + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ]; + ulIndex++; + } + } + #endif /* configENABLE_PAC */ + + return &( xMPUSettings->ulContext[ ulIndex ] ); + } + +#else /* configENABLE_MPU */ + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ + { + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + pxTopOfStack--; + *pxTopOfStack = ulTaskPacKey[ i ]; + } + } + #endif /* configENABLE_PAC */ + + return pxTopOfStack; + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Set the CONTROL register value based on PACBTI security feature + * configuration before starting the first task. */ + ( void ) prvConfigurePACBTI( pdTRUE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + { + xSchedulerRunning = pdTRUE; + } + #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + configSTACK_DEPTH_TYPE uxStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( uxStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* PXN. */ + #if ( portARMV8M_MINOR_VERSION >= 1 ) + { + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ); + } + } + #endif /* portARMV8M_MINOR_VERSION >= 1 */ + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, + uint32_t ulBufferLength, + uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */ + + { + uint32_t i, ulBufferStartAddress, ulBufferEndAddress; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE ) + { + ulBufferStartAddress = ( uint32_t ) pvBuffer; + ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL ); + + for( i = 0; i < portTOTAL_NUM_REGIONS; i++ ) + { + /* Is the MPU region enabled? */ + if( ( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR & portMPU_RLAR_REGION_ENABLE ) == portMPU_RLAR_REGION_ENABLE ) + { + if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_AUTHORIZED( ulAccessRequested, + prvGetRegionAccessPermissions( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ) ) ) + { + xAccessGranted = pdTRUE; + break; + } + } + } + } + } + + return xAccessGranted; + } + +#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings; + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else + { + xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 ) + { + xAccessGranted = pdTRUE; + } + } + } + + return xAccessGranted; + } + + #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + ( void ) lInternalIndexOfKernelObject; + + /* If Access Control List feature is not used, all the tasks have + * access to all the kernel objects. */ + return pdTRUE; + } + + #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + { + uint32_t ulControl = 0x0; + + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); + + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; + + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/ARM_CM55/non_secure/portasm.h b/portable/IAR/ARM_CM55/non_secure/portasm.h new file mode 100644 index 000000000..b7021b024 --- /dev/null +++ b/portable/IAR/ARM_CM55/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kernel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/portable/IAR/ARM_CM55/non_secure/portasm.s b/portable/IAR/ARM_CM55/non_secure/portasm.s new file mode 100644 index 000000000..8d5988819 --- /dev/null +++ b/portable/IAR/ARM_CM55/non_secure/portasm.s @@ -0,0 +1,543 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" + +/* System call numbers includes. */ +#include "mpu_syscall_numbers.h" + +#ifndef configUSE_MPU_WRAPPERS_V1 + #define configUSE_MPU_WRAPPERS_V1 0 +#endif + + EXTERN pxCurrentTCB + EXTERN xSecureContext + EXTERN vTaskSwitchContext + EXTERN vPortSVCHandler_C + EXTERN SecureContext_SaveContext + EXTERN SecureContext_LoadContext +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + EXTERN vSystemCallEnter + EXTERN vSystemCallExit +#endif + + PUBLIC xIsPrivileged + PUBLIC vResetPrivilege + PUBLIC vPortAllocateSecureContext + PUBLIC vRestoreContextOfFirstTask + PUBLIC vRaisePrivilege + PUBLIC vStartFirstTask + PUBLIC ulSetInterruptMask + PUBLIC vClearInterruptMask + PUBLIC PendSV_Handler + PUBLIC SVC_Handler + PUBLIC vPortFreeSecureContext +/*-----------------------------------------------------------*/ + +/*---------------- Unprivileged Functions -------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION .text:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +xIsPrivileged: + mrs r0, control /* r0 = CONTROL. */ + tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + ite ne + movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vResetPrivilege: + mrs r0, control /* r0 = CONTROL. */ + orr r0, r0, #1 /* r0 = r0 | 1. */ + msr control, r0 /* CONTROL = r0. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vPortAllocateSecureContext: + svc 100 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 100. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +/*----------------- Privileged Functions --------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION privileged_functions:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +vRestoreContextOfFirstTask: + program_mpu_first_task: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r3] /* r0 = pxCurrentTCB. */ + + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + str r2, [r1] /* Disable MPU. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r1, [r2] /* Program MAIR0. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + + movs r3, #4 /* r3 = 4. */ + str r3, [r1] /* Program RNR = 4. */ + ldmia r0!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + #if ( configTOTAL_MPU_REGIONS == 16 ) + movs r3, #8 /* r3 = 8. */ + str r3, [r1] /* Program RNR = 8. */ + ldmia r0!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + movs r3, #12 /* r3 = 12. */ + str r3, [r1] /* Program RNR = 12. */ + ldmia r0!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + orr r2, #1 /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */ + str r2, [r1] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + + restore_context_first_task: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* r1 = pxCurrentTCB.*/ + ldr r2, [r1] /* r2 = Location of saved context in TCB. */ + + restore_special_regs_first_task: + #if ( configENABLE_PAC == 1 ) + ldmdb r2!, {r3-r6} /* Read task's dedicated PAC key from the task's context. */ + msr PAC_KEY_P_0, r3 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_1, r4 + msr PAC_KEY_P_2, r5 + msr PAC_KEY_P_3, r6 + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + ldmdb r2!, {r0, r3-r5, lr} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */ + msr psp, r3 + msr psplim, r4 + msr control, r5 + ldr r4, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + str r0, [r4] /* Restore xSecureContext. */ + + restore_general_regs_first_task: + ldmdb r2!, {r4-r11} /* r4-r11 contain hardware saved context. */ + stmia r3!, {r4-r11} /* Copy the hardware saved context on the task stack. */ + ldmdb r2!, {r4-r11} /* r4-r11 restored. */ + + restore_context_done_first_task: + str r2, [r1] /* Save the location where the context should be saved next as the first member of TCB. */ + mov r0, #0 + msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ + bx lr + +#else /* configENABLE_MPU */ + +vRestoreContextOfFirstTask: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r3, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + +#if ( configENABLE_PAC == 1 ) + ldmia r0!, {r1-r4} /* Read task's dedicated PAC key from stack. */ + msr PAC_KEY_P_3, r1 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_2, r2 + msr PAC_KEY_P_1, r3 + msr PAC_KEY_P_0, r4 + clrm {r1-r4} /* Clear r1-r4. */ +#endif /* configENABLE_PAC */ + + ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */ + ldr r4, =xSecureContext + str r1, [r4] /* Set xSecureContext to this task's value for the same. */ + msr psplim, r2 /* Set this task's PSPLIM value. */ + mrs r1, control /* Obtain current control register value. */ + orrs r1, r1, #2 /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */ + msr control, r1 /* Write back the new control register value. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + mov r0, #0 + msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ + bx r3 /* Finally, branch to EXC_RETURN. */ + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +vRaisePrivilege: + mrs r0, control /* Read the CONTROL register. */ + bic r0, r0, #1 /* Clear the bit 0. */ + msr control, r0 /* Write back the new CONTROL value. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vStartFirstTask: + ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */ + ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */ + ldr r0, [r0] /* The first entry in vector table is stack pointer. */ + msr msp, r0 /* Set the MSP back to the start of the stack. */ + cpsie i /* Globally enable interrupts. */ + cpsie f + dsb + isb + svc 102 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */ +/*-----------------------------------------------------------*/ + +ulSetInterruptMask: + mrs r0, basepri /* r0 = basepri. Return original basepri value. */ + mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r1 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vClearInterruptMask: + msr basepri, r0 /* basepri = ulMask. */ + dsb + isb + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +PendSV_Handler: + ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + ldr r0, [r3] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */ + ldr r2, [r1] /* r2 = Location in TCB where the context should be saved. */ + + cbz r0, save_ns_context /* No secure context to save. */ + save_s_context: + push {r0-r2, lr} + bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r0-r2, lr} + + save_ns_context: + mov r3, lr /* r3 = LR (EXC_RETURN). */ + lsls r3, r3, #25 /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bmi save_special_regs /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + + save_general_regs: + mrs r3, psp + + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + add r3, r3, #0x20 /* Move r3 to location where s0 is saved. */ + tst lr, #0x10 + ittt eq + vstmiaeq r2!, {s16-s31} /* Store s16-s31. */ + vldmiaeq r3, {s0-s16} /* Copy hardware saved FP context into s0-s16. */ + vstmiaeq r2!, {s0-s16} /* Store hardware saved FP context. */ + sub r3, r3, #0x20 /* Set r3 back to the location of hardware saved context. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + + stmia r2!, {r4-r11} /* Store r4-r11. */ + ldmia r3, {r4-r11} /* Copy the hardware saved context into r4-r11. */ + stmia r2!, {r4-r11} /* Store the hardware saved context. */ + + save_special_regs: + mrs r3, psp /* r3 = PSP. */ + mrs r4, psplim /* r4 = PSPLIM. */ + mrs r5, control /* r5 = CONTROL. */ + stmia r2!, {r0, r3-r5, lr} /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ + #if ( configENABLE_PAC == 1 ) + mrs r3, PAC_KEY_P_0 /* Read task's dedicated PAC key from the PAC key registers. */ + mrs r4, PAC_KEY_P_1 + mrs r5, PAC_KEY_P_2 + mrs r6, PAC_KEY_P_3 + stmia r2!, {r3-r6} /* Store the task's dedicated PAC key on the task's context. */ + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + + str r2, [r1] /* Save the location from where the context should be restored as the first member of TCB. */ + + select_next_task: + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bl vTaskSwitchContext + mov r0, #0 /* r0 = 0. */ + msr basepri, r0 /* Enable interrupts. */ + + program_mpu: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r3] /* r0 = pxCurrentTCB.*/ + + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + str r2, [r1] /* Disable MPU. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r1, [r2] /* Program MAIR0. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + + movs r3, #4 /* r3 = 4. */ + str r3, [r1] /* Program RNR = 4. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + #if ( configTOTAL_MPU_REGIONS == 16 ) + movs r3, #8 /* r3 = 8. */ + str r3, [r1] /* Program RNR = 8. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + movs r3, #12 /* r3 = 12. */ + str r3, [r1] /* Program RNR = 12. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + orr r2, #1 /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */ + str r2, [r1] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + + restore_context: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* r1 = pxCurrentTCB.*/ + ldr r2, [r1] /* r2 = Location of saved context in TCB. */ + + restore_special_regs: + #if ( configENABLE_PAC == 1 ) + ldmdb r2!, {r3-r6} /* Read task's dedicated PAC key from the task's context. */ + msr PAC_KEY_P_0, r3 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_1, r4 + msr PAC_KEY_P_2, r5 + msr PAC_KEY_P_3, r6 + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + ldmdb r2!, {r0, r3-r5, lr} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */ + msr psp, r3 + msr psplim, r4 + msr control, r5 + ldr r4, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + str r0, [r4] /* Restore xSecureContext. */ + cbz r0, restore_ns_context /* No secure context to restore. */ + + restore_s_context: + push {r1-r3, lr} + bl SecureContext_LoadContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r1-r3, lr} + + restore_ns_context: + mov r0, lr /* r0 = LR (EXC_RETURN). */ + lsls r0, r0, #25 /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bmi restore_context_done /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + + restore_general_regs: + ldmdb r2!, {r4-r11} /* r4-r11 contain hardware saved context. */ + stmia r3!, {r4-r11} /* Copy the hardware saved context on the task stack. */ + ldmdb r2!, {r4-r11} /* r4-r11 restored. */ + + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 + ittt eq + vldmdbeq r2!, {s0-s16} /* s0-s16 contain hardware saved FP context. */ + vstmiaeq r3!, {s0-s16} /* Copy hardware saved FP context on the task stack. */ + vldmdbeq r2!, {s16-s31} /* Restore s16-s31. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + + restore_context_done: + str r2, [r1] /* Save the location where the context should be saved next as the first member of TCB. */ + bx lr + +#else /* configENABLE_MPU */ + +PendSV_Handler: + ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + ldr r0, [r3] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */ + mrs r2, psp /* Read PSP in r2. */ + + cbz r0, save_ns_context /* No secure context to save. */ + save_s_context: + push {r0-r2, lr} + bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r0-r2, lr} + + save_ns_context: + mov r3, lr /* r3 = LR. */ + lsls r3, r3, #25 /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bmi save_special_regs /* If r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used. */ + + save_general_regs: + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + it eq + vstmdbeq r2!, {s16-s31} /* Store the additional FP context registers which are not saved automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + stmdb r2!, {r4-r11} /* Store the registers that are not saved automatically. */ + + save_special_regs: + mrs r3, psplim /* r3 = PSPLIM. */ + stmdb r2!, {r0, r3, lr} /* Store xSecureContext, PSPLIM and LR on the stack. */ + #if ( configENABLE_PAC == 1 ) + mrs r3, PAC_KEY_P_3 /* Read task's dedicated PAC key from the PAC key registers. */ + mrs r4, PAC_KEY_P_2 + mrs r5, PAC_KEY_P_1 + mrs r6, PAC_KEY_P_0 + stmdb r2!, {r3-r6} /* Store the task's dedicated PAC key on the stack. */ + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + + str r2, [r1] /* Save the new top of stack in TCB. */ + + select_next_task: + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bl vTaskSwitchContext + mov r0, #0 /* r0 = 0. */ + msr basepri, r0 /* Enable interrupts. */ + + restore_context: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB. */ + ldr r2, [r1] /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */ + + restore_special_regs: + #if ( configENABLE_PAC == 1 ) + ldmia r2!, {r3-r6} /* Read task's dedicated PAC key from stack. */ + msr PAC_KEY_P_3, r3 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_2, r4 + msr PAC_KEY_P_1, r5 + msr PAC_KEY_P_0, r6 + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + ldmia r2!, {r0, r3, lr} http://files.iar.com/ftp/pub/box/bxarm-9.60.3.deb/* Read from stack - r0 = xSecureContext, r3 = PSPLIM and LR restored. */ + msr psplim, r3 /* Restore the PSPLIM register value for the task. */ + ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + str r0, [r3] /* Restore the task's xSecureContext. */ + cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */ + + restore_s_context: + push {r1-r3, lr} + bl SecureContext_LoadContext /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r1-r3, lr} + + restore_ns_context: + mov r0, lr /* r0 = LR (EXC_RETURN). */ + lsls r0, r0, #25 /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bmi restore_context_done /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + + restore_general_regs: + ldmia r2!, {r4-r11} /* Restore the registers that are not automatically restored. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + it eq + vldmiaeq r2!, {s16-s31} /* Restore the additional FP context registers which are not restored automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + + restore_context_done: + msr psp, r2 /* Remember the new top of stack for the task. */ + bx lr + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + +SVC_Handler: + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + + ldr r1, [r0, #24] + ldrb r2, [r1, #-2] + cmp r2, #NUM_SYSTEM_CALLS + blt syscall_enter + cmp r2, #104 /* portSVC_SYSTEM_CALL_EXIT. */ + beq syscall_exit + b vPortSVCHandler_C + + syscall_enter: + mov r1, lr + b vSystemCallEnter + + syscall_exit: + mov r1, lr + b vSystemCallExit + +#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +SVC_Handler: + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + b vPortSVCHandler_C + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +vPortFreeSecureContext: + /* r0 = uint32_t *pulTCB. */ + ldr r2, [r0] /* The first item in the TCB is the top of the stack. */ + ldr r1, [r2] /* The first item on the stack is the task's xSecureContext. */ + cmp r1, #0 /* Raise svc if task's xSecureContext is not NULL. */ + it ne + svcne 101 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 101. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + + END diff --git a/portable/IAR/ARM_CM55/non_secure/portmacro.h b/portable/IAR/ARM_CM55/non_secure/portmacro.h new file mode 100644 index 000000000..597af66fa --- /dev/null +++ b/portable/IAR/ARM_CM55/non_secure/portmacro.h @@ -0,0 +1,86 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_MVE + #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE. +#endif /* configENABLE_MVE */ +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M55" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portARMV8M_MINOR_VERSION 1 +#define portDONT_DISCARD __root +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ +#pragma diag_suppress=Be006 +#pragma diag_suppress=Pa082 +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h new file mode 100644 index 000000000..f373bcad5 --- /dev/null +++ b/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h @@ -0,0 +1,582 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACROCOMMON_H +#define PORTMACROCOMMON_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. +#endif /* configENABLE_FPU */ + +#ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. +#endif /* configENABLE_MPU */ + +#ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. +#endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() +#define portINLINE __inline +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif +#define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ +extern BaseType_t xPortIsInsideInterrupt( void ); + +extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + +extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; +extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + +extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; +extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + +#if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_PAC == 1 ) + + /** + * @brief Generates 128-bit task's random PAC key. + * + * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be + * filled with a 128-bit random number. + */ + void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); + +#endif /* configENABLE_PAC */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ +#if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) +#else + #define portPRIVILEGE_BIT ( 0x0UL ) +#endif /* configENABLE_MPU */ + +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ +#define portPRIVILEGED_FLASH_REGION ( 0UL ) +#define portUNPRIVILEGED_FLASH_REGION ( 1UL ) +#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) +#define portPRIVILEGED_RAM_REGION ( 3UL ) +#define portSTACK_REGION ( 4UL ) +#define portFIRST_CONFIGURABLE_REGION ( 5UL ) +#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) +#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) +#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ +#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ +#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ +#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ +#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ +#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ +#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ +#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) +#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) +#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + +#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) +#define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) +#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) +#define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + +#define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + #ifndef configSYSTEM_CALL_STACK_SIZE + #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. + #endif + + /** + * @brief System call stack. + */ + typedef struct SYSTEM_CALL_STACK_INFO + { + uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; + uint32_t * pulSystemCallStack; + uint32_t * pulSystemCallStackLimit; + uint32_t * pulTaskStack; + uint32_t ulLinkRegisterAtSystemCallEntry; + uint32_t ulStackLimitRegisterAtSystemCallEntry; + } xSYSTEM_CALL_STACK_INFO; + + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + /** + * @brief MPU settings as stored in the TCB. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><-----------><----> + * 16 17 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 71 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 17 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 55 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | | | PC, xPSR | EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><-----------><----> + * 16 17 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 70 + + #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + /* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 17 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 54 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+------------------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +----------+-----------------+------------------------------+------------+-----+ + * + * <---------><----------------><------------------------------><-----------><----> + * 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 38 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+----------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | PC, xPSR | EXC_RETURN | | | + * +----------+-----------------+----------------------+------------+-----+ + * + * <---------><----------------><----------------------><-----------><----> + * 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 37 + + #else /* #if( configENABLE_TRUSTZONE == 1 ) */ + + /* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) + + /* Size of an Access Control List (ACL) entry in bits. */ + #define portACL_ENTRY_SIZE_BITS ( 32U ) + + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + uint32_t ulContext[ MAX_CONTEXT_SIZE ]; + uint32_t ulTaskFlags; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo; + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ]; + #endif + #endif + } xMPU_SETTINGS; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Validate priority of ISRs that are allowed to call FreeRTOS + * system calls. + */ +#if ( configASSERT_DEFINED == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif +#endif + +/** + * @brief SVC numbers. + */ +#define portSVC_ALLOCATE_SECURE_CONTEXT 100 +#define portSVC_FREE_SECURE_CONTEXT 101 +#define portSVC_START_SCHEDULER 102 +#define portSVC_RAISE_PRIVILEGE 103 +#define portSVC_SYSTEM_CALL_EXIT 104 +#define portSVC_YIELD 105 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) +#endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() +#else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + extern BaseType_t xPortIsTaskPrivileged( void ); + +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACROCOMMON_H */ diff --git a/portable/IAR/ARM_CM55/secure/secure_context.c b/portable/IAR/ARM_CM55/secure/secure_context.c new file mode 100644 index 000000000..3aa335e63 --- /dev/null +++ b/portable/IAR/ARM_CM55/secure/secure_context.c @@ -0,0 +1,354 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Secure context includes. */ +#include "secure_context.h" + +/* Secure heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief CONTROL value for privileged tasks. + * + * Bit[0] - 0 --> Thread mode is privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_PRIVILEGED 0x02 + +/** + * @brief CONTROL value for un-privileged tasks. + * + * Bit[0] - 1 --> Thread mode is un-privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03 + +/** + * @brief Size of stack seal values in bytes. + */ +#define securecontextSTACK_SEAL_SIZE 8 + +/** + * @brief Stack seal value as recommended by ARM. + */ +#define securecontextSTACK_SEAL_VALUE 0xFEF5EDA5 + +/** + * @brief Maximum number of secure contexts. + */ +#ifndef secureconfigMAX_SECURE_CONTEXTS + #define secureconfigMAX_SECURE_CONTEXTS 8UL +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Pre-allocated array of secure contexts. + */ +SecureContext_t xSecureContexts[ secureconfigMAX_SECURE_CONTEXTS ]; +/*-----------------------------------------------------------*/ + +/** + * @brief Get a free secure context for a task from the secure context pool (xSecureContexts). + * + * This function ensures that only one secure context is allocated for a task. + * + * @param[in] pvTaskHandle The task handle for which the secure context is allocated. + * + * @return Index of a free secure context in the xSecureContexts array. + */ +static uint32_t ulGetSecureContext( void * pvTaskHandle ); + +/** + * @brief Return the secure context to the secure context pool (xSecureContexts). + * + * @param[in] ulSecureContextIndex Index of the context in the xSecureContexts array. + */ +static void vReturnSecureContext( uint32_t ulSecureContextIndex ); + +/* These are implemented in assembly. */ +extern void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ); +extern void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ); +/*-----------------------------------------------------------*/ + +static uint32_t ulGetSecureContext( void * pvTaskHandle ) +{ + /* Start with invalid index. */ + uint32_t i, ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + if( ( xSecureContexts[ i ].pucCurrentStackPointer == NULL ) && + ( xSecureContexts[ i ].pucStackLimit == NULL ) && + ( xSecureContexts[ i ].pucStackStart == NULL ) && + ( xSecureContexts[ i ].pvTaskHandle == NULL ) && + ( ulSecureContextIndex == secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = i; + } + else if( xSecureContexts[ i ].pvTaskHandle == pvTaskHandle ) + { + /* A task can only have one secure context. Do not allocate a second + * context for the same task. */ + ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + break; + } + } + + return ulSecureContextIndex; +} +/*-----------------------------------------------------------*/ + +static void vReturnSecureContext( uint32_t ulSecureContextIndex ) +{ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackStart = NULL; + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = NULL; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) +{ + uint32_t ulIPSR, i; + static uint32_t ulSecureContextsInitialized = 0; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ( ulIPSR != 0 ) && ( ulSecureContextsInitialized == 0 ) ) + { + /* Ensure to initialize secure contexts only once. */ + ulSecureContextsInitialized = 1; + + /* No stack for thread mode until a task's context is loaded. */ + secureportSET_PSPLIM( securecontextNO_STACK ); + secureportSET_PSP( securecontextNO_STACK ); + + /* Initialize all secure contexts. */ + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + xSecureContexts[ i ].pucCurrentStackPointer = NULL; + xSecureContexts[ i ].pucStackLimit = NULL; + xSecureContexts[ i ].pucStackStart = NULL; + xSecureContexts[ i ].pvTaskHandle = NULL; + } + + #if ( configENABLE_MPU == 1 ) + { + /* Configure thread mode to use PSP and to be unprivileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); + } + #else /* configENABLE_MPU */ + { + /* Configure thread mode to use PSP and to be privileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); + } + #endif /* configENABLE_MPU */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ) +#else /* configENABLE_MPU */ + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ) +#endif /* configENABLE_MPU */ +{ + uint8_t * pucStackMemory = NULL; + uint8_t * pucStackLimit; + uint32_t ulIPSR, ulSecureContextIndex; + SecureContextHandle_t xSecureContextHandle = securecontextINVALID_CONTEXT_ID; + + #if ( configENABLE_MPU == 1 ) + uint32_t * pulCurrentStackPointer = NULL; + #endif /* configENABLE_MPU */ + + /* Read the Interrupt Program Status Register (IPSR) and Process Stack Limit + * Register (PSPLIM) value. */ + secureportREAD_IPSR( ulIPSR ); + secureportREAD_PSPLIM( pucStackLimit ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. + * Also do nothing, if a secure context us already loaded. PSPLIM is set to + * securecontextNO_STACK when no secure context is loaded. */ + if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) ) + { + /* Obtain a free secure context. */ + ulSecureContextIndex = ulGetSecureContext( pvTaskHandle ); + + /* Were we able to get a free context? */ + if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS ) + { + /* Allocate the stack space. */ + pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + + if( pucStackMemory != NULL ) + { + /* Since stack grows down, the starting point will be the last + * location. Note that this location is next to the last + * allocated byte for stack (excluding the space for seal values) + * because the hardware decrements the stack pointer before + * writing i.e. if stack pointer is 0x2, a push operation will + * decrement the stack pointer to 0x1 and then write at 0x1. */ + xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize; + + /* Seal the created secure process stack. */ + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; + + /* The stack cannot go beyond this location. This value is + * programmed in the PSPLIM register on context switch.*/ + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = pucStackMemory; + + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle; + + #if ( configENABLE_MPU == 1 ) + { + /* Store the correct CONTROL value for the task on the stack. + * This value is programmed in the CONTROL register on + * context switch. */ + pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; + pulCurrentStackPointer--; + + if( ulIsTaskPrivileged ) + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; + } + else + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; + } + + /* Store the current stack pointer. This value is programmed in + * the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + } + #else /* configENABLE_MPU */ + { + /* Current SP is set to the starting of the stack. This + * value programmed in the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + } + #endif /* configENABLE_MPU */ + + /* Ensure to never return 0 as a valid context handle. */ + xSecureContextHandle = ulSecureContextIndex + 1UL; + } + } + } + + return xSecureContextHandle; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) +{ + uint32_t ulIPSR, ulSecureContextIndex; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* Only free if a valid context handle is passed. */ + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + /* Ensure that the secure context being deleted is associated with + * the task. */ + if( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) + { + /* Free the stack space. */ + vPortFree( xSecureContexts[ ulSecureContextIndex ].pucStackLimit ); + + /* Return the secure context back to the free secure contexts pool. */ + vReturnSecureContext( ulSecureContextIndex ); + } + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that no secure context is loaded and the task is loading it's + * own context. */ + if( ( pucStackLimit == securecontextNO_STACK ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_LoadContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that task's context is loaded and the task is saving it's own + * context. */ + if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_SaveContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/ARM_CM55/secure/secure_context.h b/portable/IAR/ARM_CM55/secure/secure_context.h new file mode 100644 index 000000000..e36a8e430 --- /dev/null +++ b/portable/IAR/ARM_CM55/secure/secure_context.h @@ -0,0 +1,138 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_CONTEXT_H__ +#define __SECURE_CONTEXT_H__ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" + +/** + * @brief PSP value when no secure context is loaded. + */ +#define securecontextNO_STACK 0x0 + +/** + * @brief Invalid context ID. + */ +#define securecontextINVALID_CONTEXT_ID 0UL +/*-----------------------------------------------------------*/ + +/** + * @brief Structure to represent a secure context. + * + * @note Since stack grows down, pucStackStart is the highest address while + * pucStackLimit is the first address of the allocated memory. + */ +typedef struct SecureContext +{ + uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */ + uint8_t * pucStackLimit; /**< Last location of the stack memory (PSPLIM). */ + uint8_t * pucStackStart; /**< First location of the stack memory. */ + void * pvTaskHandle; /**< Task handle of the task this context is associated with. */ +} SecureContext_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Opaque handle for a secure context. + */ +typedef uint32_t SecureContextHandle_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Initializes the secure context management system. + * + * PSP is set to NULL and therefore a task must allocate and load a context + * before calling any secure side function in the thread mode. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureContext_Init( void ); + +/** + * @brief Allocates a context on the secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] ulSecureStackSize Size of the stack to allocate on secure side. + * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise. + * + * @return Opaque context handle if context is successfully allocated, NULL + * otherwise. + */ +#if ( configENABLE_MPU == 1 ) + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ); +#else /* configENABLE_MPU */ + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ); +#endif /* configENABLE_MPU */ + +/** + * @brief Frees the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the + * context to be freed. + */ +void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); + +/** + * @brief Loads the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be loaded. + */ +void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); + +/** + * @brief Saves the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be saved. + */ +void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); + +#endif /* __SECURE_CONTEXT_H__ */ diff --git a/portable/IAR/ARM_CM55/secure/secure_context_port_asm.s b/portable/IAR/ARM_CM55/secure/secure_context_port_asm.s new file mode 100644 index 000000000..27a8f3933 --- /dev/null +++ b/portable/IAR/ARM_CM55/secure/secure_context_port_asm.s @@ -0,0 +1,86 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + SECTION .text:CODE:NOROOT(2) + THUMB + +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" + + PUBLIC SecureContext_LoadContextAsm + PUBLIC SecureContext_SaveContextAsm +/*-----------------------------------------------------------*/ + +SecureContext_LoadContextAsm: + /* pxSecureContext value is in r0. */ + mrs r1, ipsr /* r1 = IPSR. */ + cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */ + ldmia r0!, {r1, r2} /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */ + +#if ( configENABLE_MPU == 1 ) + ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL. */ + msr control, r3 /* CONTROL = r3. */ +#endif /* configENABLE_MPU */ + + msr psplim, r2 /* PSPLIM = r2. */ + msr psp, r1 /* PSP = r1. */ + + load_ctx_therad_mode: + bx lr +/*-----------------------------------------------------------*/ + +SecureContext_SaveContextAsm: + /* pxSecureContext value is in r0. */ + mrs r1, ipsr /* r1 = IPSR. */ + cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */ + mrs r1, psp /* r1 = PSP. */ + +#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + vstmdb r1!, {s0} /* Trigger the deferred stacking of FPU registers. */ + vldmia r1!, {s0} /* Nullify the effect of the previous statement. */ +#endif /* configENABLE_FPU || configENABLE_MVE */ + +#if ( configENABLE_MPU == 1 ) + mrs r2, control /* r2 = CONTROL. */ + stmdb r1!, {r2} /* Store CONTROL value on the stack. */ +#endif /* configENABLE_MPU */ + + str r1, [r0] /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */ + movs r1, #0 /* r1 = securecontextNO_STACK. */ + msr psplim, r1 /* PSPLIM = securecontextNO_STACK. */ + msr psp, r1 /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */ + + save_ctx_therad_mode: + bx lr +/*-----------------------------------------------------------*/ + + END diff --git a/portable/IAR/ARM_CM55/secure/secure_heap.c b/portable/IAR/ARM_CM55/secure/secure_heap.c new file mode 100644 index 000000000..896b53e2d --- /dev/null +++ b/portable/IAR/ARM_CM55/secure/secure_heap.c @@ -0,0 +1,485 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Configuration includes. */ +#include "FreeRTOSConfig.h" + +/* Secure context heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Total heap size. + */ +#ifndef secureconfigTOTAL_HEAP_SIZE + #define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) ) +#endif + +/* No test marker by default. */ +#ifndef mtCOVERAGE_TEST_MARKER + #define mtCOVERAGE_TEST_MARKER() +#endif + +/* No tracing by default. */ +#ifndef traceMALLOC + #define traceMALLOC( pvReturn, xWantedSize ) +#endif + +/* No tracing by default. */ +#ifndef traceFREE + #define traceFREE( pv, xBlockSize ) +#endif + +/* Block sizes must not get too small. */ +#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) ) + +/* Assumes 8bit bytes! */ +#define secureheapBITS_PER_BYTE ( ( size_t ) 8 ) + +/* Max value that fits in a size_t type. */ +#define secureheapSIZE_MAX ( ~( ( size_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define secureheapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) ) + +/* MSB of the xBlockSize member of an BlockLink_t structure is used to track + * the allocation status of a block. When MSB of the xBlockSize member of + * an BlockLink_t structure is set then the block belongs to the application. + * When the bit is free the block is still part of the free heap space. */ +#define secureheapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) ) +#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 ) +#define secureheapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 ) +#define secureheapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK ) +#define secureheapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK ) +/*-----------------------------------------------------------*/ + +/* Allocate the memory for the heap. */ +#if ( configAPPLICATION_ALLOCATED_HEAP == 1 ) + +/* The application writer has already defined the array used for the RTOS +* heap - probably so it can be placed in a special segment or address. */ + extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#else /* configAPPLICATION_ALLOCATED_HEAP */ + static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#endif /* configAPPLICATION_ALLOCATED_HEAP */ + +/** + * @brief The linked list structure. + * + * This is used to link free blocks in order of their memory address. + */ +typedef struct A_BLOCK_LINK +{ + struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */ + size_t xBlockSize; /**< The size of the free block. */ +} BlockLink_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Called automatically to setup the required heap structures the first + * time pvPortMalloc() is called. + */ +static void prvHeapInit( void ); + +/** + * @brief Inserts a block of memory that is being freed into the correct + * position in the list of free memory blocks. + * + * The block being freed will be merged with the block in front it and/or the + * block behind it if the memory blocks are adjacent to each other. + * + * @param[in] pxBlockToInsert The block being freed. + */ +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ); +/*-----------------------------------------------------------*/ + +/** + * @brief The size of the structure placed at the beginning of each allocated + * memory block must by correctly byte aligned. + */ +static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + +/** + * @brief Create a couple of list links to mark the start and end of the list. + */ +static BlockLink_t xStart; +static BlockLink_t * pxEnd = NULL; + +/** + * @brief Keeps track of the number of free bytes remaining, but says nothing + * about fragmentation. + */ +static size_t xFreeBytesRemaining = 0U; +static size_t xMinimumEverFreeBytesRemaining = 0U; + +/*-----------------------------------------------------------*/ + +static void prvHeapInit( void ) +{ + BlockLink_t * pxFirstFreeBlock; + uint8_t * pucAlignedHeap; + size_t uxAddress; + size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE; + + /* Ensure the heap starts on a correctly aligned boundary. */ + uxAddress = ( size_t ) ucHeap; + + if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 ) + { + uxAddress += ( secureportBYTE_ALIGNMENT - 1 ); + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; + } + + pucAlignedHeap = ( uint8_t * ) uxAddress; + + /* xStart is used to hold a pointer to the first item in the list of free + * blocks. The void cast is used to prevent compiler warnings. */ + xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; + xStart.xBlockSize = ( size_t ) 0; + + /* pxEnd is used to mark the end of the list of free blocks and is inserted + * at the end of the heap space. */ + uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; + uxAddress -= xHeapStructSize; + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + pxEnd = ( void * ) uxAddress; + pxEnd->xBlockSize = 0; + pxEnd->pxNextFreeBlock = NULL; + + /* To start with there is a single free block that is sized to take up the + * entire heap space, minus the space taken by pxEnd. */ + pxFirstFreeBlock = ( void * ) pucAlignedHeap; + pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; + pxFirstFreeBlock->pxNextFreeBlock = pxEnd; + + /* Only one block exists - and it covers the entire usable heap space. */ + xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; +} +/*-----------------------------------------------------------*/ + +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) +{ + BlockLink_t * pxIterator; + uint8_t * puc; + + /* Iterate through the list until a block is found that has a higher address + * than the block being inserted. */ + for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) + { + /* Nothing to do here, just iterate to the right position. */ + } + + /* Do the block being inserted, and the block it is being inserted after + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxIterator; + + if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) + { + pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; + pxBlockToInsert = pxIterator; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Do the block being inserted, and the block it is being inserted before + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxBlockToInsert; + + if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) + { + if( pxIterator->pxNextFreeBlock != pxEnd ) + { + /* Form one big block from the two blocks. */ + pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxEnd; + } + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; + } + + /* If the block being inserted plugged a gap, so was merged with the block + * before and the block after, then it's pxNextFreeBlock pointer will have + * already been set, and should not be set here as that would make it point + * to itself. */ + if( pxIterator != pxBlockToInsert ) + { + pxIterator->pxNextFreeBlock = pxBlockToInsert; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} +/*-----------------------------------------------------------*/ + +void * pvPortMalloc( size_t xWantedSize ) +{ + BlockLink_t * pxBlock; + BlockLink_t * pxPreviousBlock; + BlockLink_t * pxNewBlockLink; + void * pvReturn = NULL; + size_t xAdditionalRequiredSize; + size_t xAllocatedBlockSize = 0; + + /* If this is the first call to malloc then the heap will require + * initialisation to setup the list of free blocks. */ + if( pxEnd == NULL ) + { + prvHeapInit(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xWantedSize > 0 ) + { + /* The wanted size must be increased so it can contain a BlockLink_t + * structure in addition to the requested amount of bytes. */ + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 ) + { + xWantedSize += xHeapStructSize; + + /* Ensure that blocks are always aligned to the required number + * of bytes. */ + if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 ) + { + /* Byte alignment required. */ + xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ); + + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 ) + { + xWantedSize += xAdditionalRequiredSize; + } + else + { + xWantedSize = 0; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + xWantedSize = 0; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Check the requested block size is not so large that the top bit is set. + * The top bit of the block size member of the BlockLink_t structure is used + * to determine who owns the block - the application or the kernel, so it + * must be free. */ + if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 ) + { + if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) + { + /* Traverse the list from the start (lowest address) block until + * one of adequate size is found. */ + pxPreviousBlock = &xStart; + pxBlock = xStart.pxNextFreeBlock; + + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + { + pxPreviousBlock = pxBlock; + pxBlock = pxBlock->pxNextFreeBlock; + } + + /* If the end marker was reached then a block of adequate size was + * not found. */ + if( pxBlock != pxEnd ) + { + /* Return the memory space pointed to - jumping over the + * BlockLink_t structure at its start. */ + pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); + + /* This block is being returned for use so must be taken out + * of the list of free blocks. */ + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + + /* If the block is larger than required it can be split into + * two. */ + if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE ) + { + /* This block is to be split into two. Create a new + * block following the number of bytes requested. The void + * cast is used to prevent byte alignment warnings from the + * compiler. */ + pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); + secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + + /* Calculate the sizes of two blocks split from the single + * block. */ + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + pxBlock->xBlockSize = xWantedSize; + + /* Insert the new block into the list of free blocks. */ + pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock; + pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xFreeBytesRemaining -= pxBlock->xBlockSize; + + if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) + { + xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xAllocatedBlockSize = pxBlock->xBlockSize; + + /* The block is being returned - it is allocated and owned by + * the application and has no "next" block. */ + secureheapALLOCATE_BLOCK( pxBlock ); + pxBlock->pxNextFreeBlock = NULL; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceMALLOC( pvReturn, xAllocatedBlockSize ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xAllocatedBlockSize; + + #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) + { + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */ + + secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 ); + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void * pv ) +{ + uint8_t * puc = ( uint8_t * ) pv; + BlockLink_t * pxLink; + + if( pv != NULL ) + { + /* The memory being freed will have an BlockLink_t structure immediately + * before it. */ + puc -= xHeapStructSize; + + /* This casting is to keep the compiler from issuing warnings. */ + pxLink = ( void * ) puc; + + /* Check the block is actually allocated. */ + secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ); + secureportASSERT( pxLink->pxNextFreeBlock == NULL ); + + if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ) + { + if( pxLink->pxNextFreeBlock == NULL ) + { + /* The block is being returned to the heap - it is no longer + * allocated. */ + secureheapFREE_BLOCK( pxLink ); + + secureportDISABLE_NON_SECURE_INTERRUPTS(); + { + /* Add this block to the list of free blocks. */ + xFreeBytesRemaining += pxLink->xBlockSize; + traceFREE( pv, pxLink->xBlockSize ); + prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); + } + secureportENABLE_NON_SECURE_INTERRUPTS(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } +} +/*-----------------------------------------------------------*/ + +size_t xPortGetFreeHeapSize( void ) +{ + return xFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +size_t xPortGetMinimumEverFreeHeapSize( void ) +{ + return xMinimumEverFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/ARM_CM55/secure/secure_heap.h b/portable/IAR/ARM_CM55/secure/secure_heap.h new file mode 100644 index 000000000..0e84a9d9d --- /dev/null +++ b/portable/IAR/ARM_CM55/secure/secure_heap.h @@ -0,0 +1,66 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_HEAP_H__ +#define __SECURE_HEAP_H__ + +/* Standard includes. */ +#include + +/** + * @brief Allocates memory from heap. + * + * @param[in] xWantedSize The size of the memory to be allocated. + * + * @return Pointer to the memory region if the allocation is successful, NULL + * otherwise. + */ +void * pvPortMalloc( size_t xWantedSize ); + +/** + * @brief Frees the previously allocated memory. + * + * @param[in] pv Pointer to the memory to be freed. + */ +void vPortFree( void * pv ); + +/** + * @brief Get the free heap size. + * + * @return Free heap size. + */ +size_t xPortGetFreeHeapSize( void ); + +/** + * @brief Get the minimum ever free heap size. + * + * @return Minimum ever free heap size. + */ +size_t xPortGetMinimumEverFreeHeapSize( void ); + +#endif /* __SECURE_HEAP_H__ */ diff --git a/portable/IAR/ARM_CM55/secure/secure_init.c b/portable/IAR/ARM_CM55/secure/secure_init.c new file mode 100644 index 000000000..c50d37668 --- /dev/null +++ b/portable/IAR/ARM_CM55/secure/secure_init.c @@ -0,0 +1,106 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Secure init includes. */ +#include "secure_init.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Constants required to manipulate the SCB. + */ +#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */ +#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL ) +#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS ) +#define secureinitSCB_AIRCR_PRIS_POS ( 14UL ) +#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS ) + +/** + * @brief Constants required to manipulate the FPU. + */ +#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define secureinitFPCCR_LSPENS_POS ( 29UL ) +#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS ) +#define secureinitFPCCR_TS_POS ( 26UL ) +#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS ) + +#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */ +#define secureinitNSACR_CP10_POS ( 10UL ) +#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS ) +#define secureinitNSACR_CP11_POS ( 11UL ) +#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS ) +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) | + ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) | + ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK ); + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is + * permitted. CP11 should be programmed to the same value as CP10. */ + *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK ); + + /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures + * that we can enable/disable lazy stacking in port.c file. */ + *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK ); + + /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP + * registers (S16-S31) are also pushed to stack on exception entry and + * restored on exception return. */ + *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK ); + } +} +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/ARM_CM55/secure/secure_init.h b/portable/IAR/ARM_CM55/secure/secure_init.h new file mode 100644 index 000000000..ebe04900f --- /dev/null +++ b/portable/IAR/ARM_CM55/secure/secure_init.h @@ -0,0 +1,54 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_INIT_H__ +#define __SECURE_INIT_H__ + +/** + * @brief De-prioritizes the non-secure exceptions. + * + * This is needed to ensure that the non-secure PendSV runs at the lowest + * priority. Context switch is done in the non-secure PendSV handler. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_DePrioritizeNSExceptions( void ); + +/** + * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access. + * + * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point + * Registers are not leaked to the non-secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_EnableNSFPUAccess( void ); + +#endif /* __SECURE_INIT_H__ */ diff --git a/portable/IAR/ARM_CM55/secure/secure_port_macros.h b/portable/IAR/ARM_CM55/secure/secure_port_macros.h new file mode 100644 index 000000000..a70da2c65 --- /dev/null +++ b/portable/IAR/ARM_CM55/secure/secure_port_macros.h @@ -0,0 +1,140 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_PORT_MACROS_H__ +#define __SECURE_PORT_MACROS_H__ + +/** + * @brief Byte alignment requirements. + */ +#define secureportBYTE_ALIGNMENT 8 +#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 ) + +/** + * @brief Macro to declare a function as non-secure callable. + */ +#if defined( __IAR_SYSTEMS_ICC__ ) + #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry __root +#else + #define secureportNON_SECURE_CALLABLE __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) ) +#endif + +/** + * @brief Set the secure PRIMASK value. + */ +#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Set the non-secure PRIMASK value. + */ +#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Read the PSP value in the given variable. + */ +#define secureportREAD_PSP( pucOutCurrentStackPointer ) \ + __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) ) + +/** + * @brief Set the PSP to the given value. + */ +#define secureportSET_PSP( pucCurrentStackPointer ) \ + __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) ) + +/** + * @brief Read the PSPLIM value in the given variable. + */ +#define secureportREAD_PSPLIM( pucOutStackLimit ) \ + __asm volatile ( "mrs %0, psplim" : "=r" ( pucOutStackLimit ) ) + +/** + * @brief Set the PSPLIM to the given value. + */ +#define secureportSET_PSPLIM( pucStackLimit ) \ + __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) ) + +/** + * @brief Set the NonSecure MSP to the given value. + */ +#define secureportSET_MSP_NS( pucMainStackPointer ) \ + __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) ) + +/** + * @brief Set the CONTROL register to the given value. + */ +#define secureportSET_CONTROL( ulControl ) \ + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" ) + +/** + * @brief Read the Interrupt Program Status Register (IPSR) value in the given + * variable. + */ +#define secureportREAD_IPSR( ulIPSR ) \ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) ) + +/** + * @brief PRIMASK value to enable interrupts. + */ +#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0 + +/** + * @brief PRIMASK value to disable interrupts. + */ +#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1 + +/** + * @brief Disable secure interrupts. + */ +#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Disable non-secure interrupts. + * + * This effectively disables context switches. + */ +#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Enable non-secure interrupts. + */ +#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL ) + +/** + * @brief Assert definition. + */ +#define secureportASSERT( x ) \ + if( ( x ) == 0 ) \ + { \ + secureportDISABLE_SECURE_INTERRUPTS(); \ + secureportDISABLE_NON_SECURE_INTERRUPTS(); \ + for( ; ; ) {; } \ + } + +#endif /* __SECURE_PORT_MACROS_H__ */ diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S new file mode 100644 index 000000000..d2cb78e92 --- /dev/null +++ b/portable/IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S @@ -0,0 +1,1242 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + + SECTION freertos_system_calls:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +#include "FreeRTOSConfig.h" +#include "mpu_syscall_numbers.h" + +#ifndef configUSE_MPU_WRAPPERS_V1 + #define configUSE_MPU_WRAPPERS_V1 0 +#endif + +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + PUBLIC MPU_xTaskDelayUntil +MPU_xTaskDelayUntil: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskDelayUntil_Unpriv + MPU_xTaskDelayUntil_Priv: + b MPU_xTaskDelayUntilImpl + MPU_xTaskDelayUntil_Unpriv: + svc #SYSTEM_CALL_xTaskDelayUntil +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskAbortDelay +MPU_xTaskAbortDelay: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskAbortDelay_Unpriv + MPU_xTaskAbortDelay_Priv: + b MPU_xTaskAbortDelayImpl + MPU_xTaskAbortDelay_Unpriv: + svc #SYSTEM_CALL_xTaskAbortDelay +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskDelay +MPU_vTaskDelay: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskDelay_Unpriv + MPU_vTaskDelay_Priv: + b MPU_vTaskDelayImpl + MPU_vTaskDelay_Unpriv: + svc #SYSTEM_CALL_vTaskDelay +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskPriorityGet +MPU_uxTaskPriorityGet: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskPriorityGet_Unpriv + MPU_uxTaskPriorityGet_Priv: + b MPU_uxTaskPriorityGetImpl + MPU_uxTaskPriorityGet_Unpriv: + svc #SYSTEM_CALL_uxTaskPriorityGet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_eTaskGetState +MPU_eTaskGetState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_eTaskGetState_Unpriv + MPU_eTaskGetState_Priv: + b MPU_eTaskGetStateImpl + MPU_eTaskGetState_Unpriv: + svc #SYSTEM_CALL_eTaskGetState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskGetInfo +MPU_vTaskGetInfo: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskGetInfo_Unpriv + MPU_vTaskGetInfo_Priv: + b MPU_vTaskGetInfoImpl + MPU_vTaskGetInfo_Unpriv: + svc #SYSTEM_CALL_vTaskGetInfo +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetIdleTaskHandle +MPU_xTaskGetIdleTaskHandle: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetIdleTaskHandle_Unpriv + MPU_xTaskGetIdleTaskHandle_Priv: + b MPU_xTaskGetIdleTaskHandleImpl + MPU_xTaskGetIdleTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTaskGetIdleTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSuspend +MPU_vTaskSuspend: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSuspend_Unpriv + MPU_vTaskSuspend_Priv: + b MPU_vTaskSuspendImpl + MPU_vTaskSuspend_Unpriv: + svc #SYSTEM_CALL_vTaskSuspend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskResume +MPU_vTaskResume: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskResume_Unpriv + MPU_vTaskResume_Priv: + b MPU_vTaskResumeImpl + MPU_vTaskResume_Unpriv: + svc #SYSTEM_CALL_vTaskResume +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetTickCount +MPU_xTaskGetTickCount: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetTickCount_Unpriv + MPU_xTaskGetTickCount_Priv: + b MPU_xTaskGetTickCountImpl + MPU_xTaskGetTickCount_Unpriv: + svc #SYSTEM_CALL_xTaskGetTickCount +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetNumberOfTasks +MPU_uxTaskGetNumberOfTasks: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetNumberOfTasks_Unpriv + MPU_uxTaskGetNumberOfTasks_Priv: + b MPU_uxTaskGetNumberOfTasksImpl + MPU_uxTaskGetNumberOfTasks_Unpriv: + svc #SYSTEM_CALL_uxTaskGetNumberOfTasks +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetRunTimeCounter +MPU_ulTaskGetRunTimeCounter: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetRunTimeCounter_Unpriv + MPU_ulTaskGetRunTimeCounter_Priv: + b MPU_ulTaskGetRunTimeCounterImpl + MPU_ulTaskGetRunTimeCounter_Unpriv: + svc #SYSTEM_CALL_ulTaskGetRunTimeCounter +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetRunTimePercent +MPU_ulTaskGetRunTimePercent: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetRunTimePercent_Unpriv + MPU_ulTaskGetRunTimePercent_Priv: + b MPU_ulTaskGetRunTimePercentImpl + MPU_ulTaskGetRunTimePercent_Unpriv: + svc #SYSTEM_CALL_ulTaskGetRunTimePercent +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetIdleRunTimePercent +MPU_ulTaskGetIdleRunTimePercent: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetIdleRunTimePercent_Unpriv + MPU_ulTaskGetIdleRunTimePercent_Priv: + b MPU_ulTaskGetIdleRunTimePercentImpl + MPU_ulTaskGetIdleRunTimePercent_Unpriv: + svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetIdleRunTimeCounter +MPU_ulTaskGetIdleRunTimeCounter: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv + MPU_ulTaskGetIdleRunTimeCounter_Priv: + b MPU_ulTaskGetIdleRunTimeCounterImpl + MPU_ulTaskGetIdleRunTimeCounter_Unpriv: + svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetApplicationTaskTag +MPU_vTaskSetApplicationTaskTag: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetApplicationTaskTag_Unpriv + MPU_vTaskSetApplicationTaskTag_Priv: + b MPU_vTaskSetApplicationTaskTagImpl + MPU_vTaskSetApplicationTaskTag_Unpriv: + svc #SYSTEM_CALL_vTaskSetApplicationTaskTag +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetApplicationTaskTag +MPU_xTaskGetApplicationTaskTag: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetApplicationTaskTag_Unpriv + MPU_xTaskGetApplicationTaskTag_Priv: + b MPU_xTaskGetApplicationTaskTagImpl + MPU_xTaskGetApplicationTaskTag_Unpriv: + svc #SYSTEM_CALL_xTaskGetApplicationTaskTag +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetThreadLocalStoragePointer +MPU_vTaskSetThreadLocalStoragePointer: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv + MPU_vTaskSetThreadLocalStoragePointer_Priv: + b MPU_vTaskSetThreadLocalStoragePointerImpl + MPU_vTaskSetThreadLocalStoragePointer_Unpriv: + svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pvTaskGetThreadLocalStoragePointer +MPU_pvTaskGetThreadLocalStoragePointer: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv + MPU_pvTaskGetThreadLocalStoragePointer_Priv: + b MPU_pvTaskGetThreadLocalStoragePointerImpl + MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: + svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetSystemState +MPU_uxTaskGetSystemState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetSystemState_Unpriv + MPU_uxTaskGetSystemState_Priv: + b MPU_uxTaskGetSystemStateImpl + MPU_uxTaskGetSystemState_Unpriv: + svc #SYSTEM_CALL_uxTaskGetSystemState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetStackHighWaterMark +MPU_uxTaskGetStackHighWaterMark: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetStackHighWaterMark_Unpriv + MPU_uxTaskGetStackHighWaterMark_Priv: + b MPU_uxTaskGetStackHighWaterMarkImpl + MPU_uxTaskGetStackHighWaterMark_Unpriv: + svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetStackHighWaterMark2 +MPU_uxTaskGetStackHighWaterMark2: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetStackHighWaterMark2_Unpriv + MPU_uxTaskGetStackHighWaterMark2_Priv: + b MPU_uxTaskGetStackHighWaterMark2Impl + MPU_uxTaskGetStackHighWaterMark2_Unpriv: + svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2 +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetCurrentTaskHandle +MPU_xTaskGetCurrentTaskHandle: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetCurrentTaskHandle_Unpriv + MPU_xTaskGetCurrentTaskHandle_Priv: + b MPU_xTaskGetCurrentTaskHandleImpl + MPU_xTaskGetCurrentTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetSchedulerState +MPU_xTaskGetSchedulerState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetSchedulerState_Unpriv + MPU_xTaskGetSchedulerState_Priv: + b MPU_xTaskGetSchedulerStateImpl + MPU_xTaskGetSchedulerState_Unpriv: + svc #SYSTEM_CALL_xTaskGetSchedulerState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetTimeOutState +MPU_vTaskSetTimeOutState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetTimeOutState_Unpriv + MPU_vTaskSetTimeOutState_Priv: + b MPU_vTaskSetTimeOutStateImpl + MPU_vTaskSetTimeOutState_Unpriv: + svc #SYSTEM_CALL_vTaskSetTimeOutState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskCheckForTimeOut +MPU_xTaskCheckForTimeOut: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskCheckForTimeOut_Unpriv + MPU_xTaskCheckForTimeOut_Priv: + b MPU_xTaskCheckForTimeOutImpl + MPU_xTaskCheckForTimeOut_Unpriv: + svc #SYSTEM_CALL_xTaskCheckForTimeOut +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyEntry +MPU_xTaskGenericNotifyEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotify_Unpriv + MPU_xTaskGenericNotify_Priv: + b MPU_xTaskGenericNotifyImpl + MPU_xTaskGenericNotify_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotify +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyWaitEntry +MPU_xTaskGenericNotifyWaitEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotifyWait_Unpriv + MPU_xTaskGenericNotifyWait_Priv: + b MPU_xTaskGenericNotifyWaitImpl + MPU_xTaskGenericNotifyWait_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotifyWait +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGenericNotifyTake +MPU_ulTaskGenericNotifyTake: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGenericNotifyTake_Unpriv + MPU_ulTaskGenericNotifyTake_Priv: + b MPU_ulTaskGenericNotifyTakeImpl + MPU_ulTaskGenericNotifyTake_Unpriv: + svc #SYSTEM_CALL_ulTaskGenericNotifyTake +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyStateClear +MPU_xTaskGenericNotifyStateClear: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotifyStateClear_Unpriv + MPU_xTaskGenericNotifyStateClear_Priv: + b MPU_xTaskGenericNotifyStateClearImpl + MPU_xTaskGenericNotifyStateClear_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotifyStateClear +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGenericNotifyValueClear +MPU_ulTaskGenericNotifyValueClear: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGenericNotifyValueClear_Unpriv + MPU_ulTaskGenericNotifyValueClear_Priv: + b MPU_ulTaskGenericNotifyValueClearImpl + MPU_ulTaskGenericNotifyValueClear_Unpriv: + svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGenericSend +MPU_xQueueGenericSend: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGenericSend_Unpriv + MPU_xQueueGenericSend_Priv: + b MPU_xQueueGenericSendImpl + MPU_xQueueGenericSend_Unpriv: + svc #SYSTEM_CALL_xQueueGenericSend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxQueueMessagesWaiting +MPU_uxQueueMessagesWaiting: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxQueueMessagesWaiting_Unpriv + MPU_uxQueueMessagesWaiting_Priv: + b MPU_uxQueueMessagesWaitingImpl + MPU_uxQueueMessagesWaiting_Unpriv: + svc #SYSTEM_CALL_uxQueueMessagesWaiting +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxQueueSpacesAvailable +MPU_uxQueueSpacesAvailable: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxQueueSpacesAvailable_Unpriv + MPU_uxQueueSpacesAvailable_Priv: + b MPU_uxQueueSpacesAvailableImpl + MPU_uxQueueSpacesAvailable_Unpriv: + svc #SYSTEM_CALL_uxQueueSpacesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueReceive +MPU_xQueueReceive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueReceive_Unpriv + MPU_xQueueReceive_Priv: + b MPU_xQueueReceiveImpl + MPU_xQueueReceive_Unpriv: + svc #SYSTEM_CALL_xQueueReceive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueuePeek +MPU_xQueuePeek: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueuePeek_Unpriv + MPU_xQueuePeek_Priv: + b MPU_xQueuePeekImpl + MPU_xQueuePeek_Unpriv: + svc #SYSTEM_CALL_xQueuePeek +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueSemaphoreTake +MPU_xQueueSemaphoreTake: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueSemaphoreTake_Unpriv + MPU_xQueueSemaphoreTake_Priv: + b MPU_xQueueSemaphoreTakeImpl + MPU_xQueueSemaphoreTake_Unpriv: + svc #SYSTEM_CALL_xQueueSemaphoreTake +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGetMutexHolder +MPU_xQueueGetMutexHolder: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGetMutexHolder_Unpriv + MPU_xQueueGetMutexHolder_Priv: + b MPU_xQueueGetMutexHolderImpl + MPU_xQueueGetMutexHolder_Unpriv: + svc #SYSTEM_CALL_xQueueGetMutexHolder +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueTakeMutexRecursive +MPU_xQueueTakeMutexRecursive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueTakeMutexRecursive_Unpriv + MPU_xQueueTakeMutexRecursive_Priv: + b MPU_xQueueTakeMutexRecursiveImpl + MPU_xQueueTakeMutexRecursive_Unpriv: + svc #SYSTEM_CALL_xQueueTakeMutexRecursive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGiveMutexRecursive +MPU_xQueueGiveMutexRecursive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGiveMutexRecursive_Unpriv + MPU_xQueueGiveMutexRecursive_Priv: + b MPU_xQueueGiveMutexRecursiveImpl + MPU_xQueueGiveMutexRecursive_Unpriv: + svc #SYSTEM_CALL_xQueueGiveMutexRecursive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueSelectFromSet +MPU_xQueueSelectFromSet: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueSelectFromSet_Unpriv + MPU_xQueueSelectFromSet_Priv: + b MPU_xQueueSelectFromSetImpl + MPU_xQueueSelectFromSet_Unpriv: + svc #SYSTEM_CALL_xQueueSelectFromSet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueAddToSet +MPU_xQueueAddToSet: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueAddToSet_Unpriv + MPU_xQueueAddToSet_Priv: + b MPU_xQueueAddToSetImpl + MPU_xQueueAddToSet_Unpriv: + svc #SYSTEM_CALL_xQueueAddToSet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vQueueAddToRegistry +MPU_vQueueAddToRegistry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vQueueAddToRegistry_Unpriv + MPU_vQueueAddToRegistry_Priv: + b MPU_vQueueAddToRegistryImpl + MPU_vQueueAddToRegistry_Unpriv: + svc #SYSTEM_CALL_vQueueAddToRegistry +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vQueueUnregisterQueue +MPU_vQueueUnregisterQueue: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vQueueUnregisterQueue_Unpriv + MPU_vQueueUnregisterQueue_Priv: + b MPU_vQueueUnregisterQueueImpl + MPU_vQueueUnregisterQueue_Unpriv: + svc #SYSTEM_CALL_vQueueUnregisterQueue +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pcQueueGetName +MPU_pcQueueGetName: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pcQueueGetName_Unpriv + MPU_pcQueueGetName_Priv: + b MPU_pcQueueGetNameImpl + MPU_pcQueueGetName_Unpriv: + svc #SYSTEM_CALL_pcQueueGetName +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pvTimerGetTimerID +MPU_pvTimerGetTimerID: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pvTimerGetTimerID_Unpriv + MPU_pvTimerGetTimerID_Priv: + b MPU_pvTimerGetTimerIDImpl + MPU_pvTimerGetTimerID_Unpriv: + svc #SYSTEM_CALL_pvTimerGetTimerID +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTimerSetTimerID +MPU_vTimerSetTimerID: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTimerSetTimerID_Unpriv + MPU_vTimerSetTimerID_Priv: + b MPU_vTimerSetTimerIDImpl + MPU_vTimerSetTimerID_Unpriv: + svc #SYSTEM_CALL_vTimerSetTimerID +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerIsTimerActive +MPU_xTimerIsTimerActive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerIsTimerActive_Unpriv + MPU_xTimerIsTimerActive_Priv: + b MPU_xTimerIsTimerActiveImpl + MPU_xTimerIsTimerActive_Unpriv: + svc #SYSTEM_CALL_xTimerIsTimerActive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetTimerDaemonTaskHandle +MPU_xTimerGetTimerDaemonTaskHandle: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv + MPU_xTimerGetTimerDaemonTaskHandle_Priv: + b MPU_xTimerGetTimerDaemonTaskHandleImpl + MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGenericCommandFromTaskEntry +MPU_xTimerGenericCommandFromTaskEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGenericCommandFromTask_Unpriv + MPU_xTimerGenericCommandFromTask_Priv: + b MPU_xTimerGenericCommandFromTaskImpl + MPU_xTimerGenericCommandFromTask_Unpriv: + svc #SYSTEM_CALL_xTimerGenericCommandFromTask +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pcTimerGetName +MPU_pcTimerGetName: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pcTimerGetName_Unpriv + MPU_pcTimerGetName_Priv: + b MPU_pcTimerGetNameImpl + MPU_pcTimerGetName_Unpriv: + svc #SYSTEM_CALL_pcTimerGetName +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTimerSetReloadMode +MPU_vTimerSetReloadMode: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTimerSetReloadMode_Unpriv + MPU_vTimerSetReloadMode_Priv: + b MPU_vTimerSetReloadModeImpl + MPU_vTimerSetReloadMode_Unpriv: + svc #SYSTEM_CALL_vTimerSetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetReloadMode +MPU_xTimerGetReloadMode: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetReloadMode_Unpriv + MPU_xTimerGetReloadMode_Priv: + b MPU_xTimerGetReloadModeImpl + MPU_xTimerGetReloadMode_Unpriv: + svc #SYSTEM_CALL_xTimerGetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTimerGetReloadMode +MPU_uxTimerGetReloadMode: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTimerGetReloadMode_Unpriv + MPU_uxTimerGetReloadMode_Priv: + b MPU_uxTimerGetReloadModeImpl + MPU_uxTimerGetReloadMode_Unpriv: + svc #SYSTEM_CALL_uxTimerGetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetPeriod +MPU_xTimerGetPeriod: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetPeriod_Unpriv + MPU_xTimerGetPeriod_Priv: + b MPU_xTimerGetPeriodImpl + MPU_xTimerGetPeriod_Unpriv: + svc #SYSTEM_CALL_xTimerGetPeriod +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetExpiryTime +MPU_xTimerGetExpiryTime: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetExpiryTime_Unpriv + MPU_xTimerGetExpiryTime_Priv: + b MPU_xTimerGetExpiryTimeImpl + MPU_xTimerGetExpiryTime_Unpriv: + svc #SYSTEM_CALL_xTimerGetExpiryTime +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupWaitBitsEntry +MPU_xEventGroupWaitBitsEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupWaitBits_Unpriv + MPU_xEventGroupWaitBits_Priv: + b MPU_xEventGroupWaitBitsImpl + MPU_xEventGroupWaitBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupWaitBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupClearBits +MPU_xEventGroupClearBits: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupClearBits_Unpriv + MPU_xEventGroupClearBits_Priv: + b MPU_xEventGroupClearBitsImpl + MPU_xEventGroupClearBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupClearBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupSetBits +MPU_xEventGroupSetBits: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupSetBits_Unpriv + MPU_xEventGroupSetBits_Priv: + b MPU_xEventGroupSetBitsImpl + MPU_xEventGroupSetBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupSetBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupSync +MPU_xEventGroupSync: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupSync_Unpriv + MPU_xEventGroupSync_Priv: + b MPU_xEventGroupSyncImpl + MPU_xEventGroupSync_Unpriv: + svc #SYSTEM_CALL_xEventGroupSync +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxEventGroupGetNumber +MPU_uxEventGroupGetNumber: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxEventGroupGetNumber_Unpriv + MPU_uxEventGroupGetNumber_Priv: + b MPU_uxEventGroupGetNumberImpl + MPU_uxEventGroupGetNumber_Unpriv: + svc #SYSTEM_CALL_uxEventGroupGetNumber +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vEventGroupSetNumber +MPU_vEventGroupSetNumber: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vEventGroupSetNumber_Unpriv + MPU_vEventGroupSetNumber_Priv: + b MPU_vEventGroupSetNumberImpl + MPU_vEventGroupSetNumber_Unpriv: + svc #SYSTEM_CALL_vEventGroupSetNumber +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSend +MPU_xStreamBufferSend: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSend_Unpriv + MPU_xStreamBufferSend_Priv: + b MPU_xStreamBufferSendImpl + MPU_xStreamBufferSend_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferReceive +MPU_xStreamBufferReceive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferReceive_Unpriv + MPU_xStreamBufferReceive_Priv: + b MPU_xStreamBufferReceiveImpl + MPU_xStreamBufferReceive_Unpriv: + svc #SYSTEM_CALL_xStreamBufferReceive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferIsFull +MPU_xStreamBufferIsFull: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferIsFull_Unpriv + MPU_xStreamBufferIsFull_Priv: + b MPU_xStreamBufferIsFullImpl + MPU_xStreamBufferIsFull_Unpriv: + svc #SYSTEM_CALL_xStreamBufferIsFull +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferIsEmpty +MPU_xStreamBufferIsEmpty: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferIsEmpty_Unpriv + MPU_xStreamBufferIsEmpty_Priv: + b MPU_xStreamBufferIsEmptyImpl + MPU_xStreamBufferIsEmpty_Unpriv: + svc #SYSTEM_CALL_xStreamBufferIsEmpty +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSpacesAvailable +MPU_xStreamBufferSpacesAvailable: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSpacesAvailable_Unpriv + MPU_xStreamBufferSpacesAvailable_Priv: + b MPU_xStreamBufferSpacesAvailableImpl + MPU_xStreamBufferSpacesAvailable_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSpacesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferBytesAvailable +MPU_xStreamBufferBytesAvailable: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferBytesAvailable_Unpriv + MPU_xStreamBufferBytesAvailable_Priv: + b MPU_xStreamBufferBytesAvailableImpl + MPU_xStreamBufferBytesAvailable_Unpriv: + svc #SYSTEM_CALL_xStreamBufferBytesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSetTriggerLevel +MPU_xStreamBufferSetTriggerLevel: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSetTriggerLevel_Unpriv + MPU_xStreamBufferSetTriggerLevel_Priv: + b MPU_xStreamBufferSetTriggerLevelImpl + MPU_xStreamBufferSetTriggerLevel_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferNextMessageLengthBytes +MPU_xStreamBufferNextMessageLengthBytes: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv + MPU_xStreamBufferNextMessageLengthBytes_Priv: + b MPU_xStreamBufferNextMessageLengthBytesImpl + MPU_xStreamBufferNextMessageLengthBytes_Unpriv: + svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes +/*-----------------------------------------------------------*/ + +/* Default weak implementations in case one is not available from + * mpu_wrappers because of config options. */ + + PUBWEAK MPU_xTaskDelayUntilImpl +MPU_xTaskDelayUntilImpl: + b MPU_xTaskDelayUntilImpl + + PUBWEAK MPU_xTaskAbortDelayImpl +MPU_xTaskAbortDelayImpl: + b MPU_xTaskAbortDelayImpl + + PUBWEAK MPU_vTaskDelayImpl +MPU_vTaskDelayImpl: + b MPU_vTaskDelayImpl + + PUBWEAK MPU_uxTaskPriorityGetImpl +MPU_uxTaskPriorityGetImpl: + b MPU_uxTaskPriorityGetImpl + + PUBWEAK MPU_eTaskGetStateImpl +MPU_eTaskGetStateImpl: + b MPU_eTaskGetStateImpl + + PUBWEAK MPU_vTaskGetInfoImpl +MPU_vTaskGetInfoImpl: + b MPU_vTaskGetInfoImpl + + PUBWEAK MPU_xTaskGetIdleTaskHandleImpl +MPU_xTaskGetIdleTaskHandleImpl: + b MPU_xTaskGetIdleTaskHandleImpl + + PUBWEAK MPU_vTaskSuspendImpl +MPU_vTaskSuspendImpl: + b MPU_vTaskSuspendImpl + + PUBWEAK MPU_vTaskResumeImpl +MPU_vTaskResumeImpl: + b MPU_vTaskResumeImpl + + PUBWEAK MPU_xTaskGetTickCountImpl +MPU_xTaskGetTickCountImpl: + b MPU_xTaskGetTickCountImpl + + PUBWEAK MPU_uxTaskGetNumberOfTasksImpl +MPU_uxTaskGetNumberOfTasksImpl: + b MPU_uxTaskGetNumberOfTasksImpl + + PUBWEAK MPU_ulTaskGetRunTimeCounterImpl +MPU_ulTaskGetRunTimeCounterImpl: + b MPU_ulTaskGetRunTimeCounterImpl + + PUBWEAK MPU_ulTaskGetRunTimePercentImpl +MPU_ulTaskGetRunTimePercentImpl: + b MPU_ulTaskGetRunTimePercentImpl + + PUBWEAK MPU_ulTaskGetIdleRunTimePercentImpl +MPU_ulTaskGetIdleRunTimePercentImpl: + b MPU_ulTaskGetIdleRunTimePercentImpl + + PUBWEAK MPU_ulTaskGetIdleRunTimeCounterImpl +MPU_ulTaskGetIdleRunTimeCounterImpl: + b MPU_ulTaskGetIdleRunTimeCounterImpl + + PUBWEAK MPU_vTaskSetApplicationTaskTagImpl +MPU_vTaskSetApplicationTaskTagImpl: + b MPU_vTaskSetApplicationTaskTagImpl + + PUBWEAK MPU_xTaskGetApplicationTaskTagImpl +MPU_xTaskGetApplicationTaskTagImpl: + b MPU_xTaskGetApplicationTaskTagImpl + + PUBWEAK MPU_vTaskSetThreadLocalStoragePointerImpl +MPU_vTaskSetThreadLocalStoragePointerImpl: + b MPU_vTaskSetThreadLocalStoragePointerImpl + + PUBWEAK MPU_pvTaskGetThreadLocalStoragePointerImpl +MPU_pvTaskGetThreadLocalStoragePointerImpl: + b MPU_pvTaskGetThreadLocalStoragePointerImpl + + PUBWEAK MPU_uxTaskGetSystemStateImpl +MPU_uxTaskGetSystemStateImpl: + b MPU_uxTaskGetSystemStateImpl + + PUBWEAK MPU_uxTaskGetStackHighWaterMarkImpl +MPU_uxTaskGetStackHighWaterMarkImpl: + b MPU_uxTaskGetStackHighWaterMarkImpl + + PUBWEAK MPU_uxTaskGetStackHighWaterMark2Impl +MPU_uxTaskGetStackHighWaterMark2Impl: + b MPU_uxTaskGetStackHighWaterMark2Impl + + PUBWEAK MPU_xTaskGetCurrentTaskHandleImpl +MPU_xTaskGetCurrentTaskHandleImpl: + b MPU_xTaskGetCurrentTaskHandleImpl + + PUBWEAK MPU_xTaskGetSchedulerStateImpl +MPU_xTaskGetSchedulerStateImpl: + b MPU_xTaskGetSchedulerStateImpl + + PUBWEAK MPU_vTaskSetTimeOutStateImpl +MPU_vTaskSetTimeOutStateImpl: + b MPU_vTaskSetTimeOutStateImpl + + PUBWEAK MPU_xTaskCheckForTimeOutImpl +MPU_xTaskCheckForTimeOutImpl: + b MPU_xTaskCheckForTimeOutImpl + + PUBWEAK MPU_xTaskGenericNotifyImpl +MPU_xTaskGenericNotifyImpl: + b MPU_xTaskGenericNotifyImpl + + PUBWEAK MPU_xTaskGenericNotifyWaitImpl +MPU_xTaskGenericNotifyWaitImpl: + b MPU_xTaskGenericNotifyWaitImpl + + PUBWEAK MPU_ulTaskGenericNotifyTakeImpl +MPU_ulTaskGenericNotifyTakeImpl: + b MPU_ulTaskGenericNotifyTakeImpl + + PUBWEAK MPU_xTaskGenericNotifyStateClearImpl +MPU_xTaskGenericNotifyStateClearImpl: + b MPU_xTaskGenericNotifyStateClearImpl + + PUBWEAK MPU_ulTaskGenericNotifyValueClearImpl +MPU_ulTaskGenericNotifyValueClearImpl: + b MPU_ulTaskGenericNotifyValueClearImpl + + PUBWEAK MPU_xQueueGenericSendImpl +MPU_xQueueGenericSendImpl: + b MPU_xQueueGenericSendImpl + + PUBWEAK MPU_uxQueueMessagesWaitingImpl +MPU_uxQueueMessagesWaitingImpl: + b MPU_uxQueueMessagesWaitingImpl + + PUBWEAK MPU_uxQueueSpacesAvailableImpl +MPU_uxQueueSpacesAvailableImpl: + b MPU_uxQueueSpacesAvailableImpl + + PUBWEAK MPU_xQueueReceiveImpl +MPU_xQueueReceiveImpl: + b MPU_xQueueReceiveImpl + + PUBWEAK MPU_xQueuePeekImpl +MPU_xQueuePeekImpl: + b MPU_xQueuePeekImpl + + PUBWEAK MPU_xQueueSemaphoreTakeImpl +MPU_xQueueSemaphoreTakeImpl: + b MPU_xQueueSemaphoreTakeImpl + + PUBWEAK MPU_xQueueGetMutexHolderImpl +MPU_xQueueGetMutexHolderImpl: + b MPU_xQueueGetMutexHolderImpl + + PUBWEAK MPU_xQueueTakeMutexRecursiveImpl +MPU_xQueueTakeMutexRecursiveImpl: + b MPU_xQueueTakeMutexRecursiveImpl + + PUBWEAK MPU_xQueueGiveMutexRecursiveImpl +MPU_xQueueGiveMutexRecursiveImpl: + b MPU_xQueueGiveMutexRecursiveImpl + + PUBWEAK MPU_xQueueSelectFromSetImpl +MPU_xQueueSelectFromSetImpl: + b MPU_xQueueSelectFromSetImpl + + PUBWEAK MPU_xQueueAddToSetImpl +MPU_xQueueAddToSetImpl: + b MPU_xQueueAddToSetImpl + + PUBWEAK MPU_vQueueAddToRegistryImpl +MPU_vQueueAddToRegistryImpl: + b MPU_vQueueAddToRegistryImpl + + PUBWEAK MPU_vQueueUnregisterQueueImpl +MPU_vQueueUnregisterQueueImpl: + b MPU_vQueueUnregisterQueueImpl + + PUBWEAK MPU_pcQueueGetNameImpl +MPU_pcQueueGetNameImpl: + b MPU_pcQueueGetNameImpl + + PUBWEAK MPU_pvTimerGetTimerIDImpl +MPU_pvTimerGetTimerIDImpl: + b MPU_pvTimerGetTimerIDImpl + + PUBWEAK MPU_vTimerSetTimerIDImpl +MPU_vTimerSetTimerIDImpl: + b MPU_vTimerSetTimerIDImpl + + PUBWEAK MPU_xTimerIsTimerActiveImpl +MPU_xTimerIsTimerActiveImpl: + b MPU_xTimerIsTimerActiveImpl + + PUBWEAK MPU_xTimerGetTimerDaemonTaskHandleImpl +MPU_xTimerGetTimerDaemonTaskHandleImpl: + b MPU_xTimerGetTimerDaemonTaskHandleImpl + + PUBWEAK MPU_xTimerGenericCommandFromTaskImpl +MPU_xTimerGenericCommandFromTaskImpl: + b MPU_xTimerGenericCommandFromTaskImpl + + PUBWEAK MPU_pcTimerGetNameImpl +MPU_pcTimerGetNameImpl: + b MPU_pcTimerGetNameImpl + + PUBWEAK MPU_vTimerSetReloadModeImpl +MPU_vTimerSetReloadModeImpl: + b MPU_vTimerSetReloadModeImpl + + PUBWEAK MPU_xTimerGetReloadModeImpl +MPU_xTimerGetReloadModeImpl: + b MPU_xTimerGetReloadModeImpl + + PUBWEAK MPU_uxTimerGetReloadModeImpl +MPU_uxTimerGetReloadModeImpl: + b MPU_uxTimerGetReloadModeImpl + + PUBWEAK MPU_xTimerGetPeriodImpl +MPU_xTimerGetPeriodImpl: + b MPU_xTimerGetPeriodImpl + + PUBWEAK MPU_xTimerGetExpiryTimeImpl +MPU_xTimerGetExpiryTimeImpl: + b MPU_xTimerGetExpiryTimeImpl + + PUBWEAK MPU_xEventGroupWaitBitsImpl +MPU_xEventGroupWaitBitsImpl: + b MPU_xEventGroupWaitBitsImpl + + PUBWEAK MPU_xEventGroupClearBitsImpl +MPU_xEventGroupClearBitsImpl: + b MPU_xEventGroupClearBitsImpl + + PUBWEAK MPU_xEventGroupSetBitsImpl +MPU_xEventGroupSetBitsImpl: + b MPU_xEventGroupSetBitsImpl + + PUBWEAK MPU_xEventGroupSyncImpl +MPU_xEventGroupSyncImpl: + b MPU_xEventGroupSyncImpl + + PUBWEAK MPU_uxEventGroupGetNumberImpl +MPU_uxEventGroupGetNumberImpl: + b MPU_uxEventGroupGetNumberImpl + + PUBWEAK MPU_vEventGroupSetNumberImpl +MPU_vEventGroupSetNumberImpl: + b MPU_vEventGroupSetNumberImpl + + PUBWEAK MPU_xStreamBufferSendImpl +MPU_xStreamBufferSendImpl: + b MPU_xStreamBufferSendImpl + + PUBWEAK MPU_xStreamBufferReceiveImpl +MPU_xStreamBufferReceiveImpl: + b MPU_xStreamBufferReceiveImpl + + PUBWEAK MPU_xStreamBufferIsFullImpl +MPU_xStreamBufferIsFullImpl: + b MPU_xStreamBufferIsFullImpl + + PUBWEAK MPU_xStreamBufferIsEmptyImpl +MPU_xStreamBufferIsEmptyImpl: + b MPU_xStreamBufferIsEmptyImpl + + PUBWEAK MPU_xStreamBufferSpacesAvailableImpl +MPU_xStreamBufferSpacesAvailableImpl: + b MPU_xStreamBufferSpacesAvailableImpl + + PUBWEAK MPU_xStreamBufferBytesAvailableImpl +MPU_xStreamBufferBytesAvailableImpl: + b MPU_xStreamBufferBytesAvailableImpl + + PUBWEAK MPU_xStreamBufferSetTriggerLevelImpl +MPU_xStreamBufferSetTriggerLevelImpl: + b MPU_xStreamBufferSetTriggerLevelImpl + + PUBWEAK MPU_xStreamBufferNextMessageLengthBytesImpl +MPU_xStreamBufferNextMessageLengthBytesImpl: + b MPU_xStreamBufferNextMessageLengthBytesImpl + +/*-----------------------------------------------------------*/ + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + END diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c new file mode 100644 index 000000000..76d2b2445 --- /dev/null +++ b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c @@ -0,0 +1,2280 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024-2025 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU includes. */ +#include "mpu_wrappers.h" +#include "mpu_syscall_numbers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration settings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to check the validity of an interrupt priority. + */ +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) ) +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used during system call enter and exit. + */ +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Offsets in the stack to the parameters when inside the SVC handler. + */ +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +#if ( portARMV8M_MINOR_VERSION >= 1 ) + + /* Enable Privileged eXecute Never MPU attribute for the selected memory + * region. */ + #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL ) +#endif /* portARMV8M_MINOR_VERSION >= 1 */ + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Extract first address of the MPU region as encoded in the + * RBAR (Region Base Address Register) value. */ +#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \ + ( ( rbar ) & portMPU_RBAR_ADDRESS_MASK ) + +/* Extract last address of the MPU region as encoded in the + * RLAR (Region Limit Address Register) value. */ +#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \ + ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK ) + +/* Does addr lies within [start, end] address range? */ +#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \ + ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) ) + +/* Is the access request satisfied by the available permissions? */ +#define portIS_AUTHORIZED( accessRequest, permissions ) \ + ( ( ( permissions ) & ( accessRequest ) ) == accessRequest ) + +/* Max value that fits in a uint32_t type. */ +#define portUINT32_MAX ( ~( ( uint32_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. + */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 + +/** + * @brief Constants required to check and configure PACBTI security feature implementation. + */ +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) ) + + #define portCONTROL_UPAC_EN ( 1UL << 7UL ) + #define portCONTROL_PAC_EN ( 1UL << 6UL ) + #define portCONTROL_UBTI_EN ( 1UL << 5UL ) + #define portCONTROL_BTI_EN ( 1UL << 4UL ) + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Extract MPU region's access permissions from the Region Base Address + * Register (RBAR) value. + * + * @param ulRBARValue RBAR value for the MPU region. + * + * @return uint32_t Access permissions. + */ + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + + /** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + /** + * @brief Configures PACBTI features. + * + * This function configures the Pointer Authentication, and Branch Target + * Identification security features as per the user configuration. It returns + * the value of the special purpose CONTROL register accordingly, and optionally + * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M + * architecture based) target supports PACBTI security feature. + * + * @param xWriteControlRegister Used to control whether the special purpose + * CONTROL register should be updated or not. + * + * @return CONTROL register value according to the configured PACBTI option. + */ + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the system call stack so that upon returning from + * SVC, the system call stack is used. + * + * @param pulTaskStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + * @param ucSystemCallNumber The system call number of the system call. + */ + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Raise SVC for exiting from a system call. + */ + void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief This variable is set to pdTRUE when the scheduler is started. + */ + PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + + /** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +/** + * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + /** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + + /** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + + /** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the cpsid instruction + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessPermissions = 0; + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_ONLY ) + { + ulAccessPermissions = tskMPU_READ_PERMISSION; + } + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_WRITE ) + { + ulAccessPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION ); + } + + return ulAccessPermissions; + } + +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } + +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ portOFFSET_TO_PC ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ]; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulSystemCallStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the system call section (i.e. application is + * not raising SVC directly). + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as + * it is non-NULL only during the execution of a system call (i.e. + * between system call enter and exit). + * 3. System call is not for a kernel API disabled by the configuration + * in FreeRTOSConfig.h. + * 4. We do not need to check that ucSystemCallNumber is within range + * because the assembly SVC handler checks that before calling + * this function. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) && + ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) ) + { + pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the system call stack for the stack frame. */ + pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulSystemCallStack[ i ] = pulTaskStack[ i ]; + } + + /* Store the value of the Link Register before the SVC was raised. + * It contains the address of the caller of the System Call entry + * point (i.e. the caller of the MPU_). We need to restore it + * when we exit from the system call. */ + pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; + + /* Store the value of the PSPLIM register before the SVC was raised. + * We need to restore it when we exit from the system call. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* Use the pulSystemCallStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif + + /* Start executing the system call upon returning from this handler. */ + pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; + + /* Raise a request to exit from the system call upon finishing the + * system call. */ + pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; + + /* Remember the location where we should copy the stack frame when we exit from + * the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize; + + /* Record if the hardware used padding to force the stack pointer + * to be double word aligned. */ + if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK ) + { + pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG; + } + else + { + pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG ); + } + + /* We ensure in pxPortInitialiseStack that the system call stack is + * double word aligned and therefore, there is no need of padding. + * Clear the bit[9] of stacked xPSR. */ + pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + + /* Raise the privilege for the duration of the system call. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " bics r0, r1 \n" /* Clear nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */ + { + __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulTaskStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the privileged code (i.e. application is not + * raising SVC directly). This SVC is only raised from + * vRequestSystemCallExit which is in the privileged code section. + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL - + * this means that we previously entered a system call and the + * application is not attempting to exit without entering a system + * call. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) ) + { + pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the task stack for the stack frame. */ + pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulTaskStack[ i ] = pulSystemCallStack[ i ]; + } + + /* Use the pulTaskStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) ); + + /* Return to the caller of the System Call entry point (i.e. the + * caller of the MPU_). */ + pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + /* Ensure that LR has a valid value.*/ + pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + + /* Restore the PSPLIM register to what it was at the time of + * system call entry. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* If the hardware used padding to force the stack pointer + * to be double word aligned, set the stacked xPSR bit[9], + * otherwise clear it. */ + if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG ) + { + pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK; + } + else + { + pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + } + + /* This is not NULL only for the duration of the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; + + /* Drop the privilege before returning to the thread mode. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " orrs r0, r1 \n" /* Set nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xTaskIsPrivileged = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xTaskIsPrivileged = pdTRUE; + } + + return xTaskIsPrivileged; + } + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged, + xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulIndex = 0; + uint32_t ulControl = 0x0; + + xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ + ulIndex++; + + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + ulIndex++; + + #if ( configENABLE_TRUSTZONE == 1 ) + { + xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */ + ulIndex++; + } + #endif /* configENABLE_TRUSTZONE */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + ulIndex++; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Check PACBTI security feature configuration before pushing the + * CONTROL register's value on task's TCB. */ + ulControl = prvConfigurePACBTI( pdFALSE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + if( xRunPrivileged == pdTRUE ) + { + xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + else + { + xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG ); + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ + ulIndex++; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + { + /* Ensure that the system call stack is double word aligned. */ + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) + + ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + /* This is not NULL only for the duration of a system call. */ + xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL; + } + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ]; + ulIndex++; + } + } + #endif /* configENABLE_PAC */ + + return &( xMPUSettings->ulContext[ ulIndex ] ); + } + +#else /* configENABLE_MPU */ + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ + { + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + pxTopOfStack--; + *pxTopOfStack = ulTaskPacKey[ i ]; + } + } + #endif /* configENABLE_PAC */ + + return pxTopOfStack; + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Set the CONTROL register value based on PACBTI security feature + * configuration before starting the first task. */ + ( void ) prvConfigurePACBTI( pdTRUE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + { + xSchedulerRunning = pdTRUE; + } + #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + configSTACK_DEPTH_TYPE uxStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( uxStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* PXN. */ + #if ( portARMV8M_MINOR_VERSION >= 1 ) + { + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ); + } + } + #endif /* portARMV8M_MINOR_VERSION >= 1 */ + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, + uint32_t ulBufferLength, + uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */ + + { + uint32_t i, ulBufferStartAddress, ulBufferEndAddress; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE ) + { + ulBufferStartAddress = ( uint32_t ) pvBuffer; + ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL ); + + for( i = 0; i < portTOTAL_NUM_REGIONS; i++ ) + { + /* Is the MPU region enabled? */ + if( ( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR & portMPU_RLAR_REGION_ENABLE ) == portMPU_RLAR_REGION_ENABLE ) + { + if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_AUTHORIZED( ulAccessRequested, + prvGetRegionAccessPermissions( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ) ) ) + { + xAccessGranted = pdTRUE; + break; + } + } + } + } + } + + return xAccessGranted; + } + +#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings; + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else + { + xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 ) + { + xAccessGranted = pdTRUE; + } + } + } + + return xAccessGranted; + } + + #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + ( void ) lInternalIndexOfKernelObject; + + /* If Access Control List feature is not used, all the tasks have + * access to all the kernel objects. */ + return pdTRUE; + } + + #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + { + uint32_t ulControl = 0x0; + + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); + + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; + + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.h b/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.h new file mode 100644 index 000000000..b7021b024 --- /dev/null +++ b/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kernel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s b/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s new file mode 100644 index 000000000..ba6e8e915 --- /dev/null +++ b/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s @@ -0,0 +1,456 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" + +/* System call numbers includes. */ +#include "mpu_syscall_numbers.h" + +#ifndef configUSE_MPU_WRAPPERS_V1 + #define configUSE_MPU_WRAPPERS_V1 0 +#endif + + EXTERN pxCurrentTCB + EXTERN vTaskSwitchContext + EXTERN vPortSVCHandler_C +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + EXTERN vSystemCallEnter + EXTERN vSystemCallExit +#endif + + PUBLIC xIsPrivileged + PUBLIC vResetPrivilege + PUBLIC vRestoreContextOfFirstTask + PUBLIC vRaisePrivilege + PUBLIC vStartFirstTask + PUBLIC ulSetInterruptMask + PUBLIC vClearInterruptMask + PUBLIC PendSV_Handler + PUBLIC SVC_Handler +/*-----------------------------------------------------------*/ + +/*---------------- Unprivileged Functions -------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION .text:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +xIsPrivileged: + mrs r0, control /* r0 = CONTROL. */ + tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + ite ne + movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vResetPrivilege: + mrs r0, control /* r0 = CONTROL. */ + orr r0, r0, #1 /* r0 = r0 | 1. */ + msr control, r0 /* CONTROL = r0. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +/*----------------- Privileged Functions --------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION privileged_functions:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +vRestoreContextOfFirstTask: + program_mpu_first_task: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r2] /* r0 = pxCurrentTCB. */ + + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + str r2, [r1] /* Disable MPU. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r1, [r2] /* Program MAIR0. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + + movs r3, #4 /* r3 = 4. */ + str r3, [r1] /* Program RNR = 4. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + #if ( configTOTAL_MPU_REGIONS == 16 ) + movs r3, #8 /* r3 = 8. */ + str r3, [r1] /* Program RNR = 8. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + movs r3, #12 /* r3 = 12. */ + str r3, [r1] /* Program RNR = 12. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + orr r2, #1 /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */ + str r2, [r1] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + + restore_context_first_task: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r2] /* r0 = pxCurrentTCB.*/ + ldr r1, [r0] /* r1 = Location of saved context in TCB. */ + + restore_special_regs_first_task: + #if ( configENABLE_PAC == 1 ) + ldmdb r1!, {r2-r5} /* Read task's dedicated PAC key from the task's context. */ + msr PAC_KEY_P_0, r2 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_1, r3 + msr PAC_KEY_P_2, r4 + msr PAC_KEY_P_3, r5 + clrm {r2-r5} /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + ldmdb r1!, {r2-r4, lr} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */ + msr psp, r2 + msr psplim, r3 + msr control, r4 + + restore_general_regs_first_task: + ldmdb r1!, {r4-r11} /* r4-r11 contain hardware saved context. */ + stmia r2!, {r4-r11} /* Copy the hardware saved context on the task stack. */ + ldmdb r1!, {r4-r11} /* r4-r11 restored. */ + + restore_context_done_first_task: + str r1, [r0] /* Save the location where the context should be saved next as the first member of TCB. */ + mov r0, #0 + msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ + bx lr + +#else /* configENABLE_MPU */ + +vRestoreContextOfFirstTask: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + +#if ( configENABLE_PAC == 1 ) + ldmia r0!, {r1-r4} /* Read task's dedicated PAC key from stack. */ + msr PAC_KEY_P_3, r1 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_2, r2 + msr PAC_KEY_P_1, r3 + msr PAC_KEY_P_0, r4 + clrm {r1-r4} /* Clear r1-r4. */ +#endif /* configENABLE_PAC */ + + ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */ + msr psplim, r1 /* Set this task's PSPLIM value. */ + mrs r1, control /* Obtain current control register value. */ + orrs r1, r1, #2 /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */ + msr control, r1 /* Write back the new control register value. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + mov r0, #0 + msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ + bx r2 /* Finally, branch to EXC_RETURN. */ + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +vRaisePrivilege: + mrs r0, control /* Read the CONTROL register. */ + bic r0, r0, #1 /* Clear the bit 0. */ + msr control, r0 /* Write back the new CONTROL value. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vStartFirstTask: + ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */ + ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */ + ldr r0, [r0] /* The first entry in vector table is stack pointer. */ + msr msp, r0 /* Set the MSP back to the start of the stack. */ + cpsie i /* Globally enable interrupts. */ + cpsie f + dsb + isb + svc 102 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */ +/*-----------------------------------------------------------*/ + +ulSetInterruptMask: + mrs r0, basepri /* r0 = basepri. Return original basepri value. */ + mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r1 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vClearInterruptMask: + msr basepri, r0 /* basepri = ulMask. */ + dsb + isb + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +PendSV_Handler: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r2] /* r0 = pxCurrentTCB. */ + ldr r1, [r0] /* r1 = Location in TCB where the context should be saved. */ + mrs r2, psp /* r2 = PSP. */ + + save_general_regs: + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + add r2, r2, #0x20 /* Move r2 to location where s0 is saved. */ + tst lr, #0x10 + ittt eq + vstmiaeq r1!, {s16-s31} /* Store s16-s31. */ + vldmiaeq r2, {s0-s16} /* Copy hardware saved FP context into s0-s16. */ + vstmiaeq r1!, {s0-s16} /* Store hardware saved FP context. */ + sub r2, r2, #0x20 /* Set r2 back to the location of hardware saved context. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + stmia r1!, {r4-r11} /* Store r4-r11. */ + ldmia r2, {r4-r11} /* Copy the hardware saved context into r4-r11. */ + stmia r1!, {r4-r11} /* Store the hardware saved context. */ + + save_special_regs: + mrs r3, psplim /* r3 = PSPLIM. */ + mrs r4, control /* r4 = CONTROL. */ + stmia r1!, {r2-r4, lr} /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ + #if ( configENABLE_PAC == 1 ) + mrs r2, PAC_KEY_P_0 /* Read task's dedicated PAC key from the PAC key registers. */ + mrs r3, PAC_KEY_P_1 + mrs r4, PAC_KEY_P_2 + mrs r5, PAC_KEY_P_3 + stmia r1!, {r2-r5} /* Store the task's dedicated PAC key on the task's context. */ + clrm {r2-r5} /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + + str r1, [r0] /* Save the location from where the context should be restored as the first member of TCB. */ + + select_next_task: + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bl vTaskSwitchContext + mov r0, #0 /* r0 = 0. */ + msr basepri, r0 /* Enable interrupts. */ + + program_mpu: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r2] /* r0 = pxCurrentTCB. */ + + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + str r2, [r1] /* Disable MPU. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r1, [r2] /* Program MAIR0. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + + movs r3, #4 /* r3 = 4. */ + str r3, [r1] /* Program RNR = 4. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + #if ( configTOTAL_MPU_REGIONS == 16 ) + movs r3, #8 /* r3 = 8. */ + str r3, [r1] /* Program RNR = 8. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + movs r3, #12 /* r3 = 12. */ + str r3, [r1] /* Program RNR = 12. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + orr r2, #1 /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */ + str r2, [r1] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + + restore_context: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r2] /* r0 = pxCurrentTCB.*/ + ldr r1, [r0] /* r1 = Location of saved context in TCB. */ + + restore_special_regs: + #if ( configENABLE_PAC == 1 ) + ldmdb r1!, {r2-r5} /* Read task's dedicated PAC key from the task's context. */ + msr PAC_KEY_P_0, r2 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_1, r3 + msr PAC_KEY_P_2, r4 + msr PAC_KEY_P_3, r5 + clrm {r2-r5} /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + ldmdb r1!, {r2-r4, lr} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */ + msr psp, r2 + msr psplim, r3 + msr control, r4 + + restore_general_regs: + ldmdb r1!, {r4-r11} /* r4-r11 contain hardware saved context. */ + stmia r2!, {r4-r11} /* Copy the hardware saved context on the task stack. */ + ldmdb r1!, {r4-r11} /* r4-r11 restored. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 + ittt eq + vldmdbeq r1!, {s0-s16} /* s0-s16 contain hardware saved FP context. */ + vstmiaeq r2!, {s0-s16} /* Copy hardware saved FP context on the task stack. */ + vldmdbeq r1!, {s16-s31} /* Restore s16-s31. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + + restore_context_done: + str r1, [r0] /* Save the location where the context should be saved next as the first member of TCB. */ + bx lr + +#else /* configENABLE_MPU */ + +PendSV_Handler: + mrs r0, psp /* Read PSP in r0. */ +#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + it eq + vstmdbeq r0!, {s16-s31} /* Store the additional FP context registers which are not saved automatically. */ +#endif /* configENABLE_FPU || configENABLE_MVE */ + + mrs r2, psplim /* r2 = PSPLIM. */ + mov r3, lr /* r3 = LR/EXC_RETURN. */ + stmdb r0!, {r2-r11} /* Store on the stack - PSPLIM, LR and registers that are not automatically. */ + +#if ( configENABLE_PAC == 1 ) + mrs r1, PAC_KEY_P_3 /* Read task's dedicated PAC key from the PAC key registers. */ + mrs r2, PAC_KEY_P_2 + mrs r3, PAC_KEY_P_1 + mrs r4, PAC_KEY_P_0 + stmdb r0!, {r1-r4} /* Store the task's dedicated PAC key on the stack. */ + clrm {r1-r4} /* Clear r1-r4. */ +#endif /* configENABLE_PAC */ + + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + str r0, [r1] /* Save the new top of stack in TCB. */ + + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bl vTaskSwitchContext + mov r0, #0 /* r0 = 0. */ + msr basepri, r0 /* Enable interrupts. */ + + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ + +#if ( configENABLE_PAC == 1 ) + ldmia r0!, {r2-r5} /* Read task's dedicated PAC key from stack. */ + msr PAC_KEY_P_3, r2 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_2, r3 + msr PAC_KEY_P_1, r4 + msr PAC_KEY_P_0, r5 + clrm {r2-r5} /* Clear r2-r5. */ +#endif /* configENABLE_PAC */ + + ldmia r0!, {r2-r11} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */ + +#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst r3, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + it eq + vldmiaeq r0!, {s16-s31} /* Restore the additional FP context registers which are not restored automatically. */ +#endif /* configENABLE_FPU || configENABLE_MVE */ + + msr psplim, r2 /* Restore the PSPLIM register value for the task. */ + msr psp, r0 /* Remember the new top of stack for the task. */ + bx r3 + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + +SVC_Handler: + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + + ldr r1, [r0, #24] + ldrb r2, [r1, #-2] + cmp r2, #NUM_SYSTEM_CALLS + blt syscall_enter + cmp r2, #104 /* portSVC_SYSTEM_CALL_EXIT. */ + beq syscall_exit + b vPortSVCHandler_C + + syscall_enter: + mov r1, lr + b vSystemCallEnter + + syscall_exit: + mov r1, lr + b vSystemCallExit + +#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +SVC_Handler: + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + b vPortSVCHandler_C + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + + END diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h new file mode 100644 index 000000000..597af66fa --- /dev/null +++ b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h @@ -0,0 +1,86 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_MVE + #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE. +#endif /* configENABLE_MVE */ +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M55" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portARMV8M_MINOR_VERSION 1 +#define portDONT_DISCARD __root +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ +#pragma diag_suppress=Be006 +#pragma diag_suppress=Pa082 +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h new file mode 100644 index 000000000..f373bcad5 --- /dev/null +++ b/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h @@ -0,0 +1,582 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACROCOMMON_H +#define PORTMACROCOMMON_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. +#endif /* configENABLE_FPU */ + +#ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. +#endif /* configENABLE_MPU */ + +#ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. +#endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() +#define portINLINE __inline +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif +#define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ +extern BaseType_t xPortIsInsideInterrupt( void ); + +extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + +extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; +extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + +extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; +extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + +#if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_PAC == 1 ) + + /** + * @brief Generates 128-bit task's random PAC key. + * + * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be + * filled with a 128-bit random number. + */ + void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); + +#endif /* configENABLE_PAC */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ +#if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) +#else + #define portPRIVILEGE_BIT ( 0x0UL ) +#endif /* configENABLE_MPU */ + +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ +#define portPRIVILEGED_FLASH_REGION ( 0UL ) +#define portUNPRIVILEGED_FLASH_REGION ( 1UL ) +#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) +#define portPRIVILEGED_RAM_REGION ( 3UL ) +#define portSTACK_REGION ( 4UL ) +#define portFIRST_CONFIGURABLE_REGION ( 5UL ) +#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) +#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) +#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ +#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ +#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ +#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ +#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ +#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ +#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ +#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) +#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) +#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + +#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) +#define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) +#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) +#define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + +#define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + #ifndef configSYSTEM_CALL_STACK_SIZE + #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. + #endif + + /** + * @brief System call stack. + */ + typedef struct SYSTEM_CALL_STACK_INFO + { + uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; + uint32_t * pulSystemCallStack; + uint32_t * pulSystemCallStackLimit; + uint32_t * pulTaskStack; + uint32_t ulLinkRegisterAtSystemCallEntry; + uint32_t ulStackLimitRegisterAtSystemCallEntry; + } xSYSTEM_CALL_STACK_INFO; + + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + /** + * @brief MPU settings as stored in the TCB. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><-----------><----> + * 16 17 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 71 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 17 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 55 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | | | PC, xPSR | EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><-----------><----> + * 16 17 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 70 + + #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + /* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 17 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 54 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+------------------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +----------+-----------------+------------------------------+------------+-----+ + * + * <---------><----------------><------------------------------><-----------><----> + * 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 38 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+----------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | PC, xPSR | EXC_RETURN | | | + * +----------+-----------------+----------------------+------------+-----+ + * + * <---------><----------------><----------------------><-----------><----> + * 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 37 + + #else /* #if( configENABLE_TRUSTZONE == 1 ) */ + + /* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) + + /* Size of an Access Control List (ACL) entry in bits. */ + #define portACL_ENTRY_SIZE_BITS ( 32U ) + + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + uint32_t ulContext[ MAX_CONTEXT_SIZE ]; + uint32_t ulTaskFlags; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo; + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ]; + #endif + #endif + } xMPU_SETTINGS; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Validate priority of ISRs that are allowed to call FreeRTOS + * system calls. + */ +#if ( configASSERT_DEFINED == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif +#endif + +/** + * @brief SVC numbers. + */ +#define portSVC_ALLOCATE_SECURE_CONTEXT 100 +#define portSVC_FREE_SECURE_CONTEXT 101 +#define portSVC_START_SCHEDULER 102 +#define portSVC_RAISE_PRIVILEGE 103 +#define portSVC_SYSTEM_CALL_EXIT 104 +#define portSVC_YIELD 105 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) +#endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() +#else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + extern BaseType_t xPortIsTaskPrivileged( void ); + +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACROCOMMON_H */ diff --git a/portable/IAR/ARM_CM7/ReadMe.txt b/portable/IAR/ARM_CM7/ReadMe.txt new file mode 100644 index 000000000..9cc851ed0 --- /dev/null +++ b/portable/IAR/ARM_CM7/ReadMe.txt @@ -0,0 +1,18 @@ +There are two options for running FreeRTOS on ARM Cortex-M7 microcontrollers. +The best option depends on the revision of the ARM Cortex-M7 core in use. The +revision is specified by an 'r' number, and a 'p' number, so will look something +like 'r0p1'. Check the documentation for the microcontroller in use to find the +revision of the Cortex-M7 core used in that microcontroller. If in doubt, use +the FreeRTOS port provided specifically for r0p1 revisions, as that can be used +with all core revisions. + +The first option is to use the ARM Cortex-M4F port, and the second option is to +use the Cortex-M7 r0p1 port - the latter containing a minor errata workaround. + +If the revision of the ARM Cortex-M7 core is not r0p1 then either option can be +used, but it is recommended to use the FreeRTOS ARM Cortex-M4F port located in +the /FreeRTOS/Source/portable/IAR/ARM_CM4F directory. + +If the revision of the ARM Cortex-M7 core is r0p1 then use the FreeRTOS ARM +Cortex-M7 r0p1 port located in the /FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1 +directory. diff --git a/portable/IAR/ARM_CM7/r0p1/port.c b/portable/IAR/ARM_CM7/r0p1/port.c new file mode 100644 index 000000000..723389633 --- /dev/null +++ b/portable/IAR/ARM_CM7/r0p1/port.c @@ -0,0 +1,764 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ARM CM7 port. +*----------------------------------------------------------*/ + +/* IAR includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#ifndef __ARMVFP__ + #error This port can only be used when the project options are configured to enable hardware floating point support. +#endif + +#if ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) + #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ +#endif + +/* Prototype of all Interrupt Service Routines (ISRs). */ +typedef void ( * portISR_t )( void ); + +/* Constants required to manipulate the core. Registers first... */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +/* ...then bits in the registers. */ +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) + +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL ) +#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL ) + +/* Constants used to check the installation of the FreeRTOS interrupt handlers. */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xE000ED08 ) ) +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) + +/* Constants required to check the validity of an interrupt priority. */ +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) + +/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */ +#define portVECTACTIVE_MASK ( 0xFFUL ) + +/* Constants required to manipulate the VFP. */ +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */ +#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) +#define portINITIAL_EXC_RETURN ( 0xfffffffd ) + +/* The systick is a 24-bit counter. */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/* A fiddle factor to estimate the number of SysTick counts that would have + * occurred while the SysTick counter is stopped during tickless idle + * calculations. */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) + +/* For strict compliance with the Cortex-M spec the task start address should + * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */ +#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL ) + +/* Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ); + +/* + * Exception handlers. + */ +void xPortSysTickHandler( void ); + +/* + * Start first task is a separate function so it can be tested in isolation. + */ +extern void vPortStartFirstTask( void ); + +/* + * Turn the VFP on. + */ +extern void vPortEnableVFP( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/* + * FreeRTOS handlers implemented in assembly. + */ +extern void vPortSVCHandler( void ); +extern void xPortPendSVHandler( void ); +/*-----------------------------------------------------------*/ + +/* Each task maintains its own interrupt status in the critical nesting + * variable. */ +static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +/* + * The number of SysTick increments that make up one tick period. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulTimerCountsForOneTick = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * The maximum number of tick periods that can be suppressed is limited by the + * 24 bit resolution of the SysTick timer. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t xMaximumPossibleSuppressedTicks = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Compensate for the CPU cycles that pass while the SysTick is stopped (low + * power functionality only. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( configASSERT_DEFINED == 1 ) + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16; +#endif /* configASSERT_DEFINED */ + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + + /* Offset added to account for the way the MCU uses the stack on entry/exit + * of interrupts, and to ensure alignment. */ + pxTopOfStack--; + + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */ + + /* Save code space by skipping register initialisation. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + + /* A save method is being used that requires each task to maintain its + * own exec return value. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; + + pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ + configASSERT( uxCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions vPortSVCHandler and + * xPortPendSVHandler for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * vPortSVCHandler and xPortPendSVHandler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( configASSERT_DEFINED == 1 ) + { + volatile uint8_t ucOriginalPriority; + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * Save the interrupt priority value that is about to be clobbered. */ + ucOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to all + * possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + + /* Restore the clobbered interrupt priority register to its original + * value. */ + *pucFirstUserPriorityRegister = ucOriginalPriority; + } + #endif /* configASSERT_DEFINED */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + /* Ensure the VFP is enabled - it should be anyway. */ + vPortEnableVFP(); + + /* Lazy save always. */ + *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ + if( uxCriticalNesting == 1 ) + { + configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + /* The SysTick runs at the lowest interrupt priority, so when this interrupt + * executes all interrupts must be unmasked. There is therefore no need to + * save and then restore the interrupt mask value as its value is already + * known. */ + portDISABLE_INTERRUPTS(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + + /* A context switch is required. Context switching is performed in + * the PendSV interrupt. Pend the PendSV interrupt. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + portENABLE_INTERRUPTS(); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __disable_interrupt(); + __DSB(); + __ISB(); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the __disable_interrupt() + * call above. */ + __enable_interrupt(); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __DSB(); + __WFI(); + __ISB(); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the __disable_interrupt() call above. */ + __enable_interrupt(); + __DSB(); + __ISB(); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __disable_interrupt(); + __DSB(); + __ISB(); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __enable_interrupt(); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +__weak void vPortSetupTimerInterrupt( void ) +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and clear the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); +} +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* configASSERT_DEFINED */ diff --git a/portable/IAR/ARM_CM7/r0p1/portasm.s b/portable/IAR/ARM_CM7/r0p1/portasm.s new file mode 100644 index 000000000..56d4b3e04 --- /dev/null +++ b/portable/IAR/ARM_CM7/r0p1/portasm.s @@ -0,0 +1,151 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include + + RSEG CODE:CODE(2) + thumb + + EXTERN pxCurrentTCB + EXTERN vTaskSwitchContext + + PUBLIC xPortPendSVHandler + PUBLIC vPortSVCHandler + PUBLIC vPortStartFirstTask + PUBLIC vPortEnableVFP + + +/*-----------------------------------------------------------*/ + +xPortPendSVHandler: + mrs r0, psp + isb + /* Get the location of the current TCB. */ + ldr r3, =pxCurrentTCB + ldr r2, [r3] + + /* Is the task using the FPU context? If so, push high vfp registers. */ + tst r14, #0x10 + it eq + vstmdbeq r0!, {s16-s31} + + /* Save the core registers. */ + stmdb r0!, {r4-r11, r14} + + /* Save the new top of stack into the first member of the TCB. */ + str r0, [r2] + + stmdb sp!, {r0, r3} + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + cpsid i + msr basepri, r0 + dsb + isb + cpsie i + bl vTaskSwitchContext + mov r0, #0 + msr basepri, r0 + ldmia sp!, {r0, r3} + + /* The first item in pxCurrentTCB is the task top of stack. */ + ldr r1, [r3] + ldr r0, [r1] + + /* Pop the core registers. */ + ldmia r0!, {r4-r11, r14} + + /* Is the task using the FPU context? If so, pop the high vfp registers + too. */ + tst r14, #0x10 + it eq + vldmiaeq r0!, {s16-s31} + + msr psp, r0 + isb + #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */ + #if WORKAROUND_PMU_CM001 == 1 + push { r14 } + pop { pc } + #endif + #endif + + bx r14 + + +/*-----------------------------------------------------------*/ + +vPortSVCHandler: + /* Get the location of the current TCB. */ + ldr r3, =pxCurrentTCB + ldr r1, [r3] + ldr r0, [r1] + /* Pop the core registers. */ + ldmia r0!, {r4-r11, r14} + msr psp, r0 + isb + mov r0, #0 + msr basepri, r0 + bx r14 + +/*-----------------------------------------------------------*/ + +vPortStartFirstTask + /* Use the NVIC offset register to locate the stack. */ + ldr r0, =0xE000ED08 + ldr r0, [r0] + ldr r0, [r0] + /* Set the msp back to the start of the stack. */ + msr msp, r0 + /* Clear the bit that indicates the FPU is in use in case the FPU was used + before the scheduler was started - which would otherwise result in the + unnecessary leaving of space in the SVC stack for lazy saving of FPU + registers. */ + mov r0, #0 + msr control, r0 + /* Call SVC to start the first task. */ + cpsie i + cpsie f + dsb + isb + svc 0 + +/*-----------------------------------------------------------*/ + +vPortEnableVFP: + /* The FPU enable bits are in the CPACR. */ + ldr.w r0, =0xE000ED88 + ldr r1, [r0] + + /* Enable CP10 and CP11 coprocessors, then save back. */ + orr r1, r1, #( 0xf << 20 ) + str r1, [r0] + bx r14 + + + + END diff --git a/portable/IAR/ARM_CM7/r0p1/portmacro.h b/portable/IAR/ARM_CM7/r0p1/portmacro.h new file mode 100644 index 000000000..7c66ed3f9 --- /dev/null +++ b/portable/IAR/ARM_CM7/r0p1/portmacro.h @@ -0,0 +1,228 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* IAR includes. */ +#include + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +/*-----------------------------------------------------------*/ + +/* Compiler directives. */ +#define portWEAK_SYMBOL __attribute__( ( weak ) ) + +/*-----------------------------------------------------------*/ + + +/* Scheduler utilities. */ +#define portYIELD() \ + { \ + /* Set a PendSV to request a context switch. */ \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + __DSB(); \ + __ISB(); \ + } + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portYIELD(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) + +/*-----------------------------------------------------------*/ + +/* Architecture specific optimisations. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portDISABLE_INTERRUPTS() \ + { \ + /* Errata work around. */ \ + __disable_interrupt(); \ + __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \ + __DSB(); \ + __ISB(); \ + __enable_interrupt(); \ + } + +#define portENABLE_INTERRUPTS() __set_BASEPRI( 0 ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +#define portSET_INTERRUPT_MASK_FROM_ISR() __get_BASEPRI(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) __set_BASEPRI( x ) +/*-----------------------------------------------------------*/ + +/* Tickless idle/low power functionality. */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not necessary for to use this port. They are defined so the common demo files + * (which build with all the ports) will build. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif + +/* portNOP() is not required by this port. */ +#define portNOP() + +#define portINLINE __inline + +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif + +/*-----------------------------------------------------------*/ + +portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} + +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ +#pragma diag_suppress=Pe191 +#pragma diag_suppress=Pa082 + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/IAR/ARM_CM85/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM85/non_secure/mpu_wrappers_v2_asm.S new file mode 100644 index 000000000..d2cb78e92 --- /dev/null +++ b/portable/IAR/ARM_CM85/non_secure/mpu_wrappers_v2_asm.S @@ -0,0 +1,1242 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + + SECTION freertos_system_calls:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +#include "FreeRTOSConfig.h" +#include "mpu_syscall_numbers.h" + +#ifndef configUSE_MPU_WRAPPERS_V1 + #define configUSE_MPU_WRAPPERS_V1 0 +#endif + +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + PUBLIC MPU_xTaskDelayUntil +MPU_xTaskDelayUntil: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskDelayUntil_Unpriv + MPU_xTaskDelayUntil_Priv: + b MPU_xTaskDelayUntilImpl + MPU_xTaskDelayUntil_Unpriv: + svc #SYSTEM_CALL_xTaskDelayUntil +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskAbortDelay +MPU_xTaskAbortDelay: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskAbortDelay_Unpriv + MPU_xTaskAbortDelay_Priv: + b MPU_xTaskAbortDelayImpl + MPU_xTaskAbortDelay_Unpriv: + svc #SYSTEM_CALL_xTaskAbortDelay +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskDelay +MPU_vTaskDelay: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskDelay_Unpriv + MPU_vTaskDelay_Priv: + b MPU_vTaskDelayImpl + MPU_vTaskDelay_Unpriv: + svc #SYSTEM_CALL_vTaskDelay +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskPriorityGet +MPU_uxTaskPriorityGet: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskPriorityGet_Unpriv + MPU_uxTaskPriorityGet_Priv: + b MPU_uxTaskPriorityGetImpl + MPU_uxTaskPriorityGet_Unpriv: + svc #SYSTEM_CALL_uxTaskPriorityGet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_eTaskGetState +MPU_eTaskGetState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_eTaskGetState_Unpriv + MPU_eTaskGetState_Priv: + b MPU_eTaskGetStateImpl + MPU_eTaskGetState_Unpriv: + svc #SYSTEM_CALL_eTaskGetState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskGetInfo +MPU_vTaskGetInfo: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskGetInfo_Unpriv + MPU_vTaskGetInfo_Priv: + b MPU_vTaskGetInfoImpl + MPU_vTaskGetInfo_Unpriv: + svc #SYSTEM_CALL_vTaskGetInfo +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetIdleTaskHandle +MPU_xTaskGetIdleTaskHandle: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetIdleTaskHandle_Unpriv + MPU_xTaskGetIdleTaskHandle_Priv: + b MPU_xTaskGetIdleTaskHandleImpl + MPU_xTaskGetIdleTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTaskGetIdleTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSuspend +MPU_vTaskSuspend: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSuspend_Unpriv + MPU_vTaskSuspend_Priv: + b MPU_vTaskSuspendImpl + MPU_vTaskSuspend_Unpriv: + svc #SYSTEM_CALL_vTaskSuspend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskResume +MPU_vTaskResume: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskResume_Unpriv + MPU_vTaskResume_Priv: + b MPU_vTaskResumeImpl + MPU_vTaskResume_Unpriv: + svc #SYSTEM_CALL_vTaskResume +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetTickCount +MPU_xTaskGetTickCount: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetTickCount_Unpriv + MPU_xTaskGetTickCount_Priv: + b MPU_xTaskGetTickCountImpl + MPU_xTaskGetTickCount_Unpriv: + svc #SYSTEM_CALL_xTaskGetTickCount +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetNumberOfTasks +MPU_uxTaskGetNumberOfTasks: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetNumberOfTasks_Unpriv + MPU_uxTaskGetNumberOfTasks_Priv: + b MPU_uxTaskGetNumberOfTasksImpl + MPU_uxTaskGetNumberOfTasks_Unpriv: + svc #SYSTEM_CALL_uxTaskGetNumberOfTasks +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetRunTimeCounter +MPU_ulTaskGetRunTimeCounter: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetRunTimeCounter_Unpriv + MPU_ulTaskGetRunTimeCounter_Priv: + b MPU_ulTaskGetRunTimeCounterImpl + MPU_ulTaskGetRunTimeCounter_Unpriv: + svc #SYSTEM_CALL_ulTaskGetRunTimeCounter +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetRunTimePercent +MPU_ulTaskGetRunTimePercent: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetRunTimePercent_Unpriv + MPU_ulTaskGetRunTimePercent_Priv: + b MPU_ulTaskGetRunTimePercentImpl + MPU_ulTaskGetRunTimePercent_Unpriv: + svc #SYSTEM_CALL_ulTaskGetRunTimePercent +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetIdleRunTimePercent +MPU_ulTaskGetIdleRunTimePercent: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetIdleRunTimePercent_Unpriv + MPU_ulTaskGetIdleRunTimePercent_Priv: + b MPU_ulTaskGetIdleRunTimePercentImpl + MPU_ulTaskGetIdleRunTimePercent_Unpriv: + svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetIdleRunTimeCounter +MPU_ulTaskGetIdleRunTimeCounter: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv + MPU_ulTaskGetIdleRunTimeCounter_Priv: + b MPU_ulTaskGetIdleRunTimeCounterImpl + MPU_ulTaskGetIdleRunTimeCounter_Unpriv: + svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetApplicationTaskTag +MPU_vTaskSetApplicationTaskTag: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetApplicationTaskTag_Unpriv + MPU_vTaskSetApplicationTaskTag_Priv: + b MPU_vTaskSetApplicationTaskTagImpl + MPU_vTaskSetApplicationTaskTag_Unpriv: + svc #SYSTEM_CALL_vTaskSetApplicationTaskTag +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetApplicationTaskTag +MPU_xTaskGetApplicationTaskTag: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetApplicationTaskTag_Unpriv + MPU_xTaskGetApplicationTaskTag_Priv: + b MPU_xTaskGetApplicationTaskTagImpl + MPU_xTaskGetApplicationTaskTag_Unpriv: + svc #SYSTEM_CALL_xTaskGetApplicationTaskTag +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetThreadLocalStoragePointer +MPU_vTaskSetThreadLocalStoragePointer: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv + MPU_vTaskSetThreadLocalStoragePointer_Priv: + b MPU_vTaskSetThreadLocalStoragePointerImpl + MPU_vTaskSetThreadLocalStoragePointer_Unpriv: + svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pvTaskGetThreadLocalStoragePointer +MPU_pvTaskGetThreadLocalStoragePointer: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv + MPU_pvTaskGetThreadLocalStoragePointer_Priv: + b MPU_pvTaskGetThreadLocalStoragePointerImpl + MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: + svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetSystemState +MPU_uxTaskGetSystemState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetSystemState_Unpriv + MPU_uxTaskGetSystemState_Priv: + b MPU_uxTaskGetSystemStateImpl + MPU_uxTaskGetSystemState_Unpriv: + svc #SYSTEM_CALL_uxTaskGetSystemState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetStackHighWaterMark +MPU_uxTaskGetStackHighWaterMark: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetStackHighWaterMark_Unpriv + MPU_uxTaskGetStackHighWaterMark_Priv: + b MPU_uxTaskGetStackHighWaterMarkImpl + MPU_uxTaskGetStackHighWaterMark_Unpriv: + svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetStackHighWaterMark2 +MPU_uxTaskGetStackHighWaterMark2: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetStackHighWaterMark2_Unpriv + MPU_uxTaskGetStackHighWaterMark2_Priv: + b MPU_uxTaskGetStackHighWaterMark2Impl + MPU_uxTaskGetStackHighWaterMark2_Unpriv: + svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2 +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetCurrentTaskHandle +MPU_xTaskGetCurrentTaskHandle: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetCurrentTaskHandle_Unpriv + MPU_xTaskGetCurrentTaskHandle_Priv: + b MPU_xTaskGetCurrentTaskHandleImpl + MPU_xTaskGetCurrentTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetSchedulerState +MPU_xTaskGetSchedulerState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetSchedulerState_Unpriv + MPU_xTaskGetSchedulerState_Priv: + b MPU_xTaskGetSchedulerStateImpl + MPU_xTaskGetSchedulerState_Unpriv: + svc #SYSTEM_CALL_xTaskGetSchedulerState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetTimeOutState +MPU_vTaskSetTimeOutState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetTimeOutState_Unpriv + MPU_vTaskSetTimeOutState_Priv: + b MPU_vTaskSetTimeOutStateImpl + MPU_vTaskSetTimeOutState_Unpriv: + svc #SYSTEM_CALL_vTaskSetTimeOutState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskCheckForTimeOut +MPU_xTaskCheckForTimeOut: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskCheckForTimeOut_Unpriv + MPU_xTaskCheckForTimeOut_Priv: + b MPU_xTaskCheckForTimeOutImpl + MPU_xTaskCheckForTimeOut_Unpriv: + svc #SYSTEM_CALL_xTaskCheckForTimeOut +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyEntry +MPU_xTaskGenericNotifyEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotify_Unpriv + MPU_xTaskGenericNotify_Priv: + b MPU_xTaskGenericNotifyImpl + MPU_xTaskGenericNotify_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotify +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyWaitEntry +MPU_xTaskGenericNotifyWaitEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotifyWait_Unpriv + MPU_xTaskGenericNotifyWait_Priv: + b MPU_xTaskGenericNotifyWaitImpl + MPU_xTaskGenericNotifyWait_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotifyWait +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGenericNotifyTake +MPU_ulTaskGenericNotifyTake: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGenericNotifyTake_Unpriv + MPU_ulTaskGenericNotifyTake_Priv: + b MPU_ulTaskGenericNotifyTakeImpl + MPU_ulTaskGenericNotifyTake_Unpriv: + svc #SYSTEM_CALL_ulTaskGenericNotifyTake +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyStateClear +MPU_xTaskGenericNotifyStateClear: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotifyStateClear_Unpriv + MPU_xTaskGenericNotifyStateClear_Priv: + b MPU_xTaskGenericNotifyStateClearImpl + MPU_xTaskGenericNotifyStateClear_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotifyStateClear +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGenericNotifyValueClear +MPU_ulTaskGenericNotifyValueClear: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGenericNotifyValueClear_Unpriv + MPU_ulTaskGenericNotifyValueClear_Priv: + b MPU_ulTaskGenericNotifyValueClearImpl + MPU_ulTaskGenericNotifyValueClear_Unpriv: + svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGenericSend +MPU_xQueueGenericSend: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGenericSend_Unpriv + MPU_xQueueGenericSend_Priv: + b MPU_xQueueGenericSendImpl + MPU_xQueueGenericSend_Unpriv: + svc #SYSTEM_CALL_xQueueGenericSend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxQueueMessagesWaiting +MPU_uxQueueMessagesWaiting: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxQueueMessagesWaiting_Unpriv + MPU_uxQueueMessagesWaiting_Priv: + b MPU_uxQueueMessagesWaitingImpl + MPU_uxQueueMessagesWaiting_Unpriv: + svc #SYSTEM_CALL_uxQueueMessagesWaiting +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxQueueSpacesAvailable +MPU_uxQueueSpacesAvailable: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxQueueSpacesAvailable_Unpriv + MPU_uxQueueSpacesAvailable_Priv: + b MPU_uxQueueSpacesAvailableImpl + MPU_uxQueueSpacesAvailable_Unpriv: + svc #SYSTEM_CALL_uxQueueSpacesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueReceive +MPU_xQueueReceive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueReceive_Unpriv + MPU_xQueueReceive_Priv: + b MPU_xQueueReceiveImpl + MPU_xQueueReceive_Unpriv: + svc #SYSTEM_CALL_xQueueReceive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueuePeek +MPU_xQueuePeek: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueuePeek_Unpriv + MPU_xQueuePeek_Priv: + b MPU_xQueuePeekImpl + MPU_xQueuePeek_Unpriv: + svc #SYSTEM_CALL_xQueuePeek +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueSemaphoreTake +MPU_xQueueSemaphoreTake: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueSemaphoreTake_Unpriv + MPU_xQueueSemaphoreTake_Priv: + b MPU_xQueueSemaphoreTakeImpl + MPU_xQueueSemaphoreTake_Unpriv: + svc #SYSTEM_CALL_xQueueSemaphoreTake +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGetMutexHolder +MPU_xQueueGetMutexHolder: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGetMutexHolder_Unpriv + MPU_xQueueGetMutexHolder_Priv: + b MPU_xQueueGetMutexHolderImpl + MPU_xQueueGetMutexHolder_Unpriv: + svc #SYSTEM_CALL_xQueueGetMutexHolder +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueTakeMutexRecursive +MPU_xQueueTakeMutexRecursive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueTakeMutexRecursive_Unpriv + MPU_xQueueTakeMutexRecursive_Priv: + b MPU_xQueueTakeMutexRecursiveImpl + MPU_xQueueTakeMutexRecursive_Unpriv: + svc #SYSTEM_CALL_xQueueTakeMutexRecursive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGiveMutexRecursive +MPU_xQueueGiveMutexRecursive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGiveMutexRecursive_Unpriv + MPU_xQueueGiveMutexRecursive_Priv: + b MPU_xQueueGiveMutexRecursiveImpl + MPU_xQueueGiveMutexRecursive_Unpriv: + svc #SYSTEM_CALL_xQueueGiveMutexRecursive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueSelectFromSet +MPU_xQueueSelectFromSet: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueSelectFromSet_Unpriv + MPU_xQueueSelectFromSet_Priv: + b MPU_xQueueSelectFromSetImpl + MPU_xQueueSelectFromSet_Unpriv: + svc #SYSTEM_CALL_xQueueSelectFromSet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueAddToSet +MPU_xQueueAddToSet: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueAddToSet_Unpriv + MPU_xQueueAddToSet_Priv: + b MPU_xQueueAddToSetImpl + MPU_xQueueAddToSet_Unpriv: + svc #SYSTEM_CALL_xQueueAddToSet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vQueueAddToRegistry +MPU_vQueueAddToRegistry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vQueueAddToRegistry_Unpriv + MPU_vQueueAddToRegistry_Priv: + b MPU_vQueueAddToRegistryImpl + MPU_vQueueAddToRegistry_Unpriv: + svc #SYSTEM_CALL_vQueueAddToRegistry +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vQueueUnregisterQueue +MPU_vQueueUnregisterQueue: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vQueueUnregisterQueue_Unpriv + MPU_vQueueUnregisterQueue_Priv: + b MPU_vQueueUnregisterQueueImpl + MPU_vQueueUnregisterQueue_Unpriv: + svc #SYSTEM_CALL_vQueueUnregisterQueue +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pcQueueGetName +MPU_pcQueueGetName: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pcQueueGetName_Unpriv + MPU_pcQueueGetName_Priv: + b MPU_pcQueueGetNameImpl + MPU_pcQueueGetName_Unpriv: + svc #SYSTEM_CALL_pcQueueGetName +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pvTimerGetTimerID +MPU_pvTimerGetTimerID: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pvTimerGetTimerID_Unpriv + MPU_pvTimerGetTimerID_Priv: + b MPU_pvTimerGetTimerIDImpl + MPU_pvTimerGetTimerID_Unpriv: + svc #SYSTEM_CALL_pvTimerGetTimerID +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTimerSetTimerID +MPU_vTimerSetTimerID: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTimerSetTimerID_Unpriv + MPU_vTimerSetTimerID_Priv: + b MPU_vTimerSetTimerIDImpl + MPU_vTimerSetTimerID_Unpriv: + svc #SYSTEM_CALL_vTimerSetTimerID +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerIsTimerActive +MPU_xTimerIsTimerActive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerIsTimerActive_Unpriv + MPU_xTimerIsTimerActive_Priv: + b MPU_xTimerIsTimerActiveImpl + MPU_xTimerIsTimerActive_Unpriv: + svc #SYSTEM_CALL_xTimerIsTimerActive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetTimerDaemonTaskHandle +MPU_xTimerGetTimerDaemonTaskHandle: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv + MPU_xTimerGetTimerDaemonTaskHandle_Priv: + b MPU_xTimerGetTimerDaemonTaskHandleImpl + MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGenericCommandFromTaskEntry +MPU_xTimerGenericCommandFromTaskEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGenericCommandFromTask_Unpriv + MPU_xTimerGenericCommandFromTask_Priv: + b MPU_xTimerGenericCommandFromTaskImpl + MPU_xTimerGenericCommandFromTask_Unpriv: + svc #SYSTEM_CALL_xTimerGenericCommandFromTask +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pcTimerGetName +MPU_pcTimerGetName: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pcTimerGetName_Unpriv + MPU_pcTimerGetName_Priv: + b MPU_pcTimerGetNameImpl + MPU_pcTimerGetName_Unpriv: + svc #SYSTEM_CALL_pcTimerGetName +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTimerSetReloadMode +MPU_vTimerSetReloadMode: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTimerSetReloadMode_Unpriv + MPU_vTimerSetReloadMode_Priv: + b MPU_vTimerSetReloadModeImpl + MPU_vTimerSetReloadMode_Unpriv: + svc #SYSTEM_CALL_vTimerSetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetReloadMode +MPU_xTimerGetReloadMode: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetReloadMode_Unpriv + MPU_xTimerGetReloadMode_Priv: + b MPU_xTimerGetReloadModeImpl + MPU_xTimerGetReloadMode_Unpriv: + svc #SYSTEM_CALL_xTimerGetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTimerGetReloadMode +MPU_uxTimerGetReloadMode: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTimerGetReloadMode_Unpriv + MPU_uxTimerGetReloadMode_Priv: + b MPU_uxTimerGetReloadModeImpl + MPU_uxTimerGetReloadMode_Unpriv: + svc #SYSTEM_CALL_uxTimerGetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetPeriod +MPU_xTimerGetPeriod: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetPeriod_Unpriv + MPU_xTimerGetPeriod_Priv: + b MPU_xTimerGetPeriodImpl + MPU_xTimerGetPeriod_Unpriv: + svc #SYSTEM_CALL_xTimerGetPeriod +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetExpiryTime +MPU_xTimerGetExpiryTime: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetExpiryTime_Unpriv + MPU_xTimerGetExpiryTime_Priv: + b MPU_xTimerGetExpiryTimeImpl + MPU_xTimerGetExpiryTime_Unpriv: + svc #SYSTEM_CALL_xTimerGetExpiryTime +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupWaitBitsEntry +MPU_xEventGroupWaitBitsEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupWaitBits_Unpriv + MPU_xEventGroupWaitBits_Priv: + b MPU_xEventGroupWaitBitsImpl + MPU_xEventGroupWaitBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupWaitBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupClearBits +MPU_xEventGroupClearBits: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupClearBits_Unpriv + MPU_xEventGroupClearBits_Priv: + b MPU_xEventGroupClearBitsImpl + MPU_xEventGroupClearBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupClearBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupSetBits +MPU_xEventGroupSetBits: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupSetBits_Unpriv + MPU_xEventGroupSetBits_Priv: + b MPU_xEventGroupSetBitsImpl + MPU_xEventGroupSetBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupSetBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupSync +MPU_xEventGroupSync: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupSync_Unpriv + MPU_xEventGroupSync_Priv: + b MPU_xEventGroupSyncImpl + MPU_xEventGroupSync_Unpriv: + svc #SYSTEM_CALL_xEventGroupSync +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxEventGroupGetNumber +MPU_uxEventGroupGetNumber: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxEventGroupGetNumber_Unpriv + MPU_uxEventGroupGetNumber_Priv: + b MPU_uxEventGroupGetNumberImpl + MPU_uxEventGroupGetNumber_Unpriv: + svc #SYSTEM_CALL_uxEventGroupGetNumber +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vEventGroupSetNumber +MPU_vEventGroupSetNumber: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vEventGroupSetNumber_Unpriv + MPU_vEventGroupSetNumber_Priv: + b MPU_vEventGroupSetNumberImpl + MPU_vEventGroupSetNumber_Unpriv: + svc #SYSTEM_CALL_vEventGroupSetNumber +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSend +MPU_xStreamBufferSend: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSend_Unpriv + MPU_xStreamBufferSend_Priv: + b MPU_xStreamBufferSendImpl + MPU_xStreamBufferSend_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferReceive +MPU_xStreamBufferReceive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferReceive_Unpriv + MPU_xStreamBufferReceive_Priv: + b MPU_xStreamBufferReceiveImpl + MPU_xStreamBufferReceive_Unpriv: + svc #SYSTEM_CALL_xStreamBufferReceive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferIsFull +MPU_xStreamBufferIsFull: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferIsFull_Unpriv + MPU_xStreamBufferIsFull_Priv: + b MPU_xStreamBufferIsFullImpl + MPU_xStreamBufferIsFull_Unpriv: + svc #SYSTEM_CALL_xStreamBufferIsFull +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferIsEmpty +MPU_xStreamBufferIsEmpty: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferIsEmpty_Unpriv + MPU_xStreamBufferIsEmpty_Priv: + b MPU_xStreamBufferIsEmptyImpl + MPU_xStreamBufferIsEmpty_Unpriv: + svc #SYSTEM_CALL_xStreamBufferIsEmpty +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSpacesAvailable +MPU_xStreamBufferSpacesAvailable: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSpacesAvailable_Unpriv + MPU_xStreamBufferSpacesAvailable_Priv: + b MPU_xStreamBufferSpacesAvailableImpl + MPU_xStreamBufferSpacesAvailable_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSpacesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferBytesAvailable +MPU_xStreamBufferBytesAvailable: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferBytesAvailable_Unpriv + MPU_xStreamBufferBytesAvailable_Priv: + b MPU_xStreamBufferBytesAvailableImpl + MPU_xStreamBufferBytesAvailable_Unpriv: + svc #SYSTEM_CALL_xStreamBufferBytesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSetTriggerLevel +MPU_xStreamBufferSetTriggerLevel: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSetTriggerLevel_Unpriv + MPU_xStreamBufferSetTriggerLevel_Priv: + b MPU_xStreamBufferSetTriggerLevelImpl + MPU_xStreamBufferSetTriggerLevel_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferNextMessageLengthBytes +MPU_xStreamBufferNextMessageLengthBytes: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv + MPU_xStreamBufferNextMessageLengthBytes_Priv: + b MPU_xStreamBufferNextMessageLengthBytesImpl + MPU_xStreamBufferNextMessageLengthBytes_Unpriv: + svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes +/*-----------------------------------------------------------*/ + +/* Default weak implementations in case one is not available from + * mpu_wrappers because of config options. */ + + PUBWEAK MPU_xTaskDelayUntilImpl +MPU_xTaskDelayUntilImpl: + b MPU_xTaskDelayUntilImpl + + PUBWEAK MPU_xTaskAbortDelayImpl +MPU_xTaskAbortDelayImpl: + b MPU_xTaskAbortDelayImpl + + PUBWEAK MPU_vTaskDelayImpl +MPU_vTaskDelayImpl: + b MPU_vTaskDelayImpl + + PUBWEAK MPU_uxTaskPriorityGetImpl +MPU_uxTaskPriorityGetImpl: + b MPU_uxTaskPriorityGetImpl + + PUBWEAK MPU_eTaskGetStateImpl +MPU_eTaskGetStateImpl: + b MPU_eTaskGetStateImpl + + PUBWEAK MPU_vTaskGetInfoImpl +MPU_vTaskGetInfoImpl: + b MPU_vTaskGetInfoImpl + + PUBWEAK MPU_xTaskGetIdleTaskHandleImpl +MPU_xTaskGetIdleTaskHandleImpl: + b MPU_xTaskGetIdleTaskHandleImpl + + PUBWEAK MPU_vTaskSuspendImpl +MPU_vTaskSuspendImpl: + b MPU_vTaskSuspendImpl + + PUBWEAK MPU_vTaskResumeImpl +MPU_vTaskResumeImpl: + b MPU_vTaskResumeImpl + + PUBWEAK MPU_xTaskGetTickCountImpl +MPU_xTaskGetTickCountImpl: + b MPU_xTaskGetTickCountImpl + + PUBWEAK MPU_uxTaskGetNumberOfTasksImpl +MPU_uxTaskGetNumberOfTasksImpl: + b MPU_uxTaskGetNumberOfTasksImpl + + PUBWEAK MPU_ulTaskGetRunTimeCounterImpl +MPU_ulTaskGetRunTimeCounterImpl: + b MPU_ulTaskGetRunTimeCounterImpl + + PUBWEAK MPU_ulTaskGetRunTimePercentImpl +MPU_ulTaskGetRunTimePercentImpl: + b MPU_ulTaskGetRunTimePercentImpl + + PUBWEAK MPU_ulTaskGetIdleRunTimePercentImpl +MPU_ulTaskGetIdleRunTimePercentImpl: + b MPU_ulTaskGetIdleRunTimePercentImpl + + PUBWEAK MPU_ulTaskGetIdleRunTimeCounterImpl +MPU_ulTaskGetIdleRunTimeCounterImpl: + b MPU_ulTaskGetIdleRunTimeCounterImpl + + PUBWEAK MPU_vTaskSetApplicationTaskTagImpl +MPU_vTaskSetApplicationTaskTagImpl: + b MPU_vTaskSetApplicationTaskTagImpl + + PUBWEAK MPU_xTaskGetApplicationTaskTagImpl +MPU_xTaskGetApplicationTaskTagImpl: + b MPU_xTaskGetApplicationTaskTagImpl + + PUBWEAK MPU_vTaskSetThreadLocalStoragePointerImpl +MPU_vTaskSetThreadLocalStoragePointerImpl: + b MPU_vTaskSetThreadLocalStoragePointerImpl + + PUBWEAK MPU_pvTaskGetThreadLocalStoragePointerImpl +MPU_pvTaskGetThreadLocalStoragePointerImpl: + b MPU_pvTaskGetThreadLocalStoragePointerImpl + + PUBWEAK MPU_uxTaskGetSystemStateImpl +MPU_uxTaskGetSystemStateImpl: + b MPU_uxTaskGetSystemStateImpl + + PUBWEAK MPU_uxTaskGetStackHighWaterMarkImpl +MPU_uxTaskGetStackHighWaterMarkImpl: + b MPU_uxTaskGetStackHighWaterMarkImpl + + PUBWEAK MPU_uxTaskGetStackHighWaterMark2Impl +MPU_uxTaskGetStackHighWaterMark2Impl: + b MPU_uxTaskGetStackHighWaterMark2Impl + + PUBWEAK MPU_xTaskGetCurrentTaskHandleImpl +MPU_xTaskGetCurrentTaskHandleImpl: + b MPU_xTaskGetCurrentTaskHandleImpl + + PUBWEAK MPU_xTaskGetSchedulerStateImpl +MPU_xTaskGetSchedulerStateImpl: + b MPU_xTaskGetSchedulerStateImpl + + PUBWEAK MPU_vTaskSetTimeOutStateImpl +MPU_vTaskSetTimeOutStateImpl: + b MPU_vTaskSetTimeOutStateImpl + + PUBWEAK MPU_xTaskCheckForTimeOutImpl +MPU_xTaskCheckForTimeOutImpl: + b MPU_xTaskCheckForTimeOutImpl + + PUBWEAK MPU_xTaskGenericNotifyImpl +MPU_xTaskGenericNotifyImpl: + b MPU_xTaskGenericNotifyImpl + + PUBWEAK MPU_xTaskGenericNotifyWaitImpl +MPU_xTaskGenericNotifyWaitImpl: + b MPU_xTaskGenericNotifyWaitImpl + + PUBWEAK MPU_ulTaskGenericNotifyTakeImpl +MPU_ulTaskGenericNotifyTakeImpl: + b MPU_ulTaskGenericNotifyTakeImpl + + PUBWEAK MPU_xTaskGenericNotifyStateClearImpl +MPU_xTaskGenericNotifyStateClearImpl: + b MPU_xTaskGenericNotifyStateClearImpl + + PUBWEAK MPU_ulTaskGenericNotifyValueClearImpl +MPU_ulTaskGenericNotifyValueClearImpl: + b MPU_ulTaskGenericNotifyValueClearImpl + + PUBWEAK MPU_xQueueGenericSendImpl +MPU_xQueueGenericSendImpl: + b MPU_xQueueGenericSendImpl + + PUBWEAK MPU_uxQueueMessagesWaitingImpl +MPU_uxQueueMessagesWaitingImpl: + b MPU_uxQueueMessagesWaitingImpl + + PUBWEAK MPU_uxQueueSpacesAvailableImpl +MPU_uxQueueSpacesAvailableImpl: + b MPU_uxQueueSpacesAvailableImpl + + PUBWEAK MPU_xQueueReceiveImpl +MPU_xQueueReceiveImpl: + b MPU_xQueueReceiveImpl + + PUBWEAK MPU_xQueuePeekImpl +MPU_xQueuePeekImpl: + b MPU_xQueuePeekImpl + + PUBWEAK MPU_xQueueSemaphoreTakeImpl +MPU_xQueueSemaphoreTakeImpl: + b MPU_xQueueSemaphoreTakeImpl + + PUBWEAK MPU_xQueueGetMutexHolderImpl +MPU_xQueueGetMutexHolderImpl: + b MPU_xQueueGetMutexHolderImpl + + PUBWEAK MPU_xQueueTakeMutexRecursiveImpl +MPU_xQueueTakeMutexRecursiveImpl: + b MPU_xQueueTakeMutexRecursiveImpl + + PUBWEAK MPU_xQueueGiveMutexRecursiveImpl +MPU_xQueueGiveMutexRecursiveImpl: + b MPU_xQueueGiveMutexRecursiveImpl + + PUBWEAK MPU_xQueueSelectFromSetImpl +MPU_xQueueSelectFromSetImpl: + b MPU_xQueueSelectFromSetImpl + + PUBWEAK MPU_xQueueAddToSetImpl +MPU_xQueueAddToSetImpl: + b MPU_xQueueAddToSetImpl + + PUBWEAK MPU_vQueueAddToRegistryImpl +MPU_vQueueAddToRegistryImpl: + b MPU_vQueueAddToRegistryImpl + + PUBWEAK MPU_vQueueUnregisterQueueImpl +MPU_vQueueUnregisterQueueImpl: + b MPU_vQueueUnregisterQueueImpl + + PUBWEAK MPU_pcQueueGetNameImpl +MPU_pcQueueGetNameImpl: + b MPU_pcQueueGetNameImpl + + PUBWEAK MPU_pvTimerGetTimerIDImpl +MPU_pvTimerGetTimerIDImpl: + b MPU_pvTimerGetTimerIDImpl + + PUBWEAK MPU_vTimerSetTimerIDImpl +MPU_vTimerSetTimerIDImpl: + b MPU_vTimerSetTimerIDImpl + + PUBWEAK MPU_xTimerIsTimerActiveImpl +MPU_xTimerIsTimerActiveImpl: + b MPU_xTimerIsTimerActiveImpl + + PUBWEAK MPU_xTimerGetTimerDaemonTaskHandleImpl +MPU_xTimerGetTimerDaemonTaskHandleImpl: + b MPU_xTimerGetTimerDaemonTaskHandleImpl + + PUBWEAK MPU_xTimerGenericCommandFromTaskImpl +MPU_xTimerGenericCommandFromTaskImpl: + b MPU_xTimerGenericCommandFromTaskImpl + + PUBWEAK MPU_pcTimerGetNameImpl +MPU_pcTimerGetNameImpl: + b MPU_pcTimerGetNameImpl + + PUBWEAK MPU_vTimerSetReloadModeImpl +MPU_vTimerSetReloadModeImpl: + b MPU_vTimerSetReloadModeImpl + + PUBWEAK MPU_xTimerGetReloadModeImpl +MPU_xTimerGetReloadModeImpl: + b MPU_xTimerGetReloadModeImpl + + PUBWEAK MPU_uxTimerGetReloadModeImpl +MPU_uxTimerGetReloadModeImpl: + b MPU_uxTimerGetReloadModeImpl + + PUBWEAK MPU_xTimerGetPeriodImpl +MPU_xTimerGetPeriodImpl: + b MPU_xTimerGetPeriodImpl + + PUBWEAK MPU_xTimerGetExpiryTimeImpl +MPU_xTimerGetExpiryTimeImpl: + b MPU_xTimerGetExpiryTimeImpl + + PUBWEAK MPU_xEventGroupWaitBitsImpl +MPU_xEventGroupWaitBitsImpl: + b MPU_xEventGroupWaitBitsImpl + + PUBWEAK MPU_xEventGroupClearBitsImpl +MPU_xEventGroupClearBitsImpl: + b MPU_xEventGroupClearBitsImpl + + PUBWEAK MPU_xEventGroupSetBitsImpl +MPU_xEventGroupSetBitsImpl: + b MPU_xEventGroupSetBitsImpl + + PUBWEAK MPU_xEventGroupSyncImpl +MPU_xEventGroupSyncImpl: + b MPU_xEventGroupSyncImpl + + PUBWEAK MPU_uxEventGroupGetNumberImpl +MPU_uxEventGroupGetNumberImpl: + b MPU_uxEventGroupGetNumberImpl + + PUBWEAK MPU_vEventGroupSetNumberImpl +MPU_vEventGroupSetNumberImpl: + b MPU_vEventGroupSetNumberImpl + + PUBWEAK MPU_xStreamBufferSendImpl +MPU_xStreamBufferSendImpl: + b MPU_xStreamBufferSendImpl + + PUBWEAK MPU_xStreamBufferReceiveImpl +MPU_xStreamBufferReceiveImpl: + b MPU_xStreamBufferReceiveImpl + + PUBWEAK MPU_xStreamBufferIsFullImpl +MPU_xStreamBufferIsFullImpl: + b MPU_xStreamBufferIsFullImpl + + PUBWEAK MPU_xStreamBufferIsEmptyImpl +MPU_xStreamBufferIsEmptyImpl: + b MPU_xStreamBufferIsEmptyImpl + + PUBWEAK MPU_xStreamBufferSpacesAvailableImpl +MPU_xStreamBufferSpacesAvailableImpl: + b MPU_xStreamBufferSpacesAvailableImpl + + PUBWEAK MPU_xStreamBufferBytesAvailableImpl +MPU_xStreamBufferBytesAvailableImpl: + b MPU_xStreamBufferBytesAvailableImpl + + PUBWEAK MPU_xStreamBufferSetTriggerLevelImpl +MPU_xStreamBufferSetTriggerLevelImpl: + b MPU_xStreamBufferSetTriggerLevelImpl + + PUBWEAK MPU_xStreamBufferNextMessageLengthBytesImpl +MPU_xStreamBufferNextMessageLengthBytesImpl: + b MPU_xStreamBufferNextMessageLengthBytesImpl + +/*-----------------------------------------------------------*/ + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + END diff --git a/portable/IAR/ARM_CM85/non_secure/port.c b/portable/IAR/ARM_CM85/non_secure/port.c new file mode 100644 index 000000000..76d2b2445 --- /dev/null +++ b/portable/IAR/ARM_CM85/non_secure/port.c @@ -0,0 +1,2280 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024-2025 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU includes. */ +#include "mpu_wrappers.h" +#include "mpu_syscall_numbers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration settings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to check the validity of an interrupt priority. + */ +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) ) +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used during system call enter and exit. + */ +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Offsets in the stack to the parameters when inside the SVC handler. + */ +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +#if ( portARMV8M_MINOR_VERSION >= 1 ) + + /* Enable Privileged eXecute Never MPU attribute for the selected memory + * region. */ + #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL ) +#endif /* portARMV8M_MINOR_VERSION >= 1 */ + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Extract first address of the MPU region as encoded in the + * RBAR (Region Base Address Register) value. */ +#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \ + ( ( rbar ) & portMPU_RBAR_ADDRESS_MASK ) + +/* Extract last address of the MPU region as encoded in the + * RLAR (Region Limit Address Register) value. */ +#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \ + ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK ) + +/* Does addr lies within [start, end] address range? */ +#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \ + ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) ) + +/* Is the access request satisfied by the available permissions? */ +#define portIS_AUTHORIZED( accessRequest, permissions ) \ + ( ( ( permissions ) & ( accessRequest ) ) == accessRequest ) + +/* Max value that fits in a uint32_t type. */ +#define portUINT32_MAX ( ~( ( uint32_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. + */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 + +/** + * @brief Constants required to check and configure PACBTI security feature implementation. + */ +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) ) + + #define portCONTROL_UPAC_EN ( 1UL << 7UL ) + #define portCONTROL_PAC_EN ( 1UL << 6UL ) + #define portCONTROL_UBTI_EN ( 1UL << 5UL ) + #define portCONTROL_BTI_EN ( 1UL << 4UL ) + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Extract MPU region's access permissions from the Region Base Address + * Register (RBAR) value. + * + * @param ulRBARValue RBAR value for the MPU region. + * + * @return uint32_t Access permissions. + */ + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + + /** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + /** + * @brief Configures PACBTI features. + * + * This function configures the Pointer Authentication, and Branch Target + * Identification security features as per the user configuration. It returns + * the value of the special purpose CONTROL register accordingly, and optionally + * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M + * architecture based) target supports PACBTI security feature. + * + * @param xWriteControlRegister Used to control whether the special purpose + * CONTROL register should be updated or not. + * + * @return CONTROL register value according to the configured PACBTI option. + */ + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the system call stack so that upon returning from + * SVC, the system call stack is used. + * + * @param pulTaskStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + * @param ucSystemCallNumber The system call number of the system call. + */ + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Raise SVC for exiting from a system call. + */ + void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief This variable is set to pdTRUE when the scheduler is started. + */ + PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + + /** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +/** + * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + /** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + + /** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + + /** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the cpsid instruction + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessPermissions = 0; + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_ONLY ) + { + ulAccessPermissions = tskMPU_READ_PERMISSION; + } + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_WRITE ) + { + ulAccessPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION ); + } + + return ulAccessPermissions; + } + +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } + +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ portOFFSET_TO_PC ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ]; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulSystemCallStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the system call section (i.e. application is + * not raising SVC directly). + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as + * it is non-NULL only during the execution of a system call (i.e. + * between system call enter and exit). + * 3. System call is not for a kernel API disabled by the configuration + * in FreeRTOSConfig.h. + * 4. We do not need to check that ucSystemCallNumber is within range + * because the assembly SVC handler checks that before calling + * this function. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) && + ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) ) + { + pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the system call stack for the stack frame. */ + pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulSystemCallStack[ i ] = pulTaskStack[ i ]; + } + + /* Store the value of the Link Register before the SVC was raised. + * It contains the address of the caller of the System Call entry + * point (i.e. the caller of the MPU_). We need to restore it + * when we exit from the system call. */ + pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; + + /* Store the value of the PSPLIM register before the SVC was raised. + * We need to restore it when we exit from the system call. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* Use the pulSystemCallStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif + + /* Start executing the system call upon returning from this handler. */ + pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; + + /* Raise a request to exit from the system call upon finishing the + * system call. */ + pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; + + /* Remember the location where we should copy the stack frame when we exit from + * the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize; + + /* Record if the hardware used padding to force the stack pointer + * to be double word aligned. */ + if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK ) + { + pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG; + } + else + { + pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG ); + } + + /* We ensure in pxPortInitialiseStack that the system call stack is + * double word aligned and therefore, there is no need of padding. + * Clear the bit[9] of stacked xPSR. */ + pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + + /* Raise the privilege for the duration of the system call. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " bics r0, r1 \n" /* Clear nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */ + { + __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulTaskStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the privileged code (i.e. application is not + * raising SVC directly). This SVC is only raised from + * vRequestSystemCallExit which is in the privileged code section. + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL - + * this means that we previously entered a system call and the + * application is not attempting to exit without entering a system + * call. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) ) + { + pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the task stack for the stack frame. */ + pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulTaskStack[ i ] = pulSystemCallStack[ i ]; + } + + /* Use the pulTaskStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) ); + + /* Return to the caller of the System Call entry point (i.e. the + * caller of the MPU_). */ + pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + /* Ensure that LR has a valid value.*/ + pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + + /* Restore the PSPLIM register to what it was at the time of + * system call entry. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* If the hardware used padding to force the stack pointer + * to be double word aligned, set the stacked xPSR bit[9], + * otherwise clear it. */ + if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG ) + { + pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK; + } + else + { + pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + } + + /* This is not NULL only for the duration of the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; + + /* Drop the privilege before returning to the thread mode. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " orrs r0, r1 \n" /* Set nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xTaskIsPrivileged = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xTaskIsPrivileged = pdTRUE; + } + + return xTaskIsPrivileged; + } + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged, + xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulIndex = 0; + uint32_t ulControl = 0x0; + + xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ + ulIndex++; + + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + ulIndex++; + + #if ( configENABLE_TRUSTZONE == 1 ) + { + xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */ + ulIndex++; + } + #endif /* configENABLE_TRUSTZONE */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + ulIndex++; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Check PACBTI security feature configuration before pushing the + * CONTROL register's value on task's TCB. */ + ulControl = prvConfigurePACBTI( pdFALSE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + if( xRunPrivileged == pdTRUE ) + { + xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + else + { + xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG ); + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ + ulIndex++; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + { + /* Ensure that the system call stack is double word aligned. */ + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) + + ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + /* This is not NULL only for the duration of a system call. */ + xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL; + } + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ]; + ulIndex++; + } + } + #endif /* configENABLE_PAC */ + + return &( xMPUSettings->ulContext[ ulIndex ] ); + } + +#else /* configENABLE_MPU */ + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ + { + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + pxTopOfStack--; + *pxTopOfStack = ulTaskPacKey[ i ]; + } + } + #endif /* configENABLE_PAC */ + + return pxTopOfStack; + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Set the CONTROL register value based on PACBTI security feature + * configuration before starting the first task. */ + ( void ) prvConfigurePACBTI( pdTRUE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + { + xSchedulerRunning = pdTRUE; + } + #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + configSTACK_DEPTH_TYPE uxStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( uxStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* PXN. */ + #if ( portARMV8M_MINOR_VERSION >= 1 ) + { + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ); + } + } + #endif /* portARMV8M_MINOR_VERSION >= 1 */ + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, + uint32_t ulBufferLength, + uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */ + + { + uint32_t i, ulBufferStartAddress, ulBufferEndAddress; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE ) + { + ulBufferStartAddress = ( uint32_t ) pvBuffer; + ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL ); + + for( i = 0; i < portTOTAL_NUM_REGIONS; i++ ) + { + /* Is the MPU region enabled? */ + if( ( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR & portMPU_RLAR_REGION_ENABLE ) == portMPU_RLAR_REGION_ENABLE ) + { + if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_AUTHORIZED( ulAccessRequested, + prvGetRegionAccessPermissions( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ) ) ) + { + xAccessGranted = pdTRUE; + break; + } + } + } + } + } + + return xAccessGranted; + } + +#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings; + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else + { + xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 ) + { + xAccessGranted = pdTRUE; + } + } + } + + return xAccessGranted; + } + + #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + ( void ) lInternalIndexOfKernelObject; + + /* If Access Control List feature is not used, all the tasks have + * access to all the kernel objects. */ + return pdTRUE; + } + + #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + { + uint32_t ulControl = 0x0; + + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); + + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; + + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/ARM_CM85/non_secure/portasm.h b/portable/IAR/ARM_CM85/non_secure/portasm.h new file mode 100644 index 000000000..b7021b024 --- /dev/null +++ b/portable/IAR/ARM_CM85/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kernel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/portable/IAR/ARM_CM85/non_secure/portasm.s b/portable/IAR/ARM_CM85/non_secure/portasm.s new file mode 100644 index 000000000..8d5988819 --- /dev/null +++ b/portable/IAR/ARM_CM85/non_secure/portasm.s @@ -0,0 +1,543 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" + +/* System call numbers includes. */ +#include "mpu_syscall_numbers.h" + +#ifndef configUSE_MPU_WRAPPERS_V1 + #define configUSE_MPU_WRAPPERS_V1 0 +#endif + + EXTERN pxCurrentTCB + EXTERN xSecureContext + EXTERN vTaskSwitchContext + EXTERN vPortSVCHandler_C + EXTERN SecureContext_SaveContext + EXTERN SecureContext_LoadContext +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + EXTERN vSystemCallEnter + EXTERN vSystemCallExit +#endif + + PUBLIC xIsPrivileged + PUBLIC vResetPrivilege + PUBLIC vPortAllocateSecureContext + PUBLIC vRestoreContextOfFirstTask + PUBLIC vRaisePrivilege + PUBLIC vStartFirstTask + PUBLIC ulSetInterruptMask + PUBLIC vClearInterruptMask + PUBLIC PendSV_Handler + PUBLIC SVC_Handler + PUBLIC vPortFreeSecureContext +/*-----------------------------------------------------------*/ + +/*---------------- Unprivileged Functions -------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION .text:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +xIsPrivileged: + mrs r0, control /* r0 = CONTROL. */ + tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + ite ne + movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vResetPrivilege: + mrs r0, control /* r0 = CONTROL. */ + orr r0, r0, #1 /* r0 = r0 | 1. */ + msr control, r0 /* CONTROL = r0. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vPortAllocateSecureContext: + svc 100 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 100. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +/*----------------- Privileged Functions --------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION privileged_functions:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +vRestoreContextOfFirstTask: + program_mpu_first_task: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r3] /* r0 = pxCurrentTCB. */ + + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + str r2, [r1] /* Disable MPU. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r1, [r2] /* Program MAIR0. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + + movs r3, #4 /* r3 = 4. */ + str r3, [r1] /* Program RNR = 4. */ + ldmia r0!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + #if ( configTOTAL_MPU_REGIONS == 16 ) + movs r3, #8 /* r3 = 8. */ + str r3, [r1] /* Program RNR = 8. */ + ldmia r0!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + movs r3, #12 /* r3 = 12. */ + str r3, [r1] /* Program RNR = 12. */ + ldmia r0!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + orr r2, #1 /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */ + str r2, [r1] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + + restore_context_first_task: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* r1 = pxCurrentTCB.*/ + ldr r2, [r1] /* r2 = Location of saved context in TCB. */ + + restore_special_regs_first_task: + #if ( configENABLE_PAC == 1 ) + ldmdb r2!, {r3-r6} /* Read task's dedicated PAC key from the task's context. */ + msr PAC_KEY_P_0, r3 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_1, r4 + msr PAC_KEY_P_2, r5 + msr PAC_KEY_P_3, r6 + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + ldmdb r2!, {r0, r3-r5, lr} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */ + msr psp, r3 + msr psplim, r4 + msr control, r5 + ldr r4, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + str r0, [r4] /* Restore xSecureContext. */ + + restore_general_regs_first_task: + ldmdb r2!, {r4-r11} /* r4-r11 contain hardware saved context. */ + stmia r3!, {r4-r11} /* Copy the hardware saved context on the task stack. */ + ldmdb r2!, {r4-r11} /* r4-r11 restored. */ + + restore_context_done_first_task: + str r2, [r1] /* Save the location where the context should be saved next as the first member of TCB. */ + mov r0, #0 + msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ + bx lr + +#else /* configENABLE_MPU */ + +vRestoreContextOfFirstTask: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r3, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + +#if ( configENABLE_PAC == 1 ) + ldmia r0!, {r1-r4} /* Read task's dedicated PAC key from stack. */ + msr PAC_KEY_P_3, r1 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_2, r2 + msr PAC_KEY_P_1, r3 + msr PAC_KEY_P_0, r4 + clrm {r1-r4} /* Clear r1-r4. */ +#endif /* configENABLE_PAC */ + + ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */ + ldr r4, =xSecureContext + str r1, [r4] /* Set xSecureContext to this task's value for the same. */ + msr psplim, r2 /* Set this task's PSPLIM value. */ + mrs r1, control /* Obtain current control register value. */ + orrs r1, r1, #2 /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */ + msr control, r1 /* Write back the new control register value. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + mov r0, #0 + msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ + bx r3 /* Finally, branch to EXC_RETURN. */ + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +vRaisePrivilege: + mrs r0, control /* Read the CONTROL register. */ + bic r0, r0, #1 /* Clear the bit 0. */ + msr control, r0 /* Write back the new CONTROL value. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vStartFirstTask: + ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */ + ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */ + ldr r0, [r0] /* The first entry in vector table is stack pointer. */ + msr msp, r0 /* Set the MSP back to the start of the stack. */ + cpsie i /* Globally enable interrupts. */ + cpsie f + dsb + isb + svc 102 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */ +/*-----------------------------------------------------------*/ + +ulSetInterruptMask: + mrs r0, basepri /* r0 = basepri. Return original basepri value. */ + mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r1 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vClearInterruptMask: + msr basepri, r0 /* basepri = ulMask. */ + dsb + isb + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +PendSV_Handler: + ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + ldr r0, [r3] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */ + ldr r2, [r1] /* r2 = Location in TCB where the context should be saved. */ + + cbz r0, save_ns_context /* No secure context to save. */ + save_s_context: + push {r0-r2, lr} + bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r0-r2, lr} + + save_ns_context: + mov r3, lr /* r3 = LR (EXC_RETURN). */ + lsls r3, r3, #25 /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bmi save_special_regs /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + + save_general_regs: + mrs r3, psp + + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + add r3, r3, #0x20 /* Move r3 to location where s0 is saved. */ + tst lr, #0x10 + ittt eq + vstmiaeq r2!, {s16-s31} /* Store s16-s31. */ + vldmiaeq r3, {s0-s16} /* Copy hardware saved FP context into s0-s16. */ + vstmiaeq r2!, {s0-s16} /* Store hardware saved FP context. */ + sub r3, r3, #0x20 /* Set r3 back to the location of hardware saved context. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + + stmia r2!, {r4-r11} /* Store r4-r11. */ + ldmia r3, {r4-r11} /* Copy the hardware saved context into r4-r11. */ + stmia r2!, {r4-r11} /* Store the hardware saved context. */ + + save_special_regs: + mrs r3, psp /* r3 = PSP. */ + mrs r4, psplim /* r4 = PSPLIM. */ + mrs r5, control /* r5 = CONTROL. */ + stmia r2!, {r0, r3-r5, lr} /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ + #if ( configENABLE_PAC == 1 ) + mrs r3, PAC_KEY_P_0 /* Read task's dedicated PAC key from the PAC key registers. */ + mrs r4, PAC_KEY_P_1 + mrs r5, PAC_KEY_P_2 + mrs r6, PAC_KEY_P_3 + stmia r2!, {r3-r6} /* Store the task's dedicated PAC key on the task's context. */ + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + + str r2, [r1] /* Save the location from where the context should be restored as the first member of TCB. */ + + select_next_task: + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bl vTaskSwitchContext + mov r0, #0 /* r0 = 0. */ + msr basepri, r0 /* Enable interrupts. */ + + program_mpu: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r3] /* r0 = pxCurrentTCB.*/ + + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + str r2, [r1] /* Disable MPU. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r1, [r2] /* Program MAIR0. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + + movs r3, #4 /* r3 = 4. */ + str r3, [r1] /* Program RNR = 4. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + #if ( configTOTAL_MPU_REGIONS == 16 ) + movs r3, #8 /* r3 = 8. */ + str r3, [r1] /* Program RNR = 8. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + movs r3, #12 /* r3 = 12. */ + str r3, [r1] /* Program RNR = 12. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + orr r2, #1 /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */ + str r2, [r1] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + + restore_context: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* r1 = pxCurrentTCB.*/ + ldr r2, [r1] /* r2 = Location of saved context in TCB. */ + + restore_special_regs: + #if ( configENABLE_PAC == 1 ) + ldmdb r2!, {r3-r6} /* Read task's dedicated PAC key from the task's context. */ + msr PAC_KEY_P_0, r3 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_1, r4 + msr PAC_KEY_P_2, r5 + msr PAC_KEY_P_3, r6 + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + ldmdb r2!, {r0, r3-r5, lr} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */ + msr psp, r3 + msr psplim, r4 + msr control, r5 + ldr r4, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + str r0, [r4] /* Restore xSecureContext. */ + cbz r0, restore_ns_context /* No secure context to restore. */ + + restore_s_context: + push {r1-r3, lr} + bl SecureContext_LoadContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r1-r3, lr} + + restore_ns_context: + mov r0, lr /* r0 = LR (EXC_RETURN). */ + lsls r0, r0, #25 /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bmi restore_context_done /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + + restore_general_regs: + ldmdb r2!, {r4-r11} /* r4-r11 contain hardware saved context. */ + stmia r3!, {r4-r11} /* Copy the hardware saved context on the task stack. */ + ldmdb r2!, {r4-r11} /* r4-r11 restored. */ + + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 + ittt eq + vldmdbeq r2!, {s0-s16} /* s0-s16 contain hardware saved FP context. */ + vstmiaeq r3!, {s0-s16} /* Copy hardware saved FP context on the task stack. */ + vldmdbeq r2!, {s16-s31} /* Restore s16-s31. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + + restore_context_done: + str r2, [r1] /* Save the location where the context should be saved next as the first member of TCB. */ + bx lr + +#else /* configENABLE_MPU */ + +PendSV_Handler: + ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + ldr r0, [r3] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */ + mrs r2, psp /* Read PSP in r2. */ + + cbz r0, save_ns_context /* No secure context to save. */ + save_s_context: + push {r0-r2, lr} + bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r0-r2, lr} + + save_ns_context: + mov r3, lr /* r3 = LR. */ + lsls r3, r3, #25 /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bmi save_special_regs /* If r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used. */ + + save_general_regs: + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + it eq + vstmdbeq r2!, {s16-s31} /* Store the additional FP context registers which are not saved automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + stmdb r2!, {r4-r11} /* Store the registers that are not saved automatically. */ + + save_special_regs: + mrs r3, psplim /* r3 = PSPLIM. */ + stmdb r2!, {r0, r3, lr} /* Store xSecureContext, PSPLIM and LR on the stack. */ + #if ( configENABLE_PAC == 1 ) + mrs r3, PAC_KEY_P_3 /* Read task's dedicated PAC key from the PAC key registers. */ + mrs r4, PAC_KEY_P_2 + mrs r5, PAC_KEY_P_1 + mrs r6, PAC_KEY_P_0 + stmdb r2!, {r3-r6} /* Store the task's dedicated PAC key on the stack. */ + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + + str r2, [r1] /* Save the new top of stack in TCB. */ + + select_next_task: + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bl vTaskSwitchContext + mov r0, #0 /* r0 = 0. */ + msr basepri, r0 /* Enable interrupts. */ + + restore_context: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB. */ + ldr r2, [r1] /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */ + + restore_special_regs: + #if ( configENABLE_PAC == 1 ) + ldmia r2!, {r3-r6} /* Read task's dedicated PAC key from stack. */ + msr PAC_KEY_P_3, r3 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_2, r4 + msr PAC_KEY_P_1, r5 + msr PAC_KEY_P_0, r6 + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + ldmia r2!, {r0, r3, lr} http://files.iar.com/ftp/pub/box/bxarm-9.60.3.deb/* Read from stack - r0 = xSecureContext, r3 = PSPLIM and LR restored. */ + msr psplim, r3 /* Restore the PSPLIM register value for the task. */ + ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + str r0, [r3] /* Restore the task's xSecureContext. */ + cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */ + + restore_s_context: + push {r1-r3, lr} + bl SecureContext_LoadContext /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r1-r3, lr} + + restore_ns_context: + mov r0, lr /* r0 = LR (EXC_RETURN). */ + lsls r0, r0, #25 /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bmi restore_context_done /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + + restore_general_regs: + ldmia r2!, {r4-r11} /* Restore the registers that are not automatically restored. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + it eq + vldmiaeq r2!, {s16-s31} /* Restore the additional FP context registers which are not restored automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + + restore_context_done: + msr psp, r2 /* Remember the new top of stack for the task. */ + bx lr + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + +SVC_Handler: + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + + ldr r1, [r0, #24] + ldrb r2, [r1, #-2] + cmp r2, #NUM_SYSTEM_CALLS + blt syscall_enter + cmp r2, #104 /* portSVC_SYSTEM_CALL_EXIT. */ + beq syscall_exit + b vPortSVCHandler_C + + syscall_enter: + mov r1, lr + b vSystemCallEnter + + syscall_exit: + mov r1, lr + b vSystemCallExit + +#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +SVC_Handler: + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + b vPortSVCHandler_C + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +vPortFreeSecureContext: + /* r0 = uint32_t *pulTCB. */ + ldr r2, [r0] /* The first item in the TCB is the top of the stack. */ + ldr r1, [r2] /* The first item on the stack is the task's xSecureContext. */ + cmp r1, #0 /* Raise svc if task's xSecureContext is not NULL. */ + it ne + svcne 101 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 101. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + + END diff --git a/portable/IAR/ARM_CM85/non_secure/portmacro.h b/portable/IAR/ARM_CM85/non_secure/portmacro.h new file mode 100644 index 000000000..ff5c9895d --- /dev/null +++ b/portable/IAR/ARM_CM85/non_secure/portmacro.h @@ -0,0 +1,86 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_MVE + #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE. +#endif /* configENABLE_MVE */ +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M85" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portARMV8M_MINOR_VERSION 1 +#define portDONT_DISCARD __root +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ +#pragma diag_suppress=Be006 +#pragma diag_suppress=Pa082 +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h new file mode 100644 index 000000000..f373bcad5 --- /dev/null +++ b/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h @@ -0,0 +1,582 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACROCOMMON_H +#define PORTMACROCOMMON_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. +#endif /* configENABLE_FPU */ + +#ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. +#endif /* configENABLE_MPU */ + +#ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. +#endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() +#define portINLINE __inline +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif +#define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ +extern BaseType_t xPortIsInsideInterrupt( void ); + +extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + +extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; +extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + +extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; +extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + +#if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_PAC == 1 ) + + /** + * @brief Generates 128-bit task's random PAC key. + * + * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be + * filled with a 128-bit random number. + */ + void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); + +#endif /* configENABLE_PAC */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ +#if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) +#else + #define portPRIVILEGE_BIT ( 0x0UL ) +#endif /* configENABLE_MPU */ + +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ +#define portPRIVILEGED_FLASH_REGION ( 0UL ) +#define portUNPRIVILEGED_FLASH_REGION ( 1UL ) +#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) +#define portPRIVILEGED_RAM_REGION ( 3UL ) +#define portSTACK_REGION ( 4UL ) +#define portFIRST_CONFIGURABLE_REGION ( 5UL ) +#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) +#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) +#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ +#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ +#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ +#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ +#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ +#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ +#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ +#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) +#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) +#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + +#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) +#define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) +#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) +#define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + +#define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + #ifndef configSYSTEM_CALL_STACK_SIZE + #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. + #endif + + /** + * @brief System call stack. + */ + typedef struct SYSTEM_CALL_STACK_INFO + { + uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; + uint32_t * pulSystemCallStack; + uint32_t * pulSystemCallStackLimit; + uint32_t * pulTaskStack; + uint32_t ulLinkRegisterAtSystemCallEntry; + uint32_t ulStackLimitRegisterAtSystemCallEntry; + } xSYSTEM_CALL_STACK_INFO; + + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + /** + * @brief MPU settings as stored in the TCB. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><-----------><----> + * 16 17 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 71 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 17 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 55 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | | | PC, xPSR | EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><-----------><----> + * 16 17 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 70 + + #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + /* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 17 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 54 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+------------------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +----------+-----------------+------------------------------+------------+-----+ + * + * <---------><----------------><------------------------------><-----------><----> + * 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 38 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+----------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | PC, xPSR | EXC_RETURN | | | + * +----------+-----------------+----------------------+------------+-----+ + * + * <---------><----------------><----------------------><-----------><----> + * 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 37 + + #else /* #if( configENABLE_TRUSTZONE == 1 ) */ + + /* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) + + /* Size of an Access Control List (ACL) entry in bits. */ + #define portACL_ENTRY_SIZE_BITS ( 32U ) + + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + uint32_t ulContext[ MAX_CONTEXT_SIZE ]; + uint32_t ulTaskFlags; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo; + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ]; + #endif + #endif + } xMPU_SETTINGS; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Validate priority of ISRs that are allowed to call FreeRTOS + * system calls. + */ +#if ( configASSERT_DEFINED == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif +#endif + +/** + * @brief SVC numbers. + */ +#define portSVC_ALLOCATE_SECURE_CONTEXT 100 +#define portSVC_FREE_SECURE_CONTEXT 101 +#define portSVC_START_SCHEDULER 102 +#define portSVC_RAISE_PRIVILEGE 103 +#define portSVC_SYSTEM_CALL_EXIT 104 +#define portSVC_YIELD 105 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) +#endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() +#else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + extern BaseType_t xPortIsTaskPrivileged( void ); + +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACROCOMMON_H */ diff --git a/portable/IAR/ARM_CM85/secure/secure_context.c b/portable/IAR/ARM_CM85/secure/secure_context.c new file mode 100644 index 000000000..3aa335e63 --- /dev/null +++ b/portable/IAR/ARM_CM85/secure/secure_context.c @@ -0,0 +1,354 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Secure context includes. */ +#include "secure_context.h" + +/* Secure heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief CONTROL value for privileged tasks. + * + * Bit[0] - 0 --> Thread mode is privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_PRIVILEGED 0x02 + +/** + * @brief CONTROL value for un-privileged tasks. + * + * Bit[0] - 1 --> Thread mode is un-privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03 + +/** + * @brief Size of stack seal values in bytes. + */ +#define securecontextSTACK_SEAL_SIZE 8 + +/** + * @brief Stack seal value as recommended by ARM. + */ +#define securecontextSTACK_SEAL_VALUE 0xFEF5EDA5 + +/** + * @brief Maximum number of secure contexts. + */ +#ifndef secureconfigMAX_SECURE_CONTEXTS + #define secureconfigMAX_SECURE_CONTEXTS 8UL +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Pre-allocated array of secure contexts. + */ +SecureContext_t xSecureContexts[ secureconfigMAX_SECURE_CONTEXTS ]; +/*-----------------------------------------------------------*/ + +/** + * @brief Get a free secure context for a task from the secure context pool (xSecureContexts). + * + * This function ensures that only one secure context is allocated for a task. + * + * @param[in] pvTaskHandle The task handle for which the secure context is allocated. + * + * @return Index of a free secure context in the xSecureContexts array. + */ +static uint32_t ulGetSecureContext( void * pvTaskHandle ); + +/** + * @brief Return the secure context to the secure context pool (xSecureContexts). + * + * @param[in] ulSecureContextIndex Index of the context in the xSecureContexts array. + */ +static void vReturnSecureContext( uint32_t ulSecureContextIndex ); + +/* These are implemented in assembly. */ +extern void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ); +extern void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ); +/*-----------------------------------------------------------*/ + +static uint32_t ulGetSecureContext( void * pvTaskHandle ) +{ + /* Start with invalid index. */ + uint32_t i, ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + if( ( xSecureContexts[ i ].pucCurrentStackPointer == NULL ) && + ( xSecureContexts[ i ].pucStackLimit == NULL ) && + ( xSecureContexts[ i ].pucStackStart == NULL ) && + ( xSecureContexts[ i ].pvTaskHandle == NULL ) && + ( ulSecureContextIndex == secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = i; + } + else if( xSecureContexts[ i ].pvTaskHandle == pvTaskHandle ) + { + /* A task can only have one secure context. Do not allocate a second + * context for the same task. */ + ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + break; + } + } + + return ulSecureContextIndex; +} +/*-----------------------------------------------------------*/ + +static void vReturnSecureContext( uint32_t ulSecureContextIndex ) +{ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackStart = NULL; + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = NULL; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) +{ + uint32_t ulIPSR, i; + static uint32_t ulSecureContextsInitialized = 0; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ( ulIPSR != 0 ) && ( ulSecureContextsInitialized == 0 ) ) + { + /* Ensure to initialize secure contexts only once. */ + ulSecureContextsInitialized = 1; + + /* No stack for thread mode until a task's context is loaded. */ + secureportSET_PSPLIM( securecontextNO_STACK ); + secureportSET_PSP( securecontextNO_STACK ); + + /* Initialize all secure contexts. */ + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + xSecureContexts[ i ].pucCurrentStackPointer = NULL; + xSecureContexts[ i ].pucStackLimit = NULL; + xSecureContexts[ i ].pucStackStart = NULL; + xSecureContexts[ i ].pvTaskHandle = NULL; + } + + #if ( configENABLE_MPU == 1 ) + { + /* Configure thread mode to use PSP and to be unprivileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); + } + #else /* configENABLE_MPU */ + { + /* Configure thread mode to use PSP and to be privileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); + } + #endif /* configENABLE_MPU */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ) +#else /* configENABLE_MPU */ + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ) +#endif /* configENABLE_MPU */ +{ + uint8_t * pucStackMemory = NULL; + uint8_t * pucStackLimit; + uint32_t ulIPSR, ulSecureContextIndex; + SecureContextHandle_t xSecureContextHandle = securecontextINVALID_CONTEXT_ID; + + #if ( configENABLE_MPU == 1 ) + uint32_t * pulCurrentStackPointer = NULL; + #endif /* configENABLE_MPU */ + + /* Read the Interrupt Program Status Register (IPSR) and Process Stack Limit + * Register (PSPLIM) value. */ + secureportREAD_IPSR( ulIPSR ); + secureportREAD_PSPLIM( pucStackLimit ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. + * Also do nothing, if a secure context us already loaded. PSPLIM is set to + * securecontextNO_STACK when no secure context is loaded. */ + if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) ) + { + /* Obtain a free secure context. */ + ulSecureContextIndex = ulGetSecureContext( pvTaskHandle ); + + /* Were we able to get a free context? */ + if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS ) + { + /* Allocate the stack space. */ + pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + + if( pucStackMemory != NULL ) + { + /* Since stack grows down, the starting point will be the last + * location. Note that this location is next to the last + * allocated byte for stack (excluding the space for seal values) + * because the hardware decrements the stack pointer before + * writing i.e. if stack pointer is 0x2, a push operation will + * decrement the stack pointer to 0x1 and then write at 0x1. */ + xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize; + + /* Seal the created secure process stack. */ + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; + + /* The stack cannot go beyond this location. This value is + * programmed in the PSPLIM register on context switch.*/ + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = pucStackMemory; + + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle; + + #if ( configENABLE_MPU == 1 ) + { + /* Store the correct CONTROL value for the task on the stack. + * This value is programmed in the CONTROL register on + * context switch. */ + pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; + pulCurrentStackPointer--; + + if( ulIsTaskPrivileged ) + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; + } + else + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; + } + + /* Store the current stack pointer. This value is programmed in + * the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + } + #else /* configENABLE_MPU */ + { + /* Current SP is set to the starting of the stack. This + * value programmed in the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + } + #endif /* configENABLE_MPU */ + + /* Ensure to never return 0 as a valid context handle. */ + xSecureContextHandle = ulSecureContextIndex + 1UL; + } + } + } + + return xSecureContextHandle; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) +{ + uint32_t ulIPSR, ulSecureContextIndex; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* Only free if a valid context handle is passed. */ + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + /* Ensure that the secure context being deleted is associated with + * the task. */ + if( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) + { + /* Free the stack space. */ + vPortFree( xSecureContexts[ ulSecureContextIndex ].pucStackLimit ); + + /* Return the secure context back to the free secure contexts pool. */ + vReturnSecureContext( ulSecureContextIndex ); + } + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that no secure context is loaded and the task is loading it's + * own context. */ + if( ( pucStackLimit == securecontextNO_STACK ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_LoadContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that task's context is loaded and the task is saving it's own + * context. */ + if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_SaveContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/ARM_CM85/secure/secure_context.h b/portable/IAR/ARM_CM85/secure/secure_context.h new file mode 100644 index 000000000..e36a8e430 --- /dev/null +++ b/portable/IAR/ARM_CM85/secure/secure_context.h @@ -0,0 +1,138 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_CONTEXT_H__ +#define __SECURE_CONTEXT_H__ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" + +/** + * @brief PSP value when no secure context is loaded. + */ +#define securecontextNO_STACK 0x0 + +/** + * @brief Invalid context ID. + */ +#define securecontextINVALID_CONTEXT_ID 0UL +/*-----------------------------------------------------------*/ + +/** + * @brief Structure to represent a secure context. + * + * @note Since stack grows down, pucStackStart is the highest address while + * pucStackLimit is the first address of the allocated memory. + */ +typedef struct SecureContext +{ + uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */ + uint8_t * pucStackLimit; /**< Last location of the stack memory (PSPLIM). */ + uint8_t * pucStackStart; /**< First location of the stack memory. */ + void * pvTaskHandle; /**< Task handle of the task this context is associated with. */ +} SecureContext_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Opaque handle for a secure context. + */ +typedef uint32_t SecureContextHandle_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Initializes the secure context management system. + * + * PSP is set to NULL and therefore a task must allocate and load a context + * before calling any secure side function in the thread mode. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureContext_Init( void ); + +/** + * @brief Allocates a context on the secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] ulSecureStackSize Size of the stack to allocate on secure side. + * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise. + * + * @return Opaque context handle if context is successfully allocated, NULL + * otherwise. + */ +#if ( configENABLE_MPU == 1 ) + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ); +#else /* configENABLE_MPU */ + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ); +#endif /* configENABLE_MPU */ + +/** + * @brief Frees the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the + * context to be freed. + */ +void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); + +/** + * @brief Loads the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be loaded. + */ +void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); + +/** + * @brief Saves the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be saved. + */ +void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); + +#endif /* __SECURE_CONTEXT_H__ */ diff --git a/portable/IAR/ARM_CM85/secure/secure_context_port_asm.s b/portable/IAR/ARM_CM85/secure/secure_context_port_asm.s new file mode 100644 index 000000000..27a8f3933 --- /dev/null +++ b/portable/IAR/ARM_CM85/secure/secure_context_port_asm.s @@ -0,0 +1,86 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + SECTION .text:CODE:NOROOT(2) + THUMB + +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" + + PUBLIC SecureContext_LoadContextAsm + PUBLIC SecureContext_SaveContextAsm +/*-----------------------------------------------------------*/ + +SecureContext_LoadContextAsm: + /* pxSecureContext value is in r0. */ + mrs r1, ipsr /* r1 = IPSR. */ + cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */ + ldmia r0!, {r1, r2} /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */ + +#if ( configENABLE_MPU == 1 ) + ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL. */ + msr control, r3 /* CONTROL = r3. */ +#endif /* configENABLE_MPU */ + + msr psplim, r2 /* PSPLIM = r2. */ + msr psp, r1 /* PSP = r1. */ + + load_ctx_therad_mode: + bx lr +/*-----------------------------------------------------------*/ + +SecureContext_SaveContextAsm: + /* pxSecureContext value is in r0. */ + mrs r1, ipsr /* r1 = IPSR. */ + cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */ + mrs r1, psp /* r1 = PSP. */ + +#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + vstmdb r1!, {s0} /* Trigger the deferred stacking of FPU registers. */ + vldmia r1!, {s0} /* Nullify the effect of the previous statement. */ +#endif /* configENABLE_FPU || configENABLE_MVE */ + +#if ( configENABLE_MPU == 1 ) + mrs r2, control /* r2 = CONTROL. */ + stmdb r1!, {r2} /* Store CONTROL value on the stack. */ +#endif /* configENABLE_MPU */ + + str r1, [r0] /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */ + movs r1, #0 /* r1 = securecontextNO_STACK. */ + msr psplim, r1 /* PSPLIM = securecontextNO_STACK. */ + msr psp, r1 /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */ + + save_ctx_therad_mode: + bx lr +/*-----------------------------------------------------------*/ + + END diff --git a/portable/IAR/ARM_CM85/secure/secure_heap.c b/portable/IAR/ARM_CM85/secure/secure_heap.c new file mode 100644 index 000000000..896b53e2d --- /dev/null +++ b/portable/IAR/ARM_CM85/secure/secure_heap.c @@ -0,0 +1,485 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Configuration includes. */ +#include "FreeRTOSConfig.h" + +/* Secure context heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Total heap size. + */ +#ifndef secureconfigTOTAL_HEAP_SIZE + #define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) ) +#endif + +/* No test marker by default. */ +#ifndef mtCOVERAGE_TEST_MARKER + #define mtCOVERAGE_TEST_MARKER() +#endif + +/* No tracing by default. */ +#ifndef traceMALLOC + #define traceMALLOC( pvReturn, xWantedSize ) +#endif + +/* No tracing by default. */ +#ifndef traceFREE + #define traceFREE( pv, xBlockSize ) +#endif + +/* Block sizes must not get too small. */ +#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) ) + +/* Assumes 8bit bytes! */ +#define secureheapBITS_PER_BYTE ( ( size_t ) 8 ) + +/* Max value that fits in a size_t type. */ +#define secureheapSIZE_MAX ( ~( ( size_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define secureheapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) ) + +/* MSB of the xBlockSize member of an BlockLink_t structure is used to track + * the allocation status of a block. When MSB of the xBlockSize member of + * an BlockLink_t structure is set then the block belongs to the application. + * When the bit is free the block is still part of the free heap space. */ +#define secureheapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) ) +#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 ) +#define secureheapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 ) +#define secureheapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK ) +#define secureheapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK ) +/*-----------------------------------------------------------*/ + +/* Allocate the memory for the heap. */ +#if ( configAPPLICATION_ALLOCATED_HEAP == 1 ) + +/* The application writer has already defined the array used for the RTOS +* heap - probably so it can be placed in a special segment or address. */ + extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#else /* configAPPLICATION_ALLOCATED_HEAP */ + static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#endif /* configAPPLICATION_ALLOCATED_HEAP */ + +/** + * @brief The linked list structure. + * + * This is used to link free blocks in order of their memory address. + */ +typedef struct A_BLOCK_LINK +{ + struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */ + size_t xBlockSize; /**< The size of the free block. */ +} BlockLink_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Called automatically to setup the required heap structures the first + * time pvPortMalloc() is called. + */ +static void prvHeapInit( void ); + +/** + * @brief Inserts a block of memory that is being freed into the correct + * position in the list of free memory blocks. + * + * The block being freed will be merged with the block in front it and/or the + * block behind it if the memory blocks are adjacent to each other. + * + * @param[in] pxBlockToInsert The block being freed. + */ +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ); +/*-----------------------------------------------------------*/ + +/** + * @brief The size of the structure placed at the beginning of each allocated + * memory block must by correctly byte aligned. + */ +static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + +/** + * @brief Create a couple of list links to mark the start and end of the list. + */ +static BlockLink_t xStart; +static BlockLink_t * pxEnd = NULL; + +/** + * @brief Keeps track of the number of free bytes remaining, but says nothing + * about fragmentation. + */ +static size_t xFreeBytesRemaining = 0U; +static size_t xMinimumEverFreeBytesRemaining = 0U; + +/*-----------------------------------------------------------*/ + +static void prvHeapInit( void ) +{ + BlockLink_t * pxFirstFreeBlock; + uint8_t * pucAlignedHeap; + size_t uxAddress; + size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE; + + /* Ensure the heap starts on a correctly aligned boundary. */ + uxAddress = ( size_t ) ucHeap; + + if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 ) + { + uxAddress += ( secureportBYTE_ALIGNMENT - 1 ); + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; + } + + pucAlignedHeap = ( uint8_t * ) uxAddress; + + /* xStart is used to hold a pointer to the first item in the list of free + * blocks. The void cast is used to prevent compiler warnings. */ + xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; + xStart.xBlockSize = ( size_t ) 0; + + /* pxEnd is used to mark the end of the list of free blocks and is inserted + * at the end of the heap space. */ + uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; + uxAddress -= xHeapStructSize; + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + pxEnd = ( void * ) uxAddress; + pxEnd->xBlockSize = 0; + pxEnd->pxNextFreeBlock = NULL; + + /* To start with there is a single free block that is sized to take up the + * entire heap space, minus the space taken by pxEnd. */ + pxFirstFreeBlock = ( void * ) pucAlignedHeap; + pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; + pxFirstFreeBlock->pxNextFreeBlock = pxEnd; + + /* Only one block exists - and it covers the entire usable heap space. */ + xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; +} +/*-----------------------------------------------------------*/ + +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) +{ + BlockLink_t * pxIterator; + uint8_t * puc; + + /* Iterate through the list until a block is found that has a higher address + * than the block being inserted. */ + for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) + { + /* Nothing to do here, just iterate to the right position. */ + } + + /* Do the block being inserted, and the block it is being inserted after + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxIterator; + + if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) + { + pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; + pxBlockToInsert = pxIterator; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Do the block being inserted, and the block it is being inserted before + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxBlockToInsert; + + if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) + { + if( pxIterator->pxNextFreeBlock != pxEnd ) + { + /* Form one big block from the two blocks. */ + pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxEnd; + } + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; + } + + /* If the block being inserted plugged a gap, so was merged with the block + * before and the block after, then it's pxNextFreeBlock pointer will have + * already been set, and should not be set here as that would make it point + * to itself. */ + if( pxIterator != pxBlockToInsert ) + { + pxIterator->pxNextFreeBlock = pxBlockToInsert; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} +/*-----------------------------------------------------------*/ + +void * pvPortMalloc( size_t xWantedSize ) +{ + BlockLink_t * pxBlock; + BlockLink_t * pxPreviousBlock; + BlockLink_t * pxNewBlockLink; + void * pvReturn = NULL; + size_t xAdditionalRequiredSize; + size_t xAllocatedBlockSize = 0; + + /* If this is the first call to malloc then the heap will require + * initialisation to setup the list of free blocks. */ + if( pxEnd == NULL ) + { + prvHeapInit(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xWantedSize > 0 ) + { + /* The wanted size must be increased so it can contain a BlockLink_t + * structure in addition to the requested amount of bytes. */ + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 ) + { + xWantedSize += xHeapStructSize; + + /* Ensure that blocks are always aligned to the required number + * of bytes. */ + if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 ) + { + /* Byte alignment required. */ + xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ); + + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 ) + { + xWantedSize += xAdditionalRequiredSize; + } + else + { + xWantedSize = 0; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + xWantedSize = 0; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Check the requested block size is not so large that the top bit is set. + * The top bit of the block size member of the BlockLink_t structure is used + * to determine who owns the block - the application or the kernel, so it + * must be free. */ + if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 ) + { + if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) + { + /* Traverse the list from the start (lowest address) block until + * one of adequate size is found. */ + pxPreviousBlock = &xStart; + pxBlock = xStart.pxNextFreeBlock; + + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + { + pxPreviousBlock = pxBlock; + pxBlock = pxBlock->pxNextFreeBlock; + } + + /* If the end marker was reached then a block of adequate size was + * not found. */ + if( pxBlock != pxEnd ) + { + /* Return the memory space pointed to - jumping over the + * BlockLink_t structure at its start. */ + pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); + + /* This block is being returned for use so must be taken out + * of the list of free blocks. */ + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + + /* If the block is larger than required it can be split into + * two. */ + if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE ) + { + /* This block is to be split into two. Create a new + * block following the number of bytes requested. The void + * cast is used to prevent byte alignment warnings from the + * compiler. */ + pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); + secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + + /* Calculate the sizes of two blocks split from the single + * block. */ + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + pxBlock->xBlockSize = xWantedSize; + + /* Insert the new block into the list of free blocks. */ + pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock; + pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xFreeBytesRemaining -= pxBlock->xBlockSize; + + if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) + { + xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xAllocatedBlockSize = pxBlock->xBlockSize; + + /* The block is being returned - it is allocated and owned by + * the application and has no "next" block. */ + secureheapALLOCATE_BLOCK( pxBlock ); + pxBlock->pxNextFreeBlock = NULL; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceMALLOC( pvReturn, xAllocatedBlockSize ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xAllocatedBlockSize; + + #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) + { + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */ + + secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 ); + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void * pv ) +{ + uint8_t * puc = ( uint8_t * ) pv; + BlockLink_t * pxLink; + + if( pv != NULL ) + { + /* The memory being freed will have an BlockLink_t structure immediately + * before it. */ + puc -= xHeapStructSize; + + /* This casting is to keep the compiler from issuing warnings. */ + pxLink = ( void * ) puc; + + /* Check the block is actually allocated. */ + secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ); + secureportASSERT( pxLink->pxNextFreeBlock == NULL ); + + if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ) + { + if( pxLink->pxNextFreeBlock == NULL ) + { + /* The block is being returned to the heap - it is no longer + * allocated. */ + secureheapFREE_BLOCK( pxLink ); + + secureportDISABLE_NON_SECURE_INTERRUPTS(); + { + /* Add this block to the list of free blocks. */ + xFreeBytesRemaining += pxLink->xBlockSize; + traceFREE( pv, pxLink->xBlockSize ); + prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); + } + secureportENABLE_NON_SECURE_INTERRUPTS(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } +} +/*-----------------------------------------------------------*/ + +size_t xPortGetFreeHeapSize( void ) +{ + return xFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +size_t xPortGetMinimumEverFreeHeapSize( void ) +{ + return xMinimumEverFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/ARM_CM85/secure/secure_heap.h b/portable/IAR/ARM_CM85/secure/secure_heap.h new file mode 100644 index 000000000..0e84a9d9d --- /dev/null +++ b/portable/IAR/ARM_CM85/secure/secure_heap.h @@ -0,0 +1,66 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_HEAP_H__ +#define __SECURE_HEAP_H__ + +/* Standard includes. */ +#include + +/** + * @brief Allocates memory from heap. + * + * @param[in] xWantedSize The size of the memory to be allocated. + * + * @return Pointer to the memory region if the allocation is successful, NULL + * otherwise. + */ +void * pvPortMalloc( size_t xWantedSize ); + +/** + * @brief Frees the previously allocated memory. + * + * @param[in] pv Pointer to the memory to be freed. + */ +void vPortFree( void * pv ); + +/** + * @brief Get the free heap size. + * + * @return Free heap size. + */ +size_t xPortGetFreeHeapSize( void ); + +/** + * @brief Get the minimum ever free heap size. + * + * @return Minimum ever free heap size. + */ +size_t xPortGetMinimumEverFreeHeapSize( void ); + +#endif /* __SECURE_HEAP_H__ */ diff --git a/portable/IAR/ARM_CM85/secure/secure_init.c b/portable/IAR/ARM_CM85/secure/secure_init.c new file mode 100644 index 000000000..c50d37668 --- /dev/null +++ b/portable/IAR/ARM_CM85/secure/secure_init.c @@ -0,0 +1,106 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Secure init includes. */ +#include "secure_init.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Constants required to manipulate the SCB. + */ +#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */ +#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL ) +#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS ) +#define secureinitSCB_AIRCR_PRIS_POS ( 14UL ) +#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS ) + +/** + * @brief Constants required to manipulate the FPU. + */ +#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define secureinitFPCCR_LSPENS_POS ( 29UL ) +#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS ) +#define secureinitFPCCR_TS_POS ( 26UL ) +#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS ) + +#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */ +#define secureinitNSACR_CP10_POS ( 10UL ) +#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS ) +#define secureinitNSACR_CP11_POS ( 11UL ) +#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS ) +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) | + ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) | + ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK ); + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is + * permitted. CP11 should be programmed to the same value as CP10. */ + *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK ); + + /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures + * that we can enable/disable lazy stacking in port.c file. */ + *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK ); + + /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP + * registers (S16-S31) are also pushed to stack on exception entry and + * restored on exception return. */ + *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK ); + } +} +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/ARM_CM85/secure/secure_init.h b/portable/IAR/ARM_CM85/secure/secure_init.h new file mode 100644 index 000000000..ebe04900f --- /dev/null +++ b/portable/IAR/ARM_CM85/secure/secure_init.h @@ -0,0 +1,54 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_INIT_H__ +#define __SECURE_INIT_H__ + +/** + * @brief De-prioritizes the non-secure exceptions. + * + * This is needed to ensure that the non-secure PendSV runs at the lowest + * priority. Context switch is done in the non-secure PendSV handler. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_DePrioritizeNSExceptions( void ); + +/** + * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access. + * + * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point + * Registers are not leaked to the non-secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_EnableNSFPUAccess( void ); + +#endif /* __SECURE_INIT_H__ */ diff --git a/portable/IAR/ARM_CM85/secure/secure_port_macros.h b/portable/IAR/ARM_CM85/secure/secure_port_macros.h new file mode 100644 index 000000000..a70da2c65 --- /dev/null +++ b/portable/IAR/ARM_CM85/secure/secure_port_macros.h @@ -0,0 +1,140 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_PORT_MACROS_H__ +#define __SECURE_PORT_MACROS_H__ + +/** + * @brief Byte alignment requirements. + */ +#define secureportBYTE_ALIGNMENT 8 +#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 ) + +/** + * @brief Macro to declare a function as non-secure callable. + */ +#if defined( __IAR_SYSTEMS_ICC__ ) + #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry __root +#else + #define secureportNON_SECURE_CALLABLE __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) ) +#endif + +/** + * @brief Set the secure PRIMASK value. + */ +#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Set the non-secure PRIMASK value. + */ +#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Read the PSP value in the given variable. + */ +#define secureportREAD_PSP( pucOutCurrentStackPointer ) \ + __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) ) + +/** + * @brief Set the PSP to the given value. + */ +#define secureportSET_PSP( pucCurrentStackPointer ) \ + __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) ) + +/** + * @brief Read the PSPLIM value in the given variable. + */ +#define secureportREAD_PSPLIM( pucOutStackLimit ) \ + __asm volatile ( "mrs %0, psplim" : "=r" ( pucOutStackLimit ) ) + +/** + * @brief Set the PSPLIM to the given value. + */ +#define secureportSET_PSPLIM( pucStackLimit ) \ + __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) ) + +/** + * @brief Set the NonSecure MSP to the given value. + */ +#define secureportSET_MSP_NS( pucMainStackPointer ) \ + __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) ) + +/** + * @brief Set the CONTROL register to the given value. + */ +#define secureportSET_CONTROL( ulControl ) \ + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" ) + +/** + * @brief Read the Interrupt Program Status Register (IPSR) value in the given + * variable. + */ +#define secureportREAD_IPSR( ulIPSR ) \ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) ) + +/** + * @brief PRIMASK value to enable interrupts. + */ +#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0 + +/** + * @brief PRIMASK value to disable interrupts. + */ +#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1 + +/** + * @brief Disable secure interrupts. + */ +#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Disable non-secure interrupts. + * + * This effectively disables context switches. + */ +#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Enable non-secure interrupts. + */ +#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL ) + +/** + * @brief Assert definition. + */ +#define secureportASSERT( x ) \ + if( ( x ) == 0 ) \ + { \ + secureportDISABLE_SECURE_INTERRUPTS(); \ + secureportDISABLE_NON_SECURE_INTERRUPTS(); \ + for( ; ; ) {; } \ + } + +#endif /* __SECURE_PORT_MACROS_H__ */ diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S new file mode 100644 index 000000000..d2cb78e92 --- /dev/null +++ b/portable/IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S @@ -0,0 +1,1242 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + + SECTION freertos_system_calls:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +#include "FreeRTOSConfig.h" +#include "mpu_syscall_numbers.h" + +#ifndef configUSE_MPU_WRAPPERS_V1 + #define configUSE_MPU_WRAPPERS_V1 0 +#endif + +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + PUBLIC MPU_xTaskDelayUntil +MPU_xTaskDelayUntil: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskDelayUntil_Unpriv + MPU_xTaskDelayUntil_Priv: + b MPU_xTaskDelayUntilImpl + MPU_xTaskDelayUntil_Unpriv: + svc #SYSTEM_CALL_xTaskDelayUntil +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskAbortDelay +MPU_xTaskAbortDelay: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskAbortDelay_Unpriv + MPU_xTaskAbortDelay_Priv: + b MPU_xTaskAbortDelayImpl + MPU_xTaskAbortDelay_Unpriv: + svc #SYSTEM_CALL_xTaskAbortDelay +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskDelay +MPU_vTaskDelay: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskDelay_Unpriv + MPU_vTaskDelay_Priv: + b MPU_vTaskDelayImpl + MPU_vTaskDelay_Unpriv: + svc #SYSTEM_CALL_vTaskDelay +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskPriorityGet +MPU_uxTaskPriorityGet: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskPriorityGet_Unpriv + MPU_uxTaskPriorityGet_Priv: + b MPU_uxTaskPriorityGetImpl + MPU_uxTaskPriorityGet_Unpriv: + svc #SYSTEM_CALL_uxTaskPriorityGet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_eTaskGetState +MPU_eTaskGetState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_eTaskGetState_Unpriv + MPU_eTaskGetState_Priv: + b MPU_eTaskGetStateImpl + MPU_eTaskGetState_Unpriv: + svc #SYSTEM_CALL_eTaskGetState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskGetInfo +MPU_vTaskGetInfo: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskGetInfo_Unpriv + MPU_vTaskGetInfo_Priv: + b MPU_vTaskGetInfoImpl + MPU_vTaskGetInfo_Unpriv: + svc #SYSTEM_CALL_vTaskGetInfo +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetIdleTaskHandle +MPU_xTaskGetIdleTaskHandle: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetIdleTaskHandle_Unpriv + MPU_xTaskGetIdleTaskHandle_Priv: + b MPU_xTaskGetIdleTaskHandleImpl + MPU_xTaskGetIdleTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTaskGetIdleTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSuspend +MPU_vTaskSuspend: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSuspend_Unpriv + MPU_vTaskSuspend_Priv: + b MPU_vTaskSuspendImpl + MPU_vTaskSuspend_Unpriv: + svc #SYSTEM_CALL_vTaskSuspend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskResume +MPU_vTaskResume: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskResume_Unpriv + MPU_vTaskResume_Priv: + b MPU_vTaskResumeImpl + MPU_vTaskResume_Unpriv: + svc #SYSTEM_CALL_vTaskResume +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetTickCount +MPU_xTaskGetTickCount: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetTickCount_Unpriv + MPU_xTaskGetTickCount_Priv: + b MPU_xTaskGetTickCountImpl + MPU_xTaskGetTickCount_Unpriv: + svc #SYSTEM_CALL_xTaskGetTickCount +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetNumberOfTasks +MPU_uxTaskGetNumberOfTasks: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetNumberOfTasks_Unpriv + MPU_uxTaskGetNumberOfTasks_Priv: + b MPU_uxTaskGetNumberOfTasksImpl + MPU_uxTaskGetNumberOfTasks_Unpriv: + svc #SYSTEM_CALL_uxTaskGetNumberOfTasks +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetRunTimeCounter +MPU_ulTaskGetRunTimeCounter: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetRunTimeCounter_Unpriv + MPU_ulTaskGetRunTimeCounter_Priv: + b MPU_ulTaskGetRunTimeCounterImpl + MPU_ulTaskGetRunTimeCounter_Unpriv: + svc #SYSTEM_CALL_ulTaskGetRunTimeCounter +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetRunTimePercent +MPU_ulTaskGetRunTimePercent: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetRunTimePercent_Unpriv + MPU_ulTaskGetRunTimePercent_Priv: + b MPU_ulTaskGetRunTimePercentImpl + MPU_ulTaskGetRunTimePercent_Unpriv: + svc #SYSTEM_CALL_ulTaskGetRunTimePercent +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetIdleRunTimePercent +MPU_ulTaskGetIdleRunTimePercent: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetIdleRunTimePercent_Unpriv + MPU_ulTaskGetIdleRunTimePercent_Priv: + b MPU_ulTaskGetIdleRunTimePercentImpl + MPU_ulTaskGetIdleRunTimePercent_Unpriv: + svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetIdleRunTimeCounter +MPU_ulTaskGetIdleRunTimeCounter: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv + MPU_ulTaskGetIdleRunTimeCounter_Priv: + b MPU_ulTaskGetIdleRunTimeCounterImpl + MPU_ulTaskGetIdleRunTimeCounter_Unpriv: + svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetApplicationTaskTag +MPU_vTaskSetApplicationTaskTag: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetApplicationTaskTag_Unpriv + MPU_vTaskSetApplicationTaskTag_Priv: + b MPU_vTaskSetApplicationTaskTagImpl + MPU_vTaskSetApplicationTaskTag_Unpriv: + svc #SYSTEM_CALL_vTaskSetApplicationTaskTag +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetApplicationTaskTag +MPU_xTaskGetApplicationTaskTag: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetApplicationTaskTag_Unpriv + MPU_xTaskGetApplicationTaskTag_Priv: + b MPU_xTaskGetApplicationTaskTagImpl + MPU_xTaskGetApplicationTaskTag_Unpriv: + svc #SYSTEM_CALL_xTaskGetApplicationTaskTag +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetThreadLocalStoragePointer +MPU_vTaskSetThreadLocalStoragePointer: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv + MPU_vTaskSetThreadLocalStoragePointer_Priv: + b MPU_vTaskSetThreadLocalStoragePointerImpl + MPU_vTaskSetThreadLocalStoragePointer_Unpriv: + svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pvTaskGetThreadLocalStoragePointer +MPU_pvTaskGetThreadLocalStoragePointer: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv + MPU_pvTaskGetThreadLocalStoragePointer_Priv: + b MPU_pvTaskGetThreadLocalStoragePointerImpl + MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: + svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetSystemState +MPU_uxTaskGetSystemState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetSystemState_Unpriv + MPU_uxTaskGetSystemState_Priv: + b MPU_uxTaskGetSystemStateImpl + MPU_uxTaskGetSystemState_Unpriv: + svc #SYSTEM_CALL_uxTaskGetSystemState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetStackHighWaterMark +MPU_uxTaskGetStackHighWaterMark: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetStackHighWaterMark_Unpriv + MPU_uxTaskGetStackHighWaterMark_Priv: + b MPU_uxTaskGetStackHighWaterMarkImpl + MPU_uxTaskGetStackHighWaterMark_Unpriv: + svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetStackHighWaterMark2 +MPU_uxTaskGetStackHighWaterMark2: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetStackHighWaterMark2_Unpriv + MPU_uxTaskGetStackHighWaterMark2_Priv: + b MPU_uxTaskGetStackHighWaterMark2Impl + MPU_uxTaskGetStackHighWaterMark2_Unpriv: + svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2 +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetCurrentTaskHandle +MPU_xTaskGetCurrentTaskHandle: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetCurrentTaskHandle_Unpriv + MPU_xTaskGetCurrentTaskHandle_Priv: + b MPU_xTaskGetCurrentTaskHandleImpl + MPU_xTaskGetCurrentTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetSchedulerState +MPU_xTaskGetSchedulerState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetSchedulerState_Unpriv + MPU_xTaskGetSchedulerState_Priv: + b MPU_xTaskGetSchedulerStateImpl + MPU_xTaskGetSchedulerState_Unpriv: + svc #SYSTEM_CALL_xTaskGetSchedulerState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetTimeOutState +MPU_vTaskSetTimeOutState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetTimeOutState_Unpriv + MPU_vTaskSetTimeOutState_Priv: + b MPU_vTaskSetTimeOutStateImpl + MPU_vTaskSetTimeOutState_Unpriv: + svc #SYSTEM_CALL_vTaskSetTimeOutState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskCheckForTimeOut +MPU_xTaskCheckForTimeOut: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskCheckForTimeOut_Unpriv + MPU_xTaskCheckForTimeOut_Priv: + b MPU_xTaskCheckForTimeOutImpl + MPU_xTaskCheckForTimeOut_Unpriv: + svc #SYSTEM_CALL_xTaskCheckForTimeOut +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyEntry +MPU_xTaskGenericNotifyEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotify_Unpriv + MPU_xTaskGenericNotify_Priv: + b MPU_xTaskGenericNotifyImpl + MPU_xTaskGenericNotify_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotify +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyWaitEntry +MPU_xTaskGenericNotifyWaitEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotifyWait_Unpriv + MPU_xTaskGenericNotifyWait_Priv: + b MPU_xTaskGenericNotifyWaitImpl + MPU_xTaskGenericNotifyWait_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotifyWait +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGenericNotifyTake +MPU_ulTaskGenericNotifyTake: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGenericNotifyTake_Unpriv + MPU_ulTaskGenericNotifyTake_Priv: + b MPU_ulTaskGenericNotifyTakeImpl + MPU_ulTaskGenericNotifyTake_Unpriv: + svc #SYSTEM_CALL_ulTaskGenericNotifyTake +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyStateClear +MPU_xTaskGenericNotifyStateClear: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotifyStateClear_Unpriv + MPU_xTaskGenericNotifyStateClear_Priv: + b MPU_xTaskGenericNotifyStateClearImpl + MPU_xTaskGenericNotifyStateClear_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotifyStateClear +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGenericNotifyValueClear +MPU_ulTaskGenericNotifyValueClear: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGenericNotifyValueClear_Unpriv + MPU_ulTaskGenericNotifyValueClear_Priv: + b MPU_ulTaskGenericNotifyValueClearImpl + MPU_ulTaskGenericNotifyValueClear_Unpriv: + svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGenericSend +MPU_xQueueGenericSend: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGenericSend_Unpriv + MPU_xQueueGenericSend_Priv: + b MPU_xQueueGenericSendImpl + MPU_xQueueGenericSend_Unpriv: + svc #SYSTEM_CALL_xQueueGenericSend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxQueueMessagesWaiting +MPU_uxQueueMessagesWaiting: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxQueueMessagesWaiting_Unpriv + MPU_uxQueueMessagesWaiting_Priv: + b MPU_uxQueueMessagesWaitingImpl + MPU_uxQueueMessagesWaiting_Unpriv: + svc #SYSTEM_CALL_uxQueueMessagesWaiting +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxQueueSpacesAvailable +MPU_uxQueueSpacesAvailable: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxQueueSpacesAvailable_Unpriv + MPU_uxQueueSpacesAvailable_Priv: + b MPU_uxQueueSpacesAvailableImpl + MPU_uxQueueSpacesAvailable_Unpriv: + svc #SYSTEM_CALL_uxQueueSpacesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueReceive +MPU_xQueueReceive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueReceive_Unpriv + MPU_xQueueReceive_Priv: + b MPU_xQueueReceiveImpl + MPU_xQueueReceive_Unpriv: + svc #SYSTEM_CALL_xQueueReceive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueuePeek +MPU_xQueuePeek: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueuePeek_Unpriv + MPU_xQueuePeek_Priv: + b MPU_xQueuePeekImpl + MPU_xQueuePeek_Unpriv: + svc #SYSTEM_CALL_xQueuePeek +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueSemaphoreTake +MPU_xQueueSemaphoreTake: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueSemaphoreTake_Unpriv + MPU_xQueueSemaphoreTake_Priv: + b MPU_xQueueSemaphoreTakeImpl + MPU_xQueueSemaphoreTake_Unpriv: + svc #SYSTEM_CALL_xQueueSemaphoreTake +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGetMutexHolder +MPU_xQueueGetMutexHolder: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGetMutexHolder_Unpriv + MPU_xQueueGetMutexHolder_Priv: + b MPU_xQueueGetMutexHolderImpl + MPU_xQueueGetMutexHolder_Unpriv: + svc #SYSTEM_CALL_xQueueGetMutexHolder +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueTakeMutexRecursive +MPU_xQueueTakeMutexRecursive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueTakeMutexRecursive_Unpriv + MPU_xQueueTakeMutexRecursive_Priv: + b MPU_xQueueTakeMutexRecursiveImpl + MPU_xQueueTakeMutexRecursive_Unpriv: + svc #SYSTEM_CALL_xQueueTakeMutexRecursive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGiveMutexRecursive +MPU_xQueueGiveMutexRecursive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGiveMutexRecursive_Unpriv + MPU_xQueueGiveMutexRecursive_Priv: + b MPU_xQueueGiveMutexRecursiveImpl + MPU_xQueueGiveMutexRecursive_Unpriv: + svc #SYSTEM_CALL_xQueueGiveMutexRecursive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueSelectFromSet +MPU_xQueueSelectFromSet: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueSelectFromSet_Unpriv + MPU_xQueueSelectFromSet_Priv: + b MPU_xQueueSelectFromSetImpl + MPU_xQueueSelectFromSet_Unpriv: + svc #SYSTEM_CALL_xQueueSelectFromSet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueAddToSet +MPU_xQueueAddToSet: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueAddToSet_Unpriv + MPU_xQueueAddToSet_Priv: + b MPU_xQueueAddToSetImpl + MPU_xQueueAddToSet_Unpriv: + svc #SYSTEM_CALL_xQueueAddToSet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vQueueAddToRegistry +MPU_vQueueAddToRegistry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vQueueAddToRegistry_Unpriv + MPU_vQueueAddToRegistry_Priv: + b MPU_vQueueAddToRegistryImpl + MPU_vQueueAddToRegistry_Unpriv: + svc #SYSTEM_CALL_vQueueAddToRegistry +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vQueueUnregisterQueue +MPU_vQueueUnregisterQueue: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vQueueUnregisterQueue_Unpriv + MPU_vQueueUnregisterQueue_Priv: + b MPU_vQueueUnregisterQueueImpl + MPU_vQueueUnregisterQueue_Unpriv: + svc #SYSTEM_CALL_vQueueUnregisterQueue +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pcQueueGetName +MPU_pcQueueGetName: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pcQueueGetName_Unpriv + MPU_pcQueueGetName_Priv: + b MPU_pcQueueGetNameImpl + MPU_pcQueueGetName_Unpriv: + svc #SYSTEM_CALL_pcQueueGetName +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pvTimerGetTimerID +MPU_pvTimerGetTimerID: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pvTimerGetTimerID_Unpriv + MPU_pvTimerGetTimerID_Priv: + b MPU_pvTimerGetTimerIDImpl + MPU_pvTimerGetTimerID_Unpriv: + svc #SYSTEM_CALL_pvTimerGetTimerID +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTimerSetTimerID +MPU_vTimerSetTimerID: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTimerSetTimerID_Unpriv + MPU_vTimerSetTimerID_Priv: + b MPU_vTimerSetTimerIDImpl + MPU_vTimerSetTimerID_Unpriv: + svc #SYSTEM_CALL_vTimerSetTimerID +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerIsTimerActive +MPU_xTimerIsTimerActive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerIsTimerActive_Unpriv + MPU_xTimerIsTimerActive_Priv: + b MPU_xTimerIsTimerActiveImpl + MPU_xTimerIsTimerActive_Unpriv: + svc #SYSTEM_CALL_xTimerIsTimerActive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetTimerDaemonTaskHandle +MPU_xTimerGetTimerDaemonTaskHandle: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv + MPU_xTimerGetTimerDaemonTaskHandle_Priv: + b MPU_xTimerGetTimerDaemonTaskHandleImpl + MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGenericCommandFromTaskEntry +MPU_xTimerGenericCommandFromTaskEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGenericCommandFromTask_Unpriv + MPU_xTimerGenericCommandFromTask_Priv: + b MPU_xTimerGenericCommandFromTaskImpl + MPU_xTimerGenericCommandFromTask_Unpriv: + svc #SYSTEM_CALL_xTimerGenericCommandFromTask +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pcTimerGetName +MPU_pcTimerGetName: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pcTimerGetName_Unpriv + MPU_pcTimerGetName_Priv: + b MPU_pcTimerGetNameImpl + MPU_pcTimerGetName_Unpriv: + svc #SYSTEM_CALL_pcTimerGetName +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTimerSetReloadMode +MPU_vTimerSetReloadMode: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTimerSetReloadMode_Unpriv + MPU_vTimerSetReloadMode_Priv: + b MPU_vTimerSetReloadModeImpl + MPU_vTimerSetReloadMode_Unpriv: + svc #SYSTEM_CALL_vTimerSetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetReloadMode +MPU_xTimerGetReloadMode: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetReloadMode_Unpriv + MPU_xTimerGetReloadMode_Priv: + b MPU_xTimerGetReloadModeImpl + MPU_xTimerGetReloadMode_Unpriv: + svc #SYSTEM_CALL_xTimerGetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTimerGetReloadMode +MPU_uxTimerGetReloadMode: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTimerGetReloadMode_Unpriv + MPU_uxTimerGetReloadMode_Priv: + b MPU_uxTimerGetReloadModeImpl + MPU_uxTimerGetReloadMode_Unpriv: + svc #SYSTEM_CALL_uxTimerGetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetPeriod +MPU_xTimerGetPeriod: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetPeriod_Unpriv + MPU_xTimerGetPeriod_Priv: + b MPU_xTimerGetPeriodImpl + MPU_xTimerGetPeriod_Unpriv: + svc #SYSTEM_CALL_xTimerGetPeriod +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetExpiryTime +MPU_xTimerGetExpiryTime: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetExpiryTime_Unpriv + MPU_xTimerGetExpiryTime_Priv: + b MPU_xTimerGetExpiryTimeImpl + MPU_xTimerGetExpiryTime_Unpriv: + svc #SYSTEM_CALL_xTimerGetExpiryTime +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupWaitBitsEntry +MPU_xEventGroupWaitBitsEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupWaitBits_Unpriv + MPU_xEventGroupWaitBits_Priv: + b MPU_xEventGroupWaitBitsImpl + MPU_xEventGroupWaitBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupWaitBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupClearBits +MPU_xEventGroupClearBits: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupClearBits_Unpriv + MPU_xEventGroupClearBits_Priv: + b MPU_xEventGroupClearBitsImpl + MPU_xEventGroupClearBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupClearBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupSetBits +MPU_xEventGroupSetBits: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupSetBits_Unpriv + MPU_xEventGroupSetBits_Priv: + b MPU_xEventGroupSetBitsImpl + MPU_xEventGroupSetBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupSetBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupSync +MPU_xEventGroupSync: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupSync_Unpriv + MPU_xEventGroupSync_Priv: + b MPU_xEventGroupSyncImpl + MPU_xEventGroupSync_Unpriv: + svc #SYSTEM_CALL_xEventGroupSync +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxEventGroupGetNumber +MPU_uxEventGroupGetNumber: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxEventGroupGetNumber_Unpriv + MPU_uxEventGroupGetNumber_Priv: + b MPU_uxEventGroupGetNumberImpl + MPU_uxEventGroupGetNumber_Unpriv: + svc #SYSTEM_CALL_uxEventGroupGetNumber +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vEventGroupSetNumber +MPU_vEventGroupSetNumber: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vEventGroupSetNumber_Unpriv + MPU_vEventGroupSetNumber_Priv: + b MPU_vEventGroupSetNumberImpl + MPU_vEventGroupSetNumber_Unpriv: + svc #SYSTEM_CALL_vEventGroupSetNumber +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSend +MPU_xStreamBufferSend: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSend_Unpriv + MPU_xStreamBufferSend_Priv: + b MPU_xStreamBufferSendImpl + MPU_xStreamBufferSend_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferReceive +MPU_xStreamBufferReceive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferReceive_Unpriv + MPU_xStreamBufferReceive_Priv: + b MPU_xStreamBufferReceiveImpl + MPU_xStreamBufferReceive_Unpriv: + svc #SYSTEM_CALL_xStreamBufferReceive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferIsFull +MPU_xStreamBufferIsFull: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferIsFull_Unpriv + MPU_xStreamBufferIsFull_Priv: + b MPU_xStreamBufferIsFullImpl + MPU_xStreamBufferIsFull_Unpriv: + svc #SYSTEM_CALL_xStreamBufferIsFull +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferIsEmpty +MPU_xStreamBufferIsEmpty: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferIsEmpty_Unpriv + MPU_xStreamBufferIsEmpty_Priv: + b MPU_xStreamBufferIsEmptyImpl + MPU_xStreamBufferIsEmpty_Unpriv: + svc #SYSTEM_CALL_xStreamBufferIsEmpty +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSpacesAvailable +MPU_xStreamBufferSpacesAvailable: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSpacesAvailable_Unpriv + MPU_xStreamBufferSpacesAvailable_Priv: + b MPU_xStreamBufferSpacesAvailableImpl + MPU_xStreamBufferSpacesAvailable_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSpacesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferBytesAvailable +MPU_xStreamBufferBytesAvailable: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferBytesAvailable_Unpriv + MPU_xStreamBufferBytesAvailable_Priv: + b MPU_xStreamBufferBytesAvailableImpl + MPU_xStreamBufferBytesAvailable_Unpriv: + svc #SYSTEM_CALL_xStreamBufferBytesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSetTriggerLevel +MPU_xStreamBufferSetTriggerLevel: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSetTriggerLevel_Unpriv + MPU_xStreamBufferSetTriggerLevel_Priv: + b MPU_xStreamBufferSetTriggerLevelImpl + MPU_xStreamBufferSetTriggerLevel_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferNextMessageLengthBytes +MPU_xStreamBufferNextMessageLengthBytes: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv + MPU_xStreamBufferNextMessageLengthBytes_Priv: + b MPU_xStreamBufferNextMessageLengthBytesImpl + MPU_xStreamBufferNextMessageLengthBytes_Unpriv: + svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes +/*-----------------------------------------------------------*/ + +/* Default weak implementations in case one is not available from + * mpu_wrappers because of config options. */ + + PUBWEAK MPU_xTaskDelayUntilImpl +MPU_xTaskDelayUntilImpl: + b MPU_xTaskDelayUntilImpl + + PUBWEAK MPU_xTaskAbortDelayImpl +MPU_xTaskAbortDelayImpl: + b MPU_xTaskAbortDelayImpl + + PUBWEAK MPU_vTaskDelayImpl +MPU_vTaskDelayImpl: + b MPU_vTaskDelayImpl + + PUBWEAK MPU_uxTaskPriorityGetImpl +MPU_uxTaskPriorityGetImpl: + b MPU_uxTaskPriorityGetImpl + + PUBWEAK MPU_eTaskGetStateImpl +MPU_eTaskGetStateImpl: + b MPU_eTaskGetStateImpl + + PUBWEAK MPU_vTaskGetInfoImpl +MPU_vTaskGetInfoImpl: + b MPU_vTaskGetInfoImpl + + PUBWEAK MPU_xTaskGetIdleTaskHandleImpl +MPU_xTaskGetIdleTaskHandleImpl: + b MPU_xTaskGetIdleTaskHandleImpl + + PUBWEAK MPU_vTaskSuspendImpl +MPU_vTaskSuspendImpl: + b MPU_vTaskSuspendImpl + + PUBWEAK MPU_vTaskResumeImpl +MPU_vTaskResumeImpl: + b MPU_vTaskResumeImpl + + PUBWEAK MPU_xTaskGetTickCountImpl +MPU_xTaskGetTickCountImpl: + b MPU_xTaskGetTickCountImpl + + PUBWEAK MPU_uxTaskGetNumberOfTasksImpl +MPU_uxTaskGetNumberOfTasksImpl: + b MPU_uxTaskGetNumberOfTasksImpl + + PUBWEAK MPU_ulTaskGetRunTimeCounterImpl +MPU_ulTaskGetRunTimeCounterImpl: + b MPU_ulTaskGetRunTimeCounterImpl + + PUBWEAK MPU_ulTaskGetRunTimePercentImpl +MPU_ulTaskGetRunTimePercentImpl: + b MPU_ulTaskGetRunTimePercentImpl + + PUBWEAK MPU_ulTaskGetIdleRunTimePercentImpl +MPU_ulTaskGetIdleRunTimePercentImpl: + b MPU_ulTaskGetIdleRunTimePercentImpl + + PUBWEAK MPU_ulTaskGetIdleRunTimeCounterImpl +MPU_ulTaskGetIdleRunTimeCounterImpl: + b MPU_ulTaskGetIdleRunTimeCounterImpl + + PUBWEAK MPU_vTaskSetApplicationTaskTagImpl +MPU_vTaskSetApplicationTaskTagImpl: + b MPU_vTaskSetApplicationTaskTagImpl + + PUBWEAK MPU_xTaskGetApplicationTaskTagImpl +MPU_xTaskGetApplicationTaskTagImpl: + b MPU_xTaskGetApplicationTaskTagImpl + + PUBWEAK MPU_vTaskSetThreadLocalStoragePointerImpl +MPU_vTaskSetThreadLocalStoragePointerImpl: + b MPU_vTaskSetThreadLocalStoragePointerImpl + + PUBWEAK MPU_pvTaskGetThreadLocalStoragePointerImpl +MPU_pvTaskGetThreadLocalStoragePointerImpl: + b MPU_pvTaskGetThreadLocalStoragePointerImpl + + PUBWEAK MPU_uxTaskGetSystemStateImpl +MPU_uxTaskGetSystemStateImpl: + b MPU_uxTaskGetSystemStateImpl + + PUBWEAK MPU_uxTaskGetStackHighWaterMarkImpl +MPU_uxTaskGetStackHighWaterMarkImpl: + b MPU_uxTaskGetStackHighWaterMarkImpl + + PUBWEAK MPU_uxTaskGetStackHighWaterMark2Impl +MPU_uxTaskGetStackHighWaterMark2Impl: + b MPU_uxTaskGetStackHighWaterMark2Impl + + PUBWEAK MPU_xTaskGetCurrentTaskHandleImpl +MPU_xTaskGetCurrentTaskHandleImpl: + b MPU_xTaskGetCurrentTaskHandleImpl + + PUBWEAK MPU_xTaskGetSchedulerStateImpl +MPU_xTaskGetSchedulerStateImpl: + b MPU_xTaskGetSchedulerStateImpl + + PUBWEAK MPU_vTaskSetTimeOutStateImpl +MPU_vTaskSetTimeOutStateImpl: + b MPU_vTaskSetTimeOutStateImpl + + PUBWEAK MPU_xTaskCheckForTimeOutImpl +MPU_xTaskCheckForTimeOutImpl: + b MPU_xTaskCheckForTimeOutImpl + + PUBWEAK MPU_xTaskGenericNotifyImpl +MPU_xTaskGenericNotifyImpl: + b MPU_xTaskGenericNotifyImpl + + PUBWEAK MPU_xTaskGenericNotifyWaitImpl +MPU_xTaskGenericNotifyWaitImpl: + b MPU_xTaskGenericNotifyWaitImpl + + PUBWEAK MPU_ulTaskGenericNotifyTakeImpl +MPU_ulTaskGenericNotifyTakeImpl: + b MPU_ulTaskGenericNotifyTakeImpl + + PUBWEAK MPU_xTaskGenericNotifyStateClearImpl +MPU_xTaskGenericNotifyStateClearImpl: + b MPU_xTaskGenericNotifyStateClearImpl + + PUBWEAK MPU_ulTaskGenericNotifyValueClearImpl +MPU_ulTaskGenericNotifyValueClearImpl: + b MPU_ulTaskGenericNotifyValueClearImpl + + PUBWEAK MPU_xQueueGenericSendImpl +MPU_xQueueGenericSendImpl: + b MPU_xQueueGenericSendImpl + + PUBWEAK MPU_uxQueueMessagesWaitingImpl +MPU_uxQueueMessagesWaitingImpl: + b MPU_uxQueueMessagesWaitingImpl + + PUBWEAK MPU_uxQueueSpacesAvailableImpl +MPU_uxQueueSpacesAvailableImpl: + b MPU_uxQueueSpacesAvailableImpl + + PUBWEAK MPU_xQueueReceiveImpl +MPU_xQueueReceiveImpl: + b MPU_xQueueReceiveImpl + + PUBWEAK MPU_xQueuePeekImpl +MPU_xQueuePeekImpl: + b MPU_xQueuePeekImpl + + PUBWEAK MPU_xQueueSemaphoreTakeImpl +MPU_xQueueSemaphoreTakeImpl: + b MPU_xQueueSemaphoreTakeImpl + + PUBWEAK MPU_xQueueGetMutexHolderImpl +MPU_xQueueGetMutexHolderImpl: + b MPU_xQueueGetMutexHolderImpl + + PUBWEAK MPU_xQueueTakeMutexRecursiveImpl +MPU_xQueueTakeMutexRecursiveImpl: + b MPU_xQueueTakeMutexRecursiveImpl + + PUBWEAK MPU_xQueueGiveMutexRecursiveImpl +MPU_xQueueGiveMutexRecursiveImpl: + b MPU_xQueueGiveMutexRecursiveImpl + + PUBWEAK MPU_xQueueSelectFromSetImpl +MPU_xQueueSelectFromSetImpl: + b MPU_xQueueSelectFromSetImpl + + PUBWEAK MPU_xQueueAddToSetImpl +MPU_xQueueAddToSetImpl: + b MPU_xQueueAddToSetImpl + + PUBWEAK MPU_vQueueAddToRegistryImpl +MPU_vQueueAddToRegistryImpl: + b MPU_vQueueAddToRegistryImpl + + PUBWEAK MPU_vQueueUnregisterQueueImpl +MPU_vQueueUnregisterQueueImpl: + b MPU_vQueueUnregisterQueueImpl + + PUBWEAK MPU_pcQueueGetNameImpl +MPU_pcQueueGetNameImpl: + b MPU_pcQueueGetNameImpl + + PUBWEAK MPU_pvTimerGetTimerIDImpl +MPU_pvTimerGetTimerIDImpl: + b MPU_pvTimerGetTimerIDImpl + + PUBWEAK MPU_vTimerSetTimerIDImpl +MPU_vTimerSetTimerIDImpl: + b MPU_vTimerSetTimerIDImpl + + PUBWEAK MPU_xTimerIsTimerActiveImpl +MPU_xTimerIsTimerActiveImpl: + b MPU_xTimerIsTimerActiveImpl + + PUBWEAK MPU_xTimerGetTimerDaemonTaskHandleImpl +MPU_xTimerGetTimerDaemonTaskHandleImpl: + b MPU_xTimerGetTimerDaemonTaskHandleImpl + + PUBWEAK MPU_xTimerGenericCommandFromTaskImpl +MPU_xTimerGenericCommandFromTaskImpl: + b MPU_xTimerGenericCommandFromTaskImpl + + PUBWEAK MPU_pcTimerGetNameImpl +MPU_pcTimerGetNameImpl: + b MPU_pcTimerGetNameImpl + + PUBWEAK MPU_vTimerSetReloadModeImpl +MPU_vTimerSetReloadModeImpl: + b MPU_vTimerSetReloadModeImpl + + PUBWEAK MPU_xTimerGetReloadModeImpl +MPU_xTimerGetReloadModeImpl: + b MPU_xTimerGetReloadModeImpl + + PUBWEAK MPU_uxTimerGetReloadModeImpl +MPU_uxTimerGetReloadModeImpl: + b MPU_uxTimerGetReloadModeImpl + + PUBWEAK MPU_xTimerGetPeriodImpl +MPU_xTimerGetPeriodImpl: + b MPU_xTimerGetPeriodImpl + + PUBWEAK MPU_xTimerGetExpiryTimeImpl +MPU_xTimerGetExpiryTimeImpl: + b MPU_xTimerGetExpiryTimeImpl + + PUBWEAK MPU_xEventGroupWaitBitsImpl +MPU_xEventGroupWaitBitsImpl: + b MPU_xEventGroupWaitBitsImpl + + PUBWEAK MPU_xEventGroupClearBitsImpl +MPU_xEventGroupClearBitsImpl: + b MPU_xEventGroupClearBitsImpl + + PUBWEAK MPU_xEventGroupSetBitsImpl +MPU_xEventGroupSetBitsImpl: + b MPU_xEventGroupSetBitsImpl + + PUBWEAK MPU_xEventGroupSyncImpl +MPU_xEventGroupSyncImpl: + b MPU_xEventGroupSyncImpl + + PUBWEAK MPU_uxEventGroupGetNumberImpl +MPU_uxEventGroupGetNumberImpl: + b MPU_uxEventGroupGetNumberImpl + + PUBWEAK MPU_vEventGroupSetNumberImpl +MPU_vEventGroupSetNumberImpl: + b MPU_vEventGroupSetNumberImpl + + PUBWEAK MPU_xStreamBufferSendImpl +MPU_xStreamBufferSendImpl: + b MPU_xStreamBufferSendImpl + + PUBWEAK MPU_xStreamBufferReceiveImpl +MPU_xStreamBufferReceiveImpl: + b MPU_xStreamBufferReceiveImpl + + PUBWEAK MPU_xStreamBufferIsFullImpl +MPU_xStreamBufferIsFullImpl: + b MPU_xStreamBufferIsFullImpl + + PUBWEAK MPU_xStreamBufferIsEmptyImpl +MPU_xStreamBufferIsEmptyImpl: + b MPU_xStreamBufferIsEmptyImpl + + PUBWEAK MPU_xStreamBufferSpacesAvailableImpl +MPU_xStreamBufferSpacesAvailableImpl: + b MPU_xStreamBufferSpacesAvailableImpl + + PUBWEAK MPU_xStreamBufferBytesAvailableImpl +MPU_xStreamBufferBytesAvailableImpl: + b MPU_xStreamBufferBytesAvailableImpl + + PUBWEAK MPU_xStreamBufferSetTriggerLevelImpl +MPU_xStreamBufferSetTriggerLevelImpl: + b MPU_xStreamBufferSetTriggerLevelImpl + + PUBWEAK MPU_xStreamBufferNextMessageLengthBytesImpl +MPU_xStreamBufferNextMessageLengthBytesImpl: + b MPU_xStreamBufferNextMessageLengthBytesImpl + +/*-----------------------------------------------------------*/ + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + END diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c new file mode 100644 index 000000000..76d2b2445 --- /dev/null +++ b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c @@ -0,0 +1,2280 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024-2025 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU includes. */ +#include "mpu_wrappers.h" +#include "mpu_syscall_numbers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration settings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to check the validity of an interrupt priority. + */ +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) ) +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used during system call enter and exit. + */ +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Offsets in the stack to the parameters when inside the SVC handler. + */ +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +#if ( portARMV8M_MINOR_VERSION >= 1 ) + + /* Enable Privileged eXecute Never MPU attribute for the selected memory + * region. */ + #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL ) +#endif /* portARMV8M_MINOR_VERSION >= 1 */ + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Extract first address of the MPU region as encoded in the + * RBAR (Region Base Address Register) value. */ +#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \ + ( ( rbar ) & portMPU_RBAR_ADDRESS_MASK ) + +/* Extract last address of the MPU region as encoded in the + * RLAR (Region Limit Address Register) value. */ +#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \ + ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK ) + +/* Does addr lies within [start, end] address range? */ +#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \ + ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) ) + +/* Is the access request satisfied by the available permissions? */ +#define portIS_AUTHORIZED( accessRequest, permissions ) \ + ( ( ( permissions ) & ( accessRequest ) ) == accessRequest ) + +/* Max value that fits in a uint32_t type. */ +#define portUINT32_MAX ( ~( ( uint32_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. + */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 + +/** + * @brief Constants required to check and configure PACBTI security feature implementation. + */ +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) ) + + #define portCONTROL_UPAC_EN ( 1UL << 7UL ) + #define portCONTROL_PAC_EN ( 1UL << 6UL ) + #define portCONTROL_UBTI_EN ( 1UL << 5UL ) + #define portCONTROL_BTI_EN ( 1UL << 4UL ) + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Extract MPU region's access permissions from the Region Base Address + * Register (RBAR) value. + * + * @param ulRBARValue RBAR value for the MPU region. + * + * @return uint32_t Access permissions. + */ + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + + /** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + /** + * @brief Configures PACBTI features. + * + * This function configures the Pointer Authentication, and Branch Target + * Identification security features as per the user configuration. It returns + * the value of the special purpose CONTROL register accordingly, and optionally + * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M + * architecture based) target supports PACBTI security feature. + * + * @param xWriteControlRegister Used to control whether the special purpose + * CONTROL register should be updated or not. + * + * @return CONTROL register value according to the configured PACBTI option. + */ + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the system call stack so that upon returning from + * SVC, the system call stack is used. + * + * @param pulTaskStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + * @param ucSystemCallNumber The system call number of the system call. + */ + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Raise SVC for exiting from a system call. + */ + void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief This variable is set to pdTRUE when the scheduler is started. + */ + PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + + /** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +/** + * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + /** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + + /** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + + /** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the cpsid instruction + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessPermissions = 0; + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_ONLY ) + { + ulAccessPermissions = tskMPU_READ_PERMISSION; + } + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_WRITE ) + { + ulAccessPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION ); + } + + return ulAccessPermissions; + } + +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } + +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ portOFFSET_TO_PC ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ]; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulSystemCallStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the system call section (i.e. application is + * not raising SVC directly). + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as + * it is non-NULL only during the execution of a system call (i.e. + * between system call enter and exit). + * 3. System call is not for a kernel API disabled by the configuration + * in FreeRTOSConfig.h. + * 4. We do not need to check that ucSystemCallNumber is within range + * because the assembly SVC handler checks that before calling + * this function. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) && + ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) ) + { + pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the system call stack for the stack frame. */ + pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulSystemCallStack[ i ] = pulTaskStack[ i ]; + } + + /* Store the value of the Link Register before the SVC was raised. + * It contains the address of the caller of the System Call entry + * point (i.e. the caller of the MPU_). We need to restore it + * when we exit from the system call. */ + pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; + + /* Store the value of the PSPLIM register before the SVC was raised. + * We need to restore it when we exit from the system call. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* Use the pulSystemCallStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif + + /* Start executing the system call upon returning from this handler. */ + pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; + + /* Raise a request to exit from the system call upon finishing the + * system call. */ + pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; + + /* Remember the location where we should copy the stack frame when we exit from + * the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize; + + /* Record if the hardware used padding to force the stack pointer + * to be double word aligned. */ + if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK ) + { + pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG; + } + else + { + pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG ); + } + + /* We ensure in pxPortInitialiseStack that the system call stack is + * double word aligned and therefore, there is no need of padding. + * Clear the bit[9] of stacked xPSR. */ + pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + + /* Raise the privilege for the duration of the system call. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " bics r0, r1 \n" /* Clear nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */ + { + __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulTaskStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the privileged code (i.e. application is not + * raising SVC directly). This SVC is only raised from + * vRequestSystemCallExit which is in the privileged code section. + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL - + * this means that we previously entered a system call and the + * application is not attempting to exit without entering a system + * call. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) ) + { + pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the task stack for the stack frame. */ + pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulTaskStack[ i ] = pulSystemCallStack[ i ]; + } + + /* Use the pulTaskStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) ); + + /* Return to the caller of the System Call entry point (i.e. the + * caller of the MPU_). */ + pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + /* Ensure that LR has a valid value.*/ + pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + + /* Restore the PSPLIM register to what it was at the time of + * system call entry. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* If the hardware used padding to force the stack pointer + * to be double word aligned, set the stacked xPSR bit[9], + * otherwise clear it. */ + if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG ) + { + pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK; + } + else + { + pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + } + + /* This is not NULL only for the duration of the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; + + /* Drop the privilege before returning to the thread mode. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " orrs r0, r1 \n" /* Set nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xTaskIsPrivileged = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xTaskIsPrivileged = pdTRUE; + } + + return xTaskIsPrivileged; + } + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged, + xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulIndex = 0; + uint32_t ulControl = 0x0; + + xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ + ulIndex++; + + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + ulIndex++; + + #if ( configENABLE_TRUSTZONE == 1 ) + { + xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */ + ulIndex++; + } + #endif /* configENABLE_TRUSTZONE */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + ulIndex++; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Check PACBTI security feature configuration before pushing the + * CONTROL register's value on task's TCB. */ + ulControl = prvConfigurePACBTI( pdFALSE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + if( xRunPrivileged == pdTRUE ) + { + xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + else + { + xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG ); + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ + ulIndex++; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + { + /* Ensure that the system call stack is double word aligned. */ + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) + + ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + /* This is not NULL only for the duration of a system call. */ + xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL; + } + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ]; + ulIndex++; + } + } + #endif /* configENABLE_PAC */ + + return &( xMPUSettings->ulContext[ ulIndex ] ); + } + +#else /* configENABLE_MPU */ + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ + { + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + pxTopOfStack--; + *pxTopOfStack = ulTaskPacKey[ i ]; + } + } + #endif /* configENABLE_PAC */ + + return pxTopOfStack; + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Set the CONTROL register value based on PACBTI security feature + * configuration before starting the first task. */ + ( void ) prvConfigurePACBTI( pdTRUE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + { + xSchedulerRunning = pdTRUE; + } + #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + configSTACK_DEPTH_TYPE uxStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( uxStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* PXN. */ + #if ( portARMV8M_MINOR_VERSION >= 1 ) + { + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ); + } + } + #endif /* portARMV8M_MINOR_VERSION >= 1 */ + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, + uint32_t ulBufferLength, + uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */ + + { + uint32_t i, ulBufferStartAddress, ulBufferEndAddress; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE ) + { + ulBufferStartAddress = ( uint32_t ) pvBuffer; + ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL ); + + for( i = 0; i < portTOTAL_NUM_REGIONS; i++ ) + { + /* Is the MPU region enabled? */ + if( ( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR & portMPU_RLAR_REGION_ENABLE ) == portMPU_RLAR_REGION_ENABLE ) + { + if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_AUTHORIZED( ulAccessRequested, + prvGetRegionAccessPermissions( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ) ) ) + { + xAccessGranted = pdTRUE; + break; + } + } + } + } + } + + return xAccessGranted; + } + +#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings; + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else + { + xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 ) + { + xAccessGranted = pdTRUE; + } + } + } + + return xAccessGranted; + } + + #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + ( void ) lInternalIndexOfKernelObject; + + /* If Access Control List feature is not used, all the tasks have + * access to all the kernel objects. */ + return pdTRUE; + } + + #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + { + uint32_t ulControl = 0x0; + + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); + + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; + + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.h b/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.h new file mode 100644 index 000000000..b7021b024 --- /dev/null +++ b/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kernel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s b/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s new file mode 100644 index 000000000..ba6e8e915 --- /dev/null +++ b/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s @@ -0,0 +1,456 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" + +/* System call numbers includes. */ +#include "mpu_syscall_numbers.h" + +#ifndef configUSE_MPU_WRAPPERS_V1 + #define configUSE_MPU_WRAPPERS_V1 0 +#endif + + EXTERN pxCurrentTCB + EXTERN vTaskSwitchContext + EXTERN vPortSVCHandler_C +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + EXTERN vSystemCallEnter + EXTERN vSystemCallExit +#endif + + PUBLIC xIsPrivileged + PUBLIC vResetPrivilege + PUBLIC vRestoreContextOfFirstTask + PUBLIC vRaisePrivilege + PUBLIC vStartFirstTask + PUBLIC ulSetInterruptMask + PUBLIC vClearInterruptMask + PUBLIC PendSV_Handler + PUBLIC SVC_Handler +/*-----------------------------------------------------------*/ + +/*---------------- Unprivileged Functions -------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION .text:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +xIsPrivileged: + mrs r0, control /* r0 = CONTROL. */ + tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + ite ne + movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vResetPrivilege: + mrs r0, control /* r0 = CONTROL. */ + orr r0, r0, #1 /* r0 = r0 | 1. */ + msr control, r0 /* CONTROL = r0. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +/*----------------- Privileged Functions --------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION privileged_functions:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +vRestoreContextOfFirstTask: + program_mpu_first_task: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r2] /* r0 = pxCurrentTCB. */ + + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + str r2, [r1] /* Disable MPU. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r1, [r2] /* Program MAIR0. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + + movs r3, #4 /* r3 = 4. */ + str r3, [r1] /* Program RNR = 4. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + #if ( configTOTAL_MPU_REGIONS == 16 ) + movs r3, #8 /* r3 = 8. */ + str r3, [r1] /* Program RNR = 8. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + movs r3, #12 /* r3 = 12. */ + str r3, [r1] /* Program RNR = 12. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + orr r2, #1 /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */ + str r2, [r1] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + + restore_context_first_task: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r2] /* r0 = pxCurrentTCB.*/ + ldr r1, [r0] /* r1 = Location of saved context in TCB. */ + + restore_special_regs_first_task: + #if ( configENABLE_PAC == 1 ) + ldmdb r1!, {r2-r5} /* Read task's dedicated PAC key from the task's context. */ + msr PAC_KEY_P_0, r2 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_1, r3 + msr PAC_KEY_P_2, r4 + msr PAC_KEY_P_3, r5 + clrm {r2-r5} /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + ldmdb r1!, {r2-r4, lr} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */ + msr psp, r2 + msr psplim, r3 + msr control, r4 + + restore_general_regs_first_task: + ldmdb r1!, {r4-r11} /* r4-r11 contain hardware saved context. */ + stmia r2!, {r4-r11} /* Copy the hardware saved context on the task stack. */ + ldmdb r1!, {r4-r11} /* r4-r11 restored. */ + + restore_context_done_first_task: + str r1, [r0] /* Save the location where the context should be saved next as the first member of TCB. */ + mov r0, #0 + msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ + bx lr + +#else /* configENABLE_MPU */ + +vRestoreContextOfFirstTask: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + +#if ( configENABLE_PAC == 1 ) + ldmia r0!, {r1-r4} /* Read task's dedicated PAC key from stack. */ + msr PAC_KEY_P_3, r1 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_2, r2 + msr PAC_KEY_P_1, r3 + msr PAC_KEY_P_0, r4 + clrm {r1-r4} /* Clear r1-r4. */ +#endif /* configENABLE_PAC */ + + ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */ + msr psplim, r1 /* Set this task's PSPLIM value. */ + mrs r1, control /* Obtain current control register value. */ + orrs r1, r1, #2 /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */ + msr control, r1 /* Write back the new control register value. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + mov r0, #0 + msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ + bx r2 /* Finally, branch to EXC_RETURN. */ + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +vRaisePrivilege: + mrs r0, control /* Read the CONTROL register. */ + bic r0, r0, #1 /* Clear the bit 0. */ + msr control, r0 /* Write back the new CONTROL value. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vStartFirstTask: + ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */ + ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */ + ldr r0, [r0] /* The first entry in vector table is stack pointer. */ + msr msp, r0 /* Set the MSP back to the start of the stack. */ + cpsie i /* Globally enable interrupts. */ + cpsie f + dsb + isb + svc 102 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */ +/*-----------------------------------------------------------*/ + +ulSetInterruptMask: + mrs r0, basepri /* r0 = basepri. Return original basepri value. */ + mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r1 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vClearInterruptMask: + msr basepri, r0 /* basepri = ulMask. */ + dsb + isb + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +PendSV_Handler: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r2] /* r0 = pxCurrentTCB. */ + ldr r1, [r0] /* r1 = Location in TCB where the context should be saved. */ + mrs r2, psp /* r2 = PSP. */ + + save_general_regs: + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + add r2, r2, #0x20 /* Move r2 to location where s0 is saved. */ + tst lr, #0x10 + ittt eq + vstmiaeq r1!, {s16-s31} /* Store s16-s31. */ + vldmiaeq r2, {s0-s16} /* Copy hardware saved FP context into s0-s16. */ + vstmiaeq r1!, {s0-s16} /* Store hardware saved FP context. */ + sub r2, r2, #0x20 /* Set r2 back to the location of hardware saved context. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + stmia r1!, {r4-r11} /* Store r4-r11. */ + ldmia r2, {r4-r11} /* Copy the hardware saved context into r4-r11. */ + stmia r1!, {r4-r11} /* Store the hardware saved context. */ + + save_special_regs: + mrs r3, psplim /* r3 = PSPLIM. */ + mrs r4, control /* r4 = CONTROL. */ + stmia r1!, {r2-r4, lr} /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ + #if ( configENABLE_PAC == 1 ) + mrs r2, PAC_KEY_P_0 /* Read task's dedicated PAC key from the PAC key registers. */ + mrs r3, PAC_KEY_P_1 + mrs r4, PAC_KEY_P_2 + mrs r5, PAC_KEY_P_3 + stmia r1!, {r2-r5} /* Store the task's dedicated PAC key on the task's context. */ + clrm {r2-r5} /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + + str r1, [r0] /* Save the location from where the context should be restored as the first member of TCB. */ + + select_next_task: + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bl vTaskSwitchContext + mov r0, #0 /* r0 = 0. */ + msr basepri, r0 /* Enable interrupts. */ + + program_mpu: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r2] /* r0 = pxCurrentTCB. */ + + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + str r2, [r1] /* Disable MPU. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r1, [r2] /* Program MAIR0. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + + movs r3, #4 /* r3 = 4. */ + str r3, [r1] /* Program RNR = 4. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + #if ( configTOTAL_MPU_REGIONS == 16 ) + movs r3, #8 /* r3 = 8. */ + str r3, [r1] /* Program RNR = 8. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + movs r3, #12 /* r3 = 12. */ + str r3, [r1] /* Program RNR = 12. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + orr r2, #1 /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */ + str r2, [r1] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + + restore_context: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r2] /* r0 = pxCurrentTCB.*/ + ldr r1, [r0] /* r1 = Location of saved context in TCB. */ + + restore_special_regs: + #if ( configENABLE_PAC == 1 ) + ldmdb r1!, {r2-r5} /* Read task's dedicated PAC key from the task's context. */ + msr PAC_KEY_P_0, r2 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_1, r3 + msr PAC_KEY_P_2, r4 + msr PAC_KEY_P_3, r5 + clrm {r2-r5} /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + ldmdb r1!, {r2-r4, lr} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */ + msr psp, r2 + msr psplim, r3 + msr control, r4 + + restore_general_regs: + ldmdb r1!, {r4-r11} /* r4-r11 contain hardware saved context. */ + stmia r2!, {r4-r11} /* Copy the hardware saved context on the task stack. */ + ldmdb r1!, {r4-r11} /* r4-r11 restored. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 + ittt eq + vldmdbeq r1!, {s0-s16} /* s0-s16 contain hardware saved FP context. */ + vstmiaeq r2!, {s0-s16} /* Copy hardware saved FP context on the task stack. */ + vldmdbeq r1!, {s16-s31} /* Restore s16-s31. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + + restore_context_done: + str r1, [r0] /* Save the location where the context should be saved next as the first member of TCB. */ + bx lr + +#else /* configENABLE_MPU */ + +PendSV_Handler: + mrs r0, psp /* Read PSP in r0. */ +#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + it eq + vstmdbeq r0!, {s16-s31} /* Store the additional FP context registers which are not saved automatically. */ +#endif /* configENABLE_FPU || configENABLE_MVE */ + + mrs r2, psplim /* r2 = PSPLIM. */ + mov r3, lr /* r3 = LR/EXC_RETURN. */ + stmdb r0!, {r2-r11} /* Store on the stack - PSPLIM, LR and registers that are not automatically. */ + +#if ( configENABLE_PAC == 1 ) + mrs r1, PAC_KEY_P_3 /* Read task's dedicated PAC key from the PAC key registers. */ + mrs r2, PAC_KEY_P_2 + mrs r3, PAC_KEY_P_1 + mrs r4, PAC_KEY_P_0 + stmdb r0!, {r1-r4} /* Store the task's dedicated PAC key on the stack. */ + clrm {r1-r4} /* Clear r1-r4. */ +#endif /* configENABLE_PAC */ + + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + str r0, [r1] /* Save the new top of stack in TCB. */ + + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bl vTaskSwitchContext + mov r0, #0 /* r0 = 0. */ + msr basepri, r0 /* Enable interrupts. */ + + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ + +#if ( configENABLE_PAC == 1 ) + ldmia r0!, {r2-r5} /* Read task's dedicated PAC key from stack. */ + msr PAC_KEY_P_3, r2 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_2, r3 + msr PAC_KEY_P_1, r4 + msr PAC_KEY_P_0, r5 + clrm {r2-r5} /* Clear r2-r5. */ +#endif /* configENABLE_PAC */ + + ldmia r0!, {r2-r11} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */ + +#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst r3, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + it eq + vldmiaeq r0!, {s16-s31} /* Restore the additional FP context registers which are not restored automatically. */ +#endif /* configENABLE_FPU || configENABLE_MVE */ + + msr psplim, r2 /* Restore the PSPLIM register value for the task. */ + msr psp, r0 /* Remember the new top of stack for the task. */ + bx r3 + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + +SVC_Handler: + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + + ldr r1, [r0, #24] + ldrb r2, [r1, #-2] + cmp r2, #NUM_SYSTEM_CALLS + blt syscall_enter + cmp r2, #104 /* portSVC_SYSTEM_CALL_EXIT. */ + beq syscall_exit + b vPortSVCHandler_C + + syscall_enter: + mov r1, lr + b vSystemCallEnter + + syscall_exit: + mov r1, lr + b vSystemCallExit + +#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +SVC_Handler: + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + b vPortSVCHandler_C + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + + END diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h new file mode 100644 index 000000000..ff5c9895d --- /dev/null +++ b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h @@ -0,0 +1,86 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_MVE + #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE. +#endif /* configENABLE_MVE */ +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M85" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portARMV8M_MINOR_VERSION 1 +#define portDONT_DISCARD __root +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ +#pragma diag_suppress=Be006 +#pragma diag_suppress=Pa082 +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h new file mode 100644 index 000000000..f373bcad5 --- /dev/null +++ b/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h @@ -0,0 +1,582 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACROCOMMON_H +#define PORTMACROCOMMON_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. +#endif /* configENABLE_FPU */ + +#ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. +#endif /* configENABLE_MPU */ + +#ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. +#endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() +#define portINLINE __inline +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif +#define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ +extern BaseType_t xPortIsInsideInterrupt( void ); + +extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + +extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; +extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + +extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; +extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + +#if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_PAC == 1 ) + + /** + * @brief Generates 128-bit task's random PAC key. + * + * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be + * filled with a 128-bit random number. + */ + void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); + +#endif /* configENABLE_PAC */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ +#if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) +#else + #define portPRIVILEGE_BIT ( 0x0UL ) +#endif /* configENABLE_MPU */ + +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ +#define portPRIVILEGED_FLASH_REGION ( 0UL ) +#define portUNPRIVILEGED_FLASH_REGION ( 1UL ) +#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) +#define portPRIVILEGED_RAM_REGION ( 3UL ) +#define portSTACK_REGION ( 4UL ) +#define portFIRST_CONFIGURABLE_REGION ( 5UL ) +#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) +#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) +#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ +#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ +#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ +#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ +#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ +#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ +#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ +#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) +#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) +#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + +#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) +#define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) +#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) +#define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + +#define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + #ifndef configSYSTEM_CALL_STACK_SIZE + #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. + #endif + + /** + * @brief System call stack. + */ + typedef struct SYSTEM_CALL_STACK_INFO + { + uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; + uint32_t * pulSystemCallStack; + uint32_t * pulSystemCallStackLimit; + uint32_t * pulTaskStack; + uint32_t ulLinkRegisterAtSystemCallEntry; + uint32_t ulStackLimitRegisterAtSystemCallEntry; + } xSYSTEM_CALL_STACK_INFO; + + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + /** + * @brief MPU settings as stored in the TCB. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><-----------><----> + * 16 17 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 71 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 17 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 55 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | | | PC, xPSR | EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><-----------><----> + * 16 17 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 70 + + #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + /* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 17 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 54 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+------------------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +----------+-----------------+------------------------------+------------+-----+ + * + * <---------><----------------><------------------------------><-----------><----> + * 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 38 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+----------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | PC, xPSR | EXC_RETURN | | | + * +----------+-----------------+----------------------+------------+-----+ + * + * <---------><----------------><----------------------><-----------><----> + * 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 37 + + #else /* #if( configENABLE_TRUSTZONE == 1 ) */ + + /* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) + + /* Size of an Access Control List (ACL) entry in bits. */ + #define portACL_ENTRY_SIZE_BITS ( 32U ) + + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + uint32_t ulContext[ MAX_CONTEXT_SIZE ]; + uint32_t ulTaskFlags; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo; + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ]; + #endif + #endif + } xMPU_SETTINGS; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Validate priority of ISRs that are allowed to call FreeRTOS + * system calls. + */ +#if ( configASSERT_DEFINED == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif +#endif + +/** + * @brief SVC numbers. + */ +#define portSVC_ALLOCATE_SECURE_CONTEXT 100 +#define portSVC_FREE_SECURE_CONTEXT 101 +#define portSVC_START_SCHEDULER 102 +#define portSVC_RAISE_PRIVILEGE 103 +#define portSVC_SYSTEM_CALL_EXIT 104 +#define portSVC_YIELD 105 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) +#endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() +#else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + extern BaseType_t xPortIsTaskPrivileged( void ); + +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACROCOMMON_H */ diff --git a/portable/IAR/ARM_CRx_No_GIC/port.c b/portable/IAR/ARM_CRx_No_GIC/port.c new file mode 100644 index 000000000..1b5c0fb8e --- /dev/null +++ b/portable/IAR/ARM_CRx_No_GIC/port.c @@ -0,0 +1,321 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + /* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +#ifndef configSETUP_TICK_INTERRUPT + #error configSETUP_TICK_INTERRUPT() must be defined in FreeRTOSConfig.h to call the function that sets up the tick interrupt. +#endif + +#ifndef configCLEAR_TICK_INTERRUPT + #error configCLEAR_TICK_INTERRUPT must be defined in FreeRTOSConfig.h to clear which ever interrupt was used to generate the tick interrupt. +#endif + +/* A critical section is exited when the critical section nesting count reaches + * this value. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + +/* Tasks are not created with a floating point context, but can be given a + * floating point context after they have been created. A variable is stored as + * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task + * does not have an FPU context, or any other value if the task does have an FPU + * context. */ +#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) + +/* Constants required to setup the initial task context. */ +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portTHUMB_MODE_ADDRESS ( 0x01UL ) + +/* Masks all bits in the APSR other than the mode bits. */ +#define portAPSR_MODE_BITS_MASK ( 0x1F ) + +/* The value of the mode bits in the APSR when the CPU is executing in user + * mode. */ +#define portAPSR_USER_MODE ( 0x10 ) + +/* Let the user override the pre-loading of the initial LR with the address of + * prvTaskExitError() in case it messes up unwinding of the stack in the + * debugger. */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/*-----------------------------------------------------------*/ + +/* + * Starts the first task executing. This function is necessarily written in + * assembly code so is implemented in portASM.s. + */ +extern void vPortRestoreTaskContext( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* A variable is used to keep track of the critical section nesting. This + * variable has to be stored as part of the task context and must be initialised to + * a non zero value to ensure interrupts don't inadvertently become unmasked before + * the scheduler starts. As it is stored as part of the task context it will + * automatically be set to 0 when the first task is started. */ +volatile uint32_t ulCriticalNesting = 9999UL; + +/* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then + * a floating point context must be saved and restored for the task. */ +volatile uint32_t ulPortTaskHasFPUContext = pdFALSE; + +/* Set to 1 to pend a context switch from an ISR. */ +volatile uint32_t ulPortYieldRequired = pdFALSE; + +/* Counts the interrupt nesting depth. A context switch is only performed if + * if the nesting depth is 0. */ +volatile uint32_t ulPortInterruptNesting = 0UL; + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Setup the initial stack of the task. The stack is set exactly as + * expected by the portRESTORE_CONTEXT() macro. + * + * The fist real value on the stack is the status register, which is set for + * system mode, with interrupts enabled. A few NULLs are added first to ensure + * GDB does not try decoding a non-existent return address. */ + *pxTopOfStack = ( StackType_t ) NULL; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) NULL; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) NULL; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + + if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL ) + { + /* The task will start in THUMB mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + + pxTopOfStack--; + + /* Next the return address, which in this case is the start of the task. */ + *pxTopOfStack = ( StackType_t ) pxCode; + pxTopOfStack--; + + /* Next all the registers other than the stack pointer. */ + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The task will start with a critical nesting count of 0 as interrupts are + * enabled. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + pxTopOfStack--; + + /* The task will start without a floating point context. A task that uses + * the floating point hardware must call vPortTaskUsesFPU() before executing + * any floating point instructions. */ + *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ + configASSERT( ulPortInterruptNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + uint32_t ulAPSR; + + /* Only continue if the CPU is not in User mode. The CPU must be in a + * Privileged mode for the scheduler to start. */ + __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) ); + + ulAPSR &= portAPSR_MODE_BITS_MASK; + configASSERT( ulAPSR != portAPSR_USER_MODE ); + + if( ulAPSR != portAPSR_USER_MODE ) + { + /* Start the timer that generates the tick ISR. */ + portDISABLE_INTERRUPTS(); + configSETUP_TICK_INTERRUPT(); + + /* Start the first task executing. */ + vPortRestoreTaskContext(); + } + + /* Will only get here if vTaskStartScheduler() was called with the CPU in + * a non-privileged mode or the binary point register was not set to its lowest + * possible value. prvTaskExitError() is referenced to prevent a compiler + * warning about it being defined but not referenced in the case that the user + * defines their own exit address. */ + ( void ) prvTaskExitError; + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + + /* Now that interrupts are disabled, ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ + if( ulCriticalNesting == 1 ) + { + configASSERT( ulPortInterruptNesting == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as the critical section is being + * exited. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then all interrupt + * priorities must be re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Critical nesting has reached zero so all interrupt priorities + * should be unmasked. */ + portENABLE_INTERRUPTS(); + } + } +} +/*-----------------------------------------------------------*/ + +void FreeRTOS_Tick_Handler( void ) +{ + uint32_t ulInterruptStatus; + + ulInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + ulPortYieldRequired = pdTRUE; + } + + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulInterruptStatus ); + + configCLEAR_TICK_INTERRUPT(); +} +/*-----------------------------------------------------------*/ + +void vPortTaskUsesFPU( void ) +{ + uint32_t ulInitialFPSCR = 0; + + /* A task is registering the fact that it needs an FPU context. Set the + * FPU flag (which is saved as part of the task context). */ + ulPortTaskHasFPUContext = pdTRUE; + + /* Initialise the floating point status register. */ + __asm volatile ( "FMXR FPSCR, %0" ::"r" ( ulInitialFPSCR ) ); +} +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/ARM_CRx_No_GIC/portASM.s b/portable/IAR/ARM_CRx_No_GIC/portASM.s new file mode 100644 index 000000000..f37ad570b --- /dev/null +++ b/portable/IAR/ARM_CRx_No_GIC/portASM.s @@ -0,0 +1,243 @@ +;/* +; * FreeRTOS Kernel +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + +#include "FreeRTOSConfig.h" + + SECTION .text:CODE:ROOT(2) + arm + + /* Variables and functions. */ + EXTERN pxCurrentTCB + EXTERN vTaskSwitchContext + EXTERN vApplicationIRQHandler + EXTERN ulPortInterruptNesting + EXTERN ulPortTaskHasFPUContext + EXTERN ulPortYieldRequired + EXTERN ulCriticalNesting + + PUBLIC FreeRTOS_IRQ_Handler + PUBLIC FreeRTOS_SVC_Handler + PUBLIC vPortRestoreTaskContext + +SYS_MODE EQU 0x1f +SVC_MODE EQU 0x13 +IRQ_MODE EQU 0x12 + +portSAVE_CONTEXT MACRO + + /* Save the LR and SPSR onto the system mode stack before switching to + system mode to save the remaining system mode registers. */ + SRSDB sp!, #SYS_MODE + CPS #SYS_MODE + PUSH {R0-R12, R14} + + /* Push the critical nesting count. */ + LDR R2, =ulCriticalNesting + LDR R1, [R2] + PUSH {R1} + + /* Does the task have a floating point context that needs saving? If + ulPortTaskHasFPUContext is 0 then no. */ + LDR R2, =ulPortTaskHasFPUContext + LDR R3, [R2] + CMP R3, #0 + + /* Save the floating point context, if any. */ + FMRXNE R1, FPSCR + VPUSHNE {D0-D15} +#if configFPU_D32 == 1 + VPUSHNE {D16-D31} +#endif /* configFPU_D32 */ + PUSHNE {R1} + + /* Save ulPortTaskHasFPUContext itself. */ + PUSH {R3} + + /* Save the stack pointer in the TCB. */ + LDR R0, =pxCurrentTCB + LDR R1, [R0] + STR SP, [R1] + + ENDM + +; /**********************************************************************/ + +portRESTORE_CONTEXT MACRO + + /* Set the SP to point to the stack of the task being restored. */ + LDR R0, =pxCurrentTCB + LDR R1, [R0] + LDR SP, [R1] + + /* Is there a floating point context to restore? If the restored + ulPortTaskHasFPUContext is zero then no. */ + LDR R0, =ulPortTaskHasFPUContext + POP {R1} + STR R1, [R0] + CMP R1, #0 + + /* Restore the floating point context, if any. */ + POPNE {R0} +#if configFPU_D32 == 1 + VPOPNE {D16-D31} +#endif /* configFPU_D32 */ + VPOPNE {D0-D15} + VMSRNE FPSCR, R0 + + /* Restore the critical section nesting depth. */ + LDR R0, =ulCriticalNesting + POP {R1} + STR R1, [R0] + + /* Restore all system mode registers other than the SP (which is already + being used). */ + POP {R0-R12, R14} + + /* Return to the task code, loading CPSR on the way. */ + RFEIA sp! + + ENDM + + + + +/****************************************************************************** + * SVC handler is used to yield. + *****************************************************************************/ +FreeRTOS_SVC_Handler: + /* Save the context of the current task and select a new task to run. */ + portSAVE_CONTEXT + LDR R0, =vTaskSwitchContext + BLX R0 + portRESTORE_CONTEXT + + +/****************************************************************************** + * vPortRestoreTaskContext is used to start the scheduler. + *****************************************************************************/ +vPortRestoreTaskContext: + /* Switch to system mode. */ + CPS #SYS_MODE + portRESTORE_CONTEXT + +FreeRTOS_IRQ_Handler: + /* Return to the interrupted instruction. */ + SUB lr, lr, #4 + + /* Push the return address and SPSR. */ + PUSH {lr} + MRS lr, SPSR + PUSH {lr} + + /* Change to supervisor mode to allow reentry. */ + CPS #SVC_MODE + + /* Push used registers. */ + PUSH {r0-r3, r12} + + /* Increment nesting count. r3 holds the address of ulPortInterruptNesting + for future use. r1 holds the original ulPortInterruptNesting value for + future use. */ + LDR r3, =ulPortInterruptNesting + LDR r1, [r3] + ADD r0, r1, #1 + STR r0, [r3] + + /* Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for + future use. */ + MOV r0, sp + AND r2, r0, #4 + SUB sp, sp, r2 + + /* Call the interrupt handler. */ + PUSH {r0-r3, lr} + LDR r1, =vApplicationIRQHandler + BLX r1 + POP {r0-r3, lr} + ADD sp, sp, r2 + + CPSID i + DSB + ISB + + /* Write to the EOI register. */ + LDR r2, =configEOI_ADDRESS + STR r0, [r2] + + /* Restore the old nesting count. */ + STR r1, [r3] + + /* A context switch is never performed if the nesting count is not 0. */ + CMP r1, #0 + BNE exit_without_switch + + /* Did the interrupt request a context switch? r1 holds the address of + ulPortYieldRequired and r0 the value of ulPortYieldRequired for future + use. */ + LDR r1, =ulPortYieldRequired + LDR r0, [r1] + CMP r0, #0 + BNE switch_before_exit + +exit_without_switch: + /* No context switch. Restore used registers, LR_irq and SPSR before + returning. */ + POP {r0-r3, r12} + CPS #IRQ_MODE + POP {LR} + MSR SPSR_cxsf, LR + POP {LR} + MOVS PC, LR + +switch_before_exit: + /* A context switch is to be performed. Clear the context switch pending + flag. */ + MOV r0, #0 + STR r0, [r1] + + /* Restore used registers, LR-irq and SPSR before saving the context + to the task stack. */ + POP {r0-r3, r12} + CPS #IRQ_MODE + POP {LR} + MSR SPSR_cxsf, LR + POP {LR} + portSAVE_CONTEXT + + /* Call the function that selects the new task to execute. + vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD + instructions, or 8 byte aligned stack allocated data. LR does not need + saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */ + LDR R0, =vTaskSwitchContext + BLX R0 + + /* Restore the context of, and branch to, the task selected to execute + next. */ + portRESTORE_CONTEXT + + END diff --git a/portable/IAR/ARM_CRx_No_GIC/portmacro.h b/portable/IAR/ARM_CRx_No_GIC/portmacro.h new file mode 100644 index 000000000..7707fcf02 --- /dev/null +++ b/portable/IAR/ARM_CRx_No_GIC/portmacro.h @@ -0,0 +1,187 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#include + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +typedef uint32_t TickType_t; +#define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ +#define portTICK_TYPE_IS_ATOMIC 1 + +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* Called at the end of an ISR that can cause a context switch. */ +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + { \ + extern volatile uint32_t ulPortYieldRequired; \ + \ + if( xSwitchRequired != pdFALSE ) \ + { \ + ulPortYieldRequired = pdTRUE; \ + } \ + } + +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#define portYIELD() \ + __asm volatile ( "SWI 0 \n" \ + "ISB " ); + + +/*----------------------------------------------------------- +* Critical section control +*----------------------------------------------------------*/ + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +extern uint32_t ulPortSetInterruptMask( void ); +extern void vPortClearInterruptMask( uint32_t ulNewMaskValue ); +extern void vPortInstallFreeRTOSVectorTable( void ); + +/* The I bit within the CPSR. */ +#define portINTERRUPT_ENABLE_BIT ( 1 << 7 ) + +/* In the absence of a priority mask register, these functions and macros + * globally enable and disable interrupts. */ +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); +#define portENABLE_INTERRUPTS() __asm volatile ( "CPSIE i \n" ); +#define portDISABLE_INTERRUPTS() \ + __asm volatile ( "CPSID i \n" \ + "DSB \n" \ + "ISB " ); +#pragma inline +static inline uint32_t portINLINE_SET_INTERRUPT_MASK_FROM_ISR( void ) +{ + volatile uint32_t ulCPSR; + + __asm volatile ( "MRS %0, CPSR" : "=r" ( ulCPSR ) ); + + ulCPSR &= portINTERRUPT_ENABLE_BIT; + portDISABLE_INTERRUPTS(); + return ulCPSR; +} + +#define portSET_INTERRUPT_MASK_FROM_ISR() portINLINE_SET_INTERRUPT_MASK_FROM_ISR() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) do { if( x == 0 ) portENABLE_INTERRUPTS( ); } while( 0 ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not required for this port but included in case common demo code that uses these + * macros is used. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* Prototype of the FreeRTOS tick handler. This must be installed as the + * handler for whichever peripheral is used to generate the RTOS tick. */ +void FreeRTOS_Tick_Handler( void ); + +/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU() + * before any floating point instructions are executed. */ +void vPortTaskUsesFPU( void ); +#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() + +#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL ) +#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL ) + +/* Architecture specific optimisations. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __CLZ( uxReadyPriorities ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +#define portNOP() __asm volatile ( "NOP" ) +#define portINLINE inline + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ +#pragma diag_suppress=Pe191 +#pragma diag_suppress=Pa082 + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/IAR/ARM_STAR_MC3/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_STAR_MC3/non_secure/mpu_wrappers_v2_asm.S new file mode 100644 index 000000000..d2cb78e92 --- /dev/null +++ b/portable/IAR/ARM_STAR_MC3/non_secure/mpu_wrappers_v2_asm.S @@ -0,0 +1,1242 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + + SECTION freertos_system_calls:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +#include "FreeRTOSConfig.h" +#include "mpu_syscall_numbers.h" + +#ifndef configUSE_MPU_WRAPPERS_V1 + #define configUSE_MPU_WRAPPERS_V1 0 +#endif + +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + PUBLIC MPU_xTaskDelayUntil +MPU_xTaskDelayUntil: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskDelayUntil_Unpriv + MPU_xTaskDelayUntil_Priv: + b MPU_xTaskDelayUntilImpl + MPU_xTaskDelayUntil_Unpriv: + svc #SYSTEM_CALL_xTaskDelayUntil +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskAbortDelay +MPU_xTaskAbortDelay: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskAbortDelay_Unpriv + MPU_xTaskAbortDelay_Priv: + b MPU_xTaskAbortDelayImpl + MPU_xTaskAbortDelay_Unpriv: + svc #SYSTEM_CALL_xTaskAbortDelay +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskDelay +MPU_vTaskDelay: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskDelay_Unpriv + MPU_vTaskDelay_Priv: + b MPU_vTaskDelayImpl + MPU_vTaskDelay_Unpriv: + svc #SYSTEM_CALL_vTaskDelay +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskPriorityGet +MPU_uxTaskPriorityGet: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskPriorityGet_Unpriv + MPU_uxTaskPriorityGet_Priv: + b MPU_uxTaskPriorityGetImpl + MPU_uxTaskPriorityGet_Unpriv: + svc #SYSTEM_CALL_uxTaskPriorityGet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_eTaskGetState +MPU_eTaskGetState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_eTaskGetState_Unpriv + MPU_eTaskGetState_Priv: + b MPU_eTaskGetStateImpl + MPU_eTaskGetState_Unpriv: + svc #SYSTEM_CALL_eTaskGetState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskGetInfo +MPU_vTaskGetInfo: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskGetInfo_Unpriv + MPU_vTaskGetInfo_Priv: + b MPU_vTaskGetInfoImpl + MPU_vTaskGetInfo_Unpriv: + svc #SYSTEM_CALL_vTaskGetInfo +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetIdleTaskHandle +MPU_xTaskGetIdleTaskHandle: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetIdleTaskHandle_Unpriv + MPU_xTaskGetIdleTaskHandle_Priv: + b MPU_xTaskGetIdleTaskHandleImpl + MPU_xTaskGetIdleTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTaskGetIdleTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSuspend +MPU_vTaskSuspend: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSuspend_Unpriv + MPU_vTaskSuspend_Priv: + b MPU_vTaskSuspendImpl + MPU_vTaskSuspend_Unpriv: + svc #SYSTEM_CALL_vTaskSuspend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskResume +MPU_vTaskResume: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskResume_Unpriv + MPU_vTaskResume_Priv: + b MPU_vTaskResumeImpl + MPU_vTaskResume_Unpriv: + svc #SYSTEM_CALL_vTaskResume +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetTickCount +MPU_xTaskGetTickCount: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetTickCount_Unpriv + MPU_xTaskGetTickCount_Priv: + b MPU_xTaskGetTickCountImpl + MPU_xTaskGetTickCount_Unpriv: + svc #SYSTEM_CALL_xTaskGetTickCount +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetNumberOfTasks +MPU_uxTaskGetNumberOfTasks: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetNumberOfTasks_Unpriv + MPU_uxTaskGetNumberOfTasks_Priv: + b MPU_uxTaskGetNumberOfTasksImpl + MPU_uxTaskGetNumberOfTasks_Unpriv: + svc #SYSTEM_CALL_uxTaskGetNumberOfTasks +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetRunTimeCounter +MPU_ulTaskGetRunTimeCounter: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetRunTimeCounter_Unpriv + MPU_ulTaskGetRunTimeCounter_Priv: + b MPU_ulTaskGetRunTimeCounterImpl + MPU_ulTaskGetRunTimeCounter_Unpriv: + svc #SYSTEM_CALL_ulTaskGetRunTimeCounter +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetRunTimePercent +MPU_ulTaskGetRunTimePercent: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetRunTimePercent_Unpriv + MPU_ulTaskGetRunTimePercent_Priv: + b MPU_ulTaskGetRunTimePercentImpl + MPU_ulTaskGetRunTimePercent_Unpriv: + svc #SYSTEM_CALL_ulTaskGetRunTimePercent +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetIdleRunTimePercent +MPU_ulTaskGetIdleRunTimePercent: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetIdleRunTimePercent_Unpriv + MPU_ulTaskGetIdleRunTimePercent_Priv: + b MPU_ulTaskGetIdleRunTimePercentImpl + MPU_ulTaskGetIdleRunTimePercent_Unpriv: + svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetIdleRunTimeCounter +MPU_ulTaskGetIdleRunTimeCounter: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv + MPU_ulTaskGetIdleRunTimeCounter_Priv: + b MPU_ulTaskGetIdleRunTimeCounterImpl + MPU_ulTaskGetIdleRunTimeCounter_Unpriv: + svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetApplicationTaskTag +MPU_vTaskSetApplicationTaskTag: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetApplicationTaskTag_Unpriv + MPU_vTaskSetApplicationTaskTag_Priv: + b MPU_vTaskSetApplicationTaskTagImpl + MPU_vTaskSetApplicationTaskTag_Unpriv: + svc #SYSTEM_CALL_vTaskSetApplicationTaskTag +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetApplicationTaskTag +MPU_xTaskGetApplicationTaskTag: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetApplicationTaskTag_Unpriv + MPU_xTaskGetApplicationTaskTag_Priv: + b MPU_xTaskGetApplicationTaskTagImpl + MPU_xTaskGetApplicationTaskTag_Unpriv: + svc #SYSTEM_CALL_xTaskGetApplicationTaskTag +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetThreadLocalStoragePointer +MPU_vTaskSetThreadLocalStoragePointer: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv + MPU_vTaskSetThreadLocalStoragePointer_Priv: + b MPU_vTaskSetThreadLocalStoragePointerImpl + MPU_vTaskSetThreadLocalStoragePointer_Unpriv: + svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pvTaskGetThreadLocalStoragePointer +MPU_pvTaskGetThreadLocalStoragePointer: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv + MPU_pvTaskGetThreadLocalStoragePointer_Priv: + b MPU_pvTaskGetThreadLocalStoragePointerImpl + MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: + svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetSystemState +MPU_uxTaskGetSystemState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetSystemState_Unpriv + MPU_uxTaskGetSystemState_Priv: + b MPU_uxTaskGetSystemStateImpl + MPU_uxTaskGetSystemState_Unpriv: + svc #SYSTEM_CALL_uxTaskGetSystemState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetStackHighWaterMark +MPU_uxTaskGetStackHighWaterMark: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetStackHighWaterMark_Unpriv + MPU_uxTaskGetStackHighWaterMark_Priv: + b MPU_uxTaskGetStackHighWaterMarkImpl + MPU_uxTaskGetStackHighWaterMark_Unpriv: + svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetStackHighWaterMark2 +MPU_uxTaskGetStackHighWaterMark2: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetStackHighWaterMark2_Unpriv + MPU_uxTaskGetStackHighWaterMark2_Priv: + b MPU_uxTaskGetStackHighWaterMark2Impl + MPU_uxTaskGetStackHighWaterMark2_Unpriv: + svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2 +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetCurrentTaskHandle +MPU_xTaskGetCurrentTaskHandle: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetCurrentTaskHandle_Unpriv + MPU_xTaskGetCurrentTaskHandle_Priv: + b MPU_xTaskGetCurrentTaskHandleImpl + MPU_xTaskGetCurrentTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetSchedulerState +MPU_xTaskGetSchedulerState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetSchedulerState_Unpriv + MPU_xTaskGetSchedulerState_Priv: + b MPU_xTaskGetSchedulerStateImpl + MPU_xTaskGetSchedulerState_Unpriv: + svc #SYSTEM_CALL_xTaskGetSchedulerState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetTimeOutState +MPU_vTaskSetTimeOutState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetTimeOutState_Unpriv + MPU_vTaskSetTimeOutState_Priv: + b MPU_vTaskSetTimeOutStateImpl + MPU_vTaskSetTimeOutState_Unpriv: + svc #SYSTEM_CALL_vTaskSetTimeOutState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskCheckForTimeOut +MPU_xTaskCheckForTimeOut: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskCheckForTimeOut_Unpriv + MPU_xTaskCheckForTimeOut_Priv: + b MPU_xTaskCheckForTimeOutImpl + MPU_xTaskCheckForTimeOut_Unpriv: + svc #SYSTEM_CALL_xTaskCheckForTimeOut +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyEntry +MPU_xTaskGenericNotifyEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotify_Unpriv + MPU_xTaskGenericNotify_Priv: + b MPU_xTaskGenericNotifyImpl + MPU_xTaskGenericNotify_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotify +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyWaitEntry +MPU_xTaskGenericNotifyWaitEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotifyWait_Unpriv + MPU_xTaskGenericNotifyWait_Priv: + b MPU_xTaskGenericNotifyWaitImpl + MPU_xTaskGenericNotifyWait_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotifyWait +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGenericNotifyTake +MPU_ulTaskGenericNotifyTake: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGenericNotifyTake_Unpriv + MPU_ulTaskGenericNotifyTake_Priv: + b MPU_ulTaskGenericNotifyTakeImpl + MPU_ulTaskGenericNotifyTake_Unpriv: + svc #SYSTEM_CALL_ulTaskGenericNotifyTake +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyStateClear +MPU_xTaskGenericNotifyStateClear: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotifyStateClear_Unpriv + MPU_xTaskGenericNotifyStateClear_Priv: + b MPU_xTaskGenericNotifyStateClearImpl + MPU_xTaskGenericNotifyStateClear_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotifyStateClear +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGenericNotifyValueClear +MPU_ulTaskGenericNotifyValueClear: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGenericNotifyValueClear_Unpriv + MPU_ulTaskGenericNotifyValueClear_Priv: + b MPU_ulTaskGenericNotifyValueClearImpl + MPU_ulTaskGenericNotifyValueClear_Unpriv: + svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGenericSend +MPU_xQueueGenericSend: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGenericSend_Unpriv + MPU_xQueueGenericSend_Priv: + b MPU_xQueueGenericSendImpl + MPU_xQueueGenericSend_Unpriv: + svc #SYSTEM_CALL_xQueueGenericSend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxQueueMessagesWaiting +MPU_uxQueueMessagesWaiting: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxQueueMessagesWaiting_Unpriv + MPU_uxQueueMessagesWaiting_Priv: + b MPU_uxQueueMessagesWaitingImpl + MPU_uxQueueMessagesWaiting_Unpriv: + svc #SYSTEM_CALL_uxQueueMessagesWaiting +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxQueueSpacesAvailable +MPU_uxQueueSpacesAvailable: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxQueueSpacesAvailable_Unpriv + MPU_uxQueueSpacesAvailable_Priv: + b MPU_uxQueueSpacesAvailableImpl + MPU_uxQueueSpacesAvailable_Unpriv: + svc #SYSTEM_CALL_uxQueueSpacesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueReceive +MPU_xQueueReceive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueReceive_Unpriv + MPU_xQueueReceive_Priv: + b MPU_xQueueReceiveImpl + MPU_xQueueReceive_Unpriv: + svc #SYSTEM_CALL_xQueueReceive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueuePeek +MPU_xQueuePeek: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueuePeek_Unpriv + MPU_xQueuePeek_Priv: + b MPU_xQueuePeekImpl + MPU_xQueuePeek_Unpriv: + svc #SYSTEM_CALL_xQueuePeek +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueSemaphoreTake +MPU_xQueueSemaphoreTake: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueSemaphoreTake_Unpriv + MPU_xQueueSemaphoreTake_Priv: + b MPU_xQueueSemaphoreTakeImpl + MPU_xQueueSemaphoreTake_Unpriv: + svc #SYSTEM_CALL_xQueueSemaphoreTake +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGetMutexHolder +MPU_xQueueGetMutexHolder: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGetMutexHolder_Unpriv + MPU_xQueueGetMutexHolder_Priv: + b MPU_xQueueGetMutexHolderImpl + MPU_xQueueGetMutexHolder_Unpriv: + svc #SYSTEM_CALL_xQueueGetMutexHolder +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueTakeMutexRecursive +MPU_xQueueTakeMutexRecursive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueTakeMutexRecursive_Unpriv + MPU_xQueueTakeMutexRecursive_Priv: + b MPU_xQueueTakeMutexRecursiveImpl + MPU_xQueueTakeMutexRecursive_Unpriv: + svc #SYSTEM_CALL_xQueueTakeMutexRecursive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGiveMutexRecursive +MPU_xQueueGiveMutexRecursive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGiveMutexRecursive_Unpriv + MPU_xQueueGiveMutexRecursive_Priv: + b MPU_xQueueGiveMutexRecursiveImpl + MPU_xQueueGiveMutexRecursive_Unpriv: + svc #SYSTEM_CALL_xQueueGiveMutexRecursive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueSelectFromSet +MPU_xQueueSelectFromSet: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueSelectFromSet_Unpriv + MPU_xQueueSelectFromSet_Priv: + b MPU_xQueueSelectFromSetImpl + MPU_xQueueSelectFromSet_Unpriv: + svc #SYSTEM_CALL_xQueueSelectFromSet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueAddToSet +MPU_xQueueAddToSet: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueAddToSet_Unpriv + MPU_xQueueAddToSet_Priv: + b MPU_xQueueAddToSetImpl + MPU_xQueueAddToSet_Unpriv: + svc #SYSTEM_CALL_xQueueAddToSet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vQueueAddToRegistry +MPU_vQueueAddToRegistry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vQueueAddToRegistry_Unpriv + MPU_vQueueAddToRegistry_Priv: + b MPU_vQueueAddToRegistryImpl + MPU_vQueueAddToRegistry_Unpriv: + svc #SYSTEM_CALL_vQueueAddToRegistry +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vQueueUnregisterQueue +MPU_vQueueUnregisterQueue: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vQueueUnregisterQueue_Unpriv + MPU_vQueueUnregisterQueue_Priv: + b MPU_vQueueUnregisterQueueImpl + MPU_vQueueUnregisterQueue_Unpriv: + svc #SYSTEM_CALL_vQueueUnregisterQueue +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pcQueueGetName +MPU_pcQueueGetName: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pcQueueGetName_Unpriv + MPU_pcQueueGetName_Priv: + b MPU_pcQueueGetNameImpl + MPU_pcQueueGetName_Unpriv: + svc #SYSTEM_CALL_pcQueueGetName +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pvTimerGetTimerID +MPU_pvTimerGetTimerID: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pvTimerGetTimerID_Unpriv + MPU_pvTimerGetTimerID_Priv: + b MPU_pvTimerGetTimerIDImpl + MPU_pvTimerGetTimerID_Unpriv: + svc #SYSTEM_CALL_pvTimerGetTimerID +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTimerSetTimerID +MPU_vTimerSetTimerID: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTimerSetTimerID_Unpriv + MPU_vTimerSetTimerID_Priv: + b MPU_vTimerSetTimerIDImpl + MPU_vTimerSetTimerID_Unpriv: + svc #SYSTEM_CALL_vTimerSetTimerID +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerIsTimerActive +MPU_xTimerIsTimerActive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerIsTimerActive_Unpriv + MPU_xTimerIsTimerActive_Priv: + b MPU_xTimerIsTimerActiveImpl + MPU_xTimerIsTimerActive_Unpriv: + svc #SYSTEM_CALL_xTimerIsTimerActive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetTimerDaemonTaskHandle +MPU_xTimerGetTimerDaemonTaskHandle: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv + MPU_xTimerGetTimerDaemonTaskHandle_Priv: + b MPU_xTimerGetTimerDaemonTaskHandleImpl + MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGenericCommandFromTaskEntry +MPU_xTimerGenericCommandFromTaskEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGenericCommandFromTask_Unpriv + MPU_xTimerGenericCommandFromTask_Priv: + b MPU_xTimerGenericCommandFromTaskImpl + MPU_xTimerGenericCommandFromTask_Unpriv: + svc #SYSTEM_CALL_xTimerGenericCommandFromTask +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pcTimerGetName +MPU_pcTimerGetName: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pcTimerGetName_Unpriv + MPU_pcTimerGetName_Priv: + b MPU_pcTimerGetNameImpl + MPU_pcTimerGetName_Unpriv: + svc #SYSTEM_CALL_pcTimerGetName +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTimerSetReloadMode +MPU_vTimerSetReloadMode: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTimerSetReloadMode_Unpriv + MPU_vTimerSetReloadMode_Priv: + b MPU_vTimerSetReloadModeImpl + MPU_vTimerSetReloadMode_Unpriv: + svc #SYSTEM_CALL_vTimerSetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetReloadMode +MPU_xTimerGetReloadMode: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetReloadMode_Unpriv + MPU_xTimerGetReloadMode_Priv: + b MPU_xTimerGetReloadModeImpl + MPU_xTimerGetReloadMode_Unpriv: + svc #SYSTEM_CALL_xTimerGetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTimerGetReloadMode +MPU_uxTimerGetReloadMode: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTimerGetReloadMode_Unpriv + MPU_uxTimerGetReloadMode_Priv: + b MPU_uxTimerGetReloadModeImpl + MPU_uxTimerGetReloadMode_Unpriv: + svc #SYSTEM_CALL_uxTimerGetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetPeriod +MPU_xTimerGetPeriod: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetPeriod_Unpriv + MPU_xTimerGetPeriod_Priv: + b MPU_xTimerGetPeriodImpl + MPU_xTimerGetPeriod_Unpriv: + svc #SYSTEM_CALL_xTimerGetPeriod +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetExpiryTime +MPU_xTimerGetExpiryTime: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetExpiryTime_Unpriv + MPU_xTimerGetExpiryTime_Priv: + b MPU_xTimerGetExpiryTimeImpl + MPU_xTimerGetExpiryTime_Unpriv: + svc #SYSTEM_CALL_xTimerGetExpiryTime +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupWaitBitsEntry +MPU_xEventGroupWaitBitsEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupWaitBits_Unpriv + MPU_xEventGroupWaitBits_Priv: + b MPU_xEventGroupWaitBitsImpl + MPU_xEventGroupWaitBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupWaitBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupClearBits +MPU_xEventGroupClearBits: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupClearBits_Unpriv + MPU_xEventGroupClearBits_Priv: + b MPU_xEventGroupClearBitsImpl + MPU_xEventGroupClearBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupClearBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupSetBits +MPU_xEventGroupSetBits: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupSetBits_Unpriv + MPU_xEventGroupSetBits_Priv: + b MPU_xEventGroupSetBitsImpl + MPU_xEventGroupSetBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupSetBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupSync +MPU_xEventGroupSync: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupSync_Unpriv + MPU_xEventGroupSync_Priv: + b MPU_xEventGroupSyncImpl + MPU_xEventGroupSync_Unpriv: + svc #SYSTEM_CALL_xEventGroupSync +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxEventGroupGetNumber +MPU_uxEventGroupGetNumber: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxEventGroupGetNumber_Unpriv + MPU_uxEventGroupGetNumber_Priv: + b MPU_uxEventGroupGetNumberImpl + MPU_uxEventGroupGetNumber_Unpriv: + svc #SYSTEM_CALL_uxEventGroupGetNumber +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vEventGroupSetNumber +MPU_vEventGroupSetNumber: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vEventGroupSetNumber_Unpriv + MPU_vEventGroupSetNumber_Priv: + b MPU_vEventGroupSetNumberImpl + MPU_vEventGroupSetNumber_Unpriv: + svc #SYSTEM_CALL_vEventGroupSetNumber +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSend +MPU_xStreamBufferSend: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSend_Unpriv + MPU_xStreamBufferSend_Priv: + b MPU_xStreamBufferSendImpl + MPU_xStreamBufferSend_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferReceive +MPU_xStreamBufferReceive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferReceive_Unpriv + MPU_xStreamBufferReceive_Priv: + b MPU_xStreamBufferReceiveImpl + MPU_xStreamBufferReceive_Unpriv: + svc #SYSTEM_CALL_xStreamBufferReceive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferIsFull +MPU_xStreamBufferIsFull: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferIsFull_Unpriv + MPU_xStreamBufferIsFull_Priv: + b MPU_xStreamBufferIsFullImpl + MPU_xStreamBufferIsFull_Unpriv: + svc #SYSTEM_CALL_xStreamBufferIsFull +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferIsEmpty +MPU_xStreamBufferIsEmpty: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferIsEmpty_Unpriv + MPU_xStreamBufferIsEmpty_Priv: + b MPU_xStreamBufferIsEmptyImpl + MPU_xStreamBufferIsEmpty_Unpriv: + svc #SYSTEM_CALL_xStreamBufferIsEmpty +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSpacesAvailable +MPU_xStreamBufferSpacesAvailable: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSpacesAvailable_Unpriv + MPU_xStreamBufferSpacesAvailable_Priv: + b MPU_xStreamBufferSpacesAvailableImpl + MPU_xStreamBufferSpacesAvailable_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSpacesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferBytesAvailable +MPU_xStreamBufferBytesAvailable: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferBytesAvailable_Unpriv + MPU_xStreamBufferBytesAvailable_Priv: + b MPU_xStreamBufferBytesAvailableImpl + MPU_xStreamBufferBytesAvailable_Unpriv: + svc #SYSTEM_CALL_xStreamBufferBytesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSetTriggerLevel +MPU_xStreamBufferSetTriggerLevel: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSetTriggerLevel_Unpriv + MPU_xStreamBufferSetTriggerLevel_Priv: + b MPU_xStreamBufferSetTriggerLevelImpl + MPU_xStreamBufferSetTriggerLevel_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferNextMessageLengthBytes +MPU_xStreamBufferNextMessageLengthBytes: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv + MPU_xStreamBufferNextMessageLengthBytes_Priv: + b MPU_xStreamBufferNextMessageLengthBytesImpl + MPU_xStreamBufferNextMessageLengthBytes_Unpriv: + svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes +/*-----------------------------------------------------------*/ + +/* Default weak implementations in case one is not available from + * mpu_wrappers because of config options. */ + + PUBWEAK MPU_xTaskDelayUntilImpl +MPU_xTaskDelayUntilImpl: + b MPU_xTaskDelayUntilImpl + + PUBWEAK MPU_xTaskAbortDelayImpl +MPU_xTaskAbortDelayImpl: + b MPU_xTaskAbortDelayImpl + + PUBWEAK MPU_vTaskDelayImpl +MPU_vTaskDelayImpl: + b MPU_vTaskDelayImpl + + PUBWEAK MPU_uxTaskPriorityGetImpl +MPU_uxTaskPriorityGetImpl: + b MPU_uxTaskPriorityGetImpl + + PUBWEAK MPU_eTaskGetStateImpl +MPU_eTaskGetStateImpl: + b MPU_eTaskGetStateImpl + + PUBWEAK MPU_vTaskGetInfoImpl +MPU_vTaskGetInfoImpl: + b MPU_vTaskGetInfoImpl + + PUBWEAK MPU_xTaskGetIdleTaskHandleImpl +MPU_xTaskGetIdleTaskHandleImpl: + b MPU_xTaskGetIdleTaskHandleImpl + + PUBWEAK MPU_vTaskSuspendImpl +MPU_vTaskSuspendImpl: + b MPU_vTaskSuspendImpl + + PUBWEAK MPU_vTaskResumeImpl +MPU_vTaskResumeImpl: + b MPU_vTaskResumeImpl + + PUBWEAK MPU_xTaskGetTickCountImpl +MPU_xTaskGetTickCountImpl: + b MPU_xTaskGetTickCountImpl + + PUBWEAK MPU_uxTaskGetNumberOfTasksImpl +MPU_uxTaskGetNumberOfTasksImpl: + b MPU_uxTaskGetNumberOfTasksImpl + + PUBWEAK MPU_ulTaskGetRunTimeCounterImpl +MPU_ulTaskGetRunTimeCounterImpl: + b MPU_ulTaskGetRunTimeCounterImpl + + PUBWEAK MPU_ulTaskGetRunTimePercentImpl +MPU_ulTaskGetRunTimePercentImpl: + b MPU_ulTaskGetRunTimePercentImpl + + PUBWEAK MPU_ulTaskGetIdleRunTimePercentImpl +MPU_ulTaskGetIdleRunTimePercentImpl: + b MPU_ulTaskGetIdleRunTimePercentImpl + + PUBWEAK MPU_ulTaskGetIdleRunTimeCounterImpl +MPU_ulTaskGetIdleRunTimeCounterImpl: + b MPU_ulTaskGetIdleRunTimeCounterImpl + + PUBWEAK MPU_vTaskSetApplicationTaskTagImpl +MPU_vTaskSetApplicationTaskTagImpl: + b MPU_vTaskSetApplicationTaskTagImpl + + PUBWEAK MPU_xTaskGetApplicationTaskTagImpl +MPU_xTaskGetApplicationTaskTagImpl: + b MPU_xTaskGetApplicationTaskTagImpl + + PUBWEAK MPU_vTaskSetThreadLocalStoragePointerImpl +MPU_vTaskSetThreadLocalStoragePointerImpl: + b MPU_vTaskSetThreadLocalStoragePointerImpl + + PUBWEAK MPU_pvTaskGetThreadLocalStoragePointerImpl +MPU_pvTaskGetThreadLocalStoragePointerImpl: + b MPU_pvTaskGetThreadLocalStoragePointerImpl + + PUBWEAK MPU_uxTaskGetSystemStateImpl +MPU_uxTaskGetSystemStateImpl: + b MPU_uxTaskGetSystemStateImpl + + PUBWEAK MPU_uxTaskGetStackHighWaterMarkImpl +MPU_uxTaskGetStackHighWaterMarkImpl: + b MPU_uxTaskGetStackHighWaterMarkImpl + + PUBWEAK MPU_uxTaskGetStackHighWaterMark2Impl +MPU_uxTaskGetStackHighWaterMark2Impl: + b MPU_uxTaskGetStackHighWaterMark2Impl + + PUBWEAK MPU_xTaskGetCurrentTaskHandleImpl +MPU_xTaskGetCurrentTaskHandleImpl: + b MPU_xTaskGetCurrentTaskHandleImpl + + PUBWEAK MPU_xTaskGetSchedulerStateImpl +MPU_xTaskGetSchedulerStateImpl: + b MPU_xTaskGetSchedulerStateImpl + + PUBWEAK MPU_vTaskSetTimeOutStateImpl +MPU_vTaskSetTimeOutStateImpl: + b MPU_vTaskSetTimeOutStateImpl + + PUBWEAK MPU_xTaskCheckForTimeOutImpl +MPU_xTaskCheckForTimeOutImpl: + b MPU_xTaskCheckForTimeOutImpl + + PUBWEAK MPU_xTaskGenericNotifyImpl +MPU_xTaskGenericNotifyImpl: + b MPU_xTaskGenericNotifyImpl + + PUBWEAK MPU_xTaskGenericNotifyWaitImpl +MPU_xTaskGenericNotifyWaitImpl: + b MPU_xTaskGenericNotifyWaitImpl + + PUBWEAK MPU_ulTaskGenericNotifyTakeImpl +MPU_ulTaskGenericNotifyTakeImpl: + b MPU_ulTaskGenericNotifyTakeImpl + + PUBWEAK MPU_xTaskGenericNotifyStateClearImpl +MPU_xTaskGenericNotifyStateClearImpl: + b MPU_xTaskGenericNotifyStateClearImpl + + PUBWEAK MPU_ulTaskGenericNotifyValueClearImpl +MPU_ulTaskGenericNotifyValueClearImpl: + b MPU_ulTaskGenericNotifyValueClearImpl + + PUBWEAK MPU_xQueueGenericSendImpl +MPU_xQueueGenericSendImpl: + b MPU_xQueueGenericSendImpl + + PUBWEAK MPU_uxQueueMessagesWaitingImpl +MPU_uxQueueMessagesWaitingImpl: + b MPU_uxQueueMessagesWaitingImpl + + PUBWEAK MPU_uxQueueSpacesAvailableImpl +MPU_uxQueueSpacesAvailableImpl: + b MPU_uxQueueSpacesAvailableImpl + + PUBWEAK MPU_xQueueReceiveImpl +MPU_xQueueReceiveImpl: + b MPU_xQueueReceiveImpl + + PUBWEAK MPU_xQueuePeekImpl +MPU_xQueuePeekImpl: + b MPU_xQueuePeekImpl + + PUBWEAK MPU_xQueueSemaphoreTakeImpl +MPU_xQueueSemaphoreTakeImpl: + b MPU_xQueueSemaphoreTakeImpl + + PUBWEAK MPU_xQueueGetMutexHolderImpl +MPU_xQueueGetMutexHolderImpl: + b MPU_xQueueGetMutexHolderImpl + + PUBWEAK MPU_xQueueTakeMutexRecursiveImpl +MPU_xQueueTakeMutexRecursiveImpl: + b MPU_xQueueTakeMutexRecursiveImpl + + PUBWEAK MPU_xQueueGiveMutexRecursiveImpl +MPU_xQueueGiveMutexRecursiveImpl: + b MPU_xQueueGiveMutexRecursiveImpl + + PUBWEAK MPU_xQueueSelectFromSetImpl +MPU_xQueueSelectFromSetImpl: + b MPU_xQueueSelectFromSetImpl + + PUBWEAK MPU_xQueueAddToSetImpl +MPU_xQueueAddToSetImpl: + b MPU_xQueueAddToSetImpl + + PUBWEAK MPU_vQueueAddToRegistryImpl +MPU_vQueueAddToRegistryImpl: + b MPU_vQueueAddToRegistryImpl + + PUBWEAK MPU_vQueueUnregisterQueueImpl +MPU_vQueueUnregisterQueueImpl: + b MPU_vQueueUnregisterQueueImpl + + PUBWEAK MPU_pcQueueGetNameImpl +MPU_pcQueueGetNameImpl: + b MPU_pcQueueGetNameImpl + + PUBWEAK MPU_pvTimerGetTimerIDImpl +MPU_pvTimerGetTimerIDImpl: + b MPU_pvTimerGetTimerIDImpl + + PUBWEAK MPU_vTimerSetTimerIDImpl +MPU_vTimerSetTimerIDImpl: + b MPU_vTimerSetTimerIDImpl + + PUBWEAK MPU_xTimerIsTimerActiveImpl +MPU_xTimerIsTimerActiveImpl: + b MPU_xTimerIsTimerActiveImpl + + PUBWEAK MPU_xTimerGetTimerDaemonTaskHandleImpl +MPU_xTimerGetTimerDaemonTaskHandleImpl: + b MPU_xTimerGetTimerDaemonTaskHandleImpl + + PUBWEAK MPU_xTimerGenericCommandFromTaskImpl +MPU_xTimerGenericCommandFromTaskImpl: + b MPU_xTimerGenericCommandFromTaskImpl + + PUBWEAK MPU_pcTimerGetNameImpl +MPU_pcTimerGetNameImpl: + b MPU_pcTimerGetNameImpl + + PUBWEAK MPU_vTimerSetReloadModeImpl +MPU_vTimerSetReloadModeImpl: + b MPU_vTimerSetReloadModeImpl + + PUBWEAK MPU_xTimerGetReloadModeImpl +MPU_xTimerGetReloadModeImpl: + b MPU_xTimerGetReloadModeImpl + + PUBWEAK MPU_uxTimerGetReloadModeImpl +MPU_uxTimerGetReloadModeImpl: + b MPU_uxTimerGetReloadModeImpl + + PUBWEAK MPU_xTimerGetPeriodImpl +MPU_xTimerGetPeriodImpl: + b MPU_xTimerGetPeriodImpl + + PUBWEAK MPU_xTimerGetExpiryTimeImpl +MPU_xTimerGetExpiryTimeImpl: + b MPU_xTimerGetExpiryTimeImpl + + PUBWEAK MPU_xEventGroupWaitBitsImpl +MPU_xEventGroupWaitBitsImpl: + b MPU_xEventGroupWaitBitsImpl + + PUBWEAK MPU_xEventGroupClearBitsImpl +MPU_xEventGroupClearBitsImpl: + b MPU_xEventGroupClearBitsImpl + + PUBWEAK MPU_xEventGroupSetBitsImpl +MPU_xEventGroupSetBitsImpl: + b MPU_xEventGroupSetBitsImpl + + PUBWEAK MPU_xEventGroupSyncImpl +MPU_xEventGroupSyncImpl: + b MPU_xEventGroupSyncImpl + + PUBWEAK MPU_uxEventGroupGetNumberImpl +MPU_uxEventGroupGetNumberImpl: + b MPU_uxEventGroupGetNumberImpl + + PUBWEAK MPU_vEventGroupSetNumberImpl +MPU_vEventGroupSetNumberImpl: + b MPU_vEventGroupSetNumberImpl + + PUBWEAK MPU_xStreamBufferSendImpl +MPU_xStreamBufferSendImpl: + b MPU_xStreamBufferSendImpl + + PUBWEAK MPU_xStreamBufferReceiveImpl +MPU_xStreamBufferReceiveImpl: + b MPU_xStreamBufferReceiveImpl + + PUBWEAK MPU_xStreamBufferIsFullImpl +MPU_xStreamBufferIsFullImpl: + b MPU_xStreamBufferIsFullImpl + + PUBWEAK MPU_xStreamBufferIsEmptyImpl +MPU_xStreamBufferIsEmptyImpl: + b MPU_xStreamBufferIsEmptyImpl + + PUBWEAK MPU_xStreamBufferSpacesAvailableImpl +MPU_xStreamBufferSpacesAvailableImpl: + b MPU_xStreamBufferSpacesAvailableImpl + + PUBWEAK MPU_xStreamBufferBytesAvailableImpl +MPU_xStreamBufferBytesAvailableImpl: + b MPU_xStreamBufferBytesAvailableImpl + + PUBWEAK MPU_xStreamBufferSetTriggerLevelImpl +MPU_xStreamBufferSetTriggerLevelImpl: + b MPU_xStreamBufferSetTriggerLevelImpl + + PUBWEAK MPU_xStreamBufferNextMessageLengthBytesImpl +MPU_xStreamBufferNextMessageLengthBytesImpl: + b MPU_xStreamBufferNextMessageLengthBytesImpl + +/*-----------------------------------------------------------*/ + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + END diff --git a/portable/IAR/ARM_STAR_MC3/non_secure/port.c b/portable/IAR/ARM_STAR_MC3/non_secure/port.c new file mode 100644 index 000000000..76d2b2445 --- /dev/null +++ b/portable/IAR/ARM_STAR_MC3/non_secure/port.c @@ -0,0 +1,2280 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024-2025 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU includes. */ +#include "mpu_wrappers.h" +#include "mpu_syscall_numbers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration settings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to check the validity of an interrupt priority. + */ +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) ) +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used during system call enter and exit. + */ +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Offsets in the stack to the parameters when inside the SVC handler. + */ +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +#if ( portARMV8M_MINOR_VERSION >= 1 ) + + /* Enable Privileged eXecute Never MPU attribute for the selected memory + * region. */ + #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL ) +#endif /* portARMV8M_MINOR_VERSION >= 1 */ + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Extract first address of the MPU region as encoded in the + * RBAR (Region Base Address Register) value. */ +#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \ + ( ( rbar ) & portMPU_RBAR_ADDRESS_MASK ) + +/* Extract last address of the MPU region as encoded in the + * RLAR (Region Limit Address Register) value. */ +#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \ + ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK ) + +/* Does addr lies within [start, end] address range? */ +#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \ + ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) ) + +/* Is the access request satisfied by the available permissions? */ +#define portIS_AUTHORIZED( accessRequest, permissions ) \ + ( ( ( permissions ) & ( accessRequest ) ) == accessRequest ) + +/* Max value that fits in a uint32_t type. */ +#define portUINT32_MAX ( ~( ( uint32_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. + */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 + +/** + * @brief Constants required to check and configure PACBTI security feature implementation. + */ +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) ) + + #define portCONTROL_UPAC_EN ( 1UL << 7UL ) + #define portCONTROL_PAC_EN ( 1UL << 6UL ) + #define portCONTROL_UBTI_EN ( 1UL << 5UL ) + #define portCONTROL_BTI_EN ( 1UL << 4UL ) + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Extract MPU region's access permissions from the Region Base Address + * Register (RBAR) value. + * + * @param ulRBARValue RBAR value for the MPU region. + * + * @return uint32_t Access permissions. + */ + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + + /** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + /** + * @brief Configures PACBTI features. + * + * This function configures the Pointer Authentication, and Branch Target + * Identification security features as per the user configuration. It returns + * the value of the special purpose CONTROL register accordingly, and optionally + * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M + * architecture based) target supports PACBTI security feature. + * + * @param xWriteControlRegister Used to control whether the special purpose + * CONTROL register should be updated or not. + * + * @return CONTROL register value according to the configured PACBTI option. + */ + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the system call stack so that upon returning from + * SVC, the system call stack is used. + * + * @param pulTaskStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + * @param ucSystemCallNumber The system call number of the system call. + */ + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Raise SVC for exiting from a system call. + */ + void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief This variable is set to pdTRUE when the scheduler is started. + */ + PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + + /** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +/** + * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + /** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + + /** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + + /** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the cpsid instruction + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessPermissions = 0; + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_ONLY ) + { + ulAccessPermissions = tskMPU_READ_PERMISSION; + } + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_WRITE ) + { + ulAccessPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION ); + } + + return ulAccessPermissions; + } + +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } + +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ portOFFSET_TO_PC ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ]; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulSystemCallStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the system call section (i.e. application is + * not raising SVC directly). + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as + * it is non-NULL only during the execution of a system call (i.e. + * between system call enter and exit). + * 3. System call is not for a kernel API disabled by the configuration + * in FreeRTOSConfig.h. + * 4. We do not need to check that ucSystemCallNumber is within range + * because the assembly SVC handler checks that before calling + * this function. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) && + ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) ) + { + pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the system call stack for the stack frame. */ + pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulSystemCallStack[ i ] = pulTaskStack[ i ]; + } + + /* Store the value of the Link Register before the SVC was raised. + * It contains the address of the caller of the System Call entry + * point (i.e. the caller of the MPU_). We need to restore it + * when we exit from the system call. */ + pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; + + /* Store the value of the PSPLIM register before the SVC was raised. + * We need to restore it when we exit from the system call. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* Use the pulSystemCallStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif + + /* Start executing the system call upon returning from this handler. */ + pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; + + /* Raise a request to exit from the system call upon finishing the + * system call. */ + pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; + + /* Remember the location where we should copy the stack frame when we exit from + * the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize; + + /* Record if the hardware used padding to force the stack pointer + * to be double word aligned. */ + if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK ) + { + pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG; + } + else + { + pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG ); + } + + /* We ensure in pxPortInitialiseStack that the system call stack is + * double word aligned and therefore, there is no need of padding. + * Clear the bit[9] of stacked xPSR. */ + pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + + /* Raise the privilege for the duration of the system call. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " bics r0, r1 \n" /* Clear nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */ + { + __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulTaskStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the privileged code (i.e. application is not + * raising SVC directly). This SVC is only raised from + * vRequestSystemCallExit which is in the privileged code section. + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL - + * this means that we previously entered a system call and the + * application is not attempting to exit without entering a system + * call. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) ) + { + pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the task stack for the stack frame. */ + pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulTaskStack[ i ] = pulSystemCallStack[ i ]; + } + + /* Use the pulTaskStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) ); + + /* Return to the caller of the System Call entry point (i.e. the + * caller of the MPU_). */ + pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + /* Ensure that LR has a valid value.*/ + pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + + /* Restore the PSPLIM register to what it was at the time of + * system call entry. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* If the hardware used padding to force the stack pointer + * to be double word aligned, set the stacked xPSR bit[9], + * otherwise clear it. */ + if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG ) + { + pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK; + } + else + { + pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + } + + /* This is not NULL only for the duration of the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; + + /* Drop the privilege before returning to the thread mode. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " orrs r0, r1 \n" /* Set nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xTaskIsPrivileged = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xTaskIsPrivileged = pdTRUE; + } + + return xTaskIsPrivileged; + } + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged, + xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulIndex = 0; + uint32_t ulControl = 0x0; + + xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ + ulIndex++; + + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + ulIndex++; + + #if ( configENABLE_TRUSTZONE == 1 ) + { + xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */ + ulIndex++; + } + #endif /* configENABLE_TRUSTZONE */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + ulIndex++; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Check PACBTI security feature configuration before pushing the + * CONTROL register's value on task's TCB. */ + ulControl = prvConfigurePACBTI( pdFALSE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + if( xRunPrivileged == pdTRUE ) + { + xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + else + { + xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG ); + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ + ulIndex++; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + { + /* Ensure that the system call stack is double word aligned. */ + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) + + ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + /* This is not NULL only for the duration of a system call. */ + xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL; + } + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ]; + ulIndex++; + } + } + #endif /* configENABLE_PAC */ + + return &( xMPUSettings->ulContext[ ulIndex ] ); + } + +#else /* configENABLE_MPU */ + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ + { + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + pxTopOfStack--; + *pxTopOfStack = ulTaskPacKey[ i ]; + } + } + #endif /* configENABLE_PAC */ + + return pxTopOfStack; + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Set the CONTROL register value based on PACBTI security feature + * configuration before starting the first task. */ + ( void ) prvConfigurePACBTI( pdTRUE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + { + xSchedulerRunning = pdTRUE; + } + #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + configSTACK_DEPTH_TYPE uxStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( uxStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* PXN. */ + #if ( portARMV8M_MINOR_VERSION >= 1 ) + { + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ); + } + } + #endif /* portARMV8M_MINOR_VERSION >= 1 */ + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, + uint32_t ulBufferLength, + uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */ + + { + uint32_t i, ulBufferStartAddress, ulBufferEndAddress; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE ) + { + ulBufferStartAddress = ( uint32_t ) pvBuffer; + ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL ); + + for( i = 0; i < portTOTAL_NUM_REGIONS; i++ ) + { + /* Is the MPU region enabled? */ + if( ( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR & portMPU_RLAR_REGION_ENABLE ) == portMPU_RLAR_REGION_ENABLE ) + { + if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_AUTHORIZED( ulAccessRequested, + prvGetRegionAccessPermissions( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ) ) ) + { + xAccessGranted = pdTRUE; + break; + } + } + } + } + } + + return xAccessGranted; + } + +#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings; + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else + { + xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 ) + { + xAccessGranted = pdTRUE; + } + } + } + + return xAccessGranted; + } + + #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + ( void ) lInternalIndexOfKernelObject; + + /* If Access Control List feature is not used, all the tasks have + * access to all the kernel objects. */ + return pdTRUE; + } + + #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + { + uint32_t ulControl = 0x0; + + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); + + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; + + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/ARM_STAR_MC3/non_secure/portasm.h b/portable/IAR/ARM_STAR_MC3/non_secure/portasm.h new file mode 100644 index 000000000..b7021b024 --- /dev/null +++ b/portable/IAR/ARM_STAR_MC3/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kernel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/portable/IAR/ARM_STAR_MC3/non_secure/portasm.s b/portable/IAR/ARM_STAR_MC3/non_secure/portasm.s new file mode 100644 index 000000000..8d5988819 --- /dev/null +++ b/portable/IAR/ARM_STAR_MC3/non_secure/portasm.s @@ -0,0 +1,543 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" + +/* System call numbers includes. */ +#include "mpu_syscall_numbers.h" + +#ifndef configUSE_MPU_WRAPPERS_V1 + #define configUSE_MPU_WRAPPERS_V1 0 +#endif + + EXTERN pxCurrentTCB + EXTERN xSecureContext + EXTERN vTaskSwitchContext + EXTERN vPortSVCHandler_C + EXTERN SecureContext_SaveContext + EXTERN SecureContext_LoadContext +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + EXTERN vSystemCallEnter + EXTERN vSystemCallExit +#endif + + PUBLIC xIsPrivileged + PUBLIC vResetPrivilege + PUBLIC vPortAllocateSecureContext + PUBLIC vRestoreContextOfFirstTask + PUBLIC vRaisePrivilege + PUBLIC vStartFirstTask + PUBLIC ulSetInterruptMask + PUBLIC vClearInterruptMask + PUBLIC PendSV_Handler + PUBLIC SVC_Handler + PUBLIC vPortFreeSecureContext +/*-----------------------------------------------------------*/ + +/*---------------- Unprivileged Functions -------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION .text:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +xIsPrivileged: + mrs r0, control /* r0 = CONTROL. */ + tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + ite ne + movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vResetPrivilege: + mrs r0, control /* r0 = CONTROL. */ + orr r0, r0, #1 /* r0 = r0 | 1. */ + msr control, r0 /* CONTROL = r0. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vPortAllocateSecureContext: + svc 100 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 100. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +/*----------------- Privileged Functions --------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION privileged_functions:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +vRestoreContextOfFirstTask: + program_mpu_first_task: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r3] /* r0 = pxCurrentTCB. */ + + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + str r2, [r1] /* Disable MPU. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r1, [r2] /* Program MAIR0. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + + movs r3, #4 /* r3 = 4. */ + str r3, [r1] /* Program RNR = 4. */ + ldmia r0!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + #if ( configTOTAL_MPU_REGIONS == 16 ) + movs r3, #8 /* r3 = 8. */ + str r3, [r1] /* Program RNR = 8. */ + ldmia r0!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + movs r3, #12 /* r3 = 12. */ + str r3, [r1] /* Program RNR = 12. */ + ldmia r0!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + orr r2, #1 /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */ + str r2, [r1] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + + restore_context_first_task: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* r1 = pxCurrentTCB.*/ + ldr r2, [r1] /* r2 = Location of saved context in TCB. */ + + restore_special_regs_first_task: + #if ( configENABLE_PAC == 1 ) + ldmdb r2!, {r3-r6} /* Read task's dedicated PAC key from the task's context. */ + msr PAC_KEY_P_0, r3 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_1, r4 + msr PAC_KEY_P_2, r5 + msr PAC_KEY_P_3, r6 + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + ldmdb r2!, {r0, r3-r5, lr} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */ + msr psp, r3 + msr psplim, r4 + msr control, r5 + ldr r4, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + str r0, [r4] /* Restore xSecureContext. */ + + restore_general_regs_first_task: + ldmdb r2!, {r4-r11} /* r4-r11 contain hardware saved context. */ + stmia r3!, {r4-r11} /* Copy the hardware saved context on the task stack. */ + ldmdb r2!, {r4-r11} /* r4-r11 restored. */ + + restore_context_done_first_task: + str r2, [r1] /* Save the location where the context should be saved next as the first member of TCB. */ + mov r0, #0 + msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ + bx lr + +#else /* configENABLE_MPU */ + +vRestoreContextOfFirstTask: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r3, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + +#if ( configENABLE_PAC == 1 ) + ldmia r0!, {r1-r4} /* Read task's dedicated PAC key from stack. */ + msr PAC_KEY_P_3, r1 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_2, r2 + msr PAC_KEY_P_1, r3 + msr PAC_KEY_P_0, r4 + clrm {r1-r4} /* Clear r1-r4. */ +#endif /* configENABLE_PAC */ + + ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */ + ldr r4, =xSecureContext + str r1, [r4] /* Set xSecureContext to this task's value for the same. */ + msr psplim, r2 /* Set this task's PSPLIM value. */ + mrs r1, control /* Obtain current control register value. */ + orrs r1, r1, #2 /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */ + msr control, r1 /* Write back the new control register value. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + mov r0, #0 + msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ + bx r3 /* Finally, branch to EXC_RETURN. */ + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +vRaisePrivilege: + mrs r0, control /* Read the CONTROL register. */ + bic r0, r0, #1 /* Clear the bit 0. */ + msr control, r0 /* Write back the new CONTROL value. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vStartFirstTask: + ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */ + ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */ + ldr r0, [r0] /* The first entry in vector table is stack pointer. */ + msr msp, r0 /* Set the MSP back to the start of the stack. */ + cpsie i /* Globally enable interrupts. */ + cpsie f + dsb + isb + svc 102 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */ +/*-----------------------------------------------------------*/ + +ulSetInterruptMask: + mrs r0, basepri /* r0 = basepri. Return original basepri value. */ + mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r1 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vClearInterruptMask: + msr basepri, r0 /* basepri = ulMask. */ + dsb + isb + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +PendSV_Handler: + ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + ldr r0, [r3] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */ + ldr r2, [r1] /* r2 = Location in TCB where the context should be saved. */ + + cbz r0, save_ns_context /* No secure context to save. */ + save_s_context: + push {r0-r2, lr} + bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r0-r2, lr} + + save_ns_context: + mov r3, lr /* r3 = LR (EXC_RETURN). */ + lsls r3, r3, #25 /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bmi save_special_regs /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + + save_general_regs: + mrs r3, psp + + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + add r3, r3, #0x20 /* Move r3 to location where s0 is saved. */ + tst lr, #0x10 + ittt eq + vstmiaeq r2!, {s16-s31} /* Store s16-s31. */ + vldmiaeq r3, {s0-s16} /* Copy hardware saved FP context into s0-s16. */ + vstmiaeq r2!, {s0-s16} /* Store hardware saved FP context. */ + sub r3, r3, #0x20 /* Set r3 back to the location of hardware saved context. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + + stmia r2!, {r4-r11} /* Store r4-r11. */ + ldmia r3, {r4-r11} /* Copy the hardware saved context into r4-r11. */ + stmia r2!, {r4-r11} /* Store the hardware saved context. */ + + save_special_regs: + mrs r3, psp /* r3 = PSP. */ + mrs r4, psplim /* r4 = PSPLIM. */ + mrs r5, control /* r5 = CONTROL. */ + stmia r2!, {r0, r3-r5, lr} /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ + #if ( configENABLE_PAC == 1 ) + mrs r3, PAC_KEY_P_0 /* Read task's dedicated PAC key from the PAC key registers. */ + mrs r4, PAC_KEY_P_1 + mrs r5, PAC_KEY_P_2 + mrs r6, PAC_KEY_P_3 + stmia r2!, {r3-r6} /* Store the task's dedicated PAC key on the task's context. */ + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + + str r2, [r1] /* Save the location from where the context should be restored as the first member of TCB. */ + + select_next_task: + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bl vTaskSwitchContext + mov r0, #0 /* r0 = 0. */ + msr basepri, r0 /* Enable interrupts. */ + + program_mpu: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r3] /* r0 = pxCurrentTCB.*/ + + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + str r2, [r1] /* Disable MPU. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r1, [r2] /* Program MAIR0. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + + movs r3, #4 /* r3 = 4. */ + str r3, [r1] /* Program RNR = 4. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + #if ( configTOTAL_MPU_REGIONS == 16 ) + movs r3, #8 /* r3 = 8. */ + str r3, [r1] /* Program RNR = 8. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + movs r3, #12 /* r3 = 12. */ + str r3, [r1] /* Program RNR = 12. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + orr r2, #1 /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */ + str r2, [r1] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + + restore_context: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* r1 = pxCurrentTCB.*/ + ldr r2, [r1] /* r2 = Location of saved context in TCB. */ + + restore_special_regs: + #if ( configENABLE_PAC == 1 ) + ldmdb r2!, {r3-r6} /* Read task's dedicated PAC key from the task's context. */ + msr PAC_KEY_P_0, r3 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_1, r4 + msr PAC_KEY_P_2, r5 + msr PAC_KEY_P_3, r6 + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + ldmdb r2!, {r0, r3-r5, lr} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */ + msr psp, r3 + msr psplim, r4 + msr control, r5 + ldr r4, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + str r0, [r4] /* Restore xSecureContext. */ + cbz r0, restore_ns_context /* No secure context to restore. */ + + restore_s_context: + push {r1-r3, lr} + bl SecureContext_LoadContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r1-r3, lr} + + restore_ns_context: + mov r0, lr /* r0 = LR (EXC_RETURN). */ + lsls r0, r0, #25 /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bmi restore_context_done /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + + restore_general_regs: + ldmdb r2!, {r4-r11} /* r4-r11 contain hardware saved context. */ + stmia r3!, {r4-r11} /* Copy the hardware saved context on the task stack. */ + ldmdb r2!, {r4-r11} /* r4-r11 restored. */ + + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 + ittt eq + vldmdbeq r2!, {s0-s16} /* s0-s16 contain hardware saved FP context. */ + vstmiaeq r3!, {s0-s16} /* Copy hardware saved FP context on the task stack. */ + vldmdbeq r2!, {s16-s31} /* Restore s16-s31. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + + restore_context_done: + str r2, [r1] /* Save the location where the context should be saved next as the first member of TCB. */ + bx lr + +#else /* configENABLE_MPU */ + +PendSV_Handler: + ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + ldr r0, [r3] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */ + mrs r2, psp /* Read PSP in r2. */ + + cbz r0, save_ns_context /* No secure context to save. */ + save_s_context: + push {r0-r2, lr} + bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r0-r2, lr} + + save_ns_context: + mov r3, lr /* r3 = LR. */ + lsls r3, r3, #25 /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bmi save_special_regs /* If r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used. */ + + save_general_regs: + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + it eq + vstmdbeq r2!, {s16-s31} /* Store the additional FP context registers which are not saved automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + stmdb r2!, {r4-r11} /* Store the registers that are not saved automatically. */ + + save_special_regs: + mrs r3, psplim /* r3 = PSPLIM. */ + stmdb r2!, {r0, r3, lr} /* Store xSecureContext, PSPLIM and LR on the stack. */ + #if ( configENABLE_PAC == 1 ) + mrs r3, PAC_KEY_P_3 /* Read task's dedicated PAC key from the PAC key registers. */ + mrs r4, PAC_KEY_P_2 + mrs r5, PAC_KEY_P_1 + mrs r6, PAC_KEY_P_0 + stmdb r2!, {r3-r6} /* Store the task's dedicated PAC key on the stack. */ + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + + str r2, [r1] /* Save the new top of stack in TCB. */ + + select_next_task: + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bl vTaskSwitchContext + mov r0, #0 /* r0 = 0. */ + msr basepri, r0 /* Enable interrupts. */ + + restore_context: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r3] /* Read pxCurrentTCB. */ + ldr r2, [r1] /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */ + + restore_special_regs: + #if ( configENABLE_PAC == 1 ) + ldmia r2!, {r3-r6} /* Read task's dedicated PAC key from stack. */ + msr PAC_KEY_P_3, r3 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_2, r4 + msr PAC_KEY_P_1, r5 + msr PAC_KEY_P_0, r6 + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + ldmia r2!, {r0, r3, lr} http://files.iar.com/ftp/pub/box/bxarm-9.60.3.deb/* Read from stack - r0 = xSecureContext, r3 = PSPLIM and LR restored. */ + msr psplim, r3 /* Restore the PSPLIM register value for the task. */ + ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + str r0, [r3] /* Restore the task's xSecureContext. */ + cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */ + + restore_s_context: + push {r1-r3, lr} + bl SecureContext_LoadContext /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r1-r3, lr} + + restore_ns_context: + mov r0, lr /* r0 = LR (EXC_RETURN). */ + lsls r0, r0, #25 /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bmi restore_context_done /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + + restore_general_regs: + ldmia r2!, {r4-r11} /* Restore the registers that are not automatically restored. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + it eq + vldmiaeq r2!, {s16-s31} /* Restore the additional FP context registers which are not restored automatically. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + + restore_context_done: + msr psp, r2 /* Remember the new top of stack for the task. */ + bx lr + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + +SVC_Handler: + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + + ldr r1, [r0, #24] + ldrb r2, [r1, #-2] + cmp r2, #NUM_SYSTEM_CALLS + blt syscall_enter + cmp r2, #104 /* portSVC_SYSTEM_CALL_EXIT. */ + beq syscall_exit + b vPortSVCHandler_C + + syscall_enter: + mov r1, lr + b vSystemCallEnter + + syscall_exit: + mov r1, lr + b vSystemCallExit + +#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +SVC_Handler: + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + b vPortSVCHandler_C + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +vPortFreeSecureContext: + /* r0 = uint32_t *pulTCB. */ + ldr r2, [r0] /* The first item in the TCB is the top of the stack. */ + ldr r1, [r2] /* The first item on the stack is the task's xSecureContext. */ + cmp r1, #0 /* Raise svc if task's xSecureContext is not NULL. */ + it ne + svcne 101 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 101. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + + END diff --git a/portable/IAR/ARM_STAR_MC3/non_secure/portmacro.h b/portable/IAR/ARM_STAR_MC3/non_secure/portmacro.h new file mode 100644 index 000000000..a0ee66907 --- /dev/null +++ b/portable/IAR/ARM_STAR_MC3/non_secure/portmacro.h @@ -0,0 +1,87 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (c) 2026 Arm Technology (China) Co., Ltd.All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_MVE + #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE. +#endif /* configENABLE_MVE */ +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "STAR-MC3" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portARMV8M_MINOR_VERSION 1 +#define portDONT_DISCARD __root +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ +#pragma diag_suppress=Be006 +#pragma diag_suppress=Pa082 +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/IAR/ARM_STAR_MC3/non_secure/portmacrocommon.h b/portable/IAR/ARM_STAR_MC3/non_secure/portmacrocommon.h new file mode 100644 index 000000000..f373bcad5 --- /dev/null +++ b/portable/IAR/ARM_STAR_MC3/non_secure/portmacrocommon.h @@ -0,0 +1,582 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACROCOMMON_H +#define PORTMACROCOMMON_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. +#endif /* configENABLE_FPU */ + +#ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. +#endif /* configENABLE_MPU */ + +#ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. +#endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() +#define portINLINE __inline +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif +#define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ +extern BaseType_t xPortIsInsideInterrupt( void ); + +extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + +extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; +extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + +extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; +extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + +#if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_PAC == 1 ) + + /** + * @brief Generates 128-bit task's random PAC key. + * + * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be + * filled with a 128-bit random number. + */ + void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); + +#endif /* configENABLE_PAC */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ +#if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) +#else + #define portPRIVILEGE_BIT ( 0x0UL ) +#endif /* configENABLE_MPU */ + +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ +#define portPRIVILEGED_FLASH_REGION ( 0UL ) +#define portUNPRIVILEGED_FLASH_REGION ( 1UL ) +#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) +#define portPRIVILEGED_RAM_REGION ( 3UL ) +#define portSTACK_REGION ( 4UL ) +#define portFIRST_CONFIGURABLE_REGION ( 5UL ) +#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) +#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) +#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ +#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ +#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ +#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ +#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ +#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ +#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ +#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) +#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) +#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + +#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) +#define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) +#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) +#define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + +#define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + #ifndef configSYSTEM_CALL_STACK_SIZE + #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. + #endif + + /** + * @brief System call stack. + */ + typedef struct SYSTEM_CALL_STACK_INFO + { + uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; + uint32_t * pulSystemCallStack; + uint32_t * pulSystemCallStackLimit; + uint32_t * pulTaskStack; + uint32_t ulLinkRegisterAtSystemCallEntry; + uint32_t ulStackLimitRegisterAtSystemCallEntry; + } xSYSTEM_CALL_STACK_INFO; + + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + /** + * @brief MPU settings as stored in the TCB. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><-----------><----> + * 16 17 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 71 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 17 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 55 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | | | PC, xPSR | EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><-----------><----> + * 16 17 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 70 + + #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + /* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 17 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 54 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+------------------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +----------+-----------------+------------------------------+------------+-----+ + * + * <---------><----------------><------------------------------><-----------><----> + * 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 38 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+----------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | PC, xPSR | EXC_RETURN | | | + * +----------+-----------------+----------------------+------------+-----+ + * + * <---------><----------------><----------------------><-----------><----> + * 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 37 + + #else /* #if( configENABLE_TRUSTZONE == 1 ) */ + + /* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) + + /* Size of an Access Control List (ACL) entry in bits. */ + #define portACL_ENTRY_SIZE_BITS ( 32U ) + + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + uint32_t ulContext[ MAX_CONTEXT_SIZE ]; + uint32_t ulTaskFlags; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo; + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ]; + #endif + #endif + } xMPU_SETTINGS; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Validate priority of ISRs that are allowed to call FreeRTOS + * system calls. + */ +#if ( configASSERT_DEFINED == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif +#endif + +/** + * @brief SVC numbers. + */ +#define portSVC_ALLOCATE_SECURE_CONTEXT 100 +#define portSVC_FREE_SECURE_CONTEXT 101 +#define portSVC_START_SCHEDULER 102 +#define portSVC_RAISE_PRIVILEGE 103 +#define portSVC_SYSTEM_CALL_EXIT 104 +#define portSVC_YIELD 105 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) +#endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() +#else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + extern BaseType_t xPortIsTaskPrivileged( void ); + +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACROCOMMON_H */ diff --git a/portable/IAR/ARM_STAR_MC3/secure/secure_context.c b/portable/IAR/ARM_STAR_MC3/secure/secure_context.c new file mode 100644 index 000000000..3aa335e63 --- /dev/null +++ b/portable/IAR/ARM_STAR_MC3/secure/secure_context.c @@ -0,0 +1,354 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Secure context includes. */ +#include "secure_context.h" + +/* Secure heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief CONTROL value for privileged tasks. + * + * Bit[0] - 0 --> Thread mode is privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_PRIVILEGED 0x02 + +/** + * @brief CONTROL value for un-privileged tasks. + * + * Bit[0] - 1 --> Thread mode is un-privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03 + +/** + * @brief Size of stack seal values in bytes. + */ +#define securecontextSTACK_SEAL_SIZE 8 + +/** + * @brief Stack seal value as recommended by ARM. + */ +#define securecontextSTACK_SEAL_VALUE 0xFEF5EDA5 + +/** + * @brief Maximum number of secure contexts. + */ +#ifndef secureconfigMAX_SECURE_CONTEXTS + #define secureconfigMAX_SECURE_CONTEXTS 8UL +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Pre-allocated array of secure contexts. + */ +SecureContext_t xSecureContexts[ secureconfigMAX_SECURE_CONTEXTS ]; +/*-----------------------------------------------------------*/ + +/** + * @brief Get a free secure context for a task from the secure context pool (xSecureContexts). + * + * This function ensures that only one secure context is allocated for a task. + * + * @param[in] pvTaskHandle The task handle for which the secure context is allocated. + * + * @return Index of a free secure context in the xSecureContexts array. + */ +static uint32_t ulGetSecureContext( void * pvTaskHandle ); + +/** + * @brief Return the secure context to the secure context pool (xSecureContexts). + * + * @param[in] ulSecureContextIndex Index of the context in the xSecureContexts array. + */ +static void vReturnSecureContext( uint32_t ulSecureContextIndex ); + +/* These are implemented in assembly. */ +extern void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ); +extern void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ); +/*-----------------------------------------------------------*/ + +static uint32_t ulGetSecureContext( void * pvTaskHandle ) +{ + /* Start with invalid index. */ + uint32_t i, ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + if( ( xSecureContexts[ i ].pucCurrentStackPointer == NULL ) && + ( xSecureContexts[ i ].pucStackLimit == NULL ) && + ( xSecureContexts[ i ].pucStackStart == NULL ) && + ( xSecureContexts[ i ].pvTaskHandle == NULL ) && + ( ulSecureContextIndex == secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = i; + } + else if( xSecureContexts[ i ].pvTaskHandle == pvTaskHandle ) + { + /* A task can only have one secure context. Do not allocate a second + * context for the same task. */ + ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS; + break; + } + } + + return ulSecureContextIndex; +} +/*-----------------------------------------------------------*/ + +static void vReturnSecureContext( uint32_t ulSecureContextIndex ) +{ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = NULL; + xSecureContexts[ ulSecureContextIndex ].pucStackStart = NULL; + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = NULL; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) +{ + uint32_t ulIPSR, i; + static uint32_t ulSecureContextsInitialized = 0; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ( ulIPSR != 0 ) && ( ulSecureContextsInitialized == 0 ) ) + { + /* Ensure to initialize secure contexts only once. */ + ulSecureContextsInitialized = 1; + + /* No stack for thread mode until a task's context is loaded. */ + secureportSET_PSPLIM( securecontextNO_STACK ); + secureportSET_PSP( securecontextNO_STACK ); + + /* Initialize all secure contexts. */ + for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ ) + { + xSecureContexts[ i ].pucCurrentStackPointer = NULL; + xSecureContexts[ i ].pucStackLimit = NULL; + xSecureContexts[ i ].pucStackStart = NULL; + xSecureContexts[ i ].pvTaskHandle = NULL; + } + + #if ( configENABLE_MPU == 1 ) + { + /* Configure thread mode to use PSP and to be unprivileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); + } + #else /* configENABLE_MPU */ + { + /* Configure thread mode to use PSP and to be privileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); + } + #endif /* configENABLE_MPU */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ) +#else /* configENABLE_MPU */ + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ) +#endif /* configENABLE_MPU */ +{ + uint8_t * pucStackMemory = NULL; + uint8_t * pucStackLimit; + uint32_t ulIPSR, ulSecureContextIndex; + SecureContextHandle_t xSecureContextHandle = securecontextINVALID_CONTEXT_ID; + + #if ( configENABLE_MPU == 1 ) + uint32_t * pulCurrentStackPointer = NULL; + #endif /* configENABLE_MPU */ + + /* Read the Interrupt Program Status Register (IPSR) and Process Stack Limit + * Register (PSPLIM) value. */ + secureportREAD_IPSR( ulIPSR ); + secureportREAD_PSPLIM( pucStackLimit ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. + * Also do nothing, if a secure context us already loaded. PSPLIM is set to + * securecontextNO_STACK when no secure context is loaded. */ + if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) ) + { + /* Obtain a free secure context. */ + ulSecureContextIndex = ulGetSecureContext( pvTaskHandle ); + + /* Were we able to get a free context? */ + if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS ) + { + /* Allocate the stack space. */ + pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE ); + + if( pucStackMemory != NULL ) + { + /* Since stack grows down, the starting point will be the last + * location. Note that this location is next to the last + * allocated byte for stack (excluding the space for seal values) + * because the hardware decrements the stack pointer before + * writing i.e. if stack pointer is 0x2, a push operation will + * decrement the stack pointer to 0x1 and then write at 0x1. */ + xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize; + + /* Seal the created secure process stack. */ + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; + + /* The stack cannot go beyond this location. This value is + * programmed in the PSPLIM register on context switch.*/ + xSecureContexts[ ulSecureContextIndex ].pucStackLimit = pucStackMemory; + + xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle; + + #if ( configENABLE_MPU == 1 ) + { + /* Store the correct CONTROL value for the task on the stack. + * This value is programmed in the CONTROL register on + * context switch. */ + pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; + pulCurrentStackPointer--; + + if( ulIsTaskPrivileged ) + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; + } + else + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; + } + + /* Store the current stack pointer. This value is programmed in + * the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + } + #else /* configENABLE_MPU */ + { + /* Current SP is set to the starting of the stack. This + * value programmed in the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + } + #endif /* configENABLE_MPU */ + + /* Ensure to never return 0 as a valid context handle. */ + xSecureContextHandle = ulSecureContextIndex + 1UL; + } + } + } + + return xSecureContextHandle; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) +{ + uint32_t ulIPSR, ulSecureContextIndex; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* Only free if a valid context handle is passed. */ + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + /* Ensure that the secure context being deleted is associated with + * the task. */ + if( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) + { + /* Free the stack space. */ + vPortFree( xSecureContexts[ ulSecureContextIndex ].pucStackLimit ); + + /* Return the secure context back to the free secure contexts pool. */ + vReturnSecureContext( ulSecureContextIndex ); + } + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that no secure context is loaded and the task is loading it's + * own context. */ + if( ( pucStackLimit == securecontextNO_STACK ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_LoadContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) +{ + uint8_t * pucStackLimit; + uint32_t ulSecureContextIndex; + + if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) ) + { + ulSecureContextIndex = xSecureContextHandle - 1UL; + + secureportREAD_PSPLIM( pucStackLimit ); + + /* Ensure that task's context is loaded and the task is saving it's own + * context. */ + if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) && + ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) ) + { + SecureContext_SaveContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) ); + } + } +} +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/ARM_STAR_MC3/secure/secure_context.h b/portable/IAR/ARM_STAR_MC3/secure/secure_context.h new file mode 100644 index 000000000..e36a8e430 --- /dev/null +++ b/portable/IAR/ARM_STAR_MC3/secure/secure_context.h @@ -0,0 +1,138 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_CONTEXT_H__ +#define __SECURE_CONTEXT_H__ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" + +/** + * @brief PSP value when no secure context is loaded. + */ +#define securecontextNO_STACK 0x0 + +/** + * @brief Invalid context ID. + */ +#define securecontextINVALID_CONTEXT_ID 0UL +/*-----------------------------------------------------------*/ + +/** + * @brief Structure to represent a secure context. + * + * @note Since stack grows down, pucStackStart is the highest address while + * pucStackLimit is the first address of the allocated memory. + */ +typedef struct SecureContext +{ + uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */ + uint8_t * pucStackLimit; /**< Last location of the stack memory (PSPLIM). */ + uint8_t * pucStackStart; /**< First location of the stack memory. */ + void * pvTaskHandle; /**< Task handle of the task this context is associated with. */ +} SecureContext_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Opaque handle for a secure context. + */ +typedef uint32_t SecureContextHandle_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Initializes the secure context management system. + * + * PSP is set to NULL and therefore a task must allocate and load a context + * before calling any secure side function in the thread mode. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureContext_Init( void ); + +/** + * @brief Allocates a context on the secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] ulSecureStackSize Size of the stack to allocate on secure side. + * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise. + * + * @return Opaque context handle if context is successfully allocated, NULL + * otherwise. + */ +#if ( configENABLE_MPU == 1 ) + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + uint32_t ulIsTaskPrivileged, + void * pvTaskHandle ); +#else /* configENABLE_MPU */ + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, + void * pvTaskHandle ); +#endif /* configENABLE_MPU */ + +/** + * @brief Frees the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the + * context to be freed. + */ +void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); + +/** + * @brief Loads the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be loaded. + */ +void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); + +/** + * @brief Saves the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be saved. + */ +void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); + +#endif /* __SECURE_CONTEXT_H__ */ diff --git a/portable/IAR/ARM_STAR_MC3/secure/secure_context_port_asm.s b/portable/IAR/ARM_STAR_MC3/secure/secure_context_port_asm.s new file mode 100644 index 000000000..27a8f3933 --- /dev/null +++ b/portable/IAR/ARM_STAR_MC3/secure/secure_context_port_asm.s @@ -0,0 +1,86 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + SECTION .text:CODE:NOROOT(2) + THUMB + +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" + + PUBLIC SecureContext_LoadContextAsm + PUBLIC SecureContext_SaveContextAsm +/*-----------------------------------------------------------*/ + +SecureContext_LoadContextAsm: + /* pxSecureContext value is in r0. */ + mrs r1, ipsr /* r1 = IPSR. */ + cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */ + ldmia r0!, {r1, r2} /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */ + +#if ( configENABLE_MPU == 1 ) + ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL. */ + msr control, r3 /* CONTROL = r3. */ +#endif /* configENABLE_MPU */ + + msr psplim, r2 /* PSPLIM = r2. */ + msr psp, r1 /* PSP = r1. */ + + load_ctx_therad_mode: + bx lr +/*-----------------------------------------------------------*/ + +SecureContext_SaveContextAsm: + /* pxSecureContext value is in r0. */ + mrs r1, ipsr /* r1 = IPSR. */ + cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */ + mrs r1, psp /* r1 = PSP. */ + +#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + vstmdb r1!, {s0} /* Trigger the deferred stacking of FPU registers. */ + vldmia r1!, {s0} /* Nullify the effect of the previous statement. */ +#endif /* configENABLE_FPU || configENABLE_MVE */ + +#if ( configENABLE_MPU == 1 ) + mrs r2, control /* r2 = CONTROL. */ + stmdb r1!, {r2} /* Store CONTROL value on the stack. */ +#endif /* configENABLE_MPU */ + + str r1, [r0] /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */ + movs r1, #0 /* r1 = securecontextNO_STACK. */ + msr psplim, r1 /* PSPLIM = securecontextNO_STACK. */ + msr psp, r1 /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */ + + save_ctx_therad_mode: + bx lr +/*-----------------------------------------------------------*/ + + END diff --git a/portable/IAR/ARM_STAR_MC3/secure/secure_heap.c b/portable/IAR/ARM_STAR_MC3/secure/secure_heap.c new file mode 100644 index 000000000..896b53e2d --- /dev/null +++ b/portable/IAR/ARM_STAR_MC3/secure/secure_heap.c @@ -0,0 +1,485 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Configuration includes. */ +#include "FreeRTOSConfig.h" + +/* Secure context heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Total heap size. + */ +#ifndef secureconfigTOTAL_HEAP_SIZE + #define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) ) +#endif + +/* No test marker by default. */ +#ifndef mtCOVERAGE_TEST_MARKER + #define mtCOVERAGE_TEST_MARKER() +#endif + +/* No tracing by default. */ +#ifndef traceMALLOC + #define traceMALLOC( pvReturn, xWantedSize ) +#endif + +/* No tracing by default. */ +#ifndef traceFREE + #define traceFREE( pv, xBlockSize ) +#endif + +/* Block sizes must not get too small. */ +#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) ) + +/* Assumes 8bit bytes! */ +#define secureheapBITS_PER_BYTE ( ( size_t ) 8 ) + +/* Max value that fits in a size_t type. */ +#define secureheapSIZE_MAX ( ~( ( size_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define secureheapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) ) + +/* MSB of the xBlockSize member of an BlockLink_t structure is used to track + * the allocation status of a block. When MSB of the xBlockSize member of + * an BlockLink_t structure is set then the block belongs to the application. + * When the bit is free the block is still part of the free heap space. */ +#define secureheapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) ) +#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 ) +#define secureheapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 ) +#define secureheapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK ) +#define secureheapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK ) +/*-----------------------------------------------------------*/ + +/* Allocate the memory for the heap. */ +#if ( configAPPLICATION_ALLOCATED_HEAP == 1 ) + +/* The application writer has already defined the array used for the RTOS +* heap - probably so it can be placed in a special segment or address. */ + extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#else /* configAPPLICATION_ALLOCATED_HEAP */ + static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#endif /* configAPPLICATION_ALLOCATED_HEAP */ + +/** + * @brief The linked list structure. + * + * This is used to link free blocks in order of their memory address. + */ +typedef struct A_BLOCK_LINK +{ + struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */ + size_t xBlockSize; /**< The size of the free block. */ +} BlockLink_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Called automatically to setup the required heap structures the first + * time pvPortMalloc() is called. + */ +static void prvHeapInit( void ); + +/** + * @brief Inserts a block of memory that is being freed into the correct + * position in the list of free memory blocks. + * + * The block being freed will be merged with the block in front it and/or the + * block behind it if the memory blocks are adjacent to each other. + * + * @param[in] pxBlockToInsert The block being freed. + */ +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ); +/*-----------------------------------------------------------*/ + +/** + * @brief The size of the structure placed at the beginning of each allocated + * memory block must by correctly byte aligned. + */ +static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + +/** + * @brief Create a couple of list links to mark the start and end of the list. + */ +static BlockLink_t xStart; +static BlockLink_t * pxEnd = NULL; + +/** + * @brief Keeps track of the number of free bytes remaining, but says nothing + * about fragmentation. + */ +static size_t xFreeBytesRemaining = 0U; +static size_t xMinimumEverFreeBytesRemaining = 0U; + +/*-----------------------------------------------------------*/ + +static void prvHeapInit( void ) +{ + BlockLink_t * pxFirstFreeBlock; + uint8_t * pucAlignedHeap; + size_t uxAddress; + size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE; + + /* Ensure the heap starts on a correctly aligned boundary. */ + uxAddress = ( size_t ) ucHeap; + + if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 ) + { + uxAddress += ( secureportBYTE_ALIGNMENT - 1 ); + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; + } + + pucAlignedHeap = ( uint8_t * ) uxAddress; + + /* xStart is used to hold a pointer to the first item in the list of free + * blocks. The void cast is used to prevent compiler warnings. */ + xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; + xStart.xBlockSize = ( size_t ) 0; + + /* pxEnd is used to mark the end of the list of free blocks and is inserted + * at the end of the heap space. */ + uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; + uxAddress -= xHeapStructSize; + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + pxEnd = ( void * ) uxAddress; + pxEnd->xBlockSize = 0; + pxEnd->pxNextFreeBlock = NULL; + + /* To start with there is a single free block that is sized to take up the + * entire heap space, minus the space taken by pxEnd. */ + pxFirstFreeBlock = ( void * ) pucAlignedHeap; + pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; + pxFirstFreeBlock->pxNextFreeBlock = pxEnd; + + /* Only one block exists - and it covers the entire usable heap space. */ + xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; +} +/*-----------------------------------------------------------*/ + +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) +{ + BlockLink_t * pxIterator; + uint8_t * puc; + + /* Iterate through the list until a block is found that has a higher address + * than the block being inserted. */ + for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) + { + /* Nothing to do here, just iterate to the right position. */ + } + + /* Do the block being inserted, and the block it is being inserted after + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxIterator; + + if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) + { + pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; + pxBlockToInsert = pxIterator; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Do the block being inserted, and the block it is being inserted before + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxBlockToInsert; + + if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) + { + if( pxIterator->pxNextFreeBlock != pxEnd ) + { + /* Form one big block from the two blocks. */ + pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxEnd; + } + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; + } + + /* If the block being inserted plugged a gap, so was merged with the block + * before and the block after, then it's pxNextFreeBlock pointer will have + * already been set, and should not be set here as that would make it point + * to itself. */ + if( pxIterator != pxBlockToInsert ) + { + pxIterator->pxNextFreeBlock = pxBlockToInsert; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} +/*-----------------------------------------------------------*/ + +void * pvPortMalloc( size_t xWantedSize ) +{ + BlockLink_t * pxBlock; + BlockLink_t * pxPreviousBlock; + BlockLink_t * pxNewBlockLink; + void * pvReturn = NULL; + size_t xAdditionalRequiredSize; + size_t xAllocatedBlockSize = 0; + + /* If this is the first call to malloc then the heap will require + * initialisation to setup the list of free blocks. */ + if( pxEnd == NULL ) + { + prvHeapInit(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xWantedSize > 0 ) + { + /* The wanted size must be increased so it can contain a BlockLink_t + * structure in addition to the requested amount of bytes. */ + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 ) + { + xWantedSize += xHeapStructSize; + + /* Ensure that blocks are always aligned to the required number + * of bytes. */ + if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 ) + { + /* Byte alignment required. */ + xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ); + + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 ) + { + xWantedSize += xAdditionalRequiredSize; + } + else + { + xWantedSize = 0; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + xWantedSize = 0; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Check the requested block size is not so large that the top bit is set. + * The top bit of the block size member of the BlockLink_t structure is used + * to determine who owns the block - the application or the kernel, so it + * must be free. */ + if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 ) + { + if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) + { + /* Traverse the list from the start (lowest address) block until + * one of adequate size is found. */ + pxPreviousBlock = &xStart; + pxBlock = xStart.pxNextFreeBlock; + + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + { + pxPreviousBlock = pxBlock; + pxBlock = pxBlock->pxNextFreeBlock; + } + + /* If the end marker was reached then a block of adequate size was + * not found. */ + if( pxBlock != pxEnd ) + { + /* Return the memory space pointed to - jumping over the + * BlockLink_t structure at its start. */ + pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); + + /* This block is being returned for use so must be taken out + * of the list of free blocks. */ + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + + /* If the block is larger than required it can be split into + * two. */ + if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE ) + { + /* This block is to be split into two. Create a new + * block following the number of bytes requested. The void + * cast is used to prevent byte alignment warnings from the + * compiler. */ + pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); + secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + + /* Calculate the sizes of two blocks split from the single + * block. */ + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + pxBlock->xBlockSize = xWantedSize; + + /* Insert the new block into the list of free blocks. */ + pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock; + pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xFreeBytesRemaining -= pxBlock->xBlockSize; + + if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) + { + xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xAllocatedBlockSize = pxBlock->xBlockSize; + + /* The block is being returned - it is allocated and owned by + * the application and has no "next" block. */ + secureheapALLOCATE_BLOCK( pxBlock ); + pxBlock->pxNextFreeBlock = NULL; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceMALLOC( pvReturn, xAllocatedBlockSize ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xAllocatedBlockSize; + + #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) + { + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */ + + secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 ); + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void * pv ) +{ + uint8_t * puc = ( uint8_t * ) pv; + BlockLink_t * pxLink; + + if( pv != NULL ) + { + /* The memory being freed will have an BlockLink_t structure immediately + * before it. */ + puc -= xHeapStructSize; + + /* This casting is to keep the compiler from issuing warnings. */ + pxLink = ( void * ) puc; + + /* Check the block is actually allocated. */ + secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ); + secureportASSERT( pxLink->pxNextFreeBlock == NULL ); + + if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ) + { + if( pxLink->pxNextFreeBlock == NULL ) + { + /* The block is being returned to the heap - it is no longer + * allocated. */ + secureheapFREE_BLOCK( pxLink ); + + secureportDISABLE_NON_SECURE_INTERRUPTS(); + { + /* Add this block to the list of free blocks. */ + xFreeBytesRemaining += pxLink->xBlockSize; + traceFREE( pv, pxLink->xBlockSize ); + prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); + } + secureportENABLE_NON_SECURE_INTERRUPTS(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } +} +/*-----------------------------------------------------------*/ + +size_t xPortGetFreeHeapSize( void ) +{ + return xFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +size_t xPortGetMinimumEverFreeHeapSize( void ) +{ + return xMinimumEverFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/ARM_STAR_MC3/secure/secure_heap.h b/portable/IAR/ARM_STAR_MC3/secure/secure_heap.h new file mode 100644 index 000000000..0e84a9d9d --- /dev/null +++ b/portable/IAR/ARM_STAR_MC3/secure/secure_heap.h @@ -0,0 +1,66 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_HEAP_H__ +#define __SECURE_HEAP_H__ + +/* Standard includes. */ +#include + +/** + * @brief Allocates memory from heap. + * + * @param[in] xWantedSize The size of the memory to be allocated. + * + * @return Pointer to the memory region if the allocation is successful, NULL + * otherwise. + */ +void * pvPortMalloc( size_t xWantedSize ); + +/** + * @brief Frees the previously allocated memory. + * + * @param[in] pv Pointer to the memory to be freed. + */ +void vPortFree( void * pv ); + +/** + * @brief Get the free heap size. + * + * @return Free heap size. + */ +size_t xPortGetFreeHeapSize( void ); + +/** + * @brief Get the minimum ever free heap size. + * + * @return Minimum ever free heap size. + */ +size_t xPortGetMinimumEverFreeHeapSize( void ); + +#endif /* __SECURE_HEAP_H__ */ diff --git a/portable/IAR/ARM_STAR_MC3/secure/secure_init.c b/portable/IAR/ARM_STAR_MC3/secure/secure_init.c new file mode 100644 index 000000000..c50d37668 --- /dev/null +++ b/portable/IAR/ARM_STAR_MC3/secure/secure_init.c @@ -0,0 +1,106 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Secure init includes. */ +#include "secure_init.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Constants required to manipulate the SCB. + */ +#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */ +#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL ) +#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS ) +#define secureinitSCB_AIRCR_PRIS_POS ( 14UL ) +#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS ) + +/** + * @brief Constants required to manipulate the FPU. + */ +#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define secureinitFPCCR_LSPENS_POS ( 29UL ) +#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS ) +#define secureinitFPCCR_TS_POS ( 26UL ) +#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS ) + +#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */ +#define secureinitNSACR_CP10_POS ( 10UL ) +#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS ) +#define secureinitNSACR_CP11_POS ( 11UL ) +#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS ) +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) | + ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) | + ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK ); + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is + * permitted. CP11 should be programmed to the same value as CP10. */ + *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK ); + + /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures + * that we can enable/disable lazy stacking in port.c file. */ + *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK ); + + /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP + * registers (S16-S31) are also pushed to stack on exception entry and + * restored on exception return. */ + *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK ); + } +} +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/ARM_STAR_MC3/secure/secure_init.h b/portable/IAR/ARM_STAR_MC3/secure/secure_init.h new file mode 100644 index 000000000..ebe04900f --- /dev/null +++ b/portable/IAR/ARM_STAR_MC3/secure/secure_init.h @@ -0,0 +1,54 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_INIT_H__ +#define __SECURE_INIT_H__ + +/** + * @brief De-prioritizes the non-secure exceptions. + * + * This is needed to ensure that the non-secure PendSV runs at the lowest + * priority. Context switch is done in the non-secure PendSV handler. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_DePrioritizeNSExceptions( void ); + +/** + * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access. + * + * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point + * Registers are not leaked to the non-secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_EnableNSFPUAccess( void ); + +#endif /* __SECURE_INIT_H__ */ diff --git a/portable/IAR/ARM_STAR_MC3/secure/secure_port_macros.h b/portable/IAR/ARM_STAR_MC3/secure/secure_port_macros.h new file mode 100644 index 000000000..a70da2c65 --- /dev/null +++ b/portable/IAR/ARM_STAR_MC3/secure/secure_port_macros.h @@ -0,0 +1,140 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __SECURE_PORT_MACROS_H__ +#define __SECURE_PORT_MACROS_H__ + +/** + * @brief Byte alignment requirements. + */ +#define secureportBYTE_ALIGNMENT 8 +#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 ) + +/** + * @brief Macro to declare a function as non-secure callable. + */ +#if defined( __IAR_SYSTEMS_ICC__ ) + #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry __root +#else + #define secureportNON_SECURE_CALLABLE __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) ) +#endif + +/** + * @brief Set the secure PRIMASK value. + */ +#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Set the non-secure PRIMASK value. + */ +#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Read the PSP value in the given variable. + */ +#define secureportREAD_PSP( pucOutCurrentStackPointer ) \ + __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) ) + +/** + * @brief Set the PSP to the given value. + */ +#define secureportSET_PSP( pucCurrentStackPointer ) \ + __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) ) + +/** + * @brief Read the PSPLIM value in the given variable. + */ +#define secureportREAD_PSPLIM( pucOutStackLimit ) \ + __asm volatile ( "mrs %0, psplim" : "=r" ( pucOutStackLimit ) ) + +/** + * @brief Set the PSPLIM to the given value. + */ +#define secureportSET_PSPLIM( pucStackLimit ) \ + __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) ) + +/** + * @brief Set the NonSecure MSP to the given value. + */ +#define secureportSET_MSP_NS( pucMainStackPointer ) \ + __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) ) + +/** + * @brief Set the CONTROL register to the given value. + */ +#define secureportSET_CONTROL( ulControl ) \ + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" ) + +/** + * @brief Read the Interrupt Program Status Register (IPSR) value in the given + * variable. + */ +#define secureportREAD_IPSR( ulIPSR ) \ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) ) + +/** + * @brief PRIMASK value to enable interrupts. + */ +#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0 + +/** + * @brief PRIMASK value to disable interrupts. + */ +#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1 + +/** + * @brief Disable secure interrupts. + */ +#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Disable non-secure interrupts. + * + * This effectively disables context switches. + */ +#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Enable non-secure interrupts. + */ +#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL ) + +/** + * @brief Assert definition. + */ +#define secureportASSERT( x ) \ + if( ( x ) == 0 ) \ + { \ + secureportDISABLE_SECURE_INTERRUPTS(); \ + secureportDISABLE_NON_SECURE_INTERRUPTS(); \ + for( ; ; ) {; } \ + } + +#endif /* __SECURE_PORT_MACROS_H__ */ diff --git a/portable/IAR/ARM_STAR_MC3_NTZ/non_secure/mpu_wrappers_v2_asm.S b/portable/IAR/ARM_STAR_MC3_NTZ/non_secure/mpu_wrappers_v2_asm.S new file mode 100644 index 000000000..d2cb78e92 --- /dev/null +++ b/portable/IAR/ARM_STAR_MC3_NTZ/non_secure/mpu_wrappers_v2_asm.S @@ -0,0 +1,1242 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + + SECTION freertos_system_calls:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +#include "FreeRTOSConfig.h" +#include "mpu_syscall_numbers.h" + +#ifndef configUSE_MPU_WRAPPERS_V1 + #define configUSE_MPU_WRAPPERS_V1 0 +#endif + +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + PUBLIC MPU_xTaskDelayUntil +MPU_xTaskDelayUntil: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskDelayUntil_Unpriv + MPU_xTaskDelayUntil_Priv: + b MPU_xTaskDelayUntilImpl + MPU_xTaskDelayUntil_Unpriv: + svc #SYSTEM_CALL_xTaskDelayUntil +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskAbortDelay +MPU_xTaskAbortDelay: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskAbortDelay_Unpriv + MPU_xTaskAbortDelay_Priv: + b MPU_xTaskAbortDelayImpl + MPU_xTaskAbortDelay_Unpriv: + svc #SYSTEM_CALL_xTaskAbortDelay +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskDelay +MPU_vTaskDelay: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskDelay_Unpriv + MPU_vTaskDelay_Priv: + b MPU_vTaskDelayImpl + MPU_vTaskDelay_Unpriv: + svc #SYSTEM_CALL_vTaskDelay +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskPriorityGet +MPU_uxTaskPriorityGet: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskPriorityGet_Unpriv + MPU_uxTaskPriorityGet_Priv: + b MPU_uxTaskPriorityGetImpl + MPU_uxTaskPriorityGet_Unpriv: + svc #SYSTEM_CALL_uxTaskPriorityGet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_eTaskGetState +MPU_eTaskGetState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_eTaskGetState_Unpriv + MPU_eTaskGetState_Priv: + b MPU_eTaskGetStateImpl + MPU_eTaskGetState_Unpriv: + svc #SYSTEM_CALL_eTaskGetState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskGetInfo +MPU_vTaskGetInfo: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskGetInfo_Unpriv + MPU_vTaskGetInfo_Priv: + b MPU_vTaskGetInfoImpl + MPU_vTaskGetInfo_Unpriv: + svc #SYSTEM_CALL_vTaskGetInfo +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetIdleTaskHandle +MPU_xTaskGetIdleTaskHandle: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetIdleTaskHandle_Unpriv + MPU_xTaskGetIdleTaskHandle_Priv: + b MPU_xTaskGetIdleTaskHandleImpl + MPU_xTaskGetIdleTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTaskGetIdleTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSuspend +MPU_vTaskSuspend: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSuspend_Unpriv + MPU_vTaskSuspend_Priv: + b MPU_vTaskSuspendImpl + MPU_vTaskSuspend_Unpriv: + svc #SYSTEM_CALL_vTaskSuspend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskResume +MPU_vTaskResume: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskResume_Unpriv + MPU_vTaskResume_Priv: + b MPU_vTaskResumeImpl + MPU_vTaskResume_Unpriv: + svc #SYSTEM_CALL_vTaskResume +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetTickCount +MPU_xTaskGetTickCount: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetTickCount_Unpriv + MPU_xTaskGetTickCount_Priv: + b MPU_xTaskGetTickCountImpl + MPU_xTaskGetTickCount_Unpriv: + svc #SYSTEM_CALL_xTaskGetTickCount +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetNumberOfTasks +MPU_uxTaskGetNumberOfTasks: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetNumberOfTasks_Unpriv + MPU_uxTaskGetNumberOfTasks_Priv: + b MPU_uxTaskGetNumberOfTasksImpl + MPU_uxTaskGetNumberOfTasks_Unpriv: + svc #SYSTEM_CALL_uxTaskGetNumberOfTasks +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetRunTimeCounter +MPU_ulTaskGetRunTimeCounter: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetRunTimeCounter_Unpriv + MPU_ulTaskGetRunTimeCounter_Priv: + b MPU_ulTaskGetRunTimeCounterImpl + MPU_ulTaskGetRunTimeCounter_Unpriv: + svc #SYSTEM_CALL_ulTaskGetRunTimeCounter +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetRunTimePercent +MPU_ulTaskGetRunTimePercent: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetRunTimePercent_Unpriv + MPU_ulTaskGetRunTimePercent_Priv: + b MPU_ulTaskGetRunTimePercentImpl + MPU_ulTaskGetRunTimePercent_Unpriv: + svc #SYSTEM_CALL_ulTaskGetRunTimePercent +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetIdleRunTimePercent +MPU_ulTaskGetIdleRunTimePercent: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetIdleRunTimePercent_Unpriv + MPU_ulTaskGetIdleRunTimePercent_Priv: + b MPU_ulTaskGetIdleRunTimePercentImpl + MPU_ulTaskGetIdleRunTimePercent_Unpriv: + svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGetIdleRunTimeCounter +MPU_ulTaskGetIdleRunTimeCounter: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv + MPU_ulTaskGetIdleRunTimeCounter_Priv: + b MPU_ulTaskGetIdleRunTimeCounterImpl + MPU_ulTaskGetIdleRunTimeCounter_Unpriv: + svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetApplicationTaskTag +MPU_vTaskSetApplicationTaskTag: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetApplicationTaskTag_Unpriv + MPU_vTaskSetApplicationTaskTag_Priv: + b MPU_vTaskSetApplicationTaskTagImpl + MPU_vTaskSetApplicationTaskTag_Unpriv: + svc #SYSTEM_CALL_vTaskSetApplicationTaskTag +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetApplicationTaskTag +MPU_xTaskGetApplicationTaskTag: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetApplicationTaskTag_Unpriv + MPU_xTaskGetApplicationTaskTag_Priv: + b MPU_xTaskGetApplicationTaskTagImpl + MPU_xTaskGetApplicationTaskTag_Unpriv: + svc #SYSTEM_CALL_xTaskGetApplicationTaskTag +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetThreadLocalStoragePointer +MPU_vTaskSetThreadLocalStoragePointer: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv + MPU_vTaskSetThreadLocalStoragePointer_Priv: + b MPU_vTaskSetThreadLocalStoragePointerImpl + MPU_vTaskSetThreadLocalStoragePointer_Unpriv: + svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pvTaskGetThreadLocalStoragePointer +MPU_pvTaskGetThreadLocalStoragePointer: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv + MPU_pvTaskGetThreadLocalStoragePointer_Priv: + b MPU_pvTaskGetThreadLocalStoragePointerImpl + MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: + svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetSystemState +MPU_uxTaskGetSystemState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetSystemState_Unpriv + MPU_uxTaskGetSystemState_Priv: + b MPU_uxTaskGetSystemStateImpl + MPU_uxTaskGetSystemState_Unpriv: + svc #SYSTEM_CALL_uxTaskGetSystemState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetStackHighWaterMark +MPU_uxTaskGetStackHighWaterMark: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetStackHighWaterMark_Unpriv + MPU_uxTaskGetStackHighWaterMark_Priv: + b MPU_uxTaskGetStackHighWaterMarkImpl + MPU_uxTaskGetStackHighWaterMark_Unpriv: + svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTaskGetStackHighWaterMark2 +MPU_uxTaskGetStackHighWaterMark2: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetStackHighWaterMark2_Unpriv + MPU_uxTaskGetStackHighWaterMark2_Priv: + b MPU_uxTaskGetStackHighWaterMark2Impl + MPU_uxTaskGetStackHighWaterMark2_Unpriv: + svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2 +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetCurrentTaskHandle +MPU_xTaskGetCurrentTaskHandle: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetCurrentTaskHandle_Unpriv + MPU_xTaskGetCurrentTaskHandle_Priv: + b MPU_xTaskGetCurrentTaskHandleImpl + MPU_xTaskGetCurrentTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGetSchedulerState +MPU_xTaskGetSchedulerState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetSchedulerState_Unpriv + MPU_xTaskGetSchedulerState_Priv: + b MPU_xTaskGetSchedulerStateImpl + MPU_xTaskGetSchedulerState_Unpriv: + svc #SYSTEM_CALL_xTaskGetSchedulerState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTaskSetTimeOutState +MPU_vTaskSetTimeOutState: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetTimeOutState_Unpriv + MPU_vTaskSetTimeOutState_Priv: + b MPU_vTaskSetTimeOutStateImpl + MPU_vTaskSetTimeOutState_Unpriv: + svc #SYSTEM_CALL_vTaskSetTimeOutState +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskCheckForTimeOut +MPU_xTaskCheckForTimeOut: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskCheckForTimeOut_Unpriv + MPU_xTaskCheckForTimeOut_Priv: + b MPU_xTaskCheckForTimeOutImpl + MPU_xTaskCheckForTimeOut_Unpriv: + svc #SYSTEM_CALL_xTaskCheckForTimeOut +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyEntry +MPU_xTaskGenericNotifyEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotify_Unpriv + MPU_xTaskGenericNotify_Priv: + b MPU_xTaskGenericNotifyImpl + MPU_xTaskGenericNotify_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotify +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyWaitEntry +MPU_xTaskGenericNotifyWaitEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotifyWait_Unpriv + MPU_xTaskGenericNotifyWait_Priv: + b MPU_xTaskGenericNotifyWaitImpl + MPU_xTaskGenericNotifyWait_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotifyWait +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGenericNotifyTake +MPU_ulTaskGenericNotifyTake: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGenericNotifyTake_Unpriv + MPU_ulTaskGenericNotifyTake_Priv: + b MPU_ulTaskGenericNotifyTakeImpl + MPU_ulTaskGenericNotifyTake_Unpriv: + svc #SYSTEM_CALL_ulTaskGenericNotifyTake +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTaskGenericNotifyStateClear +MPU_xTaskGenericNotifyStateClear: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotifyStateClear_Unpriv + MPU_xTaskGenericNotifyStateClear_Priv: + b MPU_xTaskGenericNotifyStateClearImpl + MPU_xTaskGenericNotifyStateClear_Unpriv: + svc #SYSTEM_CALL_xTaskGenericNotifyStateClear +/*-----------------------------------------------------------*/ + + PUBLIC MPU_ulTaskGenericNotifyValueClear +MPU_ulTaskGenericNotifyValueClear: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGenericNotifyValueClear_Unpriv + MPU_ulTaskGenericNotifyValueClear_Priv: + b MPU_ulTaskGenericNotifyValueClearImpl + MPU_ulTaskGenericNotifyValueClear_Unpriv: + svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGenericSend +MPU_xQueueGenericSend: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGenericSend_Unpriv + MPU_xQueueGenericSend_Priv: + b MPU_xQueueGenericSendImpl + MPU_xQueueGenericSend_Unpriv: + svc #SYSTEM_CALL_xQueueGenericSend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxQueueMessagesWaiting +MPU_uxQueueMessagesWaiting: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxQueueMessagesWaiting_Unpriv + MPU_uxQueueMessagesWaiting_Priv: + b MPU_uxQueueMessagesWaitingImpl + MPU_uxQueueMessagesWaiting_Unpriv: + svc #SYSTEM_CALL_uxQueueMessagesWaiting +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxQueueSpacesAvailable +MPU_uxQueueSpacesAvailable: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxQueueSpacesAvailable_Unpriv + MPU_uxQueueSpacesAvailable_Priv: + b MPU_uxQueueSpacesAvailableImpl + MPU_uxQueueSpacesAvailable_Unpriv: + svc #SYSTEM_CALL_uxQueueSpacesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueReceive +MPU_xQueueReceive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueReceive_Unpriv + MPU_xQueueReceive_Priv: + b MPU_xQueueReceiveImpl + MPU_xQueueReceive_Unpriv: + svc #SYSTEM_CALL_xQueueReceive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueuePeek +MPU_xQueuePeek: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueuePeek_Unpriv + MPU_xQueuePeek_Priv: + b MPU_xQueuePeekImpl + MPU_xQueuePeek_Unpriv: + svc #SYSTEM_CALL_xQueuePeek +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueSemaphoreTake +MPU_xQueueSemaphoreTake: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueSemaphoreTake_Unpriv + MPU_xQueueSemaphoreTake_Priv: + b MPU_xQueueSemaphoreTakeImpl + MPU_xQueueSemaphoreTake_Unpriv: + svc #SYSTEM_CALL_xQueueSemaphoreTake +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGetMutexHolder +MPU_xQueueGetMutexHolder: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGetMutexHolder_Unpriv + MPU_xQueueGetMutexHolder_Priv: + b MPU_xQueueGetMutexHolderImpl + MPU_xQueueGetMutexHolder_Unpriv: + svc #SYSTEM_CALL_xQueueGetMutexHolder +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueTakeMutexRecursive +MPU_xQueueTakeMutexRecursive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueTakeMutexRecursive_Unpriv + MPU_xQueueTakeMutexRecursive_Priv: + b MPU_xQueueTakeMutexRecursiveImpl + MPU_xQueueTakeMutexRecursive_Unpriv: + svc #SYSTEM_CALL_xQueueTakeMutexRecursive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueGiveMutexRecursive +MPU_xQueueGiveMutexRecursive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGiveMutexRecursive_Unpriv + MPU_xQueueGiveMutexRecursive_Priv: + b MPU_xQueueGiveMutexRecursiveImpl + MPU_xQueueGiveMutexRecursive_Unpriv: + svc #SYSTEM_CALL_xQueueGiveMutexRecursive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueSelectFromSet +MPU_xQueueSelectFromSet: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueSelectFromSet_Unpriv + MPU_xQueueSelectFromSet_Priv: + b MPU_xQueueSelectFromSetImpl + MPU_xQueueSelectFromSet_Unpriv: + svc #SYSTEM_CALL_xQueueSelectFromSet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xQueueAddToSet +MPU_xQueueAddToSet: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueAddToSet_Unpriv + MPU_xQueueAddToSet_Priv: + b MPU_xQueueAddToSetImpl + MPU_xQueueAddToSet_Unpriv: + svc #SYSTEM_CALL_xQueueAddToSet +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vQueueAddToRegistry +MPU_vQueueAddToRegistry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vQueueAddToRegistry_Unpriv + MPU_vQueueAddToRegistry_Priv: + b MPU_vQueueAddToRegistryImpl + MPU_vQueueAddToRegistry_Unpriv: + svc #SYSTEM_CALL_vQueueAddToRegistry +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vQueueUnregisterQueue +MPU_vQueueUnregisterQueue: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vQueueUnregisterQueue_Unpriv + MPU_vQueueUnregisterQueue_Priv: + b MPU_vQueueUnregisterQueueImpl + MPU_vQueueUnregisterQueue_Unpriv: + svc #SYSTEM_CALL_vQueueUnregisterQueue +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pcQueueGetName +MPU_pcQueueGetName: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pcQueueGetName_Unpriv + MPU_pcQueueGetName_Priv: + b MPU_pcQueueGetNameImpl + MPU_pcQueueGetName_Unpriv: + svc #SYSTEM_CALL_pcQueueGetName +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pvTimerGetTimerID +MPU_pvTimerGetTimerID: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pvTimerGetTimerID_Unpriv + MPU_pvTimerGetTimerID_Priv: + b MPU_pvTimerGetTimerIDImpl + MPU_pvTimerGetTimerID_Unpriv: + svc #SYSTEM_CALL_pvTimerGetTimerID +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTimerSetTimerID +MPU_vTimerSetTimerID: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTimerSetTimerID_Unpriv + MPU_vTimerSetTimerID_Priv: + b MPU_vTimerSetTimerIDImpl + MPU_vTimerSetTimerID_Unpriv: + svc #SYSTEM_CALL_vTimerSetTimerID +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerIsTimerActive +MPU_xTimerIsTimerActive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerIsTimerActive_Unpriv + MPU_xTimerIsTimerActive_Priv: + b MPU_xTimerIsTimerActiveImpl + MPU_xTimerIsTimerActive_Unpriv: + svc #SYSTEM_CALL_xTimerIsTimerActive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetTimerDaemonTaskHandle +MPU_xTimerGetTimerDaemonTaskHandle: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv + MPU_xTimerGetTimerDaemonTaskHandle_Priv: + b MPU_xTimerGetTimerDaemonTaskHandleImpl + MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: + svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGenericCommandFromTaskEntry +MPU_xTimerGenericCommandFromTaskEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGenericCommandFromTask_Unpriv + MPU_xTimerGenericCommandFromTask_Priv: + b MPU_xTimerGenericCommandFromTaskImpl + MPU_xTimerGenericCommandFromTask_Unpriv: + svc #SYSTEM_CALL_xTimerGenericCommandFromTask +/*-----------------------------------------------------------*/ + + PUBLIC MPU_pcTimerGetName +MPU_pcTimerGetName: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pcTimerGetName_Unpriv + MPU_pcTimerGetName_Priv: + b MPU_pcTimerGetNameImpl + MPU_pcTimerGetName_Unpriv: + svc #SYSTEM_CALL_pcTimerGetName +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vTimerSetReloadMode +MPU_vTimerSetReloadMode: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTimerSetReloadMode_Unpriv + MPU_vTimerSetReloadMode_Priv: + b MPU_vTimerSetReloadModeImpl + MPU_vTimerSetReloadMode_Unpriv: + svc #SYSTEM_CALL_vTimerSetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetReloadMode +MPU_xTimerGetReloadMode: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetReloadMode_Unpriv + MPU_xTimerGetReloadMode_Priv: + b MPU_xTimerGetReloadModeImpl + MPU_xTimerGetReloadMode_Unpriv: + svc #SYSTEM_CALL_xTimerGetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxTimerGetReloadMode +MPU_uxTimerGetReloadMode: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTimerGetReloadMode_Unpriv + MPU_uxTimerGetReloadMode_Priv: + b MPU_uxTimerGetReloadModeImpl + MPU_uxTimerGetReloadMode_Unpriv: + svc #SYSTEM_CALL_uxTimerGetReloadMode +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetPeriod +MPU_xTimerGetPeriod: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetPeriod_Unpriv + MPU_xTimerGetPeriod_Priv: + b MPU_xTimerGetPeriodImpl + MPU_xTimerGetPeriod_Unpriv: + svc #SYSTEM_CALL_xTimerGetPeriod +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xTimerGetExpiryTime +MPU_xTimerGetExpiryTime: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetExpiryTime_Unpriv + MPU_xTimerGetExpiryTime_Priv: + b MPU_xTimerGetExpiryTimeImpl + MPU_xTimerGetExpiryTime_Unpriv: + svc #SYSTEM_CALL_xTimerGetExpiryTime +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupWaitBitsEntry +MPU_xEventGroupWaitBitsEntry: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupWaitBits_Unpriv + MPU_xEventGroupWaitBits_Priv: + b MPU_xEventGroupWaitBitsImpl + MPU_xEventGroupWaitBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupWaitBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupClearBits +MPU_xEventGroupClearBits: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupClearBits_Unpriv + MPU_xEventGroupClearBits_Priv: + b MPU_xEventGroupClearBitsImpl + MPU_xEventGroupClearBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupClearBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupSetBits +MPU_xEventGroupSetBits: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupSetBits_Unpriv + MPU_xEventGroupSetBits_Priv: + b MPU_xEventGroupSetBitsImpl + MPU_xEventGroupSetBits_Unpriv: + svc #SYSTEM_CALL_xEventGroupSetBits +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xEventGroupSync +MPU_xEventGroupSync: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupSync_Unpriv + MPU_xEventGroupSync_Priv: + b MPU_xEventGroupSyncImpl + MPU_xEventGroupSync_Unpriv: + svc #SYSTEM_CALL_xEventGroupSync +/*-----------------------------------------------------------*/ + + PUBLIC MPU_uxEventGroupGetNumber +MPU_uxEventGroupGetNumber: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxEventGroupGetNumber_Unpriv + MPU_uxEventGroupGetNumber_Priv: + b MPU_uxEventGroupGetNumberImpl + MPU_uxEventGroupGetNumber_Unpriv: + svc #SYSTEM_CALL_uxEventGroupGetNumber +/*-----------------------------------------------------------*/ + + PUBLIC MPU_vEventGroupSetNumber +MPU_vEventGroupSetNumber: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vEventGroupSetNumber_Unpriv + MPU_vEventGroupSetNumber_Priv: + b MPU_vEventGroupSetNumberImpl + MPU_vEventGroupSetNumber_Unpriv: + svc #SYSTEM_CALL_vEventGroupSetNumber +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSend +MPU_xStreamBufferSend: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSend_Unpriv + MPU_xStreamBufferSend_Priv: + b MPU_xStreamBufferSendImpl + MPU_xStreamBufferSend_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSend +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferReceive +MPU_xStreamBufferReceive: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferReceive_Unpriv + MPU_xStreamBufferReceive_Priv: + b MPU_xStreamBufferReceiveImpl + MPU_xStreamBufferReceive_Unpriv: + svc #SYSTEM_CALL_xStreamBufferReceive +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferIsFull +MPU_xStreamBufferIsFull: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferIsFull_Unpriv + MPU_xStreamBufferIsFull_Priv: + b MPU_xStreamBufferIsFullImpl + MPU_xStreamBufferIsFull_Unpriv: + svc #SYSTEM_CALL_xStreamBufferIsFull +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferIsEmpty +MPU_xStreamBufferIsEmpty: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferIsEmpty_Unpriv + MPU_xStreamBufferIsEmpty_Priv: + b MPU_xStreamBufferIsEmptyImpl + MPU_xStreamBufferIsEmpty_Unpriv: + svc #SYSTEM_CALL_xStreamBufferIsEmpty +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSpacesAvailable +MPU_xStreamBufferSpacesAvailable: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSpacesAvailable_Unpriv + MPU_xStreamBufferSpacesAvailable_Priv: + b MPU_xStreamBufferSpacesAvailableImpl + MPU_xStreamBufferSpacesAvailable_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSpacesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferBytesAvailable +MPU_xStreamBufferBytesAvailable: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferBytesAvailable_Unpriv + MPU_xStreamBufferBytesAvailable_Priv: + b MPU_xStreamBufferBytesAvailableImpl + MPU_xStreamBufferBytesAvailable_Unpriv: + svc #SYSTEM_CALL_xStreamBufferBytesAvailable +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferSetTriggerLevel +MPU_xStreamBufferSetTriggerLevel: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSetTriggerLevel_Unpriv + MPU_xStreamBufferSetTriggerLevel_Priv: + b MPU_xStreamBufferSetTriggerLevelImpl + MPU_xStreamBufferSetTriggerLevel_Unpriv: + svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel +/*-----------------------------------------------------------*/ + + PUBLIC MPU_xStreamBufferNextMessageLengthBytes +MPU_xStreamBufferNextMessageLengthBytes: + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv + MPU_xStreamBufferNextMessageLengthBytes_Priv: + b MPU_xStreamBufferNextMessageLengthBytesImpl + MPU_xStreamBufferNextMessageLengthBytes_Unpriv: + svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes +/*-----------------------------------------------------------*/ + +/* Default weak implementations in case one is not available from + * mpu_wrappers because of config options. */ + + PUBWEAK MPU_xTaskDelayUntilImpl +MPU_xTaskDelayUntilImpl: + b MPU_xTaskDelayUntilImpl + + PUBWEAK MPU_xTaskAbortDelayImpl +MPU_xTaskAbortDelayImpl: + b MPU_xTaskAbortDelayImpl + + PUBWEAK MPU_vTaskDelayImpl +MPU_vTaskDelayImpl: + b MPU_vTaskDelayImpl + + PUBWEAK MPU_uxTaskPriorityGetImpl +MPU_uxTaskPriorityGetImpl: + b MPU_uxTaskPriorityGetImpl + + PUBWEAK MPU_eTaskGetStateImpl +MPU_eTaskGetStateImpl: + b MPU_eTaskGetStateImpl + + PUBWEAK MPU_vTaskGetInfoImpl +MPU_vTaskGetInfoImpl: + b MPU_vTaskGetInfoImpl + + PUBWEAK MPU_xTaskGetIdleTaskHandleImpl +MPU_xTaskGetIdleTaskHandleImpl: + b MPU_xTaskGetIdleTaskHandleImpl + + PUBWEAK MPU_vTaskSuspendImpl +MPU_vTaskSuspendImpl: + b MPU_vTaskSuspendImpl + + PUBWEAK MPU_vTaskResumeImpl +MPU_vTaskResumeImpl: + b MPU_vTaskResumeImpl + + PUBWEAK MPU_xTaskGetTickCountImpl +MPU_xTaskGetTickCountImpl: + b MPU_xTaskGetTickCountImpl + + PUBWEAK MPU_uxTaskGetNumberOfTasksImpl +MPU_uxTaskGetNumberOfTasksImpl: + b MPU_uxTaskGetNumberOfTasksImpl + + PUBWEAK MPU_ulTaskGetRunTimeCounterImpl +MPU_ulTaskGetRunTimeCounterImpl: + b MPU_ulTaskGetRunTimeCounterImpl + + PUBWEAK MPU_ulTaskGetRunTimePercentImpl +MPU_ulTaskGetRunTimePercentImpl: + b MPU_ulTaskGetRunTimePercentImpl + + PUBWEAK MPU_ulTaskGetIdleRunTimePercentImpl +MPU_ulTaskGetIdleRunTimePercentImpl: + b MPU_ulTaskGetIdleRunTimePercentImpl + + PUBWEAK MPU_ulTaskGetIdleRunTimeCounterImpl +MPU_ulTaskGetIdleRunTimeCounterImpl: + b MPU_ulTaskGetIdleRunTimeCounterImpl + + PUBWEAK MPU_vTaskSetApplicationTaskTagImpl +MPU_vTaskSetApplicationTaskTagImpl: + b MPU_vTaskSetApplicationTaskTagImpl + + PUBWEAK MPU_xTaskGetApplicationTaskTagImpl +MPU_xTaskGetApplicationTaskTagImpl: + b MPU_xTaskGetApplicationTaskTagImpl + + PUBWEAK MPU_vTaskSetThreadLocalStoragePointerImpl +MPU_vTaskSetThreadLocalStoragePointerImpl: + b MPU_vTaskSetThreadLocalStoragePointerImpl + + PUBWEAK MPU_pvTaskGetThreadLocalStoragePointerImpl +MPU_pvTaskGetThreadLocalStoragePointerImpl: + b MPU_pvTaskGetThreadLocalStoragePointerImpl + + PUBWEAK MPU_uxTaskGetSystemStateImpl +MPU_uxTaskGetSystemStateImpl: + b MPU_uxTaskGetSystemStateImpl + + PUBWEAK MPU_uxTaskGetStackHighWaterMarkImpl +MPU_uxTaskGetStackHighWaterMarkImpl: + b MPU_uxTaskGetStackHighWaterMarkImpl + + PUBWEAK MPU_uxTaskGetStackHighWaterMark2Impl +MPU_uxTaskGetStackHighWaterMark2Impl: + b MPU_uxTaskGetStackHighWaterMark2Impl + + PUBWEAK MPU_xTaskGetCurrentTaskHandleImpl +MPU_xTaskGetCurrentTaskHandleImpl: + b MPU_xTaskGetCurrentTaskHandleImpl + + PUBWEAK MPU_xTaskGetSchedulerStateImpl +MPU_xTaskGetSchedulerStateImpl: + b MPU_xTaskGetSchedulerStateImpl + + PUBWEAK MPU_vTaskSetTimeOutStateImpl +MPU_vTaskSetTimeOutStateImpl: + b MPU_vTaskSetTimeOutStateImpl + + PUBWEAK MPU_xTaskCheckForTimeOutImpl +MPU_xTaskCheckForTimeOutImpl: + b MPU_xTaskCheckForTimeOutImpl + + PUBWEAK MPU_xTaskGenericNotifyImpl +MPU_xTaskGenericNotifyImpl: + b MPU_xTaskGenericNotifyImpl + + PUBWEAK MPU_xTaskGenericNotifyWaitImpl +MPU_xTaskGenericNotifyWaitImpl: + b MPU_xTaskGenericNotifyWaitImpl + + PUBWEAK MPU_ulTaskGenericNotifyTakeImpl +MPU_ulTaskGenericNotifyTakeImpl: + b MPU_ulTaskGenericNotifyTakeImpl + + PUBWEAK MPU_xTaskGenericNotifyStateClearImpl +MPU_xTaskGenericNotifyStateClearImpl: + b MPU_xTaskGenericNotifyStateClearImpl + + PUBWEAK MPU_ulTaskGenericNotifyValueClearImpl +MPU_ulTaskGenericNotifyValueClearImpl: + b MPU_ulTaskGenericNotifyValueClearImpl + + PUBWEAK MPU_xQueueGenericSendImpl +MPU_xQueueGenericSendImpl: + b MPU_xQueueGenericSendImpl + + PUBWEAK MPU_uxQueueMessagesWaitingImpl +MPU_uxQueueMessagesWaitingImpl: + b MPU_uxQueueMessagesWaitingImpl + + PUBWEAK MPU_uxQueueSpacesAvailableImpl +MPU_uxQueueSpacesAvailableImpl: + b MPU_uxQueueSpacesAvailableImpl + + PUBWEAK MPU_xQueueReceiveImpl +MPU_xQueueReceiveImpl: + b MPU_xQueueReceiveImpl + + PUBWEAK MPU_xQueuePeekImpl +MPU_xQueuePeekImpl: + b MPU_xQueuePeekImpl + + PUBWEAK MPU_xQueueSemaphoreTakeImpl +MPU_xQueueSemaphoreTakeImpl: + b MPU_xQueueSemaphoreTakeImpl + + PUBWEAK MPU_xQueueGetMutexHolderImpl +MPU_xQueueGetMutexHolderImpl: + b MPU_xQueueGetMutexHolderImpl + + PUBWEAK MPU_xQueueTakeMutexRecursiveImpl +MPU_xQueueTakeMutexRecursiveImpl: + b MPU_xQueueTakeMutexRecursiveImpl + + PUBWEAK MPU_xQueueGiveMutexRecursiveImpl +MPU_xQueueGiveMutexRecursiveImpl: + b MPU_xQueueGiveMutexRecursiveImpl + + PUBWEAK MPU_xQueueSelectFromSetImpl +MPU_xQueueSelectFromSetImpl: + b MPU_xQueueSelectFromSetImpl + + PUBWEAK MPU_xQueueAddToSetImpl +MPU_xQueueAddToSetImpl: + b MPU_xQueueAddToSetImpl + + PUBWEAK MPU_vQueueAddToRegistryImpl +MPU_vQueueAddToRegistryImpl: + b MPU_vQueueAddToRegistryImpl + + PUBWEAK MPU_vQueueUnregisterQueueImpl +MPU_vQueueUnregisterQueueImpl: + b MPU_vQueueUnregisterQueueImpl + + PUBWEAK MPU_pcQueueGetNameImpl +MPU_pcQueueGetNameImpl: + b MPU_pcQueueGetNameImpl + + PUBWEAK MPU_pvTimerGetTimerIDImpl +MPU_pvTimerGetTimerIDImpl: + b MPU_pvTimerGetTimerIDImpl + + PUBWEAK MPU_vTimerSetTimerIDImpl +MPU_vTimerSetTimerIDImpl: + b MPU_vTimerSetTimerIDImpl + + PUBWEAK MPU_xTimerIsTimerActiveImpl +MPU_xTimerIsTimerActiveImpl: + b MPU_xTimerIsTimerActiveImpl + + PUBWEAK MPU_xTimerGetTimerDaemonTaskHandleImpl +MPU_xTimerGetTimerDaemonTaskHandleImpl: + b MPU_xTimerGetTimerDaemonTaskHandleImpl + + PUBWEAK MPU_xTimerGenericCommandFromTaskImpl +MPU_xTimerGenericCommandFromTaskImpl: + b MPU_xTimerGenericCommandFromTaskImpl + + PUBWEAK MPU_pcTimerGetNameImpl +MPU_pcTimerGetNameImpl: + b MPU_pcTimerGetNameImpl + + PUBWEAK MPU_vTimerSetReloadModeImpl +MPU_vTimerSetReloadModeImpl: + b MPU_vTimerSetReloadModeImpl + + PUBWEAK MPU_xTimerGetReloadModeImpl +MPU_xTimerGetReloadModeImpl: + b MPU_xTimerGetReloadModeImpl + + PUBWEAK MPU_uxTimerGetReloadModeImpl +MPU_uxTimerGetReloadModeImpl: + b MPU_uxTimerGetReloadModeImpl + + PUBWEAK MPU_xTimerGetPeriodImpl +MPU_xTimerGetPeriodImpl: + b MPU_xTimerGetPeriodImpl + + PUBWEAK MPU_xTimerGetExpiryTimeImpl +MPU_xTimerGetExpiryTimeImpl: + b MPU_xTimerGetExpiryTimeImpl + + PUBWEAK MPU_xEventGroupWaitBitsImpl +MPU_xEventGroupWaitBitsImpl: + b MPU_xEventGroupWaitBitsImpl + + PUBWEAK MPU_xEventGroupClearBitsImpl +MPU_xEventGroupClearBitsImpl: + b MPU_xEventGroupClearBitsImpl + + PUBWEAK MPU_xEventGroupSetBitsImpl +MPU_xEventGroupSetBitsImpl: + b MPU_xEventGroupSetBitsImpl + + PUBWEAK MPU_xEventGroupSyncImpl +MPU_xEventGroupSyncImpl: + b MPU_xEventGroupSyncImpl + + PUBWEAK MPU_uxEventGroupGetNumberImpl +MPU_uxEventGroupGetNumberImpl: + b MPU_uxEventGroupGetNumberImpl + + PUBWEAK MPU_vEventGroupSetNumberImpl +MPU_vEventGroupSetNumberImpl: + b MPU_vEventGroupSetNumberImpl + + PUBWEAK MPU_xStreamBufferSendImpl +MPU_xStreamBufferSendImpl: + b MPU_xStreamBufferSendImpl + + PUBWEAK MPU_xStreamBufferReceiveImpl +MPU_xStreamBufferReceiveImpl: + b MPU_xStreamBufferReceiveImpl + + PUBWEAK MPU_xStreamBufferIsFullImpl +MPU_xStreamBufferIsFullImpl: + b MPU_xStreamBufferIsFullImpl + + PUBWEAK MPU_xStreamBufferIsEmptyImpl +MPU_xStreamBufferIsEmptyImpl: + b MPU_xStreamBufferIsEmptyImpl + + PUBWEAK MPU_xStreamBufferSpacesAvailableImpl +MPU_xStreamBufferSpacesAvailableImpl: + b MPU_xStreamBufferSpacesAvailableImpl + + PUBWEAK MPU_xStreamBufferBytesAvailableImpl +MPU_xStreamBufferBytesAvailableImpl: + b MPU_xStreamBufferBytesAvailableImpl + + PUBWEAK MPU_xStreamBufferSetTriggerLevelImpl +MPU_xStreamBufferSetTriggerLevelImpl: + b MPU_xStreamBufferSetTriggerLevelImpl + + PUBWEAK MPU_xStreamBufferNextMessageLengthBytesImpl +MPU_xStreamBufferNextMessageLengthBytesImpl: + b MPU_xStreamBufferNextMessageLengthBytesImpl + +/*-----------------------------------------------------------*/ + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + END diff --git a/portable/IAR/ARM_STAR_MC3_NTZ/non_secure/port.c b/portable/IAR/ARM_STAR_MC3_NTZ/non_secure/port.c new file mode 100644 index 000000000..76d2b2445 --- /dev/null +++ b/portable/IAR/ARM_STAR_MC3_NTZ/non_secure/port.c @@ -0,0 +1,2280 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024-2025 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU includes. */ +#include "mpu_wrappers.h" +#include "mpu_syscall_numbers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if ( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration settings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) +#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to check the validity of an interrupt priority. + */ +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xE000ED1C ) ) +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used during system call enter and exit. + */ +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Offsets in the stack to the parameters when inside the SVC handler. + */ +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +#if ( portARMV8M_MINOR_VERSION >= 1 ) + + /* Enable Privileged eXecute Never MPU attribute for the selected memory + * region. */ + #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL ) +#endif /* portARMV8M_MINOR_VERSION >= 1 */ + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE_BIT ( 1UL << 0UL ) + +/* Extract first address of the MPU region as encoded in the + * RBAR (Region Base Address Register) value. */ +#define portEXTRACT_FIRST_ADDRESS_FROM_RBAR( rbar ) \ + ( ( rbar ) & portMPU_RBAR_ADDRESS_MASK ) + +/* Extract last address of the MPU region as encoded in the + * RLAR (Region Limit Address Register) value. */ +#define portEXTRACT_LAST_ADDRESS_FROM_RLAR( rlar ) \ + ( ( ( rlar ) & portMPU_RLAR_ADDRESS_MASK ) | ~portMPU_RLAR_ADDRESS_MASK ) + +/* Does addr lies within [start, end] address range? */ +#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \ + ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) ) + +/* Is the access request satisfied by the available permissions? */ +#define portIS_AUTHORIZED( accessRequest, permissions ) \ + ( ( ( permissions ) & ( accessRequest ) ) == accessRequest ) + +/* Max value that fits in a uint32_t type. */ +#define portUINT32_MAX ( ~( ( uint32_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) ) +/*-----------------------------------------------------------*/ + +/** + * @brief The maximum 24-bit number. + * + * It is needed because the systick is a 24-bit counter. + */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/** + * @brief A fiddle factor to estimate the number of SysTick counts that would + * have occurred while the SysTick counter is stopped during tickless idle + * calculations. + */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. + */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 + +/** + * @brief Constants required to check and configure PACBTI security feature implementation. + */ +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) ) + + #define portCONTROL_UPAC_EN ( 1UL << 7UL ) + #define portCONTROL_PAC_EN ( 1UL << 6UL ) + #define portCONTROL_UBTI_EN ( 1UL << 5UL ) + #define portCONTROL_BTI_EN ( 1UL << 4UL ) + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Extract MPU region's access permissions from the Region Base Address + * Register (RBAR) value. + * + * @param ulRBARValue RBAR value for the MPU region. + * + * @return uint32_t Access permissions. + */ + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + + /** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + /** + * @brief Configures PACBTI features. + * + * This function configures the Pointer Authentication, and Branch Target + * Identification security features as per the user configuration. It returns + * the value of the special purpose CONTROL register accordingly, and optionally + * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M + * architecture based) target supports PACBTI security feature. + * + * @param xWriteControlRegister Used to control whether the special purpose + * CONTROL register should be updated or not. + * + * @return CONTROL register value according to the configured PACBTI option. + */ + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + +/** + * @brief Setup the timer to generate the tick interrupts. + * + * The implementation in this file is weak to allow application writers to + * change the timer used to generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether the current execution context is interrupt. + * + * @return pdTRUE if the current execution context is interrupt, pdFALSE + * otherwise. + */ +BaseType_t xPortIsInsideInterrupt( void ); + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION; + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the system call stack so that upon returning from + * SVC, the system call stack is used. + * + * @param pulTaskStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + * @param ucSystemCallNumber The system call number of the system call. + */ + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Raise SVC for exiting from a system call. + */ + void vRequestSystemCallExit( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) PRIVILEGED_FUNCTION; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + /** + * @brief This variable is set to pdTRUE when the scheduler is started. + */ + PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE; + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if ( configENABLE_TRUSTZONE == 1 ) + + /** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ + +/** + * @brief Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + /** + * @brief The number of SysTick increments that make up one tick period. + */ + PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0; + + /** + * @brief The maximum number of tick periods that can be suppressed is + * limited by the 24 bit resolution of the SysTick timer. + */ + PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0; + + /** + * @brief Compensate for the CPU cycles that pass while the SysTick is + * stopped (low power functionality only). + */ + PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the cpsid instruction + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessPermissions = 0; + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_ONLY ) + { + ulAccessPermissions = tskMPU_READ_PERMISSION; + } + + if( ( ulRBARValue & portMPU_RBAR_ACCESS_PERMISSIONS_MASK ) == portMPU_REGION_READ_WRITE ) + { + ulAccessPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION ); + } + + return ulAccessPermissions; + } + +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else /* if defined( __ARMCC_VERSION ) */ + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_FPU == 1 ) + + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } + +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + uint32_t ulPC; + + #if ( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0, ulR1; + extern TaskHandle_t pxCurrentTCB; + #if ( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ + #endif /* configENABLE_TRUSTZONE */ + uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ portOFFSET_TO_PC ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if ( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if ( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB ); + } + #else /* if ( configENABLE_MPU == 1 ) */ + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID ); + SecureContext_LoadContext( xSecureContext, pxCurrentTCB ); + break; + + case portSVC_FREE_SECURE_CONTEXT: + + /* R0 contains TCB being freed and R1 contains the secure + * context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + ulR1 = pulCallerStackAddress[ 1 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 ); + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + #if ( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if ( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + break; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: + + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ + + default: + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } +} +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ]; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulSystemCallStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the system call section (i.e. application is + * not raising SVC directly). + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as + * it is non-NULL only during the execution of a system call (i.e. + * between system call enter and exit). + * 3. System call is not for a kernel API disabled by the configuration + * in FreeRTOSConfig.h. + * 4. We do not need to check that ucSystemCallNumber is within range + * because the assembly SVC handler checks that before calling + * this function. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) && + ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) ) + { + pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the system call stack for the stack frame. */ + pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulSystemCallStack[ i ] = pulTaskStack[ i ]; + } + + /* Store the value of the Link Register before the SVC was raised. + * It contains the address of the caller of the System Call entry + * point (i.e. the caller of the MPU_). We need to restore it + * when we exit from the system call. */ + pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; + + /* Store the value of the PSPLIM register before the SVC was raised. + * We need to restore it when we exit from the system call. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* Use the pulSystemCallStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif + + /* Start executing the system call upon returning from this handler. */ + pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; + + /* Raise a request to exit from the system call upon finishing the + * system call. */ + pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; + + /* Remember the location where we should copy the stack frame when we exit from + * the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize; + + /* Record if the hardware used padding to force the stack pointer + * to be double word aligned. */ + if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK ) + { + pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG; + } + else + { + pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG ); + } + + /* We ensure in pxPortInitialiseStack that the system call stack is + * double word aligned and therefore, there is no need of padding. + * Clear the bit[9] of stacked xPSR. */ + pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + + /* Raise the privilege for the duration of the system call. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " bics r0, r1 \n" /* Clear nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vRequestSystemCallExit( void ) /* __attribute__( ( naked ) ) PRIVILEGED_FUNCTION */ + { + __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" ); + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulTaskStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + #endif /* #if defined( __ARMCC_VERSION ) */ + + ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the privileged code (i.e. application is not + * raising SVC directly). This SVC is only raised from + * vRequestSystemCallExit which is in the privileged code section. + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL - + * this means that we previously entered a system call and the + * application is not attempting to exit without entering a system + * call. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) ) + { + pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + { + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + __asm volatile ( + " vpush {s0} \n" /* Trigger lazy stacking. */ + " vpop {s0} \n" /* Nullify the affect of the above instruction. */ + ::: "memory" + ); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + } + #else /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + { + ulHardwareSavedExceptionFrameSize = 8; + } + #endif /* configENABLE_FPU || configENABLE_MVE */ + + /* Make space on the task stack for the stack frame. */ + pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulTaskStack[ i ] = pulSystemCallStack[ i ]; + } + + /* Use the pulTaskStack in thread mode. */ + __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) ); + + /* Return to the caller of the System Call entry point (i.e. the + * caller of the MPU_). */ + pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + /* Ensure that LR has a valid value.*/ + pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + + /* Restore the PSPLIM register to what it was at the time of + * system call entry. */ + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif + + /* If the hardware used padding to force the stack pointer + * to be double word aligned, set the stacked xPSR bit[9], + * otherwise clear it. */ + if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG ) + { + pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK; + } + else + { + pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + } + + /* This is not NULL only for the duration of the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; + + /* Drop the privilege before returning to the thread mode. */ + __asm volatile ( + " mrs r0, control \n" /* Obtain current control value. */ + " movs r1, #1 \n" /* r1 = 1. */ + " orrs r0, r1 \n" /* Set nPRIV bit. */ + " msr control, r0 \n" /* Write back new control value. */ + ::: "r0", "r1", "memory" + ); + } + } + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */ + { + BaseType_t xTaskIsPrivileged = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xTaskIsPrivileged = pdTRUE; + } + + return xTaskIsPrivileged; + } + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged, + xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulIndex = 0; + uint32_t ulControl = 0x0; + + xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x05050505; /* r5. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x06060606; /* r6. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x07070707; /* r7. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x08080808; /* r8. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x09090909; /* r9. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x10101010; /* r10. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ + ulIndex++; + + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + ulIndex++; + + #if ( configENABLE_TRUSTZONE == 1 ) + { + xMPUSettings->ulContext[ ulIndex ] = portNO_SECURE_CONTEXT; /* xSecureContext. */ + ulIndex++; + } + #endif /* configENABLE_TRUSTZONE */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ + ulIndex++; + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + ulIndex++; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Check PACBTI security feature configuration before pushing the + * CONTROL register's value on task's TCB. */ + ulControl = prvConfigurePACBTI( pdFALSE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + if( xRunPrivileged == pdTRUE ) + { + xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + else + { + xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG ); + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */ + ulIndex++; + } + + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ + ulIndex++; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + { + /* Ensure that the system call stack is double word aligned. */ + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ 0 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit = ( uint32_t * ) ( ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) + + ( uint32_t ) ( portBYTE_ALIGNMENT - 1 ) ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + /* This is not NULL only for the duration of a system call. */ + xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL; + } + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ]; + ulIndex++; + } + } + #endif /* configENABLE_PAC */ + + return &( xMPUSettings->ulContext[ ulIndex ] ); + } + +#else /* configENABLE_MPU */ + + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) /* PRIVILEGED_FUNCTION */ + { + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if ( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if ( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + pxTopOfStack--; + *pxTopOfStack = ulTaskPacKey[ i ]; + } + } + #endif /* configENABLE_PAC */ + + return pxTopOfStack; + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ + portNVIC_SHPR2_REG = 0xFF000000; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = ( uint8_t ) ( ( portNVIC_SHPR2_REG & 0xFF000000 ) >> 24 ); + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + } + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ + + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Set the CONTROL register value based on PACBTI security feature + * configuration before starting the first task. */ + ( void ) prvConfigurePACBTI( pdTRUE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + + #if ( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + { + xSchedulerRunning = pdTRUE; + } + #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + configSTACK_DEPTH_TYPE uxStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + #if defined( __ARMCC_VERSION ) + + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( uxStackDepth > 0 ) + { + ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1; + + /* If the stack is within the privileged SRAM, do not protect it + * using a separate MPU region. This is needed because privileged + * SRAM is already protected using an MPU region and ARMv8-M does + * not allow overlapping MPU regions. */ + if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) && + ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) ) + { + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0; + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0; + } + else + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* PXN. */ + #if ( portARMV8M_MINOR_VERSION >= 1 ) + { + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ); + } + } + #endif /* portARMV8M_MINOR_VERSION >= 1 */ + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr0 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, + uint32_t ulBufferLength, + uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */ + + { + uint32_t i, ulBufferStartAddress, ulBufferEndAddress; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE ) + { + ulBufferStartAddress = ( uint32_t ) pvBuffer; + ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL ); + + for( i = 0; i < portTOTAL_NUM_REGIONS; i++ ) + { + /* Is the MPU region enabled? */ + if( ( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR & portMPU_RLAR_REGION_ENABLE ) == portMPU_RLAR_REGION_ENABLE ) + { + if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress, + portEXTRACT_FIRST_ADDRESS_FROM_RBAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ), + portEXTRACT_LAST_ADDRESS_FROM_RLAR( xTaskMpuSettings->xRegionsSettings[ i ].ulRLAR ) ) && + portIS_AUTHORIZED( ulAccessRequested, + prvGetRegionAccessPermissions( xTaskMpuSettings->xRegionsSettings[ i ].ulRBAR ) ) ) + { + xAccessGranted = pdTRUE; + break; + } + } + } + } + } + + return xAccessGranted; + } + +#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. Interrupt Program + * Status Register (IPSR) holds the exception number of the currently-executing + * exception or zero for Thread mode.*/ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings; + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else + { + xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 ) + { + xAccessGranted = pdTRUE; + } + } + } + + return xAccessGranted; + } + + #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + ( void ) lInternalIndexOfKernelObject; + + /* If Access Control List feature is not used, all the tasks have + * access to all the kernel objects. */ + return pdTRUE; + } + + #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + +#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + { + uint32_t ulControl = 0x0; + + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); + + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; + + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/ARM_STAR_MC3_NTZ/non_secure/portasm.h b/portable/IAR/ARM_STAR_MC3_NTZ/non_secure/portasm.h new file mode 100644 index 000000000..b7021b024 --- /dev/null +++ b/portable/IAR/ARM_STAR_MC3_NTZ/non_secure/portasm.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) ); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kernel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__( ( naked ) ); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) ); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */ diff --git a/portable/IAR/ARM_STAR_MC3_NTZ/non_secure/portasm.s b/portable/IAR/ARM_STAR_MC3_NTZ/non_secure/portasm.s new file mode 100644 index 000000000..ba6e8e915 --- /dev/null +++ b/portable/IAR/ARM_STAR_MC3_NTZ/non_secure/portasm.s @@ -0,0 +1,456 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ +/* Including FreeRTOSConfig.h here will cause build errors if the header file +contains code not understood by the assembler - for example the 'extern' keyword. +To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so +the code is included in C files but excluded by the preprocessor in assembly +files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */ +#include "FreeRTOSConfig.h" + +/* System call numbers includes. */ +#include "mpu_syscall_numbers.h" + +#ifndef configUSE_MPU_WRAPPERS_V1 + #define configUSE_MPU_WRAPPERS_V1 0 +#endif + + EXTERN pxCurrentTCB + EXTERN vTaskSwitchContext + EXTERN vPortSVCHandler_C +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + EXTERN vSystemCallEnter + EXTERN vSystemCallExit +#endif + + PUBLIC xIsPrivileged + PUBLIC vResetPrivilege + PUBLIC vRestoreContextOfFirstTask + PUBLIC vRaisePrivilege + PUBLIC vStartFirstTask + PUBLIC ulSetInterruptMask + PUBLIC vClearInterruptMask + PUBLIC PendSV_Handler + PUBLIC SVC_Handler +/*-----------------------------------------------------------*/ + +/*---------------- Unprivileged Functions -------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION .text:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +xIsPrivileged: + mrs r0, control /* r0 = CONTROL. */ + tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + ite ne + movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vResetPrivilege: + mrs r0, control /* r0 = CONTROL. */ + orr r0, r0, #1 /* r0 = r0 | 1. */ + msr control, r0 /* CONTROL = r0. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +/*----------------- Privileged Functions --------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION privileged_functions:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +vRestoreContextOfFirstTask: + program_mpu_first_task: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r2] /* r0 = pxCurrentTCB. */ + + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + str r2, [r1] /* Disable MPU. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r1, [r2] /* Program MAIR0. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + + movs r3, #4 /* r3 = 4. */ + str r3, [r1] /* Program RNR = 4. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + #if ( configTOTAL_MPU_REGIONS == 16 ) + movs r3, #8 /* r3 = 8. */ + str r3, [r1] /* Program RNR = 8. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + movs r3, #12 /* r3 = 12. */ + str r3, [r1] /* Program RNR = 12. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + orr r2, #1 /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */ + str r2, [r1] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + + restore_context_first_task: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r2] /* r0 = pxCurrentTCB.*/ + ldr r1, [r0] /* r1 = Location of saved context in TCB. */ + + restore_special_regs_first_task: + #if ( configENABLE_PAC == 1 ) + ldmdb r1!, {r2-r5} /* Read task's dedicated PAC key from the task's context. */ + msr PAC_KEY_P_0, r2 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_1, r3 + msr PAC_KEY_P_2, r4 + msr PAC_KEY_P_3, r5 + clrm {r2-r5} /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + ldmdb r1!, {r2-r4, lr} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */ + msr psp, r2 + msr psplim, r3 + msr control, r4 + + restore_general_regs_first_task: + ldmdb r1!, {r4-r11} /* r4-r11 contain hardware saved context. */ + stmia r2!, {r4-r11} /* Copy the hardware saved context on the task stack. */ + ldmdb r1!, {r4-r11} /* r4-r11 restored. */ + + restore_context_done_first_task: + str r1, [r0] /* Save the location where the context should be saved next as the first member of TCB. */ + mov r0, #0 + msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ + bx lr + +#else /* configENABLE_MPU */ + +vRestoreContextOfFirstTask: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + +#if ( configENABLE_PAC == 1 ) + ldmia r0!, {r1-r4} /* Read task's dedicated PAC key from stack. */ + msr PAC_KEY_P_3, r1 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_2, r2 + msr PAC_KEY_P_1, r3 + msr PAC_KEY_P_0, r4 + clrm {r1-r4} /* Clear r1-r4. */ +#endif /* configENABLE_PAC */ + + ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */ + msr psplim, r1 /* Set this task's PSPLIM value. */ + mrs r1, control /* Obtain current control register value. */ + orrs r1, r1, #2 /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */ + msr control, r1 /* Write back the new control register value. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + mov r0, #0 + msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */ + bx r2 /* Finally, branch to EXC_RETURN. */ + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +vRaisePrivilege: + mrs r0, control /* Read the CONTROL register. */ + bic r0, r0, #1 /* Clear the bit 0. */ + msr control, r0 /* Write back the new CONTROL value. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vStartFirstTask: + ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */ + ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */ + ldr r0, [r0] /* The first entry in vector table is stack pointer. */ + msr msp, r0 /* Set the MSP back to the start of the stack. */ + cpsie i /* Globally enable interrupts. */ + cpsie f + dsb + isb + svc 102 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */ +/*-----------------------------------------------------------*/ + +ulSetInterruptMask: + mrs r0, basepri /* r0 = basepri. Return original basepri value. */ + mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r1 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vClearInterruptMask: + msr basepri, r0 /* basepri = ulMask. */ + dsb + isb + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +PendSV_Handler: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r2] /* r0 = pxCurrentTCB. */ + ldr r1, [r0] /* r1 = Location in TCB where the context should be saved. */ + mrs r2, psp /* r2 = PSP. */ + + save_general_regs: + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + add r2, r2, #0x20 /* Move r2 to location where s0 is saved. */ + tst lr, #0x10 + ittt eq + vstmiaeq r1!, {s16-s31} /* Store s16-s31. */ + vldmiaeq r2, {s0-s16} /* Copy hardware saved FP context into s0-s16. */ + vstmiaeq r1!, {s0-s16} /* Store hardware saved FP context. */ + sub r2, r2, #0x20 /* Set r2 back to the location of hardware saved context. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + stmia r1!, {r4-r11} /* Store r4-r11. */ + ldmia r2, {r4-r11} /* Copy the hardware saved context into r4-r11. */ + stmia r1!, {r4-r11} /* Store the hardware saved context. */ + + save_special_regs: + mrs r3, psplim /* r3 = PSPLIM. */ + mrs r4, control /* r4 = CONTROL. */ + stmia r1!, {r2-r4, lr} /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ + #if ( configENABLE_PAC == 1 ) + mrs r2, PAC_KEY_P_0 /* Read task's dedicated PAC key from the PAC key registers. */ + mrs r3, PAC_KEY_P_1 + mrs r4, PAC_KEY_P_2 + mrs r5, PAC_KEY_P_3 + stmia r1!, {r2-r5} /* Store the task's dedicated PAC key on the task's context. */ + clrm {r2-r5} /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + + str r1, [r0] /* Save the location from where the context should be restored as the first member of TCB. */ + + select_next_task: + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bl vTaskSwitchContext + mov r0, #0 /* r0 = 0. */ + msr basepri, r0 /* Enable interrupts. */ + + program_mpu: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r2] /* r0 = pxCurrentTCB. */ + + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */ + str r2, [r1] /* Disable MPU. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */ + ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r1, [r2] /* Program MAIR0. */ + + adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */ + ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + + movs r3, #4 /* r3 = 4. */ + str r3, [r1] /* Program RNR = 4. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + #if ( configTOTAL_MPU_REGIONS == 16 ) + movs r3, #8 /* r3 = 8. */ + str r3, [r1] /* Program RNR = 8. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + movs r3, #12 /* r3 = 12. */ + str r3, [r1] /* Program RNR = 12. */ + ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + #endif /* configTOTAL_MPU_REGIONS == 16 */ + + ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r2, [r1] /* Read the value of MPU_CTRL. */ + orr r2, #1 /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */ + str r2, [r1] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + + restore_context: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r0, [r2] /* r0 = pxCurrentTCB.*/ + ldr r1, [r0] /* r1 = Location of saved context in TCB. */ + + restore_special_regs: + #if ( configENABLE_PAC == 1 ) + ldmdb r1!, {r2-r5} /* Read task's dedicated PAC key from the task's context. */ + msr PAC_KEY_P_0, r2 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_1, r3 + msr PAC_KEY_P_2, r4 + msr PAC_KEY_P_3, r5 + clrm {r2-r5} /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + ldmdb r1!, {r2-r4, lr} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */ + msr psp, r2 + msr psplim, r3 + msr control, r4 + + restore_general_regs: + ldmdb r1!, {r4-r11} /* r4-r11 contain hardware saved context. */ + stmia r2!, {r4-r11} /* Copy the hardware saved context on the task stack. */ + ldmdb r1!, {r4-r11} /* r4-r11 restored. */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 + ittt eq + vldmdbeq r1!, {s0-s16} /* s0-s16 contain hardware saved FP context. */ + vstmiaeq r2!, {s0-s16} /* Copy hardware saved FP context on the task stack. */ + vldmdbeq r1!, {s16-s31} /* Restore s16-s31. */ + #endif /* configENABLE_FPU || configENABLE_MVE */ + + restore_context_done: + str r1, [r0] /* Save the location where the context should be saved next as the first member of TCB. */ + bx lr + +#else /* configENABLE_MPU */ + +PendSV_Handler: + mrs r0, psp /* Read PSP in r0. */ +#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + it eq + vstmdbeq r0!, {s16-s31} /* Store the additional FP context registers which are not saved automatically. */ +#endif /* configENABLE_FPU || configENABLE_MVE */ + + mrs r2, psplim /* r2 = PSPLIM. */ + mov r3, lr /* r3 = LR/EXC_RETURN. */ + stmdb r0!, {r2-r11} /* Store on the stack - PSPLIM, LR and registers that are not automatically. */ + +#if ( configENABLE_PAC == 1 ) + mrs r1, PAC_KEY_P_3 /* Read task's dedicated PAC key from the PAC key registers. */ + mrs r2, PAC_KEY_P_2 + mrs r3, PAC_KEY_P_1 + mrs r4, PAC_KEY_P_0 + stmdb r0!, {r1-r4} /* Store the task's dedicated PAC key on the stack. */ + clrm {r1-r4} /* Clear r1-r4. */ +#endif /* configENABLE_PAC */ + + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + str r0, [r1] /* Save the new top of stack in TCB. */ + + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + dsb + isb + bl vTaskSwitchContext + mov r0, #0 /* r0 = 0. */ + msr basepri, r0 /* Enable interrupts. */ + + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ + +#if ( configENABLE_PAC == 1 ) + ldmia r0!, {r2-r5} /* Read task's dedicated PAC key from stack. */ + msr PAC_KEY_P_3, r2 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_2, r3 + msr PAC_KEY_P_1, r4 + msr PAC_KEY_P_0, r5 + clrm {r2-r5} /* Clear r2-r5. */ +#endif /* configENABLE_PAC */ + + ldmia r0!, {r2-r11} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */ + +#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + tst r3, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ + it eq + vldmiaeq r0!, {s16-s31} /* Restore the additional FP context registers which are not restored automatically. */ +#endif /* configENABLE_FPU || configENABLE_MVE */ + + msr psplim, r2 /* Restore the PSPLIM register value for the task. */ + msr psp, r0 /* Remember the new top of stack for the task. */ + bx r3 + +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + +SVC_Handler: + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + + ldr r1, [r0, #24] + ldrb r2, [r1, #-2] + cmp r2, #NUM_SYSTEM_CALLS + blt syscall_enter + cmp r2, #104 /* portSVC_SYSTEM_CALL_EXIT. */ + beq syscall_exit + b vPortSVCHandler_C + + syscall_enter: + mov r1, lr + b vSystemCallEnter + + syscall_exit: + mov r1, lr + b vSystemCallExit + +#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +SVC_Handler: + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + b vPortSVCHandler_C + +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + + END diff --git a/portable/IAR/ARM_STAR_MC3_NTZ/non_secure/portmacro.h b/portable/IAR/ARM_STAR_MC3_NTZ/non_secure/portmacro.h new file mode 100644 index 000000000..a0ee66907 --- /dev/null +++ b/portable/IAR/ARM_STAR_MC3_NTZ/non_secure/portmacro.h @@ -0,0 +1,87 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (c) 2026 Arm Technology (China) Co., Ltd.All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_MVE + #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE. +#endif /* configENABLE_MVE */ +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "STAR-MC3" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portARMV8M_MINOR_VERSION 1 +#define portDONT_DISCARD __root +/*-----------------------------------------------------------*/ + +/* ARMv8-M common port configurations. */ +#include "portmacrocommon.h" +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ +#pragma diag_suppress=Be006 +#pragma diag_suppress=Pa082 +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/IAR/ARM_STAR_MC3_NTZ/non_secure/portmacrocommon.h b/portable/IAR/ARM_STAR_MC3_NTZ/non_secure/portmacrocommon.h new file mode 100644 index 000000000..f373bcad5 --- /dev/null +++ b/portable/IAR/ARM_STAR_MC3_NTZ/non_secure/portmacrocommon.h @@ -0,0 +1,582 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACROCOMMON_H +#define PORTMACROCOMMON_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. +#endif /* configENABLE_FPU */ + +#ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. +#endif /* configENABLE_MPU */ + +#ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. +#endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() +#define portINLINE __inline +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif +#define portHAS_STACK_OVERFLOW_CHECKING 1 +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ +extern BaseType_t xPortIsInsideInterrupt( void ); + +extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + +extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; +extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + +extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; +extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + +#if ( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; +#endif /* configENABLE_TRUSTZONE */ + +#if ( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; +#endif /* configENABLE_MPU */ + +#if ( configENABLE_PAC == 1 ) + + /** + * @brief Generates 128-bit task's random PAC key. + * + * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be + * filled with a 128-bit random number. + */ + void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); + +#endif /* configENABLE_PAC */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ +#if ( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) +#else + #define portPRIVILEGE_BIT ( 0x0UL ) +#endif /* configENABLE_MPU */ + +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* MPU regions. */ +#define portPRIVILEGED_FLASH_REGION ( 0UL ) +#define portUNPRIVILEGED_FLASH_REGION ( 1UL ) +#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) +#define portPRIVILEGED_RAM_REGION ( 3UL ) +#define portSTACK_REGION ( 4UL ) +#define portFIRST_CONFIGURABLE_REGION ( 5UL ) +#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL ) +#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) +#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ +#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ +#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ +#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ +#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ +#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ +#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ +#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) +#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) +#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + +#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) +#define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) +#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) +#define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + +#define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + /** + * @brief Settings to define an MPU region. + */ + typedef struct MPURegionSettings + { + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ + } MPURegionSettings_t; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + #ifndef configSYSTEM_CALL_STACK_SIZE + #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. + #endif + + /** + * @brief System call stack. + */ + typedef struct SYSTEM_CALL_STACK_INFO + { + uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; + uint32_t * pulSystemCallStack; + uint32_t * pulSystemCallStackLimit; + uint32_t * pulTaskStack; + uint32_t ulLinkRegisterAtSystemCallEntry; + uint32_t ulStackLimitRegisterAtSystemCallEntry; + } xSYSTEM_CALL_STACK_INFO; + + #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + + /** + * @brief MPU settings as stored in the TCB. + */ + #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><-----------><----> + * 16 17 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 71 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | + * +-----------+---------------+----------+-----------------+------------------------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><----> + * 16 17 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 55 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | | | PC, xPSR | EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><-----------><----> + * 16 17 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 70 + + #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + /* + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | | | PC, xPSR | EXC_RETURN | | + * +-----------+---------------+----------+-----------------+----------------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><----> + * 16 17 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 54 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+------------------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +----------+-----------------+------------------------------+------------+-----+ + * + * <---------><----------------><------------------------------><-----------><----> + * 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 38 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) + + /* + * +----------+-----------------+------------------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | + * +----------+-----------------+------------------------------+-----+ + * + * <---------><----------------><------------------------------><----> + * 8 8 5 1 + */ + #define MAX_CONTEXT_SIZE 22 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+----------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | PC, xPSR | EXC_RETURN | | | + * +----------+-----------------+----------------------+------------+-----+ + * + * <---------><----------------><----------------------><-----------><----> + * 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 37 + + #else /* #if( configENABLE_TRUSTZONE == 1 ) */ + + /* + * +----------+-----------------+----------------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | | + * | | PC, xPSR | EXC_RETURN | | + * +----------+-----------------+----------------------+-----+ + * + * <---------><----------------><----------------------><----> + * 8 8 4 1 + */ + #define MAX_CONTEXT_SIZE 21 + + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ + + #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + + /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) + + /* Size of an Access Control List (ACL) entry in bits. */ + #define portACL_ENTRY_SIZE_BITS ( 32U ) + + typedef struct MPU_SETTINGS + { + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ + uint32_t ulContext[ MAX_CONTEXT_SIZE ]; + uint32_t ulTaskFlags; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo; + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ]; + #endif + #endif + } xMPU_SETTINGS; + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Validate priority of ISRs that are allowed to call FreeRTOS + * system calls. + */ +#if ( configASSERT_DEFINED == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif +#endif + +/** + * @brief SVC numbers. + */ +#define portSVC_ALLOCATE_SECURE_CONTEXT 100 +#define portSVC_FREE_SECURE_CONTEXT 101 +#define portSVC_START_SCHEDULER 102 +#define portSVC_RAISE_PRIVILEGE 103 +#define portSVC_SYSTEM_CALL_EXIT 104 +#define portSVC_YIELD 105 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Tickless idle/low power functionality. + */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +#if ( configENABLE_TRUSTZONE == 1 ) + +/** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + +/** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) +#endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() +#else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if ( configENABLE_MPU == 1 ) + + extern BaseType_t xPortIsTaskPrivileged( void ); + +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() + +#endif /* configENABLE_MPU == 1 */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACROCOMMON_H */ diff --git a/portable/IAR/ATMega323/port.c b/portable/IAR/ATMega323/port.c new file mode 100644 index 000000000..980787990 --- /dev/null +++ b/portable/IAR/ATMega323/port.c @@ -0,0 +1,340 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include + +#include "FreeRTOS.h" +#include "task.h" + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the AVR/IAR port. +*----------------------------------------------------------*/ + +/* Start tasks with interrupts enables. */ +#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x80 ) + +/* Hardware constants for timer 1. */ +#define portCLEAR_COUNTER_ON_MATCH ( ( uint8_t ) 0x08 ) +#define portPRESCALE_64 ( ( uint8_t ) 0x03 ) +#define portCLOCK_PRESCALER ( ( uint32_t ) 64 ) +#define portCOMPARE_MATCH_A_INTERRUPT_ENABLE ( ( uint8_t ) 0x10 ) + +/* The number of bytes used on the hardware stack by the task start address. */ +#define portBYTES_USED_BY_RETURN_ADDRESS ( 2 ) +/*-----------------------------------------------------------*/ + +/* Stores the critical section nesting. This must not be initialised to 0. + * It will be initialised when a task starts. */ +#define portNO_CRITICAL_NESTING ( ( UBaseType_t ) 0 ) +UBaseType_t uxCriticalNesting = 0x50; + + +/* + * Perform hardware setup to enable ticks from timer 1, compare match A. + */ +static void prvSetupTimerInterrupt( void ); + +/* + * The IAR compiler does not have full support for inline assembler, so + * these are defined in the portmacro assembler file. + */ +extern void vPortYieldFromTick( void ); +extern void vPortStart( void ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + uint16_t usAddress; + StackType_t * pxTopOfHardwareStack; + + /* Place a few bytes of known values on the bottom of the stack. + * This is just useful for debugging. */ + + *pxTopOfStack = 0x11; + pxTopOfStack--; + *pxTopOfStack = 0x22; + pxTopOfStack--; + *pxTopOfStack = 0x33; + pxTopOfStack--; + + /* Remember where the top of the hardware stack is - this is required + * below. */ + pxTopOfHardwareStack = pxTopOfStack; + + + /* Simulate how the stack would look after a call to vPortYield(). */ + + /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */ + + + + /* The IAR compiler requires two stacks per task. First there is the + * hardware call stack which uses the AVR stack pointer. Second there is the + * software stack (local variables, parameter passing, etc.) which uses the + * AVR Y register. + * + * This function places both stacks within the memory block passed in as the + * first parameter. The hardware stack is placed at the bottom of the memory + * block. A gap is then left for the hardware stack to grow. Next the software + * stack is placed. The amount of space between the software and hardware + * stacks is defined by configCALL_STACK_SIZE. + * + * + * + * The first part of the stack is the hardware stack. Place the start + * address of the task on the hardware stack. */ + usAddress = ( uint16_t ) pxCode; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + usAddress >>= 8; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + + /* Leave enough space for the hardware stack before starting the software + * stack. The '- 2' is because we have already used two spaces for the + * address of the start of the task. */ + pxTopOfStack -= ( configCALL_STACK_SIZE - 2 ); + + + + /* Next simulate the stack as if after a call to portSAVE_CONTEXT(). + * portSAVE_CONTEXT places the flags on the stack immediately after r0 + * to ensure the interrupts get disabled as soon as possible, and so ensuring + * the stack use is minimal should a context switch interrupt occur. */ + *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */ + pxTopOfStack--; + *pxTopOfStack = portFLAGS_INT_ENABLED; + pxTopOfStack--; + + /* Next place the address of the hardware stack. This is required so + * the AVR stack pointer can be restored to point to the hardware stack. */ + pxTopOfHardwareStack -= portBYTES_USED_BY_RETURN_ADDRESS; + usAddress = ( uint16_t ) pxTopOfHardwareStack; + + /* SPL */ + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + /* SPH */ + usAddress >>= 8; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + + + /* Now the remaining registers. */ + *pxTopOfStack = ( StackType_t ) 0x01; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x13; /* R13 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x14; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x15; /* R15 */ + pxTopOfStack--; + + /* Place the parameter on the stack in the expected location. */ + usAddress = ( uint16_t ) pvParameters; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + usAddress >>= 8; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0x18; /* R18 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x19; /* R19 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x20; /* R20 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x21; /* R21 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x22; /* R22 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x23; /* R23 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x24; /* R24 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x25; /* R25 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x26; /* R26 X */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x27; /* R27 */ + pxTopOfStack--; + + /* The Y register is not stored as it is used as the software stack and + * gets saved into the task control block. */ + + *pxTopOfStack = ( StackType_t ) 0x30; /* R30 Z */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x031; /* R31 */ + + pxTopOfStack--; + *pxTopOfStack = portNO_CRITICAL_NESTING; /* Critical nesting is zero when the task starts. */ + + /*lint +e950 +e611 +e923 */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Setup the hardware to generate the tick. */ + prvSetupTimerInterrupt(); + + /* Restore the context of the first task that is going to run. + * Normally we would just call portRESTORE_CONTEXT() here, but as the IAR + * compiler does not fully support inline assembler we have to make a call.*/ + vPortStart(); + + /* Should not get here! */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the AVR port will get stopped. If required simply + * disable the tick interrupt here. */ +} +/*-----------------------------------------------------------*/ + +/* + * Setup timer 1 compare match A to generate a tick interrupt. + */ +static void prvSetupTimerInterrupt( void ) +{ + uint32_t ulCompareMatch; + uint8_t ucHighByte, ucLowByte; + + /* Using 16bit timer 1 to generate the tick. Correct fuses must be + * selected for the configCPU_CLOCK_HZ clock. */ + + ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ; + + /* We only have 16 bits so have to scale to get our required tick rate. */ + ulCompareMatch /= portCLOCK_PRESCALER; + + /* Adjust for correct value. */ + ulCompareMatch -= ( uint32_t ) 1; + + /* Setup compare match value for compare match A. Interrupts are disabled + * before this is called so we need not worry here. */ + ucLowByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff ); + ulCompareMatch >>= 8; + ucHighByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff ); + OCR1AH = ucHighByte; + OCR1AL = ucLowByte; + + /* Setup clock source and compare match behaviour. */ + ucLowByte = portCLEAR_COUNTER_ON_MATCH | portPRESCALE_64; + TCCR1B = ucLowByte; + + /* Enable the interrupt - this is okay as interrupt are currently globally + * disabled. */ + TIMSK |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE; +} +/*-----------------------------------------------------------*/ + +#if configUSE_PREEMPTION == 1 + +/* + * Tick ISR for preemptive scheduler. We can use a __task attribute as + * the context is saved at the start of vPortYieldFromTick(). The tick + * count is incremented after the context is saved. + */ + __task void SIG_OUTPUT_COMPARE1A( void ) + { + vPortYieldFromTick(); + asm ( "reti" ); + } + +#else + +/* + * Tick ISR for the cooperative scheduler. All this does is increment the + * tick count. We don't need to switch context, this can only be done by + * manual calls to taskYIELD(); + * + * THE INTERRUPT VECTOR IS POPULATED IN portmacro.s90. DO NOT INSTALL + * IT HERE USING THE USUAL PRAGMA. + */ + __interrupt void SIG_OUTPUT_COMPARE1A( void ) + { + xTaskIncrementTick(); + } +#endif /* if configUSE_PREEMPTION == 1 */ +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + uxCriticalNesting--; + + if( uxCriticalNesting == portNO_CRITICAL_NESTING ) + { + portENABLE_INTERRUPTS(); + } +} diff --git a/portable/IAR/ATMega323/portmacro.h b/portable/IAR/ATMega323/portmacro.h new file mode 100644 index 000000000..e50d9f3d7 --- /dev/null +++ b/portable/IAR/ATMega323/portmacro.h @@ -0,0 +1,117 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * Changes from V1.2.3 + * + + portCPU_CLOCK_HZ definition changed to 8MHz base 10, previously it + + base 16. + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE uint8_t +#define portBASE_TYPE char +#define portPOINTER_SIZE_TYPE uint16_t + +typedef portSTACK_TYPE StackType_t; +typedef signed char BaseType_t; +typedef unsigned char UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif + +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() + +#define portDISABLE_INTERRUPTS() asm ( "cli" ) +#define portENABLE_INTERRUPTS() asm ( "sei" ) +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 1 +#define portNOP() asm ( "nop" ) +/*-----------------------------------------------------------*/ + +/* Kernel utilities. */ +void vPortYield( void ); +#define portYIELD() vPortYield() + +#ifdef IAR_MEGA_AVR + #define outb( PORT, VALUE ) PORT = VALUE +#endif +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/IAR/ATMega323/portmacro.s90 b/portable/IAR/ATMega323/portmacro.s90 new file mode 100644 index 000000000..029d0dbb6 --- /dev/null +++ b/portable/IAR/ATMega323/portmacro.s90 @@ -0,0 +1,245 @@ +;/* +; * FreeRTOS Kernel +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + +#include + +; Declare all extern symbols here - including any ISRs that are referenced in +; the vector table. + +; ISR functions +; ------------- +EXTERN SIG_OUTPUT_COMPARE1A +EXTERN SIG_UART_RECV +EXTERN SIG_UART_DATA + + +; Functions used by scheduler +; --------------------------- +EXTERN vTaskSwitchContext +EXTERN pxCurrentTCB +EXTERN xTaskIncrementTick +EXTERN uxCriticalNesting + +; Functions implemented in this file +; ---------------------------------- +PUBLIC vPortYield +PUBLIC vPortYieldFromTick +PUBLIC vPortStart + + +; Interrupt vector table. +; ----------------------- +; +; For simplicity the RTOS tick interrupt routine uses the __task keyword. +; As the IAR compiler does not permit a function to be declared using both +; __task and __interrupt, the use of __task necessitates that the interrupt +; vector table be setup manually. +; +; To write an ISR, implement the ISR function using the __interrupt keyword +; but do not install the interrupt using the "#pragma vector=ABC" method. +; Instead manually place the name of the ISR in the vector table using an +; ORG and jmp instruction as demonstrated below. +; You will also have to add an EXTERN statement at the top of the file. + + ASEG + + + ORG TIMER1_COMPA_vect ; Vector address + jmp SIG_OUTPUT_COMPARE1A ; ISR + + ORG USART_RXC_vect ; Vector address + jmp SIG_UART_RECV ; ISR + + ORG USART_UDRE_vect ; Vector address + jmp SIG_UART_DATA ; ISR + + + RSEG CODE + + + +; Saving and Restoring a Task Context and Task Switching +; ------------------------------------------------------ +; +; The IAR compiler does not fully support inline assembler, so saving and +; restoring a task context has to be written in an asm file. +; +; vPortYield() and vPortYieldFromTick() are usually written in C. Doing +; so in this case would required calls to be made to portSAVE_CONTEXT() and +; portRESTORE_CONTEXT(). This is dis-advantageous as the context switch +; function would require two extra jump and return instructions over the +; WinAVR equivalent. +; +; To avoid this I have opted to implement both vPortYield() and +; vPortYieldFromTick() in this assembly file. For convenience +; portSAVE_CONTEXT and portRESTORE_CONTEXT are implemented as macros. + +portSAVE_CONTEXT MACRO + st -y, r0 ; First save the r0 register - we need to use this. + in r0, SREG ; Obtain the SREG value so we can disable interrupts... + cli ; ... as soon as possible. + st -y, r0 ; Store the SREG as it was before we disabled interrupts. + + in r0, SPL ; Next store the hardware stack pointer. The IAR... + st -y, r0 ; ... compiler uses the hardware stack as a call stack ... + in r0, SPH ; ... only. + st -y, r0 + + st -y, r1 ; Now store the rest of the registers. Dont store the ... + st -y, r2 ; ... the Y register here as it is used as the software + st -y, r3 ; stack pointer and will get saved into the TCB. + st -y, r4 + st -y, r5 + st -y, r6 + st -y, r7 + st -y, r8 + st -y, r9 + st -y, r10 + st -y, r11 + st -y, r12 + st -y, r13 + st -y, r14 + st -y, r15 + st -y, r16 + st -y, r17 + st -y, r18 + st -y, r19 + st -y, r20 + st -y, r21 + st -y, r22 + st -y, r23 + st -y, r24 + st -y, r25 + st -y, r26 + st -y, r27 + st -y, r30 + st -y, r31 + lds r0, uxCriticalNesting + st -y, r0 ; Store the critical nesting counter. + + lds r26, pxCurrentTCB ; Finally save the software stack pointer (Y ... + lds r27, pxCurrentTCB + 1 ; ... register) into the TCB. + st x+, r28 + st x+, r29 + + ENDM + + +portRESTORE_CONTEXT MACRO + lds r26, pxCurrentTCB + lds r27, pxCurrentTCB + 1 ; Restore the software stack pointer from ... + ld r28, x+ ; the TCB into the software stack pointer (... + ld r29, x+ ; ... the Y register). + + ld r0, y+ + sts uxCriticalNesting, r0 + ld r31, y+ ; Restore the registers down to R0. The Y + ld r30, y+ ; register is missing from this list as it + ld r27, y+ ; has already been restored. + ld r26, y+ + ld r25, y+ + ld r24, y+ + ld r23, y+ + ld r22, y+ + ld r21, y+ + ld r20, y+ + ld r19, y+ + ld r18, y+ + ld r17, y+ + ld r16, y+ + ld r15, y+ + ld r14, y+ + ld r13, y+ + ld r12, y+ + ld r11, y+ + ld r10, y+ + ld r9, y+ + ld r8, y+ + ld r7, y+ + ld r6, y+ + ld r5, y+ + ld r4, y+ + ld r3, y+ + ld r2, y+ + ld r1, y+ + + ld r0, y+ ; The next thing on the stack is the ... + out SPH, r0 ; ... hardware stack pointer. + ld r0, y+ + out SPL, r0 + + ld r0, y+ ; Next there is the SREG register. + out SREG, r0 + + ld r0, y+ ; Finally we have finished with r0, so restore r0. + + ENDM + + + +; vPortYield() and vPortYieldFromTick() +; ------------------------------------- +; +; Manual and preemptive context switch functions respectively. +; The IAR compiler does not fully support inline assembler, +; so these are implemented here rather than the more usually +; place of within port.c. + +vPortYield: + portSAVE_CONTEXT ; Save the context of the current task. + call vTaskSwitchContext ; Call the scheduler. + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + ret ; ... scheduler decided should run. + +vPortYieldFromTick: + portSAVE_CONTEXT ; Save the context of the current task. + call xTaskIncrementTick ; Call the timer tick function. + tst r16 + breq SkipTaskSwitch + call vTaskSwitchContext ; Call the scheduler. +SkipTaskSwitch: + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + ret ; ... scheduler decided should run. + +; vPortStart() +; ------------ +; +; Again due to the lack of inline assembler, this is required +; to get access to the portRESTORE_CONTEXT macro. + +vPortStart: + portRESTORE_CONTEXT + ret + + +; Just a filler for unused interrupt vectors. +vNoISR: + reti + + + END diff --git a/portable/IAR/AVR32_UC3/exception.s82 b/portable/IAR/AVR32_UC3/exception.s82 new file mode 100644 index 000000000..653600995 --- /dev/null +++ b/portable/IAR/AVR32_UC3/exception.s82 @@ -0,0 +1,340 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT AND BSD-3-Clause + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Exception and interrupt vectors. + * + * This file maps all events supported by an AVR32UC. + * + * - Compiler: IAR EWAVR32 + * - Supported devices: All AVR32UC devices with an INTC module can be used. + * - AppNote: + * + * \author Atmel Corporation (Now Microchip): + https://www.microchip.com \n + * Support and FAQ: https://www.microchip.com/support + * + ******************************************************************************/ + +/* + * Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include +#include "intc.h" + + +//! @{ +//! \verbatim + + +// Start of Exception Vector Table. + + // EVBA must be aligned with a power of two strictly greater than the EVBA- + // relative offset of the last vector. + COMMON EVTAB:CODE:ROOT(9) + + + // Force EVBA initialization. + EXTERN ??init_EVBA + REQUIRE ??init_EVBA + + // Export symbol. + PUBLIC ??EVBA + PUBLIC _evba +??EVBA: +_evba: + + ORG 0x000 + // Unrecoverable Exception. +_handle_Unrecoverable_Exception: + rjmp $ + + ORG 0x004 + // TLB Multiple Hit: UNUSED IN AVR32UC. +_handle_TLB_Multiple_Hit: + rjmp $ + + ORG 0x008 + // Bus Error Data Fetch. +_handle_Bus_Error_Data_Fetch: + rjmp $ + + ORG 0x00C + // Bus Error Instruction Fetch. +_handle_Bus_Error_Instruction_Fetch: + rjmp $ + + ORG 0x010 + // NMI. +_handle_NMI: + rjmp $ + + ORG 0x014 + // Instruction Address. +_handle_Instruction_Address: + rjmp $ + + ORG 0x018 + // ITLB Protection. +_handle_ITLB_Protection: + rjmp $ + + ORG 0x01C + // Breakpoint. +_handle_Breakpoint: + rjmp $ + + ORG 0x020 + // Illegal Opcode. +_handle_Illegal_Opcode: + rjmp $ + + ORG 0x024 + // Unimplemented Instruction. +_handle_Unimplemented_Instruction: + rjmp $ + + ORG 0x028 + // Privilege Violation. +_handle_Privilege_Violation: + rjmp $ + + ORG 0x02C + // Floating-Point: UNUSED IN AVR32UC. +_handle_Floating_Point: + rjmp $ + + ORG 0x030 + // Coprocessor Absent: UNUSED IN AVR32UC. +_handle_Coprocessor_Absent: + rjmp $ + + ORG 0x034 + // Data Address (Read). +_handle_Data_Address_Read: + rjmp $ + + ORG 0x038 + // Data Address (Write). +_handle_Data_Address_Write: + rjmp $ + + ORG 0x03C + // DTLB Protection (Read). +_handle_DTLB_Protection_Read: + rjmp $ + + ORG 0x040 + // DTLB Protection (Write). +_handle_DTLB_Protection_Write: + rjmp $ + + ORG 0x044 + // DTLB Modified: UNUSED IN AVR32UC. +_handle_DTLB_Modified: + rjmp $ + + ORG 0x050 + // ITLB Miss: UNUSED IN AVR32UC. +_handle_ITLB_Miss: + rjmp $ + + ORG 0x060 + // DTLB Miss (Read): UNUSED IN AVR32UC. +_handle_DTLB_Miss_Read: + rjmp $ + + ORG 0x070 + // DTLB Miss (Write): UNUSED IN AVR32UC. +_handle_DTLB_Miss_Write: + rjmp $ + + ORG 0x100 + // Supervisor Call. +_handle_Supervisor_Call: + lddpc pc, __SCALLYield + + +// Interrupt support. +// The interrupt controller must provide the offset address relative to EVBA. +// Important note: +// All interrupts call a C function named _get_interrupt_handler. +// This function will read group and interrupt line number to then return in +// R12 a pointer to a user-provided interrupt handler. + + ALIGN 2 + +_int0: + // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the + // CPU upon interrupt entry. +#if 1 // B1832: interrupt stack changed to exception stack if exception is detected. + mfsr r12, AVR32_SR + bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE + cp.w r12, 110b + brlo _int0_normal + lddsp r12, sp[0 * 4] + stdsp sp[6 * 4], r12 + lddsp r12, sp[1 * 4] + stdsp sp[7 * 4], r12 + lddsp r12, sp[3 * 4] + sub sp, -6 * 4 + rete +_int0_normal: +#endif + mov r12, 0 // Pass the int_lev parameter to the _get_interrupt_handler function. + mcall __get_interrupt_handler + cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. + movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. + rete // If this was a spurious interrupt (R12 == NULL), return from event handler. + +_int1: + // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the + // CPU upon interrupt entry. +#if 1 // B1832: interrupt stack changed to exception stack if exception is detected. + mfsr r12, AVR32_SR + bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE + cp.w r12, 110b + brlo _int1_normal + lddsp r12, sp[0 * 4] + stdsp sp[6 * 4], r12 + lddsp r12, sp[1 * 4] + stdsp sp[7 * 4], r12 + lddsp r12, sp[3 * 4] + sub sp, -6 * 4 + rete +_int1_normal: +#endif + mov r12, 1 // Pass the int_lev parameter to the _get_interrupt_handler function. + mcall __get_interrupt_handler + cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. + movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. + rete // If this was a spurious interrupt (R12 == NULL), return from event handler. + +_int2: + // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the + // CPU upon interrupt entry. +#if 1 // B1832: interrupt stack changed to exception stack if exception is detected. + mfsr r12, AVR32_SR + bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE + cp.w r12, 110b + brlo _int2_normal + lddsp r12, sp[0 * 4] + stdsp sp[6 * 4], r12 + lddsp r12, sp[1 * 4] + stdsp sp[7 * 4], r12 + lddsp r12, sp[3 * 4] + sub sp, -6 * 4 + rete +_int2_normal: +#endif + mov r12, 2 // Pass the int_lev parameter to the _get_interrupt_handler function. + mcall __get_interrupt_handler + cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. + movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. + rete // If this was a spurious interrupt (R12 == NULL), return from event handler. + +_int3: + // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the + // CPU upon interrupt entry. +#if 1 // B1832: interrupt stack changed to exception stack if exception is detected. + mfsr r12, AVR32_SR + bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE + cp.w r12, 110b + brlo _int3_normal + lddsp r12, sp[0 * 4] + stdsp sp[6 * 4], r12 + lddsp r12, sp[1 * 4] + stdsp sp[7 * 4], r12 + lddsp r12, sp[3 * 4] + sub sp, -6 * 4 + rete +_int3_normal: +#endif + mov r12, 3 // Pass the int_lev parameter to the _get_interrupt_handler function. + mcall __get_interrupt_handler + cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. + movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. + rete // If this was a spurious interrupt (R12 == NULL), return from event handler. + + +// Constant data area. + + ALIGN 2 + + // Import symbols. + EXTERN SCALLYield + EXTERN _get_interrupt_handler +__SCALLYield: + DC32 SCALLYield +__get_interrupt_handler: + DC32 _get_interrupt_handler + + // Values to store in the interrupt priority registers for the various interrupt priority levels. + // The interrupt priority registers contain the interrupt priority level and + // the EVBA-relative interrupt vector offset. + PUBLIC ipr_val +ipr_val: + DC32 (INT0 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int0 - _evba),\ + (INT1 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int1 - _evba),\ + (INT2 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int2 - _evba),\ + (INT3 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int3 - _evba) + + + END + + +//! \endverbatim +//! @} diff --git a/portable/IAR/AVR32_UC3/port.c b/portable/IAR/AVR32_UC3/port.c new file mode 100644 index 000000000..dbe121cca --- /dev/null +++ b/portable/IAR/AVR32_UC3/port.c @@ -0,0 +1,446 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT AND BSD-3-Clause + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*This file has been prepared for Doxygen automatic documentation generation.*/ + +/*! \file ********************************************************************* + * + * \brief FreeRTOS port source for AVR32 UC3. + * + * - Compiler: IAR EWAVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation (Now Microchip): + * https://www.microchip.com \n + * Support and FAQ: https://www.microchip.com/support/ + * + *****************************************************************************/ + +/* + * Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* AVR32 UC3 includes. */ +#include +#include +#include "gpio.h" + +#if configDBG + #include "usart.h" +#endif + +#if ( configTICK_USE_TC == 1 ) + #include "tc.h" +#endif + + +/* Constants required to setup the task context. */ +#define portINITIAL_SR ( ( StackType_t ) 0x00400000 ) /* AVR32 : [M2:M0]=001 I1M=0 I0M=0, GM=0 */ +#define portINSTRUCTION_SIZE ( ( StackType_t ) 0 ) + +/* Each task maintains its own critical nesting variable. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) +volatile uint32_t ulCriticalNesting = 9999UL; + +#if ( configTICK_USE_TC == 0 ) + static void prvScheduleNextTick( void ); +#else + static void prvClearTcInt( void ); +#endif + +/* Setup the timer to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/*-----------------------------------------------------------*/ + +/* + * Low-level initialization routine called during startup, before the main + * function. + */ +int __low_level_init( void ) +{ + #if configHEAP_INIT + #pragma segment = "HEAP" + BaseType_t * pxMem; + #endif + + /* Enable exceptions. */ + ENABLE_ALL_EXCEPTIONS(); + + /* Initialize interrupt handling. */ + INTC_init_interrupts(); + + #if configHEAP_INIT + { + /* Initialize the heap used by malloc. */ + for( pxMem = __segment_begin( "HEAP" ); pxMem < ( BaseType_t * ) __segment_end( "HEAP" ); ) + { + *pxMem++ = 0xA5A5A5A5; + } + } + #endif + + /* Code section present if and only if the debug trace is activated. */ + #if configDBG + { + static const gpio_map_t DBG_USART_GPIO_MAP = + { + { configDBG_USART_RX_PIN, configDBG_USART_RX_FUNCTION }, + { configDBG_USART_TX_PIN, configDBG_USART_TX_FUNCTION } + }; + + static const usart_options_t DBG_USART_OPTIONS = + { + .baudrate = configDBG_USART_BAUDRATE, + .charlength = 8, + .paritytype = USART_NO_PARITY, + .stopbits = USART_1_STOPBIT, + .channelmode = USART_NORMAL_CHMODE + }; + + /* Initialize the USART used for the debug trace with the configured parameters. */ + extern volatile avr32_usart_t * volatile stdio_usart_base; + stdio_usart_base = configDBG_USART; + gpio_enable_module( DBG_USART_GPIO_MAP, + sizeof( DBG_USART_GPIO_MAP ) / sizeof( DBG_USART_GPIO_MAP[ 0 ] ) ); + usart_init_rs232( configDBG_USART, &DBG_USART_OPTIONS, configCPU_CLOCK_HZ ); + } + #endif /* if configDBG */ + + /* Request initialization of data segments. */ + return 1; +} +/*-----------------------------------------------------------*/ + +/* Added as there is no such function in FreeRTOS. */ +void * pvPortRealloc( void * pv, + size_t xWantedSize ) +{ + void * pvReturn; + + vTaskSuspendAll(); + { + pvReturn = realloc( pv, xWantedSize ); + } + xTaskResumeAll(); + + return pvReturn; +} +/*-----------------------------------------------------------*/ + +/* The cooperative scheduler requires a normal IRQ service routine to + * simply increment the system tick. */ + +/* The preemptive scheduler is defined as "naked" as the full context is saved + * on entry as part of the context switch. */ +#pragma shadow_registers = full /* Naked. */ +static void vTick( void ) +{ + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT_OS_INT(); + + #if ( configTICK_USE_TC == 1 ) + /* Clear the interrupt flag. */ + prvClearTcInt(); + #else + + /* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ) + * clock cycles from now. */ + prvScheduleNextTick(); + #endif + + /* Because FreeRTOS is not supposed to run with nested interrupts, put all OS + * calls in a critical section . */ + portENTER_CRITICAL(); + xTaskIncrementTick(); + portEXIT_CRITICAL(); + + /* Restore the context of the "elected task". */ + portRESTORE_CONTEXT_OS_INT(); +} +/*-----------------------------------------------------------*/ + +#pragma shadow_registers = full /* Naked. */ +void SCALLYield( void ) +{ + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT_SCALL(); + vTaskSwitchContext(); + portRESTORE_CONTEXT_SCALL(); +} +/*-----------------------------------------------------------*/ + +/* The code generated by the GCC compiler uses the stack in different ways at + * different optimisation levels. The interrupt flags can therefore not always + * be saved to the stack. Instead the critical section nesting level is stored + * in a variable, which is then saved as part of the stack context. */ +#pragma optimize = no_inline +void vPortEnterCritical( void ) +{ + /* Disable interrupts */ + portDISABLE_INTERRUPTS(); + + /* Now that interrupts are disabled, ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +#pragma optimize = no_inline +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + ulCriticalNesting--; + + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Enable all interrupt/exception. */ + portENABLE_INTERRUPTS(); + } + } +} +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Setup the initial stack of the task. The stack is set exactly as + * expected by the portRESTORE_CONTEXT() macro. */ + + /* When the task starts, it will expect to find the function parameter in R12. */ + pxTopOfStack--; + *pxTopOfStack-- = ( StackType_t ) 0x08080808; /* R8 */ + *pxTopOfStack-- = ( StackType_t ) 0x09090909; /* R9 */ + *pxTopOfStack-- = ( StackType_t ) 0x0A0A0A0A; /* R10 */ + *pxTopOfStack-- = ( StackType_t ) 0x0B0B0B0B; /* R11 */ + *pxTopOfStack-- = ( StackType_t ) pvParameters; /* R12 */ + *pxTopOfStack-- = ( StackType_t ) 0xDEADBEEF; /* R14/LR */ + *pxTopOfStack-- = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; /* R15/PC */ + *pxTopOfStack-- = ( StackType_t ) portINITIAL_SR; /* SR */ + *pxTopOfStack-- = ( StackType_t ) 0xFF0000FF; /* R0 */ + *pxTopOfStack-- = ( StackType_t ) 0x01010101; /* R1 */ + *pxTopOfStack-- = ( StackType_t ) 0x02020202; /* R2 */ + *pxTopOfStack-- = ( StackType_t ) 0x03030303; /* R3 */ + *pxTopOfStack-- = ( StackType_t ) 0x04040404; /* R4 */ + *pxTopOfStack-- = ( StackType_t ) 0x05050505; /* R5 */ + *pxTopOfStack-- = ( StackType_t ) 0x06060606; /* R6 */ + *pxTopOfStack-- = ( StackType_t ) 0x07070707; /* R7 */ + *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_NESTING; /* ulCriticalNesting */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + portRESTORE_CONTEXT(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the AVR32 port will require this function as there + * is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +/* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ) + * clock cycles from now. */ +#if ( configTICK_USE_TC == 0 ) + static void prvScheduleFirstTick( void ) + { + uint32_t lCycles; + + lCycles = Get_system_register( AVR32_COUNT ); + lCycles += ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ); + + /* If lCycles ends up to be 0, make it 1 so that the COMPARE and exception */ + /* generation feature does not get disabled. */ + if( 0 == lCycles ) + { + lCycles++; + } + + Set_system_register( AVR32_COMPARE, lCycles ); + } + + #pragma optimize = no_inline + static void prvScheduleNextTick( void ) + { + uint32_t lCycles, lCount; + + lCycles = Get_system_register( AVR32_COMPARE ); + lCycles += ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ); + + /* If lCycles ends up to be 0, make it 1 so that the COMPARE and exception */ + /* generation feature does not get disabled. */ + if( 0 == lCycles ) + { + lCycles++; + } + + lCount = Get_system_register( AVR32_COUNT ); + + if( lCycles < lCount ) + { /* We missed a tick, recover for the next. */ + lCycles += ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ); + } + + Set_system_register( AVR32_COMPARE, lCycles ); + } +#else /* if ( configTICK_USE_TC == 0 ) */ + #pragma optimize = no_inline + static void prvClearTcInt( void ) + { + AVR32_TC.channel[ configTICK_TC_CHANNEL ].sr; + } +#endif /* if ( configTICK_USE_TC == 0 ) */ +/*-----------------------------------------------------------*/ + +/* Setup the timer to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ) +{ + #if ( configTICK_USE_TC == 1 ) + volatile avr32_tc_t * tc = &AVR32_TC; + + /* Options for waveform generation. */ + tc_waveform_opt_t waveform_opt = + { + .channel = configTICK_TC_CHANNEL, /* Channel selection. */ + + .bswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOB. */ + .beevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOB. */ + .bcpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOB. */ + .bcpb = TC_EVT_EFFECT_NOOP, /* RB compare effect on TIOB. */ + + .aswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOA. */ + .aeevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOA. */ + .acpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOA: toggle. */ + .acpa = TC_EVT_EFFECT_NOOP, /* RA compare effect on TIOA: toggle (other possibilities are none, set and clear). */ + + .wavsel = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER, /* Waveform selection: Up mode without automatic trigger on RC compare. */ + .enetrg = FALSE, /* External event trigger enable. */ + .eevt = 0, /* External event selection. */ + .eevtedg = TC_SEL_NO_EDGE, /* External event edge selection. */ + .cpcdis = FALSE, /* Counter disable when RC compare. */ + .cpcstop = FALSE, /* Counter clock stopped with RC compare. */ + + .burst = FALSE, /* Burst signal selection. */ + .clki = FALSE, /* Clock inversion. */ + .tcclks = TC_CLOCK_SOURCE_TC2 /* Internal source clock 2. */ + }; + + tc_interrupt_t tc_interrupt = + { + .etrgs = 0, + .ldrbs = 0, + .ldras = 0, + .cpcs = 1, + .cpbs = 0, + .cpas = 0, + .lovrs = 0, + .covfs = 0, + }; + #endif /* if ( configTICK_USE_TC == 1 ) */ + + /* Disable all interrupt/exception. */ + portDISABLE_INTERRUPTS(); + + /* Register the compare interrupt handler to the interrupt controller and + * enable the compare interrupt. */ + + #if ( configTICK_USE_TC == 1 ) + { + INTC_register_interrupt( ( __int_handler ) & vTick, configTICK_TC_IRQ, INT0 ); + + /* Initialize the timer/counter. */ + tc_init_waveform( tc, &waveform_opt ); + + /* Set the compare triggers. + * Remember TC counter is 16-bits, so counting second is not possible! + * That's why we configure it to count ms. */ + tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4 ) / configTICK_RATE_HZ ); + + tc_configure_interrupts( tc, configTICK_TC_CHANNEL, &tc_interrupt ); + + /* Start the timer/counter. */ + tc_start( tc, configTICK_TC_CHANNEL ); + } + #else /* if ( configTICK_USE_TC == 1 ) */ + { + INTC_register_interrupt( ( __int_handler ) & vTick, AVR32_CORE_COMPARE_IRQ, INT0 ); + prvScheduleFirstTick(); + } + #endif /* if ( configTICK_USE_TC == 1 ) */ +} diff --git a/portable/IAR/AVR32_UC3/portmacro.h b/portable/IAR/AVR32_UC3/portmacro.h new file mode 100644 index 000000000..036833f8f --- /dev/null +++ b/portable/IAR/AVR32_UC3/portmacro.h @@ -0,0 +1,692 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT AND BSD-3-Clause + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*This file has been prepared for Doxygen automatic documentation generation.*/ + +/*! \file ********************************************************************* + * + * \brief FreeRTOS port header for AVR32 UC3. + * + * - Compiler: IAR EWAVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation (Now Microchip): + * https://www.microchip.com + * Support and FAQ: https://www.microchip.com/support + * + *****************************************************************************/ + +/* + * Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ +#include +#include "intc.h" +#include "compiler.h" + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#define TASK_DELAY_MS( x ) ( ( x ) / portTICK_PERIOD_MS ) +#define TASK_DELAY_S( x ) ( ( x ) * 1000 / portTICK_PERIOD_MS ) +#define TASK_DELAY_MIN( x ) ( ( x ) * 60 * 1000 / portTICK_PERIOD_MS ) + +#define configTICK_TC_IRQ ATPASTE2( AVR32_TC_IRQ, configTICK_TC_CHANNEL ) + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +#define portNOP() { __asm__ __volatile__ ( "nop" ); } +/*-----------------------------------------------------------*/ + + +/*-----------------------------------------------------------*/ + +/* INTC-specific. */ +#define DISABLE_ALL_EXCEPTIONS() Disable_global_exception() +#define ENABLE_ALL_EXCEPTIONS() Enable_global_exception() + +#define DISABLE_ALL_INTERRUPTS() Disable_global_interrupt() +#define ENABLE_ALL_INTERRUPTS() Enable_global_interrupt() + +#define DISABLE_INT_LEVEL( int_lev ) Disable_interrupt_level( int_lev ) +#define ENABLE_INT_LEVEL( int_lev ) Enable_interrupt_level( int_lev ) + + +/* + * Debug trace. + * Activated if and only if configDBG is nonzero. + * Prints a formatted string to stdout. + * The current source file name and line number are output with a colon before + * the formatted string. + * A carriage return and a linefeed are appended to the output. + * stdout is redirected to the USART configured by configDBG_USART. + * The parameters are the same as for the standard printf function. + * There is no return value. + * SHALL NOT BE CALLED FROM WITHIN AN INTERRUPT as fputs and printf use malloc, + * which is interrupt-unsafe with the current __malloc_lock and __malloc_unlock. + */ +#if configDBG + #define portDBG_TRACE( ... ) \ + { \ + fputs( __FILE__ ":" ASTRINGZ( __LINE__ ) ": ", stdout ); \ + printf( __VA_ARGS__ ); \ + fputs( "\r\n", stdout ); \ + } +#else + #define portDBG_TRACE( ... ) +#endif + + +/* Critical section management. */ +#define portDISABLE_INTERRUPTS() DISABLE_ALL_INTERRUPTS() +#define portENABLE_INTERRUPTS() ENABLE_ALL_INTERRUPTS() + + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); + + +/* Added as there is no such function in FreeRTOS. */ +extern void * pvPortRealloc( void * pv, + size_t xSize ); +/*-----------------------------------------------------------*/ + + +/*=============================================================================================*/ + +/* + * Restore Context for cases other than INTi. + */ +#define portRESTORE_CONTEXT() \ + { \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void * volatile pxCurrentTCB; \ + \ + __asm__ __volatile__ ( \ + /* Set SP to point to new stack */ \ + "mov r8, LWRD("ASTRINGZ ( pxCurrentTCB ) ") \n\t" \ + "orh r8, HWRD("ASTRINGZ ( pxCurrentTCB ) ") \n\t" \ + "ld.w r0, r8[0] \n\t" \ + "ld.w sp, r0[0] \n\t" \ + \ + /* Restore ulCriticalNesting variable */ \ + "ld.w r0, sp++ \n\t" \ + "mov r8, LWRD("ASTRINGZ ( ulCriticalNesting ) ") \n\t" \ + "orh r8, HWRD("ASTRINGZ ( ulCriticalNesting ) ") \n\t" \ + "st.w r8[0], r0 \n\t" \ + \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t" \ + /* R0-R7 should not be used below this line */ \ + /* Skip PC and SR (will do it at the end) */ \ + "sub sp, -2*4 \n\t" \ + /* Restore R8..R12 and LR */ \ + "ldm sp++, r8-r12, lr \n\t" \ + /* Restore SR */ \ + "ld.w r0, sp[-8*4] \n\t" /* R0 is modified, is restored later. */ \ + "mtsr "ASTRINGZ ( AVR32_SR ) ", r0 \n\t" \ + /* Restore r0 */ \ + "ld.w r0, sp[-9*4] \n\t" \ + /* Restore PC */ \ + "ld.w pc, sp[-7*4]" /* Get PC from stack - PC is the 7th register saved */ \ + ); \ + \ + /* Force import of global symbols from assembly */ \ + ulCriticalNesting; \ + pxCurrentTCB; \ + } + + +/* + * portSAVE_CONTEXT_INT() and portRESTORE_CONTEXT_INT(): for INT0..3 exceptions. + * portSAVE_CONTEXT_SCALL() and portRESTORE_CONTEXT_SCALL(): for the scall exception. + * + * Had to make different versions because registers saved on the system stack + * are not the same between INT0..3 exceptions and the scall exception. + */ + +/* Task context stack layout: */ +/* R8 (*) */ +/* R9 (*) */ +/* R10 (*) */ +/* R11 (*) */ +/* R12 (*) */ +/* R14/LR (*) */ +/* R15/PC (*) */ +/* SR (*) */ +/* R0 */ +/* R1 */ +/* R2 */ +/* R3 */ +/* R4 */ +/* R5 */ +/* R6 */ +/* R7 */ +/* ulCriticalNesting */ +/* (*) automatically done for INT0..INT3, but not for SCALL */ + +/* + * The ISR used for the scheduler tick depends on whether the cooperative or + * the preemptive scheduler is being used. + */ +#if configUSE_PREEMPTION == 0 + +/* + * portSAVE_CONTEXT_OS_INT() for OS Tick exception. + */ + #define portSAVE_CONTEXT_OS_INT() \ + { \ + /* Save R0..R7 */ \ + __asm__ __volatile__ ( "stm --sp, r0-r7" ); \ + \ + /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ + /* there is also no context save. */ \ + } + +/* + * portRESTORE_CONTEXT_OS_INT() for Tick exception. + */ + #define portRESTORE_CONTEXT_OS_INT() \ + { \ + __asm__ __volatile__ ( \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t" \ + \ + /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ + /* there is also no context restore. */ \ + "rete" \ + ); \ + } + +#else /* if configUSE_PREEMPTION == 0 */ + +/* + * portSAVE_CONTEXT_OS_INT() for OS Tick exception. + */ + #define portSAVE_CONTEXT_OS_INT() \ + { \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void * volatile pxCurrentTCB; \ + \ + /* When we come here */ \ + /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \ + \ + __asm__ __volatile__ ( \ + /* Save R0..R7 */ \ + "stm --sp, r0-r7 \n\t" \ + \ + /* Save ulCriticalNesting variable - R0 is overwritten */ \ + "mov r8, LWRD("ASTRINGZ ( ulCriticalNesting ) ") \n\t" \ + "orh r8, HWRD("ASTRINGZ ( ulCriticalNesting ) ") \n\t" \ + "ld.w r0, r8[0] \n\t" \ + "st.w --sp, r0 \n\t" \ + \ + /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ + /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ + /* level and allow other lower interrupt level to occur). */ \ + /* In this case we don't want to do a task switch because we don't know what the stack */ \ + /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \ + /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \ + /* will just be restoring the interrupt handler, no way!!! */ \ + /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \ + "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */ \ + "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */ \ + "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */ \ + "brhi LABEL_INT_SKIP_SAVE_CONTEXT_"ASTRINGZ ( __LINE__ ) " \n\t" \ + \ + /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \ + /* NOTE: we don't enter a critical section here because all interrupt handlers */ \ + /* MUST perform a SAVE_CONTEXT/RESTORE_CONTEXT in the same way as */ \ + /* portSAVE_CONTEXT_OS_INT/port_RESTORE_CONTEXT_OS_INT if they call OS functions. */ \ + /* => all interrupt handlers must use portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR. */ \ + "mov r8, LWRD("ASTRINGZ ( pxCurrentTCB ) ") \n\t" \ + "orh r8, HWRD("ASTRINGZ ( pxCurrentTCB ) ") \n\t" \ + "ld.w r0, r8[0] \n\t" \ + "st.w r0[0], sp \n" \ + \ + "LABEL_INT_SKIP_SAVE_CONTEXT_"ASTRINGZ ( __LINE__ ) ":" \ + ); \ + } + +/* + * portRESTORE_CONTEXT_OS_INT() for Tick exception. + */ + #define portRESTORE_CONTEXT_OS_INT() \ + { \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void * volatile pxCurrentTCB; \ + \ + /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ + /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ + /* level and allow other lower interrupt level to occur). */ \ + /* In this case we don't want to do a task switch because we don't know what the stack */ \ + /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \ + /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \ + /* will just be restoring the interrupt handler, no way!!! */ \ + __asm__ __volatile__ ( \ + "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */ \ + "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */ \ + "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */ \ + "brhi LABEL_INT_SKIP_RESTORE_CONTEXT_"ASTRINGZ ( __LINE__ ) \ + ); \ + \ + /* Else */ \ + /* because it is here safe, always call vTaskSwitchContext() since an OS tick occurred. */ \ + /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */ \ + portENTER_CRITICAL(); \ + vTaskSwitchContext(); \ + portEXIT_CRITICAL(); \ + \ + /* Restore all registers */ \ + \ + __asm__ __volatile__ ( \ + /* Set SP to point to new stack */ \ + "mov r8, LWRD("ASTRINGZ ( pxCurrentTCB ) ") \n\t" \ + "orh r8, HWRD("ASTRINGZ ( pxCurrentTCB ) ") \n\t" \ + "ld.w r0, r8[0] \n\t" \ + "ld.w sp, r0[0] \n" \ + \ + "LABEL_INT_SKIP_RESTORE_CONTEXT_"ASTRINGZ ( __LINE__ ) ": \n\t" \ + \ + /* Restore ulCriticalNesting variable */ \ + "ld.w r0, sp++ \n\t" \ + "mov r8, LWRD("ASTRINGZ ( ulCriticalNesting ) ") \n\t" \ + "orh r8, HWRD("ASTRINGZ ( ulCriticalNesting ) ") \n\t" \ + "st.w r8[0], r0 \n\t" \ + \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t" \ + \ + /* Now, the stack should be R8..R12, LR, PC and SR */ \ + "rete" \ + ); \ + \ + /* Force import of global symbols from assembly */ \ + ulCriticalNesting; \ + pxCurrentTCB; \ + } + +#endif /* if configUSE_PREEMPTION == 0 */ + + +/* + * portSAVE_CONTEXT_SCALL() for SupervisorCALL exception. + * + * NOTE: taskYIELD()(== SCALL) MUST NOT be called in a mode > supervisor mode. + * + */ +#define portSAVE_CONTEXT_SCALL() \ + { \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void * volatile pxCurrentTCB; \ + \ + /* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */ \ + /* If SR[M2:M0] == 001 */ \ + /* PC and SR are on the stack. */ \ + /* Else (other modes) */ \ + /* Nothing on the stack. */ \ + \ + /* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */ \ + /* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */ \ + /* in an interrupt|exception handler. */ \ + \ + __asm__ __volatile__ ( \ + /* in order to save R0-R7 */ \ + "sub sp, 6*4 \n\t" \ + /* Save R0..R7 */ \ + "stm --sp, r0-r7 \n\t" \ + \ + /* in order to save R8-R12 and LR */ \ + /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \ + "sub r7, sp,-16*4 \n\t" \ + /* Copy PC and SR in other places in the stack. */ \ + "ld.w r0, r7[-2*4] \n\t" /* Read SR */ \ + "st.w r7[-8*4], r0 \n\t" /* Copy SR */ \ + "ld.w r0, r7[-1*4] \n\t" /* Read PC */ \ + "st.w r7[-7*4], r0 \n\t" /* Copy PC */ \ + \ + /* Save R8..R12 and LR on the stack. */ \ + "stm --r7, r8-r12, lr \n\t" \ + \ + /* Arriving here we have the following stack organizations: */ \ + /* R8..R12, LR, PC, SR, R0..R7. */ \ + \ + /* Now we can finalize the save. */ \ + \ + /* Save ulCriticalNesting variable - R0 is overwritten */ \ + "mov r8, LWRD("ASTRINGZ ( ulCriticalNesting ) ") \n\t" \ + "orh r8, HWRD("ASTRINGZ ( ulCriticalNesting ) ") \n\t" \ + "ld.w r0, r8[0] \n\t" \ + "st.w --sp, r0" \ + ); \ + \ + /* Disable the its which may cause a context switch (i.e. cause a change of */ \ + /* pxCurrentTCB). */ \ + /* Basically, all accesses to the pxCurrentTCB structure should be put in a */ \ + /* critical section because it is a global structure. */ \ + portENTER_CRITICAL(); \ + \ + /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \ + __asm__ __volatile__ ( \ + "mov r8, LWRD("ASTRINGZ ( pxCurrentTCB ) ") \n\t" \ + "orh r8, HWRD("ASTRINGZ ( pxCurrentTCB ) ") \n\t" \ + "ld.w r0, r8[0] \n\t" \ + "st.w r0[0], sp" \ + ); \ + } + +/* + * portRESTORE_CONTEXT() for SupervisorCALL exception. + */ +#define portRESTORE_CONTEXT_SCALL() \ + { \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void * volatile pxCurrentTCB; \ + \ + /* Restore all registers */ \ + \ + /* Set SP to point to new stack */ \ + __asm__ __volatile__ ( \ + "mov r8, LWRD("ASTRINGZ ( pxCurrentTCB ) ") \n\t" \ + "orh r8, HWRD("ASTRINGZ ( pxCurrentTCB ) ") \n\t" \ + "ld.w r0, r8[0] \n\t" \ + "ld.w sp, r0[0]" \ + ); \ + \ + /* Leave pxCurrentTCB variable access critical section */ \ + portEXIT_CRITICAL(); \ + \ + __asm__ __volatile__ ( \ + /* Restore ulCriticalNesting variable */ \ + "ld.w r0, sp++ \n\t" \ + "mov r8, LWRD("ASTRINGZ ( ulCriticalNesting ) ") \n\t" \ + "orh r8, HWRD("ASTRINGZ ( ulCriticalNesting ) ") \n\t" \ + "st.w r8[0], r0 \n\t" \ + \ + /* skip PC and SR */ \ + /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \ + "sub r7, sp, -10*4 \n\t" \ + /* Restore r8-r12 and LR */ \ + "ldm r7++, r8-r12, lr \n\t" \ + \ + /* RETS will take care of the extra PC and SR restore. */ \ + /* So, we have to prepare the stack for this. */ \ + "ld.w r0, r7[-8*4] \n\t" /* Read SR */ \ + "st.w r7[-2*4], r0 \n\t" /* Copy SR */ \ + "ld.w r0, r7[-7*4] \n\t" /* Read PC */ \ + "st.w r7[-1*4], r0 \n\t" /* Copy PC */ \ + \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t" \ + \ + "sub sp, -6*4 \n\t" \ + \ + "rets" \ + ); \ + \ + /* Force import of global symbols from assembly */ \ + ulCriticalNesting; \ + pxCurrentTCB; \ + } + + +/* + * The ISR used depends on whether the cooperative or + * the preemptive scheduler is being used. + */ +#if configUSE_PREEMPTION == 0 + +/* + * ISR entry and exit macros. These are only required if a task switch + * is required from the ISR. + */ + #define portENTER_SWITCHING_ISR() \ + { \ + /* Save R0..R7 */ \ + __asm__ __volatile__ ( "stm --sp, r0-r7" ); \ + \ + /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ + /* there is also no context save. */ \ + } + +/* + * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1 + */ + #define portEXIT_SWITCHING_ISR() \ + { \ + __asm__ __volatile__ ( \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t" \ + \ + /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ + /* there is also no context restore. */ \ + "rete" \ + ); \ + } + +#else /* if configUSE_PREEMPTION == 0 */ + +/* + * ISR entry and exit macros. These are only required if a task switch + * is required from the ISR. + */ + #define portENTER_SWITCHING_ISR() \ + { \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void * volatile pxCurrentTCB; \ + \ + /* When we come here */ \ + /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \ + \ + __asm__ __volatile__ ( \ + /* Save R0..R7 */ \ + "stm --sp, r0-r7 \n\t" \ + \ + /* Save ulCriticalNesting variable - R0 is overwritten */ \ + "mov r8, LWRD("ASTRINGZ ( ulCriticalNesting ) ") \n\t" \ + "orh r8, HWRD("ASTRINGZ ( ulCriticalNesting ) ") \n\t" \ + "ld.w r0, r8[0] \n\t" \ + "st.w --sp, r0 \n\t" \ + \ + /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ + /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ + /* level and allow other lower interrupt level to occur). */ \ + /* In this case we don't want to do a task switch because we don't know what the stack */ \ + /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \ + /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \ + /* will just be restoring the interrupt handler, no way!!! */ \ + /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \ + "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */ \ + "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */ \ + "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */ \ + "brhi LABEL_ISR_SKIP_SAVE_CONTEXT_"ASTRINGZ ( __LINE__ ) " \n\t" \ + \ + /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \ + "mov r8, LWRD("ASTRINGZ ( pxCurrentTCB ) ") \n\t" \ + "orh r8, HWRD("ASTRINGZ ( pxCurrentTCB ) ") \n\t" \ + "ld.w r0, r8[0] \n\t" \ + "st.w r0[0], sp \n" \ + \ + "LABEL_ISR_SKIP_SAVE_CONTEXT_"ASTRINGZ ( __LINE__ ) ":" \ + ); \ + } + + +/* + * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1 + */ + #define portEXIT_SWITCHING_ISR() \ + { \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void * volatile pxCurrentTCB; \ + \ + __asm__ __volatile__ ( \ + /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ + /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ + /* level and allow other lower interrupt level to occur). */ \ + /* In this case it's of no use to switch context and restore a new SP because we purposely */ \ + /* did not previously save SP in its TCB. */ \ + "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */ \ + "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */ \ + "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */ \ + "brhi LABEL_ISR_SKIP_RESTORE_CONTEXT_"ASTRINGZ ( __LINE__ ) " \n\t" \ + \ + /* If a switch is required then we just need to call */ \ + /* vTaskSwitchContext() as the context has already been */ \ + /* saved. */ \ + "cp.w r12, 1 \n\t" /* Check if Switch context is required. */ \ + "brne LABEL_ISR_RESTORE_CONTEXT_"ASTRINGZ ( __LINE__ ) ":C" \ + ); \ + \ + /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */ \ + portENTER_CRITICAL(); \ + vTaskSwitchContext(); \ + portEXIT_CRITICAL(); \ + \ + __asm__ __volatile__ ( \ + "LABEL_ISR_RESTORE_CONTEXT_"ASTRINGZ ( __LINE__ ) ": \n\t" \ + /* Restore the context of which ever task is now the highest */ \ + /* priority that is ready to run. */ \ + \ + /* Restore all registers */ \ + \ + /* Set SP to point to new stack */ \ + "mov r8, LWRD("ASTRINGZ ( pxCurrentTCB ) ") \n\t" \ + "orh r8, HWRD("ASTRINGZ ( pxCurrentTCB ) ") \n\t" \ + "ld.w r0, r8[0] \n\t" \ + "ld.w sp, r0[0] \n" \ + \ + "LABEL_ISR_SKIP_RESTORE_CONTEXT_"ASTRINGZ ( __LINE__ ) ": \n\t" \ + \ + /* Restore ulCriticalNesting variable */ \ + "ld.w r0, sp++ \n\t" \ + "mov r8, LWRD("ASTRINGZ ( ulCriticalNesting ) ") \n\t" \ + "orh r8, HWRD("ASTRINGZ ( ulCriticalNesting ) ") \n\t" \ + "st.w r8[0], r0 \n\t" \ + \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t" \ + \ + /* Now, the stack should be R8..R12, LR, PC and SR */ \ + "rete" \ + ); \ + \ + /* Force import of global symbols from assembly */ \ + ulCriticalNesting; \ + pxCurrentTCB; \ + } + +#endif /* if configUSE_PREEMPTION == 0 */ + + +#define portYIELD() { __asm__ __volatile__ ( "scall" ); } + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/IAR/AVR32_UC3/read.c b/portable/IAR/AVR32_UC3/read.c new file mode 100644 index 000000000..639d1f8f8 --- /dev/null +++ b/portable/IAR/AVR32_UC3/read.c @@ -0,0 +1,129 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT AND BSD-3-Clause + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ + +/*! \file ********************************************************************* +* +* \brief System-specific implementation of the \ref __read function used by +* the standard library. +* +* - Compiler: IAR EWAVR32 +* - Supported devices: All AVR32 devices with a USART module can be used. +* - AppNote: +* +* \author Atmel Corporation (Now Microchip): +* https://www.microchip.com \n +* Support and FAQ: https://www.microchip.com/support/ +* +******************************************************************************/ + +/* + * Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include +#include +#include "usart.h" + + +_STD_BEGIN + + +#pragma module_name = "?__read" + + +extern volatile avr32_usart_t * volatile stdio_usart_base; + + +/*! \brief Reads a number of bytes, at most \a size, into the memory area + * pointed to by \a buffer. + * + * \param handle File handle to read from. + * \param buffer Pointer to buffer to write read bytes to. + * \param size Number of bytes to read. + * + * \return The number of bytes read, \c 0 at the end of the file, or + * \c _LLIO_ERROR on failure. + */ +size_t __read( int handle, + uint8_t * buffer, + size_t size ) +{ + int nChars = 0; + + /* This implementation only reads from stdin. */ + /* For all other file handles, it returns failure. */ + if( handle != _LLIO_STDIN ) + { + return _LLIO_ERROR; + } + + for( ; size > 0; --size ) + { + int c = usart_getchar( stdio_usart_base ); + + if( c < 0 ) + { + break; + } + + *buffer++ = c; + ++nChars; + } + + return nChars; +} + + +_STD_END diff --git a/portable/IAR/AVR32_UC3/write.c b/portable/IAR/AVR32_UC3/write.c new file mode 100644 index 000000000..5ac796332 --- /dev/null +++ b/portable/IAR/AVR32_UC3/write.c @@ -0,0 +1,136 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT AND BSD-3-Clause + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ + +/*! \file ********************************************************************* +* +* \brief System-specific implementation of the \ref __write function used by +* the standard library. +* +* - Compiler: IAR EWAVR32 +* - Supported devices: All AVR32 devices with a USART module can be used. +* - AppNote: +* +* \author Atmel Corporation (Now Microchip): +* https://www.microchip.com \n +* Support and FAQ: https://www.microchip.com/support +* +******************************************************************************/ + +/* + * Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include +#include +#include "usart.h" + + +_STD_BEGIN + + +#pragma module_name = "?__write" + + +/*! Pointer to the base of the USART module instance to use for stdio. */ +__no_init volatile avr32_usart_t * volatile stdio_usart_base; + + +/*! \brief Writes a number of bytes, at most \a size, from the memory area + * pointed to by \a buffer. + * + * If \a buffer is zero then \ref __write performs flushing of internal buffers, + * if any. In this case, \a handle can be \c -1 to indicate that all handles + * should be flushed. + * + * \param handle File handle to write to. + * \param buffer Pointer to buffer to read bytes to write from. + * \param size Number of bytes to write. + * + * \return The number of bytes written, or \c _LLIO_ERROR on failure. + */ +size_t __write( int handle, + const uint8_t * buffer, + size_t size ) +{ + size_t nChars = 0; + + if( buffer == 0 ) + { + /* This means that we should flush internal buffers. */ + return 0; + } + + /* This implementation only writes to stdout and stderr. */ + /* For all other file handles, it returns failure. */ + if( ( handle != _LLIO_STDOUT ) && ( handle != _LLIO_STDERR ) ) + { + return _LLIO_ERROR; + } + + for( ; size != 0; --size ) + { + if( usart_putchar( stdio_usart_base, *buffer++ ) < 0 ) + { + return _LLIO_ERROR; + } + + ++nChars; + } + + return nChars; +} + + +_STD_END diff --git a/portable/IAR/AVR_AVRDx/port.c b/portable/IAR/AVR_AVRDx/port.c new file mode 100644 index 000000000..07269f0f6 --- /dev/null +++ b/portable/IAR/AVR_AVRDx/port.c @@ -0,0 +1,301 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include +#include "porthardware.h" +#include "FreeRTOS.h" +#include "task.h" + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the AVR port. +*----------------------------------------------------------*/ + +/* Start tasks with interrupts enables. */ +#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x80 ) + +/*-----------------------------------------------------------*/ + + +#define portBYTES_USED_BY_RETURN_ADDRESS 2 +#define portNO_CRITICAL_NESTING ( ( UBaseType_t ) 0 ) + +/* Stores the critical section nesting. This must not be initialised to 0. + * It will be initialised when a task starts. */ +UBaseType_t uxCriticalNesting = 0x50; + +/* + * Setup timer to generate a tick interrupt. + */ +static void prvSetupTimerInterrupt( void ); + +/* + * The IAR compiler does not have full support for inline assembler, so + * these are defined in the portmacro assembler file. + */ +extern void vPortYieldFromTick( void ); +extern void vPortStart( void ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + uint16_t usAddress; + StackType_t * pxTopOfHardwareStack; + + /* Simulate how the stack would look after a call to vPortYield(). */ + + /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */ + + /* The IAR compiler requires two stacks per task. First there is the + * hardware call stack which uses the AVR stack pointer. Second there is the + * software stack (local variables, parameter passing, etc.) which uses the + * AVR Y register. + * This function places both stacks within the memory block passed in as the + * first parameter. The hardware stack is placed at the bottom of the memory + * block. A gap is then left for the hardware stack to grow. Next the software + * stack is placed. The amount of space between the software and hardware + * stacks is defined by configCALL_STACK_SIZE. + * The first part of the stack is the hardware stack. Place the start + * address of the task on the hardware stack. */ + + /* Place a few bytes of known values on the bottom of the stack. + * This is just useful for debugging. */ + /**pxTopOfStack = 0x11; */ + /*pxTopOfStack--; */ + /**pxTopOfStack = 0x22; */ + /*pxTopOfStack--; */ + /**pxTopOfStack = 0x33; */ + /*pxTopOfStack--; */ + + /* Remember where the top of the hardware stack is - this is required + * below. */ + pxTopOfHardwareStack = pxTopOfStack; + + usAddress = ( uint16_t ) pxCode; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + usAddress >>= 8; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + /* Leave enough space for the hardware stack before starting the software + * stack. The '- 2' is because we have already used two spaces for the + * address of the start of the task. */ + pxTopOfStack -= ( configCALL_STACK_SIZE - 2 ); + + /* Next simulate the stack as if after a call to portSAVE_CONTEXT(). + * portSAVE_CONTEXT places the flags on the stack immediately after r0 + * to ensure the interrupts get disabled as soon as possible, and so ensuring + * the stack use is minimal should a context switch interrupt occur. */ + + *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */ + pxTopOfStack--; + *pxTopOfStack = portFLAGS_INT_ENABLED; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x00; /* RAMPZ */ + pxTopOfStack--; + + /* Next place the address of the hardware stack. This is required so + * the AVR stack pointer can be restored to point to the hardware stack. */ + pxTopOfHardwareStack -= portBYTES_USED_BY_RETURN_ADDRESS; + usAddress = ( uint16_t ) pxTopOfHardwareStack; + + /* SPL */ + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + /* SPH */ + usAddress >>= 8; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + /* Now the remaining registers. */ + *pxTopOfStack = ( StackType_t ) 0x01; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x13; /* R13 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x14; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x15; /* R15 */ + pxTopOfStack--; + + /* Place the parameter on the stack in the expected location. */ + usAddress = ( uint16_t ) pvParameters; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + usAddress >>= 8; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0x18; /* R18 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x19; /* R19 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x20; /* R20 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x21; /* R21 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x22; /* R22 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x23; /* R23 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x24; /* R24 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x25; /* R25 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x26; /* R26 X */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x27; /* R27 */ + pxTopOfStack--; + + /* The Y register is not stored as it is used as the software stack and + * gets saved into the task control block. */ + + *pxTopOfStack = ( StackType_t ) 0x30; /* R30 Z */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x031; /* R31 */ + + pxTopOfStack--; + *pxTopOfStack = portNO_CRITICAL_NESTING; /* Critical nesting is zero when the task starts. */ + + /*lint +e950 +e611 +e923 */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Setup the hardware to generate the tick. */ + prvSetupTimerInterrupt(); + + /* Restore the context of the first task that is going to run. + * Normally we would just call portRESTORE_CONTEXT() here, but as the IAR + * compiler does not fully support inline assembler we have to make a call.*/ + vPortStart(); + + /* Should not get here. */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* vPortEndScheduler is not implemented in this port. */ +} + +/*-----------------------------------------------------------*/ + +/* + * Setup timer to generate a tick interrupt. + */ +static void prvSetupTimerInterrupt( void ) +{ + TICK_init(); +} + +/*-----------------------------------------------------------*/ + +#if configUSE_PREEMPTION == 1 + +/* + * Tick ISR for preemptive scheduler. We can use a naked attribute as + * the context is saved at the start of vPortYieldFromTick(). The tick + * count is incremented after the context is saved. + */ + + __task void TICK_INT( void ) + { + vPortYieldFromTick(); + asm ( "reti" ); + } +#else + +/* + * Tick ISR for the cooperative scheduler. All this does is increment the + * tick count. We don't need to switch context, this can only be done by + * manual calls to taskYIELD(); + */ + + __interrupt void TICK_INT( void ) + { + /* Clear tick interrupt flag. */ + INT_FLAGS = INT_MASK; + + xTaskIncrementTick(); + } +#endif /* if configUSE_PREEMPTION == 1 */ + +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; +} + +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + uxCriticalNesting--; + + if( uxCriticalNesting == portNO_CRITICAL_NESTING ) + { + portENABLE_INTERRUPTS(); + } +} diff --git a/portable/IAR/AVR_AVRDx/porthardware.h b/portable/IAR/AVR_AVRDx/porthardware.h new file mode 100644 index 000000000..f9176f96b --- /dev/null +++ b/portable/IAR/AVR_AVRDx/porthardware.h @@ -0,0 +1,129 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ +#ifndef PORTHARDWARE_H +#define PORTHARDWARE_H + +#ifndef __IAR_SYSTEMS_ASM__ + #include +#endif +#include "FreeRTOSConfig.h" + +/*-----------------------------------------------------------*/ + +#if ( configUSE_TIMER_INSTANCE == 0 ) + + #define TICK_INT_vect TCB0_INT_vect + #define INT_FLAGS TCB0_INTFLAGS + #define INT_MASK TCB_CAPT_bm + + #define TICK_init() \ + { \ + TCB0.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ + TCB0.INTCTRL = TCB_CAPT_bm; \ + TCB0.CTRLA = TCB_ENABLE_bm; \ + } + +#elif ( configUSE_TIMER_INSTANCE == 1 ) + + #define TICK_INT_vect TCB1_INT_vect + #define INT_FLAGS TCB1_INTFLAGS + #define INT_MASK TCB_CAPT_bm + + #define TICK_init() \ + { \ + TCB1.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ + TCB1.INTCTRL = TCB_CAPT_bm; \ + TCB1.CTRLA = TCB_ENABLE_bm; \ + } + +#elif ( configUSE_TIMER_INSTANCE == 2 ) + + #define TICK_INT_vect TCB2_INT_vect + #define INT_FLAGS TCB2_INTFLAGS + #define INT_MASK TCB_CAPT_bm + + #define TICK_init() \ + { \ + TCB2.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ + TCB2.INTCTRL = TCB_CAPT_bm; \ + TCB2.CTRLA = TCB_ENABLE_bm; \ + } + +#elif ( configUSE_TIMER_INSTANCE == 3 ) + + #define TICK_INT_vect TCB3_INT_vect + #define INT_FLAGS TCB3_INTFLAGS + #define INT_MASK TCB_CAPT_bm + + #define TICK_init() \ + { \ + TCB3.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ + TCB3.INTCTRL = TCB_CAPT_bm; \ + TCB3.CTRLA = TCB_ENABLE_bm; \ + } + +#elif ( configUSE_TIMER_INSTANCE == 4 ) + + #define TICK_INT_vect TCB4_INT_vect + #define INT_FLAGS TCB4_INTFLAGS + #define INT_MASK TCB_CAPT_bm + + #define TICK_init() \ + { \ + TCB4.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ + TCB4.INTCTRL = TCB_CAPT_bm; \ + TCB4.CTRLA = TCB_ENABLE_bm; \ + } + +#elif ( configUSE_TIMER_INSTANCE == 5 ) + + #define TICK_INT_vect RTC_CNT_vect + #define INT_FLAGS RTC_INTFLAGS + #define INT_MASK RTC_OVF_bm + +/* Hertz to period for RTC setup */ + #define RTC_PERIOD_HZ( x ) ( 32768 * ( ( 1.0 / x ) ) ) + #define TICK_init() \ + { \ + while( RTC.STATUS > 0 ) {; } \ + RTC.CTRLA = RTC_PRESCALER_DIV1_gc | 1 << RTC_RTCEN_bp; \ + RTC.PER = RTC_PERIOD_HZ( configTICK_RATE_HZ ); \ + RTC.INTCTRL |= 1 << RTC_OVF_bp; \ + } + +#else /* if ( configUSE_TIMER_INSTANCE == 0 ) */ + #undef TICK_INT_vect + #undef INT_FLAGS + #undef INT_MASK + #undef TICK_init() + #error Invalid timer setting. +#endif /* if ( configUSE_TIMER_INSTANCE == 0 ) */ + +/*-----------------------------------------------------------*/ + +#endif /* PORTHARDWARE_H */ diff --git a/portable/IAR/AVR_AVRDx/portmacro.h b/portable/IAR/AVR_AVRDx/portmacro.h new file mode 100644 index 000000000..829958dc0 --- /dev/null +++ b/portable/IAR/AVR_AVRDx/portmacro.h @@ -0,0 +1,111 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE uint8_t +#define portBASE_TYPE char + +#define portPOINTER_SIZE_TYPE uint16_t + +typedef portSTACK_TYPE StackType_t; +typedef signed char BaseType_t; +typedef unsigned char UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif + +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() + +#define portDISABLE_INTERRUPTS() asm ( "cli" ) +#define portENABLE_INTERRUPTS() asm ( "sei" ) +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 1 +#define portNOP() asm ( "nop" ) +/*-----------------------------------------------------------*/ + +/* Kernel utilities. */ +extern void vPortYield( void ); +#define portYIELD() vPortYield() + +extern void vPortYieldFromISR( void ); +#define portYIELD_FROM_ISR() vPortYieldFromISR() +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/IAR/AVR_AVRDx/portmacro.s90 b/portable/IAR/AVR_AVRDx/portmacro.s90 new file mode 100644 index 000000000..c518d3af9 --- /dev/null +++ b/portable/IAR/AVR_AVRDx/portmacro.s90 @@ -0,0 +1,255 @@ +;/* +; * FreeRTOS Kernel +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + +#include "porthardware.h" + +; Declare all extern symbols here - including any ISRs that are referenced in +; the vector table. + +; ISR functions +; ------------- +EXTERN TICK_INT + +; Functions used by scheduler +; --------------------------- +EXTERN vTaskSwitchContext +EXTERN pxCurrentTCB +EXTERN xTaskIncrementTick +EXTERN uxCriticalNesting + +; Functions implemented in this file +; ---------------------------------- +PUBLIC vPortYield +PUBLIC vPortYieldFromTick +PUBLIC vPortYieldFromISR +PUBLIC vPortStart + +; Interrupt vector table. +; ----------------------- +; +; For simplicity the RTOS tick interrupt routine uses the __task keyword. +; As the IAR compiler does not permit a function to be declared using both +; __task and __interrupt, the use of __task necessitates that the interrupt +; vector table be setup manually. +; +; To write an ISR, implement the ISR function using the __interrupt keyword +; but do not install the interrupt using the "#pragma vector=ABC" method. +; Instead manually place the name of the ISR in the vector table using an +; ORG and jmp instruction as demonstrated below. +; You will also have to add an EXTERN statement at the top of the file. + + ASEG + + ORG TICK_INT_vect ; Vector address + jmp TICK_INT ; ISR + + RSEG CODE + +CLR_INT MACRO FLAG_REG, FLAG_MASK + st -y, r16 + ldi r16, FLAG_MASK + sts FLAG_REG, r16 + ld r16, y+ + + ENDM + +; Saving and Restoring a Task Context and Task Switching +; ------------------------------------------------------ +; +; The IAR compiler does not fully support inline assembler, so saving and +; restoring a task context has to be written in an asm file. +; +; vPortYield() and vPortYieldFromTick() are usually written in C. Doing +; so in this case would required calls to be made to portSAVE_CONTEXT() and +; portRESTORE_CONTEXT(). This is dis-advantageous as the context switch +; function would require two extra jump and return instructions over the +; WinAVR equivalent. +; +; To avoid this I have opted to implement both vPortYield() and +; vPortYieldFromTick() in this assembly file. For convenience +; portSAVE_CONTEXT and portRESTORE_CONTEXT are implemented as macros. + +portSAVE_CONTEXT MACRO + st -y, r0 ; First save the r0 register - we need to use this. + in r0, SREG ; Obtain the SREG value so we can disable interrupts... + cli ; ... as soon as possible. + st -y, r0 ; Store the SREG as it was before we disabled interrupts. + + in r0, RAMPZ + st -y, r0 + + in r0, SPL ; Next store the hardware stack pointer. The IAR... + st -y, r0 ; ... compiler uses the hardware stack as a call stack ... + in r0, SPH ; ... only. + st -y, r0 + + st -y, r1 ; Now store the rest of the registers. Dont store the ... + st -y, r2 ; ... the Y register here as it is used as the software + st -y, r3 ; stack pointer and will get saved into the TCB. + st -y, r4 + st -y, r5 + st -y, r6 + st -y, r7 + st -y, r8 + st -y, r9 + st -y, r10 + st -y, r11 + st -y, r12 + st -y, r13 + st -y, r14 + st -y, r15 + st -y, r16 + st -y, r17 + st -y, r18 + st -y, r19 + st -y, r20 + st -y, r21 + st -y, r22 + st -y, r23 + st -y, r24 + st -y, r25 + st -y, r26 + st -y, r27 + st -y, r30 + st -y, r31 + + lds r0, uxCriticalNesting + st -y, r0 ; Store the critical nesting counter. + + lds r26, pxCurrentTCB ; Finally save the software stack pointer (Y ... + lds r27, pxCurrentTCB + 1 ; ... register) into the TCB. + st x+, r28 + st x+, r29 + + ENDM + + +portRESTORE_CONTEXT MACRO + lds r26, pxCurrentTCB + lds r27, pxCurrentTCB + 1 ; Restore the software stack pointer from ... + ld r28, x+ ; the TCB into the software stack pointer (... + ld r29, x+ ; ... the Y register). + + ld r0, y+ + sts uxCriticalNesting, r0 + + ld r31, y+ ; Restore the registers down to R0. The Y + ld r30, y+ ; register is missing from this list as it + ld r27, y+ ; has already been restored. + ld r26, y+ + ld r25, y+ + ld r24, y+ + ld r23, y+ + ld r22, y+ + ld r21, y+ + ld r20, y+ + ld r19, y+ + ld r18, y+ + ld r17, y+ + ld r16, y+ + ld r15, y+ + ld r14, y+ + ld r13, y+ + ld r12, y+ + ld r11, y+ + ld r10, y+ + ld r9, y+ + ld r8, y+ + ld r7, y+ + ld r6, y+ + ld r5, y+ + ld r4, y+ + ld r3, y+ + ld r2, y+ + ld r1, y+ + + ld r0, y+ ; The next thing on the stack is the ... + out SPH, r0 ; ... hardware stack pointer. + ld r0, y+ + out SPL, r0 + + ld r0, y+ + out RAMPZ, r0 + + ld r0, y+ ; Next there is the SREG register. + out SREG, r0 + + ld r0, y+ ; Finally we have finished with r0, so restore r0. + + ENDM + + + +; vPortYield(), vPortYieldFromTick() and vPortYieldFromISR() +; ------------------------------------- +; +; Manual and preemptive context switch functions respectively. +; The IAR compiler does not fully support inline assembler, +; so these are implemented here rather than the more usually +; place of within port.c. + +vPortYield: + portSAVE_CONTEXT ; Save the context of the current task. + call vTaskSwitchContext ; Call the scheduler. + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + ret ; ... scheduler decided should run. + +vPortYieldFromTick: + CLR_INT INT_FLAGS, INT_MASK ; Clear tick interrupt flag + + portSAVE_CONTEXT ; Save the context of the current task. + call xTaskIncrementTick ; Call the timer tick function. + tst r16 + breq SkipTaskSwitch + call vTaskSwitchContext ; Call the scheduler. + +SkipTaskSwitch: + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + reti ; ... scheduler decided should run. + +vPortYieldFromISR: + portSAVE_CONTEXT ; Save the context of the current task. + call vTaskSwitchContext ; Call the scheduler. + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + reti ; ... scheduler decided should run. + +; vPortStart() +; ------------ +; +; Again due to the lack of inline assembler, this is required +; to get access to the portRESTORE_CONTEXT macro. + +vPortStart: + portRESTORE_CONTEXT + ret + +; Just a filler for unused interrupt vectors. +vNoISR: + reti + + END diff --git a/portable/IAR/AVR_Mega0/port.c b/portable/IAR/AVR_Mega0/port.c new file mode 100644 index 000000000..7d1d2f6e8 --- /dev/null +++ b/portable/IAR/AVR_Mega0/port.c @@ -0,0 +1,299 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include +#include "porthardware.h" +#include "FreeRTOS.h" +#include "task.h" + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the AVR port. +*----------------------------------------------------------*/ + +/* Start tasks with interrupts enables. */ +#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x80 ) + +/*-----------------------------------------------------------*/ + + +#define portBYTES_USED_BY_RETURN_ADDRESS 2 +#define portNO_CRITICAL_NESTING ( ( UBaseType_t ) 0 ) + +/* Stores the critical section nesting. This must not be initialised to 0. + * It will be initialised when a task starts. */ +UBaseType_t uxCriticalNesting = 0x50; + +/* + * Setup timer to generate a tick interrupt. + */ +static void prvSetupTimerInterrupt( void ); + +/* + * The IAR compiler does not have full support for inline assembler, so + * these are defined in the portmacro assembler file. + */ +extern void vPortYieldFromTick( void ); +extern void vPortStart( void ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + uint16_t usAddress; + StackType_t * pxTopOfHardwareStack; + + /* Simulate how the stack would look after a call to vPortYield(). */ + + /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */ + + /* The IAR compiler requires two stacks per task. First there is the + * hardware call stack which uses the AVR stack pointer. Second there is the + * software stack (local variables, parameter passing, etc.) which uses the + * AVR Y register. + * This function places both stacks within the memory block passed in as the + * first parameter. The hardware stack is placed at the bottom of the memory + * block. A gap is then left for the hardware stack to grow. Next the software + * stack is placed. The amount of space between the software and hardware + * stacks is defined by configCALL_STACK_SIZE. + * The first part of the stack is the hardware stack. Place the start + * address of the task on the hardware stack. */ + + /* Place a few bytes of known values on the bottom of the stack. + * This is just useful for debugging. */ + /**pxTopOfStack = 0x11; */ + /*pxTopOfStack--; */ + /**pxTopOfStack = 0x22; */ + /*pxTopOfStack--; */ + /**pxTopOfStack = 0x33; */ + /*pxTopOfStack--; */ + + /* Remember where the top of the hardware stack is - this is required + * below. */ + pxTopOfHardwareStack = pxTopOfStack; + + usAddress = ( uint16_t ) pxCode; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + usAddress >>= 8; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + /* Leave enough space for the hardware stack before starting the software + * stack. The '- 2' is because we have already used two spaces for the + * address of the start of the task. */ + pxTopOfStack -= ( configCALL_STACK_SIZE - 2 ); + + /* Next simulate the stack as if after a call to portSAVE_CONTEXT(). + * portSAVE_CONTEXT places the flags on the stack immediately after r0 + * to ensure the interrupts get disabled as soon as possible, and so ensuring + * the stack use is minimal should a context switch interrupt occur. */ + + *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */ + pxTopOfStack--; + *pxTopOfStack = portFLAGS_INT_ENABLED; + pxTopOfStack--; + + /* Next place the address of the hardware stack. This is required so + * the AVR stack pointer can be restored to point to the hardware stack. */ + pxTopOfHardwareStack -= portBYTES_USED_BY_RETURN_ADDRESS; + usAddress = ( uint16_t ) pxTopOfHardwareStack; + + /* SPL */ + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + /* SPH */ + usAddress >>= 8; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + /* Now the remaining registers. */ + *pxTopOfStack = ( StackType_t ) 0x01; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x13; /* R13 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x14; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x15; /* R15 */ + pxTopOfStack--; + + /* Place the parameter on the stack in the expected location. */ + usAddress = ( uint16_t ) pvParameters; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + usAddress >>= 8; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0x18; /* R18 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x19; /* R19 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x20; /* R20 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x21; /* R21 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x22; /* R22 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x23; /* R23 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x24; /* R24 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x25; /* R25 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x26; /* R26 X */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x27; /* R27 */ + pxTopOfStack--; + + /* The Y register is not stored as it is used as the software stack and + * gets saved into the task control block. */ + + *pxTopOfStack = ( StackType_t ) 0x30; /* R30 Z */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x031; /* R31 */ + + pxTopOfStack--; + *pxTopOfStack = portNO_CRITICAL_NESTING; /* Critical nesting is zero when the task starts. */ + + /*lint +e950 +e611 +e923 */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Setup the hardware to generate the tick. */ + prvSetupTimerInterrupt(); + + /* Restore the context of the first task that is going to run. + * Normally we would just call portRESTORE_CONTEXT() here, but as the IAR + * compiler does not fully support inline assembler we have to make a call.*/ + vPortStart(); + + /* Should not get here. */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* vPortEndScheduler is not implemented in this port. */ +} + +/*-----------------------------------------------------------*/ + +/* + * Setup timer to generate a tick interrupt. + */ +static void prvSetupTimerInterrupt( void ) +{ + TICK_init(); +} + +/*-----------------------------------------------------------*/ + +#if configUSE_PREEMPTION == 1 + +/* + * Tick ISR for preemptive scheduler. We can use a naked attribute as + * the context is saved at the start of vPortYieldFromTick(). The tick + * count is incremented after the context is saved. + */ + + __task void TICK_INT( void ) + { + vPortYieldFromTick(); + asm ( "reti" ); + } +#else + +/* + * Tick ISR for the cooperative scheduler. All this does is increment the + * tick count. We don't need to switch context, this can only be done by + * manual calls to taskYIELD(); + */ + + __interrupt void TICK_INT( void ) + { + /* Clear tick interrupt flag. */ + INT_FLAGS = INT_MASK; + + xTaskIncrementTick(); + } +#endif /* if configUSE_PREEMPTION == 1 */ + +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; +} + +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + uxCriticalNesting--; + + if( uxCriticalNesting == portNO_CRITICAL_NESTING ) + { + portENABLE_INTERRUPTS(); + } +} diff --git a/portable/IAR/AVR_Mega0/porthardware.h b/portable/IAR/AVR_Mega0/porthardware.h new file mode 100644 index 000000000..d834a8e82 --- /dev/null +++ b/portable/IAR/AVR_Mega0/porthardware.h @@ -0,0 +1,116 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ +#ifndef PORTHARDWARE_H +#define PORTHARDWARE_H + +#ifndef __IAR_SYSTEMS_ASM__ + #include +#endif +#include "FreeRTOSConfig.h" + +/*-----------------------------------------------------------*/ + +#if ( configUSE_TIMER_INSTANCE == 0 ) + + #define TICK_INT_vect TCB0_INT_vect + #define INT_FLAGS TCB0_INTFLAGS + #define INT_MASK TCB_CAPT_bm + + #define TICK_init() \ + { \ + TCB0.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ + TCB0.INTCTRL = TCB_CAPT_bm; \ + TCB0.CTRLA = TCB_ENABLE_bm; \ + } + +#elif ( configUSE_TIMER_INSTANCE == 1 ) + + #define TICK_INT_vect TCB1_INT_vect + #define INT_FLAGS TCB1_INTFLAGS + #define INT_MASK TCB_CAPT_bm + + #define TICK_init() \ + { \ + TCB1.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ + TCB1.INTCTRL = TCB_CAPT_bm; \ + TCB1.CTRLA = TCB_ENABLE_bm; \ + } + +#elif ( configUSE_TIMER_INSTANCE == 2 ) + + #define TICK_INT_vect TCB2_INT_vect + #define INT_FLAGS TCB2_INTFLAGS + #define INT_MASK TCB_CAPT_bm + + #define TICK_init() \ + { \ + TCB2.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ + TCB2.INTCTRL = TCB_CAPT_bm; \ + TCB2.CTRLA = TCB_ENABLE_bm; \ + } + +#elif ( configUSE_TIMER_INSTANCE == 3 ) + + #define TICK_INT_vect TCB3_INT_vect + #define INT_FLAGS TCB3_INTFLAGS + #define INT_MASK TCB_CAPT_bm + + #define TICK_init() \ + { \ + TCB3.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \ + TCB3.INTCTRL = TCB_CAPT_bm; \ + TCB3.CTRLA = TCB_ENABLE_bm; \ + } + +#elif ( configUSE_TIMER_INSTANCE == 4 ) + + #define TICK_INT_vect RTC_CNT_vect + #define INT_FLAGS RTC_INTFLAGS + #define INT_MASK RTC_OVF_bm + +/* Hertz to period for RTC setup */ + #define RTC_PERIOD_HZ( x ) ( 32768 * ( ( 1.0 / x ) ) ) + #define TICK_init() \ + { \ + while( RTC.STATUS > 0 ) {; } \ + RTC.CTRLA = RTC_PRESCALER_DIV1_gc | 1 << RTC_RTCEN_bp; \ + RTC.PER = RTC_PERIOD_HZ( configTICK_RATE_HZ ); \ + RTC.INTCTRL |= 1 << RTC_OVF_bp; \ + } + +#else /* if ( configUSE_TIMER_INSTANCE == 0 ) */ + #undef TICK_INT_vect + #undef INT_FLAGS + #undef INT_MASK + #undef TICK_init() + #error Invalid timer setting. +#endif /* if ( configUSE_TIMER_INSTANCE == 0 ) */ + +/*-----------------------------------------------------------*/ + +#endif /* PORTHARDWARE_H */ diff --git a/portable/IAR/AVR_Mega0/portmacro.h b/portable/IAR/AVR_Mega0/portmacro.h new file mode 100644 index 000000000..829958dc0 --- /dev/null +++ b/portable/IAR/AVR_Mega0/portmacro.h @@ -0,0 +1,111 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE uint8_t +#define portBASE_TYPE char + +#define portPOINTER_SIZE_TYPE uint16_t + +typedef portSTACK_TYPE StackType_t; +typedef signed char BaseType_t; +typedef unsigned char UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif + +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() + +#define portDISABLE_INTERRUPTS() asm ( "cli" ) +#define portENABLE_INTERRUPTS() asm ( "sei" ) +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 1 +#define portNOP() asm ( "nop" ) +/*-----------------------------------------------------------*/ + +/* Kernel utilities. */ +extern void vPortYield( void ); +#define portYIELD() vPortYield() + +extern void vPortYieldFromISR( void ); +#define portYIELD_FROM_ISR() vPortYieldFromISR() +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/IAR/AVR_Mega0/portmacro.s90 b/portable/IAR/AVR_Mega0/portmacro.s90 new file mode 100644 index 000000000..c2789d48e --- /dev/null +++ b/portable/IAR/AVR_Mega0/portmacro.s90 @@ -0,0 +1,249 @@ +;/* +; * FreeRTOS Kernel +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + +#include "porthardware.h" + +; Declare all extern symbols here - including any ISRs that are referenced in +; the vector table. + +; ISR functions +; ------------- +EXTERN TICK_INT + +; Functions used by scheduler +; --------------------------- +EXTERN vTaskSwitchContext +EXTERN pxCurrentTCB +EXTERN xTaskIncrementTick +EXTERN uxCriticalNesting + +; Functions implemented in this file +; ---------------------------------- +PUBLIC vPortYield +PUBLIC vPortYieldFromTick +PUBLIC vPortYieldFromISR +PUBLIC vPortStart + +; Interrupt vector table. +; ----------------------- +; +; For simplicity the RTOS tick interrupt routine uses the __task keyword. +; As the IAR compiler does not permit a function to be declared using both +; __task and __interrupt, the use of __task necessitates that the interrupt +; vector table be setup manually. +; +; To write an ISR, implement the ISR function using the __interrupt keyword +; but do not install the interrupt using the "#pragma vector=ABC" method. +; Instead manually place the name of the ISR in the vector table using an +; ORG and jmp instruction as demonstrated below. +; You will also have to add an EXTERN statement at the top of the file. + + ASEG + + ORG TICK_INT_vect ; Vector address + jmp TICK_INT ; ISR + + RSEG CODE + +CLR_INT MACRO FLAG_REG, FLAG_MASK + st -y, r16 + ldi r16, FLAG_MASK + sts FLAG_REG, r16 + ld r16, y+ + + ENDM + +; Saving and Restoring a Task Context and Task Switching +; ------------------------------------------------------ +; +; The IAR compiler does not fully support inline assembler, so saving and +; restoring a task context has to be written in an asm file. +; +; vPortYield() and vPortYieldFromTick() are usually written in C. Doing +; so in this case would required calls to be made to portSAVE_CONTEXT() and +; portRESTORE_CONTEXT(). This is dis-advantageous as the context switch +; function would require two extra jump and return instructions over the +; WinAVR equivalent. +; +; To avoid this I have opted to implement both vPortYield() and +; vPortYieldFromTick() in this assembly file. For convenience +; portSAVE_CONTEXT and portRESTORE_CONTEXT are implemented as macros. + +portSAVE_CONTEXT MACRO + st -y, r0 ; First save the r0 register - we need to use this. + in r0, SREG ; Obtain the SREG value so we can disable interrupts... + cli ; ... as soon as possible. + st -y, r0 ; Store the SREG as it was before we disabled interrupts. + + in r0, SPL ; Next store the hardware stack pointer. The IAR... + st -y, r0 ; ... compiler uses the hardware stack as a call stack ... + in r0, SPH ; ... only. + st -y, r0 + + st -y, r1 ; Now store the rest of the registers. Dont store the ... + st -y, r2 ; ... the Y register here as it is used as the software + st -y, r3 ; stack pointer and will get saved into the TCB. + st -y, r4 + st -y, r5 + st -y, r6 + st -y, r7 + st -y, r8 + st -y, r9 + st -y, r10 + st -y, r11 + st -y, r12 + st -y, r13 + st -y, r14 + st -y, r15 + st -y, r16 + st -y, r17 + st -y, r18 + st -y, r19 + st -y, r20 + st -y, r21 + st -y, r22 + st -y, r23 + st -y, r24 + st -y, r25 + st -y, r26 + st -y, r27 + st -y, r30 + st -y, r31 + + lds r0, uxCriticalNesting + st -y, r0 ; Store the critical nesting counter. + + lds r26, pxCurrentTCB ; Finally save the software stack pointer (Y ... + lds r27, pxCurrentTCB + 1 ; ... register) into the TCB. + st x+, r28 + st x+, r29 + + ENDM + + +portRESTORE_CONTEXT MACRO + lds r26, pxCurrentTCB + lds r27, pxCurrentTCB + 1 ; Restore the software stack pointer from ... + ld r28, x+ ; the TCB into the software stack pointer (... + ld r29, x+ ; ... the Y register). + + ld r0, y+ + sts uxCriticalNesting, r0 + + ld r31, y+ ; Restore the registers down to R0. The Y + ld r30, y+ ; register is missing from this list as it + ld r27, y+ ; has already been restored. + ld r26, y+ + ld r25, y+ + ld r24, y+ + ld r23, y+ + ld r22, y+ + ld r21, y+ + ld r20, y+ + ld r19, y+ + ld r18, y+ + ld r17, y+ + ld r16, y+ + ld r15, y+ + ld r14, y+ + ld r13, y+ + ld r12, y+ + ld r11, y+ + ld r10, y+ + ld r9, y+ + ld r8, y+ + ld r7, y+ + ld r6, y+ + ld r5, y+ + ld r4, y+ + ld r3, y+ + ld r2, y+ + ld r1, y+ + + ld r0, y+ ; The next thing on the stack is the ... + out SPH, r0 ; ... hardware stack pointer. + ld r0, y+ + out SPL, r0 + + ld r0, y+ ; Next there is the SREG register. + out SREG, r0 + + ld r0, y+ ; Finally we have finished with r0, so restore r0. + + ENDM + + + +; vPortYield(), vPortYieldFromTick() and vPortYieldFromISR() +; ------------------------------------- +; +; Manual and preemptive context switch functions respectively. +; The IAR compiler does not fully support inline assembler, +; so these are implemented here rather than the more usually +; place of within port.c. + +vPortYield: + portSAVE_CONTEXT ; Save the context of the current task. + call vTaskSwitchContext ; Call the scheduler. + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + ret ; ... scheduler decided should run. + +vPortYieldFromTick: + CLR_INT INT_FLAGS, INT_MASK ; Clear tick interrupt flag + + portSAVE_CONTEXT ; Save the context of the current task. + call xTaskIncrementTick ; Call the timer tick function. + tst r16 + breq SkipTaskSwitch + call vTaskSwitchContext ; Call the scheduler. + +SkipTaskSwitch: + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + reti ; ... scheduler decided should run. + +vPortYieldFromISR: + portSAVE_CONTEXT ; Save the context of the current task. + call vTaskSwitchContext ; Call the scheduler. + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + reti ; ... scheduler decided should run. + +; vPortStart() +; ------------ +; +; Again due to the lack of inline assembler, this is required +; to get access to the portRESTORE_CONTEXT macro. + +vPortStart: + portRESTORE_CONTEXT + ret + +; Just a filler for unused interrupt vectors. +vNoISR: + reti + +END diff --git a/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h b/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h new file mode 100644 index 000000000..6df767884 --- /dev/null +++ b/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h @@ -0,0 +1,1936 @@ +/* ---------------------------------------------------------------------------- */ +/* ATMEL Microcontroller Software Support - ROUSSET - */ +/* ---------------------------------------------------------------------------- */ +/* The software is delivered "AS IS" without warranty or condition of any */ +/* kind, either express, implied or statutory. This includes without */ +/* limitation any warranty or condition with respect to merchantability or */ +/* fitness for any particular purpose, or against the infringements of */ +/* intellectual property rights of others. */ +/* ---------------------------------------------------------------------------- */ +/* File Name : AT91SAM7S64.h */ +/* Object : AT91SAM7S64 definitions */ +/* Generated : AT91 SW Application Group 07/16/2004 (07:43:08) */ +/* */ +/* CVS Reference : /AT91SAM7S64.pl/1.12/Mon Jul 12 13:02:30 2004// */ +/* CVS Reference : /SYSC_SAM7Sxx.pl/1.5/Mon Jul 12 16:22:12 2004// */ +/* CVS Reference : /MC_SAM02.pl/1.3/Wed Mar 10 08:37:04 2004// */ +/* CVS Reference : /UDP_1765B.pl/1.3/Fri Aug 2 14:45:38 2002// */ +/* CVS Reference : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// */ +/* CVS Reference : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004// */ +/* CVS Reference : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// */ +/* CVS Reference : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003// */ +/* CVS Reference : /US_1739C.pl/1.2/Mon Jul 12 17:26:24 2004// */ +/* CVS Reference : /SPI2.pl/1.2/Fri Oct 17 08:13:40 2003// */ +/* CVS Reference : /SSC_1762A.pl/1.2/Fri Nov 8 13:26:40 2002// */ +/* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// */ +/* CVS Reference : /TWI_1761B.pl/1.4/Fri Feb 7 10:30:08 2003// */ +/* CVS Reference : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:24 2002// */ +/* CVS Reference : /ADC_SAM.pl/1.7/Fri Oct 17 08:12:38 2003// */ +/* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// */ +/* ---------------------------------------------------------------------------- */ + +#ifndef AT91SAM7S64_H +#define AT91SAM7S64_H + +typedef volatile unsigned int AT91_REG; /* Hardware register definition */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR System Peripherals */ +/* ***************************************************************************** */ +typedef struct _AT91S_SYSC +{ + AT91_REG SYSC_AIC_SMR[ 32 ]; /* Source Mode Register */ + AT91_REG SYSC_AIC_SVR[ 32 ]; /* Source Vector Register */ + AT91_REG SYSC_AIC_IVR; /* IRQ Vector Register */ + AT91_REG SYSC_AIC_FVR; /* FIQ Vector Register */ + AT91_REG SYSC_AIC_ISR; /* Interrupt Status Register */ + AT91_REG SYSC_AIC_IPR; /* Interrupt Pending Register */ + AT91_REG SYSC_AIC_IMR; /* Interrupt Mask Register */ + AT91_REG SYSC_AIC_CISR; /* Core Interrupt Status Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG SYSC_AIC_IECR; /* Interrupt Enable Command Register */ + AT91_REG SYSC_AIC_IDCR; /* Interrupt Disable Command Register */ + AT91_REG SYSC_AIC_ICCR; /* Interrupt Clear Command Register */ + AT91_REG SYSC_AIC_ISCR; /* Interrupt Set Command Register */ + AT91_REG SYSC_AIC_EOICR; /* End of Interrupt Command Register */ + AT91_REG SYSC_AIC_SPU; /* Spurious Vector Register */ + AT91_REG SYSC_AIC_DCR; /* Debug Control Register (Protect) */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG SYSC_AIC_FFER; /* Fast Forcing Enable Register */ + AT91_REG SYSC_AIC_FFDR; /* Fast Forcing Disable Register */ + AT91_REG SYSC_AIC_FFSR; /* Fast Forcing Status Register */ + AT91_REG Reserved2[ 45 ]; /* */ + AT91_REG SYSC_DBGU_CR; /* Control Register */ + AT91_REG SYSC_DBGU_MR; /* Mode Register */ + AT91_REG SYSC_DBGU_IER; /* Interrupt Enable Register */ + AT91_REG SYSC_DBGU_IDR; /* Interrupt Disable Register */ + AT91_REG SYSC_DBGU_IMR; /* Interrupt Mask Register */ + AT91_REG SYSC_DBGU_CSR; /* Channel Status Register */ + AT91_REG SYSC_DBGU_RHR; /* Receiver Holding Register */ + AT91_REG SYSC_DBGU_THR; /* Transmitter Holding Register */ + AT91_REG SYSC_DBGU_BRGR; /* Baud Rate Generator Register */ + AT91_REG Reserved3[ 7 ]; /* */ + AT91_REG SYSC_DBGU_C1R; /* Chip ID1 Register */ + AT91_REG SYSC_DBGU_C2R; /* Chip ID2 Register */ + AT91_REG SYSC_DBGU_FNTR; /* Force NTRST Register */ + AT91_REG Reserved4[ 45 ]; /* */ + AT91_REG SYSC_DBGU_RPR; /* Receive Pointer Register */ + AT91_REG SYSC_DBGU_RCR; /* Receive Counter Register */ + AT91_REG SYSC_DBGU_TPR; /* Transmit Pointer Register */ + AT91_REG SYSC_DBGU_TCR; /* Transmit Counter Register */ + AT91_REG SYSC_DBGU_RNPR; /* Receive Next Pointer Register */ + AT91_REG SYSC_DBGU_RNCR; /* Receive Next Counter Register */ + AT91_REG SYSC_DBGU_TNPR; /* Transmit Next Pointer Register */ + AT91_REG SYSC_DBGU_TNCR; /* Transmit Next Counter Register */ + AT91_REG SYSC_DBGU_PTCR; /* PDC Transfer Control Register */ + AT91_REG SYSC_DBGU_PTSR; /* PDC Transfer Status Register */ + AT91_REG Reserved5[ 54 ]; /* */ + AT91_REG SYSC_PIOA_PER; /* PIO Enable Register */ + AT91_REG SYSC_PIOA_PDR; /* PIO Disable Register */ + AT91_REG SYSC_PIOA_PSR; /* PIO Status Register */ + AT91_REG Reserved6[ 1 ]; /* */ + AT91_REG SYSC_PIOA_OER; /* Output Enable Register */ + AT91_REG SYSC_PIOA_ODR; /* Output Disable Registerr */ + AT91_REG SYSC_PIOA_OSR; /* Output Status Register */ + AT91_REG Reserved7[ 1 ]; /* */ + AT91_REG SYSC_PIOA_IFER; /* Input Filter Enable Register */ + AT91_REG SYSC_PIOA_IFDR; /* Input Filter Disable Register */ + AT91_REG SYSC_PIOA_IFSR; /* Input Filter Status Register */ + AT91_REG Reserved8[ 1 ]; /* */ + AT91_REG SYSC_PIOA_SODR; /* Set Output Data Register */ + AT91_REG SYSC_PIOA_CODR; /* Clear Output Data Register */ + AT91_REG SYSC_PIOA_ODSR; /* Output Data Status Register */ + AT91_REG SYSC_PIOA_PDSR; /* Pin Data Status Register */ + AT91_REG SYSC_PIOA_IER; /* Interrupt Enable Register */ + AT91_REG SYSC_PIOA_IDR; /* Interrupt Disable Register */ + AT91_REG SYSC_PIOA_IMR; /* Interrupt Mask Register */ + AT91_REG SYSC_PIOA_ISR; /* Interrupt Status Register */ + AT91_REG SYSC_PIOA_MDER; /* Multi-driver Enable Register */ + AT91_REG SYSC_PIOA_MDDR; /* Multi-driver Disable Register */ + AT91_REG SYSC_PIOA_MDSR; /* Multi-driver Status Register */ + AT91_REG Reserved9[ 1 ]; /* */ + AT91_REG SYSC_PIOA_PPUDR; /* Pull-up Disable Register */ + AT91_REG SYSC_PIOA_PPUER; /* Pull-up Enable Register */ + AT91_REG SYSC_PIOA_PPUSR; /* Pad Pull-up Status Register */ + AT91_REG Reserved10[ 1 ]; /* */ + AT91_REG SYSC_PIOA_ASR; /* Select A Register */ + AT91_REG SYSC_PIOA_BSR; /* Select B Register */ + AT91_REG SYSC_PIOA_ABSR; /* AB Select Status Register */ + AT91_REG Reserved11[ 9 ]; /* */ + AT91_REG SYSC_PIOA_OWER; /* Output Write Enable Register */ + AT91_REG SYSC_PIOA_OWDR; /* Output Write Disable Register */ + AT91_REG SYSC_PIOA_OWSR; /* Output Write Status Register */ + AT91_REG Reserved12[ 469 ]; /* */ + AT91_REG SYSC_PMC_SCER; /* System Clock Enable Register */ + AT91_REG SYSC_PMC_SCDR; /* System Clock Disable Register */ + AT91_REG SYSC_PMC_SCSR; /* System Clock Status Register */ + AT91_REG Reserved13[ 1 ]; /* */ + AT91_REG SYSC_PMC_PCER; /* Peripheral Clock Enable Register */ + AT91_REG SYSC_PMC_PCDR; /* Peripheral Clock Disable Register */ + AT91_REG SYSC_PMC_PCSR; /* Peripheral Clock Status Register */ + AT91_REG Reserved14[ 1 ]; /* */ + AT91_REG SYSC_PMC_MOR; /* Main Oscillator Register */ + AT91_REG SYSC_PMC_MCFR; /* Main Clock Frequency Register */ + AT91_REG Reserved15[ 1 ]; /* */ + AT91_REG SYSC_PMC_PLLR; /* PLL Register */ + AT91_REG SYSC_PMC_MCKR; /* Master Clock Register */ + AT91_REG Reserved16[ 3 ]; /* */ + AT91_REG SYSC_PMC_PCKR[ 8 ]; /* Programmable Clock Register */ + AT91_REG SYSC_PMC_IER; /* Interrupt Enable Register */ + AT91_REG SYSC_PMC_IDR; /* Interrupt Disable Register */ + AT91_REG SYSC_PMC_SR; /* Status Register */ + AT91_REG SYSC_PMC_IMR; /* Interrupt Mask Register */ + AT91_REG Reserved17[ 36 ]; /* */ + AT91_REG SYSC_RSTC_RCR; /* Reset Control Register */ + AT91_REG SYSC_RSTC_RSR; /* Reset Status Register */ + AT91_REG SYSC_RSTC_RMR; /* Reset Mode Register */ + AT91_REG Reserved18[ 5 ]; /* */ + AT91_REG SYSC_RTTC_RTMR; /* Real-time Mode Register */ + AT91_REG SYSC_RTTC_RTAR; /* Real-time Alarm Register */ + AT91_REG SYSC_RTTC_RTVR; /* Real-time Value Register */ + AT91_REG SYSC_RTTC_RTSR; /* Real-time Status Register */ + AT91_REG SYSC_PITC_PIMR; /* Period Interval Mode Register */ + AT91_REG SYSC_PITC_PISR; /* Period Interval Status Register */ + AT91_REG SYSC_PITC_PIVR; /* Period Interval Value Register */ + AT91_REG SYSC_PITC_PIIR; /* Period Interval Image Register */ + AT91_REG SYSC_WDTC_WDCR; /* Watchdog Control Register */ + AT91_REG SYSC_WDTC_WDMR; /* Watchdog Mode Register */ + AT91_REG SYSC_WDTC_WDSR; /* Watchdog Status Register */ + AT91_REG Reserved19[ 5 ]; /* */ + AT91_REG SYSC_SYSC_VRPM; /* Voltage Regulator Power Mode Register */ +} AT91S_SYSC, * AT91PS_SYSC; + +/* -------- VRPM : (SYSC Offset: 0xd60) Voltage Regulator Power Mode Register -------- */ +#define AT91C_SYSC_PSTDBY ( ( unsigned int ) 0x1 << 0 ) /* (SYSC) Voltage Regulator Power Mode */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Advanced Interrupt Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_AIC +{ + AT91_REG AIC_SMR[ 32 ]; /* Source Mode Register */ + AT91_REG AIC_SVR[ 32 ]; /* Source Vector Register */ + AT91_REG AIC_IVR; /* IRQ Vector Register */ + AT91_REG AIC_FVR; /* FIQ Vector Register */ + AT91_REG AIC_ISR; /* Interrupt Status Register */ + AT91_REG AIC_IPR; /* Interrupt Pending Register */ + AT91_REG AIC_IMR; /* Interrupt Mask Register */ + AT91_REG AIC_CISR; /* Core Interrupt Status Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG AIC_IECR; /* Interrupt Enable Command Register */ + AT91_REG AIC_IDCR; /* Interrupt Disable Command Register */ + AT91_REG AIC_ICCR; /* Interrupt Clear Command Register */ + AT91_REG AIC_ISCR; /* Interrupt Set Command Register */ + AT91_REG AIC_EOICR; /* End of Interrupt Command Register */ + AT91_REG AIC_SPU; /* Spurious Vector Register */ + AT91_REG AIC_DCR; /* Debug Control Register (Protect) */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG AIC_FFER; /* Fast Forcing Enable Register */ + AT91_REG AIC_FFDR; /* Fast Forcing Disable Register */ + AT91_REG AIC_FFSR; /* Fast Forcing Status Register */ +} AT91S_AIC, * AT91PS_AIC; + +/* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */ +#define AT91C_AIC_PRIOR ( ( unsigned int ) 0x7 << 0 ) /* (AIC) Priority Level */ +#define AT91C_AIC_PRIOR_LOWEST ( ( unsigned int ) 0x0 ) /* (AIC) Lowest priority level */ +#define AT91C_AIC_PRIOR_HIGHEST ( ( unsigned int ) 0x7 ) /* (AIC) Highest priority level */ +#define AT91C_AIC_SRCTYPE ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Interrupt Source Type */ +#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE ( ( unsigned int ) 0x0 << 5 ) /* (AIC) Internal Sources Code Label Level Sensitive */ +#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED ( ( unsigned int ) 0x1 << 5 ) /* (AIC) Internal Sources Code Label Edge triggered */ +#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL ( ( unsigned int ) 0x2 << 5 ) /* (AIC) External Sources Code Label High-level Sensitive */ +#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE ( ( unsigned int ) 0x3 << 5 ) /* (AIC) External Sources Code Label Positive Edge triggered */ +/* -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- */ +#define AT91C_AIC_NFIQ ( ( unsigned int ) 0x1 << 0 ) /* (AIC) NFIQ Status */ +#define AT91C_AIC_NIRQ ( ( unsigned int ) 0x1 << 1 ) /* (AIC) NIRQ Status */ +/* -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- */ +#define AT91C_AIC_DCR_PROT ( ( unsigned int ) 0x1 << 0 ) /* (AIC) Protection Mode */ +#define AT91C_AIC_DCR_GMSK ( ( unsigned int ) 0x1 << 1 ) /* (AIC) General Mask */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Debug Unit */ +/* ***************************************************************************** */ +typedef struct _AT91S_DBGU +{ + AT91_REG DBGU_CR; /* Control Register */ + AT91_REG DBGU_MR; /* Mode Register */ + AT91_REG DBGU_IER; /* Interrupt Enable Register */ + AT91_REG DBGU_IDR; /* Interrupt Disable Register */ + AT91_REG DBGU_IMR; /* Interrupt Mask Register */ + AT91_REG DBGU_CSR; /* Channel Status Register */ + AT91_REG DBGU_RHR; /* Receiver Holding Register */ + AT91_REG DBGU_THR; /* Transmitter Holding Register */ + AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */ + AT91_REG Reserved0[ 7 ]; /* */ + AT91_REG DBGU_C1R; /* Chip ID1 Register */ + AT91_REG DBGU_C2R; /* Chip ID2 Register */ + AT91_REG DBGU_FNTR; /* Force NTRST Register */ + AT91_REG Reserved1[ 45 ]; /* */ + AT91_REG DBGU_RPR; /* Receive Pointer Register */ + AT91_REG DBGU_RCR; /* Receive Counter Register */ + AT91_REG DBGU_TPR; /* Transmit Pointer Register */ + AT91_REG DBGU_TCR; /* Transmit Counter Register */ + AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */ + AT91_REG DBGU_RNCR; /* Receive Next Counter Register */ + AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */ + AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */ + AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */ + AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */ +} AT91S_DBGU, * AT91PS_DBGU; + +/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */ +#define AT91C_US_RSTRX ( ( unsigned int ) 0x1 << 2 ) /* (DBGU) Reset Receiver */ +#define AT91C_US_RSTTX ( ( unsigned int ) 0x1 << 3 ) /* (DBGU) Reset Transmitter */ +#define AT91C_US_RXEN ( ( unsigned int ) 0x1 << 4 ) /* (DBGU) Receiver Enable */ +#define AT91C_US_RXDIS ( ( unsigned int ) 0x1 << 5 ) /* (DBGU) Receiver Disable */ +#define AT91C_US_TXEN ( ( unsigned int ) 0x1 << 6 ) /* (DBGU) Transmitter Enable */ +#define AT91C_US_TXDIS ( ( unsigned int ) 0x1 << 7 ) /* (DBGU) Transmitter Disable */ +/* -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- */ +#define AT91C_US_PAR ( ( unsigned int ) 0x7 << 9 ) /* (DBGU) Parity type */ +#define AT91C_US_PAR_EVEN ( ( unsigned int ) 0x0 << 9 ) /* (DBGU) Even Parity */ +#define AT91C_US_PAR_ODD ( ( unsigned int ) 0x1 << 9 ) /* (DBGU) Odd Parity */ +#define AT91C_US_PAR_SPACE ( ( unsigned int ) 0x2 << 9 ) /* (DBGU) Parity forced to 0 (Space) */ +#define AT91C_US_PAR_MARK ( ( unsigned int ) 0x3 << 9 ) /* (DBGU) Parity forced to 1 (Mark) */ +#define AT91C_US_PAR_NONE ( ( unsigned int ) 0x4 << 9 ) /* (DBGU) No Parity */ +#define AT91C_US_PAR_MULTI_DROP ( ( unsigned int ) 0x6 << 9 ) /* (DBGU) Multi-drop mode */ +#define AT91C_US_CHMODE ( ( unsigned int ) 0x3 << 14 ) /* (DBGU) Channel Mode */ +#define AT91C_US_CHMODE_NORMAL ( ( unsigned int ) 0x0 << 14 ) /* (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. */ +#define AT91C_US_CHMODE_AUTO ( ( unsigned int ) 0x1 << 14 ) /* (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. */ +#define AT91C_US_CHMODE_LOCAL ( ( unsigned int ) 0x2 << 14 ) /* (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. */ +#define AT91C_US_CHMODE_REMOTE ( ( unsigned int ) 0x3 << 14 ) /* (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. */ +/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ +#define AT91C_US_RXRDY ( ( unsigned int ) 0x1 << 0 ) /* (DBGU) RXRDY Interrupt */ +#define AT91C_US_TXRDY ( ( unsigned int ) 0x1 << 1 ) /* (DBGU) TXRDY Interrupt */ +#define AT91C_US_ENDRX ( ( unsigned int ) 0x1 << 3 ) /* (DBGU) End of Receive Transfer Interrupt */ +#define AT91C_US_ENDTX ( ( unsigned int ) 0x1 << 4 ) /* (DBGU) End of Transmit Interrupt */ +#define AT91C_US_OVRE ( ( unsigned int ) 0x1 << 5 ) /* (DBGU) Overrun Interrupt */ +#define AT91C_US_FRAME ( ( unsigned int ) 0x1 << 6 ) /* (DBGU) Framing Error Interrupt */ +#define AT91C_US_PARE ( ( unsigned int ) 0x1 << 7 ) /* (DBGU) Parity Error Interrupt */ +#define AT91C_US_TXEMPTY ( ( unsigned int ) 0x1 << 9 ) /* (DBGU) TXEMPTY Interrupt */ +#define AT91C_US_TXBUFE ( ( unsigned int ) 0x1 << 11 ) /* (DBGU) TXBUFE Interrupt */ +#define AT91C_US_RXBUFF ( ( unsigned int ) 0x1 << 12 ) /* (DBGU) RXBUFF Interrupt */ +#define AT91C_US_COMM_TX ( ( unsigned int ) 0x1 << 30 ) /* (DBGU) COMM_TX Interrupt */ +#define AT91C_US_COMM_RX ( ( unsigned int ) 0x1 << 31 ) /* (DBGU) COMM_RX Interrupt */ +/* -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- */ +/* -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- */ +/* -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- */ +/* -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- */ +#define AT91C_US_FORCE_NTRST ( ( unsigned int ) 0x1 << 0 ) /* (DBGU) Force NTRST in JTAG */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Peripheral Data Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_PDC +{ + AT91_REG PDC_RPR; /* Receive Pointer Register */ + AT91_REG PDC_RCR; /* Receive Counter Register */ + AT91_REG PDC_TPR; /* Transmit Pointer Register */ + AT91_REG PDC_TCR; /* Transmit Counter Register */ + AT91_REG PDC_RNPR; /* Receive Next Pointer Register */ + AT91_REG PDC_RNCR; /* Receive Next Counter Register */ + AT91_REG PDC_TNPR; /* Transmit Next Pointer Register */ + AT91_REG PDC_TNCR; /* Transmit Next Counter Register */ + AT91_REG PDC_PTCR; /* PDC Transfer Control Register */ + AT91_REG PDC_PTSR; /* PDC Transfer Status Register */ +} AT91S_PDC, * AT91PS_PDC; + +/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */ +#define AT91C_PDC_RXTEN ( ( unsigned int ) 0x1 << 0 ) /* (PDC) Receiver Transfer Enable */ +#define AT91C_PDC_RXTDIS ( ( unsigned int ) 0x1 << 1 ) /* (PDC) Receiver Transfer Disable */ +#define AT91C_PDC_TXTEN ( ( unsigned int ) 0x1 << 8 ) /* (PDC) Transmitter Transfer Enable */ +#define AT91C_PDC_TXTDIS ( ( unsigned int ) 0x1 << 9 ) /* (PDC) Transmitter Transfer Disable */ +/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Parallel Input Output Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_PIO +{ + AT91_REG PIO_PER; /* PIO Enable Register */ + AT91_REG PIO_PDR; /* PIO Disable Register */ + AT91_REG PIO_PSR; /* PIO Status Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG PIO_OER; /* Output Enable Register */ + AT91_REG PIO_ODR; /* Output Disable Registerr */ + AT91_REG PIO_OSR; /* Output Status Register */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG PIO_IFER; /* Input Filter Enable Register */ + AT91_REG PIO_IFDR; /* Input Filter Disable Register */ + AT91_REG PIO_IFSR; /* Input Filter Status Register */ + AT91_REG Reserved2[ 1 ]; /* */ + AT91_REG PIO_SODR; /* Set Output Data Register */ + AT91_REG PIO_CODR; /* Clear Output Data Register */ + AT91_REG PIO_ODSR; /* Output Data Status Register */ + AT91_REG PIO_PDSR; /* Pin Data Status Register */ + AT91_REG PIO_IER; /* Interrupt Enable Register */ + AT91_REG PIO_IDR; /* Interrupt Disable Register */ + AT91_REG PIO_IMR; /* Interrupt Mask Register */ + AT91_REG PIO_ISR; /* Interrupt Status Register */ + AT91_REG PIO_MDER; /* Multi-driver Enable Register */ + AT91_REG PIO_MDDR; /* Multi-driver Disable Register */ + AT91_REG PIO_MDSR; /* Multi-driver Status Register */ + AT91_REG Reserved3[ 1 ]; /* */ + AT91_REG PIO_PPUDR; /* Pull-up Disable Register */ + AT91_REG PIO_PPUER; /* Pull-up Enable Register */ + AT91_REG PIO_PPUSR; /* Pad Pull-up Status Register */ + AT91_REG Reserved4[ 1 ]; /* */ + AT91_REG PIO_ASR; /* Select A Register */ + AT91_REG PIO_BSR; /* Select B Register */ + AT91_REG PIO_ABSR; /* AB Select Status Register */ + AT91_REG Reserved5[ 9 ]; /* */ + AT91_REG PIO_OWER; /* Output Write Enable Register */ + AT91_REG PIO_OWDR; /* Output Write Disable Register */ + AT91_REG PIO_OWSR; /* Output Write Status Register */ +} AT91S_PIO, * AT91PS_PIO; + + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Clock Generator Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_CKGR +{ + AT91_REG CKGR_MOR; /* Main Oscillator Register */ + AT91_REG CKGR_MCFR; /* Main Clock Frequency Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG CKGR_PLLR; /* PLL Register */ +} AT91S_CKGR, * AT91PS_CKGR; + +/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */ +#define AT91C_CKGR_MOSCEN ( ( unsigned int ) 0x1 << 0 ) /* (CKGR) Main Oscillator Enable */ +#define AT91C_CKGR_OSCBYPASS ( ( unsigned int ) 0x1 << 1 ) /* (CKGR) Main Oscillator Bypass */ +#define AT91C_CKGR_OSCOUNT ( ( unsigned int ) 0xFF << 8 ) /* (CKGR) Main Oscillator Start-up Time */ +/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */ +#define AT91C_CKGR_MAINF ( ( unsigned int ) 0xFFFF << 0 ) /* (CKGR) Main Clock Frequency */ +#define AT91C_CKGR_MAINRDY ( ( unsigned int ) 0x1 << 16 ) /* (CKGR) Main Clock Ready */ +/* -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- */ +#define AT91C_CKGR_DIV ( ( unsigned int ) 0xFF << 0 ) /* (CKGR) Divider Selected */ +#define AT91C_CKGR_DIV_0 ( ( unsigned int ) 0x0 ) /* (CKGR) Divider output is 0 */ +#define AT91C_CKGR_DIV_BYPASS ( ( unsigned int ) 0x1 ) /* (CKGR) Divider is bypassed */ +#define AT91C_CKGR_PLLCOUNT ( ( unsigned int ) 0x3F << 8 ) /* (CKGR) PLL Counter */ +#define AT91C_CKGR_OUT ( ( unsigned int ) 0x3 << 14 ) /* (CKGR) PLL Output Frequency Range */ +#define AT91C_CKGR_OUT_0 ( ( unsigned int ) 0x0 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_1 ( ( unsigned int ) 0x1 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_2 ( ( unsigned int ) 0x2 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_3 ( ( unsigned int ) 0x3 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_MUL ( ( unsigned int ) 0x7FF << 16 ) /* (CKGR) PLL Multiplier */ +#define AT91C_CKGR_USBDIV ( ( unsigned int ) 0x3 << 28 ) /* (CKGR) Divider for USB Clocks */ +#define AT91C_CKGR_USBDIV_0 ( ( unsigned int ) 0x0 << 28 ) /* (CKGR) Divider output is PLL clock output */ +#define AT91C_CKGR_USBDIV_1 ( ( unsigned int ) 0x1 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 2 */ +#define AT91C_CKGR_USBDIV_2 ( ( unsigned int ) 0x2 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 4 */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Power Management Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_PMC +{ + AT91_REG PMC_SCER; /* System Clock Enable Register */ + AT91_REG PMC_SCDR; /* System Clock Disable Register */ + AT91_REG PMC_SCSR; /* System Clock Status Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */ + AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */ + AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG PMC_MOR; /* Main Oscillator Register */ + AT91_REG PMC_MCFR; /* Main Clock Frequency Register */ + AT91_REG Reserved2[ 1 ]; /* */ + AT91_REG PMC_PLLR; /* PLL Register */ + AT91_REG PMC_MCKR; /* Master Clock Register */ + AT91_REG Reserved3[ 3 ]; /* */ + AT91_REG PMC_PCKR[ 8 ]; /* Programmable Clock Register */ + AT91_REG PMC_IER; /* Interrupt Enable Register */ + AT91_REG PMC_IDR; /* Interrupt Disable Register */ + AT91_REG PMC_SR; /* Status Register */ + AT91_REG PMC_IMR; /* Interrupt Mask Register */ +} AT91S_PMC, * AT91PS_PMC; + +/* -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- */ +#define AT91C_PMC_PCK ( ( unsigned int ) 0x1 << 0 ) /* (PMC) Processor Clock */ +#define AT91C_PMC_UDP ( ( unsigned int ) 0x1 << 7 ) /* (PMC) USB Device Port Clock */ +#define AT91C_PMC_PCK0 ( ( unsigned int ) 0x1 << 8 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK1 ( ( unsigned int ) 0x1 << 9 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK2 ( ( unsigned int ) 0x1 << 10 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK3 ( ( unsigned int ) 0x1 << 11 ) /* (PMC) Programmable Clock Output */ +/* -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- */ +/* -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- */ +/* -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- */ +/* -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- */ +/* -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- */ +/* -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */ +#define AT91C_PMC_CSS ( ( unsigned int ) 0x3 << 0 ) /* (PMC) Programmable Clock Selection */ +#define AT91C_PMC_CSS_SLOW_CLK ( ( unsigned int ) 0x0 ) /* (PMC) Slow Clock is selected */ +#define AT91C_PMC_CSS_MAIN_CLK ( ( unsigned int ) 0x1 ) /* (PMC) Main Clock is selected */ +#define AT91C_PMC_CSS_PLL_CLK ( ( unsigned int ) 0x3 ) /* (PMC) Clock from PLL is selected */ +#define AT91C_PMC_PRES ( ( unsigned int ) 0x7 << 2 ) /* (PMC) Programmable Clock Prescaler */ +#define AT91C_PMC_PRES_CLK ( ( unsigned int ) 0x0 << 2 ) /* (PMC) Selected clock */ +#define AT91C_PMC_PRES_CLK_2 ( ( unsigned int ) 0x1 << 2 ) /* (PMC) Selected clock divided by 2 */ +#define AT91C_PMC_PRES_CLK_4 ( ( unsigned int ) 0x2 << 2 ) /* (PMC) Selected clock divided by 4 */ +#define AT91C_PMC_PRES_CLK_8 ( ( unsigned int ) 0x3 << 2 ) /* (PMC) Selected clock divided by 8 */ +#define AT91C_PMC_PRES_CLK_16 ( ( unsigned int ) 0x4 << 2 ) /* (PMC) Selected clock divided by 16 */ +#define AT91C_PMC_PRES_CLK_32 ( ( unsigned int ) 0x5 << 2 ) /* (PMC) Selected clock divided by 32 */ +#define AT91C_PMC_PRES_CLK_64 ( ( unsigned int ) 0x6 << 2 ) /* (PMC) Selected clock divided by 64 */ +/* -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- */ +/* -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- */ +#define AT91C_PMC_MOSCS ( ( unsigned int ) 0x1 << 0 ) /* (PMC) MOSC Status/Enable/Disable/Mask */ +#define AT91C_PMC_LOCK ( ( unsigned int ) 0x1 << 2 ) /* (PMC) PLL Status/Enable/Disable/Mask */ +#define AT91C_PMC_MCKRDY ( ( unsigned int ) 0x1 << 3 ) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK0RDY ( ( unsigned int ) 0x1 << 8 ) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK1RDY ( ( unsigned int ) 0x1 << 9 ) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK2RDY ( ( unsigned int ) 0x1 << 10 ) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK3RDY ( ( unsigned int ) 0x1 << 11 ) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */ +/* -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */ +/* -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- */ +/* -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Reset Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_RSTC +{ + AT91_REG RSTC_RCR; /* Reset Control Register */ + AT91_REG RSTC_RSR; /* Reset Status Register */ + AT91_REG RSTC_RMR; /* Reset Mode Register */ +} AT91S_RSTC, * AT91PS_RSTC; + +/* -------- SYSC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- */ +#define AT91C_SYSC_PROCRST ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) Processor Reset */ +#define AT91C_SYSC_ICERST ( ( unsigned int ) 0x1 << 1 ) /* (RSTC) ICE Interface Reset */ +#define AT91C_SYSC_PERRST ( ( unsigned int ) 0x1 << 2 ) /* (RSTC) Peripheral Reset */ +#define AT91C_SYSC_EXTRST ( ( unsigned int ) 0x1 << 3 ) /* (RSTC) External Reset */ +#define AT91C_SYSC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (RSTC) Password */ +/* -------- SYSC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- */ +#define AT91C_SYSC_URSTS ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) User Reset Status */ +#define AT91C_SYSC_BODSTS ( ( unsigned int ) 0x1 << 1 ) /* (RSTC) Brown-out Detection Status */ +#define AT91C_SYSC_RSTTYP ( ( unsigned int ) 0x7 << 8 ) /* (RSTC) Reset Type */ +#define AT91C_SYSC_RSTTYP_POWERUP ( ( unsigned int ) 0x0 << 8 ) /* (RSTC) Power-up Reset. VDDCORE rising. */ +#define AT91C_SYSC_RSTTYP_WATCHDOG ( ( unsigned int ) 0x2 << 8 ) /* (RSTC) Watchdog Reset. Watchdog overflow occurred. */ +#define AT91C_SYSC_RSTTYP_SOFTWARE ( ( unsigned int ) 0x3 << 8 ) /* (RSTC) Software Reset. Processor reset required by the software. */ +#define AT91C_SYSC_RSTTYP_USER ( ( unsigned int ) 0x4 << 8 ) /* (RSTC) User Reset. NRST pin detected low. */ +#define AT91C_SYSC_RSTTYP_BROWNOUT ( ( unsigned int ) 0x5 << 8 ) /* (RSTC) Brown-out Reset. */ +#define AT91C_SYSC_NRSTL ( ( unsigned int ) 0x1 << 16 ) /* (RSTC) NRST pin level */ +#define AT91C_SYSC_SRCMP ( ( unsigned int ) 0x1 << 17 ) /* (RSTC) Software Reset Command in Progress. */ +/* -------- SYSC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- */ +#define AT91C_SYSC_URSTEN ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) User Reset Enable */ +#define AT91C_SYSC_URSTIEN ( ( unsigned int ) 0x1 << 4 ) /* (RSTC) User Reset Interrupt Enable */ +#define AT91C_SYSC_ERSTL ( ( unsigned int ) 0xF << 8 ) /* (RSTC) User Reset Enable */ +#define AT91C_SYSC_BODIEN ( ( unsigned int ) 0x1 << 16 ) /* (RSTC) Brown-out Detection Interrupt Enable */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_RTTC +{ + AT91_REG RTTC_RTMR; /* Real-time Mode Register */ + AT91_REG RTTC_RTAR; /* Real-time Alarm Register */ + AT91_REG RTTC_RTVR; /* Real-time Value Register */ + AT91_REG RTTC_RTSR; /* Real-time Status Register */ +} AT91S_RTTC, * AT91PS_RTTC; + +/* -------- SYSC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- */ +#define AT91C_SYSC_RTPRES ( ( unsigned int ) 0xFFFF << 0 ) /* (RTTC) Real-time Timer Prescaler Value */ +#define AT91C_SYSC_ALMIEN ( ( unsigned int ) 0x1 << 16 ) /* (RTTC) Alarm Interrupt Enable */ +#define AT91C_SYSC_RTTINCIEN ( ( unsigned int ) 0x1 << 17 ) /* (RTTC) Real Time Timer Increment Interrupt Enable */ +#define AT91C_SYSC_RTTRST ( ( unsigned int ) 0x1 << 18 ) /* (RTTC) Real Time Timer Restart */ +/* -------- SYSC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- */ +#define AT91C_SYSC_ALMV ( ( unsigned int ) 0x0 << 0 ) /* (RTTC) Alarm Value */ +/* -------- SYSC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- */ +#define AT91C_SYSC_CRTV ( ( unsigned int ) 0x0 << 0 ) /* (RTTC) Current Real-time Value */ +/* -------- SYSC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- */ +#define AT91C_SYSC_ALMS ( ( unsigned int ) 0x1 << 0 ) /* (RTTC) Real-time Alarm Status */ +#define AT91C_SYSC_RTTINC ( ( unsigned int ) 0x1 << 1 ) /* (RTTC) Real-time Timer Increment */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_PITC +{ + AT91_REG PITC_PIMR; /* Period Interval Mode Register */ + AT91_REG PITC_PISR; /* Period Interval Status Register */ + AT91_REG PITC_PIVR; /* Period Interval Value Register */ + AT91_REG PITC_PIIR; /* Period Interval Image Register */ +} AT91S_PITC, * AT91PS_PITC; + +/* -------- SYSC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- */ +#define AT91C_SYSC_PIV ( ( unsigned int ) 0xFFFFF << 0 ) /* (PITC) Periodic Interval Value */ +#define AT91C_SYSC_PITEN ( ( unsigned int ) 0x1 << 24 ) /* (PITC) Periodic Interval Timer Enabled */ +#define AT91C_SYSC_PITIEN ( ( unsigned int ) 0x1 << 25 ) /* (PITC) Periodic Interval Timer Interrupt Enable */ +/* -------- SYSC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- */ +#define AT91C_SYSC_PITS ( ( unsigned int ) 0x1 << 0 ) /* (PITC) Periodic Interval Timer Status */ +/* -------- SYSC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- */ +#define AT91C_SYSC_CPIV ( ( unsigned int ) 0xFFFFF << 0 ) /* (PITC) Current Periodic Interval Value */ +#define AT91C_SYSC_PICNT ( ( unsigned int ) 0xFFF << 20 ) /* (PITC) Periodic Interval Counter */ +/* -------- SYSC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_WDTC +{ + AT91_REG WDTC_WDCR; /* Watchdog Control Register */ + AT91_REG WDTC_WDMR; /* Watchdog Mode Register */ + AT91_REG WDTC_WDSR; /* Watchdog Status Register */ +} AT91S_WDTC, * AT91PS_WDTC; + +/* -------- SYSC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- */ +#define AT91C_SYSC_WDRSTT ( ( unsigned int ) 0x1 << 0 ) /* (WDTC) Watchdog Restart */ +/* -------- SYSC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */ +#define AT91C_SYSC_WDV ( ( unsigned int ) 0xFFF << 0 ) /* (WDTC) Watchdog Timer Restart */ +#define AT91C_SYSC_WDFIEN ( ( unsigned int ) 0x1 << 12 ) /* (WDTC) Watchdog Fault Interrupt Enable */ +#define AT91C_SYSC_WDRSTEN ( ( unsigned int ) 0x1 << 13 ) /* (WDTC) Watchdog Reset Enable */ +#define AT91C_SYSC_WDRPROC ( ( unsigned int ) 0x1 << 14 ) /* (WDTC) Watchdog Timer Restart */ +#define AT91C_SYSC_WDDIS ( ( unsigned int ) 0x1 << 15 ) /* (WDTC) Watchdog Disable */ +#define AT91C_SYSC_WDD ( ( unsigned int ) 0xFFF << 16 ) /* (WDTC) Watchdog Delta Value */ +#define AT91C_SYSC_WDDBGHLT ( ( unsigned int ) 0x1 << 28 ) /* (WDTC) Watchdog Debug Halt */ +#define AT91C_SYSC_WDIDLEHLT ( ( unsigned int ) 0x1 << 29 ) /* (WDTC) Watchdog Idle Halt */ +/* -------- SYSC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- */ +#define AT91C_SYSC_WDUNF ( ( unsigned int ) 0x1 << 0 ) /* (WDTC) Watchdog Underflow */ +#define AT91C_SYSC_WDERR ( ( unsigned int ) 0x1 << 1 ) /* (WDTC) Watchdog Error */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Memory Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_MC +{ + AT91_REG MC_RCR; /* MC Remap Control Register */ + AT91_REG MC_ASR; /* MC Abort Status Register */ + AT91_REG MC_AASR; /* MC Abort Address Status Register */ + AT91_REG Reserved0[ 21 ]; /* */ + AT91_REG MC_FMR; /* MC Flash Mode Register */ + AT91_REG MC_FCR; /* MC Flash Command Register */ + AT91_REG MC_FSR; /* MC Flash Status Register */ +} AT91S_MC, * AT91PS_MC; + +/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */ +#define AT91C_MC_RCB ( ( unsigned int ) 0x1 << 0 ) /* (MC) Remap Command Bit */ +/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */ +#define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Address Abort Status */ +#define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Address Abort Status */ +#define AT91C_MC_ABTSZ ( ( unsigned int ) 0x3 << 8 ) /* (MC) Abort Size Status */ +#define AT91C_MC_ABTSZ_BYTE ( ( unsigned int ) 0x0 << 8 ) /* (MC) Byte */ +#define AT91C_MC_ABTSZ_HWORD ( ( unsigned int ) 0x1 << 8 ) /* (MC) Half-word */ +#define AT91C_MC_ABTSZ_WORD ( ( unsigned int ) 0x2 << 8 ) /* (MC) Word */ +#define AT91C_MC_ABTTYP ( ( unsigned int ) 0x3 << 10 ) /* (MC) Abort Type Status */ +#define AT91C_MC_ABTTYP_DATAR ( ( unsigned int ) 0x0 << 10 ) /* (MC) Data Read */ +#define AT91C_MC_ABTTYP_DATAW ( ( unsigned int ) 0x1 << 10 ) /* (MC) Data Write */ +#define AT91C_MC_ABTTYP_FETCH ( ( unsigned int ) 0x2 << 10 ) /* (MC) Code Fetch */ +#define AT91C_MC_MST0 ( ( unsigned int ) 0x1 << 16 ) /* (MC) Master 0 Abort Source */ +#define AT91C_MC_MST1 ( ( unsigned int ) 0x1 << 17 ) /* (MC) Master 1 Abort Source */ +#define AT91C_MC_SVMST0 ( ( unsigned int ) 0x1 << 24 ) /* (MC) Saved Master 0 Abort Source */ +#define AT91C_MC_SVMST1 ( ( unsigned int ) 0x1 << 25 ) /* (MC) Saved Master 1 Abort Source */ +/* -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- */ +#define AT91C_MC_FRDY ( ( unsigned int ) 0x1 << 0 ) /* (MC) Flash Ready */ +#define AT91C_MC_LOCKE ( ( unsigned int ) 0x1 << 2 ) /* (MC) Lock Error */ +#define AT91C_MC_PROGE ( ( unsigned int ) 0x1 << 3 ) /* (MC) Programming Error */ +#define AT91C_MC_NEBP ( ( unsigned int ) 0x1 << 7 ) /* (MC) No Erase Before Programming */ +#define AT91C_MC_FWS ( ( unsigned int ) 0x3 << 8 ) /* (MC) Flash Wait State */ +#define AT91C_MC_FWS_0FWS ( ( unsigned int ) 0x0 << 8 ) /* (MC) 1 cycle for Read, 2 for Write operations */ +#define AT91C_MC_FWS_1FWS ( ( unsigned int ) 0x1 << 8 ) /* (MC) 2 cycles for Read, 3 for Write operations */ +#define AT91C_MC_FWS_2FWS ( ( unsigned int ) 0x2 << 8 ) /* (MC) 3 cycles for Read, 4 for Write operations */ +#define AT91C_MC_FWS_3FWS ( ( unsigned int ) 0x3 << 8 ) /* (MC) 4 cycles for Read, 4 for Write operations */ +#define AT91C_MC_FMCN ( ( unsigned int ) 0xFF << 16 ) /* (MC) Flash Microsecond Cycle Number */ +/* -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- */ +#define AT91C_MC_FCMD ( ( unsigned int ) 0xF << 0 ) /* (MC) Flash Command */ +#define AT91C_MC_FCMD_START_PROG ( ( unsigned int ) 0x1 ) /* (MC) Starts the programming of th epage specified by PAGEN. */ +#define AT91C_MC_FCMD_LOCK ( ( unsigned int ) 0x2 ) /* (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */ +#define AT91C_MC_FCMD_PROG_AND_LOCK ( ( unsigned int ) 0x3 ) /* (MC) The lock sequence automatically happens after the programming sequence is completed. */ +#define AT91C_MC_FCMD_UNLOCK ( ( unsigned int ) 0x4 ) /* (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */ +#define AT91C_MC_FCMD_ERASE_ALL ( ( unsigned int ) 0x8 ) /* (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. */ +#define AT91C_MC_FCMD_SET_GP_NVM ( ( unsigned int ) 0xB ) /* (MC) Set General Purpose NVM bits. */ +#define AT91C_MC_FCMD_CLR_GP_NVM ( ( unsigned int ) 0xD ) /* (MC) Clear General Purpose NVM bits. */ +#define AT91C_MC_FCMD_SET_SECURITY ( ( unsigned int ) 0xF ) /* (MC) Set Security Bit. */ +#define AT91C_MC_PAGEN ( ( unsigned int ) 0x3FF << 8 ) /* (MC) Page Number */ +#define AT91C_MC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (MC) Writing Protect Key */ +/* -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- */ +#define AT91C_MC_SECURITY ( ( unsigned int ) 0x1 << 4 ) /* (MC) Security Bit Status */ +#define AT91C_MC_GPNVM0 ( ( unsigned int ) 0x1 << 8 ) /* (MC) Sector 0 Lock Status */ +#define AT91C_MC_GPNVM1 ( ( unsigned int ) 0x1 << 9 ) /* (MC) Sector 1 Lock Status */ +#define AT91C_MC_GPNVM2 ( ( unsigned int ) 0x1 << 10 ) /* (MC) Sector 2 Lock Status */ +#define AT91C_MC_GPNVM3 ( ( unsigned int ) 0x1 << 11 ) /* (MC) Sector 3 Lock Status */ +#define AT91C_MC_GPNVM4 ( ( unsigned int ) 0x1 << 12 ) /* (MC) Sector 4 Lock Status */ +#define AT91C_MC_GPNVM5 ( ( unsigned int ) 0x1 << 13 ) /* (MC) Sector 5 Lock Status */ +#define AT91C_MC_GPNVM6 ( ( unsigned int ) 0x1 << 14 ) /* (MC) Sector 6 Lock Status */ +#define AT91C_MC_GPNVM7 ( ( unsigned int ) 0x1 << 15 ) /* (MC) Sector 7 Lock Status */ +#define AT91C_MC_LOCKS0 ( ( unsigned int ) 0x1 << 16 ) /* (MC) Sector 0 Lock Status */ +#define AT91C_MC_LOCKS1 ( ( unsigned int ) 0x1 << 17 ) /* (MC) Sector 1 Lock Status */ +#define AT91C_MC_LOCKS2 ( ( unsigned int ) 0x1 << 18 ) /* (MC) Sector 2 Lock Status */ +#define AT91C_MC_LOCKS3 ( ( unsigned int ) 0x1 << 19 ) /* (MC) Sector 3 Lock Status */ +#define AT91C_MC_LOCKS4 ( ( unsigned int ) 0x1 << 20 ) /* (MC) Sector 4 Lock Status */ +#define AT91C_MC_LOCKS5 ( ( unsigned int ) 0x1 << 21 ) /* (MC) Sector 5 Lock Status */ +#define AT91C_MC_LOCKS6 ( ( unsigned int ) 0x1 << 22 ) /* (MC) Sector 6 Lock Status */ +#define AT91C_MC_LOCKS7 ( ( unsigned int ) 0x1 << 23 ) /* (MC) Sector 7 Lock Status */ +#define AT91C_MC_LOCKS8 ( ( unsigned int ) 0x1 << 24 ) /* (MC) Sector 8 Lock Status */ +#define AT91C_MC_LOCKS9 ( ( unsigned int ) 0x1 << 25 ) /* (MC) Sector 9 Lock Status */ +#define AT91C_MC_LOCKS10 ( ( unsigned int ) 0x1 << 26 ) /* (MC) Sector 10 Lock Status */ +#define AT91C_MC_LOCKS11 ( ( unsigned int ) 0x1 << 27 ) /* (MC) Sector 11 Lock Status */ +#define AT91C_MC_LOCKS12 ( ( unsigned int ) 0x1 << 28 ) /* (MC) Sector 12 Lock Status */ +#define AT91C_MC_LOCKS13 ( ( unsigned int ) 0x1 << 29 ) /* (MC) Sector 13 Lock Status */ +#define AT91C_MC_LOCKS14 ( ( unsigned int ) 0x1 << 30 ) /* (MC) Sector 14 Lock Status */ +#define AT91C_MC_LOCKS15 ( ( unsigned int ) 0x1 << 31 ) /* (MC) Sector 15 Lock Status */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_SPI +{ + AT91_REG SPI_CR; /* Control Register */ + AT91_REG SPI_MR; /* Mode Register */ + AT91_REG SPI_RDR; /* Receive Data Register */ + AT91_REG SPI_TDR; /* Transmit Data Register */ + AT91_REG SPI_SR; /* Status Register */ + AT91_REG SPI_IER; /* Interrupt Enable Register */ + AT91_REG SPI_IDR; /* Interrupt Disable Register */ + AT91_REG SPI_IMR; /* Interrupt Mask Register */ + AT91_REG Reserved0[ 4 ]; /* */ + AT91_REG SPI_CSR[ 4 ]; /* Chip Select Register */ + AT91_REG Reserved1[ 48 ]; /* */ + AT91_REG SPI_RPR; /* Receive Pointer Register */ + AT91_REG SPI_RCR; /* Receive Counter Register */ + AT91_REG SPI_TPR; /* Transmit Pointer Register */ + AT91_REG SPI_TCR; /* Transmit Counter Register */ + AT91_REG SPI_RNPR; /* Receive Next Pointer Register */ + AT91_REG SPI_RNCR; /* Receive Next Counter Register */ + AT91_REG SPI_TNPR; /* Transmit Next Pointer Register */ + AT91_REG SPI_TNCR; /* Transmit Next Counter Register */ + AT91_REG SPI_PTCR; /* PDC Transfer Control Register */ + AT91_REG SPI_PTSR; /* PDC Transfer Status Register */ +} AT91S_SPI, * AT91PS_SPI; + +/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */ +#define AT91C_SPI_SPIEN ( ( unsigned int ) 0x1 << 0 ) /* (SPI) SPI Enable */ +#define AT91C_SPI_SPIDIS ( ( unsigned int ) 0x1 << 1 ) /* (SPI) SPI Disable */ +#define AT91C_SPI_SWRST ( ( unsigned int ) 0x1 << 7 ) /* (SPI) SPI Software reset */ +#define AT91C_SPI_LASTXFER ( ( unsigned int ) 0x1 << 24 ) /* (SPI) SPI Last Transfer */ +/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */ +#define AT91C_SPI_MSTR ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Master/Slave Mode */ +#define AT91C_SPI_PS ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Peripheral Select */ +#define AT91C_SPI_PS_FIXED ( ( unsigned int ) 0x0 << 1 ) /* (SPI) Fixed Peripheral Select */ +#define AT91C_SPI_PS_VARIABLE ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Variable Peripheral Select */ +#define AT91C_SPI_PCSDEC ( ( unsigned int ) 0x1 << 2 ) /* (SPI) Chip Select Decode */ +#define AT91C_SPI_FDIV ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Clock Selection */ +#define AT91C_SPI_MODFDIS ( ( unsigned int ) 0x1 << 4 ) /* (SPI) Mode Fault Detection */ +#define AT91C_SPI_LLB ( ( unsigned int ) 0x1 << 7 ) /* (SPI) Clock Selection */ +#define AT91C_SPI_PCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select */ +#define AT91C_SPI_DLYBCS ( ( unsigned int ) 0xFF << 24 ) /* (SPI) Delay Between Chip Selects */ +/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */ +#define AT91C_SPI_RD ( ( unsigned int ) 0xFFFF << 0 ) /* (SPI) Receive Data */ +#define AT91C_SPI_RPCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */ +/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */ +#define AT91C_SPI_TD ( ( unsigned int ) 0xFFFF << 0 ) /* (SPI) Transmit Data */ +#define AT91C_SPI_TPCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */ +/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ +#define AT91C_SPI_RDRF ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Receive Data Register Full */ +#define AT91C_SPI_TDRE ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Transmit Data Register Empty */ +#define AT91C_SPI_MODF ( ( unsigned int ) 0x1 << 2 ) /* (SPI) Mode Fault Error */ +#define AT91C_SPI_OVRES ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Overrun Error Status */ +#define AT91C_SPI_ENDRX ( ( unsigned int ) 0x1 << 4 ) /* (SPI) End of Receiver Transfer */ +#define AT91C_SPI_ENDTX ( ( unsigned int ) 0x1 << 5 ) /* (SPI) End of Receiver Transfer */ +#define AT91C_SPI_RXBUFF ( ( unsigned int ) 0x1 << 6 ) /* (SPI) RXBUFF Interrupt */ +#define AT91C_SPI_TXBUFE ( ( unsigned int ) 0x1 << 7 ) /* (SPI) TXBUFE Interrupt */ +#define AT91C_SPI_NSSR ( ( unsigned int ) 0x1 << 8 ) /* (SPI) NSSR Interrupt */ +#define AT91C_SPI_TXEMPTY ( ( unsigned int ) 0x1 << 9 ) /* (SPI) TXEMPTY Interrupt */ +#define AT91C_SPI_SPIENS ( ( unsigned int ) 0x1 << 16 ) /* (SPI) Enable Status */ +/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ +/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ +/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */ +/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */ +#define AT91C_SPI_CPOL ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Clock Polarity */ +#define AT91C_SPI_NCPHA ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Clock Phase */ +#define AT91C_SPI_CSAAT ( ( unsigned int ) 0x1 << 2 ) /* (SPI) Chip Select Active After Transfer */ +#define AT91C_SPI_BITS ( ( unsigned int ) 0xF << 4 ) /* (SPI) Bits Per Transfer */ +#define AT91C_SPI_BITS_8 ( ( unsigned int ) 0x0 << 4 ) /* (SPI) 8 Bits Per transfer */ +#define AT91C_SPI_BITS_9 ( ( unsigned int ) 0x1 << 4 ) /* (SPI) 9 Bits Per transfer */ +#define AT91C_SPI_BITS_10 ( ( unsigned int ) 0x2 << 4 ) /* (SPI) 10 Bits Per transfer */ +#define AT91C_SPI_BITS_11 ( ( unsigned int ) 0x3 << 4 ) /* (SPI) 11 Bits Per transfer */ +#define AT91C_SPI_BITS_12 ( ( unsigned int ) 0x4 << 4 ) /* (SPI) 12 Bits Per transfer */ +#define AT91C_SPI_BITS_13 ( ( unsigned int ) 0x5 << 4 ) /* (SPI) 13 Bits Per transfer */ +#define AT91C_SPI_BITS_14 ( ( unsigned int ) 0x6 << 4 ) /* (SPI) 14 Bits Per transfer */ +#define AT91C_SPI_BITS_15 ( ( unsigned int ) 0x7 << 4 ) /* (SPI) 15 Bits Per transfer */ +#define AT91C_SPI_BITS_16 ( ( unsigned int ) 0x8 << 4 ) /* (SPI) 16 Bits Per transfer */ +#define AT91C_SPI_SCBR ( ( unsigned int ) 0xFF << 8 ) /* (SPI) Serial Clock Baud Rate */ +#define AT91C_SPI_DLYBS ( ( unsigned int ) 0xFF << 16 ) /* (SPI) Serial Clock Baud Rate */ +#define AT91C_SPI_DLYBCT ( ( unsigned int ) 0xFF << 24 ) /* (SPI) Delay Between Consecutive Transfers */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Analog to Digital Convertor */ +/* ***************************************************************************** */ +typedef struct _AT91S_ADC +{ + AT91_REG ADC_CR; /* ADC Control Register */ + AT91_REG ADC_MR; /* ADC Mode Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG ADC_CHER; /* ADC Channel Enable Register */ + AT91_REG ADC_CHDR; /* ADC Channel Disable Register */ + AT91_REG ADC_CHSR; /* ADC Channel Status Register */ + AT91_REG ADC_SR; /* ADC Status Register */ + AT91_REG ADC_LCDR; /* ADC Last Converted Data Register */ + AT91_REG ADC_IER; /* ADC Interrupt Enable Register */ + AT91_REG ADC_IDR; /* ADC Interrupt Disable Register */ + AT91_REG ADC_IMR; /* ADC Interrupt Mask Register */ + AT91_REG ADC_CDR0; /* ADC Channel Data Register 0 */ + AT91_REG ADC_CDR1; /* ADC Channel Data Register 1 */ + AT91_REG ADC_CDR2; /* ADC Channel Data Register 2 */ + AT91_REG ADC_CDR3; /* ADC Channel Data Register 3 */ + AT91_REG ADC_CDR4; /* ADC Channel Data Register 4 */ + AT91_REG ADC_CDR5; /* ADC Channel Data Register 5 */ + AT91_REG ADC_CDR6; /* ADC Channel Data Register 6 */ + AT91_REG ADC_CDR7; /* ADC Channel Data Register 7 */ + AT91_REG Reserved1[ 44 ]; /* */ + AT91_REG ADC_RPR; /* Receive Pointer Register */ + AT91_REG ADC_RCR; /* Receive Counter Register */ + AT91_REG ADC_TPR; /* Transmit Pointer Register */ + AT91_REG ADC_TCR; /* Transmit Counter Register */ + AT91_REG ADC_RNPR; /* Receive Next Pointer Register */ + AT91_REG ADC_RNCR; /* Receive Next Counter Register */ + AT91_REG ADC_TNPR; /* Transmit Next Pointer Register */ + AT91_REG ADC_TNCR; /* Transmit Next Counter Register */ + AT91_REG ADC_PTCR; /* PDC Transfer Control Register */ + AT91_REG ADC_PTSR; /* PDC Transfer Status Register */ +} AT91S_ADC, * AT91PS_ADC; + +/* -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- */ +#define AT91C_ADC_SWRST ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Software Reset */ +#define AT91C_ADC_START ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Start Conversion */ +/* -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- */ +#define AT91C_ADC_TRGEN ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Trigger Enable */ +#define AT91C_ADC_TRGEN_DIS ( ( unsigned int ) 0x0 ) /* (ADC) Hardware triggers are disabled. Starting a conversion is only possible by software */ +#define AT91C_ADC_TRGEN_EN ( ( unsigned int ) 0x1 ) /* (ADC) Hardware trigger selected by TRGSEL field is enabled. */ +#define AT91C_ADC_TRGSEL ( ( unsigned int ) 0x7 << 1 ) /* (ADC) Trigger Selection */ +#define AT91C_ADC_TRGSEL_TIOA0 ( ( unsigned int ) 0x0 << 1 ) /* (ADC) Selected TRGSEL = TIAO0 */ +#define AT91C_ADC_TRGSEL_TIOA1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Selected TRGSEL = TIAO1 */ +#define AT91C_ADC_TRGSEL_TIOA2 ( ( unsigned int ) 0x2 << 1 ) /* (ADC) Selected TRGSEL = TIAO2 */ +#define AT91C_ADC_TRGSEL_TIOA3 ( ( unsigned int ) 0x3 << 1 ) /* (ADC) Selected TRGSEL = TIAO3 */ +#define AT91C_ADC_TRGSEL_TIOA4 ( ( unsigned int ) 0x4 << 1 ) /* (ADC) Selected TRGSEL = TIAO4 */ +#define AT91C_ADC_TRGSEL_TIOA5 ( ( unsigned int ) 0x5 << 1 ) /* (ADC) Selected TRGSEL = TIAO5 */ +#define AT91C_ADC_TRGSEL_EXT ( ( unsigned int ) 0x6 << 1 ) /* (ADC) Selected TRGSEL = External Trigger */ +#define AT91C_ADC_LOWRES ( ( unsigned int ) 0x1 << 4 ) /* (ADC) Resolution. */ +#define AT91C_ADC_LOWRES_10_BIT ( ( unsigned int ) 0x0 << 4 ) /* (ADC) 10-bit resolution */ +#define AT91C_ADC_LOWRES_8_BIT ( ( unsigned int ) 0x1 << 4 ) /* (ADC) 8-bit resolution */ +#define AT91C_ADC_SLEEP ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Sleep Mode */ +#define AT91C_ADC_SLEEP_NORMAL_MODE ( ( unsigned int ) 0x0 << 5 ) /* (ADC) Normal Mode */ +#define AT91C_ADC_SLEEP_MODE ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Sleep Mode */ +#define AT91C_ADC_PRESCAL ( ( unsigned int ) 0x3F << 8 ) /* (ADC) Prescaler rate selection */ +#define AT91C_ADC_STARTUP ( ( unsigned int ) 0x1F << 16 ) /* (ADC) Startup Time */ +#define AT91C_ADC_SHTIM ( ( unsigned int ) 0xF << 24 ) /* (ADC) Sample & Hold Time */ +/* -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- */ +#define AT91C_ADC_CH0 ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Channel 0 */ +#define AT91C_ADC_CH1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Channel 1 */ +#define AT91C_ADC_CH2 ( ( unsigned int ) 0x1 << 2 ) /* (ADC) Channel 2 */ +#define AT91C_ADC_CH3 ( ( unsigned int ) 0x1 << 3 ) /* (ADC) Channel 3 */ +#define AT91C_ADC_CH4 ( ( unsigned int ) 0x1 << 4 ) /* (ADC) Channel 4 */ +#define AT91C_ADC_CH5 ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Channel 5 */ +#define AT91C_ADC_CH6 ( ( unsigned int ) 0x1 << 6 ) /* (ADC) Channel 6 */ +#define AT91C_ADC_CH7 ( ( unsigned int ) 0x1 << 7 ) /* (ADC) Channel 7 */ +/* -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- */ +/* -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- */ +/* -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- */ +#define AT91C_ADC_EOC0 ( ( unsigned int ) 0x1 << 0 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC2 ( ( unsigned int ) 0x1 << 2 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC3 ( ( unsigned int ) 0x1 << 3 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC4 ( ( unsigned int ) 0x1 << 4 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC5 ( ( unsigned int ) 0x1 << 5 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC6 ( ( unsigned int ) 0x1 << 6 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC7 ( ( unsigned int ) 0x1 << 7 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_OVRE0 ( ( unsigned int ) 0x1 << 8 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE1 ( ( unsigned int ) 0x1 << 9 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE2 ( ( unsigned int ) 0x1 << 10 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE3 ( ( unsigned int ) 0x1 << 11 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE4 ( ( unsigned int ) 0x1 << 12 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE5 ( ( unsigned int ) 0x1 << 13 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE6 ( ( unsigned int ) 0x1 << 14 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE7 ( ( unsigned int ) 0x1 << 15 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_DRDY ( ( unsigned int ) 0x1 << 16 ) /* (ADC) Data Ready */ +#define AT91C_ADC_GOVRE ( ( unsigned int ) 0x1 << 17 ) /* (ADC) General Overrun */ +#define AT91C_ADC_ENDRX ( ( unsigned int ) 0x1 << 18 ) /* (ADC) End of Receiver Transfer */ +#define AT91C_ADC_RXBUFF ( ( unsigned int ) 0x1 << 19 ) /* (ADC) RXBUFF Interrupt */ +/* -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- */ +#define AT91C_ADC_LDATA ( ( unsigned int ) 0x3FF << 0 ) /* (ADC) Last Data Converted */ +/* -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- */ +/* -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- */ +/* -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- */ +/* -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- */ +#define AT91C_ADC_DATA ( ( unsigned int ) 0x3FF << 0 ) /* (ADC) Converted Data */ +/* -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- */ +/* -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- */ +/* -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- */ +/* -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- */ +/* -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- */ +/* -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- */ +/* -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_SSC +{ + AT91_REG SSC_CR; /* Control Register */ + AT91_REG SSC_CMR; /* Clock Mode Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG SSC_RCMR; /* Receive Clock ModeRegister */ + AT91_REG SSC_RFMR; /* Receive Frame Mode Register */ + AT91_REG SSC_TCMR; /* Transmit Clock Mode Register */ + AT91_REG SSC_TFMR; /* Transmit Frame Mode Register */ + AT91_REG SSC_RHR; /* Receive Holding Register */ + AT91_REG SSC_THR; /* Transmit Holding Register */ + AT91_REG Reserved1[ 2 ]; /* */ + AT91_REG SSC_RSHR; /* Receive Sync Holding Register */ + AT91_REG SSC_TSHR; /* Transmit Sync Holding Register */ + AT91_REG SSC_RC0R; /* Receive Compare 0 Register */ + AT91_REG SSC_RC1R; /* Receive Compare 1 Register */ + AT91_REG SSC_SR; /* Status Register */ + AT91_REG SSC_IER; /* Interrupt Enable Register */ + AT91_REG SSC_IDR; /* Interrupt Disable Register */ + AT91_REG SSC_IMR; /* Interrupt Mask Register */ + AT91_REG Reserved2[ 44 ]; /* */ + AT91_REG SSC_RPR; /* Receive Pointer Register */ + AT91_REG SSC_RCR; /* Receive Counter Register */ + AT91_REG SSC_TPR; /* Transmit Pointer Register */ + AT91_REG SSC_TCR; /* Transmit Counter Register */ + AT91_REG SSC_RNPR; /* Receive Next Pointer Register */ + AT91_REG SSC_RNCR; /* Receive Next Counter Register */ + AT91_REG SSC_TNPR; /* Transmit Next Pointer Register */ + AT91_REG SSC_TNCR; /* Transmit Next Counter Register */ + AT91_REG SSC_PTCR; /* PDC Transfer Control Register */ + AT91_REG SSC_PTSR; /* PDC Transfer Status Register */ +} AT91S_SSC, * AT91PS_SSC; + +/* -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- */ +#define AT91C_SSC_RXEN ( ( unsigned int ) 0x1 << 0 ) /* (SSC) Receive Enable */ +#define AT91C_SSC_RXDIS ( ( unsigned int ) 0x1 << 1 ) /* (SSC) Receive Disable */ +#define AT91C_SSC_TXEN ( ( unsigned int ) 0x1 << 8 ) /* (SSC) Transmit Enable */ +#define AT91C_SSC_TXDIS ( ( unsigned int ) 0x1 << 9 ) /* (SSC) Transmit Disable */ +#define AT91C_SSC_SWRST ( ( unsigned int ) 0x1 << 15 ) /* (SSC) Software Reset */ +/* -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- */ +#define AT91C_SSC_CKS ( ( unsigned int ) 0x3 << 0 ) /* (SSC) Receive/Transmit Clock Selection */ +#define AT91C_SSC_CKS_DIV ( ( unsigned int ) 0x0 ) /* (SSC) Divided Clock */ +#define AT91C_SSC_CKS_TK ( ( unsigned int ) 0x1 ) /* (SSC) TK Clock signal */ +#define AT91C_SSC_CKS_RK ( ( unsigned int ) 0x2 ) /* (SSC) RK pin */ +#define AT91C_SSC_CKO ( ( unsigned int ) 0x7 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode Selection */ +#define AT91C_SSC_CKO_NONE ( ( unsigned int ) 0x0 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only */ +#define AT91C_SSC_CKO_CONTINUOUS ( ( unsigned int ) 0x1 << 2 ) /* (SSC) Continuous Receive/Transmit Clock RK pin: Output */ +#define AT91C_SSC_CKO_DATA_TX ( ( unsigned int ) 0x2 << 2 ) /* (SSC) Receive/Transmit Clock only during data transfers RK pin: Output */ +#define AT91C_SSC_CKI ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Receive/Transmit Clock Inversion */ +#define AT91C_SSC_CKG ( ( unsigned int ) 0x3 << 6 ) /* (SSC) Receive/Transmit Clock Gating Selection */ +#define AT91C_SSC_CKG_NONE ( ( unsigned int ) 0x0 << 6 ) /* (SSC) Receive/Transmit Clock Gating: None, continuous clock */ +#define AT91C_SSC_CKG_LOW ( ( unsigned int ) 0x1 << 6 ) /* (SSC) Receive/Transmit Clock enabled only if RF Low */ +#define AT91C_SSC_CKG_HIGH ( ( unsigned int ) 0x2 << 6 ) /* (SSC) Receive/Transmit Clock enabled only if RF High */ +#define AT91C_SSC_START ( ( unsigned int ) 0xF << 8 ) /* (SSC) Receive/Transmit Start Selection */ +#define AT91C_SSC_START_CONTINUOUS ( ( unsigned int ) 0x0 << 8 ) /* (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */ +#define AT91C_SSC_START_TX ( ( unsigned int ) 0x1 << 8 ) /* (SSC) Transmit/Receive start */ +#define AT91C_SSC_START_LOW_RF ( ( unsigned int ) 0x2 << 8 ) /* (SSC) Detection of a low level on RF input */ +#define AT91C_SSC_START_HIGH_RF ( ( unsigned int ) 0x3 << 8 ) /* (SSC) Detection of a high level on RF input */ +#define AT91C_SSC_START_FALL_RF ( ( unsigned int ) 0x4 << 8 ) /* (SSC) Detection of a falling edge on RF input */ +#define AT91C_SSC_START_RISE_RF ( ( unsigned int ) 0x5 << 8 ) /* (SSC) Detection of a rising edge on RF input */ +#define AT91C_SSC_START_LEVEL_RF ( ( unsigned int ) 0x6 << 8 ) /* (SSC) Detection of any level change on RF input */ +#define AT91C_SSC_START_EDGE_RF ( ( unsigned int ) 0x7 << 8 ) /* (SSC) Detection of any edge on RF input */ +#define AT91C_SSC_START_0 ( ( unsigned int ) 0x8 << 8 ) /* (SSC) Compare 0 */ +#define AT91C_SSC_STOP ( ( unsigned int ) 0x1 << 12 ) /* (SSC) Receive Stop Selection */ +#define AT91C_SSC_STTOUT ( ( unsigned int ) 0x1 << 15 ) /* (SSC) Receive/Transmit Start Output Selection */ +#define AT91C_SSC_STTDLY ( ( unsigned int ) 0xFF << 16 ) /* (SSC) Receive/Transmit Start Delay */ +#define AT91C_SSC_PERIOD ( ( unsigned int ) 0xFF << 24 ) /* (SSC) Receive/Transmit Period Divider Selection */ +/* -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- */ +#define AT91C_SSC_DATLEN ( ( unsigned int ) 0x1F << 0 ) /* (SSC) Data Length */ +#define AT91C_SSC_LOOP ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Loop Mode */ +#define AT91C_SSC_MSBF ( ( unsigned int ) 0x1 << 7 ) /* (SSC) Most Significant Bit First */ +#define AT91C_SSC_DATNB ( ( unsigned int ) 0xF << 8 ) /* (SSC) Data Number per Frame */ +#define AT91C_SSC_FSLEN ( ( unsigned int ) 0xF << 16 ) /* (SSC) Receive/Transmit Frame Sync length */ +#define AT91C_SSC_FSOS ( ( unsigned int ) 0x7 << 20 ) /* (SSC) Receive/Transmit Frame Sync Output Selection */ +#define AT91C_SSC_FSOS_NONE ( ( unsigned int ) 0x0 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only */ +#define AT91C_SSC_FSOS_NEGATIVE ( ( unsigned int ) 0x1 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse */ +#define AT91C_SSC_FSOS_POSITIVE ( ( unsigned int ) 0x2 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse */ +#define AT91C_SSC_FSOS_LOW ( ( unsigned int ) 0x3 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer */ +#define AT91C_SSC_FSOS_HIGH ( ( unsigned int ) 0x4 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer */ +#define AT91C_SSC_FSOS_TOGGLE ( ( unsigned int ) 0x5 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer */ +#define AT91C_SSC_FSEDGE ( ( unsigned int ) 0x1 << 24 ) /* (SSC) Frame Sync Edge Detection */ +/* -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- */ +/* -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- */ +#define AT91C_SSC_DATDEF ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Data Default Value */ +#define AT91C_SSC_FSDEN ( ( unsigned int ) 0x1 << 23 ) /* (SSC) Frame Sync Data Enable */ +/* -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- */ +#define AT91C_SSC_TXRDY ( ( unsigned int ) 0x1 << 0 ) /* (SSC) Transmit Ready */ +#define AT91C_SSC_TXEMPTY ( ( unsigned int ) 0x1 << 1 ) /* (SSC) Transmit Empty */ +#define AT91C_SSC_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (SSC) End Of Transmission */ +#define AT91C_SSC_TXBUFE ( ( unsigned int ) 0x1 << 3 ) /* (SSC) Transmit Buffer Empty */ +#define AT91C_SSC_RXRDY ( ( unsigned int ) 0x1 << 4 ) /* (SSC) Receive Ready */ +#define AT91C_SSC_OVRUN ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Receive Overrun */ +#define AT91C_SSC_ENDRX ( ( unsigned int ) 0x1 << 6 ) /* (SSC) End of Reception */ +#define AT91C_SSC_RXBUFF ( ( unsigned int ) 0x1 << 7 ) /* (SSC) Receive Buffer Full */ +#define AT91C_SSC_CP0 ( ( unsigned int ) 0x1 << 8 ) /* (SSC) Compare 0 */ +#define AT91C_SSC_CP1 ( ( unsigned int ) 0x1 << 9 ) /* (SSC) Compare 1 */ +#define AT91C_SSC_TXSYN ( ( unsigned int ) 0x1 << 10 ) /* (SSC) Transmit Sync */ +#define AT91C_SSC_RXSYN ( ( unsigned int ) 0x1 << 11 ) /* (SSC) Receive Sync */ +#define AT91C_SSC_TXENA ( ( unsigned int ) 0x1 << 16 ) /* (SSC) Transmit Enable */ +#define AT91C_SSC_RXENA ( ( unsigned int ) 0x1 << 17 ) /* (SSC) Receive Enable */ +/* -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- */ +/* -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- */ +/* -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Usart */ +/* ***************************************************************************** */ +typedef struct _AT91S_USART +{ + AT91_REG US_CR; /* Control Register */ + AT91_REG US_MR; /* Mode Register */ + AT91_REG US_IER; /* Interrupt Enable Register */ + AT91_REG US_IDR; /* Interrupt Disable Register */ + AT91_REG US_IMR; /* Interrupt Mask Register */ + AT91_REG US_CSR; /* Channel Status Register */ + AT91_REG US_RHR; /* Receiver Holding Register */ + AT91_REG US_THR; /* Transmitter Holding Register */ + AT91_REG US_BRGR; /* Baud Rate Generator Register */ + AT91_REG US_RTOR; /* Receiver Time-out Register */ + AT91_REG US_TTGR; /* Transmitter Time-guard Register */ + AT91_REG Reserved0[ 5 ]; /* */ + AT91_REG US_FIDI; /* FI_DI_Ratio Register */ + AT91_REG US_NER; /* Nb Errors Register */ + AT91_REG US_XXR; /* XON_XOFF Register */ + AT91_REG US_IF; /* IRDA_FILTER Register */ + AT91_REG Reserved1[ 44 ]; /* */ + AT91_REG US_RPR; /* Receive Pointer Register */ + AT91_REG US_RCR; /* Receive Counter Register */ + AT91_REG US_TPR; /* Transmit Pointer Register */ + AT91_REG US_TCR; /* Transmit Counter Register */ + AT91_REG US_RNPR; /* Receive Next Pointer Register */ + AT91_REG US_RNCR; /* Receive Next Counter Register */ + AT91_REG US_TNPR; /* Transmit Next Pointer Register */ + AT91_REG US_TNCR; /* Transmit Next Counter Register */ + AT91_REG US_PTCR; /* PDC Transfer Control Register */ + AT91_REG US_PTSR; /* PDC Transfer Status Register */ +} AT91S_USART, * AT91PS_USART; + +/* -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- */ +#define AT91C_US_RSTSTA ( ( unsigned int ) 0x1 << 8 ) /* (USART) Reset Status Bits */ +#define AT91C_US_STTBRK ( ( unsigned int ) 0x1 << 9 ) /* (USART) Start Break */ +#define AT91C_US_STPBRK ( ( unsigned int ) 0x1 << 10 ) /* (USART) Stop Break */ +#define AT91C_US_STTTO ( ( unsigned int ) 0x1 << 11 ) /* (USART) Start Time-out */ +#define AT91C_US_SENDA ( ( unsigned int ) 0x1 << 12 ) /* (USART) Send Address */ +#define AT91C_US_RSTIT ( ( unsigned int ) 0x1 << 13 ) /* (USART) Reset Iterations */ +#define AT91C_US_RSTNACK ( ( unsigned int ) 0x1 << 14 ) /* (USART) Reset Non Acknowledge */ +#define AT91C_US_RETTO ( ( unsigned int ) 0x1 << 15 ) /* (USART) Rearm Time-out */ +#define AT91C_US_DTREN ( ( unsigned int ) 0x1 << 16 ) /* (USART) Data Terminal ready Enable */ +#define AT91C_US_DTRDIS ( ( unsigned int ) 0x1 << 17 ) /* (USART) Data Terminal ready Disable */ +#define AT91C_US_RTSEN ( ( unsigned int ) 0x1 << 18 ) /* (USART) Request to Send enable */ +#define AT91C_US_RTSDIS ( ( unsigned int ) 0x1 << 19 ) /* (USART) Request to Send Disable */ +/* -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- */ +#define AT91C_US_USMODE ( ( unsigned int ) 0xF << 0 ) /* (USART) Usart mode */ +#define AT91C_US_USMODE_NORMAL ( ( unsigned int ) 0x0 ) /* (USART) Normal */ +#define AT91C_US_USMODE_RS485 ( ( unsigned int ) 0x1 ) /* (USART) RS485 */ +#define AT91C_US_USMODE_HWHSH ( ( unsigned int ) 0x2 ) /* (USART) Hardware Handshaking */ +#define AT91C_US_USMODE_MODEM ( ( unsigned int ) 0x3 ) /* (USART) Modem */ +#define AT91C_US_USMODE_ISO7816_0 ( ( unsigned int ) 0x4 ) /* (USART) ISO7816 protocol: T = 0 */ +#define AT91C_US_USMODE_ISO7816_1 ( ( unsigned int ) 0x6 ) /* (USART) ISO7816 protocol: T = 1 */ +#define AT91C_US_USMODE_IRDA ( ( unsigned int ) 0x8 ) /* (USART) IrDA */ +#define AT91C_US_USMODE_SWHSH ( ( unsigned int ) 0xC ) /* (USART) Software Handshaking */ +#define AT91C_US_CLKS ( ( unsigned int ) 0x3 << 4 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */ +#define AT91C_US_CLKS_CLOCK ( ( unsigned int ) 0x0 << 4 ) /* (USART) Clock */ +#define AT91C_US_CLKS_FDIV1 ( ( unsigned int ) 0x1 << 4 ) /* (USART) fdiv1 */ +#define AT91C_US_CLKS_SLOW ( ( unsigned int ) 0x2 << 4 ) /* (USART) slow_clock (ARM) */ +#define AT91C_US_CLKS_EXT ( ( unsigned int ) 0x3 << 4 ) /* (USART) External (SCK) */ +#define AT91C_US_CHRL ( ( unsigned int ) 0x3 << 6 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */ +#define AT91C_US_CHRL_5_BITS ( ( unsigned int ) 0x0 << 6 ) /* (USART) Character Length: 5 bits */ +#define AT91C_US_CHRL_6_BITS ( ( unsigned int ) 0x1 << 6 ) /* (USART) Character Length: 6 bits */ +#define AT91C_US_CHRL_7_BITS ( ( unsigned int ) 0x2 << 6 ) /* (USART) Character Length: 7 bits */ +#define AT91C_US_CHRL_8_BITS ( ( unsigned int ) 0x3 << 6 ) /* (USART) Character Length: 8 bits */ +#define AT91C_US_SYNC ( ( unsigned int ) 0x1 << 8 ) /* (USART) Synchronous Mode Select */ +#define AT91C_US_NBSTOP ( ( unsigned int ) 0x3 << 12 ) /* (USART) Number of Stop bits */ +#define AT91C_US_NBSTOP_1_BIT ( ( unsigned int ) 0x0 << 12 ) /* (USART) 1 stop bit */ +#define AT91C_US_NBSTOP_15_BIT ( ( unsigned int ) 0x1 << 12 ) /* (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */ +#define AT91C_US_NBSTOP_2_BIT ( ( unsigned int ) 0x2 << 12 ) /* (USART) 2 stop bits */ +#define AT91C_US_MSBF ( ( unsigned int ) 0x1 << 16 ) /* (USART) Bit Order */ +#define AT91C_US_MODE9 ( ( unsigned int ) 0x1 << 17 ) /* (USART) 9-bit Character length */ +#define AT91C_US_CKLO ( ( unsigned int ) 0x1 << 18 ) /* (USART) Clock Output Select */ +#define AT91C_US_OVER ( ( unsigned int ) 0x1 << 19 ) /* (USART) Over Sampling Mode */ +#define AT91C_US_INACK ( ( unsigned int ) 0x1 << 20 ) /* (USART) Inhibit Non Acknowledge */ +#define AT91C_US_DSNACK ( ( unsigned int ) 0x1 << 21 ) /* (USART) Disable Successive NACK */ +#define AT91C_US_MAX_ITER ( ( unsigned int ) 0x1 << 24 ) /* (USART) Number of Repetitions */ +#define AT91C_US_FILTER ( ( unsigned int ) 0x1 << 28 ) /* (USART) Receive Line Filter */ +/* -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ +#define AT91C_US_RXBRK ( ( unsigned int ) 0x1 << 2 ) /* (USART) Break Received/End of Break */ +#define AT91C_US_TIMEOUT ( ( unsigned int ) 0x1 << 8 ) /* (USART) Receiver Time-out */ +#define AT91C_US_ITERATION ( ( unsigned int ) 0x1 << 10 ) /* (USART) Max number of Repetitions Reached */ +#define AT91C_US_NACK ( ( unsigned int ) 0x1 << 13 ) /* (USART) Non Acknowledge */ +#define AT91C_US_RIIC ( ( unsigned int ) 0x1 << 16 ) /* (USART) Ring INdicator Input Change Flag */ +#define AT91C_US_DSRIC ( ( unsigned int ) 0x1 << 17 ) /* (USART) Data Set Ready Input Change Flag */ +#define AT91C_US_DCDIC ( ( unsigned int ) 0x1 << 18 ) /* (USART) Data Carrier Flag */ +#define AT91C_US_CTSIC ( ( unsigned int ) 0x1 << 19 ) /* (USART) Clear To Send Input Change Flag */ +/* -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- */ +/* -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- */ +/* -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- */ +#define AT91C_US_RI ( ( unsigned int ) 0x1 << 20 ) /* (USART) Image of RI Input */ +#define AT91C_US_DSR ( ( unsigned int ) 0x1 << 21 ) /* (USART) Image of DSR Input */ +#define AT91C_US_DCD ( ( unsigned int ) 0x1 << 22 ) /* (USART) Image of DCD Input */ +#define AT91C_US_CTS ( ( unsigned int ) 0x1 << 23 ) /* (USART) Image of CTS Input */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Two-wire Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_TWI +{ + AT91_REG TWI_CR; /* Control Register */ + AT91_REG TWI_MMR; /* Master Mode Register */ + AT91_REG TWI_SMR; /* Slave Mode Register */ + AT91_REG TWI_IADR; /* Internal Address Register */ + AT91_REG TWI_CWGR; /* Clock Waveform Generator Register */ + AT91_REG Reserved0[ 3 ]; /* */ + AT91_REG TWI_SR; /* Status Register */ + AT91_REG TWI_IER; /* Interrupt Enable Register */ + AT91_REG TWI_IDR; /* Interrupt Disable Register */ + AT91_REG TWI_IMR; /* Interrupt Mask Register */ + AT91_REG TWI_RHR; /* Receive Holding Register */ + AT91_REG TWI_THR; /* Transmit Holding Register */ +} AT91S_TWI, * AT91PS_TWI; + +/* -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */ +#define AT91C_TWI_START ( ( unsigned int ) 0x1 << 0 ) /* (TWI) Send a START Condition */ +#define AT91C_TWI_STOP ( ( unsigned int ) 0x1 << 1 ) /* (TWI) Send a STOP Condition */ +#define AT91C_TWI_MSEN ( ( unsigned int ) 0x1 << 2 ) /* (TWI) TWI Master Transfer Enabled */ +#define AT91C_TWI_MSDIS ( ( unsigned int ) 0x1 << 3 ) /* (TWI) TWI Master Transfer Disabled */ +#define AT91C_TWI_SVEN ( ( unsigned int ) 0x1 << 4 ) /* (TWI) TWI Slave Transfer Enabled */ +#define AT91C_TWI_SVDIS ( ( unsigned int ) 0x1 << 5 ) /* (TWI) TWI Slave Transfer Disabled */ +#define AT91C_TWI_SWRST ( ( unsigned int ) 0x1 << 7 ) /* (TWI) Software Reset */ +/* -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */ +#define AT91C_TWI_IADRSZ ( ( unsigned int ) 0x3 << 8 ) /* (TWI) Internal Device Address Size */ +#define AT91C_TWI_IADRSZ_NO ( ( unsigned int ) 0x0 << 8 ) /* (TWI) No internal device address */ +#define AT91C_TWI_IADRSZ_1_BYTE ( ( unsigned int ) 0x1 << 8 ) /* (TWI) One-byte internal device address */ +#define AT91C_TWI_IADRSZ_2_BYTE ( ( unsigned int ) 0x2 << 8 ) /* (TWI) Two-byte internal device address */ +#define AT91C_TWI_IADRSZ_3_BYTE ( ( unsigned int ) 0x3 << 8 ) /* (TWI) Three-byte internal device address */ +#define AT91C_TWI_MREAD ( ( unsigned int ) 0x1 << 12 ) /* (TWI) Master Read Direction */ +#define AT91C_TWI_DADR ( ( unsigned int ) 0x7F << 16 ) /* (TWI) Device Address */ +/* -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- */ +#define AT91C_TWI_SADR ( ( unsigned int ) 0x7F << 16 ) /* (TWI) Slave Device Address */ +/* -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */ +#define AT91C_TWI_CLDIV ( ( unsigned int ) 0xFF << 0 ) /* (TWI) Clock Low Divider */ +#define AT91C_TWI_CHDIV ( ( unsigned int ) 0xFF << 8 ) /* (TWI) Clock High Divider */ +#define AT91C_TWI_CKDIV ( ( unsigned int ) 0x7 << 16 ) /* (TWI) Clock Divider */ +/* -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */ +#define AT91C_TWI_TXCOMP ( ( unsigned int ) 0x1 << 0 ) /* (TWI) Transmission Completed */ +#define AT91C_TWI_RXRDY ( ( unsigned int ) 0x1 << 1 ) /* (TWI) Receive holding register ReaDY */ +#define AT91C_TWI_TXRDY ( ( unsigned int ) 0x1 << 2 ) /* (TWI) Transmit holding register ReaDY */ +#define AT91C_TWI_SVREAD ( ( unsigned int ) 0x1 << 3 ) /* (TWI) Slave Read */ +#define AT91C_TWI_SVACC ( ( unsigned int ) 0x1 << 4 ) /* (TWI) Slave Access */ +#define AT91C_TWI_GCACC ( ( unsigned int ) 0x1 << 5 ) /* (TWI) General Call Access */ +#define AT91C_TWI_OVRE ( ( unsigned int ) 0x1 << 6 ) /* (TWI) Overrun Error */ +#define AT91C_TWI_UNRE ( ( unsigned int ) 0x1 << 7 ) /* (TWI) Underrun Error */ +#define AT91C_TWI_NACK ( ( unsigned int ) 0x1 << 8 ) /* (TWI) Not Acknowledged */ +#define AT91C_TWI_ARBLST ( ( unsigned int ) 0x1 << 9 ) /* (TWI) Arbitration Lost */ +/* -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */ +/* -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- */ +/* -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_TC +{ + AT91_REG TC_CCR; /* Channel Control Register */ + AT91_REG TC_CMR; /* Channel Mode Register (Capture Mode / Waveform Mode) */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG TC_CV; /* Counter Value */ + AT91_REG TC_RA; /* Register A */ + AT91_REG TC_RB; /* Register B */ + AT91_REG TC_RC; /* Register C */ + AT91_REG TC_SR; /* Status Register */ + AT91_REG TC_IER; /* Interrupt Enable Register */ + AT91_REG TC_IDR; /* Interrupt Disable Register */ + AT91_REG TC_IMR; /* Interrupt Mask Register */ +} AT91S_TC, * AT91PS_TC; + +/* -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- */ +#define AT91C_TC_CLKEN ( ( unsigned int ) 0x1 << 0 ) /* (TC) Counter Clock Enable Command */ +#define AT91C_TC_CLKDIS ( ( unsigned int ) 0x1 << 1 ) /* (TC) Counter Clock Disable Command */ +#define AT91C_TC_SWTRG ( ( unsigned int ) 0x1 << 2 ) /* (TC) Software Trigger Command */ +/* -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- */ +#define AT91C_TC_CLKS ( ( unsigned int ) 0x7 << 0 ) /* (TC) Clock Selection */ +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ( ( unsigned int ) 0x0 ) /* (TC) Clock selected: TIMER_DIV1_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ( ( unsigned int ) 0x1 ) /* (TC) Clock selected: TIMER_DIV2_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ( ( unsigned int ) 0x2 ) /* (TC) Clock selected: TIMER_DIV3_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ( ( unsigned int ) 0x3 ) /* (TC) Clock selected: TIMER_DIV4_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ( ( unsigned int ) 0x4 ) /* (TC) Clock selected: TIMER_DIV5_CLOCK */ +#define AT91C_TC_CLKS_XC0 ( ( unsigned int ) 0x5 ) /* (TC) Clock selected: XC0 */ +#define AT91C_TC_CLKS_XC1 ( ( unsigned int ) 0x6 ) /* (TC) Clock selected: XC1 */ +#define AT91C_TC_CLKS_XC2 ( ( unsigned int ) 0x7 ) /* (TC) Clock selected: XC2 */ +#define AT91C_TC_CLKI ( ( unsigned int ) 0x1 << 3 ) /* (TC) Clock Invert */ +#define AT91C_TC_BURST ( ( unsigned int ) 0x3 << 4 ) /* (TC) Burst Signal Selection */ +#define AT91C_TC_BURST_NONE ( ( unsigned int ) 0x0 << 4 ) /* (TC) The clock is not gated by an external signal */ +#define AT91C_TC_BURST_XC0 ( ( unsigned int ) 0x1 << 4 ) /* (TC) XC0 is ANDed with the selected clock */ +#define AT91C_TC_BURST_XC1 ( ( unsigned int ) 0x2 << 4 ) /* (TC) XC1 is ANDed with the selected clock */ +#define AT91C_TC_BURST_XC2 ( ( unsigned int ) 0x3 << 4 ) /* (TC) XC2 is ANDed with the selected clock */ +#define AT91C_TC_CPCSTOP ( ( unsigned int ) 0x1 << 6 ) /* (TC) Counter Clock Stopped with RC Compare */ +#define AT91C_TC_LDBSTOP ( ( unsigned int ) 0x1 << 6 ) /* (TC) Counter Clock Stopped with RB Loading */ +#define AT91C_TC_LDBDIS ( ( unsigned int ) 0x1 << 7 ) /* (TC) Counter Clock Disabled with RB Loading */ +#define AT91C_TC_CPCDIS ( ( unsigned int ) 0x1 << 7 ) /* (TC) Counter Clock Disable with RC Compare */ +#define AT91C_TC_ETRGEDG ( ( unsigned int ) 0x3 << 8 ) /* (TC) External Trigger Edge Selection */ +#define AT91C_TC_ETRGEDG_NONE ( ( unsigned int ) 0x0 << 8 ) /* (TC) Edge: None */ +#define AT91C_TC_ETRGEDG_RISING ( ( unsigned int ) 0x1 << 8 ) /* (TC) Edge: rising edge */ +#define AT91C_TC_ETRGEDG_FALLING ( ( unsigned int ) 0x2 << 8 ) /* (TC) Edge: falling edge */ +#define AT91C_TC_ETRGEDG_BOTH ( ( unsigned int ) 0x3 << 8 ) /* (TC) Edge: each edge */ +#define AT91C_TC_EEVTEDG ( ( unsigned int ) 0x3 << 8 ) /* (TC) External Event Edge Selection */ +#define AT91C_TC_EEVTEDG_NONE ( ( unsigned int ) 0x0 << 8 ) /* (TC) Edge: None */ +#define AT91C_TC_EEVTEDG_RISING ( ( unsigned int ) 0x1 << 8 ) /* (TC) Edge: rising edge */ +#define AT91C_TC_EEVTEDG_FALLING ( ( unsigned int ) 0x2 << 8 ) /* (TC) Edge: falling edge */ +#define AT91C_TC_EEVTEDG_BOTH ( ( unsigned int ) 0x3 << 8 ) /* (TC) Edge: each edge */ +#define AT91C_TC_ABETRG ( ( unsigned int ) 0x1 << 10 ) /* (TC) TIOA or TIOB External Trigger Selection */ +#define AT91C_TC_EEVT ( ( unsigned int ) 0x3 << 10 ) /* (TC) External Event Selection */ +#define AT91C_TC_EEVT_NONE ( ( unsigned int ) 0x0 << 10 ) /* (TC) Signal selected as external event: TIOB TIOB direction: input */ +#define AT91C_TC_EEVT_RISING ( ( unsigned int ) 0x1 << 10 ) /* (TC) Signal selected as external event: XC0 TIOB direction: output */ +#define AT91C_TC_EEVT_FALLING ( ( unsigned int ) 0x2 << 10 ) /* (TC) Signal selected as external event: XC1 TIOB direction: output */ +#define AT91C_TC_EEVT_BOTH ( ( unsigned int ) 0x3 << 10 ) /* (TC) Signal selected as external event: XC2 TIOB direction: output */ +#define AT91C_TC_ENETRG ( ( unsigned int ) 0x1 << 12 ) /* (TC) External Event Trigger enable */ +#define AT91C_TC_WAVESEL ( ( unsigned int ) 0x3 << 13 ) /* (TC) Waveform Selection */ +#define AT91C_TC_WAVESEL_UP ( ( unsigned int ) 0x0 << 13 ) /* (TC) UP mode without atomatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UPDOWN ( ( unsigned int ) 0x1 << 13 ) /* (TC) UPDOWN mode without automatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UP_AUTO ( ( unsigned int ) 0x2 << 13 ) /* (TC) UP mode with automatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UPDOWN_AUTO ( ( unsigned int ) 0x3 << 13 ) /* (TC) UPDOWN mode with automatic trigger on RC Compare */ +#define AT91C_TC_CPCTRG ( ( unsigned int ) 0x1 << 14 ) /* (TC) RC Compare Trigger Enable */ +#define AT91C_TC_WAVE ( ( unsigned int ) 0x1 << 15 ) /* (TC) */ +#define AT91C_TC_LDRA ( ( unsigned int ) 0x3 << 16 ) /* (TC) RA Loading Selection */ +#define AT91C_TC_LDRA_NONE ( ( unsigned int ) 0x0 << 16 ) /* (TC) Edge: None */ +#define AT91C_TC_LDRA_RISING ( ( unsigned int ) 0x1 << 16 ) /* (TC) Edge: rising edge of TIOA */ +#define AT91C_TC_LDRA_FALLING ( ( unsigned int ) 0x2 << 16 ) /* (TC) Edge: falling edge of TIOA */ +#define AT91C_TC_LDRA_BOTH ( ( unsigned int ) 0x3 << 16 ) /* (TC) Edge: each edge of TIOA */ +#define AT91C_TC_ACPA ( ( unsigned int ) 0x3 << 16 ) /* (TC) RA Compare Effect on TIOA */ +#define AT91C_TC_ACPA_NONE ( ( unsigned int ) 0x0 << 16 ) /* (TC) Effect: none */ +#define AT91C_TC_ACPA_SET ( ( unsigned int ) 0x1 << 16 ) /* (TC) Effect: set */ +#define AT91C_TC_ACPA_CLEAR ( ( unsigned int ) 0x2 << 16 ) /* (TC) Effect: clear */ +#define AT91C_TC_ACPA_TOGGLE ( ( unsigned int ) 0x3 << 16 ) /* (TC) Effect: toggle */ +#define AT91C_TC_LDRB ( ( unsigned int ) 0x3 << 18 ) /* (TC) RB Loading Selection */ +#define AT91C_TC_LDRB_NONE ( ( unsigned int ) 0x0 << 18 ) /* (TC) Edge: None */ +#define AT91C_TC_LDRB_RISING ( ( unsigned int ) 0x1 << 18 ) /* (TC) Edge: rising edge of TIOA */ +#define AT91C_TC_LDRB_FALLING ( ( unsigned int ) 0x2 << 18 ) /* (TC) Edge: falling edge of TIOA */ +#define AT91C_TC_LDRB_BOTH ( ( unsigned int ) 0x3 << 18 ) /* (TC) Edge: each edge of TIOA */ +#define AT91C_TC_ACPC ( ( unsigned int ) 0x3 << 18 ) /* (TC) RC Compare Effect on TIOA */ +#define AT91C_TC_ACPC_NONE ( ( unsigned int ) 0x0 << 18 ) /* (TC) Effect: none */ +#define AT91C_TC_ACPC_SET ( ( unsigned int ) 0x1 << 18 ) /* (TC) Effect: set */ +#define AT91C_TC_ACPC_CLEAR ( ( unsigned int ) 0x2 << 18 ) /* (TC) Effect: clear */ +#define AT91C_TC_ACPC_TOGGLE ( ( unsigned int ) 0x3 << 18 ) /* (TC) Effect: toggle */ +#define AT91C_TC_AEEVT ( ( unsigned int ) 0x3 << 20 ) /* (TC) External Event Effect on TIOA */ +#define AT91C_TC_AEEVT_NONE ( ( unsigned int ) 0x0 << 20 ) /* (TC) Effect: none */ +#define AT91C_TC_AEEVT_SET ( ( unsigned int ) 0x1 << 20 ) /* (TC) Effect: set */ +#define AT91C_TC_AEEVT_CLEAR ( ( unsigned int ) 0x2 << 20 ) /* (TC) Effect: clear */ +#define AT91C_TC_AEEVT_TOGGLE ( ( unsigned int ) 0x3 << 20 ) /* (TC) Effect: toggle */ +#define AT91C_TC_ASWTRG ( ( unsigned int ) 0x3 << 22 ) /* (TC) Software Trigger Effect on TIOA */ +#define AT91C_TC_ASWTRG_NONE ( ( unsigned int ) 0x0 << 22 ) /* (TC) Effect: none */ +#define AT91C_TC_ASWTRG_SET ( ( unsigned int ) 0x1 << 22 ) /* (TC) Effect: set */ +#define AT91C_TC_ASWTRG_CLEAR ( ( unsigned int ) 0x2 << 22 ) /* (TC) Effect: clear */ +#define AT91C_TC_ASWTRG_TOGGLE ( ( unsigned int ) 0x3 << 22 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BCPB ( ( unsigned int ) 0x3 << 24 ) /* (TC) RB Compare Effect on TIOB */ +#define AT91C_TC_BCPB_NONE ( ( unsigned int ) 0x0 << 24 ) /* (TC) Effect: none */ +#define AT91C_TC_BCPB_SET ( ( unsigned int ) 0x1 << 24 ) /* (TC) Effect: set */ +#define AT91C_TC_BCPB_CLEAR ( ( unsigned int ) 0x2 << 24 ) /* (TC) Effect: clear */ +#define AT91C_TC_BCPB_TOGGLE ( ( unsigned int ) 0x3 << 24 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BCPC ( ( unsigned int ) 0x3 << 26 ) /* (TC) RC Compare Effect on TIOB */ +#define AT91C_TC_BCPC_NONE ( ( unsigned int ) 0x0 << 26 ) /* (TC) Effect: none */ +#define AT91C_TC_BCPC_SET ( ( unsigned int ) 0x1 << 26 ) /* (TC) Effect: set */ +#define AT91C_TC_BCPC_CLEAR ( ( unsigned int ) 0x2 << 26 ) /* (TC) Effect: clear */ +#define AT91C_TC_BCPC_TOGGLE ( ( unsigned int ) 0x3 << 26 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BEEVT ( ( unsigned int ) 0x3 << 28 ) /* (TC) External Event Effect on TIOB */ +#define AT91C_TC_BEEVT_NONE ( ( unsigned int ) 0x0 << 28 ) /* (TC) Effect: none */ +#define AT91C_TC_BEEVT_SET ( ( unsigned int ) 0x1 << 28 ) /* (TC) Effect: set */ +#define AT91C_TC_BEEVT_CLEAR ( ( unsigned int ) 0x2 << 28 ) /* (TC) Effect: clear */ +#define AT91C_TC_BEEVT_TOGGLE ( ( unsigned int ) 0x3 << 28 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BSWTRG ( ( unsigned int ) 0x3 << 30 ) /* (TC) Software Trigger Effect on TIOB */ +#define AT91C_TC_BSWTRG_NONE ( ( unsigned int ) 0x0 << 30 ) /* (TC) Effect: none */ +#define AT91C_TC_BSWTRG_SET ( ( unsigned int ) 0x1 << 30 ) /* (TC) Effect: set */ +#define AT91C_TC_BSWTRG_CLEAR ( ( unsigned int ) 0x2 << 30 ) /* (TC) Effect: clear */ +#define AT91C_TC_BSWTRG_TOGGLE ( ( unsigned int ) 0x3 << 30 ) /* (TC) Effect: toggle */ +/* -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- */ +#define AT91C_TC_COVFS ( ( unsigned int ) 0x1 << 0 ) /* (TC) Counter Overflow */ +#define AT91C_TC_LOVRS ( ( unsigned int ) 0x1 << 1 ) /* (TC) Load Overrun */ +#define AT91C_TC_CPAS ( ( unsigned int ) 0x1 << 2 ) /* (TC) RA Compare */ +#define AT91C_TC_CPBS ( ( unsigned int ) 0x1 << 3 ) /* (TC) RB Compare */ +#define AT91C_TC_CPCS ( ( unsigned int ) 0x1 << 4 ) /* (TC) RC Compare */ +#define AT91C_TC_LDRAS ( ( unsigned int ) 0x1 << 5 ) /* (TC) RA Loading */ +#define AT91C_TC_LDRBS ( ( unsigned int ) 0x1 << 6 ) /* (TC) RB Loading */ +#define AT91C_TC_ETRCS ( ( unsigned int ) 0x1 << 7 ) /* (TC) External Trigger */ +#define AT91C_TC_ETRGS ( ( unsigned int ) 0x1 << 16 ) /* (TC) Clock Enabling */ +#define AT91C_TC_MTIOA ( ( unsigned int ) 0x1 << 17 ) /* (TC) TIOA Mirror */ +#define AT91C_TC_MTIOB ( ( unsigned int ) 0x1 << 18 ) /* (TC) TIOA Mirror */ +/* -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- */ +/* -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- */ +/* -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Timer Counter Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_TCB +{ + AT91S_TC TCB_TC0; /* TC Channel 0 */ + AT91_REG Reserved0[ 4 ]; /* */ + AT91S_TC TCB_TC1; /* TC Channel 1 */ + AT91_REG Reserved1[ 4 ]; /* */ + AT91S_TC TCB_TC2; /* TC Channel 2 */ + AT91_REG Reserved2[ 4 ]; /* */ + AT91_REG TCB_BCR; /* TC Block Control Register */ + AT91_REG TCB_BMR; /* TC Block Mode Register */ +} AT91S_TCB, * AT91PS_TCB; + +/* -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- */ +#define AT91C_TCB_SYNC ( ( unsigned int ) 0x1 << 0 ) /* (TCB) Synchro Command */ +/* -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- */ +#define AT91C_TCB_TC0XC0S ( ( unsigned int ) 0x1 << 0 ) /* (TCB) External Clock Signal 0 Selection */ +#define AT91C_TCB_TC0XC0S_TCLK0 ( ( unsigned int ) 0x0 ) /* (TCB) TCLK0 connected to XC0 */ +#define AT91C_TCB_TC0XC0S_NONE ( ( unsigned int ) 0x1 ) /* (TCB) None signal connected to XC0 */ +#define AT91C_TCB_TC0XC0S_TIOA1 ( ( unsigned int ) 0x2 ) /* (TCB) TIOA1 connected to XC0 */ +#define AT91C_TCB_TC0XC0S_TIOA2 ( ( unsigned int ) 0x3 ) /* (TCB) TIOA2 connected to XC0 */ +#define AT91C_TCB_TC1XC1S ( ( unsigned int ) 0x1 << 2 ) /* (TCB) External Clock Signal 1 Selection */ +#define AT91C_TCB_TC1XC1S_TCLK1 ( ( unsigned int ) 0x0 << 2 ) /* (TCB) TCLK1 connected to XC1 */ +#define AT91C_TCB_TC1XC1S_NONE ( ( unsigned int ) 0x1 << 2 ) /* (TCB) None signal connected to XC1 */ +#define AT91C_TCB_TC1XC1S_TIOA0 ( ( unsigned int ) 0x2 << 2 ) /* (TCB) TIOA0 connected to XC1 */ +#define AT91C_TCB_TC1XC1S_TIOA2 ( ( unsigned int ) 0x3 << 2 ) /* (TCB) TIOA2 connected to XC1 */ +#define AT91C_TCB_TC2XC2S ( ( unsigned int ) 0x1 << 4 ) /* (TCB) External Clock Signal 2 Selection */ +#define AT91C_TCB_TC2XC2S_TCLK2 ( ( unsigned int ) 0x0 << 4 ) /* (TCB) TCLK2 connected to XC2 */ +#define AT91C_TCB_TC2XC2S_NONE ( ( unsigned int ) 0x1 << 4 ) /* (TCB) None signal connected to XC2 */ +#define AT91C_TCB_TC2XC2S_TIOA0 ( ( unsigned int ) 0x2 << 4 ) /* (TCB) TIOA0 connected to XC2 */ +#define AT91C_TCB_TC2XC2S_TIOA2 ( ( unsigned int ) 0x3 << 4 ) /* (TCB) TIOA2 connected to XC2 */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR PWMC Channel Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_PWMC_CH +{ + AT91_REG PWMC_CMR; /* Channel Mode Register */ + AT91_REG PWMC_CDTYR; /* Channel Duty Cycle Register */ + AT91_REG PWMC_CPRDR; /* Channel Period Register */ + AT91_REG PWMC_CCNTR; /* Channel Counter Register */ + AT91_REG PWMC_CUPDR; /* Channel Update Register */ + AT91_REG PWMC_Reserved[ 3 ]; /* Reserved */ +} AT91S_PWMC_CH, * AT91PS_PWMC_CH; + +/* -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- */ +#define AT91C_PWMC_CPRE ( ( unsigned int ) 0xF << 0 ) /* (PWMC_CH) Channel Pre-scaler : PWMC_CLKx */ +#define AT91C_PWMC_CPRE_MCK ( ( unsigned int ) 0x0 ) /* (PWMC_CH) */ +#define AT91C_PWMC_CPRE_MCKA ( ( unsigned int ) 0xB ) /* (PWMC_CH) */ +#define AT91C_PWMC_CPRE_MCKB ( ( unsigned int ) 0xC ) /* (PWMC_CH) */ +#define AT91C_PWMC_CALG ( ( unsigned int ) 0x1 << 8 ) /* (PWMC_CH) Channel Alignment */ +#define AT91C_PWMC_CPOL ( ( unsigned int ) 0x1 << 9 ) /* (PWMC_CH) Channel Polarity */ +#define AT91C_PWMC_CPD ( ( unsigned int ) 0x1 << 10 ) /* (PWMC_CH) Channel Update Period */ +/* -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- */ +#define AT91C_PWMC_CDTY ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Duty Cycle */ +/* -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- */ +#define AT91C_PWMC_CPRD ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Period */ +/* -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- */ +#define AT91C_PWMC_CCNT ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Counter */ +/* -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- */ +#define AT91C_PWMC_CUPD ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Update */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_PWMC +{ + AT91_REG PWMC_MR; /* PWMC Mode Register */ + AT91_REG PWMC_ENA; /* PWMC Enable Register */ + AT91_REG PWMC_DIS; /* PWMC Disable Register */ + AT91_REG PWMC_SR; /* PWMC Status Register */ + AT91_REG PWMC_IER; /* PWMC Interrupt Enable Register */ + AT91_REG PWMC_IDR; /* PWMC Interrupt Disable Register */ + AT91_REG PWMC_IMR; /* PWMC Interrupt Mask Register */ + AT91_REG PWMC_ISR; /* PWMC Interrupt Status Register */ + AT91_REG Reserved0[ 55 ]; /* */ + AT91_REG PWMC_VR; /* PWMC Version Register */ + AT91_REG Reserved1[ 64 ]; /* */ + AT91S_PWMC_CH PWMC_CH[ 32 ]; /* PWMC Channel 0 */ +} AT91S_PWMC, * AT91PS_PWMC; + +/* -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- */ +#define AT91C_PWMC_DIVA ( ( unsigned int ) 0xFF << 0 ) /* (PWMC) CLKA divide factor. */ +#define AT91C_PWMC_PREA ( ( unsigned int ) 0xF << 8 ) /* (PWMC) Divider Input Clock Prescaler A */ +#define AT91C_PWMC_PREA_MCK ( ( unsigned int ) 0x0 << 8 ) /* (PWMC) */ +#define AT91C_PWMC_DIVB ( ( unsigned int ) 0xFF << 16 ) /* (PWMC) CLKB divide factor. */ +#define AT91C_PWMC_PREB ( ( unsigned int ) 0xF << 24 ) /* (PWMC) Divider Input Clock Prescaler B */ +#define AT91C_PWMC_PREB_MCK ( ( unsigned int ) 0x0 << 24 ) /* (PWMC) */ +/* -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- */ +#define AT91C_PWMC_CHID0 ( ( unsigned int ) 0x1 << 0 ) /* (PWMC) Channel ID 0 */ +#define AT91C_PWMC_CHID1 ( ( unsigned int ) 0x1 << 1 ) /* (PWMC) Channel ID 1 */ +#define AT91C_PWMC_CHID2 ( ( unsigned int ) 0x1 << 2 ) /* (PWMC) Channel ID 2 */ +#define AT91C_PWMC_CHID3 ( ( unsigned int ) 0x1 << 3 ) /* (PWMC) Channel ID 3 */ +#define AT91C_PWMC_CHID4 ( ( unsigned int ) 0x1 << 4 ) /* (PWMC) Channel ID 4 */ +#define AT91C_PWMC_CHID5 ( ( unsigned int ) 0x1 << 5 ) /* (PWMC) Channel ID 5 */ +#define AT91C_PWMC_CHID6 ( ( unsigned int ) 0x1 << 6 ) /* (PWMC) Channel ID 6 */ +#define AT91C_PWMC_CHID7 ( ( unsigned int ) 0x1 << 7 ) /* (PWMC) Channel ID 7 */ +/* -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- */ +/* -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- */ +/* -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- */ +/* -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- */ +/* -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- */ +/* -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR USB Device Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_UDP +{ + AT91_REG UDP_NUM; /* Frame Number Register */ + AT91_REG UDP_GLBSTATE; /* Global State Register */ + AT91_REG UDP_FADDR; /* Function Address Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG UDP_IER; /* Interrupt Enable Register */ + AT91_REG UDP_IDR; /* Interrupt Disable Register */ + AT91_REG UDP_IMR; /* Interrupt Mask Register */ + AT91_REG UDP_ISR; /* Interrupt Status Register */ + AT91_REG UDP_ICR; /* Interrupt Clear Register */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG UDP_RSTEP; /* Reset Endpoint Register */ + AT91_REG Reserved2[ 1 ]; /* */ + AT91_REG UDP_CSR[ 8 ]; /* Endpoint Control and Status Register */ + AT91_REG UDP_FDR[ 8 ]; /* Endpoint FIFO Data Register */ +} AT91S_UDP, * AT91PS_UDP; + +/* -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- */ +#define AT91C_UDP_FRM_NUM ( ( unsigned int ) 0x7FF << 0 ) /* (UDP) Frame Number as Defined in the Packet Field Formats */ +#define AT91C_UDP_FRM_ERR ( ( unsigned int ) 0x1 << 16 ) /* (UDP) Frame Error */ +#define AT91C_UDP_FRM_OK ( ( unsigned int ) 0x1 << 17 ) /* (UDP) Frame OK */ +/* -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- */ +#define AT91C_UDP_FADDEN ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Function Address Enable */ +#define AT91C_UDP_CONFG ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Configured */ +#define AT91C_UDP_RMWUPE ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Remote Wake Up Enable */ +#define AT91C_UDP_RSMINPR ( ( unsigned int ) 0x1 << 3 ) /* (UDP) A Resume Has Been Sent to the Host */ +/* -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- */ +#define AT91C_UDP_FADD ( ( unsigned int ) 0xFF << 0 ) /* (UDP) Function Address Value */ +#define AT91C_UDP_FEN ( ( unsigned int ) 0x1 << 8 ) /* (UDP) Function Enable */ +/* -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- */ +#define AT91C_UDP_EPINT0 ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Endpoint 0 Interrupt */ +#define AT91C_UDP_EPINT1 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Endpoint 0 Interrupt */ +#define AT91C_UDP_EPINT2 ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Endpoint 2 Interrupt */ +#define AT91C_UDP_EPINT3 ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Endpoint 3 Interrupt */ +#define AT91C_UDP_EPINT4 ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Endpoint 4 Interrupt */ +#define AT91C_UDP_EPINT5 ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Endpoint 5 Interrupt */ +#define AT91C_UDP_EPINT6 ( ( unsigned int ) 0x1 << 6 ) /* (UDP) Endpoint 6 Interrupt */ +#define AT91C_UDP_EPINT7 ( ( unsigned int ) 0x1 << 7 ) /* (UDP) Endpoint 7 Interrupt */ +#define AT91C_UDP_RXSUSP ( ( unsigned int ) 0x1 << 8 ) /* (UDP) USB Suspend Interrupt */ +#define AT91C_UDP_RXRSM ( ( unsigned int ) 0x1 << 9 ) /* (UDP) USB Resume Interrupt */ +#define AT91C_UDP_EXTRSM ( ( unsigned int ) 0x1 << 10 ) /* (UDP) USB External Resume Interrupt */ +#define AT91C_UDP_SOFINT ( ( unsigned int ) 0x1 << 11 ) /* (UDP) USB Start Of frame Interrupt */ +#define AT91C_UDP_WAKEUP ( ( unsigned int ) 0x1 << 13 ) /* (UDP) USB Resume Interrupt */ +/* -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- */ +/* -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- */ +/* -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- */ +#define AT91C_UDP_ENDBUSRES ( ( unsigned int ) 0x1 << 12 ) /* (UDP) USB End Of Bus Reset Interrupt */ +/* -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- */ +/* -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- */ +#define AT91C_UDP_EP0 ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Reset Endpoint 0 */ +#define AT91C_UDP_EP1 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Reset Endpoint 1 */ +#define AT91C_UDP_EP2 ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Reset Endpoint 2 */ +#define AT91C_UDP_EP3 ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Reset Endpoint 3 */ +#define AT91C_UDP_EP4 ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Reset Endpoint 4 */ +#define AT91C_UDP_EP5 ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Reset Endpoint 5 */ +#define AT91C_UDP_EP6 ( ( unsigned int ) 0x1 << 6 ) /* (UDP) Reset Endpoint 6 */ +#define AT91C_UDP_EP7 ( ( unsigned int ) 0x1 << 7 ) /* (UDP) Reset Endpoint 7 */ +/* -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- */ +#define AT91C_UDP_TXCOMP ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Generates an IN packet with data previously written in the DPR */ +#define AT91C_UDP_RX_DATA_BK0 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Receive Data Bank 0 */ +#define AT91C_UDP_RXSETUP ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Sends STALL to the Host (Control endpoints) */ +#define AT91C_UDP_ISOERROR ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Isochronous error (Isochronous endpoints) */ +#define AT91C_UDP_TXPKTRDY ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Transmit Packet Ready */ +#define AT91C_UDP_FORCESTALL ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). */ +#define AT91C_UDP_RX_DATA_BK1 ( ( unsigned int ) 0x1 << 6 ) /* (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). */ +#define AT91C_UDP_DIR ( ( unsigned int ) 0x1 << 7 ) /* (UDP) Transfer Direction */ +#define AT91C_UDP_EPTYPE ( ( unsigned int ) 0x7 << 8 ) /* (UDP) Endpoint type */ +#define AT91C_UDP_EPTYPE_CTRL ( ( unsigned int ) 0x0 << 8 ) /* (UDP) Control */ +#define AT91C_UDP_EPTYPE_ISO_OUT ( ( unsigned int ) 0x1 << 8 ) /* (UDP) Isochronous OUT */ +#define AT91C_UDP_EPTYPE_BULK_OUT ( ( unsigned int ) 0x2 << 8 ) /* (UDP) Bulk OUT */ +#define AT91C_UDP_EPTYPE_INT_OUT ( ( unsigned int ) 0x3 << 8 ) /* (UDP) Interrupt OUT */ +#define AT91C_UDP_EPTYPE_ISO_IN ( ( unsigned int ) 0x5 << 8 ) /* (UDP) Isochronous IN */ +#define AT91C_UDP_EPTYPE_BULK_IN ( ( unsigned int ) 0x6 << 8 ) /* (UDP) Bulk IN */ +#define AT91C_UDP_EPTYPE_INT_IN ( ( unsigned int ) 0x7 << 8 ) /* (UDP) Interrupt IN */ +#define AT91C_UDP_DTGLE ( ( unsigned int ) 0x1 << 11 ) /* (UDP) Data Toggle */ +#define AT91C_UDP_EPEDS ( ( unsigned int ) 0x1 << 15 ) /* (UDP) Endpoint Enable Disable */ +#define AT91C_UDP_RXBYTECNT ( ( unsigned int ) 0x7FF << 16 ) /* (UDP) Number Of Bytes Available in the FIFO */ + +/* ***************************************************************************** */ +/* REGISTER ADDRESS DEFINITION FOR AT91SAM7S64 */ +/* ***************************************************************************** */ +/* ========== Register definition for SYSC peripheral ========== */ +#define AT91C_SYSC_SYSC_VRPM ( ( AT91_REG * ) 0xFFFFFD60 ) /* (SYSC) Voltage Regulator Power Mode Register */ +/* ========== Register definition for AIC peripheral ========== */ +#define AT91C_AIC_ICCR ( ( AT91_REG * ) 0xFFFFF128 ) /* (AIC) Interrupt Clear Command Register */ +#define AT91C_AIC_IECR ( ( AT91_REG * ) 0xFFFFF120 ) /* (AIC) Interrupt Enable Command Register */ +#define AT91C_AIC_SMR ( ( AT91_REG * ) 0xFFFFF000 ) /* (AIC) Source Mode Register */ +#define AT91C_AIC_ISCR ( ( AT91_REG * ) 0xFFFFF12C ) /* (AIC) Interrupt Set Command Register */ +#define AT91C_AIC_EOICR ( ( AT91_REG * ) 0xFFFFF130 ) /* (AIC) End of Interrupt Command Register */ +#define AT91C_AIC_DCR ( ( AT91_REG * ) 0xFFFFF138 ) /* (AIC) Debug Control Register (Protect) */ +#define AT91C_AIC_FFER ( ( AT91_REG * ) 0xFFFFF140 ) /* (AIC) Fast Forcing Enable Register */ +#define AT91C_AIC_SVR ( ( AT91_REG * ) 0xFFFFF080 ) /* (AIC) Source Vector Register */ +#define AT91C_AIC_SPU ( ( AT91_REG * ) 0xFFFFF134 ) /* (AIC) Spurious Vector Register */ +#define AT91C_AIC_FFDR ( ( AT91_REG * ) 0xFFFFF144 ) /* (AIC) Fast Forcing Disable Register */ +#define AT91C_AIC_FVR ( ( AT91_REG * ) 0xFFFFF104 ) /* (AIC) FIQ Vector Register */ +#define AT91C_AIC_FFSR ( ( AT91_REG * ) 0xFFFFF148 ) /* (AIC) Fast Forcing Status Register */ +#define AT91C_AIC_IMR ( ( AT91_REG * ) 0xFFFFF110 ) /* (AIC) Interrupt Mask Register */ +#define AT91C_AIC_ISR ( ( AT91_REG * ) 0xFFFFF108 ) /* (AIC) Interrupt Status Register */ +#define AT91C_AIC_IVR ( ( AT91_REG * ) 0xFFFFF100 ) /* (AIC) IRQ Vector Register */ +#define AT91C_AIC_IDCR ( ( AT91_REG * ) 0xFFFFF124 ) /* (AIC) Interrupt Disable Command Register */ +#define AT91C_AIC_CISR ( ( AT91_REG * ) 0xFFFFF114 ) /* (AIC) Core Interrupt Status Register */ +#define AT91C_AIC_IPR ( ( AT91_REG * ) 0xFFFFF10C ) /* (AIC) Interrupt Pending Register */ +/* ========== Register definition for DBGU peripheral ========== */ +#define AT91C_DBGU_C2R ( ( AT91_REG * ) 0xFFFFF244 ) /* (DBGU) Chip ID2 Register */ +#define AT91C_DBGU_THR ( ( AT91_REG * ) 0xFFFFF21C ) /* (DBGU) Transmitter Holding Register */ +#define AT91C_DBGU_CSR ( ( AT91_REG * ) 0xFFFFF214 ) /* (DBGU) Channel Status Register */ +#define AT91C_DBGU_IDR ( ( AT91_REG * ) 0xFFFFF20C ) /* (DBGU) Interrupt Disable Register */ +#define AT91C_DBGU_MR ( ( AT91_REG * ) 0xFFFFF204 ) /* (DBGU) Mode Register */ +#define AT91C_DBGU_FNTR ( ( AT91_REG * ) 0xFFFFF248 ) /* (DBGU) Force NTRST Register */ +#define AT91C_DBGU_C1R ( ( AT91_REG * ) 0xFFFFF240 ) /* (DBGU) Chip ID1 Register */ +#define AT91C_DBGU_BRGR ( ( AT91_REG * ) 0xFFFFF220 ) /* (DBGU) Baud Rate Generator Register */ +#define AT91C_DBGU_RHR ( ( AT91_REG * ) 0xFFFFF218 ) /* (DBGU) Receiver Holding Register */ +#define AT91C_DBGU_IMR ( ( AT91_REG * ) 0xFFFFF210 ) /* (DBGU) Interrupt Mask Register */ +#define AT91C_DBGU_IER ( ( AT91_REG * ) 0xFFFFF208 ) /* (DBGU) Interrupt Enable Register */ +#define AT91C_DBGU_CR ( ( AT91_REG * ) 0xFFFFF200 ) /* (DBGU) Control Register */ +/* ========== Register definition for PDC_DBGU peripheral ========== */ +#define AT91C_DBGU_TNCR ( ( AT91_REG * ) 0xFFFFF31C ) /* (PDC_DBGU) Transmit Next Counter Register */ +#define AT91C_DBGU_RNCR ( ( AT91_REG * ) 0xFFFFF314 ) /* (PDC_DBGU) Receive Next Counter Register */ +#define AT91C_DBGU_PTCR ( ( AT91_REG * ) 0xFFFFF320 ) /* (PDC_DBGU) PDC Transfer Control Register */ +#define AT91C_DBGU_PTSR ( ( AT91_REG * ) 0xFFFFF324 ) /* (PDC_DBGU) PDC Transfer Status Register */ +#define AT91C_DBGU_RCR ( ( AT91_REG * ) 0xFFFFF304 ) /* (PDC_DBGU) Receive Counter Register */ +#define AT91C_DBGU_TCR ( ( AT91_REG * ) 0xFFFFF30C ) /* (PDC_DBGU) Transmit Counter Register */ +#define AT91C_DBGU_RPR ( ( AT91_REG * ) 0xFFFFF300 ) /* (PDC_DBGU) Receive Pointer Register */ +#define AT91C_DBGU_TPR ( ( AT91_REG * ) 0xFFFFF308 ) /* (PDC_DBGU) Transmit Pointer Register */ +#define AT91C_DBGU_RNPR ( ( AT91_REG * ) 0xFFFFF310 ) /* (PDC_DBGU) Receive Next Pointer Register */ +#define AT91C_DBGU_TNPR ( ( AT91_REG * ) 0xFFFFF318 ) /* (PDC_DBGU) Transmit Next Pointer Register */ +/* ========== Register definition for PIOA peripheral ========== */ +#define AT91C_PIOA_IMR ( ( AT91_REG * ) 0xFFFFF448 ) /* (PIOA) Interrupt Mask Register */ +#define AT91C_PIOA_IER ( ( AT91_REG * ) 0xFFFFF440 ) /* (PIOA) Interrupt Enable Register */ +#define AT91C_PIOA_OWDR ( ( AT91_REG * ) 0xFFFFF4A4 ) /* (PIOA) Output Write Disable Register */ +#define AT91C_PIOA_ISR ( ( AT91_REG * ) 0xFFFFF44C ) /* (PIOA) Interrupt Status Register */ +#define AT91C_PIOA_PPUDR ( ( AT91_REG * ) 0xFFFFF460 ) /* (PIOA) Pull-up Disable Register */ +#define AT91C_PIOA_MDSR ( ( AT91_REG * ) 0xFFFFF458 ) /* (PIOA) Multi-driver Status Register */ +#define AT91C_PIOA_MDER ( ( AT91_REG * ) 0xFFFFF450 ) /* (PIOA) Multi-driver Enable Register */ +#define AT91C_PIOA_PER ( ( AT91_REG * ) 0xFFFFF400 ) /* (PIOA) PIO Enable Register */ +#define AT91C_PIOA_PSR ( ( AT91_REG * ) 0xFFFFF408 ) /* (PIOA) PIO Status Register */ +#define AT91C_PIOA_OER ( ( AT91_REG * ) 0xFFFFF410 ) /* (PIOA) Output Enable Register */ +#define AT91C_PIOA_BSR ( ( AT91_REG * ) 0xFFFFF474 ) /* (PIOA) Select B Register */ +#define AT91C_PIOA_PPUER ( ( AT91_REG * ) 0xFFFFF464 ) /* (PIOA) Pull-up Enable Register */ +#define AT91C_PIOA_MDDR ( ( AT91_REG * ) 0xFFFFF454 ) /* (PIOA) Multi-driver Disable Register */ +#define AT91C_PIOA_PDR ( ( AT91_REG * ) 0xFFFFF404 ) /* (PIOA) PIO Disable Register */ +#define AT91C_PIOA_ODR ( ( AT91_REG * ) 0xFFFFF414 ) /* (PIOA) Output Disable Registerr */ +#define AT91C_PIOA_IFDR ( ( AT91_REG * ) 0xFFFFF424 ) /* (PIOA) Input Filter Disable Register */ +#define AT91C_PIOA_ABSR ( ( AT91_REG * ) 0xFFFFF478 ) /* (PIOA) AB Select Status Register */ +#define AT91C_PIOA_ASR ( ( AT91_REG * ) 0xFFFFF470 ) /* (PIOA) Select A Register */ +#define AT91C_PIOA_PPUSR ( ( AT91_REG * ) 0xFFFFF468 ) /* (PIOA) Pad Pull-up Status Register */ +#define AT91C_PIOA_ODSR ( ( AT91_REG * ) 0xFFFFF438 ) /* (PIOA) Output Data Status Register */ +#define AT91C_PIOA_SODR ( ( AT91_REG * ) 0xFFFFF430 ) /* (PIOA) Set Output Data Register */ +#define AT91C_PIOA_IFSR ( ( AT91_REG * ) 0xFFFFF428 ) /* (PIOA) Input Filter Status Register */ +#define AT91C_PIOA_IFER ( ( AT91_REG * ) 0xFFFFF420 ) /* (PIOA) Input Filter Enable Register */ +#define AT91C_PIOA_OSR ( ( AT91_REG * ) 0xFFFFF418 ) /* (PIOA) Output Status Register */ +#define AT91C_PIOA_IDR ( ( AT91_REG * ) 0xFFFFF444 ) /* (PIOA) Interrupt Disable Register */ +#define AT91C_PIOA_PDSR ( ( AT91_REG * ) 0xFFFFF43C ) /* (PIOA) Pin Data Status Register */ +#define AT91C_PIOA_CODR ( ( AT91_REG * ) 0xFFFFF434 ) /* (PIOA) Clear Output Data Register */ +#define AT91C_PIOA_OWSR ( ( AT91_REG * ) 0xFFFFF4A8 ) /* (PIOA) Output Write Status Register */ +#define AT91C_PIOA_OWER ( ( AT91_REG * ) 0xFFFFF4A0 ) /* (PIOA) Output Write Enable Register */ +/* ========== Register definition for CKGR peripheral ========== */ +#define AT91C_CKGR_PLLR ( ( AT91_REG * ) 0xFFFFFC2C ) /* (CKGR) PLL Register */ +#define AT91C_CKGR_MCFR ( ( AT91_REG * ) 0xFFFFFC24 ) /* (CKGR) Main Clock Frequency Register */ +#define AT91C_CKGR_MOR ( ( AT91_REG * ) 0xFFFFFC20 ) /* (CKGR) Main Oscillator Register */ +/* ========== Register definition for PMC peripheral ========== */ +#define AT91C_PMC_SCSR ( ( AT91_REG * ) 0xFFFFFC08 ) /* (PMC) System Clock Status Register */ +#define AT91C_PMC_SCER ( ( AT91_REG * ) 0xFFFFFC00 ) /* (PMC) System Clock Enable Register */ +#define AT91C_PMC_IMR ( ( AT91_REG * ) 0xFFFFFC6C ) /* (PMC) Interrupt Mask Register */ +#define AT91C_PMC_IDR ( ( AT91_REG * ) 0xFFFFFC64 ) /* (PMC) Interrupt Disable Register */ +#define AT91C_PMC_PCDR ( ( AT91_REG * ) 0xFFFFFC14 ) /* (PMC) Peripheral Clock Disable Register */ +#define AT91C_PMC_SCDR ( ( AT91_REG * ) 0xFFFFFC04 ) /* (PMC) System Clock Disable Register */ +#define AT91C_PMC_SR ( ( AT91_REG * ) 0xFFFFFC68 ) /* (PMC) Status Register */ +#define AT91C_PMC_IER ( ( AT91_REG * ) 0xFFFFFC60 ) /* (PMC) Interrupt Enable Register */ +#define AT91C_PMC_MCKR ( ( AT91_REG * ) 0xFFFFFC30 ) /* (PMC) Master Clock Register */ +#define AT91C_PMC_MOR ( ( AT91_REG * ) 0xFFFFFC20 ) /* (PMC) Main Oscillator Register */ +#define AT91C_PMC_PCER ( ( AT91_REG * ) 0xFFFFFC10 ) /* (PMC) Peripheral Clock Enable Register */ +#define AT91C_PMC_PCSR ( ( AT91_REG * ) 0xFFFFFC18 ) /* (PMC) Peripheral Clock Status Register */ +#define AT91C_PMC_PLLR ( ( AT91_REG * ) 0xFFFFFC2C ) /* (PMC) PLL Register */ +#define AT91C_PMC_MCFR ( ( AT91_REG * ) 0xFFFFFC24 ) /* (PMC) Main Clock Frequency Register */ +#define AT91C_PMC_PCKR ( ( AT91_REG * ) 0xFFFFFC40 ) /* (PMC) Programmable Clock Register */ +/* ========== Register definition for RSTC peripheral ========== */ +#define AT91C_RSTC_RSR ( ( AT91_REG * ) 0xFFFFFD04 ) /* (RSTC) Reset Status Register */ +#define AT91C_RSTC_RMR ( ( AT91_REG * ) 0xFFFFFD08 ) /* (RSTC) Reset Mode Register */ +#define AT91C_RSTC_RCR ( ( AT91_REG * ) 0xFFFFFD00 ) /* (RSTC) Reset Control Register */ +/* ========== Register definition for RTTC peripheral ========== */ +#define AT91C_RTTC_RTSR ( ( AT91_REG * ) 0xFFFFFD2C ) /* (RTTC) Real-time Status Register */ +#define AT91C_RTTC_RTAR ( ( AT91_REG * ) 0xFFFFFD24 ) /* (RTTC) Real-time Alarm Register */ +#define AT91C_RTTC_RTVR ( ( AT91_REG * ) 0xFFFFFD28 ) /* (RTTC) Real-time Value Register */ +#define AT91C_RTTC_RTMR ( ( AT91_REG * ) 0xFFFFFD20 ) /* (RTTC) Real-time Mode Register */ +/* ========== Register definition for PITC peripheral ========== */ +#define AT91C_PITC_PIIR ( ( AT91_REG * ) 0xFFFFFD3C ) /* (PITC) Period Interval Image Register */ +#define AT91C_PITC_PISR ( ( AT91_REG * ) 0xFFFFFD34 ) /* (PITC) Period Interval Status Register */ +#define AT91C_PITC_PIVR ( ( AT91_REG * ) 0xFFFFFD38 ) /* (PITC) Period Interval Value Register */ +#define AT91C_PITC_PIMR ( ( AT91_REG * ) 0xFFFFFD30 ) /* (PITC) Period Interval Mode Register */ +/* ========== Register definition for WDTC peripheral ========== */ +#define AT91C_WDTC_WDMR ( ( AT91_REG * ) 0xFFFFFD44 ) /* (WDTC) Watchdog Mode Register */ +#define AT91C_WDTC_WDSR ( ( AT91_REG * ) 0xFFFFFD48 ) /* (WDTC) Watchdog Status Register */ +#define AT91C_WDTC_WDCR ( ( AT91_REG * ) 0xFFFFFD40 ) /* (WDTC) Watchdog Control Register */ +/* ========== Register definition for MC peripheral ========== */ +#define AT91C_MC_FCR ( ( AT91_REG * ) 0xFFFFFF64 ) /* (MC) MC Flash Command Register */ +#define AT91C_MC_ASR ( ( AT91_REG * ) 0xFFFFFF04 ) /* (MC) MC Abort Status Register */ +#define AT91C_MC_FSR ( ( AT91_REG * ) 0xFFFFFF68 ) /* (MC) MC Flash Status Register */ +#define AT91C_MC_FMR ( ( AT91_REG * ) 0xFFFFFF60 ) /* (MC) MC Flash Mode Register */ +#define AT91C_MC_AASR ( ( AT91_REG * ) 0xFFFFFF08 ) /* (MC) MC Abort Address Status Register */ +#define AT91C_MC_RCR ( ( AT91_REG * ) 0xFFFFFF00 ) /* (MC) MC Remap Control Register */ +/* ========== Register definition for PDC_SPI peripheral ========== */ +#define AT91C_SPI_PTCR ( ( AT91_REG * ) 0xFFFE0120 ) /* (PDC_SPI) PDC Transfer Control Register */ +#define AT91C_SPI_TNPR ( ( AT91_REG * ) 0xFFFE0118 ) /* (PDC_SPI) Transmit Next Pointer Register */ +#define AT91C_SPI_RNPR ( ( AT91_REG * ) 0xFFFE0110 ) /* (PDC_SPI) Receive Next Pointer Register */ +#define AT91C_SPI_TPR ( ( AT91_REG * ) 0xFFFE0108 ) /* (PDC_SPI) Transmit Pointer Register */ +#define AT91C_SPI_RPR ( ( AT91_REG * ) 0xFFFE0100 ) /* (PDC_SPI) Receive Pointer Register */ +#define AT91C_SPI_PTSR ( ( AT91_REG * ) 0xFFFE0124 ) /* (PDC_SPI) PDC Transfer Status Register */ +#define AT91C_SPI_TNCR ( ( AT91_REG * ) 0xFFFE011C ) /* (PDC_SPI) Transmit Next Counter Register */ +#define AT91C_SPI_RNCR ( ( AT91_REG * ) 0xFFFE0114 ) /* (PDC_SPI) Receive Next Counter Register */ +#define AT91C_SPI_TCR ( ( AT91_REG * ) 0xFFFE010C ) /* (PDC_SPI) Transmit Counter Register */ +#define AT91C_SPI_RCR ( ( AT91_REG * ) 0xFFFE0104 ) /* (PDC_SPI) Receive Counter Register */ +/* ========== Register definition for SPI peripheral ========== */ +#define AT91C_SPI_CSR ( ( AT91_REG * ) 0xFFFE0030 ) /* (SPI) Chip Select Register */ +#define AT91C_SPI_IDR ( ( AT91_REG * ) 0xFFFE0018 ) /* (SPI) Interrupt Disable Register */ +#define AT91C_SPI_SR ( ( AT91_REG * ) 0xFFFE0010 ) /* (SPI) Status Register */ +#define AT91C_SPI_RDR ( ( AT91_REG * ) 0xFFFE0008 ) /* (SPI) Receive Data Register */ +#define AT91C_SPI_CR ( ( AT91_REG * ) 0xFFFE0000 ) /* (SPI) Control Register */ +#define AT91C_SPI_IMR ( ( AT91_REG * ) 0xFFFE001C ) /* (SPI) Interrupt Mask Register */ +#define AT91C_SPI_IER ( ( AT91_REG * ) 0xFFFE0014 ) /* (SPI) Interrupt Enable Register */ +#define AT91C_SPI_TDR ( ( AT91_REG * ) 0xFFFE000C ) /* (SPI) Transmit Data Register */ +#define AT91C_SPI_MR ( ( AT91_REG * ) 0xFFFE0004 ) /* (SPI) Mode Register */ +/* ========== Register definition for PDC_ADC peripheral ========== */ +#define AT91C_ADC_PTCR ( ( AT91_REG * ) 0xFFFD8120 ) /* (PDC_ADC) PDC Transfer Control Register */ +#define AT91C_ADC_TNPR ( ( AT91_REG * ) 0xFFFD8118 ) /* (PDC_ADC) Transmit Next Pointer Register */ +#define AT91C_ADC_RNPR ( ( AT91_REG * ) 0xFFFD8110 ) /* (PDC_ADC) Receive Next Pointer Register */ +#define AT91C_ADC_TPR ( ( AT91_REG * ) 0xFFFD8108 ) /* (PDC_ADC) Transmit Pointer Register */ +#define AT91C_ADC_RPR ( ( AT91_REG * ) 0xFFFD8100 ) /* (PDC_ADC) Receive Pointer Register */ +#define AT91C_ADC_PTSR ( ( AT91_REG * ) 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */ +#define AT91C_ADC_TNCR ( ( AT91_REG * ) 0xFFFD811C ) /* (PDC_ADC) Transmit Next Counter Register */ +#define AT91C_ADC_RNCR ( ( AT91_REG * ) 0xFFFD8114 ) /* (PDC_ADC) Receive Next Counter Register */ +#define AT91C_ADC_TCR ( ( AT91_REG * ) 0xFFFD810C ) /* (PDC_ADC) Transmit Counter Register */ +#define AT91C_ADC_RCR ( ( AT91_REG * ) 0xFFFD8104 ) /* (PDC_ADC) Receive Counter Register */ +/* ========== Register definition for ADC peripheral ========== */ +#define AT91C_ADC_IMR ( ( AT91_REG * ) 0xFFFD802C ) /* (ADC) ADC Interrupt Mask Register */ +#define AT91C_ADC_CDR4 ( ( AT91_REG * ) 0xFFFD8040 ) /* (ADC) ADC Channel Data Register 4 */ +#define AT91C_ADC_CDR2 ( ( AT91_REG * ) 0xFFFD8038 ) /* (ADC) ADC Channel Data Register 2 */ +#define AT91C_ADC_CDR0 ( ( AT91_REG * ) 0xFFFD8030 ) /* (ADC) ADC Channel Data Register 0 */ +#define AT91C_ADC_CDR7 ( ( AT91_REG * ) 0xFFFD804C ) /* (ADC) ADC Channel Data Register 7 */ +#define AT91C_ADC_CDR1 ( ( AT91_REG * ) 0xFFFD8034 ) /* (ADC) ADC Channel Data Register 1 */ +#define AT91C_ADC_CDR3 ( ( AT91_REG * ) 0xFFFD803C ) /* (ADC) ADC Channel Data Register 3 */ +#define AT91C_ADC_CDR5 ( ( AT91_REG * ) 0xFFFD8044 ) /* (ADC) ADC Channel Data Register 5 */ +#define AT91C_ADC_MR ( ( AT91_REG * ) 0xFFFD8004 ) /* (ADC) ADC Mode Register */ +#define AT91C_ADC_CDR6 ( ( AT91_REG * ) 0xFFFD8048 ) /* (ADC) ADC Channel Data Register 6 */ +#define AT91C_ADC_CR ( ( AT91_REG * ) 0xFFFD8000 ) /* (ADC) ADC Control Register */ +#define AT91C_ADC_CHER ( ( AT91_REG * ) 0xFFFD8010 ) /* (ADC) ADC Channel Enable Register */ +#define AT91C_ADC_CHSR ( ( AT91_REG * ) 0xFFFD8018 ) /* (ADC) ADC Channel Status Register */ +#define AT91C_ADC_IER ( ( AT91_REG * ) 0xFFFD8024 ) /* (ADC) ADC Interrupt Enable Register */ +#define AT91C_ADC_SR ( ( AT91_REG * ) 0xFFFD801C ) /* (ADC) ADC Status Register */ +#define AT91C_ADC_CHDR ( ( AT91_REG * ) 0xFFFD8014 ) /* (ADC) ADC Channel Disable Register */ +#define AT91C_ADC_IDR ( ( AT91_REG * ) 0xFFFD8028 ) /* (ADC) ADC Interrupt Disable Register */ +#define AT91C_ADC_LCDR ( ( AT91_REG * ) 0xFFFD8020 ) /* (ADC) ADC Last Converted Data Register */ +/* ========== Register definition for PDC_SSC peripheral ========== */ +#define AT91C_SSC_PTCR ( ( AT91_REG * ) 0xFFFD4120 ) /* (PDC_SSC) PDC Transfer Control Register */ +#define AT91C_SSC_TNPR ( ( AT91_REG * ) 0xFFFD4118 ) /* (PDC_SSC) Transmit Next Pointer Register */ +#define AT91C_SSC_RNPR ( ( AT91_REG * ) 0xFFFD4110 ) /* (PDC_SSC) Receive Next Pointer Register */ +#define AT91C_SSC_TPR ( ( AT91_REG * ) 0xFFFD4108 ) /* (PDC_SSC) Transmit Pointer Register */ +#define AT91C_SSC_RPR ( ( AT91_REG * ) 0xFFFD4100 ) /* (PDC_SSC) Receive Pointer Register */ +#define AT91C_SSC_PTSR ( ( AT91_REG * ) 0xFFFD4124 ) /* (PDC_SSC) PDC Transfer Status Register */ +#define AT91C_SSC_TNCR ( ( AT91_REG * ) 0xFFFD411C ) /* (PDC_SSC) Transmit Next Counter Register */ +#define AT91C_SSC_RNCR ( ( AT91_REG * ) 0xFFFD4114 ) /* (PDC_SSC) Receive Next Counter Register */ +#define AT91C_SSC_TCR ( ( AT91_REG * ) 0xFFFD410C ) /* (PDC_SSC) Transmit Counter Register */ +#define AT91C_SSC_RCR ( ( AT91_REG * ) 0xFFFD4104 ) /* (PDC_SSC) Receive Counter Register */ +/* ========== Register definition for SSC peripheral ========== */ +#define AT91C_SSC_RFMR ( ( AT91_REG * ) 0xFFFD4014 ) /* (SSC) Receive Frame Mode Register */ +#define AT91C_SSC_CMR ( ( AT91_REG * ) 0xFFFD4004 ) /* (SSC) Clock Mode Register */ +#define AT91C_SSC_IDR ( ( AT91_REG * ) 0xFFFD4048 ) /* (SSC) Interrupt Disable Register */ +#define AT91C_SSC_SR ( ( AT91_REG * ) 0xFFFD4040 ) /* (SSC) Status Register */ +#define AT91C_SSC_RC0R ( ( AT91_REG * ) 0xFFFD4038 ) /* (SSC) Receive Compare 0 Register */ +#define AT91C_SSC_RSHR ( ( AT91_REG * ) 0xFFFD4030 ) /* (SSC) Receive Sync Holding Register */ +#define AT91C_SSC_RHR ( ( AT91_REG * ) 0xFFFD4020 ) /* (SSC) Receive Holding Register */ +#define AT91C_SSC_TCMR ( ( AT91_REG * ) 0xFFFD4018 ) /* (SSC) Transmit Clock Mode Register */ +#define AT91C_SSC_RCMR ( ( AT91_REG * ) 0xFFFD4010 ) /* (SSC) Receive Clock ModeRegister */ +#define AT91C_SSC_CR ( ( AT91_REG * ) 0xFFFD4000 ) /* (SSC) Control Register */ +#define AT91C_SSC_IMR ( ( AT91_REG * ) 0xFFFD404C ) /* (SSC) Interrupt Mask Register */ +#define AT91C_SSC_IER ( ( AT91_REG * ) 0xFFFD4044 ) /* (SSC) Interrupt Enable Register */ +#define AT91C_SSC_RC1R ( ( AT91_REG * ) 0xFFFD403C ) /* (SSC) Receive Compare 1 Register */ +#define AT91C_SSC_TSHR ( ( AT91_REG * ) 0xFFFD4034 ) /* (SSC) Transmit Sync Holding Register */ +#define AT91C_SSC_THR ( ( AT91_REG * ) 0xFFFD4024 ) /* (SSC) Transmit Holding Register */ +#define AT91C_SSC_TFMR ( ( AT91_REG * ) 0xFFFD401C ) /* (SSC) Transmit Frame Mode Register */ +/* ========== Register definition for PDC_US1 peripheral ========== */ +#define AT91C_US1_PTSR ( ( AT91_REG * ) 0xFFFC4124 ) /* (PDC_US1) PDC Transfer Status Register */ +#define AT91C_US1_TNCR ( ( AT91_REG * ) 0xFFFC411C ) /* (PDC_US1) Transmit Next Counter Register */ +#define AT91C_US1_RNCR ( ( AT91_REG * ) 0xFFFC4114 ) /* (PDC_US1) Receive Next Counter Register */ +#define AT91C_US1_TCR ( ( AT91_REG * ) 0xFFFC410C ) /* (PDC_US1) Transmit Counter Register */ +#define AT91C_US1_RCR ( ( AT91_REG * ) 0xFFFC4104 ) /* (PDC_US1) Receive Counter Register */ +#define AT91C_US1_PTCR ( ( AT91_REG * ) 0xFFFC4120 ) /* (PDC_US1) PDC Transfer Control Register */ +#define AT91C_US1_TNPR ( ( AT91_REG * ) 0xFFFC4118 ) /* (PDC_US1) Transmit Next Pointer Register */ +#define AT91C_US1_RNPR ( ( AT91_REG * ) 0xFFFC4110 ) /* (PDC_US1) Receive Next Pointer Register */ +#define AT91C_US1_TPR ( ( AT91_REG * ) 0xFFFC4108 ) /* (PDC_US1) Transmit Pointer Register */ +#define AT91C_US1_RPR ( ( AT91_REG * ) 0xFFFC4100 ) /* (PDC_US1) Receive Pointer Register */ +/* ========== Register definition for US1 peripheral ========== */ +#define AT91C_US1_XXR ( ( AT91_REG * ) 0xFFFC4048 ) /* (US1) XON_XOFF Register */ +#define AT91C_US1_RHR ( ( AT91_REG * ) 0xFFFC4018 ) /* (US1) Receiver Holding Register */ +#define AT91C_US1_IMR ( ( AT91_REG * ) 0xFFFC4010 ) /* (US1) Interrupt Mask Register */ +#define AT91C_US1_IER ( ( AT91_REG * ) 0xFFFC4008 ) /* (US1) Interrupt Enable Register */ +#define AT91C_US1_CR ( ( AT91_REG * ) 0xFFFC4000 ) /* (US1) Control Register */ +#define AT91C_US1_RTOR ( ( AT91_REG * ) 0xFFFC4024 ) /* (US1) Receiver Time-out Register */ +#define AT91C_US1_THR ( ( AT91_REG * ) 0xFFFC401C ) /* (US1) Transmitter Holding Register */ +#define AT91C_US1_CSR ( ( AT91_REG * ) 0xFFFC4014 ) /* (US1) Channel Status Register */ +#define AT91C_US1_IDR ( ( AT91_REG * ) 0xFFFC400C ) /* (US1) Interrupt Disable Register */ +#define AT91C_US1_FIDI ( ( AT91_REG * ) 0xFFFC4040 ) /* (US1) FI_DI_Ratio Register */ +#define AT91C_US1_BRGR ( ( AT91_REG * ) 0xFFFC4020 ) /* (US1) Baud Rate Generator Register */ +#define AT91C_US1_TTGR ( ( AT91_REG * ) 0xFFFC4028 ) /* (US1) Transmitter Time-guard Register */ +#define AT91C_US1_IF ( ( AT91_REG * ) 0xFFFC404C ) /* (US1) IRDA_FILTER Register */ +#define AT91C_US1_NER ( ( AT91_REG * ) 0xFFFC4044 ) /* (US1) Nb Errors Register */ +#define AT91C_US1_MR ( ( AT91_REG * ) 0xFFFC4004 ) /* (US1) Mode Register */ +/* ========== Register definition for PDC_US0 peripheral ========== */ +#define AT91C_US0_PTCR ( ( AT91_REG * ) 0xFFFC0120 ) /* (PDC_US0) PDC Transfer Control Register */ +#define AT91C_US0_TNPR ( ( AT91_REG * ) 0xFFFC0118 ) /* (PDC_US0) Transmit Next Pointer Register */ +#define AT91C_US0_RNPR ( ( AT91_REG * ) 0xFFFC0110 ) /* (PDC_US0) Receive Next Pointer Register */ +#define AT91C_US0_TPR ( ( AT91_REG * ) 0xFFFC0108 ) /* (PDC_US0) Transmit Pointer Register */ +#define AT91C_US0_RPR ( ( AT91_REG * ) 0xFFFC0100 ) /* (PDC_US0) Receive Pointer Register */ +#define AT91C_US0_PTSR ( ( AT91_REG * ) 0xFFFC0124 ) /* (PDC_US0) PDC Transfer Status Register */ +#define AT91C_US0_TNCR ( ( AT91_REG * ) 0xFFFC011C ) /* (PDC_US0) Transmit Next Counter Register */ +#define AT91C_US0_RNCR ( ( AT91_REG * ) 0xFFFC0114 ) /* (PDC_US0) Receive Next Counter Register */ +#define AT91C_US0_TCR ( ( AT91_REG * ) 0xFFFC010C ) /* (PDC_US0) Transmit Counter Register */ +#define AT91C_US0_RCR ( ( AT91_REG * ) 0xFFFC0104 ) /* (PDC_US0) Receive Counter Register */ +/* ========== Register definition for US0 peripheral ========== */ +#define AT91C_US0_TTGR ( ( AT91_REG * ) 0xFFFC0028 ) /* (US0) Transmitter Time-guard Register */ +#define AT91C_US0_BRGR ( ( AT91_REG * ) 0xFFFC0020 ) /* (US0) Baud Rate Generator Register */ +#define AT91C_US0_RHR ( ( AT91_REG * ) 0xFFFC0018 ) /* (US0) Receiver Holding Register */ +#define AT91C_US0_IMR ( ( AT91_REG * ) 0xFFFC0010 ) /* (US0) Interrupt Mask Register */ +#define AT91C_US0_NER ( ( AT91_REG * ) 0xFFFC0044 ) /* (US0) Nb Errors Register */ +#define AT91C_US0_RTOR ( ( AT91_REG * ) 0xFFFC0024 ) /* (US0) Receiver Time-out Register */ +#define AT91C_US0_XXR ( ( AT91_REG * ) 0xFFFC0048 ) /* (US0) XON_XOFF Register */ +#define AT91C_US0_FIDI ( ( AT91_REG * ) 0xFFFC0040 ) /* (US0) FI_DI_Ratio Register */ +#define AT91C_US0_CR ( ( AT91_REG * ) 0xFFFC0000 ) /* (US0) Control Register */ +#define AT91C_US0_IER ( ( AT91_REG * ) 0xFFFC0008 ) /* (US0) Interrupt Enable Register */ +#define AT91C_US0_IF ( ( AT91_REG * ) 0xFFFC004C ) /* (US0) IRDA_FILTER Register */ +#define AT91C_US0_MR ( ( AT91_REG * ) 0xFFFC0004 ) /* (US0) Mode Register */ +#define AT91C_US0_IDR ( ( AT91_REG * ) 0xFFFC000C ) /* (US0) Interrupt Disable Register */ +#define AT91C_US0_CSR ( ( AT91_REG * ) 0xFFFC0014 ) /* (US0) Channel Status Register */ +#define AT91C_US0_THR ( ( AT91_REG * ) 0xFFFC001C ) /* (US0) Transmitter Holding Register */ +/* ========== Register definition for TWI peripheral ========== */ +#define AT91C_TWI_RHR ( ( AT91_REG * ) 0xFFFB8030 ) /* (TWI) Receive Holding Register */ +#define AT91C_TWI_IDR ( ( AT91_REG * ) 0xFFFB8028 ) /* (TWI) Interrupt Disable Register */ +#define AT91C_TWI_SR ( ( AT91_REG * ) 0xFFFB8020 ) /* (TWI) Status Register */ +#define AT91C_TWI_CWGR ( ( AT91_REG * ) 0xFFFB8010 ) /* (TWI) Clock Waveform Generator Register */ +#define AT91C_TWI_SMR ( ( AT91_REG * ) 0xFFFB8008 ) /* (TWI) Slave Mode Register */ +#define AT91C_TWI_CR ( ( AT91_REG * ) 0xFFFB8000 ) /* (TWI) Control Register */ +#define AT91C_TWI_THR ( ( AT91_REG * ) 0xFFFB8034 ) /* (TWI) Transmit Holding Register */ +#define AT91C_TWI_IMR ( ( AT91_REG * ) 0xFFFB802C ) /* (TWI) Interrupt Mask Register */ +#define AT91C_TWI_IER ( ( AT91_REG * ) 0xFFFB8024 ) /* (TWI) Interrupt Enable Register */ +#define AT91C_TWI_IADR ( ( AT91_REG * ) 0xFFFB800C ) /* (TWI) Internal Address Register */ +#define AT91C_TWI_MMR ( ( AT91_REG * ) 0xFFFB8004 ) /* (TWI) Master Mode Register */ +/* ========== Register definition for TC2 peripheral ========== */ +#define AT91C_TC2_IMR ( ( AT91_REG * ) 0xFFFA00AC ) /* (TC2) Interrupt Mask Register */ +#define AT91C_TC2_IER ( ( AT91_REG * ) 0xFFFA00A4 ) /* (TC2) Interrupt Enable Register */ +#define AT91C_TC2_RC ( ( AT91_REG * ) 0xFFFA009C ) /* (TC2) Register C */ +#define AT91C_TC2_RA ( ( AT91_REG * ) 0xFFFA0094 ) /* (TC2) Register A */ +#define AT91C_TC2_CMR ( ( AT91_REG * ) 0xFFFA0084 ) /* (TC2) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC2_IDR ( ( AT91_REG * ) 0xFFFA00A8 ) /* (TC2) Interrupt Disable Register */ +#define AT91C_TC2_SR ( ( AT91_REG * ) 0xFFFA00A0 ) /* (TC2) Status Register */ +#define AT91C_TC2_RB ( ( AT91_REG * ) 0xFFFA0098 ) /* (TC2) Register B */ +#define AT91C_TC2_CV ( ( AT91_REG * ) 0xFFFA0090 ) /* (TC2) Counter Value */ +#define AT91C_TC2_CCR ( ( AT91_REG * ) 0xFFFA0080 ) /* (TC2) Channel Control Register */ +/* ========== Register definition for TC1 peripheral ========== */ +#define AT91C_TC1_IMR ( ( AT91_REG * ) 0xFFFA006C ) /* (TC1) Interrupt Mask Register */ +#define AT91C_TC1_IER ( ( AT91_REG * ) 0xFFFA0064 ) /* (TC1) Interrupt Enable Register */ +#define AT91C_TC1_RC ( ( AT91_REG * ) 0xFFFA005C ) /* (TC1) Register C */ +#define AT91C_TC1_RA ( ( AT91_REG * ) 0xFFFA0054 ) /* (TC1) Register A */ +#define AT91C_TC1_CMR ( ( AT91_REG * ) 0xFFFA0044 ) /* (TC1) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC1_IDR ( ( AT91_REG * ) 0xFFFA0068 ) /* (TC1) Interrupt Disable Register */ +#define AT91C_TC1_SR ( ( AT91_REG * ) 0xFFFA0060 ) /* (TC1) Status Register */ +#define AT91C_TC1_RB ( ( AT91_REG * ) 0xFFFA0058 ) /* (TC1) Register B */ +#define AT91C_TC1_CV ( ( AT91_REG * ) 0xFFFA0050 ) /* (TC1) Counter Value */ +#define AT91C_TC1_CCR ( ( AT91_REG * ) 0xFFFA0040 ) /* (TC1) Channel Control Register */ +/* ========== Register definition for TC0 peripheral ========== */ +#define AT91C_TC0_IMR ( ( AT91_REG * ) 0xFFFA002C ) /* (TC0) Interrupt Mask Register */ +#define AT91C_TC0_IER ( ( AT91_REG * ) 0xFFFA0024 ) /* (TC0) Interrupt Enable Register */ +#define AT91C_TC0_RC ( ( AT91_REG * ) 0xFFFA001C ) /* (TC0) Register C */ +#define AT91C_TC0_RA ( ( AT91_REG * ) 0xFFFA0014 ) /* (TC0) Register A */ +#define AT91C_TC0_CMR ( ( AT91_REG * ) 0xFFFA0004 ) /* (TC0) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC0_IDR ( ( AT91_REG * ) 0xFFFA0028 ) /* (TC0) Interrupt Disable Register */ +#define AT91C_TC0_SR ( ( AT91_REG * ) 0xFFFA0020 ) /* (TC0) Status Register */ +#define AT91C_TC0_RB ( ( AT91_REG * ) 0xFFFA0018 ) /* (TC0) Register B */ +#define AT91C_TC0_CV ( ( AT91_REG * ) 0xFFFA0010 ) /* (TC0) Counter Value */ +#define AT91C_TC0_CCR ( ( AT91_REG * ) 0xFFFA0000 ) /* (TC0) Channel Control Register */ +/* ========== Register definition for TCB peripheral ========== */ +#define AT91C_TCB_BMR ( ( AT91_REG * ) 0xFFFA00C4 ) /* (TCB) TC Block Mode Register */ +#define AT91C_TCB_BCR ( ( AT91_REG * ) 0xFFFA00C0 ) /* (TCB) TC Block Control Register */ +/* ========== Register definition for PWMC_CH3 peripheral ========== */ +#define AT91C_CH3_CUPDR ( ( AT91_REG * ) 0xFFFCC270 ) /* (PWMC_CH3) Channel Update Register */ +#define AT91C_CH3_CPRDR ( ( AT91_REG * ) 0xFFFCC268 ) /* (PWMC_CH3) Channel Period Register */ +#define AT91C_CH3_CMR ( ( AT91_REG * ) 0xFFFCC260 ) /* (PWMC_CH3) Channel Mode Register */ +#define AT91C_CH3_Reserved ( ( AT91_REG * ) 0xFFFCC274 ) /* (PWMC_CH3) Reserved */ +#define AT91C_CH3_CCNTR ( ( AT91_REG * ) 0xFFFCC26C ) /* (PWMC_CH3) Channel Counter Register */ +#define AT91C_CH3_CDTYR ( ( AT91_REG * ) 0xFFFCC264 ) /* (PWMC_CH3) Channel Duty Cycle Register */ +/* ========== Register definition for PWMC_CH2 peripheral ========== */ +#define AT91C_CH2_CUPDR ( ( AT91_REG * ) 0xFFFCC250 ) /* (PWMC_CH2) Channel Update Register */ +#define AT91C_CH2_CPRDR ( ( AT91_REG * ) 0xFFFCC248 ) /* (PWMC_CH2) Channel Period Register */ +#define AT91C_CH2_CMR ( ( AT91_REG * ) 0xFFFCC240 ) /* (PWMC_CH2) Channel Mode Register */ +#define AT91C_CH2_Reserved ( ( AT91_REG * ) 0xFFFCC254 ) /* (PWMC_CH2) Reserved */ +#define AT91C_CH2_CCNTR ( ( AT91_REG * ) 0xFFFCC24C ) /* (PWMC_CH2) Channel Counter Register */ +#define AT91C_CH2_CDTYR ( ( AT91_REG * ) 0xFFFCC244 ) /* (PWMC_CH2) Channel Duty Cycle Register */ +/* ========== Register definition for PWMC_CH1 peripheral ========== */ +#define AT91C_CH1_CUPDR ( ( AT91_REG * ) 0xFFFCC230 ) /* (PWMC_CH1) Channel Update Register */ +#define AT91C_CH1_CPRDR ( ( AT91_REG * ) 0xFFFCC228 ) /* (PWMC_CH1) Channel Period Register */ +#define AT91C_CH1_CMR ( ( AT91_REG * ) 0xFFFCC220 ) /* (PWMC_CH1) Channel Mode Register */ +#define AT91C_CH1_Reserved ( ( AT91_REG * ) 0xFFFCC234 ) /* (PWMC_CH1) Reserved */ +#define AT91C_CH1_CCNTR ( ( AT91_REG * ) 0xFFFCC22C ) /* (PWMC_CH1) Channel Counter Register */ +#define AT91C_CH1_CDTYR ( ( AT91_REG * ) 0xFFFCC224 ) /* (PWMC_CH1) Channel Duty Cycle Register */ +/* ========== Register definition for PWMC_CH0 peripheral ========== */ +#define AT91C_CH0_CUPDR ( ( AT91_REG * ) 0xFFFCC210 ) /* (PWMC_CH0) Channel Update Register */ +#define AT91C_CH0_CPRDR ( ( AT91_REG * ) 0xFFFCC208 ) /* (PWMC_CH0) Channel Period Register */ +#define AT91C_CH0_CMR ( ( AT91_REG * ) 0xFFFCC200 ) /* (PWMC_CH0) Channel Mode Register */ +#define AT91C_CH0_Reserved ( ( AT91_REG * ) 0xFFFCC214 ) /* (PWMC_CH0) Reserved */ +#define AT91C_CH0_CCNTR ( ( AT91_REG * ) 0xFFFCC20C ) /* (PWMC_CH0) Channel Counter Register */ +#define AT91C_CH0_CDTYR ( ( AT91_REG * ) 0xFFFCC204 ) /* (PWMC_CH0) Channel Duty Cycle Register */ +/* ========== Register definition for PWMC peripheral ========== */ +#define AT91C_PWMC_VR ( ( AT91_REG * ) 0xFFFCC0FC ) /* (PWMC) PWMC Version Register */ +#define AT91C_PWMC_ISR ( ( AT91_REG * ) 0xFFFCC01C ) /* (PWMC) PWMC Interrupt Status Register */ +#define AT91C_PWMC_IDR ( ( AT91_REG * ) 0xFFFCC014 ) /* (PWMC) PWMC Interrupt Disable Register */ +#define AT91C_PWMC_SR ( ( AT91_REG * ) 0xFFFCC00C ) /* (PWMC) PWMC Status Register */ +#define AT91C_PWMC_ENA ( ( AT91_REG * ) 0xFFFCC004 ) /* (PWMC) PWMC Enable Register */ +#define AT91C_PWMC_IMR ( ( AT91_REG * ) 0xFFFCC018 ) /* (PWMC) PWMC Interrupt Mask Register */ +#define AT91C_PWMC_MR ( ( AT91_REG * ) 0xFFFCC000 ) /* (PWMC) PWMC Mode Register */ +#define AT91C_PWMC_DIS ( ( AT91_REG * ) 0xFFFCC008 ) /* (PWMC) PWMC Disable Register */ +#define AT91C_PWMC_IER ( ( AT91_REG * ) 0xFFFCC010 ) /* (PWMC) PWMC Interrupt Enable Register */ +/* ========== Register definition for UDP peripheral ========== */ +#define AT91C_UDP_ISR ( ( AT91_REG * ) 0xFFFB001C ) /* (UDP) Interrupt Status Register */ +#define AT91C_UDP_IDR ( ( AT91_REG * ) 0xFFFB0014 ) /* (UDP) Interrupt Disable Register */ +#define AT91C_UDP_GLBSTATE ( ( AT91_REG * ) 0xFFFB0004 ) /* (UDP) Global State Register */ +#define AT91C_UDP_FDR ( ( AT91_REG * ) 0xFFFB0050 ) /* (UDP) Endpoint FIFO Data Register */ +#define AT91C_UDP_CSR ( ( AT91_REG * ) 0xFFFB0030 ) /* (UDP) Endpoint Control and Status Register */ +#define AT91C_UDP_RSTEP ( ( AT91_REG * ) 0xFFFB0028 ) /* (UDP) Reset Endpoint Register */ +#define AT91C_UDP_ICR ( ( AT91_REG * ) 0xFFFB0020 ) /* (UDP) Interrupt Clear Register */ +#define AT91C_UDP_IMR ( ( AT91_REG * ) 0xFFFB0018 ) /* (UDP) Interrupt Mask Register */ +#define AT91C_UDP_IER ( ( AT91_REG * ) 0xFFFB0010 ) /* (UDP) Interrupt Enable Register */ +#define AT91C_UDP_FADDR ( ( AT91_REG * ) 0xFFFB0008 ) /* (UDP) Function Address Register */ +#define AT91C_UDP_NUM ( ( AT91_REG * ) 0xFFFB0000 ) /* (UDP) Frame Number Register */ + +/* ***************************************************************************** */ +/* PIO DEFINITIONS FOR AT91SAM7S64 */ +/* ***************************************************************************** */ +#define AT91C_PIO_PA0 ( ( unsigned int ) 1 << 0 ) /* Pin Controlled by PA0 */ +#define AT91C_PA0_PWM0 ( ( unsigned int ) AT91C_PIO_PA0 ) /* PWM Channel 0 */ +#define AT91C_PA0_TIOA0 ( ( unsigned int ) AT91C_PIO_PA0 ) /* Timer Counter 0 Multipurpose Timer I/O Pin A */ +#define AT91C_PIO_PA1 ( ( unsigned int ) 1 << 1 ) /* Pin Controlled by PA1 */ +#define AT91C_PA1_PWM1 ( ( unsigned int ) AT91C_PIO_PA1 ) /* PWM Channel 1 */ +#define AT91C_PA1_TIOB0 ( ( unsigned int ) AT91C_PIO_PA1 ) /* Timer Counter 0 Multipurpose Timer I/O Pin B */ +#define AT91C_PIO_PA10 ( ( unsigned int ) 1 << 10 ) /* Pin Controlled by PA10 */ +#define AT91C_PA10_DTXD ( ( unsigned int ) AT91C_PIO_PA10 ) /* DBGU Debug Transmit Data */ +#define AT91C_PA10_NPCS2 ( ( unsigned int ) AT91C_PIO_PA10 ) /* SPI Peripheral Chip Select 2 */ +#define AT91C_PIO_PA11 ( ( unsigned int ) 1 << 11 ) /* Pin Controlled by PA11 */ +#define AT91C_PA11_NPCS0 ( ( unsigned int ) AT91C_PIO_PA11 ) /* SPI Peripheral Chip Select 0 */ +#define AT91C_PA11_PWM0 ( ( unsigned int ) AT91C_PIO_PA11 ) /* PWM Channel 0 */ +#define AT91C_PIO_PA12 ( ( unsigned int ) 1 << 12 ) /* Pin Controlled by PA12 */ +#define AT91C_PA12_MISO ( ( unsigned int ) AT91C_PIO_PA12 ) /* SPI Master In Slave */ +#define AT91C_PA12_PWM1 ( ( unsigned int ) AT91C_PIO_PA12 ) /* PWM Channel 1 */ +#define AT91C_PIO_PA13 ( ( unsigned int ) 1 << 13 ) /* Pin Controlled by PA13 */ +#define AT91C_PA13_MOSI ( ( unsigned int ) AT91C_PIO_PA13 ) /* SPI Master Out Slave */ +#define AT91C_PA13_PWM2 ( ( unsigned int ) AT91C_PIO_PA13 ) /* PWM Channel 2 */ +#define AT91C_PIO_PA14 ( ( unsigned int ) 1 << 14 ) /* Pin Controlled by PA14 */ +#define AT91C_PA14_SPCK ( ( unsigned int ) AT91C_PIO_PA14 ) /* SPI Serial Clock */ +#define AT91C_PA14_PWM3 ( ( unsigned int ) AT91C_PIO_PA14 ) /* PWM Channel 3 */ +#define AT91C_PIO_PA15 ( ( unsigned int ) 1 << 15 ) /* Pin Controlled by PA15 */ +#define AT91C_PA15_TF ( ( unsigned int ) AT91C_PIO_PA15 ) /* SSC Transmit Frame Sync */ +#define AT91C_PA15_TIOA1 ( ( unsigned int ) AT91C_PIO_PA15 ) /* Timer Counter 1 Multipurpose Timer I/O Pin A */ +#define AT91C_PIO_PA16 ( ( unsigned int ) 1 << 16 ) /* Pin Controlled by PA16 */ +#define AT91C_PA16_TK ( ( unsigned int ) AT91C_PIO_PA16 ) /* SSC Transmit Clock */ +#define AT91C_PA16_TIOB1 ( ( unsigned int ) AT91C_PIO_PA16 ) /* Timer Counter 1 Multipurpose Timer I/O Pin B */ +#define AT91C_PIO_PA17 ( ( unsigned int ) 1 << 17 ) /* Pin Controlled by PA17 */ +#define AT91C_PA17_TD ( ( unsigned int ) AT91C_PIO_PA17 ) /* SSC Transmit data */ +#define AT91C_PA17_PCK1 ( ( unsigned int ) AT91C_PIO_PA17 ) /* PMC Programmable Clock Output 1 */ +#define AT91C_PIO_PA18 ( ( unsigned int ) 1 << 18 ) /* Pin Controlled by PA18 */ +#define AT91C_PA18_RD ( ( unsigned int ) AT91C_PIO_PA18 ) /* SSC Receive Data */ +#define AT91C_PA18_PCK2 ( ( unsigned int ) AT91C_PIO_PA18 ) /* PMC Programmable Clock Output 2 */ +#define AT91C_PIO_PA19 ( ( unsigned int ) 1 << 19 ) /* Pin Controlled by PA19 */ +#define AT91C_PA19_RK ( ( unsigned int ) AT91C_PIO_PA19 ) /* SSC Receive Clock */ +#define AT91C_PA19_FIQ ( ( unsigned int ) AT91C_PIO_PA19 ) /* AIC Fast Interrupt Input */ +#define AT91C_PIO_PA2 ( ( unsigned int ) 1 << 2 ) /* Pin Controlled by PA2 */ +#define AT91C_PA2_PWM2 ( ( unsigned int ) AT91C_PIO_PA2 ) /* PWM Channel 2 */ +#define AT91C_PA2_SCK0 ( ( unsigned int ) AT91C_PIO_PA2 ) /* USART 0 Serial Clock */ +#define AT91C_PIO_PA20 ( ( unsigned int ) 1 << 20 ) /* Pin Controlled by PA20 */ +#define AT91C_PA20_RF ( ( unsigned int ) AT91C_PIO_PA20 ) /* SSC Receive Frame Sync */ +#define AT91C_PA20_IRQ0 ( ( unsigned int ) AT91C_PIO_PA20 ) /* External Interrupt 0 */ +#define AT91C_PIO_PA21 ( ( unsigned int ) 1 << 21 ) /* Pin Controlled by PA21 */ +#define AT91C_PA21_RXD1 ( ( unsigned int ) AT91C_PIO_PA21 ) /* USART 1 Receive Data */ +#define AT91C_PA21_PCK1 ( ( unsigned int ) AT91C_PIO_PA21 ) /* PMC Programmable Clock Output 1 */ +#define AT91C_PIO_PA22 ( ( unsigned int ) 1 << 22 ) /* Pin Controlled by PA22 */ +#define AT91C_PA22_TXD1 ( ( unsigned int ) AT91C_PIO_PA22 ) /* USART 1 Transmit Data */ +#define AT91C_PA22_NPCS3 ( ( unsigned int ) AT91C_PIO_PA22 ) /* SPI Peripheral Chip Select 3 */ +#define AT91C_PIO_PA23 ( ( unsigned int ) 1 << 23 ) /* Pin Controlled by PA23 */ +#define AT91C_PA23_SCK1 ( ( unsigned int ) AT91C_PIO_PA23 ) /* USART 1 Serial Clock */ +#define AT91C_PA23_PWM0 ( ( unsigned int ) AT91C_PIO_PA23 ) /* PWM Channel 0 */ +#define AT91C_PIO_PA24 ( ( unsigned int ) 1 << 24 ) /* Pin Controlled by PA24 */ +#define AT91C_PA24_RTS1 ( ( unsigned int ) AT91C_PIO_PA24 ) /* USART 1 Ready To Send */ +#define AT91C_PA24_PWM1 ( ( unsigned int ) AT91C_PIO_PA24 ) /* PWM Channel 1 */ +#define AT91C_PIO_PA25 ( ( unsigned int ) 1 << 25 ) /* Pin Controlled by PA25 */ +#define AT91C_PA25_CTS1 ( ( unsigned int ) AT91C_PIO_PA25 ) /* USART 1 Clear To Send */ +#define AT91C_PA25_PWM2 ( ( unsigned int ) AT91C_PIO_PA25 ) /* PWM Channel 2 */ +#define AT91C_PIO_PA26 ( ( unsigned int ) 1 << 26 ) /* Pin Controlled by PA26 */ +#define AT91C_PA26_DCD1 ( ( unsigned int ) AT91C_PIO_PA26 ) /* USART 1 Data Carrier Detect */ +#define AT91C_PA26_TIOA2 ( ( unsigned int ) AT91C_PIO_PA26 ) /* Timer Counter 2 Multipurpose Timer I/O Pin A */ +#define AT91C_PIO_PA27 ( ( unsigned int ) 1 << 27 ) /* Pin Controlled by PA27 */ +#define AT91C_PA27_DTR1 ( ( unsigned int ) AT91C_PIO_PA27 ) /* USART 1 Data Terminal ready */ +#define AT91C_PA27_TIOB2 ( ( unsigned int ) AT91C_PIO_PA27 ) /* Timer Counter 2 Multipurpose Timer I/O Pin B */ +#define AT91C_PIO_PA28 ( ( unsigned int ) 1 << 28 ) /* Pin Controlled by PA28 */ +#define AT91C_PA28_DSR1 ( ( unsigned int ) AT91C_PIO_PA28 ) /* USART 1 Data Set ready */ +#define AT91C_PA28_TCLK1 ( ( unsigned int ) AT91C_PIO_PA28 ) /* Timer Counter 1 external clock input */ +#define AT91C_PIO_PA29 ( ( unsigned int ) 1 << 29 ) /* Pin Controlled by PA29 */ +#define AT91C_PA29_RI1 ( ( unsigned int ) AT91C_PIO_PA29 ) /* USART 1 Ring Indicator */ +#define AT91C_PA29_TCLK2 ( ( unsigned int ) AT91C_PIO_PA29 ) /* Timer Counter 2 external clock input */ +#define AT91C_PIO_PA3 ( ( unsigned int ) 1 << 3 ) /* Pin Controlled by PA3 */ +#define AT91C_PA3_TWD ( ( unsigned int ) AT91C_PIO_PA3 ) /* TWI Two-wire Serial Data */ +#define AT91C_PA3_NPCS3 ( ( unsigned int ) AT91C_PIO_PA3 ) /* SPI Peripheral Chip Select 3 */ +#define AT91C_PIO_PA30 ( ( unsigned int ) 1 << 30 ) /* Pin Controlled by PA30 */ +#define AT91C_PA30_IRQ1 ( ( unsigned int ) AT91C_PIO_PA30 ) /* External Interrupt 1 */ +#define AT91C_PA30_NPCS2 ( ( unsigned int ) AT91C_PIO_PA30 ) /* SPI Peripheral Chip Select 2 */ +#define AT91C_PIO_PA31 ( ( unsigned int ) 1 << 31 ) /* Pin Controlled by PA31 */ +#define AT91C_PA31_NPCS1 ( ( unsigned int ) AT91C_PIO_PA31 ) /* SPI Peripheral Chip Select 1 */ +#define AT91C_PA31_PCK2 ( ( unsigned int ) AT91C_PIO_PA31 ) /* PMC Programmable Clock Output 2 */ +#define AT91C_PIO_PA4 ( ( unsigned int ) 1 << 4 ) /* Pin Controlled by PA4 */ +#define AT91C_PA4_TWCK ( ( unsigned int ) AT91C_PIO_PA4 ) /* TWI Two-wire Serial Clock */ +#define AT91C_PA4_TCLK0 ( ( unsigned int ) AT91C_PIO_PA4 ) /* Timer Counter 0 external clock input */ +#define AT91C_PIO_PA5 ( ( unsigned int ) 1 << 5 ) /* Pin Controlled by PA5 */ +#define AT91C_PA5_RXD0 ( ( unsigned int ) AT91C_PIO_PA5 ) /* USART 0 Receive Data */ +#define AT91C_PA5_NPCS3 ( ( unsigned int ) AT91C_PIO_PA5 ) /* SPI Peripheral Chip Select 3 */ +#define AT91C_PIO_PA6 ( ( unsigned int ) 1 << 6 ) /* Pin Controlled by PA6 */ +#define AT91C_PA6_TXD0 ( ( unsigned int ) AT91C_PIO_PA6 ) /* USART 0 Transmit Data */ +#define AT91C_PA6_PCK0 ( ( unsigned int ) AT91C_PIO_PA6 ) /* PMC Programmable Clock Output 0 */ +#define AT91C_PIO_PA7 ( ( unsigned int ) 1 << 7 ) /* Pin Controlled by PA7 */ +#define AT91C_PA7_RTS0 ( ( unsigned int ) AT91C_PIO_PA7 ) /* USART 0 Ready To Send */ +#define AT91C_PA7_PWM3 ( ( unsigned int ) AT91C_PIO_PA7 ) /* PWM Channel 3 */ +#define AT91C_PIO_PA8 ( ( unsigned int ) 1 << 8 ) /* Pin Controlled by PA8 */ +#define AT91C_PA8_CTS0 ( ( unsigned int ) AT91C_PIO_PA8 ) /* USART 0 Clear To Send */ +#define AT91C_PA8_ADTRG ( ( unsigned int ) AT91C_PIO_PA8 ) /* ADC External Trigger */ +#define AT91C_PIO_PA9 ( ( unsigned int ) 1 << 9 ) /* Pin Controlled by PA9 */ +#define AT91C_PA9_DRXD ( ( unsigned int ) AT91C_PIO_PA9 ) /* DBGU Debug Receive Data */ +#define AT91C_PA9_NPCS1 ( ( unsigned int ) AT91C_PIO_PA9 ) /* SPI Peripheral Chip Select 1 */ + +/* ***************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64 */ +/* ***************************************************************************** */ +#define AT91C_ID_FIQ ( ( unsigned int ) 0 ) /* Advanced Interrupt Controller (FIQ) */ +#define AT91C_ID_SYS ( ( unsigned int ) 1 ) /* System Peripheral */ +#define AT91C_ID_PIOA ( ( unsigned int ) 2 ) /* Parallel IO Controller */ +#define AT91C_ID_3_Reserved ( ( unsigned int ) 3 ) /* Reserved */ +#define AT91C_ID_ADC ( ( unsigned int ) 4 ) /* Analog-to-Digital Converter */ +#define AT91C_ID_SPI ( ( unsigned int ) 5 ) /* Serial Peripheral Interface */ +#define AT91C_ID_US0 ( ( unsigned int ) 6 ) /* USART 0 */ +#define AT91C_ID_US1 ( ( unsigned int ) 7 ) /* USART 1 */ +#define AT91C_ID_SSC ( ( unsigned int ) 8 ) /* Serial Synchronous Controller */ +#define AT91C_ID_TWI ( ( unsigned int ) 9 ) /* Two-Wire Interface */ +#define AT91C_ID_PWMC ( ( unsigned int ) 10 ) /* PWM Controller */ +#define AT91C_ID_UDP ( ( unsigned int ) 11 ) /* USB Device Port */ +#define AT91C_ID_TC0 ( ( unsigned int ) 12 ) /* Timer Counter 0 */ +#define AT91C_ID_TC1 ( ( unsigned int ) 13 ) /* Timer Counter 1 */ +#define AT91C_ID_TC2 ( ( unsigned int ) 14 ) /* Timer Counter 2 */ +#define AT91C_ID_15_Reserved ( ( unsigned int ) 15 ) /* Reserved */ +#define AT91C_ID_16_Reserved ( ( unsigned int ) 16 ) /* Reserved */ +#define AT91C_ID_17_Reserved ( ( unsigned int ) 17 ) /* Reserved */ +#define AT91C_ID_18_Reserved ( ( unsigned int ) 18 ) /* Reserved */ +#define AT91C_ID_19_Reserved ( ( unsigned int ) 19 ) /* Reserved */ +#define AT91C_ID_20_Reserved ( ( unsigned int ) 20 ) /* Reserved */ +#define AT91C_ID_21_Reserved ( ( unsigned int ) 21 ) /* Reserved */ +#define AT91C_ID_22_Reserved ( ( unsigned int ) 22 ) /* Reserved */ +#define AT91C_ID_23_Reserved ( ( unsigned int ) 23 ) /* Reserved */ +#define AT91C_ID_24_Reserved ( ( unsigned int ) 24 ) /* Reserved */ +#define AT91C_ID_25_Reserved ( ( unsigned int ) 25 ) /* Reserved */ +#define AT91C_ID_26_Reserved ( ( unsigned int ) 26 ) /* Reserved */ +#define AT91C_ID_27_Reserved ( ( unsigned int ) 27 ) /* Reserved */ +#define AT91C_ID_28_Reserved ( ( unsigned int ) 28 ) /* Reserved */ +#define AT91C_ID_29_Reserved ( ( unsigned int ) 29 ) /* Reserved */ +#define AT91C_ID_IRQ0 ( ( unsigned int ) 30 ) /* Advanced Interrupt Controller (IRQ0) */ +#define AT91C_ID_IRQ1 ( ( unsigned int ) 31 ) /* Advanced Interrupt Controller (IRQ1) */ + +/* ***************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR AT91SAM7S64 */ +/* ***************************************************************************** */ +#define AT91C_BASE_SYSC ( ( AT91PS_SYSC ) 0xFFFFF000 ) /* (SYSC) Base Address */ +#define AT91C_BASE_AIC ( ( AT91PS_AIC ) 0xFFFFF000 ) /* (AIC) Base Address */ +#define AT91C_BASE_DBGU ( ( AT91PS_DBGU ) 0xFFFFF200 ) /* (DBGU) Base Address */ +#define AT91C_BASE_PDC_DBGU ( ( AT91PS_PDC ) 0xFFFFF300 ) /* (PDC_DBGU) Base Address */ +#define AT91C_BASE_PIOA ( ( AT91PS_PIO ) 0xFFFFF400 ) /* (PIOA) Base Address */ +#define AT91C_BASE_CKGR ( ( AT91PS_CKGR ) 0xFFFFFC20 ) /* (CKGR) Base Address */ +#define AT91C_BASE_PMC ( ( AT91PS_PMC ) 0xFFFFFC00 ) /* (PMC) Base Address */ +#define AT91C_BASE_RSTC ( ( AT91PS_RSTC ) 0xFFFFFD00 ) /* (RSTC) Base Address */ +#define AT91C_BASE_RTTC ( ( AT91PS_RTTC ) 0xFFFFFD20 ) /* (RTTC) Base Address */ +#define AT91C_BASE_PITC ( ( AT91PS_PITC ) 0xFFFFFD30 ) /* (PITC) Base Address */ +#define AT91C_BASE_WDTC ( ( AT91PS_WDTC ) 0xFFFFFD40 ) /* (WDTC) Base Address */ +#define AT91C_BASE_MC ( ( AT91PS_MC ) 0xFFFFFF00 ) /* (MC) Base Address */ +#define AT91C_BASE_PDC_SPI ( ( AT91PS_PDC ) 0xFFFE0100 ) /* (PDC_SPI) Base Address */ +#define AT91C_BASE_SPI ( ( AT91PS_SPI ) 0xFFFE0000 ) /* (SPI) Base Address */ +#define AT91C_BASE_PDC_ADC ( ( AT91PS_PDC ) 0xFFFD8100 ) /* (PDC_ADC) Base Address */ +#define AT91C_BASE_ADC ( ( AT91PS_ADC ) 0xFFFD8000 ) /* (ADC) Base Address */ +#define AT91C_BASE_PDC_SSC ( ( AT91PS_PDC ) 0xFFFD4100 ) /* (PDC_SSC) Base Address */ +#define AT91C_BASE_SSC ( ( AT91PS_SSC ) 0xFFFD4000 ) /* (SSC) Base Address */ +#define AT91C_BASE_PDC_US1 ( ( AT91PS_PDC ) 0xFFFC4100 ) /* (PDC_US1) Base Address */ +#define AT91C_BASE_US1 ( ( AT91PS_USART ) 0xFFFC4000 ) /* (US1) Base Address */ +#define AT91C_BASE_PDC_US0 ( ( AT91PS_PDC ) 0xFFFC0100 ) /* (PDC_US0) Base Address */ +#define AT91C_BASE_US0 ( ( AT91PS_USART ) 0xFFFC0000 ) /* (US0) Base Address */ +#define AT91C_BASE_TWI ( ( AT91PS_TWI ) 0xFFFB8000 ) /* (TWI) Base Address */ +#define AT91C_BASE_TC2 ( ( AT91PS_TC ) 0xFFFA0080 ) /* (TC2) Base Address */ +#define AT91C_BASE_TC1 ( ( AT91PS_TC ) 0xFFFA0040 ) /* (TC1) Base Address */ +#define AT91C_BASE_TC0 ( ( AT91PS_TC ) 0xFFFA0000 ) /* (TC0) Base Address */ +#define AT91C_BASE_TCB ( ( AT91PS_TCB ) 0xFFFA0000 ) /* (TCB) Base Address */ +#define AT91C_BASE_PWMC_CH3 ( ( AT91PS_PWMC_CH ) 0xFFFCC260 ) /* (PWMC_CH3) Base Address */ +#define AT91C_BASE_PWMC_CH2 ( ( AT91PS_PWMC_CH ) 0xFFFCC240 ) /* (PWMC_CH2) Base Address */ +#define AT91C_BASE_PWMC_CH1 ( ( AT91PS_PWMC_CH ) 0xFFFCC220 ) /* (PWMC_CH1) Base Address */ +#define AT91C_BASE_PWMC_CH0 ( ( AT91PS_PWMC_CH ) 0xFFFCC200 ) /* (PWMC_CH0) Base Address */ +#define AT91C_BASE_PWMC ( ( AT91PS_PWMC ) 0xFFFCC000 ) /* (PWMC) Base Address */ +#define AT91C_BASE_UDP ( ( AT91PS_UDP ) 0xFFFB0000 ) /* (UDP) Base Address */ + +/* ***************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64 */ +/* ***************************************************************************** */ +#define AT91C_ISRAM ( ( char * ) 0x00200000 ) /* Internal SRAM base address */ +#define AT91C_ISRAM_SIZE ( ( unsigned int ) 0x00004000 ) /* Internal SRAM size in byte (16 Kbyte) */ +#define AT91C_IFLASH ( ( char * ) 0x00100000 ) /* Internal ROM base address */ +#define AT91C_IFLASH_SIZE ( ( unsigned int ) 0x00010000 ) /* Internal ROM size in byte (64 Kbyte) */ + +#endif /* ifndef AT91SAM7S64_H */ diff --git a/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h b/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h new file mode 100644 index 000000000..a39150071 --- /dev/null +++ b/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h @@ -0,0 +1,1810 @@ +/* ---------------------------------------------------------------------------- */ +/* ATMEL Microcontroller Software Support - ROUSSET - */ +/* ---------------------------------------------------------------------------- */ +/* The software is delivered "AS IS" without warranty or condition of any */ +/* kind, either express, implied or statutory. This includes without */ +/* limitation any warranty or condition with respect to merchantability or */ +/* fitness for any particular purpose, or against the infringements of */ +/* intellectual property rights of others. */ +/* ---------------------------------------------------------------------------- */ +/* File Name : AT91SAM7S64.h */ +/* Object : AT91SAM7S64 definitions */ +/* Generated : AT91 SW Application Group 07/16/2004 (07:43:09) */ +/* */ +/* CVS Reference : /AT91SAM7S64.pl/1.12/Mon Jul 12 13:02:30 2004// */ +/* CVS Reference : /SYSC_SAM7Sxx.pl/1.5/Mon Jul 12 16:22:12 2004// */ +/* CVS Reference : /MC_SAM02.pl/1.3/Wed Mar 10 08:37:04 2004// */ +/* CVS Reference : /UDP_1765B.pl/1.3/Fri Aug 2 14:45:38 2002// */ +/* CVS Reference : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// */ +/* CVS Reference : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004// */ +/* CVS Reference : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// */ +/* CVS Reference : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003// */ +/* CVS Reference : /US_1739C.pl/1.2/Mon Jul 12 17:26:24 2004// */ +/* CVS Reference : /SPI2.pl/1.2/Fri Oct 17 08:13:40 2003// */ +/* CVS Reference : /SSC_1762A.pl/1.2/Fri Nov 8 13:26:40 2002// */ +/* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// */ +/* CVS Reference : /TWI_1761B.pl/1.4/Fri Feb 7 10:30:08 2003// */ +/* CVS Reference : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:24 2002// */ +/* CVS Reference : /ADC_SAM.pl/1.7/Fri Oct 17 08:12:38 2003// */ +/* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// */ +/* ---------------------------------------------------------------------------- */ + +/* Hardware register definition */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR System Peripherals */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_SYSC structure *** */ +#define SYSC_AIC_SMR ( 0 ) /* Source Mode Register */ +#define SYSC_AIC_SVR ( 128 ) /* Source Vector Register */ +#define SYSC_AIC_IVR ( 256 ) /* IRQ Vector Register */ +#define SYSC_AIC_FVR ( 260 ) /* FIQ Vector Register */ +#define SYSC_AIC_ISR ( 264 ) /* Interrupt Status Register */ +#define SYSC_AIC_IPR ( 268 ) /* Interrupt Pending Register */ +#define SYSC_AIC_IMR ( 272 ) /* Interrupt Mask Register */ +#define SYSC_AIC_CISR ( 276 ) /* Core Interrupt Status Register */ +#define SYSC_AIC_IECR ( 288 ) /* Interrupt Enable Command Register */ +#define SYSC_AIC_IDCR ( 292 ) /* Interrupt Disable Command Register */ +#define SYSC_AIC_ICCR ( 296 ) /* Interrupt Clear Command Register */ +#define SYSC_AIC_ISCR ( 300 ) /* Interrupt Set Command Register */ +#define SYSC_AIC_EOICR ( 304 ) /* End of Interrupt Command Register */ +#define SYSC_AIC_SPU ( 308 ) /* Spurious Vector Register */ +#define SYSC_AIC_DCR ( 312 ) /* Debug Control Register (Protect) */ +#define SYSC_AIC_FFER ( 320 ) /* Fast Forcing Enable Register */ +#define SYSC_AIC_FFDR ( 324 ) /* Fast Forcing Disable Register */ +#define SYSC_AIC_FFSR ( 328 ) /* Fast Forcing Status Register */ +#define SYSC_DBGU_CR ( 512 ) /* Control Register */ +#define SYSC_DBGU_MR ( 516 ) /* Mode Register */ +#define SYSC_DBGU_IER ( 520 ) /* Interrupt Enable Register */ +#define SYSC_DBGU_IDR ( 524 ) /* Interrupt Disable Register */ +#define SYSC_DBGU_IMR ( 528 ) /* Interrupt Mask Register */ +#define SYSC_DBGU_CSR ( 532 ) /* Channel Status Register */ +#define SYSC_DBGU_RHR ( 536 ) /* Receiver Holding Register */ +#define SYSC_DBGU_THR ( 540 ) /* Transmitter Holding Register */ +#define SYSC_DBGU_BRGR ( 544 ) /* Baud Rate Generator Register */ +#define SYSC_DBGU_C1R ( 576 ) /* Chip ID1 Register */ +#define SYSC_DBGU_C2R ( 580 ) /* Chip ID2 Register */ +#define SYSC_DBGU_FNTR ( 584 ) /* Force NTRST Register */ +#define SYSC_DBGU_RPR ( 768 ) /* Receive Pointer Register */ +#define SYSC_DBGU_RCR ( 772 ) /* Receive Counter Register */ +#define SYSC_DBGU_TPR ( 776 ) /* Transmit Pointer Register */ +#define SYSC_DBGU_TCR ( 780 ) /* Transmit Counter Register */ +#define SYSC_DBGU_RNPR ( 784 ) /* Receive Next Pointer Register */ +#define SYSC_DBGU_RNCR ( 788 ) /* Receive Next Counter Register */ +#define SYSC_DBGU_TNPR ( 792 ) /* Transmit Next Pointer Register */ +#define SYSC_DBGU_TNCR ( 796 ) /* Transmit Next Counter Register */ +#define SYSC_DBGU_PTCR ( 800 ) /* PDC Transfer Control Register */ +#define SYSC_DBGU_PTSR ( 804 ) /* PDC Transfer Status Register */ +#define SYSC_PIOA_PER ( 1024 ) /* PIO Enable Register */ +#define SYSC_PIOA_PDR ( 1028 ) /* PIO Disable Register */ +#define SYSC_PIOA_PSR ( 1032 ) /* PIO Status Register */ +#define SYSC_PIOA_OER ( 1040 ) /* Output Enable Register */ +#define SYSC_PIOA_ODR ( 1044 ) /* Output Disable Registerr */ +#define SYSC_PIOA_OSR ( 1048 ) /* Output Status Register */ +#define SYSC_PIOA_IFER ( 1056 ) /* Input Filter Enable Register */ +#define SYSC_PIOA_IFDR ( 1060 ) /* Input Filter Disable Register */ +#define SYSC_PIOA_IFSR ( 1064 ) /* Input Filter Status Register */ +#define SYSC_PIOA_SODR ( 1072 ) /* Set Output Data Register */ +#define SYSC_PIOA_CODR ( 1076 ) /* Clear Output Data Register */ +#define SYSC_PIOA_ODSR ( 1080 ) /* Output Data Status Register */ +#define SYSC_PIOA_PDSR ( 1084 ) /* Pin Data Status Register */ +#define SYSC_PIOA_IER ( 1088 ) /* Interrupt Enable Register */ +#define SYSC_PIOA_IDR ( 1092 ) /* Interrupt Disable Register */ +#define SYSC_PIOA_IMR ( 1096 ) /* Interrupt Mask Register */ +#define SYSC_PIOA_ISR ( 1100 ) /* Interrupt Status Register */ +#define SYSC_PIOA_MDER ( 1104 ) /* Multi-driver Enable Register */ +#define SYSC_PIOA_MDDR ( 1108 ) /* Multi-driver Disable Register */ +#define SYSC_PIOA_MDSR ( 1112 ) /* Multi-driver Status Register */ +#define SYSC_PIOA_PPUDR ( 1120 ) /* Pull-up Disable Register */ +#define SYSC_PIOA_PPUER ( 1124 ) /* Pull-up Enable Register */ +#define SYSC_PIOA_PPUSR ( 1128 ) /* Pad Pull-up Status Register */ +#define SYSC_PIOA_ASR ( 1136 ) /* Select A Register */ +#define SYSC_PIOA_BSR ( 1140 ) /* Select B Register */ +#define SYSC_PIOA_ABSR ( 1144 ) /* AB Select Status Register */ +#define SYSC_PIOA_OWER ( 1184 ) /* Output Write Enable Register */ +#define SYSC_PIOA_OWDR ( 1188 ) /* Output Write Disable Register */ +#define SYSC_PIOA_OWSR ( 1192 ) /* Output Write Status Register */ +#define SYSC_PMC_SCER ( 3072 ) /* System Clock Enable Register */ +#define SYSC_PMC_SCDR ( 3076 ) /* System Clock Disable Register */ +#define SYSC_PMC_SCSR ( 3080 ) /* System Clock Status Register */ +#define SYSC_PMC_PCER ( 3088 ) /* Peripheral Clock Enable Register */ +#define SYSC_PMC_PCDR ( 3092 ) /* Peripheral Clock Disable Register */ +#define SYSC_PMC_PCSR ( 3096 ) /* Peripheral Clock Status Register */ +#define SYSC_PMC_MOR ( 3104 ) /* Main Oscillator Register */ +#define SYSC_PMC_MCFR ( 3108 ) /* Main Clock Frequency Register */ +#define SYSC_PMC_PLLR ( 3116 ) /* PLL Register */ +#define SYSC_PMC_MCKR ( 3120 ) /* Master Clock Register */ +#define SYSC_PMC_PCKR ( 3136 ) /* Programmable Clock Register */ +#define SYSC_PMC_IER ( 3168 ) /* Interrupt Enable Register */ +#define SYSC_PMC_IDR ( 3172 ) /* Interrupt Disable Register */ +#define SYSC_PMC_SR ( 3176 ) /* Status Register */ +#define SYSC_PMC_IMR ( 3180 ) /* Interrupt Mask Register */ +#define SYSC_RSTC_RCR ( 3328 ) /* Reset Control Register */ +#define SYSC_RSTC_RSR ( 3332 ) /* Reset Status Register */ +#define SYSC_RSTC_RMR ( 3336 ) /* Reset Mode Register */ +#define SYSC_RTTC_RTMR ( 3360 ) /* Real-time Mode Register */ +#define SYSC_RTTC_RTAR ( 3364 ) /* Real-time Alarm Register */ +#define SYSC_RTTC_RTVR ( 3368 ) /* Real-time Value Register */ +#define SYSC_RTTC_RTSR ( 3372 ) /* Real-time Status Register */ +#define SYSC_PITC_PIMR ( 3376 ) /* Period Interval Mode Register */ +#define SYSC_PITC_PISR ( 3380 ) /* Period Interval Status Register */ +#define SYSC_PITC_PIVR ( 3384 ) /* Period Interval Value Register */ +#define SYSC_PITC_PIIR ( 3388 ) /* Period Interval Image Register */ +#define SYSC_WDTC_WDCR ( 3392 ) /* Watchdog Control Register */ +#define SYSC_WDTC_WDMR ( 3396 ) /* Watchdog Mode Register */ +#define SYSC_WDTC_WDSR ( 3400 ) /* Watchdog Status Register */ +#define SYSC_SYSC_VRPM ( 3424 ) /* Voltage Regulator Power Mode Register */ +/* -------- VRPM : (SYSC Offset: 0xd60) Voltage Regulator Power Mode Register -------- */ +#define AT91C_SYSC_PSTDBY ( 0x1 << 0 ) /* (SYSC) Voltage Regulator Power Mode */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Advanced Interrupt Controller */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_AIC structure *** */ +#define AIC_SMR ( 0 ) /* Source Mode Register */ +#define AIC_SVR ( 128 ) /* Source Vector Register */ +#define AIC_IVR ( 256 ) /* IRQ Vector Register */ +#define AIC_FVR ( 260 ) /* FIQ Vector Register */ +#define AIC_ISR ( 264 ) /* Interrupt Status Register */ +#define AIC_IPR ( 268 ) /* Interrupt Pending Register */ +#define AIC_IMR ( 272 ) /* Interrupt Mask Register */ +#define AIC_CISR ( 276 ) /* Core Interrupt Status Register */ +#define AIC_IECR ( 288 ) /* Interrupt Enable Command Register */ +#define AIC_IDCR ( 292 ) /* Interrupt Disable Command Register */ +#define AIC_ICCR ( 296 ) /* Interrupt Clear Command Register */ +#define AIC_ISCR ( 300 ) /* Interrupt Set Command Register */ +#define AIC_EOICR ( 304 ) /* End of Interrupt Command Register */ +#define AIC_SPU ( 308 ) /* Spurious Vector Register */ +#define AIC_DCR ( 312 ) /* Debug Control Register (Protect) */ +#define AIC_FFER ( 320 ) /* Fast Forcing Enable Register */ +#define AIC_FFDR ( 324 ) /* Fast Forcing Disable Register */ +#define AIC_FFSR ( 328 ) /* Fast Forcing Status Register */ +/* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */ +#define AT91C_AIC_PRIOR ( 0x7 << 0 ) /* (AIC) Priority Level */ +#define AT91C_AIC_PRIOR_LOWEST ( 0x0 ) /* (AIC) Lowest priority level */ +#define AT91C_AIC_PRIOR_HIGHEST ( 0x7 ) /* (AIC) Highest priority level */ +#define AT91C_AIC_SRCTYPE ( 0x3 << 5 ) /* (AIC) Interrupt Source Type */ +#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE ( 0x0 << 5 ) /* (AIC) Internal Sources Code Label Level Sensitive */ +#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED ( 0x1 << 5 ) /* (AIC) Internal Sources Code Label Edge triggered */ +#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL ( 0x2 << 5 ) /* (AIC) External Sources Code Label High-level Sensitive */ +#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE ( 0x3 << 5 ) /* (AIC) External Sources Code Label Positive Edge triggered */ +/* -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- */ +#define AT91C_AIC_NFIQ ( 0x1 << 0 ) /* (AIC) NFIQ Status */ +#define AT91C_AIC_NIRQ ( 0x1 << 1 ) /* (AIC) NIRQ Status */ +/* -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- */ +#define AT91C_AIC_DCR_PROT ( 0x1 << 0 ) /* (AIC) Protection Mode */ +#define AT91C_AIC_DCR_GMSK ( 0x1 << 1 ) /* (AIC) General Mask */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Debug Unit */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_DBGU structure *** */ +#define DBGU_CR ( 0 ) /* Control Register */ +#define DBGU_MR ( 4 ) /* Mode Register */ +#define DBGU_IER ( 8 ) /* Interrupt Enable Register */ +#define DBGU_IDR ( 12 ) /* Interrupt Disable Register */ +#define DBGU_IMR ( 16 ) /* Interrupt Mask Register */ +#define DBGU_CSR ( 20 ) /* Channel Status Register */ +#define DBGU_RHR ( 24 ) /* Receiver Holding Register */ +#define DBGU_THR ( 28 ) /* Transmitter Holding Register */ +#define DBGU_BRGR ( 32 ) /* Baud Rate Generator Register */ +#define DBGU_C1R ( 64 ) /* Chip ID1 Register */ +#define DBGU_C2R ( 68 ) /* Chip ID2 Register */ +#define DBGU_FNTR ( 72 ) /* Force NTRST Register */ +#define DBGU_RPR ( 256 ) /* Receive Pointer Register */ +#define DBGU_RCR ( 260 ) /* Receive Counter Register */ +#define DBGU_TPR ( 264 ) /* Transmit Pointer Register */ +#define DBGU_TCR ( 268 ) /* Transmit Counter Register */ +#define DBGU_RNPR ( 272 ) /* Receive Next Pointer Register */ +#define DBGU_RNCR ( 276 ) /* Receive Next Counter Register */ +#define DBGU_TNPR ( 280 ) /* Transmit Next Pointer Register */ +#define DBGU_TNCR ( 284 ) /* Transmit Next Counter Register */ +#define DBGU_PTCR ( 288 ) /* PDC Transfer Control Register */ +#define DBGU_PTSR ( 292 ) /* PDC Transfer Status Register */ +/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */ +#define AT91C_US_RSTRX ( 0x1 << 2 ) /* (DBGU) Reset Receiver */ +#define AT91C_US_RSTTX ( 0x1 << 3 ) /* (DBGU) Reset Transmitter */ +#define AT91C_US_RXEN ( 0x1 << 4 ) /* (DBGU) Receiver Enable */ +#define AT91C_US_RXDIS ( 0x1 << 5 ) /* (DBGU) Receiver Disable */ +#define AT91C_US_TXEN ( 0x1 << 6 ) /* (DBGU) Transmitter Enable */ +#define AT91C_US_TXDIS ( 0x1 << 7 ) /* (DBGU) Transmitter Disable */ +/* -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- */ +#define AT91C_US_PAR ( 0x7 << 9 ) /* (DBGU) Parity type */ +#define AT91C_US_PAR_EVEN ( 0x0 << 9 ) /* (DBGU) Even Parity */ +#define AT91C_US_PAR_ODD ( 0x1 << 9 ) /* (DBGU) Odd Parity */ +#define AT91C_US_PAR_SPACE ( 0x2 << 9 ) /* (DBGU) Parity forced to 0 (Space) */ +#define AT91C_US_PAR_MARK ( 0x3 << 9 ) /* (DBGU) Parity forced to 1 (Mark) */ +#define AT91C_US_PAR_NONE ( 0x4 << 9 ) /* (DBGU) No Parity */ +#define AT91C_US_PAR_MULTI_DROP ( 0x6 << 9 ) /* (DBGU) Multi-drop mode */ +#define AT91C_US_CHMODE ( 0x3 << 14 ) /* (DBGU) Channel Mode */ +#define AT91C_US_CHMODE_NORMAL ( 0x0 << 14 ) /* (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. */ +#define AT91C_US_CHMODE_AUTO ( 0x1 << 14 ) /* (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. */ +#define AT91C_US_CHMODE_LOCAL ( 0x2 << 14 ) /* (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. */ +#define AT91C_US_CHMODE_REMOTE ( 0x3 << 14 ) /* (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. */ +/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ +#define AT91C_US_RXRDY ( 0x1 << 0 ) /* (DBGU) RXRDY Interrupt */ +#define AT91C_US_TXRDY ( 0x1 << 1 ) /* (DBGU) TXRDY Interrupt */ +#define AT91C_US_ENDRX ( 0x1 << 3 ) /* (DBGU) End of Receive Transfer Interrupt */ +#define AT91C_US_ENDTX ( 0x1 << 4 ) /* (DBGU) End of Transmit Interrupt */ +#define AT91C_US_OVRE ( 0x1 << 5 ) /* (DBGU) Overrun Interrupt */ +#define AT91C_US_FRAME ( 0x1 << 6 ) /* (DBGU) Framing Error Interrupt */ +#define AT91C_US_PARE ( 0x1 << 7 ) /* (DBGU) Parity Error Interrupt */ +#define AT91C_US_TXEMPTY ( 0x1 << 9 ) /* (DBGU) TXEMPTY Interrupt */ +#define AT91C_US_TXBUFE ( 0x1 << 11 ) /* (DBGU) TXBUFE Interrupt */ +#define AT91C_US_RXBUFF ( 0x1 << 12 ) /* (DBGU) RXBUFF Interrupt */ +#define AT91C_US_COMM_TX ( 0x1 << 30 ) /* (DBGU) COMM_TX Interrupt */ +#define AT91C_US_COMM_RX ( 0x1 << 31 ) /* (DBGU) COMM_RX Interrupt */ +/* -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- */ +/* -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- */ +/* -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- */ +/* -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- */ +#define AT91C_US_FORCE_NTRST ( 0x1 << 0 ) /* (DBGU) Force NTRST in JTAG */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Peripheral Data Controller */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_PDC structure *** */ +#define PDC_RPR ( 0 ) /* Receive Pointer Register */ +#define PDC_RCR ( 4 ) /* Receive Counter Register */ +#define PDC_TPR ( 8 ) /* Transmit Pointer Register */ +#define PDC_TCR ( 12 ) /* Transmit Counter Register */ +#define PDC_RNPR ( 16 ) /* Receive Next Pointer Register */ +#define PDC_RNCR ( 20 ) /* Receive Next Counter Register */ +#define PDC_TNPR ( 24 ) /* Transmit Next Pointer Register */ +#define PDC_TNCR ( 28 ) /* Transmit Next Counter Register */ +#define PDC_PTCR ( 32 ) /* PDC Transfer Control Register */ +#define PDC_PTSR ( 36 ) /* PDC Transfer Status Register */ +/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */ +#define AT91C_PDC_RXTEN ( 0x1 << 0 ) /* (PDC) Receiver Transfer Enable */ +#define AT91C_PDC_RXTDIS ( 0x1 << 1 ) /* (PDC) Receiver Transfer Disable */ +#define AT91C_PDC_TXTEN ( 0x1 << 8 ) /* (PDC) Transmitter Transfer Enable */ +#define AT91C_PDC_TXTDIS ( 0x1 << 9 ) /* (PDC) Transmitter Transfer Disable */ +/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Parallel Input Output Controller */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_PIO structure *** */ +#define PIO_PER ( 0 ) /* PIO Enable Register */ +#define PIO_PDR ( 4 ) /* PIO Disable Register */ +#define PIO_PSR ( 8 ) /* PIO Status Register */ +#define PIO_OER ( 16 ) /* Output Enable Register */ +#define PIO_ODR ( 20 ) /* Output Disable Registerr */ +#define PIO_OSR ( 24 ) /* Output Status Register */ +#define PIO_IFER ( 32 ) /* Input Filter Enable Register */ +#define PIO_IFDR ( 36 ) /* Input Filter Disable Register */ +#define PIO_IFSR ( 40 ) /* Input Filter Status Register */ +#define PIO_SODR ( 48 ) /* Set Output Data Register */ +#define PIO_CODR ( 52 ) /* Clear Output Data Register */ +#define PIO_ODSR ( 56 ) /* Output Data Status Register */ +#define PIO_PDSR ( 60 ) /* Pin Data Status Register */ +#define PIO_IER ( 64 ) /* Interrupt Enable Register */ +#define PIO_IDR ( 68 ) /* Interrupt Disable Register */ +#define PIO_IMR ( 72 ) /* Interrupt Mask Register */ +#define PIO_ISR ( 76 ) /* Interrupt Status Register */ +#define PIO_MDER ( 80 ) /* Multi-driver Enable Register */ +#define PIO_MDDR ( 84 ) /* Multi-driver Disable Register */ +#define PIO_MDSR ( 88 ) /* Multi-driver Status Register */ +#define PIO_PPUDR ( 96 ) /* Pull-up Disable Register */ +#define PIO_PPUER ( 100 ) /* Pull-up Enable Register */ +#define PIO_PPUSR ( 104 ) /* Pad Pull-up Status Register */ +#define PIO_ASR ( 112 ) /* Select A Register */ +#define PIO_BSR ( 116 ) /* Select B Register */ +#define PIO_ABSR ( 120 ) /* AB Select Status Register */ +#define PIO_OWER ( 160 ) /* Output Write Enable Register */ +#define PIO_OWDR ( 164 ) /* Output Write Disable Register */ +#define PIO_OWSR ( 168 ) /* Output Write Status Register */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Clock Generator Controller */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_CKGR structure *** */ +#define CKGR_MOR ( 0 ) /* Main Oscillator Register */ +#define CKGR_MCFR ( 4 ) /* Main Clock Frequency Register */ +#define CKGR_PLLR ( 12 ) /* PLL Register */ +/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */ +#define AT91C_CKGR_MOSCEN ( 0x1 << 0 ) /* (CKGR) Main Oscillator Enable */ +#define AT91C_CKGR_OSCBYPASS ( 0x1 << 1 ) /* (CKGR) Main Oscillator Bypass */ +#define AT91C_CKGR_OSCOUNT ( 0xFF << 8 ) /* (CKGR) Main Oscillator Start-up Time */ +/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */ +#define AT91C_CKGR_MAINF ( 0xFFFF << 0 ) /* (CKGR) Main Clock Frequency */ +#define AT91C_CKGR_MAINRDY ( 0x1 << 16 ) /* (CKGR) Main Clock Ready */ +/* -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- */ +#define AT91C_CKGR_DIV ( 0xFF << 0 ) /* (CKGR) Divider Selected */ +#define AT91C_CKGR_DIV_0 ( 0x0 ) /* (CKGR) Divider output is 0 */ +#define AT91C_CKGR_DIV_BYPASS ( 0x1 ) /* (CKGR) Divider is bypassed */ +#define AT91C_CKGR_PLLCOUNT ( 0x3F << 8 ) /* (CKGR) PLL Counter */ +#define AT91C_CKGR_OUT ( 0x3 << 14 ) /* (CKGR) PLL Output Frequency Range */ +#define AT91C_CKGR_OUT_0 ( 0x0 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_1 ( 0x1 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_2 ( 0x2 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_3 ( 0x3 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_MUL ( 0x7FF << 16 ) /* (CKGR) PLL Multiplier */ +#define AT91C_CKGR_USBDIV ( 0x3 << 28 ) /* (CKGR) Divider for USB Clocks */ +#define AT91C_CKGR_USBDIV_0 ( 0x0 << 28 ) /* (CKGR) Divider output is PLL clock output */ +#define AT91C_CKGR_USBDIV_1 ( 0x1 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 2 */ +#define AT91C_CKGR_USBDIV_2 ( 0x2 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 4 */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Power Management Controller */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_PMC structure *** */ +#define PMC_SCER ( 0 ) /* System Clock Enable Register */ +#define PMC_SCDR ( 4 ) /* System Clock Disable Register */ +#define PMC_SCSR ( 8 ) /* System Clock Status Register */ +#define PMC_PCER ( 16 ) /* Peripheral Clock Enable Register */ +#define PMC_PCDR ( 20 ) /* Peripheral Clock Disable Register */ +#define PMC_PCSR ( 24 ) /* Peripheral Clock Status Register */ +#define PMC_MOR ( 32 ) /* Main Oscillator Register */ +#define PMC_MCFR ( 36 ) /* Main Clock Frequency Register */ +#define PMC_PLLR ( 44 ) /* PLL Register */ +#define PMC_MCKR ( 48 ) /* Master Clock Register */ +#define PMC_PCKR ( 64 ) /* Programmable Clock Register */ +#define PMC_IER ( 96 ) /* Interrupt Enable Register */ +#define PMC_IDR ( 100 ) /* Interrupt Disable Register */ +#define PMC_SR ( 104 ) /* Status Register */ +#define PMC_IMR ( 108 ) /* Interrupt Mask Register */ +/* -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- */ +#define AT91C_PMC_PCK ( 0x1 << 0 ) /* (PMC) Processor Clock */ +#define AT91C_PMC_UDP ( 0x1 << 7 ) /* (PMC) USB Device Port Clock */ +#define AT91C_PMC_PCK0 ( 0x1 << 8 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK1 ( 0x1 << 9 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK2 ( 0x1 << 10 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK3 ( 0x1 << 11 ) /* (PMC) Programmable Clock Output */ +/* -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- */ +/* -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- */ +/* -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- */ +/* -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- */ +/* -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- */ +/* -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */ +#define AT91C_PMC_CSS ( 0x3 << 0 ) /* (PMC) Programmable Clock Selection */ +#define AT91C_PMC_CSS_SLOW_CLK ( 0x0 ) /* (PMC) Slow Clock is selected */ +#define AT91C_PMC_CSS_MAIN_CLK ( 0x1 ) /* (PMC) Main Clock is selected */ +#define AT91C_PMC_CSS_PLL_CLK ( 0x3 ) /* (PMC) Clock from PLL is selected */ +#define AT91C_PMC_PRES ( 0x7 << 2 ) /* (PMC) Programmable Clock Prescaler */ +#define AT91C_PMC_PRES_CLK ( 0x0 << 2 ) /* (PMC) Selected clock */ +#define AT91C_PMC_PRES_CLK_2 ( 0x1 << 2 ) /* (PMC) Selected clock divided by 2 */ +#define AT91C_PMC_PRES_CLK_4 ( 0x2 << 2 ) /* (PMC) Selected clock divided by 4 */ +#define AT91C_PMC_PRES_CLK_8 ( 0x3 << 2 ) /* (PMC) Selected clock divided by 8 */ +#define AT91C_PMC_PRES_CLK_16 ( 0x4 << 2 ) /* (PMC) Selected clock divided by 16 */ +#define AT91C_PMC_PRES_CLK_32 ( 0x5 << 2 ) /* (PMC) Selected clock divided by 32 */ +#define AT91C_PMC_PRES_CLK_64 ( 0x6 << 2 ) /* (PMC) Selected clock divided by 64 */ +/* -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- */ +/* -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- */ +#define AT91C_PMC_MOSCS ( 0x1 << 0 ) /* (PMC) MOSC Status/Enable/Disable/Mask */ +#define AT91C_PMC_LOCK ( 0x1 << 2 ) /* (PMC) PLL Status/Enable/Disable/Mask */ +#define AT91C_PMC_MCKRDY ( 0x1 << 3 ) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK0RDY ( 0x1 << 8 ) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK1RDY ( 0x1 << 9 ) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK2RDY ( 0x1 << 10 ) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK3RDY ( 0x1 << 11 ) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */ +/* -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */ +/* -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- */ +/* -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Reset Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_RSTC structure *** */ +#define RSTC_RCR ( 0 ) /* Reset Control Register */ +#define RSTC_RSR ( 4 ) /* Reset Status Register */ +#define RSTC_RMR ( 8 ) /* Reset Mode Register */ +/* -------- SYSC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- */ +#define AT91C_SYSC_PROCRST ( 0x1 << 0 ) /* (RSTC) Processor Reset */ +#define AT91C_SYSC_ICERST ( 0x1 << 1 ) /* (RSTC) ICE Interface Reset */ +#define AT91C_SYSC_PERRST ( 0x1 << 2 ) /* (RSTC) Peripheral Reset */ +#define AT91C_SYSC_EXTRST ( 0x1 << 3 ) /* (RSTC) External Reset */ +#define AT91C_SYSC_KEY ( 0xFF << 24 ) /* (RSTC) Password */ +/* -------- SYSC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- */ +#define AT91C_SYSC_URSTS ( 0x1 << 0 ) /* (RSTC) User Reset Status */ +#define AT91C_SYSC_BODSTS ( 0x1 << 1 ) /* (RSTC) Brown-out Detection Status */ +#define AT91C_SYSC_RSTTYP ( 0x7 << 8 ) /* (RSTC) Reset Type */ +#define AT91C_SYSC_RSTTYP_POWERUP ( 0x0 << 8 ) /* (RSTC) Power-up Reset. VDDCORE rising. */ +#define AT91C_SYSC_RSTTYP_WATCHDOG ( 0x2 << 8 ) /* (RSTC) Watchdog Reset. Watchdog overflow occurred. */ +#define AT91C_SYSC_RSTTYP_SOFTWARE ( 0x3 << 8 ) /* (RSTC) Software Reset. Processor reset required by the software. */ +#define AT91C_SYSC_RSTTYP_USER ( 0x4 << 8 ) /* (RSTC) User Reset. NRST pin detected low. */ +#define AT91C_SYSC_RSTTYP_BROWNOUT ( 0x5 << 8 ) /* (RSTC) Brown-out Reset. */ +#define AT91C_SYSC_NRSTL ( 0x1 << 16 ) /* (RSTC) NRST pin level */ +#define AT91C_SYSC_SRCMP ( 0x1 << 17 ) /* (RSTC) Software Reset Command in Progress. */ +/* -------- SYSC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- */ +#define AT91C_SYSC_URSTEN ( 0x1 << 0 ) /* (RSTC) User Reset Enable */ +#define AT91C_SYSC_URSTIEN ( 0x1 << 4 ) /* (RSTC) User Reset Interrupt Enable */ +#define AT91C_SYSC_ERSTL ( 0xF << 8 ) /* (RSTC) User Reset Enable */ +#define AT91C_SYSC_BODIEN ( 0x1 << 16 ) /* (RSTC) Brown-out Detection Interrupt Enable */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_RTTC structure *** */ +#define RTTC_RTMR ( 0 ) /* Real-time Mode Register */ +#define RTTC_RTAR ( 4 ) /* Real-time Alarm Register */ +#define RTTC_RTVR ( 8 ) /* Real-time Value Register */ +#define RTTC_RTSR ( 12 ) /* Real-time Status Register */ +/* -------- SYSC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- */ +#define AT91C_SYSC_RTPRES ( 0xFFFF << 0 ) /* (RTTC) Real-time Timer Prescaler Value */ +#define AT91C_SYSC_ALMIEN ( 0x1 << 16 ) /* (RTTC) Alarm Interrupt Enable */ +#define AT91C_SYSC_RTTINCIEN ( 0x1 << 17 ) /* (RTTC) Real Time Timer Increment Interrupt Enable */ +#define AT91C_SYSC_RTTRST ( 0x1 << 18 ) /* (RTTC) Real Time Timer Restart */ +/* -------- SYSC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- */ +#define AT91C_SYSC_ALMV ( 0x0 << 0 ) /* (RTTC) Alarm Value */ +/* -------- SYSC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- */ +#define AT91C_SYSC_CRTV ( 0x0 << 0 ) /* (RTTC) Current Real-time Value */ +/* -------- SYSC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- */ +#define AT91C_SYSC_ALMS ( 0x1 << 0 ) /* (RTTC) Real-time Alarm Status */ +#define AT91C_SYSC_RTTINC ( 0x1 << 1 ) /* (RTTC) Real-time Timer Increment */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_PITC structure *** */ +#define PITC_PIMR ( 0 ) /* Period Interval Mode Register */ +#define PITC_PISR ( 4 ) /* Period Interval Status Register */ +#define PITC_PIVR ( 8 ) /* Period Interval Value Register */ +#define PITC_PIIR ( 12 ) /* Period Interval Image Register */ +/* -------- SYSC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- */ +#define AT91C_SYSC_PIV ( 0xFFFFF << 0 ) /* (PITC) Periodic Interval Value */ +#define AT91C_SYSC_PITEN ( 0x1 << 24 ) /* (PITC) Periodic Interval Timer Enabled */ +#define AT91C_SYSC_PITIEN ( 0x1 << 25 ) /* (PITC) Periodic Interval Timer Interrupt Enable */ +/* -------- SYSC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- */ +#define AT91C_SYSC_PITS ( 0x1 << 0 ) /* (PITC) Periodic Interval Timer Status */ +/* -------- SYSC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- */ +#define AT91C_SYSC_CPIV ( 0xFFFFF << 0 ) /* (PITC) Current Periodic Interval Value */ +#define AT91C_SYSC_PICNT ( 0xFFF << 20 ) /* (PITC) Periodic Interval Counter */ +/* -------- SYSC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_WDTC structure *** */ +#define WDTC_WDCR ( 0 ) /* Watchdog Control Register */ +#define WDTC_WDMR ( 4 ) /* Watchdog Mode Register */ +#define WDTC_WDSR ( 8 ) /* Watchdog Status Register */ +/* -------- SYSC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- */ +#define AT91C_SYSC_WDRSTT ( 0x1 << 0 ) /* (WDTC) Watchdog Restart */ +/* -------- SYSC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */ +#define AT91C_SYSC_WDV ( 0xFFF << 0 ) /* (WDTC) Watchdog Timer Restart */ +#define AT91C_SYSC_WDFIEN ( 0x1 << 12 ) /* (WDTC) Watchdog Fault Interrupt Enable */ +#define AT91C_SYSC_WDRSTEN ( 0x1 << 13 ) /* (WDTC) Watchdog Reset Enable */ +#define AT91C_SYSC_WDRPROC ( 0x1 << 14 ) /* (WDTC) Watchdog Timer Restart */ +#define AT91C_SYSC_WDDIS ( 0x1 << 15 ) /* (WDTC) Watchdog Disable */ +#define AT91C_SYSC_WDD ( 0xFFF << 16 ) /* (WDTC) Watchdog Delta Value */ +#define AT91C_SYSC_WDDBGHLT ( 0x1 << 28 ) /* (WDTC) Watchdog Debug Halt */ +#define AT91C_SYSC_WDIDLEHLT ( 0x1 << 29 ) /* (WDTC) Watchdog Idle Halt */ +/* -------- SYSC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- */ +#define AT91C_SYSC_WDUNF ( 0x1 << 0 ) /* (WDTC) Watchdog Underflow */ +#define AT91C_SYSC_WDERR ( 0x1 << 1 ) /* (WDTC) Watchdog Error */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Memory Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_MC structure *** */ +#define MC_RCR ( 0 ) /* MC Remap Control Register */ +#define MC_ASR ( 4 ) /* MC Abort Status Register */ +#define MC_AASR ( 8 ) /* MC Abort Address Status Register */ +#define MC_FMR ( 96 ) /* MC Flash Mode Register */ +#define MC_FCR ( 100 ) /* MC Flash Command Register */ +#define MC_FSR ( 104 ) /* MC Flash Status Register */ +/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */ +#define AT91C_MC_RCB ( 0x1 << 0 ) /* (MC) Remap Command Bit */ +/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */ +#define AT91C_MC_UNDADD ( 0x1 << 0 ) /* (MC) Undefined Address Abort Status */ +#define AT91C_MC_MISADD ( 0x1 << 1 ) /* (MC) Misaligned Address Abort Status */ +#define AT91C_MC_ABTSZ ( 0x3 << 8 ) /* (MC) Abort Size Status */ +#define AT91C_MC_ABTSZ_BYTE ( 0x0 << 8 ) /* (MC) Byte */ +#define AT91C_MC_ABTSZ_HWORD ( 0x1 << 8 ) /* (MC) Half-word */ +#define AT91C_MC_ABTSZ_WORD ( 0x2 << 8 ) /* (MC) Word */ +#define AT91C_MC_ABTTYP ( 0x3 << 10 ) /* (MC) Abort Type Status */ +#define AT91C_MC_ABTTYP_DATAR ( 0x0 << 10 ) /* (MC) Data Read */ +#define AT91C_MC_ABTTYP_DATAW ( 0x1 << 10 ) /* (MC) Data Write */ +#define AT91C_MC_ABTTYP_FETCH ( 0x2 << 10 ) /* (MC) Code Fetch */ +#define AT91C_MC_MST0 ( 0x1 << 16 ) /* (MC) Master 0 Abort Source */ +#define AT91C_MC_MST1 ( 0x1 << 17 ) /* (MC) Master 1 Abort Source */ +#define AT91C_MC_SVMST0 ( 0x1 << 24 ) /* (MC) Saved Master 0 Abort Source */ +#define AT91C_MC_SVMST1 ( 0x1 << 25 ) /* (MC) Saved Master 1 Abort Source */ +/* -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- */ +#define AT91C_MC_FRDY ( 0x1 << 0 ) /* (MC) Flash Ready */ +#define AT91C_MC_LOCKE ( 0x1 << 2 ) /* (MC) Lock Error */ +#define AT91C_MC_PROGE ( 0x1 << 3 ) /* (MC) Programming Error */ +#define AT91C_MC_NEBP ( 0x1 << 7 ) /* (MC) No Erase Before Programming */ +#define AT91C_MC_FWS ( 0x3 << 8 ) /* (MC) Flash Wait State */ +#define AT91C_MC_FWS_0FWS ( 0x0 << 8 ) /* (MC) 1 cycle for Read, 2 for Write operations */ +#define AT91C_MC_FWS_1FWS ( 0x1 << 8 ) /* (MC) 2 cycles for Read, 3 for Write operations */ +#define AT91C_MC_FWS_2FWS ( 0x2 << 8 ) /* (MC) 3 cycles for Read, 4 for Write operations */ +#define AT91C_MC_FWS_3FWS ( 0x3 << 8 ) /* (MC) 4 cycles for Read, 4 for Write operations */ +#define AT91C_MC_FMCN ( 0xFF << 16 ) /* (MC) Flash Microsecond Cycle Number */ +/* -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- */ +#define AT91C_MC_FCMD ( 0xF << 0 ) /* (MC) Flash Command */ +#define AT91C_MC_FCMD_START_PROG ( 0x1 ) /* (MC) Starts the programming of th epage specified by PAGEN. */ +#define AT91C_MC_FCMD_LOCK ( 0x2 ) /* (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */ +#define AT91C_MC_FCMD_PROG_AND_LOCK ( 0x3 ) /* (MC) The lock sequence automatically happens after the programming sequence is completed. */ +#define AT91C_MC_FCMD_UNLOCK ( 0x4 ) /* (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */ +#define AT91C_MC_FCMD_ERASE_ALL ( 0x8 ) /* (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. */ +#define AT91C_MC_FCMD_SET_GP_NVM ( 0xB ) /* (MC) Set General Purpose NVM bits. */ +#define AT91C_MC_FCMD_CLR_GP_NVM ( 0xD ) /* (MC) Clear General Purpose NVM bits. */ +#define AT91C_MC_FCMD_SET_SECURITY ( 0xF ) /* (MC) Set Security Bit. */ +#define AT91C_MC_PAGEN ( 0x3FF << 8 ) /* (MC) Page Number */ +#define AT91C_MC_KEY ( 0xFF << 24 ) /* (MC) Writing Protect Key */ +/* -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- */ +#define AT91C_MC_SECURITY ( 0x1 << 4 ) /* (MC) Security Bit Status */ +#define AT91C_MC_GPNVM0 ( 0x1 << 8 ) /* (MC) Sector 0 Lock Status */ +#define AT91C_MC_GPNVM1 ( 0x1 << 9 ) /* (MC) Sector 1 Lock Status */ +#define AT91C_MC_GPNVM2 ( 0x1 << 10 ) /* (MC) Sector 2 Lock Status */ +#define AT91C_MC_GPNVM3 ( 0x1 << 11 ) /* (MC) Sector 3 Lock Status */ +#define AT91C_MC_GPNVM4 ( 0x1 << 12 ) /* (MC) Sector 4 Lock Status */ +#define AT91C_MC_GPNVM5 ( 0x1 << 13 ) /* (MC) Sector 5 Lock Status */ +#define AT91C_MC_GPNVM6 ( 0x1 << 14 ) /* (MC) Sector 6 Lock Status */ +#define AT91C_MC_GPNVM7 ( 0x1 << 15 ) /* (MC) Sector 7 Lock Status */ +#define AT91C_MC_LOCKS0 ( 0x1 << 16 ) /* (MC) Sector 0 Lock Status */ +#define AT91C_MC_LOCKS1 ( 0x1 << 17 ) /* (MC) Sector 1 Lock Status */ +#define AT91C_MC_LOCKS2 ( 0x1 << 18 ) /* (MC) Sector 2 Lock Status */ +#define AT91C_MC_LOCKS3 ( 0x1 << 19 ) /* (MC) Sector 3 Lock Status */ +#define AT91C_MC_LOCKS4 ( 0x1 << 20 ) /* (MC) Sector 4 Lock Status */ +#define AT91C_MC_LOCKS5 ( 0x1 << 21 ) /* (MC) Sector 5 Lock Status */ +#define AT91C_MC_LOCKS6 ( 0x1 << 22 ) /* (MC) Sector 6 Lock Status */ +#define AT91C_MC_LOCKS7 ( 0x1 << 23 ) /* (MC) Sector 7 Lock Status */ +#define AT91C_MC_LOCKS8 ( 0x1 << 24 ) /* (MC) Sector 8 Lock Status */ +#define AT91C_MC_LOCKS9 ( 0x1 << 25 ) /* (MC) Sector 9 Lock Status */ +#define AT91C_MC_LOCKS10 ( 0x1 << 26 ) /* (MC) Sector 10 Lock Status */ +#define AT91C_MC_LOCKS11 ( 0x1 << 27 ) /* (MC) Sector 11 Lock Status */ +#define AT91C_MC_LOCKS12 ( 0x1 << 28 ) /* (MC) Sector 12 Lock Status */ +#define AT91C_MC_LOCKS13 ( 0x1 << 29 ) /* (MC) Sector 13 Lock Status */ +#define AT91C_MC_LOCKS14 ( 0x1 << 30 ) /* (MC) Sector 14 Lock Status */ +#define AT91C_MC_LOCKS15 ( 0x1 << 31 ) /* (MC) Sector 15 Lock Status */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_SPI structure *** */ +#define SPI_CR ( 0 ) /* Control Register */ +#define SPI_MR ( 4 ) /* Mode Register */ +#define SPI_RDR ( 8 ) /* Receive Data Register */ +#define SPI_TDR ( 12 ) /* Transmit Data Register */ +#define SPI_SR ( 16 ) /* Status Register */ +#define SPI_IER ( 20 ) /* Interrupt Enable Register */ +#define SPI_IDR ( 24 ) /* Interrupt Disable Register */ +#define SPI_IMR ( 28 ) /* Interrupt Mask Register */ +#define SPI_CSR ( 48 ) /* Chip Select Register */ +#define SPI_RPR ( 256 ) /* Receive Pointer Register */ +#define SPI_RCR ( 260 ) /* Receive Counter Register */ +#define SPI_TPR ( 264 ) /* Transmit Pointer Register */ +#define SPI_TCR ( 268 ) /* Transmit Counter Register */ +#define SPI_RNPR ( 272 ) /* Receive Next Pointer Register */ +#define SPI_RNCR ( 276 ) /* Receive Next Counter Register */ +#define SPI_TNPR ( 280 ) /* Transmit Next Pointer Register */ +#define SPI_TNCR ( 284 ) /* Transmit Next Counter Register */ +#define SPI_PTCR ( 288 ) /* PDC Transfer Control Register */ +#define SPI_PTSR ( 292 ) /* PDC Transfer Status Register */ +/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */ +#define AT91C_SPI_SPIEN ( 0x1 << 0 ) /* (SPI) SPI Enable */ +#define AT91C_SPI_SPIDIS ( 0x1 << 1 ) /* (SPI) SPI Disable */ +#define AT91C_SPI_SWRST ( 0x1 << 7 ) /* (SPI) SPI Software reset */ +#define AT91C_SPI_LASTXFER ( 0x1 << 24 ) /* (SPI) SPI Last Transfer */ +/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */ +#define AT91C_SPI_MSTR ( 0x1 << 0 ) /* (SPI) Master/Slave Mode */ +#define AT91C_SPI_PS ( 0x1 << 1 ) /* (SPI) Peripheral Select */ +#define AT91C_SPI_PS_FIXED ( 0x0 << 1 ) /* (SPI) Fixed Peripheral Select */ +#define AT91C_SPI_PS_VARIABLE ( 0x1 << 1 ) /* (SPI) Variable Peripheral Select */ +#define AT91C_SPI_PCSDEC ( 0x1 << 2 ) /* (SPI) Chip Select Decode */ +#define AT91C_SPI_FDIV ( 0x1 << 3 ) /* (SPI) Clock Selection */ +#define AT91C_SPI_MODFDIS ( 0x1 << 4 ) /* (SPI) Mode Fault Detection */ +#define AT91C_SPI_LLB ( 0x1 << 7 ) /* (SPI) Clock Selection */ +#define AT91C_SPI_PCS ( 0xF << 16 ) /* (SPI) Peripheral Chip Select */ +#define AT91C_SPI_DLYBCS ( 0xFF << 24 ) /* (SPI) Delay Between Chip Selects */ +/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */ +#define AT91C_SPI_RD ( 0xFFFF << 0 ) /* (SPI) Receive Data */ +#define AT91C_SPI_RPCS ( 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */ +/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */ +#define AT91C_SPI_TD ( 0xFFFF << 0 ) /* (SPI) Transmit Data */ +#define AT91C_SPI_TPCS ( 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */ +/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ +#define AT91C_SPI_RDRF ( 0x1 << 0 ) /* (SPI) Receive Data Register Full */ +#define AT91C_SPI_TDRE ( 0x1 << 1 ) /* (SPI) Transmit Data Register Empty */ +#define AT91C_SPI_MODF ( 0x1 << 2 ) /* (SPI) Mode Fault Error */ +#define AT91C_SPI_OVRES ( 0x1 << 3 ) /* (SPI) Overrun Error Status */ +#define AT91C_SPI_ENDRX ( 0x1 << 4 ) /* (SPI) End of Receiver Transfer */ +#define AT91C_SPI_ENDTX ( 0x1 << 5 ) /* (SPI) End of Receiver Transfer */ +#define AT91C_SPI_RXBUFF ( 0x1 << 6 ) /* (SPI) RXBUFF Interrupt */ +#define AT91C_SPI_TXBUFE ( 0x1 << 7 ) /* (SPI) TXBUFE Interrupt */ +#define AT91C_SPI_NSSR ( 0x1 << 8 ) /* (SPI) NSSR Interrupt */ +#define AT91C_SPI_TXEMPTY ( 0x1 << 9 ) /* (SPI) TXEMPTY Interrupt */ +#define AT91C_SPI_SPIENS ( 0x1 << 16 ) /* (SPI) Enable Status */ +/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ +/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ +/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */ +/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */ +#define AT91C_SPI_CPOL ( 0x1 << 0 ) /* (SPI) Clock Polarity */ +#define AT91C_SPI_NCPHA ( 0x1 << 1 ) /* (SPI) Clock Phase */ +#define AT91C_SPI_CSAAT ( 0x1 << 2 ) /* (SPI) Chip Select Active After Transfer */ +#define AT91C_SPI_BITS ( 0xF << 4 ) /* (SPI) Bits Per Transfer */ +#define AT91C_SPI_BITS_8 ( 0x0 << 4 ) /* (SPI) 8 Bits Per transfer */ +#define AT91C_SPI_BITS_9 ( 0x1 << 4 ) /* (SPI) 9 Bits Per transfer */ +#define AT91C_SPI_BITS_10 ( 0x2 << 4 ) /* (SPI) 10 Bits Per transfer */ +#define AT91C_SPI_BITS_11 ( 0x3 << 4 ) /* (SPI) 11 Bits Per transfer */ +#define AT91C_SPI_BITS_12 ( 0x4 << 4 ) /* (SPI) 12 Bits Per transfer */ +#define AT91C_SPI_BITS_13 ( 0x5 << 4 ) /* (SPI) 13 Bits Per transfer */ +#define AT91C_SPI_BITS_14 ( 0x6 << 4 ) /* (SPI) 14 Bits Per transfer */ +#define AT91C_SPI_BITS_15 ( 0x7 << 4 ) /* (SPI) 15 Bits Per transfer */ +#define AT91C_SPI_BITS_16 ( 0x8 << 4 ) /* (SPI) 16 Bits Per transfer */ +#define AT91C_SPI_SCBR ( 0xFF << 8 ) /* (SPI) Serial Clock Baud Rate */ +#define AT91C_SPI_DLYBS ( 0xFF << 16 ) /* (SPI) Serial Clock Baud Rate */ +#define AT91C_SPI_DLYBCT ( 0xFF << 24 ) /* (SPI) Delay Between Consecutive Transfers */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Analog to Digital Convertor */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_ADC structure *** */ +#define ADC_CR ( 0 ) /* ADC Control Register */ +#define ADC_MR ( 4 ) /* ADC Mode Register */ +#define ADC_CHER ( 16 ) /* ADC Channel Enable Register */ +#define ADC_CHDR ( 20 ) /* ADC Channel Disable Register */ +#define ADC_CHSR ( 24 ) /* ADC Channel Status Register */ +#define ADC_SR ( 28 ) /* ADC Status Register */ +#define ADC_LCDR ( 32 ) /* ADC Last Converted Data Register */ +#define ADC_IER ( 36 ) /* ADC Interrupt Enable Register */ +#define ADC_IDR ( 40 ) /* ADC Interrupt Disable Register */ +#define ADC_IMR ( 44 ) /* ADC Interrupt Mask Register */ +#define ADC_CDR0 ( 48 ) /* ADC Channel Data Register 0 */ +#define ADC_CDR1 ( 52 ) /* ADC Channel Data Register 1 */ +#define ADC_CDR2 ( 56 ) /* ADC Channel Data Register 2 */ +#define ADC_CDR3 ( 60 ) /* ADC Channel Data Register 3 */ +#define ADC_CDR4 ( 64 ) /* ADC Channel Data Register 4 */ +#define ADC_CDR5 ( 68 ) /* ADC Channel Data Register 5 */ +#define ADC_CDR6 ( 72 ) /* ADC Channel Data Register 6 */ +#define ADC_CDR7 ( 76 ) /* ADC Channel Data Register 7 */ +#define ADC_RPR ( 256 ) /* Receive Pointer Register */ +#define ADC_RCR ( 260 ) /* Receive Counter Register */ +#define ADC_TPR ( 264 ) /* Transmit Pointer Register */ +#define ADC_TCR ( 268 ) /* Transmit Counter Register */ +#define ADC_RNPR ( 272 ) /* Receive Next Pointer Register */ +#define ADC_RNCR ( 276 ) /* Receive Next Counter Register */ +#define ADC_TNPR ( 280 ) /* Transmit Next Pointer Register */ +#define ADC_TNCR ( 284 ) /* Transmit Next Counter Register */ +#define ADC_PTCR ( 288 ) /* PDC Transfer Control Register */ +#define ADC_PTSR ( 292 ) /* PDC Transfer Status Register */ +/* -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- */ +#define AT91C_ADC_SWRST ( 0x1 << 0 ) /* (ADC) Software Reset */ +#define AT91C_ADC_START ( 0x1 << 1 ) /* (ADC) Start Conversion */ +/* -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- */ +#define AT91C_ADC_TRGEN ( 0x1 << 0 ) /* (ADC) Trigger Enable */ +#define AT91C_ADC_TRGEN_DIS ( 0x0 ) /* (ADC) Hardware triggers are disabled. Starting a conversion is only possible by software */ +#define AT91C_ADC_TRGEN_EN ( 0x1 ) /* (ADC) Hardware trigger selected by TRGSEL field is enabled. */ +#define AT91C_ADC_TRGSEL ( 0x7 << 1 ) /* (ADC) Trigger Selection */ +#define AT91C_ADC_TRGSEL_TIOA0 ( 0x0 << 1 ) /* (ADC) Selected TRGSEL = TIAO0 */ +#define AT91C_ADC_TRGSEL_TIOA1 ( 0x1 << 1 ) /* (ADC) Selected TRGSEL = TIAO1 */ +#define AT91C_ADC_TRGSEL_TIOA2 ( 0x2 << 1 ) /* (ADC) Selected TRGSEL = TIAO2 */ +#define AT91C_ADC_TRGSEL_TIOA3 ( 0x3 << 1 ) /* (ADC) Selected TRGSEL = TIAO3 */ +#define AT91C_ADC_TRGSEL_TIOA4 ( 0x4 << 1 ) /* (ADC) Selected TRGSEL = TIAO4 */ +#define AT91C_ADC_TRGSEL_TIOA5 ( 0x5 << 1 ) /* (ADC) Selected TRGSEL = TIAO5 */ +#define AT91C_ADC_TRGSEL_EXT ( 0x6 << 1 ) /* (ADC) Selected TRGSEL = External Trigger */ +#define AT91C_ADC_LOWRES ( 0x1 << 4 ) /* (ADC) Resolution. */ +#define AT91C_ADC_LOWRES_10_BIT ( 0x0 << 4 ) /* (ADC) 10-bit resolution */ +#define AT91C_ADC_LOWRES_8_BIT ( 0x1 << 4 ) /* (ADC) 8-bit resolution */ +#define AT91C_ADC_SLEEP ( 0x1 << 5 ) /* (ADC) Sleep Mode */ +#define AT91C_ADC_SLEEP_NORMAL_MODE ( 0x0 << 5 ) /* (ADC) Normal Mode */ +#define AT91C_ADC_SLEEP_MODE ( 0x1 << 5 ) /* (ADC) Sleep Mode */ +#define AT91C_ADC_PRESCAL ( 0x3F << 8 ) /* (ADC) Prescaler rate selection */ +#define AT91C_ADC_STARTUP ( 0x1F << 16 ) /* (ADC) Startup Time */ +#define AT91C_ADC_SHTIM ( 0xF << 24 ) /* (ADC) Sample & Hold Time */ +/* -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- */ +#define AT91C_ADC_CH0 ( 0x1 << 0 ) /* (ADC) Channel 0 */ +#define AT91C_ADC_CH1 ( 0x1 << 1 ) /* (ADC) Channel 1 */ +#define AT91C_ADC_CH2 ( 0x1 << 2 ) /* (ADC) Channel 2 */ +#define AT91C_ADC_CH3 ( 0x1 << 3 ) /* (ADC) Channel 3 */ +#define AT91C_ADC_CH4 ( 0x1 << 4 ) /* (ADC) Channel 4 */ +#define AT91C_ADC_CH5 ( 0x1 << 5 ) /* (ADC) Channel 5 */ +#define AT91C_ADC_CH6 ( 0x1 << 6 ) /* (ADC) Channel 6 */ +#define AT91C_ADC_CH7 ( 0x1 << 7 ) /* (ADC) Channel 7 */ +/* -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- */ +/* -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- */ +/* -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- */ +#define AT91C_ADC_EOC0 ( 0x1 << 0 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC1 ( 0x1 << 1 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC2 ( 0x1 << 2 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC3 ( 0x1 << 3 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC4 ( 0x1 << 4 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC5 ( 0x1 << 5 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC6 ( 0x1 << 6 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC7 ( 0x1 << 7 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_OVRE0 ( 0x1 << 8 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE1 ( 0x1 << 9 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE2 ( 0x1 << 10 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE3 ( 0x1 << 11 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE4 ( 0x1 << 12 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE5 ( 0x1 << 13 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE6 ( 0x1 << 14 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE7 ( 0x1 << 15 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_DRDY ( 0x1 << 16 ) /* (ADC) Data Ready */ +#define AT91C_ADC_GOVRE ( 0x1 << 17 ) /* (ADC) General Overrun */ +#define AT91C_ADC_ENDRX ( 0x1 << 18 ) /* (ADC) End of Receiver Transfer */ +#define AT91C_ADC_RXBUFF ( 0x1 << 19 ) /* (ADC) RXBUFF Interrupt */ +/* -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- */ +#define AT91C_ADC_LDATA ( 0x3FF << 0 ) /* (ADC) Last Data Converted */ +/* -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- */ +/* -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- */ +/* -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- */ +/* -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- */ +#define AT91C_ADC_DATA ( 0x3FF << 0 ) /* (ADC) Converted Data */ +/* -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- */ +/* -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- */ +/* -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- */ +/* -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- */ +/* -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- */ +/* -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- */ +/* -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_SSC structure *** */ +#define SSC_CR ( 0 ) /* Control Register */ +#define SSC_CMR ( 4 ) /* Clock Mode Register */ +#define SSC_RCMR ( 16 ) /* Receive Clock ModeRegister */ +#define SSC_RFMR ( 20 ) /* Receive Frame Mode Register */ +#define SSC_TCMR ( 24 ) /* Transmit Clock Mode Register */ +#define SSC_TFMR ( 28 ) /* Transmit Frame Mode Register */ +#define SSC_RHR ( 32 ) /* Receive Holding Register */ +#define SSC_THR ( 36 ) /* Transmit Holding Register */ +#define SSC_RSHR ( 48 ) /* Receive Sync Holding Register */ +#define SSC_TSHR ( 52 ) /* Transmit Sync Holding Register */ +#define SSC_RC0R ( 56 ) /* Receive Compare 0 Register */ +#define SSC_RC1R ( 60 ) /* Receive Compare 1 Register */ +#define SSC_SR ( 64 ) /* Status Register */ +#define SSC_IER ( 68 ) /* Interrupt Enable Register */ +#define SSC_IDR ( 72 ) /* Interrupt Disable Register */ +#define SSC_IMR ( 76 ) /* Interrupt Mask Register */ +#define SSC_RPR ( 256 ) /* Receive Pointer Register */ +#define SSC_RCR ( 260 ) /* Receive Counter Register */ +#define SSC_TPR ( 264 ) /* Transmit Pointer Register */ +#define SSC_TCR ( 268 ) /* Transmit Counter Register */ +#define SSC_RNPR ( 272 ) /* Receive Next Pointer Register */ +#define SSC_RNCR ( 276 ) /* Receive Next Counter Register */ +#define SSC_TNPR ( 280 ) /* Transmit Next Pointer Register */ +#define SSC_TNCR ( 284 ) /* Transmit Next Counter Register */ +#define SSC_PTCR ( 288 ) /* PDC Transfer Control Register */ +#define SSC_PTSR ( 292 ) /* PDC Transfer Status Register */ +/* -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- */ +#define AT91C_SSC_RXEN ( 0x1 << 0 ) /* (SSC) Receive Enable */ +#define AT91C_SSC_RXDIS ( 0x1 << 1 ) /* (SSC) Receive Disable */ +#define AT91C_SSC_TXEN ( 0x1 << 8 ) /* (SSC) Transmit Enable */ +#define AT91C_SSC_TXDIS ( 0x1 << 9 ) /* (SSC) Transmit Disable */ +#define AT91C_SSC_SWRST ( 0x1 << 15 ) /* (SSC) Software Reset */ +/* -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- */ +#define AT91C_SSC_CKS ( 0x3 << 0 ) /* (SSC) Receive/Transmit Clock Selection */ +#define AT91C_SSC_CKS_DIV ( 0x0 ) /* (SSC) Divided Clock */ +#define AT91C_SSC_CKS_TK ( 0x1 ) /* (SSC) TK Clock signal */ +#define AT91C_SSC_CKS_RK ( 0x2 ) /* (SSC) RK pin */ +#define AT91C_SSC_CKO ( 0x7 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode Selection */ +#define AT91C_SSC_CKO_NONE ( 0x0 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only */ +#define AT91C_SSC_CKO_CONTINUOUS ( 0x1 << 2 ) /* (SSC) Continuous Receive/Transmit Clock RK pin: Output */ +#define AT91C_SSC_CKO_DATA_TX ( 0x2 << 2 ) /* (SSC) Receive/Transmit Clock only during data transfers RK pin: Output */ +#define AT91C_SSC_CKI ( 0x1 << 5 ) /* (SSC) Receive/Transmit Clock Inversion */ +#define AT91C_SSC_CKG ( 0x3 << 6 ) /* (SSC) Receive/Transmit Clock Gating Selection */ +#define AT91C_SSC_CKG_NONE ( 0x0 << 6 ) /* (SSC) Receive/Transmit Clock Gating: None, continuous clock */ +#define AT91C_SSC_CKG_LOW ( 0x1 << 6 ) /* (SSC) Receive/Transmit Clock enabled only if RF Low */ +#define AT91C_SSC_CKG_HIGH ( 0x2 << 6 ) /* (SSC) Receive/Transmit Clock enabled only if RF High */ +#define AT91C_SSC_START ( 0xF << 8 ) /* (SSC) Receive/Transmit Start Selection */ +#define AT91C_SSC_START_CONTINUOUS ( 0x0 << 8 ) /* (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */ +#define AT91C_SSC_START_TX ( 0x1 << 8 ) /* (SSC) Transmit/Receive start */ +#define AT91C_SSC_START_LOW_RF ( 0x2 << 8 ) /* (SSC) Detection of a low level on RF input */ +#define AT91C_SSC_START_HIGH_RF ( 0x3 << 8 ) /* (SSC) Detection of a high level on RF input */ +#define AT91C_SSC_START_FALL_RF ( 0x4 << 8 ) /* (SSC) Detection of a falling edge on RF input */ +#define AT91C_SSC_START_RISE_RF ( 0x5 << 8 ) /* (SSC) Detection of a rising edge on RF input */ +#define AT91C_SSC_START_LEVEL_RF ( 0x6 << 8 ) /* (SSC) Detection of any level change on RF input */ +#define AT91C_SSC_START_EDGE_RF ( 0x7 << 8 ) /* (SSC) Detection of any edge on RF input */ +#define AT91C_SSC_START_0 ( 0x8 << 8 ) /* (SSC) Compare 0 */ +#define AT91C_SSC_STOP ( 0x1 << 12 ) /* (SSC) Receive Stop Selection */ +#define AT91C_SSC_STTOUT ( 0x1 << 15 ) /* (SSC) Receive/Transmit Start Output Selection */ +#define AT91C_SSC_STTDLY ( 0xFF << 16 ) /* (SSC) Receive/Transmit Start Delay */ +#define AT91C_SSC_PERIOD ( 0xFF << 24 ) /* (SSC) Receive/Transmit Period Divider Selection */ +/* -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- */ +#define AT91C_SSC_DATLEN ( 0x1F << 0 ) /* (SSC) Data Length */ +#define AT91C_SSC_LOOP ( 0x1 << 5 ) /* (SSC) Loop Mode */ +#define AT91C_SSC_MSBF ( 0x1 << 7 ) /* (SSC) Most Significant Bit First */ +#define AT91C_SSC_DATNB ( 0xF << 8 ) /* (SSC) Data Number per Frame */ +#define AT91C_SSC_FSLEN ( 0xF << 16 ) /* (SSC) Receive/Transmit Frame Sync length */ +#define AT91C_SSC_FSOS ( 0x7 << 20 ) /* (SSC) Receive/Transmit Frame Sync Output Selection */ +#define AT91C_SSC_FSOS_NONE ( 0x0 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only */ +#define AT91C_SSC_FSOS_NEGATIVE ( 0x1 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse */ +#define AT91C_SSC_FSOS_POSITIVE ( 0x2 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse */ +#define AT91C_SSC_FSOS_LOW ( 0x3 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer */ +#define AT91C_SSC_FSOS_HIGH ( 0x4 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer */ +#define AT91C_SSC_FSOS_TOGGLE ( 0x5 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer */ +#define AT91C_SSC_FSEDGE ( 0x1 << 24 ) /* (SSC) Frame Sync Edge Detection */ +/* -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- */ +/* -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- */ +#define AT91C_SSC_DATDEF ( 0x1 << 5 ) /* (SSC) Data Default Value */ +#define AT91C_SSC_FSDEN ( 0x1 << 23 ) /* (SSC) Frame Sync Data Enable */ +/* -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- */ +#define AT91C_SSC_TXRDY ( 0x1 << 0 ) /* (SSC) Transmit Ready */ +#define AT91C_SSC_TXEMPTY ( 0x1 << 1 ) /* (SSC) Transmit Empty */ +#define AT91C_SSC_ENDTX ( 0x1 << 2 ) /* (SSC) End Of Transmission */ +#define AT91C_SSC_TXBUFE ( 0x1 << 3 ) /* (SSC) Transmit Buffer Empty */ +#define AT91C_SSC_RXRDY ( 0x1 << 4 ) /* (SSC) Receive Ready */ +#define AT91C_SSC_OVRUN ( 0x1 << 5 ) /* (SSC) Receive Overrun */ +#define AT91C_SSC_ENDRX ( 0x1 << 6 ) /* (SSC) End of Reception */ +#define AT91C_SSC_RXBUFF ( 0x1 << 7 ) /* (SSC) Receive Buffer Full */ +#define AT91C_SSC_CP0 ( 0x1 << 8 ) /* (SSC) Compare 0 */ +#define AT91C_SSC_CP1 ( 0x1 << 9 ) /* (SSC) Compare 1 */ +#define AT91C_SSC_TXSYN ( 0x1 << 10 ) /* (SSC) Transmit Sync */ +#define AT91C_SSC_RXSYN ( 0x1 << 11 ) /* (SSC) Receive Sync */ +#define AT91C_SSC_TXENA ( 0x1 << 16 ) /* (SSC) Transmit Enable */ +#define AT91C_SSC_RXENA ( 0x1 << 17 ) /* (SSC) Receive Enable */ +/* -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- */ +/* -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- */ +/* -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Usart */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_USART structure *** */ +#define US_CR ( 0 ) /* Control Register */ +#define US_MR ( 4 ) /* Mode Register */ +#define US_IER ( 8 ) /* Interrupt Enable Register */ +#define US_IDR ( 12 ) /* Interrupt Disable Register */ +#define US_IMR ( 16 ) /* Interrupt Mask Register */ +#define US_CSR ( 20 ) /* Channel Status Register */ +#define US_RHR ( 24 ) /* Receiver Holding Register */ +#define US_THR ( 28 ) /* Transmitter Holding Register */ +#define US_BRGR ( 32 ) /* Baud Rate Generator Register */ +#define US_RTOR ( 36 ) /* Receiver Time-out Register */ +#define US_TTGR ( 40 ) /* Transmitter Time-guard Register */ +#define US_FIDI ( 64 ) /* FI_DI_Ratio Register */ +#define US_NER ( 68 ) /* Nb Errors Register */ +#define US_XXR ( 72 ) /* XON_XOFF Register */ +#define US_IF ( 76 ) /* IRDA_FILTER Register */ +#define US_RPR ( 256 ) /* Receive Pointer Register */ +#define US_RCR ( 260 ) /* Receive Counter Register */ +#define US_TPR ( 264 ) /* Transmit Pointer Register */ +#define US_TCR ( 268 ) /* Transmit Counter Register */ +#define US_RNPR ( 272 ) /* Receive Next Pointer Register */ +#define US_RNCR ( 276 ) /* Receive Next Counter Register */ +#define US_TNPR ( 280 ) /* Transmit Next Pointer Register */ +#define US_TNCR ( 284 ) /* Transmit Next Counter Register */ +#define US_PTCR ( 288 ) /* PDC Transfer Control Register */ +#define US_PTSR ( 292 ) /* PDC Transfer Status Register */ +/* -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- */ +#define AT91C_US_RSTSTA ( 0x1 << 8 ) /* (USART) Reset Status Bits */ +#define AT91C_US_STTBRK ( 0x1 << 9 ) /* (USART) Start Break */ +#define AT91C_US_STPBRK ( 0x1 << 10 ) /* (USART) Stop Break */ +#define AT91C_US_STTTO ( 0x1 << 11 ) /* (USART) Start Time-out */ +#define AT91C_US_SENDA ( 0x1 << 12 ) /* (USART) Send Address */ +#define AT91C_US_RSTIT ( 0x1 << 13 ) /* (USART) Reset Iterations */ +#define AT91C_US_RSTNACK ( 0x1 << 14 ) /* (USART) Reset Non Acknowledge */ +#define AT91C_US_RETTO ( 0x1 << 15 ) /* (USART) Rearm Time-out */ +#define AT91C_US_DTREN ( 0x1 << 16 ) /* (USART) Data Terminal ready Enable */ +#define AT91C_US_DTRDIS ( 0x1 << 17 ) /* (USART) Data Terminal ready Disable */ +#define AT91C_US_RTSEN ( 0x1 << 18 ) /* (USART) Request to Send enable */ +#define AT91C_US_RTSDIS ( 0x1 << 19 ) /* (USART) Request to Send Disable */ +/* -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- */ +#define AT91C_US_USMODE ( 0xF << 0 ) /* (USART) Usart mode */ +#define AT91C_US_USMODE_NORMAL ( 0x0 ) /* (USART) Normal */ +#define AT91C_US_USMODE_RS485 ( 0x1 ) /* (USART) RS485 */ +#define AT91C_US_USMODE_HWHSH ( 0x2 ) /* (USART) Hardware Handshaking */ +#define AT91C_US_USMODE_MODEM ( 0x3 ) /* (USART) Modem */ +#define AT91C_US_USMODE_ISO7816_0 ( 0x4 ) /* (USART) ISO7816 protocol: T = 0 */ +#define AT91C_US_USMODE_ISO7816_1 ( 0x6 ) /* (USART) ISO7816 protocol: T = 1 */ +#define AT91C_US_USMODE_IRDA ( 0x8 ) /* (USART) IrDA */ +#define AT91C_US_USMODE_SWHSH ( 0xC ) /* (USART) Software Handshaking */ +#define AT91C_US_CLKS ( 0x3 << 4 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */ +#define AT91C_US_CLKS_CLOCK ( 0x0 << 4 ) /* (USART) Clock */ +#define AT91C_US_CLKS_FDIV1 ( 0x1 << 4 ) /* (USART) fdiv1 */ +#define AT91C_US_CLKS_SLOW ( 0x2 << 4 ) /* (USART) slow_clock (ARM) */ +#define AT91C_US_CLKS_EXT ( 0x3 << 4 ) /* (USART) External (SCK) */ +#define AT91C_US_CHRL ( 0x3 << 6 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */ +#define AT91C_US_CHRL_5_BITS ( 0x0 << 6 ) /* (USART) Character Length: 5 bits */ +#define AT91C_US_CHRL_6_BITS ( 0x1 << 6 ) /* (USART) Character Length: 6 bits */ +#define AT91C_US_CHRL_7_BITS ( 0x2 << 6 ) /* (USART) Character Length: 7 bits */ +#define AT91C_US_CHRL_8_BITS ( 0x3 << 6 ) /* (USART) Character Length: 8 bits */ +#define AT91C_US_SYNC ( 0x1 << 8 ) /* (USART) Synchronous Mode Select */ +#define AT91C_US_NBSTOP ( 0x3 << 12 ) /* (USART) Number of Stop bits */ +#define AT91C_US_NBSTOP_1_BIT ( 0x0 << 12 ) /* (USART) 1 stop bit */ +#define AT91C_US_NBSTOP_15_BIT ( 0x1 << 12 ) /* (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */ +#define AT91C_US_NBSTOP_2_BIT ( 0x2 << 12 ) /* (USART) 2 stop bits */ +#define AT91C_US_MSBF ( 0x1 << 16 ) /* (USART) Bit Order */ +#define AT91C_US_MODE9 ( 0x1 << 17 ) /* (USART) 9-bit Character length */ +#define AT91C_US_CKLO ( 0x1 << 18 ) /* (USART) Clock Output Select */ +#define AT91C_US_OVER ( 0x1 << 19 ) /* (USART) Over Sampling Mode */ +#define AT91C_US_INACK ( 0x1 << 20 ) /* (USART) Inhibit Non Acknowledge */ +#define AT91C_US_DSNACK ( 0x1 << 21 ) /* (USART) Disable Successive NACK */ +#define AT91C_US_MAX_ITER ( 0x1 << 24 ) /* (USART) Number of Repetitions */ +#define AT91C_US_FILTER ( 0x1 << 28 ) /* (USART) Receive Line Filter */ +/* -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ +#define AT91C_US_RXBRK ( 0x1 << 2 ) /* (USART) Break Received/End of Break */ +#define AT91C_US_TIMEOUT ( 0x1 << 8 ) /* (USART) Receiver Time-out */ +#define AT91C_US_ITERATION ( 0x1 << 10 ) /* (USART) Max number of Repetitions Reached */ +#define AT91C_US_NACK ( 0x1 << 13 ) /* (USART) Non Acknowledge */ +#define AT91C_US_RIIC ( 0x1 << 16 ) /* (USART) Ring INdicator Input Change Flag */ +#define AT91C_US_DSRIC ( 0x1 << 17 ) /* (USART) Data Set Ready Input Change Flag */ +#define AT91C_US_DCDIC ( 0x1 << 18 ) /* (USART) Data Carrier Flag */ +#define AT91C_US_CTSIC ( 0x1 << 19 ) /* (USART) Clear To Send Input Change Flag */ +/* -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- */ +/* -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- */ +/* -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- */ +#define AT91C_US_RI ( 0x1 << 20 ) /* (USART) Image of RI Input */ +#define AT91C_US_DSR ( 0x1 << 21 ) /* (USART) Image of DSR Input */ +#define AT91C_US_DCD ( 0x1 << 22 ) /* (USART) Image of DCD Input */ +#define AT91C_US_CTS ( 0x1 << 23 ) /* (USART) Image of CTS Input */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Two-wire Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_TWI structure *** */ +#define TWI_CR ( 0 ) /* Control Register */ +#define TWI_MMR ( 4 ) /* Master Mode Register */ +#define TWI_SMR ( 8 ) /* Slave Mode Register */ +#define TWI_IADR ( 12 ) /* Internal Address Register */ +#define TWI_CWGR ( 16 ) /* Clock Waveform Generator Register */ +#define TWI_SR ( 32 ) /* Status Register */ +#define TWI_IER ( 36 ) /* Interrupt Enable Register */ +#define TWI_IDR ( 40 ) /* Interrupt Disable Register */ +#define TWI_IMR ( 44 ) /* Interrupt Mask Register */ +#define TWI_RHR ( 48 ) /* Receive Holding Register */ +#define TWI_THR ( 52 ) /* Transmit Holding Register */ +/* -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */ +#define AT91C_TWI_START ( 0x1 << 0 ) /* (TWI) Send a START Condition */ +#define AT91C_TWI_STOP ( 0x1 << 1 ) /* (TWI) Send a STOP Condition */ +#define AT91C_TWI_MSEN ( 0x1 << 2 ) /* (TWI) TWI Master Transfer Enabled */ +#define AT91C_TWI_MSDIS ( 0x1 << 3 ) /* (TWI) TWI Master Transfer Disabled */ +#define AT91C_TWI_SVEN ( 0x1 << 4 ) /* (TWI) TWI Slave Transfer Enabled */ +#define AT91C_TWI_SVDIS ( 0x1 << 5 ) /* (TWI) TWI Slave Transfer Disabled */ +#define AT91C_TWI_SWRST ( 0x1 << 7 ) /* (TWI) Software Reset */ +/* -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */ +#define AT91C_TWI_IADRSZ ( 0x3 << 8 ) /* (TWI) Internal Device Address Size */ +#define AT91C_TWI_IADRSZ_NO ( 0x0 << 8 ) /* (TWI) No internal device address */ +#define AT91C_TWI_IADRSZ_1_BYTE ( 0x1 << 8 ) /* (TWI) One-byte internal device address */ +#define AT91C_TWI_IADRSZ_2_BYTE ( 0x2 << 8 ) /* (TWI) Two-byte internal device address */ +#define AT91C_TWI_IADRSZ_3_BYTE ( 0x3 << 8 ) /* (TWI) Three-byte internal device address */ +#define AT91C_TWI_MREAD ( 0x1 << 12 ) /* (TWI) Master Read Direction */ +#define AT91C_TWI_DADR ( 0x7F << 16 ) /* (TWI) Device Address */ +/* -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- */ +#define AT91C_TWI_SADR ( 0x7F << 16 ) /* (TWI) Slave Device Address */ +/* -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */ +#define AT91C_TWI_CLDIV ( 0xFF << 0 ) /* (TWI) Clock Low Divider */ +#define AT91C_TWI_CHDIV ( 0xFF << 8 ) /* (TWI) Clock High Divider */ +#define AT91C_TWI_CKDIV ( 0x7 << 16 ) /* (TWI) Clock Divider */ +/* -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */ +#define AT91C_TWI_TXCOMP ( 0x1 << 0 ) /* (TWI) Transmission Completed */ +#define AT91C_TWI_RXRDY ( 0x1 << 1 ) /* (TWI) Receive holding register ReaDY */ +#define AT91C_TWI_TXRDY ( 0x1 << 2 ) /* (TWI) Transmit holding register ReaDY */ +#define AT91C_TWI_SVREAD ( 0x1 << 3 ) /* (TWI) Slave Read */ +#define AT91C_TWI_SVACC ( 0x1 << 4 ) /* (TWI) Slave Access */ +#define AT91C_TWI_GCACC ( 0x1 << 5 ) /* (TWI) General Call Access */ +#define AT91C_TWI_OVRE ( 0x1 << 6 ) /* (TWI) Overrun Error */ +#define AT91C_TWI_UNRE ( 0x1 << 7 ) /* (TWI) Underrun Error */ +#define AT91C_TWI_NACK ( 0x1 << 8 ) /* (TWI) Not Acknowledged */ +#define AT91C_TWI_ARBLST ( 0x1 << 9 ) /* (TWI) Arbitration Lost */ +/* -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */ +/* -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- */ +/* -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_TC structure *** */ +#define TC_CCR ( 0 ) /* Channel Control Register */ +#define TC_CMR ( 4 ) /* Channel Mode Register (Capture Mode / Waveform Mode) */ +#define TC_CV ( 16 ) /* Counter Value */ +#define TC_RA ( 20 ) /* Register A */ +#define TC_RB ( 24 ) /* Register B */ +#define TC_RC ( 28 ) /* Register C */ +#define TC_SR ( 32 ) /* Status Register */ +#define TC_IER ( 36 ) /* Interrupt Enable Register */ +#define TC_IDR ( 40 ) /* Interrupt Disable Register */ +#define TC_IMR ( 44 ) /* Interrupt Mask Register */ +/* -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- */ +#define AT91C_TC_CLKEN ( 0x1 << 0 ) /* (TC) Counter Clock Enable Command */ +#define AT91C_TC_CLKDIS ( 0x1 << 1 ) /* (TC) Counter Clock Disable Command */ +#define AT91C_TC_SWTRG ( 0x1 << 2 ) /* (TC) Software Trigger Command */ +/* -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- */ +#define AT91C_TC_CLKS ( 0x7 << 0 ) /* (TC) Clock Selection */ +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ( 0x0 ) /* (TC) Clock selected: TIMER_DIV1_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ( 0x1 ) /* (TC) Clock selected: TIMER_DIV2_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ( 0x2 ) /* (TC) Clock selected: TIMER_DIV3_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ( 0x3 ) /* (TC) Clock selected: TIMER_DIV4_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ( 0x4 ) /* (TC) Clock selected: TIMER_DIV5_CLOCK */ +#define AT91C_TC_CLKS_XC0 ( 0x5 ) /* (TC) Clock selected: XC0 */ +#define AT91C_TC_CLKS_XC1 ( 0x6 ) /* (TC) Clock selected: XC1 */ +#define AT91C_TC_CLKS_XC2 ( 0x7 ) /* (TC) Clock selected: XC2 */ +#define AT91C_TC_CLKI ( 0x1 << 3 ) /* (TC) Clock Invert */ +#define AT91C_TC_BURST ( 0x3 << 4 ) /* (TC) Burst Signal Selection */ +#define AT91C_TC_BURST_NONE ( 0x0 << 4 ) /* (TC) The clock is not gated by an external signal */ +#define AT91C_TC_BURST_XC0 ( 0x1 << 4 ) /* (TC) XC0 is ANDed with the selected clock */ +#define AT91C_TC_BURST_XC1 ( 0x2 << 4 ) /* (TC) XC1 is ANDed with the selected clock */ +#define AT91C_TC_BURST_XC2 ( 0x3 << 4 ) /* (TC) XC2 is ANDed with the selected clock */ +#define AT91C_TC_CPCSTOP ( 0x1 << 6 ) /* (TC) Counter Clock Stopped with RC Compare */ +#define AT91C_TC_LDBSTOP ( 0x1 << 6 ) /* (TC) Counter Clock Stopped with RB Loading */ +#define AT91C_TC_LDBDIS ( 0x1 << 7 ) /* (TC) Counter Clock Disabled with RB Loading */ +#define AT91C_TC_CPCDIS ( 0x1 << 7 ) /* (TC) Counter Clock Disable with RC Compare */ +#define AT91C_TC_ETRGEDG ( 0x3 << 8 ) /* (TC) External Trigger Edge Selection */ +#define AT91C_TC_ETRGEDG_NONE ( 0x0 << 8 ) /* (TC) Edge: None */ +#define AT91C_TC_ETRGEDG_RISING ( 0x1 << 8 ) /* (TC) Edge: rising edge */ +#define AT91C_TC_ETRGEDG_FALLING ( 0x2 << 8 ) /* (TC) Edge: falling edge */ +#define AT91C_TC_ETRGEDG_BOTH ( 0x3 << 8 ) /* (TC) Edge: each edge */ +#define AT91C_TC_EEVTEDG ( 0x3 << 8 ) /* (TC) External Event Edge Selection */ +#define AT91C_TC_EEVTEDG_NONE ( 0x0 << 8 ) /* (TC) Edge: None */ +#define AT91C_TC_EEVTEDG_RISING ( 0x1 << 8 ) /* (TC) Edge: rising edge */ +#define AT91C_TC_EEVTEDG_FALLING ( 0x2 << 8 ) /* (TC) Edge: falling edge */ +#define AT91C_TC_EEVTEDG_BOTH ( 0x3 << 8 ) /* (TC) Edge: each edge */ +#define AT91C_TC_ABETRG ( 0x1 << 10 ) /* (TC) TIOA or TIOB External Trigger Selection */ +#define AT91C_TC_EEVT ( 0x3 << 10 ) /* (TC) External Event Selection */ +#define AT91C_TC_EEVT_NONE ( 0x0 << 10 ) /* (TC) Signal selected as external event: TIOB TIOB direction: input */ +#define AT91C_TC_EEVT_RISING ( 0x1 << 10 ) /* (TC) Signal selected as external event: XC0 TIOB direction: output */ +#define AT91C_TC_EEVT_FALLING ( 0x2 << 10 ) /* (TC) Signal selected as external event: XC1 TIOB direction: output */ +#define AT91C_TC_EEVT_BOTH ( 0x3 << 10 ) /* (TC) Signal selected as external event: XC2 TIOB direction: output */ +#define AT91C_TC_ENETRG ( 0x1 << 12 ) /* (TC) External Event Trigger enable */ +#define AT91C_TC_WAVESEL ( 0x3 << 13 ) /* (TC) Waveform Selection */ +#define AT91C_TC_WAVESEL_UP ( 0x0 << 13 ) /* (TC) UP mode without atomatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UPDOWN ( 0x1 << 13 ) /* (TC) UPDOWN mode without automatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UP_AUTO ( 0x2 << 13 ) /* (TC) UP mode with automatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UPDOWN_AUTO ( 0x3 << 13 ) /* (TC) UPDOWN mode with automatic trigger on RC Compare */ +#define AT91C_TC_CPCTRG ( 0x1 << 14 ) /* (TC) RC Compare Trigger Enable */ +#define AT91C_TC_WAVE ( 0x1 << 15 ) /* (TC) */ +#define AT91C_TC_LDRA ( 0x3 << 16 ) /* (TC) RA Loading Selection */ +#define AT91C_TC_LDRA_NONE ( 0x0 << 16 ) /* (TC) Edge: None */ +#define AT91C_TC_LDRA_RISING ( 0x1 << 16 ) /* (TC) Edge: rising edge of TIOA */ +#define AT91C_TC_LDRA_FALLING ( 0x2 << 16 ) /* (TC) Edge: falling edge of TIOA */ +#define AT91C_TC_LDRA_BOTH ( 0x3 << 16 ) /* (TC) Edge: each edge of TIOA */ +#define AT91C_TC_ACPA ( 0x3 << 16 ) /* (TC) RA Compare Effect on TIOA */ +#define AT91C_TC_ACPA_NONE ( 0x0 << 16 ) /* (TC) Effect: none */ +#define AT91C_TC_ACPA_SET ( 0x1 << 16 ) /* (TC) Effect: set */ +#define AT91C_TC_ACPA_CLEAR ( 0x2 << 16 ) /* (TC) Effect: clear */ +#define AT91C_TC_ACPA_TOGGLE ( 0x3 << 16 ) /* (TC) Effect: toggle */ +#define AT91C_TC_LDRB ( 0x3 << 18 ) /* (TC) RB Loading Selection */ +#define AT91C_TC_LDRB_NONE ( 0x0 << 18 ) /* (TC) Edge: None */ +#define AT91C_TC_LDRB_RISING ( 0x1 << 18 ) /* (TC) Edge: rising edge of TIOA */ +#define AT91C_TC_LDRB_FALLING ( 0x2 << 18 ) /* (TC) Edge: falling edge of TIOA */ +#define AT91C_TC_LDRB_BOTH ( 0x3 << 18 ) /* (TC) Edge: each edge of TIOA */ +#define AT91C_TC_ACPC ( 0x3 << 18 ) /* (TC) RC Compare Effect on TIOA */ +#define AT91C_TC_ACPC_NONE ( 0x0 << 18 ) /* (TC) Effect: none */ +#define AT91C_TC_ACPC_SET ( 0x1 << 18 ) /* (TC) Effect: set */ +#define AT91C_TC_ACPC_CLEAR ( 0x2 << 18 ) /* (TC) Effect: clear */ +#define AT91C_TC_ACPC_TOGGLE ( 0x3 << 18 ) /* (TC) Effect: toggle */ +#define AT91C_TC_AEEVT ( 0x3 << 20 ) /* (TC) External Event Effect on TIOA */ +#define AT91C_TC_AEEVT_NONE ( 0x0 << 20 ) /* (TC) Effect: none */ +#define AT91C_TC_AEEVT_SET ( 0x1 << 20 ) /* (TC) Effect: set */ +#define AT91C_TC_AEEVT_CLEAR ( 0x2 << 20 ) /* (TC) Effect: clear */ +#define AT91C_TC_AEEVT_TOGGLE ( 0x3 << 20 ) /* (TC) Effect: toggle */ +#define AT91C_TC_ASWTRG ( 0x3 << 22 ) /* (TC) Software Trigger Effect on TIOA */ +#define AT91C_TC_ASWTRG_NONE ( 0x0 << 22 ) /* (TC) Effect: none */ +#define AT91C_TC_ASWTRG_SET ( 0x1 << 22 ) /* (TC) Effect: set */ +#define AT91C_TC_ASWTRG_CLEAR ( 0x2 << 22 ) /* (TC) Effect: clear */ +#define AT91C_TC_ASWTRG_TOGGLE ( 0x3 << 22 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BCPB ( 0x3 << 24 ) /* (TC) RB Compare Effect on TIOB */ +#define AT91C_TC_BCPB_NONE ( 0x0 << 24 ) /* (TC) Effect: none */ +#define AT91C_TC_BCPB_SET ( 0x1 << 24 ) /* (TC) Effect: set */ +#define AT91C_TC_BCPB_CLEAR ( 0x2 << 24 ) /* (TC) Effect: clear */ +#define AT91C_TC_BCPB_TOGGLE ( 0x3 << 24 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BCPC ( 0x3 << 26 ) /* (TC) RC Compare Effect on TIOB */ +#define AT91C_TC_BCPC_NONE ( 0x0 << 26 ) /* (TC) Effect: none */ +#define AT91C_TC_BCPC_SET ( 0x1 << 26 ) /* (TC) Effect: set */ +#define AT91C_TC_BCPC_CLEAR ( 0x2 << 26 ) /* (TC) Effect: clear */ +#define AT91C_TC_BCPC_TOGGLE ( 0x3 << 26 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BEEVT ( 0x3 << 28 ) /* (TC) External Event Effect on TIOB */ +#define AT91C_TC_BEEVT_NONE ( 0x0 << 28 ) /* (TC) Effect: none */ +#define AT91C_TC_BEEVT_SET ( 0x1 << 28 ) /* (TC) Effect: set */ +#define AT91C_TC_BEEVT_CLEAR ( 0x2 << 28 ) /* (TC) Effect: clear */ +#define AT91C_TC_BEEVT_TOGGLE ( 0x3 << 28 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BSWTRG ( 0x3 << 30 ) /* (TC) Software Trigger Effect on TIOB */ +#define AT91C_TC_BSWTRG_NONE ( 0x0 << 30 ) /* (TC) Effect: none */ +#define AT91C_TC_BSWTRG_SET ( 0x1 << 30 ) /* (TC) Effect: set */ +#define AT91C_TC_BSWTRG_CLEAR ( 0x2 << 30 ) /* (TC) Effect: clear */ +#define AT91C_TC_BSWTRG_TOGGLE ( 0x3 << 30 ) /* (TC) Effect: toggle */ +/* -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- */ +#define AT91C_TC_COVFS ( 0x1 << 0 ) /* (TC) Counter Overflow */ +#define AT91C_TC_LOVRS ( 0x1 << 1 ) /* (TC) Load Overrun */ +#define AT91C_TC_CPAS ( 0x1 << 2 ) /* (TC) RA Compare */ +#define AT91C_TC_CPBS ( 0x1 << 3 ) /* (TC) RB Compare */ +#define AT91C_TC_CPCS ( 0x1 << 4 ) /* (TC) RC Compare */ +#define AT91C_TC_LDRAS ( 0x1 << 5 ) /* (TC) RA Loading */ +#define AT91C_TC_LDRBS ( 0x1 << 6 ) /* (TC) RB Loading */ +#define AT91C_TC_ETRCS ( 0x1 << 7 ) /* (TC) External Trigger */ +#define AT91C_TC_ETRGS ( 0x1 << 16 ) /* (TC) Clock Enabling */ +#define AT91C_TC_MTIOA ( 0x1 << 17 ) /* (TC) TIOA Mirror */ +#define AT91C_TC_MTIOB ( 0x1 << 18 ) /* (TC) TIOA Mirror */ +/* -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- */ +/* -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- */ +/* -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Timer Counter Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_TCB structure *** */ +#define TCB_TC0 ( 0 ) /* TC Channel 0 */ +#define TCB_TC1 ( 64 ) /* TC Channel 1 */ +#define TCB_TC2 ( 128 ) /* TC Channel 2 */ +#define TCB_BCR ( 192 ) /* TC Block Control Register */ +#define TCB_BMR ( 196 ) /* TC Block Mode Register */ +/* -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- */ +#define AT91C_TCB_SYNC ( 0x1 << 0 ) /* (TCB) Synchro Command */ +/* -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- */ +#define AT91C_TCB_TC0XC0S ( 0x1 << 0 ) /* (TCB) External Clock Signal 0 Selection */ +#define AT91C_TCB_TC0XC0S_TCLK0 ( 0x0 ) /* (TCB) TCLK0 connected to XC0 */ +#define AT91C_TCB_TC0XC0S_NONE ( 0x1 ) /* (TCB) None signal connected to XC0 */ +#define AT91C_TCB_TC0XC0S_TIOA1 ( 0x2 ) /* (TCB) TIOA1 connected to XC0 */ +#define AT91C_TCB_TC0XC0S_TIOA2 ( 0x3 ) /* (TCB) TIOA2 connected to XC0 */ +#define AT91C_TCB_TC1XC1S ( 0x1 << 2 ) /* (TCB) External Clock Signal 1 Selection */ +#define AT91C_TCB_TC1XC1S_TCLK1 ( 0x0 << 2 ) /* (TCB) TCLK1 connected to XC1 */ +#define AT91C_TCB_TC1XC1S_NONE ( 0x1 << 2 ) /* (TCB) None signal connected to XC1 */ +#define AT91C_TCB_TC1XC1S_TIOA0 ( 0x2 << 2 ) /* (TCB) TIOA0 connected to XC1 */ +#define AT91C_TCB_TC1XC1S_TIOA2 ( 0x3 << 2 ) /* (TCB) TIOA2 connected to XC1 */ +#define AT91C_TCB_TC2XC2S ( 0x1 << 4 ) /* (TCB) External Clock Signal 2 Selection */ +#define AT91C_TCB_TC2XC2S_TCLK2 ( 0x0 << 4 ) /* (TCB) TCLK2 connected to XC2 */ +#define AT91C_TCB_TC2XC2S_NONE ( 0x1 << 4 ) /* (TCB) None signal connected to XC2 */ +#define AT91C_TCB_TC2XC2S_TIOA0 ( 0x2 << 4 ) /* (TCB) TIOA0 connected to XC2 */ +#define AT91C_TCB_TC2XC2S_TIOA2 ( 0x3 << 4 ) /* (TCB) TIOA2 connected to XC2 */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR PWMC Channel Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_PWMC_CH structure *** */ +#define PWMC_CMR ( 0 ) /* Channel Mode Register */ +#define PWMC_CDTYR ( 4 ) /* Channel Duty Cycle Register */ +#define PWMC_CPRDR ( 8 ) /* Channel Period Register */ +#define PWMC_CCNTR ( 12 ) /* Channel Counter Register */ +#define PWMC_CUPDR ( 16 ) /* Channel Update Register */ +#define PWMC_Reserved ( 20 ) /* Reserved */ +/* -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- */ +#define AT91C_PWMC_CPRE ( 0xF << 0 ) /* (PWMC_CH) Channel Pre-scaler : PWMC_CLKx */ +#define AT91C_PWMC_CPRE_MCK ( 0x0 ) /* (PWMC_CH) */ +#define AT91C_PWMC_CPRE_MCKA ( 0xB ) /* (PWMC_CH) */ +#define AT91C_PWMC_CPRE_MCKB ( 0xC ) /* (PWMC_CH) */ +#define AT91C_PWMC_CALG ( 0x1 << 8 ) /* (PWMC_CH) Channel Alignment */ +#define AT91C_PWMC_CPOL ( 0x1 << 9 ) /* (PWMC_CH) Channel Polarity */ +#define AT91C_PWMC_CPD ( 0x1 << 10 ) /* (PWMC_CH) Channel Update Period */ +/* -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- */ +#define AT91C_PWMC_CDTY ( 0x0 << 0 ) /* (PWMC_CH) Channel Duty Cycle */ +/* -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- */ +#define AT91C_PWMC_CPRD ( 0x0 << 0 ) /* (PWMC_CH) Channel Period */ +/* -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- */ +#define AT91C_PWMC_CCNT ( 0x0 << 0 ) /* (PWMC_CH) Channel Counter */ +/* -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- */ +#define AT91C_PWMC_CUPD ( 0x0 << 0 ) /* (PWMC_CH) Channel Update */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_PWMC structure *** */ +#define PWMC_MR ( 0 ) /* PWMC Mode Register */ +#define PWMC_ENA ( 4 ) /* PWMC Enable Register */ +#define PWMC_DIS ( 8 ) /* PWMC Disable Register */ +#define PWMC_SR ( 12 ) /* PWMC Status Register */ +#define PWMC_IER ( 16 ) /* PWMC Interrupt Enable Register */ +#define PWMC_IDR ( 20 ) /* PWMC Interrupt Disable Register */ +#define PWMC_IMR ( 24 ) /* PWMC Interrupt Mask Register */ +#define PWMC_ISR ( 28 ) /* PWMC Interrupt Status Register */ +#define PWMC_VR ( 252 ) /* PWMC Version Register */ +#define PWMC_CH ( 512 ) /* PWMC Channel 0 */ +/* -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- */ +#define AT91C_PWMC_DIVA ( 0xFF << 0 ) /* (PWMC) CLKA divide factor. */ +#define AT91C_PWMC_PREA ( 0xF << 8 ) /* (PWMC) Divider Input Clock Prescaler A */ +#define AT91C_PWMC_PREA_MCK ( 0x0 << 8 ) /* (PWMC) */ +#define AT91C_PWMC_DIVB ( 0xFF << 16 ) /* (PWMC) CLKB divide factor. */ +#define AT91C_PWMC_PREB ( 0xF << 24 ) /* (PWMC) Divider Input Clock Prescaler B */ +#define AT91C_PWMC_PREB_MCK ( 0x0 << 24 ) /* (PWMC) */ +/* -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- */ +#define AT91C_PWMC_CHID0 ( 0x1 << 0 ) /* (PWMC) Channel ID 0 */ +#define AT91C_PWMC_CHID1 ( 0x1 << 1 ) /* (PWMC) Channel ID 1 */ +#define AT91C_PWMC_CHID2 ( 0x1 << 2 ) /* (PWMC) Channel ID 2 */ +#define AT91C_PWMC_CHID3 ( 0x1 << 3 ) /* (PWMC) Channel ID 3 */ +#define AT91C_PWMC_CHID4 ( 0x1 << 4 ) /* (PWMC) Channel ID 4 */ +#define AT91C_PWMC_CHID5 ( 0x1 << 5 ) /* (PWMC) Channel ID 5 */ +#define AT91C_PWMC_CHID6 ( 0x1 << 6 ) /* (PWMC) Channel ID 6 */ +#define AT91C_PWMC_CHID7 ( 0x1 << 7 ) /* (PWMC) Channel ID 7 */ +/* -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- */ +/* -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- */ +/* -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- */ +/* -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- */ +/* -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- */ +/* -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR USB Device Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_UDP structure *** */ +#define UDP_NUM ( 0 ) /* Frame Number Register */ +#define UDP_GLBSTATE ( 4 ) /* Global State Register */ +#define UDP_FADDR ( 8 ) /* Function Address Register */ +#define UDP_IER ( 16 ) /* Interrupt Enable Register */ +#define UDP_IDR ( 20 ) /* Interrupt Disable Register */ +#define UDP_IMR ( 24 ) /* Interrupt Mask Register */ +#define UDP_ISR ( 28 ) /* Interrupt Status Register */ +#define UDP_ICR ( 32 ) /* Interrupt Clear Register */ +#define UDP_RSTEP ( 40 ) /* Reset Endpoint Register */ +#define UDP_CSR ( 48 ) /* Endpoint Control and Status Register */ +#define UDP_FDR ( 80 ) /* Endpoint FIFO Data Register */ +/* -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- */ +#define AT91C_UDP_FRM_NUM ( 0x7FF << 0 ) /* (UDP) Frame Number as Defined in the Packet Field Formats */ +#define AT91C_UDP_FRM_ERR ( 0x1 << 16 ) /* (UDP) Frame Error */ +#define AT91C_UDP_FRM_OK ( 0x1 << 17 ) /* (UDP) Frame OK */ +/* -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- */ +#define AT91C_UDP_FADDEN ( 0x1 << 0 ) /* (UDP) Function Address Enable */ +#define AT91C_UDP_CONFG ( 0x1 << 1 ) /* (UDP) Configured */ +#define AT91C_UDP_RMWUPE ( 0x1 << 2 ) /* (UDP) Remote Wake Up Enable */ +#define AT91C_UDP_RSMINPR ( 0x1 << 3 ) /* (UDP) A Resume Has Been Sent to the Host */ +/* -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- */ +#define AT91C_UDP_FADD ( 0xFF << 0 ) /* (UDP) Function Address Value */ +#define AT91C_UDP_FEN ( 0x1 << 8 ) /* (UDP) Function Enable */ +/* -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- */ +#define AT91C_UDP_EPINT0 ( 0x1 << 0 ) /* (UDP) Endpoint 0 Interrupt */ +#define AT91C_UDP_EPINT1 ( 0x1 << 1 ) /* (UDP) Endpoint 0 Interrupt */ +#define AT91C_UDP_EPINT2 ( 0x1 << 2 ) /* (UDP) Endpoint 2 Interrupt */ +#define AT91C_UDP_EPINT3 ( 0x1 << 3 ) /* (UDP) Endpoint 3 Interrupt */ +#define AT91C_UDP_EPINT4 ( 0x1 << 4 ) /* (UDP) Endpoint 4 Interrupt */ +#define AT91C_UDP_EPINT5 ( 0x1 << 5 ) /* (UDP) Endpoint 5 Interrupt */ +#define AT91C_UDP_EPINT6 ( 0x1 << 6 ) /* (UDP) Endpoint 6 Interrupt */ +#define AT91C_UDP_EPINT7 ( 0x1 << 7 ) /* (UDP) Endpoint 7 Interrupt */ +#define AT91C_UDP_RXSUSP ( 0x1 << 8 ) /* (UDP) USB Suspend Interrupt */ +#define AT91C_UDP_RXRSM ( 0x1 << 9 ) /* (UDP) USB Resume Interrupt */ +#define AT91C_UDP_EXTRSM ( 0x1 << 10 ) /* (UDP) USB External Resume Interrupt */ +#define AT91C_UDP_SOFINT ( 0x1 << 11 ) /* (UDP) USB Start Of frame Interrupt */ +#define AT91C_UDP_WAKEUP ( 0x1 << 13 ) /* (UDP) USB Resume Interrupt */ +/* -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- */ +/* -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- */ +/* -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- */ +#define AT91C_UDP_ENDBUSRES ( 0x1 << 12 ) /* (UDP) USB End Of Bus Reset Interrupt */ +/* -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- */ +/* -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- */ +#define AT91C_UDP_EP0 ( 0x1 << 0 ) /* (UDP) Reset Endpoint 0 */ +#define AT91C_UDP_EP1 ( 0x1 << 1 ) /* (UDP) Reset Endpoint 1 */ +#define AT91C_UDP_EP2 ( 0x1 << 2 ) /* (UDP) Reset Endpoint 2 */ +#define AT91C_UDP_EP3 ( 0x1 << 3 ) /* (UDP) Reset Endpoint 3 */ +#define AT91C_UDP_EP4 ( 0x1 << 4 ) /* (UDP) Reset Endpoint 4 */ +#define AT91C_UDP_EP5 ( 0x1 << 5 ) /* (UDP) Reset Endpoint 5 */ +#define AT91C_UDP_EP6 ( 0x1 << 6 ) /* (UDP) Reset Endpoint 6 */ +#define AT91C_UDP_EP7 ( 0x1 << 7 ) /* (UDP) Reset Endpoint 7 */ +/* -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- */ +#define AT91C_UDP_TXCOMP ( 0x1 << 0 ) /* (UDP) Generates an IN packet with data previously written in the DPR */ +#define AT91C_UDP_RX_DATA_BK0 ( 0x1 << 1 ) /* (UDP) Receive Data Bank 0 */ +#define AT91C_UDP_RXSETUP ( 0x1 << 2 ) /* (UDP) Sends STALL to the Host (Control endpoints) */ +#define AT91C_UDP_ISOERROR ( 0x1 << 3 ) /* (UDP) Isochronous error (Isochronous endpoints) */ +#define AT91C_UDP_TXPKTRDY ( 0x1 << 4 ) /* (UDP) Transmit Packet Ready */ +#define AT91C_UDP_FORCESTALL ( 0x1 << 5 ) /* (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). */ +#define AT91C_UDP_RX_DATA_BK1 ( 0x1 << 6 ) /* (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). */ +#define AT91C_UDP_DIR ( 0x1 << 7 ) /* (UDP) Transfer Direction */ +#define AT91C_UDP_EPTYPE ( 0x7 << 8 ) /* (UDP) Endpoint type */ +#define AT91C_UDP_EPTYPE_CTRL ( 0x0 << 8 ) /* (UDP) Control */ +#define AT91C_UDP_EPTYPE_ISO_OUT ( 0x1 << 8 ) /* (UDP) Isochronous OUT */ +#define AT91C_UDP_EPTYPE_BULK_OUT ( 0x2 << 8 ) /* (UDP) Bulk OUT */ +#define AT91C_UDP_EPTYPE_INT_OUT ( 0x3 << 8 ) /* (UDP) Interrupt OUT */ +#define AT91C_UDP_EPTYPE_ISO_IN ( 0x5 << 8 ) /* (UDP) Isochronous IN */ +#define AT91C_UDP_EPTYPE_BULK_IN ( 0x6 << 8 ) /* (UDP) Bulk IN */ +#define AT91C_UDP_EPTYPE_INT_IN ( 0x7 << 8 ) /* (UDP) Interrupt IN */ +#define AT91C_UDP_DTGLE ( 0x1 << 11 ) /* (UDP) Data Toggle */ +#define AT91C_UDP_EPEDS ( 0x1 << 15 ) /* (UDP) Endpoint Enable Disable */ +#define AT91C_UDP_RXBYTECNT ( 0x7FF << 16 ) /* (UDP) Number Of Bytes Available in the FIFO */ + +/* ***************************************************************************** */ +/* REGISTER ADDRESS DEFINITION FOR AT91SAM7S64 */ +/* ***************************************************************************** */ +/* ========== Register definition for SYSC peripheral ========== */ +#define AT91C_SYSC_SYSC_VRPM ( 0xFFFFFD60 ) /* (SYSC) Voltage Regulator Power Mode Register */ +/* ========== Register definition for AIC peripheral ========== */ +#define AT91C_AIC_ICCR ( 0xFFFFF128 ) /* (AIC) Interrupt Clear Command Register */ +#define AT91C_AIC_IECR ( 0xFFFFF120 ) /* (AIC) Interrupt Enable Command Register */ +#define AT91C_AIC_SMR ( 0xFFFFF000 ) /* (AIC) Source Mode Register */ +#define AT91C_AIC_ISCR ( 0xFFFFF12C ) /* (AIC) Interrupt Set Command Register */ +#define AT91C_AIC_EOICR ( 0xFFFFF130 ) /* (AIC) End of Interrupt Command Register */ +#define AT91C_AIC_DCR ( 0xFFFFF138 ) /* (AIC) Debug Control Register (Protect) */ +#define AT91C_AIC_FFER ( 0xFFFFF140 ) /* (AIC) Fast Forcing Enable Register */ +#define AT91C_AIC_SVR ( 0xFFFFF080 ) /* (AIC) Source Vector Register */ +#define AT91C_AIC_SPU ( 0xFFFFF134 ) /* (AIC) Spurious Vector Register */ +#define AT91C_AIC_FFDR ( 0xFFFFF144 ) /* (AIC) Fast Forcing Disable Register */ +#define AT91C_AIC_FVR ( 0xFFFFF104 ) /* (AIC) FIQ Vector Register */ +#define AT91C_AIC_FFSR ( 0xFFFFF148 ) /* (AIC) Fast Forcing Status Register */ +#define AT91C_AIC_IMR ( 0xFFFFF110 ) /* (AIC) Interrupt Mask Register */ +#define AT91C_AIC_ISR ( 0xFFFFF108 ) /* (AIC) Interrupt Status Register */ +#define AT91C_AIC_IVR ( 0xFFFFF100 ) /* (AIC) IRQ Vector Register */ +#define AT91C_AIC_IDCR ( 0xFFFFF124 ) /* (AIC) Interrupt Disable Command Register */ +#define AT91C_AIC_CISR ( 0xFFFFF114 ) /* (AIC) Core Interrupt Status Register */ +#define AT91C_AIC_IPR ( 0xFFFFF10C ) /* (AIC) Interrupt Pending Register */ +/* ========== Register definition for DBGU peripheral ========== */ +#define AT91C_DBGU_C2R ( 0xFFFFF244 ) /* (DBGU) Chip ID2 Register */ +#define AT91C_DBGU_THR ( 0xFFFFF21C ) /* (DBGU) Transmitter Holding Register */ +#define AT91C_DBGU_CSR ( 0xFFFFF214 ) /* (DBGU) Channel Status Register */ +#define AT91C_DBGU_IDR ( 0xFFFFF20C ) /* (DBGU) Interrupt Disable Register */ +#define AT91C_DBGU_MR ( 0xFFFFF204 ) /* (DBGU) Mode Register */ +#define AT91C_DBGU_FNTR ( 0xFFFFF248 ) /* (DBGU) Force NTRST Register */ +#define AT91C_DBGU_C1R ( 0xFFFFF240 ) /* (DBGU) Chip ID1 Register */ +#define AT91C_DBGU_BRGR ( 0xFFFFF220 ) /* (DBGU) Baud Rate Generator Register */ +#define AT91C_DBGU_RHR ( 0xFFFFF218 ) /* (DBGU) Receiver Holding Register */ +#define AT91C_DBGU_IMR ( 0xFFFFF210 ) /* (DBGU) Interrupt Mask Register */ +#define AT91C_DBGU_IER ( 0xFFFFF208 ) /* (DBGU) Interrupt Enable Register */ +#define AT91C_DBGU_CR ( 0xFFFFF200 ) /* (DBGU) Control Register */ +/* ========== Register definition for PDC_DBGU peripheral ========== */ +#define AT91C_DBGU_TNCR ( 0xFFFFF31C ) /* (PDC_DBGU) Transmit Next Counter Register */ +#define AT91C_DBGU_RNCR ( 0xFFFFF314 ) /* (PDC_DBGU) Receive Next Counter Register */ +#define AT91C_DBGU_PTCR ( 0xFFFFF320 ) /* (PDC_DBGU) PDC Transfer Control Register */ +#define AT91C_DBGU_PTSR ( 0xFFFFF324 ) /* (PDC_DBGU) PDC Transfer Status Register */ +#define AT91C_DBGU_RCR ( 0xFFFFF304 ) /* (PDC_DBGU) Receive Counter Register */ +#define AT91C_DBGU_TCR ( 0xFFFFF30C ) /* (PDC_DBGU) Transmit Counter Register */ +#define AT91C_DBGU_RPR ( 0xFFFFF300 ) /* (PDC_DBGU) Receive Pointer Register */ +#define AT91C_DBGU_TPR ( 0xFFFFF308 ) /* (PDC_DBGU) Transmit Pointer Register */ +#define AT91C_DBGU_RNPR ( 0xFFFFF310 ) /* (PDC_DBGU) Receive Next Pointer Register */ +#define AT91C_DBGU_TNPR ( 0xFFFFF318 ) /* (PDC_DBGU) Transmit Next Pointer Register */ +/* ========== Register definition for PIOA peripheral ========== */ +#define AT91C_PIOA_IMR ( 0xFFFFF448 ) /* (PIOA) Interrupt Mask Register */ +#define AT91C_PIOA_IER ( 0xFFFFF440 ) /* (PIOA) Interrupt Enable Register */ +#define AT91C_PIOA_OWDR ( 0xFFFFF4A4 ) /* (PIOA) Output Write Disable Register */ +#define AT91C_PIOA_ISR ( 0xFFFFF44C ) /* (PIOA) Interrupt Status Register */ +#define AT91C_PIOA_PPUDR ( 0xFFFFF460 ) /* (PIOA) Pull-up Disable Register */ +#define AT91C_PIOA_MDSR ( 0xFFFFF458 ) /* (PIOA) Multi-driver Status Register */ +#define AT91C_PIOA_MDER ( 0xFFFFF450 ) /* (PIOA) Multi-driver Enable Register */ +#define AT91C_PIOA_PER ( 0xFFFFF400 ) /* (PIOA) PIO Enable Register */ +#define AT91C_PIOA_PSR ( 0xFFFFF408 ) /* (PIOA) PIO Status Register */ +#define AT91C_PIOA_OER ( 0xFFFFF410 ) /* (PIOA) Output Enable Register */ +#define AT91C_PIOA_BSR ( 0xFFFFF474 ) /* (PIOA) Select B Register */ +#define AT91C_PIOA_PPUER ( 0xFFFFF464 ) /* (PIOA) Pull-up Enable Register */ +#define AT91C_PIOA_MDDR ( 0xFFFFF454 ) /* (PIOA) Multi-driver Disable Register */ +#define AT91C_PIOA_PDR ( 0xFFFFF404 ) /* (PIOA) PIO Disable Register */ +#define AT91C_PIOA_ODR ( 0xFFFFF414 ) /* (PIOA) Output Disable Registerr */ +#define AT91C_PIOA_IFDR ( 0xFFFFF424 ) /* (PIOA) Input Filter Disable Register */ +#define AT91C_PIOA_ABSR ( 0xFFFFF478 ) /* (PIOA) AB Select Status Register */ +#define AT91C_PIOA_ASR ( 0xFFFFF470 ) /* (PIOA) Select A Register */ +#define AT91C_PIOA_PPUSR ( 0xFFFFF468 ) /* (PIOA) Pad Pull-up Status Register */ +#define AT91C_PIOA_ODSR ( 0xFFFFF438 ) /* (PIOA) Output Data Status Register */ +#define AT91C_PIOA_SODR ( 0xFFFFF430 ) /* (PIOA) Set Output Data Register */ +#define AT91C_PIOA_IFSR ( 0xFFFFF428 ) /* (PIOA) Input Filter Status Register */ +#define AT91C_PIOA_IFER ( 0xFFFFF420 ) /* (PIOA) Input Filter Enable Register */ +#define AT91C_PIOA_OSR ( 0xFFFFF418 ) /* (PIOA) Output Status Register */ +#define AT91C_PIOA_IDR ( 0xFFFFF444 ) /* (PIOA) Interrupt Disable Register */ +#define AT91C_PIOA_PDSR ( 0xFFFFF43C ) /* (PIOA) Pin Data Status Register */ +#define AT91C_PIOA_CODR ( 0xFFFFF434 ) /* (PIOA) Clear Output Data Register */ +#define AT91C_PIOA_OWSR ( 0xFFFFF4A8 ) /* (PIOA) Output Write Status Register */ +#define AT91C_PIOA_OWER ( 0xFFFFF4A0 ) /* (PIOA) Output Write Enable Register */ +/* ========== Register definition for CKGR peripheral ========== */ +#define AT91C_CKGR_PLLR ( 0xFFFFFC2C ) /* (CKGR) PLL Register */ +#define AT91C_CKGR_MCFR ( 0xFFFFFC24 ) /* (CKGR) Main Clock Frequency Register */ +#define AT91C_CKGR_MOR ( 0xFFFFFC20 ) /* (CKGR) Main Oscillator Register */ +/* ========== Register definition for PMC peripheral ========== */ +#define AT91C_PMC_SCSR ( 0xFFFFFC08 ) /* (PMC) System Clock Status Register */ +#define AT91C_PMC_SCER ( 0xFFFFFC00 ) /* (PMC) System Clock Enable Register */ +#define AT91C_PMC_IMR ( 0xFFFFFC6C ) /* (PMC) Interrupt Mask Register */ +#define AT91C_PMC_IDR ( 0xFFFFFC64 ) /* (PMC) Interrupt Disable Register */ +#define AT91C_PMC_PCDR ( 0xFFFFFC14 ) /* (PMC) Peripheral Clock Disable Register */ +#define AT91C_PMC_SCDR ( 0xFFFFFC04 ) /* (PMC) System Clock Disable Register */ +#define AT91C_PMC_SR ( 0xFFFFFC68 ) /* (PMC) Status Register */ +#define AT91C_PMC_IER ( 0xFFFFFC60 ) /* (PMC) Interrupt Enable Register */ +#define AT91C_PMC_MCKR ( 0xFFFFFC30 ) /* (PMC) Master Clock Register */ +#define AT91C_PMC_MOR ( 0xFFFFFC20 ) /* (PMC) Main Oscillator Register */ +#define AT91C_PMC_PCER ( 0xFFFFFC10 ) /* (PMC) Peripheral Clock Enable Register */ +#define AT91C_PMC_PCSR ( 0xFFFFFC18 ) /* (PMC) Peripheral Clock Status Register */ +#define AT91C_PMC_PLLR ( 0xFFFFFC2C ) /* (PMC) PLL Register */ +#define AT91C_PMC_MCFR ( 0xFFFFFC24 ) /* (PMC) Main Clock Frequency Register */ +#define AT91C_PMC_PCKR ( 0xFFFFFC40 ) /* (PMC) Programmable Clock Register */ +/* ========== Register definition for RSTC peripheral ========== */ +#define AT91C_RSTC_RSR ( 0xFFFFFD04 ) /* (RSTC) Reset Status Register */ +#define AT91C_RSTC_RMR ( 0xFFFFFD08 ) /* (RSTC) Reset Mode Register */ +#define AT91C_RSTC_RCR ( 0xFFFFFD00 ) /* (RSTC) Reset Control Register */ +/* ========== Register definition for RTTC peripheral ========== */ +#define AT91C_RTTC_RTSR ( 0xFFFFFD2C ) /* (RTTC) Real-time Status Register */ +#define AT91C_RTTC_RTAR ( 0xFFFFFD24 ) /* (RTTC) Real-time Alarm Register */ +#define AT91C_RTTC_RTVR ( 0xFFFFFD28 ) /* (RTTC) Real-time Value Register */ +#define AT91C_RTTC_RTMR ( 0xFFFFFD20 ) /* (RTTC) Real-time Mode Register */ +/* ========== Register definition for PITC peripheral ========== */ +#define AT91C_PITC_PIIR ( 0xFFFFFD3C ) /* (PITC) Period Interval Image Register */ +#define AT91C_PITC_PISR ( 0xFFFFFD34 ) /* (PITC) Period Interval Status Register */ +#define AT91C_PITC_PIVR ( 0xFFFFFD38 ) /* (PITC) Period Interval Value Register */ +#define AT91C_PITC_PIMR ( 0xFFFFFD30 ) /* (PITC) Period Interval Mode Register */ +/* ========== Register definition for WDTC peripheral ========== */ +#define AT91C_WDTC_WDMR ( 0xFFFFFD44 ) /* (WDTC) Watchdog Mode Register */ +#define AT91C_WDTC_WDSR ( 0xFFFFFD48 ) /* (WDTC) Watchdog Status Register */ +#define AT91C_WDTC_WDCR ( 0xFFFFFD40 ) /* (WDTC) Watchdog Control Register */ +/* ========== Register definition for MC peripheral ========== */ +#define AT91C_MC_FCR ( 0xFFFFFF64 ) /* (MC) MC Flash Command Register */ +#define AT91C_MC_ASR ( 0xFFFFFF04 ) /* (MC) MC Abort Status Register */ +#define AT91C_MC_FSR ( 0xFFFFFF68 ) /* (MC) MC Flash Status Register */ +#define AT91C_MC_FMR ( 0xFFFFFF60 ) /* (MC) MC Flash Mode Register */ +#define AT91C_MC_AASR ( 0xFFFFFF08 ) /* (MC) MC Abort Address Status Register */ +#define AT91C_MC_RCR ( 0xFFFFFF00 ) /* (MC) MC Remap Control Register */ +/* ========== Register definition for PDC_SPI peripheral ========== */ +#define AT91C_SPI_PTCR ( 0xFFFE0120 ) /* (PDC_SPI) PDC Transfer Control Register */ +#define AT91C_SPI_TNPR ( 0xFFFE0118 ) /* (PDC_SPI) Transmit Next Pointer Register */ +#define AT91C_SPI_RNPR ( 0xFFFE0110 ) /* (PDC_SPI) Receive Next Pointer Register */ +#define AT91C_SPI_TPR ( 0xFFFE0108 ) /* (PDC_SPI) Transmit Pointer Register */ +#define AT91C_SPI_RPR ( 0xFFFE0100 ) /* (PDC_SPI) Receive Pointer Register */ +#define AT91C_SPI_PTSR ( 0xFFFE0124 ) /* (PDC_SPI) PDC Transfer Status Register */ +#define AT91C_SPI_TNCR ( 0xFFFE011C ) /* (PDC_SPI) Transmit Next Counter Register */ +#define AT91C_SPI_RNCR ( 0xFFFE0114 ) /* (PDC_SPI) Receive Next Counter Register */ +#define AT91C_SPI_TCR ( 0xFFFE010C ) /* (PDC_SPI) Transmit Counter Register */ +#define AT91C_SPI_RCR ( 0xFFFE0104 ) /* (PDC_SPI) Receive Counter Register */ +/* ========== Register definition for SPI peripheral ========== */ +#define AT91C_SPI_CSR ( 0xFFFE0030 ) /* (SPI) Chip Select Register */ +#define AT91C_SPI_IDR ( 0xFFFE0018 ) /* (SPI) Interrupt Disable Register */ +#define AT91C_SPI_SR ( 0xFFFE0010 ) /* (SPI) Status Register */ +#define AT91C_SPI_RDR ( 0xFFFE0008 ) /* (SPI) Receive Data Register */ +#define AT91C_SPI_CR ( 0xFFFE0000 ) /* (SPI) Control Register */ +#define AT91C_SPI_IMR ( 0xFFFE001C ) /* (SPI) Interrupt Mask Register */ +#define AT91C_SPI_IER ( 0xFFFE0014 ) /* (SPI) Interrupt Enable Register */ +#define AT91C_SPI_TDR ( 0xFFFE000C ) /* (SPI) Transmit Data Register */ +#define AT91C_SPI_MR ( 0xFFFE0004 ) /* (SPI) Mode Register */ +/* ========== Register definition for PDC_ADC peripheral ========== */ +#define AT91C_ADC_PTCR ( 0xFFFD8120 ) /* (PDC_ADC) PDC Transfer Control Register */ +#define AT91C_ADC_TNPR ( 0xFFFD8118 ) /* (PDC_ADC) Transmit Next Pointer Register */ +#define AT91C_ADC_RNPR ( 0xFFFD8110 ) /* (PDC_ADC) Receive Next Pointer Register */ +#define AT91C_ADC_TPR ( 0xFFFD8108 ) /* (PDC_ADC) Transmit Pointer Register */ +#define AT91C_ADC_RPR ( 0xFFFD8100 ) /* (PDC_ADC) Receive Pointer Register */ +#define AT91C_ADC_PTSR ( 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */ +#define AT91C_ADC_TNCR ( 0xFFFD811C ) /* (PDC_ADC) Transmit Next Counter Register */ +#define AT91C_ADC_RNCR ( 0xFFFD8114 ) /* (PDC_ADC) Receive Next Counter Register */ +#define AT91C_ADC_TCR ( 0xFFFD810C ) /* (PDC_ADC) Transmit Counter Register */ +#define AT91C_ADC_RCR ( 0xFFFD8104 ) /* (PDC_ADC) Receive Counter Register */ +/* ========== Register definition for ADC peripheral ========== */ +#define AT91C_ADC_IMR ( 0xFFFD802C ) /* (ADC) ADC Interrupt Mask Register */ +#define AT91C_ADC_CDR4 ( 0xFFFD8040 ) /* (ADC) ADC Channel Data Register 4 */ +#define AT91C_ADC_CDR2 ( 0xFFFD8038 ) /* (ADC) ADC Channel Data Register 2 */ +#define AT91C_ADC_CDR0 ( 0xFFFD8030 ) /* (ADC) ADC Channel Data Register 0 */ +#define AT91C_ADC_CDR7 ( 0xFFFD804C ) /* (ADC) ADC Channel Data Register 7 */ +#define AT91C_ADC_CDR1 ( 0xFFFD8034 ) /* (ADC) ADC Channel Data Register 1 */ +#define AT91C_ADC_CDR3 ( 0xFFFD803C ) /* (ADC) ADC Channel Data Register 3 */ +#define AT91C_ADC_CDR5 ( 0xFFFD8044 ) /* (ADC) ADC Channel Data Register 5 */ +#define AT91C_ADC_MR ( 0xFFFD8004 ) /* (ADC) ADC Mode Register */ +#define AT91C_ADC_CDR6 ( 0xFFFD8048 ) /* (ADC) ADC Channel Data Register 6 */ +#define AT91C_ADC_CR ( 0xFFFD8000 ) /* (ADC) ADC Control Register */ +#define AT91C_ADC_CHER ( 0xFFFD8010 ) /* (ADC) ADC Channel Enable Register */ +#define AT91C_ADC_CHSR ( 0xFFFD8018 ) /* (ADC) ADC Channel Status Register */ +#define AT91C_ADC_IER ( 0xFFFD8024 ) /* (ADC) ADC Interrupt Enable Register */ +#define AT91C_ADC_SR ( 0xFFFD801C ) /* (ADC) ADC Status Register */ +#define AT91C_ADC_CHDR ( 0xFFFD8014 ) /* (ADC) ADC Channel Disable Register */ +#define AT91C_ADC_IDR ( 0xFFFD8028 ) /* (ADC) ADC Interrupt Disable Register */ +#define AT91C_ADC_LCDR ( 0xFFFD8020 ) /* (ADC) ADC Last Converted Data Register */ +/* ========== Register definition for PDC_SSC peripheral ========== */ +#define AT91C_SSC_PTCR ( 0xFFFD4120 ) /* (PDC_SSC) PDC Transfer Control Register */ +#define AT91C_SSC_TNPR ( 0xFFFD4118 ) /* (PDC_SSC) Transmit Next Pointer Register */ +#define AT91C_SSC_RNPR ( 0xFFFD4110 ) /* (PDC_SSC) Receive Next Pointer Register */ +#define AT91C_SSC_TPR ( 0xFFFD4108 ) /* (PDC_SSC) Transmit Pointer Register */ +#define AT91C_SSC_RPR ( 0xFFFD4100 ) /* (PDC_SSC) Receive Pointer Register */ +#define AT91C_SSC_PTSR ( 0xFFFD4124 ) /* (PDC_SSC) PDC Transfer Status Register */ +#define AT91C_SSC_TNCR ( 0xFFFD411C ) /* (PDC_SSC) Transmit Next Counter Register */ +#define AT91C_SSC_RNCR ( 0xFFFD4114 ) /* (PDC_SSC) Receive Next Counter Register */ +#define AT91C_SSC_TCR ( 0xFFFD410C ) /* (PDC_SSC) Transmit Counter Register */ +#define AT91C_SSC_RCR ( 0xFFFD4104 ) /* (PDC_SSC) Receive Counter Register */ +/* ========== Register definition for SSC peripheral ========== */ +#define AT91C_SSC_RFMR ( 0xFFFD4014 ) /* (SSC) Receive Frame Mode Register */ +#define AT91C_SSC_CMR ( 0xFFFD4004 ) /* (SSC) Clock Mode Register */ +#define AT91C_SSC_IDR ( 0xFFFD4048 ) /* (SSC) Interrupt Disable Register */ +#define AT91C_SSC_SR ( 0xFFFD4040 ) /* (SSC) Status Register */ +#define AT91C_SSC_RC0R ( 0xFFFD4038 ) /* (SSC) Receive Compare 0 Register */ +#define AT91C_SSC_RSHR ( 0xFFFD4030 ) /* (SSC) Receive Sync Holding Register */ +#define AT91C_SSC_RHR ( 0xFFFD4020 ) /* (SSC) Receive Holding Register */ +#define AT91C_SSC_TCMR ( 0xFFFD4018 ) /* (SSC) Transmit Clock Mode Register */ +#define AT91C_SSC_RCMR ( 0xFFFD4010 ) /* (SSC) Receive Clock ModeRegister */ +#define AT91C_SSC_CR ( 0xFFFD4000 ) /* (SSC) Control Register */ +#define AT91C_SSC_IMR ( 0xFFFD404C ) /* (SSC) Interrupt Mask Register */ +#define AT91C_SSC_IER ( 0xFFFD4044 ) /* (SSC) Interrupt Enable Register */ +#define AT91C_SSC_RC1R ( 0xFFFD403C ) /* (SSC) Receive Compare 1 Register */ +#define AT91C_SSC_TSHR ( 0xFFFD4034 ) /* (SSC) Transmit Sync Holding Register */ +#define AT91C_SSC_THR ( 0xFFFD4024 ) /* (SSC) Transmit Holding Register */ +#define AT91C_SSC_TFMR ( 0xFFFD401C ) /* (SSC) Transmit Frame Mode Register */ +/* ========== Register definition for PDC_US1 peripheral ========== */ +#define AT91C_US1_PTSR ( 0xFFFC4124 ) /* (PDC_US1) PDC Transfer Status Register */ +#define AT91C_US1_TNCR ( 0xFFFC411C ) /* (PDC_US1) Transmit Next Counter Register */ +#define AT91C_US1_RNCR ( 0xFFFC4114 ) /* (PDC_US1) Receive Next Counter Register */ +#define AT91C_US1_TCR ( 0xFFFC410C ) /* (PDC_US1) Transmit Counter Register */ +#define AT91C_US1_RCR ( 0xFFFC4104 ) /* (PDC_US1) Receive Counter Register */ +#define AT91C_US1_PTCR ( 0xFFFC4120 ) /* (PDC_US1) PDC Transfer Control Register */ +#define AT91C_US1_TNPR ( 0xFFFC4118 ) /* (PDC_US1) Transmit Next Pointer Register */ +#define AT91C_US1_RNPR ( 0xFFFC4110 ) /* (PDC_US1) Receive Next Pointer Register */ +#define AT91C_US1_TPR ( 0xFFFC4108 ) /* (PDC_US1) Transmit Pointer Register */ +#define AT91C_US1_RPR ( 0xFFFC4100 ) /* (PDC_US1) Receive Pointer Register */ +/* ========== Register definition for US1 peripheral ========== */ +#define AT91C_US1_XXR ( 0xFFFC4048 ) /* (US1) XON_XOFF Register */ +#define AT91C_US1_RHR ( 0xFFFC4018 ) /* (US1) Receiver Holding Register */ +#define AT91C_US1_IMR ( 0xFFFC4010 ) /* (US1) Interrupt Mask Register */ +#define AT91C_US1_IER ( 0xFFFC4008 ) /* (US1) Interrupt Enable Register */ +#define AT91C_US1_CR ( 0xFFFC4000 ) /* (US1) Control Register */ +#define AT91C_US1_RTOR ( 0xFFFC4024 ) /* (US1) Receiver Time-out Register */ +#define AT91C_US1_THR ( 0xFFFC401C ) /* (US1) Transmitter Holding Register */ +#define AT91C_US1_CSR ( 0xFFFC4014 ) /* (US1) Channel Status Register */ +#define AT91C_US1_IDR ( 0xFFFC400C ) /* (US1) Interrupt Disable Register */ +#define AT91C_US1_FIDI ( 0xFFFC4040 ) /* (US1) FI_DI_Ratio Register */ +#define AT91C_US1_BRGR ( 0xFFFC4020 ) /* (US1) Baud Rate Generator Register */ +#define AT91C_US1_TTGR ( 0xFFFC4028 ) /* (US1) Transmitter Time-guard Register */ +#define AT91C_US1_IF ( 0xFFFC404C ) /* (US1) IRDA_FILTER Register */ +#define AT91C_US1_NER ( 0xFFFC4044 ) /* (US1) Nb Errors Register */ +#define AT91C_US1_MR ( 0xFFFC4004 ) /* (US1) Mode Register */ +/* ========== Register definition for PDC_US0 peripheral ========== */ +#define AT91C_US0_PTCR ( 0xFFFC0120 ) /* (PDC_US0) PDC Transfer Control Register */ +#define AT91C_US0_TNPR ( 0xFFFC0118 ) /* (PDC_US0) Transmit Next Pointer Register */ +#define AT91C_US0_RNPR ( 0xFFFC0110 ) /* (PDC_US0) Receive Next Pointer Register */ +#define AT91C_US0_TPR ( 0xFFFC0108 ) /* (PDC_US0) Transmit Pointer Register */ +#define AT91C_US0_RPR ( 0xFFFC0100 ) /* (PDC_US0) Receive Pointer Register */ +#define AT91C_US0_PTSR ( 0xFFFC0124 ) /* (PDC_US0) PDC Transfer Status Register */ +#define AT91C_US0_TNCR ( 0xFFFC011C ) /* (PDC_US0) Transmit Next Counter Register */ +#define AT91C_US0_RNCR ( 0xFFFC0114 ) /* (PDC_US0) Receive Next Counter Register */ +#define AT91C_US0_TCR ( 0xFFFC010C ) /* (PDC_US0) Transmit Counter Register */ +#define AT91C_US0_RCR ( 0xFFFC0104 ) /* (PDC_US0) Receive Counter Register */ +/* ========== Register definition for US0 peripheral ========== */ +#define AT91C_US0_TTGR ( 0xFFFC0028 ) /* (US0) Transmitter Time-guard Register */ +#define AT91C_US0_BRGR ( 0xFFFC0020 ) /* (US0) Baud Rate Generator Register */ +#define AT91C_US0_RHR ( 0xFFFC0018 ) /* (US0) Receiver Holding Register */ +#define AT91C_US0_IMR ( 0xFFFC0010 ) /* (US0) Interrupt Mask Register */ +#define AT91C_US0_NER ( 0xFFFC0044 ) /* (US0) Nb Errors Register */ +#define AT91C_US0_RTOR ( 0xFFFC0024 ) /* (US0) Receiver Time-out Register */ +#define AT91C_US0_XXR ( 0xFFFC0048 ) /* (US0) XON_XOFF Register */ +#define AT91C_US0_FIDI ( 0xFFFC0040 ) /* (US0) FI_DI_Ratio Register */ +#define AT91C_US0_CR ( 0xFFFC0000 ) /* (US0) Control Register */ +#define AT91C_US0_IER ( 0xFFFC0008 ) /* (US0) Interrupt Enable Register */ +#define AT91C_US0_IF ( 0xFFFC004C ) /* (US0) IRDA_FILTER Register */ +#define AT91C_US0_MR ( 0xFFFC0004 ) /* (US0) Mode Register */ +#define AT91C_US0_IDR ( 0xFFFC000C ) /* (US0) Interrupt Disable Register */ +#define AT91C_US0_CSR ( 0xFFFC0014 ) /* (US0) Channel Status Register */ +#define AT91C_US0_THR ( 0xFFFC001C ) /* (US0) Transmitter Holding Register */ +/* ========== Register definition for TWI peripheral ========== */ +#define AT91C_TWI_RHR ( 0xFFFB8030 ) /* (TWI) Receive Holding Register */ +#define AT91C_TWI_IDR ( 0xFFFB8028 ) /* (TWI) Interrupt Disable Register */ +#define AT91C_TWI_SR ( 0xFFFB8020 ) /* (TWI) Status Register */ +#define AT91C_TWI_CWGR ( 0xFFFB8010 ) /* (TWI) Clock Waveform Generator Register */ +#define AT91C_TWI_SMR ( 0xFFFB8008 ) /* (TWI) Slave Mode Register */ +#define AT91C_TWI_CR ( 0xFFFB8000 ) /* (TWI) Control Register */ +#define AT91C_TWI_THR ( 0xFFFB8034 ) /* (TWI) Transmit Holding Register */ +#define AT91C_TWI_IMR ( 0xFFFB802C ) /* (TWI) Interrupt Mask Register */ +#define AT91C_TWI_IER ( 0xFFFB8024 ) /* (TWI) Interrupt Enable Register */ +#define AT91C_TWI_IADR ( 0xFFFB800C ) /* (TWI) Internal Address Register */ +#define AT91C_TWI_MMR ( 0xFFFB8004 ) /* (TWI) Master Mode Register */ +/* ========== Register definition for TC2 peripheral ========== */ +#define AT91C_TC2_IMR ( 0xFFFA00AC ) /* (TC2) Interrupt Mask Register */ +#define AT91C_TC2_IER ( 0xFFFA00A4 ) /* (TC2) Interrupt Enable Register */ +#define AT91C_TC2_RC ( 0xFFFA009C ) /* (TC2) Register C */ +#define AT91C_TC2_RA ( 0xFFFA0094 ) /* (TC2) Register A */ +#define AT91C_TC2_CMR ( 0xFFFA0084 ) /* (TC2) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC2_IDR ( 0xFFFA00A8 ) /* (TC2) Interrupt Disable Register */ +#define AT91C_TC2_SR ( 0xFFFA00A0 ) /* (TC2) Status Register */ +#define AT91C_TC2_RB ( 0xFFFA0098 ) /* (TC2) Register B */ +#define AT91C_TC2_CV ( 0xFFFA0090 ) /* (TC2) Counter Value */ +#define AT91C_TC2_CCR ( 0xFFFA0080 ) /* (TC2) Channel Control Register */ +/* ========== Register definition for TC1 peripheral ========== */ +#define AT91C_TC1_IMR ( 0xFFFA006C ) /* (TC1) Interrupt Mask Register */ +#define AT91C_TC1_IER ( 0xFFFA0064 ) /* (TC1) Interrupt Enable Register */ +#define AT91C_TC1_RC ( 0xFFFA005C ) /* (TC1) Register C */ +#define AT91C_TC1_RA ( 0xFFFA0054 ) /* (TC1) Register A */ +#define AT91C_TC1_CMR ( 0xFFFA0044 ) /* (TC1) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC1_IDR ( 0xFFFA0068 ) /* (TC1) Interrupt Disable Register */ +#define AT91C_TC1_SR ( 0xFFFA0060 ) /* (TC1) Status Register */ +#define AT91C_TC1_RB ( 0xFFFA0058 ) /* (TC1) Register B */ +#define AT91C_TC1_CV ( 0xFFFA0050 ) /* (TC1) Counter Value */ +#define AT91C_TC1_CCR ( 0xFFFA0040 ) /* (TC1) Channel Control Register */ +/* ========== Register definition for TC0 peripheral ========== */ +#define AT91C_TC0_IMR ( 0xFFFA002C ) /* (TC0) Interrupt Mask Register */ +#define AT91C_TC0_IER ( 0xFFFA0024 ) /* (TC0) Interrupt Enable Register */ +#define AT91C_TC0_RC ( 0xFFFA001C ) /* (TC0) Register C */ +#define AT91C_TC0_RA ( 0xFFFA0014 ) /* (TC0) Register A */ +#define AT91C_TC0_CMR ( 0xFFFA0004 ) /* (TC0) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC0_IDR ( 0xFFFA0028 ) /* (TC0) Interrupt Disable Register */ +#define AT91C_TC0_SR ( 0xFFFA0020 ) /* (TC0) Status Register */ +#define AT91C_TC0_RB ( 0xFFFA0018 ) /* (TC0) Register B */ +#define AT91C_TC0_CV ( 0xFFFA0010 ) /* (TC0) Counter Value */ +#define AT91C_TC0_CCR ( 0xFFFA0000 ) /* (TC0) Channel Control Register */ +/* ========== Register definition for TCB peripheral ========== */ +#define AT91C_TCB_BMR ( 0xFFFA00C4 ) /* (TCB) TC Block Mode Register */ +#define AT91C_TCB_BCR ( 0xFFFA00C0 ) /* (TCB) TC Block Control Register */ +/* ========== Register definition for PWMC_CH3 peripheral ========== */ +#define AT91C_CH3_CUPDR ( 0xFFFCC270 ) /* (PWMC_CH3) Channel Update Register */ +#define AT91C_CH3_CPRDR ( 0xFFFCC268 ) /* (PWMC_CH3) Channel Period Register */ +#define AT91C_CH3_CMR ( 0xFFFCC260 ) /* (PWMC_CH3) Channel Mode Register */ +#define AT91C_CH3_Reserved ( 0xFFFCC274 ) /* (PWMC_CH3) Reserved */ +#define AT91C_CH3_CCNTR ( 0xFFFCC26C ) /* (PWMC_CH3) Channel Counter Register */ +#define AT91C_CH3_CDTYR ( 0xFFFCC264 ) /* (PWMC_CH3) Channel Duty Cycle Register */ +/* ========== Register definition for PWMC_CH2 peripheral ========== */ +#define AT91C_CH2_CUPDR ( 0xFFFCC250 ) /* (PWMC_CH2) Channel Update Register */ +#define AT91C_CH2_CPRDR ( 0xFFFCC248 ) /* (PWMC_CH2) Channel Period Register */ +#define AT91C_CH2_CMR ( 0xFFFCC240 ) /* (PWMC_CH2) Channel Mode Register */ +#define AT91C_CH2_Reserved ( 0xFFFCC254 ) /* (PWMC_CH2) Reserved */ +#define AT91C_CH2_CCNTR ( 0xFFFCC24C ) /* (PWMC_CH2) Channel Counter Register */ +#define AT91C_CH2_CDTYR ( 0xFFFCC244 ) /* (PWMC_CH2) Channel Duty Cycle Register */ +/* ========== Register definition for PWMC_CH1 peripheral ========== */ +#define AT91C_CH1_CUPDR ( 0xFFFCC230 ) /* (PWMC_CH1) Channel Update Register */ +#define AT91C_CH1_CPRDR ( 0xFFFCC228 ) /* (PWMC_CH1) Channel Period Register */ +#define AT91C_CH1_CMR ( 0xFFFCC220 ) /* (PWMC_CH1) Channel Mode Register */ +#define AT91C_CH1_Reserved ( 0xFFFCC234 ) /* (PWMC_CH1) Reserved */ +#define AT91C_CH1_CCNTR ( 0xFFFCC22C ) /* (PWMC_CH1) Channel Counter Register */ +#define AT91C_CH1_CDTYR ( 0xFFFCC224 ) /* (PWMC_CH1) Channel Duty Cycle Register */ +/* ========== Register definition for PWMC_CH0 peripheral ========== */ +#define AT91C_CH0_CUPDR ( 0xFFFCC210 ) /* (PWMC_CH0) Channel Update Register */ +#define AT91C_CH0_CPRDR ( 0xFFFCC208 ) /* (PWMC_CH0) Channel Period Register */ +#define AT91C_CH0_CMR ( 0xFFFCC200 ) /* (PWMC_CH0) Channel Mode Register */ +#define AT91C_CH0_Reserved ( 0xFFFCC214 ) /* (PWMC_CH0) Reserved */ +#define AT91C_CH0_CCNTR ( 0xFFFCC20C ) /* (PWMC_CH0) Channel Counter Register */ +#define AT91C_CH0_CDTYR ( 0xFFFCC204 ) /* (PWMC_CH0) Channel Duty Cycle Register */ +/* ========== Register definition for PWMC peripheral ========== */ +#define AT91C_PWMC_VR ( 0xFFFCC0FC ) /* (PWMC) PWMC Version Register */ +#define AT91C_PWMC_ISR ( 0xFFFCC01C ) /* (PWMC) PWMC Interrupt Status Register */ +#define AT91C_PWMC_IDR ( 0xFFFCC014 ) /* (PWMC) PWMC Interrupt Disable Register */ +#define AT91C_PWMC_SR ( 0xFFFCC00C ) /* (PWMC) PWMC Status Register */ +#define AT91C_PWMC_ENA ( 0xFFFCC004 ) /* (PWMC) PWMC Enable Register */ +#define AT91C_PWMC_IMR ( 0xFFFCC018 ) /* (PWMC) PWMC Interrupt Mask Register */ +#define AT91C_PWMC_MR ( 0xFFFCC000 ) /* (PWMC) PWMC Mode Register */ +#define AT91C_PWMC_DIS ( 0xFFFCC008 ) /* (PWMC) PWMC Disable Register */ +#define AT91C_PWMC_IER ( 0xFFFCC010 ) /* (PWMC) PWMC Interrupt Enable Register */ +/* ========== Register definition for UDP peripheral ========== */ +#define AT91C_UDP_ISR ( 0xFFFB001C ) /* (UDP) Interrupt Status Register */ +#define AT91C_UDP_IDR ( 0xFFFB0014 ) /* (UDP) Interrupt Disable Register */ +#define AT91C_UDP_GLBSTATE ( 0xFFFB0004 ) /* (UDP) Global State Register */ +#define AT91C_UDP_FDR ( 0xFFFB0050 ) /* (UDP) Endpoint FIFO Data Register */ +#define AT91C_UDP_CSR ( 0xFFFB0030 ) /* (UDP) Endpoint Control and Status Register */ +#define AT91C_UDP_RSTEP ( 0xFFFB0028 ) /* (UDP) Reset Endpoint Register */ +#define AT91C_UDP_ICR ( 0xFFFB0020 ) /* (UDP) Interrupt Clear Register */ +#define AT91C_UDP_IMR ( 0xFFFB0018 ) /* (UDP) Interrupt Mask Register */ +#define AT91C_UDP_IER ( 0xFFFB0010 ) /* (UDP) Interrupt Enable Register */ +#define AT91C_UDP_FADDR ( 0xFFFB0008 ) /* (UDP) Function Address Register */ +#define AT91C_UDP_NUM ( 0xFFFB0000 ) /* (UDP) Frame Number Register */ + +/* ***************************************************************************** */ +/* PIO DEFINITIONS FOR AT91SAM7S64 */ +/* ***************************************************************************** */ +#define AT91C_PIO_PA0 ( 1 << 0 ) /* Pin Controlled by PA0 */ +#define AT91C_PA0_PWM0 ( AT91C_PIO_PA0 ) /* PWM Channel 0 */ +#define AT91C_PA0_TIOA0 ( AT91C_PIO_PA0 ) /* Timer Counter 0 Multipurpose Timer I/O Pin A */ +#define AT91C_PIO_PA1 ( 1 << 1 ) /* Pin Controlled by PA1 */ +#define AT91C_PA1_PWM1 ( AT91C_PIO_PA1 ) /* PWM Channel 1 */ +#define AT91C_PA1_TIOB0 ( AT91C_PIO_PA1 ) /* Timer Counter 0 Multipurpose Timer I/O Pin B */ +#define AT91C_PIO_PA10 ( 1 << 10 ) /* Pin Controlled by PA10 */ +#define AT91C_PA10_DTXD ( AT91C_PIO_PA10 ) /* DBGU Debug Transmit Data */ +#define AT91C_PA10_NPCS2 ( AT91C_PIO_PA10 ) /* SPI Peripheral Chip Select 2 */ +#define AT91C_PIO_PA11 ( 1 << 11 ) /* Pin Controlled by PA11 */ +#define AT91C_PA11_NPCS0 ( AT91C_PIO_PA11 ) /* SPI Peripheral Chip Select 0 */ +#define AT91C_PA11_PWM0 ( AT91C_PIO_PA11 ) /* PWM Channel 0 */ +#define AT91C_PIO_PA12 ( 1 << 12 ) /* Pin Controlled by PA12 */ +#define AT91C_PA12_MISO ( AT91C_PIO_PA12 ) /* SPI Master In Slave */ +#define AT91C_PA12_PWM1 ( AT91C_PIO_PA12 ) /* PWM Channel 1 */ +#define AT91C_PIO_PA13 ( 1 << 13 ) /* Pin Controlled by PA13 */ +#define AT91C_PA13_MOSI ( AT91C_PIO_PA13 ) /* SPI Master Out Slave */ +#define AT91C_PA13_PWM2 ( AT91C_PIO_PA13 ) /* PWM Channel 2 */ +#define AT91C_PIO_PA14 ( 1 << 14 ) /* Pin Controlled by PA14 */ +#define AT91C_PA14_SPCK ( AT91C_PIO_PA14 ) /* SPI Serial Clock */ +#define AT91C_PA14_PWM3 ( AT91C_PIO_PA14 ) /* PWM Channel 3 */ +#define AT91C_PIO_PA15 ( 1 << 15 ) /* Pin Controlled by PA15 */ +#define AT91C_PA15_TF ( AT91C_PIO_PA15 ) /* SSC Transmit Frame Sync */ +#define AT91C_PA15_TIOA1 ( AT91C_PIO_PA15 ) /* Timer Counter 1 Multipurpose Timer I/O Pin A */ +#define AT91C_PIO_PA16 ( 1 << 16 ) /* Pin Controlled by PA16 */ +#define AT91C_PA16_TK ( AT91C_PIO_PA16 ) /* SSC Transmit Clock */ +#define AT91C_PA16_TIOB1 ( AT91C_PIO_PA16 ) /* Timer Counter 1 Multipurpose Timer I/O Pin B */ +#define AT91C_PIO_PA17 ( 1 << 17 ) /* Pin Controlled by PA17 */ +#define AT91C_PA17_TD ( AT91C_PIO_PA17 ) /* SSC Transmit data */ +#define AT91C_PA17_PCK1 ( AT91C_PIO_PA17 ) /* PMC Programmable Clock Output 1 */ +#define AT91C_PIO_PA18 ( 1 << 18 ) /* Pin Controlled by PA18 */ +#define AT91C_PA18_RD ( AT91C_PIO_PA18 ) /* SSC Receive Data */ +#define AT91C_PA18_PCK2 ( AT91C_PIO_PA18 ) /* PMC Programmable Clock Output 2 */ +#define AT91C_PIO_PA19 ( 1 << 19 ) /* Pin Controlled by PA19 */ +#define AT91C_PA19_RK ( AT91C_PIO_PA19 ) /* SSC Receive Clock */ +#define AT91C_PA19_FIQ ( AT91C_PIO_PA19 ) /* AIC Fast Interrupt Input */ +#define AT91C_PIO_PA2 ( 1 << 2 ) /* Pin Controlled by PA2 */ +#define AT91C_PA2_PWM2 ( AT91C_PIO_PA2 ) /* PWM Channel 2 */ +#define AT91C_PA2_SCK0 ( AT91C_PIO_PA2 ) /* USART 0 Serial Clock */ +#define AT91C_PIO_PA20 ( 1 << 20 ) /* Pin Controlled by PA20 */ +#define AT91C_PA20_RF ( AT91C_PIO_PA20 ) /* SSC Receive Frame Sync */ +#define AT91C_PA20_IRQ0 ( AT91C_PIO_PA20 ) /* External Interrupt 0 */ +#define AT91C_PIO_PA21 ( 1 << 21 ) /* Pin Controlled by PA21 */ +#define AT91C_PA21_RXD1 ( AT91C_PIO_PA21 ) /* USART 1 Receive Data */ +#define AT91C_PA21_PCK1 ( AT91C_PIO_PA21 ) /* PMC Programmable Clock Output 1 */ +#define AT91C_PIO_PA22 ( 1 << 22 ) /* Pin Controlled by PA22 */ +#define AT91C_PA22_TXD1 ( AT91C_PIO_PA22 ) /* USART 1 Transmit Data */ +#define AT91C_PA22_NPCS3 ( AT91C_PIO_PA22 ) /* SPI Peripheral Chip Select 3 */ +#define AT91C_PIO_PA23 ( 1 << 23 ) /* Pin Controlled by PA23 */ +#define AT91C_PA23_SCK1 ( AT91C_PIO_PA23 ) /* USART 1 Serial Clock */ +#define AT91C_PA23_PWM0 ( AT91C_PIO_PA23 ) /* PWM Channel 0 */ +#define AT91C_PIO_PA24 ( 1 << 24 ) /* Pin Controlled by PA24 */ +#define AT91C_PA24_RTS1 ( AT91C_PIO_PA24 ) /* USART 1 Ready To Send */ +#define AT91C_PA24_PWM1 ( AT91C_PIO_PA24 ) /* PWM Channel 1 */ +#define AT91C_PIO_PA25 ( 1 << 25 ) /* Pin Controlled by PA25 */ +#define AT91C_PA25_CTS1 ( AT91C_PIO_PA25 ) /* USART 1 Clear To Send */ +#define AT91C_PA25_PWM2 ( AT91C_PIO_PA25 ) /* PWM Channel 2 */ +#define AT91C_PIO_PA26 ( 1 << 26 ) /* Pin Controlled by PA26 */ +#define AT91C_PA26_DCD1 ( AT91C_PIO_PA26 ) /* USART 1 Data Carrier Detect */ +#define AT91C_PA26_TIOA2 ( AT91C_PIO_PA26 ) /* Timer Counter 2 Multipurpose Timer I/O Pin A */ +#define AT91C_PIO_PA27 ( 1 << 27 ) /* Pin Controlled by PA27 */ +#define AT91C_PA27_DTR1 ( AT91C_PIO_PA27 ) /* USART 1 Data Terminal ready */ +#define AT91C_PA27_TIOB2 ( AT91C_PIO_PA27 ) /* Timer Counter 2 Multipurpose Timer I/O Pin B */ +#define AT91C_PIO_PA28 ( 1 << 28 ) /* Pin Controlled by PA28 */ +#define AT91C_PA28_DSR1 ( AT91C_PIO_PA28 ) /* USART 1 Data Set ready */ +#define AT91C_PA28_TCLK1 ( AT91C_PIO_PA28 ) /* Timer Counter 1 external clock input */ +#define AT91C_PIO_PA29 ( 1 << 29 ) /* Pin Controlled by PA29 */ +#define AT91C_PA29_RI1 ( AT91C_PIO_PA29 ) /* USART 1 Ring Indicator */ +#define AT91C_PA29_TCLK2 ( AT91C_PIO_PA29 ) /* Timer Counter 2 external clock input */ +#define AT91C_PIO_PA3 ( 1 << 3 ) /* Pin Controlled by PA3 */ +#define AT91C_PA3_TWD ( AT91C_PIO_PA3 ) /* TWI Two-wire Serial Data */ +#define AT91C_PA3_NPCS3 ( AT91C_PIO_PA3 ) /* SPI Peripheral Chip Select 3 */ +#define AT91C_PIO_PA30 ( 1 << 30 ) /* Pin Controlled by PA30 */ +#define AT91C_PA30_IRQ1 ( AT91C_PIO_PA30 ) /* External Interrupt 1 */ +#define AT91C_PA30_NPCS2 ( AT91C_PIO_PA30 ) /* SPI Peripheral Chip Select 2 */ +#define AT91C_PIO_PA31 ( 1 << 31 ) /* Pin Controlled by PA31 */ +#define AT91C_PA31_NPCS1 ( AT91C_PIO_PA31 ) /* SPI Peripheral Chip Select 1 */ +#define AT91C_PA31_PCK2 ( AT91C_PIO_PA31 ) /* PMC Programmable Clock Output 2 */ +#define AT91C_PIO_PA4 ( 1 << 4 ) /* Pin Controlled by PA4 */ +#define AT91C_PA4_TWCK ( AT91C_PIO_PA4 ) /* TWI Two-wire Serial Clock */ +#define AT91C_PA4_TCLK0 ( AT91C_PIO_PA4 ) /* Timer Counter 0 external clock input */ +#define AT91C_PIO_PA5 ( 1 << 5 ) /* Pin Controlled by PA5 */ +#define AT91C_PA5_RXD0 ( AT91C_PIO_PA5 ) /* USART 0 Receive Data */ +#define AT91C_PA5_NPCS3 ( AT91C_PIO_PA5 ) /* SPI Peripheral Chip Select 3 */ +#define AT91C_PIO_PA6 ( 1 << 6 ) /* Pin Controlled by PA6 */ +#define AT91C_PA6_TXD0 ( AT91C_PIO_PA6 ) /* USART 0 Transmit Data */ +#define AT91C_PA6_PCK0 ( AT91C_PIO_PA6 ) /* PMC Programmable Clock Output 0 */ +#define AT91C_PIO_PA7 ( 1 << 7 ) /* Pin Controlled by PA7 */ +#define AT91C_PA7_RTS0 ( AT91C_PIO_PA7 ) /* USART 0 Ready To Send */ +#define AT91C_PA7_PWM3 ( AT91C_PIO_PA7 ) /* PWM Channel 3 */ +#define AT91C_PIO_PA8 ( 1 << 8 ) /* Pin Controlled by PA8 */ +#define AT91C_PA8_CTS0 ( AT91C_PIO_PA8 ) /* USART 0 Clear To Send */ +#define AT91C_PA8_ADTRG ( AT91C_PIO_PA8 ) /* ADC External Trigger */ +#define AT91C_PIO_PA9 ( 1 << 9 ) /* Pin Controlled by PA9 */ +#define AT91C_PA9_DRXD ( AT91C_PIO_PA9 ) /* DBGU Debug Receive Data */ +#define AT91C_PA9_NPCS1 ( AT91C_PIO_PA9 ) /* SPI Peripheral Chip Select 1 */ + +/* ***************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64 */ +/* ***************************************************************************** */ +#define AT91C_ID_FIQ ( 0 ) /* Advanced Interrupt Controller (FIQ) */ +#define AT91C_ID_SYS ( 1 ) /* System Peripheral */ +#define AT91C_ID_PIOA ( 2 ) /* Parallel IO Controller */ +#define AT91C_ID_3_Reserved ( 3 ) /* Reserved */ +#define AT91C_ID_ADC ( 4 ) /* Analog-to-Digital Converter */ +#define AT91C_ID_SPI ( 5 ) /* Serial Peripheral Interface */ +#define AT91C_ID_US0 ( 6 ) /* USART 0 */ +#define AT91C_ID_US1 ( 7 ) /* USART 1 */ +#define AT91C_ID_SSC ( 8 ) /* Serial Synchronous Controller */ +#define AT91C_ID_TWI ( 9 ) /* Two-Wire Interface */ +#define AT91C_ID_PWMC ( 10 ) /* PWM Controller */ +#define AT91C_ID_UDP ( 11 ) /* USB Device Port */ +#define AT91C_ID_TC0 ( 12 ) /* Timer Counter 0 */ +#define AT91C_ID_TC1 ( 13 ) /* Timer Counter 1 */ +#define AT91C_ID_TC2 ( 14 ) /* Timer Counter 2 */ +#define AT91C_ID_15_Reserved ( 15 ) /* Reserved */ +#define AT91C_ID_16_Reserved ( 16 ) /* Reserved */ +#define AT91C_ID_17_Reserved ( 17 ) /* Reserved */ +#define AT91C_ID_18_Reserved ( 18 ) /* Reserved */ +#define AT91C_ID_19_Reserved ( 19 ) /* Reserved */ +#define AT91C_ID_20_Reserved ( 20 ) /* Reserved */ +#define AT91C_ID_21_Reserved ( 21 ) /* Reserved */ +#define AT91C_ID_22_Reserved ( 22 ) /* Reserved */ +#define AT91C_ID_23_Reserved ( 23 ) /* Reserved */ +#define AT91C_ID_24_Reserved ( 24 ) /* Reserved */ +#define AT91C_ID_25_Reserved ( 25 ) /* Reserved */ +#define AT91C_ID_26_Reserved ( 26 ) /* Reserved */ +#define AT91C_ID_27_Reserved ( 27 ) /* Reserved */ +#define AT91C_ID_28_Reserved ( 28 ) /* Reserved */ +#define AT91C_ID_29_Reserved ( 29 ) /* Reserved */ +#define AT91C_ID_IRQ0 ( 30 ) /* Advanced Interrupt Controller (IRQ0) */ +#define AT91C_ID_IRQ1 ( 31 ) /* Advanced Interrupt Controller (IRQ1) */ + +/* ***************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR AT91SAM7S64 */ +/* ***************************************************************************** */ +#define AT91C_BASE_SYSC ( 0xFFFFF000 ) /* (SYSC) Base Address */ +#define AT91C_BASE_AIC ( 0xFFFFF000 ) /* (AIC) Base Address */ +#define AT91C_BASE_DBGU ( 0xFFFFF200 ) /* (DBGU) Base Address */ +#define AT91C_BASE_PDC_DBGU ( 0xFFFFF300 ) /* (PDC_DBGU) Base Address */ +#define AT91C_BASE_PIOA ( 0xFFFFF400 ) /* (PIOA) Base Address */ +#define AT91C_BASE_CKGR ( 0xFFFFFC20 ) /* (CKGR) Base Address */ +#define AT91C_BASE_PMC ( 0xFFFFFC00 ) /* (PMC) Base Address */ +#define AT91C_BASE_RSTC ( 0xFFFFFD00 ) /* (RSTC) Base Address */ +#define AT91C_BASE_RTTC ( 0xFFFFFD20 ) /* (RTTC) Base Address */ +#define AT91C_BASE_PITC ( 0xFFFFFD30 ) /* (PITC) Base Address */ +#define AT91C_BASE_WDTC ( 0xFFFFFD40 ) /* (WDTC) Base Address */ +#define AT91C_BASE_MC ( 0xFFFFFF00 ) /* (MC) Base Address */ +#define AT91C_BASE_PDC_SPI ( 0xFFFE0100 ) /* (PDC_SPI) Base Address */ +#define AT91C_BASE_SPI ( 0xFFFE0000 ) /* (SPI) Base Address */ +#define AT91C_BASE_PDC_ADC ( 0xFFFD8100 ) /* (PDC_ADC) Base Address */ +#define AT91C_BASE_ADC ( 0xFFFD8000 ) /* (ADC) Base Address */ +#define AT91C_BASE_PDC_SSC ( 0xFFFD4100 ) /* (PDC_SSC) Base Address */ +#define AT91C_BASE_SSC ( 0xFFFD4000 ) /* (SSC) Base Address */ +#define AT91C_BASE_PDC_US1 ( 0xFFFC4100 ) /* (PDC_US1) Base Address */ +#define AT91C_BASE_US1 ( 0xFFFC4000 ) /* (US1) Base Address */ +#define AT91C_BASE_PDC_US0 ( 0xFFFC0100 ) /* (PDC_US0) Base Address */ +#define AT91C_BASE_US0 ( 0xFFFC0000 ) /* (US0) Base Address */ +#define AT91C_BASE_TWI ( 0xFFFB8000 ) /* (TWI) Base Address */ +#define AT91C_BASE_TC2 ( 0xFFFA0080 ) /* (TC2) Base Address */ +#define AT91C_BASE_TC1 ( 0xFFFA0040 ) /* (TC1) Base Address */ +#define AT91C_BASE_TC0 ( 0xFFFA0000 ) /* (TC0) Base Address */ +#define AT91C_BASE_TCB ( 0xFFFA0000 ) /* (TCB) Base Address */ +#define AT91C_BASE_PWMC_CH3 ( 0xFFFCC260 ) /* (PWMC_CH3) Base Address */ +#define AT91C_BASE_PWMC_CH2 ( 0xFFFCC240 ) /* (PWMC_CH2) Base Address */ +#define AT91C_BASE_PWMC_CH1 ( 0xFFFCC220 ) /* (PWMC_CH1) Base Address */ +#define AT91C_BASE_PWMC_CH0 ( 0xFFFCC200 ) /* (PWMC_CH0) Base Address */ +#define AT91C_BASE_PWMC ( 0xFFFCC000 ) /* (PWMC) Base Address */ +#define AT91C_BASE_UDP ( 0xFFFB0000 ) /* (UDP) Base Address */ + +/* ***************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64 */ +/* ***************************************************************************** */ +#define AT91C_ISRAM ( 0x00200000 ) /* Internal SRAM base address */ +#define AT91C_ISRAM_SIZE ( 0x00004000 ) /* Internal SRAM size in byte (16 Kbyte) */ +#define AT91C_IFLASH ( 0x00100000 ) /* Internal ROM base address */ +#define AT91C_IFLASH_SIZE ( 0x00010000 ) /* Internal ROM size in byte (64 Kbyte) */ diff --git a/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h b/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h new file mode 100644 index 000000000..a143430db --- /dev/null +++ b/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h @@ -0,0 +1,2743 @@ +/* ---------------------------------------------------------------------------- */ +/* ATMEL Microcontroller Software Support - ROUSSET - */ +/* ---------------------------------------------------------------------------- */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ +/* File Name : AT91SAM7X128.h */ +/* Object : AT91SAM7X128 definitions */ +/* Generated : AT91 SW Application Group 05/20/2005 (16:22:23) */ +/* */ +/* CVS Reference : /AT91SAM7X128.pl/1.14/Tue May 10 12:12:05 2005// */ +/* CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// */ +/* CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// */ +/* CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// */ +/* CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// */ +/* CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// */ +/* CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// */ +/* CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// */ +/* CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// */ +/* CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// */ +/* CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// */ +/* CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// */ +/* CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// */ +/* CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// */ +/* CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// */ +/* CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// */ +/* CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// */ +/* CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// */ +/* CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// */ +/* CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// */ +/* CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// */ +/* CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// */ +/* CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// */ +/* CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// */ +/* CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// */ +/* ---------------------------------------------------------------------------- */ + +#ifndef AT91SAM7X128_H +#define AT91SAM7X128_H + +typedef volatile unsigned int AT91_REG; /* Hardware register definition */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR System Peripherals */ +/* ***************************************************************************** */ +typedef struct _AT91S_SYS +{ + AT91_REG AIC_SMR[ 32 ]; /* Source Mode Register */ + AT91_REG AIC_SVR[ 32 ]; /* Source Vector Register */ + AT91_REG AIC_IVR; /* IRQ Vector Register */ + AT91_REG AIC_FVR; /* FIQ Vector Register */ + AT91_REG AIC_ISR; /* Interrupt Status Register */ + AT91_REG AIC_IPR; /* Interrupt Pending Register */ + AT91_REG AIC_IMR; /* Interrupt Mask Register */ + AT91_REG AIC_CISR; /* Core Interrupt Status Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG AIC_IECR; /* Interrupt Enable Command Register */ + AT91_REG AIC_IDCR; /* Interrupt Disable Command Register */ + AT91_REG AIC_ICCR; /* Interrupt Clear Command Register */ + AT91_REG AIC_ISCR; /* Interrupt Set Command Register */ + AT91_REG AIC_EOICR; /* End of Interrupt Command Register */ + AT91_REG AIC_SPU; /* Spurious Vector Register */ + AT91_REG AIC_DCR; /* Debug Control Register (Protect) */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG AIC_FFER; /* Fast Forcing Enable Register */ + AT91_REG AIC_FFDR; /* Fast Forcing Disable Register */ + AT91_REG AIC_FFSR; /* Fast Forcing Status Register */ + AT91_REG Reserved2[ 45 ]; /* */ + AT91_REG DBGU_CR; /* Control Register */ + AT91_REG DBGU_MR; /* Mode Register */ + AT91_REG DBGU_IER; /* Interrupt Enable Register */ + AT91_REG DBGU_IDR; /* Interrupt Disable Register */ + AT91_REG DBGU_IMR; /* Interrupt Mask Register */ + AT91_REG DBGU_CSR; /* Channel Status Register */ + AT91_REG DBGU_RHR; /* Receiver Holding Register */ + AT91_REG DBGU_THR; /* Transmitter Holding Register */ + AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */ + AT91_REG Reserved3[ 7 ]; /* */ + AT91_REG DBGU_CIDR; /* Chip ID Register */ + AT91_REG DBGU_EXID; /* Chip ID Extension Register */ + AT91_REG DBGU_FNTR; /* Force NTRST Register */ + AT91_REG Reserved4[ 45 ]; /* */ + AT91_REG DBGU_RPR; /* Receive Pointer Register */ + AT91_REG DBGU_RCR; /* Receive Counter Register */ + AT91_REG DBGU_TPR; /* Transmit Pointer Register */ + AT91_REG DBGU_TCR; /* Transmit Counter Register */ + AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */ + AT91_REG DBGU_RNCR; /* Receive Next Counter Register */ + AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */ + AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */ + AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */ + AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */ + AT91_REG Reserved5[ 54 ]; /* */ + AT91_REG PIOA_PER; /* PIO Enable Register */ + AT91_REG PIOA_PDR; /* PIO Disable Register */ + AT91_REG PIOA_PSR; /* PIO Status Register */ + AT91_REG Reserved6[ 1 ]; /* */ + AT91_REG PIOA_OER; /* Output Enable Register */ + AT91_REG PIOA_ODR; /* Output Disable Registerr */ + AT91_REG PIOA_OSR; /* Output Status Register */ + AT91_REG Reserved7[ 1 ]; /* */ + AT91_REG PIOA_IFER; /* Input Filter Enable Register */ + AT91_REG PIOA_IFDR; /* Input Filter Disable Register */ + AT91_REG PIOA_IFSR; /* Input Filter Status Register */ + AT91_REG Reserved8[ 1 ]; /* */ + AT91_REG PIOA_SODR; /* Set Output Data Register */ + AT91_REG PIOA_CODR; /* Clear Output Data Register */ + AT91_REG PIOA_ODSR; /* Output Data Status Register */ + AT91_REG PIOA_PDSR; /* Pin Data Status Register */ + AT91_REG PIOA_IER; /* Interrupt Enable Register */ + AT91_REG PIOA_IDR; /* Interrupt Disable Register */ + AT91_REG PIOA_IMR; /* Interrupt Mask Register */ + AT91_REG PIOA_ISR; /* Interrupt Status Register */ + AT91_REG PIOA_MDER; /* Multi-driver Enable Register */ + AT91_REG PIOA_MDDR; /* Multi-driver Disable Register */ + AT91_REG PIOA_MDSR; /* Multi-driver Status Register */ + AT91_REG Reserved9[ 1 ]; /* */ + AT91_REG PIOA_PPUDR; /* Pull-up Disable Register */ + AT91_REG PIOA_PPUER; /* Pull-up Enable Register */ + AT91_REG PIOA_PPUSR; /* Pull-up Status Register */ + AT91_REG Reserved10[ 1 ]; /* */ + AT91_REG PIOA_ASR; /* Select A Register */ + AT91_REG PIOA_BSR; /* Select B Register */ + AT91_REG PIOA_ABSR; /* AB Select Status Register */ + AT91_REG Reserved11[ 9 ]; /* */ + AT91_REG PIOA_OWER; /* Output Write Enable Register */ + AT91_REG PIOA_OWDR; /* Output Write Disable Register */ + AT91_REG PIOA_OWSR; /* Output Write Status Register */ + AT91_REG Reserved12[ 85 ]; /* */ + AT91_REG PIOB_PER; /* PIO Enable Register */ + AT91_REG PIOB_PDR; /* PIO Disable Register */ + AT91_REG PIOB_PSR; /* PIO Status Register */ + AT91_REG Reserved13[ 1 ]; /* */ + AT91_REG PIOB_OER; /* Output Enable Register */ + AT91_REG PIOB_ODR; /* Output Disable Registerr */ + AT91_REG PIOB_OSR; /* Output Status Register */ + AT91_REG Reserved14[ 1 ]; /* */ + AT91_REG PIOB_IFER; /* Input Filter Enable Register */ + AT91_REG PIOB_IFDR; /* Input Filter Disable Register */ + AT91_REG PIOB_IFSR; /* Input Filter Status Register */ + AT91_REG Reserved15[ 1 ]; /* */ + AT91_REG PIOB_SODR; /* Set Output Data Register */ + AT91_REG PIOB_CODR; /* Clear Output Data Register */ + AT91_REG PIOB_ODSR; /* Output Data Status Register */ + AT91_REG PIOB_PDSR; /* Pin Data Status Register */ + AT91_REG PIOB_IER; /* Interrupt Enable Register */ + AT91_REG PIOB_IDR; /* Interrupt Disable Register */ + AT91_REG PIOB_IMR; /* Interrupt Mask Register */ + AT91_REG PIOB_ISR; /* Interrupt Status Register */ + AT91_REG PIOB_MDER; /* Multi-driver Enable Register */ + AT91_REG PIOB_MDDR; /* Multi-driver Disable Register */ + AT91_REG PIOB_MDSR; /* Multi-driver Status Register */ + AT91_REG Reserved16[ 1 ]; /* */ + AT91_REG PIOB_PPUDR; /* Pull-up Disable Register */ + AT91_REG PIOB_PPUER; /* Pull-up Enable Register */ + AT91_REG PIOB_PPUSR; /* Pull-up Status Register */ + AT91_REG Reserved17[ 1 ]; /* */ + AT91_REG PIOB_ASR; /* Select A Register */ + AT91_REG PIOB_BSR; /* Select B Register */ + AT91_REG PIOB_ABSR; /* AB Select Status Register */ + AT91_REG Reserved18[ 9 ]; /* */ + AT91_REG PIOB_OWER; /* Output Write Enable Register */ + AT91_REG PIOB_OWDR; /* Output Write Disable Register */ + AT91_REG PIOB_OWSR; /* Output Write Status Register */ + AT91_REG Reserved19[ 341 ]; /* */ + AT91_REG PMC_SCER; /* System Clock Enable Register */ + AT91_REG PMC_SCDR; /* System Clock Disable Register */ + AT91_REG PMC_SCSR; /* System Clock Status Register */ + AT91_REG Reserved20[ 1 ]; /* */ + AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */ + AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */ + AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */ + AT91_REG Reserved21[ 1 ]; /* */ + AT91_REG PMC_MOR; /* Main Oscillator Register */ + AT91_REG PMC_MCFR; /* Main Clock Frequency Register */ + AT91_REG Reserved22[ 1 ]; /* */ + AT91_REG PMC_PLLR; /* PLL Register */ + AT91_REG PMC_MCKR; /* Master Clock Register */ + AT91_REG Reserved23[ 3 ]; /* */ + AT91_REG PMC_PCKR[ 4 ]; /* Programmable Clock Register */ + AT91_REG Reserved24[ 4 ]; /* */ + AT91_REG PMC_IER; /* Interrupt Enable Register */ + AT91_REG PMC_IDR; /* Interrupt Disable Register */ + AT91_REG PMC_SR; /* Status Register */ + AT91_REG PMC_IMR; /* Interrupt Mask Register */ + AT91_REG Reserved25[ 36 ]; /* */ + AT91_REG RSTC_RCR; /* Reset Control Register */ + AT91_REG RSTC_RSR; /* Reset Status Register */ + AT91_REG RSTC_RMR; /* Reset Mode Register */ + AT91_REG Reserved26[ 5 ]; /* */ + AT91_REG RTTC_RTMR; /* Real-time Mode Register */ + AT91_REG RTTC_RTAR; /* Real-time Alarm Register */ + AT91_REG RTTC_RTVR; /* Real-time Value Register */ + AT91_REG RTTC_RTSR; /* Real-time Status Register */ + AT91_REG PITC_PIMR; /* Period Interval Mode Register */ + AT91_REG PITC_PISR; /* Period Interval Status Register */ + AT91_REG PITC_PIVR; /* Period Interval Value Register */ + AT91_REG PITC_PIIR; /* Period Interval Image Register */ + AT91_REG WDTC_WDCR; /* Watchdog Control Register */ + AT91_REG WDTC_WDMR; /* Watchdog Mode Register */ + AT91_REG WDTC_WDSR; /* Watchdog Status Register */ + AT91_REG Reserved27[ 5 ]; /* */ + AT91_REG VREG_MR; /* Voltage Regulator Mode Register */ +} AT91S_SYS, * AT91PS_SYS; + + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Advanced Interrupt Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_AIC +{ + AT91_REG AIC_SMR[ 32 ]; /* Source Mode Register */ + AT91_REG AIC_SVR[ 32 ]; /* Source Vector Register */ + AT91_REG AIC_IVR; /* IRQ Vector Register */ + AT91_REG AIC_FVR; /* FIQ Vector Register */ + AT91_REG AIC_ISR; /* Interrupt Status Register */ + AT91_REG AIC_IPR; /* Interrupt Pending Register */ + AT91_REG AIC_IMR; /* Interrupt Mask Register */ + AT91_REG AIC_CISR; /* Core Interrupt Status Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG AIC_IECR; /* Interrupt Enable Command Register */ + AT91_REG AIC_IDCR; /* Interrupt Disable Command Register */ + AT91_REG AIC_ICCR; /* Interrupt Clear Command Register */ + AT91_REG AIC_ISCR; /* Interrupt Set Command Register */ + AT91_REG AIC_EOICR; /* End of Interrupt Command Register */ + AT91_REG AIC_SPU; /* Spurious Vector Register */ + AT91_REG AIC_DCR; /* Debug Control Register (Protect) */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG AIC_FFER; /* Fast Forcing Enable Register */ + AT91_REG AIC_FFDR; /* Fast Forcing Disable Register */ + AT91_REG AIC_FFSR; /* Fast Forcing Status Register */ +} AT91S_AIC, * AT91PS_AIC; + +/* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */ +#define AT91C_AIC_PRIOR ( ( unsigned int ) 0x7 << 0 ) /* (AIC) Priority Level */ +#define AT91C_AIC_PRIOR_LOWEST ( ( unsigned int ) 0x0 ) /* (AIC) Lowest priority level */ +#define AT91C_AIC_PRIOR_HIGHEST ( ( unsigned int ) 0x7 ) /* (AIC) Highest priority level */ +#define AT91C_AIC_SRCTYPE ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Interrupt Source Type */ +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ( ( unsigned int ) 0x0 << 5 ) /* (AIC) Internal Sources Code Label High-level Sensitive */ +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ( ( unsigned int ) 0x0 << 5 ) /* (AIC) External Sources Code Label Low-level Sensitive */ +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ( ( unsigned int ) 0x1 << 5 ) /* (AIC) Internal Sources Code Label Positive Edge triggered */ +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ( ( unsigned int ) 0x1 << 5 ) /* (AIC) External Sources Code Label Negative Edge triggered */ +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ( ( unsigned int ) 0x2 << 5 ) /* (AIC) Internal Or External Sources Code Label High-level Sensitive */ +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Internal Or External Sources Code Label Positive Edge triggered */ +/* -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- */ +#define AT91C_AIC_NFIQ ( ( unsigned int ) 0x1 << 0 ) /* (AIC) NFIQ Status */ +#define AT91C_AIC_NIRQ ( ( unsigned int ) 0x1 << 1 ) /* (AIC) NIRQ Status */ +/* -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- */ +#define AT91C_AIC_DCR_PROT ( ( unsigned int ) 0x1 << 0 ) /* (AIC) Protection Mode */ +#define AT91C_AIC_DCR_GMSK ( ( unsigned int ) 0x1 << 1 ) /* (AIC) General Mask */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Peripheral DMA Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_PDC +{ + AT91_REG PDC_RPR; /* Receive Pointer Register */ + AT91_REG PDC_RCR; /* Receive Counter Register */ + AT91_REG PDC_TPR; /* Transmit Pointer Register */ + AT91_REG PDC_TCR; /* Transmit Counter Register */ + AT91_REG PDC_RNPR; /* Receive Next Pointer Register */ + AT91_REG PDC_RNCR; /* Receive Next Counter Register */ + AT91_REG PDC_TNPR; /* Transmit Next Pointer Register */ + AT91_REG PDC_TNCR; /* Transmit Next Counter Register */ + AT91_REG PDC_PTCR; /* PDC Transfer Control Register */ + AT91_REG PDC_PTSR; /* PDC Transfer Status Register */ +} AT91S_PDC, * AT91PS_PDC; + +/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */ +#define AT91C_PDC_RXTEN ( ( unsigned int ) 0x1 << 0 ) /* (PDC) Receiver Transfer Enable */ +#define AT91C_PDC_RXTDIS ( ( unsigned int ) 0x1 << 1 ) /* (PDC) Receiver Transfer Disable */ +#define AT91C_PDC_TXTEN ( ( unsigned int ) 0x1 << 8 ) /* (PDC) Transmitter Transfer Enable */ +#define AT91C_PDC_TXTDIS ( ( unsigned int ) 0x1 << 9 ) /* (PDC) Transmitter Transfer Disable */ +/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Debug Unit */ +/* ***************************************************************************** */ +typedef struct _AT91S_DBGU +{ + AT91_REG DBGU_CR; /* Control Register */ + AT91_REG DBGU_MR; /* Mode Register */ + AT91_REG DBGU_IER; /* Interrupt Enable Register */ + AT91_REG DBGU_IDR; /* Interrupt Disable Register */ + AT91_REG DBGU_IMR; /* Interrupt Mask Register */ + AT91_REG DBGU_CSR; /* Channel Status Register */ + AT91_REG DBGU_RHR; /* Receiver Holding Register */ + AT91_REG DBGU_THR; /* Transmitter Holding Register */ + AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */ + AT91_REG Reserved0[ 7 ]; /* */ + AT91_REG DBGU_CIDR; /* Chip ID Register */ + AT91_REG DBGU_EXID; /* Chip ID Extension Register */ + AT91_REG DBGU_FNTR; /* Force NTRST Register */ + AT91_REG Reserved1[ 45 ]; /* */ + AT91_REG DBGU_RPR; /* Receive Pointer Register */ + AT91_REG DBGU_RCR; /* Receive Counter Register */ + AT91_REG DBGU_TPR; /* Transmit Pointer Register */ + AT91_REG DBGU_TCR; /* Transmit Counter Register */ + AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */ + AT91_REG DBGU_RNCR; /* Receive Next Counter Register */ + AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */ + AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */ + AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */ + AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */ +} AT91S_DBGU, * AT91PS_DBGU; + +/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */ +#define AT91C_US_RSTRX ( ( unsigned int ) 0x1 << 2 ) /* (DBGU) Reset Receiver */ +#define AT91C_US_RSTTX ( ( unsigned int ) 0x1 << 3 ) /* (DBGU) Reset Transmitter */ +#define AT91C_US_RXEN ( ( unsigned int ) 0x1 << 4 ) /* (DBGU) Receiver Enable */ +#define AT91C_US_RXDIS ( ( unsigned int ) 0x1 << 5 ) /* (DBGU) Receiver Disable */ +#define AT91C_US_TXEN ( ( unsigned int ) 0x1 << 6 ) /* (DBGU) Transmitter Enable */ +#define AT91C_US_TXDIS ( ( unsigned int ) 0x1 << 7 ) /* (DBGU) Transmitter Disable */ +#define AT91C_US_RSTSTA ( ( unsigned int ) 0x1 << 8 ) /* (DBGU) Reset Status Bits */ +/* -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- */ +#define AT91C_US_PAR ( ( unsigned int ) 0x7 << 9 ) /* (DBGU) Parity type */ +#define AT91C_US_PAR_EVEN ( ( unsigned int ) 0x0 << 9 ) /* (DBGU) Even Parity */ +#define AT91C_US_PAR_ODD ( ( unsigned int ) 0x1 << 9 ) /* (DBGU) Odd Parity */ +#define AT91C_US_PAR_SPACE ( ( unsigned int ) 0x2 << 9 ) /* (DBGU) Parity forced to 0 (Space) */ +#define AT91C_US_PAR_MARK ( ( unsigned int ) 0x3 << 9 ) /* (DBGU) Parity forced to 1 (Mark) */ +#define AT91C_US_PAR_NONE ( ( unsigned int ) 0x4 << 9 ) /* (DBGU) No Parity */ +#define AT91C_US_PAR_MULTI_DROP ( ( unsigned int ) 0x6 << 9 ) /* (DBGU) Multi-drop mode */ +#define AT91C_US_CHMODE ( ( unsigned int ) 0x3 << 14 ) /* (DBGU) Channel Mode */ +#define AT91C_US_CHMODE_NORMAL ( ( unsigned int ) 0x0 << 14 ) /* (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. */ +#define AT91C_US_CHMODE_AUTO ( ( unsigned int ) 0x1 << 14 ) /* (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. */ +#define AT91C_US_CHMODE_LOCAL ( ( unsigned int ) 0x2 << 14 ) /* (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. */ +#define AT91C_US_CHMODE_REMOTE ( ( unsigned int ) 0x3 << 14 ) /* (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. */ +/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ +#define AT91C_US_RXRDY ( ( unsigned int ) 0x1 << 0 ) /* (DBGU) RXRDY Interrupt */ +#define AT91C_US_TXRDY ( ( unsigned int ) 0x1 << 1 ) /* (DBGU) TXRDY Interrupt */ +#define AT91C_US_ENDRX ( ( unsigned int ) 0x1 << 3 ) /* (DBGU) End of Receive Transfer Interrupt */ +#define AT91C_US_ENDTX ( ( unsigned int ) 0x1 << 4 ) /* (DBGU) End of Transmit Interrupt */ +#define AT91C_US_OVRE ( ( unsigned int ) 0x1 << 5 ) /* (DBGU) Overrun Interrupt */ +#define AT91C_US_FRAME ( ( unsigned int ) 0x1 << 6 ) /* (DBGU) Framing Error Interrupt */ +#define AT91C_US_PARE ( ( unsigned int ) 0x1 << 7 ) /* (DBGU) Parity Error Interrupt */ +#define AT91C_US_TXEMPTY ( ( unsigned int ) 0x1 << 9 ) /* (DBGU) TXEMPTY Interrupt */ +#define AT91C_US_TXBUFE ( ( unsigned int ) 0x1 << 11 ) /* (DBGU) TXBUFE Interrupt */ +#define AT91C_US_RXBUFF ( ( unsigned int ) 0x1 << 12 ) /* (DBGU) RXBUFF Interrupt */ +#define AT91C_US_COMM_TX ( ( unsigned int ) 0x1 << 30 ) /* (DBGU) COMM_TX Interrupt */ +#define AT91C_US_COMM_RX ( ( unsigned int ) 0x1 << 31 ) /* (DBGU) COMM_RX Interrupt */ +/* -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- */ +/* -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- */ +/* -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- */ +/* -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- */ +#define AT91C_US_FORCE_NTRST ( ( unsigned int ) 0x1 << 0 ) /* (DBGU) Force NTRST in JTAG */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Parallel Input Output Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_PIO +{ + AT91_REG PIO_PER; /* PIO Enable Register */ + AT91_REG PIO_PDR; /* PIO Disable Register */ + AT91_REG PIO_PSR; /* PIO Status Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG PIO_OER; /* Output Enable Register */ + AT91_REG PIO_ODR; /* Output Disable Registerr */ + AT91_REG PIO_OSR; /* Output Status Register */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG PIO_IFER; /* Input Filter Enable Register */ + AT91_REG PIO_IFDR; /* Input Filter Disable Register */ + AT91_REG PIO_IFSR; /* Input Filter Status Register */ + AT91_REG Reserved2[ 1 ]; /* */ + AT91_REG PIO_SODR; /* Set Output Data Register */ + AT91_REG PIO_CODR; /* Clear Output Data Register */ + AT91_REG PIO_ODSR; /* Output Data Status Register */ + AT91_REG PIO_PDSR; /* Pin Data Status Register */ + AT91_REG PIO_IER; /* Interrupt Enable Register */ + AT91_REG PIO_IDR; /* Interrupt Disable Register */ + AT91_REG PIO_IMR; /* Interrupt Mask Register */ + AT91_REG PIO_ISR; /* Interrupt Status Register */ + AT91_REG PIO_MDER; /* Multi-driver Enable Register */ + AT91_REG PIO_MDDR; /* Multi-driver Disable Register */ + AT91_REG PIO_MDSR; /* Multi-driver Status Register */ + AT91_REG Reserved3[ 1 ]; /* */ + AT91_REG PIO_PPUDR; /* Pull-up Disable Register */ + AT91_REG PIO_PPUER; /* Pull-up Enable Register */ + AT91_REG PIO_PPUSR; /* Pull-up Status Register */ + AT91_REG Reserved4[ 1 ]; /* */ + AT91_REG PIO_ASR; /* Select A Register */ + AT91_REG PIO_BSR; /* Select B Register */ + AT91_REG PIO_ABSR; /* AB Select Status Register */ + AT91_REG Reserved5[ 9 ]; /* */ + AT91_REG PIO_OWER; /* Output Write Enable Register */ + AT91_REG PIO_OWDR; /* Output Write Disable Register */ + AT91_REG PIO_OWSR; /* Output Write Status Register */ +} AT91S_PIO, * AT91PS_PIO; + + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Clock Generator Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_CKGR +{ + AT91_REG CKGR_MOR; /* Main Oscillator Register */ + AT91_REG CKGR_MCFR; /* Main Clock Frequency Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG CKGR_PLLR; /* PLL Register */ +} AT91S_CKGR, * AT91PS_CKGR; + +/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */ +#define AT91C_CKGR_MOSCEN ( ( unsigned int ) 0x1 << 0 ) /* (CKGR) Main Oscillator Enable */ +#define AT91C_CKGR_OSCBYPASS ( ( unsigned int ) 0x1 << 1 ) /* (CKGR) Main Oscillator Bypass */ +#define AT91C_CKGR_OSCOUNT ( ( unsigned int ) 0xFF << 8 ) /* (CKGR) Main Oscillator Start-up Time */ +/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */ +#define AT91C_CKGR_MAINF ( ( unsigned int ) 0xFFFF << 0 ) /* (CKGR) Main Clock Frequency */ +#define AT91C_CKGR_MAINRDY ( ( unsigned int ) 0x1 << 16 ) /* (CKGR) Main Clock Ready */ +/* -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- */ +#define AT91C_CKGR_DIV ( ( unsigned int ) 0xFF << 0 ) /* (CKGR) Divider Selected */ +#define AT91C_CKGR_DIV_0 ( ( unsigned int ) 0x0 ) /* (CKGR) Divider output is 0 */ +#define AT91C_CKGR_DIV_BYPASS ( ( unsigned int ) 0x1 ) /* (CKGR) Divider is bypassed */ +#define AT91C_CKGR_PLLCOUNT ( ( unsigned int ) 0x3F << 8 ) /* (CKGR) PLL Counter */ +#define AT91C_CKGR_OUT ( ( unsigned int ) 0x3 << 14 ) /* (CKGR) PLL Output Frequency Range */ +#define AT91C_CKGR_OUT_0 ( ( unsigned int ) 0x0 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_1 ( ( unsigned int ) 0x1 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_2 ( ( unsigned int ) 0x2 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_3 ( ( unsigned int ) 0x3 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_MUL ( ( unsigned int ) 0x7FF << 16 ) /* (CKGR) PLL Multiplier */ +#define AT91C_CKGR_USBDIV ( ( unsigned int ) 0x3 << 28 ) /* (CKGR) Divider for USB Clocks */ +#define AT91C_CKGR_USBDIV_0 ( ( unsigned int ) 0x0 << 28 ) /* (CKGR) Divider output is PLL clock output */ +#define AT91C_CKGR_USBDIV_1 ( ( unsigned int ) 0x1 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 2 */ +#define AT91C_CKGR_USBDIV_2 ( ( unsigned int ) 0x2 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 4 */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Power Management Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_PMC +{ + AT91_REG PMC_SCER; /* System Clock Enable Register */ + AT91_REG PMC_SCDR; /* System Clock Disable Register */ + AT91_REG PMC_SCSR; /* System Clock Status Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */ + AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */ + AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG PMC_MOR; /* Main Oscillator Register */ + AT91_REG PMC_MCFR; /* Main Clock Frequency Register */ + AT91_REG Reserved2[ 1 ]; /* */ + AT91_REG PMC_PLLR; /* PLL Register */ + AT91_REG PMC_MCKR; /* Master Clock Register */ + AT91_REG Reserved3[ 3 ]; /* */ + AT91_REG PMC_PCKR[ 4 ]; /* Programmable Clock Register */ + AT91_REG Reserved4[ 4 ]; /* */ + AT91_REG PMC_IER; /* Interrupt Enable Register */ + AT91_REG PMC_IDR; /* Interrupt Disable Register */ + AT91_REG PMC_SR; /* Status Register */ + AT91_REG PMC_IMR; /* Interrupt Mask Register */ +} AT91S_PMC, * AT91PS_PMC; + +/* -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- */ +#define AT91C_PMC_PCK ( ( unsigned int ) 0x1 << 0 ) /* (PMC) Processor Clock */ +#define AT91C_PMC_UDP ( ( unsigned int ) 0x1 << 7 ) /* (PMC) USB Device Port Clock */ +#define AT91C_PMC_PCK0 ( ( unsigned int ) 0x1 << 8 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK1 ( ( unsigned int ) 0x1 << 9 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK2 ( ( unsigned int ) 0x1 << 10 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK3 ( ( unsigned int ) 0x1 << 11 ) /* (PMC) Programmable Clock Output */ +/* -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- */ +/* -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- */ +/* -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- */ +/* -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- */ +/* -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- */ +/* -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */ +#define AT91C_PMC_CSS ( ( unsigned int ) 0x3 << 0 ) /* (PMC) Programmable Clock Selection */ +#define AT91C_PMC_CSS_SLOW_CLK ( ( unsigned int ) 0x0 ) /* (PMC) Slow Clock is selected */ +#define AT91C_PMC_CSS_MAIN_CLK ( ( unsigned int ) 0x1 ) /* (PMC) Main Clock is selected */ +#define AT91C_PMC_CSS_PLL_CLK ( ( unsigned int ) 0x3 ) /* (PMC) Clock from PLL is selected */ +#define AT91C_PMC_PRES ( ( unsigned int ) 0x7 << 2 ) /* (PMC) Programmable Clock Prescaler */ +#define AT91C_PMC_PRES_CLK ( ( unsigned int ) 0x0 << 2 ) /* (PMC) Selected clock */ +#define AT91C_PMC_PRES_CLK_2 ( ( unsigned int ) 0x1 << 2 ) /* (PMC) Selected clock divided by 2 */ +#define AT91C_PMC_PRES_CLK_4 ( ( unsigned int ) 0x2 << 2 ) /* (PMC) Selected clock divided by 4 */ +#define AT91C_PMC_PRES_CLK_8 ( ( unsigned int ) 0x3 << 2 ) /* (PMC) Selected clock divided by 8 */ +#define AT91C_PMC_PRES_CLK_16 ( ( unsigned int ) 0x4 << 2 ) /* (PMC) Selected clock divided by 16 */ +#define AT91C_PMC_PRES_CLK_32 ( ( unsigned int ) 0x5 << 2 ) /* (PMC) Selected clock divided by 32 */ +#define AT91C_PMC_PRES_CLK_64 ( ( unsigned int ) 0x6 << 2 ) /* (PMC) Selected clock divided by 64 */ +/* -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- */ +/* -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- */ +#define AT91C_PMC_MOSCS ( ( unsigned int ) 0x1 << 0 ) /* (PMC) MOSC Status/Enable/Disable/Mask */ +#define AT91C_PMC_LOCK ( ( unsigned int ) 0x1 << 2 ) /* (PMC) PLL Status/Enable/Disable/Mask */ +#define AT91C_PMC_MCKRDY ( ( unsigned int ) 0x1 << 3 ) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK0RDY ( ( unsigned int ) 0x1 << 8 ) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK1RDY ( ( unsigned int ) 0x1 << 9 ) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK2RDY ( ( unsigned int ) 0x1 << 10 ) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK3RDY ( ( unsigned int ) 0x1 << 11 ) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */ +/* -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */ +/* -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- */ +/* -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Reset Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_RSTC +{ + AT91_REG RSTC_RCR; /* Reset Control Register */ + AT91_REG RSTC_RSR; /* Reset Status Register */ + AT91_REG RSTC_RMR; /* Reset Mode Register */ +} AT91S_RSTC, * AT91PS_RSTC; + +/* -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- */ +#define AT91C_RSTC_PROCRST ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) Processor Reset */ +#define AT91C_RSTC_PERRST ( ( unsigned int ) 0x1 << 2 ) /* (RSTC) Peripheral Reset */ +#define AT91C_RSTC_EXTRST ( ( unsigned int ) 0x1 << 3 ) /* (RSTC) External Reset */ +#define AT91C_RSTC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (RSTC) Password */ +/* -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- */ +#define AT91C_RSTC_URSTS ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) User Reset Status */ +#define AT91C_RSTC_BODSTS ( ( unsigned int ) 0x1 << 1 ) /* (RSTC) Brownout Detection Status */ +#define AT91C_RSTC_RSTTYP ( ( unsigned int ) 0x7 << 8 ) /* (RSTC) Reset Type */ +#define AT91C_RSTC_RSTTYP_POWERUP ( ( unsigned int ) 0x0 << 8 ) /* (RSTC) Power-up Reset. VDDCORE rising. */ +#define AT91C_RSTC_RSTTYP_WAKEUP ( ( unsigned int ) 0x1 << 8 ) /* (RSTC) WakeUp Reset. VDDCORE rising. */ +#define AT91C_RSTC_RSTTYP_WATCHDOG ( ( unsigned int ) 0x2 << 8 ) /* (RSTC) Watchdog Reset. Watchdog overflow occurred. */ +#define AT91C_RSTC_RSTTYP_SOFTWARE ( ( unsigned int ) 0x3 << 8 ) /* (RSTC) Software Reset. Processor reset required by the software. */ +#define AT91C_RSTC_RSTTYP_USER ( ( unsigned int ) 0x4 << 8 ) /* (RSTC) User Reset. NRST pin detected low. */ +#define AT91C_RSTC_RSTTYP_BROWNOUT ( ( unsigned int ) 0x5 << 8 ) /* (RSTC) Brownout Reset occurred. */ +#define AT91C_RSTC_NRSTL ( ( unsigned int ) 0x1 << 16 ) /* (RSTC) NRST pin level */ +#define AT91C_RSTC_SRCMP ( ( unsigned int ) 0x1 << 17 ) /* (RSTC) Software Reset Command in Progress. */ +/* -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- */ +#define AT91C_RSTC_URSTEN ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) User Reset Enable */ +#define AT91C_RSTC_URSTIEN ( ( unsigned int ) 0x1 << 4 ) /* (RSTC) User Reset Interrupt Enable */ +#define AT91C_RSTC_ERSTL ( ( unsigned int ) 0xF << 8 ) /* (RSTC) User Reset Enable */ +#define AT91C_RSTC_BODIEN ( ( unsigned int ) 0x1 << 16 ) /* (RSTC) Brownout Detection Interrupt Enable */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_RTTC +{ + AT91_REG RTTC_RTMR; /* Real-time Mode Register */ + AT91_REG RTTC_RTAR; /* Real-time Alarm Register */ + AT91_REG RTTC_RTVR; /* Real-time Value Register */ + AT91_REG RTTC_RTSR; /* Real-time Status Register */ +} AT91S_RTTC, * AT91PS_RTTC; + +/* -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- */ +#define AT91C_RTTC_RTPRES ( ( unsigned int ) 0xFFFF << 0 ) /* (RTTC) Real-time Timer Prescaler Value */ +#define AT91C_RTTC_ALMIEN ( ( unsigned int ) 0x1 << 16 ) /* (RTTC) Alarm Interrupt Enable */ +#define AT91C_RTTC_RTTINCIEN ( ( unsigned int ) 0x1 << 17 ) /* (RTTC) Real Time Timer Increment Interrupt Enable */ +#define AT91C_RTTC_RTTRST ( ( unsigned int ) 0x1 << 18 ) /* (RTTC) Real Time Timer Restart */ +/* -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- */ +#define AT91C_RTTC_ALMV ( ( unsigned int ) 0x0 << 0 ) /* (RTTC) Alarm Value */ +/* -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- */ +#define AT91C_RTTC_CRTV ( ( unsigned int ) 0x0 << 0 ) /* (RTTC) Current Real-time Value */ +/* -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- */ +#define AT91C_RTTC_ALMS ( ( unsigned int ) 0x1 << 0 ) /* (RTTC) Real-time Alarm Status */ +#define AT91C_RTTC_RTTINC ( ( unsigned int ) 0x1 << 1 ) /* (RTTC) Real-time Timer Increment */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_PITC +{ + AT91_REG PITC_PIMR; /* Period Interval Mode Register */ + AT91_REG PITC_PISR; /* Period Interval Status Register */ + AT91_REG PITC_PIVR; /* Period Interval Value Register */ + AT91_REG PITC_PIIR; /* Period Interval Image Register */ +} AT91S_PITC, * AT91PS_PITC; + +/* -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- */ +#define AT91C_PITC_PIV ( ( unsigned int ) 0xFFFFF << 0 ) /* (PITC) Periodic Interval Value */ +#define AT91C_PITC_PITEN ( ( unsigned int ) 0x1 << 24 ) /* (PITC) Periodic Interval Timer Enabled */ +#define AT91C_PITC_PITIEN ( ( unsigned int ) 0x1 << 25 ) /* (PITC) Periodic Interval Timer Interrupt Enable */ +/* -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- */ +#define AT91C_PITC_PITS ( ( unsigned int ) 0x1 << 0 ) /* (PITC) Periodic Interval Timer Status */ +/* -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- */ +#define AT91C_PITC_CPIV ( ( unsigned int ) 0xFFFFF << 0 ) /* (PITC) Current Periodic Interval Value */ +#define AT91C_PITC_PICNT ( ( unsigned int ) 0xFFF << 20 ) /* (PITC) Periodic Interval Counter */ +/* -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_WDTC +{ + AT91_REG WDTC_WDCR; /* Watchdog Control Register */ + AT91_REG WDTC_WDMR; /* Watchdog Mode Register */ + AT91_REG WDTC_WDSR; /* Watchdog Status Register */ +} AT91S_WDTC, * AT91PS_WDTC; + +/* -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- */ +#define AT91C_WDTC_WDRSTT ( ( unsigned int ) 0x1 << 0 ) /* (WDTC) Watchdog Restart */ +#define AT91C_WDTC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (WDTC) Watchdog KEY Password */ +/* -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */ +#define AT91C_WDTC_WDV ( ( unsigned int ) 0xFFF << 0 ) /* (WDTC) Watchdog Timer Restart */ +#define AT91C_WDTC_WDFIEN ( ( unsigned int ) 0x1 << 12 ) /* (WDTC) Watchdog Fault Interrupt Enable */ +#define AT91C_WDTC_WDRSTEN ( ( unsigned int ) 0x1 << 13 ) /* (WDTC) Watchdog Reset Enable */ +#define AT91C_WDTC_WDRPROC ( ( unsigned int ) 0x1 << 14 ) /* (WDTC) Watchdog Timer Restart */ +#define AT91C_WDTC_WDDIS ( ( unsigned int ) 0x1 << 15 ) /* (WDTC) Watchdog Disable */ +#define AT91C_WDTC_WDD ( ( unsigned int ) 0xFFF << 16 ) /* (WDTC) Watchdog Delta Value */ +#define AT91C_WDTC_WDDBGHLT ( ( unsigned int ) 0x1 << 28 ) /* (WDTC) Watchdog Debug Halt */ +#define AT91C_WDTC_WDIDLEHLT ( ( unsigned int ) 0x1 << 29 ) /* (WDTC) Watchdog Idle Halt */ +/* -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- */ +#define AT91C_WDTC_WDUNF ( ( unsigned int ) 0x1 << 0 ) /* (WDTC) Watchdog Underflow */ +#define AT91C_WDTC_WDERR ( ( unsigned int ) 0x1 << 1 ) /* (WDTC) Watchdog Error */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_VREG +{ + AT91_REG VREG_MR; /* Voltage Regulator Mode Register */ +} AT91S_VREG, * AT91PS_VREG; + +/* -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- */ +#define AT91C_VREG_PSTDBY ( ( unsigned int ) 0x1 << 0 ) /* (VREG) Voltage Regulator Power Standby Mode */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Memory Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_MC +{ + AT91_REG MC_RCR; /* MC Remap Control Register */ + AT91_REG MC_ASR; /* MC Abort Status Register */ + AT91_REG MC_AASR; /* MC Abort Address Status Register */ + AT91_REG Reserved0[ 21 ]; /* */ + AT91_REG MC_FMR; /* MC Flash Mode Register */ + AT91_REG MC_FCR; /* MC Flash Command Register */ + AT91_REG MC_FSR; /* MC Flash Status Register */ +} AT91S_MC, * AT91PS_MC; + +/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */ +#define AT91C_MC_RCB ( ( unsigned int ) 0x1 << 0 ) /* (MC) Remap Command Bit */ +/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */ +#define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Address Abort Status */ +#define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Address Abort Status */ +#define AT91C_MC_ABTSZ ( ( unsigned int ) 0x3 << 8 ) /* (MC) Abort Size Status */ +#define AT91C_MC_ABTSZ_BYTE ( ( unsigned int ) 0x0 << 8 ) /* (MC) Byte */ +#define AT91C_MC_ABTSZ_HWORD ( ( unsigned int ) 0x1 << 8 ) /* (MC) Half-word */ +#define AT91C_MC_ABTSZ_WORD ( ( unsigned int ) 0x2 << 8 ) /* (MC) Word */ +#define AT91C_MC_ABTTYP ( ( unsigned int ) 0x3 << 10 ) /* (MC) Abort Type Status */ +#define AT91C_MC_ABTTYP_DATAR ( ( unsigned int ) 0x0 << 10 ) /* (MC) Data Read */ +#define AT91C_MC_ABTTYP_DATAW ( ( unsigned int ) 0x1 << 10 ) /* (MC) Data Write */ +#define AT91C_MC_ABTTYP_FETCH ( ( unsigned int ) 0x2 << 10 ) /* (MC) Code Fetch */ +#define AT91C_MC_MST0 ( ( unsigned int ) 0x1 << 16 ) /* (MC) Master 0 Abort Source */ +#define AT91C_MC_MST1 ( ( unsigned int ) 0x1 << 17 ) /* (MC) Master 1 Abort Source */ +#define AT91C_MC_SVMST0 ( ( unsigned int ) 0x1 << 24 ) /* (MC) Saved Master 0 Abort Source */ +#define AT91C_MC_SVMST1 ( ( unsigned int ) 0x1 << 25 ) /* (MC) Saved Master 1 Abort Source */ +/* -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- */ +#define AT91C_MC_FRDY ( ( unsigned int ) 0x1 << 0 ) /* (MC) Flash Ready */ +#define AT91C_MC_LOCKE ( ( unsigned int ) 0x1 << 2 ) /* (MC) Lock Error */ +#define AT91C_MC_PROGE ( ( unsigned int ) 0x1 << 3 ) /* (MC) Programming Error */ +#define AT91C_MC_NEBP ( ( unsigned int ) 0x1 << 7 ) /* (MC) No Erase Before Programming */ +#define AT91C_MC_FWS ( ( unsigned int ) 0x3 << 8 ) /* (MC) Flash Wait State */ +#define AT91C_MC_FWS_0FWS ( ( unsigned int ) 0x0 << 8 ) /* (MC) 1 cycle for Read, 2 for Write operations */ +#define AT91C_MC_FWS_1FWS ( ( unsigned int ) 0x1 << 8 ) /* (MC) 2 cycles for Read, 3 for Write operations */ +#define AT91C_MC_FWS_2FWS ( ( unsigned int ) 0x2 << 8 ) /* (MC) 3 cycles for Read, 4 for Write operations */ +#define AT91C_MC_FWS_3FWS ( ( unsigned int ) 0x3 << 8 ) /* (MC) 4 cycles for Read, 4 for Write operations */ +#define AT91C_MC_FMCN ( ( unsigned int ) 0xFF << 16 ) /* (MC) Flash Microsecond Cycle Number */ +/* -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- */ +#define AT91C_MC_FCMD ( ( unsigned int ) 0xF << 0 ) /* (MC) Flash Command */ +#define AT91C_MC_FCMD_START_PROG ( ( unsigned int ) 0x1 ) /* (MC) Starts the programming of th epage specified by PAGEN. */ +#define AT91C_MC_FCMD_LOCK ( ( unsigned int ) 0x2 ) /* (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */ +#define AT91C_MC_FCMD_PROG_AND_LOCK ( ( unsigned int ) 0x3 ) /* (MC) The lock sequence automatically happens after the programming sequence is completed. */ +#define AT91C_MC_FCMD_UNLOCK ( ( unsigned int ) 0x4 ) /* (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */ +#define AT91C_MC_FCMD_ERASE_ALL ( ( unsigned int ) 0x8 ) /* (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. */ +#define AT91C_MC_FCMD_SET_GP_NVM ( ( unsigned int ) 0xB ) /* (MC) Set General Purpose NVM bits. */ +#define AT91C_MC_FCMD_CLR_GP_NVM ( ( unsigned int ) 0xD ) /* (MC) Clear General Purpose NVM bits. */ +#define AT91C_MC_FCMD_SET_SECURITY ( ( unsigned int ) 0xF ) /* (MC) Set Security Bit. */ +#define AT91C_MC_PAGEN ( ( unsigned int ) 0x3FF << 8 ) /* (MC) Page Number */ +#define AT91C_MC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (MC) Writing Protect Key */ +/* -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- */ +#define AT91C_MC_SECURITY ( ( unsigned int ) 0x1 << 4 ) /* (MC) Security Bit Status */ +#define AT91C_MC_GPNVM0 ( ( unsigned int ) 0x1 << 8 ) /* (MC) Sector 0 Lock Status */ +#define AT91C_MC_GPNVM1 ( ( unsigned int ) 0x1 << 9 ) /* (MC) Sector 1 Lock Status */ +#define AT91C_MC_GPNVM2 ( ( unsigned int ) 0x1 << 10 ) /* (MC) Sector 2 Lock Status */ +#define AT91C_MC_GPNVM3 ( ( unsigned int ) 0x1 << 11 ) /* (MC) Sector 3 Lock Status */ +#define AT91C_MC_GPNVM4 ( ( unsigned int ) 0x1 << 12 ) /* (MC) Sector 4 Lock Status */ +#define AT91C_MC_GPNVM5 ( ( unsigned int ) 0x1 << 13 ) /* (MC) Sector 5 Lock Status */ +#define AT91C_MC_GPNVM6 ( ( unsigned int ) 0x1 << 14 ) /* (MC) Sector 6 Lock Status */ +#define AT91C_MC_GPNVM7 ( ( unsigned int ) 0x1 << 15 ) /* (MC) Sector 7 Lock Status */ +#define AT91C_MC_LOCKS0 ( ( unsigned int ) 0x1 << 16 ) /* (MC) Sector 0 Lock Status */ +#define AT91C_MC_LOCKS1 ( ( unsigned int ) 0x1 << 17 ) /* (MC) Sector 1 Lock Status */ +#define AT91C_MC_LOCKS2 ( ( unsigned int ) 0x1 << 18 ) /* (MC) Sector 2 Lock Status */ +#define AT91C_MC_LOCKS3 ( ( unsigned int ) 0x1 << 19 ) /* (MC) Sector 3 Lock Status */ +#define AT91C_MC_LOCKS4 ( ( unsigned int ) 0x1 << 20 ) /* (MC) Sector 4 Lock Status */ +#define AT91C_MC_LOCKS5 ( ( unsigned int ) 0x1 << 21 ) /* (MC) Sector 5 Lock Status */ +#define AT91C_MC_LOCKS6 ( ( unsigned int ) 0x1 << 22 ) /* (MC) Sector 6 Lock Status */ +#define AT91C_MC_LOCKS7 ( ( unsigned int ) 0x1 << 23 ) /* (MC) Sector 7 Lock Status */ +#define AT91C_MC_LOCKS8 ( ( unsigned int ) 0x1 << 24 ) /* (MC) Sector 8 Lock Status */ +#define AT91C_MC_LOCKS9 ( ( unsigned int ) 0x1 << 25 ) /* (MC) Sector 9 Lock Status */ +#define AT91C_MC_LOCKS10 ( ( unsigned int ) 0x1 << 26 ) /* (MC) Sector 10 Lock Status */ +#define AT91C_MC_LOCKS11 ( ( unsigned int ) 0x1 << 27 ) /* (MC) Sector 11 Lock Status */ +#define AT91C_MC_LOCKS12 ( ( unsigned int ) 0x1 << 28 ) /* (MC) Sector 12 Lock Status */ +#define AT91C_MC_LOCKS13 ( ( unsigned int ) 0x1 << 29 ) /* (MC) Sector 13 Lock Status */ +#define AT91C_MC_LOCKS14 ( ( unsigned int ) 0x1 << 30 ) /* (MC) Sector 14 Lock Status */ +#define AT91C_MC_LOCKS15 ( ( unsigned int ) 0x1 << 31 ) /* (MC) Sector 15 Lock Status */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_SPI +{ + AT91_REG SPI_CR; /* Control Register */ + AT91_REG SPI_MR; /* Mode Register */ + AT91_REG SPI_RDR; /* Receive Data Register */ + AT91_REG SPI_TDR; /* Transmit Data Register */ + AT91_REG SPI_SR; /* Status Register */ + AT91_REG SPI_IER; /* Interrupt Enable Register */ + AT91_REG SPI_IDR; /* Interrupt Disable Register */ + AT91_REG SPI_IMR; /* Interrupt Mask Register */ + AT91_REG Reserved0[ 4 ]; /* */ + AT91_REG SPI_CSR[ 4 ]; /* Chip Select Register */ + AT91_REG Reserved1[ 48 ]; /* */ + AT91_REG SPI_RPR; /* Receive Pointer Register */ + AT91_REG SPI_RCR; /* Receive Counter Register */ + AT91_REG SPI_TPR; /* Transmit Pointer Register */ + AT91_REG SPI_TCR; /* Transmit Counter Register */ + AT91_REG SPI_RNPR; /* Receive Next Pointer Register */ + AT91_REG SPI_RNCR; /* Receive Next Counter Register */ + AT91_REG SPI_TNPR; /* Transmit Next Pointer Register */ + AT91_REG SPI_TNCR; /* Transmit Next Counter Register */ + AT91_REG SPI_PTCR; /* PDC Transfer Control Register */ + AT91_REG SPI_PTSR; /* PDC Transfer Status Register */ +} AT91S_SPI, * AT91PS_SPI; + +/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */ +#define AT91C_SPI_SPIEN ( ( unsigned int ) 0x1 << 0 ) /* (SPI) SPI Enable */ +#define AT91C_SPI_SPIDIS ( ( unsigned int ) 0x1 << 1 ) /* (SPI) SPI Disable */ +#define AT91C_SPI_SWRST ( ( unsigned int ) 0x1 << 7 ) /* (SPI) SPI Software reset */ +#define AT91C_SPI_LASTXFER ( ( unsigned int ) 0x1 << 24 ) /* (SPI) SPI Last Transfer */ +/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */ +#define AT91C_SPI_MSTR ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Master/Slave Mode */ +#define AT91C_SPI_PS ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Peripheral Select */ +#define AT91C_SPI_PS_FIXED ( ( unsigned int ) 0x0 << 1 ) /* (SPI) Fixed Peripheral Select */ +#define AT91C_SPI_PS_VARIABLE ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Variable Peripheral Select */ +#define AT91C_SPI_PCSDEC ( ( unsigned int ) 0x1 << 2 ) /* (SPI) Chip Select Decode */ +#define AT91C_SPI_FDIV ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Clock Selection */ +#define AT91C_SPI_MODFDIS ( ( unsigned int ) 0x1 << 4 ) /* (SPI) Mode Fault Detection */ +#define AT91C_SPI_LLB ( ( unsigned int ) 0x1 << 7 ) /* (SPI) Clock Selection */ +#define AT91C_SPI_PCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select */ +#define AT91C_SPI_DLYBCS ( ( unsigned int ) 0xFF << 24 ) /* (SPI) Delay Between Chip Selects */ +/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */ +#define AT91C_SPI_RD ( ( unsigned int ) 0xFFFF << 0 ) /* (SPI) Receive Data */ +#define AT91C_SPI_RPCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */ +/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */ +#define AT91C_SPI_TD ( ( unsigned int ) 0xFFFF << 0 ) /* (SPI) Transmit Data */ +#define AT91C_SPI_TPCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */ +/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ +#define AT91C_SPI_RDRF ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Receive Data Register Full */ +#define AT91C_SPI_TDRE ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Transmit Data Register Empty */ +#define AT91C_SPI_MODF ( ( unsigned int ) 0x1 << 2 ) /* (SPI) Mode Fault Error */ +#define AT91C_SPI_OVRES ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Overrun Error Status */ +#define AT91C_SPI_ENDRX ( ( unsigned int ) 0x1 << 4 ) /* (SPI) End of Receiver Transfer */ +#define AT91C_SPI_ENDTX ( ( unsigned int ) 0x1 << 5 ) /* (SPI) End of Receiver Transfer */ +#define AT91C_SPI_RXBUFF ( ( unsigned int ) 0x1 << 6 ) /* (SPI) RXBUFF Interrupt */ +#define AT91C_SPI_TXBUFE ( ( unsigned int ) 0x1 << 7 ) /* (SPI) TXBUFE Interrupt */ +#define AT91C_SPI_NSSR ( ( unsigned int ) 0x1 << 8 ) /* (SPI) NSSR Interrupt */ +#define AT91C_SPI_TXEMPTY ( ( unsigned int ) 0x1 << 9 ) /* (SPI) TXEMPTY Interrupt */ +#define AT91C_SPI_SPIENS ( ( unsigned int ) 0x1 << 16 ) /* (SPI) Enable Status */ +/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ +/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ +/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */ +/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */ +#define AT91C_SPI_CPOL ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Clock Polarity */ +#define AT91C_SPI_NCPHA ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Clock Phase */ +#define AT91C_SPI_CSAAT ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Chip Select Active After Transfer */ +#define AT91C_SPI_BITS ( ( unsigned int ) 0xF << 4 ) /* (SPI) Bits Per Transfer */ +#define AT91C_SPI_BITS_8 ( ( unsigned int ) 0x0 << 4 ) /* (SPI) 8 Bits Per transfer */ +#define AT91C_SPI_BITS_9 ( ( unsigned int ) 0x1 << 4 ) /* (SPI) 9 Bits Per transfer */ +#define AT91C_SPI_BITS_10 ( ( unsigned int ) 0x2 << 4 ) /* (SPI) 10 Bits Per transfer */ +#define AT91C_SPI_BITS_11 ( ( unsigned int ) 0x3 << 4 ) /* (SPI) 11 Bits Per transfer */ +#define AT91C_SPI_BITS_12 ( ( unsigned int ) 0x4 << 4 ) /* (SPI) 12 Bits Per transfer */ +#define AT91C_SPI_BITS_13 ( ( unsigned int ) 0x5 << 4 ) /* (SPI) 13 Bits Per transfer */ +#define AT91C_SPI_BITS_14 ( ( unsigned int ) 0x6 << 4 ) /* (SPI) 14 Bits Per transfer */ +#define AT91C_SPI_BITS_15 ( ( unsigned int ) 0x7 << 4 ) /* (SPI) 15 Bits Per transfer */ +#define AT91C_SPI_BITS_16 ( ( unsigned int ) 0x8 << 4 ) /* (SPI) 16 Bits Per transfer */ +#define AT91C_SPI_SCBR ( ( unsigned int ) 0xFF << 8 ) /* (SPI) Serial Clock Baud Rate */ +#define AT91C_SPI_DLYBS ( ( unsigned int ) 0xFF << 16 ) /* (SPI) Delay Before SPCK */ +#define AT91C_SPI_DLYBCT ( ( unsigned int ) 0xFF << 24 ) /* (SPI) Delay Between Consecutive Transfers */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Usart */ +/* ***************************************************************************** */ +typedef struct _AT91S_USART +{ + AT91_REG US_CR; /* Control Register */ + AT91_REG US_MR; /* Mode Register */ + AT91_REG US_IER; /* Interrupt Enable Register */ + AT91_REG US_IDR; /* Interrupt Disable Register */ + AT91_REG US_IMR; /* Interrupt Mask Register */ + AT91_REG US_CSR; /* Channel Status Register */ + AT91_REG US_RHR; /* Receiver Holding Register */ + AT91_REG US_THR; /* Transmitter Holding Register */ + AT91_REG US_BRGR; /* Baud Rate Generator Register */ + AT91_REG US_RTOR; /* Receiver Time-out Register */ + AT91_REG US_TTGR; /* Transmitter Time-guard Register */ + AT91_REG Reserved0[ 5 ]; /* */ + AT91_REG US_FIDI; /* FI_DI_Ratio Register */ + AT91_REG US_NER; /* Nb Errors Register */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG US_IF; /* IRDA_FILTER Register */ + AT91_REG Reserved2[ 44 ]; /* */ + AT91_REG US_RPR; /* Receive Pointer Register */ + AT91_REG US_RCR; /* Receive Counter Register */ + AT91_REG US_TPR; /* Transmit Pointer Register */ + AT91_REG US_TCR; /* Transmit Counter Register */ + AT91_REG US_RNPR; /* Receive Next Pointer Register */ + AT91_REG US_RNCR; /* Receive Next Counter Register */ + AT91_REG US_TNPR; /* Transmit Next Pointer Register */ + AT91_REG US_TNCR; /* Transmit Next Counter Register */ + AT91_REG US_PTCR; /* PDC Transfer Control Register */ + AT91_REG US_PTSR; /* PDC Transfer Status Register */ +} AT91S_USART, * AT91PS_USART; + +/* -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- */ +#define AT91C_US_STTBRK ( ( unsigned int ) 0x1 << 9 ) /* (USART) Start Break */ +#define AT91C_US_STPBRK ( ( unsigned int ) 0x1 << 10 ) /* (USART) Stop Break */ +#define AT91C_US_STTTO ( ( unsigned int ) 0x1 << 11 ) /* (USART) Start Time-out */ +#define AT91C_US_SENDA ( ( unsigned int ) 0x1 << 12 ) /* (USART) Send Address */ +#define AT91C_US_RSTIT ( ( unsigned int ) 0x1 << 13 ) /* (USART) Reset Iterations */ +#define AT91C_US_RSTNACK ( ( unsigned int ) 0x1 << 14 ) /* (USART) Reset Non Acknowledge */ +#define AT91C_US_RETTO ( ( unsigned int ) 0x1 << 15 ) /* (USART) Rearm Time-out */ +#define AT91C_US_DTREN ( ( unsigned int ) 0x1 << 16 ) /* (USART) Data Terminal ready Enable */ +#define AT91C_US_DTRDIS ( ( unsigned int ) 0x1 << 17 ) /* (USART) Data Terminal ready Disable */ +#define AT91C_US_RTSEN ( ( unsigned int ) 0x1 << 18 ) /* (USART) Request to Send enable */ +#define AT91C_US_RTSDIS ( ( unsigned int ) 0x1 << 19 ) /* (USART) Request to Send Disable */ +/* -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- */ +#define AT91C_US_USMODE ( ( unsigned int ) 0xF << 0 ) /* (USART) Usart mode */ +#define AT91C_US_USMODE_NORMAL ( ( unsigned int ) 0x0 ) /* (USART) Normal */ +#define AT91C_US_USMODE_RS485 ( ( unsigned int ) 0x1 ) /* (USART) RS485 */ +#define AT91C_US_USMODE_HWHSH ( ( unsigned int ) 0x2 ) /* (USART) Hardware Handshaking */ +#define AT91C_US_USMODE_MODEM ( ( unsigned int ) 0x3 ) /* (USART) Modem */ +#define AT91C_US_USMODE_ISO7816_0 ( ( unsigned int ) 0x4 ) /* (USART) ISO7816 protocol: T = 0 */ +#define AT91C_US_USMODE_ISO7816_1 ( ( unsigned int ) 0x6 ) /* (USART) ISO7816 protocol: T = 1 */ +#define AT91C_US_USMODE_IRDA ( ( unsigned int ) 0x8 ) /* (USART) IrDA */ +#define AT91C_US_USMODE_SWHSH ( ( unsigned int ) 0xC ) /* (USART) Software Handshaking */ +#define AT91C_US_CLKS ( ( unsigned int ) 0x3 << 4 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */ +#define AT91C_US_CLKS_CLOCK ( ( unsigned int ) 0x0 << 4 ) /* (USART) Clock */ +#define AT91C_US_CLKS_FDIV1 ( ( unsigned int ) 0x1 << 4 ) /* (USART) fdiv1 */ +#define AT91C_US_CLKS_SLOW ( ( unsigned int ) 0x2 << 4 ) /* (USART) slow_clock (ARM) */ +#define AT91C_US_CLKS_EXT ( ( unsigned int ) 0x3 << 4 ) /* (USART) External (SCK) */ +#define AT91C_US_CHRL ( ( unsigned int ) 0x3 << 6 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */ +#define AT91C_US_CHRL_5_BITS ( ( unsigned int ) 0x0 << 6 ) /* (USART) Character Length: 5 bits */ +#define AT91C_US_CHRL_6_BITS ( ( unsigned int ) 0x1 << 6 ) /* (USART) Character Length: 6 bits */ +#define AT91C_US_CHRL_7_BITS ( ( unsigned int ) 0x2 << 6 ) /* (USART) Character Length: 7 bits */ +#define AT91C_US_CHRL_8_BITS ( ( unsigned int ) 0x3 << 6 ) /* (USART) Character Length: 8 bits */ +#define AT91C_US_SYNC ( ( unsigned int ) 0x1 << 8 ) /* (USART) Synchronous Mode Select */ +#define AT91C_US_NBSTOP ( ( unsigned int ) 0x3 << 12 ) /* (USART) Number of Stop bits */ +#define AT91C_US_NBSTOP_1_BIT ( ( unsigned int ) 0x0 << 12 ) /* (USART) 1 stop bit */ +#define AT91C_US_NBSTOP_15_BIT ( ( unsigned int ) 0x1 << 12 ) /* (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */ +#define AT91C_US_NBSTOP_2_BIT ( ( unsigned int ) 0x2 << 12 ) /* (USART) 2 stop bits */ +#define AT91C_US_MSBF ( ( unsigned int ) 0x1 << 16 ) /* (USART) Bit Order */ +#define AT91C_US_MODE9 ( ( unsigned int ) 0x1 << 17 ) /* (USART) 9-bit Character length */ +#define AT91C_US_CKLO ( ( unsigned int ) 0x1 << 18 ) /* (USART) Clock Output Select */ +#define AT91C_US_OVER ( ( unsigned int ) 0x1 << 19 ) /* (USART) Over Sampling Mode */ +#define AT91C_US_INACK ( ( unsigned int ) 0x1 << 20 ) /* (USART) Inhibit Non Acknowledge */ +#define AT91C_US_DSNACK ( ( unsigned int ) 0x1 << 21 ) /* (USART) Disable Successive NACK */ +#define AT91C_US_MAX_ITER ( ( unsigned int ) 0x1 << 24 ) /* (USART) Number of Repetitions */ +#define AT91C_US_FILTER ( ( unsigned int ) 0x1 << 28 ) /* (USART) Receive Line Filter */ +/* -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ +#define AT91C_US_RXBRK ( ( unsigned int ) 0x1 << 2 ) /* (USART) Break Received/End of Break */ +#define AT91C_US_TIMEOUT ( ( unsigned int ) 0x1 << 8 ) /* (USART) Receiver Time-out */ +#define AT91C_US_ITERATION ( ( unsigned int ) 0x1 << 10 ) /* (USART) Max number of Repetitions Reached */ +#define AT91C_US_NACK ( ( unsigned int ) 0x1 << 13 ) /* (USART) Non Acknowledge */ +#define AT91C_US_RIIC ( ( unsigned int ) 0x1 << 16 ) /* (USART) Ring INdicator Input Change Flag */ +#define AT91C_US_DSRIC ( ( unsigned int ) 0x1 << 17 ) /* (USART) Data Set Ready Input Change Flag */ +#define AT91C_US_DCDIC ( ( unsigned int ) 0x1 << 18 ) /* (USART) Data Carrier Flag */ +#define AT91C_US_CTSIC ( ( unsigned int ) 0x1 << 19 ) /* (USART) Clear To Send Input Change Flag */ +/* -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- */ +/* -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- */ +/* -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- */ +#define AT91C_US_RI ( ( unsigned int ) 0x1 << 20 ) /* (USART) Image of RI Input */ +#define AT91C_US_DSR ( ( unsigned int ) 0x1 << 21 ) /* (USART) Image of DSR Input */ +#define AT91C_US_DCD ( ( unsigned int ) 0x1 << 22 ) /* (USART) Image of DCD Input */ +#define AT91C_US_CTS ( ( unsigned int ) 0x1 << 23 ) /* (USART) Image of CTS Input */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_SSC +{ + AT91_REG SSC_CR; /* Control Register */ + AT91_REG SSC_CMR; /* Clock Mode Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG SSC_RCMR; /* Receive Clock ModeRegister */ + AT91_REG SSC_RFMR; /* Receive Frame Mode Register */ + AT91_REG SSC_TCMR; /* Transmit Clock Mode Register */ + AT91_REG SSC_TFMR; /* Transmit Frame Mode Register */ + AT91_REG SSC_RHR; /* Receive Holding Register */ + AT91_REG SSC_THR; /* Transmit Holding Register */ + AT91_REG Reserved1[ 2 ]; /* */ + AT91_REG SSC_RSHR; /* Receive Sync Holding Register */ + AT91_REG SSC_TSHR; /* Transmit Sync Holding Register */ + AT91_REG Reserved2[ 2 ]; /* */ + AT91_REG SSC_SR; /* Status Register */ + AT91_REG SSC_IER; /* Interrupt Enable Register */ + AT91_REG SSC_IDR; /* Interrupt Disable Register */ + AT91_REG SSC_IMR; /* Interrupt Mask Register */ + AT91_REG Reserved3[ 44 ]; /* */ + AT91_REG SSC_RPR; /* Receive Pointer Register */ + AT91_REG SSC_RCR; /* Receive Counter Register */ + AT91_REG SSC_TPR; /* Transmit Pointer Register */ + AT91_REG SSC_TCR; /* Transmit Counter Register */ + AT91_REG SSC_RNPR; /* Receive Next Pointer Register */ + AT91_REG SSC_RNCR; /* Receive Next Counter Register */ + AT91_REG SSC_TNPR; /* Transmit Next Pointer Register */ + AT91_REG SSC_TNCR; /* Transmit Next Counter Register */ + AT91_REG SSC_PTCR; /* PDC Transfer Control Register */ + AT91_REG SSC_PTSR; /* PDC Transfer Status Register */ +} AT91S_SSC, * AT91PS_SSC; + +/* -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- */ +#define AT91C_SSC_RXEN ( ( unsigned int ) 0x1 << 0 ) /* (SSC) Receive Enable */ +#define AT91C_SSC_RXDIS ( ( unsigned int ) 0x1 << 1 ) /* (SSC) Receive Disable */ +#define AT91C_SSC_TXEN ( ( unsigned int ) 0x1 << 8 ) /* (SSC) Transmit Enable */ +#define AT91C_SSC_TXDIS ( ( unsigned int ) 0x1 << 9 ) /* (SSC) Transmit Disable */ +#define AT91C_SSC_SWRST ( ( unsigned int ) 0x1 << 15 ) /* (SSC) Software Reset */ +/* -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- */ +#define AT91C_SSC_CKS ( ( unsigned int ) 0x3 << 0 ) /* (SSC) Receive/Transmit Clock Selection */ +#define AT91C_SSC_CKS_DIV ( ( unsigned int ) 0x0 ) /* (SSC) Divided Clock */ +#define AT91C_SSC_CKS_TK ( ( unsigned int ) 0x1 ) /* (SSC) TK Clock signal */ +#define AT91C_SSC_CKS_RK ( ( unsigned int ) 0x2 ) /* (SSC) RK pin */ +#define AT91C_SSC_CKO ( ( unsigned int ) 0x7 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode Selection */ +#define AT91C_SSC_CKO_NONE ( ( unsigned int ) 0x0 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only */ +#define AT91C_SSC_CKO_CONTINUOUS ( ( unsigned int ) 0x1 << 2 ) /* (SSC) Continuous Receive/Transmit Clock RK pin: Output */ +#define AT91C_SSC_CKO_DATA_TX ( ( unsigned int ) 0x2 << 2 ) /* (SSC) Receive/Transmit Clock only during data transfers RK pin: Output */ +#define AT91C_SSC_CKI ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Receive/Transmit Clock Inversion */ +#define AT91C_SSC_START ( ( unsigned int ) 0xF << 8 ) /* (SSC) Receive/Transmit Start Selection */ +#define AT91C_SSC_START_CONTINUOUS ( ( unsigned int ) 0x0 << 8 ) /* (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */ +#define AT91C_SSC_START_TX ( ( unsigned int ) 0x1 << 8 ) /* (SSC) Transmit/Receive start */ +#define AT91C_SSC_START_LOW_RF ( ( unsigned int ) 0x2 << 8 ) /* (SSC) Detection of a low level on RF input */ +#define AT91C_SSC_START_HIGH_RF ( ( unsigned int ) 0x3 << 8 ) /* (SSC) Detection of a high level on RF input */ +#define AT91C_SSC_START_FALL_RF ( ( unsigned int ) 0x4 << 8 ) /* (SSC) Detection of a falling edge on RF input */ +#define AT91C_SSC_START_RISE_RF ( ( unsigned int ) 0x5 << 8 ) /* (SSC) Detection of a rising edge on RF input */ +#define AT91C_SSC_START_LEVEL_RF ( ( unsigned int ) 0x6 << 8 ) /* (SSC) Detection of any level change on RF input */ +#define AT91C_SSC_START_EDGE_RF ( ( unsigned int ) 0x7 << 8 ) /* (SSC) Detection of any edge on RF input */ +#define AT91C_SSC_START_0 ( ( unsigned int ) 0x8 << 8 ) /* (SSC) Compare 0 */ +#define AT91C_SSC_STTDLY ( ( unsigned int ) 0xFF << 16 ) /* (SSC) Receive/Transmit Start Delay */ +#define AT91C_SSC_PERIOD ( ( unsigned int ) 0xFF << 24 ) /* (SSC) Receive/Transmit Period Divider Selection */ +/* -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- */ +#define AT91C_SSC_DATLEN ( ( unsigned int ) 0x1F << 0 ) /* (SSC) Data Length */ +#define AT91C_SSC_LOOP ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Loop Mode */ +#define AT91C_SSC_MSBF ( ( unsigned int ) 0x1 << 7 ) /* (SSC) Most Significant Bit First */ +#define AT91C_SSC_DATNB ( ( unsigned int ) 0xF << 8 ) /* (SSC) Data Number per Frame */ +#define AT91C_SSC_FSLEN ( ( unsigned int ) 0xF << 16 ) /* (SSC) Receive/Transmit Frame Sync length */ +#define AT91C_SSC_FSOS ( ( unsigned int ) 0x7 << 20 ) /* (SSC) Receive/Transmit Frame Sync Output Selection */ +#define AT91C_SSC_FSOS_NONE ( ( unsigned int ) 0x0 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only */ +#define AT91C_SSC_FSOS_NEGATIVE ( ( unsigned int ) 0x1 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse */ +#define AT91C_SSC_FSOS_POSITIVE ( ( unsigned int ) 0x2 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse */ +#define AT91C_SSC_FSOS_LOW ( ( unsigned int ) 0x3 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer */ +#define AT91C_SSC_FSOS_HIGH ( ( unsigned int ) 0x4 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer */ +#define AT91C_SSC_FSOS_TOGGLE ( ( unsigned int ) 0x5 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer */ +#define AT91C_SSC_FSEDGE ( ( unsigned int ) 0x1 << 24 ) /* (SSC) Frame Sync Edge Detection */ +/* -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- */ +/* -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- */ +#define AT91C_SSC_DATDEF ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Data Default Value */ +#define AT91C_SSC_FSDEN ( ( unsigned int ) 0x1 << 23 ) /* (SSC) Frame Sync Data Enable */ +/* -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- */ +#define AT91C_SSC_TXRDY ( ( unsigned int ) 0x1 << 0 ) /* (SSC) Transmit Ready */ +#define AT91C_SSC_TXEMPTY ( ( unsigned int ) 0x1 << 1 ) /* (SSC) Transmit Empty */ +#define AT91C_SSC_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (SSC) End Of Transmission */ +#define AT91C_SSC_TXBUFE ( ( unsigned int ) 0x1 << 3 ) /* (SSC) Transmit Buffer Empty */ +#define AT91C_SSC_RXRDY ( ( unsigned int ) 0x1 << 4 ) /* (SSC) Receive Ready */ +#define AT91C_SSC_OVRUN ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Receive Overrun */ +#define AT91C_SSC_ENDRX ( ( unsigned int ) 0x1 << 6 ) /* (SSC) End of Reception */ +#define AT91C_SSC_RXBUFF ( ( unsigned int ) 0x1 << 7 ) /* (SSC) Receive Buffer Full */ +#define AT91C_SSC_TXSYN ( ( unsigned int ) 0x1 << 10 ) /* (SSC) Transmit Sync */ +#define AT91C_SSC_RXSYN ( ( unsigned int ) 0x1 << 11 ) /* (SSC) Receive Sync */ +#define AT91C_SSC_TXENA ( ( unsigned int ) 0x1 << 16 ) /* (SSC) Transmit Enable */ +#define AT91C_SSC_RXENA ( ( unsigned int ) 0x1 << 17 ) /* (SSC) Receive Enable */ +/* -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- */ +/* -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- */ +/* -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Two-wire Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_TWI +{ + AT91_REG TWI_CR; /* Control Register */ + AT91_REG TWI_MMR; /* Master Mode Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG TWI_IADR; /* Internal Address Register */ + AT91_REG TWI_CWGR; /* Clock Waveform Generator Register */ + AT91_REG Reserved1[ 3 ]; /* */ + AT91_REG TWI_SR; /* Status Register */ + AT91_REG TWI_IER; /* Interrupt Enable Register */ + AT91_REG TWI_IDR; /* Interrupt Disable Register */ + AT91_REG TWI_IMR; /* Interrupt Mask Register */ + AT91_REG TWI_RHR; /* Receive Holding Register */ + AT91_REG TWI_THR; /* Transmit Holding Register */ +} AT91S_TWI, * AT91PS_TWI; + +/* -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */ +#define AT91C_TWI_START ( ( unsigned int ) 0x1 << 0 ) /* (TWI) Send a START Condition */ +#define AT91C_TWI_STOP ( ( unsigned int ) 0x1 << 1 ) /* (TWI) Send a STOP Condition */ +#define AT91C_TWI_MSEN ( ( unsigned int ) 0x1 << 2 ) /* (TWI) TWI Master Transfer Enabled */ +#define AT91C_TWI_MSDIS ( ( unsigned int ) 0x1 << 3 ) /* (TWI) TWI Master Transfer Disabled */ +#define AT91C_TWI_SWRST ( ( unsigned int ) 0x1 << 7 ) /* (TWI) Software Reset */ +/* -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */ +#define AT91C_TWI_IADRSZ ( ( unsigned int ) 0x3 << 8 ) /* (TWI) Internal Device Address Size */ +#define AT91C_TWI_IADRSZ_NO ( ( unsigned int ) 0x0 << 8 ) /* (TWI) No internal device address */ +#define AT91C_TWI_IADRSZ_1_BYTE ( ( unsigned int ) 0x1 << 8 ) /* (TWI) One-byte internal device address */ +#define AT91C_TWI_IADRSZ_2_BYTE ( ( unsigned int ) 0x2 << 8 ) /* (TWI) Two-byte internal device address */ +#define AT91C_TWI_IADRSZ_3_BYTE ( ( unsigned int ) 0x3 << 8 ) /* (TWI) Three-byte internal device address */ +#define AT91C_TWI_MREAD ( ( unsigned int ) 0x1 << 12 ) /* (TWI) Master Read Direction */ +#define AT91C_TWI_DADR ( ( unsigned int ) 0x7F << 16 ) /* (TWI) Device Address */ +/* -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */ +#define AT91C_TWI_CLDIV ( ( unsigned int ) 0xFF << 0 ) /* (TWI) Clock Low Divider */ +#define AT91C_TWI_CHDIV ( ( unsigned int ) 0xFF << 8 ) /* (TWI) Clock High Divider */ +#define AT91C_TWI_CKDIV ( ( unsigned int ) 0x7 << 16 ) /* (TWI) Clock Divider */ +/* -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */ +#define AT91C_TWI_TXCOMP ( ( unsigned int ) 0x1 << 0 ) /* (TWI) Transmission Completed */ +#define AT91C_TWI_RXRDY ( ( unsigned int ) 0x1 << 1 ) /* (TWI) Receive holding register ReaDY */ +#define AT91C_TWI_TXRDY ( ( unsigned int ) 0x1 << 2 ) /* (TWI) Transmit holding register ReaDY */ +#define AT91C_TWI_OVRE ( ( unsigned int ) 0x1 << 6 ) /* (TWI) Overrun Error */ +#define AT91C_TWI_UNRE ( ( unsigned int ) 0x1 << 7 ) /* (TWI) Underrun Error */ +#define AT91C_TWI_NACK ( ( unsigned int ) 0x1 << 8 ) /* (TWI) Not Acknowledged */ +/* -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */ +/* -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- */ +/* -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR PWMC Channel Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_PWMC_CH +{ + AT91_REG PWMC_CMR; /* Channel Mode Register */ + AT91_REG PWMC_CDTYR; /* Channel Duty Cycle Register */ + AT91_REG PWMC_CPRDR; /* Channel Period Register */ + AT91_REG PWMC_CCNTR; /* Channel Counter Register */ + AT91_REG PWMC_CUPDR; /* Channel Update Register */ + AT91_REG PWMC_Reserved[ 3 ]; /* Reserved */ +} AT91S_PWMC_CH, * AT91PS_PWMC_CH; + +/* -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- */ +#define AT91C_PWMC_CPRE ( ( unsigned int ) 0xF << 0 ) /* (PWMC_CH) Channel Pre-scaler : PWMC_CLKx */ +#define AT91C_PWMC_CPRE_MCK ( ( unsigned int ) 0x0 ) /* (PWMC_CH) */ +#define AT91C_PWMC_CPRE_MCKA ( ( unsigned int ) 0xB ) /* (PWMC_CH) */ +#define AT91C_PWMC_CPRE_MCKB ( ( unsigned int ) 0xC ) /* (PWMC_CH) */ +#define AT91C_PWMC_CALG ( ( unsigned int ) 0x1 << 8 ) /* (PWMC_CH) Channel Alignment */ +#define AT91C_PWMC_CPOL ( ( unsigned int ) 0x1 << 9 ) /* (PWMC_CH) Channel Polarity */ +#define AT91C_PWMC_CPD ( ( unsigned int ) 0x1 << 10 ) /* (PWMC_CH) Channel Update Period */ +/* -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- */ +#define AT91C_PWMC_CDTY ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Duty Cycle */ +/* -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- */ +#define AT91C_PWMC_CPRD ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Period */ +/* -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- */ +#define AT91C_PWMC_CCNT ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Counter */ +/* -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- */ +#define AT91C_PWMC_CUPD ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Update */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_PWMC +{ + AT91_REG PWMC_MR; /* PWMC Mode Register */ + AT91_REG PWMC_ENA; /* PWMC Enable Register */ + AT91_REG PWMC_DIS; /* PWMC Disable Register */ + AT91_REG PWMC_SR; /* PWMC Status Register */ + AT91_REG PWMC_IER; /* PWMC Interrupt Enable Register */ + AT91_REG PWMC_IDR; /* PWMC Interrupt Disable Register */ + AT91_REG PWMC_IMR; /* PWMC Interrupt Mask Register */ + AT91_REG PWMC_ISR; /* PWMC Interrupt Status Register */ + AT91_REG Reserved0[ 55 ]; /* */ + AT91_REG PWMC_VR; /* PWMC Version Register */ + AT91_REG Reserved1[ 64 ]; /* */ + AT91S_PWMC_CH PWMC_CH[ 4 ]; /* PWMC Channel */ +} AT91S_PWMC, * AT91PS_PWMC; + +/* -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- */ +#define AT91C_PWMC_DIVA ( ( unsigned int ) 0xFF << 0 ) /* (PWMC) CLKA divide factor. */ +#define AT91C_PWMC_PREA ( ( unsigned int ) 0xF << 8 ) /* (PWMC) Divider Input Clock Prescaler A */ +#define AT91C_PWMC_PREA_MCK ( ( unsigned int ) 0x0 << 8 ) /* (PWMC) */ +#define AT91C_PWMC_DIVB ( ( unsigned int ) 0xFF << 16 ) /* (PWMC) CLKB divide factor. */ +#define AT91C_PWMC_PREB ( ( unsigned int ) 0xF << 24 ) /* (PWMC) Divider Input Clock Prescaler B */ +#define AT91C_PWMC_PREB_MCK ( ( unsigned int ) 0x0 << 24 ) /* (PWMC) */ +/* -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- */ +#define AT91C_PWMC_CHID0 ( ( unsigned int ) 0x1 << 0 ) /* (PWMC) Channel ID 0 */ +#define AT91C_PWMC_CHID1 ( ( unsigned int ) 0x1 << 1 ) /* (PWMC) Channel ID 1 */ +#define AT91C_PWMC_CHID2 ( ( unsigned int ) 0x1 << 2 ) /* (PWMC) Channel ID 2 */ +#define AT91C_PWMC_CHID3 ( ( unsigned int ) 0x1 << 3 ) /* (PWMC) Channel ID 3 */ +/* -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- */ +/* -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- */ +/* -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- */ +/* -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- */ +/* -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- */ +/* -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR USB Device Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_UDP +{ + AT91_REG UDP_NUM; /* Frame Number Register */ + AT91_REG UDP_GLBSTATE; /* Global State Register */ + AT91_REG UDP_FADDR; /* Function Address Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG UDP_IER; /* Interrupt Enable Register */ + AT91_REG UDP_IDR; /* Interrupt Disable Register */ + AT91_REG UDP_IMR; /* Interrupt Mask Register */ + AT91_REG UDP_ISR; /* Interrupt Status Register */ + AT91_REG UDP_ICR; /* Interrupt Clear Register */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG UDP_RSTEP; /* Reset Endpoint Register */ + AT91_REG Reserved2[ 1 ]; /* */ + AT91_REG UDP_CSR[ 6 ]; /* Endpoint Control and Status Register */ + AT91_REG Reserved3[ 2 ]; /* */ + AT91_REG UDP_FDR[ 6 ]; /* Endpoint FIFO Data Register */ + AT91_REG Reserved4[ 3 ]; /* */ + AT91_REG UDP_TXVC; /* Transceiver Control Register */ +} AT91S_UDP, * AT91PS_UDP; + +/* -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- */ +#define AT91C_UDP_FRM_NUM ( ( unsigned int ) 0x7FF << 0 ) /* (UDP) Frame Number as Defined in the Packet Field Formats */ +#define AT91C_UDP_FRM_ERR ( ( unsigned int ) 0x1 << 16 ) /* (UDP) Frame Error */ +#define AT91C_UDP_FRM_OK ( ( unsigned int ) 0x1 << 17 ) /* (UDP) Frame OK */ +/* -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- */ +#define AT91C_UDP_FADDEN ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Function Address Enable */ +#define AT91C_UDP_CONFG ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Configured */ +#define AT91C_UDP_ESR ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Enable Send Resume */ +#define AT91C_UDP_RSMINPR ( ( unsigned int ) 0x1 << 3 ) /* (UDP) A Resume Has Been Sent to the Host */ +#define AT91C_UDP_RMWUPE ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Remote Wake Up Enable */ +/* -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- */ +#define AT91C_UDP_FADD ( ( unsigned int ) 0xFF << 0 ) /* (UDP) Function Address Value */ +#define AT91C_UDP_FEN ( ( unsigned int ) 0x1 << 8 ) /* (UDP) Function Enable */ +/* -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- */ +#define AT91C_UDP_EPINT0 ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Endpoint 0 Interrupt */ +#define AT91C_UDP_EPINT1 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Endpoint 0 Interrupt */ +#define AT91C_UDP_EPINT2 ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Endpoint 2 Interrupt */ +#define AT91C_UDP_EPINT3 ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Endpoint 3 Interrupt */ +#define AT91C_UDP_EPINT4 ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Endpoint 4 Interrupt */ +#define AT91C_UDP_EPINT5 ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Endpoint 5 Interrupt */ +#define AT91C_UDP_RXSUSP ( ( unsigned int ) 0x1 << 8 ) /* (UDP) USB Suspend Interrupt */ +#define AT91C_UDP_RXRSM ( ( unsigned int ) 0x1 << 9 ) /* (UDP) USB Resume Interrupt */ +#define AT91C_UDP_EXTRSM ( ( unsigned int ) 0x1 << 10 ) /* (UDP) USB External Resume Interrupt */ +#define AT91C_UDP_SOFINT ( ( unsigned int ) 0x1 << 11 ) /* (UDP) USB Start Of frame Interrupt */ +#define AT91C_UDP_WAKEUP ( ( unsigned int ) 0x1 << 13 ) /* (UDP) USB Resume Interrupt */ +/* -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- */ +/* -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- */ +/* -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- */ +#define AT91C_UDP_ENDBUSRES ( ( unsigned int ) 0x1 << 12 ) /* (UDP) USB End Of Bus Reset Interrupt */ +/* -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- */ +/* -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- */ +#define AT91C_UDP_EP0 ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Reset Endpoint 0 */ +#define AT91C_UDP_EP1 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Reset Endpoint 1 */ +#define AT91C_UDP_EP2 ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Reset Endpoint 2 */ +#define AT91C_UDP_EP3 ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Reset Endpoint 3 */ +#define AT91C_UDP_EP4 ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Reset Endpoint 4 */ +#define AT91C_UDP_EP5 ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Reset Endpoint 5 */ +/* -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- */ +#define AT91C_UDP_TXCOMP ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Generates an IN packet with data previously written in the DPR */ +#define AT91C_UDP_RX_DATA_BK0 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Receive Data Bank 0 */ +#define AT91C_UDP_RXSETUP ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Sends STALL to the Host (Control endpoints) */ +#define AT91C_UDP_ISOERROR ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Isochronous error (Isochronous endpoints) */ +#define AT91C_UDP_TXPKTRDY ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Transmit Packet Ready */ +#define AT91C_UDP_FORCESTALL ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). */ +#define AT91C_UDP_RX_DATA_BK1 ( ( unsigned int ) 0x1 << 6 ) /* (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). */ +#define AT91C_UDP_DIR ( ( unsigned int ) 0x1 << 7 ) /* (UDP) Transfer Direction */ +#define AT91C_UDP_EPTYPE ( ( unsigned int ) 0x7 << 8 ) /* (UDP) Endpoint type */ +#define AT91C_UDP_EPTYPE_CTRL ( ( unsigned int ) 0x0 << 8 ) /* (UDP) Control */ +#define AT91C_UDP_EPTYPE_ISO_OUT ( ( unsigned int ) 0x1 << 8 ) /* (UDP) Isochronous OUT */ +#define AT91C_UDP_EPTYPE_BULK_OUT ( ( unsigned int ) 0x2 << 8 ) /* (UDP) Bulk OUT */ +#define AT91C_UDP_EPTYPE_INT_OUT ( ( unsigned int ) 0x3 << 8 ) /* (UDP) Interrupt OUT */ +#define AT91C_UDP_EPTYPE_ISO_IN ( ( unsigned int ) 0x5 << 8 ) /* (UDP) Isochronous IN */ +#define AT91C_UDP_EPTYPE_BULK_IN ( ( unsigned int ) 0x6 << 8 ) /* (UDP) Bulk IN */ +#define AT91C_UDP_EPTYPE_INT_IN ( ( unsigned int ) 0x7 << 8 ) /* (UDP) Interrupt IN */ +#define AT91C_UDP_DTGLE ( ( unsigned int ) 0x1 << 11 ) /* (UDP) Data Toggle */ +#define AT91C_UDP_EPEDS ( ( unsigned int ) 0x1 << 15 ) /* (UDP) Endpoint Enable Disable */ +#define AT91C_UDP_RXBYTECNT ( ( unsigned int ) 0x7FF << 16 ) /* (UDP) Number Of Bytes Available in the FIFO */ +/* -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- */ +#define AT91C_UDP_TXVDIS ( ( unsigned int ) 0x1 << 8 ) /* (UDP) */ +#define AT91C_UDP_PUON ( ( unsigned int ) 0x1 << 9 ) /* (UDP) Pull-up ON */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_TC +{ + AT91_REG TC_CCR; /* Channel Control Register */ + AT91_REG TC_CMR; /* Channel Mode Register (Capture Mode / Waveform Mode) */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG TC_CV; /* Counter Value */ + AT91_REG TC_RA; /* Register A */ + AT91_REG TC_RB; /* Register B */ + AT91_REG TC_RC; /* Register C */ + AT91_REG TC_SR; /* Status Register */ + AT91_REG TC_IER; /* Interrupt Enable Register */ + AT91_REG TC_IDR; /* Interrupt Disable Register */ + AT91_REG TC_IMR; /* Interrupt Mask Register */ +} AT91S_TC, * AT91PS_TC; + +/* -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- */ +#define AT91C_TC_CLKEN ( ( unsigned int ) 0x1 << 0 ) /* (TC) Counter Clock Enable Command */ +#define AT91C_TC_CLKDIS ( ( unsigned int ) 0x1 << 1 ) /* (TC) Counter Clock Disable Command */ +#define AT91C_TC_SWTRG ( ( unsigned int ) 0x1 << 2 ) /* (TC) Software Trigger Command */ +/* -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- */ +#define AT91C_TC_CLKS ( ( unsigned int ) 0x7 << 0 ) /* (TC) Clock Selection */ +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ( ( unsigned int ) 0x0 ) /* (TC) Clock selected: TIMER_DIV1_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ( ( unsigned int ) 0x1 ) /* (TC) Clock selected: TIMER_DIV2_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ( ( unsigned int ) 0x2 ) /* (TC) Clock selected: TIMER_DIV3_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ( ( unsigned int ) 0x3 ) /* (TC) Clock selected: TIMER_DIV4_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ( ( unsigned int ) 0x4 ) /* (TC) Clock selected: TIMER_DIV5_CLOCK */ +#define AT91C_TC_CLKS_XC0 ( ( unsigned int ) 0x5 ) /* (TC) Clock selected: XC0 */ +#define AT91C_TC_CLKS_XC1 ( ( unsigned int ) 0x6 ) /* (TC) Clock selected: XC1 */ +#define AT91C_TC_CLKS_XC2 ( ( unsigned int ) 0x7 ) /* (TC) Clock selected: XC2 */ +#define AT91C_TC_CLKI ( ( unsigned int ) 0x1 << 3 ) /* (TC) Clock Invert */ +#define AT91C_TC_BURST ( ( unsigned int ) 0x3 << 4 ) /* (TC) Burst Signal Selection */ +#define AT91C_TC_BURST_NONE ( ( unsigned int ) 0x0 << 4 ) /* (TC) The clock is not gated by an external signal */ +#define AT91C_TC_BURST_XC0 ( ( unsigned int ) 0x1 << 4 ) /* (TC) XC0 is ANDed with the selected clock */ +#define AT91C_TC_BURST_XC1 ( ( unsigned int ) 0x2 << 4 ) /* (TC) XC1 is ANDed with the selected clock */ +#define AT91C_TC_BURST_XC2 ( ( unsigned int ) 0x3 << 4 ) /* (TC) XC2 is ANDed with the selected clock */ +#define AT91C_TC_CPCSTOP ( ( unsigned int ) 0x1 << 6 ) /* (TC) Counter Clock Stopped with RC Compare */ +#define AT91C_TC_LDBSTOP ( ( unsigned int ) 0x1 << 6 ) /* (TC) Counter Clock Stopped with RB Loading */ +#define AT91C_TC_CPCDIS ( ( unsigned int ) 0x1 << 7 ) /* (TC) Counter Clock Disable with RC Compare */ +#define AT91C_TC_LDBDIS ( ( unsigned int ) 0x1 << 7 ) /* (TC) Counter Clock Disabled with RB Loading */ +#define AT91C_TC_ETRGEDG ( ( unsigned int ) 0x3 << 8 ) /* (TC) External Trigger Edge Selection */ +#define AT91C_TC_ETRGEDG_NONE ( ( unsigned int ) 0x0 << 8 ) /* (TC) Edge: None */ +#define AT91C_TC_ETRGEDG_RISING ( ( unsigned int ) 0x1 << 8 ) /* (TC) Edge: rising edge */ +#define AT91C_TC_ETRGEDG_FALLING ( ( unsigned int ) 0x2 << 8 ) /* (TC) Edge: falling edge */ +#define AT91C_TC_ETRGEDG_BOTH ( ( unsigned int ) 0x3 << 8 ) /* (TC) Edge: each edge */ +#define AT91C_TC_EEVTEDG ( ( unsigned int ) 0x3 << 8 ) /* (TC) External Event Edge Selection */ +#define AT91C_TC_EEVTEDG_NONE ( ( unsigned int ) 0x0 << 8 ) /* (TC) Edge: None */ +#define AT91C_TC_EEVTEDG_RISING ( ( unsigned int ) 0x1 << 8 ) /* (TC) Edge: rising edge */ +#define AT91C_TC_EEVTEDG_FALLING ( ( unsigned int ) 0x2 << 8 ) /* (TC) Edge: falling edge */ +#define AT91C_TC_EEVTEDG_BOTH ( ( unsigned int ) 0x3 << 8 ) /* (TC) Edge: each edge */ +#define AT91C_TC_EEVT ( ( unsigned int ) 0x3 << 10 ) /* (TC) External Event Selection */ +#define AT91C_TC_EEVT_TIOB ( ( unsigned int ) 0x0 << 10 ) /* (TC) Signal selected as external event: TIOB TIOB direction: input */ +#define AT91C_TC_EEVT_XC0 ( ( unsigned int ) 0x1 << 10 ) /* (TC) Signal selected as external event: XC0 TIOB direction: output */ +#define AT91C_TC_EEVT_XC1 ( ( unsigned int ) 0x2 << 10 ) /* (TC) Signal selected as external event: XC1 TIOB direction: output */ +#define AT91C_TC_EEVT_XC2 ( ( unsigned int ) 0x3 << 10 ) /* (TC) Signal selected as external event: XC2 TIOB direction: output */ +#define AT91C_TC_ABETRG ( ( unsigned int ) 0x1 << 10 ) /* (TC) TIOA or TIOB External Trigger Selection */ +#define AT91C_TC_ENETRG ( ( unsigned int ) 0x1 << 12 ) /* (TC) External Event Trigger enable */ +#define AT91C_TC_WAVESEL ( ( unsigned int ) 0x3 << 13 ) /* (TC) Waveform Selection */ +#define AT91C_TC_WAVESEL_UP ( ( unsigned int ) 0x0 << 13 ) /* (TC) UP mode without atomatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UPDOWN ( ( unsigned int ) 0x1 << 13 ) /* (TC) UPDOWN mode without automatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UP_AUTO ( ( unsigned int ) 0x2 << 13 ) /* (TC) UP mode with automatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UPDOWN_AUTO ( ( unsigned int ) 0x3 << 13 ) /* (TC) UPDOWN mode with automatic trigger on RC Compare */ +#define AT91C_TC_CPCTRG ( ( unsigned int ) 0x1 << 14 ) /* (TC) RC Compare Trigger Enable */ +#define AT91C_TC_WAVE ( ( unsigned int ) 0x1 << 15 ) /* (TC) */ +#define AT91C_TC_ACPA ( ( unsigned int ) 0x3 << 16 ) /* (TC) RA Compare Effect on TIOA */ +#define AT91C_TC_ACPA_NONE ( ( unsigned int ) 0x0 << 16 ) /* (TC) Effect: none */ +#define AT91C_TC_ACPA_SET ( ( unsigned int ) 0x1 << 16 ) /* (TC) Effect: set */ +#define AT91C_TC_ACPA_CLEAR ( ( unsigned int ) 0x2 << 16 ) /* (TC) Effect: clear */ +#define AT91C_TC_ACPA_TOGGLE ( ( unsigned int ) 0x3 << 16 ) /* (TC) Effect: toggle */ +#define AT91C_TC_LDRA ( ( unsigned int ) 0x3 << 16 ) /* (TC) RA Loading Selection */ +#define AT91C_TC_LDRA_NONE ( ( unsigned int ) 0x0 << 16 ) /* (TC) Edge: None */ +#define AT91C_TC_LDRA_RISING ( ( unsigned int ) 0x1 << 16 ) /* (TC) Edge: rising edge of TIOA */ +#define AT91C_TC_LDRA_FALLING ( ( unsigned int ) 0x2 << 16 ) /* (TC) Edge: falling edge of TIOA */ +#define AT91C_TC_LDRA_BOTH ( ( unsigned int ) 0x3 << 16 ) /* (TC) Edge: each edge of TIOA */ +#define AT91C_TC_ACPC ( ( unsigned int ) 0x3 << 18 ) /* (TC) RC Compare Effect on TIOA */ +#define AT91C_TC_ACPC_NONE ( ( unsigned int ) 0x0 << 18 ) /* (TC) Effect: none */ +#define AT91C_TC_ACPC_SET ( ( unsigned int ) 0x1 << 18 ) /* (TC) Effect: set */ +#define AT91C_TC_ACPC_CLEAR ( ( unsigned int ) 0x2 << 18 ) /* (TC) Effect: clear */ +#define AT91C_TC_ACPC_TOGGLE ( ( unsigned int ) 0x3 << 18 ) /* (TC) Effect: toggle */ +#define AT91C_TC_LDRB ( ( unsigned int ) 0x3 << 18 ) /* (TC) RB Loading Selection */ +#define AT91C_TC_LDRB_NONE ( ( unsigned int ) 0x0 << 18 ) /* (TC) Edge: None */ +#define AT91C_TC_LDRB_RISING ( ( unsigned int ) 0x1 << 18 ) /* (TC) Edge: rising edge of TIOA */ +#define AT91C_TC_LDRB_FALLING ( ( unsigned int ) 0x2 << 18 ) /* (TC) Edge: falling edge of TIOA */ +#define AT91C_TC_LDRB_BOTH ( ( unsigned int ) 0x3 << 18 ) /* (TC) Edge: each edge of TIOA */ +#define AT91C_TC_AEEVT ( ( unsigned int ) 0x3 << 20 ) /* (TC) External Event Effect on TIOA */ +#define AT91C_TC_AEEVT_NONE ( ( unsigned int ) 0x0 << 20 ) /* (TC) Effect: none */ +#define AT91C_TC_AEEVT_SET ( ( unsigned int ) 0x1 << 20 ) /* (TC) Effect: set */ +#define AT91C_TC_AEEVT_CLEAR ( ( unsigned int ) 0x2 << 20 ) /* (TC) Effect: clear */ +#define AT91C_TC_AEEVT_TOGGLE ( ( unsigned int ) 0x3 << 20 ) /* (TC) Effect: toggle */ +#define AT91C_TC_ASWTRG ( ( unsigned int ) 0x3 << 22 ) /* (TC) Software Trigger Effect on TIOA */ +#define AT91C_TC_ASWTRG_NONE ( ( unsigned int ) 0x0 << 22 ) /* (TC) Effect: none */ +#define AT91C_TC_ASWTRG_SET ( ( unsigned int ) 0x1 << 22 ) /* (TC) Effect: set */ +#define AT91C_TC_ASWTRG_CLEAR ( ( unsigned int ) 0x2 << 22 ) /* (TC) Effect: clear */ +#define AT91C_TC_ASWTRG_TOGGLE ( ( unsigned int ) 0x3 << 22 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BCPB ( ( unsigned int ) 0x3 << 24 ) /* (TC) RB Compare Effect on TIOB */ +#define AT91C_TC_BCPB_NONE ( ( unsigned int ) 0x0 << 24 ) /* (TC) Effect: none */ +#define AT91C_TC_BCPB_SET ( ( unsigned int ) 0x1 << 24 ) /* (TC) Effect: set */ +#define AT91C_TC_BCPB_CLEAR ( ( unsigned int ) 0x2 << 24 ) /* (TC) Effect: clear */ +#define AT91C_TC_BCPB_TOGGLE ( ( unsigned int ) 0x3 << 24 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BCPC ( ( unsigned int ) 0x3 << 26 ) /* (TC) RC Compare Effect on TIOB */ +#define AT91C_TC_BCPC_NONE ( ( unsigned int ) 0x0 << 26 ) /* (TC) Effect: none */ +#define AT91C_TC_BCPC_SET ( ( unsigned int ) 0x1 << 26 ) /* (TC) Effect: set */ +#define AT91C_TC_BCPC_CLEAR ( ( unsigned int ) 0x2 << 26 ) /* (TC) Effect: clear */ +#define AT91C_TC_BCPC_TOGGLE ( ( unsigned int ) 0x3 << 26 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BEEVT ( ( unsigned int ) 0x3 << 28 ) /* (TC) External Event Effect on TIOB */ +#define AT91C_TC_BEEVT_NONE ( ( unsigned int ) 0x0 << 28 ) /* (TC) Effect: none */ +#define AT91C_TC_BEEVT_SET ( ( unsigned int ) 0x1 << 28 ) /* (TC) Effect: set */ +#define AT91C_TC_BEEVT_CLEAR ( ( unsigned int ) 0x2 << 28 ) /* (TC) Effect: clear */ +#define AT91C_TC_BEEVT_TOGGLE ( ( unsigned int ) 0x3 << 28 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BSWTRG ( ( unsigned int ) 0x3 << 30 ) /* (TC) Software Trigger Effect on TIOB */ +#define AT91C_TC_BSWTRG_NONE ( ( unsigned int ) 0x0 << 30 ) /* (TC) Effect: none */ +#define AT91C_TC_BSWTRG_SET ( ( unsigned int ) 0x1 << 30 ) /* (TC) Effect: set */ +#define AT91C_TC_BSWTRG_CLEAR ( ( unsigned int ) 0x2 << 30 ) /* (TC) Effect: clear */ +#define AT91C_TC_BSWTRG_TOGGLE ( ( unsigned int ) 0x3 << 30 ) /* (TC) Effect: toggle */ +/* -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- */ +#define AT91C_TC_COVFS ( ( unsigned int ) 0x1 << 0 ) /* (TC) Counter Overflow */ +#define AT91C_TC_LOVRS ( ( unsigned int ) 0x1 << 1 ) /* (TC) Load Overrun */ +#define AT91C_TC_CPAS ( ( unsigned int ) 0x1 << 2 ) /* (TC) RA Compare */ +#define AT91C_TC_CPBS ( ( unsigned int ) 0x1 << 3 ) /* (TC) RB Compare */ +#define AT91C_TC_CPCS ( ( unsigned int ) 0x1 << 4 ) /* (TC) RC Compare */ +#define AT91C_TC_LDRAS ( ( unsigned int ) 0x1 << 5 ) /* (TC) RA Loading */ +#define AT91C_TC_LDRBS ( ( unsigned int ) 0x1 << 6 ) /* (TC) RB Loading */ +#define AT91C_TC_ETRGS ( ( unsigned int ) 0x1 << 7 ) /* (TC) External Trigger */ +#define AT91C_TC_CLKSTA ( ( unsigned int ) 0x1 << 16 ) /* (TC) Clock Enabling */ +#define AT91C_TC_MTIOA ( ( unsigned int ) 0x1 << 17 ) /* (TC) TIOA Mirror */ +#define AT91C_TC_MTIOB ( ( unsigned int ) 0x1 << 18 ) /* (TC) TIOA Mirror */ +/* -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- */ +/* -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- */ +/* -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Timer Counter Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_TCB +{ + AT91S_TC TCB_TC0; /* TC Channel 0 */ + AT91_REG Reserved0[ 4 ]; /* */ + AT91S_TC TCB_TC1; /* TC Channel 1 */ + AT91_REG Reserved1[ 4 ]; /* */ + AT91S_TC TCB_TC2; /* TC Channel 2 */ + AT91_REG Reserved2[ 4 ]; /* */ + AT91_REG TCB_BCR; /* TC Block Control Register */ + AT91_REG TCB_BMR; /* TC Block Mode Register */ +} AT91S_TCB, * AT91PS_TCB; + +/* -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- */ +#define AT91C_TCB_SYNC ( ( unsigned int ) 0x1 << 0 ) /* (TCB) Synchro Command */ +/* -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- */ +#define AT91C_TCB_TC0XC0S ( ( unsigned int ) 0x3 << 0 ) /* (TCB) External Clock Signal 0 Selection */ +#define AT91C_TCB_TC0XC0S_TCLK0 ( ( unsigned int ) 0x0 ) /* (TCB) TCLK0 connected to XC0 */ +#define AT91C_TCB_TC0XC0S_NONE ( ( unsigned int ) 0x1 ) /* (TCB) None signal connected to XC0 */ +#define AT91C_TCB_TC0XC0S_TIOA1 ( ( unsigned int ) 0x2 ) /* (TCB) TIOA1 connected to XC0 */ +#define AT91C_TCB_TC0XC0S_TIOA2 ( ( unsigned int ) 0x3 ) /* (TCB) TIOA2 connected to XC0 */ +#define AT91C_TCB_TC1XC1S ( ( unsigned int ) 0x3 << 2 ) /* (TCB) External Clock Signal 1 Selection */ +#define AT91C_TCB_TC1XC1S_TCLK1 ( ( unsigned int ) 0x0 << 2 ) /* (TCB) TCLK1 connected to XC1 */ +#define AT91C_TCB_TC1XC1S_NONE ( ( unsigned int ) 0x1 << 2 ) /* (TCB) None signal connected to XC1 */ +#define AT91C_TCB_TC1XC1S_TIOA0 ( ( unsigned int ) 0x2 << 2 ) /* (TCB) TIOA0 connected to XC1 */ +#define AT91C_TCB_TC1XC1S_TIOA2 ( ( unsigned int ) 0x3 << 2 ) /* (TCB) TIOA2 connected to XC1 */ +#define AT91C_TCB_TC2XC2S ( ( unsigned int ) 0x3 << 4 ) /* (TCB) External Clock Signal 2 Selection */ +#define AT91C_TCB_TC2XC2S_TCLK2 ( ( unsigned int ) 0x0 << 4 ) /* (TCB) TCLK2 connected to XC2 */ +#define AT91C_TCB_TC2XC2S_NONE ( ( unsigned int ) 0x1 << 4 ) /* (TCB) None signal connected to XC2 */ +#define AT91C_TCB_TC2XC2S_TIOA0 ( ( unsigned int ) 0x2 << 4 ) /* (TCB) TIOA0 connected to XC2 */ +#define AT91C_TCB_TC2XC2S_TIOA1 ( ( unsigned int ) 0x3 << 4 ) /* (TCB) TIOA2 connected to XC2 */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_CAN_MB +{ + AT91_REG CAN_MB_MMR; /* MailBox Mode Register */ + AT91_REG CAN_MB_MAM; /* MailBox Acceptance Mask Register */ + AT91_REG CAN_MB_MID; /* MailBox ID Register */ + AT91_REG CAN_MB_MFID; /* MailBox Family ID Register */ + AT91_REG CAN_MB_MSR; /* MailBox Status Register */ + AT91_REG CAN_MB_MDL; /* MailBox Data Low Register */ + AT91_REG CAN_MB_MDH; /* MailBox Data High Register */ + AT91_REG CAN_MB_MCR; /* MailBox Control Register */ +} AT91S_CAN_MB, * AT91PS_CAN_MB; + +/* -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- */ +#define AT91C_CAN_MTIMEMARK ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN_MB) Mailbox Timemark */ +#define AT91C_CAN_PRIOR ( ( unsigned int ) 0xF << 16 ) /* (CAN_MB) Mailbox Priority */ +#define AT91C_CAN_MOT ( ( unsigned int ) 0x7 << 24 ) /* (CAN_MB) Mailbox Object Type */ +#define AT91C_CAN_MOT_DIS ( ( unsigned int ) 0x0 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_RX ( ( unsigned int ) 0x1 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_RXOVERWRITE ( ( unsigned int ) 0x2 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_TX ( ( unsigned int ) 0x3 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_CONSUMER ( ( unsigned int ) 0x4 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_PRODUCER ( ( unsigned int ) 0x5 << 24 ) /* (CAN_MB) */ +/* -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- */ +#define AT91C_CAN_MIDvB ( ( unsigned int ) 0x3FFFF << 0 ) /* (CAN_MB) Complementary bits for identifier in extended mode */ +#define AT91C_CAN_MIDvA ( ( unsigned int ) 0x7FF << 18 ) /* (CAN_MB) Identifier for standard frame mode */ +#define AT91C_CAN_MIDE ( ( unsigned int ) 0x1 << 29 ) /* (CAN_MB) Identifier Version */ +/* -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- */ +/* -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- */ +/* -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- */ +#define AT91C_CAN_MTIMESTAMP ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN_MB) Timer Value */ +#define AT91C_CAN_MDLC ( ( unsigned int ) 0xF << 16 ) /* (CAN_MB) Mailbox Data Length Code */ +#define AT91C_CAN_MRTR ( ( unsigned int ) 0x1 << 20 ) /* (CAN_MB) Mailbox Remote Transmission Request */ +#define AT91C_CAN_MABT ( ( unsigned int ) 0x1 << 22 ) /* (CAN_MB) Mailbox Message Abort */ +#define AT91C_CAN_MRDY ( ( unsigned int ) 0x1 << 23 ) /* (CAN_MB) Mailbox Ready */ +#define AT91C_CAN_MMI ( ( unsigned int ) 0x1 << 24 ) /* (CAN_MB) Mailbox Message Ignored */ +/* -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- */ +/* -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- */ +/* -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- */ +#define AT91C_CAN_MACR ( ( unsigned int ) 0x1 << 22 ) /* (CAN_MB) Abort Request for Mailbox */ +#define AT91C_CAN_MTCR ( ( unsigned int ) 0x1 << 23 ) /* (CAN_MB) Mailbox Transfer Command */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Control Area Network Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_CAN +{ + AT91_REG CAN_MR; /* Mode Register */ + AT91_REG CAN_IER; /* Interrupt Enable Register */ + AT91_REG CAN_IDR; /* Interrupt Disable Register */ + AT91_REG CAN_IMR; /* Interrupt Mask Register */ + AT91_REG CAN_SR; /* Status Register */ + AT91_REG CAN_BR; /* Baudrate Register */ + AT91_REG CAN_TIM; /* Timer Register */ + AT91_REG CAN_TIMESTP; /* Time Stamp Register */ + AT91_REG CAN_ECR; /* Error Counter Register */ + AT91_REG CAN_TCR; /* Transfer Command Register */ + AT91_REG CAN_ACR; /* Abort Command Register */ + AT91_REG Reserved0[ 52 ]; /* */ + AT91_REG CAN_VR; /* Version Register */ + AT91_REG Reserved1[ 64 ]; /* */ + AT91S_CAN_MB CAN_MB0; /* CAN Mailbox 0 */ + AT91S_CAN_MB CAN_MB1; /* CAN Mailbox 1 */ + AT91S_CAN_MB CAN_MB2; /* CAN Mailbox 2 */ + AT91S_CAN_MB CAN_MB3; /* CAN Mailbox 3 */ + AT91S_CAN_MB CAN_MB4; /* CAN Mailbox 4 */ + AT91S_CAN_MB CAN_MB5; /* CAN Mailbox 5 */ + AT91S_CAN_MB CAN_MB6; /* CAN Mailbox 6 */ + AT91S_CAN_MB CAN_MB7; /* CAN Mailbox 7 */ + AT91S_CAN_MB CAN_MB8; /* CAN Mailbox 8 */ + AT91S_CAN_MB CAN_MB9; /* CAN Mailbox 9 */ + AT91S_CAN_MB CAN_MB10; /* CAN Mailbox 10 */ + AT91S_CAN_MB CAN_MB11; /* CAN Mailbox 11 */ + AT91S_CAN_MB CAN_MB12; /* CAN Mailbox 12 */ + AT91S_CAN_MB CAN_MB13; /* CAN Mailbox 13 */ + AT91S_CAN_MB CAN_MB14; /* CAN Mailbox 14 */ + AT91S_CAN_MB CAN_MB15; /* CAN Mailbox 15 */ +} AT91S_CAN, * AT91PS_CAN; + +/* -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- */ +#define AT91C_CAN_CANEN ( ( unsigned int ) 0x1 << 0 ) /* (CAN) CAN Controller Enable */ +#define AT91C_CAN_LPM ( ( unsigned int ) 0x1 << 1 ) /* (CAN) Disable/Enable Low Power Mode */ +#define AT91C_CAN_ABM ( ( unsigned int ) 0x1 << 2 ) /* (CAN) Disable/Enable Autobaud/Listen Mode */ +#define AT91C_CAN_OVL ( ( unsigned int ) 0x1 << 3 ) /* (CAN) Disable/Enable Overload Frame */ +#define AT91C_CAN_TEOF ( ( unsigned int ) 0x1 << 4 ) /* (CAN) Time Stamp messages at each end of Frame */ +#define AT91C_CAN_TTM ( ( unsigned int ) 0x1 << 5 ) /* (CAN) Disable/Enable Time Trigger Mode */ +#define AT91C_CAN_TIMFRZ ( ( unsigned int ) 0x1 << 6 ) /* (CAN) Enable Timer Freeze */ +#define AT91C_CAN_DRPT ( ( unsigned int ) 0x1 << 7 ) /* (CAN) Disable Repeat */ +/* -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- */ +#define AT91C_CAN_MB0 ( ( unsigned int ) 0x1 << 0 ) /* (CAN) Mailbox 0 Flag */ +#define AT91C_CAN_MB1 ( ( unsigned int ) 0x1 << 1 ) /* (CAN) Mailbox 1 Flag */ +#define AT91C_CAN_MB2 ( ( unsigned int ) 0x1 << 2 ) /* (CAN) Mailbox 2 Flag */ +#define AT91C_CAN_MB3 ( ( unsigned int ) 0x1 << 3 ) /* (CAN) Mailbox 3 Flag */ +#define AT91C_CAN_MB4 ( ( unsigned int ) 0x1 << 4 ) /* (CAN) Mailbox 4 Flag */ +#define AT91C_CAN_MB5 ( ( unsigned int ) 0x1 << 5 ) /* (CAN) Mailbox 5 Flag */ +#define AT91C_CAN_MB6 ( ( unsigned int ) 0x1 << 6 ) /* (CAN) Mailbox 6 Flag */ +#define AT91C_CAN_MB7 ( ( unsigned int ) 0x1 << 7 ) /* (CAN) Mailbox 7 Flag */ +#define AT91C_CAN_MB8 ( ( unsigned int ) 0x1 << 8 ) /* (CAN) Mailbox 8 Flag */ +#define AT91C_CAN_MB9 ( ( unsigned int ) 0x1 << 9 ) /* (CAN) Mailbox 9 Flag */ +#define AT91C_CAN_MB10 ( ( unsigned int ) 0x1 << 10 ) /* (CAN) Mailbox 10 Flag */ +#define AT91C_CAN_MB11 ( ( unsigned int ) 0x1 << 11 ) /* (CAN) Mailbox 11 Flag */ +#define AT91C_CAN_MB12 ( ( unsigned int ) 0x1 << 12 ) /* (CAN) Mailbox 12 Flag */ +#define AT91C_CAN_MB13 ( ( unsigned int ) 0x1 << 13 ) /* (CAN) Mailbox 13 Flag */ +#define AT91C_CAN_MB14 ( ( unsigned int ) 0x1 << 14 ) /* (CAN) Mailbox 14 Flag */ +#define AT91C_CAN_MB15 ( ( unsigned int ) 0x1 << 15 ) /* (CAN) Mailbox 15 Flag */ +#define AT91C_CAN_ERRA ( ( unsigned int ) 0x1 << 16 ) /* (CAN) Error Active Mode Flag */ +#define AT91C_CAN_WARN ( ( unsigned int ) 0x1 << 17 ) /* (CAN) Warning Limit Flag */ +#define AT91C_CAN_ERRP ( ( unsigned int ) 0x1 << 18 ) /* (CAN) Error Passive Mode Flag */ +#define AT91C_CAN_BOFF ( ( unsigned int ) 0x1 << 19 ) /* (CAN) Bus Off Mode Flag */ +#define AT91C_CAN_SLEEP ( ( unsigned int ) 0x1 << 20 ) /* (CAN) Sleep Flag */ +#define AT91C_CAN_WAKEUP ( ( unsigned int ) 0x1 << 21 ) /* (CAN) Wakeup Flag */ +#define AT91C_CAN_TOVF ( ( unsigned int ) 0x1 << 22 ) /* (CAN) Timer Overflow Flag */ +#define AT91C_CAN_TSTP ( ( unsigned int ) 0x1 << 23 ) /* (CAN) Timestamp Flag */ +#define AT91C_CAN_CERR ( ( unsigned int ) 0x1 << 24 ) /* (CAN) CRC Error */ +#define AT91C_CAN_SERR ( ( unsigned int ) 0x1 << 25 ) /* (CAN) Stuffing Error */ +#define AT91C_CAN_AERR ( ( unsigned int ) 0x1 << 26 ) /* (CAN) Acknowledgment Error */ +#define AT91C_CAN_FERR ( ( unsigned int ) 0x1 << 27 ) /* (CAN) Form Error */ +#define AT91C_CAN_BERR ( ( unsigned int ) 0x1 << 28 ) /* (CAN) Bit Error */ +/* -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- */ +/* -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- */ +/* -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- */ +#define AT91C_CAN_RBSY ( ( unsigned int ) 0x1 << 29 ) /* (CAN) Receiver Busy */ +#define AT91C_CAN_TBSY ( ( unsigned int ) 0x1 << 30 ) /* (CAN) Transmitter Busy */ +#define AT91C_CAN_OVLY ( ( unsigned int ) 0x1 << 31 ) /* (CAN) Overload Busy */ +/* -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- */ +#define AT91C_CAN_PHASE2 ( ( unsigned int ) 0x7 << 0 ) /* (CAN) Phase 2 segment */ +#define AT91C_CAN_PHASE1 ( ( unsigned int ) 0x7 << 4 ) /* (CAN) Phase 1 segment */ +#define AT91C_CAN_PROPAG ( ( unsigned int ) 0x7 << 8 ) /* (CAN) Programmation time segment */ +#define AT91C_CAN_SYNC ( ( unsigned int ) 0x3 << 12 ) /* (CAN) Re-synchronization jump width segment */ +#define AT91C_CAN_BRP ( ( unsigned int ) 0x7F << 16 ) /* (CAN) Baudrate Prescaler */ +#define AT91C_CAN_SMP ( ( unsigned int ) 0x1 << 24 ) /* (CAN) Sampling mode */ +/* -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- */ +#define AT91C_CAN_TIMER ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN) Timer field */ +/* -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- */ +/* -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- */ +#define AT91C_CAN_REC ( ( unsigned int ) 0xFF << 0 ) /* (CAN) Receive Error Counter */ +#define AT91C_CAN_TEC ( ( unsigned int ) 0xFF << 16 ) /* (CAN) Transmit Error Counter */ +/* -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- */ +#define AT91C_CAN_TIMRST ( ( unsigned int ) 0x1 << 31 ) /* (CAN) Timer Reset Field */ +/* -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 */ +/* ***************************************************************************** */ +typedef struct _AT91S_EMAC +{ + AT91_REG EMAC_NCR; /* Network Control Register */ + AT91_REG EMAC_NCFGR; /* Network Configuration Register */ + AT91_REG EMAC_NSR; /* Network Status Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG EMAC_TSR; /* Transmit Status Register */ + AT91_REG EMAC_RBQP; /* Receive Buffer Queue Pointer */ + AT91_REG EMAC_TBQP; /* Transmit Buffer Queue Pointer */ + AT91_REG EMAC_RSR; /* Receive Status Register */ + AT91_REG EMAC_ISR; /* Interrupt Status Register */ + AT91_REG EMAC_IER; /* Interrupt Enable Register */ + AT91_REG EMAC_IDR; /* Interrupt Disable Register */ + AT91_REG EMAC_IMR; /* Interrupt Mask Register */ + AT91_REG EMAC_MAN; /* PHY Maintenance Register */ + AT91_REG EMAC_PTR; /* Pause Time Register */ + AT91_REG EMAC_PFR; /* Pause Frames received Register */ + AT91_REG EMAC_FTO; /* Frames Transmitted OK Register */ + AT91_REG EMAC_SCF; /* Single Collision Frame Register */ + AT91_REG EMAC_MCF; /* Multiple Collision Frame Register */ + AT91_REG EMAC_FRO; /* Frames Received OK Register */ + AT91_REG EMAC_FCSE; /* Frame Check Sequence Error Register */ + AT91_REG EMAC_ALE; /* Alignment Error Register */ + AT91_REG EMAC_DTF; /* Deferred Transmission Frame Register */ + AT91_REG EMAC_LCOL; /* Late Collision Register */ + AT91_REG EMAC_ECOL; /* Excessive Collision Register */ + AT91_REG EMAC_TUND; /* Transmit Underrun Error Register */ + AT91_REG EMAC_CSE; /* Carrier Sense Error Register */ + AT91_REG EMAC_RRE; /* Receive Resource Error Register */ + AT91_REG EMAC_ROV; /* Receive Overrun Errors Register */ + AT91_REG EMAC_RSE; /* Receive Symbol Errors Register */ + AT91_REG EMAC_ELE; /* Excessive Length Errors Register */ + AT91_REG EMAC_RJA; /* Receive Jabbers Register */ + AT91_REG EMAC_USF; /* Undersize Frames Register */ + AT91_REG EMAC_STE; /* SQE Test Error Register */ + AT91_REG EMAC_RLE; /* Receive Length Field Mismatch Register */ + AT91_REG EMAC_TPF; /* Transmitted Pause Frames Register */ + AT91_REG EMAC_HRB; /* Hash Address Bottom[31:0] */ + AT91_REG EMAC_HRT; /* Hash Address Top[63:32] */ + AT91_REG EMAC_SA1L; /* Specific Address 1 Bottom, First 4 bytes */ + AT91_REG EMAC_SA1H; /* Specific Address 1 Top, Last 2 bytes */ + AT91_REG EMAC_SA2L; /* Specific Address 2 Bottom, First 4 bytes */ + AT91_REG EMAC_SA2H; /* Specific Address 2 Top, Last 2 bytes */ + AT91_REG EMAC_SA3L; /* Specific Address 3 Bottom, First 4 bytes */ + AT91_REG EMAC_SA3H; /* Specific Address 3 Top, Last 2 bytes */ + AT91_REG EMAC_SA4L; /* Specific Address 4 Bottom, First 4 bytes */ + AT91_REG EMAC_SA4H; /* Specific Address 4 Top, Last 2 bytes */ + AT91_REG EMAC_TID; /* Type ID Checking Register */ + AT91_REG EMAC_TPQ; /* Transmit Pause Quantum Register */ + AT91_REG EMAC_USRIO; /* USER Input/Output Register */ + AT91_REG EMAC_WOL; /* Wake On LAN Register */ + AT91_REG Reserved1[ 13 ]; /* */ + AT91_REG EMAC_REV; /* Revision Register */ +} AT91S_EMAC, * AT91PS_EMAC; + +/* -------- EMAC_NCR : (EMAC Offset: 0x0) -------- */ +#define AT91C_EMAC_LB ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */ +#define AT91C_EMAC_LLB ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) Loopback local. */ +#define AT91C_EMAC_RE ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) Receive enable. */ +#define AT91C_EMAC_TE ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) Transmit enable. */ +#define AT91C_EMAC_MPE ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) Management port enable. */ +#define AT91C_EMAC_CLRSTAT ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) Clear statistics registers. */ +#define AT91C_EMAC_INCSTAT ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) Increment statistics registers. */ +#define AT91C_EMAC_WESTAT ( ( unsigned int ) 0x1 << 7 ) /* (EMAC) Write enable for statistics registers. */ +#define AT91C_EMAC_BP ( ( unsigned int ) 0x1 << 8 ) /* (EMAC) Back pressure. */ +#define AT91C_EMAC_TSTART ( ( unsigned int ) 0x1 << 9 ) /* (EMAC) Start Transmission. */ +#define AT91C_EMAC_THALT ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) Transmission Halt. */ +#define AT91C_EMAC_TPFR ( ( unsigned int ) 0x1 << 11 ) /* (EMAC) Transmit pause frame */ +#define AT91C_EMAC_TZQ ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) Transmit zero quantum pause frame */ +/* -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- */ +#define AT91C_EMAC_SPD ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) Speed. */ +#define AT91C_EMAC_FD ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) Full duplex. */ +#define AT91C_EMAC_JFRAME ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) Jumbo Frames. */ +#define AT91C_EMAC_CAF ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) Copy all frames. */ +#define AT91C_EMAC_NBC ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) No broadcast. */ +#define AT91C_EMAC_MTI ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) Multicast hash event enable */ +#define AT91C_EMAC_UNI ( ( unsigned int ) 0x1 << 7 ) /* (EMAC) Unicast hash enable. */ +#define AT91C_EMAC_BIG ( ( unsigned int ) 0x1 << 8 ) /* (EMAC) Receive 1522 bytes. */ +#define AT91C_EMAC_EAE ( ( unsigned int ) 0x1 << 9 ) /* (EMAC) External address match enable. */ +#define AT91C_EMAC_CLK ( ( unsigned int ) 0x3 << 10 ) /* (EMAC) */ +#define AT91C_EMAC_CLK_HCLK_8 ( ( unsigned int ) 0x0 << 10 ) /* (EMAC) HCLK divided by 8 */ +#define AT91C_EMAC_CLK_HCLK_16 ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) HCLK divided by 16 */ +#define AT91C_EMAC_CLK_HCLK_32 ( ( unsigned int ) 0x2 << 10 ) /* (EMAC) HCLK divided by 32 */ +#define AT91C_EMAC_CLK_HCLK_64 ( ( unsigned int ) 0x3 << 10 ) /* (EMAC) HCLK divided by 64 */ +#define AT91C_EMAC_RTY ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) */ +#define AT91C_EMAC_PAE ( ( unsigned int ) 0x1 << 13 ) /* (EMAC) */ +#define AT91C_EMAC_RBOF ( ( unsigned int ) 0x3 << 14 ) /* (EMAC) */ +#define AT91C_EMAC_RBOF_OFFSET_0 ( ( unsigned int ) 0x0 << 14 ) /* (EMAC) no offset from start of receive buffer */ +#define AT91C_EMAC_RBOF_OFFSET_1 ( ( unsigned int ) 0x1 << 14 ) /* (EMAC) one byte offset from start of receive buffer */ +#define AT91C_EMAC_RBOF_OFFSET_2 ( ( unsigned int ) 0x2 << 14 ) /* (EMAC) two bytes offset from start of receive buffer */ +#define AT91C_EMAC_RBOF_OFFSET_3 ( ( unsigned int ) 0x3 << 14 ) /* (EMAC) three bytes offset from start of receive buffer */ +#define AT91C_EMAC_RLCE ( ( unsigned int ) 0x1 << 16 ) /* (EMAC) Receive Length field Checking Enable */ +#define AT91C_EMAC_DRFCS ( ( unsigned int ) 0x1 << 17 ) /* (EMAC) Discard Receive FCS */ +#define AT91C_EMAC_EFRHD ( ( unsigned int ) 0x1 << 18 ) /* (EMAC) */ +#define AT91C_EMAC_IRXFCS ( ( unsigned int ) 0x1 << 19 ) /* (EMAC) Ignore RX FCS */ +/* -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- */ +#define AT91C_EMAC_LINKR ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_MDIO ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_IDLE ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */ +/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- */ +#define AT91C_EMAC_UBR ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_COL ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_RLES ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */ +#define AT91C_EMAC_TGO ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) Transmit Go */ +#define AT91C_EMAC_BEX ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) Buffers exhausted mid frame */ +#define AT91C_EMAC_COMP ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) */ +#define AT91C_EMAC_UND ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) */ +/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */ +#define AT91C_EMAC_BNA ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_REC ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_OVR ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */ +/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */ +#define AT91C_EMAC_MFD ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_RCOMP ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_RXUBR ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */ +#define AT91C_EMAC_TXUBR ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) */ +#define AT91C_EMAC_TUNDR ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) */ +#define AT91C_EMAC_RLEX ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) */ +#define AT91C_EMAC_TXERR ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) */ +#define AT91C_EMAC_TCOMP ( ( unsigned int ) 0x1 << 7 ) /* (EMAC) */ +#define AT91C_EMAC_LINK ( ( unsigned int ) 0x1 << 9 ) /* (EMAC) */ +#define AT91C_EMAC_ROVR ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) */ +#define AT91C_EMAC_HRESP ( ( unsigned int ) 0x1 << 11 ) /* (EMAC) */ +#define AT91C_EMAC_PFRE ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) */ +#define AT91C_EMAC_PTZ ( ( unsigned int ) 0x1 << 13 ) /* (EMAC) */ +/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */ +/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */ +/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */ +/* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */ +#define AT91C_EMAC_DATA ( ( unsigned int ) 0xFFFF << 0 ) /* (EMAC) */ +#define AT91C_EMAC_CODE ( ( unsigned int ) 0x3 << 16 ) /* (EMAC) */ +#define AT91C_EMAC_REGA ( ( unsigned int ) 0x1F << 18 ) /* (EMAC) */ +#define AT91C_EMAC_PHYA ( ( unsigned int ) 0x1F << 23 ) /* (EMAC) */ +#define AT91C_EMAC_RW ( ( unsigned int ) 0x3 << 28 ) /* (EMAC) */ +#define AT91C_EMAC_SOF ( ( unsigned int ) 0x3 << 30 ) /* (EMAC) */ +/* -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- */ +#define AT91C_EMAC_RMII ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) Reduce MII */ +/* -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- */ +#define AT91C_EMAC_IP ( ( unsigned int ) 0xFFFF << 0 ) /* (EMAC) ARP request IP address */ +#define AT91C_EMAC_MAG ( ( unsigned int ) 0x1 << 16 ) /* (EMAC) Magic packet event enable */ +#define AT91C_EMAC_ARP ( ( unsigned int ) 0x1 << 17 ) /* (EMAC) ARP request event enable */ +#define AT91C_EMAC_SA1 ( ( unsigned int ) 0x1 << 18 ) /* (EMAC) Specific address register 1 event enable */ +/* -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- */ +#define AT91C_EMAC_REVREF ( ( unsigned int ) 0xFFFF << 0 ) /* (EMAC) */ +#define AT91C_EMAC_PARTREF ( ( unsigned int ) 0xFFFF << 16 ) /* (EMAC) */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Analog to Digital Convertor */ +/* ***************************************************************************** */ +typedef struct _AT91S_ADC +{ + AT91_REG ADC_CR; /* ADC Control Register */ + AT91_REG ADC_MR; /* ADC Mode Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG ADC_CHER; /* ADC Channel Enable Register */ + AT91_REG ADC_CHDR; /* ADC Channel Disable Register */ + AT91_REG ADC_CHSR; /* ADC Channel Status Register */ + AT91_REG ADC_SR; /* ADC Status Register */ + AT91_REG ADC_LCDR; /* ADC Last Converted Data Register */ + AT91_REG ADC_IER; /* ADC Interrupt Enable Register */ + AT91_REG ADC_IDR; /* ADC Interrupt Disable Register */ + AT91_REG ADC_IMR; /* ADC Interrupt Mask Register */ + AT91_REG ADC_CDR0; /* ADC Channel Data Register 0 */ + AT91_REG ADC_CDR1; /* ADC Channel Data Register 1 */ + AT91_REG ADC_CDR2; /* ADC Channel Data Register 2 */ + AT91_REG ADC_CDR3; /* ADC Channel Data Register 3 */ + AT91_REG ADC_CDR4; /* ADC Channel Data Register 4 */ + AT91_REG ADC_CDR5; /* ADC Channel Data Register 5 */ + AT91_REG ADC_CDR6; /* ADC Channel Data Register 6 */ + AT91_REG ADC_CDR7; /* ADC Channel Data Register 7 */ + AT91_REG Reserved1[ 44 ]; /* */ + AT91_REG ADC_RPR; /* Receive Pointer Register */ + AT91_REG ADC_RCR; /* Receive Counter Register */ + AT91_REG ADC_TPR; /* Transmit Pointer Register */ + AT91_REG ADC_TCR; /* Transmit Counter Register */ + AT91_REG ADC_RNPR; /* Receive Next Pointer Register */ + AT91_REG ADC_RNCR; /* Receive Next Counter Register */ + AT91_REG ADC_TNPR; /* Transmit Next Pointer Register */ + AT91_REG ADC_TNCR; /* Transmit Next Counter Register */ + AT91_REG ADC_PTCR; /* PDC Transfer Control Register */ + AT91_REG ADC_PTSR; /* PDC Transfer Status Register */ +} AT91S_ADC, * AT91PS_ADC; + +/* -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- */ +#define AT91C_ADC_SWRST ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Software Reset */ +#define AT91C_ADC_START ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Start Conversion */ +/* -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- */ +#define AT91C_ADC_TRGEN ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Trigger Enable */ +#define AT91C_ADC_TRGEN_DIS ( ( unsigned int ) 0x0 ) /* (ADC) Hardware triggers are disabled. Starting a conversion is only possible by software */ +#define AT91C_ADC_TRGEN_EN ( ( unsigned int ) 0x1 ) /* (ADC) Hardware trigger selected by TRGSEL field is enabled. */ +#define AT91C_ADC_TRGSEL ( ( unsigned int ) 0x7 << 1 ) /* (ADC) Trigger Selection */ +#define AT91C_ADC_TRGSEL_TIOA0 ( ( unsigned int ) 0x0 << 1 ) /* (ADC) Selected TRGSEL = TIAO0 */ +#define AT91C_ADC_TRGSEL_TIOA1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Selected TRGSEL = TIAO1 */ +#define AT91C_ADC_TRGSEL_TIOA2 ( ( unsigned int ) 0x2 << 1 ) /* (ADC) Selected TRGSEL = TIAO2 */ +#define AT91C_ADC_TRGSEL_TIOA3 ( ( unsigned int ) 0x3 << 1 ) /* (ADC) Selected TRGSEL = TIAO3 */ +#define AT91C_ADC_TRGSEL_TIOA4 ( ( unsigned int ) 0x4 << 1 ) /* (ADC) Selected TRGSEL = TIAO4 */ +#define AT91C_ADC_TRGSEL_TIOA5 ( ( unsigned int ) 0x5 << 1 ) /* (ADC) Selected TRGSEL = TIAO5 */ +#define AT91C_ADC_TRGSEL_EXT ( ( unsigned int ) 0x6 << 1 ) /* (ADC) Selected TRGSEL = External Trigger */ +#define AT91C_ADC_LOWRES ( ( unsigned int ) 0x1 << 4 ) /* (ADC) Resolution. */ +#define AT91C_ADC_LOWRES_10_BIT ( ( unsigned int ) 0x0 << 4 ) /* (ADC) 10-bit resolution */ +#define AT91C_ADC_LOWRES_8_BIT ( ( unsigned int ) 0x1 << 4 ) /* (ADC) 8-bit resolution */ +#define AT91C_ADC_SLEEP ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Sleep Mode */ +#define AT91C_ADC_SLEEP_NORMAL_MODE ( ( unsigned int ) 0x0 << 5 ) /* (ADC) Normal Mode */ +#define AT91C_ADC_SLEEP_MODE ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Sleep Mode */ +#define AT91C_ADC_PRESCAL ( ( unsigned int ) 0x3F << 8 ) /* (ADC) Prescaler rate selection */ +#define AT91C_ADC_STARTUP ( ( unsigned int ) 0x1F << 16 ) /* (ADC) Startup Time */ +#define AT91C_ADC_SHTIM ( ( unsigned int ) 0xF << 24 ) /* (ADC) Sample & Hold Time */ +/* -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- */ +#define AT91C_ADC_CH0 ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Channel 0 */ +#define AT91C_ADC_CH1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Channel 1 */ +#define AT91C_ADC_CH2 ( ( unsigned int ) 0x1 << 2 ) /* (ADC) Channel 2 */ +#define AT91C_ADC_CH3 ( ( unsigned int ) 0x1 << 3 ) /* (ADC) Channel 3 */ +#define AT91C_ADC_CH4 ( ( unsigned int ) 0x1 << 4 ) /* (ADC) Channel 4 */ +#define AT91C_ADC_CH5 ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Channel 5 */ +#define AT91C_ADC_CH6 ( ( unsigned int ) 0x1 << 6 ) /* (ADC) Channel 6 */ +#define AT91C_ADC_CH7 ( ( unsigned int ) 0x1 << 7 ) /* (ADC) Channel 7 */ +/* -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- */ +/* -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- */ +/* -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- */ +#define AT91C_ADC_EOC0 ( ( unsigned int ) 0x1 << 0 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC2 ( ( unsigned int ) 0x1 << 2 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC3 ( ( unsigned int ) 0x1 << 3 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC4 ( ( unsigned int ) 0x1 << 4 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC5 ( ( unsigned int ) 0x1 << 5 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC6 ( ( unsigned int ) 0x1 << 6 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC7 ( ( unsigned int ) 0x1 << 7 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_OVRE0 ( ( unsigned int ) 0x1 << 8 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE1 ( ( unsigned int ) 0x1 << 9 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE2 ( ( unsigned int ) 0x1 << 10 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE3 ( ( unsigned int ) 0x1 << 11 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE4 ( ( unsigned int ) 0x1 << 12 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE5 ( ( unsigned int ) 0x1 << 13 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE6 ( ( unsigned int ) 0x1 << 14 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE7 ( ( unsigned int ) 0x1 << 15 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_DRDY ( ( unsigned int ) 0x1 << 16 ) /* (ADC) Data Ready */ +#define AT91C_ADC_GOVRE ( ( unsigned int ) 0x1 << 17 ) /* (ADC) General Overrun */ +#define AT91C_ADC_ENDRX ( ( unsigned int ) 0x1 << 18 ) /* (ADC) End of Receiver Transfer */ +#define AT91C_ADC_RXBUFF ( ( unsigned int ) 0x1 << 19 ) /* (ADC) RXBUFF Interrupt */ +/* -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- */ +#define AT91C_ADC_LDATA ( ( unsigned int ) 0x3FF << 0 ) /* (ADC) Last Data Converted */ +/* -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- */ +/* -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- */ +/* -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- */ +/* -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- */ +#define AT91C_ADC_DATA ( ( unsigned int ) 0x3FF << 0 ) /* (ADC) Converted Data */ +/* -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- */ +/* -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- */ +/* -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- */ +/* -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- */ +/* -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- */ +/* -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- */ +/* -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Advanced Encryption Standard */ +/* ***************************************************************************** */ +typedef struct _AT91S_AES +{ + AT91_REG AES_CR; /* Control Register */ + AT91_REG AES_MR; /* Mode Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG AES_IER; /* Interrupt Enable Register */ + AT91_REG AES_IDR; /* Interrupt Disable Register */ + AT91_REG AES_IMR; /* Interrupt Mask Register */ + AT91_REG AES_ISR; /* Interrupt Status Register */ + AT91_REG AES_KEYWxR[ 4 ]; /* Key Word x Register */ + AT91_REG Reserved1[ 4 ]; /* */ + AT91_REG AES_IDATAxR[ 4 ]; /* Input Data x Register */ + AT91_REG AES_ODATAxR[ 4 ]; /* Output Data x Register */ + AT91_REG AES_IVxR[ 4 ]; /* Initialization Vector x Register */ + AT91_REG Reserved2[ 35 ]; /* */ + AT91_REG AES_VR; /* AES Version Register */ + AT91_REG AES_RPR; /* Receive Pointer Register */ + AT91_REG AES_RCR; /* Receive Counter Register */ + AT91_REG AES_TPR; /* Transmit Pointer Register */ + AT91_REG AES_TCR; /* Transmit Counter Register */ + AT91_REG AES_RNPR; /* Receive Next Pointer Register */ + AT91_REG AES_RNCR; /* Receive Next Counter Register */ + AT91_REG AES_TNPR; /* Transmit Next Pointer Register */ + AT91_REG AES_TNCR; /* Transmit Next Counter Register */ + AT91_REG AES_PTCR; /* PDC Transfer Control Register */ + AT91_REG AES_PTSR; /* PDC Transfer Status Register */ +} AT91S_AES, * AT91PS_AES; + +/* -------- AES_CR : (AES Offset: 0x0) Control Register -------- */ +#define AT91C_AES_START ( ( unsigned int ) 0x1 << 0 ) /* (AES) Starts Processing */ +#define AT91C_AES_SWRST ( ( unsigned int ) 0x1 << 8 ) /* (AES) Software Reset */ +#define AT91C_AES_LOADSEED ( ( unsigned int ) 0x1 << 16 ) /* (AES) Random Number Generator Seed Loading */ +/* -------- AES_MR : (AES Offset: 0x4) Mode Register -------- */ +#define AT91C_AES_CIPHER ( ( unsigned int ) 0x1 << 0 ) /* (AES) Processing Mode */ +#define AT91C_AES_PROCDLY ( ( unsigned int ) 0xF << 4 ) /* (AES) Processing Delay */ +#define AT91C_AES_SMOD ( ( unsigned int ) 0x3 << 8 ) /* (AES) Start Mode */ +#define AT91C_AES_SMOD_MANUAL ( ( unsigned int ) 0x0 << 8 ) /* (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. */ +#define AT91C_AES_SMOD_AUTO ( ( unsigned int ) 0x1 << 8 ) /* (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). */ +#define AT91C_AES_SMOD_PDC ( ( unsigned int ) 0x2 << 8 ) /* (AES) PDC Mode (cf datasheet). */ +#define AT91C_AES_OPMOD ( ( unsigned int ) 0x7 << 12 ) /* (AES) Operation Mode */ +#define AT91C_AES_OPMOD_ECB ( ( unsigned int ) 0x0 << 12 ) /* (AES) ECB Electronic CodeBook mode. */ +#define AT91C_AES_OPMOD_CBC ( ( unsigned int ) 0x1 << 12 ) /* (AES) CBC Cipher Block Chaining mode. */ +#define AT91C_AES_OPMOD_OFB ( ( unsigned int ) 0x2 << 12 ) /* (AES) OFB Output Feedback mode. */ +#define AT91C_AES_OPMOD_CFB ( ( unsigned int ) 0x3 << 12 ) /* (AES) CFB Cipher Feedback mode. */ +#define AT91C_AES_OPMOD_CTR ( ( unsigned int ) 0x4 << 12 ) /* (AES) CTR Counter mode. */ +#define AT91C_AES_LOD ( ( unsigned int ) 0x1 << 15 ) /* (AES) Last Output Data Mode */ +#define AT91C_AES_CFBS ( ( unsigned int ) 0x7 << 16 ) /* (AES) Cipher Feedback Data Size */ +#define AT91C_AES_CFBS_128_BIT ( ( unsigned int ) 0x0 << 16 ) /* (AES) 128-bit. */ +#define AT91C_AES_CFBS_64_BIT ( ( unsigned int ) 0x1 << 16 ) /* (AES) 64-bit. */ +#define AT91C_AES_CFBS_32_BIT ( ( unsigned int ) 0x2 << 16 ) /* (AES) 32-bit. */ +#define AT91C_AES_CFBS_16_BIT ( ( unsigned int ) 0x3 << 16 ) /* (AES) 16-bit. */ +#define AT91C_AES_CFBS_8_BIT ( ( unsigned int ) 0x4 << 16 ) /* (AES) 8-bit. */ +#define AT91C_AES_CKEY ( ( unsigned int ) 0xF << 20 ) /* (AES) Countermeasure Key */ +#define AT91C_AES_CTYPE ( ( unsigned int ) 0x1F << 24 ) /* (AES) Countermeasure Type */ +#define AT91C_AES_CTYPE_TYPE1_EN ( ( unsigned int ) 0x1 << 24 ) /* (AES) Countermeasure type 1 is enabled. */ +#define AT91C_AES_CTYPE_TYPE2_EN ( ( unsigned int ) 0x2 << 24 ) /* (AES) Countermeasure type 2 is enabled. */ +#define AT91C_AES_CTYPE_TYPE3_EN ( ( unsigned int ) 0x4 << 24 ) /* (AES) Countermeasure type 3 is enabled. */ +#define AT91C_AES_CTYPE_TYPE4_EN ( ( unsigned int ) 0x8 << 24 ) /* (AES) Countermeasure type 4 is enabled. */ +#define AT91C_AES_CTYPE_TYPE5_EN ( ( unsigned int ) 0x10 << 24 ) /* (AES) Countermeasure type 5 is enabled. */ +/* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */ +#define AT91C_AES_DATRDY ( ( unsigned int ) 0x1 << 0 ) /* (AES) DATRDY */ +#define AT91C_AES_ENDRX ( ( unsigned int ) 0x1 << 1 ) /* (AES) PDC Read Buffer End */ +#define AT91C_AES_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (AES) PDC Write Buffer End */ +#define AT91C_AES_RXBUFF ( ( unsigned int ) 0x1 << 3 ) /* (AES) PDC Read Buffer Full */ +#define AT91C_AES_TXBUFE ( ( unsigned int ) 0x1 << 4 ) /* (AES) PDC Write Buffer Empty */ +#define AT91C_AES_URAD ( ( unsigned int ) 0x1 << 8 ) /* (AES) Unspecified Register Access Detection */ +/* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */ +/* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */ +/* -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- */ +#define AT91C_AES_URAT ( ( unsigned int ) 0x7 << 12 ) /* (AES) Unspecified Register Access Type Status */ +#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ( ( unsigned int ) 0x0 << 12 ) /* (AES) Input data register written during the data processing in PDC mode. */ +#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ( ( unsigned int ) 0x1 << 12 ) /* (AES) Output data register read during the data processing. */ +#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ( ( unsigned int ) 0x2 << 12 ) /* (AES) Mode register written during the data processing. */ +#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ( ( unsigned int ) 0x3 << 12 ) /* (AES) Output data register read during the sub-keys generation. */ +#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ( ( unsigned int ) 0x4 << 12 ) /* (AES) Mode register written during the sub-keys generation. */ +#define AT91C_AES_URAT_WO_REG_READ ( ( unsigned int ) 0x5 << 12 ) /* (AES) Write-only register read access. */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Triple Data Encryption Standard */ +/* ***************************************************************************** */ +typedef struct _AT91S_TDES +{ + AT91_REG TDES_CR; /* Control Register */ + AT91_REG TDES_MR; /* Mode Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG TDES_IER; /* Interrupt Enable Register */ + AT91_REG TDES_IDR; /* Interrupt Disable Register */ + AT91_REG TDES_IMR; /* Interrupt Mask Register */ + AT91_REG TDES_ISR; /* Interrupt Status Register */ + AT91_REG TDES_KEY1WxR[ 2 ]; /* Key 1 Word x Register */ + AT91_REG TDES_KEY2WxR[ 2 ]; /* Key 2 Word x Register */ + AT91_REG TDES_KEY3WxR[ 2 ]; /* Key 3 Word x Register */ + AT91_REG Reserved1[ 2 ]; /* */ + AT91_REG TDES_IDATAxR[ 2 ]; /* Input Data x Register */ + AT91_REG Reserved2[ 2 ]; /* */ + AT91_REG TDES_ODATAxR[ 2 ]; /* Output Data x Register */ + AT91_REG Reserved3[ 2 ]; /* */ + AT91_REG TDES_IVxR[ 2 ]; /* Initialization Vector x Register */ + AT91_REG Reserved4[ 37 ]; /* */ + AT91_REG TDES_VR; /* TDES Version Register */ + AT91_REG TDES_RPR; /* Receive Pointer Register */ + AT91_REG TDES_RCR; /* Receive Counter Register */ + AT91_REG TDES_TPR; /* Transmit Pointer Register */ + AT91_REG TDES_TCR; /* Transmit Counter Register */ + AT91_REG TDES_RNPR; /* Receive Next Pointer Register */ + AT91_REG TDES_RNCR; /* Receive Next Counter Register */ + AT91_REG TDES_TNPR; /* Transmit Next Pointer Register */ + AT91_REG TDES_TNCR; /* Transmit Next Counter Register */ + AT91_REG TDES_PTCR; /* PDC Transfer Control Register */ + AT91_REG TDES_PTSR; /* PDC Transfer Status Register */ +} AT91S_TDES, * AT91PS_TDES; + +/* -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- */ +#define AT91C_TDES_START ( ( unsigned int ) 0x1 << 0 ) /* (TDES) Starts Processing */ +#define AT91C_TDES_SWRST ( ( unsigned int ) 0x1 << 8 ) /* (TDES) Software Reset */ +/* -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- */ +#define AT91C_TDES_CIPHER ( ( unsigned int ) 0x1 << 0 ) /* (TDES) Processing Mode */ +#define AT91C_TDES_TDESMOD ( ( unsigned int ) 0x1 << 1 ) /* (TDES) Single or Triple DES Mode */ +#define AT91C_TDES_KEYMOD ( ( unsigned int ) 0x1 << 4 ) /* (TDES) Key Mode */ +#define AT91C_TDES_SMOD ( ( unsigned int ) 0x3 << 8 ) /* (TDES) Start Mode */ +#define AT91C_TDES_SMOD_MANUAL ( ( unsigned int ) 0x0 << 8 ) /* (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. */ +#define AT91C_TDES_SMOD_AUTO ( ( unsigned int ) 0x1 << 8 ) /* (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). */ +#define AT91C_TDES_SMOD_PDC ( ( unsigned int ) 0x2 << 8 ) /* (TDES) PDC Mode (cf datasheet). */ +#define AT91C_TDES_OPMOD ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Operation Mode */ +#define AT91C_TDES_OPMOD_ECB ( ( unsigned int ) 0x0 << 12 ) /* (TDES) ECB Electronic CodeBook mode. */ +#define AT91C_TDES_OPMOD_CBC ( ( unsigned int ) 0x1 << 12 ) /* (TDES) CBC Cipher Block Chaining mode. */ +#define AT91C_TDES_OPMOD_OFB ( ( unsigned int ) 0x2 << 12 ) /* (TDES) OFB Output Feedback mode. */ +#define AT91C_TDES_OPMOD_CFB ( ( unsigned int ) 0x3 << 12 ) /* (TDES) CFB Cipher Feedback mode. */ +#define AT91C_TDES_LOD ( ( unsigned int ) 0x1 << 15 ) /* (TDES) Last Output Data Mode */ +#define AT91C_TDES_CFBS ( ( unsigned int ) 0x3 << 16 ) /* (TDES) Cipher Feedback Data Size */ +#define AT91C_TDES_CFBS_64_BIT ( ( unsigned int ) 0x0 << 16 ) /* (TDES) 64-bit. */ +#define AT91C_TDES_CFBS_32_BIT ( ( unsigned int ) 0x1 << 16 ) /* (TDES) 32-bit. */ +#define AT91C_TDES_CFBS_16_BIT ( ( unsigned int ) 0x2 << 16 ) /* (TDES) 16-bit. */ +#define AT91C_TDES_CFBS_8_BIT ( ( unsigned int ) 0x3 << 16 ) /* (TDES) 8-bit. */ +/* -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- */ +#define AT91C_TDES_DATRDY ( ( unsigned int ) 0x1 << 0 ) /* (TDES) DATRDY */ +#define AT91C_TDES_ENDRX ( ( unsigned int ) 0x1 << 1 ) /* (TDES) PDC Read Buffer End */ +#define AT91C_TDES_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (TDES) PDC Write Buffer End */ +#define AT91C_TDES_RXBUFF ( ( unsigned int ) 0x1 << 3 ) /* (TDES) PDC Read Buffer Full */ +#define AT91C_TDES_TXBUFE ( ( unsigned int ) 0x1 << 4 ) /* (TDES) PDC Write Buffer Empty */ +#define AT91C_TDES_URAD ( ( unsigned int ) 0x1 << 8 ) /* (TDES) Unspecified Register Access Detection */ +/* -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- */ +/* -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- */ +/* -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- */ +#define AT91C_TDES_URAT ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Unspecified Register Access Type Status */ +#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ( ( unsigned int ) 0x0 << 12 ) /* (TDES) Input data register written during the data processing in PDC mode. */ +#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ( ( unsigned int ) 0x1 << 12 ) /* (TDES) Output data register read during the data processing. */ +#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ( ( unsigned int ) 0x2 << 12 ) /* (TDES) Mode register written during the data processing. */ +#define AT91C_TDES_URAT_WO_REG_READ ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Write-only register read access. */ + +/* ***************************************************************************** */ +/* REGISTER ADDRESS DEFINITION FOR AT91SAM7X128 */ +/* ***************************************************************************** */ +/* ========== Register definition for SYS peripheral ========== */ +/* ========== Register definition for AIC peripheral ========== */ +#define AT91C_AIC_IVR ( ( AT91_REG * ) 0xFFFFF100 ) /* (AIC) IRQ Vector Register */ +#define AT91C_AIC_SMR ( ( AT91_REG * ) 0xFFFFF000 ) /* (AIC) Source Mode Register */ +#define AT91C_AIC_FVR ( ( AT91_REG * ) 0xFFFFF104 ) /* (AIC) FIQ Vector Register */ +#define AT91C_AIC_DCR ( ( AT91_REG * ) 0xFFFFF138 ) /* (AIC) Debug Control Register (Protect) */ +#define AT91C_AIC_EOICR ( ( AT91_REG * ) 0xFFFFF130 ) /* (AIC) End of Interrupt Command Register */ +#define AT91C_AIC_SVR ( ( AT91_REG * ) 0xFFFFF080 ) /* (AIC) Source Vector Register */ +#define AT91C_AIC_FFSR ( ( AT91_REG * ) 0xFFFFF148 ) /* (AIC) Fast Forcing Status Register */ +#define AT91C_AIC_ICCR ( ( AT91_REG * ) 0xFFFFF128 ) /* (AIC) Interrupt Clear Command Register */ +#define AT91C_AIC_ISR ( ( AT91_REG * ) 0xFFFFF108 ) /* (AIC) Interrupt Status Register */ +#define AT91C_AIC_IMR ( ( AT91_REG * ) 0xFFFFF110 ) /* (AIC) Interrupt Mask Register */ +#define AT91C_AIC_IPR ( ( AT91_REG * ) 0xFFFFF10C ) /* (AIC) Interrupt Pending Register */ +#define AT91C_AIC_FFER ( ( AT91_REG * ) 0xFFFFF140 ) /* (AIC) Fast Forcing Enable Register */ +#define AT91C_AIC_IECR ( ( AT91_REG * ) 0xFFFFF120 ) /* (AIC) Interrupt Enable Command Register */ +#define AT91C_AIC_ISCR ( ( AT91_REG * ) 0xFFFFF12C ) /* (AIC) Interrupt Set Command Register */ +#define AT91C_AIC_FFDR ( ( AT91_REG * ) 0xFFFFF144 ) /* (AIC) Fast Forcing Disable Register */ +#define AT91C_AIC_CISR ( ( AT91_REG * ) 0xFFFFF114 ) /* (AIC) Core Interrupt Status Register */ +#define AT91C_AIC_IDCR ( ( AT91_REG * ) 0xFFFFF124 ) /* (AIC) Interrupt Disable Command Register */ +#define AT91C_AIC_SPU ( ( AT91_REG * ) 0xFFFFF134 ) /* (AIC) Spurious Vector Register */ +/* ========== Register definition for PDC_DBGU peripheral ========== */ +#define AT91C_DBGU_TCR ( ( AT91_REG * ) 0xFFFFF30C ) /* (PDC_DBGU) Transmit Counter Register */ +#define AT91C_DBGU_RNPR ( ( AT91_REG * ) 0xFFFFF310 ) /* (PDC_DBGU) Receive Next Pointer Register */ +#define AT91C_DBGU_TNPR ( ( AT91_REG * ) 0xFFFFF318 ) /* (PDC_DBGU) Transmit Next Pointer Register */ +#define AT91C_DBGU_TPR ( ( AT91_REG * ) 0xFFFFF308 ) /* (PDC_DBGU) Transmit Pointer Register */ +#define AT91C_DBGU_RPR ( ( AT91_REG * ) 0xFFFFF300 ) /* (PDC_DBGU) Receive Pointer Register */ +#define AT91C_DBGU_RCR ( ( AT91_REG * ) 0xFFFFF304 ) /* (PDC_DBGU) Receive Counter Register */ +#define AT91C_DBGU_RNCR ( ( AT91_REG * ) 0xFFFFF314 ) /* (PDC_DBGU) Receive Next Counter Register */ +#define AT91C_DBGU_PTCR ( ( AT91_REG * ) 0xFFFFF320 ) /* (PDC_DBGU) PDC Transfer Control Register */ +#define AT91C_DBGU_PTSR ( ( AT91_REG * ) 0xFFFFF324 ) /* (PDC_DBGU) PDC Transfer Status Register */ +#define AT91C_DBGU_TNCR ( ( AT91_REG * ) 0xFFFFF31C ) /* (PDC_DBGU) Transmit Next Counter Register */ +/* ========== Register definition for DBGU peripheral ========== */ +#define AT91C_DBGU_EXID ( ( AT91_REG * ) 0xFFFFF244 ) /* (DBGU) Chip ID Extension Register */ +#define AT91C_DBGU_BRGR ( ( AT91_REG * ) 0xFFFFF220 ) /* (DBGU) Baud Rate Generator Register */ +#define AT91C_DBGU_IDR ( ( AT91_REG * ) 0xFFFFF20C ) /* (DBGU) Interrupt Disable Register */ +#define AT91C_DBGU_CSR ( ( AT91_REG * ) 0xFFFFF214 ) /* (DBGU) Channel Status Register */ +#define AT91C_DBGU_CIDR ( ( AT91_REG * ) 0xFFFFF240 ) /* (DBGU) Chip ID Register */ +#define AT91C_DBGU_MR ( ( AT91_REG * ) 0xFFFFF204 ) /* (DBGU) Mode Register */ +#define AT91C_DBGU_IMR ( ( AT91_REG * ) 0xFFFFF210 ) /* (DBGU) Interrupt Mask Register */ +#define AT91C_DBGU_CR ( ( AT91_REG * ) 0xFFFFF200 ) /* (DBGU) Control Register */ +#define AT91C_DBGU_FNTR ( ( AT91_REG * ) 0xFFFFF248 ) /* (DBGU) Force NTRST Register */ +#define AT91C_DBGU_THR ( ( AT91_REG * ) 0xFFFFF21C ) /* (DBGU) Transmitter Holding Register */ +#define AT91C_DBGU_RHR ( ( AT91_REG * ) 0xFFFFF218 ) /* (DBGU) Receiver Holding Register */ +#define AT91C_DBGU_IER ( ( AT91_REG * ) 0xFFFFF208 ) /* (DBGU) Interrupt Enable Register */ +/* ========== Register definition for PIOA peripheral ========== */ +#define AT91C_PIOA_ODR ( ( AT91_REG * ) 0xFFFFF414 ) /* (PIOA) Output Disable Registerr */ +#define AT91C_PIOA_SODR ( ( AT91_REG * ) 0xFFFFF430 ) /* (PIOA) Set Output Data Register */ +#define AT91C_PIOA_ISR ( ( AT91_REG * ) 0xFFFFF44C ) /* (PIOA) Interrupt Status Register */ +#define AT91C_PIOA_ABSR ( ( AT91_REG * ) 0xFFFFF478 ) /* (PIOA) AB Select Status Register */ +#define AT91C_PIOA_IER ( ( AT91_REG * ) 0xFFFFF440 ) /* (PIOA) Interrupt Enable Register */ +#define AT91C_PIOA_PPUDR ( ( AT91_REG * ) 0xFFFFF460 ) /* (PIOA) Pull-up Disable Register */ +#define AT91C_PIOA_IMR ( ( AT91_REG * ) 0xFFFFF448 ) /* (PIOA) Interrupt Mask Register */ +#define AT91C_PIOA_PER ( ( AT91_REG * ) 0xFFFFF400 ) /* (PIOA) PIO Enable Register */ +#define AT91C_PIOA_IFDR ( ( AT91_REG * ) 0xFFFFF424 ) /* (PIOA) Input Filter Disable Register */ +#define AT91C_PIOA_OWDR ( ( AT91_REG * ) 0xFFFFF4A4 ) /* (PIOA) Output Write Disable Register */ +#define AT91C_PIOA_MDSR ( ( AT91_REG * ) 0xFFFFF458 ) /* (PIOA) Multi-driver Status Register */ +#define AT91C_PIOA_IDR ( ( AT91_REG * ) 0xFFFFF444 ) /* (PIOA) Interrupt Disable Register */ +#define AT91C_PIOA_ODSR ( ( AT91_REG * ) 0xFFFFF438 ) /* (PIOA) Output Data Status Register */ +#define AT91C_PIOA_PPUSR ( ( AT91_REG * ) 0xFFFFF468 ) /* (PIOA) Pull-up Status Register */ +#define AT91C_PIOA_OWSR ( ( AT91_REG * ) 0xFFFFF4A8 ) /* (PIOA) Output Write Status Register */ +#define AT91C_PIOA_BSR ( ( AT91_REG * ) 0xFFFFF474 ) /* (PIOA) Select B Register */ +#define AT91C_PIOA_OWER ( ( AT91_REG * ) 0xFFFFF4A0 ) /* (PIOA) Output Write Enable Register */ +#define AT91C_PIOA_IFER ( ( AT91_REG * ) 0xFFFFF420 ) /* (PIOA) Input Filter Enable Register */ +#define AT91C_PIOA_PDSR ( ( AT91_REG * ) 0xFFFFF43C ) /* (PIOA) Pin Data Status Register */ +#define AT91C_PIOA_PPUER ( ( AT91_REG * ) 0xFFFFF464 ) /* (PIOA) Pull-up Enable Register */ +#define AT91C_PIOA_OSR ( ( AT91_REG * ) 0xFFFFF418 ) /* (PIOA) Output Status Register */ +#define AT91C_PIOA_ASR ( ( AT91_REG * ) 0xFFFFF470 ) /* (PIOA) Select A Register */ +#define AT91C_PIOA_MDDR ( ( AT91_REG * ) 0xFFFFF454 ) /* (PIOA) Multi-driver Disable Register */ +#define AT91C_PIOA_CODR ( ( AT91_REG * ) 0xFFFFF434 ) /* (PIOA) Clear Output Data Register */ +#define AT91C_PIOA_MDER ( ( AT91_REG * ) 0xFFFFF450 ) /* (PIOA) Multi-driver Enable Register */ +#define AT91C_PIOA_PDR ( ( AT91_REG * ) 0xFFFFF404 ) /* (PIOA) PIO Disable Register */ +#define AT91C_PIOA_IFSR ( ( AT91_REG * ) 0xFFFFF428 ) /* (PIOA) Input Filter Status Register */ +#define AT91C_PIOA_OER ( ( AT91_REG * ) 0xFFFFF410 ) /* (PIOA) Output Enable Register */ +#define AT91C_PIOA_PSR ( ( AT91_REG * ) 0xFFFFF408 ) /* (PIOA) PIO Status Register */ +/* ========== Register definition for PIOB peripheral ========== */ +#define AT91C_PIOB_OWDR ( ( AT91_REG * ) 0xFFFFF6A4 ) /* (PIOB) Output Write Disable Register */ +#define AT91C_PIOB_MDER ( ( AT91_REG * ) 0xFFFFF650 ) /* (PIOB) Multi-driver Enable Register */ +#define AT91C_PIOB_PPUSR ( ( AT91_REG * ) 0xFFFFF668 ) /* (PIOB) Pull-up Status Register */ +#define AT91C_PIOB_IMR ( ( AT91_REG * ) 0xFFFFF648 ) /* (PIOB) Interrupt Mask Register */ +#define AT91C_PIOB_ASR ( ( AT91_REG * ) 0xFFFFF670 ) /* (PIOB) Select A Register */ +#define AT91C_PIOB_PPUDR ( ( AT91_REG * ) 0xFFFFF660 ) /* (PIOB) Pull-up Disable Register */ +#define AT91C_PIOB_PSR ( ( AT91_REG * ) 0xFFFFF608 ) /* (PIOB) PIO Status Register */ +#define AT91C_PIOB_IER ( ( AT91_REG * ) 0xFFFFF640 ) /* (PIOB) Interrupt Enable Register */ +#define AT91C_PIOB_CODR ( ( AT91_REG * ) 0xFFFFF634 ) /* (PIOB) Clear Output Data Register */ +#define AT91C_PIOB_OWER ( ( AT91_REG * ) 0xFFFFF6A0 ) /* (PIOB) Output Write Enable Register */ +#define AT91C_PIOB_ABSR ( ( AT91_REG * ) 0xFFFFF678 ) /* (PIOB) AB Select Status Register */ +#define AT91C_PIOB_IFDR ( ( AT91_REG * ) 0xFFFFF624 ) /* (PIOB) Input Filter Disable Register */ +#define AT91C_PIOB_PDSR ( ( AT91_REG * ) 0xFFFFF63C ) /* (PIOB) Pin Data Status Register */ +#define AT91C_PIOB_IDR ( ( AT91_REG * ) 0xFFFFF644 ) /* (PIOB) Interrupt Disable Register */ +#define AT91C_PIOB_OWSR ( ( AT91_REG * ) 0xFFFFF6A8 ) /* (PIOB) Output Write Status Register */ +#define AT91C_PIOB_PDR ( ( AT91_REG * ) 0xFFFFF604 ) /* (PIOB) PIO Disable Register */ +#define AT91C_PIOB_ODR ( ( AT91_REG * ) 0xFFFFF614 ) /* (PIOB) Output Disable Registerr */ +#define AT91C_PIOB_IFSR ( ( AT91_REG * ) 0xFFFFF628 ) /* (PIOB) Input Filter Status Register */ +#define AT91C_PIOB_PPUER ( ( AT91_REG * ) 0xFFFFF664 ) /* (PIOB) Pull-up Enable Register */ +#define AT91C_PIOB_SODR ( ( AT91_REG * ) 0xFFFFF630 ) /* (PIOB) Set Output Data Register */ +#define AT91C_PIOB_ISR ( ( AT91_REG * ) 0xFFFFF64C ) /* (PIOB) Interrupt Status Register */ +#define AT91C_PIOB_ODSR ( ( AT91_REG * ) 0xFFFFF638 ) /* (PIOB) Output Data Status Register */ +#define AT91C_PIOB_OSR ( ( AT91_REG * ) 0xFFFFF618 ) /* (PIOB) Output Status Register */ +#define AT91C_PIOB_MDSR ( ( AT91_REG * ) 0xFFFFF658 ) /* (PIOB) Multi-driver Status Register */ +#define AT91C_PIOB_IFER ( ( AT91_REG * ) 0xFFFFF620 ) /* (PIOB) Input Filter Enable Register */ +#define AT91C_PIOB_BSR ( ( AT91_REG * ) 0xFFFFF674 ) /* (PIOB) Select B Register */ +#define AT91C_PIOB_MDDR ( ( AT91_REG * ) 0xFFFFF654 ) /* (PIOB) Multi-driver Disable Register */ +#define AT91C_PIOB_OER ( ( AT91_REG * ) 0xFFFFF610 ) /* (PIOB) Output Enable Register */ +#define AT91C_PIOB_PER ( ( AT91_REG * ) 0xFFFFF600 ) /* (PIOB) PIO Enable Register */ +/* ========== Register definition for CKGR peripheral ========== */ +#define AT91C_CKGR_MOR ( ( AT91_REG * ) 0xFFFFFC20 ) /* (CKGR) Main Oscillator Register */ +#define AT91C_CKGR_PLLR ( ( AT91_REG * ) 0xFFFFFC2C ) /* (CKGR) PLL Register */ +#define AT91C_CKGR_MCFR ( ( AT91_REG * ) 0xFFFFFC24 ) /* (CKGR) Main Clock Frequency Register */ +/* ========== Register definition for PMC peripheral ========== */ +#define AT91C_PMC_IDR ( ( AT91_REG * ) 0xFFFFFC64 ) /* (PMC) Interrupt Disable Register */ +#define AT91C_PMC_MOR ( ( AT91_REG * ) 0xFFFFFC20 ) /* (PMC) Main Oscillator Register */ +#define AT91C_PMC_PLLR ( ( AT91_REG * ) 0xFFFFFC2C ) /* (PMC) PLL Register */ +#define AT91C_PMC_PCER ( ( AT91_REG * ) 0xFFFFFC10 ) /* (PMC) Peripheral Clock Enable Register */ +#define AT91C_PMC_PCKR ( ( AT91_REG * ) 0xFFFFFC40 ) /* (PMC) Programmable Clock Register */ +#define AT91C_PMC_MCKR ( ( AT91_REG * ) 0xFFFFFC30 ) /* (PMC) Master Clock Register */ +#define AT91C_PMC_SCDR ( ( AT91_REG * ) 0xFFFFFC04 ) /* (PMC) System Clock Disable Register */ +#define AT91C_PMC_PCDR ( ( AT91_REG * ) 0xFFFFFC14 ) /* (PMC) Peripheral Clock Disable Register */ +#define AT91C_PMC_SCSR ( ( AT91_REG * ) 0xFFFFFC08 ) /* (PMC) System Clock Status Register */ +#define AT91C_PMC_PCSR ( ( AT91_REG * ) 0xFFFFFC18 ) /* (PMC) Peripheral Clock Status Register */ +#define AT91C_PMC_MCFR ( ( AT91_REG * ) 0xFFFFFC24 ) /* (PMC) Main Clock Frequency Register */ +#define AT91C_PMC_SCER ( ( AT91_REG * ) 0xFFFFFC00 ) /* (PMC) System Clock Enable Register */ +#define AT91C_PMC_IMR ( ( AT91_REG * ) 0xFFFFFC6C ) /* (PMC) Interrupt Mask Register */ +#define AT91C_PMC_IER ( ( AT91_REG * ) 0xFFFFFC60 ) /* (PMC) Interrupt Enable Register */ +#define AT91C_PMC_SR ( ( AT91_REG * ) 0xFFFFFC68 ) /* (PMC) Status Register */ +/* ========== Register definition for RSTC peripheral ========== */ +#define AT91C_RSTC_RCR ( ( AT91_REG * ) 0xFFFFFD00 ) /* (RSTC) Reset Control Register */ +#define AT91C_RSTC_RMR ( ( AT91_REG * ) 0xFFFFFD08 ) /* (RSTC) Reset Mode Register */ +#define AT91C_RSTC_RSR ( ( AT91_REG * ) 0xFFFFFD04 ) /* (RSTC) Reset Status Register */ +/* ========== Register definition for RTTC peripheral ========== */ +#define AT91C_RTTC_RTSR ( ( AT91_REG * ) 0xFFFFFD2C ) /* (RTTC) Real-time Status Register */ +#define AT91C_RTTC_RTMR ( ( AT91_REG * ) 0xFFFFFD20 ) /* (RTTC) Real-time Mode Register */ +#define AT91C_RTTC_RTVR ( ( AT91_REG * ) 0xFFFFFD28 ) /* (RTTC) Real-time Value Register */ +#define AT91C_RTTC_RTAR ( ( AT91_REG * ) 0xFFFFFD24 ) /* (RTTC) Real-time Alarm Register */ +/* ========== Register definition for PITC peripheral ========== */ +#define AT91C_PITC_PIVR ( ( AT91_REG * ) 0xFFFFFD38 ) /* (PITC) Period Interval Value Register */ +#define AT91C_PITC_PISR ( ( AT91_REG * ) 0xFFFFFD34 ) /* (PITC) Period Interval Status Register */ +#define AT91C_PITC_PIIR ( ( AT91_REG * ) 0xFFFFFD3C ) /* (PITC) Period Interval Image Register */ +#define AT91C_PITC_PIMR ( ( AT91_REG * ) 0xFFFFFD30 ) /* (PITC) Period Interval Mode Register */ +/* ========== Register definition for WDTC peripheral ========== */ +#define AT91C_WDTC_WDCR ( ( AT91_REG * ) 0xFFFFFD40 ) /* (WDTC) Watchdog Control Register */ +#define AT91C_WDTC_WDSR ( ( AT91_REG * ) 0xFFFFFD48 ) /* (WDTC) Watchdog Status Register */ +#define AT91C_WDTC_WDMR ( ( AT91_REG * ) 0xFFFFFD44 ) /* (WDTC) Watchdog Mode Register */ +/* ========== Register definition for VREG peripheral ========== */ +#define AT91C_VREG_MR ( ( AT91_REG * ) 0xFFFFFD60 ) /* (VREG) Voltage Regulator Mode Register */ +/* ========== Register definition for MC peripheral ========== */ +#define AT91C_MC_ASR ( ( AT91_REG * ) 0xFFFFFF04 ) /* (MC) MC Abort Status Register */ +#define AT91C_MC_RCR ( ( AT91_REG * ) 0xFFFFFF00 ) /* (MC) MC Remap Control Register */ +#define AT91C_MC_FCR ( ( AT91_REG * ) 0xFFFFFF64 ) /* (MC) MC Flash Command Register */ +#define AT91C_MC_AASR ( ( AT91_REG * ) 0xFFFFFF08 ) /* (MC) MC Abort Address Status Register */ +#define AT91C_MC_FSR ( ( AT91_REG * ) 0xFFFFFF68 ) /* (MC) MC Flash Status Register */ +#define AT91C_MC_FMR ( ( AT91_REG * ) 0xFFFFFF60 ) /* (MC) MC Flash Mode Register */ +/* ========== Register definition for PDC_SPI1 peripheral ========== */ +#define AT91C_SPI1_PTCR ( ( AT91_REG * ) 0xFFFE4120 ) /* (PDC_SPI1) PDC Transfer Control Register */ +#define AT91C_SPI1_RPR ( ( AT91_REG * ) 0xFFFE4100 ) /* (PDC_SPI1) Receive Pointer Register */ +#define AT91C_SPI1_TNCR ( ( AT91_REG * ) 0xFFFE411C ) /* (PDC_SPI1) Transmit Next Counter Register */ +#define AT91C_SPI1_TPR ( ( AT91_REG * ) 0xFFFE4108 ) /* (PDC_SPI1) Transmit Pointer Register */ +#define AT91C_SPI1_TNPR ( ( AT91_REG * ) 0xFFFE4118 ) /* (PDC_SPI1) Transmit Next Pointer Register */ +#define AT91C_SPI1_TCR ( ( AT91_REG * ) 0xFFFE410C ) /* (PDC_SPI1) Transmit Counter Register */ +#define AT91C_SPI1_RCR ( ( AT91_REG * ) 0xFFFE4104 ) /* (PDC_SPI1) Receive Counter Register */ +#define AT91C_SPI1_RNPR ( ( AT91_REG * ) 0xFFFE4110 ) /* (PDC_SPI1) Receive Next Pointer Register */ +#define AT91C_SPI1_RNCR ( ( AT91_REG * ) 0xFFFE4114 ) /* (PDC_SPI1) Receive Next Counter Register */ +#define AT91C_SPI1_PTSR ( ( AT91_REG * ) 0xFFFE4124 ) /* (PDC_SPI1) PDC Transfer Status Register */ +/* ========== Register definition for SPI1 peripheral ========== */ +#define AT91C_SPI1_IMR ( ( AT91_REG * ) 0xFFFE401C ) /* (SPI1) Interrupt Mask Register */ +#define AT91C_SPI1_IER ( ( AT91_REG * ) 0xFFFE4014 ) /* (SPI1) Interrupt Enable Register */ +#define AT91C_SPI1_MR ( ( AT91_REG * ) 0xFFFE4004 ) /* (SPI1) Mode Register */ +#define AT91C_SPI1_RDR ( ( AT91_REG * ) 0xFFFE4008 ) /* (SPI1) Receive Data Register */ +#define AT91C_SPI1_IDR ( ( AT91_REG * ) 0xFFFE4018 ) /* (SPI1) Interrupt Disable Register */ +#define AT91C_SPI1_SR ( ( AT91_REG * ) 0xFFFE4010 ) /* (SPI1) Status Register */ +#define AT91C_SPI1_TDR ( ( AT91_REG * ) 0xFFFE400C ) /* (SPI1) Transmit Data Register */ +#define AT91C_SPI1_CR ( ( AT91_REG * ) 0xFFFE4000 ) /* (SPI1) Control Register */ +#define AT91C_SPI1_CSR ( ( AT91_REG * ) 0xFFFE4030 ) /* (SPI1) Chip Select Register */ +/* ========== Register definition for PDC_SPI0 peripheral ========== */ +#define AT91C_SPI0_PTCR ( ( AT91_REG * ) 0xFFFE0120 ) /* (PDC_SPI0) PDC Transfer Control Register */ +#define AT91C_SPI0_TPR ( ( AT91_REG * ) 0xFFFE0108 ) /* (PDC_SPI0) Transmit Pointer Register */ +#define AT91C_SPI0_TCR ( ( AT91_REG * ) 0xFFFE010C ) /* (PDC_SPI0) Transmit Counter Register */ +#define AT91C_SPI0_RCR ( ( AT91_REG * ) 0xFFFE0104 ) /* (PDC_SPI0) Receive Counter Register */ +#define AT91C_SPI0_PTSR ( ( AT91_REG * ) 0xFFFE0124 ) /* (PDC_SPI0) PDC Transfer Status Register */ +#define AT91C_SPI0_RNPR ( ( AT91_REG * ) 0xFFFE0110 ) /* (PDC_SPI0) Receive Next Pointer Register */ +#define AT91C_SPI0_RPR ( ( AT91_REG * ) 0xFFFE0100 ) /* (PDC_SPI0) Receive Pointer Register */ +#define AT91C_SPI0_TNCR ( ( AT91_REG * ) 0xFFFE011C ) /* (PDC_SPI0) Transmit Next Counter Register */ +#define AT91C_SPI0_RNCR ( ( AT91_REG * ) 0xFFFE0114 ) /* (PDC_SPI0) Receive Next Counter Register */ +#define AT91C_SPI0_TNPR ( ( AT91_REG * ) 0xFFFE0118 ) /* (PDC_SPI0) Transmit Next Pointer Register */ +/* ========== Register definition for SPI0 peripheral ========== */ +#define AT91C_SPI0_IER ( ( AT91_REG * ) 0xFFFE0014 ) /* (SPI0) Interrupt Enable Register */ +#define AT91C_SPI0_SR ( ( AT91_REG * ) 0xFFFE0010 ) /* (SPI0) Status Register */ +#define AT91C_SPI0_IDR ( ( AT91_REG * ) 0xFFFE0018 ) /* (SPI0) Interrupt Disable Register */ +#define AT91C_SPI0_CR ( ( AT91_REG * ) 0xFFFE0000 ) /* (SPI0) Control Register */ +#define AT91C_SPI0_MR ( ( AT91_REG * ) 0xFFFE0004 ) /* (SPI0) Mode Register */ +#define AT91C_SPI0_IMR ( ( AT91_REG * ) 0xFFFE001C ) /* (SPI0) Interrupt Mask Register */ +#define AT91C_SPI0_TDR ( ( AT91_REG * ) 0xFFFE000C ) /* (SPI0) Transmit Data Register */ +#define AT91C_SPI0_RDR ( ( AT91_REG * ) 0xFFFE0008 ) /* (SPI0) Receive Data Register */ +#define AT91C_SPI0_CSR ( ( AT91_REG * ) 0xFFFE0030 ) /* (SPI0) Chip Select Register */ +/* ========== Register definition for PDC_US1 peripheral ========== */ +#define AT91C_US1_RNCR ( ( AT91_REG * ) 0xFFFC4114 ) /* (PDC_US1) Receive Next Counter Register */ +#define AT91C_US1_PTCR ( ( AT91_REG * ) 0xFFFC4120 ) /* (PDC_US1) PDC Transfer Control Register */ +#define AT91C_US1_TCR ( ( AT91_REG * ) 0xFFFC410C ) /* (PDC_US1) Transmit Counter Register */ +#define AT91C_US1_PTSR ( ( AT91_REG * ) 0xFFFC4124 ) /* (PDC_US1) PDC Transfer Status Register */ +#define AT91C_US1_TNPR ( ( AT91_REG * ) 0xFFFC4118 ) /* (PDC_US1) Transmit Next Pointer Register */ +#define AT91C_US1_RCR ( ( AT91_REG * ) 0xFFFC4104 ) /* (PDC_US1) Receive Counter Register */ +#define AT91C_US1_RNPR ( ( AT91_REG * ) 0xFFFC4110 ) /* (PDC_US1) Receive Next Pointer Register */ +#define AT91C_US1_RPR ( ( AT91_REG * ) 0xFFFC4100 ) /* (PDC_US1) Receive Pointer Register */ +#define AT91C_US1_TNCR ( ( AT91_REG * ) 0xFFFC411C ) /* (PDC_US1) Transmit Next Counter Register */ +#define AT91C_US1_TPR ( ( AT91_REG * ) 0xFFFC4108 ) /* (PDC_US1) Transmit Pointer Register */ +/* ========== Register definition for US1 peripheral ========== */ +#define AT91C_US1_IF ( ( AT91_REG * ) 0xFFFC404C ) /* (US1) IRDA_FILTER Register */ +#define AT91C_US1_NER ( ( AT91_REG * ) 0xFFFC4044 ) /* (US1) Nb Errors Register */ +#define AT91C_US1_RTOR ( ( AT91_REG * ) 0xFFFC4024 ) /* (US1) Receiver Time-out Register */ +#define AT91C_US1_CSR ( ( AT91_REG * ) 0xFFFC4014 ) /* (US1) Channel Status Register */ +#define AT91C_US1_IDR ( ( AT91_REG * ) 0xFFFC400C ) /* (US1) Interrupt Disable Register */ +#define AT91C_US1_IER ( ( AT91_REG * ) 0xFFFC4008 ) /* (US1) Interrupt Enable Register */ +#define AT91C_US1_THR ( ( AT91_REG * ) 0xFFFC401C ) /* (US1) Transmitter Holding Register */ +#define AT91C_US1_TTGR ( ( AT91_REG * ) 0xFFFC4028 ) /* (US1) Transmitter Time-guard Register */ +#define AT91C_US1_RHR ( ( AT91_REG * ) 0xFFFC4018 ) /* (US1) Receiver Holding Register */ +#define AT91C_US1_BRGR ( ( AT91_REG * ) 0xFFFC4020 ) /* (US1) Baud Rate Generator Register */ +#define AT91C_US1_IMR ( ( AT91_REG * ) 0xFFFC4010 ) /* (US1) Interrupt Mask Register */ +#define AT91C_US1_FIDI ( ( AT91_REG * ) 0xFFFC4040 ) /* (US1) FI_DI_Ratio Register */ +#define AT91C_US1_CR ( ( AT91_REG * ) 0xFFFC4000 ) /* (US1) Control Register */ +#define AT91C_US1_MR ( ( AT91_REG * ) 0xFFFC4004 ) /* (US1) Mode Register */ +/* ========== Register definition for PDC_US0 peripheral ========== */ +#define AT91C_US0_TNPR ( ( AT91_REG * ) 0xFFFC0118 ) /* (PDC_US0) Transmit Next Pointer Register */ +#define AT91C_US0_RNPR ( ( AT91_REG * ) 0xFFFC0110 ) /* (PDC_US0) Receive Next Pointer Register */ +#define AT91C_US0_TCR ( ( AT91_REG * ) 0xFFFC010C ) /* (PDC_US0) Transmit Counter Register */ +#define AT91C_US0_PTCR ( ( AT91_REG * ) 0xFFFC0120 ) /* (PDC_US0) PDC Transfer Control Register */ +#define AT91C_US0_PTSR ( ( AT91_REG * ) 0xFFFC0124 ) /* (PDC_US0) PDC Transfer Status Register */ +#define AT91C_US0_TNCR ( ( AT91_REG * ) 0xFFFC011C ) /* (PDC_US0) Transmit Next Counter Register */ +#define AT91C_US0_TPR ( ( AT91_REG * ) 0xFFFC0108 ) /* (PDC_US0) Transmit Pointer Register */ +#define AT91C_US0_RCR ( ( AT91_REG * ) 0xFFFC0104 ) /* (PDC_US0) Receive Counter Register */ +#define AT91C_US0_RPR ( ( AT91_REG * ) 0xFFFC0100 ) /* (PDC_US0) Receive Pointer Register */ +#define AT91C_US0_RNCR ( ( AT91_REG * ) 0xFFFC0114 ) /* (PDC_US0) Receive Next Counter Register */ +/* ========== Register definition for US0 peripheral ========== */ +#define AT91C_US0_BRGR ( ( AT91_REG * ) 0xFFFC0020 ) /* (US0) Baud Rate Generator Register */ +#define AT91C_US0_NER ( ( AT91_REG * ) 0xFFFC0044 ) /* (US0) Nb Errors Register */ +#define AT91C_US0_CR ( ( AT91_REG * ) 0xFFFC0000 ) /* (US0) Control Register */ +#define AT91C_US0_IMR ( ( AT91_REG * ) 0xFFFC0010 ) /* (US0) Interrupt Mask Register */ +#define AT91C_US0_FIDI ( ( AT91_REG * ) 0xFFFC0040 ) /* (US0) FI_DI_Ratio Register */ +#define AT91C_US0_TTGR ( ( AT91_REG * ) 0xFFFC0028 ) /* (US0) Transmitter Time-guard Register */ +#define AT91C_US0_MR ( ( AT91_REG * ) 0xFFFC0004 ) /* (US0) Mode Register */ +#define AT91C_US0_RTOR ( ( AT91_REG * ) 0xFFFC0024 ) /* (US0) Receiver Time-out Register */ +#define AT91C_US0_CSR ( ( AT91_REG * ) 0xFFFC0014 ) /* (US0) Channel Status Register */ +#define AT91C_US0_RHR ( ( AT91_REG * ) 0xFFFC0018 ) /* (US0) Receiver Holding Register */ +#define AT91C_US0_IDR ( ( AT91_REG * ) 0xFFFC000C ) /* (US0) Interrupt Disable Register */ +#define AT91C_US0_THR ( ( AT91_REG * ) 0xFFFC001C ) /* (US0) Transmitter Holding Register */ +#define AT91C_US0_IF ( ( AT91_REG * ) 0xFFFC004C ) /* (US0) IRDA_FILTER Register */ +#define AT91C_US0_IER ( ( AT91_REG * ) 0xFFFC0008 ) /* (US0) Interrupt Enable Register */ +/* ========== Register definition for PDC_SSC peripheral ========== */ +#define AT91C_SSC_TNCR ( ( AT91_REG * ) 0xFFFD411C ) /* (PDC_SSC) Transmit Next Counter Register */ +#define AT91C_SSC_RPR ( ( AT91_REG * ) 0xFFFD4100 ) /* (PDC_SSC) Receive Pointer Register */ +#define AT91C_SSC_RNCR ( ( AT91_REG * ) 0xFFFD4114 ) /* (PDC_SSC) Receive Next Counter Register */ +#define AT91C_SSC_TPR ( ( AT91_REG * ) 0xFFFD4108 ) /* (PDC_SSC) Transmit Pointer Register */ +#define AT91C_SSC_PTCR ( ( AT91_REG * ) 0xFFFD4120 ) /* (PDC_SSC) PDC Transfer Control Register */ +#define AT91C_SSC_TCR ( ( AT91_REG * ) 0xFFFD410C ) /* (PDC_SSC) Transmit Counter Register */ +#define AT91C_SSC_RCR ( ( AT91_REG * ) 0xFFFD4104 ) /* (PDC_SSC) Receive Counter Register */ +#define AT91C_SSC_RNPR ( ( AT91_REG * ) 0xFFFD4110 ) /* (PDC_SSC) Receive Next Pointer Register */ +#define AT91C_SSC_TNPR ( ( AT91_REG * ) 0xFFFD4118 ) /* (PDC_SSC) Transmit Next Pointer Register */ +#define AT91C_SSC_PTSR ( ( AT91_REG * ) 0xFFFD4124 ) /* (PDC_SSC) PDC Transfer Status Register */ +/* ========== Register definition for SSC peripheral ========== */ +#define AT91C_SSC_RHR ( ( AT91_REG * ) 0xFFFD4020 ) /* (SSC) Receive Holding Register */ +#define AT91C_SSC_RSHR ( ( AT91_REG * ) 0xFFFD4030 ) /* (SSC) Receive Sync Holding Register */ +#define AT91C_SSC_TFMR ( ( AT91_REG * ) 0xFFFD401C ) /* (SSC) Transmit Frame Mode Register */ +#define AT91C_SSC_IDR ( ( AT91_REG * ) 0xFFFD4048 ) /* (SSC) Interrupt Disable Register */ +#define AT91C_SSC_THR ( ( AT91_REG * ) 0xFFFD4024 ) /* (SSC) Transmit Holding Register */ +#define AT91C_SSC_RCMR ( ( AT91_REG * ) 0xFFFD4010 ) /* (SSC) Receive Clock ModeRegister */ +#define AT91C_SSC_IER ( ( AT91_REG * ) 0xFFFD4044 ) /* (SSC) Interrupt Enable Register */ +#define AT91C_SSC_TSHR ( ( AT91_REG * ) 0xFFFD4034 ) /* (SSC) Transmit Sync Holding Register */ +#define AT91C_SSC_SR ( ( AT91_REG * ) 0xFFFD4040 ) /* (SSC) Status Register */ +#define AT91C_SSC_CMR ( ( AT91_REG * ) 0xFFFD4004 ) /* (SSC) Clock Mode Register */ +#define AT91C_SSC_TCMR ( ( AT91_REG * ) 0xFFFD4018 ) /* (SSC) Transmit Clock Mode Register */ +#define AT91C_SSC_CR ( ( AT91_REG * ) 0xFFFD4000 ) /* (SSC) Control Register */ +#define AT91C_SSC_IMR ( ( AT91_REG * ) 0xFFFD404C ) /* (SSC) Interrupt Mask Register */ +#define AT91C_SSC_RFMR ( ( AT91_REG * ) 0xFFFD4014 ) /* (SSC) Receive Frame Mode Register */ +/* ========== Register definition for TWI peripheral ========== */ +#define AT91C_TWI_IER ( ( AT91_REG * ) 0xFFFB8024 ) /* (TWI) Interrupt Enable Register */ +#define AT91C_TWI_CR ( ( AT91_REG * ) 0xFFFB8000 ) /* (TWI) Control Register */ +#define AT91C_TWI_SR ( ( AT91_REG * ) 0xFFFB8020 ) /* (TWI) Status Register */ +#define AT91C_TWI_IMR ( ( AT91_REG * ) 0xFFFB802C ) /* (TWI) Interrupt Mask Register */ +#define AT91C_TWI_THR ( ( AT91_REG * ) 0xFFFB8034 ) /* (TWI) Transmit Holding Register */ +#define AT91C_TWI_IDR ( ( AT91_REG * ) 0xFFFB8028 ) /* (TWI) Interrupt Disable Register */ +#define AT91C_TWI_IADR ( ( AT91_REG * ) 0xFFFB800C ) /* (TWI) Internal Address Register */ +#define AT91C_TWI_MMR ( ( AT91_REG * ) 0xFFFB8004 ) /* (TWI) Master Mode Register */ +#define AT91C_TWI_CWGR ( ( AT91_REG * ) 0xFFFB8010 ) /* (TWI) Clock Waveform Generator Register */ +#define AT91C_TWI_RHR ( ( AT91_REG * ) 0xFFFB8030 ) /* (TWI) Receive Holding Register */ +/* ========== Register definition for PWMC_CH3 peripheral ========== */ +#define AT91C_PWMC_CH3_CUPDR ( ( AT91_REG * ) 0xFFFCC270 ) /* (PWMC_CH3) Channel Update Register */ +#define AT91C_PWMC_CH3_Reserved ( ( AT91_REG * ) 0xFFFCC274 ) /* (PWMC_CH3) Reserved */ +#define AT91C_PWMC_CH3_CPRDR ( ( AT91_REG * ) 0xFFFCC268 ) /* (PWMC_CH3) Channel Period Register */ +#define AT91C_PWMC_CH3_CDTYR ( ( AT91_REG * ) 0xFFFCC264 ) /* (PWMC_CH3) Channel Duty Cycle Register */ +#define AT91C_PWMC_CH3_CCNTR ( ( AT91_REG * ) 0xFFFCC26C ) /* (PWMC_CH3) Channel Counter Register */ +#define AT91C_PWMC_CH3_CMR ( ( AT91_REG * ) 0xFFFCC260 ) /* (PWMC_CH3) Channel Mode Register */ +/* ========== Register definition for PWMC_CH2 peripheral ========== */ +#define AT91C_PWMC_CH2_Reserved ( ( AT91_REG * ) 0xFFFCC254 ) /* (PWMC_CH2) Reserved */ +#define AT91C_PWMC_CH2_CMR ( ( AT91_REG * ) 0xFFFCC240 ) /* (PWMC_CH2) Channel Mode Register */ +#define AT91C_PWMC_CH2_CCNTR ( ( AT91_REG * ) 0xFFFCC24C ) /* (PWMC_CH2) Channel Counter Register */ +#define AT91C_PWMC_CH2_CPRDR ( ( AT91_REG * ) 0xFFFCC248 ) /* (PWMC_CH2) Channel Period Register */ +#define AT91C_PWMC_CH2_CUPDR ( ( AT91_REG * ) 0xFFFCC250 ) /* (PWMC_CH2) Channel Update Register */ +#define AT91C_PWMC_CH2_CDTYR ( ( AT91_REG * ) 0xFFFCC244 ) /* (PWMC_CH2) Channel Duty Cycle Register */ +/* ========== Register definition for PWMC_CH1 peripheral ========== */ +#define AT91C_PWMC_CH1_Reserved ( ( AT91_REG * ) 0xFFFCC234 ) /* (PWMC_CH1) Reserved */ +#define AT91C_PWMC_CH1_CUPDR ( ( AT91_REG * ) 0xFFFCC230 ) /* (PWMC_CH1) Channel Update Register */ +#define AT91C_PWMC_CH1_CPRDR ( ( AT91_REG * ) 0xFFFCC228 ) /* (PWMC_CH1) Channel Period Register */ +#define AT91C_PWMC_CH1_CCNTR ( ( AT91_REG * ) 0xFFFCC22C ) /* (PWMC_CH1) Channel Counter Register */ +#define AT91C_PWMC_CH1_CDTYR ( ( AT91_REG * ) 0xFFFCC224 ) /* (PWMC_CH1) Channel Duty Cycle Register */ +#define AT91C_PWMC_CH1_CMR ( ( AT91_REG * ) 0xFFFCC220 ) /* (PWMC_CH1) Channel Mode Register */ +/* ========== Register definition for PWMC_CH0 peripheral ========== */ +#define AT91C_PWMC_CH0_Reserved ( ( AT91_REG * ) 0xFFFCC214 ) /* (PWMC_CH0) Reserved */ +#define AT91C_PWMC_CH0_CPRDR ( ( AT91_REG * ) 0xFFFCC208 ) /* (PWMC_CH0) Channel Period Register */ +#define AT91C_PWMC_CH0_CDTYR ( ( AT91_REG * ) 0xFFFCC204 ) /* (PWMC_CH0) Channel Duty Cycle Register */ +#define AT91C_PWMC_CH0_CMR ( ( AT91_REG * ) 0xFFFCC200 ) /* (PWMC_CH0) Channel Mode Register */ +#define AT91C_PWMC_CH0_CUPDR ( ( AT91_REG * ) 0xFFFCC210 ) /* (PWMC_CH0) Channel Update Register */ +#define AT91C_PWMC_CH0_CCNTR ( ( AT91_REG * ) 0xFFFCC20C ) /* (PWMC_CH0) Channel Counter Register */ +/* ========== Register definition for PWMC peripheral ========== */ +#define AT91C_PWMC_IDR ( ( AT91_REG * ) 0xFFFCC014 ) /* (PWMC) PWMC Interrupt Disable Register */ +#define AT91C_PWMC_DIS ( ( AT91_REG * ) 0xFFFCC008 ) /* (PWMC) PWMC Disable Register */ +#define AT91C_PWMC_IER ( ( AT91_REG * ) 0xFFFCC010 ) /* (PWMC) PWMC Interrupt Enable Register */ +#define AT91C_PWMC_VR ( ( AT91_REG * ) 0xFFFCC0FC ) /* (PWMC) PWMC Version Register */ +#define AT91C_PWMC_ISR ( ( AT91_REG * ) 0xFFFCC01C ) /* (PWMC) PWMC Interrupt Status Register */ +#define AT91C_PWMC_SR ( ( AT91_REG * ) 0xFFFCC00C ) /* (PWMC) PWMC Status Register */ +#define AT91C_PWMC_IMR ( ( AT91_REG * ) 0xFFFCC018 ) /* (PWMC) PWMC Interrupt Mask Register */ +#define AT91C_PWMC_MR ( ( AT91_REG * ) 0xFFFCC000 ) /* (PWMC) PWMC Mode Register */ +#define AT91C_PWMC_ENA ( ( AT91_REG * ) 0xFFFCC004 ) /* (PWMC) PWMC Enable Register */ +/* ========== Register definition for UDP peripheral ========== */ +#define AT91C_UDP_IMR ( ( AT91_REG * ) 0xFFFB0018 ) /* (UDP) Interrupt Mask Register */ +#define AT91C_UDP_FADDR ( ( AT91_REG * ) 0xFFFB0008 ) /* (UDP) Function Address Register */ +#define AT91C_UDP_NUM ( ( AT91_REG * ) 0xFFFB0000 ) /* (UDP) Frame Number Register */ +#define AT91C_UDP_FDR ( ( AT91_REG * ) 0xFFFB0050 ) /* (UDP) Endpoint FIFO Data Register */ +#define AT91C_UDP_ISR ( ( AT91_REG * ) 0xFFFB001C ) /* (UDP) Interrupt Status Register */ +#define AT91C_UDP_CSR ( ( AT91_REG * ) 0xFFFB0030 ) /* (UDP) Endpoint Control and Status Register */ +#define AT91C_UDP_IDR ( ( AT91_REG * ) 0xFFFB0014 ) /* (UDP) Interrupt Disable Register */ +#define AT91C_UDP_ICR ( ( AT91_REG * ) 0xFFFB0020 ) /* (UDP) Interrupt Clear Register */ +#define AT91C_UDP_RSTEP ( ( AT91_REG * ) 0xFFFB0028 ) /* (UDP) Reset Endpoint Register */ +#define AT91C_UDP_TXVC ( ( AT91_REG * ) 0xFFFB0074 ) /* (UDP) Transceiver Control Register */ +#define AT91C_UDP_GLBSTATE ( ( AT91_REG * ) 0xFFFB0004 ) /* (UDP) Global State Register */ +#define AT91C_UDP_IER ( ( AT91_REG * ) 0xFFFB0010 ) /* (UDP) Interrupt Enable Register */ +/* ========== Register definition for TC0 peripheral ========== */ +#define AT91C_TC0_SR ( ( AT91_REG * ) 0xFFFA0020 ) /* (TC0) Status Register */ +#define AT91C_TC0_RC ( ( AT91_REG * ) 0xFFFA001C ) /* (TC0) Register C */ +#define AT91C_TC0_RB ( ( AT91_REG * ) 0xFFFA0018 ) /* (TC0) Register B */ +#define AT91C_TC0_CCR ( ( AT91_REG * ) 0xFFFA0000 ) /* (TC0) Channel Control Register */ +#define AT91C_TC0_CMR ( ( AT91_REG * ) 0xFFFA0004 ) /* (TC0) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC0_IER ( ( AT91_REG * ) 0xFFFA0024 ) /* (TC0) Interrupt Enable Register */ +#define AT91C_TC0_RA ( ( AT91_REG * ) 0xFFFA0014 ) /* (TC0) Register A */ +#define AT91C_TC0_IDR ( ( AT91_REG * ) 0xFFFA0028 ) /* (TC0) Interrupt Disable Register */ +#define AT91C_TC0_CV ( ( AT91_REG * ) 0xFFFA0010 ) /* (TC0) Counter Value */ +#define AT91C_TC0_IMR ( ( AT91_REG * ) 0xFFFA002C ) /* (TC0) Interrupt Mask Register */ +/* ========== Register definition for TC1 peripheral ========== */ +#define AT91C_TC1_RB ( ( AT91_REG * ) 0xFFFA0058 ) /* (TC1) Register B */ +#define AT91C_TC1_CCR ( ( AT91_REG * ) 0xFFFA0040 ) /* (TC1) Channel Control Register */ +#define AT91C_TC1_IER ( ( AT91_REG * ) 0xFFFA0064 ) /* (TC1) Interrupt Enable Register */ +#define AT91C_TC1_IDR ( ( AT91_REG * ) 0xFFFA0068 ) /* (TC1) Interrupt Disable Register */ +#define AT91C_TC1_SR ( ( AT91_REG * ) 0xFFFA0060 ) /* (TC1) Status Register */ +#define AT91C_TC1_CMR ( ( AT91_REG * ) 0xFFFA0044 ) /* (TC1) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC1_RA ( ( AT91_REG * ) 0xFFFA0054 ) /* (TC1) Register A */ +#define AT91C_TC1_RC ( ( AT91_REG * ) 0xFFFA005C ) /* (TC1) Register C */ +#define AT91C_TC1_IMR ( ( AT91_REG * ) 0xFFFA006C ) /* (TC1) Interrupt Mask Register */ +#define AT91C_TC1_CV ( ( AT91_REG * ) 0xFFFA0050 ) /* (TC1) Counter Value */ +/* ========== Register definition for TC2 peripheral ========== */ +#define AT91C_TC2_CMR ( ( AT91_REG * ) 0xFFFA0084 ) /* (TC2) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC2_CCR ( ( AT91_REG * ) 0xFFFA0080 ) /* (TC2) Channel Control Register */ +#define AT91C_TC2_CV ( ( AT91_REG * ) 0xFFFA0090 ) /* (TC2) Counter Value */ +#define AT91C_TC2_RA ( ( AT91_REG * ) 0xFFFA0094 ) /* (TC2) Register A */ +#define AT91C_TC2_RB ( ( AT91_REG * ) 0xFFFA0098 ) /* (TC2) Register B */ +#define AT91C_TC2_IDR ( ( AT91_REG * ) 0xFFFA00A8 ) /* (TC2) Interrupt Disable Register */ +#define AT91C_TC2_IMR ( ( AT91_REG * ) 0xFFFA00AC ) /* (TC2) Interrupt Mask Register */ +#define AT91C_TC2_RC ( ( AT91_REG * ) 0xFFFA009C ) /* (TC2) Register C */ +#define AT91C_TC2_IER ( ( AT91_REG * ) 0xFFFA00A4 ) /* (TC2) Interrupt Enable Register */ +#define AT91C_TC2_SR ( ( AT91_REG * ) 0xFFFA00A0 ) /* (TC2) Status Register */ +/* ========== Register definition for TCB peripheral ========== */ +#define AT91C_TCB_BMR ( ( AT91_REG * ) 0xFFFA00C4 ) /* (TCB) TC Block Mode Register */ +#define AT91C_TCB_BCR ( ( AT91_REG * ) 0xFFFA00C0 ) /* (TCB) TC Block Control Register */ +/* ========== Register definition for CAN_MB0 peripheral ========== */ +#define AT91C_CAN_MB0_MDL ( ( AT91_REG * ) 0xFFFD0214 ) /* (CAN_MB0) MailBox Data Low Register */ +#define AT91C_CAN_MB0_MAM ( ( AT91_REG * ) 0xFFFD0204 ) /* (CAN_MB0) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB0_MCR ( ( AT91_REG * ) 0xFFFD021C ) /* (CAN_MB0) MailBox Control Register */ +#define AT91C_CAN_MB0_MID ( ( AT91_REG * ) 0xFFFD0208 ) /* (CAN_MB0) MailBox ID Register */ +#define AT91C_CAN_MB0_MSR ( ( AT91_REG * ) 0xFFFD0210 ) /* (CAN_MB0) MailBox Status Register */ +#define AT91C_CAN_MB0_MFID ( ( AT91_REG * ) 0xFFFD020C ) /* (CAN_MB0) MailBox Family ID Register */ +#define AT91C_CAN_MB0_MDH ( ( AT91_REG * ) 0xFFFD0218 ) /* (CAN_MB0) MailBox Data High Register */ +#define AT91C_CAN_MB0_MMR ( ( AT91_REG * ) 0xFFFD0200 ) /* (CAN_MB0) MailBox Mode Register */ +/* ========== Register definition for CAN_MB1 peripheral ========== */ +#define AT91C_CAN_MB1_MDL ( ( AT91_REG * ) 0xFFFD0234 ) /* (CAN_MB1) MailBox Data Low Register */ +#define AT91C_CAN_MB1_MID ( ( AT91_REG * ) 0xFFFD0228 ) /* (CAN_MB1) MailBox ID Register */ +#define AT91C_CAN_MB1_MMR ( ( AT91_REG * ) 0xFFFD0220 ) /* (CAN_MB1) MailBox Mode Register */ +#define AT91C_CAN_MB1_MSR ( ( AT91_REG * ) 0xFFFD0230 ) /* (CAN_MB1) MailBox Status Register */ +#define AT91C_CAN_MB1_MAM ( ( AT91_REG * ) 0xFFFD0224 ) /* (CAN_MB1) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB1_MDH ( ( AT91_REG * ) 0xFFFD0238 ) /* (CAN_MB1) MailBox Data High Register */ +#define AT91C_CAN_MB1_MCR ( ( AT91_REG * ) 0xFFFD023C ) /* (CAN_MB1) MailBox Control Register */ +#define AT91C_CAN_MB1_MFID ( ( AT91_REG * ) 0xFFFD022C ) /* (CAN_MB1) MailBox Family ID Register */ +/* ========== Register definition for CAN_MB2 peripheral ========== */ +#define AT91C_CAN_MB2_MCR ( ( AT91_REG * ) 0xFFFD025C ) /* (CAN_MB2) MailBox Control Register */ +#define AT91C_CAN_MB2_MDH ( ( AT91_REG * ) 0xFFFD0258 ) /* (CAN_MB2) MailBox Data High Register */ +#define AT91C_CAN_MB2_MID ( ( AT91_REG * ) 0xFFFD0248 ) /* (CAN_MB2) MailBox ID Register */ +#define AT91C_CAN_MB2_MDL ( ( AT91_REG * ) 0xFFFD0254 ) /* (CAN_MB2) MailBox Data Low Register */ +#define AT91C_CAN_MB2_MMR ( ( AT91_REG * ) 0xFFFD0240 ) /* (CAN_MB2) MailBox Mode Register */ +#define AT91C_CAN_MB2_MAM ( ( AT91_REG * ) 0xFFFD0244 ) /* (CAN_MB2) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB2_MFID ( ( AT91_REG * ) 0xFFFD024C ) /* (CAN_MB2) MailBox Family ID Register */ +#define AT91C_CAN_MB2_MSR ( ( AT91_REG * ) 0xFFFD0250 ) /* (CAN_MB2) MailBox Status Register */ +/* ========== Register definition for CAN_MB3 peripheral ========== */ +#define AT91C_CAN_MB3_MFID ( ( AT91_REG * ) 0xFFFD026C ) /* (CAN_MB3) MailBox Family ID Register */ +#define AT91C_CAN_MB3_MAM ( ( AT91_REG * ) 0xFFFD0264 ) /* (CAN_MB3) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB3_MID ( ( AT91_REG * ) 0xFFFD0268 ) /* (CAN_MB3) MailBox ID Register */ +#define AT91C_CAN_MB3_MCR ( ( AT91_REG * ) 0xFFFD027C ) /* (CAN_MB3) MailBox Control Register */ +#define AT91C_CAN_MB3_MMR ( ( AT91_REG * ) 0xFFFD0260 ) /* (CAN_MB3) MailBox Mode Register */ +#define AT91C_CAN_MB3_MSR ( ( AT91_REG * ) 0xFFFD0270 ) /* (CAN_MB3) MailBox Status Register */ +#define AT91C_CAN_MB3_MDL ( ( AT91_REG * ) 0xFFFD0274 ) /* (CAN_MB3) MailBox Data Low Register */ +#define AT91C_CAN_MB3_MDH ( ( AT91_REG * ) 0xFFFD0278 ) /* (CAN_MB3) MailBox Data High Register */ +/* ========== Register definition for CAN_MB4 peripheral ========== */ +#define AT91C_CAN_MB4_MID ( ( AT91_REG * ) 0xFFFD0288 ) /* (CAN_MB4) MailBox ID Register */ +#define AT91C_CAN_MB4_MMR ( ( AT91_REG * ) 0xFFFD0280 ) /* (CAN_MB4) MailBox Mode Register */ +#define AT91C_CAN_MB4_MDH ( ( AT91_REG * ) 0xFFFD0298 ) /* (CAN_MB4) MailBox Data High Register */ +#define AT91C_CAN_MB4_MFID ( ( AT91_REG * ) 0xFFFD028C ) /* (CAN_MB4) MailBox Family ID Register */ +#define AT91C_CAN_MB4_MSR ( ( AT91_REG * ) 0xFFFD0290 ) /* (CAN_MB4) MailBox Status Register */ +#define AT91C_CAN_MB4_MCR ( ( AT91_REG * ) 0xFFFD029C ) /* (CAN_MB4) MailBox Control Register */ +#define AT91C_CAN_MB4_MDL ( ( AT91_REG * ) 0xFFFD0294 ) /* (CAN_MB4) MailBox Data Low Register */ +#define AT91C_CAN_MB4_MAM ( ( AT91_REG * ) 0xFFFD0284 ) /* (CAN_MB4) MailBox Acceptance Mask Register */ +/* ========== Register definition for CAN_MB5 peripheral ========== */ +#define AT91C_CAN_MB5_MSR ( ( AT91_REG * ) 0xFFFD02B0 ) /* (CAN_MB5) MailBox Status Register */ +#define AT91C_CAN_MB5_MCR ( ( AT91_REG * ) 0xFFFD02BC ) /* (CAN_MB5) MailBox Control Register */ +#define AT91C_CAN_MB5_MFID ( ( AT91_REG * ) 0xFFFD02AC ) /* (CAN_MB5) MailBox Family ID Register */ +#define AT91C_CAN_MB5_MDH ( ( AT91_REG * ) 0xFFFD02B8 ) /* (CAN_MB5) MailBox Data High Register */ +#define AT91C_CAN_MB5_MID ( ( AT91_REG * ) 0xFFFD02A8 ) /* (CAN_MB5) MailBox ID Register */ +#define AT91C_CAN_MB5_MMR ( ( AT91_REG * ) 0xFFFD02A0 ) /* (CAN_MB5) MailBox Mode Register */ +#define AT91C_CAN_MB5_MDL ( ( AT91_REG * ) 0xFFFD02B4 ) /* (CAN_MB5) MailBox Data Low Register */ +#define AT91C_CAN_MB5_MAM ( ( AT91_REG * ) 0xFFFD02A4 ) /* (CAN_MB5) MailBox Acceptance Mask Register */ +/* ========== Register definition for CAN_MB6 peripheral ========== */ +#define AT91C_CAN_MB6_MFID ( ( AT91_REG * ) 0xFFFD02CC ) /* (CAN_MB6) MailBox Family ID Register */ +#define AT91C_CAN_MB6_MID ( ( AT91_REG * ) 0xFFFD02C8 ) /* (CAN_MB6) MailBox ID Register */ +#define AT91C_CAN_MB6_MAM ( ( AT91_REG * ) 0xFFFD02C4 ) /* (CAN_MB6) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB6_MSR ( ( AT91_REG * ) 0xFFFD02D0 ) /* (CAN_MB6) MailBox Status Register */ +#define AT91C_CAN_MB6_MDL ( ( AT91_REG * ) 0xFFFD02D4 ) /* (CAN_MB6) MailBox Data Low Register */ +#define AT91C_CAN_MB6_MCR ( ( AT91_REG * ) 0xFFFD02DC ) /* (CAN_MB6) MailBox Control Register */ +#define AT91C_CAN_MB6_MDH ( ( AT91_REG * ) 0xFFFD02D8 ) /* (CAN_MB6) MailBox Data High Register */ +#define AT91C_CAN_MB6_MMR ( ( AT91_REG * ) 0xFFFD02C0 ) /* (CAN_MB6) MailBox Mode Register */ +/* ========== Register definition for CAN_MB7 peripheral ========== */ +#define AT91C_CAN_MB7_MCR ( ( AT91_REG * ) 0xFFFD02FC ) /* (CAN_MB7) MailBox Control Register */ +#define AT91C_CAN_MB7_MDH ( ( AT91_REG * ) 0xFFFD02F8 ) /* (CAN_MB7) MailBox Data High Register */ +#define AT91C_CAN_MB7_MFID ( ( AT91_REG * ) 0xFFFD02EC ) /* (CAN_MB7) MailBox Family ID Register */ +#define AT91C_CAN_MB7_MDL ( ( AT91_REG * ) 0xFFFD02F4 ) /* (CAN_MB7) MailBox Data Low Register */ +#define AT91C_CAN_MB7_MID ( ( AT91_REG * ) 0xFFFD02E8 ) /* (CAN_MB7) MailBox ID Register */ +#define AT91C_CAN_MB7_MMR ( ( AT91_REG * ) 0xFFFD02E0 ) /* (CAN_MB7) MailBox Mode Register */ +#define AT91C_CAN_MB7_MAM ( ( AT91_REG * ) 0xFFFD02E4 ) /* (CAN_MB7) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB7_MSR ( ( AT91_REG * ) 0xFFFD02F0 ) /* (CAN_MB7) MailBox Status Register */ +/* ========== Register definition for CAN peripheral ========== */ +#define AT91C_CAN_TCR ( ( AT91_REG * ) 0xFFFD0024 ) /* (CAN) Transfer Command Register */ +#define AT91C_CAN_IMR ( ( AT91_REG * ) 0xFFFD000C ) /* (CAN) Interrupt Mask Register */ +#define AT91C_CAN_IER ( ( AT91_REG * ) 0xFFFD0004 ) /* (CAN) Interrupt Enable Register */ +#define AT91C_CAN_ECR ( ( AT91_REG * ) 0xFFFD0020 ) /* (CAN) Error Counter Register */ +#define AT91C_CAN_TIMESTP ( ( AT91_REG * ) 0xFFFD001C ) /* (CAN) Time Stamp Register */ +#define AT91C_CAN_MR ( ( AT91_REG * ) 0xFFFD0000 ) /* (CAN) Mode Register */ +#define AT91C_CAN_IDR ( ( AT91_REG * ) 0xFFFD0008 ) /* (CAN) Interrupt Disable Register */ +#define AT91C_CAN_ACR ( ( AT91_REG * ) 0xFFFD0028 ) /* (CAN) Abort Command Register */ +#define AT91C_CAN_TIM ( ( AT91_REG * ) 0xFFFD0018 ) /* (CAN) Timer Register */ +#define AT91C_CAN_SR ( ( AT91_REG * ) 0xFFFD0010 ) /* (CAN) Status Register */ +#define AT91C_CAN_BR ( ( AT91_REG * ) 0xFFFD0014 ) /* (CAN) Baudrate Register */ +#define AT91C_CAN_VR ( ( AT91_REG * ) 0xFFFD00FC ) /* (CAN) Version Register */ +/* ========== Register definition for EMAC peripheral ========== */ +#define AT91C_EMAC_ISR ( ( AT91_REG * ) 0xFFFDC024 ) /* (EMAC) Interrupt Status Register */ +#define AT91C_EMAC_SA4H ( ( AT91_REG * ) 0xFFFDC0B4 ) /* (EMAC) Specific Address 4 Top, Last 2 bytes */ +#define AT91C_EMAC_SA1L ( ( AT91_REG * ) 0xFFFDC098 ) /* (EMAC) Specific Address 1 Bottom, First 4 bytes */ +#define AT91C_EMAC_ELE ( ( AT91_REG * ) 0xFFFDC078 ) /* (EMAC) Excessive Length Errors Register */ +#define AT91C_EMAC_LCOL ( ( AT91_REG * ) 0xFFFDC05C ) /* (EMAC) Late Collision Register */ +#define AT91C_EMAC_RLE ( ( AT91_REG * ) 0xFFFDC088 ) /* (EMAC) Receive Length Field Mismatch Register */ +#define AT91C_EMAC_WOL ( ( AT91_REG * ) 0xFFFDC0C4 ) /* (EMAC) Wake On LAN Register */ +#define AT91C_EMAC_DTF ( ( AT91_REG * ) 0xFFFDC058 ) /* (EMAC) Deferred Transmission Frame Register */ +#define AT91C_EMAC_TUND ( ( AT91_REG * ) 0xFFFDC064 ) /* (EMAC) Transmit Underrun Error Register */ +#define AT91C_EMAC_NCR ( ( AT91_REG * ) 0xFFFDC000 ) /* (EMAC) Network Control Register */ +#define AT91C_EMAC_SA4L ( ( AT91_REG * ) 0xFFFDC0B0 ) /* (EMAC) Specific Address 4 Bottom, First 4 bytes */ +#define AT91C_EMAC_RSR ( ( AT91_REG * ) 0xFFFDC020 ) /* (EMAC) Receive Status Register */ +#define AT91C_EMAC_SA3L ( ( AT91_REG * ) 0xFFFDC0A8 ) /* (EMAC) Specific Address 3 Bottom, First 4 bytes */ +#define AT91C_EMAC_TSR ( ( AT91_REG * ) 0xFFFDC014 ) /* (EMAC) Transmit Status Register */ +#define AT91C_EMAC_IDR ( ( AT91_REG * ) 0xFFFDC02C ) /* (EMAC) Interrupt Disable Register */ +#define AT91C_EMAC_RSE ( ( AT91_REG * ) 0xFFFDC074 ) /* (EMAC) Receive Symbol Errors Register */ +#define AT91C_EMAC_ECOL ( ( AT91_REG * ) 0xFFFDC060 ) /* (EMAC) Excessive Collision Register */ +#define AT91C_EMAC_TID ( ( AT91_REG * ) 0xFFFDC0B8 ) /* (EMAC) Type ID Checking Register */ +#define AT91C_EMAC_HRB ( ( AT91_REG * ) 0xFFFDC090 ) /* (EMAC) Hash Address Bottom[31:0] */ +#define AT91C_EMAC_TBQP ( ( AT91_REG * ) 0xFFFDC01C ) /* (EMAC) Transmit Buffer Queue Pointer */ +#define AT91C_EMAC_USRIO ( ( AT91_REG * ) 0xFFFDC0C0 ) /* (EMAC) USER Input/Output Register */ +#define AT91C_EMAC_PTR ( ( AT91_REG * ) 0xFFFDC038 ) /* (EMAC) Pause Time Register */ +#define AT91C_EMAC_SA2H ( ( AT91_REG * ) 0xFFFDC0A4 ) /* (EMAC) Specific Address 2 Top, Last 2 bytes */ +#define AT91C_EMAC_ROV ( ( AT91_REG * ) 0xFFFDC070 ) /* (EMAC) Receive Overrun Errors Register */ +#define AT91C_EMAC_ALE ( ( AT91_REG * ) 0xFFFDC054 ) /* (EMAC) Alignment Error Register */ +#define AT91C_EMAC_RJA ( ( AT91_REG * ) 0xFFFDC07C ) /* (EMAC) Receive Jabbers Register */ +#define AT91C_EMAC_RBQP ( ( AT91_REG * ) 0xFFFDC018 ) /* (EMAC) Receive Buffer Queue Pointer */ +#define AT91C_EMAC_TPF ( ( AT91_REG * ) 0xFFFDC08C ) /* (EMAC) Transmitted Pause Frames Register */ +#define AT91C_EMAC_NCFGR ( ( AT91_REG * ) 0xFFFDC004 ) /* (EMAC) Network Configuration Register */ +#define AT91C_EMAC_HRT ( ( AT91_REG * ) 0xFFFDC094 ) /* (EMAC) Hash Address Top[63:32] */ +#define AT91C_EMAC_USF ( ( AT91_REG * ) 0xFFFDC080 ) /* (EMAC) Undersize Frames Register */ +#define AT91C_EMAC_FCSE ( ( AT91_REG * ) 0xFFFDC050 ) /* (EMAC) Frame Check Sequence Error Register */ +#define AT91C_EMAC_TPQ ( ( AT91_REG * ) 0xFFFDC0BC ) /* (EMAC) Transmit Pause Quantum Register */ +#define AT91C_EMAC_MAN ( ( AT91_REG * ) 0xFFFDC034 ) /* (EMAC) PHY Maintenance Register */ +#define AT91C_EMAC_FTO ( ( AT91_REG * ) 0xFFFDC040 ) /* (EMAC) Frames Transmitted OK Register */ +#define AT91C_EMAC_REV ( ( AT91_REG * ) 0xFFFDC0FC ) /* (EMAC) Revision Register */ +#define AT91C_EMAC_IMR ( ( AT91_REG * ) 0xFFFDC030 ) /* (EMAC) Interrupt Mask Register */ +#define AT91C_EMAC_SCF ( ( AT91_REG * ) 0xFFFDC044 ) /* (EMAC) Single Collision Frame Register */ +#define AT91C_EMAC_PFR ( ( AT91_REG * ) 0xFFFDC03C ) /* (EMAC) Pause Frames received Register */ +#define AT91C_EMAC_MCF ( ( AT91_REG * ) 0xFFFDC048 ) /* (EMAC) Multiple Collision Frame Register */ +#define AT91C_EMAC_NSR ( ( AT91_REG * ) 0xFFFDC008 ) /* (EMAC) Network Status Register */ +#define AT91C_EMAC_SA2L ( ( AT91_REG * ) 0xFFFDC0A0 ) /* (EMAC) Specific Address 2 Bottom, First 4 bytes */ +#define AT91C_EMAC_FRO ( ( AT91_REG * ) 0xFFFDC04C ) /* (EMAC) Frames Received OK Register */ +#define AT91C_EMAC_IER ( ( AT91_REG * ) 0xFFFDC028 ) /* (EMAC) Interrupt Enable Register */ +#define AT91C_EMAC_SA1H ( ( AT91_REG * ) 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */ +#define AT91C_EMAC_CSE ( ( AT91_REG * ) 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */ +#define AT91C_EMAC_SA3H ( ( AT91_REG * ) 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */ +#define AT91C_EMAC_RRE ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Resource Error Register */ +#define AT91C_EMAC_STE ( ( AT91_REG * ) 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */ +/* ========== Register definition for PDC_ADC peripheral ========== */ +#define AT91C_ADC_PTSR ( ( AT91_REG * ) 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */ +#define AT91C_ADC_PTCR ( ( AT91_REG * ) 0xFFFD8120 ) /* (PDC_ADC) PDC Transfer Control Register */ +#define AT91C_ADC_TNPR ( ( AT91_REG * ) 0xFFFD8118 ) /* (PDC_ADC) Transmit Next Pointer Register */ +#define AT91C_ADC_TNCR ( ( AT91_REG * ) 0xFFFD811C ) /* (PDC_ADC) Transmit Next Counter Register */ +#define AT91C_ADC_RNPR ( ( AT91_REG * ) 0xFFFD8110 ) /* (PDC_ADC) Receive Next Pointer Register */ +#define AT91C_ADC_RNCR ( ( AT91_REG * ) 0xFFFD8114 ) /* (PDC_ADC) Receive Next Counter Register */ +#define AT91C_ADC_RPR ( ( AT91_REG * ) 0xFFFD8100 ) /* (PDC_ADC) Receive Pointer Register */ +#define AT91C_ADC_TCR ( ( AT91_REG * ) 0xFFFD810C ) /* (PDC_ADC) Transmit Counter Register */ +#define AT91C_ADC_TPR ( ( AT91_REG * ) 0xFFFD8108 ) /* (PDC_ADC) Transmit Pointer Register */ +#define AT91C_ADC_RCR ( ( AT91_REG * ) 0xFFFD8104 ) /* (PDC_ADC) Receive Counter Register */ +/* ========== Register definition for ADC peripheral ========== */ +#define AT91C_ADC_CDR2 ( ( AT91_REG * ) 0xFFFD8038 ) /* (ADC) ADC Channel Data Register 2 */ +#define AT91C_ADC_CDR3 ( ( AT91_REG * ) 0xFFFD803C ) /* (ADC) ADC Channel Data Register 3 */ +#define AT91C_ADC_CDR0 ( ( AT91_REG * ) 0xFFFD8030 ) /* (ADC) ADC Channel Data Register 0 */ +#define AT91C_ADC_CDR5 ( ( AT91_REG * ) 0xFFFD8044 ) /* (ADC) ADC Channel Data Register 5 */ +#define AT91C_ADC_CHDR ( ( AT91_REG * ) 0xFFFD8014 ) /* (ADC) ADC Channel Disable Register */ +#define AT91C_ADC_SR ( ( AT91_REG * ) 0xFFFD801C ) /* (ADC) ADC Status Register */ +#define AT91C_ADC_CDR4 ( ( AT91_REG * ) 0xFFFD8040 ) /* (ADC) ADC Channel Data Register 4 */ +#define AT91C_ADC_CDR1 ( ( AT91_REG * ) 0xFFFD8034 ) /* (ADC) ADC Channel Data Register 1 */ +#define AT91C_ADC_LCDR ( ( AT91_REG * ) 0xFFFD8020 ) /* (ADC) ADC Last Converted Data Register */ +#define AT91C_ADC_IDR ( ( AT91_REG * ) 0xFFFD8028 ) /* (ADC) ADC Interrupt Disable Register */ +#define AT91C_ADC_CR ( ( AT91_REG * ) 0xFFFD8000 ) /* (ADC) ADC Control Register */ +#define AT91C_ADC_CDR7 ( ( AT91_REG * ) 0xFFFD804C ) /* (ADC) ADC Channel Data Register 7 */ +#define AT91C_ADC_CDR6 ( ( AT91_REG * ) 0xFFFD8048 ) /* (ADC) ADC Channel Data Register 6 */ +#define AT91C_ADC_IER ( ( AT91_REG * ) 0xFFFD8024 ) /* (ADC) ADC Interrupt Enable Register */ +#define AT91C_ADC_CHER ( ( AT91_REG * ) 0xFFFD8010 ) /* (ADC) ADC Channel Enable Register */ +#define AT91C_ADC_CHSR ( ( AT91_REG * ) 0xFFFD8018 ) /* (ADC) ADC Channel Status Register */ +#define AT91C_ADC_MR ( ( AT91_REG * ) 0xFFFD8004 ) /* (ADC) ADC Mode Register */ +#define AT91C_ADC_IMR ( ( AT91_REG * ) 0xFFFD802C ) /* (ADC) ADC Interrupt Mask Register */ +/* ========== Register definition for PDC_AES peripheral ========== */ +#define AT91C_AES_TPR ( ( AT91_REG * ) 0xFFFA4108 ) /* (PDC_AES) Transmit Pointer Register */ +#define AT91C_AES_PTCR ( ( AT91_REG * ) 0xFFFA4120 ) /* (PDC_AES) PDC Transfer Control Register */ +#define AT91C_AES_RNPR ( ( AT91_REG * ) 0xFFFA4110 ) /* (PDC_AES) Receive Next Pointer Register */ +#define AT91C_AES_TNCR ( ( AT91_REG * ) 0xFFFA411C ) /* (PDC_AES) Transmit Next Counter Register */ +#define AT91C_AES_TCR ( ( AT91_REG * ) 0xFFFA410C ) /* (PDC_AES) Transmit Counter Register */ +#define AT91C_AES_RCR ( ( AT91_REG * ) 0xFFFA4104 ) /* (PDC_AES) Receive Counter Register */ +#define AT91C_AES_RNCR ( ( AT91_REG * ) 0xFFFA4114 ) /* (PDC_AES) Receive Next Counter Register */ +#define AT91C_AES_TNPR ( ( AT91_REG * ) 0xFFFA4118 ) /* (PDC_AES) Transmit Next Pointer Register */ +#define AT91C_AES_RPR ( ( AT91_REG * ) 0xFFFA4100 ) /* (PDC_AES) Receive Pointer Register */ +#define AT91C_AES_PTSR ( ( AT91_REG * ) 0xFFFA4124 ) /* (PDC_AES) PDC Transfer Status Register */ +/* ========== Register definition for AES peripheral ========== */ +#define AT91C_AES_IVxR ( ( AT91_REG * ) 0xFFFA4060 ) /* (AES) Initialization Vector x Register */ +#define AT91C_AES_MR ( ( AT91_REG * ) 0xFFFA4004 ) /* (AES) Mode Register */ +#define AT91C_AES_VR ( ( AT91_REG * ) 0xFFFA40FC ) /* (AES) AES Version Register */ +#define AT91C_AES_ODATAxR ( ( AT91_REG * ) 0xFFFA4050 ) /* (AES) Output Data x Register */ +#define AT91C_AES_IDATAxR ( ( AT91_REG * ) 0xFFFA4040 ) /* (AES) Input Data x Register */ +#define AT91C_AES_CR ( ( AT91_REG * ) 0xFFFA4000 ) /* (AES) Control Register */ +#define AT91C_AES_IDR ( ( AT91_REG * ) 0xFFFA4014 ) /* (AES) Interrupt Disable Register */ +#define AT91C_AES_IMR ( ( AT91_REG * ) 0xFFFA4018 ) /* (AES) Interrupt Mask Register */ +#define AT91C_AES_IER ( ( AT91_REG * ) 0xFFFA4010 ) /* (AES) Interrupt Enable Register */ +#define AT91C_AES_KEYWxR ( ( AT91_REG * ) 0xFFFA4020 ) /* (AES) Key Word x Register */ +#define AT91C_AES_ISR ( ( AT91_REG * ) 0xFFFA401C ) /* (AES) Interrupt Status Register */ +/* ========== Register definition for PDC_TDES peripheral ========== */ +#define AT91C_TDES_RNCR ( ( AT91_REG * ) 0xFFFA8114 ) /* (PDC_TDES) Receive Next Counter Register */ +#define AT91C_TDES_TCR ( ( AT91_REG * ) 0xFFFA810C ) /* (PDC_TDES) Transmit Counter Register */ +#define AT91C_TDES_RCR ( ( AT91_REG * ) 0xFFFA8104 ) /* (PDC_TDES) Receive Counter Register */ +#define AT91C_TDES_TNPR ( ( AT91_REG * ) 0xFFFA8118 ) /* (PDC_TDES) Transmit Next Pointer Register */ +#define AT91C_TDES_RNPR ( ( AT91_REG * ) 0xFFFA8110 ) /* (PDC_TDES) Receive Next Pointer Register */ +#define AT91C_TDES_RPR ( ( AT91_REG * ) 0xFFFA8100 ) /* (PDC_TDES) Receive Pointer Register */ +#define AT91C_TDES_TNCR ( ( AT91_REG * ) 0xFFFA811C ) /* (PDC_TDES) Transmit Next Counter Register */ +#define AT91C_TDES_TPR ( ( AT91_REG * ) 0xFFFA8108 ) /* (PDC_TDES) Transmit Pointer Register */ +#define AT91C_TDES_PTSR ( ( AT91_REG * ) 0xFFFA8124 ) /* (PDC_TDES) PDC Transfer Status Register */ +#define AT91C_TDES_PTCR ( ( AT91_REG * ) 0xFFFA8120 ) /* (PDC_TDES) PDC Transfer Control Register */ +/* ========== Register definition for TDES peripheral ========== */ +#define AT91C_TDES_KEY2WxR ( ( AT91_REG * ) 0xFFFA8028 ) /* (TDES) Key 2 Word x Register */ +#define AT91C_TDES_KEY3WxR ( ( AT91_REG * ) 0xFFFA8030 ) /* (TDES) Key 3 Word x Register */ +#define AT91C_TDES_IDR ( ( AT91_REG * ) 0xFFFA8014 ) /* (TDES) Interrupt Disable Register */ +#define AT91C_TDES_VR ( ( AT91_REG * ) 0xFFFA80FC ) /* (TDES) TDES Version Register */ +#define AT91C_TDES_IVxR ( ( AT91_REG * ) 0xFFFA8060 ) /* (TDES) Initialization Vector x Register */ +#define AT91C_TDES_ODATAxR ( ( AT91_REG * ) 0xFFFA8050 ) /* (TDES) Output Data x Register */ +#define AT91C_TDES_IMR ( ( AT91_REG * ) 0xFFFA8018 ) /* (TDES) Interrupt Mask Register */ +#define AT91C_TDES_MR ( ( AT91_REG * ) 0xFFFA8004 ) /* (TDES) Mode Register */ +#define AT91C_TDES_CR ( ( AT91_REG * ) 0xFFFA8000 ) /* (TDES) Control Register */ +#define AT91C_TDES_IER ( ( AT91_REG * ) 0xFFFA8010 ) /* (TDES) Interrupt Enable Register */ +#define AT91C_TDES_ISR ( ( AT91_REG * ) 0xFFFA801C ) /* (TDES) Interrupt Status Register */ +#define AT91C_TDES_IDATAxR ( ( AT91_REG * ) 0xFFFA8040 ) /* (TDES) Input Data x Register */ +#define AT91C_TDES_KEY1WxR ( ( AT91_REG * ) 0xFFFA8020 ) /* (TDES) Key 1 Word x Register */ + +/* ***************************************************************************** */ +/* PIO DEFINITIONS FOR AT91SAM7X128 */ +/* ***************************************************************************** */ +#define AT91C_PIO_PA0 ( ( unsigned int ) 1 << 0 ) /* Pin Controlled by PA0 */ +#define AT91C_PA0_RXD0 ( ( unsigned int ) AT91C_PIO_PA0 ) /* USART 0 Receive Data */ +#define AT91C_PIO_PA1 ( ( unsigned int ) 1 << 1 ) /* Pin Controlled by PA1 */ +#define AT91C_PA1_TXD0 ( ( unsigned int ) AT91C_PIO_PA1 ) /* USART 0 Transmit Data */ +#define AT91C_PIO_PA10 ( ( unsigned int ) 1 << 10 ) /* Pin Controlled by PA10 */ +#define AT91C_PA10_TWD ( ( unsigned int ) AT91C_PIO_PA10 ) /* TWI Two-wire Serial Data */ +#define AT91C_PIO_PA11 ( ( unsigned int ) 1 << 11 ) /* Pin Controlled by PA11 */ +#define AT91C_PA11_TWCK ( ( unsigned int ) AT91C_PIO_PA11 ) /* TWI Two-wire Serial Clock */ +#define AT91C_PIO_PA12 ( ( unsigned int ) 1 << 12 ) /* Pin Controlled by PA12 */ +#define AT91C_PA12_NPCS00 ( ( unsigned int ) AT91C_PIO_PA12 ) /* SPI 0 Peripheral Chip Select 0 */ +#define AT91C_PIO_PA13 ( ( unsigned int ) 1 << 13 ) /* Pin Controlled by PA13 */ +#define AT91C_PA13_NPCS01 ( ( unsigned int ) AT91C_PIO_PA13 ) /* SPI 0 Peripheral Chip Select 1 */ +#define AT91C_PA13_PCK1 ( ( unsigned int ) AT91C_PIO_PA13 ) /* PMC Programmable Clock Output 1 */ +#define AT91C_PIO_PA14 ( ( unsigned int ) 1 << 14 ) /* Pin Controlled by PA14 */ +#define AT91C_PA14_NPCS02 ( ( unsigned int ) AT91C_PIO_PA14 ) /* SPI 0 Peripheral Chip Select 2 */ +#define AT91C_PA14_IRQ1 ( ( unsigned int ) AT91C_PIO_PA14 ) /* External Interrupt 1 */ +#define AT91C_PIO_PA15 ( ( unsigned int ) 1 << 15 ) /* Pin Controlled by PA15 */ +#define AT91C_PA15_NPCS03 ( ( unsigned int ) AT91C_PIO_PA15 ) /* SPI 0 Peripheral Chip Select 3 */ +#define AT91C_PA15_TCLK2 ( ( unsigned int ) AT91C_PIO_PA15 ) /* Timer Counter 2 external clock input */ +#define AT91C_PIO_PA16 ( ( unsigned int ) 1 << 16 ) /* Pin Controlled by PA16 */ +#define AT91C_PA16_MISO0 ( ( unsigned int ) AT91C_PIO_PA16 ) /* SPI 0 Master In Slave */ +#define AT91C_PIO_PA17 ( ( unsigned int ) 1 << 17 ) /* Pin Controlled by PA17 */ +#define AT91C_PA17_MOSI0 ( ( unsigned int ) AT91C_PIO_PA17 ) /* SPI 0 Master Out Slave */ +#define AT91C_PIO_PA18 ( ( unsigned int ) 1 << 18 ) /* Pin Controlled by PA18 */ +#define AT91C_PA18_SPCK0 ( ( unsigned int ) AT91C_PIO_PA18 ) /* SPI 0 Serial Clock */ +#define AT91C_PIO_PA19 ( ( unsigned int ) 1 << 19 ) /* Pin Controlled by PA19 */ +#define AT91C_PA19_CANRX ( ( unsigned int ) AT91C_PIO_PA19 ) /* CAN Receive */ +#define AT91C_PIO_PA2 ( ( unsigned int ) 1 << 2 ) /* Pin Controlled by PA2 */ +#define AT91C_PA2_SCK0 ( ( unsigned int ) AT91C_PIO_PA2 ) /* USART 0 Serial Clock */ +#define AT91C_PA2_NPCS11 ( ( unsigned int ) AT91C_PIO_PA2 ) /* SPI 1 Peripheral Chip Select 1 */ +#define AT91C_PIO_PA20 ( ( unsigned int ) 1 << 20 ) /* Pin Controlled by PA20 */ +#define AT91C_PA20_CANTX ( ( unsigned int ) AT91C_PIO_PA20 ) /* CAN Transmit */ +#define AT91C_PIO_PA21 ( ( unsigned int ) 1 << 21 ) /* Pin Controlled by PA21 */ +#define AT91C_PA21_TF ( ( unsigned int ) AT91C_PIO_PA21 ) /* SSC Transmit Frame Sync */ +#define AT91C_PA21_NPCS10 ( ( unsigned int ) AT91C_PIO_PA21 ) /* SPI 1 Peripheral Chip Select 0 */ +#define AT91C_PIO_PA22 ( ( unsigned int ) 1 << 22 ) /* Pin Controlled by PA22 */ +#define AT91C_PA22_TK ( ( unsigned int ) AT91C_PIO_PA22 ) /* SSC Transmit Clock */ +#define AT91C_PA22_SPCK1 ( ( unsigned int ) AT91C_PIO_PA22 ) /* SPI 1 Serial Clock */ +#define AT91C_PIO_PA23 ( ( unsigned int ) 1 << 23 ) /* Pin Controlled by PA23 */ +#define AT91C_PA23_TD ( ( unsigned int ) AT91C_PIO_PA23 ) /* SSC Transmit data */ +#define AT91C_PA23_MOSI1 ( ( unsigned int ) AT91C_PIO_PA23 ) /* SPI 1 Master Out Slave */ +#define AT91C_PIO_PA24 ( ( unsigned int ) 1 << 24 ) /* Pin Controlled by PA24 */ +#define AT91C_PA24_RD ( ( unsigned int ) AT91C_PIO_PA24 ) /* SSC Receive Data */ +#define AT91C_PA24_MISO1 ( ( unsigned int ) AT91C_PIO_PA24 ) /* SPI 1 Master In Slave */ +#define AT91C_PIO_PA25 ( ( unsigned int ) 1 << 25 ) /* Pin Controlled by PA25 */ +#define AT91C_PA25_RK ( ( unsigned int ) AT91C_PIO_PA25 ) /* SSC Receive Clock */ +#define AT91C_PA25_NPCS11 ( ( unsigned int ) AT91C_PIO_PA25 ) /* SPI 1 Peripheral Chip Select 1 */ +#define AT91C_PIO_PA26 ( ( unsigned int ) 1 << 26 ) /* Pin Controlled by PA26 */ +#define AT91C_PA26_RF ( ( unsigned int ) AT91C_PIO_PA26 ) /* SSC Receive Frame Sync */ +#define AT91C_PA26_NPCS12 ( ( unsigned int ) AT91C_PIO_PA26 ) /* SPI 1 Peripheral Chip Select 2 */ +#define AT91C_PIO_PA27 ( ( unsigned int ) 1 << 27 ) /* Pin Controlled by PA27 */ +#define AT91C_PA27_DRXD ( ( unsigned int ) AT91C_PIO_PA27 ) /* DBGU Debug Receive Data */ +#define AT91C_PA27_PCK3 ( ( unsigned int ) AT91C_PIO_PA27 ) /* PMC Programmable Clock Output 3 */ +#define AT91C_PIO_PA28 ( ( unsigned int ) 1 << 28 ) /* Pin Controlled by PA28 */ +#define AT91C_PA28_DTXD ( ( unsigned int ) AT91C_PIO_PA28 ) /* DBGU Debug Transmit Data */ +#define AT91C_PIO_PA29 ( ( unsigned int ) 1 << 29 ) /* Pin Controlled by PA29 */ +#define AT91C_PA29_FIQ ( ( unsigned int ) AT91C_PIO_PA29 ) /* AIC Fast Interrupt Input */ +#define AT91C_PA29_NPCS13 ( ( unsigned int ) AT91C_PIO_PA29 ) /* SPI 1 Peripheral Chip Select 3 */ +#define AT91C_PIO_PA3 ( ( unsigned int ) 1 << 3 ) /* Pin Controlled by PA3 */ +#define AT91C_PA3_RTS0 ( ( unsigned int ) AT91C_PIO_PA3 ) /* USART 0 Ready To Send */ +#define AT91C_PA3_NPCS12 ( ( unsigned int ) AT91C_PIO_PA3 ) /* SPI 1 Peripheral Chip Select 2 */ +#define AT91C_PIO_PA30 ( ( unsigned int ) 1 << 30 ) /* Pin Controlled by PA30 */ +#define AT91C_PA30_IRQ0 ( ( unsigned int ) AT91C_PIO_PA30 ) /* External Interrupt 0 */ +#define AT91C_PA30_PCK2 ( ( unsigned int ) AT91C_PIO_PA30 ) /* PMC Programmable Clock Output 2 */ +#define AT91C_PIO_PA4 ( ( unsigned int ) 1 << 4 ) /* Pin Controlled by PA4 */ +#define AT91C_PA4_CTS0 ( ( unsigned int ) AT91C_PIO_PA4 ) /* USART 0 Clear To Send */ +#define AT91C_PA4_NPCS13 ( ( unsigned int ) AT91C_PIO_PA4 ) /* SPI 1 Peripheral Chip Select 3 */ +#define AT91C_PIO_PA5 ( ( unsigned int ) 1 << 5 ) /* Pin Controlled by PA5 */ +#define AT91C_PA5_RXD1 ( ( unsigned int ) AT91C_PIO_PA5 ) /* USART 1 Receive Data */ +#define AT91C_PIO_PA6 ( ( unsigned int ) 1 << 6 ) /* Pin Controlled by PA6 */ +#define AT91C_PA6_TXD1 ( ( unsigned int ) AT91C_PIO_PA6 ) /* USART 1 Transmit Data */ +#define AT91C_PIO_PA7 ( ( unsigned int ) 1 << 7 ) /* Pin Controlled by PA7 */ +#define AT91C_PA7_SCK1 ( ( unsigned int ) AT91C_PIO_PA7 ) /* USART 1 Serial Clock */ +#define AT91C_PA7_NPCS01 ( ( unsigned int ) AT91C_PIO_PA7 ) /* SPI 0 Peripheral Chip Select 1 */ +#define AT91C_PIO_PA8 ( ( unsigned int ) 1 << 8 ) /* Pin Controlled by PA8 */ +#define AT91C_PA8_RTS1 ( ( unsigned int ) AT91C_PIO_PA8 ) /* USART 1 Ready To Send */ +#define AT91C_PA8_NPCS02 ( ( unsigned int ) AT91C_PIO_PA8 ) /* SPI 0 Peripheral Chip Select 2 */ +#define AT91C_PIO_PA9 ( ( unsigned int ) 1 << 9 ) /* Pin Controlled by PA9 */ +#define AT91C_PA9_CTS1 ( ( unsigned int ) AT91C_PIO_PA9 ) /* USART 1 Clear To Send */ +#define AT91C_PA9_NPCS03 ( ( unsigned int ) AT91C_PIO_PA9 ) /* SPI 0 Peripheral Chip Select 3 */ +#define AT91C_PIO_PB0 ( ( unsigned int ) 1 << 0 ) /* Pin Controlled by PB0 */ +#define AT91C_PB0_ETXCK_EREFCK ( ( unsigned int ) AT91C_PIO_PB0 ) /* Ethernet MAC Transmit Clock/Reference Clock */ +#define AT91C_PB0_PCK0 ( ( unsigned int ) AT91C_PIO_PB0 ) /* PMC Programmable Clock Output 0 */ +#define AT91C_PIO_PB1 ( ( unsigned int ) 1 << 1 ) /* Pin Controlled by PB1 */ +#define AT91C_PB1_ETXEN ( ( unsigned int ) AT91C_PIO_PB1 ) /* Ethernet MAC Transmit Enable */ +#define AT91C_PIO_PB10 ( ( unsigned int ) 1 << 10 ) /* Pin Controlled by PB10 */ +#define AT91C_PB10_ETX2 ( ( unsigned int ) AT91C_PIO_PB10 ) /* Ethernet MAC Transmit Data 2 */ +#define AT91C_PB10_NPCS11 ( ( unsigned int ) AT91C_PIO_PB10 ) /* SPI 1 Peripheral Chip Select 1 */ +#define AT91C_PIO_PB11 ( ( unsigned int ) 1 << 11 ) /* Pin Controlled by PB11 */ +#define AT91C_PB11_ETX3 ( ( unsigned int ) AT91C_PIO_PB11 ) /* Ethernet MAC Transmit Data 3 */ +#define AT91C_PB11_NPCS12 ( ( unsigned int ) AT91C_PIO_PB11 ) /* SPI 1 Peripheral Chip Select 2 */ +#define AT91C_PIO_PB12 ( ( unsigned int ) 1 << 12 ) /* Pin Controlled by PB12 */ +#define AT91C_PB12_ETXER ( ( unsigned int ) AT91C_PIO_PB12 ) /* Ethernet MAC Transmit Coding Error */ +#define AT91C_PB12_TCLK0 ( ( unsigned int ) AT91C_PIO_PB12 ) /* Timer Counter 0 external clock input */ +#define AT91C_PIO_PB13 ( ( unsigned int ) 1 << 13 ) /* Pin Controlled by PB13 */ +#define AT91C_PB13_ERX2 ( ( unsigned int ) AT91C_PIO_PB13 ) /* Ethernet MAC Receive Data 2 */ +#define AT91C_PB13_NPCS01 ( ( unsigned int ) AT91C_PIO_PB13 ) /* SPI 0 Peripheral Chip Select 1 */ +#define AT91C_PIO_PB14 ( ( unsigned int ) 1 << 14 ) /* Pin Controlled by PB14 */ +#define AT91C_PB14_ERX3 ( ( unsigned int ) AT91C_PIO_PB14 ) /* Ethernet MAC Receive Data 3 */ +#define AT91C_PB14_NPCS02 ( ( unsigned int ) AT91C_PIO_PB14 ) /* SPI 0 Peripheral Chip Select 2 */ +#define AT91C_PIO_PB15 ( ( unsigned int ) 1 << 15 ) /* Pin Controlled by PB15 */ +#define AT91C_PB15_ERXDV ( ( unsigned int ) AT91C_PIO_PB15 ) /* Ethernet MAC Receive Data Valid */ +#define AT91C_PIO_PB16 ( ( unsigned int ) 1 << 16 ) /* Pin Controlled by PB16 */ +#define AT91C_PB16_ECOL ( ( unsigned int ) AT91C_PIO_PB16 ) /* Ethernet MAC Collision Detected */ +#define AT91C_PB16_NPCS13 ( ( unsigned int ) AT91C_PIO_PB16 ) /* SPI 1 Peripheral Chip Select 3 */ +#define AT91C_PIO_PB17 ( ( unsigned int ) 1 << 17 ) /* Pin Controlled by PB17 */ +#define AT91C_PB17_ERXCK ( ( unsigned int ) AT91C_PIO_PB17 ) /* Ethernet MAC Receive Clock */ +#define AT91C_PB17_NPCS03 ( ( unsigned int ) AT91C_PIO_PB17 ) /* SPI 0 Peripheral Chip Select 3 */ +#define AT91C_PIO_PB18 ( ( unsigned int ) 1 << 18 ) /* Pin Controlled by PB18 */ +#define AT91C_PB18_EF100 ( ( unsigned int ) AT91C_PIO_PB18 ) /* Ethernet MAC Force 100 Mbits/sec */ +#define AT91C_PB18_ADTRG ( ( unsigned int ) AT91C_PIO_PB18 ) /* ADC External Trigger */ +#define AT91C_PIO_PB19 ( ( unsigned int ) 1 << 19 ) /* Pin Controlled by PB19 */ +#define AT91C_PB19_PWM0 ( ( unsigned int ) AT91C_PIO_PB19 ) /* PWM Channel 0 */ +#define AT91C_PB19_TCLK1 ( ( unsigned int ) AT91C_PIO_PB19 ) /* Timer Counter 1 external clock input */ +#define AT91C_PIO_PB2 ( ( unsigned int ) 1 << 2 ) /* Pin Controlled by PB2 */ +#define AT91C_PB2_ETX0 ( ( unsigned int ) AT91C_PIO_PB2 ) /* Ethernet MAC Transmit Data 0 */ +#define AT91C_PIO_PB20 ( ( unsigned int ) 1 << 20 ) /* Pin Controlled by PB20 */ +#define AT91C_PB20_PWM1 ( ( unsigned int ) AT91C_PIO_PB20 ) /* PWM Channel 1 */ +#define AT91C_PB20_PCK0 ( ( unsigned int ) AT91C_PIO_PB20 ) /* PMC Programmable Clock Output 0 */ +#define AT91C_PIO_PB21 ( ( unsigned int ) 1 << 21 ) /* Pin Controlled by PB21 */ +#define AT91C_PB21_PWM2 ( ( unsigned int ) AT91C_PIO_PB21 ) /* PWM Channel 2 */ +#define AT91C_PB21_PCK1 ( ( unsigned int ) AT91C_PIO_PB21 ) /* PMC Programmable Clock Output 1 */ +#define AT91C_PIO_PB22 ( ( unsigned int ) 1 << 22 ) /* Pin Controlled by PB22 */ +#define AT91C_PB22_PWM3 ( ( unsigned int ) AT91C_PIO_PB22 ) /* PWM Channel 3 */ +#define AT91C_PB22_PCK2 ( ( unsigned int ) AT91C_PIO_PB22 ) /* PMC Programmable Clock Output 2 */ +#define AT91C_PIO_PB23 ( ( unsigned int ) 1 << 23 ) /* Pin Controlled by PB23 */ +#define AT91C_PB23_TIOA0 ( ( unsigned int ) AT91C_PIO_PB23 ) /* Timer Counter 0 Multipurpose Timer I/O Pin A */ +#define AT91C_PB23_DCD1 ( ( unsigned int ) AT91C_PIO_PB23 ) /* USART 1 Data Carrier Detect */ +#define AT91C_PIO_PB24 ( ( unsigned int ) 1 << 24 ) /* Pin Controlled by PB24 */ +#define AT91C_PB24_TIOB0 ( ( unsigned int ) AT91C_PIO_PB24 ) /* Timer Counter 0 Multipurpose Timer I/O Pin B */ +#define AT91C_PB24_DSR1 ( ( unsigned int ) AT91C_PIO_PB24 ) /* USART 1 Data Set ready */ +#define AT91C_PIO_PB25 ( ( unsigned int ) 1 << 25 ) /* Pin Controlled by PB25 */ +#define AT91C_PB25_TIOA1 ( ( unsigned int ) AT91C_PIO_PB25 ) /* Timer Counter 1 Multipurpose Timer I/O Pin A */ +#define AT91C_PB25_DTR1 ( ( unsigned int ) AT91C_PIO_PB25 ) /* USART 1 Data Terminal ready */ +#define AT91C_PIO_PB26 ( ( unsigned int ) 1 << 26 ) /* Pin Controlled by PB26 */ +#define AT91C_PB26_TIOB1 ( ( unsigned int ) AT91C_PIO_PB26 ) /* Timer Counter 1 Multipurpose Timer I/O Pin B */ +#define AT91C_PB26_RI1 ( ( unsigned int ) AT91C_PIO_PB26 ) /* USART 1 Ring Indicator */ +#define AT91C_PIO_PB27 ( ( unsigned int ) 1 << 27 ) /* Pin Controlled by PB27 */ +#define AT91C_PB27_TIOA2 ( ( unsigned int ) AT91C_PIO_PB27 ) /* Timer Counter 2 Multipurpose Timer I/O Pin A */ +#define AT91C_PB27_PWM0 ( ( unsigned int ) AT91C_PIO_PB27 ) /* PWM Channel 0 */ +#define AT91C_PIO_PB28 ( ( unsigned int ) 1 << 28 ) /* Pin Controlled by PB28 */ +#define AT91C_PB28_TIOB2 ( ( unsigned int ) AT91C_PIO_PB28 ) /* Timer Counter 2 Multipurpose Timer I/O Pin B */ +#define AT91C_PB28_PWM1 ( ( unsigned int ) AT91C_PIO_PB28 ) /* PWM Channel 1 */ +#define AT91C_PIO_PB29 ( ( unsigned int ) 1 << 29 ) /* Pin Controlled by PB29 */ +#define AT91C_PB29_PCK1 ( ( unsigned int ) AT91C_PIO_PB29 ) /* PMC Programmable Clock Output 1 */ +#define AT91C_PB29_PWM2 ( ( unsigned int ) AT91C_PIO_PB29 ) /* PWM Channel 2 */ +#define AT91C_PIO_PB3 ( ( unsigned int ) 1 << 3 ) /* Pin Controlled by PB3 */ +#define AT91C_PB3_ETX1 ( ( unsigned int ) AT91C_PIO_PB3 ) /* Ethernet MAC Transmit Data 1 */ +#define AT91C_PIO_PB30 ( ( unsigned int ) 1 << 30 ) /* Pin Controlled by PB30 */ +#define AT91C_PB30_PCK2 ( ( unsigned int ) AT91C_PIO_PB30 ) /* PMC Programmable Clock Output 2 */ +#define AT91C_PB30_PWM3 ( ( unsigned int ) AT91C_PIO_PB30 ) /* PWM Channel 3 */ +#define AT91C_PIO_PB4 ( ( unsigned int ) 1 << 4 ) /* Pin Controlled by PB4 */ +#define AT91C_PB4_ECRS_ECRSDV ( ( unsigned int ) AT91C_PIO_PB4 ) /* Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */ +#define AT91C_PIO_PB5 ( ( unsigned int ) 1 << 5 ) /* Pin Controlled by PB5 */ +#define AT91C_PB5_ERX0 ( ( unsigned int ) AT91C_PIO_PB5 ) /* Ethernet MAC Receive Data 0 */ +#define AT91C_PIO_PB6 ( ( unsigned int ) 1 << 6 ) /* Pin Controlled by PB6 */ +#define AT91C_PB6_ERX1 ( ( unsigned int ) AT91C_PIO_PB6 ) /* Ethernet MAC Receive Data 1 */ +#define AT91C_PIO_PB7 ( ( unsigned int ) 1 << 7 ) /* Pin Controlled by PB7 */ +#define AT91C_PB7_ERXER ( ( unsigned int ) AT91C_PIO_PB7 ) /* Ethernet MAC Receive Error */ +#define AT91C_PIO_PB8 ( ( unsigned int ) 1 << 8 ) /* Pin Controlled by PB8 */ +#define AT91C_PB8_EMDC ( ( unsigned int ) AT91C_PIO_PB8 ) /* Ethernet MAC Management Data Clock */ +#define AT91C_PIO_PB9 ( ( unsigned int ) 1 << 9 ) /* Pin Controlled by PB9 */ +#define AT91C_PB9_EMDIO ( ( unsigned int ) AT91C_PIO_PB9 ) /* Ethernet MAC Management Data Input/Output */ + +/* ***************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128 */ +/* ***************************************************************************** */ +#define AT91C_ID_FIQ ( ( unsigned int ) 0 ) /* Advanced Interrupt Controller (FIQ) */ +#define AT91C_ID_SYS ( ( unsigned int ) 1 ) /* System Peripheral */ +#define AT91C_ID_PIOA ( ( unsigned int ) 2 ) /* Parallel IO Controller A */ +#define AT91C_ID_PIOB ( ( unsigned int ) 3 ) /* Parallel IO Controller B */ +#define AT91C_ID_SPI0 ( ( unsigned int ) 4 ) /* Serial Peripheral Interface 0 */ +#define AT91C_ID_SPI1 ( ( unsigned int ) 5 ) /* Serial Peripheral Interface 1 */ +#define AT91C_ID_US0 ( ( unsigned int ) 6 ) /* USART 0 */ +#define AT91C_ID_US1 ( ( unsigned int ) 7 ) /* USART 1 */ +#define AT91C_ID_SSC ( ( unsigned int ) 8 ) /* Serial Synchronous Controller */ +#define AT91C_ID_TWI ( ( unsigned int ) 9 ) /* Two-Wire Interface */ +#define AT91C_ID_PWMC ( ( unsigned int ) 10 ) /* PWM Controller */ +#define AT91C_ID_UDP ( ( unsigned int ) 11 ) /* USB Device Port */ +#define AT91C_ID_TC0 ( ( unsigned int ) 12 ) /* Timer Counter 0 */ +#define AT91C_ID_TC1 ( ( unsigned int ) 13 ) /* Timer Counter 1 */ +#define AT91C_ID_TC2 ( ( unsigned int ) 14 ) /* Timer Counter 2 */ +#define AT91C_ID_CAN ( ( unsigned int ) 15 ) /* Control Area Network Controller */ +#define AT91C_ID_EMAC ( ( unsigned int ) 16 ) /* Ethernet MAC */ +#define AT91C_ID_ADC ( ( unsigned int ) 17 ) /* Analog-to-Digital Converter */ +#define AT91C_ID_AES ( ( unsigned int ) 18 ) /* Advanced Encryption Standard 128-bit */ +#define AT91C_ID_TDES ( ( unsigned int ) 19 ) /* Triple Data Encryption Standard */ +#define AT91C_ID_20_Reserved ( ( unsigned int ) 20 ) /* Reserved */ +#define AT91C_ID_21_Reserved ( ( unsigned int ) 21 ) /* Reserved */ +#define AT91C_ID_22_Reserved ( ( unsigned int ) 22 ) /* Reserved */ +#define AT91C_ID_23_Reserved ( ( unsigned int ) 23 ) /* Reserved */ +#define AT91C_ID_24_Reserved ( ( unsigned int ) 24 ) /* Reserved */ +#define AT91C_ID_25_Reserved ( ( unsigned int ) 25 ) /* Reserved */ +#define AT91C_ID_26_Reserved ( ( unsigned int ) 26 ) /* Reserved */ +#define AT91C_ID_27_Reserved ( ( unsigned int ) 27 ) /* Reserved */ +#define AT91C_ID_28_Reserved ( ( unsigned int ) 28 ) /* Reserved */ +#define AT91C_ID_29_Reserved ( ( unsigned int ) 29 ) /* Reserved */ +#define AT91C_ID_IRQ0 ( ( unsigned int ) 30 ) /* Advanced Interrupt Controller (IRQ0) */ +#define AT91C_ID_IRQ1 ( ( unsigned int ) 31 ) /* Advanced Interrupt Controller (IRQ1) */ + +/* ***************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR AT91SAM7X128 */ +/* ***************************************************************************** */ +#define AT91C_BASE_SYS ( ( AT91PS_SYS ) 0xFFFFF000 ) /* (SYS) Base Address */ +#define AT91C_BASE_AIC ( ( AT91PS_AIC ) 0xFFFFF000 ) /* (AIC) Base Address */ +#define AT91C_BASE_PDC_DBGU ( ( AT91PS_PDC ) 0xFFFFF300 ) /* (PDC_DBGU) Base Address */ +#define AT91C_BASE_DBGU ( ( AT91PS_DBGU ) 0xFFFFF200 ) /* (DBGU) Base Address */ +#define AT91C_BASE_PIOA ( ( AT91PS_PIO ) 0xFFFFF400 ) /* (PIOA) Base Address */ +#define AT91C_BASE_PIOB ( ( AT91PS_PIO ) 0xFFFFF600 ) /* (PIOB) Base Address */ +#define AT91C_BASE_CKGR ( ( AT91PS_CKGR ) 0xFFFFFC20 ) /* (CKGR) Base Address */ +#define AT91C_BASE_PMC ( ( AT91PS_PMC ) 0xFFFFFC00 ) /* (PMC) Base Address */ +#define AT91C_BASE_RSTC ( ( AT91PS_RSTC ) 0xFFFFFD00 ) /* (RSTC) Base Address */ +#define AT91C_BASE_RTTC ( ( AT91PS_RTTC ) 0xFFFFFD20 ) /* (RTTC) Base Address */ +#define AT91C_BASE_PITC ( ( AT91PS_PITC ) 0xFFFFFD30 ) /* (PITC) Base Address */ +#define AT91C_BASE_WDTC ( ( AT91PS_WDTC ) 0xFFFFFD40 ) /* (WDTC) Base Address */ +#define AT91C_BASE_VREG ( ( AT91PS_VREG ) 0xFFFFFD60 ) /* (VREG) Base Address */ +#define AT91C_BASE_MC ( ( AT91PS_MC ) 0xFFFFFF00 ) /* (MC) Base Address */ +#define AT91C_BASE_PDC_SPI1 ( ( AT91PS_PDC ) 0xFFFE4100 ) /* (PDC_SPI1) Base Address */ +#define AT91C_BASE_SPI1 ( ( AT91PS_SPI ) 0xFFFE4000 ) /* (SPI1) Base Address */ +#define AT91C_BASE_PDC_SPI0 ( ( AT91PS_PDC ) 0xFFFE0100 ) /* (PDC_SPI0) Base Address */ +#define AT91C_BASE_SPI0 ( ( AT91PS_SPI ) 0xFFFE0000 ) /* (SPI0) Base Address */ +#define AT91C_BASE_PDC_US1 ( ( AT91PS_PDC ) 0xFFFC4100 ) /* (PDC_US1) Base Address */ +#define AT91C_BASE_US1 ( ( AT91PS_USART ) 0xFFFC4000 ) /* (US1) Base Address */ +#define AT91C_BASE_PDC_US0 ( ( AT91PS_PDC ) 0xFFFC0100 ) /* (PDC_US0) Base Address */ +#define AT91C_BASE_US0 ( ( AT91PS_USART ) 0xFFFC0000 ) /* (US0) Base Address */ +#define AT91C_BASE_PDC_SSC ( ( AT91PS_PDC ) 0xFFFD4100 ) /* (PDC_SSC) Base Address */ +#define AT91C_BASE_SSC ( ( AT91PS_SSC ) 0xFFFD4000 ) /* (SSC) Base Address */ +#define AT91C_BASE_TWI ( ( AT91PS_TWI ) 0xFFFB8000 ) /* (TWI) Base Address */ +#define AT91C_BASE_PWMC_CH3 ( ( AT91PS_PWMC_CH ) 0xFFFCC260 ) /* (PWMC_CH3) Base Address */ +#define AT91C_BASE_PWMC_CH2 ( ( AT91PS_PWMC_CH ) 0xFFFCC240 ) /* (PWMC_CH2) Base Address */ +#define AT91C_BASE_PWMC_CH1 ( ( AT91PS_PWMC_CH ) 0xFFFCC220 ) /* (PWMC_CH1) Base Address */ +#define AT91C_BASE_PWMC_CH0 ( ( AT91PS_PWMC_CH ) 0xFFFCC200 ) /* (PWMC_CH0) Base Address */ +#define AT91C_BASE_PWMC ( ( AT91PS_PWMC ) 0xFFFCC000 ) /* (PWMC) Base Address */ +#define AT91C_BASE_UDP ( ( AT91PS_UDP ) 0xFFFB0000 ) /* (UDP) Base Address */ +#define AT91C_BASE_TC0 ( ( AT91PS_TC ) 0xFFFA0000 ) /* (TC0) Base Address */ +#define AT91C_BASE_TC1 ( ( AT91PS_TC ) 0xFFFA0040 ) /* (TC1) Base Address */ +#define AT91C_BASE_TC2 ( ( AT91PS_TC ) 0xFFFA0080 ) /* (TC2) Base Address */ +#define AT91C_BASE_TCB ( ( AT91PS_TCB ) 0xFFFA0000 ) /* (TCB) Base Address */ +#define AT91C_BASE_CAN_MB0 ( ( AT91PS_CAN_MB ) 0xFFFD0200 ) /* (CAN_MB0) Base Address */ +#define AT91C_BASE_CAN_MB1 ( ( AT91PS_CAN_MB ) 0xFFFD0220 ) /* (CAN_MB1) Base Address */ +#define AT91C_BASE_CAN_MB2 ( ( AT91PS_CAN_MB ) 0xFFFD0240 ) /* (CAN_MB2) Base Address */ +#define AT91C_BASE_CAN_MB3 ( ( AT91PS_CAN_MB ) 0xFFFD0260 ) /* (CAN_MB3) Base Address */ +#define AT91C_BASE_CAN_MB4 ( ( AT91PS_CAN_MB ) 0xFFFD0280 ) /* (CAN_MB4) Base Address */ +#define AT91C_BASE_CAN_MB5 ( ( AT91PS_CAN_MB ) 0xFFFD02A0 ) /* (CAN_MB5) Base Address */ +#define AT91C_BASE_CAN_MB6 ( ( AT91PS_CAN_MB ) 0xFFFD02C0 ) /* (CAN_MB6) Base Address */ +#define AT91C_BASE_CAN_MB7 ( ( AT91PS_CAN_MB ) 0xFFFD02E0 ) /* (CAN_MB7) Base Address */ +#define AT91C_BASE_CAN ( ( AT91PS_CAN ) 0xFFFD0000 ) /* (CAN) Base Address */ +#define AT91C_BASE_EMAC ( ( AT91PS_EMAC ) 0xFFFDC000 ) /* (EMAC) Base Address */ +#define AT91C_BASE_PDC_ADC ( ( AT91PS_PDC ) 0xFFFD8100 ) /* (PDC_ADC) Base Address */ +#define AT91C_BASE_ADC ( ( AT91PS_ADC ) 0xFFFD8000 ) /* (ADC) Base Address */ +#define AT91C_BASE_PDC_AES ( ( AT91PS_PDC ) 0xFFFA4100 ) /* (PDC_AES) Base Address */ +#define AT91C_BASE_AES ( ( AT91PS_AES ) 0xFFFA4000 ) /* (AES) Base Address */ +#define AT91C_BASE_PDC_TDES ( ( AT91PS_PDC ) 0xFFFA8100 ) /* (PDC_TDES) Base Address */ +#define AT91C_BASE_TDES ( ( AT91PS_TDES ) 0xFFFA8000 ) /* (TDES) Base Address */ + +/* ***************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128 */ +/* ***************************************************************************** */ +#define AT91C_ISRAM ( ( char * ) 0x00200000 ) /* Internal SRAM base address */ +#define AT91C_ISRAM_SIZE ( ( unsigned int ) 0x00008000 ) /* Internal SRAM size in byte (32 Kbyte) */ +#define AT91C_IFLASH ( ( char * ) 0x00100000 ) /* Internal ROM base address */ +#define AT91C_IFLASH_SIZE ( ( unsigned int ) 0x00020000 ) /* Internal ROM size in byte (128 Kbyte) */ + +#endif /* ifndef AT91SAM7X128_H */ diff --git a/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h b/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h new file mode 100644 index 000000000..78ea37595 --- /dev/null +++ b/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h @@ -0,0 +1,2444 @@ +/* ---------------------------------------------------------------------------- */ +/* ATMEL Microcontroller Software Support - ROUSSET - */ +/* ---------------------------------------------------------------------------- */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ +/* File Name : AT91SAM7X128.h */ +/* Object : AT91SAM7X128 definitions */ +/* Generated : AT91 SW Application Group 05/20/2005 (16:22:23) */ +/* */ +/* CVS Reference : /AT91SAM7X128.pl/1.14/Tue May 10 12:12:05 2005// */ +/* CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// */ +/* CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// */ +/* CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// */ +/* CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// */ +/* CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// */ +/* CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// */ +/* CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// */ +/* CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// */ +/* CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// */ +/* CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// */ +/* CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// */ +/* CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// */ +/* CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// */ +/* CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// */ +/* CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// */ +/* CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// */ +/* CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// */ +/* CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// */ +/* CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// */ +/* CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// */ +/* CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// */ +/* CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// */ +/* CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// */ +/* CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// */ +/* ---------------------------------------------------------------------------- */ + +/* Hardware register definition */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR System Peripherals */ +/* ***************************************************************************** */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Advanced Interrupt Controller */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_AIC structure *** */ +#define AIC_SMR ( 0 ) /* Source Mode Register */ +#define AIC_SVR ( 128 ) /* Source Vector Register */ +#define AIC_IVR ( 256 ) /* IRQ Vector Register */ +#define AIC_FVR ( 260 ) /* FIQ Vector Register */ +#define AIC_ISR ( 264 ) /* Interrupt Status Register */ +#define AIC_IPR ( 268 ) /* Interrupt Pending Register */ +#define AIC_IMR ( 272 ) /* Interrupt Mask Register */ +#define AIC_CISR ( 276 ) /* Core Interrupt Status Register */ +#define AIC_IECR ( 288 ) /* Interrupt Enable Command Register */ +#define AIC_IDCR ( 292 ) /* Interrupt Disable Command Register */ +#define AIC_ICCR ( 296 ) /* Interrupt Clear Command Register */ +#define AIC_ISCR ( 300 ) /* Interrupt Set Command Register */ +#define AIC_EOICR ( 304 ) /* End of Interrupt Command Register */ +#define AIC_SPU ( 308 ) /* Spurious Vector Register */ +#define AIC_DCR ( 312 ) /* Debug Control Register (Protect) */ +#define AIC_FFER ( 320 ) /* Fast Forcing Enable Register */ +#define AIC_FFDR ( 324 ) /* Fast Forcing Disable Register */ +#define AIC_FFSR ( 328 ) /* Fast Forcing Status Register */ +/* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */ +#define AT91C_AIC_PRIOR ( 0x7 << 0 ) /* (AIC) Priority Level */ +#define AT91C_AIC_PRIOR_LOWEST ( 0x0 ) /* (AIC) Lowest priority level */ +#define AT91C_AIC_PRIOR_HIGHEST ( 0x7 ) /* (AIC) Highest priority level */ +#define AT91C_AIC_SRCTYPE ( 0x3 << 5 ) /* (AIC) Interrupt Source Type */ +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ( 0x0 << 5 ) /* (AIC) Internal Sources Code Label High-level Sensitive */ +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ( 0x0 << 5 ) /* (AIC) External Sources Code Label Low-level Sensitive */ +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ( 0x1 << 5 ) /* (AIC) Internal Sources Code Label Positive Edge triggered */ +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ( 0x1 << 5 ) /* (AIC) External Sources Code Label Negative Edge triggered */ +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ( 0x2 << 5 ) /* (AIC) Internal Or External Sources Code Label High-level Sensitive */ +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ( 0x3 << 5 ) /* (AIC) Internal Or External Sources Code Label Positive Edge triggered */ +/* -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- */ +#define AT91C_AIC_NFIQ ( 0x1 << 0 ) /* (AIC) NFIQ Status */ +#define AT91C_AIC_NIRQ ( 0x1 << 1 ) /* (AIC) NIRQ Status */ +/* -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- */ +#define AT91C_AIC_DCR_PROT ( 0x1 << 0 ) /* (AIC) Protection Mode */ +#define AT91C_AIC_DCR_GMSK ( 0x1 << 1 ) /* (AIC) General Mask */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Peripheral DMA Controller */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_PDC structure *** */ +#define PDC_RPR ( 0 ) /* Receive Pointer Register */ +#define PDC_RCR ( 4 ) /* Receive Counter Register */ +#define PDC_TPR ( 8 ) /* Transmit Pointer Register */ +#define PDC_TCR ( 12 ) /* Transmit Counter Register */ +#define PDC_RNPR ( 16 ) /* Receive Next Pointer Register */ +#define PDC_RNCR ( 20 ) /* Receive Next Counter Register */ +#define PDC_TNPR ( 24 ) /* Transmit Next Pointer Register */ +#define PDC_TNCR ( 28 ) /* Transmit Next Counter Register */ +#define PDC_PTCR ( 32 ) /* PDC Transfer Control Register */ +#define PDC_PTSR ( 36 ) /* PDC Transfer Status Register */ +/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */ +#define AT91C_PDC_RXTEN ( 0x1 << 0 ) /* (PDC) Receiver Transfer Enable */ +#define AT91C_PDC_RXTDIS ( 0x1 << 1 ) /* (PDC) Receiver Transfer Disable */ +#define AT91C_PDC_TXTEN ( 0x1 << 8 ) /* (PDC) Transmitter Transfer Enable */ +#define AT91C_PDC_TXTDIS ( 0x1 << 9 ) /* (PDC) Transmitter Transfer Disable */ +/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Debug Unit */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_DBGU structure *** */ +#define DBGU_CR ( 0 ) /* Control Register */ +#define DBGU_MR ( 4 ) /* Mode Register */ +#define DBGU_IER ( 8 ) /* Interrupt Enable Register */ +#define DBGU_IDR ( 12 ) /* Interrupt Disable Register */ +#define DBGU_IMR ( 16 ) /* Interrupt Mask Register */ +#define DBGU_CSR ( 20 ) /* Channel Status Register */ +#define DBGU_RHR ( 24 ) /* Receiver Holding Register */ +#define DBGU_THR ( 28 ) /* Transmitter Holding Register */ +#define DBGU_BRGR ( 32 ) /* Baud Rate Generator Register */ +#define DBGU_CIDR ( 64 ) /* Chip ID Register */ +#define DBGU_EXID ( 68 ) /* Chip ID Extension Register */ +#define DBGU_FNTR ( 72 ) /* Force NTRST Register */ +#define DBGU_RPR ( 256 ) /* Receive Pointer Register */ +#define DBGU_RCR ( 260 ) /* Receive Counter Register */ +#define DBGU_TPR ( 264 ) /* Transmit Pointer Register */ +#define DBGU_TCR ( 268 ) /* Transmit Counter Register */ +#define DBGU_RNPR ( 272 ) /* Receive Next Pointer Register */ +#define DBGU_RNCR ( 276 ) /* Receive Next Counter Register */ +#define DBGU_TNPR ( 280 ) /* Transmit Next Pointer Register */ +#define DBGU_TNCR ( 284 ) /* Transmit Next Counter Register */ +#define DBGU_PTCR ( 288 ) /* PDC Transfer Control Register */ +#define DBGU_PTSR ( 292 ) /* PDC Transfer Status Register */ +/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */ +#define AT91C_US_RSTRX ( 0x1 << 2 ) /* (DBGU) Reset Receiver */ +#define AT91C_US_RSTTX ( 0x1 << 3 ) /* (DBGU) Reset Transmitter */ +#define AT91C_US_RXEN ( 0x1 << 4 ) /* (DBGU) Receiver Enable */ +#define AT91C_US_RXDIS ( 0x1 << 5 ) /* (DBGU) Receiver Disable */ +#define AT91C_US_TXEN ( 0x1 << 6 ) /* (DBGU) Transmitter Enable */ +#define AT91C_US_TXDIS ( 0x1 << 7 ) /* (DBGU) Transmitter Disable */ +#define AT91C_US_RSTSTA ( 0x1 << 8 ) /* (DBGU) Reset Status Bits */ +/* -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- */ +#define AT91C_US_PAR ( 0x7 << 9 ) /* (DBGU) Parity type */ +#define AT91C_US_PAR_EVEN ( 0x0 << 9 ) /* (DBGU) Even Parity */ +#define AT91C_US_PAR_ODD ( 0x1 << 9 ) /* (DBGU) Odd Parity */ +#define AT91C_US_PAR_SPACE ( 0x2 << 9 ) /* (DBGU) Parity forced to 0 (Space) */ +#define AT91C_US_PAR_MARK ( 0x3 << 9 ) /* (DBGU) Parity forced to 1 (Mark) */ +#define AT91C_US_PAR_NONE ( 0x4 << 9 ) /* (DBGU) No Parity */ +#define AT91C_US_PAR_MULTI_DROP ( 0x6 << 9 ) /* (DBGU) Multi-drop mode */ +#define AT91C_US_CHMODE ( 0x3 << 14 ) /* (DBGU) Channel Mode */ +#define AT91C_US_CHMODE_NORMAL ( 0x0 << 14 ) /* (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. */ +#define AT91C_US_CHMODE_AUTO ( 0x1 << 14 ) /* (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. */ +#define AT91C_US_CHMODE_LOCAL ( 0x2 << 14 ) /* (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. */ +#define AT91C_US_CHMODE_REMOTE ( 0x3 << 14 ) /* (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. */ +/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ +#define AT91C_US_RXRDY ( 0x1 << 0 ) /* (DBGU) RXRDY Interrupt */ +#define AT91C_US_TXRDY ( 0x1 << 1 ) /* (DBGU) TXRDY Interrupt */ +#define AT91C_US_ENDRX ( 0x1 << 3 ) /* (DBGU) End of Receive Transfer Interrupt */ +#define AT91C_US_ENDTX ( 0x1 << 4 ) /* (DBGU) End of Transmit Interrupt */ +#define AT91C_US_OVRE ( 0x1 << 5 ) /* (DBGU) Overrun Interrupt */ +#define AT91C_US_FRAME ( 0x1 << 6 ) /* (DBGU) Framing Error Interrupt */ +#define AT91C_US_PARE ( 0x1 << 7 ) /* (DBGU) Parity Error Interrupt */ +#define AT91C_US_TXEMPTY ( 0x1 << 9 ) /* (DBGU) TXEMPTY Interrupt */ +#define AT91C_US_TXBUFE ( 0x1 << 11 ) /* (DBGU) TXBUFE Interrupt */ +#define AT91C_US_RXBUFF ( 0x1 << 12 ) /* (DBGU) RXBUFF Interrupt */ +#define AT91C_US_COMM_TX ( 0x1 << 30 ) /* (DBGU) COMM_TX Interrupt */ +#define AT91C_US_COMM_RX ( 0x1 << 31 ) /* (DBGU) COMM_RX Interrupt */ +/* -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- */ +/* -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- */ +/* -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- */ +/* -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- */ +#define AT91C_US_FORCE_NTRST ( 0x1 << 0 ) /* (DBGU) Force NTRST in JTAG */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Parallel Input Output Controller */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_PIO structure *** */ +#define PIO_PER ( 0 ) /* PIO Enable Register */ +#define PIO_PDR ( 4 ) /* PIO Disable Register */ +#define PIO_PSR ( 8 ) /* PIO Status Register */ +#define PIO_OER ( 16 ) /* Output Enable Register */ +#define PIO_ODR ( 20 ) /* Output Disable Registerr */ +#define PIO_OSR ( 24 ) /* Output Status Register */ +#define PIO_IFER ( 32 ) /* Input Filter Enable Register */ +#define PIO_IFDR ( 36 ) /* Input Filter Disable Register */ +#define PIO_IFSR ( 40 ) /* Input Filter Status Register */ +#define PIO_SODR ( 48 ) /* Set Output Data Register */ +#define PIO_CODR ( 52 ) /* Clear Output Data Register */ +#define PIO_ODSR ( 56 ) /* Output Data Status Register */ +#define PIO_PDSR ( 60 ) /* Pin Data Status Register */ +#define PIO_IER ( 64 ) /* Interrupt Enable Register */ +#define PIO_IDR ( 68 ) /* Interrupt Disable Register */ +#define PIO_IMR ( 72 ) /* Interrupt Mask Register */ +#define PIO_ISR ( 76 ) /* Interrupt Status Register */ +#define PIO_MDER ( 80 ) /* Multi-driver Enable Register */ +#define PIO_MDDR ( 84 ) /* Multi-driver Disable Register */ +#define PIO_MDSR ( 88 ) /* Multi-driver Status Register */ +#define PIO_PPUDR ( 96 ) /* Pull-up Disable Register */ +#define PIO_PPUER ( 100 ) /* Pull-up Enable Register */ +#define PIO_PPUSR ( 104 ) /* Pull-up Status Register */ +#define PIO_ASR ( 112 ) /* Select A Register */ +#define PIO_BSR ( 116 ) /* Select B Register */ +#define PIO_ABSR ( 120 ) /* AB Select Status Register */ +#define PIO_OWER ( 160 ) /* Output Write Enable Register */ +#define PIO_OWDR ( 164 ) /* Output Write Disable Register */ +#define PIO_OWSR ( 168 ) /* Output Write Status Register */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Clock Generator Controller */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_CKGR structure *** */ +#define CKGR_MOR ( 0 ) /* Main Oscillator Register */ +#define CKGR_MCFR ( 4 ) /* Main Clock Frequency Register */ +#define CKGR_PLLR ( 12 ) /* PLL Register */ +/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */ +#define AT91C_CKGR_MOSCEN ( 0x1 << 0 ) /* (CKGR) Main Oscillator Enable */ +#define AT91C_CKGR_OSCBYPASS ( 0x1 << 1 ) /* (CKGR) Main Oscillator Bypass */ +#define AT91C_CKGR_OSCOUNT ( 0xFF << 8 ) /* (CKGR) Main Oscillator Start-up Time */ +/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */ +#define AT91C_CKGR_MAINF ( 0xFFFF << 0 ) /* (CKGR) Main Clock Frequency */ +#define AT91C_CKGR_MAINRDY ( 0x1 << 16 ) /* (CKGR) Main Clock Ready */ +/* -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- */ +#define AT91C_CKGR_DIV ( 0xFF << 0 ) /* (CKGR) Divider Selected */ +#define AT91C_CKGR_DIV_0 ( 0x0 ) /* (CKGR) Divider output is 0 */ +#define AT91C_CKGR_DIV_BYPASS ( 0x1 ) /* (CKGR) Divider is bypassed */ +#define AT91C_CKGR_PLLCOUNT ( 0x3F << 8 ) /* (CKGR) PLL Counter */ +#define AT91C_CKGR_OUT ( 0x3 << 14 ) /* (CKGR) PLL Output Frequency Range */ +#define AT91C_CKGR_OUT_0 ( 0x0 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_1 ( 0x1 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_2 ( 0x2 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_3 ( 0x3 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_MUL ( 0x7FF << 16 ) /* (CKGR) PLL Multiplier */ +#define AT91C_CKGR_USBDIV ( 0x3 << 28 ) /* (CKGR) Divider for USB Clocks */ +#define AT91C_CKGR_USBDIV_0 ( 0x0 << 28 ) /* (CKGR) Divider output is PLL clock output */ +#define AT91C_CKGR_USBDIV_1 ( 0x1 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 2 */ +#define AT91C_CKGR_USBDIV_2 ( 0x2 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 4 */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Power Management Controller */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_PMC structure *** */ +#define PMC_SCER ( 0 ) /* System Clock Enable Register */ +#define PMC_SCDR ( 4 ) /* System Clock Disable Register */ +#define PMC_SCSR ( 8 ) /* System Clock Status Register */ +#define PMC_PCER ( 16 ) /* Peripheral Clock Enable Register */ +#define PMC_PCDR ( 20 ) /* Peripheral Clock Disable Register */ +#define PMC_PCSR ( 24 ) /* Peripheral Clock Status Register */ +#define PMC_MOR ( 32 ) /* Main Oscillator Register */ +#define PMC_MCFR ( 36 ) /* Main Clock Frequency Register */ +#define PMC_PLLR ( 44 ) /* PLL Register */ +#define PMC_MCKR ( 48 ) /* Master Clock Register */ +#define PMC_PCKR ( 64 ) /* Programmable Clock Register */ +#define PMC_IER ( 96 ) /* Interrupt Enable Register */ +#define PMC_IDR ( 100 ) /* Interrupt Disable Register */ +#define PMC_SR ( 104 ) /* Status Register */ +#define PMC_IMR ( 108 ) /* Interrupt Mask Register */ +/* -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- */ +#define AT91C_PMC_PCK ( 0x1 << 0 ) /* (PMC) Processor Clock */ +#define AT91C_PMC_UDP ( 0x1 << 7 ) /* (PMC) USB Device Port Clock */ +#define AT91C_PMC_PCK0 ( 0x1 << 8 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK1 ( 0x1 << 9 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK2 ( 0x1 << 10 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK3 ( 0x1 << 11 ) /* (PMC) Programmable Clock Output */ +/* -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- */ +/* -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- */ +/* -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- */ +/* -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- */ +/* -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- */ +/* -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */ +#define AT91C_PMC_CSS ( 0x3 << 0 ) /* (PMC) Programmable Clock Selection */ +#define AT91C_PMC_CSS_SLOW_CLK ( 0x0 ) /* (PMC) Slow Clock is selected */ +#define AT91C_PMC_CSS_MAIN_CLK ( 0x1 ) /* (PMC) Main Clock is selected */ +#define AT91C_PMC_CSS_PLL_CLK ( 0x3 ) /* (PMC) Clock from PLL is selected */ +#define AT91C_PMC_PRES ( 0x7 << 2 ) /* (PMC) Programmable Clock Prescaler */ +#define AT91C_PMC_PRES_CLK ( 0x0 << 2 ) /* (PMC) Selected clock */ +#define AT91C_PMC_PRES_CLK_2 ( 0x1 << 2 ) /* (PMC) Selected clock divided by 2 */ +#define AT91C_PMC_PRES_CLK_4 ( 0x2 << 2 ) /* (PMC) Selected clock divided by 4 */ +#define AT91C_PMC_PRES_CLK_8 ( 0x3 << 2 ) /* (PMC) Selected clock divided by 8 */ +#define AT91C_PMC_PRES_CLK_16 ( 0x4 << 2 ) /* (PMC) Selected clock divided by 16 */ +#define AT91C_PMC_PRES_CLK_32 ( 0x5 << 2 ) /* (PMC) Selected clock divided by 32 */ +#define AT91C_PMC_PRES_CLK_64 ( 0x6 << 2 ) /* (PMC) Selected clock divided by 64 */ +/* -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- */ +/* -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- */ +#define AT91C_PMC_MOSCS ( 0x1 << 0 ) /* (PMC) MOSC Status/Enable/Disable/Mask */ +#define AT91C_PMC_LOCK ( 0x1 << 2 ) /* (PMC) PLL Status/Enable/Disable/Mask */ +#define AT91C_PMC_MCKRDY ( 0x1 << 3 ) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK0RDY ( 0x1 << 8 ) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK1RDY ( 0x1 << 9 ) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK2RDY ( 0x1 << 10 ) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK3RDY ( 0x1 << 11 ) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */ +/* -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */ +/* -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- */ +/* -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Reset Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_RSTC structure *** */ +#define RSTC_RCR ( 0 ) /* Reset Control Register */ +#define RSTC_RSR ( 4 ) /* Reset Status Register */ +#define RSTC_RMR ( 8 ) /* Reset Mode Register */ +/* -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- */ +#define AT91C_RSTC_PROCRST ( 0x1 << 0 ) /* (RSTC) Processor Reset */ +#define AT91C_RSTC_PERRST ( 0x1 << 2 ) /* (RSTC) Peripheral Reset */ +#define AT91C_RSTC_EXTRST ( 0x1 << 3 ) /* (RSTC) External Reset */ +#define AT91C_RSTC_KEY ( 0xFF << 24 ) /* (RSTC) Password */ +/* -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- */ +#define AT91C_RSTC_URSTS ( 0x1 << 0 ) /* (RSTC) User Reset Status */ +#define AT91C_RSTC_BODSTS ( 0x1 << 1 ) /* (RSTC) Brownout Detection Status */ +#define AT91C_RSTC_RSTTYP ( 0x7 << 8 ) /* (RSTC) Reset Type */ +#define AT91C_RSTC_RSTTYP_POWERUP ( 0x0 << 8 ) /* (RSTC) Power-up Reset. VDDCORE rising. */ +#define AT91C_RSTC_RSTTYP_WAKEUP ( 0x1 << 8 ) /* (RSTC) WakeUp Reset. VDDCORE rising. */ +#define AT91C_RSTC_RSTTYP_WATCHDOG ( 0x2 << 8 ) /* (RSTC) Watchdog Reset. Watchdog overflow occurred. */ +#define AT91C_RSTC_RSTTYP_SOFTWARE ( 0x3 << 8 ) /* (RSTC) Software Reset. Processor reset required by the software. */ +#define AT91C_RSTC_RSTTYP_USER ( 0x4 << 8 ) /* (RSTC) User Reset. NRST pin detected low. */ +#define AT91C_RSTC_RSTTYP_BROWNOUT ( 0x5 << 8 ) /* (RSTC) Brownout Reset occurred. */ +#define AT91C_RSTC_NRSTL ( 0x1 << 16 ) /* (RSTC) NRST pin level */ +#define AT91C_RSTC_SRCMP ( 0x1 << 17 ) /* (RSTC) Software Reset Command in Progress. */ +/* -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- */ +#define AT91C_RSTC_URSTEN ( 0x1 << 0 ) /* (RSTC) User Reset Enable */ +#define AT91C_RSTC_URSTIEN ( 0x1 << 4 ) /* (RSTC) User Reset Interrupt Enable */ +#define AT91C_RSTC_ERSTL ( 0xF << 8 ) /* (RSTC) User Reset Enable */ +#define AT91C_RSTC_BODIEN ( 0x1 << 16 ) /* (RSTC) Brownout Detection Interrupt Enable */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_RTTC structure *** */ +#define RTTC_RTMR ( 0 ) /* Real-time Mode Register */ +#define RTTC_RTAR ( 4 ) /* Real-time Alarm Register */ +#define RTTC_RTVR ( 8 ) /* Real-time Value Register */ +#define RTTC_RTSR ( 12 ) /* Real-time Status Register */ +/* -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- */ +#define AT91C_RTTC_RTPRES ( 0xFFFF << 0 ) /* (RTTC) Real-time Timer Prescaler Value */ +#define AT91C_RTTC_ALMIEN ( 0x1 << 16 ) /* (RTTC) Alarm Interrupt Enable */ +#define AT91C_RTTC_RTTINCIEN ( 0x1 << 17 ) /* (RTTC) Real Time Timer Increment Interrupt Enable */ +#define AT91C_RTTC_RTTRST ( 0x1 << 18 ) /* (RTTC) Real Time Timer Restart */ +/* -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- */ +#define AT91C_RTTC_ALMV ( 0x0 << 0 ) /* (RTTC) Alarm Value */ +/* -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- */ +#define AT91C_RTTC_CRTV ( 0x0 << 0 ) /* (RTTC) Current Real-time Value */ +/* -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- */ +#define AT91C_RTTC_ALMS ( 0x1 << 0 ) /* (RTTC) Real-time Alarm Status */ +#define AT91C_RTTC_RTTINC ( 0x1 << 1 ) /* (RTTC) Real-time Timer Increment */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_PITC structure *** */ +#define PITC_PIMR ( 0 ) /* Period Interval Mode Register */ +#define PITC_PISR ( 4 ) /* Period Interval Status Register */ +#define PITC_PIVR ( 8 ) /* Period Interval Value Register */ +#define PITC_PIIR ( 12 ) /* Period Interval Image Register */ +/* -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- */ +#define AT91C_PITC_PIV ( 0xFFFFF << 0 ) /* (PITC) Periodic Interval Value */ +#define AT91C_PITC_PITEN ( 0x1 << 24 ) /* (PITC) Periodic Interval Timer Enabled */ +#define AT91C_PITC_PITIEN ( 0x1 << 25 ) /* (PITC) Periodic Interval Timer Interrupt Enable */ +/* -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- */ +#define AT91C_PITC_PITS ( 0x1 << 0 ) /* (PITC) Periodic Interval Timer Status */ +/* -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- */ +#define AT91C_PITC_CPIV ( 0xFFFFF << 0 ) /* (PITC) Current Periodic Interval Value */ +#define AT91C_PITC_PICNT ( 0xFFF << 20 ) /* (PITC) Periodic Interval Counter */ +/* -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_WDTC structure *** */ +#define WDTC_WDCR ( 0 ) /* Watchdog Control Register */ +#define WDTC_WDMR ( 4 ) /* Watchdog Mode Register */ +#define WDTC_WDSR ( 8 ) /* Watchdog Status Register */ +/* -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- */ +#define AT91C_WDTC_WDRSTT ( 0x1 << 0 ) /* (WDTC) Watchdog Restart */ +#define AT91C_WDTC_KEY ( 0xFF << 24 ) /* (WDTC) Watchdog KEY Password */ +/* -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */ +#define AT91C_WDTC_WDV ( 0xFFF << 0 ) /* (WDTC) Watchdog Timer Restart */ +#define AT91C_WDTC_WDFIEN ( 0x1 << 12 ) /* (WDTC) Watchdog Fault Interrupt Enable */ +#define AT91C_WDTC_WDRSTEN ( 0x1 << 13 ) /* (WDTC) Watchdog Reset Enable */ +#define AT91C_WDTC_WDRPROC ( 0x1 << 14 ) /* (WDTC) Watchdog Timer Restart */ +#define AT91C_WDTC_WDDIS ( 0x1 << 15 ) /* (WDTC) Watchdog Disable */ +#define AT91C_WDTC_WDD ( 0xFFF << 16 ) /* (WDTC) Watchdog Delta Value */ +#define AT91C_WDTC_WDDBGHLT ( 0x1 << 28 ) /* (WDTC) Watchdog Debug Halt */ +#define AT91C_WDTC_WDIDLEHLT ( 0x1 << 29 ) /* (WDTC) Watchdog Idle Halt */ +/* -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- */ +#define AT91C_WDTC_WDUNF ( 0x1 << 0 ) /* (WDTC) Watchdog Underflow */ +#define AT91C_WDTC_WDERR ( 0x1 << 1 ) /* (WDTC) Watchdog Error */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_VREG structure *** */ +#define VREG_MR ( 0 ) /* Voltage Regulator Mode Register */ +/* -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- */ +#define AT91C_VREG_PSTDBY ( 0x1 << 0 ) /* (VREG) Voltage Regulator Power Standby Mode */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Memory Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_MC structure *** */ +#define MC_RCR ( 0 ) /* MC Remap Control Register */ +#define MC_ASR ( 4 ) /* MC Abort Status Register */ +#define MC_AASR ( 8 ) /* MC Abort Address Status Register */ +#define MC_FMR ( 96 ) /* MC Flash Mode Register */ +#define MC_FCR ( 100 ) /* MC Flash Command Register */ +#define MC_FSR ( 104 ) /* MC Flash Status Register */ +/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */ +#define AT91C_MC_RCB ( 0x1 << 0 ) /* (MC) Remap Command Bit */ +/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */ +#define AT91C_MC_UNDADD ( 0x1 << 0 ) /* (MC) Undefined Address Abort Status */ +#define AT91C_MC_MISADD ( 0x1 << 1 ) /* (MC) Misaligned Address Abort Status */ +#define AT91C_MC_ABTSZ ( 0x3 << 8 ) /* (MC) Abort Size Status */ +#define AT91C_MC_ABTSZ_BYTE ( 0x0 << 8 ) /* (MC) Byte */ +#define AT91C_MC_ABTSZ_HWORD ( 0x1 << 8 ) /* (MC) Half-word */ +#define AT91C_MC_ABTSZ_WORD ( 0x2 << 8 ) /* (MC) Word */ +#define AT91C_MC_ABTTYP ( 0x3 << 10 ) /* (MC) Abort Type Status */ +#define AT91C_MC_ABTTYP_DATAR ( 0x0 << 10 ) /* (MC) Data Read */ +#define AT91C_MC_ABTTYP_DATAW ( 0x1 << 10 ) /* (MC) Data Write */ +#define AT91C_MC_ABTTYP_FETCH ( 0x2 << 10 ) /* (MC) Code Fetch */ +#define AT91C_MC_MST0 ( 0x1 << 16 ) /* (MC) Master 0 Abort Source */ +#define AT91C_MC_MST1 ( 0x1 << 17 ) /* (MC) Master 1 Abort Source */ +#define AT91C_MC_SVMST0 ( 0x1 << 24 ) /* (MC) Saved Master 0 Abort Source */ +#define AT91C_MC_SVMST1 ( 0x1 << 25 ) /* (MC) Saved Master 1 Abort Source */ +/* -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- */ +#define AT91C_MC_FRDY ( 0x1 << 0 ) /* (MC) Flash Ready */ +#define AT91C_MC_LOCKE ( 0x1 << 2 ) /* (MC) Lock Error */ +#define AT91C_MC_PROGE ( 0x1 << 3 ) /* (MC) Programming Error */ +#define AT91C_MC_NEBP ( 0x1 << 7 ) /* (MC) No Erase Before Programming */ +#define AT91C_MC_FWS ( 0x3 << 8 ) /* (MC) Flash Wait State */ +#define AT91C_MC_FWS_0FWS ( 0x0 << 8 ) /* (MC) 1 cycle for Read, 2 for Write operations */ +#define AT91C_MC_FWS_1FWS ( 0x1 << 8 ) /* (MC) 2 cycles for Read, 3 for Write operations */ +#define AT91C_MC_FWS_2FWS ( 0x2 << 8 ) /* (MC) 3 cycles for Read, 4 for Write operations */ +#define AT91C_MC_FWS_3FWS ( 0x3 << 8 ) /* (MC) 4 cycles for Read, 4 for Write operations */ +#define AT91C_MC_FMCN ( 0xFF << 16 ) /* (MC) Flash Microsecond Cycle Number */ +/* -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- */ +#define AT91C_MC_FCMD ( 0xF << 0 ) /* (MC) Flash Command */ +#define AT91C_MC_FCMD_START_PROG ( 0x1 ) /* (MC) Starts the programming of th epage specified by PAGEN. */ +#define AT91C_MC_FCMD_LOCK ( 0x2 ) /* (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */ +#define AT91C_MC_FCMD_PROG_AND_LOCK ( 0x3 ) /* (MC) The lock sequence automatically happens after the programming sequence is completed. */ +#define AT91C_MC_FCMD_UNLOCK ( 0x4 ) /* (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */ +#define AT91C_MC_FCMD_ERASE_ALL ( 0x8 ) /* (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. */ +#define AT91C_MC_FCMD_SET_GP_NVM ( 0xB ) /* (MC) Set General Purpose NVM bits. */ +#define AT91C_MC_FCMD_CLR_GP_NVM ( 0xD ) /* (MC) Clear General Purpose NVM bits. */ +#define AT91C_MC_FCMD_SET_SECURITY ( 0xF ) /* (MC) Set Security Bit. */ +#define AT91C_MC_PAGEN ( 0x3FF << 8 ) /* (MC) Page Number */ +#define AT91C_MC_KEY ( 0xFF << 24 ) /* (MC) Writing Protect Key */ +/* -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- */ +#define AT91C_MC_SECURITY ( 0x1 << 4 ) /* (MC) Security Bit Status */ +#define AT91C_MC_GPNVM0 ( 0x1 << 8 ) /* (MC) Sector 0 Lock Status */ +#define AT91C_MC_GPNVM1 ( 0x1 << 9 ) /* (MC) Sector 1 Lock Status */ +#define AT91C_MC_GPNVM2 ( 0x1 << 10 ) /* (MC) Sector 2 Lock Status */ +#define AT91C_MC_GPNVM3 ( 0x1 << 11 ) /* (MC) Sector 3 Lock Status */ +#define AT91C_MC_GPNVM4 ( 0x1 << 12 ) /* (MC) Sector 4 Lock Status */ +#define AT91C_MC_GPNVM5 ( 0x1 << 13 ) /* (MC) Sector 5 Lock Status */ +#define AT91C_MC_GPNVM6 ( 0x1 << 14 ) /* (MC) Sector 6 Lock Status */ +#define AT91C_MC_GPNVM7 ( 0x1 << 15 ) /* (MC) Sector 7 Lock Status */ +#define AT91C_MC_LOCKS0 ( 0x1 << 16 ) /* (MC) Sector 0 Lock Status */ +#define AT91C_MC_LOCKS1 ( 0x1 << 17 ) /* (MC) Sector 1 Lock Status */ +#define AT91C_MC_LOCKS2 ( 0x1 << 18 ) /* (MC) Sector 2 Lock Status */ +#define AT91C_MC_LOCKS3 ( 0x1 << 19 ) /* (MC) Sector 3 Lock Status */ +#define AT91C_MC_LOCKS4 ( 0x1 << 20 ) /* (MC) Sector 4 Lock Status */ +#define AT91C_MC_LOCKS5 ( 0x1 << 21 ) /* (MC) Sector 5 Lock Status */ +#define AT91C_MC_LOCKS6 ( 0x1 << 22 ) /* (MC) Sector 6 Lock Status */ +#define AT91C_MC_LOCKS7 ( 0x1 << 23 ) /* (MC) Sector 7 Lock Status */ +#define AT91C_MC_LOCKS8 ( 0x1 << 24 ) /* (MC) Sector 8 Lock Status */ +#define AT91C_MC_LOCKS9 ( 0x1 << 25 ) /* (MC) Sector 9 Lock Status */ +#define AT91C_MC_LOCKS10 ( 0x1 << 26 ) /* (MC) Sector 10 Lock Status */ +#define AT91C_MC_LOCKS11 ( 0x1 << 27 ) /* (MC) Sector 11 Lock Status */ +#define AT91C_MC_LOCKS12 ( 0x1 << 28 ) /* (MC) Sector 12 Lock Status */ +#define AT91C_MC_LOCKS13 ( 0x1 << 29 ) /* (MC) Sector 13 Lock Status */ +#define AT91C_MC_LOCKS14 ( 0x1 << 30 ) /* (MC) Sector 14 Lock Status */ +#define AT91C_MC_LOCKS15 ( 0x1 << 31 ) /* (MC) Sector 15 Lock Status */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_SPI structure *** */ +#define SPI_CR ( 0 ) /* Control Register */ +#define SPI_MR ( 4 ) /* Mode Register */ +#define SPI_RDR ( 8 ) /* Receive Data Register */ +#define SPI_TDR ( 12 ) /* Transmit Data Register */ +#define SPI_SR ( 16 ) /* Status Register */ +#define SPI_IER ( 20 ) /* Interrupt Enable Register */ +#define SPI_IDR ( 24 ) /* Interrupt Disable Register */ +#define SPI_IMR ( 28 ) /* Interrupt Mask Register */ +#define SPI_CSR ( 48 ) /* Chip Select Register */ +#define SPI_RPR ( 256 ) /* Receive Pointer Register */ +#define SPI_RCR ( 260 ) /* Receive Counter Register */ +#define SPI_TPR ( 264 ) /* Transmit Pointer Register */ +#define SPI_TCR ( 268 ) /* Transmit Counter Register */ +#define SPI_RNPR ( 272 ) /* Receive Next Pointer Register */ +#define SPI_RNCR ( 276 ) /* Receive Next Counter Register */ +#define SPI_TNPR ( 280 ) /* Transmit Next Pointer Register */ +#define SPI_TNCR ( 284 ) /* Transmit Next Counter Register */ +#define SPI_PTCR ( 288 ) /* PDC Transfer Control Register */ +#define SPI_PTSR ( 292 ) /* PDC Transfer Status Register */ +/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */ +#define AT91C_SPI_SPIEN ( 0x1 << 0 ) /* (SPI) SPI Enable */ +#define AT91C_SPI_SPIDIS ( 0x1 << 1 ) /* (SPI) SPI Disable */ +#define AT91C_SPI_SWRST ( 0x1 << 7 ) /* (SPI) SPI Software reset */ +#define AT91C_SPI_LASTXFER ( 0x1 << 24 ) /* (SPI) SPI Last Transfer */ +/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */ +#define AT91C_SPI_MSTR ( 0x1 << 0 ) /* (SPI) Master/Slave Mode */ +#define AT91C_SPI_PS ( 0x1 << 1 ) /* (SPI) Peripheral Select */ +#define AT91C_SPI_PS_FIXED ( 0x0 << 1 ) /* (SPI) Fixed Peripheral Select */ +#define AT91C_SPI_PS_VARIABLE ( 0x1 << 1 ) /* (SPI) Variable Peripheral Select */ +#define AT91C_SPI_PCSDEC ( 0x1 << 2 ) /* (SPI) Chip Select Decode */ +#define AT91C_SPI_FDIV ( 0x1 << 3 ) /* (SPI) Clock Selection */ +#define AT91C_SPI_MODFDIS ( 0x1 << 4 ) /* (SPI) Mode Fault Detection */ +#define AT91C_SPI_LLB ( 0x1 << 7 ) /* (SPI) Clock Selection */ +#define AT91C_SPI_PCS ( 0xF << 16 ) /* (SPI) Peripheral Chip Select */ +#define AT91C_SPI_DLYBCS ( 0xFF << 24 ) /* (SPI) Delay Between Chip Selects */ +/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */ +#define AT91C_SPI_RD ( 0xFFFF << 0 ) /* (SPI) Receive Data */ +#define AT91C_SPI_RPCS ( 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */ +/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */ +#define AT91C_SPI_TD ( 0xFFFF << 0 ) /* (SPI) Transmit Data */ +#define AT91C_SPI_TPCS ( 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */ +/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ +#define AT91C_SPI_RDRF ( 0x1 << 0 ) /* (SPI) Receive Data Register Full */ +#define AT91C_SPI_TDRE ( 0x1 << 1 ) /* (SPI) Transmit Data Register Empty */ +#define AT91C_SPI_MODF ( 0x1 << 2 ) /* (SPI) Mode Fault Error */ +#define AT91C_SPI_OVRES ( 0x1 << 3 ) /* (SPI) Overrun Error Status */ +#define AT91C_SPI_ENDRX ( 0x1 << 4 ) /* (SPI) End of Receiver Transfer */ +#define AT91C_SPI_ENDTX ( 0x1 << 5 ) /* (SPI) End of Receiver Transfer */ +#define AT91C_SPI_RXBUFF ( 0x1 << 6 ) /* (SPI) RXBUFF Interrupt */ +#define AT91C_SPI_TXBUFE ( 0x1 << 7 ) /* (SPI) TXBUFE Interrupt */ +#define AT91C_SPI_NSSR ( 0x1 << 8 ) /* (SPI) NSSR Interrupt */ +#define AT91C_SPI_TXEMPTY ( 0x1 << 9 ) /* (SPI) TXEMPTY Interrupt */ +#define AT91C_SPI_SPIENS ( 0x1 << 16 ) /* (SPI) Enable Status */ +/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ +/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ +/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */ +/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */ +#define AT91C_SPI_CPOL ( 0x1 << 0 ) /* (SPI) Clock Polarity */ +#define AT91C_SPI_NCPHA ( 0x1 << 1 ) /* (SPI) Clock Phase */ +#define AT91C_SPI_CSAAT ( 0x1 << 3 ) /* (SPI) Chip Select Active After Transfer */ +#define AT91C_SPI_BITS ( 0xF << 4 ) /* (SPI) Bits Per Transfer */ +#define AT91C_SPI_BITS_8 ( 0x0 << 4 ) /* (SPI) 8 Bits Per transfer */ +#define AT91C_SPI_BITS_9 ( 0x1 << 4 ) /* (SPI) 9 Bits Per transfer */ +#define AT91C_SPI_BITS_10 ( 0x2 << 4 ) /* (SPI) 10 Bits Per transfer */ +#define AT91C_SPI_BITS_11 ( 0x3 << 4 ) /* (SPI) 11 Bits Per transfer */ +#define AT91C_SPI_BITS_12 ( 0x4 << 4 ) /* (SPI) 12 Bits Per transfer */ +#define AT91C_SPI_BITS_13 ( 0x5 << 4 ) /* (SPI) 13 Bits Per transfer */ +#define AT91C_SPI_BITS_14 ( 0x6 << 4 ) /* (SPI) 14 Bits Per transfer */ +#define AT91C_SPI_BITS_15 ( 0x7 << 4 ) /* (SPI) 15 Bits Per transfer */ +#define AT91C_SPI_BITS_16 ( 0x8 << 4 ) /* (SPI) 16 Bits Per transfer */ +#define AT91C_SPI_SCBR ( 0xFF << 8 ) /* (SPI) Serial Clock Baud Rate */ +#define AT91C_SPI_DLYBS ( 0xFF << 16 ) /* (SPI) Delay Before SPCK */ +#define AT91C_SPI_DLYBCT ( 0xFF << 24 ) /* (SPI) Delay Between Consecutive Transfers */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Usart */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_USART structure *** */ +#define US_CR ( 0 ) /* Control Register */ +#define US_MR ( 4 ) /* Mode Register */ +#define US_IER ( 8 ) /* Interrupt Enable Register */ +#define US_IDR ( 12 ) /* Interrupt Disable Register */ +#define US_IMR ( 16 ) /* Interrupt Mask Register */ +#define US_CSR ( 20 ) /* Channel Status Register */ +#define US_RHR ( 24 ) /* Receiver Holding Register */ +#define US_THR ( 28 ) /* Transmitter Holding Register */ +#define US_BRGR ( 32 ) /* Baud Rate Generator Register */ +#define US_RTOR ( 36 ) /* Receiver Time-out Register */ +#define US_TTGR ( 40 ) /* Transmitter Time-guard Register */ +#define US_FIDI ( 64 ) /* FI_DI_Ratio Register */ +#define US_NER ( 68 ) /* Nb Errors Register */ +#define US_IF ( 76 ) /* IRDA_FILTER Register */ +#define US_RPR ( 256 ) /* Receive Pointer Register */ +#define US_RCR ( 260 ) /* Receive Counter Register */ +#define US_TPR ( 264 ) /* Transmit Pointer Register */ +#define US_TCR ( 268 ) /* Transmit Counter Register */ +#define US_RNPR ( 272 ) /* Receive Next Pointer Register */ +#define US_RNCR ( 276 ) /* Receive Next Counter Register */ +#define US_TNPR ( 280 ) /* Transmit Next Pointer Register */ +#define US_TNCR ( 284 ) /* Transmit Next Counter Register */ +#define US_PTCR ( 288 ) /* PDC Transfer Control Register */ +#define US_PTSR ( 292 ) /* PDC Transfer Status Register */ +/* -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- */ +#define AT91C_US_STTBRK ( 0x1 << 9 ) /* (USART) Start Break */ +#define AT91C_US_STPBRK ( 0x1 << 10 ) /* (USART) Stop Break */ +#define AT91C_US_STTTO ( 0x1 << 11 ) /* (USART) Start Time-out */ +#define AT91C_US_SENDA ( 0x1 << 12 ) /* (USART) Send Address */ +#define AT91C_US_RSTIT ( 0x1 << 13 ) /* (USART) Reset Iterations */ +#define AT91C_US_RSTNACK ( 0x1 << 14 ) /* (USART) Reset Non Acknowledge */ +#define AT91C_US_RETTO ( 0x1 << 15 ) /* (USART) Rearm Time-out */ +#define AT91C_US_DTREN ( 0x1 << 16 ) /* (USART) Data Terminal ready Enable */ +#define AT91C_US_DTRDIS ( 0x1 << 17 ) /* (USART) Data Terminal ready Disable */ +#define AT91C_US_RTSEN ( 0x1 << 18 ) /* (USART) Request to Send enable */ +#define AT91C_US_RTSDIS ( 0x1 << 19 ) /* (USART) Request to Send Disable */ +/* -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- */ +#define AT91C_US_USMODE ( 0xF << 0 ) /* (USART) Usart mode */ +#define AT91C_US_USMODE_NORMAL ( 0x0 ) /* (USART) Normal */ +#define AT91C_US_USMODE_RS485 ( 0x1 ) /* (USART) RS485 */ +#define AT91C_US_USMODE_HWHSH ( 0x2 ) /* (USART) Hardware Handshaking */ +#define AT91C_US_USMODE_MODEM ( 0x3 ) /* (USART) Modem */ +#define AT91C_US_USMODE_ISO7816_0 ( 0x4 ) /* (USART) ISO7816 protocol: T = 0 */ +#define AT91C_US_USMODE_ISO7816_1 ( 0x6 ) /* (USART) ISO7816 protocol: T = 1 */ +#define AT91C_US_USMODE_IRDA ( 0x8 ) /* (USART) IrDA */ +#define AT91C_US_USMODE_SWHSH ( 0xC ) /* (USART) Software Handshaking */ +#define AT91C_US_CLKS ( 0x3 << 4 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */ +#define AT91C_US_CLKS_CLOCK ( 0x0 << 4 ) /* (USART) Clock */ +#define AT91C_US_CLKS_FDIV1 ( 0x1 << 4 ) /* (USART) fdiv1 */ +#define AT91C_US_CLKS_SLOW ( 0x2 << 4 ) /* (USART) slow_clock (ARM) */ +#define AT91C_US_CLKS_EXT ( 0x3 << 4 ) /* (USART) External (SCK) */ +#define AT91C_US_CHRL ( 0x3 << 6 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */ +#define AT91C_US_CHRL_5_BITS ( 0x0 << 6 ) /* (USART) Character Length: 5 bits */ +#define AT91C_US_CHRL_6_BITS ( 0x1 << 6 ) /* (USART) Character Length: 6 bits */ +#define AT91C_US_CHRL_7_BITS ( 0x2 << 6 ) /* (USART) Character Length: 7 bits */ +#define AT91C_US_CHRL_8_BITS ( 0x3 << 6 ) /* (USART) Character Length: 8 bits */ +#define AT91C_US_SYNC ( 0x1 << 8 ) /* (USART) Synchronous Mode Select */ +#define AT91C_US_NBSTOP ( 0x3 << 12 ) /* (USART) Number of Stop bits */ +#define AT91C_US_NBSTOP_1_BIT ( 0x0 << 12 ) /* (USART) 1 stop bit */ +#define AT91C_US_NBSTOP_15_BIT ( 0x1 << 12 ) /* (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */ +#define AT91C_US_NBSTOP_2_BIT ( 0x2 << 12 ) /* (USART) 2 stop bits */ +#define AT91C_US_MSBF ( 0x1 << 16 ) /* (USART) Bit Order */ +#define AT91C_US_MODE9 ( 0x1 << 17 ) /* (USART) 9-bit Character length */ +#define AT91C_US_CKLO ( 0x1 << 18 ) /* (USART) Clock Output Select */ +#define AT91C_US_OVER ( 0x1 << 19 ) /* (USART) Over Sampling Mode */ +#define AT91C_US_INACK ( 0x1 << 20 ) /* (USART) Inhibit Non Acknowledge */ +#define AT91C_US_DSNACK ( 0x1 << 21 ) /* (USART) Disable Successive NACK */ +#define AT91C_US_MAX_ITER ( 0x1 << 24 ) /* (USART) Number of Repetitions */ +#define AT91C_US_FILTER ( 0x1 << 28 ) /* (USART) Receive Line Filter */ +/* -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ +#define AT91C_US_RXBRK ( 0x1 << 2 ) /* (USART) Break Received/End of Break */ +#define AT91C_US_TIMEOUT ( 0x1 << 8 ) /* (USART) Receiver Time-out */ +#define AT91C_US_ITERATION ( 0x1 << 10 ) /* (USART) Max number of Repetitions Reached */ +#define AT91C_US_NACK ( 0x1 << 13 ) /* (USART) Non Acknowledge */ +#define AT91C_US_RIIC ( 0x1 << 16 ) /* (USART) Ring INdicator Input Change Flag */ +#define AT91C_US_DSRIC ( 0x1 << 17 ) /* (USART) Data Set Ready Input Change Flag */ +#define AT91C_US_DCDIC ( 0x1 << 18 ) /* (USART) Data Carrier Flag */ +#define AT91C_US_CTSIC ( 0x1 << 19 ) /* (USART) Clear To Send Input Change Flag */ +/* -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- */ +/* -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- */ +/* -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- */ +#define AT91C_US_RI ( 0x1 << 20 ) /* (USART) Image of RI Input */ +#define AT91C_US_DSR ( 0x1 << 21 ) /* (USART) Image of DSR Input */ +#define AT91C_US_DCD ( 0x1 << 22 ) /* (USART) Image of DCD Input */ +#define AT91C_US_CTS ( 0x1 << 23 ) /* (USART) Image of CTS Input */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_SSC structure *** */ +#define SSC_CR ( 0 ) /* Control Register */ +#define SSC_CMR ( 4 ) /* Clock Mode Register */ +#define SSC_RCMR ( 16 ) /* Receive Clock ModeRegister */ +#define SSC_RFMR ( 20 ) /* Receive Frame Mode Register */ +#define SSC_TCMR ( 24 ) /* Transmit Clock Mode Register */ +#define SSC_TFMR ( 28 ) /* Transmit Frame Mode Register */ +#define SSC_RHR ( 32 ) /* Receive Holding Register */ +#define SSC_THR ( 36 ) /* Transmit Holding Register */ +#define SSC_RSHR ( 48 ) /* Receive Sync Holding Register */ +#define SSC_TSHR ( 52 ) /* Transmit Sync Holding Register */ +#define SSC_SR ( 64 ) /* Status Register */ +#define SSC_IER ( 68 ) /* Interrupt Enable Register */ +#define SSC_IDR ( 72 ) /* Interrupt Disable Register */ +#define SSC_IMR ( 76 ) /* Interrupt Mask Register */ +#define SSC_RPR ( 256 ) /* Receive Pointer Register */ +#define SSC_RCR ( 260 ) /* Receive Counter Register */ +#define SSC_TPR ( 264 ) /* Transmit Pointer Register */ +#define SSC_TCR ( 268 ) /* Transmit Counter Register */ +#define SSC_RNPR ( 272 ) /* Receive Next Pointer Register */ +#define SSC_RNCR ( 276 ) /* Receive Next Counter Register */ +#define SSC_TNPR ( 280 ) /* Transmit Next Pointer Register */ +#define SSC_TNCR ( 284 ) /* Transmit Next Counter Register */ +#define SSC_PTCR ( 288 ) /* PDC Transfer Control Register */ +#define SSC_PTSR ( 292 ) /* PDC Transfer Status Register */ +/* -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- */ +#define AT91C_SSC_RXEN ( 0x1 << 0 ) /* (SSC) Receive Enable */ +#define AT91C_SSC_RXDIS ( 0x1 << 1 ) /* (SSC) Receive Disable */ +#define AT91C_SSC_TXEN ( 0x1 << 8 ) /* (SSC) Transmit Enable */ +#define AT91C_SSC_TXDIS ( 0x1 << 9 ) /* (SSC) Transmit Disable */ +#define AT91C_SSC_SWRST ( 0x1 << 15 ) /* (SSC) Software Reset */ +/* -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- */ +#define AT91C_SSC_CKS ( 0x3 << 0 ) /* (SSC) Receive/Transmit Clock Selection */ +#define AT91C_SSC_CKS_DIV ( 0x0 ) /* (SSC) Divided Clock */ +#define AT91C_SSC_CKS_TK ( 0x1 ) /* (SSC) TK Clock signal */ +#define AT91C_SSC_CKS_RK ( 0x2 ) /* (SSC) RK pin */ +#define AT91C_SSC_CKO ( 0x7 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode Selection */ +#define AT91C_SSC_CKO_NONE ( 0x0 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only */ +#define AT91C_SSC_CKO_CONTINUOUS ( 0x1 << 2 ) /* (SSC) Continuous Receive/Transmit Clock RK pin: Output */ +#define AT91C_SSC_CKO_DATA_TX ( 0x2 << 2 ) /* (SSC) Receive/Transmit Clock only during data transfers RK pin: Output */ +#define AT91C_SSC_CKI ( 0x1 << 5 ) /* (SSC) Receive/Transmit Clock Inversion */ +#define AT91C_SSC_START ( 0xF << 8 ) /* (SSC) Receive/Transmit Start Selection */ +#define AT91C_SSC_START_CONTINUOUS ( 0x0 << 8 ) /* (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */ +#define AT91C_SSC_START_TX ( 0x1 << 8 ) /* (SSC) Transmit/Receive start */ +#define AT91C_SSC_START_LOW_RF ( 0x2 << 8 ) /* (SSC) Detection of a low level on RF input */ +#define AT91C_SSC_START_HIGH_RF ( 0x3 << 8 ) /* (SSC) Detection of a high level on RF input */ +#define AT91C_SSC_START_FALL_RF ( 0x4 << 8 ) /* (SSC) Detection of a falling edge on RF input */ +#define AT91C_SSC_START_RISE_RF ( 0x5 << 8 ) /* (SSC) Detection of a rising edge on RF input */ +#define AT91C_SSC_START_LEVEL_RF ( 0x6 << 8 ) /* (SSC) Detection of any level change on RF input */ +#define AT91C_SSC_START_EDGE_RF ( 0x7 << 8 ) /* (SSC) Detection of any edge on RF input */ +#define AT91C_SSC_START_0 ( 0x8 << 8 ) /* (SSC) Compare 0 */ +#define AT91C_SSC_STTDLY ( 0xFF << 16 ) /* (SSC) Receive/Transmit Start Delay */ +#define AT91C_SSC_PERIOD ( 0xFF << 24 ) /* (SSC) Receive/Transmit Period Divider Selection */ +/* -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- */ +#define AT91C_SSC_DATLEN ( 0x1F << 0 ) /* (SSC) Data Length */ +#define AT91C_SSC_LOOP ( 0x1 << 5 ) /* (SSC) Loop Mode */ +#define AT91C_SSC_MSBF ( 0x1 << 7 ) /* (SSC) Most Significant Bit First */ +#define AT91C_SSC_DATNB ( 0xF << 8 ) /* (SSC) Data Number per Frame */ +#define AT91C_SSC_FSLEN ( 0xF << 16 ) /* (SSC) Receive/Transmit Frame Sync length */ +#define AT91C_SSC_FSOS ( 0x7 << 20 ) /* (SSC) Receive/Transmit Frame Sync Output Selection */ +#define AT91C_SSC_FSOS_NONE ( 0x0 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only */ +#define AT91C_SSC_FSOS_NEGATIVE ( 0x1 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse */ +#define AT91C_SSC_FSOS_POSITIVE ( 0x2 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse */ +#define AT91C_SSC_FSOS_LOW ( 0x3 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer */ +#define AT91C_SSC_FSOS_HIGH ( 0x4 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer */ +#define AT91C_SSC_FSOS_TOGGLE ( 0x5 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer */ +#define AT91C_SSC_FSEDGE ( 0x1 << 24 ) /* (SSC) Frame Sync Edge Detection */ +/* -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- */ +/* -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- */ +#define AT91C_SSC_DATDEF ( 0x1 << 5 ) /* (SSC) Data Default Value */ +#define AT91C_SSC_FSDEN ( 0x1 << 23 ) /* (SSC) Frame Sync Data Enable */ +/* -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- */ +#define AT91C_SSC_TXRDY ( 0x1 << 0 ) /* (SSC) Transmit Ready */ +#define AT91C_SSC_TXEMPTY ( 0x1 << 1 ) /* (SSC) Transmit Empty */ +#define AT91C_SSC_ENDTX ( 0x1 << 2 ) /* (SSC) End Of Transmission */ +#define AT91C_SSC_TXBUFE ( 0x1 << 3 ) /* (SSC) Transmit Buffer Empty */ +#define AT91C_SSC_RXRDY ( 0x1 << 4 ) /* (SSC) Receive Ready */ +#define AT91C_SSC_OVRUN ( 0x1 << 5 ) /* (SSC) Receive Overrun */ +#define AT91C_SSC_ENDRX ( 0x1 << 6 ) /* (SSC) End of Reception */ +#define AT91C_SSC_RXBUFF ( 0x1 << 7 ) /* (SSC) Receive Buffer Full */ +#define AT91C_SSC_TXSYN ( 0x1 << 10 ) /* (SSC) Transmit Sync */ +#define AT91C_SSC_RXSYN ( 0x1 << 11 ) /* (SSC) Receive Sync */ +#define AT91C_SSC_TXENA ( 0x1 << 16 ) /* (SSC) Transmit Enable */ +#define AT91C_SSC_RXENA ( 0x1 << 17 ) /* (SSC) Receive Enable */ +/* -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- */ +/* -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- */ +/* -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Two-wire Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_TWI structure *** */ +#define TWI_CR ( 0 ) /* Control Register */ +#define TWI_MMR ( 4 ) /* Master Mode Register */ +#define TWI_IADR ( 12 ) /* Internal Address Register */ +#define TWI_CWGR ( 16 ) /* Clock Waveform Generator Register */ +#define TWI_SR ( 32 ) /* Status Register */ +#define TWI_IER ( 36 ) /* Interrupt Enable Register */ +#define TWI_IDR ( 40 ) /* Interrupt Disable Register */ +#define TWI_IMR ( 44 ) /* Interrupt Mask Register */ +#define TWI_RHR ( 48 ) /* Receive Holding Register */ +#define TWI_THR ( 52 ) /* Transmit Holding Register */ +/* -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */ +#define AT91C_TWI_START ( 0x1 << 0 ) /* (TWI) Send a START Condition */ +#define AT91C_TWI_STOP ( 0x1 << 1 ) /* (TWI) Send a STOP Condition */ +#define AT91C_TWI_MSEN ( 0x1 << 2 ) /* (TWI) TWI Master Transfer Enabled */ +#define AT91C_TWI_MSDIS ( 0x1 << 3 ) /* (TWI) TWI Master Transfer Disabled */ +#define AT91C_TWI_SWRST ( 0x1 << 7 ) /* (TWI) Software Reset */ +/* -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */ +#define AT91C_TWI_IADRSZ ( 0x3 << 8 ) /* (TWI) Internal Device Address Size */ +#define AT91C_TWI_IADRSZ_NO ( 0x0 << 8 ) /* (TWI) No internal device address */ +#define AT91C_TWI_IADRSZ_1_BYTE ( 0x1 << 8 ) /* (TWI) One-byte internal device address */ +#define AT91C_TWI_IADRSZ_2_BYTE ( 0x2 << 8 ) /* (TWI) Two-byte internal device address */ +#define AT91C_TWI_IADRSZ_3_BYTE ( 0x3 << 8 ) /* (TWI) Three-byte internal device address */ +#define AT91C_TWI_MREAD ( 0x1 << 12 ) /* (TWI) Master Read Direction */ +#define AT91C_TWI_DADR ( 0x7F << 16 ) /* (TWI) Device Address */ +/* -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */ +#define AT91C_TWI_CLDIV ( 0xFF << 0 ) /* (TWI) Clock Low Divider */ +#define AT91C_TWI_CHDIV ( 0xFF << 8 ) /* (TWI) Clock High Divider */ +#define AT91C_TWI_CKDIV ( 0x7 << 16 ) /* (TWI) Clock Divider */ +/* -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */ +#define AT91C_TWI_TXCOMP ( 0x1 << 0 ) /* (TWI) Transmission Completed */ +#define AT91C_TWI_RXRDY ( 0x1 << 1 ) /* (TWI) Receive holding register ReaDY */ +#define AT91C_TWI_TXRDY ( 0x1 << 2 ) /* (TWI) Transmit holding register ReaDY */ +#define AT91C_TWI_OVRE ( 0x1 << 6 ) /* (TWI) Overrun Error */ +#define AT91C_TWI_UNRE ( 0x1 << 7 ) /* (TWI) Underrun Error */ +#define AT91C_TWI_NACK ( 0x1 << 8 ) /* (TWI) Not Acknowledged */ +/* -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */ +/* -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- */ +/* -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR PWMC Channel Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_PWMC_CH structure *** */ +#define PWMC_CMR ( 0 ) /* Channel Mode Register */ +#define PWMC_CDTYR ( 4 ) /* Channel Duty Cycle Register */ +#define PWMC_CPRDR ( 8 ) /* Channel Period Register */ +#define PWMC_CCNTR ( 12 ) /* Channel Counter Register */ +#define PWMC_CUPDR ( 16 ) /* Channel Update Register */ +#define PWMC_Reserved ( 20 ) /* Reserved */ +/* -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- */ +#define AT91C_PWMC_CPRE ( 0xF << 0 ) /* (PWMC_CH) Channel Pre-scaler : PWMC_CLKx */ +#define AT91C_PWMC_CPRE_MCK ( 0x0 ) /* (PWMC_CH) */ +#define AT91C_PWMC_CPRE_MCKA ( 0xB ) /* (PWMC_CH) */ +#define AT91C_PWMC_CPRE_MCKB ( 0xC ) /* (PWMC_CH) */ +#define AT91C_PWMC_CALG ( 0x1 << 8 ) /* (PWMC_CH) Channel Alignment */ +#define AT91C_PWMC_CPOL ( 0x1 << 9 ) /* (PWMC_CH) Channel Polarity */ +#define AT91C_PWMC_CPD ( 0x1 << 10 ) /* (PWMC_CH) Channel Update Period */ +/* -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- */ +#define AT91C_PWMC_CDTY ( 0x0 << 0 ) /* (PWMC_CH) Channel Duty Cycle */ +/* -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- */ +#define AT91C_PWMC_CPRD ( 0x0 << 0 ) /* (PWMC_CH) Channel Period */ +/* -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- */ +#define AT91C_PWMC_CCNT ( 0x0 << 0 ) /* (PWMC_CH) Channel Counter */ +/* -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- */ +#define AT91C_PWMC_CUPD ( 0x0 << 0 ) /* (PWMC_CH) Channel Update */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_PWMC structure *** */ +#define PWMC_MR ( 0 ) /* PWMC Mode Register */ +#define PWMC_ENA ( 4 ) /* PWMC Enable Register */ +#define PWMC_DIS ( 8 ) /* PWMC Disable Register */ +#define PWMC_SR ( 12 ) /* PWMC Status Register */ +#define PWMC_IER ( 16 ) /* PWMC Interrupt Enable Register */ +#define PWMC_IDR ( 20 ) /* PWMC Interrupt Disable Register */ +#define PWMC_IMR ( 24 ) /* PWMC Interrupt Mask Register */ +#define PWMC_ISR ( 28 ) /* PWMC Interrupt Status Register */ +#define PWMC_VR ( 252 ) /* PWMC Version Register */ +#define PWMC_CH ( 512 ) /* PWMC Channel */ +/* -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- */ +#define AT91C_PWMC_DIVA ( 0xFF << 0 ) /* (PWMC) CLKA divide factor. */ +#define AT91C_PWMC_PREA ( 0xF << 8 ) /* (PWMC) Divider Input Clock Prescaler A */ +#define AT91C_PWMC_PREA_MCK ( 0x0 << 8 ) /* (PWMC) */ +#define AT91C_PWMC_DIVB ( 0xFF << 16 ) /* (PWMC) CLKB divide factor. */ +#define AT91C_PWMC_PREB ( 0xF << 24 ) /* (PWMC) Divider Input Clock Prescaler B */ +#define AT91C_PWMC_PREB_MCK ( 0x0 << 24 ) /* (PWMC) */ +/* -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- */ +#define AT91C_PWMC_CHID0 ( 0x1 << 0 ) /* (PWMC) Channel ID 0 */ +#define AT91C_PWMC_CHID1 ( 0x1 << 1 ) /* (PWMC) Channel ID 1 */ +#define AT91C_PWMC_CHID2 ( 0x1 << 2 ) /* (PWMC) Channel ID 2 */ +#define AT91C_PWMC_CHID3 ( 0x1 << 3 ) /* (PWMC) Channel ID 3 */ +/* -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- */ +/* -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- */ +/* -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- */ +/* -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- */ +/* -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- */ +/* -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR USB Device Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_UDP structure *** */ +#define UDP_NUM ( 0 ) /* Frame Number Register */ +#define UDP_GLBSTATE ( 4 ) /* Global State Register */ +#define UDP_FADDR ( 8 ) /* Function Address Register */ +#define UDP_IER ( 16 ) /* Interrupt Enable Register */ +#define UDP_IDR ( 20 ) /* Interrupt Disable Register */ +#define UDP_IMR ( 24 ) /* Interrupt Mask Register */ +#define UDP_ISR ( 28 ) /* Interrupt Status Register */ +#define UDP_ICR ( 32 ) /* Interrupt Clear Register */ +#define UDP_RSTEP ( 40 ) /* Reset Endpoint Register */ +#define UDP_CSR ( 48 ) /* Endpoint Control and Status Register */ +#define UDP_FDR ( 80 ) /* Endpoint FIFO Data Register */ +#define UDP_TXVC ( 116 ) /* Transceiver Control Register */ +/* -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- */ +#define AT91C_UDP_FRM_NUM ( 0x7FF << 0 ) /* (UDP) Frame Number as Defined in the Packet Field Formats */ +#define AT91C_UDP_FRM_ERR ( 0x1 << 16 ) /* (UDP) Frame Error */ +#define AT91C_UDP_FRM_OK ( 0x1 << 17 ) /* (UDP) Frame OK */ +/* -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- */ +#define AT91C_UDP_FADDEN ( 0x1 << 0 ) /* (UDP) Function Address Enable */ +#define AT91C_UDP_CONFG ( 0x1 << 1 ) /* (UDP) Configured */ +#define AT91C_UDP_ESR ( 0x1 << 2 ) /* (UDP) Enable Send Resume */ +#define AT91C_UDP_RSMINPR ( 0x1 << 3 ) /* (UDP) A Resume Has Been Sent to the Host */ +#define AT91C_UDP_RMWUPE ( 0x1 << 4 ) /* (UDP) Remote Wake Up Enable */ +/* -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- */ +#define AT91C_UDP_FADD ( 0xFF << 0 ) /* (UDP) Function Address Value */ +#define AT91C_UDP_FEN ( 0x1 << 8 ) /* (UDP) Function Enable */ +/* -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- */ +#define AT91C_UDP_EPINT0 ( 0x1 << 0 ) /* (UDP) Endpoint 0 Interrupt */ +#define AT91C_UDP_EPINT1 ( 0x1 << 1 ) /* (UDP) Endpoint 0 Interrupt */ +#define AT91C_UDP_EPINT2 ( 0x1 << 2 ) /* (UDP) Endpoint 2 Interrupt */ +#define AT91C_UDP_EPINT3 ( 0x1 << 3 ) /* (UDP) Endpoint 3 Interrupt */ +#define AT91C_UDP_EPINT4 ( 0x1 << 4 ) /* (UDP) Endpoint 4 Interrupt */ +#define AT91C_UDP_EPINT5 ( 0x1 << 5 ) /* (UDP) Endpoint 5 Interrupt */ +#define AT91C_UDP_RXSUSP ( 0x1 << 8 ) /* (UDP) USB Suspend Interrupt */ +#define AT91C_UDP_RXRSM ( 0x1 << 9 ) /* (UDP) USB Resume Interrupt */ +#define AT91C_UDP_EXTRSM ( 0x1 << 10 ) /* (UDP) USB External Resume Interrupt */ +#define AT91C_UDP_SOFINT ( 0x1 << 11 ) /* (UDP) USB Start Of frame Interrupt */ +#define AT91C_UDP_WAKEUP ( 0x1 << 13 ) /* (UDP) USB Resume Interrupt */ +/* -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- */ +/* -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- */ +/* -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- */ +#define AT91C_UDP_ENDBUSRES ( 0x1 << 12 ) /* (UDP) USB End Of Bus Reset Interrupt */ +/* -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- */ +/* -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- */ +#define AT91C_UDP_EP0 ( 0x1 << 0 ) /* (UDP) Reset Endpoint 0 */ +#define AT91C_UDP_EP1 ( 0x1 << 1 ) /* (UDP) Reset Endpoint 1 */ +#define AT91C_UDP_EP2 ( 0x1 << 2 ) /* (UDP) Reset Endpoint 2 */ +#define AT91C_UDP_EP3 ( 0x1 << 3 ) /* (UDP) Reset Endpoint 3 */ +#define AT91C_UDP_EP4 ( 0x1 << 4 ) /* (UDP) Reset Endpoint 4 */ +#define AT91C_UDP_EP5 ( 0x1 << 5 ) /* (UDP) Reset Endpoint 5 */ +/* -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- */ +#define AT91C_UDP_TXCOMP ( 0x1 << 0 ) /* (UDP) Generates an IN packet with data previously written in the DPR */ +#define AT91C_UDP_RX_DATA_BK0 ( 0x1 << 1 ) /* (UDP) Receive Data Bank 0 */ +#define AT91C_UDP_RXSETUP ( 0x1 << 2 ) /* (UDP) Sends STALL to the Host (Control endpoints) */ +#define AT91C_UDP_ISOERROR ( 0x1 << 3 ) /* (UDP) Isochronous error (Isochronous endpoints) */ +#define AT91C_UDP_TXPKTRDY ( 0x1 << 4 ) /* (UDP) Transmit Packet Ready */ +#define AT91C_UDP_FORCESTALL ( 0x1 << 5 ) /* (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). */ +#define AT91C_UDP_RX_DATA_BK1 ( 0x1 << 6 ) /* (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). */ +#define AT91C_UDP_DIR ( 0x1 << 7 ) /* (UDP) Transfer Direction */ +#define AT91C_UDP_EPTYPE ( 0x7 << 8 ) /* (UDP) Endpoint type */ +#define AT91C_UDP_EPTYPE_CTRL ( 0x0 << 8 ) /* (UDP) Control */ +#define AT91C_UDP_EPTYPE_ISO_OUT ( 0x1 << 8 ) /* (UDP) Isochronous OUT */ +#define AT91C_UDP_EPTYPE_BULK_OUT ( 0x2 << 8 ) /* (UDP) Bulk OUT */ +#define AT91C_UDP_EPTYPE_INT_OUT ( 0x3 << 8 ) /* (UDP) Interrupt OUT */ +#define AT91C_UDP_EPTYPE_ISO_IN ( 0x5 << 8 ) /* (UDP) Isochronous IN */ +#define AT91C_UDP_EPTYPE_BULK_IN ( 0x6 << 8 ) /* (UDP) Bulk IN */ +#define AT91C_UDP_EPTYPE_INT_IN ( 0x7 << 8 ) /* (UDP) Interrupt IN */ +#define AT91C_UDP_DTGLE ( 0x1 << 11 ) /* (UDP) Data Toggle */ +#define AT91C_UDP_EPEDS ( 0x1 << 15 ) /* (UDP) Endpoint Enable Disable */ +#define AT91C_UDP_RXBYTECNT ( 0x7FF << 16 ) /* (UDP) Number Of Bytes Available in the FIFO */ +/* -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- */ +#define AT91C_UDP_TXVDIS ( 0x1 << 8 ) /* (UDP) */ +#define AT91C_UDP_PUON ( 0x1 << 9 ) /* (UDP) Pull-up ON */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_TC structure *** */ +#define TC_CCR ( 0 ) /* Channel Control Register */ +#define TC_CMR ( 4 ) /* Channel Mode Register (Capture Mode / Waveform Mode) */ +#define TC_CV ( 16 ) /* Counter Value */ +#define TC_RA ( 20 ) /* Register A */ +#define TC_RB ( 24 ) /* Register B */ +#define TC_RC ( 28 ) /* Register C */ +#define TC_SR ( 32 ) /* Status Register */ +#define TC_IER ( 36 ) /* Interrupt Enable Register */ +#define TC_IDR ( 40 ) /* Interrupt Disable Register */ +#define TC_IMR ( 44 ) /* Interrupt Mask Register */ +/* -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- */ +#define AT91C_TC_CLKEN ( 0x1 << 0 ) /* (TC) Counter Clock Enable Command */ +#define AT91C_TC_CLKDIS ( 0x1 << 1 ) /* (TC) Counter Clock Disable Command */ +#define AT91C_TC_SWTRG ( 0x1 << 2 ) /* (TC) Software Trigger Command */ +/* -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- */ +#define AT91C_TC_CLKS ( 0x7 << 0 ) /* (TC) Clock Selection */ +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ( 0x0 ) /* (TC) Clock selected: TIMER_DIV1_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ( 0x1 ) /* (TC) Clock selected: TIMER_DIV2_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ( 0x2 ) /* (TC) Clock selected: TIMER_DIV3_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ( 0x3 ) /* (TC) Clock selected: TIMER_DIV4_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ( 0x4 ) /* (TC) Clock selected: TIMER_DIV5_CLOCK */ +#define AT91C_TC_CLKS_XC0 ( 0x5 ) /* (TC) Clock selected: XC0 */ +#define AT91C_TC_CLKS_XC1 ( 0x6 ) /* (TC) Clock selected: XC1 */ +#define AT91C_TC_CLKS_XC2 ( 0x7 ) /* (TC) Clock selected: XC2 */ +#define AT91C_TC_CLKI ( 0x1 << 3 ) /* (TC) Clock Invert */ +#define AT91C_TC_BURST ( 0x3 << 4 ) /* (TC) Burst Signal Selection */ +#define AT91C_TC_BURST_NONE ( 0x0 << 4 ) /* (TC) The clock is not gated by an external signal */ +#define AT91C_TC_BURST_XC0 ( 0x1 << 4 ) /* (TC) XC0 is ANDed with the selected clock */ +#define AT91C_TC_BURST_XC1 ( 0x2 << 4 ) /* (TC) XC1 is ANDed with the selected clock */ +#define AT91C_TC_BURST_XC2 ( 0x3 << 4 ) /* (TC) XC2 is ANDed with the selected clock */ +#define AT91C_TC_CPCSTOP ( 0x1 << 6 ) /* (TC) Counter Clock Stopped with RC Compare */ +#define AT91C_TC_LDBSTOP ( 0x1 << 6 ) /* (TC) Counter Clock Stopped with RB Loading */ +#define AT91C_TC_CPCDIS ( 0x1 << 7 ) /* (TC) Counter Clock Disable with RC Compare */ +#define AT91C_TC_LDBDIS ( 0x1 << 7 ) /* (TC) Counter Clock Disabled with RB Loading */ +#define AT91C_TC_ETRGEDG ( 0x3 << 8 ) /* (TC) External Trigger Edge Selection */ +#define AT91C_TC_ETRGEDG_NONE ( 0x0 << 8 ) /* (TC) Edge: None */ +#define AT91C_TC_ETRGEDG_RISING ( 0x1 << 8 ) /* (TC) Edge: rising edge */ +#define AT91C_TC_ETRGEDG_FALLING ( 0x2 << 8 ) /* (TC) Edge: falling edge */ +#define AT91C_TC_ETRGEDG_BOTH ( 0x3 << 8 ) /* (TC) Edge: each edge */ +#define AT91C_TC_EEVTEDG ( 0x3 << 8 ) /* (TC) External Event Edge Selection */ +#define AT91C_TC_EEVTEDG_NONE ( 0x0 << 8 ) /* (TC) Edge: None */ +#define AT91C_TC_EEVTEDG_RISING ( 0x1 << 8 ) /* (TC) Edge: rising edge */ +#define AT91C_TC_EEVTEDG_FALLING ( 0x2 << 8 ) /* (TC) Edge: falling edge */ +#define AT91C_TC_EEVTEDG_BOTH ( 0x3 << 8 ) /* (TC) Edge: each edge */ +#define AT91C_TC_EEVT ( 0x3 << 10 ) /* (TC) External Event Selection */ +#define AT91C_TC_EEVT_TIOB ( 0x0 << 10 ) /* (TC) Signal selected as external event: TIOB TIOB direction: input */ +#define AT91C_TC_EEVT_XC0 ( 0x1 << 10 ) /* (TC) Signal selected as external event: XC0 TIOB direction: output */ +#define AT91C_TC_EEVT_XC1 ( 0x2 << 10 ) /* (TC) Signal selected as external event: XC1 TIOB direction: output */ +#define AT91C_TC_EEVT_XC2 ( 0x3 << 10 ) /* (TC) Signal selected as external event: XC2 TIOB direction: output */ +#define AT91C_TC_ABETRG ( 0x1 << 10 ) /* (TC) TIOA or TIOB External Trigger Selection */ +#define AT91C_TC_ENETRG ( 0x1 << 12 ) /* (TC) External Event Trigger enable */ +#define AT91C_TC_WAVESEL ( 0x3 << 13 ) /* (TC) Waveform Selection */ +#define AT91C_TC_WAVESEL_UP ( 0x0 << 13 ) /* (TC) UP mode without atomatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UPDOWN ( 0x1 << 13 ) /* (TC) UPDOWN mode without automatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UP_AUTO ( 0x2 << 13 ) /* (TC) UP mode with automatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UPDOWN_AUTO ( 0x3 << 13 ) /* (TC) UPDOWN mode with automatic trigger on RC Compare */ +#define AT91C_TC_CPCTRG ( 0x1 << 14 ) /* (TC) RC Compare Trigger Enable */ +#define AT91C_TC_WAVE ( 0x1 << 15 ) /* (TC) */ +#define AT91C_TC_ACPA ( 0x3 << 16 ) /* (TC) RA Compare Effect on TIOA */ +#define AT91C_TC_ACPA_NONE ( 0x0 << 16 ) /* (TC) Effect: none */ +#define AT91C_TC_ACPA_SET ( 0x1 << 16 ) /* (TC) Effect: set */ +#define AT91C_TC_ACPA_CLEAR ( 0x2 << 16 ) /* (TC) Effect: clear */ +#define AT91C_TC_ACPA_TOGGLE ( 0x3 << 16 ) /* (TC) Effect: toggle */ +#define AT91C_TC_LDRA ( 0x3 << 16 ) /* (TC) RA Loading Selection */ +#define AT91C_TC_LDRA_NONE ( 0x0 << 16 ) /* (TC) Edge: None */ +#define AT91C_TC_LDRA_RISING ( 0x1 << 16 ) /* (TC) Edge: rising edge of TIOA */ +#define AT91C_TC_LDRA_FALLING ( 0x2 << 16 ) /* (TC) Edge: falling edge of TIOA */ +#define AT91C_TC_LDRA_BOTH ( 0x3 << 16 ) /* (TC) Edge: each edge of TIOA */ +#define AT91C_TC_ACPC ( 0x3 << 18 ) /* (TC) RC Compare Effect on TIOA */ +#define AT91C_TC_ACPC_NONE ( 0x0 << 18 ) /* (TC) Effect: none */ +#define AT91C_TC_ACPC_SET ( 0x1 << 18 ) /* (TC) Effect: set */ +#define AT91C_TC_ACPC_CLEAR ( 0x2 << 18 ) /* (TC) Effect: clear */ +#define AT91C_TC_ACPC_TOGGLE ( 0x3 << 18 ) /* (TC) Effect: toggle */ +#define AT91C_TC_LDRB ( 0x3 << 18 ) /* (TC) RB Loading Selection */ +#define AT91C_TC_LDRB_NONE ( 0x0 << 18 ) /* (TC) Edge: None */ +#define AT91C_TC_LDRB_RISING ( 0x1 << 18 ) /* (TC) Edge: rising edge of TIOA */ +#define AT91C_TC_LDRB_FALLING ( 0x2 << 18 ) /* (TC) Edge: falling edge of TIOA */ +#define AT91C_TC_LDRB_BOTH ( 0x3 << 18 ) /* (TC) Edge: each edge of TIOA */ +#define AT91C_TC_AEEVT ( 0x3 << 20 ) /* (TC) External Event Effect on TIOA */ +#define AT91C_TC_AEEVT_NONE ( 0x0 << 20 ) /* (TC) Effect: none */ +#define AT91C_TC_AEEVT_SET ( 0x1 << 20 ) /* (TC) Effect: set */ +#define AT91C_TC_AEEVT_CLEAR ( 0x2 << 20 ) /* (TC) Effect: clear */ +#define AT91C_TC_AEEVT_TOGGLE ( 0x3 << 20 ) /* (TC) Effect: toggle */ +#define AT91C_TC_ASWTRG ( 0x3 << 22 ) /* (TC) Software Trigger Effect on TIOA */ +#define AT91C_TC_ASWTRG_NONE ( 0x0 << 22 ) /* (TC) Effect: none */ +#define AT91C_TC_ASWTRG_SET ( 0x1 << 22 ) /* (TC) Effect: set */ +#define AT91C_TC_ASWTRG_CLEAR ( 0x2 << 22 ) /* (TC) Effect: clear */ +#define AT91C_TC_ASWTRG_TOGGLE ( 0x3 << 22 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BCPB ( 0x3 << 24 ) /* (TC) RB Compare Effect on TIOB */ +#define AT91C_TC_BCPB_NONE ( 0x0 << 24 ) /* (TC) Effect: none */ +#define AT91C_TC_BCPB_SET ( 0x1 << 24 ) /* (TC) Effect: set */ +#define AT91C_TC_BCPB_CLEAR ( 0x2 << 24 ) /* (TC) Effect: clear */ +#define AT91C_TC_BCPB_TOGGLE ( 0x3 << 24 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BCPC ( 0x3 << 26 ) /* (TC) RC Compare Effect on TIOB */ +#define AT91C_TC_BCPC_NONE ( 0x0 << 26 ) /* (TC) Effect: none */ +#define AT91C_TC_BCPC_SET ( 0x1 << 26 ) /* (TC) Effect: set */ +#define AT91C_TC_BCPC_CLEAR ( 0x2 << 26 ) /* (TC) Effect: clear */ +#define AT91C_TC_BCPC_TOGGLE ( 0x3 << 26 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BEEVT ( 0x3 << 28 ) /* (TC) External Event Effect on TIOB */ +#define AT91C_TC_BEEVT_NONE ( 0x0 << 28 ) /* (TC) Effect: none */ +#define AT91C_TC_BEEVT_SET ( 0x1 << 28 ) /* (TC) Effect: set */ +#define AT91C_TC_BEEVT_CLEAR ( 0x2 << 28 ) /* (TC) Effect: clear */ +#define AT91C_TC_BEEVT_TOGGLE ( 0x3 << 28 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BSWTRG ( 0x3 << 30 ) /* (TC) Software Trigger Effect on TIOB */ +#define AT91C_TC_BSWTRG_NONE ( 0x0 << 30 ) /* (TC) Effect: none */ +#define AT91C_TC_BSWTRG_SET ( 0x1 << 30 ) /* (TC) Effect: set */ +#define AT91C_TC_BSWTRG_CLEAR ( 0x2 << 30 ) /* (TC) Effect: clear */ +#define AT91C_TC_BSWTRG_TOGGLE ( 0x3 << 30 ) /* (TC) Effect: toggle */ +/* -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- */ +#define AT91C_TC_COVFS ( 0x1 << 0 ) /* (TC) Counter Overflow */ +#define AT91C_TC_LOVRS ( 0x1 << 1 ) /* (TC) Load Overrun */ +#define AT91C_TC_CPAS ( 0x1 << 2 ) /* (TC) RA Compare */ +#define AT91C_TC_CPBS ( 0x1 << 3 ) /* (TC) RB Compare */ +#define AT91C_TC_CPCS ( 0x1 << 4 ) /* (TC) RC Compare */ +#define AT91C_TC_LDRAS ( 0x1 << 5 ) /* (TC) RA Loading */ +#define AT91C_TC_LDRBS ( 0x1 << 6 ) /* (TC) RB Loading */ +#define AT91C_TC_ETRGS ( 0x1 << 7 ) /* (TC) External Trigger */ +#define AT91C_TC_CLKSTA ( 0x1 << 16 ) /* (TC) Clock Enabling */ +#define AT91C_TC_MTIOA ( 0x1 << 17 ) /* (TC) TIOA Mirror */ +#define AT91C_TC_MTIOB ( 0x1 << 18 ) /* (TC) TIOA Mirror */ +/* -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- */ +/* -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- */ +/* -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Timer Counter Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_TCB structure *** */ +#define TCB_TC0 ( 0 ) /* TC Channel 0 */ +#define TCB_TC1 ( 64 ) /* TC Channel 1 */ +#define TCB_TC2 ( 128 ) /* TC Channel 2 */ +#define TCB_BCR ( 192 ) /* TC Block Control Register */ +#define TCB_BMR ( 196 ) /* TC Block Mode Register */ +/* -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- */ +#define AT91C_TCB_SYNC ( 0x1 << 0 ) /* (TCB) Synchro Command */ +/* -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- */ +#define AT91C_TCB_TC0XC0S ( 0x3 << 0 ) /* (TCB) External Clock Signal 0 Selection */ +#define AT91C_TCB_TC0XC0S_TCLK0 ( 0x0 ) /* (TCB) TCLK0 connected to XC0 */ +#define AT91C_TCB_TC0XC0S_NONE ( 0x1 ) /* (TCB) None signal connected to XC0 */ +#define AT91C_TCB_TC0XC0S_TIOA1 ( 0x2 ) /* (TCB) TIOA1 connected to XC0 */ +#define AT91C_TCB_TC0XC0S_TIOA2 ( 0x3 ) /* (TCB) TIOA2 connected to XC0 */ +#define AT91C_TCB_TC1XC1S ( 0x3 << 2 ) /* (TCB) External Clock Signal 1 Selection */ +#define AT91C_TCB_TC1XC1S_TCLK1 ( 0x0 << 2 ) /* (TCB) TCLK1 connected to XC1 */ +#define AT91C_TCB_TC1XC1S_NONE ( 0x1 << 2 ) /* (TCB) None signal connected to XC1 */ +#define AT91C_TCB_TC1XC1S_TIOA0 ( 0x2 << 2 ) /* (TCB) TIOA0 connected to XC1 */ +#define AT91C_TCB_TC1XC1S_TIOA2 ( 0x3 << 2 ) /* (TCB) TIOA2 connected to XC1 */ +#define AT91C_TCB_TC2XC2S ( 0x3 << 4 ) /* (TCB) External Clock Signal 2 Selection */ +#define AT91C_TCB_TC2XC2S_TCLK2 ( 0x0 << 4 ) /* (TCB) TCLK2 connected to XC2 */ +#define AT91C_TCB_TC2XC2S_NONE ( 0x1 << 4 ) /* (TCB) None signal connected to XC2 */ +#define AT91C_TCB_TC2XC2S_TIOA0 ( 0x2 << 4 ) /* (TCB) TIOA0 connected to XC2 */ +#define AT91C_TCB_TC2XC2S_TIOA1 ( 0x3 << 4 ) /* (TCB) TIOA2 connected to XC2 */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_CAN_MB structure *** */ +#define CAN_MB_MMR ( 0 ) /* MailBox Mode Register */ +#define CAN_MB_MAM ( 4 ) /* MailBox Acceptance Mask Register */ +#define CAN_MB_MID ( 8 ) /* MailBox ID Register */ +#define CAN_MB_MFID ( 12 ) /* MailBox Family ID Register */ +#define CAN_MB_MSR ( 16 ) /* MailBox Status Register */ +#define CAN_MB_MDL ( 20 ) /* MailBox Data Low Register */ +#define CAN_MB_MDH ( 24 ) /* MailBox Data High Register */ +#define CAN_MB_MCR ( 28 ) /* MailBox Control Register */ +/* -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- */ +#define AT91C_CAN_MTIMEMARK ( 0xFFFF << 0 ) /* (CAN_MB) Mailbox Timemark */ +#define AT91C_CAN_PRIOR ( 0xF << 16 ) /* (CAN_MB) Mailbox Priority */ +#define AT91C_CAN_MOT ( 0x7 << 24 ) /* (CAN_MB) Mailbox Object Type */ +#define AT91C_CAN_MOT_DIS ( 0x0 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_RX ( 0x1 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_RXOVERWRITE ( 0x2 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_TX ( 0x3 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_CONSUMER ( 0x4 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_PRODUCER ( 0x5 << 24 ) /* (CAN_MB) */ +/* -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- */ +#define AT91C_CAN_MIDvB ( 0x3FFFF << 0 ) /* (CAN_MB) Complementary bits for identifier in extended mode */ +#define AT91C_CAN_MIDvA ( 0x7FF << 18 ) /* (CAN_MB) Identifier for standard frame mode */ +#define AT91C_CAN_MIDE ( 0x1 << 29 ) /* (CAN_MB) Identifier Version */ +/* -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- */ +/* -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- */ +/* -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- */ +#define AT91C_CAN_MTIMESTAMP ( 0xFFFF << 0 ) /* (CAN_MB) Timer Value */ +#define AT91C_CAN_MDLC ( 0xF << 16 ) /* (CAN_MB) Mailbox Data Length Code */ +#define AT91C_CAN_MRTR ( 0x1 << 20 ) /* (CAN_MB) Mailbox Remote Transmission Request */ +#define AT91C_CAN_MABT ( 0x1 << 22 ) /* (CAN_MB) Mailbox Message Abort */ +#define AT91C_CAN_MRDY ( 0x1 << 23 ) /* (CAN_MB) Mailbox Ready */ +#define AT91C_CAN_MMI ( 0x1 << 24 ) /* (CAN_MB) Mailbox Message Ignored */ +/* -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- */ +/* -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- */ +/* -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- */ +#define AT91C_CAN_MACR ( 0x1 << 22 ) /* (CAN_MB) Abort Request for Mailbox */ +#define AT91C_CAN_MTCR ( 0x1 << 23 ) /* (CAN_MB) Mailbox Transfer Command */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Control Area Network Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_CAN structure *** */ +#define CAN_MR ( 0 ) /* Mode Register */ +#define CAN_IER ( 4 ) /* Interrupt Enable Register */ +#define CAN_IDR ( 8 ) /* Interrupt Disable Register */ +#define CAN_IMR ( 12 ) /* Interrupt Mask Register */ +#define CAN_SR ( 16 ) /* Status Register */ +#define CAN_BR ( 20 ) /* Baudrate Register */ +#define CAN_TIM ( 24 ) /* Timer Register */ +#define CAN_TIMESTP ( 28 ) /* Time Stamp Register */ +#define CAN_ECR ( 32 ) /* Error Counter Register */ +#define CAN_TCR ( 36 ) /* Transfer Command Register */ +#define CAN_ACR ( 40 ) /* Abort Command Register */ +#define CAN_VR ( 252 ) /* Version Register */ +#define CAN_MB0 ( 512 ) /* CAN Mailbox 0 */ +#define CAN_MB1 ( 544 ) /* CAN Mailbox 1 */ +#define CAN_MB2 ( 576 ) /* CAN Mailbox 2 */ +#define CAN_MB3 ( 608 ) /* CAN Mailbox 3 */ +#define CAN_MB4 ( 640 ) /* CAN Mailbox 4 */ +#define CAN_MB5 ( 672 ) /* CAN Mailbox 5 */ +#define CAN_MB6 ( 704 ) /* CAN Mailbox 6 */ +#define CAN_MB7 ( 736 ) /* CAN Mailbox 7 */ +#define CAN_MB8 ( 768 ) /* CAN Mailbox 8 */ +#define CAN_MB9 ( 800 ) /* CAN Mailbox 9 */ +#define CAN_MB10 ( 832 ) /* CAN Mailbox 10 */ +#define CAN_MB11 ( 864 ) /* CAN Mailbox 11 */ +#define CAN_MB12 ( 896 ) /* CAN Mailbox 12 */ +#define CAN_MB13 ( 928 ) /* CAN Mailbox 13 */ +#define CAN_MB14 ( 960 ) /* CAN Mailbox 14 */ +#define CAN_MB15 ( 992 ) /* CAN Mailbox 15 */ +/* -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- */ +#define AT91C_CAN_CANEN ( 0x1 << 0 ) /* (CAN) CAN Controller Enable */ +#define AT91C_CAN_LPM ( 0x1 << 1 ) /* (CAN) Disable/Enable Low Power Mode */ +#define AT91C_CAN_ABM ( 0x1 << 2 ) /* (CAN) Disable/Enable Autobaud/Listen Mode */ +#define AT91C_CAN_OVL ( 0x1 << 3 ) /* (CAN) Disable/Enable Overload Frame */ +#define AT91C_CAN_TEOF ( 0x1 << 4 ) /* (CAN) Time Stamp messages at each end of Frame */ +#define AT91C_CAN_TTM ( 0x1 << 5 ) /* (CAN) Disable/Enable Time Trigger Mode */ +#define AT91C_CAN_TIMFRZ ( 0x1 << 6 ) /* (CAN) Enable Timer Freeze */ +#define AT91C_CAN_DRPT ( 0x1 << 7 ) /* (CAN) Disable Repeat */ +/* -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- */ +#define AT91C_CAN_MB0 ( 0x1 << 0 ) /* (CAN) Mailbox 0 Flag */ +#define AT91C_CAN_MB1 ( 0x1 << 1 ) /* (CAN) Mailbox 1 Flag */ +#define AT91C_CAN_MB2 ( 0x1 << 2 ) /* (CAN) Mailbox 2 Flag */ +#define AT91C_CAN_MB3 ( 0x1 << 3 ) /* (CAN) Mailbox 3 Flag */ +#define AT91C_CAN_MB4 ( 0x1 << 4 ) /* (CAN) Mailbox 4 Flag */ +#define AT91C_CAN_MB5 ( 0x1 << 5 ) /* (CAN) Mailbox 5 Flag */ +#define AT91C_CAN_MB6 ( 0x1 << 6 ) /* (CAN) Mailbox 6 Flag */ +#define AT91C_CAN_MB7 ( 0x1 << 7 ) /* (CAN) Mailbox 7 Flag */ +#define AT91C_CAN_MB8 ( 0x1 << 8 ) /* (CAN) Mailbox 8 Flag */ +#define AT91C_CAN_MB9 ( 0x1 << 9 ) /* (CAN) Mailbox 9 Flag */ +#define AT91C_CAN_MB10 ( 0x1 << 10 ) /* (CAN) Mailbox 10 Flag */ +#define AT91C_CAN_MB11 ( 0x1 << 11 ) /* (CAN) Mailbox 11 Flag */ +#define AT91C_CAN_MB12 ( 0x1 << 12 ) /* (CAN) Mailbox 12 Flag */ +#define AT91C_CAN_MB13 ( 0x1 << 13 ) /* (CAN) Mailbox 13 Flag */ +#define AT91C_CAN_MB14 ( 0x1 << 14 ) /* (CAN) Mailbox 14 Flag */ +#define AT91C_CAN_MB15 ( 0x1 << 15 ) /* (CAN) Mailbox 15 Flag */ +#define AT91C_CAN_ERRA ( 0x1 << 16 ) /* (CAN) Error Active Mode Flag */ +#define AT91C_CAN_WARN ( 0x1 << 17 ) /* (CAN) Warning Limit Flag */ +#define AT91C_CAN_ERRP ( 0x1 << 18 ) /* (CAN) Error Passive Mode Flag */ +#define AT91C_CAN_BOFF ( 0x1 << 19 ) /* (CAN) Bus Off Mode Flag */ +#define AT91C_CAN_SLEEP ( 0x1 << 20 ) /* (CAN) Sleep Flag */ +#define AT91C_CAN_WAKEUP ( 0x1 << 21 ) /* (CAN) Wakeup Flag */ +#define AT91C_CAN_TOVF ( 0x1 << 22 ) /* (CAN) Timer Overflow Flag */ +#define AT91C_CAN_TSTP ( 0x1 << 23 ) /* (CAN) Timestamp Flag */ +#define AT91C_CAN_CERR ( 0x1 << 24 ) /* (CAN) CRC Error */ +#define AT91C_CAN_SERR ( 0x1 << 25 ) /* (CAN) Stuffing Error */ +#define AT91C_CAN_AERR ( 0x1 << 26 ) /* (CAN) Acknowledgment Error */ +#define AT91C_CAN_FERR ( 0x1 << 27 ) /* (CAN) Form Error */ +#define AT91C_CAN_BERR ( 0x1 << 28 ) /* (CAN) Bit Error */ +/* -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- */ +/* -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- */ +/* -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- */ +#define AT91C_CAN_RBSY ( 0x1 << 29 ) /* (CAN) Receiver Busy */ +#define AT91C_CAN_TBSY ( 0x1 << 30 ) /* (CAN) Transmitter Busy */ +#define AT91C_CAN_OVLY ( 0x1 << 31 ) /* (CAN) Overload Busy */ +/* -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- */ +#define AT91C_CAN_PHASE2 ( 0x7 << 0 ) /* (CAN) Phase 2 segment */ +#define AT91C_CAN_PHASE1 ( 0x7 << 4 ) /* (CAN) Phase 1 segment */ +#define AT91C_CAN_PROPAG ( 0x7 << 8 ) /* (CAN) Programmation time segment */ +#define AT91C_CAN_SYNC ( 0x3 << 12 ) /* (CAN) Re-synchronization jump width segment */ +#define AT91C_CAN_BRP ( 0x7F << 16 ) /* (CAN) Baudrate Prescaler */ +#define AT91C_CAN_SMP ( 0x1 << 24 ) /* (CAN) Sampling mode */ +/* -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- */ +#define AT91C_CAN_TIMER ( 0xFFFF << 0 ) /* (CAN) Timer field */ +/* -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- */ +/* -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- */ +#define AT91C_CAN_REC ( 0xFF << 0 ) /* (CAN) Receive Error Counter */ +#define AT91C_CAN_TEC ( 0xFF << 16 ) /* (CAN) Transmit Error Counter */ +/* -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- */ +#define AT91C_CAN_TIMRST ( 0x1 << 31 ) /* (CAN) Timer Reset Field */ +/* -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_EMAC structure *** */ +#define EMAC_NCR ( 0 ) /* Network Control Register */ +#define EMAC_NCFGR ( 4 ) /* Network Configuration Register */ +#define EMAC_NSR ( 8 ) /* Network Status Register */ +#define EMAC_TSR ( 20 ) /* Transmit Status Register */ +#define EMAC_RBQP ( 24 ) /* Receive Buffer Queue Pointer */ +#define EMAC_TBQP ( 28 ) /* Transmit Buffer Queue Pointer */ +#define EMAC_RSR ( 32 ) /* Receive Status Register */ +#define EMAC_ISR ( 36 ) /* Interrupt Status Register */ +#define EMAC_IER ( 40 ) /* Interrupt Enable Register */ +#define EMAC_IDR ( 44 ) /* Interrupt Disable Register */ +#define EMAC_IMR ( 48 ) /* Interrupt Mask Register */ +#define EMAC_MAN ( 52 ) /* PHY Maintenance Register */ +#define EMAC_PTR ( 56 ) /* Pause Time Register */ +#define EMAC_PFR ( 60 ) /* Pause Frames received Register */ +#define EMAC_FTO ( 64 ) /* Frames Transmitted OK Register */ +#define EMAC_SCF ( 68 ) /* Single Collision Frame Register */ +#define EMAC_MCF ( 72 ) /* Multiple Collision Frame Register */ +#define EMAC_FRO ( 76 ) /* Frames Received OK Register */ +#define EMAC_FCSE ( 80 ) /* Frame Check Sequence Error Register */ +#define EMAC_ALE ( 84 ) /* Alignment Error Register */ +#define EMAC_DTF ( 88 ) /* Deferred Transmission Frame Register */ +#define EMAC_LCOL ( 92 ) /* Late Collision Register */ +#define EMAC_ECOL ( 96 ) /* Excessive Collision Register */ +#define EMAC_TUND ( 100 ) /* Transmit Underrun Error Register */ +#define EMAC_CSE ( 104 ) /* Carrier Sense Error Register */ +#define EMAC_RRE ( 108 ) /* Receive Resource Error Register */ +#define EMAC_ROV ( 112 ) /* Receive Overrun Errors Register */ +#define EMAC_RSE ( 116 ) /* Receive Symbol Errors Register */ +#define EMAC_ELE ( 120 ) /* Excessive Length Errors Register */ +#define EMAC_RJA ( 124 ) /* Receive Jabbers Register */ +#define EMAC_USF ( 128 ) /* Undersize Frames Register */ +#define EMAC_STE ( 132 ) /* SQE Test Error Register */ +#define EMAC_RLE ( 136 ) /* Receive Length Field Mismatch Register */ +#define EMAC_TPF ( 140 ) /* Transmitted Pause Frames Register */ +#define EMAC_HRB ( 144 ) /* Hash Address Bottom[31:0] */ +#define EMAC_HRT ( 148 ) /* Hash Address Top[63:32] */ +#define EMAC_SA1L ( 152 ) /* Specific Address 1 Bottom, First 4 bytes */ +#define EMAC_SA1H ( 156 ) /* Specific Address 1 Top, Last 2 bytes */ +#define EMAC_SA2L ( 160 ) /* Specific Address 2 Bottom, First 4 bytes */ +#define EMAC_SA2H ( 164 ) /* Specific Address 2 Top, Last 2 bytes */ +#define EMAC_SA3L ( 168 ) /* Specific Address 3 Bottom, First 4 bytes */ +#define EMAC_SA3H ( 172 ) /* Specific Address 3 Top, Last 2 bytes */ +#define EMAC_SA4L ( 176 ) /* Specific Address 4 Bottom, First 4 bytes */ +#define EMAC_SA4H ( 180 ) /* Specific Address 4 Top, Last 2 bytes */ +#define EMAC_TID ( 184 ) /* Type ID Checking Register */ +#define EMAC_TPQ ( 188 ) /* Transmit Pause Quantum Register */ +#define EMAC_USRIO ( 192 ) /* USER Input/Output Register */ +#define EMAC_WOL ( 196 ) /* Wake On LAN Register */ +#define EMAC_REV ( 252 ) /* Revision Register */ +/* -------- EMAC_NCR : (EMAC Offset: 0x0) -------- */ +#define AT91C_EMAC_LB ( 0x1 << 0 ) /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */ +#define AT91C_EMAC_LLB ( 0x1 << 1 ) /* (EMAC) Loopback local. */ +#define AT91C_EMAC_RE ( 0x1 << 2 ) /* (EMAC) Receive enable. */ +#define AT91C_EMAC_TE ( 0x1 << 3 ) /* (EMAC) Transmit enable. */ +#define AT91C_EMAC_MPE ( 0x1 << 4 ) /* (EMAC) Management port enable. */ +#define AT91C_EMAC_CLRSTAT ( 0x1 << 5 ) /* (EMAC) Clear statistics registers. */ +#define AT91C_EMAC_INCSTAT ( 0x1 << 6 ) /* (EMAC) Increment statistics registers. */ +#define AT91C_EMAC_WESTAT ( 0x1 << 7 ) /* (EMAC) Write enable for statistics registers. */ +#define AT91C_EMAC_BP ( 0x1 << 8 ) /* (EMAC) Back pressure. */ +#define AT91C_EMAC_TSTART ( 0x1 << 9 ) /* (EMAC) Start Transmission. */ +#define AT91C_EMAC_THALT ( 0x1 << 10 ) /* (EMAC) Transmission Halt. */ +#define AT91C_EMAC_TPFR ( 0x1 << 11 ) /* (EMAC) Transmit pause frame */ +#define AT91C_EMAC_TZQ ( 0x1 << 12 ) /* (EMAC) Transmit zero quantum pause frame */ +/* -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- */ +#define AT91C_EMAC_SPD ( 0x1 << 0 ) /* (EMAC) Speed. */ +#define AT91C_EMAC_FD ( 0x1 << 1 ) /* (EMAC) Full duplex. */ +#define AT91C_EMAC_JFRAME ( 0x1 << 3 ) /* (EMAC) Jumbo Frames. */ +#define AT91C_EMAC_CAF ( 0x1 << 4 ) /* (EMAC) Copy all frames. */ +#define AT91C_EMAC_NBC ( 0x1 << 5 ) /* (EMAC) No broadcast. */ +#define AT91C_EMAC_MTI ( 0x1 << 6 ) /* (EMAC) Multicast hash event enable */ +#define AT91C_EMAC_UNI ( 0x1 << 7 ) /* (EMAC) Unicast hash enable. */ +#define AT91C_EMAC_BIG ( 0x1 << 8 ) /* (EMAC) Receive 1522 bytes. */ +#define AT91C_EMAC_EAE ( 0x1 << 9 ) /* (EMAC) External address match enable. */ +#define AT91C_EMAC_CLK ( 0x3 << 10 ) /* (EMAC) */ +#define AT91C_EMAC_CLK_HCLK_8 ( 0x0 << 10 ) /* (EMAC) HCLK divided by 8 */ +#define AT91C_EMAC_CLK_HCLK_16 ( 0x1 << 10 ) /* (EMAC) HCLK divided by 16 */ +#define AT91C_EMAC_CLK_HCLK_32 ( 0x2 << 10 ) /* (EMAC) HCLK divided by 32 */ +#define AT91C_EMAC_CLK_HCLK_64 ( 0x3 << 10 ) /* (EMAC) HCLK divided by 64 */ +#define AT91C_EMAC_RTY ( 0x1 << 12 ) /* (EMAC) */ +#define AT91C_EMAC_PAE ( 0x1 << 13 ) /* (EMAC) */ +#define AT91C_EMAC_RBOF ( 0x3 << 14 ) /* (EMAC) */ +#define AT91C_EMAC_RBOF_OFFSET_0 ( 0x0 << 14 ) /* (EMAC) no offset from start of receive buffer */ +#define AT91C_EMAC_RBOF_OFFSET_1 ( 0x1 << 14 ) /* (EMAC) one byte offset from start of receive buffer */ +#define AT91C_EMAC_RBOF_OFFSET_2 ( 0x2 << 14 ) /* (EMAC) two bytes offset from start of receive buffer */ +#define AT91C_EMAC_RBOF_OFFSET_3 ( 0x3 << 14 ) /* (EMAC) three bytes offset from start of receive buffer */ +#define AT91C_EMAC_RLCE ( 0x1 << 16 ) /* (EMAC) Receive Length field Checking Enable */ +#define AT91C_EMAC_DRFCS ( 0x1 << 17 ) /* (EMAC) Discard Receive FCS */ +#define AT91C_EMAC_EFRHD ( 0x1 << 18 ) /* (EMAC) */ +#define AT91C_EMAC_IRXFCS ( 0x1 << 19 ) /* (EMAC) Ignore RX FCS */ +/* -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- */ +#define AT91C_EMAC_LINKR ( 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_MDIO ( 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_IDLE ( 0x1 << 2 ) /* (EMAC) */ +/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- */ +#define AT91C_EMAC_UBR ( 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_COL ( 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_RLES ( 0x1 << 2 ) /* (EMAC) */ +#define AT91C_EMAC_TGO ( 0x1 << 3 ) /* (EMAC) Transmit Go */ +#define AT91C_EMAC_BEX ( 0x1 << 4 ) /* (EMAC) Buffers exhausted mid frame */ +#define AT91C_EMAC_COMP ( 0x1 << 5 ) /* (EMAC) */ +#define AT91C_EMAC_UND ( 0x1 << 6 ) /* (EMAC) */ +/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */ +#define AT91C_EMAC_BNA ( 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_REC ( 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_OVR ( 0x1 << 2 ) /* (EMAC) */ +/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */ +#define AT91C_EMAC_MFD ( 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_RCOMP ( 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_RXUBR ( 0x1 << 2 ) /* (EMAC) */ +#define AT91C_EMAC_TXUBR ( 0x1 << 3 ) /* (EMAC) */ +#define AT91C_EMAC_TUNDR ( 0x1 << 4 ) /* (EMAC) */ +#define AT91C_EMAC_RLEX ( 0x1 << 5 ) /* (EMAC) */ +#define AT91C_EMAC_TXERR ( 0x1 << 6 ) /* (EMAC) */ +#define AT91C_EMAC_TCOMP ( 0x1 << 7 ) /* (EMAC) */ +#define AT91C_EMAC_LINK ( 0x1 << 9 ) /* (EMAC) */ +#define AT91C_EMAC_ROVR ( 0x1 << 10 ) /* (EMAC) */ +#define AT91C_EMAC_HRESP ( 0x1 << 11 ) /* (EMAC) */ +#define AT91C_EMAC_PFRE ( 0x1 << 12 ) /* (EMAC) */ +#define AT91C_EMAC_PTZ ( 0x1 << 13 ) /* (EMAC) */ +/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */ +/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */ +/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */ +/* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */ +#define AT91C_EMAC_DATA ( 0xFFFF << 0 ) /* (EMAC) */ +#define AT91C_EMAC_CODE ( 0x3 << 16 ) /* (EMAC) */ +#define AT91C_EMAC_REGA ( 0x1F << 18 ) /* (EMAC) */ +#define AT91C_EMAC_PHYA ( 0x1F << 23 ) /* (EMAC) */ +#define AT91C_EMAC_RW ( 0x3 << 28 ) /* (EMAC) */ +#define AT91C_EMAC_SOF ( 0x3 << 30 ) /* (EMAC) */ +/* -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- */ +#define AT91C_EMAC_RMII ( 0x1 << 0 ) /* (EMAC) Reduce MII */ +/* -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- */ +#define AT91C_EMAC_IP ( 0xFFFF << 0 ) /* (EMAC) ARP request IP address */ +#define AT91C_EMAC_MAG ( 0x1 << 16 ) /* (EMAC) Magic packet event enable */ +#define AT91C_EMAC_ARP ( 0x1 << 17 ) /* (EMAC) ARP request event enable */ +#define AT91C_EMAC_SA1 ( 0x1 << 18 ) /* (EMAC) Specific address register 1 event enable */ +/* -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- */ +#define AT91C_EMAC_REVREF ( 0xFFFF << 0 ) /* (EMAC) */ +#define AT91C_EMAC_PARTREF ( 0xFFFF << 16 ) /* (EMAC) */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Analog to Digital Convertor */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_ADC structure *** */ +#define ADC_CR ( 0 ) /* ADC Control Register */ +#define ADC_MR ( 4 ) /* ADC Mode Register */ +#define ADC_CHER ( 16 ) /* ADC Channel Enable Register */ +#define ADC_CHDR ( 20 ) /* ADC Channel Disable Register */ +#define ADC_CHSR ( 24 ) /* ADC Channel Status Register */ +#define ADC_SR ( 28 ) /* ADC Status Register */ +#define ADC_LCDR ( 32 ) /* ADC Last Converted Data Register */ +#define ADC_IER ( 36 ) /* ADC Interrupt Enable Register */ +#define ADC_IDR ( 40 ) /* ADC Interrupt Disable Register */ +#define ADC_IMR ( 44 ) /* ADC Interrupt Mask Register */ +#define ADC_CDR0 ( 48 ) /* ADC Channel Data Register 0 */ +#define ADC_CDR1 ( 52 ) /* ADC Channel Data Register 1 */ +#define ADC_CDR2 ( 56 ) /* ADC Channel Data Register 2 */ +#define ADC_CDR3 ( 60 ) /* ADC Channel Data Register 3 */ +#define ADC_CDR4 ( 64 ) /* ADC Channel Data Register 4 */ +#define ADC_CDR5 ( 68 ) /* ADC Channel Data Register 5 */ +#define ADC_CDR6 ( 72 ) /* ADC Channel Data Register 6 */ +#define ADC_CDR7 ( 76 ) /* ADC Channel Data Register 7 */ +#define ADC_RPR ( 256 ) /* Receive Pointer Register */ +#define ADC_RCR ( 260 ) /* Receive Counter Register */ +#define ADC_TPR ( 264 ) /* Transmit Pointer Register */ +#define ADC_TCR ( 268 ) /* Transmit Counter Register */ +#define ADC_RNPR ( 272 ) /* Receive Next Pointer Register */ +#define ADC_RNCR ( 276 ) /* Receive Next Counter Register */ +#define ADC_TNPR ( 280 ) /* Transmit Next Pointer Register */ +#define ADC_TNCR ( 284 ) /* Transmit Next Counter Register */ +#define ADC_PTCR ( 288 ) /* PDC Transfer Control Register */ +#define ADC_PTSR ( 292 ) /* PDC Transfer Status Register */ +/* -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- */ +#define AT91C_ADC_SWRST ( 0x1 << 0 ) /* (ADC) Software Reset */ +#define AT91C_ADC_START ( 0x1 << 1 ) /* (ADC) Start Conversion */ +/* -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- */ +#define AT91C_ADC_TRGEN ( 0x1 << 0 ) /* (ADC) Trigger Enable */ +#define AT91C_ADC_TRGEN_DIS ( 0x0 ) /* (ADC) Hardware triggers are disabled. Starting a conversion is only possible by software */ +#define AT91C_ADC_TRGEN_EN ( 0x1 ) /* (ADC) Hardware trigger selected by TRGSEL field is enabled. */ +#define AT91C_ADC_TRGSEL ( 0x7 << 1 ) /* (ADC) Trigger Selection */ +#define AT91C_ADC_TRGSEL_TIOA0 ( 0x0 << 1 ) /* (ADC) Selected TRGSEL = TIAO0 */ +#define AT91C_ADC_TRGSEL_TIOA1 ( 0x1 << 1 ) /* (ADC) Selected TRGSEL = TIAO1 */ +#define AT91C_ADC_TRGSEL_TIOA2 ( 0x2 << 1 ) /* (ADC) Selected TRGSEL = TIAO2 */ +#define AT91C_ADC_TRGSEL_TIOA3 ( 0x3 << 1 ) /* (ADC) Selected TRGSEL = TIAO3 */ +#define AT91C_ADC_TRGSEL_TIOA4 ( 0x4 << 1 ) /* (ADC) Selected TRGSEL = TIAO4 */ +#define AT91C_ADC_TRGSEL_TIOA5 ( 0x5 << 1 ) /* (ADC) Selected TRGSEL = TIAO5 */ +#define AT91C_ADC_TRGSEL_EXT ( 0x6 << 1 ) /* (ADC) Selected TRGSEL = External Trigger */ +#define AT91C_ADC_LOWRES ( 0x1 << 4 ) /* (ADC) Resolution. */ +#define AT91C_ADC_LOWRES_10_BIT ( 0x0 << 4 ) /* (ADC) 10-bit resolution */ +#define AT91C_ADC_LOWRES_8_BIT ( 0x1 << 4 ) /* (ADC) 8-bit resolution */ +#define AT91C_ADC_SLEEP ( 0x1 << 5 ) /* (ADC) Sleep Mode */ +#define AT91C_ADC_SLEEP_NORMAL_MODE ( 0x0 << 5 ) /* (ADC) Normal Mode */ +#define AT91C_ADC_SLEEP_MODE ( 0x1 << 5 ) /* (ADC) Sleep Mode */ +#define AT91C_ADC_PRESCAL ( 0x3F << 8 ) /* (ADC) Prescaler rate selection */ +#define AT91C_ADC_STARTUP ( 0x1F << 16 ) /* (ADC) Startup Time */ +#define AT91C_ADC_SHTIM ( 0xF << 24 ) /* (ADC) Sample & Hold Time */ +/* -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- */ +#define AT91C_ADC_CH0 ( 0x1 << 0 ) /* (ADC) Channel 0 */ +#define AT91C_ADC_CH1 ( 0x1 << 1 ) /* (ADC) Channel 1 */ +#define AT91C_ADC_CH2 ( 0x1 << 2 ) /* (ADC) Channel 2 */ +#define AT91C_ADC_CH3 ( 0x1 << 3 ) /* (ADC) Channel 3 */ +#define AT91C_ADC_CH4 ( 0x1 << 4 ) /* (ADC) Channel 4 */ +#define AT91C_ADC_CH5 ( 0x1 << 5 ) /* (ADC) Channel 5 */ +#define AT91C_ADC_CH6 ( 0x1 << 6 ) /* (ADC) Channel 6 */ +#define AT91C_ADC_CH7 ( 0x1 << 7 ) /* (ADC) Channel 7 */ +/* -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- */ +/* -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- */ +/* -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- */ +#define AT91C_ADC_EOC0 ( 0x1 << 0 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC1 ( 0x1 << 1 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC2 ( 0x1 << 2 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC3 ( 0x1 << 3 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC4 ( 0x1 << 4 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC5 ( 0x1 << 5 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC6 ( 0x1 << 6 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC7 ( 0x1 << 7 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_OVRE0 ( 0x1 << 8 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE1 ( 0x1 << 9 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE2 ( 0x1 << 10 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE3 ( 0x1 << 11 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE4 ( 0x1 << 12 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE5 ( 0x1 << 13 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE6 ( 0x1 << 14 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE7 ( 0x1 << 15 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_DRDY ( 0x1 << 16 ) /* (ADC) Data Ready */ +#define AT91C_ADC_GOVRE ( 0x1 << 17 ) /* (ADC) General Overrun */ +#define AT91C_ADC_ENDRX ( 0x1 << 18 ) /* (ADC) End of Receiver Transfer */ +#define AT91C_ADC_RXBUFF ( 0x1 << 19 ) /* (ADC) RXBUFF Interrupt */ +/* -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- */ +#define AT91C_ADC_LDATA ( 0x3FF << 0 ) /* (ADC) Last Data Converted */ +/* -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- */ +/* -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- */ +/* -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- */ +/* -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- */ +#define AT91C_ADC_DATA ( 0x3FF << 0 ) /* (ADC) Converted Data */ +/* -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- */ +/* -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- */ +/* -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- */ +/* -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- */ +/* -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- */ +/* -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- */ +/* -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Advanced Encryption Standard */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_AES structure *** */ +#define AES_CR ( 0 ) /* Control Register */ +#define AES_MR ( 4 ) /* Mode Register */ +#define AES_IER ( 16 ) /* Interrupt Enable Register */ +#define AES_IDR ( 20 ) /* Interrupt Disable Register */ +#define AES_IMR ( 24 ) /* Interrupt Mask Register */ +#define AES_ISR ( 28 ) /* Interrupt Status Register */ +#define AES_KEYWxR ( 32 ) /* Key Word x Register */ +#define AES_IDATAxR ( 64 ) /* Input Data x Register */ +#define AES_ODATAxR ( 80 ) /* Output Data x Register */ +#define AES_IVxR ( 96 ) /* Initialization Vector x Register */ +#define AES_VR ( 252 ) /* AES Version Register */ +#define AES_RPR ( 256 ) /* Receive Pointer Register */ +#define AES_RCR ( 260 ) /* Receive Counter Register */ +#define AES_TPR ( 264 ) /* Transmit Pointer Register */ +#define AES_TCR ( 268 ) /* Transmit Counter Register */ +#define AES_RNPR ( 272 ) /* Receive Next Pointer Register */ +#define AES_RNCR ( 276 ) /* Receive Next Counter Register */ +#define AES_TNPR ( 280 ) /* Transmit Next Pointer Register */ +#define AES_TNCR ( 284 ) /* Transmit Next Counter Register */ +#define AES_PTCR ( 288 ) /* PDC Transfer Control Register */ +#define AES_PTSR ( 292 ) /* PDC Transfer Status Register */ +/* -------- AES_CR : (AES Offset: 0x0) Control Register -------- */ +#define AT91C_AES_START ( 0x1 << 0 ) /* (AES) Starts Processing */ +#define AT91C_AES_SWRST ( 0x1 << 8 ) /* (AES) Software Reset */ +#define AT91C_AES_LOADSEED ( 0x1 << 16 ) /* (AES) Random Number Generator Seed Loading */ +/* -------- AES_MR : (AES Offset: 0x4) Mode Register -------- */ +#define AT91C_AES_CIPHER ( 0x1 << 0 ) /* (AES) Processing Mode */ +#define AT91C_AES_PROCDLY ( 0xF << 4 ) /* (AES) Processing Delay */ +#define AT91C_AES_SMOD ( 0x3 << 8 ) /* (AES) Start Mode */ +#define AT91C_AES_SMOD_MANUAL ( 0x0 << 8 ) /* (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. */ +#define AT91C_AES_SMOD_AUTO ( 0x1 << 8 ) /* (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). */ +#define AT91C_AES_SMOD_PDC ( 0x2 << 8 ) /* (AES) PDC Mode (cf datasheet). */ +#define AT91C_AES_OPMOD ( 0x7 << 12 ) /* (AES) Operation Mode */ +#define AT91C_AES_OPMOD_ECB ( 0x0 << 12 ) /* (AES) ECB Electronic CodeBook mode. */ +#define AT91C_AES_OPMOD_CBC ( 0x1 << 12 ) /* (AES) CBC Cipher Block Chaining mode. */ +#define AT91C_AES_OPMOD_OFB ( 0x2 << 12 ) /* (AES) OFB Output Feedback mode. */ +#define AT91C_AES_OPMOD_CFB ( 0x3 << 12 ) /* (AES) CFB Cipher Feedback mode. */ +#define AT91C_AES_OPMOD_CTR ( 0x4 << 12 ) /* (AES) CTR Counter mode. */ +#define AT91C_AES_LOD ( 0x1 << 15 ) /* (AES) Last Output Data Mode */ +#define AT91C_AES_CFBS ( 0x7 << 16 ) /* (AES) Cipher Feedback Data Size */ +#define AT91C_AES_CFBS_128_BIT ( 0x0 << 16 ) /* (AES) 128-bit. */ +#define AT91C_AES_CFBS_64_BIT ( 0x1 << 16 ) /* (AES) 64-bit. */ +#define AT91C_AES_CFBS_32_BIT ( 0x2 << 16 ) /* (AES) 32-bit. */ +#define AT91C_AES_CFBS_16_BIT ( 0x3 << 16 ) /* (AES) 16-bit. */ +#define AT91C_AES_CFBS_8_BIT ( 0x4 << 16 ) /* (AES) 8-bit. */ +#define AT91C_AES_CKEY ( 0xF << 20 ) /* (AES) Countermeasure Key */ +#define AT91C_AES_CTYPE ( 0x1F << 24 ) /* (AES) Countermeasure Type */ +#define AT91C_AES_CTYPE_TYPE1_EN ( 0x1 << 24 ) /* (AES) Countermeasure type 1 is enabled. */ +#define AT91C_AES_CTYPE_TYPE2_EN ( 0x2 << 24 ) /* (AES) Countermeasure type 2 is enabled. */ +#define AT91C_AES_CTYPE_TYPE3_EN ( 0x4 << 24 ) /* (AES) Countermeasure type 3 is enabled. */ +#define AT91C_AES_CTYPE_TYPE4_EN ( 0x8 << 24 ) /* (AES) Countermeasure type 4 is enabled. */ +#define AT91C_AES_CTYPE_TYPE5_EN ( 0x10 << 24 ) /* (AES) Countermeasure type 5 is enabled. */ +/* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */ +#define AT91C_AES_DATRDY ( 0x1 << 0 ) /* (AES) DATRDY */ +#define AT91C_AES_ENDRX ( 0x1 << 1 ) /* (AES) PDC Read Buffer End */ +#define AT91C_AES_ENDTX ( 0x1 << 2 ) /* (AES) PDC Write Buffer End */ +#define AT91C_AES_RXBUFF ( 0x1 << 3 ) /* (AES) PDC Read Buffer Full */ +#define AT91C_AES_TXBUFE ( 0x1 << 4 ) /* (AES) PDC Write Buffer Empty */ +#define AT91C_AES_URAD ( 0x1 << 8 ) /* (AES) Unspecified Register Access Detection */ +/* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */ +/* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */ +/* -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- */ +#define AT91C_AES_URAT ( 0x7 << 12 ) /* (AES) Unspecified Register Access Type Status */ +#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ( 0x0 << 12 ) /* (AES) Input data register written during the data processing in PDC mode. */ +#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ( 0x1 << 12 ) /* (AES) Output data register read during the data processing. */ +#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ( 0x2 << 12 ) /* (AES) Mode register written during the data processing. */ +#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ( 0x3 << 12 ) /* (AES) Output data register read during the sub-keys generation. */ +#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ( 0x4 << 12 ) /* (AES) Mode register written during the sub-keys generation. */ +#define AT91C_AES_URAT_WO_REG_READ ( 0x5 << 12 ) /* (AES) Write-only register read access. */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Triple Data Encryption Standard */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_TDES structure *** */ +#define TDES_CR ( 0 ) /* Control Register */ +#define TDES_MR ( 4 ) /* Mode Register */ +#define TDES_IER ( 16 ) /* Interrupt Enable Register */ +#define TDES_IDR ( 20 ) /* Interrupt Disable Register */ +#define TDES_IMR ( 24 ) /* Interrupt Mask Register */ +#define TDES_ISR ( 28 ) /* Interrupt Status Register */ +#define TDES_KEY1WxR ( 32 ) /* Key 1 Word x Register */ +#define TDES_KEY2WxR ( 40 ) /* Key 2 Word x Register */ +#define TDES_KEY3WxR ( 48 ) /* Key 3 Word x Register */ +#define TDES_IDATAxR ( 64 ) /* Input Data x Register */ +#define TDES_ODATAxR ( 80 ) /* Output Data x Register */ +#define TDES_IVxR ( 96 ) /* Initialization Vector x Register */ +#define TDES_VR ( 252 ) /* TDES Version Register */ +#define TDES_RPR ( 256 ) /* Receive Pointer Register */ +#define TDES_RCR ( 260 ) /* Receive Counter Register */ +#define TDES_TPR ( 264 ) /* Transmit Pointer Register */ +#define TDES_TCR ( 268 ) /* Transmit Counter Register */ +#define TDES_RNPR ( 272 ) /* Receive Next Pointer Register */ +#define TDES_RNCR ( 276 ) /* Receive Next Counter Register */ +#define TDES_TNPR ( 280 ) /* Transmit Next Pointer Register */ +#define TDES_TNCR ( 284 ) /* Transmit Next Counter Register */ +#define TDES_PTCR ( 288 ) /* PDC Transfer Control Register */ +#define TDES_PTSR ( 292 ) /* PDC Transfer Status Register */ +/* -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- */ +#define AT91C_TDES_START ( 0x1 << 0 ) /* (TDES) Starts Processing */ +#define AT91C_TDES_SWRST ( 0x1 << 8 ) /* (TDES) Software Reset */ +/* -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- */ +#define AT91C_TDES_CIPHER ( 0x1 << 0 ) /* (TDES) Processing Mode */ +#define AT91C_TDES_TDESMOD ( 0x1 << 1 ) /* (TDES) Single or Triple DES Mode */ +#define AT91C_TDES_KEYMOD ( 0x1 << 4 ) /* (TDES) Key Mode */ +#define AT91C_TDES_SMOD ( 0x3 << 8 ) /* (TDES) Start Mode */ +#define AT91C_TDES_SMOD_MANUAL ( 0x0 << 8 ) /* (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. */ +#define AT91C_TDES_SMOD_AUTO ( 0x1 << 8 ) /* (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). */ +#define AT91C_TDES_SMOD_PDC ( 0x2 << 8 ) /* (TDES) PDC Mode (cf datasheet). */ +#define AT91C_TDES_OPMOD ( 0x3 << 12 ) /* (TDES) Operation Mode */ +#define AT91C_TDES_OPMOD_ECB ( 0x0 << 12 ) /* (TDES) ECB Electronic CodeBook mode. */ +#define AT91C_TDES_OPMOD_CBC ( 0x1 << 12 ) /* (TDES) CBC Cipher Block Chaining mode. */ +#define AT91C_TDES_OPMOD_OFB ( 0x2 << 12 ) /* (TDES) OFB Output Feedback mode. */ +#define AT91C_TDES_OPMOD_CFB ( 0x3 << 12 ) /* (TDES) CFB Cipher Feedback mode. */ +#define AT91C_TDES_LOD ( 0x1 << 15 ) /* (TDES) Last Output Data Mode */ +#define AT91C_TDES_CFBS ( 0x3 << 16 ) /* (TDES) Cipher Feedback Data Size */ +#define AT91C_TDES_CFBS_64_BIT ( 0x0 << 16 ) /* (TDES) 64-bit. */ +#define AT91C_TDES_CFBS_32_BIT ( 0x1 << 16 ) /* (TDES) 32-bit. */ +#define AT91C_TDES_CFBS_16_BIT ( 0x2 << 16 ) /* (TDES) 16-bit. */ +#define AT91C_TDES_CFBS_8_BIT ( 0x3 << 16 ) /* (TDES) 8-bit. */ +/* -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- */ +#define AT91C_TDES_DATRDY ( 0x1 << 0 ) /* (TDES) DATRDY */ +#define AT91C_TDES_ENDRX ( 0x1 << 1 ) /* (TDES) PDC Read Buffer End */ +#define AT91C_TDES_ENDTX ( 0x1 << 2 ) /* (TDES) PDC Write Buffer End */ +#define AT91C_TDES_RXBUFF ( 0x1 << 3 ) /* (TDES) PDC Read Buffer Full */ +#define AT91C_TDES_TXBUFE ( 0x1 << 4 ) /* (TDES) PDC Write Buffer Empty */ +#define AT91C_TDES_URAD ( 0x1 << 8 ) /* (TDES) Unspecified Register Access Detection */ +/* -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- */ +/* -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- */ +/* -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- */ +#define AT91C_TDES_URAT ( 0x3 << 12 ) /* (TDES) Unspecified Register Access Type Status */ +#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ( 0x0 << 12 ) /* (TDES) Input data register written during the data processing in PDC mode. */ +#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ( 0x1 << 12 ) /* (TDES) Output data register read during the data processing. */ +#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ( 0x2 << 12 ) /* (TDES) Mode register written during the data processing. */ +#define AT91C_TDES_URAT_WO_REG_READ ( 0x3 << 12 ) /* (TDES) Write-only register read access. */ + +/* ***************************************************************************** */ +/* REGISTER ADDRESS DEFINITION FOR AT91SAM7X128 */ +/* ***************************************************************************** */ +/* ========== Register definition for SYS peripheral ========== */ +/* ========== Register definition for AIC peripheral ========== */ +#define AT91C_AIC_IVR ( 0xFFFFF100 ) /* (AIC) IRQ Vector Register */ +#define AT91C_AIC_SMR ( 0xFFFFF000 ) /* (AIC) Source Mode Register */ +#define AT91C_AIC_FVR ( 0xFFFFF104 ) /* (AIC) FIQ Vector Register */ +#define AT91C_AIC_DCR ( 0xFFFFF138 ) /* (AIC) Debug Control Register (Protect) */ +#define AT91C_AIC_EOICR ( 0xFFFFF130 ) /* (AIC) End of Interrupt Command Register */ +#define AT91C_AIC_SVR ( 0xFFFFF080 ) /* (AIC) Source Vector Register */ +#define AT91C_AIC_FFSR ( 0xFFFFF148 ) /* (AIC) Fast Forcing Status Register */ +#define AT91C_AIC_ICCR ( 0xFFFFF128 ) /* (AIC) Interrupt Clear Command Register */ +#define AT91C_AIC_ISR ( 0xFFFFF108 ) /* (AIC) Interrupt Status Register */ +#define AT91C_AIC_IMR ( 0xFFFFF110 ) /* (AIC) Interrupt Mask Register */ +#define AT91C_AIC_IPR ( 0xFFFFF10C ) /* (AIC) Interrupt Pending Register */ +#define AT91C_AIC_FFER ( 0xFFFFF140 ) /* (AIC) Fast Forcing Enable Register */ +#define AT91C_AIC_IECR ( 0xFFFFF120 ) /* (AIC) Interrupt Enable Command Register */ +#define AT91C_AIC_ISCR ( 0xFFFFF12C ) /* (AIC) Interrupt Set Command Register */ +#define AT91C_AIC_FFDR ( 0xFFFFF144 ) /* (AIC) Fast Forcing Disable Register */ +#define AT91C_AIC_CISR ( 0xFFFFF114 ) /* (AIC) Core Interrupt Status Register */ +#define AT91C_AIC_IDCR ( 0xFFFFF124 ) /* (AIC) Interrupt Disable Command Register */ +#define AT91C_AIC_SPU ( 0xFFFFF134 ) /* (AIC) Spurious Vector Register */ +/* ========== Register definition for PDC_DBGU peripheral ========== */ +#define AT91C_DBGU_TCR ( 0xFFFFF30C ) /* (PDC_DBGU) Transmit Counter Register */ +#define AT91C_DBGU_RNPR ( 0xFFFFF310 ) /* (PDC_DBGU) Receive Next Pointer Register */ +#define AT91C_DBGU_TNPR ( 0xFFFFF318 ) /* (PDC_DBGU) Transmit Next Pointer Register */ +#define AT91C_DBGU_TPR ( 0xFFFFF308 ) /* (PDC_DBGU) Transmit Pointer Register */ +#define AT91C_DBGU_RPR ( 0xFFFFF300 ) /* (PDC_DBGU) Receive Pointer Register */ +#define AT91C_DBGU_RCR ( 0xFFFFF304 ) /* (PDC_DBGU) Receive Counter Register */ +#define AT91C_DBGU_RNCR ( 0xFFFFF314 ) /* (PDC_DBGU) Receive Next Counter Register */ +#define AT91C_DBGU_PTCR ( 0xFFFFF320 ) /* (PDC_DBGU) PDC Transfer Control Register */ +#define AT91C_DBGU_PTSR ( 0xFFFFF324 ) /* (PDC_DBGU) PDC Transfer Status Register */ +#define AT91C_DBGU_TNCR ( 0xFFFFF31C ) /* (PDC_DBGU) Transmit Next Counter Register */ +/* ========== Register definition for DBGU peripheral ========== */ +#define AT91C_DBGU_EXID ( 0xFFFFF244 ) /* (DBGU) Chip ID Extension Register */ +#define AT91C_DBGU_BRGR ( 0xFFFFF220 ) /* (DBGU) Baud Rate Generator Register */ +#define AT91C_DBGU_IDR ( 0xFFFFF20C ) /* (DBGU) Interrupt Disable Register */ +#define AT91C_DBGU_CSR ( 0xFFFFF214 ) /* (DBGU) Channel Status Register */ +#define AT91C_DBGU_CIDR ( 0xFFFFF240 ) /* (DBGU) Chip ID Register */ +#define AT91C_DBGU_MR ( 0xFFFFF204 ) /* (DBGU) Mode Register */ +#define AT91C_DBGU_IMR ( 0xFFFFF210 ) /* (DBGU) Interrupt Mask Register */ +#define AT91C_DBGU_CR ( 0xFFFFF200 ) /* (DBGU) Control Register */ +#define AT91C_DBGU_FNTR ( 0xFFFFF248 ) /* (DBGU) Force NTRST Register */ +#define AT91C_DBGU_THR ( 0xFFFFF21C ) /* (DBGU) Transmitter Holding Register */ +#define AT91C_DBGU_RHR ( 0xFFFFF218 ) /* (DBGU) Receiver Holding Register */ +#define AT91C_DBGU_IER ( 0xFFFFF208 ) /* (DBGU) Interrupt Enable Register */ +/* ========== Register definition for PIOA peripheral ========== */ +#define AT91C_PIOA_ODR ( 0xFFFFF414 ) /* (PIOA) Output Disable Registerr */ +#define AT91C_PIOA_SODR ( 0xFFFFF430 ) /* (PIOA) Set Output Data Register */ +#define AT91C_PIOA_ISR ( 0xFFFFF44C ) /* (PIOA) Interrupt Status Register */ +#define AT91C_PIOA_ABSR ( 0xFFFFF478 ) /* (PIOA) AB Select Status Register */ +#define AT91C_PIOA_IER ( 0xFFFFF440 ) /* (PIOA) Interrupt Enable Register */ +#define AT91C_PIOA_PPUDR ( 0xFFFFF460 ) /* (PIOA) Pull-up Disable Register */ +#define AT91C_PIOA_IMR ( 0xFFFFF448 ) /* (PIOA) Interrupt Mask Register */ +#define AT91C_PIOA_PER ( 0xFFFFF400 ) /* (PIOA) PIO Enable Register */ +#define AT91C_PIOA_IFDR ( 0xFFFFF424 ) /* (PIOA) Input Filter Disable Register */ +#define AT91C_PIOA_OWDR ( 0xFFFFF4A4 ) /* (PIOA) Output Write Disable Register */ +#define AT91C_PIOA_MDSR ( 0xFFFFF458 ) /* (PIOA) Multi-driver Status Register */ +#define AT91C_PIOA_IDR ( 0xFFFFF444 ) /* (PIOA) Interrupt Disable Register */ +#define AT91C_PIOA_ODSR ( 0xFFFFF438 ) /* (PIOA) Output Data Status Register */ +#define AT91C_PIOA_PPUSR ( 0xFFFFF468 ) /* (PIOA) Pull-up Status Register */ +#define AT91C_PIOA_OWSR ( 0xFFFFF4A8 ) /* (PIOA) Output Write Status Register */ +#define AT91C_PIOA_BSR ( 0xFFFFF474 ) /* (PIOA) Select B Register */ +#define AT91C_PIOA_OWER ( 0xFFFFF4A0 ) /* (PIOA) Output Write Enable Register */ +#define AT91C_PIOA_IFER ( 0xFFFFF420 ) /* (PIOA) Input Filter Enable Register */ +#define AT91C_PIOA_PDSR ( 0xFFFFF43C ) /* (PIOA) Pin Data Status Register */ +#define AT91C_PIOA_PPUER ( 0xFFFFF464 ) /* (PIOA) Pull-up Enable Register */ +#define AT91C_PIOA_OSR ( 0xFFFFF418 ) /* (PIOA) Output Status Register */ +#define AT91C_PIOA_ASR ( 0xFFFFF470 ) /* (PIOA) Select A Register */ +#define AT91C_PIOA_MDDR ( 0xFFFFF454 ) /* (PIOA) Multi-driver Disable Register */ +#define AT91C_PIOA_CODR ( 0xFFFFF434 ) /* (PIOA) Clear Output Data Register */ +#define AT91C_PIOA_MDER ( 0xFFFFF450 ) /* (PIOA) Multi-driver Enable Register */ +#define AT91C_PIOA_PDR ( 0xFFFFF404 ) /* (PIOA) PIO Disable Register */ +#define AT91C_PIOA_IFSR ( 0xFFFFF428 ) /* (PIOA) Input Filter Status Register */ +#define AT91C_PIOA_OER ( 0xFFFFF410 ) /* (PIOA) Output Enable Register */ +#define AT91C_PIOA_PSR ( 0xFFFFF408 ) /* (PIOA) PIO Status Register */ +/* ========== Register definition for PIOB peripheral ========== */ +#define AT91C_PIOB_OWDR ( 0xFFFFF6A4 ) /* (PIOB) Output Write Disable Register */ +#define AT91C_PIOB_MDER ( 0xFFFFF650 ) /* (PIOB) Multi-driver Enable Register */ +#define AT91C_PIOB_PPUSR ( 0xFFFFF668 ) /* (PIOB) Pull-up Status Register */ +#define AT91C_PIOB_IMR ( 0xFFFFF648 ) /* (PIOB) Interrupt Mask Register */ +#define AT91C_PIOB_ASR ( 0xFFFFF670 ) /* (PIOB) Select A Register */ +#define AT91C_PIOB_PPUDR ( 0xFFFFF660 ) /* (PIOB) Pull-up Disable Register */ +#define AT91C_PIOB_PSR ( 0xFFFFF608 ) /* (PIOB) PIO Status Register */ +#define AT91C_PIOB_IER ( 0xFFFFF640 ) /* (PIOB) Interrupt Enable Register */ +#define AT91C_PIOB_CODR ( 0xFFFFF634 ) /* (PIOB) Clear Output Data Register */ +#define AT91C_PIOB_OWER ( 0xFFFFF6A0 ) /* (PIOB) Output Write Enable Register */ +#define AT91C_PIOB_ABSR ( 0xFFFFF678 ) /* (PIOB) AB Select Status Register */ +#define AT91C_PIOB_IFDR ( 0xFFFFF624 ) /* (PIOB) Input Filter Disable Register */ +#define AT91C_PIOB_PDSR ( 0xFFFFF63C ) /* (PIOB) Pin Data Status Register */ +#define AT91C_PIOB_IDR ( 0xFFFFF644 ) /* (PIOB) Interrupt Disable Register */ +#define AT91C_PIOB_OWSR ( 0xFFFFF6A8 ) /* (PIOB) Output Write Status Register */ +#define AT91C_PIOB_PDR ( 0xFFFFF604 ) /* (PIOB) PIO Disable Register */ +#define AT91C_PIOB_ODR ( 0xFFFFF614 ) /* (PIOB) Output Disable Registerr */ +#define AT91C_PIOB_IFSR ( 0xFFFFF628 ) /* (PIOB) Input Filter Status Register */ +#define AT91C_PIOB_PPUER ( 0xFFFFF664 ) /* (PIOB) Pull-up Enable Register */ +#define AT91C_PIOB_SODR ( 0xFFFFF630 ) /* (PIOB) Set Output Data Register */ +#define AT91C_PIOB_ISR ( 0xFFFFF64C ) /* (PIOB) Interrupt Status Register */ +#define AT91C_PIOB_ODSR ( 0xFFFFF638 ) /* (PIOB) Output Data Status Register */ +#define AT91C_PIOB_OSR ( 0xFFFFF618 ) /* (PIOB) Output Status Register */ +#define AT91C_PIOB_MDSR ( 0xFFFFF658 ) /* (PIOB) Multi-driver Status Register */ +#define AT91C_PIOB_IFER ( 0xFFFFF620 ) /* (PIOB) Input Filter Enable Register */ +#define AT91C_PIOB_BSR ( 0xFFFFF674 ) /* (PIOB) Select B Register */ +#define AT91C_PIOB_MDDR ( 0xFFFFF654 ) /* (PIOB) Multi-driver Disable Register */ +#define AT91C_PIOB_OER ( 0xFFFFF610 ) /* (PIOB) Output Enable Register */ +#define AT91C_PIOB_PER ( 0xFFFFF600 ) /* (PIOB) PIO Enable Register */ +/* ========== Register definition for CKGR peripheral ========== */ +#define AT91C_CKGR_MOR ( 0xFFFFFC20 ) /* (CKGR) Main Oscillator Register */ +#define AT91C_CKGR_PLLR ( 0xFFFFFC2C ) /* (CKGR) PLL Register */ +#define AT91C_CKGR_MCFR ( 0xFFFFFC24 ) /* (CKGR) Main Clock Frequency Register */ +/* ========== Register definition for PMC peripheral ========== */ +#define AT91C_PMC_IDR ( 0xFFFFFC64 ) /* (PMC) Interrupt Disable Register */ +#define AT91C_PMC_MOR ( 0xFFFFFC20 ) /* (PMC) Main Oscillator Register */ +#define AT91C_PMC_PLLR ( 0xFFFFFC2C ) /* (PMC) PLL Register */ +#define AT91C_PMC_PCER ( 0xFFFFFC10 ) /* (PMC) Peripheral Clock Enable Register */ +#define AT91C_PMC_PCKR ( 0xFFFFFC40 ) /* (PMC) Programmable Clock Register */ +#define AT91C_PMC_MCKR ( 0xFFFFFC30 ) /* (PMC) Master Clock Register */ +#define AT91C_PMC_SCDR ( 0xFFFFFC04 ) /* (PMC) System Clock Disable Register */ +#define AT91C_PMC_PCDR ( 0xFFFFFC14 ) /* (PMC) Peripheral Clock Disable Register */ +#define AT91C_PMC_SCSR ( 0xFFFFFC08 ) /* (PMC) System Clock Status Register */ +#define AT91C_PMC_PCSR ( 0xFFFFFC18 ) /* (PMC) Peripheral Clock Status Register */ +#define AT91C_PMC_MCFR ( 0xFFFFFC24 ) /* (PMC) Main Clock Frequency Register */ +#define AT91C_PMC_SCER ( 0xFFFFFC00 ) /* (PMC) System Clock Enable Register */ +#define AT91C_PMC_IMR ( 0xFFFFFC6C ) /* (PMC) Interrupt Mask Register */ +#define AT91C_PMC_IER ( 0xFFFFFC60 ) /* (PMC) Interrupt Enable Register */ +#define AT91C_PMC_SR ( 0xFFFFFC68 ) /* (PMC) Status Register */ +/* ========== Register definition for RSTC peripheral ========== */ +#define AT91C_RSTC_RCR ( 0xFFFFFD00 ) /* (RSTC) Reset Control Register */ +#define AT91C_RSTC_RMR ( 0xFFFFFD08 ) /* (RSTC) Reset Mode Register */ +#define AT91C_RSTC_RSR ( 0xFFFFFD04 ) /* (RSTC) Reset Status Register */ +/* ========== Register definition for RTTC peripheral ========== */ +#define AT91C_RTTC_RTSR ( 0xFFFFFD2C ) /* (RTTC) Real-time Status Register */ +#define AT91C_RTTC_RTMR ( 0xFFFFFD20 ) /* (RTTC) Real-time Mode Register */ +#define AT91C_RTTC_RTVR ( 0xFFFFFD28 ) /* (RTTC) Real-time Value Register */ +#define AT91C_RTTC_RTAR ( 0xFFFFFD24 ) /* (RTTC) Real-time Alarm Register */ +/* ========== Register definition for PITC peripheral ========== */ +#define AT91C_PITC_PIVR ( 0xFFFFFD38 ) /* (PITC) Period Interval Value Register */ +#define AT91C_PITC_PISR ( 0xFFFFFD34 ) /* (PITC) Period Interval Status Register */ +#define AT91C_PITC_PIIR ( 0xFFFFFD3C ) /* (PITC) Period Interval Image Register */ +#define AT91C_PITC_PIMR ( 0xFFFFFD30 ) /* (PITC) Period Interval Mode Register */ +/* ========== Register definition for WDTC peripheral ========== */ +#define AT91C_WDTC_WDCR ( 0xFFFFFD40 ) /* (WDTC) Watchdog Control Register */ +#define AT91C_WDTC_WDSR ( 0xFFFFFD48 ) /* (WDTC) Watchdog Status Register */ +#define AT91C_WDTC_WDMR ( 0xFFFFFD44 ) /* (WDTC) Watchdog Mode Register */ +/* ========== Register definition for VREG peripheral ========== */ +#define AT91C_VREG_MR ( 0xFFFFFD60 ) /* (VREG) Voltage Regulator Mode Register */ +/* ========== Register definition for MC peripheral ========== */ +#define AT91C_MC_ASR ( 0xFFFFFF04 ) /* (MC) MC Abort Status Register */ +#define AT91C_MC_RCR ( 0xFFFFFF00 ) /* (MC) MC Remap Control Register */ +#define AT91C_MC_FCR ( 0xFFFFFF64 ) /* (MC) MC Flash Command Register */ +#define AT91C_MC_AASR ( 0xFFFFFF08 ) /* (MC) MC Abort Address Status Register */ +#define AT91C_MC_FSR ( 0xFFFFFF68 ) /* (MC) MC Flash Status Register */ +#define AT91C_MC_FMR ( 0xFFFFFF60 ) /* (MC) MC Flash Mode Register */ +/* ========== Register definition for PDC_SPI1 peripheral ========== */ +#define AT91C_SPI1_PTCR ( 0xFFFE4120 ) /* (PDC_SPI1) PDC Transfer Control Register */ +#define AT91C_SPI1_RPR ( 0xFFFE4100 ) /* (PDC_SPI1) Receive Pointer Register */ +#define AT91C_SPI1_TNCR ( 0xFFFE411C ) /* (PDC_SPI1) Transmit Next Counter Register */ +#define AT91C_SPI1_TPR ( 0xFFFE4108 ) /* (PDC_SPI1) Transmit Pointer Register */ +#define AT91C_SPI1_TNPR ( 0xFFFE4118 ) /* (PDC_SPI1) Transmit Next Pointer Register */ +#define AT91C_SPI1_TCR ( 0xFFFE410C ) /* (PDC_SPI1) Transmit Counter Register */ +#define AT91C_SPI1_RCR ( 0xFFFE4104 ) /* (PDC_SPI1) Receive Counter Register */ +#define AT91C_SPI1_RNPR ( 0xFFFE4110 ) /* (PDC_SPI1) Receive Next Pointer Register */ +#define AT91C_SPI1_RNCR ( 0xFFFE4114 ) /* (PDC_SPI1) Receive Next Counter Register */ +#define AT91C_SPI1_PTSR ( 0xFFFE4124 ) /* (PDC_SPI1) PDC Transfer Status Register */ +/* ========== Register definition for SPI1 peripheral ========== */ +#define AT91C_SPI1_IMR ( 0xFFFE401C ) /* (SPI1) Interrupt Mask Register */ +#define AT91C_SPI1_IER ( 0xFFFE4014 ) /* (SPI1) Interrupt Enable Register */ +#define AT91C_SPI1_MR ( 0xFFFE4004 ) /* (SPI1) Mode Register */ +#define AT91C_SPI1_RDR ( 0xFFFE4008 ) /* (SPI1) Receive Data Register */ +#define AT91C_SPI1_IDR ( 0xFFFE4018 ) /* (SPI1) Interrupt Disable Register */ +#define AT91C_SPI1_SR ( 0xFFFE4010 ) /* (SPI1) Status Register */ +#define AT91C_SPI1_TDR ( 0xFFFE400C ) /* (SPI1) Transmit Data Register */ +#define AT91C_SPI1_CR ( 0xFFFE4000 ) /* (SPI1) Control Register */ +#define AT91C_SPI1_CSR ( 0xFFFE4030 ) /* (SPI1) Chip Select Register */ +/* ========== Register definition for PDC_SPI0 peripheral ========== */ +#define AT91C_SPI0_PTCR ( 0xFFFE0120 ) /* (PDC_SPI0) PDC Transfer Control Register */ +#define AT91C_SPI0_TPR ( 0xFFFE0108 ) /* (PDC_SPI0) Transmit Pointer Register */ +#define AT91C_SPI0_TCR ( 0xFFFE010C ) /* (PDC_SPI0) Transmit Counter Register */ +#define AT91C_SPI0_RCR ( 0xFFFE0104 ) /* (PDC_SPI0) Receive Counter Register */ +#define AT91C_SPI0_PTSR ( 0xFFFE0124 ) /* (PDC_SPI0) PDC Transfer Status Register */ +#define AT91C_SPI0_RNPR ( 0xFFFE0110 ) /* (PDC_SPI0) Receive Next Pointer Register */ +#define AT91C_SPI0_RPR ( 0xFFFE0100 ) /* (PDC_SPI0) Receive Pointer Register */ +#define AT91C_SPI0_TNCR ( 0xFFFE011C ) /* (PDC_SPI0) Transmit Next Counter Register */ +#define AT91C_SPI0_RNCR ( 0xFFFE0114 ) /* (PDC_SPI0) Receive Next Counter Register */ +#define AT91C_SPI0_TNPR ( 0xFFFE0118 ) /* (PDC_SPI0) Transmit Next Pointer Register */ +/* ========== Register definition for SPI0 peripheral ========== */ +#define AT91C_SPI0_IER ( 0xFFFE0014 ) /* (SPI0) Interrupt Enable Register */ +#define AT91C_SPI0_SR ( 0xFFFE0010 ) /* (SPI0) Status Register */ +#define AT91C_SPI0_IDR ( 0xFFFE0018 ) /* (SPI0) Interrupt Disable Register */ +#define AT91C_SPI0_CR ( 0xFFFE0000 ) /* (SPI0) Control Register */ +#define AT91C_SPI0_MR ( 0xFFFE0004 ) /* (SPI0) Mode Register */ +#define AT91C_SPI0_IMR ( 0xFFFE001C ) /* (SPI0) Interrupt Mask Register */ +#define AT91C_SPI0_TDR ( 0xFFFE000C ) /* (SPI0) Transmit Data Register */ +#define AT91C_SPI0_RDR ( 0xFFFE0008 ) /* (SPI0) Receive Data Register */ +#define AT91C_SPI0_CSR ( 0xFFFE0030 ) /* (SPI0) Chip Select Register */ +/* ========== Register definition for PDC_US1 peripheral ========== */ +#define AT91C_US1_RNCR ( 0xFFFC4114 ) /* (PDC_US1) Receive Next Counter Register */ +#define AT91C_US1_PTCR ( 0xFFFC4120 ) /* (PDC_US1) PDC Transfer Control Register */ +#define AT91C_US1_TCR ( 0xFFFC410C ) /* (PDC_US1) Transmit Counter Register */ +#define AT91C_US1_PTSR ( 0xFFFC4124 ) /* (PDC_US1) PDC Transfer Status Register */ +#define AT91C_US1_TNPR ( 0xFFFC4118 ) /* (PDC_US1) Transmit Next Pointer Register */ +#define AT91C_US1_RCR ( 0xFFFC4104 ) /* (PDC_US1) Receive Counter Register */ +#define AT91C_US1_RNPR ( 0xFFFC4110 ) /* (PDC_US1) Receive Next Pointer Register */ +#define AT91C_US1_RPR ( 0xFFFC4100 ) /* (PDC_US1) Receive Pointer Register */ +#define AT91C_US1_TNCR ( 0xFFFC411C ) /* (PDC_US1) Transmit Next Counter Register */ +#define AT91C_US1_TPR ( 0xFFFC4108 ) /* (PDC_US1) Transmit Pointer Register */ +/* ========== Register definition for US1 peripheral ========== */ +#define AT91C_US1_IF ( 0xFFFC404C ) /* (US1) IRDA_FILTER Register */ +#define AT91C_US1_NER ( 0xFFFC4044 ) /* (US1) Nb Errors Register */ +#define AT91C_US1_RTOR ( 0xFFFC4024 ) /* (US1) Receiver Time-out Register */ +#define AT91C_US1_CSR ( 0xFFFC4014 ) /* (US1) Channel Status Register */ +#define AT91C_US1_IDR ( 0xFFFC400C ) /* (US1) Interrupt Disable Register */ +#define AT91C_US1_IER ( 0xFFFC4008 ) /* (US1) Interrupt Enable Register */ +#define AT91C_US1_THR ( 0xFFFC401C ) /* (US1) Transmitter Holding Register */ +#define AT91C_US1_TTGR ( 0xFFFC4028 ) /* (US1) Transmitter Time-guard Register */ +#define AT91C_US1_RHR ( 0xFFFC4018 ) /* (US1) Receiver Holding Register */ +#define AT91C_US1_BRGR ( 0xFFFC4020 ) /* (US1) Baud Rate Generator Register */ +#define AT91C_US1_IMR ( 0xFFFC4010 ) /* (US1) Interrupt Mask Register */ +#define AT91C_US1_FIDI ( 0xFFFC4040 ) /* (US1) FI_DI_Ratio Register */ +#define AT91C_US1_CR ( 0xFFFC4000 ) /* (US1) Control Register */ +#define AT91C_US1_MR ( 0xFFFC4004 ) /* (US1) Mode Register */ +/* ========== Register definition for PDC_US0 peripheral ========== */ +#define AT91C_US0_TNPR ( 0xFFFC0118 ) /* (PDC_US0) Transmit Next Pointer Register */ +#define AT91C_US0_RNPR ( 0xFFFC0110 ) /* (PDC_US0) Receive Next Pointer Register */ +#define AT91C_US0_TCR ( 0xFFFC010C ) /* (PDC_US0) Transmit Counter Register */ +#define AT91C_US0_PTCR ( 0xFFFC0120 ) /* (PDC_US0) PDC Transfer Control Register */ +#define AT91C_US0_PTSR ( 0xFFFC0124 ) /* (PDC_US0) PDC Transfer Status Register */ +#define AT91C_US0_TNCR ( 0xFFFC011C ) /* (PDC_US0) Transmit Next Counter Register */ +#define AT91C_US0_TPR ( 0xFFFC0108 ) /* (PDC_US0) Transmit Pointer Register */ +#define AT91C_US0_RCR ( 0xFFFC0104 ) /* (PDC_US0) Receive Counter Register */ +#define AT91C_US0_RPR ( 0xFFFC0100 ) /* (PDC_US0) Receive Pointer Register */ +#define AT91C_US0_RNCR ( 0xFFFC0114 ) /* (PDC_US0) Receive Next Counter Register */ +/* ========== Register definition for US0 peripheral ========== */ +#define AT91C_US0_BRGR ( 0xFFFC0020 ) /* (US0) Baud Rate Generator Register */ +#define AT91C_US0_NER ( 0xFFFC0044 ) /* (US0) Nb Errors Register */ +#define AT91C_US0_CR ( 0xFFFC0000 ) /* (US0) Control Register */ +#define AT91C_US0_IMR ( 0xFFFC0010 ) /* (US0) Interrupt Mask Register */ +#define AT91C_US0_FIDI ( 0xFFFC0040 ) /* (US0) FI_DI_Ratio Register */ +#define AT91C_US0_TTGR ( 0xFFFC0028 ) /* (US0) Transmitter Time-guard Register */ +#define AT91C_US0_MR ( 0xFFFC0004 ) /* (US0) Mode Register */ +#define AT91C_US0_RTOR ( 0xFFFC0024 ) /* (US0) Receiver Time-out Register */ +#define AT91C_US0_CSR ( 0xFFFC0014 ) /* (US0) Channel Status Register */ +#define AT91C_US0_RHR ( 0xFFFC0018 ) /* (US0) Receiver Holding Register */ +#define AT91C_US0_IDR ( 0xFFFC000C ) /* (US0) Interrupt Disable Register */ +#define AT91C_US0_THR ( 0xFFFC001C ) /* (US0) Transmitter Holding Register */ +#define AT91C_US0_IF ( 0xFFFC004C ) /* (US0) IRDA_FILTER Register */ +#define AT91C_US0_IER ( 0xFFFC0008 ) /* (US0) Interrupt Enable Register */ +/* ========== Register definition for PDC_SSC peripheral ========== */ +#define AT91C_SSC_TNCR ( 0xFFFD411C ) /* (PDC_SSC) Transmit Next Counter Register */ +#define AT91C_SSC_RPR ( 0xFFFD4100 ) /* (PDC_SSC) Receive Pointer Register */ +#define AT91C_SSC_RNCR ( 0xFFFD4114 ) /* (PDC_SSC) Receive Next Counter Register */ +#define AT91C_SSC_TPR ( 0xFFFD4108 ) /* (PDC_SSC) Transmit Pointer Register */ +#define AT91C_SSC_PTCR ( 0xFFFD4120 ) /* (PDC_SSC) PDC Transfer Control Register */ +#define AT91C_SSC_TCR ( 0xFFFD410C ) /* (PDC_SSC) Transmit Counter Register */ +#define AT91C_SSC_RCR ( 0xFFFD4104 ) /* (PDC_SSC) Receive Counter Register */ +#define AT91C_SSC_RNPR ( 0xFFFD4110 ) /* (PDC_SSC) Receive Next Pointer Register */ +#define AT91C_SSC_TNPR ( 0xFFFD4118 ) /* (PDC_SSC) Transmit Next Pointer Register */ +#define AT91C_SSC_PTSR ( 0xFFFD4124 ) /* (PDC_SSC) PDC Transfer Status Register */ +/* ========== Register definition for SSC peripheral ========== */ +#define AT91C_SSC_RHR ( 0xFFFD4020 ) /* (SSC) Receive Holding Register */ +#define AT91C_SSC_RSHR ( 0xFFFD4030 ) /* (SSC) Receive Sync Holding Register */ +#define AT91C_SSC_TFMR ( 0xFFFD401C ) /* (SSC) Transmit Frame Mode Register */ +#define AT91C_SSC_IDR ( 0xFFFD4048 ) /* (SSC) Interrupt Disable Register */ +#define AT91C_SSC_THR ( 0xFFFD4024 ) /* (SSC) Transmit Holding Register */ +#define AT91C_SSC_RCMR ( 0xFFFD4010 ) /* (SSC) Receive Clock ModeRegister */ +#define AT91C_SSC_IER ( 0xFFFD4044 ) /* (SSC) Interrupt Enable Register */ +#define AT91C_SSC_TSHR ( 0xFFFD4034 ) /* (SSC) Transmit Sync Holding Register */ +#define AT91C_SSC_SR ( 0xFFFD4040 ) /* (SSC) Status Register */ +#define AT91C_SSC_CMR ( 0xFFFD4004 ) /* (SSC) Clock Mode Register */ +#define AT91C_SSC_TCMR ( 0xFFFD4018 ) /* (SSC) Transmit Clock Mode Register */ +#define AT91C_SSC_CR ( 0xFFFD4000 ) /* (SSC) Control Register */ +#define AT91C_SSC_IMR ( 0xFFFD404C ) /* (SSC) Interrupt Mask Register */ +#define AT91C_SSC_RFMR ( 0xFFFD4014 ) /* (SSC) Receive Frame Mode Register */ +/* ========== Register definition for TWI peripheral ========== */ +#define AT91C_TWI_IER ( 0xFFFB8024 ) /* (TWI) Interrupt Enable Register */ +#define AT91C_TWI_CR ( 0xFFFB8000 ) /* (TWI) Control Register */ +#define AT91C_TWI_SR ( 0xFFFB8020 ) /* (TWI) Status Register */ +#define AT91C_TWI_IMR ( 0xFFFB802C ) /* (TWI) Interrupt Mask Register */ +#define AT91C_TWI_THR ( 0xFFFB8034 ) /* (TWI) Transmit Holding Register */ +#define AT91C_TWI_IDR ( 0xFFFB8028 ) /* (TWI) Interrupt Disable Register */ +#define AT91C_TWI_IADR ( 0xFFFB800C ) /* (TWI) Internal Address Register */ +#define AT91C_TWI_MMR ( 0xFFFB8004 ) /* (TWI) Master Mode Register */ +#define AT91C_TWI_CWGR ( 0xFFFB8010 ) /* (TWI) Clock Waveform Generator Register */ +#define AT91C_TWI_RHR ( 0xFFFB8030 ) /* (TWI) Receive Holding Register */ +/* ========== Register definition for PWMC_CH3 peripheral ========== */ +#define AT91C_PWMC_CH3_CUPDR ( 0xFFFCC270 ) /* (PWMC_CH3) Channel Update Register */ +#define AT91C_PWMC_CH3_Reserved ( 0xFFFCC274 ) /* (PWMC_CH3) Reserved */ +#define AT91C_PWMC_CH3_CPRDR ( 0xFFFCC268 ) /* (PWMC_CH3) Channel Period Register */ +#define AT91C_PWMC_CH3_CDTYR ( 0xFFFCC264 ) /* (PWMC_CH3) Channel Duty Cycle Register */ +#define AT91C_PWMC_CH3_CCNTR ( 0xFFFCC26C ) /* (PWMC_CH3) Channel Counter Register */ +#define AT91C_PWMC_CH3_CMR ( 0xFFFCC260 ) /* (PWMC_CH3) Channel Mode Register */ +/* ========== Register definition for PWMC_CH2 peripheral ========== */ +#define AT91C_PWMC_CH2_Reserved ( 0xFFFCC254 ) /* (PWMC_CH2) Reserved */ +#define AT91C_PWMC_CH2_CMR ( 0xFFFCC240 ) /* (PWMC_CH2) Channel Mode Register */ +#define AT91C_PWMC_CH2_CCNTR ( 0xFFFCC24C ) /* (PWMC_CH2) Channel Counter Register */ +#define AT91C_PWMC_CH2_CPRDR ( 0xFFFCC248 ) /* (PWMC_CH2) Channel Period Register */ +#define AT91C_PWMC_CH2_CUPDR ( 0xFFFCC250 ) /* (PWMC_CH2) Channel Update Register */ +#define AT91C_PWMC_CH2_CDTYR ( 0xFFFCC244 ) /* (PWMC_CH2) Channel Duty Cycle Register */ +/* ========== Register definition for PWMC_CH1 peripheral ========== */ +#define AT91C_PWMC_CH1_Reserved ( 0xFFFCC234 ) /* (PWMC_CH1) Reserved */ +#define AT91C_PWMC_CH1_CUPDR ( 0xFFFCC230 ) /* (PWMC_CH1) Channel Update Register */ +#define AT91C_PWMC_CH1_CPRDR ( 0xFFFCC228 ) /* (PWMC_CH1) Channel Period Register */ +#define AT91C_PWMC_CH1_CCNTR ( 0xFFFCC22C ) /* (PWMC_CH1) Channel Counter Register */ +#define AT91C_PWMC_CH1_CDTYR ( 0xFFFCC224 ) /* (PWMC_CH1) Channel Duty Cycle Register */ +#define AT91C_PWMC_CH1_CMR ( 0xFFFCC220 ) /* (PWMC_CH1) Channel Mode Register */ +/* ========== Register definition for PWMC_CH0 peripheral ========== */ +#define AT91C_PWMC_CH0_Reserved ( 0xFFFCC214 ) /* (PWMC_CH0) Reserved */ +#define AT91C_PWMC_CH0_CPRDR ( 0xFFFCC208 ) /* (PWMC_CH0) Channel Period Register */ +#define AT91C_PWMC_CH0_CDTYR ( 0xFFFCC204 ) /* (PWMC_CH0) Channel Duty Cycle Register */ +#define AT91C_PWMC_CH0_CMR ( 0xFFFCC200 ) /* (PWMC_CH0) Channel Mode Register */ +#define AT91C_PWMC_CH0_CUPDR ( 0xFFFCC210 ) /* (PWMC_CH0) Channel Update Register */ +#define AT91C_PWMC_CH0_CCNTR ( 0xFFFCC20C ) /* (PWMC_CH0) Channel Counter Register */ +/* ========== Register definition for PWMC peripheral ========== */ +#define AT91C_PWMC_IDR ( 0xFFFCC014 ) /* (PWMC) PWMC Interrupt Disable Register */ +#define AT91C_PWMC_DIS ( 0xFFFCC008 ) /* (PWMC) PWMC Disable Register */ +#define AT91C_PWMC_IER ( 0xFFFCC010 ) /* (PWMC) PWMC Interrupt Enable Register */ +#define AT91C_PWMC_VR ( 0xFFFCC0FC ) /* (PWMC) PWMC Version Register */ +#define AT91C_PWMC_ISR ( 0xFFFCC01C ) /* (PWMC) PWMC Interrupt Status Register */ +#define AT91C_PWMC_SR ( 0xFFFCC00C ) /* (PWMC) PWMC Status Register */ +#define AT91C_PWMC_IMR ( 0xFFFCC018 ) /* (PWMC) PWMC Interrupt Mask Register */ +#define AT91C_PWMC_MR ( 0xFFFCC000 ) /* (PWMC) PWMC Mode Register */ +#define AT91C_PWMC_ENA ( 0xFFFCC004 ) /* (PWMC) PWMC Enable Register */ +/* ========== Register definition for UDP peripheral ========== */ +#define AT91C_UDP_IMR ( 0xFFFB0018 ) /* (UDP) Interrupt Mask Register */ +#define AT91C_UDP_FADDR ( 0xFFFB0008 ) /* (UDP) Function Address Register */ +#define AT91C_UDP_NUM ( 0xFFFB0000 ) /* (UDP) Frame Number Register */ +#define AT91C_UDP_FDR ( 0xFFFB0050 ) /* (UDP) Endpoint FIFO Data Register */ +#define AT91C_UDP_ISR ( 0xFFFB001C ) /* (UDP) Interrupt Status Register */ +#define AT91C_UDP_CSR ( 0xFFFB0030 ) /* (UDP) Endpoint Control and Status Register */ +#define AT91C_UDP_IDR ( 0xFFFB0014 ) /* (UDP) Interrupt Disable Register */ +#define AT91C_UDP_ICR ( 0xFFFB0020 ) /* (UDP) Interrupt Clear Register */ +#define AT91C_UDP_RSTEP ( 0xFFFB0028 ) /* (UDP) Reset Endpoint Register */ +#define AT91C_UDP_TXVC ( 0xFFFB0074 ) /* (UDP) Transceiver Control Register */ +#define AT91C_UDP_GLBSTATE ( 0xFFFB0004 ) /* (UDP) Global State Register */ +#define AT91C_UDP_IER ( 0xFFFB0010 ) /* (UDP) Interrupt Enable Register */ +/* ========== Register definition for TC0 peripheral ========== */ +#define AT91C_TC0_SR ( 0xFFFA0020 ) /* (TC0) Status Register */ +#define AT91C_TC0_RC ( 0xFFFA001C ) /* (TC0) Register C */ +#define AT91C_TC0_RB ( 0xFFFA0018 ) /* (TC0) Register B */ +#define AT91C_TC0_CCR ( 0xFFFA0000 ) /* (TC0) Channel Control Register */ +#define AT91C_TC0_CMR ( 0xFFFA0004 ) /* (TC0) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC0_IER ( 0xFFFA0024 ) /* (TC0) Interrupt Enable Register */ +#define AT91C_TC0_RA ( 0xFFFA0014 ) /* (TC0) Register A */ +#define AT91C_TC0_IDR ( 0xFFFA0028 ) /* (TC0) Interrupt Disable Register */ +#define AT91C_TC0_CV ( 0xFFFA0010 ) /* (TC0) Counter Value */ +#define AT91C_TC0_IMR ( 0xFFFA002C ) /* (TC0) Interrupt Mask Register */ +/* ========== Register definition for TC1 peripheral ========== */ +#define AT91C_TC1_RB ( 0xFFFA0058 ) /* (TC1) Register B */ +#define AT91C_TC1_CCR ( 0xFFFA0040 ) /* (TC1) Channel Control Register */ +#define AT91C_TC1_IER ( 0xFFFA0064 ) /* (TC1) Interrupt Enable Register */ +#define AT91C_TC1_IDR ( 0xFFFA0068 ) /* (TC1) Interrupt Disable Register */ +#define AT91C_TC1_SR ( 0xFFFA0060 ) /* (TC1) Status Register */ +#define AT91C_TC1_CMR ( 0xFFFA0044 ) /* (TC1) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC1_RA ( 0xFFFA0054 ) /* (TC1) Register A */ +#define AT91C_TC1_RC ( 0xFFFA005C ) /* (TC1) Register C */ +#define AT91C_TC1_IMR ( 0xFFFA006C ) /* (TC1) Interrupt Mask Register */ +#define AT91C_TC1_CV ( 0xFFFA0050 ) /* (TC1) Counter Value */ +/* ========== Register definition for TC2 peripheral ========== */ +#define AT91C_TC2_CMR ( 0xFFFA0084 ) /* (TC2) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC2_CCR ( 0xFFFA0080 ) /* (TC2) Channel Control Register */ +#define AT91C_TC2_CV ( 0xFFFA0090 ) /* (TC2) Counter Value */ +#define AT91C_TC2_RA ( 0xFFFA0094 ) /* (TC2) Register A */ +#define AT91C_TC2_RB ( 0xFFFA0098 ) /* (TC2) Register B */ +#define AT91C_TC2_IDR ( 0xFFFA00A8 ) /* (TC2) Interrupt Disable Register */ +#define AT91C_TC2_IMR ( 0xFFFA00AC ) /* (TC2) Interrupt Mask Register */ +#define AT91C_TC2_RC ( 0xFFFA009C ) /* (TC2) Register C */ +#define AT91C_TC2_IER ( 0xFFFA00A4 ) /* (TC2) Interrupt Enable Register */ +#define AT91C_TC2_SR ( 0xFFFA00A0 ) /* (TC2) Status Register */ +/* ========== Register definition for TCB peripheral ========== */ +#define AT91C_TCB_BMR ( 0xFFFA00C4 ) /* (TCB) TC Block Mode Register */ +#define AT91C_TCB_BCR ( 0xFFFA00C0 ) /* (TCB) TC Block Control Register */ +/* ========== Register definition for CAN_MB0 peripheral ========== */ +#define AT91C_CAN_MB0_MDL ( 0xFFFD0214 ) /* (CAN_MB0) MailBox Data Low Register */ +#define AT91C_CAN_MB0_MAM ( 0xFFFD0204 ) /* (CAN_MB0) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB0_MCR ( 0xFFFD021C ) /* (CAN_MB0) MailBox Control Register */ +#define AT91C_CAN_MB0_MID ( 0xFFFD0208 ) /* (CAN_MB0) MailBox ID Register */ +#define AT91C_CAN_MB0_MSR ( 0xFFFD0210 ) /* (CAN_MB0) MailBox Status Register */ +#define AT91C_CAN_MB0_MFID ( 0xFFFD020C ) /* (CAN_MB0) MailBox Family ID Register */ +#define AT91C_CAN_MB0_MDH ( 0xFFFD0218 ) /* (CAN_MB0) MailBox Data High Register */ +#define AT91C_CAN_MB0_MMR ( 0xFFFD0200 ) /* (CAN_MB0) MailBox Mode Register */ +/* ========== Register definition for CAN_MB1 peripheral ========== */ +#define AT91C_CAN_MB1_MDL ( 0xFFFD0234 ) /* (CAN_MB1) MailBox Data Low Register */ +#define AT91C_CAN_MB1_MID ( 0xFFFD0228 ) /* (CAN_MB1) MailBox ID Register */ +#define AT91C_CAN_MB1_MMR ( 0xFFFD0220 ) /* (CAN_MB1) MailBox Mode Register */ +#define AT91C_CAN_MB1_MSR ( 0xFFFD0230 ) /* (CAN_MB1) MailBox Status Register */ +#define AT91C_CAN_MB1_MAM ( 0xFFFD0224 ) /* (CAN_MB1) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB1_MDH ( 0xFFFD0238 ) /* (CAN_MB1) MailBox Data High Register */ +#define AT91C_CAN_MB1_MCR ( 0xFFFD023C ) /* (CAN_MB1) MailBox Control Register */ +#define AT91C_CAN_MB1_MFID ( 0xFFFD022C ) /* (CAN_MB1) MailBox Family ID Register */ +/* ========== Register definition for CAN_MB2 peripheral ========== */ +#define AT91C_CAN_MB2_MCR ( 0xFFFD025C ) /* (CAN_MB2) MailBox Control Register */ +#define AT91C_CAN_MB2_MDH ( 0xFFFD0258 ) /* (CAN_MB2) MailBox Data High Register */ +#define AT91C_CAN_MB2_MID ( 0xFFFD0248 ) /* (CAN_MB2) MailBox ID Register */ +#define AT91C_CAN_MB2_MDL ( 0xFFFD0254 ) /* (CAN_MB2) MailBox Data Low Register */ +#define AT91C_CAN_MB2_MMR ( 0xFFFD0240 ) /* (CAN_MB2) MailBox Mode Register */ +#define AT91C_CAN_MB2_MAM ( 0xFFFD0244 ) /* (CAN_MB2) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB2_MFID ( 0xFFFD024C ) /* (CAN_MB2) MailBox Family ID Register */ +#define AT91C_CAN_MB2_MSR ( 0xFFFD0250 ) /* (CAN_MB2) MailBox Status Register */ +/* ========== Register definition for CAN_MB3 peripheral ========== */ +#define AT91C_CAN_MB3_MFID ( 0xFFFD026C ) /* (CAN_MB3) MailBox Family ID Register */ +#define AT91C_CAN_MB3_MAM ( 0xFFFD0264 ) /* (CAN_MB3) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB3_MID ( 0xFFFD0268 ) /* (CAN_MB3) MailBox ID Register */ +#define AT91C_CAN_MB3_MCR ( 0xFFFD027C ) /* (CAN_MB3) MailBox Control Register */ +#define AT91C_CAN_MB3_MMR ( 0xFFFD0260 ) /* (CAN_MB3) MailBox Mode Register */ +#define AT91C_CAN_MB3_MSR ( 0xFFFD0270 ) /* (CAN_MB3) MailBox Status Register */ +#define AT91C_CAN_MB3_MDL ( 0xFFFD0274 ) /* (CAN_MB3) MailBox Data Low Register */ +#define AT91C_CAN_MB3_MDH ( 0xFFFD0278 ) /* (CAN_MB3) MailBox Data High Register */ +/* ========== Register definition for CAN_MB4 peripheral ========== */ +#define AT91C_CAN_MB4_MID ( 0xFFFD0288 ) /* (CAN_MB4) MailBox ID Register */ +#define AT91C_CAN_MB4_MMR ( 0xFFFD0280 ) /* (CAN_MB4) MailBox Mode Register */ +#define AT91C_CAN_MB4_MDH ( 0xFFFD0298 ) /* (CAN_MB4) MailBox Data High Register */ +#define AT91C_CAN_MB4_MFID ( 0xFFFD028C ) /* (CAN_MB4) MailBox Family ID Register */ +#define AT91C_CAN_MB4_MSR ( 0xFFFD0290 ) /* (CAN_MB4) MailBox Status Register */ +#define AT91C_CAN_MB4_MCR ( 0xFFFD029C ) /* (CAN_MB4) MailBox Control Register */ +#define AT91C_CAN_MB4_MDL ( 0xFFFD0294 ) /* (CAN_MB4) MailBox Data Low Register */ +#define AT91C_CAN_MB4_MAM ( 0xFFFD0284 ) /* (CAN_MB4) MailBox Acceptance Mask Register */ +/* ========== Register definition for CAN_MB5 peripheral ========== */ +#define AT91C_CAN_MB5_MSR ( 0xFFFD02B0 ) /* (CAN_MB5) MailBox Status Register */ +#define AT91C_CAN_MB5_MCR ( 0xFFFD02BC ) /* (CAN_MB5) MailBox Control Register */ +#define AT91C_CAN_MB5_MFID ( 0xFFFD02AC ) /* (CAN_MB5) MailBox Family ID Register */ +#define AT91C_CAN_MB5_MDH ( 0xFFFD02B8 ) /* (CAN_MB5) MailBox Data High Register */ +#define AT91C_CAN_MB5_MID ( 0xFFFD02A8 ) /* (CAN_MB5) MailBox ID Register */ +#define AT91C_CAN_MB5_MMR ( 0xFFFD02A0 ) /* (CAN_MB5) MailBox Mode Register */ +#define AT91C_CAN_MB5_MDL ( 0xFFFD02B4 ) /* (CAN_MB5) MailBox Data Low Register */ +#define AT91C_CAN_MB5_MAM ( 0xFFFD02A4 ) /* (CAN_MB5) MailBox Acceptance Mask Register */ +/* ========== Register definition for CAN_MB6 peripheral ========== */ +#define AT91C_CAN_MB6_MFID ( 0xFFFD02CC ) /* (CAN_MB6) MailBox Family ID Register */ +#define AT91C_CAN_MB6_MID ( 0xFFFD02C8 ) /* (CAN_MB6) MailBox ID Register */ +#define AT91C_CAN_MB6_MAM ( 0xFFFD02C4 ) /* (CAN_MB6) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB6_MSR ( 0xFFFD02D0 ) /* (CAN_MB6) MailBox Status Register */ +#define AT91C_CAN_MB6_MDL ( 0xFFFD02D4 ) /* (CAN_MB6) MailBox Data Low Register */ +#define AT91C_CAN_MB6_MCR ( 0xFFFD02DC ) /* (CAN_MB6) MailBox Control Register */ +#define AT91C_CAN_MB6_MDH ( 0xFFFD02D8 ) /* (CAN_MB6) MailBox Data High Register */ +#define AT91C_CAN_MB6_MMR ( 0xFFFD02C0 ) /* (CAN_MB6) MailBox Mode Register */ +/* ========== Register definition for CAN_MB7 peripheral ========== */ +#define AT91C_CAN_MB7_MCR ( 0xFFFD02FC ) /* (CAN_MB7) MailBox Control Register */ +#define AT91C_CAN_MB7_MDH ( 0xFFFD02F8 ) /* (CAN_MB7) MailBox Data High Register */ +#define AT91C_CAN_MB7_MFID ( 0xFFFD02EC ) /* (CAN_MB7) MailBox Family ID Register */ +#define AT91C_CAN_MB7_MDL ( 0xFFFD02F4 ) /* (CAN_MB7) MailBox Data Low Register */ +#define AT91C_CAN_MB7_MID ( 0xFFFD02E8 ) /* (CAN_MB7) MailBox ID Register */ +#define AT91C_CAN_MB7_MMR ( 0xFFFD02E0 ) /* (CAN_MB7) MailBox Mode Register */ +#define AT91C_CAN_MB7_MAM ( 0xFFFD02E4 ) /* (CAN_MB7) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB7_MSR ( 0xFFFD02F0 ) /* (CAN_MB7) MailBox Status Register */ +/* ========== Register definition for CAN peripheral ========== */ +#define AT91C_CAN_TCR ( 0xFFFD0024 ) /* (CAN) Transfer Command Register */ +#define AT91C_CAN_IMR ( 0xFFFD000C ) /* (CAN) Interrupt Mask Register */ +#define AT91C_CAN_IER ( 0xFFFD0004 ) /* (CAN) Interrupt Enable Register */ +#define AT91C_CAN_ECR ( 0xFFFD0020 ) /* (CAN) Error Counter Register */ +#define AT91C_CAN_TIMESTP ( 0xFFFD001C ) /* (CAN) Time Stamp Register */ +#define AT91C_CAN_MR ( 0xFFFD0000 ) /* (CAN) Mode Register */ +#define AT91C_CAN_IDR ( 0xFFFD0008 ) /* (CAN) Interrupt Disable Register */ +#define AT91C_CAN_ACR ( 0xFFFD0028 ) /* (CAN) Abort Command Register */ +#define AT91C_CAN_TIM ( 0xFFFD0018 ) /* (CAN) Timer Register */ +#define AT91C_CAN_SR ( 0xFFFD0010 ) /* (CAN) Status Register */ +#define AT91C_CAN_BR ( 0xFFFD0014 ) /* (CAN) Baudrate Register */ +#define AT91C_CAN_VR ( 0xFFFD00FC ) /* (CAN) Version Register */ +/* ========== Register definition for EMAC peripheral ========== */ +#define AT91C_EMAC_ISR ( 0xFFFDC024 ) /* (EMAC) Interrupt Status Register */ +#define AT91C_EMAC_SA4H ( 0xFFFDC0B4 ) /* (EMAC) Specific Address 4 Top, Last 2 bytes */ +#define AT91C_EMAC_SA1L ( 0xFFFDC098 ) /* (EMAC) Specific Address 1 Bottom, First 4 bytes */ +#define AT91C_EMAC_ELE ( 0xFFFDC078 ) /* (EMAC) Excessive Length Errors Register */ +#define AT91C_EMAC_LCOL ( 0xFFFDC05C ) /* (EMAC) Late Collision Register */ +#define AT91C_EMAC_RLE ( 0xFFFDC088 ) /* (EMAC) Receive Length Field Mismatch Register */ +#define AT91C_EMAC_WOL ( 0xFFFDC0C4 ) /* (EMAC) Wake On LAN Register */ +#define AT91C_EMAC_DTF ( 0xFFFDC058 ) /* (EMAC) Deferred Transmission Frame Register */ +#define AT91C_EMAC_TUND ( 0xFFFDC064 ) /* (EMAC) Transmit Underrun Error Register */ +#define AT91C_EMAC_NCR ( 0xFFFDC000 ) /* (EMAC) Network Control Register */ +#define AT91C_EMAC_SA4L ( 0xFFFDC0B0 ) /* (EMAC) Specific Address 4 Bottom, First 4 bytes */ +#define AT91C_EMAC_RSR ( 0xFFFDC020 ) /* (EMAC) Receive Status Register */ +#define AT91C_EMAC_SA3L ( 0xFFFDC0A8 ) /* (EMAC) Specific Address 3 Bottom, First 4 bytes */ +#define AT91C_EMAC_TSR ( 0xFFFDC014 ) /* (EMAC) Transmit Status Register */ +#define AT91C_EMAC_IDR ( 0xFFFDC02C ) /* (EMAC) Interrupt Disable Register */ +#define AT91C_EMAC_RSE ( 0xFFFDC074 ) /* (EMAC) Receive Symbol Errors Register */ +#define AT91C_EMAC_ECOL ( 0xFFFDC060 ) /* (EMAC) Excessive Collision Register */ +#define AT91C_EMAC_TID ( 0xFFFDC0B8 ) /* (EMAC) Type ID Checking Register */ +#define AT91C_EMAC_HRB ( 0xFFFDC090 ) /* (EMAC) Hash Address Bottom[31:0] */ +#define AT91C_EMAC_TBQP ( 0xFFFDC01C ) /* (EMAC) Transmit Buffer Queue Pointer */ +#define AT91C_EMAC_USRIO ( 0xFFFDC0C0 ) /* (EMAC) USER Input/Output Register */ +#define AT91C_EMAC_PTR ( 0xFFFDC038 ) /* (EMAC) Pause Time Register */ +#define AT91C_EMAC_SA2H ( 0xFFFDC0A4 ) /* (EMAC) Specific Address 2 Top, Last 2 bytes */ +#define AT91C_EMAC_ROV ( 0xFFFDC070 ) /* (EMAC) Receive Overrun Errors Register */ +#define AT91C_EMAC_ALE ( 0xFFFDC054 ) /* (EMAC) Alignment Error Register */ +#define AT91C_EMAC_RJA ( 0xFFFDC07C ) /* (EMAC) Receive Jabbers Register */ +#define AT91C_EMAC_RBQP ( 0xFFFDC018 ) /* (EMAC) Receive Buffer Queue Pointer */ +#define AT91C_EMAC_TPF ( 0xFFFDC08C ) /* (EMAC) Transmitted Pause Frames Register */ +#define AT91C_EMAC_NCFGR ( 0xFFFDC004 ) /* (EMAC) Network Configuration Register */ +#define AT91C_EMAC_HRT ( 0xFFFDC094 ) /* (EMAC) Hash Address Top[63:32] */ +#define AT91C_EMAC_USF ( 0xFFFDC080 ) /* (EMAC) Undersize Frames Register */ +#define AT91C_EMAC_FCSE ( 0xFFFDC050 ) /* (EMAC) Frame Check Sequence Error Register */ +#define AT91C_EMAC_TPQ ( 0xFFFDC0BC ) /* (EMAC) Transmit Pause Quantum Register */ +#define AT91C_EMAC_MAN ( 0xFFFDC034 ) /* (EMAC) PHY Maintenance Register */ +#define AT91C_EMAC_FTO ( 0xFFFDC040 ) /* (EMAC) Frames Transmitted OK Register */ +#define AT91C_EMAC_REV ( 0xFFFDC0FC ) /* (EMAC) Revision Register */ +#define AT91C_EMAC_IMR ( 0xFFFDC030 ) /* (EMAC) Interrupt Mask Register */ +#define AT91C_EMAC_SCF ( 0xFFFDC044 ) /* (EMAC) Single Collision Frame Register */ +#define AT91C_EMAC_PFR ( 0xFFFDC03C ) /* (EMAC) Pause Frames received Register */ +#define AT91C_EMAC_MCF ( 0xFFFDC048 ) /* (EMAC) Multiple Collision Frame Register */ +#define AT91C_EMAC_NSR ( 0xFFFDC008 ) /* (EMAC) Network Status Register */ +#define AT91C_EMAC_SA2L ( 0xFFFDC0A0 ) /* (EMAC) Specific Address 2 Bottom, First 4 bytes */ +#define AT91C_EMAC_FRO ( 0xFFFDC04C ) /* (EMAC) Frames Received OK Register */ +#define AT91C_EMAC_IER ( 0xFFFDC028 ) /* (EMAC) Interrupt Enable Register */ +#define AT91C_EMAC_SA1H ( 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */ +#define AT91C_EMAC_CSE ( 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */ +#define AT91C_EMAC_SA3H ( 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */ +#define AT91C_EMAC_RRE ( 0xFFFDC06C ) /* (EMAC) Receive Resource Error Register */ +#define AT91C_EMAC_STE ( 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */ +/* ========== Register definition for PDC_ADC peripheral ========== */ +#define AT91C_ADC_PTSR ( 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */ +#define AT91C_ADC_PTCR ( 0xFFFD8120 ) /* (PDC_ADC) PDC Transfer Control Register */ +#define AT91C_ADC_TNPR ( 0xFFFD8118 ) /* (PDC_ADC) Transmit Next Pointer Register */ +#define AT91C_ADC_TNCR ( 0xFFFD811C ) /* (PDC_ADC) Transmit Next Counter Register */ +#define AT91C_ADC_RNPR ( 0xFFFD8110 ) /* (PDC_ADC) Receive Next Pointer Register */ +#define AT91C_ADC_RNCR ( 0xFFFD8114 ) /* (PDC_ADC) Receive Next Counter Register */ +#define AT91C_ADC_RPR ( 0xFFFD8100 ) /* (PDC_ADC) Receive Pointer Register */ +#define AT91C_ADC_TCR ( 0xFFFD810C ) /* (PDC_ADC) Transmit Counter Register */ +#define AT91C_ADC_TPR ( 0xFFFD8108 ) /* (PDC_ADC) Transmit Pointer Register */ +#define AT91C_ADC_RCR ( 0xFFFD8104 ) /* (PDC_ADC) Receive Counter Register */ +/* ========== Register definition for ADC peripheral ========== */ +#define AT91C_ADC_CDR2 ( 0xFFFD8038 ) /* (ADC) ADC Channel Data Register 2 */ +#define AT91C_ADC_CDR3 ( 0xFFFD803C ) /* (ADC) ADC Channel Data Register 3 */ +#define AT91C_ADC_CDR0 ( 0xFFFD8030 ) /* (ADC) ADC Channel Data Register 0 */ +#define AT91C_ADC_CDR5 ( 0xFFFD8044 ) /* (ADC) ADC Channel Data Register 5 */ +#define AT91C_ADC_CHDR ( 0xFFFD8014 ) /* (ADC) ADC Channel Disable Register */ +#define AT91C_ADC_SR ( 0xFFFD801C ) /* (ADC) ADC Status Register */ +#define AT91C_ADC_CDR4 ( 0xFFFD8040 ) /* (ADC) ADC Channel Data Register 4 */ +#define AT91C_ADC_CDR1 ( 0xFFFD8034 ) /* (ADC) ADC Channel Data Register 1 */ +#define AT91C_ADC_LCDR ( 0xFFFD8020 ) /* (ADC) ADC Last Converted Data Register */ +#define AT91C_ADC_IDR ( 0xFFFD8028 ) /* (ADC) ADC Interrupt Disable Register */ +#define AT91C_ADC_CR ( 0xFFFD8000 ) /* (ADC) ADC Control Register */ +#define AT91C_ADC_CDR7 ( 0xFFFD804C ) /* (ADC) ADC Channel Data Register 7 */ +#define AT91C_ADC_CDR6 ( 0xFFFD8048 ) /* (ADC) ADC Channel Data Register 6 */ +#define AT91C_ADC_IER ( 0xFFFD8024 ) /* (ADC) ADC Interrupt Enable Register */ +#define AT91C_ADC_CHER ( 0xFFFD8010 ) /* (ADC) ADC Channel Enable Register */ +#define AT91C_ADC_CHSR ( 0xFFFD8018 ) /* (ADC) ADC Channel Status Register */ +#define AT91C_ADC_MR ( 0xFFFD8004 ) /* (ADC) ADC Mode Register */ +#define AT91C_ADC_IMR ( 0xFFFD802C ) /* (ADC) ADC Interrupt Mask Register */ +/* ========== Register definition for PDC_AES peripheral ========== */ +#define AT91C_AES_TPR ( 0xFFFA4108 ) /* (PDC_AES) Transmit Pointer Register */ +#define AT91C_AES_PTCR ( 0xFFFA4120 ) /* (PDC_AES) PDC Transfer Control Register */ +#define AT91C_AES_RNPR ( 0xFFFA4110 ) /* (PDC_AES) Receive Next Pointer Register */ +#define AT91C_AES_TNCR ( 0xFFFA411C ) /* (PDC_AES) Transmit Next Counter Register */ +#define AT91C_AES_TCR ( 0xFFFA410C ) /* (PDC_AES) Transmit Counter Register */ +#define AT91C_AES_RCR ( 0xFFFA4104 ) /* (PDC_AES) Receive Counter Register */ +#define AT91C_AES_RNCR ( 0xFFFA4114 ) /* (PDC_AES) Receive Next Counter Register */ +#define AT91C_AES_TNPR ( 0xFFFA4118 ) /* (PDC_AES) Transmit Next Pointer Register */ +#define AT91C_AES_RPR ( 0xFFFA4100 ) /* (PDC_AES) Receive Pointer Register */ +#define AT91C_AES_PTSR ( 0xFFFA4124 ) /* (PDC_AES) PDC Transfer Status Register */ +/* ========== Register definition for AES peripheral ========== */ +#define AT91C_AES_IVxR ( 0xFFFA4060 ) /* (AES) Initialization Vector x Register */ +#define AT91C_AES_MR ( 0xFFFA4004 ) /* (AES) Mode Register */ +#define AT91C_AES_VR ( 0xFFFA40FC ) /* (AES) AES Version Register */ +#define AT91C_AES_ODATAxR ( 0xFFFA4050 ) /* (AES) Output Data x Register */ +#define AT91C_AES_IDATAxR ( 0xFFFA4040 ) /* (AES) Input Data x Register */ +#define AT91C_AES_CR ( 0xFFFA4000 ) /* (AES) Control Register */ +#define AT91C_AES_IDR ( 0xFFFA4014 ) /* (AES) Interrupt Disable Register */ +#define AT91C_AES_IMR ( 0xFFFA4018 ) /* (AES) Interrupt Mask Register */ +#define AT91C_AES_IER ( 0xFFFA4010 ) /* (AES) Interrupt Enable Register */ +#define AT91C_AES_KEYWxR ( 0xFFFA4020 ) /* (AES) Key Word x Register */ +#define AT91C_AES_ISR ( 0xFFFA401C ) /* (AES) Interrupt Status Register */ +/* ========== Register definition for PDC_TDES peripheral ========== */ +#define AT91C_TDES_RNCR ( 0xFFFA8114 ) /* (PDC_TDES) Receive Next Counter Register */ +#define AT91C_TDES_TCR ( 0xFFFA810C ) /* (PDC_TDES) Transmit Counter Register */ +#define AT91C_TDES_RCR ( 0xFFFA8104 ) /* (PDC_TDES) Receive Counter Register */ +#define AT91C_TDES_TNPR ( 0xFFFA8118 ) /* (PDC_TDES) Transmit Next Pointer Register */ +#define AT91C_TDES_RNPR ( 0xFFFA8110 ) /* (PDC_TDES) Receive Next Pointer Register */ +#define AT91C_TDES_RPR ( 0xFFFA8100 ) /* (PDC_TDES) Receive Pointer Register */ +#define AT91C_TDES_TNCR ( 0xFFFA811C ) /* (PDC_TDES) Transmit Next Counter Register */ +#define AT91C_TDES_TPR ( 0xFFFA8108 ) /* (PDC_TDES) Transmit Pointer Register */ +#define AT91C_TDES_PTSR ( 0xFFFA8124 ) /* (PDC_TDES) PDC Transfer Status Register */ +#define AT91C_TDES_PTCR ( 0xFFFA8120 ) /* (PDC_TDES) PDC Transfer Control Register */ +/* ========== Register definition for TDES peripheral ========== */ +#define AT91C_TDES_KEY2WxR ( 0xFFFA8028 ) /* (TDES) Key 2 Word x Register */ +#define AT91C_TDES_KEY3WxR ( 0xFFFA8030 ) /* (TDES) Key 3 Word x Register */ +#define AT91C_TDES_IDR ( 0xFFFA8014 ) /* (TDES) Interrupt Disable Register */ +#define AT91C_TDES_VR ( 0xFFFA80FC ) /* (TDES) TDES Version Register */ +#define AT91C_TDES_IVxR ( 0xFFFA8060 ) /* (TDES) Initialization Vector x Register */ +#define AT91C_TDES_ODATAxR ( 0xFFFA8050 ) /* (TDES) Output Data x Register */ +#define AT91C_TDES_IMR ( 0xFFFA8018 ) /* (TDES) Interrupt Mask Register */ +#define AT91C_TDES_MR ( 0xFFFA8004 ) /* (TDES) Mode Register */ +#define AT91C_TDES_CR ( 0xFFFA8000 ) /* (TDES) Control Register */ +#define AT91C_TDES_IER ( 0xFFFA8010 ) /* (TDES) Interrupt Enable Register */ +#define AT91C_TDES_ISR ( 0xFFFA801C ) /* (TDES) Interrupt Status Register */ +#define AT91C_TDES_IDATAxR ( 0xFFFA8040 ) /* (TDES) Input Data x Register */ +#define AT91C_TDES_KEY1WxR ( 0xFFFA8020 ) /* (TDES) Key 1 Word x Register */ + +/* ***************************************************************************** */ +/* PIO DEFINITIONS FOR AT91SAM7X128 */ +/* ***************************************************************************** */ +#define AT91C_PIO_PA0 ( 1 << 0 ) /* Pin Controlled by PA0 */ +#define AT91C_PA0_RXD0 ( AT91C_PIO_PA0 ) /* USART 0 Receive Data */ +#define AT91C_PIO_PA1 ( 1 << 1 ) /* Pin Controlled by PA1 */ +#define AT91C_PA1_TXD0 ( AT91C_PIO_PA1 ) /* USART 0 Transmit Data */ +#define AT91C_PIO_PA10 ( 1 << 10 ) /* Pin Controlled by PA10 */ +#define AT91C_PA10_TWD ( AT91C_PIO_PA10 ) /* TWI Two-wire Serial Data */ +#define AT91C_PIO_PA11 ( 1 << 11 ) /* Pin Controlled by PA11 */ +#define AT91C_PA11_TWCK ( AT91C_PIO_PA11 ) /* TWI Two-wire Serial Clock */ +#define AT91C_PIO_PA12 ( 1 << 12 ) /* Pin Controlled by PA12 */ +#define AT91C_PA12_NPCS00 ( AT91C_PIO_PA12 ) /* SPI 0 Peripheral Chip Select 0 */ +#define AT91C_PIO_PA13 ( 1 << 13 ) /* Pin Controlled by PA13 */ +#define AT91C_PA13_NPCS01 ( AT91C_PIO_PA13 ) /* SPI 0 Peripheral Chip Select 1 */ +#define AT91C_PA13_PCK1 ( AT91C_PIO_PA13 ) /* PMC Programmable Clock Output 1 */ +#define AT91C_PIO_PA14 ( 1 << 14 ) /* Pin Controlled by PA14 */ +#define AT91C_PA14_NPCS02 ( AT91C_PIO_PA14 ) /* SPI 0 Peripheral Chip Select 2 */ +#define AT91C_PA14_IRQ1 ( AT91C_PIO_PA14 ) /* External Interrupt 1 */ +#define AT91C_PIO_PA15 ( 1 << 15 ) /* Pin Controlled by PA15 */ +#define AT91C_PA15_NPCS03 ( AT91C_PIO_PA15 ) /* SPI 0 Peripheral Chip Select 3 */ +#define AT91C_PA15_TCLK2 ( AT91C_PIO_PA15 ) /* Timer Counter 2 external clock input */ +#define AT91C_PIO_PA16 ( 1 << 16 ) /* Pin Controlled by PA16 */ +#define AT91C_PA16_MISO0 ( AT91C_PIO_PA16 ) /* SPI 0 Master In Slave */ +#define AT91C_PIO_PA17 ( 1 << 17 ) /* Pin Controlled by PA17 */ +#define AT91C_PA17_MOSI0 ( AT91C_PIO_PA17 ) /* SPI 0 Master Out Slave */ +#define AT91C_PIO_PA18 ( 1 << 18 ) /* Pin Controlled by PA18 */ +#define AT91C_PA18_SPCK0 ( AT91C_PIO_PA18 ) /* SPI 0 Serial Clock */ +#define AT91C_PIO_PA19 ( 1 << 19 ) /* Pin Controlled by PA19 */ +#define AT91C_PA19_CANRX ( AT91C_PIO_PA19 ) /* CAN Receive */ +#define AT91C_PIO_PA2 ( 1 << 2 ) /* Pin Controlled by PA2 */ +#define AT91C_PA2_SCK0 ( AT91C_PIO_PA2 ) /* USART 0 Serial Clock */ +#define AT91C_PA2_NPCS11 ( AT91C_PIO_PA2 ) /* SPI 1 Peripheral Chip Select 1 */ +#define AT91C_PIO_PA20 ( 1 << 20 ) /* Pin Controlled by PA20 */ +#define AT91C_PA20_CANTX ( AT91C_PIO_PA20 ) /* CAN Transmit */ +#define AT91C_PIO_PA21 ( 1 << 21 ) /* Pin Controlled by PA21 */ +#define AT91C_PA21_TF ( AT91C_PIO_PA21 ) /* SSC Transmit Frame Sync */ +#define AT91C_PA21_NPCS10 ( AT91C_PIO_PA21 ) /* SPI 1 Peripheral Chip Select 0 */ +#define AT91C_PIO_PA22 ( 1 << 22 ) /* Pin Controlled by PA22 */ +#define AT91C_PA22_TK ( AT91C_PIO_PA22 ) /* SSC Transmit Clock */ +#define AT91C_PA22_SPCK1 ( AT91C_PIO_PA22 ) /* SPI 1 Serial Clock */ +#define AT91C_PIO_PA23 ( 1 << 23 ) /* Pin Controlled by PA23 */ +#define AT91C_PA23_TD ( AT91C_PIO_PA23 ) /* SSC Transmit data */ +#define AT91C_PA23_MOSI1 ( AT91C_PIO_PA23 ) /* SPI 1 Master Out Slave */ +#define AT91C_PIO_PA24 ( 1 << 24 ) /* Pin Controlled by PA24 */ +#define AT91C_PA24_RD ( AT91C_PIO_PA24 ) /* SSC Receive Data */ +#define AT91C_PA24_MISO1 ( AT91C_PIO_PA24 ) /* SPI 1 Master In Slave */ +#define AT91C_PIO_PA25 ( 1 << 25 ) /* Pin Controlled by PA25 */ +#define AT91C_PA25_RK ( AT91C_PIO_PA25 ) /* SSC Receive Clock */ +#define AT91C_PA25_NPCS11 ( AT91C_PIO_PA25 ) /* SPI 1 Peripheral Chip Select 1 */ +#define AT91C_PIO_PA26 ( 1 << 26 ) /* Pin Controlled by PA26 */ +#define AT91C_PA26_RF ( AT91C_PIO_PA26 ) /* SSC Receive Frame Sync */ +#define AT91C_PA26_NPCS12 ( AT91C_PIO_PA26 ) /* SPI 1 Peripheral Chip Select 2 */ +#define AT91C_PIO_PA27 ( 1 << 27 ) /* Pin Controlled by PA27 */ +#define AT91C_PA27_DRXD ( AT91C_PIO_PA27 ) /* DBGU Debug Receive Data */ +#define AT91C_PA27_PCK3 ( AT91C_PIO_PA27 ) /* PMC Programmable Clock Output 3 */ +#define AT91C_PIO_PA28 ( 1 << 28 ) /* Pin Controlled by PA28 */ +#define AT91C_PA28_DTXD ( AT91C_PIO_PA28 ) /* DBGU Debug Transmit Data */ +#define AT91C_PIO_PA29 ( 1 << 29 ) /* Pin Controlled by PA29 */ +#define AT91C_PA29_FIQ ( AT91C_PIO_PA29 ) /* AIC Fast Interrupt Input */ +#define AT91C_PA29_NPCS13 ( AT91C_PIO_PA29 ) /* SPI 1 Peripheral Chip Select 3 */ +#define AT91C_PIO_PA3 ( 1 << 3 ) /* Pin Controlled by PA3 */ +#define AT91C_PA3_RTS0 ( AT91C_PIO_PA3 ) /* USART 0 Ready To Send */ +#define AT91C_PA3_NPCS12 ( AT91C_PIO_PA3 ) /* SPI 1 Peripheral Chip Select 2 */ +#define AT91C_PIO_PA30 ( 1 << 30 ) /* Pin Controlled by PA30 */ +#define AT91C_PA30_IRQ0 ( AT91C_PIO_PA30 ) /* External Interrupt 0 */ +#define AT91C_PA30_PCK2 ( AT91C_PIO_PA30 ) /* PMC Programmable Clock Output 2 */ +#define AT91C_PIO_PA4 ( 1 << 4 ) /* Pin Controlled by PA4 */ +#define AT91C_PA4_CTS0 ( AT91C_PIO_PA4 ) /* USART 0 Clear To Send */ +#define AT91C_PA4_NPCS13 ( AT91C_PIO_PA4 ) /* SPI 1 Peripheral Chip Select 3 */ +#define AT91C_PIO_PA5 ( 1 << 5 ) /* Pin Controlled by PA5 */ +#define AT91C_PA5_RXD1 ( AT91C_PIO_PA5 ) /* USART 1 Receive Data */ +#define AT91C_PIO_PA6 ( 1 << 6 ) /* Pin Controlled by PA6 */ +#define AT91C_PA6_TXD1 ( AT91C_PIO_PA6 ) /* USART 1 Transmit Data */ +#define AT91C_PIO_PA7 ( 1 << 7 ) /* Pin Controlled by PA7 */ +#define AT91C_PA7_SCK1 ( AT91C_PIO_PA7 ) /* USART 1 Serial Clock */ +#define AT91C_PA7_NPCS01 ( AT91C_PIO_PA7 ) /* SPI 0 Peripheral Chip Select 1 */ +#define AT91C_PIO_PA8 ( 1 << 8 ) /* Pin Controlled by PA8 */ +#define AT91C_PA8_RTS1 ( AT91C_PIO_PA8 ) /* USART 1 Ready To Send */ +#define AT91C_PA8_NPCS02 ( AT91C_PIO_PA8 ) /* SPI 0 Peripheral Chip Select 2 */ +#define AT91C_PIO_PA9 ( 1 << 9 ) /* Pin Controlled by PA9 */ +#define AT91C_PA9_CTS1 ( AT91C_PIO_PA9 ) /* USART 1 Clear To Send */ +#define AT91C_PA9_NPCS03 ( AT91C_PIO_PA9 ) /* SPI 0 Peripheral Chip Select 3 */ +#define AT91C_PIO_PB0 ( 1 << 0 ) /* Pin Controlled by PB0 */ +#define AT91C_PB0_ETXCK_EREFCK ( AT91C_PIO_PB0 ) /* Ethernet MAC Transmit Clock/Reference Clock */ +#define AT91C_PB0_PCK0 ( AT91C_PIO_PB0 ) /* PMC Programmable Clock Output 0 */ +#define AT91C_PIO_PB1 ( 1 << 1 ) /* Pin Controlled by PB1 */ +#define AT91C_PB1_ETXEN ( AT91C_PIO_PB1 ) /* Ethernet MAC Transmit Enable */ +#define AT91C_PIO_PB10 ( 1 << 10 ) /* Pin Controlled by PB10 */ +#define AT91C_PB10_ETX2 ( AT91C_PIO_PB10 ) /* Ethernet MAC Transmit Data 2 */ +#define AT91C_PB10_NPCS11 ( AT91C_PIO_PB10 ) /* SPI 1 Peripheral Chip Select 1 */ +#define AT91C_PIO_PB11 ( 1 << 11 ) /* Pin Controlled by PB11 */ +#define AT91C_PB11_ETX3 ( AT91C_PIO_PB11 ) /* Ethernet MAC Transmit Data 3 */ +#define AT91C_PB11_NPCS12 ( AT91C_PIO_PB11 ) /* SPI 1 Peripheral Chip Select 2 */ +#define AT91C_PIO_PB12 ( 1 << 12 ) /* Pin Controlled by PB12 */ +#define AT91C_PB12_ETXER ( AT91C_PIO_PB12 ) /* Ethernet MAC Transmit Coding Error */ +#define AT91C_PB12_TCLK0 ( AT91C_PIO_PB12 ) /* Timer Counter 0 external clock input */ +#define AT91C_PIO_PB13 ( 1 << 13 ) /* Pin Controlled by PB13 */ +#define AT91C_PB13_ERX2 ( AT91C_PIO_PB13 ) /* Ethernet MAC Receive Data 2 */ +#define AT91C_PB13_NPCS01 ( AT91C_PIO_PB13 ) /* SPI 0 Peripheral Chip Select 1 */ +#define AT91C_PIO_PB14 ( 1 << 14 ) /* Pin Controlled by PB14 */ +#define AT91C_PB14_ERX3 ( AT91C_PIO_PB14 ) /* Ethernet MAC Receive Data 3 */ +#define AT91C_PB14_NPCS02 ( AT91C_PIO_PB14 ) /* SPI 0 Peripheral Chip Select 2 */ +#define AT91C_PIO_PB15 ( 1 << 15 ) /* Pin Controlled by PB15 */ +#define AT91C_PB15_ERXDV ( AT91C_PIO_PB15 ) /* Ethernet MAC Receive Data Valid */ +#define AT91C_PIO_PB16 ( 1 << 16 ) /* Pin Controlled by PB16 */ +#define AT91C_PB16_ECOL ( AT91C_PIO_PB16 ) /* Ethernet MAC Collision Detected */ +#define AT91C_PB16_NPCS13 ( AT91C_PIO_PB16 ) /* SPI 1 Peripheral Chip Select 3 */ +#define AT91C_PIO_PB17 ( 1 << 17 ) /* Pin Controlled by PB17 */ +#define AT91C_PB17_ERXCK ( AT91C_PIO_PB17 ) /* Ethernet MAC Receive Clock */ +#define AT91C_PB17_NPCS03 ( AT91C_PIO_PB17 ) /* SPI 0 Peripheral Chip Select 3 */ +#define AT91C_PIO_PB18 ( 1 << 18 ) /* Pin Controlled by PB18 */ +#define AT91C_PB18_EF100 ( AT91C_PIO_PB18 ) /* Ethernet MAC Force 100 Mbits/sec */ +#define AT91C_PB18_ADTRG ( AT91C_PIO_PB18 ) /* ADC External Trigger */ +#define AT91C_PIO_PB19 ( 1 << 19 ) /* Pin Controlled by PB19 */ +#define AT91C_PB19_PWM0 ( AT91C_PIO_PB19 ) /* PWM Channel 0 */ +#define AT91C_PB19_TCLK1 ( AT91C_PIO_PB19 ) /* Timer Counter 1 external clock input */ +#define AT91C_PIO_PB2 ( 1 << 2 ) /* Pin Controlled by PB2 */ +#define AT91C_PB2_ETX0 ( AT91C_PIO_PB2 ) /* Ethernet MAC Transmit Data 0 */ +#define AT91C_PIO_PB20 ( 1 << 20 ) /* Pin Controlled by PB20 */ +#define AT91C_PB20_PWM1 ( AT91C_PIO_PB20 ) /* PWM Channel 1 */ +#define AT91C_PB20_PCK0 ( AT91C_PIO_PB20 ) /* PMC Programmable Clock Output 0 */ +#define AT91C_PIO_PB21 ( 1 << 21 ) /* Pin Controlled by PB21 */ +#define AT91C_PB21_PWM2 ( AT91C_PIO_PB21 ) /* PWM Channel 2 */ +#define AT91C_PB21_PCK1 ( AT91C_PIO_PB21 ) /* PMC Programmable Clock Output 1 */ +#define AT91C_PIO_PB22 ( 1 << 22 ) /* Pin Controlled by PB22 */ +#define AT91C_PB22_PWM3 ( AT91C_PIO_PB22 ) /* PWM Channel 3 */ +#define AT91C_PB22_PCK2 ( AT91C_PIO_PB22 ) /* PMC Programmable Clock Output 2 */ +#define AT91C_PIO_PB23 ( 1 << 23 ) /* Pin Controlled by PB23 */ +#define AT91C_PB23_TIOA0 ( AT91C_PIO_PB23 ) /* Timer Counter 0 Multipurpose Timer I/O Pin A */ +#define AT91C_PB23_DCD1 ( AT91C_PIO_PB23 ) /* USART 1 Data Carrier Detect */ +#define AT91C_PIO_PB24 ( 1 << 24 ) /* Pin Controlled by PB24 */ +#define AT91C_PB24_TIOB0 ( AT91C_PIO_PB24 ) /* Timer Counter 0 Multipurpose Timer I/O Pin B */ +#define AT91C_PB24_DSR1 ( AT91C_PIO_PB24 ) /* USART 1 Data Set ready */ +#define AT91C_PIO_PB25 ( 1 << 25 ) /* Pin Controlled by PB25 */ +#define AT91C_PB25_TIOA1 ( AT91C_PIO_PB25 ) /* Timer Counter 1 Multipurpose Timer I/O Pin A */ +#define AT91C_PB25_DTR1 ( AT91C_PIO_PB25 ) /* USART 1 Data Terminal ready */ +#define AT91C_PIO_PB26 ( 1 << 26 ) /* Pin Controlled by PB26 */ +#define AT91C_PB26_TIOB1 ( AT91C_PIO_PB26 ) /* Timer Counter 1 Multipurpose Timer I/O Pin B */ +#define AT91C_PB26_RI1 ( AT91C_PIO_PB26 ) /* USART 1 Ring Indicator */ +#define AT91C_PIO_PB27 ( 1 << 27 ) /* Pin Controlled by PB27 */ +#define AT91C_PB27_TIOA2 ( AT91C_PIO_PB27 ) /* Timer Counter 2 Multipurpose Timer I/O Pin A */ +#define AT91C_PB27_PWM0 ( AT91C_PIO_PB27 ) /* PWM Channel 0 */ +#define AT91C_PIO_PB28 ( 1 << 28 ) /* Pin Controlled by PB28 */ +#define AT91C_PB28_TIOB2 ( AT91C_PIO_PB28 ) /* Timer Counter 2 Multipurpose Timer I/O Pin B */ +#define AT91C_PB28_PWM1 ( AT91C_PIO_PB28 ) /* PWM Channel 1 */ +#define AT91C_PIO_PB29 ( 1 << 29 ) /* Pin Controlled by PB29 */ +#define AT91C_PB29_PCK1 ( AT91C_PIO_PB29 ) /* PMC Programmable Clock Output 1 */ +#define AT91C_PB29_PWM2 ( AT91C_PIO_PB29 ) /* PWM Channel 2 */ +#define AT91C_PIO_PB3 ( 1 << 3 ) /* Pin Controlled by PB3 */ +#define AT91C_PB3_ETX1 ( AT91C_PIO_PB3 ) /* Ethernet MAC Transmit Data 1 */ +#define AT91C_PIO_PB30 ( 1 << 30 ) /* Pin Controlled by PB30 */ +#define AT91C_PB30_PCK2 ( AT91C_PIO_PB30 ) /* PMC Programmable Clock Output 2 */ +#define AT91C_PB30_PWM3 ( AT91C_PIO_PB30 ) /* PWM Channel 3 */ +#define AT91C_PIO_PB4 ( 1 << 4 ) /* Pin Controlled by PB4 */ +#define AT91C_PB4_ECRS_ECRSDV ( AT91C_PIO_PB4 ) /* Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */ +#define AT91C_PIO_PB5 ( 1 << 5 ) /* Pin Controlled by PB5 */ +#define AT91C_PB5_ERX0 ( AT91C_PIO_PB5 ) /* Ethernet MAC Receive Data 0 */ +#define AT91C_PIO_PB6 ( 1 << 6 ) /* Pin Controlled by PB6 */ +#define AT91C_PB6_ERX1 ( AT91C_PIO_PB6 ) /* Ethernet MAC Receive Data 1 */ +#define AT91C_PIO_PB7 ( 1 << 7 ) /* Pin Controlled by PB7 */ +#define AT91C_PB7_ERXER ( AT91C_PIO_PB7 ) /* Ethernet MAC Receive Error */ +#define AT91C_PIO_PB8 ( 1 << 8 ) /* Pin Controlled by PB8 */ +#define AT91C_PB8_EMDC ( AT91C_PIO_PB8 ) /* Ethernet MAC Management Data Clock */ +#define AT91C_PIO_PB9 ( 1 << 9 ) /* Pin Controlled by PB9 */ +#define AT91C_PB9_EMDIO ( AT91C_PIO_PB9 ) /* Ethernet MAC Management Data Input/Output */ + +/* ***************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128 */ +/* ***************************************************************************** */ +#define AT91C_ID_FIQ ( 0 ) /* Advanced Interrupt Controller (FIQ) */ +#define AT91C_ID_SYS ( 1 ) /* System Peripheral */ +#define AT91C_ID_PIOA ( 2 ) /* Parallel IO Controller A */ +#define AT91C_ID_PIOB ( 3 ) /* Parallel IO Controller B */ +#define AT91C_ID_SPI0 ( 4 ) /* Serial Peripheral Interface 0 */ +#define AT91C_ID_SPI1 ( 5 ) /* Serial Peripheral Interface 1 */ +#define AT91C_ID_US0 ( 6 ) /* USART 0 */ +#define AT91C_ID_US1 ( 7 ) /* USART 1 */ +#define AT91C_ID_SSC ( 8 ) /* Serial Synchronous Controller */ +#define AT91C_ID_TWI ( 9 ) /* Two-Wire Interface */ +#define AT91C_ID_PWMC ( 10 ) /* PWM Controller */ +#define AT91C_ID_UDP ( 11 ) /* USB Device Port */ +#define AT91C_ID_TC0 ( 12 ) /* Timer Counter 0 */ +#define AT91C_ID_TC1 ( 13 ) /* Timer Counter 1 */ +#define AT91C_ID_TC2 ( 14 ) /* Timer Counter 2 */ +#define AT91C_ID_CAN ( 15 ) /* Control Area Network Controller */ +#define AT91C_ID_EMAC ( 16 ) /* Ethernet MAC */ +#define AT91C_ID_ADC ( 17 ) /* Analog-to-Digital Converter */ +#define AT91C_ID_AES ( 18 ) /* Advanced Encryption Standard 128-bit */ +#define AT91C_ID_TDES ( 19 ) /* Triple Data Encryption Standard */ +#define AT91C_ID_20_Reserved ( 20 ) /* Reserved */ +#define AT91C_ID_21_Reserved ( 21 ) /* Reserved */ +#define AT91C_ID_22_Reserved ( 22 ) /* Reserved */ +#define AT91C_ID_23_Reserved ( 23 ) /* Reserved */ +#define AT91C_ID_24_Reserved ( 24 ) /* Reserved */ +#define AT91C_ID_25_Reserved ( 25 ) /* Reserved */ +#define AT91C_ID_26_Reserved ( 26 ) /* Reserved */ +#define AT91C_ID_27_Reserved ( 27 ) /* Reserved */ +#define AT91C_ID_28_Reserved ( 28 ) /* Reserved */ +#define AT91C_ID_29_Reserved ( 29 ) /* Reserved */ +#define AT91C_ID_IRQ0 ( 30 ) /* Advanced Interrupt Controller (IRQ0) */ +#define AT91C_ID_IRQ1 ( 31 ) /* Advanced Interrupt Controller (IRQ1) */ + +/* ***************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR AT91SAM7X128 */ +/* ***************************************************************************** */ +#define AT91C_BASE_SYS ( 0xFFFFF000 ) /* (SYS) Base Address */ +#define AT91C_BASE_AIC ( 0xFFFFF000 ) /* (AIC) Base Address */ +#define AT91C_BASE_PDC_DBGU ( 0xFFFFF300 ) /* (PDC_DBGU) Base Address */ +#define AT91C_BASE_DBGU ( 0xFFFFF200 ) /* (DBGU) Base Address */ +#define AT91C_BASE_PIOA ( 0xFFFFF400 ) /* (PIOA) Base Address */ +#define AT91C_BASE_PIOB ( 0xFFFFF600 ) /* (PIOB) Base Address */ +#define AT91C_BASE_CKGR ( 0xFFFFFC20 ) /* (CKGR) Base Address */ +#define AT91C_BASE_PMC ( 0xFFFFFC00 ) /* (PMC) Base Address */ +#define AT91C_BASE_RSTC ( 0xFFFFFD00 ) /* (RSTC) Base Address */ +#define AT91C_BASE_RTTC ( 0xFFFFFD20 ) /* (RTTC) Base Address */ +#define AT91C_BASE_PITC ( 0xFFFFFD30 ) /* (PITC) Base Address */ +#define AT91C_BASE_WDTC ( 0xFFFFFD40 ) /* (WDTC) Base Address */ +#define AT91C_BASE_VREG ( 0xFFFFFD60 ) /* (VREG) Base Address */ +#define AT91C_BASE_MC ( 0xFFFFFF00 ) /* (MC) Base Address */ +#define AT91C_BASE_PDC_SPI1 ( 0xFFFE4100 ) /* (PDC_SPI1) Base Address */ +#define AT91C_BASE_SPI1 ( 0xFFFE4000 ) /* (SPI1) Base Address */ +#define AT91C_BASE_PDC_SPI0 ( 0xFFFE0100 ) /* (PDC_SPI0) Base Address */ +#define AT91C_BASE_SPI0 ( 0xFFFE0000 ) /* (SPI0) Base Address */ +#define AT91C_BASE_PDC_US1 ( 0xFFFC4100 ) /* (PDC_US1) Base Address */ +#define AT91C_BASE_US1 ( 0xFFFC4000 ) /* (US1) Base Address */ +#define AT91C_BASE_PDC_US0 ( 0xFFFC0100 ) /* (PDC_US0) Base Address */ +#define AT91C_BASE_US0 ( 0xFFFC0000 ) /* (US0) Base Address */ +#define AT91C_BASE_PDC_SSC ( 0xFFFD4100 ) /* (PDC_SSC) Base Address */ +#define AT91C_BASE_SSC ( 0xFFFD4000 ) /* (SSC) Base Address */ +#define AT91C_BASE_TWI ( 0xFFFB8000 ) /* (TWI) Base Address */ +#define AT91C_BASE_PWMC_CH3 ( 0xFFFCC260 ) /* (PWMC_CH3) Base Address */ +#define AT91C_BASE_PWMC_CH2 ( 0xFFFCC240 ) /* (PWMC_CH2) Base Address */ +#define AT91C_BASE_PWMC_CH1 ( 0xFFFCC220 ) /* (PWMC_CH1) Base Address */ +#define AT91C_BASE_PWMC_CH0 ( 0xFFFCC200 ) /* (PWMC_CH0) Base Address */ +#define AT91C_BASE_PWMC ( 0xFFFCC000 ) /* (PWMC) Base Address */ +#define AT91C_BASE_UDP ( 0xFFFB0000 ) /* (UDP) Base Address */ +#define AT91C_BASE_TC0 ( 0xFFFA0000 ) /* (TC0) Base Address */ +#define AT91C_BASE_TC1 ( 0xFFFA0040 ) /* (TC1) Base Address */ +#define AT91C_BASE_TC2 ( 0xFFFA0080 ) /* (TC2) Base Address */ +#define AT91C_BASE_TCB ( 0xFFFA0000 ) /* (TCB) Base Address */ +#define AT91C_BASE_CAN_MB0 ( 0xFFFD0200 ) /* (CAN_MB0) Base Address */ +#define AT91C_BASE_CAN_MB1 ( 0xFFFD0220 ) /* (CAN_MB1) Base Address */ +#define AT91C_BASE_CAN_MB2 ( 0xFFFD0240 ) /* (CAN_MB2) Base Address */ +#define AT91C_BASE_CAN_MB3 ( 0xFFFD0260 ) /* (CAN_MB3) Base Address */ +#define AT91C_BASE_CAN_MB4 ( 0xFFFD0280 ) /* (CAN_MB4) Base Address */ +#define AT91C_BASE_CAN_MB5 ( 0xFFFD02A0 ) /* (CAN_MB5) Base Address */ +#define AT91C_BASE_CAN_MB6 ( 0xFFFD02C0 ) /* (CAN_MB6) Base Address */ +#define AT91C_BASE_CAN_MB7 ( 0xFFFD02E0 ) /* (CAN_MB7) Base Address */ +#define AT91C_BASE_CAN ( 0xFFFD0000 ) /* (CAN) Base Address */ +#define AT91C_BASE_EMAC ( 0xFFFDC000 ) /* (EMAC) Base Address */ +#define AT91C_BASE_PDC_ADC ( 0xFFFD8100 ) /* (PDC_ADC) Base Address */ +#define AT91C_BASE_ADC ( 0xFFFD8000 ) /* (ADC) Base Address */ +#define AT91C_BASE_PDC_AES ( 0xFFFA4100 ) /* (PDC_AES) Base Address */ +#define AT91C_BASE_AES ( 0xFFFA4000 ) /* (AES) Base Address */ +#define AT91C_BASE_PDC_TDES ( 0xFFFA8100 ) /* (PDC_TDES) Base Address */ +#define AT91C_BASE_TDES ( 0xFFFA8000 ) /* (TDES) Base Address */ + +/* ***************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128 */ +/* ***************************************************************************** */ +#define AT91C_ISRAM ( 0x00200000 ) /* Internal SRAM base address */ +#define AT91C_ISRAM_SIZE ( 0x00008000 ) /* Internal SRAM size in byte (32 Kbyte) */ +#define AT91C_IFLASH ( 0x00100000 ) /* Internal ROM base address */ +#define AT91C_IFLASH_SIZE ( 0x00020000 ) /* Internal ROM size in byte (128 Kbyte) */ diff --git a/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h b/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h new file mode 100644 index 000000000..f51209974 --- /dev/null +++ b/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h @@ -0,0 +1,2743 @@ +/* ---------------------------------------------------------------------------- */ +/* ATMEL Microcontroller Software Support - ROUSSET - */ +/* ---------------------------------------------------------------------------- */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ +/* File Name : AT91SAM7X256.h */ +/* Object : AT91SAM7X256 definitions */ +/* Generated : AT91 SW Application Group 05/20/2005 (16:22:29) */ +/* */ +/* CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005// */ +/* CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// */ +/* CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// */ +/* CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// */ +/* CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// */ +/* CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// */ +/* CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// */ +/* CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// */ +/* CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// */ +/* CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// */ +/* CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// */ +/* CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// */ +/* CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// */ +/* CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// */ +/* CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// */ +/* CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// */ +/* CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// */ +/* CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// */ +/* CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// */ +/* CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// */ +/* CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// */ +/* CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// */ +/* CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// */ +/* CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// */ +/* CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// */ +/* ---------------------------------------------------------------------------- */ + +#ifndef AT91SAM7X256_H +#define AT91SAM7X256_H + +typedef volatile unsigned int AT91_REG; /* Hardware register definition */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR System Peripherals */ +/* ***************************************************************************** */ +typedef struct _AT91S_SYS +{ + AT91_REG AIC_SMR[ 32 ]; /* Source Mode Register */ + AT91_REG AIC_SVR[ 32 ]; /* Source Vector Register */ + AT91_REG AIC_IVR; /* IRQ Vector Register */ + AT91_REG AIC_FVR; /* FIQ Vector Register */ + AT91_REG AIC_ISR; /* Interrupt Status Register */ + AT91_REG AIC_IPR; /* Interrupt Pending Register */ + AT91_REG AIC_IMR; /* Interrupt Mask Register */ + AT91_REG AIC_CISR; /* Core Interrupt Status Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG AIC_IECR; /* Interrupt Enable Command Register */ + AT91_REG AIC_IDCR; /* Interrupt Disable Command Register */ + AT91_REG AIC_ICCR; /* Interrupt Clear Command Register */ + AT91_REG AIC_ISCR; /* Interrupt Set Command Register */ + AT91_REG AIC_EOICR; /* End of Interrupt Command Register */ + AT91_REG AIC_SPU; /* Spurious Vector Register */ + AT91_REG AIC_DCR; /* Debug Control Register (Protect) */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG AIC_FFER; /* Fast Forcing Enable Register */ + AT91_REG AIC_FFDR; /* Fast Forcing Disable Register */ + AT91_REG AIC_FFSR; /* Fast Forcing Status Register */ + AT91_REG Reserved2[ 45 ]; /* */ + AT91_REG DBGU_CR; /* Control Register */ + AT91_REG DBGU_MR; /* Mode Register */ + AT91_REG DBGU_IER; /* Interrupt Enable Register */ + AT91_REG DBGU_IDR; /* Interrupt Disable Register */ + AT91_REG DBGU_IMR; /* Interrupt Mask Register */ + AT91_REG DBGU_CSR; /* Channel Status Register */ + AT91_REG DBGU_RHR; /* Receiver Holding Register */ + AT91_REG DBGU_THR; /* Transmitter Holding Register */ + AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */ + AT91_REG Reserved3[ 7 ]; /* */ + AT91_REG DBGU_CIDR; /* Chip ID Register */ + AT91_REG DBGU_EXID; /* Chip ID Extension Register */ + AT91_REG DBGU_FNTR; /* Force NTRST Register */ + AT91_REG Reserved4[ 45 ]; /* */ + AT91_REG DBGU_RPR; /* Receive Pointer Register */ + AT91_REG DBGU_RCR; /* Receive Counter Register */ + AT91_REG DBGU_TPR; /* Transmit Pointer Register */ + AT91_REG DBGU_TCR; /* Transmit Counter Register */ + AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */ + AT91_REG DBGU_RNCR; /* Receive Next Counter Register */ + AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */ + AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */ + AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */ + AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */ + AT91_REG Reserved5[ 54 ]; /* */ + AT91_REG PIOA_PER; /* PIO Enable Register */ + AT91_REG PIOA_PDR; /* PIO Disable Register */ + AT91_REG PIOA_PSR; /* PIO Status Register */ + AT91_REG Reserved6[ 1 ]; /* */ + AT91_REG PIOA_OER; /* Output Enable Register */ + AT91_REG PIOA_ODR; /* Output Disable Registerr */ + AT91_REG PIOA_OSR; /* Output Status Register */ + AT91_REG Reserved7[ 1 ]; /* */ + AT91_REG PIOA_IFER; /* Input Filter Enable Register */ + AT91_REG PIOA_IFDR; /* Input Filter Disable Register */ + AT91_REG PIOA_IFSR; /* Input Filter Status Register */ + AT91_REG Reserved8[ 1 ]; /* */ + AT91_REG PIOA_SODR; /* Set Output Data Register */ + AT91_REG PIOA_CODR; /* Clear Output Data Register */ + AT91_REG PIOA_ODSR; /* Output Data Status Register */ + AT91_REG PIOA_PDSR; /* Pin Data Status Register */ + AT91_REG PIOA_IER; /* Interrupt Enable Register */ + AT91_REG PIOA_IDR; /* Interrupt Disable Register */ + AT91_REG PIOA_IMR; /* Interrupt Mask Register */ + AT91_REG PIOA_ISR; /* Interrupt Status Register */ + AT91_REG PIOA_MDER; /* Multi-driver Enable Register */ + AT91_REG PIOA_MDDR; /* Multi-driver Disable Register */ + AT91_REG PIOA_MDSR; /* Multi-driver Status Register */ + AT91_REG Reserved9[ 1 ]; /* */ + AT91_REG PIOA_PPUDR; /* Pull-up Disable Register */ + AT91_REG PIOA_PPUER; /* Pull-up Enable Register */ + AT91_REG PIOA_PPUSR; /* Pull-up Status Register */ + AT91_REG Reserved10[ 1 ]; /* */ + AT91_REG PIOA_ASR; /* Select A Register */ + AT91_REG PIOA_BSR; /* Select B Register */ + AT91_REG PIOA_ABSR; /* AB Select Status Register */ + AT91_REG Reserved11[ 9 ]; /* */ + AT91_REG PIOA_OWER; /* Output Write Enable Register */ + AT91_REG PIOA_OWDR; /* Output Write Disable Register */ + AT91_REG PIOA_OWSR; /* Output Write Status Register */ + AT91_REG Reserved12[ 85 ]; /* */ + AT91_REG PIOB_PER; /* PIO Enable Register */ + AT91_REG PIOB_PDR; /* PIO Disable Register */ + AT91_REG PIOB_PSR; /* PIO Status Register */ + AT91_REG Reserved13[ 1 ]; /* */ + AT91_REG PIOB_OER; /* Output Enable Register */ + AT91_REG PIOB_ODR; /* Output Disable Registerr */ + AT91_REG PIOB_OSR; /* Output Status Register */ + AT91_REG Reserved14[ 1 ]; /* */ + AT91_REG PIOB_IFER; /* Input Filter Enable Register */ + AT91_REG PIOB_IFDR; /* Input Filter Disable Register */ + AT91_REG PIOB_IFSR; /* Input Filter Status Register */ + AT91_REG Reserved15[ 1 ]; /* */ + AT91_REG PIOB_SODR; /* Set Output Data Register */ + AT91_REG PIOB_CODR; /* Clear Output Data Register */ + AT91_REG PIOB_ODSR; /* Output Data Status Register */ + AT91_REG PIOB_PDSR; /* Pin Data Status Register */ + AT91_REG PIOB_IER; /* Interrupt Enable Register */ + AT91_REG PIOB_IDR; /* Interrupt Disable Register */ + AT91_REG PIOB_IMR; /* Interrupt Mask Register */ + AT91_REG PIOB_ISR; /* Interrupt Status Register */ + AT91_REG PIOB_MDER; /* Multi-driver Enable Register */ + AT91_REG PIOB_MDDR; /* Multi-driver Disable Register */ + AT91_REG PIOB_MDSR; /* Multi-driver Status Register */ + AT91_REG Reserved16[ 1 ]; /* */ + AT91_REG PIOB_PPUDR; /* Pull-up Disable Register */ + AT91_REG PIOB_PPUER; /* Pull-up Enable Register */ + AT91_REG PIOB_PPUSR; /* Pull-up Status Register */ + AT91_REG Reserved17[ 1 ]; /* */ + AT91_REG PIOB_ASR; /* Select A Register */ + AT91_REG PIOB_BSR; /* Select B Register */ + AT91_REG PIOB_ABSR; /* AB Select Status Register */ + AT91_REG Reserved18[ 9 ]; /* */ + AT91_REG PIOB_OWER; /* Output Write Enable Register */ + AT91_REG PIOB_OWDR; /* Output Write Disable Register */ + AT91_REG PIOB_OWSR; /* Output Write Status Register */ + AT91_REG Reserved19[ 341 ]; /* */ + AT91_REG PMC_SCER; /* System Clock Enable Register */ + AT91_REG PMC_SCDR; /* System Clock Disable Register */ + AT91_REG PMC_SCSR; /* System Clock Status Register */ + AT91_REG Reserved20[ 1 ]; /* */ + AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */ + AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */ + AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */ + AT91_REG Reserved21[ 1 ]; /* */ + AT91_REG PMC_MOR; /* Main Oscillator Register */ + AT91_REG PMC_MCFR; /* Main Clock Frequency Register */ + AT91_REG Reserved22[ 1 ]; /* */ + AT91_REG PMC_PLLR; /* PLL Register */ + AT91_REG PMC_MCKR; /* Master Clock Register */ + AT91_REG Reserved23[ 3 ]; /* */ + AT91_REG PMC_PCKR[ 4 ]; /* Programmable Clock Register */ + AT91_REG Reserved24[ 4 ]; /* */ + AT91_REG PMC_IER; /* Interrupt Enable Register */ + AT91_REG PMC_IDR; /* Interrupt Disable Register */ + AT91_REG PMC_SR; /* Status Register */ + AT91_REG PMC_IMR; /* Interrupt Mask Register */ + AT91_REG Reserved25[ 36 ]; /* */ + AT91_REG RSTC_RCR; /* Reset Control Register */ + AT91_REG RSTC_RSR; /* Reset Status Register */ + AT91_REG RSTC_RMR; /* Reset Mode Register */ + AT91_REG Reserved26[ 5 ]; /* */ + AT91_REG RTTC_RTMR; /* Real-time Mode Register */ + AT91_REG RTTC_RTAR; /* Real-time Alarm Register */ + AT91_REG RTTC_RTVR; /* Real-time Value Register */ + AT91_REG RTTC_RTSR; /* Real-time Status Register */ + AT91_REG PITC_PIMR; /* Period Interval Mode Register */ + AT91_REG PITC_PISR; /* Period Interval Status Register */ + AT91_REG PITC_PIVR; /* Period Interval Value Register */ + AT91_REG PITC_PIIR; /* Period Interval Image Register */ + AT91_REG WDTC_WDCR; /* Watchdog Control Register */ + AT91_REG WDTC_WDMR; /* Watchdog Mode Register */ + AT91_REG WDTC_WDSR; /* Watchdog Status Register */ + AT91_REG Reserved27[ 5 ]; /* */ + AT91_REG VREG_MR; /* Voltage Regulator Mode Register */ +} AT91S_SYS, * AT91PS_SYS; + + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Advanced Interrupt Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_AIC +{ + AT91_REG AIC_SMR[ 32 ]; /* Source Mode Register */ + AT91_REG AIC_SVR[ 32 ]; /* Source Vector Register */ + AT91_REG AIC_IVR; /* IRQ Vector Register */ + AT91_REG AIC_FVR; /* FIQ Vector Register */ + AT91_REG AIC_ISR; /* Interrupt Status Register */ + AT91_REG AIC_IPR; /* Interrupt Pending Register */ + AT91_REG AIC_IMR; /* Interrupt Mask Register */ + AT91_REG AIC_CISR; /* Core Interrupt Status Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG AIC_IECR; /* Interrupt Enable Command Register */ + AT91_REG AIC_IDCR; /* Interrupt Disable Command Register */ + AT91_REG AIC_ICCR; /* Interrupt Clear Command Register */ + AT91_REG AIC_ISCR; /* Interrupt Set Command Register */ + AT91_REG AIC_EOICR; /* End of Interrupt Command Register */ + AT91_REG AIC_SPU; /* Spurious Vector Register */ + AT91_REG AIC_DCR; /* Debug Control Register (Protect) */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG AIC_FFER; /* Fast Forcing Enable Register */ + AT91_REG AIC_FFDR; /* Fast Forcing Disable Register */ + AT91_REG AIC_FFSR; /* Fast Forcing Status Register */ +} AT91S_AIC, * AT91PS_AIC; + +/* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */ +#define AT91C_AIC_PRIOR ( ( unsigned int ) 0x7 << 0 ) /* (AIC) Priority Level */ +#define AT91C_AIC_PRIOR_LOWEST ( ( unsigned int ) 0x0 ) /* (AIC) Lowest priority level */ +#define AT91C_AIC_PRIOR_HIGHEST ( ( unsigned int ) 0x7 ) /* (AIC) Highest priority level */ +#define AT91C_AIC_SRCTYPE ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Interrupt Source Type */ +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ( ( unsigned int ) 0x0 << 5 ) /* (AIC) Internal Sources Code Label High-level Sensitive */ +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ( ( unsigned int ) 0x0 << 5 ) /* (AIC) External Sources Code Label Low-level Sensitive */ +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ( ( unsigned int ) 0x1 << 5 ) /* (AIC) Internal Sources Code Label Positive Edge triggered */ +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ( ( unsigned int ) 0x1 << 5 ) /* (AIC) External Sources Code Label Negative Edge triggered */ +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ( ( unsigned int ) 0x2 << 5 ) /* (AIC) Internal Or External Sources Code Label High-level Sensitive */ +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Internal Or External Sources Code Label Positive Edge triggered */ +/* -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- */ +#define AT91C_AIC_NFIQ ( ( unsigned int ) 0x1 << 0 ) /* (AIC) NFIQ Status */ +#define AT91C_AIC_NIRQ ( ( unsigned int ) 0x1 << 1 ) /* (AIC) NIRQ Status */ +/* -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- */ +#define AT91C_AIC_DCR_PROT ( ( unsigned int ) 0x1 << 0 ) /* (AIC) Protection Mode */ +#define AT91C_AIC_DCR_GMSK ( ( unsigned int ) 0x1 << 1 ) /* (AIC) General Mask */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Peripheral DMA Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_PDC +{ + AT91_REG PDC_RPR; /* Receive Pointer Register */ + AT91_REG PDC_RCR; /* Receive Counter Register */ + AT91_REG PDC_TPR; /* Transmit Pointer Register */ + AT91_REG PDC_TCR; /* Transmit Counter Register */ + AT91_REG PDC_RNPR; /* Receive Next Pointer Register */ + AT91_REG PDC_RNCR; /* Receive Next Counter Register */ + AT91_REG PDC_TNPR; /* Transmit Next Pointer Register */ + AT91_REG PDC_TNCR; /* Transmit Next Counter Register */ + AT91_REG PDC_PTCR; /* PDC Transfer Control Register */ + AT91_REG PDC_PTSR; /* PDC Transfer Status Register */ +} AT91S_PDC, * AT91PS_PDC; + +/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */ +#define AT91C_PDC_RXTEN ( ( unsigned int ) 0x1 << 0 ) /* (PDC) Receiver Transfer Enable */ +#define AT91C_PDC_RXTDIS ( ( unsigned int ) 0x1 << 1 ) /* (PDC) Receiver Transfer Disable */ +#define AT91C_PDC_TXTEN ( ( unsigned int ) 0x1 << 8 ) /* (PDC) Transmitter Transfer Enable */ +#define AT91C_PDC_TXTDIS ( ( unsigned int ) 0x1 << 9 ) /* (PDC) Transmitter Transfer Disable */ +/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Debug Unit */ +/* ***************************************************************************** */ +typedef struct _AT91S_DBGU +{ + AT91_REG DBGU_CR; /* Control Register */ + AT91_REG DBGU_MR; /* Mode Register */ + AT91_REG DBGU_IER; /* Interrupt Enable Register */ + AT91_REG DBGU_IDR; /* Interrupt Disable Register */ + AT91_REG DBGU_IMR; /* Interrupt Mask Register */ + AT91_REG DBGU_CSR; /* Channel Status Register */ + AT91_REG DBGU_RHR; /* Receiver Holding Register */ + AT91_REG DBGU_THR; /* Transmitter Holding Register */ + AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */ + AT91_REG Reserved0[ 7 ]; /* */ + AT91_REG DBGU_CIDR; /* Chip ID Register */ + AT91_REG DBGU_EXID; /* Chip ID Extension Register */ + AT91_REG DBGU_FNTR; /* Force NTRST Register */ + AT91_REG Reserved1[ 45 ]; /* */ + AT91_REG DBGU_RPR; /* Receive Pointer Register */ + AT91_REG DBGU_RCR; /* Receive Counter Register */ + AT91_REG DBGU_TPR; /* Transmit Pointer Register */ + AT91_REG DBGU_TCR; /* Transmit Counter Register */ + AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */ + AT91_REG DBGU_RNCR; /* Receive Next Counter Register */ + AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */ + AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */ + AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */ + AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */ +} AT91S_DBGU, * AT91PS_DBGU; + +/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */ +#define AT91C_US_RSTRX ( ( unsigned int ) 0x1 << 2 ) /* (DBGU) Reset Receiver */ +#define AT91C_US_RSTTX ( ( unsigned int ) 0x1 << 3 ) /* (DBGU) Reset Transmitter */ +#define AT91C_US_RXEN ( ( unsigned int ) 0x1 << 4 ) /* (DBGU) Receiver Enable */ +#define AT91C_US_RXDIS ( ( unsigned int ) 0x1 << 5 ) /* (DBGU) Receiver Disable */ +#define AT91C_US_TXEN ( ( unsigned int ) 0x1 << 6 ) /* (DBGU) Transmitter Enable */ +#define AT91C_US_TXDIS ( ( unsigned int ) 0x1 << 7 ) /* (DBGU) Transmitter Disable */ +#define AT91C_US_RSTSTA ( ( unsigned int ) 0x1 << 8 ) /* (DBGU) Reset Status Bits */ +/* -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- */ +#define AT91C_US_PAR ( ( unsigned int ) 0x7 << 9 ) /* (DBGU) Parity type */ +#define AT91C_US_PAR_EVEN ( ( unsigned int ) 0x0 << 9 ) /* (DBGU) Even Parity */ +#define AT91C_US_PAR_ODD ( ( unsigned int ) 0x1 << 9 ) /* (DBGU) Odd Parity */ +#define AT91C_US_PAR_SPACE ( ( unsigned int ) 0x2 << 9 ) /* (DBGU) Parity forced to 0 (Space) */ +#define AT91C_US_PAR_MARK ( ( unsigned int ) 0x3 << 9 ) /* (DBGU) Parity forced to 1 (Mark) */ +#define AT91C_US_PAR_NONE ( ( unsigned int ) 0x4 << 9 ) /* (DBGU) No Parity */ +#define AT91C_US_PAR_MULTI_DROP ( ( unsigned int ) 0x6 << 9 ) /* (DBGU) Multi-drop mode */ +#define AT91C_US_CHMODE ( ( unsigned int ) 0x3 << 14 ) /* (DBGU) Channel Mode */ +#define AT91C_US_CHMODE_NORMAL ( ( unsigned int ) 0x0 << 14 ) /* (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. */ +#define AT91C_US_CHMODE_AUTO ( ( unsigned int ) 0x1 << 14 ) /* (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. */ +#define AT91C_US_CHMODE_LOCAL ( ( unsigned int ) 0x2 << 14 ) /* (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. */ +#define AT91C_US_CHMODE_REMOTE ( ( unsigned int ) 0x3 << 14 ) /* (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. */ +/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ +#define AT91C_US_RXRDY ( ( unsigned int ) 0x1 << 0 ) /* (DBGU) RXRDY Interrupt */ +#define AT91C_US_TXRDY ( ( unsigned int ) 0x1 << 1 ) /* (DBGU) TXRDY Interrupt */ +#define AT91C_US_ENDRX ( ( unsigned int ) 0x1 << 3 ) /* (DBGU) End of Receive Transfer Interrupt */ +#define AT91C_US_ENDTX ( ( unsigned int ) 0x1 << 4 ) /* (DBGU) End of Transmit Interrupt */ +#define AT91C_US_OVRE ( ( unsigned int ) 0x1 << 5 ) /* (DBGU) Overrun Interrupt */ +#define AT91C_US_FRAME ( ( unsigned int ) 0x1 << 6 ) /* (DBGU) Framing Error Interrupt */ +#define AT91C_US_PARE ( ( unsigned int ) 0x1 << 7 ) /* (DBGU) Parity Error Interrupt */ +#define AT91C_US_TXEMPTY ( ( unsigned int ) 0x1 << 9 ) /* (DBGU) TXEMPTY Interrupt */ +#define AT91C_US_TXBUFE ( ( unsigned int ) 0x1 << 11 ) /* (DBGU) TXBUFE Interrupt */ +#define AT91C_US_RXBUFF ( ( unsigned int ) 0x1 << 12 ) /* (DBGU) RXBUFF Interrupt */ +#define AT91C_US_COMM_TX ( ( unsigned int ) 0x1 << 30 ) /* (DBGU) COMM_TX Interrupt */ +#define AT91C_US_COMM_RX ( ( unsigned int ) 0x1 << 31 ) /* (DBGU) COMM_RX Interrupt */ +/* -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- */ +/* -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- */ +/* -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- */ +/* -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- */ +#define AT91C_US_FORCE_NTRST ( ( unsigned int ) 0x1 << 0 ) /* (DBGU) Force NTRST in JTAG */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Parallel Input Output Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_PIO +{ + AT91_REG PIO_PER; /* PIO Enable Register */ + AT91_REG PIO_PDR; /* PIO Disable Register */ + AT91_REG PIO_PSR; /* PIO Status Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG PIO_OER; /* Output Enable Register */ + AT91_REG PIO_ODR; /* Output Disable Registerr */ + AT91_REG PIO_OSR; /* Output Status Register */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG PIO_IFER; /* Input Filter Enable Register */ + AT91_REG PIO_IFDR; /* Input Filter Disable Register */ + AT91_REG PIO_IFSR; /* Input Filter Status Register */ + AT91_REG Reserved2[ 1 ]; /* */ + AT91_REG PIO_SODR; /* Set Output Data Register */ + AT91_REG PIO_CODR; /* Clear Output Data Register */ + AT91_REG PIO_ODSR; /* Output Data Status Register */ + AT91_REG PIO_PDSR; /* Pin Data Status Register */ + AT91_REG PIO_IER; /* Interrupt Enable Register */ + AT91_REG PIO_IDR; /* Interrupt Disable Register */ + AT91_REG PIO_IMR; /* Interrupt Mask Register */ + AT91_REG PIO_ISR; /* Interrupt Status Register */ + AT91_REG PIO_MDER; /* Multi-driver Enable Register */ + AT91_REG PIO_MDDR; /* Multi-driver Disable Register */ + AT91_REG PIO_MDSR; /* Multi-driver Status Register */ + AT91_REG Reserved3[ 1 ]; /* */ + AT91_REG PIO_PPUDR; /* Pull-up Disable Register */ + AT91_REG PIO_PPUER; /* Pull-up Enable Register */ + AT91_REG PIO_PPUSR; /* Pull-up Status Register */ + AT91_REG Reserved4[ 1 ]; /* */ + AT91_REG PIO_ASR; /* Select A Register */ + AT91_REG PIO_BSR; /* Select B Register */ + AT91_REG PIO_ABSR; /* AB Select Status Register */ + AT91_REG Reserved5[ 9 ]; /* */ + AT91_REG PIO_OWER; /* Output Write Enable Register */ + AT91_REG PIO_OWDR; /* Output Write Disable Register */ + AT91_REG PIO_OWSR; /* Output Write Status Register */ +} AT91S_PIO, * AT91PS_PIO; + + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Clock Generator Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_CKGR +{ + AT91_REG CKGR_MOR; /* Main Oscillator Register */ + AT91_REG CKGR_MCFR; /* Main Clock Frequency Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG CKGR_PLLR; /* PLL Register */ +} AT91S_CKGR, * AT91PS_CKGR; + +/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */ +#define AT91C_CKGR_MOSCEN ( ( unsigned int ) 0x1 << 0 ) /* (CKGR) Main Oscillator Enable */ +#define AT91C_CKGR_OSCBYPASS ( ( unsigned int ) 0x1 << 1 ) /* (CKGR) Main Oscillator Bypass */ +#define AT91C_CKGR_OSCOUNT ( ( unsigned int ) 0xFF << 8 ) /* (CKGR) Main Oscillator Start-up Time */ +/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */ +#define AT91C_CKGR_MAINF ( ( unsigned int ) 0xFFFF << 0 ) /* (CKGR) Main Clock Frequency */ +#define AT91C_CKGR_MAINRDY ( ( unsigned int ) 0x1 << 16 ) /* (CKGR) Main Clock Ready */ +/* -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- */ +#define AT91C_CKGR_DIV ( ( unsigned int ) 0xFF << 0 ) /* (CKGR) Divider Selected */ +#define AT91C_CKGR_DIV_0 ( ( unsigned int ) 0x0 ) /* (CKGR) Divider output is 0 */ +#define AT91C_CKGR_DIV_BYPASS ( ( unsigned int ) 0x1 ) /* (CKGR) Divider is bypassed */ +#define AT91C_CKGR_PLLCOUNT ( ( unsigned int ) 0x3F << 8 ) /* (CKGR) PLL Counter */ +#define AT91C_CKGR_OUT ( ( unsigned int ) 0x3 << 14 ) /* (CKGR) PLL Output Frequency Range */ +#define AT91C_CKGR_OUT_0 ( ( unsigned int ) 0x0 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_1 ( ( unsigned int ) 0x1 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_2 ( ( unsigned int ) 0x2 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_3 ( ( unsigned int ) 0x3 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_MUL ( ( unsigned int ) 0x7FF << 16 ) /* (CKGR) PLL Multiplier */ +#define AT91C_CKGR_USBDIV ( ( unsigned int ) 0x3 << 28 ) /* (CKGR) Divider for USB Clocks */ +#define AT91C_CKGR_USBDIV_0 ( ( unsigned int ) 0x0 << 28 ) /* (CKGR) Divider output is PLL clock output */ +#define AT91C_CKGR_USBDIV_1 ( ( unsigned int ) 0x1 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 2 */ +#define AT91C_CKGR_USBDIV_2 ( ( unsigned int ) 0x2 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 4 */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Power Management Controller */ +/* ***************************************************************************** */ +typedef struct _AT91S_PMC +{ + AT91_REG PMC_SCER; /* System Clock Enable Register */ + AT91_REG PMC_SCDR; /* System Clock Disable Register */ + AT91_REG PMC_SCSR; /* System Clock Status Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */ + AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */ + AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG PMC_MOR; /* Main Oscillator Register */ + AT91_REG PMC_MCFR; /* Main Clock Frequency Register */ + AT91_REG Reserved2[ 1 ]; /* */ + AT91_REG PMC_PLLR; /* PLL Register */ + AT91_REG PMC_MCKR; /* Master Clock Register */ + AT91_REG Reserved3[ 3 ]; /* */ + AT91_REG PMC_PCKR[ 4 ]; /* Programmable Clock Register */ + AT91_REG Reserved4[ 4 ]; /* */ + AT91_REG PMC_IER; /* Interrupt Enable Register */ + AT91_REG PMC_IDR; /* Interrupt Disable Register */ + AT91_REG PMC_SR; /* Status Register */ + AT91_REG PMC_IMR; /* Interrupt Mask Register */ +} AT91S_PMC, * AT91PS_PMC; + +/* -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- */ +#define AT91C_PMC_PCK ( ( unsigned int ) 0x1 << 0 ) /* (PMC) Processor Clock */ +#define AT91C_PMC_UDP ( ( unsigned int ) 0x1 << 7 ) /* (PMC) USB Device Port Clock */ +#define AT91C_PMC_PCK0 ( ( unsigned int ) 0x1 << 8 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK1 ( ( unsigned int ) 0x1 << 9 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK2 ( ( unsigned int ) 0x1 << 10 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK3 ( ( unsigned int ) 0x1 << 11 ) /* (PMC) Programmable Clock Output */ +/* -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- */ +/* -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- */ +/* -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- */ +/* -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- */ +/* -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- */ +/* -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */ +#define AT91C_PMC_CSS ( ( unsigned int ) 0x3 << 0 ) /* (PMC) Programmable Clock Selection */ +#define AT91C_PMC_CSS_SLOW_CLK ( ( unsigned int ) 0x0 ) /* (PMC) Slow Clock is selected */ +#define AT91C_PMC_CSS_MAIN_CLK ( ( unsigned int ) 0x1 ) /* (PMC) Main Clock is selected */ +#define AT91C_PMC_CSS_PLL_CLK ( ( unsigned int ) 0x3 ) /* (PMC) Clock from PLL is selected */ +#define AT91C_PMC_PRES ( ( unsigned int ) 0x7 << 2 ) /* (PMC) Programmable Clock Prescaler */ +#define AT91C_PMC_PRES_CLK ( ( unsigned int ) 0x0 << 2 ) /* (PMC) Selected clock */ +#define AT91C_PMC_PRES_CLK_2 ( ( unsigned int ) 0x1 << 2 ) /* (PMC) Selected clock divided by 2 */ +#define AT91C_PMC_PRES_CLK_4 ( ( unsigned int ) 0x2 << 2 ) /* (PMC) Selected clock divided by 4 */ +#define AT91C_PMC_PRES_CLK_8 ( ( unsigned int ) 0x3 << 2 ) /* (PMC) Selected clock divided by 8 */ +#define AT91C_PMC_PRES_CLK_16 ( ( unsigned int ) 0x4 << 2 ) /* (PMC) Selected clock divided by 16 */ +#define AT91C_PMC_PRES_CLK_32 ( ( unsigned int ) 0x5 << 2 ) /* (PMC) Selected clock divided by 32 */ +#define AT91C_PMC_PRES_CLK_64 ( ( unsigned int ) 0x6 << 2 ) /* (PMC) Selected clock divided by 64 */ +/* -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- */ +/* -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- */ +#define AT91C_PMC_MOSCS ( ( unsigned int ) 0x1 << 0 ) /* (PMC) MOSC Status/Enable/Disable/Mask */ +#define AT91C_PMC_LOCK ( ( unsigned int ) 0x1 << 2 ) /* (PMC) PLL Status/Enable/Disable/Mask */ +#define AT91C_PMC_MCKRDY ( ( unsigned int ) 0x1 << 3 ) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK0RDY ( ( unsigned int ) 0x1 << 8 ) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK1RDY ( ( unsigned int ) 0x1 << 9 ) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK2RDY ( ( unsigned int ) 0x1 << 10 ) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK3RDY ( ( unsigned int ) 0x1 << 11 ) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */ +/* -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */ +/* -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- */ +/* -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Reset Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_RSTC +{ + AT91_REG RSTC_RCR; /* Reset Control Register */ + AT91_REG RSTC_RSR; /* Reset Status Register */ + AT91_REG RSTC_RMR; /* Reset Mode Register */ +} AT91S_RSTC, * AT91PS_RSTC; + +/* -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- */ +#define AT91C_RSTC_PROCRST ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) Processor Reset */ +#define AT91C_RSTC_PERRST ( ( unsigned int ) 0x1 << 2 ) /* (RSTC) Peripheral Reset */ +#define AT91C_RSTC_EXTRST ( ( unsigned int ) 0x1 << 3 ) /* (RSTC) External Reset */ +#define AT91C_RSTC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (RSTC) Password */ +/* -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- */ +#define AT91C_RSTC_URSTS ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) User Reset Status */ +#define AT91C_RSTC_BODSTS ( ( unsigned int ) 0x1 << 1 ) /* (RSTC) Brownout Detection Status */ +#define AT91C_RSTC_RSTTYP ( ( unsigned int ) 0x7 << 8 ) /* (RSTC) Reset Type */ +#define AT91C_RSTC_RSTTYP_POWERUP ( ( unsigned int ) 0x0 << 8 ) /* (RSTC) Power-up Reset. VDDCORE rising. */ +#define AT91C_RSTC_RSTTYP_WAKEUP ( ( unsigned int ) 0x1 << 8 ) /* (RSTC) WakeUp Reset. VDDCORE rising. */ +#define AT91C_RSTC_RSTTYP_WATCHDOG ( ( unsigned int ) 0x2 << 8 ) /* (RSTC) Watchdog Reset. Watchdog overflow occurred. */ +#define AT91C_RSTC_RSTTYP_SOFTWARE ( ( unsigned int ) 0x3 << 8 ) /* (RSTC) Software Reset. Processor reset required by the software. */ +#define AT91C_RSTC_RSTTYP_USER ( ( unsigned int ) 0x4 << 8 ) /* (RSTC) User Reset. NRST pin detected low. */ +#define AT91C_RSTC_RSTTYP_BROWNOUT ( ( unsigned int ) 0x5 << 8 ) /* (RSTC) Brownout Reset occurred. */ +#define AT91C_RSTC_NRSTL ( ( unsigned int ) 0x1 << 16 ) /* (RSTC) NRST pin level */ +#define AT91C_RSTC_SRCMP ( ( unsigned int ) 0x1 << 17 ) /* (RSTC) Software Reset Command in Progress. */ +/* -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- */ +#define AT91C_RSTC_URSTEN ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) User Reset Enable */ +#define AT91C_RSTC_URSTIEN ( ( unsigned int ) 0x1 << 4 ) /* (RSTC) User Reset Interrupt Enable */ +#define AT91C_RSTC_ERSTL ( ( unsigned int ) 0xF << 8 ) /* (RSTC) User Reset Enable */ +#define AT91C_RSTC_BODIEN ( ( unsigned int ) 0x1 << 16 ) /* (RSTC) Brownout Detection Interrupt Enable */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_RTTC +{ + AT91_REG RTTC_RTMR; /* Real-time Mode Register */ + AT91_REG RTTC_RTAR; /* Real-time Alarm Register */ + AT91_REG RTTC_RTVR; /* Real-time Value Register */ + AT91_REG RTTC_RTSR; /* Real-time Status Register */ +} AT91S_RTTC, * AT91PS_RTTC; + +/* -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- */ +#define AT91C_RTTC_RTPRES ( ( unsigned int ) 0xFFFF << 0 ) /* (RTTC) Real-time Timer Prescaler Value */ +#define AT91C_RTTC_ALMIEN ( ( unsigned int ) 0x1 << 16 ) /* (RTTC) Alarm Interrupt Enable */ +#define AT91C_RTTC_RTTINCIEN ( ( unsigned int ) 0x1 << 17 ) /* (RTTC) Real Time Timer Increment Interrupt Enable */ +#define AT91C_RTTC_RTTRST ( ( unsigned int ) 0x1 << 18 ) /* (RTTC) Real Time Timer Restart */ +/* -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- */ +#define AT91C_RTTC_ALMV ( ( unsigned int ) 0x0 << 0 ) /* (RTTC) Alarm Value */ +/* -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- */ +#define AT91C_RTTC_CRTV ( ( unsigned int ) 0x0 << 0 ) /* (RTTC) Current Real-time Value */ +/* -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- */ +#define AT91C_RTTC_ALMS ( ( unsigned int ) 0x1 << 0 ) /* (RTTC) Real-time Alarm Status */ +#define AT91C_RTTC_RTTINC ( ( unsigned int ) 0x1 << 1 ) /* (RTTC) Real-time Timer Increment */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_PITC +{ + AT91_REG PITC_PIMR; /* Period Interval Mode Register */ + AT91_REG PITC_PISR; /* Period Interval Status Register */ + AT91_REG PITC_PIVR; /* Period Interval Value Register */ + AT91_REG PITC_PIIR; /* Period Interval Image Register */ +} AT91S_PITC, * AT91PS_PITC; + +/* -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- */ +#define AT91C_PITC_PIV ( ( unsigned int ) 0xFFFFF << 0 ) /* (PITC) Periodic Interval Value */ +#define AT91C_PITC_PITEN ( ( unsigned int ) 0x1 << 24 ) /* (PITC) Periodic Interval Timer Enabled */ +#define AT91C_PITC_PITIEN ( ( unsigned int ) 0x1 << 25 ) /* (PITC) Periodic Interval Timer Interrupt Enable */ +/* -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- */ +#define AT91C_PITC_PITS ( ( unsigned int ) 0x1 << 0 ) /* (PITC) Periodic Interval Timer Status */ +/* -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- */ +#define AT91C_PITC_CPIV ( ( unsigned int ) 0xFFFFF << 0 ) /* (PITC) Current Periodic Interval Value */ +#define AT91C_PITC_PICNT ( ( unsigned int ) 0xFFF << 20 ) /* (PITC) Periodic Interval Counter */ +/* -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_WDTC +{ + AT91_REG WDTC_WDCR; /* Watchdog Control Register */ + AT91_REG WDTC_WDMR; /* Watchdog Mode Register */ + AT91_REG WDTC_WDSR; /* Watchdog Status Register */ +} AT91S_WDTC, * AT91PS_WDTC; + +/* -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- */ +#define AT91C_WDTC_WDRSTT ( ( unsigned int ) 0x1 << 0 ) /* (WDTC) Watchdog Restart */ +#define AT91C_WDTC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (WDTC) Watchdog KEY Password */ +/* -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */ +#define AT91C_WDTC_WDV ( ( unsigned int ) 0xFFF << 0 ) /* (WDTC) Watchdog Timer Restart */ +#define AT91C_WDTC_WDFIEN ( ( unsigned int ) 0x1 << 12 ) /* (WDTC) Watchdog Fault Interrupt Enable */ +#define AT91C_WDTC_WDRSTEN ( ( unsigned int ) 0x1 << 13 ) /* (WDTC) Watchdog Reset Enable */ +#define AT91C_WDTC_WDRPROC ( ( unsigned int ) 0x1 << 14 ) /* (WDTC) Watchdog Timer Restart */ +#define AT91C_WDTC_WDDIS ( ( unsigned int ) 0x1 << 15 ) /* (WDTC) Watchdog Disable */ +#define AT91C_WDTC_WDD ( ( unsigned int ) 0xFFF << 16 ) /* (WDTC) Watchdog Delta Value */ +#define AT91C_WDTC_WDDBGHLT ( ( unsigned int ) 0x1 << 28 ) /* (WDTC) Watchdog Debug Halt */ +#define AT91C_WDTC_WDIDLEHLT ( ( unsigned int ) 0x1 << 29 ) /* (WDTC) Watchdog Idle Halt */ +/* -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- */ +#define AT91C_WDTC_WDUNF ( ( unsigned int ) 0x1 << 0 ) /* (WDTC) Watchdog Underflow */ +#define AT91C_WDTC_WDERR ( ( unsigned int ) 0x1 << 1 ) /* (WDTC) Watchdog Error */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_VREG +{ + AT91_REG VREG_MR; /* Voltage Regulator Mode Register */ +} AT91S_VREG, * AT91PS_VREG; + +/* -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- */ +#define AT91C_VREG_PSTDBY ( ( unsigned int ) 0x1 << 0 ) /* (VREG) Voltage Regulator Power Standby Mode */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Memory Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_MC +{ + AT91_REG MC_RCR; /* MC Remap Control Register */ + AT91_REG MC_ASR; /* MC Abort Status Register */ + AT91_REG MC_AASR; /* MC Abort Address Status Register */ + AT91_REG Reserved0[ 21 ]; /* */ + AT91_REG MC_FMR; /* MC Flash Mode Register */ + AT91_REG MC_FCR; /* MC Flash Command Register */ + AT91_REG MC_FSR; /* MC Flash Status Register */ +} AT91S_MC, * AT91PS_MC; + +/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */ +#define AT91C_MC_RCB ( ( unsigned int ) 0x1 << 0 ) /* (MC) Remap Command Bit */ +/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */ +#define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Address Abort Status */ +#define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Address Abort Status */ +#define AT91C_MC_ABTSZ ( ( unsigned int ) 0x3 << 8 ) /* (MC) Abort Size Status */ +#define AT91C_MC_ABTSZ_BYTE ( ( unsigned int ) 0x0 << 8 ) /* (MC) Byte */ +#define AT91C_MC_ABTSZ_HWORD ( ( unsigned int ) 0x1 << 8 ) /* (MC) Half-word */ +#define AT91C_MC_ABTSZ_WORD ( ( unsigned int ) 0x2 << 8 ) /* (MC) Word */ +#define AT91C_MC_ABTTYP ( ( unsigned int ) 0x3 << 10 ) /* (MC) Abort Type Status */ +#define AT91C_MC_ABTTYP_DATAR ( ( unsigned int ) 0x0 << 10 ) /* (MC) Data Read */ +#define AT91C_MC_ABTTYP_DATAW ( ( unsigned int ) 0x1 << 10 ) /* (MC) Data Write */ +#define AT91C_MC_ABTTYP_FETCH ( ( unsigned int ) 0x2 << 10 ) /* (MC) Code Fetch */ +#define AT91C_MC_MST0 ( ( unsigned int ) 0x1 << 16 ) /* (MC) Master 0 Abort Source */ +#define AT91C_MC_MST1 ( ( unsigned int ) 0x1 << 17 ) /* (MC) Master 1 Abort Source */ +#define AT91C_MC_SVMST0 ( ( unsigned int ) 0x1 << 24 ) /* (MC) Saved Master 0 Abort Source */ +#define AT91C_MC_SVMST1 ( ( unsigned int ) 0x1 << 25 ) /* (MC) Saved Master 1 Abort Source */ +/* -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- */ +#define AT91C_MC_FRDY ( ( unsigned int ) 0x1 << 0 ) /* (MC) Flash Ready */ +#define AT91C_MC_LOCKE ( ( unsigned int ) 0x1 << 2 ) /* (MC) Lock Error */ +#define AT91C_MC_PROGE ( ( unsigned int ) 0x1 << 3 ) /* (MC) Programming Error */ +#define AT91C_MC_NEBP ( ( unsigned int ) 0x1 << 7 ) /* (MC) No Erase Before Programming */ +#define AT91C_MC_FWS ( ( unsigned int ) 0x3 << 8 ) /* (MC) Flash Wait State */ +#define AT91C_MC_FWS_0FWS ( ( unsigned int ) 0x0 << 8 ) /* (MC) 1 cycle for Read, 2 for Write operations */ +#define AT91C_MC_FWS_1FWS ( ( unsigned int ) 0x1 << 8 ) /* (MC) 2 cycles for Read, 3 for Write operations */ +#define AT91C_MC_FWS_2FWS ( ( unsigned int ) 0x2 << 8 ) /* (MC) 3 cycles for Read, 4 for Write operations */ +#define AT91C_MC_FWS_3FWS ( ( unsigned int ) 0x3 << 8 ) /* (MC) 4 cycles for Read, 4 for Write operations */ +#define AT91C_MC_FMCN ( ( unsigned int ) 0xFF << 16 ) /* (MC) Flash Microsecond Cycle Number */ +/* -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- */ +#define AT91C_MC_FCMD ( ( unsigned int ) 0xF << 0 ) /* (MC) Flash Command */ +#define AT91C_MC_FCMD_START_PROG ( ( unsigned int ) 0x1 ) /* (MC) Starts the programming of th epage specified by PAGEN. */ +#define AT91C_MC_FCMD_LOCK ( ( unsigned int ) 0x2 ) /* (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */ +#define AT91C_MC_FCMD_PROG_AND_LOCK ( ( unsigned int ) 0x3 ) /* (MC) The lock sequence automatically happens after the programming sequence is completed. */ +#define AT91C_MC_FCMD_UNLOCK ( ( unsigned int ) 0x4 ) /* (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */ +#define AT91C_MC_FCMD_ERASE_ALL ( ( unsigned int ) 0x8 ) /* (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. */ +#define AT91C_MC_FCMD_SET_GP_NVM ( ( unsigned int ) 0xB ) /* (MC) Set General Purpose NVM bits. */ +#define AT91C_MC_FCMD_CLR_GP_NVM ( ( unsigned int ) 0xD ) /* (MC) Clear General Purpose NVM bits. */ +#define AT91C_MC_FCMD_SET_SECURITY ( ( unsigned int ) 0xF ) /* (MC) Set Security Bit. */ +#define AT91C_MC_PAGEN ( ( unsigned int ) 0x3FF << 8 ) /* (MC) Page Number */ +#define AT91C_MC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (MC) Writing Protect Key */ +/* -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- */ +#define AT91C_MC_SECURITY ( ( unsigned int ) 0x1 << 4 ) /* (MC) Security Bit Status */ +#define AT91C_MC_GPNVM0 ( ( unsigned int ) 0x1 << 8 ) /* (MC) Sector 0 Lock Status */ +#define AT91C_MC_GPNVM1 ( ( unsigned int ) 0x1 << 9 ) /* (MC) Sector 1 Lock Status */ +#define AT91C_MC_GPNVM2 ( ( unsigned int ) 0x1 << 10 ) /* (MC) Sector 2 Lock Status */ +#define AT91C_MC_GPNVM3 ( ( unsigned int ) 0x1 << 11 ) /* (MC) Sector 3 Lock Status */ +#define AT91C_MC_GPNVM4 ( ( unsigned int ) 0x1 << 12 ) /* (MC) Sector 4 Lock Status */ +#define AT91C_MC_GPNVM5 ( ( unsigned int ) 0x1 << 13 ) /* (MC) Sector 5 Lock Status */ +#define AT91C_MC_GPNVM6 ( ( unsigned int ) 0x1 << 14 ) /* (MC) Sector 6 Lock Status */ +#define AT91C_MC_GPNVM7 ( ( unsigned int ) 0x1 << 15 ) /* (MC) Sector 7 Lock Status */ +#define AT91C_MC_LOCKS0 ( ( unsigned int ) 0x1 << 16 ) /* (MC) Sector 0 Lock Status */ +#define AT91C_MC_LOCKS1 ( ( unsigned int ) 0x1 << 17 ) /* (MC) Sector 1 Lock Status */ +#define AT91C_MC_LOCKS2 ( ( unsigned int ) 0x1 << 18 ) /* (MC) Sector 2 Lock Status */ +#define AT91C_MC_LOCKS3 ( ( unsigned int ) 0x1 << 19 ) /* (MC) Sector 3 Lock Status */ +#define AT91C_MC_LOCKS4 ( ( unsigned int ) 0x1 << 20 ) /* (MC) Sector 4 Lock Status */ +#define AT91C_MC_LOCKS5 ( ( unsigned int ) 0x1 << 21 ) /* (MC) Sector 5 Lock Status */ +#define AT91C_MC_LOCKS6 ( ( unsigned int ) 0x1 << 22 ) /* (MC) Sector 6 Lock Status */ +#define AT91C_MC_LOCKS7 ( ( unsigned int ) 0x1 << 23 ) /* (MC) Sector 7 Lock Status */ +#define AT91C_MC_LOCKS8 ( ( unsigned int ) 0x1 << 24 ) /* (MC) Sector 8 Lock Status */ +#define AT91C_MC_LOCKS9 ( ( unsigned int ) 0x1 << 25 ) /* (MC) Sector 9 Lock Status */ +#define AT91C_MC_LOCKS10 ( ( unsigned int ) 0x1 << 26 ) /* (MC) Sector 10 Lock Status */ +#define AT91C_MC_LOCKS11 ( ( unsigned int ) 0x1 << 27 ) /* (MC) Sector 11 Lock Status */ +#define AT91C_MC_LOCKS12 ( ( unsigned int ) 0x1 << 28 ) /* (MC) Sector 12 Lock Status */ +#define AT91C_MC_LOCKS13 ( ( unsigned int ) 0x1 << 29 ) /* (MC) Sector 13 Lock Status */ +#define AT91C_MC_LOCKS14 ( ( unsigned int ) 0x1 << 30 ) /* (MC) Sector 14 Lock Status */ +#define AT91C_MC_LOCKS15 ( ( unsigned int ) 0x1 << 31 ) /* (MC) Sector 15 Lock Status */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_SPI +{ + AT91_REG SPI_CR; /* Control Register */ + AT91_REG SPI_MR; /* Mode Register */ + AT91_REG SPI_RDR; /* Receive Data Register */ + AT91_REG SPI_TDR; /* Transmit Data Register */ + AT91_REG SPI_SR; /* Status Register */ + AT91_REG SPI_IER; /* Interrupt Enable Register */ + AT91_REG SPI_IDR; /* Interrupt Disable Register */ + AT91_REG SPI_IMR; /* Interrupt Mask Register */ + AT91_REG Reserved0[ 4 ]; /* */ + AT91_REG SPI_CSR[ 4 ]; /* Chip Select Register */ + AT91_REG Reserved1[ 48 ]; /* */ + AT91_REG SPI_RPR; /* Receive Pointer Register */ + AT91_REG SPI_RCR; /* Receive Counter Register */ + AT91_REG SPI_TPR; /* Transmit Pointer Register */ + AT91_REG SPI_TCR; /* Transmit Counter Register */ + AT91_REG SPI_RNPR; /* Receive Next Pointer Register */ + AT91_REG SPI_RNCR; /* Receive Next Counter Register */ + AT91_REG SPI_TNPR; /* Transmit Next Pointer Register */ + AT91_REG SPI_TNCR; /* Transmit Next Counter Register */ + AT91_REG SPI_PTCR; /* PDC Transfer Control Register */ + AT91_REG SPI_PTSR; /* PDC Transfer Status Register */ +} AT91S_SPI, * AT91PS_SPI; + +/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */ +#define AT91C_SPI_SPIEN ( ( unsigned int ) 0x1 << 0 ) /* (SPI) SPI Enable */ +#define AT91C_SPI_SPIDIS ( ( unsigned int ) 0x1 << 1 ) /* (SPI) SPI Disable */ +#define AT91C_SPI_SWRST ( ( unsigned int ) 0x1 << 7 ) /* (SPI) SPI Software reset */ +#define AT91C_SPI_LASTXFER ( ( unsigned int ) 0x1 << 24 ) /* (SPI) SPI Last Transfer */ +/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */ +#define AT91C_SPI_MSTR ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Master/Slave Mode */ +#define AT91C_SPI_PS ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Peripheral Select */ +#define AT91C_SPI_PS_FIXED ( ( unsigned int ) 0x0 << 1 ) /* (SPI) Fixed Peripheral Select */ +#define AT91C_SPI_PS_VARIABLE ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Variable Peripheral Select */ +#define AT91C_SPI_PCSDEC ( ( unsigned int ) 0x1 << 2 ) /* (SPI) Chip Select Decode */ +#define AT91C_SPI_FDIV ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Clock Selection */ +#define AT91C_SPI_MODFDIS ( ( unsigned int ) 0x1 << 4 ) /* (SPI) Mode Fault Detection */ +#define AT91C_SPI_LLB ( ( unsigned int ) 0x1 << 7 ) /* (SPI) Clock Selection */ +#define AT91C_SPI_PCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select */ +#define AT91C_SPI_DLYBCS ( ( unsigned int ) 0xFF << 24 ) /* (SPI) Delay Between Chip Selects */ +/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */ +#define AT91C_SPI_RD ( ( unsigned int ) 0xFFFF << 0 ) /* (SPI) Receive Data */ +#define AT91C_SPI_RPCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */ +/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */ +#define AT91C_SPI_TD ( ( unsigned int ) 0xFFFF << 0 ) /* (SPI) Transmit Data */ +#define AT91C_SPI_TPCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */ +/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ +#define AT91C_SPI_RDRF ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Receive Data Register Full */ +#define AT91C_SPI_TDRE ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Transmit Data Register Empty */ +#define AT91C_SPI_MODF ( ( unsigned int ) 0x1 << 2 ) /* (SPI) Mode Fault Error */ +#define AT91C_SPI_OVRES ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Overrun Error Status */ +#define AT91C_SPI_ENDRX ( ( unsigned int ) 0x1 << 4 ) /* (SPI) End of Receiver Transfer */ +#define AT91C_SPI_ENDTX ( ( unsigned int ) 0x1 << 5 ) /* (SPI) End of Receiver Transfer */ +#define AT91C_SPI_RXBUFF ( ( unsigned int ) 0x1 << 6 ) /* (SPI) RXBUFF Interrupt */ +#define AT91C_SPI_TXBUFE ( ( unsigned int ) 0x1 << 7 ) /* (SPI) TXBUFE Interrupt */ +#define AT91C_SPI_NSSR ( ( unsigned int ) 0x1 << 8 ) /* (SPI) NSSR Interrupt */ +#define AT91C_SPI_TXEMPTY ( ( unsigned int ) 0x1 << 9 ) /* (SPI) TXEMPTY Interrupt */ +#define AT91C_SPI_SPIENS ( ( unsigned int ) 0x1 << 16 ) /* (SPI) Enable Status */ +/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ +/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ +/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */ +/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */ +#define AT91C_SPI_CPOL ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Clock Polarity */ +#define AT91C_SPI_NCPHA ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Clock Phase */ +#define AT91C_SPI_CSAAT ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Chip Select Active After Transfer */ +#define AT91C_SPI_BITS ( ( unsigned int ) 0xF << 4 ) /* (SPI) Bits Per Transfer */ +#define AT91C_SPI_BITS_8 ( ( unsigned int ) 0x0 << 4 ) /* (SPI) 8 Bits Per transfer */ +#define AT91C_SPI_BITS_9 ( ( unsigned int ) 0x1 << 4 ) /* (SPI) 9 Bits Per transfer */ +#define AT91C_SPI_BITS_10 ( ( unsigned int ) 0x2 << 4 ) /* (SPI) 10 Bits Per transfer */ +#define AT91C_SPI_BITS_11 ( ( unsigned int ) 0x3 << 4 ) /* (SPI) 11 Bits Per transfer */ +#define AT91C_SPI_BITS_12 ( ( unsigned int ) 0x4 << 4 ) /* (SPI) 12 Bits Per transfer */ +#define AT91C_SPI_BITS_13 ( ( unsigned int ) 0x5 << 4 ) /* (SPI) 13 Bits Per transfer */ +#define AT91C_SPI_BITS_14 ( ( unsigned int ) 0x6 << 4 ) /* (SPI) 14 Bits Per transfer */ +#define AT91C_SPI_BITS_15 ( ( unsigned int ) 0x7 << 4 ) /* (SPI) 15 Bits Per transfer */ +#define AT91C_SPI_BITS_16 ( ( unsigned int ) 0x8 << 4 ) /* (SPI) 16 Bits Per transfer */ +#define AT91C_SPI_SCBR ( ( unsigned int ) 0xFF << 8 ) /* (SPI) Serial Clock Baud Rate */ +#define AT91C_SPI_DLYBS ( ( unsigned int ) 0xFF << 16 ) /* (SPI) Delay Before SPCK */ +#define AT91C_SPI_DLYBCT ( ( unsigned int ) 0xFF << 24 ) /* (SPI) Delay Between Consecutive Transfers */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Usart */ +/* ***************************************************************************** */ +typedef struct _AT91S_USART +{ + AT91_REG US_CR; /* Control Register */ + AT91_REG US_MR; /* Mode Register */ + AT91_REG US_IER; /* Interrupt Enable Register */ + AT91_REG US_IDR; /* Interrupt Disable Register */ + AT91_REG US_IMR; /* Interrupt Mask Register */ + AT91_REG US_CSR; /* Channel Status Register */ + AT91_REG US_RHR; /* Receiver Holding Register */ + AT91_REG US_THR; /* Transmitter Holding Register */ + AT91_REG US_BRGR; /* Baud Rate Generator Register */ + AT91_REG US_RTOR; /* Receiver Time-out Register */ + AT91_REG US_TTGR; /* Transmitter Time-guard Register */ + AT91_REG Reserved0[ 5 ]; /* */ + AT91_REG US_FIDI; /* FI_DI_Ratio Register */ + AT91_REG US_NER; /* Nb Errors Register */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG US_IF; /* IRDA_FILTER Register */ + AT91_REG Reserved2[ 44 ]; /* */ + AT91_REG US_RPR; /* Receive Pointer Register */ + AT91_REG US_RCR; /* Receive Counter Register */ + AT91_REG US_TPR; /* Transmit Pointer Register */ + AT91_REG US_TCR; /* Transmit Counter Register */ + AT91_REG US_RNPR; /* Receive Next Pointer Register */ + AT91_REG US_RNCR; /* Receive Next Counter Register */ + AT91_REG US_TNPR; /* Transmit Next Pointer Register */ + AT91_REG US_TNCR; /* Transmit Next Counter Register */ + AT91_REG US_PTCR; /* PDC Transfer Control Register */ + AT91_REG US_PTSR; /* PDC Transfer Status Register */ +} AT91S_USART, * AT91PS_USART; + +/* -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- */ +#define AT91C_US_STTBRK ( ( unsigned int ) 0x1 << 9 ) /* (USART) Start Break */ +#define AT91C_US_STPBRK ( ( unsigned int ) 0x1 << 10 ) /* (USART) Stop Break */ +#define AT91C_US_STTTO ( ( unsigned int ) 0x1 << 11 ) /* (USART) Start Time-out */ +#define AT91C_US_SENDA ( ( unsigned int ) 0x1 << 12 ) /* (USART) Send Address */ +#define AT91C_US_RSTIT ( ( unsigned int ) 0x1 << 13 ) /* (USART) Reset Iterations */ +#define AT91C_US_RSTNACK ( ( unsigned int ) 0x1 << 14 ) /* (USART) Reset Non Acknowledge */ +#define AT91C_US_RETTO ( ( unsigned int ) 0x1 << 15 ) /* (USART) Rearm Time-out */ +#define AT91C_US_DTREN ( ( unsigned int ) 0x1 << 16 ) /* (USART) Data Terminal ready Enable */ +#define AT91C_US_DTRDIS ( ( unsigned int ) 0x1 << 17 ) /* (USART) Data Terminal ready Disable */ +#define AT91C_US_RTSEN ( ( unsigned int ) 0x1 << 18 ) /* (USART) Request to Send enable */ +#define AT91C_US_RTSDIS ( ( unsigned int ) 0x1 << 19 ) /* (USART) Request to Send Disable */ +/* -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- */ +#define AT91C_US_USMODE ( ( unsigned int ) 0xF << 0 ) /* (USART) Usart mode */ +#define AT91C_US_USMODE_NORMAL ( ( unsigned int ) 0x0 ) /* (USART) Normal */ +#define AT91C_US_USMODE_RS485 ( ( unsigned int ) 0x1 ) /* (USART) RS485 */ +#define AT91C_US_USMODE_HWHSH ( ( unsigned int ) 0x2 ) /* (USART) Hardware Handshaking */ +#define AT91C_US_USMODE_MODEM ( ( unsigned int ) 0x3 ) /* (USART) Modem */ +#define AT91C_US_USMODE_ISO7816_0 ( ( unsigned int ) 0x4 ) /* (USART) ISO7816 protocol: T = 0 */ +#define AT91C_US_USMODE_ISO7816_1 ( ( unsigned int ) 0x6 ) /* (USART) ISO7816 protocol: T = 1 */ +#define AT91C_US_USMODE_IRDA ( ( unsigned int ) 0x8 ) /* (USART) IrDA */ +#define AT91C_US_USMODE_SWHSH ( ( unsigned int ) 0xC ) /* (USART) Software Handshaking */ +#define AT91C_US_CLKS ( ( unsigned int ) 0x3 << 4 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */ +#define AT91C_US_CLKS_CLOCK ( ( unsigned int ) 0x0 << 4 ) /* (USART) Clock */ +#define AT91C_US_CLKS_FDIV1 ( ( unsigned int ) 0x1 << 4 ) /* (USART) fdiv1 */ +#define AT91C_US_CLKS_SLOW ( ( unsigned int ) 0x2 << 4 ) /* (USART) slow_clock (ARM) */ +#define AT91C_US_CLKS_EXT ( ( unsigned int ) 0x3 << 4 ) /* (USART) External (SCK) */ +#define AT91C_US_CHRL ( ( unsigned int ) 0x3 << 6 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */ +#define AT91C_US_CHRL_5_BITS ( ( unsigned int ) 0x0 << 6 ) /* (USART) Character Length: 5 bits */ +#define AT91C_US_CHRL_6_BITS ( ( unsigned int ) 0x1 << 6 ) /* (USART) Character Length: 6 bits */ +#define AT91C_US_CHRL_7_BITS ( ( unsigned int ) 0x2 << 6 ) /* (USART) Character Length: 7 bits */ +#define AT91C_US_CHRL_8_BITS ( ( unsigned int ) 0x3 << 6 ) /* (USART) Character Length: 8 bits */ +#define AT91C_US_SYNC ( ( unsigned int ) 0x1 << 8 ) /* (USART) Synchronous Mode Select */ +#define AT91C_US_NBSTOP ( ( unsigned int ) 0x3 << 12 ) /* (USART) Number of Stop bits */ +#define AT91C_US_NBSTOP_1_BIT ( ( unsigned int ) 0x0 << 12 ) /* (USART) 1 stop bit */ +#define AT91C_US_NBSTOP_15_BIT ( ( unsigned int ) 0x1 << 12 ) /* (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */ +#define AT91C_US_NBSTOP_2_BIT ( ( unsigned int ) 0x2 << 12 ) /* (USART) 2 stop bits */ +#define AT91C_US_MSBF ( ( unsigned int ) 0x1 << 16 ) /* (USART) Bit Order */ +#define AT91C_US_MODE9 ( ( unsigned int ) 0x1 << 17 ) /* (USART) 9-bit Character length */ +#define AT91C_US_CKLO ( ( unsigned int ) 0x1 << 18 ) /* (USART) Clock Output Select */ +#define AT91C_US_OVER ( ( unsigned int ) 0x1 << 19 ) /* (USART) Over Sampling Mode */ +#define AT91C_US_INACK ( ( unsigned int ) 0x1 << 20 ) /* (USART) Inhibit Non Acknowledge */ +#define AT91C_US_DSNACK ( ( unsigned int ) 0x1 << 21 ) /* (USART) Disable Successive NACK */ +#define AT91C_US_MAX_ITER ( ( unsigned int ) 0x1 << 24 ) /* (USART) Number of Repetitions */ +#define AT91C_US_FILTER ( ( unsigned int ) 0x1 << 28 ) /* (USART) Receive Line Filter */ +/* -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ +#define AT91C_US_RXBRK ( ( unsigned int ) 0x1 << 2 ) /* (USART) Break Received/End of Break */ +#define AT91C_US_TIMEOUT ( ( unsigned int ) 0x1 << 8 ) /* (USART) Receiver Time-out */ +#define AT91C_US_ITERATION ( ( unsigned int ) 0x1 << 10 ) /* (USART) Max number of Repetitions Reached */ +#define AT91C_US_NACK ( ( unsigned int ) 0x1 << 13 ) /* (USART) Non Acknowledge */ +#define AT91C_US_RIIC ( ( unsigned int ) 0x1 << 16 ) /* (USART) Ring INdicator Input Change Flag */ +#define AT91C_US_DSRIC ( ( unsigned int ) 0x1 << 17 ) /* (USART) Data Set Ready Input Change Flag */ +#define AT91C_US_DCDIC ( ( unsigned int ) 0x1 << 18 ) /* (USART) Data Carrier Flag */ +#define AT91C_US_CTSIC ( ( unsigned int ) 0x1 << 19 ) /* (USART) Clear To Send Input Change Flag */ +/* -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- */ +/* -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- */ +/* -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- */ +#define AT91C_US_RI ( ( unsigned int ) 0x1 << 20 ) /* (USART) Image of RI Input */ +#define AT91C_US_DSR ( ( unsigned int ) 0x1 << 21 ) /* (USART) Image of DSR Input */ +#define AT91C_US_DCD ( ( unsigned int ) 0x1 << 22 ) /* (USART) Image of DCD Input */ +#define AT91C_US_CTS ( ( unsigned int ) 0x1 << 23 ) /* (USART) Image of CTS Input */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_SSC +{ + AT91_REG SSC_CR; /* Control Register */ + AT91_REG SSC_CMR; /* Clock Mode Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG SSC_RCMR; /* Receive Clock ModeRegister */ + AT91_REG SSC_RFMR; /* Receive Frame Mode Register */ + AT91_REG SSC_TCMR; /* Transmit Clock Mode Register */ + AT91_REG SSC_TFMR; /* Transmit Frame Mode Register */ + AT91_REG SSC_RHR; /* Receive Holding Register */ + AT91_REG SSC_THR; /* Transmit Holding Register */ + AT91_REG Reserved1[ 2 ]; /* */ + AT91_REG SSC_RSHR; /* Receive Sync Holding Register */ + AT91_REG SSC_TSHR; /* Transmit Sync Holding Register */ + AT91_REG Reserved2[ 2 ]; /* */ + AT91_REG SSC_SR; /* Status Register */ + AT91_REG SSC_IER; /* Interrupt Enable Register */ + AT91_REG SSC_IDR; /* Interrupt Disable Register */ + AT91_REG SSC_IMR; /* Interrupt Mask Register */ + AT91_REG Reserved3[ 44 ]; /* */ + AT91_REG SSC_RPR; /* Receive Pointer Register */ + AT91_REG SSC_RCR; /* Receive Counter Register */ + AT91_REG SSC_TPR; /* Transmit Pointer Register */ + AT91_REG SSC_TCR; /* Transmit Counter Register */ + AT91_REG SSC_RNPR; /* Receive Next Pointer Register */ + AT91_REG SSC_RNCR; /* Receive Next Counter Register */ + AT91_REG SSC_TNPR; /* Transmit Next Pointer Register */ + AT91_REG SSC_TNCR; /* Transmit Next Counter Register */ + AT91_REG SSC_PTCR; /* PDC Transfer Control Register */ + AT91_REG SSC_PTSR; /* PDC Transfer Status Register */ +} AT91S_SSC, * AT91PS_SSC; + +/* -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- */ +#define AT91C_SSC_RXEN ( ( unsigned int ) 0x1 << 0 ) /* (SSC) Receive Enable */ +#define AT91C_SSC_RXDIS ( ( unsigned int ) 0x1 << 1 ) /* (SSC) Receive Disable */ +#define AT91C_SSC_TXEN ( ( unsigned int ) 0x1 << 8 ) /* (SSC) Transmit Enable */ +#define AT91C_SSC_TXDIS ( ( unsigned int ) 0x1 << 9 ) /* (SSC) Transmit Disable */ +#define AT91C_SSC_SWRST ( ( unsigned int ) 0x1 << 15 ) /* (SSC) Software Reset */ +/* -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- */ +#define AT91C_SSC_CKS ( ( unsigned int ) 0x3 << 0 ) /* (SSC) Receive/Transmit Clock Selection */ +#define AT91C_SSC_CKS_DIV ( ( unsigned int ) 0x0 ) /* (SSC) Divided Clock */ +#define AT91C_SSC_CKS_TK ( ( unsigned int ) 0x1 ) /* (SSC) TK Clock signal */ +#define AT91C_SSC_CKS_RK ( ( unsigned int ) 0x2 ) /* (SSC) RK pin */ +#define AT91C_SSC_CKO ( ( unsigned int ) 0x7 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode Selection */ +#define AT91C_SSC_CKO_NONE ( ( unsigned int ) 0x0 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only */ +#define AT91C_SSC_CKO_CONTINUOUS ( ( unsigned int ) 0x1 << 2 ) /* (SSC) Continuous Receive/Transmit Clock RK pin: Output */ +#define AT91C_SSC_CKO_DATA_TX ( ( unsigned int ) 0x2 << 2 ) /* (SSC) Receive/Transmit Clock only during data transfers RK pin: Output */ +#define AT91C_SSC_CKI ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Receive/Transmit Clock Inversion */ +#define AT91C_SSC_START ( ( unsigned int ) 0xF << 8 ) /* (SSC) Receive/Transmit Start Selection */ +#define AT91C_SSC_START_CONTINUOUS ( ( unsigned int ) 0x0 << 8 ) /* (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */ +#define AT91C_SSC_START_TX ( ( unsigned int ) 0x1 << 8 ) /* (SSC) Transmit/Receive start */ +#define AT91C_SSC_START_LOW_RF ( ( unsigned int ) 0x2 << 8 ) /* (SSC) Detection of a low level on RF input */ +#define AT91C_SSC_START_HIGH_RF ( ( unsigned int ) 0x3 << 8 ) /* (SSC) Detection of a high level on RF input */ +#define AT91C_SSC_START_FALL_RF ( ( unsigned int ) 0x4 << 8 ) /* (SSC) Detection of a falling edge on RF input */ +#define AT91C_SSC_START_RISE_RF ( ( unsigned int ) 0x5 << 8 ) /* (SSC) Detection of a rising edge on RF input */ +#define AT91C_SSC_START_LEVEL_RF ( ( unsigned int ) 0x6 << 8 ) /* (SSC) Detection of any level change on RF input */ +#define AT91C_SSC_START_EDGE_RF ( ( unsigned int ) 0x7 << 8 ) /* (SSC) Detection of any edge on RF input */ +#define AT91C_SSC_START_0 ( ( unsigned int ) 0x8 << 8 ) /* (SSC) Compare 0 */ +#define AT91C_SSC_STTDLY ( ( unsigned int ) 0xFF << 16 ) /* (SSC) Receive/Transmit Start Delay */ +#define AT91C_SSC_PERIOD ( ( unsigned int ) 0xFF << 24 ) /* (SSC) Receive/Transmit Period Divider Selection */ +/* -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- */ +#define AT91C_SSC_DATLEN ( ( unsigned int ) 0x1F << 0 ) /* (SSC) Data Length */ +#define AT91C_SSC_LOOP ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Loop Mode */ +#define AT91C_SSC_MSBF ( ( unsigned int ) 0x1 << 7 ) /* (SSC) Most Significant Bit First */ +#define AT91C_SSC_DATNB ( ( unsigned int ) 0xF << 8 ) /* (SSC) Data Number per Frame */ +#define AT91C_SSC_FSLEN ( ( unsigned int ) 0xF << 16 ) /* (SSC) Receive/Transmit Frame Sync length */ +#define AT91C_SSC_FSOS ( ( unsigned int ) 0x7 << 20 ) /* (SSC) Receive/Transmit Frame Sync Output Selection */ +#define AT91C_SSC_FSOS_NONE ( ( unsigned int ) 0x0 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only */ +#define AT91C_SSC_FSOS_NEGATIVE ( ( unsigned int ) 0x1 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse */ +#define AT91C_SSC_FSOS_POSITIVE ( ( unsigned int ) 0x2 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse */ +#define AT91C_SSC_FSOS_LOW ( ( unsigned int ) 0x3 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer */ +#define AT91C_SSC_FSOS_HIGH ( ( unsigned int ) 0x4 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer */ +#define AT91C_SSC_FSOS_TOGGLE ( ( unsigned int ) 0x5 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer */ +#define AT91C_SSC_FSEDGE ( ( unsigned int ) 0x1 << 24 ) /* (SSC) Frame Sync Edge Detection */ +/* -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- */ +/* -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- */ +#define AT91C_SSC_DATDEF ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Data Default Value */ +#define AT91C_SSC_FSDEN ( ( unsigned int ) 0x1 << 23 ) /* (SSC) Frame Sync Data Enable */ +/* -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- */ +#define AT91C_SSC_TXRDY ( ( unsigned int ) 0x1 << 0 ) /* (SSC) Transmit Ready */ +#define AT91C_SSC_TXEMPTY ( ( unsigned int ) 0x1 << 1 ) /* (SSC) Transmit Empty */ +#define AT91C_SSC_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (SSC) End Of Transmission */ +#define AT91C_SSC_TXBUFE ( ( unsigned int ) 0x1 << 3 ) /* (SSC) Transmit Buffer Empty */ +#define AT91C_SSC_RXRDY ( ( unsigned int ) 0x1 << 4 ) /* (SSC) Receive Ready */ +#define AT91C_SSC_OVRUN ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Receive Overrun */ +#define AT91C_SSC_ENDRX ( ( unsigned int ) 0x1 << 6 ) /* (SSC) End of Reception */ +#define AT91C_SSC_RXBUFF ( ( unsigned int ) 0x1 << 7 ) /* (SSC) Receive Buffer Full */ +#define AT91C_SSC_TXSYN ( ( unsigned int ) 0x1 << 10 ) /* (SSC) Transmit Sync */ +#define AT91C_SSC_RXSYN ( ( unsigned int ) 0x1 << 11 ) /* (SSC) Receive Sync */ +#define AT91C_SSC_TXENA ( ( unsigned int ) 0x1 << 16 ) /* (SSC) Transmit Enable */ +#define AT91C_SSC_RXENA ( ( unsigned int ) 0x1 << 17 ) /* (SSC) Receive Enable */ +/* -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- */ +/* -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- */ +/* -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Two-wire Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_TWI +{ + AT91_REG TWI_CR; /* Control Register */ + AT91_REG TWI_MMR; /* Master Mode Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG TWI_IADR; /* Internal Address Register */ + AT91_REG TWI_CWGR; /* Clock Waveform Generator Register */ + AT91_REG Reserved1[ 3 ]; /* */ + AT91_REG TWI_SR; /* Status Register */ + AT91_REG TWI_IER; /* Interrupt Enable Register */ + AT91_REG TWI_IDR; /* Interrupt Disable Register */ + AT91_REG TWI_IMR; /* Interrupt Mask Register */ + AT91_REG TWI_RHR; /* Receive Holding Register */ + AT91_REG TWI_THR; /* Transmit Holding Register */ +} AT91S_TWI, * AT91PS_TWI; + +/* -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */ +#define AT91C_TWI_START ( ( unsigned int ) 0x1 << 0 ) /* (TWI) Send a START Condition */ +#define AT91C_TWI_STOP ( ( unsigned int ) 0x1 << 1 ) /* (TWI) Send a STOP Condition */ +#define AT91C_TWI_MSEN ( ( unsigned int ) 0x1 << 2 ) /* (TWI) TWI Master Transfer Enabled */ +#define AT91C_TWI_MSDIS ( ( unsigned int ) 0x1 << 3 ) /* (TWI) TWI Master Transfer Disabled */ +#define AT91C_TWI_SWRST ( ( unsigned int ) 0x1 << 7 ) /* (TWI) Software Reset */ +/* -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */ +#define AT91C_TWI_IADRSZ ( ( unsigned int ) 0x3 << 8 ) /* (TWI) Internal Device Address Size */ +#define AT91C_TWI_IADRSZ_NO ( ( unsigned int ) 0x0 << 8 ) /* (TWI) No internal device address */ +#define AT91C_TWI_IADRSZ_1_BYTE ( ( unsigned int ) 0x1 << 8 ) /* (TWI) One-byte internal device address */ +#define AT91C_TWI_IADRSZ_2_BYTE ( ( unsigned int ) 0x2 << 8 ) /* (TWI) Two-byte internal device address */ +#define AT91C_TWI_IADRSZ_3_BYTE ( ( unsigned int ) 0x3 << 8 ) /* (TWI) Three-byte internal device address */ +#define AT91C_TWI_MREAD ( ( unsigned int ) 0x1 << 12 ) /* (TWI) Master Read Direction */ +#define AT91C_TWI_DADR ( ( unsigned int ) 0x7F << 16 ) /* (TWI) Device Address */ +/* -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */ +#define AT91C_TWI_CLDIV ( ( unsigned int ) 0xFF << 0 ) /* (TWI) Clock Low Divider */ +#define AT91C_TWI_CHDIV ( ( unsigned int ) 0xFF << 8 ) /* (TWI) Clock High Divider */ +#define AT91C_TWI_CKDIV ( ( unsigned int ) 0x7 << 16 ) /* (TWI) Clock Divider */ +/* -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */ +#define AT91C_TWI_TXCOMP ( ( unsigned int ) 0x1 << 0 ) /* (TWI) Transmission Completed */ +#define AT91C_TWI_RXRDY ( ( unsigned int ) 0x1 << 1 ) /* (TWI) Receive holding register ReaDY */ +#define AT91C_TWI_TXRDY ( ( unsigned int ) 0x1 << 2 ) /* (TWI) Transmit holding register ReaDY */ +#define AT91C_TWI_OVRE ( ( unsigned int ) 0x1 << 6 ) /* (TWI) Overrun Error */ +#define AT91C_TWI_UNRE ( ( unsigned int ) 0x1 << 7 ) /* (TWI) Underrun Error */ +#define AT91C_TWI_NACK ( ( unsigned int ) 0x1 << 8 ) /* (TWI) Not Acknowledged */ +/* -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */ +/* -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- */ +/* -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR PWMC Channel Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_PWMC_CH +{ + AT91_REG PWMC_CMR; /* Channel Mode Register */ + AT91_REG PWMC_CDTYR; /* Channel Duty Cycle Register */ + AT91_REG PWMC_CPRDR; /* Channel Period Register */ + AT91_REG PWMC_CCNTR; /* Channel Counter Register */ + AT91_REG PWMC_CUPDR; /* Channel Update Register */ + AT91_REG PWMC_Reserved[ 3 ]; /* Reserved */ +} AT91S_PWMC_CH, * AT91PS_PWMC_CH; + +/* -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- */ +#define AT91C_PWMC_CPRE ( ( unsigned int ) 0xF << 0 ) /* (PWMC_CH) Channel Pre-scaler : PWMC_CLKx */ +#define AT91C_PWMC_CPRE_MCK ( ( unsigned int ) 0x0 ) /* (PWMC_CH) */ +#define AT91C_PWMC_CPRE_MCKA ( ( unsigned int ) 0xB ) /* (PWMC_CH) */ +#define AT91C_PWMC_CPRE_MCKB ( ( unsigned int ) 0xC ) /* (PWMC_CH) */ +#define AT91C_PWMC_CALG ( ( unsigned int ) 0x1 << 8 ) /* (PWMC_CH) Channel Alignment */ +#define AT91C_PWMC_CPOL ( ( unsigned int ) 0x1 << 9 ) /* (PWMC_CH) Channel Polarity */ +#define AT91C_PWMC_CPD ( ( unsigned int ) 0x1 << 10 ) /* (PWMC_CH) Channel Update Period */ +/* -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- */ +#define AT91C_PWMC_CDTY ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Duty Cycle */ +/* -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- */ +#define AT91C_PWMC_CPRD ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Period */ +/* -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- */ +#define AT91C_PWMC_CCNT ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Counter */ +/* -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- */ +#define AT91C_PWMC_CUPD ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Update */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_PWMC +{ + AT91_REG PWMC_MR; /* PWMC Mode Register */ + AT91_REG PWMC_ENA; /* PWMC Enable Register */ + AT91_REG PWMC_DIS; /* PWMC Disable Register */ + AT91_REG PWMC_SR; /* PWMC Status Register */ + AT91_REG PWMC_IER; /* PWMC Interrupt Enable Register */ + AT91_REG PWMC_IDR; /* PWMC Interrupt Disable Register */ + AT91_REG PWMC_IMR; /* PWMC Interrupt Mask Register */ + AT91_REG PWMC_ISR; /* PWMC Interrupt Status Register */ + AT91_REG Reserved0[ 55 ]; /* */ + AT91_REG PWMC_VR; /* PWMC Version Register */ + AT91_REG Reserved1[ 64 ]; /* */ + AT91S_PWMC_CH PWMC_CH[ 4 ]; /* PWMC Channel */ +} AT91S_PWMC, * AT91PS_PWMC; + +/* -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- */ +#define AT91C_PWMC_DIVA ( ( unsigned int ) 0xFF << 0 ) /* (PWMC) CLKA divide factor. */ +#define AT91C_PWMC_PREA ( ( unsigned int ) 0xF << 8 ) /* (PWMC) Divider Input Clock Prescaler A */ +#define AT91C_PWMC_PREA_MCK ( ( unsigned int ) 0x0 << 8 ) /* (PWMC) */ +#define AT91C_PWMC_DIVB ( ( unsigned int ) 0xFF << 16 ) /* (PWMC) CLKB divide factor. */ +#define AT91C_PWMC_PREB ( ( unsigned int ) 0xF << 24 ) /* (PWMC) Divider Input Clock Prescaler B */ +#define AT91C_PWMC_PREB_MCK ( ( unsigned int ) 0x0 << 24 ) /* (PWMC) */ +/* -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- */ +#define AT91C_PWMC_CHID0 ( ( unsigned int ) 0x1 << 0 ) /* (PWMC) Channel ID 0 */ +#define AT91C_PWMC_CHID1 ( ( unsigned int ) 0x1 << 1 ) /* (PWMC) Channel ID 1 */ +#define AT91C_PWMC_CHID2 ( ( unsigned int ) 0x1 << 2 ) /* (PWMC) Channel ID 2 */ +#define AT91C_PWMC_CHID3 ( ( unsigned int ) 0x1 << 3 ) /* (PWMC) Channel ID 3 */ +/* -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- */ +/* -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- */ +/* -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- */ +/* -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- */ +/* -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- */ +/* -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR USB Device Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_UDP +{ + AT91_REG UDP_NUM; /* Frame Number Register */ + AT91_REG UDP_GLBSTATE; /* Global State Register */ + AT91_REG UDP_FADDR; /* Function Address Register */ + AT91_REG Reserved0[ 1 ]; /* */ + AT91_REG UDP_IER; /* Interrupt Enable Register */ + AT91_REG UDP_IDR; /* Interrupt Disable Register */ + AT91_REG UDP_IMR; /* Interrupt Mask Register */ + AT91_REG UDP_ISR; /* Interrupt Status Register */ + AT91_REG UDP_ICR; /* Interrupt Clear Register */ + AT91_REG Reserved1[ 1 ]; /* */ + AT91_REG UDP_RSTEP; /* Reset Endpoint Register */ + AT91_REG Reserved2[ 1 ]; /* */ + AT91_REG UDP_CSR[ 6 ]; /* Endpoint Control and Status Register */ + AT91_REG Reserved3[ 2 ]; /* */ + AT91_REG UDP_FDR[ 6 ]; /* Endpoint FIFO Data Register */ + AT91_REG Reserved4[ 3 ]; /* */ + AT91_REG UDP_TXVC; /* Transceiver Control Register */ +} AT91S_UDP, * AT91PS_UDP; + +/* -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- */ +#define AT91C_UDP_FRM_NUM ( ( unsigned int ) 0x7FF << 0 ) /* (UDP) Frame Number as Defined in the Packet Field Formats */ +#define AT91C_UDP_FRM_ERR ( ( unsigned int ) 0x1 << 16 ) /* (UDP) Frame Error */ +#define AT91C_UDP_FRM_OK ( ( unsigned int ) 0x1 << 17 ) /* (UDP) Frame OK */ +/* -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- */ +#define AT91C_UDP_FADDEN ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Function Address Enable */ +#define AT91C_UDP_CONFG ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Configured */ +#define AT91C_UDP_ESR ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Enable Send Resume */ +#define AT91C_UDP_RSMINPR ( ( unsigned int ) 0x1 << 3 ) /* (UDP) A Resume Has Been Sent to the Host */ +#define AT91C_UDP_RMWUPE ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Remote Wake Up Enable */ +/* -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- */ +#define AT91C_UDP_FADD ( ( unsigned int ) 0xFF << 0 ) /* (UDP) Function Address Value */ +#define AT91C_UDP_FEN ( ( unsigned int ) 0x1 << 8 ) /* (UDP) Function Enable */ +/* -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- */ +#define AT91C_UDP_EPINT0 ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Endpoint 0 Interrupt */ +#define AT91C_UDP_EPINT1 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Endpoint 0 Interrupt */ +#define AT91C_UDP_EPINT2 ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Endpoint 2 Interrupt */ +#define AT91C_UDP_EPINT3 ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Endpoint 3 Interrupt */ +#define AT91C_UDP_EPINT4 ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Endpoint 4 Interrupt */ +#define AT91C_UDP_EPINT5 ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Endpoint 5 Interrupt */ +#define AT91C_UDP_RXSUSP ( ( unsigned int ) 0x1 << 8 ) /* (UDP) USB Suspend Interrupt */ +#define AT91C_UDP_RXRSM ( ( unsigned int ) 0x1 << 9 ) /* (UDP) USB Resume Interrupt */ +#define AT91C_UDP_EXTRSM ( ( unsigned int ) 0x1 << 10 ) /* (UDP) USB External Resume Interrupt */ +#define AT91C_UDP_SOFINT ( ( unsigned int ) 0x1 << 11 ) /* (UDP) USB Start Of frame Interrupt */ +#define AT91C_UDP_WAKEUP ( ( unsigned int ) 0x1 << 13 ) /* (UDP) USB Resume Interrupt */ +/* -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- */ +/* -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- */ +/* -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- */ +#define AT91C_UDP_ENDBUSRES ( ( unsigned int ) 0x1 << 12 ) /* (UDP) USB End Of Bus Reset Interrupt */ +/* -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- */ +/* -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- */ +#define AT91C_UDP_EP0 ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Reset Endpoint 0 */ +#define AT91C_UDP_EP1 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Reset Endpoint 1 */ +#define AT91C_UDP_EP2 ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Reset Endpoint 2 */ +#define AT91C_UDP_EP3 ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Reset Endpoint 3 */ +#define AT91C_UDP_EP4 ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Reset Endpoint 4 */ +#define AT91C_UDP_EP5 ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Reset Endpoint 5 */ +/* -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- */ +#define AT91C_UDP_TXCOMP ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Generates an IN packet with data previously written in the DPR */ +#define AT91C_UDP_RX_DATA_BK0 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Receive Data Bank 0 */ +#define AT91C_UDP_RXSETUP ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Sends STALL to the Host (Control endpoints) */ +#define AT91C_UDP_ISOERROR ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Isochronous error (Isochronous endpoints) */ +#define AT91C_UDP_TXPKTRDY ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Transmit Packet Ready */ +#define AT91C_UDP_FORCESTALL ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). */ +#define AT91C_UDP_RX_DATA_BK1 ( ( unsigned int ) 0x1 << 6 ) /* (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). */ +#define AT91C_UDP_DIR ( ( unsigned int ) 0x1 << 7 ) /* (UDP) Transfer Direction */ +#define AT91C_UDP_EPTYPE ( ( unsigned int ) 0x7 << 8 ) /* (UDP) Endpoint type */ +#define AT91C_UDP_EPTYPE_CTRL ( ( unsigned int ) 0x0 << 8 ) /* (UDP) Control */ +#define AT91C_UDP_EPTYPE_ISO_OUT ( ( unsigned int ) 0x1 << 8 ) /* (UDP) Isochronous OUT */ +#define AT91C_UDP_EPTYPE_BULK_OUT ( ( unsigned int ) 0x2 << 8 ) /* (UDP) Bulk OUT */ +#define AT91C_UDP_EPTYPE_INT_OUT ( ( unsigned int ) 0x3 << 8 ) /* (UDP) Interrupt OUT */ +#define AT91C_UDP_EPTYPE_ISO_IN ( ( unsigned int ) 0x5 << 8 ) /* (UDP) Isochronous IN */ +#define AT91C_UDP_EPTYPE_BULK_IN ( ( unsigned int ) 0x6 << 8 ) /* (UDP) Bulk IN */ +#define AT91C_UDP_EPTYPE_INT_IN ( ( unsigned int ) 0x7 << 8 ) /* (UDP) Interrupt IN */ +#define AT91C_UDP_DTGLE ( ( unsigned int ) 0x1 << 11 ) /* (UDP) Data Toggle */ +#define AT91C_UDP_EPEDS ( ( unsigned int ) 0x1 << 15 ) /* (UDP) Endpoint Enable Disable */ +#define AT91C_UDP_RXBYTECNT ( ( unsigned int ) 0x7FF << 16 ) /* (UDP) Number Of Bytes Available in the FIFO */ +/* -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- */ +#define AT91C_UDP_TXVDIS ( ( unsigned int ) 0x1 << 8 ) /* (UDP) */ +#define AT91C_UDP_PUON ( ( unsigned int ) 0x1 << 9 ) /* (UDP) Pull-up ON */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_TC +{ + AT91_REG TC_CCR; /* Channel Control Register */ + AT91_REG TC_CMR; /* Channel Mode Register (Capture Mode / Waveform Mode) */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG TC_CV; /* Counter Value */ + AT91_REG TC_RA; /* Register A */ + AT91_REG TC_RB; /* Register B */ + AT91_REG TC_RC; /* Register C */ + AT91_REG TC_SR; /* Status Register */ + AT91_REG TC_IER; /* Interrupt Enable Register */ + AT91_REG TC_IDR; /* Interrupt Disable Register */ + AT91_REG TC_IMR; /* Interrupt Mask Register */ +} AT91S_TC, * AT91PS_TC; + +/* -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- */ +#define AT91C_TC_CLKEN ( ( unsigned int ) 0x1 << 0 ) /* (TC) Counter Clock Enable Command */ +#define AT91C_TC_CLKDIS ( ( unsigned int ) 0x1 << 1 ) /* (TC) Counter Clock Disable Command */ +#define AT91C_TC_SWTRG ( ( unsigned int ) 0x1 << 2 ) /* (TC) Software Trigger Command */ +/* -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- */ +#define AT91C_TC_CLKS ( ( unsigned int ) 0x7 << 0 ) /* (TC) Clock Selection */ +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ( ( unsigned int ) 0x0 ) /* (TC) Clock selected: TIMER_DIV1_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ( ( unsigned int ) 0x1 ) /* (TC) Clock selected: TIMER_DIV2_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ( ( unsigned int ) 0x2 ) /* (TC) Clock selected: TIMER_DIV3_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ( ( unsigned int ) 0x3 ) /* (TC) Clock selected: TIMER_DIV4_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ( ( unsigned int ) 0x4 ) /* (TC) Clock selected: TIMER_DIV5_CLOCK */ +#define AT91C_TC_CLKS_XC0 ( ( unsigned int ) 0x5 ) /* (TC) Clock selected: XC0 */ +#define AT91C_TC_CLKS_XC1 ( ( unsigned int ) 0x6 ) /* (TC) Clock selected: XC1 */ +#define AT91C_TC_CLKS_XC2 ( ( unsigned int ) 0x7 ) /* (TC) Clock selected: XC2 */ +#define AT91C_TC_CLKI ( ( unsigned int ) 0x1 << 3 ) /* (TC) Clock Invert */ +#define AT91C_TC_BURST ( ( unsigned int ) 0x3 << 4 ) /* (TC) Burst Signal Selection */ +#define AT91C_TC_BURST_NONE ( ( unsigned int ) 0x0 << 4 ) /* (TC) The clock is not gated by an external signal */ +#define AT91C_TC_BURST_XC0 ( ( unsigned int ) 0x1 << 4 ) /* (TC) XC0 is ANDed with the selected clock */ +#define AT91C_TC_BURST_XC1 ( ( unsigned int ) 0x2 << 4 ) /* (TC) XC1 is ANDed with the selected clock */ +#define AT91C_TC_BURST_XC2 ( ( unsigned int ) 0x3 << 4 ) /* (TC) XC2 is ANDed with the selected clock */ +#define AT91C_TC_CPCSTOP ( ( unsigned int ) 0x1 << 6 ) /* (TC) Counter Clock Stopped with RC Compare */ +#define AT91C_TC_LDBSTOP ( ( unsigned int ) 0x1 << 6 ) /* (TC) Counter Clock Stopped with RB Loading */ +#define AT91C_TC_CPCDIS ( ( unsigned int ) 0x1 << 7 ) /* (TC) Counter Clock Disable with RC Compare */ +#define AT91C_TC_LDBDIS ( ( unsigned int ) 0x1 << 7 ) /* (TC) Counter Clock Disabled with RB Loading */ +#define AT91C_TC_ETRGEDG ( ( unsigned int ) 0x3 << 8 ) /* (TC) External Trigger Edge Selection */ +#define AT91C_TC_ETRGEDG_NONE ( ( unsigned int ) 0x0 << 8 ) /* (TC) Edge: None */ +#define AT91C_TC_ETRGEDG_RISING ( ( unsigned int ) 0x1 << 8 ) /* (TC) Edge: rising edge */ +#define AT91C_TC_ETRGEDG_FALLING ( ( unsigned int ) 0x2 << 8 ) /* (TC) Edge: falling edge */ +#define AT91C_TC_ETRGEDG_BOTH ( ( unsigned int ) 0x3 << 8 ) /* (TC) Edge: each edge */ +#define AT91C_TC_EEVTEDG ( ( unsigned int ) 0x3 << 8 ) /* (TC) External Event Edge Selection */ +#define AT91C_TC_EEVTEDG_NONE ( ( unsigned int ) 0x0 << 8 ) /* (TC) Edge: None */ +#define AT91C_TC_EEVTEDG_RISING ( ( unsigned int ) 0x1 << 8 ) /* (TC) Edge: rising edge */ +#define AT91C_TC_EEVTEDG_FALLING ( ( unsigned int ) 0x2 << 8 ) /* (TC) Edge: falling edge */ +#define AT91C_TC_EEVTEDG_BOTH ( ( unsigned int ) 0x3 << 8 ) /* (TC) Edge: each edge */ +#define AT91C_TC_EEVT ( ( unsigned int ) 0x3 << 10 ) /* (TC) External Event Selection */ +#define AT91C_TC_EEVT_TIOB ( ( unsigned int ) 0x0 << 10 ) /* (TC) Signal selected as external event: TIOB TIOB direction: input */ +#define AT91C_TC_EEVT_XC0 ( ( unsigned int ) 0x1 << 10 ) /* (TC) Signal selected as external event: XC0 TIOB direction: output */ +#define AT91C_TC_EEVT_XC1 ( ( unsigned int ) 0x2 << 10 ) /* (TC) Signal selected as external event: XC1 TIOB direction: output */ +#define AT91C_TC_EEVT_XC2 ( ( unsigned int ) 0x3 << 10 ) /* (TC) Signal selected as external event: XC2 TIOB direction: output */ +#define AT91C_TC_ABETRG ( ( unsigned int ) 0x1 << 10 ) /* (TC) TIOA or TIOB External Trigger Selection */ +#define AT91C_TC_ENETRG ( ( unsigned int ) 0x1 << 12 ) /* (TC) External Event Trigger enable */ +#define AT91C_TC_WAVESEL ( ( unsigned int ) 0x3 << 13 ) /* (TC) Waveform Selection */ +#define AT91C_TC_WAVESEL_UP ( ( unsigned int ) 0x0 << 13 ) /* (TC) UP mode without atomatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UPDOWN ( ( unsigned int ) 0x1 << 13 ) /* (TC) UPDOWN mode without automatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UP_AUTO ( ( unsigned int ) 0x2 << 13 ) /* (TC) UP mode with automatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UPDOWN_AUTO ( ( unsigned int ) 0x3 << 13 ) /* (TC) UPDOWN mode with automatic trigger on RC Compare */ +#define AT91C_TC_CPCTRG ( ( unsigned int ) 0x1 << 14 ) /* (TC) RC Compare Trigger Enable */ +#define AT91C_TC_WAVE ( ( unsigned int ) 0x1 << 15 ) /* (TC) */ +#define AT91C_TC_ACPA ( ( unsigned int ) 0x3 << 16 ) /* (TC) RA Compare Effect on TIOA */ +#define AT91C_TC_ACPA_NONE ( ( unsigned int ) 0x0 << 16 ) /* (TC) Effect: none */ +#define AT91C_TC_ACPA_SET ( ( unsigned int ) 0x1 << 16 ) /* (TC) Effect: set */ +#define AT91C_TC_ACPA_CLEAR ( ( unsigned int ) 0x2 << 16 ) /* (TC) Effect: clear */ +#define AT91C_TC_ACPA_TOGGLE ( ( unsigned int ) 0x3 << 16 ) /* (TC) Effect: toggle */ +#define AT91C_TC_LDRA ( ( unsigned int ) 0x3 << 16 ) /* (TC) RA Loading Selection */ +#define AT91C_TC_LDRA_NONE ( ( unsigned int ) 0x0 << 16 ) /* (TC) Edge: None */ +#define AT91C_TC_LDRA_RISING ( ( unsigned int ) 0x1 << 16 ) /* (TC) Edge: rising edge of TIOA */ +#define AT91C_TC_LDRA_FALLING ( ( unsigned int ) 0x2 << 16 ) /* (TC) Edge: falling edge of TIOA */ +#define AT91C_TC_LDRA_BOTH ( ( unsigned int ) 0x3 << 16 ) /* (TC) Edge: each edge of TIOA */ +#define AT91C_TC_ACPC ( ( unsigned int ) 0x3 << 18 ) /* (TC) RC Compare Effect on TIOA */ +#define AT91C_TC_ACPC_NONE ( ( unsigned int ) 0x0 << 18 ) /* (TC) Effect: none */ +#define AT91C_TC_ACPC_SET ( ( unsigned int ) 0x1 << 18 ) /* (TC) Effect: set */ +#define AT91C_TC_ACPC_CLEAR ( ( unsigned int ) 0x2 << 18 ) /* (TC) Effect: clear */ +#define AT91C_TC_ACPC_TOGGLE ( ( unsigned int ) 0x3 << 18 ) /* (TC) Effect: toggle */ +#define AT91C_TC_LDRB ( ( unsigned int ) 0x3 << 18 ) /* (TC) RB Loading Selection */ +#define AT91C_TC_LDRB_NONE ( ( unsigned int ) 0x0 << 18 ) /* (TC) Edge: None */ +#define AT91C_TC_LDRB_RISING ( ( unsigned int ) 0x1 << 18 ) /* (TC) Edge: rising edge of TIOA */ +#define AT91C_TC_LDRB_FALLING ( ( unsigned int ) 0x2 << 18 ) /* (TC) Edge: falling edge of TIOA */ +#define AT91C_TC_LDRB_BOTH ( ( unsigned int ) 0x3 << 18 ) /* (TC) Edge: each edge of TIOA */ +#define AT91C_TC_AEEVT ( ( unsigned int ) 0x3 << 20 ) /* (TC) External Event Effect on TIOA */ +#define AT91C_TC_AEEVT_NONE ( ( unsigned int ) 0x0 << 20 ) /* (TC) Effect: none */ +#define AT91C_TC_AEEVT_SET ( ( unsigned int ) 0x1 << 20 ) /* (TC) Effect: set */ +#define AT91C_TC_AEEVT_CLEAR ( ( unsigned int ) 0x2 << 20 ) /* (TC) Effect: clear */ +#define AT91C_TC_AEEVT_TOGGLE ( ( unsigned int ) 0x3 << 20 ) /* (TC) Effect: toggle */ +#define AT91C_TC_ASWTRG ( ( unsigned int ) 0x3 << 22 ) /* (TC) Software Trigger Effect on TIOA */ +#define AT91C_TC_ASWTRG_NONE ( ( unsigned int ) 0x0 << 22 ) /* (TC) Effect: none */ +#define AT91C_TC_ASWTRG_SET ( ( unsigned int ) 0x1 << 22 ) /* (TC) Effect: set */ +#define AT91C_TC_ASWTRG_CLEAR ( ( unsigned int ) 0x2 << 22 ) /* (TC) Effect: clear */ +#define AT91C_TC_ASWTRG_TOGGLE ( ( unsigned int ) 0x3 << 22 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BCPB ( ( unsigned int ) 0x3 << 24 ) /* (TC) RB Compare Effect on TIOB */ +#define AT91C_TC_BCPB_NONE ( ( unsigned int ) 0x0 << 24 ) /* (TC) Effect: none */ +#define AT91C_TC_BCPB_SET ( ( unsigned int ) 0x1 << 24 ) /* (TC) Effect: set */ +#define AT91C_TC_BCPB_CLEAR ( ( unsigned int ) 0x2 << 24 ) /* (TC) Effect: clear */ +#define AT91C_TC_BCPB_TOGGLE ( ( unsigned int ) 0x3 << 24 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BCPC ( ( unsigned int ) 0x3 << 26 ) /* (TC) RC Compare Effect on TIOB */ +#define AT91C_TC_BCPC_NONE ( ( unsigned int ) 0x0 << 26 ) /* (TC) Effect: none */ +#define AT91C_TC_BCPC_SET ( ( unsigned int ) 0x1 << 26 ) /* (TC) Effect: set */ +#define AT91C_TC_BCPC_CLEAR ( ( unsigned int ) 0x2 << 26 ) /* (TC) Effect: clear */ +#define AT91C_TC_BCPC_TOGGLE ( ( unsigned int ) 0x3 << 26 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BEEVT ( ( unsigned int ) 0x3 << 28 ) /* (TC) External Event Effect on TIOB */ +#define AT91C_TC_BEEVT_NONE ( ( unsigned int ) 0x0 << 28 ) /* (TC) Effect: none */ +#define AT91C_TC_BEEVT_SET ( ( unsigned int ) 0x1 << 28 ) /* (TC) Effect: set */ +#define AT91C_TC_BEEVT_CLEAR ( ( unsigned int ) 0x2 << 28 ) /* (TC) Effect: clear */ +#define AT91C_TC_BEEVT_TOGGLE ( ( unsigned int ) 0x3 << 28 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BSWTRG ( ( unsigned int ) 0x3 << 30 ) /* (TC) Software Trigger Effect on TIOB */ +#define AT91C_TC_BSWTRG_NONE ( ( unsigned int ) 0x0 << 30 ) /* (TC) Effect: none */ +#define AT91C_TC_BSWTRG_SET ( ( unsigned int ) 0x1 << 30 ) /* (TC) Effect: set */ +#define AT91C_TC_BSWTRG_CLEAR ( ( unsigned int ) 0x2 << 30 ) /* (TC) Effect: clear */ +#define AT91C_TC_BSWTRG_TOGGLE ( ( unsigned int ) 0x3 << 30 ) /* (TC) Effect: toggle */ +/* -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- */ +#define AT91C_TC_COVFS ( ( unsigned int ) 0x1 << 0 ) /* (TC) Counter Overflow */ +#define AT91C_TC_LOVRS ( ( unsigned int ) 0x1 << 1 ) /* (TC) Load Overrun */ +#define AT91C_TC_CPAS ( ( unsigned int ) 0x1 << 2 ) /* (TC) RA Compare */ +#define AT91C_TC_CPBS ( ( unsigned int ) 0x1 << 3 ) /* (TC) RB Compare */ +#define AT91C_TC_CPCS ( ( unsigned int ) 0x1 << 4 ) /* (TC) RC Compare */ +#define AT91C_TC_LDRAS ( ( unsigned int ) 0x1 << 5 ) /* (TC) RA Loading */ +#define AT91C_TC_LDRBS ( ( unsigned int ) 0x1 << 6 ) /* (TC) RB Loading */ +#define AT91C_TC_ETRGS ( ( unsigned int ) 0x1 << 7 ) /* (TC) External Trigger */ +#define AT91C_TC_CLKSTA ( ( unsigned int ) 0x1 << 16 ) /* (TC) Clock Enabling */ +#define AT91C_TC_MTIOA ( ( unsigned int ) 0x1 << 17 ) /* (TC) TIOA Mirror */ +#define AT91C_TC_MTIOB ( ( unsigned int ) 0x1 << 18 ) /* (TC) TIOA Mirror */ +/* -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- */ +/* -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- */ +/* -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Timer Counter Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_TCB +{ + AT91S_TC TCB_TC0; /* TC Channel 0 */ + AT91_REG Reserved0[ 4 ]; /* */ + AT91S_TC TCB_TC1; /* TC Channel 1 */ + AT91_REG Reserved1[ 4 ]; /* */ + AT91S_TC TCB_TC2; /* TC Channel 2 */ + AT91_REG Reserved2[ 4 ]; /* */ + AT91_REG TCB_BCR; /* TC Block Control Register */ + AT91_REG TCB_BMR; /* TC Block Mode Register */ +} AT91S_TCB, * AT91PS_TCB; + +/* -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- */ +#define AT91C_TCB_SYNC ( ( unsigned int ) 0x1 << 0 ) /* (TCB) Synchro Command */ +/* -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- */ +#define AT91C_TCB_TC0XC0S ( ( unsigned int ) 0x3 << 0 ) /* (TCB) External Clock Signal 0 Selection */ +#define AT91C_TCB_TC0XC0S_TCLK0 ( ( unsigned int ) 0x0 ) /* (TCB) TCLK0 connected to XC0 */ +#define AT91C_TCB_TC0XC0S_NONE ( ( unsigned int ) 0x1 ) /* (TCB) None signal connected to XC0 */ +#define AT91C_TCB_TC0XC0S_TIOA1 ( ( unsigned int ) 0x2 ) /* (TCB) TIOA1 connected to XC0 */ +#define AT91C_TCB_TC0XC0S_TIOA2 ( ( unsigned int ) 0x3 ) /* (TCB) TIOA2 connected to XC0 */ +#define AT91C_TCB_TC1XC1S ( ( unsigned int ) 0x3 << 2 ) /* (TCB) External Clock Signal 1 Selection */ +#define AT91C_TCB_TC1XC1S_TCLK1 ( ( unsigned int ) 0x0 << 2 ) /* (TCB) TCLK1 connected to XC1 */ +#define AT91C_TCB_TC1XC1S_NONE ( ( unsigned int ) 0x1 << 2 ) /* (TCB) None signal connected to XC1 */ +#define AT91C_TCB_TC1XC1S_TIOA0 ( ( unsigned int ) 0x2 << 2 ) /* (TCB) TIOA0 connected to XC1 */ +#define AT91C_TCB_TC1XC1S_TIOA2 ( ( unsigned int ) 0x3 << 2 ) /* (TCB) TIOA2 connected to XC1 */ +#define AT91C_TCB_TC2XC2S ( ( unsigned int ) 0x3 << 4 ) /* (TCB) External Clock Signal 2 Selection */ +#define AT91C_TCB_TC2XC2S_TCLK2 ( ( unsigned int ) 0x0 << 4 ) /* (TCB) TCLK2 connected to XC2 */ +#define AT91C_TCB_TC2XC2S_NONE ( ( unsigned int ) 0x1 << 4 ) /* (TCB) None signal connected to XC2 */ +#define AT91C_TCB_TC2XC2S_TIOA0 ( ( unsigned int ) 0x2 << 4 ) /* (TCB) TIOA0 connected to XC2 */ +#define AT91C_TCB_TC2XC2S_TIOA1 ( ( unsigned int ) 0x3 << 4 ) /* (TCB) TIOA2 connected to XC2 */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_CAN_MB +{ + AT91_REG CAN_MB_MMR; /* MailBox Mode Register */ + AT91_REG CAN_MB_MAM; /* MailBox Acceptance Mask Register */ + AT91_REG CAN_MB_MID; /* MailBox ID Register */ + AT91_REG CAN_MB_MFID; /* MailBox Family ID Register */ + AT91_REG CAN_MB_MSR; /* MailBox Status Register */ + AT91_REG CAN_MB_MDL; /* MailBox Data Low Register */ + AT91_REG CAN_MB_MDH; /* MailBox Data High Register */ + AT91_REG CAN_MB_MCR; /* MailBox Control Register */ +} AT91S_CAN_MB, * AT91PS_CAN_MB; + +/* -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- */ +#define AT91C_CAN_MTIMEMARK ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN_MB) Mailbox Timemark */ +#define AT91C_CAN_PRIOR ( ( unsigned int ) 0xF << 16 ) /* (CAN_MB) Mailbox Priority */ +#define AT91C_CAN_MOT ( ( unsigned int ) 0x7 << 24 ) /* (CAN_MB) Mailbox Object Type */ +#define AT91C_CAN_MOT_DIS ( ( unsigned int ) 0x0 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_RX ( ( unsigned int ) 0x1 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_RXOVERWRITE ( ( unsigned int ) 0x2 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_TX ( ( unsigned int ) 0x3 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_CONSUMER ( ( unsigned int ) 0x4 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_PRODUCER ( ( unsigned int ) 0x5 << 24 ) /* (CAN_MB) */ +/* -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- */ +#define AT91C_CAN_MIDvB ( ( unsigned int ) 0x3FFFF << 0 ) /* (CAN_MB) Complementary bits for identifier in extended mode */ +#define AT91C_CAN_MIDvA ( ( unsigned int ) 0x7FF << 18 ) /* (CAN_MB) Identifier for standard frame mode */ +#define AT91C_CAN_MIDE ( ( unsigned int ) 0x1 << 29 ) /* (CAN_MB) Identifier Version */ +/* -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- */ +/* -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- */ +/* -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- */ +#define AT91C_CAN_MTIMESTAMP ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN_MB) Timer Value */ +#define AT91C_CAN_MDLC ( ( unsigned int ) 0xF << 16 ) /* (CAN_MB) Mailbox Data Length Code */ +#define AT91C_CAN_MRTR ( ( unsigned int ) 0x1 << 20 ) /* (CAN_MB) Mailbox Remote Transmission Request */ +#define AT91C_CAN_MABT ( ( unsigned int ) 0x1 << 22 ) /* (CAN_MB) Mailbox Message Abort */ +#define AT91C_CAN_MRDY ( ( unsigned int ) 0x1 << 23 ) /* (CAN_MB) Mailbox Ready */ +#define AT91C_CAN_MMI ( ( unsigned int ) 0x1 << 24 ) /* (CAN_MB) Mailbox Message Ignored */ +/* -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- */ +/* -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- */ +/* -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- */ +#define AT91C_CAN_MACR ( ( unsigned int ) 0x1 << 22 ) /* (CAN_MB) Abort Request for Mailbox */ +#define AT91C_CAN_MTCR ( ( unsigned int ) 0x1 << 23 ) /* (CAN_MB) Mailbox Transfer Command */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Control Area Network Interface */ +/* ***************************************************************************** */ +typedef struct _AT91S_CAN +{ + AT91_REG CAN_MR; /* Mode Register */ + AT91_REG CAN_IER; /* Interrupt Enable Register */ + AT91_REG CAN_IDR; /* Interrupt Disable Register */ + AT91_REG CAN_IMR; /* Interrupt Mask Register */ + AT91_REG CAN_SR; /* Status Register */ + AT91_REG CAN_BR; /* Baudrate Register */ + AT91_REG CAN_TIM; /* Timer Register */ + AT91_REG CAN_TIMESTP; /* Time Stamp Register */ + AT91_REG CAN_ECR; /* Error Counter Register */ + AT91_REG CAN_TCR; /* Transfer Command Register */ + AT91_REG CAN_ACR; /* Abort Command Register */ + AT91_REG Reserved0[ 52 ]; /* */ + AT91_REG CAN_VR; /* Version Register */ + AT91_REG Reserved1[ 64 ]; /* */ + AT91S_CAN_MB CAN_MB0; /* CAN Mailbox 0 */ + AT91S_CAN_MB CAN_MB1; /* CAN Mailbox 1 */ + AT91S_CAN_MB CAN_MB2; /* CAN Mailbox 2 */ + AT91S_CAN_MB CAN_MB3; /* CAN Mailbox 3 */ + AT91S_CAN_MB CAN_MB4; /* CAN Mailbox 4 */ + AT91S_CAN_MB CAN_MB5; /* CAN Mailbox 5 */ + AT91S_CAN_MB CAN_MB6; /* CAN Mailbox 6 */ + AT91S_CAN_MB CAN_MB7; /* CAN Mailbox 7 */ + AT91S_CAN_MB CAN_MB8; /* CAN Mailbox 8 */ + AT91S_CAN_MB CAN_MB9; /* CAN Mailbox 9 */ + AT91S_CAN_MB CAN_MB10; /* CAN Mailbox 10 */ + AT91S_CAN_MB CAN_MB11; /* CAN Mailbox 11 */ + AT91S_CAN_MB CAN_MB12; /* CAN Mailbox 12 */ + AT91S_CAN_MB CAN_MB13; /* CAN Mailbox 13 */ + AT91S_CAN_MB CAN_MB14; /* CAN Mailbox 14 */ + AT91S_CAN_MB CAN_MB15; /* CAN Mailbox 15 */ +} AT91S_CAN, * AT91PS_CAN; + +/* -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- */ +#define AT91C_CAN_CANEN ( ( unsigned int ) 0x1 << 0 ) /* (CAN) CAN Controller Enable */ +#define AT91C_CAN_LPM ( ( unsigned int ) 0x1 << 1 ) /* (CAN) Disable/Enable Low Power Mode */ +#define AT91C_CAN_ABM ( ( unsigned int ) 0x1 << 2 ) /* (CAN) Disable/Enable Autobaud/Listen Mode */ +#define AT91C_CAN_OVL ( ( unsigned int ) 0x1 << 3 ) /* (CAN) Disable/Enable Overload Frame */ +#define AT91C_CAN_TEOF ( ( unsigned int ) 0x1 << 4 ) /* (CAN) Time Stamp messages at each end of Frame */ +#define AT91C_CAN_TTM ( ( unsigned int ) 0x1 << 5 ) /* (CAN) Disable/Enable Time Trigger Mode */ +#define AT91C_CAN_TIMFRZ ( ( unsigned int ) 0x1 << 6 ) /* (CAN) Enable Timer Freeze */ +#define AT91C_CAN_DRPT ( ( unsigned int ) 0x1 << 7 ) /* (CAN) Disable Repeat */ +/* -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- */ +#define AT91C_CAN_MB0 ( ( unsigned int ) 0x1 << 0 ) /* (CAN) Mailbox 0 Flag */ +#define AT91C_CAN_MB1 ( ( unsigned int ) 0x1 << 1 ) /* (CAN) Mailbox 1 Flag */ +#define AT91C_CAN_MB2 ( ( unsigned int ) 0x1 << 2 ) /* (CAN) Mailbox 2 Flag */ +#define AT91C_CAN_MB3 ( ( unsigned int ) 0x1 << 3 ) /* (CAN) Mailbox 3 Flag */ +#define AT91C_CAN_MB4 ( ( unsigned int ) 0x1 << 4 ) /* (CAN) Mailbox 4 Flag */ +#define AT91C_CAN_MB5 ( ( unsigned int ) 0x1 << 5 ) /* (CAN) Mailbox 5 Flag */ +#define AT91C_CAN_MB6 ( ( unsigned int ) 0x1 << 6 ) /* (CAN) Mailbox 6 Flag */ +#define AT91C_CAN_MB7 ( ( unsigned int ) 0x1 << 7 ) /* (CAN) Mailbox 7 Flag */ +#define AT91C_CAN_MB8 ( ( unsigned int ) 0x1 << 8 ) /* (CAN) Mailbox 8 Flag */ +#define AT91C_CAN_MB9 ( ( unsigned int ) 0x1 << 9 ) /* (CAN) Mailbox 9 Flag */ +#define AT91C_CAN_MB10 ( ( unsigned int ) 0x1 << 10 ) /* (CAN) Mailbox 10 Flag */ +#define AT91C_CAN_MB11 ( ( unsigned int ) 0x1 << 11 ) /* (CAN) Mailbox 11 Flag */ +#define AT91C_CAN_MB12 ( ( unsigned int ) 0x1 << 12 ) /* (CAN) Mailbox 12 Flag */ +#define AT91C_CAN_MB13 ( ( unsigned int ) 0x1 << 13 ) /* (CAN) Mailbox 13 Flag */ +#define AT91C_CAN_MB14 ( ( unsigned int ) 0x1 << 14 ) /* (CAN) Mailbox 14 Flag */ +#define AT91C_CAN_MB15 ( ( unsigned int ) 0x1 << 15 ) /* (CAN) Mailbox 15 Flag */ +#define AT91C_CAN_ERRA ( ( unsigned int ) 0x1 << 16 ) /* (CAN) Error Active Mode Flag */ +#define AT91C_CAN_WARN ( ( unsigned int ) 0x1 << 17 ) /* (CAN) Warning Limit Flag */ +#define AT91C_CAN_ERRP ( ( unsigned int ) 0x1 << 18 ) /* (CAN) Error Passive Mode Flag */ +#define AT91C_CAN_BOFF ( ( unsigned int ) 0x1 << 19 ) /* (CAN) Bus Off Mode Flag */ +#define AT91C_CAN_SLEEP ( ( unsigned int ) 0x1 << 20 ) /* (CAN) Sleep Flag */ +#define AT91C_CAN_WAKEUP ( ( unsigned int ) 0x1 << 21 ) /* (CAN) Wakeup Flag */ +#define AT91C_CAN_TOVF ( ( unsigned int ) 0x1 << 22 ) /* (CAN) Timer Overflow Flag */ +#define AT91C_CAN_TSTP ( ( unsigned int ) 0x1 << 23 ) /* (CAN) Timestamp Flag */ +#define AT91C_CAN_CERR ( ( unsigned int ) 0x1 << 24 ) /* (CAN) CRC Error */ +#define AT91C_CAN_SERR ( ( unsigned int ) 0x1 << 25 ) /* (CAN) Stuffing Error */ +#define AT91C_CAN_AERR ( ( unsigned int ) 0x1 << 26 ) /* (CAN) Acknowledgment Error */ +#define AT91C_CAN_FERR ( ( unsigned int ) 0x1 << 27 ) /* (CAN) Form Error */ +#define AT91C_CAN_BERR ( ( unsigned int ) 0x1 << 28 ) /* (CAN) Bit Error */ +/* -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- */ +/* -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- */ +/* -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- */ +#define AT91C_CAN_RBSY ( ( unsigned int ) 0x1 << 29 ) /* (CAN) Receiver Busy */ +#define AT91C_CAN_TBSY ( ( unsigned int ) 0x1 << 30 ) /* (CAN) Transmitter Busy */ +#define AT91C_CAN_OVLY ( ( unsigned int ) 0x1 << 31 ) /* (CAN) Overload Busy */ +/* -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- */ +#define AT91C_CAN_PHASE2 ( ( unsigned int ) 0x7 << 0 ) /* (CAN) Phase 2 segment */ +#define AT91C_CAN_PHASE1 ( ( unsigned int ) 0x7 << 4 ) /* (CAN) Phase 1 segment */ +#define AT91C_CAN_PROPAG ( ( unsigned int ) 0x7 << 8 ) /* (CAN) Programmation time segment */ +#define AT91C_CAN_SYNC ( ( unsigned int ) 0x3 << 12 ) /* (CAN) Re-synchronization jump width segment */ +#define AT91C_CAN_BRP ( ( unsigned int ) 0x7F << 16 ) /* (CAN) Baudrate Prescaler */ +#define AT91C_CAN_SMP ( ( unsigned int ) 0x1 << 24 ) /* (CAN) Sampling mode */ +/* -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- */ +#define AT91C_CAN_TIMER ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN) Timer field */ +/* -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- */ +/* -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- */ +#define AT91C_CAN_REC ( ( unsigned int ) 0xFF << 0 ) /* (CAN) Receive Error Counter */ +#define AT91C_CAN_TEC ( ( unsigned int ) 0xFF << 16 ) /* (CAN) Transmit Error Counter */ +/* -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- */ +#define AT91C_CAN_TIMRST ( ( unsigned int ) 0x1 << 31 ) /* (CAN) Timer Reset Field */ +/* -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 */ +/* ***************************************************************************** */ +typedef struct _AT91S_EMAC +{ + AT91_REG EMAC_NCR; /* Network Control Register */ + AT91_REG EMAC_NCFGR; /* Network Configuration Register */ + AT91_REG EMAC_NSR; /* Network Status Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG EMAC_TSR; /* Transmit Status Register */ + AT91_REG EMAC_RBQP; /* Receive Buffer Queue Pointer */ + AT91_REG EMAC_TBQP; /* Transmit Buffer Queue Pointer */ + AT91_REG EMAC_RSR; /* Receive Status Register */ + AT91_REG EMAC_ISR; /* Interrupt Status Register */ + AT91_REG EMAC_IER; /* Interrupt Enable Register */ + AT91_REG EMAC_IDR; /* Interrupt Disable Register */ + AT91_REG EMAC_IMR; /* Interrupt Mask Register */ + AT91_REG EMAC_MAN; /* PHY Maintenance Register */ + AT91_REG EMAC_PTR; /* Pause Time Register */ + AT91_REG EMAC_PFR; /* Pause Frames received Register */ + AT91_REG EMAC_FTO; /* Frames Transmitted OK Register */ + AT91_REG EMAC_SCF; /* Single Collision Frame Register */ + AT91_REG EMAC_MCF; /* Multiple Collision Frame Register */ + AT91_REG EMAC_FRO; /* Frames Received OK Register */ + AT91_REG EMAC_FCSE; /* Frame Check Sequence Error Register */ + AT91_REG EMAC_ALE; /* Alignment Error Register */ + AT91_REG EMAC_DTF; /* Deferred Transmission Frame Register */ + AT91_REG EMAC_LCOL; /* Late Collision Register */ + AT91_REG EMAC_ECOL; /* Excessive Collision Register */ + AT91_REG EMAC_TUND; /* Transmit Underrun Error Register */ + AT91_REG EMAC_CSE; /* Carrier Sense Error Register */ + AT91_REG EMAC_RRE; /* Receive Resource Error Register */ + AT91_REG EMAC_ROV; /* Receive Overrun Errors Register */ + AT91_REG EMAC_RSE; /* Receive Symbol Errors Register */ + AT91_REG EMAC_ELE; /* Excessive Length Errors Register */ + AT91_REG EMAC_RJA; /* Receive Jabbers Register */ + AT91_REG EMAC_USF; /* Undersize Frames Register */ + AT91_REG EMAC_STE; /* SQE Test Error Register */ + AT91_REG EMAC_RLE; /* Receive Length Field Mismatch Register */ + AT91_REG EMAC_TPF; /* Transmitted Pause Frames Register */ + AT91_REG EMAC_HRB; /* Hash Address Bottom[31:0] */ + AT91_REG EMAC_HRT; /* Hash Address Top[63:32] */ + AT91_REG EMAC_SA1L; /* Specific Address 1 Bottom, First 4 bytes */ + AT91_REG EMAC_SA1H; /* Specific Address 1 Top, Last 2 bytes */ + AT91_REG EMAC_SA2L; /* Specific Address 2 Bottom, First 4 bytes */ + AT91_REG EMAC_SA2H; /* Specific Address 2 Top, Last 2 bytes */ + AT91_REG EMAC_SA3L; /* Specific Address 3 Bottom, First 4 bytes */ + AT91_REG EMAC_SA3H; /* Specific Address 3 Top, Last 2 bytes */ + AT91_REG EMAC_SA4L; /* Specific Address 4 Bottom, First 4 bytes */ + AT91_REG EMAC_SA4H; /* Specific Address 4 Top, Last 2 bytes */ + AT91_REG EMAC_TID; /* Type ID Checking Register */ + AT91_REG EMAC_TPQ; /* Transmit Pause Quantum Register */ + AT91_REG EMAC_USRIO; /* USER Input/Output Register */ + AT91_REG EMAC_WOL; /* Wake On LAN Register */ + AT91_REG Reserved1[ 13 ]; /* */ + AT91_REG EMAC_REV; /* Revision Register */ +} AT91S_EMAC, * AT91PS_EMAC; + +/* -------- EMAC_NCR : (EMAC Offset: 0x0) -------- */ +#define AT91C_EMAC_LB ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */ +#define AT91C_EMAC_LLB ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) Loopback local. */ +#define AT91C_EMAC_RE ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) Receive enable. */ +#define AT91C_EMAC_TE ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) Transmit enable. */ +#define AT91C_EMAC_MPE ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) Management port enable. */ +#define AT91C_EMAC_CLRSTAT ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) Clear statistics registers. */ +#define AT91C_EMAC_INCSTAT ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) Increment statistics registers. */ +#define AT91C_EMAC_WESTAT ( ( unsigned int ) 0x1 << 7 ) /* (EMAC) Write enable for statistics registers. */ +#define AT91C_EMAC_BP ( ( unsigned int ) 0x1 << 8 ) /* (EMAC) Back pressure. */ +#define AT91C_EMAC_TSTART ( ( unsigned int ) 0x1 << 9 ) /* (EMAC) Start Transmission. */ +#define AT91C_EMAC_THALT ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) Transmission Halt. */ +#define AT91C_EMAC_TPFR ( ( unsigned int ) 0x1 << 11 ) /* (EMAC) Transmit pause frame */ +#define AT91C_EMAC_TZQ ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) Transmit zero quantum pause frame */ +/* -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- */ +#define AT91C_EMAC_SPD ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) Speed. */ +#define AT91C_EMAC_FD ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) Full duplex. */ +#define AT91C_EMAC_JFRAME ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) Jumbo Frames. */ +#define AT91C_EMAC_CAF ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) Copy all frames. */ +#define AT91C_EMAC_NBC ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) No broadcast. */ +#define AT91C_EMAC_MTI ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) Multicast hash event enable */ +#define AT91C_EMAC_UNI ( ( unsigned int ) 0x1 << 7 ) /* (EMAC) Unicast hash enable. */ +#define AT91C_EMAC_BIG ( ( unsigned int ) 0x1 << 8 ) /* (EMAC) Receive 1522 bytes. */ +#define AT91C_EMAC_EAE ( ( unsigned int ) 0x1 << 9 ) /* (EMAC) External address match enable. */ +#define AT91C_EMAC_CLK ( ( unsigned int ) 0x3 << 10 ) /* (EMAC) */ +#define AT91C_EMAC_CLK_HCLK_8 ( ( unsigned int ) 0x0 << 10 ) /* (EMAC) HCLK divided by 8 */ +#define AT91C_EMAC_CLK_HCLK_16 ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) HCLK divided by 16 */ +#define AT91C_EMAC_CLK_HCLK_32 ( ( unsigned int ) 0x2 << 10 ) /* (EMAC) HCLK divided by 32 */ +#define AT91C_EMAC_CLK_HCLK_64 ( ( unsigned int ) 0x3 << 10 ) /* (EMAC) HCLK divided by 64 */ +#define AT91C_EMAC_RTY ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) */ +#define AT91C_EMAC_PAE ( ( unsigned int ) 0x1 << 13 ) /* (EMAC) */ +#define AT91C_EMAC_RBOF ( ( unsigned int ) 0x3 << 14 ) /* (EMAC) */ +#define AT91C_EMAC_RBOF_OFFSET_0 ( ( unsigned int ) 0x0 << 14 ) /* (EMAC) no offset from start of receive buffer */ +#define AT91C_EMAC_RBOF_OFFSET_1 ( ( unsigned int ) 0x1 << 14 ) /* (EMAC) one byte offset from start of receive buffer */ +#define AT91C_EMAC_RBOF_OFFSET_2 ( ( unsigned int ) 0x2 << 14 ) /* (EMAC) two bytes offset from start of receive buffer */ +#define AT91C_EMAC_RBOF_OFFSET_3 ( ( unsigned int ) 0x3 << 14 ) /* (EMAC) three bytes offset from start of receive buffer */ +#define AT91C_EMAC_RLCE ( ( unsigned int ) 0x1 << 16 ) /* (EMAC) Receive Length field Checking Enable */ +#define AT91C_EMAC_DRFCS ( ( unsigned int ) 0x1 << 17 ) /* (EMAC) Discard Receive FCS */ +#define AT91C_EMAC_EFRHD ( ( unsigned int ) 0x1 << 18 ) /* (EMAC) */ +#define AT91C_EMAC_IRXFCS ( ( unsigned int ) 0x1 << 19 ) /* (EMAC) Ignore RX FCS */ +/* -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- */ +#define AT91C_EMAC_LINKR ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_MDIO ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_IDLE ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */ +/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- */ +#define AT91C_EMAC_UBR ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_COL ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_RLES ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */ +#define AT91C_EMAC_TGO ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) Transmit Go */ +#define AT91C_EMAC_BEX ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) Buffers exhausted mid frame */ +#define AT91C_EMAC_COMP ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) */ +#define AT91C_EMAC_UND ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) */ +/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */ +#define AT91C_EMAC_BNA ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_REC ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_OVR ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */ +/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */ +#define AT91C_EMAC_MFD ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_RCOMP ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_RXUBR ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */ +#define AT91C_EMAC_TXUBR ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) */ +#define AT91C_EMAC_TUNDR ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) */ +#define AT91C_EMAC_RLEX ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) */ +#define AT91C_EMAC_TXERR ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) */ +#define AT91C_EMAC_TCOMP ( ( unsigned int ) 0x1 << 7 ) /* (EMAC) */ +#define AT91C_EMAC_LINK ( ( unsigned int ) 0x1 << 9 ) /* (EMAC) */ +#define AT91C_EMAC_ROVR ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) */ +#define AT91C_EMAC_HRESP ( ( unsigned int ) 0x1 << 11 ) /* (EMAC) */ +#define AT91C_EMAC_PFRE ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) */ +#define AT91C_EMAC_PTZ ( ( unsigned int ) 0x1 << 13 ) /* (EMAC) */ +/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */ +/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */ +/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */ +/* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */ +#define AT91C_EMAC_DATA ( ( unsigned int ) 0xFFFF << 0 ) /* (EMAC) */ +#define AT91C_EMAC_CODE ( ( unsigned int ) 0x3 << 16 ) /* (EMAC) */ +#define AT91C_EMAC_REGA ( ( unsigned int ) 0x1F << 18 ) /* (EMAC) */ +#define AT91C_EMAC_PHYA ( ( unsigned int ) 0x1F << 23 ) /* (EMAC) */ +#define AT91C_EMAC_RW ( ( unsigned int ) 0x3 << 28 ) /* (EMAC) */ +#define AT91C_EMAC_SOF ( ( unsigned int ) 0x3 << 30 ) /* (EMAC) */ +/* -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- */ +#define AT91C_EMAC_RMII ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) Reduce MII */ +/* -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- */ +#define AT91C_EMAC_IP ( ( unsigned int ) 0xFFFF << 0 ) /* (EMAC) ARP request IP address */ +#define AT91C_EMAC_MAG ( ( unsigned int ) 0x1 << 16 ) /* (EMAC) Magic packet event enable */ +#define AT91C_EMAC_ARP ( ( unsigned int ) 0x1 << 17 ) /* (EMAC) ARP request event enable */ +#define AT91C_EMAC_SA1 ( ( unsigned int ) 0x1 << 18 ) /* (EMAC) Specific address register 1 event enable */ +/* -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- */ +#define AT91C_EMAC_REVREF ( ( unsigned int ) 0xFFFF << 0 ) /* (EMAC) */ +#define AT91C_EMAC_PARTREF ( ( unsigned int ) 0xFFFF << 16 ) /* (EMAC) */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Analog to Digital Convertor */ +/* ***************************************************************************** */ +typedef struct _AT91S_ADC +{ + AT91_REG ADC_CR; /* ADC Control Register */ + AT91_REG ADC_MR; /* ADC Mode Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG ADC_CHER; /* ADC Channel Enable Register */ + AT91_REG ADC_CHDR; /* ADC Channel Disable Register */ + AT91_REG ADC_CHSR; /* ADC Channel Status Register */ + AT91_REG ADC_SR; /* ADC Status Register */ + AT91_REG ADC_LCDR; /* ADC Last Converted Data Register */ + AT91_REG ADC_IER; /* ADC Interrupt Enable Register */ + AT91_REG ADC_IDR; /* ADC Interrupt Disable Register */ + AT91_REG ADC_IMR; /* ADC Interrupt Mask Register */ + AT91_REG ADC_CDR0; /* ADC Channel Data Register 0 */ + AT91_REG ADC_CDR1; /* ADC Channel Data Register 1 */ + AT91_REG ADC_CDR2; /* ADC Channel Data Register 2 */ + AT91_REG ADC_CDR3; /* ADC Channel Data Register 3 */ + AT91_REG ADC_CDR4; /* ADC Channel Data Register 4 */ + AT91_REG ADC_CDR5; /* ADC Channel Data Register 5 */ + AT91_REG ADC_CDR6; /* ADC Channel Data Register 6 */ + AT91_REG ADC_CDR7; /* ADC Channel Data Register 7 */ + AT91_REG Reserved1[ 44 ]; /* */ + AT91_REG ADC_RPR; /* Receive Pointer Register */ + AT91_REG ADC_RCR; /* Receive Counter Register */ + AT91_REG ADC_TPR; /* Transmit Pointer Register */ + AT91_REG ADC_TCR; /* Transmit Counter Register */ + AT91_REG ADC_RNPR; /* Receive Next Pointer Register */ + AT91_REG ADC_RNCR; /* Receive Next Counter Register */ + AT91_REG ADC_TNPR; /* Transmit Next Pointer Register */ + AT91_REG ADC_TNCR; /* Transmit Next Counter Register */ + AT91_REG ADC_PTCR; /* PDC Transfer Control Register */ + AT91_REG ADC_PTSR; /* PDC Transfer Status Register */ +} AT91S_ADC, * AT91PS_ADC; + +/* -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- */ +#define AT91C_ADC_SWRST ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Software Reset */ +#define AT91C_ADC_START ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Start Conversion */ +/* -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- */ +#define AT91C_ADC_TRGEN ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Trigger Enable */ +#define AT91C_ADC_TRGEN_DIS ( ( unsigned int ) 0x0 ) /* (ADC) Hardware triggers are disabled. Starting a conversion is only possible by software */ +#define AT91C_ADC_TRGEN_EN ( ( unsigned int ) 0x1 ) /* (ADC) Hardware trigger selected by TRGSEL field is enabled. */ +#define AT91C_ADC_TRGSEL ( ( unsigned int ) 0x7 << 1 ) /* (ADC) Trigger Selection */ +#define AT91C_ADC_TRGSEL_TIOA0 ( ( unsigned int ) 0x0 << 1 ) /* (ADC) Selected TRGSEL = TIAO0 */ +#define AT91C_ADC_TRGSEL_TIOA1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Selected TRGSEL = TIAO1 */ +#define AT91C_ADC_TRGSEL_TIOA2 ( ( unsigned int ) 0x2 << 1 ) /* (ADC) Selected TRGSEL = TIAO2 */ +#define AT91C_ADC_TRGSEL_TIOA3 ( ( unsigned int ) 0x3 << 1 ) /* (ADC) Selected TRGSEL = TIAO3 */ +#define AT91C_ADC_TRGSEL_TIOA4 ( ( unsigned int ) 0x4 << 1 ) /* (ADC) Selected TRGSEL = TIAO4 */ +#define AT91C_ADC_TRGSEL_TIOA5 ( ( unsigned int ) 0x5 << 1 ) /* (ADC) Selected TRGSEL = TIAO5 */ +#define AT91C_ADC_TRGSEL_EXT ( ( unsigned int ) 0x6 << 1 ) /* (ADC) Selected TRGSEL = External Trigger */ +#define AT91C_ADC_LOWRES ( ( unsigned int ) 0x1 << 4 ) /* (ADC) Resolution. */ +#define AT91C_ADC_LOWRES_10_BIT ( ( unsigned int ) 0x0 << 4 ) /* (ADC) 10-bit resolution */ +#define AT91C_ADC_LOWRES_8_BIT ( ( unsigned int ) 0x1 << 4 ) /* (ADC) 8-bit resolution */ +#define AT91C_ADC_SLEEP ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Sleep Mode */ +#define AT91C_ADC_SLEEP_NORMAL_MODE ( ( unsigned int ) 0x0 << 5 ) /* (ADC) Normal Mode */ +#define AT91C_ADC_SLEEP_MODE ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Sleep Mode */ +#define AT91C_ADC_PRESCAL ( ( unsigned int ) 0x3F << 8 ) /* (ADC) Prescaler rate selection */ +#define AT91C_ADC_STARTUP ( ( unsigned int ) 0x1F << 16 ) /* (ADC) Startup Time */ +#define AT91C_ADC_SHTIM ( ( unsigned int ) 0xF << 24 ) /* (ADC) Sample & Hold Time */ +/* -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- */ +#define AT91C_ADC_CH0 ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Channel 0 */ +#define AT91C_ADC_CH1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Channel 1 */ +#define AT91C_ADC_CH2 ( ( unsigned int ) 0x1 << 2 ) /* (ADC) Channel 2 */ +#define AT91C_ADC_CH3 ( ( unsigned int ) 0x1 << 3 ) /* (ADC) Channel 3 */ +#define AT91C_ADC_CH4 ( ( unsigned int ) 0x1 << 4 ) /* (ADC) Channel 4 */ +#define AT91C_ADC_CH5 ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Channel 5 */ +#define AT91C_ADC_CH6 ( ( unsigned int ) 0x1 << 6 ) /* (ADC) Channel 6 */ +#define AT91C_ADC_CH7 ( ( unsigned int ) 0x1 << 7 ) /* (ADC) Channel 7 */ +/* -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- */ +/* -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- */ +/* -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- */ +#define AT91C_ADC_EOC0 ( ( unsigned int ) 0x1 << 0 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC2 ( ( unsigned int ) 0x1 << 2 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC3 ( ( unsigned int ) 0x1 << 3 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC4 ( ( unsigned int ) 0x1 << 4 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC5 ( ( unsigned int ) 0x1 << 5 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC6 ( ( unsigned int ) 0x1 << 6 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC7 ( ( unsigned int ) 0x1 << 7 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_OVRE0 ( ( unsigned int ) 0x1 << 8 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE1 ( ( unsigned int ) 0x1 << 9 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE2 ( ( unsigned int ) 0x1 << 10 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE3 ( ( unsigned int ) 0x1 << 11 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE4 ( ( unsigned int ) 0x1 << 12 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE5 ( ( unsigned int ) 0x1 << 13 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE6 ( ( unsigned int ) 0x1 << 14 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE7 ( ( unsigned int ) 0x1 << 15 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_DRDY ( ( unsigned int ) 0x1 << 16 ) /* (ADC) Data Ready */ +#define AT91C_ADC_GOVRE ( ( unsigned int ) 0x1 << 17 ) /* (ADC) General Overrun */ +#define AT91C_ADC_ENDRX ( ( unsigned int ) 0x1 << 18 ) /* (ADC) End of Receiver Transfer */ +#define AT91C_ADC_RXBUFF ( ( unsigned int ) 0x1 << 19 ) /* (ADC) RXBUFF Interrupt */ +/* -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- */ +#define AT91C_ADC_LDATA ( ( unsigned int ) 0x3FF << 0 ) /* (ADC) Last Data Converted */ +/* -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- */ +/* -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- */ +/* -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- */ +/* -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- */ +#define AT91C_ADC_DATA ( ( unsigned int ) 0x3FF << 0 ) /* (ADC) Converted Data */ +/* -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- */ +/* -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- */ +/* -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- */ +/* -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- */ +/* -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- */ +/* -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- */ +/* -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Advanced Encryption Standard */ +/* ***************************************************************************** */ +typedef struct _AT91S_AES +{ + AT91_REG AES_CR; /* Control Register */ + AT91_REG AES_MR; /* Mode Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG AES_IER; /* Interrupt Enable Register */ + AT91_REG AES_IDR; /* Interrupt Disable Register */ + AT91_REG AES_IMR; /* Interrupt Mask Register */ + AT91_REG AES_ISR; /* Interrupt Status Register */ + AT91_REG AES_KEYWxR[ 4 ]; /* Key Word x Register */ + AT91_REG Reserved1[ 4 ]; /* */ + AT91_REG AES_IDATAxR[ 4 ]; /* Input Data x Register */ + AT91_REG AES_ODATAxR[ 4 ]; /* Output Data x Register */ + AT91_REG AES_IVxR[ 4 ]; /* Initialization Vector x Register */ + AT91_REG Reserved2[ 35 ]; /* */ + AT91_REG AES_VR; /* AES Version Register */ + AT91_REG AES_RPR; /* Receive Pointer Register */ + AT91_REG AES_RCR; /* Receive Counter Register */ + AT91_REG AES_TPR; /* Transmit Pointer Register */ + AT91_REG AES_TCR; /* Transmit Counter Register */ + AT91_REG AES_RNPR; /* Receive Next Pointer Register */ + AT91_REG AES_RNCR; /* Receive Next Counter Register */ + AT91_REG AES_TNPR; /* Transmit Next Pointer Register */ + AT91_REG AES_TNCR; /* Transmit Next Counter Register */ + AT91_REG AES_PTCR; /* PDC Transfer Control Register */ + AT91_REG AES_PTSR; /* PDC Transfer Status Register */ +} AT91S_AES, * AT91PS_AES; + +/* -------- AES_CR : (AES Offset: 0x0) Control Register -------- */ +#define AT91C_AES_START ( ( unsigned int ) 0x1 << 0 ) /* (AES) Starts Processing */ +#define AT91C_AES_SWRST ( ( unsigned int ) 0x1 << 8 ) /* (AES) Software Reset */ +#define AT91C_AES_LOADSEED ( ( unsigned int ) 0x1 << 16 ) /* (AES) Random Number Generator Seed Loading */ +/* -------- AES_MR : (AES Offset: 0x4) Mode Register -------- */ +#define AT91C_AES_CIPHER ( ( unsigned int ) 0x1 << 0 ) /* (AES) Processing Mode */ +#define AT91C_AES_PROCDLY ( ( unsigned int ) 0xF << 4 ) /* (AES) Processing Delay */ +#define AT91C_AES_SMOD ( ( unsigned int ) 0x3 << 8 ) /* (AES) Start Mode */ +#define AT91C_AES_SMOD_MANUAL ( ( unsigned int ) 0x0 << 8 ) /* (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. */ +#define AT91C_AES_SMOD_AUTO ( ( unsigned int ) 0x1 << 8 ) /* (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). */ +#define AT91C_AES_SMOD_PDC ( ( unsigned int ) 0x2 << 8 ) /* (AES) PDC Mode (cf datasheet). */ +#define AT91C_AES_OPMOD ( ( unsigned int ) 0x7 << 12 ) /* (AES) Operation Mode */ +#define AT91C_AES_OPMOD_ECB ( ( unsigned int ) 0x0 << 12 ) /* (AES) ECB Electronic CodeBook mode. */ +#define AT91C_AES_OPMOD_CBC ( ( unsigned int ) 0x1 << 12 ) /* (AES) CBC Cipher Block Chaining mode. */ +#define AT91C_AES_OPMOD_OFB ( ( unsigned int ) 0x2 << 12 ) /* (AES) OFB Output Feedback mode. */ +#define AT91C_AES_OPMOD_CFB ( ( unsigned int ) 0x3 << 12 ) /* (AES) CFB Cipher Feedback mode. */ +#define AT91C_AES_OPMOD_CTR ( ( unsigned int ) 0x4 << 12 ) /* (AES) CTR Counter mode. */ +#define AT91C_AES_LOD ( ( unsigned int ) 0x1 << 15 ) /* (AES) Last Output Data Mode */ +#define AT91C_AES_CFBS ( ( unsigned int ) 0x7 << 16 ) /* (AES) Cipher Feedback Data Size */ +#define AT91C_AES_CFBS_128_BIT ( ( unsigned int ) 0x0 << 16 ) /* (AES) 128-bit. */ +#define AT91C_AES_CFBS_64_BIT ( ( unsigned int ) 0x1 << 16 ) /* (AES) 64-bit. */ +#define AT91C_AES_CFBS_32_BIT ( ( unsigned int ) 0x2 << 16 ) /* (AES) 32-bit. */ +#define AT91C_AES_CFBS_16_BIT ( ( unsigned int ) 0x3 << 16 ) /* (AES) 16-bit. */ +#define AT91C_AES_CFBS_8_BIT ( ( unsigned int ) 0x4 << 16 ) /* (AES) 8-bit. */ +#define AT91C_AES_CKEY ( ( unsigned int ) 0xF << 20 ) /* (AES) Countermeasure Key */ +#define AT91C_AES_CTYPE ( ( unsigned int ) 0x1F << 24 ) /* (AES) Countermeasure Type */ +#define AT91C_AES_CTYPE_TYPE1_EN ( ( unsigned int ) 0x1 << 24 ) /* (AES) Countermeasure type 1 is enabled. */ +#define AT91C_AES_CTYPE_TYPE2_EN ( ( unsigned int ) 0x2 << 24 ) /* (AES) Countermeasure type 2 is enabled. */ +#define AT91C_AES_CTYPE_TYPE3_EN ( ( unsigned int ) 0x4 << 24 ) /* (AES) Countermeasure type 3 is enabled. */ +#define AT91C_AES_CTYPE_TYPE4_EN ( ( unsigned int ) 0x8 << 24 ) /* (AES) Countermeasure type 4 is enabled. */ +#define AT91C_AES_CTYPE_TYPE5_EN ( ( unsigned int ) 0x10 << 24 ) /* (AES) Countermeasure type 5 is enabled. */ +/* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */ +#define AT91C_AES_DATRDY ( ( unsigned int ) 0x1 << 0 ) /* (AES) DATRDY */ +#define AT91C_AES_ENDRX ( ( unsigned int ) 0x1 << 1 ) /* (AES) PDC Read Buffer End */ +#define AT91C_AES_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (AES) PDC Write Buffer End */ +#define AT91C_AES_RXBUFF ( ( unsigned int ) 0x1 << 3 ) /* (AES) PDC Read Buffer Full */ +#define AT91C_AES_TXBUFE ( ( unsigned int ) 0x1 << 4 ) /* (AES) PDC Write Buffer Empty */ +#define AT91C_AES_URAD ( ( unsigned int ) 0x1 << 8 ) /* (AES) Unspecified Register Access Detection */ +/* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */ +/* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */ +/* -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- */ +#define AT91C_AES_URAT ( ( unsigned int ) 0x7 << 12 ) /* (AES) Unspecified Register Access Type Status */ +#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ( ( unsigned int ) 0x0 << 12 ) /* (AES) Input data register written during the data processing in PDC mode. */ +#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ( ( unsigned int ) 0x1 << 12 ) /* (AES) Output data register read during the data processing. */ +#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ( ( unsigned int ) 0x2 << 12 ) /* (AES) Mode register written during the data processing. */ +#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ( ( unsigned int ) 0x3 << 12 ) /* (AES) Output data register read during the sub-keys generation. */ +#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ( ( unsigned int ) 0x4 << 12 ) /* (AES) Mode register written during the sub-keys generation. */ +#define AT91C_AES_URAT_WO_REG_READ ( ( unsigned int ) 0x5 << 12 ) /* (AES) Write-only register read access. */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Triple Data Encryption Standard */ +/* ***************************************************************************** */ +typedef struct _AT91S_TDES +{ + AT91_REG TDES_CR; /* Control Register */ + AT91_REG TDES_MR; /* Mode Register */ + AT91_REG Reserved0[ 2 ]; /* */ + AT91_REG TDES_IER; /* Interrupt Enable Register */ + AT91_REG TDES_IDR; /* Interrupt Disable Register */ + AT91_REG TDES_IMR; /* Interrupt Mask Register */ + AT91_REG TDES_ISR; /* Interrupt Status Register */ + AT91_REG TDES_KEY1WxR[ 2 ]; /* Key 1 Word x Register */ + AT91_REG TDES_KEY2WxR[ 2 ]; /* Key 2 Word x Register */ + AT91_REG TDES_KEY3WxR[ 2 ]; /* Key 3 Word x Register */ + AT91_REG Reserved1[ 2 ]; /* */ + AT91_REG TDES_IDATAxR[ 2 ]; /* Input Data x Register */ + AT91_REG Reserved2[ 2 ]; /* */ + AT91_REG TDES_ODATAxR[ 2 ]; /* Output Data x Register */ + AT91_REG Reserved3[ 2 ]; /* */ + AT91_REG TDES_IVxR[ 2 ]; /* Initialization Vector x Register */ + AT91_REG Reserved4[ 37 ]; /* */ + AT91_REG TDES_VR; /* TDES Version Register */ + AT91_REG TDES_RPR; /* Receive Pointer Register */ + AT91_REG TDES_RCR; /* Receive Counter Register */ + AT91_REG TDES_TPR; /* Transmit Pointer Register */ + AT91_REG TDES_TCR; /* Transmit Counter Register */ + AT91_REG TDES_RNPR; /* Receive Next Pointer Register */ + AT91_REG TDES_RNCR; /* Receive Next Counter Register */ + AT91_REG TDES_TNPR; /* Transmit Next Pointer Register */ + AT91_REG TDES_TNCR; /* Transmit Next Counter Register */ + AT91_REG TDES_PTCR; /* PDC Transfer Control Register */ + AT91_REG TDES_PTSR; /* PDC Transfer Status Register */ +} AT91S_TDES, * AT91PS_TDES; + +/* -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- */ +#define AT91C_TDES_START ( ( unsigned int ) 0x1 << 0 ) /* (TDES) Starts Processing */ +#define AT91C_TDES_SWRST ( ( unsigned int ) 0x1 << 8 ) /* (TDES) Software Reset */ +/* -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- */ +#define AT91C_TDES_CIPHER ( ( unsigned int ) 0x1 << 0 ) /* (TDES) Processing Mode */ +#define AT91C_TDES_TDESMOD ( ( unsigned int ) 0x1 << 1 ) /* (TDES) Single or Triple DES Mode */ +#define AT91C_TDES_KEYMOD ( ( unsigned int ) 0x1 << 4 ) /* (TDES) Key Mode */ +#define AT91C_TDES_SMOD ( ( unsigned int ) 0x3 << 8 ) /* (TDES) Start Mode */ +#define AT91C_TDES_SMOD_MANUAL ( ( unsigned int ) 0x0 << 8 ) /* (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. */ +#define AT91C_TDES_SMOD_AUTO ( ( unsigned int ) 0x1 << 8 ) /* (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). */ +#define AT91C_TDES_SMOD_PDC ( ( unsigned int ) 0x2 << 8 ) /* (TDES) PDC Mode (cf datasheet). */ +#define AT91C_TDES_OPMOD ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Operation Mode */ +#define AT91C_TDES_OPMOD_ECB ( ( unsigned int ) 0x0 << 12 ) /* (TDES) ECB Electronic CodeBook mode. */ +#define AT91C_TDES_OPMOD_CBC ( ( unsigned int ) 0x1 << 12 ) /* (TDES) CBC Cipher Block Chaining mode. */ +#define AT91C_TDES_OPMOD_OFB ( ( unsigned int ) 0x2 << 12 ) /* (TDES) OFB Output Feedback mode. */ +#define AT91C_TDES_OPMOD_CFB ( ( unsigned int ) 0x3 << 12 ) /* (TDES) CFB Cipher Feedback mode. */ +#define AT91C_TDES_LOD ( ( unsigned int ) 0x1 << 15 ) /* (TDES) Last Output Data Mode */ +#define AT91C_TDES_CFBS ( ( unsigned int ) 0x3 << 16 ) /* (TDES) Cipher Feedback Data Size */ +#define AT91C_TDES_CFBS_64_BIT ( ( unsigned int ) 0x0 << 16 ) /* (TDES) 64-bit. */ +#define AT91C_TDES_CFBS_32_BIT ( ( unsigned int ) 0x1 << 16 ) /* (TDES) 32-bit. */ +#define AT91C_TDES_CFBS_16_BIT ( ( unsigned int ) 0x2 << 16 ) /* (TDES) 16-bit. */ +#define AT91C_TDES_CFBS_8_BIT ( ( unsigned int ) 0x3 << 16 ) /* (TDES) 8-bit. */ +/* -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- */ +#define AT91C_TDES_DATRDY ( ( unsigned int ) 0x1 << 0 ) /* (TDES) DATRDY */ +#define AT91C_TDES_ENDRX ( ( unsigned int ) 0x1 << 1 ) /* (TDES) PDC Read Buffer End */ +#define AT91C_TDES_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (TDES) PDC Write Buffer End */ +#define AT91C_TDES_RXBUFF ( ( unsigned int ) 0x1 << 3 ) /* (TDES) PDC Read Buffer Full */ +#define AT91C_TDES_TXBUFE ( ( unsigned int ) 0x1 << 4 ) /* (TDES) PDC Write Buffer Empty */ +#define AT91C_TDES_URAD ( ( unsigned int ) 0x1 << 8 ) /* (TDES) Unspecified Register Access Detection */ +/* -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- */ +/* -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- */ +/* -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- */ +#define AT91C_TDES_URAT ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Unspecified Register Access Type Status */ +#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ( ( unsigned int ) 0x0 << 12 ) /* (TDES) Input data register written during the data processing in PDC mode. */ +#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ( ( unsigned int ) 0x1 << 12 ) /* (TDES) Output data register read during the data processing. */ +#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ( ( unsigned int ) 0x2 << 12 ) /* (TDES) Mode register written during the data processing. */ +#define AT91C_TDES_URAT_WO_REG_READ ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Write-only register read access. */ + +/* ***************************************************************************** */ +/* REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 */ +/* ***************************************************************************** */ +/* ========== Register definition for SYS peripheral ========== */ +/* ========== Register definition for AIC peripheral ========== */ +#define AT91C_AIC_IVR ( ( AT91_REG * ) 0xFFFFF100 ) /* (AIC) IRQ Vector Register */ +#define AT91C_AIC_SMR ( ( AT91_REG * ) 0xFFFFF000 ) /* (AIC) Source Mode Register */ +#define AT91C_AIC_FVR ( ( AT91_REG * ) 0xFFFFF104 ) /* (AIC) FIQ Vector Register */ +#define AT91C_AIC_DCR ( ( AT91_REG * ) 0xFFFFF138 ) /* (AIC) Debug Control Register (Protect) */ +#define AT91C_AIC_EOICR ( ( AT91_REG * ) 0xFFFFF130 ) /* (AIC) End of Interrupt Command Register */ +#define AT91C_AIC_SVR ( ( AT91_REG * ) 0xFFFFF080 ) /* (AIC) Source Vector Register */ +#define AT91C_AIC_FFSR ( ( AT91_REG * ) 0xFFFFF148 ) /* (AIC) Fast Forcing Status Register */ +#define AT91C_AIC_ICCR ( ( AT91_REG * ) 0xFFFFF128 ) /* (AIC) Interrupt Clear Command Register */ +#define AT91C_AIC_ISR ( ( AT91_REG * ) 0xFFFFF108 ) /* (AIC) Interrupt Status Register */ +#define AT91C_AIC_IMR ( ( AT91_REG * ) 0xFFFFF110 ) /* (AIC) Interrupt Mask Register */ +#define AT91C_AIC_IPR ( ( AT91_REG * ) 0xFFFFF10C ) /* (AIC) Interrupt Pending Register */ +#define AT91C_AIC_FFER ( ( AT91_REG * ) 0xFFFFF140 ) /* (AIC) Fast Forcing Enable Register */ +#define AT91C_AIC_IECR ( ( AT91_REG * ) 0xFFFFF120 ) /* (AIC) Interrupt Enable Command Register */ +#define AT91C_AIC_ISCR ( ( AT91_REG * ) 0xFFFFF12C ) /* (AIC) Interrupt Set Command Register */ +#define AT91C_AIC_FFDR ( ( AT91_REG * ) 0xFFFFF144 ) /* (AIC) Fast Forcing Disable Register */ +#define AT91C_AIC_CISR ( ( AT91_REG * ) 0xFFFFF114 ) /* (AIC) Core Interrupt Status Register */ +#define AT91C_AIC_IDCR ( ( AT91_REG * ) 0xFFFFF124 ) /* (AIC) Interrupt Disable Command Register */ +#define AT91C_AIC_SPU ( ( AT91_REG * ) 0xFFFFF134 ) /* (AIC) Spurious Vector Register */ +/* ========== Register definition for PDC_DBGU peripheral ========== */ +#define AT91C_DBGU_TCR ( ( AT91_REG * ) 0xFFFFF30C ) /* (PDC_DBGU) Transmit Counter Register */ +#define AT91C_DBGU_RNPR ( ( AT91_REG * ) 0xFFFFF310 ) /* (PDC_DBGU) Receive Next Pointer Register */ +#define AT91C_DBGU_TNPR ( ( AT91_REG * ) 0xFFFFF318 ) /* (PDC_DBGU) Transmit Next Pointer Register */ +#define AT91C_DBGU_TPR ( ( AT91_REG * ) 0xFFFFF308 ) /* (PDC_DBGU) Transmit Pointer Register */ +#define AT91C_DBGU_RPR ( ( AT91_REG * ) 0xFFFFF300 ) /* (PDC_DBGU) Receive Pointer Register */ +#define AT91C_DBGU_RCR ( ( AT91_REG * ) 0xFFFFF304 ) /* (PDC_DBGU) Receive Counter Register */ +#define AT91C_DBGU_RNCR ( ( AT91_REG * ) 0xFFFFF314 ) /* (PDC_DBGU) Receive Next Counter Register */ +#define AT91C_DBGU_PTCR ( ( AT91_REG * ) 0xFFFFF320 ) /* (PDC_DBGU) PDC Transfer Control Register */ +#define AT91C_DBGU_PTSR ( ( AT91_REG * ) 0xFFFFF324 ) /* (PDC_DBGU) PDC Transfer Status Register */ +#define AT91C_DBGU_TNCR ( ( AT91_REG * ) 0xFFFFF31C ) /* (PDC_DBGU) Transmit Next Counter Register */ +/* ========== Register definition for DBGU peripheral ========== */ +#define AT91C_DBGU_EXID ( ( AT91_REG * ) 0xFFFFF244 ) /* (DBGU) Chip ID Extension Register */ +#define AT91C_DBGU_BRGR ( ( AT91_REG * ) 0xFFFFF220 ) /* (DBGU) Baud Rate Generator Register */ +#define AT91C_DBGU_IDR ( ( AT91_REG * ) 0xFFFFF20C ) /* (DBGU) Interrupt Disable Register */ +#define AT91C_DBGU_CSR ( ( AT91_REG * ) 0xFFFFF214 ) /* (DBGU) Channel Status Register */ +#define AT91C_DBGU_CIDR ( ( AT91_REG * ) 0xFFFFF240 ) /* (DBGU) Chip ID Register */ +#define AT91C_DBGU_MR ( ( AT91_REG * ) 0xFFFFF204 ) /* (DBGU) Mode Register */ +#define AT91C_DBGU_IMR ( ( AT91_REG * ) 0xFFFFF210 ) /* (DBGU) Interrupt Mask Register */ +#define AT91C_DBGU_CR ( ( AT91_REG * ) 0xFFFFF200 ) /* (DBGU) Control Register */ +#define AT91C_DBGU_FNTR ( ( AT91_REG * ) 0xFFFFF248 ) /* (DBGU) Force NTRST Register */ +#define AT91C_DBGU_THR ( ( AT91_REG * ) 0xFFFFF21C ) /* (DBGU) Transmitter Holding Register */ +#define AT91C_DBGU_RHR ( ( AT91_REG * ) 0xFFFFF218 ) /* (DBGU) Receiver Holding Register */ +#define AT91C_DBGU_IER ( ( AT91_REG * ) 0xFFFFF208 ) /* (DBGU) Interrupt Enable Register */ +/* ========== Register definition for PIOA peripheral ========== */ +#define AT91C_PIOA_ODR ( ( AT91_REG * ) 0xFFFFF414 ) /* (PIOA) Output Disable Registerr */ +#define AT91C_PIOA_SODR ( ( AT91_REG * ) 0xFFFFF430 ) /* (PIOA) Set Output Data Register */ +#define AT91C_PIOA_ISR ( ( AT91_REG * ) 0xFFFFF44C ) /* (PIOA) Interrupt Status Register */ +#define AT91C_PIOA_ABSR ( ( AT91_REG * ) 0xFFFFF478 ) /* (PIOA) AB Select Status Register */ +#define AT91C_PIOA_IER ( ( AT91_REG * ) 0xFFFFF440 ) /* (PIOA) Interrupt Enable Register */ +#define AT91C_PIOA_PPUDR ( ( AT91_REG * ) 0xFFFFF460 ) /* (PIOA) Pull-up Disable Register */ +#define AT91C_PIOA_IMR ( ( AT91_REG * ) 0xFFFFF448 ) /* (PIOA) Interrupt Mask Register */ +#define AT91C_PIOA_PER ( ( AT91_REG * ) 0xFFFFF400 ) /* (PIOA) PIO Enable Register */ +#define AT91C_PIOA_IFDR ( ( AT91_REG * ) 0xFFFFF424 ) /* (PIOA) Input Filter Disable Register */ +#define AT91C_PIOA_OWDR ( ( AT91_REG * ) 0xFFFFF4A4 ) /* (PIOA) Output Write Disable Register */ +#define AT91C_PIOA_MDSR ( ( AT91_REG * ) 0xFFFFF458 ) /* (PIOA) Multi-driver Status Register */ +#define AT91C_PIOA_IDR ( ( AT91_REG * ) 0xFFFFF444 ) /* (PIOA) Interrupt Disable Register */ +#define AT91C_PIOA_ODSR ( ( AT91_REG * ) 0xFFFFF438 ) /* (PIOA) Output Data Status Register */ +#define AT91C_PIOA_PPUSR ( ( AT91_REG * ) 0xFFFFF468 ) /* (PIOA) Pull-up Status Register */ +#define AT91C_PIOA_OWSR ( ( AT91_REG * ) 0xFFFFF4A8 ) /* (PIOA) Output Write Status Register */ +#define AT91C_PIOA_BSR ( ( AT91_REG * ) 0xFFFFF474 ) /* (PIOA) Select B Register */ +#define AT91C_PIOA_OWER ( ( AT91_REG * ) 0xFFFFF4A0 ) /* (PIOA) Output Write Enable Register */ +#define AT91C_PIOA_IFER ( ( AT91_REG * ) 0xFFFFF420 ) /* (PIOA) Input Filter Enable Register */ +#define AT91C_PIOA_PDSR ( ( AT91_REG * ) 0xFFFFF43C ) /* (PIOA) Pin Data Status Register */ +#define AT91C_PIOA_PPUER ( ( AT91_REG * ) 0xFFFFF464 ) /* (PIOA) Pull-up Enable Register */ +#define AT91C_PIOA_OSR ( ( AT91_REG * ) 0xFFFFF418 ) /* (PIOA) Output Status Register */ +#define AT91C_PIOA_ASR ( ( AT91_REG * ) 0xFFFFF470 ) /* (PIOA) Select A Register */ +#define AT91C_PIOA_MDDR ( ( AT91_REG * ) 0xFFFFF454 ) /* (PIOA) Multi-driver Disable Register */ +#define AT91C_PIOA_CODR ( ( AT91_REG * ) 0xFFFFF434 ) /* (PIOA) Clear Output Data Register */ +#define AT91C_PIOA_MDER ( ( AT91_REG * ) 0xFFFFF450 ) /* (PIOA) Multi-driver Enable Register */ +#define AT91C_PIOA_PDR ( ( AT91_REG * ) 0xFFFFF404 ) /* (PIOA) PIO Disable Register */ +#define AT91C_PIOA_IFSR ( ( AT91_REG * ) 0xFFFFF428 ) /* (PIOA) Input Filter Status Register */ +#define AT91C_PIOA_OER ( ( AT91_REG * ) 0xFFFFF410 ) /* (PIOA) Output Enable Register */ +#define AT91C_PIOA_PSR ( ( AT91_REG * ) 0xFFFFF408 ) /* (PIOA) PIO Status Register */ +/* ========== Register definition for PIOB peripheral ========== */ +#define AT91C_PIOB_OWDR ( ( AT91_REG * ) 0xFFFFF6A4 ) /* (PIOB) Output Write Disable Register */ +#define AT91C_PIOB_MDER ( ( AT91_REG * ) 0xFFFFF650 ) /* (PIOB) Multi-driver Enable Register */ +#define AT91C_PIOB_PPUSR ( ( AT91_REG * ) 0xFFFFF668 ) /* (PIOB) Pull-up Status Register */ +#define AT91C_PIOB_IMR ( ( AT91_REG * ) 0xFFFFF648 ) /* (PIOB) Interrupt Mask Register */ +#define AT91C_PIOB_ASR ( ( AT91_REG * ) 0xFFFFF670 ) /* (PIOB) Select A Register */ +#define AT91C_PIOB_PPUDR ( ( AT91_REG * ) 0xFFFFF660 ) /* (PIOB) Pull-up Disable Register */ +#define AT91C_PIOB_PSR ( ( AT91_REG * ) 0xFFFFF608 ) /* (PIOB) PIO Status Register */ +#define AT91C_PIOB_IER ( ( AT91_REG * ) 0xFFFFF640 ) /* (PIOB) Interrupt Enable Register */ +#define AT91C_PIOB_CODR ( ( AT91_REG * ) 0xFFFFF634 ) /* (PIOB) Clear Output Data Register */ +#define AT91C_PIOB_OWER ( ( AT91_REG * ) 0xFFFFF6A0 ) /* (PIOB) Output Write Enable Register */ +#define AT91C_PIOB_ABSR ( ( AT91_REG * ) 0xFFFFF678 ) /* (PIOB) AB Select Status Register */ +#define AT91C_PIOB_IFDR ( ( AT91_REG * ) 0xFFFFF624 ) /* (PIOB) Input Filter Disable Register */ +#define AT91C_PIOB_PDSR ( ( AT91_REG * ) 0xFFFFF63C ) /* (PIOB) Pin Data Status Register */ +#define AT91C_PIOB_IDR ( ( AT91_REG * ) 0xFFFFF644 ) /* (PIOB) Interrupt Disable Register */ +#define AT91C_PIOB_OWSR ( ( AT91_REG * ) 0xFFFFF6A8 ) /* (PIOB) Output Write Status Register */ +#define AT91C_PIOB_PDR ( ( AT91_REG * ) 0xFFFFF604 ) /* (PIOB) PIO Disable Register */ +#define AT91C_PIOB_ODR ( ( AT91_REG * ) 0xFFFFF614 ) /* (PIOB) Output Disable Registerr */ +#define AT91C_PIOB_IFSR ( ( AT91_REG * ) 0xFFFFF628 ) /* (PIOB) Input Filter Status Register */ +#define AT91C_PIOB_PPUER ( ( AT91_REG * ) 0xFFFFF664 ) /* (PIOB) Pull-up Enable Register */ +#define AT91C_PIOB_SODR ( ( AT91_REG * ) 0xFFFFF630 ) /* (PIOB) Set Output Data Register */ +#define AT91C_PIOB_ISR ( ( AT91_REG * ) 0xFFFFF64C ) /* (PIOB) Interrupt Status Register */ +#define AT91C_PIOB_ODSR ( ( AT91_REG * ) 0xFFFFF638 ) /* (PIOB) Output Data Status Register */ +#define AT91C_PIOB_OSR ( ( AT91_REG * ) 0xFFFFF618 ) /* (PIOB) Output Status Register */ +#define AT91C_PIOB_MDSR ( ( AT91_REG * ) 0xFFFFF658 ) /* (PIOB) Multi-driver Status Register */ +#define AT91C_PIOB_IFER ( ( AT91_REG * ) 0xFFFFF620 ) /* (PIOB) Input Filter Enable Register */ +#define AT91C_PIOB_BSR ( ( AT91_REG * ) 0xFFFFF674 ) /* (PIOB) Select B Register */ +#define AT91C_PIOB_MDDR ( ( AT91_REG * ) 0xFFFFF654 ) /* (PIOB) Multi-driver Disable Register */ +#define AT91C_PIOB_OER ( ( AT91_REG * ) 0xFFFFF610 ) /* (PIOB) Output Enable Register */ +#define AT91C_PIOB_PER ( ( AT91_REG * ) 0xFFFFF600 ) /* (PIOB) PIO Enable Register */ +/* ========== Register definition for CKGR peripheral ========== */ +#define AT91C_CKGR_MOR ( ( AT91_REG * ) 0xFFFFFC20 ) /* (CKGR) Main Oscillator Register */ +#define AT91C_CKGR_PLLR ( ( AT91_REG * ) 0xFFFFFC2C ) /* (CKGR) PLL Register */ +#define AT91C_CKGR_MCFR ( ( AT91_REG * ) 0xFFFFFC24 ) /* (CKGR) Main Clock Frequency Register */ +/* ========== Register definition for PMC peripheral ========== */ +#define AT91C_PMC_IDR ( ( AT91_REG * ) 0xFFFFFC64 ) /* (PMC) Interrupt Disable Register */ +#define AT91C_PMC_MOR ( ( AT91_REG * ) 0xFFFFFC20 ) /* (PMC) Main Oscillator Register */ +#define AT91C_PMC_PLLR ( ( AT91_REG * ) 0xFFFFFC2C ) /* (PMC) PLL Register */ +#define AT91C_PMC_PCER ( ( AT91_REG * ) 0xFFFFFC10 ) /* (PMC) Peripheral Clock Enable Register */ +#define AT91C_PMC_PCKR ( ( AT91_REG * ) 0xFFFFFC40 ) /* (PMC) Programmable Clock Register */ +#define AT91C_PMC_MCKR ( ( AT91_REG * ) 0xFFFFFC30 ) /* (PMC) Master Clock Register */ +#define AT91C_PMC_SCDR ( ( AT91_REG * ) 0xFFFFFC04 ) /* (PMC) System Clock Disable Register */ +#define AT91C_PMC_PCDR ( ( AT91_REG * ) 0xFFFFFC14 ) /* (PMC) Peripheral Clock Disable Register */ +#define AT91C_PMC_SCSR ( ( AT91_REG * ) 0xFFFFFC08 ) /* (PMC) System Clock Status Register */ +#define AT91C_PMC_PCSR ( ( AT91_REG * ) 0xFFFFFC18 ) /* (PMC) Peripheral Clock Status Register */ +#define AT91C_PMC_MCFR ( ( AT91_REG * ) 0xFFFFFC24 ) /* (PMC) Main Clock Frequency Register */ +#define AT91C_PMC_SCER ( ( AT91_REG * ) 0xFFFFFC00 ) /* (PMC) System Clock Enable Register */ +#define AT91C_PMC_IMR ( ( AT91_REG * ) 0xFFFFFC6C ) /* (PMC) Interrupt Mask Register */ +#define AT91C_PMC_IER ( ( AT91_REG * ) 0xFFFFFC60 ) /* (PMC) Interrupt Enable Register */ +#define AT91C_PMC_SR ( ( AT91_REG * ) 0xFFFFFC68 ) /* (PMC) Status Register */ +/* ========== Register definition for RSTC peripheral ========== */ +#define AT91C_RSTC_RCR ( ( AT91_REG * ) 0xFFFFFD00 ) /* (RSTC) Reset Control Register */ +#define AT91C_RSTC_RMR ( ( AT91_REG * ) 0xFFFFFD08 ) /* (RSTC) Reset Mode Register */ +#define AT91C_RSTC_RSR ( ( AT91_REG * ) 0xFFFFFD04 ) /* (RSTC) Reset Status Register */ +/* ========== Register definition for RTTC peripheral ========== */ +#define AT91C_RTTC_RTSR ( ( AT91_REG * ) 0xFFFFFD2C ) /* (RTTC) Real-time Status Register */ +#define AT91C_RTTC_RTMR ( ( AT91_REG * ) 0xFFFFFD20 ) /* (RTTC) Real-time Mode Register */ +#define AT91C_RTTC_RTVR ( ( AT91_REG * ) 0xFFFFFD28 ) /* (RTTC) Real-time Value Register */ +#define AT91C_RTTC_RTAR ( ( AT91_REG * ) 0xFFFFFD24 ) /* (RTTC) Real-time Alarm Register */ +/* ========== Register definition for PITC peripheral ========== */ +#define AT91C_PITC_PIVR ( ( AT91_REG * ) 0xFFFFFD38 ) /* (PITC) Period Interval Value Register */ +#define AT91C_PITC_PISR ( ( AT91_REG * ) 0xFFFFFD34 ) /* (PITC) Period Interval Status Register */ +#define AT91C_PITC_PIIR ( ( AT91_REG * ) 0xFFFFFD3C ) /* (PITC) Period Interval Image Register */ +#define AT91C_PITC_PIMR ( ( AT91_REG * ) 0xFFFFFD30 ) /* (PITC) Period Interval Mode Register */ +/* ========== Register definition for WDTC peripheral ========== */ +#define AT91C_WDTC_WDCR ( ( AT91_REG * ) 0xFFFFFD40 ) /* (WDTC) Watchdog Control Register */ +#define AT91C_WDTC_WDSR ( ( AT91_REG * ) 0xFFFFFD48 ) /* (WDTC) Watchdog Status Register */ +#define AT91C_WDTC_WDMR ( ( AT91_REG * ) 0xFFFFFD44 ) /* (WDTC) Watchdog Mode Register */ +/* ========== Register definition for VREG peripheral ========== */ +#define AT91C_VREG_MR ( ( AT91_REG * ) 0xFFFFFD60 ) /* (VREG) Voltage Regulator Mode Register */ +/* ========== Register definition for MC peripheral ========== */ +#define AT91C_MC_ASR ( ( AT91_REG * ) 0xFFFFFF04 ) /* (MC) MC Abort Status Register */ +#define AT91C_MC_RCR ( ( AT91_REG * ) 0xFFFFFF00 ) /* (MC) MC Remap Control Register */ +#define AT91C_MC_FCR ( ( AT91_REG * ) 0xFFFFFF64 ) /* (MC) MC Flash Command Register */ +#define AT91C_MC_AASR ( ( AT91_REG * ) 0xFFFFFF08 ) /* (MC) MC Abort Address Status Register */ +#define AT91C_MC_FSR ( ( AT91_REG * ) 0xFFFFFF68 ) /* (MC) MC Flash Status Register */ +#define AT91C_MC_FMR ( ( AT91_REG * ) 0xFFFFFF60 ) /* (MC) MC Flash Mode Register */ +/* ========== Register definition for PDC_SPI1 peripheral ========== */ +#define AT91C_SPI1_PTCR ( ( AT91_REG * ) 0xFFFE4120 ) /* (PDC_SPI1) PDC Transfer Control Register */ +#define AT91C_SPI1_RPR ( ( AT91_REG * ) 0xFFFE4100 ) /* (PDC_SPI1) Receive Pointer Register */ +#define AT91C_SPI1_TNCR ( ( AT91_REG * ) 0xFFFE411C ) /* (PDC_SPI1) Transmit Next Counter Register */ +#define AT91C_SPI1_TPR ( ( AT91_REG * ) 0xFFFE4108 ) /* (PDC_SPI1) Transmit Pointer Register */ +#define AT91C_SPI1_TNPR ( ( AT91_REG * ) 0xFFFE4118 ) /* (PDC_SPI1) Transmit Next Pointer Register */ +#define AT91C_SPI1_TCR ( ( AT91_REG * ) 0xFFFE410C ) /* (PDC_SPI1) Transmit Counter Register */ +#define AT91C_SPI1_RCR ( ( AT91_REG * ) 0xFFFE4104 ) /* (PDC_SPI1) Receive Counter Register */ +#define AT91C_SPI1_RNPR ( ( AT91_REG * ) 0xFFFE4110 ) /* (PDC_SPI1) Receive Next Pointer Register */ +#define AT91C_SPI1_RNCR ( ( AT91_REG * ) 0xFFFE4114 ) /* (PDC_SPI1) Receive Next Counter Register */ +#define AT91C_SPI1_PTSR ( ( AT91_REG * ) 0xFFFE4124 ) /* (PDC_SPI1) PDC Transfer Status Register */ +/* ========== Register definition for SPI1 peripheral ========== */ +#define AT91C_SPI1_IMR ( ( AT91_REG * ) 0xFFFE401C ) /* (SPI1) Interrupt Mask Register */ +#define AT91C_SPI1_IER ( ( AT91_REG * ) 0xFFFE4014 ) /* (SPI1) Interrupt Enable Register */ +#define AT91C_SPI1_MR ( ( AT91_REG * ) 0xFFFE4004 ) /* (SPI1) Mode Register */ +#define AT91C_SPI1_RDR ( ( AT91_REG * ) 0xFFFE4008 ) /* (SPI1) Receive Data Register */ +#define AT91C_SPI1_IDR ( ( AT91_REG * ) 0xFFFE4018 ) /* (SPI1) Interrupt Disable Register */ +#define AT91C_SPI1_SR ( ( AT91_REG * ) 0xFFFE4010 ) /* (SPI1) Status Register */ +#define AT91C_SPI1_TDR ( ( AT91_REG * ) 0xFFFE400C ) /* (SPI1) Transmit Data Register */ +#define AT91C_SPI1_CR ( ( AT91_REG * ) 0xFFFE4000 ) /* (SPI1) Control Register */ +#define AT91C_SPI1_CSR ( ( AT91_REG * ) 0xFFFE4030 ) /* (SPI1) Chip Select Register */ +/* ========== Register definition for PDC_SPI0 peripheral ========== */ +#define AT91C_SPI0_PTCR ( ( AT91_REG * ) 0xFFFE0120 ) /* (PDC_SPI0) PDC Transfer Control Register */ +#define AT91C_SPI0_TPR ( ( AT91_REG * ) 0xFFFE0108 ) /* (PDC_SPI0) Transmit Pointer Register */ +#define AT91C_SPI0_TCR ( ( AT91_REG * ) 0xFFFE010C ) /* (PDC_SPI0) Transmit Counter Register */ +#define AT91C_SPI0_RCR ( ( AT91_REG * ) 0xFFFE0104 ) /* (PDC_SPI0) Receive Counter Register */ +#define AT91C_SPI0_PTSR ( ( AT91_REG * ) 0xFFFE0124 ) /* (PDC_SPI0) PDC Transfer Status Register */ +#define AT91C_SPI0_RNPR ( ( AT91_REG * ) 0xFFFE0110 ) /* (PDC_SPI0) Receive Next Pointer Register */ +#define AT91C_SPI0_RPR ( ( AT91_REG * ) 0xFFFE0100 ) /* (PDC_SPI0) Receive Pointer Register */ +#define AT91C_SPI0_TNCR ( ( AT91_REG * ) 0xFFFE011C ) /* (PDC_SPI0) Transmit Next Counter Register */ +#define AT91C_SPI0_RNCR ( ( AT91_REG * ) 0xFFFE0114 ) /* (PDC_SPI0) Receive Next Counter Register */ +#define AT91C_SPI0_TNPR ( ( AT91_REG * ) 0xFFFE0118 ) /* (PDC_SPI0) Transmit Next Pointer Register */ +/* ========== Register definition for SPI0 peripheral ========== */ +#define AT91C_SPI0_IER ( ( AT91_REG * ) 0xFFFE0014 ) /* (SPI0) Interrupt Enable Register */ +#define AT91C_SPI0_SR ( ( AT91_REG * ) 0xFFFE0010 ) /* (SPI0) Status Register */ +#define AT91C_SPI0_IDR ( ( AT91_REG * ) 0xFFFE0018 ) /* (SPI0) Interrupt Disable Register */ +#define AT91C_SPI0_CR ( ( AT91_REG * ) 0xFFFE0000 ) /* (SPI0) Control Register */ +#define AT91C_SPI0_MR ( ( AT91_REG * ) 0xFFFE0004 ) /* (SPI0) Mode Register */ +#define AT91C_SPI0_IMR ( ( AT91_REG * ) 0xFFFE001C ) /* (SPI0) Interrupt Mask Register */ +#define AT91C_SPI0_TDR ( ( AT91_REG * ) 0xFFFE000C ) /* (SPI0) Transmit Data Register */ +#define AT91C_SPI0_RDR ( ( AT91_REG * ) 0xFFFE0008 ) /* (SPI0) Receive Data Register */ +#define AT91C_SPI0_CSR ( ( AT91_REG * ) 0xFFFE0030 ) /* (SPI0) Chip Select Register */ +/* ========== Register definition for PDC_US1 peripheral ========== */ +#define AT91C_US1_RNCR ( ( AT91_REG * ) 0xFFFC4114 ) /* (PDC_US1) Receive Next Counter Register */ +#define AT91C_US1_PTCR ( ( AT91_REG * ) 0xFFFC4120 ) /* (PDC_US1) PDC Transfer Control Register */ +#define AT91C_US1_TCR ( ( AT91_REG * ) 0xFFFC410C ) /* (PDC_US1) Transmit Counter Register */ +#define AT91C_US1_PTSR ( ( AT91_REG * ) 0xFFFC4124 ) /* (PDC_US1) PDC Transfer Status Register */ +#define AT91C_US1_TNPR ( ( AT91_REG * ) 0xFFFC4118 ) /* (PDC_US1) Transmit Next Pointer Register */ +#define AT91C_US1_RCR ( ( AT91_REG * ) 0xFFFC4104 ) /* (PDC_US1) Receive Counter Register */ +#define AT91C_US1_RNPR ( ( AT91_REG * ) 0xFFFC4110 ) /* (PDC_US1) Receive Next Pointer Register */ +#define AT91C_US1_RPR ( ( AT91_REG * ) 0xFFFC4100 ) /* (PDC_US1) Receive Pointer Register */ +#define AT91C_US1_TNCR ( ( AT91_REG * ) 0xFFFC411C ) /* (PDC_US1) Transmit Next Counter Register */ +#define AT91C_US1_TPR ( ( AT91_REG * ) 0xFFFC4108 ) /* (PDC_US1) Transmit Pointer Register */ +/* ========== Register definition for US1 peripheral ========== */ +#define AT91C_US1_IF ( ( AT91_REG * ) 0xFFFC404C ) /* (US1) IRDA_FILTER Register */ +#define AT91C_US1_NER ( ( AT91_REG * ) 0xFFFC4044 ) /* (US1) Nb Errors Register */ +#define AT91C_US1_RTOR ( ( AT91_REG * ) 0xFFFC4024 ) /* (US1) Receiver Time-out Register */ +#define AT91C_US1_CSR ( ( AT91_REG * ) 0xFFFC4014 ) /* (US1) Channel Status Register */ +#define AT91C_US1_IDR ( ( AT91_REG * ) 0xFFFC400C ) /* (US1) Interrupt Disable Register */ +#define AT91C_US1_IER ( ( AT91_REG * ) 0xFFFC4008 ) /* (US1) Interrupt Enable Register */ +#define AT91C_US1_THR ( ( AT91_REG * ) 0xFFFC401C ) /* (US1) Transmitter Holding Register */ +#define AT91C_US1_TTGR ( ( AT91_REG * ) 0xFFFC4028 ) /* (US1) Transmitter Time-guard Register */ +#define AT91C_US1_RHR ( ( AT91_REG * ) 0xFFFC4018 ) /* (US1) Receiver Holding Register */ +#define AT91C_US1_BRGR ( ( AT91_REG * ) 0xFFFC4020 ) /* (US1) Baud Rate Generator Register */ +#define AT91C_US1_IMR ( ( AT91_REG * ) 0xFFFC4010 ) /* (US1) Interrupt Mask Register */ +#define AT91C_US1_FIDI ( ( AT91_REG * ) 0xFFFC4040 ) /* (US1) FI_DI_Ratio Register */ +#define AT91C_US1_CR ( ( AT91_REG * ) 0xFFFC4000 ) /* (US1) Control Register */ +#define AT91C_US1_MR ( ( AT91_REG * ) 0xFFFC4004 ) /* (US1) Mode Register */ +/* ========== Register definition for PDC_US0 peripheral ========== */ +#define AT91C_US0_TNPR ( ( AT91_REG * ) 0xFFFC0118 ) /* (PDC_US0) Transmit Next Pointer Register */ +#define AT91C_US0_RNPR ( ( AT91_REG * ) 0xFFFC0110 ) /* (PDC_US0) Receive Next Pointer Register */ +#define AT91C_US0_TCR ( ( AT91_REG * ) 0xFFFC010C ) /* (PDC_US0) Transmit Counter Register */ +#define AT91C_US0_PTCR ( ( AT91_REG * ) 0xFFFC0120 ) /* (PDC_US0) PDC Transfer Control Register */ +#define AT91C_US0_PTSR ( ( AT91_REG * ) 0xFFFC0124 ) /* (PDC_US0) PDC Transfer Status Register */ +#define AT91C_US0_TNCR ( ( AT91_REG * ) 0xFFFC011C ) /* (PDC_US0) Transmit Next Counter Register */ +#define AT91C_US0_TPR ( ( AT91_REG * ) 0xFFFC0108 ) /* (PDC_US0) Transmit Pointer Register */ +#define AT91C_US0_RCR ( ( AT91_REG * ) 0xFFFC0104 ) /* (PDC_US0) Receive Counter Register */ +#define AT91C_US0_RPR ( ( AT91_REG * ) 0xFFFC0100 ) /* (PDC_US0) Receive Pointer Register */ +#define AT91C_US0_RNCR ( ( AT91_REG * ) 0xFFFC0114 ) /* (PDC_US0) Receive Next Counter Register */ +/* ========== Register definition for US0 peripheral ========== */ +#define AT91C_US0_BRGR ( ( AT91_REG * ) 0xFFFC0020 ) /* (US0) Baud Rate Generator Register */ +#define AT91C_US0_NER ( ( AT91_REG * ) 0xFFFC0044 ) /* (US0) Nb Errors Register */ +#define AT91C_US0_CR ( ( AT91_REG * ) 0xFFFC0000 ) /* (US0) Control Register */ +#define AT91C_US0_IMR ( ( AT91_REG * ) 0xFFFC0010 ) /* (US0) Interrupt Mask Register */ +#define AT91C_US0_FIDI ( ( AT91_REG * ) 0xFFFC0040 ) /* (US0) FI_DI_Ratio Register */ +#define AT91C_US0_TTGR ( ( AT91_REG * ) 0xFFFC0028 ) /* (US0) Transmitter Time-guard Register */ +#define AT91C_US0_MR ( ( AT91_REG * ) 0xFFFC0004 ) /* (US0) Mode Register */ +#define AT91C_US0_RTOR ( ( AT91_REG * ) 0xFFFC0024 ) /* (US0) Receiver Time-out Register */ +#define AT91C_US0_CSR ( ( AT91_REG * ) 0xFFFC0014 ) /* (US0) Channel Status Register */ +#define AT91C_US0_RHR ( ( AT91_REG * ) 0xFFFC0018 ) /* (US0) Receiver Holding Register */ +#define AT91C_US0_IDR ( ( AT91_REG * ) 0xFFFC000C ) /* (US0) Interrupt Disable Register */ +#define AT91C_US0_THR ( ( AT91_REG * ) 0xFFFC001C ) /* (US0) Transmitter Holding Register */ +#define AT91C_US0_IF ( ( AT91_REG * ) 0xFFFC004C ) /* (US0) IRDA_FILTER Register */ +#define AT91C_US0_IER ( ( AT91_REG * ) 0xFFFC0008 ) /* (US0) Interrupt Enable Register */ +/* ========== Register definition for PDC_SSC peripheral ========== */ +#define AT91C_SSC_TNCR ( ( AT91_REG * ) 0xFFFD411C ) /* (PDC_SSC) Transmit Next Counter Register */ +#define AT91C_SSC_RPR ( ( AT91_REG * ) 0xFFFD4100 ) /* (PDC_SSC) Receive Pointer Register */ +#define AT91C_SSC_RNCR ( ( AT91_REG * ) 0xFFFD4114 ) /* (PDC_SSC) Receive Next Counter Register */ +#define AT91C_SSC_TPR ( ( AT91_REG * ) 0xFFFD4108 ) /* (PDC_SSC) Transmit Pointer Register */ +#define AT91C_SSC_PTCR ( ( AT91_REG * ) 0xFFFD4120 ) /* (PDC_SSC) PDC Transfer Control Register */ +#define AT91C_SSC_TCR ( ( AT91_REG * ) 0xFFFD410C ) /* (PDC_SSC) Transmit Counter Register */ +#define AT91C_SSC_RCR ( ( AT91_REG * ) 0xFFFD4104 ) /* (PDC_SSC) Receive Counter Register */ +#define AT91C_SSC_RNPR ( ( AT91_REG * ) 0xFFFD4110 ) /* (PDC_SSC) Receive Next Pointer Register */ +#define AT91C_SSC_TNPR ( ( AT91_REG * ) 0xFFFD4118 ) /* (PDC_SSC) Transmit Next Pointer Register */ +#define AT91C_SSC_PTSR ( ( AT91_REG * ) 0xFFFD4124 ) /* (PDC_SSC) PDC Transfer Status Register */ +/* ========== Register definition for SSC peripheral ========== */ +#define AT91C_SSC_RHR ( ( AT91_REG * ) 0xFFFD4020 ) /* (SSC) Receive Holding Register */ +#define AT91C_SSC_RSHR ( ( AT91_REG * ) 0xFFFD4030 ) /* (SSC) Receive Sync Holding Register */ +#define AT91C_SSC_TFMR ( ( AT91_REG * ) 0xFFFD401C ) /* (SSC) Transmit Frame Mode Register */ +#define AT91C_SSC_IDR ( ( AT91_REG * ) 0xFFFD4048 ) /* (SSC) Interrupt Disable Register */ +#define AT91C_SSC_THR ( ( AT91_REG * ) 0xFFFD4024 ) /* (SSC) Transmit Holding Register */ +#define AT91C_SSC_RCMR ( ( AT91_REG * ) 0xFFFD4010 ) /* (SSC) Receive Clock ModeRegister */ +#define AT91C_SSC_IER ( ( AT91_REG * ) 0xFFFD4044 ) /* (SSC) Interrupt Enable Register */ +#define AT91C_SSC_TSHR ( ( AT91_REG * ) 0xFFFD4034 ) /* (SSC) Transmit Sync Holding Register */ +#define AT91C_SSC_SR ( ( AT91_REG * ) 0xFFFD4040 ) /* (SSC) Status Register */ +#define AT91C_SSC_CMR ( ( AT91_REG * ) 0xFFFD4004 ) /* (SSC) Clock Mode Register */ +#define AT91C_SSC_TCMR ( ( AT91_REG * ) 0xFFFD4018 ) /* (SSC) Transmit Clock Mode Register */ +#define AT91C_SSC_CR ( ( AT91_REG * ) 0xFFFD4000 ) /* (SSC) Control Register */ +#define AT91C_SSC_IMR ( ( AT91_REG * ) 0xFFFD404C ) /* (SSC) Interrupt Mask Register */ +#define AT91C_SSC_RFMR ( ( AT91_REG * ) 0xFFFD4014 ) /* (SSC) Receive Frame Mode Register */ +/* ========== Register definition for TWI peripheral ========== */ +#define AT91C_TWI_IER ( ( AT91_REG * ) 0xFFFB8024 ) /* (TWI) Interrupt Enable Register */ +#define AT91C_TWI_CR ( ( AT91_REG * ) 0xFFFB8000 ) /* (TWI) Control Register */ +#define AT91C_TWI_SR ( ( AT91_REG * ) 0xFFFB8020 ) /* (TWI) Status Register */ +#define AT91C_TWI_IMR ( ( AT91_REG * ) 0xFFFB802C ) /* (TWI) Interrupt Mask Register */ +#define AT91C_TWI_THR ( ( AT91_REG * ) 0xFFFB8034 ) /* (TWI) Transmit Holding Register */ +#define AT91C_TWI_IDR ( ( AT91_REG * ) 0xFFFB8028 ) /* (TWI) Interrupt Disable Register */ +#define AT91C_TWI_IADR ( ( AT91_REG * ) 0xFFFB800C ) /* (TWI) Internal Address Register */ +#define AT91C_TWI_MMR ( ( AT91_REG * ) 0xFFFB8004 ) /* (TWI) Master Mode Register */ +#define AT91C_TWI_CWGR ( ( AT91_REG * ) 0xFFFB8010 ) /* (TWI) Clock Waveform Generator Register */ +#define AT91C_TWI_RHR ( ( AT91_REG * ) 0xFFFB8030 ) /* (TWI) Receive Holding Register */ +/* ========== Register definition for PWMC_CH3 peripheral ========== */ +#define AT91C_PWMC_CH3_CUPDR ( ( AT91_REG * ) 0xFFFCC270 ) /* (PWMC_CH3) Channel Update Register */ +#define AT91C_PWMC_CH3_Reserved ( ( AT91_REG * ) 0xFFFCC274 ) /* (PWMC_CH3) Reserved */ +#define AT91C_PWMC_CH3_CPRDR ( ( AT91_REG * ) 0xFFFCC268 ) /* (PWMC_CH3) Channel Period Register */ +#define AT91C_PWMC_CH3_CDTYR ( ( AT91_REG * ) 0xFFFCC264 ) /* (PWMC_CH3) Channel Duty Cycle Register */ +#define AT91C_PWMC_CH3_CCNTR ( ( AT91_REG * ) 0xFFFCC26C ) /* (PWMC_CH3) Channel Counter Register */ +#define AT91C_PWMC_CH3_CMR ( ( AT91_REG * ) 0xFFFCC260 ) /* (PWMC_CH3) Channel Mode Register */ +/* ========== Register definition for PWMC_CH2 peripheral ========== */ +#define AT91C_PWMC_CH2_Reserved ( ( AT91_REG * ) 0xFFFCC254 ) /* (PWMC_CH2) Reserved */ +#define AT91C_PWMC_CH2_CMR ( ( AT91_REG * ) 0xFFFCC240 ) /* (PWMC_CH2) Channel Mode Register */ +#define AT91C_PWMC_CH2_CCNTR ( ( AT91_REG * ) 0xFFFCC24C ) /* (PWMC_CH2) Channel Counter Register */ +#define AT91C_PWMC_CH2_CPRDR ( ( AT91_REG * ) 0xFFFCC248 ) /* (PWMC_CH2) Channel Period Register */ +#define AT91C_PWMC_CH2_CUPDR ( ( AT91_REG * ) 0xFFFCC250 ) /* (PWMC_CH2) Channel Update Register */ +#define AT91C_PWMC_CH2_CDTYR ( ( AT91_REG * ) 0xFFFCC244 ) /* (PWMC_CH2) Channel Duty Cycle Register */ +/* ========== Register definition for PWMC_CH1 peripheral ========== */ +#define AT91C_PWMC_CH1_Reserved ( ( AT91_REG * ) 0xFFFCC234 ) /* (PWMC_CH1) Reserved */ +#define AT91C_PWMC_CH1_CUPDR ( ( AT91_REG * ) 0xFFFCC230 ) /* (PWMC_CH1) Channel Update Register */ +#define AT91C_PWMC_CH1_CPRDR ( ( AT91_REG * ) 0xFFFCC228 ) /* (PWMC_CH1) Channel Period Register */ +#define AT91C_PWMC_CH1_CCNTR ( ( AT91_REG * ) 0xFFFCC22C ) /* (PWMC_CH1) Channel Counter Register */ +#define AT91C_PWMC_CH1_CDTYR ( ( AT91_REG * ) 0xFFFCC224 ) /* (PWMC_CH1) Channel Duty Cycle Register */ +#define AT91C_PWMC_CH1_CMR ( ( AT91_REG * ) 0xFFFCC220 ) /* (PWMC_CH1) Channel Mode Register */ +/* ========== Register definition for PWMC_CH0 peripheral ========== */ +#define AT91C_PWMC_CH0_Reserved ( ( AT91_REG * ) 0xFFFCC214 ) /* (PWMC_CH0) Reserved */ +#define AT91C_PWMC_CH0_CPRDR ( ( AT91_REG * ) 0xFFFCC208 ) /* (PWMC_CH0) Channel Period Register */ +#define AT91C_PWMC_CH0_CDTYR ( ( AT91_REG * ) 0xFFFCC204 ) /* (PWMC_CH0) Channel Duty Cycle Register */ +#define AT91C_PWMC_CH0_CMR ( ( AT91_REG * ) 0xFFFCC200 ) /* (PWMC_CH0) Channel Mode Register */ +#define AT91C_PWMC_CH0_CUPDR ( ( AT91_REG * ) 0xFFFCC210 ) /* (PWMC_CH0) Channel Update Register */ +#define AT91C_PWMC_CH0_CCNTR ( ( AT91_REG * ) 0xFFFCC20C ) /* (PWMC_CH0) Channel Counter Register */ +/* ========== Register definition for PWMC peripheral ========== */ +#define AT91C_PWMC_IDR ( ( AT91_REG * ) 0xFFFCC014 ) /* (PWMC) PWMC Interrupt Disable Register */ +#define AT91C_PWMC_DIS ( ( AT91_REG * ) 0xFFFCC008 ) /* (PWMC) PWMC Disable Register */ +#define AT91C_PWMC_IER ( ( AT91_REG * ) 0xFFFCC010 ) /* (PWMC) PWMC Interrupt Enable Register */ +#define AT91C_PWMC_VR ( ( AT91_REG * ) 0xFFFCC0FC ) /* (PWMC) PWMC Version Register */ +#define AT91C_PWMC_ISR ( ( AT91_REG * ) 0xFFFCC01C ) /* (PWMC) PWMC Interrupt Status Register */ +#define AT91C_PWMC_SR ( ( AT91_REG * ) 0xFFFCC00C ) /* (PWMC) PWMC Status Register */ +#define AT91C_PWMC_IMR ( ( AT91_REG * ) 0xFFFCC018 ) /* (PWMC) PWMC Interrupt Mask Register */ +#define AT91C_PWMC_MR ( ( AT91_REG * ) 0xFFFCC000 ) /* (PWMC) PWMC Mode Register */ +#define AT91C_PWMC_ENA ( ( AT91_REG * ) 0xFFFCC004 ) /* (PWMC) PWMC Enable Register */ +/* ========== Register definition for UDP peripheral ========== */ +#define AT91C_UDP_IMR ( ( AT91_REG * ) 0xFFFB0018 ) /* (UDP) Interrupt Mask Register */ +#define AT91C_UDP_FADDR ( ( AT91_REG * ) 0xFFFB0008 ) /* (UDP) Function Address Register */ +#define AT91C_UDP_NUM ( ( AT91_REG * ) 0xFFFB0000 ) /* (UDP) Frame Number Register */ +#define AT91C_UDP_FDR ( ( AT91_REG * ) 0xFFFB0050 ) /* (UDP) Endpoint FIFO Data Register */ +#define AT91C_UDP_ISR ( ( AT91_REG * ) 0xFFFB001C ) /* (UDP) Interrupt Status Register */ +#define AT91C_UDP_CSR ( ( AT91_REG * ) 0xFFFB0030 ) /* (UDP) Endpoint Control and Status Register */ +#define AT91C_UDP_IDR ( ( AT91_REG * ) 0xFFFB0014 ) /* (UDP) Interrupt Disable Register */ +#define AT91C_UDP_ICR ( ( AT91_REG * ) 0xFFFB0020 ) /* (UDP) Interrupt Clear Register */ +#define AT91C_UDP_RSTEP ( ( AT91_REG * ) 0xFFFB0028 ) /* (UDP) Reset Endpoint Register */ +#define AT91C_UDP_TXVC ( ( AT91_REG * ) 0xFFFB0074 ) /* (UDP) Transceiver Control Register */ +#define AT91C_UDP_GLBSTATE ( ( AT91_REG * ) 0xFFFB0004 ) /* (UDP) Global State Register */ +#define AT91C_UDP_IER ( ( AT91_REG * ) 0xFFFB0010 ) /* (UDP) Interrupt Enable Register */ +/* ========== Register definition for TC0 peripheral ========== */ +#define AT91C_TC0_SR ( ( AT91_REG * ) 0xFFFA0020 ) /* (TC0) Status Register */ +#define AT91C_TC0_RC ( ( AT91_REG * ) 0xFFFA001C ) /* (TC0) Register C */ +#define AT91C_TC0_RB ( ( AT91_REG * ) 0xFFFA0018 ) /* (TC0) Register B */ +#define AT91C_TC0_CCR ( ( AT91_REG * ) 0xFFFA0000 ) /* (TC0) Channel Control Register */ +#define AT91C_TC0_CMR ( ( AT91_REG * ) 0xFFFA0004 ) /* (TC0) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC0_IER ( ( AT91_REG * ) 0xFFFA0024 ) /* (TC0) Interrupt Enable Register */ +#define AT91C_TC0_RA ( ( AT91_REG * ) 0xFFFA0014 ) /* (TC0) Register A */ +#define AT91C_TC0_IDR ( ( AT91_REG * ) 0xFFFA0028 ) /* (TC0) Interrupt Disable Register */ +#define AT91C_TC0_CV ( ( AT91_REG * ) 0xFFFA0010 ) /* (TC0) Counter Value */ +#define AT91C_TC0_IMR ( ( AT91_REG * ) 0xFFFA002C ) /* (TC0) Interrupt Mask Register */ +/* ========== Register definition for TC1 peripheral ========== */ +#define AT91C_TC1_RB ( ( AT91_REG * ) 0xFFFA0058 ) /* (TC1) Register B */ +#define AT91C_TC1_CCR ( ( AT91_REG * ) 0xFFFA0040 ) /* (TC1) Channel Control Register */ +#define AT91C_TC1_IER ( ( AT91_REG * ) 0xFFFA0064 ) /* (TC1) Interrupt Enable Register */ +#define AT91C_TC1_IDR ( ( AT91_REG * ) 0xFFFA0068 ) /* (TC1) Interrupt Disable Register */ +#define AT91C_TC1_SR ( ( AT91_REG * ) 0xFFFA0060 ) /* (TC1) Status Register */ +#define AT91C_TC1_CMR ( ( AT91_REG * ) 0xFFFA0044 ) /* (TC1) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC1_RA ( ( AT91_REG * ) 0xFFFA0054 ) /* (TC1) Register A */ +#define AT91C_TC1_RC ( ( AT91_REG * ) 0xFFFA005C ) /* (TC1) Register C */ +#define AT91C_TC1_IMR ( ( AT91_REG * ) 0xFFFA006C ) /* (TC1) Interrupt Mask Register */ +#define AT91C_TC1_CV ( ( AT91_REG * ) 0xFFFA0050 ) /* (TC1) Counter Value */ +/* ========== Register definition for TC2 peripheral ========== */ +#define AT91C_TC2_CMR ( ( AT91_REG * ) 0xFFFA0084 ) /* (TC2) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC2_CCR ( ( AT91_REG * ) 0xFFFA0080 ) /* (TC2) Channel Control Register */ +#define AT91C_TC2_CV ( ( AT91_REG * ) 0xFFFA0090 ) /* (TC2) Counter Value */ +#define AT91C_TC2_RA ( ( AT91_REG * ) 0xFFFA0094 ) /* (TC2) Register A */ +#define AT91C_TC2_RB ( ( AT91_REG * ) 0xFFFA0098 ) /* (TC2) Register B */ +#define AT91C_TC2_IDR ( ( AT91_REG * ) 0xFFFA00A8 ) /* (TC2) Interrupt Disable Register */ +#define AT91C_TC2_IMR ( ( AT91_REG * ) 0xFFFA00AC ) /* (TC2) Interrupt Mask Register */ +#define AT91C_TC2_RC ( ( AT91_REG * ) 0xFFFA009C ) /* (TC2) Register C */ +#define AT91C_TC2_IER ( ( AT91_REG * ) 0xFFFA00A4 ) /* (TC2) Interrupt Enable Register */ +#define AT91C_TC2_SR ( ( AT91_REG * ) 0xFFFA00A0 ) /* (TC2) Status Register */ +/* ========== Register definition for TCB peripheral ========== */ +#define AT91C_TCB_BMR ( ( AT91_REG * ) 0xFFFA00C4 ) /* (TCB) TC Block Mode Register */ +#define AT91C_TCB_BCR ( ( AT91_REG * ) 0xFFFA00C0 ) /* (TCB) TC Block Control Register */ +/* ========== Register definition for CAN_MB0 peripheral ========== */ +#define AT91C_CAN_MB0_MDL ( ( AT91_REG * ) 0xFFFD0214 ) /* (CAN_MB0) MailBox Data Low Register */ +#define AT91C_CAN_MB0_MAM ( ( AT91_REG * ) 0xFFFD0204 ) /* (CAN_MB0) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB0_MCR ( ( AT91_REG * ) 0xFFFD021C ) /* (CAN_MB0) MailBox Control Register */ +#define AT91C_CAN_MB0_MID ( ( AT91_REG * ) 0xFFFD0208 ) /* (CAN_MB0) MailBox ID Register */ +#define AT91C_CAN_MB0_MSR ( ( AT91_REG * ) 0xFFFD0210 ) /* (CAN_MB0) MailBox Status Register */ +#define AT91C_CAN_MB0_MFID ( ( AT91_REG * ) 0xFFFD020C ) /* (CAN_MB0) MailBox Family ID Register */ +#define AT91C_CAN_MB0_MDH ( ( AT91_REG * ) 0xFFFD0218 ) /* (CAN_MB0) MailBox Data High Register */ +#define AT91C_CAN_MB0_MMR ( ( AT91_REG * ) 0xFFFD0200 ) /* (CAN_MB0) MailBox Mode Register */ +/* ========== Register definition for CAN_MB1 peripheral ========== */ +#define AT91C_CAN_MB1_MDL ( ( AT91_REG * ) 0xFFFD0234 ) /* (CAN_MB1) MailBox Data Low Register */ +#define AT91C_CAN_MB1_MID ( ( AT91_REG * ) 0xFFFD0228 ) /* (CAN_MB1) MailBox ID Register */ +#define AT91C_CAN_MB1_MMR ( ( AT91_REG * ) 0xFFFD0220 ) /* (CAN_MB1) MailBox Mode Register */ +#define AT91C_CAN_MB1_MSR ( ( AT91_REG * ) 0xFFFD0230 ) /* (CAN_MB1) MailBox Status Register */ +#define AT91C_CAN_MB1_MAM ( ( AT91_REG * ) 0xFFFD0224 ) /* (CAN_MB1) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB1_MDH ( ( AT91_REG * ) 0xFFFD0238 ) /* (CAN_MB1) MailBox Data High Register */ +#define AT91C_CAN_MB1_MCR ( ( AT91_REG * ) 0xFFFD023C ) /* (CAN_MB1) MailBox Control Register */ +#define AT91C_CAN_MB1_MFID ( ( AT91_REG * ) 0xFFFD022C ) /* (CAN_MB1) MailBox Family ID Register */ +/* ========== Register definition for CAN_MB2 peripheral ========== */ +#define AT91C_CAN_MB2_MCR ( ( AT91_REG * ) 0xFFFD025C ) /* (CAN_MB2) MailBox Control Register */ +#define AT91C_CAN_MB2_MDH ( ( AT91_REG * ) 0xFFFD0258 ) /* (CAN_MB2) MailBox Data High Register */ +#define AT91C_CAN_MB2_MID ( ( AT91_REG * ) 0xFFFD0248 ) /* (CAN_MB2) MailBox ID Register */ +#define AT91C_CAN_MB2_MDL ( ( AT91_REG * ) 0xFFFD0254 ) /* (CAN_MB2) MailBox Data Low Register */ +#define AT91C_CAN_MB2_MMR ( ( AT91_REG * ) 0xFFFD0240 ) /* (CAN_MB2) MailBox Mode Register */ +#define AT91C_CAN_MB2_MAM ( ( AT91_REG * ) 0xFFFD0244 ) /* (CAN_MB2) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB2_MFID ( ( AT91_REG * ) 0xFFFD024C ) /* (CAN_MB2) MailBox Family ID Register */ +#define AT91C_CAN_MB2_MSR ( ( AT91_REG * ) 0xFFFD0250 ) /* (CAN_MB2) MailBox Status Register */ +/* ========== Register definition for CAN_MB3 peripheral ========== */ +#define AT91C_CAN_MB3_MFID ( ( AT91_REG * ) 0xFFFD026C ) /* (CAN_MB3) MailBox Family ID Register */ +#define AT91C_CAN_MB3_MAM ( ( AT91_REG * ) 0xFFFD0264 ) /* (CAN_MB3) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB3_MID ( ( AT91_REG * ) 0xFFFD0268 ) /* (CAN_MB3) MailBox ID Register */ +#define AT91C_CAN_MB3_MCR ( ( AT91_REG * ) 0xFFFD027C ) /* (CAN_MB3) MailBox Control Register */ +#define AT91C_CAN_MB3_MMR ( ( AT91_REG * ) 0xFFFD0260 ) /* (CAN_MB3) MailBox Mode Register */ +#define AT91C_CAN_MB3_MSR ( ( AT91_REG * ) 0xFFFD0270 ) /* (CAN_MB3) MailBox Status Register */ +#define AT91C_CAN_MB3_MDL ( ( AT91_REG * ) 0xFFFD0274 ) /* (CAN_MB3) MailBox Data Low Register */ +#define AT91C_CAN_MB3_MDH ( ( AT91_REG * ) 0xFFFD0278 ) /* (CAN_MB3) MailBox Data High Register */ +/* ========== Register definition for CAN_MB4 peripheral ========== */ +#define AT91C_CAN_MB4_MID ( ( AT91_REG * ) 0xFFFD0288 ) /* (CAN_MB4) MailBox ID Register */ +#define AT91C_CAN_MB4_MMR ( ( AT91_REG * ) 0xFFFD0280 ) /* (CAN_MB4) MailBox Mode Register */ +#define AT91C_CAN_MB4_MDH ( ( AT91_REG * ) 0xFFFD0298 ) /* (CAN_MB4) MailBox Data High Register */ +#define AT91C_CAN_MB4_MFID ( ( AT91_REG * ) 0xFFFD028C ) /* (CAN_MB4) MailBox Family ID Register */ +#define AT91C_CAN_MB4_MSR ( ( AT91_REG * ) 0xFFFD0290 ) /* (CAN_MB4) MailBox Status Register */ +#define AT91C_CAN_MB4_MCR ( ( AT91_REG * ) 0xFFFD029C ) /* (CAN_MB4) MailBox Control Register */ +#define AT91C_CAN_MB4_MDL ( ( AT91_REG * ) 0xFFFD0294 ) /* (CAN_MB4) MailBox Data Low Register */ +#define AT91C_CAN_MB4_MAM ( ( AT91_REG * ) 0xFFFD0284 ) /* (CAN_MB4) MailBox Acceptance Mask Register */ +/* ========== Register definition for CAN_MB5 peripheral ========== */ +#define AT91C_CAN_MB5_MSR ( ( AT91_REG * ) 0xFFFD02B0 ) /* (CAN_MB5) MailBox Status Register */ +#define AT91C_CAN_MB5_MCR ( ( AT91_REG * ) 0xFFFD02BC ) /* (CAN_MB5) MailBox Control Register */ +#define AT91C_CAN_MB5_MFID ( ( AT91_REG * ) 0xFFFD02AC ) /* (CAN_MB5) MailBox Family ID Register */ +#define AT91C_CAN_MB5_MDH ( ( AT91_REG * ) 0xFFFD02B8 ) /* (CAN_MB5) MailBox Data High Register */ +#define AT91C_CAN_MB5_MID ( ( AT91_REG * ) 0xFFFD02A8 ) /* (CAN_MB5) MailBox ID Register */ +#define AT91C_CAN_MB5_MMR ( ( AT91_REG * ) 0xFFFD02A0 ) /* (CAN_MB5) MailBox Mode Register */ +#define AT91C_CAN_MB5_MDL ( ( AT91_REG * ) 0xFFFD02B4 ) /* (CAN_MB5) MailBox Data Low Register */ +#define AT91C_CAN_MB5_MAM ( ( AT91_REG * ) 0xFFFD02A4 ) /* (CAN_MB5) MailBox Acceptance Mask Register */ +/* ========== Register definition for CAN_MB6 peripheral ========== */ +#define AT91C_CAN_MB6_MFID ( ( AT91_REG * ) 0xFFFD02CC ) /* (CAN_MB6) MailBox Family ID Register */ +#define AT91C_CAN_MB6_MID ( ( AT91_REG * ) 0xFFFD02C8 ) /* (CAN_MB6) MailBox ID Register */ +#define AT91C_CAN_MB6_MAM ( ( AT91_REG * ) 0xFFFD02C4 ) /* (CAN_MB6) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB6_MSR ( ( AT91_REG * ) 0xFFFD02D0 ) /* (CAN_MB6) MailBox Status Register */ +#define AT91C_CAN_MB6_MDL ( ( AT91_REG * ) 0xFFFD02D4 ) /* (CAN_MB6) MailBox Data Low Register */ +#define AT91C_CAN_MB6_MCR ( ( AT91_REG * ) 0xFFFD02DC ) /* (CAN_MB6) MailBox Control Register */ +#define AT91C_CAN_MB6_MDH ( ( AT91_REG * ) 0xFFFD02D8 ) /* (CAN_MB6) MailBox Data High Register */ +#define AT91C_CAN_MB6_MMR ( ( AT91_REG * ) 0xFFFD02C0 ) /* (CAN_MB6) MailBox Mode Register */ +/* ========== Register definition for CAN_MB7 peripheral ========== */ +#define AT91C_CAN_MB7_MCR ( ( AT91_REG * ) 0xFFFD02FC ) /* (CAN_MB7) MailBox Control Register */ +#define AT91C_CAN_MB7_MDH ( ( AT91_REG * ) 0xFFFD02F8 ) /* (CAN_MB7) MailBox Data High Register */ +#define AT91C_CAN_MB7_MFID ( ( AT91_REG * ) 0xFFFD02EC ) /* (CAN_MB7) MailBox Family ID Register */ +#define AT91C_CAN_MB7_MDL ( ( AT91_REG * ) 0xFFFD02F4 ) /* (CAN_MB7) MailBox Data Low Register */ +#define AT91C_CAN_MB7_MID ( ( AT91_REG * ) 0xFFFD02E8 ) /* (CAN_MB7) MailBox ID Register */ +#define AT91C_CAN_MB7_MMR ( ( AT91_REG * ) 0xFFFD02E0 ) /* (CAN_MB7) MailBox Mode Register */ +#define AT91C_CAN_MB7_MAM ( ( AT91_REG * ) 0xFFFD02E4 ) /* (CAN_MB7) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB7_MSR ( ( AT91_REG * ) 0xFFFD02F0 ) /* (CAN_MB7) MailBox Status Register */ +/* ========== Register definition for CAN peripheral ========== */ +#define AT91C_CAN_TCR ( ( AT91_REG * ) 0xFFFD0024 ) /* (CAN) Transfer Command Register */ +#define AT91C_CAN_IMR ( ( AT91_REG * ) 0xFFFD000C ) /* (CAN) Interrupt Mask Register */ +#define AT91C_CAN_IER ( ( AT91_REG * ) 0xFFFD0004 ) /* (CAN) Interrupt Enable Register */ +#define AT91C_CAN_ECR ( ( AT91_REG * ) 0xFFFD0020 ) /* (CAN) Error Counter Register */ +#define AT91C_CAN_TIMESTP ( ( AT91_REG * ) 0xFFFD001C ) /* (CAN) Time Stamp Register */ +#define AT91C_CAN_MR ( ( AT91_REG * ) 0xFFFD0000 ) /* (CAN) Mode Register */ +#define AT91C_CAN_IDR ( ( AT91_REG * ) 0xFFFD0008 ) /* (CAN) Interrupt Disable Register */ +#define AT91C_CAN_ACR ( ( AT91_REG * ) 0xFFFD0028 ) /* (CAN) Abort Command Register */ +#define AT91C_CAN_TIM ( ( AT91_REG * ) 0xFFFD0018 ) /* (CAN) Timer Register */ +#define AT91C_CAN_SR ( ( AT91_REG * ) 0xFFFD0010 ) /* (CAN) Status Register */ +#define AT91C_CAN_BR ( ( AT91_REG * ) 0xFFFD0014 ) /* (CAN) Baudrate Register */ +#define AT91C_CAN_VR ( ( AT91_REG * ) 0xFFFD00FC ) /* (CAN) Version Register */ +/* ========== Register definition for EMAC peripheral ========== */ +#define AT91C_EMAC_ISR ( ( AT91_REG * ) 0xFFFDC024 ) /* (EMAC) Interrupt Status Register */ +#define AT91C_EMAC_SA4H ( ( AT91_REG * ) 0xFFFDC0B4 ) /* (EMAC) Specific Address 4 Top, Last 2 bytes */ +#define AT91C_EMAC_SA1L ( ( AT91_REG * ) 0xFFFDC098 ) /* (EMAC) Specific Address 1 Bottom, First 4 bytes */ +#define AT91C_EMAC_ELE ( ( AT91_REG * ) 0xFFFDC078 ) /* (EMAC) Excessive Length Errors Register */ +#define AT91C_EMAC_LCOL ( ( AT91_REG * ) 0xFFFDC05C ) /* (EMAC) Late Collision Register */ +#define AT91C_EMAC_RLE ( ( AT91_REG * ) 0xFFFDC088 ) /* (EMAC) Receive Length Field Mismatch Register */ +#define AT91C_EMAC_WOL ( ( AT91_REG * ) 0xFFFDC0C4 ) /* (EMAC) Wake On LAN Register */ +#define AT91C_EMAC_DTF ( ( AT91_REG * ) 0xFFFDC058 ) /* (EMAC) Deferred Transmission Frame Register */ +#define AT91C_EMAC_TUND ( ( AT91_REG * ) 0xFFFDC064 ) /* (EMAC) Transmit Underrun Error Register */ +#define AT91C_EMAC_NCR ( ( AT91_REG * ) 0xFFFDC000 ) /* (EMAC) Network Control Register */ +#define AT91C_EMAC_SA4L ( ( AT91_REG * ) 0xFFFDC0B0 ) /* (EMAC) Specific Address 4 Bottom, First 4 bytes */ +#define AT91C_EMAC_RSR ( ( AT91_REG * ) 0xFFFDC020 ) /* (EMAC) Receive Status Register */ +#define AT91C_EMAC_SA3L ( ( AT91_REG * ) 0xFFFDC0A8 ) /* (EMAC) Specific Address 3 Bottom, First 4 bytes */ +#define AT91C_EMAC_TSR ( ( AT91_REG * ) 0xFFFDC014 ) /* (EMAC) Transmit Status Register */ +#define AT91C_EMAC_IDR ( ( AT91_REG * ) 0xFFFDC02C ) /* (EMAC) Interrupt Disable Register */ +#define AT91C_EMAC_RSE ( ( AT91_REG * ) 0xFFFDC074 ) /* (EMAC) Receive Symbol Errors Register */ +#define AT91C_EMAC_ECOL ( ( AT91_REG * ) 0xFFFDC060 ) /* (EMAC) Excessive Collision Register */ +#define AT91C_EMAC_TID ( ( AT91_REG * ) 0xFFFDC0B8 ) /* (EMAC) Type ID Checking Register */ +#define AT91C_EMAC_HRB ( ( AT91_REG * ) 0xFFFDC090 ) /* (EMAC) Hash Address Bottom[31:0] */ +#define AT91C_EMAC_TBQP ( ( AT91_REG * ) 0xFFFDC01C ) /* (EMAC) Transmit Buffer Queue Pointer */ +#define AT91C_EMAC_USRIO ( ( AT91_REG * ) 0xFFFDC0C0 ) /* (EMAC) USER Input/Output Register */ +#define AT91C_EMAC_PTR ( ( AT91_REG * ) 0xFFFDC038 ) /* (EMAC) Pause Time Register */ +#define AT91C_EMAC_SA2H ( ( AT91_REG * ) 0xFFFDC0A4 ) /* (EMAC) Specific Address 2 Top, Last 2 bytes */ +#define AT91C_EMAC_ROV ( ( AT91_REG * ) 0xFFFDC070 ) /* (EMAC) Receive Overrun Errors Register */ +#define AT91C_EMAC_ALE ( ( AT91_REG * ) 0xFFFDC054 ) /* (EMAC) Alignment Error Register */ +#define AT91C_EMAC_RJA ( ( AT91_REG * ) 0xFFFDC07C ) /* (EMAC) Receive Jabbers Register */ +#define AT91C_EMAC_RBQP ( ( AT91_REG * ) 0xFFFDC018 ) /* (EMAC) Receive Buffer Queue Pointer */ +#define AT91C_EMAC_TPF ( ( AT91_REG * ) 0xFFFDC08C ) /* (EMAC) Transmitted Pause Frames Register */ +#define AT91C_EMAC_NCFGR ( ( AT91_REG * ) 0xFFFDC004 ) /* (EMAC) Network Configuration Register */ +#define AT91C_EMAC_HRT ( ( AT91_REG * ) 0xFFFDC094 ) /* (EMAC) Hash Address Top[63:32] */ +#define AT91C_EMAC_USF ( ( AT91_REG * ) 0xFFFDC080 ) /* (EMAC) Undersize Frames Register */ +#define AT91C_EMAC_FCSE ( ( AT91_REG * ) 0xFFFDC050 ) /* (EMAC) Frame Check Sequence Error Register */ +#define AT91C_EMAC_TPQ ( ( AT91_REG * ) 0xFFFDC0BC ) /* (EMAC) Transmit Pause Quantum Register */ +#define AT91C_EMAC_MAN ( ( AT91_REG * ) 0xFFFDC034 ) /* (EMAC) PHY Maintenance Register */ +#define AT91C_EMAC_FTO ( ( AT91_REG * ) 0xFFFDC040 ) /* (EMAC) Frames Transmitted OK Register */ +#define AT91C_EMAC_REV ( ( AT91_REG * ) 0xFFFDC0FC ) /* (EMAC) Revision Register */ +#define AT91C_EMAC_IMR ( ( AT91_REG * ) 0xFFFDC030 ) /* (EMAC) Interrupt Mask Register */ +#define AT91C_EMAC_SCF ( ( AT91_REG * ) 0xFFFDC044 ) /* (EMAC) Single Collision Frame Register */ +#define AT91C_EMAC_PFR ( ( AT91_REG * ) 0xFFFDC03C ) /* (EMAC) Pause Frames received Register */ +#define AT91C_EMAC_MCF ( ( AT91_REG * ) 0xFFFDC048 ) /* (EMAC) Multiple Collision Frame Register */ +#define AT91C_EMAC_NSR ( ( AT91_REG * ) 0xFFFDC008 ) /* (EMAC) Network Status Register */ +#define AT91C_EMAC_SA2L ( ( AT91_REG * ) 0xFFFDC0A0 ) /* (EMAC) Specific Address 2 Bottom, First 4 bytes */ +#define AT91C_EMAC_FRO ( ( AT91_REG * ) 0xFFFDC04C ) /* (EMAC) Frames Received OK Register */ +#define AT91C_EMAC_IER ( ( AT91_REG * ) 0xFFFDC028 ) /* (EMAC) Interrupt Enable Register */ +#define AT91C_EMAC_SA1H ( ( AT91_REG * ) 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */ +#define AT91C_EMAC_CSE ( ( AT91_REG * ) 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */ +#define AT91C_EMAC_SA3H ( ( AT91_REG * ) 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */ +#define AT91C_EMAC_RRE ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Resource Error Register */ +#define AT91C_EMAC_STE ( ( AT91_REG * ) 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */ +/* ========== Register definition for PDC_ADC peripheral ========== */ +#define AT91C_ADC_PTSR ( ( AT91_REG * ) 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */ +#define AT91C_ADC_PTCR ( ( AT91_REG * ) 0xFFFD8120 ) /* (PDC_ADC) PDC Transfer Control Register */ +#define AT91C_ADC_TNPR ( ( AT91_REG * ) 0xFFFD8118 ) /* (PDC_ADC) Transmit Next Pointer Register */ +#define AT91C_ADC_TNCR ( ( AT91_REG * ) 0xFFFD811C ) /* (PDC_ADC) Transmit Next Counter Register */ +#define AT91C_ADC_RNPR ( ( AT91_REG * ) 0xFFFD8110 ) /* (PDC_ADC) Receive Next Pointer Register */ +#define AT91C_ADC_RNCR ( ( AT91_REG * ) 0xFFFD8114 ) /* (PDC_ADC) Receive Next Counter Register */ +#define AT91C_ADC_RPR ( ( AT91_REG * ) 0xFFFD8100 ) /* (PDC_ADC) Receive Pointer Register */ +#define AT91C_ADC_TCR ( ( AT91_REG * ) 0xFFFD810C ) /* (PDC_ADC) Transmit Counter Register */ +#define AT91C_ADC_TPR ( ( AT91_REG * ) 0xFFFD8108 ) /* (PDC_ADC) Transmit Pointer Register */ +#define AT91C_ADC_RCR ( ( AT91_REG * ) 0xFFFD8104 ) /* (PDC_ADC) Receive Counter Register */ +/* ========== Register definition for ADC peripheral ========== */ +#define AT91C_ADC_CDR2 ( ( AT91_REG * ) 0xFFFD8038 ) /* (ADC) ADC Channel Data Register 2 */ +#define AT91C_ADC_CDR3 ( ( AT91_REG * ) 0xFFFD803C ) /* (ADC) ADC Channel Data Register 3 */ +#define AT91C_ADC_CDR0 ( ( AT91_REG * ) 0xFFFD8030 ) /* (ADC) ADC Channel Data Register 0 */ +#define AT91C_ADC_CDR5 ( ( AT91_REG * ) 0xFFFD8044 ) /* (ADC) ADC Channel Data Register 5 */ +#define AT91C_ADC_CHDR ( ( AT91_REG * ) 0xFFFD8014 ) /* (ADC) ADC Channel Disable Register */ +#define AT91C_ADC_SR ( ( AT91_REG * ) 0xFFFD801C ) /* (ADC) ADC Status Register */ +#define AT91C_ADC_CDR4 ( ( AT91_REG * ) 0xFFFD8040 ) /* (ADC) ADC Channel Data Register 4 */ +#define AT91C_ADC_CDR1 ( ( AT91_REG * ) 0xFFFD8034 ) /* (ADC) ADC Channel Data Register 1 */ +#define AT91C_ADC_LCDR ( ( AT91_REG * ) 0xFFFD8020 ) /* (ADC) ADC Last Converted Data Register */ +#define AT91C_ADC_IDR ( ( AT91_REG * ) 0xFFFD8028 ) /* (ADC) ADC Interrupt Disable Register */ +#define AT91C_ADC_CR ( ( AT91_REG * ) 0xFFFD8000 ) /* (ADC) ADC Control Register */ +#define AT91C_ADC_CDR7 ( ( AT91_REG * ) 0xFFFD804C ) /* (ADC) ADC Channel Data Register 7 */ +#define AT91C_ADC_CDR6 ( ( AT91_REG * ) 0xFFFD8048 ) /* (ADC) ADC Channel Data Register 6 */ +#define AT91C_ADC_IER ( ( AT91_REG * ) 0xFFFD8024 ) /* (ADC) ADC Interrupt Enable Register */ +#define AT91C_ADC_CHER ( ( AT91_REG * ) 0xFFFD8010 ) /* (ADC) ADC Channel Enable Register */ +#define AT91C_ADC_CHSR ( ( AT91_REG * ) 0xFFFD8018 ) /* (ADC) ADC Channel Status Register */ +#define AT91C_ADC_MR ( ( AT91_REG * ) 0xFFFD8004 ) /* (ADC) ADC Mode Register */ +#define AT91C_ADC_IMR ( ( AT91_REG * ) 0xFFFD802C ) /* (ADC) ADC Interrupt Mask Register */ +/* ========== Register definition for PDC_AES peripheral ========== */ +#define AT91C_AES_TPR ( ( AT91_REG * ) 0xFFFA4108 ) /* (PDC_AES) Transmit Pointer Register */ +#define AT91C_AES_PTCR ( ( AT91_REG * ) 0xFFFA4120 ) /* (PDC_AES) PDC Transfer Control Register */ +#define AT91C_AES_RNPR ( ( AT91_REG * ) 0xFFFA4110 ) /* (PDC_AES) Receive Next Pointer Register */ +#define AT91C_AES_TNCR ( ( AT91_REG * ) 0xFFFA411C ) /* (PDC_AES) Transmit Next Counter Register */ +#define AT91C_AES_TCR ( ( AT91_REG * ) 0xFFFA410C ) /* (PDC_AES) Transmit Counter Register */ +#define AT91C_AES_RCR ( ( AT91_REG * ) 0xFFFA4104 ) /* (PDC_AES) Receive Counter Register */ +#define AT91C_AES_RNCR ( ( AT91_REG * ) 0xFFFA4114 ) /* (PDC_AES) Receive Next Counter Register */ +#define AT91C_AES_TNPR ( ( AT91_REG * ) 0xFFFA4118 ) /* (PDC_AES) Transmit Next Pointer Register */ +#define AT91C_AES_RPR ( ( AT91_REG * ) 0xFFFA4100 ) /* (PDC_AES) Receive Pointer Register */ +#define AT91C_AES_PTSR ( ( AT91_REG * ) 0xFFFA4124 ) /* (PDC_AES) PDC Transfer Status Register */ +/* ========== Register definition for AES peripheral ========== */ +#define AT91C_AES_IVxR ( ( AT91_REG * ) 0xFFFA4060 ) /* (AES) Initialization Vector x Register */ +#define AT91C_AES_MR ( ( AT91_REG * ) 0xFFFA4004 ) /* (AES) Mode Register */ +#define AT91C_AES_VR ( ( AT91_REG * ) 0xFFFA40FC ) /* (AES) AES Version Register */ +#define AT91C_AES_ODATAxR ( ( AT91_REG * ) 0xFFFA4050 ) /* (AES) Output Data x Register */ +#define AT91C_AES_IDATAxR ( ( AT91_REG * ) 0xFFFA4040 ) /* (AES) Input Data x Register */ +#define AT91C_AES_CR ( ( AT91_REG * ) 0xFFFA4000 ) /* (AES) Control Register */ +#define AT91C_AES_IDR ( ( AT91_REG * ) 0xFFFA4014 ) /* (AES) Interrupt Disable Register */ +#define AT91C_AES_IMR ( ( AT91_REG * ) 0xFFFA4018 ) /* (AES) Interrupt Mask Register */ +#define AT91C_AES_IER ( ( AT91_REG * ) 0xFFFA4010 ) /* (AES) Interrupt Enable Register */ +#define AT91C_AES_KEYWxR ( ( AT91_REG * ) 0xFFFA4020 ) /* (AES) Key Word x Register */ +#define AT91C_AES_ISR ( ( AT91_REG * ) 0xFFFA401C ) /* (AES) Interrupt Status Register */ +/* ========== Register definition for PDC_TDES peripheral ========== */ +#define AT91C_TDES_RNCR ( ( AT91_REG * ) 0xFFFA8114 ) /* (PDC_TDES) Receive Next Counter Register */ +#define AT91C_TDES_TCR ( ( AT91_REG * ) 0xFFFA810C ) /* (PDC_TDES) Transmit Counter Register */ +#define AT91C_TDES_RCR ( ( AT91_REG * ) 0xFFFA8104 ) /* (PDC_TDES) Receive Counter Register */ +#define AT91C_TDES_TNPR ( ( AT91_REG * ) 0xFFFA8118 ) /* (PDC_TDES) Transmit Next Pointer Register */ +#define AT91C_TDES_RNPR ( ( AT91_REG * ) 0xFFFA8110 ) /* (PDC_TDES) Receive Next Pointer Register */ +#define AT91C_TDES_RPR ( ( AT91_REG * ) 0xFFFA8100 ) /* (PDC_TDES) Receive Pointer Register */ +#define AT91C_TDES_TNCR ( ( AT91_REG * ) 0xFFFA811C ) /* (PDC_TDES) Transmit Next Counter Register */ +#define AT91C_TDES_TPR ( ( AT91_REG * ) 0xFFFA8108 ) /* (PDC_TDES) Transmit Pointer Register */ +#define AT91C_TDES_PTSR ( ( AT91_REG * ) 0xFFFA8124 ) /* (PDC_TDES) PDC Transfer Status Register */ +#define AT91C_TDES_PTCR ( ( AT91_REG * ) 0xFFFA8120 ) /* (PDC_TDES) PDC Transfer Control Register */ +/* ========== Register definition for TDES peripheral ========== */ +#define AT91C_TDES_KEY2WxR ( ( AT91_REG * ) 0xFFFA8028 ) /* (TDES) Key 2 Word x Register */ +#define AT91C_TDES_KEY3WxR ( ( AT91_REG * ) 0xFFFA8030 ) /* (TDES) Key 3 Word x Register */ +#define AT91C_TDES_IDR ( ( AT91_REG * ) 0xFFFA8014 ) /* (TDES) Interrupt Disable Register */ +#define AT91C_TDES_VR ( ( AT91_REG * ) 0xFFFA80FC ) /* (TDES) TDES Version Register */ +#define AT91C_TDES_IVxR ( ( AT91_REG * ) 0xFFFA8060 ) /* (TDES) Initialization Vector x Register */ +#define AT91C_TDES_ODATAxR ( ( AT91_REG * ) 0xFFFA8050 ) /* (TDES) Output Data x Register */ +#define AT91C_TDES_IMR ( ( AT91_REG * ) 0xFFFA8018 ) /* (TDES) Interrupt Mask Register */ +#define AT91C_TDES_MR ( ( AT91_REG * ) 0xFFFA8004 ) /* (TDES) Mode Register */ +#define AT91C_TDES_CR ( ( AT91_REG * ) 0xFFFA8000 ) /* (TDES) Control Register */ +#define AT91C_TDES_IER ( ( AT91_REG * ) 0xFFFA8010 ) /* (TDES) Interrupt Enable Register */ +#define AT91C_TDES_ISR ( ( AT91_REG * ) 0xFFFA801C ) /* (TDES) Interrupt Status Register */ +#define AT91C_TDES_IDATAxR ( ( AT91_REG * ) 0xFFFA8040 ) /* (TDES) Input Data x Register */ +#define AT91C_TDES_KEY1WxR ( ( AT91_REG * ) 0xFFFA8020 ) /* (TDES) Key 1 Word x Register */ + +/* ***************************************************************************** */ +/* PIO DEFINITIONS FOR AT91SAM7X256 */ +/* ***************************************************************************** */ +#define AT91C_PIO_PA0 ( ( unsigned int ) 1 << 0 ) /* Pin Controlled by PA0 */ +#define AT91C_PA0_RXD0 ( ( unsigned int ) AT91C_PIO_PA0 ) /* USART 0 Receive Data */ +#define AT91C_PIO_PA1 ( ( unsigned int ) 1 << 1 ) /* Pin Controlled by PA1 */ +#define AT91C_PA1_TXD0 ( ( unsigned int ) AT91C_PIO_PA1 ) /* USART 0 Transmit Data */ +#define AT91C_PIO_PA10 ( ( unsigned int ) 1 << 10 ) /* Pin Controlled by PA10 */ +#define AT91C_PA10_TWD ( ( unsigned int ) AT91C_PIO_PA10 ) /* TWI Two-wire Serial Data */ +#define AT91C_PIO_PA11 ( ( unsigned int ) 1 << 11 ) /* Pin Controlled by PA11 */ +#define AT91C_PA11_TWCK ( ( unsigned int ) AT91C_PIO_PA11 ) /* TWI Two-wire Serial Clock */ +#define AT91C_PIO_PA12 ( ( unsigned int ) 1 << 12 ) /* Pin Controlled by PA12 */ +#define AT91C_PA12_NPCS00 ( ( unsigned int ) AT91C_PIO_PA12 ) /* SPI 0 Peripheral Chip Select 0 */ +#define AT91C_PIO_PA13 ( ( unsigned int ) 1 << 13 ) /* Pin Controlled by PA13 */ +#define AT91C_PA13_NPCS01 ( ( unsigned int ) AT91C_PIO_PA13 ) /* SPI 0 Peripheral Chip Select 1 */ +#define AT91C_PA13_PCK1 ( ( unsigned int ) AT91C_PIO_PA13 ) /* PMC Programmable Clock Output 1 */ +#define AT91C_PIO_PA14 ( ( unsigned int ) 1 << 14 ) /* Pin Controlled by PA14 */ +#define AT91C_PA14_NPCS02 ( ( unsigned int ) AT91C_PIO_PA14 ) /* SPI 0 Peripheral Chip Select 2 */ +#define AT91C_PA14_IRQ1 ( ( unsigned int ) AT91C_PIO_PA14 ) /* External Interrupt 1 */ +#define AT91C_PIO_PA15 ( ( unsigned int ) 1 << 15 ) /* Pin Controlled by PA15 */ +#define AT91C_PA15_NPCS03 ( ( unsigned int ) AT91C_PIO_PA15 ) /* SPI 0 Peripheral Chip Select 3 */ +#define AT91C_PA15_TCLK2 ( ( unsigned int ) AT91C_PIO_PA15 ) /* Timer Counter 2 external clock input */ +#define AT91C_PIO_PA16 ( ( unsigned int ) 1 << 16 ) /* Pin Controlled by PA16 */ +#define AT91C_PA16_MISO0 ( ( unsigned int ) AT91C_PIO_PA16 ) /* SPI 0 Master In Slave */ +#define AT91C_PIO_PA17 ( ( unsigned int ) 1 << 17 ) /* Pin Controlled by PA17 */ +#define AT91C_PA17_MOSI0 ( ( unsigned int ) AT91C_PIO_PA17 ) /* SPI 0 Master Out Slave */ +#define AT91C_PIO_PA18 ( ( unsigned int ) 1 << 18 ) /* Pin Controlled by PA18 */ +#define AT91C_PA18_SPCK0 ( ( unsigned int ) AT91C_PIO_PA18 ) /* SPI 0 Serial Clock */ +#define AT91C_PIO_PA19 ( ( unsigned int ) 1 << 19 ) /* Pin Controlled by PA19 */ +#define AT91C_PA19_CANRX ( ( unsigned int ) AT91C_PIO_PA19 ) /* CAN Receive */ +#define AT91C_PIO_PA2 ( ( unsigned int ) 1 << 2 ) /* Pin Controlled by PA2 */ +#define AT91C_PA2_SCK0 ( ( unsigned int ) AT91C_PIO_PA2 ) /* USART 0 Serial Clock */ +#define AT91C_PA2_NPCS11 ( ( unsigned int ) AT91C_PIO_PA2 ) /* SPI 1 Peripheral Chip Select 1 */ +#define AT91C_PIO_PA20 ( ( unsigned int ) 1 << 20 ) /* Pin Controlled by PA20 */ +#define AT91C_PA20_CANTX ( ( unsigned int ) AT91C_PIO_PA20 ) /* CAN Transmit */ +#define AT91C_PIO_PA21 ( ( unsigned int ) 1 << 21 ) /* Pin Controlled by PA21 */ +#define AT91C_PA21_TF ( ( unsigned int ) AT91C_PIO_PA21 ) /* SSC Transmit Frame Sync */ +#define AT91C_PA21_NPCS10 ( ( unsigned int ) AT91C_PIO_PA21 ) /* SPI 1 Peripheral Chip Select 0 */ +#define AT91C_PIO_PA22 ( ( unsigned int ) 1 << 22 ) /* Pin Controlled by PA22 */ +#define AT91C_PA22_TK ( ( unsigned int ) AT91C_PIO_PA22 ) /* SSC Transmit Clock */ +#define AT91C_PA22_SPCK1 ( ( unsigned int ) AT91C_PIO_PA22 ) /* SPI 1 Serial Clock */ +#define AT91C_PIO_PA23 ( ( unsigned int ) 1 << 23 ) /* Pin Controlled by PA23 */ +#define AT91C_PA23_TD ( ( unsigned int ) AT91C_PIO_PA23 ) /* SSC Transmit data */ +#define AT91C_PA23_MOSI1 ( ( unsigned int ) AT91C_PIO_PA23 ) /* SPI 1 Master Out Slave */ +#define AT91C_PIO_PA24 ( ( unsigned int ) 1 << 24 ) /* Pin Controlled by PA24 */ +#define AT91C_PA24_RD ( ( unsigned int ) AT91C_PIO_PA24 ) /* SSC Receive Data */ +#define AT91C_PA24_MISO1 ( ( unsigned int ) AT91C_PIO_PA24 ) /* SPI 1 Master In Slave */ +#define AT91C_PIO_PA25 ( ( unsigned int ) 1 << 25 ) /* Pin Controlled by PA25 */ +#define AT91C_PA25_RK ( ( unsigned int ) AT91C_PIO_PA25 ) /* SSC Receive Clock */ +#define AT91C_PA25_NPCS11 ( ( unsigned int ) AT91C_PIO_PA25 ) /* SPI 1 Peripheral Chip Select 1 */ +#define AT91C_PIO_PA26 ( ( unsigned int ) 1 << 26 ) /* Pin Controlled by PA26 */ +#define AT91C_PA26_RF ( ( unsigned int ) AT91C_PIO_PA26 ) /* SSC Receive Frame Sync */ +#define AT91C_PA26_NPCS12 ( ( unsigned int ) AT91C_PIO_PA26 ) /* SPI 1 Peripheral Chip Select 2 */ +#define AT91C_PIO_PA27 ( ( unsigned int ) 1 << 27 ) /* Pin Controlled by PA27 */ +#define AT91C_PA27_DRXD ( ( unsigned int ) AT91C_PIO_PA27 ) /* DBGU Debug Receive Data */ +#define AT91C_PA27_PCK3 ( ( unsigned int ) AT91C_PIO_PA27 ) /* PMC Programmable Clock Output 3 */ +#define AT91C_PIO_PA28 ( ( unsigned int ) 1 << 28 ) /* Pin Controlled by PA28 */ +#define AT91C_PA28_DTXD ( ( unsigned int ) AT91C_PIO_PA28 ) /* DBGU Debug Transmit Data */ +#define AT91C_PIO_PA29 ( ( unsigned int ) 1 << 29 ) /* Pin Controlled by PA29 */ +#define AT91C_PA29_FIQ ( ( unsigned int ) AT91C_PIO_PA29 ) /* AIC Fast Interrupt Input */ +#define AT91C_PA29_NPCS13 ( ( unsigned int ) AT91C_PIO_PA29 ) /* SPI 1 Peripheral Chip Select 3 */ +#define AT91C_PIO_PA3 ( ( unsigned int ) 1 << 3 ) /* Pin Controlled by PA3 */ +#define AT91C_PA3_RTS0 ( ( unsigned int ) AT91C_PIO_PA3 ) /* USART 0 Ready To Send */ +#define AT91C_PA3_NPCS12 ( ( unsigned int ) AT91C_PIO_PA3 ) /* SPI 1 Peripheral Chip Select 2 */ +#define AT91C_PIO_PA30 ( ( unsigned int ) 1 << 30 ) /* Pin Controlled by PA30 */ +#define AT91C_PA30_IRQ0 ( ( unsigned int ) AT91C_PIO_PA30 ) /* External Interrupt 0 */ +#define AT91C_PA30_PCK2 ( ( unsigned int ) AT91C_PIO_PA30 ) /* PMC Programmable Clock Output 2 */ +#define AT91C_PIO_PA4 ( ( unsigned int ) 1 << 4 ) /* Pin Controlled by PA4 */ +#define AT91C_PA4_CTS0 ( ( unsigned int ) AT91C_PIO_PA4 ) /* USART 0 Clear To Send */ +#define AT91C_PA4_NPCS13 ( ( unsigned int ) AT91C_PIO_PA4 ) /* SPI 1 Peripheral Chip Select 3 */ +#define AT91C_PIO_PA5 ( ( unsigned int ) 1 << 5 ) /* Pin Controlled by PA5 */ +#define AT91C_PA5_RXD1 ( ( unsigned int ) AT91C_PIO_PA5 ) /* USART 1 Receive Data */ +#define AT91C_PIO_PA6 ( ( unsigned int ) 1 << 6 ) /* Pin Controlled by PA6 */ +#define AT91C_PA6_TXD1 ( ( unsigned int ) AT91C_PIO_PA6 ) /* USART 1 Transmit Data */ +#define AT91C_PIO_PA7 ( ( unsigned int ) 1 << 7 ) /* Pin Controlled by PA7 */ +#define AT91C_PA7_SCK1 ( ( unsigned int ) AT91C_PIO_PA7 ) /* USART 1 Serial Clock */ +#define AT91C_PA7_NPCS01 ( ( unsigned int ) AT91C_PIO_PA7 ) /* SPI 0 Peripheral Chip Select 1 */ +#define AT91C_PIO_PA8 ( ( unsigned int ) 1 << 8 ) /* Pin Controlled by PA8 */ +#define AT91C_PA8_RTS1 ( ( unsigned int ) AT91C_PIO_PA8 ) /* USART 1 Ready To Send */ +#define AT91C_PA8_NPCS02 ( ( unsigned int ) AT91C_PIO_PA8 ) /* SPI 0 Peripheral Chip Select 2 */ +#define AT91C_PIO_PA9 ( ( unsigned int ) 1 << 9 ) /* Pin Controlled by PA9 */ +#define AT91C_PA9_CTS1 ( ( unsigned int ) AT91C_PIO_PA9 ) /* USART 1 Clear To Send */ +#define AT91C_PA9_NPCS03 ( ( unsigned int ) AT91C_PIO_PA9 ) /* SPI 0 Peripheral Chip Select 3 */ +#define AT91C_PIO_PB0 ( ( unsigned int ) 1 << 0 ) /* Pin Controlled by PB0 */ +#define AT91C_PB0_ETXCK_EREFCK ( ( unsigned int ) AT91C_PIO_PB0 ) /* Ethernet MAC Transmit Clock/Reference Clock */ +#define AT91C_PB0_PCK0 ( ( unsigned int ) AT91C_PIO_PB0 ) /* PMC Programmable Clock Output 0 */ +#define AT91C_PIO_PB1 ( ( unsigned int ) 1 << 1 ) /* Pin Controlled by PB1 */ +#define AT91C_PB1_ETXEN ( ( unsigned int ) AT91C_PIO_PB1 ) /* Ethernet MAC Transmit Enable */ +#define AT91C_PIO_PB10 ( ( unsigned int ) 1 << 10 ) /* Pin Controlled by PB10 */ +#define AT91C_PB10_ETX2 ( ( unsigned int ) AT91C_PIO_PB10 ) /* Ethernet MAC Transmit Data 2 */ +#define AT91C_PB10_NPCS11 ( ( unsigned int ) AT91C_PIO_PB10 ) /* SPI 1 Peripheral Chip Select 1 */ +#define AT91C_PIO_PB11 ( ( unsigned int ) 1 << 11 ) /* Pin Controlled by PB11 */ +#define AT91C_PB11_ETX3 ( ( unsigned int ) AT91C_PIO_PB11 ) /* Ethernet MAC Transmit Data 3 */ +#define AT91C_PB11_NPCS12 ( ( unsigned int ) AT91C_PIO_PB11 ) /* SPI 1 Peripheral Chip Select 2 */ +#define AT91C_PIO_PB12 ( ( unsigned int ) 1 << 12 ) /* Pin Controlled by PB12 */ +#define AT91C_PB12_ETXER ( ( unsigned int ) AT91C_PIO_PB12 ) /* Ethernet MAC Transmit Coding Error */ +#define AT91C_PB12_TCLK0 ( ( unsigned int ) AT91C_PIO_PB12 ) /* Timer Counter 0 external clock input */ +#define AT91C_PIO_PB13 ( ( unsigned int ) 1 << 13 ) /* Pin Controlled by PB13 */ +#define AT91C_PB13_ERX2 ( ( unsigned int ) AT91C_PIO_PB13 ) /* Ethernet MAC Receive Data 2 */ +#define AT91C_PB13_NPCS01 ( ( unsigned int ) AT91C_PIO_PB13 ) /* SPI 0 Peripheral Chip Select 1 */ +#define AT91C_PIO_PB14 ( ( unsigned int ) 1 << 14 ) /* Pin Controlled by PB14 */ +#define AT91C_PB14_ERX3 ( ( unsigned int ) AT91C_PIO_PB14 ) /* Ethernet MAC Receive Data 3 */ +#define AT91C_PB14_NPCS02 ( ( unsigned int ) AT91C_PIO_PB14 ) /* SPI 0 Peripheral Chip Select 2 */ +#define AT91C_PIO_PB15 ( ( unsigned int ) 1 << 15 ) /* Pin Controlled by PB15 */ +#define AT91C_PB15_ERXDV ( ( unsigned int ) AT91C_PIO_PB15 ) /* Ethernet MAC Receive Data Valid */ +#define AT91C_PIO_PB16 ( ( unsigned int ) 1 << 16 ) /* Pin Controlled by PB16 */ +#define AT91C_PB16_ECOL ( ( unsigned int ) AT91C_PIO_PB16 ) /* Ethernet MAC Collision Detected */ +#define AT91C_PB16_NPCS13 ( ( unsigned int ) AT91C_PIO_PB16 ) /* SPI 1 Peripheral Chip Select 3 */ +#define AT91C_PIO_PB17 ( ( unsigned int ) 1 << 17 ) /* Pin Controlled by PB17 */ +#define AT91C_PB17_ERXCK ( ( unsigned int ) AT91C_PIO_PB17 ) /* Ethernet MAC Receive Clock */ +#define AT91C_PB17_NPCS03 ( ( unsigned int ) AT91C_PIO_PB17 ) /* SPI 0 Peripheral Chip Select 3 */ +#define AT91C_PIO_PB18 ( ( unsigned int ) 1 << 18 ) /* Pin Controlled by PB18 */ +#define AT91C_PB18_EF100 ( ( unsigned int ) AT91C_PIO_PB18 ) /* Ethernet MAC Force 100 Mbits/sec */ +#define AT91C_PB18_ADTRG ( ( unsigned int ) AT91C_PIO_PB18 ) /* ADC External Trigger */ +#define AT91C_PIO_PB19 ( ( unsigned int ) 1 << 19 ) /* Pin Controlled by PB19 */ +#define AT91C_PB19_PWM0 ( ( unsigned int ) AT91C_PIO_PB19 ) /* PWM Channel 0 */ +#define AT91C_PB19_TCLK1 ( ( unsigned int ) AT91C_PIO_PB19 ) /* Timer Counter 1 external clock input */ +#define AT91C_PIO_PB2 ( ( unsigned int ) 1 << 2 ) /* Pin Controlled by PB2 */ +#define AT91C_PB2_ETX0 ( ( unsigned int ) AT91C_PIO_PB2 ) /* Ethernet MAC Transmit Data 0 */ +#define AT91C_PIO_PB20 ( ( unsigned int ) 1 << 20 ) /* Pin Controlled by PB20 */ +#define AT91C_PB20_PWM1 ( ( unsigned int ) AT91C_PIO_PB20 ) /* PWM Channel 1 */ +#define AT91C_PB20_PCK0 ( ( unsigned int ) AT91C_PIO_PB20 ) /* PMC Programmable Clock Output 0 */ +#define AT91C_PIO_PB21 ( ( unsigned int ) 1 << 21 ) /* Pin Controlled by PB21 */ +#define AT91C_PB21_PWM2 ( ( unsigned int ) AT91C_PIO_PB21 ) /* PWM Channel 2 */ +#define AT91C_PB21_PCK1 ( ( unsigned int ) AT91C_PIO_PB21 ) /* PMC Programmable Clock Output 1 */ +#define AT91C_PIO_PB22 ( ( unsigned int ) 1 << 22 ) /* Pin Controlled by PB22 */ +#define AT91C_PB22_PWM3 ( ( unsigned int ) AT91C_PIO_PB22 ) /* PWM Channel 3 */ +#define AT91C_PB22_PCK2 ( ( unsigned int ) AT91C_PIO_PB22 ) /* PMC Programmable Clock Output 2 */ +#define AT91C_PIO_PB23 ( ( unsigned int ) 1 << 23 ) /* Pin Controlled by PB23 */ +#define AT91C_PB23_TIOA0 ( ( unsigned int ) AT91C_PIO_PB23 ) /* Timer Counter 0 Multipurpose Timer I/O Pin A */ +#define AT91C_PB23_DCD1 ( ( unsigned int ) AT91C_PIO_PB23 ) /* USART 1 Data Carrier Detect */ +#define AT91C_PIO_PB24 ( ( unsigned int ) 1 << 24 ) /* Pin Controlled by PB24 */ +#define AT91C_PB24_TIOB0 ( ( unsigned int ) AT91C_PIO_PB24 ) /* Timer Counter 0 Multipurpose Timer I/O Pin B */ +#define AT91C_PB24_DSR1 ( ( unsigned int ) AT91C_PIO_PB24 ) /* USART 1 Data Set ready */ +#define AT91C_PIO_PB25 ( ( unsigned int ) 1 << 25 ) /* Pin Controlled by PB25 */ +#define AT91C_PB25_TIOA1 ( ( unsigned int ) AT91C_PIO_PB25 ) /* Timer Counter 1 Multipurpose Timer I/O Pin A */ +#define AT91C_PB25_DTR1 ( ( unsigned int ) AT91C_PIO_PB25 ) /* USART 1 Data Terminal ready */ +#define AT91C_PIO_PB26 ( ( unsigned int ) 1 << 26 ) /* Pin Controlled by PB26 */ +#define AT91C_PB26_TIOB1 ( ( unsigned int ) AT91C_PIO_PB26 ) /* Timer Counter 1 Multipurpose Timer I/O Pin B */ +#define AT91C_PB26_RI1 ( ( unsigned int ) AT91C_PIO_PB26 ) /* USART 1 Ring Indicator */ +#define AT91C_PIO_PB27 ( ( unsigned int ) 1 << 27 ) /* Pin Controlled by PB27 */ +#define AT91C_PB27_TIOA2 ( ( unsigned int ) AT91C_PIO_PB27 ) /* Timer Counter 2 Multipurpose Timer I/O Pin A */ +#define AT91C_PB27_PWM0 ( ( unsigned int ) AT91C_PIO_PB27 ) /* PWM Channel 0 */ +#define AT91C_PIO_PB28 ( ( unsigned int ) 1 << 28 ) /* Pin Controlled by PB28 */ +#define AT91C_PB28_TIOB2 ( ( unsigned int ) AT91C_PIO_PB28 ) /* Timer Counter 2 Multipurpose Timer I/O Pin B */ +#define AT91C_PB28_PWM1 ( ( unsigned int ) AT91C_PIO_PB28 ) /* PWM Channel 1 */ +#define AT91C_PIO_PB29 ( ( unsigned int ) 1 << 29 ) /* Pin Controlled by PB29 */ +#define AT91C_PB29_PCK1 ( ( unsigned int ) AT91C_PIO_PB29 ) /* PMC Programmable Clock Output 1 */ +#define AT91C_PB29_PWM2 ( ( unsigned int ) AT91C_PIO_PB29 ) /* PWM Channel 2 */ +#define AT91C_PIO_PB3 ( ( unsigned int ) 1 << 3 ) /* Pin Controlled by PB3 */ +#define AT91C_PB3_ETX1 ( ( unsigned int ) AT91C_PIO_PB3 ) /* Ethernet MAC Transmit Data 1 */ +#define AT91C_PIO_PB30 ( ( unsigned int ) 1 << 30 ) /* Pin Controlled by PB30 */ +#define AT91C_PB30_PCK2 ( ( unsigned int ) AT91C_PIO_PB30 ) /* PMC Programmable Clock Output 2 */ +#define AT91C_PB30_PWM3 ( ( unsigned int ) AT91C_PIO_PB30 ) /* PWM Channel 3 */ +#define AT91C_PIO_PB4 ( ( unsigned int ) 1 << 4 ) /* Pin Controlled by PB4 */ +#define AT91C_PB4_ECRS_ECRSDV ( ( unsigned int ) AT91C_PIO_PB4 ) /* Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */ +#define AT91C_PIO_PB5 ( ( unsigned int ) 1 << 5 ) /* Pin Controlled by PB5 */ +#define AT91C_PB5_ERX0 ( ( unsigned int ) AT91C_PIO_PB5 ) /* Ethernet MAC Receive Data 0 */ +#define AT91C_PIO_PB6 ( ( unsigned int ) 1 << 6 ) /* Pin Controlled by PB6 */ +#define AT91C_PB6_ERX1 ( ( unsigned int ) AT91C_PIO_PB6 ) /* Ethernet MAC Receive Data 1 */ +#define AT91C_PIO_PB7 ( ( unsigned int ) 1 << 7 ) /* Pin Controlled by PB7 */ +#define AT91C_PB7_ERXER ( ( unsigned int ) AT91C_PIO_PB7 ) /* Ethernet MAC Receive Error */ +#define AT91C_PIO_PB8 ( ( unsigned int ) 1 << 8 ) /* Pin Controlled by PB8 */ +#define AT91C_PB8_EMDC ( ( unsigned int ) AT91C_PIO_PB8 ) /* Ethernet MAC Management Data Clock */ +#define AT91C_PIO_PB9 ( ( unsigned int ) 1 << 9 ) /* Pin Controlled by PB9 */ +#define AT91C_PB9_EMDIO ( ( unsigned int ) AT91C_PIO_PB9 ) /* Ethernet MAC Management Data Input/Output */ + +/* ***************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 */ +/* ***************************************************************************** */ +#define AT91C_ID_FIQ ( ( unsigned int ) 0 ) /* Advanced Interrupt Controller (FIQ) */ +#define AT91C_ID_SYS ( ( unsigned int ) 1 ) /* System Peripheral */ +#define AT91C_ID_PIOA ( ( unsigned int ) 2 ) /* Parallel IO Controller A */ +#define AT91C_ID_PIOB ( ( unsigned int ) 3 ) /* Parallel IO Controller B */ +#define AT91C_ID_SPI0 ( ( unsigned int ) 4 ) /* Serial Peripheral Interface 0 */ +#define AT91C_ID_SPI1 ( ( unsigned int ) 5 ) /* Serial Peripheral Interface 1 */ +#define AT91C_ID_US0 ( ( unsigned int ) 6 ) /* USART 0 */ +#define AT91C_ID_US1 ( ( unsigned int ) 7 ) /* USART 1 */ +#define AT91C_ID_SSC ( ( unsigned int ) 8 ) /* Serial Synchronous Controller */ +#define AT91C_ID_TWI ( ( unsigned int ) 9 ) /* Two-Wire Interface */ +#define AT91C_ID_PWMC ( ( unsigned int ) 10 ) /* PWM Controller */ +#define AT91C_ID_UDP ( ( unsigned int ) 11 ) /* USB Device Port */ +#define AT91C_ID_TC0 ( ( unsigned int ) 12 ) /* Timer Counter 0 */ +#define AT91C_ID_TC1 ( ( unsigned int ) 13 ) /* Timer Counter 1 */ +#define AT91C_ID_TC2 ( ( unsigned int ) 14 ) /* Timer Counter 2 */ +#define AT91C_ID_CAN ( ( unsigned int ) 15 ) /* Control Area Network Controller */ +#define AT91C_ID_EMAC ( ( unsigned int ) 16 ) /* Ethernet MAC */ +#define AT91C_ID_ADC ( ( unsigned int ) 17 ) /* Analog-to-Digital Converter */ +#define AT91C_ID_AES ( ( unsigned int ) 18 ) /* Advanced Encryption Standard 128-bit */ +#define AT91C_ID_TDES ( ( unsigned int ) 19 ) /* Triple Data Encryption Standard */ +#define AT91C_ID_20_Reserved ( ( unsigned int ) 20 ) /* Reserved */ +#define AT91C_ID_21_Reserved ( ( unsigned int ) 21 ) /* Reserved */ +#define AT91C_ID_22_Reserved ( ( unsigned int ) 22 ) /* Reserved */ +#define AT91C_ID_23_Reserved ( ( unsigned int ) 23 ) /* Reserved */ +#define AT91C_ID_24_Reserved ( ( unsigned int ) 24 ) /* Reserved */ +#define AT91C_ID_25_Reserved ( ( unsigned int ) 25 ) /* Reserved */ +#define AT91C_ID_26_Reserved ( ( unsigned int ) 26 ) /* Reserved */ +#define AT91C_ID_27_Reserved ( ( unsigned int ) 27 ) /* Reserved */ +#define AT91C_ID_28_Reserved ( ( unsigned int ) 28 ) /* Reserved */ +#define AT91C_ID_29_Reserved ( ( unsigned int ) 29 ) /* Reserved */ +#define AT91C_ID_IRQ0 ( ( unsigned int ) 30 ) /* Advanced Interrupt Controller (IRQ0) */ +#define AT91C_ID_IRQ1 ( ( unsigned int ) 31 ) /* Advanced Interrupt Controller (IRQ1) */ + +/* ***************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 */ +/* ***************************************************************************** */ +#define AT91C_BASE_SYS ( ( AT91PS_SYS ) 0xFFFFF000 ) /* (SYS) Base Address */ +#define AT91C_BASE_AIC ( ( AT91PS_AIC ) 0xFFFFF000 ) /* (AIC) Base Address */ +#define AT91C_BASE_PDC_DBGU ( ( AT91PS_PDC ) 0xFFFFF300 ) /* (PDC_DBGU) Base Address */ +#define AT91C_BASE_DBGU ( ( AT91PS_DBGU ) 0xFFFFF200 ) /* (DBGU) Base Address */ +#define AT91C_BASE_PIOA ( ( AT91PS_PIO ) 0xFFFFF400 ) /* (PIOA) Base Address */ +#define AT91C_BASE_PIOB ( ( AT91PS_PIO ) 0xFFFFF600 ) /* (PIOB) Base Address */ +#define AT91C_BASE_CKGR ( ( AT91PS_CKGR ) 0xFFFFFC20 ) /* (CKGR) Base Address */ +#define AT91C_BASE_PMC ( ( AT91PS_PMC ) 0xFFFFFC00 ) /* (PMC) Base Address */ +#define AT91C_BASE_RSTC ( ( AT91PS_RSTC ) 0xFFFFFD00 ) /* (RSTC) Base Address */ +#define AT91C_BASE_RTTC ( ( AT91PS_RTTC ) 0xFFFFFD20 ) /* (RTTC) Base Address */ +#define AT91C_BASE_PITC ( ( AT91PS_PITC ) 0xFFFFFD30 ) /* (PITC) Base Address */ +#define AT91C_BASE_WDTC ( ( AT91PS_WDTC ) 0xFFFFFD40 ) /* (WDTC) Base Address */ +#define AT91C_BASE_VREG ( ( AT91PS_VREG ) 0xFFFFFD60 ) /* (VREG) Base Address */ +#define AT91C_BASE_MC ( ( AT91PS_MC ) 0xFFFFFF00 ) /* (MC) Base Address */ +#define AT91C_BASE_PDC_SPI1 ( ( AT91PS_PDC ) 0xFFFE4100 ) /* (PDC_SPI1) Base Address */ +#define AT91C_BASE_SPI1 ( ( AT91PS_SPI ) 0xFFFE4000 ) /* (SPI1) Base Address */ +#define AT91C_BASE_PDC_SPI0 ( ( AT91PS_PDC ) 0xFFFE0100 ) /* (PDC_SPI0) Base Address */ +#define AT91C_BASE_SPI0 ( ( AT91PS_SPI ) 0xFFFE0000 ) /* (SPI0) Base Address */ +#define AT91C_BASE_PDC_US1 ( ( AT91PS_PDC ) 0xFFFC4100 ) /* (PDC_US1) Base Address */ +#define AT91C_BASE_US1 ( ( AT91PS_USART ) 0xFFFC4000 ) /* (US1) Base Address */ +#define AT91C_BASE_PDC_US0 ( ( AT91PS_PDC ) 0xFFFC0100 ) /* (PDC_US0) Base Address */ +#define AT91C_BASE_US0 ( ( AT91PS_USART ) 0xFFFC0000 ) /* (US0) Base Address */ +#define AT91C_BASE_PDC_SSC ( ( AT91PS_PDC ) 0xFFFD4100 ) /* (PDC_SSC) Base Address */ +#define AT91C_BASE_SSC ( ( AT91PS_SSC ) 0xFFFD4000 ) /* (SSC) Base Address */ +#define AT91C_BASE_TWI ( ( AT91PS_TWI ) 0xFFFB8000 ) /* (TWI) Base Address */ +#define AT91C_BASE_PWMC_CH3 ( ( AT91PS_PWMC_CH ) 0xFFFCC260 ) /* (PWMC_CH3) Base Address */ +#define AT91C_BASE_PWMC_CH2 ( ( AT91PS_PWMC_CH ) 0xFFFCC240 ) /* (PWMC_CH2) Base Address */ +#define AT91C_BASE_PWMC_CH1 ( ( AT91PS_PWMC_CH ) 0xFFFCC220 ) /* (PWMC_CH1) Base Address */ +#define AT91C_BASE_PWMC_CH0 ( ( AT91PS_PWMC_CH ) 0xFFFCC200 ) /* (PWMC_CH0) Base Address */ +#define AT91C_BASE_PWMC ( ( AT91PS_PWMC ) 0xFFFCC000 ) /* (PWMC) Base Address */ +#define AT91C_BASE_UDP ( ( AT91PS_UDP ) 0xFFFB0000 ) /* (UDP) Base Address */ +#define AT91C_BASE_TC0 ( ( AT91PS_TC ) 0xFFFA0000 ) /* (TC0) Base Address */ +#define AT91C_BASE_TC1 ( ( AT91PS_TC ) 0xFFFA0040 ) /* (TC1) Base Address */ +#define AT91C_BASE_TC2 ( ( AT91PS_TC ) 0xFFFA0080 ) /* (TC2) Base Address */ +#define AT91C_BASE_TCB ( ( AT91PS_TCB ) 0xFFFA0000 ) /* (TCB) Base Address */ +#define AT91C_BASE_CAN_MB0 ( ( AT91PS_CAN_MB ) 0xFFFD0200 ) /* (CAN_MB0) Base Address */ +#define AT91C_BASE_CAN_MB1 ( ( AT91PS_CAN_MB ) 0xFFFD0220 ) /* (CAN_MB1) Base Address */ +#define AT91C_BASE_CAN_MB2 ( ( AT91PS_CAN_MB ) 0xFFFD0240 ) /* (CAN_MB2) Base Address */ +#define AT91C_BASE_CAN_MB3 ( ( AT91PS_CAN_MB ) 0xFFFD0260 ) /* (CAN_MB3) Base Address */ +#define AT91C_BASE_CAN_MB4 ( ( AT91PS_CAN_MB ) 0xFFFD0280 ) /* (CAN_MB4) Base Address */ +#define AT91C_BASE_CAN_MB5 ( ( AT91PS_CAN_MB ) 0xFFFD02A0 ) /* (CAN_MB5) Base Address */ +#define AT91C_BASE_CAN_MB6 ( ( AT91PS_CAN_MB ) 0xFFFD02C0 ) /* (CAN_MB6) Base Address */ +#define AT91C_BASE_CAN_MB7 ( ( AT91PS_CAN_MB ) 0xFFFD02E0 ) /* (CAN_MB7) Base Address */ +#define AT91C_BASE_CAN ( ( AT91PS_CAN ) 0xFFFD0000 ) /* (CAN) Base Address */ +#define AT91C_BASE_EMAC ( ( AT91PS_EMAC ) 0xFFFDC000 ) /* (EMAC) Base Address */ +#define AT91C_BASE_PDC_ADC ( ( AT91PS_PDC ) 0xFFFD8100 ) /* (PDC_ADC) Base Address */ +#define AT91C_BASE_ADC ( ( AT91PS_ADC ) 0xFFFD8000 ) /* (ADC) Base Address */ +#define AT91C_BASE_PDC_AES ( ( AT91PS_PDC ) 0xFFFA4100 ) /* (PDC_AES) Base Address */ +#define AT91C_BASE_AES ( ( AT91PS_AES ) 0xFFFA4000 ) /* (AES) Base Address */ +#define AT91C_BASE_PDC_TDES ( ( AT91PS_PDC ) 0xFFFA8100 ) /* (PDC_TDES) Base Address */ +#define AT91C_BASE_TDES ( ( AT91PS_TDES ) 0xFFFA8000 ) /* (TDES) Base Address */ + +/* ***************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 */ +/* ***************************************************************************** */ +#define AT91C_ISRAM ( ( char * ) 0x00200000 ) /* Internal SRAM base address */ +#define AT91C_ISRAM_SIZE ( ( unsigned int ) 0x00010000 ) /* Internal SRAM size in byte (64 Kbyte) */ +#define AT91C_IFLASH ( ( char * ) 0x00100000 ) /* Internal ROM base address */ +#define AT91C_IFLASH_SIZE ( ( unsigned int ) 0x00040000 ) /* Internal ROM size in byte (256 Kbyte) */ + +#endif /* ifndef AT91SAM7X256_H */ diff --git a/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h b/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h new file mode 100644 index 000000000..8471ca44d --- /dev/null +++ b/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h @@ -0,0 +1,2444 @@ +/* ---------------------------------------------------------------------------- */ +/* ATMEL Microcontroller Software Support - ROUSSET - */ +/* ---------------------------------------------------------------------------- */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ +/* File Name : AT91SAM7X256.h */ +/* Object : AT91SAM7X256 definitions */ +/* Generated : AT91 SW Application Group 05/20/2005 (16:22:29) */ +/* */ +/* CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005// */ +/* CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// */ +/* CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// */ +/* CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// */ +/* CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// */ +/* CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// */ +/* CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// */ +/* CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// */ +/* CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// */ +/* CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// */ +/* CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// */ +/* CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// */ +/* CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// */ +/* CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// */ +/* CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// */ +/* CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// */ +/* CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// */ +/* CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// */ +/* CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// */ +/* CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// */ +/* CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// */ +/* CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// */ +/* CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// */ +/* CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// */ +/* CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// */ +/* ---------------------------------------------------------------------------- */ + +/* Hardware register definition */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR System Peripherals */ +/* ***************************************************************************** */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Advanced Interrupt Controller */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_AIC structure *** */ +#define AIC_SMR ( 0 ) /* Source Mode Register */ +#define AIC_SVR ( 128 ) /* Source Vector Register */ +#define AIC_IVR ( 256 ) /* IRQ Vector Register */ +#define AIC_FVR ( 260 ) /* FIQ Vector Register */ +#define AIC_ISR ( 264 ) /* Interrupt Status Register */ +#define AIC_IPR ( 268 ) /* Interrupt Pending Register */ +#define AIC_IMR ( 272 ) /* Interrupt Mask Register */ +#define AIC_CISR ( 276 ) /* Core Interrupt Status Register */ +#define AIC_IECR ( 288 ) /* Interrupt Enable Command Register */ +#define AIC_IDCR ( 292 ) /* Interrupt Disable Command Register */ +#define AIC_ICCR ( 296 ) /* Interrupt Clear Command Register */ +#define AIC_ISCR ( 300 ) /* Interrupt Set Command Register */ +#define AIC_EOICR ( 304 ) /* End of Interrupt Command Register */ +#define AIC_SPU ( 308 ) /* Spurious Vector Register */ +#define AIC_DCR ( 312 ) /* Debug Control Register (Protect) */ +#define AIC_FFER ( 320 ) /* Fast Forcing Enable Register */ +#define AIC_FFDR ( 324 ) /* Fast Forcing Disable Register */ +#define AIC_FFSR ( 328 ) /* Fast Forcing Status Register */ +/* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */ +#define AT91C_AIC_PRIOR ( 0x7 << 0 ) /* (AIC) Priority Level */ +#define AT91C_AIC_PRIOR_LOWEST ( 0x0 ) /* (AIC) Lowest priority level */ +#define AT91C_AIC_PRIOR_HIGHEST ( 0x7 ) /* (AIC) Highest priority level */ +#define AT91C_AIC_SRCTYPE ( 0x3 << 5 ) /* (AIC) Interrupt Source Type */ +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ( 0x0 << 5 ) /* (AIC) Internal Sources Code Label High-level Sensitive */ +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ( 0x0 << 5 ) /* (AIC) External Sources Code Label Low-level Sensitive */ +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ( 0x1 << 5 ) /* (AIC) Internal Sources Code Label Positive Edge triggered */ +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ( 0x1 << 5 ) /* (AIC) External Sources Code Label Negative Edge triggered */ +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ( 0x2 << 5 ) /* (AIC) Internal Or External Sources Code Label High-level Sensitive */ +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ( 0x3 << 5 ) /* (AIC) Internal Or External Sources Code Label Positive Edge triggered */ +/* -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- */ +#define AT91C_AIC_NFIQ ( 0x1 << 0 ) /* (AIC) NFIQ Status */ +#define AT91C_AIC_NIRQ ( 0x1 << 1 ) /* (AIC) NIRQ Status */ +/* -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- */ +#define AT91C_AIC_DCR_PROT ( 0x1 << 0 ) /* (AIC) Protection Mode */ +#define AT91C_AIC_DCR_GMSK ( 0x1 << 1 ) /* (AIC) General Mask */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Peripheral DMA Controller */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_PDC structure *** */ +#define PDC_RPR ( 0 ) /* Receive Pointer Register */ +#define PDC_RCR ( 4 ) /* Receive Counter Register */ +#define PDC_TPR ( 8 ) /* Transmit Pointer Register */ +#define PDC_TCR ( 12 ) /* Transmit Counter Register */ +#define PDC_RNPR ( 16 ) /* Receive Next Pointer Register */ +#define PDC_RNCR ( 20 ) /* Receive Next Counter Register */ +#define PDC_TNPR ( 24 ) /* Transmit Next Pointer Register */ +#define PDC_TNCR ( 28 ) /* Transmit Next Counter Register */ +#define PDC_PTCR ( 32 ) /* PDC Transfer Control Register */ +#define PDC_PTSR ( 36 ) /* PDC Transfer Status Register */ +/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */ +#define AT91C_PDC_RXTEN ( 0x1 << 0 ) /* (PDC) Receiver Transfer Enable */ +#define AT91C_PDC_RXTDIS ( 0x1 << 1 ) /* (PDC) Receiver Transfer Disable */ +#define AT91C_PDC_TXTEN ( 0x1 << 8 ) /* (PDC) Transmitter Transfer Enable */ +#define AT91C_PDC_TXTDIS ( 0x1 << 9 ) /* (PDC) Transmitter Transfer Disable */ +/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Debug Unit */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_DBGU structure *** */ +#define DBGU_CR ( 0 ) /* Control Register */ +#define DBGU_MR ( 4 ) /* Mode Register */ +#define DBGU_IER ( 8 ) /* Interrupt Enable Register */ +#define DBGU_IDR ( 12 ) /* Interrupt Disable Register */ +#define DBGU_IMR ( 16 ) /* Interrupt Mask Register */ +#define DBGU_CSR ( 20 ) /* Channel Status Register */ +#define DBGU_RHR ( 24 ) /* Receiver Holding Register */ +#define DBGU_THR ( 28 ) /* Transmitter Holding Register */ +#define DBGU_BRGR ( 32 ) /* Baud Rate Generator Register */ +#define DBGU_CIDR ( 64 ) /* Chip ID Register */ +#define DBGU_EXID ( 68 ) /* Chip ID Extension Register */ +#define DBGU_FNTR ( 72 ) /* Force NTRST Register */ +#define DBGU_RPR ( 256 ) /* Receive Pointer Register */ +#define DBGU_RCR ( 260 ) /* Receive Counter Register */ +#define DBGU_TPR ( 264 ) /* Transmit Pointer Register */ +#define DBGU_TCR ( 268 ) /* Transmit Counter Register */ +#define DBGU_RNPR ( 272 ) /* Receive Next Pointer Register */ +#define DBGU_RNCR ( 276 ) /* Receive Next Counter Register */ +#define DBGU_TNPR ( 280 ) /* Transmit Next Pointer Register */ +#define DBGU_TNCR ( 284 ) /* Transmit Next Counter Register */ +#define DBGU_PTCR ( 288 ) /* PDC Transfer Control Register */ +#define DBGU_PTSR ( 292 ) /* PDC Transfer Status Register */ +/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */ +#define AT91C_US_RSTRX ( 0x1 << 2 ) /* (DBGU) Reset Receiver */ +#define AT91C_US_RSTTX ( 0x1 << 3 ) /* (DBGU) Reset Transmitter */ +#define AT91C_US_RXEN ( 0x1 << 4 ) /* (DBGU) Receiver Enable */ +#define AT91C_US_RXDIS ( 0x1 << 5 ) /* (DBGU) Receiver Disable */ +#define AT91C_US_TXEN ( 0x1 << 6 ) /* (DBGU) Transmitter Enable */ +#define AT91C_US_TXDIS ( 0x1 << 7 ) /* (DBGU) Transmitter Disable */ +#define AT91C_US_RSTSTA ( 0x1 << 8 ) /* (DBGU) Reset Status Bits */ +/* -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- */ +#define AT91C_US_PAR ( 0x7 << 9 ) /* (DBGU) Parity type */ +#define AT91C_US_PAR_EVEN ( 0x0 << 9 ) /* (DBGU) Even Parity */ +#define AT91C_US_PAR_ODD ( 0x1 << 9 ) /* (DBGU) Odd Parity */ +#define AT91C_US_PAR_SPACE ( 0x2 << 9 ) /* (DBGU) Parity forced to 0 (Space) */ +#define AT91C_US_PAR_MARK ( 0x3 << 9 ) /* (DBGU) Parity forced to 1 (Mark) */ +#define AT91C_US_PAR_NONE ( 0x4 << 9 ) /* (DBGU) No Parity */ +#define AT91C_US_PAR_MULTI_DROP ( 0x6 << 9 ) /* (DBGU) Multi-drop mode */ +#define AT91C_US_CHMODE ( 0x3 << 14 ) /* (DBGU) Channel Mode */ +#define AT91C_US_CHMODE_NORMAL ( 0x0 << 14 ) /* (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. */ +#define AT91C_US_CHMODE_AUTO ( 0x1 << 14 ) /* (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. */ +#define AT91C_US_CHMODE_LOCAL ( 0x2 << 14 ) /* (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. */ +#define AT91C_US_CHMODE_REMOTE ( 0x3 << 14 ) /* (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. */ +/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ +#define AT91C_US_RXRDY ( 0x1 << 0 ) /* (DBGU) RXRDY Interrupt */ +#define AT91C_US_TXRDY ( 0x1 << 1 ) /* (DBGU) TXRDY Interrupt */ +#define AT91C_US_ENDRX ( 0x1 << 3 ) /* (DBGU) End of Receive Transfer Interrupt */ +#define AT91C_US_ENDTX ( 0x1 << 4 ) /* (DBGU) End of Transmit Interrupt */ +#define AT91C_US_OVRE ( 0x1 << 5 ) /* (DBGU) Overrun Interrupt */ +#define AT91C_US_FRAME ( 0x1 << 6 ) /* (DBGU) Framing Error Interrupt */ +#define AT91C_US_PARE ( 0x1 << 7 ) /* (DBGU) Parity Error Interrupt */ +#define AT91C_US_TXEMPTY ( 0x1 << 9 ) /* (DBGU) TXEMPTY Interrupt */ +#define AT91C_US_TXBUFE ( 0x1 << 11 ) /* (DBGU) TXBUFE Interrupt */ +#define AT91C_US_RXBUFF ( 0x1 << 12 ) /* (DBGU) RXBUFF Interrupt */ +#define AT91C_US_COMM_TX ( 0x1 << 30 ) /* (DBGU) COMM_TX Interrupt */ +#define AT91C_US_COMM_RX ( 0x1 << 31 ) /* (DBGU) COMM_RX Interrupt */ +/* -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- */ +/* -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- */ +/* -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- */ +/* -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- */ +#define AT91C_US_FORCE_NTRST ( 0x1 << 0 ) /* (DBGU) Force NTRST in JTAG */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Parallel Input Output Controller */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_PIO structure *** */ +#define PIO_PER ( 0 ) /* PIO Enable Register */ +#define PIO_PDR ( 4 ) /* PIO Disable Register */ +#define PIO_PSR ( 8 ) /* PIO Status Register */ +#define PIO_OER ( 16 ) /* Output Enable Register */ +#define PIO_ODR ( 20 ) /* Output Disable Registerr */ +#define PIO_OSR ( 24 ) /* Output Status Register */ +#define PIO_IFER ( 32 ) /* Input Filter Enable Register */ +#define PIO_IFDR ( 36 ) /* Input Filter Disable Register */ +#define PIO_IFSR ( 40 ) /* Input Filter Status Register */ +#define PIO_SODR ( 48 ) /* Set Output Data Register */ +#define PIO_CODR ( 52 ) /* Clear Output Data Register */ +#define PIO_ODSR ( 56 ) /* Output Data Status Register */ +#define PIO_PDSR ( 60 ) /* Pin Data Status Register */ +#define PIO_IER ( 64 ) /* Interrupt Enable Register */ +#define PIO_IDR ( 68 ) /* Interrupt Disable Register */ +#define PIO_IMR ( 72 ) /* Interrupt Mask Register */ +#define PIO_ISR ( 76 ) /* Interrupt Status Register */ +#define PIO_MDER ( 80 ) /* Multi-driver Enable Register */ +#define PIO_MDDR ( 84 ) /* Multi-driver Disable Register */ +#define PIO_MDSR ( 88 ) /* Multi-driver Status Register */ +#define PIO_PPUDR ( 96 ) /* Pull-up Disable Register */ +#define PIO_PPUER ( 100 ) /* Pull-up Enable Register */ +#define PIO_PPUSR ( 104 ) /* Pull-up Status Register */ +#define PIO_ASR ( 112 ) /* Select A Register */ +#define PIO_BSR ( 116 ) /* Select B Register */ +#define PIO_ABSR ( 120 ) /* AB Select Status Register */ +#define PIO_OWER ( 160 ) /* Output Write Enable Register */ +#define PIO_OWDR ( 164 ) /* Output Write Disable Register */ +#define PIO_OWSR ( 168 ) /* Output Write Status Register */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Clock Generator Controller */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_CKGR structure *** */ +#define CKGR_MOR ( 0 ) /* Main Oscillator Register */ +#define CKGR_MCFR ( 4 ) /* Main Clock Frequency Register */ +#define CKGR_PLLR ( 12 ) /* PLL Register */ +/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */ +#define AT91C_CKGR_MOSCEN ( 0x1 << 0 ) /* (CKGR) Main Oscillator Enable */ +#define AT91C_CKGR_OSCBYPASS ( 0x1 << 1 ) /* (CKGR) Main Oscillator Bypass */ +#define AT91C_CKGR_OSCOUNT ( 0xFF << 8 ) /* (CKGR) Main Oscillator Start-up Time */ +/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */ +#define AT91C_CKGR_MAINF ( 0xFFFF << 0 ) /* (CKGR) Main Clock Frequency */ +#define AT91C_CKGR_MAINRDY ( 0x1 << 16 ) /* (CKGR) Main Clock Ready */ +/* -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- */ +#define AT91C_CKGR_DIV ( 0xFF << 0 ) /* (CKGR) Divider Selected */ +#define AT91C_CKGR_DIV_0 ( 0x0 ) /* (CKGR) Divider output is 0 */ +#define AT91C_CKGR_DIV_BYPASS ( 0x1 ) /* (CKGR) Divider is bypassed */ +#define AT91C_CKGR_PLLCOUNT ( 0x3F << 8 ) /* (CKGR) PLL Counter */ +#define AT91C_CKGR_OUT ( 0x3 << 14 ) /* (CKGR) PLL Output Frequency Range */ +#define AT91C_CKGR_OUT_0 ( 0x0 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_1 ( 0x1 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_2 ( 0x2 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_OUT_3 ( 0x3 << 14 ) /* (CKGR) Please refer to the PLL datasheet */ +#define AT91C_CKGR_MUL ( 0x7FF << 16 ) /* (CKGR) PLL Multiplier */ +#define AT91C_CKGR_USBDIV ( 0x3 << 28 ) /* (CKGR) Divider for USB Clocks */ +#define AT91C_CKGR_USBDIV_0 ( 0x0 << 28 ) /* (CKGR) Divider output is PLL clock output */ +#define AT91C_CKGR_USBDIV_1 ( 0x1 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 2 */ +#define AT91C_CKGR_USBDIV_2 ( 0x2 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 4 */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Power Management Controller */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_PMC structure *** */ +#define PMC_SCER ( 0 ) /* System Clock Enable Register */ +#define PMC_SCDR ( 4 ) /* System Clock Disable Register */ +#define PMC_SCSR ( 8 ) /* System Clock Status Register */ +#define PMC_PCER ( 16 ) /* Peripheral Clock Enable Register */ +#define PMC_PCDR ( 20 ) /* Peripheral Clock Disable Register */ +#define PMC_PCSR ( 24 ) /* Peripheral Clock Status Register */ +#define PMC_MOR ( 32 ) /* Main Oscillator Register */ +#define PMC_MCFR ( 36 ) /* Main Clock Frequency Register */ +#define PMC_PLLR ( 44 ) /* PLL Register */ +#define PMC_MCKR ( 48 ) /* Master Clock Register */ +#define PMC_PCKR ( 64 ) /* Programmable Clock Register */ +#define PMC_IER ( 96 ) /* Interrupt Enable Register */ +#define PMC_IDR ( 100 ) /* Interrupt Disable Register */ +#define PMC_SR ( 104 ) /* Status Register */ +#define PMC_IMR ( 108 ) /* Interrupt Mask Register */ +/* -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- */ +#define AT91C_PMC_PCK ( 0x1 << 0 ) /* (PMC) Processor Clock */ +#define AT91C_PMC_UDP ( 0x1 << 7 ) /* (PMC) USB Device Port Clock */ +#define AT91C_PMC_PCK0 ( 0x1 << 8 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK1 ( 0x1 << 9 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK2 ( 0x1 << 10 ) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK3 ( 0x1 << 11 ) /* (PMC) Programmable Clock Output */ +/* -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- */ +/* -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- */ +/* -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- */ +/* -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- */ +/* -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- */ +/* -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */ +#define AT91C_PMC_CSS ( 0x3 << 0 ) /* (PMC) Programmable Clock Selection */ +#define AT91C_PMC_CSS_SLOW_CLK ( 0x0 ) /* (PMC) Slow Clock is selected */ +#define AT91C_PMC_CSS_MAIN_CLK ( 0x1 ) /* (PMC) Main Clock is selected */ +#define AT91C_PMC_CSS_PLL_CLK ( 0x3 ) /* (PMC) Clock from PLL is selected */ +#define AT91C_PMC_PRES ( 0x7 << 2 ) /* (PMC) Programmable Clock Prescaler */ +#define AT91C_PMC_PRES_CLK ( 0x0 << 2 ) /* (PMC) Selected clock */ +#define AT91C_PMC_PRES_CLK_2 ( 0x1 << 2 ) /* (PMC) Selected clock divided by 2 */ +#define AT91C_PMC_PRES_CLK_4 ( 0x2 << 2 ) /* (PMC) Selected clock divided by 4 */ +#define AT91C_PMC_PRES_CLK_8 ( 0x3 << 2 ) /* (PMC) Selected clock divided by 8 */ +#define AT91C_PMC_PRES_CLK_16 ( 0x4 << 2 ) /* (PMC) Selected clock divided by 16 */ +#define AT91C_PMC_PRES_CLK_32 ( 0x5 << 2 ) /* (PMC) Selected clock divided by 32 */ +#define AT91C_PMC_PRES_CLK_64 ( 0x6 << 2 ) /* (PMC) Selected clock divided by 64 */ +/* -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- */ +/* -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- */ +#define AT91C_PMC_MOSCS ( 0x1 << 0 ) /* (PMC) MOSC Status/Enable/Disable/Mask */ +#define AT91C_PMC_LOCK ( 0x1 << 2 ) /* (PMC) PLL Status/Enable/Disable/Mask */ +#define AT91C_PMC_MCKRDY ( 0x1 << 3 ) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK0RDY ( 0x1 << 8 ) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK1RDY ( 0x1 << 9 ) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK2RDY ( 0x1 << 10 ) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK3RDY ( 0x1 << 11 ) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */ +/* -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */ +/* -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- */ +/* -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Reset Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_RSTC structure *** */ +#define RSTC_RCR ( 0 ) /* Reset Control Register */ +#define RSTC_RSR ( 4 ) /* Reset Status Register */ +#define RSTC_RMR ( 8 ) /* Reset Mode Register */ +/* -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- */ +#define AT91C_RSTC_PROCRST ( 0x1 << 0 ) /* (RSTC) Processor Reset */ +#define AT91C_RSTC_PERRST ( 0x1 << 2 ) /* (RSTC) Peripheral Reset */ +#define AT91C_RSTC_EXTRST ( 0x1 << 3 ) /* (RSTC) External Reset */ +#define AT91C_RSTC_KEY ( 0xFF << 24 ) /* (RSTC) Password */ +/* -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- */ +#define AT91C_RSTC_URSTS ( 0x1 << 0 ) /* (RSTC) User Reset Status */ +#define AT91C_RSTC_BODSTS ( 0x1 << 1 ) /* (RSTC) Brownout Detection Status */ +#define AT91C_RSTC_RSTTYP ( 0x7 << 8 ) /* (RSTC) Reset Type */ +#define AT91C_RSTC_RSTTYP_POWERUP ( 0x0 << 8 ) /* (RSTC) Power-up Reset. VDDCORE rising. */ +#define AT91C_RSTC_RSTTYP_WAKEUP ( 0x1 << 8 ) /* (RSTC) WakeUp Reset. VDDCORE rising. */ +#define AT91C_RSTC_RSTTYP_WATCHDOG ( 0x2 << 8 ) /* (RSTC) Watchdog Reset. Watchdog overflow occurred. */ +#define AT91C_RSTC_RSTTYP_SOFTWARE ( 0x3 << 8 ) /* (RSTC) Software Reset. Processor reset required by the software. */ +#define AT91C_RSTC_RSTTYP_USER ( 0x4 << 8 ) /* (RSTC) User Reset. NRST pin detected low. */ +#define AT91C_RSTC_RSTTYP_BROWNOUT ( 0x5 << 8 ) /* (RSTC) Brownout Reset occurred. */ +#define AT91C_RSTC_NRSTL ( 0x1 << 16 ) /* (RSTC) NRST pin level */ +#define AT91C_RSTC_SRCMP ( 0x1 << 17 ) /* (RSTC) Software Reset Command in Progress. */ +/* -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- */ +#define AT91C_RSTC_URSTEN ( 0x1 << 0 ) /* (RSTC) User Reset Enable */ +#define AT91C_RSTC_URSTIEN ( 0x1 << 4 ) /* (RSTC) User Reset Interrupt Enable */ +#define AT91C_RSTC_ERSTL ( 0xF << 8 ) /* (RSTC) User Reset Enable */ +#define AT91C_RSTC_BODIEN ( 0x1 << 16 ) /* (RSTC) Brownout Detection Interrupt Enable */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_RTTC structure *** */ +#define RTTC_RTMR ( 0 ) /* Real-time Mode Register */ +#define RTTC_RTAR ( 4 ) /* Real-time Alarm Register */ +#define RTTC_RTVR ( 8 ) /* Real-time Value Register */ +#define RTTC_RTSR ( 12 ) /* Real-time Status Register */ +/* -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- */ +#define AT91C_RTTC_RTPRES ( 0xFFFF << 0 ) /* (RTTC) Real-time Timer Prescaler Value */ +#define AT91C_RTTC_ALMIEN ( 0x1 << 16 ) /* (RTTC) Alarm Interrupt Enable */ +#define AT91C_RTTC_RTTINCIEN ( 0x1 << 17 ) /* (RTTC) Real Time Timer Increment Interrupt Enable */ +#define AT91C_RTTC_RTTRST ( 0x1 << 18 ) /* (RTTC) Real Time Timer Restart */ +/* -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- */ +#define AT91C_RTTC_ALMV ( 0x0 << 0 ) /* (RTTC) Alarm Value */ +/* -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- */ +#define AT91C_RTTC_CRTV ( 0x0 << 0 ) /* (RTTC) Current Real-time Value */ +/* -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- */ +#define AT91C_RTTC_ALMS ( 0x1 << 0 ) /* (RTTC) Real-time Alarm Status */ +#define AT91C_RTTC_RTTINC ( 0x1 << 1 ) /* (RTTC) Real-time Timer Increment */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_PITC structure *** */ +#define PITC_PIMR ( 0 ) /* Period Interval Mode Register */ +#define PITC_PISR ( 4 ) /* Period Interval Status Register */ +#define PITC_PIVR ( 8 ) /* Period Interval Value Register */ +#define PITC_PIIR ( 12 ) /* Period Interval Image Register */ +/* -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- */ +#define AT91C_PITC_PIV ( 0xFFFFF << 0 ) /* (PITC) Periodic Interval Value */ +#define AT91C_PITC_PITEN ( 0x1 << 24 ) /* (PITC) Periodic Interval Timer Enabled */ +#define AT91C_PITC_PITIEN ( 0x1 << 25 ) /* (PITC) Periodic Interval Timer Interrupt Enable */ +/* -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- */ +#define AT91C_PITC_PITS ( 0x1 << 0 ) /* (PITC) Periodic Interval Timer Status */ +/* -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- */ +#define AT91C_PITC_CPIV ( 0xFFFFF << 0 ) /* (PITC) Current Periodic Interval Value */ +#define AT91C_PITC_PICNT ( 0xFFF << 20 ) /* (PITC) Periodic Interval Counter */ +/* -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_WDTC structure *** */ +#define WDTC_WDCR ( 0 ) /* Watchdog Control Register */ +#define WDTC_WDMR ( 4 ) /* Watchdog Mode Register */ +#define WDTC_WDSR ( 8 ) /* Watchdog Status Register */ +/* -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- */ +#define AT91C_WDTC_WDRSTT ( 0x1 << 0 ) /* (WDTC) Watchdog Restart */ +#define AT91C_WDTC_KEY ( 0xFF << 24 ) /* (WDTC) Watchdog KEY Password */ +/* -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */ +#define AT91C_WDTC_WDV ( 0xFFF << 0 ) /* (WDTC) Watchdog Timer Restart */ +#define AT91C_WDTC_WDFIEN ( 0x1 << 12 ) /* (WDTC) Watchdog Fault Interrupt Enable */ +#define AT91C_WDTC_WDRSTEN ( 0x1 << 13 ) /* (WDTC) Watchdog Reset Enable */ +#define AT91C_WDTC_WDRPROC ( 0x1 << 14 ) /* (WDTC) Watchdog Timer Restart */ +#define AT91C_WDTC_WDDIS ( 0x1 << 15 ) /* (WDTC) Watchdog Disable */ +#define AT91C_WDTC_WDD ( 0xFFF << 16 ) /* (WDTC) Watchdog Delta Value */ +#define AT91C_WDTC_WDDBGHLT ( 0x1 << 28 ) /* (WDTC) Watchdog Debug Halt */ +#define AT91C_WDTC_WDIDLEHLT ( 0x1 << 29 ) /* (WDTC) Watchdog Idle Halt */ +/* -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- */ +#define AT91C_WDTC_WDUNF ( 0x1 << 0 ) /* (WDTC) Watchdog Underflow */ +#define AT91C_WDTC_WDERR ( 0x1 << 1 ) /* (WDTC) Watchdog Error */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_VREG structure *** */ +#define VREG_MR ( 0 ) /* Voltage Regulator Mode Register */ +/* -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- */ +#define AT91C_VREG_PSTDBY ( 0x1 << 0 ) /* (VREG) Voltage Regulator Power Standby Mode */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Memory Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_MC structure *** */ +#define MC_RCR ( 0 ) /* MC Remap Control Register */ +#define MC_ASR ( 4 ) /* MC Abort Status Register */ +#define MC_AASR ( 8 ) /* MC Abort Address Status Register */ +#define MC_FMR ( 96 ) /* MC Flash Mode Register */ +#define MC_FCR ( 100 ) /* MC Flash Command Register */ +#define MC_FSR ( 104 ) /* MC Flash Status Register */ +/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */ +#define AT91C_MC_RCB ( 0x1 << 0 ) /* (MC) Remap Command Bit */ +/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */ +#define AT91C_MC_UNDADD ( 0x1 << 0 ) /* (MC) Undefined Address Abort Status */ +#define AT91C_MC_MISADD ( 0x1 << 1 ) /* (MC) Misaligned Address Abort Status */ +#define AT91C_MC_ABTSZ ( 0x3 << 8 ) /* (MC) Abort Size Status */ +#define AT91C_MC_ABTSZ_BYTE ( 0x0 << 8 ) /* (MC) Byte */ +#define AT91C_MC_ABTSZ_HWORD ( 0x1 << 8 ) /* (MC) Half-word */ +#define AT91C_MC_ABTSZ_WORD ( 0x2 << 8 ) /* (MC) Word */ +#define AT91C_MC_ABTTYP ( 0x3 << 10 ) /* (MC) Abort Type Status */ +#define AT91C_MC_ABTTYP_DATAR ( 0x0 << 10 ) /* (MC) Data Read */ +#define AT91C_MC_ABTTYP_DATAW ( 0x1 << 10 ) /* (MC) Data Write */ +#define AT91C_MC_ABTTYP_FETCH ( 0x2 << 10 ) /* (MC) Code Fetch */ +#define AT91C_MC_MST0 ( 0x1 << 16 ) /* (MC) Master 0 Abort Source */ +#define AT91C_MC_MST1 ( 0x1 << 17 ) /* (MC) Master 1 Abort Source */ +#define AT91C_MC_SVMST0 ( 0x1 << 24 ) /* (MC) Saved Master 0 Abort Source */ +#define AT91C_MC_SVMST1 ( 0x1 << 25 ) /* (MC) Saved Master 1 Abort Source */ +/* -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- */ +#define AT91C_MC_FRDY ( 0x1 << 0 ) /* (MC) Flash Ready */ +#define AT91C_MC_LOCKE ( 0x1 << 2 ) /* (MC) Lock Error */ +#define AT91C_MC_PROGE ( 0x1 << 3 ) /* (MC) Programming Error */ +#define AT91C_MC_NEBP ( 0x1 << 7 ) /* (MC) No Erase Before Programming */ +#define AT91C_MC_FWS ( 0x3 << 8 ) /* (MC) Flash Wait State */ +#define AT91C_MC_FWS_0FWS ( 0x0 << 8 ) /* (MC) 1 cycle for Read, 2 for Write operations */ +#define AT91C_MC_FWS_1FWS ( 0x1 << 8 ) /* (MC) 2 cycles for Read, 3 for Write operations */ +#define AT91C_MC_FWS_2FWS ( 0x2 << 8 ) /* (MC) 3 cycles for Read, 4 for Write operations */ +#define AT91C_MC_FWS_3FWS ( 0x3 << 8 ) /* (MC) 4 cycles for Read, 4 for Write operations */ +#define AT91C_MC_FMCN ( 0xFF << 16 ) /* (MC) Flash Microsecond Cycle Number */ +/* -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- */ +#define AT91C_MC_FCMD ( 0xF << 0 ) /* (MC) Flash Command */ +#define AT91C_MC_FCMD_START_PROG ( 0x1 ) /* (MC) Starts the programming of th epage specified by PAGEN. */ +#define AT91C_MC_FCMD_LOCK ( 0x2 ) /* (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */ +#define AT91C_MC_FCMD_PROG_AND_LOCK ( 0x3 ) /* (MC) The lock sequence automatically happens after the programming sequence is completed. */ +#define AT91C_MC_FCMD_UNLOCK ( 0x4 ) /* (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */ +#define AT91C_MC_FCMD_ERASE_ALL ( 0x8 ) /* (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. */ +#define AT91C_MC_FCMD_SET_GP_NVM ( 0xB ) /* (MC) Set General Purpose NVM bits. */ +#define AT91C_MC_FCMD_CLR_GP_NVM ( 0xD ) /* (MC) Clear General Purpose NVM bits. */ +#define AT91C_MC_FCMD_SET_SECURITY ( 0xF ) /* (MC) Set Security Bit. */ +#define AT91C_MC_PAGEN ( 0x3FF << 8 ) /* (MC) Page Number */ +#define AT91C_MC_KEY ( 0xFF << 24 ) /* (MC) Writing Protect Key */ +/* -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- */ +#define AT91C_MC_SECURITY ( 0x1 << 4 ) /* (MC) Security Bit Status */ +#define AT91C_MC_GPNVM0 ( 0x1 << 8 ) /* (MC) Sector 0 Lock Status */ +#define AT91C_MC_GPNVM1 ( 0x1 << 9 ) /* (MC) Sector 1 Lock Status */ +#define AT91C_MC_GPNVM2 ( 0x1 << 10 ) /* (MC) Sector 2 Lock Status */ +#define AT91C_MC_GPNVM3 ( 0x1 << 11 ) /* (MC) Sector 3 Lock Status */ +#define AT91C_MC_GPNVM4 ( 0x1 << 12 ) /* (MC) Sector 4 Lock Status */ +#define AT91C_MC_GPNVM5 ( 0x1 << 13 ) /* (MC) Sector 5 Lock Status */ +#define AT91C_MC_GPNVM6 ( 0x1 << 14 ) /* (MC) Sector 6 Lock Status */ +#define AT91C_MC_GPNVM7 ( 0x1 << 15 ) /* (MC) Sector 7 Lock Status */ +#define AT91C_MC_LOCKS0 ( 0x1 << 16 ) /* (MC) Sector 0 Lock Status */ +#define AT91C_MC_LOCKS1 ( 0x1 << 17 ) /* (MC) Sector 1 Lock Status */ +#define AT91C_MC_LOCKS2 ( 0x1 << 18 ) /* (MC) Sector 2 Lock Status */ +#define AT91C_MC_LOCKS3 ( 0x1 << 19 ) /* (MC) Sector 3 Lock Status */ +#define AT91C_MC_LOCKS4 ( 0x1 << 20 ) /* (MC) Sector 4 Lock Status */ +#define AT91C_MC_LOCKS5 ( 0x1 << 21 ) /* (MC) Sector 5 Lock Status */ +#define AT91C_MC_LOCKS6 ( 0x1 << 22 ) /* (MC) Sector 6 Lock Status */ +#define AT91C_MC_LOCKS7 ( 0x1 << 23 ) /* (MC) Sector 7 Lock Status */ +#define AT91C_MC_LOCKS8 ( 0x1 << 24 ) /* (MC) Sector 8 Lock Status */ +#define AT91C_MC_LOCKS9 ( 0x1 << 25 ) /* (MC) Sector 9 Lock Status */ +#define AT91C_MC_LOCKS10 ( 0x1 << 26 ) /* (MC) Sector 10 Lock Status */ +#define AT91C_MC_LOCKS11 ( 0x1 << 27 ) /* (MC) Sector 11 Lock Status */ +#define AT91C_MC_LOCKS12 ( 0x1 << 28 ) /* (MC) Sector 12 Lock Status */ +#define AT91C_MC_LOCKS13 ( 0x1 << 29 ) /* (MC) Sector 13 Lock Status */ +#define AT91C_MC_LOCKS14 ( 0x1 << 30 ) /* (MC) Sector 14 Lock Status */ +#define AT91C_MC_LOCKS15 ( 0x1 << 31 ) /* (MC) Sector 15 Lock Status */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_SPI structure *** */ +#define SPI_CR ( 0 ) /* Control Register */ +#define SPI_MR ( 4 ) /* Mode Register */ +#define SPI_RDR ( 8 ) /* Receive Data Register */ +#define SPI_TDR ( 12 ) /* Transmit Data Register */ +#define SPI_SR ( 16 ) /* Status Register */ +#define SPI_IER ( 20 ) /* Interrupt Enable Register */ +#define SPI_IDR ( 24 ) /* Interrupt Disable Register */ +#define SPI_IMR ( 28 ) /* Interrupt Mask Register */ +#define SPI_CSR ( 48 ) /* Chip Select Register */ +#define SPI_RPR ( 256 ) /* Receive Pointer Register */ +#define SPI_RCR ( 260 ) /* Receive Counter Register */ +#define SPI_TPR ( 264 ) /* Transmit Pointer Register */ +#define SPI_TCR ( 268 ) /* Transmit Counter Register */ +#define SPI_RNPR ( 272 ) /* Receive Next Pointer Register */ +#define SPI_RNCR ( 276 ) /* Receive Next Counter Register */ +#define SPI_TNPR ( 280 ) /* Transmit Next Pointer Register */ +#define SPI_TNCR ( 284 ) /* Transmit Next Counter Register */ +#define SPI_PTCR ( 288 ) /* PDC Transfer Control Register */ +#define SPI_PTSR ( 292 ) /* PDC Transfer Status Register */ +/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */ +#define AT91C_SPI_SPIEN ( 0x1 << 0 ) /* (SPI) SPI Enable */ +#define AT91C_SPI_SPIDIS ( 0x1 << 1 ) /* (SPI) SPI Disable */ +#define AT91C_SPI_SWRST ( 0x1 << 7 ) /* (SPI) SPI Software reset */ +#define AT91C_SPI_LASTXFER ( 0x1 << 24 ) /* (SPI) SPI Last Transfer */ +/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */ +#define AT91C_SPI_MSTR ( 0x1 << 0 ) /* (SPI) Master/Slave Mode */ +#define AT91C_SPI_PS ( 0x1 << 1 ) /* (SPI) Peripheral Select */ +#define AT91C_SPI_PS_FIXED ( 0x0 << 1 ) /* (SPI) Fixed Peripheral Select */ +#define AT91C_SPI_PS_VARIABLE ( 0x1 << 1 ) /* (SPI) Variable Peripheral Select */ +#define AT91C_SPI_PCSDEC ( 0x1 << 2 ) /* (SPI) Chip Select Decode */ +#define AT91C_SPI_FDIV ( 0x1 << 3 ) /* (SPI) Clock Selection */ +#define AT91C_SPI_MODFDIS ( 0x1 << 4 ) /* (SPI) Mode Fault Detection */ +#define AT91C_SPI_LLB ( 0x1 << 7 ) /* (SPI) Clock Selection */ +#define AT91C_SPI_PCS ( 0xF << 16 ) /* (SPI) Peripheral Chip Select */ +#define AT91C_SPI_DLYBCS ( 0xFF << 24 ) /* (SPI) Delay Between Chip Selects */ +/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */ +#define AT91C_SPI_RD ( 0xFFFF << 0 ) /* (SPI) Receive Data */ +#define AT91C_SPI_RPCS ( 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */ +/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */ +#define AT91C_SPI_TD ( 0xFFFF << 0 ) /* (SPI) Transmit Data */ +#define AT91C_SPI_TPCS ( 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */ +/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ +#define AT91C_SPI_RDRF ( 0x1 << 0 ) /* (SPI) Receive Data Register Full */ +#define AT91C_SPI_TDRE ( 0x1 << 1 ) /* (SPI) Transmit Data Register Empty */ +#define AT91C_SPI_MODF ( 0x1 << 2 ) /* (SPI) Mode Fault Error */ +#define AT91C_SPI_OVRES ( 0x1 << 3 ) /* (SPI) Overrun Error Status */ +#define AT91C_SPI_ENDRX ( 0x1 << 4 ) /* (SPI) End of Receiver Transfer */ +#define AT91C_SPI_ENDTX ( 0x1 << 5 ) /* (SPI) End of Receiver Transfer */ +#define AT91C_SPI_RXBUFF ( 0x1 << 6 ) /* (SPI) RXBUFF Interrupt */ +#define AT91C_SPI_TXBUFE ( 0x1 << 7 ) /* (SPI) TXBUFE Interrupt */ +#define AT91C_SPI_NSSR ( 0x1 << 8 ) /* (SPI) NSSR Interrupt */ +#define AT91C_SPI_TXEMPTY ( 0x1 << 9 ) /* (SPI) TXEMPTY Interrupt */ +#define AT91C_SPI_SPIENS ( 0x1 << 16 ) /* (SPI) Enable Status */ +/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ +/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ +/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */ +/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */ +#define AT91C_SPI_CPOL ( 0x1 << 0 ) /* (SPI) Clock Polarity */ +#define AT91C_SPI_NCPHA ( 0x1 << 1 ) /* (SPI) Clock Phase */ +#define AT91C_SPI_CSAAT ( 0x1 << 3 ) /* (SPI) Chip Select Active After Transfer */ +#define AT91C_SPI_BITS ( 0xF << 4 ) /* (SPI) Bits Per Transfer */ +#define AT91C_SPI_BITS_8 ( 0x0 << 4 ) /* (SPI) 8 Bits Per transfer */ +#define AT91C_SPI_BITS_9 ( 0x1 << 4 ) /* (SPI) 9 Bits Per transfer */ +#define AT91C_SPI_BITS_10 ( 0x2 << 4 ) /* (SPI) 10 Bits Per transfer */ +#define AT91C_SPI_BITS_11 ( 0x3 << 4 ) /* (SPI) 11 Bits Per transfer */ +#define AT91C_SPI_BITS_12 ( 0x4 << 4 ) /* (SPI) 12 Bits Per transfer */ +#define AT91C_SPI_BITS_13 ( 0x5 << 4 ) /* (SPI) 13 Bits Per transfer */ +#define AT91C_SPI_BITS_14 ( 0x6 << 4 ) /* (SPI) 14 Bits Per transfer */ +#define AT91C_SPI_BITS_15 ( 0x7 << 4 ) /* (SPI) 15 Bits Per transfer */ +#define AT91C_SPI_BITS_16 ( 0x8 << 4 ) /* (SPI) 16 Bits Per transfer */ +#define AT91C_SPI_SCBR ( 0xFF << 8 ) /* (SPI) Serial Clock Baud Rate */ +#define AT91C_SPI_DLYBS ( 0xFF << 16 ) /* (SPI) Delay Before SPCK */ +#define AT91C_SPI_DLYBCT ( 0xFF << 24 ) /* (SPI) Delay Between Consecutive Transfers */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Usart */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_USART structure *** */ +#define US_CR ( 0 ) /* Control Register */ +#define US_MR ( 4 ) /* Mode Register */ +#define US_IER ( 8 ) /* Interrupt Enable Register */ +#define US_IDR ( 12 ) /* Interrupt Disable Register */ +#define US_IMR ( 16 ) /* Interrupt Mask Register */ +#define US_CSR ( 20 ) /* Channel Status Register */ +#define US_RHR ( 24 ) /* Receiver Holding Register */ +#define US_THR ( 28 ) /* Transmitter Holding Register */ +#define US_BRGR ( 32 ) /* Baud Rate Generator Register */ +#define US_RTOR ( 36 ) /* Receiver Time-out Register */ +#define US_TTGR ( 40 ) /* Transmitter Time-guard Register */ +#define US_FIDI ( 64 ) /* FI_DI_Ratio Register */ +#define US_NER ( 68 ) /* Nb Errors Register */ +#define US_IF ( 76 ) /* IRDA_FILTER Register */ +#define US_RPR ( 256 ) /* Receive Pointer Register */ +#define US_RCR ( 260 ) /* Receive Counter Register */ +#define US_TPR ( 264 ) /* Transmit Pointer Register */ +#define US_TCR ( 268 ) /* Transmit Counter Register */ +#define US_RNPR ( 272 ) /* Receive Next Pointer Register */ +#define US_RNCR ( 276 ) /* Receive Next Counter Register */ +#define US_TNPR ( 280 ) /* Transmit Next Pointer Register */ +#define US_TNCR ( 284 ) /* Transmit Next Counter Register */ +#define US_PTCR ( 288 ) /* PDC Transfer Control Register */ +#define US_PTSR ( 292 ) /* PDC Transfer Status Register */ +/* -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- */ +#define AT91C_US_STTBRK ( 0x1 << 9 ) /* (USART) Start Break */ +#define AT91C_US_STPBRK ( 0x1 << 10 ) /* (USART) Stop Break */ +#define AT91C_US_STTTO ( 0x1 << 11 ) /* (USART) Start Time-out */ +#define AT91C_US_SENDA ( 0x1 << 12 ) /* (USART) Send Address */ +#define AT91C_US_RSTIT ( 0x1 << 13 ) /* (USART) Reset Iterations */ +#define AT91C_US_RSTNACK ( 0x1 << 14 ) /* (USART) Reset Non Acknowledge */ +#define AT91C_US_RETTO ( 0x1 << 15 ) /* (USART) Rearm Time-out */ +#define AT91C_US_DTREN ( 0x1 << 16 ) /* (USART) Data Terminal ready Enable */ +#define AT91C_US_DTRDIS ( 0x1 << 17 ) /* (USART) Data Terminal ready Disable */ +#define AT91C_US_RTSEN ( 0x1 << 18 ) /* (USART) Request to Send enable */ +#define AT91C_US_RTSDIS ( 0x1 << 19 ) /* (USART) Request to Send Disable */ +/* -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- */ +#define AT91C_US_USMODE ( 0xF << 0 ) /* (USART) Usart mode */ +#define AT91C_US_USMODE_NORMAL ( 0x0 ) /* (USART) Normal */ +#define AT91C_US_USMODE_RS485 ( 0x1 ) /* (USART) RS485 */ +#define AT91C_US_USMODE_HWHSH ( 0x2 ) /* (USART) Hardware Handshaking */ +#define AT91C_US_USMODE_MODEM ( 0x3 ) /* (USART) Modem */ +#define AT91C_US_USMODE_ISO7816_0 ( 0x4 ) /* (USART) ISO7816 protocol: T = 0 */ +#define AT91C_US_USMODE_ISO7816_1 ( 0x6 ) /* (USART) ISO7816 protocol: T = 1 */ +#define AT91C_US_USMODE_IRDA ( 0x8 ) /* (USART) IrDA */ +#define AT91C_US_USMODE_SWHSH ( 0xC ) /* (USART) Software Handshaking */ +#define AT91C_US_CLKS ( 0x3 << 4 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */ +#define AT91C_US_CLKS_CLOCK ( 0x0 << 4 ) /* (USART) Clock */ +#define AT91C_US_CLKS_FDIV1 ( 0x1 << 4 ) /* (USART) fdiv1 */ +#define AT91C_US_CLKS_SLOW ( 0x2 << 4 ) /* (USART) slow_clock (ARM) */ +#define AT91C_US_CLKS_EXT ( 0x3 << 4 ) /* (USART) External (SCK) */ +#define AT91C_US_CHRL ( 0x3 << 6 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */ +#define AT91C_US_CHRL_5_BITS ( 0x0 << 6 ) /* (USART) Character Length: 5 bits */ +#define AT91C_US_CHRL_6_BITS ( 0x1 << 6 ) /* (USART) Character Length: 6 bits */ +#define AT91C_US_CHRL_7_BITS ( 0x2 << 6 ) /* (USART) Character Length: 7 bits */ +#define AT91C_US_CHRL_8_BITS ( 0x3 << 6 ) /* (USART) Character Length: 8 bits */ +#define AT91C_US_SYNC ( 0x1 << 8 ) /* (USART) Synchronous Mode Select */ +#define AT91C_US_NBSTOP ( 0x3 << 12 ) /* (USART) Number of Stop bits */ +#define AT91C_US_NBSTOP_1_BIT ( 0x0 << 12 ) /* (USART) 1 stop bit */ +#define AT91C_US_NBSTOP_15_BIT ( 0x1 << 12 ) /* (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */ +#define AT91C_US_NBSTOP_2_BIT ( 0x2 << 12 ) /* (USART) 2 stop bits */ +#define AT91C_US_MSBF ( 0x1 << 16 ) /* (USART) Bit Order */ +#define AT91C_US_MODE9 ( 0x1 << 17 ) /* (USART) 9-bit Character length */ +#define AT91C_US_CKLO ( 0x1 << 18 ) /* (USART) Clock Output Select */ +#define AT91C_US_OVER ( 0x1 << 19 ) /* (USART) Over Sampling Mode */ +#define AT91C_US_INACK ( 0x1 << 20 ) /* (USART) Inhibit Non Acknowledge */ +#define AT91C_US_DSNACK ( 0x1 << 21 ) /* (USART) Disable Successive NACK */ +#define AT91C_US_MAX_ITER ( 0x1 << 24 ) /* (USART) Number of Repetitions */ +#define AT91C_US_FILTER ( 0x1 << 28 ) /* (USART) Receive Line Filter */ +/* -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ +#define AT91C_US_RXBRK ( 0x1 << 2 ) /* (USART) Break Received/End of Break */ +#define AT91C_US_TIMEOUT ( 0x1 << 8 ) /* (USART) Receiver Time-out */ +#define AT91C_US_ITERATION ( 0x1 << 10 ) /* (USART) Max number of Repetitions Reached */ +#define AT91C_US_NACK ( 0x1 << 13 ) /* (USART) Non Acknowledge */ +#define AT91C_US_RIIC ( 0x1 << 16 ) /* (USART) Ring INdicator Input Change Flag */ +#define AT91C_US_DSRIC ( 0x1 << 17 ) /* (USART) Data Set Ready Input Change Flag */ +#define AT91C_US_DCDIC ( 0x1 << 18 ) /* (USART) Data Carrier Flag */ +#define AT91C_US_CTSIC ( 0x1 << 19 ) /* (USART) Clear To Send Input Change Flag */ +/* -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- */ +/* -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- */ +/* -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- */ +#define AT91C_US_RI ( 0x1 << 20 ) /* (USART) Image of RI Input */ +#define AT91C_US_DSR ( 0x1 << 21 ) /* (USART) Image of DSR Input */ +#define AT91C_US_DCD ( 0x1 << 22 ) /* (USART) Image of DCD Input */ +#define AT91C_US_CTS ( 0x1 << 23 ) /* (USART) Image of CTS Input */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_SSC structure *** */ +#define SSC_CR ( 0 ) /* Control Register */ +#define SSC_CMR ( 4 ) /* Clock Mode Register */ +#define SSC_RCMR ( 16 ) /* Receive Clock ModeRegister */ +#define SSC_RFMR ( 20 ) /* Receive Frame Mode Register */ +#define SSC_TCMR ( 24 ) /* Transmit Clock Mode Register */ +#define SSC_TFMR ( 28 ) /* Transmit Frame Mode Register */ +#define SSC_RHR ( 32 ) /* Receive Holding Register */ +#define SSC_THR ( 36 ) /* Transmit Holding Register */ +#define SSC_RSHR ( 48 ) /* Receive Sync Holding Register */ +#define SSC_TSHR ( 52 ) /* Transmit Sync Holding Register */ +#define SSC_SR ( 64 ) /* Status Register */ +#define SSC_IER ( 68 ) /* Interrupt Enable Register */ +#define SSC_IDR ( 72 ) /* Interrupt Disable Register */ +#define SSC_IMR ( 76 ) /* Interrupt Mask Register */ +#define SSC_RPR ( 256 ) /* Receive Pointer Register */ +#define SSC_RCR ( 260 ) /* Receive Counter Register */ +#define SSC_TPR ( 264 ) /* Transmit Pointer Register */ +#define SSC_TCR ( 268 ) /* Transmit Counter Register */ +#define SSC_RNPR ( 272 ) /* Receive Next Pointer Register */ +#define SSC_RNCR ( 276 ) /* Receive Next Counter Register */ +#define SSC_TNPR ( 280 ) /* Transmit Next Pointer Register */ +#define SSC_TNCR ( 284 ) /* Transmit Next Counter Register */ +#define SSC_PTCR ( 288 ) /* PDC Transfer Control Register */ +#define SSC_PTSR ( 292 ) /* PDC Transfer Status Register */ +/* -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- */ +#define AT91C_SSC_RXEN ( 0x1 << 0 ) /* (SSC) Receive Enable */ +#define AT91C_SSC_RXDIS ( 0x1 << 1 ) /* (SSC) Receive Disable */ +#define AT91C_SSC_TXEN ( 0x1 << 8 ) /* (SSC) Transmit Enable */ +#define AT91C_SSC_TXDIS ( 0x1 << 9 ) /* (SSC) Transmit Disable */ +#define AT91C_SSC_SWRST ( 0x1 << 15 ) /* (SSC) Software Reset */ +/* -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- */ +#define AT91C_SSC_CKS ( 0x3 << 0 ) /* (SSC) Receive/Transmit Clock Selection */ +#define AT91C_SSC_CKS_DIV ( 0x0 ) /* (SSC) Divided Clock */ +#define AT91C_SSC_CKS_TK ( 0x1 ) /* (SSC) TK Clock signal */ +#define AT91C_SSC_CKS_RK ( 0x2 ) /* (SSC) RK pin */ +#define AT91C_SSC_CKO ( 0x7 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode Selection */ +#define AT91C_SSC_CKO_NONE ( 0x0 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only */ +#define AT91C_SSC_CKO_CONTINUOUS ( 0x1 << 2 ) /* (SSC) Continuous Receive/Transmit Clock RK pin: Output */ +#define AT91C_SSC_CKO_DATA_TX ( 0x2 << 2 ) /* (SSC) Receive/Transmit Clock only during data transfers RK pin: Output */ +#define AT91C_SSC_CKI ( 0x1 << 5 ) /* (SSC) Receive/Transmit Clock Inversion */ +#define AT91C_SSC_START ( 0xF << 8 ) /* (SSC) Receive/Transmit Start Selection */ +#define AT91C_SSC_START_CONTINUOUS ( 0x0 << 8 ) /* (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */ +#define AT91C_SSC_START_TX ( 0x1 << 8 ) /* (SSC) Transmit/Receive start */ +#define AT91C_SSC_START_LOW_RF ( 0x2 << 8 ) /* (SSC) Detection of a low level on RF input */ +#define AT91C_SSC_START_HIGH_RF ( 0x3 << 8 ) /* (SSC) Detection of a high level on RF input */ +#define AT91C_SSC_START_FALL_RF ( 0x4 << 8 ) /* (SSC) Detection of a falling edge on RF input */ +#define AT91C_SSC_START_RISE_RF ( 0x5 << 8 ) /* (SSC) Detection of a rising edge on RF input */ +#define AT91C_SSC_START_LEVEL_RF ( 0x6 << 8 ) /* (SSC) Detection of any level change on RF input */ +#define AT91C_SSC_START_EDGE_RF ( 0x7 << 8 ) /* (SSC) Detection of any edge on RF input */ +#define AT91C_SSC_START_0 ( 0x8 << 8 ) /* (SSC) Compare 0 */ +#define AT91C_SSC_STTDLY ( 0xFF << 16 ) /* (SSC) Receive/Transmit Start Delay */ +#define AT91C_SSC_PERIOD ( 0xFF << 24 ) /* (SSC) Receive/Transmit Period Divider Selection */ +/* -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- */ +#define AT91C_SSC_DATLEN ( 0x1F << 0 ) /* (SSC) Data Length */ +#define AT91C_SSC_LOOP ( 0x1 << 5 ) /* (SSC) Loop Mode */ +#define AT91C_SSC_MSBF ( 0x1 << 7 ) /* (SSC) Most Significant Bit First */ +#define AT91C_SSC_DATNB ( 0xF << 8 ) /* (SSC) Data Number per Frame */ +#define AT91C_SSC_FSLEN ( 0xF << 16 ) /* (SSC) Receive/Transmit Frame Sync length */ +#define AT91C_SSC_FSOS ( 0x7 << 20 ) /* (SSC) Receive/Transmit Frame Sync Output Selection */ +#define AT91C_SSC_FSOS_NONE ( 0x0 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only */ +#define AT91C_SSC_FSOS_NEGATIVE ( 0x1 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse */ +#define AT91C_SSC_FSOS_POSITIVE ( 0x2 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse */ +#define AT91C_SSC_FSOS_LOW ( 0x3 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer */ +#define AT91C_SSC_FSOS_HIGH ( 0x4 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer */ +#define AT91C_SSC_FSOS_TOGGLE ( 0x5 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer */ +#define AT91C_SSC_FSEDGE ( 0x1 << 24 ) /* (SSC) Frame Sync Edge Detection */ +/* -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- */ +/* -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- */ +#define AT91C_SSC_DATDEF ( 0x1 << 5 ) /* (SSC) Data Default Value */ +#define AT91C_SSC_FSDEN ( 0x1 << 23 ) /* (SSC) Frame Sync Data Enable */ +/* -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- */ +#define AT91C_SSC_TXRDY ( 0x1 << 0 ) /* (SSC) Transmit Ready */ +#define AT91C_SSC_TXEMPTY ( 0x1 << 1 ) /* (SSC) Transmit Empty */ +#define AT91C_SSC_ENDTX ( 0x1 << 2 ) /* (SSC) End Of Transmission */ +#define AT91C_SSC_TXBUFE ( 0x1 << 3 ) /* (SSC) Transmit Buffer Empty */ +#define AT91C_SSC_RXRDY ( 0x1 << 4 ) /* (SSC) Receive Ready */ +#define AT91C_SSC_OVRUN ( 0x1 << 5 ) /* (SSC) Receive Overrun */ +#define AT91C_SSC_ENDRX ( 0x1 << 6 ) /* (SSC) End of Reception */ +#define AT91C_SSC_RXBUFF ( 0x1 << 7 ) /* (SSC) Receive Buffer Full */ +#define AT91C_SSC_TXSYN ( 0x1 << 10 ) /* (SSC) Transmit Sync */ +#define AT91C_SSC_RXSYN ( 0x1 << 11 ) /* (SSC) Receive Sync */ +#define AT91C_SSC_TXENA ( 0x1 << 16 ) /* (SSC) Transmit Enable */ +#define AT91C_SSC_RXENA ( 0x1 << 17 ) /* (SSC) Receive Enable */ +/* -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- */ +/* -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- */ +/* -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Two-wire Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_TWI structure *** */ +#define TWI_CR ( 0 ) /* Control Register */ +#define TWI_MMR ( 4 ) /* Master Mode Register */ +#define TWI_IADR ( 12 ) /* Internal Address Register */ +#define TWI_CWGR ( 16 ) /* Clock Waveform Generator Register */ +#define TWI_SR ( 32 ) /* Status Register */ +#define TWI_IER ( 36 ) /* Interrupt Enable Register */ +#define TWI_IDR ( 40 ) /* Interrupt Disable Register */ +#define TWI_IMR ( 44 ) /* Interrupt Mask Register */ +#define TWI_RHR ( 48 ) /* Receive Holding Register */ +#define TWI_THR ( 52 ) /* Transmit Holding Register */ +/* -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */ +#define AT91C_TWI_START ( 0x1 << 0 ) /* (TWI) Send a START Condition */ +#define AT91C_TWI_STOP ( 0x1 << 1 ) /* (TWI) Send a STOP Condition */ +#define AT91C_TWI_MSEN ( 0x1 << 2 ) /* (TWI) TWI Master Transfer Enabled */ +#define AT91C_TWI_MSDIS ( 0x1 << 3 ) /* (TWI) TWI Master Transfer Disabled */ +#define AT91C_TWI_SWRST ( 0x1 << 7 ) /* (TWI) Software Reset */ +/* -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */ +#define AT91C_TWI_IADRSZ ( 0x3 << 8 ) /* (TWI) Internal Device Address Size */ +#define AT91C_TWI_IADRSZ_NO ( 0x0 << 8 ) /* (TWI) No internal device address */ +#define AT91C_TWI_IADRSZ_1_BYTE ( 0x1 << 8 ) /* (TWI) One-byte internal device address */ +#define AT91C_TWI_IADRSZ_2_BYTE ( 0x2 << 8 ) /* (TWI) Two-byte internal device address */ +#define AT91C_TWI_IADRSZ_3_BYTE ( 0x3 << 8 ) /* (TWI) Three-byte internal device address */ +#define AT91C_TWI_MREAD ( 0x1 << 12 ) /* (TWI) Master Read Direction */ +#define AT91C_TWI_DADR ( 0x7F << 16 ) /* (TWI) Device Address */ +/* -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */ +#define AT91C_TWI_CLDIV ( 0xFF << 0 ) /* (TWI) Clock Low Divider */ +#define AT91C_TWI_CHDIV ( 0xFF << 8 ) /* (TWI) Clock High Divider */ +#define AT91C_TWI_CKDIV ( 0x7 << 16 ) /* (TWI) Clock Divider */ +/* -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */ +#define AT91C_TWI_TXCOMP ( 0x1 << 0 ) /* (TWI) Transmission Completed */ +#define AT91C_TWI_RXRDY ( 0x1 << 1 ) /* (TWI) Receive holding register ReaDY */ +#define AT91C_TWI_TXRDY ( 0x1 << 2 ) /* (TWI) Transmit holding register ReaDY */ +#define AT91C_TWI_OVRE ( 0x1 << 6 ) /* (TWI) Overrun Error */ +#define AT91C_TWI_UNRE ( 0x1 << 7 ) /* (TWI) Underrun Error */ +#define AT91C_TWI_NACK ( 0x1 << 8 ) /* (TWI) Not Acknowledged */ +/* -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */ +/* -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- */ +/* -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR PWMC Channel Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_PWMC_CH structure *** */ +#define PWMC_CMR ( 0 ) /* Channel Mode Register */ +#define PWMC_CDTYR ( 4 ) /* Channel Duty Cycle Register */ +#define PWMC_CPRDR ( 8 ) /* Channel Period Register */ +#define PWMC_CCNTR ( 12 ) /* Channel Counter Register */ +#define PWMC_CUPDR ( 16 ) /* Channel Update Register */ +#define PWMC_Reserved ( 20 ) /* Reserved */ +/* -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- */ +#define AT91C_PWMC_CPRE ( 0xF << 0 ) /* (PWMC_CH) Channel Pre-scaler : PWMC_CLKx */ +#define AT91C_PWMC_CPRE_MCK ( 0x0 ) /* (PWMC_CH) */ +#define AT91C_PWMC_CPRE_MCKA ( 0xB ) /* (PWMC_CH) */ +#define AT91C_PWMC_CPRE_MCKB ( 0xC ) /* (PWMC_CH) */ +#define AT91C_PWMC_CALG ( 0x1 << 8 ) /* (PWMC_CH) Channel Alignment */ +#define AT91C_PWMC_CPOL ( 0x1 << 9 ) /* (PWMC_CH) Channel Polarity */ +#define AT91C_PWMC_CPD ( 0x1 << 10 ) /* (PWMC_CH) Channel Update Period */ +/* -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- */ +#define AT91C_PWMC_CDTY ( 0x0 << 0 ) /* (PWMC_CH) Channel Duty Cycle */ +/* -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- */ +#define AT91C_PWMC_CPRD ( 0x0 << 0 ) /* (PWMC_CH) Channel Period */ +/* -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- */ +#define AT91C_PWMC_CCNT ( 0x0 << 0 ) /* (PWMC_CH) Channel Counter */ +/* -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- */ +#define AT91C_PWMC_CUPD ( 0x0 << 0 ) /* (PWMC_CH) Channel Update */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_PWMC structure *** */ +#define PWMC_MR ( 0 ) /* PWMC Mode Register */ +#define PWMC_ENA ( 4 ) /* PWMC Enable Register */ +#define PWMC_DIS ( 8 ) /* PWMC Disable Register */ +#define PWMC_SR ( 12 ) /* PWMC Status Register */ +#define PWMC_IER ( 16 ) /* PWMC Interrupt Enable Register */ +#define PWMC_IDR ( 20 ) /* PWMC Interrupt Disable Register */ +#define PWMC_IMR ( 24 ) /* PWMC Interrupt Mask Register */ +#define PWMC_ISR ( 28 ) /* PWMC Interrupt Status Register */ +#define PWMC_VR ( 252 ) /* PWMC Version Register */ +#define PWMC_CH ( 512 ) /* PWMC Channel */ +/* -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- */ +#define AT91C_PWMC_DIVA ( 0xFF << 0 ) /* (PWMC) CLKA divide factor. */ +#define AT91C_PWMC_PREA ( 0xF << 8 ) /* (PWMC) Divider Input Clock Prescaler A */ +#define AT91C_PWMC_PREA_MCK ( 0x0 << 8 ) /* (PWMC) */ +#define AT91C_PWMC_DIVB ( 0xFF << 16 ) /* (PWMC) CLKB divide factor. */ +#define AT91C_PWMC_PREB ( 0xF << 24 ) /* (PWMC) Divider Input Clock Prescaler B */ +#define AT91C_PWMC_PREB_MCK ( 0x0 << 24 ) /* (PWMC) */ +/* -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- */ +#define AT91C_PWMC_CHID0 ( 0x1 << 0 ) /* (PWMC) Channel ID 0 */ +#define AT91C_PWMC_CHID1 ( 0x1 << 1 ) /* (PWMC) Channel ID 1 */ +#define AT91C_PWMC_CHID2 ( 0x1 << 2 ) /* (PWMC) Channel ID 2 */ +#define AT91C_PWMC_CHID3 ( 0x1 << 3 ) /* (PWMC) Channel ID 3 */ +/* -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- */ +/* -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- */ +/* -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- */ +/* -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- */ +/* -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- */ +/* -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR USB Device Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_UDP structure *** */ +#define UDP_NUM ( 0 ) /* Frame Number Register */ +#define UDP_GLBSTATE ( 4 ) /* Global State Register */ +#define UDP_FADDR ( 8 ) /* Function Address Register */ +#define UDP_IER ( 16 ) /* Interrupt Enable Register */ +#define UDP_IDR ( 20 ) /* Interrupt Disable Register */ +#define UDP_IMR ( 24 ) /* Interrupt Mask Register */ +#define UDP_ISR ( 28 ) /* Interrupt Status Register */ +#define UDP_ICR ( 32 ) /* Interrupt Clear Register */ +#define UDP_RSTEP ( 40 ) /* Reset Endpoint Register */ +#define UDP_CSR ( 48 ) /* Endpoint Control and Status Register */ +#define UDP_FDR ( 80 ) /* Endpoint FIFO Data Register */ +#define UDP_TXVC ( 116 ) /* Transceiver Control Register */ +/* -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- */ +#define AT91C_UDP_FRM_NUM ( 0x7FF << 0 ) /* (UDP) Frame Number as Defined in the Packet Field Formats */ +#define AT91C_UDP_FRM_ERR ( 0x1 << 16 ) /* (UDP) Frame Error */ +#define AT91C_UDP_FRM_OK ( 0x1 << 17 ) /* (UDP) Frame OK */ +/* -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- */ +#define AT91C_UDP_FADDEN ( 0x1 << 0 ) /* (UDP) Function Address Enable */ +#define AT91C_UDP_CONFG ( 0x1 << 1 ) /* (UDP) Configured */ +#define AT91C_UDP_ESR ( 0x1 << 2 ) /* (UDP) Enable Send Resume */ +#define AT91C_UDP_RSMINPR ( 0x1 << 3 ) /* (UDP) A Resume Has Been Sent to the Host */ +#define AT91C_UDP_RMWUPE ( 0x1 << 4 ) /* (UDP) Remote Wake Up Enable */ +/* -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- */ +#define AT91C_UDP_FADD ( 0xFF << 0 ) /* (UDP) Function Address Value */ +#define AT91C_UDP_FEN ( 0x1 << 8 ) /* (UDP) Function Enable */ +/* -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- */ +#define AT91C_UDP_EPINT0 ( 0x1 << 0 ) /* (UDP) Endpoint 0 Interrupt */ +#define AT91C_UDP_EPINT1 ( 0x1 << 1 ) /* (UDP) Endpoint 0 Interrupt */ +#define AT91C_UDP_EPINT2 ( 0x1 << 2 ) /* (UDP) Endpoint 2 Interrupt */ +#define AT91C_UDP_EPINT3 ( 0x1 << 3 ) /* (UDP) Endpoint 3 Interrupt */ +#define AT91C_UDP_EPINT4 ( 0x1 << 4 ) /* (UDP) Endpoint 4 Interrupt */ +#define AT91C_UDP_EPINT5 ( 0x1 << 5 ) /* (UDP) Endpoint 5 Interrupt */ +#define AT91C_UDP_RXSUSP ( 0x1 << 8 ) /* (UDP) USB Suspend Interrupt */ +#define AT91C_UDP_RXRSM ( 0x1 << 9 ) /* (UDP) USB Resume Interrupt */ +#define AT91C_UDP_EXTRSM ( 0x1 << 10 ) /* (UDP) USB External Resume Interrupt */ +#define AT91C_UDP_SOFINT ( 0x1 << 11 ) /* (UDP) USB Start Of frame Interrupt */ +#define AT91C_UDP_WAKEUP ( 0x1 << 13 ) /* (UDP) USB Resume Interrupt */ +/* -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- */ +/* -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- */ +/* -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- */ +#define AT91C_UDP_ENDBUSRES ( 0x1 << 12 ) /* (UDP) USB End Of Bus Reset Interrupt */ +/* -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- */ +/* -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- */ +#define AT91C_UDP_EP0 ( 0x1 << 0 ) /* (UDP) Reset Endpoint 0 */ +#define AT91C_UDP_EP1 ( 0x1 << 1 ) /* (UDP) Reset Endpoint 1 */ +#define AT91C_UDP_EP2 ( 0x1 << 2 ) /* (UDP) Reset Endpoint 2 */ +#define AT91C_UDP_EP3 ( 0x1 << 3 ) /* (UDP) Reset Endpoint 3 */ +#define AT91C_UDP_EP4 ( 0x1 << 4 ) /* (UDP) Reset Endpoint 4 */ +#define AT91C_UDP_EP5 ( 0x1 << 5 ) /* (UDP) Reset Endpoint 5 */ +/* -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- */ +#define AT91C_UDP_TXCOMP ( 0x1 << 0 ) /* (UDP) Generates an IN packet with data previously written in the DPR */ +#define AT91C_UDP_RX_DATA_BK0 ( 0x1 << 1 ) /* (UDP) Receive Data Bank 0 */ +#define AT91C_UDP_RXSETUP ( 0x1 << 2 ) /* (UDP) Sends STALL to the Host (Control endpoints) */ +#define AT91C_UDP_ISOERROR ( 0x1 << 3 ) /* (UDP) Isochronous error (Isochronous endpoints) */ +#define AT91C_UDP_TXPKTRDY ( 0x1 << 4 ) /* (UDP) Transmit Packet Ready */ +#define AT91C_UDP_FORCESTALL ( 0x1 << 5 ) /* (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). */ +#define AT91C_UDP_RX_DATA_BK1 ( 0x1 << 6 ) /* (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). */ +#define AT91C_UDP_DIR ( 0x1 << 7 ) /* (UDP) Transfer Direction */ +#define AT91C_UDP_EPTYPE ( 0x7 << 8 ) /* (UDP) Endpoint type */ +#define AT91C_UDP_EPTYPE_CTRL ( 0x0 << 8 ) /* (UDP) Control */ +#define AT91C_UDP_EPTYPE_ISO_OUT ( 0x1 << 8 ) /* (UDP) Isochronous OUT */ +#define AT91C_UDP_EPTYPE_BULK_OUT ( 0x2 << 8 ) /* (UDP) Bulk OUT */ +#define AT91C_UDP_EPTYPE_INT_OUT ( 0x3 << 8 ) /* (UDP) Interrupt OUT */ +#define AT91C_UDP_EPTYPE_ISO_IN ( 0x5 << 8 ) /* (UDP) Isochronous IN */ +#define AT91C_UDP_EPTYPE_BULK_IN ( 0x6 << 8 ) /* (UDP) Bulk IN */ +#define AT91C_UDP_EPTYPE_INT_IN ( 0x7 << 8 ) /* (UDP) Interrupt IN */ +#define AT91C_UDP_DTGLE ( 0x1 << 11 ) /* (UDP) Data Toggle */ +#define AT91C_UDP_EPEDS ( 0x1 << 15 ) /* (UDP) Endpoint Enable Disable */ +#define AT91C_UDP_RXBYTECNT ( 0x7FF << 16 ) /* (UDP) Number Of Bytes Available in the FIFO */ +/* -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- */ +#define AT91C_UDP_TXVDIS ( 0x1 << 8 ) /* (UDP) */ +#define AT91C_UDP_PUON ( 0x1 << 9 ) /* (UDP) Pull-up ON */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_TC structure *** */ +#define TC_CCR ( 0 ) /* Channel Control Register */ +#define TC_CMR ( 4 ) /* Channel Mode Register (Capture Mode / Waveform Mode) */ +#define TC_CV ( 16 ) /* Counter Value */ +#define TC_RA ( 20 ) /* Register A */ +#define TC_RB ( 24 ) /* Register B */ +#define TC_RC ( 28 ) /* Register C */ +#define TC_SR ( 32 ) /* Status Register */ +#define TC_IER ( 36 ) /* Interrupt Enable Register */ +#define TC_IDR ( 40 ) /* Interrupt Disable Register */ +#define TC_IMR ( 44 ) /* Interrupt Mask Register */ +/* -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- */ +#define AT91C_TC_CLKEN ( 0x1 << 0 ) /* (TC) Counter Clock Enable Command */ +#define AT91C_TC_CLKDIS ( 0x1 << 1 ) /* (TC) Counter Clock Disable Command */ +#define AT91C_TC_SWTRG ( 0x1 << 2 ) /* (TC) Software Trigger Command */ +/* -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- */ +#define AT91C_TC_CLKS ( 0x7 << 0 ) /* (TC) Clock Selection */ +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ( 0x0 ) /* (TC) Clock selected: TIMER_DIV1_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ( 0x1 ) /* (TC) Clock selected: TIMER_DIV2_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ( 0x2 ) /* (TC) Clock selected: TIMER_DIV3_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ( 0x3 ) /* (TC) Clock selected: TIMER_DIV4_CLOCK */ +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ( 0x4 ) /* (TC) Clock selected: TIMER_DIV5_CLOCK */ +#define AT91C_TC_CLKS_XC0 ( 0x5 ) /* (TC) Clock selected: XC0 */ +#define AT91C_TC_CLKS_XC1 ( 0x6 ) /* (TC) Clock selected: XC1 */ +#define AT91C_TC_CLKS_XC2 ( 0x7 ) /* (TC) Clock selected: XC2 */ +#define AT91C_TC_CLKI ( 0x1 << 3 ) /* (TC) Clock Invert */ +#define AT91C_TC_BURST ( 0x3 << 4 ) /* (TC) Burst Signal Selection */ +#define AT91C_TC_BURST_NONE ( 0x0 << 4 ) /* (TC) The clock is not gated by an external signal */ +#define AT91C_TC_BURST_XC0 ( 0x1 << 4 ) /* (TC) XC0 is ANDed with the selected clock */ +#define AT91C_TC_BURST_XC1 ( 0x2 << 4 ) /* (TC) XC1 is ANDed with the selected clock */ +#define AT91C_TC_BURST_XC2 ( 0x3 << 4 ) /* (TC) XC2 is ANDed with the selected clock */ +#define AT91C_TC_CPCSTOP ( 0x1 << 6 ) /* (TC) Counter Clock Stopped with RC Compare */ +#define AT91C_TC_LDBSTOP ( 0x1 << 6 ) /* (TC) Counter Clock Stopped with RB Loading */ +#define AT91C_TC_CPCDIS ( 0x1 << 7 ) /* (TC) Counter Clock Disable with RC Compare */ +#define AT91C_TC_LDBDIS ( 0x1 << 7 ) /* (TC) Counter Clock Disabled with RB Loading */ +#define AT91C_TC_ETRGEDG ( 0x3 << 8 ) /* (TC) External Trigger Edge Selection */ +#define AT91C_TC_ETRGEDG_NONE ( 0x0 << 8 ) /* (TC) Edge: None */ +#define AT91C_TC_ETRGEDG_RISING ( 0x1 << 8 ) /* (TC) Edge: rising edge */ +#define AT91C_TC_ETRGEDG_FALLING ( 0x2 << 8 ) /* (TC) Edge: falling edge */ +#define AT91C_TC_ETRGEDG_BOTH ( 0x3 << 8 ) /* (TC) Edge: each edge */ +#define AT91C_TC_EEVTEDG ( 0x3 << 8 ) /* (TC) External Event Edge Selection */ +#define AT91C_TC_EEVTEDG_NONE ( 0x0 << 8 ) /* (TC) Edge: None */ +#define AT91C_TC_EEVTEDG_RISING ( 0x1 << 8 ) /* (TC) Edge: rising edge */ +#define AT91C_TC_EEVTEDG_FALLING ( 0x2 << 8 ) /* (TC) Edge: falling edge */ +#define AT91C_TC_EEVTEDG_BOTH ( 0x3 << 8 ) /* (TC) Edge: each edge */ +#define AT91C_TC_EEVT ( 0x3 << 10 ) /* (TC) External Event Selection */ +#define AT91C_TC_EEVT_TIOB ( 0x0 << 10 ) /* (TC) Signal selected as external event: TIOB TIOB direction: input */ +#define AT91C_TC_EEVT_XC0 ( 0x1 << 10 ) /* (TC) Signal selected as external event: XC0 TIOB direction: output */ +#define AT91C_TC_EEVT_XC1 ( 0x2 << 10 ) /* (TC) Signal selected as external event: XC1 TIOB direction: output */ +#define AT91C_TC_EEVT_XC2 ( 0x3 << 10 ) /* (TC) Signal selected as external event: XC2 TIOB direction: output */ +#define AT91C_TC_ABETRG ( 0x1 << 10 ) /* (TC) TIOA or TIOB External Trigger Selection */ +#define AT91C_TC_ENETRG ( 0x1 << 12 ) /* (TC) External Event Trigger enable */ +#define AT91C_TC_WAVESEL ( 0x3 << 13 ) /* (TC) Waveform Selection */ +#define AT91C_TC_WAVESEL_UP ( 0x0 << 13 ) /* (TC) UP mode without atomatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UPDOWN ( 0x1 << 13 ) /* (TC) UPDOWN mode without automatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UP_AUTO ( 0x2 << 13 ) /* (TC) UP mode with automatic trigger on RC Compare */ +#define AT91C_TC_WAVESEL_UPDOWN_AUTO ( 0x3 << 13 ) /* (TC) UPDOWN mode with automatic trigger on RC Compare */ +#define AT91C_TC_CPCTRG ( 0x1 << 14 ) /* (TC) RC Compare Trigger Enable */ +#define AT91C_TC_WAVE ( 0x1 << 15 ) /* (TC) */ +#define AT91C_TC_ACPA ( 0x3 << 16 ) /* (TC) RA Compare Effect on TIOA */ +#define AT91C_TC_ACPA_NONE ( 0x0 << 16 ) /* (TC) Effect: none */ +#define AT91C_TC_ACPA_SET ( 0x1 << 16 ) /* (TC) Effect: set */ +#define AT91C_TC_ACPA_CLEAR ( 0x2 << 16 ) /* (TC) Effect: clear */ +#define AT91C_TC_ACPA_TOGGLE ( 0x3 << 16 ) /* (TC) Effect: toggle */ +#define AT91C_TC_LDRA ( 0x3 << 16 ) /* (TC) RA Loading Selection */ +#define AT91C_TC_LDRA_NONE ( 0x0 << 16 ) /* (TC) Edge: None */ +#define AT91C_TC_LDRA_RISING ( 0x1 << 16 ) /* (TC) Edge: rising edge of TIOA */ +#define AT91C_TC_LDRA_FALLING ( 0x2 << 16 ) /* (TC) Edge: falling edge of TIOA */ +#define AT91C_TC_LDRA_BOTH ( 0x3 << 16 ) /* (TC) Edge: each edge of TIOA */ +#define AT91C_TC_ACPC ( 0x3 << 18 ) /* (TC) RC Compare Effect on TIOA */ +#define AT91C_TC_ACPC_NONE ( 0x0 << 18 ) /* (TC) Effect: none */ +#define AT91C_TC_ACPC_SET ( 0x1 << 18 ) /* (TC) Effect: set */ +#define AT91C_TC_ACPC_CLEAR ( 0x2 << 18 ) /* (TC) Effect: clear */ +#define AT91C_TC_ACPC_TOGGLE ( 0x3 << 18 ) /* (TC) Effect: toggle */ +#define AT91C_TC_LDRB ( 0x3 << 18 ) /* (TC) RB Loading Selection */ +#define AT91C_TC_LDRB_NONE ( 0x0 << 18 ) /* (TC) Edge: None */ +#define AT91C_TC_LDRB_RISING ( 0x1 << 18 ) /* (TC) Edge: rising edge of TIOA */ +#define AT91C_TC_LDRB_FALLING ( 0x2 << 18 ) /* (TC) Edge: falling edge of TIOA */ +#define AT91C_TC_LDRB_BOTH ( 0x3 << 18 ) /* (TC) Edge: each edge of TIOA */ +#define AT91C_TC_AEEVT ( 0x3 << 20 ) /* (TC) External Event Effect on TIOA */ +#define AT91C_TC_AEEVT_NONE ( 0x0 << 20 ) /* (TC) Effect: none */ +#define AT91C_TC_AEEVT_SET ( 0x1 << 20 ) /* (TC) Effect: set */ +#define AT91C_TC_AEEVT_CLEAR ( 0x2 << 20 ) /* (TC) Effect: clear */ +#define AT91C_TC_AEEVT_TOGGLE ( 0x3 << 20 ) /* (TC) Effect: toggle */ +#define AT91C_TC_ASWTRG ( 0x3 << 22 ) /* (TC) Software Trigger Effect on TIOA */ +#define AT91C_TC_ASWTRG_NONE ( 0x0 << 22 ) /* (TC) Effect: none */ +#define AT91C_TC_ASWTRG_SET ( 0x1 << 22 ) /* (TC) Effect: set */ +#define AT91C_TC_ASWTRG_CLEAR ( 0x2 << 22 ) /* (TC) Effect: clear */ +#define AT91C_TC_ASWTRG_TOGGLE ( 0x3 << 22 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BCPB ( 0x3 << 24 ) /* (TC) RB Compare Effect on TIOB */ +#define AT91C_TC_BCPB_NONE ( 0x0 << 24 ) /* (TC) Effect: none */ +#define AT91C_TC_BCPB_SET ( 0x1 << 24 ) /* (TC) Effect: set */ +#define AT91C_TC_BCPB_CLEAR ( 0x2 << 24 ) /* (TC) Effect: clear */ +#define AT91C_TC_BCPB_TOGGLE ( 0x3 << 24 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BCPC ( 0x3 << 26 ) /* (TC) RC Compare Effect on TIOB */ +#define AT91C_TC_BCPC_NONE ( 0x0 << 26 ) /* (TC) Effect: none */ +#define AT91C_TC_BCPC_SET ( 0x1 << 26 ) /* (TC) Effect: set */ +#define AT91C_TC_BCPC_CLEAR ( 0x2 << 26 ) /* (TC) Effect: clear */ +#define AT91C_TC_BCPC_TOGGLE ( 0x3 << 26 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BEEVT ( 0x3 << 28 ) /* (TC) External Event Effect on TIOB */ +#define AT91C_TC_BEEVT_NONE ( 0x0 << 28 ) /* (TC) Effect: none */ +#define AT91C_TC_BEEVT_SET ( 0x1 << 28 ) /* (TC) Effect: set */ +#define AT91C_TC_BEEVT_CLEAR ( 0x2 << 28 ) /* (TC) Effect: clear */ +#define AT91C_TC_BEEVT_TOGGLE ( 0x3 << 28 ) /* (TC) Effect: toggle */ +#define AT91C_TC_BSWTRG ( 0x3 << 30 ) /* (TC) Software Trigger Effect on TIOB */ +#define AT91C_TC_BSWTRG_NONE ( 0x0 << 30 ) /* (TC) Effect: none */ +#define AT91C_TC_BSWTRG_SET ( 0x1 << 30 ) /* (TC) Effect: set */ +#define AT91C_TC_BSWTRG_CLEAR ( 0x2 << 30 ) /* (TC) Effect: clear */ +#define AT91C_TC_BSWTRG_TOGGLE ( 0x3 << 30 ) /* (TC) Effect: toggle */ +/* -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- */ +#define AT91C_TC_COVFS ( 0x1 << 0 ) /* (TC) Counter Overflow */ +#define AT91C_TC_LOVRS ( 0x1 << 1 ) /* (TC) Load Overrun */ +#define AT91C_TC_CPAS ( 0x1 << 2 ) /* (TC) RA Compare */ +#define AT91C_TC_CPBS ( 0x1 << 3 ) /* (TC) RB Compare */ +#define AT91C_TC_CPCS ( 0x1 << 4 ) /* (TC) RC Compare */ +#define AT91C_TC_LDRAS ( 0x1 << 5 ) /* (TC) RA Loading */ +#define AT91C_TC_LDRBS ( 0x1 << 6 ) /* (TC) RB Loading */ +#define AT91C_TC_ETRGS ( 0x1 << 7 ) /* (TC) External Trigger */ +#define AT91C_TC_CLKSTA ( 0x1 << 16 ) /* (TC) Clock Enabling */ +#define AT91C_TC_MTIOA ( 0x1 << 17 ) /* (TC) TIOA Mirror */ +#define AT91C_TC_MTIOB ( 0x1 << 18 ) /* (TC) TIOA Mirror */ +/* -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- */ +/* -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- */ +/* -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Timer Counter Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_TCB structure *** */ +#define TCB_TC0 ( 0 ) /* TC Channel 0 */ +#define TCB_TC1 ( 64 ) /* TC Channel 1 */ +#define TCB_TC2 ( 128 ) /* TC Channel 2 */ +#define TCB_BCR ( 192 ) /* TC Block Control Register */ +#define TCB_BMR ( 196 ) /* TC Block Mode Register */ +/* -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- */ +#define AT91C_TCB_SYNC ( 0x1 << 0 ) /* (TCB) Synchro Command */ +/* -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- */ +#define AT91C_TCB_TC0XC0S ( 0x3 << 0 ) /* (TCB) External Clock Signal 0 Selection */ +#define AT91C_TCB_TC0XC0S_TCLK0 ( 0x0 ) /* (TCB) TCLK0 connected to XC0 */ +#define AT91C_TCB_TC0XC0S_NONE ( 0x1 ) /* (TCB) None signal connected to XC0 */ +#define AT91C_TCB_TC0XC0S_TIOA1 ( 0x2 ) /* (TCB) TIOA1 connected to XC0 */ +#define AT91C_TCB_TC0XC0S_TIOA2 ( 0x3 ) /* (TCB) TIOA2 connected to XC0 */ +#define AT91C_TCB_TC1XC1S ( 0x3 << 2 ) /* (TCB) External Clock Signal 1 Selection */ +#define AT91C_TCB_TC1XC1S_TCLK1 ( 0x0 << 2 ) /* (TCB) TCLK1 connected to XC1 */ +#define AT91C_TCB_TC1XC1S_NONE ( 0x1 << 2 ) /* (TCB) None signal connected to XC1 */ +#define AT91C_TCB_TC1XC1S_TIOA0 ( 0x2 << 2 ) /* (TCB) TIOA0 connected to XC1 */ +#define AT91C_TCB_TC1XC1S_TIOA2 ( 0x3 << 2 ) /* (TCB) TIOA2 connected to XC1 */ +#define AT91C_TCB_TC2XC2S ( 0x3 << 4 ) /* (TCB) External Clock Signal 2 Selection */ +#define AT91C_TCB_TC2XC2S_TCLK2 ( 0x0 << 4 ) /* (TCB) TCLK2 connected to XC2 */ +#define AT91C_TCB_TC2XC2S_NONE ( 0x1 << 4 ) /* (TCB) None signal connected to XC2 */ +#define AT91C_TCB_TC2XC2S_TIOA0 ( 0x2 << 4 ) /* (TCB) TIOA0 connected to XC2 */ +#define AT91C_TCB_TC2XC2S_TIOA1 ( 0x3 << 4 ) /* (TCB) TIOA2 connected to XC2 */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_CAN_MB structure *** */ +#define CAN_MB_MMR ( 0 ) /* MailBox Mode Register */ +#define CAN_MB_MAM ( 4 ) /* MailBox Acceptance Mask Register */ +#define CAN_MB_MID ( 8 ) /* MailBox ID Register */ +#define CAN_MB_MFID ( 12 ) /* MailBox Family ID Register */ +#define CAN_MB_MSR ( 16 ) /* MailBox Status Register */ +#define CAN_MB_MDL ( 20 ) /* MailBox Data Low Register */ +#define CAN_MB_MDH ( 24 ) /* MailBox Data High Register */ +#define CAN_MB_MCR ( 28 ) /* MailBox Control Register */ +/* -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- */ +#define AT91C_CAN_MTIMEMARK ( 0xFFFF << 0 ) /* (CAN_MB) Mailbox Timemark */ +#define AT91C_CAN_PRIOR ( 0xF << 16 ) /* (CAN_MB) Mailbox Priority */ +#define AT91C_CAN_MOT ( 0x7 << 24 ) /* (CAN_MB) Mailbox Object Type */ +#define AT91C_CAN_MOT_DIS ( 0x0 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_RX ( 0x1 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_RXOVERWRITE ( 0x2 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_TX ( 0x3 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_CONSUMER ( 0x4 << 24 ) /* (CAN_MB) */ +#define AT91C_CAN_MOT_PRODUCER ( 0x5 << 24 ) /* (CAN_MB) */ +/* -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- */ +#define AT91C_CAN_MIDvB ( 0x3FFFF << 0 ) /* (CAN_MB) Complementary bits for identifier in extended mode */ +#define AT91C_CAN_MIDvA ( 0x7FF << 18 ) /* (CAN_MB) Identifier for standard frame mode */ +#define AT91C_CAN_MIDE ( 0x1 << 29 ) /* (CAN_MB) Identifier Version */ +/* -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- */ +/* -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- */ +/* -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- */ +#define AT91C_CAN_MTIMESTAMP ( 0xFFFF << 0 ) /* (CAN_MB) Timer Value */ +#define AT91C_CAN_MDLC ( 0xF << 16 ) /* (CAN_MB) Mailbox Data Length Code */ +#define AT91C_CAN_MRTR ( 0x1 << 20 ) /* (CAN_MB) Mailbox Remote Transmission Request */ +#define AT91C_CAN_MABT ( 0x1 << 22 ) /* (CAN_MB) Mailbox Message Abort */ +#define AT91C_CAN_MRDY ( 0x1 << 23 ) /* (CAN_MB) Mailbox Ready */ +#define AT91C_CAN_MMI ( 0x1 << 24 ) /* (CAN_MB) Mailbox Message Ignored */ +/* -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- */ +/* -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- */ +/* -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- */ +#define AT91C_CAN_MACR ( 0x1 << 22 ) /* (CAN_MB) Abort Request for Mailbox */ +#define AT91C_CAN_MTCR ( 0x1 << 23 ) /* (CAN_MB) Mailbox Transfer Command */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Control Area Network Interface */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_CAN structure *** */ +#define CAN_MR ( 0 ) /* Mode Register */ +#define CAN_IER ( 4 ) /* Interrupt Enable Register */ +#define CAN_IDR ( 8 ) /* Interrupt Disable Register */ +#define CAN_IMR ( 12 ) /* Interrupt Mask Register */ +#define CAN_SR ( 16 ) /* Status Register */ +#define CAN_BR ( 20 ) /* Baudrate Register */ +#define CAN_TIM ( 24 ) /* Timer Register */ +#define CAN_TIMESTP ( 28 ) /* Time Stamp Register */ +#define CAN_ECR ( 32 ) /* Error Counter Register */ +#define CAN_TCR ( 36 ) /* Transfer Command Register */ +#define CAN_ACR ( 40 ) /* Abort Command Register */ +#define CAN_VR ( 252 ) /* Version Register */ +#define CAN_MB0 ( 512 ) /* CAN Mailbox 0 */ +#define CAN_MB1 ( 544 ) /* CAN Mailbox 1 */ +#define CAN_MB2 ( 576 ) /* CAN Mailbox 2 */ +#define CAN_MB3 ( 608 ) /* CAN Mailbox 3 */ +#define CAN_MB4 ( 640 ) /* CAN Mailbox 4 */ +#define CAN_MB5 ( 672 ) /* CAN Mailbox 5 */ +#define CAN_MB6 ( 704 ) /* CAN Mailbox 6 */ +#define CAN_MB7 ( 736 ) /* CAN Mailbox 7 */ +#define CAN_MB8 ( 768 ) /* CAN Mailbox 8 */ +#define CAN_MB9 ( 800 ) /* CAN Mailbox 9 */ +#define CAN_MB10 ( 832 ) /* CAN Mailbox 10 */ +#define CAN_MB11 ( 864 ) /* CAN Mailbox 11 */ +#define CAN_MB12 ( 896 ) /* CAN Mailbox 12 */ +#define CAN_MB13 ( 928 ) /* CAN Mailbox 13 */ +#define CAN_MB14 ( 960 ) /* CAN Mailbox 14 */ +#define CAN_MB15 ( 992 ) /* CAN Mailbox 15 */ +/* -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- */ +#define AT91C_CAN_CANEN ( 0x1 << 0 ) /* (CAN) CAN Controller Enable */ +#define AT91C_CAN_LPM ( 0x1 << 1 ) /* (CAN) Disable/Enable Low Power Mode */ +#define AT91C_CAN_ABM ( 0x1 << 2 ) /* (CAN) Disable/Enable Autobaud/Listen Mode */ +#define AT91C_CAN_OVL ( 0x1 << 3 ) /* (CAN) Disable/Enable Overload Frame */ +#define AT91C_CAN_TEOF ( 0x1 << 4 ) /* (CAN) Time Stamp messages at each end of Frame */ +#define AT91C_CAN_TTM ( 0x1 << 5 ) /* (CAN) Disable/Enable Time Trigger Mode */ +#define AT91C_CAN_TIMFRZ ( 0x1 << 6 ) /* (CAN) Enable Timer Freeze */ +#define AT91C_CAN_DRPT ( 0x1 << 7 ) /* (CAN) Disable Repeat */ +/* -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- */ +#define AT91C_CAN_MB0 ( 0x1 << 0 ) /* (CAN) Mailbox 0 Flag */ +#define AT91C_CAN_MB1 ( 0x1 << 1 ) /* (CAN) Mailbox 1 Flag */ +#define AT91C_CAN_MB2 ( 0x1 << 2 ) /* (CAN) Mailbox 2 Flag */ +#define AT91C_CAN_MB3 ( 0x1 << 3 ) /* (CAN) Mailbox 3 Flag */ +#define AT91C_CAN_MB4 ( 0x1 << 4 ) /* (CAN) Mailbox 4 Flag */ +#define AT91C_CAN_MB5 ( 0x1 << 5 ) /* (CAN) Mailbox 5 Flag */ +#define AT91C_CAN_MB6 ( 0x1 << 6 ) /* (CAN) Mailbox 6 Flag */ +#define AT91C_CAN_MB7 ( 0x1 << 7 ) /* (CAN) Mailbox 7 Flag */ +#define AT91C_CAN_MB8 ( 0x1 << 8 ) /* (CAN) Mailbox 8 Flag */ +#define AT91C_CAN_MB9 ( 0x1 << 9 ) /* (CAN) Mailbox 9 Flag */ +#define AT91C_CAN_MB10 ( 0x1 << 10 ) /* (CAN) Mailbox 10 Flag */ +#define AT91C_CAN_MB11 ( 0x1 << 11 ) /* (CAN) Mailbox 11 Flag */ +#define AT91C_CAN_MB12 ( 0x1 << 12 ) /* (CAN) Mailbox 12 Flag */ +#define AT91C_CAN_MB13 ( 0x1 << 13 ) /* (CAN) Mailbox 13 Flag */ +#define AT91C_CAN_MB14 ( 0x1 << 14 ) /* (CAN) Mailbox 14 Flag */ +#define AT91C_CAN_MB15 ( 0x1 << 15 ) /* (CAN) Mailbox 15 Flag */ +#define AT91C_CAN_ERRA ( 0x1 << 16 ) /* (CAN) Error Active Mode Flag */ +#define AT91C_CAN_WARN ( 0x1 << 17 ) /* (CAN) Warning Limit Flag */ +#define AT91C_CAN_ERRP ( 0x1 << 18 ) /* (CAN) Error Passive Mode Flag */ +#define AT91C_CAN_BOFF ( 0x1 << 19 ) /* (CAN) Bus Off Mode Flag */ +#define AT91C_CAN_SLEEP ( 0x1 << 20 ) /* (CAN) Sleep Flag */ +#define AT91C_CAN_WAKEUP ( 0x1 << 21 ) /* (CAN) Wakeup Flag */ +#define AT91C_CAN_TOVF ( 0x1 << 22 ) /* (CAN) Timer Overflow Flag */ +#define AT91C_CAN_TSTP ( 0x1 << 23 ) /* (CAN) Timestamp Flag */ +#define AT91C_CAN_CERR ( 0x1 << 24 ) /* (CAN) CRC Error */ +#define AT91C_CAN_SERR ( 0x1 << 25 ) /* (CAN) Stuffing Error */ +#define AT91C_CAN_AERR ( 0x1 << 26 ) /* (CAN) Acknowledgment Error */ +#define AT91C_CAN_FERR ( 0x1 << 27 ) /* (CAN) Form Error */ +#define AT91C_CAN_BERR ( 0x1 << 28 ) /* (CAN) Bit Error */ +/* -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- */ +/* -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- */ +/* -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- */ +#define AT91C_CAN_RBSY ( 0x1 << 29 ) /* (CAN) Receiver Busy */ +#define AT91C_CAN_TBSY ( 0x1 << 30 ) /* (CAN) Transmitter Busy */ +#define AT91C_CAN_OVLY ( 0x1 << 31 ) /* (CAN) Overload Busy */ +/* -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- */ +#define AT91C_CAN_PHASE2 ( 0x7 << 0 ) /* (CAN) Phase 2 segment */ +#define AT91C_CAN_PHASE1 ( 0x7 << 4 ) /* (CAN) Phase 1 segment */ +#define AT91C_CAN_PROPAG ( 0x7 << 8 ) /* (CAN) Programmation time segment */ +#define AT91C_CAN_SYNC ( 0x3 << 12 ) /* (CAN) Re-synchronization jump width segment */ +#define AT91C_CAN_BRP ( 0x7F << 16 ) /* (CAN) Baudrate Prescaler */ +#define AT91C_CAN_SMP ( 0x1 << 24 ) /* (CAN) Sampling mode */ +/* -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- */ +#define AT91C_CAN_TIMER ( 0xFFFF << 0 ) /* (CAN) Timer field */ +/* -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- */ +/* -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- */ +#define AT91C_CAN_REC ( 0xFF << 0 ) /* (CAN) Receive Error Counter */ +#define AT91C_CAN_TEC ( 0xFF << 16 ) /* (CAN) Transmit Error Counter */ +/* -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- */ +#define AT91C_CAN_TIMRST ( 0x1 << 31 ) /* (CAN) Timer Reset Field */ +/* -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_EMAC structure *** */ +#define EMAC_NCR ( 0 ) /* Network Control Register */ +#define EMAC_NCFGR ( 4 ) /* Network Configuration Register */ +#define EMAC_NSR ( 8 ) /* Network Status Register */ +#define EMAC_TSR ( 20 ) /* Transmit Status Register */ +#define EMAC_RBQP ( 24 ) /* Receive Buffer Queue Pointer */ +#define EMAC_TBQP ( 28 ) /* Transmit Buffer Queue Pointer */ +#define EMAC_RSR ( 32 ) /* Receive Status Register */ +#define EMAC_ISR ( 36 ) /* Interrupt Status Register */ +#define EMAC_IER ( 40 ) /* Interrupt Enable Register */ +#define EMAC_IDR ( 44 ) /* Interrupt Disable Register */ +#define EMAC_IMR ( 48 ) /* Interrupt Mask Register */ +#define EMAC_MAN ( 52 ) /* PHY Maintenance Register */ +#define EMAC_PTR ( 56 ) /* Pause Time Register */ +#define EMAC_PFR ( 60 ) /* Pause Frames received Register */ +#define EMAC_FTO ( 64 ) /* Frames Transmitted OK Register */ +#define EMAC_SCF ( 68 ) /* Single Collision Frame Register */ +#define EMAC_MCF ( 72 ) /* Multiple Collision Frame Register */ +#define EMAC_FRO ( 76 ) /* Frames Received OK Register */ +#define EMAC_FCSE ( 80 ) /* Frame Check Sequence Error Register */ +#define EMAC_ALE ( 84 ) /* Alignment Error Register */ +#define EMAC_DTF ( 88 ) /* Deferred Transmission Frame Register */ +#define EMAC_LCOL ( 92 ) /* Late Collision Register */ +#define EMAC_ECOL ( 96 ) /* Excessive Collision Register */ +#define EMAC_TUND ( 100 ) /* Transmit Underrun Error Register */ +#define EMAC_CSE ( 104 ) /* Carrier Sense Error Register */ +#define EMAC_RRE ( 108 ) /* Receive Resource Error Register */ +#define EMAC_ROV ( 112 ) /* Receive Overrun Errors Register */ +#define EMAC_RSE ( 116 ) /* Receive Symbol Errors Register */ +#define EMAC_ELE ( 120 ) /* Excessive Length Errors Register */ +#define EMAC_RJA ( 124 ) /* Receive Jabbers Register */ +#define EMAC_USF ( 128 ) /* Undersize Frames Register */ +#define EMAC_STE ( 132 ) /* SQE Test Error Register */ +#define EMAC_RLE ( 136 ) /* Receive Length Field Mismatch Register */ +#define EMAC_TPF ( 140 ) /* Transmitted Pause Frames Register */ +#define EMAC_HRB ( 144 ) /* Hash Address Bottom[31:0] */ +#define EMAC_HRT ( 148 ) /* Hash Address Top[63:32] */ +#define EMAC_SA1L ( 152 ) /* Specific Address 1 Bottom, First 4 bytes */ +#define EMAC_SA1H ( 156 ) /* Specific Address 1 Top, Last 2 bytes */ +#define EMAC_SA2L ( 160 ) /* Specific Address 2 Bottom, First 4 bytes */ +#define EMAC_SA2H ( 164 ) /* Specific Address 2 Top, Last 2 bytes */ +#define EMAC_SA3L ( 168 ) /* Specific Address 3 Bottom, First 4 bytes */ +#define EMAC_SA3H ( 172 ) /* Specific Address 3 Top, Last 2 bytes */ +#define EMAC_SA4L ( 176 ) /* Specific Address 4 Bottom, First 4 bytes */ +#define EMAC_SA4H ( 180 ) /* Specific Address 4 Top, Last 2 bytes */ +#define EMAC_TID ( 184 ) /* Type ID Checking Register */ +#define EMAC_TPQ ( 188 ) /* Transmit Pause Quantum Register */ +#define EMAC_USRIO ( 192 ) /* USER Input/Output Register */ +#define EMAC_WOL ( 196 ) /* Wake On LAN Register */ +#define EMAC_REV ( 252 ) /* Revision Register */ +/* -------- EMAC_NCR : (EMAC Offset: 0x0) -------- */ +#define AT91C_EMAC_LB ( 0x1 << 0 ) /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */ +#define AT91C_EMAC_LLB ( 0x1 << 1 ) /* (EMAC) Loopback local. */ +#define AT91C_EMAC_RE ( 0x1 << 2 ) /* (EMAC) Receive enable. */ +#define AT91C_EMAC_TE ( 0x1 << 3 ) /* (EMAC) Transmit enable. */ +#define AT91C_EMAC_MPE ( 0x1 << 4 ) /* (EMAC) Management port enable. */ +#define AT91C_EMAC_CLRSTAT ( 0x1 << 5 ) /* (EMAC) Clear statistics registers. */ +#define AT91C_EMAC_INCSTAT ( 0x1 << 6 ) /* (EMAC) Increment statistics registers. */ +#define AT91C_EMAC_WESTAT ( 0x1 << 7 ) /* (EMAC) Write enable for statistics registers. */ +#define AT91C_EMAC_BP ( 0x1 << 8 ) /* (EMAC) Back pressure. */ +#define AT91C_EMAC_TSTART ( 0x1 << 9 ) /* (EMAC) Start Transmission. */ +#define AT91C_EMAC_THALT ( 0x1 << 10 ) /* (EMAC) Transmission Halt. */ +#define AT91C_EMAC_TPFR ( 0x1 << 11 ) /* (EMAC) Transmit pause frame */ +#define AT91C_EMAC_TZQ ( 0x1 << 12 ) /* (EMAC) Transmit zero quantum pause frame */ +/* -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- */ +#define AT91C_EMAC_SPD ( 0x1 << 0 ) /* (EMAC) Speed. */ +#define AT91C_EMAC_FD ( 0x1 << 1 ) /* (EMAC) Full duplex. */ +#define AT91C_EMAC_JFRAME ( 0x1 << 3 ) /* (EMAC) Jumbo Frames. */ +#define AT91C_EMAC_CAF ( 0x1 << 4 ) /* (EMAC) Copy all frames. */ +#define AT91C_EMAC_NBC ( 0x1 << 5 ) /* (EMAC) No broadcast. */ +#define AT91C_EMAC_MTI ( 0x1 << 6 ) /* (EMAC) Multicast hash event enable */ +#define AT91C_EMAC_UNI ( 0x1 << 7 ) /* (EMAC) Unicast hash enable. */ +#define AT91C_EMAC_BIG ( 0x1 << 8 ) /* (EMAC) Receive 1522 bytes. */ +#define AT91C_EMAC_EAE ( 0x1 << 9 ) /* (EMAC) External address match enable. */ +#define AT91C_EMAC_CLK ( 0x3 << 10 ) /* (EMAC) */ +#define AT91C_EMAC_CLK_HCLK_8 ( 0x0 << 10 ) /* (EMAC) HCLK divided by 8 */ +#define AT91C_EMAC_CLK_HCLK_16 ( 0x1 << 10 ) /* (EMAC) HCLK divided by 16 */ +#define AT91C_EMAC_CLK_HCLK_32 ( 0x2 << 10 ) /* (EMAC) HCLK divided by 32 */ +#define AT91C_EMAC_CLK_HCLK_64 ( 0x3 << 10 ) /* (EMAC) HCLK divided by 64 */ +#define AT91C_EMAC_RTY ( 0x1 << 12 ) /* (EMAC) */ +#define AT91C_EMAC_PAE ( 0x1 << 13 ) /* (EMAC) */ +#define AT91C_EMAC_RBOF ( 0x3 << 14 ) /* (EMAC) */ +#define AT91C_EMAC_RBOF_OFFSET_0 ( 0x0 << 14 ) /* (EMAC) no offset from start of receive buffer */ +#define AT91C_EMAC_RBOF_OFFSET_1 ( 0x1 << 14 ) /* (EMAC) one byte offset from start of receive buffer */ +#define AT91C_EMAC_RBOF_OFFSET_2 ( 0x2 << 14 ) /* (EMAC) two bytes offset from start of receive buffer */ +#define AT91C_EMAC_RBOF_OFFSET_3 ( 0x3 << 14 ) /* (EMAC) three bytes offset from start of receive buffer */ +#define AT91C_EMAC_RLCE ( 0x1 << 16 ) /* (EMAC) Receive Length field Checking Enable */ +#define AT91C_EMAC_DRFCS ( 0x1 << 17 ) /* (EMAC) Discard Receive FCS */ +#define AT91C_EMAC_EFRHD ( 0x1 << 18 ) /* (EMAC) */ +#define AT91C_EMAC_IRXFCS ( 0x1 << 19 ) /* (EMAC) Ignore RX FCS */ +/* -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- */ +#define AT91C_EMAC_LINKR ( 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_MDIO ( 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_IDLE ( 0x1 << 2 ) /* (EMAC) */ +/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- */ +#define AT91C_EMAC_UBR ( 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_COL ( 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_RLES ( 0x1 << 2 ) /* (EMAC) */ +#define AT91C_EMAC_TGO ( 0x1 << 3 ) /* (EMAC) Transmit Go */ +#define AT91C_EMAC_BEX ( 0x1 << 4 ) /* (EMAC) Buffers exhausted mid frame */ +#define AT91C_EMAC_COMP ( 0x1 << 5 ) /* (EMAC) */ +#define AT91C_EMAC_UND ( 0x1 << 6 ) /* (EMAC) */ +/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */ +#define AT91C_EMAC_BNA ( 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_REC ( 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_OVR ( 0x1 << 2 ) /* (EMAC) */ +/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */ +#define AT91C_EMAC_MFD ( 0x1 << 0 ) /* (EMAC) */ +#define AT91C_EMAC_RCOMP ( 0x1 << 1 ) /* (EMAC) */ +#define AT91C_EMAC_RXUBR ( 0x1 << 2 ) /* (EMAC) */ +#define AT91C_EMAC_TXUBR ( 0x1 << 3 ) /* (EMAC) */ +#define AT91C_EMAC_TUNDR ( 0x1 << 4 ) /* (EMAC) */ +#define AT91C_EMAC_RLEX ( 0x1 << 5 ) /* (EMAC) */ +#define AT91C_EMAC_TXERR ( 0x1 << 6 ) /* (EMAC) */ +#define AT91C_EMAC_TCOMP ( 0x1 << 7 ) /* (EMAC) */ +#define AT91C_EMAC_LINK ( 0x1 << 9 ) /* (EMAC) */ +#define AT91C_EMAC_ROVR ( 0x1 << 10 ) /* (EMAC) */ +#define AT91C_EMAC_HRESP ( 0x1 << 11 ) /* (EMAC) */ +#define AT91C_EMAC_PFRE ( 0x1 << 12 ) /* (EMAC) */ +#define AT91C_EMAC_PTZ ( 0x1 << 13 ) /* (EMAC) */ +/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */ +/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */ +/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */ +/* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */ +#define AT91C_EMAC_DATA ( 0xFFFF << 0 ) /* (EMAC) */ +#define AT91C_EMAC_CODE ( 0x3 << 16 ) /* (EMAC) */ +#define AT91C_EMAC_REGA ( 0x1F << 18 ) /* (EMAC) */ +#define AT91C_EMAC_PHYA ( 0x1F << 23 ) /* (EMAC) */ +#define AT91C_EMAC_RW ( 0x3 << 28 ) /* (EMAC) */ +#define AT91C_EMAC_SOF ( 0x3 << 30 ) /* (EMAC) */ +/* -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- */ +#define AT91C_EMAC_RMII ( 0x1 << 0 ) /* (EMAC) Reduce MII */ +/* -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- */ +#define AT91C_EMAC_IP ( 0xFFFF << 0 ) /* (EMAC) ARP request IP address */ +#define AT91C_EMAC_MAG ( 0x1 << 16 ) /* (EMAC) Magic packet event enable */ +#define AT91C_EMAC_ARP ( 0x1 << 17 ) /* (EMAC) ARP request event enable */ +#define AT91C_EMAC_SA1 ( 0x1 << 18 ) /* (EMAC) Specific address register 1 event enable */ +/* -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- */ +#define AT91C_EMAC_REVREF ( 0xFFFF << 0 ) /* (EMAC) */ +#define AT91C_EMAC_PARTREF ( 0xFFFF << 16 ) /* (EMAC) */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Analog to Digital Convertor */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_ADC structure *** */ +#define ADC_CR ( 0 ) /* ADC Control Register */ +#define ADC_MR ( 4 ) /* ADC Mode Register */ +#define ADC_CHER ( 16 ) /* ADC Channel Enable Register */ +#define ADC_CHDR ( 20 ) /* ADC Channel Disable Register */ +#define ADC_CHSR ( 24 ) /* ADC Channel Status Register */ +#define ADC_SR ( 28 ) /* ADC Status Register */ +#define ADC_LCDR ( 32 ) /* ADC Last Converted Data Register */ +#define ADC_IER ( 36 ) /* ADC Interrupt Enable Register */ +#define ADC_IDR ( 40 ) /* ADC Interrupt Disable Register */ +#define ADC_IMR ( 44 ) /* ADC Interrupt Mask Register */ +#define ADC_CDR0 ( 48 ) /* ADC Channel Data Register 0 */ +#define ADC_CDR1 ( 52 ) /* ADC Channel Data Register 1 */ +#define ADC_CDR2 ( 56 ) /* ADC Channel Data Register 2 */ +#define ADC_CDR3 ( 60 ) /* ADC Channel Data Register 3 */ +#define ADC_CDR4 ( 64 ) /* ADC Channel Data Register 4 */ +#define ADC_CDR5 ( 68 ) /* ADC Channel Data Register 5 */ +#define ADC_CDR6 ( 72 ) /* ADC Channel Data Register 6 */ +#define ADC_CDR7 ( 76 ) /* ADC Channel Data Register 7 */ +#define ADC_RPR ( 256 ) /* Receive Pointer Register */ +#define ADC_RCR ( 260 ) /* Receive Counter Register */ +#define ADC_TPR ( 264 ) /* Transmit Pointer Register */ +#define ADC_TCR ( 268 ) /* Transmit Counter Register */ +#define ADC_RNPR ( 272 ) /* Receive Next Pointer Register */ +#define ADC_RNCR ( 276 ) /* Receive Next Counter Register */ +#define ADC_TNPR ( 280 ) /* Transmit Next Pointer Register */ +#define ADC_TNCR ( 284 ) /* Transmit Next Counter Register */ +#define ADC_PTCR ( 288 ) /* PDC Transfer Control Register */ +#define ADC_PTSR ( 292 ) /* PDC Transfer Status Register */ +/* -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- */ +#define AT91C_ADC_SWRST ( 0x1 << 0 ) /* (ADC) Software Reset */ +#define AT91C_ADC_START ( 0x1 << 1 ) /* (ADC) Start Conversion */ +/* -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- */ +#define AT91C_ADC_TRGEN ( 0x1 << 0 ) /* (ADC) Trigger Enable */ +#define AT91C_ADC_TRGEN_DIS ( 0x0 ) /* (ADC) Hardware triggers are disabled. Starting a conversion is only possible by software */ +#define AT91C_ADC_TRGEN_EN ( 0x1 ) /* (ADC) Hardware trigger selected by TRGSEL field is enabled. */ +#define AT91C_ADC_TRGSEL ( 0x7 << 1 ) /* (ADC) Trigger Selection */ +#define AT91C_ADC_TRGSEL_TIOA0 ( 0x0 << 1 ) /* (ADC) Selected TRGSEL = TIAO0 */ +#define AT91C_ADC_TRGSEL_TIOA1 ( 0x1 << 1 ) /* (ADC) Selected TRGSEL = TIAO1 */ +#define AT91C_ADC_TRGSEL_TIOA2 ( 0x2 << 1 ) /* (ADC) Selected TRGSEL = TIAO2 */ +#define AT91C_ADC_TRGSEL_TIOA3 ( 0x3 << 1 ) /* (ADC) Selected TRGSEL = TIAO3 */ +#define AT91C_ADC_TRGSEL_TIOA4 ( 0x4 << 1 ) /* (ADC) Selected TRGSEL = TIAO4 */ +#define AT91C_ADC_TRGSEL_TIOA5 ( 0x5 << 1 ) /* (ADC) Selected TRGSEL = TIAO5 */ +#define AT91C_ADC_TRGSEL_EXT ( 0x6 << 1 ) /* (ADC) Selected TRGSEL = External Trigger */ +#define AT91C_ADC_LOWRES ( 0x1 << 4 ) /* (ADC) Resolution. */ +#define AT91C_ADC_LOWRES_10_BIT ( 0x0 << 4 ) /* (ADC) 10-bit resolution */ +#define AT91C_ADC_LOWRES_8_BIT ( 0x1 << 4 ) /* (ADC) 8-bit resolution */ +#define AT91C_ADC_SLEEP ( 0x1 << 5 ) /* (ADC) Sleep Mode */ +#define AT91C_ADC_SLEEP_NORMAL_MODE ( 0x0 << 5 ) /* (ADC) Normal Mode */ +#define AT91C_ADC_SLEEP_MODE ( 0x1 << 5 ) /* (ADC) Sleep Mode */ +#define AT91C_ADC_PRESCAL ( 0x3F << 8 ) /* (ADC) Prescaler rate selection */ +#define AT91C_ADC_STARTUP ( 0x1F << 16 ) /* (ADC) Startup Time */ +#define AT91C_ADC_SHTIM ( 0xF << 24 ) /* (ADC) Sample & Hold Time */ +/* -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- */ +#define AT91C_ADC_CH0 ( 0x1 << 0 ) /* (ADC) Channel 0 */ +#define AT91C_ADC_CH1 ( 0x1 << 1 ) /* (ADC) Channel 1 */ +#define AT91C_ADC_CH2 ( 0x1 << 2 ) /* (ADC) Channel 2 */ +#define AT91C_ADC_CH3 ( 0x1 << 3 ) /* (ADC) Channel 3 */ +#define AT91C_ADC_CH4 ( 0x1 << 4 ) /* (ADC) Channel 4 */ +#define AT91C_ADC_CH5 ( 0x1 << 5 ) /* (ADC) Channel 5 */ +#define AT91C_ADC_CH6 ( 0x1 << 6 ) /* (ADC) Channel 6 */ +#define AT91C_ADC_CH7 ( 0x1 << 7 ) /* (ADC) Channel 7 */ +/* -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- */ +/* -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- */ +/* -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- */ +#define AT91C_ADC_EOC0 ( 0x1 << 0 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC1 ( 0x1 << 1 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC2 ( 0x1 << 2 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC3 ( 0x1 << 3 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC4 ( 0x1 << 4 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC5 ( 0x1 << 5 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC6 ( 0x1 << 6 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_EOC7 ( 0x1 << 7 ) /* (ADC) End of Conversion */ +#define AT91C_ADC_OVRE0 ( 0x1 << 8 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE1 ( 0x1 << 9 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE2 ( 0x1 << 10 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE3 ( 0x1 << 11 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE4 ( 0x1 << 12 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE5 ( 0x1 << 13 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE6 ( 0x1 << 14 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_OVRE7 ( 0x1 << 15 ) /* (ADC) Overrun Error */ +#define AT91C_ADC_DRDY ( 0x1 << 16 ) /* (ADC) Data Ready */ +#define AT91C_ADC_GOVRE ( 0x1 << 17 ) /* (ADC) General Overrun */ +#define AT91C_ADC_ENDRX ( 0x1 << 18 ) /* (ADC) End of Receiver Transfer */ +#define AT91C_ADC_RXBUFF ( 0x1 << 19 ) /* (ADC) RXBUFF Interrupt */ +/* -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- */ +#define AT91C_ADC_LDATA ( 0x3FF << 0 ) /* (ADC) Last Data Converted */ +/* -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- */ +/* -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- */ +/* -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- */ +/* -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- */ +#define AT91C_ADC_DATA ( 0x3FF << 0 ) /* (ADC) Converted Data */ +/* -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- */ +/* -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- */ +/* -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- */ +/* -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- */ +/* -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- */ +/* -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- */ +/* -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Advanced Encryption Standard */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_AES structure *** */ +#define AES_CR ( 0 ) /* Control Register */ +#define AES_MR ( 4 ) /* Mode Register */ +#define AES_IER ( 16 ) /* Interrupt Enable Register */ +#define AES_IDR ( 20 ) /* Interrupt Disable Register */ +#define AES_IMR ( 24 ) /* Interrupt Mask Register */ +#define AES_ISR ( 28 ) /* Interrupt Status Register */ +#define AES_KEYWxR ( 32 ) /* Key Word x Register */ +#define AES_IDATAxR ( 64 ) /* Input Data x Register */ +#define AES_ODATAxR ( 80 ) /* Output Data x Register */ +#define AES_IVxR ( 96 ) /* Initialization Vector x Register */ +#define AES_VR ( 252 ) /* AES Version Register */ +#define AES_RPR ( 256 ) /* Receive Pointer Register */ +#define AES_RCR ( 260 ) /* Receive Counter Register */ +#define AES_TPR ( 264 ) /* Transmit Pointer Register */ +#define AES_TCR ( 268 ) /* Transmit Counter Register */ +#define AES_RNPR ( 272 ) /* Receive Next Pointer Register */ +#define AES_RNCR ( 276 ) /* Receive Next Counter Register */ +#define AES_TNPR ( 280 ) /* Transmit Next Pointer Register */ +#define AES_TNCR ( 284 ) /* Transmit Next Counter Register */ +#define AES_PTCR ( 288 ) /* PDC Transfer Control Register */ +#define AES_PTSR ( 292 ) /* PDC Transfer Status Register */ +/* -------- AES_CR : (AES Offset: 0x0) Control Register -------- */ +#define AT91C_AES_START ( 0x1 << 0 ) /* (AES) Starts Processing */ +#define AT91C_AES_SWRST ( 0x1 << 8 ) /* (AES) Software Reset */ +#define AT91C_AES_LOADSEED ( 0x1 << 16 ) /* (AES) Random Number Generator Seed Loading */ +/* -------- AES_MR : (AES Offset: 0x4) Mode Register -------- */ +#define AT91C_AES_CIPHER ( 0x1 << 0 ) /* (AES) Processing Mode */ +#define AT91C_AES_PROCDLY ( 0xF << 4 ) /* (AES) Processing Delay */ +#define AT91C_AES_SMOD ( 0x3 << 8 ) /* (AES) Start Mode */ +#define AT91C_AES_SMOD_MANUAL ( 0x0 << 8 ) /* (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. */ +#define AT91C_AES_SMOD_AUTO ( 0x1 << 8 ) /* (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). */ +#define AT91C_AES_SMOD_PDC ( 0x2 << 8 ) /* (AES) PDC Mode (cf datasheet). */ +#define AT91C_AES_OPMOD ( 0x7 << 12 ) /* (AES) Operation Mode */ +#define AT91C_AES_OPMOD_ECB ( 0x0 << 12 ) /* (AES) ECB Electronic CodeBook mode. */ +#define AT91C_AES_OPMOD_CBC ( 0x1 << 12 ) /* (AES) CBC Cipher Block Chaining mode. */ +#define AT91C_AES_OPMOD_OFB ( 0x2 << 12 ) /* (AES) OFB Output Feedback mode. */ +#define AT91C_AES_OPMOD_CFB ( 0x3 << 12 ) /* (AES) CFB Cipher Feedback mode. */ +#define AT91C_AES_OPMOD_CTR ( 0x4 << 12 ) /* (AES) CTR Counter mode. */ +#define AT91C_AES_LOD ( 0x1 << 15 ) /* (AES) Last Output Data Mode */ +#define AT91C_AES_CFBS ( 0x7 << 16 ) /* (AES) Cipher Feedback Data Size */ +#define AT91C_AES_CFBS_128_BIT ( 0x0 << 16 ) /* (AES) 128-bit. */ +#define AT91C_AES_CFBS_64_BIT ( 0x1 << 16 ) /* (AES) 64-bit. */ +#define AT91C_AES_CFBS_32_BIT ( 0x2 << 16 ) /* (AES) 32-bit. */ +#define AT91C_AES_CFBS_16_BIT ( 0x3 << 16 ) /* (AES) 16-bit. */ +#define AT91C_AES_CFBS_8_BIT ( 0x4 << 16 ) /* (AES) 8-bit. */ +#define AT91C_AES_CKEY ( 0xF << 20 ) /* (AES) Countermeasure Key */ +#define AT91C_AES_CTYPE ( 0x1F << 24 ) /* (AES) Countermeasure Type */ +#define AT91C_AES_CTYPE_TYPE1_EN ( 0x1 << 24 ) /* (AES) Countermeasure type 1 is enabled. */ +#define AT91C_AES_CTYPE_TYPE2_EN ( 0x2 << 24 ) /* (AES) Countermeasure type 2 is enabled. */ +#define AT91C_AES_CTYPE_TYPE3_EN ( 0x4 << 24 ) /* (AES) Countermeasure type 3 is enabled. */ +#define AT91C_AES_CTYPE_TYPE4_EN ( 0x8 << 24 ) /* (AES) Countermeasure type 4 is enabled. */ +#define AT91C_AES_CTYPE_TYPE5_EN ( 0x10 << 24 ) /* (AES) Countermeasure type 5 is enabled. */ +/* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */ +#define AT91C_AES_DATRDY ( 0x1 << 0 ) /* (AES) DATRDY */ +#define AT91C_AES_ENDRX ( 0x1 << 1 ) /* (AES) PDC Read Buffer End */ +#define AT91C_AES_ENDTX ( 0x1 << 2 ) /* (AES) PDC Write Buffer End */ +#define AT91C_AES_RXBUFF ( 0x1 << 3 ) /* (AES) PDC Read Buffer Full */ +#define AT91C_AES_TXBUFE ( 0x1 << 4 ) /* (AES) PDC Write Buffer Empty */ +#define AT91C_AES_URAD ( 0x1 << 8 ) /* (AES) Unspecified Register Access Detection */ +/* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */ +/* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */ +/* -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- */ +#define AT91C_AES_URAT ( 0x7 << 12 ) /* (AES) Unspecified Register Access Type Status */ +#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ( 0x0 << 12 ) /* (AES) Input data register written during the data processing in PDC mode. */ +#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ( 0x1 << 12 ) /* (AES) Output data register read during the data processing. */ +#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ( 0x2 << 12 ) /* (AES) Mode register written during the data processing. */ +#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ( 0x3 << 12 ) /* (AES) Output data register read during the sub-keys generation. */ +#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ( 0x4 << 12 ) /* (AES) Mode register written during the sub-keys generation. */ +#define AT91C_AES_URAT_WO_REG_READ ( 0x5 << 12 ) /* (AES) Write-only register read access. */ + +/* ***************************************************************************** */ +/* SOFTWARE API DEFINITION FOR Triple Data Encryption Standard */ +/* ***************************************************************************** */ +/* *** Register offset in AT91S_TDES structure *** */ +#define TDES_CR ( 0 ) /* Control Register */ +#define TDES_MR ( 4 ) /* Mode Register */ +#define TDES_IER ( 16 ) /* Interrupt Enable Register */ +#define TDES_IDR ( 20 ) /* Interrupt Disable Register */ +#define TDES_IMR ( 24 ) /* Interrupt Mask Register */ +#define TDES_ISR ( 28 ) /* Interrupt Status Register */ +#define TDES_KEY1WxR ( 32 ) /* Key 1 Word x Register */ +#define TDES_KEY2WxR ( 40 ) /* Key 2 Word x Register */ +#define TDES_KEY3WxR ( 48 ) /* Key 3 Word x Register */ +#define TDES_IDATAxR ( 64 ) /* Input Data x Register */ +#define TDES_ODATAxR ( 80 ) /* Output Data x Register */ +#define TDES_IVxR ( 96 ) /* Initialization Vector x Register */ +#define TDES_VR ( 252 ) /* TDES Version Register */ +#define TDES_RPR ( 256 ) /* Receive Pointer Register */ +#define TDES_RCR ( 260 ) /* Receive Counter Register */ +#define TDES_TPR ( 264 ) /* Transmit Pointer Register */ +#define TDES_TCR ( 268 ) /* Transmit Counter Register */ +#define TDES_RNPR ( 272 ) /* Receive Next Pointer Register */ +#define TDES_RNCR ( 276 ) /* Receive Next Counter Register */ +#define TDES_TNPR ( 280 ) /* Transmit Next Pointer Register */ +#define TDES_TNCR ( 284 ) /* Transmit Next Counter Register */ +#define TDES_PTCR ( 288 ) /* PDC Transfer Control Register */ +#define TDES_PTSR ( 292 ) /* PDC Transfer Status Register */ +/* -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- */ +#define AT91C_TDES_START ( 0x1 << 0 ) /* (TDES) Starts Processing */ +#define AT91C_TDES_SWRST ( 0x1 << 8 ) /* (TDES) Software Reset */ +/* -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- */ +#define AT91C_TDES_CIPHER ( 0x1 << 0 ) /* (TDES) Processing Mode */ +#define AT91C_TDES_TDESMOD ( 0x1 << 1 ) /* (TDES) Single or Triple DES Mode */ +#define AT91C_TDES_KEYMOD ( 0x1 << 4 ) /* (TDES) Key Mode */ +#define AT91C_TDES_SMOD ( 0x3 << 8 ) /* (TDES) Start Mode */ +#define AT91C_TDES_SMOD_MANUAL ( 0x0 << 8 ) /* (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. */ +#define AT91C_TDES_SMOD_AUTO ( 0x1 << 8 ) /* (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). */ +#define AT91C_TDES_SMOD_PDC ( 0x2 << 8 ) /* (TDES) PDC Mode (cf datasheet). */ +#define AT91C_TDES_OPMOD ( 0x3 << 12 ) /* (TDES) Operation Mode */ +#define AT91C_TDES_OPMOD_ECB ( 0x0 << 12 ) /* (TDES) ECB Electronic CodeBook mode. */ +#define AT91C_TDES_OPMOD_CBC ( 0x1 << 12 ) /* (TDES) CBC Cipher Block Chaining mode. */ +#define AT91C_TDES_OPMOD_OFB ( 0x2 << 12 ) /* (TDES) OFB Output Feedback mode. */ +#define AT91C_TDES_OPMOD_CFB ( 0x3 << 12 ) /* (TDES) CFB Cipher Feedback mode. */ +#define AT91C_TDES_LOD ( 0x1 << 15 ) /* (TDES) Last Output Data Mode */ +#define AT91C_TDES_CFBS ( 0x3 << 16 ) /* (TDES) Cipher Feedback Data Size */ +#define AT91C_TDES_CFBS_64_BIT ( 0x0 << 16 ) /* (TDES) 64-bit. */ +#define AT91C_TDES_CFBS_32_BIT ( 0x1 << 16 ) /* (TDES) 32-bit. */ +#define AT91C_TDES_CFBS_16_BIT ( 0x2 << 16 ) /* (TDES) 16-bit. */ +#define AT91C_TDES_CFBS_8_BIT ( 0x3 << 16 ) /* (TDES) 8-bit. */ +/* -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- */ +#define AT91C_TDES_DATRDY ( 0x1 << 0 ) /* (TDES) DATRDY */ +#define AT91C_TDES_ENDRX ( 0x1 << 1 ) /* (TDES) PDC Read Buffer End */ +#define AT91C_TDES_ENDTX ( 0x1 << 2 ) /* (TDES) PDC Write Buffer End */ +#define AT91C_TDES_RXBUFF ( 0x1 << 3 ) /* (TDES) PDC Read Buffer Full */ +#define AT91C_TDES_TXBUFE ( 0x1 << 4 ) /* (TDES) PDC Write Buffer Empty */ +#define AT91C_TDES_URAD ( 0x1 << 8 ) /* (TDES) Unspecified Register Access Detection */ +/* -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- */ +/* -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- */ +/* -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- */ +#define AT91C_TDES_URAT ( 0x3 << 12 ) /* (TDES) Unspecified Register Access Type Status */ +#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ( 0x0 << 12 ) /* (TDES) Input data register written during the data processing in PDC mode. */ +#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ( 0x1 << 12 ) /* (TDES) Output data register read during the data processing. */ +#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ( 0x2 << 12 ) /* (TDES) Mode register written during the data processing. */ +#define AT91C_TDES_URAT_WO_REG_READ ( 0x3 << 12 ) /* (TDES) Write-only register read access. */ + +/* ***************************************************************************** */ +/* REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 */ +/* ***************************************************************************** */ +/* ========== Register definition for SYS peripheral ========== */ +/* ========== Register definition for AIC peripheral ========== */ +#define AT91C_AIC_IVR ( 0xFFFFF100 ) /* (AIC) IRQ Vector Register */ +#define AT91C_AIC_SMR ( 0xFFFFF000 ) /* (AIC) Source Mode Register */ +#define AT91C_AIC_FVR ( 0xFFFFF104 ) /* (AIC) FIQ Vector Register */ +#define AT91C_AIC_DCR ( 0xFFFFF138 ) /* (AIC) Debug Control Register (Protect) */ +#define AT91C_AIC_EOICR ( 0xFFFFF130 ) /* (AIC) End of Interrupt Command Register */ +#define AT91C_AIC_SVR ( 0xFFFFF080 ) /* (AIC) Source Vector Register */ +#define AT91C_AIC_FFSR ( 0xFFFFF148 ) /* (AIC) Fast Forcing Status Register */ +#define AT91C_AIC_ICCR ( 0xFFFFF128 ) /* (AIC) Interrupt Clear Command Register */ +#define AT91C_AIC_ISR ( 0xFFFFF108 ) /* (AIC) Interrupt Status Register */ +#define AT91C_AIC_IMR ( 0xFFFFF110 ) /* (AIC) Interrupt Mask Register */ +#define AT91C_AIC_IPR ( 0xFFFFF10C ) /* (AIC) Interrupt Pending Register */ +#define AT91C_AIC_FFER ( 0xFFFFF140 ) /* (AIC) Fast Forcing Enable Register */ +#define AT91C_AIC_IECR ( 0xFFFFF120 ) /* (AIC) Interrupt Enable Command Register */ +#define AT91C_AIC_ISCR ( 0xFFFFF12C ) /* (AIC) Interrupt Set Command Register */ +#define AT91C_AIC_FFDR ( 0xFFFFF144 ) /* (AIC) Fast Forcing Disable Register */ +#define AT91C_AIC_CISR ( 0xFFFFF114 ) /* (AIC) Core Interrupt Status Register */ +#define AT91C_AIC_IDCR ( 0xFFFFF124 ) /* (AIC) Interrupt Disable Command Register */ +#define AT91C_AIC_SPU ( 0xFFFFF134 ) /* (AIC) Spurious Vector Register */ +/* ========== Register definition for PDC_DBGU peripheral ========== */ +#define AT91C_DBGU_TCR ( 0xFFFFF30C ) /* (PDC_DBGU) Transmit Counter Register */ +#define AT91C_DBGU_RNPR ( 0xFFFFF310 ) /* (PDC_DBGU) Receive Next Pointer Register */ +#define AT91C_DBGU_TNPR ( 0xFFFFF318 ) /* (PDC_DBGU) Transmit Next Pointer Register */ +#define AT91C_DBGU_TPR ( 0xFFFFF308 ) /* (PDC_DBGU) Transmit Pointer Register */ +#define AT91C_DBGU_RPR ( 0xFFFFF300 ) /* (PDC_DBGU) Receive Pointer Register */ +#define AT91C_DBGU_RCR ( 0xFFFFF304 ) /* (PDC_DBGU) Receive Counter Register */ +#define AT91C_DBGU_RNCR ( 0xFFFFF314 ) /* (PDC_DBGU) Receive Next Counter Register */ +#define AT91C_DBGU_PTCR ( 0xFFFFF320 ) /* (PDC_DBGU) PDC Transfer Control Register */ +#define AT91C_DBGU_PTSR ( 0xFFFFF324 ) /* (PDC_DBGU) PDC Transfer Status Register */ +#define AT91C_DBGU_TNCR ( 0xFFFFF31C ) /* (PDC_DBGU) Transmit Next Counter Register */ +/* ========== Register definition for DBGU peripheral ========== */ +#define AT91C_DBGU_EXID ( 0xFFFFF244 ) /* (DBGU) Chip ID Extension Register */ +#define AT91C_DBGU_BRGR ( 0xFFFFF220 ) /* (DBGU) Baud Rate Generator Register */ +#define AT91C_DBGU_IDR ( 0xFFFFF20C ) /* (DBGU) Interrupt Disable Register */ +#define AT91C_DBGU_CSR ( 0xFFFFF214 ) /* (DBGU) Channel Status Register */ +#define AT91C_DBGU_CIDR ( 0xFFFFF240 ) /* (DBGU) Chip ID Register */ +#define AT91C_DBGU_MR ( 0xFFFFF204 ) /* (DBGU) Mode Register */ +#define AT91C_DBGU_IMR ( 0xFFFFF210 ) /* (DBGU) Interrupt Mask Register */ +#define AT91C_DBGU_CR ( 0xFFFFF200 ) /* (DBGU) Control Register */ +#define AT91C_DBGU_FNTR ( 0xFFFFF248 ) /* (DBGU) Force NTRST Register */ +#define AT91C_DBGU_THR ( 0xFFFFF21C ) /* (DBGU) Transmitter Holding Register */ +#define AT91C_DBGU_RHR ( 0xFFFFF218 ) /* (DBGU) Receiver Holding Register */ +#define AT91C_DBGU_IER ( 0xFFFFF208 ) /* (DBGU) Interrupt Enable Register */ +/* ========== Register definition for PIOA peripheral ========== */ +#define AT91C_PIOA_ODR ( 0xFFFFF414 ) /* (PIOA) Output Disable Registerr */ +#define AT91C_PIOA_SODR ( 0xFFFFF430 ) /* (PIOA) Set Output Data Register */ +#define AT91C_PIOA_ISR ( 0xFFFFF44C ) /* (PIOA) Interrupt Status Register */ +#define AT91C_PIOA_ABSR ( 0xFFFFF478 ) /* (PIOA) AB Select Status Register */ +#define AT91C_PIOA_IER ( 0xFFFFF440 ) /* (PIOA) Interrupt Enable Register */ +#define AT91C_PIOA_PPUDR ( 0xFFFFF460 ) /* (PIOA) Pull-up Disable Register */ +#define AT91C_PIOA_IMR ( 0xFFFFF448 ) /* (PIOA) Interrupt Mask Register */ +#define AT91C_PIOA_PER ( 0xFFFFF400 ) /* (PIOA) PIO Enable Register */ +#define AT91C_PIOA_IFDR ( 0xFFFFF424 ) /* (PIOA) Input Filter Disable Register */ +#define AT91C_PIOA_OWDR ( 0xFFFFF4A4 ) /* (PIOA) Output Write Disable Register */ +#define AT91C_PIOA_MDSR ( 0xFFFFF458 ) /* (PIOA) Multi-driver Status Register */ +#define AT91C_PIOA_IDR ( 0xFFFFF444 ) /* (PIOA) Interrupt Disable Register */ +#define AT91C_PIOA_ODSR ( 0xFFFFF438 ) /* (PIOA) Output Data Status Register */ +#define AT91C_PIOA_PPUSR ( 0xFFFFF468 ) /* (PIOA) Pull-up Status Register */ +#define AT91C_PIOA_OWSR ( 0xFFFFF4A8 ) /* (PIOA) Output Write Status Register */ +#define AT91C_PIOA_BSR ( 0xFFFFF474 ) /* (PIOA) Select B Register */ +#define AT91C_PIOA_OWER ( 0xFFFFF4A0 ) /* (PIOA) Output Write Enable Register */ +#define AT91C_PIOA_IFER ( 0xFFFFF420 ) /* (PIOA) Input Filter Enable Register */ +#define AT91C_PIOA_PDSR ( 0xFFFFF43C ) /* (PIOA) Pin Data Status Register */ +#define AT91C_PIOA_PPUER ( 0xFFFFF464 ) /* (PIOA) Pull-up Enable Register */ +#define AT91C_PIOA_OSR ( 0xFFFFF418 ) /* (PIOA) Output Status Register */ +#define AT91C_PIOA_ASR ( 0xFFFFF470 ) /* (PIOA) Select A Register */ +#define AT91C_PIOA_MDDR ( 0xFFFFF454 ) /* (PIOA) Multi-driver Disable Register */ +#define AT91C_PIOA_CODR ( 0xFFFFF434 ) /* (PIOA) Clear Output Data Register */ +#define AT91C_PIOA_MDER ( 0xFFFFF450 ) /* (PIOA) Multi-driver Enable Register */ +#define AT91C_PIOA_PDR ( 0xFFFFF404 ) /* (PIOA) PIO Disable Register */ +#define AT91C_PIOA_IFSR ( 0xFFFFF428 ) /* (PIOA) Input Filter Status Register */ +#define AT91C_PIOA_OER ( 0xFFFFF410 ) /* (PIOA) Output Enable Register */ +#define AT91C_PIOA_PSR ( 0xFFFFF408 ) /* (PIOA) PIO Status Register */ +/* ========== Register definition for PIOB peripheral ========== */ +#define AT91C_PIOB_OWDR ( 0xFFFFF6A4 ) /* (PIOB) Output Write Disable Register */ +#define AT91C_PIOB_MDER ( 0xFFFFF650 ) /* (PIOB) Multi-driver Enable Register */ +#define AT91C_PIOB_PPUSR ( 0xFFFFF668 ) /* (PIOB) Pull-up Status Register */ +#define AT91C_PIOB_IMR ( 0xFFFFF648 ) /* (PIOB) Interrupt Mask Register */ +#define AT91C_PIOB_ASR ( 0xFFFFF670 ) /* (PIOB) Select A Register */ +#define AT91C_PIOB_PPUDR ( 0xFFFFF660 ) /* (PIOB) Pull-up Disable Register */ +#define AT91C_PIOB_PSR ( 0xFFFFF608 ) /* (PIOB) PIO Status Register */ +#define AT91C_PIOB_IER ( 0xFFFFF640 ) /* (PIOB) Interrupt Enable Register */ +#define AT91C_PIOB_CODR ( 0xFFFFF634 ) /* (PIOB) Clear Output Data Register */ +#define AT91C_PIOB_OWER ( 0xFFFFF6A0 ) /* (PIOB) Output Write Enable Register */ +#define AT91C_PIOB_ABSR ( 0xFFFFF678 ) /* (PIOB) AB Select Status Register */ +#define AT91C_PIOB_IFDR ( 0xFFFFF624 ) /* (PIOB) Input Filter Disable Register */ +#define AT91C_PIOB_PDSR ( 0xFFFFF63C ) /* (PIOB) Pin Data Status Register */ +#define AT91C_PIOB_IDR ( 0xFFFFF644 ) /* (PIOB) Interrupt Disable Register */ +#define AT91C_PIOB_OWSR ( 0xFFFFF6A8 ) /* (PIOB) Output Write Status Register */ +#define AT91C_PIOB_PDR ( 0xFFFFF604 ) /* (PIOB) PIO Disable Register */ +#define AT91C_PIOB_ODR ( 0xFFFFF614 ) /* (PIOB) Output Disable Registerr */ +#define AT91C_PIOB_IFSR ( 0xFFFFF628 ) /* (PIOB) Input Filter Status Register */ +#define AT91C_PIOB_PPUER ( 0xFFFFF664 ) /* (PIOB) Pull-up Enable Register */ +#define AT91C_PIOB_SODR ( 0xFFFFF630 ) /* (PIOB) Set Output Data Register */ +#define AT91C_PIOB_ISR ( 0xFFFFF64C ) /* (PIOB) Interrupt Status Register */ +#define AT91C_PIOB_ODSR ( 0xFFFFF638 ) /* (PIOB) Output Data Status Register */ +#define AT91C_PIOB_OSR ( 0xFFFFF618 ) /* (PIOB) Output Status Register */ +#define AT91C_PIOB_MDSR ( 0xFFFFF658 ) /* (PIOB) Multi-driver Status Register */ +#define AT91C_PIOB_IFER ( 0xFFFFF620 ) /* (PIOB) Input Filter Enable Register */ +#define AT91C_PIOB_BSR ( 0xFFFFF674 ) /* (PIOB) Select B Register */ +#define AT91C_PIOB_MDDR ( 0xFFFFF654 ) /* (PIOB) Multi-driver Disable Register */ +#define AT91C_PIOB_OER ( 0xFFFFF610 ) /* (PIOB) Output Enable Register */ +#define AT91C_PIOB_PER ( 0xFFFFF600 ) /* (PIOB) PIO Enable Register */ +/* ========== Register definition for CKGR peripheral ========== */ +#define AT91C_CKGR_MOR ( 0xFFFFFC20 ) /* (CKGR) Main Oscillator Register */ +#define AT91C_CKGR_PLLR ( 0xFFFFFC2C ) /* (CKGR) PLL Register */ +#define AT91C_CKGR_MCFR ( 0xFFFFFC24 ) /* (CKGR) Main Clock Frequency Register */ +/* ========== Register definition for PMC peripheral ========== */ +#define AT91C_PMC_IDR ( 0xFFFFFC64 ) /* (PMC) Interrupt Disable Register */ +#define AT91C_PMC_MOR ( 0xFFFFFC20 ) /* (PMC) Main Oscillator Register */ +#define AT91C_PMC_PLLR ( 0xFFFFFC2C ) /* (PMC) PLL Register */ +#define AT91C_PMC_PCER ( 0xFFFFFC10 ) /* (PMC) Peripheral Clock Enable Register */ +#define AT91C_PMC_PCKR ( 0xFFFFFC40 ) /* (PMC) Programmable Clock Register */ +#define AT91C_PMC_MCKR ( 0xFFFFFC30 ) /* (PMC) Master Clock Register */ +#define AT91C_PMC_SCDR ( 0xFFFFFC04 ) /* (PMC) System Clock Disable Register */ +#define AT91C_PMC_PCDR ( 0xFFFFFC14 ) /* (PMC) Peripheral Clock Disable Register */ +#define AT91C_PMC_SCSR ( 0xFFFFFC08 ) /* (PMC) System Clock Status Register */ +#define AT91C_PMC_PCSR ( 0xFFFFFC18 ) /* (PMC) Peripheral Clock Status Register */ +#define AT91C_PMC_MCFR ( 0xFFFFFC24 ) /* (PMC) Main Clock Frequency Register */ +#define AT91C_PMC_SCER ( 0xFFFFFC00 ) /* (PMC) System Clock Enable Register */ +#define AT91C_PMC_IMR ( 0xFFFFFC6C ) /* (PMC) Interrupt Mask Register */ +#define AT91C_PMC_IER ( 0xFFFFFC60 ) /* (PMC) Interrupt Enable Register */ +#define AT91C_PMC_SR ( 0xFFFFFC68 ) /* (PMC) Status Register */ +/* ========== Register definition for RSTC peripheral ========== */ +#define AT91C_RSTC_RCR ( 0xFFFFFD00 ) /* (RSTC) Reset Control Register */ +#define AT91C_RSTC_RMR ( 0xFFFFFD08 ) /* (RSTC) Reset Mode Register */ +#define AT91C_RSTC_RSR ( 0xFFFFFD04 ) /* (RSTC) Reset Status Register */ +/* ========== Register definition for RTTC peripheral ========== */ +#define AT91C_RTTC_RTSR ( 0xFFFFFD2C ) /* (RTTC) Real-time Status Register */ +#define AT91C_RTTC_RTMR ( 0xFFFFFD20 ) /* (RTTC) Real-time Mode Register */ +#define AT91C_RTTC_RTVR ( 0xFFFFFD28 ) /* (RTTC) Real-time Value Register */ +#define AT91C_RTTC_RTAR ( 0xFFFFFD24 ) /* (RTTC) Real-time Alarm Register */ +/* ========== Register definition for PITC peripheral ========== */ +#define AT91C_PITC_PIVR ( 0xFFFFFD38 ) /* (PITC) Period Interval Value Register */ +#define AT91C_PITC_PISR ( 0xFFFFFD34 ) /* (PITC) Period Interval Status Register */ +#define AT91C_PITC_PIIR ( 0xFFFFFD3C ) /* (PITC) Period Interval Image Register */ +#define AT91C_PITC_PIMR ( 0xFFFFFD30 ) /* (PITC) Period Interval Mode Register */ +/* ========== Register definition for WDTC peripheral ========== */ +#define AT91C_WDTC_WDCR ( 0xFFFFFD40 ) /* (WDTC) Watchdog Control Register */ +#define AT91C_WDTC_WDSR ( 0xFFFFFD48 ) /* (WDTC) Watchdog Status Register */ +#define AT91C_WDTC_WDMR ( 0xFFFFFD44 ) /* (WDTC) Watchdog Mode Register */ +/* ========== Register definition for VREG peripheral ========== */ +#define AT91C_VREG_MR ( 0xFFFFFD60 ) /* (VREG) Voltage Regulator Mode Register */ +/* ========== Register definition for MC peripheral ========== */ +#define AT91C_MC_ASR ( 0xFFFFFF04 ) /* (MC) MC Abort Status Register */ +#define AT91C_MC_RCR ( 0xFFFFFF00 ) /* (MC) MC Remap Control Register */ +#define AT91C_MC_FCR ( 0xFFFFFF64 ) /* (MC) MC Flash Command Register */ +#define AT91C_MC_AASR ( 0xFFFFFF08 ) /* (MC) MC Abort Address Status Register */ +#define AT91C_MC_FSR ( 0xFFFFFF68 ) /* (MC) MC Flash Status Register */ +#define AT91C_MC_FMR ( 0xFFFFFF60 ) /* (MC) MC Flash Mode Register */ +/* ========== Register definition for PDC_SPI1 peripheral ========== */ +#define AT91C_SPI1_PTCR ( 0xFFFE4120 ) /* (PDC_SPI1) PDC Transfer Control Register */ +#define AT91C_SPI1_RPR ( 0xFFFE4100 ) /* (PDC_SPI1) Receive Pointer Register */ +#define AT91C_SPI1_TNCR ( 0xFFFE411C ) /* (PDC_SPI1) Transmit Next Counter Register */ +#define AT91C_SPI1_TPR ( 0xFFFE4108 ) /* (PDC_SPI1) Transmit Pointer Register */ +#define AT91C_SPI1_TNPR ( 0xFFFE4118 ) /* (PDC_SPI1) Transmit Next Pointer Register */ +#define AT91C_SPI1_TCR ( 0xFFFE410C ) /* (PDC_SPI1) Transmit Counter Register */ +#define AT91C_SPI1_RCR ( 0xFFFE4104 ) /* (PDC_SPI1) Receive Counter Register */ +#define AT91C_SPI1_RNPR ( 0xFFFE4110 ) /* (PDC_SPI1) Receive Next Pointer Register */ +#define AT91C_SPI1_RNCR ( 0xFFFE4114 ) /* (PDC_SPI1) Receive Next Counter Register */ +#define AT91C_SPI1_PTSR ( 0xFFFE4124 ) /* (PDC_SPI1) PDC Transfer Status Register */ +/* ========== Register definition for SPI1 peripheral ========== */ +#define AT91C_SPI1_IMR ( 0xFFFE401C ) /* (SPI1) Interrupt Mask Register */ +#define AT91C_SPI1_IER ( 0xFFFE4014 ) /* (SPI1) Interrupt Enable Register */ +#define AT91C_SPI1_MR ( 0xFFFE4004 ) /* (SPI1) Mode Register */ +#define AT91C_SPI1_RDR ( 0xFFFE4008 ) /* (SPI1) Receive Data Register */ +#define AT91C_SPI1_IDR ( 0xFFFE4018 ) /* (SPI1) Interrupt Disable Register */ +#define AT91C_SPI1_SR ( 0xFFFE4010 ) /* (SPI1) Status Register */ +#define AT91C_SPI1_TDR ( 0xFFFE400C ) /* (SPI1) Transmit Data Register */ +#define AT91C_SPI1_CR ( 0xFFFE4000 ) /* (SPI1) Control Register */ +#define AT91C_SPI1_CSR ( 0xFFFE4030 ) /* (SPI1) Chip Select Register */ +/* ========== Register definition for PDC_SPI0 peripheral ========== */ +#define AT91C_SPI0_PTCR ( 0xFFFE0120 ) /* (PDC_SPI0) PDC Transfer Control Register */ +#define AT91C_SPI0_TPR ( 0xFFFE0108 ) /* (PDC_SPI0) Transmit Pointer Register */ +#define AT91C_SPI0_TCR ( 0xFFFE010C ) /* (PDC_SPI0) Transmit Counter Register */ +#define AT91C_SPI0_RCR ( 0xFFFE0104 ) /* (PDC_SPI0) Receive Counter Register */ +#define AT91C_SPI0_PTSR ( 0xFFFE0124 ) /* (PDC_SPI0) PDC Transfer Status Register */ +#define AT91C_SPI0_RNPR ( 0xFFFE0110 ) /* (PDC_SPI0) Receive Next Pointer Register */ +#define AT91C_SPI0_RPR ( 0xFFFE0100 ) /* (PDC_SPI0) Receive Pointer Register */ +#define AT91C_SPI0_TNCR ( 0xFFFE011C ) /* (PDC_SPI0) Transmit Next Counter Register */ +#define AT91C_SPI0_RNCR ( 0xFFFE0114 ) /* (PDC_SPI0) Receive Next Counter Register */ +#define AT91C_SPI0_TNPR ( 0xFFFE0118 ) /* (PDC_SPI0) Transmit Next Pointer Register */ +/* ========== Register definition for SPI0 peripheral ========== */ +#define AT91C_SPI0_IER ( 0xFFFE0014 ) /* (SPI0) Interrupt Enable Register */ +#define AT91C_SPI0_SR ( 0xFFFE0010 ) /* (SPI0) Status Register */ +#define AT91C_SPI0_IDR ( 0xFFFE0018 ) /* (SPI0) Interrupt Disable Register */ +#define AT91C_SPI0_CR ( 0xFFFE0000 ) /* (SPI0) Control Register */ +#define AT91C_SPI0_MR ( 0xFFFE0004 ) /* (SPI0) Mode Register */ +#define AT91C_SPI0_IMR ( 0xFFFE001C ) /* (SPI0) Interrupt Mask Register */ +#define AT91C_SPI0_TDR ( 0xFFFE000C ) /* (SPI0) Transmit Data Register */ +#define AT91C_SPI0_RDR ( 0xFFFE0008 ) /* (SPI0) Receive Data Register */ +#define AT91C_SPI0_CSR ( 0xFFFE0030 ) /* (SPI0) Chip Select Register */ +/* ========== Register definition for PDC_US1 peripheral ========== */ +#define AT91C_US1_RNCR ( 0xFFFC4114 ) /* (PDC_US1) Receive Next Counter Register */ +#define AT91C_US1_PTCR ( 0xFFFC4120 ) /* (PDC_US1) PDC Transfer Control Register */ +#define AT91C_US1_TCR ( 0xFFFC410C ) /* (PDC_US1) Transmit Counter Register */ +#define AT91C_US1_PTSR ( 0xFFFC4124 ) /* (PDC_US1) PDC Transfer Status Register */ +#define AT91C_US1_TNPR ( 0xFFFC4118 ) /* (PDC_US1) Transmit Next Pointer Register */ +#define AT91C_US1_RCR ( 0xFFFC4104 ) /* (PDC_US1) Receive Counter Register */ +#define AT91C_US1_RNPR ( 0xFFFC4110 ) /* (PDC_US1) Receive Next Pointer Register */ +#define AT91C_US1_RPR ( 0xFFFC4100 ) /* (PDC_US1) Receive Pointer Register */ +#define AT91C_US1_TNCR ( 0xFFFC411C ) /* (PDC_US1) Transmit Next Counter Register */ +#define AT91C_US1_TPR ( 0xFFFC4108 ) /* (PDC_US1) Transmit Pointer Register */ +/* ========== Register definition for US1 peripheral ========== */ +#define AT91C_US1_IF ( 0xFFFC404C ) /* (US1) IRDA_FILTER Register */ +#define AT91C_US1_NER ( 0xFFFC4044 ) /* (US1) Nb Errors Register */ +#define AT91C_US1_RTOR ( 0xFFFC4024 ) /* (US1) Receiver Time-out Register */ +#define AT91C_US1_CSR ( 0xFFFC4014 ) /* (US1) Channel Status Register */ +#define AT91C_US1_IDR ( 0xFFFC400C ) /* (US1) Interrupt Disable Register */ +#define AT91C_US1_IER ( 0xFFFC4008 ) /* (US1) Interrupt Enable Register */ +#define AT91C_US1_THR ( 0xFFFC401C ) /* (US1) Transmitter Holding Register */ +#define AT91C_US1_TTGR ( 0xFFFC4028 ) /* (US1) Transmitter Time-guard Register */ +#define AT91C_US1_RHR ( 0xFFFC4018 ) /* (US1) Receiver Holding Register */ +#define AT91C_US1_BRGR ( 0xFFFC4020 ) /* (US1) Baud Rate Generator Register */ +#define AT91C_US1_IMR ( 0xFFFC4010 ) /* (US1) Interrupt Mask Register */ +#define AT91C_US1_FIDI ( 0xFFFC4040 ) /* (US1) FI_DI_Ratio Register */ +#define AT91C_US1_CR ( 0xFFFC4000 ) /* (US1) Control Register */ +#define AT91C_US1_MR ( 0xFFFC4004 ) /* (US1) Mode Register */ +/* ========== Register definition for PDC_US0 peripheral ========== */ +#define AT91C_US0_TNPR ( 0xFFFC0118 ) /* (PDC_US0) Transmit Next Pointer Register */ +#define AT91C_US0_RNPR ( 0xFFFC0110 ) /* (PDC_US0) Receive Next Pointer Register */ +#define AT91C_US0_TCR ( 0xFFFC010C ) /* (PDC_US0) Transmit Counter Register */ +#define AT91C_US0_PTCR ( 0xFFFC0120 ) /* (PDC_US0) PDC Transfer Control Register */ +#define AT91C_US0_PTSR ( 0xFFFC0124 ) /* (PDC_US0) PDC Transfer Status Register */ +#define AT91C_US0_TNCR ( 0xFFFC011C ) /* (PDC_US0) Transmit Next Counter Register */ +#define AT91C_US0_TPR ( 0xFFFC0108 ) /* (PDC_US0) Transmit Pointer Register */ +#define AT91C_US0_RCR ( 0xFFFC0104 ) /* (PDC_US0) Receive Counter Register */ +#define AT91C_US0_RPR ( 0xFFFC0100 ) /* (PDC_US0) Receive Pointer Register */ +#define AT91C_US0_RNCR ( 0xFFFC0114 ) /* (PDC_US0) Receive Next Counter Register */ +/* ========== Register definition for US0 peripheral ========== */ +#define AT91C_US0_BRGR ( 0xFFFC0020 ) /* (US0) Baud Rate Generator Register */ +#define AT91C_US0_NER ( 0xFFFC0044 ) /* (US0) Nb Errors Register */ +#define AT91C_US0_CR ( 0xFFFC0000 ) /* (US0) Control Register */ +#define AT91C_US0_IMR ( 0xFFFC0010 ) /* (US0) Interrupt Mask Register */ +#define AT91C_US0_FIDI ( 0xFFFC0040 ) /* (US0) FI_DI_Ratio Register */ +#define AT91C_US0_TTGR ( 0xFFFC0028 ) /* (US0) Transmitter Time-guard Register */ +#define AT91C_US0_MR ( 0xFFFC0004 ) /* (US0) Mode Register */ +#define AT91C_US0_RTOR ( 0xFFFC0024 ) /* (US0) Receiver Time-out Register */ +#define AT91C_US0_CSR ( 0xFFFC0014 ) /* (US0) Channel Status Register */ +#define AT91C_US0_RHR ( 0xFFFC0018 ) /* (US0) Receiver Holding Register */ +#define AT91C_US0_IDR ( 0xFFFC000C ) /* (US0) Interrupt Disable Register */ +#define AT91C_US0_THR ( 0xFFFC001C ) /* (US0) Transmitter Holding Register */ +#define AT91C_US0_IF ( 0xFFFC004C ) /* (US0) IRDA_FILTER Register */ +#define AT91C_US0_IER ( 0xFFFC0008 ) /* (US0) Interrupt Enable Register */ +/* ========== Register definition for PDC_SSC peripheral ========== */ +#define AT91C_SSC_TNCR ( 0xFFFD411C ) /* (PDC_SSC) Transmit Next Counter Register */ +#define AT91C_SSC_RPR ( 0xFFFD4100 ) /* (PDC_SSC) Receive Pointer Register */ +#define AT91C_SSC_RNCR ( 0xFFFD4114 ) /* (PDC_SSC) Receive Next Counter Register */ +#define AT91C_SSC_TPR ( 0xFFFD4108 ) /* (PDC_SSC) Transmit Pointer Register */ +#define AT91C_SSC_PTCR ( 0xFFFD4120 ) /* (PDC_SSC) PDC Transfer Control Register */ +#define AT91C_SSC_TCR ( 0xFFFD410C ) /* (PDC_SSC) Transmit Counter Register */ +#define AT91C_SSC_RCR ( 0xFFFD4104 ) /* (PDC_SSC) Receive Counter Register */ +#define AT91C_SSC_RNPR ( 0xFFFD4110 ) /* (PDC_SSC) Receive Next Pointer Register */ +#define AT91C_SSC_TNPR ( 0xFFFD4118 ) /* (PDC_SSC) Transmit Next Pointer Register */ +#define AT91C_SSC_PTSR ( 0xFFFD4124 ) /* (PDC_SSC) PDC Transfer Status Register */ +/* ========== Register definition for SSC peripheral ========== */ +#define AT91C_SSC_RHR ( 0xFFFD4020 ) /* (SSC) Receive Holding Register */ +#define AT91C_SSC_RSHR ( 0xFFFD4030 ) /* (SSC) Receive Sync Holding Register */ +#define AT91C_SSC_TFMR ( 0xFFFD401C ) /* (SSC) Transmit Frame Mode Register */ +#define AT91C_SSC_IDR ( 0xFFFD4048 ) /* (SSC) Interrupt Disable Register */ +#define AT91C_SSC_THR ( 0xFFFD4024 ) /* (SSC) Transmit Holding Register */ +#define AT91C_SSC_RCMR ( 0xFFFD4010 ) /* (SSC) Receive Clock ModeRegister */ +#define AT91C_SSC_IER ( 0xFFFD4044 ) /* (SSC) Interrupt Enable Register */ +#define AT91C_SSC_TSHR ( 0xFFFD4034 ) /* (SSC) Transmit Sync Holding Register */ +#define AT91C_SSC_SR ( 0xFFFD4040 ) /* (SSC) Status Register */ +#define AT91C_SSC_CMR ( 0xFFFD4004 ) /* (SSC) Clock Mode Register */ +#define AT91C_SSC_TCMR ( 0xFFFD4018 ) /* (SSC) Transmit Clock Mode Register */ +#define AT91C_SSC_CR ( 0xFFFD4000 ) /* (SSC) Control Register */ +#define AT91C_SSC_IMR ( 0xFFFD404C ) /* (SSC) Interrupt Mask Register */ +#define AT91C_SSC_RFMR ( 0xFFFD4014 ) /* (SSC) Receive Frame Mode Register */ +/* ========== Register definition for TWI peripheral ========== */ +#define AT91C_TWI_IER ( 0xFFFB8024 ) /* (TWI) Interrupt Enable Register */ +#define AT91C_TWI_CR ( 0xFFFB8000 ) /* (TWI) Control Register */ +#define AT91C_TWI_SR ( 0xFFFB8020 ) /* (TWI) Status Register */ +#define AT91C_TWI_IMR ( 0xFFFB802C ) /* (TWI) Interrupt Mask Register */ +#define AT91C_TWI_THR ( 0xFFFB8034 ) /* (TWI) Transmit Holding Register */ +#define AT91C_TWI_IDR ( 0xFFFB8028 ) /* (TWI) Interrupt Disable Register */ +#define AT91C_TWI_IADR ( 0xFFFB800C ) /* (TWI) Internal Address Register */ +#define AT91C_TWI_MMR ( 0xFFFB8004 ) /* (TWI) Master Mode Register */ +#define AT91C_TWI_CWGR ( 0xFFFB8010 ) /* (TWI) Clock Waveform Generator Register */ +#define AT91C_TWI_RHR ( 0xFFFB8030 ) /* (TWI) Receive Holding Register */ +/* ========== Register definition for PWMC_CH3 peripheral ========== */ +#define AT91C_PWMC_CH3_CUPDR ( 0xFFFCC270 ) /* (PWMC_CH3) Channel Update Register */ +#define AT91C_PWMC_CH3_Reserved ( 0xFFFCC274 ) /* (PWMC_CH3) Reserved */ +#define AT91C_PWMC_CH3_CPRDR ( 0xFFFCC268 ) /* (PWMC_CH3) Channel Period Register */ +#define AT91C_PWMC_CH3_CDTYR ( 0xFFFCC264 ) /* (PWMC_CH3) Channel Duty Cycle Register */ +#define AT91C_PWMC_CH3_CCNTR ( 0xFFFCC26C ) /* (PWMC_CH3) Channel Counter Register */ +#define AT91C_PWMC_CH3_CMR ( 0xFFFCC260 ) /* (PWMC_CH3) Channel Mode Register */ +/* ========== Register definition for PWMC_CH2 peripheral ========== */ +#define AT91C_PWMC_CH2_Reserved ( 0xFFFCC254 ) /* (PWMC_CH2) Reserved */ +#define AT91C_PWMC_CH2_CMR ( 0xFFFCC240 ) /* (PWMC_CH2) Channel Mode Register */ +#define AT91C_PWMC_CH2_CCNTR ( 0xFFFCC24C ) /* (PWMC_CH2) Channel Counter Register */ +#define AT91C_PWMC_CH2_CPRDR ( 0xFFFCC248 ) /* (PWMC_CH2) Channel Period Register */ +#define AT91C_PWMC_CH2_CUPDR ( 0xFFFCC250 ) /* (PWMC_CH2) Channel Update Register */ +#define AT91C_PWMC_CH2_CDTYR ( 0xFFFCC244 ) /* (PWMC_CH2) Channel Duty Cycle Register */ +/* ========== Register definition for PWMC_CH1 peripheral ========== */ +#define AT91C_PWMC_CH1_Reserved ( 0xFFFCC234 ) /* (PWMC_CH1) Reserved */ +#define AT91C_PWMC_CH1_CUPDR ( 0xFFFCC230 ) /* (PWMC_CH1) Channel Update Register */ +#define AT91C_PWMC_CH1_CPRDR ( 0xFFFCC228 ) /* (PWMC_CH1) Channel Period Register */ +#define AT91C_PWMC_CH1_CCNTR ( 0xFFFCC22C ) /* (PWMC_CH1) Channel Counter Register */ +#define AT91C_PWMC_CH1_CDTYR ( 0xFFFCC224 ) /* (PWMC_CH1) Channel Duty Cycle Register */ +#define AT91C_PWMC_CH1_CMR ( 0xFFFCC220 ) /* (PWMC_CH1) Channel Mode Register */ +/* ========== Register definition for PWMC_CH0 peripheral ========== */ +#define AT91C_PWMC_CH0_Reserved ( 0xFFFCC214 ) /* (PWMC_CH0) Reserved */ +#define AT91C_PWMC_CH0_CPRDR ( 0xFFFCC208 ) /* (PWMC_CH0) Channel Period Register */ +#define AT91C_PWMC_CH0_CDTYR ( 0xFFFCC204 ) /* (PWMC_CH0) Channel Duty Cycle Register */ +#define AT91C_PWMC_CH0_CMR ( 0xFFFCC200 ) /* (PWMC_CH0) Channel Mode Register */ +#define AT91C_PWMC_CH0_CUPDR ( 0xFFFCC210 ) /* (PWMC_CH0) Channel Update Register */ +#define AT91C_PWMC_CH0_CCNTR ( 0xFFFCC20C ) /* (PWMC_CH0) Channel Counter Register */ +/* ========== Register definition for PWMC peripheral ========== */ +#define AT91C_PWMC_IDR ( 0xFFFCC014 ) /* (PWMC) PWMC Interrupt Disable Register */ +#define AT91C_PWMC_DIS ( 0xFFFCC008 ) /* (PWMC) PWMC Disable Register */ +#define AT91C_PWMC_IER ( 0xFFFCC010 ) /* (PWMC) PWMC Interrupt Enable Register */ +#define AT91C_PWMC_VR ( 0xFFFCC0FC ) /* (PWMC) PWMC Version Register */ +#define AT91C_PWMC_ISR ( 0xFFFCC01C ) /* (PWMC) PWMC Interrupt Status Register */ +#define AT91C_PWMC_SR ( 0xFFFCC00C ) /* (PWMC) PWMC Status Register */ +#define AT91C_PWMC_IMR ( 0xFFFCC018 ) /* (PWMC) PWMC Interrupt Mask Register */ +#define AT91C_PWMC_MR ( 0xFFFCC000 ) /* (PWMC) PWMC Mode Register */ +#define AT91C_PWMC_ENA ( 0xFFFCC004 ) /* (PWMC) PWMC Enable Register */ +/* ========== Register definition for UDP peripheral ========== */ +#define AT91C_UDP_IMR ( 0xFFFB0018 ) /* (UDP) Interrupt Mask Register */ +#define AT91C_UDP_FADDR ( 0xFFFB0008 ) /* (UDP) Function Address Register */ +#define AT91C_UDP_NUM ( 0xFFFB0000 ) /* (UDP) Frame Number Register */ +#define AT91C_UDP_FDR ( 0xFFFB0050 ) /* (UDP) Endpoint FIFO Data Register */ +#define AT91C_UDP_ISR ( 0xFFFB001C ) /* (UDP) Interrupt Status Register */ +#define AT91C_UDP_CSR ( 0xFFFB0030 ) /* (UDP) Endpoint Control and Status Register */ +#define AT91C_UDP_IDR ( 0xFFFB0014 ) /* (UDP) Interrupt Disable Register */ +#define AT91C_UDP_ICR ( 0xFFFB0020 ) /* (UDP) Interrupt Clear Register */ +#define AT91C_UDP_RSTEP ( 0xFFFB0028 ) /* (UDP) Reset Endpoint Register */ +#define AT91C_UDP_TXVC ( 0xFFFB0074 ) /* (UDP) Transceiver Control Register */ +#define AT91C_UDP_GLBSTATE ( 0xFFFB0004 ) /* (UDP) Global State Register */ +#define AT91C_UDP_IER ( 0xFFFB0010 ) /* (UDP) Interrupt Enable Register */ +/* ========== Register definition for TC0 peripheral ========== */ +#define AT91C_TC0_SR ( 0xFFFA0020 ) /* (TC0) Status Register */ +#define AT91C_TC0_RC ( 0xFFFA001C ) /* (TC0) Register C */ +#define AT91C_TC0_RB ( 0xFFFA0018 ) /* (TC0) Register B */ +#define AT91C_TC0_CCR ( 0xFFFA0000 ) /* (TC0) Channel Control Register */ +#define AT91C_TC0_CMR ( 0xFFFA0004 ) /* (TC0) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC0_IER ( 0xFFFA0024 ) /* (TC0) Interrupt Enable Register */ +#define AT91C_TC0_RA ( 0xFFFA0014 ) /* (TC0) Register A */ +#define AT91C_TC0_IDR ( 0xFFFA0028 ) /* (TC0) Interrupt Disable Register */ +#define AT91C_TC0_CV ( 0xFFFA0010 ) /* (TC0) Counter Value */ +#define AT91C_TC0_IMR ( 0xFFFA002C ) /* (TC0) Interrupt Mask Register */ +/* ========== Register definition for TC1 peripheral ========== */ +#define AT91C_TC1_RB ( 0xFFFA0058 ) /* (TC1) Register B */ +#define AT91C_TC1_CCR ( 0xFFFA0040 ) /* (TC1) Channel Control Register */ +#define AT91C_TC1_IER ( 0xFFFA0064 ) /* (TC1) Interrupt Enable Register */ +#define AT91C_TC1_IDR ( 0xFFFA0068 ) /* (TC1) Interrupt Disable Register */ +#define AT91C_TC1_SR ( 0xFFFA0060 ) /* (TC1) Status Register */ +#define AT91C_TC1_CMR ( 0xFFFA0044 ) /* (TC1) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC1_RA ( 0xFFFA0054 ) /* (TC1) Register A */ +#define AT91C_TC1_RC ( 0xFFFA005C ) /* (TC1) Register C */ +#define AT91C_TC1_IMR ( 0xFFFA006C ) /* (TC1) Interrupt Mask Register */ +#define AT91C_TC1_CV ( 0xFFFA0050 ) /* (TC1) Counter Value */ +/* ========== Register definition for TC2 peripheral ========== */ +#define AT91C_TC2_CMR ( 0xFFFA0084 ) /* (TC2) Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC2_CCR ( 0xFFFA0080 ) /* (TC2) Channel Control Register */ +#define AT91C_TC2_CV ( 0xFFFA0090 ) /* (TC2) Counter Value */ +#define AT91C_TC2_RA ( 0xFFFA0094 ) /* (TC2) Register A */ +#define AT91C_TC2_RB ( 0xFFFA0098 ) /* (TC2) Register B */ +#define AT91C_TC2_IDR ( 0xFFFA00A8 ) /* (TC2) Interrupt Disable Register */ +#define AT91C_TC2_IMR ( 0xFFFA00AC ) /* (TC2) Interrupt Mask Register */ +#define AT91C_TC2_RC ( 0xFFFA009C ) /* (TC2) Register C */ +#define AT91C_TC2_IER ( 0xFFFA00A4 ) /* (TC2) Interrupt Enable Register */ +#define AT91C_TC2_SR ( 0xFFFA00A0 ) /* (TC2) Status Register */ +/* ========== Register definition for TCB peripheral ========== */ +#define AT91C_TCB_BMR ( 0xFFFA00C4 ) /* (TCB) TC Block Mode Register */ +#define AT91C_TCB_BCR ( 0xFFFA00C0 ) /* (TCB) TC Block Control Register */ +/* ========== Register definition for CAN_MB0 peripheral ========== */ +#define AT91C_CAN_MB0_MDL ( 0xFFFD0214 ) /* (CAN_MB0) MailBox Data Low Register */ +#define AT91C_CAN_MB0_MAM ( 0xFFFD0204 ) /* (CAN_MB0) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB0_MCR ( 0xFFFD021C ) /* (CAN_MB0) MailBox Control Register */ +#define AT91C_CAN_MB0_MID ( 0xFFFD0208 ) /* (CAN_MB0) MailBox ID Register */ +#define AT91C_CAN_MB0_MSR ( 0xFFFD0210 ) /* (CAN_MB0) MailBox Status Register */ +#define AT91C_CAN_MB0_MFID ( 0xFFFD020C ) /* (CAN_MB0) MailBox Family ID Register */ +#define AT91C_CAN_MB0_MDH ( 0xFFFD0218 ) /* (CAN_MB0) MailBox Data High Register */ +#define AT91C_CAN_MB0_MMR ( 0xFFFD0200 ) /* (CAN_MB0) MailBox Mode Register */ +/* ========== Register definition for CAN_MB1 peripheral ========== */ +#define AT91C_CAN_MB1_MDL ( 0xFFFD0234 ) /* (CAN_MB1) MailBox Data Low Register */ +#define AT91C_CAN_MB1_MID ( 0xFFFD0228 ) /* (CAN_MB1) MailBox ID Register */ +#define AT91C_CAN_MB1_MMR ( 0xFFFD0220 ) /* (CAN_MB1) MailBox Mode Register */ +#define AT91C_CAN_MB1_MSR ( 0xFFFD0230 ) /* (CAN_MB1) MailBox Status Register */ +#define AT91C_CAN_MB1_MAM ( 0xFFFD0224 ) /* (CAN_MB1) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB1_MDH ( 0xFFFD0238 ) /* (CAN_MB1) MailBox Data High Register */ +#define AT91C_CAN_MB1_MCR ( 0xFFFD023C ) /* (CAN_MB1) MailBox Control Register */ +#define AT91C_CAN_MB1_MFID ( 0xFFFD022C ) /* (CAN_MB1) MailBox Family ID Register */ +/* ========== Register definition for CAN_MB2 peripheral ========== */ +#define AT91C_CAN_MB2_MCR ( 0xFFFD025C ) /* (CAN_MB2) MailBox Control Register */ +#define AT91C_CAN_MB2_MDH ( 0xFFFD0258 ) /* (CAN_MB2) MailBox Data High Register */ +#define AT91C_CAN_MB2_MID ( 0xFFFD0248 ) /* (CAN_MB2) MailBox ID Register */ +#define AT91C_CAN_MB2_MDL ( 0xFFFD0254 ) /* (CAN_MB2) MailBox Data Low Register */ +#define AT91C_CAN_MB2_MMR ( 0xFFFD0240 ) /* (CAN_MB2) MailBox Mode Register */ +#define AT91C_CAN_MB2_MAM ( 0xFFFD0244 ) /* (CAN_MB2) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB2_MFID ( 0xFFFD024C ) /* (CAN_MB2) MailBox Family ID Register */ +#define AT91C_CAN_MB2_MSR ( 0xFFFD0250 ) /* (CAN_MB2) MailBox Status Register */ +/* ========== Register definition for CAN_MB3 peripheral ========== */ +#define AT91C_CAN_MB3_MFID ( 0xFFFD026C ) /* (CAN_MB3) MailBox Family ID Register */ +#define AT91C_CAN_MB3_MAM ( 0xFFFD0264 ) /* (CAN_MB3) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB3_MID ( 0xFFFD0268 ) /* (CAN_MB3) MailBox ID Register */ +#define AT91C_CAN_MB3_MCR ( 0xFFFD027C ) /* (CAN_MB3) MailBox Control Register */ +#define AT91C_CAN_MB3_MMR ( 0xFFFD0260 ) /* (CAN_MB3) MailBox Mode Register */ +#define AT91C_CAN_MB3_MSR ( 0xFFFD0270 ) /* (CAN_MB3) MailBox Status Register */ +#define AT91C_CAN_MB3_MDL ( 0xFFFD0274 ) /* (CAN_MB3) MailBox Data Low Register */ +#define AT91C_CAN_MB3_MDH ( 0xFFFD0278 ) /* (CAN_MB3) MailBox Data High Register */ +/* ========== Register definition for CAN_MB4 peripheral ========== */ +#define AT91C_CAN_MB4_MID ( 0xFFFD0288 ) /* (CAN_MB4) MailBox ID Register */ +#define AT91C_CAN_MB4_MMR ( 0xFFFD0280 ) /* (CAN_MB4) MailBox Mode Register */ +#define AT91C_CAN_MB4_MDH ( 0xFFFD0298 ) /* (CAN_MB4) MailBox Data High Register */ +#define AT91C_CAN_MB4_MFID ( 0xFFFD028C ) /* (CAN_MB4) MailBox Family ID Register */ +#define AT91C_CAN_MB4_MSR ( 0xFFFD0290 ) /* (CAN_MB4) MailBox Status Register */ +#define AT91C_CAN_MB4_MCR ( 0xFFFD029C ) /* (CAN_MB4) MailBox Control Register */ +#define AT91C_CAN_MB4_MDL ( 0xFFFD0294 ) /* (CAN_MB4) MailBox Data Low Register */ +#define AT91C_CAN_MB4_MAM ( 0xFFFD0284 ) /* (CAN_MB4) MailBox Acceptance Mask Register */ +/* ========== Register definition for CAN_MB5 peripheral ========== */ +#define AT91C_CAN_MB5_MSR ( 0xFFFD02B0 ) /* (CAN_MB5) MailBox Status Register */ +#define AT91C_CAN_MB5_MCR ( 0xFFFD02BC ) /* (CAN_MB5) MailBox Control Register */ +#define AT91C_CAN_MB5_MFID ( 0xFFFD02AC ) /* (CAN_MB5) MailBox Family ID Register */ +#define AT91C_CAN_MB5_MDH ( 0xFFFD02B8 ) /* (CAN_MB5) MailBox Data High Register */ +#define AT91C_CAN_MB5_MID ( 0xFFFD02A8 ) /* (CAN_MB5) MailBox ID Register */ +#define AT91C_CAN_MB5_MMR ( 0xFFFD02A0 ) /* (CAN_MB5) MailBox Mode Register */ +#define AT91C_CAN_MB5_MDL ( 0xFFFD02B4 ) /* (CAN_MB5) MailBox Data Low Register */ +#define AT91C_CAN_MB5_MAM ( 0xFFFD02A4 ) /* (CAN_MB5) MailBox Acceptance Mask Register */ +/* ========== Register definition for CAN_MB6 peripheral ========== */ +#define AT91C_CAN_MB6_MFID ( 0xFFFD02CC ) /* (CAN_MB6) MailBox Family ID Register */ +#define AT91C_CAN_MB6_MID ( 0xFFFD02C8 ) /* (CAN_MB6) MailBox ID Register */ +#define AT91C_CAN_MB6_MAM ( 0xFFFD02C4 ) /* (CAN_MB6) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB6_MSR ( 0xFFFD02D0 ) /* (CAN_MB6) MailBox Status Register */ +#define AT91C_CAN_MB6_MDL ( 0xFFFD02D4 ) /* (CAN_MB6) MailBox Data Low Register */ +#define AT91C_CAN_MB6_MCR ( 0xFFFD02DC ) /* (CAN_MB6) MailBox Control Register */ +#define AT91C_CAN_MB6_MDH ( 0xFFFD02D8 ) /* (CAN_MB6) MailBox Data High Register */ +#define AT91C_CAN_MB6_MMR ( 0xFFFD02C0 ) /* (CAN_MB6) MailBox Mode Register */ +/* ========== Register definition for CAN_MB7 peripheral ========== */ +#define AT91C_CAN_MB7_MCR ( 0xFFFD02FC ) /* (CAN_MB7) MailBox Control Register */ +#define AT91C_CAN_MB7_MDH ( 0xFFFD02F8 ) /* (CAN_MB7) MailBox Data High Register */ +#define AT91C_CAN_MB7_MFID ( 0xFFFD02EC ) /* (CAN_MB7) MailBox Family ID Register */ +#define AT91C_CAN_MB7_MDL ( 0xFFFD02F4 ) /* (CAN_MB7) MailBox Data Low Register */ +#define AT91C_CAN_MB7_MID ( 0xFFFD02E8 ) /* (CAN_MB7) MailBox ID Register */ +#define AT91C_CAN_MB7_MMR ( 0xFFFD02E0 ) /* (CAN_MB7) MailBox Mode Register */ +#define AT91C_CAN_MB7_MAM ( 0xFFFD02E4 ) /* (CAN_MB7) MailBox Acceptance Mask Register */ +#define AT91C_CAN_MB7_MSR ( 0xFFFD02F0 ) /* (CAN_MB7) MailBox Status Register */ +/* ========== Register definition for CAN peripheral ========== */ +#define AT91C_CAN_TCR ( 0xFFFD0024 ) /* (CAN) Transfer Command Register */ +#define AT91C_CAN_IMR ( 0xFFFD000C ) /* (CAN) Interrupt Mask Register */ +#define AT91C_CAN_IER ( 0xFFFD0004 ) /* (CAN) Interrupt Enable Register */ +#define AT91C_CAN_ECR ( 0xFFFD0020 ) /* (CAN) Error Counter Register */ +#define AT91C_CAN_TIMESTP ( 0xFFFD001C ) /* (CAN) Time Stamp Register */ +#define AT91C_CAN_MR ( 0xFFFD0000 ) /* (CAN) Mode Register */ +#define AT91C_CAN_IDR ( 0xFFFD0008 ) /* (CAN) Interrupt Disable Register */ +#define AT91C_CAN_ACR ( 0xFFFD0028 ) /* (CAN) Abort Command Register */ +#define AT91C_CAN_TIM ( 0xFFFD0018 ) /* (CAN) Timer Register */ +#define AT91C_CAN_SR ( 0xFFFD0010 ) /* (CAN) Status Register */ +#define AT91C_CAN_BR ( 0xFFFD0014 ) /* (CAN) Baudrate Register */ +#define AT91C_CAN_VR ( 0xFFFD00FC ) /* (CAN) Version Register */ +/* ========== Register definition for EMAC peripheral ========== */ +#define AT91C_EMAC_ISR ( 0xFFFDC024 ) /* (EMAC) Interrupt Status Register */ +#define AT91C_EMAC_SA4H ( 0xFFFDC0B4 ) /* (EMAC) Specific Address 4 Top, Last 2 bytes */ +#define AT91C_EMAC_SA1L ( 0xFFFDC098 ) /* (EMAC) Specific Address 1 Bottom, First 4 bytes */ +#define AT91C_EMAC_ELE ( 0xFFFDC078 ) /* (EMAC) Excessive Length Errors Register */ +#define AT91C_EMAC_LCOL ( 0xFFFDC05C ) /* (EMAC) Late Collision Register */ +#define AT91C_EMAC_RLE ( 0xFFFDC088 ) /* (EMAC) Receive Length Field Mismatch Register */ +#define AT91C_EMAC_WOL ( 0xFFFDC0C4 ) /* (EMAC) Wake On LAN Register */ +#define AT91C_EMAC_DTF ( 0xFFFDC058 ) /* (EMAC) Deferred Transmission Frame Register */ +#define AT91C_EMAC_TUND ( 0xFFFDC064 ) /* (EMAC) Transmit Underrun Error Register */ +#define AT91C_EMAC_NCR ( 0xFFFDC000 ) /* (EMAC) Network Control Register */ +#define AT91C_EMAC_SA4L ( 0xFFFDC0B0 ) /* (EMAC) Specific Address 4 Bottom, First 4 bytes */ +#define AT91C_EMAC_RSR ( 0xFFFDC020 ) /* (EMAC) Receive Status Register */ +#define AT91C_EMAC_SA3L ( 0xFFFDC0A8 ) /* (EMAC) Specific Address 3 Bottom, First 4 bytes */ +#define AT91C_EMAC_TSR ( 0xFFFDC014 ) /* (EMAC) Transmit Status Register */ +#define AT91C_EMAC_IDR ( 0xFFFDC02C ) /* (EMAC) Interrupt Disable Register */ +#define AT91C_EMAC_RSE ( 0xFFFDC074 ) /* (EMAC) Receive Symbol Errors Register */ +#define AT91C_EMAC_ECOL ( 0xFFFDC060 ) /* (EMAC) Excessive Collision Register */ +#define AT91C_EMAC_TID ( 0xFFFDC0B8 ) /* (EMAC) Type ID Checking Register */ +#define AT91C_EMAC_HRB ( 0xFFFDC090 ) /* (EMAC) Hash Address Bottom[31:0] */ +#define AT91C_EMAC_TBQP ( 0xFFFDC01C ) /* (EMAC) Transmit Buffer Queue Pointer */ +#define AT91C_EMAC_USRIO ( 0xFFFDC0C0 ) /* (EMAC) USER Input/Output Register */ +#define AT91C_EMAC_PTR ( 0xFFFDC038 ) /* (EMAC) Pause Time Register */ +#define AT91C_EMAC_SA2H ( 0xFFFDC0A4 ) /* (EMAC) Specific Address 2 Top, Last 2 bytes */ +#define AT91C_EMAC_ROV ( 0xFFFDC070 ) /* (EMAC) Receive Overrun Errors Register */ +#define AT91C_EMAC_ALE ( 0xFFFDC054 ) /* (EMAC) Alignment Error Register */ +#define AT91C_EMAC_RJA ( 0xFFFDC07C ) /* (EMAC) Receive Jabbers Register */ +#define AT91C_EMAC_RBQP ( 0xFFFDC018 ) /* (EMAC) Receive Buffer Queue Pointer */ +#define AT91C_EMAC_TPF ( 0xFFFDC08C ) /* (EMAC) Transmitted Pause Frames Register */ +#define AT91C_EMAC_NCFGR ( 0xFFFDC004 ) /* (EMAC) Network Configuration Register */ +#define AT91C_EMAC_HRT ( 0xFFFDC094 ) /* (EMAC) Hash Address Top[63:32] */ +#define AT91C_EMAC_USF ( 0xFFFDC080 ) /* (EMAC) Undersize Frames Register */ +#define AT91C_EMAC_FCSE ( 0xFFFDC050 ) /* (EMAC) Frame Check Sequence Error Register */ +#define AT91C_EMAC_TPQ ( 0xFFFDC0BC ) /* (EMAC) Transmit Pause Quantum Register */ +#define AT91C_EMAC_MAN ( 0xFFFDC034 ) /* (EMAC) PHY Maintenance Register */ +#define AT91C_EMAC_FTO ( 0xFFFDC040 ) /* (EMAC) Frames Transmitted OK Register */ +#define AT91C_EMAC_REV ( 0xFFFDC0FC ) /* (EMAC) Revision Register */ +#define AT91C_EMAC_IMR ( 0xFFFDC030 ) /* (EMAC) Interrupt Mask Register */ +#define AT91C_EMAC_SCF ( 0xFFFDC044 ) /* (EMAC) Single Collision Frame Register */ +#define AT91C_EMAC_PFR ( 0xFFFDC03C ) /* (EMAC) Pause Frames received Register */ +#define AT91C_EMAC_MCF ( 0xFFFDC048 ) /* (EMAC) Multiple Collision Frame Register */ +#define AT91C_EMAC_NSR ( 0xFFFDC008 ) /* (EMAC) Network Status Register */ +#define AT91C_EMAC_SA2L ( 0xFFFDC0A0 ) /* (EMAC) Specific Address 2 Bottom, First 4 bytes */ +#define AT91C_EMAC_FRO ( 0xFFFDC04C ) /* (EMAC) Frames Received OK Register */ +#define AT91C_EMAC_IER ( 0xFFFDC028 ) /* (EMAC) Interrupt Enable Register */ +#define AT91C_EMAC_SA1H ( 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */ +#define AT91C_EMAC_CSE ( 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */ +#define AT91C_EMAC_SA3H ( 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */ +#define AT91C_EMAC_RRE ( 0xFFFDC06C ) /* (EMAC) Receive Resource Error Register */ +#define AT91C_EMAC_STE ( 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */ +/* ========== Register definition for PDC_ADC peripheral ========== */ +#define AT91C_ADC_PTSR ( 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */ +#define AT91C_ADC_PTCR ( 0xFFFD8120 ) /* (PDC_ADC) PDC Transfer Control Register */ +#define AT91C_ADC_TNPR ( 0xFFFD8118 ) /* (PDC_ADC) Transmit Next Pointer Register */ +#define AT91C_ADC_TNCR ( 0xFFFD811C ) /* (PDC_ADC) Transmit Next Counter Register */ +#define AT91C_ADC_RNPR ( 0xFFFD8110 ) /* (PDC_ADC) Receive Next Pointer Register */ +#define AT91C_ADC_RNCR ( 0xFFFD8114 ) /* (PDC_ADC) Receive Next Counter Register */ +#define AT91C_ADC_RPR ( 0xFFFD8100 ) /* (PDC_ADC) Receive Pointer Register */ +#define AT91C_ADC_TCR ( 0xFFFD810C ) /* (PDC_ADC) Transmit Counter Register */ +#define AT91C_ADC_TPR ( 0xFFFD8108 ) /* (PDC_ADC) Transmit Pointer Register */ +#define AT91C_ADC_RCR ( 0xFFFD8104 ) /* (PDC_ADC) Receive Counter Register */ +/* ========== Register definition for ADC peripheral ========== */ +#define AT91C_ADC_CDR2 ( 0xFFFD8038 ) /* (ADC) ADC Channel Data Register 2 */ +#define AT91C_ADC_CDR3 ( 0xFFFD803C ) /* (ADC) ADC Channel Data Register 3 */ +#define AT91C_ADC_CDR0 ( 0xFFFD8030 ) /* (ADC) ADC Channel Data Register 0 */ +#define AT91C_ADC_CDR5 ( 0xFFFD8044 ) /* (ADC) ADC Channel Data Register 5 */ +#define AT91C_ADC_CHDR ( 0xFFFD8014 ) /* (ADC) ADC Channel Disable Register */ +#define AT91C_ADC_SR ( 0xFFFD801C ) /* (ADC) ADC Status Register */ +#define AT91C_ADC_CDR4 ( 0xFFFD8040 ) /* (ADC) ADC Channel Data Register 4 */ +#define AT91C_ADC_CDR1 ( 0xFFFD8034 ) /* (ADC) ADC Channel Data Register 1 */ +#define AT91C_ADC_LCDR ( 0xFFFD8020 ) /* (ADC) ADC Last Converted Data Register */ +#define AT91C_ADC_IDR ( 0xFFFD8028 ) /* (ADC) ADC Interrupt Disable Register */ +#define AT91C_ADC_CR ( 0xFFFD8000 ) /* (ADC) ADC Control Register */ +#define AT91C_ADC_CDR7 ( 0xFFFD804C ) /* (ADC) ADC Channel Data Register 7 */ +#define AT91C_ADC_CDR6 ( 0xFFFD8048 ) /* (ADC) ADC Channel Data Register 6 */ +#define AT91C_ADC_IER ( 0xFFFD8024 ) /* (ADC) ADC Interrupt Enable Register */ +#define AT91C_ADC_CHER ( 0xFFFD8010 ) /* (ADC) ADC Channel Enable Register */ +#define AT91C_ADC_CHSR ( 0xFFFD8018 ) /* (ADC) ADC Channel Status Register */ +#define AT91C_ADC_MR ( 0xFFFD8004 ) /* (ADC) ADC Mode Register */ +#define AT91C_ADC_IMR ( 0xFFFD802C ) /* (ADC) ADC Interrupt Mask Register */ +/* ========== Register definition for PDC_AES peripheral ========== */ +#define AT91C_AES_TPR ( 0xFFFA4108 ) /* (PDC_AES) Transmit Pointer Register */ +#define AT91C_AES_PTCR ( 0xFFFA4120 ) /* (PDC_AES) PDC Transfer Control Register */ +#define AT91C_AES_RNPR ( 0xFFFA4110 ) /* (PDC_AES) Receive Next Pointer Register */ +#define AT91C_AES_TNCR ( 0xFFFA411C ) /* (PDC_AES) Transmit Next Counter Register */ +#define AT91C_AES_TCR ( 0xFFFA410C ) /* (PDC_AES) Transmit Counter Register */ +#define AT91C_AES_RCR ( 0xFFFA4104 ) /* (PDC_AES) Receive Counter Register */ +#define AT91C_AES_RNCR ( 0xFFFA4114 ) /* (PDC_AES) Receive Next Counter Register */ +#define AT91C_AES_TNPR ( 0xFFFA4118 ) /* (PDC_AES) Transmit Next Pointer Register */ +#define AT91C_AES_RPR ( 0xFFFA4100 ) /* (PDC_AES) Receive Pointer Register */ +#define AT91C_AES_PTSR ( 0xFFFA4124 ) /* (PDC_AES) PDC Transfer Status Register */ +/* ========== Register definition for AES peripheral ========== */ +#define AT91C_AES_IVxR ( 0xFFFA4060 ) /* (AES) Initialization Vector x Register */ +#define AT91C_AES_MR ( 0xFFFA4004 ) /* (AES) Mode Register */ +#define AT91C_AES_VR ( 0xFFFA40FC ) /* (AES) AES Version Register */ +#define AT91C_AES_ODATAxR ( 0xFFFA4050 ) /* (AES) Output Data x Register */ +#define AT91C_AES_IDATAxR ( 0xFFFA4040 ) /* (AES) Input Data x Register */ +#define AT91C_AES_CR ( 0xFFFA4000 ) /* (AES) Control Register */ +#define AT91C_AES_IDR ( 0xFFFA4014 ) /* (AES) Interrupt Disable Register */ +#define AT91C_AES_IMR ( 0xFFFA4018 ) /* (AES) Interrupt Mask Register */ +#define AT91C_AES_IER ( 0xFFFA4010 ) /* (AES) Interrupt Enable Register */ +#define AT91C_AES_KEYWxR ( 0xFFFA4020 ) /* (AES) Key Word x Register */ +#define AT91C_AES_ISR ( 0xFFFA401C ) /* (AES) Interrupt Status Register */ +/* ========== Register definition for PDC_TDES peripheral ========== */ +#define AT91C_TDES_RNCR ( 0xFFFA8114 ) /* (PDC_TDES) Receive Next Counter Register */ +#define AT91C_TDES_TCR ( 0xFFFA810C ) /* (PDC_TDES) Transmit Counter Register */ +#define AT91C_TDES_RCR ( 0xFFFA8104 ) /* (PDC_TDES) Receive Counter Register */ +#define AT91C_TDES_TNPR ( 0xFFFA8118 ) /* (PDC_TDES) Transmit Next Pointer Register */ +#define AT91C_TDES_RNPR ( 0xFFFA8110 ) /* (PDC_TDES) Receive Next Pointer Register */ +#define AT91C_TDES_RPR ( 0xFFFA8100 ) /* (PDC_TDES) Receive Pointer Register */ +#define AT91C_TDES_TNCR ( 0xFFFA811C ) /* (PDC_TDES) Transmit Next Counter Register */ +#define AT91C_TDES_TPR ( 0xFFFA8108 ) /* (PDC_TDES) Transmit Pointer Register */ +#define AT91C_TDES_PTSR ( 0xFFFA8124 ) /* (PDC_TDES) PDC Transfer Status Register */ +#define AT91C_TDES_PTCR ( 0xFFFA8120 ) /* (PDC_TDES) PDC Transfer Control Register */ +/* ========== Register definition for TDES peripheral ========== */ +#define AT91C_TDES_KEY2WxR ( 0xFFFA8028 ) /* (TDES) Key 2 Word x Register */ +#define AT91C_TDES_KEY3WxR ( 0xFFFA8030 ) /* (TDES) Key 3 Word x Register */ +#define AT91C_TDES_IDR ( 0xFFFA8014 ) /* (TDES) Interrupt Disable Register */ +#define AT91C_TDES_VR ( 0xFFFA80FC ) /* (TDES) TDES Version Register */ +#define AT91C_TDES_IVxR ( 0xFFFA8060 ) /* (TDES) Initialization Vector x Register */ +#define AT91C_TDES_ODATAxR ( 0xFFFA8050 ) /* (TDES) Output Data x Register */ +#define AT91C_TDES_IMR ( 0xFFFA8018 ) /* (TDES) Interrupt Mask Register */ +#define AT91C_TDES_MR ( 0xFFFA8004 ) /* (TDES) Mode Register */ +#define AT91C_TDES_CR ( 0xFFFA8000 ) /* (TDES) Control Register */ +#define AT91C_TDES_IER ( 0xFFFA8010 ) /* (TDES) Interrupt Enable Register */ +#define AT91C_TDES_ISR ( 0xFFFA801C ) /* (TDES) Interrupt Status Register */ +#define AT91C_TDES_IDATAxR ( 0xFFFA8040 ) /* (TDES) Input Data x Register */ +#define AT91C_TDES_KEY1WxR ( 0xFFFA8020 ) /* (TDES) Key 1 Word x Register */ + +/* ***************************************************************************** */ +/* PIO DEFINITIONS FOR AT91SAM7X256 */ +/* ***************************************************************************** */ +#define AT91C_PIO_PA0 ( 1 << 0 ) /* Pin Controlled by PA0 */ +#define AT91C_PA0_RXD0 ( AT91C_PIO_PA0 ) /* USART 0 Receive Data */ +#define AT91C_PIO_PA1 ( 1 << 1 ) /* Pin Controlled by PA1 */ +#define AT91C_PA1_TXD0 ( AT91C_PIO_PA1 ) /* USART 0 Transmit Data */ +#define AT91C_PIO_PA10 ( 1 << 10 ) /* Pin Controlled by PA10 */ +#define AT91C_PA10_TWD ( AT91C_PIO_PA10 ) /* TWI Two-wire Serial Data */ +#define AT91C_PIO_PA11 ( 1 << 11 ) /* Pin Controlled by PA11 */ +#define AT91C_PA11_TWCK ( AT91C_PIO_PA11 ) /* TWI Two-wire Serial Clock */ +#define AT91C_PIO_PA12 ( 1 << 12 ) /* Pin Controlled by PA12 */ +#define AT91C_PA12_NPCS00 ( AT91C_PIO_PA12 ) /* SPI 0 Peripheral Chip Select 0 */ +#define AT91C_PIO_PA13 ( 1 << 13 ) /* Pin Controlled by PA13 */ +#define AT91C_PA13_NPCS01 ( AT91C_PIO_PA13 ) /* SPI 0 Peripheral Chip Select 1 */ +#define AT91C_PA13_PCK1 ( AT91C_PIO_PA13 ) /* PMC Programmable Clock Output 1 */ +#define AT91C_PIO_PA14 ( 1 << 14 ) /* Pin Controlled by PA14 */ +#define AT91C_PA14_NPCS02 ( AT91C_PIO_PA14 ) /* SPI 0 Peripheral Chip Select 2 */ +#define AT91C_PA14_IRQ1 ( AT91C_PIO_PA14 ) /* External Interrupt 1 */ +#define AT91C_PIO_PA15 ( 1 << 15 ) /* Pin Controlled by PA15 */ +#define AT91C_PA15_NPCS03 ( AT91C_PIO_PA15 ) /* SPI 0 Peripheral Chip Select 3 */ +#define AT91C_PA15_TCLK2 ( AT91C_PIO_PA15 ) /* Timer Counter 2 external clock input */ +#define AT91C_PIO_PA16 ( 1 << 16 ) /* Pin Controlled by PA16 */ +#define AT91C_PA16_MISO0 ( AT91C_PIO_PA16 ) /* SPI 0 Master In Slave */ +#define AT91C_PIO_PA17 ( 1 << 17 ) /* Pin Controlled by PA17 */ +#define AT91C_PA17_MOSI0 ( AT91C_PIO_PA17 ) /* SPI 0 Master Out Slave */ +#define AT91C_PIO_PA18 ( 1 << 18 ) /* Pin Controlled by PA18 */ +#define AT91C_PA18_SPCK0 ( AT91C_PIO_PA18 ) /* SPI 0 Serial Clock */ +#define AT91C_PIO_PA19 ( 1 << 19 ) /* Pin Controlled by PA19 */ +#define AT91C_PA19_CANRX ( AT91C_PIO_PA19 ) /* CAN Receive */ +#define AT91C_PIO_PA2 ( 1 << 2 ) /* Pin Controlled by PA2 */ +#define AT91C_PA2_SCK0 ( AT91C_PIO_PA2 ) /* USART 0 Serial Clock */ +#define AT91C_PA2_NPCS11 ( AT91C_PIO_PA2 ) /* SPI 1 Peripheral Chip Select 1 */ +#define AT91C_PIO_PA20 ( 1 << 20 ) /* Pin Controlled by PA20 */ +#define AT91C_PA20_CANTX ( AT91C_PIO_PA20 ) /* CAN Transmit */ +#define AT91C_PIO_PA21 ( 1 << 21 ) /* Pin Controlled by PA21 */ +#define AT91C_PA21_TF ( AT91C_PIO_PA21 ) /* SSC Transmit Frame Sync */ +#define AT91C_PA21_NPCS10 ( AT91C_PIO_PA21 ) /* SPI 1 Peripheral Chip Select 0 */ +#define AT91C_PIO_PA22 ( 1 << 22 ) /* Pin Controlled by PA22 */ +#define AT91C_PA22_TK ( AT91C_PIO_PA22 ) /* SSC Transmit Clock */ +#define AT91C_PA22_SPCK1 ( AT91C_PIO_PA22 ) /* SPI 1 Serial Clock */ +#define AT91C_PIO_PA23 ( 1 << 23 ) /* Pin Controlled by PA23 */ +#define AT91C_PA23_TD ( AT91C_PIO_PA23 ) /* SSC Transmit data */ +#define AT91C_PA23_MOSI1 ( AT91C_PIO_PA23 ) /* SPI 1 Master Out Slave */ +#define AT91C_PIO_PA24 ( 1 << 24 ) /* Pin Controlled by PA24 */ +#define AT91C_PA24_RD ( AT91C_PIO_PA24 ) /* SSC Receive Data */ +#define AT91C_PA24_MISO1 ( AT91C_PIO_PA24 ) /* SPI 1 Master In Slave */ +#define AT91C_PIO_PA25 ( 1 << 25 ) /* Pin Controlled by PA25 */ +#define AT91C_PA25_RK ( AT91C_PIO_PA25 ) /* SSC Receive Clock */ +#define AT91C_PA25_NPCS11 ( AT91C_PIO_PA25 ) /* SPI 1 Peripheral Chip Select 1 */ +#define AT91C_PIO_PA26 ( 1 << 26 ) /* Pin Controlled by PA26 */ +#define AT91C_PA26_RF ( AT91C_PIO_PA26 ) /* SSC Receive Frame Sync */ +#define AT91C_PA26_NPCS12 ( AT91C_PIO_PA26 ) /* SPI 1 Peripheral Chip Select 2 */ +#define AT91C_PIO_PA27 ( 1 << 27 ) /* Pin Controlled by PA27 */ +#define AT91C_PA27_DRXD ( AT91C_PIO_PA27 ) /* DBGU Debug Receive Data */ +#define AT91C_PA27_PCK3 ( AT91C_PIO_PA27 ) /* PMC Programmable Clock Output 3 */ +#define AT91C_PIO_PA28 ( 1 << 28 ) /* Pin Controlled by PA28 */ +#define AT91C_PA28_DTXD ( AT91C_PIO_PA28 ) /* DBGU Debug Transmit Data */ +#define AT91C_PIO_PA29 ( 1 << 29 ) /* Pin Controlled by PA29 */ +#define AT91C_PA29_FIQ ( AT91C_PIO_PA29 ) /* AIC Fast Interrupt Input */ +#define AT91C_PA29_NPCS13 ( AT91C_PIO_PA29 ) /* SPI 1 Peripheral Chip Select 3 */ +#define AT91C_PIO_PA3 ( 1 << 3 ) /* Pin Controlled by PA3 */ +#define AT91C_PA3_RTS0 ( AT91C_PIO_PA3 ) /* USART 0 Ready To Send */ +#define AT91C_PA3_NPCS12 ( AT91C_PIO_PA3 ) /* SPI 1 Peripheral Chip Select 2 */ +#define AT91C_PIO_PA30 ( 1 << 30 ) /* Pin Controlled by PA30 */ +#define AT91C_PA30_IRQ0 ( AT91C_PIO_PA30 ) /* External Interrupt 0 */ +#define AT91C_PA30_PCK2 ( AT91C_PIO_PA30 ) /* PMC Programmable Clock Output 2 */ +#define AT91C_PIO_PA4 ( 1 << 4 ) /* Pin Controlled by PA4 */ +#define AT91C_PA4_CTS0 ( AT91C_PIO_PA4 ) /* USART 0 Clear To Send */ +#define AT91C_PA4_NPCS13 ( AT91C_PIO_PA4 ) /* SPI 1 Peripheral Chip Select 3 */ +#define AT91C_PIO_PA5 ( 1 << 5 ) /* Pin Controlled by PA5 */ +#define AT91C_PA5_RXD1 ( AT91C_PIO_PA5 ) /* USART 1 Receive Data */ +#define AT91C_PIO_PA6 ( 1 << 6 ) /* Pin Controlled by PA6 */ +#define AT91C_PA6_TXD1 ( AT91C_PIO_PA6 ) /* USART 1 Transmit Data */ +#define AT91C_PIO_PA7 ( 1 << 7 ) /* Pin Controlled by PA7 */ +#define AT91C_PA7_SCK1 ( AT91C_PIO_PA7 ) /* USART 1 Serial Clock */ +#define AT91C_PA7_NPCS01 ( AT91C_PIO_PA7 ) /* SPI 0 Peripheral Chip Select 1 */ +#define AT91C_PIO_PA8 ( 1 << 8 ) /* Pin Controlled by PA8 */ +#define AT91C_PA8_RTS1 ( AT91C_PIO_PA8 ) /* USART 1 Ready To Send */ +#define AT91C_PA8_NPCS02 ( AT91C_PIO_PA8 ) /* SPI 0 Peripheral Chip Select 2 */ +#define AT91C_PIO_PA9 ( 1 << 9 ) /* Pin Controlled by PA9 */ +#define AT91C_PA9_CTS1 ( AT91C_PIO_PA9 ) /* USART 1 Clear To Send */ +#define AT91C_PA9_NPCS03 ( AT91C_PIO_PA9 ) /* SPI 0 Peripheral Chip Select 3 */ +#define AT91C_PIO_PB0 ( 1 << 0 ) /* Pin Controlled by PB0 */ +#define AT91C_PB0_ETXCK_EREFCK ( AT91C_PIO_PB0 ) /* Ethernet MAC Transmit Clock/Reference Clock */ +#define AT91C_PB0_PCK0 ( AT91C_PIO_PB0 ) /* PMC Programmable Clock Output 0 */ +#define AT91C_PIO_PB1 ( 1 << 1 ) /* Pin Controlled by PB1 */ +#define AT91C_PB1_ETXEN ( AT91C_PIO_PB1 ) /* Ethernet MAC Transmit Enable */ +#define AT91C_PIO_PB10 ( 1 << 10 ) /* Pin Controlled by PB10 */ +#define AT91C_PB10_ETX2 ( AT91C_PIO_PB10 ) /* Ethernet MAC Transmit Data 2 */ +#define AT91C_PB10_NPCS11 ( AT91C_PIO_PB10 ) /* SPI 1 Peripheral Chip Select 1 */ +#define AT91C_PIO_PB11 ( 1 << 11 ) /* Pin Controlled by PB11 */ +#define AT91C_PB11_ETX3 ( AT91C_PIO_PB11 ) /* Ethernet MAC Transmit Data 3 */ +#define AT91C_PB11_NPCS12 ( AT91C_PIO_PB11 ) /* SPI 1 Peripheral Chip Select 2 */ +#define AT91C_PIO_PB12 ( 1 << 12 ) /* Pin Controlled by PB12 */ +#define AT91C_PB12_ETXER ( AT91C_PIO_PB12 ) /* Ethernet MAC Transmit Coding Error */ +#define AT91C_PB12_TCLK0 ( AT91C_PIO_PB12 ) /* Timer Counter 0 external clock input */ +#define AT91C_PIO_PB13 ( 1 << 13 ) /* Pin Controlled by PB13 */ +#define AT91C_PB13_ERX2 ( AT91C_PIO_PB13 ) /* Ethernet MAC Receive Data 2 */ +#define AT91C_PB13_NPCS01 ( AT91C_PIO_PB13 ) /* SPI 0 Peripheral Chip Select 1 */ +#define AT91C_PIO_PB14 ( 1 << 14 ) /* Pin Controlled by PB14 */ +#define AT91C_PB14_ERX3 ( AT91C_PIO_PB14 ) /* Ethernet MAC Receive Data 3 */ +#define AT91C_PB14_NPCS02 ( AT91C_PIO_PB14 ) /* SPI 0 Peripheral Chip Select 2 */ +#define AT91C_PIO_PB15 ( 1 << 15 ) /* Pin Controlled by PB15 */ +#define AT91C_PB15_ERXDV ( AT91C_PIO_PB15 ) /* Ethernet MAC Receive Data Valid */ +#define AT91C_PIO_PB16 ( 1 << 16 ) /* Pin Controlled by PB16 */ +#define AT91C_PB16_ECOL ( AT91C_PIO_PB16 ) /* Ethernet MAC Collision Detected */ +#define AT91C_PB16_NPCS13 ( AT91C_PIO_PB16 ) /* SPI 1 Peripheral Chip Select 3 */ +#define AT91C_PIO_PB17 ( 1 << 17 ) /* Pin Controlled by PB17 */ +#define AT91C_PB17_ERXCK ( AT91C_PIO_PB17 ) /* Ethernet MAC Receive Clock */ +#define AT91C_PB17_NPCS03 ( AT91C_PIO_PB17 ) /* SPI 0 Peripheral Chip Select 3 */ +#define AT91C_PIO_PB18 ( 1 << 18 ) /* Pin Controlled by PB18 */ +#define AT91C_PB18_EF100 ( AT91C_PIO_PB18 ) /* Ethernet MAC Force 100 Mbits/sec */ +#define AT91C_PB18_ADTRG ( AT91C_PIO_PB18 ) /* ADC External Trigger */ +#define AT91C_PIO_PB19 ( 1 << 19 ) /* Pin Controlled by PB19 */ +#define AT91C_PB19_PWM0 ( AT91C_PIO_PB19 ) /* PWM Channel 0 */ +#define AT91C_PB19_TCLK1 ( AT91C_PIO_PB19 ) /* Timer Counter 1 external clock input */ +#define AT91C_PIO_PB2 ( 1 << 2 ) /* Pin Controlled by PB2 */ +#define AT91C_PB2_ETX0 ( AT91C_PIO_PB2 ) /* Ethernet MAC Transmit Data 0 */ +#define AT91C_PIO_PB20 ( 1 << 20 ) /* Pin Controlled by PB20 */ +#define AT91C_PB20_PWM1 ( AT91C_PIO_PB20 ) /* PWM Channel 1 */ +#define AT91C_PB20_PCK0 ( AT91C_PIO_PB20 ) /* PMC Programmable Clock Output 0 */ +#define AT91C_PIO_PB21 ( 1 << 21 ) /* Pin Controlled by PB21 */ +#define AT91C_PB21_PWM2 ( AT91C_PIO_PB21 ) /* PWM Channel 2 */ +#define AT91C_PB21_PCK1 ( AT91C_PIO_PB21 ) /* PMC Programmable Clock Output 1 */ +#define AT91C_PIO_PB22 ( 1 << 22 ) /* Pin Controlled by PB22 */ +#define AT91C_PB22_PWM3 ( AT91C_PIO_PB22 ) /* PWM Channel 3 */ +#define AT91C_PB22_PCK2 ( AT91C_PIO_PB22 ) /* PMC Programmable Clock Output 2 */ +#define AT91C_PIO_PB23 ( 1 << 23 ) /* Pin Controlled by PB23 */ +#define AT91C_PB23_TIOA0 ( AT91C_PIO_PB23 ) /* Timer Counter 0 Multipurpose Timer I/O Pin A */ +#define AT91C_PB23_DCD1 ( AT91C_PIO_PB23 ) /* USART 1 Data Carrier Detect */ +#define AT91C_PIO_PB24 ( 1 << 24 ) /* Pin Controlled by PB24 */ +#define AT91C_PB24_TIOB0 ( AT91C_PIO_PB24 ) /* Timer Counter 0 Multipurpose Timer I/O Pin B */ +#define AT91C_PB24_DSR1 ( AT91C_PIO_PB24 ) /* USART 1 Data Set ready */ +#define AT91C_PIO_PB25 ( 1 << 25 ) /* Pin Controlled by PB25 */ +#define AT91C_PB25_TIOA1 ( AT91C_PIO_PB25 ) /* Timer Counter 1 Multipurpose Timer I/O Pin A */ +#define AT91C_PB25_DTR1 ( AT91C_PIO_PB25 ) /* USART 1 Data Terminal ready */ +#define AT91C_PIO_PB26 ( 1 << 26 ) /* Pin Controlled by PB26 */ +#define AT91C_PB26_TIOB1 ( AT91C_PIO_PB26 ) /* Timer Counter 1 Multipurpose Timer I/O Pin B */ +#define AT91C_PB26_RI1 ( AT91C_PIO_PB26 ) /* USART 1 Ring Indicator */ +#define AT91C_PIO_PB27 ( 1 << 27 ) /* Pin Controlled by PB27 */ +#define AT91C_PB27_TIOA2 ( AT91C_PIO_PB27 ) /* Timer Counter 2 Multipurpose Timer I/O Pin A */ +#define AT91C_PB27_PWM0 ( AT91C_PIO_PB27 ) /* PWM Channel 0 */ +#define AT91C_PIO_PB28 ( 1 << 28 ) /* Pin Controlled by PB28 */ +#define AT91C_PB28_TIOB2 ( AT91C_PIO_PB28 ) /* Timer Counter 2 Multipurpose Timer I/O Pin B */ +#define AT91C_PB28_PWM1 ( AT91C_PIO_PB28 ) /* PWM Channel 1 */ +#define AT91C_PIO_PB29 ( 1 << 29 ) /* Pin Controlled by PB29 */ +#define AT91C_PB29_PCK1 ( AT91C_PIO_PB29 ) /* PMC Programmable Clock Output 1 */ +#define AT91C_PB29_PWM2 ( AT91C_PIO_PB29 ) /* PWM Channel 2 */ +#define AT91C_PIO_PB3 ( 1 << 3 ) /* Pin Controlled by PB3 */ +#define AT91C_PB3_ETX1 ( AT91C_PIO_PB3 ) /* Ethernet MAC Transmit Data 1 */ +#define AT91C_PIO_PB30 ( 1 << 30 ) /* Pin Controlled by PB30 */ +#define AT91C_PB30_PCK2 ( AT91C_PIO_PB30 ) /* PMC Programmable Clock Output 2 */ +#define AT91C_PB30_PWM3 ( AT91C_PIO_PB30 ) /* PWM Channel 3 */ +#define AT91C_PIO_PB4 ( 1 << 4 ) /* Pin Controlled by PB4 */ +#define AT91C_PB4_ECRS_ECRSDV ( AT91C_PIO_PB4 ) /* Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */ +#define AT91C_PIO_PB5 ( 1 << 5 ) /* Pin Controlled by PB5 */ +#define AT91C_PB5_ERX0 ( AT91C_PIO_PB5 ) /* Ethernet MAC Receive Data 0 */ +#define AT91C_PIO_PB6 ( 1 << 6 ) /* Pin Controlled by PB6 */ +#define AT91C_PB6_ERX1 ( AT91C_PIO_PB6 ) /* Ethernet MAC Receive Data 1 */ +#define AT91C_PIO_PB7 ( 1 << 7 ) /* Pin Controlled by PB7 */ +#define AT91C_PB7_ERXER ( AT91C_PIO_PB7 ) /* Ethernet MAC Receive Error */ +#define AT91C_PIO_PB8 ( 1 << 8 ) /* Pin Controlled by PB8 */ +#define AT91C_PB8_EMDC ( AT91C_PIO_PB8 ) /* Ethernet MAC Management Data Clock */ +#define AT91C_PIO_PB9 ( 1 << 9 ) /* Pin Controlled by PB9 */ +#define AT91C_PB9_EMDIO ( AT91C_PIO_PB9 ) /* Ethernet MAC Management Data Input/Output */ + +/* ***************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 */ +/* ***************************************************************************** */ +#define AT91C_ID_FIQ ( 0 ) /* Advanced Interrupt Controller (FIQ) */ +#define AT91C_ID_SYS ( 1 ) /* System Peripheral */ +#define AT91C_ID_PIOA ( 2 ) /* Parallel IO Controller A */ +#define AT91C_ID_PIOB ( 3 ) /* Parallel IO Controller B */ +#define AT91C_ID_SPI0 ( 4 ) /* Serial Peripheral Interface 0 */ +#define AT91C_ID_SPI1 ( 5 ) /* Serial Peripheral Interface 1 */ +#define AT91C_ID_US0 ( 6 ) /* USART 0 */ +#define AT91C_ID_US1 ( 7 ) /* USART 1 */ +#define AT91C_ID_SSC ( 8 ) /* Serial Synchronous Controller */ +#define AT91C_ID_TWI ( 9 ) /* Two-Wire Interface */ +#define AT91C_ID_PWMC ( 10 ) /* PWM Controller */ +#define AT91C_ID_UDP ( 11 ) /* USB Device Port */ +#define AT91C_ID_TC0 ( 12 ) /* Timer Counter 0 */ +#define AT91C_ID_TC1 ( 13 ) /* Timer Counter 1 */ +#define AT91C_ID_TC2 ( 14 ) /* Timer Counter 2 */ +#define AT91C_ID_CAN ( 15 ) /* Control Area Network Controller */ +#define AT91C_ID_EMAC ( 16 ) /* Ethernet MAC */ +#define AT91C_ID_ADC ( 17 ) /* Analog-to-Digital Converter */ +#define AT91C_ID_AES ( 18 ) /* Advanced Encryption Standard 128-bit */ +#define AT91C_ID_TDES ( 19 ) /* Triple Data Encryption Standard */ +#define AT91C_ID_20_Reserved ( 20 ) /* Reserved */ +#define AT91C_ID_21_Reserved ( 21 ) /* Reserved */ +#define AT91C_ID_22_Reserved ( 22 ) /* Reserved */ +#define AT91C_ID_23_Reserved ( 23 ) /* Reserved */ +#define AT91C_ID_24_Reserved ( 24 ) /* Reserved */ +#define AT91C_ID_25_Reserved ( 25 ) /* Reserved */ +#define AT91C_ID_26_Reserved ( 26 ) /* Reserved */ +#define AT91C_ID_27_Reserved ( 27 ) /* Reserved */ +#define AT91C_ID_28_Reserved ( 28 ) /* Reserved */ +#define AT91C_ID_29_Reserved ( 29 ) /* Reserved */ +#define AT91C_ID_IRQ0 ( 30 ) /* Advanced Interrupt Controller (IRQ0) */ +#define AT91C_ID_IRQ1 ( 31 ) /* Advanced Interrupt Controller (IRQ1) */ + +/* ***************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 */ +/* ***************************************************************************** */ +#define AT91C_BASE_SYS ( 0xFFFFF000 ) /* (SYS) Base Address */ +#define AT91C_BASE_AIC ( 0xFFFFF000 ) /* (AIC) Base Address */ +#define AT91C_BASE_PDC_DBGU ( 0xFFFFF300 ) /* (PDC_DBGU) Base Address */ +#define AT91C_BASE_DBGU ( 0xFFFFF200 ) /* (DBGU) Base Address */ +#define AT91C_BASE_PIOA ( 0xFFFFF400 ) /* (PIOA) Base Address */ +#define AT91C_BASE_PIOB ( 0xFFFFF600 ) /* (PIOB) Base Address */ +#define AT91C_BASE_CKGR ( 0xFFFFFC20 ) /* (CKGR) Base Address */ +#define AT91C_BASE_PMC ( 0xFFFFFC00 ) /* (PMC) Base Address */ +#define AT91C_BASE_RSTC ( 0xFFFFFD00 ) /* (RSTC) Base Address */ +#define AT91C_BASE_RTTC ( 0xFFFFFD20 ) /* (RTTC) Base Address */ +#define AT91C_BASE_PITC ( 0xFFFFFD30 ) /* (PITC) Base Address */ +#define AT91C_BASE_WDTC ( 0xFFFFFD40 ) /* (WDTC) Base Address */ +#define AT91C_BASE_VREG ( 0xFFFFFD60 ) /* (VREG) Base Address */ +#define AT91C_BASE_MC ( 0xFFFFFF00 ) /* (MC) Base Address */ +#define AT91C_BASE_PDC_SPI1 ( 0xFFFE4100 ) /* (PDC_SPI1) Base Address */ +#define AT91C_BASE_SPI1 ( 0xFFFE4000 ) /* (SPI1) Base Address */ +#define AT91C_BASE_PDC_SPI0 ( 0xFFFE0100 ) /* (PDC_SPI0) Base Address */ +#define AT91C_BASE_SPI0 ( 0xFFFE0000 ) /* (SPI0) Base Address */ +#define AT91C_BASE_PDC_US1 ( 0xFFFC4100 ) /* (PDC_US1) Base Address */ +#define AT91C_BASE_US1 ( 0xFFFC4000 ) /* (US1) Base Address */ +#define AT91C_BASE_PDC_US0 ( 0xFFFC0100 ) /* (PDC_US0) Base Address */ +#define AT91C_BASE_US0 ( 0xFFFC0000 ) /* (US0) Base Address */ +#define AT91C_BASE_PDC_SSC ( 0xFFFD4100 ) /* (PDC_SSC) Base Address */ +#define AT91C_BASE_SSC ( 0xFFFD4000 ) /* (SSC) Base Address */ +#define AT91C_BASE_TWI ( 0xFFFB8000 ) /* (TWI) Base Address */ +#define AT91C_BASE_PWMC_CH3 ( 0xFFFCC260 ) /* (PWMC_CH3) Base Address */ +#define AT91C_BASE_PWMC_CH2 ( 0xFFFCC240 ) /* (PWMC_CH2) Base Address */ +#define AT91C_BASE_PWMC_CH1 ( 0xFFFCC220 ) /* (PWMC_CH1) Base Address */ +#define AT91C_BASE_PWMC_CH0 ( 0xFFFCC200 ) /* (PWMC_CH0) Base Address */ +#define AT91C_BASE_PWMC ( 0xFFFCC000 ) /* (PWMC) Base Address */ +#define AT91C_BASE_UDP ( 0xFFFB0000 ) /* (UDP) Base Address */ +#define AT91C_BASE_TC0 ( 0xFFFA0000 ) /* (TC0) Base Address */ +#define AT91C_BASE_TC1 ( 0xFFFA0040 ) /* (TC1) Base Address */ +#define AT91C_BASE_TC2 ( 0xFFFA0080 ) /* (TC2) Base Address */ +#define AT91C_BASE_TCB ( 0xFFFA0000 ) /* (TCB) Base Address */ +#define AT91C_BASE_CAN_MB0 ( 0xFFFD0200 ) /* (CAN_MB0) Base Address */ +#define AT91C_BASE_CAN_MB1 ( 0xFFFD0220 ) /* (CAN_MB1) Base Address */ +#define AT91C_BASE_CAN_MB2 ( 0xFFFD0240 ) /* (CAN_MB2) Base Address */ +#define AT91C_BASE_CAN_MB3 ( 0xFFFD0260 ) /* (CAN_MB3) Base Address */ +#define AT91C_BASE_CAN_MB4 ( 0xFFFD0280 ) /* (CAN_MB4) Base Address */ +#define AT91C_BASE_CAN_MB5 ( 0xFFFD02A0 ) /* (CAN_MB5) Base Address */ +#define AT91C_BASE_CAN_MB6 ( 0xFFFD02C0 ) /* (CAN_MB6) Base Address */ +#define AT91C_BASE_CAN_MB7 ( 0xFFFD02E0 ) /* (CAN_MB7) Base Address */ +#define AT91C_BASE_CAN ( 0xFFFD0000 ) /* (CAN) Base Address */ +#define AT91C_BASE_EMAC ( 0xFFFDC000 ) /* (EMAC) Base Address */ +#define AT91C_BASE_PDC_ADC ( 0xFFFD8100 ) /* (PDC_ADC) Base Address */ +#define AT91C_BASE_ADC ( 0xFFFD8000 ) /* (ADC) Base Address */ +#define AT91C_BASE_PDC_AES ( 0xFFFA4100 ) /* (PDC_AES) Base Address */ +#define AT91C_BASE_AES ( 0xFFFA4000 ) /* (AES) Base Address */ +#define AT91C_BASE_PDC_TDES ( 0xFFFA8100 ) /* (PDC_TDES) Base Address */ +#define AT91C_BASE_TDES ( 0xFFFA8000 ) /* (TDES) Base Address */ + +/* ***************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 */ +/* ***************************************************************************** */ +#define AT91C_ISRAM ( 0x00200000 ) /* Internal SRAM base address */ +#define AT91C_ISRAM_SIZE ( 0x00010000 ) /* Internal SRAM size in byte (64 Kbyte) */ +#define AT91C_IFLASH ( 0x00100000 ) /* Internal ROM base address */ +#define AT91C_IFLASH_SIZE ( 0x00040000 ) /* Internal ROM size in byte (256 Kbyte) */ diff --git a/portable/IAR/AtmelSAM7S64/ISR_Support.h b/portable/IAR/AtmelSAM7S64/ISR_Support.h new file mode 100644 index 000000000..273e95141 --- /dev/null +++ b/portable/IAR/AtmelSAM7S64/ISR_Support.h @@ -0,0 +1,151 @@ +; /* + * ; * FreeRTOS Kernel + * ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * ; * + * ; * SPDX-License-Identifier: MIT + * ; * + * ; * Permission is hereby granted, free of charge, to any person obtaining a copy of + * ; * this software and associated documentation files (the "Software"), to deal in + * ; * the Software without restriction, including without limitation the rights to + * ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * ; * the Software, and to permit persons to whom the Software is furnished to do so, + * ; * subject to the following conditions: + * ; * + * ; * The above copyright notice and this permission notice shall be included in all + * ; * copies or substantial portions of the Software. + * ; * + * ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * ; * + * ; * https://www.FreeRTOS.org + * ; * https://github.com/FreeRTOS + * ; * + * ; */ + +EXTERN pxCurrentTCB +EXTERN ulCriticalNesting + +; +Context save and restore macro definitions +; + +portSAVE_CONTEXT MACRO + +; +Push R0 as we are going to use the register. + STMDB SP !, { + R0 +} + +Set R0 to point to the task stack pointer. + STMDB SP, { + SP +} +^ +NOP +SUB SP, SP, # 4 +LDMIA SP !, { + R0 +} + +; +Push the return address onto the stack. + STMDB R0 !, { + LR + } + + Now we have saved LR we can use it instead of R0. + MOV LR, R0 + +; + +Pop R0 so we can save it onto the system mode stack. + LDMIA SP !, { + R0 +} + +Push all the system mode registers onto the task stack. + STMDB LR, { + R0 - LR +} +^ +NOP +SUB LR, LR, # 60 + +; +Push the SPSR onto the task stack. + MRS R0, SPSR +STMDB LR !, { + R0 +} + +LDR R0, = ulCriticalNesting + LDR R0, [ R0 ] +STMDB LR !, { + R0 +} + +Store the new top of stack + +for the task. + LDR R1, = pxCurrentTCB + LDR R0, [ R1 ] +STR LR, [ R0 ] + +ENDM + + +portRESTORE_CONTEXT MACRO + +; +Set the LR to the task stack. + LDR R1, = pxCurrentTCB + LDR R0, [ R1 ] +LDR LR, [ R0 ] + +; +The critical nesting depth is the first item on the stack. + ; +Load it into the ulCriticalNesting variable. + LDR R0, = ulCriticalNesting + LDMFD LR !, { + R1 +} + +STR R1, [ R0 ] + +; +Get the SPSR from the stack. + LDMFD LR !, { + R0 +} +MSR SPSR_cxsf, R0 + +; +Restore all system mode registers + +for the task. + LDMFD LR, { + R0 - R14 +} + +^ +NOP + +; +Restore the return address. + LDR LR, [ LR, # + 60 ] + +; + +And return -correcting the offset in the LR to obtain the +; + +correct address. + SUBS PC, LR, # 4 + +ENDM diff --git a/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h b/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h new file mode 100644 index 000000000..c53e6c8af --- /dev/null +++ b/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h @@ -0,0 +1,3113 @@ +/**---------------------------------------------------------------------------- */ +/** ATMEL Microcontroller Software Support - ROUSSET - */ +/**---------------------------------------------------------------------------- */ +/** The software is delivered "AS IS" without warranty or condition of any */ +/** kind, either express, implied or statutory. This includes without */ +/** limitation any warranty or condition with respect to merchantability or */ +/** fitness for any particular purpose, or against the infringements of */ +/** intellectual property rights of others. */ +/**---------------------------------------------------------------------------- */ +/** File Name : lib_AT91SAM7S64.h */ +/** Object : AT91SAM7S64 inlined functions */ +/** Generated : AT91 SW Application Group 07/16/2004 (07:43:09) */ +/** */ +/** CVS Reference : /lib_MC_SAM.h/1.3/Thu Mar 25 15:19:14 2004// */ +/** CVS Reference : /lib_pdc_1363d.h/1.2/Wed Feb 19 09:25:22 2003// */ +/** CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// */ +/** CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// */ +/** CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 13:23:52 2003// */ +/** CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// */ +/** CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// */ +/** CVS Reference : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004// */ +/** CVS Reference : /lib_adc.h/1.6/Fri Oct 17 08:12:38 2003// */ +/** CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// */ +/** CVS Reference : /lib_twi.h/1.2/Fri Jan 31 12:19:38 2003// */ +/** CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// */ +/** CVS Reference : /lib_udp.h/1.3/Fri Jan 31 12:19:48 2003// */ +/** CVS Reference : /lib_aic.h/1.3/Fri Jul 12 07:46:12 2002// */ +/**---------------------------------------------------------------------------- */ + +#ifndef lib_AT91SAM7S64_H +#define lib_AT91SAM7S64_H + +/* ***************************************************************************** +* SOFTWARE API FOR MC +***************************************************************************** */ + +#define AT91C_MC_CORRECT_KEY ( ( unsigned int ) 0x5A << 24 ) /* (MC) Correct Protect Key */ + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_MC_Remap */ +/** \brief Make Remap */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_MC_Remap( void ) /* */ +{ + AT91PS_MC pMC = ( AT91PS_MC ) AT91C_BASE_MC; + + pMC->MC_RCR = AT91C_MC_RCB; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_MC_EFC_CfgModeReg */ +/** \brief Configure the EFC Mode Register of the MC controller */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_MC_EFC_CfgModeReg( AT91PS_MC pMC, /* pointer to a MC controller */ + unsigned int mode ) /* mode register */ +{ + /* Write to the FMR register */ + pMC->MC_FMR = mode; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_MC_EFC_GetModeReg */ +/** \brief Return MC EFC Mode Register */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_MC_EFC_GetModeReg( AT91PS_MC pMC ) /* pointer to a MC controller */ +{ + return pMC->MC_FMR; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_MC_EFC_ComputeFMCN */ +/** \brief Return MC EFC Mode Register */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_MC_EFC_ComputeFMCN( int master_clock ) /* master clock in Hz */ +{ + return( master_clock / 1000000 + 2 ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_MC_EFC_PerformCmd */ +/** \brief Perform EFC Command */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_MC_EFC_PerformCmd( AT91PS_MC pMC, /* pointer to a MC controller */ + unsigned int transfer_cmd ) +{ + pMC->MC_FCR = transfer_cmd; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_MC_EFC_GetStatus */ +/** \brief Return MC EFC Status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_MC_EFC_GetStatus( AT91PS_MC pMC ) /* pointer to a MC controller */ +{ + return pMC->MC_FSR; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_MC_EFC_IsInterruptMasked */ +/** \brief Test if EFC MC Interrupt is Masked */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_MC_EFC_IsInterruptMasked( AT91PS_MC pMC, /* \arg pointer to a MC controller */ + unsigned int flag ) /* \arg flag to be tested */ +{ + return( AT91F_MC_EFC_GetModeReg( pMC ) & flag ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_MC_EFC_IsInterruptSet */ +/** \brief Test if EFC MC Interrupt is Set */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_MC_EFC_IsInterruptSet( AT91PS_MC pMC, /* \arg pointer to a MC controller */ + unsigned int flag ) /* \arg flag to be tested */ +{ + return( AT91F_MC_EFC_GetStatus( pMC ) & flag ); +} + +/* ***************************************************************************** +* SOFTWARE API FOR PDC +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_SetNextRx */ +/** \brief Set the next receive transfer descriptor */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PDC_SetNextRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ + char * address, /* \arg address to the next block to be received */ + unsigned int bytes ) /* \arg number of bytes to be received */ +{ + pPDC->PDC_RNPR = ( unsigned int ) address; + pPDC->PDC_RNCR = bytes; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_SetNextTx */ +/** \brief Set the next transmit transfer descriptor */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PDC_SetNextTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ + char * address, /* \arg address to the next block to be transmitted */ + unsigned int bytes ) /* \arg number of bytes to be transmitted */ +{ + pPDC->PDC_TNPR = ( unsigned int ) address; + pPDC->PDC_TNCR = bytes; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_SetRx */ +/** \brief Set the receive transfer descriptor */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PDC_SetRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ + char * address, /* \arg address to the next block to be received */ + unsigned int bytes ) /* \arg number of bytes to be received */ +{ + pPDC->PDC_RPR = ( unsigned int ) address; + pPDC->PDC_RCR = bytes; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_SetTx */ +/** \brief Set the transmit transfer descriptor */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PDC_SetTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ + char * address, /* \arg address to the next block to be transmitted */ + unsigned int bytes ) /* \arg number of bytes to be transmitted */ +{ + pPDC->PDC_TPR = ( unsigned int ) address; + pPDC->PDC_TCR = bytes; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_EnableTx */ +/** \brief Enable transmit */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PDC_EnableTx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ +{ + pPDC->PDC_PTCR = AT91C_PDC_TXTEN; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_EnableRx */ +/** \brief Enable receive */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PDC_EnableRx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ +{ + pPDC->PDC_PTCR = AT91C_PDC_RXTEN; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_DisableTx */ +/** \brief Disable transmit */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PDC_DisableTx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ +{ + pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_DisableRx */ +/** \brief Disable receive */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PDC_DisableRx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ +{ + pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_IsTxEmpty */ +/** \brief Test if the current transfer descriptor has been sent */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_PDC_IsTxEmpty( /* \return return 1 if transfer is complete */ + AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ +{ + return !( pPDC->PDC_TCR ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_IsNextTxEmpty */ +/** \brief Test if the next transfer descriptor has been moved to the current td */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_PDC_IsNextTxEmpty( /* \return return 1 if transfer is complete */ + AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ +{ + return !( pPDC->PDC_TNCR ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_IsRxEmpty */ +/** \brief Test if the current transfer descriptor has been filled */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_PDC_IsRxEmpty( /* \return return 1 if transfer is complete */ + AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ +{ + return !( pPDC->PDC_RCR ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_IsNextRxEmpty */ +/** \brief Test if the next transfer descriptor has been moved to the current td */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_PDC_IsNextRxEmpty( /* \return return 1 if transfer is complete */ + AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ +{ + return !( pPDC->PDC_RNCR ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_Open */ +/** \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PDC_Open( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ +{ + /** Disable the RX and TX PDC transfer requests */ + AT91F_PDC_DisableRx( pPDC ); + AT91F_PDC_DisableTx( pPDC ); + + /** Reset all Counter register Next buffer first */ + AT91F_PDC_SetNextTx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetNextRx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetTx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetRx( pPDC, ( char * ) 0, 0 ); + + /** Enable the RX and TX PDC transfer requests */ + AT91F_PDC_EnableRx( pPDC ); + AT91F_PDC_EnableTx( pPDC ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_Close */ +/** \brief Close PDC: disable TX and RX reset transfer descriptors */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PDC_Close( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ +{ + /** Disable the RX and TX PDC transfer requests */ + AT91F_PDC_DisableRx( pPDC ); + AT91F_PDC_DisableTx( pPDC ); + + /** Reset all Counter register Next buffer first */ + AT91F_PDC_SetNextTx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetNextRx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetTx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetRx( pPDC, ( char * ) 0, 0 ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_SendFrame */ +/** \brief Close PDC: disable TX and RX reset transfer descriptors */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PDC_SendFrame( AT91PS_PDC pPDC, + char * pBuffer, + unsigned int szBuffer, + char * pNextBuffer, + unsigned int szNextBuffer ) +{ + if( AT91F_PDC_IsTxEmpty( pPDC ) ) + { + /** Buffer and next buffer can be initialized */ + AT91F_PDC_SetTx( pPDC, pBuffer, szBuffer ); + AT91F_PDC_SetNextTx( pPDC, pNextBuffer, szNextBuffer ); + return 2; + } + else if( AT91F_PDC_IsNextTxEmpty( pPDC ) ) + { + /** Only one buffer can be initialized */ + AT91F_PDC_SetNextTx( pPDC, pBuffer, szBuffer ); + return 1; + } + else + { + /** All buffer are in use... */ + return 0; + } +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_ReceiveFrame */ +/** \brief Close PDC: disable TX and RX reset transfer descriptors */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PDC_ReceiveFrame( AT91PS_PDC pPDC, + char * pBuffer, + unsigned int szBuffer, + char * pNextBuffer, + unsigned int szNextBuffer ) +{ + if( AT91F_PDC_IsRxEmpty( pPDC ) ) + { + /** Buffer and next buffer can be initialized */ + AT91F_PDC_SetRx( pPDC, pBuffer, szBuffer ); + AT91F_PDC_SetNextRx( pPDC, pNextBuffer, szNextBuffer ); + return 2; + } + else if( AT91F_PDC_IsNextRxEmpty( pPDC ) ) + { + /** Only one buffer can be initialized */ + AT91F_PDC_SetNextRx( pPDC, pBuffer, szBuffer ); + return 1; + } + else + { + /** All buffer are in use... */ + return 0; + } +} + +/* ***************************************************************************** +* SOFTWARE API FOR DBGU +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_DBGU_InterruptEnable */ +/** \brief Enable DBGU Interrupt */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_DBGU_InterruptEnable( AT91PS_DBGU pDbgu, /* \arg pointer to a DBGU controller */ + unsigned int flag ) /* \arg dbgu interrupt to be enabled */ +{ + pDbgu->DBGU_IER = flag; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_DBGU_InterruptDisable */ +/** \brief Disable DBGU Interrupt */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_DBGU_InterruptDisable( AT91PS_DBGU pDbgu, /* \arg pointer to a DBGU controller */ + unsigned int flag ) /* \arg dbgu interrupt to be disabled */ +{ + pDbgu->DBGU_IDR = flag; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_DBGU_GetInterruptMaskStatus */ +/** \brief Return DBGU Interrupt Mask Status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( /* \return DBGU Interrupt Mask Status */ + AT91PS_DBGU pDbgu ) /* \arg pointer to a DBGU controller */ +{ + return pDbgu->DBGU_IMR; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_DBGU_IsInterruptMasked */ +/** \brief Test if DBGU Interrupt is Masked */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_DBGU_IsInterruptMasked( AT91PS_DBGU pDbgu, /* \arg pointer to a DBGU controller */ + unsigned int flag ) /* \arg flag to be tested */ +{ + return( AT91F_DBGU_GetInterruptMaskStatus( pDbgu ) & flag ); +} + +/* ***************************************************************************** +* SOFTWARE API FOR SSC +***************************************************************************** */ +/** Define the standard I2S mode configuration */ + +/** Configuration to set in the SSC Transmit Clock Mode Register */ +/** Parameters : nb_bit_by_slot : 8, 16 or 32 bits */ +/** nb_slot_by_frame : number of channels */ +#define AT91C_I2S_ASY_MASTER_TX_SETTING( nb_bit_by_slot, nb_slot_by_frame ) \ + ( + \ + AT91C_SSC_CKS_DIV + \ + AT91C_SSC_CKO_CONTINUOUS + \ + AT91C_SSC_CKG_NONE + \ + AT91C_SSC_START_FALL_RF + \ + AT91C_SSC_STTOUT + \ + ( ( 1 << 16 ) & AT91C_SSC_STTDLY ) + \ + ( ( ( ( nb_bit_by_slot * nb_slot_by_frame ) / 2 ) - 1 ) << 24 ) ) + + +/** Configuration to set in the SSC Transmit Frame Mode Register */ +/** Parameters : nb_bit_by_slot : 8, 16 or 32 bits */ +/** nb_slot_by_frame : number of channels */ +#define AT91C_I2S_ASY_TX_FRAME_SETTING( nb_bit_by_slot, nb_slot_by_frame ) \ + ( + \ + ( nb_bit_by_slot - 1 ) + \ + AT91C_SSC_MSBF + \ + ( ( ( nb_slot_by_frame - 1 ) << 8 ) & AT91C_SSC_DATNB ) + \ + ( ( ( nb_bit_by_slot - 1 ) << 16 ) & AT91C_SSC_FSLEN ) + \ + AT91C_SSC_FSOS_NEGATIVE ) + + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SSC_SetBaudrate */ +/** \brief Set the baudrate according to the CPU clock */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_SSC_SetBaudrate( AT91PS_SSC pSSC, /* \arg pointer to a SSC controller */ + unsigned int mainClock, /* \arg peripheral clock */ + unsigned int speed ) /* \arg SSC baudrate */ +{ + unsigned int baud_value; + + /** Define the baud rate divisor register */ + if( speed == 0 ) + { + baud_value = 0; + } + else + { + baud_value = ( unsigned int ) ( mainClock * 10 ) / ( 2 * speed ); + + if( ( baud_value % 10 ) >= 5 ) + { + baud_value = ( baud_value / 10 ) + 1; + } + else + { + baud_value /= 10; + } + } + + pSSC->SSC_CMR = baud_value; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SSC_Configure */ +/** \brief Configure SSC */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_SSC_Configure( AT91PS_SSC pSSC, /* \arg pointer to a SSC controller */ + unsigned int syst_clock, /* \arg System Clock Frequency */ + unsigned int baud_rate, /* \arg Expected Baud Rate Frequency */ + unsigned int clock_rx, /* \arg Receiver Clock Parameters */ + unsigned int mode_rx, /* \arg mode Register to be programmed */ + unsigned int clock_tx, /* \arg Transmitter Clock Parameters */ + unsigned int mode_tx ) /* \arg mode Register to be programmed */ +{ + /** Disable interrupts */ + pSSC->SSC_IDR = ( unsigned int ) -1; + + /** Reset receiver and transmitter */ + pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS; + + /** Define the Clock Mode Register */ + AT91F_SSC_SetBaudrate( pSSC, syst_clock, baud_rate ); + + /** Write the Receive Clock Mode Register */ + pSSC->SSC_RCMR = clock_rx; + + /** Write the Transmit Clock Mode Register */ + pSSC->SSC_TCMR = clock_tx; + + /** Write the Receive Frame Mode Register */ + pSSC->SSC_RFMR = mode_rx; + + /** Write the Transmit Frame Mode Register */ + pSSC->SSC_TFMR = mode_tx; + + /** Clear Transmit and Receive Counters */ + AT91F_PDC_Open( ( AT91PS_PDC ) &( pSSC->SSC_RPR ) ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SSC_EnableRx */ +/** \brief Enable receiving data */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_SSC_EnableRx( AT91PS_SSC pSSC ) /* \arg pointer to a SSC controller */ +{ + /** Enable receiver */ + pSSC->SSC_CR = AT91C_SSC_RXEN; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SSC_DisableRx */ +/** \brief Disable receiving data */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_SSC_DisableRx( AT91PS_SSC pSSC ) /* \arg pointer to a SSC controller */ +{ + /** Disable receiver */ + pSSC->SSC_CR = AT91C_SSC_RXDIS; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SSC_EnableTx */ +/** \brief Enable sending data */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_SSC_EnableTx( AT91PS_SSC pSSC ) /* \arg pointer to a SSC controller */ +{ + /** Enable transmitter */ + pSSC->SSC_CR = AT91C_SSC_TXEN; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SSC_DisableTx */ +/** \brief Disable sending data */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_SSC_DisableTx( AT91PS_SSC pSSC ) /* \arg pointer to a SSC controller */ +{ + /** Disable transmitter */ + pSSC->SSC_CR = AT91C_SSC_TXDIS; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SSC_EnableIt */ +/** \brief Enable SSC IT */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_SSC_EnableIt( AT91PS_SSC pSSC, /* \arg pointer to a SSC controller */ + unsigned int flag ) /* \arg IT to be enabled */ +{ + /** Write to the IER register */ + pSSC->SSC_IER = flag; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SSC_DisableIt */ +/** \brief Disable SSC IT */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_SSC_DisableIt( AT91PS_SSC pSSC, /* \arg pointer to a SSC controller */ + unsigned int flag ) /* \arg IT to be disabled */ +{ + /** Write to the IDR register */ + pSSC->SSC_IDR = flag; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SSC_ReceiveFrame */ +/** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_SSC_ReceiveFrame( AT91PS_SSC pSSC, + char * pBuffer, + unsigned int szBuffer, + char * pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + ( AT91PS_PDC ) &( pSSC->SSC_RPR ), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SSC_SendFrame */ +/** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_SSC_SendFrame( AT91PS_SSC pSSC, + char * pBuffer, + unsigned int szBuffer, + char * pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + ( AT91PS_PDC ) &( pSSC->SSC_RPR ), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SSC_GetInterruptMaskStatus */ +/** \brief Return SSC Interrupt Mask Status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( /* \return SSC Interrupt Mask Status */ + AT91PS_SSC pSsc ) /* \arg pointer to a SSC controller */ +{ + return pSsc->SSC_IMR; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SSC_IsInterruptMasked */ +/** \brief Test if SSC Interrupt is Masked */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_SSC_IsInterruptMasked( AT91PS_SSC pSsc, /* \arg pointer to a SSC controller */ + unsigned int flag ) /* \arg flag to be tested */ +{ + return( AT91F_SSC_GetInterruptMaskStatus( pSsc ) & flag ); +} + +/* ***************************************************************************** +* SOFTWARE API FOR SPI +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SPI_Open */ +/** \brief Open a SPI Port */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_SPI_Open( const unsigned int null ) /* \arg */ +{ + /* NOT DEFINED AT THIS MOMENT */ + return( 0 ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SPI_CfgCs */ +/** \brief Configure SPI chip select register */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_SPI_CfgCs( AT91PS_SPI pSPI, /* pointer to a SPI controller */ + int cs, /* SPI cs number (0 to 3) */ + int val ) /* chip select register */ +{ + /** Write to the CSR register */ + *( pSPI->SPI_CSR + cs ) = val; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SPI_EnableIt */ +/** \brief Enable SPI interrupt */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_SPI_EnableIt( AT91PS_SPI pSPI, /* pointer to a SPI controller */ + unsigned int flag ) /* IT to be enabled */ +{ + /** Write to the IER register */ + pSPI->SPI_IER = flag; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SPI_DisableIt */ +/** \brief Disable SPI interrupt */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_SPI_DisableIt( AT91PS_SPI pSPI, /* pointer to a SPI controller */ + unsigned int flag ) /* IT to be disabled */ +{ + /** Write to the IDR register */ + pSPI->SPI_IDR = flag; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SPI_Reset */ +/** \brief Reset the SPI controller */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_SPI_Reset( AT91PS_SPI pSPI /* pointer to a SPI controller */ + ) +{ + /** Write to the CR register */ + pSPI->SPI_CR = AT91C_SPI_SWRST; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SPI_Enable */ +/** \brief Enable the SPI controller */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_SPI_Enable( AT91PS_SPI pSPI /* pointer to a SPI controller */ + ) +{ + /** Write to the CR register */ + pSPI->SPI_CR = AT91C_SPI_SPIEN; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SPI_Disable */ +/** \brief Disable the SPI controller */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_SPI_Disable( AT91PS_SPI pSPI /* pointer to a SPI controller */ + ) +{ + /** Write to the CR register */ + pSPI->SPI_CR = AT91C_SPI_SPIDIS; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SPI_CfgMode */ +/** \brief Enable the SPI controller */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_SPI_CfgMode( AT91PS_SPI pSPI, /* pointer to a SPI controller */ + int mode ) /* mode register */ +{ + /** Write to the MR register */ + pSPI->SPI_MR = mode; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SPI_CfgPCS */ +/** \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_SPI_CfgPCS( AT91PS_SPI pSPI, /* pointer to a SPI controller */ + char PCS_Device ) /* PCS of the Device */ +{ + /** Write to the MR register */ + pSPI->SPI_MR &= 0xFFF0FFFF; + pSPI->SPI_MR |= ( ( PCS_Device << 16 ) & AT91C_SPI_PCS ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SPI_ReceiveFrame */ +/** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_SPI_ReceiveFrame( AT91PS_SPI pSPI, + char * pBuffer, + unsigned int szBuffer, + char * pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + ( AT91PS_PDC ) &( pSPI->SPI_RPR ), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SPI_SendFrame */ +/** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is bSPIy */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_SPI_SendFrame( AT91PS_SPI pSPI, + char * pBuffer, + unsigned int szBuffer, + char * pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + ( AT91PS_PDC ) &( pSPI->SPI_RPR ), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SPI_Close */ +/** \brief Close SPI: disable IT disable transfer, close PDC */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_SPI_Close( AT91PS_SPI pSPI ) /* \arg pointer to a SPI controller */ +{ + /** Reset all the Chip Select register */ + pSPI->SPI_CSR[ 0 ] = 0; + pSPI->SPI_CSR[ 1 ] = 0; + pSPI->SPI_CSR[ 2 ] = 0; + pSPI->SPI_CSR[ 3 ] = 0; + + /** Reset the SPI mode */ + pSPI->SPI_MR = 0; + + /** Disable all interrupts */ + pSPI->SPI_IDR = 0xFFFFFFFF; + + /** Abort the Peripheral Data Transfers */ + AT91F_PDC_Close( ( AT91PS_PDC ) &( pSPI->SPI_RPR ) ); + + /** Disable receiver and transmitter and stop any activity immediately */ + pSPI->SPI_CR = AT91C_SPI_SPIDIS; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SPI_PutChar */ +/** \brief Send a character,does not check if ready to send */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_SPI_PutChar( AT91PS_SPI pSPI, + unsigned int character, + unsigned int cs_number ) +{ + unsigned int value_for_cs; + + value_for_cs = ( ~( 1 << cs_number ) ) & 0xF; /*Place a zero among a 4 ONEs number */ + pSPI->SPI_TDR = ( character & 0xFFFF ) | ( value_for_cs << 16 ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SPI_GetChar */ +/** \brief Receive a character,does not check if a character is available */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_SPI_GetChar( const AT91PS_SPI pSPI ) +{ + return( ( pSPI->SPI_RDR ) & 0xFFFF ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SPI_GetInterruptMaskStatus */ +/** \brief Return SPI Interrupt Mask Status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( /* \return SPI Interrupt Mask Status */ + AT91PS_SPI pSpi ) /* \arg pointer to a SPI controller */ +{ + return pSpi->SPI_IMR; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SPI_IsInterruptMasked */ +/** \brief Test if SPI Interrupt is Masked */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_SPI_IsInterruptMasked( AT91PS_SPI pSpi, /* \arg pointer to a SPI controller */ + unsigned int flag ) /* \arg flag to be tested */ +{ + return( AT91F_SPI_GetInterruptMaskStatus( pSpi ) & flag ); +} + +/* ***************************************************************************** +* SOFTWARE API FOR PWMC +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PWM_GetStatus */ +/** \brief Return PWM Interrupt Status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PWMC_GetStatus( /* \return PWM Interrupt Status */ + AT91PS_PWMC pPWM ) /* pointer to a PWM controller */ +{ + return pPWM->PWMC_SR; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PWM_InterruptEnable */ +/** \brief Enable PWM Interrupt */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PWMC_InterruptEnable( AT91PS_PWMC pPwm, /* \arg pointer to a PWM controller */ + unsigned int flag ) /* \arg PWM interrupt to be enabled */ +{ + pPwm->PWMC_IER = flag; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PWM_InterruptDisable */ +/** \brief Disable PWM Interrupt */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PWMC_InterruptDisable( AT91PS_PWMC pPwm, /* \arg pointer to a PWM controller */ + unsigned int flag ) /* \arg PWM interrupt to be disabled */ +{ + pPwm->PWMC_IDR = flag; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PWM_GetInterruptMaskStatus */ +/** \brief Return PWM Interrupt Mask Status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( /* \return PWM Interrupt Mask Status */ + AT91PS_PWMC pPwm ) /* \arg pointer to a PWM controller */ +{ + return pPwm->PWMC_IMR; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PWM_IsInterruptMasked */ +/** \brief Test if PWM Interrupt is Masked */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PWMC_IsInterruptMasked( AT91PS_PWMC pPWM, /* \arg pointer to a PWM controller */ + unsigned int flag ) /* \arg flag to be tested */ +{ + return( AT91F_PWMC_GetInterruptMaskStatus( pPWM ) & flag ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PWM_IsStatusSet */ +/** \brief Test if PWM Interrupt is Set */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PWMC_IsStatusSet( AT91PS_PWMC pPWM, /* \arg pointer to a PWM controller */ + unsigned int flag ) /* \arg flag to be tested */ +{ + return( AT91F_PWMC_GetStatus( pPWM ) & flag ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PWM_CfgChannel */ +/** \brief Test if PWM Interrupt is Set */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PWMC_CfgChannel( AT91PS_PWMC pPWM, /* \arg pointer to a PWM controller */ + unsigned int channelId, /* \arg PWM channel ID */ + unsigned int mode, /* \arg PWM mode */ + unsigned int period, /* \arg PWM period */ + unsigned int duty ) /* \arg PWM duty cycle */ +{ + pPWM->PWMC_CH[ channelId ].PWMC_CMR = mode; + pPWM->PWMC_CH[ channelId ].PWMC_CDTYR = duty; + pPWM->PWMC_CH[ channelId ].PWMC_CPRDR = period; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PWM_StartChannel */ +/** \brief Enable channel */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PWMC_StartChannel( AT91PS_PWMC pPWM, /* \arg pointer to a PWM controller */ + unsigned int flag ) /* \arg Channels IDs to be enabled */ +{ + pPWM->PWMC_ENA = flag; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PWM_StopChannel */ +/** \brief Disable channel */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PWMC_StopChannel( AT91PS_PWMC pPWM, /* \arg pointer to a PWM controller */ + unsigned int flag ) /* \arg Channels IDs to be enabled */ +{ + pPWM->PWMC_DIS = flag; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PWM_UpdateChannel */ +/** \brief Update Period or Duty Cycle */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PWMC_UpdateChannel( AT91PS_PWMC pPWM, /* \arg pointer to a PWM controller */ + unsigned int channelId, /* \arg PWM channel ID */ + unsigned int update ) /* \arg Channels IDs to be enabled */ +{ + pPWM->PWMC_CH[ channelId ].PWMC_CUPDR = update; +} + +/* ***************************************************************************** +* SOFTWARE API FOR TC +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_TC_InterruptEnable */ +/** \brief Enable TC Interrupt */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_TC_InterruptEnable( AT91PS_TC pTc, /* \arg pointer to a TC controller */ + unsigned int flag ) /* \arg TC interrupt to be enabled */ +{ + pTc->TC_IER = flag; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_TC_InterruptDisable */ +/** \brief Disable TC Interrupt */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_TC_InterruptDisable( AT91PS_TC pTc, /* \arg pointer to a TC controller */ + unsigned int flag ) /* \arg TC interrupt to be disabled */ +{ + pTc->TC_IDR = flag; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_TC_GetInterruptMaskStatus */ +/** \brief Return TC Interrupt Mask Status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_TC_GetInterruptMaskStatus( /* \return TC Interrupt Mask Status */ + AT91PS_TC pTc ) /* \arg pointer to a TC controller */ +{ + return pTc->TC_IMR; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_TC_IsInterruptMasked */ +/** \brief Test if TC Interrupt is Masked */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_TC_IsInterruptMasked( AT91PS_TC pTc, /* \arg pointer to a TC controller */ + unsigned int flag ) /* \arg flag to be tested */ +{ + return( AT91F_TC_GetInterruptMaskStatus( pTc ) & flag ); +} + +/* ***************************************************************************** +* SOFTWARE API FOR PMC +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_CfgSysClkEnableReg */ +/** \brief Configure the System Clock Enable Register of the PMC controller */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PMC_CfgSysClkEnableReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int mode ) +{ + /** Write to the SCER register */ + pPMC->PMC_SCER = mode; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_CfgSysClkDisableReg */ +/** \brief Configure the System Clock Disable Register of the PMC controller */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PMC_CfgSysClkDisableReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int mode ) +{ + /** Write to the SCDR register */ + pPMC->PMC_SCDR = mode; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_GetSysClkStatusReg */ +/** \brief Return the System Clock Status Register of the PMC controller */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PMC_GetSysClkStatusReg( AT91PS_PMC pPMC /* pointer to a CAN controller */ + ) +{ + return pPMC->PMC_SCSR; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_EnablePeriphClock */ +/** \brief Enable peripheral clock */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PMC_EnablePeriphClock( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int periphIds ) /* \arg IDs of peripherals to enable */ +{ + pPMC->PMC_PCER = periphIds; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_DisablePeriphClock */ +/** \brief Disable peripheral clock */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PMC_DisablePeriphClock( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int periphIds ) /* \arg IDs of peripherals to enable */ +{ + pPMC->PMC_PCDR = periphIds; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_GetPeriphClock */ +/** \brief Get peripheral clock status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PMC_GetPeriphClock( AT91PS_PMC pPMC ) /* \arg pointer to PMC controller */ +{ + return pPMC->PMC_PCSR; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_CfgMainOscillatorReg */ +/** \brief Cfg the main oscillator */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_CKGR_CfgMainOscillatorReg( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */ + unsigned int mode ) +{ + pCKGR->CKGR_MOR = mode; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_GetMainOscillatorReg */ +/** \brief Cfg the main oscillator */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_CKGR_GetMainOscillatorReg( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */ +{ + return pCKGR->CKGR_MOR; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_EnableMainOscillator */ +/** \brief Enable the main oscillator */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_CKGR_EnableMainOscillator( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */ +{ + pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_DisableMainOscillator */ +/** \brief Disable the main oscillator */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_CKGR_DisableMainOscillator( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */ +{ + pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_CfgMainOscStartUpTime */ +/** \brief Cfg MORE Register according to the main osc startup time */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_CKGR_CfgMainOscStartUpTime( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */ + unsigned int startup_time, /* \arg main osc startup time in microsecond (us) */ + unsigned int slowClock ) /* \arg slowClock in Hz */ +{ + pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT; + pCKGR->CKGR_MOR |= ( ( slowClock * startup_time ) / ( 8 * 1000000 ) ) << 8; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_GetMainClockFreqReg */ +/** \brief Cfg the main oscillator */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_CKGR_GetMainClockFreqReg( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */ +{ + return pCKGR->CKGR_MCFR; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_GetMainClock */ +/** \brief Return Main clock in Hz */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_CKGR_GetMainClock( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */ + unsigned int slowClock ) /* \arg slowClock in Hz */ +{ + return ( ( pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF ) * slowClock ) >> 4; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_CfgMCKReg */ +/** \brief Cfg Master Clock Register */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PMC_CfgMCKReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int mode ) +{ + pPMC->PMC_MCKR = mode; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_GetMCKReg */ +/** \brief Return Master Clock Register */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PMC_GetMCKReg( AT91PS_PMC pPMC ) /* \arg pointer to PMC controller */ +{ + return pPMC->PMC_MCKR; +} + +/**------------------------------------------------------------------------------ */ +/** \fn AT91F_PMC_GetMasterClock */ +/** \brief Return master clock in Hz which corresponds to processor clock for ARM7 */ +/**------------------------------------------------------------------------------ */ +__inline unsigned int AT91F_PMC_GetMasterClock( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */ + unsigned int slowClock ) /* \arg slowClock in Hz */ +{ + unsigned int reg = pPMC->PMC_MCKR; + unsigned int prescaler = ( 1 << ( ( reg & AT91C_PMC_PRES ) >> 2 ) ); + unsigned int pllDivider, pllMultiplier; + + switch( reg & AT91C_PMC_CSS ) + { + case AT91C_PMC_CSS_SLOW_CLK: /* Slow clock selected */ + return slowClock / prescaler; + + case AT91C_PMC_CSS_MAIN_CLK: /* Main clock is selected */ + return AT91F_CKGR_GetMainClock( pCKGR, slowClock ) / prescaler; + + case AT91C_PMC_CSS_PLL_CLK: /* PLLB clock is selected */ + reg = pCKGR->CKGR_PLLR; + pllDivider = ( reg & AT91C_CKGR_DIV ); + pllMultiplier = ( ( reg & AT91C_CKGR_MUL ) >> 16 ) + 1; + return AT91F_CKGR_GetMainClock( pCKGR, slowClock ) / pllDivider * pllMultiplier / prescaler; + } + + return 0; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_EnablePCK */ +/** \brief Enable peripheral clock */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PMC_EnablePCK( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int pck, /* \arg Peripheral clock identifier 0 .. 7 */ + unsigned int mode ) +{ + pPMC->PMC_PCKR[ pck ] = mode; + pPMC->PMC_SCER = ( 1 << pck ) << 8; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_DisablePCK */ +/** \brief Enable peripheral clock */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PMC_DisablePCK( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int pck ) /* \arg Peripheral clock identifier 0 .. 7 */ +{ + pPMC->PMC_SCDR = ( 1 << pck ) << 8; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_EnableIt */ +/** \brief Enable PMC interrupt */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PMC_EnableIt( AT91PS_PMC pPMC, /* pointer to a PMC controller */ + unsigned int flag ) /* IT to be enabled */ +{ + /** Write to the IER register */ + pPMC->PMC_IER = flag; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_DisableIt */ +/** \brief Disable PMC interrupt */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PMC_DisableIt( AT91PS_PMC pPMC, /* pointer to a PMC controller */ + unsigned int flag ) /* IT to be disabled */ +{ + /** Write to the IDR register */ + pPMC->PMC_IDR = flag; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_GetStatus */ +/** \brief Return PMC Interrupt Status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PMC_GetStatus( /* \return PMC Interrupt Status */ + AT91PS_PMC pPMC ) /* pointer to a PMC controller */ +{ + return pPMC->PMC_SR; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_GetInterruptMaskStatus */ +/** \brief Return PMC Interrupt Mask Status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( /* \return PMC Interrupt Mask Status */ + AT91PS_PMC pPMC ) /* pointer to a PMC controller */ +{ + return pPMC->PMC_IMR; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_IsInterruptMasked */ +/** \brief Test if PMC Interrupt is Masked */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PMC_IsInterruptMasked( AT91PS_PMC pPMC, /* \arg pointer to a PMC controller */ + unsigned int flag ) /* \arg flag to be tested */ +{ + return( AT91F_PMC_GetInterruptMaskStatus( pPMC ) & flag ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_IsStatusSet */ +/** \brief Test if PMC Status is Set */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PMC_IsStatusSet( AT91PS_PMC pPMC, /* \arg pointer to a PMC controller */ + unsigned int flag ) /* \arg flag to be tested */ +{ + return( AT91F_PMC_GetStatus( pPMC ) & flag ); +} /* ***************************************************************************** + * SOFTWARE API FOR ADC + ***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_EnableIt */ +/** \brief Enable ADC interrupt */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_ADC_EnableIt( AT91PS_ADC pADC, /* pointer to a ADC controller */ + unsigned int flag ) /* IT to be enabled */ +{ + /** Write to the IER register */ + pADC->ADC_IER = flag; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_DisableIt */ +/** \brief Disable ADC interrupt */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_ADC_DisableIt( AT91PS_ADC pADC, /* pointer to a ADC controller */ + unsigned int flag ) /* IT to be disabled */ +{ + /** Write to the IDR register */ + pADC->ADC_IDR = flag; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_GetStatus */ +/** \brief Return ADC Interrupt Status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_ADC_GetStatus( /* \return ADC Interrupt Status */ + AT91PS_ADC pADC ) /* pointer to a ADC controller */ +{ + return pADC->ADC_SR; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_GetInterruptMaskStatus */ +/** \brief Return ADC Interrupt Mask Status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( /* \return ADC Interrupt Mask Status */ + AT91PS_ADC pADC ) /* pointer to a ADC controller */ +{ + return pADC->ADC_IMR; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_IsInterruptMasked */ +/** \brief Test if ADC Interrupt is Masked */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_ADC_IsInterruptMasked( AT91PS_ADC pADC, /* \arg pointer to a ADC controller */ + unsigned int flag ) /* \arg flag to be tested */ +{ + return( AT91F_ADC_GetInterruptMaskStatus( pADC ) & flag ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_IsStatusSet */ +/** \brief Test if ADC Status is Set */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_ADC_IsStatusSet( AT91PS_ADC pADC, /* \arg pointer to a ADC controller */ + unsigned int flag ) /* \arg flag to be tested */ +{ + return( AT91F_ADC_GetStatus( pADC ) & flag ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_CfgModeReg */ +/** \brief Configure the Mode Register of the ADC controller */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_ADC_CfgModeReg( AT91PS_ADC pADC, /* pointer to a ADC controller */ + unsigned int mode ) /* mode register */ +{ + /** Write to the MR register */ + pADC->ADC_MR = mode; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_GetModeReg */ +/** \brief Return the Mode Register of the ADC controller value */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_ADC_GetModeReg( AT91PS_ADC pADC /* pointer to a ADC controller */ + ) +{ + return pADC->ADC_MR; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_CfgTimings */ +/** \brief Configure the different necessary timings of the ADC controller */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_ADC_CfgTimings( AT91PS_ADC pADC, /* pointer to a ADC controller */ + unsigned int mck_clock, /* in MHz */ + unsigned int adc_clock, /* in MHz */ + unsigned int startup_time, /* in us */ + unsigned int sample_and_hold_time ) /* in ns */ +{ + unsigned int prescal, startup, shtim; + + prescal = mck_clock / ( 2 * adc_clock ) - 1; + startup = adc_clock * startup_time / 8 - 1; + shtim = adc_clock * sample_and_hold_time / 1000 - 1; + + /** Write to the MR register */ + pADC->ADC_MR = ( ( prescal << 8 ) & AT91C_ADC_PRESCAL ) | ( ( startup << 16 ) & AT91C_ADC_STARTUP ) | ( ( shtim << 24 ) & AT91C_ADC_SHTIM ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_EnableChannel */ +/** \brief Return ADC Timer Register Value */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_ADC_EnableChannel( AT91PS_ADC pADC, /* pointer to a ADC controller */ + unsigned int channel ) /* mode register */ +{ + /** Write to the CHER register */ + pADC->ADC_CHER = channel; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_DisableChannel */ +/** \brief Return ADC Timer Register Value */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_ADC_DisableChannel( AT91PS_ADC pADC, /* pointer to a ADC controller */ + unsigned int channel ) /* mode register */ +{ + /** Write to the CHDR register */ + pADC->ADC_CHDR = channel; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_GetChannelStatus */ +/** \brief Return ADC Timer Register Value */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_ADC_GetChannelStatus( AT91PS_ADC pADC /* pointer to a ADC controller */ + ) +{ + return pADC->ADC_CHSR; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_StartConversion */ +/** \brief Software request for a analog to digital conversion */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_ADC_StartConversion( AT91PS_ADC pADC /* pointer to a ADC controller */ + ) +{ + pADC->ADC_CR = AT91C_ADC_START; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_SoftReset */ +/** \brief Software reset */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_ADC_SoftReset( AT91PS_ADC pADC /* pointer to a ADC controller */ + ) +{ + pADC->ADC_CR = AT91C_ADC_SWRST; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_GetLastConvertedData */ +/** \brief Return the Last Converted Data */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_ADC_GetLastConvertedData( AT91PS_ADC pADC /* pointer to a ADC controller */ + ) +{ + return pADC->ADC_LCDR; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_GetConvertedDataCH0 */ +/** \brief Return the Channel 0 Converted Data */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_ADC_GetConvertedDataCH0( AT91PS_ADC pADC /* pointer to a ADC controller */ + ) +{ + return pADC->ADC_CDR0; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_GetConvertedDataCH1 */ +/** \brief Return the Channel 1 Converted Data */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_ADC_GetConvertedDataCH1( AT91PS_ADC pADC /* pointer to a ADC controller */ + ) +{ + return pADC->ADC_CDR1; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_GetConvertedDataCH2 */ +/** \brief Return the Channel 2 Converted Data */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_ADC_GetConvertedDataCH2( AT91PS_ADC pADC /* pointer to a ADC controller */ + ) +{ + return pADC->ADC_CDR2; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_GetConvertedDataCH3 */ +/** \brief Return the Channel 3 Converted Data */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_ADC_GetConvertedDataCH3( AT91PS_ADC pADC /* pointer to a ADC controller */ + ) +{ + return pADC->ADC_CDR3; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_GetConvertedDataCH4 */ +/** \brief Return the Channel 4 Converted Data */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_ADC_GetConvertedDataCH4( AT91PS_ADC pADC /* pointer to a ADC controller */ + ) +{ + return pADC->ADC_CDR4; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_GetConvertedDataCH5 */ +/** \brief Return the Channel 5 Converted Data */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_ADC_GetConvertedDataCH5( AT91PS_ADC pADC /* pointer to a ADC controller */ + ) +{ + return pADC->ADC_CDR5; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_GetConvertedDataCH6 */ +/** \brief Return the Channel 6 Converted Data */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_ADC_GetConvertedDataCH6( AT91PS_ADC pADC /* pointer to a ADC controller */ + ) +{ + return pADC->ADC_CDR6; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_GetConvertedDataCH7 */ +/** \brief Return the Channel 7 Converted Data */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_ADC_GetConvertedDataCH7( AT91PS_ADC pADC /* pointer to a ADC controller */ + ) +{ + return pADC->ADC_CDR7; +} + +/* ***************************************************************************** +* SOFTWARE API FOR PIO +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgPeriph */ +/** \brief Enable pins to be derived by peripheral */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_CfgPeriph( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int periphAEnable, /* \arg PERIPH A to enable */ + unsigned int periphBEnable ) /* \arg PERIPH B to enable */ + +{ + pPio->PIO_ASR = periphAEnable; + pPio->PIO_BSR = periphBEnable; + pPio->PIO_PDR = ( periphAEnable | periphBEnable ); /* Set in Periph mode */ +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgOutput */ +/** \brief Enable PIO in output mode */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_CfgOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int pioEnable ) /* \arg PIO to be enabled */ +{ + pPio->PIO_PER = pioEnable; /* Set in PIO mode */ + pPio->PIO_OER = pioEnable; /* Configure in Output */ +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgInput */ +/** \brief Enable PIO in input mode */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_CfgInput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int inputEnable ) /* \arg PIO to be enabled */ +{ + /* Disable output */ + pPio->PIO_ODR = inputEnable; + pPio->PIO_PER = inputEnable; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgOpendrain */ +/** \brief Configure PIO in open drain */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_CfgOpendrain( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int multiDrvEnable ) /* \arg pio to be configured in open drain */ +{ + /* Configure the multi-drive option */ + pPio->PIO_MDDR = ~multiDrvEnable; + pPio->PIO_MDER = multiDrvEnable; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgPullup */ +/** \brief Enable pullup on PIO */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_CfgPullup( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int pullupEnable ) /* \arg enable pullup on PIO */ +{ + /* Connect or not Pullup */ + pPio->PIO_PPUDR = ~pullupEnable; + pPio->PIO_PPUER = pullupEnable; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgDirectDrive */ +/** \brief Enable direct drive on PIO */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_CfgDirectDrive( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int directDrive ) /* \arg PIO to be configured with direct drive */ + +{ + /* Configure the Direct Drive */ + pPio->PIO_OWDR = ~directDrive; + pPio->PIO_OWER = directDrive; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgInputFilter */ +/** \brief Enable input filter on input PIO */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_CfgInputFilter( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int inputFilter ) /* \arg PIO to be configured with input filter */ + +{ + /* Configure the Direct Drive */ + pPio->PIO_IFDR = ~inputFilter; + pPio->PIO_IFER = inputFilter; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetInput */ +/** \brief Return PIO input value */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PIO_GetInput( /* \return PIO input */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ +{ + return pPio->PIO_PDSR; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsInputSet */ +/** \brief Test if PIO is input flag is active */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_PIO_IsInputSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ +{ + return( AT91F_PIO_GetInput( pPio ) & flag ); +} + + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_SetOutput */ +/** \brief Set to 1 output PIO */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_SetOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg output to be set */ +{ + pPio->PIO_SODR = flag; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_ClearOutput */ +/** \brief Set to 0 output PIO */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_ClearOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg output to be cleared */ +{ + pPio->PIO_CODR = flag; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_ForceOutput */ +/** \brief Force output when Direct drive option is enabled */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_ForceOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg output to be forced */ +{ + pPio->PIO_ODSR = flag; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_Enable */ +/** \brief Enable PIO */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_Enable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio to be enabled */ +{ + pPio->PIO_PER = flag; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_Disable */ +/** \brief Disable PIO */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_Disable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio to be disabled */ +{ + pPio->PIO_PDR = flag; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetStatus */ +/** \brief Return PIO Status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PIO_GetStatus( /* \return PIO Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ +{ + return pPio->PIO_PSR; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsSet */ +/** \brief Test if PIO is Set */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_PIO_IsSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ +{ + return( AT91F_PIO_GetStatus( pPio ) & flag ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_OutputEnable */ +/** \brief Output Enable PIO */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_OutputEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio output to be enabled */ +{ + pPio->PIO_OER = flag; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_OutputDisable */ +/** \brief Output Enable PIO */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_OutputDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio output to be disabled */ +{ + pPio->PIO_ODR = flag; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetOutputStatus */ +/** \brief Return PIO Output Status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PIO_GetOutputStatus( /* \return PIO Output Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ +{ + return pPio->PIO_OSR; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsOuputSet */ +/** \brief Test if PIO Output is Set */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_PIO_IsOutputSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ +{ + return( AT91F_PIO_GetOutputStatus( pPio ) & flag ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_InputFilterEnable */ +/** \brief Input Filter Enable PIO */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_InputFilterEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio input filter to be enabled */ +{ + pPio->PIO_IFER = flag; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_InputFilterDisable */ +/** \brief Input Filter Disable PIO */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_InputFilterDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio input filter to be disabled */ +{ + pPio->PIO_IFDR = flag; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetInputFilterStatus */ +/** \brief Return PIO Input Filter Status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PIO_GetInputFilterStatus( /* \return PIO Input Filter Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ +{ + return pPio->PIO_IFSR; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsInputFilterSet */ +/** \brief Test if PIO Input filter is Set */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_PIO_IsInputFilterSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ +{ + return( AT91F_PIO_GetInputFilterStatus( pPio ) & flag ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetOutputDataStatus */ +/** \brief Return PIO Output Data Status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PIO_GetOutputDataStatus( /* \return PIO Output Data Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ +{ + return pPio->PIO_ODSR; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_InterruptEnable */ +/** \brief Enable PIO Interrupt */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_InterruptEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio interrupt to be enabled */ +{ + pPio->PIO_IER = flag; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_InterruptDisable */ +/** \brief Disable PIO Interrupt */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_InterruptDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio interrupt to be disabled */ +{ + pPio->PIO_IDR = flag; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetInterruptMaskStatus */ +/** \brief Return PIO Interrupt Mask Status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( /* \return PIO Interrupt Mask Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ +{ + return pPio->PIO_IMR; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetInterruptStatus */ +/** \brief Return PIO Interrupt Status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PIO_GetInterruptStatus( /* \return PIO Interrupt Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ +{ + return pPio->PIO_ISR; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsInterruptMasked */ +/** \brief Test if PIO Interrupt is Masked */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_PIO_IsInterruptMasked( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ +{ + return( AT91F_PIO_GetInterruptMaskStatus( pPio ) & flag ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsInterruptSet */ +/** \brief Test if PIO Interrupt is Set */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_PIO_IsInterruptSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ +{ + return( AT91F_PIO_GetInterruptStatus( pPio ) & flag ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_MultiDriverEnable */ +/** \brief Multi Driver Enable PIO */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_MultiDriverEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio to be enabled */ +{ + pPio->PIO_MDER = flag; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_MultiDriverDisable */ +/** \brief Multi Driver Disable PIO */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_MultiDriverDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio to be disabled */ +{ + pPio->PIO_MDDR = flag; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetMultiDriverStatus */ +/** \brief Return PIO Multi Driver Status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PIO_GetMultiDriverStatus( /* \return PIO Multi Driver Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ +{ + return pPio->PIO_MDSR; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsMultiDriverSet */ +/** \brief Test if PIO MultiDriver is Set */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_PIO_IsMultiDriverSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ +{ + return( AT91F_PIO_GetMultiDriverStatus( pPio ) & flag ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_A_RegisterSelection */ +/** \brief PIO A Register Selection */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_A_RegisterSelection( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio A register selection */ +{ + pPio->PIO_ASR = flag; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_B_RegisterSelection */ +/** \brief PIO B Register Selection */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_B_RegisterSelection( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio B register selection */ +{ + pPio->PIO_BSR = flag; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_Get_AB_RegisterStatus */ +/** \brief Return PIO Interrupt Status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( /* \return PIO AB Register Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ +{ + return pPio->PIO_ABSR; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsAB_RegisterSet */ +/** \brief Test if PIO AB Register is Set */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_PIO_IsAB_RegisterSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ +{ + return( AT91F_PIO_Get_AB_RegisterStatus( pPio ) & flag ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_OutputWriteEnable */ +/** \brief Output Write Enable PIO */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_OutputWriteEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio output write to be enabled */ +{ + pPio->PIO_OWER = flag; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_OutputWriteDisable */ +/** \brief Output Write Disable PIO */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIO_OutputWriteDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio output write to be disabled */ +{ + pPio->PIO_OWDR = flag; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetOutputWriteStatus */ +/** \brief Return PIO Output Write Status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PIO_GetOutputWriteStatus( /* \return PIO Output Write Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ +{ + return pPio->PIO_OWSR; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsOutputWriteSet */ +/** \brief Test if PIO OutputWrite is Set */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_PIO_IsOutputWriteSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ +{ + return( AT91F_PIO_GetOutputWriteStatus( pPio ) & flag ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetCfgPullup */ +/** \brief Return PIO Configuration Pullup */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_PIO_GetCfgPullup( /* \return PIO Configuration Pullup */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ +{ + return pPio->PIO_PPUSR; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsOutputDataStatusSet */ +/** \brief Test if PIO Output Data Status is Set */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_PIO_IsOutputDataStatusSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ +{ + return( AT91F_PIO_GetOutputDataStatus( pPio ) & flag ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsCfgPullupStatusSet */ +/** \brief Test if PIO Configuration Pullup Status is Set */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_PIO_IsCfgPullupStatusSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ +{ + return( ~AT91F_PIO_GetCfgPullup( pPio ) & flag ); +} + +/* ***************************************************************************** +* SOFTWARE API FOR TWI +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_TWI_EnableIt */ +/** \brief Enable TWI IT */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_TWI_EnableIt( AT91PS_TWI pTWI, /* \arg pointer to a TWI controller */ + unsigned int flag ) /* \arg IT to be enabled */ +{ + /** Write to the IER register */ + pTWI->TWI_IER = flag; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_TWI_DisableIt */ +/** \brief Disable TWI IT */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_TWI_DisableIt( AT91PS_TWI pTWI, /* \arg pointer to a TWI controller */ + unsigned int flag ) /* \arg IT to be disabled */ +{ + /** Write to the IDR register */ + pTWI->TWI_IDR = flag; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_TWI_Configure */ +/** \brief Configure TWI in master mode */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_TWI_Configure( AT91PS_TWI pTWI ) /* \arg pointer to a TWI controller */ +{ + /** Disable interrupts */ + pTWI->TWI_IDR = ( unsigned int ) -1; + + /** Reset peripheral */ + pTWI->TWI_CR = AT91C_TWI_SWRST; + + /** Set Master mode */ + pTWI->TWI_CR = AT91C_TWI_MSEN | AT91C_TWI_SVDIS; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_TWI_GetInterruptMaskStatus */ +/** \brief Return TWI Interrupt Mask Status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( /* \return TWI Interrupt Mask Status */ + AT91PS_TWI pTwi ) /* \arg pointer to a TWI controller */ +{ + return pTwi->TWI_IMR; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_TWI_IsInterruptMasked */ +/** \brief Test if TWI Interrupt is Masked */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_TWI_IsInterruptMasked( AT91PS_TWI pTwi, /* \arg pointer to a TWI controller */ + unsigned int flag ) /* \arg flag to be tested */ +{ + return( AT91F_TWI_GetInterruptMaskStatus( pTwi ) & flag ); +} + +/* ***************************************************************************** +* SOFTWARE API FOR USART +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US_Baudrate */ +/** \brief Calculate the baudrate */ +/** Standard Asynchronous Mode : 8 bits , 1 stop , no parity */ +#define AT91C_US_ASYNC_MODE \ + ( AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +/** Standard External Asynchronous Mode : 8 bits , 1 stop , no parity */ +#define AT91C_US_ASYNC_SCK_MODE \ + ( AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_EXT ) + +/** Standard Synchronous Mode : 8 bits , 1 stop , no parity */ +#define AT91C_US_SYNC_MODE \ + ( AT91C_US_SYNC + \ + AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +/** SCK used Label */ +#define AT91C_US_SCK_USED ( AT91C_US_CKLO | AT91C_US_CLKS_EXT ) + +/** Standard ISO T=0 Mode : 8 bits , 1 stop , parity */ +#define AT91C_US_ISO_READER_MODE \ + ( AT91C_US_USMODE_ISO7816_0 + \ + AT91C_US_CLKS_CLOCK + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_EVEN + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CKLO + \ + AT91C_US_OVER ) + +/** Standard IRDA mode */ +#define AT91C_US_ASYNC_IRDA_MODE \ + ( AT91C_US_USMODE_IRDA + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US_Baudrate */ +/** \brief Calculate baud_value according to the main clock and the baud rate */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_US_Baudrate( const unsigned int main_clock, /* \arg peripheral clock */ + const unsigned int baud_rate ) /* \arg UART baudrate */ +{ + unsigned int baud_value = ( ( main_clock * 10 ) / ( baud_rate * 16 ) ); + + if( ( baud_value % 10 ) >= 5 ) + { + baud_value = ( baud_value / 10 ) + 1; + } + else + { + baud_value /= 10; + } + + return baud_value; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US_SetBaudrate */ +/** \brief Set the baudrate according to the CPU clock */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_US_SetBaudrate( AT91PS_USART pUSART, /* \arg pointer to a USART controller */ + unsigned int mainClock, /* \arg peripheral clock */ + unsigned int speed ) /* \arg UART baudrate */ +{ + /** Define the baud rate divisor register */ + pUSART->US_BRGR = AT91F_US_Baudrate( mainClock, speed ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US_SetTimeguard */ +/** \brief Set USART timeguard */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_US_SetTimeguard( AT91PS_USART pUSART, /* \arg pointer to a USART controller */ + unsigned int timeguard ) /* \arg timeguard value */ +{ + /** Write the Timeguard Register */ + pUSART->US_TTGR = timeguard; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US_EnableIt */ +/** \brief Enable USART IT */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_US_EnableIt( AT91PS_USART pUSART, /* \arg pointer to a USART controller */ + unsigned int flag ) /* \arg IT to be enabled */ +{ + /** Write to the IER register */ + pUSART->US_IER = flag; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US_DisableIt */ +/** \brief Disable USART IT */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_US_DisableIt( AT91PS_USART pUSART, /* \arg pointer to a USART controller */ + unsigned int flag ) /* \arg IT to be disabled */ +{ + /** Write to the IER register */ + pUSART->US_IDR = flag; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US_Configure */ +/** \brief Configure USART */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_US_Configure( AT91PS_USART pUSART, /* \arg pointer to a USART controller */ + unsigned int mainClock, /* \arg peripheral clock */ + unsigned int mode, /* \arg mode Register to be programmed */ + unsigned int baudRate, /* \arg baudrate to be programmed */ + unsigned int timeguard ) /* \arg timeguard to be programmed */ +{ + /** Disable interrupts */ + pUSART->US_IDR = ( unsigned int ) -1; + + /** Reset receiver and transmitter */ + pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS; + + /** Define the baud rate divisor register */ + AT91F_US_SetBaudrate( pUSART, mainClock, baudRate ); + + /** Write the Timeguard Register */ + AT91F_US_SetTimeguard( pUSART, timeguard ); + + /** Clear Transmit and Receive Counters */ + AT91F_PDC_Open( ( AT91PS_PDC ) &( pUSART->US_RPR ) ); + + /** Define the USART mode */ + pUSART->US_MR = mode; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US_EnableRx */ +/** \brief Enable receiving characters */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_US_EnableRx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */ +{ + /** Enable receiver */ + pUSART->US_CR = AT91C_US_RXEN; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US_EnableTx */ +/** \brief Enable sending characters */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_US_EnableTx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */ +{ + /** Enable transmitter */ + pUSART->US_CR = AT91C_US_TXEN; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US_ResetRx */ +/** \brief Reset Receiver and re-enable it */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_US_ResetRx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */ +{ + /** Reset receiver */ + pUSART->US_CR = AT91C_US_RSTRX; + /** Re-Enable receiver */ + pUSART->US_CR = AT91C_US_RXEN; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US_ResetTx */ +/** \brief Reset Transmitter and re-enable it */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_US_ResetTx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */ +{ + /** Reset transmitter */ + pUSART->US_CR = AT91C_US_RSTTX; + /** Enable transmitter */ + pUSART->US_CR = AT91C_US_TXEN; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US_DisableRx */ +/** \brief Disable Receiver */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_US_DisableRx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */ +{ + /** Disable receiver */ + pUSART->US_CR = AT91C_US_RXDIS; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US_DisableTx */ +/** \brief Disable Transmitter */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_US_DisableTx( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */ +{ + /** Disable transmitter */ + pUSART->US_CR = AT91C_US_TXDIS; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US_Close */ +/** \brief Close USART: disable IT disable receiver and transmitter, close PDC */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_US_Close( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */ +{ + /** Reset the baud rate divisor register */ + pUSART->US_BRGR = 0; + + /** Reset the USART mode */ + pUSART->US_MR = 0; + + /** Reset the Timeguard Register */ + pUSART->US_TTGR = 0; + + /** Disable all interrupts */ + pUSART->US_IDR = 0xFFFFFFFF; + + /** Abort the Peripheral Data Transfers */ + AT91F_PDC_Close( ( AT91PS_PDC ) &( pUSART->US_RPR ) ); + + /** Disable receiver and transmitter and stop any activity immediately */ + pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US_TxReady */ +/** \brief Return 1 if a character can be written in US_THR */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_US_TxReady( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */ +{ + return( pUSART->US_CSR & AT91C_US_TXRDY ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US_RxReady */ +/** \brief Return 1 if a character can be read in US_RHR */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_US_RxReady( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */ +{ + return( pUSART->US_CSR & AT91C_US_RXRDY ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US_Error */ +/** \brief Return the error flag */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_US_Error( AT91PS_USART pUSART ) /* \arg pointer to a USART controller */ +{ + return( pUSART->US_CSR & + ( AT91C_US_OVRE | /* Overrun error */ + AT91C_US_FRAME | /* Framing error */ + AT91C_US_PARE ) ); /* Parity error */ +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US_PutChar */ +/** \brief Send a character,does not check if ready to send */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_US_PutChar( AT91PS_USART pUSART, + int character ) +{ + pUSART->US_THR = ( character & 0x1FF ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US_GetChar */ +/** \brief Receive a character,does not check if a character is available */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_US_GetChar( const AT91PS_USART pUSART ) +{ + return( ( pUSART->US_RHR ) & 0x1FF ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US_SendFrame */ +/** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_US_SendFrame( AT91PS_USART pUSART, + char * pBuffer, + unsigned int szBuffer, + char * pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + ( AT91PS_PDC ) &( pUSART->US_RPR ), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US_ReceiveFrame */ +/** \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_US_ReceiveFrame( AT91PS_USART pUSART, + char * pBuffer, + unsigned int szBuffer, + char * pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + ( AT91PS_PDC ) &( pUSART->US_RPR ), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US_SetIrdaFilter */ +/** \brief Set the value of IrDa filter register */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_US_SetIrdaFilter( AT91PS_USART pUSART, + unsigned char value ) +{ + pUSART->US_IF = value; +} + +/* ***************************************************************************** +* SOFTWARE API FOR UDP +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_UDP_EnableIt */ +/** \brief Enable UDP IT */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_UDP_EnableIt( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */ + unsigned int flag ) /* \arg IT to be enabled */ +{ + /** Write to the IER register */ + pUDP->UDP_IER = flag; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_UDP_DisableIt */ +/** \brief Disable UDP IT */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_UDP_DisableIt( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */ + unsigned int flag ) /* \arg IT to be disabled */ +{ + /** Write to the IDR register */ + pUDP->UDP_IDR = flag; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_UDP_SetAddress */ +/** \brief Set UDP functional address */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_UDP_SetAddress( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */ + unsigned char address ) /* \arg new UDP address */ +{ + pUDP->UDP_FADDR = ( AT91C_UDP_FEN | address ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_UDP_EnableEp */ +/** \brief Enable Endpoint */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_UDP_EnableEp( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */ + unsigned int flag ) /* \arg endpoints to be enabled */ +{ + pUDP->UDP_GLBSTATE |= flag; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_UDP_DisableEp */ +/** \brief Enable Endpoint */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_UDP_DisableEp( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */ + unsigned int flag ) /* \arg endpoints to be enabled */ +{ + pUDP->UDP_GLBSTATE &= ~( flag ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_UDP_SetState */ +/** \brief Set UDP Device state */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_UDP_SetState( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */ + unsigned int flag ) /* \arg new UDP address */ +{ + pUDP->UDP_GLBSTATE &= ~( AT91C_UDP_FADDEN | AT91C_UDP_CONFG ); + pUDP->UDP_GLBSTATE |= flag; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_UDP_GetState */ +/** \brief return UDP Device state */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_UDP_GetState( /* \return the UDP device state */ + AT91PS_UDP pUDP ) /* \arg pointer to a UDP controller */ +{ + return( pUDP->UDP_GLBSTATE & ( AT91C_UDP_FADDEN | AT91C_UDP_CONFG ) ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_UDP_ResetEp */ +/** \brief Reset UDP endpoint */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_UDP_ResetEp( /* \return the UDP device state */ + AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */ + unsigned int flag ) /* \arg Endpoints to be reset */ +{ + pUDP->UDP_RSTEP = flag; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_UDP_EpStall */ +/** \brief Endpoint will STALL requests */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_UDP_EpStall( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */ + unsigned char endpoint ) /* \arg endpoint number */ +{ + pUDP->UDP_CSR[ endpoint ] |= AT91C_UDP_FORCESTALL; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_UDP_EpWrite */ +/** \brief Write value in the DPR */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_UDP_EpWrite( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */ + unsigned char endpoint, /* \arg endpoint number */ + unsigned char value ) /* \arg value to be written in the DPR */ +{ + pUDP->UDP_FDR[ endpoint ] = value; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_UDP_EpRead */ +/** \brief Return value from the DPR */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_UDP_EpRead( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */ + unsigned char endpoint ) /* \arg endpoint number */ +{ + return pUDP->UDP_FDR[ endpoint ]; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_UDP_EpEndOfWr */ +/** \brief Notify the UDP that values in DPR are ready to be sent */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_UDP_EpEndOfWr( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */ + unsigned char endpoint ) /* \arg endpoint number */ +{ + pUDP->UDP_CSR[ endpoint ] |= AT91C_UDP_TXPKTRDY; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_UDP_EpClear */ +/** \brief Clear flag in the endpoint CSR register */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_UDP_EpClear( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */ + unsigned char endpoint, /* \arg endpoint number */ + unsigned int flag ) /* \arg flag to be cleared */ +{ + pUDP->UDP_CSR[ endpoint ] &= ~( flag ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_UDP_EpSet */ +/** \brief Set flag in the endpoint CSR register */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_UDP_EpSet( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */ + unsigned char endpoint, /* \arg endpoint number */ + unsigned int flag ) /* \arg flag to be cleared */ +{ + pUDP->UDP_CSR[ endpoint ] |= flag; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_UDP_EpStatus */ +/** \brief Return the endpoint CSR register */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_UDP_EpStatus( AT91PS_UDP pUDP, /* \arg pointer to a UDP controller */ + unsigned char endpoint ) /* \arg endpoint number */ +{ + return pUDP->UDP_CSR[ endpoint ]; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_UDP_GetInterruptMaskStatus */ +/** \brief Return UDP Interrupt Mask Status */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( /* \return UDP Interrupt Mask Status */ + AT91PS_UDP pUdp ) /* \arg pointer to a UDP controller */ +{ + return pUdp->UDP_IMR; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_UDP_IsInterruptMasked */ +/** \brief Test if UDP Interrupt is Masked */ +/**---------------------------------------------------------------------------- */ +__inline int AT91F_UDP_IsInterruptMasked( AT91PS_UDP pUdp, /* \arg pointer to a UDP controller */ + unsigned int flag ) /* \arg flag to be tested */ +{ + return( AT91F_UDP_GetInterruptMaskStatus( pUdp ) & flag ); +} + +/* ***************************************************************************** +* SOFTWARE API FOR AIC +***************************************************************************** */ +#define AT91C_AIC_BRANCH_OPCODE ( ( void ( * )() ) 0xE51FFF20 ) /* ldr, pc, [pc, #-&F20] */ + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_ConfigureIt */ +/** \brief Interrupt Handler Initialization */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_AIC_ConfigureIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id, /* \arg interrupt number to initialize */ + unsigned int priority, /* \arg priority to give to the interrupt */ + unsigned int src_type, /* \arg activation and sense of activation */ + void ( * newHandler )( void ) ) /* \arg address of the interrupt handler */ +{ + unsigned int oldHandler; + unsigned int mask; + + oldHandler = pAic->AIC_SVR[ irq_id ]; + + mask = 0x1 << irq_id; + /** Disable the interrupt on the interrupt controller */ + pAic->AIC_IDCR = mask; + /** Save the interrupt handler routine pointer and the interrupt priority */ + pAic->AIC_SVR[ irq_id ] = ( unsigned int ) newHandler; + /** Store the Source Mode Register */ + pAic->AIC_SMR[ irq_id ] = src_type | priority; + /** Clear the interrupt on the interrupt controller */ + pAic->AIC_ICCR = mask; + + return oldHandler; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_EnableIt */ +/** \brief Enable corresponding IT number */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_AIC_EnableIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg interrupt number to initialize */ +{ + /** Enable the interrupt on the interrupt controller */ + pAic->AIC_IECR = 0x1 << irq_id; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_DisableIt */ +/** \brief Disable corresponding IT number */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_AIC_DisableIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg interrupt number to initialize */ +{ + unsigned int mask = 0x1 << irq_id; + + /** Disable the interrupt on the interrupt controller */ + pAic->AIC_IDCR = mask; + /** Clear the interrupt on the Interrupt Controller ( if one is pending ) */ + pAic->AIC_ICCR = mask; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_ClearIt */ +/** \brief Clear corresponding IT number */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_AIC_ClearIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg interrupt number to initialize */ +{ + /** Clear the interrupt on the Interrupt Controller ( if one is pending ) */ + pAic->AIC_ICCR = ( 0x1 << irq_id ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_AcknowledgeIt */ +/** \brief Acknowledge corresponding IT number */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_AIC_AcknowledgeIt( AT91PS_AIC pAic ) /* \arg pointer to the AIC registers */ +{ + pAic->AIC_EOICR = pAic->AIC_EOICR; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_SetExceptionVector */ +/** \brief Configure vector handler */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_AIC_SetExceptionVector( unsigned int * pVector, /* \arg pointer to the AIC registers */ + void ( * Handler )() ) /* \arg Interrupt Handler */ +{ + unsigned int oldVector = *pVector; + + if( ( unsigned int ) Handler == ( unsigned int ) AT91C_AIC_BRANCH_OPCODE ) + { + *pVector = ( unsigned int ) AT91C_AIC_BRANCH_OPCODE; + } + else + { + *pVector = ( ( ( ( ( unsigned int ) Handler ) - ( ( unsigned int ) pVector ) - 0x8 ) >> 2 ) & 0x00FFFFFF ) | 0xEA000000; + } + + return oldVector; +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_Trig */ +/** \brief Trig an IT */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_AIC_Trig( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg interrupt number */ +{ + pAic->AIC_ISCR = ( 0x1 << irq_id ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_IsActive */ +/** \brief Test if an IT is active */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_AIC_IsActive( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg Interrupt Number */ +{ + return( pAic->AIC_ISR & ( 0x1 << irq_id ) ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_IsPending */ +/** \brief Test if an IT is pending */ +/**---------------------------------------------------------------------------- */ +__inline unsigned int AT91F_AIC_IsPending( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg Interrupt Number */ +{ + return( pAic->AIC_IPR & ( 0x1 << irq_id ) ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_Open */ +/** \brief Set exception vectors and AIC registers to default values */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_AIC_Open( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + void ( * IrqHandler )(), /* \arg Default IRQ vector exception */ + void ( * FiqHandler )(), /* \arg Default FIQ vector exception */ + void ( * DefaultHandler )(), /* \arg Default Handler set in ISR */ + void ( * SpuriousHandler )(), /* \arg Default Spurious Handler */ + unsigned int protectMode ) /* \arg Debug Control Register */ +{ + int i; + + /* Disable all interrupts and set IVR to the default handler */ + for( i = 0; i < 32; ++i ) + { + AT91F_AIC_DisableIt( pAic, i ); + AT91F_AIC_ConfigureIt( pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, DefaultHandler ); + } + + /* Set the IRQ exception vector */ + AT91F_AIC_SetExceptionVector( ( unsigned int * ) 0x18, IrqHandler ); + /* Set the Fast Interrupt exception vector */ + AT91F_AIC_SetExceptionVector( ( unsigned int * ) 0x1C, FiqHandler ); + + pAic->AIC_SPU = ( unsigned int ) SpuriousHandler; + pAic->AIC_DCR = protectMode; +} +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_MC_CfgPMC */ +/** \brief Enable Peripheral clock in PMC for MC */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_MC_CfgPMC( void ) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, /* PIO controller base address */ + ( ( unsigned int ) 1 << AT91C_ID_SYS ) ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_DBGU_CfgPMC */ +/** \brief Enable Peripheral clock in PMC for DBGU */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_DBGU_CfgPMC( void ) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, /* PIO controller base address */ + ( ( unsigned int ) 1 << AT91C_ID_SYS ) ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_DBGU_CfgPIO */ +/** \brief Configure PIO controllers to drive DBGU signals */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_DBGU_CfgPIO( void ) +{ + /* Configure PIO controllers to periph mode */ + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, /* PIO controller base address */ + ( ( unsigned int ) AT91C_PA10_DTXD ) | + ( ( unsigned int ) AT91C_PA9_DRXD ), /* Peripheral A */ + 0 ); /* Peripheral B */ +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PWMC_CH3_CfgPIO */ +/** \brief Configure PIO controllers to drive PWMC_CH3 signals */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PWMC_CH3_CfgPIO( void ) +{ + /* Configure PIO controllers to periph mode */ + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, /* PIO controller base address */ + 0, /* Peripheral A */ + ( ( unsigned int ) AT91C_PA14_PWM3 ) | + ( ( unsigned int ) AT91C_PA7_PWM3 ) ); /* Peripheral B */ +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PWMC_CH2_CfgPIO */ +/** \brief Configure PIO controllers to drive PWMC_CH2 signals */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PWMC_CH2_CfgPIO( void ) +{ + /* Configure PIO controllers to periph mode */ + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, /* PIO controller base address */ + ( ( unsigned int ) AT91C_PA2_PWM2 ), /* Peripheral A */ + ( ( unsigned int ) AT91C_PA25_PWM2 ) | + ( ( unsigned int ) AT91C_PA13_PWM2 ) ); /* Peripheral B */ +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PWMC_CH1_CfgPIO */ +/** \brief Configure PIO controllers to drive PWMC_CH1 signals */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PWMC_CH1_CfgPIO( void ) +{ + /* Configure PIO controllers to periph mode */ + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, /* PIO controller base address */ + ( ( unsigned int ) AT91C_PA1_PWM1 ), /* Peripheral A */ + ( ( unsigned int ) AT91C_PA24_PWM1 ) | + ( ( unsigned int ) AT91C_PA12_PWM1 ) ); /* Peripheral B */ +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PWMC_CH0_CfgPIO */ +/** \brief Configure PIO controllers to drive PWMC_CH0 signals */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PWMC_CH0_CfgPIO( void ) +{ + /* Configure PIO controllers to periph mode */ + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, /* PIO controller base address */ + ( ( unsigned int ) AT91C_PA0_PWM0 ), /* Peripheral A */ + ( ( unsigned int ) AT91C_PA23_PWM0 ) | + ( ( unsigned int ) AT91C_PA11_PWM0 ) ); /* Peripheral B */ +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SSC_CfgPMC */ +/** \brief Enable Peripheral clock in PMC for SSC */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_SSC_CfgPMC( void ) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, /* PIO controller base address */ + ( ( unsigned int ) 1 << AT91C_ID_SSC ) ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SSC_CfgPIO */ +/** \brief Configure PIO controllers to drive SSC signals */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_SSC_CfgPIO( void ) +{ + /* Configure PIO controllers to periph mode */ + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, /* PIO controller base address */ + ( ( unsigned int ) AT91C_PA17_TD ) | + ( ( unsigned int ) AT91C_PA15_TF ) | + ( ( unsigned int ) AT91C_PA19_RK ) | + ( ( unsigned int ) AT91C_PA18_RD ) | + ( ( unsigned int ) AT91C_PA20_RF ) | + ( ( unsigned int ) AT91C_PA16_TK ), /* Peripheral A */ + 0 ); /* Peripheral B */ +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SPI_CfgPMC */ +/** \brief Enable Peripheral clock in PMC for SPI */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_SPI_CfgPMC( void ) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, /* PIO controller base address */ + ( ( unsigned int ) 1 << AT91C_ID_SPI ) ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_SPI_CfgPIO */ +/** \brief Configure PIO controllers to drive SPI signals */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_SPI_CfgPIO( void ) +{ + /* Configure PIO controllers to periph mode */ + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, /* PIO controller base address */ + ( ( unsigned int ) AT91C_PA11_NPCS0 ) | + ( ( unsigned int ) AT91C_PA13_MOSI ) | + ( ( unsigned int ) AT91C_PA31_NPCS1 ) | + ( ( unsigned int ) AT91C_PA12_MISO ) | + ( ( unsigned int ) AT91C_PA14_SPCK ), /* Peripheral A */ + ( ( unsigned int ) AT91C_PA9_NPCS1 ) | + ( ( unsigned int ) AT91C_PA30_NPCS2 ) | + ( ( unsigned int ) AT91C_PA10_NPCS2 ) | + ( ( unsigned int ) AT91C_PA22_NPCS3 ) | + ( ( unsigned int ) AT91C_PA3_NPCS3 ) | + ( ( unsigned int ) AT91C_PA5_NPCS3 ) ); /* Peripheral B */ +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PWMC_CfgPMC */ +/** \brief Enable Peripheral clock in PMC for PWMC */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PWMC_CfgPMC( void ) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, /* PIO controller base address */ + ( ( unsigned int ) 1 << AT91C_ID_PWMC ) ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_TC2_CfgPMC */ +/** \brief Enable Peripheral clock in PMC for TC2 */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_TC2_CfgPMC( void ) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, /* PIO controller base address */ + ( ( unsigned int ) 1 << AT91C_ID_TC2 ) ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_TC2_CfgPIO */ +/** \brief Configure PIO controllers to drive TC2 signals */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_TC2_CfgPIO( void ) +{ + /* Configure PIO controllers to periph mode */ + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, /* PIO controller base address */ + 0, /* Peripheral A */ + ( ( unsigned int ) AT91C_PA26_TIOA2 ) | + ( ( unsigned int ) AT91C_PA27_TIOB2 ) | + ( ( unsigned int ) AT91C_PA29_TCLK2 ) ); /* Peripheral B */ +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_TC1_CfgPMC */ +/** \brief Enable Peripheral clock in PMC for TC1 */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_TC1_CfgPMC( void ) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, /* PIO controller base address */ + ( ( unsigned int ) 1 << AT91C_ID_TC1 ) ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_TC1_CfgPIO */ +/** \brief Configure PIO controllers to drive TC1 signals */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_TC1_CfgPIO( void ) +{ + /* Configure PIO controllers to periph mode */ + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, /* PIO controller base address */ + 0, /* Peripheral A */ + ( ( unsigned int ) AT91C_PA15_TIOA1 ) | + ( ( unsigned int ) AT91C_PA16_TIOB1 ) | + ( ( unsigned int ) AT91C_PA28_TCLK1 ) ); /* Peripheral B */ +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_TC0_CfgPMC */ +/** \brief Enable Peripheral clock in PMC for TC0 */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_TC0_CfgPMC( void ) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, /* PIO controller base address */ + ( ( unsigned int ) 1 << AT91C_ID_TC0 ) ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_TC0_CfgPIO */ +/** \brief Configure PIO controllers to drive TC0 signals */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_TC0_CfgPIO( void ) +{ + /* Configure PIO controllers to periph mode */ + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, /* PIO controller base address */ + 0, /* Peripheral A */ + ( ( unsigned int ) AT91C_PA0_TIOA0 ) | + ( ( unsigned int ) AT91C_PA1_TIOB0 ) | + ( ( unsigned int ) AT91C_PA4_TCLK0 ) ); /* Peripheral B */ +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_CfgPMC */ +/** \brief Enable Peripheral clock in PMC for PMC */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PMC_CfgPMC( void ) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, /* PIO controller base address */ + ( ( unsigned int ) 1 << AT91C_ID_SYS ) ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_CfgPIO */ +/** \brief Configure PIO controllers to drive PMC signals */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PMC_CfgPIO( void ) +{ + /* Configure PIO controllers to periph mode */ + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, /* PIO controller base address */ + 0, /* Peripheral A */ + ( ( unsigned int ) AT91C_PA17_PCK1 ) | + ( ( unsigned int ) AT91C_PA21_PCK1 ) | + ( ( unsigned int ) AT91C_PA31_PCK2 ) | + ( ( unsigned int ) AT91C_PA18_PCK2 ) | + ( ( unsigned int ) AT91C_PA6_PCK0 ) ); /* Peripheral B */ +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_CfgPMC */ +/** \brief Enable Peripheral clock in PMC for ADC */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_ADC_CfgPMC( void ) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, /* PIO controller base address */ + ( ( unsigned int ) 1 << AT91C_ID_ADC ) ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_ADC_CfgPIO */ +/** \brief Configure PIO controllers to drive ADC signals */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_ADC_CfgPIO( void ) +{ + /* Configure PIO controllers to periph mode */ + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, /* PIO controller base address */ + 0, /* Peripheral A */ + ( ( unsigned int ) AT91C_PA8_ADTRG ) ); /* Peripheral B */ +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIOA_CfgPMC */ +/** \brief Enable Peripheral clock in PMC for PIOA */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_PIOA_CfgPMC( void ) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, /* PIO controller base address */ + ( ( unsigned int ) 1 << AT91C_ID_PIOA ) ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_TWI_CfgPMC */ +/** \brief Enable Peripheral clock in PMC for TWI */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_TWI_CfgPMC( void ) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, /* PIO controller base address */ + ( ( unsigned int ) 1 << AT91C_ID_TWI ) ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_TWI_CfgPIO */ +/** \brief Configure PIO controllers to drive TWI signals */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_TWI_CfgPIO( void ) +{ + /* Configure PIO controllers to periph mode */ + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, /* PIO controller base address */ + ( ( unsigned int ) AT91C_PA3_TWD ) | + ( ( unsigned int ) AT91C_PA4_TWCK ), /* Peripheral A */ + 0 ); /* Peripheral B */ +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US1_CfgPMC */ +/** \brief Enable Peripheral clock in PMC for US1 */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_US1_CfgPMC( void ) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, /* PIO controller base address */ + ( ( unsigned int ) 1 << AT91C_ID_US1 ) ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US1_CfgPIO */ +/** \brief Configure PIO controllers to drive US1 signals */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_US1_CfgPIO( void ) +{ + /* Configure PIO controllers to periph mode */ + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, /* PIO controller base address */ + ( ( unsigned int ) AT91C_PA21_RXD1 ) | + ( ( unsigned int ) AT91C_PA27_DTR1 ) | + ( ( unsigned int ) AT91C_PA26_DCD1 ) | + ( ( unsigned int ) AT91C_PA22_TXD1 ) | + ( ( unsigned int ) AT91C_PA24_RTS1 ) | + ( ( unsigned int ) AT91C_PA23_SCK1 ) | + ( ( unsigned int ) AT91C_PA28_DSR1 ) | + ( ( unsigned int ) AT91C_PA29_RI1 ) | + ( ( unsigned int ) AT91C_PA25_CTS1 ), /* Peripheral A */ + 0 ); /* Peripheral B */ +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US0_CfgPMC */ +/** \brief Enable Peripheral clock in PMC for US0 */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_US0_CfgPMC( void ) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, /* PIO controller base address */ + ( ( unsigned int ) 1 << AT91C_ID_US0 ) ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_US0_CfgPIO */ +/** \brief Configure PIO controllers to drive US0 signals */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_US0_CfgPIO( void ) +{ + /* Configure PIO controllers to periph mode */ + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, /* PIO controller base address */ + ( ( unsigned int ) AT91C_PA5_RXD0 ) | + ( ( unsigned int ) AT91C_PA6_TXD0 ) | + ( ( unsigned int ) AT91C_PA7_RTS0 ) | + ( ( unsigned int ) AT91C_PA8_CTS0 ), /* Peripheral A */ + ( ( unsigned int ) AT91C_PA2_SCK0 ) ); /* Peripheral B */ +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_UDP_CfgPMC */ +/** \brief Enable Peripheral clock in PMC for UDP */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_UDP_CfgPMC( void ) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, /* PIO controller base address */ + ( ( unsigned int ) 1 << AT91C_ID_UDP ) ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_CfgPMC */ +/** \brief Enable Peripheral clock in PMC for AIC */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_AIC_CfgPMC( void ) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, /* PIO controller base address */ + ( ( unsigned int ) 1 << AT91C_ID_IRQ0 ) | + ( ( unsigned int ) 1 << AT91C_ID_FIQ ) | + ( ( unsigned int ) 1 << AT91C_ID_IRQ1 ) ); +} + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_CfgPIO */ +/** \brief Configure PIO controllers to drive AIC signals */ +/**---------------------------------------------------------------------------- */ +__inline void AT91F_AIC_CfgPIO( void ) +{ + /* Configure PIO controllers to periph mode */ + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, /* PIO controller base address */ + ( ( unsigned int ) AT91C_PA30_IRQ1 ), /* Peripheral A */ + ( ( unsigned int ) AT91C_PA20_IRQ0 ) | + ( ( unsigned int ) AT91C_PA19_FIQ ) ); /* Peripheral B */ +} + +#endif // lib_AT91SAM7S64_H diff --git a/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h b/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h new file mode 100644 index 000000000..4fc975894 --- /dev/null +++ b/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h @@ -0,0 +1,1396 @@ +/** ---------------------------------------------------------------------------- */ +/** ATMEL Microcontroller Software Support - ROUSSET - */ +/** ---------------------------------------------------------------------------- */ +/** DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/** MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/** DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/** LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/** OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/** LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/** NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/** EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/** ---------------------------------------------------------------------------- */ +/** File Name : lib_AT91SAM7X128.h */ +/** Object : AT91SAM7X128 inlined functions */ +/** Generated : AT91 SW Application Group 05/20/2005 (16:22:23) */ +/** */ +/** CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// */ +/** CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005// */ +/** CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005// */ +/** CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004// */ +/** CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// */ +/** CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004// */ +/** CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// */ +/** CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003// */ +/** CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004// */ +/** CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005// */ +/** CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005// */ +/** CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// */ +/** CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// */ +/** CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004// */ +/** CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005// */ +/** CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005// */ +/** CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// */ +/** CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004// */ +/** CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// */ +/** CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003// */ +/** CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// */ +/** CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002// */ +/** ---------------------------------------------------------------------------- */ + +#ifndef lib_AT91SAM7X128_H + #define lib_AT91SAM7X128_H + +/* ***************************************************************************** +* SOFTWARE API FOR AIC +***************************************************************************** */ + #define AT91C_AIC_BRANCH_OPCODE ( ( void ( * )() ) 0xE51FFF20 ) /* ldr, pc, [pc, #-&F20] */ + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_ConfigureIt */ +/** \brief Interrupt Handler Initialization */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_AIC_ConfigureIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id, /* \arg interrupt number to initialize */ + unsigned int priority, /* \arg priority to give to the interrupt */ + unsigned int src_type, /* \arg activation and sense of activation */ + void ( * newHandler )( void ) ) /* \arg address of the interrupt handler */ + { + unsigned int oldHandler; + unsigned int mask; + + oldHandler = pAic->AIC_SVR[ irq_id ]; + + mask = 0x1 << irq_id; + /** Disable the interrupt on the interrupt controller */ + pAic->AIC_IDCR = mask; + /** Save the interrupt handler routine pointer and the interrupt priority */ + pAic->AIC_SVR[ irq_id ] = ( unsigned int ) newHandler; + /** Store the Source Mode Register */ + pAic->AIC_SMR[ irq_id ] = src_type | priority; + /** Clear the interrupt on the interrupt controller */ + pAic->AIC_ICCR = mask; + + return oldHandler; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_EnableIt */ +/** \brief Enable corresponding IT number */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_AIC_EnableIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg interrupt number to initialize */ + { + /** Enable the interrupt on the interrupt controller */ + pAic->AIC_IECR = 0x1 << irq_id; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_DisableIt */ +/** \brief Disable corresponding IT number */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_AIC_DisableIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg interrupt number to initialize */ + { + unsigned int mask = 0x1 << irq_id; + + /** Disable the interrupt on the interrupt controller */ + pAic->AIC_IDCR = mask; + /** Clear the interrupt on the Interrupt Controller ( if one is pending ) */ + pAic->AIC_ICCR = mask; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_ClearIt */ +/** \brief Clear corresponding IT number */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_AIC_ClearIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg interrupt number to initialize */ + { + /** Clear the interrupt on the Interrupt Controller ( if one is pending ) */ + pAic->AIC_ICCR = ( 0x1 << irq_id ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_AcknowledgeIt */ +/** \brief Acknowledge corresponding IT number */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_AIC_AcknowledgeIt( AT91PS_AIC pAic ) /* \arg pointer to the AIC registers */ + { + pAic->AIC_EOICR = pAic->AIC_EOICR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_SetExceptionVector */ +/** \brief Configure vector handler */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_AIC_SetExceptionVector( unsigned int * pVector, /* \arg pointer to the AIC registers */ + void ( * Handler )() ) /* \arg Interrupt Handler */ + { + unsigned int oldVector = *pVector; + + if( ( unsigned int ) Handler == ( unsigned int ) AT91C_AIC_BRANCH_OPCODE ) + { + *pVector = ( unsigned int ) AT91C_AIC_BRANCH_OPCODE; + } + else + { + *pVector = ( ( ( ( ( unsigned int ) Handler ) - ( ( unsigned int ) pVector ) - 0x8 ) >> 2 ) & 0x00FFFFFF ) | 0xEA000000; + } + + return oldVector; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_Trig */ +/** \brief Trig an IT */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_AIC_Trig( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg interrupt number */ + { + pAic->AIC_ISCR = ( 0x1 << irq_id ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_IsActive */ +/** \brief Test if an IT is active */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_AIC_IsActive( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg Interrupt Number */ + { + return( pAic->AIC_ISR & ( 0x1 << irq_id ) ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_IsPending */ +/** \brief Test if an IT is pending */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_AIC_IsPending( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg Interrupt Number */ + { + return( pAic->AIC_IPR & ( 0x1 << irq_id ) ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_Open */ +/** \brief Set exception vectors and AIC registers to default values */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_AIC_Open( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + void ( * IrqHandler )(), /* \arg Default IRQ vector exception */ + void ( * FiqHandler )(), /* \arg Default FIQ vector exception */ + void ( * DefaultHandler )(), /* \arg Default Handler set in ISR */ + void ( * SpuriousHandler )(), /* \arg Default Spurious Handler */ + unsigned int protectMode ) /* \arg Debug Control Register */ + { + int i; + + /* Disable all interrupts and set IVR to the default handler */ + for( i = 0; i < 32; ++i ) + { + AT91F_AIC_DisableIt( pAic, i ); + AT91F_AIC_ConfigureIt( pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler ); + } + + /* Set the IRQ exception vector */ + AT91F_AIC_SetExceptionVector( ( unsigned int * ) 0x18, IrqHandler ); + /* Set the Fast Interrupt exception vector */ + AT91F_AIC_SetExceptionVector( ( unsigned int * ) 0x1C, FiqHandler ); + + pAic->AIC_SPU = ( unsigned int ) SpuriousHandler; + pAic->AIC_DCR = protectMode; + } + +/* ***************************************************************************** +* SOFTWARE API FOR PDC +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_SetNextRx */ +/** \brief Set the next receive transfer descriptor */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_SetNextRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ + char * address, /* \arg address to the next block to be received */ + unsigned int bytes ) /* \arg number of bytes to be received */ + { + pPDC->PDC_RNPR = ( unsigned int ) address; + pPDC->PDC_RNCR = bytes; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_SetNextTx */ +/** \brief Set the next transmit transfer descriptor */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_SetNextTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ + char * address, /* \arg address to the next block to be transmitted */ + unsigned int bytes ) /* \arg number of bytes to be transmitted */ + { + pPDC->PDC_TNPR = ( unsigned int ) address; + pPDC->PDC_TNCR = bytes; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_SetRx */ +/** \brief Set the receive transfer descriptor */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_SetRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ + char * address, /* \arg address to the next block to be received */ + unsigned int bytes ) /* \arg number of bytes to be received */ + { + pPDC->PDC_RPR = ( unsigned int ) address; + pPDC->PDC_RCR = bytes; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_SetTx */ +/** \brief Set the transmit transfer descriptor */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_SetTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ + char * address, /* \arg address to the next block to be transmitted */ + unsigned int bytes ) /* \arg number of bytes to be transmitted */ + { + pPDC->PDC_TPR = ( unsigned int ) address; + pPDC->PDC_TCR = bytes; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_EnableTx */ +/** \brief Enable transmit */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_EnableTx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + pPDC->PDC_PTCR = AT91C_PDC_TXTEN; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_EnableRx */ +/** \brief Enable receive */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_EnableRx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + pPDC->PDC_PTCR = AT91C_PDC_RXTEN; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_DisableTx */ +/** \brief Disable transmit */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_DisableTx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_DisableRx */ +/** \brief Disable receive */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_DisableRx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_IsTxEmpty */ +/** \brief Test if the current transfer descriptor has been sent */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PDC_IsTxEmpty( /* \return return 1 if transfer is complete */ + AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + return !( pPDC->PDC_TCR ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_IsNextTxEmpty */ +/** \brief Test if the next transfer descriptor has been moved to the current td */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PDC_IsNextTxEmpty( /* \return return 1 if transfer is complete */ + AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + return !( pPDC->PDC_TNCR ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_IsRxEmpty */ +/** \brief Test if the current transfer descriptor has been filled */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PDC_IsRxEmpty( /* \return return 1 if transfer is complete */ + AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + return !( pPDC->PDC_RCR ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_IsNextRxEmpty */ +/** \brief Test if the next transfer descriptor has been moved to the current td */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PDC_IsNextRxEmpty( /* \return return 1 if transfer is complete */ + AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + return !( pPDC->PDC_RNCR ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_Open */ +/** \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_Open( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + /** Disable the RX and TX PDC transfer requests */ + AT91F_PDC_DisableRx( pPDC ); + AT91F_PDC_DisableTx( pPDC ); + + /** Reset all Counter register Next buffer first */ + AT91F_PDC_SetNextTx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetNextRx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetTx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetRx( pPDC, ( char * ) 0, 0 ); + + /** Enable the RX and TX PDC transfer requests */ + AT91F_PDC_EnableRx( pPDC ); + AT91F_PDC_EnableTx( pPDC ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_Close */ +/** \brief Close PDC: disable TX and RX reset transfer descriptors */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_Close( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + /** Disable the RX and TX PDC transfer requests */ + AT91F_PDC_DisableRx( pPDC ); + AT91F_PDC_DisableTx( pPDC ); + + /** Reset all Counter register Next buffer first */ + AT91F_PDC_SetNextTx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetNextRx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetTx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetRx( pPDC, ( char * ) 0, 0 ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_SendFrame */ +/** \brief Close PDC: disable TX and RX reset transfer descriptors */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PDC_SendFrame( AT91PS_PDC pPDC, + char * pBuffer, + unsigned int szBuffer, + char * pNextBuffer, + unsigned int szNextBuffer ) + { + if( AT91F_PDC_IsTxEmpty( pPDC ) ) + { + /** Buffer and next buffer can be initialized */ + AT91F_PDC_SetTx( pPDC, pBuffer, szBuffer ); + AT91F_PDC_SetNextTx( pPDC, pNextBuffer, szNextBuffer ); + return 2; + } + else if( AT91F_PDC_IsNextTxEmpty( pPDC ) ) + { + /** Only one buffer can be initialized */ + AT91F_PDC_SetNextTx( pPDC, pBuffer, szBuffer ); + return 1; + } + else + { + /** All buffer are in use... */ + return 0; + } + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_ReceiveFrame */ +/** \brief Close PDC: disable TX and RX reset transfer descriptors */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PDC_ReceiveFrame( AT91PS_PDC pPDC, + char * pBuffer, + unsigned int szBuffer, + char * pNextBuffer, + unsigned int szNextBuffer ) + { + if( AT91F_PDC_IsRxEmpty( pPDC ) ) + { + /** Buffer and next buffer can be initialized */ + AT91F_PDC_SetRx( pPDC, pBuffer, szBuffer ); + AT91F_PDC_SetNextRx( pPDC, pNextBuffer, szNextBuffer ); + return 2; + } + else if( AT91F_PDC_IsNextRxEmpty( pPDC ) ) + { + /** Only one buffer can be initialized */ + AT91F_PDC_SetNextRx( pPDC, pBuffer, szBuffer ); + return 1; + } + else + { + /** All buffer are in use... */ + return 0; + } + } + +/* ***************************************************************************** +* SOFTWARE API FOR DBGU +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_DBGU_InterruptEnable */ +/** \brief Enable DBGU Interrupt */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_DBGU_InterruptEnable( AT91PS_DBGU pDbgu, /* \arg pointer to a DBGU controller */ + unsigned int flag ) /* \arg dbgu interrupt to be enabled */ + { + pDbgu->DBGU_IER = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_DBGU_InterruptDisable */ +/** \brief Disable DBGU Interrupt */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_DBGU_InterruptDisable( AT91PS_DBGU pDbgu, /* \arg pointer to a DBGU controller */ + unsigned int flag ) /* \arg dbgu interrupt to be disabled */ + { + pDbgu->DBGU_IDR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_DBGU_GetInterruptMaskStatus */ +/** \brief Return DBGU Interrupt Mask Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( /* \return DBGU Interrupt Mask Status */ + AT91PS_DBGU pDbgu ) /* \arg pointer to a DBGU controller */ + { + return pDbgu->DBGU_IMR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_DBGU_IsInterruptMasked */ +/** \brief Test if DBGU Interrupt is Masked */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_DBGU_IsInterruptMasked( AT91PS_DBGU pDbgu, /* \arg pointer to a DBGU controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_DBGU_GetInterruptMaskStatus( pDbgu ) & flag ); + } + +/* ***************************************************************************** +* SOFTWARE API FOR PIO +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgPeriph */ +/** \brief Enable pins to be derived by peripheral */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_CfgPeriph( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int periphAEnable, /* \arg PERIPH A to enable */ + unsigned int periphBEnable ) /* \arg PERIPH B to enable */ + + { + pPio->PIO_ASR = periphAEnable; + pPio->PIO_BSR = periphBEnable; + pPio->PIO_PDR = ( periphAEnable | periphBEnable ); /* Set in Periph mode */ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgOutput */ +/** \brief Enable PIO in output mode */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_CfgOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int pioEnable ) /* \arg PIO to be enabled */ + { + pPio->PIO_PER = pioEnable; /* Set in PIO mode */ + pPio->PIO_OER = pioEnable; /* Configure in Output */ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgInput */ +/** \brief Enable PIO in input mode */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_CfgInput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int inputEnable ) /* \arg PIO to be enabled */ + { + /* Disable output */ + pPio->PIO_ODR = inputEnable; + pPio->PIO_PER = inputEnable; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgOpendrain */ +/** \brief Configure PIO in open drain */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_CfgOpendrain( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int multiDrvEnable ) /* \arg pio to be configured in open drain */ + { + /* Configure the multi-drive option */ + pPio->PIO_MDDR = ~multiDrvEnable; + pPio->PIO_MDER = multiDrvEnable; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgPullup */ +/** \brief Enable pullup on PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_CfgPullup( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int pullupEnable ) /* \arg enable pullup on PIO */ + { + /* Connect or not Pullup */ + pPio->PIO_PPUDR = ~pullupEnable; + pPio->PIO_PPUER = pullupEnable; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgDirectDrive */ +/** \brief Enable direct drive on PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_CfgDirectDrive( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int directDrive ) /* \arg PIO to be configured with direct drive */ + + { + /* Configure the Direct Drive */ + pPio->PIO_OWDR = ~directDrive; + pPio->PIO_OWER = directDrive; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgInputFilter */ +/** \brief Enable input filter on input PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_CfgInputFilter( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int inputFilter ) /* \arg PIO to be configured with input filter */ + + { + /* Configure the Direct Drive */ + pPio->PIO_IFDR = ~inputFilter; + pPio->PIO_IFER = inputFilter; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetInput */ +/** \brief Return PIO input value */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetInput( /* \return PIO input */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { + return pPio->PIO_PDSR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsInputSet */ +/** \brief Test if PIO is input flag is active */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsInputSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetInput( pPio ) & flag ); + } + + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_SetOutput */ +/** \brief Set to 1 output PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_SetOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg output to be set */ + { + pPio->PIO_SODR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_ClearOutput */ +/** \brief Set to 0 output PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_ClearOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg output to be cleared */ + { + pPio->PIO_CODR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_ForceOutput */ +/** \brief Force output when Direct drive option is enabled */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_ForceOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg output to be forced */ + { + pPio->PIO_ODSR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_Enable */ +/** \brief Enable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_Enable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio to be enabled */ + { + pPio->PIO_PER = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_Disable */ +/** \brief Disable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_Disable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio to be disabled */ + { + pPio->PIO_PDR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetStatus */ +/** \brief Return PIO Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetStatus( /* \return PIO Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { + return pPio->PIO_PSR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsSet */ +/** \brief Test if PIO is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_OutputEnable */ +/** \brief Output Enable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_OutputEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio output to be enabled */ + { + pPio->PIO_OER = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_OutputDisable */ +/** \brief Output Enable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_OutputDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio output to be disabled */ + { + pPio->PIO_ODR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetOutputStatus */ +/** \brief Return PIO Output Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetOutputStatus( /* \return PIO Output Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { + return pPio->PIO_OSR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsOuputSet */ +/** \brief Test if PIO Output is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsOutputSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetOutputStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_InputFilterEnable */ +/** \brief Input Filter Enable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_InputFilterEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio input filter to be enabled */ + { + pPio->PIO_IFER = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_InputFilterDisable */ +/** \brief Input Filter Disable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_InputFilterDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio input filter to be disabled */ + { + pPio->PIO_IFDR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetInputFilterStatus */ +/** \brief Return PIO Input Filter Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetInputFilterStatus( /* \return PIO Input Filter Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { + return pPio->PIO_IFSR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsInputFilterSet */ +/** \brief Test if PIO Input filter is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsInputFilterSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetInputFilterStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetOutputDataStatus */ +/** \brief Return PIO Output Data Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetOutputDataStatus( /* \return PIO Output Data Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { + return pPio->PIO_ODSR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_InterruptEnable */ +/** \brief Enable PIO Interrupt */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_InterruptEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio interrupt to be enabled */ + { + pPio->PIO_IER = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_InterruptDisable */ +/** \brief Disable PIO Interrupt */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_InterruptDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio interrupt to be disabled */ + { + pPio->PIO_IDR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetInterruptMaskStatus */ +/** \brief Return PIO Interrupt Mask Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetInterruptMaskStatus( /* \return PIO Interrupt Mask Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { + return pPio->PIO_IMR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetInterruptStatus */ +/** \brief Return PIO Interrupt Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetInterruptStatus( /* \return PIO Interrupt Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { + return pPio->PIO_ISR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsInterruptMasked */ +/** \brief Test if PIO Interrupt is Masked */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsInterruptMasked( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetInterruptMaskStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsInterruptSet */ +/** \brief Test if PIO Interrupt is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsInterruptSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetInterruptStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_MultiDriverEnable */ +/** \brief Multi Driver Enable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_MultiDriverEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio to be enabled */ + { + pPio->PIO_MDER = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_MultiDriverDisable */ +/** \brief Multi Driver Disable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_MultiDriverDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio to be disabled */ + { + pPio->PIO_MDDR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetMultiDriverStatus */ +/** \brief Return PIO Multi Driver Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetMultiDriverStatus( /* \return PIO Multi Driver Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { + return pPio->PIO_MDSR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsMultiDriverSet */ +/** \brief Test if PIO MultiDriver is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsMultiDriverSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetMultiDriverStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_A_RegisterSelection */ +/** \brief PIO A Register Selection */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_A_RegisterSelection( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio A register selection */ + { + pPio->PIO_ASR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_B_RegisterSelection */ +/** \brief PIO B Register Selection */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_B_RegisterSelection( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio B register selection */ + { + pPio->PIO_BSR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_Get_AB_RegisterStatus */ +/** \brief Return PIO Interrupt Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( /* \return PIO AB Register Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { + return pPio->PIO_ABSR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsAB_RegisterSet */ +/** \brief Test if PIO AB Register is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsAB_RegisterSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_Get_AB_RegisterStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_OutputWriteEnable */ +/** \brief Output Write Enable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_OutputWriteEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio output write to be enabled */ + { + pPio->PIO_OWER = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_OutputWriteDisable */ +/** \brief Output Write Disable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_OutputWriteDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio output write to be disabled */ + { + pPio->PIO_OWDR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetOutputWriteStatus */ +/** \brief Return PIO Output Write Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetOutputWriteStatus( /* \return PIO Output Write Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { + return pPio->PIO_OWSR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsOutputWriteSet */ +/** \brief Test if PIO OutputWrite is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsOutputWriteSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetOutputWriteStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetCfgPullup */ +/** \brief Return PIO Configuration Pullup */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetCfgPullup( /* \return PIO Configuration Pullup */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { + return pPio->PIO_PPUSR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsOutputDataStatusSet */ +/** \brief Test if PIO Output Data Status is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsOutputDataStatusSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetOutputDataStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsCfgPullupStatusSet */ +/** \brief Test if PIO Configuration Pullup Status is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsCfgPullupStatusSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( ~AT91F_PIO_GetCfgPullup( pPio ) & flag ); + } + +/* ***************************************************************************** +* SOFTWARE API FOR PMC +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_CfgSysClkEnableReg */ +/** \brief Configure the System Clock Enable Register of the PMC controller */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_CfgSysClkEnableReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int mode ) + { + /** Write to the SCER register */ + pPMC->PMC_SCER = mode; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_CfgSysClkDisableReg */ +/** \brief Configure the System Clock Disable Register of the PMC controller */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_CfgSysClkDisableReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int mode ) + { + /** Write to the SCDR register */ + pPMC->PMC_SCDR = mode; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_GetSysClkStatusReg */ +/** \brief Return the System Clock Status Register of the PMC controller */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PMC_GetSysClkStatusReg( AT91PS_PMC pPMC /* pointer to a CAN controller */ + ) + { + return pPMC->PMC_SCSR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_EnablePeriphClock */ +/** \brief Enable peripheral clock */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_EnablePeriphClock( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int periphIds ) /* \arg IDs of peripherals to enable */ + { + pPMC->PMC_PCER = periphIds; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_DisablePeriphClock */ +/** \brief Disable peripheral clock */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_DisablePeriphClock( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int periphIds ) /* \arg IDs of peripherals to enable */ + { + pPMC->PMC_PCDR = periphIds; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_GetPeriphClock */ +/** \brief Get peripheral clock status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PMC_GetPeriphClock( AT91PS_PMC pPMC ) /* \arg pointer to PMC controller */ + { + return pPMC->PMC_PCSR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_CfgMainOscillatorReg */ +/** \brief Cfg the main oscillator */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_CKGR_CfgMainOscillatorReg( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */ + unsigned int mode ) + { + pCKGR->CKGR_MOR = mode; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_GetMainOscillatorReg */ +/** \brief Cfg the main oscillator */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_CKGR_GetMainOscillatorReg( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */ + { + return pCKGR->CKGR_MOR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_EnableMainOscillator */ +/** \brief Enable the main oscillator */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_CKGR_EnableMainOscillator( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */ + { + pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_DisableMainOscillator */ +/** \brief Disable the main oscillator */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_CKGR_DisableMainOscillator( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */ + { + pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_CfgMainOscStartUpTime */ +/** \brief Cfg MORE Register according to the main osc startup time */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_CKGR_CfgMainOscStartUpTime( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */ + unsigned int startup_time, /* \arg main osc startup time in microsecond (us) */ + unsigned int slowClock ) /* \arg slowClock in Hz */ + { + pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT; + pCKGR->CKGR_MOR |= ( ( slowClock * startup_time ) / ( 8 * 1000000 ) ) << 8; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_GetMainClockFreqReg */ +/** \brief Cfg the main oscillator */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_CKGR_GetMainClockFreqReg( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */ + { + return pCKGR->CKGR_MCFR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_GetMainClock */ +/** \brief Return Main clock in Hz */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_CKGR_GetMainClock( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */ + unsigned int slowClock ) /* \arg slowClock in Hz */ + { + return ( ( pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF ) * slowClock ) >> 4; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_CfgMCKReg */ +/** \brief Cfg Master Clock Register */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_CfgMCKReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int mode ) + { + pPMC->PMC_MCKR = mode; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_GetMCKReg */ +/** \brief Return Master Clock Register */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PMC_GetMCKReg( AT91PS_PMC pPMC ) /* \arg pointer to PMC controller */ + { + return pPMC->PMC_MCKR; + } + +/**------------------------------------------------------------------------------ */ +/** \fn AT91F_PMC_GetMasterClock */ +/** \brief Return master clock in Hz which corresponds to processor clock for ARM7 */ +/**------------------------------------------------------------------------------ */ + __inline unsigned int AT91F_PMC_GetMasterClock( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */ + unsigned int slowClock ) /* \arg slowClock in Hz */ + { + unsigned int reg = pPMC->PMC_MCKR; + unsigned int prescaler = ( 1 << ( ( reg & AT91C_PMC_PRES ) >> 2 ) ); + unsigned int pllDivider, pllMultiplier; + + switch( reg & AT91C_PMC_CSS ) + { + case AT91C_PMC_CSS_SLOW_CLK: /* Slow clock selected */ + return slowClock / prescaler; + + case AT91C_PMC_CSS_MAIN_CLK: /* Main clock is selected */ + return AT91F_CKGR_GetMainClock( pCKGR, slowClock ) / prescaler; + + case AT91C_PMC_CSS_PLL_CLK: /* PLLB clock is selected */ + reg = pCKGR->CKGR_PLLR; + pllDivider = ( reg & AT91C_CKGR_DIV ); + pllMultiplier = ( ( reg & AT91C_CKGR_MUL ) >> 16 ) + 1; + return AT91F_CKGR_GetMainClock( pCKGR, slowClock ) / pllDivider * pllMultiplier / prescaler; + } + + return 0; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_EnablePCK */ +/** \brief Enable peripheral clock */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_EnablePCK( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int pck, /* \arg Peripheral clock identifier 0 .. 7 */ + unsigned int mode ) + { + pPMC->PMC_PCKR[ pck ] = mode; + pPMC->PMC_SCER = ( 1 << pck ) << 8; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_DisablePCK */ +/** \brief Enable peripheral clock */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_DisablePCK( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int pck ) /* \arg Peripheral clock identifier 0 .. 7 */ + { + pPMC->PMC_SCDR = ( 1 << pck ) << 8; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_EnableIt */ +/** \brief Enable PMC interrupt */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_EnableIt( AT91PS_PMC pPMC, /* pointer to a PMC controller */ + unsigned int flag ) /* IT to be enabled */ + { + /** Write to the IER register */ + pPMC->PMC_IER = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_DisableIt */ +/** \brief Disable PMC interrupt */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_DisableIt( AT91PS_PMC pPMC, /* pointer to a PMC controller */ + unsigned int flag ) /* IT to be disabled */ + { + /** Write to the IDR register */ + pPMC->PMC_IDR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_GetStatus */ +/** \brief Return PMC Interrupt Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PMC_GetStatus( /* \return PMC Interrupt Status */ + AT91PS_PMC pPMC ) /* pointer to a PMC controller */ + { + return pPMC->PMC_SR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_GetInterruptMaskStatus */ +/** \brief Return PMC Interrupt Mask Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PMC_GetInterruptMaskStatus( /* \return PMC Interrupt Mask Status */ + AT91PS_PMC pPMC ) /* pointer to a PMC controller */ + { + return pPMC->PMC_IMR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_IsInterruptMasked */ +/** \brief Test if PMC Interrupt is Masked */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PMC_IsInterruptMasked( AT91PS_PMC pPMC, /* \arg pointer to a PMC controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PMC_GetInterruptMaskStatus( pPMC ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_IsStatusSet */ +/** \brief Test if PMC Status is Set */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PMC_IsStatusSet( AT91PS_PMC pPMC, /* \arg pointer to a PMC controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PMC_GetStatus( pPMC ) & flag ); + } /* ***************************************************************************** + * SOFTWARE API FOR RSTC + ***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_RSTSoftReset */ +/** \brief Start Software Reset */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_RSTSoftReset( AT91PS_RSTC pRSTC, + unsigned int reset ) + { + pRSTC->RSTC_RCR = ( 0xA5000000 | reset ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_RSTSetMode */ +/** \brief Set Reset Mode */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_RSTSetMode( AT91PS_RSTC pRSTC, + unsigned int mode ) + { + pRSTC->RSTC_RMR = ( 0xA5000000 | mode ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_RSTGetMode */ +/** \brief Get Reset Mode */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RSTGetMode( AT91PS_RSTC pRSTC ) + { + return( pRSTC->RSTC_RMR ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_RSTGetStatus */ +/** \brief Get Reset Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RSTGetStatus( AT91PS_RSTC pRSTC ) + { + return( pRSTC->RSTC_RSR ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_RSTIsSoftRstActive */ +/** \brief Return !=0 if software reset is still not completed */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RSTIsSoftRstActive( AT91PS_RSTC pRSTC ) + { + return( ( pRSTC->RSTC_RSR ) & AT91C_RSTC_SRCMP ); + } + +/* ***************************************************************************** +* SOFTWARE API FOR RTTC +***************************************************************************** */ +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_SetRTT_TimeBase() */ +/** \brief Set the RTT prescaler according to the TimeBase in ms */ +/**-------------------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RTTSetTimeBase( AT91PS_RTTC pRTTC, + unsigned int ms ) + { + if( ms > 2000 ) + { + return 1; /* AT91C_TIME_OUT_OF_RANGE */ + } + + pRTTC->RTTC_RTMR &= ~0xFFFF; + pRTTC->RTTC_RTMR |= ( ( ( ms << 15 ) / 1000 ) & 0xFFFF ); + return 0; + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTTSetPrescaler() */ +/** \brief Set the new prescaler value */ +/**-------------------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RTTSetPrescaler( AT91PS_RTTC pRTTC, + unsigned int rtpres ) + { + pRTTC->RTTC_RTMR &= ~0xFFFF; + pRTTC->RTTC_RTMR |= ( rtpres & 0xFFFF ); + return( pRTTC->RTTC_RTMR ); + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTTRestart() */ +/** \brief Restart the RTT prescaler */ +/**-------------------------------------------------------------------------------------- */ + __inline void AT91F_RTTRestart( AT91PS_RTTC pRTTC ) + { + pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST; + } + + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTT_SetAlarmINT() */ +/** \brief Enable RTT Alarm Interrupt */ +/**-------------------------------------------------------------------------------------- */ + __inline void AT91F_RTTSetAlarmINT( AT91PS_RTTC pRTTC ) + { + pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN; + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTT_ClearAlarmINT() */ +/** \brief Disable RTT Alarm Interrupt */ +/**-------------------------------------------------------------------------------------- */ + __inline void AT91F_RTTClearAlarmINT( AT91PS_RTTC pRTTC ) + { + pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN; + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTT_SetRttIncINT() */ +/** \brief Enable RTT INC Interrupt */ +/**-------------------------------------------------------------------------------------- */ + __inline void AT91F_RTTSetRttIncINT( AT91PS_RTTC pRTTC ) + { + pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN; + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTT_ClearRttIncINT() */ +/** \brief Disable RTT INC Interrupt */ +/**-------------------------------------------------------------------------------------- */ + __inline void AT91F_RTTClearRttIncINT( AT91PS_RTTC pRTTC ) + { + pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN; + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTT_SetAlarmValue() */ +/** \brief Set RTT Alarm Value */ +/**-------------------------------------------------------------------------------------- */ + __inline void AT91F_RTTSetAlarmValue( AT91PS_RTTC pRTTC, + unsigned int alarm ) + { + pRTTC->RTTC_RTAR = alarm; + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTT_GetAlarmValue() */ +/** \brief Get RTT Alarm Value */ +/**-------------------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RTTGetAlarmValue( AT91PS_RTTC pRTTC ) + { + return( pRTTC->RTTC_RTAR ); + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTTGetStatus() */ +/** \brief Read the RTT status */ +/**-------------------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RTTGetStatus( AT91PS_RTTC pRTTC ) + { + return( pRTTC->RTTC_RTSR ); + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTT_ReadValue() */ +/** \brief Read the RTT value */ +/**-------------------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RTTReadValue( AT91PS_RTTC pRTTC ) + { + register volatile unsigned int val1, val2; + + do + { + val1 = pRTTC->RTTC_RTVR; + val2 = pRTTC->RTTC_RTVR; + } + while( val1 != val2 ); + + return( val1 ); + } + +/* ***************************************************************************** +* SOFTWARE API FOR PITC +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PITInit */ +/** \brief System timer init : period in */ diff --git a/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h b/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h new file mode 100644 index 000000000..4ac85fb96 --- /dev/null +++ b/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h @@ -0,0 +1,1396 @@ +/** ---------------------------------------------------------------------------- */ +/** ATMEL Microcontroller Software Support - ROUSSET - */ +/** ---------------------------------------------------------------------------- */ +/** DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/** MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/** DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/** LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/** OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/** LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/** NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/** EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/** ---------------------------------------------------------------------------- */ +/** File Name : lib_AT91SAM7X256.h */ +/** Object : AT91SAM7X256 inlined functions */ +/** Generated : AT91 SW Application Group 05/20/2005 (16:22:29) */ +/** */ +/** CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// */ +/** CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005// */ +/** CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005// */ +/** CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004// */ +/** CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// */ +/** CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004// */ +/** CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// */ +/** CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003// */ +/** CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004// */ +/** CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005// */ +/** CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005// */ +/** CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// */ +/** CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// */ +/** CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004// */ +/** CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005// */ +/** CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005// */ +/** CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// */ +/** CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004// */ +/** CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// */ +/** CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003// */ +/** CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// */ +/** CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002// */ +/** ---------------------------------------------------------------------------- */ + +#ifndef lib_AT91SAM7X256_H + #define lib_AT91SAM7X256_H + +/* ***************************************************************************** +* SOFTWARE API FOR AIC +***************************************************************************** */ + #define AT91C_AIC_BRANCH_OPCODE ( ( void ( * )() ) 0xE51FFF20 ) /* ldr, pc, [pc, #-&F20] */ + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_ConfigureIt */ +/** \brief Interrupt Handler Initialization */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_AIC_ConfigureIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id, /* \arg interrupt number to initialize */ + unsigned int priority, /* \arg priority to give to the interrupt */ + unsigned int src_type, /* \arg activation and sense of activation */ + void ( * newHandler )( void ) ) /* \arg address of the interrupt handler */ + { + unsigned int oldHandler; + unsigned int mask; + + oldHandler = pAic->AIC_SVR[ irq_id ]; + + mask = 0x1 << irq_id; + /** Disable the interrupt on the interrupt controller */ + pAic->AIC_IDCR = mask; + /** Save the interrupt handler routine pointer and the interrupt priority */ + pAic->AIC_SVR[ irq_id ] = ( unsigned int ) newHandler; + /** Store the Source Mode Register */ + pAic->AIC_SMR[ irq_id ] = src_type | priority; + /** Clear the interrupt on the interrupt controller */ + pAic->AIC_ICCR = mask; + + return oldHandler; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_EnableIt */ +/** \brief Enable corresponding IT number */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_AIC_EnableIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg interrupt number to initialize */ + { + /** Enable the interrupt on the interrupt controller */ + pAic->AIC_IECR = 0x1 << irq_id; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_DisableIt */ +/** \brief Disable corresponding IT number */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_AIC_DisableIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg interrupt number to initialize */ + { + unsigned int mask = 0x1 << irq_id; + + /** Disable the interrupt on the interrupt controller */ + pAic->AIC_IDCR = mask; + /** Clear the interrupt on the Interrupt Controller ( if one is pending ) */ + pAic->AIC_ICCR = mask; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_ClearIt */ +/** \brief Clear corresponding IT number */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_AIC_ClearIt( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg interrupt number to initialize */ + { + /** Clear the interrupt on the Interrupt Controller ( if one is pending ) */ + pAic->AIC_ICCR = ( 0x1 << irq_id ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_AcknowledgeIt */ +/** \brief Acknowledge corresponding IT number */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_AIC_AcknowledgeIt( AT91PS_AIC pAic ) /* \arg pointer to the AIC registers */ + { + pAic->AIC_EOICR = pAic->AIC_EOICR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_SetExceptionVector */ +/** \brief Configure vector handler */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_AIC_SetExceptionVector( unsigned int * pVector, /* \arg pointer to the AIC registers */ + void ( * Handler )() ) /* \arg Interrupt Handler */ + { + unsigned int oldVector = *pVector; + + if( ( unsigned int ) Handler == ( unsigned int ) AT91C_AIC_BRANCH_OPCODE ) + { + *pVector = ( unsigned int ) AT91C_AIC_BRANCH_OPCODE; + } + else + { + *pVector = ( ( ( ( ( unsigned int ) Handler ) - ( ( unsigned int ) pVector ) - 0x8 ) >> 2 ) & 0x00FFFFFF ) | 0xEA000000; + } + + return oldVector; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_Trig */ +/** \brief Trig an IT */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_AIC_Trig( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg interrupt number */ + { + pAic->AIC_ISCR = ( 0x1 << irq_id ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_IsActive */ +/** \brief Test if an IT is active */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_AIC_IsActive( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg Interrupt Number */ + { + return( pAic->AIC_ISR & ( 0x1 << irq_id ) ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_IsPending */ +/** \brief Test if an IT is pending */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_AIC_IsPending( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + unsigned int irq_id ) /* \arg Interrupt Number */ + { + return( pAic->AIC_IPR & ( 0x1 << irq_id ) ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_AIC_Open */ +/** \brief Set exception vectors and AIC registers to default values */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_AIC_Open( AT91PS_AIC pAic, /* \arg pointer to the AIC registers */ + void ( * IrqHandler )(), /* \arg Default IRQ vector exception */ + void ( * FiqHandler )(), /* \arg Default FIQ vector exception */ + void ( * DefaultHandler )(), /* \arg Default Handler set in ISR */ + void ( * SpuriousHandler )(), /* \arg Default Spurious Handler */ + unsigned int protectMode ) /* \arg Debug Control Register */ + { + int i; + + /* Disable all interrupts and set IVR to the default handler */ + for( i = 0; i < 32; ++i ) + { + AT91F_AIC_DisableIt( pAic, i ); + AT91F_AIC_ConfigureIt( pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler ); + } + + /* Set the IRQ exception vector */ + AT91F_AIC_SetExceptionVector( ( unsigned int * ) 0x18, IrqHandler ); + /* Set the Fast Interrupt exception vector */ + AT91F_AIC_SetExceptionVector( ( unsigned int * ) 0x1C, FiqHandler ); + + pAic->AIC_SPU = ( unsigned int ) SpuriousHandler; + pAic->AIC_DCR = protectMode; + } + +/* ***************************************************************************** +* SOFTWARE API FOR PDC +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_SetNextRx */ +/** \brief Set the next receive transfer descriptor */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_SetNextRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ + char * address, /* \arg address to the next block to be received */ + unsigned int bytes ) /* \arg number of bytes to be received */ + { + pPDC->PDC_RNPR = ( unsigned int ) address; + pPDC->PDC_RNCR = bytes; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_SetNextTx */ +/** \brief Set the next transmit transfer descriptor */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_SetNextTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ + char * address, /* \arg address to the next block to be transmitted */ + unsigned int bytes ) /* \arg number of bytes to be transmitted */ + { + pPDC->PDC_TNPR = ( unsigned int ) address; + pPDC->PDC_TNCR = bytes; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_SetRx */ +/** \brief Set the receive transfer descriptor */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_SetRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ + char * address, /* \arg address to the next block to be received */ + unsigned int bytes ) /* \arg number of bytes to be received */ + { + pPDC->PDC_RPR = ( unsigned int ) address; + pPDC->PDC_RCR = bytes; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_SetTx */ +/** \brief Set the transmit transfer descriptor */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_SetTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */ + char * address, /* \arg address to the next block to be transmitted */ + unsigned int bytes ) /* \arg number of bytes to be transmitted */ + { + pPDC->PDC_TPR = ( unsigned int ) address; + pPDC->PDC_TCR = bytes; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_EnableTx */ +/** \brief Enable transmit */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_EnableTx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + pPDC->PDC_PTCR = AT91C_PDC_TXTEN; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_EnableRx */ +/** \brief Enable receive */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_EnableRx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + pPDC->PDC_PTCR = AT91C_PDC_RXTEN; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_DisableTx */ +/** \brief Disable transmit */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_DisableTx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_DisableRx */ +/** \brief Disable receive */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_DisableRx( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_IsTxEmpty */ +/** \brief Test if the current transfer descriptor has been sent */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PDC_IsTxEmpty( /* \return return 1 if transfer is complete */ + AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + return !( pPDC->PDC_TCR ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_IsNextTxEmpty */ +/** \brief Test if the next transfer descriptor has been moved to the current td */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PDC_IsNextTxEmpty( /* \return return 1 if transfer is complete */ + AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + return !( pPDC->PDC_TNCR ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_IsRxEmpty */ +/** \brief Test if the current transfer descriptor has been filled */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PDC_IsRxEmpty( /* \return return 1 if transfer is complete */ + AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + return !( pPDC->PDC_RCR ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_IsNextRxEmpty */ +/** \brief Test if the next transfer descriptor has been moved to the current td */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PDC_IsNextRxEmpty( /* \return return 1 if transfer is complete */ + AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + return !( pPDC->PDC_RNCR ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_Open */ +/** \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_Open( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + /** Disable the RX and TX PDC transfer requests */ + AT91F_PDC_DisableRx( pPDC ); + AT91F_PDC_DisableTx( pPDC ); + + /** Reset all Counter register Next buffer first */ + AT91F_PDC_SetNextTx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetNextRx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetTx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetRx( pPDC, ( char * ) 0, 0 ); + + /** Enable the RX and TX PDC transfer requests */ + AT91F_PDC_EnableRx( pPDC ); + AT91F_PDC_EnableTx( pPDC ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_Close */ +/** \brief Close PDC: disable TX and RX reset transfer descriptors */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PDC_Close( AT91PS_PDC pPDC ) /* \arg pointer to a PDC controller */ + { + /** Disable the RX and TX PDC transfer requests */ + AT91F_PDC_DisableRx( pPDC ); + AT91F_PDC_DisableTx( pPDC ); + + /** Reset all Counter register Next buffer first */ + AT91F_PDC_SetNextTx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetNextRx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetTx( pPDC, ( char * ) 0, 0 ); + AT91F_PDC_SetRx( pPDC, ( char * ) 0, 0 ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_SendFrame */ +/** \brief Close PDC: disable TX and RX reset transfer descriptors */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PDC_SendFrame( AT91PS_PDC pPDC, + char * pBuffer, + unsigned int szBuffer, + char * pNextBuffer, + unsigned int szNextBuffer ) + { + if( AT91F_PDC_IsTxEmpty( pPDC ) ) + { + /** Buffer and next buffer can be initialized */ + AT91F_PDC_SetTx( pPDC, pBuffer, szBuffer ); + AT91F_PDC_SetNextTx( pPDC, pNextBuffer, szNextBuffer ); + return 2; + } + else if( AT91F_PDC_IsNextTxEmpty( pPDC ) ) + { + /** Only one buffer can be initialized */ + AT91F_PDC_SetNextTx( pPDC, pBuffer, szBuffer ); + return 1; + } + else + { + /** All buffer are in use... */ + return 0; + } + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PDC_ReceiveFrame */ +/** \brief Close PDC: disable TX and RX reset transfer descriptors */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PDC_ReceiveFrame( AT91PS_PDC pPDC, + char * pBuffer, + unsigned int szBuffer, + char * pNextBuffer, + unsigned int szNextBuffer ) + { + if( AT91F_PDC_IsRxEmpty( pPDC ) ) + { + /** Buffer and next buffer can be initialized */ + AT91F_PDC_SetRx( pPDC, pBuffer, szBuffer ); + AT91F_PDC_SetNextRx( pPDC, pNextBuffer, szNextBuffer ); + return 2; + } + else if( AT91F_PDC_IsNextRxEmpty( pPDC ) ) + { + /** Only one buffer can be initialized */ + AT91F_PDC_SetNextRx( pPDC, pBuffer, szBuffer ); + return 1; + } + else + { + /** All buffer are in use... */ + return 0; + } + } + +/* ***************************************************************************** +* SOFTWARE API FOR DBGU +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_DBGU_InterruptEnable */ +/** \brief Enable DBGU Interrupt */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_DBGU_InterruptEnable( AT91PS_DBGU pDbgu, /* \arg pointer to a DBGU controller */ + unsigned int flag ) /* \arg dbgu interrupt to be enabled */ + { + pDbgu->DBGU_IER = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_DBGU_InterruptDisable */ +/** \brief Disable DBGU Interrupt */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_DBGU_InterruptDisable( AT91PS_DBGU pDbgu, /* \arg pointer to a DBGU controller */ + unsigned int flag ) /* \arg dbgu interrupt to be disabled */ + { + pDbgu->DBGU_IDR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_DBGU_GetInterruptMaskStatus */ +/** \brief Return DBGU Interrupt Mask Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( /* \return DBGU Interrupt Mask Status */ + AT91PS_DBGU pDbgu ) /* \arg pointer to a DBGU controller */ + { + return pDbgu->DBGU_IMR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_DBGU_IsInterruptMasked */ +/** \brief Test if DBGU Interrupt is Masked */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_DBGU_IsInterruptMasked( AT91PS_DBGU pDbgu, /* \arg pointer to a DBGU controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_DBGU_GetInterruptMaskStatus( pDbgu ) & flag ); + } + +/* ***************************************************************************** +* SOFTWARE API FOR PIO +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgPeriph */ +/** \brief Enable pins to be derived by peripheral */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_CfgPeriph( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int periphAEnable, /* \arg PERIPH A to enable */ + unsigned int periphBEnable ) /* \arg PERIPH B to enable */ + + { + pPio->PIO_ASR = periphAEnable; + pPio->PIO_BSR = periphBEnable; + pPio->PIO_PDR = ( periphAEnable | periphBEnable ); /* Set in Periph mode */ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgOutput */ +/** \brief Enable PIO in output mode */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_CfgOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int pioEnable ) /* \arg PIO to be enabled */ + { + pPio->PIO_PER = pioEnable; /* Set in PIO mode */ + pPio->PIO_OER = pioEnable; /* Configure in Output */ + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgInput */ +/** \brief Enable PIO in input mode */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_CfgInput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int inputEnable ) /* \arg PIO to be enabled */ + { + /* Disable output */ + pPio->PIO_ODR = inputEnable; + pPio->PIO_PER = inputEnable; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgOpendrain */ +/** \brief Configure PIO in open drain */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_CfgOpendrain( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int multiDrvEnable ) /* \arg pio to be configured in open drain */ + { + /* Configure the multi-drive option */ + pPio->PIO_MDDR = ~multiDrvEnable; + pPio->PIO_MDER = multiDrvEnable; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgPullup */ +/** \brief Enable pullup on PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_CfgPullup( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int pullupEnable ) /* \arg enable pullup on PIO */ + { + /* Connect or not Pullup */ + pPio->PIO_PPUDR = ~pullupEnable; + pPio->PIO_PPUER = pullupEnable; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgDirectDrive */ +/** \brief Enable direct drive on PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_CfgDirectDrive( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int directDrive ) /* \arg PIO to be configured with direct drive */ + + { + /* Configure the Direct Drive */ + pPio->PIO_OWDR = ~directDrive; + pPio->PIO_OWER = directDrive; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_CfgInputFilter */ +/** \brief Enable input filter on input PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_CfgInputFilter( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int inputFilter ) /* \arg PIO to be configured with input filter */ + + { + /* Configure the Direct Drive */ + pPio->PIO_IFDR = ~inputFilter; + pPio->PIO_IFER = inputFilter; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetInput */ +/** \brief Return PIO input value */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetInput( /* \return PIO input */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { + return pPio->PIO_PDSR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsInputSet */ +/** \brief Test if PIO is input flag is active */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsInputSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetInput( pPio ) & flag ); + } + + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_SetOutput */ +/** \brief Set to 1 output PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_SetOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg output to be set */ + { + pPio->PIO_SODR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_ClearOutput */ +/** \brief Set to 0 output PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_ClearOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg output to be cleared */ + { + pPio->PIO_CODR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_ForceOutput */ +/** \brief Force output when Direct drive option is enabled */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_ForceOutput( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg output to be forced */ + { + pPio->PIO_ODSR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_Enable */ +/** \brief Enable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_Enable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio to be enabled */ + { + pPio->PIO_PER = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_Disable */ +/** \brief Disable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_Disable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio to be disabled */ + { + pPio->PIO_PDR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetStatus */ +/** \brief Return PIO Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetStatus( /* \return PIO Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { + return pPio->PIO_PSR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsSet */ +/** \brief Test if PIO is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_OutputEnable */ +/** \brief Output Enable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_OutputEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio output to be enabled */ + { + pPio->PIO_OER = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_OutputDisable */ +/** \brief Output Enable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_OutputDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio output to be disabled */ + { + pPio->PIO_ODR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetOutputStatus */ +/** \brief Return PIO Output Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetOutputStatus( /* \return PIO Output Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { + return pPio->PIO_OSR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsOuputSet */ +/** \brief Test if PIO Output is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsOutputSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetOutputStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_InputFilterEnable */ +/** \brief Input Filter Enable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_InputFilterEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio input filter to be enabled */ + { + pPio->PIO_IFER = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_InputFilterDisable */ +/** \brief Input Filter Disable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_InputFilterDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio input filter to be disabled */ + { + pPio->PIO_IFDR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetInputFilterStatus */ +/** \brief Return PIO Input Filter Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetInputFilterStatus( /* \return PIO Input Filter Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { + return pPio->PIO_IFSR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsInputFilterSet */ +/** \brief Test if PIO Input filter is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsInputFilterSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetInputFilterStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetOutputDataStatus */ +/** \brief Return PIO Output Data Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetOutputDataStatus( /* \return PIO Output Data Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { + return pPio->PIO_ODSR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_InterruptEnable */ +/** \brief Enable PIO Interrupt */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_InterruptEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio interrupt to be enabled */ + { + pPio->PIO_IER = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_InterruptDisable */ +/** \brief Disable PIO Interrupt */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_InterruptDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio interrupt to be disabled */ + { + pPio->PIO_IDR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetInterruptMaskStatus */ +/** \brief Return PIO Interrupt Mask Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetInterruptMaskStatus( /* \return PIO Interrupt Mask Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { + return pPio->PIO_IMR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetInterruptStatus */ +/** \brief Return PIO Interrupt Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetInterruptStatus( /* \return PIO Interrupt Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { + return pPio->PIO_ISR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsInterruptMasked */ +/** \brief Test if PIO Interrupt is Masked */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsInterruptMasked( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetInterruptMaskStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsInterruptSet */ +/** \brief Test if PIO Interrupt is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsInterruptSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetInterruptStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_MultiDriverEnable */ +/** \brief Multi Driver Enable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_MultiDriverEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio to be enabled */ + { + pPio->PIO_MDER = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_MultiDriverDisable */ +/** \brief Multi Driver Disable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_MultiDriverDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio to be disabled */ + { + pPio->PIO_MDDR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetMultiDriverStatus */ +/** \brief Return PIO Multi Driver Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetMultiDriverStatus( /* \return PIO Multi Driver Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { + return pPio->PIO_MDSR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsMultiDriverSet */ +/** \brief Test if PIO MultiDriver is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsMultiDriverSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetMultiDriverStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_A_RegisterSelection */ +/** \brief PIO A Register Selection */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_A_RegisterSelection( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio A register selection */ + { + pPio->PIO_ASR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_B_RegisterSelection */ +/** \brief PIO B Register Selection */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_B_RegisterSelection( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio B register selection */ + { + pPio->PIO_BSR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_Get_AB_RegisterStatus */ +/** \brief Return PIO Interrupt Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( /* \return PIO AB Register Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { + return pPio->PIO_ABSR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsAB_RegisterSet */ +/** \brief Test if PIO AB Register is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsAB_RegisterSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_Get_AB_RegisterStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_OutputWriteEnable */ +/** \brief Output Write Enable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_OutputWriteEnable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio output write to be enabled */ + { + pPio->PIO_OWER = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_OutputWriteDisable */ +/** \brief Output Write Disable PIO */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PIO_OutputWriteDisable( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg pio output write to be disabled */ + { + pPio->PIO_OWDR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetOutputWriteStatus */ +/** \brief Return PIO Output Write Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetOutputWriteStatus( /* \return PIO Output Write Status */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { + return pPio->PIO_OWSR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsOutputWriteSet */ +/** \brief Test if PIO OutputWrite is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsOutputWriteSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetOutputWriteStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_GetCfgPullup */ +/** \brief Return PIO Configuration Pullup */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PIO_GetCfgPullup( /* \return PIO Configuration Pullup */ + AT91PS_PIO pPio ) /* \arg pointer to a PIO controller */ + { + return pPio->PIO_PPUSR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsOutputDataStatusSet */ +/** \brief Test if PIO Output Data Status is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsOutputDataStatusSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PIO_GetOutputDataStatus( pPio ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PIO_IsCfgPullupStatusSet */ +/** \brief Test if PIO Configuration Pullup Status is Set */ +/**---------------------------------------------------------------------------- */ + __inline int AT91F_PIO_IsCfgPullupStatusSet( AT91PS_PIO pPio, /* \arg pointer to a PIO controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( ~AT91F_PIO_GetCfgPullup( pPio ) & flag ); + } + +/* ***************************************************************************** +* SOFTWARE API FOR PMC +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_CfgSysClkEnableReg */ +/** \brief Configure the System Clock Enable Register of the PMC controller */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_CfgSysClkEnableReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int mode ) + { + /** Write to the SCER register */ + pPMC->PMC_SCER = mode; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_CfgSysClkDisableReg */ +/** \brief Configure the System Clock Disable Register of the PMC controller */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_CfgSysClkDisableReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int mode ) + { + /** Write to the SCDR register */ + pPMC->PMC_SCDR = mode; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_GetSysClkStatusReg */ +/** \brief Return the System Clock Status Register of the PMC controller */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PMC_GetSysClkStatusReg( AT91PS_PMC pPMC /* pointer to a CAN controller */ + ) + { + return pPMC->PMC_SCSR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_EnablePeriphClock */ +/** \brief Enable peripheral clock */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_EnablePeriphClock( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int periphIds ) /* \arg IDs of peripherals to enable */ + { + pPMC->PMC_PCER = periphIds; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_DisablePeriphClock */ +/** \brief Disable peripheral clock */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_DisablePeriphClock( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int periphIds ) /* \arg IDs of peripherals to enable */ + { + pPMC->PMC_PCDR = periphIds; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_GetPeriphClock */ +/** \brief Get peripheral clock status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PMC_GetPeriphClock( AT91PS_PMC pPMC ) /* \arg pointer to PMC controller */ + { + return pPMC->PMC_PCSR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_CfgMainOscillatorReg */ +/** \brief Cfg the main oscillator */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_CKGR_CfgMainOscillatorReg( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */ + unsigned int mode ) + { + pCKGR->CKGR_MOR = mode; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_GetMainOscillatorReg */ +/** \brief Cfg the main oscillator */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_CKGR_GetMainOscillatorReg( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */ + { + return pCKGR->CKGR_MOR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_EnableMainOscillator */ +/** \brief Enable the main oscillator */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_CKGR_EnableMainOscillator( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */ + { + pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_DisableMainOscillator */ +/** \brief Disable the main oscillator */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_CKGR_DisableMainOscillator( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */ + { + pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_CfgMainOscStartUpTime */ +/** \brief Cfg MORE Register according to the main osc startup time */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_CKGR_CfgMainOscStartUpTime( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */ + unsigned int startup_time, /* \arg main osc startup time in microsecond (us) */ + unsigned int slowClock ) /* \arg slowClock in Hz */ + { + pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT; + pCKGR->CKGR_MOR |= ( ( slowClock * startup_time ) / ( 8 * 1000000 ) ) << 8; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_GetMainClockFreqReg */ +/** \brief Cfg the main oscillator */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_CKGR_GetMainClockFreqReg( AT91PS_CKGR pCKGR ) /* \arg pointer to CKGR controller */ + { + return pCKGR->CKGR_MCFR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_CKGR_GetMainClock */ +/** \brief Return Main clock in Hz */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_CKGR_GetMainClock( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */ + unsigned int slowClock ) /* \arg slowClock in Hz */ + { + return ( ( pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF ) * slowClock ) >> 4; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_CfgMCKReg */ +/** \brief Cfg Master Clock Register */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_CfgMCKReg( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int mode ) + { + pPMC->PMC_MCKR = mode; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_GetMCKReg */ +/** \brief Return Master Clock Register */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PMC_GetMCKReg( AT91PS_PMC pPMC ) /* \arg pointer to PMC controller */ + { + return pPMC->PMC_MCKR; + } + +/**------------------------------------------------------------------------------ */ +/** \fn AT91F_PMC_GetMasterClock */ +/** \brief Return master clock in Hz which corresponds to processor clock for ARM7 */ +/**------------------------------------------------------------------------------ */ + __inline unsigned int AT91F_PMC_GetMasterClock( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */ + unsigned int slowClock ) /* \arg slowClock in Hz */ + { + unsigned int reg = pPMC->PMC_MCKR; + unsigned int prescaler = ( 1 << ( ( reg & AT91C_PMC_PRES ) >> 2 ) ); + unsigned int pllDivider, pllMultiplier; + + switch( reg & AT91C_PMC_CSS ) + { + case AT91C_PMC_CSS_SLOW_CLK: /* Slow clock selected */ + return slowClock / prescaler; + + case AT91C_PMC_CSS_MAIN_CLK: /* Main clock is selected */ + return AT91F_CKGR_GetMainClock( pCKGR, slowClock ) / prescaler; + + case AT91C_PMC_CSS_PLL_CLK: /* PLLB clock is selected */ + reg = pCKGR->CKGR_PLLR; + pllDivider = ( reg & AT91C_CKGR_DIV ); + pllMultiplier = ( ( reg & AT91C_CKGR_MUL ) >> 16 ) + 1; + return AT91F_CKGR_GetMainClock( pCKGR, slowClock ) / pllDivider * pllMultiplier / prescaler; + } + + return 0; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_EnablePCK */ +/** \brief Enable peripheral clock */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_EnablePCK( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int pck, /* \arg Peripheral clock identifier 0 .. 7 */ + unsigned int mode ) + { + pPMC->PMC_PCKR[ pck ] = mode; + pPMC->PMC_SCER = ( 1 << pck ) << 8; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_DisablePCK */ +/** \brief Enable peripheral clock */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_DisablePCK( AT91PS_PMC pPMC, /* \arg pointer to PMC controller */ + unsigned int pck ) /* \arg Peripheral clock identifier 0 .. 7 */ + { + pPMC->PMC_SCDR = ( 1 << pck ) << 8; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_EnableIt */ +/** \brief Enable PMC interrupt */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_EnableIt( AT91PS_PMC pPMC, /* pointer to a PMC controller */ + unsigned int flag ) /* IT to be enabled */ + { + /** Write to the IER register */ + pPMC->PMC_IER = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_DisableIt */ +/** \brief Disable PMC interrupt */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_PMC_DisableIt( AT91PS_PMC pPMC, /* pointer to a PMC controller */ + unsigned int flag ) /* IT to be disabled */ + { + /** Write to the IDR register */ + pPMC->PMC_IDR = flag; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_GetStatus */ +/** \brief Return PMC Interrupt Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PMC_GetStatus( /* \return PMC Interrupt Status */ + AT91PS_PMC pPMC ) /* pointer to a PMC controller */ + { + return pPMC->PMC_SR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_GetInterruptMaskStatus */ +/** \brief Return PMC Interrupt Mask Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PMC_GetInterruptMaskStatus( /* \return PMC Interrupt Mask Status */ + AT91PS_PMC pPMC ) /* pointer to a PMC controller */ + { + return pPMC->PMC_IMR; + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_IsInterruptMasked */ +/** \brief Test if PMC Interrupt is Masked */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PMC_IsInterruptMasked( AT91PS_PMC pPMC, /* \arg pointer to a PMC controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PMC_GetInterruptMaskStatus( pPMC ) & flag ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PMC_IsStatusSet */ +/** \brief Test if PMC Status is Set */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_PMC_IsStatusSet( AT91PS_PMC pPMC, /* \arg pointer to a PMC controller */ + unsigned int flag ) /* \arg flag to be tested */ + { + return( AT91F_PMC_GetStatus( pPMC ) & flag ); + } /* ***************************************************************************** + * SOFTWARE API FOR RSTC + ***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_RSTSoftReset */ +/** \brief Start Software Reset */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_RSTSoftReset( AT91PS_RSTC pRSTC, + unsigned int reset ) + { + pRSTC->RSTC_RCR = ( 0xA5000000 | reset ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_RSTSetMode */ +/** \brief Set Reset Mode */ +/**---------------------------------------------------------------------------- */ + __inline void AT91F_RSTSetMode( AT91PS_RSTC pRSTC, + unsigned int mode ) + { + pRSTC->RSTC_RMR = ( 0xA5000000 | mode ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_RSTGetMode */ +/** \brief Get Reset Mode */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RSTGetMode( AT91PS_RSTC pRSTC ) + { + return( pRSTC->RSTC_RMR ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_RSTGetStatus */ +/** \brief Get Reset Status */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RSTGetStatus( AT91PS_RSTC pRSTC ) + { + return( pRSTC->RSTC_RSR ); + } + +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_RSTIsSoftRstActive */ +/** \brief Return !=0 if software reset is still not completed */ +/**---------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RSTIsSoftRstActive( AT91PS_RSTC pRSTC ) + { + return( ( pRSTC->RSTC_RSR ) & AT91C_RSTC_SRCMP ); + } + +/* ***************************************************************************** +* SOFTWARE API FOR RTTC +***************************************************************************** */ +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_SetRTT_TimeBase() */ +/** \brief Set the RTT prescaler according to the TimeBase in ms */ +/**-------------------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RTTSetTimeBase( AT91PS_RTTC pRTTC, + unsigned int ms ) + { + if( ms > 2000 ) + { + return 1; /* AT91C_TIME_OUT_OF_RANGE */ + } + + pRTTC->RTTC_RTMR &= ~0xFFFF; + pRTTC->RTTC_RTMR |= ( ( ( ms << 15 ) / 1000 ) & 0xFFFF ); + return 0; + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTTSetPrescaler() */ +/** \brief Set the new prescaler value */ +/**-------------------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RTTSetPrescaler( AT91PS_RTTC pRTTC, + unsigned int rtpres ) + { + pRTTC->RTTC_RTMR &= ~0xFFFF; + pRTTC->RTTC_RTMR |= ( rtpres & 0xFFFF ); + return( pRTTC->RTTC_RTMR ); + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTTRestart() */ +/** \brief Restart the RTT prescaler */ +/**-------------------------------------------------------------------------------------- */ + __inline void AT91F_RTTRestart( AT91PS_RTTC pRTTC ) + { + pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST; + } + + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTT_SetAlarmINT() */ +/** \brief Enable RTT Alarm Interrupt */ +/**-------------------------------------------------------------------------------------- */ + __inline void AT91F_RTTSetAlarmINT( AT91PS_RTTC pRTTC ) + { + pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN; + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTT_ClearAlarmINT() */ +/** \brief Disable RTT Alarm Interrupt */ +/**-------------------------------------------------------------------------------------- */ + __inline void AT91F_RTTClearAlarmINT( AT91PS_RTTC pRTTC ) + { + pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN; + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTT_SetRttIncINT() */ +/** \brief Enable RTT INC Interrupt */ +/**-------------------------------------------------------------------------------------- */ + __inline void AT91F_RTTSetRttIncINT( AT91PS_RTTC pRTTC ) + { + pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN; + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTT_ClearRttIncINT() */ +/** \brief Disable RTT INC Interrupt */ +/**-------------------------------------------------------------------------------------- */ + __inline void AT91F_RTTClearRttIncINT( AT91PS_RTTC pRTTC ) + { + pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN; + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTT_SetAlarmValue() */ +/** \brief Set RTT Alarm Value */ +/**-------------------------------------------------------------------------------------- */ + __inline void AT91F_RTTSetAlarmValue( AT91PS_RTTC pRTTC, + unsigned int alarm ) + { + pRTTC->RTTC_RTAR = alarm; + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTT_GetAlarmValue() */ +/** \brief Get RTT Alarm Value */ +/**-------------------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RTTGetAlarmValue( AT91PS_RTTC pRTTC ) + { + return( pRTTC->RTTC_RTAR ); + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTTGetStatus() */ +/** \brief Read the RTT status */ +/**-------------------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RTTGetStatus( AT91PS_RTTC pRTTC ) + { + return( pRTTC->RTTC_RTSR ); + } + +/**-------------------------------------------------------------------------------------- */ +/** \fn AT91F_RTT_ReadValue() */ +/** \brief Read the RTT value */ +/**-------------------------------------------------------------------------------------- */ + __inline unsigned int AT91F_RTTReadValue( AT91PS_RTTC pRTTC ) + { + register volatile unsigned int val1, val2; + + do + { + val1 = pRTTC->RTTC_RTVR; + val2 = pRTTC->RTTC_RTVR; + } + while( val1 != val2 ); + + return( val1 ); + } + +/* ***************************************************************************** +* SOFTWARE API FOR PITC +***************************************************************************** */ +/**---------------------------------------------------------------------------- */ +/** \fn AT91F_PITInit */ +/** \brief System timer init : period in */ diff --git a/portable/IAR/AtmelSAM7S64/port.c b/portable/IAR/AtmelSAM7S64/port.c new file mode 100644 index 000000000..5f5f7625f --- /dev/null +++ b/portable/IAR/AtmelSAM7S64/port.c @@ -0,0 +1,252 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the Atmel ARM7 port. +*----------------------------------------------------------*/ + + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to setup the initial stack. */ +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) + +/* Constants required to setup the PIT. */ +#define portPIT_CLOCK_DIVISOR ( ( uint32_t ) 16 ) +#define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_PERIOD_MS ) + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + + +#define portINT_LEVEL_SENSITIVE 0 +#define portPIT_ENABLE ( ( uint16_t ) 0x1 << 24 ) +#define portPIT_INT_ENABLE ( ( uint16_t ) 0x1 << 25 ) +/*-----------------------------------------------------------*/ + +/* Setup the PIT to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* ulCriticalNesting will get set to zero when the first task starts. It + * cannot be initialised to 0 as this will cause interrupts to be enabled + * during the kernel initialisation process. */ +uint32_t ulCriticalNesting = ( uint32_t ) 9999; + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + StackType_t * pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + /* To ensure asserts in tasks.c don't fail, although in this case the assert + * is not really required. */ + pxTopOfStack--; + + /* Setup the initial stack of the task. The stack is set exactly as + * expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which in this case is the + * start of the task. The offset is added to make the return address appear + * as it would within an IRQ ISR. */ + *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + * R0. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The status register is set for system mode, with interrupts enabled. */ + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + + if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00UL ) + { + /* We want the task to start in thumb mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + + pxTopOfStack--; + + /* Interrupt flags cannot always be stored on the stack and will + * instead be stored in a variable, which is then saved as part of the + * tasks context. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + extern void vPortStartFirstTask( void ); + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + * is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +#if configUSE_PREEMPTION == 0 + +/* The cooperative scheduler requires a normal IRQ service routine to + * simply increment the system tick. */ + static __arm __irq void vPortNonPreemptiveTick( void ); + static __arm __irq void vPortNonPreemptiveTick( void ) + { + uint32_t ulDummy; + + /* Increment the tick count - which may wake some tasks but as the + * preemptive scheduler is not being used any woken task is not given + * processor time no matter what its priority. */ + xTaskIncrementTick(); + + /* Clear the PIT interrupt. */ + ulDummy = AT91C_BASE_PITC->PITC_PIVR; + + /* End the interrupt in the AIC. */ + AT91C_BASE_AIC->AIC_EOICR = ulDummy; + } + +#else /* if configUSE_PREEMPTION == 0 */ + +/* Currently the IAR port requires the preemptive tick function to be + * defined in an asm file. */ + +#endif /* if configUSE_PREEMPTION == 0 */ + +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ + AT91PS_PITC pxPIT = AT91C_BASE_PITC; + + /* Setup the AIC for PIT interrupts. The interrupt routine chosen depends + * on whether the preemptive or cooperative scheduler is being used. */ + #if configUSE_PREEMPTION == 0 + AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void ( * )( void ) )vPortNonPreemptiveTick ); + #else + extern void( vPortPreemptiveTick )( void ); + AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void ( * )( void ) )vPortPreemptiveTick ); + #endif + + /* Configure the PIT period. */ + pxPIT->PITC_PIMR = portPIT_ENABLE | portPIT_INT_ENABLE | portPIT_COUNTER_VALUE; + + /* Enable the interrupt. Global interrupts are disabled at this point so + * this is safe. */ + AT91F_AIC_EnableIt( AT91C_BASE_AIC, AT91C_ID_SYS ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + /* Disable interrupts first! */ + __disable_interrupt(); + + /* Now that interrupts are disabled, ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + * re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + __enable_interrupt(); + } + } +} +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/AtmelSAM7S64/portasm.s79 b/portable/IAR/AtmelSAM7S64/portasm.s79 new file mode 100644 index 000000000..4f5f5c083 --- /dev/null +++ b/portable/IAR/AtmelSAM7S64/portasm.s79 @@ -0,0 +1,88 @@ +;/* +; * FreeRTOS Kernel +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + RSEG ICODE:CODE + CODE32 + + EXTERN vTaskSwitchContext + EXTERN xTaskIncrementTick + + PUBLIC vPortYieldProcessor + PUBLIC vPortPreemptiveTick + PUBLIC vPortStartFirstTask + +#include "AT91SAM7S64_inc.h" +#include "ISR_Support.h" + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Starting the first task is just a matter of restoring the context that +; was created by pxPortInitialiseStack(). +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortStartFirstTask: + portRESTORE_CONTEXT + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Manual context switch function. This is the SWI hander. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortYieldProcessor: + ADD LR, LR, #4 ; Add 4 to the LR to make the LR appear exactly + ; as if the context was saved during and IRQ + ; handler. + + portSAVE_CONTEXT ; Save the context of the current task... + LDR R0, =vTaskSwitchContext ; before selecting the next task to execute. + mov lr, pc + BX R0 + portRESTORE_CONTEXT ; Restore the context of the selected task. + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Preemptive context switch function. This will only ever get installed if +; portUSE_PREEMPTION is set to 1 in portmacro.h. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortPreemptiveTick: + portSAVE_CONTEXT ; Save the context of the current task. + + LDR R0, =xTaskIncrementTick ; Increment the tick count - this may wake a task. + mov lr, pc + BX R0 + + CMP R0, #0 + BEQ SkipContextSwitch + LDR R0, =vTaskSwitchContext ; Select the next task to execute. + mov lr, pc + BX R0 +SkipContextSwitch + LDR R14, =AT91C_BASE_PITC ; Clear the PIT interrupt + LDR R0, [R14, #PITC_PIVR ] + + LDR R14, =AT91C_BASE_AIC ; Mark the End of Interrupt on the AIC + STR R14, [R14, #AIC_EOICR] + + portRESTORE_CONTEXT ; Restore the context of the selected task. + + + END diff --git a/portable/IAR/AtmelSAM7S64/portmacro.h b/portable/IAR/AtmelSAM7S64/portmacro.h new file mode 100644 index 000000000..75588d526 --- /dev/null +++ b/portable/IAR/AtmelSAM7S64/portmacro.h @@ -0,0 +1,121 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portYIELD() asm ( "SWI 0" ) +#define portNOP() asm ( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +__arm __interwork void vPortDisableInterruptsFromThumb( void ); +__arm __interwork void vPortEnableInterruptsFromThumb( void ); +__arm __interwork void vPortEnterCritical( void ); +__arm __interwork void vPortExitCritical( void ); + +#define portDISABLE_INTERRUPTS() __disable_interrupt() +#define portENABLE_INTERRUPTS() __enable_interrupt() +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + { \ + extern void vTaskSwitchContext( void ); \ + \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + vTaskSwitchContext(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } +/*-----------------------------------------------------------*/ + + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/IAR/AtmelSAM9XE/ISR_Support.h b/portable/IAR/AtmelSAM9XE/ISR_Support.h new file mode 100644 index 000000000..ac73c7816 --- /dev/null +++ b/portable/IAR/AtmelSAM9XE/ISR_Support.h @@ -0,0 +1,150 @@ +; /* + * ; * FreeRTOS Kernel + * ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * ; * + * ; * SPDX-License-Identifier: MIT + * ; * + * ; * Permission is hereby granted, free of charge, to any person obtaining a copy of + * ; * this software and associated documentation files (the "Software"), to deal in + * ; * the Software without restriction, including without limitation the rights to + * ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * ; * the Software, and to permit persons to whom the Software is furnished to do so, + * ; * subject to the following conditions: + * ; * + * ; * The above copyright notice and this permission notice shall be included in all + * ; * copies or substantial portions of the Software. + * ; * + * ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * ; * + * ; * https://www.FreeRTOS.org + * ; * https://github.com/FreeRTOS + * ; * + * ; */ +EXTERN pxCurrentTCB +EXTERN ulCriticalNesting + +; +Context save and restore macro definitions +; + +portSAVE_CONTEXT MACRO + +; +Push R0 as we are going to use the register. + STMDB SP !, { + R0 +} + +Set R0 to point to the task stack pointer. + STMDB SP, { + SP +} +^ +NOP +SUB SP, SP, # 4 +LDMIA SP !, { + R0 +} + +; +Push the return address onto the stack. + STMDB R0 !, { + LR + } + + Now we have saved LR we can use it instead of R0. + MOV LR, R0 + +; + +Pop R0 so we can save it onto the system mode stack. + LDMIA SP !, { + R0 +} + +Push all the system mode registers onto the task stack. + STMDB LR, { + R0 - LR +} +^ +NOP +SUB LR, LR, # 60 + +; +Push the SPSR onto the task stack. + MRS R0, SPSR +STMDB LR !, { + R0 +} + +LDR R0, = ulCriticalNesting + LDR R0, [ R0 ] +STMDB LR !, { + R0 +} + +Store the new top of stack + +for the task. + LDR R1, = pxCurrentTCB + LDR R0, [ R1 ] +STR LR, [ R0 ] + +ENDM + + +portRESTORE_CONTEXT MACRO + +; +Set the LR to the task stack. + LDR R1, = pxCurrentTCB + LDR R0, [ R1 ] +LDR LR, [ R0 ] + +; +The critical nesting depth is the first item on the stack. + ; +Load it into the ulCriticalNesting variable. + LDR R0, = ulCriticalNesting + LDMFD LR !, { + R1 +} + +STR R1, [ R0 ] + +; +Get the SPSR from the stack. + LDMFD LR !, { + R0 +} +MSR SPSR_cxsf, R0 + +; +Restore all system mode registers + +for the task. + LDMFD LR, { + R0 - R14 +} + +^ +NOP + +; +Restore the return address. + LDR LR, [ LR, # + 60 ] + +; + +And return -correcting the offset in the LR to obtain the +; + +correct address. + SUBS PC, LR, # 4 + +ENDM diff --git a/portable/IAR/AtmelSAM9XE/port.c b/portable/IAR/AtmelSAM9XE/port.c new file mode 100644 index 000000000..f2bd893fc --- /dev/null +++ b/portable/IAR/AtmelSAM9XE/port.c @@ -0,0 +1,253 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the Atmel ARM7 port. +*----------------------------------------------------------*/ + + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Hardware includes. */ +#include +#include +#include +#include +#include +#include +#include +#include + +/*-----------------------------------------------------------*/ + +/* Constants required to setup the initial stack. */ +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) + +/* Constants required to setup the PIT. */ +#define port1MHz_IN_Hz ( 1000000ul ) +#define port1SECOND_IN_uS ( 1000000.0 ) + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + + +#define portINT_LEVEL_SENSITIVE 0 +#define portPIT_ENABLE ( ( uint16_t ) 0x1 << 24 ) +#define portPIT_INT_ENABLE ( ( uint16_t ) 0x1 << 25 ) +/*-----------------------------------------------------------*/ + +/* Setup the PIT to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* The PIT interrupt handler - the RTOS tick. */ +static void vPortTickISR( void ); + +/* ulCriticalNesting will get set to zero when the first task starts. It + * cannot be initialised to 0 as this will cause interrupts to be enabled + * during the kernel initialisation process. */ +uint32_t ulCriticalNesting = ( uint32_t ) 9999; + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + StackType_t * pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + /* To ensure asserts in tasks.c don't fail, although in this case the assert + * is not really required. */ + pxTopOfStack--; + + /* Setup the initial stack of the task. The stack is set exactly as + * expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which in this case is the + * start of the task. The offset is added to make the return address appear + * as it would within an IRQ ISR. */ + *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + * R0. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The status register is set for system mode, with interrupts enabled. */ + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + + #ifdef THUMB_INTERWORK + { + /* We want the task to start in thumb mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + #endif + + pxTopOfStack--; + + /* Interrupt flags cannot always be stored on the stack and will + * instead be stored in a variable, which is then saved as part of the + * tasks context. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + extern void vPortStartFirstTask( void ); + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + * is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +static __arm void vPortTickISR( void ) +{ + volatile uint32_t ulDummy; + + /* Increment the tick count - which may wake some tasks but as the + * preemptive scheduler is not being used any woken task is not given + * processor time no matter what its priority. */ + if( xTaskIncrementTick() != pdFALSE ) + { + vTaskSwitchContext(); + } + + /* Clear the PIT interrupt. */ + ulDummy = AT91C_BASE_PITC->PITC_PIVR; + + /* To remove compiler warning. */ + ( void ) ulDummy; + + /* The AIC is cleared in the asm wrapper, outside of this function. */ +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ + const uint32_t ulPeriodIn_uS = ( 1.0 / ( double ) configTICK_RATE_HZ ) * port1SECOND_IN_uS; + + /* Setup the PIT for the required frequency. */ + PIT_Init( ulPeriodIn_uS, BOARD_MCK / port1MHz_IN_Hz ); + + /* Setup the PIT interrupt. */ + AIC_DisableIT( AT91C_ID_SYS ); + AIC_ConfigureIT( AT91C_ID_SYS, AT91C_AIC_PRIOR_LOWEST, vPortTickISR ); + AIC_EnableIT( AT91C_ID_SYS ); + PIT_EnableIT(); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + /* Disable interrupts first! */ + __disable_irq(); + + /* Now that interrupts are disabled, ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + * re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + __enable_irq(); + } + } +} +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/AtmelSAM9XE/portasm.s79 b/portable/IAR/AtmelSAM9XE/portasm.s79 new file mode 100644 index 000000000..37241da9c --- /dev/null +++ b/portable/IAR/AtmelSAM9XE/portasm.s79 @@ -0,0 +1,60 @@ +;/* +; * FreeRTOS Kernel +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + RSEG ICODE:CODE + CODE32 + + EXTERN vTaskSwitchContext + + PUBLIC vPortYieldProcessor + PUBLIC vPortStartFirstTask + +#include "ISR_Support.h" + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Starting the first task is just a matter of restoring the context that +; was created by pxPortInitialiseStack(). +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortStartFirstTask: + portRESTORE_CONTEXT + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Manual context switch function. This is the SWI hander. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortYieldProcessor: + ADD LR, LR, #4 ; Add 4 to the LR to make the LR appear exactly + ; as if the context was saved during and IRQ + ; handler. + + portSAVE_CONTEXT ; Save the context of the current task... + LDR R0, =vTaskSwitchContext ; before selecting the next task to execute. + mov lr, pc + BX R0 + portRESTORE_CONTEXT ; Restore the context of the selected task. + + + END diff --git a/portable/IAR/AtmelSAM9XE/portmacro.h b/portable/IAR/AtmelSAM9XE/portmacro.h new file mode 100644 index 000000000..68e54c8d3 --- /dev/null +++ b/portable/IAR/AtmelSAM9XE/portmacro.h @@ -0,0 +1,124 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#include + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portYIELD() asm ( "SWI 0" ) +#define portNOP() asm ( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +__arm __interwork void vPortDisableInterruptsFromThumb( void ); +__arm __interwork void vPortEnableInterruptsFromThumb( void ); +__arm __interwork void vPortEnterCritical( void ); +__arm __interwork void vPortExitCritical( void ); + +#define portDISABLE_INTERRUPTS() __disable_irq() +#define portENABLE_INTERRUPTS() __enable_irq() +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + { \ + extern void vTaskSwitchContext( void ); \ + \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + vTaskSwitchContext(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } +/*-----------------------------------------------------------*/ + + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/IAR/LPC2000/ISR_Support.h b/portable/IAR/LPC2000/ISR_Support.h new file mode 100644 index 000000000..273e95141 --- /dev/null +++ b/portable/IAR/LPC2000/ISR_Support.h @@ -0,0 +1,151 @@ +; /* + * ; * FreeRTOS Kernel + * ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * ; * + * ; * SPDX-License-Identifier: MIT + * ; * + * ; * Permission is hereby granted, free of charge, to any person obtaining a copy of + * ; * this software and associated documentation files (the "Software"), to deal in + * ; * the Software without restriction, including without limitation the rights to + * ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * ; * the Software, and to permit persons to whom the Software is furnished to do so, + * ; * subject to the following conditions: + * ; * + * ; * The above copyright notice and this permission notice shall be included in all + * ; * copies or substantial portions of the Software. + * ; * + * ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * ; * + * ; * https://www.FreeRTOS.org + * ; * https://github.com/FreeRTOS + * ; * + * ; */ + +EXTERN pxCurrentTCB +EXTERN ulCriticalNesting + +; +Context save and restore macro definitions +; + +portSAVE_CONTEXT MACRO + +; +Push R0 as we are going to use the register. + STMDB SP !, { + R0 +} + +Set R0 to point to the task stack pointer. + STMDB SP, { + SP +} +^ +NOP +SUB SP, SP, # 4 +LDMIA SP !, { + R0 +} + +; +Push the return address onto the stack. + STMDB R0 !, { + LR + } + + Now we have saved LR we can use it instead of R0. + MOV LR, R0 + +; + +Pop R0 so we can save it onto the system mode stack. + LDMIA SP !, { + R0 +} + +Push all the system mode registers onto the task stack. + STMDB LR, { + R0 - LR +} +^ +NOP +SUB LR, LR, # 60 + +; +Push the SPSR onto the task stack. + MRS R0, SPSR +STMDB LR !, { + R0 +} + +LDR R0, = ulCriticalNesting + LDR R0, [ R0 ] +STMDB LR !, { + R0 +} + +Store the new top of stack + +for the task. + LDR R1, = pxCurrentTCB + LDR R0, [ R1 ] +STR LR, [ R0 ] + +ENDM + + +portRESTORE_CONTEXT MACRO + +; +Set the LR to the task stack. + LDR R1, = pxCurrentTCB + LDR R0, [ R1 ] +LDR LR, [ R0 ] + +; +The critical nesting depth is the first item on the stack. + ; +Load it into the ulCriticalNesting variable. + LDR R0, = ulCriticalNesting + LDMFD LR !, { + R1 +} + +STR R1, [ R0 ] + +; +Get the SPSR from the stack. + LDMFD LR !, { + R0 +} +MSR SPSR_cxsf, R0 + +; +Restore all system mode registers + +for the task. + LDMFD LR, { + R0 - R14 +} + +^ +NOP + +; +Restore the return address. + LDR LR, [ LR, # + 60 ] + +; + +And return -correcting the offset in the LR to obtain the +; + +correct address. + SUBS PC, LR, # 4 + +ENDM diff --git a/portable/IAR/LPC2000/port.c b/portable/IAR/LPC2000/port.c new file mode 100644 index 000000000..69d711d3b --- /dev/null +++ b/portable/IAR/LPC2000/port.c @@ -0,0 +1,314 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the Philips ARM7 port. +*----------------------------------------------------------*/ + +/* + * Changes from V3.2.2 + * + + Bug fix - The prescale value for the timer setup is now written to T0PR + + instead of T0PC. This bug would have had no effect unless a prescale + + value was actually used. + */ + +/* Standard includes. */ +#include +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to setup the tick ISR. */ +#define portENABLE_TIMER ( ( uint8_t ) 0x01 ) +#define portPRESCALE_VALUE 0x00 +#define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 ) +#define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 ) + +/* Constants required to setup the initial stack. */ +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) + +/* Constants required to setup the PIT. */ +#define portPIT_CLOCK_DIVISOR ( ( uint32_t ) 16 ) +#define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_PERIOD_MS ) + +/* Constants required to handle interrupts. */ +#define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 ) +#define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 ) + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + + +#define portINT_LEVEL_SENSITIVE 0 +#define portPIT_ENABLE ( ( uint16_t ) 0x1 << 24 ) +#define portPIT_INT_ENABLE ( ( uint16_t ) 0x1 << 25 ) + +/* Constants required to setup the VIC for the tick ISR. */ +#define portTIMER_VIC_CHANNEL ( ( uint32_t ) 0x0004 ) +#define portTIMER_VIC_CHANNEL_BIT ( ( uint32_t ) 0x0010 ) +#define portTIMER_VIC_ENABLE ( ( uint32_t ) 0x0020 ) + +/*-----------------------------------------------------------*/ + +/* Setup the PIT to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* ulCriticalNesting will get set to zero when the first task starts. It + * cannot be initialised to 0 as this will cause interrupts to be enabled + * during the kernel initialisation process. */ +uint32_t ulCriticalNesting = ( uint32_t ) 9999; + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + StackType_t * pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + /* Setup the initial stack of the task. The stack is set exactly as + * expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which in this case is the + * start of the task. The offset is added to make the return address appear + * as it would within an IRQ ISR. */ + *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + * R0. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The status register is set for system mode, with interrupts enabled. */ + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + + if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00UL ) + { + /* We want the task to start in thumb mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + + pxTopOfStack--; + + /* Interrupt flags cannot always be stored on the stack and will + * instead be stored in a variable, which is then saved as part of the + * tasks context. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + extern void vPortStartFirstTask( void ); + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + * is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +#if configUSE_PREEMPTION == 0 + +/* The cooperative scheduler requires a normal IRQ service routine to + * simply increment the system tick. */ + static __arm __irq void vPortNonPreemptiveTick( void ); + static __arm __irq void vPortNonPreemptiveTick( void ) + { + /* Increment the tick count - which may wake some tasks but as the + * preemptive scheduler is not being used any woken task is not given + * processor time no matter what its priority. */ + xTaskIncrementTick(); + + /* Ready for the next interrupt. */ + T0IR = portTIMER_MATCH_ISR_BIT; + VICVectAddr = portCLEAR_VIC_INTERRUPT; + } + +#else /* if configUSE_PREEMPTION == 0 */ + +/* This function is called from an asm wrapper, so does not require the __irq + * keyword. */ + void vPortPreemptiveTick( void ); + void vPortPreemptiveTick( void ) + { + /* Increment the tick counter. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* The new tick value might unblock a task. Ensure the highest task that + * is ready to execute is the task that will execute when the tick ISR + * exits. */ + vTaskSwitchContext(); + } + + /* Ready for the next interrupt. */ + T0IR = portTIMER_MATCH_ISR_BIT; + VICVectAddr = portCLEAR_VIC_INTERRUPT; + } + +#endif /* if configUSE_PREEMPTION == 0 */ + +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ + uint32_t ulCompareMatch; + + /* A 1ms tick does not require the use of the timer prescale. This is + * defaulted to zero but can be used if necessary. */ + T0PR = portPRESCALE_VALUE; + + /* Calculate the match value required for our wanted tick rate. */ + ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ; + + /* Protect against divide by zero. Using an if() statement still results + * in a warning - hence the #if. */ + #if portPRESCALE_VALUE != 0 + { + ulCompareMatch /= ( portPRESCALE_VALUE + 1 ); + } + #endif + + T0MR0 = ulCompareMatch; + + /* Generate tick with timer 0 compare match. */ + T0MCR = portRESET_COUNT_ON_MATCH | portINTERRUPT_ON_MATCH; + + /* Setup the VIC for the timer. */ + VICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT ); + VICIntEnable |= portTIMER_VIC_CHANNEL_BIT; + + /* The ISR installed depends on whether the preemptive or cooperative + * scheduler is being used. */ + #if configUSE_PREEMPTION == 1 + { + extern void( vPortPreemptiveTickEntry )( void ); + + VICVectAddr0 = ( uint32_t ) vPortPreemptiveTickEntry; + } + #else + { + extern void( vNonPreemptiveTick )( void ); + + VICVectAddr0 = ( int32_t ) vPortNonPreemptiveTick; + } + #endif /* if configUSE_PREEMPTION == 1 */ + + VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE; + + /* Start the timer - interrupts are disabled when this function is called + * so it is okay to do this here. */ + T0TCR = portENABLE_TIMER; +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + /* Disable interrupts first! */ + __disable_interrupt(); + + /* Now that interrupts are disabled, ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + * re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + __enable_interrupt(); + } + } +} +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/LPC2000/portasm.s79 b/portable/IAR/LPC2000/portasm.s79 new file mode 100644 index 000000000..2bd1ccc06 --- /dev/null +++ b/portable/IAR/LPC2000/portasm.s79 @@ -0,0 +1,76 @@ +;/* +; * FreeRTOS Kernel +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + + RSEG ICODE:CODE + CODE32 + + EXTERN vTaskSwitchContext + EXTERN vPortPreemptiveTick + + PUBLIC vPortPreemptiveTickEntry + PUBLIC vPortYieldProcessor + PUBLIC vPortStartFirstTask + +#include "FreeRTOSConfig.h" +#include "ISR_Support.h" + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Starting the first task is just a matter of restoring the context that +; was created by pxPortInitialiseStack(). +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortStartFirstTask: + portRESTORE_CONTEXT + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Manual context switch function. This is the SWI hander. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortYieldProcessor: + ADD LR, LR, #4 ; Add 4 to the LR to make the LR appear exactly + ; as if the context was saved during and IRQ + ; handler. + + portSAVE_CONTEXT ; Save the context of the current task... + LDR R0, =vTaskSwitchContext ; before selecting the next task to execute. + mov lr, pc + BX R0 + portRESTORE_CONTEXT ; Restore the context of the selected task. + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Preemptive context switch function. This will only ever get installed if +; portUSE_PREEMPTION is set to 1 in portmacro.h. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortPreemptiveTickEntry: +#if configUSE_PREEMPTION == 1 + portSAVE_CONTEXT ; Save the context of the current task... + LDR R0, =vPortPreemptiveTick; before selecting the next task to execute. + mov lr, pc + BX R0 + portRESTORE_CONTEXT ; Restore the context of the selected task. +#endif + + END diff --git a/portable/IAR/LPC2000/portmacro.h b/portable/IAR/LPC2000/portmacro.h new file mode 100644 index 000000000..b44d307f3 --- /dev/null +++ b/portable/IAR/LPC2000/portmacro.h @@ -0,0 +1,123 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#include + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portYIELD() asm ( "SWI 0" ) +#define portNOP() asm ( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +__arm __interwork void vPortDisableInterruptsFromThumb( void ); +__arm __interwork void vPortEnableInterruptsFromThumb( void ); +__arm __interwork void vPortEnterCritical( void ); +__arm __interwork void vPortExitCritical( void ); + +#define portDISABLE_INTERRUPTS() __disable_interrupt() +#define portENABLE_INTERRUPTS() __enable_interrupt() +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + { \ + extern void vTaskSwitchContext( void ); \ + \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + vTaskSwitchContext(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/IAR/MSP430/port.c b/portable/IAR/MSP430/port.c new file mode 100644 index 000000000..070f64bf0 --- /dev/null +++ b/portable/IAR/MSP430/port.c @@ -0,0 +1,173 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the MSP430 port. +*----------------------------------------------------------*/ + +/* Constants required for hardware setup. The tick ISR runs off the ACLK, + * not the MCLK. */ +#define portACLK_FREQUENCY_HZ ( ( TickType_t ) 32768 ) +#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 ) +#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x08 ) + +/* We require the address of the pxCurrentTCB variable, but don't want to know + * any details of its type. */ +typedef void TCB_t; +extern volatile TCB_t * volatile pxCurrentTCB; + +/* Each task maintains a count of the critical section nesting depth. Each + * time a critical section is entered the count is incremented. Each time a + * critical section is exited the count is decremented - with interrupts only + * being re-enabled if the count is zero. + * + * usCriticalNesting will get set to zero when the scheduler starts, but must + * not be initialised to zero as this will cause problems during the startup + * sequence. */ +volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING; +/*-----------------------------------------------------------*/ + + +/* + * Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but + * could have alternatively used the watchdog timer or timer 1. + */ +void vPortSetupTimerInterrupt( void ); +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See the header file portable.h. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* + * Place a few bytes of known values on the bottom of the stack. + * This is just useful for debugging and can be included if required. + * + * pxTopOfStack = ( StackType_t ) 0x1111; + * pxTopOfStack--; + * pxTopOfStack = ( StackType_t ) 0x2222; + * pxTopOfStack--; + * pxTopOfStack = ( StackType_t ) 0x3333; + * pxTopOfStack--; + */ + + /* The msp430 automatically pushes the PC then SR onto the stack before + * executing an ISR. We want the stack to look just as if this has happened + * so place a pointer to the start of the task on the stack first - followed + * by the flags we want the task to use when it starts up. */ + *pxTopOfStack = ( StackType_t ) pxCode; + pxTopOfStack--; + *pxTopOfStack = portFLAGS_INT_ENABLED; + pxTopOfStack--; + + /* Next the general purpose registers. */ + *pxTopOfStack = ( StackType_t ) 0x4444; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x5555; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x6666; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x7777; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x8888; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x9999; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xaaaa; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xbbbb; + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + * R15. */ + *pxTopOfStack = ( StackType_t ) pvParameters; + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0xdddd; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xeeee; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xffff; + pxTopOfStack--; + + /* A variable is used to keep track of the critical section nesting. + * This variable has to be stored as part of the task context and is + * initially set to zero. */ + *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING; + + /* Return a pointer to the top of the stack we have generated so this can + * be stored in the task control block for the task. */ + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the MSP430 port will get stopped. If required simply + * disable the tick interrupt here. */ +} +/*-----------------------------------------------------------*/ + +/* + * Hardware initialisation to generate the RTOS tick. This uses timer 0 + * but could alternatively use the watchdog timer or timer 1. + */ +void vPortSetupTimerInterrupt( void ) +{ + /* Ensure the timer is stopped. */ + TACTL = 0; + + /* Run the timer of the ACLK. */ + TACTL = TASSEL_1; + + /* Clear everything to start with. */ + TACTL |= TACLR; + + /* Set the compare match value according to the tick rate we want. */ + TACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ; + + /* Enable the interrupts. */ + TACCTL0 = CCIE; + + /* Start up clean. */ + TACTL |= TACLR; + + /* Up mode. */ + TACTL |= MC_1; +} +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/MSP430/portasm.h b/portable/IAR/MSP430/portasm.h new file mode 100644 index 000000000..0d8115034 --- /dev/null +++ b/portable/IAR/MSP430/portasm.h @@ -0,0 +1,84 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTASM_H +#define PORTASM_H + +portSAVE_CONTEXT macro + + IMPORT pxCurrentTCB + IMPORT usCriticalNesting + + /* Save the remaining registers. */ + push r4 + push r5 + push r6 + push r7 + push r8 + push r9 + push r10 + push r11 + push r12 + push r13 + push r14 + push r15 + mov.w &usCriticalNesting, r14 + push r14 + mov.w &pxCurrentTCB, r12 + mov.w r1, 0(r12) + endm +/*-----------------------------------------------------------*/ + +portRESTORE_CONTEXT macro + mov.w &pxCurrentTCB, r12 + mov.w @r12, r1 + pop r15 + mov.w r15, &usCriticalNesting + pop r15 + pop r14 + pop r13 + pop r12 + pop r11 + pop r10 + pop r9 + pop r8 + pop r7 + pop r6 + pop r5 + pop r4 + + /* The last thing on the stack will be the status register. + * Ensure the power down bits are clear ready for the next + * time this power down register is popped from the stack. */ + bic.w #0xf0, 0(SP) + + reti + endm +/*-----------------------------------------------------------*/ + +#endif /* ifndef PORTASM_H */ diff --git a/portable/IAR/MSP430/portext.s43 b/portable/IAR/MSP430/portext.s43 new file mode 100644 index 000000000..bfe6a190f --- /dev/null +++ b/portable/IAR/MSP430/portext.s43 @@ -0,0 +1,106 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ +#include "FreeRTOSConfig.h" +#include "portasm.h" + + IMPORT xTaskIncrementTick + IMPORT vTaskSwitchContext + IMPORT vPortSetupTimerInterrupt + + EXPORT vTickISR + EXPORT vPortYield + EXPORT xPortStartScheduler + + RSEG CODE + +/* + * The RTOS tick ISR. + * + * If the cooperative scheduler is in use this simply increments the tick + * count. + * + * If the preemptive scheduler is in use a context switch can also occur. + */ +vTickISR: + portSAVE_CONTEXT + + call #xTaskIncrementTick + cmp.w #0x0, R12 + jeq SkipContextSwitch + call #vTaskSwitchContext +SkipContextSwitch: + + portRESTORE_CONTEXT +/*-----------------------------------------------------------*/ + + +/* + * Manual context switch called by the portYIELD() macro. + */ +vPortYield: + + /* Mimic an interrupt by pushing the SR. */ + push SR + + /* Now the SR is stacked we can disable interrupts. */ + dint + + /* Save the context of the current task. */ + portSAVE_CONTEXT + + /* Switch to the highest priority task that is ready to run. */ + call #vTaskSwitchContext + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT +/*-----------------------------------------------------------*/ + + +/* + * Start off the scheduler by initialising the RTOS tick timer, then restoring + * the context of the first task. + */ +xPortStartScheduler: + + /* Setup the hardware to generate the tick. Interrupts are disabled + when this function is called. */ + call #vPortSetupTimerInterrupt + + /* Restore the context of the first task that is going to run. */ + portRESTORE_CONTEXT +/*-----------------------------------------------------------*/ + + + /* Install vTickISR as the timer A0 interrupt. */ + ASEG + ORG 0xFFE0 + TIMERA0_VECTOR + + _vTickISR_: DC16 vTickISR + + + END diff --git a/portable/IAR/MSP430/portmacro.h b/portable/IAR/MSP430/portmacro.h new file mode 100644 index 000000000..f87bfe589 --- /dev/null +++ b/portable/IAR/MSP430/portmacro.h @@ -0,0 +1,135 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE uint16_t +#define portBASE_TYPE short + +typedef portSTACK_TYPE StackType_t; +typedef short BaseType_t; +typedef unsigned short UBaseType_t; + + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif + +/*-----------------------------------------------------------*/ + +/* Interrupt control macros. */ +#define portDISABLE_INTERRUPTS() _DINT(); _NOP() +#define portENABLE_INTERRUPTS() _EINT(); _NOP() +/*-----------------------------------------------------------*/ + +/* Critical section control macros. */ +#define portNO_CRITICAL_SECTION_NESTING ( ( uint16_t ) 0 ) + +#define portENTER_CRITICAL() \ + { \ + extern volatile uint16_t usCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + \ + /* Now interrupts are disabled usCriticalNesting can be accessed */ \ + /* directly. Increment ulCriticalNesting to keep a count of how many */ \ + /* times portENTER_CRITICAL() has been called. */ \ + usCriticalNesting++; \ + } + +#define portEXIT_CRITICAL() \ + { \ + extern volatile uint16_t usCriticalNesting; \ + \ + if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ + { \ + /* Decrement the nesting count as we are leaving a critical section. */ \ + usCriticalNesting--; \ + \ + /* If the nesting level has reached zero then interrupts should be */ \ + /* re-enabled. */ \ + if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } \ + } +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* + * Manual context switch called by portYIELD or taskYIELD. + */ +extern void vPortYield( void ); +#define portYIELD() vPortYield() +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 2 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() +#define portPOINTER_SIZE_TYPE uint16_t +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +#if configINTERRUPT_EXAMPLE_METHOD == 2 + + extern void vTaskSwitchContext( void ); + #define portYIELD_FROM_ISR( x ) do { if( x ) vTaskSwitchContext( ); } while( 0 ) + +#endif + +#endif /* PORTMACRO_H */ diff --git a/portable/IAR/MSP430X/data_model.h b/portable/IAR/MSP430X/data_model.h new file mode 100644 index 000000000..0d5dcbdd4 --- /dev/null +++ b/portable/IAR/MSP430X/data_model.h @@ -0,0 +1,63 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef DATA_MODEL_H +#define DATA_MODEL_H + +#if __DATA_MODEL__ == __DATA_MODEL_SMALL__ + #define pushm_x pushm.w + #define popm_x popm.w + #define push_x push.w + #define pop_x pop.w + #define mov_x mov.w + #define cmp_x cmp.w +#endif + +#if __DATA_MODEL__ == __DATA_MODEL_MEDIUM__ + #define pushm_x pushm.a + #define popm_x popm.a + #define push_x pushx.a + #define pop_x popx.a + #define mov_x mov.w + #define cmp_x cmp.w +#endif + +#if __DATA_MODEL__ == __DATA_MODEL_LARGE__ + #define pushm_x pushm.a + #define popm_x popm.a + #define push_x pushx.a + #define pop_x popx.a + #define mov_x movx.a + #define cmp_x cmpx.a +#endif + +#ifndef pushm_x + #error The assembler options must define one of the following symbols: __DATA_MODEL_SMALL__, __DATA_MODEL_MEDIUM__, or __DATA_MODEL_LARGE__ +#endif + +#endif /* DATA_MODEL_H */ diff --git a/portable/IAR/MSP430X/port.c b/portable/IAR/MSP430X/port.c new file mode 100644 index 000000000..6c5b21c3a --- /dev/null +++ b/portable/IAR/MSP430X/port.c @@ -0,0 +1,187 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Hardware includes. */ +#include "msp430.h" + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the MSP430X port. +*----------------------------------------------------------*/ + +/* Constants required for hardware setup. The tick ISR runs off the ACLK, + * not the MCLK. */ +#define portACLK_FREQUENCY_HZ ( ( TickType_t ) 32768 ) +#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 ) +#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x08 ) + +/* We require the address of the pxCurrentTCB variable, but don't want to know + * any details of its type. */ +typedef void TCB_t; +extern volatile TCB_t * volatile pxCurrentTCB; + +/* Each task maintains a count of the critical section nesting depth. Each + * time a critical section is entered the count is incremented. Each time a + * critical section is exited the count is decremented - with interrupts only + * being re-enabled if the count is zero. + * + * usCriticalNesting will get set to zero when the scheduler starts, but must + * not be initialised to zero as this will cause problems during the startup + * sequence. */ +volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING; +/*-----------------------------------------------------------*/ + + +/* + * Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but + * could have alternatively used the watchdog timer or timer 1. + */ +void vPortSetupTimerInterrupt( void ); +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See the header file portable.h. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + uint16_t * pusTopOfStack; + uint32_t * pulTopOfStack; + + /* + * Place a few bytes of known values on the bottom of the stack. + * This is just useful for debugging and can be included if required. + * + * pxTopOfStack = ( StackType_t ) 0x1111; + * pxTopOfStack--; + * pxTopOfStack = ( StackType_t ) 0x2222; + * pxTopOfStack--; + * pxTopOfStack = ( StackType_t ) 0x3333; + */ + + /* StackType_t is either 16 bits or 32 bits depending on the data model. + * Some stacked items do not change size depending on the data model so have + * to be explicitly cast to the correct size so this function will work + * whichever data model is being used. */ + if( sizeof( StackType_t ) == sizeof( uint16_t ) ) + { + /* Make room for a 20 bit value stored as a 32 bit value. */ + pusTopOfStack = ( uint16_t * ) pxTopOfStack; + pusTopOfStack--; + pulTopOfStack = ( uint32_t * ) pusTopOfStack; + } + else + { + pulTopOfStack = ( uint32_t * ) pxTopOfStack; + } + + *pulTopOfStack = ( uint32_t ) pxCode; + + pusTopOfStack = ( uint16_t * ) pulTopOfStack; + pusTopOfStack--; + *pusTopOfStack = portFLAGS_INT_ENABLED; + pusTopOfStack -= ( sizeof( StackType_t ) / 2 ); + + /* From here on the size of stacked items depends on the memory model. */ + pxTopOfStack = ( StackType_t * ) pusTopOfStack; + + /* Next the general purpose registers. */ + #ifdef PRELOAD_REGISTER_VALUES + *pxTopOfStack = ( StackType_t ) 0xffff; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xeeee; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xdddd; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xbbbb; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xaaaa; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x9999; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x8888; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x5555; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x6666; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x5555; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x4444; + pxTopOfStack--; + #else /* ifdef PRELOAD_REGISTER_VALUES */ + pxTopOfStack -= 3; + *pxTopOfStack = ( StackType_t ) pvParameters; + pxTopOfStack -= 9; + #endif /* ifdef PRELOAD_REGISTER_VALUES */ + + + /* A variable is used to keep track of the critical section nesting. + * This variable has to be stored as part of the task context and is + * initially set to zero. */ + *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING; + + /* Return a pointer to the top of the stack we have generated so this can + * be stored in the task control block for the task. */ + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the MSP430 port will get stopped. If required simply + * disable the tick interrupt here. */ +} +/*-----------------------------------------------------------*/ + +/* + * Hardware initialisation to generate the RTOS tick. + */ +void vPortSetupTimerInterrupt( void ) +{ + vApplicationSetupTimerInterrupt(); +} +/*-----------------------------------------------------------*/ + +#pragma vector=configTICK_VECTOR +__interrupt __raw void vTickISREntry( void ) +{ + extern void vPortTickISR( void ); + + __bic_SR_register_on_exit( SCG1 + SCG0 + OSCOFF + CPUOFF ); + vPortTickISR(); +} diff --git a/portable/IAR/MSP430X/portext.s43 b/portable/IAR/MSP430X/portext.s43 new file mode 100644 index 000000000..ccfd084c2 --- /dev/null +++ b/portable/IAR/MSP430X/portext.s43 @@ -0,0 +1,138 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ +#include "msp430.h" +#include "FreeRTOSConfig.h" +#include "data_model.h" + + IMPORT xTaskIncrementTick + IMPORT vTaskSwitchContext + IMPORT vPortSetupTimerInterrupt + IMPORT pxCurrentTCB + IMPORT usCriticalNesting + + EXPORT vPortTickISR + EXPORT vPortYield + EXPORT xPortStartScheduler + +portSAVE_CONTEXT macro + + /* Save the remaining registers. */ + pushm_x #12, r15 + mov.w &usCriticalNesting, r14 + push_x r14 + mov_x &pxCurrentTCB, r12 + mov_x sp, 0( r12 ) + endm +/*-----------------------------------------------------------*/ + +portRESTORE_CONTEXT macro + + mov_x &pxCurrentTCB, r12 + mov_x @r12, sp + pop_x r15 + mov.w r15, &usCriticalNesting + popm_x #12, r15 + nop + pop.w sr + nop + reta + endm +/*-----------------------------------------------------------*/ + + +/* + * The RTOS tick ISR. + * + * If the cooperative scheduler is in use this simply increments the tick + * count. + * + * If the preemptive scheduler is in use a context switch can also occur. + */ + + RSEG CODE + EVEN + +vPortTickISR: + + /* The sr is not saved in portSAVE_CONTEXT() because vPortYield() needs + to save it manually before it gets modified (interrupts get disabled). + Entering through this interrupt means the SR is already on the stack, but + this keeps the stack frames identical. */ + push.w sr + portSAVE_CONTEXT + + calla #xTaskIncrementTick + cmp.w #0x0, R12 + jeq SkipContextSwitch + calla #vTaskSwitchContext +SkipContextSwitch: + portRESTORE_CONTEXT +/*-----------------------------------------------------------*/ + +/* + * Manual context switch called by the portYIELD() macro. + */ + EVEN + +vPortYield: + + /* The sr needs saving before it is modified. */ + push.w sr + + /* Now the SR is stacked interrupts can be disabled. */ + dint + nop + + /* Save the context of the current task. */ + portSAVE_CONTEXT + + /* Select the next task to run. */ + calla #vTaskSwitchContext + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT +/*-----------------------------------------------------------*/ + + +/* + * Start off the scheduler by initialising the RTOS tick timer, then restoring + * the context of the first task. + */ + EVEN + +xPortStartScheduler: + + /* Setup the hardware to generate the tick. Interrupts are disabled + when this function is called. */ + calla #vPortSetupTimerInterrupt + + /* Restore the context of the first task that is going to run. */ + portRESTORE_CONTEXT +/*-----------------------------------------------------------*/ + + END diff --git a/portable/IAR/MSP430X/portmacro.h b/portable/IAR/MSP430X/portmacro.h new file mode 100644 index 000000000..b428f8d40 --- /dev/null +++ b/portable/IAR/MSP430X/portmacro.h @@ -0,0 +1,141 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portBASE_TYPE short + +/* The stack type changes depending on the data model. */ +#if ( __DATA_MODEL__ == __DATA_MODEL_SMALL__ ) + #define portSTACK_TYPE uint16_t + #define portPOINTER_SIZE_TYPE uint16_t +#else + #define portSTACK_TYPE uint32_t +#endif + +typedef portSTACK_TYPE StackType_t; +typedef short BaseType_t; +typedef unsigned short UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif + +/*-----------------------------------------------------------*/ + +/* Interrupt control macros. */ +#define portDISABLE_INTERRUPTS() __asm volatile ( "DINT\n" "NOP" ) +#define portENABLE_INTERRUPTS() __asm volatile ( "NOP\n" "EINT\n" "NOP" ) +/*-----------------------------------------------------------*/ + +/* Critical section control macros. */ +#define portNO_CRITICAL_SECTION_NESTING ( ( uint16_t ) 0 ) + +#define portENTER_CRITICAL() \ + { \ + extern volatile uint16_t usCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + \ + /* Now interrupts are disabled usCriticalNesting can be accessed */ \ + /* directly. Increment ulCriticalNesting to keep a count of how many */ \ + /* times portENTER_CRITICAL() has been called. */ \ + usCriticalNesting++; \ + } + +#define portEXIT_CRITICAL() \ + { \ + extern volatile uint16_t usCriticalNesting; \ + \ + if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ + { \ + /* Decrement the nesting count as we are leaving a critical section. */ \ + usCriticalNesting--; \ + \ + /* If the nesting level has reached zero then interrupts should be */ \ + /* re-enabled. */ \ + if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } \ + } +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* + * Manual context switch called by portYIELD or taskYIELD. + */ +extern void vPortYield( void ); +#define portYIELD() vPortYield() +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 2 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() __asm volatile ( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +#define portYIELD_FROM_ISR( x ) do { if( x ) vPortYield( ); } while( 0 ) + +void vApplicationSetupTimerInterrupt( void ); + +/* sizeof( int ) != sizeof( long ) so a full printf() library is required if + * run time stats information is to be displayed. */ +#define portLU_PRINTF_SPECIFIER_REQUIRED + +#endif /* PORTMACRO_H */ diff --git a/portable/IAR/RISC-V/Documentation.url b/portable/IAR/RISC-V/Documentation.url new file mode 100644 index 000000000..5546f8707 --- /dev/null +++ b/portable/IAR/RISC-V/Documentation.url @@ -0,0 +1,5 @@ +[{000214A0-0000-0000-C000-000000000046}] +Prop3=19,11 +[InternetShortcut] +IDList= +URL=https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html diff --git a/portable/IAR/RISC-V/chip_extensions.cmake b/portable/IAR/RISC-V/chip_extensions.cmake new file mode 100644 index 000000000..110ec4a2e --- /dev/null +++ b/portable/IAR/RISC-V/chip_extensions.cmake @@ -0,0 +1,16 @@ +if( FREERTOS_PORT STREQUAL "IAR_RISC_V_GENERIC" ) + set( VALID_CHIP_EXTENSIONS + "RV32I_CLINT_no_extensions" ) + + if( ( NOT FREERTOS_RISCV_EXTENSION ) OR ( NOT ( ${FREERTOS_RISCV_EXTENSION} IN_LIST VALID_CHIP_EXTENSIONS ) ) ) + message(FATAL_ERROR + "FREERTOS_RISCV_EXTENSION \"${FREERTOS_RISCV_EXTENSION}\" is not set or unsupported.\n" + "Please specify it from top-level CMake file (example):\n" + " set(FREERTOS_RISCV_EXTENSION RISCV_MTIME_CLINT_no_extensions CACHE STRING \"\")\n" + " or from CMake command line option:\n" + " -DFREERTOS_RISCV_EXTENSION=RISCV_MTIME_CLINT_no_extensions\n" + "\n" + " Available extension options:\n" + " ${VALID_CHIP_EXTENSIONS} \n") + endif() +endif() diff --git a/portable/IAR/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h b/portable/IAR/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h new file mode 100644 index 000000000..364fd5773 --- /dev/null +++ b/portable/IAR/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h @@ -0,0 +1,69 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * The FreeRTOS kernel's RISC-V port is split between the the code that is + * common across all currently supported RISC-V chips (implementations of the + * RISC-V ISA), and code that tailors the port to a specific RISC-V chip: + * + * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that + * is common to all currently supported RISC-V chips. There is only one + * portASM.S file because the same file is built for all RISC-V target chips. + * + * + Header files called freertos_risc_v_chip_specific_extensions.h contain the + * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V + * chip. There are multiple freertos_risc_v_chip_specific_extensions.h files + * as there are multiple RISC-V chip implementations. + * + * !!!NOTE!!! + * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h + * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the + * compiler's!) include path. For example, if the chip in use includes a core + * local interrupter (CLINT) and does not include any chip specific register + * extensions then add the path below to the assembler's include path: + * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions + * + */ + + +#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__ +#define __FREERTOS_RISC_V_EXTENSIONS_H__ + +#define portasmHAS_SIFIVE_CLINT 1 +#define portasmHAS_MTIME 1 +#define portasmADDITIONAL_CONTEXT_SIZE 0 /* Must be even number on 32-bit cores. */ + +portasmSAVE_ADDITIONAL_REGISTERS MACRO +/* No additional registers to save, so this macro does nothing. */ +ENDM + +portasmRESTORE_ADDITIONAL_REGISTERS MACRO +/* No additional registers to restore, so this macro does nothing. */ + ENDM + +#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */ diff --git a/portable/IAR/RISC-V/chip_specific_extensions/readme.txt b/portable/IAR/RISC-V/chip_specific_extensions/readme.txt new file mode 100644 index 000000000..b24c0b9fb --- /dev/null +++ b/portable/IAR/RISC-V/chip_specific_extensions/readme.txt @@ -0,0 +1,23 @@ +/* + * The FreeRTOS kernel's RISC-V port is split between the the code that is + * common across all currently supported RISC-V chips (implementations of the + * RISC-V ISA), and code that tailors the port to a specific RISC-V chip: + * + * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that + * is common to all currently supported RISC-V chips. There is only one + * portASM.S file because the same file is built for all RISC-V target chips. + * + * + Header files called freertos_risc_v_chip_specific_extensions.h contain the + * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V + * chip. There are multiple freertos_risc_v_chip_specific_extensions.h files + * as there are multiple RISC-V chip implementations. + * + * !!!NOTE!!! + * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h + * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the + * compiler's!) include path. For example, if the chip in use includes a core + * local interrupter (CLINT) and does not include any chip specific register + * extensions then add the path below to the assembler's include path: + * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions + * + */ diff --git a/portable/IAR/RISC-V/port.c b/portable/IAR/RISC-V/port.c new file mode 100644 index 000000000..820423ec5 --- /dev/null +++ b/portable/IAR/RISC-V/port.c @@ -0,0 +1,241 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the RISC-V port. + *----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "portmacro.h" + +/* Standard includes. */ +#include "string.h" + +#ifdef configCLINT_BASE_ADDRESS + #warning "The configCLINT_BASE_ADDRESS constant has been deprecated. configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS are currently being derived from the (possibly 0) configCLINT_BASE_ADDRESS setting. Please update to define configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS directly in place of configCLINT_BASE_ADDRESS. See www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html" +#endif + +#ifndef configMTIME_BASE_ADDRESS + #warning "configMTIME_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtime register then set configMTIME_BASE_ADDRESS to the mapped address. Otherwise set configMTIME_BASE_ADDRESS to 0. See www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html" +#endif + +#ifndef configMTIMECMP_BASE_ADDRESS + #warning "configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtimecmp register then set configMTIMECMP_BASE_ADDRESS to the mapped address. Otherwise set configMTIMECMP_BASE_ADDRESS to 0. See www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html" +#endif + +/* Let the user override the pre-loading of the initial LR with the address of + * prvTaskExitError() in case it messes up unwinding of the stack in the + * debugger. */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/* The stack used by interrupt service routines. Set configISR_STACK_SIZE_WORDS + * to use a statically allocated array as the interrupt stack. Alternative leave + * configISR_STACK_SIZE_WORDS undefined and update the linker script so that a + * linker variable names __freertos_irq_stack_top has the same value as the top + * of the stack used by main. Using the linker script method will repurpose the + * stack that was used by main before the scheduler was started for use as the + * interrupt stack after the scheduler has started. */ +#ifdef configISR_STACK_SIZE_WORDS +static __attribute__( ( aligned( 16 ) ) ) StackType_t xISRStack[ configISR_STACK_SIZE_WORDS ] = { 0 }; +const StackType_t xISRStackTop = ( StackType_t ) &( xISRStack[ configISR_STACK_SIZE_WORDS & ~portBYTE_ALIGNMENT_MASK ] ); + +/* Don't use 0xa5 as the stack fill bytes as that is used by the kernel for + * the task stacks, and so will legitimately appear in many positions within + * the ISR stack. */ + #define portISR_STACK_FILL_BYTE 0xee +#else + extern const uint32_t __freertos_irq_stack_top[]; + const StackType_t xISRStackTop = ( StackType_t ) __freertos_irq_stack_top; +#endif + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ) __attribute__( ( weak ) ); + +/*-----------------------------------------------------------*/ + +/* Used to program the machine timer compare register. */ +uint64_t ullNextTime = 0ULL; +const uint64_t * pullNextTime = &ullNextTime; +const size_t uxTimerIncrementsForOneTick = ( size_t ) ( ( configCPU_CLOCK_HZ ) / ( configTICK_RATE_HZ ) ); /* Assumes increment won't go over 32-bits. */ +UBaseType_t const ullMachineTimerCompareRegisterBase = configMTIMECMP_BASE_ADDRESS; +volatile uint64_t * pullMachineTimerCompareRegister = NULL; + +/* Holds the critical nesting value - deliberately non-zero at start up to + * ensure interrupts are not accidentally enabled before the scheduler starts. */ +size_t xCriticalNesting = ( size_t ) 0xaaaaaaaa; +size_t * pxCriticalNesting = &xCriticalNesting; + +/* Used to catch tasks that attempt to return from their implementing function. */ +size_t xTaskReturnAddress = ( size_t ) portTASK_RETURN_ADDRESS; + +/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task + * stack checking. A problem in the ISR stack will trigger an assert, not call + * the stack overflow hook function (because the stack overflow hook is specific + * to a task stack, not the ISR stack). */ +#if defined( configISR_STACK_SIZE_WORDS ) && ( configCHECK_FOR_STACK_OVERFLOW > 2 ) + #warning "This path not tested, or even compiled yet." + + static const uint8_t ucExpectedStackBytes[] = + { + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE + }; \ + + #define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) ) +#else /* if defined( configISR_STACK_SIZE_WORDS ) && ( configCHECK_FOR_STACK_OVERFLOW > 2 ) */ + /* Define the function away. */ + #define portCHECK_ISR_STACK() +#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */ + +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( xCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) + + void vPortSetupTimerInterrupt( void ) + { + uint32_t ulCurrentTimeHigh, ulCurrentTimeLow; + volatile uint32_t * const pulTimeHigh = ( uint32_t * ) ( ( configMTIME_BASE_ADDRESS ) + 4UL ); /* 8-byte type so high 32-bit word is 4 bytes up. */ + volatile uint32_t * const pulTimeLow = ( uint32_t * ) ( configMTIME_BASE_ADDRESS ); + volatile uint32_t ulHartId; + + __asm volatile ( "csrr %0, 0xf14" : "=r" ( ulHartId ) ); /* 0xf14 is HART ID. */ + + pullMachineTimerCompareRegister = ( volatile uint64_t * ) ( ullMachineTimerCompareRegisterBase + ( ulHartId * sizeof( uint64_t ) ) ); + + do + { + ulCurrentTimeHigh = *pulTimeHigh; + ulCurrentTimeLow = *pulTimeLow; + } while( ulCurrentTimeHigh != *pulTimeHigh ); + + ullNextTime = ( uint64_t ) ulCurrentTimeHigh; + ullNextTime <<= 32ULL; /* High 4-byte word is 32-bits up. */ + ullNextTime |= ( uint64_t ) ulCurrentTimeLow; + ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick; + *pullMachineTimerCompareRegister = ullNextTime; + + /* Prepare the time to use after the next tick interrupt. */ + ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick; + } + +#endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIME_BASE_ADDRESS != 0 ) */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + extern void xPortStartFirstTask( void ); + + #if ( configASSERT_DEFINED == 1 ) + { + /* Check alignment of the interrupt stack - which is the same as the + * stack that was being used by main() prior to the scheduler being + * started. */ + configASSERT( ( xISRStackTop & portBYTE_ALIGNMENT_MASK ) == 0 ); + + #ifdef configISR_STACK_SIZE_WORDS + { + memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) ); + } + #endif /* configISR_STACK_SIZE_WORDS */ + } + #endif /* configASSERT_DEFINED */ + + /* If there is a CLINT then it is ok to use the default implementation + * in this file, otherwise vPortSetupTimerInterrupt() must be implemented to + * configure whichever clock is to be used to generate the tick interrupt. */ + vPortSetupTimerInterrupt(); + + #if ( ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) ) + { + /* Enable mtime and external interrupts. 1<<7 for timer interrupt, + * 1<<11 for external interrupt. _RB_ What happens here when mtime is + * not present as with pulpino? */ + __asm volatile ( "csrs 0x304, %0" ::"r" ( 0x880 ) ); /* 0x304 is mie. */ + } + #endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) */ + + xPortStartFirstTask(); + + /* Should not get here as after calling xPortStartFirstTask() only tasks + * should be executing. */ + return pdFAIL; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented. */ + for( ; ; ) + { + } +} +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/RISC-V/portASM.s b/portable/IAR/RISC-V/portASM.s new file mode 100644 index 000000000..12a2a6154 --- /dev/null +++ b/portable/IAR/RISC-V/portASM.s @@ -0,0 +1,399 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * The FreeRTOS kernel's RISC-V port is split between the the code that is + * common across all currently supported RISC-V chips (implementations of the + * RISC-V ISA), and code which tailors the port to a specific RISC-V chip: + * + * + The code that is common to all RISC-V chips is implemented in + * FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S. There is only one + * portASM.S file because the same file is used no matter which RISC-V chip is + * in use. + * + * + The code that tailors the kernel's RISC-V port to a specific RISC-V + * chip is implemented in freertos_risc_v_chip_specific_extensions.h. There + * is one freertos_risc_v_chip_specific_extensions.h that can be used with any + * RISC-V chip that both includes a standard CLINT and does not add to the + * base set of RISC-V registers. There are additional + * freertos_risc_v_chip_specific_extensions.h files for RISC-V implementations + * that do not include a standard CLINT or do add to the base set of RISC-V + * registers. + * + * CARE MUST BE TAKEN TO INCLDUE THE CORRECT + * freertos_risc_v_chip_specific_extensions.h HEADER FILE FOR THE CHIP + * IN USE. To include the correct freertos_risc_v_chip_specific_extensions.h + * header file ensure the path to the correct header file is in the assembler's + * include path. + * + * This freertos_risc_v_chip_specific_extensions.h is for use on RISC-V chips + * that include a standard CLINT and do not add to the base set of RISC-V + * registers. + * + */ + +#include "portContext.h" + +/* Check the freertos_risc_v_chip_specific_extensions.h and/or command line +definitions. */ +#if defined( portasmHAS_CLINT ) && defined( portasmHAS_MTIME ) + #error The portasmHAS_CLINT constant has been deprecated. Please replace it with portasmHAS_MTIME. portasmHAS_CLINT and portasmHAS_MTIME cannot both be defined at once. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html +#endif + +#ifdef portasmHAS_CLINT + #warning The portasmHAS_CLINT constant has been deprecated. Please replace it with portasmHAS_MTIME and portasmHAS_SIFIVE_CLINT. For now portasmHAS_MTIME and portasmHAS_SIFIVE_CLINT are derived from portasmHAS_CLINT. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html + #define portasmHAS_MTIME portasmHAS_CLINT + #define portasmHAS_SIFIVE_CLINT portasmHAS_CLINT +#endif + +#ifndef portasmHAS_MTIME + #error freertos_risc_v_chip_specific_extensions.h must define portasmHAS_MTIME to either 1 (MTIME clock present) or 0 (MTIME clock not present). See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html +#endif + +#ifndef portasmHAS_SIFIVE_CLINT + #define portasmHAS_SIFIVE_CLINT 0 +#endif + +/* CSR definitions. */ +#define CSR_MSTATUS 0x300 +#define CSR_MTVEC 0x305 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 + + PUBLIC xPortStartFirstTask + PUBLIC pxPortInitialiseStack + PUBLIC freertos_risc_v_trap_handler + PUBLIC freertos_risc_v_exception_handler + PUBLIC freertos_risc_v_interrupt_handler + PUBLIC freertos_risc_v_mtimer_interrupt_handler + + EXTERN vTaskSwitchContext + EXTERN xTaskIncrementTick + EXTERN pullMachineTimerCompareRegister + EXTERN pullNextTime + EXTERN uxTimerIncrementsForOneTick /* size_t type so 32-bit on 32-bit core and 64-bits on 64-bit core. */ + EXTERN xTaskReturnAddress + + PUBWEAK freertos_risc_v_application_exception_handler + PUBWEAK freertos_risc_v_application_interrupt_handler +/*-----------------------------------------------------------*/ + + SECTION `.text`:CODE:NOROOT(2) + CODE + +portUPDATE_MTIMER_COMPARE_REGISTER MACRO + load_x a0, pullMachineTimerCompareRegister /* Load address of compare register into a0. */ + load_x a1, pullNextTime /* Load the address of ullNextTime into a1. */ + + #if( __riscv_xlen == 32 ) + + /* Update the 64-bit mtimer compare match value in two 32-bit writes. */ + li a4, -1 + lw a2, 0(a1) /* Load the low word of ullNextTime into a2. */ + lw a3, 4(a1) /* Load the high word of ullNextTime into a3. */ + sw a4, 0(a0) /* Low word no smaller than old value to start with - will be overwritten below. */ + sw a3, 4(a0) /* Store high word of ullNextTime into compare register. No smaller than new value. */ + sw a2, 0(a0) /* Store low word of ullNextTime into compare register. */ + lw t0, uxTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */ + add a4, t0, a2 /* Add the low word of ullNextTime to the timer increments for one tick (assumes timer increment for one tick fits in 32-bits). */ + sltu t1, a4, a2 /* See if the sum of low words overflowed (what about the zero case?). */ + add t2, a3, t1 /* Add overflow to high word of ullNextTime. */ + sw a4, 0(a1) /* Store new low word of ullNextTime. */ + sw t2, 4(a1) /* Store new high word of ullNextTime. */ + + #endif /* __riscv_xlen == 32 */ + + #if( __riscv_xlen == 64 ) + + /* Update the 64-bit mtimer compare match value. */ + ld t2, 0(a1) /* Load ullNextTime into t2. */ + sd t2, 0(a0) /* Store ullNextTime into compare register. */ + ld t0, uxTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */ + add t4, t0, t2 /* Add ullNextTime to the timer increments for one tick. */ + sd t4, 0(a1) /* Store ullNextTime. */ + + #endif /* __riscv_xlen == 64 */ + ENDM +/*-----------------------------------------------------------*/ + +/* + * Unlike other ports pxPortInitialiseStack() is written in assembly code as it + * needs access to the portasmADDITIONAL_CONTEXT_SIZE constant. The prototype + * for the function is as per the other ports: + * StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ); + * + * As per the standard RISC-V ABI pxTopOfStack is passed in in a0, pxCode in + * a1, and pvParameters in a2. The new top of stack is passed out in a0. + * + * RISC-V maps registers to ABI names as follows (X1 to X31 integer registers + * for the 'I' profile, X1 to X15 for the 'E' profile, currently I assumed). + * + * Register ABI Name Description Saver + * x0 zero Hard-wired zero - + * x1 ra Return address Caller + * x2 sp Stack pointer Callee + * x3 gp Global pointer - + * x4 tp Thread pointer - + * x5-7 t0-2 Temporaries Caller + * x8 s0/fp Saved register/Frame pointer Callee + * x9 s1 Saved register Callee + * x10-11 a0-1 Function Arguments/return values Caller + * x12-17 a2-7 Function arguments Caller + * x18-27 s2-11 Saved registers Callee + * x28-31 t3-6 Temporaries Caller + * + * The RISC-V context is saved to FreeRTOS tasks in the following stack frame, + * where the global and thread pointers are currently assumed to be constant so + * are not saved: + * + * mstatus + * xCriticalNesting + * x31 + * x30 + * x29 + * x28 + * x27 + * x26 + * x25 + * x24 + * x23 + * x22 + * x21 + * x20 + * x19 + * x18 + * x17 + * x16 + * x15 + * x14 + * x13 + * x12 + * x11 + * pvParameters + * x9 + * x8 + * x7 + * x6 + * x5 + * portTASK_RETURN_ADDRESS + * [chip specific registers go here] + * pxCode + */ +pxPortInitialiseStack: + csrr t0, CSR_MSTATUS /* Obtain current mstatus value. */ + andi t0, t0, ~0x8 /* Ensure interrupts are disabled when the stack is restored within an ISR. Required when a task is created after the schedulre has been started, otherwise interrupts would be disabled anyway. */ + addi t1, x0, 0x188 /* Generate the value 0x1880, which are the MPIE and MPP bits to set in mstatus. */ + slli t1, t1, 4 + or t0, t0, t1 /* Set MPIE and MPP bits in mstatus value. */ + + addi a0, a0, -portWORD_SIZE + store_x t0, 0(a0) /* mstatus onto the stack. */ + addi a0, a0, -portWORD_SIZE /* Space for critical nesting count. */ + store_x x0, 0(a0) /* Critical nesting count starts at 0 for every task. */ +#ifdef __riscv_32e + addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x10-15. */ +#else + addi a0, a0, -(22 * portWORD_SIZE) /* Space for registers x10-x31. */ +#endif + store_x a2, 0(a0) /* Task parameters (pvParameters parameter) goes into register X10/a0 on the stack. */ + addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x5-x9 + taskReturnAddress. */ + load_x t0, xTaskReturnAddress + store_x t0, 0(a0) /* Return address onto the stack. */ + addi t0, x0, portasmADDITIONAL_CONTEXT_SIZE /* The number of chip specific additional registers. */ +chip_specific_stack_frame: /* First add any chip specific registers to the stack frame being created. */ + beq t0, x0, no_more_regs /* No more chip specific registers to save. */ + addi a0, a0, -portWORD_SIZE /* Make space for chip specific register. */ + store_x x0, 0(a0) /* Give the chip specific register an initial value of zero. */ + addi t0, t0, -1 /* Decrement the count of chip specific registers remaining. */ + j chip_specific_stack_frame /* Until no more chip specific registers. */ +no_more_regs: + addi a0, a0, -portWORD_SIZE + store_x a1, 0(a0) /* mret value (pxCode parameter) onto the stack. */ + ret +/*-----------------------------------------------------------*/ + +xPortStartFirstTask: + load_x sp, pxCurrentTCB /* Load pxCurrentTCB. */ + load_x sp, 0( sp ) /* Read sp from first TCB member. */ + + load_x x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */ + + portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */ + + load_x x7, 4 * portWORD_SIZE( sp ) /* t2 */ + load_x x8, 5 * portWORD_SIZE( sp ) /* s0/fp */ + load_x x9, 6 * portWORD_SIZE( sp ) /* s1 */ + load_x x10, 7 * portWORD_SIZE( sp ) /* a0 */ + load_x x11, 8 * portWORD_SIZE( sp ) /* a1 */ + load_x x12, 9 * portWORD_SIZE( sp ) /* a2 */ + load_x x13, 10 * portWORD_SIZE( sp ) /* a3 */ + load_x x14, 11 * portWORD_SIZE( sp ) /* a4 */ + load_x x15, 12 * portWORD_SIZE( sp ) /* a5 */ +#ifndef __riscv_32e + load_x x16, 13 * portWORD_SIZE( sp ) /* a6 */ + load_x x17, 14 * portWORD_SIZE( sp ) /* a7 */ + load_x x18, 15 * portWORD_SIZE( sp ) /* s2 */ + load_x x19, 16 * portWORD_SIZE( sp ) /* s3 */ + load_x x20, 17 * portWORD_SIZE( sp ) /* s4 */ + load_x x21, 18 * portWORD_SIZE( sp ) /* s5 */ + load_x x22, 19 * portWORD_SIZE( sp ) /* s6 */ + load_x x23, 20 * portWORD_SIZE( sp ) /* s7 */ + load_x x24, 21 * portWORD_SIZE( sp ) /* s8 */ + load_x x25, 22 * portWORD_SIZE( sp ) /* s9 */ + load_x x26, 23 * portWORD_SIZE( sp ) /* s10 */ + load_x x27, 24 * portWORD_SIZE( sp ) /* s11 */ + load_x x28, 25 * portWORD_SIZE( sp ) /* t3 */ + load_x x29, 26 * portWORD_SIZE( sp ) /* t4 */ + load_x x30, 27 * portWORD_SIZE( sp ) /* t5 */ + load_x x31, 28 * portWORD_SIZE( sp ) /* t6 */ +#endif + + load_x x5, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Obtain xCriticalNesting value for this task from task's stack. */ + load_x x6, pxCriticalNesting /* Load the address of xCriticalNesting into x6. */ + store_x x5, 0( x6 ) /* Restore the critical nesting value for this task. */ + + load_x x5, portMSTATUS_OFFSET * portWORD_SIZE( sp ) /* Initial mstatus into x5 (t0). */ + addi x5, x5, 0x08 /* Set MIE bit so the first task starts with interrupts enabled - required as returns with ret not eret. */ + csrrw x0, CSR_MSTATUS, x5 /* Interrupts enabled from here! */ + + load_x x5, 2 * portWORD_SIZE( sp ) /* Initial x5 (t0) value. */ + load_x x6, 3 * portWORD_SIZE( sp ) /* Initial x6 (t1) value. */ + + addi sp, sp, portCONTEXT_SIZE + ret +/*-----------------------------------------------------------*/ + +freertos_risc_v_application_exception_handler: + csrr t0, CSR_MCAUSE /* For viewing in the debugger only. */ + csrr t1, CSR_MEPC /* For viewing in the debugger only */ + csrr t2, CSR_MSTATUS /* For viewing in the debugger only */ + j $ +/*-----------------------------------------------------------*/ + +freertos_risc_v_application_interrupt_handler: + csrr t0, CSR_MCAUSE /* For viewing in the debugger only. */ + csrr t1, CSR_MEPC /* For viewing in the debugger only */ + csrr t2, CSR_MSTATUS /* For viewing in the debugger only */ + j $ +/*-----------------------------------------------------------*/ + + SECTION `.text.freertos_risc_v_exception_handler`:CODE:NOROOT(2) + CODE + +freertos_risc_v_exception_handler: + portcontextSAVE_EXCEPTION_CONTEXT + /* a0 now contains mcause. */ + li t0, 11 /* 11 == environment call. */ + bne a0, t0, other_exception /* Not an M environment call, so some other exception. */ + call vTaskSwitchContext + portcontextRESTORE_CONTEXT + +other_exception: + call freertos_risc_v_application_exception_handler + portcontextRESTORE_CONTEXT +/*-----------------------------------------------------------*/ + + SECTION `.text.freertos_risc_v_interrupt_handler`:CODE:NOROOT(2) + CODE + +freertos_risc_v_interrupt_handler: + portcontextSAVE_INTERRUPT_CONTEXT + call freertos_risc_v_application_interrupt_handler + portcontextRESTORE_CONTEXT +/*-----------------------------------------------------------*/ + + SECTION `.text.freertos_risc_v_mtimer_interrupt_handler`:CODE:NOROOT(2) + CODE + +freertos_risc_v_mtimer_interrupt_handler: + portcontextSAVE_INTERRUPT_CONTEXT + portUPDATE_MTIMER_COMPARE_REGISTER + call xTaskIncrementTick + beqz a0, exit_without_context_switch /* Don't switch context if incrementing tick didn't unblock a task. */ + call vTaskSwitchContext +exit_without_context_switch: + portcontextRESTORE_CONTEXT +/*-----------------------------------------------------------*/ + + SECTION `.text.freertos_risc_v_trap_handler`:CODE:NOROOT(8) + CODE + +freertos_risc_v_trap_handler: + portcontextSAVE_CONTEXT_INTERNAL + + csrr a0, CSR_MCAUSE + csrr a1, CSR_MEPC + + bge a0, x0, synchronous_exception + +asynchronous_interrupt: + store_x a1, 0( sp ) /* Asynchronous interrupt so save unmodified exception return address. */ + load_x sp, xISRStackTop /* Switch to ISR stack. */ + j handle_interrupt + +synchronous_exception: + addi a1, a1, 4 /* Synchronous so update exception return address to the instruction after the instruction that generated the exeption. */ + store_x a1, 0( sp ) /* Save updated exception return address. */ + load_x sp, xISRStackTop /* Switch to ISR stack. */ + j handle_exception + +handle_interrupt: +#if( portasmHAS_MTIME != 0 ) + + test_if_mtimer: /* If there is a CLINT then the mtimer is used to generate the tick interrupt. */ + addi t0, x0, 1 + slli t0, t0, __riscv_xlen - 1 /* LSB is already set, shift into MSB. Shift 31 on 32-bit or 63 on 64-bit cores. */ + addi t1, t0, 7 /* 0x8000[]0007 == machine timer interrupt. */ + bne a0, t1, application_interrupt_handler + + portUPDATE_MTIMER_COMPARE_REGISTER + call xTaskIncrementTick + beqz a0, processed_source /* Don't switch context if incrementing tick didn't unblock a task. */ + call vTaskSwitchContext + j processed_source + +#endif /* portasmHAS_MTIME */ + +application_interrupt_handler: + call freertos_risc_v_application_interrupt_handler + j processed_source + +handle_exception: + /* a0 contains mcause. */ + li t0, 11 /* 11 == environment call. */ + bne a0, t0, application_exception_handler /* Not an M environment call, so some other exception. */ + call vTaskSwitchContext + j processed_source + +application_exception_handler: + call freertos_risc_v_application_exception_handler + j processed_source /* No other exceptions handled yet. */ + +processed_source: + portcontextRESTORE_CONTEXT +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/RISC-V/portContext.h b/portable/IAR/RISC-V/portContext.h new file mode 100644 index 000000000..7b3244e7b --- /dev/null +++ b/portable/IAR/RISC-V/portContext.h @@ -0,0 +1,189 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTCONTEXT_H +#define PORTCONTEXT_H + +#if __riscv_xlen == 64 + #define portWORD_SIZE 8 + #define store_x sd + #define load_x ld +#elif __riscv_xlen == 32 + #define store_x sw + #define load_x lw + #define portWORD_SIZE 4 +#else + #error Assembler did not define __riscv_xlen +#endif + +#include "freertos_risc_v_chip_specific_extensions.h" + +/* Only the standard core registers are stored by default. Any additional + * registers must be saved by the portasmSAVE_ADDITIONAL_REGISTERS and + * portasmRESTORE_ADDITIONAL_REGISTERS macros - which can be defined in a chip + * specific version of freertos_risc_v_chip_specific_extensions.h. See the + * notes at the top of portASM.S file. */ +#ifdef __riscv_32e + #define portCONTEXT_SIZE ( 15 * portWORD_SIZE ) + #define portCRITICAL_NESTING_OFFSET 13 + #define portMSTATUS_OFFSET 14 +#else + #define portCONTEXT_SIZE ( 31 * portWORD_SIZE ) + #define portCRITICAL_NESTING_OFFSET 29 + #define portMSTATUS_OFFSET 30 +#endif + +EXTERN pxCurrentTCB +EXTERN xISRStackTop +EXTERN xCriticalNesting +EXTERN pxCriticalNesting + +/*-----------------------------------------------------------*/ + +portcontextSAVE_CONTEXT_INTERNAL MACRO +addi sp, sp, -portCONTEXT_SIZE +store_x x1, 1 * portWORD_SIZE( sp ) +store_x x5, 2 * portWORD_SIZE( sp ) +store_x x6, 3 * portWORD_SIZE( sp ) +store_x x7, 4 * portWORD_SIZE( sp ) +store_x x8, 5 * portWORD_SIZE( sp ) +store_x x9, 6 * portWORD_SIZE( sp ) +store_x x10, 7 * portWORD_SIZE( sp ) +store_x x11, 8 * portWORD_SIZE( sp ) +store_x x12, 9 * portWORD_SIZE( sp ) +store_x x13, 10 * portWORD_SIZE( sp ) +store_x x14, 11 * portWORD_SIZE( sp ) +store_x x15, 12 * portWORD_SIZE( sp ) +#ifndef __riscv_32e + store_x x16, 13 * portWORD_SIZE( sp ) + store_x x17, 14 * portWORD_SIZE( sp ) + store_x x18, 15 * portWORD_SIZE( sp ) + store_x x19, 16 * portWORD_SIZE( sp ) + store_x x20, 17 * portWORD_SIZE( sp ) + store_x x21, 18 * portWORD_SIZE( sp ) + store_x x22, 19 * portWORD_SIZE( sp ) + store_x x23, 20 * portWORD_SIZE( sp ) + store_x x24, 21 * portWORD_SIZE( sp ) + store_x x25, 22 * portWORD_SIZE( sp ) + store_x x26, 23 * portWORD_SIZE( sp ) + store_x x27, 24 * portWORD_SIZE( sp ) + store_x x28, 25 * portWORD_SIZE( sp ) + store_x x29, 26 * portWORD_SIZE( sp ) + store_x x30, 27 * portWORD_SIZE( sp ) + store_x x31, 28 * portWORD_SIZE( sp ) +#endif /* ifndef __riscv_32e */ + +load_x t0, xCriticalNesting /* Load the value of xCriticalNesting into t0. */ +store_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Store the critical nesting value to the stack. */ + +csrr t0, mstatus /* Required for MPIE bit. */ +store_x t0, portMSTATUS_OFFSET * portWORD_SIZE( sp ) + +portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */ + +load_x t0, pxCurrentTCB /* Load pxCurrentTCB. */ +store_x sp, 0 ( t0 ) /* Write sp to first TCB member. */ + +ENDM +/*-----------------------------------------------------------*/ + +portcontextSAVE_EXCEPTION_CONTEXT MACRO +portcontextSAVE_CONTEXT_INTERNAL +csrr a0, mcause +csrr a1, mepc +addi a1, a1, 4 /* Synchronous so update exception return address to the instruction after the instruction that generated the exception. */ +store_x a1, 0 ( sp ) /* Save updated exception return address. */ +load_x sp, xISRStackTop /* Switch to ISR stack. */ +ENDM +/*-----------------------------------------------------------*/ + +portcontextSAVE_INTERRUPT_CONTEXT MACRO +portcontextSAVE_CONTEXT_INTERNAL +csrr a0, mcause +csrr a1, mepc +store_x a1, 0 ( sp ) /* Asynchronous interrupt so save unmodified exception return address. */ +load_x sp, xISRStackTop /* Switch to ISR stack. */ +ENDM +/*-----------------------------------------------------------*/ + +portcontextRESTORE_CONTEXT MACRO +load_x t1, pxCurrentTCB /* Load pxCurrentTCB. */ +load_x sp, 0 ( t1 ) /* Read sp from first TCB member. */ + +/* Load mepc with the address of the instruction in the task to run next. */ +load_x t0, 0 ( sp ) +csrw mepc, t0 + +/* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */ +portasmRESTORE_ADDITIONAL_REGISTERS + +/* Load mstatus with the interrupt enable bits used by the task. */ +load_x t0, portMSTATUS_OFFSET * portWORD_SIZE( sp ) +csrw mstatus, t0 /* Required for MPIE bit. */ + +load_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Obtain xCriticalNesting value for this task from task's stack. */ +load_x t1, pxCriticalNesting /* Load the address of xCriticalNesting into t1. */ +store_x t0, 0 ( t1 ) /* Restore the critical nesting value for this task. */ + +load_x x1, 1 * portWORD_SIZE( sp ) +load_x x5, 2 * portWORD_SIZE( sp ) +load_x x6, 3 * portWORD_SIZE( sp ) +load_x x7, 4 * portWORD_SIZE( sp ) +load_x x8, 5 * portWORD_SIZE( sp ) +load_x x9, 6 * portWORD_SIZE( sp ) +load_x x10, 7 * portWORD_SIZE( sp ) +load_x x11, 8 * portWORD_SIZE( sp ) +load_x x12, 9 * portWORD_SIZE( sp ) +load_x x13, 10 * portWORD_SIZE( sp ) +load_x x14, 11 * portWORD_SIZE( sp ) +load_x x15, 12 * portWORD_SIZE( sp ) +#ifndef __riscv_32e + load_x x16, 13 * portWORD_SIZE( sp ) + load_x x17, 14 * portWORD_SIZE( sp ) + load_x x18, 15 * portWORD_SIZE( sp ) + load_x x19, 16 * portWORD_SIZE( sp ) + load_x x20, 17 * portWORD_SIZE( sp ) + load_x x21, 18 * portWORD_SIZE( sp ) + load_x x22, 19 * portWORD_SIZE( sp ) + load_x x23, 20 * portWORD_SIZE( sp ) + load_x x24, 21 * portWORD_SIZE( sp ) + load_x x25, 22 * portWORD_SIZE( sp ) + load_x x26, 23 * portWORD_SIZE( sp ) + load_x x27, 24 * portWORD_SIZE( sp ) + load_x x28, 25 * portWORD_SIZE( sp ) + load_x x29, 26 * portWORD_SIZE( sp ) + load_x x30, 27 * portWORD_SIZE( sp ) + load_x x31, 28 * portWORD_SIZE( sp ) +#endif /* ifndef __riscv_32e */ +addi sp, sp, portCONTEXT_SIZE + +mret +ENDM +/*-----------------------------------------------------------*/ + +#endif /* PORTCONTEXT_H */ diff --git a/portable/IAR/RISC-V/portmacro.h b/portable/IAR/RISC-V/portmacro.h new file mode 100644 index 000000000..c7237b363 --- /dev/null +++ b/portable/IAR/RISC-V/portmacro.h @@ -0,0 +1,198 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#include "intrinsics.h" + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#if __riscv_xlen == 64 + #define portSTACK_TYPE uint64_t + #define portBASE_TYPE int64_t + #define portUBASE_TYPE uint64_t + #define portMAX_DELAY ( TickType_t ) 0xffffffffffffffffUL + #define portPOINTER_SIZE_TYPE uint64_t +#elif __riscv_xlen == 32 + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE int32_t + #define portUBASE_TYPE uint32_t + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#else /* if __riscv_xlen == 64 */ + #error "Assembler did not define __riscv_xlen" +#endif /* if __riscv_xlen == 64 */ + +typedef portSTACK_TYPE StackType_t; +typedef portBASE_TYPE BaseType_t; +typedef portUBASE_TYPE UBaseType_t; +typedef portUBASE_TYPE TickType_t; + +/* Legacy type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ +#define portTICK_TYPE_IS_ATOMIC 1 +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#ifdef __riscv_32e + #define portBYTE_ALIGNMENT 8 /* RV32E uses RISC-V EABI with reduced stack alignment requirements. */ +#else + #define portBYTE_ALIGNMENT 16 +#endif +/*-----------------------------------------------------------*/ + +/* Scheduler utilities. */ +extern void vTaskSwitchContext( void ); +#define portYIELD() __asm volatile ( "ecall" ); +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + vTaskSwitchContext(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +#define portCRITICAL_NESTING_IN_TCB 0 + +#define portDISABLE_INTERRUPTS() __disable_interrupt() +#define portENABLE_INTERRUPTS() __enable_interrupt() + +extern size_t xCriticalNesting; +#define portENTER_CRITICAL() \ + { \ + portDISABLE_INTERRUPTS(); \ + xCriticalNesting++; \ + } + +#define portEXIT_CRITICAL() \ + { \ + xCriticalNesting--; \ + if( xCriticalNesting == 0 ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } + +/*-----------------------------------------------------------*/ + +/* Architecture specific optimisations. */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + + #error "configUSE_PORT_OPTIMISED_TASK_SELECTION cannot yet be used in the IAR RISC-V port, the CLZ instruction needs to be emulated." + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not necessary for to use this port. They are defined so the common demo + * files (which build with all the ports) will build. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/*-----------------------------------------------------------*/ + +#define portNOP() __asm volatile ( " nop " ) +#define portINLINE __inline + +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif + +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in + * the source code because to do so would cause other compilers to generate + * warnings. */ +#pragma diag_suppress=Pa082 + +/* configCLINT_BASE_ADDRESS is a legacy definition that was replaced by the + * configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS definitions. For + * backward compatibility derive the newer definitions from the old if the old + * definition is found. */ +#if defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS ) && ( configCLINT_BASE_ADDRESS == 0 ) + +/* Legacy case where configCLINT_BASE_ADDRESS was defined as 0 to indicate + * there was no CLINT. Equivalent now is to set the MTIME and MTIMECMP + * addresses to 0. */ + #define configMTIME_BASE_ADDRESS ( 0 ) + #define configMTIMECMP_BASE_ADDRESS ( 0 ) +#elif defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS ) + +/* Legacy case where configCLINT_BASE_ADDRESS was set to the base address of + * the CLINT. Equivalent now is to derive the MTIME and MTIMECMP addresses + * from the CLINT address. */ + #define configMTIME_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0xBFF8UL ) + #define configMTIMECMP_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0x4000UL ) +#elif !defined( configMTIME_BASE_ADDRESS ) || !defined( configMTIMECMP_BASE_ADDRESS ) + #error "configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. Set them to zero if there is no MTIME (machine time) clock. See www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html" +#endif /* if defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS ) && ( configCLINT_BASE_ADDRESS == 0 ) */ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/IAR/RISC-V/readme.txt b/portable/IAR/RISC-V/readme.txt new file mode 100644 index 000000000..b24c0b9fb --- /dev/null +++ b/portable/IAR/RISC-V/readme.txt @@ -0,0 +1,23 @@ +/* + * The FreeRTOS kernel's RISC-V port is split between the the code that is + * common across all currently supported RISC-V chips (implementations of the + * RISC-V ISA), and code that tailors the port to a specific RISC-V chip: + * + * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that + * is common to all currently supported RISC-V chips. There is only one + * portASM.S file because the same file is built for all RISC-V target chips. + * + * + Header files called freertos_risc_v_chip_specific_extensions.h contain the + * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V + * chip. There are multiple freertos_risc_v_chip_specific_extensions.h files + * as there are multiple RISC-V chip implementations. + * + * !!!NOTE!!! + * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h + * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the + * compiler's!) include path. For example, if the chip in use includes a core + * local interrupter (CLINT) and does not include any chip specific register + * extensions then add the path below to the assembler's include path: + * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions + * + */ diff --git a/portable/IAR/RL78/port.c b/portable/IAR/RL78/port.c new file mode 100644 index 000000000..656efeb2d --- /dev/null +++ b/portable/IAR/RL78/port.c @@ -0,0 +1,241 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* The critical nesting value is initialised to a non zero value to ensure + * interrupts don't accidentally become enabled before the scheduler is started. */ +#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 ) + +/* Initial PSW value allocated to a newly created task. + * 1100011000000000 + * ||||||||-------------- Fill byte + * |||||||--------------- Carry Flag cleared + * |||||----------------- In-service priority Flags set to low level + * ||||------------------ Register bank Select 0 Flag cleared + * |||------------------- Auxiliary Carry Flag cleared + * ||-------------------- Register bank Select 1 Flag cleared + * |--------------------- Zero Flag set + * ---------------------- Global Interrupt Flag set (enabled) + */ +#define portPSW ( 0xc6UL ) + +/* The address of the pxCurrentTCB variable, but don't know or need to know its + * type. */ +typedef void TCB_t; +extern volatile TCB_t * volatile pxCurrentTCB; + +/* Each task maintains a count of the critical section nesting depth. Each time + * a critical section is entered the count is incremented. Each time a critical + * section is exited the count is decremented - with interrupts only being + * re-enabled if the count is zero. + * + * usCriticalNesting will get set to zero when the scheduler starts, but must + * not be initialised to zero as that could cause problems during the startup + * sequence. */ +volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING; + +/*-----------------------------------------------------------*/ + +/* + * Sets up the periodic ISR used for the RTOS tick. + */ +extern void vApplicationSetupTimerInterrupt( void ); + +/* + * Starts the scheduler by loading the context of the first Task to run. + * (implemented in portasm.s). + */ +extern void vPortStartFirstTask( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See the header file portable.h. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + uint32_t * pulLocal; + /* With large data sizeof( StackType_t ) == 2, and + * sizeof( StackType_t * ) == 4. With small data + * sizeof( StackType_t ) == 2 and sizeof( StackType_t * ) == 2. */ +#if __DATA_MODEL__ == __DATA_MODEL_FAR__ + { + /* Far pointer parameters are passed using the A:DE registers (24-bit). + * Although they are stored in memory as a 32-bit value. Hence decrement + * the stack pointer, so 2 bytes are left for the contents of A, before + * storing the pvParameters value. */ + pxTopOfStack--; + pulLocal = ( uint32_t * ) pxTopOfStack; + #if __CALLING_CONVENTION__ == __CC_V2__ + /* V2: parameter via A:DE, do not push pvParameters on stack */ + #else + /* V1 or unknown: keep stack write */ + *pulLocal = ( uint32_t ) pvParameters; + pxTopOfStack--; + #endif + /* The return address is a 32-bit value. So decrement the stack pointer + * in order to make extra room needed to store the correct value. See the + * comments above the prvTaskExitError() prototype at the top of this file. */ + pxTopOfStack--; + pulLocal = ( uint32_t * ) pxTopOfStack; + *pulLocal = ( uint32_t ) prvTaskExitError; + pxTopOfStack--; + /* The task function start address combined with the PSW is also stored + * as a 32-bit value. So leave a space for the second two bytes. */ + pxTopOfStack--; + pulLocal = ( uint32_t * ) pxTopOfStack; + *pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) ); + pxTopOfStack--; + /* Register image on task entry. */ + #if __CALLING_CONVENTION__ == __CC_V2__ + { + uint32_t p = ( uint32_t ) pvParameters; + uint16_t de_init = (uint16_t)( p & 0xFFFFU ); + uint16_t ax_init = (uint16_t)( ((p >> 16) & 0xFFU) << 8 ); + /* AX register image */ + *pxTopOfStack = ( StackType_t ) ax_init; + pxTopOfStack--; + /* HL register image (dummy) */ + *pxTopOfStack = ( StackType_t ) 0x2222; + pxTopOfStack--; + /* CS:ES register image */ + *pxTopOfStack = ( StackType_t ) 0x0F00; + pxTopOfStack--; + /* DE register image */ + *pxTopOfStack = ( StackType_t ) de_init; + pxTopOfStack--; + } + #else + /* An initial value for the AX register. */ + *pxTopOfStack = ( StackType_t ) 0x1111; + pxTopOfStack--; + /* HL register image (dummy) */ + *pxTopOfStack = ( StackType_t ) 0x2222; + pxTopOfStack--; + /* CS:ES register image */ + *pxTopOfStack = ( StackType_t ) 0x0F00; + pxTopOfStack--; + /* DE register image (dummy) */ + *pxTopOfStack = ( StackType_t ) 0xDEDE; + pxTopOfStack--; + #endif + /* BC remains a dummy value (not used for parameter passing). */ + *pxTopOfStack = ( StackType_t ) 0xBCBC; + pxTopOfStack--; + } +#else /* if __DATA_MODEL__ == __DATA_MODEL_FAR__ */ + { + /* The return address, leaving space for the first two bytes of the + * 32-bit value. See the comments above the prvTaskExitError() prototype + * at the top of this file. */ + pxTopOfStack--; + pulLocal = ( uint32_t * ) pxTopOfStack; + *pulLocal = ( uint32_t ) prvTaskExitError; + pxTopOfStack--; + /* Task function. Again as it is written as a 32-bit value a space is + * left on the stack for the second two bytes. */ + pxTopOfStack--; + /* Task function start address combined with the PSW. */ + pulLocal = ( uint32_t * ) pxTopOfStack; + *pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) ); + pxTopOfStack--; + /* The parameter is passed in AX. */ + *pxTopOfStack = ( StackType_t ) pvParameters; + pxTopOfStack--; + /* An initial value for the HL register. */ + *pxTopOfStack = ( StackType_t ) 0x2222; + pxTopOfStack--; + /* CS and ES registers. */ + *pxTopOfStack = ( StackType_t ) 0x0F00; + pxTopOfStack--; + /* The remaining general purpose registers DE and BC */ + *pxTopOfStack = ( StackType_t ) 0xDEDE; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xBCBC; + pxTopOfStack--; + } +#endif /* __DATA_MODEL__ */ + /* Finally the critical section nesting count is set to zero when the task + * first starts. */ + *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING; + /* Return a pointer to the top of the stack that has been generated so + * it can be stored in the task control block for the task. */ + return pxTopOfStack; +} + +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ + configASSERT( usCriticalNesting == ~0U ); + portDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Setup the hardware to generate the tick. Interrupts are disabled when + * this function is called. */ + vApplicationSetupTimerInterrupt(); + + /* Restore the context of the first task that is going to run. */ + vPortStartFirstTask(); + + /* Execution should not reach here as the tasks are now running! */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the RL78 port will get stopped. */ +} +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/RL78/portasm.s b/portable/IAR/RL78/portasm.s new file mode 100644 index 000000000..7067cb1e4 --- /dev/null +++ b/portable/IAR/RL78/portasm.s @@ -0,0 +1,84 @@ +;/* +; * FreeRTOS Kernel +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + +#include "portmacro.h" + + EXTERN _vTaskSwitchContext + EXTERN _xTaskIncrementTick + + EXTERN _interrupt_vector_table + + PUBLIC _vPortYield + PUBLIC _vPortStartFirstTask + PUBLIC _vPortTickISR + +#if !defined(__IASMRL78__) || (__VER__ < 310) + #error "This port requires the IAR Assembler for RL78 version 3.10 or later." +#endif + +;------------------------------------------------------------------------------- +; FreeRTOS yield handler. This is installed as the BRK software interrupt +; handler. +;------------------------------------------------------------------------------- + SECTION `.text`:CODE:ROOT(1) +_vPortYield: + portSAVE_CONTEXT ; Save the context of the current task. + RCALL (_vTaskSwitchContext) ; Call the scheduler to select the next task. + portRESTORE_CONTEXT ; Restore the context of the next task to run. + RETB +;------------------------------------------------------------------------------- + + +;------------------------------------------------------------------------------- +; Starts the scheduler by restoring the context of the task that will execute +; first. +;------------------------------------------------------------------------------- + SECTION `.text`:CODE:ROOT(1) +_vPortStartFirstTask: + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + RETI ; An interrupt stack frame is used so the + ; task is started using a RETI instruction. +;------------------------------------------------------------------------------- + + +;------------------------------------------------------------------------------- +; FreeRTOS Timer Tick handler. +; This is installed as the interval timer interrupt handler. +;------------------------------------------------------------------------------- + SECTION `.text`:CODE:ROOT(1) +_vPortTickISR: + portSAVE_CONTEXT ; Save the context of the current task. + RCALL (_xTaskIncrementTick) ; Call the timer tick function. + CMPW AX, #0x00 + SKZ + RCALL (_vTaskSwitchContext) ; Call the scheduler to select the next task. + portRESTORE_CONTEXT ; Restore the context of the next task to run. + RETI +;------------------------------------------------------------------------------- + + END diff --git a/portable/IAR/RL78/portmacro.h b/portable/IAR/RL78/portmacro.h new file mode 100644 index 000000000..36697a620 --- /dev/null +++ b/portable/IAR/RL78/portmacro.h @@ -0,0 +1,245 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __IAR_SYSTEMS_ICC__ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + + #if __DATA_MODEL__ == __DATA_MODEL_FAR__ && __CODE_MODEL__ == __CODE_MODEL_NEAR__ + #warning This port has not been tested with your selected memory model combination. If a far data model is required it is recommended to also use a far code model. + #endif + + #if __DATA_MODEL__ == __DATA_MODEL_NEAR__ && __CODE_MODEL__ == __CODE_MODEL_FAR__ + #warning This port has not been tested with your selected memory model combination. If a far code model is required it is recommended to also use a far data model. + #endif + +/* Type definitions. */ + + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint16_t + #define portBASE_TYPE short + + typedef portSTACK_TYPE StackType_t; + typedef short BaseType_t; + typedef unsigned short UBaseType_t; + + + #if __DATA_MODEL__ == __DATA_MODEL_FAR__ + #define portPOINTER_SIZE_TYPE uint32_t + #else + #define portPOINTER_SIZE_TYPE uint16_t + #endif + + + #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef unsigned int TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) + #else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. + #endif +/*-----------------------------------------------------------*/ + +/* Interrupt control macros. */ + #define portDISABLE_INTERRUPTS() __asm( "DI" ) + #define portENABLE_INTERRUPTS() __asm( "EI" ) +/*-----------------------------------------------------------*/ + +/* Critical section control macros. */ + #define portNO_CRITICAL_SECTION_NESTING ( ( uint16_t ) 0 ) + + #define portENTER_CRITICAL() \ + { \ + extern volatile uint16_t usCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + \ + /* Now that interrupts are disabled, ulCriticalNesting can be accessed */ \ + /* directly. Increment ulCriticalNesting to keep a count of how many */ \ + /* times portENTER_CRITICAL() has been called. */ \ + usCriticalNesting++; \ + } + + #define portEXIT_CRITICAL() \ + { \ + extern volatile uint16_t usCriticalNesting; \ + \ + if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ + { \ + /* Decrement the nesting count when leaving a critical section. */ \ + usCriticalNesting--; \ + \ + /* If the nesting level has reached zero then interrupts should be */ \ + /* re-enabled. */ \ + if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } \ + } +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + #define portNOP() __asm( "NOP" ) + #define portYIELD() __asm( "BRK" ) + #ifndef configREQUIRE_ASM_ISR_WRAPPER + #define configREQUIRE_ASM_ISR_WRAPPER 1 + #endif + #if( configREQUIRE_ASM_ISR_WRAPPER == 1 ) + /* You must implement an assembly ISR wrapper (see the below for details) if you need an ISR to cause a context switch. + * https://www.freertos.org/Documentation/02-Kernel/03-Supported-devices/04-Demos/Renesas/RTOS_RL78_IAR_Demos#writing-interrupt-service-routines */ + #define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) do { if( xHigherPriorityTaskWoken != pdFALSE ) vTaskSwitchContext(); } while( 0 ) + #else + /* You must not implement an assembly ISR wrapper even if you need an ISR to cause a context switch. + * The portYIELD, which is similar to role of an assembly ISR wrapper, runs only when a context switch is required. */ + #define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) do { if( xHigherPriorityTaskWoken != pdFALSE ) portYIELD(); } while( 0 ) + #endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ + #define portBYTE_ALIGNMENT 2 + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* __IAR_SYSTEMS_ICC__ */ + +; /*----------------------------------------------------------------------------- */ + /* The macros below are processed for asm sources which include portmacro.h. */ + /*----------------------------------------------------------------------------- */ +#ifdef __IAR_SYSTEMS_ASM__ + + ; /* Functions and variables used by this file. */ + /*----------------------------------------------------------------------------- */ + EXTERN _pxCurrentTCB + EXTERN _usCriticalNesting + + ; /* Macro used to declutter calls, depends on the selected code model. */ + /*----------------------------------------------------------------------------- */ + #if __CODE_MODEL__ == __CODE_MODEL_FAR__ + #define RCALL( X ) CALL F: X + #else + #define RCALL( X ) CALL X + #endif + + + ; /*----------------------------------------------------------------------------- + * ; * portSAVE_CONTEXT MACRO + * ; * Saves the context of the general purpose registers, CS and ES (only in __far + * ; * memory mode) registers the _usCriticalNesting value and the Stack Pointer + * ; * of the active Task onto the task stack. + * ; *---------------------------------------------------------------------------*/ +portSAVE_CONTEXT MACRO + PUSH AX; /* Save AX Register to stack. */ + PUSH HL + #if __CODE_MODEL__ == __CODE_MODEL_FAR__ + MOV A, CS; /* Save CS register. */ + XCH A, X + MOV A, ES; /* Save ES register. */ + PUSH AX + #else + MOV A, CS; /* Save CS register. */ + PUSH AX + #endif + PUSH DE; /* Save the remaining general purpose registers. */ + PUSH BC + MOVW AX, _usCriticalNesting; /* Save the _usCriticalNesting value. */ + PUSH AX + MOVW AX, _pxCurrentTCB; /* Save the Task stack pointer. */ + MOVW HL, AX + MOVW AX, SP + MOVW[ HL ], AX + ENDM + ; /*----------------------------------------------------------------------------- */ + + +/*----------------------------------------------------------------------------- + * ; * portRESTORE_CONTEXT MACRO + * ; * Restores the task Stack Pointer then use this to restore _usCriticalNesting, + * ; * general purpose registers and the CS and ES (only in __far memory mode) + * ; * of the selected task from the task stack. + * ; *---------------------------------------------------------------------------*/ +portRESTORE_CONTEXT MACRO + MOVW AX, _pxCurrentTCB; /* Restore the Task stack pointer. */ + MOVW HL, AX + MOVW AX, [ HL ] + MOVW SP, AX + POP AX; /* Restore _usCriticalNesting value. */ + MOVW _usCriticalNesting, AX + POP BC; /* Restore the necessary general purpose registers. */ + POP DE + #if __CODE_MODEL__ == __CODE_MODEL_FAR__ + POP AX; /* Restore the ES register. */ + MOV ES, A + XCH A, X; /* Restore the CS register. */ + MOV CS, A + #else + POP AX + MOV CS, A; /* Restore CS register. */ + #endif + POP HL; /* Restore general purpose register HL. */ + POP AX; /* Restore AX. */ + ENDM + ; /*----------------------------------------------------------------------------- */ + +#endif /* __IAR_SYSTEMS_ASM__ */ + +#endif /* PORTMACRO_H */ diff --git a/portable/IAR/RX100/port.c b/portable/IAR/RX100/port.c new file mode 100644 index 000000000..b63b23b48 --- /dev/null +++ b/portable/IAR/RX100/port.c @@ -0,0 +1,523 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the SH2A port. +*----------------------------------------------------------*/ + +/* Standard C includes. */ +#include "limits.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Library includes. */ +#include "string.h" + +/* Hardware specifics. */ +#include "machine.h" + +/*-----------------------------------------------------------*/ + +/* Tasks should start with interrupts enabled and in Supervisor mode, therefore + * PSW is set with U and I set, and PM and IPL clear. */ +#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) + +/* The peripheral clock is divided by this value before being supplying the + * CMT. */ +#if ( configUSE_TICKLESS_IDLE == 0 ) + /* If tickless idle is not used then the divisor can be fixed. */ + #define portCLOCK_DIVISOR 8UL +#elif ( configPERIPHERAL_CLOCK_HZ >= 12000000 ) + #define portCLOCK_DIVISOR 512UL +#elif ( configPERIPHERAL_CLOCK_HZ >= 6000000 ) + #define portCLOCK_DIVISOR 128UL +#elif ( configPERIPHERAL_CLOCK_HZ >= 1000000 ) + #define portCLOCK_DIVISOR 32UL +#else + #define portCLOCK_DIVISOR 8UL +#endif + + +/* Keys required to lock and unlock access to certain system registers + * respectively. */ +#define portUNLOCK_KEY 0xA50B +#define portLOCK_KEY 0xA500 + +/*-----------------------------------------------------------*/ + +/* + * Function to start the first task executing - written in asm code as direct + * access to registers is required. + */ +extern void prvStartFirstTask( void ); + +/* + * The tick ISR handler. The peripheral used is configured by the application + * via a hook/callback function. + */ +__interrupt static void prvTickISR( void ); + +/* + * Sets up the periodic ISR used for the RTOS tick using the CMT. + * The application writer can define configSETUP_TICK_INTERRUPT() (in + * FreeRTOSConfig.h) such that their own tick interrupt configuration is used + * in place of prvSetupTimerInterrupt(). + */ +static void prvSetupTimerInterrupt( void ); +#ifndef configSETUP_TICK_INTERRUPT + +/* The user has not provided their own tick interrupt configuration so use + * the definition in this file (which uses the interval timer). */ + #define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt() +#endif /* configSETUP_TICK_INTERRUPT */ + +/* + * Called after the sleep mode registers have been configured, prvSleep() + * executes the pre and post sleep macros, and actually calls the wait + * instruction. + */ +#if configUSE_TICKLESS_IDLE == 1 + static void prvSleep( TickType_t xExpectedIdleTime ); +#endif /* configUSE_TICKLESS_IDLE */ + +/*-----------------------------------------------------------*/ + +extern void * pxCurrentTCB; + +/*-----------------------------------------------------------*/ + +/* Calculate how many clock increments make up a single tick period. */ +static const uint32_t ulMatchValueForOneTick = ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ ); + +#if configUSE_TICKLESS_IDLE == 1 + +/* Holds the maximum number of ticks that can be suppressed - which is + * basically how far into the future an interrupt can be generated. Set + * during initialisation. This is the maximum possible value that the + * compare match register can hold divided by ulMatchValueForOneTick. */ + static const TickType_t xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ ); + +/* Flag set from the tick interrupt to allow the sleep processing to know if + * sleep mode was exited because of a tick interrupt, or an interrupt + * generated by something else. */ + static volatile uint32_t ulTickFlag = pdFALSE; + +/* The CMT counter is stopped temporarily each time it is re-programmed. + * The following constant offsets the CMT counter match value by the number of + * CMT counts that would typically be missed while the counter was stopped to + * compensate for the lost time. The large difference between the divided CMT + * clock and the CPU clock means it is likely ulStoppedTimerCompensation will + * equal zero - and be optimised away. */ + static const uint32_t ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) ); + +#endif /* if configUSE_TICKLESS_IDLE == 1 */ + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Offset to end up on 8 byte boundary. */ + pxTopOfStack--; + + /* R0 is not included as it is the stack pointer. */ + *pxTopOfStack = 0x00; + pxTopOfStack--; + *pxTopOfStack = 0x00; + pxTopOfStack--; + *pxTopOfStack = portINITIAL_PSW; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; + + /* When debugging it can be useful if every register is set to a known + * value. Otherwise code space can be saved by just setting the registers + * that need to be set. */ + #ifdef USE_FULL_REGISTER_INITIALISATION + { + pxTopOfStack--; + *pxTopOfStack = 0x12345678; /* r15. */ + pxTopOfStack--; + *pxTopOfStack = 0xaaaabbbb; + pxTopOfStack--; + *pxTopOfStack = 0xdddddddd; + pxTopOfStack--; + *pxTopOfStack = 0xcccccccc; + pxTopOfStack--; + *pxTopOfStack = 0xbbbbbbbb; + pxTopOfStack--; + *pxTopOfStack = 0xaaaaaaaa; + pxTopOfStack--; + *pxTopOfStack = 0x99999999; + pxTopOfStack--; + *pxTopOfStack = 0x88888888; + pxTopOfStack--; + *pxTopOfStack = 0x77777777; + pxTopOfStack--; + *pxTopOfStack = 0x66666666; + pxTopOfStack--; + *pxTopOfStack = 0x55555555; + pxTopOfStack--; + *pxTopOfStack = 0x44444444; + pxTopOfStack--; + *pxTopOfStack = 0x33333333; + pxTopOfStack--; + *pxTopOfStack = 0x22222222; + pxTopOfStack--; + } + #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ + { + /* Leave space for the registers that will get popped from the stack + * when the task first starts executing. */ + pxTopOfStack -= 15; + } + #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */ + + *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = 0x12345678; /* Accumulator. */ + pxTopOfStack--; + *pxTopOfStack = 0x87654321; /* Accumulator. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Use pxCurrentTCB just so it does not get optimised away. */ + if( pxCurrentTCB != NULL ) + { + /* Call an application function to set up the timer that will generate + * the tick interrupt. This way the application can decide which + * peripheral to use. If tickless mode is used then the default + * implementation defined in this file (which uses CMT0) should not be + * overridden. */ + configSETUP_TICK_INTERRUPT(); + + /* Enable the software interrupt. */ + _IEN( _ICU_SWINT ) = 1; + + /* Ensure the software interrupt is clear. */ + _IR( _ICU_SWINT ) = 0; + + /* Ensure the software interrupt is set to the kernel priority. */ + _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the first task. */ + prvStartFirstTask(); + } + + /* Execution should not reach here as the tasks are now running! + * prvSetupTimerInterrupt() is called here to prevent the compiler outputting + * a warning about a statically declared function not being referenced in the + * case that the application writer has provided their own tick interrupt + * configuration routine (and defined configSETUP_TICK_INTERRUPT() such that + * their own routine will be called in place of prvSetupTimerInterrupt()). */ + prvSetupTimerInterrupt(); + + /* Should not get here. */ + return pdFAIL; +} +/*-----------------------------------------------------------*/ + +#pragma vector = configTICK_VECTOR +__interrupt static void prvTickISR( void ) +{ + /* Re-enable interrupts. */ + __enable_interrupt(); + + /* Increment the tick, and perform any processing the new tick value + * necessitates. */ + __set_interrupt_level( configMAX_SYSCALL_INTERRUPT_PRIORITY ); + { + if( xTaskIncrementTick() != pdFALSE ) + { + taskYIELD(); + } + } + __set_interrupt_level( configKERNEL_INTERRUPT_PRIORITY ); + + #if configUSE_TICKLESS_IDLE == 1 + { + /* The CPU woke because of a tick. */ + ulTickFlag = pdTRUE; + + /* If this is the first tick since exiting tickless mode then the CMT + * compare match value needs resetting. */ + CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick; + } + #endif +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( pxCurrentTCB == NULL ); +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ + /* Unlock. */ + SYSTEM.PRCR.WORD = portUNLOCK_KEY; + + /* Enable CMT0. */ + MSTP( CMT0 ) = 0; + + /* Lock again. */ + SYSTEM.PRCR.WORD = portLOCK_KEY; + + /* Interrupt on compare match. */ + CMT0.CMCR.BIT.CMIE = 1; + + /* Set the compare match value. */ + CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick; + + /* Divide the PCLK. */ + #if portCLOCK_DIVISOR == 512 + { + CMT0.CMCR.BIT.CKS = 3; + } + #elif portCLOCK_DIVISOR == 128 + { + CMT0.CMCR.BIT.CKS = 2; + } + #elif portCLOCK_DIVISOR == 32 + { + CMT0.CMCR.BIT.CKS = 1; + } + #elif portCLOCK_DIVISOR == 8 + { + CMT0.CMCR.BIT.CKS = 0; + } + #else /* if portCLOCK_DIVISOR == 512 */ + { + #error Invalid portCLOCK_DIVISOR setting + } + #endif /* if portCLOCK_DIVISOR == 512 */ + + + /* Enable the interrupt... */ + _IEN( _CMT0_CMI0 ) = 1; + + /* ...and set its priority to the application defined kernel priority. */ + _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the timer. */ + CMT.CMSTR0.BIT.STR0 = 1; +} +/*-----------------------------------------------------------*/ + +#if configUSE_TICKLESS_IDLE == 1 + + static void prvSleep( TickType_t xExpectedIdleTime ) + { + /* Allow the application to define some pre-sleep processing. */ + configPRE_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING() + * means the application defined code has already executed the WAIT + * instruction. */ + if( xExpectedIdleTime > 0 ) + { + __wait_for_interrupt(); + } + + /* Allow the application to define some post sleep processing. */ + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if configUSE_TICKLESS_IDLE == 1 + + void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount; + eSleepModeStatus eSleepAction; + + /* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */ + + /* Make sure the CMT reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Calculate the reload value required to wait xExpectedIdleTime tick + * periods. */ + ulMatchValue = ulMatchValueForOneTick * xExpectedIdleTime; + + if( ulMatchValue > ulStoppedTimerCompensation ) + { + /* Compensate for the fact that the CMT is going to be stopped + * momentarily. */ + ulMatchValue -= ulStoppedTimerCompensation; + } + + /* Stop the CMT momentarily. The time the CMT is stopped for is + * accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + CMT.CMSTR0.BIT.STR0 = 0; + + while( CMT.CMSTR0.BIT.STR0 == 1 ) + { + /* Nothing to do here. */ + } + + /* Critical section using the global interrupt bit as the i bit is + * automatically reset by the WAIT instruction. */ + __disable_interrupt(); + + /* The tick flag is set to false before sleeping. If it is true when + * sleep mode is exited then sleep mode was probably exited because the + * tick was suppressed for the entire xExpectedIdleTime period. */ + ulTickFlag = pdFALSE; + + /* If a context switch is pending then abandon the low power entry as + * the context switch might have been pended by an external interrupt that + * requires processing. */ + eSleepAction = eTaskConfirmSleepModeStatus(); + + if( eSleepAction == eAbortSleep ) + { + /* Restart tick. */ + CMT.CMSTR0.BIT.STR0 = 1; + __enable_interrupt(); + } + else if( eSleepAction == eNoTasksWaitingTimeout ) + { + /* Protection off. */ + SYSTEM.PRCR.WORD = portUNLOCK_KEY; + + /* Ready for software standby with all clocks stopped. */ + SYSTEM.SBYCR.BIT.SSBY = 1; + + /* Protection on. */ + SYSTEM.PRCR.WORD = portLOCK_KEY; + + /* Sleep until something happens. Calling prvSleep() will + * automatically reset the i bit in the PSW. */ + prvSleep( xExpectedIdleTime ); + + /* Restart the CMT. */ + CMT.CMSTR0.BIT.STR0 = 1; + } + else + { + /* Protection off. */ + SYSTEM.PRCR.WORD = portUNLOCK_KEY; + + /* Ready for deep sleep mode. */ + SYSTEM.MSTPCRC.BIT.DSLPE = 1; + SYSTEM.MSTPCRA.BIT.MSTPA28 = 1; + SYSTEM.SBYCR.BIT.SSBY = 0; + + /* Protection on. */ + SYSTEM.PRCR.WORD = portLOCK_KEY; + + /* Adjust the match value to take into account that the current + * time slice is already partially complete. */ + ulMatchValue -= ( uint32_t ) CMT0.CMCNT; + CMT0.CMCOR = ( uint16_t ) ulMatchValue; + + /* Restart the CMT to count up to the new match value. */ + CMT0.CMCNT = 0; + CMT.CMSTR0.BIT.STR0 = 1; + + /* Sleep until something happens. Calling prvSleep() will + * automatically reset the i bit in the PSW. */ + prvSleep( xExpectedIdleTime ); + + /* Stop CMT. Again, the time the SysTick is stopped for is + * accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + CMT.CMSTR0.BIT.STR0 = 0; + + while( CMT.CMSTR0.BIT.STR0 == 1 ) + { + /* Nothing to do here. */ + } + + ulCurrentCount = ( uint32_t ) CMT0.CMCNT; + + if( ulTickFlag != pdFALSE ) + { + /* The tick interrupt has already executed, although because + * this function is called with the scheduler suspended the actual + * tick processing will not occur until after this function has + * exited. Reset the match value with whatever remains of this + * tick period. */ + ulMatchValue = ulMatchValueForOneTick - ulCurrentCount; + CMT0.CMCOR = ( uint16_t ) ulMatchValue; + + /* The tick interrupt handler will already have pended the tick + * processing in the kernel. As the pending tick will be + * processed as soon as this function exits, the tick value + * maintained by the tick is stepped forward by one less than the + * time spent sleeping. The actual stepping of the tick appears + * later in this function. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. + * How many complete tick periods passed while the processor was + * sleeping? */ + ulCompleteTickPeriods = ulCurrentCount / ulMatchValueForOneTick; + + /* The match value is set to whatever fraction of a single tick + * period remains. */ + ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick ); + CMT0.CMCOR = ( uint16_t ) ulMatchValue; + } + + /* Restart the CMT so it runs up to the match value. The match value + * will get set to the value required to generate exactly one tick period + * the next time the CMT interrupt executes. */ + CMT0.CMCNT = 0; + CMT.CMSTR0.BIT.STR0 = 1; + + /* Wind the tick forward by the number of tick periods that the CPU + * remained in a low power state. */ + vTaskStepTick( ulCompleteTickPeriods ); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ diff --git a/portable/IAR/RX100/port_asm.s b/portable/IAR/RX100/port_asm.s new file mode 100644 index 000000000..5eb90f7d1 --- /dev/null +++ b/portable/IAR/RX100/port_asm.s @@ -0,0 +1,151 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include "PriorityDefinitions.h" + + PUBLIC _prvStartFirstTask + PUBLIC ___interrupt_27 + + EXTERN _pxCurrentTCB + EXTERN _vTaskSwitchContext + + RSEG CODE:CODE(4) + +_prvStartFirstTask: + + /* When starting the scheduler there is nothing that needs moving to the + interrupt stack because the function is not called from an interrupt. + Just ensure the current stack is the user stack. */ + SETPSW U + + /* Obtain the location of the stack associated with which ever task + pxCurrentTCB is currently pointing to. */ + MOV.L #_pxCurrentTCB, R15 + MOV.L [R15], R15 + MOV.L [R15], R0 + + /* Restore the registers from the stack of the task pointed to by + pxCurrentTCB. */ + POP R15 + + /* Accumulator low 32 bits. */ + MVTACLO R15 + POP R15 + + /* Accumulator high 32 bits. */ + MVTACHI R15 + + /* R1 to R15 - R0 is not included as it is the SP. */ + POPM R1-R15 + + /* This pops the remaining registers. */ + RTE + NOP + NOP + +/*-----------------------------------------------------------*/ + +/* The software interrupt - overwrite the default 'weak' definition. */ +___interrupt_27: + + /* Re-enable interrupts. */ + SETPSW I + + /* Move the data that was automatically pushed onto the interrupt stack when + the interrupt occurred from the interrupt stack to the user stack. + + R15 is saved before it is clobbered. */ + PUSH.L R15 + + /* Read the user stack pointer. */ + MVFC USP, R15 + + /* Move the address down to the data being moved. */ + SUB #12, R15 + MVTC R15, USP + + /* Copy the data across, R15, then PC, then PSW. */ + MOV.L [ R0 ], [ R15 ] + MOV.L 4[ R0 ], 4[ R15 ] + MOV.L 8[ R0 ], 8[ R15 ] + + /* Move the interrupt stack pointer to its new correct position. */ + ADD #12, R0 + + /* All the rest of the registers are saved directly to the user stack. */ + SETPSW U + + /* Save the rest of the general registers (R15 has been saved already). */ + PUSHM R1-R14 + + /* Save the accumulator. */ + MVFACHI R15 + PUSH.L R15 + + /* Middle word. */ + MVFACMI R15 + + /* Shifted left as it is restored to the low order word. */ + SHLL #16, R15 + PUSH.L R15 + + /* Save the stack pointer to the TCB. */ + MOV.L #_pxCurrentTCB, R15 + MOV.L [ R15 ], R15 + MOV.L R0, [ R15 ] + + /* Ensure the interrupt mask is set to the syscall priority while the kernel + structures are being accessed. */ + MVTIPL #configMAX_SYSCALL_INTERRUPT_PRIORITY + + /* Select the next task to run. */ + BSR.A _vTaskSwitchContext + + /* Reset the interrupt mask as no more data structure access is required. */ + MVTIPL #configKERNEL_INTERRUPT_PRIORITY + + /* Load the stack pointer of the task that is now selected as the Running + state task from its TCB. */ + MOV.L #_pxCurrentTCB,R15 + MOV.L [ R15 ], R15 + MOV.L [ R15 ], R0 + + /* Restore the context of the new task. The PSW (Program Status Word) and + PC will be popped by the RTE instruction. */ + POP R15 + MVTACLO R15 + POP R15 + MVTACHI R15 + POPM R1-R15 + RTE + NOP + NOP + +/*-----------------------------------------------------------*/ + + END diff --git a/portable/IAR/RX100/portmacro.h b/portable/IAR/RX100/portmacro.h new file mode 100644 index 000000000..ab5eae69f --- /dev/null +++ b/portable/IAR/RX100/portmacro.h @@ -0,0 +1,156 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#include + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/* Hardware specifics. */ +#include "machine.h" + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions - these are a bit legacy and not really used now, other than + * portSTACK_TYPE and portBASE_TYPE. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() __no_operation() + +#define portYIELD() \ + __asm volatile \ + ( \ + "MOV.L #0x872E0, R15 \n" \ + "MOV.B #1, [R15] \n" \ + "MOV.L [R15], R15 \n" \ + ::: "R15" \ + ) + +#define portYIELD_FROM_ISR( x ) do { if( ( x ) != pdFALSE ) { portYIELD(); } } while( 0 ) + +/* These macros should not be called directly, but through the + * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is + * performed if configASSERT() is defined to ensure an assertion handler does not + * inadvertently attempt to lower the IPL when the call to assert was triggered + * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY + * when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API + * functions are those that end in FromISR. FreeRTOS maintains a separate + * interrupt API to ensure API function and interrupt entry is as fast and as + * simple as possible. */ +#define portENABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) 0 ) +#if ( configASSERT_DEFINED == 1 ) + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) + #define portDISABLE_INTERRUPTS() if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#else + #define portDISABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#endif + +/* Critical nesting counts are stored in the TCB. */ +#define portCRITICAL_NESTING_IN_TCB ( 1 ) + +/* The critical nesting functions defined within tasks.c. */ +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() + +/* As this port allows interrupt nesting... */ +#define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_level(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) __set_interrupt_level( ( uint8_t ) ( uxSavedInterruptStatus ) ) + +/* Tickless idle/low power functionality. */ +#if configUSE_TICKLESS_IDLE == 1 + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif +#endif + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* Prevent warnings of undefined behaviour: the order of volatile accesses is + * undefined - all warnings have been manually checked and are not an issue, and + * the warnings cannot be prevent by code changes without undesirable effects. */ +#pragma diag_suppress=Pa082 + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/IAR/RX100/readme.txt b/portable/IAR/RX100/readme.txt new file mode 100644 index 000000000..8dbc983fd --- /dev/null +++ b/portable/IAR/RX100/readme.txt @@ -0,0 +1,71 @@ +The following table shows which port is recommended to be used. + + +RX MCU Group CPU FPU FPU Port Layer + Core (Single (Double CC-RX GNURX ICCRX (*6) + Type Precision) Precision) + +RX110 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX111 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX113 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX130 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX13T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 + +RX210 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX21A RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX220 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX230,RX231 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23E-A RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23W RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24U RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 + +RX610 RXv1 Yes --- N/A (*4) N/A (*4) N/A (*4) +RX62N,RX621 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX630 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX634 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63N,RX631 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX64M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX65N,RX651 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX66N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX62T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX62G RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX66T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +RX71M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX72M RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +Notes: + +*1: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is not used, please define configSETUP_TICK_INTERRUPT() (in FreeRTOSConfig.h) and provide +the configuration function. Please be aware that port.c is hard coded to use CMT0 though it seems to be +configured to use any CMTn according to the definition of configTICK_VECTOR (in FreeRTOSConfig.h). + +*2: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is used, please modify port.c for the configuration. Please be aware that port.c is +hard coded to use CMT0 though it seems to be configured to use any CMTn according to the definition of +configTICK_VECTOR (in FreeRTOSConfig.h). + +*3: RX100 ports are also available. + +*4: RX600 ports use MVTIPL instruction but RX610 MCUs don't support this instruction. + +*5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h. + +#define configUSE_TASK_DPFPU_SUPPORT 0 + +*6: PriorityDefinitions.h has to be provided for port_asm.s in case of other than RX700v3_DPFPU port. +It contains two definitions of interrupt priority like the following. + +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + + +For more information about Renesas RX MCUs, please visit the following URL: + +https://www.renesas.com/products/microcontrollers-microprocessors/rx.html diff --git a/portable/IAR/RX600/port.c b/portable/IAR/RX600/port.c new file mode 100644 index 000000000..73ff96cff --- /dev/null +++ b/portable/IAR/RX600/port.c @@ -0,0 +1,193 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the SH2A port. +*----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Library includes. */ +#include "string.h" + +/* Hardware specifics. */ +#include + +/*-----------------------------------------------------------*/ + +/* Tasks should start with interrupts enabled and in Supervisor mode, therefore + * PSW is set with U and I set, and PM and IPL clear. */ +#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) +#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 ) + +/*-----------------------------------------------------------*/ + +/* + * Function to start the first task executing - written in asm code as direct + * access to registers is required. + */ +extern void prvStartFirstTask( void ); + +/* + * The tick ISR handler. The peripheral used is configured by the application + * via a hook/callback function. + */ +__interrupt void vTickISR( void ); + +/*-----------------------------------------------------------*/ + +extern void * pxCurrentTCB; + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* R0 is not included as it is the stack pointer. */ + + *pxTopOfStack = 0x00; + pxTopOfStack--; + *pxTopOfStack = portINITIAL_PSW; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; + + /* When debugging it can be useful if every register is set to a known + * value. Otherwise code space can be saved by just setting the registers + * that need to be set. */ + #ifdef USE_FULL_REGISTER_INITIALISATION + { + pxTopOfStack--; + *pxTopOfStack = 0xffffffff; /* r15. */ + pxTopOfStack--; + *pxTopOfStack = 0xeeeeeeee; + pxTopOfStack--; + *pxTopOfStack = 0xdddddddd; + pxTopOfStack--; + *pxTopOfStack = 0xcccccccc; + pxTopOfStack--; + *pxTopOfStack = 0xbbbbbbbb; + pxTopOfStack--; + *pxTopOfStack = 0xaaaaaaaa; + pxTopOfStack--; + *pxTopOfStack = 0x99999999; + pxTopOfStack--; + *pxTopOfStack = 0x88888888; + pxTopOfStack--; + *pxTopOfStack = 0x77777777; + pxTopOfStack--; + *pxTopOfStack = 0x66666666; + pxTopOfStack--; + *pxTopOfStack = 0x55555555; + pxTopOfStack--; + *pxTopOfStack = 0x44444444; + pxTopOfStack--; + *pxTopOfStack = 0x33333333; + pxTopOfStack--; + *pxTopOfStack = 0x22222222; + pxTopOfStack--; + } + #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ + { + pxTopOfStack -= 15; + } + #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */ + + *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_FPSW; + pxTopOfStack--; + *pxTopOfStack = 0x12345678; /* Accumulator. */ + pxTopOfStack--; + *pxTopOfStack = 0x87654321; /* Accumulator. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + extern void vApplicationSetupTimerInterrupt( void ); + + /* Use pxCurrentTCB just so it does not get optimised away. */ + if( pxCurrentTCB != NULL ) + { + /* Call an application function to set up the timer that will generate the + * tick interrupt. This way the application can decide which peripheral to + * use. A demo application is provided to show a suitable example. */ + vApplicationSetupTimerInterrupt(); + + /* Enable the software interrupt. */ + _IEN( _ICU_SWINT ) = 1; + + /* Ensure the software interrupt is clear. */ + _IR( _ICU_SWINT ) = 0; + + /* Ensure the software interrupt is set to the kernel priority. */ + _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the first task. */ + prvStartFirstTask(); + } + + /* Should not get here. */ + return pdFAIL; +} +/*-----------------------------------------------------------*/ + +#pragma vector = configTICK_VECTOR +__interrupt void vTickISR( void ) +{ + /* Re-enable interrupts. */ + __enable_interrupt(); + + /* Increment the tick, and perform any processing the new tick value + * necessitates. */ + __set_interrupt_level( configMAX_SYSCALL_INTERRUPT_PRIORITY ); + { + if( xTaskIncrementTick() != pdFALSE ) + { + taskYIELD(); + } + } + __set_interrupt_level( configKERNEL_INTERRUPT_PRIORITY ); +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( pxCurrentTCB == NULL ); +} +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/RX600/port_asm.s b/portable/IAR/RX600/port_asm.s new file mode 100644 index 000000000..29698534d --- /dev/null +++ b/portable/IAR/RX600/port_asm.s @@ -0,0 +1,159 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include "PriorityDefinitions.h" + + PUBLIC _prvStartFirstTask + PUBLIC ___interrupt_27 + + EXTERN _pxCurrentTCB + EXTERN _vTaskSwitchContext + + RSEG CODE:CODE(4) + +_prvStartFirstTask: + + /* When starting the scheduler there is nothing that needs moving to the + interrupt stack because the function is not called from an interrupt. + Just ensure the current stack is the user stack. */ + SETPSW U + + /* Obtain the location of the stack associated with which ever task + pxCurrentTCB is currently pointing to. */ + MOV.L #_pxCurrentTCB, R15 + MOV.L [R15], R15 + MOV.L [R15], R0 + + /* Restore the registers from the stack of the task pointed to by + pxCurrentTCB. */ + POP R15 + + /* Accumulator low 32 bits. */ + MVTACLO R15 + POP R15 + + /* Accumulator high 32 bits. */ + MVTACHI R15 + POP R15 + + /* Floating point status word. */ + MVTC R15, FPSW + + /* R1 to R15 - R0 is not included as it is the SP. */ + POPM R1-R15 + + /* This pops the remaining registers. */ + RTE + NOP + NOP + +/*-----------------------------------------------------------*/ + +/* The software interrupt - overwrite the default 'weak' definition. */ +___interrupt_27: + + /* Re-enable interrupts. */ + SETPSW I + + /* Move the data that was automatically pushed onto the interrupt stack when + the interrupt occurred from the interrupt stack to the user stack. + + R15 is saved before it is clobbered. */ + PUSH.L R15 + + /* Read the user stack pointer. */ + MVFC USP, R15 + + /* Move the address down to the data being moved. */ + SUB #12, R15 + MVTC R15, USP + + /* Copy the data across, R15, then PC, then PSW. */ + MOV.L [ R0 ], [ R15 ] + MOV.L 4[ R0 ], 4[ R15 ] + MOV.L 8[ R0 ], 8[ R15 ] + + /* Move the interrupt stack pointer to its new correct position. */ + ADD #12, R0 + + /* All the rest of the registers are saved directly to the user stack. */ + SETPSW U + + /* Save the rest of the general registers (R15 has been saved already). */ + PUSHM R1-R14 + + /* Save the FPSW and accumulator. */ + MVFC FPSW, R15 + PUSH.L R15 + MVFACHI R15 + PUSH.L R15 + + /* Middle word. */ + MVFACMI R15 + + /* Shifted left as it is restored to the low order word. */ + SHLL #16, R15 + PUSH.L R15 + + /* Save the stack pointer to the TCB. */ + MOV.L #_pxCurrentTCB, R15 + MOV.L [ R15 ], R15 + MOV.L R0, [ R15 ] + + /* Ensure the interrupt mask is set to the syscall priority while the kernel + structures are being accessed. */ + MVTIPL #configMAX_SYSCALL_INTERRUPT_PRIORITY + + /* Select the next task to run. */ + BSR.A _vTaskSwitchContext + + /* Reset the interrupt mask as no more data structure access is required. */ + MVTIPL #configKERNEL_INTERRUPT_PRIORITY + + /* Load the stack pointer of the task that is now selected as the Running + state task from its TCB. */ + MOV.L #_pxCurrentTCB,R15 + MOV.L [ R15 ], R15 + MOV.L [ R15 ], R0 + + /* Restore the context of the new task. The PSW (Program Status Word) and + PC will be popped by the RTE instruction. */ + POP R15 + MVTACLO R15 + POP R15 + MVTACHI R15 + POP R15 + MVTC R15, FPSW + POPM R1-R15 + RTE + NOP + NOP + +/*-----------------------------------------------------------*/ + + END diff --git a/portable/IAR/RX600/portmacro.h b/portable/IAR/RX600/portmacro.h new file mode 100644 index 000000000..87faf8639 --- /dev/null +++ b/portable/IAR/RX600/portmacro.h @@ -0,0 +1,145 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#include + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions - these are a bit legacy and not really used now, other than + * portSTACK_TYPE and portBASE_TYPE. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() __no_operation() + +/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;" + * where portITU_SWINTR is the location of the software interrupt register + * (0x000872E0). Don't rely on the assembler to select a register, so instead + * save and restore clobbered registers manually. */ +#define portYIELD() \ + __asm volatile \ + ( \ + "PUSH.L R10 \n" \ + "MOV.L #0x872E0, R10 \n" \ + "MOV.B #0x1, [R10] \n" \ + "MOV.L [R10], R10 \n" \ + "POP R10 \n" \ + ) + +#define portYIELD_FROM_ISR( x ) do { if( ( x ) != pdFALSE ) portYIELD( ); } while( 0 ) + +/* These macros should not be called directly, but through the + * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is + * performed if configASSERT() is defined to ensure an assertion handler does not + * inadvertently attempt to lower the IPL when the call to assert was triggered + * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY + * when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API + * functions are those that end in FromISR. FreeRTOS maintains a separate + * interrupt API to ensure API function and interrupt entry is as fast and as + * simple as possible. */ +#define portENABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) 0 ) +#if ( configASSERT_DEFINED == 1 ) + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) + #define portDISABLE_INTERRUPTS() if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#else + #define portDISABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#endif + +/* Critical nesting counts are stored in the TCB. */ +#define portCRITICAL_NESTING_IN_TCB ( 1 ) + +/* The critical nesting functions defined within tasks.c. */ +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() + +/* As this port allows interrupt nesting... */ +#define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_level(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) __set_interrupt_level( ( uint8_t ) ( uxSavedInterruptStatus ) ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/IAR/RX600/readme.txt b/portable/IAR/RX600/readme.txt new file mode 100644 index 000000000..8dbc983fd --- /dev/null +++ b/portable/IAR/RX600/readme.txt @@ -0,0 +1,71 @@ +The following table shows which port is recommended to be used. + + +RX MCU Group CPU FPU FPU Port Layer + Core (Single (Double CC-RX GNURX ICCRX (*6) + Type Precision) Precision) + +RX110 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX111 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX113 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX130 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX13T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 + +RX210 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX21A RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX220 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX230,RX231 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23E-A RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23W RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24U RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 + +RX610 RXv1 Yes --- N/A (*4) N/A (*4) N/A (*4) +RX62N,RX621 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX630 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX634 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63N,RX631 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX64M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX65N,RX651 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX66N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX62T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX62G RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX66T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +RX71M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX72M RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +Notes: + +*1: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is not used, please define configSETUP_TICK_INTERRUPT() (in FreeRTOSConfig.h) and provide +the configuration function. Please be aware that port.c is hard coded to use CMT0 though it seems to be +configured to use any CMTn according to the definition of configTICK_VECTOR (in FreeRTOSConfig.h). + +*2: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is used, please modify port.c for the configuration. Please be aware that port.c is +hard coded to use CMT0 though it seems to be configured to use any CMTn according to the definition of +configTICK_VECTOR (in FreeRTOSConfig.h). + +*3: RX100 ports are also available. + +*4: RX600 ports use MVTIPL instruction but RX610 MCUs don't support this instruction. + +*5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h. + +#define configUSE_TASK_DPFPU_SUPPORT 0 + +*6: PriorityDefinitions.h has to be provided for port_asm.s in case of other than RX700v3_DPFPU port. +It contains two definitions of interrupt priority like the following. + +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + + +For more information about Renesas RX MCUs, please visit the following URL: + +https://www.renesas.com/products/microcontrollers-microprocessors/rx.html diff --git a/portable/IAR/RX700v3_DPFPU/port.c b/portable/IAR/RX700v3_DPFPU/port.c new file mode 100644 index 000000000..d05835975 --- /dev/null +++ b/portable/IAR/RX700v3_DPFPU/port.c @@ -0,0 +1,565 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the RXv3 DPFPU port. +*----------------------------------------------------------*/ + +#warning Testing for DFPU support in this port is not yet complete + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Library includes. */ +#include "string.h" + +/* Hardware specifics. */ +#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 ) + + #include "platform.h" + +#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + + #include "iodefine.h" + +#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + +/*-----------------------------------------------------------*/ + +/* Tasks should start with interrupts enabled and in Supervisor mode, therefore + * PSW is set with U and I set, and PM and IPL clear. */ +#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) +#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 ) +#define portINITIAL_DPSW ( ( StackType_t ) 0x00000100 ) +#define portINITIAL_DCMR ( ( StackType_t ) 0x00000000 ) +#define portINITIAL_DECNT ( ( StackType_t ) 0x00000001 ) + +/* Tasks are not created with a DPFPU context, but can be given a DPFPU context + * after they have been created. A variable is stored as part of the tasks context + * that holds portNO_DPFPU_CONTEXT if the task does not have a DPFPU context, or + * any other value if the task does have a DPFPU context. */ +#define portNO_DPFPU_CONTEXT ( ( StackType_t ) 0 ) +#define portHAS_DPFPU_CONTEXT ( ( StackType_t ) 1 ) + +/* The space on the stack required to hold the DPFPU data registers. This is 16 + * 64-bit registers. */ +#define portDPFPU_DATA_REGISTER_WORDS ( 16 * 2 ) + +/*-----------------------------------------------------------*/ + +/* + * Function to start the first task executing - written in asm code as direct + * access to registers is required. + */ +static void prvStartFirstTask( void ); + +/* + * Software interrupt handler. Performs the actual context switch (saving and + * restoring of registers). Written in asm code as direct register access is + * required. + */ +__interrupt void vSoftwareInterruptISR( void ); + +/* + * The tick ISR handler. The peripheral used is configured by the application + * via a hook/callback function. + */ +__interrupt void vTickISR( void ); + +/*-----------------------------------------------------------*/ + +/* Saved as part of the task context. If ulPortTaskHasDPFPUContext is non-zero + * then a DPFPU context must be saved and restored for the task. */ +#if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) + + StackType_t ulPortTaskHasDPFPUContext = portNO_DPFPU_CONTEXT; + +#endif /* configUSE_TASK_DPFPU_SUPPORT */ + +/* This is accessed by the inline assembler functions so is file scope for + * convenience. */ +extern void * pxCurrentTCB; +extern void vTaskSwitchContext( void ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* R0 is not included as it is the stack pointer. */ + + *pxTopOfStack = 0x00; + pxTopOfStack--; + *pxTopOfStack = portINITIAL_PSW; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; + + /* When debugging it can be useful if every register is set to a known + * value. Otherwise code space can be saved by just setting the registers + * that need to be set. */ + #ifdef USE_FULL_REGISTER_INITIALISATION + { + pxTopOfStack--; + *pxTopOfStack = 0xffffffff; /* r15. */ + pxTopOfStack--; + *pxTopOfStack = 0xeeeeeeee; + pxTopOfStack--; + *pxTopOfStack = 0xdddddddd; + pxTopOfStack--; + *pxTopOfStack = 0xcccccccc; + pxTopOfStack--; + *pxTopOfStack = 0xbbbbbbbb; + pxTopOfStack--; + *pxTopOfStack = 0xaaaaaaaa; + pxTopOfStack--; + *pxTopOfStack = 0x99999999; + pxTopOfStack--; + *pxTopOfStack = 0x88888888; + pxTopOfStack--; + *pxTopOfStack = 0x77777777; + pxTopOfStack--; + *pxTopOfStack = 0x66666666; + pxTopOfStack--; + *pxTopOfStack = 0x55555555; + pxTopOfStack--; + *pxTopOfStack = 0x44444444; + pxTopOfStack--; + *pxTopOfStack = 0x33333333; + pxTopOfStack--; + *pxTopOfStack = 0x22222222; + pxTopOfStack--; + } + #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ + { + pxTopOfStack -= 15; + } + #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */ + + *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_FPSW; + pxTopOfStack--; + *pxTopOfStack = 0x11111111; /* Accumulator 1. */ + pxTopOfStack--; + *pxTopOfStack = 0x22222222; /* Accumulator 1. */ + pxTopOfStack--; + *pxTopOfStack = 0x33333333; /* Accumulator 1. */ + pxTopOfStack--; + *pxTopOfStack = 0x44444444; /* Accumulator 0. */ + pxTopOfStack--; + *pxTopOfStack = 0x55555555; /* Accumulator 0. */ + pxTopOfStack--; + *pxTopOfStack = 0x66666666; /* Accumulator 0. */ + + #if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) + { + /* The task will start without a DPFPU context. A task that + * uses the DPFPU hardware must call vPortTaskUsesDPFPU() before + * executing any floating point instructions. */ + pxTopOfStack--; + *pxTopOfStack = portNO_DPFPU_CONTEXT; + } + #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 ) + { + /* The task will start with a DPFPU context. Leave enough + * space for the registers - and ensure they are initialised if desired. */ + #ifdef USE_FULL_REGISTER_INITIALISATION + { + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 1515.1515; /* DR15. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 1414.1414; /* DR14. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 1313.1313; /* DR13. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 1212.1212; /* DR12. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 1111.1111; /* DR11. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 1010.1010; /* DR10. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 909.0909; /* DR9. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 808.0808; /* DR8. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 707.0707; /* DR7. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 606.0606; /* DR6. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 505.0505; /* DR5. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 404.0404; /* DR4. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 303.0303; /* DR3. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 202.0202; /* DR2. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 101.0101; /* DR1. */ + pxTopOfStack -= 2; + *( double * ) pxTopOfStack = 9876.54321; /* DR0. */ + } + #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ + { + pxTopOfStack -= portDPFPU_DATA_REGISTER_WORDS; + memset( pxTopOfStack, 0x00, portDPFPU_DATA_REGISTER_WORDS * sizeof( StackType_t ) ); + } + #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_DECNT; /* DECNT. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_DCMR; /* DCMR. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_DPSW; /* DPSW. */ + } + #elif ( configUSE_TASK_DPFPU_SUPPORT == 0 ) + { + /* Omit DPFPU support. */ + } + #else /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */ + { + #error Invalid configUSE_TASK_DPFPU_SUPPORT setting - configUSE_TASK_DPFPU_SUPPORT must be set to 0, 1, 2, or left undefined. + } + #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) + + void vPortTaskUsesDPFPU( void ) + { + /* A task is registering the fact that it needs a DPFPU context. Set the + * DPFPU flag (which is saved as part of the task context). */ + ulPortTaskHasDPFPUContext = portHAS_DPFPU_CONTEXT; + } + +#endif /* configUSE_TASK_DPFPU_SUPPORT */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + extern void vApplicationSetupTimerInterrupt( void ); + + /* Use pxCurrentTCB just so it does not get optimised away. */ + if( pxCurrentTCB != NULL ) + { + /* Call an application function to set up the timer that will generate the + * tick interrupt. This way the application can decide which peripheral to + * use. A demo application is provided to show a suitable example. */ + vApplicationSetupTimerInterrupt(); + + /* Enable the software interrupt. */ + _IEN( _ICU_SWINT ) = 1; + + /* Ensure the software interrupt is clear. */ + _IR( _ICU_SWINT ) = 0; + + /* Ensure the software interrupt is set to the kernel priority. */ + _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the first task. */ + prvStartFirstTask(); + } + + /* Should not get here. */ + return pdFAIL; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( pxCurrentTCB == NULL ); + + /* The following line is just to prevent the symbol getting optimised away. */ + ( void ) vTaskSwitchContext(); +} +/*-----------------------------------------------------------*/ + +static void prvStartFirstTask( void ) +{ + __asm volatile + ( + + /* When starting the scheduler there is nothing that needs moving to the + * interrupt stack because the function is not called from an interrupt. + * Just ensure the current stack is the user stack. */ + "SETPSW U \n" \ + + + /* Obtain the location of the stack associated with which ever task + * pxCurrentTCB is currently pointing to. */ + "MOV.L #_pxCurrentTCB, R15 \n" \ + "MOV.L [R15], R15 \n" \ + "MOV.L [R15], R0 \n" \ + + + /* Restore the registers from the stack of the task pointed to by + * pxCurrentTCB. */ + + #if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) + + /* The restored ulPortTaskHasDPFPUContext is to be zero here. + * So, it is never necessary to restore the DPFPU context here. */ + "POP R15 \n" \ + "MOV.L #_ulPortTaskHasDPFPUContext, R14 \n" \ + "MOV.L R15, [R14] \n" \ + + #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 ) + /* Restore the DPFPU context. */ + "DPOPM.L DPSW-DECNT \n" \ + "DPOPM.D DR0-DR15 \n" \ + + #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */ + + "POP R15 \n" \ + + /* Accumulator low 32 bits. */ + "MVTACLO R15, A0 \n" \ + "POP R15 \n" \ + + /* Accumulator high 32 bits. */ + "MVTACHI R15, A0 \n" \ + "POP R15 \n" \ + + /* Accumulator guard. */ + "MVTACGU R15, A0 \n" \ + "POP R15 \n" \ + + /* Accumulator low 32 bits. */ + "MVTACLO R15, A1 \n" \ + "POP R15 \n" \ + + /* Accumulator high 32 bits. */ + "MVTACHI R15, A1 \n" \ + "POP R15 \n" \ + + /* Accumulator guard. */ + "MVTACGU R15, A1 \n" \ + "POP R15 \n" \ + + /* Floating point status word. */ + "MVTC R15, FPSW \n" \ + + /* R1 to R15 - R0 is not included as it is the SP. */ + "POPM R1-R15 \n" \ + + /* This pops the remaining registers. */ + "RTE \n" \ + "NOP \n" \ + "NOP \n" + ); +} +/*-----------------------------------------------------------*/ + +#pragma vector = VECT( ICU, SWINT ) +__interrupt void vSoftwareInterruptISR( void ) +{ + __asm volatile + ( + /* Re-enable interrupts. */ + "SETPSW I \n" \ + + + /* Move the data that was automatically pushed onto the interrupt stack when + * the interrupt occurred from the interrupt stack to the user stack. + * + * R15 is saved before it is clobbered. */ + "PUSH.L R15 \n" \ + + /* Read the user stack pointer. */ + "MVFC USP, R15 \n" \ + + /* Move the address down to the data being moved. */ + "SUB #12, R15 \n" \ + "MVTC R15, USP \n" \ + + /* Copy the data across, R15, then PC, then PSW. */ + "MOV.L [ R0 ], [ R15 ] \n" \ + "MOV.L 4[ R0 ], 4[ R15 ] \n" \ + "MOV.L 8[ R0 ], 8[ R15 ] \n" \ + + /* Move the interrupt stack pointer to its new correct position. */ + "ADD #12, R0 \n" \ + + /* All the rest of the registers are saved directly to the user stack. */ + "SETPSW U \n" \ + + /* Save the rest of the general registers (R15 has been saved already). */ + "PUSHM R1-R14 \n" \ + + /* Save the FPSW and accumulators. */ + "MVFC FPSW, R15 \n" \ + "PUSH.L R15 \n" \ + "MVFACGU #0, A1, R15 \n" \ + "PUSH.L R15 \n" \ + "MVFACHI #0, A1, R15 \n" \ + "PUSH.L R15 \n" \ + "MVFACLO #0, A1, R15 \n" /* Low order word. */ \ + "PUSH.L R15 \n" \ + "MVFACGU #0, A0, R15 \n" \ + "PUSH.L R15 \n" \ + "MVFACHI #0, A0, R15 \n" \ + "PUSH.L R15 \n" \ + "MVFACLO #0, A0, R15 \n" /* Low order word. */ \ + "PUSH.L R15 \n" \ + + #if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) + + /* Does the task have a DPFPU context that needs saving? If + * ulPortTaskHasDPFPUContext is 0 then no. */ + "MOV.L #_ulPortTaskHasDPFPUContext, R15 \n" \ + "MOV.L [R15], R15 \n" \ + "CMP #0, R15 \n" \ + + /* Save the DPFPU context, if any. */ + "BEQ.B __lab1 \n" \ + "DPUSHM.D DR0-DR15 \n" \ + "DPUSHM.L DPSW-DECNT \n" \ + "__lab1: \n" \ + + /* Save ulPortTaskHasDPFPUContext itself. */ + "PUSH.L R15 \n" \ + + #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 ) + /* Save the DPFPU context, always. */ + "DPUSHM.D DR0-DR15 \n" \ + "DPUSHM.L DPSW-DECNT \n" \ + + #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */ + + + /* Save the stack pointer to the TCB. */ + "MOV.L #_pxCurrentTCB, R15 \n" \ + "MOV.L [ R15 ], R15 \n" \ + "MOV.L R0, [ R15 ] \n" \ + + + /* Ensure the interrupt mask is set to the syscall priority while the kernel + * structures are being accessed. */ + "MVTIPL %0 \n" \ + + /* Select the next task to run. */ + "BSR.A _vTaskSwitchContext \n" \ + + /* Reset the interrupt mask as no more data structure access is required. */ + "MVTIPL %1 \n" \ + + + /* Load the stack pointer of the task that is now selected as the Running + * state task from its TCB. */ + "MOV.L #_pxCurrentTCB,R15 \n" \ + "MOV.L [ R15 ], R15 \n" \ + "MOV.L [ R15 ], R0 \n" \ + + + /* Restore the context of the new task. The PSW (Program Status Word) and + * PC will be popped by the RTE instruction. */ + + #if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) + + /* Is there a DPFPU context to restore? If the restored + * ulPortTaskHasDPFPUContext is zero then no. */ + "POP R15 \n" \ + "MOV.L #_ulPortTaskHasDPFPUContext, R14 \n" \ + "MOV.L R15, [R14] \n" \ + "CMP #0, R15 \n" \ + + /* Restore the DPFPU context, if any. */ + "BEQ.B __lab2 \n" \ + "DPOPM.L DPSW-DECNT \n" \ + "DPOPM.D DR0-DR15 \n" \ + "__lab2: \n" \ + + #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 ) + /* Restore the DPFPU context, always. */ + "DPOPM.L DPSW-DECNT \n" \ + "DPOPM.D DR0-DR15 \n" \ + + #endif /* if( configUSE_TASK_DPFPU_SUPPORT == 1 ) */ + + "POP R15 \n" \ + + /* Accumulator low 32 bits. */ + "MVTACLO R15, A0 \n" \ + "POP R15 \n" \ + + /* Accumulator high 32 bits. */ + "MVTACHI R15, A0 \n" \ + "POP R15 \n" \ + + /* Accumulator guard. */ + "MVTACGU R15, A0 \n" \ + "POP R15 \n" \ + + /* Accumulator low 32 bits. */ + "MVTACLO R15, A1 \n" \ + "POP R15 \n" \ + + /* Accumulator high 32 bits. */ + "MVTACHI R15, A1 \n" \ + "POP R15 \n" \ + + /* Accumulator guard. */ + "MVTACGU R15, A1 \n" \ + "POP R15 \n" \ + "MVTC R15, FPSW \n" \ + "POPM R1-R15 \n" \ + "RTE \n" \ + "NOP \n" \ + "NOP " + portCDT_NO_PARSE( ::) "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ), "i" ( configKERNEL_INTERRUPT_PRIORITY ) + ); +} +/*-----------------------------------------------------------*/ + +#pragma vector = _VECT( configTICK_VECTOR ) +__interrupt void vTickISR( void ) +{ + /* Re-enable interrupts. */ + __enable_interrupt(); + + /* Increment the tick, and perform any processing the new tick value + * necessitates. Ensure IPL is at the max syscall value first. */ + __set_interrupt_level( configMAX_SYSCALL_INTERRUPT_PRIORITY ); + { + if( xTaskIncrementTick() != pdFALSE ) + { + taskYIELD(); + } + } + __set_interrupt_level( configKERNEL_INTERRUPT_PRIORITY ); +} +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/RX700v3_DPFPU/portmacro.h b/portable/IAR/RX700v3_DPFPU/portmacro.h new file mode 100644 index 000000000..e24cbfe53 --- /dev/null +++ b/portable/IAR/RX700v3_DPFPU/portmacro.h @@ -0,0 +1,203 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* Hardware specifics. */ +#include + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* When the FIT configurator or the Smart Configurator is used, platform.h has to be + * used. */ +#ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H + #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0 +#endif + +/* If configUSE_TASK_DPFPU_SUPPORT is set to 1 (or undefined) then each task will + * be created without a DPFPU context, and a task must call vTaskUsesDPFPU() before + * making use of any DPFPU registers. If configUSE_TASK_DPFPU_SUPPORT is set to 2 then + * tasks are created with a DPFPU context by default, and calling vTaskUsesDPFPU() has + * no effect. If configUSE_TASK_DPFPU_SUPPORT is set to 0 then tasks never take care + * of any DPFPU context (even if DPFPU registers are used). */ +#ifndef configUSE_TASK_DPFPU_SUPPORT + #define configUSE_TASK_DPFPU_SUPPORT 1 +#endif + +/*-----------------------------------------------------------*/ + +/* Type definitions - these are a bit legacy and not really used now, other than + * portSTACK_TYPE and portBASE_TYPE. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif + +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() __no_operation() + +/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;" + * where portITU_SWINTR is the location of the software interrupt register + * (0x000872E0). Don't rely on the assembler to select a register, so instead + * save and restore clobbered registers manually. */ +#define portYIELD() \ + __asm volatile \ + ( \ + "PUSH.L R10 \n" \ + "MOV.L #0x872E0, R10 \n" \ + "MOV.B #0x1, [R10] \n" \ + "CMP [R10].UB, R10 \n" \ + "POP R10 \n" \ + portCDT_NO_PARSE( ::: ) "cc" \ + ) + +#define portYIELD_FROM_ISR( x ) do { if( ( x ) != pdFALSE ) portYIELD( ); } while( 0 ) + +/* Workaround to reduce errors/warnings caused by e2 studio CDT's INDEXER and CODAN. */ +#ifdef __CDT_PARSER__ + #ifndef __asm + #define __asm asm + #endif + #ifndef __attribute__ + #define __attribute__( ... ) + #endif + #define portCDT_NO_PARSE( token ) +#else + #define portCDT_NO_PARSE( token ) token +#endif + +/* These macros should not be called directly, but through the + * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is + * performed if configASSERT() is defined to ensure an assertion handler does not + * inadvertently attempt to lower the IPL when the call to assert was triggered + * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY + * when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API + * functions are those that end in FromISR. FreeRTOS maintains a separate + * interrupt API to ensure API function and interrupt entry is as fast and as + * simple as possible. */ +#define portENABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) 0 ) +#if ( configASSERT_DEFINED == 1 ) + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) + #define portDISABLE_INTERRUPTS() if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#else + #define portDISABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#endif + +/* Critical nesting counts are stored in the TCB. */ +#define portCRITICAL_NESTING_IN_TCB ( 1 ) + +/* The critical nesting functions defined within tasks.c. */ +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() + +/* As this port allows interrupt nesting... */ +#define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_level(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) __set_interrupt_level( ( uint8_t ) ( uxSavedInterruptStatus ) ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/*-----------------------------------------------------------*/ + +/* If configUSE_TASK_DPFPU_SUPPORT is set to 1 (or left undefined) then tasks are + * created without a DPFPU context and must call vPortTaskUsesDPFPU() to give + * themselves a DPFPU context before using any DPFPU instructions. If + * configUSE_TASK_DPFPU_SUPPORT is set to 2 then all tasks will have a DPFPU context + * by default. */ +#if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) + void vPortTaskUsesDPFPU( void ); +#else + +/* Each task has a DPFPU context already, so define this function away to + * nothing to prevent it being called accidentally. */ + #define vPortTaskUsesDPFPU() +#endif +#define portTASK_USES_DPFPU() vPortTaskUsesDPFPU() + +/* Definition to allow compatibility with existing FreeRTOS Demo using flop.c. */ +#define portTASK_USES_FLOATING_POINT() vPortTaskUsesDPFPU() + +/* Prevent warnings of undefined behaviour: the order of volatile accesses is + * undefined - all warnings have been manually checked and are not an issue, and + * the warnings cannot be prevent by code changes without undesirable effects. */ +#pragma diag_suppress=Pa082 + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/IAR/RX700v3_DPFPU/readme.txt b/portable/IAR/RX700v3_DPFPU/readme.txt new file mode 100644 index 000000000..8dbc983fd --- /dev/null +++ b/portable/IAR/RX700v3_DPFPU/readme.txt @@ -0,0 +1,71 @@ +The following table shows which port is recommended to be used. + + +RX MCU Group CPU FPU FPU Port Layer + Core (Single (Double CC-RX GNURX ICCRX (*6) + Type Precision) Precision) + +RX110 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX111 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX113 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX130 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX13T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 + +RX210 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX21A RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX220 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX230,RX231 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23E-A RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23W RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24U RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 + +RX610 RXv1 Yes --- N/A (*4) N/A (*4) N/A (*4) +RX62N,RX621 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX630 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX634 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63N,RX631 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX64M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX65N,RX651 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX66N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX62T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX62G RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX66T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +RX71M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX72M RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +Notes: + +*1: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is not used, please define configSETUP_TICK_INTERRUPT() (in FreeRTOSConfig.h) and provide +the configuration function. Please be aware that port.c is hard coded to use CMT0 though it seems to be +configured to use any CMTn according to the definition of configTICK_VECTOR (in FreeRTOSConfig.h). + +*2: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is used, please modify port.c for the configuration. Please be aware that port.c is +hard coded to use CMT0 though it seems to be configured to use any CMTn according to the definition of +configTICK_VECTOR (in FreeRTOSConfig.h). + +*3: RX100 ports are also available. + +*4: RX600 ports use MVTIPL instruction but RX610 MCUs don't support this instruction. + +*5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h. + +#define configUSE_TASK_DPFPU_SUPPORT 0 + +*6: PriorityDefinitions.h has to be provided for port_asm.s in case of other than RX700v3_DPFPU port. +It contains two definitions of interrupt priority like the following. + +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + + +For more information about Renesas RX MCUs, please visit the following URL: + +https://www.renesas.com/products/microcontrollers-microprocessors/rx.html diff --git a/portable/IAR/RXv2/port.c b/portable/IAR/RXv2/port.c new file mode 100644 index 000000000..af21ae57a --- /dev/null +++ b/portable/IAR/RXv2/port.c @@ -0,0 +1,201 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the SH2A port. +*----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Library includes. */ +#include "string.h" + +/* Hardware specifics. */ +#include + +/*-----------------------------------------------------------*/ + +/* Tasks should start with interrupts enabled and in Supervisor mode, therefore + * PSW is set with U and I set, and PM and IPL clear. */ +#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) +#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 ) + +/*-----------------------------------------------------------*/ + +/* + * Function to start the first task executing - written in asm code as direct + * access to registers is required. + */ +extern void prvStartFirstTask( void ); + +/* + * The tick ISR handler. The peripheral used is configured by the application + * via a hook/callback function. + */ +__interrupt void vTickISR( void ); + +/*-----------------------------------------------------------*/ + +extern void * pxCurrentTCB; + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* R0 is not included as it is the stack pointer. */ + + *pxTopOfStack = 0x00; + pxTopOfStack--; + *pxTopOfStack = portINITIAL_PSW; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; + + /* When debugging it can be useful if every register is set to a known + * value. Otherwise code space can be saved by just setting the registers + * that need to be set. */ + #ifdef USE_FULL_REGISTER_INITIALISATION + { + pxTopOfStack--; + *pxTopOfStack = 0xffffffff; /* r15. */ + pxTopOfStack--; + *pxTopOfStack = 0xeeeeeeee; + pxTopOfStack--; + *pxTopOfStack = 0xdddddddd; + pxTopOfStack--; + *pxTopOfStack = 0xcccccccc; + pxTopOfStack--; + *pxTopOfStack = 0xbbbbbbbb; + pxTopOfStack--; + *pxTopOfStack = 0xaaaaaaaa; + pxTopOfStack--; + *pxTopOfStack = 0x99999999; + pxTopOfStack--; + *pxTopOfStack = 0x88888888; + pxTopOfStack--; + *pxTopOfStack = 0x77777777; + pxTopOfStack--; + *pxTopOfStack = 0x66666666; + pxTopOfStack--; + *pxTopOfStack = 0x55555555; + pxTopOfStack--; + *pxTopOfStack = 0x44444444; + pxTopOfStack--; + *pxTopOfStack = 0x33333333; + pxTopOfStack--; + *pxTopOfStack = 0x22222222; + pxTopOfStack--; + } + #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ + { + pxTopOfStack -= 15; + } + #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */ + + *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_FPSW; + pxTopOfStack--; + *pxTopOfStack = 0x11111111; /* Accumulator 0. */ + pxTopOfStack--; + *pxTopOfStack = 0x22222222; /* Accumulator 0. */ + pxTopOfStack--; + *pxTopOfStack = 0x33333333; /* Accumulator 0. */ + pxTopOfStack--; + *pxTopOfStack = 0x44444444; /* Accumulator 1. */ + pxTopOfStack--; + *pxTopOfStack = 0x55555555; /* Accumulator 1. */ + pxTopOfStack--; + *pxTopOfStack = 0x66666666; /* Accumulator 1. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + extern void vApplicationSetupTimerInterrupt( void ); + + /* Use pxCurrentTCB just so it does not get optimised away. */ + if( pxCurrentTCB != NULL ) + { + /* Call an application function to set up the timer that will generate the + * tick interrupt. This way the application can decide which peripheral to + * use. A demo application is provided to show a suitable example. */ + vApplicationSetupTimerInterrupt(); + + /* Enable the software interrupt. */ + _IEN( _ICU_SWINT ) = 1; + + /* Ensure the software interrupt is clear. */ + _IR( _ICU_SWINT ) = 0; + + /* Ensure the software interrupt is set to the kernel priority. */ + _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the first task. */ + prvStartFirstTask(); + } + + /* Should not get here. */ + return pdFAIL; +} +/*-----------------------------------------------------------*/ + +#pragma vector = configTICK_VECTOR +__interrupt void vTickISR( void ) +{ + /* Re-enable interrupts. */ + __enable_interrupt(); + + /* Increment the tick, and perform any processing the new tick value + * necessitates. */ + __set_interrupt_level( configMAX_SYSCALL_INTERRUPT_PRIORITY ); + { + if( xTaskIncrementTick() != pdFALSE ) + { + taskYIELD(); + } + } + __set_interrupt_level( configKERNEL_INTERRUPT_PRIORITY ); +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( pxCurrentTCB == NULL ); +} +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/RXv2/port_asm.s b/portable/IAR/RXv2/port_asm.s new file mode 100644 index 000000000..122f8a4f4 --- /dev/null +++ b/portable/IAR/RXv2/port_asm.s @@ -0,0 +1,253 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include "PriorityDefinitions.h" + + PUBLIC _prvStartFirstTask + PUBLIC ___interrupt_27 + + EXTERN _pxCurrentTCB + EXTERN _vTaskSwitchContext + + CFI Names cfiNames0 + CFI StackFrame CFA SP DATA + CFI VirtualResource ?RET:32 + CFI Resource R1:32, R2:32, R3:32, R4:32, R5:32, R6:32, R7:32, R8:32 + CFI Resource R9:32, R10:32, R11:32, R12:32, R13:32, R14:32, R15:32 + CFI Resource SP:32 + CFI EndNames cfiNames0 + + CFI Common cfiCommon0 Using cfiNames0 + CFI CodeAlign 1 + CFI DataAlign 1 + CFI ReturnAddress ?RET CODE + CFI CFA SP+4 + CFI ?RET Frame(CFA, -4) + CFI R1 Undefined + CFI R2 Undefined + CFI R3 Undefined + CFI R4 Undefined + CFI R5 Undefined + CFI R6 SameValue + CFI R7 SameValue + CFI R8 SameValue + CFI R9 SameValue + CFI R10 SameValue + CFI R11 SameValue + CFI R12 SameValue + CFI R13 SameValue + CFI R14 Undefined + CFI R15 Undefined + CFI EndCommon cfiCommon0 + + RSEG CODE:CODE(4) + +_prvStartFirstTask: + + /* When starting the scheduler there is nothing that needs moving to the + interrupt stack because the function is not called from an interrupt. + Just ensure the current stack is the user stack. */ + SETPSW U + + /* Obtain the location of the stack associated with which ever task + pxCurrentTCB is currently pointing to. */ + MOV.L #_pxCurrentTCB, R15 + MOV.L [R15], R15 + MOV.L [R15], R0 + + /* Restore the registers from the stack of the task pointed to by + pxCurrentTCB. */ + POP R15 + + /* Accumulator low 32 bits. */ + MVTACLO R15, A0 + POP R15 + + /* Accumulator high 32 bits. */ + MVTACHI R15, A0 + POP R15 + + /* Accumulator guard. */ + MVTACGU R15, A0 + POP R15 + + /* Accumulator low 32 bits. */ + MVTACLO R15, A1 + POP R15 + + /* Accumulator high 32 bits. */ + MVTACHI R15, A1 + POP R15 + + /* Accumulator guard. */ + MVTACGU R15, A1 + POP R15 + + /* Floating point status word. */ + MVTC R15, FPSW + + /* R1 to R15 - R0 is not included as it is the SP. */ + POPM R1-R15 + + /* This pops the remaining registers. */ + RTE + NOP + NOP + +/*-----------------------------------------------------------*/ + +/* The software interrupt - overwrite the default 'weak' definition. */ + CFI Block cfiBlock0 Using cfiCommon0 + CFI Function ___interrupt_27 + CODE +___interrupt_27: + + /* Re-enable interrupts. */ + SETPSW I + + /* Move the data that was automatically pushed onto the interrupt stack when + the interrupt occurred from the interrupt stack to the user stack. + + R15 is saved before it is clobbered. */ + PUSH.L R15 + + /* Read the user stack pointer. */ + MVFC USP, R15 + + /* Move the address down to the data being moved. */ + SUB #12, R15 + MVTC R15, USP + + /* Copy the data across, R15, then PC, then PSW. */ + MOV.L [ R0 ], [ R15 ] + MOV.L 4[ R0 ], 4[ R15 ] + MOV.L 8[ R0 ], 8[ R15 ] + + /* Move the interrupt stack pointer to its new correct position. */ + ADD #12, R0 + + /* All the rest of the registers are saved directly to the user stack. */ + SETPSW U + + /* Save the rest of the general registers (R15 has been saved already). */ + PUSHM R1-R14 + + /* Save the FPSW and accumulator. */ + MVFC FPSW, R15 + PUSH.L R15 + MVFACGU #0, A1, R15 + PUSH.L R15 + MVFACHI #0, A1, R15 + PUSH.L R15 + /* Low order word. */ + MVFACLO #0, A1, R15 + PUSH.L R15 + MVFACGU #0, A0, R15 + PUSH.L R15 + MVFACHI #0, A0, R15 + PUSH.L R15 + /* Low order word. */ + MVFACLO #0, A0, R15 + PUSH.L R15 + + /* Save the stack pointer to the TCB. */ + MOV.L #_pxCurrentTCB, R15 + MOV.L [ R15 ], R15 + MOV.L R0, [ R15 ] + + /* Ensure the interrupt mask is set to the syscall priority while the kernel + structures are being accessed. */ + MVTIPL #configMAX_SYSCALL_INTERRUPT_PRIORITY + + /* Select the next task to run. */ + CFI ?RET Frame(CFA, -8) + CFI R15 Frame(CFA, -12) + CFI R14 Frame(CFA, -16) + CFI R13 Frame(CFA, -20) + CFI R12 Frame(CFA, -24) + CFI R11 Frame(CFA, -28) + CFI R10 Frame(CFA, -32) + CFI R9 Frame(CFA, -36) + CFI R8 Frame(CFA, -40) + CFI R7 Frame(CFA, -44) + CFI R6 Frame(CFA, -48) + CFI R5 Frame(CFA, -52) + CFI R4 Frame(CFA, -56) + CFI R3 Frame(CFA, -60) + CFI R2 Frame(CFA, -64) + CFI R1 Frame(CFA, -68) + CFI CFA SP+96 + CFI FunCall _vTaskSwitchContext + BSR.A _vTaskSwitchContext + + /* Reset the interrupt mask as no more data structure access is required. */ + MVTIPL #configKERNEL_INTERRUPT_PRIORITY + + /* Load the stack pointer of the task that is now selected as the Running + state task from its TCB. */ + MOV.L #_pxCurrentTCB,R15 + MOV.L [ R15 ], R15 + MOV.L [ R15 ], R0 + + /* Restore the context of the new task. The PSW (Program Status Word) and + PC will be popped by the RTE instruction. */ + POP R15 + + /* Accumulator low 32 bits. */ + MVTACLO R15, A0 + POP R15 + + /* Accumulator high 32 bits. */ + MVTACHI R15, A0 + POP R15 + + /* Accumulator guard. */ + MVTACGU R15, A0 + POP R15 + + /* Accumulator low 32 bits. */ + MVTACLO R15, A1 + POP R15 + + /* Accumulator high 32 bits. */ + MVTACHI R15, A1 + POP R15 + + /* Accumulator guard. */ + MVTACGU R15, A1 + POP R15 + MVTC R15, FPSW + POPM R1-R15 + RTE + NOP + NOP + CFI EndBlock cfiBlock0 + +/*-----------------------------------------------------------*/ + + END diff --git a/portable/IAR/RXv2/portmacro.h b/portable/IAR/RXv2/portmacro.h new file mode 100644 index 000000000..792beb9df --- /dev/null +++ b/portable/IAR/RXv2/portmacro.h @@ -0,0 +1,150 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#include + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions - these are a bit legacy and not really used now, other than + * portSTACK_TYPE and portBASE_TYPE. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() __no_operation() + +/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;" + * where portITU_SWINTR is the location of the software interrupt register + * (0x000872E0). Don't rely on the assembler to select a register, so instead + * save and restore clobbered registers manually. */ +#define portYIELD() \ + __asm volatile \ + ( \ + "PUSH.L R10 \n" \ + "MOV.L #0x872E0, R10 \n" \ + "MOV.B #0x1, [R10] \n" \ + "MOV.L [R10], R10 \n" \ + "POP R10 \n" \ + ) + +#define portYIELD_FROM_ISR( x ) do { if( ( x ) != pdFALSE ) portYIELD( ); } while( 0 ) + +/* These macros should not be called directly, but through the + * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is + * performed if configASSERT() is defined to ensure an assertion handler does not + * inadvertently attempt to lower the IPL when the call to assert was triggered + * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY + * when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API + * functions are those that end in FromISR. FreeRTOS maintains a separate + * interrupt API to ensure API function and interrupt entry is as fast and as + * simple as possible. */ +#define portENABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) 0 ) +#if ( configASSERT_DEFINED == 1 ) + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) + #define portDISABLE_INTERRUPTS() if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#else + #define portDISABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#endif + +/* Critical nesting counts are stored in the TCB. */ +#define portCRITICAL_NESTING_IN_TCB ( 1 ) + +/* The critical nesting functions defined within tasks.c. */ +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() + +/* As this port allows interrupt nesting... */ +#define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_level(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) __set_interrupt_level( ( uint8_t ) ( uxSavedInterruptStatus ) ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* Prevent warnings of undefined behaviour: the order of volatile accesses is + * undefined - all warnings have been manually checked and are not an issue, and + * the warnings cannot be prevent by code changes without undesirable effects. */ +#pragma diag_suppress=Pa082 + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/IAR/RXv2/readme.txt b/portable/IAR/RXv2/readme.txt new file mode 100644 index 000000000..8dbc983fd --- /dev/null +++ b/portable/IAR/RXv2/readme.txt @@ -0,0 +1,71 @@ +The following table shows which port is recommended to be used. + + +RX MCU Group CPU FPU FPU Port Layer + Core (Single (Double CC-RX GNURX ICCRX (*6) + Type Precision) Precision) + +RX110 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX111 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX113 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX130 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX13T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 + +RX210 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX21A RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX220 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX230,RX231 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23E-A RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23W RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24U RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 + +RX610 RXv1 Yes --- N/A (*4) N/A (*4) N/A (*4) +RX62N,RX621 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX630 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX634 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63N,RX631 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX64M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX65N,RX651 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX66N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX62T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX62G RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX66T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +RX71M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX72M RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +Notes: + +*1: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is not used, please define configSETUP_TICK_INTERRUPT() (in FreeRTOSConfig.h) and provide +the configuration function. Please be aware that port.c is hard coded to use CMT0 though it seems to be +configured to use any CMTn according to the definition of configTICK_VECTOR (in FreeRTOSConfig.h). + +*2: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is used, please modify port.c for the configuration. Please be aware that port.c is +hard coded to use CMT0 though it seems to be configured to use any CMTn according to the definition of +configTICK_VECTOR (in FreeRTOSConfig.h). + +*3: RX100 ports are also available. + +*4: RX600 ports use MVTIPL instruction but RX610 MCUs don't support this instruction. + +*5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h. + +#define configUSE_TASK_DPFPU_SUPPORT 0 + +*6: PriorityDefinitions.h has to be provided for port_asm.s in case of other than RX700v3_DPFPU port. +It contains two definitions of interrupt priority like the following. + +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + + +For more information about Renesas RX MCUs, please visit the following URL: + +https://www.renesas.com/products/microcontrollers-microprocessors/rx.html diff --git a/portable/IAR/STR71x/ISR_Support.h b/portable/IAR/STR71x/ISR_Support.h new file mode 100644 index 000000000..273e95141 --- /dev/null +++ b/portable/IAR/STR71x/ISR_Support.h @@ -0,0 +1,151 @@ +; /* + * ; * FreeRTOS Kernel + * ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * ; * + * ; * SPDX-License-Identifier: MIT + * ; * + * ; * Permission is hereby granted, free of charge, to any person obtaining a copy of + * ; * this software and associated documentation files (the "Software"), to deal in + * ; * the Software without restriction, including without limitation the rights to + * ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * ; * the Software, and to permit persons to whom the Software is furnished to do so, + * ; * subject to the following conditions: + * ; * + * ; * The above copyright notice and this permission notice shall be included in all + * ; * copies or substantial portions of the Software. + * ; * + * ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * ; * + * ; * https://www.FreeRTOS.org + * ; * https://github.com/FreeRTOS + * ; * + * ; */ + +EXTERN pxCurrentTCB +EXTERN ulCriticalNesting + +; +Context save and restore macro definitions +; + +portSAVE_CONTEXT MACRO + +; +Push R0 as we are going to use the register. + STMDB SP !, { + R0 +} + +Set R0 to point to the task stack pointer. + STMDB SP, { + SP +} +^ +NOP +SUB SP, SP, # 4 +LDMIA SP !, { + R0 +} + +; +Push the return address onto the stack. + STMDB R0 !, { + LR + } + + Now we have saved LR we can use it instead of R0. + MOV LR, R0 + +; + +Pop R0 so we can save it onto the system mode stack. + LDMIA SP !, { + R0 +} + +Push all the system mode registers onto the task stack. + STMDB LR, { + R0 - LR +} +^ +NOP +SUB LR, LR, # 60 + +; +Push the SPSR onto the task stack. + MRS R0, SPSR +STMDB LR !, { + R0 +} + +LDR R0, = ulCriticalNesting + LDR R0, [ R0 ] +STMDB LR !, { + R0 +} + +Store the new top of stack + +for the task. + LDR R1, = pxCurrentTCB + LDR R0, [ R1 ] +STR LR, [ R0 ] + +ENDM + + +portRESTORE_CONTEXT MACRO + +; +Set the LR to the task stack. + LDR R1, = pxCurrentTCB + LDR R0, [ R1 ] +LDR LR, [ R0 ] + +; +The critical nesting depth is the first item on the stack. + ; +Load it into the ulCriticalNesting variable. + LDR R0, = ulCriticalNesting + LDMFD LR !, { + R1 +} + +STR R1, [ R0 ] + +; +Get the SPSR from the stack. + LDMFD LR !, { + R0 +} +MSR SPSR_cxsf, R0 + +; +Restore all system mode registers + +for the task. + LDMFD LR, { + R0 - R14 +} + +^ +NOP + +; +Restore the return address. + LDR LR, [ LR, # + 60 ] + +; + +And return -correcting the offset in the LR to obtain the +; + +correct address. + SUBS PC, LR, # 4 + +ENDM diff --git a/portable/IAR/STR71x/port.c b/portable/IAR/STR71x/port.c new file mode 100644 index 000000000..8f0e78c0d --- /dev/null +++ b/portable/IAR/STR71x/port.c @@ -0,0 +1,255 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ST STR71x ARM7 +* port. +*----------------------------------------------------------*/ + +/* Library includes. */ +#include "wdg.h" +#include "eic.h" + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to setup the initial stack. */ +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + +#define portMICROS_PER_SECOND 1000000 + +/*-----------------------------------------------------------*/ + +/* Setup the watchdog to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* ulCriticalNesting will get set to zero when the first task starts. It + * cannot be initialised to 0 as this will cause interrupts to be enabled + * during the kernel initialisation process. */ +uint32_t ulCriticalNesting = ( uint32_t ) 9999; + +/* Tick interrupt routines for cooperative and preemptive operation + * respectively. The preemptive version is not defined as __irq as it is called + * from an asm wrapper function. */ +__arm __irq void vPortNonPreemptiveTick( void ); +void vPortPreemptiveTick( void ); + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + StackType_t * pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + /* To ensure asserts in tasks.c don't fail, although in this case the assert + * is not really required. */ + pxTopOfStack--; + + /* Setup the initial stack of the task. The stack is set exactly as + * expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which in this case is the + * start of the task. The offset is added to make the return address appear + * as it would within an IRQ ISR. */ + *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + * R0. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The status register is set for system mode, with interrupts enabled. */ + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + + if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00UL ) + { + /* We want the task to start in thumb mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + + pxTopOfStack--; + + /* Interrupt flags cannot always be stored on the stack and will + * instead be stored in a variable, which is then saved as part of the + * tasks context. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + extern void vPortStartFirstTask( void ); + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + * is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +/* The cooperative scheduler requires a normal IRQ service routine to + * simply increment the system tick. */ +__arm __irq void vPortNonPreemptiveTick( void ) +{ + /* Increment the tick count - which may wake some tasks but as the + * preemptive scheduler is not being used any woken task is not given + * processor time no matter what its priority. */ + xTaskIncrementTick(); + + /* Clear the interrupt in the watchdog and EIC. */ + WDG->SR = 0x0000; + portCLEAR_EIC(); +} +/*-----------------------------------------------------------*/ + +/* This function is called from an asm wrapper, so does not require the __irq + * keyword. */ +void vPortPreemptiveTick( void ) +{ + /* Increment the tick counter. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Select a new task to execute. */ + vTaskSwitchContext(); + } + + /* Clear the interrupt in the watchdog and EIC. */ + WDG->SR = 0x0000; + portCLEAR_EIC(); +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ + /* Set the watchdog up to generate a periodic tick. */ + WDG_ECITConfig( DISABLE ); + WDG_CntOnOffConfig( DISABLE ); + WDG_PeriodValueConfig( portMICROS_PER_SECOND / configTICK_RATE_HZ ); + + /* Setup the tick interrupt in the EIC. */ + EIC_IRQChannelPriorityConfig( WDG_IRQChannel, 1 ); + EIC_IRQChannelConfig( WDG_IRQChannel, ENABLE ); + EIC_IRQConfig( ENABLE ); + WDG_ECITConfig( ENABLE ); + + /* Start the timer - interrupts are actually disabled at this point so + * it is safe to do this here. */ + WDG_CntOnOffConfig( ENABLE ); +} +/*-----------------------------------------------------------*/ + +__arm __interwork void vPortEnterCritical( void ) +{ + /* Disable interrupts first! */ + __disable_interrupt(); + + /* Now that interrupts are disabled, ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +__arm __interwork void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + * re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + __enable_interrupt(); + } + } +} +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/STR71x/portasm.s79 b/portable/IAR/STR71x/portasm.s79 new file mode 100644 index 000000000..87166f691 --- /dev/null +++ b/portable/IAR/STR71x/portasm.s79 @@ -0,0 +1,76 @@ +;/* +; * FreeRTOS Kernel +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + + RSEG ICODE:CODE + CODE32 + + EXTERN vPortPreemptiveTick + EXTERN vTaskSwitchContext + + PUBLIC vPortYieldProcessor + PUBLIC vPortStartFirstTask + PUBLIC vPortPreemptiveTickISR + +#include "ISR_Support.h" + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Starting the first task is just a matter of restoring the context that +; was created by pxPortInitialiseStack(). +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortStartFirstTask: + portRESTORE_CONTEXT + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Manual context switch function. This is the SWI hander. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortYieldProcessor: + ADD LR, LR, #4 ; Add 4 to the LR to make the LR appear exactly + ; as if the context was saved during and IRQ + ; handler. + + portSAVE_CONTEXT ; Save the context of the current task... + LDR R0, =vTaskSwitchContext ; before selecting the next task to execute. + mov lr, pc + BX R0 + portRESTORE_CONTEXT ; Restore the context of the selected task. + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Preemptive context switch function. This will only ever get used if +; portUSE_PREEMPTION is set to 1 in portmacro.h. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortPreemptiveTickISR: + portSAVE_CONTEXT ; Save the context of the current task. + + LDR R0, =vPortPreemptiveTick ; Increment the tick count - this may wake a task. + MOV lr, pc + BX R0 + + portRESTORE_CONTEXT ; Restore the context of the selected task. + + + END diff --git a/portable/IAR/STR71x/portmacro.h b/portable/IAR/STR71x/portmacro.h new file mode 100644 index 000000000..e05c380ab --- /dev/null +++ b/portable/IAR/STR71x/portmacro.h @@ -0,0 +1,131 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +#include + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portYIELD() asm ( "SWI 0" ) +#define portNOP() asm ( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +__arm __interwork void vPortDisableInterruptsFromThumb( void ); +__arm __interwork void vPortEnableInterruptsFromThumb( void ); +__arm __interwork void vPortEnterCritical( void ); +__arm __interwork void vPortExitCritical( void ); + +#define portDISABLE_INTERRUPTS() __disable_interrupt() +#define portENABLE_INTERRUPTS() __enable_interrupt() +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + { \ + extern void vTaskSwitchContext( void ); \ + \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + vTaskSwitchContext(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } +/*-----------------------------------------------------------*/ + +/* EIC utilities. */ +#define portEIC_CICR_ADDR *( ( uint32_t * ) 0xFFFFF804 ) +#define portEIC_IPR_ADDR *( ( uint32_t * ) 0xFFFFF840 ) +#define portCLEAR_EIC() portEIC_IPR_ADDR = 0x01 << portEIC_CICR_ADDR + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/IAR/STR75x/ISR_Support.h b/portable/IAR/STR75x/ISR_Support.h new file mode 100644 index 000000000..273e95141 --- /dev/null +++ b/portable/IAR/STR75x/ISR_Support.h @@ -0,0 +1,151 @@ +; /* + * ; * FreeRTOS Kernel + * ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * ; * + * ; * SPDX-License-Identifier: MIT + * ; * + * ; * Permission is hereby granted, free of charge, to any person obtaining a copy of + * ; * this software and associated documentation files (the "Software"), to deal in + * ; * the Software without restriction, including without limitation the rights to + * ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * ; * the Software, and to permit persons to whom the Software is furnished to do so, + * ; * subject to the following conditions: + * ; * + * ; * The above copyright notice and this permission notice shall be included in all + * ; * copies or substantial portions of the Software. + * ; * + * ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * ; * + * ; * https://www.FreeRTOS.org + * ; * https://github.com/FreeRTOS + * ; * + * ; */ + +EXTERN pxCurrentTCB +EXTERN ulCriticalNesting + +; +Context save and restore macro definitions +; + +portSAVE_CONTEXT MACRO + +; +Push R0 as we are going to use the register. + STMDB SP !, { + R0 +} + +Set R0 to point to the task stack pointer. + STMDB SP, { + SP +} +^ +NOP +SUB SP, SP, # 4 +LDMIA SP !, { + R0 +} + +; +Push the return address onto the stack. + STMDB R0 !, { + LR + } + + Now we have saved LR we can use it instead of R0. + MOV LR, R0 + +; + +Pop R0 so we can save it onto the system mode stack. + LDMIA SP !, { + R0 +} + +Push all the system mode registers onto the task stack. + STMDB LR, { + R0 - LR +} +^ +NOP +SUB LR, LR, # 60 + +; +Push the SPSR onto the task stack. + MRS R0, SPSR +STMDB LR !, { + R0 +} + +LDR R0, = ulCriticalNesting + LDR R0, [ R0 ] +STMDB LR !, { + R0 +} + +Store the new top of stack + +for the task. + LDR R1, = pxCurrentTCB + LDR R0, [ R1 ] +STR LR, [ R0 ] + +ENDM + + +portRESTORE_CONTEXT MACRO + +; +Set the LR to the task stack. + LDR R1, = pxCurrentTCB + LDR R0, [ R1 ] +LDR LR, [ R0 ] + +; +The critical nesting depth is the first item on the stack. + ; +Load it into the ulCriticalNesting variable. + LDR R0, = ulCriticalNesting + LDMFD LR !, { + R1 +} + +STR R1, [ R0 ] + +; +Get the SPSR from the stack. + LDMFD LR !, { + R0 +} +MSR SPSR_cxsf, R0 + +; +Restore all system mode registers + +for the task. + LDMFD LR, { + R0 - R14 +} + +^ +NOP + +; +Restore the return address. + LDR LR, [ LR, # + 60 ] + +; + +And return -correcting the offset in the LR to obtain the +; + +correct address. + SUBS PC, LR, # 4 + +ENDM diff --git a/portable/IAR/STR75x/port.c b/portable/IAR/STR75x/port.c new file mode 100644 index 000000000..b4ec381a5 --- /dev/null +++ b/portable/IAR/STR75x/port.c @@ -0,0 +1,234 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ST STR75x ARM7 +* port. +*----------------------------------------------------------*/ + +/* Library includes. */ +#include "75x_tb.h" +#include "75x_eic.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to setup the initial stack. */ +#define portINITIAL_SPSR ( ( StackType_t ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */ +#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + +/* Prescale used on the timer clock when calculating the tick period. */ +#define portPRESCALE 20 + + +/*-----------------------------------------------------------*/ + +/* Setup the TB to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* ulCriticalNesting will get set to zero when the first task starts. It + * cannot be initialised to 0 as this will cause interrupts to be enabled + * during the kernel initialisation process. */ +uint32_t ulCriticalNesting = ( uint32_t ) 9999; + +/* Tick interrupt routines for preemptive operation. */ +__arm void vPortPreemptiveTick( void ); + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + StackType_t * pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + /* To ensure asserts in tasks.c don't fail, although in this case the assert + * is not really required. */ + pxTopOfStack--; + + /* Setup the initial stack of the task. The stack is set exactly as + * expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which in this case is the + * start of the task. The offset is added to make the return address appear + * as it would within an IRQ ISR. */ + *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + * R0. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The status register is set for system mode, with interrupts enabled. */ + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + pxTopOfStack--; + + /* Interrupt flags cannot always be stored on the stack and will + * instead be stored in a variable, which is then saved as part of the + * tasks context. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + extern void vPortStartFirstTask( void ); + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + * is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +__arm void vPortPreemptiveTick( void ) +{ + /* Increment the tick counter. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Select a new task to execute. */ + vTaskSwitchContext(); + } + + TB_ClearITPendingBit( TB_IT_Update ); +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ + EIC_IRQInitTypeDef EIC_IRQInitStructure; + TB_InitTypeDef TB_InitStructure; + + /* Setup the EIC for the TB. */ + EIC_IRQInitStructure.EIC_IRQChannelCmd = ENABLE; + EIC_IRQInitStructure.EIC_IRQChannel = TB_IRQChannel; + EIC_IRQInitStructure.EIC_IRQChannelPriority = 1; + EIC_IRQInit( &EIC_IRQInitStructure ); + + /* Setup the TB for the generation of the tick interrupt. */ + TB_InitStructure.TB_Mode = TB_Mode_Timing; + TB_InitStructure.TB_CounterMode = TB_CounterMode_Down; + TB_InitStructure.TB_Prescaler = portPRESCALE - 1; + TB_InitStructure.TB_AutoReload = ( ( configCPU_CLOCK_HZ / portPRESCALE ) / configTICK_RATE_HZ ); + TB_Init( &TB_InitStructure ); + + /* Enable TB Update interrupt */ + TB_ITConfig( TB_IT_Update, ENABLE ); + + /* Clear TB Update interrupt pending bit */ + TB_ClearITPendingBit( TB_IT_Update ); + + /* Enable TB */ + TB_Cmd( ENABLE ); +} +/*-----------------------------------------------------------*/ + +__arm __interwork void vPortEnterCritical( void ) +{ + /* Disable interrupts first! */ + __disable_interrupt(); + + /* Now that interrupts are disabled, ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +__arm __interwork void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + * re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + __enable_interrupt(); + } + } +} +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/STR75x/portasm.s79 b/portable/IAR/STR75x/portasm.s79 new file mode 100644 index 000000000..ad2aa1b5e --- /dev/null +++ b/portable/IAR/STR75x/portasm.s79 @@ -0,0 +1,63 @@ +;/* +; * FreeRTOS Kernel +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + + RSEG ICODE:CODE + CODE32 + + EXTERN vPortPreemptiveTick + EXTERN vTaskSwitchContext + + PUBLIC vPortYieldProcessor + PUBLIC vPortStartFirstTask + +#include "ISR_Support.h" + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Starting the first task is just a matter of restoring the context that +; was created by pxPortInitialiseStack(). +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortStartFirstTask: + portRESTORE_CONTEXT + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Manual context switch function. This is the SWI hander. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortYieldProcessor: + ADD LR, LR, #4 ; Add 4 to the LR to make the LR appear exactly + ; as if the context was saved during and IRQ + ; handler. + + portSAVE_CONTEXT ; Save the context of the current task... + LDR R0, =vTaskSwitchContext ; before selecting the next task to execute. + mov lr, pc + BX R0 + portRESTORE_CONTEXT ; Restore the context of the selected task. + + + + END diff --git a/portable/IAR/STR75x/portmacro.h b/portable/IAR/STR75x/portmacro.h new file mode 100644 index 000000000..1d5cdabbe --- /dev/null +++ b/portable/IAR/STR75x/portmacro.h @@ -0,0 +1,122 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +#include + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portYIELD() asm ( "SWI 0" ) +#define portNOP() asm ( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +__arm __interwork void vPortEnterCritical( void ); +__arm __interwork void vPortExitCritical( void ); + +#define portDISABLE_INTERRUPTS() __disable_interrupt() +#define portENABLE_INTERRUPTS() __enable_interrupt() +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + { \ + extern void vTaskSwitchContext( void ); \ + \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + vTaskSwitchContext(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } +/*-----------------------------------------------------------*/ + + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/IAR/STR91x/ISR_Support.h b/portable/IAR/STR91x/ISR_Support.h new file mode 100644 index 000000000..2e6973757 --- /dev/null +++ b/portable/IAR/STR91x/ISR_Support.h @@ -0,0 +1,151 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +EXTERN pxCurrentTCB +EXTERN ulCriticalNesting + +; +Context save and restore macro definitions +; + +portSAVE_CONTEXT MACRO + +; +Push R0 as we are going to use the register. + STMDB SP !, { + R0 +} + +Set R0 to point to the task stack pointer. + STMDB SP, { + SP +} +^ +NOP +SUB SP, SP, # 4 +LDMIA SP !, { + R0 +} + +; +Push the return address onto the stack. + STMDB R0 !, { + LR + } + + Now we have saved LR we can use it instead of R0. + MOV LR, R0 + +; + +Pop R0 so we can save it onto the system mode stack. + LDMIA SP !, { + R0 +} + +Push all the system mode registers onto the task stack. + STMDB LR, { + R0 - LR +} +^ +NOP +SUB LR, LR, # 60 + +; +Push the SPSR onto the task stack. + MRS R0, SPSR +STMDB LR !, { + R0 +} + +LDR R0, = ulCriticalNesting + LDR R0, [ R0 ] +STMDB LR !, { + R0 +} + +Store the new top of stack + +for the task. + LDR R1, = pxCurrentTCB + LDR R0, [ R1 ] +STR LR, [ R0 ] + +ENDM + + +portRESTORE_CONTEXT MACRO + +; +Set the LR to the task stack. + LDR R1, = pxCurrentTCB + LDR R0, [ R1 ] +LDR LR, [ R0 ] + +; +The critical nesting depth is the first item on the stack. + ; +Load it into the ulCriticalNesting variable. + LDR R0, = ulCriticalNesting + LDMFD LR !, { + R1 +} + +STR R1, [ R0 ] + +; +Get the SPSR from the stack. + LDMFD LR !, { + R0 +} +MSR SPSR_cxsf, R0 + +; +Restore all system mode registers + +for the task. + LDMFD LR, { + R0 - R14 +} + +^ +NOP + +; +Restore the return address. + LDR LR, [ LR, # + 60 ] + +; + +And return -correcting the offset in the LR to obtain the +; + +correct address. + SUBS PC, LR, # 4 + +ENDM diff --git a/portable/IAR/STR91x/port.c b/portable/IAR/STR91x/port.c new file mode 100644 index 000000000..f706c946e --- /dev/null +++ b/portable/IAR/STR91x/port.c @@ -0,0 +1,435 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ST STR91x ARM9 +* port. +*----------------------------------------------------------*/ + +/* Library includes. */ +#include "91x_lib.h" + +/* Standard includes. */ +#include +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#ifndef configUSE_WATCHDOG_TICK + #error configUSE_WATCHDOG_TICK must be set to either 1 or 0 in FreeRTOSConfig.h to use either the Watchdog or timer 2 to generate the tick interrupt respectively. +#endif + +/* Constants required to setup the initial stack. */ +#ifndef _RUN_TASK_IN_ARM_MODE_ + #define portINITIAL_SPSR ( ( StackType_t ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */ +#else + #define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#endif + +#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + +#ifndef abs + #define abs( x ) ( ( x ) > 0 ? ( x ) : -( x ) ) +#endif + +/** + * Toggle a led using the following algorithm: + * if ( GPIO_ReadBit(GPIO9, GPIO_Pin_2) ) + * { + * GPIO_WriteBit( GPIO9, GPIO_Pin_2, Bit_RESET ); + * } + * else + * { + * GPIO_WriteBit( GPIO9, GPIO_Pin_2, Bit_RESET ); + * } + * + */ +#define TOGGLE_LED( port, pin ) \ + if( ( ( ( ( port )->DR[ ( pin ) << 2 ] ) ) & ( pin ) ) != Bit_RESET ) \ + { \ + ( port )->DR[ ( pin ) << 2 ] = 0x00; \ + } \ + else \ + { \ + ( port )->DR[ ( pin ) << 2 ] = ( pin ); \ + } + + +/*-----------------------------------------------------------*/ + +/* Setup the watchdog to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* ulCriticalNesting will get set to zero when the first task starts. It + * cannot be initialised to 0 as this will cause interrupts to be enabled + * during the kernel initialisation process. */ +uint32_t ulCriticalNesting = ( uint32_t ) 9999; + +/* Tick interrupt routines for cooperative and preemptive operation + * respectively. The preemptive version is not defined as __irq as it is called + * from an asm wrapper function. */ +void WDG_IRQHandler( void ); + +/* VIC interrupt default handler. */ +static void prvDefaultHandler( void ); + +#if configUSE_WATCHDOG_TICK == 0 + /* Used to update the OCR timer register */ + static u16 s_nPulseLength; +#endif + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + StackType_t * pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + /* To ensure asserts in tasks.c don't fail, although in this case the assert + * is not really required. */ + pxTopOfStack--; + + /* Setup the initial stack of the task. The stack is set exactly as + * expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which in this case is the + * start of the task. The offset is added to make the return address appear + * as it would within an IRQ ISR. */ + *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + * R0. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The status register is set for system mode, with interrupts enabled. */ + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + pxTopOfStack--; + + /* Interrupt flags cannot always be stored on the stack and will + * instead be stored in a variable, which is then saved as part of the + * tasks context. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + extern void vPortStartFirstTask( void ); + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + * is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +/* This function is called from an asm wrapper, so does not require the __irq + * keyword. */ +#if configUSE_WATCHDOG_TICK == 1 + + static void prvFindFactors( u32 n, + u16 * a, + u32 * b ) + { + /* This function is copied from the ST STR7 library and is + * copyright STMicroelectronics. Reproduced with permission. */ + + u32 b0; + u16 a0; + int32_t err, err_min = n; + + *a = a0 = ( ( n - 1 ) / 65536ul ) + 1; + *b = b0 = n / *a; + + for( ; *a <= 256; ( *a )++ ) + { + *b = n / *a; + err = ( int32_t ) *a * ( int32_t ) *b - ( int32_t ) n; + + if( abs( err ) > ( *a / 2 ) ) + { + ( *b )++; + err = ( int32_t ) *a * ( int32_t ) *b - ( int32_t ) n; + } + + if( abs( err ) < abs( err_min ) ) + { + err_min = err; + a0 = *a; + b0 = *b; + + if( err == 0 ) + { + break; + } + } + } + + *a = a0; + *b = b0; + } + /*-----------------------------------------------------------*/ + + static void prvSetupTimerInterrupt( void ) + { + WDG_InitTypeDef xWdg; + uint16_t a; + uint32_t n = configCPU_PERIPH_HZ / configTICK_RATE_HZ, b; + + /* Configure the watchdog as a free running timer that generates a + * periodic interrupt. */ + + SCU_APBPeriphClockConfig( __WDG, ENABLE ); + WDG_DeInit(); + WDG_StructInit( &xWdg ); + prvFindFactors( n, &a, &b ); + xWdg.WDG_Prescaler = a - 1; + xWdg.WDG_Preload = b - 1; + WDG_Init( &xWdg ); + WDG_ITConfig( ENABLE ); + + /* Configure the VIC for the WDG interrupt. */ + VIC_Config( WDG_ITLine, VIC_IRQ, 10 ); + VIC_ITCmd( WDG_ITLine, ENABLE ); + + /* Install the default handlers for both VIC's. */ + VIC0->DVAR = ( uint32_t ) prvDefaultHandler; + VIC1->DVAR = ( uint32_t ) prvDefaultHandler; + + WDG_Cmd( ENABLE ); + } + /*-----------------------------------------------------------*/ + + void WDG_IRQHandler( void ) + { + { + /* Increment the tick counter. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Select a new task to execute. */ + vTaskSwitchContext(); + } + + /* Clear the interrupt in the watchdog. */ + WDG->SR &= ~0x0001; + } + } + +#else /* if configUSE_WATCHDOG_TICK == 1 */ + + static void prvFindFactors( u32 n, + u8 * a, + u16 * b ) + { + /* This function is copied from the ST STR7 library and is + * copyright STMicroelectronics. Reproduced with permission. */ + + u16 b0; + u8 a0; + int32_t err, err_min = n; + + + *a = a0 = ( ( n - 1 ) / 256 ) + 1; + *b = b0 = n / *a; + + for( ; *a <= 256; ( *a )++ ) + { + *b = n / *a; + err = ( int32_t ) *a * ( int32_t ) *b - ( int32_t ) n; + + if( abs( err ) > ( *a / 2 ) ) + { + ( *b )++; + err = ( int32_t ) *a * ( int32_t ) *b - ( int32_t ) n; + } + + if( abs( err ) < abs( err_min ) ) + { + err_min = err; + a0 = *a; + b0 = *b; + + if( err == 0 ) + { + break; + } + } + } + + *a = a0; + *b = b0; + } + /*-----------------------------------------------------------*/ + + static void prvSetupTimerInterrupt( void ) + { + uint8_t a; + uint16_t b; + uint32_t n = configCPU_PERIPH_HZ / configTICK_RATE_HZ; + + TIM_InitTypeDef timer; + + SCU_APBPeriphClockConfig( __TIM23, ENABLE ); + TIM_DeInit( TIM2 ); + TIM_StructInit( &timer ); + prvFindFactors( n, &a, &b ); + + timer.TIM_Mode = TIM_OCM_CHANNEL_1; + timer.TIM_OC1_Modes = TIM_TIMING; + timer.TIM_Clock_Source = TIM_CLK_APB; + timer.TIM_Clock_Edge = TIM_CLK_EDGE_RISING; + timer.TIM_Prescaler = a - 1; + timer.TIM_Pulse_Level_1 = TIM_HIGH; + timer.TIM_Pulse_Length_1 = s_nPulseLength = b - 1; + + TIM_Init( TIM2, &timer ); + TIM_ITConfig( TIM2, TIM_IT_OC1, ENABLE ); + /* Configure the VIC for the WDG interrupt. */ + VIC_Config( TIM2_ITLine, VIC_IRQ, 10 ); + VIC_ITCmd( TIM2_ITLine, ENABLE ); + + /* Install the default handlers for both VIC's. */ + VIC0->DVAR = ( uint32_t ) prvDefaultHandler; + VIC1->DVAR = ( uint32_t ) prvDefaultHandler; + + TIM_CounterCmd( TIM2, TIM_CLEAR ); + TIM_CounterCmd( TIM2, TIM_START ); + } + /*-----------------------------------------------------------*/ + + void TIM2_IRQHandler( void ) + { + /* Reset the timer counter to avoid overflow. */ + TIM2->OC1R += s_nPulseLength; + + /* Increment the tick counter. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Select a new task to run. */ + vTaskSwitchContext(); + } + + /* Clear the interrupt in the watchdog. */ + TIM2->SR &= ~TIM_FLAG_OC1; + } + +#endif /* USE_WATCHDOG_TICK */ + +/*-----------------------------------------------------------*/ + +__arm __interwork void vPortEnterCritical( void ) +{ + /* Disable interrupts first! */ + portDISABLE_INTERRUPTS(); + + /* Now that interrupts are disabled, ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +__arm __interwork void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + * re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + portENABLE_INTERRUPTS(); + } + } +} +/*-----------------------------------------------------------*/ + +static void prvDefaultHandler( void ) +{ +} diff --git a/portable/IAR/STR91x/portasm.s79 b/portable/IAR/STR91x/portasm.s79 new file mode 100644 index 000000000..9b91475c7 --- /dev/null +++ b/portable/IAR/STR91x/portasm.s79 @@ -0,0 +1,60 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + RSEG ICODE:CODE + CODE32 + + EXTERN vTaskSwitchContext + + PUBLIC vPortYieldProcessor + PUBLIC vPortStartFirstTask + +#include "ISR_Support.h" + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Starting the first task is just a matter of restoring the context that +; was created by pxPortInitialiseStack(). +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortStartFirstTask: + portRESTORE_CONTEXT + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Manual context switch function. This is the SWI hander. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortYieldProcessor: + ADD LR, LR, #4 ; Add 4 to the LR to make the LR appear exactly + ; as if the context was saved during and IRQ + ; handler. + + portSAVE_CONTEXT ; Save the context of the current task... + LDR R0, =vTaskSwitchContext ; before selecting the next task to execute. + MOV lr, pc + BX R0 + portRESTORE_CONTEXT ; Restore the context of the selected task. + + END diff --git a/portable/IAR/STR91x/portmacro.h b/portable/IAR/STR91x/portmacro.h new file mode 100644 index 000000000..fde5b6dcb --- /dev/null +++ b/portable/IAR/STR91x/portmacro.h @@ -0,0 +1,124 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +#include + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portYIELD() asm ( "SWI 0" ) +#define portNOP() asm ( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +__arm __interwork void vPortEnterCritical( void ); +__arm __interwork void vPortExitCritical( void ); +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() + +#define portDISABLE_INTERRUPTS() __disable_interrupt() +#define portENABLE_INTERRUPTS() __enable_interrupt() + + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + { \ + extern void vTaskSwitchContext( void ); \ + \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + vTaskSwitchContext(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } +/*-----------------------------------------------------------*/ + + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/IAR/V850ES/ISR_Support.h b/portable/IAR/V850ES/ISR_Support.h new file mode 100644 index 000000000..b99126d0f --- /dev/null +++ b/portable/IAR/V850ES/ISR_Support.h @@ -0,0 +1,175 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +EXTERN pxCurrentTCB +EXTERN usCriticalNesting + +#include "FreeRTOSConfig.h" + +; +Context save and restore macro definitions +; + +portSAVE_CONTEXT MACRO + + add - 0x0C, sp; +prepare stack to save necessary values +st.w lp, 8[ sp ]; +store LP to stack + stsr 0, r31 + st.w lp, 4[ sp ]; +store EIPC to stack + stsr 1, lp + st.w lp, 0[ sp ]; +store EIPSW to stack +#if configDATA_MODE == 1; Using the Tiny data model +prepare { + r20, r21, r22, r23, r24, r25, r26, r27, r28, r29, r30 +}, 76, sp; +save general purpose registers +sst.w r19, 72[ ep ] +sst.w r18, 68[ ep ] +sst.w r17, 64[ ep ] +sst.w r16, 60[ ep ] +sst.w r15, 56[ ep ] +sst.w r14, 52[ ep ] +sst.w r13, 48[ ep ] +sst.w r12, 44[ ep ] +sst.w r11, 40[ ep ] +sst.w r10, 36[ ep ] +sst.w r9, 32[ ep ] +sst.w r8, 28[ ep ] +sst.w r7, 24[ ep ] +sst.w r6, 20[ ep ] +sst.w r5, 16[ ep ] +sst.w r4, 12[ ep ] +#else; Using the Small / Large data model +prepare { + r20, r21, r22, r23, r24, r26, r27, r28, r29, r30 +}, 72, sp; +save general purpose registers +sst.w r19, 68[ ep ] +sst.w r18, 64[ ep ] +sst.w r17, 60[ ep ] +sst.w r16, 56[ ep ] +sst.w r15, 52[ ep ] +sst.w r14, 48[ ep ] +sst.w r13, 44[ ep ] +sst.w r12, 40[ ep ] +sst.w r11, 36[ ep ] +sst.w r10, 32[ ep ] +sst.w r9, 28[ ep ] +sst.w r8, 24[ ep ] +sst.w r7, 20[ ep ] +sst.w r6, 16[ ep ] +sst.w r5, 12[ ep ] +#endif /* configDATA_MODE */ +sst.w r2, 8[ ep ] +sst.w r1, 4[ ep ] +MOVHI hi1( usCriticalNesting ), r0, r1; +save usCriticalNesting value to stack +ld.w lw1( usCriticalNesting )[ r1 ], r2 +sst.w r2, 0[ ep ] +MOVHI hi1( pxCurrentTCB ), r0, r1; +save SP to top of current TCB +ld.w lw1( pxCurrentTCB )[ r1 ], r2 +st.w sp, 0[ r2 ] +ENDM + + +portRESTORE_CONTEXT MACRO + +MOVHI hi1( pxCurrentTCB ), r0, r1; +get Stackpointer address +ld.w lw1( pxCurrentTCB )[ r1 ], sp +MOV sp, r1 +ld.w 0[ r1 ], sp; +load stackpointer +MOV sp, ep; +set stack pointer to element pointer +sld.w 0[ ep ], r1; +load usCriticalNesting value from stack +MOVHI hi1( usCriticalNesting ), r0, r2 +st.w r1, lw1( usCriticalNesting )[ r2 ] +sld.w 4[ ep ], r1; +restore general purpose registers +sld.w 8[ ep ], r2 +#if configDATA_MODE == 1; Using Tiny data model + sld.w 12[ ep ], r4 + sld.w 16[ ep ], r5 + sld.w 20[ ep ], r6 + sld.w 24[ ep ], r7 + sld.w 28[ ep ], r8 + sld.w 32[ ep ], r9 + sld.w 36[ ep ], r10 + sld.w 40[ ep ], r11 + sld.w 44[ ep ], r12 + sld.w 48[ ep ], r13 + sld.w 52[ ep ], r14 + sld.w 56[ ep ], r15 + sld.w 60[ ep ], r16 + sld.w 64[ ep ], r17 + sld.w 68[ ep ], r18 + sld.w 72[ ep ], r19 + dispose 76, { + r20, r21, r22, r23, r24, r25, r26, r27, r28, r29, r30 + } +#else; Using Small / Large data model + sld.w 12[ ep ], r5 + sld.w 16[ ep ], r6 + sld.w 20[ ep ], r7 + sld.w 24[ ep ], r8 + sld.w 28[ ep ], r9 + sld.w 32[ ep ], r10 + sld.w 36[ ep ], r11 + sld.w 40[ ep ], r12 + sld.w 44[ ep ], r13 + sld.w 48[ ep ], r14 + sld.w 52[ ep ], r15 + sld.w 56[ ep ], r16 + sld.w 60[ ep ], r17 + sld.w 64[ ep ], r18 + sld.w 68[ ep ], r19 + dispose 72, { + r20, r21, r22, r23, r24, r26, r27, r28, r29, r30 + } +#endif /* configDATA_MODE */ +ld.w 0[ sp ], lp; +restore EIPSW from stack +ldsr lp, 1 +ld.w 4[ sp ], lp; +restore EIPC from stack +ldsr lp, 0 +ld.w 8[ sp ], lp; +restore LP from stack + add 0x0C, sp; +set SP to right position + +RETI + +ENDM diff --git a/portable/IAR/V850ES/port.c b/portable/IAR/V850ES/port.c new file mode 100644 index 000000000..d1d9d6a7d --- /dev/null +++ b/portable/IAR/V850ES/port.c @@ -0,0 +1,184 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Critical nesting should be initialised to a non zero value so interrupts don't + * accidentally get enabled before the scheduler is started. */ +#define portINITIAL_CRITICAL_NESTING ( ( StackType_t ) 10 ) + +/* The PSW value assigned to tasks when they start to run for the first time. */ +#define portPSW ( ( StackType_t ) 0x00000000 ) + +/* We require the address of the pxCurrentTCB variable, but don't want to know + * any details of its type. */ +typedef void TCB_t; +extern volatile TCB_t * volatile pxCurrentTCB; + +/* Keeps track of the nesting level of critical sections. */ +volatile StackType_t usCriticalNesting = portINITIAL_CRITICAL_NESTING; +/*-----------------------------------------------------------*/ + +/* Sets up the timer to generate the tick interrupt. */ +static void prvSetupTimerInterrupt( void ); + +/*-----------------------------------------------------------*/ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + *pxTopOfStack = ( StackType_t ) pxCode; /* Task function start address */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* Task function start address */ + pxTopOfStack--; + *pxTopOfStack = portPSW; /* Initial PSW value */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x20202020; /* Initial Value of R20 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x21212121; /* Initial Value of R21 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x22222222; /* Initial Value of R22 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x23232323; /* Initial Value of R23 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x24242424; /* Initial Value of R24 */ + pxTopOfStack--; + #if ( __DATA_MODEL__ == 0 ) || ( __DATA_MODEL__ == 1 ) + *pxTopOfStack = ( StackType_t ) 0x25252525; /* Initial Value of R25 */ + pxTopOfStack--; + #endif /* configDATA_MODE */ + *pxTopOfStack = ( StackType_t ) 0x26262626; /* Initial Value of R26 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x27272727; /* Initial Value of R27 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x28282828; /* Initial Value of R28 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x29292929; /* Initial Value of R29 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x30303030; /* Initial Value of R30 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x19191919; /* Initial Value of R19 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x18181818; /* Initial Value of R18 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x17171717; /* Initial Value of R17 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x16161616; /* Initial Value of R16 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x15151515; /* Initial Value of R15 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x14141414; /* Initial Value of R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x13131313; /* Initial Value of R13 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* Initial Value of R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* Initial Value of R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* Initial Value of R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x99999999; /* Initial Value of R09 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x88888888; /* Initial Value of R08 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x77777777; /* Initial Value of R07 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x66666666; /* Initial Value of R06 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x55555555; /* Initial Value of R05 */ + pxTopOfStack--; + #if __DATA_MODEL__ == 0 || __DATA_MODEL__ == 1 + *pxTopOfStack = ( StackType_t ) 0x44444444; /* Initial Value of R04 */ + pxTopOfStack--; + #endif /* configDATA_MODE */ + *pxTopOfStack = ( StackType_t ) 0x22222222; /* Initial Value of R02 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 is expected to hold the function parameter*/ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING; + + /* + * Return a pointer to the top of the stack we have generated so this can + * be stored in the task control block for the task. + */ + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Setup the hardware to generate the tick. Interrupts are disabled when + * this function is called. */ + prvSetupTimerInterrupt(); + + /* Restore the context of the first task that is going to run. */ + vPortStart(); + + /* Should not get here as the tasks are now running! */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the V850ES/Fx3 port will get stopped. If required simply + * disable the tick interrupt here. */ +} +/*-----------------------------------------------------------*/ + +/* + * Hardware initialisation to generate the RTOS tick. This uses + */ +static void prvSetupTimerInterrupt( void ) +{ + TM0CE = 0; /* TMM0 operation disable */ + TM0EQMK0 = 1; /* INTTM0EQ0 interrupt disable */ + TM0EQIF0 = 0; /* clear INTTM0EQ0 interrupt flag */ + + #ifdef __IAR_V850ES_Fx3__ + { + TM0CMP0 = ( ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) / 2 ) - 1 ); /* divided by 2 because peripherals only run at CPU_CLOCK/2 */ + } + #else + { + TM0CMP0 = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ); + } + #endif + + TM0EQIC0 &= 0xF8; + TM0CTL0 = 0x00; + TM0EQIF0 = 0; /* clear INTTM0EQ0 interrupt flag */ + TM0EQMK0 = 0; /* INTTM0EQ0 interrupt enable */ + TM0CE = 1; /* TMM0 operation enable */ +} +/*-----------------------------------------------------------*/ diff --git a/portable/IAR/V850ES/portasm.s85 b/portable/IAR/V850ES/portasm.s85 new file mode 100644 index 000000000..b01753667 --- /dev/null +++ b/portable/IAR/V850ES/portasm.s85 @@ -0,0 +1,315 @@ +;/* +; * FreeRTOS Kernel +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ +; Note: Select the correct include files for the device used by the application. +#include "FreeRTOSConfig.h" +;------------------------------------------------------------------------------ + +; Functions used by scheduler +;------------------------------------------------------------------------------ + EXTERN vTaskSwitchContext + EXTERN xTaskIncrementTick + +; Variables used by scheduler +;------------------------------------------------------------------------------ + EXTERN pxCurrentTCB + EXTERN usCriticalNesting + +; Functions implemented in this file +;------------------------------------------------------------------------------ + PUBLIC vPortYield + PUBLIC vPortStart + +; Security ID definition +;------------------------------------------------------------------------------ +#define CG_SECURITY0 0FFH +#define CG_SECURITY1 0FFH +#define CG_SECURITY2 0FFH +#define CG_SECURITY3 0FFH +#define CG_SECURITY4 0FFH +#define CG_SECURITY5 0FFH +#define CG_SECURITY6 0FFH +#define CG_SECURITY7 0FFH +#define CG_SECURITY8 0FFH +#define CG_SECURITY9 0FFH + +; Tick ISR Prototype +;------------------------------------------------------------------------------ + PUBWEAK `??MD_INTTM0EQ0??INTVEC 640` + PUBLIC MD_INTTM0EQ0 + +MD_INTTM0EQ0 SYMBOL "MD_INTTM0EQ0" +`??MD_INTTM0EQ0??INTVEC 640` SYMBOL "??INTVEC 640", MD_INTTM0EQ0 + +;------------------------------------------------------------------------------ +; portSAVE_CONTEXT MACRO +; Saves the context of the remaining general purpose registers +; and the usCriticalNesting Value of the active Task onto the task stack +; saves stack pointer to the TCB +;------------------------------------------------------------------------------ +portSAVE_CONTEXT MACRO +#if configDATA_MODE == 1 ; Using the Tiny data model + prepare {r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30},76,sp ; save general purpose registers + sst.w r19,72[ep] + sst.w r18,68[ep] + sst.w r17,64[ep] + sst.w r16,60[ep] + sst.w r15,56[ep] + sst.w r14,52[ep] + sst.w r13,48[ep] + sst.w r12,44[ep] + sst.w r11,40[ep] + sst.w r10,36[ep] + sst.w r9,32[ep] + sst.w r8,28[ep] + sst.w r7,24[ep] + sst.w r6,20[ep] + sst.w r5,16[ep] + sst.w r4,12[ep] +#else ; Using the Small/Large data model + prepare {r20,r21,r22,r23,r24,r26,r27,r28,r29,r30},72,sp ; save general purpose registers + sst.w r19,68[ep] + sst.w r18,64[ep] + sst.w r17,60[ep] + sst.w r16,56[ep] + sst.w r15,52[ep] + sst.w r14,48[ep] + sst.w r13,44[ep] + sst.w r12,40[ep] + sst.w r11,36[ep] + sst.w r10,32[ep] + sst.w r9,28[ep] + sst.w r8,24[ep] + sst.w r7,20[ep] + sst.w r6,16[ep] + sst.w r5,12[ep] +#endif /* configDATA_MODE */ + sst.w r2,8[ep] + sst.w r1,4[ep] + MOVHI hi1(usCriticalNesting),r0,r1 ; save usCriticalNesting value to stack + ld.w lw1(usCriticalNesting)[r1],r2 + sst.w r2,0[ep] + MOVHI hi1(pxCurrentTCB),r0,r1 ; save SP to top of current TCB + ld.w lw1(pxCurrentTCB)[r1],r2 + st.w sp,0[r2] + ENDM +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; portRESTORE_CONTEXT MACRO +; Gets stack pointer from the current TCB +; Restores the context of the usCriticalNesting value and general purpose +; registers of the selected task from the task stack +;------------------------------------------------------------------------------ +portRESTORE_CONTEXT MACRO + MOVHI hi1(pxCurrentTCB),r0,r1 ; get Stackpointer address + ld.w lw1(pxCurrentTCB)[r1],sp + MOV sp,r1 + ld.w 0[r1],sp ; load stackpointer + MOV sp,ep ; set stack pointer to element pointer + sld.w 0[ep],r1 ; load usCriticalNesting value from stack + MOVHI hi1(usCriticalNesting),r0,r2 + st.w r1,lw1(usCriticalNesting)[r2] + sld.w 4[ep],r1 ; restore general purpose registers + sld.w 8[ep],r2 +#if configDATA_MODE == 1 ; Using Tiny data model + sld.w 12[ep],r4 + sld.w 16[ep],r5 + sld.w 20[ep],r6 + sld.w 24[ep],r7 + sld.w 28[ep],r8 + sld.w 32[ep],r9 + sld.w 36[ep],r10 + sld.w 40[ep],r11 + sld.w 44[ep],r12 + sld.w 48[ep],r13 + sld.w 52[ep],r14 + sld.w 56[ep],r15 + sld.w 60[ep],r16 + sld.w 64[ep],r17 + sld.w 68[ep],r18 + sld.w 72[ep],r19 + dispose 76,{r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30} +#else ; Using Small/Large data model + sld.w 12[ep],r5 + sld.w 16[ep],r6 + sld.w 20[ep],r7 + sld.w 24[ep],r8 + sld.w 28[ep],r9 + sld.w 32[ep],r10 + sld.w 36[ep],r11 + sld.w 40[ep],r12 + sld.w 44[ep],r13 + sld.w 48[ep],r14 + sld.w 52[ep],r15 + sld.w 56[ep],r16 + sld.w 60[ep],r17 + sld.w 64[ep],r18 + sld.w 68[ep],r19 + dispose 72,{r20,r21,r22,r23,r24,r26,r27,r28,r29,r30} +#endif /* configDATA_MODE */ + ENDM +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Restore the context of the first task that is going to run. +; +; Input: NONE +; +; Call: CALL vPortStart +; +; Output: NONE +;------------------------------------------------------------------------------ + RSEG CODE:CODE +vPortStart: + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + ld.w 0[sp],lp + ldsr lp,5 ; restore PSW + DI + ld.w 4[sp],lp ; restore LP + ld.w 8[sp],lp ; restore LP + ADD 0x0C,sp ; set SP to right position + EI + jmp [lp] +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Port Yield function to check for a Task switch in the cooperative and +; preemptive mode +; +; Input: NONE +; +; Call: CALL vPortYield +; +; Output: NONE +;------------------------------------------------------------------------------ + + RSEG CODE:CODE +vPortYield: + + add -0x0C,sp ; prepare stack to save necessary values + st.w lp,8[sp] ; store LP to stack + stsr 0,r31 + st.w lp,4[sp] ; store EIPC to stack + stsr 1,lp + st.w lp,0[sp] ; store EIPSW to stack + portSAVE_CONTEXT ; Save the context of the current task. + jarl vTaskSwitchContext,lp ; Call the scheduler. + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + ; ... scheduler decided should run. + ld.w 0[sp],lp ; restore EIPSW from stack + ldsr lp,1 + ld.w 4[sp],lp ; restore EIPC from stack + ldsr lp,0 + ld.w 8[sp],lp ; restore LP from stack + add 0x0C,sp ; set SP to right position + + RETI + +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Perform the necessary steps of the Tick Count Increment and Task Switch +; depending on the chosen kernel configuration +; +; Input: NONE +; +; Call: ISR +; +; Output: NONE +;------------------------------------------------------------------------------ +#if configUSE_PREEMPTION == 1 ; use preemptive kernel mode + +MD_INTTM0EQ0: + + add -0x0C,sp ; prepare stack to save necessary values + st.w lp,8[sp] ; store LP to stack + stsr 0,r31 + st.w lp,4[sp] ; store EIPC to stack + stsr 1,lp + st.w lp,0[sp] ; store EIPSW to stack + portSAVE_CONTEXT ; Save the context of the current task. + jarl xTaskIncrementTick,lp ; Call the timer tick function. + jarl vTaskSwitchContext,lp ; Call the scheduler. + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + ; ... scheduler decided should run. + ld.w 0[sp],lp ; restore EIPSW from stack + ldsr lp,1 + ld.w 4[sp],lp ; restore EIPC from stack + ldsr lp,0 + ld.w 8[sp],lp ; restore LP from stack + add 0x0C,sp ; set SP to right position + + RETI +;------------------------------------------------------------------------------ +#else ; use cooperative kernel mode + +MD_INTTM0EQ0: + prepare {lp,ep},8,sp + sst.w r1,4[ep] + sst.w r5,0[ep] + jarl xTaskIncrementTick,lp ; Call the timer tick function. + sld.w 0[ep],r5 + sld.w 4[ep],r1 + dispose 8,{lp,ep} + RETI +#endif /* configUSE_PREEMPTION */ + +;------------------------------------------------------------------------------ + COMMON INTVEC:CODE:ROOT(2) + ORG 640 +`??MD_INTTM0EQ0??INTVEC 640`: + JR MD_INTTM0EQ0 + + RSEG NEAR_ID:CONST:SORT:NOROOT(2) +`?`: + DW 10 + + COMMON INTVEC:CODE:ROOT(2) + ORG 40H +`??vPortYield??INTVEC 40`: + JR vPortYield + +;------------------------------------------------------------------------------ +; set microcontroller security ID + + COMMON INTVEC:CODE:ROOT(2) + ORG 70H +`SECUID`: + DB CG_SECURITY0 + DB CG_SECURITY1 + DB CG_SECURITY2 + DB CG_SECURITY3 + DB CG_SECURITY4 + DB CG_SECURITY5 + DB CG_SECURITY6 + DB CG_SECURITY7 + DB CG_SECURITY8 + DB CG_SECURITY9 + + + END diff --git a/portable/IAR/V850ES/portasm_Fx3.s85 b/portable/IAR/V850ES/portasm_Fx3.s85 new file mode 100644 index 000000000..12262b3af --- /dev/null +++ b/portable/IAR/V850ES/portasm_Fx3.s85 @@ -0,0 +1,336 @@ +;/* +; * FreeRTOS Kernel +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ +; Note: Select the correct include files for the device used by the application. +#include "FreeRTOSConfig.h" +;------------------------------------------------------------------------------ + +; Functions used by scheduler +;------------------------------------------------------------------------------ + EXTERN vTaskSwitchContext + EXTERN xTaskIncrementTick + +; Variables used by scheduler +;------------------------------------------------------------------------------ + EXTERN pxCurrentTCB + EXTERN usCriticalNesting + +; Functions implemented in this file +;------------------------------------------------------------------------------ + PUBLIC vPortYield + PUBLIC vPortStart + +; Security ID definition +;------------------------------------------------------------------------------ +#define CG_SECURITY0 0FFH +#define CG_SECURITY1 0FFH +#define CG_SECURITY2 0FFH +#define CG_SECURITY3 0FFH +#define CG_SECURITY4 0FFH +#define CG_SECURITY5 0FFH +#define CG_SECURITY6 0FFH +#define CG_SECURITY7 0FFH +#define CG_SECURITY8 0FFH +#define CG_SECURITY9 0FFH + +; Option Byte definitions +;------------------------------------------------------------------------------ +#define CG_OPTION7A 0x00 +#define CG_OPTION7B 0x04 +#define OPT7C 0x00 +#define OPT7D 0x00 +#define OPT7E 0x00 +#define OPT7F 0x00 + +; Tick ISR Prototype +;------------------------------------------------------------------------------ + PUBWEAK `??MD_INTTM0EQ0??INTVEC 608` + PUBLIC MD_INTTM0EQ0 + +MD_INTTM0EQ0 SYMBOL "MD_INTTM0EQ0" +`??MD_INTTM0EQ0??INTVEC 608` SYMBOL "??INTVEC 608", MD_INTTM0EQ0 + +;------------------------------------------------------------------------------ +; portSAVE_CONTEXT MACRO +; Saves the context of the remaining general purpose registers +; and the usCriticalNesting Value of the active Task onto the task stack +; saves stack pointer to the TCB +;------------------------------------------------------------------------------ +portSAVE_CONTEXT MACRO +#if configDATA_MODE == 1 ; Using the Tiny data model + prepare {r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30},76,sp ; save general purpose registers + sst.w r19,72[ep] + sst.w r18,68[ep] + sst.w r17,64[ep] + sst.w r16,60[ep] + sst.w r15,56[ep] + sst.w r14,52[ep] + sst.w r13,48[ep] + sst.w r12,44[ep] + sst.w r11,40[ep] + sst.w r10,36[ep] + sst.w r9,32[ep] + sst.w r8,28[ep] + sst.w r7,24[ep] + sst.w r6,20[ep] + sst.w r5,16[ep] + sst.w r4,12[ep] +#else ; Using the Small/Large data model + prepare {r20,r21,r22,r23,r24,r26,r27,r28,r29,r30},72,sp ; save general purpose registers + sst.w r19,68[ep] + sst.w r18,64[ep] + sst.w r17,60[ep] + sst.w r16,56[ep] + sst.w r15,52[ep] + sst.w r14,48[ep] + sst.w r13,44[ep] + sst.w r12,40[ep] + sst.w r11,36[ep] + sst.w r10,32[ep] + sst.w r9,28[ep] + sst.w r8,24[ep] + sst.w r7,20[ep] + sst.w r6,16[ep] + sst.w r5,12[ep] +#endif /* configDATA_MODE */ + sst.w r2,8[ep] + sst.w r1,4[ep] + MOVHI hi1(usCriticalNesting),r0,r1 ; save usCriticalNesting value to stack + ld.w lw1(usCriticalNesting)[r1],r2 + sst.w r2,0[ep] + MOVHI hi1(pxCurrentTCB),r0,r1 ; save SP to top of current TCB + ld.w lw1(pxCurrentTCB)[r1],r2 + st.w sp,0[r2] + ENDM +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; portRESTORE_CONTEXT MACRO +; Gets stack pointer from the current TCB +; Restores the context of the usCriticalNesting value and general purpose +; registers of the selected task from the task stack +;------------------------------------------------------------------------------ +portRESTORE_CONTEXT MACRO + MOVHI hi1(pxCurrentTCB),r0,r1 ; get Stackpointer address + ld.w lw1(pxCurrentTCB)[r1],sp + MOV sp,r1 + ld.w 0[r1],sp ; load stackpointer + MOV sp,ep ; set stack pointer to element pointer + sld.w 0[ep],r1 ; load usCriticalNesting value from stack + MOVHI hi1(usCriticalNesting),r0,r2 + st.w r1,lw1(usCriticalNesting)[r2] + sld.w 4[ep],r1 ; restore general purpose registers + sld.w 8[ep],r2 +#if configDATA_MODE == 1 ; Using Tiny data model + sld.w 12[ep],r4 + sld.w 16[ep],r5 + sld.w 20[ep],r6 + sld.w 24[ep],r7 + sld.w 28[ep],r8 + sld.w 32[ep],r9 + sld.w 36[ep],r10 + sld.w 40[ep],r11 + sld.w 44[ep],r12 + sld.w 48[ep],r13 + sld.w 52[ep],r14 + sld.w 56[ep],r15 + sld.w 60[ep],r16 + sld.w 64[ep],r17 + sld.w 68[ep],r18 + sld.w 72[ep],r19 + dispose 76,{r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30} +#else ; Using Small/Large data model + sld.w 12[ep],r5 + sld.w 16[ep],r6 + sld.w 20[ep],r7 + sld.w 24[ep],r8 + sld.w 28[ep],r9 + sld.w 32[ep],r10 + sld.w 36[ep],r11 + sld.w 40[ep],r12 + sld.w 44[ep],r13 + sld.w 48[ep],r14 + sld.w 52[ep],r15 + sld.w 56[ep],r16 + sld.w 60[ep],r17 + sld.w 64[ep],r18 + sld.w 68[ep],r19 + dispose 72,{r20,r21,r22,r23,r24,r26,r27,r28,r29,r30} +#endif /* configDATA_MODE */ + ENDM +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Restore the context of the first task that is going to run. +; +; Input: NONE +; +; Call: CALL vPortStart +; +; Output: NONE +;------------------------------------------------------------------------------ + RSEG CODE:CODE +vPortStart: + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + ld.w 0[sp],lp + ldsr lp,5 ; restore PSW + DI + ld.w 4[sp],lp ; restore LP + ld.w 8[sp],lp ; restore LP + ADD 0x0C,sp ; set SP to right position + EI + jmp [lp] +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Port Yield function to check for a Task switch in the cooperative and +; preemptive mode +; +; Input: NONE +; +; Call: CALL vPortYield +; +; Output: NONE +;------------------------------------------------------------------------------ + + RSEG CODE:CODE +vPortYield: + + add -0x0C,sp ; prepare stack to save necessary values + st.w lp,8[sp] ; store LP to stack + stsr 0,r31 + st.w lp,4[sp] ; store EIPC to stack + stsr 1,lp + st.w lp,0[sp] ; store EIPSW to stack + portSAVE_CONTEXT ; Save the context of the current task. + jarl vTaskSwitchContext,lp ; Call the scheduler. + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + ; ... scheduler decided should run. + ld.w 0[sp],lp ; restore EIPSW from stack + ldsr lp,1 + ld.w 4[sp],lp ; restore EIPC from stack + ldsr lp,0 + ld.w 8[sp],lp ; restore LP from stack + add 0x0C,sp ; set SP to right position + + RETI + +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Perform the necessary steps of the Tick Count Increment and Task Switch +; depending on the chosen kernel configuration +; +; Input: NONE +; +; Call: ISR +; +; Output: NONE +;------------------------------------------------------------------------------ +#if configUSE_PREEMPTION == 1 ; use preemptive kernel mode + +MD_INTTM0EQ0: + + add -0x0C,sp ; prepare stack to save necessary values + st.w lp,8[sp] ; store LP to stack + stsr 0,r31 + st.w lp,4[sp] ; store EIPC to stack + stsr 1,lp + st.w lp,0[sp] ; store EIPSW to stack + portSAVE_CONTEXT ; Save the context of the current task. + jarl xTaskIncrementTick,lp ; Call the timer tick function. + jarl vTaskSwitchContext,lp ; Call the scheduler. + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + ; ... scheduler decided should run. + ld.w 0[sp],lp ; restore EIPSW from stack + ldsr lp,1 + ld.w 4[sp],lp ; restore EIPC from stack + ldsr lp,0 + ld.w 8[sp],lp ; restore LP from stack + add 0x0C,sp ; set SP to right position + + RETI +;------------------------------------------------------------------------------ +#else ; use cooperative kernel mode + +MD_INTTM0EQ0: + prepare {lp,ep},8,sp + sst.w r1,4[ep] + sst.w r5,0[ep] + jarl xTaskIncrementTick,lp ; Call the timer tick function. + sld.w 0[ep],r5 + sld.w 4[ep],r1 + dispose 8,{lp,ep} + RETI +#endif /* configUSE_PREEMPTION */ + +;------------------------------------------------------------------------------ + COMMON INTVEC:CODE:ROOT(2) + ORG 608 +`??MD_INTTM0EQ0??INTVEC 608`: + JR MD_INTTM0EQ0 + + RSEG NEAR_ID:CONST:SORT:NOROOT(2) +`?`: + DW 10 + + COMMON INTVEC:CODE:ROOT(2) + ORG 40H +`??vPortYield??INTVEC 40`: + JR vPortYield + +;------------------------------------------------------------------------------ +; set microcontroller security ID + + COMMON INTVEC:CODE:ROOT(2) + ORG 70H +`SECUID`: + DB CG_SECURITY0 + DB CG_SECURITY1 + DB CG_SECURITY2 + DB CG_SECURITY3 + DB CG_SECURITY4 + DB CG_SECURITY5 + DB CG_SECURITY6 + DB CG_SECURITY7 + DB CG_SECURITY8 + DB CG_SECURITY9 + +;------------------------------------------------------------------------------ +; set microcontroller option bytes + + COMMON INTVEC:CODE:ROOT(2) + ORG 7AH +`OPTBYTES`: + DB CG_OPTION7A + DB CG_OPTION7B + DB OPT7C + DB OPT7D + DB OPT7E + DB OPT7F + + END diff --git a/portable/IAR/V850ES/portasm_Hx2.s85 b/portable/IAR/V850ES/portasm_Hx2.s85 new file mode 100644 index 000000000..03c2e38ae --- /dev/null +++ b/portable/IAR/V850ES/portasm_Hx2.s85 @@ -0,0 +1,350 @@ +;/* +; * FreeRTOS Kernel +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ +; Note: Select the correct include files for the device used by the application. +#include "FreeRTOSConfig.h" +;------------------------------------------------------------------------------ + +; Functions used by scheduler +;------------------------------------------------------------------------------ + EXTERN vTaskSwitchContext + EXTERN xTaskIncrementTick + +; Variables used by scheduler +;------------------------------------------------------------------------------ + EXTERN pxCurrentTCB + EXTERN usCriticalNesting + +; Functions implemented in this file +;------------------------------------------------------------------------------ + PUBLIC vPortYield + PUBLIC vPortStart + +; Security ID definition +;------------------------------------------------------------------------------ +#define CG_SECURITY0 0FFH +#define CG_SECURITY1 0FFH +#define CG_SECURITY2 0FFH +#define CG_SECURITY3 0FFH +#define CG_SECURITY4 0FFH +#define CG_SECURITY5 0FFH +#define CG_SECURITY6 0FFH +#define CG_SECURITY7 0FFH +#define CG_SECURITY8 0FFH +#define CG_SECURITY9 0FFH + +; Tick ISR Prototype +;------------------------------------------------------------------------------ + PUBWEAK `??MD_INTTM0EQ0??INTVEC 544` + PUBLIC MD_INTTM0EQ0 + +MD_INTTM0EQ0 SYMBOL "MD_INTTM0EQ0" +`??MD_INTTM0EQ0??INTVEC 544` SYMBOL "??INTVEC 544", MD_INTTM0EQ0 + +;------------------------------------------------------------------------------ +; portSAVE_CONTEXT MACRO +; Saves the context of the remaining general purpose registers +; and the usCriticalNesting Value of the active Task onto the task stack +; saves stack pointer to the TCB +;------------------------------------------------------------------------------ +portSAVE_CONTEXT MACRO +#if configDATA_MODE == 1 ; Using the Tiny data model + prepare {r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30},76,sp ; save general purpose registers + sst.w r19,72[ep] + sst.w r18,68[ep] + sst.w r17,64[ep] + sst.w r16,60[ep] + sst.w r15,56[ep] + sst.w r14,52[ep] + sst.w r13,48[ep] + sst.w r12,44[ep] + sst.w r11,40[ep] + sst.w r10,36[ep] + sst.w r9,32[ep] + sst.w r8,28[ep] + sst.w r7,24[ep] + sst.w r6,20[ep] + sst.w r5,16[ep] + sst.w r4,12[ep] +#else ; Using the Small/Large data model + prepare {r20,r21,r22,r23,r24,r26,r27,r28,r29,r30},72,sp ; save general purpose registers + sst.w r19,68[ep] + sst.w r18,64[ep] + sst.w r17,60[ep] + sst.w r16,56[ep] + sst.w r15,52[ep] + sst.w r14,48[ep] + sst.w r13,44[ep] + sst.w r12,40[ep] + sst.w r11,36[ep] + sst.w r10,32[ep] + sst.w r9,28[ep] + sst.w r8,24[ep] + sst.w r7,20[ep] + sst.w r6,16[ep] + sst.w r5,12[ep] +#endif /* configDATA_MODE */ + sst.w r2,8[ep] + sst.w r1,4[ep] + MOVHI hi1(usCriticalNesting),r0,r1 ; save usCriticalNesting value to stack + ld.w lw1(usCriticalNesting)[r1],r2 + sst.w r2,0[ep] + MOVHI hi1(pxCurrentTCB),r0,r1 ; save SP to top of current TCB + ld.w lw1(pxCurrentTCB)[r1],r2 + st.w sp,0[r2] + ENDM +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; portRESTORE_CONTEXT MACRO +; Gets stack pointer from the current TCB +; Restores the context of the usCriticalNesting value and general purpose +; registers of the selected task from the task stack +;------------------------------------------------------------------------------ +portRESTORE_CONTEXT MACRO + MOVHI hi1(pxCurrentTCB),r0,r1 ; get Stackpointer address + ld.w lw1(pxCurrentTCB)[r1],sp + MOV sp,r1 + ld.w 0[r1],sp ; load stackpointer + MOV sp,ep ; set stack pointer to element pointer + sld.w 0[ep],r1 ; load usCriticalNesting value from stack + MOVHI hi1(usCriticalNesting),r0,r2 + st.w r1,lw1(usCriticalNesting)[r2] + sld.w 4[ep],r1 ; restore general purpose registers + sld.w 8[ep],r2 +#if configDATA_MODE == 1 ; Using Tiny data model + sld.w 12[ep],r4 + sld.w 16[ep],r5 + sld.w 20[ep],r6 + sld.w 24[ep],r7 + sld.w 28[ep],r8 + sld.w 32[ep],r9 + sld.w 36[ep],r10 + sld.w 40[ep],r11 + sld.w 44[ep],r12 + sld.w 48[ep],r13 + sld.w 52[ep],r14 + sld.w 56[ep],r15 + sld.w 60[ep],r16 + sld.w 64[ep],r17 + sld.w 68[ep],r18 + sld.w 72[ep],r19 + dispose 76,{r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30} +#else ; Using Small/Large data model + sld.w 12[ep],r5 + sld.w 16[ep],r6 + sld.w 20[ep],r7 + sld.w 24[ep],r8 + sld.w 28[ep],r9 + sld.w 32[ep],r10 + sld.w 36[ep],r11 + sld.w 40[ep],r12 + sld.w 44[ep],r13 + sld.w 48[ep],r14 + sld.w 52[ep],r15 + sld.w 56[ep],r16 + sld.w 60[ep],r17 + sld.w 64[ep],r18 + sld.w 68[ep],r19 + dispose 72,{r20,r21,r22,r23,r24,r26,r27,r28,r29,r30} +#endif /* configDATA_MODE */ + ENDM +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Restore the context of the first task that is going to run. +; +; Input: NONE +; +; Call: CALL vPortStart +; +; Output: NONE +;------------------------------------------------------------------------------ + RSEG CODE:CODE +vPortStart: + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + ld.w 0[sp],lp + ldsr lp,5 ; restore PSW + DI + ld.w 4[sp],lp ; restore LP + ld.w 8[sp],lp ; restore LP + ADD 0x0C,sp ; set SP to right position + EI + jmp [lp] +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Port Yield function to check for a Task switch in the cooperative and +; preemptive mode +; +; Input: NONE +; +; Call: CALL vPortYield +; +; Output: NONE +;------------------------------------------------------------------------------ + + RSEG CODE:CODE +vPortYield: + + add -0x0C,sp ; prepare stack to save necessary values + st.w lp,8[sp] ; store LP to stack + stsr 0,r31 + st.w lp,4[sp] ; store EIPC to stack + stsr 1,lp + st.w lp,0[sp] ; store EIPSW to stack + portSAVE_CONTEXT ; Save the context of the current task. + jarl vTaskSwitchContext,lp ; Call the scheduler. + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + ; ... scheduler decided should run. + ld.w 0[sp],lp ; restore EIPSW from stack + ldsr lp,1 + ld.w 4[sp],lp ; restore EIPC from stack + ldsr lp,0 + ld.w 8[sp],lp ; restore LP from stack + add 0x0C,sp ; set SP to right position + + RETI + +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Perform the necessary steps of the Tick Count Increment and Task Switch +; depending on the chosen kernel configuration +; +; Input: NONE +; +; Call: ISR +; +; Output: NONE +;------------------------------------------------------------------------------ +#if configUSE_PREEMPTION == 1 ; use preemptive kernel mode + +MD_INTTM0EQ0: + + add -0x0C,sp ; prepare stack to save necessary values + st.w lp,8[sp] ; store LP to stack + stsr 0,r31 + st.w lp,4[sp] ; store EIPC to stack + stsr 1,lp + st.w lp,0[sp] ; store EIPSW to stack + portSAVE_CONTEXT ; Save the context of the current task. + jarl xTaskIncrementTick,lp ; Call the timer tick function. + jarl vTaskSwitchContext,lp ; Call the scheduler. + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + ; ... scheduler decided should run. + ld.w 0[sp],lp ; restore EIPSW from stack + ldsr lp,1 + ld.w 4[sp],lp ; restore EIPC from stack + ldsr lp,0 + ld.w 8[sp],lp ; restore LP from stack + add 0x0C,sp ; set SP to right position + + RETI +;------------------------------------------------------------------------------ +#else ; use cooperative kernel mode + +MD_INTTM0EQ0: + prepare {lp,ep},8,sp + sst.w r1,4[ep] + sst.w r5,0[ep] + jarl xTaskIncrementTick,lp ; Call the timer tick function. + sld.w 0[ep],r5 + sld.w 4[ep],r1 + dispose 8,{lp,ep} + RETI +#endif /* configUSE_PREEMPTION */ + +;------------------------------------------------------------------------------ + COMMON INTVEC:CODE:ROOT(2) + ORG 544 +`??MD_INTTM0EQ0??INTVEC 544`: + JR MD_INTTM0EQ0 + + RSEG NEAR_ID:CONST:SORT:NOROOT(2) +`?`: + DW 10 + + COMMON INTVEC:CODE:ROOT(2) + ORG 40H +`??vPortYield??INTVEC 40`: + JR vPortYield + +;------------------------------------------------------------------------------ +; set microcontroller security ID + + COMMON INTVEC:CODE:ROOT(2) + ORG 70H +`SECUID`: + DB CG_SECURITY0 + DB CG_SECURITY1 + DB CG_SECURITY2 + DB CG_SECURITY3 + DB CG_SECURITY4 + DB CG_SECURITY5 + DB CG_SECURITY6 + DB CG_SECURITY7 + DB CG_SECURITY8 + DB CG_SECURITY9 + + +; set microcontroller Option bytes + + COMMON INTVEC:CODE:ROOT(2) + ORG 122 +`OPTBYTES`: + DB 0xFD + DB 0xFF + DB 0xFF + DB 0xFF + DB 0xFF + DB 0xFF + +#if configOCD_USAGE == 1 + + COMMON INTVEC:CODE:ROOT(4) + ORG 0x230 + PUBLIC ROM_INT2 +ROM_INT2: + DB 0xff, 0xff, 0xff, 0xff + DB 0xff, 0xff, 0xff, 0xff + DB 0xff, 0xff, 0xff, 0xff + DB 0xff, 0xff, 0xff, 0xff + + + COMMON INTVEC:CODE:ROOT(4) + ORG 0x60 + PUBLIC ROM_INT +ROM_INT: + DB 0xff, 0xff, 0xff, 0xff + DB 0xff, 0xff, 0xff, 0xff + DB 0xff, 0xff, 0xff, 0xff + DB 0xff, 0xff, 0xff, 0xff + +#endif /* configOCD_USAGE */ + + END diff --git a/portable/IAR/V850ES/portmacro.h b/portable/IAR/V850ES/portmacro.h new file mode 100644 index 000000000..0f066a0fc --- /dev/null +++ b/portable/IAR/V850ES/portmacro.h @@ -0,0 +1,141 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned int +#define portBASE_TYPE int + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Interrupt control macros. */ +#define portDISABLE_INTERRUPTS() __asm( "DI" ) +#define portENABLE_INTERRUPTS() __asm( "EI" ) +/*-----------------------------------------------------------*/ + +/* Critical section control macros. */ +#define portNO_CRITICAL_SECTION_NESTING ( ( UBaseType_t ) 0 ) + +#define portENTER_CRITICAL() \ + { \ + extern volatile /*uint16_t*/ portSTACK_TYPE usCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + \ + /* Now that interrupts are disabled, ulCriticalNesting can be accessed */ \ + /* directly. Increment ulCriticalNesting to keep a count of how many */ \ + /* times portENTER_CRITICAL() has been called. */ \ + usCriticalNesting++; \ + } + +#define portEXIT_CRITICAL() \ + { \ + extern volatile /*uint16_t*/ portSTACK_TYPE usCriticalNesting; \ + \ + if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ + { \ + /* Decrement the nesting count as we are leaving a critical section. */ \ + usCriticalNesting--; \ + \ + /* If the nesting level has reached zero then interrupts should be */ \ + /* re-enabled. */ \ + if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } \ + } +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +extern void vPortYield( void ); +extern void vPortStart( void ); +extern void portSAVE_CONTEXT( void ); +extern void portRESTORE_CONTEXT( void ); +#define portYIELD() __asm( "trap 0" ) +#define portNOP() __asm( "NOP" ) +extern void vTaskSwitchContext( void ); +#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) do { if( xHigherPriorityTaskWoken ) vTaskSwitchContext( ); } while( 0 ) + +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 4 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/Keil/See-also-the-RVDS-directory.txt b/portable/Keil/See-also-the-RVDS-directory.txt new file mode 100644 index 000000000..944c593a9 --- /dev/null +++ b/portable/Keil/See-also-the-RVDS-directory.txt @@ -0,0 +1 @@ +Nothing to see here. diff --git a/portable/MPLAB/PIC18F/port.c b/portable/MPLAB/PIC18F/port.c new file mode 100644 index 000000000..bb8451581 --- /dev/null +++ b/portable/MPLAB/PIC18F/port.c @@ -0,0 +1,615 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* +Changes between V1.2.4 and V1.2.5 + + + Introduced portGLOBAL_INTERRUPT_FLAG definition to test the global + interrupt flag setting. Using the two bits defined within + portINITAL_INTERRUPT_STATE was causing the w register to get clobbered + before the test was performed. + +Changes from V1.2.5 + + + Set the interrupt vector address to 0x08. Previously it was at the + incorrect address for compatibility mode of 0x18. + +Changes from V2.1.1 + + + PCLATU and PCLATH are now saved as part of the context. This allows + function pointers to be used within tasks. Thanks to Javier Espeche + for the enhancement. + +Changes from V2.3.1 + + + TABLAT is now saved as part of the task context. + +Changes from V3.2.0 + + + TBLPTRU is now initialised to zero as the MPLAB compiler expects this + value and does not write to the register. +*/ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPLAB library include file. */ +#include "timers.h" + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the PIC port. + *----------------------------------------------------------*/ + +/* Hardware setup for tick. */ +#define portTIMER_FOSC_SCALE ( ( uint32_t ) 4 ) + +/* Initial interrupt enable state for newly created tasks. This value is +copied into INTCON when a task switches in for the first time. */ +#define portINITAL_INTERRUPT_STATE 0xc0 + +/* Just the bit within INTCON for the global interrupt flag. */ +#define portGLOBAL_INTERRUPT_FLAG 0x80 + +/* Constant used for context switch macro when we require the interrupt +enable state to be unchanged when the interrupted task is switched back in. */ +#define portINTERRUPTS_UNCHANGED 0x00 + +/* Some memory areas get saved as part of the task context. These memory +area's get used by the compiler for temporary storage, especially when +performing mathematical operations, or when using 32bit data types. This +constant defines the size of memory area which must be saved. */ +#define portCOMPILER_MANAGED_MEMORY_SIZE ( ( uint8_t ) 0x13 ) + +/* We require the address of the pxCurrentTCB variable, but don't want to know +any details of its type. */ +typedef void TCB_t; +extern volatile TCB_t * volatile pxCurrentTCB; + +/* IO port constants. */ +#define portBIT_SET ( ( uint8_t ) 1 ) +#define portBIT_CLEAR ( ( uint8_t ) 0 ) + +/* + * The serial port ISR's are defined in serial.c, but are called from portable + * as they use the same vector as the tick ISR. + */ +void vSerialTxISR( void ); +void vSerialRxISR( void ); + +/* + * Perform hardware setup to enable ticks. + */ +static void prvSetupTimerInterrupt( void ); + +/* + * ISR to maintain the tick, and perform tick context switches if the + * preemptive scheduler is being used. + */ +static void prvTickISR( void ); + +/* + * ISR placed on the low priority vector. This calls the appropriate ISR for + * the actual interrupt. + */ +static void prvLowInterrupt( void ); + +/* + * Macro that pushes all the registers that make up the context of a task onto + * the stack, then saves the new top of stack into the TCB. + * + * If this is called from an ISR then the interrupt enable bits must have been + * set for the ISR to ever get called. Therefore we want to save the INTCON + * register with the enable bits forced to be set - and ucForcedInterruptFlags + * must contain these bit settings. This means the interrupts will again be + * enabled when the interrupted task is switched back in. + * + * If this is called from a manual context switch (i.e. from a call to yield), + * then we want to save the INTCON so it is restored with its current state, + * and ucForcedInterruptFlags must be 0. This allows a yield from within + * a critical section. + * + * The compiler uses some locations at the bottom of the memory for temporary + * storage during math and other computations. This is especially true if + * 32bit data types are utilized (as they are by the scheduler). The .tmpdata + * and MATH_DATA sections have to be stored in there entirety as part of a task + * context. This macro stores from data address 0x00 to + * portCOMPILER_MANAGED_MEMORY_SIZE. This is sufficient for the demo + * applications but you should check the map file for your project to ensure + * this is sufficient for your needs. It is not clear whether this size is + * fixed for all compilations or has the potential to be program specific. + */ +#define portSAVE_CONTEXT( ucForcedInterruptFlags ) \ +{ \ + _asm \ + /* Save the status and WREG registers first, as these will get modified \ + by the operations below. */ \ + MOVFF WREG, PREINC1 \ + MOVFF STATUS, PREINC1 \ + /* Save the INTCON register with the appropriate bits forced if \ + necessary - as described above. */ \ + MOVFF INTCON, WREG \ + IORLW ucForcedInterruptFlags \ + MOVFF WREG, PREINC1 \ + _endasm \ + \ + portDISABLE_INTERRUPTS(); \ + \ + _asm \ + /* Store the necessary registers to the stack. */ \ + MOVFF BSR, PREINC1 \ + MOVFF FSR2L, PREINC1 \ + MOVFF FSR2H, PREINC1 \ + MOVFF FSR0L, PREINC1 \ + MOVFF FSR0H, PREINC1 \ + MOVFF TABLAT, PREINC1 \ + MOVFF TBLPTRU, PREINC1 \ + MOVFF TBLPTRH, PREINC1 \ + MOVFF TBLPTRL, PREINC1 \ + MOVFF PRODH, PREINC1 \ + MOVFF PRODL, PREINC1 \ + MOVFF PCLATU, PREINC1 \ + MOVFF PCLATH, PREINC1 \ + /* Store the .tempdata and MATH_DATA areas as described above. */ \ + CLRF FSR0L, 0 \ + CLRF FSR0H, 0 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF POSTINC0, PREINC1 \ + MOVFF INDF0, PREINC1 \ + MOVFF FSR0L, PREINC1 \ + MOVFF FSR0H, PREINC1 \ + /* Store the hardware stack pointer in a temp register before we \ + modify it. */ \ + MOVFF STKPTR, FSR0L \ + _endasm \ + \ + /* Store each address from the hardware stack. */ \ + while( STKPTR > ( uint8_t ) 0 ) \ + { \ + _asm \ + MOVFF TOSL, PREINC1 \ + MOVFF TOSH, PREINC1 \ + MOVFF TOSU, PREINC1 \ + POP \ + _endasm \ + } \ + \ + _asm \ + /* Store the number of addresses on the hardware stack (from the \ + temporary register). */ \ + MOVFF FSR0L, PREINC1 \ + MOVF PREINC1, 1, 0 \ + _endasm \ + \ + /* Save the new top of the software stack in the TCB. */ \ + _asm \ + MOVFF pxCurrentTCB, FSR0L \ + MOVFF pxCurrentTCB + 1, FSR0H \ + MOVFF FSR1L, POSTINC0 \ + MOVFF FSR1H, POSTINC0 \ + _endasm \ +} +/*-----------------------------------------------------------*/ + +/* + * This is the reverse of portSAVE_CONTEXT. See portSAVE_CONTEXT for more + * details. + */ +#define portRESTORE_CONTEXT() \ +{ \ + _asm \ + /* Set FSR0 to point to pxCurrentTCB->pxTopOfStack. */ \ + MOVFF pxCurrentTCB, FSR0L \ + MOVFF pxCurrentTCB + 1, FSR0H \ + \ + /* De-reference FSR0 to set the address it holds into FSR1. \ + (i.e. *( pxCurrentTCB->pxTopOfStack ) ). */ \ + MOVFF POSTINC0, FSR1L \ + MOVFF POSTINC0, FSR1H \ + \ + /* How many return addresses are there on the hardware stack? Discard \ + the first byte as we are pointing to the next free space. */ \ + MOVFF POSTDEC1, FSR0L \ + MOVFF POSTDEC1, FSR0L \ + _endasm \ + \ + /* Fill the hardware stack from our software stack. */ \ + STKPTR = 0; \ + \ + while( STKPTR < FSR0L ) \ + { \ + _asm \ + PUSH \ + MOVF POSTDEC1, 0, 0 \ + MOVWF TOSU, 0 \ + MOVF POSTDEC1, 0, 0 \ + MOVWF TOSH, 0 \ + MOVF POSTDEC1, 0, 0 \ + MOVWF TOSL, 0 \ + _endasm \ + } \ + \ + _asm \ + /* Restore the .tmpdata and MATH_DATA memory. */ \ + MOVFF POSTDEC1, FSR0H \ + MOVFF POSTDEC1, FSR0L \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, POSTDEC0 \ + MOVFF POSTDEC1, INDF0 \ + /* Restore the other registers forming the tasks context. */ \ + MOVFF POSTDEC1, PCLATH \ + MOVFF POSTDEC1, PCLATU \ + MOVFF POSTDEC1, PRODL \ + MOVFF POSTDEC1, PRODH \ + MOVFF POSTDEC1, TBLPTRL \ + MOVFF POSTDEC1, TBLPTRH \ + MOVFF POSTDEC1, TBLPTRU \ + MOVFF POSTDEC1, TABLAT \ + MOVFF POSTDEC1, FSR0H \ + MOVFF POSTDEC1, FSR0L \ + MOVFF POSTDEC1, FSR2H \ + MOVFF POSTDEC1, FSR2L \ + MOVFF POSTDEC1, BSR \ + /* The next byte is the INTCON register. Read this into WREG as some \ + manipulation is required. */ \ + MOVFF POSTDEC1, WREG \ + _endasm \ + \ + /* From the INTCON register, only the interrupt enable bits form part \ + of the tasks context. It is perfectly legitimate for another task to \ + have modified any other bits. We therefore only restore the top two bits. \ + */ \ + if( WREG & portGLOBAL_INTERRUPT_FLAG ) \ + { \ + _asm \ + MOVFF POSTDEC1, STATUS \ + MOVFF POSTDEC1, WREG \ + /* Return enabling interrupts. */ \ + RETFIE 0 \ + _endasm \ + } \ + else \ + { \ + _asm \ + MOVFF POSTDEC1, STATUS \ + MOVFF POSTDEC1, WREG \ + /* Return without effecting interrupts. The context may have \ + been saved from a critical region. */ \ + RETURN 0 \ + _endasm \ + } \ +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +uint32_t ulAddress; +uint8_t ucBlock; + + /* Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging. */ + + *pxTopOfStack = 0x11; + pxTopOfStack++; + *pxTopOfStack = 0x22; + pxTopOfStack++; + *pxTopOfStack = 0x33; + pxTopOfStack++; + + + /* Simulate how the stack would look after a call to vPortYield() generated + by the compiler. + + First store the function parameters. This is where the task will expect to + find them when it starts running. */ + ulAddress = ( uint32_t ) pvParameters; + *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff ); + pxTopOfStack++; + + ulAddress >>= 8; + *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff ); + pxTopOfStack++; + + /* Next we just leave a space. When a context is saved the stack pointer + is incremented before it is used so as not to corrupt whatever the stack + pointer is actually pointing to. This is especially necessary during + function epilogue code generated by the compiler. */ + *pxTopOfStack = 0x44; + pxTopOfStack++; + + /* Next are all the registers that form part of the task context. */ + + *pxTopOfStack = ( StackType_t ) 0x66; /* WREG. */ + pxTopOfStack++; + + *pxTopOfStack = ( StackType_t ) 0xcc; /* Status. */ + pxTopOfStack++; + + /* INTCON is saved with interrupts enabled. */ + *pxTopOfStack = ( StackType_t ) portINITAL_INTERRUPT_STATE; /* INTCON */ + pxTopOfStack++; + + *pxTopOfStack = ( StackType_t ) 0x11; /* BSR. */ + pxTopOfStack++; + + *pxTopOfStack = ( StackType_t ) 0x22; /* FSR2L. */ + pxTopOfStack++; + + *pxTopOfStack = ( StackType_t ) 0x33; /* FSR2H. */ + pxTopOfStack++; + + *pxTopOfStack = ( StackType_t ) 0x44; /* FSR0L. */ + pxTopOfStack++; + + *pxTopOfStack = ( StackType_t ) 0x55; /* FSR0H. */ + pxTopOfStack++; + + *pxTopOfStack = ( StackType_t ) 0x66; /* TABLAT. */ + pxTopOfStack++; + + *pxTopOfStack = ( StackType_t ) 0x00; /* TBLPTRU. */ + pxTopOfStack++; + + *pxTopOfStack = ( StackType_t ) 0x88; /* TBLPTRUH. */ + pxTopOfStack++; + + *pxTopOfStack = ( StackType_t ) 0x99; /* TBLPTRUL. */ + pxTopOfStack++; + + *pxTopOfStack = ( StackType_t ) 0xaa; /* PRODH. */ + pxTopOfStack++; + + *pxTopOfStack = ( StackType_t ) 0xbb; /* PRODL. */ + pxTopOfStack++; + + *pxTopOfStack = ( StackType_t ) 0x00; /* PCLATU. */ + pxTopOfStack++; + + *pxTopOfStack = ( StackType_t ) 0x00; /* PCLATH. */ + pxTopOfStack++; + + /* Next the .tmpdata and MATH_DATA sections. */ + for( ucBlock = 0; ucBlock <= portCOMPILER_MANAGED_MEMORY_SIZE; ucBlock++ ) + { + *pxTopOfStack = ( StackType_t ) ucBlock; + *pxTopOfStack++; + } + + /* Store the top of the global data section. */ + *pxTopOfStack = ( StackType_t ) portCOMPILER_MANAGED_MEMORY_SIZE; /* Low. */ + pxTopOfStack++; + + *pxTopOfStack = ( StackType_t ) 0x00; /* High. */ + pxTopOfStack++; + + /* The only function return address so far is the address of the + task. */ + ulAddress = ( uint32_t ) pxCode; + + /* TOS low. */ + *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff ); + pxTopOfStack++; + ulAddress >>= 8; + + /* TOS high. */ + *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff ); + pxTopOfStack++; + ulAddress >>= 8; + + /* TOS even higher. */ + *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff ); + pxTopOfStack++; + + /* Store the number of return addresses on the hardware stack - so far only + the address of the task entry point. */ + *pxTopOfStack = ( StackType_t ) 1; + pxTopOfStack++; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Setup a timer for the tick ISR is using the preemptive scheduler. */ + prvSetupTimerInterrupt(); + + /* Restore the context of the first task to run. */ + portRESTORE_CONTEXT(); + + /* Should not get here. Use the function name to stop compiler warnings. */ + ( void ) prvLowInterrupt; + ( void ) prvTickISR; + + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the scheduler for the PIC port will get stopped + once running. If required disable the tick interrupt here, then return + to xPortStartScheduler(). */ +} +/*-----------------------------------------------------------*/ + +/* + * Manual context switch. This is similar to the tick context switch, + * but does not increment the tick count. It must be identical to the + * tick context switch in how it stores the stack of a task. + */ +void vPortYield( void ) +{ + /* This can get called with interrupts either enabled or disabled. We + will save the INTCON register with the interrupt enable bits unmodified. */ + portSAVE_CONTEXT( portINTERRUPTS_UNCHANGED ); + + /* Switch to the highest priority task that is ready to run. */ + vTaskSwitchContext(); + + /* Start executing the task we have just switched to. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * Vector for ISR. Nothing here must alter any registers! + */ +#pragma code high_vector=0x08 +static void prvLowInterrupt( void ) +{ + /* Was the interrupt the tick? */ + if( PIR1bits.CCP1IF ) + { + _asm + goto prvTickISR + _endasm + } + + /* Was the interrupt a byte being received? */ + if( PIR1bits.RCIF ) + { + _asm + goto vSerialRxISR + _endasm + } + + /* Was the interrupt the Tx register becoming empty? */ + if( PIR1bits.TXIF ) + { + if( PIE1bits.TXIE ) + { + _asm + goto vSerialTxISR + _endasm + } + } +} +#pragma code + +/*-----------------------------------------------------------*/ + +/* + * ISR for the tick. + * This increments the tick count and, if using the preemptive scheduler, + * performs a context switch. This must be identical to the manual + * context switch in how it stores the context of a task. + */ +static void prvTickISR( void ) +{ + /* Interrupts must have been enabled for the ISR to fire, so we have to + save the context with interrupts enabled. */ + portSAVE_CONTEXT( portGLOBAL_INTERRUPT_FLAG ); + PIR1bits.CCP1IF = 0; + + /* Maintain the tick count. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Switch to the highest priority task that is ready to run. */ + vTaskSwitchContext(); + } + + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +/* + * Setup a timer for a regular tick. + */ +static void prvSetupTimerInterrupt( void ) +{ +const uint32_t ulConstCompareValue = ( ( configCPU_CLOCK_HZ / portTIMER_FOSC_SCALE ) / configTICK_RATE_HZ ); +uint32_t ulCompareValue; +uint8_t ucByte; + + /* Interrupts are disabled when this function is called. + + Setup CCP1 to provide the tick interrupt using a compare match on timer + 1. + + Clear the time count then setup timer. */ + TMR1H = ( uint8_t ) 0x00; + TMR1L = ( uint8_t ) 0x00; + + /* Set the compare match value. */ + ulCompareValue = ulConstCompareValue; + CCPR1L = ( uint8_t ) ( ulCompareValue & ( uint32_t ) 0xff ); + ulCompareValue >>= ( uint32_t ) 8; + CCPR1H = ( uint8_t ) ( ulCompareValue & ( uint32_t ) 0xff ); + + CCP1CONbits.CCP1M0 = portBIT_SET; /*< Compare match mode. */ + CCP1CONbits.CCP1M1 = portBIT_SET; /*< Compare match mode. */ + CCP1CONbits.CCP1M2 = portBIT_CLEAR; /*< Compare match mode. */ + CCP1CONbits.CCP1M3 = portBIT_SET; /*< Compare match mode. */ + PIE1bits.CCP1IE = portBIT_SET; /*< Interrupt enable. */ + + /* We are only going to use the global interrupt bit, so set the peripheral + bit to true. */ + INTCONbits.GIEL = portBIT_SET; + + /* Provided library function for setting up the timer that will produce the + tick. */ + OpenTimer1( T1_16BIT_RW & T1_SOURCE_INT & T1_PS_1_1 & T1_CCP1_T3_CCP2 ); +} diff --git a/portable/MPLAB/PIC18F/portmacro.h b/portable/MPLAB/PIC18F/portmacro.h new file mode 100644 index 000000000..a0bfb44b5 --- /dev/null +++ b/portable/MPLAB/PIC18F/portmacro.h @@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE uint8_t +#define portBASE_TYPE char + +typedef portSTACK_TYPE StackType_t; +typedef signed char BaseType_t; +typedef unsigned char UBaseType_t; + +#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 1 +#define portGLOBAL_INT_ENABLE_BIT 0x80 +#define portSTACK_GROWTH 1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +#define portDISABLE_INTERRUPTS() INTCONbits.GIEH = 0; +#define portENABLE_INTERRUPTS() INTCONbits.GIEH = 1; + +/* Push the INTCON register onto the stack, then disable interrupts. */ +#define portENTER_CRITICAL() POSTINC1 = INTCON; \ + INTCONbits.GIEH = 0; + +/* Retrieve the INTCON register from the stack, and enable interrupts +if they were saved as being enabled. Don't modify any other bits +within the INTCON register as these may have legitimately have been +modified within the critical region. */ +#define portEXIT_CRITICAL() _asm \ + MOVF POSTDEC1, 1, 0 \ + _endasm \ + if( INDF1 & portGLOBAL_INT_ENABLE_BIT ) \ + { \ + portENABLE_INTERRUPTS(); \ + } +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +extern void vPortYield( void ); +#define portYIELD() vPortYield() +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +/*-----------------------------------------------------------*/ + +/* Required by the kernel aware debugger. */ +#ifdef __DEBUG + #define portREMOVE_STATIC_QUALIFIER +#endif + + +#define portNOP() _asm \ + NOP \ + _endasm + +#endif /* PORTMACRO_H */ diff --git a/Source/portable/MPLAB/PIC18F/stdio.h b/portable/MPLAB/PIC18F/stdio.h similarity index 100% rename from Source/portable/MPLAB/PIC18F/stdio.h rename to portable/MPLAB/PIC18F/stdio.h diff --git a/portable/MPLAB/PIC24_dsPIC/port.c b/portable/MPLAB/PIC24_dsPIC/port.c new file mode 100644 index 000000000..f309128e5 --- /dev/null +++ b/portable/MPLAB/PIC24_dsPIC/port.c @@ -0,0 +1,334 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + Changes from V4.2.1 + + + Introduced the configKERNEL_INTERRUPT_PRIORITY definition. +*/ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the PIC24 port. + *----------------------------------------------------------*/ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Hardware specifics. */ +#define portBIT_SET 1 +#define portTIMER_PRESCALE 8 +#define portINITIAL_SR 0 + +/* Defined for backward compatibility with project created prior to +FreeRTOS.org V4.3.0. */ +#ifndef configKERNEL_INTERRUPT_PRIORITY + #define configKERNEL_INTERRUPT_PRIORITY 1 +#endif + +/* Use _T1Interrupt as the interrupt handler name if the application writer has +not provided their own. */ +#ifndef configTICK_INTERRUPT_HANDLER + #define configTICK_INTERRUPT_HANDLER _T1Interrupt +#endif /* configTICK_INTERRUPT_HANDLER */ + +/* The program counter is only 23 bits. */ +#define portUNUSED_PR_BITS 0x7f + +/* Records the nesting depth of calls to portENTER_CRITICAL(). */ +UBaseType_t uxCriticalNesting = 0xef; + +#if configKERNEL_INTERRUPT_PRIORITY != 1 + #error If configKERNEL_INTERRUPT_PRIORITY is not 1 then the #32 in the following macros needs changing to equal the portINTERRUPT_BITS value, which is ( configKERNEL_INTERRUPT_PRIORITY << 5 ) +#endif + +#if defined( __PIC24E__ ) || defined ( __PIC24F__ ) || defined( __PIC24FK__ ) || defined( __PIC24H__ ) + + #ifdef __HAS_EDS__ + #define portRESTORE_CONTEXT() \ + asm volatile( "MOV _pxCurrentTCB, W0 \n" /* Restore the stack pointer for the task. */ \ + "MOV [W0], W15 \n" \ + "POP W0 \n" /* Restore the critical nesting counter for the task. */ \ + "MOV W0, _uxCriticalNesting \n" \ + "POP DSWPAG \n" \ + "POP DSRPAG \n" \ + "POP CORCON \n" \ + "POP TBLPAG \n" \ + "POP RCOUNT \n" /* Restore the registers from the stack. */ \ + "POP W14 \n" \ + "POP.D W12 \n" \ + "POP.D W10 \n" \ + "POP.D W8 \n" \ + "POP.D W6 \n" \ + "POP.D W4 \n" \ + "POP.D W2 \n" \ + "POP.D W0 \n" \ + "POP SR " ); + #else /* __HAS_EDS__ */ + #define portRESTORE_CONTEXT() \ + asm volatile( "MOV _pxCurrentTCB, W0 \n" /* Restore the stack pointer for the task. */ \ + "MOV [W0], W15 \n" \ + "POP W0 \n" /* Restore the critical nesting counter for the task. */ \ + "MOV W0, _uxCriticalNesting \n" \ + "POP PSVPAG \n" \ + "POP CORCON \n" \ + "POP TBLPAG \n" \ + "POP RCOUNT \n" /* Restore the registers from the stack. */ \ + "POP W14 \n" \ + "POP.D W12 \n" \ + "POP.D W10 \n" \ + "POP.D W8 \n" \ + "POP.D W6 \n" \ + "POP.D W4 \n" \ + "POP.D W2 \n" \ + "POP.D W0 \n" \ + "POP SR " ); + #endif /* __HAS_EDS__ */ +#endif /* defined( __PIC24E__ ) || defined ( __PIC24F__ ) || defined( __PIC24FK__ ) || defined( __PIC24H__ ) */ + +#if defined( __dsPIC30F__ ) || defined( __dsPIC33F__ ) + + #define portRESTORE_CONTEXT() \ + asm volatile( "MOV _pxCurrentTCB, W0 \n" /* Restore the stack pointer for the task. */ \ + "MOV [W0], W15 \n" \ + "POP W0 \n" /* Restore the critical nesting counter for the task. */ \ + "MOV W0, _uxCriticalNesting \n" \ + "POP PSVPAG \n" \ + "POP CORCON \n" \ + "POP DOENDH \n" \ + "POP DOENDL \n" \ + "POP DOSTARTH \n" \ + "POP DOSTARTL \n" \ + "POP DCOUNT \n" \ + "POP ACCBU \n" \ + "POP ACCBH \n" \ + "POP ACCBL \n" \ + "POP ACCAU \n" \ + "POP ACCAH \n" \ + "POP ACCAL \n" \ + "POP TBLPAG \n" \ + "POP RCOUNT \n" /* Restore the registers from the stack. */ \ + "POP W14 \n" \ + "POP.D W12 \n" \ + "POP.D W10 \n" \ + "POP.D W8 \n" \ + "POP.D W6 \n" \ + "POP.D W4 \n" \ + "POP.D W2 \n" \ + "POP.D W0 \n" \ + "POP SR " ); + +#endif /* defined( __dsPIC30F__ ) || defined( __dsPIC33F__ ) */ + +#ifndef portRESTORE_CONTEXT + #error Unrecognised device selected + + /* Note: dsPIC parts with EDS are not supported as there is no easy way to + recover the hardware stacked copies for DOCOUNT, DOHIGH, DOLOW. */ +#endif + +/* + * Setup the timer used to generate the tick interrupt. + */ +void vApplicationSetupTickTimerInterrupt( void ); + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +uint16_t usCode; +UBaseType_t i; + +const StackType_t xInitialStack[] = +{ + 0x1111, /* W1 */ + 0x2222, /* W2 */ + 0x3333, /* W3 */ + 0x4444, /* W4 */ + 0x5555, /* W5 */ + 0x6666, /* W6 */ + 0x7777, /* W7 */ + 0x8888, /* W8 */ + 0x9999, /* W9 */ + 0xaaaa, /* W10 */ + 0xbbbb, /* W11 */ + 0xcccc, /* W12 */ + 0xdddd, /* W13 */ + 0xeeee, /* W14 */ + 0xcdce, /* RCOUNT */ + 0xabac, /* TBLPAG */ + + /* dsPIC specific registers. */ + #if defined( __dsPIC30F__ ) || defined( __dsPIC33F__ ) + 0x0202, /* ACCAL */ + 0x0303, /* ACCAH */ + 0x0404, /* ACCAU */ + 0x0505, /* ACCBL */ + 0x0606, /* ACCBH */ + 0x0707, /* ACCBU */ + 0x0808, /* DCOUNT */ + 0x090a, /* DOSTARTL */ + 0x1010, /* DOSTARTH */ + 0x1110, /* DOENDL */ + 0x1212, /* DOENDH */ + #endif +}; + + /* Setup the stack as if a yield had occurred. + + Save the low bytes of the program counter. */ + usCode = ( uint16_t ) pxCode; + *pxTopOfStack = ( StackType_t ) usCode; + pxTopOfStack++; + + /* Save the high byte of the program counter. This will always be zero + here as it is passed in a 16bit pointer. If the address is greater than + 16 bits then the pointer will point to a jump table. */ + *pxTopOfStack = ( StackType_t ) 0; + pxTopOfStack++; + + /* Status register with interrupts enabled. */ + *pxTopOfStack = portINITIAL_SR; + pxTopOfStack++; + + /* Parameters are passed in W0. */ + *pxTopOfStack = ( StackType_t ) pvParameters; + pxTopOfStack++; + + for( i = 0; i < ( sizeof( xInitialStack ) / sizeof( StackType_t ) ); i++ ) + { + *pxTopOfStack = xInitialStack[ i ]; + pxTopOfStack++; + } + + *pxTopOfStack = CORCON; + pxTopOfStack++; + + #if defined(__HAS_EDS__) + *pxTopOfStack = DSRPAG; + pxTopOfStack++; + *pxTopOfStack = DSWPAG; + pxTopOfStack++; + #else /* __HAS_EDS__ */ + *pxTopOfStack = PSVPAG; + pxTopOfStack++; + #endif /* __HAS_EDS__ */ + + /* Finally the critical nesting depth. */ + *pxTopOfStack = 0x00; + pxTopOfStack++; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Setup a timer for the tick ISR. */ + vApplicationSetupTickTimerInterrupt(); + + /* Restore the context of the first task to run. */ + portRESTORE_CONTEXT(); + + /* Simulate the end of the yield function. */ + asm volatile ( "return" ); + + /* Should not reach here. */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +/* + * Setup a timer for a regular tick. + */ +__attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void ) +{ +const uint32_t ulCompareMatch = ( ( configCPU_CLOCK_HZ / portTIMER_PRESCALE ) / configTICK_RATE_HZ ) - 1; + + /* Prescale of 8. */ + T1CON = 0; + TMR1 = 0; + + PR1 = ( uint16_t ) ulCompareMatch; + + /* Setup timer 1 interrupt priority. */ + IPC0bits.T1IP = configKERNEL_INTERRUPT_PRIORITY; + + /* Clear the interrupt as a starting condition. */ + IFS0bits.T1IF = 0; + + /* Enable the interrupt. */ + IEC0bits.T1IE = 1; + + /* Setup the prescale value. */ + T1CONbits.TCKPS0 = 1; + T1CONbits.TCKPS1 = 0; + + /* Start the timer. */ + T1CONbits.TON = 1; +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void __attribute__((__interrupt__, auto_psv)) configTICK_INTERRUPT_HANDLER( void ) +{ + /* Clear the timer interrupt. */ + IFS0bits.T1IF = 0; + + if( xTaskIncrementTick() != pdFALSE ) + { + portYIELD(); + } +} +/*-----------------------------------------------------------*/ diff --git a/portable/MPLAB/PIC24_dsPIC/portasm_PIC24.S b/portable/MPLAB/PIC24_dsPIC/portasm_PIC24.S new file mode 100644 index 000000000..e2a7d6267 --- /dev/null +++ b/portable/MPLAB/PIC24_dsPIC/portasm_PIC24.S @@ -0,0 +1,93 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#if defined( __PIC24E__ ) || defined ( __PIC24F__ ) || defined( __PIC24FK__ ) || defined( __PIC24H__ ) + + .global _vPortYield + .extern _vTaskSwitchContext + .extern uxCriticalNesting + +_vPortYield: + + PUSH SR /* Save the SR used by the task.... */ + PUSH W0 /* ....then disable interrupts. */ + MOV #32, W0 + MOV W0, SR + PUSH W1 /* Save registers to the stack. */ + PUSH.D W2 + PUSH.D W4 + PUSH.D W6 + PUSH.D W8 + PUSH.D W10 + PUSH.D W12 + PUSH W14 + PUSH RCOUNT + PUSH TBLPAG + + PUSH CORCON + #ifdef __HAS_EDS__ + PUSH DSRPAG + PUSH DSWPAG + #else + PUSH PSVPAG + #endif /* __HAS_EDS__ */ + MOV _uxCriticalNesting, W0 /* Save the critical nesting counter for the task. */ + PUSH W0 + MOV _pxCurrentTCB, W0 /* Save the new top of stack into the TCB. */ + MOV W15, [W0] + + call _vTaskSwitchContext + + MOV _pxCurrentTCB, W0 /* Restore the stack pointer for the task. */ + MOV [W0], W15 + POP W0 /* Restore the critical nesting counter for the task. */ + MOV W0, _uxCriticalNesting + #ifdef __HAS_EDS__ + POP DSWPAG + POP DSRPAG + #else + POP PSVPAG + #endif /* __HAS_EDS__ */ + POP CORCON + POP TBLPAG + POP RCOUNT /* Restore the registers from the stack. */ + POP W14 + POP.D W12 + POP.D W10 + POP.D W8 + POP.D W6 + POP.D W4 + POP.D W2 + POP.D W0 + POP SR + + return + + .end + +#endif /* defined( __PIC24E__ ) || defined ( __PIC24F__ ) || defined( __PIC24FK__ ) || defined( __PIC24H__ ) */ diff --git a/portable/MPLAB/PIC24_dsPIC/portasm_dsPIC.S b/portable/MPLAB/PIC24_dsPIC/portasm_dsPIC.S new file mode 100644 index 000000000..ec1f070a4 --- /dev/null +++ b/portable/MPLAB/PIC24_dsPIC/portasm_dsPIC.S @@ -0,0 +1,106 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#if defined( __dsPIC30F__ ) || defined( __dsPIC33F__ ) + + .global _vPortYield + .extern _vTaskSwitchContext + .extern uxCriticalNesting + +_vPortYield: + + PUSH SR /* Save the SR used by the task.... */ + PUSH W0 /* ....then disable interrupts. */ + MOV #32, W0 + MOV W0, SR + PUSH W1 /* Save registers to the stack. */ + PUSH.D W2 + PUSH.D W4 + PUSH.D W6 + PUSH.D W8 + PUSH.D W10 + PUSH.D W12 + PUSH W14 + PUSH RCOUNT + PUSH TBLPAG + PUSH ACCAL + PUSH ACCAH + PUSH ACCAU + PUSH ACCBL + PUSH ACCBH + PUSH ACCBU + PUSH DCOUNT + PUSH DOSTARTL + PUSH DOSTARTH + PUSH DOENDL + PUSH DOENDH + + + PUSH CORCON + PUSH PSVPAG + MOV _uxCriticalNesting, W0 /* Save the critical nesting counter for the task. */ + PUSH W0 + MOV _pxCurrentTCB, W0 /* Save the new top of stack into the TCB. */ + MOV W15, [W0] + + call _vTaskSwitchContext + + MOV _pxCurrentTCB, W0 /* Restore the stack pointer for the task. */ + MOV [W0], W15 + POP W0 /* Restore the critical nesting counter for the task. */ + MOV W0, _uxCriticalNesting + POP PSVPAG + POP CORCON + POP DOENDH + POP DOENDL + POP DOSTARTH + POP DOSTARTL + POP DCOUNT + POP ACCBU + POP ACCBH + POP ACCBL + POP ACCAU + POP ACCAH + POP ACCAL + POP TBLPAG + POP RCOUNT /* Restore the registers from the stack. */ + POP W14 + POP.D W12 + POP.D W10 + POP.D W8 + POP.D W6 + POP.D W4 + POP.D W2 + POP.D W0 + POP SR + + return + + .end + +#endif /* defined( __dsPIC30F__ ) || defined( __dsPIC33F__ ) */ diff --git a/portable/MPLAB/PIC24_dsPIC/portmacro.h b/portable/MPLAB/PIC24_dsPIC/portmacro.h new file mode 100644 index 000000000..fbac471d5 --- /dev/null +++ b/portable/MPLAB/PIC24_dsPIC/portmacro.h @@ -0,0 +1,119 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint16_t +#define portBASE_TYPE short +#define portPOINTER_SIZE_TYPE size_t +#define SIZE_MAX ( ( size_t ) -1 ) + +typedef portSTACK_TYPE StackType_t; +typedef short BaseType_t; +typedef unsigned short UBaseType_t; + +#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +/* 16-bit tick type on a 16-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 2 +#define portSTACK_GROWTH 1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +#define portDISABLE_INTERRUPTS() SET_CPU_IPL( configKERNEL_INTERRUPT_PRIORITY ); __asm volatile ( "NOP" ) +#define portENABLE_INTERRUPTS() SET_CPU_IPL( 0 ) + +/* Note that exiting a critical sectino will set the IPL bits to 0, no matter +what their value was prior to entering the critical section. */ +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +extern void vPortYield( void ); +#define portYIELD() asm volatile ( "CALL _vPortYield \n" \ + "NOP " ); +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +/*-----------------------------------------------------------*/ + +/* Required by the kernel aware debugger. */ +#ifdef __DEBUG + #define portREMOVE_STATIC_QUALIFIER +#endif + +#define portNOP() asm volatile ( "NOP" ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/MPLAB/PIC32MEC14xx/ISR_Support.h b/portable/MPLAB/PIC32MEC14xx/ISR_Support.h new file mode 100644 index 000000000..ce7c4ad63 --- /dev/null +++ b/portable/MPLAB/PIC32MEC14xx/ISR_Support.h @@ -0,0 +1,214 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include "FreeRTOSConfig.h" + +#define portCONTEXT_SIZE 132 +#define portEPC_STACK_LOCATION 124 +#define portSTATUS_STACK_LOCATION 128 + +#ifdef __LANGUAGE_ASSEMBLY__ + +/******************************************************************/ +.macro portSAVE_CONTEXT + + /* Make room for the context. First save the current status so it can be + manipulated, and the cause and EPC registers so their original values are + captured. */ + mfc0 k0, _CP0_CAUSE + addiu sp, sp, -portCONTEXT_SIZE + mfc0 k1, _CP0_STATUS + + /* Also save s6 and s5 so they can be used. Any nesting interrupts should + maintain the values of these registers across the ISR. */ + sw s6, 44(sp) + sw s5, 40(sp) + sw k1, portSTATUS_STACK_LOCATION(sp) + + /* Prepare to enable interrupts above the current priority. + k0 = k0 >> 10. Moves RIPL[17:10] to [7:0] */ + srl k0, k0, 0xa + + /* Insert bit field. 7 bits k0[6:0] to k1[16:10] */ + ins k1, k0, 10, 7 + + /* Sets CP0.Status.IPL = CP0.Cause.RIPL + Copy the MSB of the IPL, but it would be an error if it was set anyway. */ + srl k0, k0, 0x7 + + /* MSB of IPL is bit[18] of CP0.Status */ + ins k1, k0, 18, 1 + + /* CP0.Status[5:1] = 0 b[5]=Rsvd, b[4]=UM, + b[3]=Rsvd, b[2]=ERL, b[1]=EXL + Setting EXL=0 allows higher priority interrupts + to preempt this handler */ + ins k1, zero, 1, 4 + + + /* s5 is used as the frame pointer. */ + add s5, zero, sp + + /* Check the nesting count value. */ + la k0, uxInterruptNesting + lw s6, (k0) + + /* If the nesting count is 0 then swap to the the system stack, otherwise + the system stack is already being used. */ + bne s6, zero, 1f + nop + + /* Swap to the system stack. */ + la sp, xISRStackTop + lw sp, (sp) + + /* Increment and save the nesting count. */ +1: addiu s6, s6, 1 + sw s6, 0(k0) + + /* s6 holds the EPC value, this is saved after interrupts are re-enabled. */ + mfc0 s6, _CP0_EPC + + /* Re-enable interrupts. */ + mtc0 k1, _CP0_STATUS + + /* Save the context into the space just created. s6 is saved again + here as it now contains the EPC value. No other s registers need be + saved. */ + sw ra, 120(s5) /* Return address (RA=R31) */ + sw s8, 116(s5) /* Frame Pointer (FP=R30) */ + sw t9, 112(s5) + sw t8, 108(s5) + sw t7, 104(s5) + sw t6, 100(s5) + sw t5, 96(s5) + sw t4, 92(s5) + sw t3, 88(s5) + sw t2, 84(s5) + sw t1, 80(s5) + sw t0, 76(s5) + sw a3, 72(s5) + sw a2, 68(s5) + sw a1, 64(s5) + sw a0, 60(s5) + sw v1, 56(s5) + sw v0, 52(s5) + sw s6, portEPC_STACK_LOCATION(s5) + sw $1, 16(s5) + + /* MEC14xx does not have DSP, removed 7 words */ + mfhi s6 + sw s6, 12(s5) + mflo s6 + sw s6, 8(s5) + + /* Update the task stack pointer value if nesting is zero. */ + la s6, uxInterruptNesting + lw s6, (s6) + addiu s6, s6, -1 + bne s6, zero, 1f + nop + + /* Save the stack pointer. */ + la s6, uxSavedTaskStackPointer + sw s5, (s6) +1: + .endm + +/******************************************************************/ +.macro portRESTORE_CONTEXT + + /* Restore the stack pointer from the TCB. This is only done if the + nesting count is 1. */ + la s6, uxInterruptNesting + lw s6, (s6) + addiu s6, s6, -1 + bne s6, zero, 1f + nop + la s6, uxSavedTaskStackPointer + lw s5, (s6) + + /* Restore the context. + MCHP MEC14xx does not include DSP */ +1: + lw s6, 8(s5) + mtlo s6 + lw s6, 12(s5) + mthi s6 + lw $1, 16(s5) + + /* s6 is loaded as it was used as a scratch register and therefore saved + as part of the interrupt context. */ + lw s6, 44(s5) + lw v0, 52(s5) + lw v1, 56(s5) + lw a0, 60(s5) + lw a1, 64(s5) + lw a2, 68(s5) + lw a3, 72(s5) + lw t0, 76(s5) + lw t1, 80(s5) + lw t2, 84(s5) + lw t3, 88(s5) + lw t4, 92(s5) + lw t5, 96(s5) + lw t6, 100(s5) + lw t7, 104(s5) + lw t8, 108(s5) + lw t9, 112(s5) + lw s8, 116(s5) + lw ra, 120(s5) + + /* Protect access to the k registers, and others. */ + di + ehb + + /* Decrement the nesting count. */ + la k0, uxInterruptNesting + lw k1, (k0) + addiu k1, k1, -1 + sw k1, 0(k0) + + lw k0, portSTATUS_STACK_LOCATION(s5) + lw k1, portEPC_STACK_LOCATION(s5) + + /* Leave the stack in its original state. First load sp from s5, then + restore s5 from the stack. */ + add sp, zero, s5 + lw s5, 40(sp) + addiu sp, sp, portCONTEXT_SIZE + + mtc0 k0, _CP0_STATUS + mtc0 k1, _CP0_EPC + ehb + eret + nop + + .endm + +#endif /* #ifdef __LANGUAGE_ASSEMBLY__ */ diff --git a/portable/MPLAB/PIC32MEC14xx/port.c b/portable/MPLAB/PIC32MEC14xx/port.c new file mode 100644 index 000000000..1f0d9cc03 --- /dev/null +++ b/portable/MPLAB/PIC32MEC14xx/port.c @@ -0,0 +1,341 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the PIC32MEC14xx port. + *----------------------------------------------------------*/ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Microchip includes. */ +#include +#include + +#if !defined(__MEC__) + #error This port is designed to work with XC32 on MEC14xx. Please update your C compiler version or settings. +#endif + +#if( ( configMAX_SYSCALL_INTERRUPT_PRIORITY >= 0x7 ) || ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) ) + #error configMAX_SYSCALL_INTERRUPT_PRIORITY must be less than 7 and greater than 0 +#endif + +/* Bits within various registers. */ +#define portIE_BIT ( 0x00000001 ) +#define portEXL_BIT ( 0x00000002 ) + +/* The EXL bit is set to ensure interrupts do not occur while the context of +the first task is being restored. MEC14xx does not have DSP HW. */ +#define portINITIAL_SR ( portIE_BIT | portEXL_BIT ) + +/* MEC14xx RTOS Timer MMCR's. */ +#define portMMCR_RTMR_PRELOAD *((volatile uint32_t *)(0xA0007404ul)) +#define portMMCR_RTMR_CONTROL *((volatile uint32_t *)(0xA0007408ul)) + +/* MEC14xx JTVIC external interrupt controller is mapped to M14K closely-coupled +peripheral space. */ +#define portGIRQ23_RTOS_TIMER_BITPOS ( 4 ) +#define portGIRQ23_RTOS_TIMER_MASK ( 1ul << ( portGIRQ23_RTOS_TIMER_BITPOS ) ) +#define portMMCR_JTVIC_GIRQ23_SRC *((volatile uint32_t *)(0xBFFFC0F0ul)) +#define portMMCR_JTVIC_GIRQ23_SETEN *((volatile uint32_t *)(0xBFFFC0F4ul)) +#define portMMCR_JTVIC_GIRQ23_PRIA *((volatile uint32_t *)(0xBFFFC3F0ul)) + +/* MIPS Software Interrupts are routed through JTVIC GIRQ24 */ +#define portGIRQ24_M14K_SOFTIRQ0_BITPOS ( 1 ) +#define portGIRQ24_M14K_SOFTIRQ0_MASK ( 1ul << ( portGIRQ24_M14K_SOFTIRQ0_BITPOS ) ) +#define portMMCR_JTVIC_GIRQ24_SRC *((volatile uint32_t *)(0xBFFFC100ul)) +#define portMMCR_JTVIC_GIRQ24_SETEN *((volatile uint32_t *)(0xBFFFC104ul)) +#define portMMCR_JTVIC_GIRQ24_PRIA *((volatile uint32_t *)(0xBFFFC400ul)) + +/* +By default port.c generates its tick interrupt from the RTOS timer. The user +can override this behaviour by: + 1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(), + which is the function that configures the timer. The function is defined + as a weak symbol in this file so if the same function name is used in the + application code then the version in the application code will be linked + into the application in preference to the version defined in this file. + 2: Provide a vector implementation in port_asm.S that overrides the default + behaviour for the specified interrupt vector. + 3: Specify the correct bit to clear the interrupt during the timer interrupt + handler. +*/ +#ifndef configTICK_INTERRUPT_VECTOR + #define configTICK_INTERRUPT_VECTOR girq23_b4 + #define configCLEAR_TICK_TIMER_INTERRUPT() portMMCR_JTVIC_GIRQ23_SRC = portGIRQ23_RTOS_TIMER_MASK +#else + #ifndef configCLEAR_TICK_TIMER_INTERRUPT + #error If configTICK_INTERRUPT_VECTOR is defined in application code then configCLEAR_TICK_TIMER_INTERRUPT must also be defined in application code. + #endif +#endif + +/* Let the user override the pre-loading of the initial RA with the address of +prvTaskExitError() in case it messes up unwinding of the stack in the debugger - +in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task +stack checking. A problem in the ISR stack will trigger an assert, not call the +stack overflow hook function (because the stack overflow hook is specific to a +task stack, not the ISR stack). */ +#if( configCHECK_FOR_STACK_OVERFLOW > 2 ) + + /* Don't use 0xa5 as the stack fill bytes as that is used by the kernel for + the task stacks, and so will legitimately appear in many positions within + the ISR stack. */ + #define portISR_STACK_FILL_BYTE 0xee + + static const uint8_t ucExpectedStackBytes[] = { + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE }; \ + + #define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) ) +#else + /* Define the function away. */ + #define portCHECK_ISR_STACK() +#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */ + + +/*-----------------------------------------------------------*/ + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* Records the interrupt nesting depth. This is initialised to one as it is +decremented to 0 when the first task starts. */ +volatile UBaseType_t uxInterruptNesting = 0x01; + +/* Stores the task stack pointer when a switch is made to use the system stack. */ +UBaseType_t uxSavedTaskStackPointer = 0; + +/* The stack used by interrupt service routines that cause a context switch. */ +StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 }; + +/* The top of stack value ensures there is enough space to store 6 registers on +the callers stack, as some functions seem to want to do this. */ +const StackType_t * const xISRStackTop = &( xISRStack[ configISR_STACK_SIZE - 7 ] ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* Ensure byte alignment is maintained when leaving this function. */ + pxTopOfStack--; + + *pxTopOfStack = (StackType_t) 0xDEADBEEF; + pxTopOfStack--; + + *pxTopOfStack = (StackType_t) 0x12345678; /* Word to which the stack pointer will be left pointing after context restore. */ + pxTopOfStack--; + + *pxTopOfStack = (StackType_t) ulPortGetCP0Cause(); + pxTopOfStack--; + + *pxTopOfStack = (StackType_t) portINITIAL_SR; /* CP0_STATUS */ + pxTopOfStack--; + + *pxTopOfStack = (StackType_t) pxCode; /* CP0_EPC */ + pxTopOfStack--; + + *pxTopOfStack = (StackType_t) portTASK_RETURN_ADDRESS; /* ra */ + pxTopOfStack -= 15; + + *pxTopOfStack = (StackType_t) pvParameters; /* Parameters to pass in. */ + pxTopOfStack -= 15; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static __inline uint32_t prvDisableInterrupt( void ) +{ +uint32_t prev_state; + + __asm volatile( "di %0; ehb" : "=r" ( prev_state ) :: "memory" ); + return prev_state; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + its caller as there is nothing to return to. If a task wants to exit it + should instead call vTaskDelete( NULL ). + + Artificially force an assert() to be triggered if configASSERT() is + defined, then stop here so application writers can catch the error. */ + configASSERT( uxSavedTaskStackPointer == 0UL ); + portDISABLE_INTERRUPTS(); + for( ;; ); +} +/*-----------------------------------------------------------*/ + +/* + * Setup a timer for a regular tick. This function uses the RTOS timer. + * The function is declared weak so an application writer can use a different + * timer by redefining this implementation. If a different timer is used then + * configTICK_INTERRUPT_VECTOR must also be defined in FreeRTOSConfig.h to + * ensure the RTOS provided tick interrupt handler is installed on the correct + * vector number. + */ +__attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void ) +{ +/* MEC14xx RTOS Timer whose input clock is 32KHz. */ +const uint32_t ulPreload = ( 32768ul / ( configTICK_RATE_HZ ) ); + + configASSERT( ulPreload != 0UL ); + + /* Configure the RTOS timer. */ + portMMCR_RTMR_CONTROL = 0ul; + portMMCR_RTMR_PRELOAD = ulPreload; + + /* Configure interrupts from the RTOS timer. */ + portMMCR_JTVIC_GIRQ23_SRC = ( portGIRQ23_RTOS_TIMER_MASK ); + portMMCR_JTVIC_GIRQ23_PRIA &= ~( 0x0Ful << 16 ); + portMMCR_JTVIC_GIRQ23_PRIA |= ( ( portIPL_TO_CODE( configKERNEL_INTERRUPT_PRIORITY ) ) << 16 ); + portMMCR_JTVIC_GIRQ23_SETEN = ( portGIRQ23_RTOS_TIMER_MASK ); + + /* Enable the RTOS timer. */ + portMMCR_RTMR_CONTROL = 0x0Fu; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler(void) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( uxInterruptNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void vPortStartFirstTask( void ); +extern void *pxCurrentTCB; + + #if ( configCHECK_FOR_STACK_OVERFLOW > 2 ) + { + /* Fill the ISR stack to make it easy to asses how much is being used. */ + memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) ); + } + #endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */ + + /* Clear the software interrupt flag. */ + portMMCR_JTVIC_GIRQ24_SRC = (portGIRQ24_M14K_SOFTIRQ0_MASK); + + /* Set software timer priority. Each GIRQn has one nibble containing its + priority */ + portMMCR_JTVIC_GIRQ24_PRIA &= ~(0xF0ul); + portMMCR_JTVIC_GIRQ24_PRIA |= ( portIPL_TO_CODE( configKERNEL_INTERRUPT_PRIORITY ) << 4 ); + + /* Enable software interrupt. */ + portMMCR_JTVIC_GIRQ24_SETEN = ( portGIRQ24_M14K_SOFTIRQ0_MASK ); + + /* Setup the timer to generate the tick. Interrupts will have been disabled + by the time we get here. */ + vApplicationSetupTickTimerInterrupt(); + + /* Start the highest priority task that has been created so far. Its stack + location is loaded into uxSavedTaskStackPointer. */ + uxSavedTaskStackPointer = *( UBaseType_t * ) pxCurrentTCB; + vPortStartFirstTask(); + + /* Should never get here as the tasks will now be executing! Call the task + exit error function to prevent compiler warnings about a static function + not being called in the case that the application writer overrides this + functionality by defining configTASK_RETURN_ADDRESS. */ + prvTaskExitError(); + + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +void vPortIncrementTick( void ) +{ +UBaseType_t uxSavedStatus; +uint32_t ulCause; + + uxSavedStatus = uxPortSetInterruptMaskFromISR(); + { + if( xTaskIncrementTick() != pdFALSE ) + { + /* Pend a context switch. */ + ulCause = ulPortGetCP0Cause(); + ulCause |= ( 1ul << 8UL ); + vPortSetCP0Cause( ulCause ); + } + } + vPortClearInterruptMaskFromISR( uxSavedStatus ); + + /* Look for the ISR stack getting near or past its limit. */ + portCHECK_ISR_STACK(); + + /* Clear timer interrupt. */ + configCLEAR_TICK_TIMER_INTERRUPT(); +} +/*-----------------------------------------------------------*/ + +UBaseType_t uxPortSetInterruptMaskFromISR( void ) +{ +UBaseType_t uxSavedStatusRegister; + + prvDisableInterrupt(); + uxSavedStatusRegister = ulPortGetCP0Status() | 0x01; + + /* This clears the IPL bits, then sets them to + configMAX_SYSCALL_INTERRUPT_PRIORITY. This function should not be called + from an interrupt that has a priority above + configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action + can only result in the IPL being unchanged or raised, and therefore never + lowered. */ + vPortSetCP0Status( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ); + + return uxSavedStatusRegister; +} +/*-----------------------------------------------------------*/ + +void vPortClearInterruptMaskFromISR( UBaseType_t uxSavedStatusRegister ) +{ + vPortSetCP0Status( uxSavedStatusRegister ); +} +/*-----------------------------------------------------------*/ diff --git a/portable/MPLAB/PIC32MEC14xx/port_asm.S b/portable/MPLAB/PIC32MEC14xx/port_asm.S new file mode 100644 index 000000000..b2c37f2db --- /dev/null +++ b/portable/MPLAB/PIC32MEC14xx/port_asm.S @@ -0,0 +1,345 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" +#include "ISR_Support.h" + +/* Microchip includes. */ +#include +#include + + .extern pxCurrentTCB + .extern vTaskSwitchContext + .extern vPortIncrementTick + .extern xISRStackTop + + PORT_CPP_JTVIC_BASE = 0xBFFFC000 + PORT_CCP_JTVIC_GIRQ24_SRC = 0xBFFFC100 + + .global vPortStartFirstTask .text + .global vPortYieldISR .text + .global vPortTickInterruptHandler .text + + +/******************************************************************/ + + +/*************************************************************** +* The following is needed to locate the +* vPortTickInterruptHandler function into the correct vector +* MEC14xx - This ISR will only be used if HW timers' interrupts +* in GIRQ23 are disaggregated. +* +***************************************************************/ + + .set noreorder + .set noat + .set micromips + + .section .text, code + .ent vPortTickInterruptHandler + +#if configTIMERS_DISAGGREGATED_ISRS == 0 + + .globl girq23_isr + +girq23_isr: +vPortTickInterruptHandler: + + portSAVE_CONTEXT + + jal girq23_handler + nop + + portRESTORE_CONTEXT + +.end vPortTickInterruptHandler + +#else + + .globl girq23_b4 + +girq23_b4: +vPortTickInterruptHandler: + + portSAVE_CONTEXT + + jal vPortIncrementTick + nop + + portRESTORE_CONTEXT + +.end vPortTickInterruptHandler + +#endif /* #if configTIMERS_DISAGGREGATED_ISRS == 0 */ + +/******************************************************************/ + + .set micromips + .set noreorder + .set noat + + .section .text, code + .ent vPortStartFirstTask + +vPortStartFirstTask: + + /* Simply restore the context of the highest priority task that has + been created so far. */ + portRESTORE_CONTEXT + +.end vPortStartFirstTask + + + +/*******************************************************************/ + +/*************************************************************** +* The following is needed to locate the vPortYieldISR function into the correct +* vector. +***************************************************************/ + + .set micromips + .set noreorder + .set noat + + .section .text, code + + .global vPortYieldISR + + +#if configCPU_DISAGGREGATED_ISRS == 0 + .global girq24_isr + .ent girq24_isr +girq24_isr: + la k0, PORT_CPP_JTVIC_BASE + lw k0, 0x10C(k0) + andi k1, k0, 0x2 + bgtz k1, vPortYieldISR + nop + + portSAVE_CONTEXT + + jal girq24_b_0_2 + + portRESTORE_CONTEXT + + .end girq24_isr + +#else + .global girq24_b1 +girq24_b1: +#endif + .ent vPortYieldISR +vPortYieldISR: + + /* Make room for the context. First save the current status so it can be + manipulated, and the cause and EPC registers so thier original values + are captured. */ + addiu sp, sp, -portCONTEXT_SIZE + mfc0 k1, _CP0_STATUS + + /* Also save s6 and s5 so they can be used. Any nesting interrupts should + maintain the values of these registers across the ISR. */ + sw s6, 44(sp) + sw s5, 40(sp) + sw k1, portSTATUS_STACK_LOCATION(sp) + + /* Prepare to re-enable interrupts above the kernel priority. */ + ins k1, zero, 10, 7 /* Clear IPL bits 0:6. */ + ins k1, zero, 18, 1 /* Clear IPL bit 7 */ + ori k1, k1, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) + ins k1, zero, 1, 4 /* Clear EXL, ERL and UM. */ + + /* s5 is used as the frame pointer. */ + add s5, zero, sp + + /* Swap to the system stack. This is not conditional on the nesting + count as this interrupt is always the lowest priority and therefore + the nesting is always 0. */ + la sp, xISRStackTop + lw sp, (sp) + + /* Set the nesting count. */ + la k0, uxInterruptNesting + addiu s6, zero, 1 + sw s6, 0(k0) + + /* s6 holds the EPC value, this is saved with the rest of the context + after interrupts are enabled. */ + mfc0 s6, _CP0_EPC + + /* Re-enable interrupts above configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + mtc0 k1, _CP0_STATUS + + /* Save the context into the space just created. s6 is saved again + here as it now contains the EPC value. */ + sw ra, 120(s5) + sw s8, 116(s5) + sw t9, 112(s5) + sw t8, 108(s5) + sw t7, 104(s5) + sw t6, 100(s5) + sw t5, 96(s5) + sw t4, 92(s5) + sw t3, 88(s5) + sw t2, 84(s5) + sw t1, 80(s5) + sw t0, 76(s5) + sw a3, 72(s5) + sw a2, 68(s5) + sw a1, 64(s5) + sw a0, 60(s5) + sw v1, 56(s5) + sw v0, 52(s5) + sw s7, 48(s5) + sw s6, portEPC_STACK_LOCATION(s5) + /* s5 and s6 has already been saved. */ + sw s4, 36(s5) + sw s3, 32(s5) + sw s2, 28(s5) + sw s1, 24(s5) + sw s0, 20(s5) + sw $1, 16(s5) + + /* s7 is used as a scratch register as this should always be saved acro ss + nesting interrupts. */ + mfhi s7 + sw s7, 12(s5) + mflo s7 + sw s7, 8(s5) + + /* Save the stack pointer to the task. */ + la s7, pxCurrentTCB + lw s7, (s7) + sw s5, (s7) + + /* Set the interrupt mask to the max priority that can use the API. + The yield handler will only be called at configKERNEL_INTERRUPT_PRIORITY + which is below configMAX_SYSCALL_INTERRUPT_PRIORITY - so this can only + ever raise the IPL value and never lower it. */ + di + ehb + mfc0 s7, _CP0_STATUS + ins s7, zero, 10, 7 + ins s7, zero, 18, 1 + ori s6, s7, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) | 1 + + /* This mtc0 re-enables interrupts, but only above + configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + mtc0 s6, _CP0_STATUS + ehb + + /* Clear the software interrupt in the core. */ + mfc0 s6, _CP0_CAUSE + ins s6, zero, 8, 1 + mtc0 s6, _CP0_CAUSE + ehb + + /* Clear the interrupt in the interrupt controller. + MEC14xx GIRQ24 Source bit[1] = 1 to clear */ + la s6, PORT_CCP_JTVIC_GIRQ24_SRC + addiu s4, zero, 2 + sw s4, (s6) + jal vTaskSwitchContext + nop + + /* Clear the interrupt mask again. The saved status value is still in s7 */ + mtc0 s7, _CP0_STATUS + ehb + + /* Restore the stack pointer from the TCB. */ + la s0, pxCurrentTCB + lw s0, (s0) + lw s5, (s0) + + /* Restore the rest of the context. */ + lw s0, 8(s5) + mtlo s0 + lw s0, 12(s5) + mthi s0 + + lw $1, 16(s5) + lw s0, 20(s5) + lw s1, 24(s5) + lw s2, 28(s5) + lw s3, 32(s5) + lw s4, 36(s5) + + /* s5 is loaded later. */ + lw s6, 44(s5) + lw s7, 48(s5) + lw v0, 52(s5) + lw v1, 56(s5) + lw a0, 60(s5) + lw a1, 64(s5) + lw a2, 68(s5) + lw a3, 72(s5) + lw t0, 76(s5) + lw t1, 80(s5) + lw t2, 84(s5) + lw t3, 88(s5) + lw t4, 92(s5) + lw t5, 96(s5) + lw t6, 100(s5) + lw t7, 104(s5) + lw t8, 108(s5) + lw t9, 112(s5) + lw s8, 116(s5) + lw ra, 120(s5) + + /* Protect access to the k registers, and others. */ + di + ehb + + /* Set nesting back to zero. As the lowest priority interrupt this + interrupt cannot have nested. */ + la k0, uxInterruptNesting + sw zero, 0(k0) + + /* Switch back to use the real stack pointer. */ + add sp, zero, s5 + + /* Restore the real s5 value. */ + lw s5, 40(sp) + + /* Pop the status and epc values. */ + lw k1, portSTATUS_STACK_LOCATION(sp) + lw k0, portEPC_STACK_LOCATION(sp) + + /* Remove stack frame. */ + addiu sp, sp, portCONTEXT_SIZE + + mtc0 k1, _CP0_STATUS + mtc0 k0, _CP0_EPC + ehb + eret + nop + +.end vPortYieldISR diff --git a/portable/MPLAB/PIC32MEC14xx/portmacro.h b/portable/MPLAB/PIC32MEC14xx/portmacro.h new file mode 100644 index 000000000..f431ae324 --- /dev/null +++ b/portable/MPLAB/PIC32MEC14xx/portmacro.h @@ -0,0 +1,267 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 8 +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +#define portIPL_SHIFT ( 10UL ) +/* Don't straddle the CEE bit. Interrupts calling FreeRTOS functions should +never have higher IPL bits set anyway. */ +#define portALL_IPL_BITS ( 0x7FUL << portIPL_SHIFT ) +#define portSW0_BIT ( 0x01 << 8 ) + +/* Interrupt priority conversion */ +#define portIPL_TO_CODE( iplNumber ) ( ( iplNumber >> 1 ) & 0x03ul ) +#define portCODE_TO_IPL( iplCode ) ( ( iplCode << 1 ) | 0x01ul ) + +/*-----------------------------------------------------------*/ + +static inline uint32_t ulPortGetCP0Status( void ) +{ +uint32_t rv; + + __asm volatile( + "\n\t" + "mfc0 %0,$12,0 \n\t" + : "=r" ( rv ) :: ); + + return rv; +} +/*-----------------------------------------------------------*/ + +static inline void vPortSetCP0Status( uint32_t new_status) +{ + ( void ) new_status; + + __asm__ __volatile__( + "\n\t" + "mtc0 %0,$12,0 \n\t" + "ehb \n\t" + : + :"r" ( new_status ) : ); +} +/*-----------------------------------------------------------*/ + +static inline uint32_t ulPortGetCP0Cause( void ) +{ +uint32_t rv; + + __asm volatile( + "\n\t" + "mfc0 %0,$13,0 \n\t" + : "=r" ( rv ) :: ); + + return rv; +} +/*-----------------------------------------------------------*/ + +static inline void vPortSetCP0Cause( uint32_t new_cause ) +{ + ( void ) new_cause; + + __asm__ __volatile__( + "\n\t" + "mtc0 %0,$13,0 \n\t" + "ehb \n\t" + : + :"r" ( new_cause ) : ); +} +/*-----------------------------------------------------------*/ + +/* This clears the IPL bits, then sets them to +configMAX_SYSCALL_INTERRUPT_PRIORITY. An extra check is performed if +configASSERT() is defined to ensure an assertion handler does not inadvertently +attempt to lower the IPL when the call to assert was triggered because the IPL +value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR +safe FreeRTOS API function was executed. ISR safe FreeRTOS API functions are +those that end in FromISR. FreeRTOS maintains a separate interrupt API to +ensure API function and interrupt entry is as fast and as simple as possible. */ +#if ( configASSERT_DEFINED == 1 ) + #define portDISABLE_INTERRUPTS() \ + { \ + uint32_t ulStatus; \ + /* Mask interrupts at and below the kernel interrupt priority. */ \ + ulStatus = ulPortGetCP0Status(); \ + /* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */ \ + if( ( ( ulStatus & portALL_IPL_BITS ) >> portIPL_SHIFT ) < configMAX_SYSCALL_INTERRUPT_PRIORITY ) \ + { \ + ulStatus &= ~portALL_IPL_BITS; \ + vPortSetCP0Status( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \ + } \ + } +#else /* configASSERT */ + #define portDISABLE_INTERRUPTS() \ + { \ + uint32_t ulStatus; \ + /* Mask interrupts at and below the kernel interrupt priority. */ \ + ulStatus = ulPortGetCP0Status(); \ + ulStatus &= ~portALL_IPL_BITS; \ + vPortSetCP0Status( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \ + } +#endif /* configASSERT */ + +#define portENABLE_INTERRUPTS() \ +{ \ +uint32_t ulStatus; \ + /* Unmask all interrupts. */ \ + ulStatus = ulPortGetCP0Status(); \ + ulStatus &= ~portALL_IPL_BITS; \ + vPortSetCP0Status( ulStatus ); \ +} + + +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); +#define portCRITICAL_NESTING_IN_TCB 1 +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() + +extern UBaseType_t uxPortSetInterruptMaskFromISR(); +extern void vPortClearInterruptMaskFromISR( UBaseType_t ); +#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister ) + +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + + /* Check the configuration. */ + #if( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + + /* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + + /*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - _clz( ( uxReadyPriorities ) ) ) + +#endif /* taskRECORD_READY_PRIORITY */ + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +#define portYIELD() \ +{ \ +uint32_t ulCause; \ + /* Trigger software interrupt. */ \ + ulCause = ulPortGetCP0Cause(); \ + ulCause |= portSW0_BIT; \ + vPortSetCP0Cause( ulCause ); \ +} + +extern volatile UBaseType_t uxInterruptNesting; +#define portASSERT_IF_IN_ISR() configASSERT( uxInterruptNesting == 0 ) + +#define portNOP() __asm volatile ( "nop" ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn)) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +/*-----------------------------------------------------------*/ + +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portYIELD(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) + +/* Required by the kernel aware debugger. */ +#ifdef __DEBUG + #define portREMOVE_STATIC_QUALIFIER +#endif + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/MPLAB/PIC32MX/ISR_Support.h b/portable/MPLAB/PIC32MX/ISR_Support.h new file mode 100644 index 000000000..0bff08fe1 --- /dev/null +++ b/portable/MPLAB/PIC32MX/ISR_Support.h @@ -0,0 +1,191 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include "FreeRTOSConfig.h" + +#define portCONTEXT_SIZE 132 +#define portEPC_STACK_LOCATION 124 +#define portSTATUS_STACK_LOCATION 128 + +/******************************************************************/ +.macro portSAVE_CONTEXT + + /* Make room for the context. First save the current status so it can be + manipulated, and the cause and EPC registers so their original values are + captured. */ + mfc0 k0, _CP0_CAUSE + addiu sp, sp, -portCONTEXT_SIZE + mfc0 k1, _CP0_STATUS + + /* Also save s6 and s5 so they can be used. Any nesting interrupts should + maintain the values of these registers across the ISR. */ + sw s6, 44(sp) + sw s5, 40(sp) + sw k1, portSTATUS_STACK_LOCATION(sp) + + /* Prepare to enable interrupts above the current priority. */ + srl k0, k0, 0xa + ins k1, k0, 10, 6 + ins k1, zero, 1, 4 + + /* s5 is used as the frame pointer. */ + add s5, zero, sp + + /* Check the nesting count value. */ + la k0, uxInterruptNesting + lw s6, (k0) + + /* If the nesting count is 0 then swap to the the system stack, otherwise + the system stack is already being used. */ + bne s6, zero, 1f + nop + + /* Swap to the system stack. */ + la sp, xISRStackTop + lw sp, (sp) + + /* Increment and save the nesting count. */ +1: addiu s6, s6, 1 + sw s6, 0(k0) + + /* s6 holds the EPC value, this is saved after interrupts are re-enabled. */ + mfc0 s6, _CP0_EPC + + /* Re-enable interrupts. */ + mtc0 k1, _CP0_STATUS + + /* Save the context into the space just created. s6 is saved again + here as it now contains the EPC value. No other s registers need be + saved. */ + sw ra, 120(s5) + sw s8, 116(s5) + sw t9, 112(s5) + sw t8, 108(s5) + sw t7, 104(s5) + sw t6, 100(s5) + sw t5, 96(s5) + sw t4, 92(s5) + sw t3, 88(s5) + sw t2, 84(s5) + sw t1, 80(s5) + sw t0, 76(s5) + sw a3, 72(s5) + sw a2, 68(s5) + sw a1, 64(s5) + sw a0, 60(s5) + sw v1, 56(s5) + sw v0, 52(s5) + sw s6, portEPC_STACK_LOCATION(s5) + sw $1, 16(s5) + + /* s6 is used as a scratch register. */ + mfhi s6 + sw s6, 12(s5) + mflo s6 + sw s6, 8(s5) + + /* Update the task stack pointer value if nesting is zero. */ + la s6, uxInterruptNesting + lw s6, (s6) + addiu s6, s6, -1 + bne s6, zero, 1f + nop + + /* Save the stack pointer. */ + la s6, uxSavedTaskStackPointer + sw s5, (s6) +1: + .endm + +/******************************************************************/ +.macro portRESTORE_CONTEXT + + /* Restore the stack pointer from the TCB. This is only done if the + nesting count is 1. */ + la s6, uxInterruptNesting + lw s6, (s6) + addiu s6, s6, -1 + bne s6, zero, 1f + nop + la s6, uxSavedTaskStackPointer + lw s5, (s6) + + /* Restore the context. */ +1: lw s6, 8(s5) + mtlo s6 + lw s6, 12(s5) + mthi s6 + lw $1, 16(s5) + /* s6 is loaded as it was used as a scratch register and therefore saved + as part of the interrupt context. */ + lw s6, 44(s5) + lw v0, 52(s5) + lw v1, 56(s5) + lw a0, 60(s5) + lw a1, 64(s5) + lw a2, 68(s5) + lw a3, 72(s5) + lw t0, 76(s5) + lw t1, 80(s5) + lw t2, 84(s5) + lw t3, 88(s5) + lw t4, 92(s5) + lw t5, 96(s5) + lw t6, 100(s5) + lw t7, 104(s5) + lw t8, 108(s5) + lw t9, 112(s5) + lw s8, 116(s5) + lw ra, 120(s5) + + /* Protect access to the k registers, and others. */ + di + ehb + + /* Decrement the nesting count. */ + la k0, uxInterruptNesting + lw k1, (k0) + addiu k1, k1, -1 + sw k1, 0(k0) + + lw k0, portSTATUS_STACK_LOCATION(s5) + lw k1, portEPC_STACK_LOCATION(s5) + + /* Leave the stack in its original state. First load sp from s5, then + restore s5 from the stack. */ + add sp, zero, s5 + lw s5, 40(sp) + addiu sp, sp, portCONTEXT_SIZE + + mtc0 k0, _CP0_STATUS + mtc0 k1, _CP0_EPC + ehb + eret + nop + + .endm diff --git a/portable/MPLAB/PIC32MX/port.c b/portable/MPLAB/PIC32MX/port.c new file mode 100644 index 000000000..582a600a3 --- /dev/null +++ b/portable/MPLAB/PIC32MX/port.c @@ -0,0 +1,330 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the PIC32MX port. + *----------------------------------------------------------*/ + +#ifndef __XC + #error This port is designed to work with XC32. Please update your C compiler version. +#endif + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Hardware specifics. */ +#define portTIMER_PRESCALE 8 +#define portPRESCALE_BITS 1 + +/* Bits within various registers. */ +#define portIE_BIT ( 0x00000001 ) +#define portEXL_BIT ( 0x00000002 ) + +/* Bits within the CAUSE register. */ +#define portCORE_SW_0 ( 0x00000100 ) +#define portCORE_SW_1 ( 0x00000200 ) + +/* The EXL bit is set to ensure interrupts do not occur while the context of +the first task is being restored. */ +#define portINITIAL_SR ( portIE_BIT | portEXL_BIT ) + +/* +By default port.c generates its tick interrupt from TIMER1. The user can +override this behaviour by: + 1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(), + which is the function that configures the timer. The function is defined + as a weak symbol in this file so if the same function name is used in the + application code then the version in the application code will be linked + into the application in preference to the version defined in this file. + 2: Define configTICK_INTERRUPT_VECTOR to the vector number of the timer used + to generate the tick interrupt. For example, when timer 1 is used then + configTICK_INTERRUPT_VECTOR is set to _TIMER_1_VECTOR. + configTICK_INTERRUPT_VECTOR should be defined in FreeRTOSConfig.h. + 3: Define configCLEAR_TICK_TIMER_INTERRUPT() to clear the interrupt in the + timer used to generate the tick interrupt. For example, when timer 1 is + used configCLEAR_TICK_TIMER_INTERRUPT() is defined to + IFS0CLR = _IFS0_T1IF_MASK. +*/ +#ifndef configTICK_INTERRUPT_VECTOR + #define configTICK_INTERRUPT_VECTOR _TIMER_1_VECTOR + #define configCLEAR_TICK_TIMER_INTERRUPT() IFS0CLR = _IFS0_T1IF_MASK +#else + #ifndef configCLEAR_TICK_TIMER_INTERRUPT + #error If configTICK_INTERRUPT_VECTOR is defined in application code then configCLEAR_TICK_TIMER_INTERRUPT must also be defined in application code. + #endif +#endif + +/* Let the user override the pre-loading of the initial RA with the address of +prvTaskExitError() in case it messes up unwinding of the stack in the +debugger - in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task +stack checking. A problem in the ISR stack will trigger an assert, not call the +stack overflow hook function (because the stack overflow hook is specific to a +task stack, not the ISR stack). */ +#if( configCHECK_FOR_STACK_OVERFLOW > 2 ) + + /* Don't use 0xa5 as the stack fill bytes as that is used by the kernel for + the task stacks, and so will legitimately appear in many positions within + the ISR stack. */ + #define portISR_STACK_FILL_BYTE 0xee + + static const uint8_t ucExpectedStackBytes[] = { + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE }; \ + + #define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) ) +#else + /* Define the function away. */ + #define portCHECK_ISR_STACK() +#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */ + +/*-----------------------------------------------------------*/ + + +/* + * Place the prototype here to ensure the interrupt vector is correctly installed. + * Note that because the interrupt is written in assembly, the IPL setting in the + * following line of code has no effect. The interrupt priority is set by the + * call to ConfigIntTimer1() in vApplicationSetupTickTimerInterrupt(). + */ +extern void __attribute__( (interrupt(IPL1AUTO), vector( configTICK_INTERRUPT_VECTOR ))) vPortTickInterruptHandler( void ); + +/* + * The software interrupt handler that performs the yield. Note that, because + * the interrupt is written in assembly, the IPL setting in the following line of + * code has no effect. The interrupt priority is set by the call to + * mConfigIntCoreSW0() in xPortStartScheduler(). + */ +void __attribute__( (interrupt(IPL1AUTO), vector(_CORE_SOFTWARE_0_VECTOR))) vPortYieldISR( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* Records the interrupt nesting depth. This is initialised to one as it is +decremented to 0 when the first task starts. */ +volatile UBaseType_t uxInterruptNesting = 0x01; + +/* Stores the task stack pointer when a switch is made to use the system stack. */ +UBaseType_t uxSavedTaskStackPointer = 0; + +/* The stack used by interrupt service routines that cause a context switch. */ +__attribute__ ((aligned(8))) StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 }; + +/* The top of stack value ensures there is enough space to store 6 registers on +the callers stack, as some functions seem to want to do this. */ +const StackType_t * const xISRStackTop = &( xISRStack[ ( configISR_STACK_SIZE & ~portBYTE_ALIGNMENT_MASK ) - 8 ] ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* Ensure 8 byte alignment is maintained when the context is popped from + * stack. The size of the context is 33 words (132 bytes). */ + pxTopOfStack--; + pxTopOfStack--; + + *pxTopOfStack = (StackType_t) 0xDEADBEEF; + pxTopOfStack--; + + *pxTopOfStack = (StackType_t) 0x12345678; /* Word to which the stack pointer will be left pointing after context restore. */ + pxTopOfStack--; + + *pxTopOfStack = (StackType_t) _CP0_GET_CAUSE(); + pxTopOfStack--; + + *pxTopOfStack = (StackType_t) portINITIAL_SR;/* CP0_STATUS */ + pxTopOfStack--; + + *pxTopOfStack = (StackType_t) pxCode; /* CP0_EPC */ + pxTopOfStack--; + + *pxTopOfStack = (StackType_t) portTASK_RETURN_ADDRESS; /* ra */ + pxTopOfStack -= 15; + + *pxTopOfStack = (StackType_t) pvParameters; /* Parameters to pass in. */ + pxTopOfStack -= 15; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + its caller as there is nothing to return to. If a task wants to exit it + should instead call vTaskDelete( NULL ). + + Artificially force an assert() to be triggered if configASSERT() is + defined, then stop here so application writers can catch the error. */ + configASSERT( uxSavedTaskStackPointer == 0UL ); + portDISABLE_INTERRUPTS(); + for( ;; ); +} +/*-----------------------------------------------------------*/ + +/* + * Setup a timer for a regular tick. This function uses peripheral timer 1. + * The function is declared weak so an application writer can use a different + * timer by redefining this implementation. If a different timer is used then + * configTICK_INTERRUPT_VECTOR must also be defined in FreeRTOSConfig.h to + * ensure the RTOS provided tick interrupt handler is installed on the correct + * vector number. When Timer 1 is used the vector number is defined as + * _TIMER_1_VECTOR. + */ +__attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void ) +{ +const uint32_t ulCompareMatch = ( (configPERIPHERAL_CLOCK_HZ / portTIMER_PRESCALE) / configTICK_RATE_HZ ) - 1; + + T1CON = 0x0000; + T1CONbits.TCKPS = portPRESCALE_BITS; + PR1 = ulCompareMatch; + IPC1bits.T1IP = configKERNEL_INTERRUPT_PRIORITY; + + /* Clear the interrupt as a starting condition. */ + IFS0bits.T1IF = 0; + + /* Enable the interrupt. */ + IEC0bits.T1IE = 1; + + /* Start the timer. */ + T1CONbits.TON = 1; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler(void) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( uxInterruptNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void vPortStartFirstTask( void ); +extern void *pxCurrentTCB; + + #if ( configCHECK_FOR_STACK_OVERFLOW > 2 ) + { + /* Fill the ISR stack to make it easy to asses how much is being used. */ + memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) ); + } + #endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */ + + /* Clear the software interrupt flag. */ + IFS0CLR = _IFS0_CS0IF_MASK; + + /* Set software timer priority. */ + IPC0CLR = _IPC0_CS0IP_MASK; + IPC0SET = ( configKERNEL_INTERRUPT_PRIORITY << _IPC0_CS0IP_POSITION ); + + /* Enable software interrupt. */ + IEC0CLR = _IEC0_CS0IE_MASK; + IEC0SET = 1 << _IEC0_CS0IE_POSITION; + + /* Setup the timer to generate the tick. Interrupts will have been + disabled by the time we get here. */ + vApplicationSetupTickTimerInterrupt(); + + /* Kick off the highest priority task that has been created so far. + Its stack location is loaded into uxSavedTaskStackPointer. */ + uxSavedTaskStackPointer = *( UBaseType_t * ) pxCurrentTCB; + vPortStartFirstTask(); + + /* Should never get here as the tasks will now be executing! Call the task + exit error function to prevent compiler warnings about a static function + not being called in the case that the application writer overrides this + functionality by defining configTASK_RETURN_ADDRESS. */ + prvTaskExitError(); + + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +void vPortIncrementTick( void ) +{ +UBaseType_t uxSavedStatus; + + uxSavedStatus = uxPortSetInterruptMaskFromISR(); + { + if( xTaskIncrementTick() != pdFALSE ) + { + /* Pend a context switch. */ + _CP0_BIS_CAUSE( portCORE_SW_0 ); + } + } + vPortClearInterruptMaskFromISR( uxSavedStatus ); + + /* Look for the ISR stack getting near or past its limit. */ + portCHECK_ISR_STACK(); + + /* Clear timer interrupt. */ + configCLEAR_TICK_TIMER_INTERRUPT(); +} +/*-----------------------------------------------------------*/ + +UBaseType_t uxPortSetInterruptMaskFromISR( void ) +{ +UBaseType_t uxSavedStatusRegister; + + __builtin_disable_interrupts(); + uxSavedStatusRegister = _CP0_GET_STATUS() | 0x01; + /* This clears the IPL bits, then sets them to + configMAX_SYSCALL_INTERRUPT_PRIORITY. This function should not be called + from an interrupt that has a priority above + configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action + can only result in the IPL being unchanged or raised, and therefore never + lowered. */ + _CP0_SET_STATUS( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ); + + return uxSavedStatusRegister; +} +/*-----------------------------------------------------------*/ + +void vPortClearInterruptMaskFromISR( UBaseType_t uxSavedStatusRegister ) +{ + _CP0_SET_STATUS( uxSavedStatusRegister ); +} +/*-----------------------------------------------------------*/ diff --git a/portable/MPLAB/PIC32MX/port_asm.S b/portable/MPLAB/PIC32MX/port_asm.S new file mode 100644 index 000000000..4e00324eb --- /dev/null +++ b/portable/MPLAB/PIC32MX/port_asm.S @@ -0,0 +1,266 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include +#include +#include "ISR_Support.h" + + + .set nomips16 + .set noreorder + + .extern pxCurrentTCB + .extern vTaskSwitchContext + .extern vPortIncrementTick + .extern xISRStackTop + + .global vPortStartFirstTask + .global vPortYieldISR + .global vPortTickInterruptHandler + + +/******************************************************************/ + + .set noreorder + .set noat + .ent vPortTickInterruptHandler + +vPortTickInterruptHandler: + + portSAVE_CONTEXT + + jal vPortIncrementTick + nop + + portRESTORE_CONTEXT + + .end vPortTickInterruptHandler + +/******************************************************************/ + + .set noreorder + .set noat + .ent vPortStartFirstTask + +vPortStartFirstTask: + + /* Simply restore the context of the highest priority task that has been + created so far. */ + portRESTORE_CONTEXT + + .end vPortStartFirstTask + + + +/*******************************************************************/ + + .set noreorder + .set noat + .ent vPortYieldISR + +vPortYieldISR: + + /* Make room for the context. First save the current status so it can be + manipulated. */ + addiu sp, sp, -portCONTEXT_SIZE + mfc0 k1, _CP0_STATUS + + /* Also save s6 and s5 so they can be used. Any nesting interrupts should + maintain the values of these registers across the ISR. */ + sw s6, 44(sp) + sw s5, 40(sp) + sw k1, portSTATUS_STACK_LOCATION(sp) + + /* Prepare to re-enabled interrupt above the kernel priority. */ + ins k1, zero, 10, 6 + ori k1, k1, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) + ins k1, zero, 1, 4 + + /* s5 is used as the frame pointer. */ + add s5, zero, sp + + /* Swap to the system stack. This is not conditional on the nesting + count as this interrupt is always the lowest priority and therefore + the nesting is always 0. */ + la sp, xISRStackTop + lw sp, (sp) + + /* Set the nesting count. */ + la k0, uxInterruptNesting + addiu s6, zero, 1 + sw s6, 0(k0) + + /* s6 holds the EPC value, this is saved with the rest of the context + after interrupts are enabled. */ + mfc0 s6, _CP0_EPC + + /* Re-enable interrupts above configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + mtc0 k1, _CP0_STATUS + + /* Save the context into the space just created. s6 is saved again + here as it now contains the EPC value. */ + sw ra, 120(s5) + sw s8, 116(s5) + sw t9, 112(s5) + sw t8, 108(s5) + sw t7, 104(s5) + sw t6, 100(s5) + sw t5, 96(s5) + sw t4, 92(s5) + sw t3, 88(s5) + sw t2, 84(s5) + sw t1, 80(s5) + sw t0, 76(s5) + sw a3, 72(s5) + sw a2, 68(s5) + sw a1, 64(s5) + sw a0, 60(s5) + sw v1, 56(s5) + sw v0, 52(s5) + sw s7, 48(s5) + sw s6, portEPC_STACK_LOCATION(s5) + /* s5 and s6 has already been saved. */ + sw s4, 36(s5) + sw s3, 32(s5) + sw s2, 28(s5) + sw s1, 24(s5) + sw s0, 20(s5) + sw $1, 16(s5) + + /* s7 is used as a scratch register as this should always be saved across + nesting interrupts. */ + mfhi s7 + sw s7, 12(s5) + mflo s7 + sw s7, 8(s5) + + /* Save the stack pointer to the task. */ + la s7, pxCurrentTCB + lw s7, (s7) + sw s5, (s7) + + /* Set the interrupt mask to the max priority that can use the API. The + yield handler will only be called at configKERNEL_INTERRUPT_PRIORITY which + is below configMAX_SYSCALL_INTERRUPT_PRIORITY - so this can only ever + raise the IPL value and never lower it. */ + di + ehb + mfc0 s7, _CP0_STATUS + ins s7, zero, 10, 6 + ori s6, s7, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) | 1 + + /* This mtc0 re-enables interrupts, but only above + configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + mtc0 s6, _CP0_STATUS + ehb + + /* Clear the software interrupt in the core. */ + mfc0 s6, _CP0_CAUSE + ins s6, zero, 8, 1 + mtc0 s6, _CP0_CAUSE + ehb + + /* Clear the interrupt in the interrupt controller. */ + la s6, IFS0CLR + addiu s4, zero, 2 + sw s4, (s6) + + jal vTaskSwitchContext + nop + + /* Clear the interrupt mask again. The saved status value is still in s7. */ + mtc0 s7, _CP0_STATUS + ehb + + /* Restore the stack pointer from the TCB. */ + la s0, pxCurrentTCB + lw s0, (s0) + lw s5, (s0) + + /* Restore the rest of the context. */ + lw s0, 8(s5) + mtlo s0 + lw s0, 12(s5) + mthi s0 + lw $1, 16(s5) + lw s0, 20(s5) + lw s1, 24(s5) + lw s2, 28(s5) + lw s3, 32(s5) + lw s4, 36(s5) + /* s5 is loaded later. */ + lw s6, 44(s5) + lw s7, 48(s5) + lw v0, 52(s5) + lw v1, 56(s5) + lw a0, 60(s5) + lw a1, 64(s5) + lw a2, 68(s5) + lw a3, 72(s5) + lw t0, 76(s5) + lw t1, 80(s5) + lw t2, 84(s5) + lw t3, 88(s5) + lw t4, 92(s5) + lw t5, 96(s5) + lw t6, 100(s5) + lw t7, 104(s5) + lw t8, 108(s5) + lw t9, 112(s5) + lw s8, 116(s5) + lw ra, 120(s5) + + /* Protect access to the k registers, and others. */ + di + ehb + + /* Set nesting back to zero. As the lowest priority interrupt this + interrupt cannot have nested. */ + la k0, uxInterruptNesting + sw zero, 0(k0) + + /* Switch back to use the real stack pointer. */ + add sp, zero, s5 + + /* Restore the real s5 value. */ + lw s5, 40(sp) + + /* Pop the status and epc values. */ + lw k1, portSTATUS_STACK_LOCATION(sp) + lw k0, portEPC_STACK_LOCATION(sp) + + /* Remove stack frame. */ + addiu sp, sp, portCONTEXT_SIZE + + mtc0 k1, _CP0_STATUS + mtc0 k0, _CP0_EPC + ehb + eret + nop + + .end vPortYieldISR diff --git a/portable/MPLAB/PIC32MX/portmacro.h b/portable/MPLAB/PIC32MX/portmacro.h new file mode 100644 index 000000000..7868dcb8c --- /dev/null +++ b/portable/MPLAB/PIC32MX/portmacro.h @@ -0,0 +1,219 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* System include files */ +#include + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 8 +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +#define portIPL_SHIFT ( 10UL ) +#define portALL_IPL_BITS ( 0x3fUL << portIPL_SHIFT ) +#define portSW0_BIT ( 0x01 << 8 ) + +/* This clears the IPL bits, then sets them to +configMAX_SYSCALL_INTERRUPT_PRIORITY. An extra check is performed if +configASSERT() is defined to ensure an assertion handler does not inadvertently +attempt to lower the IPL when the call to assert was triggered because the IPL +value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR +safe FreeRTOS API function was executed. ISR safe FreeRTOS API functions are +those that end in FromISR. FreeRTOS maintains a separate interrupt API to +ensure API function and interrupt entry is as fast and as simple as possible. */ +#if ( configASSERT_DEFINED == 1 ) + #define portDISABLE_INTERRUPTS() \ + { \ + uint32_t ulStatus; \ + \ + /* Mask interrupts at and below the kernel interrupt priority. */ \ + ulStatus = _CP0_GET_STATUS(); \ + \ + /* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */ \ + if( ( ( ulStatus & portALL_IPL_BITS ) >> portIPL_SHIFT ) < configMAX_SYSCALL_INTERRUPT_PRIORITY ) \ + { \ + ulStatus &= ~portALL_IPL_BITS; \ + _CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \ + } \ + } +#else /* configASSERT */ + #define portDISABLE_INTERRUPTS() \ + { \ + uint32_t ulStatus; \ + \ + /* Mask interrupts at and below the kernel interrupt priority. */ \ + ulStatus = _CP0_GET_STATUS(); \ + ulStatus &= ~portALL_IPL_BITS; \ + _CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \ + } +#endif /* configASSERT */ + +#define portENABLE_INTERRUPTS() \ +{ \ +uint32_t ulStatus; \ + \ + /* Unmask all interrupts. */ \ + ulStatus = _CP0_GET_STATUS(); \ + ulStatus &= ~portALL_IPL_BITS; \ + _CP0_SET_STATUS( ulStatus ); \ +} + + +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); +#define portCRITICAL_NESTING_IN_TCB 1 +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() + +extern UBaseType_t uxPortSetInterruptMaskFromISR(); +extern void vPortClearInterruptMaskFromISR( UBaseType_t ); +#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister ) + +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + + /* Check the configuration. */ + #if( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + + /* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + + /*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - _clz( ( uxReadyPriorities ) ) ) + +#endif /* taskRECORD_READY_PRIORITY */ + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +#define portYIELD() \ +{ \ +uint32_t ulCause; \ + \ + /* Trigger software interrupt. */ \ + ulCause = _CP0_GET_CAUSE(); \ + ulCause |= portSW0_BIT; \ + _CP0_SET_CAUSE( ulCause ); \ +} + +extern volatile UBaseType_t uxInterruptNesting; +#define portASSERT_IF_IN_ISR() configASSERT( uxInterruptNesting == 0 ) + +#define portNOP() __asm volatile ( "nop" ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn)) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +/*-----------------------------------------------------------*/ + +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portYIELD(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) + +/* Required by the kernel aware debugger. */ +#ifdef __DEBUG + #define portREMOVE_STATIC_QUALIFIER +#endif + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/MPLAB/PIC32MZ/ISR_Support.h b/portable/MPLAB/PIC32MZ/ISR_Support.h new file mode 100644 index 000000000..292877f42 --- /dev/null +++ b/portable/MPLAB/PIC32MZ/ISR_Support.h @@ -0,0 +1,432 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include "FreeRTOSConfig.h" + +#define portCONTEXT_SIZE 160 +#define portEPC_STACK_LOCATION 152 +#define portSTATUS_STACK_LOCATION 156 +#define portFPCSR_STACK_LOCATION 0 +#define portTASK_HAS_FPU_STACK_LOCATION 0 +#define portFPU_CONTEXT_SIZE 264 + +/******************************************************************/ +.macro portSAVE_FPU_REGS offset, base + /* Macro to assist with saving just the FPU registers to the + * specified address and base offset, + * offset is a constant, base is the base pointer register */ + + sdc1 $f31, \offset + 248(\base) + sdc1 $f30, \offset + 240(\base) + sdc1 $f29, \offset + 232(\base) + sdc1 $f28, \offset + 224(\base) + sdc1 $f27, \offset + 216(\base) + sdc1 $f26, \offset + 208(\base) + sdc1 $f25, \offset + 200(\base) + sdc1 $f24, \offset + 192(\base) + sdc1 $f23, \offset + 184(\base) + sdc1 $f22, \offset + 176(\base) + sdc1 $f21, \offset + 168(\base) + sdc1 $f20, \offset + 160(\base) + sdc1 $f19, \offset + 152(\base) + sdc1 $f18, \offset + 144(\base) + sdc1 $f17, \offset + 136(\base) + sdc1 $f16, \offset + 128(\base) + sdc1 $f15, \offset + 120(\base) + sdc1 $f14, \offset + 112(\base) + sdc1 $f13, \offset + 104(\base) + sdc1 $f12, \offset + 96(\base) + sdc1 $f11, \offset + 88(\base) + sdc1 $f10, \offset + 80(\base) + sdc1 $f9, \offset + 72(\base) + sdc1 $f8, \offset + 64(\base) + sdc1 $f7, \offset + 56(\base) + sdc1 $f6, \offset + 48(\base) + sdc1 $f5, \offset + 40(\base) + sdc1 $f4, \offset + 32(\base) + sdc1 $f3, \offset + 24(\base) + sdc1 $f2, \offset + 16(\base) + sdc1 $f1, \offset + 8(\base) + sdc1 $f0, \offset + 0(\base) + + .endm + +/******************************************************************/ +.macro portLOAD_FPU_REGS offset, base + /* Macro to assist with loading just the FPU registers from the + * specified address and base offset, offset is a constant, + * base is the base pointer register */ + + ldc1 $f0, \offset + 0(\base) + ldc1 $f1, \offset + 8(\base) + ldc1 $f2, \offset + 16(\base) + ldc1 $f3, \offset + 24(\base) + ldc1 $f4, \offset + 32(\base) + ldc1 $f5, \offset + 40(\base) + ldc1 $f6, \offset + 48(\base) + ldc1 $f7, \offset + 56(\base) + ldc1 $f8, \offset + 64(\base) + ldc1 $f9, \offset + 72(\base) + ldc1 $f10, \offset + 80(\base) + ldc1 $f11, \offset + 88(\base) + ldc1 $f12, \offset + 96(\base) + ldc1 $f13, \offset + 104(\base) + ldc1 $f14, \offset + 112(\base) + ldc1 $f15, \offset + 120(\base) + ldc1 $f16, \offset + 128(\base) + ldc1 $f17, \offset + 136(\base) + ldc1 $f18, \offset + 144(\base) + ldc1 $f19, \offset + 152(\base) + ldc1 $f20, \offset + 160(\base) + ldc1 $f21, \offset + 168(\base) + ldc1 $f22, \offset + 176(\base) + ldc1 $f23, \offset + 184(\base) + ldc1 $f24, \offset + 192(\base) + ldc1 $f25, \offset + 200(\base) + ldc1 $f26, \offset + 208(\base) + ldc1 $f27, \offset + 216(\base) + ldc1 $f28, \offset + 224(\base) + ldc1 $f29, \offset + 232(\base) + ldc1 $f30, \offset + 240(\base) + ldc1 $f31, \offset + 248(\base) + + .endm + +/******************************************************************/ +.macro portSAVE_CONTEXT + + /* Make room for the context. First save the current status so it can be + manipulated, and the cause and EPC registers so their original values are + captured. */ + mfc0 k0, _CP0_CAUSE + addiu sp, sp, -portCONTEXT_SIZE + + #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) + /* Test if we are already using the system stack. Only tasks may use the + FPU so if we are already in a nested interrupt then the FPU context does + not require saving. */ + la k1, uxInterruptNesting + lw k1, 0(k1) + bne k1, zero, 2f + nop + + /* Test if the current task needs the FPU context saving. */ + la k1, ulTaskHasFPUContext + lw k1, 0(k1) + beq k1, zero, 1f + nop + + /* Adjust the stack to account for the additional FPU context.*/ + addiu sp, sp, -portFPU_CONTEXT_SIZE + + 1: + /* Save the ulTaskHasFPUContext flag. */ + sw k1, portTASK_HAS_FPU_STACK_LOCATION(sp) + + 2: + #endif + + mfc0 k1, _CP0_STATUS + + /* Also save s7, s6 and s5 so they can be used. Any nesting interrupts + should maintain the values of these registers across the ISR. */ + sw s7, 48(sp) + sw s6, 44(sp) + sw s5, 40(sp) + sw k1, portSTATUS_STACK_LOCATION(sp) + + /* Prepare to enable interrupts above the current priority. */ + srl k0, k0, 0xa + ins k1, k0, 10, 7 + srl k0, k0, 0x7 /* This copies the MSB of the IPL, but it would be an error if it was set anyway. */ + ins k1, k0, 18, 1 + ins k1, zero, 1, 4 + + /* s5 is used as the frame pointer. */ + add s5, zero, sp + + /* Check the nesting count value. */ + la k0, uxInterruptNesting + lw s6, (k0) + + /* If the nesting count is 0 then swap to the the system stack, otherwise + the system stack is already being used. */ + bne s6, zero, 1f + nop + + /* Swap to the system stack. */ + la sp, xISRStackTop + lw sp, (sp) + + /* Increment and save the nesting count. */ +1: addiu s6, s6, 1 + sw s6, 0(k0) + + /* s6 holds the EPC value, this is saved after interrupts are re-enabled. */ + mfc0 s6, _CP0_EPC + + /* Re-enable interrupts. */ + mtc0 k1, _CP0_STATUS + + /* Save the context into the space just created. s6 is saved again + here as it now contains the EPC value. No other s registers need be + saved. */ + sw ra, 120(s5) + sw s8, 116(s5) + sw t9, 112(s5) + sw t8, 108(s5) + sw t7, 104(s5) + sw t6, 100(s5) + sw t5, 96(s5) + sw t4, 92(s5) + sw t3, 88(s5) + sw t2, 84(s5) + sw t1, 80(s5) + sw t0, 76(s5) + sw a3, 72(s5) + sw a2, 68(s5) + sw a1, 64(s5) + sw a0, 60(s5) + sw v1, 56(s5) + sw v0, 52(s5) + sw s6, portEPC_STACK_LOCATION(s5) + sw $1, 16(s5) + + /* Save the AC0, AC1, AC2, AC3 registers from the DSP. s6 is used as a + scratch register. */ + mfhi s6, $ac1 + sw s6, 128(s5) + mflo s6, $ac1 + sw s6, 124(s5) + + mfhi s6, $ac2 + sw s6, 136(s5) + mflo s6, $ac2 + sw s6, 132(s5) + + mfhi s6, $ac3 + sw s6, 144(s5) + mflo s6, $ac3 + sw s6, 140(s5) + + /* Save the DSP Control register */ + rddsp s6 + sw s6, 148(s5) + + /* ac0 is done separately to match the MX port. */ + mfhi s6, $ac0 + sw s6, 12(s5) + mflo s6, $ac0 + sw s6, 8(s5) + + /* Save the FPU context if the nesting count was zero. */ + #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) + la s6, uxInterruptNesting + lw s6, 0(s6) + addiu s6, s6, -1 + bne s6, zero, 1f + nop + + /* Test if the current task needs the FPU context saving. */ + lw s6, portTASK_HAS_FPU_STACK_LOCATION(s5) + beq s6, zero, 1f + nop + + /* Save the FPU registers. */ + portSAVE_FPU_REGS ( portCONTEXT_SIZE + 8 ), s5 + + /* Save the FPU status register */ + cfc1 s6, $f31 + sw s6, (portCONTEXT_SIZE + portFPCSR_STACK_LOCATION)(s5) + + 1: + #endif + + /* Update the task stack pointer value if nesting is zero. */ + la s6, uxInterruptNesting + lw s6, (s6) + addiu s6, s6, -1 + bne s6, zero, 1f + nop + + /* Save the stack pointer. */ + la s6, uxSavedTaskStackPointer + sw s5, (s6) +1: + .endm + +/******************************************************************/ +.macro portRESTORE_CONTEXT + + /* Restore the stack pointer from the TCB. This is only done if the + nesting count is 1. */ + la s6, uxInterruptNesting + lw s6, (s6) + addiu s6, s6, -1 + bne s6, zero, 1f + nop + la s6, uxSavedTaskStackPointer + lw s5, (s6) + + #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) + /* Restore the FPU context if required. */ + lw s6, portTASK_HAS_FPU_STACK_LOCATION(s5) + beq s6, zero, 1f + nop + + /* Restore the FPU registers. */ + portLOAD_FPU_REGS ( portCONTEXT_SIZE + 8 ), s5 + + /* Restore the FPU status register. */ + lw s6, ( portCONTEXT_SIZE + portFPCSR_STACK_LOCATION )(s5) + ctc1 s6, $f31 + #endif + +1: + + /* Restore the context. */ + lw s6, 128(s5) + mthi s6, $ac1 + lw s6, 124(s5) + mtlo s6, $ac1 + + lw s6, 136(s5) + mthi s6, $ac2 + lw s6, 132(s5) + mtlo s6, $ac2 + + lw s6, 144(s5) + mthi s6, $ac3 + lw s6, 140(s5) + mtlo s6, $ac3 + + /* Restore DSPControl. */ + lw s6, 148(s5) + wrdsp s6 + + lw s6, 8(s5) + mtlo s6, $ac0 + lw s6, 12(s5) + mthi s6, $ac0 + lw $1, 16(s5) + + /* s6 is loaded as it was used as a scratch register and therefore saved + as part of the interrupt context. */ + lw s7, 48(s5) + lw s6, 44(s5) + lw v0, 52(s5) + lw v1, 56(s5) + lw a0, 60(s5) + lw a1, 64(s5) + lw a2, 68(s5) + lw a3, 72(s5) + lw t0, 76(s5) + lw t1, 80(s5) + lw t2, 84(s5) + lw t3, 88(s5) + lw t4, 92(s5) + lw t5, 96(s5) + lw t6, 100(s5) + lw t7, 104(s5) + lw t8, 108(s5) + lw t9, 112(s5) + lw s8, 116(s5) + lw ra, 120(s5) + + /* Protect access to the k registers, and others. */ + di + ehb + + /* Decrement the nesting count. */ + la k0, uxInterruptNesting + lw k1, (k0) + addiu k1, k1, -1 + sw k1, 0(k0) + + #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) + /* If the nesting count is now zero then the FPU context may be restored. */ + bne k1, zero, 1f + nop + + /* Restore the value of ulTaskHasFPUContext */ + la k0, ulTaskHasFPUContext + lw k1, 0(s5) + sw k1, 0(k0) + + /* If the task does not have an FPU context then adjust the stack normally. */ + beq k1, zero, 1f + nop + + /* Restore the STATUS and EPC registers */ + lw k0, portSTATUS_STACK_LOCATION(s5) + lw k1, portEPC_STACK_LOCATION(s5) + + /* Leave the stack in its original state. First load sp from s5, then + restore s5 from the stack. */ + add sp, zero, s5 + lw s5, 40(sp) + + /* Adjust the stack pointer to remove the FPU context */ + addiu sp, sp, portFPU_CONTEXT_SIZE + beq zero, zero, 2f + nop + + 1: /* Restore the STATUS and EPC registers */ + lw k0, portSTATUS_STACK_LOCATION(s5) + lw k1, portEPC_STACK_LOCATION(s5) + + /* Leave the stack in its original state. First load sp from s5, then + restore s5 from the stack. */ + add sp, zero, s5 + lw s5, 40(sp) + + 2: /* Adjust the stack pointer */ + addiu sp, sp, portCONTEXT_SIZE + + #else + + /* Restore the frame when there is no hardware FP support. */ + lw k0, portSTATUS_STACK_LOCATION(s5) + lw k1, portEPC_STACK_LOCATION(s5) + + /* Leave the stack in its original state. First load sp from s5, then + restore s5 from the stack. */ + add sp, zero, s5 + lw s5, 40(sp) + + addiu sp, sp, portCONTEXT_SIZE + + #endif // ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) + + mtc0 k0, _CP0_STATUS + mtc0 k1, _CP0_EPC + ehb + eret + nop + + .endm diff --git a/portable/MPLAB/PIC32MZ/port.c b/portable/MPLAB/PIC32MZ/port.c new file mode 100644 index 000000000..4af1fb832 --- /dev/null +++ b/portable/MPLAB/PIC32MZ/port.c @@ -0,0 +1,374 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the PIC32MZ port. + *----------------------------------------------------------*/ + +/* Microchip specific headers. */ +#include + +/* Standard headers. */ +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +#if !defined(__PIC32MZ__) + #error This port is designed to work with XC32 on PIC32MZ MCUs. Please update your C compiler version or settings. +#endif + +#if( ( configMAX_SYSCALL_INTERRUPT_PRIORITY >= 0x7 ) || ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) ) + #error configMAX_SYSCALL_INTERRUPT_PRIORITY must be less than 7 and greater than 0 +#endif + +/* Hardware specifics. */ +#define portTIMER_PRESCALE 8 +#define portPRESCALE_BITS 1 + +/* Bits within various registers. */ +#define portIE_BIT ( 0x00000001 ) +#define portEXL_BIT ( 0x00000002 ) +#define portMX_BIT ( 0x01000000 ) /* Allow access to DSP instructions. */ +#define portCU1_BIT ( 0x20000000 ) /* enable CP1 for parts with hardware. */ +#define portFR_BIT ( 0x04000000 ) /* Enable 64 bit floating point registers. */ + +/* Bits within the CAUSE register. */ +#define portCORE_SW_0 ( 0x00000100 ) +#define portCORE_SW_1 ( 0x00000200 ) + +/* The EXL bit is set to ensure interrupts do not occur while the context of +the first task is being restored. */ +#if ( __mips_hard_float == 1 ) + #define portINITIAL_SR ( portIE_BIT | portEXL_BIT | portMX_BIT | portFR_BIT | portCU1_BIT ) +#else + #define portINITIAL_SR ( portIE_BIT | portEXL_BIT | portMX_BIT ) +#endif + +/* The initial value to store into the FPU status and control register. This is + only used on parts that support a hardware FPU. */ +#define portINITIAL_FPSCR (0x1000000) /* High perf on denormal ops */ + + +/* +By default port.c generates its tick interrupt from TIMER1. The user can +override this behaviour by: + 1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(), + which is the function that configures the timer. The function is defined + as a weak symbol in this file so if the same function name is used in the + application code then the version in the application code will be linked + into the application in preference to the version defined in this file. + 2: Define configTICK_INTERRUPT_VECTOR to the vector number of the timer used + to generate the tick interrupt. For example, when timer 1 is used then + configTICK_INTERRUPT_VECTOR is set to _TIMER_1_VECTOR. + configTICK_INTERRUPT_VECTOR should be defined in FreeRTOSConfig.h. + 3: Define configCLEAR_TICK_TIMER_INTERRUPT() to clear the interrupt in the + timer used to generate the tick interrupt. For example, when timer 1 is + used configCLEAR_TICK_TIMER_INTERRUPT() is defined to + IFS0CLR = _IFS0_T1IF_MASK. +*/ +#ifndef configTICK_INTERRUPT_VECTOR + #define configTICK_INTERRUPT_VECTOR _TIMER_1_VECTOR + #define configCLEAR_TICK_TIMER_INTERRUPT() IFS0CLR = _IFS0_T1IF_MASK +#else + #ifndef configCLEAR_TICK_TIMER_INTERRUPT + #error If configTICK_INTERRUPT_VECTOR is defined in application code then configCLEAR_TICK_TIMER_INTERRUPT must also be defined in application code. + #endif +#endif + +/* Let the user override the pre-loading of the initial RA with the address of +prvTaskExitError() in case it messes up unwinding of the stack in the +debugger - in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task +stack checking. A problem in the ISR stack will trigger an assert, not call the +stack overflow hook function (because the stack overflow hook is specific to a +task stack, not the ISR stack). */ +#if( configCHECK_FOR_STACK_OVERFLOW > 2 ) + + /* Don't use 0xa5 as the stack fill bytes as that is used by the kernel for + the task stacks, and so will legitimately appear in many positions within + the ISR stack. */ + #define portISR_STACK_FILL_BYTE 0xee + + static const uint8_t ucExpectedStackBytes[] = { + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \ + portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE }; \ + + #define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) ) +#else + /* Define the function away. */ + #define portCHECK_ISR_STACK() +#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */ + +/*-----------------------------------------------------------*/ + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* Records the interrupt nesting depth. This is initialised to one as it is +decremented to 0 when the first task starts. */ +volatile UBaseType_t uxInterruptNesting = 0x01; + +/* Stores the task stack pointer when a switch is made to use the system stack. */ +UBaseType_t uxSavedTaskStackPointer = 0; + +/* The stack used by interrupt service routines that cause a context switch. */ +__attribute__ ((aligned(8))) StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 }; + +/* The top of stack value ensures there is enough space to store 6 registers on +the callers stack, as some functions seem to want to do this. 8 byte alignment +is required to allow double word floating point stack pushes generated by the +compiler. */ +const StackType_t * const xISRStackTop = &( xISRStack[ ( configISR_STACK_SIZE & ~portBYTE_ALIGNMENT_MASK ) - 8 ] ); + +/* Saved as part of the task context. Set to pdFALSE if the task does not + require an FPU context. */ +#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) + uint32_t ulTaskHasFPUContext = 0; +#endif + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* Ensure 8 byte alignment is maintained when leaving this function. */ + pxTopOfStack--; + pxTopOfStack--; + + *pxTopOfStack = (StackType_t) 0xDEADBEEF; + pxTopOfStack--; + + *pxTopOfStack = (StackType_t) 0x12345678; /* Word to which the stack pointer will be left pointing after context restore. */ + pxTopOfStack--; + + *pxTopOfStack = (StackType_t) _CP0_GET_CAUSE(); + pxTopOfStack--; + + *pxTopOfStack = (StackType_t) portINITIAL_SR;/* CP0_STATUS */ + pxTopOfStack--; + + *pxTopOfStack = (StackType_t) pxCode; /* CP0_EPC */ + pxTopOfStack--; + + *pxTopOfStack = (StackType_t) 0x00000000; /* DSPControl */ + pxTopOfStack -= 7; /* Includes space for AC1 - AC3. */ + + *pxTopOfStack = (StackType_t) portTASK_RETURN_ADDRESS; /* ra */ + pxTopOfStack -= 15; + + *pxTopOfStack = (StackType_t) pvParameters; /* Parameters to pass in. */ + pxTopOfStack -= 15; + + *pxTopOfStack = (StackType_t) pdFALSE; /*by default disable FPU context save on parts with FPU */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + its caller as there is nothing to return to. If a task wants to exit it + should instead call vTaskDelete( NULL ). + + Artificially force an assert() to be triggered if configASSERT() is + defined, then stop here so application writers can catch the error. */ + configASSERT( uxSavedTaskStackPointer == 0UL ); + portDISABLE_INTERRUPTS(); + for( ;; ); +} +/*-----------------------------------------------------------*/ + +/* + * Setup a timer for a regular tick. This function uses peripheral timer 1. + * The function is declared weak so an application writer can use a different + * timer by redefining this implementation. If a different timer is used then + * configTICK_INTERRUPT_VECTOR must also be defined in FreeRTOSConfig.h to + * ensure the RTOS provided tick interrupt handler is installed on the correct + * vector number. When Timer 1 is used the vector number is defined as + * _TIMER_1_VECTOR. + */ +__attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void ) +{ +const uint32_t ulCompareMatch = ( (configPERIPHERAL_CLOCK_HZ / portTIMER_PRESCALE) / configTICK_RATE_HZ ) - 1UL; + + /* PR1 is 16-bit. Ensure that the configPERIPHERAL_CLOCK_HZ and + * configTICK_RATE_HZ are defined such that ulCompareMatch value would fit + * in 16-bits. */ + configASSERT( ( ulCompareMatch & 0xFFFF0000 ) == 0 ); + + T1CON = 0x0000; + T1CONbits.TCKPS = portPRESCALE_BITS; + PR1 = ulCompareMatch; + IPC1bits.T1IP = configKERNEL_INTERRUPT_PRIORITY; + + /* Clear the interrupt as a starting condition. */ + IFS0bits.T1IF = 0; + + /* Enable the interrupt. */ + IEC0bits.T1IE = 1; + + /* Start the timer. */ + T1CONbits.TON = 1; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler(void) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( uxInterruptNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void vPortStartFirstTask( void ); +extern void *pxCurrentTCB; + + #if ( configCHECK_FOR_STACK_OVERFLOW > 2 ) + { + /* Fill the ISR stack to make it easy to asses how much is being used. */ + memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) ); + } + #endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */ + + /* Clear the software interrupt flag. */ + IFS0CLR = _IFS0_CS0IF_MASK; + + /* Set software timer priority. */ + IPC0CLR = _IPC0_CS0IP_MASK; + IPC0SET = ( configKERNEL_INTERRUPT_PRIORITY << _IPC0_CS0IP_POSITION ); + + /* Enable software interrupt. */ + IEC0CLR = _IEC0_CS0IE_MASK; + IEC0SET = 1 << _IEC0_CS0IE_POSITION; + + /* Setup the timer to generate the tick. Interrupts will have been + disabled by the time we get here. */ + vApplicationSetupTickTimerInterrupt(); + + /* Kick off the highest priority task that has been created so far. + Its stack location is loaded into uxSavedTaskStackPointer. */ + uxSavedTaskStackPointer = *( UBaseType_t * ) pxCurrentTCB; + vPortStartFirstTask(); + + /* Should never get here as the tasks will now be executing! Call the task + exit error function to prevent compiler warnings about a static function + not being called in the case that the application writer overrides this + functionality by defining configTASK_RETURN_ADDRESS. */ + prvTaskExitError(); + + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +void vPortIncrementTick( void ) +{ +UBaseType_t uxSavedStatus; + + uxSavedStatus = uxPortSetInterruptMaskFromISR(); + { + if( xTaskIncrementTick() != pdFALSE ) + { + /* Pend a context switch. */ + _CP0_BIS_CAUSE( portCORE_SW_0 ); + } + } + vPortClearInterruptMaskFromISR( uxSavedStatus ); + + /* Look for the ISR stack getting near or past its limit. */ + portCHECK_ISR_STACK(); + + /* Clear timer interrupt. */ + configCLEAR_TICK_TIMER_INTERRUPT(); +} +/*-----------------------------------------------------------*/ + +UBaseType_t uxPortSetInterruptMaskFromISR( void ) +{ +UBaseType_t uxSavedStatusRegister; + + __builtin_disable_interrupts(); + uxSavedStatusRegister = _CP0_GET_STATUS() | 0x01; + /* This clears the IPL bits, then sets them to + configMAX_SYSCALL_INTERRUPT_PRIORITY. This function should not be called + from an interrupt that has a priority above + configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action + can only result in the IPL being unchanged or raised, and therefore never + lowered. */ + _CP0_SET_STATUS( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ); + + return uxSavedStatusRegister; +} +/*-----------------------------------------------------------*/ + +void vPortClearInterruptMaskFromISR( UBaseType_t uxSavedStatusRegister ) +{ + _CP0_SET_STATUS( uxSavedStatusRegister ); +} +/*-----------------------------------------------------------*/ + +#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) + + void vPortTaskUsesFPU(void) + { + extern void vPortInitialiseFPSCR( uint32_t uxFPSCRInit ); + + portENTER_CRITICAL(); + + /* Initialise the floating point status register. */ + vPortInitialiseFPSCR(portINITIAL_FPSCR); + + /* A task is registering the fact that it needs a FPU context. Set the + FPU flag (saved as part of the task context). */ + ulTaskHasFPUContext = pdTRUE; + + portEXIT_CRITICAL(); + } + +#endif /* __mips_hard_float == 1 */ + +/*-----------------------------------------------------------*/ diff --git a/portable/MPLAB/PIC32MZ/port_asm.S b/portable/MPLAB/PIC32MZ/port_asm.S new file mode 100644 index 000000000..78cb14165 --- /dev/null +++ b/portable/MPLAB/PIC32MZ/port_asm.S @@ -0,0 +1,765 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include +#include +#include "FreeRTOSConfig.h" +#include "ISR_Support.h" + + .extern pxCurrentTCB + .extern vTaskSwitchContext + .extern vPortIncrementTick + .extern xISRStackTop + .extern ulTaskHasFPUContext + + .global vPortStartFirstTask + .global vPortYieldISR + .global vPortTickInterruptHandler + .global vPortInitialiseFPSCR + + +/******************************************************************/ + + .set nomips16 + .set nomicromips + .set noreorder + .set noat + + /*************************************************************** + * The following is needed to locate the + * vPortTickInterruptHandler function into the correct vector + ***************************************************************/ + #ifdef configTICK_INTERRUPT_VECTOR + #if (configTICK_INTERRUPT_VECTOR == _CORE_TIMER_VECTOR) + .equ __vector_dispatch_0, vPortTickInterruptHandler + .global __vector_dispatch_0 + .section .vector_0, code, keep + #elif (configTICK_INTERRUPT_VECTOR == _TIMER_1_VECTOR) + .equ __vector_dispatch_4, vPortTickInterruptHandler + .global __vector_dispatch_4 + .section .vector_4, code, keep + #elif (configTICK_INTERRUPT_VECTOR == _TIMER_2_VECTOR) + .equ __vector_dispatch_9, vPortTickInterruptHandler + .global __vector_dispatch_9 + .section .vector_9, code, keep + #elif (configTICK_INTERRUPT_VECTOR == _TIMER_3_VECTOR) + .equ __vector_dispatch_14, vPortTickInterruptHandler + .global __vector_dispatch_14 + .section .vector_14, code, keep + #elif (configTICK_INTERRUPT_VECTOR == _TIMER_4_VECTOR) + .equ __vector_dispatch_19, vPortTickInterruptHandler + .global __vector_dispatch_19 + .section .vector_19, code, keep + #elif (configTICK_INTERRUPT_VECTOR == _TIMER_5_VECTOR) + .equ __vector_dispatch_24, vPortTickInterruptHandler + .global __vector_dispatch_24 + .section .vector_24, code, keep + #elif (configTICK_INTERRUPT_VECTOR == _TIMER_6_VECTOR) + .equ __vector_dispatch_28, vPortTickInterruptHandler + .global __vector_dispatch_28 + .section .vector_28, code, keep + #elif (configTICK_INTERRUPT_VECTOR == _TIMER_7_VECTOR) + .equ __vector_dispatch_32, vPortTickInterruptHandler + .global __vector_dispatch_32 + .section .vector_32, code, keep + #elif (configTICK_INTERRUPT_VECTOR == _TIMER_8_VECTOR) + .equ __vector_dispatch_36, vPortTickInterruptHandler + .global __vector_dispatch_36 + .section .vector_36, code, keep + #elif (configTICK_INTERRUPT_VECTOR == _TIMER_9_VECTOR) + .equ __vector_dispatch_40, vPortTickInterruptHandler + .global __vector_dispatch_40 + .section .vector_40, code, keep + #endif + #else + .equ __vector_dispatch_4, vPortTickInterruptHandler + .global __vector_dispatch_4 + .section .vector_4, code, keep + #endif + + .ent vPortTickInterruptHandler + +vPortTickInterruptHandler: + + portSAVE_CONTEXT + + jal vPortIncrementTick + nop + + portRESTORE_CONTEXT + + .end vPortTickInterruptHandler + +/******************************************************************/ + + .set noreorder + .set noat + .section .text, code + .ent vPortStartFirstTask + +vPortStartFirstTask: + + /* Simply restore the context of the highest priority task that has been + created so far. */ + portRESTORE_CONTEXT + + .end vPortStartFirstTask + + + +/*******************************************************************/ + + .set nomips16 + .set nomicromips + .set noreorder + .set noat + /*************************************************************** + * The following is needed to locate the vPortYieldISR function + * into the correct vector + ***************************************************************/ + .equ __vector_dispatch_1, vPortYieldISR + .global __vector_dispatch_1 + .section .vector_1, code + + .ent vPortYieldISR +vPortYieldISR: + + #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) + /* Code sequence for FPU support, the context save requires advance + knowledge of the stack frame size and if the current task actually uses the + FPU. */ + + /* Make room for the context. First save the current status so it can be + manipulated, and the cause and EPC registers so their original values are + captured. */ + la k0, ulTaskHasFPUContext + lw k0, 0(k0) + beq k0, zero, 1f + addiu sp, sp, -portCONTEXT_SIZE /* always reserve space for the context. */ + addiu sp, sp, -portFPU_CONTEXT_SIZE /* reserve additional space for the FPU context. */ + 1: + mfc0 k1, _CP0_STATUS + + /* Also save s6 and s5 so they can be used. Any nesting interrupts should + maintain the values of these registers across the ISR. */ + sw s6, 44(sp) + sw s5, 40(sp) + sw k1, portSTATUS_STACK_LOCATION(sp) + sw k0, portTASK_HAS_FPU_STACK_LOCATION(sp) + + /* Prepare to re-enabled interrupts above the kernel priority. */ + ins k1, zero, 10, 7 /* Clear IPL bits 0:6. */ + ins k1, zero, 18, 1 /* Clear IPL bit 7. It would be an error here if this bit were set anyway. */ + ori k1, k1, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) + ins k1, zero, 1, 4 /* Clear EXL, ERL and UM. */ + + /* s5 is used as the frame pointer. */ + add s5, zero, sp + + /* Swap to the system stack. This is not conditional on the nesting + count as this interrupt is always the lowest priority and therefore + the nesting is always 0. */ + la sp, xISRStackTop + lw sp, (sp) + + /* Set the nesting count. */ + la k0, uxInterruptNesting + addiu s6, zero, 1 + sw s6, 0(k0) + + /* s6 holds the EPC value, this is saved with the rest of the context + after interrupts are enabled. */ + mfc0 s6, _CP0_EPC + + /* Re-enable interrupts above configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + mtc0 k1, _CP0_STATUS + + /* Save the context into the space just created. s6 is saved again + here as it now contains the EPC value. */ + sw ra, 120(s5) + sw s8, 116(s5) + sw t9, 112(s5) + sw t8, 108(s5) + sw t7, 104(s5) + sw t6, 100(s5) + sw t5, 96(s5) + sw t4, 92(s5) + sw t3, 88(s5) + sw t2, 84(s5) + sw t1, 80(s5) + sw t0, 76(s5) + sw a3, 72(s5) + sw a2, 68(s5) + sw a1, 64(s5) + sw a0, 60(s5) + sw v1, 56(s5) + sw v0, 52(s5) + sw s7, 48(s5) + sw s6, portEPC_STACK_LOCATION(s5) + /* s5 and s6 has already been saved. */ + sw s4, 36(s5) + sw s3, 32(s5) + sw s2, 28(s5) + sw s1, 24(s5) + sw s0, 20(s5) + sw $1, 16(s5) + + /* s7 is used as a scratch register as this should always be saved across + nesting interrupts. */ + + /* Save the AC0, AC1, AC2 and AC3. */ + mfhi s7, $ac1 + sw s7, 128(s5) + mflo s7, $ac1 + sw s7, 124(s5) + + mfhi s7, $ac2 + sw s7, 136(s5) + mflo s7, $ac2 + sw s7, 132(s5) + + mfhi s7, $ac3 + sw s7, 144(s5) + mflo s7, $ac3 + sw s7, 140(s5) + + rddsp s7 + sw s7, 148(s5) + + mfhi s7, $ac0 + sw s7, 12(s5) + mflo s7, $ac0 + sw s7, 8(s5) + + /* Test if FPU context save is required. */ + lw s7, portTASK_HAS_FPU_STACK_LOCATION(s5) + beq s7, zero, 1f + nop + + /* Save the FPU registers above the normal context. */ + portSAVE_FPU_REGS (portCONTEXT_SIZE + 8), s5 + + /* Save the FPU status register */ + cfc1 s7, $f31 + sw s7, ( portCONTEXT_SIZE + portFPCSR_STACK_LOCATION )(s5) + + 1: + /* Save the stack pointer to the task. */ + la s7, pxCurrentTCB + lw s7, (s7) + sw s5, (s7) + + /* Set the interrupt mask to the max priority that can use the API. The + yield handler will only be called at configKERNEL_INTERRUPT_PRIORITY which + is below configMAX_SYSCALL_INTERRUPT_PRIORITY - so this can only ever + raise the IPL value and never lower it. */ + di + ehb + mfc0 s7, _CP0_STATUS + ins s7, zero, 10, 7 + ins s7, zero, 18, 1 + ori s6, s7, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) | 1 + + /* This mtc0 re-enables interrupts, but only above + configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + mtc0 s6, _CP0_STATUS + ehb + + /* Clear the software interrupt in the core. */ + mfc0 s6, _CP0_CAUSE + ins s6, zero, 8, 1 + mtc0 s6, _CP0_CAUSE + ehb + + /* Clear the interrupt in the interrupt controller. */ + la s6, IFS0CLR + addiu s4, zero, 2 + sw s4, (s6) + + jal vTaskSwitchContext + nop + + /* Clear the interrupt mask again. The saved status value is still in s7. */ + mtc0 s7, _CP0_STATUS + ehb + + /* Restore the stack pointer from the TCB. */ + la s0, pxCurrentTCB + lw s0, (s0) + lw s5, (s0) + + /* Test if the FPU context needs restoring. */ + lw s0, portTASK_HAS_FPU_STACK_LOCATION(s5) + beq s0, zero, 1f + nop + + /* Restore the FPU status register. */ + lw s0, ( portCONTEXT_SIZE + portFPCSR_STACK_LOCATION )(s5) + ctc1 s0, $f31 + + /* Restore the FPU registers. */ + portLOAD_FPU_REGS ( portCONTEXT_SIZE + 8 ), s5 + + 1: + /* Restore the rest of the context. */ + lw s0, 128(s5) + mthi s0, $ac1 + lw s0, 124(s5) + mtlo s0, $ac1 + + lw s0, 136(s5) + mthi s0, $ac2 + lw s0, 132(s5) + mtlo s0, $ac2 + + lw s0, 144(s5) + mthi s0, $ac3 + lw s0, 140(s5) + mtlo s0, $ac3 + + lw s0, 148(s5) + wrdsp s0 + + lw s0, 8(s5) + mtlo s0, $ac0 + lw s0, 12(s5) + mthi s0, $ac0 + + lw $1, 16(s5) + lw s0, 20(s5) + lw s1, 24(s5) + lw s2, 28(s5) + lw s3, 32(s5) + lw s4, 36(s5) + + /* s5 is loaded later. */ + lw s6, 44(s5) + lw s7, 48(s5) + lw v0, 52(s5) + lw v1, 56(s5) + lw a0, 60(s5) + lw a1, 64(s5) + lw a2, 68(s5) + lw a3, 72(s5) + lw t0, 76(s5) + lw t1, 80(s5) + lw t2, 84(s5) + lw t3, 88(s5) + lw t4, 92(s5) + lw t5, 96(s5) + lw t6, 100(s5) + lw t7, 104(s5) + lw t8, 108(s5) + lw t9, 112(s5) + lw s8, 116(s5) + lw ra, 120(s5) + + /* Protect access to the k registers, and others. */ + di + ehb + + /* Set nesting back to zero. As the lowest priority interrupt this + interrupt cannot have nested. */ + la k0, uxInterruptNesting + sw zero, 0(k0) + + /* Switch back to use the real stack pointer. */ + add sp, zero, s5 + + /* Restore the real s5 value. */ + lw s5, 40(sp) + + /* Pop the FPU context value from the stack */ + lw k0, portTASK_HAS_FPU_STACK_LOCATION(sp) + la k1, ulTaskHasFPUContext + sw k0, 0(k1) + beq k0, zero, 1f + nop + + /* task has FPU context so adjust the stack frame after popping the + status and epc values. */ + lw k1, portSTATUS_STACK_LOCATION(sp) + lw k0, portEPC_STACK_LOCATION(sp) + addiu sp, sp, portFPU_CONTEXT_SIZE + beq zero, zero, 2f + nop + + 1: + /* Pop the status and epc values. */ + lw k1, portSTATUS_STACK_LOCATION(sp) + lw k0, portEPC_STACK_LOCATION(sp) + + 2: + /* Remove stack frame. */ + addiu sp, sp, portCONTEXT_SIZE + + #else + /* Code sequence for no FPU support, the context save requires advance + knowledge of the stack frame size when no FPU is being used */ + + /* Make room for the context. First save the current status so it can be + manipulated, and the cause and EPC registers so thier original values are + captured. */ + addiu sp, sp, -portCONTEXT_SIZE + mfc0 k1, _CP0_STATUS + + /* Also save s6 and s5 so they can be used. Any nesting interrupts should + maintain the values of these registers across the ISR. */ + sw s6, 44(sp) + sw s5, 40(sp) + sw k1, portSTATUS_STACK_LOCATION(sp) + + /* Prepare to re-enabled interrupts above the kernel priority. */ + ins k1, zero, 10, 7 /* Clear IPL bits 0:6. */ + ins k1, zero, 18, 1 /* Clear IPL bit 7. It would be an error here if this bit were set anyway. */ + ori k1, k1, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) + ins k1, zero, 1, 4 /* Clear EXL, ERL and UM. */ + + /* s5 is used as the frame pointer. */ + add s5, zero, sp + + /* Swap to the system stack. This is not conditional on the nesting + count as this interrupt is always the lowest priority and therefore + the nesting is always 0. */ + la sp, xISRStackTop + lw sp, (sp) + + /* Set the nesting count. */ + la k0, uxInterruptNesting + addiu s6, zero, 1 + sw s6, 0(k0) + + /* s6 holds the EPC value, this is saved with the rest of the context + after interrupts are enabled. */ + mfc0 s6, _CP0_EPC + + /* Re-enable interrupts above configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + mtc0 k1, _CP0_STATUS + + /* Save the context into the space just created. s6 is saved again + here as it now contains the EPC value. */ + sw ra, 120(s5) + sw s8, 116(s5) + sw t9, 112(s5) + sw t8, 108(s5) + sw t7, 104(s5) + sw t6, 100(s5) + sw t5, 96(s5) + sw t4, 92(s5) + sw t3, 88(s5) + sw t2, 84(s5) + sw t1, 80(s5) + sw t0, 76(s5) + sw a3, 72(s5) + sw a2, 68(s5) + sw a1, 64(s5) + sw a0, 60(s5) + sw v1, 56(s5) + sw v0, 52(s5) + sw s7, 48(s5) + sw s6, portEPC_STACK_LOCATION(s5) + /* s5 and s6 has already been saved. */ + sw s4, 36(s5) + sw s3, 32(s5) + sw s2, 28(s5) + sw s1, 24(s5) + sw s0, 20(s5) + sw $1, 16(s5) + + /* s7 is used as a scratch register as this should always be saved across + nesting interrupts. */ + + /* Save the AC0, AC1, AC2 and AC3. */ + mfhi s7, $ac1 + sw s7, 128(s5) + mflo s7, $ac1 + sw s7, 124(s5) + + mfhi s7, $ac2 + sw s7, 136(s5) + mflo s7, $ac2 + sw s7, 132(s5) + + mfhi s7, $ac3 + sw s7, 144(s5) + mflo s7, $ac3 + sw s7, 140(s5) + + rddsp s7 + sw s7, 148(s5) + + mfhi s7, $ac0 + sw s7, 12(s5) + mflo s7, $ac0 + sw s7, 8(s5) + + /* Save the stack pointer to the task. */ + la s7, pxCurrentTCB + lw s7, (s7) + sw s5, (s7) + + /* Set the interrupt mask to the max priority that can use the API. The + yield handler will only be called at configKERNEL_INTERRUPT_PRIORITY which + is below configMAX_SYSCALL_INTERRUPT_PRIORITY - so this can only ever + raise the IPL value and never lower it. */ + di + ehb + mfc0 s7, _CP0_STATUS + ins s7, zero, 10, 7 + ins s7, zero, 18, 1 + ori s6, s7, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) | 1 + + /* This mtc0 re-enables interrupts, but only above + configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + mtc0 s6, _CP0_STATUS + ehb + + /* Clear the software interrupt in the core. */ + mfc0 s6, _CP0_CAUSE + ins s6, zero, 8, 1 + mtc0 s6, _CP0_CAUSE + ehb + + /* Clear the interrupt in the interrupt controller. */ + la s6, IFS0CLR + addiu s4, zero, 2 + sw s4, (s6) + + jal vTaskSwitchContext + nop + + /* Clear the interrupt mask again. The saved status value is still in s7. */ + mtc0 s7, _CP0_STATUS + ehb + + /* Restore the stack pointer from the TCB. */ + la s0, pxCurrentTCB + lw s0, (s0) + lw s5, (s0) + + /* Restore the rest of the context. */ + lw s0, 128(s5) + mthi s0, $ac1 + lw s0, 124(s5) + mtlo s0, $ac1 + + lw s0, 136(s5) + mthi s0, $ac2 + lw s0, 132(s5) + mtlo s0, $ac2 + + lw s0, 144(s5) + mthi s0, $ac3 + lw s0, 140(s5) + mtlo s0, $ac3 + + lw s0, 148(s5) + wrdsp s0 + + lw s0, 8(s5) + mtlo s0, $ac0 + lw s0, 12(s5) + mthi s0, $ac0 + + lw $1, 16(s5) + lw s0, 20(s5) + lw s1, 24(s5) + lw s2, 28(s5) + lw s3, 32(s5) + lw s4, 36(s5) + + /* s5 is loaded later. */ + lw s6, 44(s5) + lw s7, 48(s5) + lw v0, 52(s5) + lw v1, 56(s5) + lw a0, 60(s5) + lw a1, 64(s5) + lw a2, 68(s5) + lw a3, 72(s5) + lw t0, 76(s5) + lw t1, 80(s5) + lw t2, 84(s5) + lw t3, 88(s5) + lw t4, 92(s5) + lw t5, 96(s5) + lw t6, 100(s5) + lw t7, 104(s5) + lw t8, 108(s5) + lw t9, 112(s5) + lw s8, 116(s5) + lw ra, 120(s5) + + /* Protect access to the k registers, and others. */ + di + ehb + + /* Set nesting back to zero. As the lowest priority interrupt this + interrupt cannot have nested. */ + la k0, uxInterruptNesting + sw zero, 0(k0) + + /* Switch back to use the real stack pointer. */ + add sp, zero, s5 + + /* Restore the real s5 value. */ + lw s5, 40(sp) + + /* Pop the status and epc values. */ + lw k1, portSTATUS_STACK_LOCATION(sp) + lw k0, portEPC_STACK_LOCATION(sp) + + /* Remove stack frame. */ + addiu sp, sp, portCONTEXT_SIZE + + #endif /* ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */ + + /* Restore the status and EPC registers and return */ + mtc0 k1, _CP0_STATUS + mtc0 k0, _CP0_EPC + ehb + eret + nop + + .end vPortYieldISR + +/******************************************************************/ + +#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) + + .macro portFPUSetAndInc reg, dest + mtc1 \reg, \dest + cvt.d.w \dest, \dest + addiu \reg, \reg, 1 + .endm + + .set noreorder + .set noat + .section .text, code + .ent vPortInitialiseFPSCR + +vPortInitialiseFPSCR: + + /* Initialize the floating point status register in CP1. The initial + value is passed in a0. */ + ctc1 a0, $f31 + + /* Clear the FPU registers */ + addiu a0, zero, 0x0000 + portFPUSetAndInc a0, $f0 + portFPUSetAndInc a0, $f1 + portFPUSetAndInc a0, $f2 + portFPUSetAndInc a0, $f3 + portFPUSetAndInc a0, $f4 + portFPUSetAndInc a0, $f5 + portFPUSetAndInc a0, $f6 + portFPUSetAndInc a0, $f7 + portFPUSetAndInc a0, $f8 + portFPUSetAndInc a0, $f9 + portFPUSetAndInc a0, $f10 + portFPUSetAndInc a0, $f11 + portFPUSetAndInc a0, $f12 + portFPUSetAndInc a0, $f13 + portFPUSetAndInc a0, $f14 + portFPUSetAndInc a0, $f15 + portFPUSetAndInc a0, $f16 + portFPUSetAndInc a0, $f17 + portFPUSetAndInc a0, $f18 + portFPUSetAndInc a0, $f19 + portFPUSetAndInc a0, $f20 + portFPUSetAndInc a0, $f21 + portFPUSetAndInc a0, $f22 + portFPUSetAndInc a0, $f23 + portFPUSetAndInc a0, $f24 + portFPUSetAndInc a0, $f25 + portFPUSetAndInc a0, $f26 + portFPUSetAndInc a0, $f27 + portFPUSetAndInc a0, $f28 + portFPUSetAndInc a0, $f29 + portFPUSetAndInc a0, $f30 + portFPUSetAndInc a0, $f31 + + jr ra + nop + + .end vPortInitialiseFPSCR + +#endif /* ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */ + +#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) + + /**********************************************************************/ + /* Test read back */ + /* a0 = address to store registers */ + + .set noreorder + .set noat + .section .text, code + .ent vPortFPUReadback + .global vPortFPUReadback + +vPortFPUReadback: + sdc1 $f0, 0(a0) + sdc1 $f1, 8(a0) + sdc1 $f2, 16(a0) + sdc1 $f3, 24(a0) + sdc1 $f4, 32(a0) + sdc1 $f5, 40(a0) + sdc1 $f6, 48(a0) + sdc1 $f7, 56(a0) + sdc1 $f8, 64(a0) + sdc1 $f9, 72(a0) + sdc1 $f10, 80(a0) + sdc1 $f11, 88(a0) + sdc1 $f12, 96(a0) + sdc1 $f13, 104(a0) + sdc1 $f14, 112(a0) + sdc1 $f15, 120(a0) + sdc1 $f16, 128(a0) + sdc1 $f17, 136(a0) + sdc1 $f18, 144(a0) + sdc1 $f19, 152(a0) + sdc1 $f20, 160(a0) + sdc1 $f21, 168(a0) + sdc1 $f22, 176(a0) + sdc1 $f23, 184(a0) + sdc1 $f24, 192(a0) + sdc1 $f25, 200(a0) + sdc1 $f26, 208(a0) + sdc1 $f27, 216(a0) + sdc1 $f28, 224(a0) + sdc1 $f29, 232(a0) + sdc1 $f30, 240(a0) + sdc1 $f31, 248(a0) + + jr ra + nop + + .end vPortFPUReadback + +#endif /* ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */ diff --git a/portable/MPLAB/PIC32MZ/portmacro.h b/portable/MPLAB/PIC32MZ/portmacro.h new file mode 100644 index 000000000..8b0497086 --- /dev/null +++ b/portable/MPLAB/PIC32MZ/portmacro.h @@ -0,0 +1,230 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* System include files */ +#include + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 8 +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +#define portIPL_SHIFT ( 10UL ) +/* Don't straddle the CEE bit. Interrupts calling FreeRTOS functions should +never have higher IPL bits set anyway. */ +#define portALL_IPL_BITS ( 0x7FUL << portIPL_SHIFT ) +#define portSW0_BIT ( 0x01 << 8 ) + +/* This clears the IPL bits, then sets them to +configMAX_SYSCALL_INTERRUPT_PRIORITY. An extra check is performed if +configASSERT() is defined to ensure an assertion handler does not inadvertently +attempt to lower the IPL when the call to assert was triggered because the IPL +value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR +safe FreeRTOS API function was executed. ISR safe FreeRTOS API functions are +those that end in FromISR. FreeRTOS maintains a separate interrupt API to +ensure API function and interrupt entry is as fast and as simple as possible. */ +#if ( configASSERT_DEFINED == 1 ) + #define portDISABLE_INTERRUPTS() \ + { \ + uint32_t ulStatus; \ + \ + /* Mask interrupts at and below the kernel interrupt priority. */ \ + ulStatus = _CP0_GET_STATUS(); \ + \ + /* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */ \ + if( ( ( ulStatus & portALL_IPL_BITS ) >> portIPL_SHIFT ) < configMAX_SYSCALL_INTERRUPT_PRIORITY ) \ + { \ + ulStatus &= ~portALL_IPL_BITS; \ + _CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \ + } \ + } +#else /* configASSERT */ + #define portDISABLE_INTERRUPTS() \ + { \ + uint32_t ulStatus; \ + \ + /* Mask interrupts at and below the kernel interrupt priority. */ \ + ulStatus = _CP0_GET_STATUS(); \ + ulStatus &= ~portALL_IPL_BITS; \ + _CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \ + } +#endif /* configASSERT */ + +#define portENABLE_INTERRUPTS() \ +{ \ +uint32_t ulStatus; \ + \ + /* Unmask all interrupts. */ \ + ulStatus = _CP0_GET_STATUS(); \ + ulStatus &= ~portALL_IPL_BITS; \ + _CP0_SET_STATUS( ulStatus ); \ +} + + +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); +#define portCRITICAL_NESTING_IN_TCB 1 +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() + +extern UBaseType_t uxPortSetInterruptMaskFromISR(); +extern void vPortClearInterruptMaskFromISR( UBaseType_t ); +#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister ) + +#if ( __mips_hard_float == 0 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) + #error configUSE_TASK_FPU_SUPPORT can only be set to 1 when the part supports a hardware FPU module. +#endif + +#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) + void vPortTaskUsesFPU( void ); + #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() +#endif + +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + + /* Check the configuration. */ + #if( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + + /* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + + /*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - _clz( ( uxReadyPriorities ) ) ) + +#endif /* taskRECORD_READY_PRIORITY */ + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +#define portYIELD() \ +{ \ +uint32_t ulCause; \ + \ + /* Trigger software interrupt. */ \ + ulCause = _CP0_GET_CAUSE(); \ + ulCause |= portSW0_BIT; \ + _CP0_SET_CAUSE( ulCause ); \ +} + +extern volatile UBaseType_t uxInterruptNesting; +#define portASSERT_IF_IN_ISR() configASSERT( uxInterruptNesting == 0 ) + +#define portNOP() __asm volatile ( "nop" ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn)) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +/*-----------------------------------------------------------*/ + +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portYIELD(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) + +/* Required by the kernel aware debugger. */ +#ifdef __DEBUG + #define portREMOVE_STATIC_QUALIFIER +#endif + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/MSVC-MingW/port.c b/portable/MSVC-MingW/port.c new file mode 100644 index 000000000..d992c4d3c --- /dev/null +++ b/portable/MSVC-MingW/port.c @@ -0,0 +1,753 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#ifdef WIN32_LEAN_AND_MEAN + #include +#else + #include +#endif + +#ifdef _MSC_VER + #include + #pragma comment(lib, "winmm.lib") +#else + #include +#endif + +#define portMAX_INTERRUPTS ( ( uint32_t ) sizeof( uint32_t ) * 8UL ) /* The number of bits in an uint32_t. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + +/* The priorities at which the various components of the simulation execute. */ +#define portDELETE_SELF_THREAD_PRIORITY THREAD_PRIORITY_TIME_CRITICAL /* Must be highest. */ +#define portSIMULATED_INTERRUPTS_THREAD_PRIORITY THREAD_PRIORITY_TIME_CRITICAL +#define portSIMULATED_TIMER_THREAD_PRIORITY THREAD_PRIORITY_HIGHEST +#define portTASK_THREAD_PRIORITY THREAD_PRIORITY_ABOVE_NORMAL + +/* + * Created as a high priority thread, this function uses a timer to simulate + * a tick interrupt being generated on an embedded target. In this Windows + * environment the timer does not achieve anything approaching real time + * performance though. + */ +static DWORD WINAPI prvSimulatedPeripheralTimer( LPVOID lpParameter ); + +/* + * Process all the simulated interrupts - each represented by a bit in + * ulPendingInterrupts variable. + */ +static void prvProcessSimulatedInterrupts( void ); + +/* + * Interrupt handlers used by the kernel itself. These are executed from the + * simulated interrupt handler thread. + */ +static uint32_t prvProcessYieldInterrupt( void ); +static uint32_t prvProcessTickInterrupt( void ); + +/* + * Exiting a critical section will cause the calling task to block on yield + * event to wait for an interrupt to process if an interrupt was pended while + * inside the critical section. This variable protects against a recursive + * attempt to obtain pvInterruptEventMutex if a critical section is used inside + * an interrupt handler itself. + */ +volatile BaseType_t xInsideInterrupt = pdFALSE; + +/* + * Called when the process exits to let Windows know the high timer resolution + * is no longer required. + */ +static BOOL WINAPI prvEndProcess( DWORD dwCtrlType ); + +/*-----------------------------------------------------------*/ + +/* The WIN32 simulator runs each task in a thread. The context switching is + * managed by the threads, so the task stack does not have to be managed directly, + * although the task stack is still used to hold an xThreadState structure this is + * the only thing it will ever hold. The structure indirectly maps the task handle + * to a thread handle. */ +typedef struct +{ + /* Handle of the thread that executes the task. */ + void * pvThread; + + /* Event used to make sure the thread does not execute past a yield point + * between the call to SuspendThread() to suspend the thread and the + * asynchronous SuspendThread() operation actually being performed. */ + void * pvYieldEvent; +} ThreadState_t; + +/* Simulated interrupts waiting to be processed. This is a bit mask where each + * bit represents one interrupt, so a maximum of 32 interrupts can be simulated. */ +static volatile uint32_t ulPendingInterrupts = 0UL; + +/* An event used to inform the simulated interrupt processing thread (a high + * priority thread that simulated interrupt processing) that an interrupt is + * pending. */ +static void * pvInterruptEvent = NULL; + +/* Mutex used to protect all the simulated interrupt variables that are accessed + * by multiple threads. */ +static void * pvInterruptEventMutex = NULL; + +/* The critical nesting count for the currently executing task. This is + * initialised to a non-zero value so interrupts do not become enabled during + * the initialisation phase. As each task has its own critical nesting value + * ulCriticalNesting will get set to zero when the first task runs. This + * initialisation is probably not critical in this simulated environment as the + * simulated interrupt handlers do not get created until the FreeRTOS scheduler is + * started anyway. */ +static volatile uint32_t ulCriticalNesting = 9999UL; + +/* Handlers for all the simulated software interrupts. The first two positions + * are used for the Yield and Tick interrupts so are handled slightly differently, + * all the other interrupts can be user defined. */ +static uint32_t (* ulIsrHandler[ portMAX_INTERRUPTS ])( void ) = { 0 }; + +/* Pointer to the TCB of the currently executing task. */ +extern void * volatile pxCurrentTCB; + +/* Used to ensure nothing is processed during the startup sequence. */ +static BaseType_t xPortRunning = pdFALSE; + +/*-----------------------------------------------------------*/ + +static DWORD WINAPI prvSimulatedPeripheralTimer( LPVOID lpParameter ) +{ + TickType_t xMinimumWindowsBlockTime; + TIMECAPS xTimeCaps; + TickType_t xWaitTimeBetweenTicks = portTICK_PERIOD_MS; + HANDLE hTimer = NULL; + LARGE_INTEGER liDueTime; + BOOL bSuccess; + + /* Set the timer resolution to the maximum possible. */ + if( timeGetDevCaps( &xTimeCaps, sizeof( xTimeCaps ) ) == MMSYSERR_NOERROR ) + { + xMinimumWindowsBlockTime = ( TickType_t ) xTimeCaps.wPeriodMin; + timeBeginPeriod( xTimeCaps.wPeriodMin ); + + /* Register an exit handler so the timeBeginPeriod() function can be + * matched with a timeEndPeriod() when the application exits. */ + SetConsoleCtrlHandler( prvEndProcess, TRUE ); + } + else + { + xMinimumWindowsBlockTime = ( TickType_t ) 20; + } + + /* Just to prevent compiler warnings. */ + ( void ) lpParameter; + + /* Tick time for the timer is adjusted with the maximum available + resolution. */ + if( portTICK_PERIOD_MS < xMinimumWindowsBlockTime ) + { + xWaitTimeBetweenTicks = xMinimumWindowsBlockTime; + } + + /* Convert the tick time in milliseconds to nanoseconds resolution + for the Waitable Timer. */ + liDueTime.u.LowPart = xWaitTimeBetweenTicks * 1000 * 1000; + liDueTime.u.HighPart = 0; + + /* Create a synchronization Waitable Timer.*/ + hTimer = CreateWaitableTimer( NULL, FALSE, NULL ); + + configASSERT( hTimer != NULL ); + + /* Set the Waitable Timer. The timer is set to run periodically at every + xWaitTimeBetweenTicks milliseconds. */ + bSuccess = SetWaitableTimer( hTimer, &liDueTime, xWaitTimeBetweenTicks, NULL, NULL, 0 ); + configASSERT( bSuccess ); + + while( xPortRunning == pdTRUE ) + { + /* Wait until the timer expires and we can access the simulated interrupt + * variables. */ + + WaitForSingleObject( hTimer, INFINITE ); + + vPortGenerateSimulatedInterruptFromWindowsThread( portINTERRUPT_TICK ); + } + + return 0; +} +/*-----------------------------------------------------------*/ + +static BOOL WINAPI prvEndProcess( DWORD dwCtrlType ) +{ + TIMECAPS xTimeCaps; + + ( void ) dwCtrlType; + + if( timeGetDevCaps( &xTimeCaps, sizeof( xTimeCaps ) ) == MMSYSERR_NOERROR ) + { + /* Match the call to timeBeginPeriod( xTimeCaps.wPeriodMin ) made when + * the process started with a timeEndPeriod() as the process exits. */ + timeEndPeriod( xTimeCaps.wPeriodMin ); + } + + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + ThreadState_t * pxThreadState = NULL; + int8_t * pcTopOfStack = ( int8_t * ) pxTopOfStack; + const SIZE_T xStackSize = 1024; /* Set the size to a small number which will get rounded up to the minimum possible. */ + + /* In this simulated case a stack is not initialised, but instead a thread + * is created that will execute the task being created. The thread handles + * the context switching itself. The ThreadState_t object is placed onto + * the stack that was created for the task - so the stack buffer is still + * used, just not in the conventional way. It will not be used for anything + * other than holding this structure. */ + pxThreadState = ( ThreadState_t * ) ( pcTopOfStack - sizeof( ThreadState_t ) ); + + /* Create the event used to prevent the thread from executing past its yield + * point if the SuspendThread() call that suspends the thread does not take + * effect immediately (it is an asynchronous call). */ + pxThreadState->pvYieldEvent = CreateEvent( NULL, /* Default security attributes. */ + FALSE, /* Auto reset. */ + FALSE, /* Start not signalled. */ + NULL ); /* No name. */ + + +#ifdef __GNUC__ + /* GCC reports the warning for the cast operation from TaskFunction_t to LPTHREAD_START_ROUTINE. */ + /* Disable this warning here by the #pragma option. */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wcast-function-type" +#endif + /* Create the thread itself. */ + pxThreadState->pvThread = CreateThread( NULL, xStackSize, ( LPTHREAD_START_ROUTINE ) pxCode, pvParameters, CREATE_SUSPENDED | STACK_SIZE_PARAM_IS_A_RESERVATION, NULL ); +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + + configASSERT( pxThreadState->pvThread ); /* See comment where TerminateThread() is called. */ + SetThreadAffinityMask( pxThreadState->pvThread, 0x01 ); + SetThreadPriorityBoost( pxThreadState->pvThread, TRUE ); + SetThreadPriority( pxThreadState->pvThread, portTASK_THREAD_PRIORITY ); + + return ( StackType_t * ) pxThreadState; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + void * pvHandle = NULL; + int32_t lSuccess; + ThreadState_t * pxThreadState = NULL; + SYSTEM_INFO xSystemInfo; + + /* This port runs windows threads with extremely high priority. All the + * threads execute on the same core - to prevent locking up the host only start + * if the host has multiple cores. */ + GetSystemInfo( &xSystemInfo ); + + if( xSystemInfo.dwNumberOfProcessors <= 1 ) + { + printf( "This version of the FreeRTOS Windows port can only be used on multi-core hosts.\r\n" ); + lSuccess = pdFAIL; + } + else + { + lSuccess = pdPASS; + + /* The highest priority class is used to [try to] prevent other Windows + * activity interfering with FreeRTOS timing too much. */ + if( SetPriorityClass( GetCurrentProcess(), REALTIME_PRIORITY_CLASS ) == 0 ) + { + printf( "SetPriorityClass() failed\r\n" ); + } + + /* Install the interrupt handlers used by the scheduler itself. */ + vPortSetInterruptHandler( portINTERRUPT_YIELD, prvProcessYieldInterrupt ); + vPortSetInterruptHandler( portINTERRUPT_TICK, prvProcessTickInterrupt ); + + /* Create the events and mutexes that are used to synchronise all the + * threads. */ + pvInterruptEventMutex = CreateMutex( NULL, FALSE, NULL ); + pvInterruptEvent = CreateEvent( NULL, FALSE, FALSE, NULL ); + + if( ( pvInterruptEventMutex == NULL ) || ( pvInterruptEvent == NULL ) ) + { + lSuccess = pdFAIL; + } + + /* Set the priority of this thread such that it is above the priority of + * the threads that run tasks. This higher priority is required to ensure + * simulated interrupts take priority over tasks. */ + pvHandle = GetCurrentThread(); + + if( pvHandle == NULL ) + { + lSuccess = pdFAIL; + } + } + + if( lSuccess == pdPASS ) + { + if( SetThreadPriority( pvHandle, portSIMULATED_INTERRUPTS_THREAD_PRIORITY ) == 0 ) + { + lSuccess = pdFAIL; + } + + SetThreadPriorityBoost( pvHandle, TRUE ); + SetThreadAffinityMask( pvHandle, 0x01 ); + } + + if( lSuccess == pdPASS ) + { + /* Start the thread that simulates the timer peripheral to generate + * tick interrupts. The priority is set below that of the simulated + * interrupt handler so the interrupt event mutex is used for the + * handshake / overrun protection. */ + pvHandle = CreateThread( NULL, 0, prvSimulatedPeripheralTimer, NULL, CREATE_SUSPENDED, NULL ); + + if( pvHandle != NULL ) + { + SetThreadPriority( pvHandle, portSIMULATED_TIMER_THREAD_PRIORITY ); + SetThreadPriorityBoost( pvHandle, TRUE ); + SetThreadAffinityMask( pvHandle, 0x01 ); + ResumeThread( pvHandle ); + } + + /* Start the highest priority task by obtaining its associated thread + * state structure, in which is stored the thread handle. */ + pxThreadState = ( ThreadState_t * ) *( ( size_t * ) pxCurrentTCB ); + ulCriticalNesting = portNO_CRITICAL_NESTING; + + /* The scheduler is now running. */ + xPortRunning = pdTRUE; + + /* Start the first task. */ + ResumeThread( pxThreadState->pvThread ); + + /* Handle all simulated interrupts - including yield requests and + * simulated ticks. */ + prvProcessSimulatedInterrupts(); + } + + /* Would not expect to return from prvProcessSimulatedInterrupts(), so should + * not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +static uint32_t prvProcessYieldInterrupt( void ) +{ + /* Always return true as this is a yield. */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +static uint32_t prvProcessTickInterrupt( void ) +{ + uint32_t ulSwitchRequired; + + /* Process the tick itself. */ + configASSERT( xPortRunning ); + ulSwitchRequired = ( uint32_t ) xTaskIncrementTick(); + + return ulSwitchRequired; +} +/*-----------------------------------------------------------*/ + +static void prvProcessSimulatedInterrupts( void ) +{ + uint32_t ulSwitchRequired, i; + ThreadState_t * pxThreadState; + void * pvObjectList[ 2 ]; + CONTEXT xContext; + DWORD xWinApiResult; + const DWORD xTimeoutMilliseconds = 1000; + + /* Going to block on the mutex that ensured exclusive access to the simulated + * interrupt objects, and the event that signals that a simulated interrupt + * should be processed. */ + pvObjectList[ 0 ] = pvInterruptEventMutex; + pvObjectList[ 1 ] = pvInterruptEvent; + + /* Create a pending tick to ensure the first task is started as soon as + * this thread pends. */ + ulPendingInterrupts |= ( 1 << portINTERRUPT_TICK ); + SetEvent( pvInterruptEvent ); + + while( xPortRunning == pdTRUE ) + { + xInsideInterrupt = pdFALSE; + + /* Wait with timeout so that we can exit from this loop when + * the scheduler is stopped by calling vPortEndScheduler. */ + xWinApiResult = WaitForMultipleObjects( sizeof( pvObjectList ) / sizeof( void * ), pvObjectList, TRUE, xTimeoutMilliseconds ); + + if( xWinApiResult != WAIT_TIMEOUT ) + { + /* Cannot be in a critical section to get here. Tasks that exit a + * critical section will block on a yield mutex to wait for an interrupt to + * process if an interrupt was set pending while the task was inside the + * critical section. xInsideInterrupt prevents interrupts that contain + * critical sections from doing the same. */ + xInsideInterrupt = pdTRUE; + + /* Used to indicate whether the simulated interrupt processing has + * necessitated a context switch to another task/thread. */ + ulSwitchRequired = pdFALSE; + + /* For each interrupt we are interested in processing, each of which is + * represented by a bit in the 32bit ulPendingInterrupts variable. */ + for( i = 0; i < portMAX_INTERRUPTS; i++ ) + { + /* Is the simulated interrupt pending? */ + if( ( ulPendingInterrupts & ( 1UL << i ) ) != 0 ) + { + /* Is a handler installed? */ + if( ulIsrHandler[ i ] != NULL ) + { + /* Run the actual handler. Handlers return pdTRUE if they + * necessitate a context switch. */ + if( ulIsrHandler[ i ]() != pdFALSE ) + { + /* A bit mask is used purely to help debugging. */ + ulSwitchRequired |= ( 1 << i ); + } + } + + /* Clear the interrupt pending bit. */ + ulPendingInterrupts &= ~( 1UL << i ); + } + } + + if( ulSwitchRequired != pdFALSE ) + { + /* Suspend the old thread. */ + pxThreadState = ( ThreadState_t * ) *( ( size_t * ) pxCurrentTCB ); + SuspendThread( pxThreadState->pvThread ); + + /* Ensure the thread is actually suspended by performing a + * synchronous operation that can only complete when the thread + * is actually suspended. The below code asks for dummy register + * data. Experimentation shows that these two lines don't appear + * to do anything now, but according to + * https://devblogs.microsoft.com/oldnewthing/20150205-00/?p=44743 + * they do - so as they do not harm (slight run-time hit). */ + xContext.ContextFlags = CONTEXT_INTEGER; + ( void ) GetThreadContext( pxThreadState->pvThread, &xContext ); + + /* Select the next task to run. */ + vTaskSwitchContext(); + + /* Obtain the state of the task now selected to enter the + * Running state. */ + pxThreadState = ( ThreadState_t * ) ( *( size_t * ) pxCurrentTCB ); + + /* pxThreadState->pvThread can be NULL if the task deleted + * itself - but a deleted task should never be resumed here. */ + configASSERT( pxThreadState->pvThread != NULL ); + ResumeThread( pxThreadState->pvThread ); + } + + /* If the thread that is about to be resumed stopped running + * because it yielded then it will wait on an event when it resumed + * (to ensure it does not continue running after the call to + * SuspendThread() above as SuspendThread() is asynchronous). + * Signal the event to ensure the thread can proceed now it is + * valid for it to do so. Signaling the event is benign in the case that + * the task was switched out asynchronously by an interrupt as the event + * is reset before the task blocks on it. */ + pxThreadState = ( ThreadState_t * ) ( *( size_t * ) pxCurrentTCB ); + SetEvent( pxThreadState->pvYieldEvent ); + ReleaseMutex( pvInterruptEventMutex ); + } + } +} +/*-----------------------------------------------------------*/ + +void vPortDeleteThread( void * pvTaskToDelete ) +{ + ThreadState_t * pxThreadState; + uint32_t ulErrorCode; + + /* Remove compiler warnings if configASSERT() is not defined. */ + ( void ) ulErrorCode; + + /* Find the handle of the thread being deleted. */ + pxThreadState = ( ThreadState_t * ) ( *( size_t * ) pvTaskToDelete ); + + /* Check that the thread is still valid, it might have been closed by + * vPortCloseRunningThread() - which will be the case if the task associated + * with the thread originally deleted itself rather than being deleted by a + * different task. */ + if( pxThreadState->pvThread != NULL ) + { + WaitForSingleObject( pvInterruptEventMutex, INFINITE ); + + /* !!! This is not a nice way to terminate a thread, and will eventually + * result in resources being depleted if tasks frequently delete other + * tasks (rather than deleting themselves) as the task stacks will not be + * freed. */ + ulErrorCode = TerminateThread( pxThreadState->pvThread, 0 ); + configASSERT( ulErrorCode ); + + ulErrorCode = CloseHandle( pxThreadState->pvThread ); + configASSERT( ulErrorCode ); + + ReleaseMutex( pvInterruptEventMutex ); + } +} +/*-----------------------------------------------------------*/ + +void vPortCloseRunningThread( void * pvTaskToDelete, + volatile BaseType_t * pxPendYield ) +{ + ThreadState_t * pxThreadState; + void * pvThread; + uint32_t ulErrorCode; + + /* Remove compiler warnings if configASSERT() is not defined. */ + ( void ) ulErrorCode; + + /* Find the handle of the thread being deleted. */ + pxThreadState = ( ThreadState_t * ) ( *( size_t * ) pvTaskToDelete ); + pvThread = pxThreadState->pvThread; + + /* Raise the Windows priority of the thread to ensure the FreeRTOS scheduler + * does not run and swap it out before it is closed. If that were to happen + * the thread would never run again and effectively be a thread handle and + * memory leak. */ + SetThreadPriority( pvThread, portDELETE_SELF_THREAD_PRIORITY ); + + /* This function will not return, therefore a yield is set as pending to + * ensure a context switch occurs away from this thread on the next tick. */ + *pxPendYield = pdTRUE; + + /* Mark the thread associated with this task as invalid so + * vPortDeleteThread() does not try to terminate it. */ + pxThreadState->pvThread = NULL; + + /* Close the thread. */ + ulErrorCode = CloseHandle( pvThread ); + configASSERT( ulErrorCode ); + + /* This is called from a critical section, which must be exited before the + * thread stops. */ + taskEXIT_CRITICAL(); + + /* Record that a yield is pending so that the next tick interrupt switches + * out this thread regardless of the value of configUSE_PREEMPTION. This is + * needed when a task deletes itself - the taskYIELD_WITHIN_API within + * vTaskDelete does not get called because this function never returns. If + * we do not pend portINTERRUPT_YIELD here, the next task is not scheduled + * when configUSE_PREEMPTION is set to 0. */ + if( pvInterruptEventMutex != NULL ) + { + WaitForSingleObject( pvInterruptEventMutex, INFINITE ); + ulPendingInterrupts |= ( 1 << portINTERRUPT_YIELD ); + ReleaseMutex( pvInterruptEventMutex ); + } + + CloseHandle( pxThreadState->pvYieldEvent ); + ExitThread( 0 ); +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + xPortRunning = pdFALSE; +} +/*-----------------------------------------------------------*/ + +void vPortGenerateSimulatedInterrupt( uint32_t ulInterruptNumber ) +{ + ThreadState_t * pxThreadState = ( ThreadState_t * ) *( ( size_t * ) pxCurrentTCB ); + + configASSERT( xPortRunning ); + + if( ( ulInterruptNumber < portMAX_INTERRUPTS ) && ( pvInterruptEventMutex != NULL ) ) + { + WaitForSingleObject( pvInterruptEventMutex, INFINITE ); + ulPendingInterrupts |= ( 1 << ulInterruptNumber ); + + /* The simulated interrupt is now held pending, but don't actually + * process it yet if this call is within a critical section. It is + * possible for this to be in a critical section as calls to wait for + * mutexes are accumulative. If in a critical section then the event + * will get set when the critical section nesting count is wound back + * down to zero. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + SetEvent( pvInterruptEvent ); + + /* Going to wait for an event - make sure the event is not already + * signaled. */ + ResetEvent( pxThreadState->pvYieldEvent ); + } + + ReleaseMutex( pvInterruptEventMutex ); + + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* An interrupt was pended so ensure to block to allow it to + * execute. In most cases the (simulated) interrupt will have + * executed before the next line is reached - so this is just to make + * sure. */ + WaitForSingleObject( pxThreadState->pvYieldEvent, INFINITE ); + } + } +} +/*-----------------------------------------------------------*/ + +void vPortGenerateSimulatedInterruptFromWindowsThread( uint32_t ulInterruptNumber ) +{ + if( xPortRunning == pdTRUE ) + { + /* Can't proceed if in a critical section as pvInterruptEventMutex won't + * be available. */ + WaitForSingleObject( pvInterruptEventMutex, INFINITE ); + + /* Pending a user defined interrupt to be handled in simulated interrupt + * handler thread. */ + ulPendingInterrupts |= ( 1 << ulInterruptNumber ); + + /* The interrupt is now pending - notify the simulated interrupt + * handler thread. Must be outside of a critical section to get here so + * the handler thread can execute immediately pvInterruptEventMutex is + * released. */ + configASSERT( ulCriticalNesting == 0UL ); + SetEvent( pvInterruptEvent ); + + /* Give back the mutex so the simulated interrupt handler unblocks + * and can access the interrupt handler variables. */ + ReleaseMutex( pvInterruptEventMutex ); + } +} +/*-----------------------------------------------------------*/ + +void vPortSetInterruptHandler( uint32_t ulInterruptNumber, + uint32_t ( * pvHandler )( void ) ) +{ + if( ulInterruptNumber < portMAX_INTERRUPTS ) + { + if( pvInterruptEventMutex != NULL ) + { + WaitForSingleObject( pvInterruptEventMutex, INFINITE ); + ulIsrHandler[ ulInterruptNumber ] = pvHandler; + ReleaseMutex( pvInterruptEventMutex ); + } + else + { + ulIsrHandler[ ulInterruptNumber ] = pvHandler; + } + } +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + if( xPortRunning == pdTRUE ) + { + /* The interrupt event mutex is held for the entire critical section, + * effectively disabling (simulated) interrupts. */ + WaitForSingleObject( pvInterruptEventMutex, INFINITE ); + } + + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + int32_t lMutexNeedsReleasing; + + /* The interrupt event mutex should already be held by this thread as it was + * obtained on entry to the critical section. */ + lMutexNeedsReleasing = pdTRUE; + + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + ulCriticalNesting--; + + /* Don't need to wait for any pending interrupts to execute if the + * critical section was exited from inside an interrupt. */ + if( ( ulCriticalNesting == portNO_CRITICAL_NESTING ) && ( xInsideInterrupt == pdFALSE ) ) + { + /* Were any interrupts set to pending while interrupts were + * (simulated) disabled? */ + if( ulPendingInterrupts != 0UL ) + { + ThreadState_t * pxThreadState = ( ThreadState_t * ) *( ( size_t * ) pxCurrentTCB ); + + configASSERT( xPortRunning ); + + /* The interrupt won't actually executed until + * pvInterruptEventMutex is released as it waits on both + * pvInterruptEventMutex and pvInterruptEvent. + * pvInterruptEvent is only set when the simulated + * interrupt is pended if the interrupt is pended + * from outside a critical section - hence it is set + * here. */ + SetEvent( pvInterruptEvent ); + + /* The calling task is going to wait for an event to ensure the + * interrupt that is pending executes immediately after the + * critical section is exited - so make sure the event is not + * already signaled. */ + ResetEvent( pxThreadState->pvYieldEvent ); + + /* Mutex will be released now so the (simulated) interrupt can + * execute, so does not require releasing on function exit. */ + lMutexNeedsReleasing = pdFALSE; + ReleaseMutex( pvInterruptEventMutex ); + WaitForSingleObject( pxThreadState->pvYieldEvent, INFINITE ); + } + } + } + + if( pvInterruptEventMutex != NULL ) + { + if( lMutexNeedsReleasing == pdTRUE ) + { + configASSERT( xPortRunning ); + ReleaseMutex( pvInterruptEventMutex ); + } + } +} +/*-----------------------------------------------------------*/ diff --git a/portable/MSVC-MingW/portmacro.h b/portable/MSVC-MingW/portmacro.h new file mode 100644 index 000000000..37bfb2586 --- /dev/null +++ b/portable/MSVC-MingW/portmacro.h @@ -0,0 +1,218 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/****************************************************************************** +* Defines +******************************************************************************/ +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE size_t +#define portPOINTER_SIZE_TYPE size_t + +typedef portSTACK_TYPE StackType_t; + +#if defined( __x86_64__ ) || defined( _M_X64 ) + #define portBASE_TYPE long long + typedef long long BaseType_t; + typedef unsigned long long UBaseType_t; +#else + #define portBASE_TYPE long + typedef long BaseType_t; + typedef unsigned long UBaseType_t; +#endif + + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32/64-bit architecture, so reads of the tick + * count do not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_64_BITS ) + typedef uint64_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffffffffffULL + +#if defined( __x86_64__ ) || defined( _M_X64 ) +/* 64-bit tick type on a 64-bit architecture, so reads of the tick + * count do not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#endif +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portINLINE __inline + +#if defined( __x86_64__ ) || defined( _M_X64 ) + #define portBYTE_ALIGNMENT 8 +#else + #define portBYTE_ALIGNMENT 4 +#endif + +#define portYIELD() vPortGenerateSimulatedInterrupt( portINTERRUPT_YIELD ) + + +extern volatile BaseType_t xInsideInterrupt; +#define portSOFTWARE_BARRIER() while( xInsideInterrupt != pdFALSE ) + + +/* Simulated interrupts return pdFALSE if no context switch should be performed, + * or a non-zero number if a context switch should be performed. */ +#define portYIELD_FROM_ISR( x ) return x +#define portEND_SWITCHING_ISR( x ) portYIELD_FROM_ISR( ( x ) ) + +void vPortCloseRunningThread( void * pvTaskToDelete, + volatile BaseType_t * pxPendYield ); +void vPortDeleteThread( void * pvThreadToDelete ); +#define portCLEAN_UP_TCB( pxTCB ) vPortDeleteThread( pxTCB ) +#define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxPendYield ) vPortCloseRunningThread( ( pvTaskToDelete ), ( pxPendYield ) ) +#define portDISABLE_INTERRUPTS() vPortEnterCritical() +#define portENABLE_INTERRUPTS() vPortExitCritical() + +/* Critical section handling. */ +void vPortEnterCritical( void ); +void vPortExitCritical( void ); + +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() + +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +/*-----------------------------------------------------------*/ + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + + /* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + + /* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( ( ( UBaseType_t ) 1 ) << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( ( ( UBaseType_t ) 1 ) << ( uxPriority ) ) + + #ifdef __GNUC__ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) \ + __asm volatile ( "bsr %1, %0\n\t" \ + : "=r" ( uxTopPriority ) \ + : "rm" ( uxReadyPriorities ) \ + : "cc" ) + + #else /* __GNUC__ */ + #include + + /* BitScanReverse returns the bit position of the most significant '1' + * in the word. */ + #if defined( __x86_64__ ) || defined( _M_X64 ) + #pragma intrinsic(_BitScanReverse64) + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) \ + do \ + { \ + unsigned long ulTopPriority; \ + _BitScanReverse64( &ulTopPriority, ( uxReadyPriorities ) ); \ + uxTopPriority = ulTopPriority; \ + } while( 0 ) + + #else /* #if defined( __x86_64__ ) || defined( _M_X64 ) */ + #pragma intrinsic(_BitScanReverse) + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) _BitScanReverse( ( unsigned long * ) &( uxTopPriority ), ( uxReadyPriorities ) ) + + #endif /* #if defined( __x86_64__ ) || defined( _M_X64 ) */ + + #endif /* __GNUC__ */ + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +#ifndef __GNUC__ + __pragma( warning( disable:4211 ) ) /* Nonstandard extension used, as extern is only nonstandard to MSVC. */ +#endif + + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +#define portINTERRUPT_YIELD ( 0UL ) +#define portINTERRUPT_TICK ( 1UL ) +#define portINTERRUPT_APPLICATION_DEFINED_START ( 2UL ) + +/* + * Raise a simulated interrupt represented by the bit mask in ulInterruptMask. + * Each bit can be used to represent an individual interrupt - with the first + * two bits being used for the Yield and Tick interrupts respectively. + */ +void vPortGenerateSimulatedInterrupt( uint32_t ulInterruptNumber ); + +/* + * Raise a simulated interrupt represented by the bit mask in ulInterruptMask. + * Each bit can be used to represent an individual interrupt - with the first + * two bits being used for the Yield and Tick interrupts respectively. This function + * can be called in a windows thread. + */ +void vPortGenerateSimulatedInterruptFromWindowsThread( uint32_t ulInterruptNumber ); + +/* + * Install an interrupt handler to be called by the simulated interrupt handler + * thread. The interrupt number must be above any used by the kernel itself + * (at the time of writing the kernel was using interrupt numbers 0, 1, and 2 + * as defined above). The number must also be lower than 32. + * + * Interrupt handler functions must return a non-zero value if executing the + * handler resulted in a task switch being required. + */ +void vPortSetInterruptHandler( uint32_t ulInterruptNumber, + uint32_t ( * pvHandler )( void ) ); + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef PORTMACRO_H */ diff --git a/portable/MemMang/ReadMe.url b/portable/MemMang/ReadMe.url new file mode 100644 index 000000000..28c993773 --- /dev/null +++ b/portable/MemMang/ReadMe.url @@ -0,0 +1,5 @@ +[{000214A0-0000-0000-C000-000000000046}] +Prop3=19,2 +[InternetShortcut] +URL=https://www.FreeRTOS.org/a00111.html +IDList= diff --git a/portable/MemMang/heap_1.c b/portable/MemMang/heap_1.c new file mode 100644 index 000000000..f697c907c --- /dev/null +++ b/portable/MemMang/heap_1.c @@ -0,0 +1,178 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/* + * The simplest possible implementation of pvPortMalloc(). Note that this + * implementation does NOT allow allocated memory to be freed again. + * + * See heap_2.c, heap_3.c and heap_4.c for alternative implementations, and the + * memory management pages of https://www.FreeRTOS.org for more information. + */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#include "FreeRTOS.h" +#include "task.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) + #error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0 +#endif + +/* A few bytes might be lost to byte aligning the heap start address. */ +#define configADJUSTED_HEAP_SIZE ( configTOTAL_HEAP_SIZE - portBYTE_ALIGNMENT ) + +/* Max value that fits in a size_t type. */ +#define heapSIZE_MAX ( ~( ( size_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define heapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( heapSIZE_MAX - ( b ) ) ) + +/*-----------------------------------------------------------*/ + +/* Allocate the memory for the heap. */ +#if ( configAPPLICATION_ALLOCATED_HEAP == 1 ) + +/* The application writer has already defined the array used for the RTOS + * heap - probably so it can be placed in a special segment or address. */ + extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ]; +#else + static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ]; +#endif /* configAPPLICATION_ALLOCATED_HEAP */ + +/* Index into the ucHeap array. */ +static size_t xNextFreeByte = ( size_t ) 0U; + +/*-----------------------------------------------------------*/ + +void * pvPortMalloc( size_t xWantedSize ) +{ + void * pvReturn = NULL; + static uint8_t * pucAlignedHeap = NULL; + + /* Ensure that blocks are always aligned. */ + #if ( portBYTE_ALIGNMENT != 1 ) + { + size_t xAdditionalRequiredSize; + + if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 ) + { + /* Byte alignment required. */ + xAdditionalRequiredSize = portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ); + + if( heapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 ) + { + xWantedSize += xAdditionalRequiredSize; + } + else + { + xWantedSize = 0; + } + } + } + #endif /* if ( portBYTE_ALIGNMENT != 1 ) */ + + vTaskSuspendAll(); + { + if( pucAlignedHeap == NULL ) + { + /* Ensure the heap starts on a correctly aligned boundary. */ + pucAlignedHeap = ( uint8_t * ) ( ( ( portPOINTER_SIZE_TYPE ) &( ucHeap[ portBYTE_ALIGNMENT - 1 ] ) ) & + ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); + } + + /* Check there is enough room left for the allocation. */ + if( ( xWantedSize > 0 ) && + ( heapADD_WILL_OVERFLOW( xNextFreeByte, xWantedSize ) == 0 ) && + ( ( xNextFreeByte + xWantedSize ) < configADJUSTED_HEAP_SIZE ) ) + { + /* Return the next free byte then increment the index past this + * block. */ + pvReturn = pucAlignedHeap + xNextFreeByte; + xNextFreeByte += xWantedSize; + } + + traceMALLOC( pvReturn, xWantedSize ); + } + ( void ) xTaskResumeAll(); + + #if ( configUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) + { + vApplicationMallocFailedHook(); + } + } + #endif + + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void * pv ) +{ + /* Memory cannot be freed using this scheme. See heap_2.c, heap_3.c and + * heap_4.c for alternative implementations, and the memory management pages of + * https://www.FreeRTOS.org for more information. */ + ( void ) pv; + + /* Force an assert as it is invalid to call this function. */ + configASSERT( pv == NULL ); +} +/*-----------------------------------------------------------*/ + +void vPortInitialiseBlocks( void ) +{ + /* Only required when static memory is not cleared. */ + xNextFreeByte = ( size_t ) 0; +} +/*-----------------------------------------------------------*/ + +size_t xPortGetFreeHeapSize( void ) +{ + return( configADJUSTED_HEAP_SIZE - xNextFreeByte ); +} + +/*-----------------------------------------------------------*/ + +/* + * Reset the state in this file. This state is normally initialized at start up. + * This function must be called by the application before restarting the + * scheduler. + */ +void vPortHeapResetState( void ) +{ + xNextFreeByte = ( size_t ) 0U; +} +/*-----------------------------------------------------------*/ diff --git a/portable/MemMang/heap_2.c b/portable/MemMang/heap_2.c new file mode 100644 index 000000000..fa6ea9d9b --- /dev/null +++ b/portable/MemMang/heap_2.c @@ -0,0 +1,407 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * A sample implementation of pvPortMalloc() and vPortFree() that permits + * allocated blocks to be freed, but does not combine adjacent free blocks + * into a single larger block (and so will fragment memory). See heap_4.c for + * an equivalent that does combine adjacent blocks into single larger blocks. + * + * See heap_1.c, heap_3.c and heap_4.c for alternative implementations, and the + * memory management pages of https://www.FreeRTOS.org for more information. + */ +#include +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#include "FreeRTOS.h" +#include "task.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) + #error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0 +#endif + +#ifndef configHEAP_CLEAR_MEMORY_ON_FREE + #define configHEAP_CLEAR_MEMORY_ON_FREE 0 +#endif + +/* A few bytes might be lost to byte aligning the heap start address. */ +#define configADJUSTED_HEAP_SIZE ( configTOTAL_HEAP_SIZE - portBYTE_ALIGNMENT ) + +/* Assumes 8bit bytes! */ +#define heapBITS_PER_BYTE ( ( size_t ) 8 ) + +/* Max value that fits in a size_t type. */ +#define heapSIZE_MAX ( ~( ( size_t ) 0 ) ) + +/* Check if multiplying a and b will result in overflow. */ +#define heapMULTIPLY_WILL_OVERFLOW( a, b ) ( ( ( a ) > 0 ) && ( ( b ) > ( heapSIZE_MAX / ( a ) ) ) ) + +/* Check if adding a and b will result in overflow. */ +#define heapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( heapSIZE_MAX - ( b ) ) ) + +/* MSB of the xBlockSize member of an BlockLink_t structure is used to track + * the allocation status of a block. When MSB of the xBlockSize member of + * an BlockLink_t structure is set then the block belongs to the application. + * When the bit is free the block is still part of the free heap space. */ +#define heapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 ) ) +#define heapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & heapBLOCK_ALLOCATED_BITMASK ) == 0 ) +#define heapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & heapBLOCK_ALLOCATED_BITMASK ) != 0 ) +#define heapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= heapBLOCK_ALLOCATED_BITMASK ) +#define heapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~heapBLOCK_ALLOCATED_BITMASK ) + +/*-----------------------------------------------------------*/ + +/* Allocate the memory for the heap. */ +#if ( configAPPLICATION_ALLOCATED_HEAP == 1 ) + +/* The application writer has already defined the array used for the RTOS + * heap - probably so it can be placed in a special segment or address. */ + extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ]; +#else + PRIVILEGED_DATA static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ]; +#endif /* configAPPLICATION_ALLOCATED_HEAP */ + + +/* Define the linked list structure. This is used to link free blocks in order + * of their size. */ +typedef struct A_BLOCK_LINK +{ + struct A_BLOCK_LINK * pxNextFreeBlock; /*<< The next free block in the list. */ + size_t xBlockSize; /*<< The size of the free block. */ +} BlockLink_t; + + +static const size_t xHeapStructSize = ( ( sizeof( BlockLink_t ) + ( size_t ) ( portBYTE_ALIGNMENT - 1 ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK ) ); +#define heapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize * 2 ) ) + +/* Create a couple of list links to mark the start and end of the list. */ +PRIVILEGED_DATA static BlockLink_t xStart, xEnd; + +/* Keeps track of the number of free bytes remaining, but says nothing about + * fragmentation. */ +PRIVILEGED_DATA static size_t xFreeBytesRemaining = configADJUSTED_HEAP_SIZE; + +/* Indicates whether the heap has been initialised or not. */ +PRIVILEGED_DATA static BaseType_t xHeapHasBeenInitialised = pdFALSE; + +/*-----------------------------------------------------------*/ + +/* + * Initialises the heap structures before their first use. + */ +static void prvHeapInit( void ) PRIVILEGED_FUNCTION; + +/*-----------------------------------------------------------*/ + +/* STATIC FUNCTIONS ARE DEFINED AS MACROS TO MINIMIZE THE FUNCTION CALL DEPTH. */ + +/* + * Insert a block into the list of free blocks - which is ordered by size of + * the block. Small blocks at the start of the list and large blocks at the end + * of the list. + */ +#define prvInsertBlockIntoFreeList( pxBlockToInsert ) \ + { \ + BlockLink_t * pxIterator; \ + size_t xBlockSize; \ + \ + xBlockSize = pxBlockToInsert->xBlockSize; \ + \ + /* Iterate through the list until a block is found that has a larger size */ \ + /* than the block we are inserting. */ \ + for( pxIterator = &xStart; pxIterator->pxNextFreeBlock->xBlockSize < xBlockSize; pxIterator = pxIterator->pxNextFreeBlock ) \ + { \ + /* There is nothing to do here - just iterate to the correct position. */ \ + } \ + \ + /* Update the list to include the block being inserted in the correct */ \ + /* position. */ \ + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; \ + pxIterator->pxNextFreeBlock = pxBlockToInsert; \ + } +/*-----------------------------------------------------------*/ + +void * pvPortMalloc( size_t xWantedSize ) +{ + BlockLink_t * pxBlock; + BlockLink_t * pxPreviousBlock; + BlockLink_t * pxNewBlockLink; + void * pvReturn = NULL; + size_t xAdditionalRequiredSize; + size_t xAllocatedBlockSize = 0; + + if( xWantedSize > 0 ) + { + /* The wanted size must be increased so it can contain a BlockLink_t + * structure in addition to the requested amount of bytes. */ + if( heapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 ) + { + xWantedSize += xHeapStructSize; + + /* Ensure that blocks are always aligned to the required number + * of bytes. */ + if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 ) + { + /* Byte alignment required. */ + xAdditionalRequiredSize = portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ); + + if( heapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 ) + { + xWantedSize += xAdditionalRequiredSize; + } + else + { + xWantedSize = 0; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + xWantedSize = 0; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + vTaskSuspendAll(); + { + /* If this is the first call to malloc then the heap will require + * initialisation to setup the list of free blocks. */ + if( xHeapHasBeenInitialised == pdFALSE ) + { + prvHeapInit(); + xHeapHasBeenInitialised = pdTRUE; + } + + /* Check the block size we are trying to allocate is not so large that the + * top bit is set. The top bit of the block size member of the BlockLink_t + * structure is used to determine who owns the block - the application or + * the kernel, so it must be free. */ + if( heapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 ) + { + if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) + { + /* Blocks are stored in byte order - traverse the list from the start + * (smallest) block until one of adequate size is found. */ + pxPreviousBlock = &xStart; + pxBlock = xStart.pxNextFreeBlock; + + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + { + pxPreviousBlock = pxBlock; + pxBlock = pxBlock->pxNextFreeBlock; + } + + /* If we found the end marker then a block of adequate size was not found. */ + if( pxBlock != &xEnd ) + { + /* Return the memory space - jumping over the BlockLink_t structure + * at its start. */ + pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); + + /* This block is being returned for use so must be taken out of the + * list of free blocks. */ + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + + /* If the block is larger than required it can be split into two. */ + if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE ) + { + /* This block is to be split into two. Create a new block + * following the number of bytes requested. The void cast is + * used to prevent byte alignment warnings from the compiler. */ + pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); + + /* Calculate the sizes of two blocks split from the single + * block. */ + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + pxBlock->xBlockSize = xWantedSize; + + /* Insert the new block into the list of free blocks. + * The list of free blocks is sorted by their size, we have to + * iterate to find the right place to insert new block. */ + prvInsertBlockIntoFreeList( ( pxNewBlockLink ) ); + } + + xFreeBytesRemaining -= pxBlock->xBlockSize; + + xAllocatedBlockSize = pxBlock->xBlockSize; + + /* The block is being returned - it is allocated and owned + * by the application and has no "next" block. */ + heapALLOCATE_BLOCK( pxBlock ); + pxBlock->pxNextFreeBlock = NULL; + } + } + } + + traceMALLOC( pvReturn, xAllocatedBlockSize ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xAllocatedBlockSize; + } + ( void ) xTaskResumeAll(); + + #if ( configUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) + { + vApplicationMallocFailedHook(); + } + } + #endif + + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void * pv ) +{ + uint8_t * puc = ( uint8_t * ) pv; + BlockLink_t * pxLink; + + if( pv != NULL ) + { + /* The memory being freed will have an BlockLink_t structure immediately + * before it. */ + puc -= xHeapStructSize; + + /* This unexpected casting is to keep some compilers from issuing + * byte alignment warnings. */ + pxLink = ( void * ) puc; + + configASSERT( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 ); + configASSERT( pxLink->pxNextFreeBlock == NULL ); + + if( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 ) + { + if( pxLink->pxNextFreeBlock == NULL ) + { + /* The block is being returned to the heap - it is no longer + * allocated. */ + heapFREE_BLOCK( pxLink ); + #if ( configHEAP_CLEAR_MEMORY_ON_FREE == 1 ) + { + ( void ) memset( puc + xHeapStructSize, 0, pxLink->xBlockSize - xHeapStructSize ); + } + #endif + + vTaskSuspendAll(); + { + /* Add this block to the list of free blocks. */ + prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); + xFreeBytesRemaining += pxLink->xBlockSize; + traceFREE( pv, pxLink->xBlockSize ); + } + ( void ) xTaskResumeAll(); + } + } + } +} +/*-----------------------------------------------------------*/ + +size_t xPortGetFreeHeapSize( void ) +{ + return xFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +void vPortInitialiseBlocks( void ) +{ + /* This just exists to keep the linker quiet. */ +} +/*-----------------------------------------------------------*/ + +void * pvPortCalloc( size_t xNum, + size_t xSize ) +{ + void * pv = NULL; + + if( heapMULTIPLY_WILL_OVERFLOW( xNum, xSize ) == 0 ) + { + pv = pvPortMalloc( xNum * xSize ); + + if( pv != NULL ) + { + ( void ) memset( pv, 0, xNum * xSize ); + } + } + + return pv; +} +/*-----------------------------------------------------------*/ + +static void prvHeapInit( void ) /* PRIVILEGED_FUNCTION */ +{ + BlockLink_t * pxFirstFreeBlock; + uint8_t * pucAlignedHeap; + + /* Ensure the heap starts on a correctly aligned boundary. */ + pucAlignedHeap = ( uint8_t * ) ( ( ( portPOINTER_SIZE_TYPE ) & ucHeap[ portBYTE_ALIGNMENT - 1 ] ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); + + /* xStart is used to hold a pointer to the first item in the list of free + * blocks. The void cast is used to prevent compiler warnings. */ + xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; + xStart.xBlockSize = ( size_t ) 0; + + /* xEnd is used to mark the end of the list of free blocks. */ + xEnd.xBlockSize = configADJUSTED_HEAP_SIZE; + xEnd.pxNextFreeBlock = NULL; + + /* To start with there is a single free block that is sized to take up the + * entire heap space. */ + pxFirstFreeBlock = ( BlockLink_t * ) pucAlignedHeap; + pxFirstFreeBlock->xBlockSize = configADJUSTED_HEAP_SIZE; + pxFirstFreeBlock->pxNextFreeBlock = &xEnd; +} +/*-----------------------------------------------------------*/ + +/* + * Reset the state in this file. This state is normally initialized at start up. + * This function must be called by the application before restarting the + * scheduler. + */ +void vPortHeapResetState( void ) +{ + xFreeBytesRemaining = configADJUSTED_HEAP_SIZE; + + xHeapHasBeenInitialised = pdFALSE; +} +/*-----------------------------------------------------------*/ diff --git a/portable/MemMang/heap_3.c b/portable/MemMang/heap_3.c new file mode 100644 index 000000000..5094390b5 --- /dev/null +++ b/portable/MemMang/heap_3.c @@ -0,0 +1,106 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/* + * Implementation of pvPortMalloc() and vPortFree() that relies on the + * compilers own malloc() and free() implementations. + * + * This file can only be used if the linker is configured to to generate + * a heap memory area. + * + * See heap_1.c, heap_2.c and heap_4.c for alternative implementations, and the + * memory management pages of https://www.FreeRTOS.org for more information. + */ + +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#include "FreeRTOS.h" +#include "task.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) + #error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0 +#endif + +/*-----------------------------------------------------------*/ + +void * pvPortMalloc( size_t xWantedSize ) +{ + void * pvReturn; + + vTaskSuspendAll(); + { + pvReturn = malloc( xWantedSize ); + traceMALLOC( pvReturn, xWantedSize ); + } + ( void ) xTaskResumeAll(); + + #if ( configUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) + { + vApplicationMallocFailedHook(); + } + } + #endif + + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void * pv ) +{ + if( pv != NULL ) + { + vTaskSuspendAll(); + { + free( pv ); + traceFREE( pv, 0 ); + } + ( void ) xTaskResumeAll(); + } +} +/*-----------------------------------------------------------*/ + +/* + * Reset the state in this file. This state is normally initialized at start up. + * This function must be called by the application before restarting the + * scheduler. + */ +void vPortHeapResetState( void ) +{ + /* No state needs to be re-initialised in heap_3. */ +} +/*-----------------------------------------------------------*/ diff --git a/portable/MemMang/heap_4.c b/portable/MemMang/heap_4.c new file mode 100644 index 000000000..50af15dfb --- /dev/null +++ b/portable/MemMang/heap_4.c @@ -0,0 +1,638 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * A sample implementation of pvPortMalloc() and vPortFree() that combines + * (coalescences) adjacent memory blocks as they are freed, and in so doing + * limits memory fragmentation. + * + * See heap_1.c, heap_2.c and heap_3.c for alternative implementations, and the + * memory management pages of https://www.FreeRTOS.org for more information. + */ +#include +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#include "FreeRTOS.h" +#include "task.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) + #error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0 +#endif + +#ifndef configHEAP_CLEAR_MEMORY_ON_FREE + #define configHEAP_CLEAR_MEMORY_ON_FREE 0 +#endif + +/* Block sizes must not get too small. */ +#define heapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) ) + +/* Assumes 8bit bytes! */ +#define heapBITS_PER_BYTE ( ( size_t ) 8 ) + +/* Max value that fits in a size_t type. */ +#define heapSIZE_MAX ( ~( ( size_t ) 0 ) ) + +/* Check if multiplying a and b will result in overflow. */ +#define heapMULTIPLY_WILL_OVERFLOW( a, b ) ( ( ( a ) > 0 ) && ( ( b ) > ( heapSIZE_MAX / ( a ) ) ) ) + +/* Check if adding a and b will result in overflow. */ +#define heapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( heapSIZE_MAX - ( b ) ) ) + +/* Check if the subtraction operation ( a - b ) will result in underflow. */ +#define heapSUBTRACT_WILL_UNDERFLOW( a, b ) ( ( a ) < ( b ) ) + +/* MSB of the xBlockSize member of an BlockLink_t structure is used to track + * the allocation status of a block. When MSB of the xBlockSize member of + * an BlockLink_t structure is set then the block belongs to the application. + * When the bit is free the block is still part of the free heap space. */ +#define heapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 ) ) +#define heapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & heapBLOCK_ALLOCATED_BITMASK ) == 0 ) +#define heapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & heapBLOCK_ALLOCATED_BITMASK ) != 0 ) +#define heapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= heapBLOCK_ALLOCATED_BITMASK ) +#define heapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~heapBLOCK_ALLOCATED_BITMASK ) + +/*-----------------------------------------------------------*/ + +/* Allocate the memory for the heap. */ +#if ( configAPPLICATION_ALLOCATED_HEAP == 1 ) + +/* The application writer has already defined the array used for the RTOS + * heap - probably so it can be placed in a special segment or address. */ + extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ]; +#else + PRIVILEGED_DATA static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ]; +#endif /* configAPPLICATION_ALLOCATED_HEAP */ + +/* Define the linked list structure. This is used to link free blocks in order + * of their memory address. */ +typedef struct A_BLOCK_LINK +{ + struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */ + size_t xBlockSize; /**< The size of the free block. */ +} BlockLink_t; + +/* Setting configENABLE_HEAP_PROTECTOR to 1 enables heap block pointers + * protection using an application supplied canary value to catch heap + * corruption should a heap buffer overflow occur. + */ +#if ( configENABLE_HEAP_PROTECTOR == 1 ) + +/** + * @brief Application provided function to get a random value to be used as canary. + * + * @param pxHeapCanary [out] Output parameter to return the canary value. + */ + extern void vApplicationGetRandomHeapCanary( portPOINTER_SIZE_TYPE * pxHeapCanary ); + +/* Canary value for protecting internal heap pointers. */ + PRIVILEGED_DATA static portPOINTER_SIZE_TYPE xHeapCanary; + +/* Macro to load/store BlockLink_t pointers to memory. By XORing the + * pointers with a random canary value, heap overflows will result + * in randomly unpredictable pointer values which will be caught by + * heapVALIDATE_BLOCK_POINTER assert. */ + #define heapPROTECT_BLOCK_POINTER( pxBlock ) ( ( BlockLink_t * ) ( ( ( portPOINTER_SIZE_TYPE ) ( pxBlock ) ) ^ xHeapCanary ) ) +#else + + #define heapPROTECT_BLOCK_POINTER( pxBlock ) ( pxBlock ) + +#endif /* configENABLE_HEAP_PROTECTOR */ + +/* Assert that a heap block pointer is within the heap bounds. */ +#define heapVALIDATE_BLOCK_POINTER( pxBlock ) \ + configASSERT( ( ( uint8_t * ) ( pxBlock ) >= &( ucHeap[ 0 ] ) ) && \ + ( ( uint8_t * ) ( pxBlock ) <= &( ucHeap[ configTOTAL_HEAP_SIZE - 1 ] ) ) ) + +/*-----------------------------------------------------------*/ + +/* + * Inserts a block of memory that is being freed into the correct position in + * the list of free memory blocks. The block being freed will be merged with + * the block in front it and/or the block behind it if the memory blocks are + * adjacent to each other. + */ +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) PRIVILEGED_FUNCTION; + +/* + * Called automatically to setup the required heap structures the first time + * pvPortMalloc() is called. + */ +static void prvHeapInit( void ) PRIVILEGED_FUNCTION; + +/*-----------------------------------------------------------*/ + +/* The size of the structure placed at the beginning of each allocated memory + * block must by correctly byte aligned. */ +static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( portBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); + +/* Create a couple of list links to mark the start and end of the list. */ +PRIVILEGED_DATA static BlockLink_t xStart; +PRIVILEGED_DATA static BlockLink_t * pxEnd = NULL; + +/* Keeps track of the number of calls to allocate and free memory as well as the + * number of free bytes remaining, but says nothing about fragmentation. */ +PRIVILEGED_DATA static size_t xFreeBytesRemaining = ( size_t ) 0U; +PRIVILEGED_DATA static size_t xMinimumEverFreeBytesRemaining = ( size_t ) 0U; +PRIVILEGED_DATA static size_t xNumberOfSuccessfulAllocations = ( size_t ) 0U; +PRIVILEGED_DATA static size_t xNumberOfSuccessfulFrees = ( size_t ) 0U; + +/*-----------------------------------------------------------*/ + +void * pvPortMalloc( size_t xWantedSize ) +{ + BlockLink_t * pxBlock; + BlockLink_t * pxPreviousBlock; + BlockLink_t * pxNewBlockLink; + void * pvReturn = NULL; + size_t xAdditionalRequiredSize; + size_t xAllocatedBlockSize = 0; + + if( xWantedSize > 0 ) + { + /* The wanted size must be increased so it can contain a BlockLink_t + * structure in addition to the requested amount of bytes. */ + if( heapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 ) + { + xWantedSize += xHeapStructSize; + + /* Ensure that blocks are always aligned to the required number + * of bytes. */ + if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 ) + { + /* Byte alignment required. */ + xAdditionalRequiredSize = portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ); + + if( heapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 ) + { + xWantedSize += xAdditionalRequiredSize; + } + else + { + xWantedSize = 0; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + xWantedSize = 0; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + vTaskSuspendAll(); + { + /* If this is the first call to malloc then the heap will require + * initialisation to setup the list of free blocks. */ + if( pxEnd == NULL ) + { + prvHeapInit(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Check the block size we are trying to allocate is not so large that the + * top bit is set. The top bit of the block size member of the BlockLink_t + * structure is used to determine who owns the block - the application or + * the kernel, so it must be free. */ + if( heapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 ) + { + if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) + { + /* Traverse the list from the start (lowest address) block until + * one of adequate size is found. */ + pxPreviousBlock = &xStart; + pxBlock = heapPROTECT_BLOCK_POINTER( xStart.pxNextFreeBlock ); + heapVALIDATE_BLOCK_POINTER( pxBlock ); + + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != heapPROTECT_BLOCK_POINTER( NULL ) ) ) + { + pxPreviousBlock = pxBlock; + pxBlock = heapPROTECT_BLOCK_POINTER( pxBlock->pxNextFreeBlock ); + heapVALIDATE_BLOCK_POINTER( pxBlock ); + } + + /* If the end marker was reached then a block of adequate size + * was not found. */ + if( pxBlock != pxEnd ) + { + /* Return the memory space pointed to - jumping over the + * BlockLink_t structure at its start. */ + pvReturn = ( void * ) ( ( ( uint8_t * ) heapPROTECT_BLOCK_POINTER( pxPreviousBlock->pxNextFreeBlock ) ) + xHeapStructSize ); + heapVALIDATE_BLOCK_POINTER( pvReturn ); + + /* This block is being returned for use so must be taken out + * of the list of free blocks. */ + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + + /* If the block is larger than required it can be split into + * two. */ + configASSERT( heapSUBTRACT_WILL_UNDERFLOW( pxBlock->xBlockSize, xWantedSize ) == 0 ); + + if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE ) + { + /* This block is to be split into two. Create a new + * block following the number of bytes requested. The void + * cast is used to prevent byte alignment warnings from the + * compiler. */ + pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); + configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 ); + + /* Calculate the sizes of two blocks split from the + * single block. */ + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + pxBlock->xBlockSize = xWantedSize; + + /* Insert the new block into the list of free blocks. */ + pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock; + pxPreviousBlock->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxNewBlockLink ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xFreeBytesRemaining -= pxBlock->xBlockSize; + + if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) + { + xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xAllocatedBlockSize = pxBlock->xBlockSize; + + /* The block is being returned - it is allocated and owned + * by the application and has no "next" block. */ + heapALLOCATE_BLOCK( pxBlock ); + pxBlock->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( NULL ); + xNumberOfSuccessfulAllocations++; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceMALLOC( pvReturn, xAllocatedBlockSize ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xAllocatedBlockSize; + } + ( void ) xTaskResumeAll(); + + #if ( configUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) + { + vApplicationMallocFailedHook(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* if ( configUSE_MALLOC_FAILED_HOOK == 1 ) */ + + configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 ); + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void * pv ) +{ + uint8_t * puc = ( uint8_t * ) pv; + BlockLink_t * pxLink; + + if( pv != NULL ) + { + /* The memory being freed will have an BlockLink_t structure immediately + * before it. */ + puc -= xHeapStructSize; + + /* This casting is to keep the compiler from issuing warnings. */ + pxLink = ( void * ) puc; + + heapVALIDATE_BLOCK_POINTER( pxLink ); + configASSERT( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 ); + configASSERT( pxLink->pxNextFreeBlock == heapPROTECT_BLOCK_POINTER( NULL ) ); + + if( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 ) + { + if( pxLink->pxNextFreeBlock == heapPROTECT_BLOCK_POINTER( NULL ) ) + { + /* The block is being returned to the heap - it is no longer + * allocated. */ + heapFREE_BLOCK( pxLink ); + #if ( configHEAP_CLEAR_MEMORY_ON_FREE == 1 ) + { + /* Check for underflow as this can occur if xBlockSize is + * overwritten in a heap block. */ + if( heapSUBTRACT_WILL_UNDERFLOW( pxLink->xBlockSize, xHeapStructSize ) == 0 ) + { + ( void ) memset( puc + xHeapStructSize, 0, pxLink->xBlockSize - xHeapStructSize ); + } + } + #endif + + vTaskSuspendAll(); + { + /* Add this block to the list of free blocks. */ + xFreeBytesRemaining += pxLink->xBlockSize; + traceFREE( pv, pxLink->xBlockSize ); + prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); + xNumberOfSuccessfulFrees++; + } + ( void ) xTaskResumeAll(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } +} +/*-----------------------------------------------------------*/ + +size_t xPortGetFreeHeapSize( void ) +{ + return xFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +size_t xPortGetMinimumEverFreeHeapSize( void ) +{ + return xMinimumEverFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +void xPortResetHeapMinimumEverFreeHeapSize( void ) +{ + xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +void vPortInitialiseBlocks( void ) +{ + /* This just exists to keep the linker quiet. */ +} +/*-----------------------------------------------------------*/ + +void * pvPortCalloc( size_t xNum, + size_t xSize ) +{ + void * pv = NULL; + + if( heapMULTIPLY_WILL_OVERFLOW( xNum, xSize ) == 0 ) + { + pv = pvPortMalloc( xNum * xSize ); + + if( pv != NULL ) + { + ( void ) memset( pv, 0, xNum * xSize ); + } + } + + return pv; +} +/*-----------------------------------------------------------*/ + +static void prvHeapInit( void ) /* PRIVILEGED_FUNCTION */ +{ + BlockLink_t * pxFirstFreeBlock; + portPOINTER_SIZE_TYPE uxStartAddress, uxEndAddress; + size_t xTotalHeapSize = configTOTAL_HEAP_SIZE; + + /* Ensure the heap starts on a correctly aligned boundary. */ + uxStartAddress = ( portPOINTER_SIZE_TYPE ) ucHeap; + + if( ( uxStartAddress & portBYTE_ALIGNMENT_MASK ) != 0 ) + { + uxStartAddress += ( portBYTE_ALIGNMENT - 1 ); + uxStartAddress &= ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ); + xTotalHeapSize -= ( size_t ) ( uxStartAddress - ( portPOINTER_SIZE_TYPE ) ucHeap ); + } + + #if ( configENABLE_HEAP_PROTECTOR == 1 ) + { + vApplicationGetRandomHeapCanary( &( xHeapCanary ) ); + } + #endif + + /* xStart is used to hold a pointer to the first item in the list of free + * blocks. The void cast is used to prevent compiler warnings. */ + xStart.pxNextFreeBlock = ( void * ) heapPROTECT_BLOCK_POINTER( uxStartAddress ); + xStart.xBlockSize = ( size_t ) 0; + + /* pxEnd is used to mark the end of the list of free blocks and is inserted + * at the end of the heap space. */ + uxEndAddress = uxStartAddress + ( portPOINTER_SIZE_TYPE ) xTotalHeapSize; + uxEndAddress -= ( portPOINTER_SIZE_TYPE ) xHeapStructSize; + uxEndAddress &= ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ); + pxEnd = ( BlockLink_t * ) uxEndAddress; + pxEnd->xBlockSize = 0; + pxEnd->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( NULL ); + + /* To start with there is a single free block that is sized to take up the + * entire heap space, minus the space taken by pxEnd. */ + pxFirstFreeBlock = ( BlockLink_t * ) uxStartAddress; + pxFirstFreeBlock->xBlockSize = ( size_t ) ( uxEndAddress - ( portPOINTER_SIZE_TYPE ) pxFirstFreeBlock ); + pxFirstFreeBlock->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxEnd ); + + /* Only one block exists - and it covers the entire usable heap space. */ + xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; +} +/*-----------------------------------------------------------*/ + +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) /* PRIVILEGED_FUNCTION */ +{ + BlockLink_t * pxIterator; + uint8_t * puc; + + /* Iterate through the list until a block is found that has a higher address + * than the block being inserted. */ + for( pxIterator = &xStart; heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock ) < pxBlockToInsert; pxIterator = heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock ) ) + { + /* Nothing to do here, just iterate to the right position. */ + } + + if( pxIterator != &xStart ) + { + heapVALIDATE_BLOCK_POINTER( pxIterator ); + } + + /* Do the block being inserted, and the block it is being inserted after + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxIterator; + + if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) + { + pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; + pxBlockToInsert = pxIterator; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Do the block being inserted, and the block it is being inserted before + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxBlockToInsert; + + if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock ) ) + { + if( heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock ) != pxEnd ) + { + /* Form one big block from the two blocks. */ + pxBlockToInsert->xBlockSize += heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock )->xBlockSize; + pxBlockToInsert->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock )->pxNextFreeBlock; + } + else + { + pxBlockToInsert->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxEnd ); + } + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; + } + + /* If the block being inserted plugged a gap, so was merged with the block + * before and the block after, then it's pxNextFreeBlock pointer will have + * already been set, and should not be set here as that would make it point + * to itself. */ + if( pxIterator != pxBlockToInsert ) + { + pxIterator->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxBlockToInsert ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} +/*-----------------------------------------------------------*/ + +void vPortGetHeapStats( HeapStats_t * pxHeapStats ) +{ + BlockLink_t * pxBlock; + size_t xBlocks = 0, xMaxSize = 0, xMinSize = SIZE_MAX; + + vTaskSuspendAll(); + { + pxBlock = heapPROTECT_BLOCK_POINTER( xStart.pxNextFreeBlock ); + + /* pxBlock will be NULL if the heap has not been initialised. The heap + * is initialised automatically when the first allocation is made. */ + if( pxBlock != NULL ) + { + while( pxBlock != pxEnd ) + { + /* Increment the number of blocks and record the largest block seen + * so far. */ + xBlocks++; + + if( pxBlock->xBlockSize > xMaxSize ) + { + xMaxSize = pxBlock->xBlockSize; + } + + if( pxBlock->xBlockSize < xMinSize ) + { + xMinSize = pxBlock->xBlockSize; + } + + /* Move to the next block in the chain until the last block is + * reached. */ + pxBlock = heapPROTECT_BLOCK_POINTER( pxBlock->pxNextFreeBlock ); + } + } + } + ( void ) xTaskResumeAll(); + + pxHeapStats->xSizeOfLargestFreeBlockInBytes = xMaxSize; + pxHeapStats->xSizeOfSmallestFreeBlockInBytes = xMinSize; + pxHeapStats->xNumberOfFreeBlocks = xBlocks; + + taskENTER_CRITICAL(); + { + pxHeapStats->xAvailableHeapSpaceInBytes = xFreeBytesRemaining; + pxHeapStats->xNumberOfSuccessfulAllocations = xNumberOfSuccessfulAllocations; + pxHeapStats->xNumberOfSuccessfulFrees = xNumberOfSuccessfulFrees; + pxHeapStats->xMinimumEverFreeBytesRemaining = xMinimumEverFreeBytesRemaining; + } + taskEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +/* + * Reset the state in this file. This state is normally initialized at start up. + * This function must be called by the application before restarting the + * scheduler. + */ +void vPortHeapResetState( void ) +{ + pxEnd = NULL; + + xFreeBytesRemaining = ( size_t ) 0U; + xMinimumEverFreeBytesRemaining = ( size_t ) 0U; + xNumberOfSuccessfulAllocations = ( size_t ) 0U; + xNumberOfSuccessfulFrees = ( size_t ) 0U; +} +/*-----------------------------------------------------------*/ diff --git a/portable/MemMang/heap_5.c b/portable/MemMang/heap_5.c new file mode 100644 index 000000000..bf321304f --- /dev/null +++ b/portable/MemMang/heap_5.c @@ -0,0 +1,749 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * A sample implementation of pvPortMalloc() that allows the heap to be defined + * across multiple non-contiguous blocks and combines (coalescences) adjacent + * memory blocks as they are freed. + * + * See heap_1.c, heap_2.c, heap_3.c and heap_4.c for alternative + * implementations, and the memory management pages of https://www.FreeRTOS.org + * for more information. + * + * Usage notes: + * + * vPortDefineHeapRegions() ***must*** be called before pvPortMalloc(). + * pvPortMalloc() will be called if any task objects (tasks, queues, event + * groups, etc.) are created, therefore vPortDefineHeapRegions() ***must*** be + * called before any other objects are defined. + * + * vPortDefineHeapRegions() takes a single parameter. The parameter is an array + * of HeapRegion_t structures. HeapRegion_t is defined in portable.h as + * + * typedef struct HeapRegion + * { + * uint8_t *pucStartAddress; << Start address of a block of memory that will be part of the heap. + * size_t xSizeInBytes; << Size of the block of memory. + * } HeapRegion_t; + * + * The array is terminated using a NULL zero sized region definition, and the + * memory regions defined in the array ***must*** appear in address order from + * low address to high address. So the following is a valid example of how + * to use the function. + * + * HeapRegion_t xHeapRegions[] = + * { + * { ( uint8_t * ) 0x80000000UL, 0x10000 }, << Defines a block of 0x10000 bytes starting at address 0x80000000 + * { ( uint8_t * ) 0x90000000UL, 0xa0000 }, << Defines a block of 0xa0000 bytes starting at address of 0x90000000 + * { NULL, 0 } << Terminates the array. + * }; + * + * vPortDefineHeapRegions( xHeapRegions ); << Pass the array into vPortDefineHeapRegions(). + * + * Note 0x80000000 is the lower address so appears in the array first. + * + */ +#include +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#include "FreeRTOS.h" +#include "task.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) + #error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0 +#endif + +#ifndef configHEAP_CLEAR_MEMORY_ON_FREE + #define configHEAP_CLEAR_MEMORY_ON_FREE 0 +#endif + +/* Block sizes must not get too small. */ +#define heapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) ) + +/* Assumes 8bit bytes! */ +#define heapBITS_PER_BYTE ( ( size_t ) 8 ) + +/* Max value that fits in a size_t type. */ +#define heapSIZE_MAX ( ~( ( size_t ) 0 ) ) + +/* Check if multiplying a and b will result in overflow. */ +#define heapMULTIPLY_WILL_OVERFLOW( a, b ) ( ( ( a ) > 0 ) && ( ( b ) > ( heapSIZE_MAX / ( a ) ) ) ) + +/* Check if adding a and b will result in overflow. */ +#define heapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( heapSIZE_MAX - ( b ) ) ) + +/* Check if the subtraction operation ( a - b ) will result in underflow. */ +#define heapSUBTRACT_WILL_UNDERFLOW( a, b ) ( ( a ) < ( b ) ) + +/* MSB of the xBlockSize member of an BlockLink_t structure is used to track + * the allocation status of a block. When MSB of the xBlockSize member of + * an BlockLink_t structure is set then the block belongs to the application. + * When the bit is free the block is still part of the free heap space. */ +#define heapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 ) ) +#define heapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & heapBLOCK_ALLOCATED_BITMASK ) == 0 ) +#define heapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & heapBLOCK_ALLOCATED_BITMASK ) != 0 ) +#define heapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= heapBLOCK_ALLOCATED_BITMASK ) +#define heapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~heapBLOCK_ALLOCATED_BITMASK ) + +/* Setting configENABLE_HEAP_PROTECTOR to 1 enables heap block pointers + * protection using an application supplied canary value to catch heap + * corruption should a heap buffer overflow occur. + */ +#if ( configENABLE_HEAP_PROTECTOR == 1 ) + +/* Macro to load/store BlockLink_t pointers to memory. By XORing the + * pointers with a random canary value, heap overflows will result + * in randomly unpredictable pointer values which will be caught by + * heapVALIDATE_BLOCK_POINTER assert. */ + #define heapPROTECT_BLOCK_POINTER( pxBlock ) ( ( BlockLink_t * ) ( ( ( portPOINTER_SIZE_TYPE ) ( pxBlock ) ) ^ xHeapCanary ) ) + +/* Assert that a heap block pointer is within the heap bounds. + * Setting configVALIDATE_HEAP_BLOCK_POINTER to 1 enables customized heap block pointers + * protection on heap_5. */ + #ifndef configVALIDATE_HEAP_BLOCK_POINTER + #define heapVALIDATE_BLOCK_POINTER( pxBlock ) \ + configASSERT( ( pucHeapHighAddress != NULL ) && \ + ( pucHeapLowAddress != NULL ) && \ + ( ( uint8_t * ) ( pxBlock ) >= pucHeapLowAddress ) && \ + ( ( uint8_t * ) ( pxBlock ) < pucHeapHighAddress ) ) + #else /* ifndef configVALIDATE_HEAP_BLOCK_POINTER */ + #define heapVALIDATE_BLOCK_POINTER( pxBlock ) \ + configVALIDATE_HEAP_BLOCK_POINTER( pxBlock ) + #endif /* configVALIDATE_HEAP_BLOCK_POINTER */ + +#else /* if ( configENABLE_HEAP_PROTECTOR == 1 ) */ + + #define heapPROTECT_BLOCK_POINTER( pxBlock ) ( pxBlock ) + + #define heapVALIDATE_BLOCK_POINTER( pxBlock ) + +#endif /* configENABLE_HEAP_PROTECTOR */ + +/*-----------------------------------------------------------*/ + +/* Define the linked list structure. This is used to link free blocks in order + * of their memory address. */ +typedef struct A_BLOCK_LINK +{ + struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */ + size_t xBlockSize; /**< The size of the free block. */ +} BlockLink_t; + +/*-----------------------------------------------------------*/ + +/* + * Inserts a block of memory that is being freed into the correct position in + * the list of free memory blocks. The block being freed will be merged with + * the block in front it and/or the block behind it if the memory blocks are + * adjacent to each other. + */ +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) PRIVILEGED_FUNCTION; +void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) PRIVILEGED_FUNCTION; + +#if ( configENABLE_HEAP_PROTECTOR == 1 ) + +/** + * @brief Application provided function to get a random value to be used as canary. + * + * @param pxHeapCanary [out] Output parameter to return the canary value. + */ + extern void vApplicationGetRandomHeapCanary( portPOINTER_SIZE_TYPE * pxHeapCanary ); +#endif /* configENABLE_HEAP_PROTECTOR */ + +/*-----------------------------------------------------------*/ + +/* The size of the structure placed at the beginning of each allocated memory + * block must by correctly byte aligned. */ +static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( portBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); + +/* Create a couple of list links to mark the start and end of the list. */ +PRIVILEGED_DATA static BlockLink_t xStart; +PRIVILEGED_DATA static BlockLink_t * pxEnd = NULL; + +/* Keeps track of the number of calls to allocate and free memory as well as the + * number of free bytes remaining, but says nothing about fragmentation. */ +PRIVILEGED_DATA static size_t xFreeBytesRemaining = ( size_t ) 0U; +PRIVILEGED_DATA static size_t xMinimumEverFreeBytesRemaining = ( size_t ) 0U; +PRIVILEGED_DATA static size_t xNumberOfSuccessfulAllocations = ( size_t ) 0U; +PRIVILEGED_DATA static size_t xNumberOfSuccessfulFrees = ( size_t ) 0U; + +#if ( configENABLE_HEAP_PROTECTOR == 1 ) + +/* Canary value for protecting internal heap pointers. */ + PRIVILEGED_DATA static portPOINTER_SIZE_TYPE xHeapCanary; + +/* Highest and lowest heap addresses used for heap block bounds checking. */ + PRIVILEGED_DATA static uint8_t * pucHeapHighAddress = NULL; + PRIVILEGED_DATA static uint8_t * pucHeapLowAddress = NULL; + +#endif /* configENABLE_HEAP_PROTECTOR */ + +/*-----------------------------------------------------------*/ + +void * pvPortMalloc( size_t xWantedSize ) +{ + BlockLink_t * pxBlock; + BlockLink_t * pxPreviousBlock; + BlockLink_t * pxNewBlockLink; + void * pvReturn = NULL; + size_t xAdditionalRequiredSize; + size_t xAllocatedBlockSize = 0; + + /* The heap must be initialised before the first call to + * pvPortMalloc(). */ + configASSERT( pxEnd ); + + if( xWantedSize > 0 ) + { + /* The wanted size must be increased so it can contain a BlockLink_t + * structure in addition to the requested amount of bytes. */ + if( heapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 ) + { + xWantedSize += xHeapStructSize; + + /* Ensure that blocks are always aligned to the required number + * of bytes. */ + if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 ) + { + /* Byte alignment required. */ + xAdditionalRequiredSize = portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ); + + if( heapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 ) + { + xWantedSize += xAdditionalRequiredSize; + } + else + { + xWantedSize = 0; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + xWantedSize = 0; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + vTaskSuspendAll(); + { + /* Check the block size we are trying to allocate is not so large that the + * top bit is set. The top bit of the block size member of the BlockLink_t + * structure is used to determine who owns the block - the application or + * the kernel, so it must be free. */ + if( heapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 ) + { + if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) + { + /* Traverse the list from the start (lowest address) block until + * one of adequate size is found. */ + pxPreviousBlock = &xStart; + pxBlock = heapPROTECT_BLOCK_POINTER( xStart.pxNextFreeBlock ); + heapVALIDATE_BLOCK_POINTER( pxBlock ); + + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != heapPROTECT_BLOCK_POINTER( NULL ) ) ) + { + pxPreviousBlock = pxBlock; + pxBlock = heapPROTECT_BLOCK_POINTER( pxBlock->pxNextFreeBlock ); + heapVALIDATE_BLOCK_POINTER( pxBlock ); + } + + /* If the end marker was reached then a block of adequate size + * was not found. */ + if( pxBlock != pxEnd ) + { + /* Return the memory space pointed to - jumping over the + * BlockLink_t structure at its start. */ + pvReturn = ( void * ) ( ( ( uint8_t * ) heapPROTECT_BLOCK_POINTER( pxPreviousBlock->pxNextFreeBlock ) ) + xHeapStructSize ); + heapVALIDATE_BLOCK_POINTER( pvReturn ); + + /* This block is being returned for use so must be taken out + * of the list of free blocks. */ + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + + /* If the block is larger than required it can be split into + * two. */ + configASSERT( heapSUBTRACT_WILL_UNDERFLOW( pxBlock->xBlockSize, xWantedSize ) == 0 ); + + if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE ) + { + /* This block is to be split into two. Create a new + * block following the number of bytes requested. The void + * cast is used to prevent byte alignment warnings from the + * compiler. */ + pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); + configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 ); + + /* Calculate the sizes of two blocks split from the + * single block. */ + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + pxBlock->xBlockSize = xWantedSize; + + /* Insert the new block into the list of free blocks. */ + pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock; + pxPreviousBlock->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxNewBlockLink ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xFreeBytesRemaining -= pxBlock->xBlockSize; + + if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) + { + xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xAllocatedBlockSize = pxBlock->xBlockSize; + + /* The block is being returned - it is allocated and owned + * by the application and has no "next" block. */ + heapALLOCATE_BLOCK( pxBlock ); + pxBlock->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( NULL ); + xNumberOfSuccessfulAllocations++; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceMALLOC( pvReturn, xAllocatedBlockSize ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xAllocatedBlockSize; + } + ( void ) xTaskResumeAll(); + + #if ( configUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) + { + vApplicationMallocFailedHook(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* if ( configUSE_MALLOC_FAILED_HOOK == 1 ) */ + + configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 ); + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void * pv ) +{ + uint8_t * puc = ( uint8_t * ) pv; + BlockLink_t * pxLink; + + if( pv != NULL ) + { + /* The memory being freed will have an BlockLink_t structure immediately + * before it. */ + puc -= xHeapStructSize; + + /* This casting is to keep the compiler from issuing warnings. */ + pxLink = ( void * ) puc; + + heapVALIDATE_BLOCK_POINTER( pxLink ); + configASSERT( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 ); + configASSERT( pxLink->pxNextFreeBlock == heapPROTECT_BLOCK_POINTER( NULL ) ); + + if( heapBLOCK_IS_ALLOCATED( pxLink ) != 0 ) + { + if( pxLink->pxNextFreeBlock == heapPROTECT_BLOCK_POINTER( NULL ) ) + { + /* The block is being returned to the heap - it is no longer + * allocated. */ + heapFREE_BLOCK( pxLink ); + #if ( configHEAP_CLEAR_MEMORY_ON_FREE == 1 ) + { + /* Check for underflow as this can occur if xBlockSize is + * overwritten in a heap block. */ + if( heapSUBTRACT_WILL_UNDERFLOW( pxLink->xBlockSize, xHeapStructSize ) == 0 ) + { + ( void ) memset( puc + xHeapStructSize, 0, pxLink->xBlockSize - xHeapStructSize ); + } + } + #endif + + vTaskSuspendAll(); + { + /* Add this block to the list of free blocks. */ + xFreeBytesRemaining += pxLink->xBlockSize; + traceFREE( pv, pxLink->xBlockSize ); + prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); + xNumberOfSuccessfulFrees++; + } + ( void ) xTaskResumeAll(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } +} +/*-----------------------------------------------------------*/ + +size_t xPortGetFreeHeapSize( void ) +{ + return xFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +size_t xPortGetMinimumEverFreeHeapSize( void ) +{ + return xMinimumEverFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +void xPortResetHeapMinimumEverFreeHeapSize( void ) +{ + xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +void * pvPortCalloc( size_t xNum, + size_t xSize ) +{ + void * pv = NULL; + + if( heapMULTIPLY_WILL_OVERFLOW( xNum, xSize ) == 0 ) + { + pv = pvPortMalloc( xNum * xSize ); + + if( pv != NULL ) + { + ( void ) memset( pv, 0, xNum * xSize ); + } + } + + return pv; +} +/*-----------------------------------------------------------*/ + +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) /* PRIVILEGED_FUNCTION */ +{ + BlockLink_t * pxIterator; + uint8_t * puc; + + /* Iterate through the list until a block is found that has a higher address + * than the block being inserted. */ + for( pxIterator = &xStart; heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock ) < pxBlockToInsert; pxIterator = heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock ) ) + { + /* Nothing to do here, just iterate to the right position. */ + } + + if( pxIterator != &xStart ) + { + heapVALIDATE_BLOCK_POINTER( pxIterator ); + } + + /* Do the block being inserted, and the block it is being inserted after + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxIterator; + + if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) + { + pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; + pxBlockToInsert = pxIterator; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Do the block being inserted, and the block it is being inserted before + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxBlockToInsert; + + if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock ) ) + { + if( heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock ) != pxEnd ) + { + /* Form one big block from the two blocks. */ + pxBlockToInsert->xBlockSize += heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock )->xBlockSize; + pxBlockToInsert->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxIterator->pxNextFreeBlock )->pxNextFreeBlock; + } + else + { + pxBlockToInsert->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxEnd ); + } + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; + } + + /* If the block being inserted plugged a gap, so was merged with the block + * before and the block after, then it's pxNextFreeBlock pointer will have + * already been set, and should not be set here as that would make it point + * to itself. */ + if( pxIterator != pxBlockToInsert ) + { + pxIterator->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxBlockToInsert ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} +/*-----------------------------------------------------------*/ + +void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) /* PRIVILEGED_FUNCTION */ +{ + BlockLink_t * pxFirstFreeBlockInRegion = NULL; + BlockLink_t * pxPreviousFreeBlock; + portPOINTER_SIZE_TYPE xAlignedHeap; + size_t xTotalRegionSize, xTotalHeapSize = 0; + BaseType_t xDefinedRegions = 0; + portPOINTER_SIZE_TYPE xAddress; + const HeapRegion_t * pxHeapRegion; + + /* Can only call once! */ + configASSERT( pxEnd == NULL ); + + #if ( configENABLE_HEAP_PROTECTOR == 1 ) + { + vApplicationGetRandomHeapCanary( &( xHeapCanary ) ); + } + #endif + + pxHeapRegion = &( pxHeapRegions[ xDefinedRegions ] ); + + while( pxHeapRegion->xSizeInBytes > 0 ) + { + xTotalRegionSize = pxHeapRegion->xSizeInBytes; + + /* Ensure the heap region starts on a correctly aligned boundary. */ + xAddress = ( portPOINTER_SIZE_TYPE ) pxHeapRegion->pucStartAddress; + + if( ( xAddress & portBYTE_ALIGNMENT_MASK ) != 0 ) + { + xAddress += ( portBYTE_ALIGNMENT - 1 ); + xAddress &= ~( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK; + + /* Adjust the size for the bytes lost to alignment. */ + xTotalRegionSize -= ( size_t ) ( xAddress - ( portPOINTER_SIZE_TYPE ) pxHeapRegion->pucStartAddress ); + } + + xAlignedHeap = xAddress; + + /* Set xStart if it has not already been set. */ + if( xDefinedRegions == 0 ) + { + /* xStart is used to hold a pointer to the first item in the list of + * free blocks. The void cast is used to prevent compiler warnings. */ + xStart.pxNextFreeBlock = ( BlockLink_t * ) heapPROTECT_BLOCK_POINTER( xAlignedHeap ); + xStart.xBlockSize = ( size_t ) 0; + } + else + { + /* Should only get here if one region has already been added to the + * heap. */ + configASSERT( pxEnd != heapPROTECT_BLOCK_POINTER( NULL ) ); + + /* Check blocks are passed in with increasing start addresses. */ + configASSERT( ( size_t ) xAddress > ( size_t ) pxEnd ); + } + + #if ( configENABLE_HEAP_PROTECTOR == 1 ) + { + if( ( pucHeapLowAddress == NULL ) || + ( ( uint8_t * ) xAlignedHeap < pucHeapLowAddress ) ) + { + pucHeapLowAddress = ( uint8_t * ) xAlignedHeap; + } + } + #endif /* configENABLE_HEAP_PROTECTOR */ + + /* Remember the location of the end marker in the previous region, if + * any. */ + pxPreviousFreeBlock = pxEnd; + + /* pxEnd is used to mark the end of the list of free blocks and is + * inserted at the end of the region space. */ + xAddress = xAlignedHeap + ( portPOINTER_SIZE_TYPE ) xTotalRegionSize; + xAddress -= ( portPOINTER_SIZE_TYPE ) xHeapStructSize; + xAddress &= ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ); + pxEnd = ( BlockLink_t * ) xAddress; + pxEnd->xBlockSize = 0; + pxEnd->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( NULL ); + + /* To start with there is a single free block in this region that is + * sized to take up the entire heap region minus the space taken by the + * free block structure. */ + pxFirstFreeBlockInRegion = ( BlockLink_t * ) xAlignedHeap; + pxFirstFreeBlockInRegion->xBlockSize = ( size_t ) ( xAddress - ( portPOINTER_SIZE_TYPE ) pxFirstFreeBlockInRegion ); + pxFirstFreeBlockInRegion->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxEnd ); + + /* If this is not the first region that makes up the entire heap space + * then link the previous region to this region. */ + if( pxPreviousFreeBlock != NULL ) + { + pxPreviousFreeBlock->pxNextFreeBlock = heapPROTECT_BLOCK_POINTER( pxFirstFreeBlockInRegion ); + } + + xTotalHeapSize += pxFirstFreeBlockInRegion->xBlockSize; + + #if ( configENABLE_HEAP_PROTECTOR == 1 ) + { + if( ( pucHeapHighAddress == NULL ) || + ( ( ( ( uint8_t * ) pxFirstFreeBlockInRegion ) + pxFirstFreeBlockInRegion->xBlockSize ) > pucHeapHighAddress ) ) + { + pucHeapHighAddress = ( ( uint8_t * ) pxFirstFreeBlockInRegion ) + pxFirstFreeBlockInRegion->xBlockSize; + } + } + #endif + + /* Move onto the next HeapRegion_t structure. */ + xDefinedRegions++; + pxHeapRegion = &( pxHeapRegions[ xDefinedRegions ] ); + } + + xMinimumEverFreeBytesRemaining = xTotalHeapSize; + xFreeBytesRemaining = xTotalHeapSize; + + /* Check something was actually defined before it is accessed. */ + configASSERT( xTotalHeapSize ); +} +/*-----------------------------------------------------------*/ + +void vPortGetHeapStats( HeapStats_t * pxHeapStats ) +{ + BlockLink_t * pxBlock; + size_t xBlocks = 0, xMaxSize = 0, xMinSize = SIZE_MAX; + + vTaskSuspendAll(); + { + pxBlock = heapPROTECT_BLOCK_POINTER( xStart.pxNextFreeBlock ); + + /* pxBlock will be NULL if the heap has not been initialised. The heap + * is initialised automatically when the first allocation is made. */ + if( pxBlock != NULL ) + { + while( pxBlock != pxEnd ) + { + /* Increment the number of blocks and record the largest block seen + * so far. */ + xBlocks++; + + if( pxBlock->xBlockSize > xMaxSize ) + { + xMaxSize = pxBlock->xBlockSize; + } + + /* Heap five will have a zero sized block at the end of each + * each region - the block is only used to link to the next + * heap region so it not a real block. */ + if( pxBlock->xBlockSize != 0 ) + { + if( pxBlock->xBlockSize < xMinSize ) + { + xMinSize = pxBlock->xBlockSize; + } + } + + /* Move to the next block in the chain until the last block is + * reached. */ + pxBlock = heapPROTECT_BLOCK_POINTER( pxBlock->pxNextFreeBlock ); + } + } + } + ( void ) xTaskResumeAll(); + + pxHeapStats->xSizeOfLargestFreeBlockInBytes = xMaxSize; + pxHeapStats->xSizeOfSmallestFreeBlockInBytes = xMinSize; + pxHeapStats->xNumberOfFreeBlocks = xBlocks; + + taskENTER_CRITICAL(); + { + pxHeapStats->xAvailableHeapSpaceInBytes = xFreeBytesRemaining; + pxHeapStats->xNumberOfSuccessfulAllocations = xNumberOfSuccessfulAllocations; + pxHeapStats->xNumberOfSuccessfulFrees = xNumberOfSuccessfulFrees; + pxHeapStats->xMinimumEverFreeBytesRemaining = xMinimumEverFreeBytesRemaining; + } + taskEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +/* + * Reset the state in this file. This state is normally initialized at start up. + * This function must be called by the application before restarting the + * scheduler. + */ +void vPortHeapResetState( void ) +{ + pxEnd = NULL; + + xFreeBytesRemaining = ( size_t ) 0U; + xMinimumEverFreeBytesRemaining = ( size_t ) 0U; + xNumberOfSuccessfulAllocations = ( size_t ) 0U; + xNumberOfSuccessfulFrees = ( size_t ) 0U; + + #if ( configENABLE_HEAP_PROTECTOR == 1 ) + pucHeapHighAddress = NULL; + pucHeapLowAddress = NULL; + #endif /* #if ( configENABLE_HEAP_PROTECTOR == 1 ) */ +} +/*-----------------------------------------------------------*/ diff --git a/portable/MikroC/ARM_CM4F/port.c b/portable/MikroC/ARM_CM4F/port.c new file mode 100644 index 000000000..a167f8588 --- /dev/null +++ b/portable/MikroC/ARM_CM4F/port.c @@ -0,0 +1,915 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ARM CM4F port. +*----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to manipulate the core. Registers first... */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +/* ...then bits in the registers. */ +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) + +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL ) +#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL ) + +/* Constants required to check the validity of an interrupt priority. */ +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) + +/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */ +#define portVECTACTIVE_MASK ( 0xFFUL ) + +/* Constants required to manipulate the VFP. */ +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */ +#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) +#define portINITIAL_EXC_RETURN ( 0xfffffffd ) + +/* The systick is a 24-bit counter. */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/* A fiddle factor to estimate the number of SysTick counts that would have + * occurred while the SysTick counter is stopped during tickless idle + * calculations. */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) + +/* Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/* Let the user override the pre-loading of the initial LR with the address of + * prvTaskExitError() in case it messes up unwinding of the stack in the + * debugger. */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/* Cannot find a weak linkage attribute, so the + * configOVERRIDE_DEFAULT_TICK_CONFIGURATION constant must be set to 1 if the + * application writer wants to provide their own implementation of + * vPortSetupTimerInterrupt(). Ensure configOVERRIDE_DEFAULT_TICK_CONFIGURATION + * is defined. */ +#ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION + #define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 0 +#endif + +/* Manual definition of missing asm names. */ +#define psp 9 +#define basepri 17 +#define msp 8 +#define ipsr 5 +#define control 20 + +/* From port.c. */ +extern void * pxCurrentTCB; + +/* Each task maintains its own interrupt status in the critical nesting + * variable. */ +static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ); + +/* + * Exception handlers. + */ +void xPortPendSVHandler( void ); +void xPortSysTickHandler( void ); +void vPortSVCHandler( void ); + +/* + * Start first task is a separate function so it can be tested in isolation. + */ +static void prvPortStartFirstTask( void ); + +/* + * Function to enable the VFP. + */ +static void vPortEnableVFP( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* + * The number of SysTick increments that make up one tick period. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulTimerCountsForOneTick = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * The maximum number of tick periods that can be suppressed is limited by the + * 24 bit resolution of the SysTick timer. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t xMaximumPossibleSuppressedTicks = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Compensate for the CPU cycles that pass while the SysTick is stopped (low + * power functionality only. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( configASSERT_DEFINED == 1 ) + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; +#endif /* configASSERT_DEFINED */ + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + + /* Offset added to account for the way the MCU uses the stack on entry/exit + * of interrupts, and to ensure alignment. */ + pxTopOfStack--; + + /* Sometimes the parameters are loaded from the stack. */ + *pxTopOfStack = ( StackType_t ) pvParameters; + pxTopOfStack--; + + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + + /* Save code space by skipping register initialisation. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + + /* A save method is being used that requires each task to maintain its + * own exec return value. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; + + pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ + configASSERT( uxCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler( void ) iv IVT_INT_SVCall ics ICS_OFF +{ + __asm { +/* *INDENT-OFF* */ + ldr r3, =_pxCurrentTCB /* Restore the context. */ + ldr r1, [ r3 ] /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */ + ldr r0, [ r1 ] /* The first item in pxCurrentTCB is the task top of stack. */ + ldm r0 !, ( r4 - r11, r14 ) /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */ + msr psp, r0 /* Restore the task stack pointer. */ + isb + mov r0, #0 + msr basepri, r0 + bx r14 +/* *INDENT-ON* */ + }; +} +/*-----------------------------------------------------------*/ + +static void prvPortStartFirstTask( void ) +{ + __asm { +/* *INDENT-OFF* */ + ldr r0, =0xE000ED08 /* Use the NVIC offset register to locate the stack. */ + ldr r0, [ r0 ] + ldr r0, [ r0 ] + msr msp, r0 /* Set the msp back to the start of the stack. */ + + /* Clear the bit that indicates the FPU is in use in case the FPU was used + * before the scheduler was started - which would otherwise result in the + * unnecessary leaving of space in the SVC stack for lazy saving of FPU + * registers. */ + mov r0, #0 + msr control, r0 + cpsie i /* Globally enable interrupts. */ + cpsie f + dsb + isb + svc #0 /* System call to start first task. */ + nop +/* *INDENT-ON* */ + }; +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + #if ( configASSERT_DEFINED == 1 ) + { + volatile uint8_t ucOriginalPriority; + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * Save the interrupt priority value that is about to be clobbered. */ + ucOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to all + * possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + + /* Restore the clobbered interrupt priority register to its original + * value. */ + *pucFirstUserPriorityRegister = ucOriginalPriority; + } + #endif /* configASSERT_DEFINED */ + + /* Make PendSV and SysTick the lowest priority interrupts. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + /* Ensure the VFP is enabled - it should be anyway. */ + vPortEnableVFP(); + + /* Lazy save always. */ + *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; + + /* Start the first task. */ + prvPortStartFirstTask(); + + /* Should never get here as the tasks will now be executing! Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. */ + prvTaskExitError(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ + if( uxCriticalNesting == 1 ) + { + configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +const uint8_t ucMaxSyscallInterruptPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY; +void xPortPendSVHandler( void ) iv IVT_INT_PendSV ics ICS_OFF +{ + __asm { + #ifdef HW_DEBUG +/* *INDENT-OFF* */ + + /* The function is not truly naked, so add back the 4 bytes subtracted + * from the stack pointer by the function prologue. */ + add sp, sp, # 4 + #endif + mrs r0, psp + isb + + ldr r3, =_pxCurrentTCB /* Get the location of the current TCB. */ + ldr r2, [ r3 ] + + tst r14, #0x10 /* Is the task using the FPU context? If so, push high vfp registers. */ + it eq + vstmdbeq r0 !, ( s16 - s31 ) + + stmdb r0 !, ( r4 - r11, r14 ) /* Save the core registers. */ + + str r0, [ r2 ] /* Save the new top of stack into the first member of the TCB. */ + + stmdb sp !, ( r0, r3 ) + ldr r0, = _ucMaxSyscallInterruptPriority + ldr r1, [ r0 ] + msr basepri, r1 + dsb + isb + bl _vTaskSwitchContext + mov r0, #0 + msr basepri, r0 + ldm sp !, ( r0, r3 ) + + ldr r1, [ r3 ] /* The first item in pxCurrentTCB is the task top of stack. */ + ldr r0, [ r1 ] + + ldm r0 !, ( r4 - r11, r14 ) /* Pop the core registers. */ + + tst r14, #0x10 /* Is the task using the FPU context? If so, pop the high vfp registers too. */ + it eq + vldmiaeq r0 !, ( s16 - s31 ) + + msr psp, r0 + isb + bx r14 +/* *INDENT-ON* */ + } +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) iv IVT_INT_SysTick ics ICS_AUTO +{ + /* The SysTick runs at the lowest interrupt priority, so when this interrupt + * executes all interrupts must be unmasked. There is therefore no need to + * save and then restore the interrupt mask value as its value is already + * known - therefore the slightly faster portDISABLE_INTERRUPTS() function is + * used in place of portSET_INTERRUPT_MASK_FROM_ISR(). */ + portDISABLE_INTERRUPTS(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + + /* A context switch is required. Context switching is performed in + * the PendSV interrupt. Pend the PendSV interrupt. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + portENABLE_INTERRUPTS(); +} +/*-----------------------------------------------------------*/ + + #if ( ( configUSE_TICKLESS_IDLE == 1 ) && ( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 ) ) + + void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm { + "cpsid i" + }; + __asm { + "dsb" + }; + __asm { + "isb" + }; + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the cpsid instruction + * above. */ + __asm { + "cpsie i" + }; + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm { + "dsb" + }; + __asm { + "wfi" + }; + __asm { + "isb" + }; + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the cpsid instruction above. */ + __asm { + "cpsie i" + }; + __asm { + "dsb" + }; + __asm { + "isb" + }; + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm { + "cpsid i" + }; + __asm { + "dsb" + }; + __asm { + "isb" + }; + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __asm { + "cpsie i" + }; + } + } + + #endif /* #if configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ + #if ( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 ) + + void vPortSetupTimerInterrupt( void ) + { + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Reset SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); + } + + #endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */ +/*-----------------------------------------------------------*/ + +/* This is a naked function. */ +static void vPortEnableVFP( void ) +{ + __asm { +/* *INDENT-OFF* */ + ldr r0, =0xE000ED88 /* The FPU enable bits are in the CPACR. */ + ldr r1, [ r0 ] + + orr r1, r1, #0xF00000 /* Enable CP10 and CP11 coprocessors, then save back. */ + str r1, [ r0 ] + bx r14 +/* *INDENT-ON* */ + }; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsInsideInterrupt( void ) +{ + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + if( CPU_REG_GET( CPU_IPSR ) == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + + #if ( configASSERT_DEFINED == 1 ) + +/* Limitations in the MikroC inline asm means ulCurrentInterrupt has to be + * global - which makes vPortValidateInterruptPriority() non re-entrant. + * However that should not matter as an interrupt can only itself be + * interrupted by a higher priority interrupt. That means if + * ulCurrentInterrupt, so ulCurrentInterrupt getting corrupted cannot lead to + * an invalid interrupt priority being missed. */ + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + void vPortValidateInterruptPriority( void ) + { + /* Obtain the number of the currently executing interrupt. */ + __asm { +/* *INDENT-OFF* */ + push( r0, r1 ) + mrs r0, ipsr + ldr r1, =_ulCurrentInterrupt + str r0, [ r1 ] + pop( r0, r1 ) +/* *INDENT-ON* */ + }; + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = *( ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + ulCurrentInterrupt ) ); + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + + #endif /* configASSERT_DEFINED */ diff --git a/portable/MikroC/ARM_CM4F/portmacro.h b/portable/MikroC/ARM_CM4F/portmacro.h new file mode 100644 index 000000000..d6cd752e4 --- /dev/null +++ b/portable/MikroC/ARM_CM4F/portmacro.h @@ -0,0 +1,208 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H + #define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* The compiler needs to be told functions that are only referenced by pointer + * are to be included in the build. NOTE: Omitting these lines will result in a + * run-time crash, not a linker error! */ + #pragma funcall vTaskStartScheduler prvIdleTask + #pragma funcall xTimerCreateTimerTask prvTimerTask + +/* Type definitions. */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. + #endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 +/*-----------------------------------------------------------*/ + +/* Scheduler utilities. */ + #define portYIELD() \ + { \ + /* Set a PendSV to request a context switch. */ \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + \ + /* Barriers are normally not required but do ensure the code is completely \ + * within the specified behaviour for the architecture. */ \ + __asm{ dsb }; \ + __asm{ isb }; \ + } + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portYIELD(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ + extern void vPortEnterCritical( void ); + extern void vPortExitCritical( void ); + #define portDISABLE_INTERRUPTS() CPU_REG_SET( CPU_BASEPRI, configMAX_SYSCALL_INTERRUPT_PRIORITY ); __asm{ dsb }; __asm{ isb } + #define portENABLE_INTERRUPTS() CPU_REG_SET( CPU_BASEPRI, 0 ); + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() + #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) CPU_REG_SET( CPU_BASEPRI, x ); /* Barrier instructions not used as this is only used to lower the basepri. */ + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not necessary for to use this port. They are defined so the common demo files + * (which build with all the ports) will build. */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +/* Tickless idle/low power functionality. */ + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif +/*-----------------------------------------------------------*/ + +/* Architecture specific optimisations. */ + #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #endif + + #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + +/* Generic helper function. */ + __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint8_t ucReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) ); + + return ucReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + + #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/*-----------------------------------------------------------*/ + + #if ( configASSERT_DEFINED == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif + +/* portNOP() is not required by this port. */ + #define portNOP() + + BaseType_t xPortIsInsideInterrupt( void ); + +/*-----------------------------------------------------------*/ + + static inline uint32_t ulPortRaiseBASEPRI( void ) + { + uint32_t ulOriginalBASEPRI; + + ulOriginalBASEPRI = CPU_REG_GET( CPU_BASEPRI ); + CPU_REG_SET( CPU_BASEPRI, configMAX_SYSCALL_INTERRUPT_PRIORITY ); + __asm{ dsb }; + __asm{ isb }; + return ulOriginalBASEPRI; + } +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/Paradigm/Tern_EE/large_untested/port.c b/portable/Paradigm/Tern_EE/large_untested/port.c new file mode 100644 index 000000000..443104885 --- /dev/null +++ b/portable/Paradigm/Tern_EE/large_untested/port.c @@ -0,0 +1,233 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the Tern EE 186 + * port. + *----------------------------------------------------------*/ + +/* Library includes. */ +#include +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "portasm.h" + +/* The timer increments every four clocks, hence the divide by 4. */ +#define portTIMER_COMPARE ( uint16_t ) ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) / ( uint32_t ) 4 ) + +/* From the RDC data sheet. */ +#define portENABLE_TIMER_AND_INTERRUPT ( uint16_t ) 0xe001 + +/* Interrupt control. */ +#define portEIO_REGISTER 0xff22 +#define portCLEAR_INTERRUPT 0x0008 + +/* Setup the hardware to generate the required tick frequency. */ +static void prvSetupTimerInterrupt( void ); + +/* The ISR used depends on whether the preemptive or cooperative scheduler +is being used. */ +#if( configUSE_PREEMPTION == 1 ) + /* Tick service routine used by the scheduler when preemptive scheduling is + being used. */ + static void __interrupt __far prvPreemptiveTick( void ); +#else + /* Tick service routine used by the scheduler when cooperative scheduling is + being used. */ + static void __interrupt __far prvNonPreemptiveTick( void ); +#endif + +/* Trap routine used by taskYIELD() to manually cause a context switch. */ +static void __interrupt __far prvYieldProcessor( void ); + +/* The timer initialisation functions leave interrupts enabled, +which is not what we want. This ISR is installed temporarily in case +the timer fires before we get a change to disable interrupts again. */ +static void __interrupt __far prvDummyISR( void ); + +/*-----------------------------------------------------------*/ +/* See header file for description. */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +StackType_t DS_Reg = 0; + + /* Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging. */ + + *pxTopOfStack = 0x1111; + pxTopOfStack--; + *pxTopOfStack = 0x2222; + pxTopOfStack--; + *pxTopOfStack = 0x3333; + pxTopOfStack--; + + /* We are going to start the scheduler using a return from interrupt + instruction to load the program counter, so first there would be the + function call with parameters preamble. */ + + *pxTopOfStack = FP_SEG( pvParameters ); + pxTopOfStack--; + *pxTopOfStack = FP_OFF( pvParameters ); + pxTopOfStack--; + *pxTopOfStack = FP_SEG( pxCode ); + pxTopOfStack--; + *pxTopOfStack = FP_OFF( pxCode ); + pxTopOfStack--; + + /* Next the status register and interrupt return address. */ + *pxTopOfStack = portINITIAL_SW; + pxTopOfStack--; + *pxTopOfStack = FP_SEG( pxCode ); + pxTopOfStack--; + *pxTopOfStack = FP_OFF( pxCode ); + pxTopOfStack--; + + /* The remaining registers would be pushed on the stack by our context + switch function. These are loaded with values simply to make debugging + easier. */ + *pxTopOfStack = ( StackType_t ) 0xAAAA; /* AX */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xBBBB; /* BX */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xCCCC; /* CX */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xDDDD; /* DX */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xEEEE; /* ES */ + pxTopOfStack--; + + /* We need the true data segment. */ + __asm{ MOV DS_Reg, DS }; + + *pxTopOfStack = DS_Reg; /* DS */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x0123; /* SI */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xDDDD; /* DI */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xBBBB; /* BP */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* This is called with interrupts already disabled. */ + + /* Put our manual switch (yield) function on a known + vector. */ + setvect( portSWITCH_INT_NUMBER, prvYieldProcessor ); + + /* Setup the tick interrupt. */ + prvSetupTimerInterrupt(); + + /* Kick off the scheduler by setting up the context of the first task. */ + portFIRST_CONTEXT(); + + /* Should not get here! */ + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +static void __interrupt __far prvDummyISR( void ) +{ + /* The timer initialisation functions leave interrupts enabled, + which is not what we want. This ISR is installed temporarily in case + the timer fires before we get a change to disable interrupts again. */ + outport( portEIO_REGISTER, portCLEAR_INTERRUPT ); +} +/*-----------------------------------------------------------*/ + +/* The ISR used depends on whether the preemptive or cooperative scheduler +is being used. */ +#if( configUSE_PREEMPTION == 1 ) + static void __interrupt __far prvPreemptiveTick( void ) + { + /* Get the scheduler to update the task states following the tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Switch in the context of the next task to be run. */ + portSWITCH_CONTEXT(); + } + + /* Reset interrupt. */ + outport( portEIO_REGISTER, portCLEAR_INTERRUPT ); + } +#else + static void __interrupt __far prvNonPreemptiveTick( void ) + { + /* Same as preemptive tick, but the cooperative scheduler is being used + so we don't have to switch in the context of the next task. */ + xTaskIncrementTick(); + + /* Reset interrupt. */ + outport( portEIO_REGISTER, portCLEAR_INTERRUPT ); + } +#endif +/*-----------------------------------------------------------*/ + +static void __interrupt __far prvYieldProcessor( void ) +{ + /* Switch in the context of the next task to be run. */ + portSWITCH_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented. */ +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ +const uint16_t usTimerACompare = portTIMER_COMPARE, usTimerAMode = portENABLE_TIMER_AND_INTERRUPT; +const uint16_t usT2_IRQ = 0x13; + + /* Configure the timer, the dummy handler is used here as the init + function leaves interrupts enabled. */ + t2_init( usTimerAMode, usTimerACompare, prvDummyISR ); + + /* Disable interrupts again before installing the real handlers. */ + portDISABLE_INTERRUPTS(); + + #if( configUSE_PREEMPTION == 1 ) + /* Tick service routine used by the scheduler when preemptive scheduling is + being used. */ + setvect( usT2_IRQ, prvPreemptiveTick ); + #else + /* Tick service routine used by the scheduler when cooperative scheduling is + being used. */ + setvect( usT2_IRQ, prvNonPreemptiveTick ); + #endif +} diff --git a/portable/Paradigm/Tern_EE/large_untested/portasm.h b/portable/Paradigm/Tern_EE/large_untested/portasm.h new file mode 100644 index 000000000..cf9e711c8 --- /dev/null +++ b/portable/Paradigm/Tern_EE/large_untested/portasm.h @@ -0,0 +1,75 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +typedef void TCB_t; +extern volatile TCB_t * volatile pxCurrentTCB; +extern void vTaskSwitchContext( void ); + +/* + * Saves the stack pointer for one task into its TCB, calls + * vTaskSwitchContext() to update the TCB being used, then restores the stack + * from the new TCB read to run the task. + */ +void portSWITCH_CONTEXT( void ); + +/* + * Load the stack pointer from the TCB of the task which is going to be first + * to execute. Then force an IRET so the registers and IP are popped off the + * stack. + */ +void portFIRST_CONTEXT( void ); + +#define portSWITCH_CONTEXT() \ + asm { mov ax, seg pxCurrentTCB } \ + asm { mov ds, ax } \ + asm { les bx, pxCurrentTCB } /* Save the stack pointer into the TCB. */ \ + asm { mov es:0x2[ bx ], ss } \ + asm { mov es:[ bx ], sp } \ + asm { call far ptr vTaskSwitchContext } /* Perform the switch. */ \ + asm { mov ax, seg pxCurrentTCB } /* Restore the stack pointer from the TCB. */ \ + asm { mov ds, ax } \ + asm { les bx, dword ptr pxCurrentTCB } \ + asm { mov ss, es:[ bx + 2 ] } \ + asm { mov sp, es:[ bx ] } + +#define portFIRST_CONTEXT() \ + asm { mov ax, seg pxCurrentTCB } \ + asm { mov ds, ax } \ + asm { les bx, dword ptr pxCurrentTCB } \ + asm { mov ss, es:[ bx + 2 ] } \ + asm { mov sp, es:[ bx ] } \ + asm { pop bp } \ + asm { pop di } \ + asm { pop si } \ + asm { pop ds } \ + asm { pop es } \ + asm { pop dx } \ + asm { pop cx } \ + asm { pop bx } \ + asm { pop ax } \ + asm { iret } diff --git a/portable/Paradigm/Tern_EE/large_untested/portmacro.h b/portable/Paradigm/Tern_EE/large_untested/portmacro.h new file mode 100644 index 000000000..1ea0c3176 --- /dev/null +++ b/portable/Paradigm/Tern_EE/large_untested/portmacro.h @@ -0,0 +1,112 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE long +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE uint16_t +#define portBASE_TYPE short + +typedef portSTACK_TYPE StackType_t; +typedef short BaseType_t; +typedef unsigned short UBaseType_t; + + +#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +#define portENTER_CRITICAL() __asm{ pushf } \ + __asm{ cli } \ + +#define portEXIT_CRITICAL() __asm{ popf } + +#define portDISABLE_INTERRUPTS() __asm{ cli } + +#define portENABLE_INTERRUPTS() __asm{ sti } +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portNOP() __asm{ nop } +#define portSTACK_GROWTH ( -1 ) +#define portSWITCH_INT_NUMBER 0x80 +#define portYIELD() __asm{ int portSWITCH_INT_NUMBER } +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 2 +#define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */ +/*-----------------------------------------------------------*/ + +/* Compiler specifics. */ +#define portINPUT_BYTE( xAddr ) inp( xAddr ) +#define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue ) +#define portINPUT_WORD( xAddr ) inpw( xAddr ) +#define portOUTPUT_WORD( xAddr, usValue ) outpw( xAddr, usValue ) +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters ) +#define portTASK_FUNCTION( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + + +#endif /* PORTMACRO_H */ diff --git a/portable/Paradigm/Tern_EE/small/port.c b/portable/Paradigm/Tern_EE/small/port.c new file mode 100644 index 000000000..75273f225 --- /dev/null +++ b/portable/Paradigm/Tern_EE/small/port.c @@ -0,0 +1,213 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the Tern EE 186 + * port. + *----------------------------------------------------------*/ + +/* Library includes. */ +#include +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "portasm.h" + +/* The timer increments every four clocks, hence the divide by 4. */ +#define portPRESCALE_VALUE ( 16 ) +#define portTIMER_COMPARE ( configCPU_CLOCK_HZ / ( configTICK_RATE_HZ * 4UL ) ) + +/* From the RDC data sheet. */ +#define portENABLE_TIMER_AND_INTERRUPT ( uint16_t ) 0xe00b +#define portENABLE_TIMER ( uint16_t ) 0xC001 + +/* Interrupt control. */ +#define portEIO_REGISTER 0xff22 +#define portCLEAR_INTERRUPT 0x0008 + +/* Setup the hardware to generate the required tick frequency. */ +static void prvSetupTimerInterrupt( void ); + +/* The ISR used depends on whether the preemptive or cooperative scheduler +is being used. */ +#if( configUSE_PREEMPTION == 1 ) + /* Tick service routine used by the scheduler when preemptive scheduling is + being used. */ + static void __interrupt __far prvPreemptiveTick( void ); +#else + /* Tick service routine used by the scheduler when cooperative scheduling is + being used. */ + static void __interrupt __far prvNonPreemptiveTick( void ); +#endif + +/* Trap routine used by taskYIELD() to manually cause a context switch. */ +static void __interrupt __far prvYieldProcessor( void ); + +/*-----------------------------------------------------------*/ +/* See header file for description. */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +StackType_t DS_Reg = 0; + + /* We need the true data segment. */ + __asm{ MOV DS_Reg, DS }; + + /* Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging. */ + + *pxTopOfStack = 0x1111; + pxTopOfStack--; + *pxTopOfStack = 0x2222; + pxTopOfStack--; + *pxTopOfStack = 0x3333; + pxTopOfStack--; + + /* We are going to start the scheduler using a return from interrupt + instruction to load the program counter, so first there would be the + function call with parameters preamble. */ + + *pxTopOfStack = FP_OFF( pvParameters ); + pxTopOfStack--; + *pxTopOfStack = FP_OFF( pxCode ); + pxTopOfStack--; + + /* Next the status register and interrupt return address. */ + *pxTopOfStack = portINITIAL_SW; + pxTopOfStack--; + *pxTopOfStack = FP_SEG( pxCode ); + pxTopOfStack--; + *pxTopOfStack = FP_OFF( pxCode ); + pxTopOfStack--; + + /* The remaining registers would be pushed on the stack by our context + switch function. These are loaded with values simply to make debugging + easier. */ + *pxTopOfStack = ( StackType_t ) 0xAAAA; /* AX */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xBBBB; /* BX */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xCCCC; /* CX */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xDDDD; /* DX */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xEEEE; /* ES */ + pxTopOfStack--; + + *pxTopOfStack = DS_Reg; /* DS */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x0123; /* SI */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xDDDD; /* DI */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xBBBB; /* BP */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* This is called with interrupts already disabled. */ + + /* Put our manual switch (yield) function on a known + vector. */ + setvect( portSWITCH_INT_NUMBER, prvYieldProcessor ); + + /* Setup the tick interrupt. */ + prvSetupTimerInterrupt(); + + /* Kick off the scheduler by setting up the context of the first task. */ + portFIRST_CONTEXT(); + + /* Should not get here! */ + return pdFALSE; +} +/*-----------------------------------------------------------*/ + +/* The ISR used depends on whether the preemptive or cooperative scheduler +is being used. */ +#if( configUSE_PREEMPTION == 1 ) + static void __interrupt __far prvPreemptiveTick( void ) + { + /* Get the scheduler to update the task states following the tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Switch in the context of the next task to be run. */ + portEND_SWITCHING_ISR(); + } + + /* Reset interrupt. */ + outport( portEIO_REGISTER, portCLEAR_INTERRUPT ); + } +#else + static void __interrupt __far prvNonPreemptiveTick( void ) + { + /* Same as preemptive tick, but the cooperative scheduler is being used + so we don't have to switch in the context of the next task. */ + xTaskIncrementTick(); + + /* Reset interrupt. */ + outport( portEIO_REGISTER, portCLEAR_INTERRUPT ); + } +#endif +/*-----------------------------------------------------------*/ + +static void __interrupt __far prvYieldProcessor( void ) +{ + /* Switch in the context of the next task to be run. */ + portEND_SWITCHING_ISR(); +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented. */ +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ +const uint32_t ulCompareValue = portTIMER_COMPARE; +uint16_t usTimerCompare; + + usTimerCompare = ( uint16_t ) ( ulCompareValue >> 4 ); + t2_init( portENABLE_TIMER, portPRESCALE_VALUE, NULL ); + + #if( configUSE_PREEMPTION == 1 ) + /* Tick service routine used by the scheduler when preemptive scheduling is + being used. */ + t1_init( portENABLE_TIMER_AND_INTERRUPT, usTimerCompare, usTimerCompare, prvPreemptiveTick ); + #else + /* Tick service routine used by the scheduler when cooperative scheduling is + being used. */ + t1_init( portENABLE_TIMER_AND_INTERRUPT, usTimerCompare, usTimerCompare, prvNonPreemptiveTick ); + #endif +} diff --git a/portable/Paradigm/Tern_EE/small/portasm.h b/portable/Paradigm/Tern_EE/small/portasm.h new file mode 100644 index 000000000..88ef3ba99 --- /dev/null +++ b/portable/Paradigm/Tern_EE/small/portasm.h @@ -0,0 +1,72 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORT_ASM_H +#define PORT_ASM_H + +typedef void TCB_t; +extern volatile TCB_t * volatile pxCurrentTCB; +extern void vTaskSwitchContext( void ); + +/* + * Saves the stack pointer for one task into its TCB, calls + * vTaskSwitchContext() to update the TCB being used, then restores the stack + * from the new TCB read to run the task. + */ +void portEND_SWITCHING_ISR( void ); + +/* + * Load the stack pointer from the TCB of the task which is going to be first + * to execute. Then force an IRET so the registers and IP are popped off the + * stack. + */ +void portFIRST_CONTEXT( void ); + +#define portEND_SWITCHING_ISR() \ + asm { mov bx, [pxCurrentTCB] } \ + asm { mov word ptr [bx], sp } \ + asm { call far ptr vTaskSwitchContext } \ + asm { mov bx, [pxCurrentTCB] } \ + asm { mov sp, [bx] } + +#define portFIRST_CONTEXT() \ + asm { mov bx, [pxCurrentTCB] } \ + asm { mov sp, [bx] } \ + asm { pop bp } \ + asm { pop di } \ + asm { pop si } \ + asm { pop ds } \ + asm { pop es } \ + asm { pop dx } \ + asm { pop cx } \ + asm { pop bx } \ + asm { pop ax } \ + asm { iret } + + +#endif diff --git a/portable/Paradigm/Tern_EE/small/portmacro.h b/portable/Paradigm/Tern_EE/small/portmacro.h new file mode 100644 index 000000000..0ab083838 --- /dev/null +++ b/portable/Paradigm/Tern_EE/small/portmacro.h @@ -0,0 +1,113 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE long +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE uint16_t +#define portBASE_TYPE short + +typedef portSTACK_TYPE StackType_t; +typedef short BaseType_t; +typedef unsigned short UBaseType_t; + + +typedef void ( __interrupt __far *pxISR )(); + +#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +#define portENTER_CRITICAL() __asm{ pushf } \ + __asm{ cli } \ + +#define portEXIT_CRITICAL() __asm{ popf } + +#define portDISABLE_INTERRUPTS() __asm{ cli } + +#define portENABLE_INTERRUPTS() __asm{ sti } +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portNOP() __asm{ nop } +#define portSTACK_GROWTH ( -1 ) +#define portSWITCH_INT_NUMBER 0x80 +#define portYIELD() __asm{ int portSWITCH_INT_NUMBER } +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 2 +#define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */ +/*-----------------------------------------------------------*/ + +/* Compiler specifics. */ +#define portINPUT_BYTE( xAddr ) inp( xAddr ) +#define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue ) +#define portINPUT_WORD( xAddr ) inpw( xAddr ) +#define portOUTPUT_WORD( xAddr, usValue ) outpw( xAddr, usValue ) +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters ) +#define portTASK_FUNCTION( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/RVDS/ARM7_LPC21xx/port.c b/portable/RVDS/ARM7_LPC21xx/port.c new file mode 100644 index 000000000..5476af8c9 --- /dev/null +++ b/portable/RVDS/ARM7_LPC21xx/port.c @@ -0,0 +1,292 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to setup the initial task context. */ +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) +#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 ) + +/* Constants required to setup the tick ISR. */ +#define portENABLE_TIMER ( ( uint8_t ) 0x01 ) +#define portPRESCALE_VALUE 0x00 +#define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 ) +#define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 ) + +/* Constants required to setup the VIC for the tick ISR. */ +#define portTIMER_VIC_CHANNEL ( ( uint32_t ) 0x0004 ) +#define portTIMER_VIC_CHANNEL_BIT ( ( uint32_t ) 0x0010 ) +#define portTIMER_VIC_ENABLE ( ( uint32_t ) 0x0020 ) + +/* Constants required to handle interrupts. */ +#define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 ) +#define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 ) + +/*-----------------------------------------------------------*/ + +/* The code generated by the Keil compiler does not maintain separate + * stack and frame pointers. The portENTER_CRITICAL macro cannot therefore + * use the stack as per other ports. Instead a variable is used to keep + * track of the critical section nesting. This variable has to be stored + * as part of the task context and must be initialised to a non zero value. */ + +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) +volatile uint32_t ulCriticalNesting = 9999UL; + +/*-----------------------------------------------------------*/ + +/* Setup the timer to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* + * The scheduler can only be started from ARM mode, so + * vPortStartFirstSTask() is defined in portISR.c. + */ +extern __asm void vPortStartFirstTask( void ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + StackType_t * pxOriginalTOS; + + /* Setup the initial stack of the task. The stack is set exactly as + * expected by the portRESTORE_CONTEXT() macro. + * + * Remember where the top of the (simulated) stack is before we place + * anything on it. */ + pxOriginalTOS = pxTopOfStack; + + /* To ensure asserts in tasks.c don't fail, although in this case the assert + * is not really required. */ + pxTopOfStack--; + + /* First on the stack is the return address - which in this case is the + * start of the task. The offset is added to make the return address appear + * as it would within an IRQ ISR. */ + *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The last thing onto the stack is the status register, which is set for + * system mode, with interrupts enabled. */ + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + + if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00UL ) + { + /* We want the task to start in thumb mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + + pxTopOfStack--; + + /* The code generated by the Keil compiler does not maintain separate + * stack and frame pointers. The portENTER_CRITICAL macro cannot therefore + * use the stack as per other ports. Instead a variable is used to keep + * track of the critical section nesting. This variable has to be stored + * as part of the task context and is initially set to zero. */ + *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Start the timer that generates the tick ISR. */ + prvSetupTimerInterrupt(); + + /* Start the first task. This is done from portISR.c as ARM mode must be + * used. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + * is nothing to return to. If this is required - stop the tick ISR then + * return back to main. */ +} +/*-----------------------------------------------------------*/ + +#if configUSE_PREEMPTION == 0 + +/* + * The cooperative scheduler requires a normal IRQ service routine to + * simply increment the system tick. + */ + void vNonPreemptiveTick( void ) __irq; + void vNonPreemptiveTick( void ) __irq + { + /* Increment the tick count - this may make a delaying task ready + * to run - but a context switch is not performed. */ + xTaskIncrementTick(); + + T0IR = portTIMER_MATCH_ISR_BIT; /* Clear the timer event */ + VICVectAddr = portCLEAR_VIC_INTERRUPT; /* Acknowledge the Interrupt */ + } + +#else /* if configUSE_PREEMPTION == 0 */ + +/* + ************************************************************************** + * The preemptive scheduler ISR is written in assembler and can be found + * in the portASM.s file. This will only get used if portUSE_PREEMPTION + * is set to 1 in portmacro.h + ************************************************************************** + */ + + void vPreemptiveTick( void ); + +#endif /* if configUSE_PREEMPTION == 0 */ +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ + uint32_t ulCompareMatch; + + /* A 1ms tick does not require the use of the timer prescale. This is + * defaulted to zero but can be used if necessary. */ + T0PR = portPRESCALE_VALUE; + + /* Calculate the match value required for our wanted tick rate. */ + ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ; + + /* Protect against divide by zero. Using an if() statement still results + * in a warning - hence the #if. */ + #if portPRESCALE_VALUE != 0 + { + ulCompareMatch /= ( portPRESCALE_VALUE + 1 ); + } + #endif + + T0MR0 = ulCompareMatch; + + /* Generate tick with timer 0 compare match. */ + T0MCR = portRESET_COUNT_ON_MATCH | portINTERRUPT_ON_MATCH; + + /* Setup the VIC for the timer. */ + VICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT ); + VICIntEnable |= portTIMER_VIC_CHANNEL_BIT; + + /* The ISR installed depends on whether the preemptive or cooperative + * scheduler is being used. */ + #if configUSE_PREEMPTION == 1 + { + VICVectAddr0 = ( uint32_t ) vPreemptiveTick; + } + #else + { + VICVectAddr0 = ( uint32_t ) vNonPreemptiveTick; + } + #endif + + VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE; + + /* Start the timer - interrupts are disabled when this function is called + * so it is okay to do this here. */ + T0TCR = portENABLE_TIMER; +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ + __disable_irq(); + + /* Now that interrupts are disabled, ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + * re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Enable interrupts as per portEXIT_CRITICAL(). */ + __enable_irq(); + } + } +} +/*-----------------------------------------------------------*/ diff --git a/portable/RVDS/ARM7_LPC21xx/portASM.s b/portable/RVDS/ARM7_LPC21xx/portASM.s new file mode 100644 index 000000000..c47a9a641 --- /dev/null +++ b/portable/RVDS/ARM7_LPC21xx/portASM.s @@ -0,0 +1,124 @@ +;/* +; * FreeRTOS Kernel +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + + INCLUDE portmacro.inc + + IMPORT vTaskSwitchContext + IMPORT xTaskIncrementTick + + EXPORT vPortYieldProcessor + EXPORT vPortStartFirstTask + EXPORT vPreemptiveTick + EXPORT vPortYield + + +VICVECTADDR EQU 0xFFFFF030 +T0IR EQU 0xE0004000 +T0MATCHBIT EQU 0x00000001 + + ARM + AREA PORT_ASM, CODE, READONLY + + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Starting the first task is done by just restoring the context +; setup by pxPortInitialiseStack +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortStartFirstTask + + PRESERVE8 + + portRESTORE_CONTEXT + +vPortYield + + PRESERVE8 + + SVC 0 + bx lr + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Interrupt service routine for the SWI interrupt. The vector table is +; configured in the startup.s file. +; +; vPortYieldProcessor() is used to manually force a context switch. The +; SWI interrupt is generated by a call to taskYIELD() or portYIELD(). +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +vPortYieldProcessor + + PRESERVE8 + + ; Within an IRQ ISR the link register has an offset from the true return + ; address, but an SWI ISR does not. Add the offset manually so the same + ; ISR return code can be used in both cases. + ADD LR, LR, #4 + + ; Perform the context switch. + portSAVE_CONTEXT ; Save current task context + LDR R0, =vTaskSwitchContext ; Get the address of the context switch function + MOV LR, PC ; Store the return address + BX R0 ; Call the contedxt switch function + portRESTORE_CONTEXT ; restore the context of the selected task + + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Interrupt service routine for preemptive scheduler tick timer +; Only used if portUSE_PREEMPTION is set to 1 in portmacro.h +; +; Uses timer 0 of LPC21XX Family +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +vPreemptiveTick + + PRESERVE8 + + portSAVE_CONTEXT ; Save the context of the current task. + + LDR R0, =xTaskIncrementTick ; Increment the tick count. + MOV LR, PC ; This may make a delayed task ready + BX R0 ; to run. + + CMP R0, #0 + BEQ SkipContextSwitch + LDR R0, =vTaskSwitchContext ; Find the highest priority task that + MOV LR, PC ; is ready to run. + BX R0 +SkipContextSwitch + MOV R0, #T0MATCHBIT ; Clear the timer event + LDR R1, =T0IR + STR R0, [R1] + + LDR R0, =VICVECTADDR ; Acknowledge the interrupt + STR R0,[R0] + + portRESTORE_CONTEXT ; Restore the context of the highest + ; priority task that is ready to run. + END diff --git a/portable/RVDS/ARM7_LPC21xx/portmacro.h b/portable/RVDS/ARM7_LPC21xx/portmacro.h new file mode 100644 index 000000000..5535dcfef --- /dev/null +++ b/portable/RVDS/ARM7_LPC21xx/portmacro.h @@ -0,0 +1,152 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/*----------------------------------------------------------- +* ISR entry and exit macros. These are only required if a task switch +* is required from an ISR. +*----------------------------------------------------------*/ + +/* If a switch is required then we just need to call */ +/* vTaskSwitchContext() as the context has already been */ +/* saved. */ + +#define portEXIT_SWITCHING_ISR( SwitchRequired ) \ + { \ + extern void vTaskSwitchContext( void ); \ + \ + if( SwitchRequired ) \ + { \ + vTaskSwitchContext(); \ + } \ + } \ + +extern void vPortYield( void ); +#define portYIELD() vPortYield() + + +/* Critical section management. */ + +/* + ****************************************************************** + * We don't need to worry about whether we're in ARM or + * THUMB mode with the Keil Real View compiler when enabling + * or disabling interrupts as the compiler's intrinsic functions + * take care of that for us. + ******************************************************************* + */ +#define portDISABLE_INTERRUPTS() __disable_irq() +#define portENABLE_INTERRUPTS() __enable_irq() + + +/*----------------------------------------------------------- +* Critical section control +* +* The code generated by the Keil compiler does not maintain separate +* stack and frame pointers. The portENTER_CRITICAL macro cannot therefore +* use the stack as per other ports. Instead a variable is used to keep +* track of the critical section nesting. This necessitates the use of a +* function in place of the macro. +*----------------------------------------------------------*/ + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); +/*-----------------------------------------------------------*/ + +/* Compiler specifics. */ +#define inline +#define register +#define portNOP() __asm { NOP } +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/RVDS/ARM7_LPC21xx/portmacro.inc b/portable/RVDS/ARM7_LPC21xx/portmacro.inc new file mode 100644 index 000000000..ef84d1adf --- /dev/null +++ b/portable/RVDS/ARM7_LPC21xx/portmacro.inc @@ -0,0 +1,92 @@ +;/* +; * FreeRTOS Kernel +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + + IMPORT ulCriticalNesting ; + IMPORT pxCurrentTCB ; + + + MACRO + portRESTORE_CONTEXT + + + LDR R0, =pxCurrentTCB ; Set the LR to the task stack. The location was... + LDR R0, [R0] ; ... stored in pxCurrentTCB + LDR LR, [R0] + + LDR R0, =ulCriticalNesting ; The critical nesting depth is the first item on... + LDMFD LR!, {R1} ; ...the stack. Load it into the ulCriticalNesting var. + STR R1, [R0] ; + + LDMFD LR!, {R0} ; Get the SPSR from the stack. + MSR SPSR_cxsf, R0 ; + + LDMFD LR, {R0-R14}^ ; Restore all system mode registers for the task. + NOP ; + + LDR LR, [LR, #+60] ; Restore the return address + + ; And return - correcting the offset in the LR to obtain ... + SUBS PC, LR, #4 ; ...the correct address. + + MEND + +; /**********************************************************************/ + + MACRO + portSAVE_CONTEXT + + + STMDB SP!, {R0} ; Store R0 first as we need to use it. + + STMDB SP,{SP}^ ; Set R0 to point to the task stack pointer. + NOP ; + SUB SP, SP, #4 ; + LDMIA SP!,{R0} ; + + STMDB R0!, {LR} ; Push the return address onto the stack. + MOV LR, R0 ; Now we have saved LR we can use it instead of R0. + LDMIA SP!, {R0} ; Pop R0 so we can save it onto the system mode stack. + + STMDB LR,{R0-LR}^ ; Push all the system mode registers onto the task stack. + NOP ; + SUB LR, LR, #60 ; + + MRS R0, SPSR ; Push the SPSR onto the task stack. + STMDB LR!, {R0} ; + + LDR R0, =ulCriticalNesting ; + LDR R0, [R0] ; + STMDB LR!, {R0} ; + + LDR R0, =pxCurrentTCB ; Store the new top of stack for the task. + LDR R1, [R0] ; + STR LR, [R1] ; + + MEND + + END diff --git a/portable/RVDS/ARM_CA9/port.c b/portable/RVDS/ARM_CA9/port.c new file mode 100644 index 000000000..7ef38f399 --- /dev/null +++ b/portable/RVDS/ARM_CA9/port.c @@ -0,0 +1,484 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS + #error "configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" +#endif + +#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET + #error "configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" +#endif + +#ifndef configUNIQUE_INTERRUPT_PRIORITIES + #error "configUNIQUE_INTERRUPT_PRIORITIES must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" +#endif + +#ifndef configSETUP_TICK_INTERRUPT + #error "configSETUP_TICK_INTERRUPT() must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" +#endif /* configSETUP_TICK_INTERRUPT */ + +#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" +#endif + +#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0 + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0" +#endif + +#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority" +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + /* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice." + #endif +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/* In case security extensions are implemented. */ +#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 ) + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )" +#endif + +#ifndef configCLEAR_TICK_INTERRUPT + #define configCLEAR_TICK_INTERRUPT() +#endif + +/* The number of bits to shift for an interrupt priority is dependent on the + * number of bits implemented by the interrupt controller. */ +#if configUNIQUE_INTERRUPT_PRIORITIES == 16 + #define portPRIORITY_SHIFT 4 + #define portMAX_BINARY_POINT_VALUE 3 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 32 + #define portPRIORITY_SHIFT 3 + #define portMAX_BINARY_POINT_VALUE 2 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 64 + #define portPRIORITY_SHIFT 2 + #define portMAX_BINARY_POINT_VALUE 1 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 128 + #define portPRIORITY_SHIFT 1 + #define portMAX_BINARY_POINT_VALUE 0 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 256 + #define portPRIORITY_SHIFT 0 + #define portMAX_BINARY_POINT_VALUE 0 +#else /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */ + #error "Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware" +#endif /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */ + +/* A critical section is exited when the critical section nesting count reaches + * this value. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + +/* In all GICs 255 can be written to the priority mask register to unmask all + * (but the lowest) interrupt priority. */ +#define portUNMASK_VALUE ( 0xFFUL ) + +/* Tasks are not created with a floating point context, but can be given a + * floating point context after they have been created. A variable is stored as + * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task + * does not have an FPU context, or any other value if the task does have an FPU + * context. */ +#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) + +/* Interrupt controller access addresses. */ +#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 ) +#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C ) +#define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 ) +#define portICCBPR_BINARY_POINT_OFFSET ( 0x08 ) +#define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 ) +#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET ) +#define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) ) +#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ) +#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET ) +#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) +#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) ) +#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) ) + +/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary + * point is zero. */ +#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 ) + +/* Constants required to setup the initial task context. */ +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portTHUMB_MODE_ADDRESS ( 0x01UL ) + +/* Masks all bits in the APSR other than the mode bits. */ +#define portAPSR_MODE_BITS_MASK ( 0x1F ) + +/* The value of the mode bits in the APSR when the CPU is executing in user + * mode. */ +#define portAPSR_USER_MODE ( 0x10 ) + +/* Macro to unmask all interrupt priorities. */ +#define portCLEAR_INTERRUPT_MASK() \ + { \ + __disable_irq(); \ + portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \ + __asm( "DSB \n" \ + "ISB \n" ); \ + __enable_irq(); \ + } + +/*-----------------------------------------------------------*/ + +/* + * Starts the first task executing. This function is necessarily written in + * assembly code so is implemented in portASM.s. + */ +extern void vPortRestoreTaskContext( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* A variable is used to keep track of the critical section nesting. This + * variable has to be stored as part of the task context and must be initialised to + * a non zero value to ensure interrupts don't inadvertently become unmasked before + * the scheduler starts. As it is stored as part of the task context it will + * automatically be set to 0 when the first task is started. */ +volatile uint32_t ulCriticalNesting = 9999UL; + +/* Used to pass constants into the ASM code. The address at which variables are + * placed is the constant value so indirect loads in the asm code are not + * required. */ +uint32_t ulICCIAR __attribute__( ( at( portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ) ) ); +uint32_t ulICCEOIR __attribute__( ( at( portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ) ) ); +uint32_t ulICCPMR __attribute__( ( at( portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ) ) ); +uint32_t ulAsmAPIPriorityMask __attribute__( ( at( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ) ); + +/* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then + * a floating point context must be saved and restored for the task. */ +uint32_t ulPortTaskHasFPUContext = pdFALSE; + +/* Set to 1 to pend a context switch from an ISR. */ +uint32_t ulPortYieldRequired = pdFALSE; + +/* Counts the interrupt nesting depth. A context switch is only performed if + * if the nesting depth is 0. */ +uint32_t ulPortInterruptNesting = 0UL; + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Setup the initial stack of the task. The stack is set exactly as + * expected by the portRESTORE_CONTEXT() macro. + * + * The fist real value on the stack is the status register, which is set for + * system mode, with interrupts enabled. A few NULLs are added first to ensure + * GDB does not try decoding a non-existent return address. */ + *pxTopOfStack = NULL; + pxTopOfStack--; + *pxTopOfStack = NULL; + pxTopOfStack--; + *pxTopOfStack = NULL; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + + if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL ) + { + /* The task will start in THUMB mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + + pxTopOfStack--; + + /* Next the return address, which in this case is the start of the task. */ + *pxTopOfStack = ( StackType_t ) pxCode; + pxTopOfStack--; + + /* Next all the registers other than the stack pointer. */ + *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The task will start with a critical nesting count of 0 as interrupts are + * enabled. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + pxTopOfStack--; + + /* The task will start without a floating point context. A task that uses + * the floating point hardware must call vPortTaskUsesFPU() before executing + * any floating point instructions. */ + *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ + configASSERT( ulPortInterruptNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + uint32_t ulAPSR; + + /* Only continue if the CPU is not in User mode. The CPU must be in a + * Privileged mode for the scheduler to start. */ + __asm( "MRS ulAPSR, APSR" ); + ulAPSR &= portAPSR_MODE_BITS_MASK; + configASSERT( ulAPSR != portAPSR_USER_MODE ); + + if( ulAPSR != portAPSR_USER_MODE ) + { + /* Only continue if the binary point value is set to its lowest possible + * setting. See the comments in vPortValidateInterruptPriority() below for + * more information. */ + configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ); + + if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ) + { + /* Start the timer that generates the tick ISR. */ + configSETUP_TICK_INTERRUPT(); + + __enable_irq(); + vPortRestoreTaskContext(); + } + } + + /* Will only get here if vTaskStartScheduler() was called with the CPU in + * a non-privileged mode or the binary point register was not set to its lowest + * possible value. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ + ulPortSetInterruptMask(); + + /* Now that interrupts are disabled, ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ + if( ulCriticalNesting == 1 ) + { + configASSERT( ulPortInterruptNesting == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as the critical section is being + * exited. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then all interrupt + * priorities must be re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Critical nesting has reached zero so all interrupt priorities + * should be unmasked. */ + portCLEAR_INTERRUPT_MASK(); + } + } +} +/*-----------------------------------------------------------*/ + +void FreeRTOS_Tick_Handler( void ) +{ + /* Set interrupt mask before altering scheduler structures. The tick + * handler runs at the lowest priority, so interrupts cannot already be masked, + * so there is no need to save and restore the current mask value. */ + __disable_irq(); + portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); + __asm( "DSB \n" + "ISB \n" ); + __enable_irq(); + + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + ulPortYieldRequired = pdTRUE; + } + + /* Ensure all interrupt priorities are active again. */ + portCLEAR_INTERRUPT_MASK(); + configCLEAR_TICK_INTERRUPT(); +} +/*-----------------------------------------------------------*/ + +void vPortTaskUsesFPU( void ) +{ + uint32_t ulInitialFPSCR = 0; + + /* A task is registering the fact that it needs an FPU context. Set the + * FPU flag (which is saved as part of the task context). */ + ulPortTaskHasFPUContext = pdTRUE; + + /* Initialise the floating point status register. */ + __asm( "FMXR FPSCR, ulInitialFPSCR" ); +} +/*-----------------------------------------------------------*/ + +void vPortClearInterruptMask( uint32_t ulNewMaskValue ) +{ + if( ulNewMaskValue == pdFALSE ) + { + portCLEAR_INTERRUPT_MASK(); + } +} +/*-----------------------------------------------------------*/ + +uint32_t ulPortSetInterruptMask( void ) +{ + uint32_t ulReturn; + + __disable_irq(); + + if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ) + { + /* Interrupts were already masked. */ + ulReturn = pdTRUE; + } + else + { + ulReturn = pdFALSE; + portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); + __asm( "DSB \n" + "ISB \n" ); + } + + __enable_irq(); + + return ulReturn; +} +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ); + + /* Priority grouping: The interrupt controller (GIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * The priority grouping is configured by the GIC's binary point register + * (ICCBPR). Writing 0 to ICCBPR will ensure it is set to its lowest + * possible value (which may be above 0). */ + configASSERT( portICCBPR_BINARY_POINT_REGISTER <= portMAX_BINARY_POINT_VALUE ); + } + +#endif /* configASSERT_DEFINED */ diff --git a/portable/RVDS/ARM_CA9/portASM.s b/portable/RVDS/ARM_CA9/portASM.s new file mode 100644 index 000000000..771b140da --- /dev/null +++ b/portable/RVDS/ARM_CA9/portASM.s @@ -0,0 +1,171 @@ +;/* +; * FreeRTOS Kernel +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + + INCLUDE portmacro.inc + + IMPORT vApplicationIRQHandler + IMPORT vTaskSwitchContext + IMPORT ulPortYieldRequired + IMPORT ulPortInterruptNesting + IMPORT vTaskSwitchContext + IMPORT ulICCIAR + IMPORT ulICCEOIR + + EXPORT FreeRTOS_SWI_Handler + EXPORT FreeRTOS_IRQ_Handler + EXPORT vPortRestoreTaskContext + + ARM + AREA PORT_ASM, CODE, READONLY + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; SVC handler is used to yield a task. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +FreeRTOS_SWI_Handler + + PRESERVE8 + + ; Save the context of the current task and select a new task to run. + portSAVE_CONTEXT + LDR R0, =vTaskSwitchContext + BLX R0 + portRESTORE_CONTEXT + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; vPortRestoreTaskContext is used to start the scheduler. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortRestoreTaskContext + ; Switch to system mode + CPS #SYS_MODE + portRESTORE_CONTEXT + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; PL390 GIC interrupt handler +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +FreeRTOS_IRQ_Handler + + ; Return to the interrupted instruction. + SUB lr, lr, #4 + + ; Push the return address and SPSR + PUSH {lr} + MRS lr, SPSR + PUSH {lr} + + ; Change to supervisor mode to allow reentry. + CPS #SVC_MODE + + ; Push used registers. + PUSH {r0-r4, r12} + + ; Increment nesting count. r3 holds the address of ulPortInterruptNesting + ; for future use. r1 holds the original ulPortInterruptNesting value for + ; future use. + LDR r3, =ulPortInterruptNesting + LDR r1, [r3] + ADD r4, r1, #1 + STR r4, [r3] + + ; Read value from the interrupt acknowledge register, which is stored in r0 + ; for future parameter and interrupt clearing use. + LDR r2, =ulICCIAR + LDR r0, [r2] + + ; Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for + ; future use. _RB_ Does this ever actually need to be done provided the + ; start of the stack is 8-byte aligned? + MOV r2, sp + AND r2, r2, #4 + SUB sp, sp, r2 + + ; Call the interrupt handler. r4 is pushed to maintain alignment. + PUSH {r0-r4, lr} + LDR r1, =vApplicationIRQHandler + BLX r1 + POP {r0-r4, lr} + ADD sp, sp, r2 + + CPSID i + + ; Write the value read from ICCIAR to ICCEOIR + LDR r4, =ulICCEOIR + STR r0, [r4] + + ; Restore the old nesting count + STR r1, [r3] + + ; A context switch is never performed if the nesting count is not 0 + CMP r1, #0 + BNE exit_without_switch + + ; Did the interrupt request a context switch? r1 holds the address of + ; ulPortYieldRequired and r0 the value of ulPortYieldRequired for future + ; use. + LDR r1, =ulPortYieldRequired + LDR r0, [r1] + CMP r0, #0 + BNE switch_before_exit + +exit_without_switch + ; No context switch. Restore used registers, LR_irq and SPSR before + ; returning. + POP {r0-r4, r12} + CPS #IRQ_MODE + POP {LR} + MSR SPSR_cxsf, LR + POP {LR} + MOVS PC, LR + +switch_before_exit + ; A context switch is to be performed. Clear the context switch pending + ; flag. + MOV r0, #0 + STR r0, [r1] + + ; Restore used registers, LR-irq and SPSR before saving the context + ; to the task stack. + POP {r0-r4, r12} + CPS #IRQ_MODE + POP {LR} + MSR SPSR_cxsf, LR + POP {LR} + portSAVE_CONTEXT + + ; Call the function that selects the new task to execute. + ; vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD + ; instructions, or 8 byte aligned stack allocated data. LR does not need + ; saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. + LDR r0, =vTaskSwitchContext + BLX r0 + + ; Restore the context of, and branch to, the task selected to execute next. + portRESTORE_CONTEXT + + + END diff --git a/portable/RVDS/ARM_CA9/portmacro.h b/portable/RVDS/ARM_CA9/portmacro.h new file mode 100644 index 000000000..2218a6379 --- /dev/null +++ b/portable/RVDS/ARM_CA9/portmacro.h @@ -0,0 +1,169 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* Called at the end of an ISR that can cause a context switch. */ +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + { \ + extern uint32_t ulPortYieldRequired; \ + \ + if( xSwitchRequired != pdFALSE ) \ + { \ + ulPortYieldRequired = pdTRUE; \ + } \ + } + +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#define portYIELD() __asm( "SWI 0" ); + + +/*----------------------------------------------------------- +* Critical section control +*----------------------------------------------------------*/ + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +extern uint32_t ulPortSetInterruptMask( void ); +extern void vPortClearInterruptMask( uint32_t ulNewMaskValue ); + +/* These macros do not globally disable/enable interrupts. They do mask off + * interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */ +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); +#define portDISABLE_INTERRUPTS() ulPortSetInterruptMask() +#define portENABLE_INTERRUPTS() vPortClearInterruptMask( 0 ) +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortClearInterruptMask( x ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not required for this port but included in case common demo code that uses these + * macros is used. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* Prototype of the FreeRTOS tick handler. This must be installed as the + * handler for whichever peripheral is used to generate the RTOS tick. */ +void FreeRTOS_Tick_Handler( void ); + +/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU() + * before any floating point instructions are executed. */ +void vPortTaskUsesFPU( void ); +#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() + +#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL ) +#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL ) + +/* Architecture specific optimisations. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __clz( uxReadyPriorities ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +#if ( configASSERT_DEFINED == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif + +#define portNOP() __nop() + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/RVDS/ARM_CA9/portmacro.inc b/portable/RVDS/ARM_CA9/portmacro.inc new file mode 100644 index 000000000..68a73945f --- /dev/null +++ b/portable/RVDS/ARM_CA9/portmacro.inc @@ -0,0 +1,120 @@ +;/* +; * FreeRTOS Kernel +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + +SYS_MODE EQU 0x1f +SVC_MODE EQU 0x13 +IRQ_MODE EQU 0x12 + + IMPORT ulCriticalNesting + IMPORT pxCurrentTCB + IMPORT ulPortTaskHasFPUContext + IMPORT ulAsmAPIPriorityMask + IMPORT ulICCPMR + + + MACRO + portSAVE_CONTEXT + + ; Save the LR and SPSR onto the system mode stack before switching to + ; system mode to save the remaining system mode registers + SRSDB sp!, #SYS_MODE + CPS #SYS_MODE + PUSH {R0-R12, R14} + + ; Push the critical nesting count + LDR R2, =ulCriticalNesting + LDR R1, [R2] + PUSH {R1} + + ; Does the task have a floating point context that needs saving? If + ; ulPortTaskHasFPUContext is 0 then no. + LDR R2, =ulPortTaskHasFPUContext + LDR R3, [R2] + CMP R3, #0 + + ; Save the floating point context, if any + FMRXNE R1, FPSCR + VPUSHNE {D0-D15} + VPUSHNE {D16-D31} + PUSHNE {R1} + + ; Save ulPortTaskHasFPUContext itself + PUSH {R3} + + ; Save the stack pointer in the TCB + LDR R0, =pxCurrentTCB + LDR R1, [R0] + STR SP, [R1] + + MEND + +; /**********************************************************************/ + + MACRO + portRESTORE_CONTEXT + + ; Set the SP to point to the stack of the task being restored. + LDR R0, =pxCurrentTCB + LDR R1, [R0] + LDR SP, [R1] + + ; Is there a floating point context to restore? If the restored + ; ulPortTaskHasFPUContext is zero then no. + LDR R0, =ulPortTaskHasFPUContext + POP {R1} + STR R1, [R0] + CMP R1, #0 + + ; Restore the floating point context, if any + POPNE {R0} + VPOPNE {D16-D31} + VPOPNE {D0-D15} + VMSRNE FPSCR, R0 + + ; Restore the critical section nesting depth + LDR R0, =ulCriticalNesting + POP {R1} + STR R1, [R0] + + ; Ensure the priority mask is correct for the critical nesting depth + LDR R2, =ulICCPMR + CMP R1, #0 + MOVEQ R4, #255 + LDRNE R4, =ulAsmAPIPriorityMask + STR R4, [r2] + + ; Restore all system mode registers other than the SP (which is already + ; being used) + POP {R0-R12, R14} + + ; Return to the task code, loading CPSR on the way. + RFEIA sp! + + MEND + + END diff --git a/portable/RVDS/ARM_CM0/port.c b/portable/RVDS/ARM_CM0/port.c new file mode 100644 index 000000000..ececb715a --- /dev/null +++ b/portable/RVDS/ARM_CM0/port.c @@ -0,0 +1,622 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ARM CM0 port. +*----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to manipulate the NVIC. */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) + +/* The systick is a 24-bit counter. */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/* A fiddle factor to estimate the number of SysTick counts that would have + * occurred while the SysTick counter is stopped during tickless idle + * calculations. */ +#ifndef portMISSED_COUNTS_FACTOR + #define portMISSED_COUNTS_FACTOR ( 94UL ) +#endif + +/* Constants used with memory barrier intrinsics. */ +#define portSY_FULL_READ_WRITE ( 15 ) + +/* Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/* Legacy macro for backward compatibility only. This macro used to be used to + * replace the function that configures the clock used to generate the tick + * interrupt (prvSetupTimerInterrupt()), but now the function is declared weak so + * the application writer can override it by simply defining a function of the + * same name (vApplicationSetupTickInterrupt()). */ +#ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION + #define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 0 +#endif + +/* Each task maintains its own interrupt status in the critical nesting + * variable. */ +static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +/* The number of SysTick increments that make up one tick period. */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulTimerCountsForOneTick = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* The maximum number of tick periods that can be suppressed is limited by the + * 24 bit resolution of the SysTick timer. */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t xMaximumPossibleSuppressedTicks = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* Compensate for the CPU cycles that pass while the SysTick is stopped (low + * power functionality only. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ); + +/* + * Exception handlers. + */ +void xPortPendSVHandler( void ); +void xPortSysTickHandler( void ); +void vPortSVCHandler( void ); + +/* + * Start first task is a separate function so it can be tested in isolation. + */ +static void prvPortStartFirstTask( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack -= 8; /* R11..R4. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ + configASSERT( uxCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler( void ) +{ + /* This function is no longer used, but retained for backward + * compatibility. */ +} +/*-----------------------------------------------------------*/ + +__asm void prvPortStartFirstTask( void ) +{ + extern pxCurrentTCB; + + PRESERVE8 + + /* The MSP stack is not reset as, unlike on M3/4 parts, there is no vector + * table offset register that can be used to locate the initial stack value. + * Not all M0 parts have the application vector table at address 0. */ +/* *INDENT-OFF* */ + + ldr r3, = pxCurrentTCB /* Obtain location of pxCurrentTCB. */ + ldr r1, [ r3 ] + ldr r0, [ r1 ] /* The first item in pxCurrentTCB is the task top of stack. */ + adds r0, # 32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + movs r0, # 2 /* Switch to the psp stack. */ + msr CONTROL, r0 + isb + pop { r0 - r5 } /* Pop the registers that are saved automatically. */ + mov lr, r5 /* lr is now in r5. */ + pop { r3 } /* The return address is now in r3. */ + pop { r2 } /* Pop and discard the XPSR. */ + cpsie i /* The first task has its context and interrupts can be enabled. */ + bx r3 /* Finally, jump to the user defined task code. */ + + ALIGN +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + /* Start the first task. */ + prvPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortYield( void ) +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is completely + * within the specified behaviour for the architecture. */ + __dsb( portSY_FULL_READ_WRITE ); + __isb( portSY_FULL_READ_WRITE ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + __dsb( portSY_FULL_READ_WRITE ); + __isb( portSY_FULL_READ_WRITE ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +__asm uint32_t ulSetInterruptMaskFromISR( void ) +{ +/* *INDENT-OFF* */ + mrs r0, PRIMASK + cpsid i + bx lr +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +__asm void vClearInterruptMaskFromISR( uint32_t ulMask ) +{ +/* *INDENT-OFF* */ + msr PRIMASK, r0 + bx lr +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +__asm void xPortPendSVHandler( void ) +{ + extern vTaskSwitchContext + extern pxCurrentTCB + +/* *INDENT-OFF* */ + PRESERVE8 + + mrs r0, psp + + ldr r3, = pxCurrentTCB /* Get the location of the current TCB. */ + ldr r2, [ r3 ] + + subs r0, # 32 /* Make space for the remaining low registers. */ + str r0, [ r2 ] /* Save the new top of stack. */ + stmia r0 !, { r4 - r7 } /* Store the low registers that are not saved automatically. */ + mov r4, r8 /* Store the high registers. */ + mov r5, r9 + mov r6, r10 + mov r7, r11 + stmia r0 !, { r4 - r7 } + + push { r3, r14 } + cpsid i + bl vTaskSwitchContext + cpsie i + pop { r2, r3 } /* lr goes in r3. r2 now holds tcb pointer. */ + + ldr r1, [ r2 ] + ldr r0, [ r1 ] /* The first item in pxCurrentTCB is the task top of stack. */ + adds r0, # 16 /* Move to the high registers. */ + ldmia r0 !, { r4 - r7 } /* Pop the high registers. */ + mov r8, r4 + mov r9, r5 + mov r10, r6 + mov r11, r7 + + msr psp, r0 /* Remember the new top of stack for the task. */ + + subs r0, # 32 /* Go back for the low registers that are not automatically restored. */ + ldmia r0 !, { r4 - r7 } /* Pop low registers. */ + + bx r3 + ALIGN +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +#if ( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 ) + + __weak void vPortSetupTimerInterrupt( void ) + { + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and clear the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); + } + +#endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __disable_irq(); + __dsb( portSY_FULL_READ_WRITE ); + __isb( portSY_FULL_READ_WRITE ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the __disable_irq() + * call above. */ + __enable_irq(); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __dsb( portSY_FULL_READ_WRITE ); + __wfi(); + __isb( portSY_FULL_READ_WRITE ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the __disable_irq() call above. */ + __enable_irq(); + __dsb( portSY_FULL_READ_WRITE ); + __isb( portSY_FULL_READ_WRITE ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __disable_irq(); + __dsb( portSY_FULL_READ_WRITE ); + __isb( portSY_FULL_READ_WRITE ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __enable_irq(); + } + } + +#endif /* #if configUSE_TICKLESS_IDLE */ + +/*-----------------------------------------------------------*/ diff --git a/portable/RVDS/ARM_CM0/portmacro.h b/portable/RVDS/ARM_CM0/portmacro.h new file mode 100644 index 000000000..785138722 --- /dev/null +++ b/portable/RVDS/ARM_CM0/portmacro.h @@ -0,0 +1,174 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +/*-----------------------------------------------------------*/ + + +/* Scheduler utilities. */ +extern void vPortYield( void ); +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portYIELD() vPortYield() +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +extern uint32_t ulSetInterruptMaskFromISR( void ); +extern void vClearInterruptMaskFromISR( uint32_t ulMask ); + +#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMaskFromISR( x ) +#define portDISABLE_INTERRUPTS() __disable_irq() +#define portENABLE_INTERRUPTS() __enable_irq() +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() + +/*-----------------------------------------------------------*/ + +/* Tickless idle/low power functionality. */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +#define portNOP() + +#define portINLINE __inline + +#ifndef portFORCE_INLINE + #define portFORCE_INLINE __forceinline +#endif + +/*-----------------------------------------------------------*/ + +static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + __asm + { +/* *INDENT-OFF* */ + mrs ulCurrentInterrupt, ipsr +/* *INDENT-ON* */ + } + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} + +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/RVDS/ARM_CM3/port.c b/portable/RVDS/ARM_CM3/port.c new file mode 100644 index 000000000..725127193 --- /dev/null +++ b/portable/RVDS/ARM_CM3/port.c @@ -0,0 +1,793 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ARM CM3 port. +*----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 + #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ +#endif + +/* Legacy macro for backward compatibility only. This macro used to be used to + * replace the function that configures the clock used to generate the tick + * interrupt (prvSetupTimerInterrupt()), but now the function is declared weak so + * the application writer can override it by simply defining a function of the + * same name (vApplicationSetupTickInterrupt()). */ +#ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION + #define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 0 +#endif + +/* Constants required to manipulate the core. Registers first... */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +/* ...then bits in the registers. */ +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) + +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL ) +#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL ) + +/* Constants required to check the validity of an interrupt priority. */ +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) + +/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */ +#define portVECTACTIVE_MASK ( 0xFFUL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) + +/* The systick is a 24-bit counter. */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/* A fiddle factor to estimate the number of SysTick counts that would have + * occurred while the SysTick counter is stopped during tickless idle + * calculations. */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) + +/* For strict compliance with the Cortex-M spec the task start address should + * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */ +#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL ) + +/* Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ); + +/* + * Exception handlers. + */ +void xPortPendSVHandler( void ); +void xPortSysTickHandler( void ); +void vPortSVCHandler( void ); + +/* + * Start first task is a separate function so it can be tested in isolation. + */ +static void prvStartFirstTask( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* Each task maintains its own interrupt status in the critical nesting + * variable. */ +static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +/* + * The number of SysTick increments that make up one tick period. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulTimerCountsForOneTick = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * The maximum number of tick periods that can be suppressed is limited by the + * 24 bit resolution of the SysTick timer. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t xMaximumPossibleSuppressedTicks = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Compensate for the CPU cycles that pass while the SysTick is stopped (low + * power functionality only. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( configASSERT_DEFINED == 1 ) + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; +#endif /* configASSERT_DEFINED */ + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */ + + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ + configASSERT( uxCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } +} +/*-----------------------------------------------------------*/ + +__asm void vPortSVCHandler( void ) +{ +/* *INDENT-OFF* */ + PRESERVE8 + + ldr r3, = pxCurrentTCB /* Restore the context. */ + ldr r1, [ r3 ] /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */ + ldr r0, [ r1 ] /* The first item in pxCurrentTCB is the task top of stack. */ + ldmia r0 !, { r4 - r11 } /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */ + msr psp, r0 /* Restore the task stack pointer. */ + isb + mov r0, # 0 + msr basepri, r0 + orr r14, # 0xd + bx r14 +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +__asm void prvStartFirstTask( void ) +{ +/* *INDENT-OFF* */ + PRESERVE8 + + /* Use the NVIC offset register to locate the stack. */ + ldr r0, =0xE000ED08 + ldr r0, [ r0 ] + ldr r0, [ r0 ] + + /* Set the msp back to the start of the stack. */ + msr msp, r0 + /* Globally enable interrupts. */ + cpsie i + cpsie f + dsb + isb + /* Call SVC to start the first task. */ + svc 0 + nop + nop +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + #if ( configASSERT_DEFINED == 1 ) + { + volatile uint8_t ucOriginalPriority; + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * Save the interrupt priority value that is about to be clobbered. */ + ucOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to all + * possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + + /* Restore the clobbered interrupt priority register to its original + * value. */ + *pucFirstUserPriorityRegister = ucOriginalPriority; + } + #endif /* configASSERT_DEFINED */ + + /* Make PendSV and SysTick the lowest priority interrupts. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + /* Start the first task. */ + prvStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ + if( uxCriticalNesting == 1 ) + { + configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +__asm void xPortPendSVHandler( void ) +{ + extern uxCriticalNesting; + extern pxCurrentTCB; + extern vTaskSwitchContext; + +/* *INDENT-OFF* */ + PRESERVE8 + + mrs r0, psp + isb + + ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */ + ldr r2, [ r3 ] + + stmdb r0 !, { r4 - r11 } /* Save the remaining registers. */ + str r0, [ r2 ] /* Save the new top of stack into the first member of the TCB. */ + + stmdb sp !, { r3, r14 } + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 + dsb + isb + bl vTaskSwitchContext + mov r0, #0 + msr basepri, r0 + ldmia sp !, { r3, r14 } + + ldr r1, [ r3 ] + ldr r0, [ r1 ] /* The first item in pxCurrentTCB is the task top of stack. */ + ldmia r0 !, { r4 - r11 } /* Pop the registers and the critical nesting count. */ + msr psp, r0 + isb + bx r14 + nop +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + /* The SysTick runs at the lowest interrupt priority, so when this interrupt + * executes all interrupts must be unmasked. There is therefore no need to + * save and then restore the interrupt mask value as its value is already + * known - therefore the slightly faster vPortRaiseBASEPRI() function is used + * in place of portSET_INTERRUPT_MASK_FROM_ISR(). */ + vPortRaiseBASEPRI(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + + /* A context switch is required. Context switching is performed in + * the PendSV interrupt. Pend the PendSV interrupt. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + + vPortClearBASEPRIFromISR(); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __disable_irq(); + __dsb( portSY_FULL_READ_WRITE ); + __isb( portSY_FULL_READ_WRITE ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the __disable_irq() + * call above. */ + __enable_irq(); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __dsb( portSY_FULL_READ_WRITE ); + __wfi(); + __isb( portSY_FULL_READ_WRITE ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the __disable_irq() call above. */ + __enable_irq(); + __dsb( portSY_FULL_READ_WRITE ); + __isb( portSY_FULL_READ_WRITE ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __disable_irq(); + __dsb( portSY_FULL_READ_WRITE ); + __isb( portSY_FULL_READ_WRITE ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __enable_irq(); + } + } + +#endif /* #if configUSE_TICKLESS_IDLE */ + +/*-----------------------------------------------------------*/ + +/* + * Setup the SysTick timer to generate the tick interrupts at the required + * frequency. + */ +#if ( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 ) + + __weak void vPortSetupTimerInterrupt( void ) + { + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and clear the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); + } + +#endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */ +/*-----------------------------------------------------------*/ + +__asm uint32_t vPortGetIPSR( void ) +{ +/* *INDENT-OFF* */ + PRESERVE8 + + mrs r0, ipsr + bx r14 +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + ulCurrentInterrupt = vPortGetIPSR(); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* configASSERT_DEFINED */ diff --git a/portable/RVDS/ARM_CM3/portmacro.h b/portable/RVDS/ARM_CM3/portmacro.h new file mode 100644 index 000000000..0436525fd --- /dev/null +++ b/portable/RVDS/ARM_CM3/portmacro.h @@ -0,0 +1,280 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 + +/* Constants used with memory barrier intrinsics. */ +#define portSY_FULL_READ_WRITE ( 15 ) + +/*-----------------------------------------------------------*/ + +/* Scheduler utilities. */ +#define portYIELD() \ + { \ + /* Set a PendSV to request a context switch. */ \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + \ + /* Barriers are normally not required but do ensure the code is completely \ + * within the specified behaviour for the architecture. */ \ + __dsb( portSY_FULL_READ_WRITE ); \ + __isb( portSY_FULL_READ_WRITE ); \ + } +/*-----------------------------------------------------------*/ + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portYIELD(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() +#define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x ) + +/*-----------------------------------------------------------*/ + +/* Tickless idle/low power functionality. */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif +/*-----------------------------------------------------------*/ + +/* Port specific optimisations. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) ) + +#endif /* taskRECORD_READY_PRIORITY */ +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not necessary for to use this port. They are defined so the common demo files + * (which build with all the ports) will build. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif + +/* portNOP() is not required by this port. */ +#define portNOP() + +#define portINLINE __inline + +#ifndef portFORCE_INLINE + #define portFORCE_INLINE __forceinline +#endif + +/*-----------------------------------------------------------*/ + +static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI ) +{ + __asm + { + /* Barrier instructions are not used as this function is only used to + * lower the BASEPRI value. */ +/* *INDENT-OFF* */ + msr basepri, ulBASEPRI +/* *INDENT-ON* */ + } +} +/*-----------------------------------------------------------*/ + +static portFORCE_INLINE void vPortRaiseBASEPRI( void ) +{ + uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY; + + __asm + { + /* Set BASEPRI to the max syscall priority to effect a critical + * section. */ +/* *INDENT-OFF* */ + msr basepri, ulNewBASEPRI + dsb + isb +/* *INDENT-ON* */ + } +} +/*-----------------------------------------------------------*/ + +static portFORCE_INLINE void vPortClearBASEPRIFromISR( void ) +{ + __asm + { + /* Set BASEPRI to 0 so no interrupts are masked. This function is only + * used to lower the mask in an interrupt, so memory barriers are not + * used. */ +/* *INDENT-OFF* */ + msr basepri, # 0 +/* *INDENT-ON* */ + } +} +/*-----------------------------------------------------------*/ + +static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void ) +{ + uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY; + + __asm + { + /* Set BASEPRI to the max syscall priority to effect a critical + * section. */ +/* *INDENT-OFF* */ + mrs ulReturn, basepri + msr basepri, ulNewBASEPRI + dsb + isb +/* *INDENT-ON* */ + } + + return ulReturn; +} +/*-----------------------------------------------------------*/ + +static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + __asm + { +/* *INDENT-OFF* */ + mrs ulCurrentInterrupt, ipsr +/* *INDENT-ON* */ + } + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} + + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/RVDS/ARM_CM4F/port.c b/portable/RVDS/ARM_CM4F/port.c new file mode 100644 index 000000000..8d21daffb --- /dev/null +++ b/portable/RVDS/ARM_CM4F/port.c @@ -0,0 +1,889 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ARM CM4F port. +*----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#ifndef __TARGET_FPU_VFP + #error This port can only be used when the project options are configured to enable hardware floating point support. +#endif + +#if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 + #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ +#endif + +/* Legacy macro for backward compatibility only. This macro used to be used to + * replace the function that configures the clock used to generate the tick + * interrupt (prvSetupTimerInterrupt()), but now the function is declared weak so + * the application writer can override it by simply defining a function of the + * same name (vApplicationSetupTickInterrupt()). */ +#ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION + #define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 0 +#endif + +/* Constants required to manipulate the core. Registers first... */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +/* ...then bits in the registers. */ +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) + +/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7 + * r0p1 port. */ +#define portCPUID ( *( ( volatile uint32_t * ) 0xE000ed00 ) ) +#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL ) +#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL ) + +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL ) +#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL ) + +/* Constants required to check the validity of an interrupt priority. */ +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) + +/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */ +#define portVECTACTIVE_MASK ( 0xFFUL ) + +/* Constants required to manipulate the VFP. */ +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */ +#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) +#define portINITIAL_EXC_RETURN ( 0xfffffffd ) + +/* The systick is a 24-bit counter. */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/* A fiddle factor to estimate the number of SysTick counts that would have + * occurred while the SysTick counter is stopped during tickless idle + * calculations. */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) + +/* For strict compliance with the Cortex-M spec the task start address should + * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */ +#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL ) + +/* Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ); + +/* + * Exception handlers. + */ +void xPortPendSVHandler( void ); +void xPortSysTickHandler( void ); +void vPortSVCHandler( void ); + +/* + * Start first task is a separate function so it can be tested in isolation. + */ +static void prvStartFirstTask( void ); + +/* + * Functions defined in portasm.s to enable the VFP. + */ +static void prvEnableVFP( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* Each task maintains its own interrupt status in the critical nesting + * variable. */ +static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +/* + * The number of SysTick increments that make up one tick period. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulTimerCountsForOneTick = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * The maximum number of tick periods that can be suppressed is limited by the + * 24 bit resolution of the SysTick timer. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t xMaximumPossibleSuppressedTicks = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Compensate for the CPU cycles that pass while the SysTick is stopped (low + * power functionality only. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( configASSERT_DEFINED == 1 ) + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; +#endif /* configASSERT_DEFINED */ + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + + /* Offset added to account for the way the MCU uses the stack on entry/exit + * of interrupts, and to ensure alignment. */ + pxTopOfStack--; + + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */ + + /* Save code space by skipping register initialisation. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + + /* A save method is being used that requires each task to maintain its + * own exec return value. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; + + pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ + configASSERT( uxCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } +} +/*-----------------------------------------------------------*/ + +__asm void vPortSVCHandler( void ) +{ +/* *INDENT-OFF* */ + PRESERVE8 + + /* Get the location of the current TCB. */ + ldr r3, =pxCurrentTCB + ldr r1, [ r3 ] + ldr r0, [ r1 ] + /* Pop the core registers. */ + ldmia r0!, {r4-r11,r14} + msr psp, r0 + isb + mov r0, #0 + msr basepri, r0 + bx r14 +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +__asm void prvStartFirstTask( void ) +{ +/* *INDENT-OFF* */ + PRESERVE8 + + /* Use the NVIC offset register to locate the stack. */ + ldr r0, =0xE000ED08 + ldr r0, [ r0 ] + ldr r0, [ r0 ] + /* Set the msp back to the start of the stack. */ + msr msp, r0 + + /* Clear the bit that indicates the FPU is in use in case the FPU was used + * before the scheduler was started - which would otherwise result in the + * unnecessary leaving of space in the SVC stack for lazy saving of FPU + * registers. */ + mov r0, #0 + msr control, r0 + /* Globally enable interrupts. */ + cpsie i + cpsie f + dsb + isb + /* Call SVC to start the first task. */ + svc 0 + nop + nop +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +__asm void prvEnableVFP( void ) +{ +/* *INDENT-OFF* */ + PRESERVE8 + + /* The FPU enable bits are in the CPACR. */ + ldr.w r0, =0xE000ED88 + ldr r1, [ r0 ] + + /* Enable CP10 and CP11 coprocessors, then save back. */ + orr r1, r1, #( 0xf << 20 ) + str r1, [ r0 ] + bx r14 + nop +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY ); + + /* This port can be used on all revisions of the Cortex-M7 core other than + * the r0p1 parts. r0p1 parts should use the port from the + * /source/portable/GCC/ARM_CM7/r0p1 directory. */ + configASSERT( portCPUID != portCORTEX_M7_r0p1_ID ); + configASSERT( portCPUID != portCORTEX_M7_r0p0_ID ); + + #if ( configASSERT_DEFINED == 1 ) + { + volatile uint8_t ucOriginalPriority; + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * Save the interrupt priority value that is about to be clobbered. */ + ucOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to all + * possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + + /* Restore the clobbered interrupt priority register to its original + * value. */ + *pucFirstUserPriorityRegister = ucOriginalPriority; + } + #endif /* configASSERT_DEFINED */ + + /* Make PendSV and SysTick the lowest priority interrupts. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + /* Ensure the VFP is enabled - it should be anyway. */ + prvEnableVFP(); + + /* Lazy save always. */ + *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; + + /* Start the first task. */ + prvStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ + if( uxCriticalNesting == 1 ) + { + configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +__asm void xPortPendSVHandler( void ) +{ + extern uxCriticalNesting; + extern pxCurrentTCB; + extern vTaskSwitchContext; + +/* *INDENT-OFF* */ + PRESERVE8 + + mrs r0, psp + isb + /* Get the location of the current TCB. */ + ldr r3, =pxCurrentTCB + ldr r2, [ r3 ] + + /* Is the task using the FPU context? If so, push high vfp registers. */ + tst r14, #0x10 + it eq + vstmdbeq r0!, {s16-s31} + + /* Save the core registers. */ + stmdb r0!, {r4-r11, r14} + + /* Save the new top of stack into the first member of the TCB. */ + str r0, [ r2 ] + + stmdb sp!, {r0, r3} + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 + dsb + isb + bl vTaskSwitchContext + mov r0, #0 + msr basepri, r0 + ldmia sp!, {r0, r3} + + /* The first item in pxCurrentTCB is the task top of stack. */ + ldr r1, [ r3 ] + ldr r0, [ r1 ] + + /* Pop the core registers. */ + ldmia r0!, {r4-r11, r14} + + /* Is the task using the FPU context? If so, pop the high vfp registers + * too. */ + tst r14, #0x10 + it eq + vldmiaeq r0!, {s16-s31} + + msr psp, r0 + isb + #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */ + #if WORKAROUND_PMU_CM001 == 1 + push { r14 } + pop { pc } + nop + #endif + #endif + + bx r14 +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + /* The SysTick runs at the lowest interrupt priority, so when this interrupt + * executes all interrupts must be unmasked. There is therefore no need to + * save and then restore the interrupt mask value as its value is already + * known - therefore the slightly faster vPortRaiseBASEPRI() function is used + * in place of portSET_INTERRUPT_MASK_FROM_ISR(). */ + vPortRaiseBASEPRI(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + + /* A context switch is required. Context switching is performed in + * the PendSV interrupt. Pend the PendSV interrupt. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + + vPortClearBASEPRIFromISR(); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __disable_irq(); + __dsb( portSY_FULL_READ_WRITE ); + __isb( portSY_FULL_READ_WRITE ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the __disable_irq() + * call above. */ + __enable_irq(); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __dsb( portSY_FULL_READ_WRITE ); + __wfi(); + __isb( portSY_FULL_READ_WRITE ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the __disable_irq() call above. */ + __enable_irq(); + __dsb( portSY_FULL_READ_WRITE ); + __isb( portSY_FULL_READ_WRITE ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __disable_irq(); + __dsb( portSY_FULL_READ_WRITE ); + __isb( portSY_FULL_READ_WRITE ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __enable_irq(); + } + } + +#endif /* #if configUSE_TICKLESS_IDLE */ + +/*-----------------------------------------------------------*/ + +/* + * Setup the SysTick timer to generate the tick interrupts at the required + * frequency. + */ +#if ( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 ) + + __weak void vPortSetupTimerInterrupt( void ) + { + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and clear the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); + } + +#endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */ +/*-----------------------------------------------------------*/ + +__asm uint32_t vPortGetIPSR( void ) +{ +/* *INDENT-OFF* */ + PRESERVE8 + + mrs r0, ipsr + bx r14 +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + ulCurrentInterrupt = vPortGetIPSR(); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* configASSERT_DEFINED */ diff --git a/portable/RVDS/ARM_CM4F/portmacro.h b/portable/RVDS/ARM_CM4F/portmacro.h new file mode 100644 index 000000000..063b148f4 --- /dev/null +++ b/portable/RVDS/ARM_CM4F/portmacro.h @@ -0,0 +1,279 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 + +/* Constants used with memory barrier intrinsics. */ +#define portSY_FULL_READ_WRITE ( 15 ) + +/*-----------------------------------------------------------*/ + +/* Scheduler utilities. */ +#define portYIELD() \ + { \ + /* Set a PendSV to request a context switch. */ \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + \ + /* Barriers are normally not required but do ensure the code is completely \ + * within the specified behaviour for the architecture. */ \ + __dsb( portSY_FULL_READ_WRITE ); \ + __isb( portSY_FULL_READ_WRITE ); \ + } +/*-----------------------------------------------------------*/ + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portYIELD(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() +#define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x ) + +/*-----------------------------------------------------------*/ + +/* Tickless idle/low power functionality. */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif +/*-----------------------------------------------------------*/ + +/* Port specific optimisations. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) ) + +#endif /* taskRECORD_READY_PRIORITY */ +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not necessary for to use this port. They are defined so the common demo files + * (which build with all the ports) will build. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif + +/* portNOP() is not required by this port. */ +#define portNOP() + +#define portINLINE __inline + +#ifndef portFORCE_INLINE + #define portFORCE_INLINE __forceinline +#endif + +/*-----------------------------------------------------------*/ + +static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI ) +{ + __asm + { + /* Barrier instructions are not used as this function is only used to + * lower the BASEPRI value. */ +/* *INDENT-OFF* */ + msr basepri, ulBASEPRI +/* *INDENT-ON* */ + } +} +/*-----------------------------------------------------------*/ + +static portFORCE_INLINE void vPortRaiseBASEPRI( void ) +{ + uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY; + + __asm + { + /* Set BASEPRI to the max syscall priority to effect a critical + * section. */ +/* *INDENT-OFF* */ + msr basepri, ulNewBASEPRI + dsb + isb +/* *INDENT-ON* */ + } +} +/*-----------------------------------------------------------*/ + +static portFORCE_INLINE void vPortClearBASEPRIFromISR( void ) +{ + __asm + { + /* Set BASEPRI to 0 so no interrupts are masked. This function is only + * used to lower the mask in an interrupt, so memory barriers are not + * used. */ +/* *INDENT-OFF* */ + msr basepri, # 0 +/* *INDENT-ON* */ + } +} +/*-----------------------------------------------------------*/ + +static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void ) +{ + uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY; + + __asm + { + /* Set BASEPRI to the max syscall priority to effect a critical + * section. */ +/* *INDENT-OFF* */ + mrs ulReturn, basepri + msr basepri, ulNewBASEPRI + dsb + isb +/* *INDENT-ON* */ + } + + return ulReturn; +} +/*-----------------------------------------------------------*/ + +static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + __asm + { +/* *INDENT-OFF* */ + mrs ulCurrentInterrupt, ipsr +/* *INDENT-ON* */ + } + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c b/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c new file mode 100644 index 000000000..950788e09 --- /dev/null +++ b/portable/RVDS/ARM_CM4_MPU/mpu_wrappers_v2_asm.c @@ -0,0 +1,1705 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" +#include "event_groups.h" +#include "stream_buffer.h" +#include "mpu_prototypes.h" +#include "mpu_syscall_numbers.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE +/*-----------------------------------------------------------*/ + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + +#if ( INCLUDE_xTaskDelayUntil == 1 ) + +BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) FREERTOS_SYSTEM_CALL; + +__asm BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_xTaskDelayUntilImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskDelayUntil_Unpriv +MPU_xTaskDelayUntil_Priv + b MPU_xTaskDelayUntilImpl +MPU_xTaskDelayUntil_Unpriv + svc #SYSTEM_CALL_xTaskDelayUntil +} + +#endif /* if ( INCLUDE_xTaskDelayUntil == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_xTaskAbortDelay == 1 ) + +BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; + +__asm BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_xTaskAbortDelayImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskAbortDelay_Unpriv +MPU_xTaskAbortDelay_Priv + b MPU_xTaskAbortDelayImpl +MPU_xTaskAbortDelay_Unpriv + svc #SYSTEM_CALL_xTaskAbortDelay +} + +#endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskDelay == 1 ) + +void MPU_vTaskDelay( const TickType_t xTicksToDelay ) FREERTOS_SYSTEM_CALL; + +__asm void MPU_vTaskDelay( const TickType_t xTicksToDelay ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_vTaskDelayImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskDelay_Unpriv +MPU_vTaskDelay_Priv + b MPU_vTaskDelayImpl +MPU_vTaskDelay_Unpriv + svc #SYSTEM_CALL_vTaskDelay +} + +#endif /* if ( INCLUDE_vTaskDelay == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_uxTaskPriorityGet == 1 ) + +UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; + +__asm UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_uxTaskPriorityGetImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskPriorityGet_Unpriv +MPU_uxTaskPriorityGet_Priv + b MPU_uxTaskPriorityGetImpl +MPU_uxTaskPriorityGet_Unpriv + svc #SYSTEM_CALL_uxTaskPriorityGet +} + +#endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_eTaskGetState == 1 ) + +eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; + +__asm eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_eTaskGetStateImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_eTaskGetState_Unpriv +MPU_eTaskGetState_Priv + b MPU_eTaskGetStateImpl +MPU_eTaskGetState_Unpriv + svc #SYSTEM_CALL_eTaskGetState +} + +#endif /* if ( INCLUDE_eTaskGetState == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + +void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) FREERTOS_SYSTEM_CALL; + +__asm void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_vTaskGetInfoImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskGetInfo_Unpriv +MPU_vTaskGetInfo_Priv + b MPU_vTaskGetInfoImpl +MPU_vTaskGetInfo_Unpriv + svc #SYSTEM_CALL_vTaskGetInfo +} + +#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) + +TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) FREERTOS_SYSTEM_CALL; + +__asm TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_xTaskGetIdleTaskHandleImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetIdleTaskHandle_Unpriv +MPU_xTaskGetIdleTaskHandle_Priv + b MPU_xTaskGetIdleTaskHandleImpl +MPU_xTaskGetIdleTaskHandle_Unpriv + svc #SYSTEM_CALL_xTaskGetIdleTaskHandle +} + +#endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskSuspend == 1 ) + +void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) FREERTOS_SYSTEM_CALL; + +__asm void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_vTaskSuspendImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSuspend_Unpriv +MPU_vTaskSuspend_Priv + b MPU_vTaskSuspendImpl +MPU_vTaskSuspend_Unpriv + svc #SYSTEM_CALL_vTaskSuspend +} + +#endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskSuspend == 1 ) + +void MPU_vTaskResume( TaskHandle_t xTaskToResume ) FREERTOS_SYSTEM_CALL; + +__asm void MPU_vTaskResume( TaskHandle_t xTaskToResume ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_vTaskResumeImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskResume_Unpriv +MPU_vTaskResume_Priv + b MPU_vTaskResumeImpl +MPU_vTaskResume_Unpriv + svc #SYSTEM_CALL_vTaskResume +} + +#endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ +/*-----------------------------------------------------------*/ + +TickType_t MPU_xTaskGetTickCount( void ) FREERTOS_SYSTEM_CALL; + +__asm TickType_t MPU_xTaskGetTickCount( void ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_xTaskGetTickCountImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetTickCount_Unpriv +MPU_xTaskGetTickCount_Priv + b MPU_xTaskGetTickCountImpl +MPU_xTaskGetTickCount_Unpriv + svc #SYSTEM_CALL_xTaskGetTickCount +} +/*-----------------------------------------------------------*/ + +UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) FREERTOS_SYSTEM_CALL; + +__asm UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_uxTaskGetNumberOfTasksImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetNumberOfTasks_Unpriv +MPU_uxTaskGetNumberOfTasks_Priv + b MPU_uxTaskGetNumberOfTasksImpl +MPU_uxTaskGetNumberOfTasks_Unpriv + svc #SYSTEM_CALL_uxTaskGetNumberOfTasks +} +/*-----------------------------------------------------------*/ + +#if ( configGENERATE_RUN_TIME_STATS == 1 ) + +configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; + +__asm configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_ulTaskGetRunTimeCounterImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetRunTimeCounter_Unpriv +MPU_ulTaskGetRunTimeCounter_Priv + b MPU_ulTaskGetRunTimeCounterImpl +MPU_ulTaskGetRunTimeCounter_Unpriv + svc #SYSTEM_CALL_ulTaskGetRunTimeCounter +} + +#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( configGENERATE_RUN_TIME_STATS == 1 ) + +configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; + +__asm configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetRunTimePercent( const TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_ulTaskGetRunTimePercentImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetRunTimePercent_Unpriv +MPU_ulTaskGetRunTimePercent_Priv + b MPU_ulTaskGetRunTimePercentImpl +MPU_ulTaskGetRunTimePercent_Unpriv + svc #SYSTEM_CALL_ulTaskGetRunTimePercent +} + +#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + +configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) FREERTOS_SYSTEM_CALL; + +__asm configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_ulTaskGetIdleRunTimePercentImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetIdleRunTimePercent_Unpriv +MPU_ulTaskGetIdleRunTimePercent_Priv + b MPU_ulTaskGetIdleRunTimePercentImpl +MPU_ulTaskGetIdleRunTimePercent_Unpriv + svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent +} + +#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + +configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) FREERTOS_SYSTEM_CALL; + +__asm configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_ulTaskGetIdleRunTimeCounterImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv +MPU_ulTaskGetIdleRunTimeCounter_Priv + b MPU_ulTaskGetIdleRunTimeCounterImpl +MPU_ulTaskGetIdleRunTimeCounter_Unpriv + svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter +} + +#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_APPLICATION_TASK_TAG == 1 ) + +void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) FREERTOS_SYSTEM_CALL; + +__asm void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_vTaskSetApplicationTaskTagImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetApplicationTaskTag_Unpriv +MPU_vTaskSetApplicationTaskTag_Priv + b MPU_vTaskSetApplicationTaskTagImpl +MPU_vTaskSetApplicationTaskTag_Unpriv + svc #SYSTEM_CALL_vTaskSetApplicationTaskTag +} + +#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_APPLICATION_TASK_TAG == 1 ) + +TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; + +__asm TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_xTaskGetApplicationTaskTagImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetApplicationTaskTag_Unpriv +MPU_xTaskGetApplicationTaskTag_Priv + b MPU_xTaskGetApplicationTaskTagImpl +MPU_xTaskGetApplicationTaskTag_Unpriv + svc #SYSTEM_CALL_xTaskGetApplicationTaskTag +} + +#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + +void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) FREERTOS_SYSTEM_CALL; + +__asm void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_vTaskSetThreadLocalStoragePointerImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv +MPU_vTaskSetThreadLocalStoragePointer_Priv + b MPU_vTaskSetThreadLocalStoragePointerImpl +MPU_vTaskSetThreadLocalStoragePointer_Unpriv + svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer +} + +#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + +void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) FREERTOS_SYSTEM_CALL; + +__asm void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_pvTaskGetThreadLocalStoragePointerImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv +MPU_pvTaskGetThreadLocalStoragePointer_Priv + b MPU_pvTaskGetThreadLocalStoragePointerImpl +MPU_pvTaskGetThreadLocalStoragePointer_Unpriv + svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer +} + +#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + +UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) FREERTOS_SYSTEM_CALL; + +__asm UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_uxTaskGetSystemStateImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetSystemState_Unpriv +MPU_uxTaskGetSystemState_Priv + b MPU_uxTaskGetSystemStateImpl +MPU_uxTaskGetSystemState_Unpriv + svc #SYSTEM_CALL_uxTaskGetSystemState +} + +#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) + +UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; + +__asm UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_uxTaskGetStackHighWaterMarkImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetStackHighWaterMark_Unpriv +MPU_uxTaskGetStackHighWaterMark_Priv + b MPU_uxTaskGetStackHighWaterMarkImpl +MPU_uxTaskGetStackHighWaterMark_Unpriv + svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark +} + +#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) + +configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; + +__asm configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_uxTaskGetStackHighWaterMark2Impl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTaskGetStackHighWaterMark2_Unpriv +MPU_uxTaskGetStackHighWaterMark2_Priv + b MPU_uxTaskGetStackHighWaterMark2Impl +MPU_uxTaskGetStackHighWaterMark2_Unpriv + svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2 +} + +#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) + +TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) FREERTOS_SYSTEM_CALL; + +__asm TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_xTaskGetCurrentTaskHandleImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetCurrentTaskHandle_Unpriv +MPU_xTaskGetCurrentTaskHandle_Priv + b MPU_xTaskGetCurrentTaskHandleImpl +MPU_xTaskGetCurrentTaskHandle_Unpriv + svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle +} + +#endif /* if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_xTaskGetSchedulerState == 1 ) + +BaseType_t MPU_xTaskGetSchedulerState( void ) FREERTOS_SYSTEM_CALL; + +__asm BaseType_t MPU_xTaskGetSchedulerState( void ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_xTaskGetSchedulerStateImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGetSchedulerState_Unpriv +MPU_xTaskGetSchedulerState_Priv + b MPU_xTaskGetSchedulerStateImpl +MPU_xTaskGetSchedulerState_Unpriv + svc #SYSTEM_CALL_xTaskGetSchedulerState +} + +#endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */ +/*-----------------------------------------------------------*/ + +void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) FREERTOS_SYSTEM_CALL; + +__asm void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_vTaskSetTimeOutStateImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTaskSetTimeOutState_Unpriv +MPU_vTaskSetTimeOutState_Priv + b MPU_vTaskSetTimeOutStateImpl +MPU_vTaskSetTimeOutState_Unpriv + svc #SYSTEM_CALL_vTaskSetTimeOutState +} +/*-----------------------------------------------------------*/ + +BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) FREERTOS_SYSTEM_CALL; + +__asm BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_xTaskCheckForTimeOutImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskCheckForTimeOut_Unpriv +MPU_xTaskCheckForTimeOut_Priv + b MPU_xTaskCheckForTimeOutImpl +MPU_xTaskCheckForTimeOut_Unpriv + svc #SYSTEM_CALL_xTaskCheckForTimeOut +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_NOTIFICATIONS == 1 ) + +BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) FREERTOS_SYSTEM_CALL; + +__asm BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_xTaskGenericNotifyImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotify_Unpriv +MPU_xTaskGenericNotify_Priv + b MPU_xTaskGenericNotifyImpl +MPU_xTaskGenericNotify_Unpriv + svc #SYSTEM_CALL_xTaskGenericNotify +} + +#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_NOTIFICATIONS == 1 ) + +BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) FREERTOS_SYSTEM_CALL; + +__asm BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_xTaskGenericNotifyWaitImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotifyWait_Unpriv +MPU_xTaskGenericNotifyWait_Priv + b MPU_xTaskGenericNotifyWaitImpl +MPU_xTaskGenericNotifyWait_Unpriv + svc #SYSTEM_CALL_xTaskGenericNotifyWait +} + +#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_NOTIFICATIONS == 1 ) + +uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; + +__asm uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_ulTaskGenericNotifyTakeImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGenericNotifyTake_Unpriv +MPU_ulTaskGenericNotifyTake_Priv + b MPU_ulTaskGenericNotifyTakeImpl +MPU_ulTaskGenericNotifyTake_Unpriv + svc #SYSTEM_CALL_ulTaskGenericNotifyTake +} + +#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_NOTIFICATIONS == 1 ) + +BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) FREERTOS_SYSTEM_CALL; + +__asm BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_xTaskGenericNotifyStateClearImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTaskGenericNotifyStateClear_Unpriv +MPU_xTaskGenericNotifyStateClear_Priv + b MPU_xTaskGenericNotifyStateClearImpl +MPU_xTaskGenericNotifyStateClear_Unpriv + svc #SYSTEM_CALL_xTaskGenericNotifyStateClear +} + +#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_NOTIFICATIONS == 1 ) + +uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) FREERTOS_SYSTEM_CALL; + +__asm uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_ulTaskGenericNotifyValueClearImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_ulTaskGenericNotifyValueClear_Unpriv +MPU_ulTaskGenericNotifyValueClear_Priv + b MPU_ulTaskGenericNotifyValueClearImpl +MPU_ulTaskGenericNotifyValueClear_Unpriv + svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear +} + +#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ +/*-----------------------------------------------------------*/ + +BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) FREERTOS_SYSTEM_CALL; + +__asm BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_xQueueGenericSendImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGenericSend_Unpriv +MPU_xQueueGenericSend_Priv + b MPU_xQueueGenericSendImpl +MPU_xQueueGenericSend_Unpriv + svc #SYSTEM_CALL_xQueueGenericSend +} +/*-----------------------------------------------------------*/ + +UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; + +__asm UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_uxQueueMessagesWaitingImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxQueueMessagesWaiting_Unpriv +MPU_uxQueueMessagesWaiting_Priv + b MPU_uxQueueMessagesWaitingImpl +MPU_uxQueueMessagesWaiting_Unpriv + svc #SYSTEM_CALL_uxQueueMessagesWaiting +} +/*-----------------------------------------------------------*/ + +UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; + +__asm UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_uxQueueSpacesAvailableImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxQueueSpacesAvailable_Unpriv +MPU_uxQueueSpacesAvailable_Priv + b MPU_uxQueueSpacesAvailableImpl +MPU_uxQueueSpacesAvailable_Unpriv + svc #SYSTEM_CALL_uxQueueSpacesAvailable +} +/*-----------------------------------------------------------*/ + +BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; + +__asm BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_xQueueReceiveImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueReceive_Unpriv +MPU_xQueueReceive_Priv + b MPU_xQueueReceiveImpl +MPU_xQueueReceive_Unpriv + svc #SYSTEM_CALL_xQueueReceive +} +/*-----------------------------------------------------------*/ + +BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; + +__asm BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_xQueuePeekImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueuePeek_Unpriv +MPU_xQueuePeek_Priv + b MPU_xQueuePeekImpl +MPU_xQueuePeek_Unpriv + svc #SYSTEM_CALL_xQueuePeek +} +/*-----------------------------------------------------------*/ + +BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; + +__asm BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_xQueueSemaphoreTakeImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueSemaphoreTake_Unpriv +MPU_xQueueSemaphoreTake_Priv + b MPU_xQueueSemaphoreTakeImpl +MPU_xQueueSemaphoreTake_Unpriv + svc #SYSTEM_CALL_xQueueSemaphoreTake +} +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) + +TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) FREERTOS_SYSTEM_CALL; + +__asm TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_xQueueGetMutexHolderImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGetMutexHolder_Unpriv +MPU_xQueueGetMutexHolder_Priv + b MPU_xQueueGetMutexHolderImpl +MPU_xQueueGetMutexHolder_Unpriv + svc #SYSTEM_CALL_xQueueGetMutexHolder +} + +#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_RECURSIVE_MUTEXES == 1 ) + +BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; + +__asm BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_xQueueTakeMutexRecursiveImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueTakeMutexRecursive_Unpriv +MPU_xQueueTakeMutexRecursive_Priv + b MPU_xQueueTakeMutexRecursiveImpl +MPU_xQueueTakeMutexRecursive_Unpriv + svc #SYSTEM_CALL_xQueueTakeMutexRecursive +} + +#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_RECURSIVE_MUTEXES == 1 ) + +BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) FREERTOS_SYSTEM_CALL; + +__asm BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_xQueueGiveMutexRecursiveImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueGiveMutexRecursive_Unpriv +MPU_xQueueGiveMutexRecursive_Priv + b MPU_xQueueGiveMutexRecursiveImpl +MPU_xQueueGiveMutexRecursive_Unpriv + svc #SYSTEM_CALL_xQueueGiveMutexRecursive +} + +#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_QUEUE_SETS == 1 ) + +QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; + +__asm QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_xQueueSelectFromSetImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueSelectFromSet_Unpriv +MPU_xQueueSelectFromSet_Priv + b MPU_xQueueSelectFromSetImpl +MPU_xQueueSelectFromSet_Unpriv + svc #SYSTEM_CALL_xQueueSelectFromSet +} + +#endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_QUEUE_SETS == 1 ) + +BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL; + +__asm BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_xQueueAddToSetImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xQueueAddToSet_Unpriv +MPU_xQueueAddToSet_Priv + b MPU_xQueueAddToSetImpl +MPU_xQueueAddToSet_Unpriv + svc #SYSTEM_CALL_xQueueAddToSet +} + +#endif /* if ( configUSE_QUEUE_SETS == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( configQUEUE_REGISTRY_SIZE > 0 ) + +void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) FREERTOS_SYSTEM_CALL; + +__asm void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_vQueueAddToRegistryImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vQueueAddToRegistry_Unpriv +MPU_vQueueAddToRegistry_Priv + b MPU_vQueueAddToRegistryImpl +MPU_vQueueAddToRegistry_Unpriv + svc #SYSTEM_CALL_vQueueAddToRegistry +} + +#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( configQUEUE_REGISTRY_SIZE > 0 ) + +void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; + +__asm void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_vQueueUnregisterQueueImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vQueueUnregisterQueue_Unpriv +MPU_vQueueUnregisterQueue_Priv + b MPU_vQueueUnregisterQueueImpl +MPU_vQueueUnregisterQueue_Unpriv + svc #SYSTEM_CALL_vQueueUnregisterQueue +} + +#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( configQUEUE_REGISTRY_SIZE > 0 ) + +const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; + +__asm const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_pcQueueGetNameImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pcQueueGetName_Unpriv +MPU_pcQueueGetName_Priv + b MPU_pcQueueGetNameImpl +MPU_pcQueueGetName_Unpriv + svc #SYSTEM_CALL_pcQueueGetName +} + +#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TIMERS == 1 ) + +void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; + +__asm void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_pvTimerGetTimerIDImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pvTimerGetTimerID_Unpriv +MPU_pvTimerGetTimerID_Priv + b MPU_pvTimerGetTimerIDImpl +MPU_pvTimerGetTimerID_Unpriv + svc #SYSTEM_CALL_pvTimerGetTimerID +} + +#endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TIMERS == 1 ) + +void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) FREERTOS_SYSTEM_CALL; + +__asm void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_vTimerSetTimerIDImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTimerSetTimerID_Unpriv +MPU_vTimerSetTimerID_Priv + b MPU_vTimerSetTimerIDImpl +MPU_vTimerSetTimerID_Unpriv + svc #SYSTEM_CALL_vTimerSetTimerID +} + +#endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TIMERS == 1 ) + +BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; + +__asm BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_xTimerIsTimerActiveImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerIsTimerActive_Unpriv +MPU_xTimerIsTimerActive_Priv + b MPU_xTimerIsTimerActiveImpl +MPU_xTimerIsTimerActive_Unpriv + svc #SYSTEM_CALL_xTimerIsTimerActive +} + +#endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TIMERS == 1 ) + +TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) FREERTOS_SYSTEM_CALL; + +__asm TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_xTimerGetTimerDaemonTaskHandleImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv +MPU_xTimerGetTimerDaemonTaskHandle_Priv + b MPU_xTimerGetTimerDaemonTaskHandleImpl +MPU_xTimerGetTimerDaemonTaskHandle_Unpriv + svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle +} + +#endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TIMERS == 1 ) + +BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) FREERTOS_SYSTEM_CALL; + +__asm BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_xTimerGenericCommandFromTaskImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGenericCommandFromTask_Unpriv +MPU_xTimerGenericCommandFromTask_Priv + b MPU_xTimerGenericCommandFromTaskImpl +MPU_xTimerGenericCommandFromTask_Unpriv + svc #SYSTEM_CALL_xTimerGenericCommandFromTask +} + +#endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TIMERS == 1 ) + +const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; + +__asm const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_pcTimerGetNameImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_pcTimerGetName_Unpriv +MPU_pcTimerGetName_Priv + b MPU_pcTimerGetNameImpl +MPU_pcTimerGetName_Unpriv + svc #SYSTEM_CALL_pcTimerGetName +} + +#endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TIMERS == 1 ) + +void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) FREERTOS_SYSTEM_CALL; + +__asm void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_vTimerSetReloadModeImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vTimerSetReloadMode_Unpriv +MPU_vTimerSetReloadMode_Priv + b MPU_vTimerSetReloadModeImpl +MPU_vTimerSetReloadMode_Unpriv + svc #SYSTEM_CALL_vTimerSetReloadMode +} + +#endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TIMERS == 1 ) + +BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; + +__asm BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_xTimerGetReloadModeImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetReloadMode_Unpriv +MPU_xTimerGetReloadMode_Priv + b MPU_xTimerGetReloadModeImpl +MPU_xTimerGetReloadMode_Unpriv + svc #SYSTEM_CALL_xTimerGetReloadMode +} + +#endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TIMERS == 1 ) + +UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; + +__asm UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_uxTimerGetReloadModeImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxTimerGetReloadMode_Unpriv +MPU_uxTimerGetReloadMode_Priv + b MPU_uxTimerGetReloadModeImpl +MPU_uxTimerGetReloadMode_Unpriv + svc #SYSTEM_CALL_uxTimerGetReloadMode +} + +#endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TIMERS == 1 ) + +TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; + +__asm TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_xTimerGetPeriodImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetPeriod_Unpriv +MPU_xTimerGetPeriod_Priv + b MPU_xTimerGetPeriodImpl +MPU_xTimerGetPeriod_Unpriv + svc #SYSTEM_CALL_xTimerGetPeriod +} + +#endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TIMERS == 1 ) + +TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; + +__asm TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_xTimerGetExpiryTimeImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xTimerGetExpiryTime_Unpriv +MPU_xTimerGetExpiryTime_Priv + b MPU_xTimerGetExpiryTimeImpl +MPU_xTimerGetExpiryTime_Unpriv + svc #SYSTEM_CALL_xTimerGetExpiryTime +} + +#endif /* if ( configUSE_TIMERS == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_EVENT_GROUPS == 1 ) + +EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) FREERTOS_SYSTEM_CALL; + +__asm EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_xEventGroupWaitBitsImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupWaitBits_Unpriv +MPU_xEventGroupWaitBits_Priv + b MPU_xEventGroupWaitBitsImpl +MPU_xEventGroupWaitBits_Unpriv + svc #SYSTEM_CALL_xEventGroupWaitBits +} + +#endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_EVENT_GROUPS == 1 ) + +EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) FREERTOS_SYSTEM_CALL; + +__asm EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_xEventGroupClearBitsImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupClearBits_Unpriv +MPU_xEventGroupClearBits_Priv + b MPU_xEventGroupClearBitsImpl +MPU_xEventGroupClearBits_Unpriv + svc #SYSTEM_CALL_xEventGroupClearBits +} + +#endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_EVENT_GROUPS == 1 ) + +EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) FREERTOS_SYSTEM_CALL; + +__asm EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_xEventGroupSetBitsImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupSetBits_Unpriv +MPU_xEventGroupSetBits_Priv + b MPU_xEventGroupSetBitsImpl +MPU_xEventGroupSetBits_Unpriv + svc #SYSTEM_CALL_xEventGroupSetBits +} + +#endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_EVENT_GROUPS == 1 ) + +EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; + +__asm EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_xEventGroupSyncImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xEventGroupSync_Unpriv +MPU_xEventGroupSync_Priv + b MPU_xEventGroupSyncImpl +MPU_xEventGroupSync_Unpriv + svc #SYSTEM_CALL_xEventGroupSync +} + +#endif /* #if ( configUSE_EVENT_GROUPS == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + +UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) FREERTOS_SYSTEM_CALL; + +__asm UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_uxEventGroupGetNumberImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_uxEventGroupGetNumber_Unpriv +MPU_uxEventGroupGetNumber_Priv + b MPU_uxEventGroupGetNumberImpl +MPU_uxEventGroupGetNumber_Unpriv + svc #SYSTEM_CALL_uxEventGroupGetNumber +} + +#endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + +void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) FREERTOS_SYSTEM_CALL; + +__asm void MPU_vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_vEventGroupSetNumberImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_vEventGroupSetNumber_Unpriv +MPU_vEventGroupSetNumber_Priv + b MPU_vEventGroupSetNumberImpl +MPU_vEventGroupSetNumber_Unpriv + svc #SYSTEM_CALL_vEventGroupSetNumber +} + +#endif /* #if ( ( configUSE_EVENT_GROUPS == 1 ) && ( configUSE_TRACE_FACILITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_STREAM_BUFFERS == 1 ) + +size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; + +__asm size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_xStreamBufferSendImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSend_Unpriv +MPU_xStreamBufferSend_Priv + b MPU_xStreamBufferSendImpl +MPU_xStreamBufferSend_Unpriv + svc #SYSTEM_CALL_xStreamBufferSend +} + +#endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_STREAM_BUFFERS == 1 ) + +size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; + +__asm size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_xStreamBufferReceiveImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferReceive_Unpriv +MPU_xStreamBufferReceive_Priv + b MPU_xStreamBufferReceiveImpl +MPU_xStreamBufferReceive_Unpriv + svc #SYSTEM_CALL_xStreamBufferReceive +} + +#endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_STREAM_BUFFERS == 1 ) + +BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; + +__asm BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_xStreamBufferIsFullImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferIsFull_Unpriv +MPU_xStreamBufferIsFull_Priv + b MPU_xStreamBufferIsFullImpl +MPU_xStreamBufferIsFull_Unpriv + svc #SYSTEM_CALL_xStreamBufferIsFull +} + +#endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_STREAM_BUFFERS == 1 ) + +BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; + +__asm BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_xStreamBufferIsEmptyImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferIsEmpty_Unpriv +MPU_xStreamBufferIsEmpty_Priv + b MPU_xStreamBufferIsEmptyImpl +MPU_xStreamBufferIsEmpty_Unpriv + svc #SYSTEM_CALL_xStreamBufferIsEmpty +} + +#endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_STREAM_BUFFERS == 1 ) + +size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; + +__asm size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_xStreamBufferSpacesAvailableImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSpacesAvailable_Unpriv +MPU_xStreamBufferSpacesAvailable_Priv + b MPU_xStreamBufferSpacesAvailableImpl +MPU_xStreamBufferSpacesAvailable_Unpriv + svc #SYSTEM_CALL_xStreamBufferSpacesAvailable +} + +#endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_STREAM_BUFFERS == 1 ) + +size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; + +__asm size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_xStreamBufferBytesAvailableImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferBytesAvailable_Unpriv +MPU_xStreamBufferBytesAvailable_Priv + b MPU_xStreamBufferBytesAvailableImpl +MPU_xStreamBufferBytesAvailable_Unpriv + svc #SYSTEM_CALL_xStreamBufferBytesAvailable +} + +#endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_STREAM_BUFFERS == 1 ) + +BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) FREERTOS_SYSTEM_CALL; + +__asm BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_xStreamBufferSetTriggerLevelImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferSetTriggerLevel_Unpriv +MPU_xStreamBufferSetTriggerLevel_Priv + b MPU_xStreamBufferSetTriggerLevelImpl +MPU_xStreamBufferSetTriggerLevel_Unpriv + svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel +} + +#endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_STREAM_BUFFERS == 1 ) + +size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; + +__asm size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */ +{ + PRESERVE8 + extern MPU_xStreamBufferNextMessageLengthBytesImpl + + push {r0} + mrs r0, control + tst r0, #1 + pop {r0} + bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv +MPU_xStreamBufferNextMessageLengthBytes_Priv + b MPU_xStreamBufferNextMessageLengthBytesImpl +MPU_xStreamBufferNextMessageLengthBytes_Unpriv + svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes +} + +#endif /* #if ( configUSE_STREAM_BUFFERS == 1 ) */ +/*-----------------------------------------------------------*/ + +#endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ diff --git a/portable/RVDS/ARM_CM4_MPU/port.c b/portable/RVDS/ARM_CM4_MPU/port.c new file mode 100644 index 000000000..450b86211 --- /dev/null +++ b/portable/RVDS/ARM_CM4_MPU/port.c @@ -0,0 +1,1731 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2025 Arm Limited and/or its affiliates + * + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ARM CM4 MPU port. +*----------------------------------------------------------*/ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "mpu_syscall_numbers.h" + +#ifndef __TARGET_FPU_VFP + #error This port can only be used when the project options are configured to enable hardware floating point support. +#endif + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#ifndef configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS + #warning "configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS is not defined. We recommend defining it to 0 in FreeRTOSConfig.h for better security." + #define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS 1 +#endif + +/* Prototype of all Interrupt Service Routines (ISRs). */ +typedef void ( * portISR_t )( void ); + +/* Constants required to access and manipulate the NVIC. */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) ) +#define portNVIC_SYS_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) +#define portNVIC_MEM_FAULT_ENABLE ( 1UL << 16UL ) + +/* Constants used to detect Cortex-M7 r0p0 and r0p1 cores, and ensure + * that a work around is active for errata 837070. */ +#define portCPUID ( *( ( volatile uint32_t * ) 0xE000ed00 ) ) +#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL ) +#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL ) + +/* Constants required to access and manipulate the MPU. */ +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_REGION_BASE_ADDRESS_REG ( *( ( volatile uint32_t * ) 0xe000ed9C ) ) +#define portMPU_REGION_ATTRIBUTE_REG ( *( ( volatile uint32_t * ) 0xe000edA0 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL ) +#define portMPU_ENABLE ( 0x01UL ) +#define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL ) +#define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL ) +#define portMPU_REGION_VALID ( 0x10UL ) +#define portMPU_REGION_ENABLE ( 0x01UL ) +#define portPERIPHERALS_START_ADDRESS 0x40000000UL +#define portPERIPHERALS_END_ADDRESS 0x5FFFFFFFUL + +/* Constants required to access and manipulate the SysTick. */ +#define portNVIC_SYSTICK_CLK ( 0x00000004UL ) +#define portNVIC_SYSTICK_INT ( 0x00000002UL ) +#define portNVIC_SYSTICK_ENABLE ( 0x00000001UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL ) +#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL ) + +/* Constants required to manipulate the VFP. */ +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34UL ) /* Floating point context control register. */ +#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000UL ) +#define portINITIAL_EXC_RETURN ( 0xfffffffdUL ) +#define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 ) +#define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 ) + +/* Constants used to check the installation of the FreeRTOS interrupt handlers. */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xE000ED08 ) ) +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) + +/* Constants required to check the validity of an interrupt priority. */ +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) + +/* Constants used during system call enter and exit. */ +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) + +/* Offsets in the stack to the parameters when inside the SVC handler. */ +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) + +/* For strict compliance with the Cortex-M spec the task start address should + * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */ +#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL ) + +/* Does addr lie within [start, end] address range? */ +#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \ + ( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) ) + +/* Is the access request satisfied by the available permissions? */ +#define portIS_AUTHORIZED( accessRequest, permissions ) \ + ( ( ( permissions ) & ( accessRequest ) ) == accessRequest ) + +/* Max value that fits in a uint32_t type. */ +#define portUINT32_MAX ( ~( ( uint32_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define portADD_UINT32_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT32_MAX - ( b ) ) ) +/*-----------------------------------------------------------*/ + +/* Each task maintains its own interrupt status in the critical nesting + * variable. Note this is not saved as part of the task context as context + * switches can only occur when uxCriticalNesting is zero. */ +PRIVILEGED_DATA static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + +/* + * This variable is set to pdTRUE when the scheduler is started. + */ + PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE; + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/* + * Setup the timer to generate the tick interrupts. + */ +void vSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/* + * Configure a number of standard MPU regions that are used by all tasks. + */ +static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; + +/* + * Start first task is a separate function so it can be tested in isolation. + */ +static void prvStartFirstTask( void ) PRIVILEGED_FUNCTION; + +/* + * Return the smallest MPU region size that a given number of bytes will fit + * into. The region size is returned as the value that should be programmed + * into the region attribute register for that region. + */ +static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION; + +/* + * Standard FreeRTOS exception handlers. + */ +void xPortPendSVHandler( void ) PRIVILEGED_FUNCTION; +void xPortSysTickHandler( void ) PRIVILEGED_FUNCTION; +void vPortSVCHandler( void ) PRIVILEGED_FUNCTION; + +/* + * Starts the scheduler by restoring the context of the first task to run. + */ +static void prvRestoreContextOfFirstTask( void ) PRIVILEGED_FUNCTION; + +/* + * C portion of the SVC handler. The SVC handler is split between an asm entry + * and a C wrapper for simplicity of coding and maintenance. + */ +void vSVCHandler_C( uint32_t * pulRegisters ) __attribute__( ( used ) ) PRIVILEGED_FUNCTION; + +/* + * Function to enable the VFP. + */ +static void vPortEnableVFP( void ); + +/* + * Utility function. + */ +static uint32_t prvPortGetIPSR( void ); + +/* + * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( configASSERT_DEFINED == 1 ) + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; +#endif /* configASSERT_DEFINED */ + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ); + +/** + * @brief Make a task unprivileged. + */ +void vPortSwitchToUserMode( void ); + +/** + * @brief Enter critical section. + */ +#if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) + void vPortEnterCritical( void ) FREERTOS_SYSTEM_CALL; +#else + void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; +#endif + +/** + * @brief Exit from critical section. + */ +#if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) + void vPortExitCritical( void ) FREERTOS_SYSTEM_CALL; +#else + void vPortExitCritical( void ) PRIVILEGED_FUNCTION; +#endif + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + +/** + * @brief Triggers lazy stacking of FPU registers. + */ + static void prvTriggerLazyStacking( void ) PRIVILEGED_FUNCTION; + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + +/** + * @brief Sets up the system call stack so that upon returning from + * SVC, the system call stack is used. + * + * @param pulTaskStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + * @param ucSystemCallNumber The system call number of the system call. + */ + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) PRIVILEGED_FUNCTION; + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + +/** + * @brief Raise SVC for exiting from a system call. + */ + void vRequestSystemCallExit( void ) PRIVILEGED_FUNCTION; + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + +/** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) PRIVILEGED_FUNCTION; + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ +BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged, + xMPU_SETTINGS * xMPUSettings ) +{ + if( xRunPrivileged == pdTRUE ) + { + xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; + xMPUSettings->ulContext[ 0 ] = portINITIAL_CONTROL_IF_PRIVILEGED; + } + else + { + xMPUSettings->ulTaskFlags &= ( ~( portTASK_IS_PRIVILEGED_FLAG ) ); + xMPUSettings->ulContext[ 0 ] = portINITIAL_CONTROL_IF_UNPRIVILEGED; + } + + xMPUSettings->ulContext[ 1 ] = 0x04040404; /* r4. */ + xMPUSettings->ulContext[ 2 ] = 0x05050505; /* r5. */ + xMPUSettings->ulContext[ 3 ] = 0x06060606; /* r6. */ + xMPUSettings->ulContext[ 4 ] = 0x07070707; /* r7. */ + xMPUSettings->ulContext[ 5 ] = 0x08080808; /* r8. */ + xMPUSettings->ulContext[ 6 ] = 0x09090909; /* r9. */ + xMPUSettings->ulContext[ 7 ] = 0x10101010; /* r10. */ + xMPUSettings->ulContext[ 8 ] = 0x11111111; /* r11. */ + xMPUSettings->ulContext[ 9 ] = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ + + xMPUSettings->ulContext[ 10 ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ + xMPUSettings->ulContext[ 11 ] = ( uint32_t ) pvParameters; /* r0. */ + xMPUSettings->ulContext[ 12 ] = 0x01010101; /* r1. */ + xMPUSettings->ulContext[ 13 ] = 0x02020202; /* r2. */ + xMPUSettings->ulContext[ 14 ] = 0x03030303; /* r3. */ + xMPUSettings->ulContext[ 15 ] = 0x12121212; /* r12. */ + xMPUSettings->ulContext[ 16 ] = 0; /* LR. */ + xMPUSettings->ulContext[ 17 ] = ( ( uint32_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC. */ + xMPUSettings->ulContext[ 18 ] = portINITIAL_XPSR; /* xPSR. */ + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + { + /* Ensure that the system call stack is double word aligned. */ + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = &( xMPUSettings->xSystemCallStackInfo.ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE - 1 ] ); + xMPUSettings->xSystemCallStackInfo.pulSystemCallStack = ( uint32_t * ) ( ( uint32_t ) ( xMPUSettings->xSystemCallStackInfo.pulSystemCallStack ) & + ( uint32_t ) ( ~( portBYTE_ALIGNMENT_MASK ) ) ); + + /* This is not NULL only for the duration of a system call. */ + xMPUSettings->xSystemCallStackInfo.pulTaskStack = NULL; + } + #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + return &( xMPUSettings->ulContext[ 19 ] ); +} +/*-----------------------------------------------------------*/ + +void vSVCHandler_C( uint32_t * pulParam ) +{ + uint8_t ucSVCNumber; + uint32_t ulPC; + + #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) + uint32_t ulReg; + #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( ( configUSE_MPU_WRAPPERS_V1 == 1 ) && ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) ) + extern uint32_t __syscalls_flash_start__; + extern uint32_t __syscalls_flash_end__; + #endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 1 ) && ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) ) */ + + /* The stack contains: r0, r1, r2, r3, r12, LR, PC and xPSR. The first + * argument (r0) is pulParam[ 0 ]. */ + ulPC = pulParam[ portOFFSET_TO_PC ]; + ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + case portSVC_START_SCHEDULER: + prvRestoreContextOfFirstTask(); + break; + + case portSVC_YIELD: + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required + * but do ensure the code is completely + * within the specified behaviour for the + * architecture. */ + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + break; + + #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) + #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) + case portSVC_RAISE_PRIVILEGE: /* Only raise the privilege, if the + * svc was raised from any of the + * system calls. */ + + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + __asm + { + /* *INDENT-OFF* */ + mrs ulReg, control /* Obtain current control value. */ + bic ulReg, # 1 /* Set privilege bit. */ + msr control, ulReg /* Write back new control value. */ + /* *INDENT-ON* */ + } + } + + break; + #else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */ + case portSVC_RAISE_PRIVILEGE: + __asm + { + /* *INDENT-OFF* */ + mrs ulReg, control /* Obtain current control value. */ + bic ulReg, # 1 /* Set privilege bit. */ + msr control, ulReg /* Write back new control value. */ + /* *INDENT-ON* */ + } + break; + #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */ + #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + default: /* Unknown SVC call. */ + break; + } +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + __asm void prvTriggerLazyStacking( void ) /* PRIVILEGED_FUNCTION */ + { + /* *INDENT-OFF* */ + PRESERVE8 + + vpush {s0} /* Trigger lazy stacking. */ + vpop {s0} /* Nullify the affect of the above instruction. */ + + /* *INDENT-ON* */ + } + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + void vSystemCallEnter( uint32_t * pulTaskStack, + uint32_t ulLR, + uint8_t ucSystemCallNumber ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + extern UBaseType_t uxSystemCallImplementations[ NUM_SYSTEM_CALLS ]; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulSystemCallStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i, r1; + extern uint32_t __syscalls_flash_start__; + extern uint32_t __syscalls_flash_end__; + + ulSystemCallLocation = pulTaskStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the system call section (i.e. application is + * not raising SVC directly). + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must be NULL as + * it is non-NULL only during the execution of a system call (i.e. + * between system call enter and exit). + * 3. System call is not for a kernel API disabled by the configuration + * in FreeRTOSConfig.h. + * 4. We do not need to check that ucSystemCallNumber is within range + * because the assembly SVC handler checks that before calling + * this function. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __syscalls_flash_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack == NULL ) && + ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) ) + { + pulSystemCallStack = pxMpuSettings->xSystemCallStackInfo.pulSystemCallStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + prvTriggerLazyStacking(); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + + /* Make space on the system call stack for the stack frame. */ + pulSystemCallStack = pulSystemCallStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulSystemCallStack[ i ] = pulTaskStack[ i ]; + } + + /* Use the pulSystemCallStack in thread mode. */ + __asm + { + msr psp, pulSystemCallStack + }; + + /* Raise the privilege for the duration of the system call. */ + __asm + { + mrs r1, control /* Obtain current control value. */ + bic r1, # 1 /* Clear nPRIV bit. */ + msr control, r1 /* Write back new control value. */ + }; + + /* Remember the location where we should copy the stack frame when we exit from + * the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = pulTaskStack + ulHardwareSavedExceptionFrameSize; + + /* Store the value of the Link Register before the SVC was raised. + * It contains the address of the caller of the System Call entry + * point (i.e. the caller of the MPU_). We need to restore it + * when we exit from the system call. */ + pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry = pulTaskStack[ portOFFSET_TO_LR ]; + + /* Start executing the system call upon returning from this handler. */ + pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; + /* Raise a request to exit from the system call upon finishing the + * system call. */ + pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; + + /* Record if the hardware used padding to force the stack pointer + * to be double word aligned. */ + if( ( pulTaskStack[ portOFFSET_TO_PSR ] & portPSR_STACK_PADDING_MASK ) == portPSR_STACK_PADDING_MASK ) + { + pxMpuSettings->ulTaskFlags |= portSTACK_FRAME_HAS_PADDING_FLAG; + } + else + { + pxMpuSettings->ulTaskFlags &= ( ~portSTACK_FRAME_HAS_PADDING_FLAG ); + } + + /* We ensure in pxPortInitialiseStack that the system call stack is + * double word aligned and therefore, there is no need of padding. + * Clear the bit[9] of stacked xPSR. */ + pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + } + } + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + __asm void vRequestSystemCallExit( void ) /* PRIVILEGED_FUNCTION */ + { + PRESERVE8 + + svc #portSVC_SYSTEM_CALL_EXIT + } + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + void vSystemCallExit( uint32_t * pulSystemCallStack, + uint32_t ulLR ) /* PRIVILEGED_FUNCTION */ + { + extern TaskHandle_t pxCurrentTCB; + xMPU_SETTINGS * pxMpuSettings; + uint32_t * pulTaskStack; + uint32_t ulHardwareSavedExceptionFrameSize, ulSystemCallLocation, i, r1; + extern uint32_t __privileged_functions_start__; + extern uint32_t __privileged_functions_end__; + + ulSystemCallLocation = pulSystemCallStack[ portOFFSET_TO_PC ]; + pxMpuSettings = xTaskGetMPUSettings( pxCurrentTCB ); + + /* Checks: + * 1. SVC is raised from the privileged code (i.e. application is not + * raising SVC directly). This SVC is only raised from + * vRequestSystemCallExit which is in the privileged code section. + * 2. pxMpuSettings->xSystemCallStackInfo.pulTaskStack must not be NULL - + * this means that we previously entered a system call and the + * application is not attempting to exit without entering a system + * call. + */ + if( ( ulSystemCallLocation >= ( uint32_t ) __privileged_functions_start__ ) && + ( ulSystemCallLocation <= ( uint32_t ) __privileged_functions_end__ ) && + ( pxMpuSettings->xSystemCallStackInfo.pulTaskStack != NULL ) ) + { + pulTaskStack = pxMpuSettings->xSystemCallStackInfo.pulTaskStack; + + /* Hardware Saved Stack Frame Size upon Exception entry: + * - No FPU: basic frame (R0-R3, R12, LR, PC, and xPSR) = 8 words. + * - With FPU (lazy stacking): basic frame + S0–S15 + FPSCR + reserved word = 26 words. + */ + if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) + { + /* Extended frame i.e. FPU in use. */ + ulHardwareSavedExceptionFrameSize = 26; + prvTriggerLazyStacking(); + } + else + { + /* Standard frame i.e. FPU not in use. */ + ulHardwareSavedExceptionFrameSize = 8; + } + + /* Make space on the task stack for the stack frame. */ + pulTaskStack = pulTaskStack - ulHardwareSavedExceptionFrameSize; + + /* Copy the stack frame. */ + for( i = 0; i < ulHardwareSavedExceptionFrameSize; i++ ) + { + pulTaskStack[ i ] = pulSystemCallStack[ i ]; + } + + /* Use the pulTaskStack in thread mode. */ + __asm + { + msr psp, pulTaskStack + }; + + /* Drop the privilege before returning to the thread mode. */ + __asm + { + mrs r1, control /* Obtain current control value. */ + orr r1, # 1 /* Set nPRIV bit. */ + msr control, r1 /* Write back new control value. */ + }; + + /* Return to the caller of the System Call entry point (i.e. the + * caller of the MPU_). */ + pulTaskStack[ portOFFSET_TO_PC ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + /* Ensure that LR has a valid value.*/ + pulTaskStack[ portOFFSET_TO_LR ] = pxMpuSettings->xSystemCallStackInfo.ulLinkRegisterAtSystemCallEntry; + + /* If the hardware used padding to force the stack pointer + * to be double word aligned, set the stacked xPSR bit[9], + * otherwise clear it. */ + if( ( pxMpuSettings->ulTaskFlags & portSTACK_FRAME_HAS_PADDING_FLAG ) == portSTACK_FRAME_HAS_PADDING_FLAG ) + { + pulTaskStack[ portOFFSET_TO_PSR ] |= portPSR_STACK_PADDING_MASK; + } + else + { + pulTaskStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); + } + + /* This is not NULL only for the duration of the system call. */ + pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; + } + } + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortIsTaskPrivileged( void ) /* PRIVILEGED_FUNCTION */ +{ + BaseType_t xTaskIsPrivileged = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xTaskIsPrivileged = pdTRUE; + } + + return xTaskIsPrivileged; +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + __asm void vPortSVCHandler( void ) + { + extern vSVCHandler_C + extern vSystemCallEnter + extern vSystemCallExit + +/* *INDENT-OFF* */ + PRESERVE8 + + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + + ldr r1, [r0, #24] + ldrb r2, [r1, #-2] + cmp r2, #NUM_SYSTEM_CALLS + blt syscall_enter + cmp r2, #portSVC_SYSTEM_CALL_EXIT + beq syscall_exit + b vSVCHandler_C + +syscall_enter + mov r1, lr + b vSystemCallEnter + +syscall_exit + mov r1, lr + b vSystemCallExit +/* *INDENT-ON* */ + } + +#else /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + __asm void vPortSVCHandler( void ) + { + extern vSVCHandler_C + +/* *INDENT-OFF* */ + PRESERVE8 + + /* Assumes psp was in use. */ + #ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */ + tst lr, # 4 + ite eq + mrseq r0, msp + mrsne r0, psp + #else + mrs r0, psp + #endif + + b vSVCHandler_C +/* *INDENT-ON* */ + } + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +__asm void prvRestoreContextOfFirstTask( void ) +{ +/* *INDENT-OFF* */ + PRESERVE8 + + ldr r0, =0xE000ED08 /* Use the NVIC offset register to locate the stack. */ + ldr r0, [r0] + ldr r0, [r0] + msr msp, r0 /* Set the msp back to the start of the stack. */ + + /*------------ Program MPU. ------------ */ + ldr r3, =pxCurrentTCB /* r3 = &( pxCurrentTCB ). */ + ldr r2, [r3] /* r2 = pxCurrentTCB. */ + add r2, r2, #4 /* r2 = Second item in the TCB which is xMPUSettings. */ + + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r0, =0xe000ed94 /* MPU_CTRL register. */ + ldr r3, [r0] /* Read the value of MPU_CTRL. */ + bic r3, r3, # 1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */ + str r3, [r0] /* Disable MPU. */ + + ldr r0, =0xe000ed9c /* Region Base Address register. */ + ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */ + stmia r0, {r4-r11} /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */ + + #if ( configTOTAL_MPU_REGIONS == 16 ) + ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */ + stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 4 - 7]. */ + ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */ + stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */ + #endif /* configTOTAL_MPU_REGIONS == 16. */ + + ldr r0, =0xe000ed94 /* MPU_CTRL register. */ + ldr r3, [r0] /* Read the value of MPU_CTRL. */ + orr r3, r3, #1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */ + str r3, [r0] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + + /*---------- Restore Context. ---------- */ + ldr r3, =pxCurrentTCB /* r3 = &( pxCurrentTCB ). */ + ldr r2, [r3] /* r2 = pxCurrentTCB. */ + ldr r1, [r2] /* r1 = Location of saved context in TCB. */ + + ldmdb r1!, {r0, r4-r11} /* r0 contains PSP after the hardware had saved context. r4-r11 contain hardware saved context. */ + msr psp, r0 + stmia r0, {r4-r11} /* Copy the hardware saved context on the task stack. */ + ldmdb r1!, {r3-r11, lr} /* r3 contains CONTROL register. r4-r11 and LR restored. */ + msr control, r3 + str r1, [r2] /* Save the location where the context should be saved next as the first member of TCB. */ + + mov r0, #0 + msr basepri, r0 + bx lr +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY ); + + /* Errata 837070 workaround must only be enabled on Cortex-M7 r0p0 + * and r0p1 cores. */ + #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) + configASSERT( ( portCPUID == portCORTEX_M7_r0p1_ID ) || ( portCPUID == portCORTEX_M7_r0p0_ID ) ); + #else + + /* When using this port on a Cortex-M7 r0p0 or r0p1 core, define + * configENABLE_ERRATA_837070_WORKAROUND to 1 in your + * FreeRTOSConfig.h. */ + configASSERT( portCPUID != portCORTEX_M7_r0p1_ID ); + configASSERT( portCPUID != portCORTEX_M7_r0p0_ID ); + #endif + + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions vPortSVCHandler and + * xPortPendSVHandler for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * vPortSVCHandler and xPortPendSVHandler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( configASSERT_DEFINED == 1 ) + { + volatile uint8_t ucOriginalPriority; + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * Save the interrupt priority value that is about to be clobbered. */ + ucOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to all + * possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + + /* Restore the clobbered interrupt priority register to its original + * value. */ + *pucFirstUserPriorityRegister = ucOriginalPriority; + } + #endif /* configASSERT_DEFINED */ + + /* Make PendSV and SysTick the same priority as the kernel, and the SVC + * handler highest priority so it can be used to exit a critical section + * (where lower priorities are masked). */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + /* Configure the regions in the MPU that are common to all tasks. */ + prvSetupMPU(); + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + { + xSchedulerRunning = pdTRUE; + } + #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + + /* Ensure the VFP is enabled - it should be anyway. */ + vPortEnableVFP(); + + /* Lazy save always. */ + *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; + + /* Start the first task. */ + prvStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +__asm void prvStartFirstTask( void ) +{ +/* *INDENT-OFF* */ + PRESERVE8 + + /* Use the NVIC offset register to locate the stack. */ + ldr r0, =0xE000ED08 + ldr r0, [ r0 ] + ldr r0, [ r0 ] + /* Set the msp back to the start of the stack. */ + msr msp, r0 + + /* Clear the bit that indicates the FPU is in use in case the FPU was used + * before the scheduler was started - which would otherwise result in the + * unnecessary leaving of space in the SVC stack for lazy saving of FPU + * registers. */ + mov r0, #0 + msr control, r0 + /* Globally enable interrupts. */ + cpsie i + cpsie f + dsb + isb + svc portSVC_START_SCHEDULER /* System call to start first task. */ + nop + nop +/* *INDENT-ON* */ +} + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + #if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + } + #else /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + #endif /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */ +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + #if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) + if( portIS_PRIVILEGED() == pdFALSE ) + { + portRAISE_PRIVILEGE(); + portMEMORY_BARRIER(); + + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + + portMEMORY_BARRIER(); + + portRESET_PRIVILEGE(); + portMEMORY_BARRIER(); + } + else + { + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + } + #else /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */ + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + #endif /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */ +} +/*-----------------------------------------------------------*/ + +__asm void xPortPendSVHandler( void ) +{ + extern uxCriticalNesting; + extern pxCurrentTCB; + extern vTaskSwitchContext; + +/* *INDENT-OFF* */ + PRESERVE8 + + ldr r3, =pxCurrentTCB /* r3 = &( pxCurrentTCB ). */ + ldr r2, [r3] /* r2 = pxCurrentTCB. */ + ldr r1, [r2] /* r1 = Location where the context should be saved. */ + + /*------------ Save Context. ----------- */ + mrs r3, control + mrs r0, psp + isb + + add r0, r0, #0x20 /* Move r0 to location where s0 is saved. */ + tst lr, #0x10 + ittt eq + vstmiaeq r1!, {s16-s31} /* Store s16-s31. */ + vldmiaeq r0, {s0-s16} /* Copy hardware saved FP context into s0-s16. */ + vstmiaeq r1!, {s0-s16} /* Store hardware saved FP context. */ + sub r0, r0, #0x20 /* Set r0 back to the location of hardware saved context. */ + + stmia r1!, {r3-r11, lr} /* Store CONTROL register, r4-r11 and LR. */ + ldmia r0, {r4-r11} /* Copy hardware saved context into r4-r11. */ + stmia r1!, {r0, r4-r11} /* Store original PSP (after hardware has saved context) and the hardware saved context. */ + str r1, [r2] /* Save the location from where the context should be restored as the first member of TCB. */ + + /*---------- Select next task. --------- */ + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY +#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) + cpsid i /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */ +#endif + msr basepri, r0 + dsb + isb +#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) + cpsie i /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */ +#endif + bl vTaskSwitchContext + mov r0, #0 + msr basepri, r0 + + /*------------ Program MPU. ------------ */ + ldr r3, =pxCurrentTCB /* r3 = &( pxCurrentTCB ). */ + ldr r2, [r3] /* r2 = pxCurrentTCB. */ + add r2, r2, #4 /* r2 = Second item in the TCB which is xMPUSettings. */ + + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r0, =0xe000ed94 /* MPU_CTRL register. */ + ldr r3, [r0] /* Read the value of MPU_CTRL. */ + bic r3, #1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */ + str r3, [r0] /* Disable MPU. */ + + ldr r0, =0xe000ed9c /* Region Base Address register. */ + ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */ + stmia r0, {r4-r11} /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */ + +#if ( configTOTAL_MPU_REGIONS == 16 ) + ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */ + stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 4 - 7]. */ + ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */ + stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */ +#endif /* configTOTAL_MPU_REGIONS == 16. */ + + ldr r0, =0xe000ed94 /* MPU_CTRL register. */ + ldr r3, [r0] /* Read the value of MPU_CTRL. */ + orr r3, #1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */ + str r3, [r0] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + + /*---------- Restore Context. ---------- */ + ldr r3, =pxCurrentTCB /* r3 = &( pxCurrentTCB ). */ + ldr r2, [r3] /* r2 = pxCurrentTCB. */ + ldr r1, [r2] /* r1 = Location of saved context in TCB. */ + + ldmdb r1!, {r0, r4-r11} /* r0 contains PSP after the hardware had saved context. r4-r11 contain hardware saved context. */ + msr psp, r0 + stmia r0!, {r4-r11} /* Copy the hardware saved context on the task stack. */ + ldmdb r1!, {r3-r11, lr} /* r3 contains CONTROL register. r4-r11 and LR restored. */ + msr control, r3 + + tst lr, #0x10 + ittt eq + vldmdbeq r1!, {s0-s16} /* s0-s16 contain hardware saved FP context. */ + vstmiaeq r0!, {s0-s16} /* Copy hardware saved FP context on the task stack. */ + vldmdbeq r1!, {s16-s31} /* Restore s16-s31. */ + + str r1, [r2] /* Save the location where the context should be saved next as the first member of TCB. */ + bx lr +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + uint32_t ulDummy; + + ulDummy = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy ); +} +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +__weak void vSetupTimerInterrupt( void ) +{ + /* Reset the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE; +} +/*-----------------------------------------------------------*/ + +__asm void vPortEnableVFP( void ) +{ +/* *INDENT-OFF* */ + PRESERVE8 + + ldr.w r0, =0xE000ED88 /* The FPU enable bits are in the CPACR. */ + ldr r1, [ r0 ] + + orr r1, r1, #( 0xf << 20 ) /* Enable CP10 and CP11 coprocessors, then save back. */ + str r1, [ r0 ] + bx r14 + nop +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +static void prvSetupMPU( void ) +{ + extern uint32_t __privileged_functions_start__; + extern uint32_t __privileged_functions_end__; + extern uint32_t __FLASH_segment_start__; + extern uint32_t __FLASH_segment_end__; + extern uint32_t __privileged_data_start__; + extern uint32_t __privileged_data_end__; + + /* The only permitted number of regions are 8 or 16. */ + configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) ); + + /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */ + configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ); + + /* Check the expected MPU is present. */ + if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ) + { + /* First setup the unprivileged flash for unprivileged read only access. */ + portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */ + ( portMPU_REGION_VALID ) | + ( portUNPRIVILEGED_FLASH_REGION ); + + portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) | + ( ( configTEX_S_C_B_FLASH & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) | + ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) | + ( portMPU_REGION_ENABLE ); + + /* Setup the privileged flash for privileged only access. This is where + * the kernel code is placed. */ + portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_functions_start__ ) | /* Base address. */ + ( portMPU_REGION_VALID ) | + ( portPRIVILEGED_FLASH_REGION ); + + portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) | + ( ( configTEX_S_C_B_FLASH & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) | + ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __privileged_functions_start__ ) ) | + ( portMPU_REGION_ENABLE ); + + /* Setup the privileged data RAM region. This is where the kernel data + * is placed. */ + portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */ + ( portMPU_REGION_VALID ) | + ( portPRIVILEGED_RAM_REGION ); + + portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ) | + ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) | + prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) | + ( portMPU_REGION_ENABLE ); + + /* By default allow everything to access the general peripherals. The + * system peripherals and registers are protected. */ + portMPU_REGION_BASE_ADDRESS_REG = ( portPERIPHERALS_START_ADDRESS ) | + ( portMPU_REGION_VALID ) | + ( portGENERAL_PERIPHERALS_REGION ); + + portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) | + ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) | + ( portMPU_REGION_ENABLE ); + + /* Enable the memory fault exception. */ + portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE; + + /* Enable the MPU with the background region configured. */ + portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE ); + } +} +/*-----------------------------------------------------------*/ + +static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) +{ + uint32_t ulRegionSize, ulReturnValue = 4; + + /* 32 is the smallest region size, 31 is the largest valid value for + * ulReturnValue. */ + for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) ) + { + if( ulActualSizeInBytes <= ulRegionSize ) + { + break; + } + else + { + ulReturnValue++; + } + } + + /* Shift the code by one before returning so it can be written directly + * into the the correct bit position of the attribute register. */ + return( ulReturnValue << 1UL ); +} +/*-----------------------------------------------------------*/ + +__asm BaseType_t xIsPrivileged( void ) +{ +/* *INDENT-OFF* */ + PRESERVE8 + + mrs r0, control /* r0 = CONTROL. */ + tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + ite ne + movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + bx lr /* Return. */ +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +__asm void vResetPrivilege( void ) +{ +/* *INDENT-OFF* */ + PRESERVE8 + + mrs r0, control /* r0 = CONTROL. */ + orrs r0, #1 /* r0 = r0 | 1. */ + msr control, r0 /* CONTROL = r0. */ + bx lr /* Return. */ +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +void vPortSwitchToUserMode( void ) +{ + /* Load the current task's MPU settings from its TCB. */ + xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); + + /* Mark the task as unprivileged. */ + xTaskMpuSettings->ulTaskFlags &= ( ~( portTASK_IS_PRIVILEGED_FLAG ) ); + + /* Lower the processor's privilege level. */ + vResetPrivilege(); +} +/*-----------------------------------------------------------*/ + +void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + configSTACK_DEPTH_TYPE uxStackDepth ) +{ + extern uint32_t __SRAM_segment_start__; + extern uint32_t __SRAM_segment_end__; + extern uint32_t __privileged_data_start__; + extern uint32_t __privileged_data_end__; + + + int32_t lIndex; + uint32_t ul; + + if( xRegions == NULL ) + { + /* No MPU regions are specified so allow access to all RAM. */ + xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress = + ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */ + ( portMPU_REGION_VALID ) | + ( portSTACK_REGION ); /* Region number. */ + + xMPUSettings->xRegion[ 0 ].ulRegionAttribute = + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ) | + ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) | + ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) | + ( portMPU_REGION_ENABLE ); + + xMPUSettings->xRegionSettings[ 0 ].ulRegionStartAddress = ( uint32_t ) __SRAM_segment_start__; + xMPUSettings->xRegionSettings[ 0 ].ulRegionEndAddress = ( uint32_t ) __SRAM_segment_end__; + xMPUSettings->xRegionSettings[ 0 ].ulRegionPermissions = ( tskMPU_READ_PERMISSION | + tskMPU_WRITE_PERMISSION ); + + /* Invalidate user configurable regions. */ + for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ ) + { + xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID ); + xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL; + xMPUSettings->xRegionSettings[ ul ].ulRegionStartAddress = 0UL; + xMPUSettings->xRegionSettings[ ul ].ulRegionEndAddress = 0UL; + xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = 0UL; + } + } + else + { + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that the + * stack region has already been configured. */ + if( uxStackDepth > 0 ) + { + /* Define the region that allows access to the stack. */ + xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress = + ( ( uint32_t ) pxBottomOfStack ) | + ( portMPU_REGION_VALID ) | + ( portSTACK_REGION ); /* Region number. */ + + xMPUSettings->xRegion[ 0 ].ulRegionAttribute = + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ) | + ( prvGetMPURegionSizeSetting( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) ) | + ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) | + ( portMPU_REGION_ENABLE ); + + xMPUSettings->xRegionSettings[ 0 ].ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; + xMPUSettings->xRegionSettings[ 0 ].ulRegionEndAddress = ( uint32_t ) ( ( uint32_t ) ( pxBottomOfStack ) + + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1UL ); + xMPUSettings->xRegionSettings[ 0 ].ulRegionPermissions = ( tskMPU_READ_PERMISSION | + tskMPU_WRITE_PERMISSION ); + } + + lIndex = 0; + + for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ ) + { + if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL ) + { + /* Translate the generic region definition contained in + * xRegions into the CM4 specific MPU settings that are then + * stored in xMPUSettings. */ + xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = + ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) | + ( portMPU_REGION_VALID ) | + ( ul - 1UL ); /* Region number. */ + + xMPUSettings->xRegion[ ul ].ulRegionAttribute = + ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) | + ( xRegions[ lIndex ].ulParameters ) | + ( portMPU_REGION_ENABLE ); + + xMPUSettings->xRegionSettings[ ul ].ulRegionStartAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress; + xMPUSettings->xRegionSettings[ ul ].ulRegionEndAddress = ( uint32_t ) ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1UL ); + xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = 0UL; + + if( ( ( xRegions[ lIndex ].ulParameters & portMPU_REGION_READ_ONLY ) == portMPU_REGION_READ_ONLY ) || + ( ( xRegions[ lIndex ].ulParameters & portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ) == portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ) ) + { + xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = tskMPU_READ_PERMISSION; + } + + if( ( xRegions[ lIndex ].ulParameters & portMPU_REGION_READ_WRITE ) == portMPU_REGION_READ_WRITE ) + { + xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION ); + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID ); + xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL; + xMPUSettings->xRegionSettings[ ul ].ulRegionStartAddress = 0UL; + xMPUSettings->xRegionSettings[ ul ].ulRegionEndAddress = 0UL; + xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = 0UL; + } + + lIndex++; + } + } +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, + uint32_t ulBufferLength, + uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */ + + { + uint32_t i, ulBufferStartAddress, ulBufferEndAddress; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE ) + { + ulBufferStartAddress = ( uint32_t ) pvBuffer; + ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL ); + + for( i = 0; i < portTOTAL_NUM_REGIONS_IN_TCB; i++ ) + { + if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress, + xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress, + xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) && + portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress, + xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress, + xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) && + portIS_AUTHORIZED( ulAccessRequested, xTaskMpuSettings->xRegionSettings[ i ].ulRegionPermissions ) ) + { + xAccessGranted = pdTRUE; + break; + } + } + } + } + + return xAccessGranted; + } + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ + +__asm uint32_t prvPortGetIPSR( void ) +{ +/* *INDENT-OFF* */ + PRESERVE8 + + mrs r0, ipsr + bx r14 +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + ulCurrentInterrupt = prvPortGetIPSR(); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* configASSERT_DEFINED */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortGrantAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] |= ( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + + void vPortRevokeAccessToKernelObject( TaskHandle_t xInternalTaskHandle, + int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + xMPU_SETTINGS * xTaskMpuSettings; + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + xTaskMpuSettings = xTaskGetMPUSettings( xInternalTaskHandle ); + + xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] &= ~( 1U << ulAccessControlListEntryBit ); + } + +#endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + uint32_t ulAccessControlListEntryIndex, ulAccessControlListEntryBit; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings; + + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else + { + xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + ulAccessControlListEntryIndex = ( ( uint32_t ) lInternalIndexOfKernelObject / portACL_ENTRY_SIZE_BITS ); + ulAccessControlListEntryBit = ( ( uint32_t ) lInternalIndexOfKernelObject % portACL_ENTRY_SIZE_BITS ); + + if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( ( xTaskMpuSettings->ulAccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 ) + { + xAccessGranted = pdTRUE; + } + } + } + + return xAccessGranted; + } + + #else /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + + BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) /* PRIVILEGED_FUNCTION */ + { + ( void ) lInternalIndexOfKernelObject; + + /* If Access Control List feature is not used, all the tasks have + * access to all the kernel objects. */ + return pdTRUE; + } + + #endif /* #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) */ + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ +/*-----------------------------------------------------------*/ diff --git a/portable/RVDS/ARM_CM4_MPU/portmacro.h b/portable/RVDS/ARM_CM4_MPU/portmacro.h new file mode 100644 index 000000000..8e682ba74 --- /dev/null +++ b/portable/RVDS/ARM_CM4_MPU/portmacro.h @@ -0,0 +1,514 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error "configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width." +#endif + +/* Errata 837070 workaround must be enabled on Cortex-M7 r0p0 + * and r0p1 cores. */ +#ifndef configENABLE_ERRATA_837070_WORKAROUND + #define configENABLE_ERRATA_837070_WORKAROUND 0 +#endif +/*-----------------------------------------------------------*/ + +/* MPU specific constants. */ +#define portUSING_MPU_WRAPPERS 1 +#define portPRIVILEGE_BIT ( 0x80000000UL ) + +#define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL ) +#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL ) +#define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL ) +#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL ) +#define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ( 0x02UL << 24UL ) +#define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL ) +#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL ) + +/* Location of the TEX,S,C,B bits in the MPU Region Attribute and Size + * Register (RASR). */ +#define portMPU_RASR_TEX_S_C_B_LOCATION ( 16UL ) +#define portMPU_RASR_TEX_S_C_B_MASK ( 0x3FUL ) + +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ +#ifndef configTOTAL_MPU_REGIONS + /* Define to 8 for backward compatibility. */ + #define configTOTAL_MPU_REGIONS ( 8UL ) +#endif + +/* + * The TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits define the + * memory type, and where necessary the cacheable and shareable properties + * of the memory region. + * + * The TEX, C, and B bits together indicate the memory type of the region, + * and: + * - For Normal memory, the cacheable properties of the region. + * - For Device memory, whether the region is shareable. + * + * For Normal memory regions, the S bit indicates whether the region is + * shareable. For Strongly-ordered and Device memory, the S bit is ignored. + * + * See the following two tables for setting TEX, S, C and B bits for + * unprivileged flash, privileged flash and privileged RAM regions. + * + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | TEX | C | B | Memory type | Description or Normal region cacheability | Shareable? | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 000 | 0 | 0 | Strongly-ordered | Strongly ordered | Shareable | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 000 | 0 | 1 | Device | Shared device | Shareable | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 000 | 1 | 0 | Normal | Outer and inner write-through; no write allocate | S bit | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 000 | 1 | 1 | Normal | Outer and inner write-back; no write allocate | S bit | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 001 | 0 | 0 | Normal | Outer and inner Non-cacheable | S bit | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 001 | 0 | 1 | Reserved | Reserved | Reserved | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 001 | 1 | 0 | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 001 | 1 | 1 | Normal | Outer and inner write-back; write and read allocate | S bit | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 010 | 0 | 0 | Device | Non-shared device | Not shareable | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 010 | 0 | 1 | Reserved | Reserved | Reserved | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 010 | 1 | X | Reserved | Reserved | Reserved | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 011 | X | X | Reserved | Reserved | Reserved | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | 1BB | A | A | Normal | Cached memory, with AA and BB indicating the inner and | Reserved | + | | | | | outer cacheability rules that must be exported on the | | + | | | | | bus. See the table below for the cacheability policy | | + | | | | | encoding. memory, BB=Outer policy, AA=Inner policy. | | + +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+ + | + +-----------------------------------------+----------------------------------------+ + | AA or BB subfield of {TEX,C,B} encoding | Cacheability policy | + +-----------------------------------------+----------------------------------------+ + | 00 | Non-cacheable | + +-----------------------------------------+----------------------------------------+ + | 01 | Write-back, write and read allocate | + +-----------------------------------------+----------------------------------------+ + | 10 | Write-through, no write allocate | + +-----------------------------------------+----------------------------------------+ + | 11 | Write-back, no write allocate | + +-----------------------------------------+----------------------------------------+ + */ + +/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for Flash + * region. */ +#ifndef configTEX_S_C_B_FLASH + /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */ + #define configTEX_S_C_B_FLASH ( 0x07UL ) +#endif + +/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for SRAM + * region. */ +#ifndef configTEX_S_C_B_SRAM + /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */ + #define configTEX_S_C_B_SRAM ( 0x07UL ) +#endif + +#define portSTACK_REGION ( configTOTAL_MPU_REGIONS - 5UL ) +#define portGENERAL_PERIPHERALS_REGION ( configTOTAL_MPU_REGIONS - 4UL ) +#define portUNPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 3UL ) +#define portPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 2UL ) +#define portPRIVILEGED_RAM_REGION ( configTOTAL_MPU_REGIONS - 1UL ) +#define portFIRST_CONFIGURABLE_REGION ( 0UL ) +#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 6UL ) +#define portNUM_CONFIGURABLE_REGIONS ( configTOTAL_MPU_REGIONS - 5UL ) +#define portTOTAL_NUM_REGIONS_IN_TCB ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus 1 to create space for the stack region. */ + +typedef struct MPU_REGION_REGISTERS +{ + uint32_t ulRegionBaseAddress; + uint32_t ulRegionAttribute; +} xMPU_REGION_REGISTERS; + +typedef struct MPU_REGION_SETTINGS +{ + uint32_t ulRegionStartAddress; + uint32_t ulRegionEndAddress; + uint32_t ulRegionPermissions; +} xMPU_REGION_SETTINGS; + +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + + #ifndef configSYSTEM_CALL_STACK_SIZE + #error "configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2." + #endif + + typedef struct SYSTEM_CALL_STACK_INFO + { + uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; + uint32_t * pulSystemCallStack; + uint32_t * pulTaskStack; + uint32_t ulLinkRegisterAtSystemCallEntry; + } xSYSTEM_CALL_STACK_INFO; + +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ + +/* + * +---------+---------------+-----------------+-----------------+-----+ + * | s16-s31 | s0-s15, FPSCR | CONTROL, r4-r11 | PSP, r0-r3, r12 | | + * | | | EXC_RETURN | LR, PC, xPSR | | + * +---------+---------------+-----------------+-----------------+-----+ + * + * <--------><---------------><----------------><----------------><----> + * 16 17 10 9 1 + */ +#define MAX_CONTEXT_SIZE ( 53 ) + +/* Size of an Access Control List (ACL) entry in bits. */ +#define portACL_ENTRY_SIZE_BITS ( 32U ) + +/* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ +#define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) +#define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) + +typedef struct MPU_SETTINGS +{ + xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS_IN_TCB ]; + xMPU_REGION_SETTINGS xRegionSettings[ portTOTAL_NUM_REGIONS_IN_TCB ]; + uint32_t ulContext[ MAX_CONTEXT_SIZE ]; + uint32_t ulTaskFlags; + + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) + xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo; + #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) + uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ]; + #endif + #endif +} xMPU_SETTINGS; + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 + +/* Constants used with memory barrier intrinsics. */ +#define portSY_FULL_READ_WRITE ( 15 ) + +/*-----------------------------------------------------------*/ + +/* SVC numbers for various services. */ +#define portSVC_START_SCHEDULER 100 +#define portSVC_YIELD 101 +#define portSVC_RAISE_PRIVILEGE 102 +#define portSVC_SYSTEM_CALL_EXIT 103 + +/* Scheduler utilities. */ + +#define portYIELD() __asm { SVC portSVC_YIELD } +#define portYIELD_WITHIN_API() \ + { \ + /* Set a PendSV to request a context switch. */ \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + \ + /* Barriers are normally not required but do ensure the code is completely \ + * within the specified behaviour for the architecture. */ \ + __dsb( portSY_FULL_READ_WRITE ); \ + __isb( portSY_FULL_READ_WRITE ); \ + } +/*-----------------------------------------------------------*/ + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() +#define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x ) + +/*-----------------------------------------------------------*/ + +/* Architecture specific optimisations. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice." + #endif + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not necessary for to use this port. They are defined so the common demo files + * (which build with all the ports) will build. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif + +/* portNOP() is not required by this port. */ +#define portNOP() + +#define portINLINE __inline + +#ifndef portFORCE_INLINE + #define portFORCE_INLINE __forceinline +#endif +/*-----------------------------------------------------------*/ + +extern BaseType_t xIsPrivileged( void ); +extern void vResetPrivilege( void ); +extern void vPortSwitchToUserMode( void ); + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +#define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. + */ +#define portRAISE_PRIVILEGE() __asm { svc portSVC_RAISE_PRIVILEGE } + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ +#define portRESET_PRIVILEGE() vResetPrivilege() + +/** + * @brief Make a task unprivileged. + * + * It must be called from privileged tasks only. Calling it from unprivileged + * task will result in a memory protection fault. + */ +#define portSWITCH_TO_USER_MODE() vPortSwitchToUserMode() +/*-----------------------------------------------------------*/ + +extern BaseType_t xPortIsTaskPrivileged( void ); + +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ +#define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() +/*-----------------------------------------------------------*/ + +static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI ) +{ + __asm + { + /* Barrier instructions are not used as this function is only used to + * lower the BASEPRI value. */ +/* *INDENT-OFF* */ + msr basepri, ulBASEPRI +/* *INDENT-ON* */ + } +} +/*-----------------------------------------------------------*/ + +static portFORCE_INLINE void vPortRaiseBASEPRI( void ) +{ + uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY; + + __asm + { + /* Set BASEPRI to the max syscall priority to effect a critical + * section. */ +/* *INDENT-OFF* */ + #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) + cpsid i + #endif + msr basepri, ulNewBASEPRI + dsb + isb + #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) + cpsie i + #endif +/* *INDENT-ON* */ + } +} +/*-----------------------------------------------------------*/ + +static portFORCE_INLINE void vPortClearBASEPRIFromISR( void ) +{ + __asm + { + /* Set BASEPRI to 0 so no interrupts are masked. This function is only + * used to lower the mask in an interrupt, so memory barriers are not + * used. */ +/* *INDENT-OFF* */ + msr basepri, # 0 +/* *INDENT-ON* */ + } +} +/*-----------------------------------------------------------*/ + +static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void ) +{ + uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY; + + __asm + { + /* Set BASEPRI to the max syscall priority to effect a critical + * section. */ +/* *INDENT-OFF* */ + mrs ulReturn, basepri + #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) + cpsid i + #endif + msr basepri, ulNewBASEPRI + dsb + isb + #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) + cpsie i + #endif +/* *INDENT-ON* */ + } + + return ulReturn; +} +/*-----------------------------------------------------------*/ + +static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + __asm + { + mrs ulCurrentInterrupt, ipsr + } + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +#ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY + #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. www.FreeRTOS.org/FreeRTOS-V10.3.x.html" + #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0 +#endif +/*-----------------------------------------------------------*/ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/RVDS/ARM_CM7/ReadMe.txt b/portable/RVDS/ARM_CM7/ReadMe.txt new file mode 100644 index 000000000..d8e94ac4b --- /dev/null +++ b/portable/RVDS/ARM_CM7/ReadMe.txt @@ -0,0 +1,18 @@ +There are two options for running FreeRTOS on ARM Cortex-M7 microcontrollers. +The best option depends on the revision of the ARM Cortex-M7 core in use. The +revision is specified by an 'r' number, and a 'p' number, so will look something +like 'r0p1'. Check the documentation for the microcontroller in use to find the +revision of the Cortex-M7 core used in that microcontroller. If in doubt, use +the FreeRTOS port provided specifically for r0p1 revisions, as that can be used +with all core revisions. + +The first option is to use the ARM Cortex-M4F port, and the second option is to +use the Cortex-M7 r0p1 port - the latter containing a minor errata workaround. + +If the revision of the ARM Cortex-M7 core is not r0p1 then either option can be +used, but it is recommended to use the FreeRTOS ARM Cortex-M4F port located in +the /FreeRTOS/Source/portable/RVDS/ARM_CM4F directory. + +If the revision of the ARM Cortex-M7 core is r0p1 then use the FreeRTOS ARM +Cortex-M7 r0p1 port located in the /FreeRTOS/Source/portable/RVDS/ARM_CM7/r0p1 +directory. diff --git a/portable/RVDS/ARM_CM7/r0p1/port.c b/portable/RVDS/ARM_CM7/r0p1/port.c new file mode 100644 index 000000000..33fa80266 --- /dev/null +++ b/portable/RVDS/ARM_CM7/r0p1/port.c @@ -0,0 +1,875 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ARM CM7 port. +*----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#ifndef __TARGET_FPU_VFP + #error This port can only be used when the project options are configured to enable hardware floating point support. +#endif + +#if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 + #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ +#endif + +/* The __weak attribute does not work as you might expect with the Keil tools + * so the configOVERRIDE_DEFAULT_TICK_CONFIGURATION constant must be set to 1 if + * the application writer wants to provide their own implementation of + * vPortSetupTimerInterrupt(). Ensure configOVERRIDE_DEFAULT_TICK_CONFIGURATION + * is defined. */ +#ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION + #define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 0 +#endif + +/* Constants required to manipulate the core. Registers first... */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +/* ...then bits in the registers. */ +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL ) +#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) + +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL ) +#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL ) + +/* Constants required to check the validity of an interrupt priority. */ +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) + +/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */ +#define portVECTACTIVE_MASK ( 0xFFUL ) + +/* Constants required to manipulate the VFP. */ +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */ +#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) +#define portINITIAL_EXC_RETURN ( 0xfffffffd ) + +/* The systick is a 24-bit counter. */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/* A fiddle factor to estimate the number of SysTick counts that would have + * occurred while the SysTick counter is stopped during tickless idle + * calculations. */ +#define portMISSED_COUNTS_FACTOR ( 94UL ) + +/* For strict compliance with the Cortex-M spec the task start address should + * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */ +#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL ) + +/* Let the user override the default SysTick clock rate. If defined by the + * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the + * configuration register. */ +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ ) + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT ) +#else + /* Select the option to clock SysTick not at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 ) +#endif + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ); + +/* + * Exception handlers. + */ +void xPortPendSVHandler( void ); +void xPortSysTickHandler( void ); +void vPortSVCHandler( void ); + +/* + * Start first task is a separate function so it can be tested in isolation. + */ +static void prvStartFirstTask( void ); + +/* + * Functions defined in portasm.s to enable the VFP. + */ +static void prvEnableVFP( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* Each task maintains its own interrupt status in the critical nesting + * variable. */ +static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +/* + * The number of SysTick increments that make up one tick period. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulTimerCountsForOneTick = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * The maximum number of tick periods that can be suppressed is limited by the + * 24 bit resolution of the SysTick timer. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t xMaximumPossibleSuppressedTicks = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Compensate for the CPU cycles that pass while the SysTick is stopped (low + * power functionality only. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( configASSERT_DEFINED == 1 ) + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; +#endif /* configASSERT_DEFINED */ + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + + /* Offset added to account for the way the MCU uses the stack on entry/exit + * of interrupts, and to ensure alignment. */ + pxTopOfStack--; + + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */ + + /* Save code space by skipping register initialisation. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + + /* A save method is being used that requires each task to maintain its + * own exec return value. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; + + pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ + configASSERT( uxCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } +} +/*-----------------------------------------------------------*/ + +__asm void vPortSVCHandler( void ) +{ +/* *INDENT-OFF* */ + PRESERVE8 + + /* Get the location of the current TCB. */ + ldr r3, =pxCurrentTCB + ldr r1, [ r3 ] + ldr r0, [ r1 ] + /* Pop the core registers. */ + ldmia r0!, { r4-r11, r14 } + msr psp, r0 + isb + mov r0, #0 + msr basepri, r0 + bx r14 +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +__asm void prvStartFirstTask( void ) +{ +/* *INDENT-OFF* */ + PRESERVE8 + + /* Use the NVIC offset register to locate the stack. */ + ldr r0, =0xE000ED08 + ldr r0, [ r0 ] + ldr r0, [ r0 ] + /* Set the msp back to the start of the stack. */ + msr msp, r0 + + /* Clear the bit that indicates the FPU is in use in case the FPU was used + * before the scheduler was started - which would otherwise result in the + * unnecessary leaving of space in the SVC stack for lazy saving of FPU + * registers. */ + mov r0, #0 + msr control, r0 + /* Globally enable interrupts. */ + cpsie i + cpsie f + dsb + isb + /* Call SVC to start the first task. */ + svc 0 + nop + nop +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +__asm void prvEnableVFP( void ) +{ +/* *INDENT-OFF* */ + PRESERVE8 + + /* The FPU enable bits are in the CPACR. */ + ldr.w r0, =0xE000ED88 + ldr r1, [ r0 ] + + /* Enable CP10 and CP11 coprocessors, then save back. */ + orr r1, r1, #( 0xf << 20 ) + str r1, [ r0 ] + bx r14 + nop +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + #if ( configASSERT_DEFINED == 1 ) + { + volatile uint8_t ucOriginalPriority; + volatile uint32_t ulImplementedPrioBits = 0; + volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * Save the interrupt priority value that is about to be clobbered. */ + ucOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to all + * possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Check that the maximum system call priority is nonzero after + * accounting for the number of priority bits supported by the + * hardware. A priority of 0 is invalid because setting the BASEPRI + * register to 0 unmasks all interrupts, and interrupts with priority 0 + * cannot be masked using BASEPRI. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ucMaxSysCallPriority ); + + /* Check that the bits not implemented in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulImplementedPrioBits++; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + if( ulImplementedPrioBits == 8 ) + { + /* When the hardware implements 8 priority bits, there is no way for + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); + ulMaxPRIGROUPValue = 0; + } + else + { + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; + } + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + + /* Restore the clobbered interrupt priority register to its original + * value. */ + *pucFirstUserPriorityRegister = ucOriginalPriority; + } + #endif /* configASSERT_DEFINED */ + + /* Make PendSV and SysTick the lowest priority interrupts. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + /* Ensure the VFP is enabled - it should be anyway. */ + prvEnableVFP(); + + /* Lazy save always. */ + *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; + + /* Start the first task. */ + prvStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ + if( uxCriticalNesting == 1 ) + { + configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +__asm void xPortPendSVHandler( void ) +{ + extern uxCriticalNesting; + extern pxCurrentTCB; + extern vTaskSwitchContext; + +/* *INDENT-OFF* */ + PRESERVE8 + + mrs r0, psp + isb + /* Get the location of the current TCB. */ + ldr r3, =pxCurrentTCB + ldr r2, [ r3 ] + + /* Is the task using the FPU context? If so, push high vfp registers. */ + tst r14, #0x10 + it eq + vstmdbeq r0!, {s16-s31} + + /* Save the core registers. */ + stmdb r0!, {r4-r11, r14 } + + /* Save the new top of stack into the first member of the TCB. */ + str r0, [ r2 ] + + stmdb sp!, { r0, r3 } + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + cpsid i + msr basepri, r0 + dsb + isb + cpsie i + bl vTaskSwitchContext + mov r0, #0 + msr basepri, r0 + ldmia sp!, { r0, r3 } + + /* The first item in pxCurrentTCB is the task top of stack. */ + ldr r1, [ r3 ] + ldr r0, [ r1 ] + + /* Pop the core registers. */ + ldmia r0!, { r4-r11, r14 } + + /* Is the task using the FPU context? If so, pop the high vfp registers + * too. */ + tst r14, #0x10 + it eq + vldmiaeq r0!, { s16-s31 } + + msr psp, r0 + isb + #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */ + #if WORKAROUND_PMU_CM001 == 1 + push { r14 } + pop { pc } + nop + #endif + #endif + + bx r14 +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + /* The SysTick runs at the lowest interrupt priority, so when this interrupt + * executes all interrupts must be unmasked. There is therefore no need to + * save and then restore the interrupt mask value as its value is already + * known - therefore the slightly faster vPortRaiseBASEPRI() function is used + * in place of portSET_INTERRUPT_MASK_FROM_ISR(). */ + vPortRaiseBASEPRI(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + + /* A context switch is required. Context switching is performed in + * the PendSV interrupt. Pend the PendSV interrupt. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + + vPortClearBASEPRIFromISR(); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __disable_irq(); + __dsb( portSY_FULL_READ_WRITE ); + __isb( portSY_FULL_READ_WRITE ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Re-enable interrupts - see comments above the __disable_irq() + * call above. */ + __enable_irq(); + } + else + { + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Use the SysTick current-value register to determine the number of + * SysTick decrements remaining until the next tick interrupt. If the + * current-value register is zero, then there are actually + * ulTimerCountsForOneTick decrements remaining, not zero, because the + * SysTick requests the interrupt when decrementing from 1 to 0. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulTimerCountsForOneTick; + } + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code normally executes part + * way through the first tick period. But if the SysTick IRQ is now + * pending, then clear the IRQ, suppressing the first tick, and correct + * the reload value to reflect that the second tick period is already + * underway. The expected idle time is always at least two ticks. */ + ulReloadValue = ulSysTickDecrementsLeft + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ( portNVIC_INT_CTRL_REG & portNVIC_PEND_SYSTICK_SET_BIT ) != 0 ) + { + portNVIC_INT_CTRL_REG = portNVIC_PEND_SYSTICK_CLEAR_BIT; + ulReloadValue -= ulTimerCountsForOneTick; + } + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __dsb( portSY_FULL_READ_WRITE ); + __wfi(); + __isb( portSY_FULL_READ_WRITE ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. See comments above + * the __disable_irq() call above. */ + __enable_irq(); + __dsb( portSY_FULL_READ_WRITE ); + __isb( portSY_FULL_READ_WRITE ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __disable_irq(); + __dsb( portSY_FULL_READ_WRITE ); + __isb( portSY_FULL_READ_WRITE ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT ); + + /* Determine whether the SysTick has already counted to zero. */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt ended the sleep (or is now pending), and + * a new tick period has started. Reset portNVIC_SYSTICK_LOAD_REG + * with whatever remains of the new tick period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long or because the SysTick current-value register + * is zero. */ + if( ( ulCalculatedLoadValue <= ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. */ + + /* Use the SysTick current-value register to determine the + * number of SysTick decrements remaining until the expected idle + * time would have ended. */ + ulSysTickDecrementsLeft = portNVIC_SYSTICK_CURRENT_VALUE_REG; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG != portNVIC_SYSTICK_CLK_BIT ) + { + /* If the SysTick is not using the core clock, the current- + * value register might still be zero here. In that case, the + * SysTick didn't load from the reload register, and there are + * ulReloadValue decrements remaining in the expected idle + * time, not zero. */ + if( ulSysTickDecrementsLeft == 0 ) + { + ulSysTickDecrementsLeft = ulReloadValue; + } + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - ulSysTickDecrementsLeft; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG again, + * then set portNVIC_SYSTICK_LOAD_REG back to its standard value. If + * the SysTick is not using the core clock, temporarily configure it to + * use the core clock. This configuration forces the SysTick to load + * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next + * cycle of the other clock. Then portNVIC_SYSTICK_LOAD_REG is ready + * to receive the standard value immediately. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + #if ( portNVIC_SYSTICK_CLK_BIT_CONFIG == portNVIC_SYSTICK_CLK_BIT ) + { + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + } + #else + { + /* The temporary usage of the core clock has served its purpose, + * as described above. Resume usage of the other clock. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT; + + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + /* The partial tick period already ended. Be sure the SysTick + * counts it only once. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0; + } + + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; + } + #endif /* portNVIC_SYSTICK_CLK_BIT_CONFIG */ + + /* Step the tick to account for any tick periods that elapsed. */ + vTaskStepTick( ulCompleteTickPeriods ); + + /* Exit with interrupts enabled. */ + __enable_irq(); + } + } + +#endif /* #if configUSE_TICKLESS_IDLE */ + +/*-----------------------------------------------------------*/ + +/* + * Setup the SysTick timer to generate the tick interrupts at the required + * frequency. + */ +#if ( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 ) + + __weak void vPortSetupTimerInterrupt( void ) + { + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and clear the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); + } + +#endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */ +/*-----------------------------------------------------------*/ + +__asm uint32_t vPortGetIPSR( void ) +{ +/* *INDENT-OFF* */ + PRESERVE8 + + mrs r0, ipsr + bx r14 +/* *INDENT-ON* */ +} +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + ulCurrentInterrupt = vPortGetIPSR(); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* configASSERT_DEFINED */ diff --git a/portable/RVDS/ARM_CM7/r0p1/portmacro.h b/portable/RVDS/ARM_CM7/r0p1/portmacro.h new file mode 100644 index 000000000..b36b427d9 --- /dev/null +++ b/portable/RVDS/ARM_CM7/r0p1/portmacro.h @@ -0,0 +1,283 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 + +/* Constants used with memory barrier intrinsics. */ +#define portSY_FULL_READ_WRITE ( 15 ) + +/*-----------------------------------------------------------*/ + +/* Scheduler utilities. */ +#define portYIELD() \ + { \ + /* Set a PendSV to request a context switch. */ \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + \ + /* Barriers are normally not required but do ensure the code is completely \ + * within the specified behaviour for the architecture. */ \ + __dsb( portSY_FULL_READ_WRITE ); \ + __isb( portSY_FULL_READ_WRITE ); \ + } +/*-----------------------------------------------------------*/ + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portYIELD(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() +#define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x ) + +/*-----------------------------------------------------------*/ + +/* Tickless idle/low power functionality. */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif +/*-----------------------------------------------------------*/ + +/* Port specific optimisations. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) ) + +#endif /* taskRECORD_READY_PRIORITY */ +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not necessary for to use this port. They are defined so the common demo files + * (which build with all the ports) will build. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif + +/* portNOP() is not required by this port. */ +#define portNOP() + +#define portINLINE __inline + +#ifndef portFORCE_INLINE + #define portFORCE_INLINE __forceinline +#endif + +/*-----------------------------------------------------------*/ + +static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI ) +{ + __asm + { + /* Barrier instructions are not used as this function is only used to + * lower the BASEPRI value. */ +/* *INDENT-OFF* */ + msr basepri, ulBASEPRI +/* *INDENT-ON* */ + } +} +/*-----------------------------------------------------------*/ + +static portFORCE_INLINE void vPortRaiseBASEPRI( void ) +{ + uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY; + + __asm + { + /* Set BASEPRI to the max syscall priority to effect a critical + * section. */ +/* *INDENT-OFF* */ + cpsid i + msr basepri, ulNewBASEPRI + dsb + isb + cpsie i +/* *INDENT-ON* */ + } +} +/*-----------------------------------------------------------*/ + +static portFORCE_INLINE void vPortClearBASEPRIFromISR( void ) +{ + __asm + { + /* Set BASEPRI to 0 so no interrupts are masked. This function is only + * used to lower the mask in an interrupt, so memory barriers are not + * used. */ +/* *INDENT-OFF* */ + msr basepri, # 0 +/* *INDENT-ON* */ + } +} +/*-----------------------------------------------------------*/ + +static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void ) +{ + uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY; + + __asm + { + /* Set BASEPRI to the max syscall priority to effect a critical + * section. */ +/* *INDENT-OFF* */ + mrs ulReturn, basepri + cpsid i + msr basepri, ulNewBASEPRI + dsb + isb + cpsie i +/* *INDENT-ON* */ + } + + return ulReturn; +} +/*-----------------------------------------------------------*/ + +static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + __asm + { +/* *INDENT-OFF* */ + mrs ulCurrentInterrupt, ipsr +/* *INDENT-ON* */ + } + + if( ulCurrentInterrupt == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/Renesas/RX100/port.c b/portable/Renesas/RX100/port.c new file mode 100644 index 000000000..a22da66cf --- /dev/null +++ b/portable/Renesas/RX100/port.c @@ -0,0 +1,646 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the RX100 port. + *----------------------------------------------------------*/ + +/* Standard C includes. */ +#include "limits.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Library includes. */ +#include "string.h" + +/* Hardware specifics. */ +#include "iodefine.h" + +/*-----------------------------------------------------------*/ + +/* Tasks should start with interrupts enabled and in Supervisor mode, therefore +PSW is set with U and I set, and PM and IPL clear. */ +#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) + +/* The peripheral clock is divided by this value before being supplying the +CMT. */ +#if ( configUSE_TICKLESS_IDLE == 0 ) + /* If tickless idle is not used then the divisor can be fixed. */ + #define portCLOCK_DIVISOR 8UL +#elif ( configPERIPHERAL_CLOCK_HZ >= 12000000 ) + #define portCLOCK_DIVISOR 512UL +#elif ( configPERIPHERAL_CLOCK_HZ >= 6000000 ) + #define portCLOCK_DIVISOR 128UL +#elif ( configPERIPHERAL_CLOCK_HZ >= 1000000 ) + #define portCLOCK_DIVISOR 32UL +#else + #define portCLOCK_DIVISOR 8UL +#endif + + +/* Keys required to lock and unlock access to certain system registers +respectively. */ +#define portUNLOCK_KEY 0xA50B +#define portLOCK_KEY 0xA500 + +/*-----------------------------------------------------------*/ + +/* The following lines are to ensure vSoftwareInterruptEntry can be referenced, + and therefore installed in the vector table, when the FreeRTOS code is built +as a library. */ +extern BaseType_t vSoftwareInterruptEntry; +const BaseType_t * p_vSoftwareInterruptEntry = &vSoftwareInterruptEntry; + +/*-----------------------------------------------------------*/ + +/* + * Function to start the first task executing - written in asm code as direct + * access to registers is required. + */ +static void prvStartFirstTask( void ); + +/* + * Software interrupt handler. Performs the actual context switch (saving and + * restoring of registers). Written in asm code as direct register access is + * required. + */ +static void prvYieldHandler( void ); + +/* + * The entry point for the software interrupt handler. This is the function + * that calls the inline asm function prvYieldHandler(). It is installed in + * the vector table, but the code that installs it is in prvYieldHandler rather + * than using a #pragma. + */ +void vSoftwareInterruptISR( void ); + +/* + * Sets up the periodic ISR used for the RTOS tick using the CMT. + * The application writer can define configSETUP_TICK_INTERRUPT() (in + * FreeRTOSConfig.h) such that their own tick interrupt configuration is used + * in place of prvSetupTimerInterrupt(). + */ +static void prvSetupTimerInterrupt( void ); +#ifndef configSETUP_TICK_INTERRUPT + /* The user has not provided their own tick interrupt configuration so use + the definition in this file (which uses the interval timer). */ + #define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt() +#endif /* configSETUP_TICK_INTERRUPT */ + +/* + * Called after the sleep mode registers have been configured, prvSleep() + * executes the pre and post sleep macros, and actually calls the wait + * instruction. + */ +#if configUSE_TICKLESS_IDLE == 1 + static void prvSleep( TickType_t xExpectedIdleTime ); +#endif /* configUSE_TICKLESS_IDLE */ + +/*-----------------------------------------------------------*/ + +/* These is accessed by the inline assembler functions. */ +extern void *pxCurrentTCB; +extern void vTaskSwitchContext( void ); + +/*-----------------------------------------------------------*/ + +/* Calculate how many clock increments make up a single tick period. */ +static const uint32_t ulMatchValueForOneTick = ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ ); + +#if configUSE_TICKLESS_IDLE == 1 + + /* Holds the maximum number of ticks that can be suppressed - which is + basically how far into the future an interrupt can be generated. Set + during initialisation. This is the maximum possible value that the + compare match register can hold divided by ulMatchValueForOneTick. */ + static const TickType_t xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ ); + + /* Flag set from the tick interrupt to allow the sleep processing to know if + sleep mode was exited because of a tick interrupt, or an interrupt + generated by something else. */ + static volatile uint32_t ulTickFlag = pdFALSE; + + /* The CMT counter is stopped temporarily each time it is re-programmed. + The following constant offsets the CMT counter match value by the number of + CMT counts that would typically be missed while the counter was stopped to + compensate for the lost time. The large difference between the divided CMT + clock and the CPU clock means it is likely ulStoppedTimerCompensation will + equal zero - and be optimised away. */ + static const uint32_t ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) ); + +#endif + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* Offset to end up on 8 byte boundary. */ + pxTopOfStack--; + + /* R0 is not included as it is the stack pointer. */ + *pxTopOfStack = 0x00; + pxTopOfStack--; + *pxTopOfStack = 0x00; + pxTopOfStack--; + *pxTopOfStack = portINITIAL_PSW; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; + + /* When debugging it can be useful if every register is set to a known + value. Otherwise code space can be saved by just setting the registers + that need to be set. */ + #ifdef USE_FULL_REGISTER_INITIALISATION + { + pxTopOfStack--; + *pxTopOfStack = 0x12345678; /* r15. */ + pxTopOfStack--; + *pxTopOfStack = 0xaaaabbbb; + pxTopOfStack--; + *pxTopOfStack = 0xdddddddd; + pxTopOfStack--; + *pxTopOfStack = 0xcccccccc; + pxTopOfStack--; + *pxTopOfStack = 0xbbbbbbbb; + pxTopOfStack--; + *pxTopOfStack = 0xaaaaaaaa; + pxTopOfStack--; + *pxTopOfStack = 0x99999999; + pxTopOfStack--; + *pxTopOfStack = 0x88888888; + pxTopOfStack--; + *pxTopOfStack = 0x77777777; + pxTopOfStack--; + *pxTopOfStack = 0x66666666; + pxTopOfStack--; + *pxTopOfStack = 0x55555555; + pxTopOfStack--; + *pxTopOfStack = 0x44444444; + pxTopOfStack--; + *pxTopOfStack = 0x33333333; + pxTopOfStack--; + *pxTopOfStack = 0x22222222; + pxTopOfStack--; + } + #else + { + /* Leave space for the registers that will get popped from the stack + when the task first starts executing. */ + pxTopOfStack -= 15; + } + #endif + + *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = 0x12345678; /* Accumulator. */ + pxTopOfStack--; + *pxTopOfStack = 0x87654321; /* Accumulator. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Use pxCurrentTCB just so it does not get optimised away. */ + if( pxCurrentTCB != NULL ) + { + /* Call an application function to set up the timer that will generate + the tick interrupt. This way the application can decide which + peripheral to use. If tickless mode is used then the default + implementation defined in this file (which uses CMT0) should not be + overridden. */ + configSETUP_TICK_INTERRUPT(); + + /* Enable the software interrupt. */ + _IEN( _ICU_SWINT ) = 1; + + /* Ensure the software interrupt is clear. */ + _IR( _ICU_SWINT ) = 0; + + /* Ensure the software interrupt is set to the kernel priority. */ + _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the first task. */ + prvStartFirstTask(); + } + + /* Execution should not reach here as the tasks are now running! + prvSetupTimerInterrupt() is called here to prevent the compiler outputting + a warning about a statically declared function not being referenced in the + case that the application writer has provided their own tick interrupt + configuration routine (and defined configSETUP_TICK_INTERRUPT() such that + their own routine will be called in place of prvSetupTimerInterrupt()). */ + prvSetupTimerInterrupt(); + + /* Just to make sure the function is not optimised away. */ + ( void ) vSoftwareInterruptISR(); + + /* Should not get here. */ + return pdFAIL; +} +/*-----------------------------------------------------------*/ + +#pragma inline_asm prvStartFirstTask +static void prvStartFirstTask( void ) +{ + /* When starting the scheduler there is nothing that needs moving to the + interrupt stack because the function is not called from an interrupt. + Just ensure the current stack is the user stack. */ + SETPSW U + + /* Obtain the location of the stack associated with which ever task + pxCurrentTCB is currently pointing to. */ + MOV.L #_pxCurrentTCB, R15 + MOV.L [R15], R15 + MOV.L [R15], R0 + + /* Restore the registers from the stack of the task pointed to by + pxCurrentTCB. */ + POP R15 + MVTACLO R15 /* Accumulator low 32 bits. */ + POP R15 + MVTACHI R15 /* Accumulator high 32 bits. */ + POPM R1-R15 /* R1 to R15 - R0 is not included as it is the SP. */ + RTE /* This pops the remaining registers. */ + NOP + NOP +} +/*-----------------------------------------------------------*/ + +#pragma interrupt ( prvTickISR( vect = _VECT( configTICK_VECTOR ), enable ) ) +void prvTickISR( void ) +{ + /* Increment the tick, and perform any processing the new tick value + necessitates. */ + set_ipl( configMAX_SYSCALL_INTERRUPT_PRIORITY ); + { + if( xTaskIncrementTick() != pdFALSE ) + { + taskYIELD(); + } + } + set_ipl( configKERNEL_INTERRUPT_PRIORITY ); + + #if configUSE_TICKLESS_IDLE == 1 + { + /* The CPU woke because of a tick. */ + ulTickFlag = pdTRUE; + + /* If this is the first tick since exiting tickless mode then the CMT + compare match value needs resetting. */ + CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick; + } + #endif +} +/*-----------------------------------------------------------*/ + +void vSoftwareInterruptISR( void ) +{ + prvYieldHandler(); +} +/*-----------------------------------------------------------*/ + +#pragma inline_asm prvYieldHandler +static void prvYieldHandler( void ) +{ + /* Re-enable interrupts. */ + SETPSW I + + /* Move the data that was automatically pushed onto the interrupt stack + when the interrupt occurred from the interrupt stack to the user stack. + + R15 is saved before it is clobbered. */ + PUSH.L R15 + + /* Read the user stack pointer. */ + MVFC USP, R15 + + /* Move the address down to the data being moved. */ + SUB #12, R15 + MVTC R15, USP + + /* Copy the data across. */ + MOV.L [ R0 ], [ R15 ] ; R15 + MOV.L 4[ R0 ], 4[ R15 ] ; PC + MOV.L 8[ R0 ], 8[ R15 ] ; PSW + + /* Move the interrupt stack pointer to its new correct position. */ + ADD #12, R0 + + /* All the rest of the registers are saved directly to the user stack. */ + SETPSW U + + /* Save the rest of the general registers (R15 has been saved already). */ + PUSHM R1-R14 + + /* Save the accumulator. */ + MVFACHI R15 + PUSH.L R15 + MVFACMI R15 ; Middle order word. + SHLL #16, R15 ; Shifted left as it is restored to the low order word. + PUSH.L R15 + + /* Save the stack pointer to the TCB. */ + MOV.L #_pxCurrentTCB, R15 + MOV.L [ R15 ], R15 + MOV.L R0, [ R15 ] + + /* Ensure the interrupt mask is set to the syscall priority while the + kernel structures are being accessed. */ + MVTIPL #configMAX_SYSCALL_INTERRUPT_PRIORITY + + /* Select the next task to run. */ + BSR.A _vTaskSwitchContext + + /* Reset the interrupt mask as no more data structure access is + required. */ + MVTIPL #configKERNEL_INTERRUPT_PRIORITY + + /* Load the stack pointer of the task that is now selected as the Running + state task from its TCB. */ + MOV.L #_pxCurrentTCB,R15 + MOV.L [ R15 ], R15 + MOV.L [ R15 ], R0 + + /* Restore the context of the new task. The PSW (Program Status Word) and + PC will be popped by the RTE instruction. */ + POP R15 + MVTACLO R15 + POP R15 + MVTACHI R15 + POPM R1-R15 + RTE + NOP + NOP +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( pxCurrentTCB == NULL ); + + /* The following line is just to prevent the symbol getting optimised away. */ + ( void ) vTaskSwitchContext(); +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ + /* Unlock. */ + SYSTEM.PRCR.WORD = portUNLOCK_KEY; + + /* Enable CMT0. */ + MSTP( CMT0 ) = 0; + + /* Lock again. */ + SYSTEM.PRCR.WORD = portLOCK_KEY; + + /* Interrupt on compare match. */ + CMT0.CMCR.BIT.CMIE = 1; + + /* Set the compare match value. */ + CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick; + + /* Divide the PCLK. */ + #if portCLOCK_DIVISOR == 512 + { + CMT0.CMCR.BIT.CKS = 3; + } + #elif portCLOCK_DIVISOR == 128 + { + CMT0.CMCR.BIT.CKS = 2; + } + #elif portCLOCK_DIVISOR == 32 + { + CMT0.CMCR.BIT.CKS = 1; + } + #elif portCLOCK_DIVISOR == 8 + { + CMT0.CMCR.BIT.CKS = 0; + } + #else + { + #error Invalid portCLOCK_DIVISOR setting + } + #endif + + + /* Enable the interrupt... */ + _IEN( _CMT0_CMI0 ) = 1; + + /* ...and set its priority to the application defined kernel priority. */ + _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the timer. */ + CMT.CMSTR0.BIT.STR0 = 1; +} +/*-----------------------------------------------------------*/ + +#if configUSE_TICKLESS_IDLE == 1 + + static void prvSleep( TickType_t xExpectedIdleTime ) + { + /* Allow the application to define some pre-sleep processing. */ + configPRE_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING() + means the application defined code has already executed the WAIT + instruction. */ + if( xExpectedIdleTime > 0 ) + { + wait(); + } + + /* Allow the application to define some post sleep processing. */ + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if configUSE_TICKLESS_IDLE == 1 + + void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount; + eSleepModeStatus eSleepAction; + + /* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */ + + /* Make sure the CMT reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Calculate the reload value required to wait xExpectedIdleTime tick + periods. */ + ulMatchValue = ulMatchValueForOneTick * xExpectedIdleTime; + if( ulMatchValue > ulStoppedTimerCompensation ) + { + /* Compensate for the fact that the CMT is going to be stopped + momentarily. */ + ulMatchValue -= ulStoppedTimerCompensation; + } + + /* Stop the CMT momentarily. The time the CMT is stopped for is + accounted for as best it can be, but using the tickless mode will + inevitably result in some tiny drift of the time maintained by the + kernel with respect to calendar time. */ + CMT.CMSTR0.BIT.STR0 = 0; + while( CMT.CMSTR0.BIT.STR0 == 1 ) + { + /* Nothing to do here. */ + } + + /* Critical section using the global interrupt bit as the i bit is + automatically reset by the WAIT instruction. */ + clrpsw_i(); + + /* The tick flag is set to false before sleeping. If it is true when + sleep mode is exited then sleep mode was probably exited because the + tick was suppressed for the entire xExpectedIdleTime period. */ + ulTickFlag = pdFALSE; + + /* If a context switch is pending then abandon the low power entry as + the context switch might have been pended by an external interrupt that + requires processing. */ + eSleepAction = eTaskConfirmSleepModeStatus(); + if( eSleepAction == eAbortSleep ) + { + /* Restart tick. */ + CMT.CMSTR0.BIT.STR0 = 1; + setpsw_i(); + } + else if( eSleepAction == eNoTasksWaitingTimeout ) + { + /* Protection off. */ + SYSTEM.PRCR.WORD = portUNLOCK_KEY; + + /* Ready for software standby with all clocks stopped. */ + SYSTEM.SBYCR.BIT.SSBY = 1; + + /* Protection on. */ + SYSTEM.PRCR.WORD = portLOCK_KEY; + + /* Sleep until something happens. Calling prvSleep() will + automatically reset the i bit in the PSW. */ + prvSleep( xExpectedIdleTime ); + + /* Restart the CMT. */ + CMT.CMSTR0.BIT.STR0 = 1; + } + else + { + /* Protection off. */ + SYSTEM.PRCR.WORD = portUNLOCK_KEY; + + /* Ready for deep sleep mode. */ + SYSTEM.MSTPCRC.BIT.DSLPE = 1; + SYSTEM.MSTPCRA.BIT.MSTPA28 = 1; + SYSTEM.SBYCR.BIT.SSBY = 0; + + /* Protection on. */ + SYSTEM.PRCR.WORD = portLOCK_KEY; + + /* Adjust the match value to take into account that the current + time slice is already partially complete. */ + ulMatchValue -= ( uint32_t ) CMT0.CMCNT; + CMT0.CMCOR = ( uint16_t ) ulMatchValue; + + /* Restart the CMT to count up to the new match value. */ + CMT0.CMCNT = 0; + CMT.CMSTR0.BIT.STR0 = 1; + + /* Sleep until something happens. Calling prvSleep() will + automatically reset the i bit in the PSW. */ + prvSleep( xExpectedIdleTime ); + + /* Stop CMT. Again, the time the SysTick is stopped for is + accounted for as best it can be, but using the tickless mode will + inevitably result in some tiny drift of the time maintained by the + kernel with respect to calendar time. */ + CMT.CMSTR0.BIT.STR0 = 0; + while( CMT.CMSTR0.BIT.STR0 == 1 ) + { + /* Nothing to do here. */ + } + + ulCurrentCount = ( uint32_t ) CMT0.CMCNT; + + if( ulTickFlag != pdFALSE ) + { + /* The tick interrupt has already executed, although because + this function is called with the scheduler suspended the actual + tick processing will not occur until after this function has + exited. Reset the match value with whatever remains of this + tick period. */ + ulMatchValue = ulMatchValueForOneTick - ulCurrentCount; + CMT0.CMCOR = ( uint16_t ) ulMatchValue; + + /* The tick interrupt handler will already have pended the tick + processing in the kernel. As the pending tick will be + processed as soon as this function exits, the tick value + maintained by the tick is stepped forward by one less than the + time spent sleeping. The actual stepping of the tick appears + later in this function. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. + How many complete tick periods passed while the processor was + sleeping? */ + ulCompleteTickPeriods = ulCurrentCount / ulMatchValueForOneTick; + + /* The match value is set to whatever fraction of a single tick + period remains. */ + ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick ); + CMT0.CMCOR = ( uint16_t ) ulMatchValue; + } + + /* Restart the CMT so it runs up to the match value. The match value + will get set to the value required to generate exactly one tick period + the next time the CMT interrupt executes. */ + CMT0.CMCNT = 0; + CMT.CMSTR0.BIT.STR0 = 1; + + /* Wind the tick forward by the number of tick periods that the CPU + remained in a low power state. */ + vTaskStepTick( ulCompleteTickPeriods ); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ diff --git a/portable/Renesas/RX100/port_asm.src b/portable/Renesas/RX100/port_asm.src new file mode 100644 index 000000000..afe0aba5b --- /dev/null +++ b/portable/Renesas/RX100/port_asm.src @@ -0,0 +1,39 @@ +;/* +; * FreeRTOS Kernel +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + .GLB _vSoftwareInterruptISR + .GLB _vSoftwareInterruptEntry + + .SECTION P,CODE + +_vSoftwareInterruptEntry: + + BRA _vSoftwareInterruptISR + + .RVECTOR 27, _vSoftwareInterruptEntry + + .END diff --git a/portable/Renesas/RX100/portmacro.h b/portable/Renesas/RX100/portmacro.h new file mode 100644 index 000000000..5ae7d05aa --- /dev/null +++ b/portable/Renesas/RX100/portmacro.h @@ -0,0 +1,164 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/* Hardware specifics. */ +#include "machine.h" + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions - these are a bit legacy and not really used now, other +than portSTACK_TYPE and portBASE_TYPE. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() nop() + +#pragma inline_asm vPortYield +static void vPortYield( void ) +{ + /* Save clobbered register - may not actually be necessary if inline asm + functions are considered to use the same rules as function calls by the + compiler. */ + PUSH.L R5 + /* Set ITU SWINTR. */ + MOV.L #872E0H, R5 + MOV.B #1, [R5] + /* Read back to ensure the value is taken before proceeding. */ + MOV.L [R5], R5 + /* Restore clobbered register to its previous value. */ + POP R5 +} +#define portYIELD() vPortYield() +#define portYIELD_FROM_ISR( x ) do { if( x != pdFALSE ) { portYIELD(); } } while( 0 ) + +/* These macros should not be called directly, but through the +taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is +performed if configASSERT() is defined to ensure an assertion handler does not +inadvertently attempt to lower the IPL when the call to assert was triggered +because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY +when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API +functions are those that end in FromISR. FreeRTOS maintains a separate +interrupt API to ensure API function and interrupt entry is as fast and as +simple as possible. */ +#define portENABLE_INTERRUPTS() set_ipl( ( long ) 0 ) +#if ( configASSERT_DEFINED == 1 ) + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) + #define portDISABLE_INTERRUPTS() if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#else + #define portDISABLE_INTERRUPTS() set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#endif + +/* Critical nesting counts are stored in the TCB. */ +#define portCRITICAL_NESTING_IN_TCB ( 1 ) + +/* The critical nesting functions defined within tasks.c. */ +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() + +/* As this port allows interrupt nesting... */ +#define portSET_INTERRUPT_MASK_FROM_ISR() ( UBaseType_t ) get_ipl(); set_ipl( ( signed long ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) set_ipl( ( signed long ) uxSavedInterruptStatus ) + +/*-----------------------------------------------------------*/ + +/* Tickless idle/low power functionality. */ +#if configUSE_TICKLESS_IDLE == 1 + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif +#endif + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#pragma inline_asm vPortMemoryBarrier +static void vPortMemoryBarrier( void ) +{ +} + +#define portMEMORY_BARRIER() vPortMemoryBarrier() + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/Renesas/RX100/readme.txt b/portable/Renesas/RX100/readme.txt new file mode 100644 index 000000000..8dbc983fd --- /dev/null +++ b/portable/Renesas/RX100/readme.txt @@ -0,0 +1,71 @@ +The following table shows which port is recommended to be used. + + +RX MCU Group CPU FPU FPU Port Layer + Core (Single (Double CC-RX GNURX ICCRX (*6) + Type Precision) Precision) + +RX110 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX111 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX113 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX130 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX13T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 + +RX210 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX21A RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX220 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX230,RX231 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23E-A RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23W RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24U RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 + +RX610 RXv1 Yes --- N/A (*4) N/A (*4) N/A (*4) +RX62N,RX621 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX630 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX634 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63N,RX631 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX64M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX65N,RX651 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX66N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX62T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX62G RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX66T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +RX71M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX72M RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +Notes: + +*1: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is not used, please define configSETUP_TICK_INTERRUPT() (in FreeRTOSConfig.h) and provide +the configuration function. Please be aware that port.c is hard coded to use CMT0 though it seems to be +configured to use any CMTn according to the definition of configTICK_VECTOR (in FreeRTOSConfig.h). + +*2: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is used, please modify port.c for the configuration. Please be aware that port.c is +hard coded to use CMT0 though it seems to be configured to use any CMTn according to the definition of +configTICK_VECTOR (in FreeRTOSConfig.h). + +*3: RX100 ports are also available. + +*4: RX600 ports use MVTIPL instruction but RX610 MCUs don't support this instruction. + +*5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h. + +#define configUSE_TASK_DPFPU_SUPPORT 0 + +*6: PriorityDefinitions.h has to be provided for port_asm.s in case of other than RX700v3_DPFPU port. +It contains two definitions of interrupt priority like the following. + +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + + +For more information about Renesas RX MCUs, please visit the following URL: + +https://www.renesas.com/products/microcontrollers-microprocessors/rx.html diff --git a/portable/Renesas/RX200/port.c b/portable/Renesas/RX200/port.c new file mode 100644 index 000000000..fe05cf750 --- /dev/null +++ b/portable/Renesas/RX200/port.c @@ -0,0 +1,322 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the RX200 port. + *----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Library includes. */ +#include "string.h" + +/* Hardware specifics. */ +#include "iodefine.h" + +/*-----------------------------------------------------------*/ + +/* Tasks should start with interrupts enabled and in Supervisor mode, therefore +PSW is set with U and I set, and PM and IPL clear. */ +#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) + +/*-----------------------------------------------------------*/ + +/* The following lines are to ensure vSoftwareInterruptEntry can be referenced, + and therefore installed in the vector table, when the FreeRTOS code is built +as a library. */ +extern BaseType_t vSoftwareInterruptEntry; +const BaseType_t * p_vSoftwareInterruptEntry = &vSoftwareInterruptEntry; + +/*-----------------------------------------------------------*/ + +/* + * Function to start the first task executing - written in asm code as direct + * access to registers is required. + */ +static void prvStartFirstTask( void ); + +/* + * Software interrupt handler. Performs the actual context switch (saving and + * restoring of registers). Written in asm code as direct register access is + * required. + */ +static void prvYieldHandler( void ); + +/* + * The entry point for the software interrupt handler. This is the function + * that calls the inline asm function prvYieldHandler(). It is installed in + * the vector table, but the code that installs it is in prvYieldHandler rather + * than using a #pragma. + */ +void vSoftwareInterruptISR( void ); + +/*-----------------------------------------------------------*/ + +/* This is accessed by the inline assembler functions so is file scope for +convenience. */ +extern void *pxCurrentTCB; +extern void vTaskSwitchContext( void ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* Offset to end up on 8 byte boundary. */ + pxTopOfStack--; + + /* R0 is not included as it is the stack pointer. */ + *pxTopOfStack = 0x00; + pxTopOfStack--; + *pxTopOfStack = 0x00; + pxTopOfStack--; + *pxTopOfStack = portINITIAL_PSW; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; + + /* When debugging it can be useful if every register is set to a known + value. Otherwise code space can be saved by just setting the registers + that need to be set. */ + #ifdef USE_FULL_REGISTER_INITIALISATION + { + pxTopOfStack--; + *pxTopOfStack = 0x12345678; /* r15. */ + pxTopOfStack--; + *pxTopOfStack = 0xaaaabbbb; + pxTopOfStack--; + *pxTopOfStack = 0xdddddddd; + pxTopOfStack--; + *pxTopOfStack = 0xcccccccc; + pxTopOfStack--; + *pxTopOfStack = 0xbbbbbbbb; + pxTopOfStack--; + *pxTopOfStack = 0xaaaaaaaa; + pxTopOfStack--; + *pxTopOfStack = 0x99999999; + pxTopOfStack--; + *pxTopOfStack = 0x88888888; + pxTopOfStack--; + *pxTopOfStack = 0x77777777; + pxTopOfStack--; + *pxTopOfStack = 0x66666666; + pxTopOfStack--; + *pxTopOfStack = 0x55555555; + pxTopOfStack--; + *pxTopOfStack = 0x44444444; + pxTopOfStack--; + *pxTopOfStack = 0x33333333; + pxTopOfStack--; + *pxTopOfStack = 0x22222222; + pxTopOfStack--; + } + #else + { + pxTopOfStack -= 15; + } + #endif + + *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = 0x12345678; /* Accumulator. */ + pxTopOfStack--; + *pxTopOfStack = 0x87654321; /* Accumulator. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void vApplicationSetupTimerInterrupt( void ); + + /* Use pxCurrentTCB just so it does not get optimised away. */ + if( pxCurrentTCB != NULL ) + { + /* Call an application function to set up the timer that will generate the + tick interrupt. This way the application can decide which peripheral to + use. A demo application is provided to show a suitable example. */ + vApplicationSetupTimerInterrupt(); + + /* Enable the software interrupt. */ + _IEN( _ICU_SWINT ) = 1; + + /* Ensure the software interrupt is clear. */ + _IR( _ICU_SWINT ) = 0; + + /* Ensure the software interrupt is set to the kernel priority. */ + _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the first task. */ + prvStartFirstTask(); + } + + /* Just to make sure the function is not optimised away. */ + ( void ) vSoftwareInterruptISR(); + + /* Should not get here. */ + return pdFAIL; +} +/*-----------------------------------------------------------*/ + +#pragma inline_asm prvStartFirstTask +static void prvStartFirstTask( void ) +{ + /* When starting the scheduler there is nothing that needs moving to the + interrupt stack because the function is not called from an interrupt. + Just ensure the current stack is the user stack. */ + SETPSW U + + /* Obtain the location of the stack associated with which ever task + pxCurrentTCB is currently pointing to. */ + MOV.L #_pxCurrentTCB, R15 + MOV.L [R15], R15 + MOV.L [R15], R0 + + /* Restore the registers from the stack of the task pointed to by + pxCurrentTCB. */ + POP R15 + MVTACLO R15 /* Accumulator low 32 bits. */ + POP R15 + MVTACHI R15 /* Accumulator high 32 bits. */ + POPM R1-R15 /* R1 to R15 - R0 is not included as it is the SP. */ + RTE /* This pops the remaining registers. */ + NOP + NOP +} +/*-----------------------------------------------------------*/ + +#pragma interrupt ( vTickISR( vect = _VECT( configTICK_VECTOR ), enable ) ) +void vTickISR( void ) +{ + /* Increment the tick, and perform any processing the new tick value + necessitates. */ + set_ipl( configMAX_SYSCALL_INTERRUPT_PRIORITY ); + { + if( xTaskIncrementTick() != pdFALSE ) + { + taskYIELD(); + } + } + set_ipl( configKERNEL_INTERRUPT_PRIORITY ); +} +/*-----------------------------------------------------------*/ + +void vSoftwareInterruptISR( void ) +{ + prvYieldHandler(); +} +/*-----------------------------------------------------------*/ + +#pragma inline_asm prvYieldHandler +static void prvYieldHandler( void ) +{ + /* Re-enable interrupts. */ + SETPSW I + + /* Move the data that was automatically pushed onto the interrupt stack when + the interrupt occurred from the interrupt stack to the user stack. + + R15 is saved before it is clobbered. */ + PUSH.L R15 + + /* Read the user stack pointer. */ + MVFC USP, R15 + + /* Move the address down to the data being moved. */ + SUB #12, R15 + MVTC R15, USP + + /* Copy the data across. */ + MOV.L [ R0 ], [ R15 ] ; R15 + MOV.L 4[ R0 ], 4[ R15 ] ; PC + MOV.L 8[ R0 ], 8[ R15 ] ; PSW + + /* Move the interrupt stack pointer to its new correct position. */ + ADD #12, R0 + + /* All the rest of the registers are saved directly to the user stack. */ + SETPSW U + + /* Save the rest of the general registers (R15 has been saved already). */ + PUSHM R1-R14 + + /* Save the accumulator. */ + MVFACHI R15 + PUSH.L R15 + MVFACMI R15 ; Middle order word. + SHLL #16, R15 ; Shifted left as it is restored to the low order word. + PUSH.L R15 + + /* Save the stack pointer to the TCB. */ + MOV.L #_pxCurrentTCB, R15 + MOV.L [ R15 ], R15 + MOV.L R0, [ R15 ] + + /* Ensure the interrupt mask is set to the syscall priority while the kernel + structures are being accessed. */ + MVTIPL #configMAX_SYSCALL_INTERRUPT_PRIORITY + + /* Select the next task to run. */ + BSR.A _vTaskSwitchContext + + /* Reset the interrupt mask as no more data structure access is required. */ + MVTIPL #configKERNEL_INTERRUPT_PRIORITY + + /* Load the stack pointer of the task that is now selected as the Running + state task from its TCB. */ + MOV.L #_pxCurrentTCB,R15 + MOV.L [ R15 ], R15 + MOV.L [ R15 ], R0 + + /* Restore the context of the new task. The PSW (Program Status Word) and + PC will be popped by the RTE instruction. */ + POP R15 + MVTACLO R15 + POP R15 + MVTACHI R15 + POPM R1-R15 + RTE + NOP + NOP +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( pxCurrentTCB == NULL ); + + /* The following line is just to prevent the symbol getting optimised away. */ + ( void ) vTaskSwitchContext(); +} +/*-----------------------------------------------------------*/ diff --git a/portable/Renesas/RX200/port_asm.src b/portable/Renesas/RX200/port_asm.src new file mode 100644 index 000000000..afe0aba5b --- /dev/null +++ b/portable/Renesas/RX200/port_asm.src @@ -0,0 +1,39 @@ +;/* +; * FreeRTOS Kernel +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + .GLB _vSoftwareInterruptISR + .GLB _vSoftwareInterruptEntry + + .SECTION P,CODE + +_vSoftwareInterruptEntry: + + BRA _vSoftwareInterruptISR + + .RVECTOR 27, _vSoftwareInterruptEntry + + .END diff --git a/portable/Renesas/RX200/portmacro.h b/portable/Renesas/RX200/portmacro.h new file mode 100644 index 000000000..bf11b2e93 --- /dev/null +++ b/portable/Renesas/RX200/portmacro.h @@ -0,0 +1,153 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/* Hardware specifics. */ +#include "machine.h" + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions - these are a bit legacy and not really used now, other than +portSTACK_TYPE and portBASE_TYPE. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() nop() + +#pragma inline_asm vPortYield +static void vPortYield( void ) +{ + /* Save clobbered register - may not actually be necessary if inline asm + functions are considered to use the same rules as function calls by the + compiler. */ + PUSH.L R5 + /* Set ITU SWINTR. */ + MOV.L #553696, R5 + MOV.B #1, [R5] + /* Read back to ensure the value is taken before proceeding. */ + MOV.L [R5], R5 + /* Restore clobbered register to its previous value. */ + POP R5 +} +#define portYIELD() vPortYield() +#define portYIELD_FROM_ISR( x ) do { if( x != pdFALSE ) portYIELD(); } while( 0 ) + +/* These macros should not be called directly, but through the +taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is +performed if configASSERT() is defined to ensure an assertion handler does not +inadvertently attempt to lower the IPL when the call to assert was triggered +because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY +when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API +functions are those that end in FromISR. FreeRTOS maintains a separate +interrupt API to ensure API function and interrupt entry is as fast and as +simple as possible. */ +#define portENABLE_INTERRUPTS() set_ipl( ( long ) 0 ) +#if ( configASSERT_DEFINED == 1 ) + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) + #define portDISABLE_INTERRUPTS() if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#else + #define portDISABLE_INTERRUPTS() set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#endif + +/* Critical nesting counts are stored in the TCB. */ +#define portCRITICAL_NESTING_IN_TCB ( 1 ) + +/* The critical nesting functions defined within tasks.c. */ +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() + +/* As this port allows interrupt nesting... */ +#define portSET_INTERRUPT_MASK_FROM_ISR() get_ipl(); set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) set_ipl( ( long ) uxSavedInterruptStatus ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#pragma inline_asm vPortMemoryBarrier +static void vPortMemoryBarrier( void ) +{ +} + +#define portMEMORY_BARRIER() vPortMemoryBarrier() +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/Renesas/RX200/readme.txt b/portable/Renesas/RX200/readme.txt new file mode 100644 index 000000000..8dbc983fd --- /dev/null +++ b/portable/Renesas/RX200/readme.txt @@ -0,0 +1,71 @@ +The following table shows which port is recommended to be used. + + +RX MCU Group CPU FPU FPU Port Layer + Core (Single (Double CC-RX GNURX ICCRX (*6) + Type Precision) Precision) + +RX110 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX111 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX113 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX130 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX13T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 + +RX210 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX21A RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX220 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX230,RX231 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23E-A RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23W RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24U RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 + +RX610 RXv1 Yes --- N/A (*4) N/A (*4) N/A (*4) +RX62N,RX621 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX630 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX634 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63N,RX631 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX64M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX65N,RX651 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX66N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX62T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX62G RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX66T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +RX71M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX72M RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +Notes: + +*1: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is not used, please define configSETUP_TICK_INTERRUPT() (in FreeRTOSConfig.h) and provide +the configuration function. Please be aware that port.c is hard coded to use CMT0 though it seems to be +configured to use any CMTn according to the definition of configTICK_VECTOR (in FreeRTOSConfig.h). + +*2: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is used, please modify port.c for the configuration. Please be aware that port.c is +hard coded to use CMT0 though it seems to be configured to use any CMTn according to the definition of +configTICK_VECTOR (in FreeRTOSConfig.h). + +*3: RX100 ports are also available. + +*4: RX600 ports use MVTIPL instruction but RX610 MCUs don't support this instruction. + +*5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h. + +#define configUSE_TASK_DPFPU_SUPPORT 0 + +*6: PriorityDefinitions.h has to be provided for port_asm.s in case of other than RX700v3_DPFPU port. +It contains two definitions of interrupt priority like the following. + +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + + +For more information about Renesas RX MCUs, please visit the following URL: + +https://www.renesas.com/products/microcontrollers-microprocessors/rx.html diff --git a/portable/Renesas/RX600/port.c b/portable/Renesas/RX600/port.c new file mode 100644 index 000000000..95431adce --- /dev/null +++ b/portable/Renesas/RX600/port.c @@ -0,0 +1,327 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the RX600 port. + *----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Library includes. */ +#include "string.h" + +/* Hardware specifics. */ +#include "iodefine.h" + +/*-----------------------------------------------------------*/ + +/* Tasks should start with interrupts enabled and in Supervisor mode, therefore +PSW is set with U and I set, and PM and IPL clear. */ +#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) +#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 ) + +/*-----------------------------------------------------------*/ + +/* The following lines are to ensure vSoftwareInterruptEntry can be referenced, + and therefore installed in the vector table, when the FreeRTOS code is built +as a library. */ +extern BaseType_t vSoftwareInterruptEntry; +const BaseType_t * p_vSoftwareInterruptEntry = &vSoftwareInterruptEntry; + +/*-----------------------------------------------------------*/ + +/* + * Function to start the first task executing - written in asm code as direct + * access to registers is required. + */ +static void prvStartFirstTask( void ); + +/* + * Software interrupt handler. Performs the actual context switch (saving and + * restoring of registers). Written in asm code as direct register access is + * required. + */ +static void prvYieldHandler( void ); + +/* + * The entry point for the software interrupt handler. This is the function + * that calls the inline asm function prvYieldHandler(). It is installed in + * the vector table, but the code that installs it is in prvYieldHandler rather + * than using a #pragma. + */ +void vSoftwareInterruptISR( void ); + +/*-----------------------------------------------------------*/ + +/* This is accessed by the inline assembler functions so is file scope for +convenience. */ +extern void *pxCurrentTCB; +extern void vTaskSwitchContext( void ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* R0 is not included as it is the stack pointer. */ + + *pxTopOfStack = 0x00; + pxTopOfStack--; + *pxTopOfStack = portINITIAL_PSW; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; + + /* When debugging it can be useful if every register is set to a known + value. Otherwise code space can be saved by just setting the registers + that need to be set. */ + #ifdef USE_FULL_REGISTER_INITIALISATION + { + pxTopOfStack--; + *pxTopOfStack = 0xffffffff; /* r15. */ + pxTopOfStack--; + *pxTopOfStack = 0xeeeeeeee; + pxTopOfStack--; + *pxTopOfStack = 0xdddddddd; + pxTopOfStack--; + *pxTopOfStack = 0xcccccccc; + pxTopOfStack--; + *pxTopOfStack = 0xbbbbbbbb; + pxTopOfStack--; + *pxTopOfStack = 0xaaaaaaaa; + pxTopOfStack--; + *pxTopOfStack = 0x99999999; + pxTopOfStack--; + *pxTopOfStack = 0x88888888; + pxTopOfStack--; + *pxTopOfStack = 0x77777777; + pxTopOfStack--; + *pxTopOfStack = 0x66666666; + pxTopOfStack--; + *pxTopOfStack = 0x55555555; + pxTopOfStack--; + *pxTopOfStack = 0x44444444; + pxTopOfStack--; + *pxTopOfStack = 0x33333333; + pxTopOfStack--; + *pxTopOfStack = 0x22222222; + pxTopOfStack--; + } + #else + { + pxTopOfStack -= 15; + } + #endif + + *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_FPSW; + pxTopOfStack--; + *pxTopOfStack = 0x12345678; /* Accumulator. */ + pxTopOfStack--; + *pxTopOfStack = 0x87654321; /* Accumulator. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void vApplicationSetupTimerInterrupt( void ); + + /* Use pxCurrentTCB just so it does not get optimised away. */ + if( pxCurrentTCB != NULL ) + { + /* Call an application function to set up the timer that will generate the + tick interrupt. This way the application can decide which peripheral to + use. A demo application is provided to show a suitable example. */ + vApplicationSetupTimerInterrupt(); + + /* Enable the software interrupt. */ + _IEN( _ICU_SWINT ) = 1; + + /* Ensure the software interrupt is clear. */ + _IR( _ICU_SWINT ) = 0; + + /* Ensure the software interrupt is set to the kernel priority. */ + _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the first task. */ + prvStartFirstTask(); + } + + /* Just to make sure the function is not optimised away. */ + ( void ) vSoftwareInterruptISR(); + + /* Should not get here. */ + return pdFAIL; +} +/*-----------------------------------------------------------*/ + +#pragma inline_asm prvStartFirstTask +static void prvStartFirstTask( void ) +{ + /* When starting the scheduler there is nothing that needs moving to the + interrupt stack because the function is not called from an interrupt. + Just ensure the current stack is the user stack. */ + SETPSW U + + /* Obtain the location of the stack associated with which ever task + pxCurrentTCB is currently pointing to. */ + MOV.L #_pxCurrentTCB, R15 + MOV.L [R15], R15 + MOV.L [R15], R0 + + /* Restore the registers from the stack of the task pointed to by + pxCurrentTCB. */ + POP R15 + MVTACLO R15 /* Accumulator low 32 bits. */ + POP R15 + MVTACHI R15 /* Accumulator high 32 bits. */ + POP R15 + MVTC R15,FPSW /* Floating point status word. */ + POPM R1-R15 /* R1 to R15 - R0 is not included as it is the SP. */ + RTE /* This pops the remaining registers. */ + NOP + NOP +} +/*-----------------------------------------------------------*/ + +#pragma interrupt ( vTickISR( vect = _VECT( configTICK_VECTOR ), enable ) ) +void vTickISR( void ) +{ + /* Increment the tick, and perform any processing the new tick value + necessitates. */ + set_ipl( configMAX_SYSCALL_INTERRUPT_PRIORITY ); + { + if( xTaskIncrementTick() != pdFALSE ) + { + taskYIELD(); + } + } + set_ipl( configKERNEL_INTERRUPT_PRIORITY ); +} +/*-----------------------------------------------------------*/ + +void vSoftwareInterruptISR( void ) +{ + prvYieldHandler(); +} +/*-----------------------------------------------------------*/ + +#pragma inline_asm prvYieldHandler +static void prvYieldHandler( void ) +{ + /* Re-enable interrupts. */ + SETPSW I + + /* Move the data that was automatically pushed onto the interrupt stack when + the interrupt occurred from the interrupt stack to the user stack. + + R15 is saved before it is clobbered. */ + PUSH.L R15 + + /* Read the user stack pointer. */ + MVFC USP, R15 + + /* Move the address down to the data being moved. */ + SUB #12, R15 + MVTC R15, USP + + /* Copy the data across. */ + MOV.L [ R0 ], [ R15 ] ; R15 + MOV.L 4[ R0 ], 4[ R15 ] ; PC + MOV.L 8[ R0 ], 8[ R15 ] ; PSW + + /* Move the interrupt stack pointer to its new correct position. */ + ADD #12, R0 + + /* All the rest of the registers are saved directly to the user stack. */ + SETPSW U + + /* Save the rest of the general registers (R15 has been saved already). */ + PUSHM R1-R14 + + /* Save the FPSW and accumulator. */ + MVFC FPSW, R15 + PUSH.L R15 + MVFACHI R15 + PUSH.L R15 + MVFACMI R15 ; Middle order word. + SHLL #16, R15 ; Shifted left as it is restored to the low order word. + PUSH.L R15 + + /* Save the stack pointer to the TCB. */ + MOV.L #_pxCurrentTCB, R15 + MOV.L [ R15 ], R15 + MOV.L R0, [ R15 ] + + /* Ensure the interrupt mask is set to the syscall priority while the kernel + structures are being accessed. */ + MVTIPL #configMAX_SYSCALL_INTERRUPT_PRIORITY + + /* Select the next task to run. */ + BSR.A _vTaskSwitchContext + + /* Reset the interrupt mask as no more data structure access is required. */ + MVTIPL #configKERNEL_INTERRUPT_PRIORITY + + /* Load the stack pointer of the task that is now selected as the Running + state task from its TCB. */ + MOV.L #_pxCurrentTCB,R15 + MOV.L [ R15 ], R15 + MOV.L [ R15 ], R0 + + /* Restore the context of the new task. The PSW (Program Status Word) and + PC will be popped by the RTE instruction. */ + POP R15 + MVTACLO R15 + POP R15 + MVTACHI R15 + POP R15 + MVTC R15,FPSW + POPM R1-R15 + RTE + NOP + NOP +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( pxCurrentTCB == NULL ); + + /* The following line is just to prevent the symbol getting optimised away. */ + ( void ) vTaskSwitchContext(); +} +/*-----------------------------------------------------------*/ diff --git a/portable/Renesas/RX600/port_asm.src b/portable/Renesas/RX600/port_asm.src new file mode 100644 index 000000000..afe0aba5b --- /dev/null +++ b/portable/Renesas/RX600/port_asm.src @@ -0,0 +1,39 @@ +;/* +; * FreeRTOS Kernel +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + .GLB _vSoftwareInterruptISR + .GLB _vSoftwareInterruptEntry + + .SECTION P,CODE + +_vSoftwareInterruptEntry: + + BRA _vSoftwareInterruptISR + + .RVECTOR 27, _vSoftwareInterruptEntry + + .END diff --git a/portable/Renesas/RX600/portmacro.h b/portable/Renesas/RX600/portmacro.h new file mode 100644 index 000000000..53f45dec7 --- /dev/null +++ b/portable/Renesas/RX600/portmacro.h @@ -0,0 +1,155 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/* Hardware specifics. */ +#include "machine.h" + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions - these are a bit legacy and not really used now, other than +portSTACK_TYPE and portBASE_TYPE. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() nop() + + +#pragma inline_asm vPortYield +static void vPortYield( void ) +{ + /* Save clobbered register - may not actually be necessary if inline asm + functions are considered to use the same rules as function calls by the + compiler. */ + PUSH.L R5 + /* Set ITU SWINTR. */ + MOV.L #553696, R5 + MOV.B #1, [R5] + /* Read back to ensure the value is taken before proceeding. */ + MOV.L [R5], R5 + /* Restore clobbered register to its previous value. */ + POP R5 +} +#define portYIELD() vPortYield() +#define portYIELD_FROM_ISR( x ) do { if( x != pdFALSE ) portYIELD(); } while( 0 ) + +/* These macros should not be called directly, but through the +taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is +performed if configASSERT() is defined to ensure an assertion handler does not +inadvertently attempt to lower the IPL when the call to assert was triggered +because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY +when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API +functions are those that end in FromISR. FreeRTOS maintains a separate +interrupt API to ensure API function and interrupt entry is as fast and as +simple as possible. */ +#define portENABLE_INTERRUPTS() set_ipl( ( long ) 0 ) +#if ( configASSERT_DEFINED == 1 ) + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) + #define portDISABLE_INTERRUPTS() if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#else + #define portDISABLE_INTERRUPTS() set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#endif + +/* Critical nesting counts are stored in the TCB. */ +#define portCRITICAL_NESTING_IN_TCB ( 1 ) + +/* The critical nesting functions defined within tasks.c. */ +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() + +/* As this port allows interrupt nesting... */ +#define portSET_INTERRUPT_MASK_FROM_ISR() get_ipl(); set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) set_ipl( ( long ) uxSavedInterruptStatus ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#pragma inline_asm vPortMemoryBarrier +static void vPortMemoryBarrier( void ) +{ +} + +#define portMEMORY_BARRIER() vPortMemoryBarrier() + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/Renesas/RX600/readme.txt b/portable/Renesas/RX600/readme.txt new file mode 100644 index 000000000..8dbc983fd --- /dev/null +++ b/portable/Renesas/RX600/readme.txt @@ -0,0 +1,71 @@ +The following table shows which port is recommended to be used. + + +RX MCU Group CPU FPU FPU Port Layer + Core (Single (Double CC-RX GNURX ICCRX (*6) + Type Precision) Precision) + +RX110 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX111 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX113 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX130 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX13T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 + +RX210 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX21A RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX220 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX230,RX231 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23E-A RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23W RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24U RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 + +RX610 RXv1 Yes --- N/A (*4) N/A (*4) N/A (*4) +RX62N,RX621 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX630 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX634 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63N,RX631 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX64M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX65N,RX651 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX66N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX62T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX62G RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX66T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +RX71M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX72M RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +Notes: + +*1: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is not used, please define configSETUP_TICK_INTERRUPT() (in FreeRTOSConfig.h) and provide +the configuration function. Please be aware that port.c is hard coded to use CMT0 though it seems to be +configured to use any CMTn according to the definition of configTICK_VECTOR (in FreeRTOSConfig.h). + +*2: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is used, please modify port.c for the configuration. Please be aware that port.c is +hard coded to use CMT0 though it seems to be configured to use any CMTn according to the definition of +configTICK_VECTOR (in FreeRTOSConfig.h). + +*3: RX100 ports are also available. + +*4: RX600 ports use MVTIPL instruction but RX610 MCUs don't support this instruction. + +*5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h. + +#define configUSE_TASK_DPFPU_SUPPORT 0 + +*6: PriorityDefinitions.h has to be provided for port_asm.s in case of other than RX700v3_DPFPU port. +It contains two definitions of interrupt priority like the following. + +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + + +For more information about Renesas RX MCUs, please visit the following URL: + +https://www.renesas.com/products/microcontrollers-microprocessors/rx.html diff --git a/portable/Renesas/RX600v2/port.c b/portable/Renesas/RX600v2/port.c new file mode 100644 index 000000000..bae8fd623 --- /dev/null +++ b/portable/Renesas/RX600v2/port.c @@ -0,0 +1,362 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the RX600 port. + *----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Library includes. */ +#include "string.h" + +/* Hardware specifics. */ +#if defined( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H ) && ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 ) + #include "platform.h" +#else + #include "iodefine.h" +#endif + +/*-----------------------------------------------------------*/ + +/* Tasks should start with interrupts enabled and in Supervisor mode, therefore +PSW is set with U and I set, and PM and IPL clear. */ +#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) +#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 ) + +/*-----------------------------------------------------------*/ + +/* The following lines are to ensure vSoftwareInterruptEntry can be referenced, + and therefore installed in the vector table, when the FreeRTOS code is built +as a library. */ +extern BaseType_t vSoftwareInterruptEntry; +const BaseType_t * p_vSoftwareInterruptEntry = &vSoftwareInterruptEntry; + +/*-----------------------------------------------------------*/ + +/* + * Function to start the first task executing - written in asm code as direct + * access to registers is required. + */ +static void prvStartFirstTask( void ); + +/* + * Software interrupt handler. Performs the actual context switch (saving and + * restoring of registers). Written in asm code as direct register access is + * required. + */ +static void prvYieldHandler( void ); + +/* + * The entry point for the software interrupt handler. This is the function + * that calls the inline asm function prvYieldHandler(). It is installed in + * the vector table, but the code that installs it is in prvYieldHandler rather + * than using a #pragma. + */ +void vSoftwareInterruptISR( void ); + +/*-----------------------------------------------------------*/ + +/* This is accessed by the inline assembler functions so is file scope for +convenience. */ +extern void *pxCurrentTCB; +extern void vTaskSwitchContext( void ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* R0 is not included as it is the stack pointer. */ + + *pxTopOfStack = 0x00; + pxTopOfStack--; + *pxTopOfStack = portINITIAL_PSW; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; + + /* When debugging it can be useful if every register is set to a known + value. Otherwise code space can be saved by just setting the registers + that need to be set. */ + #ifdef USE_FULL_REGISTER_INITIALISATION + { + pxTopOfStack--; + *pxTopOfStack = 0xffffffff; /* r15. */ + pxTopOfStack--; + *pxTopOfStack = 0xeeeeeeee; + pxTopOfStack--; + *pxTopOfStack = 0xdddddddd; + pxTopOfStack--; + *pxTopOfStack = 0xcccccccc; + pxTopOfStack--; + *pxTopOfStack = 0xbbbbbbbb; + pxTopOfStack--; + *pxTopOfStack = 0xaaaaaaaa; + pxTopOfStack--; + *pxTopOfStack = 0x99999999; + pxTopOfStack--; + *pxTopOfStack = 0x88888888; + pxTopOfStack--; + *pxTopOfStack = 0x77777777; + pxTopOfStack--; + *pxTopOfStack = 0x66666666; + pxTopOfStack--; + *pxTopOfStack = 0x55555555; + pxTopOfStack--; + *pxTopOfStack = 0x44444444; + pxTopOfStack--; + *pxTopOfStack = 0x33333333; + pxTopOfStack--; + *pxTopOfStack = 0x22222222; + pxTopOfStack--; + } + #else + { + pxTopOfStack -= 15; + } + #endif + + *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_FPSW; + pxTopOfStack--; + *pxTopOfStack = 0x11111111; /* Accumulator 0. */ + pxTopOfStack--; + *pxTopOfStack = 0x22222222; /* Accumulator 0. */ + pxTopOfStack--; + *pxTopOfStack = 0x33333333; /* Accumulator 0. */ + pxTopOfStack--; + *pxTopOfStack = 0x44444444; /* Accumulator 1. */ + pxTopOfStack--; + *pxTopOfStack = 0x55555555; /* Accumulator 1. */ + pxTopOfStack--; + *pxTopOfStack = 0x66666666; /* Accumulator 1. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void vApplicationSetupTimerInterrupt( void ); + + /* Use pxCurrentTCB just so it does not get optimised away. */ + if( pxCurrentTCB != NULL ) + { + /* Call an application function to set up the timer that will generate the + tick interrupt. This way the application can decide which peripheral to + use. A demo application is provided to show a suitable example. */ + vApplicationSetupTimerInterrupt(); + + /* Enable the software interrupt. */ + _IEN( _ICU_SWINT ) = 1; + + /* Ensure the software interrupt is clear. */ + _IR( _ICU_SWINT ) = 0; + + /* Ensure the software interrupt is set to the kernel priority. */ + _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the first task. */ + prvStartFirstTask(); + } + + /* Just to make sure the function is not optimised away. */ + ( void ) vSoftwareInterruptISR(); + + /* Should not get here. */ + return pdFAIL; +} +/*-----------------------------------------------------------*/ + +#pragma inline_asm prvStartFirstTask +static void prvStartFirstTask( void ) +{ + /* When starting the scheduler there is nothing that needs moving to the + interrupt stack because the function is not called from an interrupt. + Just ensure the current stack is the user stack. */ + SETPSW U + + /* Obtain the location of the stack associated with which ever task + pxCurrentTCB is currently pointing to. */ + MOV.L #_pxCurrentTCB, R15 + MOV.L [R15], R15 + MOV.L [R15], R0 + + /* Restore the registers from the stack of the task pointed to by + pxCurrentTCB. */ + POP R15 + MVTACLO R15, A0 /* Accumulator low 32 bits. */ + POP R15 + MVTACHI R15, A0 /* Accumulator high 32 bits. */ + POP R15 + MVTACGU R15, A0 /* Accumulator guard. */ + POP R15 + MVTACLO R15, A1 /* Accumulator low 32 bits. */ + POP R15 + MVTACHI R15, A1 /* Accumulator high 32 bits. */ + POP R15 + MVTACGU R15, A1 /* Accumulator guard. */ + POP R15 + MVTC R15,FPSW /* Floating point status word. */ + POPM R1-R15 /* R1 to R15 - R0 is not included as it is the SP. */ + RTE /* This pops the remaining registers. */ + NOP + NOP +} +/*-----------------------------------------------------------*/ + +#pragma interrupt ( vTickISR( vect = _VECT( configTICK_VECTOR ), enable ) ) +void vTickISR( void ) +{ + /* Increment the tick, and perform any processing the new tick value + necessitates. */ + set_ipl( configMAX_SYSCALL_INTERRUPT_PRIORITY ); + { + if( xTaskIncrementTick() != pdFALSE ) + { + taskYIELD(); + } + } + set_ipl( configKERNEL_INTERRUPT_PRIORITY ); +} +/*-----------------------------------------------------------*/ + +void vSoftwareInterruptISR( void ) +{ + prvYieldHandler(); +} +/*-----------------------------------------------------------*/ + +#pragma inline_asm prvYieldHandler +static void prvYieldHandler( void ) +{ + /* Re-enable interrupts. */ + SETPSW I + + /* Move the data that was automatically pushed onto the interrupt stack when + the interrupt occurred from the interrupt stack to the user stack. + + R15 is saved before it is clobbered. */ + PUSH.L R15 + + /* Read the user stack pointer. */ + MVFC USP, R15 + + /* Move the address down to the data being moved. */ + SUB #12, R15 + MVTC R15, USP + + /* Copy the data across. */ + MOV.L [ R0 ], [ R15 ] ; R15 + MOV.L 4[ R0 ], 4[ R15 ] ; PC + MOV.L 8[ R0 ], 8[ R15 ] ; PSW + + /* Move the interrupt stack pointer to its new correct position. */ + ADD #12, R0 + + /* All the rest of the registers are saved directly to the user stack. */ + SETPSW U + + /* Save the rest of the general registers (R15 has been saved already). */ + PUSHM R1-R14 + + /* Save the FPSW and accumulators. */ + MVFC FPSW, R15 + PUSH.L R15 + MVFACGU #0, A1, R15 + PUSH.L R15 + MVFACHI #0, A1, R15 + PUSH.L R15 + MVFACLO #0, A1, R15 ; Low order word. + PUSH.L R15 + MVFACGU #0, A0, R15 + PUSH.L R15 + MVFACHI #0, A0, R15 + PUSH.L R15 + MVFACLO #0, A0, R15 ; Low order word. + PUSH.L R15 + + /* Save the stack pointer to the TCB. */ + MOV.L #_pxCurrentTCB, R15 + MOV.L [ R15 ], R15 + MOV.L R0, [ R15 ] + + /* Ensure the interrupt mask is set to the syscall priority while the kernel + structures are being accessed. */ + MVTIPL #configMAX_SYSCALL_INTERRUPT_PRIORITY + + /* Select the next task to run. */ + BSR.A _vTaskSwitchContext + + /* Reset the interrupt mask as no more data structure access is required. */ + MVTIPL #configKERNEL_INTERRUPT_PRIORITY + + /* Load the stack pointer of the task that is now selected as the Running + state task from its TCB. */ + MOV.L #_pxCurrentTCB,R15 + MOV.L [ R15 ], R15 + MOV.L [ R15 ], R0 + + /* Restore the context of the new task. The PSW (Program Status Word) and + PC will be popped by the RTE instruction. */ + POP R15 + MVTACLO R15, A0 /* Accumulator low 32 bits. */ + POP R15 + MVTACHI R15, A0 /* Accumulator high 32 bits. */ + POP R15 + MVTACGU R15, A0 /* Accumulator guard. */ + POP R15 + MVTACLO R15, A1 /* Accumulator low 32 bits. */ + POP R15 + MVTACHI R15, A1 /* Accumulator high 32 bits. */ + POP R15 + MVTACGU R15, A1 /* Accumulator guard. */ + POP R15 + MVTC R15,FPSW + POPM R1-R15 + RTE + NOP + NOP +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( pxCurrentTCB == NULL ); + + /* The following line is just to prevent the symbol getting optimised away. */ + ( void ) vTaskSwitchContext(); +} +/*-----------------------------------------------------------*/ diff --git a/portable/Renesas/RX600v2/port_asm.src b/portable/Renesas/RX600v2/port_asm.src new file mode 100644 index 000000000..8d5200b6c --- /dev/null +++ b/portable/Renesas/RX600v2/port_asm.src @@ -0,0 +1,39 @@ +;/* +; * FreeRTOS Kernel +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + .GLB _vSoftwareInterruptISR + .GLB _vSoftwareInterruptEntry + + .SECTION P,CODE + +_vSoftwareInterruptEntry: + + BRA _vSoftwareInterruptISR + + .RVECTOR 27, _vSoftwareInterruptEntry + + .END diff --git a/portable/Renesas/RX600v2/portmacro.h b/portable/Renesas/RX600v2/portmacro.h new file mode 100644 index 000000000..0442b05a1 --- /dev/null +++ b/portable/Renesas/RX600v2/portmacro.h @@ -0,0 +1,155 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/* Hardware specifics. */ +#include "machine.h" + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions - these are a bit legacy and not really used now, other than +portSTACK_TYPE and portBASE_TYPE. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() nop() + + +#pragma inline_asm vPortYield +static void vPortYield( void ) +{ + /* Save clobbered register - may not actually be necessary if inline asm + functions are considered to use the same rules as function calls by the + compiler. */ + PUSH.L R5 + /* Set ITU SWINTR. */ + MOV.L #553696, R5 + MOV.B #1, [R5] + /* Read back to ensure the value is taken before proceeding. */ + MOV.L [R5], R5 + /* Restore clobbered register to its previous value. */ + POP R5 +} +#define portYIELD() vPortYield() +#define portYIELD_FROM_ISR( x ) do { if( x != pdFALSE ) portYIELD(); } while( 0 ) + +/* These macros should not be called directly, but through the +taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is +performed if configASSERT() is defined to ensure an assertion handler does not +inadvertently attempt to lower the IPL when the call to assert was triggered +because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY +when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API +functions are those that end in FromISR. FreeRTOS maintains a separate +interrupt API to ensure API function and interrupt entry is as fast and as +simple as possible. */ +#define portENABLE_INTERRUPTS() set_ipl( ( long ) 0 ) +#if ( configASSERT_DEFINED == 1 ) + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) + #define portDISABLE_INTERRUPTS() if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#else + #define portDISABLE_INTERRUPTS() set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#endif + +/* Critical nesting counts are stored in the TCB. */ +#define portCRITICAL_NESTING_IN_TCB ( 1 ) + +/* The critical nesting functions defined within tasks.c. */ +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() + +/* As this port allows interrupt nesting... */ +#define portSET_INTERRUPT_MASK_FROM_ISR() ( UBaseType_t ) get_ipl(); set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) set_ipl( ( long ) uxSavedInterruptStatus ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#pragma inline_asm vPortMemoryBarrier +static void vPortMemoryBarrier( void ) +{ +} + +#define portMEMORY_BARRIER() vPortMemoryBarrier() + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/Renesas/RX600v2/readme.txt b/portable/Renesas/RX600v2/readme.txt new file mode 100644 index 000000000..8dbc983fd --- /dev/null +++ b/portable/Renesas/RX600v2/readme.txt @@ -0,0 +1,71 @@ +The following table shows which port is recommended to be used. + + +RX MCU Group CPU FPU FPU Port Layer + Core (Single (Double CC-RX GNURX ICCRX (*6) + Type Precision) Precision) + +RX110 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX111 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX113 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX130 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX13T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 + +RX210 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX21A RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX220 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX230,RX231 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23E-A RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23W RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24U RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 + +RX610 RXv1 Yes --- N/A (*4) N/A (*4) N/A (*4) +RX62N,RX621 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX630 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX634 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63N,RX631 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX64M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX65N,RX651 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX66N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX62T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX62G RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX66T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +RX71M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX72M RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +Notes: + +*1: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is not used, please define configSETUP_TICK_INTERRUPT() (in FreeRTOSConfig.h) and provide +the configuration function. Please be aware that port.c is hard coded to use CMT0 though it seems to be +configured to use any CMTn according to the definition of configTICK_VECTOR (in FreeRTOSConfig.h). + +*2: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is used, please modify port.c for the configuration. Please be aware that port.c is +hard coded to use CMT0 though it seems to be configured to use any CMTn according to the definition of +configTICK_VECTOR (in FreeRTOSConfig.h). + +*3: RX100 ports are also available. + +*4: RX600 ports use MVTIPL instruction but RX610 MCUs don't support this instruction. + +*5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h. + +#define configUSE_TASK_DPFPU_SUPPORT 0 + +*6: PriorityDefinitions.h has to be provided for port_asm.s in case of other than RX700v3_DPFPU port. +It contains two definitions of interrupt priority like the following. + +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + + +For more information about Renesas RX MCUs, please visit the following URL: + +https://www.renesas.com/products/microcontrollers-microprocessors/rx.html diff --git a/portable/Renesas/RX700v3_DPFPU/port.c b/portable/Renesas/RX700v3_DPFPU/port.c new file mode 100644 index 000000000..6fec50425 --- /dev/null +++ b/portable/Renesas/RX700v3_DPFPU/port.c @@ -0,0 +1,591 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the RXv3 DPFPU port. +*----------------------------------------------------------*/ + +#warning Testing for DFPU support in this port is not yet complete + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Library includes. */ +#include "string.h" + +/* Hardware specifics. */ +#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 ) + + #include "platform.h" + +#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + + #include "iodefine.h" + +#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */ + +/*-----------------------------------------------------------*/ + +/* Tasks should start with interrupts enabled and in Supervisor mode, therefore + * PSW is set with U and I set, and PM and IPL clear. */ +#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) +#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 ) +#define portINITIAL_DPSW ( ( StackType_t ) 0x00000100 ) +#define portINITIAL_DCMR ( ( StackType_t ) 0x00000000 ) +#define portINITIAL_DECNT ( ( StackType_t ) 0x00000001 ) + +/* Tasks are not created with a DPFPU context, but can be given a DPFPU context + * after they have been created. A variable is stored as part of the tasks context + * that holds portNO_DPFPU_CONTEXT if the task does not have a DPFPU context, or + * any other value if the task does have a DPFPU context. */ +#define portNO_DPFPU_CONTEXT ( ( StackType_t ) 0 ) +#define portHAS_DPFPU_CONTEXT ( ( StackType_t ) 1 ) + +/* The space on the stack required to hold the DPFPU data registers. This is 16 + * 64-bit registers. */ +#define portDPFPU_DATA_REGISTER_WORDS ( 16 * 2 ) + +/*-----------------------------------------------------------*/ + +/* The following lines are to ensure vSoftwareInterruptEntry can be referenced, + * and therefore installed in the vector table, when the FreeRTOS code is built + * as a library. */ +extern BaseType_t vSoftwareInterruptEntry; +const BaseType_t * p_vSoftwareInterruptEntry = &vSoftwareInterruptEntry; + +/*-----------------------------------------------------------*/ + +/* + * Function to start the first task executing - written in asm code as direct + * access to registers is required. + */ +static void prvStartFirstTask( void ); + +/* + * Software interrupt handler. Performs the actual context switch (saving and + * restoring of registers). Written in asm code as direct register access is + * required. + */ +static void prvYieldHandler( void ); + +/* + * The entry point for the software interrupt handler. This is the function + * that calls the inline asm function prvYieldHandler(). It is installed in + * the vector table, but the code that installs it is in prvYieldHandler rather + * than using a #pragma. + */ +void vSoftwareInterruptISR( void ); + +/* + * The tick ISR handler. The peripheral used is configured by the application + * via a hook/callback function. + */ +void vTickISR( void ); + +/*-----------------------------------------------------------*/ + +/* Saved as part of the task context. If ulPortTaskHasDPFPUContext is non-zero + * then a DPFPU context must be saved and restored for the task. */ +#if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) + + StackType_t ulPortTaskHasDPFPUContext = portNO_DPFPU_CONTEXT; + +#endif /* configUSE_TASK_DPFPU_SUPPORT */ + +/* This is accessed by the inline assembler functions so is file scope for + * convenience. */ +extern void * pxCurrentTCB; +extern void vTaskSwitchContext( void ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* R0 is not included as it is the stack pointer. */ + + *pxTopOfStack = 0x00; + pxTopOfStack--; + *pxTopOfStack = portINITIAL_PSW; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; + + /* When debugging it can be useful if every register is set to a known + * value. Otherwise code space can be saved by just setting the registers + * that need to be set. */ + #ifdef USE_FULL_REGISTER_INITIALISATION + { + pxTopOfStack--; + *pxTopOfStack = 0xffffffff; /* r15. */ + pxTopOfStack--; + *pxTopOfStack = 0xeeeeeeee; + pxTopOfStack--; + *pxTopOfStack = 0xdddddddd; + pxTopOfStack--; + *pxTopOfStack = 0xcccccccc; + pxTopOfStack--; + *pxTopOfStack = 0xbbbbbbbb; + pxTopOfStack--; + *pxTopOfStack = 0xaaaaaaaa; + pxTopOfStack--; + *pxTopOfStack = 0x99999999; + pxTopOfStack--; + *pxTopOfStack = 0x88888888; + pxTopOfStack--; + *pxTopOfStack = 0x77777777; + pxTopOfStack--; + *pxTopOfStack = 0x66666666; + pxTopOfStack--; + *pxTopOfStack = 0x55555555; + pxTopOfStack--; + *pxTopOfStack = 0x44444444; + pxTopOfStack--; + *pxTopOfStack = 0x33333333; + pxTopOfStack--; + *pxTopOfStack = 0x22222222; + pxTopOfStack--; + } + #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ + { + pxTopOfStack -= 15; + } + #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */ + + *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_FPSW; + pxTopOfStack--; + *pxTopOfStack = 0x11111111; /* Accumulator 1. */ + pxTopOfStack--; + *pxTopOfStack = 0x22222222; /* Accumulator 1. */ + pxTopOfStack--; + *pxTopOfStack = 0x33333333; /* Accumulator 1. */ + pxTopOfStack--; + *pxTopOfStack = 0x44444444; /* Accumulator 0. */ + pxTopOfStack--; + *pxTopOfStack = 0x55555555; /* Accumulator 0. */ + pxTopOfStack--; + *pxTopOfStack = 0x66666666; /* Accumulator 0. */ + + #if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) + { + /* The task will start without a DPFPU context. A task that + * uses the DPFPU hardware must call vPortTaskUsesDPFPU() before + * executing any floating point instructions. */ + pxTopOfStack--; + *pxTopOfStack = portNO_DPFPU_CONTEXT; + } + #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 ) + { + /* The task will start with a DPFPU context. Leave enough + * space for the registers - and ensure they are initialised if desired. */ + #ifdef USE_FULL_REGISTER_INITIALISATION + { + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 1515.1515; /* DR15. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 1414.1414; /* DR14. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 1313.1313; /* DR13. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 1212.1212; /* DR12. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 1111.1111; /* DR11. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 1010.1010; /* DR10. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 909.0909; /* DR9. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 808.0808; /* DR8. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 707.0707; /* DR7. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 606.0606; /* DR6. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 505.0505; /* DR5. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 404.0404; /* DR4. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 303.0303; /* DR3. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 202.0202; /* DR2. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 101.0101; /* DR1. */ + pxTopOfStack -= 2; + *(double *)pxTopOfStack = 9876.54321;/* DR0. */ + } + #else /* ifdef USE_FULL_REGISTER_INITIALISATION */ + { + pxTopOfStack -= portDPFPU_DATA_REGISTER_WORDS; + memset( pxTopOfStack, 0x00, portDPFPU_DATA_REGISTER_WORDS * sizeof( StackType_t ) ); + } + #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_DECNT; /* DECNT. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_DCMR; /* DCMR. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_DPSW; /* DPSW. */ + } + #elif ( configUSE_TASK_DPFPU_SUPPORT == 0 ) + { + /* Omit DPFPU support. */ + } + #else /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */ + { + #error Invalid configUSE_TASK_DPFPU_SUPPORT setting - configUSE_TASK_DPFPU_SUPPORT must be set to 0, 1, 2, or left undefined. + } + #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) + + void vPortTaskUsesDPFPU( void ) + { + /* A task is registering the fact that it needs a DPFPU context. Set the + * DPFPU flag (which is saved as part of the task context). */ + ulPortTaskHasDPFPUContext = portHAS_DPFPU_CONTEXT; + } + +#endif /* configUSE_TASK_DPFPU_SUPPORT */ +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + extern void vApplicationSetupTimerInterrupt( void ); + + /* Use pxCurrentTCB just so it does not get optimised away. */ + if( pxCurrentTCB != NULL ) + { + /* Call an application function to set up the timer that will generate the + * tick interrupt. This way the application can decide which peripheral to + * use. A demo application is provided to show a suitable example. */ + vApplicationSetupTimerInterrupt(); + + /* Enable the software interrupt. */ + _IEN( _ICU_SWINT ) = 1; + + /* Ensure the software interrupt is clear. */ + _IR( _ICU_SWINT ) = 0; + + /* Ensure the software interrupt is set to the kernel priority. */ + _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the first task. */ + prvStartFirstTask(); + } + + /* Just to make sure the function is not optimised away. */ + ( void ) vSoftwareInterruptISR(); + + /* Should not get here. */ + return pdFAIL; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( pxCurrentTCB == NULL ); + + /* The following line is just to prevent the symbol getting optimised away. */ + ( void ) vTaskSwitchContext(); +} +/*-----------------------------------------------------------*/ + +#pragma inline_asm prvStartFirstTask +static void prvStartFirstTask( void ) +{ +#ifndef __CDT_PARSER__ + + /* When starting the scheduler there is nothing that needs moving to the + * interrupt stack because the function is not called from an interrupt. + * Just ensure the current stack is the user stack. */ + SETPSW U + + + /* Obtain the location of the stack associated with which ever task + * pxCurrentTCB is currently pointing to. */ + MOV.L # _pxCurrentTCB, R15 + MOV.L [ R15 ], R15 + MOV.L [ R15 ], R0 + + + /* Restore the registers from the stack of the task pointed to by + * pxCurrentTCB. */ + + #if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) + + /* The restored ulPortTaskHasDPFPUContext is to be zero here. + * So, it is never necessary to restore the DPFPU context here. */ + POP R15 + MOV.L # _ulPortTaskHasDPFPUContext, R14 + MOV.L R15, [ R14 ] + + #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 ) + + /* Restore the DPFPU context. */ + DPOPM.L DPSW-DECNT + DPOPM.D DR0-DR15 + + #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */ + + POP R15 + + /* Accumulator low 32 bits. */ + MVTACLO R15, A0 + POP R15 + + /* Accumulator high 32 bits. */ + MVTACHI R15, A0 + POP R15 + + /* Accumulator guard. */ + MVTACGU R15, A0 + POP R15 + + /* Accumulator low 32 bits. */ + MVTACLO R15, A1 + POP R15 + + /* Accumulator high 32 bits. */ + MVTACHI R15, A1 + POP R15 + + /* Accumulator guard. */ + MVTACGU R15, A1 + POP R15 + + /* Floating point status word. */ + MVTC R15, FPSW + + /* R1 to R15 - R0 is not included as it is the SP. */ + POPM R1-R15 + + /* This pops the remaining registers. */ + RTE + NOP + NOP + +#endif /* ifndef __CDT_PARSER__ */ +} +/*-----------------------------------------------------------*/ + +void vSoftwareInterruptISR( void ) +{ + prvYieldHandler(); +} +/*-----------------------------------------------------------*/ + +#pragma inline_asm prvYieldHandler +static void prvYieldHandler( void ) +{ +#ifndef __CDT_PARSER__ + + /* Re-enable interrupts. */ + SETPSW I + + + /* Move the data that was automatically pushed onto the interrupt stack when + * the interrupt occurred from the interrupt stack to the user stack. + * + * R15 is saved before it is clobbered. */ + PUSH.L R15 + + /* Read the user stack pointer. */ + MVFC USP, R15 + + /* Move the address down to the data being moved. */ + SUB # 12, R15 + MVTC R15, USP + + /* Copy the data across, R15, then PC, then PSW. */ + MOV.L [ R0 ], [ R15 ] + MOV.L 4[ R0 ], 4[ R15 ] + MOV.L 8[ R0 ], 8[ R15 ] + + /* Move the interrupt stack pointer to its new correct position. */ + ADD # 12, R0 + + /* All the rest of the registers are saved directly to the user stack. */ + SETPSW U + + /* Save the rest of the general registers (R15 has been saved already). */ + PUSHM R1-R14 + + /* Save the FPSW and accumulators. */ + MVFC FPSW, R15 + PUSH.L R15 + MVFACGU # 0, A1, R15 + PUSH.L R15 + MVFACHI # 0, A1, R15 + PUSH.L R15 + MVFACLO # 0, A1, R15 /* Low order word. */ + PUSH.L R15 + MVFACGU # 0, A0, R15 + PUSH.L R15 + MVFACHI # 0, A0, R15 + PUSH.L R15 + MVFACLO # 0, A0, R15 /* Low order word. */ + PUSH.L R15 + + #if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) + + /* Does the task have a DPFPU context that needs saving? If + * ulPortTaskHasDPFPUContext is 0 then no. */ + MOV.L # _ulPortTaskHasDPFPUContext, R15 + MOV.L [ R15 ], R15 + CMP # 0, R15 + + /* Save the DPFPU context, if any. */ + BEQ.B ?+ + DPUSHM.D DR0-DR15 + DPUSHM.L DPSW-DECNT + ?: + + /* Save ulPortTaskHasDPFPUContext itself. */ + PUSH.L R15 + + #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 ) + + /* Save the DPFPU context, always. */ + DPUSHM.D DR0-DR15 + DPUSHM.L DPSW-DECNT + + #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */ + + + /* Save the stack pointer to the TCB. */ + MOV.L # _pxCurrentTCB, R15 + MOV.L [ R15 ], R15 + MOV.L R0, [ R15 ] + + + /* Ensure the interrupt mask is set to the syscall priority while the kernel + * structures are being accessed. */ + MVTIPL # configMAX_SYSCALL_INTERRUPT_PRIORITY + + /* Select the next task to run. */ + BSR.A _vTaskSwitchContext + + /* Reset the interrupt mask as no more data structure access is required. */ + MVTIPL # configKERNEL_INTERRUPT_PRIORITY + + + /* Load the stack pointer of the task that is now selected as the Running + * state task from its TCB. */ + MOV.L # _pxCurrentTCB, R15 + MOV.L [ R15 ], R15 + MOV.L [ R15 ], R0 + + + /* Restore the context of the new task. The PSW (Program Status Word) and + * PC will be popped by the RTE instruction. */ + + #if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) + + /* Is there a DPFPU context to restore? If the restored + * ulPortTaskHasDPFPUContext is zero then no. */ + POP R15 + MOV.L # _ulPortTaskHasDPFPUContext, R14 + MOV.L R15, [ R14 ] + CMP # 0, R15 + + /* Restore the DPFPU context, if any. */ + BEQ.B ?+ + DPOPM.L DPSW-DECNT + DPOPM.D DR0-DR15 + ?: + + #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 ) + + /* Restore the DPFPU context, always. */ + DPOPM.L DPSW-DECNT + DPOPM.D DR0-DR15 + + #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */ + + POP R15 + + /* Accumulator low 32 bits. */ + MVTACLO R15, A0 + POP R15 + + /* Accumulator high 32 bits. */ + MVTACHI R15, A0 + POP R15 + + /* Accumulator guard. */ + MVTACGU R15, A0 + POP R15 + + /* Accumulator low 32 bits. */ + MVTACLO R15, A1 + POP R15 + + /* Accumulator high 32 bits. */ + MVTACHI R15, A1 + POP R15 + + /* Accumulator guard. */ + MVTACGU R15, A1 + POP R15 + MVTC R15, FPSW + POPM R1-R15 + RTE + NOP + NOP + +#endif /* ifndef __CDT_PARSER__ */ +} +/*-----------------------------------------------------------*/ + +#pragma interrupt ( vTickISR( vect = _VECT( configTICK_VECTOR ), enable ) ) +void vTickISR( void ) +{ + /* Increment the tick, and perform any processing the new tick value + * necessitates. Ensure IPL is at the max syscall value first. */ + set_ipl( configMAX_SYSCALL_INTERRUPT_PRIORITY ); + { + if( xTaskIncrementTick() != pdFALSE ) + { + taskYIELD(); + } + } + set_ipl( configKERNEL_INTERRUPT_PRIORITY ); +} +/*-----------------------------------------------------------*/ diff --git a/portable/Renesas/RX700v3_DPFPU/port_asm.src b/portable/Renesas/RX700v3_DPFPU/port_asm.src new file mode 100644 index 000000000..8d5200b6c --- /dev/null +++ b/portable/Renesas/RX700v3_DPFPU/port_asm.src @@ -0,0 +1,39 @@ +;/* +; * FreeRTOS Kernel +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + .GLB _vSoftwareInterruptISR + .GLB _vSoftwareInterruptEntry + + .SECTION P,CODE + +_vSoftwareInterruptEntry: + + BRA _vSoftwareInterruptISR + + .RVECTOR 27, _vSoftwareInterruptEntry + + .END diff --git a/portable/Renesas/RX700v3_DPFPU/portmacro.h b/portable/Renesas/RX700v3_DPFPU/portmacro.h new file mode 100644 index 000000000..e0c6b1df1 --- /dev/null +++ b/portable/Renesas/RX700v3_DPFPU/portmacro.h @@ -0,0 +1,199 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H + #define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/* Hardware specifics. */ + #include + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* When the FIT configurator or the Smart Configurator is used, platform.h has to be + * used. */ + #ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H + #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0 + #endif + +/* If configUSE_TASK_DPFPU_SUPPORT is set to 1 (or undefined) then each task will + * be created without a DPFPU context, and a task must call vTaskUsesDPFPU() before + * making use of any DPFPU registers. If configUSE_TASK_DPFPU_SUPPORT is set to 2 then + * tasks are created with a DPFPU context by default, and calling vTaskUsesDPFPU() has + * no effect. If configUSE_TASK_DPFPU_SUPPORT is set to 0 then tasks never take care + * of any DPFPU context (even if DPFPU registers are used). */ + #ifndef configUSE_TASK_DPFPU_SUPPORT + #define configUSE_TASK_DPFPU_SUPPORT 1 + #endif + +/*-----------------------------------------------------------*/ + +/* Type definitions - these are a bit legacy and not really used now, other than + * portSTACK_TYPE and portBASE_TYPE. */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. + #endif + +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ + #define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ + #define portSTACK_GROWTH -1 + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portNOP() nop() + +/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;" + * where portITU_SWINTR is the location of the software interrupt register + * (0x000872E0). Don't rely on the assembler to select a register, so instead + * save and restore clobbered registers manually. */ + #pragma inline_asm vPortYield + static void vPortYield( void ) + { + #ifndef __CDT_PARSER__ + /* Save clobbered register - may not actually be necessary if inline asm + * functions are considered to use the same rules as function calls by the + * compiler. */ + PUSH.L R5 + /* Set ITU SWINTR. */ + MOV.L # 000872E0H, R5 + MOV.B # 1, [ R5 ] + /* Read back to ensure the value is taken before proceeding. */ + CMP [ R5 ].UB, R5 + /* Restore clobbered register to its previous value. */ + POP R5 + #endif + } + + #define portYIELD() vPortYield() + #define portYIELD_FROM_ISR( x ) do { if( ( x ) != pdFALSE ) portYIELD(); } while( 0 ) + +/* These macros should not be called directly, but through the + * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is + * performed if configASSERT() is defined to ensure an assertion handler does not + * inadvertently attempt to lower the IPL when the call to assert was triggered + * because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY + * when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API + * functions are those that end in FromISR. FreeRTOS maintains a separate + * interrupt API to ensure API function and interrupt entry is as fast and as + * simple as possible. */ + #define portENABLE_INTERRUPTS() set_ipl( ( long ) 0 ) + #if ( configASSERT_DEFINED == 1 ) + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) + #define portDISABLE_INTERRUPTS() if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) + #else + #define portDISABLE_INTERRUPTS() set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) + #endif + +/* Critical nesting counts are stored in the TCB. */ + #define portCRITICAL_NESTING_IN_TCB ( 1 ) + +/* The critical nesting functions defined within tasks.c. */ + extern void vTaskEnterCritical( void ); + extern void vTaskExitCritical( void ); + #define portENTER_CRITICAL() vTaskEnterCritical() + #define portEXIT_CRITICAL() vTaskExitCritical() + +/* As this port allows interrupt nesting... */ + #define portSET_INTERRUPT_MASK_FROM_ISR() ( UBaseType_t ) get_ipl(); set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) set_ipl( ( long ) uxSavedInterruptStatus ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/*-----------------------------------------------------------*/ + +/* If configUSE_TASK_DPFPU_SUPPORT is set to 1 (or left undefined) then tasks are + * created without a DPFPU context and must call vPortTaskUsesDPFPU() to give + * themselves a DPFPU context before using any DPFPU instructions. If + * configUSE_TASK_DPFPU_SUPPORT is set to 2 then all tasks will have a DPFPU context + * by default. */ + #if( configUSE_TASK_DPFPU_SUPPORT == 1 ) + void vPortTaskUsesDPFPU( void ); + #else +/* Each task has a DPFPU context already, so define this function away to + * nothing to prevent it being called accidentally. */ + #define vPortTaskUsesDPFPU() + #endif + #define portTASK_USES_DPFPU() vPortTaskUsesDPFPU() + +/* Definition to allow compatibility with existing FreeRTOS Demo using flop.c. */ + #define portTASK_USES_FLOATING_POINT() vPortTaskUsesDPFPU() + +#pragma inline_asm vPortMemoryBarrier +static void vPortMemoryBarrier( void ) +{ +} + +#define portMEMORY_BARRIER() vPortMemoryBarrier() + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/Renesas/RX700v3_DPFPU/readme.txt b/portable/Renesas/RX700v3_DPFPU/readme.txt new file mode 100644 index 000000000..8dbc983fd --- /dev/null +++ b/portable/Renesas/RX700v3_DPFPU/readme.txt @@ -0,0 +1,71 @@ +The following table shows which port is recommended to be used. + + +RX MCU Group CPU FPU FPU Port Layer + Core (Single (Double CC-RX GNURX ICCRX (*6) + Type Precision) Precision) + +RX110 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX111 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX113 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX130 RXv1 No --- Renesas/RX100 (*1,*2) GCC/RX100 (*1,*2) IAR/RX100 (*1,*2) +RX13T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 + +RX210 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX21A RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX220 RXv1 No --- Renesas/RX200 (*3) N/A (*3) N/A (*3) +RX230,RX231 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23E-A RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23W RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX23T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24T RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX24U RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 + +RX610 RXv1 Yes --- N/A (*4) N/A (*4) N/A (*4) +RX62N,RX621 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX630 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX634 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63N,RX631 RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX64M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX65N,RX651 RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX66N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX62T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX62G RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX63T RXv1 Yes --- Renesas/RX600 GCC/RX600 IAR/RX600 +RX66T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +RX71M RXv2 Yes --- Renesas/RX600v2 GCC/RX600v2 IAR/RXv2 +RX72M RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72N RXv3 Yes Yes Renesas/RX700v3_DPFPU GCC/RX700v3_DPFPU IAR/RX700v3_DPFPU +RX72T RXv3 Yes No Renesas/RX600v2 (*5) GCC/RX600v2 (*5) IAR/RXv2 (*5) + +Notes: + +*1: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is not used, please define configSETUP_TICK_INTERRUPT() (in FreeRTOSConfig.h) and provide +the configuration function. Please be aware that port.c is hard coded to use CMT0 though it seems to be +configured to use any CMTn according to the definition of configTICK_VECTOR (in FreeRTOSConfig.h). + +*2: If the application writer wants to use their own tick interrupt configuration when tickless idle +functionality is used, please modify port.c for the configuration. Please be aware that port.c is +hard coded to use CMT0 though it seems to be configured to use any CMTn according to the definition of +configTICK_VECTOR (in FreeRTOSConfig.h). + +*3: RX100 ports are also available. + +*4: RX600 ports use MVTIPL instruction but RX610 MCUs don't support this instruction. + +*5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h. + +#define configUSE_TASK_DPFPU_SUPPORT 0 + +*6: PriorityDefinitions.h has to be provided for port_asm.s in case of other than RX700v3_DPFPU port. +It contains two definitions of interrupt priority like the following. + +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + + +For more information about Renesas RX MCUs, please visit the following URL: + +https://www.renesas.com/products/microcontrollers-microprocessors/rx.html diff --git a/portable/Renesas/SH2A_FPU/ISR_Support.inc b/portable/Renesas/SH2A_FPU/ISR_Support.inc new file mode 100644 index 000000000..33ad2de68 --- /dev/null +++ b/portable/Renesas/SH2A_FPU/ISR_Support.inc @@ -0,0 +1,75 @@ +;/* +; * FreeRTOS Kernel +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + .macro portSAVE_CONTEXT + + ; Save r0 to r14 and pr. + movml.l r15, @-r15 + + ; Save mac1, mach and gbr + sts.l macl, @-r15 + sts.l mach, @-r15 + stc.l gbr, @-r15 + + ; Get the address of pxCurrentTCB + mov.l #_pxCurrentTCB, r0 + + ; Get the address of pxTopOfStack from the TCB. + mov.l @r0, r0 + + ; Save the stack pointer in pxTopOfStack. + mov.l r15, @r0 + + .endm + +;----------------------------------------------------------- + + .macro portRESTORE_CONTEXT + + ; Get the address of the pxCurrentTCB variable. + mov.l #_pxCurrentTCB, r0 + + ; Get the address of the task stack from pxCurrentTCB. + mov.l @r0, r0 + + ; Get the task stack itself into the stack pointer. + mov.l @r0, r15 + + ; Restore system registers. + ldc.l @r15+, gbr + lds.l @r15+, mach + lds.l @r15+, macl + + ; Restore r0 to r14 and PR + movml.l @r15+, r15 + + ; Pop the SR and PC to jump to the start of the task. + rte + nop + + .endm +;----------------------------------------------------------- diff --git a/portable/Renesas/SH2A_FPU/port.c b/portable/Renesas/SH2A_FPU/port.c new file mode 100644 index 000000000..c14a0a851 --- /dev/null +++ b/portable/Renesas/SH2A_FPU/port.c @@ -0,0 +1,272 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the SH2A port. +*----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Library includes. */ +#include "string.h" + +/*-----------------------------------------------------------*/ + +/* The SR assigned to a newly created task. The only important thing in this + * value is for all interrupts to be enabled. */ +#define portINITIAL_SR ( 0UL ) + +/* Dimensions the array into which the floating point context is saved. + * Allocate enough space for FPR0 to FPR15, FPUL and FPSCR, each of which is 4 + * bytes big. If this number is changed then the 72 in portasm.src also needs + * changing. */ +#define portFLOP_REGISTERS_TO_STORE ( 18 ) +#define portFLOP_STORAGE_SIZE ( portFLOP_REGISTERS_TO_STORE * 4 ) + +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) + #error configSUPPORT_DYNAMIC_ALLOCATION must be 1 to use this port. +#endif + +/*-----------------------------------------------------------*/ + +/* + * The TRAPA handler used to force a context switch. + */ +void vPortYield( void ); + +/* + * Function to start the first task executing - defined in portasm.src. + */ +extern void vPortStartFirstTask( void ); + +/* + * Obtains the current GBR value - defined in portasm.src. + */ +extern uint32_t ulPortGetGBR( void ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Mark the end of the stack - used for debugging only and can be removed. */ + *pxTopOfStack = 0x11111111UL; + pxTopOfStack--; + *pxTopOfStack = 0x22222222UL; + pxTopOfStack--; + *pxTopOfStack = 0x33333333UL; + pxTopOfStack--; + + /* SR. */ + *pxTopOfStack = portINITIAL_SR; + pxTopOfStack--; + + /* PC. */ + *pxTopOfStack = ( uint32_t ) pxCode; + pxTopOfStack--; + + /* PR. */ + *pxTopOfStack = 15; + pxTopOfStack--; + + /* 14. */ + *pxTopOfStack = 14; + pxTopOfStack--; + + /* R13. */ + *pxTopOfStack = 13; + pxTopOfStack--; + + /* R12. */ + *pxTopOfStack = 12; + pxTopOfStack--; + + /* R11. */ + *pxTopOfStack = 11; + pxTopOfStack--; + + /* R10. */ + *pxTopOfStack = 10; + pxTopOfStack--; + + /* R9. */ + *pxTopOfStack = 9; + pxTopOfStack--; + + /* R8. */ + *pxTopOfStack = 8; + pxTopOfStack--; + + /* R7. */ + *pxTopOfStack = 7; + pxTopOfStack--; + + /* R6. */ + *pxTopOfStack = 6; + pxTopOfStack--; + + /* R5. */ + *pxTopOfStack = 5; + pxTopOfStack--; + + /* R4. */ + *pxTopOfStack = ( uint32_t ) pvParameters; + pxTopOfStack--; + + /* R3. */ + *pxTopOfStack = 3; + pxTopOfStack--; + + /* R2. */ + *pxTopOfStack = 2; + pxTopOfStack--; + + /* R1. */ + *pxTopOfStack = 1; + pxTopOfStack--; + + /* R0 */ + *pxTopOfStack = 0; + pxTopOfStack--; + + /* MACL. */ + *pxTopOfStack = 16; + pxTopOfStack--; + + /* MACH. */ + *pxTopOfStack = 17; + pxTopOfStack--; + + /* GBR. */ + *pxTopOfStack = ulPortGetGBR(); + + /* GBR = global base register. + * VBR = vector base register. + * TBR = jump table base register. + * R15 is the stack pointer. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + extern void vApplicationSetupTimerInterrupt( void ); + + /* Call an application function to set up the timer that will generate the + * tick interrupt. This way the application can decide which peripheral to + * use. A demo application is provided to show a suitable example. */ + vApplicationSetupTimerInterrupt(); + + /* Start the first task. This will only restore the standard registers and + * not the flop registers. This does not really matter though because the only + * flop register that is initialised to a particular value is fpscr, and it is + * only initialised to the current value, which will still be the current value + * when the first task starts executing. */ + trapa( portSTART_SCHEDULER_TRAP_NO ); + + /* Should not get here. */ + return pdFAIL; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented as there is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +void vPortYield( void ) +{ + int32_t lInterruptMask; + + /* Ensure the yield trap runs at the same priority as the other interrupts + * that can cause a context switch. */ + lInterruptMask = get_imask(); + + /* taskYIELD() can only be called from a task, not an interrupt, so the + * current interrupt mask can only be 0 or portKERNEL_INTERRUPT_PRIORITY and + * the mask can be set without risk of accidentally lowering the mask value. */ + set_imask( portKERNEL_INTERRUPT_PRIORITY ); + + trapa( portYIELD_TRAP_NO ); + + /* Restore the interrupt mask to whatever it was previously (when the + * function was entered). */ + set_imask( ( int ) lInterruptMask ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortUsesFloatingPoint( TaskHandle_t xTask ) +{ + uint32_t * pulFlopBuffer; + BaseType_t xReturn; + extern void * volatile pxCurrentTCB; + + /* This function tells the kernel that the task referenced by xTask is + * going to use the floating point registers and therefore requires the + * floating point registers saved as part of its context. */ + + /* Passing NULL as xTask is used to indicate that the calling task is the + * subject task - so pxCurrentTCB is the task handle. */ + if( xTask == NULL ) + { + xTask = ( TaskHandle_t ) pxCurrentTCB; + } + + /* Allocate a buffer large enough to hold all the flop registers. */ + pulFlopBuffer = ( uint32_t * ) pvPortMalloc( portFLOP_STORAGE_SIZE ); + + if( pulFlopBuffer != NULL ) + { + /* Start with the registers in a benign state. */ + memset( ( void * ) pulFlopBuffer, 0x00, portFLOP_STORAGE_SIZE ); + + /* The first thing to get saved in the buffer is the FPSCR value - + * initialise this to the current FPSCR value. */ + *pulFlopBuffer = get_fpscr(); + + /* Use the task tag to point to the flop buffer. Pass pointer to just + * above the buffer because the flop save routine uses a pre-decrement. */ + vTaskSetApplicationTaskTag( xTask, ( void * ) ( pulFlopBuffer + portFLOP_REGISTERS_TO_STORE ) ); + xReturn = pdPASS; + } + else + { + xReturn = pdFAIL; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ diff --git a/portable/Renesas/SH2A_FPU/portasm.src b/portable/Renesas/SH2A_FPU/portasm.src new file mode 100644 index 000000000..4cf7225aa --- /dev/null +++ b/portable/Renesas/SH2A_FPU/portasm.src @@ -0,0 +1,150 @@ +;/* +; * FreeRTOS Kernel +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + + .import _pxCurrentTCB + .import _vTaskSwitchContext + .import _xTaskIncrementTick + + .export _vPortStartFirstTask + .export _ulPortGetGBR + .export _vPortYieldHandler + .export _vPortPreemptiveTick + .export _vPortCooperativeTick + .export _vPortSaveFlopRegisters + .export _vPortRestoreFlopRegisters + + .section P + + .INCLUDE "ISR_Support.inc" + +_vPortStartFirstTask: + + portRESTORE_CONTEXT + +;----------------------------------------------------------- + +_vPortYieldHandler: + + portSAVE_CONTEXT + + mov.l #_vTaskSwitchContext, r0 + jsr @r0 + nop + + portRESTORE_CONTEXT + +;----------------------------------------------------------- + +_vPortPreemptiveTick + + portSAVE_CONTEXT + + mov.l #_xTaskIncrementTick, r0 + jsr @r0 + nop + + mov.l #_vTaskSwitchContext, r0 + jsr @r0 + nop + + portRESTORE_CONTEXT + +;----------------------------------------------------------- + +_vPortCooperativeTick + + portSAVE_CONTEXT + + mov.l #_xTaskIncrementTick, r0 + jsr @r0 + nop + + portRESTORE_CONTEXT + +;----------------------------------------------------------- + +_ulPortGetGBR: + + stc.l gbr, r0 + rts + nop + +;----------------------------------------------------------- + +_vPortSaveFlopRegisters: + + fmov.s fr0, @-r4 + fmov.s fr1, @-r4 + fmov.s fr2, @-r4 + fmov.s fr3, @-r4 + fmov.s fr4, @-r4 + fmov.s fr5, @-r4 + fmov.s fr6, @-r4 + fmov.s fr7, @-r4 + fmov.s fr8, @-r4 + fmov.s fr9, @-r4 + fmov.s fr10, @-r4 + fmov.s fr11, @-r4 + fmov.s fr12, @-r4 + fmov.s fr13, @-r4 + fmov.s fr14, @-r4 + fmov.s fr15, @-r4 + sts.l fpul, @-r4 + sts.l fpscr, @-r4 + + rts + nop + +;----------------------------------------------------------- + +_vPortRestoreFlopRegisters: + + add.l #-72, r4 + lds.l @r4+, fpscr + lds.l @r4+, fpul + fmov.s @r4+, fr15 + fmov.s @r4+, fr14 + fmov.s @r4+, fr13 + fmov.s @r4+, fr12 + fmov.s @r4+, fr11 + fmov.s @r4+, fr10 + fmov.s @r4+, fr9 + fmov.s @r4+, fr8 + fmov.s @r4+, fr7 + fmov.s @r4+, fr6 + fmov.s @r4+, fr5 + fmov.s @r4+, fr4 + fmov.s @r4+, fr3 + fmov.s @r4+, fr2 + fmov.s @r4+, fr1 + fmov.s @r4+, fr0 + + rts + nop + + .end diff --git a/portable/Renesas/SH2A_FPU/portmacro.h b/portable/Renesas/SH2A_FPU/portmacro.h new file mode 100644 index 000000000..2229fd3f6 --- /dev/null +++ b/portable/Renesas/SH2A_FPU/portmacro.h @@ -0,0 +1,143 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#include + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions - these are a bit legacy and not really used now, other than + * portSTACK_TYPE and portBASE_TYPE. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 8 +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() nop() +#define portSTART_SCHEDULER_TRAP_NO ( 32 ) +#define portYIELD_TRAP_NO ( 33 ) +#define portKERNEL_INTERRUPT_PRIORITY ( 1 ) + +void vPortYield( void ); +#define portYIELD() vPortYield() + +extern void vTaskSwitchContext( void ); +#define portYIELD_FROM_ISR( x ) do { if( x != pdFALSE ) vTaskSwitchContext( ); } while( 0 ) + +/* + * This function tells the kernel that the task referenced by xTask is going to + * use the floating point registers and therefore requires the floating point + * registers saved as part of its context. + */ +BaseType_t xPortUsesFloatingPoint( void * xTask ); + +/* + * The flop save and restore functions are defined in portasm.src and called by + * the trace "task switched in" and "trace task switched out" macros. + */ +void vPortSaveFlopRegisters( void * pulBuffer ); +void vPortRestoreFlopRegisters( void * pulBuffer ); + +/* + * pxTaskTag is used to point to the buffer into which the floating point + * context should be saved. If pxTaskTag is NULL then the task does not use + * a floating point context. + */ +#define traceTASK_SWITCHED_OUT() do { if( pxCurrentTCB->pxTaskTag != NULL ) vPortSaveFlopRegisters( pxCurrentTCB->pxTaskTag ); } while( 0 ) +#define traceTASK_SWITCHED_IN() do { if( pxCurrentTCB->pxTaskTag != NULL ) vPortRestoreFlopRegisters( pxCurrentTCB->pxTaskTag ); } while( 0 ) + +/* + * These macros should be called directly, but through the taskENTER_CRITICAL() + * and taskEXIT_CRITICAL() macros. + */ +#define portENABLE_INTERRUPTS() set_imask( 0x00 ) +#define portDISABLE_INTERRUPTS() set_imask( portKERNEL_INTERRUPT_PRIORITY ) + +/* Critical nesting counts are stored in the TCB. */ +#define portCRITICAL_NESTING_IN_TCB ( 1 ) + +/* The critical nesting functions defined within tasks.c. */ +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); +#define portENTER_CRITICAL() vTaskEnterCritical(); +#define portEXIT_CRITICAL() vTaskExitCritical(); + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/Rowley/ARM7/readme.txt b/portable/Rowley/ARM7/readme.txt new file mode 100644 index 000000000..0ac88a609 --- /dev/null +++ b/portable/Rowley/ARM7/readme.txt @@ -0,0 +1 @@ +The Rowley ARM7 demo uses the GCC ARM7 port files. diff --git a/portable/Rowley/MSP430F449/port.c b/portable/Rowley/MSP430F449/port.c new file mode 100644 index 000000000..392dadbdd --- /dev/null +++ b/portable/Rowley/MSP430F449/port.c @@ -0,0 +1,173 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the MSP430 port. + *----------------------------------------------------------*/ + +/* Constants required for hardware setup. The tick ISR runs off the ACLK, +not the MCLK. */ +#define portACLK_FREQUENCY_HZ ( ( TickType_t ) 32768 ) +#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 ) +#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x08 ) + +/* We require the address of the pxCurrentTCB variable, but don't want to know +any details of its type. */ +typedef void TCB_t; +extern volatile TCB_t * volatile pxCurrentTCB; + +/* Each task maintains a count of the critical section nesting depth. Each +time a critical section is entered the count is incremented. Each time a +critical section is exited the count is decremented - with interrupts only +being re-enabled if the count is zero. + +usCriticalNesting will get set to zero when the scheduler starts, but must +not be initialised to zero as this will cause problems during the startup +sequence. */ +volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING; +/*-----------------------------------------------------------*/ + + +/* + * Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but + * could have alternatively used the watchdog timer or timer 1. + */ +void prvSetupTimerInterrupt( void ); +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See the header file portable.h. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* + Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging and can be included if required. + + *pxTopOfStack = ( StackType_t ) 0x1111; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x2222; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x3333; + pxTopOfStack--; + */ + + /* The msp430 automatically pushes the PC then SR onto the stack before + executing an ISR. We want the stack to look just as if this has happened + so place a pointer to the start of the task on the stack first - followed + by the flags we want the task to use when it starts up. */ + *pxTopOfStack = ( StackType_t ) pxCode; + pxTopOfStack--; + *pxTopOfStack = portFLAGS_INT_ENABLED; + pxTopOfStack--; + + /* Next the general purpose registers. */ + *pxTopOfStack = ( StackType_t ) 0x4444; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x5555; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x6666; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x7777; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x8888; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x9999; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xaaaa; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xbbbb; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xcccc; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xdddd; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xeeee; + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R15. */ + *pxTopOfStack = ( StackType_t ) pvParameters; + pxTopOfStack--; + + /* A variable is used to keep track of the critical section nesting. + This variable has to be stored as part of the task context and is + initially set to zero. */ + *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING; + + /* Return a pointer to the top of the stack we have generated so this can + be stored in the task control block for the task. */ + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the MSP430 port will get stopped. If required simply + disable the tick interrupt here. */ +} +/*-----------------------------------------------------------*/ + +/* + * Hardware initialisation to generate the RTOS tick. This uses timer 0 + * but could alternatively use the watchdog timer or timer 1. + */ +void prvSetupTimerInterrupt( void ) +{ + /* Ensure the timer is stopped. */ + TACTL = 0; + + /* Run the timer of the ACLK. */ + TACTL = TASSEL_1; + + /* Clear everything to start with. */ + TACTL |= TACLR; + + /* Set the compare match value according to the tick rate we want. */ + TACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ; + + /* Enable the interrupts. */ + TACCTL0 = CCIE; + + /* Start up clean. */ + TACTL |= TACLR; + + /* Up mode. */ + TACTL |= MC_1; +} +/*-----------------------------------------------------------*/ + + + diff --git a/portable/Rowley/MSP430F449/portasm.h b/portable/Rowley/MSP430F449/portasm.h new file mode 100644 index 000000000..18361cce3 --- /dev/null +++ b/portable/Rowley/MSP430F449/portasm.h @@ -0,0 +1,80 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORT_ASM_H +#define PORT_ASM_H + +portSAVE_CONTEXT macro + /* Save the remaining registers. */ + push r4 + push r5 + push r6 + push r7 + push r8 + push r9 + push r10 + push r11 + push r12 + push r13 + push r14 + push r15 + mov.w &_usCriticalNesting, r14 + push r14 + mov.w &_pxCurrentTCB, r12 + mov.w r1, @r12 + endm +/*-----------------------------------------------------------*/ + +portRESTORE_CONTEXT macro + mov.w &_pxCurrentTCB, r12 + mov.w @r12, r1 + pop r15 + mov.w r15, &_usCriticalNesting + pop r15 + pop r14 + pop r13 + pop r12 + pop r11 + pop r10 + pop r9 + pop r8 + pop r7 + pop r6 + pop r5 + pop r4 + + /* The last thing on the stack will be the status register. + Ensure the power down bits are clear ready for the next + time this power down register is popped from the stack. */ + bic.w #0xf0,0(SP) + + reti + endm +/*-----------------------------------------------------------*/ + +#endif diff --git a/portable/Rowley/MSP430F449/portext.asm b/portable/Rowley/MSP430F449/portext.asm new file mode 100644 index 000000000..80cdcef81 --- /dev/null +++ b/portable/Rowley/MSP430F449/portext.asm @@ -0,0 +1,103 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include "FreeRTOSConfig.h" +#include "portasm.h" + + +.CODE + +/* + * The RTOS tick ISR. + * + * If the cooperative scheduler is in use this simply increments the tick + * count. + * + * If the preemptive scheduler is in use a context switch can also occur. + */ +_vTickISR: + portSAVE_CONTEXT + + call #_xTaskIncrementTick + cmp.w #0x00, r15 + jeq _SkipContextSwitch + call #_vTaskSwitchContext +_SkipContextSwitch: + portRESTORE_CONTEXT +/*-----------------------------------------------------------*/ + + +/* + * Manual context switch called by the portYIELD() macro. + */ +_vPortYield:: + + /* Mimic an interrupt by pushing the SR. */ + push SR + + /* Now the SR is stacked we can disable interrupts. */ + dint + + /* Save the context of the current task. */ + portSAVE_CONTEXT + + /* Switch to the highest priority task that is ready to run. */ + call #_vTaskSwitchContext + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT +/*-----------------------------------------------------------*/ + + +/* + * Start off the scheduler by initialising the RTOS tick timer, then restoring + * the context of the first task. + */ +_xPortStartScheduler:: + + /* Setup the hardware to generate the tick. Interrupts are disabled + when this function is called. */ + call #_prvSetupTimerInterrupt + + /* Restore the context of the first task that is going to run. */ + portRESTORE_CONTEXT +/*-----------------------------------------------------------*/ + + + /* Place the tick ISR in the correct vector. */ + .VECTORS + + .KEEP + + ORG TIMERA0_VECTOR + DW _vTickISR + + + + END + diff --git a/portable/Rowley/MSP430F449/portmacro.h b/portable/Rowley/MSP430F449/portmacro.h new file mode 100644 index 000000000..38304fb03 --- /dev/null +++ b/portable/Rowley/MSP430F449/portmacro.h @@ -0,0 +1,134 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE uint16_t +#define portBASE_TYPE short + +typedef portSTACK_TYPE StackType_t; +typedef short BaseType_t; +typedef unsigned short UBaseType_t; + + +#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif + +/*-----------------------------------------------------------*/ + +/* Interrupt control macros. */ +#define portDISABLE_INTERRUPTS() _DINT(); _NOP() +#define portENABLE_INTERRUPTS() _EINT(); +/*-----------------------------------------------------------*/ + +/* Critical section control macros. */ +#define portNO_CRITICAL_SECTION_NESTING ( ( uint16_t ) 0 ) + +#define portENTER_CRITICAL() \ +{ \ +extern volatile uint16_t usCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + \ + /* Now interrupts are disabled usCriticalNesting can be accessed */ \ + /* directly. Increment ulCriticalNesting to keep a count of how many */ \ + /* times portENTER_CRITICAL() has been called. */ \ + usCriticalNesting++; \ +} + +#define portEXIT_CRITICAL() \ +{ \ +extern volatile uint16_t usCriticalNesting; \ + \ + if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ + { \ + /* Decrement the nesting count as we are leaving a critical section. */ \ + usCriticalNesting--; \ + \ + /* If the nesting level has reached zero then interrupts should be */ \ + /* re-enabled. */ \ + if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } \ +} +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* + * Manual context switch called by portYIELD or taskYIELD. + */ +extern void vPortYield( void ); +#define portYIELD() vPortYield() +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 2 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) __toplevel + +#if configINTERRUPT_EXAMPLE_METHOD == 2 + +extern void vTaskSwitchContext( void ); +#define portYIELD_FROM_ISR( x ) do { if( x ) vTaskSwitchContext(); } while( 0 ) + +#endif + +#endif /* PORTMACRO_H */ diff --git a/portable/SDCC/Cygnal/port.c b/portable/SDCC/Cygnal/port.c new file mode 100644 index 000000000..418a50430 --- /dev/null +++ b/portable/SDCC/Cygnal/port.c @@ -0,0 +1,421 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the Cygnal port. + *----------------------------------------------------------*/ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to setup timer 2 to produce the RTOS tick. */ +#define portCLOCK_DIVISOR ( ( uint32_t ) 12 ) +#define portMAX_TIMER_VALUE ( ( uint32_t ) 0xffff ) +#define portENABLE_TIMER ( ( uint8_t ) 0x04 ) +#define portTIMER_2_INTERRUPT_ENABLE ( ( uint8_t ) 0x20 ) + +/* The value used in the IE register when a task first starts. */ +#define portGLOBAL_INTERRUPT_BIT ( ( StackType_t ) 0x80 ) + +/* The value used in the PSW register when a task first starts. */ +#define portINITIAL_PSW ( ( StackType_t ) 0x00 ) + +/* Macro to clear the timer 2 interrupt flag. */ +#define portCLEAR_INTERRUPT_FLAG() TMR2CN &= ~0x80; + +/* Used during a context switch to store the size of the stack being copied +to or from XRAM. */ +data static uint8_t ucStackBytes; + +/* Used during a context switch to point to the next byte in XRAM from/to which +a RAM byte is to be copied. */ +xdata static StackType_t * data pxXRAMStack; + +/* Used during a context switch to point to the next byte in RAM from/to which +an XRAM byte is to be copied. */ +data static StackType_t * data pxRAMStack; + +/* We require the address of the pxCurrentTCB variable, but don't want to know +any details of its type. */ +typedef void TCB_t; +extern volatile TCB_t * volatile pxCurrentTCB; + +/* + * Setup the hardware to generate an interrupt off timer 2 at the required + * frequency. + */ +static void prvSetupTimerInterrupt( void ); + +/*-----------------------------------------------------------*/ +/* + * Macro that copies the current stack from internal RAM to XRAM. This is + * required as the 8051 only contains enough internal RAM for a single stack, + * but we have a stack for every task. + */ +#define portCOPY_STACK_TO_XRAM() \ +{ \ + /* pxCurrentTCB points to a TCB which itself points to the location into \ + which the first stack byte should be copied. Set pxXRAMStack to point \ + to the location into which the first stack byte is to be copied. */ \ + pxXRAMStack = ( xdata StackType_t * ) *( ( xdata StackType_t ** ) pxCurrentTCB ); \ + \ + /* Set pxRAMStack to point to the first byte to be coped from the stack. */ \ + pxRAMStack = ( data StackType_t * data ) configSTACK_START; \ + \ + /* Calculate the size of the stack we are about to copy from the current \ + stack pointer value. */ \ + ucStackBytes = SP - ( configSTACK_START - 1 ); \ + \ + /* Before starting to copy the stack, store the calculated stack size so \ + the stack can be restored when the task is resumed. */ \ + *pxXRAMStack = ucStackBytes; \ + \ + /* Copy each stack byte in turn. pxXRAMStack is incremented first as we \ + have already stored the stack size into XRAM. */ \ + while( ucStackBytes ) \ + { \ + pxXRAMStack++; \ + *pxXRAMStack = *pxRAMStack; \ + pxRAMStack++; \ + ucStackBytes--; \ + } \ +} +/*-----------------------------------------------------------*/ + +/* + * Macro that copies the stack of the task being resumed from XRAM into + * internal RAM. + */ +#define portCOPY_XRAM_TO_STACK() \ +{ \ + /* Setup the pointers as per portCOPY_STACK_TO_XRAM(), but this time to \ + copy the data back out of XRAM and into the stack. */ \ + pxXRAMStack = ( xdata StackType_t * ) *( ( xdata StackType_t ** ) pxCurrentTCB ); \ + pxRAMStack = ( data StackType_t * data ) ( configSTACK_START - 1 ); \ + \ + /* The first value stored in XRAM was the size of the stack - i.e. the \ + number of bytes we need to copy back. */ \ + ucStackBytes = pxXRAMStack[ 0 ]; \ + \ + /* Copy the required number of bytes back into the stack. */ \ + do \ + { \ + pxXRAMStack++; \ + pxRAMStack++; \ + *pxRAMStack = *pxXRAMStack; \ + ucStackBytes--; \ + } while( ucStackBytes ); \ + \ + /* Restore the stack pointer ready to use the restored stack. */ \ + SP = ( uint8_t ) pxRAMStack; \ +} +/*-----------------------------------------------------------*/ + +/* + * Macro to push the current execution context onto the stack, before the stack + * is moved to XRAM. + */ +#define portSAVE_CONTEXT() \ +{ \ + _asm \ + /* Push ACC first, as when restoring the context it must be restored \ + last (it is used to set the IE register). */ \ + push ACC \ + /* Store the IE register then disable interrupts. */ \ + push IE \ + clr _EA \ + push DPL \ + push DPH \ + push b \ + push ar2 \ + push ar3 \ + push ar4 \ + push ar5 \ + push ar6 \ + push ar7 \ + push ar0 \ + push ar1 \ + push PSW \ + _endasm; \ + PSW = 0; \ + _asm \ + push _bp \ + _endasm; \ +} +/*-----------------------------------------------------------*/ + +/* + * Macro that restores the execution context from the stack. The execution + * context was saved into the stack before the stack was copied into XRAM. + */ +#define portRESTORE_CONTEXT() \ +{ \ + _asm \ + pop _bp \ + pop PSW \ + pop ar1 \ + pop ar0 \ + pop ar7 \ + pop ar6 \ + pop ar5 \ + pop ar4 \ + pop ar3 \ + pop ar2 \ + pop b \ + pop DPH \ + pop DPL \ + /* The next byte of the stack is the IE register. Only the global \ + enable bit forms part of the task context. Pop off the IE then set \ + the global enable bit to match that of the stored IE register. */ \ + pop ACC \ + JB ACC.7,0098$ \ + CLR IE.7 \ + LJMP 0099$ \ + 0098$: \ + SETB IE.7 \ + 0099$: \ + /* Finally pop off the ACC, which was the first register saved. */ \ + pop ACC \ + reti \ + _endasm; \ +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +uint32_t ulAddress; +StackType_t *pxStartOfStack; + + /* Leave space to write the size of the stack as the first byte. */ + pxStartOfStack = pxTopOfStack; + pxTopOfStack++; + + /* Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging and can be uncommented if required. + *pxTopOfStack = 0x11; + pxTopOfStack++; + *pxTopOfStack = 0x22; + pxTopOfStack++; + *pxTopOfStack = 0x33; + pxTopOfStack++; + */ + + /* Simulate how the stack would look after a call to the scheduler tick + ISR. + + The return address that would have been pushed by the MCU. */ + ulAddress = ( uint32_t ) pxCode; + *pxTopOfStack = ( StackType_t ) ulAddress; + ulAddress >>= 8; + pxTopOfStack++; + *pxTopOfStack = ( StackType_t ) ( ulAddress ); + pxTopOfStack++; + + /* Next all the registers will have been pushed by portSAVE_CONTEXT(). */ + *pxTopOfStack = 0xaa; /* acc */ + pxTopOfStack++; + + /* We want tasks to start with interrupts enabled. */ + *pxTopOfStack = portGLOBAL_INTERRUPT_BIT; + pxTopOfStack++; + + /* The function parameters will be passed in the DPTR and B register as + a three byte generic pointer is used. */ + ulAddress = ( uint32_t ) pvParameters; + *pxTopOfStack = ( StackType_t ) ulAddress; /* DPL */ + ulAddress >>= 8; + *pxTopOfStack++; + *pxTopOfStack = ( StackType_t ) ulAddress; /* DPH */ + ulAddress >>= 8; + pxTopOfStack++; + *pxTopOfStack = ( StackType_t ) ulAddress; /* b */ + pxTopOfStack++; + + /* The remaining registers are straight forward. */ + *pxTopOfStack = 0x02; /* R2 */ + pxTopOfStack++; + *pxTopOfStack = 0x03; /* R3 */ + pxTopOfStack++; + *pxTopOfStack = 0x04; /* R4 */ + pxTopOfStack++; + *pxTopOfStack = 0x05; /* R5 */ + pxTopOfStack++; + *pxTopOfStack = 0x06; /* R6 */ + pxTopOfStack++; + *pxTopOfStack = 0x07; /* R7 */ + pxTopOfStack++; + *pxTopOfStack = 0x00; /* R0 */ + pxTopOfStack++; + *pxTopOfStack = 0x01; /* R1 */ + pxTopOfStack++; + *pxTopOfStack = 0x00; /* PSW */ + pxTopOfStack++; + *pxTopOfStack = 0xbb; /* BP */ + + /* Dont increment the stack size here as we don't want to include + the stack size byte as part of the stack size count. + + Finally we place the stack size at the beginning. */ + *pxStartOfStack = ( StackType_t ) ( pxTopOfStack - pxStartOfStack ); + + /* Unlike most ports, we return the start of the stack as this is where the + size of the stack is stored. */ + return pxStartOfStack; +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + /* Setup timer 2 to generate the RTOS tick. */ + prvSetupTimerInterrupt(); + + /* Make sure we start with the expected SFR page. This line should not + really be required. */ + SFRPAGE = 0; + + /* Copy the stack for the first task to execute from XRAM into the stack, + restore the task context from the new stack, then start running the task. */ + portCOPY_XRAM_TO_STACK(); + portRESTORE_CONTEXT(); + + /* Should never get here! */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented for this port. */ +} +/*-----------------------------------------------------------*/ + +/* + * Manual context switch. The first thing we do is save the registers so we + * can use a naked attribute. + */ +void vPortYield( void ) _naked +{ + /* Save the execution context onto the stack, then copy the entire stack + to XRAM. This is necessary as the internal RAM is only large enough to + hold one stack, and we want one per task. + + PERFORMANCE COULD BE IMPROVED BY ONLY COPYING TO XRAM IF A TASK SWITCH + IS REQUIRED. */ + portSAVE_CONTEXT(); + portCOPY_STACK_TO_XRAM(); + + /* Call the standard scheduler context switch function. */ + vTaskSwitchContext(); + + /* Copy the stack of the task about to execute from XRAM into RAM and + restore it's context ready to run on exiting. */ + portCOPY_XRAM_TO_STACK(); + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +#if configUSE_PREEMPTION == 1 + void vTimer2ISR( void ) interrupt 5 _naked + { + /* Preemptive context switch function triggered by the timer 2 ISR. + This does the same as vPortYield() (see above) with the addition + of incrementing the RTOS tick count. */ + + portSAVE_CONTEXT(); + portCOPY_STACK_TO_XRAM(); + + if( xTaskIncrementTick() != pdFALSE ) + { + vTaskSwitchContext(); + } + + portCLEAR_INTERRUPT_FLAG(); + portCOPY_XRAM_TO_STACK(); + portRESTORE_CONTEXT(); + } +#else + void vTimer2ISR( void ) interrupt 5 + { + /* When using the cooperative scheduler the timer 2 ISR is only + required to increment the RTOS tick count. */ + + xTaskIncrementTick(); + portCLEAR_INTERRUPT_FLAG(); + } +#endif +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ +uint8_t ucOriginalSFRPage; + +/* Constants calculated to give the required timer capture values. */ +const uint32_t ulTicksPerSecond = configCPU_CLOCK_HZ / portCLOCK_DIVISOR; +const uint32_t ulCaptureTime = ulTicksPerSecond / configTICK_RATE_HZ; +const uint32_t ulCaptureValue = portMAX_TIMER_VALUE - ulCaptureTime; +const uint8_t ucLowCaptureByte = ( uint8_t ) ( ulCaptureValue & ( uint32_t ) 0xff ); +const uint8_t ucHighCaptureByte = ( uint8_t ) ( ulCaptureValue >> ( uint32_t ) 8 ); + + /* NOTE: This uses a timer only present on 8052 architecture. */ + + /* Remember the current SFR page so we can restore it at the end of the + function. */ + ucOriginalSFRPage = SFRPAGE; + SFRPAGE = 0; + + /* TMR2CF can be left in its default state. */ + TMR2CF = ( uint8_t ) 0; + + /* Setup the overflow reload value. */ + RCAP2L = ucLowCaptureByte; + RCAP2H = ucHighCaptureByte; + + /* The initial load is performed manually. */ + TMR2L = ucLowCaptureByte; + TMR2H = ucHighCaptureByte; + + /* Enable the timer 2 interrupts. */ + IE |= portTIMER_2_INTERRUPT_ENABLE; + + /* Interrupts are disabled when this is called so the timer can be started + here. */ + TMR2CN = portENABLE_TIMER; + + /* Restore the original SFR page. */ + SFRPAGE = ucOriginalSFRPage; +} diff --git a/portable/SDCC/Cygnal/portmacro.h b/portable/SDCC/Cygnal/portmacro.h new file mode 100644 index 000000000..fe0340757 --- /dev/null +++ b/portable/SDCC/Cygnal/portmacro.h @@ -0,0 +1,116 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#if configUSE_PREEMPTION == 0 + void vTimer2ISR( void ) interrupt 5; +#else + void vTimer2ISR( void ) interrupt 5 _naked; +#endif + +void vSerialISR( void ) interrupt 4; + + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE float +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint8_t +#define portBASE_TYPE char + +typedef portSTACK_TYPE StackType_t; +typedef signed char BaseType_t; +typedef unsigned char UBaseType_t; + +#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +#define portENTER_CRITICAL() _asm \ + push ACC \ + push IE \ + _endasm; \ + EA = 0; + +#define portEXIT_CRITICAL() _asm \ + pop ACC \ + _endasm; \ + ACC &= 0x80; \ + IE |= ACC; \ + _asm \ + pop ACC \ + _endasm; + +#define portDISABLE_INTERRUPTS() EA = 0; +#define portENABLE_INTERRUPTS() EA = 1; +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 1 +#define portSTACK_GROWTH ( 1 ) +#define portTICK_PERIOD_MS ( ( uint32_t ) 1000 / configTICK_RATE_HZ ) +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +void vPortYield( void ) _naked; +#define portYIELD() vPortYield(); +/*-----------------------------------------------------------*/ + +#define portNOP() _asm \ + nop \ + _endasm; + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#endif /* PORTMACRO_H */ diff --git a/portable/Softune/MB91460/__STD_LIB_sbrk.c b/portable/Softune/MB91460/__STD_LIB_sbrk.c new file mode 100644 index 000000000..4f986e804 --- /dev/null +++ b/portable/Softune/MB91460/__STD_LIB_sbrk.c @@ -0,0 +1,55 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ +/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ +/* ELIGIBILITY FOR ANY PURPOSES. */ +/* (C) Fujitsu Microelectronics Europe GmbH */ +/*--------------------------------------------------------------------------- + __STD_LIB_sbrk.C + - Used by heap_3.c for memory allocation and deletion. + +/*---------------------------------------------------------------------------*/ + +#include "FreeRTOSConfig.h" +#include + + static long brk_siz = 0; + typedef int _heep_t; + #define ROUNDUP(s) (((s)+sizeof(_heep_t)-1)&~(sizeof(_heep_t)-1)) + static _heep_t _heep[ROUNDUP(configTOTAL_HEAP_SIZE)/sizeof(_heep_t)]; + #define _heep_size ROUNDUP(configTOTAL_HEAP_SIZE) + + extern char *sbrk(int size) + { + if (brk_siz + size > _heep_size || brk_siz + size < 0) + + return((char*)-1); + brk_siz += size; + return( (char*)_heep + brk_siz - size); + } diff --git a/portable/Softune/MB91460/port.c b/portable/Softune/MB91460/port.c new file mode 100644 index 000000000..4b87ba402 --- /dev/null +++ b/portable/Softune/MB91460/port.c @@ -0,0 +1,321 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include "FreeRTOS.h" +#include "task.h" +#include "mb91467d.h" + +/*-----------------------------------------------------------*/ + +/* We require the address of the pxCurrentTCB variable, but don't want to know +any details of its type. */ +typedef void TCB_t; +extern volatile TCB_t * volatile pxCurrentTCB; + +/*-----------------------------------------------------------*/ + +#pragma asm +#macro SaveContext + ORCCR #0x20 ;Switch to user stack + ST RP,@-R15 ;Store RP + STM0 (R7,R6,R5,R4,R3,R2,R1,R0) ;Store R7-R0 + STM1 (R14,R13,R12,R11,R10,R9,R8) ;Store R14-R8 + ST MDH, @-R15 ;Store MDH + ST MDL, @-R15 ;Store MDL + + ANDCCR #0xDF ;Switch back to system stack + LD @R15+,R0 ;Store PC to R0 + ORCCR #0x20 ;Switch to user stack + ST R0,@-R15 ;Store PC to User stack + + ANDCCR #0xDF ;Switch back to system stack + LD @R15+,R0 ;Store PS to R0 + ORCCR #0x20 ;Switch to user stack + ST R0,@-R15 ;Store PS to User stack + + LDI #_pxCurrentTCB, R0 ;Get pxCurrentTCB address + LD @R0, R0 ;Get the pxCurrentTCB->pxTopOfStack address + ST R15,@R0 ;Store USP to pxCurrentTCB->pxTopOfStack + + ANDCCR #0xDF ;Switch back to system stack for the rest of tick ISR +#endm + +#macro RestoreContext + LDI #_pxCurrentTCB, R0 ;Get pxCurrentTCB address + LD @R0, R0 ;Get the pxCurrentTCB->pxTopOfStack address + ORCCR #0x20 ;Switch to user stack + LD @R0, R15 ;Restore USP from pxCurrentTCB->pxTopOfStack + + LD @R15+,R0 ;Store PS to R0 + ANDCCR #0xDF ;Switch to system stack + ST R0,@-R15 ;Store PS to system stack + + ORCCR #0x20 ;Switch to user stack + LD @R15+,R0 ;Store PC to R0 + ANDCCR #0xDF ;Switch to system stack + ST R0,@-R15 ;Store PC to system stack + + ORCCR #0x20 ;Switch back to retrieve the remaining context + + LD @R15+, MDL ;Restore MDL + LD @R15+, MDH ;Restore MDH + LDM1 (R14,R13,R12,R11,R10,R9,R8) ;Restore R14-R8 + LDM0 (R7,R6,R5,R4,R3,R2,R1,R0) ;Restore R7-R0 + LD @R15+, RP ;Restore RP + + ANDCCR #0xDF ;Switch back to system stack for the rest of tick ISR +#endm +#pragma endasm + +/*-----------------------------------------------------------*/ + +/* + * Perform hardware setup to enable ticks from timer 1, + */ +static void prvSetupTimerInterrupt( void ); +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See the header file portable.h. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging. */ + + *pxTopOfStack = 0x11111111; + pxTopOfStack--; + *pxTopOfStack = 0x22222222; + pxTopOfStack--; + *pxTopOfStack = 0x33333333; + pxTopOfStack--; + + /* This is a redundant push to the stack, it may be required if + in some implementations of the compiler the parameter to the task + is passed on to the stack rather than in R4 register. */ + *pxTopOfStack = (StackType_t)(pvParameters); + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0x00000000; /* RP */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x00007777; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x00006666; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x00005555; /* R5 */ + pxTopOfStack--; + + /* In the current implementation of the compiler the first + parameter to the task (or function) is passed via R4 parameter + to the task, hence the pvParameters pointer is copied into the R4 + register. See compiler manual section 4.6.2 for more information. */ + *pxTopOfStack = ( StackType_t ) (pvParameters); /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x00003333; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x00002222; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x00001111; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x00000001; /* R0 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x0000EEEE; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x0000DDDD; /* R13 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x0000CCCC; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x0000BBBB; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x0000AAAA; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x00009999; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x00008888; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11110000; /* MDH */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x22220000; /* MDL */ + pxTopOfStack--; + + /* The start of the task code. */ + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + + /* PS - User Mode, USP, ILM=31, Interrupts enabled */ + *pxTopOfStack = ( StackType_t ) 0x001F0030; /* PS */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Setup the hardware to generate the tick. */ + prvSetupTimerInterrupt(); + + /* Restore the context of the first task that is going to run. */ + #pragma asm + RestoreContext + #pragma endasm + + /* Simulate a function call end as generated by the compiler. We will now + jump to the start of the task the context of which we have just restored. */ + __asm(" reti "); + + /* Should not get here. */ + return pdFAIL; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented - unlikely to ever be required as there is nothing to + return to. */ +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ +/* The peripheral clock divided by 32 is used by the timer. */ +const uint16_t usReloadValue = ( uint16_t ) ( ( ( configPER_CLOCK_HZ / configTICK_RATE_HZ ) / 32UL ) - 1UL ); + + /* Setup RLT0 to generate a tick interrupt. */ + + TMCSR0_CNTE = 0; /* Count Disable */ + TMCSR0_CSL = 0x2; /* CLKP/32 */ + TMCSR0_MOD = 0; /* Software trigger */ + TMCSR0_RELD = 1; /* Reload */ + + TMCSR0_UF = 0; /* Clear underflow flag */ + TMRLR0 = usReloadValue; + TMCSR0_INTE = 1; /* Interrupt Enable */ + TMCSR0_CNTE = 1; /* Count Enable */ + TMCSR0_TRG = 1; /* Trigger */ + + PORTEN = 0x3; /* Port Enable */ +} +/*-----------------------------------------------------------*/ + +#if configUSE_PREEMPTION == 1 + + /* + * Tick ISR for preemptive scheduler. The tick count is incremented + * after the context is saved. Then the context is switched if required, + * and last the context of the task which is to be resumed is restored. + */ + + #pragma asm + + .global _ReloadTimer0_IRQHandler + _ReloadTimer0_IRQHandler: + + ANDCCR #0xEF ;Disable Interrupts + SaveContext ;Save context + ORCCR #0x10 ;Re-enable Interrupts + + LDI #0xFFFB,R1 + LDI #_tmcsr0, R0 + AND R1,@R0 ;Clear RLT0 interrupt flag + + CALL32 _xTaskIncrementTick,R12 ;Increment Tick + CALL32 _vTaskSwitchContext,R12 ;Switch context if required + + ANDCCR #0xEF ;Disable Interrupts + RestoreContext ;Restore context + ORCCR #0x10 ;Re-enable Interrupts + + RETI + + #pragma endasm + +#else + + /* + * Tick ISR for the cooperative scheduler. All this does is increment the + * tick count. We don't need to switch context, this can only be done by + * manual calls to taskYIELD(); + */ + __interrupt void ReloadTimer0_IRQHandler( void ) + { + /* Clear RLT0 interrupt flag */ + TMCSR0_UF = 0; + xTaskIncrementTick(); + } + +#endif + +/* + * Manual context switch. We can use a __nosavereg attribute as the context + * would be saved by PortSAVE_CONTEXT(). The context is switched and then + * the context of the new task is restored saved. + */ +#pragma asm + + .global _vPortYieldDelayed + _vPortYieldDelayed: + + ANDCCR #0xEF ;Disable Interrupts + SaveContext ;Save context + ORCCR #0x10 ;Re-enable Interrupts + + LDI #_dicr, R0 + BANDL #0x0E, @R0 ;Clear Delayed interrupt flag + + CALL32 _vTaskSwitchContext,R12 ;Switch context if required + + ANDCCR #0xEF ;Disable Interrupts + RestoreContext ;Restore context + ORCCR #0x10 ;Re-enable Interrupts + + RETI + +#pragma endasm +/*-----------------------------------------------------------*/ + +/* + * Manual context switch. We can use a __nosavereg attribute as the context + * would be saved by PortSAVE_CONTEXT(). The context is switched and then + * the context of the new task is restored saved. + */ +#pragma asm + + .global _vPortYield + _vPortYield: + + SaveContext ;Save context + CALL32 _vTaskSwitchContext,R12 ;Switch context if required + RestoreContext ;Restore context + + RETI + +#pragma endasm +/*-----------------------------------------------------------*/ diff --git a/portable/Softune/MB91460/portmacro.h b/portable/Softune/MB91460/portmacro.h new file mode 100644 index 000000000..182a3057e --- /dev/null +++ b/portable/Softune/MB91460/portmacro.h @@ -0,0 +1,111 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* Hardware specific includes. */ +#include "mb91467d.h" + +/* Standard includes. */ +#include + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +#if configKERNEL_INTERRUPT_PRIORITY != 30 + #error configKERNEL_INTERRUPT_PRIORITY (set in FreeRTOSConfig.h) must match the ILM value set in the following line - 30 (1Eh) being the default. +#endif +#define portDISABLE_INTERRUPTS() __asm(" STILM #1Eh ") +#define portENABLE_INTERRUPTS() __asm(" STILM #1Fh ") + +#define portENTER_CRITICAL() \ + __asm(" ST PS,@-R15 "); \ + __asm(" ANDCCR #0xef "); \ + + +#define portEXIT_CRITICAL() \ + __asm(" LD @R15+,PS "); \ + +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +#define portNOP() __asm( " nop " ); +/*-----------------------------------------------------------*/ + +/* portYIELD() uses a SW interrupt */ +#define portYIELD() __asm( " INT #40H " ); + +/* portYIELD_FROM_ISR() uses delayed interrupt */ +#define portYIELD_FROM_ISR() DICR_DLYI = 1 +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#define portMINIMAL_STACK_SIZE configMINIMAL_STACK_SIZE + + +#endif /* PORTMACRO_H */ diff --git a/portable/Softune/MB96340/__STD_LIB_sbrk.c b/portable/Softune/MB96340/__STD_LIB_sbrk.c new file mode 100644 index 000000000..4f986e804 --- /dev/null +++ b/portable/Softune/MB96340/__STD_LIB_sbrk.c @@ -0,0 +1,55 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ +/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ +/* ELIGIBILITY FOR ANY PURPOSES. */ +/* (C) Fujitsu Microelectronics Europe GmbH */ +/*--------------------------------------------------------------------------- + __STD_LIB_sbrk.C + - Used by heap_3.c for memory allocation and deletion. + +/*---------------------------------------------------------------------------*/ + +#include "FreeRTOSConfig.h" +#include + + static long brk_siz = 0; + typedef int _heep_t; + #define ROUNDUP(s) (((s)+sizeof(_heep_t)-1)&~(sizeof(_heep_t)-1)) + static _heep_t _heep[ROUNDUP(configTOTAL_HEAP_SIZE)/sizeof(_heep_t)]; + #define _heep_size ROUNDUP(configTOTAL_HEAP_SIZE) + + extern char *sbrk(int size) + { + if (brk_siz + size > _heep_size || brk_siz + size < 0) + + return((char*)-1); + brk_siz += size; + return( (char*)_heep + brk_siz - size); + } diff --git a/portable/Softune/MB96340/port.c b/portable/Softune/MB96340/port.c new file mode 100644 index 000000000..ec0d977bc --- /dev/null +++ b/portable/Softune/MB96340/port.c @@ -0,0 +1,509 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include "FreeRTOS.h" +#include "task.h" + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the 16FX port. + *----------------------------------------------------------*/ + +/* + * Get current value of DPR and ADB registers + */ +StackType_t xGet_DPR_ADB_bank( void ); + +/* + * Get current value of DTB and PCB registers + */ +StackType_t xGet_DTB_PCB_bank( void ); + +/* + * Sets up the periodic ISR used for the RTOS tick. This uses RLT0, but + * can be done using any given RLT. + */ +static void prvSetupRLT0Interrupt( void ); + +/*-----------------------------------------------------------*/ + +/* + * We require the address of the pxCurrentTCB variable, but don't want to know + * any details of its type. + */ +typedef void TCB_t; +extern volatile TCB_t * volatile pxCurrentTCB; + +/*-----------------------------------------------------------*/ + +/* + * Macro to save a task context to the task stack. This macro copies the + * saved context (AH:AL, DPR:ADB, DTB:PCB , PC and PS) from the system + * stack to task stack pointed by user stack pointer ( USP for SMALL and + * MEDIUM memory model amd USB:USP for COMPACT and LARGE memory model ), + * then it pushes the general purpose registers RW0-RW7 on to the task + * stack. Finally the resultant stack pointer value is saved into the + * task control block so it can be retrieved the next time the task + * executes. + */ +#if( ( configMEMMODEL == portSMALL ) || ( configMEMMODEL == portMEDIUM ) ) + + #define portSAVE_CONTEXT() \ + { __asm(" POPW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" PUSHW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" POPW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" PUSHW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" POPW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" PUSHW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" POPW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" PUSHW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" POPW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" PUSHW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" POPW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" PUSHW A "); \ + __asm(" PUSHW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) "); \ + __asm(" MOVW A, _pxCurrentTCB "); \ + __asm(" MOVW A, SP "); \ + __asm(" SWAPW "); \ + __asm(" MOVW @AL, AH "); \ + __asm(" OR CCR,#H'20 "); \ + } + +/* + * Macro to restore a task context from the task stack. This is + * effectively the reverse of SAVE_CONTEXT(). First the stack pointer + * value (USP for SMALL and MEDIUM memory model amd USB:USP for COMPACT + * and LARGE memory model ) is loaded from the task control block. Next + * the value of all the general purpose registers RW0-RW7 is retrieved. + * Finally it copies of the context ( AH:AL, DPR:ADB, DTB:PCB, PC and PS) + * of the task to be executed upon RETI from user stack to system stack. + */ + + #define portRESTORE_CONTEXT() \ + { __asm(" MOVW A, _pxCurrentTCB "); \ + __asm(" MOVW A, @A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" MOVW SP, A "); \ + __asm(" POPW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) "); \ + __asm(" POPW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" PUSHW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" POPW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" PUSHW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" POPW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" PUSHW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" POPW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" PUSHW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" POPW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" PUSHW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" POPW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" PUSHW A "); \ + } + +#elif( ( configMEMMODEL == portCOMPACT ) || ( configMEMMODEL == portLARGE ) ) + + #define portSAVE_CONTEXT() \ + { __asm(" POPW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" PUSHW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" POPW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" PUSHW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" POPW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" PUSHW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" POPW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" PUSHW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" POPW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" PUSHW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" POPW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" PUSHW A "); \ + __asm(" PUSHW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) "); \ + __asm(" MOVL A, _pxCurrentTCB "); \ + __asm(" MOVL RL2, A "); \ + __asm(" MOVW A, SP "); \ + __asm(" MOVW @RL2+0, A "); \ + __asm(" MOV A, USB "); \ + __asm(" MOV @RL2+2, A "); \ + } + + #define portRESTORE_CONTEXT() \ + { __asm(" MOVL A, _pxCurrentTCB "); \ + __asm(" MOVL RL2, A "); \ + __asm(" MOVW A, @RL2+0 "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" MOVW SP, A "); \ + __asm(" MOV A, @RL2+2 "); \ + __asm(" MOV USB, A "); \ + __asm(" POPW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) "); \ + __asm(" POPW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" PUSHW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" POPW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" PUSHW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" POPW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" PUSHW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" POPW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" PUSHW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" POPW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" PUSHW A "); \ + __asm(" AND CCR,#H'DF "); \ + __asm(" POPW A "); \ + __asm(" OR CCR,#H'20 "); \ + __asm(" PUSHW A "); \ + } +#endif + +/*-----------------------------------------------------------*/ + +/* + * Functions for obtaining the current value of DPR:ADB, DTB:PCB bank registers + */ + +#pragma asm + + .GLOBAL _xGet_DPR_ADB_bank + .GLOBAL _xGet_DTB_PCB_bank + .SECTION CODE, CODE, ALIGN=1 + +_xGet_DPR_ADB_bank: + + MOV A, DPR + SWAP + MOV A, ADB + ORW A + #if configMEMMODEL == portMEDIUM || configMEMMODEL == portLARGE + RETP + #elif configMEMMODEL == portSMALL || configMEMMODEL == portCOMPACT + RET + #endif + + +_xGet_DTB_PCB_bank: + + MOV A, DTB + SWAP + MOV A, PCB + ORW A + #if configMEMMODEL == portMEDIUM || configMEMMODEL == portLARGE + RETP + #elif configMEMMODEL == portSMALL || configMEMMODEL == portCOMPACT + RET + #endif + +#pragma endasm +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See the header file portable.h. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging. */ + *pxTopOfStack = 0x1111; + pxTopOfStack--; + *pxTopOfStack = 0x2222; + pxTopOfStack--; + *pxTopOfStack = 0x3333; + pxTopOfStack--; + + /* Once the task is called the task would push the pointer to the + parameter onto the stack. Hence here the pointer would be copied to the stack + first. When using the COMPACT or LARGE memory model the pointer would be 24 + bits, and when using the SMALL or MEDIUM memory model the pointer would be 16 + bits. */ + #if( ( configMEMMODEL == portCOMPACT ) || ( configMEMMODEL == portLARGE ) ) + { + *pxTopOfStack = ( StackType_t ) ( ( uint32_t ) ( pvParameters ) >> 16 ); + pxTopOfStack--; + } + #endif + + *pxTopOfStack = ( StackType_t ) ( pvParameters ); + pxTopOfStack--; + + /* This is redundant push to the stack. This is required in order to introduce + an offset so that the task accesses a parameter correctly that is passed on to + the task stack. */ + #if( ( configMEMMODEL == portMEDIUM ) || ( configMEMMODEL == portLARGE ) ) + { + *pxTopOfStack = ( xGet_DTB_PCB_bank() & 0xff00 ) | ( ( ( int32_t ) ( pxCode ) >> 16 ) & 0xff ); + pxTopOfStack--; + } + #endif + + /* This is redundant push to the stack. This is required in order to introduce + an offset so the task correctly accesses the parameter passed on the task stack. */ + *pxTopOfStack = ( StackType_t ) ( pxCode ); + pxTopOfStack--; + + /* PS - User Mode, ILM=7, RB=0, Interrupts enabled,USP */ + *pxTopOfStack = 0xE0C0; + pxTopOfStack--; + + /* PC */ + *pxTopOfStack = ( StackType_t ) ( pxCode ); + pxTopOfStack--; + + /* DTB | PCB */ + #if configMEMMODEL == portSMALL || configMEMMODEL == portCOMPACT + { + *pxTopOfStack = xGet_DTB_PCB_bank(); + pxTopOfStack--; + } + #endif + + /* DTB | PCB, in case of MEDIUM and LARGE memory models, PCB would be used + along with PC to indicate the start address of the function. */ + #if( ( configMEMMODEL == portMEDIUM ) || ( configMEMMODEL == portLARGE ) ) + { + *pxTopOfStack = ( xGet_DTB_PCB_bank() & 0xff00 ) | ( ( ( int32_t ) ( pxCode ) >> 16 ) & 0xff ); + pxTopOfStack--; + } + #endif + + /* DPR | ADB */ + *pxTopOfStack = xGet_DPR_ADB_bank(); + pxTopOfStack--; + + /* AL */ + *pxTopOfStack = ( StackType_t ) 0x9999; + pxTopOfStack--; + + /* AH */ + *pxTopOfStack = ( StackType_t ) 0xAAAA; + pxTopOfStack--; + + /* Next the general purpose registers. */ + *pxTopOfStack = ( StackType_t ) 0x7777; /* RW7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x6666; /* RW6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x5555; /* RW5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x4444; /* RW4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x3333; /* RW3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x2222; /* RW2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x1111; /* RW1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x8888; /* RW0 */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvSetupRLT0Interrupt( void ) +{ +/* The peripheral clock divided by 16 is used by the timer. */ +const uint16_t usReloadValue = ( uint16_t ) ( ( ( configCLKP1_CLOCK_HZ / configTICK_RATE_HZ ) / 16UL ) - 1UL ); + + /* set reload value = 34999+1, TICK Interrupt after 10 ms @ 56MHz of CLKP1 */ + TMRLR0 = usReloadValue; + + /* prescaler 1:16, reload, interrupt enable, count enable, trigger */ + TMCSR0 = 0x041B; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Setup the hardware to generate the tick. */ + prvSetupRLT0Interrupt(); + + /* Restore the context of the first task that is going to run. */ + portRESTORE_CONTEXT(); + + /* Simulate a function call end as generated by the compiler. We will now + jump to the start of the task the context of which we have just restored. */ + __asm(" reti "); + + + /* Should not get here. */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented - unlikely to ever be required as there is nothing to + return to. */ +} + +/*-----------------------------------------------------------*/ + +/* + * The interrupt service routine used depends on whether the pre-emptive + * scheduler is being used or not. + */ + +#if configUSE_PREEMPTION == 1 + + /* + * Tick ISR for preemptive scheduler. We can use a __nosavereg attribute + * as the context is to be saved by the portSAVE_CONTEXT() macro, not the + * compiler generated code. The tick count is incremented after the context + * is saved. + */ + __nosavereg __interrupt void prvRLT0_TICKISR( void ) + { + /* Disable interrupts so that portSAVE_CONTEXT() is not interrupted */ + __DI(); + + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT(); + + /* Enable interrupts */ + __EI(); + + /* Clear RLT0 interrupt flag */ + TMCSR0_UF = 0; + + /* Increment the tick count then switch to the highest priority task + that is ready to run. */ + if( xTaskIncrementTick() != pdFALSE ) + { + vTaskSwitchContext(); + } + + /* Disable interrupts so that portRESTORE_CONTEXT() is not interrupted */ + __DI(); + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT(); + + /* Enable interrupts */ + __EI(); + } + +#else + + /* + * Tick ISR for the cooperative scheduler. All this does is increment the + * tick count. We don't need to switch context, this can only be done by + * manual calls to taskYIELD(); + */ + __interrupt void prvRLT0_TICKISR( void ) + { + /* Clear RLT0 interrupt flag */ + TMCSR0_UF = 0; + + xTaskIncrementTick(); + } + +#endif + +/*-----------------------------------------------------------*/ + +/* + * Manual context switch. We can use a __nosavereg attribute as the context + * is to be saved by the portSAVE_CONTEXT() macro, not the compiler generated + * code. + */ +__nosavereg __interrupt void vPortYield( void ) +{ + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT(); + + /* Switch to the highest priority task that is ready to run. */ + vTaskSwitchContext(); + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +__nosavereg __interrupt void vPortYieldDelayed( void ) +{ + /* Disable interrupts so that portSAVE_CONTEXT() is not interrupted */ + __DI(); + + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT(); + + /* Enable interrupts */ + __EI(); + + /* Clear delayed interrupt flag */ + __asm (" CLRB 03A4H:0 "); + + /* Switch to the highest priority task that is ready to run. */ + vTaskSwitchContext(); + + /* Disable interrupts so that portSAVE_CONTEXT() is not interrupted */ + __DI(); + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT(); + + /* Enable interrupts */ + __EI(); +} +/*-----------------------------------------------------------*/ diff --git a/portable/Softune/MB96340/portmacro.h b/portable/Softune/MB96340/portmacro.h new file mode 100644 index 000000000..ef4a1eb5a --- /dev/null +++ b/portable/Softune/MB96340/portmacro.h @@ -0,0 +1,118 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* Standard includes. */ +#include + +/* Constants denoting the available memory models. These are used within +FreeRTOSConfig.h to set the configMEMMODEL value. */ +#define portSMALL 0 +#define portMEDIUM 1 +#define portCOMPACT 2 +#define portLARGE 3 + + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint16_t +#define portBASE_TYPE short + +typedef portSTACK_TYPE StackType_t; +typedef short BaseType_t; +typedef unsigned short UBaseType_t; + + +#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +#if configKERNEL_INTERRUPT_PRIORITY != 6 + #error configKERNEL_INTERRUPT_PRIORITY (set in FreeRTOSConfig.h) must match the ILM value set in the following line - #06H being the default. +#endif +#define portDISABLE_INTERRUPTS() __asm(" MOV ILM, #06h ") +#define portENABLE_INTERRUPTS() __asm(" MOV ILM, #07h ") + +#define portENTER_CRITICAL() \ + { __asm(" PUSHW PS "); \ + portDISABLE_INTERRUPTS(); \ + } + +#define portEXIT_CRITICAL() \ + { __asm(" POPW PS "); \ + } + +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 2 +#define portNOP() __asm( " NOP " ); +/*-----------------------------------------------------------*/ + +/* portYIELD() uses SW interrupt */ +#define portYIELD() __asm( " INT #122 " ); + +/* portYIELD_FROM_ISR() uses delayed interrupt */ +#define portYIELD_FROM_ISR() __asm( " SETB 03A4H:0 " ); +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#define portMINIMAL_STACK_SIZE configMINIMAL_STACK_SIZE + + +#endif /* PORTMACRO_H */ diff --git a/portable/Tasking/ARM_CM4F/port.c b/portable/Tasking/ARM_CM4F/port.c new file mode 100644 index 000000000..43a892f1e --- /dev/null +++ b/portable/Tasking/ARM_CM4F/port.c @@ -0,0 +1,275 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ARM CM4F port. +*----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to manipulate the NVIC. */ +#define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t * ) 0xe000e010 ) +#define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t * ) 0xe000e014 ) +#define portNVIC_SHPR3_REG ( ( volatile uint32_t * ) 0xe000ed20 ) +#define portNVIC_SYSTICK_CLK 0x00000004 +#define portNVIC_SYSTICK_INT 0x00000002 +#define portNVIC_SYSTICK_ENABLE 0x00000001 +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL ) +#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL ) + +/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */ +#define portVECTACTIVE_MASK ( 0xFFUL ) + +/* Constants required to manipulate the VFP. */ +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */ +#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) +#define portINITIAL_EXC_RETURN ( 0xfffffffd ) + +/* Let the user override the pre-loading of the initial LR with the address of + * prvTaskExitError() in case it messes up unwinding of the stack in the + * debugger. */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/* For strict compliance with the Cortex-M spec the task start address should + * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */ +#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL ) + +/* The priority used by the kernel is assigned to a variable to make access + * from inline assembler easier. */ +const uint32_t ulKernelPriority = portMIN_INTERRUPT_PRIORITY; + +/* Each task maintains its own interrupt status in the critical nesting + * variable. */ +static uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +/* + * Setup the timer to generate the tick interrupts. + */ +static void prvSetupTimerInterrupt( void ); + +/* + * Exception handlers. + */ +void SysTick_Handler( void ); + +/* + * Functions defined in port_asm.asm. + */ +extern void vPortEnableVFP( void ); +extern void vPortStartFirstTask( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/* This exists purely to allow the const to be used from within the + * port_asm.asm assembly file. */ +const uint32_t ulMaxSyscallInterruptPriorityConst = configMAX_SYSCALL_INTERRUPT_PRIORITY; + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + + /* Offset added to account for the way the MCU uses the stack on entry/exit + * of interrupts, and to ensure alignment. */ + pxTopOfStack--; + + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + + /* Save code space by skipping register initialisation. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + + /* A save method is being used that requires each task to maintain its + * own exec return value. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; + + pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + for( ; ; ) + { + } +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ); + + /* Make PendSV and SysTick the lowest priority interrupts. */ + *( portNVIC_SHPR3_REG ) |= portNVIC_PENDSV_PRI; + *( portNVIC_SHPR3_REG ) |= portNVIC_SYSTICK_PRI; + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + prvSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + /* Ensure the VFP is enabled - it should be anyway. */ + vPortEnableVFP(); + + /* Lazy save always. */ + *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortYield( void ) +{ + /* Set a PendSV to request a context switch. */ + *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET; + + /* Barriers are normally not required but do ensure the code is completely + * within the specified behaviour for the architecture. */ + __DSB(); + __ISB(); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + __DSB(); + __ISB(); + + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ + if( ulCriticalNesting == 1 ) + { + configASSERT( ( ( *( portNVIC_INT_CTRL ) ) & portVECTACTIVE_MASK ) == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) +{ + uint32_t ulDummy; + + ulDummy = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); + { + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + /* Pend a context switch. */ + *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET; + } + else + { + traceISR_EXIT(); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy ); +} +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +void prvSetupTimerInterrupt( void ) +{ + /* Configure SysTick to interrupt at the requested rate. */ + *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE; +} \ No newline at end of file diff --git a/portable/Tasking/ARM_CM4F/port_asm.asm b/portable/Tasking/ARM_CM4F/port_asm.asm new file mode 100644 index 000000000..8b6784e70 --- /dev/null +++ b/portable/Tasking/ARM_CM4F/port_asm.asm @@ -0,0 +1,236 @@ +;/* +; * FreeRTOS Kernel +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * SPDX-License-Identifier: MIT +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * https://www.FreeRTOS.org +; * https://github.com/FreeRTOS +; * +; */ + + + .extern pxCurrentTCB + .extern vTaskSwitchContext + .extern ulMaxSyscallInterruptPriorityConst + + .global _vector_14 + .global _lc_ref__vector_pp_14 + .global SVC_Handler + .global vPortStartFirstTask + .global vPortEnableVFP + .global ulPortSetInterruptMask + .global vPortClearInterruptMask + +;----------------------------------------------------------- + + .section .text + .thumb + .align 4 +_vector_14: .type func + + mrs r0, psp + isb + + ;Get the location of the current TCB. + ldr.w r3, =pxCurrentTCB + ldr r2, [r3] + + ;Is the task using the FPU context? If so, push high vfp registers. + tst r14, #0x10 + it eq + vstmdbeq r0!, {s16-s31} + + ;Save the core registers. + stmdb r0!, {r4-r11, r14} + + ;Save the new top of stack into the first member of the TCB. + str r0, [r2] + + stmdb sp!, {r0, r3} + ldr.w r0, =ulMaxSyscallInterruptPriorityConst + ldr r0, [r0] + msr basepri, r0 + bl vTaskSwitchContext + mov r0, #0 + msr basepri, r0 + ldmia sp!, {r0, r3} + + ;The first item in pxCurrentTCB is the task top of stack. + ldr r1, [r3] + ldr r0, [r1] + + ;Pop the core registers. + ldmia r0!, {r4-r11, r14} + + ;Is the task using the FPU context? If so, pop the high vfp registers too. + tst r14, #0x10 + it eq + vldmiaeq r0!, {s16-s31} + + msr psp, r0 + isb + bx r14 + + .size _vector_14, $-_vector_14 + .endsec + +;----------------------------------------------------------- + +; This function is an XMC4000 silicon errata workaround. It will get used when +; the SILICON_BUG_PMC_CM_001 linker macro is defined. + .section .text + .thumb + .align 4 +_lc_ref__vector_pp_14: .type func + + mrs r0, psp + isb + + ;Get the location of the current TCB. + ldr.w r3, =pxCurrentTCB + ldr r2, [r3] + + ;Is the task using the FPU context? If so, push high vfp registers. + tst r14, #0x10 + it eq + vstmdbeq r0!, {s16-s31} + + ;Save the core registers. + stmdb r0!, {r4-r11, r14} + + ;Save the new top of stack into the first member of the TCB. + str r0, [r2] + + stmdb sp!, {r3} + ldr.w r0, =ulMaxSyscallInterruptPriorityConst + ldr r0, [r0] + msr basepri, r0 + bl vTaskSwitchContext + mov r0, #0 + msr basepri, r0 + ldmia sp!, {r3} + + ;The first item in pxCurrentTCB is the task top of stack. + ldr r1, [r3] + ldr r0, [r1] + + ;Pop the core registers. + ldmia r0!, {r4-r11, r14} + + ;Is the task using the FPU context? If so, pop the high vfp registers too. + tst r14, #0x10 + it eq + vldmiaeq r0!, {s16-s31} + + msr psp, r0 + isb + push { lr } + pop { pc } ; XMC4000 specific errata workaround. Do not used "bx lr" here. + + .size _lc_ref__vector_pp_14, $-_lc_ref__vector_pp_14 + .endsec + +;----------------------------------------------------------- + + .section .text + .thumb + .align 4 +SVC_Handler: .type func + ;Get the location of the current TCB. + ldr.w r3, =pxCurrentTCB + ldr r1, [r3] + ldr r0, [r1] + ;Pop the core registers. + ldmia r0!, {r4-r11, r14} + msr psp, r0 + isb + mov r0, #0 + msr basepri, r0 + bx r14 + .size SVC_Handler, $-SVC_Handler + .endsec + +;----------------------------------------------------------- + + .section .text + .thumb + .align 4 +vPortStartFirstTask .type func + ;Use the NVIC offset register to locate the stack. + ldr.w r0, =0xE000ED08 + ldr r0, [r0] + ldr r0, [r0] + ;Set the msp back to the start of the stack. + msr msp, r0 + ;Call SVC to start the first task. + cpsie i + cpsie f + dsb + isb + svc 0 + .size vPortStartFirstTask, $-vPortStartFirstTask + .endsec + +;----------------------------------------------------------- + + .section .text + .thumb + .align 4 +vPortEnableVFP .type func + ;The FPU enable bits are in the CPACR. + ldr.w r0, =0xE000ED88 + ldr r1, [r0] + + ;Enable CP10 and CP11 coprocessors, then save back. + orr r1, r1, #( 0xf << 20 ) + str r1, [r0] + bx r14 + .size vPortEnableVFP, $-vPortEnableVFP + .endsec + +;----------------------------------------------------------- + + .section .text + .thumb + .align 4 +ulPortSetInterruptMask: + mrs r0, basepri + ldr.w r1, =ulMaxSyscallInterruptPriorityConst + ldr r1, [r1] + msr basepri, r1 + bx r14 + .size ulPortSetInterruptMask, $-ulPortSetInterruptMask + .endsec + +;----------------------------------------------------------- + + .section .text + .thumb + .align 4 +vPortClearInterruptMask: + msr basepri, r0 + bx r14 + .size vPortClearInterruptMask, $-vPortClearInterruptMask + .endsec + +;----------------------------------------------------------- + + .end diff --git a/portable/Tasking/ARM_CM4F/portmacro.h b/portable/Tasking/ARM_CM4F/portmacro.h new file mode 100644 index 000000000..3d16cd6da --- /dev/null +++ b/portable/Tasking/ARM_CM4F/portmacro.h @@ -0,0 +1,151 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H + #define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + + #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. + #endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 +/*-----------------------------------------------------------*/ + + +/* Scheduler utilities. */ +extern void vPortYield( void ); +#define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 ) +#define portNVIC_PENDSVSET 0x10000000 +#define portYIELD() vPortYield() + +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + + +/* Critical section management. */ + +/* + * Set basepri to portMAX_SYSCALL_INTERRUPT_PRIORITY without effecting other + * registers. r0 is clobbered. + */ + #define portSET_INTERRUPT_MASK() __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ) + +/* + * Set basepri back to 0 without effective other registers. + * r0 is clobbered. FAQ: Setting BASEPRI to 0 is not a bug. Please see + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. + */ + #define portCLEAR_INTERRUPT_MASK() __set_BASEPRI( 0 ) + + extern uint32_t ulPortSetInterruptMask( void ); + extern void vPortClearInterruptMask( uint32_t ulNewMask ); + #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortClearInterruptMask( x ) + + + extern void vPortEnterCritical( void ); + extern void vPortExitCritical( void ); + + #define portDISABLE_INTERRUPTS() portSET_INTERRUPT_MASK() + #define portENABLE_INTERRUPTS() portCLEAR_INTERRUPT_MASK() + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + + #define portNOP() + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/ThirdParty/CDK/T-HEAD_CK802/port.c b/portable/ThirdParty/CDK/T-HEAD_CK802/port.c new file mode 100644 index 000000000..8f5ab7d26 --- /dev/null +++ b/portable/ThirdParty/CDK/T-HEAD_CK802/port.c @@ -0,0 +1,168 @@ +/* + * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" + +extern void vPortStartTask( void ); + +/* Used to keep track of the number of nested calls to taskENTER_CRITICAL(). This + * will be set to 0 prior to the first task being started. */ +portLONG ulCriticalNesting = 0x9999UL; + +/* Used to record one tack want to switch task after enter critical area, we need know it + * and implement task switch after exit critical area */ +portLONG pendsvflag = 0; + +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + StackType_t * stk = NULL; + + stk = pxTopOfStack; + + *( --stk ) = ( uint32_t ) pxCode; /* Entry Point */ + *( --stk ) = ( uint32_t ) 0xE0000140L; /* PSR */ + *( --stk ) = ( uint32_t ) 0xFFFFFFFEL; /* R15 (LR) (init value will cause fault if ever used) */ + *( --stk ) = ( uint32_t ) 0x13131313L; /* R13 */ + *( --stk ) = ( uint32_t ) 0x12121212L; /* R12 */ + *( --stk ) = ( uint32_t ) 0x11111111L; /* R11 */ + *( --stk ) = ( uint32_t ) 0x10101010L; /* R10 */ + *( --stk ) = ( uint32_t ) 0x09090909L; /* R9 */ + *( --stk ) = ( uint32_t ) 0x08080808L; /* R8 */ + *( --stk ) = ( uint32_t ) 0x07070707L; /* R7 */ + *( --stk ) = ( uint32_t ) 0x06060606L; /* R6 */ + *( --stk ) = ( uint32_t ) 0x05050505L; /* R5 */ + *( --stk ) = ( uint32_t ) 0x04040404L; /* R4 */ + *( --stk ) = ( uint32_t ) 0x03030303L; /* R3 */ + *( --stk ) = ( uint32_t ) 0x02020202L; /* R2 */ + *( --stk ) = ( uint32_t ) 0x01010101L; /* R1 */ + *( --stk ) = ( uint32_t ) pvParameters; /* R0 : argument */ + + return stk; +} + +BaseType_t xPortStartScheduler( void ) +{ + ulCriticalNesting = 0UL; + + vPortStartTask(); + + return pdFALSE; +} + + +void vPortEndScheduler( void ) +{ + /* Not implemented as there is nothing to return to. */ +} + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; +} + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting == 0 ) + { + while( 1 ) + { + } + } + + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + + if( pendsvflag ) + { + pendsvflag = 0; + portYIELD(); + } + } +} + +#if configUSE_PREEMPTION == 0 + void xPortSysTickHandler( void ) + { + portLONG ulDummy; + + ulDummy = portSET_INTERRUPT_MASK_FROM_ISR(); + xTaskIncrementTick(); + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy ); + } + +#else + void xPortSysTickHandler( void ) + { + portLONG ulDummy; + + ulDummy = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); + { + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + portYIELD_FROM_ISR( pdTRUE ); + } + else + { + traceISR_EXIT(); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy ); + } +#endif /* if configUSE_PREEMPTION == 0 */ + +void vPortYieldHandler( void ) +{ + uint32_t ulSavedInterruptMask; + + ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR(); + + vTaskSwitchContext(); + + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask ); +} + +__attribute__( ( weak ) ) void vApplicationStackOverflowHook( xTaskHandle * pxTask, + signed portCHAR * pcTaskName ) +{ + for( ; ; ) + { + } +} + +__attribute__( ( weak ) ) void vApplicationMallocFailedHook( void ) +{ + for( ; ; ) + { + } +} diff --git a/portable/ThirdParty/CDK/T-HEAD_CK802/portasm.S b/portable/ThirdParty/CDK/T-HEAD_CK802/portasm.S new file mode 100644 index 000000000..3ab6a9a28 --- /dev/null +++ b/portable/ThirdParty/CDK/T-HEAD_CK802/portasm.S @@ -0,0 +1,127 @@ +/* + * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +//#include + +/******************************************************************** + * Functions: vPortStartTask + * + ********************************************************************/ +.global vPortStartTask +.type vPortStartTask, %function +vPortStartTask: + psrclr ie + lrw r4, pxCurrentTCB + ld.w r4, (r4) // the current task stack pointer is the first member + ld.w sp, (r4) + + ldw r0, (sp, 64) + mtcr r0, epc + ldw r0, (sp, 60) + mtcr r0, epsr + ldw r15, (sp, 56) + ldm r0-r13, (sp) + addi sp, 68 + rte + +/******************************************************************** + * Functions: vPortYield + * + ********************************************************************/ +.global vPortYield +.type vPortYield, %function +vPortYield: + psrclr ee + subi sp, 68 + stm r0-r13, (sp) + stw r15, (sp, 56) + mfcr r0, psr + bseti r0, 8 + stw r0, (sp, 60) + stw r15, (sp, 64) + + lrw r2, pxCurrentTCB + ld.w r3, (r2) + st.w sp, (r3) + + jbsr vTaskSwitchContext + lrw r4, pxCurrentTCB + ld.w r4, (r4) + ld.w sp, (r4) + + ldw r0, (sp, 64) + mtcr r0, epc + ldw r0, (sp, 60) + mtcr r0, epsr + ldw r15, (sp, 56) + ldm r0-r13, (sp) + addi sp, 68 + + rte + +/******************************************************************** + * Functions: NOVIC_IRQ_Default_Handler + * + ********************************************************************/ +.global NOVIC_IRQ_Default_Handler +.type NOVIC_IRQ_Default_Handler, %function +NOVIC_IRQ_Default_Handler: + psrset ee + subi sp, 68 + stm r0-r13, (sp) + stw r15, (sp, 56) + mfcr r0, epsr + stw r0, (sp, 60) + mfcr r0, epc + stw r0, (sp, 64) + + lrw r7, pxCurrentTCB + ldw r7, (r7) + stw sp, (r7) + + lrw sp, g_top_irqstack + + lrw r1, g_irqvector + mfcr r0, psr + lsri r0, 16 + sextb r0 + subi r0, 32 + lsli r0, 2 + add r1, r0 + ldw r1, (r1) + lsri r0, 2 + jsr r1 + + lrw r7, pxCurrentTCB + ldw r7, (r7) + ldw sp, (r7) + + ldw r0, (sp, 64) + mtcr r0, epc + ldw r0, (sp, 60) + mtcr r0, epsr + ldm r0-r13, (sp) + ldw r15, (sp, 56) + addi sp, 68 + rte diff --git a/portable/ThirdParty/CDK/T-HEAD_CK802/portmacro.h b/portable/ThirdParty/CDK/T-HEAD_CK802/portmacro.h new file mode 100644 index 000000000..76c72f488 --- /dev/null +++ b/portable/ThirdParty/CDK/T-HEAD_CK802/portmacro.h @@ -0,0 +1,174 @@ +/* + * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#include +#include +#include + +extern void vPortYield( void ); + +/* *INDENT-OFF* */ +#ifdef __cplusplus + class vPortYield; + extern "C" { +#endif +/* *INDENT-ON* */ + + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; +typedef void (* portvectorfunc)( void ); + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif + + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 8 +#define portSTACK_GROWTH -1 +#define portMS_PERIOD_TICK 10 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + + +static inline void vPortEnableInterrupt( void ) +{ + __enable_irq(); +} + +static inline void vPortDisableInterrupt( void ) +{ + __disable_irq(); +} + +static inline portLONG GetCurrentPSR( void ) +{ + return __get_PSR(); +} + +static inline portLONG SaveLocalPSR( void ) +{ + portLONG flags = __get_PSR(); + + __disable_irq(); + return flags; +} + +static inline void RestoreLocalPSR( portLONG newMask ) +{ + __asm__ __volatile__ ( + "mtcr %0, psr \n" + : + : "r" ( newMask ) + : "memory" + ); +} + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +extern __attribute__( ( naked ) ) void cpu_yeild( void ); + +#define portDISABLE_INTERRUPTS() vPortDisableInterrupt() +#define portENABLE_INTERRUPTS() vPortEnableInterrupt() +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +#define portSET_INTERRUPT_MASK_FROM_ISR() SaveLocalPSR() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( a ) RestoreLocalPSR( a ) + +#define portNOP() asm ( "nop" ) + +extern portLONG ulCriticalNesting; +extern portLONG pendsvflag; + +#define portYIELD() \ + if( ulCriticalNesting == 0 ) \ + { \ + vPortYield(); \ + } \ + else \ + { \ + pendsvflag = 1; \ + } \ + portNOP(); portNOP() + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) __attribute__( ( noreturn ) ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portYIELD(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) + +#define portYIELD_FROM_ISR( a ) vTaskSwitchContext() + + + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/ThirdParty/Community-Supported-Ports b/portable/ThirdParty/Community-Supported-Ports new file mode 160000 index 000000000..bae4c7aa1 --- /dev/null +++ b/portable/ThirdParty/Community-Supported-Ports @@ -0,0 +1 @@ +Subproject commit bae4c7aa19009825ba48071a8fe25dcb8be84880 diff --git a/portable/ThirdParty/GCC/ARC_EM_HS/arc_freertos_exceptions.c b/portable/ThirdParty/GCC/ARC_EM_HS/arc_freertos_exceptions.c new file mode 100644 index 000000000..3b5b085a2 --- /dev/null +++ b/portable/ThirdParty/GCC/ARC_EM_HS/arc_freertos_exceptions.c @@ -0,0 +1,52 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/** + * \file + * \brief exception processing for freertos + */ + +/* #include "embARC.h" */ + +#include "arc_freertos_exceptions.h" + +#ifdef __GNU__ + extern void gnu_printf_setup( void ); +#endif + +/** + * \brief freertos related cpu exception initialization, all the interrupts handled by freertos must be not + * fast irqs. If fiq is needed, please install the default firq_exc_entry or your own fast irq entry into + * the specific interrupt exception. + */ +void freertos_exc_init( void ) +{ + #ifdef __GNU__ + gnu_printf_setup(); + #endif +} diff --git a/portable/ThirdParty/GCC/ARC_EM_HS/arc_freertos_exceptions.h b/portable/ThirdParty/GCC/ARC_EM_HS/arc_freertos_exceptions.h new file mode 100644 index 000000000..35a5abafb --- /dev/null +++ b/portable/ThirdParty/GCC/ARC_EM_HS/arc_freertos_exceptions.h @@ -0,0 +1,46 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef ARC_FREERTOS_EXCEPTIONS_H +#define ARC_FREERTOS_EXCEPTIONS_H + +/* + * here, all arc cpu exceptions share the same entry, also for all interrupt + * exceptions + */ +extern void exc_entry_cpu( void ); /* cpu exception entry for freertos */ +extern void exc_entry_int( void ); /* int exception entry for freertos */ + +/* task dispatch functions in .s */ +extern void start_r( void ); +extern void start_dispatch(); +extern void dispatch(); + +extern void freertos_exc_init( void ); + +#endif /* ARC_FREERTOS_EXCEPTIONS_H */ diff --git a/portable/ThirdParty/GCC/ARC_EM_HS/arc_support.s b/portable/ThirdParty/GCC/ARC_EM_HS/arc_support.s new file mode 100644 index 000000000..14174a376 --- /dev/null +++ b/portable/ThirdParty/GCC/ARC_EM_HS/arc_support.s @@ -0,0 +1,522 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/** + * \file + * \ingroup OS_FREERTOS + * \brief freertos support for arc processor + * like task dispatcher, interrupt handler + */ +/** @cond OS_FREERTOS_ASM_ARC_SUPPORT */ + +/* + * core-dependent part in assemble language (for arc) + */ +#define __ASSEMBLY__ +#include "arc/arc.h" +#include "arc/arc_asm_common.h" + +/* + * task dispatcher + * + */ + .text + .align 4 + .global dispatch +dispatch: +/* + * the pre-conditions of this routine are task context, CPU is + * locked, dispatch is enabled. + */ + SAVE_NONSCRATCH_REGS /* save callee save registers */ + mov r1, dispatch_r + PUSH r1 /* save return address */ + ld r0, [pxCurrentTCB] + bl dispatcher + +/* return routine when task dispatch happened in task context */ +dispatch_r: + RESTORE_NONSCRATCH_REGS /* recover registers */ + j [blink] + +/* + * start dispatch + */ + .global start_dispatch + .align 4 +start_dispatch: +/* + * this routine is called in the non-task context during the startup of the kernel + * , and all the interrupts are locked. + * + * when the dispatcher is called, the cpu is locked, no nest exception (CPU exception/interrupt). + * In target_initialize, all interrupt priority mask should be cleared, cpu should be + * locked, the interrupts outside the kernel such as fiq can be + * enabled. + */ + clri + mov r0, 0 + st r0, [exc_nest_count] + b dispatcher_0 +/* + * dispatcher + */ +dispatcher: + ld r1, [ulCriticalNesting] + PUSH r1 /* save critical nesting */ + st sp, [r0] /* save stack pointer of current task, r0->pxCurrentTCB */ + jl vTaskSwitchContext /* change the value of pxCurrentTCB */ +/* + * before dispatcher is called, task context | cpu locked | dispatch enabled + * should be satisfied. In this routine, the processor will jump + * into the entry of next to run task + * + * i.e. kernel mode, IRQ disabled, dispatch enabled + */ +dispatcher_0: + ld r1, [pxCurrentTCB] + ld sp, [r1] /* recover task stack */ +#if ARC_FEATURE_STACK_CHECK +#if ARC_FEATURE_SEC_PRESENT + lr r0, [AUX_SEC_STAT] + bclr r0, r0, AUX_SEC_STAT_BIT_SSC + sflag r0 +#else + lr r0, [AUX_STATUS32] + bclr r0, r0, AUX_STATUS_BIT_SC + kflag r0 +#endif + jl vPortSetStackCheck +#if ARC_FEATURE_SEC_PRESENT + lr r0, [AUX_SEC_STAT] + bset r0, r0, AUX_SEC_STAT_BIT_SSC + sflag r0 +#else + lr r0, [AUX_STATUS32] + bset r0, r0, AUX_STATUS_BIT_SC + kflag r0 +#endif +#endif + POP r0 /* get critical nesting */ + st r0, [ulCriticalNesting] + POP r0 /* get return address */ + j [r0] + +/* + * task startup routine + * + */ + .text + .global start_r + .align 4 +start_r: + seti /* unlock cpu */ + mov blink, vPortEndTask /* set return address */ + POP r1 /* get task function body */ + POP r0 /* get task parameters */ + j [r1] + +/****** exceptions and interrupts handing ******/ +/****** entry for exception handling ******/ + .global exc_entry_cpu + .align 4 +exc_entry_cpu: + + EXCEPTION_PROLOGUE + + mov blink, sp + mov r3, sp /* as exception handler's para(p_excinfo) */ + + ld r0, [exc_nest_count] + add r1, r0, 1 + st r1, [exc_nest_count] + brne r0, 0, exc_handler_1 +/* change to exception stack if interrupt happened in task context */ + mov sp, _e_stack +exc_handler_1: + PUSH blink + + lr r0, [AUX_ECR] + lsr r0, r0, 16 + mov r1, exc_int_handler_table + ld.as r2, [r1, r0] + + mov r0, r3 + jl [r2] /* !!!!jump to exception handler where interrupts are not allowed! */ + +/* interrupts are not allowed */ +ret_exc: + POP sp + mov r1, exc_nest_count + ld r0, [r1] + sub r0, r0, 1 + st r0, [r1] + brne r0, 0, ret_exc_1 /* nest exception case */ + lr r1, [AUX_IRQ_ACT] /* nest interrupt case */ + brne r1, 0, ret_exc_1 + + ld r0, [context_switch_reqflg] + brne r0, 0, ret_exc_2 +ret_exc_1: /* return from non-task context, interrupts or exceptions are nested */ + + EXCEPTION_EPILOGUE + rtie + +/* there is a dispatch request */ +ret_exc_2: + /* clear dispatch request */ + mov r0, 0 + st r0, [context_switch_reqflg] + + ld r0, [pxCurrentTCB] + breq r0, 0, ret_exc_1 + + SAVE_CALLEE_REGS /* save callee save registers */ + + lr r0, [AUX_STATUS32] + bclr r0, r0, AUX_STATUS_BIT_AE /* clear exception bit */ + kflag r0 + + mov r1, ret_exc_r /* save return address */ + PUSH r1 + + bl dispatcher /* r0->pxCurrentTCB */ + +ret_exc_r: + /* recover exception status */ + lr r0, [AUX_STATUS32] + bset r0, r0, AUX_STATUS_BIT_AE + kflag r0 + + RESTORE_CALLEE_REGS /* recover registers */ + EXCEPTION_EPILOGUE + rtie + +/****** entry for normal interrupt exception handling ******/ + .global exc_entry_int /* entry for interrupt handling */ + .align 4 +exc_entry_int: +#if ARC_FEATURE_FIRQ == 1 +#if ARC_FEATURE_RGF_NUM_BANKS > 1 + lr r0, [AUX_IRQ_ACT] /* check whether it is P0 interrupt */ + btst r0, 0 + jnz exc_entry_firq +#else + PUSH r10 + lr r10, [AUX_IRQ_ACT] + btst r10, 0 + POP r10 + jnz exc_entry_firq +#endif +#endif + INTERRUPT_PROLOGUE + + mov blink, sp + + clri /* disable interrupt */ + ld r3, [exc_nest_count] + add r2, r3, 1 + st r2, [exc_nest_count] + seti /* enable higher priority interrupt */ + + brne r3, 0, irq_handler_1 +/* change to exception stack if interrupt happened in task context */ + mov sp, _e_stack +#if ARC_FEATURE_STACK_CHECK +#if ARC_FEATURE_SEC_PRESENT + lr r0, [AUX_SEC_STAT] + bclr r0, r0, AUX_SEC_STAT_BIT_SSC + sflag r0 +#else + lr r0, [AUX_STATUS32] + bclr r0, r0, AUX_STATUS_BIT_SC + kflag r0 +#endif +#endif +irq_handler_1: + PUSH blink + + lr r0, [AUX_IRQ_CAUSE] + mov r1, exc_int_handler_table + ld.as r2, [r1, r0] /* r2 = exc_int_handler_table + irqno *4 */ +/* handle software triggered interrupt */ + lr r3, [AUX_IRQ_HINT] + cmp r3, r0 + bne.d irq_hint_handled + xor r3, r3, r3 + sr r3, [AUX_IRQ_HINT] +irq_hint_handled: + + jl [r2] /* jump to interrupt handler */ +/* no interrupts are allowed from here */ +ret_int: + clri /* disable interrupt */ + + POP sp + mov r1, exc_nest_count + ld r0, [r1] + sub r0, r0, 1 + st r0, [r1] +/* if there are multi-bits set in IRQ_ACT, it's still in nest interrupt */ + lr r0, [AUX_IRQ_CAUSE] + sr r0, [AUX_IRQ_SELECT] + lr r3, [AUX_IRQ_PRIORITY] + lr r1, [AUX_IRQ_ACT] + bclr r2, r1, r3 + brne r2, 0, ret_int_1 + + ld r0, [context_switch_reqflg] + brne r0, 0, ret_int_2 +ret_int_1: /* return from non-task context */ + INTERRUPT_EPILOGUE + rtie +/* there is a dispatch request */ +ret_int_2: + /* clear dispatch request */ + mov r0, 0 + st r0, [context_switch_reqflg] + + ld r0, [pxCurrentTCB] + breq r0, 0, ret_int_1 + +/* r1 has old AUX_IRQ_ACT */ + PUSH r1 +/* clear related bits in IRQ_ACT manually to simulate a irq return */ + sr r2, [AUX_IRQ_ACT] + + SAVE_CALLEE_REGS /* save callee save registers */ + mov r1, ret_int_r /* save return address */ + PUSH r1 + + bl dispatcher /* r0->pxCurrentTCB */ + +ret_int_r: + RESTORE_CALLEE_REGS /* recover registers */ + POPAX AUX_IRQ_ACT + INTERRUPT_EPILOGUE + rtie + +#if ARC_FEATURE_FIRQ == 1 + .global exc_entry_firq + .align 4 +exc_entry_firq: +#if ARC_FEATURE_STACK_CHECK && ARC_FEATURE_RGF_NUM_BANKS > 1 +#if ARC_FEATURE_SEC_PRESENT + lr r0, [AUX_SEC_STAT] + bclr r0, r0, AUX_SEC_STAT_BIT_SSC + sflag r0 +#else + lr r0, [AUX_STATUS32] + bclr r0, r0, AUX_STATUS_BIT_SC + kflag r0 +#endif +#endif + SAVE_FIQ_EXC_REGS + + mov blink, sp + + ld r3, [exc_nest_count] + add r2, r3, 1 + st r2, [exc_nest_count] + + brne r3, 0, firq_handler_1 +#if ARC_FEATURE_STACK_CHECK && ARC_FEATURE_RGF_NUM_BANKS == 1 +#if ARC_FEATURE_SEC_PRESENT + lr r0, [AUX_SEC_STAT] + bclr r0, r0, AUX_SEC_STAT_BIT_SSC + sflag r0 +#else + lr r0, [AUX_STATUS32] + bclr r0, r0, AUX_STATUS_BIT_SC + kflag r0 +#endif +#endif +/* change to exception stack if interrupt happened in task context */ + mov sp, _e_stack +firq_handler_1: + PUSH blink + + lr r0, [AUX_IRQ_CAUSE] + mov r1, exc_int_handler_table + ld.as r2, [r1, r0] /* r2 = exc_int_handler_table + irqno *4 */ +/* handle software triggered interrupt */ + lr r3, [AUX_IRQ_HINT] + brne r3, r0, firq_hint_handled + xor r3, r3, r3 + sr r3, [AUX_IRQ_HINT] +firq_hint_handled: + + jl [r2] /* jump to interrupt handler */ +/* no interrupts are allowed from here */ +ret_firq: + clri + POP sp + + mov r1, exc_nest_count + ld r0, [r1] + sub r0, r0, 1 + st r0, [r1] +/* if there are multi-bits set in IRQ_ACT, it's still in nest interrupt */ + lr r1, [AUX_IRQ_ACT] + bclr r1, r1, 0 + brne r1, 0, ret_firq_1 + + ld r0, [context_switch_reqflg] + brne r0, 0, ret_firq_2 +ret_firq_1: /* return from non-task context */ + RESTORE_FIQ_EXC_REGS + rtie +/* there is a dispatch request */ +ret_firq_2: + /* clear dispatch request */ + mov r0, 0 + st r0, [context_switch_reqflg] + + ld r0, [pxCurrentTCB] + breq r0, 0, ret_firq_1 + +/* reconstruct the interruptted context + * When ARC_FEATURE_RGF_BANKED_REGS >= 16 (16, 32), sp is banked + * so need to restore the fast irq stack. + */ +#if ARC_FEATURE_RGF_BANKED_REGS >= 16 + RESTORE_LP_REGS +#if ARC_FEATURE_CODE_DENSITY + RESTORE_CODE_DENSITY +#endif + RESTORE_R58_R59 +#endif + +/* when BANKED_REGS == 16, r4-r9 wiil be also saved in fast irq stack + * so pop them out + */ +#if ARC_FEATURE_RGF_BANKED_REGS == 16 && !defined(ARC_FEATURE_RF16) + POP r9 + POP r8 + POP r7 + POP r6 + POP r5 + POP r4 +#endif + +/* for other cases, unbanked regs are already in interrupted context's stack, + * so just need to save and pop the banked regs + */ + +/* save the interruptted context */ +#if ARC_FEATURE_RGF_BANKED_REGS > 0 +/* switch back to bank0 */ + lr r0, [AUX_STATUS32] + bic r0, r0, 0x70000 + kflag r0 +#endif + +#if ARC_FEATURE_RGF_BANKED_REGS == 4 +/* r4 - r12, gp, fp, r30, blink already saved */ + PUSH r0 + PUSH r1 + PUSH r2 + PUSH r3 +#elif ARC_FEATURE_RGF_BANKED_REGS == 8 +/* r4 - r9, r0, r11 gp, fp, r30, blink already saved */ + PUSH r0 + PUSH r1 + PUSH r2 + PUSH r3 + PUSH r12 +#elif ARC_FEATURE_RGF_BANKED_REGS >= 16 +/* nothing is saved, */ + SAVE_R0_TO_R12 + + SAVE_R58_R59 + PUSH gp + PUSH fp + PUSH r30 /* general purpose */ + PUSH blink + +#if ARC_FEATURE_CODE_DENSITY + SAVE_CODE_DENSITY +#endif + SAVE_LP_REGS +#endif + PUSH ilink + lr r0, [AUX_STATUS32_P0] + PUSH r0 + lr r0, [AUX_IRQ_ACT] + PUSH r0 + bclr r0, r0, 0 + sr r0, [AUX_IRQ_ACT] + + SAVE_CALLEE_REGS /* save callee save registers */ + + mov r1, ret_firq_r /* save return address */ + PUSH r1 + ld r0, [pxCurrentTCB] + bl dispatcher /* r0->pxCurrentTCB */ + +ret_firq_r: + RESTORE_CALLEE_REGS /* recover registers */ + POPAX AUX_IRQ_ACT + POPAX AUX_STATUS32_P0 + POP ilink + +#if ARC_FEATURE_RGF_NUM_BANKS > 1 +#if ARC_FEATURE_RGF_BANKED_REGS == 4 +/* r4 - r12, gp, fp, r30, blink already saved */ + POP r3 + POP r2 + POP r1 + POP r0 + RESTORE_FIQ_EXC_REGS +#elif ARC_FEATURE_RGF_BANKED_REGS == 8 +/* r4 - r9, gp, fp, r30, blink already saved */ + POP r12 + POP r3 + POP r2 + POP r1 + POP r0 + RESTORE_FIQ_EXC_REGS +#elif ARC_FEATURE_RGF_BANKED_REGS >= 16 + RESTORE_LP_REGS +#if ARC_FEATURE_CODE_DENSITY + RESTORE_CODE_DENSITY +#endif + POP blink + POP r30 + POP fp + POP gp + + RESTORE_R58_R59 + RESTORE_R0_TO_R12 +#endif /* ARC_FEATURE_RGF_BANKED_REGS */ +#else + RESTORE_FIQ_EXC_REGS +#endif /* ARC_FEATURE_RGF_NUM_BANKS */ + rtie +#endif +/** @endcond */ diff --git a/portable/ThirdParty/GCC/ARC_EM_HS/freertos_tls.c b/portable/ThirdParty/GCC/ARC_EM_HS/freertos_tls.c new file mode 100644 index 000000000..7d74f319e --- /dev/null +++ b/portable/ThirdParty/GCC/ARC_EM_HS/freertos_tls.c @@ -0,0 +1,240 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#if defined( __MW__ ) + + #include + #include + #include + + #include "FreeRTOS.h" + + #include "queue.h" + #include "semphr.h" + #include "task.h" + + #include "arc/arc_exception.h" + #include "embARC_toolchain.h" + #include "embARC_debug.h" + + #ifdef ENABLE_FREERTOS_TLS_DEBUG + #define TLS_DEBUG( fmt, ... ) EMBARC_PRINTF( fmt, ## __VA_ARGS__ ) + #else + #define TLS_DEBUG( fmt, ... ) + #endif + +/* + * Runtime routines to execute constructors and + * destructors for task local storage. + */ + extern void __mw_run_tls_dtor(); + extern void __mw_run_tls_ctor(); + + extern uint32_t exc_nest_count; + +/* + * Linker generated symbols to mark .tls section addresses + * first byte .. last byte + */ + extern char _ftls[], _etls[]; + #pragma weak _ftls + #pragma weak _etls + + void executable_requires_tls_section( void ) + { + #if _ARC + for( ; ; ) + { + _flag( 1 ); + _nop(); + _nop(); + _nop(); + _nop(); + _nop(); + } + #endif + } + #pragma off_inline(executable_requires_tls_section); + #pragma alias(executable_requires_tls_section, "executable_requires_.tls_section"); + + static void * init_task_tls( void ) + { + uint32_t len = ( uint32_t ) ( _etls - _ftls ); + void * tls = NULL; + + #if FREERTOS_HEAP_SEL == 3 + #warning "FreeRTOS TLS support is not compatible with heap 3 solution(FREERTOS_HEAP_SEL=3)!" + #warning "You can change FREERTOS_HEAP_SEL in freertos.mk to select other heap solution." + #else + tls = pvPortMalloc( len ); + #endif + + if( tls ) + { + TLS_DEBUG( "Malloc task tls:%dbytes\r\n", len ); + memcpy( tls, _ftls, len ); + __mw_run_tls_ctor(); /* Run constructors */ + } + + return tls; + } + + static void free_task_tls( void * pxTCB ) + { + TaskHandle_t task2free = ( TaskHandle_t ) pxTCB; + + if( task2free != NULL ) + { + void * tls = pvTaskGetThreadLocalStoragePointer( task2free, 0 ); + + if( tls ) + { + TLS_DEBUG( "Free task tls\r\n" ); + __mw_run_tls_dtor(); + vPortFree( tls ); + vTaskSetThreadLocalStoragePointer( task2free, 0, NULL ); + } + } + } + + void task_end_hook( void * pxTCB ) + { + free_task_tls( pxTCB ); + } + + static void * get_isr_tls( void ) + { + /* In an ISR */ + static int first = 1; + + if( _Rarely( first ) ) + { + first = 0; + __mw_run_tls_ctor(); /* Run constructors */ + } + + return ( void * ) _ftls; + } + #pragma off_inline(get_isr_tls) + + static void * get_task_tls( void ) + { + TaskHandle_t cur_task; + + cur_task = xTaskGetCurrentTaskHandle(); + + if( cur_task == NULL ) + { + return get_isr_tls(); + } + + void * tls = pvTaskGetThreadLocalStoragePointer( cur_task, 0 ); + + if( tls == NULL ) + { + tls = init_task_tls(); + + if( tls ) + { + vTaskSetThreadLocalStoragePointer( cur_task, 0, tls ); + } + else + { + tls = get_isr_tls(); + } + } + + return tls; + } + #pragma off_inline(get_task_tls) + + #if _ARC /* for ARC XCALLs need to preserve flags */ + extern void * _Preserve_flags _mwget_tls( void ); + #endif + +/* + * Back end gens calls to find local data for this task + */ + void * _mwget_tls( void ) + { + if( _ftls == ( char * ) 0 ) + { + executable_requires_tls_section(); + } + + if( exc_nest_count > 0 ) /* In ISR */ + { + return get_isr_tls(); + } + else /* In Task */ + { + return get_task_tls(); + } + } + + +/* simple interface of thread safe */ + typedef xSemaphoreHandle _lock_t; + #if configUSE_RECURSIVE_MUTEXES != 1 + #error "configUSE_RECURSIVE_MUTEXES in FreeRTOSConfig.h need to 1" + #endif + + void _mwmutex_create( _lock_t * mutex_ptr ) + { + *mutex_ptr = xSemaphoreCreateRecursiveMutex(); + } + + void _mwmutex_delete( _lock_t * mutex_ptr ) + { + if( ( *mutex_ptr ) != NULL ) + { + vSemaphoreDelete( *mutex_ptr ); + } + } + + void _mwmutex_lock( _lock_t mutex ) + { + if( ( mutex ) != NULL ) + { + while( xSemaphoreTakeRecursive( mutex, portMAX_DELAY ) != pdTRUE ) + { + } + } + } + + void _mwmutex_unlock( _lock_t mutex ) + { + if( ( mutex ) != NULL ) + { + xSemaphoreGiveRecursive( mutex ); + } + } + +#else /* if defined( __MW__ ) */ + +#endif /* __MW__ */ diff --git a/portable/ThirdParty/GCC/ARC_EM_HS/port.c b/portable/ThirdParty/GCC/ARC_EM_HS/port.c new file mode 100644 index 000000000..7837f8f73 --- /dev/null +++ b/portable/ThirdParty/GCC/ARC_EM_HS/port.c @@ -0,0 +1,293 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * Implementation of functions defined in portable.h + */ + +#include "FreeRTOS.h" +#include "task.h" +#include "FreeRTOSConfig.h" + +#include "arc/arc_exception.h" +#include "arc/arc_timer.h" +#include "board.h" + +#include "arc_freertos_exceptions.h" + +volatile unsigned int ulCriticalNesting = 999UL; +volatile unsigned int context_switch_reqflg; /* task context switch request flag in exceptions and interrupts handling */ + +/** + * \var exc_nest_count + * \brief the counter for exc/int processing, =0 no int/exc + * >1 in int/exc processing + * @} + */ +uint32_t exc_nest_count; +/* --------------------------------------------------------------------------*/ + +/** + * @brief kernel tick interrupt handler of freertos + */ +/* ----------------------------------------------------------------------------*/ +static void vKernelTick( void * ptr ) +{ + /* clear timer interrupt */ + arc_timer_int_clear( BOARD_OS_TIMER_ID ); + board_timer_update( configTICK_RATE_HZ ); + + if( xTaskIncrementTick() ) + { + portYIELD_FROM_ISR(); /* need to make task switch */ + } +} + +/* --------------------------------------------------------------------------*/ + +/** + * @brief setup freertos kernel tick + */ +/* ----------------------------------------------------------------------------*/ +static void prvSetupTimerInterrupt( void ) +{ + unsigned int cyc = configCPU_CLOCK_HZ / configTICK_RATE_HZ; + + int_disable( BOARD_OS_TIMER_INTNO ); /* disable os timer interrupt */ + arc_timer_stop( BOARD_OS_TIMER_ID ); + arc_timer_start( BOARD_OS_TIMER_ID, TIMER_CTRL_IE | TIMER_CTRL_NH, cyc ); + + int_handler_install( BOARD_OS_TIMER_INTNO, ( INT_HANDLER_T ) vKernelTick ); + int_pri_set( BOARD_OS_TIMER_INTNO, INT_PRI_MIN ); + int_enable( BOARD_OS_TIMER_INTNO ); +} + +/* + * Setup the stack of a new task so it is ready to be placed under the + * scheduler control. The registers have to be placed on the stack in + * the order that the port expects to find them. + * + * For ARC, task context switch is implemented with the help of SWI exception + * It's not efficient but simple. + * + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* To ensure asserts in tasks.c don't fail, although in this case the assert + * is not really required. */ + pxTopOfStack--; + + /* Setup the initial stack of the task. The stack is set exactly as + * expected by the portRESTORE_CONTEXT() macro. */ + + /* When the task starts is will expect to find the function parameter in + * R0. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* function body */ + + /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) start_r; /* dispatch return address */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_NESTING; + return pxTopOfStack; +} + +/* --------------------------------------------------------------------------*/ + +/** + * @brief start the freertos scheduler, go to the first task + * + * @returns + */ +/* ----------------------------------------------------------------------------*/ +BaseType_t xPortStartScheduler( void ) +{ + /* Start the timer that generates the tick ISR. */ + prvSetupTimerInterrupt(); + start_dispatch(); + + /* Should not get here! */ + return 0; +} + +/* --------------------------------------------------------------------------*/ + +/** + * @brief + */ +/* ----------------------------------------------------------------------------*/ +void vPortEndScheduler( void ) +{ +} + +/* --------------------------------------------------------------------------*/ + +/** + * @brief generate a task switch request in ISR + */ +/* ----------------------------------------------------------------------------*/ +void vPortYieldFromIsr( void ) +{ + unsigned int status32; + + status32 = cpu_lock_save(); + context_switch_reqflg = true; + cpu_unlock_restore( status32 ); +} + +/* --------------------------------------------------------------------------*/ + +/** + * @brief + */ +/* ----------------------------------------------------------------------------*/ +void vPortYield( void ) +{ + unsigned int status32; + + status32 = cpu_lock_save(); + dispatch(); + cpu_unlock_restore( status32 ); +} + +/* --------------------------------------------------------------------------*/ + +/** + * @brief + */ +/* ----------------------------------------------------------------------------*/ +void vPortEndTask( void ) +{ + #if ( INCLUDE_vTaskDelete == 1 ) + vTaskDelete( NULL ); /* Delete task itself */ + #endif + + while( 1 ) /* Yield to other task */ + { + vPortYield(); + } +} + +#if ARC_FEATURE_STACK_CHECK + +/* + * !!! Note !!! + * This a trick!!! + * It's a copy from task.c. We need to know the definition of TCB for the purpose of hardware + * stack check. Pls don't forget to update it when FreeRTOS is updated. + */ + typedef struct tskTaskControlBlock /* The old naming convention is used to prevent breaking kernel aware debuggers. */ + { + volatile StackType_t * pxTopOfStack; /*< Points to the location of the last item placed on the tasks stack. THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */ + + #if ( portUSING_MPU_WRAPPERS == 1 ) + xMPU_SETTINGS xMPUSettings; /*< The MPU settings are defined as part of the port layer. THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */ + #endif + + ListItem_t xStateListItem; /*< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */ + ListItem_t xEventListItem; /*< Used to reference a task from an event list. */ + UBaseType_t uxPriority; /*< The priority of the task. 0 is the lowest priority. */ + StackType_t * pxStack; /*< Points to the start of the stack. */ + char pcTaskName[ configMAX_TASK_NAME_LEN ]; /*< Descriptive name given to the task when created. Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + + #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) ) + StackType_t * pxEndOfStack; /*< Points to the highest valid address for the stack. */ + #endif + + #if ( portCRITICAL_NESTING_IN_TCB == 1 ) + UBaseType_t uxCriticalNesting; /*< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */ + #endif + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxTCBNumber; /*< Stores a number that increments each time a TCB is created. It allows debuggers to determine when a task has been deleted and then recreated. */ + UBaseType_t uxTaskNumber; /*< Stores a number specifically for use by third party trace code. */ + #endif + + #if ( configUSE_MUTEXES == 1 ) + UBaseType_t uxBasePriority; /*< The priority last assigned to the task - used by the priority inheritance mechanism. */ + UBaseType_t uxMutexesHeld; + #endif + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + TaskHookFunction_t pxTaskTag; + #endif + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 ) + void * pvThreadLocalStoragePointers[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ]; + #endif + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + uint32_t ulRunTimeCounter; /*< Stores the amount of time the task has spent in the Running state. */ + #endif + + #if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) + configTLS_BLOCK_TYPE xTLSBlock; /*< Memory block used as Thread Local Storage (TLS) Block for the task. */ + #endif + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + volatile uint32_t ulNotifiedValue; + volatile uint8_t ucNotifyState; + #endif + + /* See the comments above the definition of + * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE. */ + #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ + uint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */ + #endif + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + uint8_t ucDelayAborted; + #endif + + #if ( configUSE_POSIX_ERRNO == 1 ) + int iTaskErrno; + #endif + } tskTCB; + + + void vPortSetStackCheck( TaskHandle_t old, + TaskHandle_t new ) + { + if( new != NULL ) + { + #if ARC_FEATURE_SEC_PRESENT + arc_aux_write( AUX_S_KSTACK_BASE, ( uint32_t ) ( new->pxEndOfStack ) ); + arc_aux_write( AUX_S_KSTACK_TOP, ( uint32_t ) ( new->pxStack ) ); + #else + arc_aux_write( AUX_KSTACK_BASE, ( uint32_t ) ( new->pxEndOfStack ) ); + arc_aux_write( AUX_KSTACK_TOP, ( uint32_t ) ( new->pxStack ) ); + #endif + } + } +#endif /* if ARC_FEATURE_STACK_CHECK */ diff --git a/portable/ThirdParty/GCC/ARC_EM_HS/portmacro.h b/portable/ThirdParty/GCC/ARC_EM_HS/portmacro.h new file mode 100644 index 000000000..e5004146b --- /dev/null +++ b/portable/ThirdParty/GCC/ARC_EM_HS/portmacro.h @@ -0,0 +1,160 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/* record stack high address for stack check */ +#ifndef configRECORD_STACK_HIGH_ADDRESS + #define configRECORD_STACK_HIGH_ADDRESS 1 +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned int +#define portBASE_TYPE portLONG + +#ifndef Asm + #define Asm __asm__ volatile +#endif + +/* + * normal constants + */ +#ifndef NULL + #define NULL 0 /* invalid pointer */ +#endif /* NULL */ + +#ifndef true + #define true 1 /* true */ +#endif /* true */ + +#ifndef false + #define false 0 /* false */ +#endif /* false */ + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif + +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() Asm( "nop_s" ); +#define IPM_ENABLE_ALL 1 + +#define portYIELD_FROM_ISR() vPortYieldFromIsr() +#define portYIELD() vPortYield() + +/* Critical section management. */ +#define portDISABLE_INTERRUPTS() \ + { \ + Asm( "clri" ); \ + Asm( "" ::: "memory" ); \ + } \ + +#define portENABLE_INTERRUPTS() \ + { \ + Asm( "" ::: "memory" ); \ + Asm( "seti" ); \ + } \ + +extern volatile unsigned int ulCriticalNesting; + +#define portENTER_CRITICAL() \ + { \ + portDISABLE_INTERRUPTS() \ + ulCriticalNesting++; \ + } + + +#define portEXIT_CRITICAL() \ + { \ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) \ + { \ + ulCriticalNesting--; \ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) \ + { \ + portENABLE_INTERRUPTS() \ + } \ + } \ + } + + +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() do {} while( 0 ) /* we use the timer */ +#define portALT_GET_RUN_TIME_COUNTER_VALUE( dest ) ( dest = xTickCount ) + +#if defined( __MW__ ) + extern void task_end_hook( void * pxTCB ); + #define portCLEAN_UP_TCB( pxTCB ) task_end_hook( ( void * ) pxTCB ) +#endif + +void vPortYield( void ); +void vPortYieldFromIsr( void ); + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/ThirdParty/GCC/ARC_v1/arc_freertos_exceptions.c b/portable/ThirdParty/GCC/ARC_v1/arc_freertos_exceptions.c new file mode 100644 index 000000000..3b5b085a2 --- /dev/null +++ b/portable/ThirdParty/GCC/ARC_v1/arc_freertos_exceptions.c @@ -0,0 +1,52 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/** + * \file + * \brief exception processing for freertos + */ + +/* #include "embARC.h" */ + +#include "arc_freertos_exceptions.h" + +#ifdef __GNU__ + extern void gnu_printf_setup( void ); +#endif + +/** + * \brief freertos related cpu exception initialization, all the interrupts handled by freertos must be not + * fast irqs. If fiq is needed, please install the default firq_exc_entry or your own fast irq entry into + * the specific interrupt exception. + */ +void freertos_exc_init( void ) +{ + #ifdef __GNU__ + gnu_printf_setup(); + #endif +} diff --git a/portable/ThirdParty/GCC/ARC_v1/arc_freertos_exceptions.h b/portable/ThirdParty/GCC/ARC_v1/arc_freertos_exceptions.h new file mode 100644 index 000000000..35a5abafb --- /dev/null +++ b/portable/ThirdParty/GCC/ARC_v1/arc_freertos_exceptions.h @@ -0,0 +1,46 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef ARC_FREERTOS_EXCEPTIONS_H +#define ARC_FREERTOS_EXCEPTIONS_H + +/* + * here, all arc cpu exceptions share the same entry, also for all interrupt + * exceptions + */ +extern void exc_entry_cpu( void ); /* cpu exception entry for freertos */ +extern void exc_entry_int( void ); /* int exception entry for freertos */ + +/* task dispatch functions in .s */ +extern void start_r( void ); +extern void start_dispatch(); +extern void dispatch(); + +extern void freertos_exc_init( void ); + +#endif /* ARC_FREERTOS_EXCEPTIONS_H */ diff --git a/portable/ThirdParty/GCC/ARC_v1/arc_support.s b/portable/ThirdParty/GCC/ARC_v1/arc_support.s new file mode 100644 index 000000000..df2ec408c --- /dev/null +++ b/portable/ThirdParty/GCC/ARC_v1/arc_support.s @@ -0,0 +1,322 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/** + * \file + * \ingroup OS_FREERTOS + * \brief freertos support for arc processor + * like task dispatcher, interrupt handler + */ +/** @cond OS_FREERTOS_ASM_ARC_SUPPORT */ + +/* + * core-dependent part in assemble language (for arc) + */ +#define __ASSEMBLY__ +#include "arc/arc.h" +#include "arc/arc_asm_common.h" + +/* + * task dispatcher + * + */ + .text + .align 4 + .global dispatch +dispatch: +/* + * the pre-conditions of this routine are task context, CPU is + * locked, dispatch is enabled. + */ + SAVE_NONSCRATCH_REGS /* save callee save registers */ + mov r1, dispatch_r + PUSH r1 /* save return address */ + ld r0, [pxCurrentTCB] + bl dispatcher + +/* return routine when task dispatch happened in task context */ +dispatch_r: + RESTORE_NONSCRATCH_REGS /* recover registers */ + j [blink] + +/* + * start dispatch + */ + .global start_dispatch + .align 4 +start_dispatch: +/* + * this routine is called in the non-task context during the startup of the kernel + * , and all the interrupts are locked. + * + * when the dispatcher is called, the cpu is locked, no nest exception (CPU exception/interrupt). + * In target_initialize, all interrupt priority mask should be cleared, cpu should be + * locked, the interrupts outside the kernel such as fiq can be + * enabled. + */ + clri + mov r0, 0 + st r0, [exc_nest_count] + b dispatcher_0 +/* + * dispatcher + */ +dispatcher: + ld r1, [ulCriticalNesting] + PUSH r1 /* save critical nesting */ + st sp, [r0] /* save stack pointer of current task, r0->pxCurrentTCB */ + jl vTaskSwitchContext /* change the value of pxCurrentTCB */ +/* + * before dispatcher is called, task context | cpu locked | dispatch enabled + * should be satisfied. In this routine, the processor will jump + * into the entry of next to run task + * + * i.e. kernel mode, IRQ disabled, dispatch enabled + */ +dispatcher_0: + ld r1, [pxCurrentTCB] + ld sp, [r1] /* recover task stack */ +#if ARC_FEATURE_STACK_CHECK + lr r0, [AUX_STATUS32] + bclr r0, r0, AUX_STATUS_BIT_SC + flag r0 + jl vPortSetStackCheck + lr r0, [AUX_STATUS32] + bset r0, r0, AUX_STATUS_BIT_SC + flag r0 +#endif + POP r0 /* get critical nesting */ + st r0, [ulCriticalNesting] + POP r0 /* get return address */ + j [r0] + +/* + * task startup routine + * + */ + .text + .global start_r + .align 4 +start_r: + seti /* unlock cpu */ + mov blink, vPortEndTask /* set return address */ + POP r1 /* get task function body */ + POP r0 /* get task parameters */ + j [r1] + +/****** exceptions and interrupts handing ******/ +/****** entry for exception handling ******/ + .global exc_entry_cpu + .align 4 +exc_entry_cpu: + + EXCEPTION_PROLOGUE + + + mov blink, sp + mov r3, sp /* as exception handler's para(p_excinfo) */ + + ld r1, [exc_nest_count] + add r1, r1, 1 + st r1, [exc_nest_count] + brne r1, 0, exc_handler_1 +/* change to exception stack if interrupt happened in task context */ + mov sp, _e_stack +exc_handler_1: + PUSH blink + +/* find the exception cause */ +#if ARC_FEATURE_CORE_700 + lr r0, [AUX_ECR] + lsr r0, r0, 16 + bmsk r0, r0, 7 +#endif + mov r1, exc_int_handler_table + ld.as r2, [r1, r0] + + mov r0, r3 + jl [r2] /* !!!!jump to exception handler where interrupts are not allowed! */ + +/* interrupts are not allowed */ +ret_exc: + POP sp + mov r1, exc_nest_count + ld r0, [r1] + sub r0, r0, 1 + st r0, [r1] + brne r0, 0, ret_exc_1 /* nested exception case */ + lr r1, [AUX_IRQ_LV12] + brne r1, 0, ret_exc_1 /* nested or pending interrupt case */ + + ld r0, [context_switch_reqflg] + brne r0, 0, ret_exc_2 +ret_exc_1: /* return from non-task context, interrupts or exceptions are nested */ + + EXCEPTION_EPILOGUE +#if ARC_FEATURE_CORE_600 + rtie ilink2 +#else + rtie +#endif + +/* there is a dispatch request */ +ret_exc_2: + /* clear dispatch request */ + mov r0, 0 + st r0, [context_switch_reqflg] + + ld r0, [pxCurrentTCB] + breq r0, 0, ret_exc_1 + + SAVE_CALLEE_REGS /* save callee save registers */ + + lr r0, [AUX_STATUS32] + bclr r0, r0, AUX_STATUS_BIT_AE /* clear exception bit */ + flag r0 + + mov r1, ret_exc_r /* save return address */ + PUSH r1 + + bl dispatcher /* r0->pxCurrentTCB */ + +ret_exc_r: + /* recover exception status */ + lr r0, [AUX_STATUS32] + bset r0, r0, AUX_STATUS_BIT_AE + flag r0 + + RESTORE_CALLEE_REGS /* recover registers */ + EXCEPTION_EPILOGUE +#if ARC_FEATURE_CORE_600 + rtie ilink2 +#else + rtie +#endif + +/****** entry for normal interrupt exception handling ******/ + .global exc_entry_int /* entry for interrupt handling */ + .align 4 +exc_entry_int: + + INTERRUPT_PROLOGUE + + mov blink, sp + + /* disable interrupt */ + push r0 + lr r0, [AUX_STATUS32] + push r0 + bclr r0, r0, AUX_STATUS_BIT_E1 + bclr r0, r0, AUX_STATUS_BIT_E2 + flag r0 + ld r3, [exc_nest_count] + add r2, r3, 1 + st r2, [exc_nest_count] + /* enable interrupt */ + pop r0 + flag r0 + pop r0 + + brne r3, 0, irq_handler_1 +/* change to exception stack if interrupt happened in task context */ + mov sp, _e_stack +#if ARC_FEATURE_STACK_CHECK + lr r0, [AUX_STATUS32] + bclr r0, r0, AUX_STATUS_BIT_SC + flag r0 +#endif +irq_handler_1: + PUSH blink + +/* critical area */ +#if ARC_FEATURE_CORE_700 + lr r0, [AUX_IRQ_CAUSE1] +#endif + mov r1, exc_int_handler_table + ld.as r2, [r1, r0] /* r2 = exc_int_handler_table + irqno *4 */ +/* handle software triggered interrupt */ + lr r3, [AUX_IRQ_HINT] + cmp r3, r0 + bne.d irq_hint_handled + xor r3, r3, r3 + sr r3, [AUX_IRQ_HINT] +irq_hint_handled: + + jl [r2] /* jump to interrupt handler */ +/* no interrupts are allowed from here */ +ret_int: + clri /* disable interrupt */ + + POP sp + mov r1, exc_nest_count + ld r0, [r1] + sub r0, r0, 1 + st r0, [r1] +/* if there are multi-bits set in IRQ_LV12, it's still in nest interrupt */ + lr r1, [AUX_IRQ_LV12] + + ld r0, [context_switch_reqflg] + brne r0, 0, ret_int_2 +ret_int_1: /* return from non-task context */ + INTERRUPT_EPILOGUE +#if ARC_FEATURE_CORE_600 +/* TODO: series 600 IRQ6 and IRQ7 uses ilink2 */ + rtie ilink1 +#else + rtie +#endif +/* there is a dispatch request */ +ret_int_2: + /* clear dispatch request */ + mov r0, 0 + st r0, [context_switch_reqflg] + + ld r0, [pxCurrentTCB] + breq r0, 0, ret_int_1 + +/* r1 has old AUX_IRQ_LV12 */ + PUSH r1 +/* clear related bits in IRQ_ACT manually to simulate a irq return */ + + SAVE_CALLEE_REGS /* save callee save registers */ + mov r1, ret_int_r /* save return address */ + PUSH r1 + + bl dispatcher /* r0->pxCurrentTCB */ + +ret_int_r: + RESTORE_CALLEE_REGS /* recover registers */ + POPAX AUX_IRQ_LV12 + INTERRUPT_EPILOGUE +#if ARC_FEATURE_CORE_600 + rtie ilink1 +#else + rtie +#endif + +/** @endcond */ diff --git a/portable/ThirdParty/GCC/ARC_v1/port.c b/portable/ThirdParty/GCC/ARC_v1/port.c new file mode 100644 index 000000000..39e8b771b --- /dev/null +++ b/portable/ThirdParty/GCC/ARC_v1/port.c @@ -0,0 +1,288 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * Implementation of functions defined in portable.h + */ + +#include "FreeRTOS.h" +#include "task.h" +#include "FreeRTOSConfig.h" + +#include "arc/arc_exception.h" +#include "arc/arc_timer.h" +#include "board.h" + +#include "arc_freertos_exceptions.h" + +volatile unsigned int ulCriticalNesting = 999UL; +volatile unsigned int context_switch_reqflg; /* task context switch request flag in exceptions and interrupts handling */ + +/** + * \var exc_nest_count + * \brief the counter for exc/int processing, =0 no int/exc + * >1 in int/exc processing + * @} + */ +uint32_t exc_nest_count; +/* --------------------------------------------------------------------------*/ + +/** + * @brief kernel tick interrupt handler of freertos + */ +/* ----------------------------------------------------------------------------*/ +static void vKernelTick( void * ptr ) +{ + /* clear timer interrupt */ + arc_timer_int_clear( BOARD_OS_TIMER_ID ); + board_timer_update( configTICK_RATE_HZ ); + + if( xTaskIncrementTick() ) + { + portYIELD_FROM_ISR(); /* need to make task switch */ + } +} + +/* --------------------------------------------------------------------------*/ + +/** + * @brief setup freertos kernel tick + */ +/* ----------------------------------------------------------------------------*/ +static void prvSetupTimerInterrupt( void ) +{ + unsigned int cyc = configCPU_CLOCK_HZ / configTICK_RATE_HZ; + + int_disable( BOARD_OS_TIMER_INTNO ); /* disable os timer interrupt */ + arc_timer_stop( BOARD_OS_TIMER_ID ); + arc_timer_start( BOARD_OS_TIMER_ID, TIMER_CTRL_IE | TIMER_CTRL_NH, cyc ); + + int_handler_install( BOARD_OS_TIMER_INTNO, ( INT_HANDLER_T ) vKernelTick ); + int_pri_set( BOARD_OS_TIMER_INTNO, INT_PRI_MIN ); + int_enable( BOARD_OS_TIMER_INTNO ); +} + +/* + * Setup the stack of a new task so it is ready to be placed under the + * scheduler control. The registers have to be placed on the stack in + * the order that the port expects to find them. + * + * For ARC, task context switch is implemented with the help of SWI exception + * It's not efficient but simple. + * + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* To ensure asserts in tasks.c don't fail, although in this case the assert + * is not really required. */ + pxTopOfStack--; + + /* Setup the initial stack of the task. The stack is set exactly as + * expected by the portRESTORE_CONTEXT() macro. */ + + /* When the task starts is will expect to find the function parameter in + * R0. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* function body */ + + /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) start_r; /* dispatch return address */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_NESTING; + return pxTopOfStack; +} + +/* --------------------------------------------------------------------------*/ + +/** + * @brief start the freertos scheduler, go to the first task + * + * @returns + */ +/* ----------------------------------------------------------------------------*/ +BaseType_t xPortStartScheduler( void ) +{ + /* Start the timer that generates the tick ISR. */ + prvSetupTimerInterrupt(); + start_dispatch(); + + /* Should not get here! */ + return 0; +} + +/* --------------------------------------------------------------------------*/ + +/** + * @brief + */ +/* ----------------------------------------------------------------------------*/ +void vPortEndScheduler( void ) +{ +} + +/* --------------------------------------------------------------------------*/ + +/** + * @brief generate a task switch request in ISR + */ +/* ----------------------------------------------------------------------------*/ +void vPortYieldFromIsr( void ) +{ + unsigned int status32; + + status32 = cpu_lock_save(); + context_switch_reqflg = true; + cpu_unlock_restore( status32 ); +} + +/* --------------------------------------------------------------------------*/ + +/** + * @brief + */ +/* ----------------------------------------------------------------------------*/ +void vPortYield( void ) +{ + unsigned int status32; + + status32 = cpu_lock_save(); + dispatch(); + cpu_unlock_restore( status32 ); +} + +/* --------------------------------------------------------------------------*/ + +/** + * @brief + */ +/* ----------------------------------------------------------------------------*/ +void vPortEndTask( void ) +{ + #if ( INCLUDE_vTaskDelete == 1 ) + vTaskDelete( NULL ); /* Delete task itself */ + #endif + + while( 1 ) /* Yield to other task */ + { + vPortYield(); + } +} + +#if ARC_FEATURE_STACK_CHECK + +/* + * !!! Note !!! + * This a trick!!! + * It's a copy from task.c. We need to know the definition of TCB for the purpose of hardware + * stack check. Pls don't forget to update it when FreeRTOS is updated. + */ + typedef struct tskTaskControlBlock /* The old naming convention is used to prevent breaking kernel aware debuggers. */ + { + volatile StackType_t * pxTopOfStack; /*< Points to the location of the last item placed on the tasks stack. THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */ + + #if ( portUSING_MPU_WRAPPERS == 1 ) + xMPU_SETTINGS xMPUSettings; /*< The MPU settings are defined as part of the port layer. THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */ + #endif + + ListItem_t xStateListItem; /*< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */ + ListItem_t xEventListItem; /*< Used to reference a task from an event list. */ + UBaseType_t uxPriority; /*< The priority of the task. 0 is the lowest priority. */ + StackType_t * pxStack; /*< Points to the start of the stack. */ + char pcTaskName[ configMAX_TASK_NAME_LEN ]; /*< Descriptive name given to the task when created. Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + + #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) ) + StackType_t * pxEndOfStack; /*< Points to the highest valid address for the stack. */ + #endif + + #if ( portCRITICAL_NESTING_IN_TCB == 1 ) + UBaseType_t uxCriticalNesting; /*< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */ + #endif + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxTCBNumber; /*< Stores a number that increments each time a TCB is created. It allows debuggers to determine when a task has been deleted and then recreated. */ + UBaseType_t uxTaskNumber; /*< Stores a number specifically for use by third party trace code. */ + #endif + + #if ( configUSE_MUTEXES == 1 ) + UBaseType_t uxBasePriority; /*< The priority last assigned to the task - used by the priority inheritance mechanism. */ + UBaseType_t uxMutexesHeld; + #endif + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + TaskHookFunction_t pxTaskTag; + #endif + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 ) + void * pvThreadLocalStoragePointers[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ]; + #endif + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + uint32_t ulRunTimeCounter; /*< Stores the amount of time the task has spent in the Running state. */ + #endif + + #if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) + configTLS_BLOCK_TYPE xTLSBlock; /*< Memory block used as Thread Local Storage (TLS) Block for the task. */ + #endif + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + volatile uint32_t ulNotifiedValue; + volatile uint8_t ucNotifyState; + #endif + + /* See the comments above the definition of + * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE. */ + #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ + uint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */ + #endif + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + uint8_t ucDelayAborted; + #endif + + #if ( configUSE_POSIX_ERRNO == 1 ) + int iTaskErrno; + #endif + } tskTCB; + + + void vPortSetStackCheck( TaskHandle_t old, + TaskHandle_t new ) + { + if( new != NULL ) + { + arc_aux_write( AUX_USTACK_BASE, ( uint32_t ) ( new->pxEndOfStack ) ); + arc_aux_write( AUX_USTACK_TOP, ( uint32_t ) ( new->pxStack ) ); + } + } +#endif /* if ARC_FEATURE_STACK_CHECK */ diff --git a/portable/ThirdParty/GCC/ARC_v1/portmacro.h b/portable/ThirdParty/GCC/ARC_v1/portmacro.h new file mode 100644 index 000000000..cc67ad613 --- /dev/null +++ b/portable/ThirdParty/GCC/ARC_v1/portmacro.h @@ -0,0 +1,154 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H +#include "embARC.h" + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/* record stack high address for stack check */ +#ifndef configRECORD_STACK_HIGH_ADDRESS + #define configRECORD_STACK_HIGH_ADDRESS 1 +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned int +#define portBASE_TYPE portLONG + +#ifndef Asm + #define Asm __asm__ volatile +#endif + +/* + * normal constants + */ +#ifndef NULL + #define NULL 0 /* invalid pointer */ +#endif /* NULL */ + +#ifndef true + #define true 1 /* true */ +#endif /* true */ + +#ifndef false + #define false 0 /* false */ +#endif /* false */ + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif + +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() Asm( "nop_s" ); +#define IPM_ENABLE_ALL 1 + +#define portYIELD_FROM_ISR() vPortYieldFromIsr() +#define portYIELD() vPortYield() + +/* Critical section management. */ +#define portDISABLE_INTERRUPTS() \ + { \ + arc_lock(); \ + } \ + +#define portENABLE_INTERRUPTS() \ + { \ + arc_unlock(); \ + } \ + +extern volatile unsigned int ulCriticalNesting; + +#define portENTER_CRITICAL() \ + { \ + portDISABLE_INTERRUPTS() \ + ulCriticalNesting++; \ + } + + +#define portEXIT_CRITICAL() \ + { \ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) \ + { \ + ulCriticalNesting--; \ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) \ + { \ + portENABLE_INTERRUPTS() \ + } \ + } \ + } + + +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() do {} while( 0 ) /* we use the timer */ +#define portALT_GET_RUN_TIME_COUNTER_VALUE( dest ) ( dest = xTickCount ) + +void vPortYield( void ); +void vPortYieldFromIsr( void ); + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/ThirdParty/GCC/ARM_TFM/README.md b/portable/ThirdParty/GCC/ARM_TFM/README.md new file mode 100644 index 000000000..c419a0187 --- /dev/null +++ b/portable/ThirdParty/GCC/ARM_TFM/README.md @@ -0,0 +1,80 @@ +# Target of this port + +This port adds the support that FreeRTOS applications can call the secure +services in Trusted Firmware M(TF-M) through Platform Security Architecture +(PSA) API based on the ARM Cortex-M23, Cortex-M33, Cortex-M52, Cortex-M55， +Cortex-M85 and Arm China STAR-MC3 platform. + +The Platform Security Architecture (PSA) makes it quicker, easier and cheaper +to design security into a device from the ground up. PSA is made up of four key +stages: analyze, architect, implement, and certify. See [PSA Resource Page](https://www.arm.com/architecture/security-features/platform-security). + +TF-M is an open source project. It provides a reference implementation of PSA +for Arm M-profile architecture. Please get the details from this [link](https://www.trustedfirmware.org/projects/tf-m/). + +# Derivation of the source code + +* `os_wrapper_freertos.c` + The implementation of APIs which are defined in `/interface/include/os_wrapper/mutex.h` + in trusted-firmware-m (tag: TF-Mv2.0.0). The implementation is based on + FreeRTOS mutex type semaphore. + +# Usage notes + +To build a project based on this port: +* Step 1: build the secure image. Please follow the **Build the Secure Side** section for details. +* Step 2: build the nonsecure image. Please follow the **Build the Non-Secure Side** for details. + +## Build the Secure Side + +### Get the TF-M source code + +See the [link](https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/) to get the source code. This port is supported by TF-M version **tag: TF-Mv2.0.0**. + +### Build TF-M + +Please refer to this [link](https://trustedfirmware-m.readthedocs.io/en/latest/getting_started/) to build the secure side. +_**Note:** `TFM_NS_MANAGE_NSID` must be configured as "OFF" when building TF-M_. + +## Build the Non-Secure Side + +Please copy all the files in `freertos_kernel/portable/GCC/ARM_[CM23|CM33|CM52|CM55|CM85|STAR_MC3]_NTZ` into the `freertos_kernel/portable/ThirdParty/GCC/ARM_TFM` folder before using this port. Note that TrustZone is enabled in this port. The TF-M runs in the Secure Side. + +Please call the API `tfm_ns_interface_init()` which is defined in `/interface/src/os_wrapper/tfm_ns_interface_rtos.c` by trusted-firmware-m (tag: TF-Mv2.0.0) at the very beginning of your application. Otherwise, it will always fail when calling a TF-M service in the Nonsecure Side. + +### Configuration in FreeRTOS kernel + +* `configRUN_FREERTOS_SECURE_ONLY` +This macro should be configured as 0. In this port, TF-M runs in the Secure Side while FreeRTOS +Kernel runs in the Non-Secure Side. + +* `configENABLE_FPU` +The setting of this macro is decided by the setting in Secure Side which is platform-specific. +If the Secure Side enables Non-Secure access to FPU, then this macro can be configured as 0 or 1. Otherwise, this macro can only be configured as 0. +Please note that Cortex-M23 does not support FPU. +Please refer to [TF-M documentation](https://trustedfirmware-m.readthedocs.io/en/latest/integration_guide/tfm_fpu_support.html) for FPU usage on the Non-Secure side. + +* `configENABLE_MVE` +The setting of this macro is decided by the setting in Secure Side which is platform-specific. +If the Secure Side enables Non-Secure access to MVE, then this macro can be configured as 0 or 1. Otherwise, this macro can only be configured as 0. +Please note that only Cortex-M52, Cortex-M55, Cortex-M85 and STAR-MC3 support MVE. +Please refer to [TF-M documentation](https://trustedfirmware-m.readthedocs.io/en/latest/integration_guide/tfm_fpu_support.html) for MVE usage on the Non-Secure side. + +* `configENABLE_TRUSTZONE` +This macro should be configured as 0 because TF-M doesn't use the secure context management function of FreeRTOS. New secure context management might be introduced when TF-M supports multiple secure context. + + +### Integrate TF-M Non-Secure interface with FreeRTOS project + +To enable calling TF-M services by the Non-Secure Side, the files below should be included in the FreeRTOS project and built together. +* files in `trusted-firmware-m/build/api_ns/interface/src` + These files contain the implementation of PSA Functional Developer APIs which can be called by Non-Secure Side directly and PSA Firmware Framework APIs in the IPC model. These files should be taken as part of the Non-Secure source code. +* files in `trusted-firmware-m/build/api_ns/interface/include` + These files are the necessary header files to call TF-M services. +* `trusted-firmware-m/build/api_ns/interface/lib/s_veneers.o` + This object file contains all the Non-Secure callable functions exported by + TF-M and it should be linked when generating the Non-Secure image. + + + +*Copyright (c) 2020-2024, Arm Limited. All rights reserved.* diff --git a/portable/ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c b/portable/ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c new file mode 100644 index 000000000..35add2b5a --- /dev/null +++ b/portable/ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2019-2024, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +/* + * This file contains the implementation of APIs which are defined in + * \interface/include/os_wrapper/mutex.h by TF-M(tag: TF-Mv2.0.0). + * The implementation is based on FreeRTOS mutex type semaphore. + */ + +#include "os_wrapper/mutex.h" + +#include "FreeRTOS.h" +#include "semphr.h" +#include "mpu_wrappers.h" + +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + +/* + * In the static allocation, the RAM is required to hold the semaphore's + * state. + */ + StaticSemaphore_t xSecureMutexBuffer; +#endif + +void * os_wrapper_mutex_create( void ) +{ + SemaphoreHandle_t xMutexHandle = NULL; + + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + xMutexHandle = xSemaphoreCreateMutex(); + #elif ( configSUPPORT_STATIC_ALLOCATION == 1 ) + xMutexHandle = xSemaphoreCreateMutexStatic( &xSecureMutexBuffer ); + #endif + return ( void * ) xMutexHandle; +} +/*-----------------------------------------------------------*/ + +uint32_t os_wrapper_mutex_acquire( void * handle, + uint32_t timeout ) +{ + BaseType_t xRet; + + if( !handle ) + { + return OS_WRAPPER_ERROR; + } + + xRet = xSemaphoreTake( ( SemaphoreHandle_t ) handle, + ( timeout == OS_WRAPPER_WAIT_FOREVER ) ? + portMAX_DELAY : ( TickType_t ) timeout ); + + if( xRet != pdPASS ) + { + return OS_WRAPPER_ERROR; + } + else + { + return OS_WRAPPER_SUCCESS; + } +} +/*-----------------------------------------------------------*/ + +uint32_t os_wrapper_mutex_release( void * handle ) +{ + BaseType_t xRet; + + if( !handle ) + { + return OS_WRAPPER_ERROR; + } + + xRet = xSemaphoreGive( ( SemaphoreHandle_t ) handle ); + + if( xRet != pdPASS ) + { + return OS_WRAPPER_ERROR; + } + else + { + return OS_WRAPPER_SUCCESS; + } +} +/*-----------------------------------------------------------*/ + +uint32_t os_wrapper_mutex_delete( void * handle ) +{ + vSemaphoreDelete( ( SemaphoreHandle_t ) handle ); + + return OS_WRAPPER_SUCCESS; +} +/*-----------------------------------------------------------*/ diff --git a/portable/ThirdParty/GCC/ATmega/port.c b/portable/ThirdParty/GCC/ATmega/port.c new file mode 100644 index 000000000..168bcdd94 --- /dev/null +++ b/portable/ThirdParty/GCC/ATmega/port.c @@ -0,0 +1,779 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#include + +#include +#include +#include + +#include "FreeRTOS.h" +#include "task.h" + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the AVR port. +*----------------------------------------------------------*/ + +/* Start tasks with interrupts enabled. */ +#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x80 ) + +#if defined( portUSE_WDTO ) + #warning "Watchdog Timer used for scheduler." + #define portSCHEDULER_ISR WDT_vect + +#elif defined( portUSE_TIMER0 ) +/* Hardware constants for Timer0. */ + #warning "Timer0 used for scheduler." + #define portSCHEDULER_ISR TIMER0_COMPA_vect + #define portCLEAR_COUNTER_ON_MATCH ( ( uint8_t ) _BV( WGM01 ) ) + #define portPRESCALE_1024 ( ( uint8_t ) ( _BV( CS02 ) | _BV( CS00 ) ) ) + #define portCLOCK_PRESCALER ( ( uint32_t ) 1024 ) + #define portCOMPARE_MATCH_A_INTERRUPT_ENABLE ( ( uint8_t ) _BV( OCIE0A ) ) + #define portOCRL OCR0A + #define portTCCRa TCCR0A + #define portTCCRb TCCR0B + #define portTIMSK TIMSK0 + #define portTIFR TIFR0 + +#else /* if defined( portUSE_WDTO ) */ + #error "No Timer defined for scheduler" +#endif /* if defined( portUSE_WDTO ) */ + +/*-----------------------------------------------------------*/ + +/* We require the address of the pxCurrentTCB variable, but don't want to know + * any details of its type. */ +typedef void TCB_t; +extern volatile TCB_t * volatile pxCurrentTCB; + +/*-----------------------------------------------------------*/ + +/** + * Enable the watchdog timer, configuring it for expire after + * (value) timeout (which is a combination of the WDP0 + * through WDP3 bits). + * + * This function is derived from but enables only + * the interrupt bit (WDIE), rather than the reset bit (WDE). + * + * Can't find it documented but the WDT, once enabled, + * rolls over and fires a new interrupt each time. + * + * See also the symbolic constants WDTO_15MS et al. + * + * Updated to match avr-libc 2.0.0 + */ + +#if defined( portUSE_WDTO ) + + static __inline__ + __attribute__( ( __always_inline__ ) ) + void wdt_interrupt_enable( const uint8_t value ) + { + if( _SFR_IO_REG_P( _WD_CONTROL_REG ) ) + { + __asm__ __volatile__ ( + "in __tmp_reg__,__SREG__" "\n\t" + "cli" "\n\t" + "wdr" "\n\t" + "out %0, %1" "\n\t" + "out __SREG__,__tmp_reg__" "\n\t" + "out %0, %2" "\n\t" + : /* no outputs */ + : "I" ( _SFR_IO_ADDR( _WD_CONTROL_REG ) ), + "r" ( ( uint8_t ) ( _BV( _WD_CHANGE_BIT ) | _BV( WDE ) ) ), + "r" ( ( uint8_t ) ( ( value & 0x08 ? _WD_PS3_MASK : 0x00 ) | + _BV( WDIF ) | _BV( WDIE ) | ( value & 0x07 ) ) ) + : "r0" + ); + } + else + { + __asm__ __volatile__ ( + "in __tmp_reg__,__SREG__" "\n\t" + "cli" "\n\t" + "wdr" "\n\t" + "sts %0, %1" "\n\t" + "out __SREG__,__tmp_reg__" "\n\t" + "sts %0, %2" "\n\t" + : /* no outputs */ + : "n" ( _SFR_MEM_ADDR( _WD_CONTROL_REG ) ), + "r" ( ( uint8_t ) ( _BV( _WD_CHANGE_BIT ) | _BV( WDE ) ) ), + "r" ( ( uint8_t ) ( ( value & 0x08 ? _WD_PS3_MASK : 0x00 ) | + _BV( WDIF ) | _BV( WDIE ) | ( value & 0x07 ) ) ) + : "r0" + ); + } + } +#endif /* if defined( portUSE_WDTO ) */ + +/*-----------------------------------------------------------*/ + +/** + * Enable the watchdog timer, configuring it for expire after + * (value) timeout (which is a combination of the WDP0 + * through WDP3 bits). + * + * This function is derived from but enables both + * the reset bit (WDE), and the interrupt bit (WDIE). + * + * This will ensure that if the interrupt is not serviced + * before the second timeout, the AVR will reset. + * + * Servicing the interrupt automatically clears it, + * and ensures the AVR does not reset. + * + * Can't find it documented but the WDT, once enabled, + * rolls over and fires a new interrupt each time. + * + * See also the symbolic constants WDTO_15MS et al. + * + * Updated to match avr-libc 2.0.0 + */ + +#if defined( portUSE_WDTO ) + + static __inline__ + __attribute__( ( __always_inline__ ) ) + void wdt_interrupt_reset_enable( const uint8_t value ) + { + if( _SFR_IO_REG_P( _WD_CONTROL_REG ) ) + { + __asm__ __volatile__ ( + "in __tmp_reg__,__SREG__" "\n\t" + "cli" "\n\t" + "wdr" "\n\t" + "out %0, %1" "\n\t" + "out __SREG__,__tmp_reg__" "\n\t" + "out %0, %2" "\n\t" + : /* no outputs */ + : "I" ( _SFR_IO_ADDR( _WD_CONTROL_REG ) ), + "r" ( ( uint8_t ) ( _BV( _WD_CHANGE_BIT ) | _BV( WDE ) ) ), + "r" ( ( uint8_t ) ( ( value & 0x08 ? _WD_PS3_MASK : 0x00 ) | + _BV( WDIF ) | _BV( WDIE ) | _BV( WDE ) | ( value & 0x07 ) ) ) + : "r0" + ); + } + else + { + __asm__ __volatile__ ( + "in __tmp_reg__,__SREG__" "\n\t" + "cli" "\n\t" + "wdr" "\n\t" + "sts %0, %1" "\n\t" + "out __SREG__,__tmp_reg__" "\n\t" + "sts %0, %2" "\n\t" + : /* no outputs */ + : "n" ( _SFR_MEM_ADDR( _WD_CONTROL_REG ) ), + "r" ( ( uint8_t ) ( _BV( _WD_CHANGE_BIT ) | _BV( WDE ) ) ), + "r" ( ( uint8_t ) ( ( value & 0x08 ? _WD_PS3_MASK : 0x00 ) | + _BV( WDIF ) | _BV( WDIE ) | _BV( WDE ) | ( value & 0x07 ) ) ) + : "r0" + ); + } + } +#endif /* if defined( portUSE_WDTO ) */ + +/*-----------------------------------------------------------*/ + +/* + * Macro to save all the general purpose registers, the save the stack pointer + * into the TCB. + * + * The first thing we do is save the flags then disable interrupts. This is to + * guard our stack against having a context switch interrupt after we have already + * pushed the registers onto the stack - causing the 32 registers to be on the + * stack twice. + * + * r1 is set to zero (__zero_reg__) as the compiler expects it to be thus, however + * some of the math routines make use of R1. + * + * r0 is set to __tmp_reg__ as the compiler expects it to be thus. + * + * #if defined(__AVR_HAVE_RAMPZ__) + * #define __RAMPZ__ 0x3B + * #endif + * + * #if defined(__AVR_3_BYTE_PC__) + * #define __EIND__ 0x3C + * #endif + * + * The interrupts will have been disabled during the call to portSAVE_CONTEXT() + * so we need not worry about reading/writing to the stack pointer. + */ +#if defined( __AVR_3_BYTE_PC__ ) && defined( __AVR_HAVE_RAMPZ__ ) +/* 3-Byte PC Save with RAMPZ */ + #define portSAVE_CONTEXT() \ + __asm__ __volatile__ ( "push __tmp_reg__ \n\t" \ + "in __tmp_reg__, __SREG__ \n\t" \ + "cli \n\t" \ + "push __tmp_reg__ \n\t" \ + "in __tmp_reg__, 0x3B \n\t" \ + "push __tmp_reg__ \n\t" \ + "in __tmp_reg__, 0x3C \n\t" \ + "push __tmp_reg__ \n\t" \ + "push __zero_reg__ \n\t" \ + "clr __zero_reg__ \n\t" \ + "push r2 \n\t" \ + "push r3 \n\t" \ + "push r4 \n\t" \ + "push r5 \n\t" \ + "push r6 \n\t" \ + "push r7 \n\t" \ + "push r8 \n\t" \ + "push r9 \n\t" \ + "push r10 \n\t" \ + "push r11 \n\t" \ + "push r12 \n\t" \ + "push r13 \n\t" \ + "push r14 \n\t" \ + "push r15 \n\t" \ + "push r16 \n\t" \ + "push r17 \n\t" \ + "push r18 \n\t" \ + "push r19 \n\t" \ + "push r20 \n\t" \ + "push r21 \n\t" \ + "push r22 \n\t" \ + "push r23 \n\t" \ + "push r24 \n\t" \ + "push r25 \n\t" \ + "push r26 \n\t" \ + "push r27 \n\t" \ + "push r28 \n\t" \ + "push r29 \n\t" \ + "push r30 \n\t" \ + "push r31 \n\t" \ + "lds r26, pxCurrentTCB \n\t" \ + "lds r27, pxCurrentTCB + 1 \n\t" \ + "in __tmp_reg__, __SP_L__ \n\t" \ + "st x+, __tmp_reg__ \n\t" \ + "in __tmp_reg__, __SP_H__ \n\t" \ + "st x+, __tmp_reg__ \n\t" \ + ); +#elif defined( __AVR_HAVE_RAMPZ__ ) +/* 2-Byte PC Save with RAMPZ */ + #define portSAVE_CONTEXT() \ + __asm__ __volatile__ ( "push __tmp_reg__ \n\t" \ + "in __tmp_reg__, __SREG__ \n\t" \ + "cli \n\t" \ + "push __tmp_reg__ \n\t" \ + "in __tmp_reg__, 0x3B \n\t" \ + "push __tmp_reg__ \n\t" \ + "push __zero_reg__ \n\t" \ + "clr __zero_reg__ \n\t" \ + "push r2 \n\t" \ + "push r3 \n\t" \ + "push r4 \n\t" \ + "push r5 \n\t" \ + "push r6 \n\t" \ + "push r7 \n\t" \ + "push r8 \n\t" \ + "push r9 \n\t" \ + "push r10 \n\t" \ + "push r11 \n\t" \ + "push r12 \n\t" \ + "push r13 \n\t" \ + "push r14 \n\t" \ + "push r15 \n\t" \ + "push r16 \n\t" \ + "push r17 \n\t" \ + "push r18 \n\t" \ + "push r19 \n\t" \ + "push r20 \n\t" \ + "push r21 \n\t" \ + "push r22 \n\t" \ + "push r23 \n\t" \ + "push r24 \n\t" \ + "push r25 \n\t" \ + "push r26 \n\t" \ + "push r27 \n\t" \ + "push r28 \n\t" \ + "push r29 \n\t" \ + "push r30 \n\t" \ + "push r31 \n\t" \ + "lds r26, pxCurrentTCB \n\t" \ + "lds r27, pxCurrentTCB + 1 \n\t" \ + "in __tmp_reg__, __SP_L__ \n\t" \ + "st x+, __tmp_reg__ \n\t" \ + "in __tmp_reg__, __SP_H__ \n\t" \ + "st x+, __tmp_reg__ \n\t" \ + ); +#else /* if defined( __AVR_3_BYTE_PC__ ) && defined( __AVR_HAVE_RAMPZ__ ) */ +/* 2-Byte PC Save */ + #define portSAVE_CONTEXT() \ + __asm__ __volatile__ ( "push __tmp_reg__ \n\t" \ + "in __tmp_reg__, __SREG__ \n\t" \ + "cli \n\t" \ + "push __tmp_reg__ \n\t" \ + "push __zero_reg__ \n\t" \ + "clr __zero_reg__ \n\t" \ + "push r2 \n\t" \ + "push r3 \n\t" \ + "push r4 \n\t" \ + "push r5 \n\t" \ + "push r6 \n\t" \ + "push r7 \n\t" \ + "push r8 \n\t" \ + "push r9 \n\t" \ + "push r10 \n\t" \ + "push r11 \n\t" \ + "push r12 \n\t" \ + "push r13 \n\t" \ + "push r14 \n\t" \ + "push r15 \n\t" \ + "push r16 \n\t" \ + "push r17 \n\t" \ + "push r18 \n\t" \ + "push r19 \n\t" \ + "push r20 \n\t" \ + "push r21 \n\t" \ + "push r22 \n\t" \ + "push r23 \n\t" \ + "push r24 \n\t" \ + "push r25 \n\t" \ + "push r26 \n\t" \ + "push r27 \n\t" \ + "push r28 \n\t" \ + "push r29 \n\t" \ + "push r30 \n\t" \ + "push r31 \n\t" \ + "lds r26, pxCurrentTCB \n\t" \ + "lds r27, pxCurrentTCB + 1 \n\t" \ + "in __tmp_reg__, __SP_L__ \n\t" \ + "st x+, __tmp_reg__ \n\t" \ + "in __tmp_reg__, __SP_H__ \n\t" \ + "st x+, __tmp_reg__ \n\t" \ + ); +#endif /* if defined( __AVR_3_BYTE_PC__ ) && defined( __AVR_HAVE_RAMPZ__ ) */ + +/* + * Opposite to portSAVE_CONTEXT(). Interrupts will have been disabled during + * the context save so we can write to the stack pointer. + */ +#if defined( __AVR_3_BYTE_PC__ ) && defined( __AVR_HAVE_RAMPZ__ ) +/* 3-Byte PC Restore with RAMPZ */ + #define portRESTORE_CONTEXT() \ + __asm__ __volatile__ ( "lds r26, pxCurrentTCB \n\t" \ + "lds r27, pxCurrentTCB + 1 \n\t" \ + "ld r28, x+ \n\t" \ + "out __SP_L__, r28 \n\t" \ + "ld r29, x+ \n\t" \ + "out __SP_H__, r29 \n\t" \ + "pop r31 \n\t" \ + "pop r30 \n\t" \ + "pop r29 \n\t" \ + "pop r28 \n\t" \ + "pop r27 \n\t" \ + "pop r26 \n\t" \ + "pop r25 \n\t" \ + "pop r24 \n\t" \ + "pop r23 \n\t" \ + "pop r22 \n\t" \ + "pop r21 \n\t" \ + "pop r20 \n\t" \ + "pop r19 \n\t" \ + "pop r18 \n\t" \ + "pop r17 \n\t" \ + "pop r16 \n\t" \ + "pop r15 \n\t" \ + "pop r14 \n\t" \ + "pop r13 \n\t" \ + "pop r12 \n\t" \ + "pop r11 \n\t" \ + "pop r10 \n\t" \ + "pop r9 \n\t" \ + "pop r8 \n\t" \ + "pop r7 \n\t" \ + "pop r6 \n\t" \ + "pop r5 \n\t" \ + "pop r4 \n\t" \ + "pop r3 \n\t" \ + "pop r2 \n\t" \ + "pop __zero_reg__ \n\t" \ + "pop __tmp_reg__ \n\t" \ + "out 0x3C, __tmp_reg__ \n\t" \ + "pop __tmp_reg__ \n\t" \ + "out 0x3B, __tmp_reg__ \n\t" \ + "pop __tmp_reg__ \n\t" \ + "out __SREG__, __tmp_reg__ \n\t" \ + "pop __tmp_reg__ \n\t" \ + ); +#elif defined( __AVR_HAVE_RAMPZ__ ) +/* 2-Byte PC Restore with RAMPZ */ + #define portRESTORE_CONTEXT() \ + __asm__ __volatile__ ( "lds r26, pxCurrentTCB \n\t" \ + "lds r27, pxCurrentTCB + 1 \n\t" \ + "ld r28, x+ \n\t" \ + "out __SP_L__, r28 \n\t" \ + "ld r29, x+ \n\t" \ + "out __SP_H__, r29 \n\t" \ + "pop r31 \n\t" \ + "pop r30 \n\t" \ + "pop r29 \n\t" \ + "pop r28 \n\t" \ + "pop r27 \n\t" \ + "pop r26 \n\t" \ + "pop r25 \n\t" \ + "pop r24 \n\t" \ + "pop r23 \n\t" \ + "pop r22 \n\t" \ + "pop r21 \n\t" \ + "pop r20 \n\t" \ + "pop r19 \n\t" \ + "pop r18 \n\t" \ + "pop r17 \n\t" \ + "pop r16 \n\t" \ + "pop r15 \n\t" \ + "pop r14 \n\t" \ + "pop r13 \n\t" \ + "pop r12 \n\t" \ + "pop r11 \n\t" \ + "pop r10 \n\t" \ + "pop r9 \n\t" \ + "pop r8 \n\t" \ + "pop r7 \n\t" \ + "pop r6 \n\t" \ + "pop r5 \n\t" \ + "pop r4 \n\t" \ + "pop r3 \n\t" \ + "pop r2 \n\t" \ + "pop __zero_reg__ \n\t" \ + "pop __tmp_reg__ \n\t" \ + "out 0x3B, __tmp_reg__ \n\t" \ + "pop __tmp_reg__ \n\t" \ + "out __SREG__, __tmp_reg__ \n\t" \ + "pop __tmp_reg__ \n\t" \ + ); +#else /* if defined( __AVR_3_BYTE_PC__ ) && defined( __AVR_HAVE_RAMPZ__ ) */ +/* 2-Byte PC Restore */ + #define portRESTORE_CONTEXT() \ + __asm__ __volatile__ ( "lds r26, pxCurrentTCB \n\t" \ + "lds r27, pxCurrentTCB + 1 \n\t" \ + "ld r28, x+ \n\t" \ + "out __SP_L__, r28 \n\t" \ + "ld r29, x+ \n\t" \ + "out __SP_H__, r29 \n\t" \ + "pop r31 \n\t" \ + "pop r30 \n\t" \ + "pop r29 \n\t" \ + "pop r28 \n\t" \ + "pop r27 \n\t" \ + "pop r26 \n\t" \ + "pop r25 \n\t" \ + "pop r24 \n\t" \ + "pop r23 \n\t" \ + "pop r22 \n\t" \ + "pop r21 \n\t" \ + "pop r20 \n\t" \ + "pop r19 \n\t" \ + "pop r18 \n\t" \ + "pop r17 \n\t" \ + "pop r16 \n\t" \ + "pop r15 \n\t" \ + "pop r14 \n\t" \ + "pop r13 \n\t" \ + "pop r12 \n\t" \ + "pop r11 \n\t" \ + "pop r10 \n\t" \ + "pop r9 \n\t" \ + "pop r8 \n\t" \ + "pop r7 \n\t" \ + "pop r6 \n\t" \ + "pop r5 \n\t" \ + "pop r4 \n\t" \ + "pop r3 \n\t" \ + "pop r2 \n\t" \ + "pop __zero_reg__ \n\t" \ + "pop __tmp_reg__ \n\t" \ + "out __SREG__, __tmp_reg__ \n\t" \ + "pop __tmp_reg__ \n\t" \ + ); +#endif /* if defined( __AVR_3_BYTE_PC__ ) && defined( __AVR_HAVE_RAMPZ__ ) */ +/*-----------------------------------------------------------*/ + +/* + * Perform hardware setup to enable ticks from relevant Timer. + */ +static void prvSetupTimerInterrupt( void ); +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + uint16_t usAddress; + + /* Simulate how the stack would look after a call to vPortYield() generated by + * the compiler. */ + + /* The start of the task code will be popped off the stack last, so place + * it on first. */ + usAddress = ( uint16_t ) pxCode; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + usAddress >>= 8; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + #if defined( __AVR_3_BYTE_PC__ ) + + /* The AVR ATmega2560/ATmega2561 have 256KBytes of program memory and a 17-bit + * program counter. When a code address is stored on the stack, it takes 3 bytes + * instead of 2 for the other ATmega* chips. + * + * Store 0 as the top byte since we force all task routines to the bottom 128K + * of flash. We do this by using the .lowtext label in the linker script. + * + * In order to do this properly, we would need to get a full 3-byte pointer to + * pxCode. That requires a change to GCC. Not likely to happen any time soon. + */ + *pxTopOfStack = 0; + pxTopOfStack--; + #endif + + /* Next simulate the stack as if after a call to portSAVE_CONTEXT(). + * portSAVE_CONTEXT places the flags on the stack immediately after r0 + * to ensure the interrupts get disabled as soon as possible, and so ensuring + * the stack use is minimal should a context switch interrupt occur. */ + *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */ + pxTopOfStack--; + *pxTopOfStack = portFLAGS_INT_ENABLED; + pxTopOfStack--; + + #if defined( __AVR_3_BYTE_PC__ ) + + /* If we have an ATmega256x, we are also saving the EIND register. + * We should default to 0. + */ + *pxTopOfStack = ( StackType_t ) 0x00; /* EIND */ + pxTopOfStack--; + #endif + + #if defined( __AVR_HAVE_RAMPZ__ ) + + /* We are saving the RAMPZ register. + * We should default to 0. + */ + *pxTopOfStack = ( StackType_t ) 0x00; /* RAMPZ */ + pxTopOfStack--; + #endif + + /* Now the remaining registers. The compiler expects R1 to be 0. */ + *pxTopOfStack = ( StackType_t ) 0x00; /* R1 */ + + /* Leave R2 - R23 untouched */ + pxTopOfStack -= 23; + + /* Place the parameter on the stack in the expected location. */ + usAddress = ( uint16_t ) pvParameters; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + usAddress >>= 8; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + + /* Leave register R26 - R31 untouched */ + pxTopOfStack -= 7; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Setup the relevant timer hardware to generate the tick. */ + prvSetupTimerInterrupt(); + + /* Restore the context of the first task that is going to run. */ + portRESTORE_CONTEXT(); + + /* Simulate a function call end as generated by the compiler. We will now + * jump to the start of the task the context of which we have just restored. */ + __asm__ __volatile__ ( "ret" ); + + /* Should not get here. */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ATmega port will get stopped. */ +} +/*-----------------------------------------------------------*/ + +/* + * Manual context switch. The first thing we do is save the registers so we + * can use a naked attribute. + */ +void vPortYield( void ) __attribute__( ( hot, flatten, naked ) ); +void vPortYield( void ) +{ + portSAVE_CONTEXT(); + vTaskSwitchContext(); + portRESTORE_CONTEXT(); + + __asm__ __volatile__ ( "ret" ); +} +/*-----------------------------------------------------------*/ + +/* + * Manual context switch callable from ISRs. The first thing we do is save + * the registers so we can use a naked attribute. + */ +void vPortYieldFromISR( void ) __attribute__( ( hot, flatten, naked ) ); +void vPortYieldFromISR( void ) +{ + portSAVE_CONTEXT(); + vTaskSwitchContext(); + portRESTORE_CONTEXT(); + + __asm__ __volatile__ ( "reti" ); +} +/*-----------------------------------------------------------*/ + +/* + * Context switch function used by the tick. This must be identical to + * vPortYield() from the call to vTaskSwitchContext() onwards. The only + * difference from vPortYield() is the tick count is incremented as the + * call comes from the tick ISR. + */ +void vPortYieldFromTick( void ) __attribute__( ( hot, flatten, naked ) ); +void vPortYieldFromTick( void ) +{ + portSAVE_CONTEXT(); + + if( xTaskIncrementTick() != pdFALSE ) + { + vTaskSwitchContext(); + } + + portRESTORE_CONTEXT(); + + __asm__ __volatile__ ( "ret" ); +} +/*-----------------------------------------------------------*/ + +#if defined( portUSE_WDTO ) + +/* + * Setup WDT to generate a tick interrupt. + */ + void prvSetupTimerInterrupt( void ) + { + /* reset watchdog */ + wdt_reset(); + + /* set up WDT Interrupt (rather than the WDT Reset). */ + wdt_interrupt_enable( portUSE_WDTO ); + } + +#elif defined( portUSE_TIMER0 ) + +/* + * Setup Timer0 compare match A to generate a tick interrupt. + */ + static void prvSetupTimerInterrupt( void ) + { + uint32_t ulCompareMatch; + uint8_t ucLowByte; + + /* Using 8bit Timer0 to generate the tick. Correct fuses must be + * selected for the configCPU_CLOCK_HZ clock.*/ + + ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ; + + /* We only have 8 bits so have to scale 1024 to get our required tick rate. */ + ulCompareMatch /= portCLOCK_PRESCALER; + + /* Adjust for correct value. */ + ulCompareMatch -= ( uint32_t ) 1; + + /* Setup compare match value for compare match A. Interrupts are disabled + * before this is called so we need not worry here. */ + ucLowByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff ); + portOCRL = ucLowByte; + + /* Setup clock source and compare match behaviour. */ + portTCCRa = portCLEAR_COUNTER_ON_MATCH; + portTCCRb = portPRESCALE_1024; + + + /* Enable the interrupt - this is okay as interrupt are currently globally disabled. */ + ucLowByte = portTIMSK; + ucLowByte |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE; + portTIMSK = ucLowByte; + } + +#endif /* if defined( portUSE_WDTO ) */ + +/*-----------------------------------------------------------*/ + +#if configUSE_PREEMPTION == 1 + +/* + * Tick ISR for preemptive scheduler. We can use a naked attribute as + * the context is saved at the start of vPortYieldFromTick(). The tick + * count is incremented after the context is saved. + * + * use ISR_NOBLOCK where there is an important timer running, that should preempt the scheduler. + * + */ + ISR( portSCHEDULER_ISR, ISR_NAKED ) __attribute__( ( hot, flatten ) ); + +/* ISR(portSCHEDULER_ISR, ISR_NAKED ISR_NOBLOCK) __attribute__ ((hot, flatten)); + */ + ISR( portSCHEDULER_ISR ) + { + vPortYieldFromTick(); + __asm__ __volatile__ ( "reti" ); + } +#else /* if configUSE_PREEMPTION == 1 */ + +/* + * Tick ISR for the cooperative scheduler. All this does is increment the + * tick count. We don't need to switch context, this can only be done by + * manual calls to taskYIELD(); + * + * use ISR_NOBLOCK where there is an important timer running, that should preempt the scheduler. + */ + ISR( portSCHEDULER_ISR ) __attribute__( ( hot, flatten ) ); + +/* ISR(portSCHEDULER_ISR, ISR_NOBLOCK) __attribute__ ((hot, flatten)); + */ + ISR( portSCHEDULER_ISR ) + { + xTaskIncrementTick(); + } +#endif /* if configUSE_PREEMPTION == 1 */ diff --git a/portable/ThirdParty/GCC/ATmega/portmacro.h b/portable/ThirdParty/GCC/ATmega/portmacro.h new file mode 100644 index 000000000..0cc583479 --- /dev/null +++ b/portable/ThirdParty/GCC/ATmega/portmacro.h @@ -0,0 +1,167 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +#include + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int + +#define portPOINTER_SIZE_TYPE uint16_t + +typedef uint8_t StackType_t; +typedef int8_t BaseType_t; +typedef uint8_t UBaseType_t; + +#if configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Critical section management. */ + +#define portENTER_CRITICAL() \ + __asm__ __volatile__ ( \ + "in __tmp_reg__, __SREG__" "\n\t" \ + "cli" "\n\t" \ + "push __tmp_reg__" "\n\t" \ + ::: "memory" \ + ) + + +#define portEXIT_CRITICAL() \ + __asm__ __volatile__ ( \ + "pop __tmp_reg__" "\n\t" \ + "out __SREG__, __tmp_reg__" "\n\t" \ + ::: "memory" \ + ) + + +#define portDISABLE_INTERRUPTS() __asm__ __volatile__ ( "cli" ::: "memory" ) +#define portENABLE_INTERRUPTS() __asm__ __volatile__ ( "sei" ::: "memory" ) +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ + +/* System Tick - Scheduler timer + * Prefer to use the enhanced Watchdog Timer, but also Timer0 is ok. + */ + +#if defined( WDIE ) && defined( WDIF ) /* If Enhanced WDT with interrupt capability is available */ + + #define portUSE_WDTO WDTO_15MS /* use the Watchdog Timer for xTaskIncrementTick */ + +/* Watchdog period options: WDTO_15MS + * WDTO_30MS + * WDTO_60MS + * WDTO_120MS + * WDTO_250MS + * WDTO_500MS + * WDTO_1S + * WDTO_2S + */ + +#else + + #define portUSE_TIMER0 /* use the 8-bit Timer0 for xTaskIncrementTick */ + +#endif + +#define portSTACK_GROWTH ( -1 ) + +/* Timing for the scheduler. + * Watchdog Timer is 128kHz nominal, + * but 120 kHz at 5V DC and 25 degrees is actually more accurate, + * from data sheet. + */ +#if defined( portUSE_WDTO ) + #define portTICK_PERIOD_MS ( ( TickType_t ) _BV( portUSE_WDTO + 4 ) ) +#else + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#endif + +#define portBYTE_ALIGNMENT 1 +#define portNOP() __asm__ __volatile__ ( "nop" ); +/*-----------------------------------------------------------*/ + +/* Kernel utilities. */ +extern void vPortYield( void ) __attribute__( ( naked ) ); +#define portYIELD() vPortYield() + +extern void vPortYieldFromISR( void ) __attribute__( ( naked ) ); +#define portYIELD_FROM_ISR() vPortYieldFromISR() +/*-----------------------------------------------------------*/ + +#if defined( __AVR_3_BYTE_PC__ ) +/* Task function macros as described on the FreeRTOS.org WEB site. */ + +/* Add .lowtext tag from the avr linker script avr6.x for ATmega2560 and ATmega2561 + * to make sure functions are loaded in low memory. + */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) __attribute__( ( section( ".lowtext" ) ) ) +#else + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#endif + +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/ThirdParty/GCC/ATmega/readme.md b/portable/ThirdParty/GCC/ATmega/readme.md new file mode 100644 index 000000000..ec478de9d --- /dev/null +++ b/portable/ThirdParty/GCC/ATmega/readme.md @@ -0,0 +1,86 @@ +

ATmegaxxxx

+ +__Port for generalised Microchip ATmega architecture__ + +

Description

+ +This port provides a basis for supporting all modern ATmega devices using either the Enhanced Watchdog Timer, or Timer0 (an 8-bit Timer generally available across the whole range). + +This initial commit contains the information required to build with System Tick being generated by either the: +- Watchdog Timer, or +- Timer0 - an 8-bit Timer, or +- TimerN - a 16-bit Timer which will be configured by the user. + +Further commits can add support for 16-bit Timers available on many relevant devices. The availability of these 16-bit Timers is somewhat device specific, and these complex and highly configurable Timers are often used to generate phase correct PWM timing (for example) and they would be wasted as a simple System Tick. + +The port also provides support for the 3 byte program counter devices __ATmega2560__ and __ATmega2561__. Specific to these two devices the `EIND` register need to be preserved during a context switch. Also, due to a limitation in GCC, the scheduler needs to reside in the lower 128kB of flash for both of these devices. This is achieved by adding the `.lowtext` section attribute to the function prototype. + +To build generic Microchip (AVR) ATmega support the similarities across the family must be considered, and differences respected. Some comments on the strategy follow. + +

System Tick

+ +The Microchip (AVR) ATmega family has limited Timer and Pin capabilities, and is designed to be used in physical applications, controlling hardware with PWM and recognising level and edge voltage changes. It does this mainly through the use of 16-bit Timers (for generating phase correct PWM by up/down counting), and Pins attached to Interrupts. The 8-bit Timers are also attached to Pins, and they can be used for more simple timing tasks, requiring only a single counting direction. + +The Timers not attached to Pins (and therefore not impacting the application of the device) are some 16-bit Timers (very device dependent, eg Timer3 on 1284p), The RTC Timer, and the Watch Dog Timer. + +The Watch Dog Timer is configured identically across most of the ATmega devices. It comes in two variants. 1. Old style (eg ATmega32) which does not have an Interrupt capability, and hence on these old devices cannot be used as the System Tick. and 2. New style enhanced WDT, which can generate an Interrupt, and is available on every relevant device. + +Using the Watch Dog Timer (WDT) to generate the System Tick does not impact its use as a watch dog. It can be configured to generate a System Tick interrupt, and then one period later to Reset the device if the interrupt is not serviced. + +Configuration and usage of the WDT is covered in `` which was revised in avr-libc 2.0.0. + +Two additional WDT functions are provided in `port.c`, which extend avr-libc functions to enable the WDT Interrupt without enabling Reset `wdt_interrupt_enable()`, and to enable both the Interrupt and the Reset `wdt_interrupt_reset_enable()`. + +

3 Byte PC Devices

+ +The ATtiny, ATmega, ATxmega families can optionally support both 3 byte PC and 3 byte RAM addresses. However, focusing on just the ATmega family only two devices have a large Flash requiring them to use 3 byte PC. These are the __ATmega2560__ and __ATmega2561__. This PR provides support for these two devices in two ways. + + - providing `portSAVE_CONTEXT()` and `portRESTORE_CONTEXT` saving both the __RAMPZ__ and __EIND__ registers. + - providing a `portTASK_FUNCTION_PROTO()` with the linker attribute `.lowtext` which is used to ensure that the scheduler and relevant functions remain in the lower 128kB of Flash. + +For devices which can support __XRAM__ and have the __RAMPZ__ register, this register is also preserved during the context switch. + +

Interrupt Nesting

+ +The ATmega family does not support interrupt nesting, having only one interrupt priority. This means that when the Scheduler is running, interrupts are normally disabled. + +When a very time critical process is running, based on microsecond timing generated by one of the Timers, it is important to re-enable interrupts as early as possible in processing a Yield. Fortunately, this is supported through the use of the `NO_BLOCK` decorator when defining the Interrupt Service Routine. + +The `NO_BLOCK` decorator will enable the global interrupt early in the handling of an ISR (in this case for the Scheduler), and enable interrupts to be nested. Using this method, I've been able to successfully implement an [Audio Synthesiser](https://feilipu.me/2015/06/02/goldilocks-analogue-synthesizer/) with less than 83 microseconds for each cycle, whilst still running the Scheduler to handle display and input. + +Using `NO_BLOCK` is optional, and should only be done if a critical Timer should interrupt the Scheduler. + +

Heap Management

+ +Most users of FreeRTOS will choose to manage their own heap using one of the pre-allocated heap management algorithms, but for those that choose to use `heap_3.c`, the wrappered `malloc()` method, there is an issue that needs to be addressed. + +The avr-libc library assumes that the stack will always be above the heap, and does a check for this when responding to a `malloc()` request. This is not the case when Tasks are running, as their stack is located in the early allocated heap address ranges which will be below free heap memory, and so the `malloc()` request will fail even though heap space is available. + +To avoid this issue causing `pvPort_Malloc()` to failing, the user needs to issue this tuning statement BEFORE they use the heap, or use the `xTaskCreate()` API. + +```c +if( __malloc_heap_end == 0 ) + __malloc_heap_end = (char *)(RAMEND - __malloc_margin); +``` +Unfortunately in the repository there is nowhere sensible to include this statement as it should be included early in the `main()` function. + +For devices which can support __XRAM__ the user will need to tune the location of stack and heap according to their own requirements. + +

Supported Devices

+ +ATmega devices with __ENHANCED WDT__ Interrupt capability - will use WDT. + + - ATmega8U2/16U2/32U2 -> 2kB RAM + - ATmega16U4/32U4 - Arduino Leonardo -> 2.5kB RAM + - ATmega48PB/88PB/168PB/328PB - Arduino Uno -> 2kB RAM + - ATmega164PA/324PA/644PA/1284P - Goldilocks -> __16kB RAM__ + - ATmega324PB -> 2kB RAM + - ATmega640/1280/2560/1281/2561 - Arduino Mega -> __8kB RAM + XRAM__ + +ATmega devices without enhanced __WDT__ Interrupt capability - will use a 8-bit or 16-bit Timer. + + - ATmega8A/16A/32A/64A/128A -> 4kB RAM + - ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P -> 4kB RAM + - ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P -> 4kB RAM + - ATmega808/809/1608/1609/3208/3209/4808/4809 - megaAVR 0-Series -> 6kB RAM + diff --git a/portable/ThirdParty/GCC/Posix/FreeRTOS-simulator-for-Linux.url b/portable/ThirdParty/GCC/Posix/FreeRTOS-simulator-for-Linux.url new file mode 100644 index 000000000..84cc36d60 --- /dev/null +++ b/portable/ThirdParty/GCC/Posix/FreeRTOS-simulator-for-Linux.url @@ -0,0 +1,5 @@ +[{000214A0-0000-0000-C000-000000000046}] +Prop3=19,11 +[InternetShortcut] +IDList= +URL=https://www.freertos.org/FreeRTOS-simulator-for-Linux.html diff --git a/portable/ThirdParty/GCC/Posix/port.c b/portable/ThirdParty/GCC/Posix/port.c new file mode 100644 index 000000000..a1b1ca8c7 --- /dev/null +++ b/portable/ThirdParty/GCC/Posix/port.c @@ -0,0 +1,680 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2020 Cambridge Consultants Ltd. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the Posix port. +* +* Each task has a pthread which eases use of standard debuggers +* (allowing backtraces of tasks etc). Threads for tasks that are not +* running are blocked in sigwait(). +* +* Task switch is done by resuming the thread for the next task by +* signaling the condition variable and then waiting on a condition variable +* with the current thread. +* +* The timer interrupt uses SIGALRM and care is taken to ensure that +* the signal handler runs only on the thread for the current task. +* +* Use of part of the standard C library requires care as some +* functions can take pthread mutexes internally which can result in +* deadlocks as the FreeRTOS kernel can switch tasks while they're +* holding a pthread mutex. +* +* stdio (printf() and friends) should be called from a single task +* only or serialized with a FreeRTOS primitive such as a binary +* semaphore or mutex. +* +* Note: When using LLDB (the default debugger on macOS) with this port, +* suppress SIGUSR1 to prevent debugger interference. This can be +* done by adding the following line to ~/.lldbinit: +* `process handle SIGUSR1 -n true -p false -s false` +*----------------------------------------------------------*/ +#ifdef __linux__ + #define _GNU_SOURCE +#endif +#include "portmacro.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "utils/wait_for_event.h" +/*-----------------------------------------------------------*/ + +#define SIG_RESUME SIGUSR1 + +typedef struct THREAD +{ + pthread_t pthread; + TaskFunction_t pxCode; + void * pvParams; + BaseType_t xDying; + struct event * ev; +} Thread_t; + +/* + * The additional per-thread data is stored at the beginning of the + * task's stack. + */ +static inline Thread_t * prvGetThreadFromTask( TaskHandle_t xTask ) +{ + StackType_t * pxTopOfStack = *( StackType_t ** ) xTask; + + return ( Thread_t * ) ( pxTopOfStack + 1 ); +} + +/*-----------------------------------------------------------*/ + +static pthread_once_t hSigSetupThread = PTHREAD_ONCE_INIT; +static pthread_once_t hThreadKeyOnce = PTHREAD_ONCE_INIT; +static sigset_t xAllSignals; +static sigset_t xSchedulerOriginalSignalMask; +static pthread_t hMainThread = ( pthread_t ) NULL; +static volatile BaseType_t uxCriticalNesting; +static BaseType_t xSchedulerEnd = pdFALSE; +static pthread_t hTimerTickThread; +static bool xTimerTickThreadShouldRun; +static uint64_t prvStartTimeNs; +static pthread_key_t xThreadKey = 0; +/*-----------------------------------------------------------*/ + +static void prvSetupSignalsAndSchedulerPolicy( void ); +static void prvSetupTimerInterrupt( void ); +static void * prvWaitForStart( void * pvParams ); +static void prvSwitchThread( Thread_t * xThreadToResume, + Thread_t * xThreadToSuspend ); +static void prvSuspendSelf( Thread_t * thread ); +static void prvResumeThread( Thread_t * xThreadId ); +static void vPortSystemTickHandler( int sig ); +static void vPortStartFirstTask( void ); +static void prvPortYieldFromISR( void ); +static void prvThreadKeyDestructor( void * pvData ); +static void prvInitThreadKey( void ); +static void prvMarkAsFreeRTOSThread( void ); +static BaseType_t prvIsFreeRTOSThread( void ); +static void prvDestroyThreadKey( void ); +/*-----------------------------------------------------------*/ + +static void prvThreadKeyDestructor( void * pvData ) +{ + free( pvData ); +} +/*-----------------------------------------------------------*/ + +static void prvInitThreadKey( void ) +{ + pthread_key_create( &xThreadKey, prvThreadKeyDestructor ); + /* Destroy xThreadKey when the process exits. */ + atexit( prvDestroyThreadKey ); +} +/*-----------------------------------------------------------*/ + +static void prvMarkAsFreeRTOSThread( void ) +{ + uint8_t * pucThreadData = NULL; + + ( void ) pthread_once( &hThreadKeyOnce, prvInitThreadKey ); + + pucThreadData = malloc( 1 ); + configASSERT( pucThreadData != NULL ); + + *pucThreadData = 1; + + pthread_setspecific( xThreadKey, pucThreadData ); +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvIsFreeRTOSThread( void ) +{ + uint8_t * pucThreadData = NULL; + BaseType_t xRet = pdFALSE; + + ( void ) pthread_once( &hThreadKeyOnce, prvInitThreadKey ); + + pucThreadData = ( uint8_t * ) pthread_getspecific( xThreadKey ); + + if( ( pucThreadData != NULL ) && ( *pucThreadData == 1 ) ) + { + xRet = pdTRUE; + } + + return xRet; +} +/*-----------------------------------------------------------*/ + +static void prvDestroyThreadKey( void ) +{ + pthread_key_delete( xThreadKey ); +} +/*-----------------------------------------------------------*/ + +static void prvFatalError( const char * pcCall, + int iErrno ) __attribute__( ( __noreturn__ ) ); + +void prvFatalError( const char * pcCall, + int iErrno ) +{ + fprintf( stderr, "%s: %s\n", pcCall, strerror( iErrno ) ); + abort(); +} +/*-----------------------------------------------------------*/ + +static void prvPortSetCurrentThreadName( const char * pxThreadName ) +{ + #ifdef __APPLE__ + pthread_setname_np( pxThreadName ); + #else + pthread_setname_np( pthread_self(), pxThreadName ); + #endif +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + Thread_t * thread; + pthread_attr_t xThreadAttributes; + size_t ulStackSize; + int iRet; + + ( void ) pthread_once( &hSigSetupThread, prvSetupSignalsAndSchedulerPolicy ); + + /* + * Store the additional thread data at the start of the stack. + */ + thread = ( Thread_t * ) ( pxTopOfStack + 1 ) - 1; + pxTopOfStack = ( StackType_t * ) thread - 1; + + /* Ensure that there is enough space to store Thread_t on the stack. */ + ulStackSize = ( size_t ) ( pxTopOfStack + 1 - pxEndOfStack ) * sizeof( *pxTopOfStack ); + configASSERT( ulStackSize > sizeof( Thread_t ) ); + ( void ) ulStackSize; /* suppress set but not used warning */ + + thread->pxCode = pxCode; + thread->pvParams = pvParameters; + thread->xDying = pdFALSE; + + pthread_attr_init( &xThreadAttributes ); + + thread->ev = event_create(); + + vPortEnterCritical(); + + iRet = pthread_create( &thread->pthread, &xThreadAttributes, + prvWaitForStart, thread ); + + if( iRet != 0 ) + { + prvFatalError( "pthread_create", iRet ); + } + + vPortExitCritical(); + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +void vPortStartFirstTask( void ) +{ + Thread_t * pxFirstThread = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() ); + + /* Start the first task. */ + prvResumeThread( pxFirstThread ); +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + int iSignal; + sigset_t xSignals; + + hMainThread = pthread_self(); + prvPortSetCurrentThreadName( "Scheduler" ); + + /* Start the timer that generates the tick ISR(SIGALRM). + * Interrupts are disabled here already. */ + prvSetupTimerInterrupt(); + + /* + * Block SIG_RESUME before starting any tasks so the main thread can sigwait on it. + * To sigwait on an unblocked signal is undefined. + * https://pubs.opengroup.org/onlinepubs/009604499/functions/sigwait.html + */ + sigemptyset( &xSignals ); + sigaddset( &xSignals, SIG_RESUME ); + ( void ) pthread_sigmask( SIG_BLOCK, &xSignals, NULL ); + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Wait until signaled by vPortEndScheduler(). */ + while( xSchedulerEnd != pdTRUE ) + { + sigwait( &xSignals, &iSignal ); + } + + /* + * clear out the variable that is used to end the scheduler, otherwise + * subsequent scheduler restarts will end immediately. + */ + xSchedulerEnd = pdFALSE; + + /* Reset pthread_once_t, needed to restart the scheduler again. + * memset the internal struct members for MacOS/Linux Compatibility */ + #if __APPLE__ + hSigSetupThread.__sig = _PTHREAD_ONCE_SIG_init; + hThreadKeyOnce.__sig = _PTHREAD_ONCE_SIG_init; + memset( ( void * ) &hSigSetupThread.__opaque, 0, sizeof( hSigSetupThread.__opaque ) ); + memset( ( void * ) &hThreadKeyOnce.__opaque, 0, sizeof( hThreadKeyOnce.__opaque ) ); + #else /* Linux PTHREAD library*/ + hSigSetupThread = ( pthread_once_t ) PTHREAD_ONCE_INIT; + hThreadKeyOnce = ( pthread_once_t ) PTHREAD_ONCE_INIT; + #endif /* __APPLE__*/ + + /* Restore original signal mask. */ + ( void ) pthread_sigmask( SIG_SETMASK, &xSchedulerOriginalSignalMask, NULL ); + + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + Thread_t * pxCurrentThread; + BaseType_t xIsFreeRTOSThread; + + /* Stop the timer tick thread. */ + xTimerTickThreadShouldRun = false; + pthread_join( hTimerTickThread, NULL ); + + /* Check whether the current thread is a FreeRTOS thread. + * This has to happen before the scheduler is signaled to exit + * its loop to prevent data races on the thread key. */ + xIsFreeRTOSThread = prvIsFreeRTOSThread(); + + /* Signal the scheduler to exit its loop. */ + xSchedulerEnd = pdTRUE; + ( void ) pthread_kill( hMainThread, SIG_RESUME ); + + /* Waiting to be deleted here. */ + if( xIsFreeRTOSThread == pdTRUE ) + { + pxCurrentThread = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() ); + event_wait( pxCurrentThread->ev ); + } + + pthread_testcancel(); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + if( uxCriticalNesting == 0 ) + { + vPortDisableInterrupts(); + } + + uxCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + uxCriticalNesting--; + + /* If we have reached 0 then re-enable the interrupts. */ + if( uxCriticalNesting == 0 ) + { + vPortEnableInterrupts(); + } +} +/*-----------------------------------------------------------*/ + +static void prvPortYieldFromISR( void ) +{ + Thread_t * xThreadToSuspend; + Thread_t * xThreadToResume; + + xThreadToSuspend = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() ); + + vTaskSwitchContext(); + + xThreadToResume = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() ); + + prvSwitchThread( xThreadToResume, xThreadToSuspend ); +} +/*-----------------------------------------------------------*/ + +void vPortYield( void ) +{ + /* This must never be called from outside of a FreeRTOS-owned thread, or + * the thread could get stuck in a suspended state. */ + configASSERT( prvIsFreeRTOSThread() == pdTRUE ); + + vPortEnterCritical(); + + prvPortYieldFromISR(); + + vPortExitCritical(); +} +/*-----------------------------------------------------------*/ + +void vPortDisableInterrupts( void ) +{ + if( prvIsFreeRTOSThread() == pdTRUE ) + { + pthread_sigmask( SIG_BLOCK, &xAllSignals, NULL ); + } +} +/*-----------------------------------------------------------*/ + +void vPortEnableInterrupts( void ) +{ + if( prvIsFreeRTOSThread() == pdTRUE ) + { + pthread_sigmask( SIG_UNBLOCK, &xAllSignals, NULL ); + } +} +/*-----------------------------------------------------------*/ + +UBaseType_t xPortSetInterruptMask( void ) +{ + /* Interrupts are always disabled inside ISRs (signals + * handlers). */ + return ( UBaseType_t ) 0; +} +/*-----------------------------------------------------------*/ + +void vPortClearInterruptMask( UBaseType_t uxMask ) +{ + ( void ) uxMask; +} +/*-----------------------------------------------------------*/ + +static uint64_t prvGetTimeNs( void ) +{ + struct timespec t; + + clock_gettime( CLOCK_MONOTONIC, &t ); + + return ( uint64_t ) t.tv_sec * ( uint64_t ) 1000000000UL + ( uint64_t ) t.tv_nsec; +} +/*-----------------------------------------------------------*/ + +/* commented as part of the code below in vPortSystemTickHandler, + * to adjust timing according to full demo requirements */ +/* static uint64_t prvTickCount; */ + +static void * prvTimerTickHandler( void * arg ) +{ + ( void ) arg; + + prvMarkAsFreeRTOSThread(); + + prvPortSetCurrentThreadName( "Scheduler timer" ); + + while( xTimerTickThreadShouldRun ) + { + /* + * signal to the active task to cause tick handling or + * preemption (if enabled) + */ + Thread_t * thread = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() ); + pthread_kill( thread->pthread, SIGALRM ); + usleep( portTICK_RATE_MICROSECONDS ); + } + + return NULL; +} +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +void prvSetupTimerInterrupt( void ) +{ + xTimerTickThreadShouldRun = true; + pthread_create( &hTimerTickThread, NULL, prvTimerTickHandler, NULL ); + + prvStartTimeNs = prvGetTimeNs(); +} +/*-----------------------------------------------------------*/ + +static void vPortSystemTickHandler( int sig ) +{ + if( prvIsFreeRTOSThread() == pdTRUE ) + { + Thread_t * pxThreadToSuspend; + Thread_t * pxThreadToResume; + + ( void ) sig; + + uxCriticalNesting++; /* Signals are blocked in this signal handler. */ + + pxThreadToSuspend = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() ); + + if( xTaskIncrementTick() != pdFALSE ) + { + /* Select Next Task. */ + vTaskSwitchContext(); + + pxThreadToResume = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() ); + + prvSwitchThread( pxThreadToResume, pxThreadToSuspend ); + } + + uxCriticalNesting--; + } + else + { + fprintf( stderr, "vPortSystemTickHandler called from non-FreeRTOS thread\n" ); + } +} +/*-----------------------------------------------------------*/ + +void vPortThreadDying( void * pxTaskToDelete, + volatile BaseType_t * pxPendYield ) +{ + Thread_t * pxThread = prvGetThreadFromTask( pxTaskToDelete ); + + ( void ) pxPendYield; + + pxThread->xDying = pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortCancelThread( void * pxTaskToDelete ) +{ + Thread_t * pxThreadToCancel = prvGetThreadFromTask( pxTaskToDelete ); + + /* + * The thread has already been suspended so it can be safely cancelled. + */ + pthread_cancel( pxThreadToCancel->pthread ); + event_signal( pxThreadToCancel->ev ); + pthread_join( pxThreadToCancel->pthread, NULL ); + event_delete( pxThreadToCancel->ev ); +} +/*-----------------------------------------------------------*/ + +static void * prvWaitForStart( void * pvParams ) +{ + Thread_t * pxThread = pvParams; + + prvMarkAsFreeRTOSThread(); + + prvSuspendSelf( pxThread ); + + /* Resumed for the first time, unblocks all signals. */ + uxCriticalNesting = 0; + vPortEnableInterrupts(); + + /* Set thread name */ + prvPortSetCurrentThreadName( pcTaskGetName( xTaskGetCurrentTaskHandle() ) ); + + /* Call the task's entry point. */ + pxThread->pxCode( pxThread->pvParams ); + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, so application writers can + * catch the error. */ + configASSERT( pdFALSE ); + + return NULL; +} +/*-----------------------------------------------------------*/ + +static void prvSwitchThread( Thread_t * pxThreadToResume, + Thread_t * pxThreadToSuspend ) +{ + BaseType_t uxSavedCriticalNesting; + + if( pxThreadToSuspend != pxThreadToResume ) + { + /* + * Switch tasks. + * + * The critical section nesting is per-task, so save it on the + * stack of the current (suspending thread), restoring it when + * we switch back to this task. + */ + uxSavedCriticalNesting = uxCriticalNesting; + + prvResumeThread( pxThreadToResume ); + + if( pxThreadToSuspend->xDying == pdTRUE ) + { + pthread_exit( NULL ); + } + + prvSuspendSelf( pxThreadToSuspend ); + + uxCriticalNesting = uxSavedCriticalNesting; + } +} +/*-----------------------------------------------------------*/ + +static void prvSuspendSelf( Thread_t * thread ) +{ + /* + * Suspend this thread by waiting for a pthread_cond_signal event. + * + * A suspended thread must not handle signals (interrupts) so + * all signals must be blocked by calling this from: + * + * - Inside a critical section (vPortEnterCritical() / + * vPortExitCritical()). + * + * - From a signal handler that has all signals masked. + * + * - A thread with all signals blocked with pthread_sigmask(). + */ + event_wait( thread->ev ); + pthread_testcancel(); +} + +/*-----------------------------------------------------------*/ + +static void prvResumeThread( Thread_t * xThreadId ) +{ + if( pthread_self() != xThreadId->pthread ) + { + event_signal( xThreadId->ev ); + } +} +/*-----------------------------------------------------------*/ + +static void prvSetupSignalsAndSchedulerPolicy( void ) +{ + struct sigaction sigtick; + int iRet; + + hMainThread = pthread_self(); + + /* Initialise common signal masks. */ + sigfillset( &xAllSignals ); + + /* Don't block SIGINT so this can be used to break into GDB while + * in a critical section. */ + sigdelset( &xAllSignals, SIGINT ); + + /* + * Block all signals in this thread so all new threads + * inherits this mask. + * + * When a thread is resumed for the first time, all signals + * will be unblocked. + */ + ( void ) pthread_sigmask( SIG_SETMASK, + &xAllSignals, + &xSchedulerOriginalSignalMask ); + + sigtick.sa_flags = 0; + sigtick.sa_handler = vPortSystemTickHandler; + sigfillset( &sigtick.sa_mask ); + + iRet = sigaction( SIGALRM, &sigtick, NULL ); + + if( iRet == -1 ) + { + prvFatalError( "sigaction", errno ); + } +} +/*-----------------------------------------------------------*/ + +uint32_t ulPortGetRunTime( void ) +{ + struct tms xTimes; + + times( &xTimes ); + + return ( uint32_t ) xTimes.tms_utime; +} +/*-----------------------------------------------------------*/ diff --git a/portable/ThirdParty/GCC/Posix/portmacro.h b/portable/ThirdParty/GCC/Posix/portmacro.h new file mode 100644 index 000000000..e117749fe --- /dev/null +++ b/portable/ThirdParty/GCC/Posix/portmacro.h @@ -0,0 +1,153 @@ +/* + * FreeRTOS Kernel + * Copyright 2020 Cambridge Consultants Ltd. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +#include +#include + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned long +#define portBASE_TYPE long +#define portPOINTER_SIZE_TYPE intptr_t + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +typedef unsigned long TickType_t; +#define portMAX_DELAY ( ( TickType_t ) ULONG_MAX ) + +#define portTICK_TYPE_IS_ATOMIC 1 + +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portHAS_STACK_OVERFLOW_CHECKING ( 1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portTICK_RATE_MICROSECONDS ( ( TickType_t ) 1000000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +/*-----------------------------------------------------------*/ + +/* Scheduler utilities. */ +extern void vPortYield( void ); + +#define portYIELD() vPortYield() + +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + vPortYield(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +extern void vPortDisableInterrupts( void ); +extern void vPortEnableInterrupts( void ); +#define portSET_INTERRUPT_MASK() ( vPortDisableInterrupts() ) +#define portCLEAR_INTERRUPT_MASK() ( vPortEnableInterrupts() ) + +extern UBaseType_t xPortSetInterruptMask( void ); +extern void vPortClearInterruptMask( UBaseType_t xMask ); + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +#define portSET_INTERRUPT_MASK_FROM_ISR() xPortSetInterruptMask() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortClearInterruptMask( x ) +#define portDISABLE_INTERRUPTS() portSET_INTERRUPT_MASK() +#define portENABLE_INTERRUPTS() portCLEAR_INTERRUPT_MASK() +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() + +/*-----------------------------------------------------------*/ + +extern void vPortThreadDying( void * pxTaskToDelete, + volatile BaseType_t * pxPendYield ); +extern void vPortCancelThread( void * pxTaskToDelete ); +#define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxPendYield ) vPortThreadDying( ( pvTaskToDelete ), ( pxPendYield ) ) +#define portCLEAN_UP_TCB( pxTCB ) vPortCancelThread( pxTCB ) +/*-----------------------------------------------------------*/ + +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) __attribute__( ( noreturn ) ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +/* + * Tasks run in their own pthreads and context switches between them + * are always a full memory barrier. ISRs are emulated as signals + * which also imply a full memory barrier. + * + * Thus, only a compiler barrier is needed to prevent the compiler + * reordering. + */ +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) + +extern uint32_t ulPortGetRunTime( void ); +#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() /* no-op */ +#define portGET_RUN_TIME_COUNTER_VALUE() ulPortGetRunTime() + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/ThirdParty/GCC/Posix/utils/wait_for_event.c b/portable/ThirdParty/GCC/Posix/utils/wait_for_event.c new file mode 100644 index 000000000..55fd7bbfc --- /dev/null +++ b/portable/ThirdParty/GCC/Posix/utils/wait_for_event.c @@ -0,0 +1,139 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include +#include +#include + +#include "wait_for_event.h" + +struct event +{ + pthread_mutex_t mutex; + pthread_mutexattr_t mutexattr; + pthread_cond_t cond; + bool event_triggered; +}; +/*-----------------------------------------------------------*/ + +struct event * event_create( void ) +{ + struct event * ev = malloc( sizeof( struct event ) ); + + if( ev != NULL ) + { + ev->event_triggered = false; + pthread_mutexattr_init( &ev->mutexattr ); + #ifndef __APPLE__ + pthread_mutexattr_setrobust( &ev->mutexattr, PTHREAD_MUTEX_ROBUST ); + #endif + pthread_mutex_init( &ev->mutex, &ev->mutexattr ); + pthread_cond_init( &ev->cond, NULL ); + } + + return ev; +} +/*-----------------------------------------------------------*/ + +void event_delete( struct event * ev ) +{ + pthread_mutex_destroy( &ev->mutex ); + pthread_mutexattr_destroy( &ev->mutexattr ); + pthread_cond_destroy( &ev->cond ); + free( ev ); +} +/*-----------------------------------------------------------*/ + +bool event_wait( struct event * ev ) +{ + if( pthread_mutex_lock( &ev->mutex ) == EOWNERDEAD ) + { + #ifndef __APPLE__ + /* If the thread owning the mutex died, make the mutex consistent. */ + pthread_mutex_consistent( &ev->mutex ); + #endif + } + + while( ev->event_triggered == false ) + { + pthread_cond_wait( &ev->cond, &ev->mutex ); + } + + ev->event_triggered = false; + pthread_mutex_unlock( &ev->mutex ); + return true; +} +/*-----------------------------------------------------------*/ + +bool event_wait_timed( struct event * ev, + time_t ms ) +{ + struct timespec ts; + int ret = 0; + + clock_gettime( CLOCK_REALTIME, &ts ); + ts.tv_sec += ms / 1000; + ts.tv_nsec += ( ( ms % 1000 ) * 1000000 ); + if( pthread_mutex_lock( &ev->mutex ) == EOWNERDEAD ) + { + #ifndef __APPLE__ + /* If the thread owning the mutex died, make the mutex consistent. */ + pthread_mutex_consistent( &ev->mutex ); + #endif + } + + while( ( ev->event_triggered == false ) && ( ret == 0 ) ) + { + ret = pthread_cond_timedwait( &ev->cond, &ev->mutex, &ts ); + + if( ( ret == -1 ) && ( errno == ETIMEDOUT ) ) + { + return false; + } + } + + ev->event_triggered = false; + pthread_mutex_unlock( &ev->mutex ); + return true; +} +/*-----------------------------------------------------------*/ + +void event_signal( struct event * ev ) +{ + if( pthread_mutex_lock( &ev->mutex ) == EOWNERDEAD ) + { + #ifndef __APPLE__ + /* If the thread owning the mutex died, make the mutex consistent. */ + pthread_mutex_consistent( &ev->mutex ); + #endif + } + ev->event_triggered = true; + pthread_cond_signal( &ev->cond ); + pthread_mutex_unlock( &ev->mutex ); +} +/*-----------------------------------------------------------*/ diff --git a/portable/ThirdParty/GCC/Posix/utils/wait_for_event.h b/portable/ThirdParty/GCC/Posix/utils/wait_for_event.h new file mode 100644 index 000000000..533db04f1 --- /dev/null +++ b/portable/ThirdParty/GCC/Posix/utils/wait_for_event.h @@ -0,0 +1,46 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef WAIT_FOR_EVENT_H_ +#define WAIT_FOR_EVENT_H_ + +#include +#include + +struct event; + +struct event * event_create( void ); +void event_delete( struct event * ); +bool event_wait( struct event * ev ); +bool event_wait_timed( struct event * ev, + time_t ms ); +void event_signal( struct event * ev ); + + + +#endif /* ifndef WAIT_FOR_EVENT_H_ */ diff --git a/portable/ThirdParty/GCC/RISC-V/README-for-info-on-official-MIT-license-port.txt b/portable/ThirdParty/GCC/RISC-V/README-for-info-on-official-MIT-license-port.txt new file mode 100644 index 000000000..fb6854ee0 --- /dev/null +++ b/portable/ThirdParty/GCC/RISC-V/README-for-info-on-official-MIT-license-port.txt @@ -0,0 +1,5 @@ +The official and MIT licensed FreeRTOS ports for RISC-V are located in the following directories: +\FreeRTOS\Source\portable\GCC\RISC-V +\FreeRTOS\Source\portable\IAR\RISC-V + +Also so https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html diff --git a/portable/ThirdParty/GCC/RP2040/.gitignore b/portable/ThirdParty/GCC/RP2040/.gitignore new file mode 100644 index 000000000..35eb91952 --- /dev/null +++ b/portable/ThirdParty/GCC/RP2040/.gitignore @@ -0,0 +1,2 @@ +**/cmake-* +.idea diff --git a/portable/ThirdParty/GCC/RP2040/CMakeLists.txt b/portable/ThirdParty/GCC/RP2040/CMakeLists.txt new file mode 100644 index 000000000..e1034ebad --- /dev/null +++ b/portable/ThirdParty/GCC/RP2040/CMakeLists.txt @@ -0,0 +1,53 @@ +cmake_minimum_required(VERSION 3.13) + +if (NOT TARGET _FreeRTOS_kernel_inclusion_marker) + add_library(_FreeRTOS_kernel_inclusion_marker INTERFACE) + + # Pull in PICO SDK (must be before project) + include(pico_sdk_import.cmake) + if (PICO_SDK_VERSION_STRING VERSION_LESS "1.2.0") + message(FATAL_ERROR "Require at least Raspberry Pi Pico SDK version 1.2.0") + endif() + + if (NOT FREERTOS_KERNEL_PATH) + get_filename_component(FREERTOS_KERNEL_PATH ${CMAKE_CURRENT_LIST_DIR}/../../../.. REALPATH) + endif () + + message(DEBUG "FREERTOS_KERNEL_PATH is ${FREERTOS_KERNEL_PATH}") + project(FreeRTOS-Kernel C CXX) + + set(CMAKE_C_STANDARD 11) + set(CMAKE_CXX_STANDARD 17) + + pico_is_top_level_project(FREERTOS_KERNEL_TOP_LEVEL_PROJECT) + + # if the SDK has already been initialized, then just add our libraries now - this allows + # this FreeRTOS port to just be added as a sub-directory or include within another project, rather than + # having to include it at the top level before pico_sdk_init() + if (TARGET _pico_sdk_inclusion_marker) + if (PICO_SDK_VERSION_STRING VERSION_LESS "1.3.2") + message(FATAL_ERROR "Require at least Raspberry Pi Pico SDK version 1.3.2 to include FreeRTOS after pico_sdk_init()") + endif() + include(${CMAKE_CURRENT_LIST_DIR}/library.cmake) + else() + # The real work gets done in library.cmake which is called at the end of pico_sdk_init + list(APPEND PICO_SDK_POST_LIST_FILES ${CMAKE_CURRENT_LIST_DIR}/library.cmake) + if (PICO_SDK_VERSION_STRING VERSION_LESS "1.3.2") + # We need to inject the following header file into ALL SDK files (which we do via the config header) + list(APPEND PICO_CONFIG_HEADER_FILES ${CMAKE_CURRENT_LIST_DIR}/include/freertos_sdk_config.h) + endif() + + if (FREERTOS_KERNEL_TOP_LEVEL_PROJECT) + message("FreeRTOS: initialize SDK since we're the top-level") + # Initialize the SDK + pico_sdk_init() + else() + set(FREERTOS_KERNEL_PATH ${FREERTOS_KERNEL_PATH} PARENT_SCOPE) + set(PICO_CONFIG_HEADER_FILES ${PICO_CONFIG_HEADER_FILES} PARENT_SCOPE) + set(PICO_SDK_POST_LIST_FILES ${PICO_SDK_POST_LIST_FILES} PARENT_SCOPE) + set(PICO_SDK_VERSION_MAJOR ${PICO_SDK_VERSION_MAJOR} PARENT_SCOPE) + set(PICO_SDK_VERSION_MINOR ${PICO_SDK_VERSION_MINOR} PARENT_SCOPE) + set(PICO_SDK_VERSION_REVISION ${PICO_SDK_VERSION_REVISION} PARENT_SCOPE) + endif() + endif() +endif() diff --git a/portable/ThirdParty/GCC/RP2040/FreeRTOS_Kernel_import.cmake b/portable/ThirdParty/GCC/RP2040/FreeRTOS_Kernel_import.cmake new file mode 100644 index 000000000..854aab43f --- /dev/null +++ b/portable/ThirdParty/GCC/RP2040/FreeRTOS_Kernel_import.cmake @@ -0,0 +1,91 @@ +# This is a copy of /portable/ThirdParty/GCC/RP2040/FREERTOS_KERNEL_import.cmake + +# This can be dropped into an external project to help locate the FreeRTOS kernel +# It should be include()ed prior to project(). Alternatively this file may +# or the CMakeLists.txt in this directory may be included or added via add_subdirectory +# respectively. + +if (DEFINED ENV{FREERTOS_KERNEL_PATH} AND (NOT FREERTOS_KERNEL_PATH)) + set(FREERTOS_KERNEL_PATH $ENV{FREERTOS_KERNEL_PATH}) + message("Using FREERTOS_KERNEL_PATH from environment ('${FREERTOS_KERNEL_PATH}')") +endif () + +# first pass we look in old tree; second pass we look in new tree +foreach(SEARCH_PASS RANGE 0 1) + if (SEARCH_PASS) + # ports may be moving to submodule in the future + set(FREERTOS_KERNEL_RP2040_RELATIVE_PATH "portable/ThirdParty/Community-Supported-Ports/GCC") + set(FREERTOS_KERNEL_RP2040_BACK_PATH "../../../../..") + else() + set(FREERTOS_KERNEL_RP2040_RELATIVE_PATH "portable/ThirdParty/GCC") + set(FREERTOS_KERNEL_RP2040_BACK_PATH "../../../..") + endif() + + if(PICO_PLATFORM STREQUAL "rp2040") + set(FREERTOS_KERNEL_RP2040_RELATIVE_PATH "${FREERTOS_KERNEL_RP2040_RELATIVE_PATH}/RP2040") + else() + if (PICO_PLATFORM STREQUAL "rp2350-riscv") + set(FREERTOS_KERNEL_RP2040_RELATIVE_PATH "${FREERTOS_KERNEL_RP2040_RELATIVE_PATH}/RP2350_RISC-V") + else() + set(FREERTOS_KERNEL_RP2040_RELATIVE_PATH "${FREERTOS_KERNEL_RP2040_RELATIVE_PATH}/RP2350_ARM_NTZ") + endif() + endif() + + if (NOT FREERTOS_KERNEL_PATH) + # check if we are inside the FreeRTOS kernel tree (i.e. this file has been included directly) + get_filename_component(_ACTUAL_PATH ${CMAKE_CURRENT_LIST_DIR} REALPATH) + get_filename_component(_POSSIBLE_PATH ${CMAKE_CURRENT_LIST_DIR}/${FREERTOS_KERNEL_RP2040_BACK_PATH}/${FREERTOS_KERNEL_RP2040_RELATIVE_PATH} REALPATH) + if (_ACTUAL_PATH STREQUAL _POSSIBLE_PATH) + get_filename_component(FREERTOS_KERNEL_PATH ${CMAKE_CURRENT_LIST_DIR}/${FREERTOS_KERNEL_RP2040_BACK_PATH} REALPATH) + endif() + if (_ACTUAL_PATH STREQUAL _POSSIBLE_PATH) + get_filename_component(FREERTOS_KERNEL_PATH ${CMAKE_CURRENT_LIST_DIR}/${FREERTOS_KERNEL_RP2040_BACK_PATH} REALPATH) + message("Setting FREERTOS_KERNEL_PATH to ${FREERTOS_KERNEL_PATH} based on location of FreeRTOS-Kernel-import.cmake") + break() + elseif (PICO_SDK_PATH AND EXISTS "${PICO_SDK_PATH}/../FreeRTOS-Kernel") + set(FREERTOS_KERNEL_PATH ${PICO_SDK_PATH}/../FreeRTOS-Kernel) + message("Defaulting FREERTOS_KERNEL_PATH as sibling of PICO_SDK_PATH: ${FREERTOS_KERNEL_PATH}") + break() + endif() + endif () + + if (NOT FREERTOS_KERNEL_PATH) + foreach(POSSIBLE_SUFFIX Source FreeRTOS-Kernel FreeRTOS/Source) + # check if FreeRTOS-Kernel exists under directory that included us + set(SEARCH_ROOT ${CMAKE_CURRENT_SOURCE_DIR}) + get_filename_component(_POSSIBLE_PATH ${SEARCH_ROOT}/${POSSIBLE_SUFFIX} REALPATH) + if (EXISTS ${_POSSIBLE_PATH}/${FREERTOS_KERNEL_RP2040_RELATIVE_PATH}/CMakeLists.txt) + get_filename_component(FREERTOS_KERNEL_PATH ${_POSSIBLE_PATH} REALPATH) + message("Setting FREERTOS_KERNEL_PATH to '${FREERTOS_KERNEL_PATH}' found relative to enclosing project") + break() + endif() + endforeach() + if (FREERTOS_KERNEL_PATH) + break() + endif() + endif() + + # user must have specified + if (FREERTOS_KERNEL_PATH) + if (EXISTS "${FREERTOS_KERNEL_PATH}/${FREERTOS_KERNEL_RP2040_RELATIVE_PATH}") + break() + endif() + endif() +endforeach () + +if (NOT FREERTOS_KERNEL_PATH) + message(FATAL_ERROR "FreeRTOS location was not specified. Please set FREERTOS_KERNEL_PATH.") +endif() + +set(FREERTOS_KERNEL_PATH "${FREERTOS_KERNEL_PATH}" CACHE PATH "Path to the FreeRTOS Kernel") + +get_filename_component(FREERTOS_KERNEL_PATH "${FREERTOS_KERNEL_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}") +if (NOT EXISTS ${FREERTOS_KERNEL_PATH}) + message(FATAL_ERROR "Directory '${FREERTOS_KERNEL_PATH}' not found") +endif() +if (NOT EXISTS ${FREERTOS_KERNEL_PATH}/${FREERTOS_KERNEL_RP2040_RELATIVE_PATH}/CMakeLists.txt) + message(FATAL_ERROR "Directory '${FREERTOS_KERNEL_PATH}' does not contain a '${PICO_PLATFORM}' port here: ${FREERTOS_KERNEL_RP2040_RELATIVE_PATH}") +endif() +set(FREERTOS_KERNEL_PATH ${FREERTOS_KERNEL_PATH} CACHE PATH "Path to the FreeRTOS_KERNEL" FORCE) + +add_subdirectory(${FREERTOS_KERNEL_PATH}/${FREERTOS_KERNEL_RP2040_RELATIVE_PATH} FREERTOS_KERNEL) \ No newline at end of file diff --git a/portable/ThirdParty/GCC/RP2040/LICENSE.md b/portable/ThirdParty/GCC/RP2040/LICENSE.md new file mode 100644 index 000000000..62cf25569 --- /dev/null +++ b/portable/ThirdParty/GCC/RP2040/LICENSE.md @@ -0,0 +1,23 @@ +BSD-3-Clause License + +Copyright (c) 2020-2021 Raspberry Pi (Trading) Ltd. + +Redistribution and use in source and binary forms, with or without modification, are permitted provided that the +following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following + disclaimer. + +2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following + disclaimer in the documentation and/or other materials provided with the distribution. + +3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/portable/ThirdParty/GCC/RP2040/README.md b/portable/ThirdParty/GCC/RP2040/README.md new file mode 100644 index 000000000..5db8702c5 --- /dev/null +++ b/portable/ThirdParty/GCC/RP2040/README.md @@ -0,0 +1,43 @@ +## Overview + +This directory provides an SMP FreeRTOS-Kernel port that can be used with the Raspberry Pi Pico SDK. It supports: + + * Simple CMake INTERFACE libraries, to provide the FreeRTOS-Kernel and also the individual allocator types, without copying code into the user's project. + * Running the FreeRTOS-Kernel and tasks on either core 0 or core 1, or both. + * Use of SDK synchronization primitives (such as mutexes, semaphores, queues from pico_sync) between FreeRTOS tasks and code executing on a non FreeRTOS core, or in IRQ handlers. + +Note that whilst this SMP version can be run on just a single (either) core, it is probably +more efficient to use the non SMP version in the main FreeRTOS-Kernel branch in that case. + +## Using this port + +You can copy [FreeRTOS_Kernel_import.cmake](FreeRTOS_Kernel_import.cmake) into your project, and +add the following in your `CMakeLists.txt`: + +```cmake +include(FreeRTOS_Kernel_import.cmake) +``` + +This will locate the FreeRTOS kernel if it is a direct sub-module of your project, or if you provide the +`FREERTOS_KERNEL_PATH` variable in your environment or via `-DFREERTOS_KERNEL_PATH=/path/to/FreeRTOS-Kernel` on the CMake command line. + +**NOTE:** If you are using version 1.3.1 or older of the Raspberry Pi Pico SDK then this line must appear before the +`pico_sdk_init()` and will cause FreeRTOS to be included/required in all RP2040 targets in your project. After this SDK +version, you can include the FreeRTOS-Kernel support later in your CMake build (possibly in a subdirectory) and the +FreeRTOS-Kernel support will only apply to those targets which explicitly include FreeRTOS support. + +As an alternative to the `import` statement above, you can just add this directory directly via the following (with +the same placement restrictions related to the Raspberry Pi Pico SDK version above): + +```cmake +add_subdirectory(path/to/this/directory FreeRTOS-Kernel) +``` + + +## Advanced Configuration + +Some additional `config` options are defined [here](include/rp2040_config.h) which control some low level implementation details. + +## Known Limitations + +- Tickless idle has not currently been tested, and is likely non-functional diff --git a/portable/ThirdParty/GCC/RP2040/include/freertos_sdk_config.h b/portable/ThirdParty/GCC/RP2040/include/freertos_sdk_config.h new file mode 100644 index 000000000..71ca3277e --- /dev/null +++ b/portable/ThirdParty/GCC/RP2040/include/freertos_sdk_config.h @@ -0,0 +1,77 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + */ + +#ifndef FREERTOS_SDK_CONFIG_H +#define FREERTOS_SDK_CONFIG_H + +#ifndef __ASSEMBLER__ + #include "FreeRTOSConfig.h" + #include "rp2040_config.h" + #ifndef PICO_USE_MALLOC_MUTEX + /* malloc needs to be made thread safe */ + #define PICO_USE_MALLOC_MUTEX 1 + #endif /* PICO_USE_MALLOC_MUTEX */ + #if ( configSUPPORT_PICO_SYNC_INTEROP == 1 ) + /* increase the amount of time it may reasonably take to wake us up */ + #ifndef PICO_TIME_SLEEP_OVERHEAD_ADJUST_US + #define PICO_TIME_SLEEP_OVERHEAD_ADJUST_US 150 + #endif + + #define lock_owner_id_t uint32_t + extern uint32_t ulPortLockGetCurrentOwnerId( void ); + #define lock_get_caller_owner_id() ulPortLockGetCurrentOwnerId() + #define LOCK_INVALID_OWNER_ID ( ( uint32_t ) -1 ) + + struct lock_core; + #ifndef lock_internal_spin_unlock_with_wait + extern void vPortLockInternalSpinUnlockWithWait( struct lock_core * pxLock, + uint32_t ulSave ); + #define lock_internal_spin_unlock_with_wait( lock, save ) vPortLockInternalSpinUnlockWithWait( lock, save ) + #endif + + #ifndef lock_internal_spin_unlock_with_notify + extern void vPortLockInternalSpinUnlockWithNotify( struct lock_core * pxLock, + uint32_t save ); + #define lock_internal_spin_unlock_with_notify( lock, save ) vPortLockInternalSpinUnlockWithNotify( lock, save ); + #endif + + #ifndef lock_internal_spin_unlock_with_best_effort_wait_or_timeout + extern bool xPortLockInternalSpinUnlockWithBestEffortWaitOrTimeout( struct lock_core * pxLock, + uint32_t ulSave, + absolute_time_t uxUntil ); + #define lock_internal_spin_unlock_with_best_effort_wait_or_timeout( lock, save, until ) \ + xPortLockInternalSpinUnlockWithBestEffortWaitOrTimeout( lock, save, until ) + #endif + #endif /* configSUPPORT_PICO_SYNC_INTEROP */ + + #if ( configSUPPORT_PICO_TIME_INTEROP == 1 ) + extern void xPortSyncInternalYieldUntilBefore( absolute_time_t t ); + #define sync_internal_yield_until_before( t ) xPortSyncInternalYieldUntilBefore( t ) + #endif /* configSUPPORT_PICO_TIME_INTEROP */ +#endif /* __ASSEMBLER__ */ +#endif /* ifndef FREERTOS_SDK_CONFIG_H */ diff --git a/portable/ThirdParty/GCC/RP2040/include/portmacro.h b/portable/ThirdParty/GCC/RP2040/include/portmacro.h new file mode 100644 index 000000000..d8173716e --- /dev/null +++ b/portable/ThirdParty/GCC/RP2040/include/portmacro.h @@ -0,0 +1,293 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: MIT AND BSD-3-Clause + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +#include "pico.h" +#include "hardware/sync.h" +#include "rp2040_config.h" + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef int32_t BaseType_t; +typedef uint32_t UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portDONT_DISCARD __attribute__( ( used ) ) + +/* We have to use PICO_DIVIDER_DISABLE_INTERRUPTS as the source of truth rather than our config, + * as our FreeRTOSConfig.h header cannot be included by ASM code - which is what this affects in the SDK */ +#define portUSE_DIVIDER_SAVE_RESTORE !PICO_DIVIDER_DISABLE_INTERRUPTS +#if portUSE_DIVIDER_SAVE_RESTORE + #define portSTACK_LIMIT_PADDING 4 +#endif + +/*-----------------------------------------------------------*/ + + +/* Scheduler utilities. */ +extern void vPortYield( void ); +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portYIELD() vPortYield() +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) + +/*-----------------------------------------------------------*/ + +/* Exception handlers */ +#if ( configUSE_DYNAMIC_EXCEPTION_HANDLERS == 0 ) + /* We only need to override the SDK's weak functions if we want to replace them at compile time */ + #define vPortSVCHandler isr_svcall + #define xPortPendSVHandler isr_pendsv + #define xPortSysTickHandler isr_systick +#endif + +/*-----------------------------------------------------------*/ + +/* Multi-core */ +#define portMAX_CORE_COUNT 2 + +/* Check validity of number of cores specified in config */ +#if ( configNUMBER_OF_CORES < 1 || portMAX_CORE_COUNT < configNUMBER_OF_CORES ) + #error "Invalid number of cores specified in config!" +#endif + +#if ( configTICK_CORE < 0 || configTICK_CORE > configNUMBER_OF_CORES ) + #error "Invalid tick core specified in config!" +#endif +/* FreeRTOS core id is always zero based, so always 0 if we're running on only one core */ +#if configNUMBER_OF_CORES == portMAX_CORE_COUNT + #define portGET_CORE_ID() get_core_num() +#else + #define portGET_CORE_ID() 0 +#endif + +#define portCHECK_IF_IN_ISR() \ + ( { \ + uint32_t ulIPSR; \ + __asm volatile ( "mrs %0, IPSR" : "=r" ( ulIPSR )::); \ + ( ( uint8_t ) ulIPSR ) > 0; } ) + +/* Use #define rather than inline method to make it easier for user code + * to work with kernel versions both with and without xPortIsInsideInterrupt */ +#define xPortIsInsideInterrupt() ((BaseType_t)portCHECK_IF_IN_ISR()) + +void vYieldCore( int xCoreID ); +#define portYIELD_CORE( a ) vYieldCore( a ) + +/*-----------------------------------------------------------*/ + +/* Critical nesting count management. */ +#define portCRITICAL_NESTING_IN_TCB 0 + +extern UBaseType_t uxCriticalNestings[ configNUMBER_OF_CORES ]; +#define portGET_CRITICAL_NESTING_COUNT( xCoreID ) ( uxCriticalNestings[ ( xCoreID ) ] ) +#define portSET_CRITICAL_NESTING_COUNT( xCoreID, x ) ( uxCriticalNestings[ ( xCoreID ) ] = ( x ) ) +#define portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( uxCriticalNestings[ ( xCoreID ) ]++ ) +#define portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( uxCriticalNestings[ ( xCoreID ) ]-- ) + +/*-----------------------------------------------------------*/ + +/* Critical section management. */ + +#define portSET_INTERRUPT_MASK() \ + ( { \ + uint32_t ulState; \ + __asm volatile ( "mrs %0, PRIMASK" : "=r" ( ulState )::); \ + __asm volatile ( " cpsid i " ::: "memory" ); \ + ulState; } ) + +#define portCLEAR_INTERRUPT_MASK( ulState ) __asm volatile ( "msr PRIMASK,%0" ::"r" ( ulState ) : ) + +extern uint32_t ulSetInterruptMaskFromISR( void ) __attribute__( ( naked ) ); +extern void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__( ( naked ) ); +#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMaskFromISR( x ) + +#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" ) +#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" ) + +#if ( configNUMBER_OF_CORES == 1 ) + extern void vPortEnterCritical( void ); + extern void vPortExitCritical( void ); + #define portENTER_CRITICAL() vPortEnterCritical() + #define portEXIT_CRITICAL() vPortExitCritical() +#else + extern void vTaskEnterCritical( void ); + extern void vTaskExitCritical( void ); + extern UBaseType_t vTaskEnterCriticalFromISR( void ); + extern void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus ); + #define portENTER_CRITICAL() vTaskEnterCritical() + #define portEXIT_CRITICAL() vTaskExitCritical() + #define portENTER_CRITICAL_FROM_ISR() vTaskEnterCriticalFromISR() + #define portEXIT_CRITICAL_FROM_ISR( x ) vTaskExitCriticalFromISR( x ) +#endif /* if ( configNUMBER_OF_CORES == 1 ) */ + +#define portRTOS_SPINLOCK_COUNT 2 + +#if PICO_SDK_VERSION_MAJOR < 2 +__force_inline static bool spin_try_lock_unsafe(spin_lock_t *lock) { + return *lock; +} +#endif + +/* Note this is a single method with uxAcquire parameter since we have + * static vars, the method is always called with a compile time constant for + * uxAcquire, and the compiler should do the right thing! */ +static inline void vPortRecursiveLock( BaseType_t xCoreID, + uint32_t ulLockNum, + spin_lock_t * pxSpinLock, + BaseType_t uxAcquire ) +{ + static volatile uint8_t ucOwnedByCore[ portMAX_CORE_COUNT ][portRTOS_SPINLOCK_COUNT]; + static volatile uint8_t ucRecursionCountByLock[ portRTOS_SPINLOCK_COUNT ]; + + configASSERT( ulLockNum < portRTOS_SPINLOCK_COUNT ); + + if( uxAcquire ) + { + if (!spin_try_lock_unsafe(pxSpinLock)) { + if( ucOwnedByCore[ xCoreID ][ ulLockNum ] ) + { + configASSERT( ucRecursionCountByLock[ ulLockNum ] != 255u ); + ucRecursionCountByLock[ ulLockNum ] = ucRecursionCountByLock[ ulLockNum ] + 1; + return; + } + spin_lock_unsafe_blocking(pxSpinLock); + } + configASSERT( ucRecursionCountByLock[ ulLockNum ] == 0 ); + ucRecursionCountByLock[ ulLockNum ] = 1; + ucOwnedByCore[ xCoreID ][ ulLockNum ] = 1; + } + else + { + configASSERT( ( ucOwnedByCore[ xCoreID ] [ulLockNum ] ) != 0 ); + configASSERT( ucRecursionCountByLock[ ulLockNum ] != 0 ); + + ucRecursionCountByLock[ ulLockNum ] = ucRecursionCountByLock[ ulLockNum ] - 1; + if ( ucRecursionCountByLock[ ulLockNum ] == 0U ) + { + ucOwnedByCore[ xCoreID ] [ ulLockNum ] = 0; + spin_unlock_unsafe(pxSpinLock); + } + } +} + +#if ( configNUMBER_OF_CORES == 1 ) + #define portGET_ISR_LOCK( xCoreID ) + #define portRELEASE_ISR_LOCK( xCoreID ) + #define portGET_TASK_LOCK( xCoreID ) + #define portRELEASE_TASK_LOCK( xCoreID ) +#else + #define portGET_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( xCoreID ), 0, spin_lock_instance( configSMP_SPINLOCK_0 ), pdTRUE ) + #define portRELEASE_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( xCoreID ), 0, spin_lock_instance( configSMP_SPINLOCK_0 ), pdFALSE ) + #define portGET_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( xCoreID ), 1, spin_lock_instance( configSMP_SPINLOCK_1 ), pdTRUE ) + #define portRELEASE_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( xCoreID ), 1, spin_lock_instance( configSMP_SPINLOCK_1 ), pdFALSE ) +#endif + +/*-----------------------------------------------------------*/ + +/* Tickless idle/low power functionality. */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +#define portNOP() __asm volatile ( "nop" ) + +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/ThirdParty/GCC/RP2040/include/rp2040_config.h b/portable/ThirdParty/GCC/RP2040/include/rp2040_config.h new file mode 100644 index 000000000..b2159a94e --- /dev/null +++ b/portable/ThirdParty/GCC/RP2040/include/rp2040_config.h @@ -0,0 +1,94 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: MIT AND BSD-3-Clause + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + */ + +#ifndef RP2040_CONFIG_H +#define RP2040_CONFIG_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/* configUSE_DYNAMIC_EXCEPTION_HANDLERS == 1 means set the exception handlers dynamically on cores + * that need them in case the user has set up distinct vector table offsets per core + */ +#ifndef configUSE_DYNAMIC_EXCEPTION_HANDLERS + #if defined( PICO_NO_RAM_VECTOR_TABLE ) && ( PICO_NO_RAM_VECTOR_TABLE == 1 ) + #define configUSE_DYNAMIC_EXCEPTION_HANDLERS 0 + #else + #define configUSE_DYNAMIC_EXCEPTION_HANDLERS 1 + #endif +#endif + +/* configSUPPORT_PICO_SYNC_INTEROP == 1 means that SDK pico_sync + * sem/mutex/queue etc. will work correctly when called from FreeRTOS tasks + */ +#ifndef configSUPPORT_PICO_SYNC_INTEROP + #if LIB_PICO_SYNC + #define configSUPPORT_PICO_SYNC_INTEROP 1 + #endif +#endif + +/* configSUPPORT_PICO_SYNC_INTEROP == 1 means that SDK pico_time + * sleep_ms/sleep_us/sleep_until will work correctly when called from FreeRTOS + * tasks, and will actually block at the FreeRTOS level + */ +#ifndef configSUPPORT_PICO_TIME_INTEROP + #if LIB_PICO_TIME + #define configSUPPORT_PICO_TIME_INTEROP 1 + #endif +#endif + +#if ( configNUMBER_OF_CORES > 1 ) + +/* configTICK_CORE indicates which core should handle the SysTick + * interrupts */ + #ifndef configTICK_CORE + #define configTICK_CORE 0 + #endif +#endif + +/* This SMP port requires two spin locks, which are claimed from the SDK. + * the spin lock numbers to be used are defined statically and defaulted here + * to the values nominally set aside for RTOS by the SDK */ +#ifndef configSMP_SPINLOCK_0 + #define configSMP_SPINLOCK_0 PICO_SPINLOCK_ID_OS1 +#endif + +#ifndef configSMP_SPINLOCK_1 + #define configSMP_SPINLOCK_1 PICO_SPINLOCK_ID_OS2 +#endif + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* ifndef RP2040_CONFIG_H */ diff --git a/portable/ThirdParty/GCC/RP2040/library.cmake b/portable/ThirdParty/GCC/RP2040/library.cmake new file mode 100644 index 000000000..33968de85 --- /dev/null +++ b/portable/ThirdParty/GCC/RP2040/library.cmake @@ -0,0 +1,72 @@ +# Copyright (c) 2020 Raspberry Pi (Trading) Ltd. +# +# SPDX-License-Identifier: BSD-3-Clause + +# Called after the Raspberry Pi Pico SDK has been initialized to add our libraries + +add_library(FreeRTOS-Kernel-Core INTERFACE) +target_sources(FreeRTOS-Kernel-Core INTERFACE + ${FREERTOS_KERNEL_PATH}/croutine.c + ${FREERTOS_KERNEL_PATH}/event_groups.c + ${FREERTOS_KERNEL_PATH}/list.c + ${FREERTOS_KERNEL_PATH}/queue.c + ${FREERTOS_KERNEL_PATH}/stream_buffer.c + ${FREERTOS_KERNEL_PATH}/tasks.c + ${FREERTOS_KERNEL_PATH}/timers.c + ) +target_include_directories(FreeRTOS-Kernel-Core INTERFACE ${FREERTOS_KERNEL_PATH}/include) + +if (PICO_SDK_VERSION_STRING VERSION_GREATER_EQUAL "1.3.2") + target_compile_definitions(FreeRTOS-Kernel-Core INTERFACE + PICO_CONFIG_RTOS_ADAPTER_HEADER=${CMAKE_CURRENT_LIST_DIR}/include/freertos_sdk_config.h) +endif() + +add_library(FreeRTOS-Kernel INTERFACE) +target_sources(FreeRTOS-Kernel INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/port.c +) + +target_include_directories(FreeRTOS-Kernel INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/include + ${FREERTOS_CONFIG_FILE_DIRECTORY}) + +target_link_libraries(FreeRTOS-Kernel INTERFACE + FreeRTOS-Kernel-Core + pico_base_headers + hardware_clocks + hardware_exception + pico_multicore +) + +target_compile_definitions(FreeRTOS-Kernel INTERFACE + LIB_FREERTOS_KERNEL=1 + FREE_RTOS_KERNEL_SMP=1 +) + +add_library(FreeRTOS-Kernel-Static INTERFACE) +target_compile_definitions(FreeRTOS-Kernel-Static INTERFACE + configSUPPORT_STATIC_ALLOCATION=1 + configKERNEL_PROVIDED_STATIC_MEMORY=1 + ) + +target_link_libraries(FreeRTOS-Kernel-Static INTERFACE FreeRTOS-Kernel) + +add_library(FreeRTOS-Kernel-Heap1 INTERFACE) +target_sources(FreeRTOS-Kernel-Heap1 INTERFACE ${FREERTOS_KERNEL_PATH}/portable/MemMang/heap_1.c) +target_link_libraries(FreeRTOS-Kernel-Heap1 INTERFACE FreeRTOS-Kernel) + +add_library(FreeRTOS-Kernel-Heap2 INTERFACE) +target_sources(FreeRTOS-Kernel-Heap2 INTERFACE ${FREERTOS_KERNEL_PATH}/portable/MemMang/heap_2.c) +target_link_libraries(FreeRTOS-Kernel-Heap2 INTERFACE FreeRTOS-Kernel) + +add_library(FreeRTOS-Kernel-Heap3 INTERFACE) +target_sources(FreeRTOS-Kernel-Heap3 INTERFACE ${FREERTOS_KERNEL_PATH}/portable/MemMang/heap_3.c) +target_link_libraries(FreeRTOS-Kernel-Heap3 INTERFACE FreeRTOS-Kernel) + +add_library(FreeRTOS-Kernel-Heap4 INTERFACE) +target_sources(FreeRTOS-Kernel-Heap4 INTERFACE ${FREERTOS_KERNEL_PATH}/portable/MemMang/heap_4.c) +target_link_libraries(FreeRTOS-Kernel-Heap4 INTERFACE FreeRTOS-Kernel) + +add_library(FreeRTOS-Kernel-Heap5 INTERFACE) +target_sources(FreeRTOS-Kernel-Heap5 INTERFACE ${FREERTOS_KERNEL_PATH}/portable/MemMang/heap_5.c) +target_link_libraries(FreeRTOS-Kernel-Heap5 INTERFACE FreeRTOS-Kernel) diff --git a/portable/ThirdParty/GCC/RP2040/pico_sdk_import.cmake b/portable/ThirdParty/GCC/RP2040/pico_sdk_import.cmake new file mode 100644 index 000000000..e6c7a66ea --- /dev/null +++ b/portable/ThirdParty/GCC/RP2040/pico_sdk_import.cmake @@ -0,0 +1,66 @@ +# Copyright (c) 2020 Raspberry Pi (Trading) Ltd. +# +# SPDX-License-Identifier: BSD-3-Clause + +# This is a copy of /external/pico_sdk_import.cmake + +# This can be dropped into an external project to help locate this SDK +# It should be include()ed prior to project() + +if (DEFINED ENV{PICO_SDK_PATH} AND (NOT PICO_SDK_PATH)) + set(PICO_SDK_PATH $ENV{PICO_SDK_PATH}) + message("Using PICO_SDK_PATH from environment ('${PICO_SDK_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT} AND (NOT PICO_SDK_FETCH_FROM_GIT)) + set(PICO_SDK_FETCH_FROM_GIT $ENV{PICO_SDK_FETCH_FROM_GIT}) + message("Using PICO_SDK_FETCH_FROM_GIT from environment ('${PICO_SDK_FETCH_FROM_GIT}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_PATH} AND (NOT PICO_SDK_FETCH_FROM_GIT_PATH)) + set(PICO_SDK_FETCH_FROM_GIT_PATH $ENV{PICO_SDK_FETCH_FROM_GIT_PATH}) + message("Using PICO_SDK_FETCH_FROM_GIT_PATH from environment ('${PICO_SDK_FETCH_FROM_GIT_PATH}')") +endif () + +set(PICO_SDK_PATH "${PICO_SDK_PATH}" CACHE PATH "Path to the Raspberry Pi Pico SDK") +set(PICO_SDK_FETCH_FROM_GIT "${PICO_SDK_FETCH_FROM_GIT}" CACHE BOOL "Set to ON to fetch copy of SDK from git if not otherwise locatable") +set(PICO_SDK_FETCH_FROM_GIT_PATH "${PICO_SDK_FETCH_FROM_GIT_PATH}" CACHE FILEPATH "location to download SDK") + +if (NOT PICO_SDK_PATH) + if (PICO_SDK_FETCH_FROM_GIT) + include(FetchContent) + set(FETCHCONTENT_BASE_DIR_SAVE ${FETCHCONTENT_BASE_DIR}) + if (PICO_SDK_FETCH_FROM_GIT_PATH) + get_filename_component(FETCHCONTENT_BASE_DIR "${PICO_SDK_FETCH_FROM_GIT_PATH}" REALPATH BASE_DIR "${CMAKE_SOURCE_DIR}") + endif () + FetchContent_Declare( + pico_sdk + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG master + ) + if (NOT pico_sdk) + message("Downloading Raspberry Pi Pico SDK") + FetchContent_Populate(pico_sdk) + set(PICO_SDK_PATH ${pico_sdk_SOURCE_DIR}) + endif () + set(FETCHCONTENT_BASE_DIR ${FETCHCONTENT_BASE_DIR_SAVE}) + else () + message(FATAL_ERROR + "SDK location was not specified. Please set PICO_SDK_PATH or set PICO_SDK_FETCH_FROM_GIT to on to fetch from git." + ) + endif () +endif () + +get_filename_component(PICO_SDK_PATH "${PICO_SDK_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}") +if (NOT EXISTS ${PICO_SDK_PATH}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' not found") +endif () + +set(PICO_SDK_INIT_CMAKE_FILE ${PICO_SDK_PATH}/pico_sdk_init.cmake) +if (NOT EXISTS ${PICO_SDK_INIT_CMAKE_FILE}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' does not appear to contain the Raspberry Pi Pico SDK") +endif () + +set(PICO_SDK_PATH ${PICO_SDK_PATH} CACHE PATH "Path to the Raspberry Pi Pico SDK" FORCE) + +include(${PICO_SDK_INIT_CMAKE_FILE}) diff --git a/portable/ThirdParty/GCC/RP2040/port.c b/portable/ThirdParty/GCC/RP2040/port.c new file mode 100644 index 000000000..66d633720 --- /dev/null +++ b/portable/ThirdParty/GCC/RP2040/port.c @@ -0,0 +1,1160 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: MIT AND BSD-3-Clause + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*---------------------------------------------------------------------- + * Implementation of functions defined in portable.h for the RP2040 port. + *----------------------------------------------------------------------*/ + +#include "FreeRTOS.h" +#include "task.h" +#include "rp2040_config.h" +#include "hardware/clocks.h" +#include "hardware/exception.h" + +/* + * LIB_PICO_MULTICORE == 1, if we are linked with pico_multicore (note that + * the non SMP FreeRTOS_Kernel is not linked with pico_multicore itself). We + * use this flag to determine if we need multi-core functionality. + */ +#if ( LIB_PICO_MULTICORE == 1 ) + #include "pico/multicore.h" +#endif /* LIB_PICO_MULTICORE */ + +/* Constants required to manipulate the NVIC. */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) + +/* The systick is a 24-bit counter. */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/* A fiddle factor to estimate the number of SysTick counts that would have + * occurred while the SysTick counter is stopped during tickless idle + * calculations. */ +#ifndef portMISSED_COUNTS_FACTOR + #define portMISSED_COUNTS_FACTOR ( 45UL ) +#endif + +/* Let the user override the pre-loading of the initial LR with the address of + * prvTaskExitError() in case it messes up unwinding of the stack in the + * debugger. */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ); + +/* + * Exception handlers. + */ +void xPortPendSVHandler( void ) __attribute__( ( naked ) ); +void xPortSysTickHandler( void ); +void vPortSVCHandler( void ); + +/* + * Start first task is a separate function so it can be tested in isolation. + */ +static void vPortStartFirstTask( void ) __attribute__( ( naked ) ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* Each task maintains its own interrupt status in the critical nesting + * variable. This is initialized to 0 to allow vPortEnter/ExitCritical + * to be called before the scheduler is started */ +#if ( configNUMBER_OF_CORES == 1 ) + static UBaseType_t uxCriticalNesting; +#else /* #if ( configNUMBER_OF_CORES == 1 ) */ +UBaseType_t uxCriticalNestings[ configNUMBER_OF_CORES ] = { 0 }; +#endif /* #if ( configNUMBER_OF_CORES == 1 ) */ + +/*-----------------------------------------------------------*/ + +#if ( configSUPPORT_PICO_SYNC_INTEROP == 1 || configNUMBER_OF_CORES > 1 ) + #include "hardware/irq.h" +#endif /* ( configSUPPORT_PICO_SYNC_INTEROP == 1 || configNUMBER_OF_CORES > 1 ) */ +#if ( configSUPPORT_PICO_SYNC_INTEROP == 1 ) + #include "pico/lock_core.h" + #include "event_groups.h" + #if configSUPPORT_STATIC_ALLOCATION + static StaticEventGroup_t xStaticEventGroup; + #define pEventGroup ( &xStaticEventGroup ) + #endif /* configSUPPORT_STATIC_ALLOCATION */ + static EventGroupHandle_t xEventGroup; + #if ( configNUMBER_OF_CORES == 1 ) + static EventBits_t uxCrossCoreEventBits; + static spin_lock_t * pxCrossCoreSpinLock; /* protects uxCrossCoreEventBits */ + #endif +#endif /* configSUPPORT_PICO_SYNC_INTEROP */ + +/* + * The number of SysTick increments that make up one tick period. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulTimerCountsForOneTick = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * The maximum number of tick periods that can be suppressed is limited by the + * 24 bit resolution of the SysTick timer. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t xMaximumPossibleSuppressedTicks = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Compensate for the CPU cycles that pass while the SysTick is stopped (low + * power functionality only. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/*-----------------------------------------------------------*/ + +#define INVALID_PRIMARY_CORE_NUM 0xffu +/* The primary core number (the own which has the SysTick handler) */ +static uint8_t ucPrimaryCoreNum = INVALID_PRIMARY_CORE_NUM; + +/* Note: portIS_FREE_RTOS_CORE() also returns false until the scheduler is started */ +#if ( configNUMBER_OF_CORES != 1 ) + #define portIS_FREE_RTOS_CORE() ( ucPrimaryCoreNum != INVALID_PRIMARY_CORE_NUM ) +#else + #define portIS_FREE_RTOS_CORE() ( ucPrimaryCoreNum == get_core_num() ) +#endif + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack -= 8; /* R11..R4. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). */ + panic_unsupported(); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler( void ) +{ + /* This function is no longer used, but retained for backward + * compatibility. */ +} +/*-----------------------------------------------------------*/ + +void vPortStartFirstTask( void ) +{ + #if ( configNUMBER_OF_CORES == 1 ) + __asm volatile ( + " .syntax unified \n" + " ldr r2, pxCurrentTCBConst1 \n" /* Obtain location of pxCurrentTCB. */ + " ldr r3, [r2] \n" + " ldr r0, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. */ + " adds r0, #32 \n" /* Discard everything up to r0. */ + " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */ + " movs r0, #2 \n" /* Switch to the psp stack. */ + " msr CONTROL, r0 \n" + " isb \n" + " pop {r0-r5} \n" /* Pop the registers that are saved automatically. */ + " mov lr, r5 \n" /* lr is now in r5. */ + " pop {r3} \n" /* Return address is now in r3. */ + " pop {r2} \n" /* Pop and discard XPSR. */ + " cpsie i \n" /* The first task has its context and interrupts can be enabled. */ + " bx r3 \n" /* Finally, jump to the user defined task code. */ + " .align 4 \n" + "pxCurrentTCBConst1: .word pxCurrentTCB\n" + ); + #else /* if ( configNUMBER_OF_CORES == 1 ) */ + __asm volatile ( + " .syntax unified \n" + #if configRESET_STACK_POINTER + " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n" + " ldr r0, [r0] \n" + " msr msp, r0 \n" /* Set the msp back to the start of the stack. */ + #endif /* configRESET_STACK_POINTER */ + " adr r1, ulAsmLocals \n" /* Get the location of the current TCB for the current core. */ + " ldmia r1!, {r2, r3} \n" + " ldr r2, [r2] \n" /* r2 = Core number */ + " lsls r2, #2 \n" + " ldr r3, [r3, r2] \n" /* r3 = pxCurrentTCBs[get_core_num()] */ + " ldr r0, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. */ + " adds r0, #32 \n" /* Discard everything up to r0. */ + " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */ + " movs r0, #2 \n" /* Switch to the psp stack. */ + " msr CONTROL, r0 \n" + " isb \n" + " pop {r0-r5} \n" /* Pop the registers that are saved automatically. */ + " mov lr, r5 \n" /* lr is now in r5. */ + " pop {r3} \n" /* Return address is now in r3. */ + " pop {r2} \n" /* Pop and discard XPSR. */ + " cpsie i \n" /* The first task has its context and interrupts can be enabled. */ + " bx r3 \n" /* Finally, jump to the user defined task code. */ + " \n" + " .align 4 \n" + "ulAsmLocals: \n" + " .word 0xD0000000 \n" /* SIO */ + " .word pxCurrentTCBs \n" + ); + #endif /* if ( configNUMBER_OF_CORES == 1 ) */ +} +/*-----------------------------------------------------------*/ + +#if ( LIB_PICO_MULTICORE == 1 ) && ( configSUPPORT_PICO_SYNC_INTEROP == 1 ) + static void prvFIFOInterruptHandler() + { + /* We must remove the contents (which we don't care about) + * to clear the IRQ */ + multicore_fifo_drain(); + + /* And explicitly clear any other IRQ flags. */ + multicore_fifo_clear_irq(); + + #if ( configNUMBER_OF_CORES != 1 ) + portYIELD_FROM_ISR( pdTRUE ); + #elif ( configSUPPORT_PICO_SYNC_INTEROP == 1 ) + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + uint32_t ulSave = spin_lock_blocking( pxCrossCoreSpinLock ); + EventBits_t ulBits = uxCrossCoreEventBits; + uxCrossCoreEventBits &= ~ulBits; + spin_unlock( pxCrossCoreSpinLock, ulSave ); + xEventGroupSetBitsFromISR( xEventGroup, ulBits, &xHigherPriorityTaskWoken ); + portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + #endif /* configNUMBER_OF_CORES != 1 */ + } +#endif /* if ( LIB_PICO_MULTICORE == 1 ) && ( configSUPPORT_PICO_SYNC_INTEROP == 1 ) */ + +#if ( configNUMBER_OF_CORES > 1 ) + +/* + * See header file for description. + */ + static BaseType_t xPortStartSchedulerOnCore() + { + if( ucPrimaryCoreNum == get_core_num() ) + { + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + #if ( configUSE_DYNAMIC_EXCEPTION_HANDLERS == 1 ) + exception_set_exclusive_handler( SYSTICK_EXCEPTION, xPortSysTickHandler ); + #endif + } + + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + + #if ( configUSE_DYNAMIC_EXCEPTION_HANDLERS == 1 ) + exception_set_exclusive_handler( PENDSV_EXCEPTION, xPortPendSVHandler ); + exception_set_exclusive_handler( SVCALL_EXCEPTION, vPortSVCHandler ); + #endif + + /* Install FIFO handler to receive interrupt from other core */ + multicore_fifo_clear_irq(); + multicore_fifo_drain(); + uint32_t ulIRQNum = SIO_IRQ_PROC0 + get_core_num(); + irq_set_priority( ulIRQNum, portMIN_INTERRUPT_PRIORITY ); + irq_set_exclusive_handler( ulIRQNum, prvFIFOInterruptHandler ); + irq_set_enabled( ulIRQNum, 1 ); + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should never get here as the tasks will now be executing! Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext( portGET_CORE_ID() ); + prvTaskExitError(); + + /* Should not get here. */ + return 0; + } + + static void prvDisableInterruptsAndPortStartSchedulerOnCore( void ) + { + portDISABLE_INTERRUPTS(); + xPortStartSchedulerOnCore(); + } + +/* + * See header file for description. + */ + BaseType_t xPortStartScheduler( void ) + { + configASSERT( ucPrimaryCoreNum == INVALID_PRIMARY_CORE_NUM ); + + /* No one else should use these! */ + spin_lock_claim( configSMP_SPINLOCK_0 ); + spin_lock_claim( configSMP_SPINLOCK_1 ); + + ucPrimaryCoreNum = configTICK_CORE; + configASSERT( get_core_num() == 0 ); /* we must be started on core 0 */ + multicore_reset_core1(); + multicore_launch_core1( prvDisableInterruptsAndPortStartSchedulerOnCore ); + + xPortStartSchedulerOnCore(); + + /* Should not get here! */ + return 0; + } + +#else /* if ( configNUMBER_OF_CORES > 1 ) */ + +/* + * See header file for description. + */ + BaseType_t xPortStartScheduler( void ) + { + /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + #if ( configUSE_DYNAMIC_EXCEPTION_HANDLERS == 1 ) + exception_set_exclusive_handler( PENDSV_EXCEPTION, xPortPendSVHandler ); + exception_set_exclusive_handler( SYSTICK_EXCEPTION, xPortSysTickHandler ); + exception_set_exclusive_handler( SVCALL_EXCEPTION, vPortSVCHandler ); + #endif + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + ucPrimaryCoreNum = get_core_num(); + #if ( LIB_PICO_MULTICORE == 1 ) + #if ( configSUPPORT_PICO_SYNC_INTEROP == 1 ) + multicore_fifo_clear_irq(); + multicore_fifo_drain(); + uint32_t irq_num = SIO_IRQ_PROC0 + get_core_num(); + irq_set_priority( irq_num, portMIN_INTERRUPT_PRIORITY ); + irq_set_exclusive_handler( irq_num, prvFIFOInterruptHandler ); + irq_set_enabled( irq_num, 1 ); + #endif + #endif + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should never get here as the tasks will now be executing! Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here! */ + return 0; + } +#endif /* if ( configNUMBER_OF_CORES > 1 ) */ + +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( portGET_CORE_ID() == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortYield( void ) +{ + /* Set a PendSV to request a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + + /* Barriers are normally not required but do ensure the code is completely + * within the specified behaviour for the architecture. */ + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); +} + +/*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES == 1 ) + void vPortEnterCritical( void ) + { + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "isb" ); + } +#endif /* #if ( configNUMBER_OF_CORES == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES == 1 ) + void vPortExitCritical( void ) + { + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + } +#endif /* #if ( configNUMBER_OF_CORES == 1 ) */ + +/*-----------------------------------------------------------*/ + +uint32_t ulSetInterruptMaskFromISR( void ) +{ + __asm volatile ( + " mrs r0, PRIMASK \n" + " cpsid i \n" + " bx lr " + ::: "memory" + ); +} +/*-----------------------------------------------------------*/ + +void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) +{ + __asm volatile ( + " msr PRIMASK, r0 \n" + " bx lr " + ::: "memory" + ); +} + +/*-----------------------------------------------------------*/ + +void vYieldCore( int xCoreID ) +{ + /* Remove warning if configASSERT is not defined. + * xCoreID is not used in this function due to this is a dual-core system. The yielding core must be different from the current core. */ + ( void ) xCoreID; + + configASSERT( xCoreID != ( int ) portGET_CORE_ID() ); + + #if configNUMBER_OF_CORES != 1 + + /* Non blocking, will cause interrupt on other core if the queue isn't already full, + * in which case an IRQ must be pending */ + sio_hw->fifo_wr = 0; + #endif +} + +/*-----------------------------------------------------------*/ + +void xPortPendSVHandler( void ) +{ + /* This is a naked function. */ + #if ( configNUMBER_OF_CORES == 1 ) + __asm volatile + ( + " .syntax unified \n" + " mrs r0, psp \n" + " \n" + " ldr r3, pxCurrentTCBConst2 \n" /* Get the location of the current TCB. */ + " ldr r2, [r3] \n" + " \n" + " subs r0, r0, #32 \n" /* Make space for the remaining low registers. */ + " str r0, [r2] \n" /* Save the new top of stack. */ + " stmia r0!, {r4-r7} \n" /* Store the low registers that are not saved automatically. */ + " mov r4, r8 \n" /* Store the high registers. */ + " mov r5, r9 \n" + " mov r6, r10 \n" + " mov r7, r11 \n" + " stmia r0!, {r4-r7} \n" + #if portUSE_DIVIDER_SAVE_RESTORE + " movs r2, #0xd \n" /* Store the divider state. */ + " lsls r2, #28 \n" + + /* We expect that the divider is ready at this point (which is + * necessary to safely save/restore), because: + * a) if we have not been interrupted since we entered this method, + * then >8 cycles have clearly passed, so the divider is done + * b) if we were interrupted in the interim, then any "safe" - i.e. + * does the right thing in an IRQ - use of the divider should + * have waited for any in-process divide to complete, saved and + * then fully restored the result, thus the result is ready in + * that case too. */ + " ldr r4, [r2, #0x60] \n" /* SIO_DIV_UDIVIDEND_OFFSET */ + " ldr r5, [r2, #0x64] \n" /* SIO_DIV_UDIVISOR_OFFSET */ + " ldr r6, [r2, #0x74] \n" /* SIO_DIV_REMAINDER_OFFSET */ + " ldr r7, [r2, #0x70] \n" /* SIO_DIV_QUOTIENT_OFFSET */ + + /* We actually save the divider state in the 4 words below + * our recorded stack pointer, so as not to disrupt the stack + * frame expected by debuggers - this is addressed by + * portEXTRA_STACK_SIZE */ + " subs r0, r0, #48 \n" + " stmia r0!, {r4-r7} \n" + #endif /* portUSE_DIVIDER_SAVE_RESTORE */ + " push {r3, r14} \n" + " cpsid i \n" + " bl vTaskSwitchContext \n" + " cpsie i \n" + " pop {r2, r3} \n" /* lr goes in r3. r2 now holds tcb pointer. */ + " \n" + " ldr r1, [r2] \n" + " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */ + " adds r0, r0, #16 \n" /* Move to the high registers. */ + " ldmia r0!, {r4-r7} \n" /* Pop the high registers. */ + " mov r8, r4 \n" + " mov r9, r5 \n" + " mov r10, r6 \n" + " mov r11, r7 \n" + " \n" + " msr psp, r0 \n" /* Remember the new top of stack for the task. */ + " \n" + #if portUSE_DIVIDER_SAVE_RESTORE + " movs r2, #0xd \n" /* Pop the divider state. */ + " lsls r2, #28 \n" + " subs r0, r0, #48 \n" /* Go back for the divider state */ + " ldmia r0!, {r4-r7} \n" /* Pop the divider state. */ + + /* Note always restore via SIO_DIV_UDIVI*, because we will overwrite the + * results stopping the calculation anyway, however the sign of results + * is adjusted by the h/w at read time based on whether the last started + * division was signed and the inputs' signs differed */ + " str r4, [r2, #0x60] \n" /* SIO_DIV_UDIVIDEND_OFFSET */ + " str r5, [r2, #0x64] \n" /* SIO_DIV_UDIVISOR_OFFSET */ + " str r6, [r2, #0x74] \n" /* SIO_DIV_REMAINDER_OFFSET */ + " str r7, [r2, #0x70] \n" /* SIO_DIV_QUOTIENT_OFFSET */ + #else /* if portUSE_DIVIDER_SAVE_RESTORE */ + " subs r0, r0, #32 \n" /* Go back for the low registers that are not automatically restored. */ + #endif /* portUSE_DIVIDER_SAVE_RESTORE */ + " ldmia r0!, {r4-r7} \n" /* Pop low registers. */ + " \n" + " bx r3 \n" + " .align 4 \n" + "pxCurrentTCBConst2: .word pxCurrentTCB \n" + ); + #else /* if ( configNUMBER_OF_CORES == 1 ) */ + __asm volatile + ( + " .syntax unified \n" + " mrs r1, psp \n" + " \n" + " adr r0, ulAsmLocals2 \n" /* Get the location of the current TCB for the current core. */ + " ldmia r0!, {r2, r3} \n" + " ldr r0, [r2] \n" /* r0 = Core number */ + " lsls r0, r0, #2 \n" + " adds r3, r0 \n" /* r3 = &pxCurrentTCBs[get_core_num()] */ + " ldr r0, [r3] \n" /* r0 = pxCurrentTCB */ + " \n" + " subs r1, r1, #32 \n" /* Make space for the remaining low registers. */ + " str r1, [r0] \n" /* Save the new top of stack. */ + " stmia r1!, {r4-r7} \n" /* Store the low registers that are not saved automatically. */ + " mov r4, r8 \n" /* Store the high registers. */ + " mov r5, r9 \n" + " mov r6, r10 \n" + " mov r7, r11 \n" + " stmia r1!, {r4-r7} \n" + #if portUSE_DIVIDER_SAVE_RESTORE + + /* We expect that the divider is ready at this point (which is + * necessary to safely save/restore), because: + * a) if we have not been interrupted since we entered this method, + * then >8 cycles have clearly passed, so the divider is done + * b) if we were interrupted in the interim, then any "safe" - i.e. + * does the right thing in an IRQ - use of the divider should + * have waited for any in-process divide to complete, saved and + * then fully restored the result, thus the result is ready in + * that case too. */ + " ldr r4, [r2, #0x60] \n" /* SIO_DIV_UDIVIDEND_OFFSET */ + " ldr r5, [r2, #0x64] \n" /* SIO_DIV_UDIVISOR_OFFSET */ + " ldr r6, [r2, #0x74] \n" /* SIO_DIV_REMAINDER_OFFSET */ + " ldr r7, [r2, #0x70] \n" /* SIO_DIV_QUOTIENT_OFFSET */ + + /* We actually save the divider state in the 4 words below + * our recorded stack pointer, so as not to disrupt the stack + * frame expected by debuggers - this is addressed by + * portEXTRA_STACK_SIZE */ + " subs r1, r1, #48 \n" + " stmia r1!, {r4-r7} \n" + #endif /* portUSE_DIVIDER_SAVE_RESTORE */ + " ldr r0, [r2] \n" /* r0 = Core number */ + " push {r3, r14} \n" + " cpsid i \n" + " bl vTaskSwitchContext \n" + " cpsie i \n" + " pop {r2, r3} \n" /* lr goes in r3. r2 now holds tcb pointer. */ + " \n" + " ldr r1, [r2] \n" + " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */ + " adds r0, r0, #16 \n" /* Move to the high registers. */ + " ldmia r0!, {r4-r7} \n" /* Pop the high registers. */ + " mov r8, r4 \n" + " mov r9, r5 \n" + " mov r10, r6 \n" + " mov r11, r7 \n" + " \n" + " msr psp, r0 \n" /* Remember the new top of stack for the task. */ + " \n" + #if portUSE_DIVIDER_SAVE_RESTORE + " movs r2, #0xd \n" /* Pop the divider state. */ + " lsls r2, #28 \n" + " subs r0, r0, #48 \n" /* Go back for the divider state */ + " ldmia r0!, {r4-r7} \n" /* Pop the divider state. */ + + /* Note always restore via SIO_DIV_UDIVI*, because we will overwrite the + * results stopping the calculation anyway, however the sign of results + * is adjusted by the h/w at read time based on whether the last started + * division was signed and the inputs' signs differed */ + " str r4, [r2, #0x60] \n" /* SIO_DIV_UDIVIDEND_OFFSET */ + " str r5, [r2, #0x64] \n" /* SIO_DIV_UDIVISOR_OFFSET */ + " str r6, [r2, #0x74] \n" /* SIO_DIV_REMAINDER_OFFSET */ + " str r7, [r2, #0x70] \n" /* SIO_DIV_QUOTIENT_OFFSET */ + #else /* if portUSE_DIVIDER_SAVE_RESTORE */ + " subs r0, r0, #32 \n" /* Go back for the low registers that are not automatically restored. */ + #endif /* portUSE_DIVIDER_SAVE_RESTORE */ + " ldmia r0!, {r4-r7} \n" /* Pop low registers. */ + " \n" + " bx r3 \n" + " \n" + " .align 4 \n" + "ulAsmLocals2: \n" + " .word 0xD0000000 \n" /* SIO */ + " .word pxCurrentTCBs \n" + ); + #endif /* if ( configNUMBER_OF_CORES == 1 ) */ +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + uint32_t ulPreviousMask; + + ulPreviousMask = taskENTER_CRITICAL_FROM_ISR(); + traceISR_ENTER(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + /* Pend a context switch. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + else + { + traceISR_EXIT(); + } + } + taskEXIT_CRITICAL_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( clock_get_hz( clk_sys ) / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR; + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and reset the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( clock_get_hz( clk_sys ) / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT; +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT; + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code will execute part way + * through one of the tick periods. */ + ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Restart from whatever is left in the count register to complete + * this tick period. */ + portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Reset the reload register to the value required for normal tick + * periods. */ + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Re-enable interrupts - see comments above the cpsid instruction() + * above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + else + { + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + if( xModifiableIdleTime > 0 ) + { + __asm volatile ( "dsb" ::: "memory" ); + __asm volatile ( "wfi" ); + __asm volatile ( "isb" ); + } + + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. see comments above + * __disable_interrupt() call above. */ + __asm volatile ( "cpsie i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm volatile ( "cpsid i" ::: "memory" ); + __asm volatile ( "dsb" ); + __asm volatile ( "isb" ); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT ); + + /* Determine if the SysTick clock has already counted to zero and + * been set back to the current reload value (the reload back being + * correct for the entire expected idle time) or if the SysTick is yet + * to count to zero (in which case an interrupt other than the SysTick + * must have brought the system out of sleep mode). */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt is already pending, and the SysTick count + * reloaded with ulReloadValue. Reset the + * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick + * period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long. */ + if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. + * Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG + * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard + * value. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + vTaskStepTick( ulCompleteTickPeriods ); + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Exit with interrupts enabled. */ + __asm volatile ( "cpsie i" ::: "memory" ); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ + +#if ( configSUPPORT_PICO_SYNC_INTEROP == 1 ) || ( configSUPPORT_PICO_TIME_INTEROP == 1 ) + static TickType_t prvGetTicksToWaitBefore( absolute_time_t t ) + { + int64_t xDelay = absolute_time_diff_us( get_absolute_time(), t ); + const uint32_t ulTickPeriod = 1000000 / configTICK_RATE_HZ; + + xDelay -= ulTickPeriod; + + if( xDelay >= ulTickPeriod ) + { + return xDelay / ulTickPeriod; + } + + return 0; + } +#endif /* if ( configSUPPORT_PICO_SYNC_INTEROP == 1 ) || ( configSUPPORT_PICO_TIME_INTEROP == 1 ) */ + +#if ( configSUPPORT_PICO_SYNC_INTEROP == 1 ) + uint32_t ulPortLockGetCurrentOwnerId() + { + if( portIS_FREE_RTOS_CORE() ) + { + uint32_t exception = __get_current_exception(); + + if( !exception ) + { + return ( uintptr_t ) xTaskGetCurrentTaskHandle(); + } + + /* Note: since ROM as at 0x00000000, these can't be confused with + * valid task handles (pointers) in RAM */ + /* We make all exception handler/core combinations distinct owners */ + return get_core_num() + exception * 2; + } + + /* Note: since ROM as at 0x00000000, this can't be confused with + * valid task handles (pointers) in RAM */ + return get_core_num(); + } + + static inline EventBits_t prvGetEventGroupBit( spin_lock_t * spinLock ) + { + uint32_t ulBit; + + #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + ulBit = 1u << ( spin_lock_get_num( spinLock ) & 0x7u ); + #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + /* Avoid potential use of SIO divider for % here out of abundance of caution */ + ulBit = spin_lock_get_num( spinLock ); + if (ulBit >= 24) ulBit -= 24; + ulBit = 1u << ulBit; + #endif /* configTICK_TYPE_WIDTH_IN_BITS */ + return ( EventBits_t ) ulBit; + } + + static inline EventBits_t prvGetAllEventGroupBits() + { + #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + return ( EventBits_t ) 0xffu; + #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + return ( EventBits_t ) 0xffffffu; + #endif /* configTICK_TYPE_WIDTH_IN_BITS */ + } + + void vPortLockInternalSpinUnlockWithWait( struct lock_core * pxLock, + uint32_t ulSave ) + { + configASSERT( !portCHECK_IF_IN_ISR() ); + configASSERT( pxLock->spin_lock ); + + if( !portIS_FREE_RTOS_CORE() ) + { + spin_unlock( pxLock->spin_lock, ulSave ); + __wfe(); + } + else + { + /* The requirement (from the SDK) on this implementation is that this method + * should always wake up from a corresponding call to vPortLockInternalSpinUnlockWithNotify + * that happens after this method is called. + * + * The moment that we unlock the spin lock, we need to be sure that + * there is no way that we end up blocking in xEventGroupWaitBits, + * despite the fact that other tasks can now run, if the corresponding + * unlock has occurred. + * + * Previously the RP2xxx ports used to attempt to disable IRQs until the + * task actually (potentially) became blocked by hooking the IRQ re-enable + * when xEventGroupWaitBits completes (or switches tasks), but this + * was a broken hack, in that IRQs are re-enabled at other points during + * that call. + * + * This deferred IRQ enable is not actually needed, because all we + * care about is that: + * + * Even in the presence of other tasks acquiring then releasing + * the lock, between the interrupt_enable and the xEventGroupWaitBits, + * the corresponding bit will still be set. + * + * This is the case, even any intervening blocked lock (which + * clears the event bit) will need to unlock it before we proceed, + * which will set the event bit again. + * + * The multiplexing down of multiple spin lock numbers to fewer + * event bits does not cause a possible race condition, + * but it does mean that a task waiting for lock A can be + * blocked by a task B which owns another lock. + * + * This could be fixed by using an array of event groups, however + * since the SDK spin locks are generally intended for very short + * term usage anyway, and rarely nested except in exotic cases + * like video output, we'll leave it as one event group for now + */ + spin_unlock( pxLock->spin_lock, ulSave); + xEventGroupWaitBits( xEventGroup, prvGetEventGroupBit( pxLock->spin_lock ), + pdTRUE, pdFALSE, portMAX_DELAY ); + } + } + + void vPortLockInternalSpinUnlockWithNotify( struct lock_core * pxLock, + uint32_t ulSave ) + { + EventBits_t uxBits = prvGetEventGroupBit( pxLock->spin_lock ); + + if( portIS_FREE_RTOS_CORE() ) + { + #if LIB_PICO_MULTICORE + /* signal an event in case a regular core is waiting */ + __sev(); + #endif + spin_unlock( pxLock->spin_lock, ulSave ); + + if( !portCHECK_IF_IN_ISR() ) + { + xEventGroupSetBits( xEventGroup, uxBits ); + } + else + { + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + xEventGroupSetBitsFromISR( xEventGroup, uxBits, &xHigherPriorityTaskWoken ); + portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + } + } + else + { + __sev(); + #if ( configNUMBER_OF_CORES == 1 ) + if( pxCrossCoreSpinLock != pxLock->spin_lock ) + { + spin_lock_unsafe_blocking( pxCrossCoreSpinLock ); + uxCrossCoreEventBits |= uxBits; + spin_unlock_unsafe( pxCrossCoreSpinLock ); + } + else + { + uxCrossCoreEventBits |= uxBits; + } + + /* This causes fifo irq on the other (FreeRTOS) core which will do the set the event bits */ + sio_hw->fifo_wr = 0; + #endif /* configNUMBER_OF_CORES == 1 */ + spin_unlock( pxLock->spin_lock, ulSave ); + } + } + + bool xPortLockInternalSpinUnlockWithBestEffortWaitOrTimeout( struct lock_core * pxLock, + uint32_t ulSave, + absolute_time_t uxUntil ) + { + configASSERT( !portCHECK_IF_IN_ISR() ); + configASSERT( pxLock->spin_lock ); + + /* note no need to check LIB_PICO_MULTICORE, as this is always returns true if that is not defined */ + if( !portIS_FREE_RTOS_CORE() ) + { + spin_unlock( pxLock->spin_lock, ulSave ); + return best_effort_wfe_or_timeout( uxUntil ); + } + else + { + configASSERT( portIS_FREE_RTOS_CORE() ); + + TickType_t uxTicksToWait = prvGetTicksToWaitBefore( uxUntil ); + + if( uxTicksToWait ) + { + /* See comment in vPortLockInternalSpinUnlockWithWait for detail + * about possible race conditions */ + spin_unlock( pxLock->spin_lock, ulSave ); + xEventGroupWaitBits( xEventGroup, + prvGetEventGroupBit( pxLock->spin_lock ), pdTRUE, + pdFALSE, uxTicksToWait ); + } + else + { + spin_unlock( pxLock->spin_lock, ulSave ); + } + + if( time_reached( uxUntil ) ) + { + return true; + } + else + { + /* We do not want to hog the core */ + portYIELD(); + /* We aren't sure if we've reached the timeout yet; the caller will check */ + return false; + } + } + } + + #if ( configSUPPORT_PICO_SYNC_INTEROP == 1 ) + /* runs before main */ + static void __attribute__( ( constructor ) ) prvRuntimeInitializer( void ) + { + /* This must be done even before the scheduler is started, as the spin lock + * is used by the overrides of the SDK wait/notify primitives */ + #if ( configNUMBER_OF_CORES == 1 ) + pxCrossCoreSpinLock = spin_lock_instance( next_striped_spin_lock_num() ); + #endif /* configNUMBER_OF_CORES == 1 */ + + /* The event group is not used prior to scheduler init, but is initialized + * here to since it logically belongs with the spin lock */ + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + xEventGroup = xEventGroupCreateStatic( &xStaticEventGroup ); + #else + + /* Note that it is slightly dubious calling this here before the scheduler is initialized, + * however the only thing it touches is the allocator which then calls vPortEnterCritical + * and vPortExitCritical, and allocating here saves us checking the one time initialized variable in + * some rather critical code paths */ + xEventGroup = xEventGroupCreate(); + #endif /* configSUPPORT_STATIC_ALLOCATION */ + } + #endif /* if ( configSUPPORT_PICO_SYNC_INTEROP == 1 ) */ +#endif /* configSUPPORT_PICO_SYNC_INTEROP */ + +#if ( configSUPPORT_PICO_TIME_INTEROP == 1 ) + void xPortSyncInternalYieldUntilBefore( absolute_time_t t ) + { + TickType_t uxTicksToWait = prvGetTicksToWaitBefore( t ); + + if( uxTicksToWait ) + { + vTaskDelay( uxTicksToWait ); + } + } +#endif /* configSUPPORT_PICO_TIME_INTEROP */ diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/FreeRTOS-openocd.c b/portable/ThirdParty/GCC/Xtensa_ESP32/FreeRTOS-openocd.c new file mode 100644 index 000000000..fecfe3566 --- /dev/null +++ b/portable/ThirdParty/GCC/Xtensa_ESP32/FreeRTOS-openocd.c @@ -0,0 +1,27 @@ +/* + * Since at least FreeRTOS V7.5.3 uxTopUsedPriority is no longer + * present in the kernel, so it has to be supplied by other means for + * OpenOCD's threads awareness. + * + * Add this file to your project, and, if you're using --gc-sections, + * ``--undefined=uxTopUsedPriority'' (or + * ``-Wl,--undefined=uxTopUsedPriority'' when using gcc for final + * linking) to your LDFLAGS; same with all the other symbols you need. + */ + +#include "FreeRTOS.h" +#include "esp_attr.h" +#include "sdkconfig.h" + +#ifdef __GNUC__ + #define USED __attribute__( ( used ) ) +#else + #define USED +#endif + +/* + * This file is no longer needed as AFTER FreeRTOS V10.14.1 OpenOCD is fixed in the kernel. + * #ifdef CONFIG_ESP32_DEBUG_OCDAWARE + * const int USED DRAM_ATTR uxTopUsedPriority = configMAX_PRIORITIES - 1; + * #endif + */ diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/include/FreeRTOSConfig_arch.h b/portable/ThirdParty/GCC/Xtensa_ESP32/include/FreeRTOSConfig_arch.h new file mode 100644 index 000000000..57f7b0156 --- /dev/null +++ b/portable/ThirdParty/GCC/Xtensa_ESP32/include/FreeRTOSConfig_arch.h @@ -0,0 +1,139 @@ +/* + * SPDX-FileCopyrightText: 2022 Amazon.com, Inc. or its affiliates + * + * SPDX-License-Identifier: MIT + * + * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD + */ + +/* + * FreeRTOS Kernel + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + * 1 tab == 4 spaces! + */ + +#ifndef FREERTOS_CONFIG_XTENSA_H +#define FREERTOS_CONFIG_XTENSA_H + +#include "sdkconfig.h" + +/* enable use of optimized task selection by the scheduler */ +#if defined( CONFIG_FREERTOS_OPTIMIZED_SCHEDULER ) && !defined( configUSE_PORT_OPTIMISED_TASK_SELECTION ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#define XT_USE_THREAD_SAFE_CLIB 0 +#undef XT_USE_SWPRI + +#if CONFIG_FREERTOS_CORETIMER_0 + #define XT_TIMER_INDEX 0 +#elif CONFIG_FREERTOS_CORETIMER_1 + #define XT_TIMER_INDEX 1 +#endif + +#ifndef __ASSEMBLER__ + +/** + * This function is defined to provide a deprecation warning whenever + * XT_CLOCK_FREQ macro is used. + * Update the code to use esp_clk_cpu_freq function instead. + * @return current CPU clock frequency, in Hz + */ + int xt_clock_freq( void ) __attribute__( ( deprecated ) ); + + #define XT_CLOCK_FREQ ( xt_clock_freq() ) + +#endif // __ASSEMBLER__ + +/* Required for configuration-dependent settings */ +#include + +/* configASSERT behaviour */ +#ifndef __ASSEMBLER__ + #include + #include "esp_rom_sys.h" + #if CONFIG_IDF_TARGET_ESP32 + #include "esp32/rom/ets_sys.h" /* will be removed in idf v5.0 */ + #elif CONFIG_IDF_TARGET_ESP32S2 + #include "esp32s2/rom/ets_sys.h" + #elif CONFIG_IDF_TARGET_ESP32S3 + #include "esp32s3/rom/ets_sys.h" + #endif +#endif // __ASSEMBLER__ + +/* If CONFIG_FREERTOS_ASSERT_DISABLE is set then configASSERT is defined empty later in FreeRTOS.h and the macro */ +/* configASSERT_DEFINED remains unset (meaning some warnings are avoided) */ +#if ( configASSERT_DEFINED == 1 ) + #undef configASSERT + #if defined( CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE ) + #define configASSERT( a ) \ + if( unlikely( !( a ) ) ) { \ + esp_rom_printf( "%s:%d (%s)- assert failed!\n", __FILE__, __LINE__, \ + __FUNCTION__ ); \ + } + #elif defined( CONFIG_FREERTOS_ASSERT_FAIL_ABORT ) + #define configASSERT( a ) assert( a ) + #endif +#endif /* ifdef configASSERT */ + +#if CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION + #define UNTESTED_FUNCTION() \ + { esp_rom_printf( "Untested FreeRTOS function %s\r\n", __FUNCTION__ ); configASSERT( false ); } \ + while( 0 ) +#else + #define UNTESTED_FUNCTION() +#endif + +#define configXT_BOARD 1 /* Board mode */ +#define configXT_SIMULATOR 0 + +/* The maximum interrupt priority from which FreeRTOS.org API functions can + * be called. Only API functions that end in ...FromISR() can be used within + * interrupts. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY XCHAL_EXCM_LEVEL + +/* Stack alignment, architecture specific. Must be a power of two. */ +#define configSTACK_ALIGNMENT 16 + + +/* The Xtensa port uses a separate interrupt stack. Adjust the stack size + * to suit the needs of your specific application. + * Size needs to be aligned to the stack increment, since the location of + * the stack for the 2nd CPU will be calculated using configISR_STACK_SIZE. + */ +#ifndef configISR_STACK_SIZE + #define configISR_STACK_SIZE ( ( CONFIG_FREERTOS_ISR_STACKSIZE + configSTACK_ALIGNMENT - 1 ) & ( ~( configSTACK_ALIGNMENT - 1 ) ) ) +#endif + +#ifndef __ASSEMBLER__ + #if CONFIG_APPTRACE_SV_ENABLE + extern uint32_t port_switch_flag[]; + #define os_task_switch_is_pended( _cpu_ ) ( port_switch_flag[ _cpu_ ] ) + #else + #define os_task_switch_is_pended( _cpu_ ) ( false ) + #endif +#endif + +#endif // FREERTOS_CONFIG_XTENSA_H diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/include/port_systick.h b/portable/ThirdParty/GCC/Xtensa_ESP32/include/port_systick.h new file mode 100644 index 000000000..22f18ba52 --- /dev/null +++ b/portable/ThirdParty/GCC/Xtensa_ESP32/include/port_systick.h @@ -0,0 +1,24 @@ +/* + * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/** + * @brief Set up the SysTick interrupt + */ +void vPortSetupTimer( void ); + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/include/portbenchmark.h b/portable/ThirdParty/GCC/Xtensa_ESP32/include/portbenchmark.h new file mode 100644 index 000000000..ad5c881d1 --- /dev/null +++ b/portable/ThirdParty/GCC/Xtensa_ESP32/include/portbenchmark.h @@ -0,0 +1,53 @@ +/* + * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc. + * + * SPDX-License-Identifier: MIT + * + * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD + */ + +/* + * Copyright (c) 2015-2019 Cadence Design Systems, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * This utility helps benchmarking interrupt latency and context switches. + * In order to enable it, set configBENCHMARK to 1 in FreeRTOSConfig.h. + * You will also need to download the FreeRTOS_trace patch that contains + * portbenchmark.c and the complete version of portbenchmark.h + */ + +#ifndef PORTBENCHMARK_H +#define PORTBENCHMARK_H + +#if configBENCHMARK + #error "You need to download the FreeRTOS_trace patch that overwrites this file" +#endif + +#define portbenchmarkINTERRUPT_DISABLE() +#define portbenchmarkINTERRUPT_RESTORE( newstate ) +#define portbenchmarkIntLatency() +#define portbenchmarkIntWait() +#define portbenchmarkReset() +#define portbenchmarkPrint() + +#endif /* PORTBENCHMARK */ diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h b/portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h new file mode 100644 index 000000000..2f3fe55e0 --- /dev/null +++ b/portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h @@ -0,0 +1,579 @@ +/* + * SPDX-FileCopyrightText: 2017 Amazon.com, Inc. or its affiliates + * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc. + * + * SPDX-License-Identifier: MIT + * + * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD + */ + +/* + * FreeRTOS Kernel + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + * 1 tab == 4 spaces! + */ + +/* + * Copyright (c) 2015-2019 Cadence Design Systems, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +#ifndef __ASSEMBLER__ + + #include + + #include + #include + #include /* required for XSHAL_CLIB */ + #include + #include "soc/spinlock.h" + #include "esp_timer.h" /* required for FreeRTOS run time stats */ + #include "esp_system.h" + #include "esp_idf_version.h" + #include "esp_heap_caps.h" + +/* TODO: Resolve build warnings generated due to this header inclusion */ + #include "hal/cpu_hal.h" + +/* TODO: These includes are not directly used in this file. They are kept into to prevent a breaking change. Remove these. */ + #include + #include + + #include "soc/cpu.h" + #include "soc/soc_memory_layout.h" + #if ( ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL( 4, 2, 0 ) ) + #include "soc/compare_set.h" + #endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */ + +/*#include "xtensa_context.h" */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ + + #define portCHAR int8_t + #define portFLOAT float + #define portDOUBLE double + #define portLONG int32_t + #define portSHORT int16_t + #define portSTACK_TYPE uint8_t + #define portBASE_TYPE int + + typedef portSTACK_TYPE StackType_t; + typedef portBASE_TYPE BaseType_t; + typedef unsigned portBASE_TYPE UBaseType_t; + + #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + #else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. + #endif +/*-----------------------------------------------------------*/ + +/* portbenchmark */ + #include "portbenchmark.h" + + #include "sdkconfig.h" + #include "esp_attr.h" + +/* "mux" data structure (spinlock) */ + typedef spinlock_t portMUX_TYPE; /**< Spinlock type used by FreeRTOS critical sections */ + #define portMUX_INITIALIZER_UNLOCKED SPINLOCK_INITIALIZER /**< Spinlock initializer */ + #define portMUX_FREE_VAL SPINLOCK_FREE /**< Spinlock is free. [refactor-todo] check if this is still required */ + #define portMUX_NO_TIMEOUT SPINLOCK_WAIT_FOREVER /**< When passed for 'timeout_cycles', spin forever if necessary. [refactor-todo] check if this is still required */ + #define portMUX_TRY_LOCK SPINLOCK_NO_WAIT /**< Try to acquire the spinlock a single time only. [refactor-todo] check if this is still required */ + #define portMUX_INITIALIZE( mux ) spinlock_initialize( mux ) /*< Initialize a spinlock to its unlocked state */ + + #define portCRITICAL_NESTING_IN_TCB 1 + +/* + * Modifications to portENTER_CRITICAL. + * + * For an introduction, see "Critical Sections & Disabling Interrupts" in docs/api-guides/freertos-smp.rst + * + * The original portENTER_CRITICAL only disabled the ISRs. This is enough for single-CPU operation: by + * disabling the interrupts, there is no task switch so no other tasks can meddle in the data, and because + * interrupts are disabled, ISRs can't corrupt data structures either. + * + * For multiprocessing, things get a bit more hairy. First of all, disabling the interrupts doesn't stop + * the tasks or ISRs on the other processors meddling with our CPU. For tasks, this is solved by adding + * a spinlock to the portENTER_CRITICAL macro. A task running on the other CPU accessing the same data will + * spinlock in the portENTER_CRITICAL code until the first CPU is done. + * + * For ISRs, we now also need muxes: while portENTER_CRITICAL disabling interrupts will stop ISRs on the same + * CPU from meddling with the data, it does not stop interrupts on the other cores from interfering with the + * data. For this, we also use a spinlock in the routines called by the ISR, but these spinlocks + * do not disable the interrupts (because they already are). + * + * This all assumes that interrupts are either entirely disabled or enabled. Interrupt priority levels + * will break this scheme. + * + * Remark: For the ESP32, portENTER_CRITICAL and portENTER_CRITICAL_ISR both alias vPortEnterCritical, meaning + * that either function can be called both from ISR as well as task context. This is not standard FreeRTOS + * behaviour; please keep this in mind if you need any compatibility with other FreeRTOS implementations. + */ + void vPortCPUInitializeMutex( portMUX_TYPE * mux ); + #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG + #error CONFIG_FREERTOS_PORTMUX_DEBUG not supported in Amazon FreeRTOS + #endif + + void vTaskExitCritical(); + void vTaskEnterCritical(); + static inline void vPortConsumeSpinlockArg( int unused, + ... ) + { + } + +/** @brief Acquire a portmux spinlock with a timeout + * + * @param mux Pointer to portmux to acquire. + * @param timeout_cycles Timeout to spin, in CPU cycles. Pass portMUX_NO_TIMEOUT to wait forever, + * portMUX_TRY_LOCK to try a single time to acquire the lock. + * + * @return true if mutex is successfully acquired, false on timeout. + */ + bool vPortCPUAcquireMutexTimeout( portMUX_TYPE * mux, + int timeout_cycles ); + void vPortCPUReleaseMutex( portMUX_TYPE * mux ); + + #define portENTER_CRITICAL( ... ) do { vTaskEnterCritical(); vPortConsumeSpinlockArg( 0, ## __VA_ARGS__ ); } while( 0 ) + #define portEXIT_CRITICAL( ... ) do { vTaskExitCritical(); vPortConsumeSpinlockArg( 0, ## __VA_ARGS__ ); } while( 0 ) + + + #define portENTER_CRITICAL_ISR( mux ) vPortCPUAcquireMutexTimeout( mux, portMUX_NO_TIMEOUT ) + #define portEXIT_CRITICAL_ISR( mux ) vPortCPUReleaseMutex( mux ) + + #define portENTER_CRITICAL_SAFE( mux ) \ + do { \ + if( xPortInIsrContext() ) { \ + portENTER_CRITICAL_ISR( mux ); \ + } \ + else { \ + portENTER_CRITICAL( mux ); \ + } \ + } while( 0 ) + + #define portEXIT_CRITICAL_SAFE( mux ) \ + do { \ + if( xPortInIsrContext() ) { \ + portEXIT_CRITICAL_ISR( mux ); \ + } \ + else { \ + portEXIT_CRITICAL( mux ); \ + } \ + } while( 0 ) + + #define portASSERT_IF_IN_ISR() vPortAssertIfInISR() + void vPortAssertIfInISR( void ); + +/* Critical section management. NW-TODO: replace XTOS_SET_INTLEVEL with more efficient version, if any? */ +/* These cannot be nested. They should be used with a lot of care and cannot be called from interrupt level. */ +/* */ +/* Only applies to one CPU. See notes above & below for reasons not to use these. */ + #define portDISABLE_INTERRUPTS() do { XTOS_SET_INTLEVEL( XCHAL_EXCM_LEVEL ); portbenchmarkINTERRUPT_DISABLE(); } while( 0 ) + #define portENABLE_INTERRUPTS() do { portbenchmarkINTERRUPT_RESTORE( 0 ); XTOS_SET_INTLEVEL( 0 ); } while( 0 ) + +/* Cleaner solution allows nested interrupts disabling and restoring via local registers or stack. */ +/* They can be called from interrupts too. */ +/* WARNING: Only applies to current CPU. See notes above. */ + static inline UBaseType_t __attribute__( ( always_inline ) ) xPortSetInterruptMaskFromISR( void ) + { + UBaseType_t prev_int_level = XTOS_SET_INTLEVEL( XCHAL_EXCM_LEVEL ); + + portbenchmarkINTERRUPT_DISABLE(); + return prev_int_level; + } + + static inline void __attribute__( ( always_inline ) ) vPortClearInterruptMaskFromISR( UBaseType_t prev_level ) + { + portbenchmarkINTERRUPT_RESTORE( prev_level ); + XTOS_RESTORE_JUST_INTLEVEL( prev_level ); + } + +/* These FreeRTOS versions are similar to the nested versions above */ + #define portSET_INTERRUPT_MASK_FROM_ISR() xPortSetInterruptMaskFromISR() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( prev_level ) vPortClearInterruptMaskFromISR( prev_level ) + +/*Because the ROM routines don't necessarily handle a stack in external RAM correctly, we force */ +/*the stack memory to always be internal. */ + #define portTcbMemoryCaps ( MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT ) + #define portStackMemoryCaps ( MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT ) + + #define pvPortMallocTcbMem( size ) heap_caps_malloc( size, portTcbMemoryCaps ) + #define pvPortMallocStackMem( size ) heap_caps_malloc( size, portStackMemoryCaps ) + +/*xTaskCreateStatic uses these functions to check incoming memory. */ + #define portVALID_TCB_MEM( ptr ) ( esp_ptr_internal( ptr ) && esp_ptr_byte_accessible( ptr ) ) + #ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY + #define portVALID_STACK_MEM( ptr ) esp_ptr_byte_accessible( ptr ) + #else + #define portVALID_STACK_MEM( ptr ) ( esp_ptr_internal( ptr ) && esp_ptr_byte_accessible( ptr ) ) + #endif + +/* + * Wrapper for the Xtensa compare-and-set instruction. This subroutine will atomically compare + * *addr to 'compare'. If *addr == compare, *addr is set to *set. *set is updated with the previous + * value of *addr (either 'compare' or some other value.) + * + * Warning: From the ISA docs: in some (unspecified) cases, the s32c1i instruction may return the + * *bitwise inverse* of the old mem if the mem wasn't written. This doesn't seem to happen on the + * ESP32 (portMUX assertions would fail). + */ + static inline void uxPortCompareSet( volatile uint32_t * addr, + uint32_t compare, + uint32_t * set ) + { + #if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) ) + __asm__ __volatile__ ( + "WSR %2,SCOMPARE1 \n" + "S32C1I %0, %1, 0 \n" + : "=r" ( *set ) + : "r" ( addr ), "r" ( compare ), "0" ( *set ) + ); + #else + #if ( XCHAL_HAVE_S32C1I > 0 ) + __asm__ __volatile__ ( + "WSR %2,SCOMPARE1 \n" + "S32C1I %0, %1, 0 \n" + : "=r" ( *set ) + : "r" ( addr ), "r" ( compare ), "0" ( *set ) + ); + #else + /* No S32C1I, so do this by disabling and re-enabling interrupts (slower) */ + uint32_t intlevel, old_value; + __asm__ __volatile__ ( "rsil %0, " XTSTR( XCHAL_EXCM_LEVEL ) "\n" + : "=r" ( intlevel ) ); + + old_value = *addr; + + if( old_value == compare ) + { + *addr = *set; + } + + __asm__ __volatile__ ( "memw \n" + "wsr %0, ps\n" + : : "r" ( intlevel ) ); + + *set = old_value; + #endif /* if ( XCHAL_HAVE_S32C1I > 0 ) */ + #endif /* #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) */ + } + + #if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) ) + void uxPortCompareSetExtram( volatile uint32_t * addr, + uint32_t compare, + uint32_t * set ); + #else + static inline void uxPortCompareSetExtram( volatile uint32_t * addr, + uint32_t compare, + uint32_t * set ) + { + #if defined( CONFIG_SPIRAM ) + compare_and_set_extram( addr, compare, set ); + #endif + } + #endif /* if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) ) */ + +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 4 + #define portNOP() XT_NOP() +/*-----------------------------------------------------------*/ + +/* Fine resolution time */ + #define portGET_RUN_TIME_COUNTER_VALUE() xthal_get_ccount() +/*ccount or esp_timer are initialized elsewhere */ + #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() + + #ifdef CONFIG_FREERTOS_RUN_TIME_STATS_USING_ESP_TIMER +/* Coarse resolution time (us) */ + #define portALT_GET_RUN_TIME_COUNTER_VALUE( x ) do { x = ( uint32_t ) esp_timer_get_time(); } while( 0 ) + #endif + + + +/* Kernel utilities. */ + void vPortYield( void ); + void vPortEvaluateYieldFromISR( int argc, + ... ); + void _frxt_setup_switch( void ); + +/* Macro to count number of arguments of a __VA_ARGS__ used to support portYIELD_FROM_ISR with, + * or without arguments. The macro counts only 0 or 1 arguments. + * + * In the future, we want to switch to C++20. We also want to become compatible with clang. + * Hence, we provide two versions of the following macros which are using variadic arguments. + * The first one is using the GNU extension ##__VA_ARGS__. The second one is using the C++20 feature __VA_OPT__(,). + * This allows users to compile their code with standard C++20 enabled instead of the GNU extension. + * Below C++20, we haven't found any good alternative to using ##__VA_ARGS__. + */ + #if defined( __cplusplus ) && ( __cplusplus > 201703L ) + #define portGET_ARGUMENT_COUNT( ... ) portGET_ARGUMENT_COUNT_INNER( 0 __VA_OPT__(, ) __VA_ARGS__, 1, 0 ) + #else + #define portGET_ARGUMENT_COUNT( ... ) portGET_ARGUMENT_COUNT_INNER( 0, ## __VA_ARGS__, 1, 0 ) + #endif + #define portGET_ARGUMENT_COUNT_INNER( zero, one, count, ... ) count + + _Static_assert( portGET_ARGUMENT_COUNT() == 0, "portGET_ARGUMENT_COUNT() result does not match for 0 arguments" ); + _Static_assert( portGET_ARGUMENT_COUNT( 1 ) == 1, "portGET_ARGUMENT_COUNT() result does not match for 1 argument" ); + + #define portYIELD() vPortYield() + +/* The macro below could be used when passing a single argument, or without any argument, + * it was developed to support both usages of portYIELD inside of an ISR. Any other usage form + * might result in undesired behaviour + */ + #if defined( __cplusplus ) && ( __cplusplus > 201703L ) + #define portYIELD_FROM_ISR( ... ) vPortEvaluateYieldFromISR( portGET_ARGUMENT_COUNT( __VA_ARGS__ ) __VA_OPT__(, ) __VA_ARGS__ ) + #else + #define portYIELD_FROM_ISR( ... ) vPortEvaluateYieldFromISR( portGET_ARGUMENT_COUNT( __VA_ARGS__ ), ## __VA_ARGS__ ) + #endif + + static inline BaseType_t xPortGetCoreID(); + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +/* When coprocessors are defined, we to maintain a pointer to coprocessors area. */ +/* We currently use a hack: redefine field xMPU_SETTINGS in TCB block as a structure that can hold: */ +/* MPU wrappers, coprocessor area pointer, trace code structure, and more if needed. */ +/* The field is normally used for memory protection. FreeRTOS should create another general purpose field. */ + typedef struct + { + #if XCHAL_CP_NUM > 0 + volatile StackType_t * coproc_area; /* Pointer to coprocessor save area; MUST BE FIRST */ + #endif + + #if portUSING_MPU_WRAPPERS + /* Define here mpu_settings, which is port dependent */ + int mpu_setting; /* Just a dummy example here; MPU not ported to Xtensa yet */ + #endif + + #if configUSE_TRACE_FACILITY_2 + struct + { + /* Cf. porttraceStamp() */ + int taskstamp; /* Stamp from inside task to see where we are */ + int taskstampcount; /* A counter usually incremented when we restart the task's loop */ + } porttrace; + #endif + } xMPU_SETTINGS; + +/* Main hack to use MPU_wrappers even when no MPU is defined (warning: mpu_setting should not be accessed; otherwise move this above xMPU_SETTINGS) */ + #if ( XCHAL_CP_NUM > 0 || configUSE_TRACE_FACILITY_2 ) && !portUSING_MPU_WRAPPERS /* If MPU wrappers not used, we still need to allocate coproc area */ + #undef portUSING_MPU_WRAPPERS + #define portUSING_MPU_WRAPPERS 1 /* Enable it to allocate coproc area */ + #define MPU_WRAPPERS_H /* Override mpu_wrapper.h to disable unwanted code */ + #define PRIVILEGED_FUNCTION + #define PRIVILEGED_DATA + #endif + + void vApplicationSleep( TickType_t xExpectedIdleTime ); + + #define portSUPPRESS_TICKS_AND_SLEEP( idleTime ) vApplicationSleep( idleTime ) + + void _xt_coproc_release( volatile void * coproc_sa_base ); + +/*-----------------------------------------------------------*/ + + #if ( ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL( 4, 2, 0 ) ) + /* Architecture specific optimisations. */ + + #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( ( uxReadyPriorities ) ) ) + + #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + + #endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */ + +/*-----------------------------------------------------------*/ + +/* + * Map to the memory management routines required for the port. + * + * Note that libc standard malloc/free are also available for + * non-FreeRTOS-specific code, and behave the same as + * pvPortMalloc()/vPortFree(). + */ + #define pvPortMalloc heap_caps_malloc_default + #define vPortFree heap_caps_free + #define xPortGetFreeHeapSize esp_get_free_heap_size + #define xPortGetMinimumEverFreeHeapSize esp_get_minimum_free_heap_size + + #if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) ) + +/* + * Send an interrupt to another core in order to make the task running + * on it yield for a higher-priority task. + */ + + void vPortYieldOtherCore( BaseType_t coreid ) PRIVILEGED_FUNCTION; + + #endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0) */ + +/* + * Callback to set a watchpoint on the end of the stack. Called every context switch to change the stack + * watchpoint around. + */ + void vPortSetStackWatchpoint( void * pxStackStart ); + +/* + * Returns true if the current core is in ISR context; low prio ISR, med prio ISR or timer tick ISR. High prio ISRs + * aren't detected here, but they normally cannot call C code, so that should not be an issue anyway. + */ + BaseType_t xPortInIsrContext(); + + +/* + * This function will be called in High prio ISRs. Returns true if the current core was in ISR context + * before calling into high prio ISR context. + */ + BaseType_t xPortInterruptedFromISRContext(); + +/* + * The structures and methods of manipulating the MPU are contained within the + * port layer. + * + * Fills the xMPUSettings structure with the memory region information + * contained in xRegions. + */ + #if ( portUSING_MPU_WRAPPERS == 1 ) + struct xMEMORY_REGION; + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + configSTACK_DEPTH_TYPE uxStackDepth ) PRIVILEGED_FUNCTION; + void vPortReleaseTaskMPUSettings( xMPU_SETTINGS * xMPUSettings ); + #endif + +/* Multi-core: get current core ID */ + static inline BaseType_t IRAM_ATTR xPortGetCoreID() + { + return ( uint32_t ) cpu_hal_get_core_id(); + } + +/* Get tick rate per second */ + uint32_t xPortGetTickRateHz( void ); + + static inline bool IRAM_ATTR xPortCanYield( void ) + { + uint32_t ps_reg = 0; + + /*Get the current value of PS (processor status) register */ + RSR( PS, ps_reg ); + + /* + * intlevel = (ps_reg & 0xf); + * excm = (ps_reg >> 4) & 0x1; + * CINTLEVEL is max(excm * EXCMLEVEL, INTLEVEL), where EXCMLEVEL is 3. + * However, just return true, only intlevel is zero. + */ + + return( ( ps_reg & PS_INTLEVEL_MASK ) == 0 ); + } + +/* porttrace */ + #if configUSE_TRACE_FACILITY_2 + #include "porttrace.h" + #endif + +/* configASSERT_2 if requested */ + #if configASSERT_2 + #include + void exit( int ); + #define configASSERT( x ) if( !( x ) ) { porttracePrint( -1 ); printf( "\nAssertion failed in %s:%d\n", __FILE__, __LINE__ ); exit( -1 ); } + #endif + +/* Barriers */ + #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) + + +#endif // __ASSEMBLER__ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/include/xt_asm_utils.h b/portable/ThirdParty/GCC/Xtensa_ESP32/include/xt_asm_utils.h new file mode 100644 index 000000000..9660e49a9 --- /dev/null +++ b/portable/ThirdParty/GCC/Xtensa_ESP32/include/xt_asm_utils.h @@ -0,0 +1,75 @@ +/* + * SPDX-FileCopyrightText: 2017, Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD + */ + +/* File adapted to use on IDF FreeRTOS component, extracted + * originally from zephyr RTOS code base: + * https://github.com/zephyrproject-rtos/zephyr/blob/dafd3485bf67880e667b6e9a758b0b64fb688d63/arch/xtensa/include/xtensa-asm2-s.h + */ + +#ifndef __XT_ASM_UTILS_H +#define __XT_ASM_UTILS_H + +/* + * SPILL_ALL_WINDOWS + * + * Spills all windowed registers (i.e. registers not visible as + * A0-A15) to their ABI-defined spill regions on the stack. + * + * Unlike the Xtensa HAL implementation, this code requires that the + * EXCM and WOE bit be enabled in PS, and relies on repeated hardware + * exception handling to do the register spills. The trick is to do a + * noop write to the high registers, which the hardware will trap + * (into an overflow exception) in the case where those registers are + * already used by an existing call frame. Then it rotates the window + * and repeats until all but the A0-A3 registers of the original frame + * are guaranteed to be spilled, eventually rotating back around into + * the original frame. Advantages: + * + * - Vastly smaller code size + * + * - More easily maintained if changes are needed to window over/underflow + * exception handling. + * + * - Requires no scratch registers to do its work, so can be used safely in any + * context. + * + * - If the WOE bit is not enabled (for example, in code written for + * the CALL0 ABI), this becomes a silent noop and operates compatbily. + * + * - Hilariously it's ACTUALLY FASTER than the HAL routine. And not + * just a little bit, it's MUCH faster. With a mostly full register + * file on an LX6 core (ESP-32) I'm measuring 145 cycles to spill + * registers with this vs. 279 (!) to do it with + * xthal_spill_windows(). + */ + +.macro SPILL_ALL_WINDOWS +#if XCHAL_NUM_AREGS == 64 + and a12, a12, a12 + rotw 3 + and a12, a12, a12 + rotw 3 + and a12, a12, a12 + rotw 3 + and a12, a12, a12 + rotw 3 + and a12, a12, a12 + rotw 4 +#elif XCHAL_NUM_AREGS == 32 + and a12, a12, a12 + rotw 3 + and a12, a12, a12 + rotw 3 + and a4, a4, a4 + rotw 2 +#else /* if XCHAL_NUM_AREGS == 64 */ + #error Unrecognized XCHAL_NUM_AREGS +#endif /* if XCHAL_NUM_AREGS == 64 */ + .endm + +#endif /* ifndef __XT_ASM_UTILS_H */ diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_api.h b/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_api.h new file mode 100644 index 000000000..a9069d798 --- /dev/null +++ b/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_api.h @@ -0,0 +1,31 @@ +/* + * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc. + * + * SPDX-License-Identifier: MIT + * + * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD + */ + +/* + * Copyright (c) 2015-2019 Cadence Design Systems, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#include diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_config.h b/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_config.h new file mode 100644 index 000000000..635e8647a --- /dev/null +++ b/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_config.h @@ -0,0 +1,158 @@ +/* + * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc. + * + * SPDX-License-Identifier: MIT + * + * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD + */ + +/* + * Copyright (c) 2015-2019 Cadence Design Systems, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/******************************************************************************* +* +* Configuration-specific information for Xtensa build. This file must be +* included in FreeRTOSConfig.h to properly set up the config-dependent +* parameters correctly. +* +* NOTE: To enable thread-safe C library support, XT_USE_THREAD_SAFE_CLIB must +* be defined to be > 0 somewhere above or on the command line. +* +*******************************************************************************/ + +#ifndef XTENSA_CONFIG_H +#define XTENSA_CONFIG_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +#include +#include +#include /* required for XSHAL_CLIB */ + +#include "xtensa_context.h" + + +/*----------------------------------------------------------------------------- + * STACK REQUIREMENTS + * + * This section defines the minimum stack size, and the extra space required to + * be allocated for saving coprocessor state and/or C library state information + * (if thread safety is enabled for the C library). The sizes are in bytes. + * + * Stack sizes for individual tasks should be derived from these minima based on + * the maximum call depth of the task and the maximum level of interrupt nesting. + * A minimum stack size is defined by XT_STACK_MIN_SIZE. This minimum is based + * on the requirement for a task that calls nothing else but can be interrupted. + * This assumes that interrupt handlers do not call more than a few levels deep. + * If this is not true, i.e. one or more interrupt handlers make deep calls then + * the minimum must be increased. + * + * If the Xtensa processor configuration includes coprocessors, then space is + * allocated to save the coprocessor state on the stack. + * + * If thread safety is enabled for the C runtime library, (XT_USE_THREAD_SAFE_CLIB + * is defined) then space is allocated to save the C library context in the TCB. + * + * Allocating insufficient stack space is a common source of hard-to-find errors. + * During development, it is best to enable the FreeRTOS stack checking features. + * + * Usage: + * + * XT_USE_THREAD_SAFE_CLIB -- Define this to a nonzero value to enable thread-safe + * use of the C library. This will require extra stack + * space to be allocated for tasks that use the C library + * reentrant functions. See below for more information. + * + * NOTE: The Xtensa toolchain supports multiple C libraries and not all of them + * support thread safety. Check your core configuration to see which C library + * was chosen for your system. + * + * XT_STACK_MIN_SIZE -- The minimum stack size for any task. It is recommended + * that you do not use a stack smaller than this for any + * task. In case you want to use stacks smaller than this + * size, you must verify that the smaller size(s) will work + * under all operating conditions. + * + * XT_STACK_EXTRA -- The amount of extra stack space to allocate for a task + * that does not make C library reentrant calls. Add this + * to the amount of stack space required by the task itself. + * + * XT_STACK_EXTRA_CLIB -- The amount of space to allocate for C library state. + * + * -----------------------------------------------------------------------------*/ + +/* Extra space required for interrupt/exception hooks. */ +#ifdef XT_INTEXC_HOOKS + #ifdef __XTENSA_CALL0_ABI__ + #define STK_INTEXC_EXTRA 0x200 + #else + #define STK_INTEXC_EXTRA 0x180 + #endif +#else + #define STK_INTEXC_EXTRA 0 +#endif + +#define XT_CLIB_CONTEXT_AREA_SIZE 0 + +/*------------------------------------------------------------------------------ + * Extra size -- interrupt frame plus coprocessor save area plus hook space. + * NOTE: Make sure XT_INTEXC_HOOKS is undefined unless you really need the hooks. + * ------------------------------------------------------------------------------*/ +#ifdef __XTENSA_CALL0_ABI__ + #define XT_XTRA_SIZE ( XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x10 + XT_CP_SIZE ) +#else + #define XT_XTRA_SIZE ( XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x20 + XT_CP_SIZE ) +#endif + +/*------------------------------------------------------------------------------ + * Space allocated for user code -- function calls and local variables. + * NOTE: This number can be adjusted to suit your needs. You must verify that the + * amount of space you reserve is adequate for the worst-case conditions in your + * application. + * NOTE: The windowed ABI requires more stack, since space has to be reserved + * for spilling register windows. + * ------------------------------------------------------------------------------*/ +#ifdef __XTENSA_CALL0_ABI__ + #define XT_USER_SIZE 0x200 +#else + #define XT_USER_SIZE 0x400 +#endif + +/* Minimum recommended stack size. */ +#define XT_STACK_MIN_SIZE ( ( XT_XTRA_SIZE + XT_USER_SIZE ) / sizeof( unsigned char ) ) + +/* OS overhead with and without C library thread context. */ +#define XT_STACK_EXTRA ( XT_XTRA_SIZE ) +#define XT_STACK_EXTRA_CLIB ( XT_XTRA_SIZE + XT_CLIB_CONTEXT_AREA_SIZE ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* XTENSA_CONFIG_H */ diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_context.h b/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_context.h new file mode 100644 index 000000000..56e6bf5c7 --- /dev/null +++ b/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_context.h @@ -0,0 +1,31 @@ +/* + * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc. + * + * SPDX-License-Identifier: MIT + * + * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD + */ + +/* + * Copyright (c) 2015-2019 Cadence Design Systems, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#include diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_rtos.h b/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_rtos.h new file mode 100644 index 000000000..767e95052 --- /dev/null +++ b/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_rtos.h @@ -0,0 +1,244 @@ +/* + * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc. + * + * SPDX-License-Identifier: MIT + * + * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD + */ + +/* + * Copyright (c) 2015-2019 Cadence Design Systems, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/******************************************************************************* +* +* RTOS-SPECIFIC INFORMATION FOR XTENSA RTOS ASSEMBLER SOURCES +* (FreeRTOS Port) +* +* This header is the primary glue between generic Xtensa RTOS support +* sources and a specific RTOS port for Xtensa. It contains definitions +* and macros for use primarily by Xtensa assembly coded source files. +* +* Macros in this header map callouts from generic Xtensa files to specific +* RTOS functions. It may also be included in C source files. +* +* Xtensa RTOS ports support all RTOS-compatible configurations of the Xtensa +* architecture, using the Xtensa hardware abstraction layer (HAL) to deal +* with configuration specifics. +* +* Should be included by all Xtensa generic and RTOS port-specific sources. +* +*******************************************************************************/ + +#ifndef XTENSA_RTOS_H +#define XTENSA_RTOS_H + +#ifdef __ASSEMBLER__ + #include +#else + #include +#endif + +#include +#include +#include "sdkconfig.h" + +/* + * Include any RTOS specific definitions that are needed by this header. + */ +#include "FreeRTOSConfig.h" + +/* + * Convert FreeRTOSConfig definitions to XTENSA definitions. + * However these can still be overridden from the command line. + */ + +#ifndef XT_SIMULATOR + #if configXT_SIMULATOR + #define XT_SIMULATOR 1 /* Simulator mode */ + #endif +#endif + +#ifndef XT_BOARD + #if configXT_BOARD + #define XT_BOARD 1 /* Board mode */ + #endif +#endif + +#ifndef XT_TIMER_INDEX + #if defined configXT_TIMER_INDEX + #define XT_TIMER_INDEX configXT_TIMER_INDEX /* Index of hardware timer to be used */ + #endif +#endif + +#ifndef XT_INTEXC_HOOKS + #if configXT_INTEXC_HOOKS + #define XT_INTEXC_HOOKS 1 /* Enables exception hooks */ + #endif +#endif + +#if !defined( XT_SIMULATOR ) && !defined( XT_BOARD ) + #error Either XT_SIMULATOR or XT_BOARD must be defined. +#endif + + +/* + * Name of RTOS (for messages). + */ +#define XT_RTOS_NAME FreeRTOS + +/* + * Check some Xtensa configuration requirements and report error if not met. + * Error messages can be customize to the RTOS port. + */ + +#if !XCHAL_HAVE_XEA2 + #error "FreeRTOS/Xtensa requires XEA2 (exception architecture 2)." +#endif + + +/******************************************************************************* +* +* RTOS CALLOUT MACROS MAPPED TO RTOS PORT-SPECIFIC FUNCTIONS. +* +* Define callout macros used in generic Xtensa code to interact with the RTOS. +* The macros are simply the function names for use in calls from assembler code. +* Some of these functions may call back to generic functions in xtensa_context.h . +* +*******************************************************************************/ + +/* + * Inform RTOS of entry into an interrupt handler that will affect it. + * Allows RTOS to manage switch to any system stack and count nesting level. + * Called after minimal context has been saved, with interrupts disabled. + * RTOS port can call0 _xt_context_save to save the rest of the context. + * May only be called from assembly code by the 'call0' instruction. + */ +/* void XT_RTOS_INT_ENTER(void) */ +#define XT_RTOS_INT_ENTER _frxt_int_enter + +/* + * Inform RTOS of completion of an interrupt handler, and give control to + * RTOS to perform thread/task scheduling, switch back from any system stack + * and restore the context, and return to the exit dispatcher saved in the + * stack frame at XT_STK_EXIT. RTOS port can call0 _xt_context_restore + * to save the context saved in XT_RTOS_INT_ENTER via _xt_context_save, + * leaving only a minimal part of the context to be restored by the exit + * dispatcher. This function does not return to the place it was called from. + * May only be called from assembly code by the 'call0' instruction. + */ +/* void XT_RTOS_INT_EXIT(void) */ +#define XT_RTOS_INT_EXIT _frxt_int_exit + +/* + * Inform RTOS of the occurrence of a tick timer interrupt. + * If RTOS has no tick timer, leave XT_RTOS_TIMER_INT undefined. + * May be coded in or called from C or assembly, per ABI conventions. + * RTOS may optionally define XT_TICK_PER_SEC in its own way (eg. macro). + */ +/* void XT_RTOS_TIMER_INT(void) */ +#ifdef CONFIG_FREERTOS_SYSTICK_USES_CCOUNT + #define XT_RTOS_TIMER_INT _frxt_timer_int +#endif +#define XT_TICK_PER_SEC configTICK_RATE_HZ + +/* + * Return in a15 the base address of the co-processor state save area for the + * thread that triggered a co-processor exception, or 0 if no thread was running. + * The state save area is structured as defined in xtensa_context.h and has size + * XT_CP_SIZE. Co-processor instructions should only be used in thread code, never + * in interrupt handlers or the RTOS kernel. May only be called from assembly code + * and by the 'call0' instruction. A result of 0 indicates an unrecoverable error. + * The implementation may use only a2-4, a15 (all other regs must be preserved). + */ +/* void* XT_RTOS_CP_STATE(void) */ +#define XT_RTOS_CP_STATE _frxt_task_coproc_state + + +/******************************************************************************* +* +* HOOKS TO DYNAMICALLY INSTALL INTERRUPT AND EXCEPTION HANDLERS PER LEVEL. +* +* This Xtensa RTOS port provides hooks for dynamically installing exception +* and interrupt handlers to facilitate automated testing where each test +* case can install its own handler for user exceptions and each interrupt +* priority (level). This consists of an array of function pointers indexed +* by interrupt priority, with index 0 being the user exception handler hook. +* Each entry in the array is initially 0, and may be replaced by a function +* pointer of type XT_INTEXC_HOOK. A handler may be uninstalled by installing 0. +* +* The handler for low and medium priority obeys ABI conventions so may be coded +* in C. For the exception handler, the cause is the contents of the EXCCAUSE +* reg, and the result is -1 if handled, else the cause (still needs handling). +* For interrupt handlers, the cause is a mask of pending enabled interrupts at +* that level, and the result is the same mask with the bits for the handled +* interrupts cleared (those not cleared still need handling). This allows a test +* case to either pre-handle or override the default handling for the exception +* or interrupt level (see xtensa_vectors.S). +* +* High priority handlers (including NMI) must be coded in assembly, are always +* called by 'call0' regardless of ABI, must preserve all registers except a0, +* and must not use or modify the interrupted stack. The hook argument 'cause' +* is not passed and the result is ignored, so as not to burden the caller with +* saving and restoring a2 (it assumes only one interrupt per level - see the +* discussion in high priority interrupts in xtensa_vectors.S). The handler +* therefore should be coded to prototype 'void h(void)' even though it plugs +* into an array of handlers of prototype 'unsigned h(unsigned)'. +* +* To enable interrupt/exception hooks, compile the RTOS with '-DXT_INTEXC_HOOKS'. +* +*******************************************************************************/ + +#define XT_INTEXC_HOOK_NUM ( 1 + XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI ) + +#ifndef __ASSEMBLER__ + typedef unsigned (* XT_INTEXC_HOOK)( unsigned cause ); + extern volatile XT_INTEXC_HOOK _xt_intexc_hooks[ XT_INTEXC_HOOK_NUM ]; +#endif + + +/******************************************************************************* +* +* CONVENIENCE INCLUSIONS. +* +* Ensures RTOS specific files need only include this one Xtensa-generic header. +* These headers are included last so they can use the RTOS definitions above. +* +*******************************************************************************/ + +#include "xtensa_context.h" + +#ifdef XT_RTOS_TIMER_INT + #include "xtensa_timer.h" +#endif + + +/******************************************************************************* +* +* Xtensa Port Version. +* +*******************************************************************************/ + +#define XTENSA_PORT_VERSION 1.4 .2 +#define XTENSA_PORT_VERSION_STRING "1.4.2" + +#endif /* XTENSA_RTOS_H */ diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_timer.h b/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_timer.h new file mode 100644 index 000000000..d046feac5 --- /dev/null +++ b/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_timer.h @@ -0,0 +1,168 @@ +/* + * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc. + * + * SPDX-License-Identifier: MIT + * + * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD + */ + +/* + * Copyright (c) 2015-2019 Cadence Design Systems, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/******************************************************************************* +* +* XTENSA INFORMATION FOR RTOS TICK TIMER AND CLOCK FREQUENCY +* +* This header contains definitions and macros for use primarily by Xtensa +* RTOS assembly coded source files. It includes and uses the Xtensa hardware +* abstraction layer (HAL) to deal with config specifics. It may also be +* included in C source files. +* +* User may edit to modify timer selection and to specify clock frequency and +* tick duration to match timer interrupt to the real-time tick duration. +* +* If the RTOS has no timer interrupt, then there is no tick timer and the +* clock frequency is irrelevant, so all of these macros are left undefined +* and the Xtensa core configuration need not have a timer. +* +*******************************************************************************/ + +#ifndef XTENSA_TIMER_H +#define XTENSA_TIMER_H + +#ifdef __ASSEMBLER__ + #include +#endif + +#include +#include + +#include "xtensa_rtos.h" /* in case this wasn't included directly */ + +#include "FreeRTOSConfig.h" + +/* + * Select timer to use for periodic tick, and determine its interrupt number + * and priority. User may specify a timer by defining XT_TIMER_INDEX with -D, + * in which case its validity is checked (it must exist in this core and must + * not be on a high priority interrupt - an error will be reported in invalid). + * Otherwise select the first low or medium priority interrupt timer available. + */ +#if XCHAL_NUM_TIMERS == 0 + + #error "This Xtensa configuration is unsupported, it has no timers." + +#else + + #ifndef XT_TIMER_INDEX + #if XCHAL_TIMER3_INTERRUPT != XTHAL_TIMER_UNCONFIGURED + #if XCHAL_INT_LEVEL( XCHAL_TIMER3_INTERRUPT ) <= XCHAL_EXCM_LEVEL + #undef XT_TIMER_INDEX + #define XT_TIMER_INDEX 3 + #endif + #endif + #if XCHAL_TIMER2_INTERRUPT != XTHAL_TIMER_UNCONFIGURED + #if XCHAL_INT_LEVEL( XCHAL_TIMER2_INTERRUPT ) <= XCHAL_EXCM_LEVEL + #undef XT_TIMER_INDEX + #define XT_TIMER_INDEX 2 + #endif + #endif + #if XCHAL_TIMER1_INTERRUPT != XTHAL_TIMER_UNCONFIGURED + #if XCHAL_INT_LEVEL( XCHAL_TIMER1_INTERRUPT ) <= XCHAL_EXCM_LEVEL + #undef XT_TIMER_INDEX + #define XT_TIMER_INDEX 1 + #endif + #endif + #if XCHAL_TIMER0_INTERRUPT != XTHAL_TIMER_UNCONFIGURED + #if XCHAL_INT_LEVEL( XCHAL_TIMER0_INTERRUPT ) <= XCHAL_EXCM_LEVEL + #undef XT_TIMER_INDEX + #define XT_TIMER_INDEX 0 + #endif + #endif + #endif /* ifndef XT_TIMER_INDEX */ + #ifndef XT_TIMER_INDEX + #error "There is no suitable timer in this Xtensa configuration." + #endif + + #define XT_CCOMPARE ( CCOMPARE + XT_TIMER_INDEX ) + #define XT_TIMER_INTNUM XCHAL_TIMER_INTERRUPT( XT_TIMER_INDEX ) + #define XT_TIMER_INTPRI XCHAL_INT_LEVEL( XT_TIMER_INTNUM ) + #define XT_TIMER_INTEN ( 1 << XT_TIMER_INTNUM ) + + #if XT_TIMER_INTNUM == XTHAL_TIMER_UNCONFIGURED + #error "The timer selected by XT_TIMER_INDEX does not exist in this core." + #elif XT_TIMER_INTPRI > XCHAL_EXCM_LEVEL + #error "The timer interrupt cannot be high priority (use medium or low)." + #endif + +#endif /* XCHAL_NUM_TIMERS */ + +/* + * Set processor clock frequency, used to determine clock divisor for timer tick. + * User should BE SURE TO ADJUST THIS for the Xtensa platform being used. + * If using a supported board via the board-independent API defined in xtbsp.h, + * this may be left undefined and frequency and tick divisor will be computed + * and cached during run-time initialization. + * + * NOTE ON SIMULATOR: + * Under the Xtensa instruction set simulator, the frequency can only be estimated + * because it depends on the speed of the host and the version of the simulator. + * Also because it runs much slower than hardware, it is not possible to achieve + * real-time performance for most applications under the simulator. A frequency + * too low does not allow enough time between timer interrupts, starving threads. + * To obtain a more convenient but non-real-time tick duration on the simulator, + * compile with xt-xcc option "-DXT_SIMULATOR". + * Adjust this frequency to taste (it's not real-time anyway!). + */ +#if defined( XT_SIMULATOR ) && !defined( XT_CLOCK_FREQ ) + #define XT_CLOCK_FREQ configCPU_CLOCK_HZ +#endif + +#if !defined( XT_CLOCK_FREQ ) && !defined( XT_BOARD ) + #error "XT_CLOCK_FREQ must be defined for the target platform." +#endif + +/* + * Default number of timer "ticks" per second (default 100 for 10ms tick). + * RTOS may define this in its own way (if applicable) in xtensa_rtos.h. + * User may redefine this to an optimal value for the application, either by + * editing this here or in xtensa_rtos.h, or compiling with xt-xcc option + * "-DXT_TICK_PER_SEC=" where is a suitable number. + */ +#ifndef XT_TICK_PER_SEC + #define XT_TICK_PER_SEC configTICK_RATE_HZ /* 10 ms tick = 100 ticks per second */ +#endif + +/* + * Derivation of clock divisor for timer tick and interrupt (one per tick). + */ +#ifdef XT_CLOCK_FREQ + #define XT_TICK_DIVISOR ( XT_CLOCK_FREQ / XT_TICK_PER_SEC ) +#endif + +#ifndef __ASSEMBLER__ + extern unsigned _xt_tick_divisor; + extern void _xt_tick_divisor_init( void ); +#endif + +#endif /* XTENSA_TIMER_H */ diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/port.c b/portable/ThirdParty/GCC/Xtensa_ESP32/port.c new file mode 100644 index 000000000..a89868baa --- /dev/null +++ b/portable/ThirdParty/GCC/Xtensa_ESP32/port.c @@ -0,0 +1,572 @@ +/* + * SPDX-FileCopyrightText: 2020 Amazon.com, Inc. or its affiliates + * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc. + * + * SPDX-License-Identifier: MIT + * + * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD + */ + +/* + * FreeRTOS Kernel + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + * 1 tab == 4 spaces! + */ + +/* + * Copyright (c) 2015-2019 Cadence Design Systems, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +#include "xtensa_rtos.h" +#include "esp_idf_version.h" + +#if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) ) + #include "rom/ets_sys.h" + #include "esp_panic.h" + #include "esp_crosscore_int.h" +#else + #if CONFIG_IDF_TARGET_ESP32S3 + #include "esp32s3/rom/ets_sys.h" + #elif CONFIG_IDF_TARGET_ESP32S2 + #include "esp32s2/rom/ets_sys.h" + #elif CONFIG_IDF_TARGET_ESP32 + #include "esp32/rom/ets_sys.h" + #endif + #include "esp_private/panic_reason.h" + #include "esp_debug_helpers.h" + #include "esp_private/crosscore_int.h" + #include "esp_log.h" +#endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0) */ +#include "soc/cpu.h" + +#include "FreeRTOS.h" +#include "task.h" + +#include "esp_heap_caps.h" + +#include "esp_intr_alloc.h" + +#include "port_systick.h" + +/* Defined in xtensa_context.S */ +extern void _xt_coproc_init( void ); + +_Static_assert( tskNO_AFFINITY == CONFIG_FREERTOS_NO_AFFINITY, "incorrect tskNO_AFFINITY value" ); + +/*-----------------------------------------------------------*/ + +extern volatile int port_xSchedulerRunning[ portNUM_PROCESSORS ]; +unsigned port_interruptNesting[ portNUM_PROCESSORS ] = { 0 }; /* Interrupt nesting level. Increased/decreased in portasm.c, _frxt_int_enter/_frxt_int_exit */ + +/*-----------------------------------------------------------*/ + +/* User exception dispatcher when exiting */ +void _xt_user_exit( void ); + +#if CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER +/* Wrapper to allow task functions to return (increases stack overhead by 16 bytes) */ + static void vPortTaskWrapper( TaskFunction_t pxCode, + void * pvParameters ) + { + pxCode( pvParameters ); + /*FreeRTOS tasks should not return. Log the task name and abort. */ + char * pcTaskName = pcTaskGetTaskName( NULL ); + ESP_LOGE( "FreeRTOS", "FreeRTOS Task \"%s\" should not return, Aborting now!", pcTaskName ); + abort(); + } +#endif /* if CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER */ + +/* + * Stack initialization + */ +/* *INDENT-OFF* */ +#if portUSING_MPU_WRAPPERS + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged ) +#else + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +#endif +/* *INDENT-ON* */ +{ + StackType_t * sp; + StackType_t * tp; + XtExcFrame * frame; + + #if XCHAL_CP_NUM > 0 + uint32_t * p; + #endif + + uint32_t * threadptr; + void * task_thread_local_start; + extern int _thread_local_start, _thread_local_end, _flash_rodata_start, _flash_rodata_align; + + /* TODO: check that TLS area fits the stack */ + uint32_t thread_local_sz = ( uint8_t * ) &_thread_local_end - ( uint8_t * ) &_thread_local_start; + + thread_local_sz = ALIGNUP( 0x10, thread_local_sz ); + + /* Initialize task's stack so that we have the following structure at the top: + * + * ----LOW ADDRESSES ----------------------------------------HIGH ADDRESSES---------- + * task stack | interrupt stack frame | thread local vars | co-processor save area | + * ---------------------------------------------------------------------------------- + | | + | SP pxTopOfStack + | + | All parts are aligned to 16 byte boundary. + */ + + /* Create interrupt stack frame aligned to 16 byte boundary */ + sp = ( StackType_t * ) ( ( ( UBaseType_t ) pxTopOfStack - XT_CP_SIZE - thread_local_sz - XT_STK_FRMSZ ) & ~0xf ); + + /* Clear the entire frame (do not use memset() because we don't depend on C library) */ + for( tp = sp; tp <= pxTopOfStack; ++tp ) + { + *tp = 0; + } + + frame = ( XtExcFrame * ) sp; + + /* Explicitly initialize certain saved registers */ + #if CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER + frame->pc = ( UBaseType_t ) vPortTaskWrapper; /* task wrapper */ + #else + frame->pc = ( UBaseType_t ) pxCode; /* task entrypoint */ + #endif + frame->a0 = 0; /* to terminate GDB backtrace */ + frame->a1 = ( UBaseType_t ) sp + XT_STK_FRMSZ; /* physical top of stack frame */ + frame->exit = ( UBaseType_t ) _xt_user_exit; /* user exception exit dispatcher */ + + /* Set initial PS to int level 0, EXCM disabled ('rfe' will enable), user mode. */ + /* Also set entry point argument parameter. */ + #ifdef __XTENSA_CALL0_ABI__ + #if CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER + frame->a2 = ( UBaseType_t ) pxCode; + frame->a3 = ( UBaseType_t ) pvParameters; + #else + frame->a2 = ( UBaseType_t ) pvParameters; + #endif + frame->ps = PS_UM | PS_EXCM; + #else + /* + for windowed ABI also set WOE and CALLINC (pretend task was 'call4'd). */ + #if CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER + frame->a6 = ( UBaseType_t ) pxCode; + frame->a7 = ( UBaseType_t ) pvParameters; + #else + frame->a6 = ( UBaseType_t ) pvParameters; + #endif + frame->ps = PS_UM | PS_EXCM | PS_WOE | PS_CALLINC( 1 ); + #endif /* ifdef __XTENSA_CALL0_ABI__ */ + + #ifdef XT_USE_SWPRI + /* Set the initial virtual priority mask value to all 1's. */ + frame->vpri = 0xFFFFFFFF; + #endif + + /* Init threadptr register and set up TLS run-time area. */ + task_thread_local_start = ( void * ) ( ( ( uint32_t ) pxTopOfStack - XT_CP_SIZE - thread_local_sz ) & ~0xf ); + memcpy( task_thread_local_start, &_thread_local_start, thread_local_sz ); + threadptr = ( uint32_t * ) ( sp + XT_STK_EXTRA ); + + /* Calculate THREADPTR value. + * The generated code will add THREADPTR value to a constant value determined at link time, + * to get the address of the TLS variable. + * The constant value is calculated by the linker as follows + * (search for 'tpoff' in elf32-xtensa.c in BFD): + * offset = address - tls_section_vma + align_up(TCB_SIZE, tls_section_alignment) + * where TCB_SIZE is hardcoded to 8. + */ + const uint32_t tls_section_alignment = ( uint32_t ) &_flash_rodata_align; /* ALIGN value of .flash.rodata section */ + const uint32_t tcb_size = 8; /* Unrelated to FreeRTOS, this is the constant from BFD */ + const uint32_t base = ( tcb_size + tls_section_alignment - 1 ) & ( ~( tls_section_alignment - 1 ) ); + *threadptr = ( uint32_t ) task_thread_local_start - ( ( uint32_t ) &_thread_local_start - ( uint32_t ) &_flash_rodata_start ) - base; + + #if XCHAL_CP_NUM > 0 + /* Init the coprocessor save area (see xtensa_context.h) */ + + /* No access to TCB here, so derive indirectly. Stack growth is top to bottom. + * //p = (uint32_t *) xMPUSettings->coproc_area; + */ + p = ( uint32_t * ) ( ( ( uint32_t ) pxTopOfStack - XT_CP_SIZE ) & ~0xf ); + configASSERT( ( uint32_t ) p >= frame->a1 ); + p[ 0 ] = 0; + p[ 1 ] = 0; + p[ 2 ] = ( ( ( uint32_t ) p ) + 12 + XCHAL_TOTAL_SA_ALIGN - 1 ) & -XCHAL_TOTAL_SA_ALIGN; + #endif + + return sp; +} + +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the Xtensa port will get stopped. If required simply + * disable the tick interrupt here. */ + abort(); +} + +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + portDISABLE_INTERRUPTS(); + /* Interrupts are disabled at this point and stack contains PS with enabled interrupts when task context is restored */ + + #if XCHAL_CP_NUM > 0 + /* Initialize co-processor management for tasks. Leave CPENABLE alone. */ + _xt_coproc_init(); + #endif + + /* Setup the hardware to generate the tick */ + vPortSetupTimer(); + + /* NOTE: For ESP32-S3, vPortSetupTimer allocates an interrupt for the + * systimer which is used as the source for FreeRTOS systick. + * + * The behaviour of portEXIT_CRITICAL is different in FreeRTOS and ESP-IDF - + * the former enables the interrupts no matter what the state was at the beginning + * of the call while the latter restores the interrupt state to what was at the + * beginning of the call. + * + * This resulted in the interrupts being enabled before the _frxt_dispatch call, + * who was unable to switch context to the queued tasks. + */ + portDISABLE_INTERRUPTS(); + + port_xSchedulerRunning[ xPortGetCoreID() ] = 1; + + /* Cannot be directly called from C; never returns */ + __asm__ volatile ( "call0 _frxt_dispatch\n" ); + + /* Should not get here. */ + return pdTRUE; +} + +/*-----------------------------------------------------------*/ + +void vPortYieldOtherCore( BaseType_t coreid ) +{ + esp_crosscore_int_send_yield( coreid ); +} + +/*-----------------------------------------------------------*/ + +/* + * Used to set coprocessor area in stack. Current hack is to reuse MPU pointer for coprocessor area. + */ +#if portUSING_MPU_WRAPPERS + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + configSTACK_DEPTH_TYPE uxStackDepth ) + { + #if XCHAL_CP_NUM > 0 + xMPUSettings->coproc_area = ( StackType_t * ) ( ( uint32_t ) ( pxBottomOfStack + uxStackDepth - 1 ) ); + xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) xMPUSettings->coproc_area ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); + xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( uint32_t ) xMPUSettings->coproc_area - XT_CP_SIZE ) & ~0xf ); + + /* NOTE: we cannot initialize the coprocessor save area here because FreeRTOS is going to + * clear the stack area after we return. This is done in pxPortInitialiseStack(). + */ + #endif + } + + void vPortReleaseTaskMPUSettings( xMPU_SETTINGS * xMPUSettings ) + { + /* If task has live floating point registers somewhere, release them */ + _xt_coproc_release( xMPUSettings->coproc_area ); + } + +#endif /* if portUSING_MPU_WRAPPERS */ + +/* + * Returns true if the current core is in ISR context; low prio ISR, med prio ISR or timer tick ISR. High prio ISRs + * aren't detected here, but they normally cannot call C code, so that should not be an issue anyway. + */ +BaseType_t xPortInIsrContext() +{ + unsigned int irqStatus; + BaseType_t ret; + + irqStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + ret = ( port_interruptNesting[ xPortGetCoreID() ] != 0 ); + portCLEAR_INTERRUPT_MASK_FROM_ISR( irqStatus ); + return ret; +} + +/* + * This function will be called in High prio ISRs. Returns true if the current core was in ISR context + * before calling into high prio ISR context. + */ +BaseType_t IRAM_ATTR xPortInterruptedFromISRContext() +{ + return( port_interruptNesting[ xPortGetCoreID() ] != 0 ); +} + +void IRAM_ATTR vPortEvaluateYieldFromISR( int argc, + ... ) +{ + BaseType_t xYield; + va_list ap; + + va_start( ap, argc ); + + if( argc ) + { + xYield = ( BaseType_t ) va_arg( ap, int ); + va_end( ap ); + } + else + { + /*it is a empty parameter vPortYieldFromISR macro call: */ + va_end( ap ); + traceISR_EXIT_TO_SCHEDULER(); + _frxt_setup_switch(); + return; + } + + /*Yield exists, so need evaluate it first then switch: */ + if( xYield == pdTRUE ) + { + traceISR_EXIT_TO_SCHEDULER(); + _frxt_setup_switch(); + } +} + +void vPortAssertIfInISR() +{ + if( xPortInIsrContext() ) + { + esp_rom_printf( "core=%d port_interruptNesting=%d\n\n", xPortGetCoreID(), port_interruptNesting[ xPortGetCoreID() ] ); + } + + configASSERT( !xPortInIsrContext() ); +} + +/* + * For kernel use: Initialize a per-CPU mux. Mux will be initialized unlocked. + */ +void vPortCPUInitializeMutex( portMUX_TYPE * mux ) +{ + #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG + esp_rom_printf( "Initializing mux %p\n", mux ); + mux->lastLockedFn = "(never locked)"; + mux->lastLockedLine = -1; + #endif + mux->owner = portMUX_FREE_VAL; + mux->count = 0; +} + +#include "portmux_impl.h" + +/* + * For kernel use: Acquire a per-CPU mux. Spinlocks, so don't hold on to these muxes for too long. + */ +#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG + void vPortCPUAcquireMutex( portMUX_TYPE * mux, + const char * fnName, + int line ) + { + unsigned int irqStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + + vPortCPUAcquireMutexIntsDisabled( mux, portMUX_NO_TIMEOUT, fnName, line ); + portCLEAR_INTERRUPT_MASK_FROM_ISR( irqStatus ); + } + + bool vPortCPUAcquireMutexTimeout( portMUX_TYPE * mux, + int timeout_cycles, + const char * fnName, + int line ) + { + unsigned int irqStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + bool result = vPortCPUAcquireMutexIntsDisabled( mux, timeout_cycles, fnName, line ); + + portCLEAR_INTERRUPT_MASK_FROM_ISR( irqStatus ); + return result; + } + +#else /* ifdef CONFIG_FREERTOS_PORTMUX_DEBUG */ + void vPortCPUAcquireMutex( portMUX_TYPE * mux ) + { + unsigned int irqStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + + vPortCPUAcquireMutexIntsDisabled( mux, portMUX_NO_TIMEOUT ); + portCLEAR_INTERRUPT_MASK_FROM_ISR( irqStatus ); + } + + bool vPortCPUAcquireMutexTimeout( portMUX_TYPE * mux, + int timeout_cycles ) + { + unsigned int irqStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + bool result = vPortCPUAcquireMutexIntsDisabled( mux, timeout_cycles ); + + portCLEAR_INTERRUPT_MASK_FROM_ISR( irqStatus ); + return result; + } +#endif /* ifdef CONFIG_FREERTOS_PORTMUX_DEBUG */ + + +/* + * For kernel use: Release a per-CPU mux + * + * Mux must be already locked by this core + */ +#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG + void vPortCPUReleaseMutex( portMUX_TYPE * mux, + const char * fnName, + int line ) + { + unsigned int irqStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + + vPortCPUReleaseMutexIntsDisabled( mux, fnName, line ); + portCLEAR_INTERRUPT_MASK_FROM_ISR( irqStatus ); + } +#else + void vPortCPUReleaseMutex( portMUX_TYPE * mux ) + { + unsigned int irqStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + + vPortCPUReleaseMutexIntsDisabled( mux ); + portCLEAR_INTERRUPT_MASK_FROM_ISR( irqStatus ); + } +#endif /* ifdef CONFIG_FREERTOS_PORTMUX_DEBUG */ + +#define STACK_WATCH_AREA_SIZE ( 32 ) +#define STACK_WATCH_POINT_NUMBER ( SOC_CPU_WATCHPOINTS_NUM - 1 ) + +void vPortSetStackWatchpoint( void * pxStackStart ) +{ + /*Set watchpoint 1 to watch the last 32 bytes of the stack. */ + /*Unfortunately, the Xtensa watchpoints can't set a watchpoint on a random [base - base+n] region because */ + /*the size works by masking off the lowest address bits. For that reason, we futz a bit and watch the lowest 32 */ + /*bytes of the stack we can actually watch. In general, this can cause the watchpoint to be triggered at most */ + /*28 bytes early. The value 32 is chosen because it's larger than the stack canary, which in FreeRTOS is 20 bytes. */ + /*This way, we make sure we trigger before/when the stack canary is corrupted, not after. */ + int addr = ( int ) pxStackStart; + + addr = ( addr + 31 ) & ( ~31 ); + esp_cpu_set_watchpoint( STACK_WATCH_POINT_NUMBER, ( char * ) addr, 32, ESP_WATCHPOINT_STORE ); +} + +#if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) ) + + #if defined( CONFIG_SPIRAM_SUPPORT ) + +/* + * Compare & set (S32C1) does not work in external RAM. Instead, this routine uses a mux (in internal memory) to fake it. + */ + static portMUX_TYPE extram_mux = portMUX_INITIALIZER_UNLOCKED; + + void uxPortCompareSetExtram( volatile uint32_t * addr, + uint32_t compare, + uint32_t * set ) + { + uint32_t prev; + + uint32_t oldlevel = portSET_INTERRUPT_MASK_FROM_ISR(); + + #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG + vPortCPUAcquireMutexIntsDisabled( &extram_mux, portMUX_NO_TIMEOUT, __FUNCTION__, __LINE__ ); + #else + vPortCPUAcquireMutexIntsDisabled( &extram_mux, portMUX_NO_TIMEOUT ); + #endif + prev = *addr; + + if( prev == compare ) + { + *addr = *set; + } + + *set = prev; + #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG + vPortCPUReleaseMutexIntsDisabled( &extram_mux, __FUNCTION__, __LINE__ ); + #else + vPortCPUReleaseMutexIntsDisabled( &extram_mux ); + #endif + + portCLEAR_INTERRUPT_MASK_FROM_ISR( oldlevel ); + } + #endif //defined(CONFIG_SPIRAM_SUPPORT) + +#endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0) */ + + +uint32_t xPortGetTickRateHz( void ) +{ + return ( uint32_t ) configTICK_RATE_HZ; +} + +/* For now, running FreeRTOS on one core and a bare metal on the other (or other OSes) */ +/* is not supported. For now CONFIG_FREERTOS_UNICORE and CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE */ +/* should mirror each other's values. */ +/* */ +/* And since this should be true, we can just check for CONFIG_FREERTOS_UNICORE. */ +#if CONFIG_FREERTOS_UNICORE != CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE + #error "FreeRTOS and system configuration mismatch regarding the use of multiple cores." +#endif + +extern void esp_startup_start_app_common( void ); + +void esp_startup_start_app( void ) +{ + #if !CONFIG_ESP_INT_WDT + #if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX + assert( !soc_has_cache_lock_bug() && "ESP32 Rev 3 + Dual Core + PSRAM requires INT WDT enabled in project config!" ); + #endif + #endif + + esp_startup_start_app_common(); + + ESP_LOGI( "cpu_start", "Starting scheduler on PRO CPU." ); + vTaskStartScheduler(); +} diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/port_common.c b/portable/ThirdParty/GCC/Xtensa_ESP32/port_common.c new file mode 100644 index 000000000..cd8193a89 --- /dev/null +++ b/portable/ThirdParty/GCC/Xtensa_ESP32/port_common.c @@ -0,0 +1,167 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "FreeRTOS.h" +#include "task.h" +#include "portmacro.h" +#include "esp_system.h" +#include "esp_heap_caps_init.h" +#include "esp_int_wdt.h" +#include "esp_task_wdt.h" +#include "esp_task.h" +#include "esp_private/crosscore_int.h" +#include "esp_private/startup_internal.h" /* Required by g_spiram_ok. [refactor-todo] for g_spiram_ok */ +#include "esp_log.h" +#include "soc/soc_memory_types.h" +#include "soc/dport_access.h" +#include "sdkconfig.h" +#include "esp_freertos_hooks.h" + +#if CONFIG_IDF_TARGET_ESP32 + #include "esp32/spiram.h" +#elif CONFIG_IDF_TARGET_ESP32S2 + #include "esp32s2/spiram.h" +#elif CONFIG_IDF_TARGET_ESP32S3 + #include "esp32s3/spiram.h" +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 +/* SPIRAM is not supported on ESP32-C3 */ +#endif + +#if CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL + static const char * TAG = "cpu_start"; +#endif + +/* Architecture-agnostic parts of the FreeRTOS ESP-IDF port layer can go here. + * + * The actual call flow will be to call esp_startup_start_app() in /port.c, + * which will then call esp_startup_start_app_common() + */ + +/* Duplicate of inaccessible xSchedulerRunning; needed at startup to avoid counting nesting */ +volatile unsigned port_xSchedulerRunning[ portNUM_PROCESSORS ] = { 0 }; + +/* For now, running FreeRTOS on one core and a bare metal on the other (or other OSes) */ +/* is not supported. For now CONFIG_FREERTOS_UNICORE and CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE */ +/* should mirror each other's values. */ +/* */ +/* And since this should be true, we can just check for CONFIG_FREERTOS_UNICORE. */ +#if CONFIG_FREERTOS_UNICORE != CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE + #error "FreeRTOS and system configuration mismatch regarding the use of multiple cores." +#endif + +static void main_task( void * args ); + +#ifdef CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME + void esp_gdbstub_init( void ); +#endif // CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME + +extern void app_main( void ); + +void esp_startup_start_app_common( void ) +{ + #if CONFIG_ESP_INT_WDT + esp_int_wdt_init(); + /*Initialize the interrupt watch dog for CPU0. */ + esp_int_wdt_cpu_init(); + #endif + + esp_crosscore_int_init(); + + #ifdef CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME + esp_gdbstub_init(); + #endif // CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME + + portBASE_TYPE res = xTaskCreatePinnedToCore( &main_task, "main", + ESP_TASK_MAIN_STACK, NULL, + ESP_TASK_MAIN_PRIO, NULL, ESP_TASK_MAIN_CORE ); + assert( res == pdTRUE ); + ( void ) res; +} + +#if !CONFIG_FREERTOS_UNICORE + static volatile bool s_other_cpu_startup_done = false; + static bool other_cpu_startup_idle_hook_cb( void ) + { + s_other_cpu_startup_done = true; + return true; + } +#endif + +static void main_task( void * args ) +{ + #if !CONFIG_FREERTOS_UNICORE + /* Wait for FreeRTOS initialization to finish on other core, before replacing its startup stack */ + esp_register_freertos_idle_hook_for_cpu( other_cpu_startup_idle_hook_cb, !xPortGetCoreID() ); + + while( !s_other_cpu_startup_done ) + { + } + esp_deregister_freertos_idle_hook_for_cpu( other_cpu_startup_idle_hook_cb, !xPortGetCoreID() ); + #endif + + /* [refactor-todo] check if there is a way to move the following block to esp_system startup */ + heap_caps_enable_nonos_stack_heaps(); + + /* Now we have startup stack RAM available for heap, enable any DMA pool memory */ + #if CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL + if( g_spiram_ok ) + { + esp_err_t r = esp_spiram_reserve_dma_pool( CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL ); + + if( r != ESP_OK ) + { + ESP_EARLY_LOGE( TAG, "Could not reserve internal/DMA pool (error 0x%x)", r ); + abort(); + } + } + #endif /* if CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL */ + + /*Initialize task wdt if configured to do so */ + #ifdef CONFIG_ESP_TASK_WDT_PANIC + ESP_ERROR_CHECK( esp_task_wdt_init( CONFIG_ESP_TASK_WDT_TIMEOUT_S, true ) ); + #elif CONFIG_ESP_TASK_WDT + ESP_ERROR_CHECK( esp_task_wdt_init( CONFIG_ESP_TASK_WDT_TIMEOUT_S, false ) ); + #endif + + /*Add IDLE 0 to task wdt */ + #ifdef CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0 + TaskHandle_t idle_0 = xTaskGetIdleTaskHandleForCPU( 0 ); + + if( idle_0 != NULL ) + { + ESP_ERROR_CHECK( esp_task_wdt_add( idle_0 ) ); + } + #endif + /*Add IDLE 1 to task wdt */ + #ifdef CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1 + TaskHandle_t idle_1 = xTaskGetIdleTaskHandleForCPU( 1 ); + + if( idle_1 != NULL ) + { + ESP_ERROR_CHECK( esp_task_wdt_add( idle_1 ) ); + } + #endif + + app_main(); + vTaskDelete( NULL ); +} + +/* -------------------- Heap Related ----------------------- */ + +bool xPortCheckValidTCBMem( const void * ptr ) +{ + return esp_ptr_internal( ptr ) && esp_ptr_byte_accessible( ptr ); +} + +bool xPortcheckValidStackMem( const void * ptr ) +{ + #ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY + return esp_ptr_byte_accessible( ptr ); + #else + return esp_ptr_internal( ptr ) && esp_ptr_byte_accessible( ptr ); + #endif +} diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/port_systick.c b/portable/ThirdParty/GCC/Xtensa_ESP32/port_systick.c new file mode 100644 index 000000000..b7a49170b --- /dev/null +++ b/portable/ThirdParty/GCC/Xtensa_ESP32/port_systick.c @@ -0,0 +1,197 @@ +/* + * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include "soc/cpu.h" +#include "FreeRTOS.h" +#include "task.h" +#include "esp_intr_alloc.h" +#include "esp_err.h" +#include "esp_log.h" +#include "sdkconfig.h" +#ifdef CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER + #include "soc/periph_defs.h" + #include "soc/system_reg.h" + #include "hal/systimer_hal.h" + #include "hal/systimer_ll.h" +#endif + +#ifdef CONFIG_PM_TRACE + #include "esp_private/pm_trace.h" +#endif //CONFIG_PM_TRACE + +BaseType_t xPortSysTickHandler( void ); + +#ifdef CONFIG_FREERTOS_SYSTICK_USES_CCOUNT + extern void _frxt_tick_timer_init( void ); + extern void _xt_tick_divisor_init( void ); + + #ifdef CONFIG_FREERTOS_CORETIMER_0 + #define SYSTICK_INTR_ID ( ETS_INTERNAL_TIMER0_INTR_SOURCE + ETS_INTERNAL_INTR_SOURCE_OFF ) + #endif + #ifdef CONFIG_FREERTOS_CORETIMER_1 + #define SYSTICK_INTR_ID ( ETS_INTERNAL_TIMER1_INTR_SOURCE + ETS_INTERNAL_INTR_SOURCE_OFF ) + #endif + +/** + * @brief Initialize CCONT timer to generate the tick interrupt + * + */ + void vPortSetupTimer( void ) + { + /* Init the tick divisor value */ + _xt_tick_divisor_init(); + + _frxt_tick_timer_init(); + } + + +#elif CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER + + _Static_assert( SOC_CPU_CORES_NUM <= SOC_SYSTIMER_ALARM_NUM - 1, "the number of cores must match the number of core alarms in SYSTIMER" ); + + void SysTickIsrHandler( void * arg ); + + static uint32_t s_handled_systicks[ portNUM_PROCESSORS ] = { 0 }; + + #define SYSTICK_INTR_ID ( ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE ) + +/** + * @brief Set up the systimer peripheral to generate the tick interrupt + * + * Both timer alarms are configured in periodic mode. + * It is done at the same time so SysTicks for both CPUs occur at the same time or very close. + * Shifts a time of triggering interrupts for core 0 and core 1. + */ + void vPortSetupTimer( void ) + { + unsigned cpuid = xPortGetCoreID(); + + #ifdef CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL3 + const unsigned level = ESP_INTR_FLAG_LEVEL3; + #else + const unsigned level = ESP_INTR_FLAG_LEVEL1; + #endif + /* Systimer HAL layer object */ + static systimer_hal_context_t systimer_hal; + /* set system timer interrupt vector */ + ESP_ERROR_CHECK( esp_intr_alloc( ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE + cpuid, ESP_INTR_FLAG_IRAM | level, SysTickIsrHandler, &systimer_hal, NULL ) ); + + if( cpuid == 0 ) + { + systimer_hal_init( &systimer_hal ); + systimer_ll_set_counter_value( systimer_hal.dev, SYSTIMER_LL_COUNTER_OS_TICK, 0 ); + systimer_ll_apply_counter_value( systimer_hal.dev, SYSTIMER_LL_COUNTER_OS_TICK ); + + for( cpuid = 0; cpuid < SOC_CPU_CORES_NUM; cpuid++ ) + { + systimer_hal_counter_can_stall_by_cpu( &systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK, cpuid, false ); + } + + for( cpuid = 0; cpuid < portNUM_PROCESSORS; ++cpuid ) + { + uint32_t alarm_id = SYSTIMER_LL_ALARM_OS_TICK_CORE0 + cpuid; + + /* configure the timer */ + systimer_hal_connect_alarm_counter( &systimer_hal, alarm_id, SYSTIMER_LL_COUNTER_OS_TICK ); + systimer_hal_set_alarm_period( &systimer_hal, alarm_id, 1000000UL / CONFIG_FREERTOS_HZ ); + systimer_hal_select_alarm_mode( &systimer_hal, alarm_id, SYSTIMER_ALARM_MODE_PERIOD ); + systimer_hal_counter_can_stall_by_cpu( &systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK, cpuid, true ); + + if( cpuid == 0 ) + { + systimer_hal_enable_alarm_int( &systimer_hal, alarm_id ); + systimer_hal_enable_counter( &systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK ); + #ifndef CONFIG_FREERTOS_UNICORE + /* SysTick of core 0 and core 1 are shifted by half of period */ + systimer_hal_counter_value_advance( &systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK, 1000000UL / CONFIG_FREERTOS_HZ / 2 ); + #endif + } + } + } + else + { + uint32_t alarm_id = SYSTIMER_LL_ALARM_OS_TICK_CORE0 + cpuid; + systimer_hal_enable_alarm_int( &systimer_hal, alarm_id ); + } + } + +/** + * @brief Systimer interrupt handler. + * + * The Systimer interrupt for SysTick works in periodic mode no need to calc the next alarm. + * If a timer interrupt is ever serviced more than one tick late, it is necessary to process multiple ticks. + */ + IRAM_ATTR void SysTickIsrHandler( void * arg ) + { + uint32_t cpuid = xPortGetCoreID(); + systimer_hal_context_t * systimer_hal = ( systimer_hal_context_t * ) arg; + + #ifdef CONFIG_PM_TRACE + ESP_PM_TRACE_ENTER( TICK, cpuid ); + #endif + + uint32_t alarm_id = SYSTIMER_LL_ALARM_OS_TICK_CORE0 + cpuid; + + do + { + systimer_ll_clear_alarm_int( systimer_hal->dev, alarm_id ); + + uint32_t diff = systimer_hal_get_counter_value( systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK ) / systimer_ll_get_alarm_period( systimer_hal->dev, alarm_id ) - s_handled_systicks[ cpuid ]; + + if( diff > 0 ) + { + if( s_handled_systicks[ cpuid ] == 0 ) + { + s_handled_systicks[ cpuid ] = diff; + diff = 1; + } + else + { + s_handled_systicks[ cpuid ] += diff; + } + + do + { + xPortSysTickHandler(); + } while( --diff ); + } + } while( systimer_ll_is_alarm_int_fired( systimer_hal->dev, alarm_id ) ); + + #ifdef CONFIG_PM_TRACE + ESP_PM_TRACE_EXIT( TICK, cpuid ); + #endif + } + +#endif // CONFIG_FREERTOS_SYSTICK_USES_CCOUNT + +/** + * @brief Handler of SysTick + * + * The function is called from: + * - _frxt_timer_int for xtensa with CONFIG_FREERTOS_SYSTICK_USES_CCOUNT + * - SysTickIsrHandler for xtensa with CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER + * - SysTickIsrHandler for riscv + */ +BaseType_t xPortSysTickHandler( void ) +{ + portbenchmarkIntLatency(); + traceISR_ENTER( SYSTICK_INTR_ID ); + BaseType_t ret = xTaskIncrementTick(); + + if( ret != pdFALSE ) + { + traceISR_EXIT_TO_SCHEDULER(); + portYIELD_FROM_ISR(); + } + else + { + traceISR_EXIT(); + } + + return ret; +} diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/portasm.S b/portable/ThirdParty/GCC/Xtensa_ESP32/portasm.S new file mode 100644 index 000000000..809752455 --- /dev/null +++ b/portable/ThirdParty/GCC/Xtensa_ESP32/portasm.S @@ -0,0 +1,701 @@ +/* + * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc. + * + * SPDX-License-Identifier: MIT + * + * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD + */ +/* + * Copyright (c) 2015-2019 Cadence Design Systems, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "xtensa_rtos.h" +#include "sdkconfig.h" +#include "esp_idf_version.h" + +#define TOPOFSTACK_OFFS 0x00 /* StackType_t *pxTopOfStack */ +#define CP_TOPOFSTACK_OFFS 0x04 /* xMPU_SETTINGS.coproc_area */ + +.extern pxCurrentTCB + +/* +******************************************************************************* +* Interrupt stack. The size of the interrupt stack is determined by the config +* parameter "configISR_STACK_SIZE" in FreeRTOSConfig.h +******************************************************************************* +*/ + + .data + .align 16 + .global port_IntStack + .global port_IntStackTop + .global port_switch_flag +port_IntStack: + .space configISR_STACK_SIZE*portNUM_PROCESSORS /* This allocates stacks for each individual CPU. */ +port_IntStackTop: + .word 0 +port_switch_flag: + .space portNUM_PROCESSORS*4 /* One flag for each individual CPU. */ + + .text + +/* +******************************************************************************* +* _frxt_setup_switch +* void _frxt_setup_switch(void); +* +* Sets an internal flag indicating that a task switch is required on return +* from interrupt handling. +* +******************************************************************************* +*/ + .global _frxt_setup_switch + .type _frxt_setup_switch,@function + .align 4 +_frxt_setup_switch: + + ENTRY(16) + + getcoreid a3 + movi a2, port_switch_flag + addx4 a2, a3, a2 + + movi a3, 1 + s32i a3, a2, 0 + + RET(16) + + + + + + +/* +******************************************************************************* +* _frxt_int_enter +* void _frxt_int_enter(void) +* +* Implements the Xtensa RTOS porting layer's XT_RTOS_INT_ENTER function for +* freeRTOS. Saves the rest of the interrupt context (not already saved). +* May only be called from assembly code by the 'call0' instruction, with +* interrupts disabled. +* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h. +* +******************************************************************************* +*/ + .globl _frxt_int_enter + .type _frxt_int_enter,@function + .align 4 +_frxt_int_enter: + + /* Save a12-13 in the stack frame as required by _xt_context_save. */ + s32i a12, a1, XT_STK_A12 + s32i a13, a1, XT_STK_A13 + + /* Save return address in a safe place (free a0). */ + mov a12, a0 + + /* Save the rest of the interrupted context (preserves A12-13). */ + call0 _xt_context_save + + /* + Save interrupted task's SP in TCB only if not nesting. + Manage nesting directly rather than call the generic IntEnter() + (in windowed ABI we can't call a C function here anyway because PS.EXCM is still set). + */ + getcoreid a4 + movi a2, port_xSchedulerRunning + addx4 a2, a4, a2 + movi a3, port_interruptNesting + addx4 a3, a4, a3 + l32i a2, a2, 0 /* a2 = port_xSchedulerRunning */ + beqz a2, 1f /* scheduler not running, no tasks */ + l32i a2, a3, 0 /* a2 = port_interruptNesting */ + addi a2, a2, 1 /* increment nesting count */ + s32i a2, a3, 0 /* save nesting count */ + bnei a2, 1, .Lnested /* !=0 before incr, so nested */ + + movi a2, pxCurrentTCB + addx4 a2, a4, a2 + l32i a2, a2, 0 /* a2 = current TCB */ + beqz a2, 1f + s32i a1, a2, TOPOFSTACK_OFFS /* pxCurrentTCB->pxTopOfStack = SP */ + movi a1, port_IntStack+configISR_STACK_SIZE /* a1 = top of intr stack for CPU 0 */ + movi a2, configISR_STACK_SIZE /* add configISR_STACK_SIZE * cpu_num to arrive at top of stack for cpu_num */ + mull a2, a4, a2 + add a1, a1, a2 /* for current proc */ + + #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) + #ifdef CONFIG_FREERTOS_FPU_IN_ISR + #if XCHAL_CP_NUM > 0 + rsr a3, CPENABLE /* Restore thread scope CPENABLE */ + addi sp, sp,-4 /* ISR will manage FPU coprocessor by forcing */ + s32i a3, a1, 0 /* its trigger */ + #endif + #endif + #endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */ + +.Lnested: +1: + #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) + #ifdef CONFIG_FREERTOS_FPU_IN_ISR + #if XCHAL_CP_NUM > 0 + movi a3, 0 /* whilst ISRs pending keep CPENABLE exception active */ + wsr a3, CPENABLE + rsync + #endif + #endif + #endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */ + + mov a0, a12 /* restore return addr and return */ + ret + +/* +******************************************************************************* +* _frxt_int_exit +* void _frxt_int_exit(void) +* +* Implements the Xtensa RTOS porting layer's XT_RTOS_INT_EXIT function for +* FreeRTOS. If required, calls vPortYieldFromInt() to perform task context +* switching, restore the (possibly) new task's context, and return to the +* exit dispatcher saved in the task's stack frame at XT_STK_EXIT. +* May only be called from assembly code by the 'call0' instruction. Does not +* return to caller. +* See the description of the XT_RTOS_ENTER macro in xtensa_rtos.h. +* +******************************************************************************* +*/ + .globl _frxt_int_exit + .type _frxt_int_exit,@function + .align 4 +_frxt_int_exit: + + getcoreid a4 + movi a2, port_xSchedulerRunning + addx4 a2, a4, a2 + movi a3, port_interruptNesting + addx4 a3, a4, a3 + rsil a0, XCHAL_EXCM_LEVEL /* lock out interrupts */ + l32i a2, a2, 0 /* a2 = port_xSchedulerRunning */ + beqz a2, .Lnoswitch /* scheduler not running, no tasks */ + l32i a2, a3, 0 /* a2 = port_interruptNesting */ + addi a2, a2, -1 /* decrement nesting count */ + s32i a2, a3, 0 /* save nesting count */ + bnez a2, .Lnesting /* !=0 after decr so still nested */ + + #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) + #ifdef CONFIG_FREERTOS_FPU_IN_ISR + #if XCHAL_CP_NUM > 0 + l32i a3, sp, 0 /* Grab last CPENABLE before leave ISR */ + addi sp, sp, 4 + wsr a3, CPENABLE + rsync /* ensure CPENABLE was modified */ + #endif + #endif + #endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */ + + movi a2, pxCurrentTCB + addx4 a2, a4, a2 + l32i a2, a2, 0 /* a2 = current TCB */ + beqz a2, 1f /* no task ? go to dispatcher */ + l32i a1, a2, TOPOFSTACK_OFFS /* SP = pxCurrentTCB->pxTopOfStack */ + + movi a2, port_switch_flag /* address of switch flag */ + addx4 a2, a4, a2 /* point to flag for this cpu */ + l32i a3, a2, 0 /* a3 = port_switch_flag */ + beqz a3, .Lnoswitch /* flag = 0 means no switch reqd */ + movi a3, 0 + s32i a3, a2, 0 /* zero out the flag for next time */ + +1: + /* + Call0 ABI callee-saved regs a12-15 need to be saved before possible preemption. + However a12-13 were already saved by _frxt_int_enter(). + */ + #ifdef __XTENSA_CALL0_ABI__ + s32i a14, a1, XT_STK_A14 + s32i a15, a1, XT_STK_A15 + #endif + + #ifdef __XTENSA_CALL0_ABI__ + call0 vPortYieldFromInt /* call dispatch inside the function; never returns */ + #else + call4 vPortYieldFromInt /* this one returns */ + call0 _frxt_dispatch /* tail-call dispatcher */ + /* Never returns here. */ + #endif + +.Lnoswitch: + /* + If we came here then about to resume the interrupted task. + */ + +.Lnesting: + /* + We come here only if there was no context switch, that is if this + is a nested interrupt, or the interrupted task was not preempted. + In either case there's no need to load the SP. + */ + + /* Restore full context from interrupt stack frame */ + call0 _xt_context_restore + + /* + Must return via the exit dispatcher corresponding to the entrypoint from which + this was called. Interruptee's A0, A1, PS, PC are restored and the interrupt + stack frame is deallocated in the exit dispatcher. + */ + l32i a0, a1, XT_STK_EXIT + ret + + +/* +********************************************************************************************************** +* _frxt_timer_int +* void _frxt_timer_int(void) +* +* Implements the Xtensa RTOS porting layer's XT_RTOS_TIMER_INT function for FreeRTOS. +* Called every timer interrupt. +* Manages the tick timer and calls xPortSysTickHandler() every tick. +* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h. +* +* Callable from C (obeys ABI conventions). Implemented in assmebly code for performance. +* +********************************************************************************************************** +*/ +#ifdef CONFIG_FREERTOS_SYSTICK_USES_CCOUNT + .globl _frxt_timer_int + .type _frxt_timer_int,@function + .align 4 +_frxt_timer_int: + + /* + Xtensa timers work by comparing a cycle counter with a preset value. Once the match occurs + an interrupt is generated, and the handler has to set a new cycle count into the comparator. + To avoid clock drift due to interrupt latency, the new cycle count is computed from the old, + not the time the interrupt was serviced. However if a timer interrupt is ever serviced more + than one tick late, it is necessary to process multiple ticks until the new cycle count is + in the future, otherwise the next timer interrupt would not occur until after the cycle + counter had wrapped (2^32 cycles later). + + do { + ticks++; + old_ccompare = read_ccompare_i(); + write_ccompare_i( old_ccompare + divisor ); + service one tick; + diff = read_ccount() - old_ccompare; + } while ( diff > divisor ); + */ + + ENTRY(16) + + #ifdef CONFIG_PM_TRACE + movi a6, 1 /* = ESP_PM_TRACE_TICK */ + getcoreid a7 + call4 esp_pm_trace_enter + #endif // CONFIG_PM_TRACE + +.L_xt_timer_int_catchup: + + /* Update the timer comparator for the next tick. */ + #ifdef XT_CLOCK_FREQ + movi a2, XT_TICK_DIVISOR /* a2 = comparator increment */ + #else + movi a3, _xt_tick_divisor + l32i a2, a3, 0 /* a2 = comparator increment */ + #endif + rsr a3, XT_CCOMPARE /* a3 = old comparator value */ + add a4, a3, a2 /* a4 = new comparator value */ + wsr a4, XT_CCOMPARE /* update comp. and clear interrupt */ + esync + + #ifdef __XTENSA_CALL0_ABI__ + /* Preserve a2 and a3 across C calls. */ + s32i a2, sp, 4 + s32i a3, sp, 8 + #endif + + /* Call the FreeRTOS tick handler (see port_systick.c). */ + #ifdef __XTENSA_CALL0_ABI__ + call0 xPortSysTickHandler + #else + call4 xPortSysTickHandler + #endif + + #ifdef __XTENSA_CALL0_ABI__ + /* Restore a2 and a3. */ + l32i a2, sp, 4 + l32i a3, sp, 8 + #endif + + /* Check if we need to process more ticks to catch up. */ + esync /* ensure comparator update complete */ + rsr a4, CCOUNT /* a4 = cycle count */ + sub a4, a4, a3 /* diff = ccount - old comparator */ + blt a2, a4, .L_xt_timer_int_catchup /* repeat while diff > divisor */ + +#ifdef CONFIG_PM_TRACE + movi a6, 1 /* = ESP_PM_TRACE_TICK */ + getcoreid a7 + call4 esp_pm_trace_exit +#endif // CONFIG_PM_TRACE + + RET(16) +#endif // CONFIG_FREERTOS_SYSTICK_USES_CCOUNT + + /* +********************************************************************************************************** +* _frxt_tick_timer_init +* void _frxt_tick_timer_init(void) +* +* Initialize timer and timer interrrupt handler (_xt_tick_divisor_init() has already been been called). +* Callable from C (obeys ABI conventions on entry). +* +********************************************************************************************************** +*/ +#ifdef CONFIG_FREERTOS_SYSTICK_USES_CCOUNT + .globl _frxt_tick_timer_init + .type _frxt_tick_timer_init,@function + .align 4 +_frxt_tick_timer_init: + + ENTRY(16) + + + /* Set up the periodic tick timer (assume enough time to complete init). */ + #ifdef XT_CLOCK_FREQ + movi a3, XT_TICK_DIVISOR + #else + movi a2, _xt_tick_divisor + l32i a3, a2, 0 + #endif + rsr a2, CCOUNT /* current cycle count */ + add a2, a2, a3 /* time of first timer interrupt */ + wsr a2, XT_CCOMPARE /* set the comparator */ + + /* + Enable the timer interrupt at the device level. Don't write directly + to the INTENABLE register because it may be virtualized. + */ + #ifdef __XTENSA_CALL0_ABI__ + movi a2, XT_TIMER_INTEN + call0 xt_ints_on + #else + movi a6, XT_TIMER_INTEN + call4 xt_ints_on + #endif + + RET(16) +#endif // CONFIG_FREERTOS_SYSTICK_USES_CCOUNT + +/* +********************************************************************************************************** +* DISPATCH THE HIGH READY TASK +* void _frxt_dispatch(void) +* +* Switch context to the highest priority ready task, restore its state and dispatch control to it. +* +* This is a common dispatcher that acts as a shared exit path for all the context switch functions +* including vPortYield() and vPortYieldFromInt(), all of which tail-call this dispatcher +* (for windowed ABI vPortYieldFromInt() calls it indirectly via _frxt_int_exit() ). +* +* The Xtensa port uses different stack frames for solicited and unsolicited task suspension (see +* comments on stack frames in xtensa_context.h). This function restores the state accordingly. +* If restoring a task that solicited entry, restores the minimal state and leaves CPENABLE clear. +* If restoring a task that was preempted, restores all state including the task's CPENABLE. +* +* Entry: +* pxCurrentTCB points to the TCB of the task to suspend, +* Because it is tail-called without a true function entrypoint, it needs no 'entry' instruction. +* +* Exit: +* If incoming task called vPortYield() (solicited), this function returns as if from vPortYield(). +* If incoming task was preempted by an interrupt, this function jumps to exit dispatcher. +* +********************************************************************************************************** +*/ + .globl _frxt_dispatch + .type _frxt_dispatch,@function + .align 4 +_frxt_dispatch: + + #ifdef __XTENSA_CALL0_ABI__ + call0 vTaskSwitchContext // Get next TCB to resume + movi a2, pxCurrentTCB + getcoreid a3 + addx4 a2, a3, a2 + #else + call4 vTaskSwitchContext // Get next TCB to resume + movi a2, pxCurrentTCB + getcoreid a3 + addx4 a2, a3, a2 + #endif + l32i a3, a2, 0 + l32i sp, a3, TOPOFSTACK_OFFS /* SP = next_TCB->pxTopOfStack; */ + s32i a3, a2, 0 + + /* Determine the type of stack frame. */ + l32i a2, sp, XT_STK_EXIT /* exit dispatcher or solicited flag */ + bnez a2, .L_frxt_dispatch_stk + +.L_frxt_dispatch_sol: + + /* Solicited stack frame. Restore minimal context and return from vPortYield(). */ + #if XCHAL_HAVE_THREADPTR + l32i a2, sp, XT_SOL_THREADPTR + wur.threadptr a2 + #endif + l32i a3, sp, XT_SOL_PS + #ifdef __XTENSA_CALL0_ABI__ + l32i a12, sp, XT_SOL_A12 + l32i a13, sp, XT_SOL_A13 + l32i a14, sp, XT_SOL_A14 + l32i a15, sp, XT_SOL_A15 + #endif + l32i a0, sp, XT_SOL_PC + #if XCHAL_CP_NUM > 0 + /* Ensure wsr.CPENABLE is complete (should be, it was cleared on entry). */ + rsync + #endif + /* As soons as PS is restored, interrupts can happen. No need to sync PS. */ + wsr a3, PS + #ifdef __XTENSA_CALL0_ABI__ + addi sp, sp, XT_SOL_FRMSZ + ret + #else + retw + #endif + +.L_frxt_dispatch_stk: + + #if XCHAL_CP_NUM > 0 + /* Restore CPENABLE from task's co-processor save area. */ + movi a3, pxCurrentTCB /* cp_state = */ + getcoreid a2 + addx4 a3, a2, a3 + l32i a3, a3, 0 + l32i a2, a3, CP_TOPOFSTACK_OFFS /* StackType_t *pxStack; */ + l16ui a3, a2, XT_CPENABLE /* CPENABLE = cp_state->cpenable; */ + wsr a3, CPENABLE + #endif + + /* Interrupt stack frame. Restore full context and return to exit dispatcher. */ + call0 _xt_context_restore + + /* In Call0 ABI, restore callee-saved regs (A12, A13 already restored). */ + #ifdef __XTENSA_CALL0_ABI__ + l32i a14, sp, XT_STK_A14 + l32i a15, sp, XT_STK_A15 + #endif + + #if XCHAL_CP_NUM > 0 + /* Ensure wsr.CPENABLE has completed. */ + rsync + #endif + + /* + Must return via the exit dispatcher corresponding to the entrypoint from which + this was called. Interruptee's A0, A1, PS, PC are restored and the interrupt + stack frame is deallocated in the exit dispatcher. + */ + l32i a0, sp, XT_STK_EXIT + ret + + +/* +********************************************************************************************************** +* PERFORM A SOLICTED CONTEXT SWITCH (from a task) +* void vPortYield(void) +* +* This function saves the minimal state needed for a solicited task suspension, clears CPENABLE, +* then tail-calls the dispatcher _frxt_dispatch() to perform the actual context switch +* +* At Entry: +* pxCurrentTCB points to the TCB of the task to suspend +* Callable from C (obeys ABI conventions on entry). +* +* Does not return to caller. +* +********************************************************************************************************** +*/ + .globl vPortYield + .type vPortYield,@function + .align 4 +vPortYield: + + #ifdef __XTENSA_CALL0_ABI__ + addi sp, sp, -XT_SOL_FRMSZ + #else + entry sp, XT_SOL_FRMSZ + #endif + + rsr a2, PS + s32i a0, sp, XT_SOL_PC + s32i a2, sp, XT_SOL_PS + #if XCHAL_HAVE_THREADPTR + rur.threadptr a2 + s32i a2, sp, XT_SOL_THREADPTR + #endif + #ifdef __XTENSA_CALL0_ABI__ + s32i a12, sp, XT_SOL_A12 /* save callee-saved registers */ + s32i a13, sp, XT_SOL_A13 + s32i a14, sp, XT_SOL_A14 + s32i a15, sp, XT_SOL_A15 + #else + /* Spill register windows. Calling xthal_window_spill() causes extra */ + /* spills and reloads, so we will set things up to call the _nw version */ + /* instead to save cycles. */ + movi a6, ~(PS_WOE_MASK|PS_INTLEVEL_MASK) /* spills a4-a7 if needed */ + and a2, a2, a6 /* clear WOE, INTLEVEL */ + addi a2, a2, XCHAL_EXCM_LEVEL /* set INTLEVEL */ + wsr a2, PS + rsync + call0 xthal_window_spill_nw + l32i a2, sp, XT_SOL_PS /* restore PS */ + wsr a2, PS + #endif + + rsil a2, XCHAL_EXCM_LEVEL /* disable low/med interrupts */ + + #if XCHAL_CP_NUM > 0 + /* Save coprocessor callee-saved state (if any). At this point CPENABLE */ + /* should still reflect which CPs were in use (enabled). */ + call0 _xt_coproc_savecs + #endif + + movi a2, pxCurrentTCB + getcoreid a3 + addx4 a2, a3, a2 + l32i a2, a2, 0 /* a2 = pxCurrentTCB */ + movi a3, 0 + s32i a3, sp, XT_SOL_EXIT /* 0 to flag as solicited frame */ + s32i sp, a2, TOPOFSTACK_OFFS /* pxCurrentTCB->pxTopOfStack = SP */ + + #if XCHAL_CP_NUM > 0 + /* Clear CPENABLE, also in task's co-processor state save area. */ + l32i a2, a2, CP_TOPOFSTACK_OFFS /* a2 = pxCurrentTCB->cp_state */ + movi a3, 0 + wsr a3, CPENABLE + beqz a2, 1f + s16i a3, a2, XT_CPENABLE /* clear saved cpenable */ +1: + #endif + + /* Tail-call dispatcher. */ + call0 _frxt_dispatch + /* Never reaches here. */ + + +/* +********************************************************************************************************** +* PERFORM AN UNSOLICITED CONTEXT SWITCH (from an interrupt) +* void vPortYieldFromInt(void) +* +* This calls the context switch hook (removed), saves and clears CPENABLE, then tail-calls the dispatcher +* _frxt_dispatch() to perform the actual context switch. +* +* At Entry: +* Interrupted task context has been saved in an interrupt stack frame at pxCurrentTCB->pxTopOfStack. +* pxCurrentTCB points to the TCB of the task to suspend, +* Callable from C (obeys ABI conventions on entry). +* +* At Exit: +* Windowed ABI defers the actual context switch until the stack is unwound to interrupt entry. +* Call0 ABI tail-calls the dispatcher directly (no need to unwind) so does not return to caller. +* +********************************************************************************************************** +*/ + .globl vPortYieldFromInt + .type vPortYieldFromInt,@function + .align 4 +vPortYieldFromInt: + + ENTRY(16) + + #if XCHAL_CP_NUM > 0 + /* Save CPENABLE in task's co-processor save area, and clear CPENABLE. */ + movi a3, pxCurrentTCB /* cp_state = */ + getcoreid a2 + addx4 a3, a2, a3 + l32i a3, a3, 0 + + l32i a2, a3, CP_TOPOFSTACK_OFFS + + rsr a3, CPENABLE + s16i a3, a2, XT_CPENABLE /* cp_state->cpenable = CPENABLE; */ + movi a3, 0 + wsr a3, CPENABLE /* disable all co-processors */ + #endif + + #ifdef __XTENSA_CALL0_ABI__ + /* Tail-call dispatcher. */ + call0 _frxt_dispatch + /* Never reaches here. */ + #else + RET(16) + #endif + +/* +********************************************************************************************************** +* _frxt_task_coproc_state +* void _frxt_task_coproc_state(void) +* +* Implements the Xtensa RTOS porting layer's XT_RTOS_CP_STATE function for FreeRTOS. +* +* May only be called when a task is running, not within an interrupt handler (returns 0 in that case). +* May only be called from assembly code by the 'call0' instruction. Does NOT obey ABI conventions. +* Returns in A15 a pointer to the base of the co-processor state save area for the current task. +* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h. +* +********************************************************************************************************** +*/ +#if XCHAL_CP_NUM > 0 + + .globl _frxt_task_coproc_state + .type _frxt_task_coproc_state,@function + .align 4 +_frxt_task_coproc_state: + + + /* We can use a3 as a scratchpad, the instances of code calling XT_RTOS_CP_STATE don't seem to need it saved. */ + getcoreid a3 + movi a15, port_xSchedulerRunning /* if (port_xSchedulerRunning */ + addx4 a15, a3,a15 + l32i a15, a15, 0 + beqz a15, 1f + movi a15, port_interruptNesting /* && port_interruptNesting == 0 */ + addx4 a15, a3, a15 + l32i a15, a15, 0 + bnez a15, 1f + + movi a15, pxCurrentTCB + addx4 a15, a3, a15 + l32i a15, a15, 0 /* && pxCurrentTCB != 0) { */ + + beqz a15, 2f + l32i a15, a15, CP_TOPOFSTACK_OFFS + ret + +1: movi a15, 0 +2: ret + +#endif /* XCHAL_CP_NUM > 0 */ diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/portmux_impl.h b/portable/ThirdParty/GCC/Xtensa_ESP32/portmux_impl.h new file mode 100644 index 000000000..b9a4fa508 --- /dev/null +++ b/portable/ThirdParty/GCC/Xtensa_ESP32/portmux_impl.h @@ -0,0 +1,100 @@ +/* + * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* This header exists for performance reasons, in order to inline the + * implementation of vPortCPUAcquireMutexIntsDisabled and + * vPortCPUReleaseMutexIntsDisabled into the + * vTaskEnterCritical/vTaskExitCritical functions in task.c as well as the + * vPortCPUAcquireMutex/vPortCPUReleaseMutex implementations. + * + * Normally this kind of performance hack is over the top, but + * vTaskEnterCritical/vTaskExitCritical is called a great + * deal by FreeRTOS internals. + * + * It should be #included by freertos port.c or tasks.c, in esp-idf. + * + * The way it works is that it essentially uses portmux_impl.inc.h as a + * generator template of sorts. When no external memory is used, this + * template is only used to generate the vPortCPUAcquireMutexIntsDisabledInternal + * and vPortCPUReleaseMutexIntsDisabledInternal functions, which use S32C1 to + * do an atomic compare & swap. When external memory is used the functions + * vPortCPUAcquireMutexIntsDisabledExtram and vPortCPUReleaseMutexIntsDisabledExtram + * are also generated, which use uxPortCompareSetExtram to fake the S32C1 instruction. + * The wrapper functions vPortCPUAcquireMutexIntsDisabled and + * vPortCPUReleaseMutexIntsDisabled will then use the appropriate function to do the + * actual lock/unlock. + */ +#include "soc/cpu.h" +#include "portable.h" + +/* XOR one core ID with this value to get the other core ID */ +#if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) ) + #define CORE_ID_XOR_SWAP ( CORE_ID_PRO ^ CORE_ID_APP ) +#else + #define CORE_ID_REGVAL_XOR_SWAP ( CORE_ID_REGVAL_PRO ^ CORE_ID_REGVAL_APP ) +#endif + + + +/*Define the mux routines for use with muxes in internal RAM */ +#define PORTMUX_AQUIRE_MUX_FN_NAME vPortCPUAcquireMutexIntsDisabledInternal +#define PORTMUX_RELEASE_MUX_FN_NAME vPortCPUReleaseMutexIntsDisabledInternal +#define PORTMUX_COMPARE_SET_FN_NAME uxPortCompareSet +#include "portmux_impl.inc.h" +#undef PORTMUX_AQUIRE_MUX_FN_NAME +#undef PORTMUX_RELEASE_MUX_FN_NAME +#undef PORTMUX_COMPARE_SET_FN_NAME + + +#if defined( CONFIG_SPIRAM_SUPPORT ) + + #define PORTMUX_AQUIRE_MUX_FN_NAME vPortCPUAcquireMutexIntsDisabledExtram + #define PORTMUX_RELEASE_MUX_FN_NAME vPortCPUReleaseMutexIntsDisabledExtram + #define PORTMUX_COMPARE_SET_FN_NAME uxPortCompareSetExtram + #include "portmux_impl.inc.h" + #undef PORTMUX_AQUIRE_MUX_FN_NAME + #undef PORTMUX_RELEASE_MUX_FN_NAME + #undef PORTMUX_COMPARE_SET_FN_NAME + +#endif + + +#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG + #define PORTMUX_AQUIRE_MUX_FN_ARGS portMUX_TYPE * mux, int timeout_cycles, const char * fnName, int line + #define PORTMUX_RELEASE_MUX_FN_ARGS portMUX_TYPE * mux, const char * fnName, int line + #define PORTMUX_AQUIRE_MUX_FN_CALL_ARGS( x ) x, timeout_cycles, fnName, line + #define PORTMUX_RELEASE_MUX_FN_CALL_ARGS( x ) x, fnName, line +#else + #define PORTMUX_AQUIRE_MUX_FN_ARGS portMUX_TYPE * mux, int timeout_cycles + #define PORTMUX_RELEASE_MUX_FN_ARGS portMUX_TYPE * mux + #define PORTMUX_AQUIRE_MUX_FN_CALL_ARGS( x ) x, timeout_cycles + #define PORTMUX_RELEASE_MUX_FN_CALL_ARGS( x ) x +#endif + + +static inline bool __attribute__( ( always_inline ) ) vPortCPUAcquireMutexIntsDisabled( PORTMUX_AQUIRE_MUX_FN_ARGS ) +{ + #if defined( CONFIG_SPIRAM_SUPPORT ) + if( esp_ptr_external_ram( mux ) ) + { + return vPortCPUAcquireMutexIntsDisabledExtram( PORTMUX_AQUIRE_MUX_FN_CALL_ARGS( mux ) ); + } + #endif + return vPortCPUAcquireMutexIntsDisabledInternal( PORTMUX_AQUIRE_MUX_FN_CALL_ARGS( mux ) ); +} + + +static inline void vPortCPUReleaseMutexIntsDisabled( PORTMUX_RELEASE_MUX_FN_ARGS ) +{ + #if defined( CONFIG_SPIRAM_SUPPORT ) + if( esp_ptr_external_ram( mux ) ) + { + vPortCPUReleaseMutexIntsDisabledExtram( PORTMUX_RELEASE_MUX_FN_CALL_ARGS( mux ) ); + return; + } + #endif + vPortCPUReleaseMutexIntsDisabledInternal( PORTMUX_RELEASE_MUX_FN_CALL_ARGS( mux ) ); +} diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/portmux_impl.inc.h b/portable/ThirdParty/GCC/Xtensa_ESP32/portmux_impl.inc.h new file mode 100644 index 000000000..37ca2fd0b --- /dev/null +++ b/portable/ThirdParty/GCC/Xtensa_ESP32/portmux_impl.inc.h @@ -0,0 +1,195 @@ +/* + * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + + +/* + * Warning: funky preprocessor hackery ahead. Including these headers will generate two + * functions, which names are defined by the preprocessor macros + * PORTMUX_AQUIRE_MUX_FN_NAME and PORTMUX_RELEASE_MUX_FN_NAME. In order to do the compare + * and exchange function, they will use whatever PORTMUX_COMPARE_SET_FN_NAME resolves to. + * + * In some scenarios, this header is included *twice* in portmux_impl.h: one time + * for the 'normal' mux code which uses a compare&exchange routine, another time + * to generate code for a second set of these routines that use a second mux + * (in internal ram) to fake a compare&exchange on a variable in external memory. + */ + + + +static inline bool __attribute__( ( always_inline ) ) +#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG + PORTMUX_AQUIRE_MUX_FN_NAME( portMUX_TYPE * mux, + int timeout_cycles, + const char * fnName, + int line ) + { +#else + PORTMUX_AQUIRE_MUX_FN_NAME( portMUX_TYPE * mux, int timeout_cycles ) + { + #endif + + + #if !CONFIG_FREERTOS_UNICORE + uint32_t res; + portBASE_TYPE coreID, otherCoreID; + uint32_t ccount_start; + bool set_timeout = timeout_cycles > portMUX_NO_TIMEOUT; + #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG + if( !set_timeout ) + { + timeout_cycles = 10000; /* Always set a timeout in debug mode */ + set_timeout = true; + } + #endif + + if( set_timeout ) /* Timeout */ + { + RSR( CCOUNT, ccount_start ); + } + + #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG + uint32_t owner = mux->owner; + + #if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) ) + if( ( owner != portMUX_FREE_VAL ) && ( owner != CORE_ID_PRO ) && ( owner != CORE_ID_APP ) ) + #else + if( ( owner != portMUX_FREE_VAL ) && ( owner != CORE_ID_REGVAL_PRO ) && ( owner != CORE_ID_REGVAL_APP ) ) + #endif + { + ets_printf( "ERROR: vPortCPUAcquireMutex: mux %p is uninitialized (0x%X)! Called from %s line %d.\n", mux, owner, fnName, line ); + mux->owner = portMUX_FREE_VAL; + } + #endif /* ifdef CONFIG_FREERTOS_PORTMUX_DEBUG */ + + /* Spin until we own the core */ + + RSR( PRID, coreID ); + + /* Note: coreID is the full 32 bit core ID (CORE_ID_PRO/CORE_ID_APP), + * not the 0/1 value returned by xPortGetCoreID() + */ + #if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) ) + otherCoreID = CORE_ID_XOR_SWAP ^ coreID; + #else + otherCoreID = CORE_ID_REGVAL_XOR_SWAP ^ coreID; + #endif + + do + { + /* mux->owner should be one of portMUX_FREE_VAL, CORE_ID_PRO, + * CORE_ID_APP: + * + * - If portMUX_FREE_VAL, we want to atomically set to 'coreID'. + * - If "our" coreID, we can drop through immediately. + * - If "otherCoreID", we spin here. + */ + res = coreID; + PORTMUX_COMPARE_SET_FN_NAME( &mux->owner, portMUX_FREE_VAL, &res ); + + if( res != otherCoreID ) + { + break; /* mux->owner is "our" coreID */ + } + + if( set_timeout ) + { + uint32_t ccount_now; + RSR( CCOUNT, ccount_now ); + + if( ccount_now - ccount_start > ( unsigned ) timeout_cycles ) + { + #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG + ets_printf( "Timeout on mux! last non-recursive lock %s line %d, curr %s line %d\n", mux->lastLockedFn, mux->lastLockedLine, fnName, line ); + ets_printf( "Owner 0x%x count %d\n", mux->owner, mux->count ); + #endif + return false; + } + } + } while( 1 ); + + assert( res == coreID || res == portMUX_FREE_VAL ); /* any other value implies memory corruption or uninitialized mux */ + assert( ( res == portMUX_FREE_VAL ) == ( mux->count == 0 ) ); /* we're first to lock iff count is zero */ + assert( mux->count < 0xFF ); /* Bad count value implies memory corruption */ + + /* now we own it, we can increment the refcount */ + mux->count++; + + + #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG + if( res == portMUX_FREE_VAL ) /*initial lock */ + { + mux->lastLockedFn = fnName; + mux->lastLockedLine = line; + } + else + { + ets_printf( "Recursive lock: count=%d last non-recursive lock %s line %d, curr %s line %d\n", mux->count - 1, + mux->lastLockedFn, mux->lastLockedLine, fnName, line ); + } + #endif /* CONFIG_FREERTOS_PORTMUX_DEBUG */ + #endif /* CONFIG_FREERTOS_UNICORE */ + return true; + } + +#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG + static inline void PORTMUX_RELEASE_MUX_FN_NAME( portMUX_TYPE * mux, + const char * fnName, + int line ) + { +#else + static inline void PORTMUX_RELEASE_MUX_FN_NAME( portMUX_TYPE * mux ) + { + #endif + + + #if !CONFIG_FREERTOS_UNICORE + portBASE_TYPE coreID; + #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG + const char * lastLockedFn = mux->lastLockedFn; + int lastLockedLine = mux->lastLockedLine; + mux->lastLockedFn = fnName; + mux->lastLockedLine = line; + uint32_t owner = mux->owner; + + #if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) ) + if( ( owner != portMUX_FREE_VAL ) && ( owner != CORE_ID_PRO ) && ( owner != CORE_ID_APP ) ) + #else + if( ( owner != portMUX_FREE_VAL ) && ( owner != CORE_ID_REGVAL_PRO ) && ( owner != CORE_ID_REGVAL_APP ) ) + #endif + { + ets_printf( "ERROR: vPortCPUReleaseMutex: mux %p is invalid (0x%x)!\n", mux, mux->owner ); + } + #endif /* ifdef CONFIG_FREERTOS_PORTMUX_DEBUG */ + + #if CONFIG_FREERTOS_PORTMUX_DEBUG || !defined( NDEBUG ) + RSR( PRID, coreID ); + #endif + + #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG + if( coreID != mux->owner ) + { + ets_printf( "ERROR: vPortCPUReleaseMutex: mux %p was already unlocked!\n", mux ); + ets_printf( "Last non-recursive unlock %s line %d, curr unlock %s line %d\n", lastLockedFn, lastLockedLine, fnName, line ); + } + #endif + + assert( coreID == mux->owner ); /* This is a mutex we didn't lock, or it's corrupt */ + + mux->count--; + + if( mux->count == 0 ) + { + mux->owner = portMUX_FREE_VAL; + } + else + { + assert( mux->count < 0x100 ); /* Indicates memory corruption */ + #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG_RECURSIVE + ets_printf( "Recursive unlock: count=%d last locked %s line %d, curr %s line %d\n", mux->count, lastLockedFn, lastLockedLine, fnName, line ); + #endif + } + #endif //!CONFIG_FREERTOS_UNICORE + } diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_context.S b/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_context.S new file mode 100644 index 000000000..976d0fefc --- /dev/null +++ b/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_context.S @@ -0,0 +1,710 @@ +/* + * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc. + * + * SPDX-License-Identifier: MIT + * + * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD + */ +/* + * Copyright (c) 2015-2019 Cadence Design Systems, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/******************************************************************************* + + XTENSA CONTEXT SAVE AND RESTORE ROUTINES + +Low-level Call0 functions for handling generic context save and restore of +registers not specifically addressed by the interrupt vectors and handlers. +Those registers (not handled by these functions) are PC, PS, A0, A1 (SP). +Except for the calls to RTOS functions, this code is generic to Xtensa. + +Note that in Call0 ABI, interrupt handlers are expected to preserve the callee- +save regs (A12-A15), which is always the case if the handlers are coded in C. +However A12, A13 are made available as scratch registers for interrupt dispatch +code, so are presumed saved anyway, and are always restored even in Call0 ABI. +Only A14, A15 are truly handled as callee-save regs. + +Because Xtensa is a configurable architecture, this port supports all user +generated configurations (except restrictions stated in the release notes). +This is accomplished by conditional compilation using macros and functions +defined in the Xtensa HAL (hardware adaptation layer) for your configuration. +Only the processor state included in your configuration is saved and restored, +including any processor state added by user configuration options or TIE. + +*******************************************************************************/ + +/* Warn nicely if this file gets named with a lowercase .s instead of .S: */ +#define NOERROR # +NOERROR: .error "C preprocessor needed for this file: make sure its filename\ + ends in uppercase .S, or use xt-xcc's -x assembler-with-cpp option." + + +#include "xtensa_rtos.h" +#include "xtensa_context.h" +#include "esp_idf_version.h" +#if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) +#include "xt_asm_utils.h" +#endif + +#ifdef XT_USE_OVLY +#include +#endif + + .text + +/******************************************************************************* + +_xt_context_save + + !! MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION !! + +Saves all Xtensa processor state except PC, PS, A0, A1 (SP), A12, A13, in the +interrupt stack frame defined in xtensa_rtos.h. +Its counterpart is _xt_context_restore (which also restores A12, A13). + +Caller is expected to have saved PC, PS, A0, A1 (SP), A12, A13 in the frame. +This function preserves A12 & A13 in order to provide the caller with 2 scratch +regs that need not be saved over the call to this function. The choice of which +2 regs to provide is governed by xthal_window_spill_nw and xthal_save_extra_nw, +to avoid moving data more than necessary. Caller can assign regs accordingly. + +Entry Conditions: + A0 = Return address in caller. + A1 = Stack pointer of interrupted thread or handler ("interruptee"). + Original A12, A13 have already been saved in the interrupt stack frame. + Other processor state except PC, PS, A0, A1 (SP), A12, A13, is as at the + point of interruption. + If windowed ABI, PS.EXCM = 1 (exceptions disabled). + +Exit conditions: + A0 = Return address in caller. + A1 = Stack pointer of interrupted thread or handler ("interruptee"). + A12, A13 as at entry (preserved). + If windowed ABI, PS.EXCM = 1 (exceptions disabled). + +*******************************************************************************/ + + .global _xt_context_save + .type _xt_context_save,@function + .align 4 + .literal_position + .align 4 + +_xt_context_save: + + s32i a2, sp, XT_STK_A2 + s32i a3, sp, XT_STK_A3 + s32i a4, sp, XT_STK_A4 + s32i a5, sp, XT_STK_A5 + s32i a6, sp, XT_STK_A6 + s32i a7, sp, XT_STK_A7 + s32i a8, sp, XT_STK_A8 + s32i a9, sp, XT_STK_A9 + s32i a10, sp, XT_STK_A10 + s32i a11, sp, XT_STK_A11 + + /* + Call0 ABI callee-saved regs a12-15 do not need to be saved here. + a12-13 are the caller's responsibility so it can use them as scratch. + So only need to save a14-a15 here for Windowed ABI (not Call0). + */ + #ifndef __XTENSA_CALL0_ABI__ + s32i a14, sp, XT_STK_A14 + s32i a15, sp, XT_STK_A15 + #endif + + rsr a3, SAR + s32i a3, sp, XT_STK_SAR + + #if XCHAL_HAVE_LOOPS + rsr a3, LBEG + s32i a3, sp, XT_STK_LBEG + rsr a3, LEND + s32i a3, sp, XT_STK_LEND + rsr a3, LCOUNT + s32i a3, sp, XT_STK_LCOUNT + #endif + + #ifdef XT_USE_SWPRI + /* Save virtual priority mask */ + movi a3, _xt_vpri_mask + l32i a3, a3, 0 + s32i a3, sp, XT_STK_VPRI + #endif + + #if XCHAL_EXTRA_SA_SIZE > 0 || !defined(__XTENSA_CALL0_ABI__) + mov a9, a0 /* preserve ret addr */ + #endif + + #if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0)) + #ifndef __XTENSA_CALL0_ABI__ + /* + To spill the reg windows, temp. need pre-interrupt stack ptr and a4-15. + Need to save a9,12,13 temporarily (in frame temps) and recover originals. + Interrupts need to be disabled below XCHAL_EXCM_LEVEL and window overflow + and underflow exceptions disabled (assured by PS.EXCM == 1). + */ + s32i a12, sp, XT_STK_TMP0 /* temp. save stuff in stack frame */ + s32i a13, sp, XT_STK_TMP1 + s32i a9, sp, XT_STK_TMP2 + + /* + Save the overlay state if we are supporting overlays. Since we just saved + three registers, we can conveniently use them here. Note that as of now, + overlays only work for windowed calling ABI. + */ + #ifdef XT_USE_OVLY + l32i a9, sp, XT_STK_PC /* recover saved PC */ + _xt_overlay_get_state a9, a12, a13 + s32i a9, sp, XT_STK_OVLY /* save overlay state */ + #endif + + l32i a12, sp, XT_STK_A12 /* recover original a9,12,13 */ + l32i a13, sp, XT_STK_A13 + l32i a9, sp, XT_STK_A9 + addi sp, sp, XT_STK_FRMSZ /* restore the interruptee's SP */ + call0 xthal_window_spill_nw /* preserves only a4,5,8,9,12,13 */ + addi sp, sp, -XT_STK_FRMSZ + l32i a12, sp, XT_STK_TMP0 /* recover stuff from stack frame */ + l32i a13, sp, XT_STK_TMP1 + l32i a9, sp, XT_STK_TMP2 + #endif + #endif /* (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0)) */ + + #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) + s32i a12, sp, XT_STK_TMP0 /* temp. save stuff in stack frame */ + s32i a13, sp, XT_STK_TMP1 + s32i a9, sp, XT_STK_TMP2 + + l32i a12, sp, XT_STK_A12 /* recover original a9,12,13 */ + l32i a13, sp, XT_STK_A13 + l32i a9, sp, XT_STK_A9 + #endif + + #if XCHAL_EXTRA_SA_SIZE > 0 + addi a2, sp, XT_STK_EXTRA /* where to save it */ + # if XCHAL_EXTRA_SA_ALIGN > 16 + movi a3, -XCHAL_EXTRA_SA_ALIGN + and a2, a2, a3 /* align dynamically >16 bytes */ + # endif + call0 xthal_save_extra_nw /* destroys a0,2,3 */ + #endif + + #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) + #ifndef __XTENSA_CALL0_ABI__ + #ifdef XT_USE_OVLY + l32i a9, sp, XT_STK_PC /* recover saved PC */ + _xt_overlay_get_state a9, a12, a13 + s32i a9, sp, XT_STK_OVLY /* save overlay state */ + #endif + + /* SPILL_ALL_WINDOWS macro requires window overflow exceptions to be enabled, + * i.e. PS.EXCM cleared and PS.WOE set. + * Since we are going to clear PS.EXCM, we also need to increase INTLEVEL + * at least to XCHAL_EXCM_LEVEL. This matches that value of effective INTLEVEL + * at entry (CINTLEVEL=max(PS.INTLEVEL, XCHAL_EXCM_LEVEL) when PS.EXCM is set. + * Since WindowOverflow exceptions will trigger inside SPILL_ALL_WINDOWS, + * need to save/restore EPC1 as well. + * Note: even though a4-a15 are saved into the exception frame, we should not + * clobber them until after SPILL_ALL_WINDOWS. This is because these registers + * may contain live windows belonging to previous frames in the call stack. + * These frames will be spilled by SPILL_ALL_WINDOWS, and if the register was + * used as a temporary by this code, the temporary value would get stored + * onto the stack, instead of the real value. + */ + rsr a2, PS /* to be restored after SPILL_ALL_WINDOWS */ + movi a0, PS_INTLEVEL_MASK + and a3, a2, a0 /* get the current INTLEVEL */ + bgeui a3, XCHAL_EXCM_LEVEL, 1f /* calculate max(INTLEVEL, XCHAL_EXCM_LEVEL) */ + movi a3, XCHAL_EXCM_LEVEL +1: + movi a0, PS_UM | PS_WOE /* clear EXCM, enable window overflow, set new INTLEVEL */ + or a3, a3, a0 + wsr a3, ps + rsr a0, EPC1 /* to be restored after SPILL_ALL_WINDOWS */ + + addi sp, sp, XT_STK_FRMSZ /* restore the interruptee's SP */ + SPILL_ALL_WINDOWS + addi sp, sp, -XT_STK_FRMSZ /* return the current stack pointer and proceed with context save*/ + + + wsr a2, PS /* restore to the value at entry */ + rsync + wsr a0, EPC1 /* likewise */ + + #endif /* __XTENSA_CALL0_ABI__ */ + + l32i a12, sp, XT_STK_TMP0 /* restore the temp saved registers */ + l32i a13, sp, XT_STK_TMP1 /* our return address is there */ + l32i a9, sp, XT_STK_TMP2 + #endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */ + + #if XCHAL_EXTRA_SA_SIZE > 0 || !defined(__XTENSA_CALL0_ABI__) + mov a0, a9 /* retrieve ret addr */ + #endif + + ret + +/******************************************************************************* + +_xt_context_restore + + !! MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION !! + +Restores all Xtensa processor state except PC, PS, A0, A1 (SP) (and in Call0 +ABI, A14, A15 which are preserved by all interrupt handlers) from an interrupt +stack frame defined in xtensa_rtos.h . +Its counterpart is _xt_context_save (whose caller saved A12, A13). + +Caller is responsible to restore PC, PS, A0, A1 (SP). + +Entry Conditions: + A0 = Return address in caller. + A1 = Stack pointer of interrupted thread or handler ("interruptee"). + +Exit conditions: + A0 = Return address in caller. + A1 = Stack pointer of interrupted thread or handler ("interruptee"). + Other processor state except PC, PS, A0, A1 (SP), is as at the point + of interruption. + +*******************************************************************************/ + + .global _xt_context_restore + .type _xt_context_restore,@function + .align 4 + .literal_position + .align 4 +_xt_context_restore: + + #if XCHAL_EXTRA_SA_SIZE > 0 + /* + NOTE: Normally the xthal_restore_extra_nw macro only affects address + registers a2-a5. It is theoretically possible for Xtensa processor + designers to write TIE that causes more address registers to be + affected, but it is generally unlikely. If that ever happens, + more registers need to be saved/restored around this macro invocation. + Here we only assume a13 is preserved. + Future Xtensa tools releases might limit the regs that can be affected. + */ + mov a13, a0 /* preserve ret addr */ + addi a2, sp, XT_STK_EXTRA /* where to find it */ + # if XCHAL_EXTRA_SA_ALIGN > 16 + movi a3, -XCHAL_EXTRA_SA_ALIGN + and a2, a2, a3 /* align dynamically >16 bytes */ + # endif + call0 xthal_restore_extra_nw /* destroys a0,2,3,4,5 */ + mov a0, a13 /* retrieve ret addr */ + #endif + + #if XCHAL_HAVE_LOOPS + l32i a2, sp, XT_STK_LBEG + l32i a3, sp, XT_STK_LEND + wsr a2, LBEG + l32i a2, sp, XT_STK_LCOUNT + wsr a3, LEND + wsr a2, LCOUNT + #endif + + #ifdef XT_USE_OVLY + /* + If we are using overlays, this is a good spot to check if we need + to restore an overlay for the incoming task. Here we have a bunch + of registers to spare. Note that this step is going to use a few + bytes of storage below SP (SP-20 to SP-32) if an overlay is going + to be restored. + */ + l32i a2, sp, XT_STK_PC /* retrieve PC */ + l32i a3, sp, XT_STK_PS /* retrieve PS */ + l32i a4, sp, XT_STK_OVLY /* retrieve overlay state */ + l32i a5, sp, XT_STK_A1 /* retrieve stack ptr */ + _xt_overlay_check_map a2, a3, a4, a5, a6 + s32i a2, sp, XT_STK_PC /* save updated PC */ + s32i a3, sp, XT_STK_PS /* save updated PS */ + #endif + + #ifdef XT_USE_SWPRI + /* Restore virtual interrupt priority and interrupt enable */ + movi a3, _xt_intdata + l32i a4, a3, 0 /* a4 = _xt_intenable */ + l32i a5, sp, XT_STK_VPRI /* a5 = saved _xt_vpri_mask */ + and a4, a4, a5 + wsr a4, INTENABLE /* update INTENABLE */ + s32i a5, a3, 4 /* restore _xt_vpri_mask */ + #endif + + l32i a3, sp, XT_STK_SAR + l32i a2, sp, XT_STK_A2 + wsr a3, SAR + l32i a3, sp, XT_STK_A3 + l32i a4, sp, XT_STK_A4 + l32i a5, sp, XT_STK_A5 + l32i a6, sp, XT_STK_A6 + l32i a7, sp, XT_STK_A7 + l32i a8, sp, XT_STK_A8 + l32i a9, sp, XT_STK_A9 + l32i a10, sp, XT_STK_A10 + l32i a11, sp, XT_STK_A11 + + /* + Call0 ABI callee-saved regs a12-15 do not need to be restored here. + However a12-13 were saved for scratch before XT_RTOS_INT_ENTER(), + so need to be restored anyway, despite being callee-saved in Call0. + */ + l32i a12, sp, XT_STK_A12 + l32i a13, sp, XT_STK_A13 + #ifndef __XTENSA_CALL0_ABI__ + l32i a14, sp, XT_STK_A14 + l32i a15, sp, XT_STK_A15 + #endif + + ret + + +/******************************************************************************* + +_xt_coproc_init + +Initializes global co-processor management data, setting all co-processors +to "unowned". Leaves CPENABLE as it found it (does NOT clear it). + +Called during initialization of the RTOS, before any threads run. + +This may be called from normal Xtensa single-threaded application code which +might use co-processors. The Xtensa run-time initialization enables all +co-processors. They must remain enabled here, else a co-processor exception +might occur outside of a thread, which the exception handler doesn't expect. + +Entry Conditions: + Xtensa single-threaded run-time environment is in effect. + No thread is yet running. + +Exit conditions: + None. + +Obeys ABI conventions per prototype: + void _xt_coproc_init(void) + +*******************************************************************************/ + +#if XCHAL_CP_NUM > 0 + + .global _xt_coproc_init + .type _xt_coproc_init,@function + .align 4 + .literal_position + .align 4 +_xt_coproc_init: + ENTRY0 + + /* Initialize thread co-processor ownerships to 0 (unowned). */ + movi a2, _xt_coproc_owner_sa /* a2 = base of owner array */ + addi a3, a2, (XCHAL_CP_MAX*portNUM_PROCESSORS) << 2 /* a3 = top+1 of owner array */ + movi a4, 0 /* a4 = 0 (unowned) */ +1: s32i a4, a2, 0 + addi a2, a2, 4 + bltu a2, a3, 1b + + RET0 + +#endif + + +/******************************************************************************* + +_xt_coproc_release + +Releases any and all co-processors owned by a given thread. The thread is +identified by it's co-processor state save area defined in xtensa_context.h . + +Must be called before a thread's co-proc save area is deleted to avoid +memory corruption when the exception handler tries to save the state. +May be called when a thread terminates or completes but does not delete +the co-proc save area, to avoid the exception handler having to save the +thread's co-proc state before another thread can use it (optimization). + +Needs to be called on the processor the thread was running on. Unpinned threads +won't have an entry here because they get pinned as soon they use a coprocessor. + +Entry Conditions: + A2 = Pointer to base of co-processor state save area. + +Exit conditions: + None. + +Obeys ABI conventions per prototype: + void _xt_coproc_release(void * coproc_sa_base) + +*******************************************************************************/ + +#if XCHAL_CP_NUM > 0 + + .global _xt_coproc_release + .type _xt_coproc_release,@function + .align 4 + .literal_position + .align 4 +_xt_coproc_release: + ENTRY0 /* a2 = base of save area */ + + getcoreid a5 + movi a3, XCHAL_CP_MAX << 2 + mull a5, a5, a3 + movi a3, _xt_coproc_owner_sa /* a3 = base of owner array */ + add a3, a3, a5 + + addi a4, a3, XCHAL_CP_MAX << 2 /* a4 = top+1 of owner array */ + movi a5, 0 /* a5 = 0 (unowned) */ + + rsil a6, XCHAL_EXCM_LEVEL /* lock interrupts */ + +1: l32i a7, a3, 0 /* a7 = owner at a3 */ + bne a2, a7, 2f /* if (coproc_sa_base == owner) */ + s32i a5, a3, 0 /* owner = unowned */ +2: addi a3, a3, 1<<2 /* a3 = next entry in owner array */ + bltu a3, a4, 1b /* repeat until end of array */ + +3: wsr a6, PS /* restore interrupts */ + + RET0 + +#endif + + +/******************************************************************************* +_xt_coproc_savecs + +If there is a current thread and it has a coprocessor state save area, then +save all callee-saved state into this area. This function is called from the +solicited context switch handler. It calls a system-specific function to get +the coprocessor save area base address. + +Entry conditions: + - The thread being switched out is still the current thread. + - CPENABLE state reflects which coprocessors are active. + - Registers have been saved/spilled already. + +Exit conditions: + - All necessary CP callee-saved state has been saved. + - Registers a2-a7, a13-a15 have been trashed. + +Must be called from assembly code only, using CALL0. +*******************************************************************************/ +#if XCHAL_CP_NUM > 0 + + .extern _xt_coproc_sa_offset /* external reference */ + + .global _xt_coproc_savecs + .type _xt_coproc_savecs,@function + .align 4 + .literal_position + .align 4 +_xt_coproc_savecs: + + /* At entry, CPENABLE should be showing which CPs are enabled. */ + + rsr a2, CPENABLE /* a2 = which CPs are enabled */ + beqz a2, .Ldone /* quick exit if none */ + mov a14, a0 /* save return address */ + call0 XT_RTOS_CP_STATE /* get address of CP save area */ + mov a0, a14 /* restore return address */ + beqz a15, .Ldone /* if none then nothing to do */ + s16i a2, a15, XT_CP_CS_ST /* save mask of CPs being stored */ + movi a13, _xt_coproc_sa_offset /* array of CP save offsets */ + l32i a15, a15, XT_CP_ASA /* a15 = base of aligned save area */ + +#if XCHAL_CP0_SA_SIZE + bbci.l a2, 0, 2f /* CP 0 not enabled */ + l32i a14, a13, 0 /* a14 = _xt_coproc_sa_offset[0] */ + add a3, a14, a15 /* a3 = save area for CP 0 */ + xchal_cp0_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP1_SA_SIZE + bbci.l a2, 1, 2f /* CP 1 not enabled */ + l32i a14, a13, 4 /* a14 = _xt_coproc_sa_offset[1] */ + add a3, a14, a15 /* a3 = save area for CP 1 */ + xchal_cp1_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP2_SA_SIZE + bbci.l a2, 2, 2f + l32i a14, a13, 8 + add a3, a14, a15 + xchal_cp2_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP3_SA_SIZE + bbci.l a2, 3, 2f + l32i a14, a13, 12 + add a3, a14, a15 + xchal_cp3_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP4_SA_SIZE + bbci.l a2, 4, 2f + l32i a14, a13, 16 + add a3, a14, a15 + xchal_cp4_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP5_SA_SIZE + bbci.l a2, 5, 2f + l32i a14, a13, 20 + add a3, a14, a15 + xchal_cp5_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP6_SA_SIZE + bbci.l a2, 6, 2f + l32i a14, a13, 24 + add a3, a14, a15 + xchal_cp6_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP7_SA_SIZE + bbci.l a2, 7, 2f + l32i a14, a13, 28 + add a3, a14, a15 + xchal_cp7_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +.Ldone: + ret +#endif + + +/******************************************************************************* +_xt_coproc_restorecs + +Restore any callee-saved coprocessor state for the incoming thread. +This function is called from coprocessor exception handling, when giving +ownership to a thread that solicited a context switch earlier. It calls a +system-specific function to get the coprocessor save area base address. + +Entry conditions: + - The incoming thread is set as the current thread. + - CPENABLE is set up correctly for all required coprocessors. + - a2 = mask of coprocessors to be restored. + +Exit conditions: + - All necessary CP callee-saved state has been restored. + - CPENABLE - unchanged. + - Registers a2-a7, a13-a15 have been trashed. + +Must be called from assembly code only, using CALL0. +*******************************************************************************/ +#if XCHAL_CP_NUM > 0 + + .global _xt_coproc_restorecs + .type _xt_coproc_restorecs,@function + .align 4 + .literal_position + .align 4 +_xt_coproc_restorecs: + + mov a14, a0 /* save return address */ + call0 XT_RTOS_CP_STATE /* get address of CP save area */ + mov a0, a14 /* restore return address */ + beqz a15, .Ldone2 /* if none then nothing to do */ + l16ui a3, a15, XT_CP_CS_ST /* a3 = which CPs have been saved */ + xor a3, a3, a2 /* clear the ones being restored */ + s32i a3, a15, XT_CP_CS_ST /* update saved CP mask */ + movi a13, _xt_coproc_sa_offset /* array of CP save offsets */ + l32i a15, a15, XT_CP_ASA /* a15 = base of aligned save area */ + +#if XCHAL_CP0_SA_SIZE + bbci.l a2, 0, 2f /* CP 0 not enabled */ + l32i a14, a13, 0 /* a14 = _xt_coproc_sa_offset[0] */ + add a3, a14, a15 /* a3 = save area for CP 0 */ + xchal_cp0_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP1_SA_SIZE + bbci.l a2, 1, 2f /* CP 1 not enabled */ + l32i a14, a13, 4 /* a14 = _xt_coproc_sa_offset[1] */ + add a3, a14, a15 /* a3 = save area for CP 1 */ + xchal_cp1_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP2_SA_SIZE + bbci.l a2, 2, 2f + l32i a14, a13, 8 + add a3, a14, a15 + xchal_cp2_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP3_SA_SIZE + bbci.l a2, 3, 2f + l32i a14, a13, 12 + add a3, a14, a15 + xchal_cp3_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP4_SA_SIZE + bbci.l a2, 4, 2f + l32i a14, a13, 16 + add a3, a14, a15 + xchal_cp4_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP5_SA_SIZE + bbci.l a2, 5, 2f + l32i a14, a13, 20 + add a3, a14, a15 + xchal_cp5_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP6_SA_SIZE + bbci.l a2, 6, 2f + l32i a14, a13, 24 + add a3, a14, a15 + xchal_cp6_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP7_SA_SIZE + bbci.l a2, 7, 2f + l32i a14, a13, 28 + add a3, a14, a15 + xchal_cp7_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +.Ldone2: + ret + +#endif diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_init.c b/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_init.c new file mode 100644 index 000000000..fbdd95fc5 --- /dev/null +++ b/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_init.c @@ -0,0 +1,76 @@ +/* + * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc. + * + * SPDX-License-Identifier: MIT + * + * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD + */ + +/* + * Copyright (c) 2015-2019 Cadence Design Systems, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/******************************************************************************* +* +* XTENSA INITIALIZATION ROUTINES CODED IN C +* +* This file contains miscellaneous Xtensa RTOS-generic initialization functions +* that are implemented in C. +* +*******************************************************************************/ + + +#ifdef XT_BOARD + #include "xtensa/xtbsp.h" +#endif + +#include "xtensa_rtos.h" +#include "sdkconfig.h" +#include "esp_idf_version.h" +#if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) ) + #include "esp_clk.h" +#else + #if CONFIG_IDF_TARGET_ESP32 + #include "esp32/clk.h" + #elif CONFIG_IDF_TARGET_ESP32S2 + #include "esp32s2/clk.h" + #elif CONFIG_IDF_TARGET_ESP32S3 + #include "esp32s3/clk.h" + #endif +#endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0) */ + +#ifdef XT_RTOS_TIMER_INT + + unsigned _xt_tick_divisor = 0; /* cached number of cycles per tick */ + + void _xt_tick_divisor_init( void ) + { + _xt_tick_divisor = esp_clk_cpu_freq() / XT_TICK_PER_SEC; + } + +/* Deprecated, to be removed */ + int xt_clock_freq( void ) + { + return esp_clk_cpu_freq(); + } + +#endif /* XT_RTOS_TIMER_INT */ diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_loadstore_handler.S b/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_loadstore_handler.S new file mode 100644 index 000000000..4572eb684 --- /dev/null +++ b/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_loadstore_handler.S @@ -0,0 +1,549 @@ +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * LoadStoreErrorCause: Occurs when trying to access 32 bit addressable memory region as 8 bit or 16 bit + * LoadStoreAlignmentCause: Occurs when trying to access in an unaligned manner + * + * xxxx xxxx = imm8 field + * yyyy = imm4 field + * ssss = s field + * tttt = t field + * + * 16 0 + * ------------------- + * L32I.N yyyy ssss tttt 1000 + * S32I.N yyyy ssss tttt 1001 + * + * 23 0 + * ----------------------------- + * L8UI xxxx xxxx 0000 ssss tttt 0010 <- LoadStoreError + * L16UI xxxx xxxx 0001 ssss tttt 0010 <- LoadStoreError, LoadStoreAlignment + * L16SI xxxx xxxx 1001 ssss tttt 0010 <- LoadStoreError, LoadStoreAlignment + * L32I xxxx xxxx 0010 ssss tttt 0010 <- LoadStoreAlignment + * + * S8I xxxx xxxx 0100 ssss tttt 0010 <- LoadStoreError + * S16I xxxx xxxx 0101 ssss tttt 0010 <- LoadStoreError, LoadStoreAlignment + * S32I xxxx xxxx 0110 ssss tttt 0010 <- LoadStoreAlignment + * + * ******* UNSUPPORTED ******* + * + * L32E 0000 1001 rrrr ssss tttt 0000 + * S32E 0100 1001 rrrr ssss tttt 0000 + * ----------------------------- + */ + +#include "xtensa_rtos.h" +#include "sdkconfig.h" +#include "soc/soc.h" + +#define LOADSTORE_HANDLER_STACK_SZ 8 + .section .bss, "aw" + .balign 16 +LoadStoreHandlerStack: + .rept LOADSTORE_HANDLER_STACK_SZ + .word 0 + .endr + + +/* LoadStoreErrorCause handler: + * + * Completes 8-bit or 16-bit load/store instructions from 32-bit aligned memory region + * Called from UserExceptionVector if EXCCAUSE is LoadStoreErrorCause + */ + + .global LoadStoreErrorHandler + .section .iram1, "ax" + + .literal_position + + .balign 4 +LoadStoreErrorHandler: + .type LoadStoreErrorHandler, @function + + wsr a0, depc // Save return address in depc + mov a0, sp + movi sp, LoadStoreHandlerStack + s32i a0, sp, 0x04 // Since a0 contains value of a1 + s32i a2, sp, 0x08 + s32i a3, sp, 0x0c + s32i a4, sp, 0x10 + + rsr a0, sar // Save SAR in a0 to restore later + + /* Check whether the address lies in the valid range */ + rsr a3, excvaddr + movi a4, _iram_text_end // End of code section of IRAM + bge a3, a4, 1f + movi a4, SOC_CACHE_APP_LOW // Check if in APP cache region + blt a3, a4, .LS_wrong_opcode + movi a4, SOC_CACHE_APP_HIGH + bge a3, a4, .LS_wrong_opcode + j 2f + +1: + movi a4, SOC_IRAM_HIGH // End of IRAM address range + bge a3, a4, .LS_wrong_opcode + +2: + /* Examine the opcode which generated the exception */ + /* Note: Instructions are in this order to avoid pipeline stalls. */ + rsr a2, epc1 + movi a4, ~3 + ssa8l a2 // sar is now correct shift for aligned read + and a2, a2, a4 // a2 now 4-byte aligned address of instruction + l32i a4, a2, 0 + l32i a2, a2, 4 + + src a2, a2, a4 // a2 now instruction that failed + bbci a2, 1, .LS_wrong_opcode + bbsi a2, 14, .LSE_store_op // Store instruction + + /* l8/l16ui/l16si */ + movi a4, ~3 + and a4, a3, a4 // a4 now word aligned read address + + ssa8l a3 // sar is now shift to extract a3's byte + l32i a4, a4, 0 // perform the actual read + srl a4, a4 // shift right correct distance + extui a3, a2, 12, 4 + bnez a3, 1f // l16ui/l16si + extui a4, a4, 0, 8 // mask off bits needed for an l8 + j 2f + +1: + extui a4, a4, 0, 16 + bbci a2, 15, 2f // l16ui + + /* Sign adjustment */ + slli a4, a4, 16 + srai a4, a4, 16 // a4 contains the value + +2: + /* a4 contains the value */ + rsr a3, epc1 + addi a3, a3, 3 + wsr a3, epc1 + wsr a0, sar + rsr a0, excsave1 + + extui a2, a2, 3, 5 + blti a2, 10, .LSE_stack_reg + + movi a3, .LS_jumptable_base + addx8 a2, a2, a3 // a2 is now the address to jump to + l32i a3, sp, 0x0c + jx a2 + +.LSE_stack_reg: + addx2 a2, a2, sp + s32i a4, a2, 0 + + /* Restore all values */ + l32i a4, sp, 0x10 + l32i a3, sp, 0x0c + l32i a2, sp, 0x08 + l32i a1, sp, 0x04 + rfe + +.LSE_store_op: + s32i a5, a1, 0x14 + s32i a6, a1, 0x18 + + /* a2 -> instruction that caused the error */ + /* a3 -> unaligned address */ + extui a4, a2, 4, 4 + blti a4, 7, 1f + movi a5, .LSE_store_reg + addx8 a5, a4, a5 + jx a5 + +1: + addx4 a4, a4, sp + l32i a4, a4, 0 + +.LSE_store_data: + /* a4 contains the value */ + rsr a6, epc1 + addi a6, a6, 3 + wsr a6, epc1 + + ssa8b a3 + movi a5, -1 + bbsi a2, 12, 1f // s16 + extui a4, a4, 0, 8 + movi a6, 0xff + j 2f +1: + extui a4, a4, 0, 16 + movi a6, 0xffff +2: + sll a4, a4 // shift the value to proper offset + sll a6, a6 + xor a5, a5, a6 // a5 contains the mask + + movi a6, ~3 + and a3, a3, a6 // a3 has the aligned address + l32i a6, a3, 0 // a6 contains the data at the aligned address + and a6, a6, a5 + or a4, a6, a4 + s32i a4, a3, 0 + + /* Restore registers */ + wsr a0, sar + + l32i a6, sp, 0x18 + l32i a5, sp, 0x14 + l32i a4, sp, 0x10 + l32i a3, sp, 0x0c + l32i a2, sp, 0x08 + l32i a1, sp, 0x04 + rsr a0, excsave1 + + rfe + +.LSE_store_reg: + .org .LSE_store_reg + (7 * 8) + mov a4, a7 + j .LSE_store_data + + .org .LSE_store_reg + (8 * 8) + mov a4, a8 + j .LSE_store_data + + .org .LSE_store_reg + (9 * 8) + mov a4, a9 + j .LSE_store_data + + .org .LSE_store_reg + (10 * 8) + mov a4, a10 + j .LSE_store_data + + .org .LSE_store_reg + (11 * 8) + mov a4, a11 + j .LSE_store_data + + .org .LSE_store_reg + (12 * 8) + mov a4, a12 + j .LSE_store_data + + .org .LSE_store_reg + (13 * 8) + mov a4, a13 + j .LSE_store_data + + .org .LSE_store_reg + (14 * 8) + mov a4, a14 + j .LSE_store_data + + .org .LSE_store_reg + (15 * 8) + mov a4, a15 + j .LSE_store_data + + +/* LoadStoreAlignmentCause handler: + * + * Completes unaligned 16-bit and 32-bit load/store instructions from 32-bit aligned memory region + * Called from UserExceptionVector if EXCCAUSE is LoadStoreAlignmentCause + */ + + .global AlignmentErrorHandler + .section .iram1, "ax" + + .literal_position + + .balign 4 +AlignmentErrorHandler: + .type AlignmentErrorHandler, @function + + wsr a0, depc // Save return address in depc + mov a0, sp + movi sp, LoadStoreHandlerStack + s32i a0, sp, 0x04 // Since a0 contains value of a1 + s32i a2, sp, 0x08 + s32i a3, sp, 0x0c + s32i a4, sp, 0x10 + + rsr a0, sar // Save SAR in a0 to restore later + + /* Check whether the address lies in the valid range */ + rsr a3, excvaddr + movi a4, _iram_text_end // End of code section of IRAM + bge a3, a4, 1f + movi a4, SOC_CACHE_APP_LOW // Check if in APP cache region + blt a3, a4, .LS_wrong_opcode + movi a4, SOC_CACHE_APP_HIGH + bge a3, a4, .LS_wrong_opcode + j 2f + +1: + movi a4, SOC_IRAM_HIGH // End of IRAM address range + bge a3, a4, .LS_wrong_opcode + +2: + /* Examine the opcode which generated the exception */ + /* Note: Instructions are in this order to avoid pipeline stalls. */ + rsr a2, epc1 + movi a4, ~3 + ssa8l a2 // sar is now correct shift for aligned read + and a2, a2, a4 // a2 now 4-byte aligned address of instruction + l32i a4, a2, 0 + l32i a2, a2, 4 + + /* a2 has the instruction that caused the error */ + src a2, a2, a4 + extui a4, a2, 0, 4 + addi a4, a4, -9 + beqz a4, .LSA_store_op + bbsi a2, 14, .LSA_store_op + + ssa8l a3 // a3 contains the unaligned address + movi a4, ~3 + and a4, a3, a4 // a4 has the aligned address + l32i a3, a4, 0 + l32i a4, a4, 4 + src a4, a4, a3 + + rsr a3, epc1 + addi a3, a3, 2 + bbsi a2, 3, 1f // l32i.n + bbci a2, 1, .LS_wrong_opcode + addi a3, a3, 1 + + bbsi a2, 13, 1f // l32 + extui a4, a4, 0, 16 + bbci a2, 15, 1f // l16ui + + /* Sign adjustment */ + slli a4, a4, 16 + srai a4, a4, 16 // a4 contains the value + +1: + wsr a3, epc1 + wsr a0, sar + rsr a0, excsave1 + + extui a2, a2, 4, 4 + blti a2, 5, .LSA_stack_reg // a3 contains the target register + + movi a3, .LS_jumptable_base + slli a2, a2, 4 + add a2, a2, a3 // a2 is now the address to jump to + l32i a3, sp, 0x0c + jx a2 + +.LSA_stack_reg: + addx4 a2, a2, sp + s32i a4, a2, 0 + + /* Restore all values */ + l32i a4, sp, 0x10 + l32i a3, sp, 0x0c + l32i a2, sp, 0x08 + l32i a1, sp, 0x04 + rfe + +/* Store instruction */ +.LSA_store_op: + s32i a5, sp, 0x14 + s32i a6, sp, 0x18 + s32i a7, sp, 0x1c + + /* a2 -> instruction that caused the error */ + /* a3 -> unaligned address */ + extui a4, a2, 4, 4 + blti a4, 8, 1f + movi a5, .LSA_store_reg + addx8 a5, a4, a5 + jx a5 + +1: + addx4 a4, a4, sp + l32i a4, a4, 0 // a4 contains the value + +.LSA_store_data: + movi a6, 0 + + rsr a7, epc1 + addi a7, a7 ,2 + bbsi a2, 3, 1f // s32i.n + bbci a2, 1, .LS_wrong_opcode + + addi a7, a7, 1 + bbsi a2, 13, 1f // s32i + + movi a5, -1 + extui a4, a4, 0, 16 + slli a6, a5, 16 // 0xffff0000 + +1: + wsr a7, epc1 + movi a5, ~3 + and a5, a3, a5 // a5 has the aligned address + + ssa8b a3 + movi a3, -1 + src a7, a6, a3 + src a3, a3, a6 + + /* Store data on lower address */ + l32i a6, a5, 0 + and a6, a6, a7 + sll a7, a4 + or a6, a6, a7 + s32i a6, a5, 0 + + /* Store data on higher address */ + l32i a7, a5, 4 + srl a6, a4 + and a3, a7, a3 + or a3, a3, a6 + s32i a3, a5, 4 + + /* Restore registers */ + wsr a0, sar + rsr a0, excsave1 + + l32i a7, sp, 0x1c + l32i a6, sp, 0x18 + l32i a5, sp, 0x14 + l32i a4, sp, 0x10 + l32i a3, sp, 0x0c + l32i a2, sp, 0x08 + l32i a1, sp, 0x04 + rfe + +.LSA_store_reg: + .org .LSA_store_reg + (8 * 8) + mov a4, a8 + j .LSA_store_data + + .org .LSA_store_reg + (9 * 8) + mov a4, a9 + j .LSA_store_data + + .org .LSA_store_reg + (10 * 8) + mov a4, a10 + j .LSA_store_data + + .org .LSA_store_reg + (11 * 8) + mov a4, a11 + j .LSA_store_data + + .org .LSA_store_reg + (12 * 8) + mov a4, a12 + j .LSA_store_data + + .org .LSA_store_reg + (13 * 8) + mov a4, a13 + j .LSA_store_data + + .org .LSA_store_reg + (14 * 8) + mov a4, a14 + j .LSA_store_data + + .org .LSA_store_reg + (15 * 8) + mov a4, a15 + j .LSA_store_data + +/* + * Common routines for both the exception handlers + */ + .balign 4 +.LS_jumptable: + /* The first 5 entries (80 bytes) of this table are unused (registers + a0..a4 are handled separately above). Rather than have a whole bunch + of wasted space, just pretend that the table starts 80 bytes + earlier in memory. */ + .set .LS_jumptable_base, .LS_jumptable - (16 * 5) + + .org .LS_jumptable_base + (16 * 5) + mov a5, a4 + l32i a4, sp, 0x10 + l32i a2, sp, 0x08 + l32i a1, sp, 0x04 + rfe + + .org .LS_jumptable_base + (16 * 6) + mov a6, a4 + l32i a4, sp, 0x10 + l32i a2, sp, 0x08 + l32i a1, sp, 0x04 + rfe + + .org .LS_jumptable_base + (16 * 7) + mov a7, a4 + l32i a4, sp, 0x10 + l32i a2, sp, 0x08 + l32i a1, sp, 0x04 + rfe + + .org .LS_jumptable_base + (16 * 8) + mov a8, a4 + l32i a4, sp, 0x10 + l32i a2, sp, 0x08 + l32i a1, sp, 0x04 + rfe + + .org .LS_jumptable_base + (16 * 9) + mov a9, a4 + l32i a4, sp, 0x10 + l32i a2, sp, 0x08 + l32i a1, sp, 0x04 + rfe + + .org .LS_jumptable_base + (16 * 10) + mov a10, a4 + l32i a4, sp, 0x10 + l32i a2, sp, 0x08 + l32i a1, sp, 0x04 + rfe + + .org .LS_jumptable_base + (16 * 11) + mov a11, a4 + l32i a4, sp, 0x10 + l32i a2, sp, 0x08 + l32i a1, sp, 0x04 + rfe + + .org .LS_jumptable_base + (16 * 12) + mov a12, a4 + l32i a4, sp, 0x10 + l32i a2, sp, 0x08 + l32i a1, sp, 0x04 + rfe + + .org .LS_jumptable_base + (16 * 13) + mov a13, a4 + l32i a4, sp, 0x10 + l32i a2, sp, 0x08 + l32i a1, sp, 0x04 + rfe + + .org .LS_jumptable_base + (16 * 14) + mov a14, a4 + l32i a4, sp, 0x10 + l32i a2, sp, 0x08 + l32i a1, sp, 0x04 + rfe + + .org .LS_jumptable_base + (16 * 15) + mov a15, a4 + l32i a4, sp, 0x10 + l32i a2, sp, 0x08 + l32i a1, sp, 0x04 + rfe + +.LS_wrong_opcode: + /* Reaches here if the address is in invalid range or the opcode isn't supported. + * Restore registers and jump back to _xt_user_exc + */ + wsr a0, sar + l32i a4, sp, 0x10 + l32i a3, sp, 0x0c + l32i a2, sp, 0x08 + l32i a1, sp, 0x04 + rsr a0, depc + ret // Equivalent to jx a0 diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_overlay_os_hook.c b/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_overlay_os_hook.c new file mode 100644 index 000000000..4146f5d64 --- /dev/null +++ b/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_overlay_os_hook.c @@ -0,0 +1,76 @@ +/* + * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc. + * + * SPDX-License-Identifier: MIT + * + * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD + */ + +/* + * Copyright (c) 2015-2019 Cadence Design Systems, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/* xtensa_overlay_os_hook.c -- Overlay manager OS hooks for FreeRTOS. */ + +#include "FreeRTOS.h" +#include "semphr.h" + +#if configUSE_MUTEX + +/* Mutex object that controls access to the overlay. Currently only one + * overlay region is supported so one mutex suffices. + */ + static SemaphoreHandle_t xt_overlay_mutex; + + +/* This function should be overridden to provide OS specific init such + * as the creation of a mutex lock that can be used for overlay locking. + * Typically this mutex would be set up with priority inheritance. See + * overlay manager documentation for more details. + */ + void xt_overlay_init_os( void ) + { + /* Create the mutex for overlay access. Priority inheritance is + * required. + */ + xt_overlay_mutex = xSemaphoreCreateMutex(); + } + + +/* This function locks access to shared overlay resources, typically + * by acquiring a mutex. + */ + void xt_overlay_lock( void ) + { + xSemaphoreTake( xt_overlay_mutex, 0 ); + } + + +/* This function releases access to shared overlay resources, typically + * by unlocking a mutex. + */ + void xt_overlay_unlock( void ) + { + xSemaphoreGive( xt_overlay_mutex ); + } + +#endif /* if configUSE_MUTEX */ diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_vector_defaults.S b/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_vector_defaults.S new file mode 100644 index 000000000..a016e02d9 --- /dev/null +++ b/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_vector_defaults.S @@ -0,0 +1,235 @@ +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "xtensa_rtos.h" +#include "esp_idf_version.h" +#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0)) +#include "esp_panic.h" +#else +#include "esp_private/panic_reason.h" +#endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0) */ +#include "sdkconfig.h" +#include "soc/soc.h" + +/* +This file contains the default handlers for the high interrupt levels as well as some specialized exceptions. +The default behaviour is to just exit the interrupt or call the panic handler on the exceptions +*/ + + +#if XCHAL_HAVE_DEBUG + .global xt_debugexception + .weak xt_debugexception + .set xt_debugexception, _xt_debugexception + .section .iram1,"ax" + .type _xt_debugexception,@function + .align 4 + +_xt_debugexception: +#if (CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI) +#define XT_DEBUGCAUSE_DI (5) + getcoreid a0 +#if (CONFIG_BTDM_CTRL_PINNED_TO_CORE == PRO_CPU_NUM) + beqz a0, 1f +#else + bnez a0, 1f +#endif + + rsr a0, DEBUGCAUSE + extui a0, a0, XT_DEBUGCAUSE_DI, 1 + bnez a0, _xt_debug_di_exc +1: +#endif //(CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI) + + movi a0,PANIC_RSN_DEBUGEXCEPTION + wsr a0,EXCCAUSE + /* _xt_panic assumes a level 1 exception. As we're + crashing anyhow, copy EPC & EXCSAVE from DEBUGLEVEL + to level 1. */ + rsr a0,(EPC + XCHAL_DEBUGLEVEL) + wsr a0,EPC_1 + rsr a0,(EXCSAVE + XCHAL_DEBUGLEVEL) + wsr a0,EXCSAVE_1 + call0 _xt_panic /* does not return */ + rfi XCHAL_DEBUGLEVEL + +#if (CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI) + .align 4 +_xt_debug_di_exc: + + /* + The delay time can be calculated by the following formula: + T = ceil(0.25 + max(t1, t2)) us + + t1 = 80 / f1, t2 = (1 + 14/N) * 20 / f2 + + f1: PSRAM access frequency, unit: MHz. + f2: Flash access frequency, unit: MHz. + + When flash is slow/fast read, N = 1. + When flash is DOUT/DIO read, N = 2. + When flash is QOUT/QIO read, N = 4. + + And after testing, when CPU frequency is 240 MHz, it will take 1us to loop 27 times. + */ +#if defined(CONFIG_ESPTOOLPY_FLASHMODE_QIO) || defined(CONFIG_ESPTOOLPY_FLASHMODE_QOUT) + +# if defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_80M) + movi a0, 54 +# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_40M) + movi a0, 81 +# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_40M) && defined(CONFIG_SPIRAM_SPEED_40M) + movi a0, 81 +# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_26M) && defined(CONFIG_SPIRAM_SPEED_40M) + movi a0, 108 +# else + movi a0, 135 +# endif + +#elif defined(CONFIG_ESPTOOLPY_FLASHMODE_DIO) || defined(CONFIG_ESPTOOLPY_FLASHMODE_DOUT) + +# if defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_80M) + movi a0, 81 +# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_40M) + movi a0, 81 +# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_40M) && defined(CONFIG_SPIRAM_SPEED_40M) + movi a0, 135 +# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_26M) && defined(CONFIG_SPIRAM_SPEED_40M) + movi a0, 189 +# else + movi a0, 243 +# endif + +#else + movi a0, 243 +#endif + +1: addi a0, a0, -1 /* delay_us(N) */ + .rept 4 + nop + .endr + bnez a0, 1b + + rsr a0, EXCSAVE+XCHAL_DEBUGLEVEL + rfi XCHAL_DEBUGLEVEL +#endif //(CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI) +#endif /* Debug exception */ + + +#if XCHAL_NUM_INTLEVELS >=2 && XCHAL_EXCM_LEVEL <2 && XCHAL_DEBUGLEVEL !=2 + .global xt_highint2 + .weak xt_highint2 + .set xt_highint2, _xt_highint2 + .section .iram1,"ax" + .type _xt_highint2,@function + .align 4 +_xt_highint2: + + /* Default handler does nothing; just returns */ + .align 4 +.L_xt_highint2_exit: + rsr a0, EXCSAVE_2 /* restore a0 */ + rfi 2 + +#endif /* Level 2 */ + +#if XCHAL_NUM_INTLEVELS >=3 && XCHAL_EXCM_LEVEL <3 && XCHAL_DEBUGLEVEL !=3 + + .global xt_highint3 + .weak xt_highint3 + .set xt_highint3, _xt_highint3 + .section .iram1,"ax" + .type _xt_highint3,@function + .align 4 +_xt_highint3: + + /* Default handler does nothing; just returns */ + + .align 4 +.L_xt_highint3_exit: + rsr a0, EXCSAVE_3 /* restore a0 */ + rfi 3 + +#endif /* Level 3 */ + +#if XCHAL_NUM_INTLEVELS >=4 && XCHAL_EXCM_LEVEL <4 && XCHAL_DEBUGLEVEL !=4 + + .global xt_highint4 + .weak xt_highint4 + .set xt_highint4, _xt_highint4 + .section .iram1,"ax" + .type _xt_highint4,@function + .align 4 +_xt_highint4: + + /* Default handler does nothing; just returns */ + + .align 4 +.L_xt_highint4_exit: + rsr a0, EXCSAVE_4 /* restore a0 */ + rfi 4 + +#endif /* Level 4 */ + +#if XCHAL_NUM_INTLEVELS >=5 && XCHAL_EXCM_LEVEL <5 && XCHAL_DEBUGLEVEL !=5 + + .global xt_highint5 + .weak xt_highint5 + .set xt_highint5, _xt_highint5 + .section .iram1,"ax" + .type _xt_highint5,@function + .align 4 +_xt_highint5: + + /* Default handler does nothing; just returns */ + + .align 4 +.L_xt_highint5_exit: + rsr a0, EXCSAVE_5 /* restore a0 */ + rfi 5 + + +#endif /* Level 5 */ + +#if XCHAL_NUM_INTLEVELS >=6 && XCHAL_EXCM_LEVEL <6 && XCHAL_DEBUGLEVEL !=6 + + .global _xt_highint6 + .global xt_highint6 + .weak xt_highint6 + .set xt_highint6, _xt_highint6 + .section .iram1,"ax" + .type _xt_highint6,@function + .align 4 +_xt_highint6: + + /* Default handler does nothing; just returns */ + + .align 4 +.L_xt_highint6_exit: + rsr a0, EXCSAVE_6 /* restore a0 */ + rfi 6 + +#endif /* Level 6 */ + +#if XCHAL_HAVE_NMI + + .global _xt_nmi + .global xt_nmi + .weak xt_nmi + .set xt_nmi, _xt_nmi + .section .iram1,"ax" + .type _xt_nmi,@function + .align 4 +_xt_nmi: + + /* Default handler does nothing; just returns */ + + .align 4 +.L_xt_nmi_exit: + rsr a0, EXCSAVE + XCHAL_NMILEVEL /* restore a0 */ + rfi XCHAL_NMILEVEL + +#endif /* NMI */ diff --git a/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_vectors.S b/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_vectors.S new file mode 100644 index 000000000..3a0a9569d --- /dev/null +++ b/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_vectors.S @@ -0,0 +1,2067 @@ +/* + * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc. + * + * SPDX-License-Identifier: MIT + * + * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD + */ +/* + * Copyright (c) 2015-2019 Cadence Design Systems, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/******************************************************************************* +-------------------------------------------------------------------------------- + + XTENSA VECTORS AND LOW LEVEL HANDLERS FOR AN RTOS + + Xtensa low level exception and interrupt vectors and handlers for an RTOS. + + Interrupt handlers and user exception handlers support interaction with + the RTOS by calling XT_RTOS_INT_ENTER and XT_RTOS_INT_EXIT before and + after user's specific interrupt handlers. These macros are defined in + xtensa_.h to call suitable functions in a specific RTOS. + + Users can install application-specific interrupt handlers for low and + medium level interrupts, by calling xt_set_interrupt_handler(). These + handlers can be written in C, and must obey C calling convention. The + handler table is indexed by the interrupt number. Each handler may be + provided with an argument. + + Note that the system timer interrupt is handled specially, and is + dispatched to the RTOS-specific handler. This timer cannot be hooked + by application code. + + Optional hooks are also provided to install a handler per level at + run-time, made available by compiling this source file with + '-DXT_INTEXC_HOOKS' (useful for automated testing). + +!! This file is a template that usually needs to be modified to handle !! +!! application specific interrupts. Search USER_EDIT for helpful comments !! +!! on where to insert handlers and how to write them. !! + + Users can also install application-specific exception handlers in the + same way, by calling xt_set_exception_handler(). One handler slot is + provided for each exception type. Note that some exceptions are handled + by the porting layer itself, and cannot be taken over by application + code in this manner. These are the alloca, syscall, and coprocessor + exceptions. + + The exception handlers can be written in C, and must follow C calling + convention. Each handler is passed a pointer to an exception frame as + its single argument. The exception frame is created on the stack, and + holds the saved context of the thread that took the exception. If the + handler returns, the context will be restored and the instruction that + caused the exception will be retried. If the handler makes any changes + to the saved state in the exception frame, the changes will be applied + when restoring the context. + + Because Xtensa is a configurable architecture, this port supports all user + generated configurations (except restrictions stated in the release notes). + This is accomplished by conditional compilation using macros and functions + defined in the Xtensa HAL (hardware adaptation layer) for your configuration. + Only the relevant parts of this file will be included in your RTOS build. + For example, this file provides interrupt vector templates for all types and + all priority levels, but only the ones in your configuration are built. + + NOTES on the use of 'call0' for long jumps instead of 'j': + 1. This file should be assembled with the -mlongcalls option to xt-xcc. + 2. The -mlongcalls compiler option causes 'call0 dest' to be expanded to + a sequence 'l32r a0, dest' 'callx0 a0' which works regardless of the + distance from the call to the destination. The linker then relaxes + it back to 'call0 dest' if it determines that dest is within range. + This allows more flexibility in locating code without the performance + overhead of the 'l32r' literal data load in cases where the destination + is in range of 'call0'. There is an additional benefit in that 'call0' + has a longer range than 'j' due to the target being word-aligned, so + the 'l32r' sequence is less likely needed. + 3. The use of 'call0' with -mlongcalls requires that register a0 not be + live at the time of the call, which is always the case for a function + call but needs to be ensured if 'call0' is used as a jump in lieu of 'j'. + 4. This use of 'call0' is independent of the C function call ABI. + +*******************************************************************************/ + +#include "xtensa_rtos.h" +#include "esp_idf_version.h" +#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0)) +#include "esp_panic.h" +#else +#include "esp_private/panic_reason.h" +#endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0) */ +#include "sdkconfig.h" +#include "soc/soc.h" + +/* + Define for workaround: pin no-cpu-affinity tasks to a cpu when fpu is used. + Please change this when the tcb structure is changed +*/ +#define TASKTCB_XCOREID_OFFSET (0x38+configMAX_TASK_NAME_LEN+3)&~3 +.extern pxCurrentTCB + +/* +-------------------------------------------------------------------------------- + In order for backtracing to be able to trace from the pre-exception stack + across to the exception stack (including nested interrupts), we need to create + a pseudo base-save area to make it appear like the exception dispatcher was + triggered by a CALL4 from the pre-exception code. In reality, the exception + dispatcher uses the same window as pre-exception code, and only CALL0s are + used within the exception dispatcher. + + To create the pseudo base-save area, we need to store a copy of the pre-exception's + base save area (a0 to a4) below the exception dispatcher's SP. EXCSAVE_x will + be used to store a copy of the SP that points to the interrupted code's exception + frame just in case the exception dispatcher's SP does not point to the exception + frame (which is the case when switching from task to interrupt stack). + + Clearing the pseudo base-save area is uncessary as the interrupt dispatcher + will restore the current SP to that of the pre-exception SP. +-------------------------------------------------------------------------------- +*/ +#ifdef CONFIG_FREERTOS_INTERRUPT_BACKTRACE +#define XT_DEBUG_BACKTRACE 1 +#endif + + +/* +-------------------------------------------------------------------------------- + Defines used to access _xtos_interrupt_table. +-------------------------------------------------------------------------------- +*/ +#define XIE_HANDLER 0 +#define XIE_ARG 4 +#define XIE_SIZE 8 + + +/* + Macro get_percpu_entry_for - convert a per-core ID into a multicore entry. + Basically does reg=reg*portNUM_PROCESSORS+current_core_id + Multiple versions here to optimize for specific portNUM_PROCESSORS values. +*/ + .macro get_percpu_entry_for reg scratch +#if (portNUM_PROCESSORS == 1) + /* No need to do anything */ +#elif (portNUM_PROCESSORS == 2) + /* Optimized 2-core code. */ + getcoreid \scratch + addx2 \reg,\reg,\scratch +#else + /* Generalized n-core code. Untested! */ + movi \scratch,portNUM_PROCESSORS + mull \scratch,\reg,\scratch + getcoreid \reg + add \reg,\scratch,\reg +#endif + .endm +/* +-------------------------------------------------------------------------------- + Macro extract_msb - return the input with only the highest bit set. + + Input : "ain" - Input value, clobbered. + Output : "aout" - Output value, has only one bit set, MSB of "ain". + The two arguments must be different AR registers. +-------------------------------------------------------------------------------- +*/ + + .macro extract_msb aout ain +1: + addi \aout, \ain, -1 /* aout = ain - 1 */ + and \ain, \ain, \aout /* ain = ain & aout */ + bnez \ain, 1b /* repeat until ain == 0 */ + addi \aout, \aout, 1 /* return aout + 1 */ + .endm + +/* +-------------------------------------------------------------------------------- + Macro dispatch_c_isr - dispatch interrupts to user ISRs. + This will dispatch to user handlers (if any) that are registered in the + XTOS dispatch table (_xtos_interrupt_table). These handlers would have + been registered by calling _xtos_set_interrupt_handler(). There is one + exception - the timer interrupt used by the OS will not be dispatched + to a user handler - this must be handled by the caller of this macro. + + Level triggered and software interrupts are automatically deasserted by + this code. + + ASSUMPTIONS: + -- PS.INTLEVEL is set to "level" at entry + -- PS.EXCM = 0, C calling enabled + + NOTE: For CALL0 ABI, a12-a15 have not yet been saved. + + NOTE: This macro will use registers a0 and a2-a7. The arguments are: + level -- interrupt level + mask -- interrupt bitmask for this level +-------------------------------------------------------------------------------- +*/ + + .macro dispatch_c_isr level mask + + #ifdef CONFIG_PM_TRACE + movi a6, 0 /* = ESP_PM_TRACE_IDLE */ + getcoreid a7 + call4 esp_pm_trace_exit + #endif // CONFIG_PM_TRACE + + /* Get mask of pending, enabled interrupts at this level into a2. */ + +.L_xt_user_int_&level&: + rsr a2, INTENABLE + rsr a3, INTERRUPT + movi a4, \mask + and a2, a2, a3 + and a2, a2, a4 + beqz a2, 9f /* nothing to do */ + + /* This bit of code provides a nice debug backtrace in the debugger. + It does take a few more instructions, so undef XT_DEBUG_BACKTRACE + if you want to save the cycles. + At this point, the exception frame should have been allocated and filled, + and current sp points to the interrupt stack (for non-nested interrupt) + or below the allocated exception frame (for nested interrupts). Copy the + pre-exception's base save area below the current SP. + */ + #ifdef XT_DEBUG_BACKTRACE + #ifndef __XTENSA_CALL0_ABI__ + #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) + rsr a0, EXCSAVE_1 + \level - 1 /* Get exception frame pointer stored in EXCSAVE_x */ + l32i a3, a0, XT_STK_A0 /* Copy pre-exception a0 (return address) */ + s32e a3, a1, -16 + l32i a3, a0, XT_STK_A1 /* Copy pre-exception a1 (stack pointer) */ + s32e a3, a1, -12 + #endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */ + /* Backtracing only needs a0 and a1, no need to create full base save area. + Also need to change current frame's return address to point to pre-exception's + last run instruction. + */ + rsr a0, EPC_1 + \level - 1 /* return address */ + movi a4, 0xC0000000 /* constant with top 2 bits set (call size) */ + or a0, a0, a4 /* set top 2 bits */ + addx2 a0, a4, a0 /* clear top bit -- simulating call4 size */ + #endif + #endif + + #ifdef CONFIG_PM_ENABLE + call4 esp_pm_impl_isr_hook + #endif + + #ifdef XT_INTEXC_HOOKS + /* Call interrupt hook if present to (pre)handle interrupts. */ + movi a4, _xt_intexc_hooks + l32i a4, a4, \level << 2 + beqz a4, 2f + #ifdef __XTENSA_CALL0_ABI__ + callx0 a4 + beqz a2, 9f + #else + mov a6, a2 + callx4 a4 + beqz a6, 9f + mov a2, a6 + #endif +2: + #endif + + /* Now look up in the dispatch table and call user ISR if any. */ + /* If multiple bits are set then MSB has highest priority. */ + + extract_msb a4, a2 /* a4 = MSB of a2, a2 trashed */ + + #ifdef XT_USE_SWPRI + /* Enable all interrupts at this level that are numerically higher + than the one we just selected, since they are treated as higher + priority. + */ + movi a3, \mask /* a3 = all interrupts at this level */ + add a2, a4, a4 /* a2 = a4 << 1 */ + addi a2, a2, -1 /* a2 = mask of 1's <= a4 bit */ + and a2, a2, a3 /* a2 = mask of all bits <= a4 at this level */ + movi a3, _xt_intdata + l32i a6, a3, 4 /* a6 = _xt_vpri_mask */ + neg a2, a2 + addi a2, a2, -1 /* a2 = mask to apply */ + and a5, a6, a2 /* mask off all bits <= a4 bit */ + s32i a5, a3, 4 /* update _xt_vpri_mask */ + rsr a3, INTENABLE + and a3, a3, a2 /* mask off all bits <= a4 bit */ + wsr a3, INTENABLE + rsil a3, \level - 1 /* lower interrupt level by 1 */ + #endif + + #ifdef XT_RTOS_TIMER_INT + movi a3, XT_TIMER_INTEN /* a3 = timer interrupt bit */ + wsr a4, INTCLEAR /* clear sw or edge-triggered interrupt */ + beq a3, a4, 7f /* if timer interrupt then skip table */ + #else + wsr a4, INTCLEAR /* clear sw or edge-triggered interrupt */ + #endif // XT_RTOS_TIMER_INT + + find_ms_setbit a3, a4, a3, 0 /* a3 = interrupt number */ + + get_percpu_entry_for a3, a12 + movi a4, _xt_interrupt_table + addx8 a3, a3, a4 /* a3 = address of interrupt table entry */ + l32i a4, a3, XIE_HANDLER /* a4 = handler address */ + #ifdef __XTENSA_CALL0_ABI__ + mov a12, a6 /* save in callee-saved reg */ + l32i a2, a3, XIE_ARG /* a2 = handler arg */ + callx0 a4 /* call handler */ + mov a2, a12 + #else + mov a2, a6 /* save in windowed reg */ + l32i a6, a3, XIE_ARG /* a6 = handler arg */ + callx4 a4 /* call handler */ + #endif + + #ifdef XT_USE_SWPRI + j 8f + #else + j .L_xt_user_int_&level& /* check for more interrupts */ + #endif + #ifdef XT_RTOS_TIMER_INT +7: + + .ifeq XT_TIMER_INTPRI - \level +.L_xt_user_int_timer_&level&: + /* + Interrupt handler for the RTOS tick timer if at this level. + We'll be reading the interrupt state again after this call + so no need to preserve any registers except a6 (vpri_mask). + */ + + #ifdef __XTENSA_CALL0_ABI__ + mov a12, a6 + call0 XT_RTOS_TIMER_INT + mov a2, a12 + #else + mov a2, a6 + call4 XT_RTOS_TIMER_INT + #endif + .endif + #endif // XT_RTOS_TIMER_INT + + #ifdef XT_USE_SWPRI + j 8f + #else + j .L_xt_user_int_&level& /* check for more interrupts */ + #endif + + #ifdef XT_USE_SWPRI +8: + /* Restore old value of _xt_vpri_mask from a2. Also update INTENABLE from + virtual _xt_intenable which _could_ have changed during interrupt + processing. */ + + movi a3, _xt_intdata + l32i a4, a3, 0 /* a4 = _xt_intenable */ + s32i a2, a3, 4 /* update _xt_vpri_mask */ + and a4, a4, a2 /* a4 = masked intenable */ + wsr a4, INTENABLE /* update INTENABLE */ + #endif + +9: + /* done */ + + .endm + +#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0)) +/* +-------------------------------------------------------------------------------- + Panic handler. + Should be reached by call0 (preferable) or jump only. If call0, a0 says where + from. If on simulator, display panic message and abort, else loop indefinitely. +-------------------------------------------------------------------------------- +*/ + + .section .iram1,"ax" + .global panicHandler + + .global _xt_panic + .type _xt_panic,@function + .align 4 + .literal_position + .align 4 + +_xt_panic: + /* Allocate exception frame and save minimal context. */ + mov a0, sp + addi sp, sp, -XT_STK_FRMSZ + s32i a0, sp, XT_STK_A1 + #if XCHAL_HAVE_WINDOWED + s32e a0, sp, -12 /* for debug backtrace */ + #endif + rsr a0, PS /* save interruptee's PS */ + s32i a0, sp, XT_STK_PS + rsr a0, EPC_1 /* save interruptee's PC */ + s32i a0, sp, XT_STK_PC + #if XCHAL_HAVE_WINDOWED + s32e a0, sp, -16 /* for debug backtrace */ + #endif + s32i a12, sp, XT_STK_A12 /* _xt_context_save requires A12- */ + s32i a13, sp, XT_STK_A13 /* A13 to have already been saved */ + call0 _xt_context_save + + /* Save exc cause and vaddr into exception frame */ + rsr a0, EXCCAUSE + s32i a0, sp, XT_STK_EXCCAUSE + rsr a0, EXCVADDR + s32i a0, sp, XT_STK_EXCVADDR + + /* _xt_context_save seems to save the current a0, but we need the interuptees a0. Fix this. */ + rsr a0, EXCSAVE_1 /* save interruptee's a0 */ + + s32i a0, sp, XT_STK_A0 + + /* Set up PS for C, disable all interrupts except NMI and debug, and clear EXCM. */ + movi a0, PS_INTLEVEL(5) | PS_UM | PS_WOE + wsr a0, PS + + //Call panic handler + mov a6,sp + call4 panicHandler + + + .align 4 +//Call using call0. Prints the hex char in a2. Kills a3, a4, a5 +panic_print_hex: + movi a3,0x60000000 + movi a4,8 +panic_print_hex_loop: + l32i a5, a3, 0x1c + extui a5, a5, 16, 8 + bgei a5,64,panic_print_hex_loop + + srli a5,a2,28 + bgei a5,10,panic_print_hex_a + addi a5,a5,'0' + j panic_print_hex_ok +panic_print_hex_a: + addi a5,a5,'A'-10 +panic_print_hex_ok: + s32i a5,a3,0 + slli a2,a2,4 + + addi a4,a4,-1 + bnei a4,0,panic_print_hex_loop + movi a5,' ' + s32i a5,a3,0 + + ret +#endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */ + + + .section .rodata, "a" + .align 4 + +/* +-------------------------------------------------------------------------------- + Hooks to dynamically install handlers for exceptions and interrupts. + Allows automated regression frameworks to install handlers per test. + Consists of an array of function pointers indexed by interrupt level, + with index 0 containing the entry for user exceptions. + Initialized with all 0s, meaning no handler is installed at each level. + See comment in xtensa_rtos.h for more details. + + *WARNING* This array is for all CPUs, that is, installing a hook for + one CPU will install it for all others as well! +-------------------------------------------------------------------------------- +*/ + + #ifdef XT_INTEXC_HOOKS + .data + .global _xt_intexc_hooks + .type _xt_intexc_hooks,@object + .align 4 + +_xt_intexc_hooks: + .fill XT_INTEXC_HOOK_NUM, 4, 0 + #endif + + +/* +-------------------------------------------------------------------------------- + EXCEPTION AND LEVEL 1 INTERRUPT VECTORS AND LOW LEVEL HANDLERS + (except window exception vectors). + + Each vector goes at a predetermined location according to the Xtensa + hardware configuration, which is ensured by its placement in a special + section known to the Xtensa linker support package (LSP). It performs + the minimum necessary before jumping to the handler in the .text section. + + The corresponding handler goes in the normal .text section. It sets up + the appropriate stack frame, saves a few vector-specific registers and + calls XT_RTOS_INT_ENTER to save the rest of the interrupted context + and enter the RTOS, then sets up a C environment. It then calls the + user's interrupt handler code (which may be coded in C) and finally + calls XT_RTOS_INT_EXIT to transfer control to the RTOS for scheduling. + + While XT_RTOS_INT_EXIT does not return directly to the interruptee, + eventually the RTOS scheduler will want to dispatch the interrupted + task or handler. The scheduler will return to the exit point that was + saved in the interrupt stack frame at XT_STK_EXIT. +-------------------------------------------------------------------------------- +*/ + + +/* +-------------------------------------------------------------------------------- +Debug Exception. +-------------------------------------------------------------------------------- +*/ + +#if XCHAL_HAVE_DEBUG + + .begin literal_prefix .DebugExceptionVector + .section .DebugExceptionVector.text, "ax" + .global _DebugExceptionVector + .align 4 + .global xt_debugexception +_DebugExceptionVector: + wsr a0, EXCSAVE+XCHAL_DEBUGLEVEL /* preserve a0 */ + call0 xt_debugexception /* load exception handler */ + + .end literal_prefix + +#endif + +/* +-------------------------------------------------------------------------------- +Double Exception. +Double exceptions are not a normal occurrence. They indicate a bug of some kind. +-------------------------------------------------------------------------------- +*/ + +#ifdef XCHAL_DOUBLEEXC_VECTOR_VADDR + + .begin literal_prefix .DoubleExceptionVector + .section .DoubleExceptionVector.text, "ax" + .global _DoubleExceptionVector + .align 4 + +_DoubleExceptionVector: + + #if XCHAL_HAVE_DEBUG + break 1, 4 /* unhandled double exception */ + #endif + movi a0,PANIC_RSN_DOUBLEEXCEPTION + wsr a0,EXCCAUSE + call0 _xt_panic /* does not return */ + rfde /* make a0 point here not later */ + + .end literal_prefix + +#endif /* XCHAL_DOUBLEEXC_VECTOR_VADDR */ + +/* +-------------------------------------------------------------------------------- +Kernel Exception (including Level 1 Interrupt from kernel mode). +-------------------------------------------------------------------------------- +*/ + + .begin literal_prefix .KernelExceptionVector + .section .KernelExceptionVector.text, "ax" + .global _KernelExceptionVector + .align 4 + +_KernelExceptionVector: + + wsr a0, EXCSAVE_1 /* preserve a0 */ + call0 _xt_kernel_exc /* kernel exception handler */ + /* never returns here - call0 is used as a jump (see note at top) */ + + .end literal_prefix + + .section .iram1,"ax" + .align 4 + +_xt_kernel_exc: + #if XCHAL_HAVE_DEBUG + break 1, 0 /* unhandled kernel exception */ + #endif + movi a0,PANIC_RSN_KERNELEXCEPTION + wsr a0,EXCCAUSE + call0 _xt_panic /* does not return */ + rfe /* make a0 point here not there */ + + +/* +-------------------------------------------------------------------------------- +User Exception (including Level 1 Interrupt from user mode). +-------------------------------------------------------------------------------- +*/ + + .begin literal_prefix .UserExceptionVector + .section .UserExceptionVector.text, "ax" + .global _UserExceptionVector + .type _UserExceptionVector,@function + .align 4 + +_UserExceptionVector: + + wsr a0, EXCSAVE_1 /* preserve a0 */ + call0 _xt_user_exc /* user exception handler */ + /* never returns here - call0 is used as a jump (see note at top) */ + + .end literal_prefix + +/* +-------------------------------------------------------------------------------- + Insert some waypoints for jumping beyond the signed 8-bit range of + conditional branch instructions, so the conditional branchces to specific + exception handlers are not taken in the mainline. Saves some cycles in the + mainline. +-------------------------------------------------------------------------------- +*/ + +#ifdef CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY + .global LoadStoreErrorHandler + .global AlignmentErrorHandler +#endif + + .section .iram1,"ax" + + #if XCHAL_HAVE_WINDOWED + .align 4 +_xt_to_alloca_exc: + call0 _xt_alloca_exc /* in window vectors section */ + /* never returns here - call0 is used as a jump (see note at top) */ + #endif + + .align 4 +_xt_to_syscall_exc: + call0 _xt_syscall_exc + /* never returns here - call0 is used as a jump (see note at top) */ + + #if XCHAL_CP_NUM > 0 + .align 4 +_xt_to_coproc_exc: + call0 _xt_coproc_exc + /* never returns here - call0 is used as a jump (see note at top) */ + #endif + +#ifdef CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY + .align 4 +_call_loadstore_handler: + call0 LoadStoreErrorHandler + /* This will return only if wrong opcode or address out of range*/ + j .LS_exit + + .align 4 +_call_alignment_handler: + call0 AlignmentErrorHandler + /* This will return only if wrong opcode or address out of range*/ + addi a0, a0, 1 + j .LS_exit +#endif + +/* +-------------------------------------------------------------------------------- + User exception handler. +-------------------------------------------------------------------------------- +*/ + + .type _xt_user_exc,@function + .align 4 + +_xt_user_exc: + + /* If level 1 interrupt then jump to the dispatcher */ + rsr a0, EXCCAUSE + beqi a0, EXCCAUSE_LEVEL1INTERRUPT, _xt_lowint1 + + /* Handle any coprocessor exceptions. Rely on the fact that exception + numbers above EXCCAUSE_CP0_DISABLED all relate to the coprocessors. + */ + #if XCHAL_CP_NUM > 0 + bgeui a0, EXCCAUSE_CP0_DISABLED, _xt_to_coproc_exc + #endif + + /* Handle alloca and syscall exceptions */ + #if XCHAL_HAVE_WINDOWED + beqi a0, EXCCAUSE_ALLOCA, _xt_to_alloca_exc + #endif + beqi a0, EXCCAUSE_SYSCALL, _xt_to_syscall_exc + +#ifdef CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY + beqi a0, EXCCAUSE_LOAD_STORE_ERROR, _call_loadstore_handler + + addi a0, a0, -1 + beqi a0, 8, _call_alignment_handler + addi a0, a0, 1 +.LS_exit: +#endif + + /* Handle all other exceptions. All can have user-defined handlers. */ + /* NOTE: we'll stay on the user stack for exception handling. */ + + /* Allocate exception frame and save minimal context. */ + mov a0, sp + addi sp, sp, -XT_STK_FRMSZ + s32i a0, sp, XT_STK_A1 + #if XCHAL_HAVE_WINDOWED + s32e a0, sp, -12 /* for debug backtrace */ + #endif + rsr a0, PS /* save interruptee's PS */ + s32i a0, sp, XT_STK_PS + rsr a0, EPC_1 /* save interruptee's PC */ + s32i a0, sp, XT_STK_PC + #if XCHAL_HAVE_WINDOWED + s32e a0, sp, -16 /* for debug backtrace */ + #endif + s32i a12, sp, XT_STK_A12 /* _xt_context_save requires A12- */ + s32i a13, sp, XT_STK_A13 /* A13 to have already been saved */ + call0 _xt_context_save + + /* Save exc cause and vaddr into exception frame */ + rsr a0, EXCCAUSE + s32i a0, sp, XT_STK_EXCCAUSE + rsr a0, EXCVADDR + s32i a0, sp, XT_STK_EXCVADDR + + /* _xt_context_save seems to save the current a0, but we need the interuptees a0. Fix this. */ + rsr a0, EXCSAVE_1 /* save interruptee's a0 */ + s32i a0, sp, XT_STK_A0 + + /* Set up PS for C, reenable debug and NMI interrupts, and clear EXCM. */ + #ifdef __XTENSA_CALL0_ABI__ + movi a0, PS_INTLEVEL(XCHAL_DEBUGLEVEL - 2) | PS_UM + #else + movi a0, PS_INTLEVEL(XCHAL_DEBUGLEVEL - 2) | PS_UM | PS_WOE + #endif + wsr a0, PS + + /* + Create pseudo base save area. At this point, sp is still pointing to the + allocated and filled exception stack frame. + */ + #ifdef XT_DEBUG_BACKTRACE + #ifndef __XTENSA_CALL0_ABI__ + #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) + l32i a3, sp, XT_STK_A0 /* Copy pre-exception a0 (return address) */ + s32e a3, sp, -16 + l32i a3, sp, XT_STK_A1 /* Copy pre-exception a1 (stack pointer) */ + s32e a3, sp, -12 + #endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */ + rsr a0, EPC_1 /* return address for debug backtrace */ + movi a5, 0xC0000000 /* constant with top 2 bits set (call size) */ + rsync /* wait for WSR.PS to complete */ + or a0, a0, a5 /* set top 2 bits */ + addx2 a0, a5, a0 /* clear top bit -- thus simulating call4 size */ + #else + rsync /* wait for WSR.PS to complete */ + #endif + #endif + + rsr a2, EXCCAUSE /* recover exc cause */ + + #ifdef XT_INTEXC_HOOKS + /* + Call exception hook to pre-handle exceptions (if installed). + Pass EXCCAUSE in a2, and check result in a2 (if -1, skip default handling). + */ + movi a4, _xt_intexc_hooks + l32i a4, a4, 0 /* user exception hook index 0 */ + beqz a4, 1f +.Ln_xt_user_exc_call_hook: + #ifdef __XTENSA_CALL0_ABI__ + callx0 a4 + beqi a2, -1, .L_xt_user_done + #else + mov a6, a2 + callx4 a4 + beqi a6, -1, .L_xt_user_done + mov a2, a6 + #endif +1: + #endif + + rsr a2, EXCCAUSE /* recover exc cause */ + movi a3, _xt_exception_table + get_percpu_entry_for a2, a4 + addx4 a4, a2, a3 /* a4 = address of exception table entry */ + l32i a4, a4, 0 /* a4 = handler address */ + #ifdef __XTENSA_CALL0_ABI__ + mov a2, sp /* a2 = pointer to exc frame */ + callx0 a4 /* call handler */ + #else + mov a6, sp /* a6 = pointer to exc frame */ + callx4 a4 /* call handler */ + #endif + +.L_xt_user_done: + + /* Restore context and return */ + call0 _xt_context_restore + l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */ + wsr a0, PS + l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */ + wsr a0, EPC_1 + l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */ + l32i sp, sp, XT_STK_A1 /* remove exception frame */ + rsync /* ensure PS and EPC written */ + rfe /* PS.EXCM is cleared */ + + +/* +-------------------------------------------------------------------------------- + Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT + on entry and used to return to a thread or interrupted interrupt handler. +-------------------------------------------------------------------------------- +*/ + + .global _xt_user_exit + .type _xt_user_exit,@function + .align 4 +_xt_user_exit: + l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */ + wsr a0, PS + l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */ + wsr a0, EPC_1 + l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */ + l32i sp, sp, XT_STK_A1 /* remove interrupt stack frame */ + rsync /* ensure PS and EPC written */ + rfe /* PS.EXCM is cleared */ + + +/* + +-------------------------------------------------------------------------------- +Syscall Exception Handler (jumped to from User Exception Handler). +Syscall 0 is required to spill the register windows (no-op in Call 0 ABI). +Only syscall 0 is handled here. Other syscalls return -1 to caller in a2. +-------------------------------------------------------------------------------- +*/ + + .section .iram1,"ax" + .type _xt_syscall_exc,@function + .align 4 +_xt_syscall_exc: + + #ifdef __XTENSA_CALL0_ABI__ + /* + Save minimal regs for scratch. Syscall 0 does nothing in Call0 ABI. + Use a minimal stack frame (16B) to save A2 & A3 for scratch. + PS.EXCM could be cleared here, but unlikely to improve worst-case latency. + rsr a0, PS + addi a0, a0, -PS_EXCM_MASK + wsr a0, PS + */ + addi sp, sp, -16 + s32i a2, sp, 8 + s32i a3, sp, 12 + #else /* Windowed ABI */ + /* + Save necessary context and spill the register windows. + PS.EXCM is still set and must remain set until after the spill. + Reuse context save function though it saves more than necessary. + For this reason, a full interrupt stack frame is allocated. + */ + addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */ + s32i a12, sp, XT_STK_A12 /* _xt_context_save requires A12- */ + s32i a13, sp, XT_STK_A13 /* A13 to have already been saved */ + call0 _xt_context_save + #endif + + /* + Grab the interruptee's PC and skip over the 'syscall' instruction. + If it's at the end of a zero-overhead loop and it's not on the last + iteration, decrement loop counter and skip to beginning of loop. + */ + rsr a2, EPC_1 /* a2 = PC of 'syscall' */ + addi a3, a2, 3 /* ++PC */ + #if XCHAL_HAVE_LOOPS + rsr a0, LEND /* if (PC == LEND */ + bne a3, a0, 1f + rsr a0, LCOUNT /* && LCOUNT != 0) */ + beqz a0, 1f /* { */ + addi a0, a0, -1 /* --LCOUNT */ + rsr a3, LBEG /* PC = LBEG */ + wsr a0, LCOUNT /* } */ + #endif +1: wsr a3, EPC_1 /* update PC */ + + /* Restore interruptee's context and return from exception. */ + #ifdef __XTENSA_CALL0_ABI__ + l32i a2, sp, 8 + l32i a3, sp, 12 + addi sp, sp, 16 + #else + call0 _xt_context_restore + addi sp, sp, XT_STK_FRMSZ + #endif + movi a0, -1 + movnez a2, a0, a2 /* return -1 if not syscall 0 */ + rsr a0, EXCSAVE_1 + rfe + +/* +-------------------------------------------------------------------------------- +Co-Processor Exception Handler (jumped to from User Exception Handler). +These exceptions are generated by co-processor instructions, which are only +allowed in thread code (not in interrupts or kernel code). This restriction is +deliberately imposed to reduce the burden of state-save/restore in interrupts. +-------------------------------------------------------------------------------- +*/ +#if XCHAL_CP_NUM > 0 + + .section .rodata, "a" + +/* Offset to CP n save area in thread's CP save area. */ + .global _xt_coproc_sa_offset + .type _xt_coproc_sa_offset,@object + .align 16 /* minimize crossing cache boundaries */ +_xt_coproc_sa_offset: + .word XT_CP0_SA, XT_CP1_SA, XT_CP2_SA, XT_CP3_SA + .word XT_CP4_SA, XT_CP5_SA, XT_CP6_SA, XT_CP7_SA + +/* Bitmask for CP n's CPENABLE bit. */ + .type _xt_coproc_mask,@object + .align 16,,8 /* try to keep it all in one cache line */ + .set i, 0 +_xt_coproc_mask: + .rept XCHAL_CP_MAX + .long (i<<16) | (1<= ESP_IDF_VERSION_VAL(4, 2, 0)) + #ifndef CONFIG_FREERTOS_FPU_IN_ISR + #endif + beq a15, a2, .L_goto_done /* new owner == old, we're done */ + #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) + #endif + #endif + + /* If no old owner then nothing to save. */ + beqz a2, .L_check_new + + /* If old owner not actively using CP then nothing to save. */ + l16ui a4, a2, XT_CPENABLE /* a4 = old owner's CPENABLE */ + bnone a4, a0, .L_check_new /* old owner not using CP */ + +.L_save_old: + /* Save old owner's coprocessor state. */ + + movi a5, _xt_coproc_sa_offset + + /* Mark old owner state as no longer active (CPENABLE bit n clear). */ + xor a4, a4, a0 /* clear CP bit in CPENABLE */ + s16i a4, a2, XT_CPENABLE /* update old owner's CPENABLE */ + + extui a4, a0, 16, 5 /* a4 = CP index = n */ + addx4 a5, a4, a5 /* a5 = &_xt_coproc_sa_offset[n] */ + + /* Mark old owner state as saved (CPSTORED bit n set). */ + l16ui a4, a2, XT_CPSTORED /* a4 = old owner's CPSTORED */ + l32i a5, a5, 0 /* a5 = XT_CP[n]_SA offset */ + or a4, a4, a0 /* set CP in old owner's CPSTORED */ + s16i a4, a2, XT_CPSTORED /* update old owner's CPSTORED */ + l32i a2, a2, XT_CP_ASA /* ptr to actual (aligned) save area */ + extui a3, a0, 16, 5 /* a3 = CP index = n */ + add a2, a2, a5 /* a2 = old owner's area for CP n */ + + /* + The config-specific HAL macro invoked below destroys a2-5, preserves a0-1. + It is theoretically possible for Xtensa processor designers to write TIE + that causes more address registers to be affected, but it is generally + unlikely. If that ever happens, more registers needs to be saved/restored + around this macro invocation, and the value in a15 needs to be recomputed. + */ + xchal_cpi_store_funcbody + +.L_check_new: + /* Check if any state has to be restored for new owner. */ + /* NOTE: a15 = new owner's save area, cannot be zero when we get here. */ + #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) + beqz a15, .L_xt_coproc_done + #endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */ + + l16ui a3, a15, XT_CPSTORED /* a3 = new owner's CPSTORED */ + movi a4, _xt_coproc_sa_offset + bnone a3, a0, .L_check_cs /* full CP not saved, check callee-saved */ + xor a3, a3, a0 /* CPSTORED bit is set, clear it */ + s16i a3, a15, XT_CPSTORED /* update new owner's CPSTORED */ + + /* Adjust new owner's save area pointers to area for CP n. */ + extui a3, a0, 16, 5 /* a3 = CP index = n */ + addx4 a4, a3, a4 /* a4 = &_xt_coproc_sa_offset[n] */ + l32i a4, a4, 0 /* a4 = XT_CP[n]_SA */ + l32i a5, a15, XT_CP_ASA /* ptr to actual (aligned) save area */ + add a2, a4, a5 /* a2 = new owner's area for CP */ + + /* + The config-specific HAL macro invoked below destroys a2-5, preserves a0-1. + It is theoretically possible for Xtensa processor designers to write TIE + that causes more address registers to be affected, but it is generally + unlikely. If that ever happens, more registers needs to be saved/restored + around this macro invocation. + */ + xchal_cpi_load_funcbody + + /* Restore interruptee's saved registers. */ + /* Can omit rsync for wsr.CPENABLE here because _xt_user_exit does it. */ +.L_xt_coproc_done: + l32i a15, sp, XT_STK_A15 + l32i a5, sp, XT_STK_A5 + l32i a4, sp, XT_STK_A4 + l32i a3, sp, XT_STK_A3 + l32i a2, sp, XT_STK_A2 + call0 _xt_user_exit /* return via exit dispatcher */ + /* Never returns here - call0 is used as a jump (see note at top) */ + +.L_check_cs: + /* a0 = CP mask in low bits, a15 = new owner's save area */ + l16ui a2, a15, XT_CP_CS_ST /* a2 = mask of CPs saved */ + bnone a2, a0, .L_xt_coproc_done /* if no match then done */ + and a2, a2, a0 /* a2 = which CPs to restore */ + extui a2, a2, 0, 8 /* extract low 8 bits */ + s32i a6, sp, XT_STK_A6 /* save extra needed regs */ + s32i a7, sp, XT_STK_A7 + s32i a13, sp, XT_STK_A13 + s32i a14, sp, XT_STK_A14 + call0 _xt_coproc_restorecs /* restore CP registers */ + l32i a6, sp, XT_STK_A6 /* restore saved registers */ + l32i a7, sp, XT_STK_A7 + l32i a13, sp, XT_STK_A13 + l32i a14, sp, XT_STK_A14 + j .L_xt_coproc_done + + /* Co-processor exception occurred outside a thread (not supported). */ +.L_xt_coproc_invalid: + movi a0,PANIC_RSN_COPROCEXCEPTION + wsr a0,EXCCAUSE + call0 _xt_panic /* not in a thread (invalid) */ + /* never returns */ + + +#endif /* XCHAL_CP_NUM */ + + +/* +------------------------------------------------------------------------------- + Level 1 interrupt dispatch. Assumes stack frame has not been allocated yet. +------------------------------------------------------------------------------- +*/ + + .section .iram1,"ax" + .type _xt_lowint1,@function + .align 4 + +_xt_lowint1: + mov a0, sp /* sp == a1 */ + addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */ + s32i a0, sp, XT_STK_A1 /* save pre-interrupt SP */ + rsr a0, PS /* save interruptee's PS */ + s32i a0, sp, XT_STK_PS + rsr a0, EPC_1 /* save interruptee's PC */ + s32i a0, sp, XT_STK_PC + rsr a0, EXCSAVE_1 /* save interruptee's a0 */ + s32i a0, sp, XT_STK_A0 + movi a0, _xt_user_exit /* save exit point for dispatch */ + s32i a0, sp, XT_STK_EXIT + + #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) + /* EXCSAVE_1 should now be free to use. Use it to keep a copy of the + current stack pointer that points to the exception frame (XT_STK_FRAME).*/ + #ifdef XT_DEBUG_BACKTRACE + #ifndef __XTENSA_CALL0_ABI__ + mov a0, sp + wsr a0, EXCSAVE_1 + #endif + #endif + #endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */ + + + /* Save rest of interrupt context and enter RTOS. */ + call0 XT_RTOS_INT_ENTER /* common RTOS interrupt entry */ + + /* !! We are now on the RTOS system stack !! */ + + /* Set up PS for C, enable interrupts above this level and clear EXCM. */ + #ifdef __XTENSA_CALL0_ABI__ + movi a0, PS_INTLEVEL(1) | PS_UM + #else + movi a0, PS_INTLEVEL(1) | PS_UM | PS_WOE + #endif + wsr a0, PS + rsync + + /* OK to call C code at this point, dispatch user ISRs */ + + dispatch_c_isr 1 XCHAL_INTLEVEL1_MASK + + /* Done handling interrupts, transfer control to OS */ + call0 XT_RTOS_INT_EXIT /* does not return directly here */ + + +/* +------------------------------------------------------------------------------- + MEDIUM PRIORITY (LEVEL 2+) INTERRUPT VECTORS AND LOW LEVEL HANDLERS. + + Medium priority interrupts are by definition those with priority greater + than 1 and not greater than XCHAL_EXCM_LEVEL. These are disabled by + setting PS.EXCM and therefore can easily support a C environment for + handlers in C, and interact safely with an RTOS. + + Each vector goes at a predetermined location according to the Xtensa + hardware configuration, which is ensured by its placement in a special + section known to the Xtensa linker support package (LSP). It performs + the minimum necessary before jumping to the handler in the .text section. + + The corresponding handler goes in the normal .text section. It sets up + the appropriate stack frame, saves a few vector-specific registers and + calls XT_RTOS_INT_ENTER to save the rest of the interrupted context + and enter the RTOS, then sets up a C environment. It then calls the + user's interrupt handler code (which may be coded in C) and finally + calls XT_RTOS_INT_EXIT to transfer control to the RTOS for scheduling. + + While XT_RTOS_INT_EXIT does not return directly to the interruptee, + eventually the RTOS scheduler will want to dispatch the interrupted + task or handler. The scheduler will return to the exit point that was + saved in the interrupt stack frame at XT_STK_EXIT. +------------------------------------------------------------------------------- +*/ + +#if XCHAL_EXCM_LEVEL >= 2 + + .begin literal_prefix .Level2InterruptVector + .section .Level2InterruptVector.text, "ax" + .global _Level2Vector + .type _Level2Vector,@function + .align 4 +_Level2Vector: + wsr a0, EXCSAVE_2 /* preserve a0 */ + call0 _xt_medint2 /* load interrupt handler */ + /* never returns here - call0 is used as a jump (see note at top) */ + + .end literal_prefix + + .section .iram1,"ax" + .type _xt_medint2,@function + .align 4 +_xt_medint2: + mov a0, sp /* sp == a1 */ + addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */ + s32i a0, sp, XT_STK_A1 /* save pre-interrupt SP */ + rsr a0, EPS_2 /* save interruptee's PS */ + s32i a0, sp, XT_STK_PS + rsr a0, EPC_2 /* save interruptee's PC */ + s32i a0, sp, XT_STK_PC + rsr a0, EXCSAVE_2 /* save interruptee's a0 */ + s32i a0, sp, XT_STK_A0 + movi a0, _xt_medint2_exit /* save exit point for dispatch */ + s32i a0, sp, XT_STK_EXIT + + /* EXCSAVE_2 should now be free to use. Use it to keep a copy of the + current stack pointer that points to the exception frame (XT_STK_FRAME).*/ + #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) + #ifdef XT_DEBUG_BACKTRACE + #ifndef __XTENSA_CALL0_ABI__ + mov a0, sp + wsr a0, EXCSAVE_2 + #endif + #endif + #endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */ + + + /* Save rest of interrupt context and enter RTOS. */ + call0 XT_RTOS_INT_ENTER /* common RTOS interrupt entry */ + + /* !! We are now on the RTOS system stack !! */ + + /* Set up PS for C, enable interrupts above this level and clear EXCM. */ + #ifdef __XTENSA_CALL0_ABI__ + movi a0, PS_INTLEVEL(2) | PS_UM + #else + movi a0, PS_INTLEVEL(2) | PS_UM | PS_WOE + #endif + wsr a0, PS + rsync + + /* OK to call C code at this point, dispatch user ISRs */ + + dispatch_c_isr 2 XCHAL_INTLEVEL2_MASK + + /* Done handling interrupts, transfer control to OS */ + call0 XT_RTOS_INT_EXIT /* does not return directly here */ + + /* + Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT + on entry and used to return to a thread or interrupted interrupt handler. + */ + .global _xt_medint2_exit + .type _xt_medint2_exit,@function + .align 4 +_xt_medint2_exit: + /* Restore only level-specific regs (the rest were already restored) */ + l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */ + wsr a0, EPS_2 + l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */ + wsr a0, EPC_2 + l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */ + l32i sp, sp, XT_STK_A1 /* remove interrupt stack frame */ + rsync /* ensure EPS and EPC written */ + rfi 2 + +#endif /* Level 2 */ + +#if XCHAL_EXCM_LEVEL >= 3 + + .begin literal_prefix .Level3InterruptVector + .section .Level3InterruptVector.text, "ax" + .global _Level3Vector + .type _Level3Vector,@function + .align 4 +_Level3Vector: + wsr a0, EXCSAVE_3 /* preserve a0 */ + call0 _xt_medint3 /* load interrupt handler */ + /* never returns here - call0 is used as a jump (see note at top) */ + + .end literal_prefix + + .section .iram1,"ax" + .type _xt_medint3,@function + .align 4 +_xt_medint3: + mov a0, sp /* sp == a1 */ + addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */ + s32i a0, sp, XT_STK_A1 /* save pre-interrupt SP */ + rsr a0, EPS_3 /* save interruptee's PS */ + s32i a0, sp, XT_STK_PS + rsr a0, EPC_3 /* save interruptee's PC */ + s32i a0, sp, XT_STK_PC + rsr a0, EXCSAVE_3 /* save interruptee's a0 */ + s32i a0, sp, XT_STK_A0 + movi a0, _xt_medint3_exit /* save exit point for dispatch */ + s32i a0, sp, XT_STK_EXIT + + /* EXCSAVE_3 should now be free to use. Use it to keep a copy of the + current stack pointer that points to the exception frame (XT_STK_FRAME).*/ + #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) + #ifdef XT_DEBUG_BACKTRACE + #ifndef __XTENSA_CALL0_ABI__ + mov a0, sp + wsr a0, EXCSAVE_3 + #endif + #endif + #endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */ + + + /* Save rest of interrupt context and enter RTOS. */ + call0 XT_RTOS_INT_ENTER /* common RTOS interrupt entry */ + + /* !! We are now on the RTOS system stack !! */ + + /* Set up PS for C, enable interrupts above this level and clear EXCM. */ + #ifdef __XTENSA_CALL0_ABI__ + movi a0, PS_INTLEVEL(3) | PS_UM + #else + movi a0, PS_INTLEVEL(3) | PS_UM | PS_WOE + #endif + wsr a0, PS + rsync + + /* OK to call C code at this point, dispatch user ISRs */ + + dispatch_c_isr 3 XCHAL_INTLEVEL3_MASK + + /* Done handling interrupts, transfer control to OS */ + call0 XT_RTOS_INT_EXIT /* does not return directly here */ + + /* + Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT + on entry and used to return to a thread or interrupted interrupt handler. + */ + .global _xt_medint3_exit + .type _xt_medint3_exit,@function + .align 4 +_xt_medint3_exit: + /* Restore only level-specific regs (the rest were already restored) */ + l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */ + wsr a0, EPS_3 + l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */ + wsr a0, EPC_3 + l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */ + l32i sp, sp, XT_STK_A1 /* remove interrupt stack frame */ + rsync /* ensure EPS and EPC written */ + rfi 3 + +#endif /* Level 3 */ + +#if XCHAL_EXCM_LEVEL >= 4 + + .begin literal_prefix .Level4InterruptVector + .section .Level4InterruptVector.text, "ax" + .global _Level4Vector + .type _Level4Vector,@function + .align 4 +_Level4Vector: + wsr a0, EXCSAVE_4 /* preserve a0 */ + call0 _xt_medint4 /* load interrupt handler */ + + .end literal_prefix + + .section .iram1,"ax" + .type _xt_medint4,@function + .align 4 +_xt_medint4: + mov a0, sp /* sp == a1 */ + addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */ + s32i a0, sp, XT_STK_A1 /* save pre-interrupt SP */ + rsr a0, EPS_4 /* save interruptee's PS */ + s32i a0, sp, XT_STK_PS + rsr a0, EPC_4 /* save interruptee's PC */ + s32i a0, sp, XT_STK_PC + rsr a0, EXCSAVE_4 /* save interruptee's a0 */ + s32i a0, sp, XT_STK_A0 + movi a0, _xt_medint4_exit /* save exit point for dispatch */ + s32i a0, sp, XT_STK_EXIT + + /* EXCSAVE_4 should now be free to use. Use it to keep a copy of the + current stack pointer that points to the exception frame (XT_STK_FRAME).*/ + #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) + #ifdef XT_DEBUG_BACKTRACE + #ifndef __XTENSA_CALL0_ABI__ + mov a0, sp + wsr a0, EXCSAVE_4 + #endif + #endif + #endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */ + + + /* Save rest of interrupt context and enter RTOS. */ + call0 XT_RTOS_INT_ENTER /* common RTOS interrupt entry */ + + /* !! We are now on the RTOS system stack !! */ + + /* Set up PS for C, enable interrupts above this level and clear EXCM. */ + #ifdef __XTENSA_CALL0_ABI__ + movi a0, PS_INTLEVEL(4) | PS_UM + #else + movi a0, PS_INTLEVEL(4) | PS_UM | PS_WOE + #endif + wsr a0, PS + rsync + + /* OK to call C code at this point, dispatch user ISRs */ + + dispatch_c_isr 4 XCHAL_INTLEVEL4_MASK + + /* Done handling interrupts, transfer control to OS */ + call0 XT_RTOS_INT_EXIT /* does not return directly here */ + + /* + Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT + on entry and used to return to a thread or interrupted interrupt handler. + */ + .global _xt_medint4_exit + .type _xt_medint4_exit,@function + .align 4 +_xt_medint4_exit: + /* Restore only level-specific regs (the rest were already restored) */ + l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */ + wsr a0, EPS_4 + l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */ + wsr a0, EPC_4 + l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */ + l32i sp, sp, XT_STK_A1 /* remove interrupt stack frame */ + rsync /* ensure EPS and EPC written */ + rfi 4 + +#endif /* Level 4 */ + +#if XCHAL_EXCM_LEVEL >= 5 + + .begin literal_prefix .Level5InterruptVector + .section .Level5InterruptVector.text, "ax" + .global _Level5Vector + .type _Level5Vector,@function + .align 4 +_Level5Vector: + wsr a0, EXCSAVE_5 /* preserve a0 */ + call0 _xt_medint5 /* load interrupt handler */ + + .end literal_prefix + + .section .iram1,"ax" + .type _xt_medint5,@function + .align 4 +_xt_medint5: + mov a0, sp /* sp == a1 */ + addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */ + s32i a0, sp, XT_STK_A1 /* save pre-interrupt SP */ + rsr a0, EPS_5 /* save interruptee's PS */ + s32i a0, sp, XT_STK_PS + rsr a0, EPC_5 /* save interruptee's PC */ + s32i a0, sp, XT_STK_PC + rsr a0, EXCSAVE_5 /* save interruptee's a0 */ + s32i a0, sp, XT_STK_A0 + movi a0, _xt_medint5_exit /* save exit point for dispatch */ + s32i a0, sp, XT_STK_EXIT + + /* EXCSAVE_5 should now be free to use. Use it to keep a copy of the + current stack pointer that points to the exception frame (XT_STK_FRAME).*/ + #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) + #ifdef XT_DEBUG_BACKTRACE + #ifndef __XTENSA_CALL0_ABI__ + mov a0, sp + wsr a0, EXCSAVE_5 + #endif + #endif + #endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */ + + /* Save rest of interrupt context and enter RTOS. */ + call0 XT_RTOS_INT_ENTER /* common RTOS interrupt entry */ + + /* !! We are now on the RTOS system stack !! */ + + /* Set up PS for C, enable interrupts above this level and clear EXCM. */ + #ifdef __XTENSA_CALL0_ABI__ + movi a0, PS_INTLEVEL(5) | PS_UM + #else + movi a0, PS_INTLEVEL(5) | PS_UM | PS_WOE + #endif + wsr a0, PS + rsync + + /* OK to call C code at this point, dispatch user ISRs */ + + dispatch_c_isr 5 XCHAL_INTLEVEL5_MASK + + /* Done handling interrupts, transfer control to OS */ + call0 XT_RTOS_INT_EXIT /* does not return directly here */ + + /* + Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT + on entry and used to return to a thread or interrupted interrupt handler. + */ + .global _xt_medint5_exit + .type _xt_medint5_exit,@function + .align 4 +_xt_medint5_exit: + /* Restore only level-specific regs (the rest were already restored) */ + l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */ + wsr a0, EPS_5 + l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */ + wsr a0, EPC_5 + l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */ + l32i sp, sp, XT_STK_A1 /* remove interrupt stack frame */ + rsync /* ensure EPS and EPC written */ + rfi 5 + +#endif /* Level 5 */ + +#if XCHAL_EXCM_LEVEL >= 6 + + .begin literal_prefix .Level6InterruptVector + .section .Level6InterruptVector.text, "ax" + .global _Level6Vector + .type _Level6Vector,@function + .align 4 +_Level6Vector: + wsr a0, EXCSAVE_6 /* preserve a0 */ + call0 _xt_medint6 /* load interrupt handler */ + + .end literal_prefix + + .section .iram1,"ax" + .type _xt_medint6,@function + .align 4 +_xt_medint6: + mov a0, sp /* sp == a1 */ + addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */ + s32i a0, sp, XT_STK_A1 /* save pre-interrupt SP */ + rsr a0, EPS_6 /* save interruptee's PS */ + s32i a0, sp, XT_STK_PS + rsr a0, EPC_6 /* save interruptee's PC */ + s32i a0, sp, XT_STK_PC + rsr a0, EXCSAVE_6 /* save interruptee's a0 */ + s32i a0, sp, XT_STK_A0 + movi a0, _xt_medint6_exit /* save exit point for dispatch */ + s32i a0, sp, XT_STK_EXIT + + /* EXCSAVE_6 should now be free to use. Use it to keep a copy of the + current stack pointer that points to the exception frame (XT_STK_FRAME).*/ + #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) + #ifdef XT_DEBUG_BACKTRACE + #ifndef __XTENSA_CALL0_ABI__ + mov a0, sp + wsr a0, EXCSAVE_6 + #endif + #endif + #endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */ + + /* Save rest of interrupt context and enter RTOS. */ + call0 XT_RTOS_INT_ENTER /* common RTOS interrupt entry */ + + /* !! We are now on the RTOS system stack !! */ + + /* Set up PS for C, enable interrupts above this level and clear EXCM. */ + #ifdef __XTENSA_CALL0_ABI__ + movi a0, PS_INTLEVEL(6) | PS_UM + #else + movi a0, PS_INTLEVEL(6) | PS_UM | PS_WOE + #endif + wsr a0, PS + rsync + + /* OK to call C code at this point, dispatch user ISRs */ + + dispatch_c_isr 6 XCHAL_INTLEVEL6_MASK + + /* Done handling interrupts, transfer control to OS */ + call0 XT_RTOS_INT_EXIT /* does not return directly here */ + + /* + Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT + on entry and used to return to a thread or interrupted interrupt handler. + */ + .global _xt_medint6_exit + .type _xt_medint6_exit,@function + .align 4 +_xt_medint6_exit: + /* Restore only level-specific regs (the rest were already restored) */ + l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */ + wsr a0, EPS_6 + l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */ + wsr a0, EPC_6 + l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */ + l32i sp, sp, XT_STK_A1 /* remove interrupt stack frame */ + rsync /* ensure EPS and EPC written */ + rfi 6 + +#endif /* Level 6 */ + + +/******************************************************************************* + +HIGH PRIORITY (LEVEL > XCHAL_EXCM_LEVEL) INTERRUPT VECTORS AND HANDLERS + +High priority interrupts are by definition those with priorities greater +than XCHAL_EXCM_LEVEL. This includes non-maskable (NMI). High priority +interrupts cannot interact with the RTOS, that is they must save all regs +they use and not call any RTOS function. + +A further restriction imposed by the Xtensa windowed architecture is that +high priority interrupts must not modify the stack area even logically +"above" the top of the interrupted stack (they need to provide their +own stack or static save area). + +Cadence Design Systems recommends high priority interrupt handlers be coded in assembly +and used for purposes requiring very short service times. + +Here are templates for high priority (level 2+) interrupt vectors. +They assume only one interrupt per level to avoid the burden of identifying +which interrupts at this level are pending and enabled. This allows for +minimum latency and avoids having to save/restore a2 in addition to a0. +If more than one interrupt per high priority level is configured, this burden +is on the handler which in any case must provide a way to save and restore +registers it uses without touching the interrupted stack. + +Each vector goes at a predetermined location according to the Xtensa +hardware configuration, which is ensured by its placement in a special +section known to the Xtensa linker support package (LSP). It performs +the minimum necessary before jumping to the handler in the .text section. + +*******************************************************************************/ + +/* +These stubs just call xt_highintX/xt_nmi to handle the real interrupt. Please define +these in an external assembly source file. If these symbols are not defined anywhere +else, the defaults in xtensa_vector_defaults.S are used. +*/ + +#if XCHAL_NUM_INTLEVELS >=2 && XCHAL_EXCM_LEVEL <2 && XCHAL_DEBUGLEVEL !=2 + + .begin literal_prefix .Level2InterruptVector + .section .Level2InterruptVector.text, "ax" + .global _Level2Vector + .type _Level2Vector,@function + .global xt_highint2 + .align 4 +_Level2Vector: + wsr a0, EXCSAVE_2 /* preserve a0 */ + call0 xt_highint2 /* load interrupt handler */ + + .end literal_prefix + +#endif /* Level 2 */ + +#if XCHAL_NUM_INTLEVELS >=3 && XCHAL_EXCM_LEVEL <3 && XCHAL_DEBUGLEVEL !=3 + + .begin literal_prefix .Level3InterruptVector + .section .Level3InterruptVector.text, "ax" + .global _Level3Vector + .type _Level3Vector,@function + .global xt_highint3 + .align 4 +_Level3Vector: + wsr a0, EXCSAVE_3 /* preserve a0 */ + call0 xt_highint3 /* load interrupt handler */ + /* never returns here - call0 is used as a jump (see note at top) */ + + .end literal_prefix + +#endif /* Level 3 */ + +#if XCHAL_NUM_INTLEVELS >=4 && XCHAL_EXCM_LEVEL <4 && XCHAL_DEBUGLEVEL !=4 + + .begin literal_prefix .Level4InterruptVector + .section .Level4InterruptVector.text, "ax" + .global _Level4Vector + .type _Level4Vector,@function + .global xt_highint4 + .align 4 +_Level4Vector: + wsr a0, EXCSAVE_4 /* preserve a0 */ + call0 xt_highint4 /* load interrupt handler */ + /* never returns here - call0 is used as a jump (see note at top) */ + + .end literal_prefix + +#endif /* Level 4 */ + +#if XCHAL_NUM_INTLEVELS >=5 && XCHAL_EXCM_LEVEL <5 && XCHAL_DEBUGLEVEL !=5 + + .begin literal_prefix .Level5InterruptVector + .section .Level5InterruptVector.text, "ax" + .global _Level5Vector + .type _Level5Vector,@function + .global xt_highint5 + .align 4 +_Level5Vector: + wsr a0, EXCSAVE_5 /* preserve a0 */ + call0 xt_highint5 /* load interrupt handler */ + /* never returns here - call0 is used as a jump (see note at top) */ + + .end literal_prefix + +#endif /* Level 5 */ + +#if XCHAL_NUM_INTLEVELS >=6 && XCHAL_EXCM_LEVEL <6 && XCHAL_DEBUGLEVEL !=6 + + .begin literal_prefix .Level6InterruptVector + .section .Level6InterruptVector.text, "ax" + .global _Level6Vector + .type _Level6Vector,@function + .global xt_highint6 + .align 4 +_Level6Vector: + wsr a0, EXCSAVE_6 /* preserve a0 */ + call0 xt_highint6 /* load interrupt handler */ + /* never returns here - call0 is used as a jump (see note at top) */ + + .end literal_prefix + +#endif /* Level 6 */ + +#if XCHAL_HAVE_NMI + + .begin literal_prefix .NMIExceptionVector + .section .NMIExceptionVector.text, "ax" + .global _NMIExceptionVector + .type _NMIExceptionVector,@function + .global xt_nmi + .align 4 +_NMIExceptionVector: + wsr a0, EXCSAVE + XCHAL_NMILEVEL _ /* preserve a0 */ + call0 xt_nmi /* load interrupt handler */ + /* never returns here - call0 is used as a jump (see note at top) */ + + .end literal_prefix + +#endif /* NMI */ + + +/******************************************************************************* + +WINDOW OVERFLOW AND UNDERFLOW EXCEPTION VECTORS AND ALLOCA EXCEPTION HANDLER + +Here is the code for each window overflow/underflow exception vector and +(interspersed) efficient code for handling the alloca exception cause. +Window exceptions are handled entirely in the vector area and are very +tight for performance. The alloca exception is also handled entirely in +the window vector area so comes at essentially no cost in code size. +Users should never need to modify them and Cadence Design Systems recommends +they do not. + +Window handlers go at predetermined vector locations according to the +Xtensa hardware configuration, which is ensured by their placement in a +special section known to the Xtensa linker support package (LSP). Since +their offsets in that section are always the same, the LSPs do not define +a section per vector. + +These things are coded for XEA2 only (XEA1 is not supported). + +Note on Underflow Handlers: +The underflow handler for returning from call[i+1] to call[i] +must preserve all the registers from call[i+1]'s window. +In particular, a0 and a1 must be preserved because the RETW instruction +will be reexecuted (and may even underflow if an intervening exception +has flushed call[i]'s registers). +Registers a2 and up may contain return values. + +*******************************************************************************/ + +#if XCHAL_HAVE_WINDOWED + + .section .WindowVectors.text, "ax" + +/* +-------------------------------------------------------------------------------- +Window Overflow Exception for Call4. + +Invoked if a call[i] referenced a register (a4-a15) +that contains data from ancestor call[j]; +call[j] had done a call4 to call[j+1]. +On entry here: + window rotated to call[j] start point; + a0-a3 are registers to be saved; + a4-a15 must be preserved; + a5 is call[j+1]'s stack pointer. +-------------------------------------------------------------------------------- +*/ + + .org 0x0 + .global _WindowOverflow4 +_WindowOverflow4: + + s32e a0, a5, -16 /* save a0 to call[j+1]'s stack frame */ + s32e a1, a5, -12 /* save a1 to call[j+1]'s stack frame */ + s32e a2, a5, -8 /* save a2 to call[j+1]'s stack frame */ + s32e a3, a5, -4 /* save a3 to call[j+1]'s stack frame */ + rfwo /* rotates back to call[i] position */ + +/* +-------------------------------------------------------------------------------- +Window Underflow Exception for Call4 + +Invoked by RETW returning from call[i+1] to call[i] +where call[i]'s registers must be reloaded (not live in ARs); +where call[i] had done a call4 to call[i+1]. +On entry here: + window rotated to call[i] start point; + a0-a3 are undefined, must be reloaded with call[i].reg[0..3]; + a4-a15 must be preserved (they are call[i+1].reg[0..11]); + a5 is call[i+1]'s stack pointer. +-------------------------------------------------------------------------------- +*/ + + .org 0x40 + .global _WindowUnderflow4 +_WindowUnderflow4: + + l32e a0, a5, -16 /* restore a0 from call[i+1]'s stack frame */ + l32e a1, a5, -12 /* restore a1 from call[i+1]'s stack frame */ + l32e a2, a5, -8 /* restore a2 from call[i+1]'s stack frame */ + l32e a3, a5, -4 /* restore a3 from call[i+1]'s stack frame */ + rfwu + +/* +-------------------------------------------------------------------------------- +Handle alloca exception generated by interruptee executing 'movsp'. +This uses space between the window vectors, so is essentially "free". +All interruptee's regs are intact except a0 which is saved in EXCSAVE_1, +and PS.EXCM has been set by the exception hardware (can't be interrupted). +The fact the alloca exception was taken means the registers associated with +the base-save area have been spilled and will be restored by the underflow +handler, so those 4 registers are available for scratch. +The code is optimized to avoid unaligned branches and minimize cache misses. +-------------------------------------------------------------------------------- +*/ + + .align 4 + .global _xt_alloca_exc +_xt_alloca_exc: + + rsr a0, WINDOWBASE /* grab WINDOWBASE before rotw changes it */ + rotw -1 /* WINDOWBASE goes to a4, new a0-a3 are scratch */ + rsr a2, PS + extui a3, a2, XCHAL_PS_OWB_SHIFT, XCHAL_PS_OWB_BITS + xor a3, a3, a4 /* bits changed from old to current windowbase */ + rsr a4, EXCSAVE_1 /* restore original a0 (now in a4) */ + slli a3, a3, XCHAL_PS_OWB_SHIFT + xor a2, a2, a3 /* flip changed bits in old window base */ + wsr a2, PS /* update PS.OWB to new window base */ + rsync + + _bbci.l a4, 31, _WindowUnderflow4 + rotw -1 /* original a0 goes to a8 */ + _bbci.l a8, 30, _WindowUnderflow8 + rotw -1 + j _WindowUnderflow12 + +/* +-------------------------------------------------------------------------------- +Window Overflow Exception for Call8 + +Invoked if a call[i] referenced a register (a4-a15) +that contains data from ancestor call[j]; +call[j] had done a call8 to call[j+1]. +On entry here: + window rotated to call[j] start point; + a0-a7 are registers to be saved; + a8-a15 must be preserved; + a9 is call[j+1]'s stack pointer. +-------------------------------------------------------------------------------- +*/ + + .org 0x80 + .global _WindowOverflow8 +_WindowOverflow8: + + s32e a0, a9, -16 /* save a0 to call[j+1]'s stack frame */ + l32e a0, a1, -12 /* a0 <- call[j-1]'s sp + (used to find end of call[j]'s frame) */ + s32e a1, a9, -12 /* save a1 to call[j+1]'s stack frame */ + s32e a2, a9, -8 /* save a2 to call[j+1]'s stack frame */ + s32e a3, a9, -4 /* save a3 to call[j+1]'s stack frame */ + s32e a4, a0, -32 /* save a4 to call[j]'s stack frame */ + s32e a5, a0, -28 /* save a5 to call[j]'s stack frame */ + s32e a6, a0, -24 /* save a6 to call[j]'s stack frame */ + s32e a7, a0, -20 /* save a7 to call[j]'s stack frame */ + rfwo /* rotates back to call[i] position */ + +/* +-------------------------------------------------------------------------------- +Window Underflow Exception for Call8 + +Invoked by RETW returning from call[i+1] to call[i] +where call[i]'s registers must be reloaded (not live in ARs); +where call[i] had done a call8 to call[i+1]. +On entry here: + window rotated to call[i] start point; + a0-a7 are undefined, must be reloaded with call[i].reg[0..7]; + a8-a15 must be preserved (they are call[i+1].reg[0..7]); + a9 is call[i+1]'s stack pointer. +-------------------------------------------------------------------------------- +*/ + + .org 0xC0 + .global _WindowUnderflow8 +_WindowUnderflow8: + + l32e a0, a9, -16 /* restore a0 from call[i+1]'s stack frame */ + l32e a1, a9, -12 /* restore a1 from call[i+1]'s stack frame */ + l32e a2, a9, -8 /* restore a2 from call[i+1]'s stack frame */ + l32e a7, a1, -12 /* a7 <- call[i-1]'s sp + (used to find end of call[i]'s frame) */ + l32e a3, a9, -4 /* restore a3 from call[i+1]'s stack frame */ + l32e a4, a7, -32 /* restore a4 from call[i]'s stack frame */ + l32e a5, a7, -28 /* restore a5 from call[i]'s stack frame */ + l32e a6, a7, -24 /* restore a6 from call[i]'s stack frame */ + l32e a7, a7, -20 /* restore a7 from call[i]'s stack frame */ + rfwu + +/* +-------------------------------------------------------------------------------- +Window Overflow Exception for Call12 + +Invoked if a call[i] referenced a register (a4-a15) +that contains data from ancestor call[j]; +call[j] had done a call12 to call[j+1]. +On entry here: + window rotated to call[j] start point; + a0-a11 are registers to be saved; + a12-a15 must be preserved; + a13 is call[j+1]'s stack pointer. +-------------------------------------------------------------------------------- +*/ + + .org 0x100 + .global _WindowOverflow12 +_WindowOverflow12: + + s32e a0, a13, -16 /* save a0 to call[j+1]'s stack frame */ + l32e a0, a1, -12 /* a0 <- call[j-1]'s sp + (used to find end of call[j]'s frame) */ + s32e a1, a13, -12 /* save a1 to call[j+1]'s stack frame */ + s32e a2, a13, -8 /* save a2 to call[j+1]'s stack frame */ + s32e a3, a13, -4 /* save a3 to call[j+1]'s stack frame */ + s32e a4, a0, -48 /* save a4 to end of call[j]'s stack frame */ + s32e a5, a0, -44 /* save a5 to end of call[j]'s stack frame */ + s32e a6, a0, -40 /* save a6 to end of call[j]'s stack frame */ + s32e a7, a0, -36 /* save a7 to end of call[j]'s stack frame */ + s32e a8, a0, -32 /* save a8 to end of call[j]'s stack frame */ + s32e a9, a0, -28 /* save a9 to end of call[j]'s stack frame */ + s32e a10, a0, -24 /* save a10 to end of call[j]'s stack frame */ + s32e a11, a0, -20 /* save a11 to end of call[j]'s stack frame */ + rfwo /* rotates back to call[i] position */ + +/* +-------------------------------------------------------------------------------- +Window Underflow Exception for Call12 + +Invoked by RETW returning from call[i+1] to call[i] +where call[i]'s registers must be reloaded (not live in ARs); +where call[i] had done a call12 to call[i+1]. +On entry here: + window rotated to call[i] start point; + a0-a11 are undefined, must be reloaded with call[i].reg[0..11]; + a12-a15 must be preserved (they are call[i+1].reg[0..3]); + a13 is call[i+1]'s stack pointer. +-------------------------------------------------------------------------------- +*/ + + .org 0x140 + .global _WindowUnderflow12 +_WindowUnderflow12: + + l32e a0, a13, -16 /* restore a0 from call[i+1]'s stack frame */ + l32e a1, a13, -12 /* restore a1 from call[i+1]'s stack frame */ + l32e a2, a13, -8 /* restore a2 from call[i+1]'s stack frame */ + l32e a11, a1, -12 /* a11 <- call[i-1]'s sp + (used to find end of call[i]'s frame) */ + l32e a3, a13, -4 /* restore a3 from call[i+1]'s stack frame */ + l32e a4, a11, -48 /* restore a4 from end of call[i]'s stack frame */ + l32e a5, a11, -44 /* restore a5 from end of call[i]'s stack frame */ + l32e a6, a11, -40 /* restore a6 from end of call[i]'s stack frame */ + l32e a7, a11, -36 /* restore a7 from end of call[i]'s stack frame */ + l32e a8, a11, -32 /* restore a8 from end of call[i]'s stack frame */ + l32e a9, a11, -28 /* restore a9 from end of call[i]'s stack frame */ + l32e a10, a11, -24 /* restore a10 from end of call[i]'s stack frame */ + l32e a11, a11, -20 /* restore a11 from end of call[i]'s stack frame */ + rfwu + +#endif /* XCHAL_HAVE_WINDOWED */ + + .section .UserEnter.text, "ax" + .global call_user_start + .type call_user_start,@function + .align 4 + .literal_position diff --git a/portable/ThirdParty/KnownIssues.md b/portable/ThirdParty/KnownIssues.md new file mode 100644 index 000000000..593a41115 --- /dev/null +++ b/portable/ThirdParty/KnownIssues.md @@ -0,0 +1,7 @@ +# Known Issues +This document lists the known issues in various FreeRTOS third +party ports. + +## ThirdParty/GCC/ARC_EM_HS +* [Memory Read Protection Violation from Secure MPU on exit from +interrupt](https://github.com/FreeRTOS/FreeRTOS-Kernel/issues/331) diff --git a/portable/ThirdParty/Partner-Supported-Ports b/portable/ThirdParty/Partner-Supported-Ports new file mode 160000 index 000000000..abc22103e --- /dev/null +++ b/portable/ThirdParty/Partner-Supported-Ports @@ -0,0 +1 @@ +Subproject commit abc22103e1e6634b33457d4127bff1ab62f27f90 diff --git a/portable/ThirdParty/README.md b/portable/ThirdParty/README.md new file mode 100644 index 000000000..93a4398b5 --- /dev/null +++ b/portable/ThirdParty/README.md @@ -0,0 +1,51 @@ +# FreeRTOS Third Party Ports + +FreeRTOS third party ports can be supported by the FreeRTOS team, a FreeRTOS +partner or FreeRTOS community members. Depending on who supports it, the support +provided will differ as follows: + +## FreeRTOS Team Supported Third Party FreeRTOS Ports + +Location: https://github.com/FreeRTOS/FreeRTOS-Kernel/tree/main/portable/ThirdParty + +These third party FreeRTOS ports are supported by the FreeRTOS team. For a +FreeRTOS team supported third party FreeRTOS port: + +* The code has been reviewed by the FreeRTOS team. +* FreeRTOS team has access to the hardware and the test results have been + verified by the FreeRTOS team. +* Customer queries as well as bugs are addressed by the FreeRTOS team. +* The code can be included in Long Term Support (LTS) releases. + +A new FreeRTOS port cannot be directly contributed to this location. Instead, +the FreeRTOS team will decide to take ownership of a partner supported or a +community supported FreeRTOS port based on the community interest. + +## Partner Supported FreeRTOS Ports + +Location: https://github.com/FreeRTOS/FreeRTOS-Kernel-Partner-Supported-Ports/tree/main + +These FreeRTOS ports are supported by a FreeRTOS partner. For a partner +supported FreeRTOS port: + +* The code has not been reviewed by the FreeRTOS team. +* FreeRTOS team has not verified the tests results but tests exist and are + reported to be successful by the partner. +* Customer queries as well as bugs are addressed by the partner. + +A new FreeRTOS port can be directly contributed by a partner. The process to +contribute a FreeRTOS port is documented [here](https://github.com/FreeRTOS/FreeRTOS-Kernel-Partner-Supported-Ports/blob/main/README.md). + +## Community Supported FreeRTOS Ports + +Location: https://github.com/FreeRTOS/FreeRTOS-Kernel-Community-Supported-Ports/tree/main + +These FreeRTOS ports are supported by the FreeRTOS community members. For a +community supported FreeRTOS port: + +* The code has not been reviewed by the FreeRTOS team. +* Tests may or may not exist for the FreeRTOS port. +* Customer queries as well as bugs are addressed by the community. + +A new FreeRTOS port can be directly contributed by anyone. The process to +contribute a FreeRTOS port is documented [here](https://github.com/FreeRTOS/FreeRTOS-Kernel-Community-Supported-Ports/blob/main/README.md). diff --git a/portable/ThirdParty/XCC/Xtensa/readme_xtensa.txt b/portable/ThirdParty/XCC/Xtensa/readme_xtensa.txt new file mode 100644 index 000000000..e2ee4307c --- /dev/null +++ b/portable/ThirdParty/XCC/Xtensa/readme_xtensa.txt @@ -0,0 +1,11 @@ + FreeRTOS Port for Xtensa Configurable Processors + ================================================ + +The Xtensa FreeRTOS port has moved and can be found in the +"FreeRTOS-Kernel-Partner-Supported-Ports" submodule of FreeRTOS-Kernel: + +FreeRTOS/Source/portable/ThirdParty/Partner-Supported-Ports/Cadence/Xtensa + +Please see the Xtensa-specific README in this location for more details. + +-End- diff --git a/portable/ThirdParty/xClang/XCOREAI/port.c b/portable/ThirdParty/xClang/XCOREAI/port.c new file mode 100644 index 000000000..ac12aa31a --- /dev/null +++ b/portable/ThirdParty/xClang/XCOREAI/port.c @@ -0,0 +1,293 @@ +/* Copyright (c) 2019, XMOS Ltd, All rights reserved */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include +#include +#include +#include + +static hwtimer_t xKernelTimer; + +uint32_t ulPortYieldRequired[ portMAX_CORE_COUNT ] = { pdFALSE }; + +/* When this port was designed, it was assumed that pxCurrentTCBs would always + exist and that it would always be an array containing pointers to the current + TCBs for each core. In v11, this is not the case; if we are only running one + core, the symbol is pxCurrentTCB instead. Therefore, this port adds a layer + of indirection - we populate this pointer-to-pointer in the RTOS kernel entry + function below. This makes this port agnostic to whether it is running on SMP + or singlecore RTOS. */ +void ** xcorePvtTCBContainer; + +/*-----------------------------------------------------------*/ + +void vIntercoreInterruptISR( void ) +{ + int xCoreID; + +/* debug_printf( "In KCALL: %u\n", ulData ); */ + xCoreID = rtos_core_id_get(); + ulPortYieldRequired[ xCoreID ] = pdTRUE; +} +/*-----------------------------------------------------------*/ + +DEFINE_RTOS_INTERRUPT_CALLBACK( pxKernelTimerISR, pvData ) +{ + uint32_t ulLastTrigger; + uint32_t ulNow; + int xCoreID; + UBaseType_t uxSavedInterruptStatus; + + xCoreID = 0; + + configASSERT( xCoreID == rtos_core_id_get() ); + + /* Need the next interrupt to be scheduled relative to + * the current trigger time, rather than the current + * time. */ + ulLastTrigger = hwtimer_get_trigger_time( xKernelTimer ); + + /* Check to see if the ISR is late. If it is, we don't + * want to schedule the next interrupt to be in the past. */ + ulNow = hwtimer_get_time( xKernelTimer ); + + if( ulNow - ulLastTrigger >= configCPU_CLOCK_HZ / configTICK_RATE_HZ ) + { + ulLastTrigger = ulNow; + } + + ulLastTrigger += configCPU_CLOCK_HZ / configTICK_RATE_HZ; + hwtimer_change_trigger_time( xKernelTimer, ulLastTrigger ); + + #if configUPDATE_RTOS_TIME_FROM_TICK_ISR == 1 + rtos_time_increment( RTOS_TICK_PERIOD( configTICK_RATE_HZ ) ); + #endif + + uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR(); + + if( xTaskIncrementTick() != pdFALSE ) + { + ulPortYieldRequired[ xCoreID ] = pdTRUE; + } + + taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); +} +/*-----------------------------------------------------------*/ + +void vPortYieldOtherCore( int xOtherCoreID ) +{ + int xCoreID; + + /* + * This function must be called from within a critical section. + */ + + xCoreID = rtos_core_id_get(); + +/* debug_printf("%d->%d\n", xCoreID, xOtherCoreID); */ + +/* debug_printf("Yield core %d from %d\n", xOtherCoreID, xCoreID ); */ + + rtos_irq( xOtherCoreID, xCoreID ); +} +/*-----------------------------------------------------------*/ + +static int prvCoreInit( void ) +{ + int xCoreID; + + xCoreID = rtos_core_register(); + debug_printf( "Logical Core %d initializing as FreeRTOS Core %d\n", get_logical_core_id(), xCoreID ); + + asm volatile ( + "ldap r11, kexcept\n\t" + "set kep, r11\n\t" + : + : + : "r11" + ); + + rtos_irq_enable( configNUMBER_OF_CORES ); + + /* + * All threads wait here until all have enabled IRQs + */ + while( rtos_irq_ready() == pdFALSE ) + { + } + + if( xCoreID == 0 ) + { + uint32_t ulNow; + ulNow = hwtimer_get_time( xKernelTimer ); +/* debug_printf( "The time is now (%u)\n", ulNow ); */ + + ulNow += configCPU_CLOCK_HZ / configTICK_RATE_HZ; + + triggerable_setup_interrupt_callback( xKernelTimer, NULL, RTOS_INTERRUPT_CALLBACK( pxKernelTimerISR ) ); + hwtimer_set_trigger_time( xKernelTimer, ulNow ); + triggerable_enable_trigger( xKernelTimer ); + } + + return xCoreID; +} +/*-----------------------------------------------------------*/ + +DEFINE_RTOS_KERNEL_ENTRY( void, vPortStartSchedulerOnCore, void ) +{ + int xCoreID; + + xCoreID = prvCoreInit(); + + #if ( configUSE_CORE_INIT_HOOK == 1 ) + { + extern void vApplicationCoreInitHook( BaseType_t xCoreID ); + + vApplicationCoreInitHook( xCoreID ); + } + #endif + + /* Populate the TCBContainer depending on whether we're singlecore or SMP */ + #if ( configNUMBER_OF_CORES == 1 ) + { + asm volatile ( + "ldaw %0, dp[pxCurrentTCB]\n\t" + : "=r"(xcorePvtTCBContainer) + : /* no inputs */ + : /* no clobbers */ + ); + } + #else + { + asm volatile ( + "ldaw %0, dp[pxCurrentTCBs]\n\t" + : "=r"(xcorePvtTCBContainer) + : /* no inputs */ + : /* no clobbers */ + ); + } + + #endif + + debug_printf( "FreeRTOS Core %d initialized\n", xCoreID ); + + /* + * Restore the context of the first thread + * to run and jump into it. + */ + asm volatile ( + "mov r6, %0\n\t" /* R6 must be the FreeRTOS core ID. In singlecore this is always 0. */ + "ldw r5, dp[xcorePvtTCBContainer]\n\t" /* R5 must be the TCB list which is indexed by R6 */ + "bu _freertos_restore_ctx\n\t" + : /* no outputs */ + : "r" ( xCoreID ) + : "r5", "r6" + ); +} +/*-----------------------------------------------------------*/ + +/*-----------------------------------------------------------*/ +/* Public functions required by all ports below: */ +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + /*debug_printf( "Top of stack was %p for task %p\n", pxTopOfStack, pxCode ); */ + + /* + * Grow the thread's stack by portTHREAD_CONTEXT_STACK_GROWTH + * so we can push the context onto it. + */ + pxTopOfStack -= portTHREAD_CONTEXT_STACK_GROWTH; + + uint32_t dp; + uint32_t cp; + + /* + * We need to get the current CP and DP pointers. + */ + asm volatile ( + "ldaw r11, cp[0]\n\t" /* get CP into R11 */ + "mov %0, r11\n\t" /* get R11 (CP) into cp */ + "ldaw r11, dp[0]\n\t" /* get DP into R11 */ + "mov %1, r11\n\t" /* get R11 (DP) into dp */ + : "=r" ( cp ), "=r" ( dp ) /* output 0 is cp, output 1 is dp */ + : /* there are no inputs */ + : "r11" /* R11 gets clobbered */ + ); + + /* + * Push the thread context onto the stack. + * Saved PC will point to the new thread's + * entry pointer. + * Interrupts will default to enabled. + * KEDI is also set to enable dual issue mode + * upon kernel entry. + */ + pxTopOfStack[ 1 ] = ( StackType_t ) pxCode; /* SP[1] := SPC */ + pxTopOfStack[ 2 ] = XS1_SR_IEBLE_MASK + | XS1_SR_KEDI_MASK; /* SP[2] := SSR */ + pxTopOfStack[ 3 ] = 0x00000000; /* SP[3] := SED */ + pxTopOfStack[ 4 ] = 0x00000000; /* SP[4] := ET */ + pxTopOfStack[ 5 ] = dp; /* SP[5] := DP */ + pxTopOfStack[ 6 ] = cp; /* SP[6] := CP */ + pxTopOfStack[ 7 ] = 0x00000000; /* SP[7] := LR */ + pxTopOfStack[ 8 ] = ( StackType_t ) pvParameters; /* SP[8] := R0 */ + pxTopOfStack[ 9 ] = 0x01010101; /* SP[9] := R1 */ + pxTopOfStack[ 10 ] = 0x02020202; /* SP[10] := R2 */ + pxTopOfStack[ 11 ] = 0x03030303; /* SP[11] := R3 */ + pxTopOfStack[ 12 ] = 0x04040404; /* SP[12] := R4 */ + pxTopOfStack[ 13 ] = 0x05050505; /* SP[13] := R5 */ + pxTopOfStack[ 14 ] = 0x06060606; /* SP[14] := R6 */ + pxTopOfStack[ 15 ] = 0x07070707; /* SP[15] := R7 */ + pxTopOfStack[ 16 ] = 0x08080808; /* SP[16] := R8 */ + pxTopOfStack[ 17 ] = 0x09090909; /* SP[17] := R9 */ + pxTopOfStack[ 18 ] = 0x10101010; /* SP[18] := R10 */ + pxTopOfStack[ 19 ] = 0x11111111; /* SP[19] := R11 */ + pxTopOfStack[ 20 ] = 0x00000000; /* SP[20] := vH and vSR */ + memset( &pxTopOfStack[ 21 ], 0, 32 ); /* SP[21 - 28] := vR */ + memset( &pxTopOfStack[ 29 ], 1, 32 ); /* SP[29 - 36] := vD */ + memset( &pxTopOfStack[ 37 ], 2, 32 ); /* SP[37 - 44] := vC */ + + /*debug_printf( "Top of stack is now %p for task %p\n", pxTopOfStack, pxCode ); */ + + /* + * Returns the new top of the stack + */ + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +void vPortStartSMPScheduler( void ); + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + if( ( configNUMBER_OF_CORES > portMAX_CORE_COUNT ) || ( configNUMBER_OF_CORES <= 0 ) ) + { + return pdFAIL; + } + + rtos_locks_initialize(); + xKernelTimer = hwtimer_alloc(); + + vPortStartSMPScheduler(); + + return pdPASS; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Do not implement. */ +} +/*-----------------------------------------------------------*/ diff --git a/portable/ThirdParty/xClang/XCOREAI/port.xc b/portable/ThirdParty/xClang/XCOREAI/port.xc new file mode 100644 index 000000000..926b15086 --- /dev/null +++ b/portable/ThirdParty/xClang/XCOREAI/port.xc @@ -0,0 +1,26 @@ +/* + * port.xc + * + * Created on: Jul 31, 2019 + * Author: mbruno + */ + +//#include "rtos_support.h" + +extern "C" { + +#include "FreeRTOSConfig.h" /* to get configNUMBER_OF_CORES */ +#ifndef configNUMBER_OF_CORES +#define configNUMBER_OF_CORES 1 +#endif + +void __xcore_interrupt_permitted_ugs_vPortStartSchedulerOnCore(void); + +} /* extern "C" */ + +void vPortStartSMPScheduler( void ) +{ + par (int i = 0; i < configNUMBER_OF_CORES; i++) { + __xcore_interrupt_permitted_ugs_vPortStartSchedulerOnCore(); + } +} diff --git a/portable/ThirdParty/xClang/XCOREAI/portasm.S b/portable/ThirdParty/xClang/XCOREAI/portasm.S new file mode 100644 index 000000000..64b7b9d9a --- /dev/null +++ b/portable/ThirdParty/xClang/XCOREAI/portasm.S @@ -0,0 +1,186 @@ +// Copyright (c) 2020, XMOS Ltd, All rights reserved + +#include "rtos_support_rtos_config.h" + +/* The FreeRTOS interrupt code calls vTaskSwitchContext. +Therfore it must be added to the rtos_isr group with the +rest of the ISR callback functions. */ +.weak _fptrgroup.rtos_isr.nstackwords.group +.add_to_set _fptrgroup.rtos_isr.nstackwords.group, vTaskSwitchContext.nstackwords, vTaskSwitchContext + +.globl kexcept +.align 128 /* align the kernel section to 128 bytes */ +.type kexcept,@function +.issue_mode dual +.cc_top kexcept.function, kexcept +kexcept: + bu _DoException /* This symbol is generated by the toolchain and */ + /* provides graceful exception handling */ + +_yield: + {set sp, r4 /* Restore the task's SP to save the rest of its context. */ + get r11, id} /* Get the logical core ID into r11. */ + ldaw r0, dp[rtos_core_map] + ldw r0, r0[r11] /* Translate to the RTOS core ID into r0 */ + bu _yield_continue /* Skip the ulPortYieldRequired check and jump right to */ + /* the context save and switch. Also skips saving SPC */ + /* since the kcall handler has already saved it. */ + +.align 64 +kcall: + /* start saving the thread's context */ + extsp RTOS_SUPPORT_INTERRUPT_STACK_GROWTH + stw r1, sp[9] + stw r11, sp[19] + + /* kcall sets SPC to the instruction of the kcall rather than the next instruction */ + /* so we need to adjust the SPC value that we save to the stack: */ + stw spc, sp[1] /* save the saved program counter onto the stack... */ + ldw r1, sp[1] /* so that we can load it into r1 (which we have already saved). */ + add r1, r1, 4 /* Add 4 to the spc to make it point to the instruction after the kcall. */ + {stw r1, sp[1] /* Now save it to the stack. */ + + /* kcall uses the same common function as interrupt callbacks. */ + /* tell it to call _yield above. */ + ldap r11, _yield} + mov r1, r11 + + /* fall into rtos_interrupt_callback_common */ + +.globl rtos_interrupt_callback_common +rtos_interrupt_callback_common: + /* This is the body of the RTOS _xcore_c_interrupt_callback_XXX functions. */ + /* r1 = interrupt_callback_t function */ + + /* Save the thread's context onto the thread's stack. */ + /* The stack was extended for this by the wrapper function. */ + /* Begin only by saving some registers. The rest will be saved */ + /* later if vTaskSwitchContext() needs to be called. */ + /* DP and CP need to be saved because these are restored for the kernel ISR. */ + /* LR needs to be saved because it is clobbered when calling the callback. */ + /* r0-r3, and r11 need to be saved because the callback may clobber them. */ + /* r4 is saved because it is used here to hold the task SP. */ + + stw dp, sp[5] + stw cp, sp[6] + stw lr, sp[7] + stw r0, sp[8] +/*stw r1, sp[9] already saved by the wrapper function. */ + stw r2, sp[10] + stw r3, sp[11] + {stw r4, sp[12] +/*stw r11, sp[19] already saved by the wrapper function. */ + + ldaw r4, sp[0]} /* Get value of current stackpointer into r4. */ + + {kentsp 0 /* switch to the kernel stack. */ + /* The value 0 is safe to use since we don't need the SP */ + /* that it saves to KSP[0]. We already have it in r4. */ + + get r11, ed} /* Get the event data... */ + ldw dp, sp[3] /* (Restore CP and DP required for the RTOS ISR */ + ldw cp, sp[4] /* in case the active thread has modified them.) */ + {mov r0, r11 /* ...into the first argument for the callback function, */ + bla r1} /* and call the callback function. */ + + {set sp, r4 /* Restore the task's SP now. */ + + get r11, id} /* Get the logical core ID into r11. */ + ldaw r0, dp[rtos_core_map] + ldw r0, r0[r11] /* Translate to the RTOS core ID into r0. */ + ldaw r2, dp[ulPortYieldRequired] /* Get the yield required array into r2. */ + ldw r1, r2[r0] /* Is a yield required for this core? */ + {bf r1, _freertos_restore_ctx_partial /* If not, restore the context now. */ + ldc r1, 0} + stw r1, r2[r0] /* Otherwise, clear the yield required flag. */ + + /* Save the rest of the current task's context. */ + + /* Save standard xs2 regs */ + stw spc, sp[1] +_yield_continue: + stw ssr, sp[2] + stw sed, sp[3] + stw et, sp[4] + stw r5, sp[13] + stw r6, sp[14] + stw r7, sp[15] + stw r8, sp[16] + stw r9, sp[17] + stw r10, sp[18] +#if 1 + /* Save VPU status and headroom */ + vgetc r11 + {stw r11, sp[20] + /* Save VPU regs */ + ldaw r11, sp[21]} + {vstr r11[0] + ldaw r11, sp[29]} + {vstd r11[0] + ldaw r11, sp[37]} + vstc r11[0] +#endif + ldw r5, dp[xcorePvtTCBContainer] + ldw r1, r5[r0] /* Get this core's current TCB pointer into r1. */ + stw r4, r1[0x0] /* Save the current task's SP to the first */ + /* word (top of stack) in the current TCB. */ + + {kentsp 0 /* switch back to the kernel stack. */ + + mov r6, r0} /* copy the RTOS core ID into r6 so we don't lose it. */ + ldap r11, vTaskSwitchContext + bla r11 /* Finally call vTaskSwitchContext(core_id) now that the task's */ + /* entire context is saved. Note the core id in r0 is the argument. */ + +//krestsp 0 /* unnecessary since KSP is already set and the SP */ + /* is being restored next from the current TCB. */ + +.globl _freertos_restore_ctx +_freertos_restore_ctx: + + ldw r0, r5[r6] /* get this core's current TCB pointer into r0 */ + ldw r0, r0[0x0] /* Get the top of the stack from the current TCB... */ + set sp, r0 /* into the stack pointer register. */ + + /* Restore the current task's context */ +#if 1 + /* Restore VPU regs */ + ldaw r11, sp[37] + {vldc r11[0] + ldaw r11, sp[29]} + {vldd r11[0] + ldaw r11, sp[21]} + vldr r11[0] + /* Restore VPU status and headroom */ + ldw r11, sp[20] + vsetc r11 +#endif + /* Restore standard xs2 regs */ + ldw spc, sp[1] + ldw ssr, sp[2] + ldw sed, sp[3] + ldw et, sp[4] + ldw r5, sp[13] + ldw r6, sp[14] + ldw r7, sp[15] + ldw r8, sp[16] + ldw r9, sp[17] + ldw r10, sp[18] +_freertos_restore_ctx_partial: + ldw dp, sp[5] + ldw cp, sp[6] + ldw lr, sp[7] + ldw r0, sp[8] + ldw r1, sp[9] + ldw r2, sp[10] + ldw r3, sp[11] + ldw r4, sp[12] + {ldw r11, sp[19] + + /* shrink the stack by the size of the context just restored */ + ldaw sp, sp[RTOS_SUPPORT_INTERRUPT_STACK_GROWTH]} + + kret /* exit kernel mode and return to the thread */ + +.cc_bottom kexcept.function + diff --git a/portable/ThirdParty/xClang/XCOREAI/portmacro.h b/portable/ThirdParty/xClang/XCOREAI/portmacro.h new file mode 100644 index 000000000..088133314 --- /dev/null +++ b/portable/ThirdParty/xClang/XCOREAI/portmacro.h @@ -0,0 +1,212 @@ +/* Copyright (c) 2020, XMOS Ltd, All rights reserved */ + +#ifndef PORTMACRO_H + #define PORTMACRO_H + + #ifndef __ASSEMBLER__ + +/* Inclusion of xc1.h will result in clock being defined as a type. + * By default, FreeRTOS will require standard time.h, where clock is a function. + */ + #ifndef USE_XCORE_CLOCK_TYPE + #define _clock_defined + #endif + + #include + #include "rtos_support.h" + + #ifdef __cplusplus + extern "C" { + #endif + +/* Type definitions. */ + #define portSTACK_TYPE uint32_t + typedef portSTACK_TYPE StackType_t; + typedef double portDOUBLE; + typedef int32_t BaseType_t; + typedef uint32_t UBaseType_t; + + #define portBASE_TYPE BaseType_t + + #if ( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff + #else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + #endif +/*-----------------------------------------------------------*/ + + #endif /* __ASSEMBLER__ */ + +/* Architecture specifics. These can be used by assembly files as well. */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 + #define portCRITICAL_NESTING_IN_TCB 1 + #define portMAX_CORE_COUNT 8 + #ifndef configNUMBER_OF_CORES + #define configNUMBER_OF_CORES 1 + #endif + +/* This may be set to zero in the config file if the rtos_time + * functions are not needed or if it is incremented elsewhere. */ + #ifndef configUPDATE_RTOS_TIME_FROM_TICK_ISR + #define configUPDATE_RTOS_TIME_FROM_TICK_ISR 1 + #endif + +/* + * When entering an ISR we need to grow the stack by one more word than + * we actually need to save the thread context. This is because there are + * some functions, written in assembly *cough* memcpy() *cough*, that think + * it is OK to store words at SP[0]. Therefore the ISR must leave SP[0] alone + * even though it is normally not necessary to do so. + */ + #define portTHREAD_CONTEXT_STACK_GROWTH RTOS_SUPPORT_INTERRUPT_STACK_GROWTH + + #ifndef __ASSEMBLER__ + +/* Check validity of number of cores specified in config */ + #if ( configNUMBER_OF_CORES < 1 || portMAX_CORE_COUNT < configNUMBER_OF_CORES ) + #error "Invalid number of cores specified in config!" + #endif + + #define portMEMORY_BARRIER() RTOS_MEMORY_BARRIER() + #define portTASK_STACK_DEPTH( pxTaskCode ) RTOS_THREAD_STACK_SIZE( pxTaskCode ) +/*-----------------------------------------------------------*/ + +/* Scheduler utilities. */ + #define portYIELD() asm volatile ( "KCALLI_lu6 0" ::: "memory" ) + + #define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + extern uint32_t ulPortYieldRequired[ portMAX_CORE_COUNT ]; \ + ulPortYieldRequired[ portGET_CORE_ID() ] = pdTRUE; \ + } \ + } while( 0 ) + + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/* SMP utilities. */ + #define portGET_CORE_ID() rtos_core_id_get() + + void vPortYieldOtherCore( int xOtherCoreID ); + #define portYIELD_CORE( x ) vPortYieldOtherCore( x ) +/*-----------------------------------------------------------*/ + +/* Architecture specific optimisations. */ + #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif + + #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __builtin_clz( uxReadyPriorities ) ) + + #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* Critical section management. */ + + #define portGET_INTERRUPT_STATE() rtos_interrupt_mask_get() + +/* + * This differs from the standard portDISABLE_INTERRUPTS() + * in that it also returns what the interrupt state was + * before it disabling interrupts. + */ + #define portDISABLE_INTERRUPTS() rtos_interrupt_mask_all() + + #define portENABLE_INTERRUPTS() rtos_interrupt_unmask_all() + +/* + * Port set interrupt mask and clear interrupt mask. + */ + #define portSET_INTERRUPT_MASK() rtos_interrupt_mask_all() + #define portCLEAR_INTERRUPT_MASK( ulState ) rtos_interrupt_mask_set( ulState ) + +/* + * Will enable interrupts if ulState is non-zero. + */ + #define portRESTORE_INTERRUPTS( ulState ) rtos_interrupt_mask_set( ulState ) + +/* + * Returns non-zero if currently running in an + * ISR or otherwise in kernel mode. + */ + #define portCHECK_IF_IN_ISR() rtos_isr_running() + + #define portASSERT_IF_IN_ISR() configASSERT( portCHECK_IF_IN_ISR() == 0 ) + + #define portGET_ISR_LOCK( xCoreID ) do{ ( void )( xCoreID ); rtos_lock_acquire( 0 ); } while( 0 ) + #define portRELEASE_ISR_LOCK( xCoreID ) do{ ( void )( xCoreID ); rtos_lock_release( 0 ); } while( 0 ) + #define portGET_TASK_LOCK( xCoreID ) do{ ( void )( xCoreID ); rtos_lock_acquire( 1 ); } while( 0 ) + #define portRELEASE_TASK_LOCK( xCoreID ) do{ ( void )( xCoreID ); rtos_lock_release( 1 ); } while( 0 ) + + + void vTaskEnterCritical( void ); + void vTaskExitCritical( void ); + #define portENTER_CRITICAL() vTaskEnterCritical() + #define portEXIT_CRITICAL() vTaskExitCritical() + + extern UBaseType_t vTaskEnterCriticalFromISR( void ); + extern void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus ); + #define portENTER_CRITICAL_FROM_ISR vTaskEnterCriticalFromISR + #define portEXIT_CRITICAL_FROM_ISR vTaskExitCriticalFromISR + +/*-----------------------------------------------------------*/ + +/* Runtime stats support */ + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + int xscope_gettime( void ); + #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() /* nothing needed here */ + #define portGET_RUN_TIME_COUNTER_VALUE() xscope_gettime() + #endif +/*-----------------------------------------------------------*/ + +/* Maps sprintf and snprintf to the lite version in lib_rtos_support */ + #if ( configUSE_DEBUG_SPRINTF == 1 ) + #define sprintf( ... ) rtos_sprintf( __VA_ARGS__ ) + #define snprintf( ... ) rtos_snprintf( __VA_ARGS__ ) + #endif + +/* Attribute for the pxCallbackFunction member of the Timer_t struct. + * Required by xcc to calculate stack usage. */ + #define portTIMER_CALLBACK_ATTRIBUTE __attribute__( ( fptrgroup( "timerCallbackGroup" ) ) ) + +/* Timer callback function macros. For xcc this ensures they get added to the timer callback + * group so that stack usage for certain functions in timers.c can be calculated. */ + #define portTIMER_CALLBACK_FUNCTION_PROTO( vFunction, xTimer ) void vFunction( TimerHandle_t xTimer ) + #define portTIMER_CALLBACK_FUNCTION( vFunction, xTimer ) portTIMER_CALLBACK_ATTRIBUTE void vFunction( TimerHandle_t xTimer ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not necessary for to use this port. They are defined so the common demo files + * (which build with all the ports) will build. */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + + + #ifdef __cplusplus +} + #endif + + #endif /* __ASSEMBLER__ */ + +#endif /* PORTMACRO_H */ diff --git a/portable/ThirdParty/xClang/XCOREAI/rtos_support_rtos_config.h b/portable/ThirdParty/xClang/XCOREAI/rtos_support_rtos_config.h new file mode 100644 index 000000000..3e4140903 --- /dev/null +++ b/portable/ThirdParty/xClang/XCOREAI/rtos_support_rtos_config.h @@ -0,0 +1,95 @@ +/* Copyright (c) 2020, XMOS Ltd, All rights reserved */ + +#ifndef RTOS_SUPPORT_RTOS_CONFIG_H_ +#define RTOS_SUPPORT_RTOS_CONFIG_H_ + +/** + * Lets the application know that the RTOS in use is FreeRTOS. + */ +#define RTOS_FREERTOS 1 + +/** + * The number of words to extend the stack by when entering an ISR. + * + * When entering an ISR we need to grow the stack by one more word than + * we actually need to save the thread context. This is because there are + * some functions, written in assembly *cough* memcpy() *cough*, that think + * it is OK to store words at SP[0]. Therefore the ISR must leave SP[0] alone + * even though it is normally not necessary to do so. + */ +#define RTOS_SUPPORT_INTERRUPT_STACK_GROWTH ( 44 + 1 ) + +/** + * The word offset into the stack where R1 is to be stored after it + * is extended when saving a thread's context. + */ +#define RTOS_SUPPORT_INTERRUPT_R1_STACK_OFFSET 9 + +/** + * The word offset into the stack where R11 is to be stored after it + * is extended when saving a thread's context. + */ +#define RTOS_SUPPORT_INTERRUPT_R11_STACK_OFFSET 19 + +/** + * The RTOS provided handler that should run when a + * core receives an intercore interrupt request. + */ +#define RTOS_INTERCORE_INTERRUPT_ISR() \ + do { \ + void vIntercoreInterruptISR( void ); \ + vIntercoreInterruptISR(); \ + } while( 0 ) + +/** + * The number of hardware locks that the RTOS + * requires. For a single core RTOS this could be + * zero. Locks are recursive. + * + * Note that the IRQ routines require a lock and + * will share the first one with the RTOS. + */ +#define RTOS_LOCK_COUNT 2 + +/** + * Remaps all calls to debug_printf() to rtos_printf(). + * When this is on, files should not include both rtos_support.h + * and debug_print.h. + */ +#define RTOS_DEBUG_PRINTF_REMAP 1 + + +#ifdef configENABLE_DEBUG_PRINTF + #if configENABLE_DEBUG_PRINTF + +/* ensure that debug_printf is enabled */ + #ifdef DEBUG_PRINT_ENABLE + #undef DEBUG_PRINT_ENABLE + #endif + #define DEBUG_PRINT_ENABLE 1 + + #ifndef configTASKS_DEBUG + #define configTASKS_DEBUG 0 + #endif + #if configTASKS_DEBUG == 1 + #define DEBUG_PRINT_ENABLE_FREERTOS_TASKS 1 + #else + #define DEBUG_PRINT_DISABLE_FREERTOS_TASKS 1 + #endif + + #else /* configENABLE_DEBUG_PRINTF */ + +/* ensure that debug_printf is disabled */ + #ifdef DEBUG_UNIT + #undef DEBUG_UNIT + #endif + #ifdef DEBUG_PRINT_ENABLE + #undef DEBUG_PRINT_ENABLE + #endif + + #define DEBUG_PRINT_ENABLE 0 + + #endif /* configENABLE_DEBUG_PRINTF */ +#endif /* ifdef configENABLE_DEBUG_PRINTF */ + +#endif /* RTOS_SUPPORT_RTOS_CONFIG_H_ */ diff --git a/portable/WizC/PIC18/Drivers/Tick/Tick.c b/portable/WizC/PIC18/Drivers/Tick/Tick.c new file mode 100644 index 000000000..53c2dbcc7 --- /dev/null +++ b/portable/WizC/PIC18/Drivers/Tick/Tick.c @@ -0,0 +1,139 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* +Changes from V3.0.0 + + ISRcode is pulled inline and portTICKisr() is therefore + deleted from this file. + + + Prescaler logic for Timer1 added to allow for a wider + range of TickRates. + +Changes from V3.0.1 +*/ + +#include +#include + +/* IO port constants. */ +#define portBIT_SET (1) +#define portBIT_CLEAR (0) + +/* + * Hardware setup for the tick. + * We use a compare match on timer1. Depending on MPU-frequency + * and requested tickrate, a prescaled value with a matching + * prescaler are determined. + */ +#define portTIMER_COMPARE_BASE ((APROCFREQ/4)/configTICK_RATE_HZ) + +#if portTIMER_COMPARE_BASE < 0x10000 + #define portTIMER_COMPARE_VALUE (portTIMER_COMPARE_BASE) + #define portTIMER_COMPARE_PS1 (portBIT_CLEAR) + #define portTIMER_COMPARE_PS0 (portBIT_CLEAR) +#elif portTIMER_COMPARE_BASE < 0x20000 + #define portTIMER_COMPARE_VALUE (portTIMER_COMPARE_BASE / 2) + #define portTIMER_COMPARE_PS1 (portBIT_CLEAR) + #define portTIMER_COMPARE_PS0 (portBIT_SET) +#elif portTIMER_COMPARE_BASE < 0x40000 + #define portTIMER_COMPARE_VALUE (portTIMER_COMPARE_BASE / 4) + #define portTIMER_COMPARE_PS1 (portBIT_SET) + #define portTIMER_COMPARE_PS0 (portBIT_CLEAR) +#elif portTIMER_COMPARE_BASE < 0x80000 + #define portTIMER_COMPARE_VALUE (portTIMER_COMPARE_BASE / 8) + #define portTIMER_COMPARE_PS1 (portBIT_SET) + #define portTIMER_COMPARE_PS0 (portBIT_SET) +#else + #error "TickRate out of range" +#endif + +/*-----------------------------------------------------------*/ + +/* + * Setup a timer for a regular tick. + */ +void portSetupTick( void ) +{ + /* + * Interrupts are disabled when this function is called. + */ + + /* + * Setup CCP1 + * Provide the tick interrupt using a compare match on timer1. + */ + + /* + * Set the compare match value. + */ + CCPR1H = ( uint8_t ) ( ( portTIMER_COMPARE_VALUE >> 8 ) & 0xff ); + CCPR1L = ( uint8_t ) ( portTIMER_COMPARE_VALUE & 0xff ); + + /* + * Set Compare Special Event Trigger Mode + */ + bCCP1M3 = portBIT_SET; + bCCP1M2 = portBIT_CLEAR; + bCCP1M1 = portBIT_SET; + bCCP1M0 = portBIT_SET; + + /* + * Enable CCP1 interrupt + */ + bCCP1IE = portBIT_SET; + + /* + * We are only going to use the global interrupt bit, so disable + * interruptpriorities and enable peripheral interrupts. + */ + bIPEN = portBIT_CLEAR; + bPEIE = portBIT_SET; + + /* + * Set up timer1 + * It will produce the system tick. + */ + + /* + * Clear the time count + */ + TMR1H = ( uint8_t ) 0x00; + TMR1L = ( uint8_t ) 0x00; + + /* + * Setup the timer + */ + bRD16 = portBIT_SET; // 16-bit + bT1CKPS1 = portTIMER_COMPARE_PS1; // prescaler + bT1CKPS0 = portTIMER_COMPARE_PS0; // prescaler + bT1OSCEN = portBIT_SET; // Oscillator enable + bT1SYNC = portBIT_SET; // No external clock sync + bTMR1CS = portBIT_CLEAR; // Internal clock + + bTMR1ON = portBIT_SET; // Start timer1 +} diff --git a/portable/WizC/PIC18/Drivers/Tick/isrTick.c b/portable/WizC/PIC18/Drivers/Tick/isrTick.c new file mode 100644 index 000000000..d68f8431f --- /dev/null +++ b/portable/WizC/PIC18/Drivers/Tick/isrTick.c @@ -0,0 +1,79 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* +Changes from V3.0.0 + + ISRcode pulled inline to reduce stack-usage. + + + Added functionality to only call vTaskSwitchContext() once + when handling multiple interruptsources in a single interruptcall. + + + Filename changed to a .c extension to allow stepping through code + using F7. + +Changes from V3.0.1 +*/ + +/* + * ISR for the tick. + * This increments the tick count and, if using the preemptive scheduler, + * performs a context switch. This must be identical to the manual + * context switch in how it stores the context of a task. + */ + +#ifndef _FREERTOS_DRIVERS_TICK_ISRTICK_C +#define _FREERTOS_DRIVERS_TICK_ISRTICK_C + +{ + /* + * Was the interrupt the SystemClock? + */ + if( bCCP1IF && bCCP1IE ) + { + /* + * Reset the interrupt flag + */ + bCCP1IF = 0; + + /* + * Maintain the tick count. + */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* + * Ask for a switch to the highest priority task + * that is ready to run. + */ + uxSwitchRequested = pdTRUE; + } + } +} + +#pragma wizcpp uselib "$__PATHNAME__/Tick.c" + +#endif /* _FREERTOS_DRIVERS_TICK_ISRTICK_C */ diff --git a/Source/portable/WizC/PIC18/Install.bat b/portable/WizC/PIC18/Install.bat similarity index 97% rename from Source/portable/WizC/PIC18/Install.bat rename to portable/WizC/PIC18/Install.bat index 590092856..7259ead3a 100644 --- a/Source/portable/WizC/PIC18/Install.bat +++ b/portable/WizC/PIC18/Install.bat @@ -1,171 +1,172 @@ -@echo off -cls - -SET PACKAGENAME=the FreeRTOS port for fedC and wizC - -echo. -echo Hello, I'm the installationscript for %PACKAGENAME%. -echo. - -:CHECKFEDC - set FED=C:\Program Files\FED\PIC_C - echo. - echo I'm checking your system for fedC - if not exist "%FED%" goto NOFEDC - echo YES, I found a fedC-installation! - goto FOUNDFED -:NOFEDC - echo I could not find a fedC-installation. - - -:CHECKWIZC - set FED=C:\Program Files\FED\PIXIE - echo. - echo I'm checking your system for wizC - if not exist "%FED%" goto NOWIZC - echo YES, I found a wizC-installation! - goto FOUNDFED -:noWIZC - echo I could not find a wizC-installation. - - -:ERROR - echo. - echo. - echo I could not find a FED C-compiler installation on your system. - echo. - echo Perhaps I got confused because you installed fedC or wizC in a non-default directory. - echo If this is the case, please change the path at the top of this install-script. - echo After that rerun the script and I will be happy to try again. - echo. - goto ENDIT - - -:FOUNDFED - echo. - echo. - - set FEDLIBS=%FED%\Libs - set FEDLIBSUSER=%FEDLIBS%\LibsUser - - if exist "%FEDLIBS%" goto INSTALL - echo The FED installationdirectory "%FED%" - echo contains no Libs subdirectory. This is weird! - echo. - echo Installation is aborted, sorry... - goto ENDIT - - -:INSTALL - echo I am about to install %PACKAGENAME% - echo into directory %FEDLIBSUSER% - echo. - echo Press 'enter' to let me do my thing - echo Press 'ctrl-c' to stop me - pause >nul - echo. - echo Installing... - - -:RESET_READONLY - echo. - echo Removing ReadOnly attributes - attrib -R "%FEDLIBSUSER%\libFreeRTOS\Modules\Croutine.c" >nul - attrib -R "%FEDLIBSUSER%\libFreeRTOS\Modules\Port.c" >nul - attrib -R "%FEDLIBSUSER%\libFreeRTOS\Modules\List.c" >nul - attrib -R "%FEDLIBSUSER%\libFreeRTOS\Modules\Queue.c" >nul - attrib -R "%FEDLIBSUSER%\libFreeRTOS\Modules\Tasks.c" >nul - attrib -R "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\Tick.c" >nul - attrib -R "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\isrTick.c" >nul - attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Portmacro.h" >nul - attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Croutine.h" >nul - attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\List.h" >nul - attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Portable.h" >nul - attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Projdefs.h" >nul - attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Queue.h" >nul - attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Semphr.h" >nul - attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Task.h" >nul - attrib -R "%FEDLIBSUSER%\FreeRTOS.h" >nul - echo Done - -:CREATE_DIRECTORIES - echo. - echo Creating directories (if necessary)... - if not exist "%FEDLIBSUSER%" mkdir "%FEDLIBSUSER%" - if not exist "%FEDLIBSUSER%\libFreeRTOS" mkdir "%FEDLIBSUSER%\libFreeRTOS" - if not exist "%FEDLIBSUSER%\libFreeRTOS\Drivers" mkdir "%FEDLIBSUSER%\libFreeRTOS\Drivers" - if not exist "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick" mkdir "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick" - if not exist "%FEDLIBSUSER%\libFreeRTOS\Include" mkdir "%FEDLIBSUSER%\libFreeRTOS\Include" - if not exist "%FEDLIBSUSER%\libFreeRTOS\Modules" mkdir "%FEDLIBSUSER%\libFreeRTOS\Modules" - echo Done - - - echo. - echo Copying Files... -:COPY_MODULES - echo Modules... - copy /V /Y "Port.c" "%FEDLIBSUSER%\libFreeRTOS\Modules\Port.c" >nul - copy /V /Y "..\..\..\Croutine.c" "%FEDLIBSUSER%\libFreeRTOS\Modules\Croutine.c" >nul - copy /V /Y "..\..\..\List.c" "%FEDLIBSUSER%\libFreeRTOS\Modules\List.c" >nul - copy /V /Y "..\..\..\Queue.c" "%FEDLIBSUSER%\libFreeRTOS\Modules\Queue.c" >nul - copy /V /Y "..\..\..\Tasks.c" "%FEDLIBSUSER%\libFreeRTOS\Modules\Tasks.c" >nul - -:COPY_DRIVERS - echo Drivers... - copy /V /Y "Drivers\Tick\Tick.c" "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\Tick.c" >nul - copy /V /Y "Drivers\Tick\isrTick.c" "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\isrTick.c" >nul - -:COPY_HEADERS - echo Headers... - copy /V /Y "portmacro.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Portmacro.h" >nul - copy /V /Y "..\..\..\include\Croutine.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Croutine.h" >nul - copy /V /Y "..\..\..\include\List.h" "%FEDLIBSUSER%\libFreeRTOS\Include\List.h" >nul - copy /V /Y "..\..\..\include\Portable.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Portable.h" >nul - copy /V /Y "..\..\..\include\Projdefs.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Projdefs.h" >nul - copy /V /Y "..\..\..\include\Queue.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Queue.h" >nul - copy /V /Y "..\..\..\include\Semphr.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Semphr.h" >nul - copy /V /Y "..\..\..\include\Task.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Task.h" >nul - copy /V /Y "addFreeRTOS.h" + "..\..\..\include\FreeRTOS.h" "%FEDLIBSUSER%\FreeRTOS.h" >nul - - - echo Done - - -:SET_READONLY - echo. - echo Setting files to ReadOnly - attrib +R "%FEDLIBSUSER%\libFreeRTOS\Modules\Port.c" >nul - attrib +R "%FEDLIBSUSER%\libFreeRTOS\Modules\Croutine.c" >nul - attrib +R "%FEDLIBSUSER%\libFreeRTOS\Modules\List.c" >nul - attrib +R "%FEDLIBSUSER%\libFreeRTOS\Modules\Queue.c" >nul - attrib +R "%FEDLIBSUSER%\libFreeRTOS\Modules\Tasks.c" >nul - attrib +R "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\Tick.c" >nul - attrib +R "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\isrTick.c" >nul - attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Portmacro.h" >nul - attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Croutine.h" >nul - attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\List.h" >nul - attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Portable.h" >nul - attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Projdefs.h" >nul - attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Queue.h" >nul - attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Semphr.h" >nul - attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Task.h" >nul - attrib +R "%FEDLIBSUSER%\FreeRTOS.h" >nul - echo Done - - -:FINISHED - echo. - echo The installation of %PACKAGENAME% is completed. - echo. - echo Please review the installation instructions as additional libraries - echo and fedC/wizC configuration settings may be needed for FreeRTOS - echo to function correctly. - - goto ENDIT - - -:ENDIT - echo. - echo. - echo Press 'enter' to close this window - pause >nul + +@echo off +cls + +SET PACKAGENAME=the FreeRTOS port for fedC and wizC + +echo. +echo Hello, I'm the installationscript for %PACKAGENAME%. +echo. + +:CHECKFEDC + set FED=C:\Program Files\FED\PIC_C + echo. + echo I'm checking your system for fedC + if not exist "%FED%" goto NOFEDC + echo YES, I found a fedC-installation! + goto FOUNDFED +:NOFEDC + echo I could not find a fedC-installation. + + +:CHECKWIZC + set FED=C:\Program Files\FED\PIXIE + echo. + echo I'm checking your system for wizC + if not exist "%FED%" goto NOWIZC + echo YES, I found a wizC-installation! + goto FOUNDFED +:noWIZC + echo I could not find a wizC-installation. + + +:ERROR + echo. + echo. + echo I could not find a FED C-compiler installation on your system. + echo. + echo Perhaps I got confused because you installed fedC or wizC in a non-default directory. + echo If this is the case, please change the path at the top of this install-script. + echo After that rerun the script and I will be happy to try again. + echo. + goto ENDIT + + +:FOUNDFED + echo. + echo. + + set FEDLIBS=%FED%\Libs + set FEDLIBSUSER=%FEDLIBS%\LibsUser + + if exist "%FEDLIBS%" goto INSTALL + echo The FED installationdirectory "%FED%" + echo contains no Libs subdirectory. This is weird! + echo. + echo Installation is aborted, sorry... + goto ENDIT + + +:INSTALL + echo I am about to install %PACKAGENAME% + echo into directory %FEDLIBSUSER% + echo. + echo Press 'enter' to let me do my thing + echo Press 'ctrl-c' to stop me + pause >nul + echo. + echo Installing... + + +:RESET_READONLY + echo. + echo Removing ReadOnly attributes + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Modules\Croutine.c" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Modules\Port.c" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Modules\List.c" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Modules\Queue.c" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Modules\Tasks.c" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\Tick.c" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\isrTick.c" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Portmacro.h" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Croutine.h" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\List.h" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Portable.h" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Projdefs.h" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Queue.h" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Semphr.h" >nul + attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Task.h" >nul + attrib -R "%FEDLIBSUSER%\FreeRTOS.h" >nul + echo Done + +:CREATE_DIRECTORIES + echo. + echo Creating directories (if necessary)... + if not exist "%FEDLIBSUSER%" mkdir "%FEDLIBSUSER%" + if not exist "%FEDLIBSUSER%\libFreeRTOS" mkdir "%FEDLIBSUSER%\libFreeRTOS" + if not exist "%FEDLIBSUSER%\libFreeRTOS\Drivers" mkdir "%FEDLIBSUSER%\libFreeRTOS\Drivers" + if not exist "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick" mkdir "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick" + if not exist "%FEDLIBSUSER%\libFreeRTOS\Include" mkdir "%FEDLIBSUSER%\libFreeRTOS\Include" + if not exist "%FEDLIBSUSER%\libFreeRTOS\Modules" mkdir "%FEDLIBSUSER%\libFreeRTOS\Modules" + echo Done + + + echo. + echo Copying Files... +:COPY_MODULES + echo Modules... + copy /V /Y "Port.c" "%FEDLIBSUSER%\libFreeRTOS\Modules\Port.c" >nul + copy /V /Y "..\..\..\Croutine.c" "%FEDLIBSUSER%\libFreeRTOS\Modules\Croutine.c" >nul + copy /V /Y "..\..\..\List.c" "%FEDLIBSUSER%\libFreeRTOS\Modules\List.c" >nul + copy /V /Y "..\..\..\Queue.c" "%FEDLIBSUSER%\libFreeRTOS\Modules\Queue.c" >nul + copy /V /Y "..\..\..\Tasks.c" "%FEDLIBSUSER%\libFreeRTOS\Modules\Tasks.c" >nul + +:COPY_DRIVERS + echo Drivers... + copy /V /Y "Drivers\Tick\Tick.c" "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\Tick.c" >nul + copy /V /Y "Drivers\Tick\isrTick.c" "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\isrTick.c" >nul + +:COPY_HEADERS + echo Headers... + copy /V /Y "portmacro.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Portmacro.h" >nul + copy /V /Y "..\..\..\include\Croutine.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Croutine.h" >nul + copy /V /Y "..\..\..\include\List.h" "%FEDLIBSUSER%\libFreeRTOS\Include\List.h" >nul + copy /V /Y "..\..\..\include\Portable.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Portable.h" >nul + copy /V /Y "..\..\..\include\Projdefs.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Projdefs.h" >nul + copy /V /Y "..\..\..\include\Queue.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Queue.h" >nul + copy /V /Y "..\..\..\include\Semphr.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Semphr.h" >nul + copy /V /Y "..\..\..\include\Task.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Task.h" >nul + copy /V /Y "addFreeRTOS.h" + "..\..\..\include\FreeRTOS.h" "%FEDLIBSUSER%\FreeRTOS.h" >nul + + + echo Done + + +:SET_READONLY + echo. + echo Setting files to ReadOnly + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Modules\Port.c" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Modules\Croutine.c" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Modules\List.c" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Modules\Queue.c" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Modules\Tasks.c" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\Tick.c" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\isrTick.c" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Portmacro.h" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Croutine.h" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\List.h" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Portable.h" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Projdefs.h" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Queue.h" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Semphr.h" >nul + attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Task.h" >nul + attrib +R "%FEDLIBSUSER%\FreeRTOS.h" >nul + echo Done + + +:FINISHED + echo. + echo The installation of %PACKAGENAME% is completed. + echo. + echo Please review the installation instructions as additional libraries + echo and fedC/wizC configuration settings may be needed for FreeRTOS + echo to function correctly. + + goto ENDIT + + +:ENDIT + echo. + echo. + echo Press 'enter' to close this window + pause >nul diff --git a/portable/WizC/PIC18/addFreeRTOS.h b/portable/WizC/PIC18/addFreeRTOS.h new file mode 100644 index 000000000..386ae9f7e --- /dev/null +++ b/portable/WizC/PIC18/addFreeRTOS.h @@ -0,0 +1,54 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* +Changes from V3.0.0 + +Changes from V3.0.1 + +Changes from V4.0.1 + Uselib pragma added for Croutine.c +*/ + +/* + * The installation script will automatically prepend this file to the default FreeRTOS.h. + */ + +#ifndef WIZC_FREERTOS_H +#define WIZC_FREERTOS_H + +#pragma noheap +#pragma wizcpp expandnl on +#pragma wizcpp searchpath "$__PATHNAME__/libFreeRTOS/Include/" +#pragma wizcpp uselib "$__PATHNAME__/libFreeRTOS/Modules/Croutine.c" +#pragma wizcpp uselib "$__PATHNAME__/libFreeRTOS/Modules/Tasks.c" +#pragma wizcpp uselib "$__PATHNAME__/libFreeRTOS/Modules/Queue.c" +#pragma wizcpp uselib "$__PATHNAME__/libFreeRTOS/Modules/List.c" +#pragma wizcpp uselib "$__PATHNAME__/libFreeRTOS/Modules/Port.c" + +#endif /* WIZC_FREERTOS_H */ diff --git a/portable/WizC/PIC18/port.c b/portable/WizC/PIC18/port.c new file mode 100644 index 000000000..6941ece4f --- /dev/null +++ b/portable/WizC/PIC18/port.c @@ -0,0 +1,318 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* +Changes from V3.2.1 + + CallReturn Depth increased from 8 to 10 levels to accommodate wizC/fedC V12. + +Changes from V3.2.0 + + TBLPTRU is now initialised to zero during the initial stack creation of a new task. This solves + an error on devices with more than 64kB ROM. + +Changes from V3.0.0 + + ucCriticalNesting is now initialised to 0x7F to prevent interrupts from being + handled before the scheduler is started. + +Changes from V3.0.1 +*/ + +/* Scheduler include files. */ +#include +#include + +#include + +/*--------------------------------------------------------------------------- + * Implementation of functions defined in portable.h for the WizC PIC18 port. + *---------------------------------------------------------------------------*/ + +/* + * We require the address of the pxCurrentTCB variable, but don't want to + * know any details of its type. + */ +typedef void TCB_t; +extern volatile TCB_t * volatile pxCurrentTCB; + +/* + * Define minimal-stack constants + * ----- + * FSR's: + * STATUS, WREG, BSR, PRODH, PRODL, FSR0H, FSR0L, + * FSR1H, FSR1L,TABLAT, (TBLPTRU), TBLPTRH, TBLPTRL, + * (PCLATU), PCLATH + * sfr's within parenthesis only on devices > 64kB + * ----- + * Call/Return stack: + * 2 bytes per entry on devices <= 64kB + * 3 bytes per entry on devices > 64kB + * ----- + * Other bytes: + * 2 bytes: FunctionParameter for initial taskcode + * 1 byte : Number of entries on call/return stack + * 1 byte : ucCriticalNesting + * 16 bytes: Free space on stack + */ +#if _ROMSIZE > 0x8000 + #define portSTACK_FSR_BYTES ( 15 ) + #define portSTACK_CALLRETURN_ENTRY_SIZE ( 3 ) +#else + #define portSTACK_FSR_BYTES ( 13 ) + #define portSTACK_CALLRETURN_ENTRY_SIZE ( 2 ) +#endif + +#define portSTACK_MINIMAL_CALLRETURN_DEPTH ( 10 ) +#define portSTACK_OTHER_BYTES ( 20 ) + +uint16_t usCalcMinStackSize = 0; + +/*-----------------------------------------------------------*/ + +/* + * We initialise ucCriticalNesting to the middle value an + * uint8_t can contain. This way portENTER_CRITICAL() + * and portEXIT_CRITICAL() can be called without interrupts + * being enabled before the scheduler starts. + */ +register uint8_t ucCriticalNesting = 0x7F; + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a new task. + * See portSAVE_CONTEXT macro for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +uint8_t ucScratch; + /* + * Get the size of the RAMarea in page 0 used by the compiler + * We do this here already to avoid W-register conflicts. + */ + _Pragma("asm") + movlw OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE + movwf PRODL,ACCESS ; PRODL is used as temp register + _Pragma("asmend") + ucScratch = PRODL; + + /* + * Place a few bytes of known values on the bottom of the stack. + * This is just useful for debugging. + */ +// *pxTopOfStack-- = 0x11; +// *pxTopOfStack-- = 0x22; +// *pxTopOfStack-- = 0x33; + + /* + * Simulate how the stack would look after a call to vPortYield() + * generated by the compiler. + */ + + /* + * First store the function parameters. This is where the task expects + * to find them when it starts running. + */ + *pxTopOfStack-- = ( StackType_t ) ( (( uint16_t ) pvParameters >> 8) & 0x00ff ); + *pxTopOfStack-- = ( StackType_t ) ( ( uint16_t ) pvParameters & 0x00ff ); + + /* + * Next are all the registers that form part of the task context. + */ + *pxTopOfStack-- = ( StackType_t ) 0x11; /* STATUS. */ + *pxTopOfStack-- = ( StackType_t ) 0x22; /* WREG. */ + *pxTopOfStack-- = ( StackType_t ) 0x33; /* BSR. */ + *pxTopOfStack-- = ( StackType_t ) 0x44; /* PRODH. */ + *pxTopOfStack-- = ( StackType_t ) 0x55; /* PRODL. */ + *pxTopOfStack-- = ( StackType_t ) 0x66; /* FSR0H. */ + *pxTopOfStack-- = ( StackType_t ) 0x77; /* FSR0L. */ + *pxTopOfStack-- = ( StackType_t ) 0x88; /* FSR1H. */ + *pxTopOfStack-- = ( StackType_t ) 0x99; /* FSR1L. */ + *pxTopOfStack-- = ( StackType_t ) 0xAA; /* TABLAT. */ +#if _ROMSIZE > 0x8000 + *pxTopOfStack-- = ( StackType_t ) 0x00; /* TBLPTRU. */ +#endif + *pxTopOfStack-- = ( StackType_t ) 0xCC; /* TBLPTRH. */ + *pxTopOfStack-- = ( StackType_t ) 0xDD; /* TBLPTRL. */ +#if _ROMSIZE > 0x8000 + *pxTopOfStack-- = ( StackType_t ) 0xEE; /* PCLATU. */ +#endif + *pxTopOfStack-- = ( StackType_t ) 0xFF; /* PCLATH. */ + + /* + * Next the compiler's scratchspace. + */ + while(ucScratch-- > 0) + { + *pxTopOfStack-- = ( StackType_t ) 0; + } + + /* + * The only function return address so far is the address of the task entry. + * The order is TOSU/TOSH/TOSL. For devices > 64kB, TOSU is put on the + * stack, too. TOSU is always written as zero here because wizC does not allow + * functionpointers to point above 64kB in ROM. + */ +#if _ROMSIZE > 0x8000 + *pxTopOfStack-- = ( StackType_t ) 0; +#endif + *pxTopOfStack-- = ( StackType_t ) ( ( ( uint16_t ) pxCode >> 8 ) & 0x00ff ); + *pxTopOfStack-- = ( StackType_t ) ( ( uint16_t ) pxCode & 0x00ff ); + + /* + * Store the number of return addresses on the hardware stack. + * So far only the address of the task entry point. + */ + *pxTopOfStack-- = ( StackType_t ) 1; + + /* + * The code generated by wizC does not maintain separate + * stack and frame pointers. Therefore the portENTER_CRITICAL macro cannot + * use the stack as per other ports. Instead a variable is used to keep + * track of the critical section nesting. This variable has to be stored + * as part of the task context and is initially set to zero. + */ + *pxTopOfStack-- = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +uint16_t usPortCALCULATE_MINIMAL_STACK_SIZE( void ) +{ + /* + * Fetch the size of compiler's scratchspace. + */ + _Pragma("asm") + movlw OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE + movlb usCalcMinStackSize>>8 + movwf usCalcMinStackSize,BANKED + _Pragma("asmend") + + /* + * Add minimum needed stackspace + */ + usCalcMinStackSize += ( portSTACK_FSR_BYTES ) + + ( portSTACK_MINIMAL_CALLRETURN_DEPTH * portSTACK_CALLRETURN_ENTRY_SIZE ) + + ( portSTACK_OTHER_BYTES ); + + return(usCalcMinStackSize); +} + +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + extern void portSetupTick( void ); + + /* + * Setup a timer for the tick ISR for the preemptive scheduler. + */ + portSetupTick(); + + /* + * Restore the context of the first task to run. + */ + portRESTORE_CONTEXT(); + + /* + * This point should never be reached during execution. + */ + return pdTRUE; +} + +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* + * It is unlikely that the scheduler for the PIC port will get stopped + * once running. When called a reset is done which is probably the + * most valid action. + */ + _Pragma(asmline reset); +} + +/*-----------------------------------------------------------*/ + +/* + * Manual context switch. This is similar to the tick context switch, + * but does not increment the tick count. It must be identical to the + * tick context switch in how it stores the stack of a task. + */ +void vPortYield( void ) +{ + /* + * Save the context of the current task. + */ + portSAVE_CONTEXT( portINTERRUPTS_UNCHANGED ); + + /* + * Switch to the highest priority task that is ready to run. + */ + vTaskSwitchContext(); + + /* + * Start executing the task we have just switched to. + */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + void *pvPortMalloc( uint16_t usWantedSize ) + { + void *pvReturn; + + vTaskSuspendAll(); + { + pvReturn = malloc( ( malloc_t ) usWantedSize ); + } + xTaskResumeAll(); + + return pvReturn; + } + +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +/*-----------------------------------------------------------*/ + +#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + void vPortFree( void *pv ) + { + if( pv ) + { + vTaskSuspendAll(); + { + free( pv ); + } + xTaskResumeAll(); + } + } + +#endif /* configSUPPORT_DYNAMIC_ALLOCATION */ diff --git a/portable/WizC/PIC18/portmacro.h b/portable/WizC/PIC18/portmacro.h new file mode 100644 index 000000000..abeb955d0 --- /dev/null +++ b/portable/WizC/PIC18/portmacro.h @@ -0,0 +1,425 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* +Changes from V3.0.0 + +Changes from V3.0.1 +*/ +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#if !defined(_SERIES) || _SERIES != 18 + #error "WizC supports FreeRTOS on the Microchip PIC18-series only" +#endif + +#if !defined(QUICKCALL) || QUICKCALL != 1 + #error "QuickCall must be enabled (see ProjectOptions/Optimisations)" +#endif + +#include +#include + +#define portCHAR char +#define portFLOAT float +#define portDOUBLE portFLOAT +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint8_t +#define portBASE_TYPE char + +typedef portSTACK_TYPE StackType_t; +typedef signed char BaseType_t; +typedef unsigned char UBaseType_t; + + +#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFF ) +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) ( 0xFFFFFFFFUL ) +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif + +#define portBYTE_ALIGNMENT 1 + +/*-----------------------------------------------------------*/ + +/* + * Constant used for context switch macro when we require the interrupt + * enable state to be forced when the interrupted task is switched back in. + */ +#define portINTERRUPTS_FORCED (0x01) + +/* + * Constant used for context switch macro when we require the interrupt + * enable state to be unchanged when the interrupted task is switched back in. + */ +#define portINTERRUPTS_UNCHANGED (0x00) + +/* Initial interrupt enable state for newly created tasks. This value is + * used when a task switches in for the first time. + */ +#define portINTERRUPTS_INITIAL_STATE (portINTERRUPTS_FORCED) + +/* + * Macros to modify the global interrupt enable bit in INTCON. + */ +#define portDISABLE_INTERRUPTS() \ + do \ + { \ + bGIE=0; \ + } while(bGIE) // MicroChip recommends this check! + +#define portENABLE_INTERRUPTS() \ + do \ + { \ + bGIE=1; \ + } while(0) + +/*-----------------------------------------------------------*/ + +/* + * Critical section macros. + */ +extern uint8_t ucCriticalNesting; + +#define portNO_CRITICAL_SECTION_NESTING ( ( uint8_t ) 0 ) + +#define portENTER_CRITICAL() \ + do \ + { \ + portDISABLE_INTERRUPTS(); \ + \ + /* \ + * Now interrupts are disabled ucCriticalNesting \ + * can be accessed directly. Increment \ + * ucCriticalNesting to keep a count of how \ + * many times portENTER_CRITICAL() has been called. \ + */ \ + ucCriticalNesting++; \ + } while(0) + +#define portEXIT_CRITICAL() \ + do \ + { \ + if(ucCriticalNesting > portNO_CRITICAL_SECTION_NESTING) \ + { \ + /* \ + * Decrement the nesting count as we are leaving a \ + * critical section. \ + */ \ + ucCriticalNesting--; \ + } \ + \ + /* \ + * If the nesting level has reached zero then \ + * interrupts should be re-enabled. \ + */ \ + if( ucCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } while(0) + +/*-----------------------------------------------------------*/ + +/* + * The minimal stacksize is calculated on the first reference of + * portMINIMAL_STACK_SIZE. Some input to this calculation is + * compile time determined, other input is port-defined (see port.c) + */ +extern uint16_t usPortCALCULATE_MINIMAL_STACK_SIZE( void ); +extern uint16_t usCalcMinStackSize; + +#define portMINIMAL_STACK_SIZE \ + ((usCalcMinStackSize == 0) \ + ? usPortCALCULATE_MINIMAL_STACK_SIZE() \ + : usCalcMinStackSize ) + +/* + * WizC uses a downgrowing stack + */ +#define portSTACK_GROWTH ( -1 ) + +/*-----------------------------------------------------------*/ + +/* + * Macro's that pushes all the registers that make up the context of a task onto + * the stack, then saves the new top of stack into the TCB. TOSU and TBLPTRU + * are only saved/restored on devices with more than 64kB (32k Words) ROM. + * + * The stackpointer is held by WizC in FSR2 and points to the first free byte. + * WizC uses a "downgrowing" stack. There is no framepointer. + * + * We keep track of the interruptstatus using ucCriticalNesting. When this + * value equals zero, interrupts have to be enabled upon exit from the + * portRESTORE_CONTEXT macro. + * + * If this is called from an ISR then the interrupt enable bits must have been + * set for the ISR to ever get called. Therefore we want to save + * ucCriticalNesting with value zero. This means the interrupts will again be + * re-enabled when the interrupted task is switched back in. + * + * If this is called from a manual context switch (i.e. from a call to yield), + * then we want to keep the current value of ucCriticalNesting so it is restored + * with its current value. This allows a yield from within a critical section. + * + * The compiler uses some locations at the bottom of RAM for temporary + * storage. The compiler may also have been instructed to optimize + * function-parameters and local variables to global storage. The compiler + * uses an area called LocOpt for this wizC feature. + * The total overheadstorage has to be saved in it's entirety as part of + * a task context. These macro's store/restore from data address 0x0000 to + * (OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE - 1). + * OVERHEADPAGE0, LOCOPTSIZE and MAXLOCOPTSIZE are compiler-generated + * assembler definitions. + */ + +#define portSAVE_CONTEXT( ucInterruptForced ) \ + do \ + { \ + portDISABLE_INTERRUPTS(); \ + \ + _Pragma("asm") \ + ; \ + ; Push the relevant SFR's onto the task's stack \ + ; \ + movff STATUS,POSTDEC2 \ + movff WREG,POSTDEC2 \ + movff BSR,POSTDEC2 \ + movff PRODH,POSTDEC2 \ + movff PRODL,POSTDEC2 \ + movff FSR0H,POSTDEC2 \ + movff FSR0L,POSTDEC2 \ + movff FSR1H,POSTDEC2 \ + movff FSR1L,POSTDEC2 \ + movff TABLAT,POSTDEC2 \ + if __ROMSIZE > 0x8000 \ + movff TBLPTRU,POSTDEC2 \ + endif \ + movff TBLPTRH,POSTDEC2 \ + movff TBLPTRL,POSTDEC2 \ + if __ROMSIZE > 0x8000 \ + movff PCLATU,POSTDEC2 \ + endif \ + movff PCLATH,POSTDEC2 \ + ; \ + ; Store the compiler-scratch-area as described above. \ + ; \ + movlw OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE \ + clrf FSR0L,ACCESS \ + clrf FSR0H,ACCESS \ + _rtos_S1: \ + movff POSTINC0,POSTDEC2 \ + decfsz WREG,W,ACCESS \ + SMARTJUMP _rtos_S1 \ + ; \ + ; Save the pic call/return-stack belonging to the \ + ; current task by copying it to the task's software- \ + ; stack. We save the hardware stack pointer (which \ + ; is the number of addresses on the stack) in the \ + ; W-register first because we need it later and it \ + ; is modified in the save-loop by executing pop's. \ + ; After the loop the W-register is stored on the \ + ; stack, too. \ + ; \ + movf STKPTR,W,ACCESS \ + bz _rtos_s3 \ + _rtos_S2: \ + if __ROMSIZE > 0x8000 \ + movff TOSU,POSTDEC2 \ + endif \ + movff TOSH,POSTDEC2 \ + movff TOSL,POSTDEC2 \ + pop \ + tstfsz STKPTR,ACCESS \ + SMARTJUMP _rtos_S2 \ + _rtos_s3: \ + movwf POSTDEC2,ACCESS \ + ; \ + ; Next the value for ucCriticalNesting used by the \ + ; task is stored on the stack. When \ + ; (ucInterruptForced == portINTERRUPTS_FORCED), we save \ + ; it as 0 (portNO_CRITICAL_SECTION_NESTING). \ + ; \ + if ucInterruptForced == portINTERRUPTS_FORCED \ + clrf POSTDEC2,ACCESS \ + else \ + movff ucCriticalNesting,POSTDEC2 \ + endif \ + ; \ + ; Save the new top of the software stack in the TCB. \ + ; \ + movff pxCurrentTCB,FSR0L \ + movff pxCurrentTCB+1,FSR0H \ + movff FSR2L,POSTINC0 \ + movff FSR2H,POSTINC0 \ + _Pragma("asmend") \ + } while(0) + +/************************************************************/ + +/* + * This is the reverse of portSAVE_CONTEXT. + */ +#define portRESTORE_CONTEXT() \ + do \ + { \ + _Pragma("asm") \ + ; \ + ; Set FSR0 to point to pxCurrentTCB->pxTopOfStack. \ + ; \ + movff pxCurrentTCB,FSR0L \ + movff pxCurrentTCB+1,FSR0H \ + ; \ + ; De-reference FSR0 to set the address it holds into \ + ; FSR2 (i.e. *( pxCurrentTCB->pxTopOfStack ) ). FSR2 \ + ; is used by wizC as stackpointer. \ + ; \ + movff POSTINC0,FSR2L \ + movff POSTINC0,FSR2H \ + ; \ + ; Next, the value for ucCriticalNesting used by the \ + ; task is retrieved from the stack. \ + ; \ + movff PREINC2,ucCriticalNesting \ + ; \ + ; Rebuild the pic call/return-stack. The number of \ + ; return addresses is the next item on the task stack. \ + ; Save this number in PRODL. Then fetch the addresses \ + ; and store them on the hardwarestack. \ + ; The datasheets say we can't use movff here... \ + ; \ + movff PREINC2,PRODL // Use PRODL as tempregister \ + clrf STKPTR,ACCESS \ + _rtos_R1: \ + push \ + movf PREINC2,W,ACCESS \ + movwf TOSL,ACCESS \ + movf PREINC2,W,ACCESS \ + movwf TOSH,ACCESS \ + if __ROMSIZE > 0x8000 \ + movf PREINC2,W,ACCESS \ + movwf TOSU,ACCESS \ + else \ + clrf TOSU,ACCESS \ + endif \ + decfsz PRODL,F,ACCESS \ + SMARTJUMP _rtos_R1 \ + ; \ + ; Restore the compiler's working storage area to page 0 \ + ; \ + movlw OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE \ + movwf FSR0L,ACCESS \ + clrf FSR0H,ACCESS \ + _rtos_R2: \ + decf FSR0L,F,ACCESS \ + movff PREINC2,INDF0 \ + tstfsz FSR0L,ACCESS \ + SMARTJUMP _rtos_R2 \ + ; \ + ; Restore the sfr's forming the tasks context. \ + ; We cannot yet restore bsr, w and status because \ + ; we need these registers for a final test. \ + ; \ + movff PREINC2,PCLATH \ + if __ROMSIZE > 0x8000 \ + movff PREINC2,PCLATU \ + else \ + clrf PCLATU,ACCESS \ + endif \ + movff PREINC2,TBLPTRL \ + movff PREINC2,TBLPTRH \ + if __ROMSIZE > 0x8000 \ + movff PREINC2,TBLPTRU \ + else \ + clrf TBLPTRU,ACCESS \ + endif \ + movff PREINC2,TABLAT \ + movff PREINC2,FSR1L \ + movff PREINC2,FSR1H \ + movff PREINC2,FSR0L \ + movff PREINC2,FSR0H \ + movff PREINC2,PRODL \ + movff PREINC2,PRODH \ + ; \ + ; The return from portRESTORE_CONTEXT() depends on \ + ; the value of ucCriticalNesting. When it is zero, \ + ; interrupts need to be enabled. This is done via a \ + ; retfie instruction because we need the \ + ; interrupt-enabling and the return to the restored \ + ; task to be uninterruptible. \ + ; Because bsr, status and W are affected by the test \ + ; they are restored after the test. \ + ; \ + movlb ucCriticalNesting>>8 \ + tstfsz ucCriticalNesting,BANKED \ + SMARTJUMP _rtos_R4 \ + _rtos_R3: \ + movff PREINC2,BSR \ + movff PREINC2,WREG \ + movff PREINC2,STATUS \ + retfie 0 ; Return enabling interrupts \ + _rtos_R4: \ + movff PREINC2,BSR \ + movff PREINC2,WREG \ + movff PREINC2,STATUS \ + return 0 ; Return without affecting interrupts \ + _Pragma("asmend") \ + } while(0) + +/*-----------------------------------------------------------*/ + +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + +/*-----------------------------------------------------------*/ + +extern void vPortYield( void ); +#define portYIELD() vPortYield() + +#define portNOP() _Pragma("asm") \ + nop \ + _Pragma("asmend") + +/*-----------------------------------------------------------*/ + +#define portTASK_FUNCTION( xFunction, pvParameters ) \ + void pointed xFunction( void *pvParameters ) \ + _Pragma(asmfunc xFunction) + +#define portTASK_FUNCTION_PROTO portTASK_FUNCTION +/*-----------------------------------------------------------*/ + + +#define volatile +#define register + +#endif /* PORTMACRO_H */ diff --git a/portable/oWatcom/16BitDOS/Flsh186/port.c b/portable/oWatcom/16BitDOS/Flsh186/port.c new file mode 100644 index 000000000..4b900b6a8 --- /dev/null +++ b/portable/oWatcom/16BitDOS/Flsh186/port.c @@ -0,0 +1,246 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* +Changes from V1.00: + + + Call to taskYIELD() from within tick ISR has been replaced by the more + efficient portSWITCH_CONTEXT(). + + ISR function definitions renamed to include the prv prefix. + +Changes from V1.2.0: + + + portRESET_PIC() is now called last thing before the end of the preemptive + tick routine. + +Changes from V2.6.1 + + + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION + macro to be consistent with the later ports. +*/ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the Flashlite 186 + * port. + *----------------------------------------------------------*/ + +#include +#include +#include +#include + +#include "FreeRTOS.h" +#include "task.h" +#include "portasm.h" + +/*lint -e950 Non ANSI reserved words okay in this file only. */ + +#define portTIMER_EOI_TYPE ( 8 ) +#define portRESET_PIC() portOUTPUT_WORD( ( uint16_t ) 0xff22, portTIMER_EOI_TYPE ) +#define portTIMER_INT_NUMBER 0x12 + +#define portTIMER_1_CONTROL_REGISTER ( ( uint16_t ) 0xff5e ) +#define portTIMER_0_CONTROL_REGISTER ( ( uint16_t ) 0xff56 ) +#define portTIMER_INTERRUPT_ENABLE ( ( uint16_t ) 0x2000 ) + +/* Setup the hardware to generate the required tick frequency. */ +static void prvSetTickFrequency( uint32_t ulTickRateHz ); + +/* Set the hardware back to the state as per before the scheduler started. */ +static void prvExitFunction( void ); + +#if configUSE_PREEMPTION == 1 + /* Tick service routine used by the scheduler when preemptive scheduling is + being used. */ + static void __interrupt __far prvPreemptiveTick( void ); +#else + /* Tick service routine used by the scheduler when cooperative scheduling is + being used. */ + static void __interrupt __far prvNonPreemptiveTick( void ); +#endif + +/* Trap routine used by taskYIELD() to manually cause a context switch. */ +static void __interrupt __far prvYieldProcessor( void ); + +/*lint -e956 File scopes necessary here. */ + +/* Set true when the vectors are set so the scheduler will service the tick. */ +static int16_t sSchedulerRunning = pdFALSE; + +/* Points to the original routine installed on the vector we use for manual context switches. This is then used to restore the original routine during prvExitFunction(). */ +static void ( __interrupt __far *pxOldSwitchISR )(); + +/* Used to restore the original DOS context when the scheduler is ended. */ +static jmp_buf xJumpBuf; + +/*lint +e956 */ + +/*-----------------------------------------------------------*/ +BaseType_t xPortStartScheduler( void ) +{ + /* This is called with interrupts already disabled. */ + + /* Remember what was on the interrupts we are going to use + so we can put them back later if required. */ + pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER ); + + /* Put our manual switch (yield) function on a known + vector. */ + _dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor ); + + #if configUSE_PREEMPTION == 1 + { + /* Put our tick switch function on the timer interrupt. */ + _dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick ); + } + #else + { + /* We want the timer interrupt to just increment the tick count. */ + _dos_setvect( portTIMER_INT_NUMBER, prvNonPreemptiveTick ); + } + #endif + + prvSetTickFrequency( configTICK_RATE_HZ ); + + /* Clean up function if we want to return to DOS. */ + if( setjmp( xJumpBuf ) != 0 ) + { + prvExitFunction(); + sSchedulerRunning = pdFALSE; + } + else + { + sSchedulerRunning = pdTRUE; + + /* Kick off the scheduler by setting up the context of the first task. */ + portFIRST_CONTEXT(); + } + + return sSchedulerRunning; +} +/*-----------------------------------------------------------*/ + +/* The tick ISR used depend on whether or not the preemptive or cooperative +kernel is being used. */ +#if configUSE_PREEMPTION == 1 + static void __interrupt __far prvPreemptiveTick( void ) + { + /* Get the scheduler to update the task states following the tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Switch in the context of the next task to be run. */ + portSWITCH_CONTEXT(); + } + + /* Reset the PIC ready for the next time. */ + portRESET_PIC(); + } +#else + static void __interrupt __far prvNonPreemptiveTick( void ) + { + /* Same as preemptive tick, but the cooperative scheduler is being used + so we don't have to switch in the context of the next task. */ + xTaskIncrementTick(); + portRESET_PIC(); + } +#endif +/*-----------------------------------------------------------*/ + +static void __interrupt __far prvYieldProcessor( void ) +{ + /* Switch in the context of the next task to be run. */ + portSWITCH_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Jump back to the processor state prior to starting the + scheduler. This means we are not going to be using a + task stack frame so the task can be deleted. */ + longjmp( xJumpBuf, 1 ); +} +/*-----------------------------------------------------------*/ + +static void prvExitFunction( void ) +{ +const uint16_t usTimerDisable = 0x0000; +uint16_t usTimer0Control; + + /* Interrupts should be disabled here anyway - but no + harm in making sure. */ + portDISABLE_INTERRUPTS(); + if( sSchedulerRunning == pdTRUE ) + { + /* Put back the switch interrupt routines that was in place + before the scheduler started. */ + _dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR ); + } + + /* Disable the timer used for the tick to ensure the scheduler is + not called before restoring interrupts. There was previously nothing + on this timer so there is no old ISR to restore. */ + portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerDisable ); + + /* Restart the DOS tick. */ + usTimer0Control = portINPUT_WORD( portTIMER_0_CONTROL_REGISTER ); + usTimer0Control |= portTIMER_INTERRUPT_ENABLE; + portOUTPUT_WORD( portTIMER_0_CONTROL_REGISTER, usTimer0Control ); + + + portENABLE_INTERRUPTS(); +} +/*-----------------------------------------------------------*/ + +static void prvSetTickFrequency( uint32_t ulTickRateHz ) +{ +const uint16_t usMaxCountRegister = 0xff5a; +const uint16_t usTimerPriorityRegister = 0xff32; +const uint16_t usTimerEnable = 0xC000; +const uint16_t usRetrigger = 0x0001; +const uint16_t usTimerHighPriority = 0x0000; +uint16_t usTimer0Control; + +/* ( CPU frequency / 4 ) / clock 2 max count [inpw( 0xff62 ) = 7] */ + +const uint32_t ulClockFrequency = 0x7f31a0; + +uint32_t ulTimerCount = ulClockFrequency / ulTickRateHz; + + portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerEnable | portTIMER_INTERRUPT_ENABLE | usRetrigger ); + portOUTPUT_WORD( usMaxCountRegister, ( uint16_t ) ulTimerCount ); + portOUTPUT_WORD( usTimerPriorityRegister, usTimerHighPriority ); + + /* Stop the DOS tick - don't do this if you want to maintain a TOD clock. */ + usTimer0Control = portINPUT_WORD( portTIMER_0_CONTROL_REGISTER ); + usTimer0Control &= ~portTIMER_INTERRUPT_ENABLE; + portOUTPUT_WORD( portTIMER_0_CONTROL_REGISTER, usTimer0Control ); +} + + +/*lint +e950 */ diff --git a/portable/oWatcom/16BitDOS/Flsh186/portmacro.h b/portable/oWatcom/16BitDOS/Flsh186/portmacro.h new file mode 100644 index 000000000..efa43611b --- /dev/null +++ b/portable/oWatcom/16BitDOS/Flsh186/portmacro.h @@ -0,0 +1,116 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE long +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE uint16_t +#define portBASE_TYPE short + +typedef portSTACK_TYPE StackType_t; +typedef short BaseType_t; +typedef unsigned short UBaseType_t; + + +#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +void portENTER_CRITICAL( void ); +#pragma aux portENTER_CRITICAL = "pushf" \ + "cli"; + +void portEXIT_CRITICAL( void ); +#pragma aux portEXIT_CRITICAL = "popf"; + +void portDISABLE_INTERRUPTS( void ); +#pragma aux portDISABLE_INTERRUPTS = "cli"; + +void portENABLE_INTERRUPTS( void ); +#pragma aux portENABLE_INTERRUPTS = "sti"; +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portSWITCH_INT_NUMBER 0x80 +#define portYIELD() __asm{ int portSWITCH_INT_NUMBER } +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 2 +#define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */ +#define portNOP() __asm{ nop } +/*-----------------------------------------------------------*/ + +/* Compiler specifics. */ +#define portINPUT_BYTE( xAddr ) inp( xAddr ) +#define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue ) +#define portINPUT_WORD( xAddr ) inpw( xAddr ) +#define portOUTPUT_WORD( xAddr, usValue ) outpw( xAddr, usValue ) +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTMACRO_H */ diff --git a/portable/oWatcom/16BitDOS/PC/port.c b/portable/oWatcom/16BitDOS/PC/port.c new file mode 100644 index 000000000..bbee5ec68 --- /dev/null +++ b/portable/oWatcom/16BitDOS/PC/port.c @@ -0,0 +1,302 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* +Changes from V1.00: + + + Call to taskYIELD() from within tick ISR has been replaced by the more + efficient portSWITCH_CONTEXT(). + + ISR function definitions renamed to include the prv prefix. + +Changes from V1.2.0: + + + prvPortResetPIC() is now called last thing before the end of the + preemptive tick routine. + +Changes from V2.6.1 + + + Replaced the sUsingPreemption variable with the configUSE_PREEMPTION + macro to be consistent with the later ports. + +Changes from V4.0.1 + + + Add function prvSetTickFrequencyDefault() to set the DOS tick back to + its proper value when the scheduler exits. +*/ + +#include +#include +#include +#include +#include + +#include "FreeRTOS.h" +#include "task.h" +#include "portasm.h" + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the industrial + * PC port. + *----------------------------------------------------------*/ + +/*lint -e950 Non ANSI reserved words okay in this file only. */ + +#define portTIMER_INT_NUMBER 0x08 + +/* Setup hardware for required tick interrupt rate. */ +static void prvSetTickFrequency( uint32_t ulTickRateHz ); + +/* Restore hardware to as it was prior to starting the scheduler. */ +static void prvExitFunction( void ); + +/* Either chain to the DOS tick (which itself clears the PIC) or clear the PIC +directly. We chain to the DOS tick as close as possible to the standard DOS +tick rate. */ +static void prvPortResetPIC( void ); + +/* The tick ISR used depends on whether the preemptive or cooperative scheduler +is being used. */ +#if configUSE_PREEMPTION == 1 + /* Tick service routine used by the scheduler when preemptive scheduling is + being used. */ + static void __interrupt __far prvPreemptiveTick( void ); +#else + /* Tick service routine used by the scheduler when cooperative scheduling is + being used. */ + static void __interrupt __far prvNonPreemptiveTick( void ); +#endif +/* Trap routine used by taskYIELD() to manually cause a context switch. */ +static void __interrupt __far prvYieldProcessor( void ); + +/* Set the tick frequency back so the floppy drive works correctly when the +scheduler exits. */ +static void prvSetTickFrequencyDefault( void ); + +/*lint -e956 File scopes necessary here. */ + +/* Used to signal when to chain to the DOS tick, and when to just clear the PIC ourselves. */ +static int16_t sDOSTickCounter; + +/* Set true when the vectors are set so the scheduler will service the tick. */ +static int16_t sSchedulerRunning = pdFALSE; + +/* Points to the original routine installed on the vector we use for manual context switches. This is then used to restore the original routine during prvExitFunction(). */ +static void ( __interrupt __far *pxOldSwitchISR )(); + +/* Points to the original routine installed on the vector we use to chain to the DOS tick. This is then used to restore the original routine during prvExitFunction(). */ +static void ( __interrupt __far *pxOldSwitchISRPlus1 )(); + +/* Used to restore the original DOS context when the scheduler is ended. */ +static jmp_buf xJumpBuf; + +/*lint +e956 */ + +/*-----------------------------------------------------------*/ +BaseType_t xPortStartScheduler( void ) +{ +pxISR pxOriginalTickISR; + + /* This is called with interrupts already disabled. */ + + /* Remember what was on the interrupts we are going to use + so we can put them back later if required. */ + pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER ); + pxOriginalTickISR = _dos_getvect( portTIMER_INT_NUMBER ); + pxOldSwitchISRPlus1 = _dos_getvect( portSWITCH_INT_NUMBER + 1 ); + + prvSetTickFrequency( configTICK_RATE_HZ ); + + /* Put our manual switch (yield) function on a known + vector. */ + _dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor ); + + /* Put the old tick on a different interrupt number so we can + call it when we want. */ + _dos_setvect( portSWITCH_INT_NUMBER + 1, pxOriginalTickISR ); + + #if configUSE_PREEMPTION == 1 + { + /* Put our tick switch function on the timer interrupt. */ + _dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick ); + } + #else + { + /* We want the timer interrupt to just increment the tick count. */ + _dos_setvect( portTIMER_INT_NUMBER, prvNonPreemptiveTick ); + } + #endif + + /* Setup a counter that is used to call the DOS interrupt as close + to it's original frequency as can be achieved given our chosen tick + frequency. */ + sDOSTickCounter = portTICKS_PER_DOS_TICK; + + /* Clean up function if we want to return to DOS. */ + if( setjmp( xJumpBuf ) != 0 ) + { + prvExitFunction(); + sSchedulerRunning = pdFALSE; + } + else + { + sSchedulerRunning = pdTRUE; + + /* Kick off the scheduler by setting up the context of the first task. */ + portFIRST_CONTEXT(); + } + + return sSchedulerRunning; +} +/*-----------------------------------------------------------*/ + +/* The tick ISR used depends on whether the preemptive or cooperative scheduler +is being used. */ +#if configUSE_PREEMPTION == 1 + /* Tick service routine used by the scheduler when preemptive scheduling is + being used. */ + static void __interrupt __far prvPreemptiveTick( void ) + { + /* Get the scheduler to update the task states following the tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Switch in the context of the next task to be run. */ + portSWITCH_CONTEXT(); + } + + /* Reset the PIC ready for the next time. */ + prvPortResetPIC(); + } +#else + static void __interrupt __far prvNonPreemptiveTick( void ) + { + /* Same as preemptive tick, but the cooperative scheduler is being used + so we don't have to switch in the context of the next task. */ + xTaskIncrementTick(); + prvPortResetPIC(); + } +#endif +/*-----------------------------------------------------------*/ + + +static void __interrupt __far prvYieldProcessor( void ) +{ + /* Switch in the context of the next task to be run. */ + portSWITCH_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +static void prvPortResetPIC( void ) +{ + /* We are going to call the DOS tick interrupt at as close a + frequency to the normal DOS tick as possible. */ + + /* WE SHOULD NOT DO THIS IF YIELD WAS CALLED. */ + --sDOSTickCounter; + if( sDOSTickCounter <= 0 ) + { + sDOSTickCounter = ( int16_t ) portTICKS_PER_DOS_TICK; + __asm{ int portSWITCH_INT_NUMBER + 1 }; + } + else + { + /* Reset the PIC as the DOS tick is not being called to + do it. */ + __asm + { + mov al, 20H + out 20H, al + }; + } +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Jump back to the processor state prior to starting the + scheduler. This means we are not going to be using a + task stack frame so the task can be deleted. */ + longjmp( xJumpBuf, 1 ); +} +/*-----------------------------------------------------------*/ + +static void prvExitFunction( void ) +{ +void ( __interrupt __far *pxOriginalTickISR )(); + + /* Interrupts should be disabled here anyway - but no + harm in making sure. */ + portDISABLE_INTERRUPTS(); + if( sSchedulerRunning == pdTRUE ) + { + /* Set the DOS tick back onto the timer ticker. */ + pxOriginalTickISR = _dos_getvect( portSWITCH_INT_NUMBER + 1 ); + _dos_setvect( portTIMER_INT_NUMBER, pxOriginalTickISR ); + prvSetTickFrequencyDefault(); + + /* Put back the switch interrupt routines that was in place + before the scheduler started. */ + _dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR ); + _dos_setvect( portSWITCH_INT_NUMBER + 1, pxOldSwitchISRPlus1 ); + } + /* The tick timer is back how DOS wants it. We can re-enable + interrupts without the scheduler being called. */ + portENABLE_INTERRUPTS(); +} +/*-----------------------------------------------------------*/ + +static void prvSetTickFrequency( uint32_t ulTickRateHz ) +{ +const uint16_t usPIT_MODE = ( uint16_t ) 0x43; +const uint16_t usPIT0 = ( uint16_t ) 0x40; +const uint32_t ulPIT_CONST = ( uint32_t ) 1193180; +const uint16_t us8254_CTR0_MODE3 = ( uint16_t ) 0x36; +uint32_t ulOutput; + + /* Setup the 8245 to tick at the wanted frequency. */ + portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 ); + ulOutput = ulPIT_CONST / ulTickRateHz; + + portOUTPUT_BYTE( usPIT0, ( uint16_t )( ulOutput & ( uint32_t ) 0xff ) ); + ulOutput >>= 8; + portOUTPUT_BYTE( usPIT0, ( uint16_t ) ( ulOutput & ( uint32_t ) 0xff ) ); +} +/*-----------------------------------------------------------*/ + +static void prvSetTickFrequencyDefault( void ) +{ +const uint16_t usPIT_MODE = ( uint16_t ) 0x43; +const uint16_t usPIT0 = ( uint16_t ) 0x40; +const uint16_t us8254_CTR0_MODE3 = ( uint16_t ) 0x36; + + portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 ); + portOUTPUT_BYTE( usPIT0,0 ); + portOUTPUT_BYTE( usPIT0,0 ); +} + + +/*lint +e950 */ diff --git a/portable/oWatcom/16BitDOS/PC/portmacro.h b/portable/oWatcom/16BitDOS/PC/portmacro.h new file mode 100644 index 000000000..99b29dbc7 --- /dev/null +++ b/portable/oWatcom/16BitDOS/PC/portmacro.h @@ -0,0 +1,118 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE uint16_t +#define portBASE_TYPE short + +typedef portSTACK_TYPE StackType_t; +typedef short BaseType_t; +typedef unsigned short UBaseType_t; + + +#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif +/*-----------------------------------------------------------*/ + +/* Critical section definitions. portENTER_CRITICAL() must be defined as a +macro for portable.h to work properly. */ +void portLOCAL_ENTER_CRITICAL( void ); +#pragma aux portLOCAL_ENTER_CRITICAL = "pushf" \ + "cli"; +#define portENTER_CRITICAL() portLOCAL_ENTER_CRITICAL() + +void portEXIT_CRITICAL( void ); +#pragma aux portEXIT_CRITICAL = "popf"; + +void portDISABLE_INTERRUPTS( void ); +#pragma aux portDISABLE_INTERRUPTS = "cli"; + +void portENABLE_INTERRUPTS( void ); +#pragma aux portENABLE_INTERRUPTS = "sti"; +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portSWITCH_INT_NUMBER 0x80 +#define portYIELD() __asm{ int portSWITCH_INT_NUMBER } +#define portDOS_TICK_RATE ( 18.20648 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portTICKS_PER_DOS_TICK ( ( uint16_t ) ( ( ( portDOUBLE ) configTICK_RATE_HZ / portDOS_TICK_RATE ) + 0.5 ) ) +#define portINITIAL_SW ( ( portSTACK_TYPE ) 0x0202 ) /* Start the tasks with interrupts enabled. */ +#define portBYTE_ALIGNMENT ( 2 ) +/*-----------------------------------------------------------*/ + +/* Compiler specifics. */ +#define portINPUT_BYTE( xAddr ) inp( xAddr ) +#define portOUTPUT_BYTE( xAddr, ucValue ) outp( xAddr, ucValue ) +#define portNOP() __asm{ nop } +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters ) +#define portTASK_FUNCTION( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters ) + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + + +#endif /* PORTMACRO_H */ diff --git a/portable/oWatcom/16BitDOS/common/portasm.h b/portable/oWatcom/16BitDOS/common/portasm.h new file mode 100644 index 000000000..b9cb0e697 --- /dev/null +++ b/portable/oWatcom/16BitDOS/common/portasm.h @@ -0,0 +1,109 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +typedef void TCB_t; +extern volatile TCB_t * volatile pxCurrentTCB; +extern void vTaskSwitchContext( void ); + +/* + * Saves the stack pointer for one task into its TCB, calls + * vTaskSwitchContext() to update the TCB being used, then restores the stack + * from the new TCB read to run the task. + */ +void portSWITCH_CONTEXT( void ); + +/* + * Load the stack pointer from the TCB of the task which is going to be first + * to execute. Then force an IRET so the registers and IP are popped off the + * stack. + */ +void portFIRST_CONTEXT( void ); + +/* There are slightly different versions depending on whether you are building +to include debugger information. If debugger information is used then there +are a couple of extra bytes left of the ISR stack (presumably for use by the +debugger). The true stack pointer is then stored in the bp register. We add +2 to the stack pointer to remove the extra bytes before we restore our context. */ + +#ifdef DEBUG_BUILD + + #pragma aux portSWITCH_CONTEXT = "mov ax, seg pxCurrentTCB" \ + "mov ds, ax" \ + "les bx, pxCurrentTCB" /* Save the stack pointer into the TCB. */ \ + "mov es:0x2[ bx ], ss" \ + "mov es:[ bx ], sp" \ + "call vTaskSwitchContext" /* Perform the switch. */ \ + "mov ax, seg pxCurrentTCB" /* Restore the stack pointer from the TCB. */ \ + "mov ds, ax" \ + "les bx, dword ptr pxCurrentTCB" \ + "mov ss, es:[ bx + 2 ]" \ + "mov sp, es:[ bx ]" \ + "mov bp, sp" /* Prepare the bp register for the restoration of the SP in the compiler generated portion of the ISR */ \ + "add bp, 0x0002" + + + + #pragma aux portFIRST_CONTEXT = "mov ax, seg pxCurrentTCB" \ + "mov ds, ax" \ + "les bx, dword ptr pxCurrentTCB" \ + "mov ss, es:[ bx + 2 ]" \ + "mov sp, es:[ bx ]" \ + "add sp, 0x0002" /* Remove the extra bytes that exist in debug builds before restoring the context. */ \ + "pop ax" \ + "pop ax" \ + "pop es" \ + "pop ds" \ + "popa" \ + "iret" +#else + + #pragma aux portSWITCH_CONTEXT = "mov ax, seg pxCurrentTCB" \ + "mov ds, ax" \ + "les bx, pxCurrentTCB" /* Save the stack pointer into the TCB. */ \ + "mov es:0x2[ bx ], ss" \ + "mov es:[ bx ], sp" \ + "call vTaskSwitchContext" /* Perform the switch. */ \ + "mov ax, seg pxCurrentTCB" /* Restore the stack pointer from the TCB. */ \ + "mov ds, ax" \ + "les bx, dword ptr pxCurrentTCB" \ + "mov ss, es:[ bx + 2 ]" \ + "mov sp, es:[ bx ]" + + + #pragma aux portFIRST_CONTEXT = "mov ax, seg pxCurrentTCB" \ + "mov ds, ax" \ + "les bx, dword ptr pxCurrentTCB" \ + "mov ss, es:[ bx + 2 ]" \ + "mov sp, es:[ bx ]" \ + "pop ax" \ + "pop ax" \ + "pop es" \ + "pop ds" \ + "popa" \ + "iret" +#endif diff --git a/portable/oWatcom/16BitDOS/common/portcomn.c b/portable/oWatcom/16BitDOS/common/portcomn.c new file mode 100644 index 000000000..d05b1fd1f --- /dev/null +++ b/portable/oWatcom/16BitDOS/common/portcomn.c @@ -0,0 +1,141 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* +Changes from V1.00: + + + pxPortInitialiseStack() now initialises the stack of new tasks to the + same format used by the compiler. This allows the compiler generated + interrupt mechanism to be used for context switches. + +Changes from V2.4.2: + + + pvPortMalloc and vPortFree have been removed. The projects now use + the definitions from the source/portable/MemMang directory. + +Changes from V2.6.1: + + + usPortCheckFreeStackSpace() has been moved to tasks.c. +*/ + + + +#include +#include "FreeRTOS.h" + +/*-----------------------------------------------------------*/ + +/* See header file for description. */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +StackType_t DS_Reg = 0; +StackType_t * pxOriginalSP; + + /* Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging. */ + + *pxTopOfStack = 0x1111; + pxTopOfStack--; + *pxTopOfStack = 0x2222; + pxTopOfStack--; + *pxTopOfStack = 0x3333; + pxTopOfStack--; + *pxTopOfStack = 0x4444; + pxTopOfStack--; + *pxTopOfStack = 0x5555; + pxTopOfStack--; + + + /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */ + + /* We are going to start the scheduler using a return from interrupt + instruction to load the program counter, so first there would be the + status register and interrupt return address. We make this the start + of the task. */ + *pxTopOfStack = portINITIAL_SW; + pxTopOfStack--; + *pxTopOfStack = FP_SEG( pxCode ); + pxTopOfStack--; + *pxTopOfStack = FP_OFF( pxCode ); + pxTopOfStack--; + + /* We are going to setup the stack for the new task to look like + the stack frame was setup by a compiler generated ISR. We need to know + the address of the existing stack top to place in the SP register within + the stack frame. pxOriginalSP holds SP before (simulated) pusha was + called. */ + pxOriginalSP = pxTopOfStack; + + /* The remaining registers would be pushed on the stack by our context + switch function. These are loaded with values simply to make debugging + easier. */ + *pxTopOfStack = FP_OFF( pvParameters ); /* AX */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xCCCC; /* CX */ + pxTopOfStack--; + *pxTopOfStack = FP_SEG( pvParameters ); /* DX */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xBBBB; /* BX */ + pxTopOfStack--; + *pxTopOfStack = FP_OFF( pxOriginalSP ); /* SP */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xBBBB; /* BP */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x0123; /* SI */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xDDDD; /* DI */ + + /* We need the true data segment. */ + __asm{ MOV DS_Reg, DS }; + + pxTopOfStack--; + *pxTopOfStack = DS_Reg; /* DS */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xEEEE; /* ES */ + + /* The AX register is pushed again twice - don't know why. */ + pxTopOfStack--; + *pxTopOfStack = FP_OFF( pvParameters ); /* AX */ + pxTopOfStack--; + *pxTopOfStack = FP_OFF( pvParameters ); /* AX */ + + + #ifdef DEBUG_BUILD + /* The compiler adds space to each ISR stack if building to + include debug information. Presumably this is used by the + debugger - we don't need to initialise it to anything just + make sure it is there. */ + pxTopOfStack--; + #endif + + /*lint +e950 +e611 +e923 */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ diff --git a/portable/readme.txt b/portable/readme.txt new file mode 100644 index 000000000..ca8f71ed0 --- /dev/null +++ b/portable/readme.txt @@ -0,0 +1,19 @@ +Each real time kernel port consists of three files that contain the core kernel +components and are common to every port, and one or more files that are +specific to a particular microcontroller and/or compiler. + + ++ The FreeRTOS/Source/Portable/MemMang directory contains the five sample +memory allocators as described on the https://www.FreeRTOS.org WEB site. + ++ The other directories each contain files specific to a particular +microcontroller or compiler, where the directory name denotes the compiler +specific files the directory contains. + + + +For example, if you are interested in the [compiler] port for the [architecture] +microcontroller, then the port specific files are contained in +FreeRTOS/Source/Portable/[compiler]/[architecture] directory. If this is the +only port you are interested in then all the other directories can be +ignored. diff --git a/portable/template/port.c b/portable/template/port.c new file mode 100644 index 000000000..7cac1c991 --- /dev/null +++ b/portable/template/port.c @@ -0,0 +1,82 @@ +/* + * FreeRTOS Kernel + * license and copyright intentionally withheld to promote copying into user code. + */ + +#include "FreeRTOS.h" +#include "task.h" + +BaseType_t xPortStartScheduler( void ) +{ + return pdTRUE; +} + +void vPortEndScheduler( void ) +{ +} + +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) +{ + ( void ) pxTopOfStack; + ( void ) pvParameters; + ( void ) * pxCode; + + return NULL; +} + +void vPortYield( void ) +{ + /* Save the current Context */ + + /* Switch to the highest priority task that is ready to run. */ + #if ( configNUMBER_OF_CORES == 1 ) + { + vTaskSwitchContext(); + } + #else + { + vTaskSwitchContext( portGET_CORE_ID() ); + } + #endif + + /* Start executing the task we have just switched to. */ +} + +static void prvTickISR( void ) +{ + /* Interrupts must have been enabled for the ISR to fire, so we have to + * save the context with interrupts enabled. */ + + #if ( configNUMBER_OF_CORES == 1 ) + { + /* Maintain the tick count. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Switch to the highest priority task that is ready to run. */ + vTaskSwitchContext(); + } + } + #else + { + UBaseType_t ulPreviousMask; + + /* Tasks or ISRs running on other cores may still in critical section in + * multiple cores environment. Incrementing tick needs to performed in + * critical section. */ + ulPreviousMask = taskENTER_CRITICAL_FROM_ISR(); + + /* Maintain the tick count. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Switch to the highest priority task that is ready to run. */ + vTaskSwitchContext( portGET_CORE_ID() ); + } + + taskEXIT_CRITICAL_FROM_ISR( ulPreviousMask ); + } + #endif /* if ( configNUMBER_OF_CORES == 1 ) */ + + /* start executing the new task */ +} diff --git a/portable/template/portmacro.h b/portable/template/portmacro.h new file mode 100644 index 000000000..a426f0003 --- /dev/null +++ b/portable/template/portmacro.h @@ -0,0 +1,142 @@ +/* + * FreeRTOS Kernel + * license and copyright intentionally withheld to promote copying into user code. + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE uint8_t +#define portBASE_TYPE char + +#define portSTACK_GROWTH ( -1 ) +#define portBYTE_ALIGNMENT 4 +#define portPOINTER_SIZE_TYPE size_t +typedef portSTACK_TYPE StackType_t; +typedef signed char BaseType_t; +typedef unsigned char UBaseType_t; + +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffU +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffU +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_64_BITS ) + typedef uint64_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffffffffffU +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif + +/* Architecture specific optimisations. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) \ + do { \ + uxTopPriority = 0; \ + } while( 0 ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/* Disable the interrupts */ +#define portDISABLE_INTERRUPTS() do {} while( 0 ) + +/* Enable the interrupts */ +#define portENABLE_INTERRUPTS() do {} while( 0 ) + +#if ( configNUMBER_OF_CORES == 1 ) +/* preserve current interrupt state and then disable interrupts */ + #define portENTER_CRITICAL() do {} while( 0 ) + +/* restore previously preserved interrupt state */ + #define portEXIT_CRITICAL() do {} while( 0 ) +#else + +/* The port can maintain the critical nesting count in TCB or maintain the critical + * nesting count in the port. */ + #define portCRITICAL_NESTING_IN_TCB 1 + +/* vTaskEnterCritical and vTaskExitCritical should be used in the implementation + * of portENTER/EXIT_CRITICAL if the number of cores is more than 1 in the system. */ + #define portENTER_CRITICAL vTaskEnterCritical + #define portEXIT_CRITICAL vTaskExitCritical + +/* vTaskEnterCriticalFromISR and vTaskExitCriticalFromISR should be used in the + * implementation of portENTER/EXIT_CRITICAL_FROM_ISR if the number of cores is + * more than 1 in the system. */ + #define portENTER_CRITICAL_FROM_ISR vTaskEnterCriticalFromISR + #define portEXIT_CRITICAL_FROM_ISR vTaskExitCriticalFromISR + +#endif /* if ( configNUMBER_OF_CORES == 1 ) */ + +extern void vPortYield( void ); +#define portYIELD() vPortYield() + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) __attribute__( ( noreturn ) ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +#if ( configNUMBER_OF_CORES > 1 ) + /* Return the core ID on which the code is running. */ + #define portGET_CORE_ID() 0 + +/* Set the interrupt mask. */ + #define portSET_INTERRUPT_MASK() 0 + +/* Clear the interrupt mask. */ + #define portCLEAR_INTERRUPT_MASK( x ) ( ( void ) ( x ) ) + +/* Request the core ID x to yield. */ + #define portYIELD_CORE( x ) do {} while( 0 ) + +/* Acquire the TASK lock. TASK lock is a recursive lock. + * It should be able to be locked by the same core multiple times. */ + #define portGET_TASK_LOCK( xCoreID ) do {} while( 0 ) + +/* Release the TASK lock. If a TASK lock is locked by the same core multiple times, + * it should be released as many times as it is locked. */ + #define portRELEASE_TASK_LOCK( xCoreID ) do {} while( 0 ) + +/* Acquire the ISR lock. ISR lock is a recursive lock. + * It should be able to be locked by the same core multiple times. */ + #define portGET_ISR_LOCK( xCoreID ) do {} while( 0 ) + +/* Release the ISR lock. If a ISR lock is locked by the same core multiple times, \ + * it should be released as many times as it is locked. */ + #define portRELEASE_ISR_LOCK( xCoreID ) do {} while( 0 ) + +#endif /* if ( configNUMBER_OF_CORES > 1 ) */ + +#endif /* PORTMACRO_H */ diff --git a/queue.c b/queue.c new file mode 100644 index 000000000..a967839de --- /dev/null +++ b/queue.c @@ -0,0 +1,3387 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +#if ( configUSE_CO_ROUTINES == 1 ) + #include "croutine.h" +#endif + +/* The MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined + * for the header files above, but not in this file, in order to generate the + * correct privileged Vs unprivileged linkage and placement. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + + +/* Constants used with the cRxLock and cTxLock structure members. */ +#define queueUNLOCKED ( ( int8_t ) -1 ) +#define queueLOCKED_UNMODIFIED ( ( int8_t ) 0 ) +#define queueINT8_MAX ( ( int8_t ) 127 ) + +/* When the Queue_t structure is used to represent a base queue its pcHead and + * pcTail members are used as pointers into the queue storage area. When the + * Queue_t structure is used to represent a mutex pcHead and pcTail pointers are + * not necessary, and the pcHead pointer is set to NULL to indicate that the + * structure instead holds a pointer to the mutex holder (if any). Map alternative + * names to the pcHead and structure member to ensure the readability of the code + * is maintained. The QueuePointers_t and SemaphoreData_t types are used to form + * a union as their usage is mutually exclusive dependent on what the queue is + * being used for. */ +#define uxQueueType pcHead +#define queueQUEUE_IS_MUTEX NULL + +typedef struct QueuePointers +{ + int8_t * pcTail; /**< Points to the byte at the end of the queue storage area. Once more byte is allocated than necessary to store the queue items, this is used as a marker. */ + int8_t * pcReadFrom; /**< Points to the last place that a queued item was read from when the structure is used as a queue. */ +} QueuePointers_t; + +typedef struct SemaphoreData +{ + TaskHandle_t xMutexHolder; /**< The handle of the task that holds the mutex. */ + UBaseType_t uxRecursiveCallCount; /**< Maintains a count of the number of times a recursive mutex has been recursively 'taken' when the structure is used as a mutex. */ +} SemaphoreData_t; + +/* Semaphores do not actually store or copy data, so have an item size of + * zero. */ +#define queueSEMAPHORE_QUEUE_ITEM_LENGTH ( ( UBaseType_t ) 0 ) +#define queueMUTEX_GIVE_BLOCK_TIME ( ( TickType_t ) 0U ) + +#if ( configUSE_PREEMPTION == 0 ) + +/* If the cooperative scheduler is being used then a yield should not be + * performed just because a higher priority task has been woken. */ + #define queueYIELD_IF_USING_PREEMPTION() +#else + #if ( configNUMBER_OF_CORES == 1 ) + #define queueYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API() + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + #define queueYIELD_IF_USING_PREEMPTION() vTaskYieldWithinAPI() + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ +#endif + +/* + * Definition of the queue used by the scheduler. + * Items are queued by copy, not reference. See the following link for the + * rationale: https://www.FreeRTOS.org/Embedded-RTOS-Queues.html + */ +typedef struct QueueDefinition /* The old naming convention is used to prevent breaking kernel aware debuggers. */ +{ + int8_t * pcHead; /**< Points to the beginning of the queue storage area. */ + int8_t * pcWriteTo; /**< Points to the free next place in the storage area. */ + + union + { + QueuePointers_t xQueue; /**< Data required exclusively when this structure is used as a queue. */ + SemaphoreData_t xSemaphore; /**< Data required exclusively when this structure is used as a semaphore. */ + } u; + + List_t xTasksWaitingToSend; /**< List of tasks that are blocked waiting to post onto this queue. Stored in priority order. */ + List_t xTasksWaitingToReceive; /**< List of tasks that are blocked waiting to read from this queue. Stored in priority order. */ + + volatile UBaseType_t uxMessagesWaiting; /**< The number of items currently in the queue. */ + UBaseType_t uxLength; /**< The length of the queue defined as the number of items it will hold, not the number of bytes. */ + UBaseType_t uxItemSize; /**< The size of each items that the queue will hold. */ + + volatile int8_t cRxLock; /**< Stores the number of items received from the queue (removed from the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */ + volatile int8_t cTxLock; /**< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */ + + #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucStaticallyAllocated; /**< Set to pdTRUE if the memory used by the queue was statically allocated to ensure no attempt is made to free the memory. */ + #endif + + #if ( configUSE_QUEUE_SETS == 1 ) + struct QueueDefinition * pxQueueSetContainer; + #endif + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxQueueNumber; + uint8_t ucQueueType; + #endif +} xQUEUE; + +/* The old xQUEUE name is maintained above then typedefed to the new Queue_t + * name below to enable the use of older kernel aware debuggers. */ +typedef xQUEUE Queue_t; + +/*-----------------------------------------------------------*/ + +/* + * The queue registry is just a means for kernel aware debuggers to locate + * queue structures. It has no other purpose so is an optional component. + */ +#if ( configQUEUE_REGISTRY_SIZE > 0 ) + +/* The type stored within the queue registry array. This allows a name + * to be assigned to each queue making kernel aware debugging a little + * more user friendly. */ + typedef struct QUEUE_REGISTRY_ITEM + { + const char * pcQueueName; + QueueHandle_t xHandle; + } xQueueRegistryItem; + +/* The old xQueueRegistryItem name is maintained above then typedefed to the + * new xQueueRegistryItem name below to enable the use of older kernel aware + * debuggers. */ + typedef xQueueRegistryItem QueueRegistryItem_t; + +/* The queue registry is simply an array of QueueRegistryItem_t structures. + * The pcQueueName member of a structure being NULL is indicative of the + * array position being vacant. */ + +/* MISRA Ref 8.4.2 [Declaration shall be visible] */ +/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-84 */ +/* coverity[misra_c_2012_rule_8_4_violation] */ + PRIVILEGED_DATA QueueRegistryItem_t xQueueRegistry[ configQUEUE_REGISTRY_SIZE ]; + +#endif /* configQUEUE_REGISTRY_SIZE */ + +/* + * Unlocks a queue locked by a call to prvLockQueue. Locking a queue does not + * prevent an ISR from adding or removing items to the queue, but does prevent + * an ISR from removing tasks from the queue event lists. If an ISR finds a + * queue is locked it will instead increment the appropriate queue lock count + * to indicate that a task may require unblocking. When the queue in unlocked + * these lock counts are inspected, and the appropriate action taken. + */ +static void prvUnlockQueue( Queue_t * const pxQueue ) PRIVILEGED_FUNCTION; + +/* + * Uses a critical section to determine if there is any data in a queue. + * + * @return pdTRUE if the queue contains no items, otherwise pdFALSE. + */ +static BaseType_t prvIsQueueEmpty( const Queue_t * pxQueue ) PRIVILEGED_FUNCTION; + +/* + * Uses a critical section to determine if there is any space in a queue. + * + * @return pdTRUE if there is no space, otherwise pdFALSE; + */ +static BaseType_t prvIsQueueFull( const Queue_t * pxQueue ) PRIVILEGED_FUNCTION; + +/* + * Copies an item into the queue, either at the front of the queue or the + * back of the queue. + */ +static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, + const void * pvItemToQueue, + const BaseType_t xPosition ) PRIVILEGED_FUNCTION; + +/* + * Copies an item out of a queue. + */ +static void prvCopyDataFromQueue( Queue_t * const pxQueue, + void * const pvBuffer ) PRIVILEGED_FUNCTION; + +#if ( configUSE_QUEUE_SETS == 1 ) + +/* + * Checks to see if a queue is a member of a queue set, and if so, notifies + * the queue set that the queue contains data. + */ + static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION; +#endif + +/* + * Called after a Queue_t structure has been allocated either statically or + * dynamically to fill in the structure's members. + */ +static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, + const UBaseType_t uxItemSize, + uint8_t * pucQueueStorage, + const uint8_t ucQueueType, + Queue_t * pxNewQueue ) PRIVILEGED_FUNCTION; + +/* + * Mutexes are a special type of queue. When a mutex is created, first the + * queue is created, then prvInitialiseMutex() is called to configure the queue + * as a mutex. + */ +#if ( configUSE_MUTEXES == 1 ) + static void prvInitialiseMutex( Queue_t * pxNewQueue ) PRIVILEGED_FUNCTION; +#endif + +#if ( configUSE_MUTEXES == 1 ) + +/* + * If a task waiting for a mutex causes the mutex holder to inherit a + * priority, but the waiting task times out, then the holder should + * disinherit the priority - but only down to the highest priority of any + * other tasks that are waiting for the same mutex. This function returns + * that priority. + */ + static UBaseType_t prvGetHighestPriorityOfWaitToReceiveList( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION; +#endif +/*-----------------------------------------------------------*/ + +/* + * Macro to mark a queue as locked. Locking a queue prevents an ISR from + * accessing the queue event lists. + */ +#define prvLockQueue( pxQueue ) \ + taskENTER_CRITICAL(); \ + { \ + if( ( pxQueue )->cRxLock == queueUNLOCKED ) \ + { \ + ( pxQueue )->cRxLock = queueLOCKED_UNMODIFIED; \ + } \ + if( ( pxQueue )->cTxLock == queueUNLOCKED ) \ + { \ + ( pxQueue )->cTxLock = queueLOCKED_UNMODIFIED; \ + } \ + } \ + taskEXIT_CRITICAL() + +/* + * Macro to increment cTxLock member of the queue data structure. It is + * capped at the number of tasks in the system as we cannot unblock more + * tasks than the number of tasks in the system. + */ +#define prvIncrementQueueTxLock( pxQueue, cTxLock ) \ + do { \ + const UBaseType_t uxNumberOfTasks = uxTaskGetNumberOfTasks(); \ + if( ( UBaseType_t ) ( cTxLock ) < uxNumberOfTasks ) \ + { \ + configASSERT( ( cTxLock ) != queueINT8_MAX ); \ + ( pxQueue )->cTxLock = ( int8_t ) ( ( cTxLock ) + ( int8_t ) 1 ); \ + } \ + } while( 0 ) + +/* + * Macro to increment cRxLock member of the queue data structure. It is + * capped at the number of tasks in the system as we cannot unblock more + * tasks than the number of tasks in the system. + */ +#define prvIncrementQueueRxLock( pxQueue, cRxLock ) \ + do { \ + const UBaseType_t uxNumberOfTasks = uxTaskGetNumberOfTasks(); \ + if( ( UBaseType_t ) ( cRxLock ) < uxNumberOfTasks ) \ + { \ + configASSERT( ( cRxLock ) != queueINT8_MAX ); \ + ( pxQueue )->cRxLock = ( int8_t ) ( ( cRxLock ) + ( int8_t ) 1 ); \ + } \ + } while( 0 ) +/*-----------------------------------------------------------*/ + +BaseType_t xQueueGenericReset( QueueHandle_t xQueue, + BaseType_t xNewQueue ) +{ + BaseType_t xReturn = pdPASS; + Queue_t * const pxQueue = xQueue; + + traceENTER_xQueueGenericReset( xQueue, xNewQueue ); + + configASSERT( pxQueue ); + + if( ( pxQueue != NULL ) && + ( pxQueue->uxLength >= 1U ) && + /* Check for multiplication overflow. */ + ( ( SIZE_MAX / pxQueue->uxLength ) >= pxQueue->uxItemSize ) ) + { + taskENTER_CRITICAL(); + { + pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); + pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U; + pxQueue->pcWriteTo = pxQueue->pcHead; + pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); + pxQueue->cRxLock = queueUNLOCKED; + pxQueue->cTxLock = queueUNLOCKED; + + if( xNewQueue == pdFALSE ) + { + /* If there are tasks blocked waiting to read from the queue, then + * the tasks will remain blocked as after this function exits the queue + * will still be empty. If there are tasks blocked waiting to write to + * the queue, then one should be unblocked as after this function exits + * it will be possible to write to it. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + { + queueYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* Ensure the event queues start in the correct state. */ + vListInitialise( &( pxQueue->xTasksWaitingToSend ) ); + vListInitialise( &( pxQueue->xTasksWaitingToReceive ) ); + } + } + taskEXIT_CRITICAL(); + } + else + { + xReturn = pdFAIL; + } + + configASSERT( xReturn != pdFAIL ); + + /* A value is returned for calling semantic consistency with previous + * versions. */ + traceRETURN_xQueueGenericReset( xReturn ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + + QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, + const UBaseType_t uxItemSize, + uint8_t * pucQueueStorage, + StaticQueue_t * pxStaticQueue, + const uint8_t ucQueueType ) + { + Queue_t * pxNewQueue = NULL; + + traceENTER_xQueueGenericCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxStaticQueue, ucQueueType ); + + /* The StaticQueue_t structure and the queue storage area must be + * supplied. */ + configASSERT( pxStaticQueue ); + + if( ( uxQueueLength > ( UBaseType_t ) 0 ) && + ( pxStaticQueue != NULL ) && + + /* A queue storage area should be provided if the item size is not 0, and + * should not be provided if the item size is 0. */ + ( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0U ) ) ) && + ( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0U ) ) ) ) + { + #if ( configASSERT_DEFINED == 1 ) + { + /* Sanity check that the size of the structure used to declare a + * variable of type StaticQueue_t or StaticSemaphore_t equals the size of + * the real queue and semaphore structures. */ + volatile size_t xSize = sizeof( StaticQueue_t ); + + /* This assertion cannot be branch covered in unit tests */ + configASSERT( xSize == sizeof( Queue_t ) ); /* LCOV_EXCL_BR_LINE */ + ( void ) xSize; /* Prevent unused variable warning when configASSERT() is not defined. */ + } + #endif /* configASSERT_DEFINED */ + + /* The address of a statically allocated queue was passed in, use it. + * The address of a statically allocated storage area was also passed in + * but is already set. */ + /* MISRA Ref 11.3.1 [Misaligned access] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */ + /* coverity[misra_c_2012_rule_11_3_violation] */ + pxNewQueue = ( Queue_t * ) pxStaticQueue; + + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + { + /* Queues can be allocated either statically or dynamically, so + * note this queue was allocated statically in case the queue is + * later deleted. */ + pxNewQueue->ucStaticallyAllocated = pdTRUE; + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + + prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue ); + } + else + { + configASSERT( pxNewQueue ); + mtCOVERAGE_TEST_MARKER(); + } + + traceRETURN_xQueueGenericCreateStatic( pxNewQueue ); + + return pxNewQueue; + } + +#endif /* configSUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + + BaseType_t xQueueGenericGetStaticBuffers( QueueHandle_t xQueue, + uint8_t ** ppucQueueStorage, + StaticQueue_t ** ppxStaticQueue ) + { + BaseType_t xReturn; + Queue_t * const pxQueue = xQueue; + + traceENTER_xQueueGenericGetStaticBuffers( xQueue, ppucQueueStorage, ppxStaticQueue ); + + configASSERT( pxQueue ); + configASSERT( ppxStaticQueue ); + + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + { + /* Check if the queue was statically allocated. */ + if( pxQueue->ucStaticallyAllocated == ( uint8_t ) pdTRUE ) + { + if( ppucQueueStorage != NULL ) + { + *ppucQueueStorage = ( uint8_t * ) pxQueue->pcHead; + } + + /* MISRA Ref 11.3.1 [Misaligned access] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */ + /* coverity[misra_c_2012_rule_11_3_violation] */ + *ppxStaticQueue = ( StaticQueue_t * ) pxQueue; + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + } + #else /* configSUPPORT_DYNAMIC_ALLOCATION */ + { + /* Queue must have been statically allocated. */ + if( ppucQueueStorage != NULL ) + { + *ppucQueueStorage = ( uint8_t * ) pxQueue->pcHead; + } + + *ppxStaticQueue = ( StaticQueue_t * ) pxQueue; + xReturn = pdTRUE; + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + + traceRETURN_xQueueGenericGetStaticBuffers( xReturn ); + + return xReturn; + } + +#endif /* configSUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, + const UBaseType_t uxItemSize, + const uint8_t ucQueueType ) + { + Queue_t * pxNewQueue = NULL; + size_t xQueueSizeInBytes; + uint8_t * pucQueueStorage; + + traceENTER_xQueueGenericCreate( uxQueueLength, uxItemSize, ucQueueType ); + + if( ( uxQueueLength > ( UBaseType_t ) 0 ) && + /* Check for multiplication overflow. */ + ( ( SIZE_MAX / uxQueueLength ) >= uxItemSize ) && + /* Check for addition overflow. */ + /* MISRA Ref 14.3.1 [Configuration dependent invariant] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-143. */ + /* coverity[misra_c_2012_rule_14_3_violation] */ + ( ( SIZE_MAX - sizeof( Queue_t ) ) >= ( size_t ) ( ( size_t ) uxQueueLength * ( size_t ) uxItemSize ) ) ) + { + /* Allocate enough space to hold the maximum number of items that + * can be in the queue at any time. It is valid for uxItemSize to be + * zero in the case the queue is used as a semaphore. */ + xQueueSizeInBytes = ( size_t ) ( ( size_t ) uxQueueLength * ( size_t ) uxItemSize ); + + /* MISRA Ref 11.5.1 [Malloc memory assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); + + if( pxNewQueue != NULL ) + { + /* Jump past the queue structure to find the location of the queue + * storage area. */ + pucQueueStorage = ( uint8_t * ) pxNewQueue; + pucQueueStorage += sizeof( Queue_t ); + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + /* Queues can be created either statically or dynamically, so + * note this task was created dynamically in case it is later + * deleted. */ + pxNewQueue->ucStaticallyAllocated = pdFALSE; + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ + + prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue ); + } + else + { + traceQUEUE_CREATE_FAILED( ucQueueType ); + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + configASSERT( pxNewQueue ); + mtCOVERAGE_TEST_MARKER(); + } + + traceRETURN_xQueueGenericCreate( pxNewQueue ); + + return pxNewQueue; + } + +#endif /* configSUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, + const UBaseType_t uxItemSize, + uint8_t * pucQueueStorage, + const uint8_t ucQueueType, + Queue_t * pxNewQueue ) +{ + /* Remove compiler warnings about unused parameters should + * configUSE_TRACE_FACILITY not be set to 1. */ + ( void ) ucQueueType; + + if( uxItemSize == ( UBaseType_t ) 0 ) + { + /* No RAM was allocated for the queue storage area, but PC head cannot + * be set to NULL because NULL is used as a key to say the queue is used as + * a mutex. Therefore just set pcHead to point to the queue as a benign + * value that is known to be within the memory map. */ + pxNewQueue->pcHead = ( int8_t * ) pxNewQueue; + } + else + { + /* Set the head to the start of the queue storage area. */ + pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage; + } + + /* Initialise the queue members as described where the queue type is + * defined. */ + pxNewQueue->uxLength = uxQueueLength; + pxNewQueue->uxItemSize = uxItemSize; + ( void ) xQueueGenericReset( pxNewQueue, pdTRUE ); + + #if ( configUSE_TRACE_FACILITY == 1 ) + { + pxNewQueue->ucQueueType = ucQueueType; + } + #endif /* configUSE_TRACE_FACILITY */ + + #if ( configUSE_QUEUE_SETS == 1 ) + { + pxNewQueue->pxQueueSetContainer = NULL; + } + #endif /* configUSE_QUEUE_SETS */ + + traceQUEUE_CREATE( pxNewQueue ); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_MUTEXES == 1 ) + + static void prvInitialiseMutex( Queue_t * pxNewQueue ) + { + if( pxNewQueue != NULL ) + { + /* The queue create function will set all the queue structure members + * correctly for a generic queue, but this function is creating a + * mutex. Overwrite those members that need to be set differently - + * in particular the information required for priority inheritance. */ + pxNewQueue->u.xSemaphore.xMutexHolder = NULL; + pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX; + + /* In case this is a recursive mutex. */ + pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0; + + traceCREATE_MUTEX( pxNewQueue ); + + /* Start with the semaphore in the expected state. */ + ( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK ); + } + else + { + traceCREATE_MUTEX_FAILED(); + } + } + +#endif /* configUSE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + + QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) + { + QueueHandle_t xNewQueue; + const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0; + + traceENTER_xQueueCreateMutex( ucQueueType ); + + xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType ); + prvInitialiseMutex( ( Queue_t * ) xNewQueue ); + + traceRETURN_xQueueCreateMutex( xNewQueue ); + + return xNewQueue; + } + +#endif /* configUSE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + + QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, + StaticQueue_t * pxStaticQueue ) + { + QueueHandle_t xNewQueue; + const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0; + + traceENTER_xQueueCreateMutexStatic( ucQueueType, pxStaticQueue ); + + /* Prevent compiler warnings about unused parameters if + * configUSE_TRACE_FACILITY does not equal 1. */ + ( void ) ucQueueType; + + xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType ); + prvInitialiseMutex( ( Queue_t * ) xNewQueue ); + + traceRETURN_xQueueCreateMutexStatic( xNewQueue ); + + return xNewQueue; + } + +#endif /* configUSE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) + + TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore ) + { + TaskHandle_t pxReturn; + Queue_t * const pxSemaphore = ( Queue_t * ) xSemaphore; + + traceENTER_xQueueGetMutexHolder( xSemaphore ); + + configASSERT( xSemaphore ); + + /* This function is called by xSemaphoreGetMutexHolder(), and should not + * be called directly. Note: This is a good way of determining if the + * calling task is the mutex holder, but not a good way of determining the + * identity of the mutex holder, as the holder may change between the + * following critical section exiting and the function returning. */ + taskENTER_CRITICAL(); + { + if( pxSemaphore->uxQueueType == queueQUEUE_IS_MUTEX ) + { + pxReturn = pxSemaphore->u.xSemaphore.xMutexHolder; + } + else + { + pxReturn = NULL; + } + } + taskEXIT_CRITICAL(); + + traceRETURN_xQueueGetMutexHolder( pxReturn ); + + return pxReturn; + } + +#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) + + TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) + { + TaskHandle_t pxReturn; + + traceENTER_xQueueGetMutexHolderFromISR( xSemaphore ); + + configASSERT( xSemaphore ); + + /* Mutexes cannot be used in interrupt service routines, so the mutex + * holder should not change in an ISR, and therefore a critical section is + * not required here. */ + if( ( ( Queue_t * ) xSemaphore )->uxQueueType == queueQUEUE_IS_MUTEX ) + { + pxReturn = ( ( Queue_t * ) xSemaphore )->u.xSemaphore.xMutexHolder; + } + else + { + pxReturn = NULL; + } + + traceRETURN_xQueueGetMutexHolderFromISR( pxReturn ); + + return pxReturn; + } + +#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) + { + BaseType_t xReturn; + Queue_t * const pxMutex = ( Queue_t * ) xMutex; + + traceENTER_xQueueGiveMutexRecursive( xMutex ); + + configASSERT( pxMutex ); + + /* If this is the task that holds the mutex then xMutexHolder will not + * change outside of this task. If this task does not hold the mutex then + * pxMutexHolder can never coincidentally equal the tasks handle, and as + * this is the only condition we are interested in it does not matter if + * pxMutexHolder is accessed simultaneously by another task. Therefore no + * mutual exclusion is required to test the pxMutexHolder variable. */ + if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() ) + { + traceGIVE_MUTEX_RECURSIVE( pxMutex ); + + /* uxRecursiveCallCount cannot be zero if xMutexHolder is equal to + * the task handle, therefore no underflow check is required. Also, + * uxRecursiveCallCount is only modified by the mutex holder, and as + * there can only be one, no mutual exclusion is required to modify the + * uxRecursiveCallCount member. */ + ( pxMutex->u.xSemaphore.uxRecursiveCallCount )--; + + /* Has the recursive call count unwound to 0? */ + if( pxMutex->u.xSemaphore.uxRecursiveCallCount == ( UBaseType_t ) 0 ) + { + /* Return the mutex. This will automatically unblock any other + * task that might be waiting to access the mutex. */ + ( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xReturn = pdPASS; + } + else + { + /* The mutex cannot be given because the calling task is not the + * holder. */ + xReturn = pdFAIL; + + traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex ); + } + + traceRETURN_xQueueGiveMutexRecursive( xReturn ); + + return xReturn; + } + +#endif /* configUSE_RECURSIVE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) + { + BaseType_t xReturn; + Queue_t * const pxMutex = ( Queue_t * ) xMutex; + + traceENTER_xQueueTakeMutexRecursive( xMutex, xTicksToWait ); + + configASSERT( pxMutex ); + + /* Comments regarding mutual exclusion as per those within + * xQueueGiveMutexRecursive(). */ + + traceTAKE_MUTEX_RECURSIVE( pxMutex ); + + if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() ) + { + ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++; + + /* Check if an overflow occurred. */ + configASSERT( pxMutex->u.xSemaphore.uxRecursiveCallCount ); + + xReturn = pdPASS; + } + else + { + xReturn = xQueueSemaphoreTake( pxMutex, xTicksToWait ); + + /* pdPASS will only be returned if the mutex was successfully + * obtained. The calling task may have entered the Blocked state + * before reaching here. */ + if( xReturn != pdFAIL ) + { + ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++; + + /* Check if an overflow occurred. */ + configASSERT( pxMutex->u.xSemaphore.uxRecursiveCallCount ); + } + else + { + traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex ); + } + } + + traceRETURN_xQueueTakeMutexRecursive( xReturn ); + + return xReturn; + } + +#endif /* configUSE_RECURSIVE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + + QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, + const UBaseType_t uxInitialCount, + StaticQueue_t * pxStaticQueue ) + { + QueueHandle_t xHandle = NULL; + + traceENTER_xQueueCreateCountingSemaphoreStatic( uxMaxCount, uxInitialCount, pxStaticQueue ); + + if( ( uxMaxCount != 0U ) && + ( uxInitialCount <= uxMaxCount ) ) + { + xHandle = xQueueGenericCreateStatic( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticQueue, queueQUEUE_TYPE_COUNTING_SEMAPHORE ); + + if( xHandle != NULL ) + { + ( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount; + + traceCREATE_COUNTING_SEMAPHORE(); + } + else + { + traceCREATE_COUNTING_SEMAPHORE_FAILED(); + } + } + else + { + configASSERT( xHandle ); + mtCOVERAGE_TEST_MARKER(); + } + + traceRETURN_xQueueCreateCountingSemaphoreStatic( xHandle ); + + return xHandle; + } + +#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + + QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, + const UBaseType_t uxInitialCount ) + { + QueueHandle_t xHandle = NULL; + + traceENTER_xQueueCreateCountingSemaphore( uxMaxCount, uxInitialCount ); + + if( ( uxMaxCount != 0U ) && + ( uxInitialCount <= uxMaxCount ) ) + { + xHandle = xQueueGenericCreate( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_COUNTING_SEMAPHORE ); + + if( xHandle != NULL ) + { + ( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount; + + traceCREATE_COUNTING_SEMAPHORE(); + } + else + { + traceCREATE_COUNTING_SEMAPHORE_FAILED(); + } + } + else + { + configASSERT( xHandle ); + mtCOVERAGE_TEST_MARKER(); + } + + traceRETURN_xQueueCreateCountingSemaphore( xHandle ); + + return xHandle; + } + +#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +BaseType_t xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) +{ + BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired; + TimeOut_t xTimeOut; + Queue_t * const pxQueue = xQueue; + + traceENTER_xQueueGenericSend( xQueue, pvItemToQueue, xTicksToWait, xCopyPosition ); + + configASSERT( pxQueue ); + configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); + configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + } + #endif + + for( ; ; ) + { + taskENTER_CRITICAL(); + { + /* Is there room on the queue now? The running task must be the + * highest priority task wanting to access the queue. If the head item + * in the queue is to be overwritten then it does not matter if the + * queue is full. */ + if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) + { + traceQUEUE_SEND( pxQueue ); + + #if ( configUSE_QUEUE_SETS == 1 ) + { + const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting; + + xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); + + if( pxQueue->pxQueueSetContainer != NULL ) + { + if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) ) + { + /* Do not notify the queue set as an existing item + * was overwritten in the queue so the number of items + * in the queue has not changed. */ + mtCOVERAGE_TEST_MARKER(); + } + else if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE ) + { + /* The queue is a member of a queue set, and posting + * to the queue set caused a higher priority task to + * unblock. A context switch is required. */ + queueYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* If there was a task waiting for data to arrive on the + * queue then unblock it now. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The unblocked task has a priority higher than + * our own so yield immediately. Yes it is ok to + * do this from within the critical section - the + * kernel takes care of that. */ + queueYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else if( xYieldRequired != pdFALSE ) + { + /* This path is a special case that will only get + * executed if the task was holding multiple mutexes + * and the mutexes were given back in an order that is + * different to that in which they were taken. */ + queueYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + #else /* configUSE_QUEUE_SETS */ + { + xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); + + /* If there was a task waiting for data to arrive on the + * queue then unblock it now. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The unblocked task has a priority higher than + * our own so yield immediately. Yes it is ok to do + * this from within the critical section - the kernel + * takes care of that. */ + queueYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else if( xYieldRequired != pdFALSE ) + { + /* This path is a special case that will only get + * executed if the task was holding multiple mutexes and + * the mutexes were given back in an order that is + * different to that in which they were taken. */ + queueYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_QUEUE_SETS */ + + taskEXIT_CRITICAL(); + + traceRETURN_xQueueGenericSend( pdPASS ); + + return pdPASS; + } + else + { + if( xTicksToWait == ( TickType_t ) 0 ) + { + /* The queue was full and no block time is specified (or + * the block time has expired) so leave now. */ + taskEXIT_CRITICAL(); + + /* Return to the original privilege level before exiting + * the function. */ + traceQUEUE_SEND_FAILED( pxQueue ); + traceRETURN_xQueueGenericSend( errQUEUE_FULL ); + + return errQUEUE_FULL; + } + else if( xEntryTimeSet == pdFALSE ) + { + /* The queue was full and a block time was specified so + * configure the timeout structure. */ + vTaskInternalSetTimeOutState( &xTimeOut ); + xEntryTimeSet = pdTRUE; + } + else + { + /* Entry time was already set. */ + mtCOVERAGE_TEST_MARKER(); + } + } + } + taskEXIT_CRITICAL(); + + /* Interrupts and other tasks can send to and receive from the queue + * now the critical section has been exited. */ + + vTaskSuspendAll(); + prvLockQueue( pxQueue ); + + /* Update the timeout state to see if it has expired yet. */ + if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) + { + if( prvIsQueueFull( pxQueue ) != pdFALSE ) + { + traceBLOCKING_ON_QUEUE_SEND( pxQueue ); + vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait ); + + /* Unlocking the queue means queue events can effect the + * event list. It is possible that interrupts occurring now + * remove this task from the event list again - but as the + * scheduler is suspended the task will go onto the pending + * ready list instead of the actual ready list. */ + prvUnlockQueue( pxQueue ); + + /* Resuming the scheduler will move tasks from the pending + * ready list into the ready list - so it is feasible that this + * task is already in the ready list before it yields - in which + * case the yield will not cause a context switch unless there + * is also a higher priority task in the pending ready list. */ + if( xTaskResumeAll() == pdFALSE ) + { + taskYIELD_WITHIN_API(); + } + } + else + { + /* Try again. */ + prvUnlockQueue( pxQueue ); + ( void ) xTaskResumeAll(); + } + } + else + { + /* The timeout has expired. */ + prvUnlockQueue( pxQueue ); + ( void ) xTaskResumeAll(); + + traceQUEUE_SEND_FAILED( pxQueue ); + traceRETURN_xQueueGenericSend( errQUEUE_FULL ); + + return errQUEUE_FULL; + } + } +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, + const void * const pvItemToQueue, + BaseType_t * const pxHigherPriorityTaskWoken, + const BaseType_t xCopyPosition ) +{ + BaseType_t xReturn; + UBaseType_t uxSavedInterruptStatus; + Queue_t * const pxQueue = xQueue; + + traceENTER_xQueueGenericSendFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken, xCopyPosition ); + + configASSERT( ( pxQueue != NULL ) && !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); + configASSERT( ( pxQueue != NULL ) && !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); + + /* RTOS ports that support interrupt nesting have the concept of a maximum + * system call (or maximum API call) interrupt priority. Interrupts that are + * above the maximum system call priority are kept permanently enabled, even + * when the RTOS kernel is in a critical section, but cannot make any calls to + * FreeRTOS API functions. If configASSERT() is defined in FreeRTOSConfig.h + * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has been + * assigned a priority above the configured maximum system call priority. + * Only FreeRTOS functions that end in FromISR can be called from interrupts + * that have been assigned a priority at or (logically) below the maximum + * system call interrupt priority. FreeRTOS maintains a separate interrupt + * safe API to ensure interrupt entry is as fast and as simple as possible. + * More information (albeit Cortex-M specific) is provided on the following + * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + /* Similar to xQueueGenericSend, except without blocking if there is no room + * in the queue. Also don't directly wake a task that was blocked on a queue + * read, instead return a flag to say whether a context switch is required or + * not (i.e. has a task with a higher priority than us been woken by this + * post). */ + /* MISRA Ref 4.7.1 [Return value shall be checked] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */ + /* coverity[misra_c_2012_directive_4_7_violation] */ + uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR(); + { + if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) + { + const int8_t cTxLock = pxQueue->cTxLock; + const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting; + + traceQUEUE_SEND_FROM_ISR( pxQueue ); + + /* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a + * semaphore or mutex. That means prvCopyDataToQueue() cannot result + * in a task disinheriting a priority and prvCopyDataToQueue() can be + * called here even though the disinherit function does not check if + * the scheduler is suspended before accessing the ready lists. */ + ( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); + + /* The event list is not altered if the queue is locked. This will + * be done when the queue is unlocked later. */ + if( cTxLock == queueUNLOCKED ) + { + #if ( configUSE_QUEUE_SETS == 1 ) + { + if( pxQueue->pxQueueSetContainer != NULL ) + { + if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) ) + { + /* Do not notify the queue set as an existing item + * was overwritten in the queue so the number of items + * in the queue has not changed. */ + mtCOVERAGE_TEST_MARKER(); + } + else if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE ) + { + /* The queue is a member of a queue set, and posting + * to the queue set caused a higher priority task to + * unblock. A context switch is required. */ + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The task waiting has a higher priority so + * record that a context switch is required. */ + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + #else /* configUSE_QUEUE_SETS */ + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The task waiting has a higher priority so record that a + * context switch is required. */ + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Not used in this path. */ + ( void ) uxPreviousMessagesWaiting; + } + #endif /* configUSE_QUEUE_SETS */ + } + else + { + /* Increment the lock count so the task that unlocks the queue + * knows that data was posted while it was locked. */ + prvIncrementQueueTxLock( pxQueue, cTxLock ); + } + + xReturn = pdPASS; + } + else + { + traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ); + xReturn = errQUEUE_FULL; + } + } + taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + + traceRETURN_xQueueGenericSendFromISR( xReturn ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, + BaseType_t * const pxHigherPriorityTaskWoken ) +{ + BaseType_t xReturn; + UBaseType_t uxSavedInterruptStatus; + Queue_t * const pxQueue = xQueue; + + traceENTER_xQueueGiveFromISR( xQueue, pxHigherPriorityTaskWoken ); + + /* Similar to xQueueGenericSendFromISR() but used with semaphores where the + * item size is 0. Don't directly wake a task that was blocked on a queue + * read, instead return a flag to say whether a context switch is required or + * not (i.e. has a task with a higher priority than us been woken by this + * post). */ + + /* xQueueGenericSendFromISR() should be used instead of xQueueGiveFromISR() + * if the item size is not 0. */ + configASSERT( ( pxQueue != NULL ) && ( pxQueue->uxItemSize == 0 ) ); + + /* Normally a mutex would not be given from an interrupt, especially if + * there is a mutex holder, as priority inheritance makes no sense for an + * interrupt, only tasks. */ + configASSERT( ( pxQueue != NULL ) && !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->u.xSemaphore.xMutexHolder != NULL ) ) ); + + /* RTOS ports that support interrupt nesting have the concept of a maximum + * system call (or maximum API call) interrupt priority. Interrupts that are + * above the maximum system call priority are kept permanently enabled, even + * when the RTOS kernel is in a critical section, but cannot make any calls to + * FreeRTOS API functions. If configASSERT() is defined in FreeRTOSConfig.h + * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has been + * assigned a priority above the configured maximum system call priority. + * Only FreeRTOS functions that end in FromISR can be called from interrupts + * that have been assigned a priority at or (logically) below the maximum + * system call interrupt priority. FreeRTOS maintains a separate interrupt + * safe API to ensure interrupt entry is as fast and as simple as possible. + * More information (albeit Cortex-M specific) is provided on the following + * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + /* MISRA Ref 4.7.1 [Return value shall be checked] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */ + /* coverity[misra_c_2012_directive_4_7_violation] */ + uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR(); + { + const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; + + /* When the queue is used to implement a semaphore no data is ever + * moved through the queue but it is still valid to see if the queue 'has + * space'. */ + if( uxMessagesWaiting < pxQueue->uxLength ) + { + const int8_t cTxLock = pxQueue->cTxLock; + + traceQUEUE_SEND_FROM_ISR( pxQueue ); + + /* A task can only have an inherited priority if it is a mutex + * holder - and if there is a mutex holder then the mutex cannot be + * given from an ISR. As this is the ISR version of the function it + * can be assumed there is no mutex holder and no need to determine if + * priority disinheritance is needed. Simply increase the count of + * messages (semaphores) available. */ + pxQueue->uxMessagesWaiting = ( UBaseType_t ) ( uxMessagesWaiting + ( UBaseType_t ) 1 ); + + /* The event list is not altered if the queue is locked. This will + * be done when the queue is unlocked later. */ + if( cTxLock == queueUNLOCKED ) + { + #if ( configUSE_QUEUE_SETS == 1 ) + { + if( pxQueue->pxQueueSetContainer != NULL ) + { + if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE ) + { + /* The semaphore is a member of a queue set, and + * posting to the queue set caused a higher priority + * task to unblock. A context switch is required. */ + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The task waiting has a higher priority so + * record that a context switch is required. */ + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + #else /* configUSE_QUEUE_SETS */ + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The task waiting has a higher priority so record that a + * context switch is required. */ + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_QUEUE_SETS */ + } + else + { + /* Increment the lock count so the task that unlocks the queue + * knows that data was posted while it was locked. */ + prvIncrementQueueTxLock( pxQueue, cTxLock ); + } + + xReturn = pdPASS; + } + else + { + traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ); + xReturn = errQUEUE_FULL; + } + } + taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + + traceRETURN_xQueueGiveFromISR( xReturn ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) +{ + BaseType_t xEntryTimeSet = pdFALSE; + TimeOut_t xTimeOut; + Queue_t * const pxQueue = xQueue; + + traceENTER_xQueueReceive( xQueue, pvBuffer, xTicksToWait ); + + /* Check the pointer is not NULL. */ + configASSERT( ( pxQueue ) ); + + /* The buffer into which data is received can only be NULL if the data size + * is zero (so no data is copied into the buffer). */ + configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) ); + + /* Cannot block if the scheduler is suspended. */ + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + } + #endif + + for( ; ; ) + { + taskENTER_CRITICAL(); + { + const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; + + /* Is there data in the queue now? To be running the calling task + * must be the highest priority task wanting to access the queue. */ + if( uxMessagesWaiting > ( UBaseType_t ) 0 ) + { + /* Data available, remove one item. */ + prvCopyDataFromQueue( pxQueue, pvBuffer ); + traceQUEUE_RECEIVE( pxQueue ); + pxQueue->uxMessagesWaiting = ( UBaseType_t ) ( uxMessagesWaiting - ( UBaseType_t ) 1 ); + + /* There is now space in the queue, were any tasks waiting to + * post to the queue? If so, unblock the highest priority waiting + * task. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + { + queueYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + taskEXIT_CRITICAL(); + + traceRETURN_xQueueReceive( pdPASS ); + + return pdPASS; + } + else + { + if( xTicksToWait == ( TickType_t ) 0 ) + { + /* The queue was empty and no block time is specified (or + * the block time has expired) so leave now. */ + taskEXIT_CRITICAL(); + + traceQUEUE_RECEIVE_FAILED( pxQueue ); + traceRETURN_xQueueReceive( errQUEUE_EMPTY ); + + return errQUEUE_EMPTY; + } + else if( xEntryTimeSet == pdFALSE ) + { + /* The queue was empty and a block time was specified so + * configure the timeout structure. */ + vTaskInternalSetTimeOutState( &xTimeOut ); + xEntryTimeSet = pdTRUE; + } + else + { + /* Entry time was already set. */ + mtCOVERAGE_TEST_MARKER(); + } + } + } + taskEXIT_CRITICAL(); + + /* Interrupts and other tasks can send to and receive from the queue + * now the critical section has been exited. */ + + vTaskSuspendAll(); + prvLockQueue( pxQueue ); + + /* Update the timeout state to see if it has expired yet. */ + if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) + { + /* The timeout has not expired. If the queue is still empty place + * the task on the list of tasks waiting to receive from the queue. */ + if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) + { + traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ); + vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); + prvUnlockQueue( pxQueue ); + + if( xTaskResumeAll() == pdFALSE ) + { + taskYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* The queue contains data again. Loop back to try and read the + * data. */ + prvUnlockQueue( pxQueue ); + ( void ) xTaskResumeAll(); + } + } + else + { + /* Timed out. If there is no data in the queue exit, otherwise loop + * back and attempt to read the data. */ + prvUnlockQueue( pxQueue ); + ( void ) xTaskResumeAll(); + + if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) + { + traceQUEUE_RECEIVE_FAILED( pxQueue ); + traceRETURN_xQueueReceive( errQUEUE_EMPTY ); + + return errQUEUE_EMPTY; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) +{ + BaseType_t xEntryTimeSet = pdFALSE; + TimeOut_t xTimeOut; + Queue_t * const pxQueue = xQueue; + + #if ( configUSE_MUTEXES == 1 ) + BaseType_t xInheritanceOccurred = pdFALSE; + #endif + + traceENTER_xQueueSemaphoreTake( xQueue, xTicksToWait ); + + /* Check the queue pointer is not NULL. */ + configASSERT( ( pxQueue ) ); + + /* Check this really is a semaphore, in which case the item size will be + * 0. */ + configASSERT( pxQueue->uxItemSize == 0 ); + + /* Cannot block if the scheduler is suspended. */ + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + } + #endif + + for( ; ; ) + { + taskENTER_CRITICAL(); + { + /* Semaphores are queues with an item size of 0, and where the + * number of messages in the queue is the semaphore's count value. */ + const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting; + + /* Is there data in the queue now? To be running the calling task + * must be the highest priority task wanting to access the queue. */ + if( uxSemaphoreCount > ( UBaseType_t ) 0 ) + { + traceQUEUE_RECEIVE( pxQueue ); + + /* Semaphores are queues with a data size of zero and where the + * messages waiting is the semaphore's count. Reduce the count. */ + pxQueue->uxMessagesWaiting = ( UBaseType_t ) ( uxSemaphoreCount - ( UBaseType_t ) 1 ); + + #if ( configUSE_MUTEXES == 1 ) + { + if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) + { + /* Record the information required to implement + * priority inheritance should it become necessary. */ + pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_MUTEXES */ + + /* Check to see if other tasks are blocked waiting to give the + * semaphore, and if so, unblock the highest priority such task. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + { + queueYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + taskEXIT_CRITICAL(); + + traceRETURN_xQueueSemaphoreTake( pdPASS ); + + return pdPASS; + } + else + { + if( xTicksToWait == ( TickType_t ) 0 ) + { + /* The semaphore count was 0 and no block time is specified + * (or the block time has expired) so exit now. */ + taskEXIT_CRITICAL(); + + traceQUEUE_RECEIVE_FAILED( pxQueue ); + traceRETURN_xQueueSemaphoreTake( errQUEUE_EMPTY ); + + return errQUEUE_EMPTY; + } + else if( xEntryTimeSet == pdFALSE ) + { + /* The semaphore count was 0 and a block time was specified + * so configure the timeout structure ready to block. */ + vTaskInternalSetTimeOutState( &xTimeOut ); + xEntryTimeSet = pdTRUE; + } + else + { + /* Entry time was already set. */ + mtCOVERAGE_TEST_MARKER(); + } + } + } + taskEXIT_CRITICAL(); + + /* Interrupts and other tasks can give to and take from the semaphore + * now the critical section has been exited. */ + + vTaskSuspendAll(); + prvLockQueue( pxQueue ); + + /* Update the timeout state to see if it has expired yet. */ + if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) + { + /* A block time is specified and not expired. If the semaphore + * count is 0 then enter the Blocked state to wait for a semaphore to + * become available. As semaphores are implemented with queues the + * queue being empty is equivalent to the semaphore count being 0. */ + if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) + { + traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ); + + #if ( configUSE_MUTEXES == 1 ) + { + if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) + { + taskENTER_CRITICAL(); + { + xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder ); + } + taskEXIT_CRITICAL(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* if ( configUSE_MUTEXES == 1 ) */ + + vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); + prvUnlockQueue( pxQueue ); + + if( xTaskResumeAll() == pdFALSE ) + { + taskYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* There was no timeout and the semaphore count was not 0, so + * attempt to take the semaphore again. */ + prvUnlockQueue( pxQueue ); + ( void ) xTaskResumeAll(); + } + } + else + { + /* Timed out. */ + prvUnlockQueue( pxQueue ); + ( void ) xTaskResumeAll(); + + /* If the semaphore count is 0 exit now as the timeout has + * expired. Otherwise return to attempt to take the semaphore that is + * known to be available. As semaphores are implemented by queues the + * queue being empty is equivalent to the semaphore count being 0. */ + if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) + { + #if ( configUSE_MUTEXES == 1 ) + { + /* xInheritanceOccurred could only have be set if + * pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to + * test the mutex type again to check it is actually a mutex. */ + if( xInheritanceOccurred != pdFALSE ) + { + taskENTER_CRITICAL(); + { + UBaseType_t uxHighestWaitingPriority; + + /* This task blocking on the mutex caused another + * task to inherit this task's priority. Now this task + * has timed out the priority should be disinherited + * again, but only as low as the next highest priority + * task that is waiting for the same mutex. */ + uxHighestWaitingPriority = prvGetHighestPriorityOfWaitToReceiveList( pxQueue ); + + /* vTaskPriorityDisinheritAfterTimeout uses the uxHighestWaitingPriority + * parameter to index pxReadyTasksLists when adding the task holding + * mutex to the ready list for its new priority. Coverity thinks that + * it can result in out-of-bounds access which is not true because + * uxHighestWaitingPriority, as returned by prvGetHighestPriorityOfWaitToReceiveList, + * is capped at ( configMAX_PRIORITIES - 1 ). */ + /* coverity[overrun] */ + vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority ); + } + taskEXIT_CRITICAL(); + } + } + #endif /* configUSE_MUTEXES */ + + traceQUEUE_RECEIVE_FAILED( pxQueue ); + traceRETURN_xQueueSemaphoreTake( errQUEUE_EMPTY ); + + return errQUEUE_EMPTY; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) +{ + BaseType_t xEntryTimeSet = pdFALSE; + TimeOut_t xTimeOut; + int8_t * pcOriginalReadPosition; + Queue_t * const pxQueue = xQueue; + + traceENTER_xQueuePeek( xQueue, pvBuffer, xTicksToWait ); + + /* The buffer into which data is received can only be NULL if the data size + * is zero (so no data is copied into the buffer. */ + configASSERT( ( pxQueue != NULL ) && !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) ); + + /* Cannot block if the scheduler is suspended. */ + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + } + #endif + + for( ; ; ) + { + taskENTER_CRITICAL(); + { + const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; + + /* Is there data in the queue now? To be running the calling task + * must be the highest priority task wanting to access the queue. */ + if( uxMessagesWaiting > ( UBaseType_t ) 0 ) + { + /* Remember the read position so it can be reset after the data + * is read from the queue as this function is only peeking the + * data, not removing it. */ + pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom; + + prvCopyDataFromQueue( pxQueue, pvBuffer ); + traceQUEUE_PEEK( pxQueue ); + + /* The data is not being removed, so reset the read pointer. */ + pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition; + + /* The data is being left in the queue, so see if there are + * any other tasks waiting for the data. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The task waiting has a higher priority than this task. */ + queueYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + taskEXIT_CRITICAL(); + + traceRETURN_xQueuePeek( pdPASS ); + + return pdPASS; + } + else + { + if( xTicksToWait == ( TickType_t ) 0 ) + { + /* The queue was empty and no block time is specified (or + * the block time has expired) so leave now. */ + taskEXIT_CRITICAL(); + + traceQUEUE_PEEK_FAILED( pxQueue ); + traceRETURN_xQueuePeek( errQUEUE_EMPTY ); + + return errQUEUE_EMPTY; + } + else if( xEntryTimeSet == pdFALSE ) + { + /* The queue was empty and a block time was specified so + * configure the timeout structure ready to enter the blocked + * state. */ + vTaskInternalSetTimeOutState( &xTimeOut ); + xEntryTimeSet = pdTRUE; + } + else + { + /* Entry time was already set. */ + mtCOVERAGE_TEST_MARKER(); + } + } + } + taskEXIT_CRITICAL(); + + /* Interrupts and other tasks can send to and receive from the queue + * now that the critical section has been exited. */ + + vTaskSuspendAll(); + prvLockQueue( pxQueue ); + + /* Update the timeout state to see if it has expired yet. */ + if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) + { + /* Timeout has not expired yet, check to see if there is data in the + * queue now, and if not enter the Blocked state to wait for data. */ + if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) + { + traceBLOCKING_ON_QUEUE_PEEK( pxQueue ); + vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); + prvUnlockQueue( pxQueue ); + + if( xTaskResumeAll() == pdFALSE ) + { + taskYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* There is data in the queue now, so don't enter the blocked + * state, instead return to try and obtain the data. */ + prvUnlockQueue( pxQueue ); + ( void ) xTaskResumeAll(); + } + } + else + { + /* The timeout has expired. If there is still no data in the queue + * exit, otherwise go back and try to read the data again. */ + prvUnlockQueue( pxQueue ); + ( void ) xTaskResumeAll(); + + if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) + { + traceQUEUE_PEEK_FAILED( pxQueue ); + traceRETURN_xQueuePeek( errQUEUE_EMPTY ); + + return errQUEUE_EMPTY; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, + void * const pvBuffer, + BaseType_t * const pxHigherPriorityTaskWoken ) +{ + BaseType_t xReturn; + UBaseType_t uxSavedInterruptStatus; + Queue_t * const pxQueue = xQueue; + + traceENTER_xQueueReceiveFromISR( xQueue, pvBuffer, pxHigherPriorityTaskWoken ); + + configASSERT( pxQueue ); + configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); + + /* RTOS ports that support interrupt nesting have the concept of a maximum + * system call (or maximum API call) interrupt priority. Interrupts that are + * above the maximum system call priority are kept permanently enabled, even + * when the RTOS kernel is in a critical section, but cannot make any calls to + * FreeRTOS API functions. If configASSERT() is defined in FreeRTOSConfig.h + * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has been + * assigned a priority above the configured maximum system call priority. + * Only FreeRTOS functions that end in FromISR can be called from interrupts + * that have been assigned a priority at or (logically) below the maximum + * system call interrupt priority. FreeRTOS maintains a separate interrupt + * safe API to ensure interrupt entry is as fast and as simple as possible. + * More information (albeit Cortex-M specific) is provided on the following + * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + /* MISRA Ref 4.7.1 [Return value shall be checked] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */ + /* coverity[misra_c_2012_directive_4_7_violation] */ + uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR(); + { + const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; + + /* Cannot block in an ISR, so check there is data available. */ + if( uxMessagesWaiting > ( UBaseType_t ) 0 ) + { + const int8_t cRxLock = pxQueue->cRxLock; + + traceQUEUE_RECEIVE_FROM_ISR( pxQueue ); + + prvCopyDataFromQueue( pxQueue, pvBuffer ); + pxQueue->uxMessagesWaiting = ( UBaseType_t ) ( uxMessagesWaiting - ( UBaseType_t ) 1 ); + + /* If the queue is locked the event list will not be modified. + * Instead update the lock count so the task that unlocks the queue + * will know that an ISR has removed data while the queue was + * locked. */ + if( cRxLock == queueUNLOCKED ) + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + { + /* The task waiting has a higher priority than us so + * force a context switch. */ + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* Increment the lock count so the task that unlocks the queue + * knows that data was removed while it was locked. */ + prvIncrementQueueRxLock( pxQueue, cRxLock ); + } + + xReturn = pdPASS; + } + else + { + xReturn = pdFAIL; + traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue ); + } + } + taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + + traceRETURN_xQueueReceiveFromISR( xReturn ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, + void * const pvBuffer ) +{ + BaseType_t xReturn; + UBaseType_t uxSavedInterruptStatus; + int8_t * pcOriginalReadPosition; + Queue_t * const pxQueue = xQueue; + + traceENTER_xQueuePeekFromISR( xQueue, pvBuffer ); + + configASSERT( ( pxQueue != NULL ) && !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); + configASSERT( ( pxQueue != NULL ) && ( pxQueue->uxItemSize != 0 ) ); /* Can't peek a semaphore. */ + + /* RTOS ports that support interrupt nesting have the concept of a maximum + * system call (or maximum API call) interrupt priority. Interrupts that are + * above the maximum system call priority are kept permanently enabled, even + * when the RTOS kernel is in a critical section, but cannot make any calls to + * FreeRTOS API functions. If configASSERT() is defined in FreeRTOSConfig.h + * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has been + * assigned a priority above the configured maximum system call priority. + * Only FreeRTOS functions that end in FromISR can be called from interrupts + * that have been assigned a priority at or (logically) below the maximum + * system call interrupt priority. FreeRTOS maintains a separate interrupt + * safe API to ensure interrupt entry is as fast and as simple as possible. + * More information (albeit Cortex-M specific) is provided on the following + * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + /* MISRA Ref 4.7.1 [Return value shall be checked] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */ + /* coverity[misra_c_2012_directive_4_7_violation] */ + uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR(); + { + /* Cannot block in an ISR, so check there is data available. */ + if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 ) + { + traceQUEUE_PEEK_FROM_ISR( pxQueue ); + + /* Remember the read position so it can be reset as nothing is + * actually being removed from the queue. */ + pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom; + prvCopyDataFromQueue( pxQueue, pvBuffer ); + pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition; + + xReturn = pdPASS; + } + else + { + xReturn = pdFAIL; + traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue ); + } + } + taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + + traceRETURN_xQueuePeekFromISR( xReturn ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ) +{ + UBaseType_t uxReturn; + + traceENTER_uxQueueMessagesWaiting( xQueue ); + + configASSERT( xQueue ); + + portBASE_TYPE_ENTER_CRITICAL(); + { + uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting; + } + portBASE_TYPE_EXIT_CRITICAL(); + + traceRETURN_uxQueueMessagesWaiting( uxReturn ); + + return uxReturn; +} +/*-----------------------------------------------------------*/ + +UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ) +{ + UBaseType_t uxReturn; + Queue_t * const pxQueue = xQueue; + + traceENTER_uxQueueSpacesAvailable( xQueue ); + + configASSERT( pxQueue ); + + portBASE_TYPE_ENTER_CRITICAL(); + { + uxReturn = ( UBaseType_t ) ( pxQueue->uxLength - pxQueue->uxMessagesWaiting ); + } + portBASE_TYPE_EXIT_CRITICAL(); + + traceRETURN_uxQueueSpacesAvailable( uxReturn ); + + return uxReturn; +} +/*-----------------------------------------------------------*/ + +UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) +{ + UBaseType_t uxReturn; + Queue_t * const pxQueue = xQueue; + + traceENTER_uxQueueMessagesWaitingFromISR( xQueue ); + + configASSERT( pxQueue ); + uxReturn = pxQueue->uxMessagesWaiting; + + traceRETURN_uxQueueMessagesWaitingFromISR( uxReturn ); + + return uxReturn; +} +/*-----------------------------------------------------------*/ + +void vQueueDelete( QueueHandle_t xQueue ) +{ + Queue_t * const pxQueue = xQueue; + + traceENTER_vQueueDelete( xQueue ); + + configASSERT( pxQueue ); + traceQUEUE_DELETE( pxQueue ); + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + { + vQueueUnregisterQueue( pxQueue ); + } + #endif + + #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) ) + { + /* The queue can only have been allocated dynamically - free it + * again. */ + vPortFree( pxQueue ); + } + #elif ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + { + /* The queue could have been allocated statically or dynamically, so + * check before attempting to free the memory. */ + if( pxQueue->ucStaticallyAllocated == ( uint8_t ) pdFALSE ) + { + vPortFree( pxQueue ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #else /* if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) ) */ + { + /* The queue must have been statically allocated, so is not going to be + * deleted. Avoid compiler warnings about the unused parameter. */ + ( void ) pxQueue; + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + + traceRETURN_vQueueDelete(); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) + { + traceENTER_uxQueueGetQueueNumber( xQueue ); + + traceRETURN_uxQueueGetQueueNumber( ( ( Queue_t * ) xQueue )->uxQueueNumber ); + + return ( ( Queue_t * ) xQueue )->uxQueueNumber; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + void vQueueSetQueueNumber( QueueHandle_t xQueue, + UBaseType_t uxQueueNumber ) + { + traceENTER_vQueueSetQueueNumber( xQueue, uxQueueNumber ); + + ( ( Queue_t * ) xQueue )->uxQueueNumber = uxQueueNumber; + + traceRETURN_vQueueSetQueueNumber(); + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) + { + traceENTER_ucQueueGetQueueType( xQueue ); + + traceRETURN_ucQueueGetQueueType( ( ( Queue_t * ) xQueue )->ucQueueType ); + + return ( ( Queue_t * ) xQueue )->ucQueueType; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +UBaseType_t uxQueueGetQueueItemSize( QueueHandle_t xQueue ) /* PRIVILEGED_FUNCTION */ +{ + traceENTER_uxQueueGetQueueItemSize( xQueue ); + + traceRETURN_uxQueueGetQueueItemSize( ( ( Queue_t * ) xQueue )->uxItemSize ); + + return ( ( Queue_t * ) xQueue )->uxItemSize; +} +/*-----------------------------------------------------------*/ + +UBaseType_t uxQueueGetQueueLength( QueueHandle_t xQueue ) /* PRIVILEGED_FUNCTION */ +{ + traceENTER_uxQueueGetQueueLength( xQueue ); + + traceRETURN_uxQueueGetQueueLength( ( ( Queue_t * ) xQueue )->uxLength ); + + return ( ( Queue_t * ) xQueue )->uxLength; +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_MUTEXES == 1 ) + + static UBaseType_t prvGetHighestPriorityOfWaitToReceiveList( const Queue_t * const pxQueue ) + { + UBaseType_t uxHighestPriorityOfWaitingTasks; + + /* If a task waiting for a mutex causes the mutex holder to inherit a + * priority, but the waiting task times out, then the holder should + * disinherit the priority - but only down to the highest priority of any + * other tasks that are waiting for the same mutex. For this purpose, + * return the priority of the highest priority task that is waiting for the + * mutex. */ + if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U ) + { + uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) ( ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) ) ); + } + else + { + uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY; + } + + return uxHighestPriorityOfWaitingTasks; + } + +#endif /* configUSE_MUTEXES */ +/*-----------------------------------------------------------*/ + +static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, + const void * pvItemToQueue, + const BaseType_t xPosition ) +{ + BaseType_t xReturn = pdFALSE; + UBaseType_t uxMessagesWaiting; + + /* This function is called from a critical section. */ + + uxMessagesWaiting = pxQueue->uxMessagesWaiting; + + if( pxQueue->uxItemSize == ( UBaseType_t ) 0 ) + { + #if ( configUSE_MUTEXES == 1 ) + { + if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) + { + /* The mutex is no longer being held. */ + xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder ); + pxQueue->u.xSemaphore.xMutexHolder = NULL; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_MUTEXES */ + } + else if( xPosition == queueSEND_TO_BACK ) + { + ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); + pxQueue->pcWriteTo += pxQueue->uxItemSize; + + if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) + { + pxQueue->pcWriteTo = pxQueue->pcHead; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + ( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); + pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize; + + if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) + { + pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xPosition == queueOVERWRITE ) + { + if( uxMessagesWaiting > ( UBaseType_t ) 0 ) + { + /* An item is not being added but overwritten, so subtract + * one from the recorded number of items in the queue so when + * one is added again below the number of recorded items remains + * correct. */ + --uxMessagesWaiting; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + pxQueue->uxMessagesWaiting = ( UBaseType_t ) ( uxMessagesWaiting + ( UBaseType_t ) 1 ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static void prvCopyDataFromQueue( Queue_t * const pxQueue, + void * const pvBuffer ) +{ + if( pxQueue->uxItemSize != ( UBaseType_t ) 0 ) + { + pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; + + if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) + { + pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); + } +} +/*-----------------------------------------------------------*/ + +static void prvUnlockQueue( Queue_t * const pxQueue ) +{ + /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */ + + /* The lock counts contains the number of extra data items placed or + * removed from the queue while the queue was locked. When a queue is + * locked items can be added or removed, but the event lists cannot be + * updated. */ + taskENTER_CRITICAL(); + { + int8_t cTxLock = pxQueue->cTxLock; + + /* See if data was added to the queue while it was locked. */ + while( cTxLock > queueLOCKED_UNMODIFIED ) + { + /* Data was posted while the queue was locked. Are any tasks + * blocked waiting for data to become available? */ + #if ( configUSE_QUEUE_SETS == 1 ) + { + if( pxQueue->pxQueueSetContainer != NULL ) + { + if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE ) + { + /* The queue is a member of a queue set, and posting to + * the queue set caused a higher priority task to unblock. + * A context switch is required. */ + vTaskMissedYield(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* Tasks that are removed from the event list will get + * added to the pending ready list as the scheduler is still + * suspended. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The task waiting has a higher priority so record that a + * context switch is required. */ + vTaskMissedYield(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + break; + } + } + } + #else /* configUSE_QUEUE_SETS */ + { + /* Tasks that are removed from the event list will get added to + * the pending ready list as the scheduler is still suspended. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The task waiting has a higher priority so record that + * a context switch is required. */ + vTaskMissedYield(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + break; + } + } + #endif /* configUSE_QUEUE_SETS */ + + --cTxLock; + } + + pxQueue->cTxLock = queueUNLOCKED; + } + taskEXIT_CRITICAL(); + + /* Do the same for the Rx lock. */ + taskENTER_CRITICAL(); + { + int8_t cRxLock = pxQueue->cRxLock; + + while( cRxLock > queueLOCKED_UNMODIFIED ) + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + { + vTaskMissedYield(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + --cRxLock; + } + else + { + break; + } + } + + pxQueue->cRxLock = queueUNLOCKED; + } + taskEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvIsQueueEmpty( const Queue_t * pxQueue ) +{ + BaseType_t xReturn; + + taskENTER_CRITICAL(); + { + if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + } + taskEXIT_CRITICAL(); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) +{ + BaseType_t xReturn; + Queue_t * const pxQueue = xQueue; + + traceENTER_xQueueIsQueueEmptyFromISR( xQueue ); + + configASSERT( pxQueue ); + + if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + traceRETURN_xQueueIsQueueEmptyFromISR( xReturn ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvIsQueueFull( const Queue_t * pxQueue ) +{ + BaseType_t xReturn; + + taskENTER_CRITICAL(); + { + if( pxQueue->uxMessagesWaiting == pxQueue->uxLength ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + } + taskEXIT_CRITICAL(); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) +{ + BaseType_t xReturn; + Queue_t * const pxQueue = xQueue; + + traceENTER_xQueueIsQueueFullFromISR( xQueue ); + + configASSERT( pxQueue ); + + if( pxQueue->uxMessagesWaiting == pxQueue->uxLength ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + traceRETURN_xQueueIsQueueFullFromISR( xReturn ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_CO_ROUTINES == 1 ) + + BaseType_t xQueueCRSend( QueueHandle_t xQueue, + const void * pvItemToQueue, + TickType_t xTicksToWait ) + { + BaseType_t xReturn; + Queue_t * const pxQueue = xQueue; + + traceENTER_xQueueCRSend( xQueue, pvItemToQueue, xTicksToWait ); + + /* If the queue is already full we may have to block. A critical section + * is required to prevent an interrupt removing something from the queue + * between the check to see if the queue is full and blocking on the queue. */ + portDISABLE_INTERRUPTS(); + { + if( prvIsQueueFull( pxQueue ) != pdFALSE ) + { + /* The queue is full - do we want to block or just leave without + * posting? */ + if( xTicksToWait > ( TickType_t ) 0 ) + { + /* As this is called from a coroutine we cannot block directly, but + * return indicating that we need to block. */ + vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) ); + portENABLE_INTERRUPTS(); + return errQUEUE_BLOCKED; + } + else + { + portENABLE_INTERRUPTS(); + return errQUEUE_FULL; + } + } + } + portENABLE_INTERRUPTS(); + + portDISABLE_INTERRUPTS(); + { + if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) + { + /* There is room in the queue, copy the data into the queue. */ + prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK ); + xReturn = pdPASS; + + /* Were any co-routines waiting for data to become available? */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + /* In this instance the co-routine could be placed directly + * into the ready list as we are within a critical section. + * Instead the same pending ready list mechanism is used as if + * the event were caused from within an interrupt. */ + if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The co-routine waiting has a higher priority so record + * that a yield might be appropriate. */ + xReturn = errQUEUE_YIELD; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + xReturn = errQUEUE_FULL; + } + } + portENABLE_INTERRUPTS(); + + traceRETURN_xQueueCRSend( xReturn ); + + return xReturn; + } + +#endif /* configUSE_CO_ROUTINES */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_CO_ROUTINES == 1 ) + + BaseType_t xQueueCRReceive( QueueHandle_t xQueue, + void * pvBuffer, + TickType_t xTicksToWait ) + { + BaseType_t xReturn; + Queue_t * const pxQueue = xQueue; + + traceENTER_xQueueCRReceive( xQueue, pvBuffer, xTicksToWait ); + + /* If the queue is already empty we may have to block. A critical section + * is required to prevent an interrupt adding something to the queue + * between the check to see if the queue is empty and blocking on the queue. */ + portDISABLE_INTERRUPTS(); + { + if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 ) + { + /* There are no messages in the queue, do we want to block or just + * leave with nothing? */ + if( xTicksToWait > ( TickType_t ) 0 ) + { + /* As this is a co-routine we cannot block directly, but return + * indicating that we need to block. */ + vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) ); + portENABLE_INTERRUPTS(); + return errQUEUE_BLOCKED; + } + else + { + portENABLE_INTERRUPTS(); + return errQUEUE_FULL; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + portENABLE_INTERRUPTS(); + + portDISABLE_INTERRUPTS(); + { + if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 ) + { + /* Data is available from the queue. */ + pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; + + if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) + { + pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + --( pxQueue->uxMessagesWaiting ); + ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); + + xReturn = pdPASS; + + /* Were any co-routines waiting for space to become available? */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + { + /* In this instance the co-routine could be placed directly + * into the ready list as we are within a critical section. + * Instead the same pending ready list mechanism is used as if + * the event were caused from within an interrupt. */ + if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + { + xReturn = errQUEUE_YIELD; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + xReturn = pdFAIL; + } + } + portENABLE_INTERRUPTS(); + + traceRETURN_xQueueCRReceive( xReturn ); + + return xReturn; + } + +#endif /* configUSE_CO_ROUTINES */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_CO_ROUTINES == 1 ) + + BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, + const void * pvItemToQueue, + BaseType_t xCoRoutinePreviouslyWoken ) + { + Queue_t * const pxQueue = xQueue; + + traceENTER_xQueueCRSendFromISR( xQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ); + + /* Cannot block within an ISR so if there is no space on the queue then + * exit without doing anything. */ + if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) + { + prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK ); + + /* We only want to wake one co-routine per ISR, so check that a + * co-routine has not already been woken. */ + if( xCoRoutinePreviouslyWoken == pdFALSE ) + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + return pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceRETURN_xQueueCRSendFromISR( xCoRoutinePreviouslyWoken ); + + return xCoRoutinePreviouslyWoken; + } + +#endif /* configUSE_CO_ROUTINES */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_CO_ROUTINES == 1 ) + + BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, + void * pvBuffer, + BaseType_t * pxCoRoutineWoken ) + { + BaseType_t xReturn; + Queue_t * const pxQueue = xQueue; + + traceENTER_xQueueCRReceiveFromISR( xQueue, pvBuffer, pxCoRoutineWoken ); + + /* We cannot block from an ISR, so check there is data available. If + * not then just leave without doing anything. */ + if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 ) + { + /* Copy the data from the queue. */ + pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; + + if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) + { + pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + --( pxQueue->uxMessagesWaiting ); + ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); + + if( ( *pxCoRoutineWoken ) == pdFALSE ) + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + { + if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + { + *pxCoRoutineWoken = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xReturn = pdPASS; + } + else + { + xReturn = pdFAIL; + } + + traceRETURN_xQueueCRReceiveFromISR( xReturn ); + + return xReturn; + } + +#endif /* configUSE_CO_ROUTINES */ +/*-----------------------------------------------------------*/ + +#if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcQueueName ) + { + UBaseType_t ux; + QueueRegistryItem_t * pxEntryToWrite = NULL; + + traceENTER_vQueueAddToRegistry( xQueue, pcQueueName ); + + configASSERT( xQueue ); + + if( pcQueueName != NULL ) + { + /* See if there is an empty space in the registry. A NULL name denotes + * a free slot. */ + for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) + { + /* Replace an existing entry if the queue is already in the registry. */ + if( xQueue == xQueueRegistry[ ux ].xHandle ) + { + pxEntryToWrite = &( xQueueRegistry[ ux ] ); + break; + } + /* Otherwise, store in the next empty location */ + else if( ( pxEntryToWrite == NULL ) && ( xQueueRegistry[ ux ].pcQueueName == NULL ) ) + { + pxEntryToWrite = &( xQueueRegistry[ ux ] ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + + if( pxEntryToWrite != NULL ) + { + /* Store the information on this queue. */ + pxEntryToWrite->pcQueueName = pcQueueName; + pxEntryToWrite->xHandle = xQueue; + + traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName ); + } + + traceRETURN_vQueueAddToRegistry(); + } + +#endif /* configQUEUE_REGISTRY_SIZE */ +/*-----------------------------------------------------------*/ + +#if ( configQUEUE_REGISTRY_SIZE > 0 ) + + const char * pcQueueGetName( QueueHandle_t xQueue ) + { + UBaseType_t ux; + const char * pcReturn = NULL; + + traceENTER_pcQueueGetName( xQueue ); + + configASSERT( xQueue ); + + /* Note there is nothing here to protect against another task adding or + * removing entries from the registry while it is being searched. */ + + for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) + { + if( xQueueRegistry[ ux ].xHandle == xQueue ) + { + pcReturn = xQueueRegistry[ ux ].pcQueueName; + break; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + traceRETURN_pcQueueGetName( pcReturn ); + + return pcReturn; + } + +#endif /* configQUEUE_REGISTRY_SIZE */ +/*-----------------------------------------------------------*/ + +#if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void vQueueUnregisterQueue( QueueHandle_t xQueue ) + { + UBaseType_t ux; + + traceENTER_vQueueUnregisterQueue( xQueue ); + + configASSERT( xQueue ); + + /* See if the handle of the queue being unregistered in actually in the + * registry. */ + for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) + { + if( xQueueRegistry[ ux ].xHandle == xQueue ) + { + /* Set the name to NULL to show that this slot if free again. */ + xQueueRegistry[ ux ].pcQueueName = NULL; + + /* Set the handle to NULL to ensure the same queue handle cannot + * appear in the registry twice if it is added, removed, then + * added again. */ + xQueueRegistry[ ux ].xHandle = ( QueueHandle_t ) 0; + break; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + traceRETURN_vQueueUnregisterQueue(); + } + +#endif /* configQUEUE_REGISTRY_SIZE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TIMERS == 1 ) + + void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, + TickType_t xTicksToWait, + const BaseType_t xWaitIndefinitely ) + { + Queue_t * const pxQueue = xQueue; + + traceENTER_vQueueWaitForMessageRestricted( xQueue, xTicksToWait, xWaitIndefinitely ); + + /* This function should not be called by application code hence the + * 'Restricted' in its name. It is not part of the public API. It is + * designed for use by kernel code, and has special calling requirements. + * It can result in vListInsert() being called on a list that can only + * possibly ever have one item in it, so the list will be fast, but even + * so it should be called with the scheduler locked and not from a critical + * section. */ + + /* Only do anything if there are no messages in the queue. This function + * will not actually cause the task to block, just place it on a blocked + * list. It will not block until the scheduler is unlocked - at which + * time a yield will be performed. If an item is added to the queue while + * the queue is locked, and the calling task blocks on the queue, then the + * calling task will be immediately unblocked when the queue is unlocked. */ + prvLockQueue( pxQueue ); + + if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U ) + { + /* There is nothing in the queue, block for the specified period. */ + vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + prvUnlockQueue( pxQueue ); + + traceRETURN_vQueueWaitForMessageRestricted(); + } + +#endif /* configUSE_TIMERS */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + + QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) + { + QueueSetHandle_t pxQueue; + + traceENTER_xQueueCreateSet( uxEventQueueLength ); + + pxQueue = xQueueGenericCreate( uxEventQueueLength, ( UBaseType_t ) sizeof( Queue_t * ), queueQUEUE_TYPE_SET ); + + traceRETURN_xQueueCreateSet( pxQueue ); + + return pxQueue; + } + +#endif /* #if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + + QueueSetHandle_t xQueueCreateSetStatic( const UBaseType_t uxEventQueueLength, + uint8_t * pucQueueStorage, + StaticQueue_t * pxStaticQueue ) + { + QueueSetHandle_t pxQueue; + + traceENTER_xQueueCreateSetStatic( uxEventQueueLength ); + + pxQueue = xQueueGenericCreateStatic( uxEventQueueLength, ( UBaseType_t ) sizeof( Queue_t * ), pucQueueStorage, pxStaticQueue, queueQUEUE_TYPE_SET ); + + traceRETURN_xQueueCreateSetStatic( pxQueue ); + + return pxQueue; + } + +#endif /* #if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_QUEUE_SETS == 1 ) + + BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) + { + BaseType_t xReturn; + + traceENTER_xQueueAddToSet( xQueueOrSemaphore, xQueueSet ); + + taskENTER_CRITICAL(); + { + if( ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer != NULL ) + { + /* Cannot add a queue/semaphore to more than one queue set. */ + xReturn = pdFAIL; + } + else if( ( ( Queue_t * ) xQueueOrSemaphore )->uxMessagesWaiting != ( UBaseType_t ) 0 ) + { + /* Cannot add a queue/semaphore to a queue set if there are already + * items in the queue/semaphore. */ + xReturn = pdFAIL; + } + else + { + ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer = xQueueSet; + xReturn = pdPASS; + } + } + taskEXIT_CRITICAL(); + + traceRETURN_xQueueAddToSet( xReturn ); + + return xReturn; + } + +#endif /* configUSE_QUEUE_SETS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_QUEUE_SETS == 1 ) + + BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) + { + BaseType_t xReturn; + Queue_t * const pxQueueOrSemaphore = ( Queue_t * ) xQueueOrSemaphore; + + traceENTER_xQueueRemoveFromSet( xQueueOrSemaphore, xQueueSet ); + + if( pxQueueOrSemaphore->pxQueueSetContainer != xQueueSet ) + { + /* The queue was not a member of the set. */ + xReturn = pdFAIL; + } + else if( pxQueueOrSemaphore->uxMessagesWaiting != ( UBaseType_t ) 0 ) + { + /* It is dangerous to remove a queue from a set when the queue is + * not empty because the queue set will still hold pending events for + * the queue. */ + xReturn = pdFAIL; + } + else + { + taskENTER_CRITICAL(); + { + /* The queue is no longer contained in the set. */ + pxQueueOrSemaphore->pxQueueSetContainer = NULL; + } + taskEXIT_CRITICAL(); + xReturn = pdPASS; + } + + traceRETURN_xQueueRemoveFromSet( xReturn ); + + return xReturn; + } + +#endif /* configUSE_QUEUE_SETS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_QUEUE_SETS == 1 ) + + QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + TickType_t const xTicksToWait ) + { + QueueSetMemberHandle_t xReturn = NULL; + + traceENTER_xQueueSelectFromSet( xQueueSet, xTicksToWait ); + + ( void ) xQueueReceive( ( QueueHandle_t ) xQueueSet, &xReturn, xTicksToWait ); + + traceRETURN_xQueueSelectFromSet( xReturn ); + + return xReturn; + } + +#endif /* configUSE_QUEUE_SETS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_QUEUE_SETS == 1 ) + + QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) + { + QueueSetMemberHandle_t xReturn = NULL; + + traceENTER_xQueueSelectFromSetFromISR( xQueueSet ); + + ( void ) xQueueReceiveFromISR( ( QueueHandle_t ) xQueueSet, &xReturn, NULL ); + + traceRETURN_xQueueSelectFromSetFromISR( xReturn ); + + return xReturn; + } + +#endif /* configUSE_QUEUE_SETS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_QUEUE_SETS == 1 ) + + static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue ) + { + Queue_t * pxQueueSetContainer = pxQueue->pxQueueSetContainer; + BaseType_t xReturn = pdFALSE; + + /* This function must be called form a critical section. */ + + /* The following line is not reachable in unit tests because every call + * to prvNotifyQueueSetContainer is preceded by a check that + * pxQueueSetContainer != NULL */ + configASSERT( pxQueueSetContainer ); /* LCOV_EXCL_BR_LINE */ + configASSERT( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength ); + + if( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength ) + { + const int8_t cTxLock = pxQueueSetContainer->cTxLock; + + traceQUEUE_SET_SEND( pxQueueSetContainer ); + + /* The data copied is the handle of the queue that contains data. */ + xReturn = prvCopyDataToQueue( pxQueueSetContainer, &pxQueue, queueSEND_TO_BACK ); + + if( cTxLock == queueUNLOCKED ) + { + if( listLIST_IS_EMPTY( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The task waiting has a higher priority. */ + xReturn = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + prvIncrementQueueTxLock( pxQueueSetContainer, cTxLock ); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xReturn; + } + +#endif /* configUSE_QUEUE_SETS */ diff --git a/readme.txt b/readme.txt deleted file mode 100644 index 49eecd6cd..000000000 --- a/readme.txt +++ /dev/null @@ -1,19 +0,0 @@ -The download includes the kernel source code, and a demo application for EVERY -RTOS port. See http://www.freertos.org/a00017.html for full details of the -directory structure and information on locating the files you require. - -The easiest way to use FreeRTOS is start start with one of the demo application -projects. Once this is running the project can be modified to include your own -source files. This way the correct files and compiler options will be -automatically included in your application. - -+ The Source directory contains the real time kernel source files for every -port. The kernel itself is only 3 files. - -+ The Demo directory contains the demo application source files for every -port. - -+ The TraceCon directory contains the trace visualisation exe file. - -See the readme files in the respective directories for further information. - diff --git a/stream_buffer.c b/stream_buffer.c new file mode 100644 index 000000000..287bd0736 --- /dev/null +++ b/stream_buffer.c @@ -0,0 +1,1719 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "stream_buffer.h" + +/* The MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined + * for the header files above, but not in this file, in order to generate the + * correct privileged Vs unprivileged linkage and placement. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* This entire source file will be skipped if the application is not configured + * to include stream buffer functionality. This #if is closed at the very bottom + * of this file. If you want to include stream buffers then ensure + * configUSE_STREAM_BUFFERS is set to 1 in FreeRTOSConfig.h. */ +#if ( configUSE_STREAM_BUFFERS == 1 ) + + #if ( configUSE_TASK_NOTIFICATIONS != 1 ) + #error configUSE_TASK_NOTIFICATIONS must be set to 1 to build stream_buffer.c + #endif + + #if ( INCLUDE_xTaskGetCurrentTaskHandle != 1 ) + #error INCLUDE_xTaskGetCurrentTaskHandle must be set to 1 to build stream_buffer.c + #endif + +/* If the user has not provided application specific Rx notification macros, + * or #defined the notification macros away, then provide default implementations + * that uses task notifications. */ + #ifndef sbRECEIVE_COMPLETED + #define sbRECEIVE_COMPLETED( pxStreamBuffer ) \ + do \ + { \ + vTaskSuspendAll(); \ + { \ + if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL ) \ + { \ + ( void ) xTaskNotifyIndexed( ( pxStreamBuffer )->xTaskWaitingToSend, \ + ( pxStreamBuffer )->uxNotificationIndex, \ + ( uint32_t ) 0, \ + eNoAction ); \ + ( pxStreamBuffer )->xTaskWaitingToSend = NULL; \ + } \ + } \ + ( void ) xTaskResumeAll(); \ + } while( 0 ) + #endif /* sbRECEIVE_COMPLETED */ + +/* If user has provided a per-instance receive complete callback, then + * invoke the callback else use the receive complete macro which is provided by default for all instances. + */ + #if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) + #define prvRECEIVE_COMPLETED( pxStreamBuffer ) \ + do { \ + if( ( pxStreamBuffer )->pxReceiveCompletedCallback != NULL ) \ + { \ + ( pxStreamBuffer )->pxReceiveCompletedCallback( ( pxStreamBuffer ), pdFALSE, NULL ); \ + } \ + else \ + { \ + sbRECEIVE_COMPLETED( ( pxStreamBuffer ) ); \ + } \ + } while( 0 ) + #else /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */ + #define prvRECEIVE_COMPLETED( pxStreamBuffer ) sbRECEIVE_COMPLETED( ( pxStreamBuffer ) ) + #endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */ + + #ifndef sbRECEIVE_COMPLETED_FROM_ISR + #define sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, \ + pxHigherPriorityTaskWoken ) \ + do { \ + UBaseType_t uxSavedInterruptStatus; \ + \ + uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR(); \ + { \ + if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL ) \ + { \ + ( void ) xTaskNotifyIndexedFromISR( ( pxStreamBuffer )->xTaskWaitingToSend, \ + ( pxStreamBuffer )->uxNotificationIndex, \ + ( uint32_t ) 0, \ + eNoAction, \ + ( pxHigherPriorityTaskWoken ) ); \ + ( pxStreamBuffer )->xTaskWaitingToSend = NULL; \ + } \ + } \ + taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); \ + } while( 0 ) + #endif /* sbRECEIVE_COMPLETED_FROM_ISR */ + + #if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) + #define prvRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, \ + pxHigherPriorityTaskWoken ) \ + do { \ + if( ( pxStreamBuffer )->pxReceiveCompletedCallback != NULL ) \ + { \ + ( pxStreamBuffer )->pxReceiveCompletedCallback( ( pxStreamBuffer ), pdTRUE, ( pxHigherPriorityTaskWoken ) ); \ + } \ + else \ + { \ + sbRECEIVE_COMPLETED_FROM_ISR( ( pxStreamBuffer ), ( pxHigherPriorityTaskWoken ) ); \ + } \ + } while( 0 ) + #else /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */ + #define prvRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken ) \ + sbRECEIVE_COMPLETED_FROM_ISR( ( pxStreamBuffer ), ( pxHigherPriorityTaskWoken ) ) + #endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */ + +/* If the user has not provided an application specific Tx notification macro, + * or #defined the notification macro away, then provide a default + * implementation that uses task notifications. + */ + #ifndef sbSEND_COMPLETED + #define sbSEND_COMPLETED( pxStreamBuffer ) \ + vTaskSuspendAll(); \ + { \ + if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL ) \ + { \ + ( void ) xTaskNotifyIndexed( ( pxStreamBuffer )->xTaskWaitingToReceive, \ + ( pxStreamBuffer )->uxNotificationIndex, \ + ( uint32_t ) 0, \ + eNoAction ); \ + ( pxStreamBuffer )->xTaskWaitingToReceive = NULL; \ + } \ + } \ + ( void ) xTaskResumeAll() + #endif /* sbSEND_COMPLETED */ + +/* If user has provided a per-instance send completed callback, then + * invoke the callback else use the send complete macro which is provided by default for all instances. + */ + #if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) + #define prvSEND_COMPLETED( pxStreamBuffer ) \ + do { \ + if( ( pxStreamBuffer )->pxSendCompletedCallback != NULL ) \ + { \ + ( pxStreamBuffer )->pxSendCompletedCallback( ( pxStreamBuffer ), pdFALSE, NULL ); \ + } \ + else \ + { \ + sbSEND_COMPLETED( ( pxStreamBuffer ) ); \ + } \ + } while( 0 ) + #else /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */ + #define prvSEND_COMPLETED( pxStreamBuffer ) sbSEND_COMPLETED( ( pxStreamBuffer ) ) + #endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */ + + + #ifndef sbSEND_COMPLETE_FROM_ISR + #define sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken ) \ + do { \ + UBaseType_t uxSavedInterruptStatus; \ + \ + uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR(); \ + { \ + if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL ) \ + { \ + ( void ) xTaskNotifyIndexedFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive, \ + ( pxStreamBuffer )->uxNotificationIndex, \ + ( uint32_t ) 0, \ + eNoAction, \ + ( pxHigherPriorityTaskWoken ) ); \ + ( pxStreamBuffer )->xTaskWaitingToReceive = NULL; \ + } \ + } \ + taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); \ + } while( 0 ) + #endif /* sbSEND_COMPLETE_FROM_ISR */ + + + #if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) + #define prvSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken ) \ + do { \ + if( ( pxStreamBuffer )->pxSendCompletedCallback != NULL ) \ + { \ + ( pxStreamBuffer )->pxSendCompletedCallback( ( pxStreamBuffer ), pdTRUE, ( pxHigherPriorityTaskWoken ) ); \ + } \ + else \ + { \ + sbSEND_COMPLETE_FROM_ISR( ( pxStreamBuffer ), ( pxHigherPriorityTaskWoken ) ); \ + } \ + } while( 0 ) + #else /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */ + #define prvSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken ) \ + sbSEND_COMPLETE_FROM_ISR( ( pxStreamBuffer ), ( pxHigherPriorityTaskWoken ) ) + #endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */ + +/* The number of bytes used to hold the length of a message in the buffer. */ + #define sbBYTES_TO_STORE_MESSAGE_LENGTH ( sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) ) + +/* Bits stored in the ucFlags field of the stream buffer. */ + #define sbFLAGS_IS_MESSAGE_BUFFER ( ( uint8_t ) 1 ) /* Set if the stream buffer was created as a message buffer, in which case it holds discrete messages rather than a stream. */ + #define sbFLAGS_IS_STATICALLY_ALLOCATED ( ( uint8_t ) 2 ) /* Set if the stream buffer was created using statically allocated memory. */ + #define sbFLAGS_IS_BATCHING_BUFFER ( ( uint8_t ) 4 ) /* Set if the stream buffer was created as a batching buffer, meaning the receiver task will only unblock when the trigger level exceededs. */ + +/*-----------------------------------------------------------*/ + +/* Structure that hold state information on the buffer. */ +typedef struct StreamBufferDef_t +{ + volatile size_t xTail; /* Index to the next item to read within the buffer. */ + volatile size_t xHead; /* Index to the next item to write within the buffer. */ + size_t xLength; /* The length of the buffer pointed to by pucBuffer. */ + size_t xTriggerLevelBytes; /* The number of bytes that must be in the stream buffer before a task that is waiting for data is unblocked. */ + volatile TaskHandle_t xTaskWaitingToReceive; /* Holds the handle of a task waiting for data, or NULL if no tasks are waiting. */ + volatile TaskHandle_t xTaskWaitingToSend; /* Holds the handle of a task waiting to send data to a message buffer that is full. */ + uint8_t * pucBuffer; /* Points to the buffer itself - that is - the RAM that stores the data passed through the buffer. */ + uint8_t ucFlags; + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxStreamBufferNumber; /* Used for tracing purposes. */ + #endif + + #if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) + StreamBufferCallbackFunction_t pxSendCompletedCallback; /* Optional callback called on send complete. sbSEND_COMPLETED is called if this is NULL. */ + StreamBufferCallbackFunction_t pxReceiveCompletedCallback; /* Optional callback called on receive complete. sbRECEIVE_COMPLETED is called if this is NULL. */ + #endif + UBaseType_t uxNotificationIndex; /* The index we are using for notification, by default tskDEFAULT_INDEX_TO_NOTIFY. */ +} StreamBuffer_t; + +/* + * The number of bytes available to be read from the buffer. + */ +static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer ) PRIVILEGED_FUNCTION; + +/* + * Add xCount bytes from pucData into the pxStreamBuffer's data storage area. + * This function does not update the buffer's xHead pointer, so multiple writes + * may be chained together "atomically". This is useful for Message Buffers where + * the length and data bytes are written in two separate chunks, and we don't want + * the reader to see the buffer as having grown until after all data is copied over. + * This function takes a custom xHead value to indicate where to write to (necessary + * for chaining) and returns the the resulting xHead position. + * To mark the write as complete, manually set the buffer's xHead field with the + * returned xHead from this function. + */ +static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, + const uint8_t * pucData, + size_t xCount, + size_t xHead ) PRIVILEGED_FUNCTION; + +/* + * If the stream buffer is being used as a message buffer, then reads an entire + * message out of the buffer. If the stream buffer is being used as a stream + * buffer then read as many bytes as possible from the buffer. + * prvReadBytesFromBuffer() is called to actually extract the bytes from the + * buffer's data storage area. + */ +static size_t prvReadMessageFromBuffer( StreamBuffer_t * pxStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + size_t xBytesAvailable ) PRIVILEGED_FUNCTION; + +/* + * If the stream buffer is being used as a message buffer, then writes an entire + * message to the buffer. If the stream buffer is being used as a stream + * buffer then write as many bytes as possible to the buffer. + * prvWriteBytestoBuffer() is called to actually send the bytes to the buffer's + * data storage area. + */ +static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + size_t xSpace, + size_t xRequiredSpace ) PRIVILEGED_FUNCTION; + +/* + * Copies xCount bytes from the pxStreamBuffer's data storage area to pucData. + * This function does not update the buffer's xTail pointer, so multiple reads + * may be chained together "atomically". This is useful for Message Buffers where + * the length and data bytes are read in two separate chunks, and we don't want + * the writer to see the buffer as having more free space until after all data is + * copied over, especially if we have to abort the read due to insufficient receiving space. + * This function takes a custom xTail value to indicate where to read from (necessary + * for chaining) and returns the the resulting xTail position. + * To mark the read as complete, manually set the buffer's xTail field with the + * returned xTail from this function. + */ +static size_t prvReadBytesFromBuffer( StreamBuffer_t * pxStreamBuffer, + uint8_t * pucData, + size_t xCount, + size_t xTail ) PRIVILEGED_FUNCTION; + +/* + * Called by both pxStreamBufferCreate() and pxStreamBufferCreateStatic() to + * initialise the members of the newly created stream buffer structure. + */ +static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer, + uint8_t * const pucBuffer, + size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + uint8_t ucFlags, + StreamBufferCallbackFunction_t pxSendCompletedCallback, + StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION; + +/*-----------------------------------------------------------*/ + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + BaseType_t xStreamBufferType, + StreamBufferCallbackFunction_t pxSendCompletedCallback, + StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) + { + void * pvAllocatedMemory; + uint8_t ucFlags; + + traceENTER_xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, xStreamBufferType, pxSendCompletedCallback, pxReceiveCompletedCallback ); + + /* In case the stream buffer is going to be used as a message buffer + * (that is, it will hold discrete messages with a little meta data that + * says how big the next message is) check the buffer will be large enough + * to hold at least one message. */ + if( xStreamBufferType == sbTYPE_MESSAGE_BUFFER ) + { + /* Is a message buffer but not statically allocated. */ + ucFlags = sbFLAGS_IS_MESSAGE_BUFFER; + configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH ); + } + else if( xStreamBufferType == sbTYPE_STREAM_BATCHING_BUFFER ) + { + /* Is a batching buffer but not statically allocated. */ + ucFlags = sbFLAGS_IS_BATCHING_BUFFER; + configASSERT( xBufferSizeBytes > 0 ); + } + else + { + /* Not a message buffer and not statically allocated. */ + ucFlags = 0; + configASSERT( xBufferSizeBytes > 0 ); + } + + configASSERT( xTriggerLevelBytes <= xBufferSizeBytes ); + + /* A trigger level of 0 would cause a waiting task to unblock even when + * the buffer was empty. */ + if( xTriggerLevelBytes == ( size_t ) 0 ) + { + xTriggerLevelBytes = ( size_t ) 1; + } + + /* A stream buffer requires a StreamBuffer_t structure and a buffer. + * Both are allocated in a single call to pvPortMalloc(). The + * StreamBuffer_t structure is placed at the start of the allocated memory + * and the buffer follows immediately after. The requested size is + * incremented so the free space is returned as the user would expect - + * this is a quirk of the implementation that means otherwise the free + * space would be reported as one byte smaller than would be logically + * expected. */ + if( xBufferSizeBytes < ( xBufferSizeBytes + 1U + sizeof( StreamBuffer_t ) ) ) + { + xBufferSizeBytes++; + pvAllocatedMemory = pvPortMalloc( xBufferSizeBytes + sizeof( StreamBuffer_t ) ); + } + else + { + pvAllocatedMemory = NULL; + } + + if( pvAllocatedMemory != NULL ) + { + /* MISRA Ref 11.5.1 [Malloc memory assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + prvInitialiseNewStreamBuffer( ( StreamBuffer_t * ) pvAllocatedMemory, /* Structure at the start of the allocated memory. */ + /* MISRA Ref 11.5.1 [Malloc memory assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + ( ( uint8_t * ) pvAllocatedMemory ) + sizeof( StreamBuffer_t ), /* Storage area follows. */ + xBufferSizeBytes, + xTriggerLevelBytes, + ucFlags, + pxSendCompletedCallback, + pxReceiveCompletedCallback ); + + traceSTREAM_BUFFER_CREATE( ( ( StreamBuffer_t * ) pvAllocatedMemory ), xStreamBufferType ); + } + else + { + traceSTREAM_BUFFER_CREATE_FAILED( xStreamBufferType ); + } + + traceRETURN_xStreamBufferGenericCreate( pvAllocatedMemory ); + + /* MISRA Ref 11.5.1 [Malloc memory assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + return ( StreamBufferHandle_t ) pvAllocatedMemory; + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + + StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + BaseType_t xStreamBufferType, + uint8_t * const pucStreamBufferStorageArea, + StaticStreamBuffer_t * const pxStaticStreamBuffer, + StreamBufferCallbackFunction_t pxSendCompletedCallback, + StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) + { + /* MISRA Ref 11.3.1 [Misaligned access] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */ + /* coverity[misra_c_2012_rule_11_3_violation] */ + StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) pxStaticStreamBuffer; + StreamBufferHandle_t xReturn; + uint8_t ucFlags; + + traceENTER_xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, xStreamBufferType, pucStreamBufferStorageArea, pxStaticStreamBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback ); + + configASSERT( pucStreamBufferStorageArea ); + configASSERT( pxStaticStreamBuffer ); + configASSERT( xTriggerLevelBytes <= xBufferSizeBytes ); + + /* A trigger level of 0 would cause a waiting task to unblock even when + * the buffer was empty. */ + if( xTriggerLevelBytes == ( size_t ) 0 ) + { + xTriggerLevelBytes = ( size_t ) 1; + } + + /* In case the stream buffer is going to be used as a message buffer + * (that is, it will hold discrete messages with a little meta data that + * says how big the next message is) check the buffer will be large enough + * to hold at least one message. */ + + if( xStreamBufferType == sbTYPE_MESSAGE_BUFFER ) + { + /* Statically allocated message buffer. */ + ucFlags = sbFLAGS_IS_MESSAGE_BUFFER | sbFLAGS_IS_STATICALLY_ALLOCATED; + configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH ); + } + else if( xStreamBufferType == sbTYPE_STREAM_BATCHING_BUFFER ) + { + /* Statically allocated batching buffer. */ + ucFlags = sbFLAGS_IS_BATCHING_BUFFER | sbFLAGS_IS_STATICALLY_ALLOCATED; + configASSERT( xBufferSizeBytes > 0 ); + } + else + { + /* Statically allocated stream buffer. */ + ucFlags = sbFLAGS_IS_STATICALLY_ALLOCATED; + } + + #if ( configASSERT_DEFINED == 1 ) + { + /* Sanity check that the size of the structure used to declare a + * variable of type StaticStreamBuffer_t equals the size of the real + * message buffer structure. */ + volatile size_t xSize = sizeof( StaticStreamBuffer_t ); + configASSERT( xSize == sizeof( StreamBuffer_t ) ); + } + #endif /* configASSERT_DEFINED */ + + if( ( pucStreamBufferStorageArea != NULL ) && ( pxStaticStreamBuffer != NULL ) ) + { + prvInitialiseNewStreamBuffer( pxStreamBuffer, + pucStreamBufferStorageArea, + xBufferSizeBytes, + xTriggerLevelBytes, + ucFlags, + pxSendCompletedCallback, + pxReceiveCompletedCallback ); + + /* Remember this was statically allocated in case it is ever deleted + * again. */ + pxStreamBuffer->ucFlags |= sbFLAGS_IS_STATICALLY_ALLOCATED; + + traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xStreamBufferType ); + + /* MISRA Ref 11.3.1 [Misaligned access] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */ + /* coverity[misra_c_2012_rule_11_3_violation] */ + xReturn = ( StreamBufferHandle_t ) pxStaticStreamBuffer; + } + else + { + xReturn = NULL; + traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xStreamBufferType ); + } + + traceRETURN_xStreamBufferGenericCreateStatic( xReturn ); + + return xReturn; + } + #endif /* ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ +/*-----------------------------------------------------------*/ + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + BaseType_t xStreamBufferGetStaticBuffers( StreamBufferHandle_t xStreamBuffer, + uint8_t ** ppucStreamBufferStorageArea, + StaticStreamBuffer_t ** ppxStaticStreamBuffer ) + { + BaseType_t xReturn; + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + + traceENTER_xStreamBufferGetStaticBuffers( xStreamBuffer, ppucStreamBufferStorageArea, ppxStaticStreamBuffer ); + + configASSERT( pxStreamBuffer ); + configASSERT( ppucStreamBufferStorageArea ); + configASSERT( ppxStaticStreamBuffer ); + + if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_STATICALLY_ALLOCATED ) != ( uint8_t ) 0 ) + { + *ppucStreamBufferStorageArea = pxStreamBuffer->pucBuffer; + /* MISRA Ref 11.3.1 [Misaligned access] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */ + /* coverity[misra_c_2012_rule_11_3_violation] */ + *ppxStaticStreamBuffer = ( StaticStreamBuffer_t * ) pxStreamBuffer; + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + traceRETURN_xStreamBufferGetStaticBuffers( xReturn ); + + return xReturn; + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) +{ + StreamBuffer_t * pxStreamBuffer = xStreamBuffer; + + traceENTER_vStreamBufferDelete( xStreamBuffer ); + + configASSERT( pxStreamBuffer ); + + traceSTREAM_BUFFER_DELETE( xStreamBuffer ); + + if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) pdFALSE ) + { + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + { + /* Both the structure and the buffer were allocated using a single call + * to pvPortMalloc(), hence only one call to vPortFree() is required. */ + vPortFree( ( void * ) pxStreamBuffer ); + } + #else + { + /* Should not be possible to get here, ucFlags must be corrupt. + * Force an assert. */ + configASSERT( xStreamBuffer == ( StreamBufferHandle_t ) ~0 ); + } + #endif + } + else + { + /* The structure and buffer were not allocated dynamically and cannot be + * freed - just scrub the structure so future use will assert. */ + ( void ) memset( pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) ); + } + + traceRETURN_vStreamBufferDelete(); +} +/*-----------------------------------------------------------*/ + +BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + BaseType_t xReturn = pdFAIL; + StreamBufferCallbackFunction_t pxSendCallback = NULL, pxReceiveCallback = NULL; + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxStreamBufferNumber; + #endif + + traceENTER_xStreamBufferReset( xStreamBuffer ); + + configASSERT( pxStreamBuffer ); + + #if ( configUSE_TRACE_FACILITY == 1 ) + { + /* Store the stream buffer number so it can be restored after the + * reset. */ + uxStreamBufferNumber = pxStreamBuffer->uxStreamBufferNumber; + } + #endif + + /* Can only reset a message buffer if there are no tasks blocked on it. */ + taskENTER_CRITICAL(); + { + if( ( pxStreamBuffer->xTaskWaitingToReceive == NULL ) && ( pxStreamBuffer->xTaskWaitingToSend == NULL ) ) + { + #if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) + { + pxSendCallback = pxStreamBuffer->pxSendCompletedCallback; + pxReceiveCallback = pxStreamBuffer->pxReceiveCompletedCallback; + } + #endif + + prvInitialiseNewStreamBuffer( pxStreamBuffer, + pxStreamBuffer->pucBuffer, + pxStreamBuffer->xLength, + pxStreamBuffer->xTriggerLevelBytes, + pxStreamBuffer->ucFlags, + pxSendCallback, + pxReceiveCallback ); + + #if ( configUSE_TRACE_FACILITY == 1 ) + { + pxStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber; + } + #endif + + traceSTREAM_BUFFER_RESET( xStreamBuffer ); + + xReturn = pdPASS; + } + } + taskEXIT_CRITICAL(); + + traceRETURN_xStreamBufferReset( xReturn ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xStreamBufferResetFromISR( StreamBufferHandle_t xStreamBuffer ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + BaseType_t xReturn = pdFAIL; + StreamBufferCallbackFunction_t pxSendCallback = NULL, pxReceiveCallback = NULL; + UBaseType_t uxSavedInterruptStatus; + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxStreamBufferNumber; + #endif + + traceENTER_xStreamBufferResetFromISR( xStreamBuffer ); + + configASSERT( pxStreamBuffer ); + + #if ( configUSE_TRACE_FACILITY == 1 ) + { + /* Store the stream buffer number so it can be restored after the + * reset. */ + uxStreamBufferNumber = pxStreamBuffer->uxStreamBufferNumber; + } + #endif + + /* Can only reset a message buffer if there are no tasks blocked on it. */ + /* MISRA Ref 4.7.1 [Return value shall be checked] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */ + /* coverity[misra_c_2012_directive_4_7_violation] */ + uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR(); + { + if( ( pxStreamBuffer->xTaskWaitingToReceive == NULL ) && ( pxStreamBuffer->xTaskWaitingToSend == NULL ) ) + { + #if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) + { + pxSendCallback = pxStreamBuffer->pxSendCompletedCallback; + pxReceiveCallback = pxStreamBuffer->pxReceiveCompletedCallback; + } + #endif + + prvInitialiseNewStreamBuffer( pxStreamBuffer, + pxStreamBuffer->pucBuffer, + pxStreamBuffer->xLength, + pxStreamBuffer->xTriggerLevelBytes, + pxStreamBuffer->ucFlags, + pxSendCallback, + pxReceiveCallback ); + + #if ( configUSE_TRACE_FACILITY == 1 ) + { + pxStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber; + } + #endif + + traceSTREAM_BUFFER_RESET_FROM_ISR( xStreamBuffer ); + + xReturn = pdPASS; + } + } + taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + + traceRETURN_xStreamBufferResetFromISR( xReturn ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + BaseType_t xReturn; + + traceENTER_xStreamBufferSetTriggerLevel( xStreamBuffer, xTriggerLevel ); + + configASSERT( pxStreamBuffer ); + + /* It is not valid for the trigger level to be 0. */ + if( xTriggerLevel == ( size_t ) 0 ) + { + xTriggerLevel = ( size_t ) 1; + } + + /* The trigger level is the number of bytes that must be in the stream + * buffer before a task that is waiting for data is unblocked. */ + if( xTriggerLevel < pxStreamBuffer->xLength ) + { + pxStreamBuffer->xTriggerLevelBytes = xTriggerLevel; + xReturn = pdPASS; + } + else + { + xReturn = pdFALSE; + } + + traceRETURN_xStreamBufferSetTriggerLevel( xReturn ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) +{ + const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + size_t xSpace; + size_t xOriginalTail; + + traceENTER_xStreamBufferSpacesAvailable( xStreamBuffer ); + + configASSERT( pxStreamBuffer ); + + /* The code below reads xTail and then xHead. This is safe if the stream + * buffer is updated once between the two reads - but not if the stream buffer + * is updated more than once between the two reads - hence the loop. */ + do + { + xOriginalTail = pxStreamBuffer->xTail; + xSpace = pxStreamBuffer->xLength + pxStreamBuffer->xTail; + xSpace -= pxStreamBuffer->xHead; + } while( xOriginalTail != pxStreamBuffer->xTail ); + + xSpace -= ( size_t ) 1; + + if( xSpace >= pxStreamBuffer->xLength ) + { + xSpace -= pxStreamBuffer->xLength; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceRETURN_xStreamBufferSpacesAvailable( xSpace ); + + return xSpace; +} +/*-----------------------------------------------------------*/ + +size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) +{ + const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + size_t xReturn; + + traceENTER_xStreamBufferBytesAvailable( xStreamBuffer ); + + configASSERT( pxStreamBuffer ); + + xReturn = prvBytesInBuffer( pxStreamBuffer ); + + traceRETURN_xStreamBufferBytesAvailable( xReturn ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + size_t xReturn, xSpace = 0; + size_t xRequiredSpace = xDataLengthBytes; + TimeOut_t xTimeOut; + size_t xMaxReportedSpace = 0; + + traceENTER_xStreamBufferSend( xStreamBuffer, pvTxData, xDataLengthBytes, xTicksToWait ); + + configASSERT( pvTxData ); + configASSERT( pxStreamBuffer ); + + /* The maximum amount of space a stream buffer will ever report is its length + * minus 1. */ + xMaxReportedSpace = pxStreamBuffer->xLength - ( size_t ) 1; + + /* This send function is used to write to both message buffers and stream + * buffers. If this is a message buffer then the space needed must be + * increased by the amount of bytes needed to store the length of the + * message. */ + if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) + { + xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH; + + /* Overflow? */ + configASSERT( xRequiredSpace > xDataLengthBytes ); + + /* If this is a message buffer then it must be possible to write the + * whole message. */ + if( xRequiredSpace > xMaxReportedSpace ) + { + /* The message would not fit even if the entire buffer was empty, + * so don't wait for space. */ + xTicksToWait = ( TickType_t ) 0; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* If this is a stream buffer then it is acceptable to write only part + * of the message to the buffer. Cap the length to the total length of + * the buffer. */ + if( xRequiredSpace > xMaxReportedSpace ) + { + xRequiredSpace = xMaxReportedSpace; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + if( xTicksToWait != ( TickType_t ) 0 ) + { + vTaskSetTimeOutState( &xTimeOut ); + + do + { + /* Wait until the required number of bytes are free in the message + * buffer. */ + taskENTER_CRITICAL(); + { + xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer ); + + if( xSpace < xRequiredSpace ) + { + /* Clear notification state as going to wait for space. */ + ( void ) xTaskNotifyStateClearIndexed( NULL, pxStreamBuffer->uxNotificationIndex ); + + /* Should only be one writer. */ + configASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL ); + pxStreamBuffer->xTaskWaitingToSend = xTaskGetCurrentTaskHandle(); + } + else + { + taskEXIT_CRITICAL(); + break; + } + } + taskEXIT_CRITICAL(); + + traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer ); + ( void ) xTaskNotifyWaitIndexed( pxStreamBuffer->uxNotificationIndex, ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait ); + pxStreamBuffer->xTaskWaitingToSend = NULL; + } while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xSpace == ( size_t ) 0 ) + { + xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace ); + + if( xReturn > ( size_t ) 0 ) + { + traceSTREAM_BUFFER_SEND( xStreamBuffer, xReturn ); + + /* Was a task waiting for the data? */ + if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes ) + { + prvSEND_COMPLETED( pxStreamBuffer ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer ); + } + + traceRETURN_xStreamBufferSend( xReturn ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + BaseType_t * const pxHigherPriorityTaskWoken ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + size_t xReturn, xSpace; + size_t xRequiredSpace = xDataLengthBytes; + + traceENTER_xStreamBufferSendFromISR( xStreamBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken ); + + configASSERT( pvTxData ); + configASSERT( pxStreamBuffer ); + + /* This send function is used to write to both message buffers and stream + * buffers. If this is a message buffer then the space needed must be + * increased by the amount of bytes needed to store the length of the + * message. */ + if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) + { + xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH; + + /* Overflow? */ + configASSERT( xRequiredSpace > xDataLengthBytes ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer ); + xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace ); + + if( xReturn > ( size_t ) 0 ) + { + /* Was a task waiting for the data? */ + if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes ) + { + /* MISRA Ref 4.7.1 [Return value shall be checked] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */ + /* coverity[misra_c_2012_directive_4_7_violation] */ + prvSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xReturn ); + traceRETURN_xStreamBufferSendFromISR( xReturn ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + size_t xSpace, + size_t xRequiredSpace ) +{ + size_t xNextHead = pxStreamBuffer->xHead; + configMESSAGE_BUFFER_LENGTH_TYPE xMessageLength; + + if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) + { + /* This is a message buffer, as opposed to a stream buffer. */ + + /* Convert xDataLengthBytes to the message length type. */ + xMessageLength = ( configMESSAGE_BUFFER_LENGTH_TYPE ) xDataLengthBytes; + + /* Ensure the data length given fits within configMESSAGE_BUFFER_LENGTH_TYPE. */ + configASSERT( ( size_t ) xMessageLength == xDataLengthBytes ); + + if( xSpace >= xRequiredSpace ) + { + /* There is enough space to write both the message length and the message + * itself into the buffer. Start by writing the length of the data, the data + * itself will be written later in this function. */ + xNextHead = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) &( xMessageLength ), sbBYTES_TO_STORE_MESSAGE_LENGTH, xNextHead ); + } + else + { + /* Not enough space, so do not write data to the buffer. */ + xDataLengthBytes = 0; + } + } + else + { + /* This is a stream buffer, as opposed to a message buffer, so writing a + * stream of bytes rather than discrete messages. Plan to write as many + * bytes as possible. */ + xDataLengthBytes = configMIN( xDataLengthBytes, xSpace ); + } + + if( xDataLengthBytes != ( size_t ) 0 ) + { + /* Write the data to the buffer. */ + /* MISRA Ref 11.5.5 [Void pointer assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + pxStreamBuffer->xHead = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) pvTxData, xDataLengthBytes, xNextHead ); + } + + return xDataLengthBytes; +} +/*-----------------------------------------------------------*/ + +size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength; + + traceENTER_xStreamBufferReceive( xStreamBuffer, pvRxData, xBufferLengthBytes, xTicksToWait ); + + configASSERT( pvRxData ); + configASSERT( pxStreamBuffer ); + + /* This receive function is used by both message buffers, which store + * discrete messages, and stream buffers, which store a continuous stream of + * bytes. Discrete messages include an additional + * sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the + * message. */ + if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) + { + xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH; + } + else if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_BATCHING_BUFFER ) != ( uint8_t ) 0 ) + { + /* Force task to block if the batching buffer contains less bytes than + * the trigger level. */ + xBytesToStoreMessageLength = pxStreamBuffer->xTriggerLevelBytes; + } + else + { + xBytesToStoreMessageLength = 0; + } + + if( xTicksToWait != ( TickType_t ) 0 ) + { + /* Checking if there is data and clearing the notification state must be + * performed atomically. */ + taskENTER_CRITICAL(); + { + xBytesAvailable = prvBytesInBuffer( pxStreamBuffer ); + + /* If this function was invoked by a message buffer read then + * xBytesToStoreMessageLength holds the number of bytes used to hold + * the length of the next discrete message. If this function was + * invoked by a stream buffer read then xBytesToStoreMessageLength will + * be 0. If this function was invoked by a stream batch buffer read + * then xBytesToStoreMessageLength will be xTriggerLevelBytes value + * for the buffer.*/ + if( xBytesAvailable <= xBytesToStoreMessageLength ) + { + /* Clear notification state as going to wait for data. */ + ( void ) xTaskNotifyStateClearIndexed( NULL, pxStreamBuffer->uxNotificationIndex ); + + /* Should only be one reader. */ + configASSERT( pxStreamBuffer->xTaskWaitingToReceive == NULL ); + pxStreamBuffer->xTaskWaitingToReceive = xTaskGetCurrentTaskHandle(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + + if( xBytesAvailable <= xBytesToStoreMessageLength ) + { + /* Wait for data to be available. */ + traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer ); + ( void ) xTaskNotifyWaitIndexed( pxStreamBuffer->uxNotificationIndex, ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait ); + pxStreamBuffer->xTaskWaitingToReceive = NULL; + + /* Recheck the data available after blocking. */ + xBytesAvailable = prvBytesInBuffer( pxStreamBuffer ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + xBytesAvailable = prvBytesInBuffer( pxStreamBuffer ); + } + + /* Whether receiving a discrete message (where xBytesToStoreMessageLength + * holds the number of bytes used to store the message length) or a stream of + * bytes (where xBytesToStoreMessageLength is zero), the number of bytes + * available must be greater than xBytesToStoreMessageLength to be able to + * read bytes from the buffer. */ + if( xBytesAvailable > xBytesToStoreMessageLength ) + { + xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable ); + + /* Was a task waiting for space in the buffer? */ + if( xReceivedLength != ( size_t ) 0 ) + { + traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength ); + prvRECEIVE_COMPLETED( xStreamBuffer ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer ); + mtCOVERAGE_TEST_MARKER(); + } + + traceRETURN_xStreamBufferReceive( xReceivedLength ); + + return xReceivedLength; +} +/*-----------------------------------------------------------*/ + +size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + size_t xReturn, xBytesAvailable; + configMESSAGE_BUFFER_LENGTH_TYPE xTempReturn; + + traceENTER_xStreamBufferNextMessageLengthBytes( xStreamBuffer ); + + configASSERT( pxStreamBuffer ); + + /* Ensure the stream buffer is being used as a message buffer. */ + if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) + { + xBytesAvailable = prvBytesInBuffer( pxStreamBuffer ); + + if( xBytesAvailable > sbBYTES_TO_STORE_MESSAGE_LENGTH ) + { + /* The number of bytes available is greater than the number of bytes + * required to hold the length of the next message, so another message + * is available. */ + ( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempReturn, sbBYTES_TO_STORE_MESSAGE_LENGTH, pxStreamBuffer->xTail ); + xReturn = ( size_t ) xTempReturn; + } + else + { + /* The minimum amount of bytes in a message buffer is + * ( sbBYTES_TO_STORE_MESSAGE_LENGTH + 1 ), so if xBytesAvailable is + * less than sbBYTES_TO_STORE_MESSAGE_LENGTH the only other valid + * value is 0. */ + configASSERT( xBytesAvailable == 0 ); + xReturn = 0; + } + } + else + { + xReturn = 0; + } + + traceRETURN_xStreamBufferNextMessageLengthBytes( xReturn ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + BaseType_t * const pxHigherPriorityTaskWoken ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength; + + traceENTER_xStreamBufferReceiveFromISR( xStreamBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken ); + + configASSERT( pvRxData ); + configASSERT( pxStreamBuffer ); + + /* This receive function is used by both message buffers, which store + * discrete messages, and stream buffers, which store a continuous stream of + * bytes. Discrete messages include an additional + * sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the + * message. */ + if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) + { + xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH; + } + else + { + xBytesToStoreMessageLength = 0; + } + + xBytesAvailable = prvBytesInBuffer( pxStreamBuffer ); + + /* Whether receiving a discrete message (where xBytesToStoreMessageLength + * holds the number of bytes used to store the message length) or a stream of + * bytes (where xBytesToStoreMessageLength is zero), the number of bytes + * available must be greater than xBytesToStoreMessageLength to be able to + * read bytes from the buffer. */ + if( xBytesAvailable > xBytesToStoreMessageLength ) + { + xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable ); + + /* Was a task waiting for space in the buffer? */ + if( xReceivedLength != ( size_t ) 0 ) + { + /* MISRA Ref 4.7.1 [Return value shall be checked] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */ + /* coverity[misra_c_2012_directive_4_7_violation] */ + prvRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength ); + traceRETURN_xStreamBufferReceiveFromISR( xReceivedLength ); + + return xReceivedLength; +} +/*-----------------------------------------------------------*/ + +static size_t prvReadMessageFromBuffer( StreamBuffer_t * pxStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + size_t xBytesAvailable ) +{ + size_t xCount, xNextMessageLength; + configMESSAGE_BUFFER_LENGTH_TYPE xTempNextMessageLength; + size_t xNextTail = pxStreamBuffer->xTail; + + if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) + { + /* A discrete message is being received. First receive the length + * of the message. */ + xNextTail = prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempNextMessageLength, sbBYTES_TO_STORE_MESSAGE_LENGTH, xNextTail ); + xNextMessageLength = ( size_t ) xTempNextMessageLength; + + /* Reduce the number of bytes available by the number of bytes just + * read out. */ + xBytesAvailable -= sbBYTES_TO_STORE_MESSAGE_LENGTH; + + /* Check there is enough space in the buffer provided by the + * user. */ + if( xNextMessageLength > xBufferLengthBytes ) + { + /* The user has provided insufficient space to read the message. */ + xNextMessageLength = 0; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* A stream of bytes is being received (as opposed to a discrete + * message), so read as many bytes as possible. */ + xNextMessageLength = xBufferLengthBytes; + } + + /* Use the minimum of the wanted bytes and the available bytes. */ + xCount = configMIN( xNextMessageLength, xBytesAvailable ); + + if( xCount != ( size_t ) 0 ) + { + /* Read the actual data and update the tail to mark the data as officially consumed. */ + /* MISRA Ref 11.5.5 [Void pointer assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + pxStreamBuffer->xTail = prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) pvRxData, xCount, xNextTail ); + } + + return xCount; +} +/*-----------------------------------------------------------*/ + +BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) +{ + const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + BaseType_t xReturn; + size_t xTail; + + traceENTER_xStreamBufferIsEmpty( xStreamBuffer ); + + configASSERT( pxStreamBuffer ); + + /* True if no bytes are available. */ + xTail = pxStreamBuffer->xTail; + + if( pxStreamBuffer->xHead == xTail ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + traceRETURN_xStreamBufferIsEmpty( xReturn ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) +{ + BaseType_t xReturn; + size_t xBytesToStoreMessageLength; + const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + + traceENTER_xStreamBufferIsFull( xStreamBuffer ); + + configASSERT( pxStreamBuffer ); + + /* This generic version of the receive function is used by both message + * buffers, which store discrete messages, and stream buffers, which store a + * continuous stream of bytes. Discrete messages include an additional + * sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the message. */ + if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) + { + xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH; + } + else + { + xBytesToStoreMessageLength = 0; + } + + /* True if the available space equals zero. */ + if( xStreamBufferSpacesAvailable( xStreamBuffer ) <= xBytesToStoreMessageLength ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + traceRETURN_xStreamBufferIsFull( xReturn ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, + BaseType_t * pxHigherPriorityTaskWoken ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + BaseType_t xReturn; + UBaseType_t uxSavedInterruptStatus; + + traceENTER_xStreamBufferSendCompletedFromISR( xStreamBuffer, pxHigherPriorityTaskWoken ); + + configASSERT( pxStreamBuffer ); + + /* MISRA Ref 4.7.1 [Return value shall be checked] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */ + /* coverity[misra_c_2012_directive_4_7_violation] */ + uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR(); + { + if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL ) + { + ( void ) xTaskNotifyIndexedFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive, + ( pxStreamBuffer )->uxNotificationIndex, + ( uint32_t ) 0, + eNoAction, + pxHigherPriorityTaskWoken ); + ( pxStreamBuffer )->xTaskWaitingToReceive = NULL; + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + } + taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + + traceRETURN_xStreamBufferSendCompletedFromISR( xReturn ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, + BaseType_t * pxHigherPriorityTaskWoken ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + BaseType_t xReturn; + UBaseType_t uxSavedInterruptStatus; + + traceENTER_xStreamBufferReceiveCompletedFromISR( xStreamBuffer, pxHigherPriorityTaskWoken ); + + configASSERT( pxStreamBuffer ); + + /* MISRA Ref 4.7.1 [Return value shall be checked] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */ + /* coverity[misra_c_2012_directive_4_7_violation] */ + uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR(); + { + if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL ) + { + ( void ) xTaskNotifyIndexedFromISR( ( pxStreamBuffer )->xTaskWaitingToSend, + ( pxStreamBuffer )->uxNotificationIndex, + ( uint32_t ) 0, + eNoAction, + pxHigherPriorityTaskWoken ); + ( pxStreamBuffer )->xTaskWaitingToSend = NULL; + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + } + taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + + traceRETURN_xStreamBufferReceiveCompletedFromISR( xReturn ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, + const uint8_t * pucData, + size_t xCount, + size_t xHead ) +{ + size_t xFirstLength; + + configASSERT( xCount > ( size_t ) 0 ); + + /* Calculate the number of bytes that can be added in the first write - + * which may be less than the total number of bytes that need to be added if + * the buffer will wrap back to the beginning. */ + xFirstLength = configMIN( pxStreamBuffer->xLength - xHead, xCount ); + + /* Write as many bytes as can be written in the first write. */ + configASSERT( ( xHead + xFirstLength ) <= pxStreamBuffer->xLength ); + ( void ) memcpy( ( void * ) ( &( pxStreamBuffer->pucBuffer[ xHead ] ) ), ( const void * ) pucData, xFirstLength ); + + /* If the number of bytes written was less than the number that could be + * written in the first write... */ + if( xCount > xFirstLength ) + { + /* ...then write the remaining bytes to the start of the buffer. */ + configASSERT( ( xCount - xFirstLength ) <= pxStreamBuffer->xLength ); + ( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xHead += xCount; + + if( xHead >= pxStreamBuffer->xLength ) + { + xHead -= pxStreamBuffer->xLength; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xHead; +} +/*-----------------------------------------------------------*/ + +static size_t prvReadBytesFromBuffer( StreamBuffer_t * pxStreamBuffer, + uint8_t * pucData, + size_t xCount, + size_t xTail ) +{ + size_t xFirstLength; + + configASSERT( xCount != ( size_t ) 0 ); + + /* Calculate the number of bytes that can be read - which may be + * less than the number wanted if the data wraps around to the start of + * the buffer. */ + xFirstLength = configMIN( pxStreamBuffer->xLength - xTail, xCount ); + + /* Obtain the number of bytes it is possible to obtain in the first + * read. Asserts check bounds of read and write. */ + configASSERT( xFirstLength <= xCount ); + configASSERT( ( xTail + xFirstLength ) <= pxStreamBuffer->xLength ); + ( void ) memcpy( ( void * ) pucData, ( const void * ) &( pxStreamBuffer->pucBuffer[ xTail ] ), xFirstLength ); + + /* If the total number of wanted bytes is greater than the number + * that could be read in the first read... */ + if( xCount > xFirstLength ) + { + /* ...then read the remaining bytes from the start of the buffer. */ + ( void ) memcpy( ( void * ) &( pucData[ xFirstLength ] ), ( void * ) ( pxStreamBuffer->pucBuffer ), xCount - xFirstLength ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Move the tail pointer to effectively remove the data read from the buffer. */ + xTail += xCount; + + if( xTail >= pxStreamBuffer->xLength ) + { + xTail -= pxStreamBuffer->xLength; + } + + return xTail; +} +/*-----------------------------------------------------------*/ + +static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer ) +{ + /* Returns the distance between xTail and xHead. */ + size_t xCount; + + xCount = pxStreamBuffer->xLength + pxStreamBuffer->xHead; + xCount -= pxStreamBuffer->xTail; + + if( xCount >= pxStreamBuffer->xLength ) + { + xCount -= pxStreamBuffer->xLength; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xCount; +} +/*-----------------------------------------------------------*/ + +static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer, + uint8_t * const pucBuffer, + size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + uint8_t ucFlags, + StreamBufferCallbackFunction_t pxSendCompletedCallback, + StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) +{ + /* Assert here is deliberately writing to the entire buffer to ensure it can + * be written to without generating exceptions, and is setting the buffer to a + * known value to assist in development/debugging. */ + #if ( configASSERT_DEFINED == 1 ) + { + /* The value written just has to be identifiable when looking at the + * memory. Don't use 0xA5 as that is the stack fill value and could + * result in confusion as to what is actually being observed. */ + #define STREAM_BUFFER_BUFFER_WRITE_VALUE ( 0x55 ) + configASSERT( memset( pucBuffer, ( int ) STREAM_BUFFER_BUFFER_WRITE_VALUE, xBufferSizeBytes ) == pucBuffer ); + } + #endif + + ( void ) memset( ( void * ) pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) ); + pxStreamBuffer->pucBuffer = pucBuffer; + pxStreamBuffer->xLength = xBufferSizeBytes; + pxStreamBuffer->xTriggerLevelBytes = xTriggerLevelBytes; + pxStreamBuffer->ucFlags = ucFlags; + pxStreamBuffer->uxNotificationIndex = tskDEFAULT_INDEX_TO_NOTIFY; + #if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) + { + pxStreamBuffer->pxSendCompletedCallback = pxSendCompletedCallback; + pxStreamBuffer->pxReceiveCompletedCallback = pxReceiveCompletedCallback; + } + #else + { + /* MISRA Ref 11.1.1 [Object type casting] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-111 */ + /* coverity[misra_c_2012_rule_11_1_violation] */ + ( void ) pxSendCompletedCallback; + + /* MISRA Ref 11.1.1 [Object type casting] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-111 */ + /* coverity[misra_c_2012_rule_11_1_violation] */ + ( void ) pxReceiveCompletedCallback; + } + #endif /* if ( configUSE_SB_COMPLETED_CALLBACK == 1 ) */ +} +/*-----------------------------------------------------------*/ + +UBaseType_t uxStreamBufferGetStreamBufferNotificationIndex( StreamBufferHandle_t xStreamBuffer ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + + traceENTER_uxStreamBufferGetStreamBufferNotificationIndex( xStreamBuffer ); + + configASSERT( pxStreamBuffer ); + + traceRETURN_uxStreamBufferGetStreamBufferNotificationIndex( pxStreamBuffer->uxNotificationIndex ); + + return pxStreamBuffer->uxNotificationIndex; +} +/*-----------------------------------------------------------*/ + +void vStreamBufferSetStreamBufferNotificationIndex( StreamBufferHandle_t xStreamBuffer, + UBaseType_t uxNotificationIndex ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + + traceENTER_vStreamBufferSetStreamBufferNotificationIndex( xStreamBuffer, uxNotificationIndex ); + + /* There should be no task waiting otherwise we'd never resume them. */ + configASSERT( ( pxStreamBuffer != NULL ) && ( pxStreamBuffer->xTaskWaitingToReceive == NULL ) ); + configASSERT( ( pxStreamBuffer != NULL ) && ( pxStreamBuffer->xTaskWaitingToSend == NULL ) ); + + /* Check that the task notification index is valid. */ + configASSERT( uxNotificationIndex < configTASK_NOTIFICATION_ARRAY_ENTRIES ); + + pxStreamBuffer->uxNotificationIndex = uxNotificationIndex; + + traceRETURN_vStreamBufferSetStreamBufferNotificationIndex(); +} +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer ) + { + traceENTER_uxStreamBufferGetStreamBufferNumber( xStreamBuffer ); + + traceRETURN_uxStreamBufferGetStreamBufferNumber( xStreamBuffer->uxStreamBufferNumber ); + + return xStreamBuffer->uxStreamBufferNumber; + } + + #endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, + UBaseType_t uxStreamBufferNumber ) + { + traceENTER_vStreamBufferSetStreamBufferNumber( xStreamBuffer, uxStreamBufferNumber ); + + xStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber; + + traceRETURN_vStreamBufferSetStreamBufferNumber(); + } + + #endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer ) + { + traceENTER_ucStreamBufferGetStreamBufferType( xStreamBuffer ); + + traceRETURN_ucStreamBufferGetStreamBufferType( ( uint8_t ) ( xStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) ); + + return( ( uint8_t ) ( xStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) ); + } + + #endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +/* This entire source file will be skipped if the application is not configured + * to include stream buffer functionality. This #if is closed at the very bottom + * of this file. If you want to include stream buffers then ensure + * configUSE_STREAM_BUFFERS is set to 1 in FreeRTOSConfig.h. */ +#endif /* configUSE_STREAM_BUFFERS == 1 */ diff --git a/tasks.c b/tasks.c new file mode 100644 index 000000000..c596c475f --- /dev/null +++ b/tasks.c @@ -0,0 +1,8872 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2026 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "stack_macros.h" + +/* The default definitions are only available for non-MPU ports. The + * reason is that the stack alignment requirements vary for different + * architectures.*/ +#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configKERNEL_PROVIDED_STATIC_MEMORY == 1 ) && ( portUSING_MPU_WRAPPERS != 0 ) ) + #error configKERNEL_PROVIDED_STATIC_MEMORY cannot be set to 1 when using an MPU port. The vApplicationGet*TaskMemory() functions must be provided manually. +#endif + +/* The MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined + * for the header files above, but not in this file, in order to generate the + * correct privileged Vs unprivileged linkage and placement. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Set configUSE_STATS_FORMATTING_FUNCTIONS to 2 to include the stats formatting + * functions but without including stdio.h here. */ +#if ( configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) + +/* At the bottom of this file are two optional functions that can be used + * to generate human readable text from the raw data generated by the + * uxTaskGetSystemState() function. Note the formatting functions are provided + * for convenience only, and are NOT considered part of the kernel. */ + #include +#endif /* configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) */ + +#if ( configUSE_PREEMPTION == 0 ) + +/* If the cooperative scheduler is being used then a yield should not be + * performed just because a higher priority task has been woken. */ + #define taskYIELD_TASK_CORE_IF_USING_PREEMPTION( pxTCB ) + #define taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxTCB ) +#else + + #if ( configNUMBER_OF_CORES == 1 ) + +/* This macro requests the running task pxTCB to yield. In single core + * scheduler, a running task always runs on core 0 and portYIELD_WITHIN_API() + * can be used to request the task running on core 0 to yield. Therefore, pxTCB + * is not used in this macro. */ + #define taskYIELD_TASK_CORE_IF_USING_PREEMPTION( pxTCB ) \ + do { \ + ( void ) ( pxTCB ); \ + portYIELD_WITHIN_API(); \ + } while( 0 ) + + #define taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxTCB ) \ + do { \ + if( pxCurrentTCB->uxPriority < ( pxTCB )->uxPriority ) \ + { \ + portYIELD_WITHIN_API(); \ + } \ + else \ + { \ + mtCOVERAGE_TEST_MARKER(); \ + } \ + } while( 0 ) + + #else /* if ( configNUMBER_OF_CORES == 1 ) */ + +/* Yield the core on which this task is running. */ + #define taskYIELD_TASK_CORE_IF_USING_PREEMPTION( pxTCB ) prvYieldCore( ( pxTCB )->xTaskRunState ) + +/* Yield for the task if a running task has priority lower than this task. */ + #define taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxTCB ) prvYieldForTask( pxTCB ) + + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ + +#endif /* if ( configUSE_PREEMPTION == 0 ) */ + +/* Values that can be assigned to the ucNotifyState member of the TCB. */ +#define taskNOT_WAITING_NOTIFICATION ( ( uint8_t ) 0 ) /* Must be zero as it is the initialised value. */ +#define taskWAITING_NOTIFICATION ( ( uint8_t ) 1 ) +#define taskNOTIFICATION_RECEIVED ( ( uint8_t ) 2 ) + +/* + * The value used to fill the stack of a task when the task is created. This + * is used purely for checking the high water mark for tasks. + */ +#define tskSTACK_FILL_BYTE ( 0xa5U ) + +/* Bits used to record how a task's stack and TCB were allocated. */ +#define tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB ( ( uint8_t ) 0 ) +#define tskSTATICALLY_ALLOCATED_STACK_ONLY ( ( uint8_t ) 1 ) +#define tskSTATICALLY_ALLOCATED_STACK_AND_TCB ( ( uint8_t ) 2 ) + +/* If any of the following are set then task stacks are filled with a known + * value so the high water mark can be determined. If none of the following are + * set then don't fill the stack so there is no unnecessary dependency on memset. */ +#if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) ) + #define tskSET_NEW_STACKS_TO_KNOWN_VALUE 1 +#else + #define tskSET_NEW_STACKS_TO_KNOWN_VALUE 0 +#endif + +/* + * Macros used by vListTask to indicate which state a task is in. + */ +#define tskRUNNING_CHAR ( 'X' ) +#define tskBLOCKED_CHAR ( 'B' ) +#define tskREADY_CHAR ( 'R' ) +#define tskDELETED_CHAR ( 'D' ) +#define tskSUSPENDED_CHAR ( 'S' ) + +/* + * Some kernel aware debuggers require the data the debugger needs access to be + * global, rather than file scope. + */ +#ifdef portREMOVE_STATIC_QUALIFIER + #define static +#endif + +/* The name allocated to the Idle task. This can be overridden by defining + * configIDLE_TASK_NAME in FreeRTOSConfig.h. */ +#ifndef configIDLE_TASK_NAME + #define configIDLE_TASK_NAME "IDLE" +#endif + +/* Reserve space for Core ID and null termination. */ +#if ( configNUMBER_OF_CORES > 1 ) + /* Multi-core systems with up to 9 cores require 1 character for core ID and 1 for null termination. */ + #if ( configMAX_TASK_NAME_LEN < 2U ) + #error Minimum required task name length is 2. Please increase configMAX_TASK_NAME_LEN. + #endif + #define taskRESERVED_TASK_NAME_LENGTH 2U + +#else /* if ( configNUMBER_OF_CORES > 1 ) */ + /* Reserve space for null termination. */ + #if ( configMAX_TASK_NAME_LEN < 1U ) + #error Minimum required task name length is 1. Please increase configMAX_TASK_NAME_LEN. + #endif + #define taskRESERVED_TASK_NAME_LENGTH 1U +#endif /* if ( ( configNUMBER_OF_CORES > 1 ) */ + +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 ) + +/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 0 then task selection is + * performed in a generic way that is not optimised to any particular + * microcontroller architecture. */ + +/* uxTopReadyPriority holds the priority of the highest priority ready + * state task. */ + #define taskRECORD_READY_PRIORITY( uxPriority ) \ + do { \ + if( ( uxPriority ) > uxTopReadyPriority ) \ + { \ + uxTopReadyPriority = ( uxPriority ); \ + } \ + } while( 0 ) /* taskRECORD_READY_PRIORITY */ + +/*-----------------------------------------------------------*/ + + #if ( configNUMBER_OF_CORES == 1 ) + #define taskSELECT_HIGHEST_PRIORITY_TASK() \ + do { \ + UBaseType_t uxTopPriority = uxTopReadyPriority; \ + \ + /* Find the highest priority queue that contains ready tasks. */ \ + while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopPriority ] ) ) != pdFALSE ) \ + { \ + configASSERT( uxTopPriority ); \ + --uxTopPriority; \ + } \ + \ + /* listGET_OWNER_OF_NEXT_ENTRY indexes through the list, so the tasks of \ + * the same priority get an equal share of the processor time. */ \ + listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) ); \ + uxTopReadyPriority = uxTopPriority; \ + } while( 0 ) /* taskSELECT_HIGHEST_PRIORITY_TASK */ + #else /* if ( configNUMBER_OF_CORES == 1 ) */ + + #define taskSELECT_HIGHEST_PRIORITY_TASK( xCoreID ) prvSelectHighestPriorityTask( xCoreID ) + + #endif /* if ( configNUMBER_OF_CORES == 1 ) */ + +/*-----------------------------------------------------------*/ + +/* Define away taskRESET_READY_PRIORITY() and portRESET_READY_PRIORITY() as + * they are only required when a port optimised method of task selection is + * being used. */ + #define taskRESET_READY_PRIORITY( uxPriority ) + #define portRESET_READY_PRIORITY( uxPriority, uxTopReadyPriority ) + +#else /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 1 then task selection is + * performed in a way that is tailored to the particular microcontroller + * architecture being used. */ + +/* A port optimised version is provided. Call the port defined macros. */ + #define taskRECORD_READY_PRIORITY( uxPriority ) portRECORD_READY_PRIORITY( ( uxPriority ), uxTopReadyPriority ) + +/*-----------------------------------------------------------*/ + + #define taskSELECT_HIGHEST_PRIORITY_TASK() \ + do { \ + UBaseType_t uxTopPriority; \ + \ + /* Find the highest priority list that contains ready tasks. */ \ + portGET_HIGHEST_PRIORITY( uxTopPriority, uxTopReadyPriority ); \ + configASSERT( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ uxTopPriority ] ) ) > 0 ); \ + listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) ); \ + } while( 0 ) + +/*-----------------------------------------------------------*/ + +/* A port optimised version is provided, call it only if the TCB being reset + * is being referenced from a ready list. If it is referenced from a delayed + * or suspended list then it won't be in a ready list. */ + #define taskRESET_READY_PRIORITY( uxPriority ) \ + do { \ + if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ ( uxPriority ) ] ) ) == ( UBaseType_t ) 0 ) \ + { \ + portRESET_READY_PRIORITY( ( uxPriority ), ( uxTopReadyPriority ) ); \ + } \ + } while( 0 ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/*-----------------------------------------------------------*/ + +/* pxDelayedTaskList and pxOverflowDelayedTaskList are switched when the tick + * count overflows. */ +#define taskSWITCH_DELAYED_LISTS() \ + do { \ + List_t * pxTemp; \ + \ + /* The delayed tasks list should be empty when the lists are switched. */ \ + configASSERT( ( listLIST_IS_EMPTY( pxDelayedTaskList ) ) ); \ + \ + pxTemp = pxDelayedTaskList; \ + pxDelayedTaskList = pxOverflowDelayedTaskList; \ + pxOverflowDelayedTaskList = pxTemp; \ + xNumOfOverflows = ( BaseType_t ) ( xNumOfOverflows + 1 ); \ + prvResetNextTaskUnblockTime(); \ + } while( 0 ) + +/*-----------------------------------------------------------*/ + +/* + * Place the task represented by pxTCB into the appropriate ready list for + * the task. It is inserted at the end of the list. + */ +#define prvAddTaskToReadyList( pxTCB ) \ + do { \ + traceMOVED_TASK_TO_READY_STATE( pxTCB ); \ + taskRECORD_READY_PRIORITY( ( pxTCB )->uxPriority ); \ + listINSERT_END( &( pxReadyTasksLists[ ( pxTCB )->uxPriority ] ), &( ( pxTCB )->xStateListItem ) ); \ + tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB ); \ + } while( 0 ) +/*-----------------------------------------------------------*/ + +/* + * Several functions take a TaskHandle_t parameter that can optionally be NULL, + * where NULL is used to indicate that the handle of the currently executing + * task should be used in place of the parameter. This macro simply checks to + * see if the parameter is NULL and returns a pointer to the appropriate TCB. + */ +#define prvGetTCBFromHandle( pxHandle ) ( ( ( pxHandle ) == NULL ) ? pxCurrentTCB : ( pxHandle ) ) + +/* The item value of the event list item is normally used to hold the priority + * of the task to which it belongs (coded to allow it to be held in reverse + * priority order). However, it is occasionally borrowed for other purposes. It + * is important its value is not updated due to a task priority change while it is + * being used for another purpose. The following bit definition is used to inform + * the scheduler that the value should not be changed - in which case it is the + * responsibility of whichever module is using the value to ensure it gets set back + * to its original value when it is released. */ +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + #define taskEVENT_LIST_ITEM_VALUE_IN_USE ( ( uint16_t ) 0x8000U ) +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + #define taskEVENT_LIST_ITEM_VALUE_IN_USE ( ( uint32_t ) 0x80000000U ) +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_64_BITS ) + #define taskEVENT_LIST_ITEM_VALUE_IN_USE ( ( uint64_t ) 0x8000000000000000U ) +#endif + +/* Indicates that the task is not actively running on any core. */ +#define taskTASK_NOT_RUNNING ( ( BaseType_t ) ( -1 ) ) + +/* Indicates that the task is actively running but scheduled to yield. */ +#define taskTASK_SCHEDULED_TO_YIELD ( ( BaseType_t ) ( -2 ) ) + +/* Returns pdTRUE if the task is actively running and not scheduled to yield. */ +#if ( configNUMBER_OF_CORES == 1 ) + #define taskTASK_IS_RUNNING( pxTCB ) ( ( ( pxTCB ) == pxCurrentTCB ) ? ( pdTRUE ) : ( pdFALSE ) ) + #define taskTASK_IS_RUNNING_OR_SCHEDULED_TO_YIELD( pxTCB ) ( ( ( pxTCB ) == pxCurrentTCB ) ? ( pdTRUE ) : ( pdFALSE ) ) +#else + #define taskTASK_IS_RUNNING( pxTCB ) ( ( ( ( pxTCB )->xTaskRunState >= ( BaseType_t ) 0 ) && ( ( pxTCB )->xTaskRunState < ( BaseType_t ) configNUMBER_OF_CORES ) ) ? ( pdTRUE ) : ( pdFALSE ) ) + #define taskTASK_IS_RUNNING_OR_SCHEDULED_TO_YIELD( pxTCB ) ( ( ( pxTCB )->xTaskRunState != taskTASK_NOT_RUNNING ) ? ( pdTRUE ) : ( pdFALSE ) ) +#endif + +/* Indicates that the task is an Idle task. */ +#define taskATTRIBUTE_IS_IDLE ( UBaseType_t ) ( 1U << 0U ) + +#if ( ( configNUMBER_OF_CORES > 1 ) && ( portCRITICAL_NESTING_IN_TCB == 1 ) ) + #define portGET_CRITICAL_NESTING_COUNT( xCoreID ) ( pxCurrentTCBs[ ( xCoreID ) ]->uxCriticalNesting ) + #define portSET_CRITICAL_NESTING_COUNT( xCoreID, x ) ( pxCurrentTCBs[ ( xCoreID ) ]->uxCriticalNesting = ( x ) ) + #define portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( pxCurrentTCBs[ ( xCoreID ) ]->uxCriticalNesting++ ) + #define portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( pxCurrentTCBs[ ( xCoreID ) ]->uxCriticalNesting-- ) +#endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( portCRITICAL_NESTING_IN_TCB == 1 ) ) */ + +#define taskBITS_PER_BYTE ( ( size_t ) 8 ) + +#if ( configNUMBER_OF_CORES > 1 ) + +/* Yields the given core. This must be called from a critical section and xCoreID + * must be valid. This macro is not required in single core since there is only + * one core to yield. */ + #define prvYieldCore( xCoreID ) \ + do { \ + if( ( xCoreID ) == ( BaseType_t ) portGET_CORE_ID() ) \ + { \ + /* Pending a yield for this core since it is in the critical section. */ \ + xYieldPendings[ ( xCoreID ) ] = pdTRUE; \ + } \ + else \ + { \ + /* Request other core to yield if it is not requested before. */ \ + if( pxCurrentTCBs[ ( xCoreID ) ]->xTaskRunState != taskTASK_SCHEDULED_TO_YIELD ) \ + { \ + portYIELD_CORE( xCoreID ); \ + pxCurrentTCBs[ ( xCoreID ) ]->xTaskRunState = taskTASK_SCHEDULED_TO_YIELD; \ + } \ + } \ + } while( 0 ) +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ +/*-----------------------------------------------------------*/ + +/* + * Task control block. A task control block (TCB) is allocated for each task, + * and stores task state information, including a pointer to the task's context + * (the task's run time environment, including register values) + */ +typedef struct tskTaskControlBlock /* The old naming convention is used to prevent breaking kernel aware debuggers. */ +{ + volatile StackType_t * pxTopOfStack; /**< Points to the location of the last item placed on the tasks stack. THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */ + + #if ( portUSING_MPU_WRAPPERS == 1 ) + xMPU_SETTINGS xMPUSettings; /**< The MPU settings are defined as part of the port layer. THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */ + #endif + + #if ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) + UBaseType_t uxCoreAffinityMask; /**< Used to link the task to certain cores. UBaseType_t must have greater than or equal to the number of bits as configNUMBER_OF_CORES. */ + #endif + + ListItem_t xStateListItem; /**< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */ + ListItem_t xEventListItem; /**< Used to reference a task from an event list. */ + UBaseType_t uxPriority; /**< The priority of the task. 0 is the lowest priority. */ + StackType_t * pxStack; /**< Points to the start of the stack. */ + #if ( configNUMBER_OF_CORES > 1 ) + volatile BaseType_t xTaskRunState; /**< Used to identify the core the task is running on, if the task is running. Otherwise, identifies the task's state - not running or yielding. */ + UBaseType_t uxTaskAttributes; /**< Task's attributes - currently used to identify the idle tasks. */ + #endif + char pcTaskName[ configMAX_TASK_NAME_LEN ]; /**< Descriptive name given to the task when created. Facilitates debugging only. */ + + #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 ) + BaseType_t xPreemptionDisable; /**< Used to prevent the task from being preempted. */ + #endif + + #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) ) + StackType_t * pxEndOfStack; /**< Points to the highest valid address for the stack. */ + #endif + + #if ( portCRITICAL_NESTING_IN_TCB == 1 ) + UBaseType_t uxCriticalNesting; /**< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */ + #endif + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxTCBNumber; /**< Stores a number that increments each time a TCB is created. It allows debuggers to determine when a task has been deleted and then recreated. */ + UBaseType_t uxTaskNumber; /**< Stores a number specifically for use by third party trace code. */ + #endif + + #if ( configUSE_MUTEXES == 1 ) + UBaseType_t uxBasePriority; /**< The priority last assigned to the task - used by the priority inheritance mechanism. */ + UBaseType_t uxMutexesHeld; + #endif + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + TaskHookFunction_t pxTaskTag; + #endif + + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 ) + void * pvThreadLocalStoragePointers[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ]; + #endif + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + configRUN_TIME_COUNTER_TYPE ulRunTimeCounter; /**< Stores the amount of time the task has spent in the Running state. */ + #endif + + #if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) + configTLS_BLOCK_TYPE xTLSBlock; /**< Memory block used as Thread Local Storage (TLS) Block for the task. */ + #endif + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + volatile uint32_t ulNotifiedValue[ configTASK_NOTIFICATION_ARRAY_ENTRIES ]; + volatile uint8_t ucNotifyState[ configTASK_NOTIFICATION_ARRAY_ENTRIES ]; + #endif + + /* See the comments in FreeRTOS.h with the definition of + * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE. */ + #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) + uint8_t ucStaticallyAllocated; /**< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */ + #endif + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + uint8_t ucDelayAborted; + #endif + + #if ( configUSE_POSIX_ERRNO == 1 ) + int iTaskErrno; + #endif +} tskTCB; + +/* The old tskTCB name is maintained above then typedefed to the new TCB_t name + * below to enable the use of older kernel aware debuggers. */ +typedef tskTCB TCB_t; + +#if ( configNUMBER_OF_CORES == 1 ) + /* MISRA Ref 8.4.1 [Declaration shall be visible] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-84 */ + /* coverity[misra_c_2012_rule_8_4_violation] */ + portDONT_DISCARD PRIVILEGED_DATA TCB_t * volatile pxCurrentTCB = NULL; +#else + /* MISRA Ref 8.4.1 [Declaration shall be visible] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-84 */ + /* coverity[misra_c_2012_rule_8_4_violation] */ + portDONT_DISCARD PRIVILEGED_DATA TCB_t * volatile pxCurrentTCBs[ configNUMBER_OF_CORES ]; + #define pxCurrentTCB xTaskGetCurrentTaskHandle() +#endif + +/* Lists for ready and blocked tasks. -------------------- + * xDelayedTaskList1 and xDelayedTaskList2 could be moved to function scope but + * doing so breaks some kernel aware debuggers and debuggers that rely on removing + * the static qualifier. */ +PRIVILEGED_DATA static List_t pxReadyTasksLists[ configMAX_PRIORITIES ]; /**< Prioritised ready tasks. */ +PRIVILEGED_DATA static List_t xDelayedTaskList1; /**< Delayed tasks. */ +PRIVILEGED_DATA static List_t xDelayedTaskList2; /**< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */ +PRIVILEGED_DATA static List_t * volatile pxDelayedTaskList; /**< Points to the delayed task list currently being used. */ +PRIVILEGED_DATA static List_t * volatile pxOverflowDelayedTaskList; /**< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */ +PRIVILEGED_DATA static List_t xPendingReadyList; /**< Tasks that have been readied while the scheduler was suspended. They will be moved to the ready list when the scheduler is resumed. */ + +#if ( INCLUDE_vTaskDelete == 1 ) + + PRIVILEGED_DATA static List_t xTasksWaitingTermination; /**< Tasks that have been deleted - but their memory not yet freed. */ + PRIVILEGED_DATA static volatile UBaseType_t uxDeletedTasksWaitingCleanUp = ( UBaseType_t ) 0U; + +#endif + +#if ( INCLUDE_vTaskSuspend == 1 ) + + PRIVILEGED_DATA static List_t xSuspendedTaskList; /**< Tasks that are currently suspended. */ + +#endif + +/* Global POSIX errno. Its value is changed upon context switching to match + * the errno of the currently running task. */ +#if ( configUSE_POSIX_ERRNO == 1 ) + int FreeRTOS_errno = 0; +#endif + +/* Other file private variables. --------------------------------*/ +PRIVILEGED_DATA static volatile UBaseType_t uxCurrentNumberOfTasks = ( UBaseType_t ) 0U; +PRIVILEGED_DATA static volatile TickType_t xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT; +PRIVILEGED_DATA static volatile UBaseType_t uxTopReadyPriority = tskIDLE_PRIORITY; +PRIVILEGED_DATA static volatile BaseType_t xSchedulerRunning = pdFALSE; +PRIVILEGED_DATA static volatile TickType_t xPendedTicks = ( TickType_t ) 0U; +PRIVILEGED_DATA static volatile BaseType_t xYieldPendings[ configNUMBER_OF_CORES ] = { pdFALSE }; +PRIVILEGED_DATA static volatile BaseType_t xNumOfOverflows = ( BaseType_t ) 0; +PRIVILEGED_DATA static UBaseType_t uxTaskNumber = ( UBaseType_t ) 0U; +PRIVILEGED_DATA static volatile TickType_t xNextTaskUnblockTime = ( TickType_t ) 0U; /* Initialised to portMAX_DELAY before the scheduler starts. */ +PRIVILEGED_DATA static TaskHandle_t xIdleTaskHandles[ configNUMBER_OF_CORES ]; /**< Holds the handles of the idle tasks. The idle tasks are created automatically when the scheduler is started. */ + +/* Improve support for OpenOCD. The kernel tracks Ready tasks via priority lists. + * For tracking the state of remote threads, OpenOCD uses uxTopUsedPriority + * to determine the number of priority lists to read back from the remote target. */ +static const volatile UBaseType_t uxTopUsedPriority = configMAX_PRIORITIES - 1U; + +/* Context switches are held pending while the scheduler is suspended. Also, + * interrupts must not manipulate the xStateListItem of a TCB, or any of the + * lists the xStateListItem can be referenced from, if the scheduler is suspended. + * If an interrupt needs to unblock a task while the scheduler is suspended then it + * moves the task's event list item into the xPendingReadyList, ready for the + * kernel to move the task from the pending ready list into the real ready list + * when the scheduler is unsuspended. The pending ready list itself can only be + * accessed from a critical section. + * + * Updates to uxSchedulerSuspended must be protected by both the task lock and the ISR lock + * and must not be done from an ISR. Reads must be protected by either lock and may be done + * from either an ISR or a task. */ +PRIVILEGED_DATA static volatile UBaseType_t uxSchedulerSuspended = ( UBaseType_t ) 0U; + +#if ( configGENERATE_RUN_TIME_STATS == 1 ) + +/* Do not move these variables to function scope as doing so prevents the + * code working with debuggers that need to remove the static qualifier. */ +PRIVILEGED_DATA static configRUN_TIME_COUNTER_TYPE ulTaskSwitchedInTime[ configNUMBER_OF_CORES ] = { 0U }; /**< Holds the value of a timer/counter the last time a task was switched in. */ +PRIVILEGED_DATA static volatile configRUN_TIME_COUNTER_TYPE ulTotalRunTime[ configNUMBER_OF_CORES ] = { 0U }; /**< Holds the total amount of execution time as defined by the run time counter clock. */ + +#endif + +/*-----------------------------------------------------------*/ + +/* File private functions. --------------------------------*/ + +/* + * Creates the idle tasks during scheduler start. + */ +static BaseType_t prvCreateIdleTasks( void ); + +#if ( configNUMBER_OF_CORES > 1 ) + +/* + * Checks to see if another task moved the current task out of the ready + * list while it was waiting to enter a critical section and yields, if so. + */ + static void prvCheckForRunStateChange( void ); +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ + +#if ( configNUMBER_OF_CORES > 1 ) + +/* + * Yields a core, or cores if multiple priorities are not allowed to run + * simultaneously, to allow the task pxTCB to run. + */ + static void prvYieldForTask( const TCB_t * pxTCB ); +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ + +#if ( configNUMBER_OF_CORES > 1 ) + +/* + * Selects the highest priority available task for the given core. + */ + static void prvSelectHighestPriorityTask( BaseType_t xCoreID ); +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ + +/** + * Utility task that simply returns pdTRUE if the task referenced by xTask is + * currently in the Suspended state, or pdFALSE if the task referenced by xTask + * is in any other state. + */ +#if ( INCLUDE_vTaskSuspend == 1 ) + + static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +#endif /* INCLUDE_vTaskSuspend */ + +/* + * Utility to ready all the lists used by the scheduler. This is called + * automatically upon the creation of the first task. + */ +static void prvInitialiseTaskLists( void ) PRIVILEGED_FUNCTION; + +/* + * The idle task, which as all tasks is implemented as a never ending loop. + * The idle task is automatically created and added to the ready lists upon + * creation of the first user task. + * + * In the FreeRTOS SMP, configNUMBER_OF_CORES - 1 passive idle tasks are also + * created to ensure that each core has an idle task to run when no other + * task is available to run. + * + * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific + * language extensions. The equivalent prototype for these functions are: + * + * void prvIdleTask( void *pvParameters ); + * void prvPassiveIdleTask( void *pvParameters ); + * + */ +static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters ) PRIVILEGED_FUNCTION; +#if ( configNUMBER_OF_CORES > 1 ) + static portTASK_FUNCTION_PROTO( prvPassiveIdleTask, pvParameters ) PRIVILEGED_FUNCTION; +#endif + +/* + * Utility to free all memory allocated by the scheduler to hold a TCB, + * including the stack pointed to by the TCB. + * + * This does not free memory allocated by the task itself (i.e. memory + * allocated by calls to pvPortMalloc from within the tasks application code). + */ +#if ( INCLUDE_vTaskDelete == 1 ) + + static void prvDeleteTCB( TCB_t * pxTCB ) PRIVILEGED_FUNCTION; + +#endif + +/* + * Used only by the idle task. This checks to see if anything has been placed + * in the list of tasks waiting to be deleted. If so the task is cleaned up + * and its TCB deleted. + */ +static void prvCheckTasksWaitingTermination( void ) PRIVILEGED_FUNCTION; + +/* + * The currently executing task is entering the Blocked state. Add the task to + * either the current or the overflow delayed task list. + */ +static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, + const BaseType_t xCanBlockIndefinitely ) PRIVILEGED_FUNCTION; + +/* + * Fills an TaskStatus_t structure with information on each task that is + * referenced from the pxList list (which may be a ready list, a delayed list, + * a suspended list, etc.). + * + * THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM + * NORMAL APPLICATION CODE. + */ +#if ( configUSE_TRACE_FACILITY == 1 ) + + static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t * pxTaskStatusArray, + List_t * pxList, + eTaskState eState ) PRIVILEGED_FUNCTION; + +#endif + +/* + * Searches pxList for a task with name pcNameToQuery - returning a handle to + * the task if it is found, or NULL if the task is not found. + */ +#if ( INCLUDE_xTaskGetHandle == 1 ) + + static TCB_t * prvSearchForNameWithinSingleList( List_t * pxList, + const char pcNameToQuery[] ) PRIVILEGED_FUNCTION; + +#endif + +/* + * When a task is created, the stack of the task is filled with a known value. + * This function determines the 'high water mark' of the task stack by + * determining how much of the stack remains at the original preset value. + */ +#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) ) + + static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) PRIVILEGED_FUNCTION; + +#endif + +/* + * Return the amount of time, in ticks, that will pass before the kernel will + * next move a task from the Blocked state to the Running state or before the + * tick count overflows (whichever is earlier). + * + * This conditional compilation should use inequality to 0, not equality to 1. + * This is to ensure portSUPPRESS_TICKS_AND_SLEEP() can be called when user + * defined low power mode implementations require configUSE_TICKLESS_IDLE to be + * set to a value other than 1. + */ +#if ( configUSE_TICKLESS_IDLE != 0 ) + + static TickType_t prvGetExpectedIdleTime( void ) PRIVILEGED_FUNCTION; + +#endif + +/* + * Set xNextTaskUnblockTime to the time at which the next Blocked state task + * will exit the Blocked state. + */ +static void prvResetNextTaskUnblockTime( void ) PRIVILEGED_FUNCTION; + +#if ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) + +/* + * Helper function used to pad task names with spaces when printing out + * human readable tables of task information. + */ + static char * prvWriteNameToBuffer( char * pcBuffer, + const char * pcTaskName ) PRIVILEGED_FUNCTION; + +#endif + +/* + * Called after a Task_t structure has been allocated either statically or + * dynamically to fill in the structure's members. + */ +static void prvInitialiseNewTask( TaskFunction_t pxTaskCode, + const char * const pcName, + const configSTACK_DEPTH_TYPE uxStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * const pxCreatedTask, + TCB_t * pxNewTCB, + const MemoryRegion_t * const xRegions ) PRIVILEGED_FUNCTION; + +/* + * Called after a new task has been created and initialised to place the task + * under the control of the scheduler. + */ +static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION; + +/* + * Create a task with static buffer for both TCB and stack. Returns a handle to + * the task if it is created successfully. Otherwise, returns NULL. + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + static TCB_t * prvCreateStaticTask( TaskFunction_t pxTaskCode, + const char * const pcName, + const configSTACK_DEPTH_TYPE uxStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + StackType_t * const puxStackBuffer, + StaticTask_t * const pxTaskBuffer, + TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION; +#endif /* #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ + +/* + * Create a restricted task with static buffer for both TCB and stack. Returns + * a handle to the task if it is created successfully. Otherwise, returns NULL. + */ +#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + static TCB_t * prvCreateRestrictedStaticTask( const TaskParameters_t * const pxTaskDefinition, + TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION; +#endif /* #if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */ + +/* + * Create a restricted task with static buffer for task stack and allocated buffer + * for TCB. Returns a handle to the task if it is created successfully. Otherwise, + * returns NULL. + */ +#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + static TCB_t * prvCreateRestrictedTask( const TaskParameters_t * const pxTaskDefinition, + TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION; +#endif /* #if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ + +/* + * Create a task with allocated buffer for both TCB and stack. Returns a handle to + * the task if it is created successfully. Otherwise, returns NULL. + */ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + static TCB_t * prvCreateTask( TaskFunction_t pxTaskCode, + const char * const pcName, + const configSTACK_DEPTH_TYPE uxStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION; +#endif /* #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */ + +/* + * freertos_tasks_c_additions_init() should only be called if the user definable + * macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is the only macro + * called by the function. + */ +#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT + + static void freertos_tasks_c_additions_init( void ) PRIVILEGED_FUNCTION; + +#endif + +#if ( configUSE_PASSIVE_IDLE_HOOK == 1 ) + extern void vApplicationPassiveIdleHook( void ); +#endif /* #if ( configUSE_PASSIVE_IDLE_HOOK == 1 ) */ + +#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) + +/* + * Convert the snprintf return value to the number of characters + * written. The following are the possible cases: + * + * 1. The buffer supplied to snprintf is large enough to hold the + * generated string. The return value in this case is the number + * of characters actually written, not counting the terminating + * null character. + * 2. The buffer supplied to snprintf is NOT large enough to hold + * the generated string. The return value in this case is the + * number of characters that would have been written if the + * buffer had been sufficiently large, not counting the + * terminating null character. + * 3. Encoding error. The return value in this case is a negative + * number. + * + * From 1 and 2 above ==> Only when the return value is non-negative + * and less than the supplied buffer length, the string has been + * completely written. + */ + static size_t prvSnprintfReturnValueToCharsWritten( int iSnprintfReturnValue, + size_t n ); + +#endif /* #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + static void prvCheckForRunStateChange( void ) + { + UBaseType_t uxPrevCriticalNesting; + const TCB_t * pxThisTCB; + BaseType_t xCoreID = ( BaseType_t ) portGET_CORE_ID(); + + /* This must only be called from within a task. */ + portASSERT_IF_IN_ISR(); + + /* This function is always called with interrupts disabled + * so this is safe. */ + pxThisTCB = pxCurrentTCBs[ xCoreID ]; + + while( pxThisTCB->xTaskRunState == taskTASK_SCHEDULED_TO_YIELD ) + { + /* We are only here if we just entered a critical section + * or if we just suspended the scheduler, and another task + * has requested that we yield. + * + * This is slightly complicated since we need to save and restore + * the suspension and critical nesting counts, as well as release + * and reacquire the correct locks. And then, do it all over again + * if our state changed again during the reacquisition. */ + uxPrevCriticalNesting = portGET_CRITICAL_NESTING_COUNT( xCoreID ); + + if( uxPrevCriticalNesting > 0U ) + { + portSET_CRITICAL_NESTING_COUNT( xCoreID, 0U ); + portRELEASE_ISR_LOCK( xCoreID ); + } + else + { + /* The scheduler is suspended. uxSchedulerSuspended is updated + * only when the task is not requested to yield. */ + mtCOVERAGE_TEST_MARKER(); + } + + portRELEASE_TASK_LOCK( xCoreID ); + portMEMORY_BARRIER(); + configASSERT( pxThisTCB->xTaskRunState == taskTASK_SCHEDULED_TO_YIELD ); + + portENABLE_INTERRUPTS(); + + /* Enabling interrupts should cause this core to immediately service + * the pending interrupt and yield. After servicing the pending interrupt, + * the task needs to re-evaluate its run state within this loop, as + * other cores may have requested this task to yield, potentially altering + * its run state. */ + + portDISABLE_INTERRUPTS(); + + xCoreID = ( BaseType_t ) portGET_CORE_ID(); + portGET_TASK_LOCK( xCoreID ); + portGET_ISR_LOCK( xCoreID ); + + portSET_CRITICAL_NESTING_COUNT( xCoreID, uxPrevCriticalNesting ); + + if( uxPrevCriticalNesting == 0U ) + { + portRELEASE_ISR_LOCK( xCoreID ); + } + } + } +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ + +/*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + static void prvYieldForTask( const TCB_t * pxTCB ) + { + BaseType_t xLowestPriorityToPreempt; + BaseType_t xCurrentCoreTaskPriority; + BaseType_t xLowestPriorityCore = ( BaseType_t ) -1; + BaseType_t xCoreID; + const BaseType_t xCurrentCoreID = ( BaseType_t ) portGET_CORE_ID(); + + #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) + BaseType_t xYieldCount = 0; + #endif /* #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) */ + + /* This must be called from a critical section. */ + configASSERT( portGET_CRITICAL_NESTING_COUNT( xCurrentCoreID ) > 0U ); + + #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) + + /* No task should yield for this one if it is a lower priority + * than priority level of currently ready tasks. */ + if( pxTCB->uxPriority >= uxTopReadyPriority ) + #else + /* Yield is not required for a task which is already running. */ + if( taskTASK_IS_RUNNING( pxTCB ) == pdFALSE ) + #endif + { + xLowestPriorityToPreempt = ( BaseType_t ) pxTCB->uxPriority; + + /* xLowestPriorityToPreempt will be decremented to -1 if the priority of pxTCB + * is 0. This is ok as we will give system idle tasks a priority of -1 below. */ + --xLowestPriorityToPreempt; + + for( xCoreID = ( BaseType_t ) 0; xCoreID < ( BaseType_t ) configNUMBER_OF_CORES; xCoreID++ ) + { + xCurrentCoreTaskPriority = ( BaseType_t ) pxCurrentTCBs[ xCoreID ]->uxPriority; + + /* System idle tasks are being assigned a priority of tskIDLE_PRIORITY - 1 here. */ + if( ( pxCurrentTCBs[ xCoreID ]->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) != 0U ) + { + xCurrentCoreTaskPriority = ( BaseType_t ) ( xCurrentCoreTaskPriority - 1 ); + } + + if( ( taskTASK_IS_RUNNING( pxCurrentTCBs[ xCoreID ] ) != pdFALSE ) && ( xYieldPendings[ xCoreID ] == pdFALSE ) ) + { + #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) + if( taskTASK_IS_RUNNING( pxTCB ) == pdFALSE ) + #endif + { + if( xCurrentCoreTaskPriority <= xLowestPriorityToPreempt ) + { + #if ( configUSE_CORE_AFFINITY == 1 ) + if( ( pxTCB->uxCoreAffinityMask & ( ( UBaseType_t ) 1U << ( UBaseType_t ) xCoreID ) ) != 0U ) + #endif + { + #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 ) + if( pxCurrentTCBs[ xCoreID ]->xPreemptionDisable == pdFALSE ) + #endif + { + xLowestPriorityToPreempt = xCurrentCoreTaskPriority; + xLowestPriorityCore = xCoreID; + } + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) + { + /* Yield all currently running non-idle tasks with a priority lower than + * the task that needs to run. */ + if( ( xCurrentCoreTaskPriority > ( ( BaseType_t ) tskIDLE_PRIORITY - 1 ) ) && + ( xCurrentCoreTaskPriority < ( BaseType_t ) pxTCB->uxPriority ) ) + { + prvYieldCore( xCoreID ); + xYieldCount++; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) */ + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) + if( ( xYieldCount == 0 ) && ( xLowestPriorityCore >= 0 ) ) + #else /* #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) */ + if( xLowestPriorityCore >= 0 ) + #endif /* #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) */ + { + prvYieldCore( xLowestPriorityCore ); + } + + #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) + /* Verify that the calling core always yields to higher priority tasks. */ + if( ( ( pxCurrentTCBs[ xCurrentCoreID ]->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) == 0U ) && + ( pxTCB->uxPriority > pxCurrentTCBs[ xCurrentCoreID ]->uxPriority ) ) + { + configASSERT( ( xYieldPendings[ xCurrentCoreID ] == pdTRUE ) || + ( taskTASK_IS_RUNNING( pxCurrentTCBs[ xCurrentCoreID ] ) == pdFALSE ) ); + } + #endif + } + } +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + static void prvSelectHighestPriorityTask( BaseType_t xCoreID ) + { + UBaseType_t uxCurrentPriority = uxTopReadyPriority; + BaseType_t xTaskScheduled = pdFALSE; + BaseType_t xDecrementTopPriority = pdTRUE; + TCB_t * pxTCB = NULL; + + #if ( configUSE_CORE_AFFINITY == 1 ) + const TCB_t * pxPreviousTCB = NULL; + #endif + #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) + BaseType_t xPriorityDropped = pdFALSE; + #endif + + /* This function should be called when scheduler is running. */ + configASSERT( xSchedulerRunning == pdTRUE ); + + /* A new task is created and a running task with the same priority yields + * itself to run the new task. When a running task yields itself, it is still + * in the ready list. This running task will be selected before the new task + * since the new task is always added to the end of the ready list. + * The other problem is that the running task still in the same position of + * the ready list when it yields itself. It is possible that it will be selected + * earlier then other tasks which waits longer than this task. + * + * To fix these problems, the running task should be put to the end of the + * ready list before searching for the ready task in the ready list. */ + if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxCurrentTCBs[ xCoreID ]->uxPriority ] ), + &pxCurrentTCBs[ xCoreID ]->xStateListItem ) == pdTRUE ) + { + ( void ) uxListRemove( &pxCurrentTCBs[ xCoreID ]->xStateListItem ); + vListInsertEnd( &( pxReadyTasksLists[ pxCurrentTCBs[ xCoreID ]->uxPriority ] ), + &pxCurrentTCBs[ xCoreID ]->xStateListItem ); + } + + while( xTaskScheduled == pdFALSE ) + { + #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) + { + if( uxCurrentPriority < uxTopReadyPriority ) + { + /* We can't schedule any tasks, other than idle, that have a + * priority lower than the priority of a task currently running + * on another core. */ + uxCurrentPriority = tskIDLE_PRIORITY; + } + } + #endif + + if( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxCurrentPriority ] ) ) == pdFALSE ) + { + const List_t * const pxReadyList = &( pxReadyTasksLists[ uxCurrentPriority ] ); + const ListItem_t * pxEndMarker = listGET_END_MARKER( pxReadyList ); + ListItem_t * pxIterator; + + /* The ready task list for uxCurrentPriority is not empty, so uxTopReadyPriority + * must not be decremented any further. */ + xDecrementTopPriority = pdFALSE; + + for( pxIterator = listGET_HEAD_ENTRY( pxReadyList ); pxIterator != pxEndMarker; pxIterator = listGET_NEXT( pxIterator ) ) + { + /* MISRA Ref 11.5.3 [Void pointer assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + pxTCB = ( TCB_t * ) listGET_LIST_ITEM_OWNER( pxIterator ); + + #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) + { + /* When falling back to the idle priority because only one priority + * level is allowed to run at a time, we should ONLY schedule the true + * idle tasks, not user tasks at the idle priority. */ + if( uxCurrentPriority < uxTopReadyPriority ) + { + if( ( pxTCB->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) == 0U ) + { + continue; + } + } + } + #endif /* #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) */ + + if( pxTCB->xTaskRunState == taskTASK_NOT_RUNNING ) + { + #if ( configUSE_CORE_AFFINITY == 1 ) + if( ( pxTCB->uxCoreAffinityMask & ( ( UBaseType_t ) 1U << ( UBaseType_t ) xCoreID ) ) != 0U ) + #endif + { + /* If the task is not being executed by any core swap it in. */ + pxCurrentTCBs[ xCoreID ]->xTaskRunState = taskTASK_NOT_RUNNING; + #if ( configUSE_CORE_AFFINITY == 1 ) + pxPreviousTCB = pxCurrentTCBs[ xCoreID ]; + #endif + pxTCB->xTaskRunState = xCoreID; + pxCurrentTCBs[ xCoreID ] = pxTCB; + xTaskScheduled = pdTRUE; + } + } + else if( pxTCB == pxCurrentTCBs[ xCoreID ] ) + { + configASSERT( ( pxTCB->xTaskRunState == xCoreID ) || ( pxTCB->xTaskRunState == taskTASK_SCHEDULED_TO_YIELD ) ); + + #if ( configUSE_CORE_AFFINITY == 1 ) + if( ( pxTCB->uxCoreAffinityMask & ( ( UBaseType_t ) 1U << ( UBaseType_t ) xCoreID ) ) != 0U ) + #endif + { + /* The task is already running on this core, mark it as scheduled. */ + pxTCB->xTaskRunState = xCoreID; + xTaskScheduled = pdTRUE; + } + } + else + { + /* This task is running on the core other than xCoreID. */ + mtCOVERAGE_TEST_MARKER(); + } + + if( xTaskScheduled != pdFALSE ) + { + /* A task has been selected to run on this core. */ + break; + } + } + } + else + { + if( xDecrementTopPriority != pdFALSE ) + { + uxTopReadyPriority--; + #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) + { + xPriorityDropped = pdTRUE; + } + #endif + } + } + + /* There are configNUMBER_OF_CORES Idle tasks created when scheduler started. + * The scheduler should be able to select a task to run when uxCurrentPriority + * is tskIDLE_PRIORITY. uxCurrentPriority is never decreased to value blow + * tskIDLE_PRIORITY. */ + if( uxCurrentPriority > tskIDLE_PRIORITY ) + { + uxCurrentPriority--; + } + else + { + /* This function is called when idle task is not created. Break the + * loop to prevent uxCurrentPriority overrun. */ + break; + } + } + + #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) + { + if( xTaskScheduled == pdTRUE ) + { + if( xPriorityDropped != pdFALSE ) + { + /* There may be several ready tasks that were being prevented from running because there was + * a higher priority task running. Now that the last of the higher priority tasks is no longer + * running, make sure all the other idle tasks yield. */ + BaseType_t x; + + for( x = ( BaseType_t ) 0; x < ( BaseType_t ) configNUMBER_OF_CORES; x++ ) + { + if( ( pxCurrentTCBs[ x ]->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) != 0U ) + { + prvYieldCore( x ); + } + } + } + } + } + #endif /* #if ( configRUN_MULTIPLE_PRIORITIES == 0 ) */ + + #if ( configUSE_CORE_AFFINITY == 1 ) + { + if( xTaskScheduled == pdTRUE ) + { + if( ( pxPreviousTCB != NULL ) && ( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxPreviousTCB->uxPriority ] ), &( pxPreviousTCB->xStateListItem ) ) != pdFALSE ) ) + { + /* A ready task was just evicted from this core. See if it can be + * scheduled on any other core. */ + UBaseType_t uxCoreMap = pxPreviousTCB->uxCoreAffinityMask; + BaseType_t xLowestPriority = ( BaseType_t ) pxPreviousTCB->uxPriority; + BaseType_t xLowestPriorityCore = -1; + BaseType_t x; + + if( ( pxPreviousTCB->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) != 0U ) + { + xLowestPriority = xLowestPriority - 1; + } + + if( ( uxCoreMap & ( ( UBaseType_t ) 1U << ( UBaseType_t ) xCoreID ) ) != 0U ) + { + /* pxPreviousTCB was removed from this core and this core is not excluded + * from it's core affinity mask. + * + * pxPreviousTCB is preempted by the new higher priority task + * pxCurrentTCBs[ xCoreID ]. When searching a new core for pxPreviousTCB, + * we do not need to look at the cores on which pxCurrentTCBs[ xCoreID ] + * is allowed to run. The reason is - when more than one cores are + * eligible for an incoming task, we preempt the core with the minimum + * priority task. Because this core (i.e. xCoreID) was preempted for + * pxCurrentTCBs[ xCoreID ], this means that all the others cores + * where pxCurrentTCBs[ xCoreID ] can run, are running tasks with priority + * no lower than pxPreviousTCB's priority. Therefore, the only cores where + * which can be preempted for pxPreviousTCB are the ones where + * pxCurrentTCBs[ xCoreID ] is not allowed to run (and obviously, + * pxPreviousTCB is allowed to run). + * + * This is an optimization which reduces the number of cores needed to be + * searched for pxPreviousTCB to run. */ + uxCoreMap &= ~( pxCurrentTCBs[ xCoreID ]->uxCoreAffinityMask ); + } + else + { + /* pxPreviousTCB's core affinity mask is changed and it is no longer + * allowed to run on this core. Searching all the cores in pxPreviousTCB's + * new core affinity mask to find a core on which it can run. */ + } + + uxCoreMap &= ( ( 1U << configNUMBER_OF_CORES ) - 1U ); + + for( x = ( ( BaseType_t ) configNUMBER_OF_CORES - 1 ); x >= ( BaseType_t ) 0; x-- ) + { + UBaseType_t uxCore = ( UBaseType_t ) x; + BaseType_t xTaskPriority; + + if( ( uxCoreMap & ( ( UBaseType_t ) 1U << uxCore ) ) != 0U ) + { + xTaskPriority = ( BaseType_t ) pxCurrentTCBs[ uxCore ]->uxPriority; + + if( ( pxCurrentTCBs[ uxCore ]->uxTaskAttributes & taskATTRIBUTE_IS_IDLE ) != 0U ) + { + xTaskPriority = xTaskPriority - ( BaseType_t ) 1; + } + + uxCoreMap &= ~( ( UBaseType_t ) 1U << uxCore ); + + if( ( xTaskPriority < xLowestPriority ) && + ( taskTASK_IS_RUNNING( pxCurrentTCBs[ uxCore ] ) != pdFALSE ) && + ( xYieldPendings[ uxCore ] == pdFALSE ) ) + { + #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 ) + if( pxCurrentTCBs[ uxCore ]->xPreemptionDisable == pdFALSE ) + #endif + { + xLowestPriority = xTaskPriority; + xLowestPriorityCore = ( BaseType_t ) uxCore; + } + } + } + } + + if( xLowestPriorityCore >= 0 ) + { + prvYieldCore( xLowestPriorityCore ); + } + } + } + } + #endif /* #if ( configUSE_CORE_AFFINITY == 1 ) */ + } + +#endif /* ( configNUMBER_OF_CORES > 1 ) */ + +/*-----------------------------------------------------------*/ + +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + + static TCB_t * prvCreateStaticTask( TaskFunction_t pxTaskCode, + const char * const pcName, + const configSTACK_DEPTH_TYPE uxStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + StackType_t * const puxStackBuffer, + StaticTask_t * const pxTaskBuffer, + TaskHandle_t * const pxCreatedTask ) + { + TCB_t * pxNewTCB; + + configASSERT( puxStackBuffer != NULL ); + configASSERT( pxTaskBuffer != NULL ); + + #if ( configASSERT_DEFINED == 1 ) + { + /* Sanity check that the size of the structure used to declare a + * variable of type StaticTask_t equals the size of the real task + * structure. */ + volatile size_t xSize = sizeof( StaticTask_t ); + configASSERT( xSize == sizeof( TCB_t ) ); + ( void ) xSize; /* Prevent unused variable warning when configASSERT() is not used. */ + } + #endif /* configASSERT_DEFINED */ + + if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) ) + { + /* The memory used for the task's TCB and stack are passed into this + * function - use them. */ + /* MISRA Ref 11.3.1 [Misaligned access] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */ + /* coverity[misra_c_2012_rule_11_3_violation] */ + pxNewTCB = ( TCB_t * ) pxTaskBuffer; + ( void ) memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) ); + pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer; + + #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) + { + /* Tasks can be created statically or dynamically, so note this + * task was created statically in case the task is later deleted. */ + pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB; + } + #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ + + prvInitialiseNewTask( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL ); + } + else + { + pxNewTCB = NULL; + } + + return pxNewTCB; + } +/*-----------------------------------------------------------*/ + + TaskHandle_t xTaskCreateStatic( TaskFunction_t pxTaskCode, + const char * const pcName, + const configSTACK_DEPTH_TYPE uxStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + StackType_t * const puxStackBuffer, + StaticTask_t * const pxTaskBuffer ) + { + TaskHandle_t xReturn = NULL; + TCB_t * pxNewTCB; + + traceENTER_xTaskCreateStatic( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer ); + + pxNewTCB = prvCreateStaticTask( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer, &xReturn ); + + if( pxNewTCB != NULL ) + { + #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) + { + /* Set the task's affinity before scheduling it. */ + pxNewTCB->uxCoreAffinityMask = configTASK_DEFAULT_CORE_AFFINITY; + } + #endif + + prvAddNewTaskToReadyList( pxNewTCB ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceRETURN_xTaskCreateStatic( xReturn ); + + return xReturn; + } +/*-----------------------------------------------------------*/ + + #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) + TaskHandle_t xTaskCreateStaticAffinitySet( TaskFunction_t pxTaskCode, + const char * const pcName, + const configSTACK_DEPTH_TYPE uxStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + StackType_t * const puxStackBuffer, + StaticTask_t * const pxTaskBuffer, + UBaseType_t uxCoreAffinityMask ) + { + TaskHandle_t xReturn = NULL; + TCB_t * pxNewTCB; + + traceENTER_xTaskCreateStaticAffinitySet( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer, uxCoreAffinityMask ); + + pxNewTCB = prvCreateStaticTask( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer, &xReturn ); + + if( pxNewTCB != NULL ) + { + /* Set the task's affinity before scheduling it. */ + pxNewTCB->uxCoreAffinityMask = uxCoreAffinityMask; + + prvAddNewTaskToReadyList( pxNewTCB ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceRETURN_xTaskCreateStaticAffinitySet( xReturn ); + + return xReturn; + } + #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */ + +#endif /* SUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + static TCB_t * prvCreateRestrictedStaticTask( const TaskParameters_t * const pxTaskDefinition, + TaskHandle_t * const pxCreatedTask ) + { + TCB_t * pxNewTCB; + + configASSERT( pxTaskDefinition->puxStackBuffer != NULL ); + configASSERT( pxTaskDefinition->pxTaskBuffer != NULL ); + + if( ( pxTaskDefinition->puxStackBuffer != NULL ) && ( pxTaskDefinition->pxTaskBuffer != NULL ) ) + { + /* Allocate space for the TCB. Where the memory comes from depends + * on the implementation of the port malloc function and whether or + * not static allocation is being used. */ + pxNewTCB = ( TCB_t * ) pxTaskDefinition->pxTaskBuffer; + ( void ) memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) ); + + /* Store the stack location in the TCB. */ + pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer; + + #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) + { + /* Tasks can be created statically or dynamically, so note this + * task was created statically in case the task is later deleted. */ + pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB; + } + #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ + + prvInitialiseNewTask( pxTaskDefinition->pvTaskCode, + pxTaskDefinition->pcName, + pxTaskDefinition->usStackDepth, + pxTaskDefinition->pvParameters, + pxTaskDefinition->uxPriority, + pxCreatedTask, pxNewTCB, + pxTaskDefinition->xRegions ); + } + else + { + pxNewTCB = NULL; + } + + return pxNewTCB; + } +/*-----------------------------------------------------------*/ + + BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, + TaskHandle_t * pxCreatedTask ) + { + TCB_t * pxNewTCB; + BaseType_t xReturn; + + traceENTER_xTaskCreateRestrictedStatic( pxTaskDefinition, pxCreatedTask ); + + configASSERT( pxTaskDefinition != NULL ); + + pxNewTCB = prvCreateRestrictedStaticTask( pxTaskDefinition, pxCreatedTask ); + + if( pxNewTCB != NULL ) + { + #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) + { + /* Set the task's affinity before scheduling it. */ + pxNewTCB->uxCoreAffinityMask = configTASK_DEFAULT_CORE_AFFINITY; + } + #endif + + prvAddNewTaskToReadyList( pxNewTCB ); + xReturn = pdPASS; + } + else + { + xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + } + + traceRETURN_xTaskCreateRestrictedStatic( xReturn ); + + return xReturn; + } +/*-----------------------------------------------------------*/ + + #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) + BaseType_t xTaskCreateRestrictedStaticAffinitySet( const TaskParameters_t * const pxTaskDefinition, + UBaseType_t uxCoreAffinityMask, + TaskHandle_t * pxCreatedTask ) + { + TCB_t * pxNewTCB; + BaseType_t xReturn; + + traceENTER_xTaskCreateRestrictedStaticAffinitySet( pxTaskDefinition, uxCoreAffinityMask, pxCreatedTask ); + + configASSERT( pxTaskDefinition != NULL ); + + pxNewTCB = prvCreateRestrictedStaticTask( pxTaskDefinition, pxCreatedTask ); + + if( pxNewTCB != NULL ) + { + /* Set the task's affinity before scheduling it. */ + pxNewTCB->uxCoreAffinityMask = uxCoreAffinityMask; + + prvAddNewTaskToReadyList( pxNewTCB ); + xReturn = pdPASS; + } + else + { + xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + } + + traceRETURN_xTaskCreateRestrictedStaticAffinitySet( xReturn ); + + return xReturn; + } + #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */ + +#endif /* ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + static TCB_t * prvCreateRestrictedTask( const TaskParameters_t * const pxTaskDefinition, + TaskHandle_t * const pxCreatedTask ) + { + TCB_t * pxNewTCB; + + configASSERT( pxTaskDefinition->puxStackBuffer ); + + if( pxTaskDefinition->puxStackBuffer != NULL ) + { + /* MISRA Ref 11.5.1 [Malloc memory assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); + + if( pxNewTCB != NULL ) + { + ( void ) memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) ); + + /* Store the stack location in the TCB. */ + pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer; + + #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) + { + /* Tasks can be created statically or dynamically, so note + * this task had a statically allocated stack in case it is + * later deleted. The TCB was allocated dynamically. */ + pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_ONLY; + } + #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ + + prvInitialiseNewTask( pxTaskDefinition->pvTaskCode, + pxTaskDefinition->pcName, + pxTaskDefinition->usStackDepth, + pxTaskDefinition->pvParameters, + pxTaskDefinition->uxPriority, + pxCreatedTask, pxNewTCB, + pxTaskDefinition->xRegions ); + } + } + else + { + pxNewTCB = NULL; + } + + return pxNewTCB; + } +/*-----------------------------------------------------------*/ + + BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, + TaskHandle_t * pxCreatedTask ) + { + TCB_t * pxNewTCB; + BaseType_t xReturn; + + traceENTER_xTaskCreateRestricted( pxTaskDefinition, pxCreatedTask ); + + pxNewTCB = prvCreateRestrictedTask( pxTaskDefinition, pxCreatedTask ); + + if( pxNewTCB != NULL ) + { + #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) + { + /* Set the task's affinity before scheduling it. */ + pxNewTCB->uxCoreAffinityMask = configTASK_DEFAULT_CORE_AFFINITY; + } + #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */ + + prvAddNewTaskToReadyList( pxNewTCB ); + + xReturn = pdPASS; + } + else + { + xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + } + + traceRETURN_xTaskCreateRestricted( xReturn ); + + return xReturn; + } +/*-----------------------------------------------------------*/ + + #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) + BaseType_t xTaskCreateRestrictedAffinitySet( const TaskParameters_t * const pxTaskDefinition, + UBaseType_t uxCoreAffinityMask, + TaskHandle_t * pxCreatedTask ) + { + TCB_t * pxNewTCB; + BaseType_t xReturn; + + traceENTER_xTaskCreateRestrictedAffinitySet( pxTaskDefinition, uxCoreAffinityMask, pxCreatedTask ); + + pxNewTCB = prvCreateRestrictedTask( pxTaskDefinition, pxCreatedTask ); + + if( pxNewTCB != NULL ) + { + /* Set the task's affinity before scheduling it. */ + pxNewTCB->uxCoreAffinityMask = uxCoreAffinityMask; + + prvAddNewTaskToReadyList( pxNewTCB ); + + xReturn = pdPASS; + } + else + { + xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + } + + traceRETURN_xTaskCreateRestrictedAffinitySet( xReturn ); + + return xReturn; + } + #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */ + + +#endif /* portUSING_MPU_WRAPPERS */ +/*-----------------------------------------------------------*/ + +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + static TCB_t * prvCreateTask( TaskFunction_t pxTaskCode, + const char * const pcName, + const configSTACK_DEPTH_TYPE uxStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * const pxCreatedTask ) + { + TCB_t * pxNewTCB; + + /* If the stack grows down then allocate the stack then the TCB so the stack + * does not grow into the TCB. Likewise if the stack grows up then allocate + * the TCB then the stack. */ + #if ( portSTACK_GROWTH > 0 ) + { + /* Allocate space for the TCB. Where the memory comes from depends on + * the implementation of the port malloc function and whether or not static + * allocation is being used. */ + /* MISRA Ref 11.5.1 [Malloc memory assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); + + if( pxNewTCB != NULL ) + { + ( void ) memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) ); + + /* Allocate space for the stack used by the task being created. + * The base of the stack memory stored in the TCB so the task can + * be deleted later if required. */ + /* MISRA Ref 11.5.1 [Malloc memory assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + pxNewTCB->pxStack = ( StackType_t * ) pvPortMallocStack( ( ( ( size_t ) uxStackDepth ) * sizeof( StackType_t ) ) ); + + if( pxNewTCB->pxStack == NULL ) + { + /* Could not allocate the stack. Delete the allocated TCB. */ + vPortFree( pxNewTCB ); + pxNewTCB = NULL; + } + } + } + #else /* portSTACK_GROWTH */ + { + StackType_t * pxStack; + + /* Allocate space for the stack used by the task being created. */ + /* MISRA Ref 11.5.1 [Malloc memory assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + pxStack = ( StackType_t * ) pvPortMallocStack( ( ( ( size_t ) uxStackDepth ) * sizeof( StackType_t ) ) ); + + if( pxStack != NULL ) + { + /* Allocate space for the TCB. */ + /* MISRA Ref 11.5.1 [Malloc memory assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); + + if( pxNewTCB != NULL ) + { + ( void ) memset( ( void * ) pxNewTCB, 0x00, sizeof( TCB_t ) ); + + /* Store the stack location in the TCB. */ + pxNewTCB->pxStack = pxStack; + } + else + { + /* The stack cannot be used as the TCB was not created. Free + * it again. */ + vPortFreeStack( pxStack ); + } + } + else + { + pxNewTCB = NULL; + } + } + #endif /* portSTACK_GROWTH */ + + if( pxNewTCB != NULL ) + { + #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) + { + /* Tasks can be created statically or dynamically, so note this + * task was created dynamically in case it is later deleted. */ + pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB; + } + #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ + + prvInitialiseNewTask( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL ); + } + + return pxNewTCB; + } +/*-----------------------------------------------------------*/ + + BaseType_t xTaskCreate( TaskFunction_t pxTaskCode, + const char * const pcName, + const configSTACK_DEPTH_TYPE uxStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * const pxCreatedTask ) + { + TCB_t * pxNewTCB; + BaseType_t xReturn; + + traceENTER_xTaskCreate( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, pxCreatedTask ); + + pxNewTCB = prvCreateTask( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, pxCreatedTask ); + + if( pxNewTCB != NULL ) + { + #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) + { + /* Set the task's affinity before scheduling it. */ + pxNewTCB->uxCoreAffinityMask = configTASK_DEFAULT_CORE_AFFINITY; + } + #endif + + prvAddNewTaskToReadyList( pxNewTCB ); + xReturn = pdPASS; + } + else + { + xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + } + + traceRETURN_xTaskCreate( xReturn ); + + return xReturn; + } +/*-----------------------------------------------------------*/ + + #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) + BaseType_t xTaskCreateAffinitySet( TaskFunction_t pxTaskCode, + const char * const pcName, + const configSTACK_DEPTH_TYPE uxStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + UBaseType_t uxCoreAffinityMask, + TaskHandle_t * const pxCreatedTask ) + { + TCB_t * pxNewTCB; + BaseType_t xReturn; + + traceENTER_xTaskCreateAffinitySet( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, uxCoreAffinityMask, pxCreatedTask ); + + pxNewTCB = prvCreateTask( pxTaskCode, pcName, uxStackDepth, pvParameters, uxPriority, pxCreatedTask ); + + if( pxNewTCB != NULL ) + { + /* Set the task's affinity before scheduling it. */ + pxNewTCB->uxCoreAffinityMask = uxCoreAffinityMask; + + prvAddNewTaskToReadyList( pxNewTCB ); + xReturn = pdPASS; + } + else + { + xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + } + + traceRETURN_xTaskCreateAffinitySet( xReturn ); + + return xReturn; + } + #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */ + +#endif /* configSUPPORT_DYNAMIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +static void prvInitialiseNewTask( TaskFunction_t pxTaskCode, + const char * const pcName, + const configSTACK_DEPTH_TYPE uxStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * const pxCreatedTask, + TCB_t * pxNewTCB, + const MemoryRegion_t * const xRegions ) +{ + StackType_t * pxTopOfStack; + UBaseType_t x; + + #if ( portUSING_MPU_WRAPPERS == 1 ) + /* Should the task be created in privileged mode? */ + BaseType_t xRunPrivileged; + + if( ( uxPriority & portPRIVILEGE_BIT ) != 0U ) + { + xRunPrivileged = pdTRUE; + } + else + { + xRunPrivileged = pdFALSE; + } + uxPriority &= ~portPRIVILEGE_BIT; + #endif /* portUSING_MPU_WRAPPERS == 1 */ + + /* Avoid dependency on memset() if it is not required. */ + #if ( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 ) + { + /* Fill the stack with a known value to assist debugging. */ + ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) uxStackDepth * sizeof( StackType_t ) ); + } + #endif /* tskSET_NEW_STACKS_TO_KNOWN_VALUE */ + + /* Calculate the top of stack address. This depends on whether the stack + * grows from high memory to low (as per the 80x86) or vice versa. + * portSTACK_GROWTH is used to make the result positive or negative as required + * by the port. */ + #if ( portSTACK_GROWTH < 0 ) + { + pxTopOfStack = &( pxNewTCB->pxStack[ uxStackDepth - ( configSTACK_DEPTH_TYPE ) 1 ] ); + pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); + + /* Check the alignment of the calculated top of stack is correct. */ + configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0U ) ); + + #if ( configRECORD_STACK_HIGH_ADDRESS == 1 ) + { + /* Also record the stack's high address, which may assist + * debugging. */ + pxNewTCB->pxEndOfStack = pxTopOfStack; + } + #endif /* configRECORD_STACK_HIGH_ADDRESS */ + } + #else /* portSTACK_GROWTH */ + { + pxTopOfStack = pxNewTCB->pxStack; + pxTopOfStack = ( StackType_t * ) ( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) + portBYTE_ALIGNMENT_MASK ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); + + /* Check the alignment of the calculated top of stack is correct. */ + configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0U ) ); + + /* The other extreme of the stack space is required if stack checking is + * performed. */ + pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( uxStackDepth - ( configSTACK_DEPTH_TYPE ) 1 ); + } + #endif /* portSTACK_GROWTH */ + + /* Store the task name in the TCB. */ + if( pcName != NULL ) + { + for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) + { + pxNewTCB->pcTaskName[ x ] = pcName[ x ]; + + /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than + * configMAX_TASK_NAME_LEN characters just in case the memory after the + * string is not accessible (extremely unlikely). */ + if( pcName[ x ] == ( char ) 0x00 ) + { + break; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + /* Ensure the name string is terminated in the case that the string length + * was greater or equal to configMAX_TASK_NAME_LEN. */ + pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1U ] = '\0'; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* This is used as an array index so must ensure it's not too large. */ + configASSERT( uxPriority < configMAX_PRIORITIES ); + + if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES ) + { + uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + pxNewTCB->uxPriority = uxPriority; + #if ( configUSE_MUTEXES == 1 ) + { + pxNewTCB->uxBasePriority = uxPriority; + } + #endif /* configUSE_MUTEXES */ + + vListInitialiseItem( &( pxNewTCB->xStateListItem ) ); + vListInitialiseItem( &( pxNewTCB->xEventListItem ) ); + + /* Set the pxNewTCB as a link back from the ListItem_t. This is so we can get + * back to the containing TCB from a generic item in a list. */ + listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB ); + + /* Event lists are always in priority order. */ + listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); + listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB ); + + #if ( portUSING_MPU_WRAPPERS == 1 ) + { + vPortStoreTaskMPUSettings( &( pxNewTCB->xMPUSettings ), xRegions, pxNewTCB->pxStack, uxStackDepth ); + } + #else + { + /* Avoid compiler warning about unreferenced parameter. */ + ( void ) xRegions; + } + #endif + + #if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) + { + /* Allocate and initialize memory for the task's TLS Block. */ + configINIT_TLS_BLOCK( pxNewTCB->xTLSBlock, pxTopOfStack ); + } + #endif + + /* Initialize the TCB stack to look as if the task was already running, + * but had been interrupted by the scheduler. The return address is set + * to the start of the task function. Once the stack has been initialised + * the top of stack variable is updated. */ + #if ( portUSING_MPU_WRAPPERS == 1 ) + { + /* If the port has capability to detect stack overflow, + * pass the stack end address to the stack initialization + * function as well. */ + #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 ) + { + #if ( portSTACK_GROWTH < 0 ) + { + pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters, xRunPrivileged, &( pxNewTCB->xMPUSettings ) ); + } + #else /* portSTACK_GROWTH */ + { + pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters, xRunPrivileged, &( pxNewTCB->xMPUSettings ) ); + } + #endif /* portSTACK_GROWTH */ + } + #else /* portHAS_STACK_OVERFLOW_CHECKING */ + { + pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged, &( pxNewTCB->xMPUSettings ) ); + } + #endif /* portHAS_STACK_OVERFLOW_CHECKING */ + } + #else /* portUSING_MPU_WRAPPERS */ + { + /* If the port has capability to detect stack overflow, + * pass the stack end address to the stack initialization + * function as well. */ + #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 ) + { + #if ( portSTACK_GROWTH < 0 ) + { + pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters ); + } + #else /* portSTACK_GROWTH */ + { + pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters ); + } + #endif /* portSTACK_GROWTH */ + } + #else /* portHAS_STACK_OVERFLOW_CHECKING */ + { + pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters ); + } + #endif /* portHAS_STACK_OVERFLOW_CHECKING */ + + #if ( portSTACK_GROWTH < 0 ) + { + configASSERT( ( ( portPOINTER_SIZE_TYPE ) ( pxTopOfStack - pxNewTCB->pxTopOfStack ) ) < ( ( portPOINTER_SIZE_TYPE ) uxStackDepth ) ); + } + #else /* portSTACK_GROWTH */ + { + configASSERT( ( ( portPOINTER_SIZE_TYPE ) ( pxNewTCB->pxTopOfStack - pxTopOfStack ) ) < ( ( portPOINTER_SIZE_TYPE ) uxStackDepth ) ); + } + #endif /* portSTACK_GROWTH */ + } + #endif /* portUSING_MPU_WRAPPERS */ + + /* Initialize task state and task attributes. */ + #if ( configNUMBER_OF_CORES > 1 ) + { + pxNewTCB->xTaskRunState = taskTASK_NOT_RUNNING; + + /* Is this an idle task? */ + if( ( ( TaskFunction_t ) pxTaskCode == ( TaskFunction_t ) ( &prvIdleTask ) ) || ( ( TaskFunction_t ) pxTaskCode == ( TaskFunction_t ) ( &prvPassiveIdleTask ) ) ) + { + pxNewTCB->uxTaskAttributes |= taskATTRIBUTE_IS_IDLE; + } + } + #endif /* #if ( configNUMBER_OF_CORES > 1 ) */ + + if( pxCreatedTask != NULL ) + { + /* Pass the handle out in an anonymous way. The handle can be used to + * change the created task's priority, delete the created task, etc.*/ + *pxCreatedTask = ( TaskHandle_t ) pxNewTCB; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} +/*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES == 1 ) + + static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) + { + /* Ensure interrupts don't access the task lists while the lists are being + * updated. */ + taskENTER_CRITICAL(); + { + uxCurrentNumberOfTasks = ( UBaseType_t ) ( uxCurrentNumberOfTasks + 1U ); + + if( pxCurrentTCB == NULL ) + { + /* There are no other tasks, or all the other tasks are in + * the suspended state - make this the current task. */ + pxCurrentTCB = pxNewTCB; + + if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 ) + { + /* This is the first task to be created so do the preliminary + * initialisation required. We will not recover if this call + * fails, but we will report the failure. */ + prvInitialiseTaskLists(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* If the scheduler is not already running, make this task the + * current task if it is the highest priority task to be created + * so far. */ + if( xSchedulerRunning == pdFALSE ) + { + if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority ) + { + pxCurrentTCB = pxNewTCB; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + uxTaskNumber++; + + #if ( configUSE_TRACE_FACILITY == 1 ) + { + /* Add a counter into the TCB for tracing only. */ + pxNewTCB->uxTCBNumber = uxTaskNumber; + } + #endif /* configUSE_TRACE_FACILITY */ + traceTASK_CREATE( pxNewTCB ); + + prvAddTaskToReadyList( pxNewTCB ); + + portSETUP_TCB( pxNewTCB ); + } + taskEXIT_CRITICAL(); + + if( xSchedulerRunning != pdFALSE ) + { + /* If the created task is of a higher priority than the current task + * then it should run now. */ + taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxNewTCB ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + +#else /* #if ( configNUMBER_OF_CORES == 1 ) */ + + static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) + { + /* Ensure interrupts don't access the task lists while the lists are being + * updated. */ + taskENTER_CRITICAL(); + { + uxCurrentNumberOfTasks++; + + if( xSchedulerRunning == pdFALSE ) + { + if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 ) + { + /* This is the first task to be created so do the preliminary + * initialisation required. We will not recover if this call + * fails, but we will report the failure. */ + prvInitialiseTaskLists(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* All the cores start with idle tasks before the SMP scheduler + * is running. Idle tasks are assigned to cores when they are + * created in prvCreateIdleTasks(). */ + } + + uxTaskNumber++; + + #if ( configUSE_TRACE_FACILITY == 1 ) + { + /* Add a counter into the TCB for tracing only. */ + pxNewTCB->uxTCBNumber = uxTaskNumber; + } + #endif /* configUSE_TRACE_FACILITY */ + traceTASK_CREATE( pxNewTCB ); + + prvAddTaskToReadyList( pxNewTCB ); + + portSETUP_TCB( pxNewTCB ); + + if( xSchedulerRunning != pdFALSE ) + { + /* If the created task is of a higher priority than another + * currently running task and preemption is on then it should + * run now. */ + taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxNewTCB ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + } + +#endif /* #if ( configNUMBER_OF_CORES == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) + + static size_t prvSnprintfReturnValueToCharsWritten( int iSnprintfReturnValue, + size_t n ) + { + size_t uxCharsWritten; + + if( iSnprintfReturnValue < 0 ) + { + /* Encoding error - Return 0 to indicate that nothing + * was written to the buffer. */ + uxCharsWritten = 0; + } + else if( iSnprintfReturnValue >= ( int ) n ) + { + /* This is the case when the supplied buffer is not + * large to hold the generated string. Return the + * number of characters actually written without + * counting the terminating NULL character. */ + uxCharsWritten = n - 1U; + } + else + { + /* Complete string was written to the buffer. */ + uxCharsWritten = ( size_t ) iSnprintfReturnValue; + } + + return uxCharsWritten; + } + +#endif /* #if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskDelete == 1 ) + + void vTaskDelete( TaskHandle_t xTaskToDelete ) + { + TCB_t * pxTCB; + BaseType_t xDeleteTCBInIdleTask = pdFALSE; + BaseType_t xTaskIsRunningOrYielding; + + traceENTER_vTaskDelete( xTaskToDelete ); + + taskENTER_CRITICAL(); + { + /* If null is passed in here then it is the calling task that is + * being deleted. */ + pxTCB = prvGetTCBFromHandle( xTaskToDelete ); + configASSERT( pxTCB != NULL ); + + /* Remove task from the ready/delayed list. */ + if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + { + taskRESET_READY_PRIORITY( pxTCB->uxPriority ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Is the task waiting on an event also? */ + if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) + { + ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Increment the uxTaskNumber also so kernel aware debuggers can + * detect that the task lists need re-generating. This is done before + * portPRE_TASK_DELETE_HOOK() as in the Windows port that macro will + * not return. */ + uxTaskNumber++; + + /* Use temp variable as distinct sequence points for reading volatile + * variables prior to a logical operator to ensure compliance with + * MISRA C 2012 Rule 13.5. */ + xTaskIsRunningOrYielding = taskTASK_IS_RUNNING_OR_SCHEDULED_TO_YIELD( pxTCB ); + + /* If the task is running (or yielding), we must add it to the + * termination list so that an idle task can delete it when it is + * no longer running. */ + if( ( xSchedulerRunning != pdFALSE ) && ( xTaskIsRunningOrYielding != pdFALSE ) ) + { + /* A running task or a task which is scheduled to yield is being + * deleted. This cannot complete when the task is still running + * on a core, as a context switch to another task is required. + * Place the task in the termination list. The idle task will check + * the termination list and free up any memory allocated by the + * scheduler for the TCB and stack of the deleted task. */ + vListInsertEnd( &xTasksWaitingTermination, &( pxTCB->xStateListItem ) ); + + /* Increment the ucTasksDeleted variable so the idle task knows + * there is a task that has been deleted and that it should therefore + * check the xTasksWaitingTermination list. */ + ++uxDeletedTasksWaitingCleanUp; + + /* Call the delete hook before portPRE_TASK_DELETE_HOOK() as + * portPRE_TASK_DELETE_HOOK() does not return in the Win32 port. */ + traceTASK_DELETE( pxTCB ); + + /* Delete the task TCB in idle task. */ + xDeleteTCBInIdleTask = pdTRUE; + + /* The pre-delete hook is primarily for the Windows simulator, + * in which Windows specific clean up operations are performed, + * after which it is not possible to yield away from this task - + * hence xYieldPending is used to latch that a context switch is + * required. */ + #if ( configNUMBER_OF_CORES == 1 ) + portPRE_TASK_DELETE_HOOK( pxTCB, &( xYieldPendings[ 0 ] ) ); + #else + portPRE_TASK_DELETE_HOOK( pxTCB, &( xYieldPendings[ pxTCB->xTaskRunState ] ) ); + #endif + + /* In the case of SMP, it is possible that the task being deleted + * is running on another core. We must evict the task before + * exiting the critical section to ensure that the task cannot + * take an action which puts it back on ready/state/event list, + * thereby nullifying the delete operation. Once evicted, the + * task won't be scheduled ever as it will no longer be on the + * ready list. */ + #if ( configNUMBER_OF_CORES > 1 ) + { + if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE ) + { + if( pxTCB->xTaskRunState == ( BaseType_t ) portGET_CORE_ID() ) + { + configASSERT( uxSchedulerSuspended == 0 ); + taskYIELD_WITHIN_API(); + } + else + { + prvYieldCore( pxTCB->xTaskRunState ); + } + } + } + #endif /* #if ( configNUMBER_OF_CORES > 1 ) */ + } + else + { + --uxCurrentNumberOfTasks; + traceTASK_DELETE( pxTCB ); + + /* Reset the next expected unblock time in case it referred to + * the task that has just been deleted. */ + prvResetNextTaskUnblockTime(); + } + } + taskEXIT_CRITICAL(); + + /* If the task is not deleting itself, call prvDeleteTCB from outside of + * critical section. If a task deletes itself, prvDeleteTCB is called + * from prvCheckTasksWaitingTermination which is called from Idle task. */ + if( xDeleteTCBInIdleTask != pdTRUE ) + { + prvDeleteTCB( pxTCB ); + } + + /* Force a reschedule if it is the currently running task that has just + * been deleted. */ + #if ( configNUMBER_OF_CORES == 1 ) + { + if( xSchedulerRunning != pdFALSE ) + { + if( pxTCB == pxCurrentTCB ) + { + configASSERT( uxSchedulerSuspended == 0 ); + taskYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ + + traceRETURN_vTaskDelete(); + } + +#endif /* INCLUDE_vTaskDelete */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_xTaskDelayUntil == 1 ) + + BaseType_t xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) + { + TickType_t xTimeToWake; + BaseType_t xAlreadyYielded, xShouldDelay = pdFALSE; + + traceENTER_xTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement ); + + configASSERT( pxPreviousWakeTime ); + configASSERT( ( xTimeIncrement > 0U ) ); + + vTaskSuspendAll(); + { + /* Minor optimisation. The tick count cannot change in this + * block. */ + const TickType_t xConstTickCount = xTickCount; + + configASSERT( uxSchedulerSuspended == 1U ); + + /* Generate the tick time at which the task wants to wake. */ + xTimeToWake = *pxPreviousWakeTime + xTimeIncrement; + + if( xConstTickCount < *pxPreviousWakeTime ) + { + /* The tick count has overflowed since this function was + * lasted called. In this case the only time we should ever + * actually delay is if the wake time has also overflowed, + * and the wake time is greater than the tick time. When this + * is the case it is as if neither time had overflowed. */ + if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xConstTickCount ) ) + { + xShouldDelay = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* The tick time has not overflowed. In this case we will + * delay if either the wake time has overflowed, and/or the + * tick time is less than the wake time. */ + if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xConstTickCount ) ) + { + xShouldDelay = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + /* Update the wake time ready for the next call. */ + *pxPreviousWakeTime = xTimeToWake; + + if( xShouldDelay != pdFALSE ) + { + traceTASK_DELAY_UNTIL( xTimeToWake ); + + /* prvAddCurrentTaskToDelayedList() needs the block time, not + * the time to wake, so subtract the current tick count. */ + prvAddCurrentTaskToDelayedList( xTimeToWake - xConstTickCount, pdFALSE ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + xAlreadyYielded = xTaskResumeAll(); + + /* Force a reschedule if xTaskResumeAll has not already done so, we may + * have put ourselves to sleep. */ + if( xAlreadyYielded == pdFALSE ) + { + taskYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceRETURN_xTaskDelayUntil( xShouldDelay ); + + return xShouldDelay; + } + +#endif /* INCLUDE_xTaskDelayUntil */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskDelay == 1 ) + + void vTaskDelay( const TickType_t xTicksToDelay ) + { + BaseType_t xAlreadyYielded = pdFALSE; + + traceENTER_vTaskDelay( xTicksToDelay ); + + /* A delay time of zero just forces a reschedule. */ + if( xTicksToDelay > ( TickType_t ) 0U ) + { + vTaskSuspendAll(); + { + configASSERT( uxSchedulerSuspended == 1U ); + + traceTASK_DELAY(); + + /* A task that is removed from the event list while the + * scheduler is suspended will not get placed in the ready + * list or removed from the blocked list until the scheduler + * is resumed. + * + * This task cannot be in an event list as it is the currently + * executing task. */ + prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE ); + } + xAlreadyYielded = xTaskResumeAll(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Force a reschedule if xTaskResumeAll has not already done so, we may + * have put ourselves to sleep. */ + if( xAlreadyYielded == pdFALSE ) + { + taskYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceRETURN_vTaskDelay(); + } + +#endif /* INCLUDE_vTaskDelay */ +/*-----------------------------------------------------------*/ + +#if ( ( INCLUDE_eTaskGetState == 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_xTaskAbortDelay == 1 ) ) + + eTaskState eTaskGetState( TaskHandle_t xTask ) + { + eTaskState eReturn; + List_t const * pxStateList; + List_t const * pxEventList; + List_t const * pxDelayedList; + List_t const * pxOverflowedDelayedList; + const TCB_t * const pxTCB = xTask; + + traceENTER_eTaskGetState( xTask ); + + configASSERT( pxTCB != NULL ); + + #if ( configNUMBER_OF_CORES == 1 ) + if( pxTCB == pxCurrentTCB ) + { + /* The task calling this function is querying its own state. */ + eReturn = eRunning; + } + else + #endif + { + taskENTER_CRITICAL(); + { + pxStateList = listLIST_ITEM_CONTAINER( &( pxTCB->xStateListItem ) ); + pxEventList = listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ); + pxDelayedList = pxDelayedTaskList; + pxOverflowedDelayedList = pxOverflowDelayedTaskList; + } + taskEXIT_CRITICAL(); + + if( pxEventList == &xPendingReadyList ) + { + /* The task has been placed on the pending ready list, so its + * state is eReady regardless of what list the task's state list + * item is currently placed on. */ + eReturn = eReady; + } + else if( ( pxStateList == pxDelayedList ) || ( pxStateList == pxOverflowedDelayedList ) ) + { + /* The task being queried is referenced from one of the Blocked + * lists. */ + eReturn = eBlocked; + } + + #if ( INCLUDE_vTaskSuspend == 1 ) + else if( pxStateList == &xSuspendedTaskList ) + { + /* The task being queried is referenced from the suspended + * list. Is it genuinely suspended or is it blocked + * indefinitely? */ + if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL ) + { + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + { + BaseType_t x; + + /* The task does not appear on the event list item of + * and of the RTOS objects, but could still be in the + * blocked state if it is waiting on its notification + * rather than waiting on an object. If not, is + * suspended. */ + eReturn = eSuspended; + + for( x = ( BaseType_t ) 0; x < ( BaseType_t ) configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ ) + { + if( pxTCB->ucNotifyState[ x ] == taskWAITING_NOTIFICATION ) + { + eReturn = eBlocked; + break; + } + } + } + #else /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ + { + eReturn = eSuspended; + } + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ + } + else + { + eReturn = eBlocked; + } + } + #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ + + #if ( INCLUDE_vTaskDelete == 1 ) + else if( ( pxStateList == &xTasksWaitingTermination ) || ( pxStateList == NULL ) ) + { + /* The task being queried is referenced from the deleted + * tasks list, or it is not referenced from any lists at + * all. */ + eReturn = eDeleted; + } + #endif + + else + { + #if ( configNUMBER_OF_CORES == 1 ) + { + /* If the task is not in any other state, it must be in the + * Ready (including pending ready) state. */ + eReturn = eReady; + } + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + { + if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE ) + { + /* Is it actively running on a core? */ + eReturn = eRunning; + } + else + { + /* If the task is not in any other state, it must be in the + * Ready (including pending ready) state. */ + eReturn = eReady; + } + } + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ + } + } + + traceRETURN_eTaskGetState( eReturn ); + + return eReturn; + } + +#endif /* INCLUDE_eTaskGetState */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_uxTaskPriorityGet == 1 ) + + UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask ) + { + TCB_t const * pxTCB; + UBaseType_t uxReturn; + + traceENTER_uxTaskPriorityGet( xTask ); + + portBASE_TYPE_ENTER_CRITICAL(); + { + /* If null is passed in here then it is the priority of the task + * that called uxTaskPriorityGet() that is being queried. */ + pxTCB = prvGetTCBFromHandle( xTask ); + configASSERT( pxTCB != NULL ); + + uxReturn = pxTCB->uxPriority; + } + portBASE_TYPE_EXIT_CRITICAL(); + + traceRETURN_uxTaskPriorityGet( uxReturn ); + + return uxReturn; + } + +#endif /* INCLUDE_uxTaskPriorityGet */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_uxTaskPriorityGet == 1 ) + + UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) + { + TCB_t const * pxTCB; + UBaseType_t uxReturn; + UBaseType_t uxSavedInterruptStatus; + + traceENTER_uxTaskPriorityGetFromISR( xTask ); + + /* RTOS ports that support interrupt nesting have the concept of a + * maximum system call (or maximum API call) interrupt priority. + * Interrupts that are above the maximum system call priority are keep + * permanently enabled, even when the RTOS kernel is in a critical section, + * but cannot make any calls to FreeRTOS API functions. If configASSERT() + * is defined in FreeRTOSConfig.h then + * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has + * been assigned a priority above the configured maximum system call + * priority. Only FreeRTOS functions that end in FromISR can be called + * from interrupts that have been assigned a priority at or (logically) + * below the maximum system call interrupt priority. FreeRTOS maintains a + * separate interrupt safe API to ensure interrupt entry is as fast and as + * simple as possible. More information (albeit Cortex-M specific) is + * provided on the following link: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + /* MISRA Ref 4.7.1 [Return value shall be checked] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */ + /* coverity[misra_c_2012_directive_4_7_violation] */ + uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR(); + { + /* If null is passed in here then it is the priority of the calling + * task that is being queried. */ + pxTCB = prvGetTCBFromHandle( xTask ); + configASSERT( pxTCB != NULL ); + + uxReturn = pxTCB->uxPriority; + } + taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + + traceRETURN_uxTaskPriorityGetFromISR( uxReturn ); + + return uxReturn; + } + +#endif /* INCLUDE_uxTaskPriorityGet */ +/*-----------------------------------------------------------*/ + +#if ( ( INCLUDE_uxTaskPriorityGet == 1 ) && ( configUSE_MUTEXES == 1 ) ) + + UBaseType_t uxTaskBasePriorityGet( const TaskHandle_t xTask ) + { + TCB_t const * pxTCB; + UBaseType_t uxReturn; + + traceENTER_uxTaskBasePriorityGet( xTask ); + + portBASE_TYPE_ENTER_CRITICAL(); + { + /* If null is passed in here then it is the base priority of the task + * that called uxTaskBasePriorityGet() that is being queried. */ + pxTCB = prvGetTCBFromHandle( xTask ); + configASSERT( pxTCB != NULL ); + + uxReturn = pxTCB->uxBasePriority; + } + portBASE_TYPE_EXIT_CRITICAL(); + + traceRETURN_uxTaskBasePriorityGet( uxReturn ); + + return uxReturn; + } + +#endif /* #if ( ( INCLUDE_uxTaskPriorityGet == 1 ) && ( configUSE_MUTEXES == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( INCLUDE_uxTaskPriorityGet == 1 ) && ( configUSE_MUTEXES == 1 ) ) + + UBaseType_t uxTaskBasePriorityGetFromISR( const TaskHandle_t xTask ) + { + TCB_t const * pxTCB; + UBaseType_t uxReturn; + UBaseType_t uxSavedInterruptStatus; + + traceENTER_uxTaskBasePriorityGetFromISR( xTask ); + + /* RTOS ports that support interrupt nesting have the concept of a + * maximum system call (or maximum API call) interrupt priority. + * Interrupts that are above the maximum system call priority are keep + * permanently enabled, even when the RTOS kernel is in a critical section, + * but cannot make any calls to FreeRTOS API functions. If configASSERT() + * is defined in FreeRTOSConfig.h then + * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has + * been assigned a priority above the configured maximum system call + * priority. Only FreeRTOS functions that end in FromISR can be called + * from interrupts that have been assigned a priority at or (logically) + * below the maximum system call interrupt priority. FreeRTOS maintains a + * separate interrupt safe API to ensure interrupt entry is as fast and as + * simple as possible. More information (albeit Cortex-M specific) is + * provided on the following link: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + /* MISRA Ref 4.7.1 [Return value shall be checked] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */ + /* coverity[misra_c_2012_directive_4_7_violation] */ + uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR(); + { + /* If null is passed in here then it is the base priority of the calling + * task that is being queried. */ + pxTCB = prvGetTCBFromHandle( xTask ); + configASSERT( pxTCB != NULL ); + + uxReturn = pxTCB->uxBasePriority; + } + taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + + traceRETURN_uxTaskBasePriorityGetFromISR( uxReturn ); + + return uxReturn; + } + +#endif /* #if ( ( INCLUDE_uxTaskPriorityGet == 1 ) && ( configUSE_MUTEXES == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskPrioritySet == 1 ) + + void vTaskPrioritySet( TaskHandle_t xTask, + UBaseType_t uxNewPriority ) + { + TCB_t * pxTCB; + UBaseType_t uxCurrentBasePriority, uxPriorityUsedOnEntry; + BaseType_t xYieldRequired = pdFALSE; + + #if ( configNUMBER_OF_CORES > 1 ) + BaseType_t xYieldForTask = pdFALSE; + #endif + + traceENTER_vTaskPrioritySet( xTask, uxNewPriority ); + + configASSERT( uxNewPriority < configMAX_PRIORITIES ); + + /* Ensure the new priority is valid. */ + if( uxNewPriority >= ( UBaseType_t ) configMAX_PRIORITIES ) + { + uxNewPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + taskENTER_CRITICAL(); + { + /* If null is passed in here then it is the priority of the calling + * task that is being changed. */ + pxTCB = prvGetTCBFromHandle( xTask ); + configASSERT( pxTCB != NULL ); + + traceTASK_PRIORITY_SET( pxTCB, uxNewPriority ); + + #if ( configUSE_MUTEXES == 1 ) + { + uxCurrentBasePriority = pxTCB->uxBasePriority; + } + #else + { + uxCurrentBasePriority = pxTCB->uxPriority; + } + #endif + + if( uxCurrentBasePriority != uxNewPriority ) + { + /* The priority change may have readied a task of higher + * priority than a running task. */ + if( uxNewPriority > uxCurrentBasePriority ) + { + #if ( configNUMBER_OF_CORES == 1 ) + { + if( pxTCB != pxCurrentTCB ) + { + /* The priority of a task other than the currently + * running task is being raised. Is the priority being + * raised above that of the running task? */ + if( uxNewPriority > pxCurrentTCB->uxPriority ) + { + xYieldRequired = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* The priority of the running task is being raised, + * but the running task must already be the highest + * priority task able to run so no yield is required. */ + } + } + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + { + /* The priority of a task is being raised so + * perform a yield for this task later. */ + xYieldForTask = pdTRUE; + } + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ + } + else if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE ) + { + /* Setting the priority of a running task down means + * there may now be another task of higher priority that + * is ready to execute. */ + #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 ) + if( pxTCB->xPreemptionDisable == pdFALSE ) + #endif + { + xYieldRequired = pdTRUE; + } + } + else + { + /* Setting the priority of any other task down does not + * require a yield as the running task must be above the + * new priority of the task being modified. */ + } + + /* Remember the ready list the task might be referenced from + * before its uxPriority member is changed so the + * taskRESET_READY_PRIORITY() macro can function correctly. */ + uxPriorityUsedOnEntry = pxTCB->uxPriority; + + #if ( configUSE_MUTEXES == 1 ) + { + /* Only change the priority being used if the task is not + * currently using an inherited priority or the new priority + * is bigger than the inherited priority. */ + if( ( pxTCB->uxBasePriority == pxTCB->uxPriority ) || ( uxNewPriority > pxTCB->uxPriority ) ) + { + pxTCB->uxPriority = uxNewPriority; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* The base priority gets set whatever. */ + pxTCB->uxBasePriority = uxNewPriority; + } + #else /* if ( configUSE_MUTEXES == 1 ) */ + { + pxTCB->uxPriority = uxNewPriority; + } + #endif /* if ( configUSE_MUTEXES == 1 ) */ + + /* Only reset the event list item value if the value is not + * being used for anything else. */ + if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == ( ( TickType_t ) 0U ) ) + { + listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxNewPriority ) ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* If the task is in the blocked or suspended list we need do + * nothing more than change its priority variable. However, if + * the task is in a ready list it needs to be removed and placed + * in the list appropriate to its new priority. */ + if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE ) + { + /* The task is currently in its ready list - remove before + * adding it to its new ready list. As we are in a critical + * section we can do this even if the scheduler is suspended. */ + if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + { + /* It is known that the task is in its ready list so + * there is no need to check again and the port level + * reset macro can be called directly. */ + portRESET_READY_PRIORITY( uxPriorityUsedOnEntry, uxTopReadyPriority ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + prvAddTaskToReadyList( pxTCB ); + } + else + { + #if ( configNUMBER_OF_CORES == 1 ) + { + mtCOVERAGE_TEST_MARKER(); + } + #else + { + /* It's possible that xYieldForTask was already set to pdTRUE because + * its priority is being raised. However, since it is not in a ready list + * we don't actually need to yield for it. */ + xYieldForTask = pdFALSE; + } + #endif + } + + if( xYieldRequired != pdFALSE ) + { + /* The running task priority is set down. Request the task to yield. */ + taskYIELD_TASK_CORE_IF_USING_PREEMPTION( pxTCB ); + } + else + { + #if ( configNUMBER_OF_CORES > 1 ) + if( xYieldForTask != pdFALSE ) + { + /* The priority of the task is being raised. If a running + * task has priority lower than this task, it should yield + * for this task. */ + taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxTCB ); + } + else + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + { + mtCOVERAGE_TEST_MARKER(); + } + } + + /* Remove compiler warning about unused variables when the port + * optimised task selection is not being used. */ + ( void ) uxPriorityUsedOnEntry; + } + } + taskEXIT_CRITICAL(); + + traceRETURN_vTaskPrioritySet(); + } + +#endif /* INCLUDE_vTaskPrioritySet */ +/*-----------------------------------------------------------*/ + +#if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) + void vTaskCoreAffinitySet( const TaskHandle_t xTask, + UBaseType_t uxCoreAffinityMask ) + { + TCB_t * pxTCB; + BaseType_t xCoreID; + + traceENTER_vTaskCoreAffinitySet( xTask, uxCoreAffinityMask ); + + taskENTER_CRITICAL(); + { + pxTCB = prvGetTCBFromHandle( xTask ); + configASSERT( pxTCB != NULL ); + + pxTCB->uxCoreAffinityMask = uxCoreAffinityMask; + + if( xSchedulerRunning != pdFALSE ) + { + if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE ) + { + xCoreID = ( BaseType_t ) pxTCB->xTaskRunState; + + /* If the task can no longer run on the core it was running, + * request the core to yield. */ + if( ( uxCoreAffinityMask & ( ( UBaseType_t ) 1U << ( UBaseType_t ) xCoreID ) ) == 0U ) + { + prvYieldCore( xCoreID ); + } + } + else + { + #if ( configUSE_PREEMPTION == 1 ) + { + /* The SMP scheduler requests a core to yield when a ready + * task is able to run. It is possible that the core affinity + * of the ready task is changed before the requested core + * can select it to run. In that case, the task may not be + * selected by the previously requested core due to core affinity + * constraint and the SMP scheduler must select a new core to + * yield for the task. */ + prvYieldForTask( xTask ); + } + #else /* #if( configUSE_PREEMPTION == 1 ) */ + { + mtCOVERAGE_TEST_MARKER(); + } + #endif /* #if( configUSE_PREEMPTION == 1 ) */ + } + } + } + taskEXIT_CRITICAL(); + + traceRETURN_vTaskCoreAffinitySet(); + } +#endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) + UBaseType_t vTaskCoreAffinityGet( ConstTaskHandle_t xTask ) + { + const TCB_t * pxTCB; + UBaseType_t uxCoreAffinityMask; + + traceENTER_vTaskCoreAffinityGet( xTask ); + + portBASE_TYPE_ENTER_CRITICAL(); + { + pxTCB = prvGetTCBFromHandle( xTask ); + configASSERT( pxTCB != NULL ); + + uxCoreAffinityMask = pxTCB->uxCoreAffinityMask; + } + portBASE_TYPE_EXIT_CRITICAL(); + + traceRETURN_vTaskCoreAffinityGet( uxCoreAffinityMask ); + + return uxCoreAffinityMask; + } +#endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */ + +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_PREEMPTION_DISABLE == 1 ) + + void vTaskPreemptionDisable( const TaskHandle_t xTask ) + { + TCB_t * pxTCB; + + traceENTER_vTaskPreemptionDisable( xTask ); + + taskENTER_CRITICAL(); + { + pxTCB = prvGetTCBFromHandle( xTask ); + configASSERT( pxTCB != NULL ); + + pxTCB->xPreemptionDisable = pdTRUE; + } + taskEXIT_CRITICAL(); + + traceRETURN_vTaskPreemptionDisable(); + } + +#endif /* #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_PREEMPTION_DISABLE == 1 ) + + void vTaskPreemptionEnable( const TaskHandle_t xTask ) + { + TCB_t * pxTCB; + BaseType_t xCoreID; + + traceENTER_vTaskPreemptionEnable( xTask ); + + taskENTER_CRITICAL(); + { + pxTCB = prvGetTCBFromHandle( xTask ); + configASSERT( pxTCB != NULL ); + + pxTCB->xPreemptionDisable = pdFALSE; + + if( xSchedulerRunning != pdFALSE ) + { + if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE ) + { + xCoreID = ( BaseType_t ) pxTCB->xTaskRunState; + prvYieldCore( xCoreID ); + } + } + } + taskEXIT_CRITICAL(); + + traceRETURN_vTaskPreemptionEnable(); + } + +#endif /* #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskSuspend == 1 ) + + void vTaskSuspend( TaskHandle_t xTaskToSuspend ) + { + TCB_t * pxTCB; + + traceENTER_vTaskSuspend( xTaskToSuspend ); + + taskENTER_CRITICAL(); + { + /* If null is passed in here then it is the running task that is + * being suspended. */ + pxTCB = prvGetTCBFromHandle( xTaskToSuspend ); + configASSERT( pxTCB != NULL ); + + traceTASK_SUSPEND( pxTCB ); + + /* Remove task from the ready/delayed list and place in the + * suspended list. */ + if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + { + taskRESET_READY_PRIORITY( pxTCB->uxPriority ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Is the task waiting on an event also? */ + if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) + { + ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + vListInsertEnd( &xSuspendedTaskList, &( pxTCB->xStateListItem ) ); + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + { + BaseType_t x; + + for( x = ( BaseType_t ) 0; x < ( BaseType_t ) configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ ) + { + if( pxTCB->ucNotifyState[ x ] == taskWAITING_NOTIFICATION ) + { + /* The task was blocked to wait for a notification, but is + * now suspended, so no notification was received. */ + pxTCB->ucNotifyState[ x ] = taskNOT_WAITING_NOTIFICATION; + } + } + } + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ + + /* In the case of SMP, it is possible that the task being suspended + * is running on another core. We must evict the task before + * exiting the critical section to ensure that the task cannot + * take an action which puts it back on ready/state/event list, + * thereby nullifying the suspend operation. Once evicted, the + * task won't be scheduled before it is resumed as it will no longer + * be on the ready list. */ + #if ( configNUMBER_OF_CORES > 1 ) + { + if( xSchedulerRunning != pdFALSE ) + { + /* Reset the next expected unblock time in case it referred to the + * task that is now in the Suspended state. */ + prvResetNextTaskUnblockTime(); + + if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE ) + { + if( pxTCB->xTaskRunState == ( BaseType_t ) portGET_CORE_ID() ) + { + /* The current task has just been suspended. */ + configASSERT( uxSchedulerSuspended == 0 ); + vTaskYieldWithinAPI(); + } + else + { + prvYieldCore( pxTCB->xTaskRunState ); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* #if ( configNUMBER_OF_CORES > 1 ) */ + } + taskEXIT_CRITICAL(); + + #if ( configNUMBER_OF_CORES == 1 ) + { + UBaseType_t uxCurrentListLength; + + if( xSchedulerRunning != pdFALSE ) + { + /* Reset the next expected unblock time in case it referred to the + * task that is now in the Suspended state. */ + taskENTER_CRITICAL(); + { + prvResetNextTaskUnblockTime(); + } + taskEXIT_CRITICAL(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( pxTCB == pxCurrentTCB ) + { + if( xSchedulerRunning != pdFALSE ) + { + /* The current task has just been suspended. */ + configASSERT( uxSchedulerSuspended == 0 ); + portYIELD_WITHIN_API(); + } + else + { + /* The scheduler is not running, but the task that was pointed + * to by pxCurrentTCB has just been suspended and pxCurrentTCB + * must be adjusted to point to a different task. */ + + /* Use a temp variable as a distinct sequence point for reading + * volatile variables prior to a comparison to ensure compliance + * with MISRA C 2012 Rule 13.2. */ + uxCurrentListLength = listCURRENT_LIST_LENGTH( &xSuspendedTaskList ); + + if( uxCurrentListLength == uxCurrentNumberOfTasks ) + { + /* No other tasks are ready, so set pxCurrentTCB back to + * NULL so when the next task is created pxCurrentTCB will + * be set to point to it no matter what its relative priority + * is. */ + pxCurrentTCB = NULL; + } + else + { + vTaskSwitchContext(); + } + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ + + traceRETURN_vTaskSuspend(); + } + +#endif /* INCLUDE_vTaskSuspend */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskSuspend == 1 ) + + static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask ) + { + BaseType_t xReturn = pdFALSE; + const TCB_t * const pxTCB = xTask; + + /* Accesses xPendingReadyList so must be called from a critical + * section. */ + + /* It does not make sense to check if the calling task is suspended. */ + configASSERT( xTask ); + + /* Is the task being resumed actually in the suspended list? */ + if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xStateListItem ) ) != pdFALSE ) + { + /* Has the task already been resumed from within an ISR? */ + if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) == pdFALSE ) + { + /* Is it in the suspended list because it is in the Suspended + * state, or because it is blocked with no timeout? */ + if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) != pdFALSE ) + { + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + { + BaseType_t x; + + /* The task does not appear on the event list item of + * and of the RTOS objects, but could still be in the + * blocked state if it is waiting on its notification + * rather than waiting on an object. If not, is + * suspended. */ + xReturn = pdTRUE; + + for( x = ( BaseType_t ) 0; x < ( BaseType_t ) configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ ) + { + if( pxTCB->ucNotifyState[ x ] == taskWAITING_NOTIFICATION ) + { + xReturn = pdFALSE; + break; + } + } + } + #else /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ + { + xReturn = pdTRUE; + } + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xReturn; + } + +#endif /* INCLUDE_vTaskSuspend */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskSuspend == 1 ) + + void vTaskResume( TaskHandle_t xTaskToResume ) + { + TCB_t * const pxTCB = xTaskToResume; + + traceENTER_vTaskResume( xTaskToResume ); + + /* It does not make sense to resume the calling task. */ + configASSERT( xTaskToResume ); + + #if ( configNUMBER_OF_CORES == 1 ) + + /* The parameter cannot be NULL as it is impossible to resume the + * currently executing task. */ + if( ( pxTCB != pxCurrentTCB ) && ( pxTCB != NULL ) ) + #else + + /* The parameter cannot be NULL as it is impossible to resume the + * currently executing task. It is also impossible to resume a task + * that is actively running on another core but it is not safe + * to check their run state here. Therefore, we get into a critical + * section and check if the task is actually suspended or not. */ + if( pxTCB != NULL ) + #endif + { + taskENTER_CRITICAL(); + { + if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE ) + { + traceTASK_RESUME( pxTCB ); + + /* The ready list can be accessed even if the scheduler is + * suspended because this is inside a critical section. */ + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + prvAddTaskToReadyList( pxTCB ); + + /* This yield may not cause the task just resumed to run, + * but will leave the lists in the correct state for the + * next yield. */ + taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxTCB ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceRETURN_vTaskResume(); + } + +#endif /* INCLUDE_vTaskSuspend */ + +/*-----------------------------------------------------------*/ + +#if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) + + BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume ) + { + BaseType_t xYieldRequired = pdFALSE; + TCB_t * const pxTCB = xTaskToResume; + UBaseType_t uxSavedInterruptStatus; + + traceENTER_xTaskResumeFromISR( xTaskToResume ); + + configASSERT( xTaskToResume ); + + /* RTOS ports that support interrupt nesting have the concept of a + * maximum system call (or maximum API call) interrupt priority. + * Interrupts that are above the maximum system call priority are keep + * permanently enabled, even when the RTOS kernel is in a critical section, + * but cannot make any calls to FreeRTOS API functions. If configASSERT() + * is defined in FreeRTOSConfig.h then + * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has + * been assigned a priority above the configured maximum system call + * priority. Only FreeRTOS functions that end in FromISR can be called + * from interrupts that have been assigned a priority at or (logically) + * below the maximum system call interrupt priority. FreeRTOS maintains a + * separate interrupt safe API to ensure interrupt entry is as fast and as + * simple as possible. More information (albeit Cortex-M specific) is + * provided on the following link: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + /* MISRA Ref 4.7.1 [Return value shall be checked] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */ + /* coverity[misra_c_2012_directive_4_7_violation] */ + uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR(); + { + if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE ) + { + traceTASK_RESUME_FROM_ISR( pxTCB ); + + /* Check the ready lists can be accessed. */ + if( uxSchedulerSuspended == ( UBaseType_t ) 0U ) + { + #if ( configNUMBER_OF_CORES == 1 ) + { + /* Ready lists can be accessed so move the task from the + * suspended list to the ready list directly. */ + if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) + { + xYieldRequired = pdTRUE; + + /* Mark that a yield is pending in case the user is not + * using the return value to initiate a context switch + * from the ISR using the port specific portYIELD_FROM_ISR(). */ + xYieldPendings[ 0 ] = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ + + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + prvAddTaskToReadyList( pxTCB ); + } + else + { + /* The delayed or ready lists cannot be accessed so the task + * is held in the pending ready list until the scheduler is + * unsuspended. */ + vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) ); + } + + #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_PREEMPTION == 1 ) ) + { + prvYieldForTask( pxTCB ); + + if( xYieldPendings[ portGET_CORE_ID() ] != pdFALSE ) + { + xYieldRequired = pdTRUE; + } + } + #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_PREEMPTION == 1 ) ) */ + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + + traceRETURN_xTaskResumeFromISR( xYieldRequired ); + + return xYieldRequired; + } + +#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */ +/*-----------------------------------------------------------*/ + +static BaseType_t prvCreateIdleTasks( void ) +{ + BaseType_t xReturn = pdPASS; + BaseType_t xCoreID; + char cIdleName[ configMAX_TASK_NAME_LEN ] = { 0 }; + TaskFunction_t pxIdleTaskFunction = NULL; + UBaseType_t xIdleTaskNameIndex; + + /* MISRA Ref 14.3.1 [Configuration dependent invariant] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-143. */ + /* coverity[misra_c_2012_rule_14_3_violation] */ + for( xIdleTaskNameIndex = 0U; xIdleTaskNameIndex < ( configMAX_TASK_NAME_LEN - taskRESERVED_TASK_NAME_LENGTH ); xIdleTaskNameIndex++ ) + { + /* MISRA Ref 18.1.1 [Configuration dependent bounds checking] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-181. */ + /* coverity[misra_c_2012_rule_18_1_violation] */ + cIdleName[ xIdleTaskNameIndex ] = configIDLE_TASK_NAME[ xIdleTaskNameIndex ]; + + if( cIdleName[ xIdleTaskNameIndex ] == ( char ) 0x00 ) + { + break; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + /* Ensure null termination. */ + cIdleName[ xIdleTaskNameIndex ] = '\0'; + + /* Add each idle task at the lowest priority. */ + for( xCoreID = ( BaseType_t ) 0; xCoreID < ( BaseType_t ) configNUMBER_OF_CORES; xCoreID++ ) + { + #if ( configNUMBER_OF_CORES == 1 ) + { + pxIdleTaskFunction = &prvIdleTask; + } + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + { + /* In the FreeRTOS SMP, configNUMBER_OF_CORES - 1 passive idle tasks + * are also created to ensure that each core has an idle task to + * run when no other task is available to run. */ + if( xCoreID == 0 ) + { + pxIdleTaskFunction = &prvIdleTask; + } + else + { + pxIdleTaskFunction = &prvPassiveIdleTask; + } + } + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ + + /* Update the idle task name with suffix to differentiate the idle tasks. + * This function is not required in single core FreeRTOS since there is + * only one idle task. */ + #if ( configNUMBER_OF_CORES > 1 ) + { + /* Append the idle task number to the end of the name. + * + * Note: Idle task name index only supports single-character + * core IDs (0-9). If the core ID exceeds 9, the idle task + * name will contain an incorrect ASCII character. This is + * acceptable as the task name is used mainly for debugging. */ + cIdleName[ xIdleTaskNameIndex ] = ( char ) ( xCoreID + '0' ); + cIdleName[ xIdleTaskNameIndex + 1U ] = '\0'; + } + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + StaticTask_t * pxIdleTaskTCBBuffer = NULL; + StackType_t * pxIdleTaskStackBuffer = NULL; + configSTACK_DEPTH_TYPE uxIdleTaskStackSize; + + /* The Idle task is created using user provided RAM - obtain the + * address of the RAM then create the idle task. */ + #if ( configNUMBER_OF_CORES == 1 ) + { + vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &uxIdleTaskStackSize ); + } + #else + { + if( xCoreID == 0 ) + { + vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &uxIdleTaskStackSize ); + } + else + { + vApplicationGetPassiveIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &uxIdleTaskStackSize, ( BaseType_t ) ( xCoreID - 1 ) ); + } + } + #endif /* if ( configNUMBER_OF_CORES == 1 ) */ + xIdleTaskHandles[ xCoreID ] = xTaskCreateStatic( pxIdleTaskFunction, + cIdleName, + uxIdleTaskStackSize, + ( void * ) NULL, + portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */ + pxIdleTaskStackBuffer, + pxIdleTaskTCBBuffer ); + + if( xIdleTaskHandles[ xCoreID ] != NULL ) + { + xReturn = pdPASS; + } + else + { + xReturn = pdFAIL; + } + } + #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ + { + /* The Idle task is being created using dynamically allocated RAM. */ + xReturn = xTaskCreate( pxIdleTaskFunction, + cIdleName, + configMINIMAL_STACK_SIZE, + ( void * ) NULL, + portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */ + &xIdleTaskHandles[ xCoreID ] ); + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ + + /* Break the loop if any of the idle task is failed to be created. */ + if( xReturn != pdPASS ) + { + break; + } + else + { + #if ( configNUMBER_OF_CORES == 1 ) + { + mtCOVERAGE_TEST_MARKER(); + } + #else + { + /* Assign idle task to each core before SMP scheduler is running. */ + xIdleTaskHandles[ xCoreID ]->xTaskRunState = xCoreID; + pxCurrentTCBs[ xCoreID ] = xIdleTaskHandles[ xCoreID ]; + } + #endif + } + } + + return xReturn; +} + +/*-----------------------------------------------------------*/ + +void vTaskStartScheduler( void ) +{ + BaseType_t xReturn; + + traceENTER_vTaskStartScheduler(); + + #if ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) + { + /* Sanity check that the UBaseType_t must have greater than or equal to + * the number of bits as confNUMBER_OF_CORES. */ + configASSERT( ( sizeof( UBaseType_t ) * taskBITS_PER_BYTE ) >= configNUMBER_OF_CORES ); + } + #endif /* #if ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) */ + + xReturn = prvCreateIdleTasks(); + + #if ( configUSE_TIMERS == 1 ) + { + if( xReturn == pdPASS ) + { + xReturn = xTimerCreateTimerTask(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_TIMERS */ + + if( xReturn == pdPASS ) + { + /* freertos_tasks_c_additions_init() should only be called if the user + * definable macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is + * the only macro called by the function. */ + #ifdef FREERTOS_TASKS_C_ADDITIONS_INIT + { + freertos_tasks_c_additions_init(); + } + #endif + + /* Interrupts are turned off here, to ensure a tick does not occur + * before or during the call to xPortStartScheduler(). The stacks of + * the created tasks contain a status word with interrupts switched on + * so interrupts will automatically get re-enabled when the first task + * starts to run. */ + portDISABLE_INTERRUPTS(); + + #if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) + { + /* Switch C-Runtime's TLS Block to point to the TLS + * block specific to the task that will run first. */ + configSET_TLS_BLOCK( pxCurrentTCB->xTLSBlock ); + } + #endif + + xNextTaskUnblockTime = portMAX_DELAY; + xSchedulerRunning = pdTRUE; + xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT; + + /* If configGENERATE_RUN_TIME_STATS is defined then the following + * macro must be defined to configure the timer/counter used to generate + * the run time counter time base. NOTE: If configGENERATE_RUN_TIME_STATS + * is set to 0 and the following line fails to build then ensure you do not + * have portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() defined in your + * FreeRTOSConfig.h file. */ + portCONFIGURE_TIMER_FOR_RUN_TIME_STATS(); + + traceTASK_SWITCHED_IN(); + + traceSTARTING_SCHEDULER( xIdleTaskHandles ); + + /* Setting up the timer tick is hardware specific and thus in the + * portable interface. */ + + /* The return value for xPortStartScheduler is not required + * hence using a void datatype. */ + ( void ) xPortStartScheduler(); + + /* In most cases, xPortStartScheduler() will not return. If it + * returns pdTRUE then there was not enough heap memory available + * to create either the Idle or the Timer task. If it returned + * pdFALSE, then the application called xTaskEndScheduler(). + * Most ports don't implement xTaskEndScheduler() as there is + * nothing to return to. */ + } + else + { + /* This line will only be reached if the kernel could not be started, + * because there was not enough FreeRTOS heap to create the idle task + * or the timer task. */ + configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ); + } + + /* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0, + * meaning xIdleTaskHandles are not used anywhere else. */ + ( void ) xIdleTaskHandles; + + /* OpenOCD makes use of uxTopUsedPriority for thread debugging. Prevent uxTopUsedPriority + * from getting optimized out as it is no longer used by the kernel. */ + ( void ) uxTopUsedPriority; + + traceRETURN_vTaskStartScheduler(); +} +/*-----------------------------------------------------------*/ + +void vTaskEndScheduler( void ) +{ + traceENTER_vTaskEndScheduler(); + + #if ( INCLUDE_vTaskDelete == 1 ) + { + BaseType_t xCoreID; + + #if ( configUSE_TIMERS == 1 ) + { + /* Delete the timer task created by the kernel. */ + vTaskDelete( xTimerGetTimerDaemonTaskHandle() ); + } + #endif /* #if ( configUSE_TIMERS == 1 ) */ + + /* Delete Idle tasks created by the kernel.*/ + for( xCoreID = 0; xCoreID < ( BaseType_t ) configNUMBER_OF_CORES; xCoreID++ ) + { + vTaskDelete( xIdleTaskHandles[ xCoreID ] ); + } + + /* Idle task is responsible for reclaiming the resources of the tasks in + * xTasksWaitingTermination list. Since the idle task is now deleted and + * no longer going to run, we need to reclaim resources of all the tasks + * in the xTasksWaitingTermination list. */ + prvCheckTasksWaitingTermination(); + } + #endif /* #if ( INCLUDE_vTaskDelete == 1 ) */ + + /* Stop the scheduler interrupts and call the portable scheduler end + * routine so the original ISRs can be restored if necessary. The port + * layer must ensure interrupts enable bit is left in the correct state. */ + portDISABLE_INTERRUPTS(); + xSchedulerRunning = pdFALSE; + + /* This function must be called from a task and the application is + * responsible for deleting that task after the scheduler is stopped. */ + vPortEndScheduler(); + + traceRETURN_vTaskEndScheduler(); +} +/*----------------------------------------------------------*/ + +void vTaskSuspendAll( void ) +{ + traceENTER_vTaskSuspendAll(); + + #if ( configNUMBER_OF_CORES == 1 ) + { + /* A critical section is not required as the variable is of type + * BaseType_t. Each task maintains its own context, and a context switch + * cannot occur if the variable is non zero. So, as long as the writing + * from the register back into the memory is atomic, it is not a + * problem. + * + * Consider the following scenario, which starts with + * uxSchedulerSuspended at zero. + * + * 1. load uxSchedulerSuspended into register. + * 2. Now a context switch causes another task to run, and the other + * task uses the same variable. The other task will see the variable + * as zero because the variable has not yet been updated by the + * original task. Eventually the original task runs again. **That can + * only happen when uxSchedulerSuspended is once again zero**. When + * the original task runs again, the contents of the CPU registers + * are restored to exactly how they were when it was switched out - + * therefore the value it read into the register still matches the + * value of the uxSchedulerSuspended variable. + * + * 3. increment register. + * 4. store register into uxSchedulerSuspended. The value restored to + * uxSchedulerSuspended will be the correct value of 1, even though + * the variable was used by other tasks in the mean time. + */ + + /* portSOFTWARE_BARRIER() is only implemented for emulated/simulated ports that + * do not otherwise exhibit real time behaviour. */ + portSOFTWARE_BARRIER(); + + /* The scheduler is suspended if uxSchedulerSuspended is non-zero. An increment + * is used to allow calls to vTaskSuspendAll() to nest. */ + uxSchedulerSuspended = ( UBaseType_t ) ( uxSchedulerSuspended + 1U ); + + /* Enforces ordering for ports and optimised compilers that may otherwise place + * the above increment elsewhere. */ + portMEMORY_BARRIER(); + } + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + { + UBaseType_t ulState; + BaseType_t xCoreID; + + /* This must only be called from within a task. */ + portASSERT_IF_IN_ISR(); + + if( xSchedulerRunning != pdFALSE ) + { + /* Writes to uxSchedulerSuspended must be protected by both the task AND ISR locks. + * We must disable interrupts before we grab the locks in the event that this task is + * interrupted and switches context before incrementing uxSchedulerSuspended. + * It is safe to re-enable interrupts after releasing the ISR lock and incrementing + * uxSchedulerSuspended since that will prevent context switches. */ + ulState = portSET_INTERRUPT_MASK(); + + xCoreID = ( BaseType_t ) portGET_CORE_ID(); + + /* This must never be called from inside a critical section. */ + configASSERT( portGET_CRITICAL_NESTING_COUNT( xCoreID ) == 0 ); + + /* portSOFTWARE_BARRIER() is only implemented for emulated/simulated ports that + * do not otherwise exhibit real time behaviour. */ + portSOFTWARE_BARRIER(); + + portGET_TASK_LOCK( xCoreID ); + + /* uxSchedulerSuspended is increased after prvCheckForRunStateChange. The + * purpose is to prevent altering the variable when fromISR APIs are readying + * it. */ + if( uxSchedulerSuspended == 0U ) + { + prvCheckForRunStateChange(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Query the coreID again as prvCheckForRunStateChange may have + * caused the task to get scheduled on a different core. The correct + * task lock for the core is acquired in prvCheckForRunStateChange. */ + xCoreID = ( BaseType_t ) portGET_CORE_ID(); + + portGET_ISR_LOCK( xCoreID ); + + /* The scheduler is suspended if uxSchedulerSuspended is non-zero. An increment + * is used to allow calls to vTaskSuspendAll() to nest. */ + ++uxSchedulerSuspended; + portRELEASE_ISR_LOCK( xCoreID ); + + portCLEAR_INTERRUPT_MASK( ulState ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ + + traceRETURN_vTaskSuspendAll(); +} + +/*----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE != 0 ) + + static TickType_t prvGetExpectedIdleTime( void ) + { + TickType_t xReturn; + BaseType_t xHigherPriorityReadyTasks = pdFALSE; + + /* xHigherPriorityReadyTasks takes care of the case where + * configUSE_PREEMPTION is 0, so there may be tasks above the idle priority + * task that are in the Ready state, even though the idle task is + * running. */ + #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 ) + { + if( uxTopReadyPriority > tskIDLE_PRIORITY ) + { + xHigherPriorityReadyTasks = pdTRUE; + } + } + #else + { + const UBaseType_t uxLeastSignificantBit = ( UBaseType_t ) 0x01; + + /* When port optimised task selection is used the uxTopReadyPriority + * variable is used as a bit map. If bits other than the least + * significant bit are set then there are tasks that have a priority + * above the idle priority that are in the Ready state. This takes + * care of the case where the co-operative scheduler is in use. */ + if( uxTopReadyPriority > uxLeastSignificantBit ) + { + xHigherPriorityReadyTasks = pdTRUE; + } + } + #endif /* if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 ) */ + + if( pxCurrentTCB->uxPriority > tskIDLE_PRIORITY ) + { + xReturn = 0; + } + else if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > 1U ) + { + /* There are other idle priority tasks in the ready state. If + * time slicing is used then the very next tick interrupt must be + * processed. */ + xReturn = 0; + } + else if( xHigherPriorityReadyTasks != pdFALSE ) + { + /* There are tasks in the Ready state that have a priority above the + * idle priority. This path can only be reached if + * configUSE_PREEMPTION is 0. */ + xReturn = 0; + } + else + { + xReturn = xNextTaskUnblockTime; + xReturn -= xTickCount; + } + + return xReturn; + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*----------------------------------------------------------*/ + +BaseType_t xTaskResumeAll( void ) +{ + TCB_t * pxTCB = NULL; + BaseType_t xAlreadyYielded = pdFALSE; + + traceENTER_xTaskResumeAll(); + + #if ( configNUMBER_OF_CORES > 1 ) + if( xSchedulerRunning != pdFALSE ) + #endif + { + /* It is possible that an ISR caused a task to be removed from an event + * list while the scheduler was suspended. If this was the case then the + * removed task will have been added to the xPendingReadyList. Once the + * scheduler has been resumed it is safe to move all the pending ready + * tasks from this list into their appropriate ready list. */ + taskENTER_CRITICAL(); + { + const BaseType_t xCoreID = ( BaseType_t ) portGET_CORE_ID(); + + /* If uxSchedulerSuspended is zero then this function does not match a + * previous call to vTaskSuspendAll(). */ + configASSERT( uxSchedulerSuspended != 0U ); + + uxSchedulerSuspended = ( UBaseType_t ) ( uxSchedulerSuspended - 1U ); + portRELEASE_TASK_LOCK( xCoreID ); + + if( uxSchedulerSuspended == ( UBaseType_t ) 0U ) + { + if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U ) + { + /* Move any readied tasks from the pending list into the + * appropriate ready list. */ + while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) + { + /* MISRA Ref 11.5.3 [Void pointer assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); + listREMOVE_ITEM( &( pxTCB->xEventListItem ) ); + portMEMORY_BARRIER(); + listREMOVE_ITEM( &( pxTCB->xStateListItem ) ); + prvAddTaskToReadyList( pxTCB ); + + #if ( configNUMBER_OF_CORES == 1 ) + { + /* If the moved task has a priority higher than the current + * task then a yield must be performed. */ + if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) + { + xYieldPendings[ xCoreID ] = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + { + /* All appropriate tasks yield at the moment a task is added to xPendingReadyList. + * If the current core yielded then vTaskSwitchContext() has already been called + * which sets xYieldPendings for the current core to pdTRUE. */ + } + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ + } + + if( pxTCB != NULL ) + { + /* A task was unblocked while the scheduler was suspended, + * which may have prevented the next unblock time from being + * re-calculated, in which case re-calculate it now. Mainly + * important for low power tickless implementations, where + * this can prevent an unnecessary exit from low power + * state. */ + prvResetNextTaskUnblockTime(); + } + + /* If any ticks occurred while the scheduler was suspended then + * they should be processed now. This ensures the tick count does + * not slip, and that any delayed tasks are resumed at the correct + * time. + * + * It should be safe to call xTaskIncrementTick here from any core + * since we are in a critical section and xTaskIncrementTick itself + * protects itself within a critical section. Suspending the scheduler + * from any core causes xTaskIncrementTick to increment uxPendedCounts. */ + { + TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */ + + if( xPendedCounts > ( TickType_t ) 0U ) + { + do + { + if( xTaskIncrementTick() != pdFALSE ) + { + /* Other cores are interrupted from + * within xTaskIncrementTick(). */ + xYieldPendings[ xCoreID ] = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + --xPendedCounts; + } while( xPendedCounts > ( TickType_t ) 0U ); + + xPendedTicks = 0; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + if( xYieldPendings[ xCoreID ] != pdFALSE ) + { + #if ( configUSE_PREEMPTION != 0 ) + { + xAlreadyYielded = pdTRUE; + } + #endif /* #if ( configUSE_PREEMPTION != 0 ) */ + + #if ( configNUMBER_OF_CORES == 1 ) + { + taskYIELD_TASK_CORE_IF_USING_PREEMPTION( pxCurrentTCB ); + } + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + } + + traceRETURN_xTaskResumeAll( xAlreadyYielded ); + + return xAlreadyYielded; +} +/*-----------------------------------------------------------*/ + +TickType_t xTaskGetTickCount( void ) +{ + TickType_t xTicks; + + traceENTER_xTaskGetTickCount(); + + /* Critical section required if running on a 16 bit processor. */ + portTICK_TYPE_ENTER_CRITICAL(); + { + xTicks = xTickCount; + } + portTICK_TYPE_EXIT_CRITICAL(); + + traceRETURN_xTaskGetTickCount( xTicks ); + + return xTicks; +} +/*-----------------------------------------------------------*/ + +TickType_t xTaskGetTickCountFromISR( void ) +{ + TickType_t xReturn; + UBaseType_t uxSavedInterruptStatus; + + traceENTER_xTaskGetTickCountFromISR(); + + /* RTOS ports that support interrupt nesting have the concept of a maximum + * system call (or maximum API call) interrupt priority. Interrupts that are + * above the maximum system call priority are kept permanently enabled, even + * when the RTOS kernel is in a critical section, but cannot make any calls to + * FreeRTOS API functions. If configASSERT() is defined in FreeRTOSConfig.h + * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has been + * assigned a priority above the configured maximum system call priority. + * Only FreeRTOS functions that end in FromISR can be called from interrupts + * that have been assigned a priority at or (logically) below the maximum + * system call interrupt priority. FreeRTOS maintains a separate interrupt + * safe API to ensure interrupt entry is as fast and as simple as possible. + * More information (albeit Cortex-M specific) is provided on the following + * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + uxSavedInterruptStatus = portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR(); + { + xReturn = xTickCount; + } + portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + traceRETURN_xTaskGetTickCountFromISR( xReturn ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +UBaseType_t uxTaskGetNumberOfTasks( void ) +{ + traceENTER_uxTaskGetNumberOfTasks(); + + /* A critical section is not required because the variables are of type + * BaseType_t. */ + traceRETURN_uxTaskGetNumberOfTasks( uxCurrentNumberOfTasks ); + + return uxCurrentNumberOfTasks; +} +/*-----------------------------------------------------------*/ + +char * pcTaskGetName( TaskHandle_t xTaskToQuery ) +{ + TCB_t * pxTCB; + + traceENTER_pcTaskGetName( xTaskToQuery ); + + /* If null is passed in here then the name of the calling task is being + * queried. */ + pxTCB = prvGetTCBFromHandle( xTaskToQuery ); + configASSERT( pxTCB != NULL ); + + traceRETURN_pcTaskGetName( &( pxTCB->pcTaskName[ 0 ] ) ); + + return &( pxTCB->pcTaskName[ 0 ] ); +} +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_xTaskGetHandle == 1 ) + static TCB_t * prvSearchForNameWithinSingleList( List_t * pxList, + const char pcNameToQuery[] ) + { + TCB_t * pxReturn = NULL; + TCB_t * pxTCB = NULL; + UBaseType_t x; + char cNextChar; + BaseType_t xBreakLoop; + const ListItem_t * pxEndMarker = listGET_END_MARKER( pxList ); + ListItem_t * pxIterator; + + /* This function is called with the scheduler suspended. */ + + if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 ) + { + for( pxIterator = listGET_HEAD_ENTRY( pxList ); pxIterator != pxEndMarker; pxIterator = listGET_NEXT( pxIterator ) ) + { + /* MISRA Ref 11.5.3 [Void pointer assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + pxTCB = listGET_LIST_ITEM_OWNER( pxIterator ); + + /* Check each character in the name looking for a match or + * mismatch. */ + xBreakLoop = pdFALSE; + + for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) + { + cNextChar = pxTCB->pcTaskName[ x ]; + + if( cNextChar != pcNameToQuery[ x ] ) + { + /* Characters didn't match. */ + xBreakLoop = pdTRUE; + } + else if( cNextChar == ( char ) 0x00 ) + { + /* Both strings terminated, a match must have been + * found. */ + pxReturn = pxTCB; + xBreakLoop = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xBreakLoop != pdFALSE ) + { + break; + } + } + + if( pxReturn != NULL ) + { + /* The handle has been found. */ + break; + } + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return pxReturn; + } + +#endif /* INCLUDE_xTaskGetHandle */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_xTaskGetHandle == 1 ) + + TaskHandle_t xTaskGetHandle( const char * pcNameToQuery ) + { + UBaseType_t uxQueue = configMAX_PRIORITIES; + TCB_t * pxTCB; + + traceENTER_xTaskGetHandle( pcNameToQuery ); + + /* Task names will be truncated to configMAX_TASK_NAME_LEN - 1 bytes. */ + configASSERT( strlen( pcNameToQuery ) < configMAX_TASK_NAME_LEN ); + + vTaskSuspendAll(); + { + /* Search the ready lists. */ + do + { + uxQueue--; + pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) &( pxReadyTasksLists[ uxQueue ] ), pcNameToQuery ); + + if( pxTCB != NULL ) + { + /* Found the handle. */ + break; + } + } while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); + + /* Search the delayed lists. */ + if( pxTCB == NULL ) + { + pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxDelayedTaskList, pcNameToQuery ); + } + + if( pxTCB == NULL ) + { + pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxOverflowDelayedTaskList, pcNameToQuery ); + } + + #if ( INCLUDE_vTaskSuspend == 1 ) + { + if( pxTCB == NULL ) + { + /* Search the suspended list. */ + pxTCB = prvSearchForNameWithinSingleList( &xSuspendedTaskList, pcNameToQuery ); + } + } + #endif + + #if ( INCLUDE_vTaskDelete == 1 ) + { + if( pxTCB == NULL ) + { + /* Search the deleted list. */ + pxTCB = prvSearchForNameWithinSingleList( &xTasksWaitingTermination, pcNameToQuery ); + } + } + #endif + } + ( void ) xTaskResumeAll(); + + traceRETURN_xTaskGetHandle( pxTCB ); + + return pxTCB; + } + +#endif /* INCLUDE_xTaskGetHandle */ +/*-----------------------------------------------------------*/ + +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + + BaseType_t xTaskGetStaticBuffers( TaskHandle_t xTask, + StackType_t ** ppuxStackBuffer, + StaticTask_t ** ppxTaskBuffer ) + { + BaseType_t xReturn; + TCB_t * pxTCB; + + traceENTER_xTaskGetStaticBuffers( xTask, ppuxStackBuffer, ppxTaskBuffer ); + + configASSERT( ppuxStackBuffer != NULL ); + configASSERT( ppxTaskBuffer != NULL ); + + pxTCB = prvGetTCBFromHandle( xTask ); + configASSERT( pxTCB != NULL ); + + #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE == 1 ) + { + if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB ) + { + *ppuxStackBuffer = pxTCB->pxStack; + /* MISRA Ref 11.3.1 [Misaligned access] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */ + /* coverity[misra_c_2012_rule_11_3_violation] */ + *ppxTaskBuffer = ( StaticTask_t * ) pxTCB; + xReturn = pdTRUE; + } + else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY ) + { + *ppuxStackBuffer = pxTCB->pxStack; + *ppxTaskBuffer = NULL; + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + } + #else /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE == 1 */ + { + *ppuxStackBuffer = pxTCB->pxStack; + *ppxTaskBuffer = ( StaticTask_t * ) pxTCB; + xReturn = pdTRUE; + } + #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE == 1 */ + + traceRETURN_xTaskGetStaticBuffers( xReturn ); + + return xReturn; + } + +#endif /* configSUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) + { + UBaseType_t uxTask = 0, uxQueue = configMAX_PRIORITIES; + + traceENTER_uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, pulTotalRunTime ); + + vTaskSuspendAll(); + { + /* Is there a space in the array for each task in the system? */ + if( uxArraySize >= uxCurrentNumberOfTasks ) + { + /* Fill in an TaskStatus_t structure with information on each + * task in the Ready state. */ + do + { + uxQueue--; + uxTask = ( UBaseType_t ) ( uxTask + prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &( pxReadyTasksLists[ uxQueue ] ), eReady ) ); + } while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); + + /* Fill in an TaskStatus_t structure with information on each + * task in the Blocked state. */ + uxTask = ( UBaseType_t ) ( uxTask + prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxDelayedTaskList, eBlocked ) ); + uxTask = ( UBaseType_t ) ( uxTask + prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxOverflowDelayedTaskList, eBlocked ) ); + + #if ( INCLUDE_vTaskDelete == 1 ) + { + /* Fill in an TaskStatus_t structure with information on + * each task that has been deleted but not yet cleaned up. */ + uxTask = ( UBaseType_t ) ( uxTask + prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xTasksWaitingTermination, eDeleted ) ); + } + #endif + + #if ( INCLUDE_vTaskSuspend == 1 ) + { + /* Fill in an TaskStatus_t structure with information on + * each task in the Suspended state. */ + uxTask = ( UBaseType_t ) ( uxTask + prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xSuspendedTaskList, eSuspended ) ); + } + #endif + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + { + if( pulTotalRunTime != NULL ) + { + #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE + portALT_GET_RUN_TIME_COUNTER_VALUE( ( *pulTotalRunTime ) ); + #else + *pulTotalRunTime = ( configRUN_TIME_COUNTER_TYPE ) portGET_RUN_TIME_COUNTER_VALUE(); + #endif + } + } + #else /* if ( configGENERATE_RUN_TIME_STATS == 1 ) */ + { + if( pulTotalRunTime != NULL ) + { + *pulTotalRunTime = 0; + } + } + #endif /* if ( configGENERATE_RUN_TIME_STATS == 1 ) */ + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + ( void ) xTaskResumeAll(); + + traceRETURN_uxTaskGetSystemState( uxTask ); + + return uxTask; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*----------------------------------------------------------*/ + +#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) + + #if ( configNUMBER_OF_CORES == 1 ) + TaskHandle_t xTaskGetIdleTaskHandle( void ) + { + traceENTER_xTaskGetIdleTaskHandle(); + + /* If xTaskGetIdleTaskHandle() is called before the scheduler has been + * started, then xIdleTaskHandles will be NULL. */ + configASSERT( ( xIdleTaskHandles[ 0 ] != NULL ) ); + + traceRETURN_xTaskGetIdleTaskHandle( xIdleTaskHandles[ 0 ] ); + + return xIdleTaskHandles[ 0 ]; + } + #endif /* if ( configNUMBER_OF_CORES == 1 ) */ + + TaskHandle_t xTaskGetIdleTaskHandleForCore( BaseType_t xCoreID ) + { + traceENTER_xTaskGetIdleTaskHandleForCore( xCoreID ); + + /* Ensure the core ID is valid. */ + configASSERT( taskVALID_CORE_ID( xCoreID ) == pdTRUE ); + + /* If xTaskGetIdleTaskHandle() is called before the scheduler has been + * started, then xIdleTaskHandles will be NULL. */ + configASSERT( ( xIdleTaskHandles[ xCoreID ] != NULL ) ); + + traceRETURN_xTaskGetIdleTaskHandleForCore( xIdleTaskHandles[ xCoreID ] ); + + return xIdleTaskHandles[ xCoreID ]; + } + +#endif /* INCLUDE_xTaskGetIdleTaskHandle */ +/*----------------------------------------------------------*/ + +/* This conditional compilation should use inequality to 0, not equality to 1. + * This is to ensure vTaskStepTick() is available when user defined low power mode + * implementations require configUSE_TICKLESS_IDLE to be set to a value other than + * 1. */ +#if ( configUSE_TICKLESS_IDLE != 0 ) + + void vTaskStepTick( TickType_t xTicksToJump ) + { + TickType_t xUpdatedTickCount; + + traceENTER_vTaskStepTick( xTicksToJump ); + + /* Correct the tick count value after a period during which the tick + * was suppressed. Note this does *not* call the tick hook function for + * each stepped tick. */ + xUpdatedTickCount = xTickCount + xTicksToJump; + configASSERT( xUpdatedTickCount <= xNextTaskUnblockTime ); + + if( xUpdatedTickCount == xNextTaskUnblockTime ) + { + /* Arrange for xTickCount to reach xNextTaskUnblockTime in + * xTaskIncrementTick() when the scheduler resumes. This ensures + * that any delayed tasks are resumed at the correct time. */ + configASSERT( uxSchedulerSuspended != ( UBaseType_t ) 0U ); + configASSERT( xTicksToJump != ( TickType_t ) 0 ); + + /* Prevent the tick interrupt modifying xPendedTicks simultaneously. */ + taskENTER_CRITICAL(); + { + xPendedTicks++; + } + taskEXIT_CRITICAL(); + xTicksToJump--; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xTickCount += xTicksToJump; + + traceINCREASE_TICK_COUNT( xTicksToJump ); + traceRETURN_vTaskStepTick(); + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*----------------------------------------------------------*/ + +BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) +{ + BaseType_t xYieldOccurred; + + traceENTER_xTaskCatchUpTicks( xTicksToCatchUp ); + + /* Must not be called with the scheduler suspended as the implementation + * relies on xPendedTicks being wound down to 0 in xTaskResumeAll(). */ + configASSERT( uxSchedulerSuspended == ( UBaseType_t ) 0U ); + + /* Use xPendedTicks to mimic xTicksToCatchUp number of ticks occurring when + * the scheduler is suspended so the ticks are executed in xTaskResumeAll(). */ + vTaskSuspendAll(); + + /* Prevent the tick interrupt modifying xPendedTicks simultaneously. */ + taskENTER_CRITICAL(); + { + xPendedTicks += xTicksToCatchUp; + } + taskEXIT_CRITICAL(); + xYieldOccurred = xTaskResumeAll(); + + traceRETURN_xTaskCatchUpTicks( xYieldOccurred ); + + return xYieldOccurred; +} +/*----------------------------------------------------------*/ + +#if ( INCLUDE_xTaskAbortDelay == 1 ) + + BaseType_t xTaskAbortDelay( TaskHandle_t xTask ) + { + TCB_t * pxTCB = xTask; + BaseType_t xReturn; + + traceENTER_xTaskAbortDelay( xTask ); + + configASSERT( pxTCB != NULL ); + + vTaskSuspendAll(); + { + /* A task can only be prematurely removed from the Blocked state if + * it is actually in the Blocked state. */ + if( eTaskGetState( xTask ) == eBlocked ) + { + xReturn = pdPASS; + + /* Remove the reference to the task from the blocked list. An + * interrupt won't touch the xStateListItem because the + * scheduler is suspended. */ + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + + /* Is the task waiting on an event also? If so remove it from + * the event list too. Interrupts can touch the event list item, + * even though the scheduler is suspended, so a critical section + * is used. */ + taskENTER_CRITICAL(); + { + if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) + { + ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); + + /* This lets the task know it was forcibly removed from the + * blocked state so it should not re-evaluate its block time and + * then block again. */ + pxTCB->ucDelayAborted = ( uint8_t ) pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + + /* Place the unblocked task into the appropriate ready list. */ + prvAddTaskToReadyList( pxTCB ); + + /* A task being unblocked cannot cause an immediate context + * switch if preemption is turned off. */ + #if ( configUSE_PREEMPTION == 1 ) + { + #if ( configNUMBER_OF_CORES == 1 ) + { + /* Preemption is on, but a context switch should only be + * performed if the unblocked task has a priority that is + * higher than the currently executing task. */ + if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) + { + /* Pend the yield to be performed when the scheduler + * is unsuspended. */ + xYieldPendings[ 0 ] = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + { + taskENTER_CRITICAL(); + { + prvYieldForTask( pxTCB ); + } + taskEXIT_CRITICAL(); + } + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ + } + #endif /* #if ( configUSE_PREEMPTION == 1 ) */ + } + else + { + xReturn = pdFAIL; + } + } + ( void ) xTaskResumeAll(); + + traceRETURN_xTaskAbortDelay( xReturn ); + + return xReturn; + } + +#endif /* INCLUDE_xTaskAbortDelay */ +/*----------------------------------------------------------*/ + +BaseType_t xTaskIncrementTick( void ) +{ + TCB_t * pxTCB; + TickType_t xItemValue; + BaseType_t xSwitchRequired = pdFALSE; + + traceENTER_xTaskIncrementTick(); + + /* Called by the portable layer each time a tick interrupt occurs. + * Increments the tick then checks to see if the new tick value will cause any + * tasks to be unblocked. */ + traceTASK_INCREMENT_TICK( xTickCount ); + + /* Tick increment should occur on every kernel timer event. Core 0 has the + * responsibility to increment the tick, or increment the pended ticks if the + * scheduler is suspended. If pended ticks is greater than zero, the core that + * calls xTaskResumeAll has the responsibility to increment the tick. */ + if( uxSchedulerSuspended == ( UBaseType_t ) 0U ) + { + /* Minor optimisation. The tick count cannot change in this + * block. */ + const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1; + + /* Increment the RTOS tick, switching the delayed and overflowed + * delayed lists if it wraps to 0. */ + xTickCount = xConstTickCount; + + if( xConstTickCount == ( TickType_t ) 0U ) + { + taskSWITCH_DELAYED_LISTS(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* See if this tick has made a timeout expire. Tasks are stored in + * the queue in the order of their wake time - meaning once one task + * has been found whose block time has not expired there is no need to + * look any further down the list. */ + if( xConstTickCount >= xNextTaskUnblockTime ) + { + for( ; ; ) + { + if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) + { + /* The delayed list is empty. Set xNextTaskUnblockTime + * to the maximum possible value so it is extremely + * unlikely that the + * if( xTickCount >= xNextTaskUnblockTime ) test will pass + * next time through. */ + xNextTaskUnblockTime = portMAX_DELAY; + break; + } + else + { + /* The delayed list is not empty, get the value of the + * item at the head of the delayed list. This is the time + * at which the task at the head of the delayed list must + * be removed from the Blocked state. */ + /* MISRA Ref 11.5.3 [Void pointer assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); + xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) ); + + if( xConstTickCount < xItemValue ) + { + /* It is not time to unblock this item yet, but the + * item value is the time at which the task at the head + * of the blocked list must be removed from the Blocked + * state - so record the item value in + * xNextTaskUnblockTime. */ + xNextTaskUnblockTime = xItemValue; + break; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* It is time to remove the item from the Blocked state. */ + listREMOVE_ITEM( &( pxTCB->xStateListItem ) ); + + /* Is the task waiting on an event also? If so remove + * it from the event list. */ + if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) + { + listREMOVE_ITEM( &( pxTCB->xEventListItem ) ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Place the unblocked task into the appropriate ready + * list. */ + prvAddTaskToReadyList( pxTCB ); + + /* A task being unblocked cannot cause an immediate + * context switch if preemption is turned off. */ + #if ( configUSE_PREEMPTION == 1 ) + { + #if ( configNUMBER_OF_CORES == 1 ) + { + /* Preemption is on, but a context switch should + * only be performed if the unblocked task's + * priority is higher than the currently executing + * task. + * The case of equal priority tasks sharing + * processing time (which happens when both + * preemption and time slicing are on) is + * handled below.*/ + if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) + { + xSwitchRequired = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #else /* #if( configNUMBER_OF_CORES == 1 ) */ + { + prvYieldForTask( pxTCB ); + } + #endif /* #if( configNUMBER_OF_CORES == 1 ) */ + } + #endif /* #if ( configUSE_PREEMPTION == 1 ) */ + } + } + } + + /* Tasks of equal priority to the currently running task will share + * processing time (time slice) if preemption is on, and the application + * writer has not explicitly turned time slicing off. */ + #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) + { + #if ( configNUMBER_OF_CORES == 1 ) + { + if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > 1U ) + { + xSwitchRequired = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + { + BaseType_t xCoreID; + + for( xCoreID = 0; xCoreID < ( ( BaseType_t ) configNUMBER_OF_CORES ); xCoreID++ ) + { + if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCBs[ xCoreID ]->uxPriority ] ) ) > 1U ) + { + xYieldPendings[ xCoreID ] = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ + } + #endif /* #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) */ + + #if ( configUSE_TICK_HOOK == 1 ) + { + /* Guard against the tick hook being called when the pended tick + * count is being unwound (when the scheduler is being unlocked). */ + if( xPendedTicks == ( TickType_t ) 0 ) + { + vApplicationTickHook(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_TICK_HOOK */ + + #if ( configUSE_PREEMPTION == 1 ) + { + #if ( configNUMBER_OF_CORES == 1 ) + { + /* For single core the core ID is always 0. */ + if( xYieldPendings[ 0 ] != pdFALSE ) + { + xSwitchRequired = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + { + BaseType_t xCoreID, xCurrentCoreID; + xCurrentCoreID = ( BaseType_t ) portGET_CORE_ID(); + + for( xCoreID = 0; xCoreID < ( BaseType_t ) configNUMBER_OF_CORES; xCoreID++ ) + { + #if ( configUSE_TASK_PREEMPTION_DISABLE == 1 ) + if( pxCurrentTCBs[ xCoreID ]->xPreemptionDisable == pdFALSE ) + #endif + { + if( xYieldPendings[ xCoreID ] != pdFALSE ) + { + if( xCoreID == xCurrentCoreID ) + { + xSwitchRequired = pdTRUE; + } + else + { + prvYieldCore( xCoreID ); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + } + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ + } + #endif /* #if ( configUSE_PREEMPTION == 1 ) */ + } + else + { + xPendedTicks += 1U; + + /* The tick hook gets called at regular intervals, even if the + * scheduler is locked. */ + #if ( configUSE_TICK_HOOK == 1 ) + { + vApplicationTickHook(); + } + #endif + } + + traceRETURN_xTaskIncrementTick( xSwitchRequired ); + + return xSwitchRequired; +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + void vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) + { + TCB_t * xTCB; + + traceENTER_vTaskSetApplicationTaskTag( xTask, pxHookFunction ); + + /* If xTask is NULL then it is the task hook of the calling task that is + * getting set. */ + if( xTask == NULL ) + { + xTCB = ( TCB_t * ) pxCurrentTCB; + } + else + { + xTCB = xTask; + } + + /* Save the hook function in the TCB. A critical section is required as + * the value can be accessed from an interrupt. */ + taskENTER_CRITICAL(); + { + xTCB->pxTaskTag = pxHookFunction; + } + taskEXIT_CRITICAL(); + + traceRETURN_vTaskSetApplicationTaskTag(); + } + +#endif /* configUSE_APPLICATION_TASK_TAG */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask ) + { + TCB_t * pxTCB; + TaskHookFunction_t xReturn; + + traceENTER_xTaskGetApplicationTaskTag( xTask ); + + /* If xTask is NULL then set the calling task's hook. */ + pxTCB = prvGetTCBFromHandle( xTask ); + configASSERT( pxTCB != NULL ); + + /* Save the hook function in the TCB. A critical section is required as + * the value can be accessed from an interrupt. */ + taskENTER_CRITICAL(); + { + xReturn = pxTCB->pxTaskTag; + } + taskEXIT_CRITICAL(); + + traceRETURN_xTaskGetApplicationTaskTag( xReturn ); + + return xReturn; + } + +#endif /* configUSE_APPLICATION_TASK_TAG */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask ) + { + TCB_t * pxTCB; + TaskHookFunction_t xReturn; + UBaseType_t uxSavedInterruptStatus; + + traceENTER_xTaskGetApplicationTaskTagFromISR( xTask ); + + /* If xTask is NULL then set the calling task's hook. */ + pxTCB = prvGetTCBFromHandle( xTask ); + configASSERT( pxTCB != NULL ); + + /* Save the hook function in the TCB. A critical section is required as + * the value can be accessed from an interrupt. */ + /* MISRA Ref 4.7.1 [Return value shall be checked] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */ + /* coverity[misra_c_2012_directive_4_7_violation] */ + uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR(); + { + xReturn = pxTCB->pxTaskTag; + } + taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + + traceRETURN_xTaskGetApplicationTaskTagFromISR( xReturn ); + + return xReturn; + } + +#endif /* configUSE_APPLICATION_TASK_TAG */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_APPLICATION_TASK_TAG == 1 ) + + BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, + void * pvParameter ) + { + TCB_t * xTCB; + BaseType_t xReturn; + + traceENTER_xTaskCallApplicationTaskHook( xTask, pvParameter ); + + /* If xTask is NULL then we are calling our own task hook. */ + if( xTask == NULL ) + { + xTCB = pxCurrentTCB; + } + else + { + xTCB = xTask; + } + + if( xTCB->pxTaskTag != NULL ) + { + xReturn = xTCB->pxTaskTag( pvParameter ); + } + else + { + xReturn = pdFAIL; + } + + traceRETURN_xTaskCallApplicationTaskHook( xReturn ); + + return xReturn; + } + +#endif /* configUSE_APPLICATION_TASK_TAG */ +/*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES == 1 ) + void vTaskSwitchContext( void ) + { + traceENTER_vTaskSwitchContext(); + + if( uxSchedulerSuspended != ( UBaseType_t ) 0U ) + { + /* The scheduler is currently suspended - do not allow a context + * switch. */ + xYieldPendings[ 0 ] = pdTRUE; + } + else + { + xYieldPendings[ 0 ] = pdFALSE; + traceTASK_SWITCHED_OUT(); + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + { + #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE + portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime[ 0 ] ); + #else + ulTotalRunTime[ 0 ] = portGET_RUN_TIME_COUNTER_VALUE(); + #endif + + /* Add the amount of time the task has been running to the + * accumulated time so far. The time the task started running was + * stored in ulTaskSwitchedInTime. Note that there is no overflow + * protection here so count values are only valid until the timer + * overflows. The guard against negative values is to protect + * against suspect run time stat counter implementations - which + * are provided by the application, not the kernel. */ + if( ulTotalRunTime[ 0 ] > ulTaskSwitchedInTime[ 0 ] ) + { + pxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime[ 0 ] - ulTaskSwitchedInTime[ 0 ] ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + ulTaskSwitchedInTime[ 0 ] = ulTotalRunTime[ 0 ]; + } + #endif /* configGENERATE_RUN_TIME_STATS */ + + /* Check for stack overflow, if configured. */ + taskCHECK_FOR_STACK_OVERFLOW(); + + /* Before the currently running task is switched out, save its errno. */ + #if ( configUSE_POSIX_ERRNO == 1 ) + { + pxCurrentTCB->iTaskErrno = FreeRTOS_errno; + } + #endif + + /* Select a new task to run using either the generic C or port + * optimised asm code. */ + /* MISRA Ref 11.5.3 [Void pointer assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + taskSELECT_HIGHEST_PRIORITY_TASK(); + traceTASK_SWITCHED_IN(); + + /* Macro to inject port specific behaviour immediately after + * switching tasks, such as setting an end of stack watchpoint + * or reconfiguring the MPU. */ + portTASK_SWITCH_HOOK( pxCurrentTCB ); + + /* After the new task is switched in, update the global errno. */ + #if ( configUSE_POSIX_ERRNO == 1 ) + { + FreeRTOS_errno = pxCurrentTCB->iTaskErrno; + } + #endif + + #if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) + { + /* Switch C-Runtime's TLS Block to point to the TLS + * Block specific to this task. */ + configSET_TLS_BLOCK( pxCurrentTCB->xTLSBlock ); + } + #endif + } + + traceRETURN_vTaskSwitchContext(); + } +#else /* if ( configNUMBER_OF_CORES == 1 ) */ + void vTaskSwitchContext( BaseType_t xCoreID ) + { + traceENTER_vTaskSwitchContext(); + + /* Acquire both locks: + * - The ISR lock protects the ready list from simultaneous access by + * both other ISRs and tasks. + * - We also take the task lock to pause here in case another core has + * suspended the scheduler. We don't want to simply set xYieldPending + * and move on if another core suspended the scheduler. We should only + * do that if the current core has suspended the scheduler. */ + + portGET_TASK_LOCK( xCoreID ); /* Must always acquire the task lock first. */ + portGET_ISR_LOCK( xCoreID ); + { + /* vTaskSwitchContext() must never be called from within a critical section. + * This is not necessarily true for single core FreeRTOS, but it is for this + * SMP port. */ + configASSERT( portGET_CRITICAL_NESTING_COUNT( xCoreID ) == 0 ); + + if( uxSchedulerSuspended != ( UBaseType_t ) 0U ) + { + /* The scheduler is currently suspended - do not allow a context + * switch. */ + xYieldPendings[ xCoreID ] = pdTRUE; + } + else + { + xYieldPendings[ xCoreID ] = pdFALSE; + traceTASK_SWITCHED_OUT(); + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + { + #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE + portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime[ xCoreID ] ); + #else + ulTotalRunTime[ xCoreID ] = portGET_RUN_TIME_COUNTER_VALUE(); + #endif + + /* Add the amount of time the task has been running to the + * accumulated time so far. The time the task started running was + * stored in ulTaskSwitchedInTime. Note that there is no overflow + * protection here so count values are only valid until the timer + * overflows. The guard against negative values is to protect + * against suspect run time stat counter implementations - which + * are provided by the application, not the kernel. */ + if( ulTotalRunTime[ xCoreID ] > ulTaskSwitchedInTime[ xCoreID ] ) + { + pxCurrentTCBs[ xCoreID ]->ulRunTimeCounter += ( ulTotalRunTime[ xCoreID ] - ulTaskSwitchedInTime[ xCoreID ] ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + ulTaskSwitchedInTime[ xCoreID ] = ulTotalRunTime[ xCoreID ]; + } + #endif /* configGENERATE_RUN_TIME_STATS */ + + /* Check for stack overflow, if configured. */ + taskCHECK_FOR_STACK_OVERFLOW(); + + /* Before the currently running task is switched out, save its errno. */ + #if ( configUSE_POSIX_ERRNO == 1 ) + { + pxCurrentTCBs[ xCoreID ]->iTaskErrno = FreeRTOS_errno; + } + #endif + + /* Select a new task to run. */ + taskSELECT_HIGHEST_PRIORITY_TASK( xCoreID ); + traceTASK_SWITCHED_IN(); + + /* Macro to inject port specific behaviour immediately after + * switching tasks, such as setting an end of stack watchpoint + * or reconfiguring the MPU. */ + portTASK_SWITCH_HOOK( pxCurrentTCBs[ portGET_CORE_ID() ] ); + + /* After the new task is switched in, update the global errno. */ + #if ( configUSE_POSIX_ERRNO == 1 ) + { + FreeRTOS_errno = pxCurrentTCBs[ xCoreID ]->iTaskErrno; + } + #endif + + #if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) + { + /* Switch C-Runtime's TLS Block to point to the TLS + * Block specific to this task. */ + configSET_TLS_BLOCK( pxCurrentTCBs[ xCoreID ]->xTLSBlock ); + } + #endif + } + } + portRELEASE_ISR_LOCK( xCoreID ); + portRELEASE_TASK_LOCK( xCoreID ); + + traceRETURN_vTaskSwitchContext(); + } +#endif /* if ( configNUMBER_OF_CORES > 1 ) */ +/*-----------------------------------------------------------*/ + +void vTaskPlaceOnEventList( List_t * const pxEventList, + const TickType_t xTicksToWait ) +{ + traceENTER_vTaskPlaceOnEventList( pxEventList, xTicksToWait ); + + configASSERT( pxEventList ); + + /* THIS FUNCTION MUST BE CALLED WITH THE + * SCHEDULER SUSPENDED AND THE QUEUE BEING ACCESSED LOCKED. */ + + /* Place the event list item of the TCB in the appropriate event list. + * This is placed in the list in priority order so the highest priority task + * is the first to be woken by the event. + * + * Note: Lists are sorted in ascending order by ListItem_t.xItemValue. + * Normally, the xItemValue of a TCB's ListItem_t members is: + * xItemValue = ( configMAX_PRIORITIES - uxPriority ) + * Therefore, the event list is sorted in descending priority order. + * + * The queue that contains the event list is locked, preventing + * simultaneous access from interrupts. */ + vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) ); + + prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); + + traceRETURN_vTaskPlaceOnEventList(); +} +/*-----------------------------------------------------------*/ + +void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, + const TickType_t xItemValue, + const TickType_t xTicksToWait ) +{ + traceENTER_vTaskPlaceOnUnorderedEventList( pxEventList, xItemValue, xTicksToWait ); + + configASSERT( pxEventList ); + + /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. It is used by + * the event groups implementation. */ + configASSERT( uxSchedulerSuspended != ( UBaseType_t ) 0U ); + + /* Store the item value in the event list item. It is safe to access the + * event list item here as interrupts won't access the event list item of a + * task that is not in the Blocked state. */ + listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE ); + + /* Place the event list item of the TCB at the end of the appropriate event + * list. It is safe to access the event list here because it is part of an + * event group implementation - and interrupts don't access event groups + * directly (instead they access them indirectly by pending function calls to + * the task level). */ + listINSERT_END( pxEventList, &( pxCurrentTCB->xEventListItem ) ); + + prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); + + traceRETURN_vTaskPlaceOnUnorderedEventList(); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TIMERS == 1 ) + + void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, + TickType_t xTicksToWait, + const BaseType_t xWaitIndefinitely ) + { + traceENTER_vTaskPlaceOnEventListRestricted( pxEventList, xTicksToWait, xWaitIndefinitely ); + + configASSERT( pxEventList ); + + /* This function should not be called by application code hence the + * 'Restricted' in its name. It is not part of the public API. It is + * designed for use by kernel code, and has special calling requirements - + * it should be called with the scheduler suspended. */ + + + /* Place the event list item of the TCB in the appropriate event list. + * In this case it is assume that this is the only task that is going to + * be waiting on this event list, so the faster vListInsertEnd() function + * can be used in place of vListInsert. */ + listINSERT_END( pxEventList, &( pxCurrentTCB->xEventListItem ) ); + + /* If the task should block indefinitely then set the block time to a + * value that will be recognised as an indefinite delay inside the + * prvAddCurrentTaskToDelayedList() function. */ + if( xWaitIndefinitely != pdFALSE ) + { + xTicksToWait = portMAX_DELAY; + } + + traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) ); + prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely ); + + traceRETURN_vTaskPlaceOnEventListRestricted(); + } + +#endif /* configUSE_TIMERS */ +/*-----------------------------------------------------------*/ + +BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) +{ + TCB_t * pxUnblockedTCB; + BaseType_t xReturn; + + traceENTER_xTaskRemoveFromEventList( pxEventList ); + + /* THIS FUNCTION MUST BE CALLED FROM A CRITICAL SECTION. It can also be + * called from a critical section within an ISR. */ + + /* The event list is sorted in priority order, so the first in the list can + * be removed as it is known to be the highest priority. Remove the TCB from + * the delayed list, and add it to the ready list. + * + * If an event is for a queue that is locked then this function will never + * get called - the lock count on the queue will get modified instead. This + * means exclusive access to the event list is guaranteed here. + * + * This function assumes that a check has already been made to ensure that + * pxEventList is not empty. */ + /* MISRA Ref 11.5.3 [Void pointer assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); + configASSERT( pxUnblockedTCB ); + listREMOVE_ITEM( &( pxUnblockedTCB->xEventListItem ) ); + + if( uxSchedulerSuspended == ( UBaseType_t ) 0U ) + { + listREMOVE_ITEM( &( pxUnblockedTCB->xStateListItem ) ); + prvAddTaskToReadyList( pxUnblockedTCB ); + + #if ( configUSE_TICKLESS_IDLE != 0 ) + { + /* If a task is blocked on a kernel object then xNextTaskUnblockTime + * might be set to the blocked task's time out time. If the task is + * unblocked for a reason other than a timeout xNextTaskUnblockTime is + * normally left unchanged, because it is automatically reset to a new + * value when the tick count equals xNextTaskUnblockTime. However if + * tickless idling is used it might be more important to enter sleep mode + * at the earliest possible time - so reset xNextTaskUnblockTime here to + * ensure it is updated at the earliest possible time. */ + prvResetNextTaskUnblockTime(); + } + #endif + } + else + { + /* The delayed and ready lists cannot be accessed, so hold this task + * pending until the scheduler is resumed. */ + listINSERT_END( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) ); + } + + #if ( configNUMBER_OF_CORES == 1 ) + { + if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority ) + { + /* Return true if the task removed from the event list has a higher + * priority than the calling task. This allows the calling task to know if + * it should force a context switch now. */ + xReturn = pdTRUE; + + /* Mark that a yield is pending in case the user is not using the + * "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */ + xYieldPendings[ 0 ] = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + } + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + { + xReturn = pdFALSE; + + #if ( configUSE_PREEMPTION == 1 ) + { + prvYieldForTask( pxUnblockedTCB ); + + if( xYieldPendings[ portGET_CORE_ID() ] != pdFALSE ) + { + xReturn = pdTRUE; + } + } + #endif /* #if ( configUSE_PREEMPTION == 1 ) */ + } + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ + + traceRETURN_xTaskRemoveFromEventList( xReturn ); + return xReturn; +} +/*-----------------------------------------------------------*/ + +void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, + const TickType_t xItemValue ) +{ + TCB_t * pxUnblockedTCB; + + traceENTER_vTaskRemoveFromUnorderedEventList( pxEventListItem, xItemValue ); + + /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. It is used by + * the event flags implementation. */ + configASSERT( uxSchedulerSuspended != ( UBaseType_t ) 0U ); + + /* Store the new item value in the event list. */ + listSET_LIST_ITEM_VALUE( pxEventListItem, xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE ); + + /* Remove the event list form the event flag. Interrupts do not access + * event flags. */ + /* MISRA Ref 11.5.3 [Void pointer assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + pxUnblockedTCB = listGET_LIST_ITEM_OWNER( pxEventListItem ); + configASSERT( pxUnblockedTCB ); + listREMOVE_ITEM( pxEventListItem ); + + #if ( configUSE_TICKLESS_IDLE != 0 ) + { + /* If a task is blocked on a kernel object then xNextTaskUnblockTime + * might be set to the blocked task's time out time. If the task is + * unblocked for a reason other than a timeout xNextTaskUnblockTime is + * normally left unchanged, because it is automatically reset to a new + * value when the tick count equals xNextTaskUnblockTime. However if + * tickless idling is used it might be more important to enter sleep mode + * at the earliest possible time - so reset xNextTaskUnblockTime here to + * ensure it is updated at the earliest possible time. */ + prvResetNextTaskUnblockTime(); + } + #endif + + /* Remove the task from the delayed list and add it to the ready list. The + * scheduler is suspended so interrupts will not be accessing the ready + * lists. */ + listREMOVE_ITEM( &( pxUnblockedTCB->xStateListItem ) ); + prvAddTaskToReadyList( pxUnblockedTCB ); + + #if ( configNUMBER_OF_CORES == 1 ) + { + if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority ) + { + /* The unblocked task has a priority above that of the calling task, so + * a context switch is required. This function is called with the + * scheduler suspended so xYieldPending is set so the context switch + * occurs immediately that the scheduler is resumed (unsuspended). */ + xYieldPendings[ 0 ] = pdTRUE; + } + } + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + { + #if ( configUSE_PREEMPTION == 1 ) + { + taskENTER_CRITICAL(); + { + prvYieldForTask( pxUnblockedTCB ); + } + taskEXIT_CRITICAL(); + } + #endif + } + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ + + traceRETURN_vTaskRemoveFromUnorderedEventList(); +} +/*-----------------------------------------------------------*/ + +void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) +{ + traceENTER_vTaskSetTimeOutState( pxTimeOut ); + + configASSERT( pxTimeOut ); + taskENTER_CRITICAL(); + { + pxTimeOut->xOverflowCount = xNumOfOverflows; + pxTimeOut->xTimeOnEntering = xTickCount; + } + taskEXIT_CRITICAL(); + + traceRETURN_vTaskSetTimeOutState(); +} +/*-----------------------------------------------------------*/ + +void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) +{ + traceENTER_vTaskInternalSetTimeOutState( pxTimeOut ); + + /* For internal use only as it does not use a critical section. */ + pxTimeOut->xOverflowCount = xNumOfOverflows; + pxTimeOut->xTimeOnEntering = xTickCount; + + traceRETURN_vTaskInternalSetTimeOutState(); +} +/*-----------------------------------------------------------*/ + +BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) +{ + BaseType_t xReturn; + + traceENTER_xTaskCheckForTimeOut( pxTimeOut, pxTicksToWait ); + + configASSERT( pxTimeOut ); + configASSERT( pxTicksToWait ); + + taskENTER_CRITICAL(); + { + /* Minor optimisation. The tick count cannot change in this block. */ + const TickType_t xConstTickCount = xTickCount; + const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering; + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + if( pxCurrentTCB->ucDelayAborted != ( uint8_t ) pdFALSE ) + { + /* The delay was aborted, which is not the same as a time out, + * but has the same result. */ + pxCurrentTCB->ucDelayAborted = ( uint8_t ) pdFALSE; + xReturn = pdTRUE; + } + else + #endif + + #if ( INCLUDE_vTaskSuspend == 1 ) + if( *pxTicksToWait == portMAX_DELAY ) + { + /* If INCLUDE_vTaskSuspend is set to 1 and the block time + * specified is the maximum block time then the task should block + * indefinitely, and therefore never time out. */ + xReturn = pdFALSE; + } + else + #endif + + if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) + { + /* The tick count is greater than the time at which + * vTaskSetTimeout() was called, but has also overflowed since + * vTaskSetTimeOut() was called. It must have wrapped all the way + * around and gone past again. This passed since vTaskSetTimeout() + * was called. */ + xReturn = pdTRUE; + *pxTicksToWait = ( TickType_t ) 0; + } + else if( xElapsedTime < *pxTicksToWait ) + { + /* Not a genuine timeout. Adjust parameters for time remaining. */ + *pxTicksToWait -= xElapsedTime; + vTaskInternalSetTimeOutState( pxTimeOut ); + xReturn = pdFALSE; + } + else + { + *pxTicksToWait = ( TickType_t ) 0; + xReturn = pdTRUE; + } + } + taskEXIT_CRITICAL(); + + traceRETURN_xTaskCheckForTimeOut( xReturn ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void vTaskMissedYield( void ) +{ + traceENTER_vTaskMissedYield(); + + /* Must be called from within a critical section. */ + xYieldPendings[ portGET_CORE_ID() ] = pdTRUE; + + traceRETURN_vTaskMissedYield(); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ) + { + UBaseType_t uxReturn; + TCB_t const * pxTCB; + + traceENTER_uxTaskGetTaskNumber( xTask ); + + if( xTask != NULL ) + { + pxTCB = xTask; + uxReturn = pxTCB->uxTaskNumber; + } + else + { + uxReturn = 0U; + } + + traceRETURN_uxTaskGetTaskNumber( uxReturn ); + + return uxReturn; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + void vTaskSetTaskNumber( TaskHandle_t xTask, + const UBaseType_t uxHandle ) + { + TCB_t * pxTCB; + + traceENTER_vTaskSetTaskNumber( xTask, uxHandle ); + + if( xTask != NULL ) + { + pxTCB = xTask; + pxTCB->uxTaskNumber = uxHandle; + } + + traceRETURN_vTaskSetTaskNumber(); + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +/* + * ----------------------------------------------------------- + * The passive idle task. + * ---------------------------------------------------------- + * + * The passive idle task is used for all the additional cores in a SMP + * system. There must be only 1 active idle task and the rest are passive + * idle tasks. + * + * The portTASK_FUNCTION() macro is used to allow port/compiler specific + * language extensions. The equivalent prototype for this function is: + * + * void prvPassiveIdleTask( void *pvParameters ); + */ + +#if ( configNUMBER_OF_CORES > 1 ) + static portTASK_FUNCTION( prvPassiveIdleTask, pvParameters ) + { + ( void ) pvParameters; + + taskYIELD(); + + for( ; configCONTROL_INFINITE_LOOP(); ) + { + #if ( configUSE_PREEMPTION == 0 ) + { + /* If we are not using preemption we keep forcing a task switch to + * see if any other task has become available. If we are using + * preemption we don't need to do this as any task becoming available + * will automatically get the processor anyway. */ + taskYIELD(); + } + #endif /* configUSE_PREEMPTION */ + + #if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) + { + /* When using preemption tasks of equal priority will be + * timesliced. If a task that is sharing the idle priority is ready + * to run then the idle task should yield before the end of the + * timeslice. + * + * A critical region is not required here as we are just reading from + * the list, and an occasional incorrect value will not matter. If + * the ready list at the idle priority contains one more task than the + * number of idle tasks, which is equal to the configured numbers of cores + * then a task other than the idle task is ready to execute. */ + if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) configNUMBER_OF_CORES ) + { + taskYIELD(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) */ + + #if ( configUSE_PASSIVE_IDLE_HOOK == 1 ) + { + /* Call the user defined function from within the idle task. This + * allows the application designer to add background functionality + * without the overhead of a separate task. + * + * This hook is intended to manage core activity such as disabling cores that go idle. + * + * NOTE: vApplicationPassiveIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES, + * CALL A FUNCTION THAT MIGHT BLOCK. */ + vApplicationPassiveIdleHook(); + } + #endif /* configUSE_PASSIVE_IDLE_HOOK */ + } + } +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ + +/* + * ----------------------------------------------------------- + * The idle task. + * ---------------------------------------------------------- + * + * The portTASK_FUNCTION() macro is used to allow port/compiler specific + * language extensions. The equivalent prototype for this function is: + * + * void prvIdleTask( void *pvParameters ); + * + */ + +static portTASK_FUNCTION( prvIdleTask, pvParameters ) +{ + /* Stop warnings. */ + ( void ) pvParameters; + + /** THIS IS THE RTOS IDLE TASK - WHICH IS CREATED AUTOMATICALLY WHEN THE + * SCHEDULER IS STARTED. **/ + + /* In case a task that has a secure context deletes itself, in which case + * the idle task is responsible for deleting the task's secure context, if + * any. */ + portALLOCATE_SECURE_CONTEXT( configMINIMAL_SECURE_STACK_SIZE ); + + #if ( configNUMBER_OF_CORES > 1 ) + { + /* SMP all cores start up in the idle task. This initial yield gets the application + * tasks started. */ + taskYIELD(); + } + #endif /* #if ( configNUMBER_OF_CORES > 1 ) */ + + for( ; configCONTROL_INFINITE_LOOP(); ) + { + /* See if any tasks have deleted themselves - if so then the idle task + * is responsible for freeing the deleted task's TCB and stack. */ + prvCheckTasksWaitingTermination(); + + #if ( configUSE_PREEMPTION == 0 ) + { + /* If we are not using preemption we keep forcing a task switch to + * see if any other task has become available. If we are using + * preemption we don't need to do this as any task becoming available + * will automatically get the processor anyway. */ + taskYIELD(); + } + #endif /* configUSE_PREEMPTION */ + + #if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) + { + /* When using preemption tasks of equal priority will be + * timesliced. If a task that is sharing the idle priority is ready + * to run then the idle task should yield before the end of the + * timeslice. + * + * A critical region is not required here as we are just reading from + * the list, and an occasional incorrect value will not matter. If + * the ready list at the idle priority contains one more task than the + * number of idle tasks, which is equal to the configured numbers of cores + * then a task other than the idle task is ready to execute. */ + if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) configNUMBER_OF_CORES ) + { + taskYIELD(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) */ + + #if ( configUSE_IDLE_HOOK == 1 ) + { + /* Call the user defined function from within the idle task. */ + vApplicationIdleHook(); + } + #endif /* configUSE_IDLE_HOOK */ + + /* This conditional compilation should use inequality to 0, not equality + * to 1. This is to ensure portSUPPRESS_TICKS_AND_SLEEP() is called when + * user defined low power mode implementations require + * configUSE_TICKLESS_IDLE to be set to a value other than 1. */ + #if ( configUSE_TICKLESS_IDLE != 0 ) + { + TickType_t xExpectedIdleTime; + + /* It is not desirable to suspend then resume the scheduler on + * each iteration of the idle task. Therefore, a preliminary + * test of the expected idle time is performed without the + * scheduler suspended. The result here is not necessarily + * valid. */ + xExpectedIdleTime = prvGetExpectedIdleTime(); + + if( xExpectedIdleTime >= ( TickType_t ) configEXPECTED_IDLE_TIME_BEFORE_SLEEP ) + { + vTaskSuspendAll(); + { + /* Now the scheduler is suspended, the expected idle + * time can be sampled again, and this time its value can + * be used. */ + configASSERT( xNextTaskUnblockTime >= xTickCount ); + xExpectedIdleTime = prvGetExpectedIdleTime(); + + /* Define the following macro to set xExpectedIdleTime to 0 + * if the application does not want + * portSUPPRESS_TICKS_AND_SLEEP() to be called. */ + configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( xExpectedIdleTime ); + + if( xExpectedIdleTime >= ( TickType_t ) configEXPECTED_IDLE_TIME_BEFORE_SLEEP ) + { + traceLOW_POWER_IDLE_BEGIN(); + portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ); + traceLOW_POWER_IDLE_END(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + ( void ) xTaskResumeAll(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_TICKLESS_IDLE */ + + #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_PASSIVE_IDLE_HOOK == 1 ) ) + { + /* Call the user defined function from within the idle task. This + * allows the application designer to add background functionality + * without the overhead of a separate task. + * + * This hook is intended to manage core activity such as disabling cores that go idle. + * + * NOTE: vApplicationPassiveIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES, + * CALL A FUNCTION THAT MIGHT BLOCK. */ + vApplicationPassiveIdleHook(); + } + #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_PASSIVE_IDLE_HOOK == 1 ) ) */ + } +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE != 0 ) + + eSleepModeStatus eTaskConfirmSleepModeStatus( void ) + { + #if ( INCLUDE_vTaskSuspend == 1 ) + /* The idle task exists in addition to the application tasks. */ + const UBaseType_t uxNonApplicationTasks = configNUMBER_OF_CORES; + #endif /* INCLUDE_vTaskSuspend */ + + eSleepModeStatus eReturn = eStandardSleep; + + traceENTER_eTaskConfirmSleepModeStatus(); + + /* This function must be called from a critical section. */ + + if( listCURRENT_LIST_LENGTH( &xPendingReadyList ) != 0U ) + { + /* A task was made ready while the scheduler was suspended. */ + eReturn = eAbortSleep; + } + else if( xYieldPendings[ portGET_CORE_ID() ] != pdFALSE ) + { + /* A yield was pended while the scheduler was suspended. */ + eReturn = eAbortSleep; + } + else if( xPendedTicks != 0U ) + { + /* A tick interrupt has already occurred but was held pending + * because the scheduler is suspended. */ + eReturn = eAbortSleep; + } + + #if ( INCLUDE_vTaskSuspend == 1 ) + else if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == ( uxCurrentNumberOfTasks - uxNonApplicationTasks ) ) + { + /* If all the tasks are in the suspended list (which might mean they + * have an infinite block time rather than actually being suspended) + * then it is safe to turn all clocks off and just wait for external + * interrupts. */ + eReturn = eNoTasksWaitingTimeout; + } + #endif /* INCLUDE_vTaskSuspend */ + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceRETURN_eTaskConfirmSleepModeStatus( eReturn ); + + return eReturn; + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) + { + TCB_t * pxTCB; + + traceENTER_vTaskSetThreadLocalStoragePointer( xTaskToSet, xIndex, pvValue ); + + if( ( xIndex >= 0 ) && + ( xIndex < ( BaseType_t ) configNUM_THREAD_LOCAL_STORAGE_POINTERS ) ) + { + pxTCB = prvGetTCBFromHandle( xTaskToSet ); + configASSERT( pxTCB != NULL ); + pxTCB->pvThreadLocalStoragePointers[ xIndex ] = pvValue; + } + + traceRETURN_vTaskSetThreadLocalStoragePointer(); + } + +#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */ +/*-----------------------------------------------------------*/ + +#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) + + void * pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) + { + void * pvReturn = NULL; + TCB_t * pxTCB; + + traceENTER_pvTaskGetThreadLocalStoragePointer( xTaskToQuery, xIndex ); + + if( ( xIndex >= 0 ) && + ( xIndex < ( BaseType_t ) configNUM_THREAD_LOCAL_STORAGE_POINTERS ) ) + { + pxTCB = prvGetTCBFromHandle( xTaskToQuery ); + configASSERT( pxTCB != NULL ); + + pvReturn = pxTCB->pvThreadLocalStoragePointers[ xIndex ]; + } + else + { + pvReturn = NULL; + } + + traceRETURN_pvTaskGetThreadLocalStoragePointer( pvReturn ); + + return pvReturn; + } + +#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */ +/*-----------------------------------------------------------*/ + +#if ( portUSING_MPU_WRAPPERS == 1 ) + + void vTaskAllocateMPURegions( TaskHandle_t xTaskToModify, + const MemoryRegion_t * const pxRegions ) + { + TCB_t * pxTCB; + + traceENTER_vTaskAllocateMPURegions( xTaskToModify, pxRegions ); + + /* If null is passed in here then we are modifying the MPU settings of + * the calling task. */ + pxTCB = prvGetTCBFromHandle( xTaskToModify ); + configASSERT( pxTCB != NULL ); + + vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), pxRegions, NULL, 0 ); + + traceRETURN_vTaskAllocateMPURegions(); + } + +#endif /* portUSING_MPU_WRAPPERS */ +/*-----------------------------------------------------------*/ + +static void prvInitialiseTaskLists( void ) +{ + UBaseType_t uxPriority; + + for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) + { + vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) ); + } + + vListInitialise( &xDelayedTaskList1 ); + vListInitialise( &xDelayedTaskList2 ); + vListInitialise( &xPendingReadyList ); + + #if ( INCLUDE_vTaskDelete == 1 ) + { + vListInitialise( &xTasksWaitingTermination ); + } + #endif /* INCLUDE_vTaskDelete */ + + #if ( INCLUDE_vTaskSuspend == 1 ) + { + vListInitialise( &xSuspendedTaskList ); + } + #endif /* INCLUDE_vTaskSuspend */ + + /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList + * using list2. */ + pxDelayedTaskList = &xDelayedTaskList1; + pxOverflowDelayedTaskList = &xDelayedTaskList2; +} +/*-----------------------------------------------------------*/ + +static void prvCheckTasksWaitingTermination( void ) +{ + /** THIS FUNCTION IS CALLED FROM THE RTOS IDLE TASK **/ + + #if ( INCLUDE_vTaskDelete == 1 ) + { + TCB_t * pxTCB; + + /* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL() + * being called too often in the idle task. */ + while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) + { + #if ( configNUMBER_OF_CORES == 1 ) + { + taskENTER_CRITICAL(); + { + { + /* MISRA Ref 11.5.3 [Void pointer assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + --uxCurrentNumberOfTasks; + --uxDeletedTasksWaitingCleanUp; + } + } + taskEXIT_CRITICAL(); + + prvDeleteTCB( pxTCB ); + } + #else /* #if( configNUMBER_OF_CORES == 1 ) */ + { + pxTCB = NULL; + + taskENTER_CRITICAL(); + { + /* For SMP, multiple idles can be running simultaneously + * and we need to check that other idles did not cleanup while we were + * waiting to enter the critical section. */ + if( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) + { + /* MISRA Ref 11.5.3 [Void pointer assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); + + if( pxTCB->xTaskRunState == taskTASK_NOT_RUNNING ) + { + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + --uxCurrentNumberOfTasks; + --uxDeletedTasksWaitingCleanUp; + } + else + { + /* The TCB to be deleted still has not yet been switched out + * by the scheduler, so we will just exit this loop early and + * try again next time. */ + taskEXIT_CRITICAL(); + break; + } + } + } + taskEXIT_CRITICAL(); + + if( pxTCB != NULL ) + { + prvDeleteTCB( pxTCB ); + } + } + #endif /* #if( configNUMBER_OF_CORES == 1 ) */ + } + } + #endif /* INCLUDE_vTaskDelete */ +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + void vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) + { + TCB_t * pxTCB; + + traceENTER_vTaskGetInfo( xTask, pxTaskStatus, xGetFreeStackSpace, eState ); + + /* xTask is NULL then get the state of the calling task. */ + pxTCB = prvGetTCBFromHandle( xTask ); + configASSERT( pxTCB != NULL ); + + pxTaskStatus->xHandle = pxTCB; + pxTaskStatus->pcTaskName = ( const char * ) &( pxTCB->pcTaskName[ 0 ] ); + pxTaskStatus->uxCurrentPriority = pxTCB->uxPriority; + pxTaskStatus->pxStackBase = pxTCB->pxStack; + #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) ) + pxTaskStatus->pxTopOfStack = ( StackType_t * ) pxTCB->pxTopOfStack; + pxTaskStatus->pxEndOfStack = pxTCB->pxEndOfStack; + #endif + pxTaskStatus->xTaskNumber = pxTCB->uxTCBNumber; + + #if ( ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) ) + { + pxTaskStatus->uxCoreAffinityMask = pxTCB->uxCoreAffinityMask; + } + #endif + + #if ( configUSE_MUTEXES == 1 ) + { + pxTaskStatus->uxBasePriority = pxTCB->uxBasePriority; + } + #else + { + pxTaskStatus->uxBasePriority = 0; + } + #endif + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + { + pxTaskStatus->ulRunTimeCounter = ulTaskGetRunTimeCounter( xTask ); + } + #else + { + pxTaskStatus->ulRunTimeCounter = ( configRUN_TIME_COUNTER_TYPE ) 0; + } + #endif + + /* Obtaining the task state is a little fiddly, so is only done if the + * value of eState passed into this function is eInvalid - otherwise the + * state is just set to whatever is passed in. */ + if( eState != eInvalid ) + { + if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE ) + { + pxTaskStatus->eCurrentState = eRunning; + } + else + { + pxTaskStatus->eCurrentState = eState; + + #if ( INCLUDE_vTaskSuspend == 1 ) + { + /* If the task is in the suspended list then there is a + * chance it is actually just blocked indefinitely - so really + * it should be reported as being in the Blocked state. */ + if( eState == eSuspended ) + { + vTaskSuspendAll(); + { + if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) + { + pxTaskStatus->eCurrentState = eBlocked; + } + else + { + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + { + BaseType_t x; + + /* The task does not appear on the event list item of + * and of the RTOS objects, but could still be in the + * blocked state if it is waiting on its notification + * rather than waiting on an object. If not, is + * suspended. */ + for( x = ( BaseType_t ) 0; x < ( BaseType_t ) configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ ) + { + if( pxTCB->ucNotifyState[ x ] == taskWAITING_NOTIFICATION ) + { + pxTaskStatus->eCurrentState = eBlocked; + break; + } + } + } + #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ + } + } + ( void ) xTaskResumeAll(); + } + } + #endif /* INCLUDE_vTaskSuspend */ + + /* Tasks can be in pending ready list and other state list at the + * same time. These tasks are in ready state no matter what state + * list the task is in. */ + taskENTER_CRITICAL(); + { + if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) != pdFALSE ) + { + pxTaskStatus->eCurrentState = eReady; + } + } + taskEXIT_CRITICAL(); + } + } + else + { + pxTaskStatus->eCurrentState = eTaskGetState( pxTCB ); + } + + /* Obtaining the stack space takes some time, so the xGetFreeStackSpace + * parameter is provided to allow it to be skipped. */ + if( xGetFreeStackSpace != pdFALSE ) + { + #if ( portSTACK_GROWTH > 0 ) + { + pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxEndOfStack ); + } + #else + { + pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxStack ); + } + #endif + } + else + { + pxTaskStatus->usStackHighWaterMark = 0; + } + + traceRETURN_vTaskGetInfo(); + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t * pxTaskStatusArray, + List_t * pxList, + eTaskState eState ) + { + UBaseType_t uxTask = 0; + const ListItem_t * pxEndMarker = listGET_END_MARKER( pxList ); + ListItem_t * pxIterator; + TCB_t * pxTCB = NULL; + + if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 ) + { + /* Populate an TaskStatus_t structure within the + * pxTaskStatusArray array for each task that is referenced from + * pxList. See the definition of TaskStatus_t in task.h for the + * meaning of each TaskStatus_t structure member. */ + for( pxIterator = listGET_HEAD_ENTRY( pxList ); pxIterator != pxEndMarker; pxIterator = listGET_NEXT( pxIterator ) ) + { + /* MISRA Ref 11.5.3 [Void pointer assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + pxTCB = listGET_LIST_ITEM_OWNER( pxIterator ); + + vTaskGetInfo( ( TaskHandle_t ) pxTCB, &( pxTaskStatusArray[ uxTask ] ), pdTRUE, eState ); + uxTask++; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return uxTask; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) ) + + static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) + { + configSTACK_DEPTH_TYPE uxCount = 0U; + + while( *pucStackByte == ( uint8_t ) tskSTACK_FILL_BYTE ) + { + pucStackByte -= portSTACK_GROWTH; + uxCount++; + } + + uxCount /= ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ); + + return uxCount; + } + +#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) + +/* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the + * same except for their return type. Using configSTACK_DEPTH_TYPE allows the + * user to determine the return type. It gets around the problem of the value + * overflowing on 8-bit types without breaking backward compatibility for + * applications that expect an 8-bit return type. */ + configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) + { + TCB_t * pxTCB; + uint8_t * pucEndOfStack; + configSTACK_DEPTH_TYPE uxReturn; + + traceENTER_uxTaskGetStackHighWaterMark2( xTask ); + + /* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are + * the same except for their return type. Using configSTACK_DEPTH_TYPE + * allows the user to determine the return type. It gets around the + * problem of the value overflowing on 8-bit types without breaking + * backward compatibility for applications that expect an 8-bit return + * type. */ + + pxTCB = prvGetTCBFromHandle( xTask ); + configASSERT( pxTCB != NULL ); + + #if portSTACK_GROWTH < 0 + { + pucEndOfStack = ( uint8_t * ) pxTCB->pxStack; + } + #else + { + pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack; + } + #endif + + uxReturn = prvTaskCheckFreeStackSpace( pucEndOfStack ); + + traceRETURN_uxTaskGetStackHighWaterMark2( uxReturn ); + + return uxReturn; + } + +#endif /* INCLUDE_uxTaskGetStackHighWaterMark2 */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) + + UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) + { + TCB_t * pxTCB; + uint8_t * pucEndOfStack; + UBaseType_t uxReturn; + + traceENTER_uxTaskGetStackHighWaterMark( xTask ); + + pxTCB = prvGetTCBFromHandle( xTask ); + configASSERT( pxTCB != NULL ); + + #if portSTACK_GROWTH < 0 + { + pucEndOfStack = ( uint8_t * ) pxTCB->pxStack; + } + #else + { + pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack; + } + #endif + + uxReturn = ( UBaseType_t ) prvTaskCheckFreeStackSpace( pucEndOfStack ); + + traceRETURN_uxTaskGetStackHighWaterMark( uxReturn ); + + return uxReturn; + } + +#endif /* INCLUDE_uxTaskGetStackHighWaterMark */ +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskDelete == 1 ) + + static void prvDeleteTCB( TCB_t * pxTCB ) + { + /* This call is required specifically for the TriCore port. It must be + * above the vPortFree() calls. The call is also used by ports/demos that + * want to allocate and clean RAM statically. */ + portCLEAN_UP_TCB( pxTCB ); + + #if ( configUSE_C_RUNTIME_TLS_SUPPORT == 1 ) + { + /* Free up the memory allocated for the task's TLS Block. */ + configDEINIT_TLS_BLOCK( pxTCB->xTLSBlock ); + } + #endif + + #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( portUSING_MPU_WRAPPERS == 0 ) ) + { + /* The task can only have been allocated dynamically - free both + * the stack and TCB. */ + vPortFreeStack( pxTCB->pxStack ); + vPortFree( pxTCB ); + } + #elif ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) + { + /* The task could have been allocated statically or dynamically, so + * check what was statically allocated before trying to free the + * memory. */ + if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB ) + { + /* Both the stack and TCB were allocated dynamically, so both + * must be freed. */ + vPortFreeStack( pxTCB->pxStack ); + vPortFree( pxTCB ); + } + else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY ) + { + /* Only the stack was statically allocated, so the TCB is the + * only memory that must be freed. */ + vPortFree( pxTCB ); + } + else + { + /* Neither the stack nor the TCB were allocated dynamically, so + * nothing needs to be freed. */ + configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB ); + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + } + +#endif /* INCLUDE_vTaskDelete */ +/*-----------------------------------------------------------*/ + +static void prvResetNextTaskUnblockTime( void ) +{ + if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) + { + /* The new current delayed list is empty. Set xNextTaskUnblockTime to + * the maximum possible value so it is extremely unlikely that the + * if( xTickCount >= xNextTaskUnblockTime ) test will pass until + * there is an item in the delayed list. */ + xNextTaskUnblockTime = portMAX_DELAY; + } + else + { + /* The new current delayed list is not empty, get the value of + * the item at the head of the delayed list. This is the time at + * which the task at the head of the delayed list should be removed + * from the Blocked state. */ + xNextTaskUnblockTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxDelayedTaskList ); + } +} +/*-----------------------------------------------------------*/ + +#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_RECURSIVE_MUTEXES == 1 ) ) || ( configNUMBER_OF_CORES > 1 ) + + #if ( configNUMBER_OF_CORES == 1 ) + TaskHandle_t xTaskGetCurrentTaskHandle( void ) + { + TaskHandle_t xReturn; + + traceENTER_xTaskGetCurrentTaskHandle(); + + /* A critical section is not required as this is not called from + * an interrupt and the current TCB will always be the same for any + * individual execution thread. */ + xReturn = pxCurrentTCB; + + traceRETURN_xTaskGetCurrentTaskHandle( xReturn ); + + return xReturn; + } + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + TaskHandle_t xTaskGetCurrentTaskHandle( void ) + { + TaskHandle_t xReturn; + UBaseType_t uxSavedInterruptStatus; + + traceENTER_xTaskGetCurrentTaskHandle(); + + uxSavedInterruptStatus = portSET_INTERRUPT_MASK(); + { + xReturn = pxCurrentTCBs[ portGET_CORE_ID() ]; + } + portCLEAR_INTERRUPT_MASK( uxSavedInterruptStatus ); + + traceRETURN_xTaskGetCurrentTaskHandle( xReturn ); + + return xReturn; + } + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ + + TaskHandle_t xTaskGetCurrentTaskHandleForCore( BaseType_t xCoreID ) + { + TaskHandle_t xReturn = NULL; + + traceENTER_xTaskGetCurrentTaskHandleForCore( xCoreID ); + + if( taskVALID_CORE_ID( xCoreID ) != pdFALSE ) + { + #if ( configNUMBER_OF_CORES == 1 ) + xReturn = pxCurrentTCB; + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + xReturn = pxCurrentTCBs[ xCoreID ]; + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ + } + + traceRETURN_xTaskGetCurrentTaskHandleForCore( xReturn ); + + return xReturn; + } + +#endif /* ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_RECURSIVE_MUTEXES == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + + BaseType_t xTaskGetSchedulerState( void ) + { + BaseType_t xReturn; + + traceENTER_xTaskGetSchedulerState(); + + if( xSchedulerRunning == pdFALSE ) + { + xReturn = taskSCHEDULER_NOT_STARTED; + } + else + { + #if ( configNUMBER_OF_CORES > 1 ) + taskENTER_CRITICAL(); + #endif + { + if( uxSchedulerSuspended == ( UBaseType_t ) 0U ) + { + xReturn = taskSCHEDULER_RUNNING; + } + else + { + xReturn = taskSCHEDULER_SUSPENDED; + } + } + #if ( configNUMBER_OF_CORES > 1 ) + taskEXIT_CRITICAL(); + #endif + } + + traceRETURN_xTaskGetSchedulerState( xReturn ); + + return xReturn; + } + +#endif /* ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_MUTEXES == 1 ) + + BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) + { + TCB_t * const pxMutexHolderTCB = pxMutexHolder; + BaseType_t xReturn = pdFALSE; + + traceENTER_xTaskPriorityInherit( pxMutexHolder ); + + /* If the mutex is taken by an interrupt, the mutex holder is NULL. Priority + * inheritance is not applied in this scenario. */ + if( pxMutexHolder != NULL ) + { + /* If the holder of the mutex has a priority below the priority of + * the task attempting to obtain the mutex then it will temporarily + * inherit the priority of the task attempting to obtain the mutex. */ + if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority ) + { + /* Adjust the mutex holder state to account for its new + * priority. Only reset the event list item value if the value is + * not being used for anything else. */ + if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == ( ( TickType_t ) 0U ) ) + { + listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* If the task being modified is in the ready state it will need + * to be moved into a new list. */ + if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE ) + { + if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + { + /* It is known that the task is in its ready list so + * there is no need to check again and the port level + * reset macro can be called directly. */ + portRESET_READY_PRIORITY( pxMutexHolderTCB->uxPriority, uxTopReadyPriority ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Inherit the priority before being moved into the new list. */ + pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority; + prvAddTaskToReadyList( pxMutexHolderTCB ); + #if ( configNUMBER_OF_CORES > 1 ) + { + /* The priority of the task is raised. Yield for this task + * if it is not running. */ + if( taskTASK_IS_RUNNING( pxMutexHolderTCB ) != pdTRUE ) + { + prvYieldForTask( pxMutexHolderTCB ); + } + } + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + } + else + { + /* Just inherit the priority. */ + pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority; + } + + traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority ); + + /* Inheritance occurred. */ + xReturn = pdTRUE; + } + else + { + if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority ) + { + /* The base priority of the mutex holder is lower than the + * priority of the task attempting to take the mutex, but the + * current priority of the mutex holder is not lower than the + * priority of the task attempting to take the mutex. + * Therefore the mutex holder must have already inherited a + * priority, but inheritance would have occurred if that had + * not been the case. */ + xReturn = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceRETURN_xTaskPriorityInherit( xReturn ); + + return xReturn; + } + +#endif /* configUSE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_MUTEXES == 1 ) + + BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) + { + TCB_t * const pxTCB = pxMutexHolder; + BaseType_t xReturn = pdFALSE; + + traceENTER_xTaskPriorityDisinherit( pxMutexHolder ); + + if( pxMutexHolder != NULL ) + { + /* A task can only have an inherited priority if it holds the mutex. + * If the mutex is held by a task then it cannot be given from an + * interrupt, and if a mutex is given by the holding task then it must + * be the running state task. */ + configASSERT( pxTCB == pxCurrentTCB ); + configASSERT( pxTCB->uxMutexesHeld ); + ( pxTCB->uxMutexesHeld )--; + + /* Has the holder of the mutex inherited the priority of another + * task? */ + if( pxTCB->uxPriority != pxTCB->uxBasePriority ) + { + /* Only disinherit if no other mutexes are held. */ + if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 ) + { + /* A task can only have an inherited priority if it holds + * the mutex. If the mutex is held by a task then it cannot be + * given from an interrupt, and if a mutex is given by the + * holding task then it must be the running state task. Remove + * the holding task from the ready list. */ + if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + { + portRESET_READY_PRIORITY( pxTCB->uxPriority, uxTopReadyPriority ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Disinherit the priority before adding the task into the + * new ready list. */ + traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority ); + pxTCB->uxPriority = pxTCB->uxBasePriority; + + /* Reset the event list item value. It cannot be in use for + * any other purpose if this task is running, and it must be + * running to give back the mutex. */ + listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); + prvAddTaskToReadyList( pxTCB ); + #if ( configNUMBER_OF_CORES > 1 ) + { + /* The priority of the task is dropped. Yield the core on + * which the task is running. */ + if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE ) + { + prvYieldCore( pxTCB->xTaskRunState ); + } + } + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + + /* Return true to indicate that a context switch is required. + * This is only actually required in the corner case whereby + * multiple mutexes were held and the mutexes were given back + * in an order different to that in which they were taken. + * If a context switch did not occur when the first mutex was + * returned, even if a task was waiting on it, then a context + * switch should occur when the last mutex is returned whether + * a task is waiting on it or not. */ + xReturn = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceRETURN_xTaskPriorityDisinherit( xReturn ); + + return xReturn; + } + +#endif /* configUSE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_MUTEXES == 1 ) + + void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, + UBaseType_t uxHighestPriorityWaitingTask ) + { + TCB_t * const pxTCB = pxMutexHolder; + UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse; + const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1; + + traceENTER_vTaskPriorityDisinheritAfterTimeout( pxMutexHolder, uxHighestPriorityWaitingTask ); + + if( pxMutexHolder != NULL ) + { + /* If pxMutexHolder is not NULL then the holder must hold at least + * one mutex. */ + configASSERT( pxTCB->uxMutexesHeld ); + + /* Determine the priority to which the priority of the task that + * holds the mutex should be set. This will be the greater of the + * holding task's base priority and the priority of the highest + * priority task that is waiting to obtain the mutex. */ + if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask ) + { + uxPriorityToUse = uxHighestPriorityWaitingTask; + } + else + { + uxPriorityToUse = pxTCB->uxBasePriority; + } + + /* Does the priority need to change? */ + if( pxTCB->uxPriority != uxPriorityToUse ) + { + /* Only disinherit if no other mutexes are held. This is a + * simplification in the priority inheritance implementation. If + * the task that holds the mutex is also holding other mutexes then + * the other mutexes may have caused the priority inheritance. */ + if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld ) + { + /* If a task has timed out because it already holds the + * mutex it was trying to obtain then it cannot of inherited + * its own priority. */ + configASSERT( pxTCB != pxCurrentTCB ); + + /* Disinherit the priority, remembering the previous + * priority to facilitate determining the subject task's + * state. */ + traceTASK_PRIORITY_DISINHERIT( pxTCB, uxPriorityToUse ); + uxPriorityUsedOnEntry = pxTCB->uxPriority; + pxTCB->uxPriority = uxPriorityToUse; + + /* Only reset the event list item value if the value is not + * being used for anything else. */ + if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == ( ( TickType_t ) 0U ) ) + { + listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* If the running task is not the task that holds the mutex + * then the task that holds the mutex could be in either the + * Ready, Blocked or Suspended states. Only remove the task + * from its current state list if it is in the Ready state as + * the task's priority is going to change and there is one + * Ready list per priority. */ + if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE ) + { + if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + { + /* It is known that the task is in its ready list so + * there is no need to check again and the port level + * reset macro can be called directly. */ + portRESET_READY_PRIORITY( uxPriorityUsedOnEntry, uxTopReadyPriority ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + prvAddTaskToReadyList( pxTCB ); + #if ( configNUMBER_OF_CORES > 1 ) + { + /* The priority of the task is dropped. Yield the core on + * which the task is running. */ + if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE ) + { + prvYieldCore( pxTCB->xTaskRunState ); + } + } + #endif /* if ( configNUMBER_OF_CORES > 1 ) */ + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceRETURN_vTaskPriorityDisinheritAfterTimeout(); + } + +#endif /* configUSE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + +/* If not in a critical section then yield immediately. + * Otherwise set xYieldPendings to true to wait to + * yield until exiting the critical section. + */ + void vTaskYieldWithinAPI( void ) + { + UBaseType_t ulState; + + traceENTER_vTaskYieldWithinAPI(); + + ulState = portSET_INTERRUPT_MASK(); + { + const BaseType_t xCoreID = ( BaseType_t ) portGET_CORE_ID(); + + if( portGET_CRITICAL_NESTING_COUNT( xCoreID ) == 0U ) + { + portYIELD(); + } + else + { + xYieldPendings[ xCoreID ] = pdTRUE; + } + } + portCLEAR_INTERRUPT_MASK( ulState ); + + traceRETURN_vTaskYieldWithinAPI(); + } +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ + +/*-----------------------------------------------------------*/ + +#if ( ( portCRITICAL_NESTING_IN_TCB == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) + + void vTaskEnterCritical( void ) + { + traceENTER_vTaskEnterCritical(); + + portDISABLE_INTERRUPTS(); + + if( xSchedulerRunning != pdFALSE ) + { + ( pxCurrentTCB->uxCriticalNesting )++; + + /* This is not the interrupt safe version of the enter critical + * function so assert() if it is being called from an interrupt + * context. Only API functions that end in "FromISR" can be used in an + * interrupt. Only assert if the critical nesting count is 1 to + * protect against recursive calls if the assert function also uses a + * critical section. */ + if( pxCurrentTCB->uxCriticalNesting == 1U ) + { + portASSERT_IF_IN_ISR(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceRETURN_vTaskEnterCritical(); + } + +#endif /* #if ( ( portCRITICAL_NESTING_IN_TCB == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + + void vTaskEnterCritical( void ) + { + traceENTER_vTaskEnterCritical(); + + portDISABLE_INTERRUPTS(); + { + const BaseType_t xCoreID = ( BaseType_t ) portGET_CORE_ID(); + + if( xSchedulerRunning != pdFALSE ) + { + if( portGET_CRITICAL_NESTING_COUNT( xCoreID ) == 0U ) + { + portGET_TASK_LOCK( xCoreID ); + portGET_ISR_LOCK( xCoreID ); + } + + portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ); + + /* This is not the interrupt safe version of the enter critical + * function so assert() if it is being called from an interrupt + * context. Only API functions that end in "FromISR" can be used in an + * interrupt. Only assert if the critical nesting count is 1 to + * protect against recursive calls if the assert function also uses a + * critical section. */ + if( portGET_CRITICAL_NESTING_COUNT( xCoreID ) == 1U ) + { + portASSERT_IF_IN_ISR(); + + if( uxSchedulerSuspended == 0U ) + { + /* The only time there would be a problem is if this is called + * before a context switch and vTaskExitCritical() is called + * after pxCurrentTCB changes. Therefore this should not be + * used within vTaskSwitchContext(). */ + prvCheckForRunStateChange(); + } + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + traceRETURN_vTaskEnterCritical(); + } + +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ + +/*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + + UBaseType_t vTaskEnterCriticalFromISR( void ) + { + UBaseType_t uxSavedInterruptStatus = 0; + const BaseType_t xCoreID = ( BaseType_t ) portGET_CORE_ID(); + + traceENTER_vTaskEnterCriticalFromISR(); + + if( xSchedulerRunning != pdFALSE ) + { + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + + if( portGET_CRITICAL_NESTING_COUNT( xCoreID ) == 0U ) + { + portGET_ISR_LOCK( xCoreID ); + } + + portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceRETURN_vTaskEnterCriticalFromISR( uxSavedInterruptStatus ); + + return uxSavedInterruptStatus; + } + +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( portCRITICAL_NESTING_IN_TCB == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) + + void vTaskExitCritical( void ) + { + traceENTER_vTaskExitCritical(); + + if( xSchedulerRunning != pdFALSE ) + { + /* If pxCurrentTCB->uxCriticalNesting is zero then this function + * does not match a previous call to vTaskEnterCritical(). */ + configASSERT( pxCurrentTCB->uxCriticalNesting > 0U ); + + /* This function should not be called in ISR. Use vTaskExitCriticalFromISR + * to exit critical section from ISR. */ + portASSERT_IF_IN_ISR(); + + if( pxCurrentTCB->uxCriticalNesting > 0U ) + { + ( pxCurrentTCB->uxCriticalNesting )--; + + if( pxCurrentTCB->uxCriticalNesting == 0U ) + { + portENABLE_INTERRUPTS(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceRETURN_vTaskExitCritical(); + } + +#endif /* #if ( ( portCRITICAL_NESTING_IN_TCB == 1 ) && ( configNUMBER_OF_CORES == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + + void vTaskExitCritical( void ) + { + const BaseType_t xCoreID = ( BaseType_t ) portGET_CORE_ID(); + + traceENTER_vTaskExitCritical(); + + if( xSchedulerRunning != pdFALSE ) + { + /* If critical nesting count is zero then this function + * does not match a previous call to vTaskEnterCritical(). */ + configASSERT( portGET_CRITICAL_NESTING_COUNT( xCoreID ) > 0U ); + + /* This function should not be called in ISR. Use vTaskExitCriticalFromISR + * to exit critical section from ISR. */ + portASSERT_IF_IN_ISR(); + + if( portGET_CRITICAL_NESTING_COUNT( xCoreID ) > 0U ) + { + portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ); + + if( portGET_CRITICAL_NESTING_COUNT( xCoreID ) == 0U ) + { + BaseType_t xYieldCurrentTask; + + /* Get the xYieldPending stats inside the critical section. */ + xYieldCurrentTask = xYieldPendings[ xCoreID ]; + + portRELEASE_ISR_LOCK( xCoreID ); + portRELEASE_TASK_LOCK( xCoreID ); + portENABLE_INTERRUPTS(); + + /* When a task yields in a critical section it just sets + * xYieldPending to true. So now that we have exited the + * critical section check if xYieldPending is true, and + * if so yield. */ + if( xYieldCurrentTask != pdFALSE ) + { + portYIELD(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceRETURN_vTaskExitCritical(); + } + +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( configNUMBER_OF_CORES > 1 ) + + void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus ) + { + BaseType_t xCoreID; + + traceENTER_vTaskExitCriticalFromISR( uxSavedInterruptStatus ); + + if( xSchedulerRunning != pdFALSE ) + { + xCoreID = ( BaseType_t ) portGET_CORE_ID(); + + /* If critical nesting count is zero then this function + * does not match a previous call to vTaskEnterCritical(). */ + configASSERT( portGET_CRITICAL_NESTING_COUNT( xCoreID ) > 0U ); + + if( portGET_CRITICAL_NESTING_COUNT( xCoreID ) > 0U ) + { + portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ); + + if( portGET_CRITICAL_NESTING_COUNT( xCoreID ) == 0U ) + { + portRELEASE_ISR_LOCK( xCoreID ); + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceRETURN_vTaskExitCriticalFromISR(); + } + +#endif /* #if ( configNUMBER_OF_CORES > 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) + + static char * prvWriteNameToBuffer( char * pcBuffer, + const char * pcTaskName ) + { + size_t x; + + /* Start by copying the entire string. */ + ( void ) strcpy( pcBuffer, pcTaskName ); + + /* Pad the end of the string with spaces to ensure columns line up when + * printed out. */ + for( x = strlen( pcBuffer ); x < ( size_t ) ( ( size_t ) configMAX_TASK_NAME_LEN - 1U ); x++ ) + { + pcBuffer[ x ] = ' '; + } + + /* Terminate. */ + pcBuffer[ x ] = ( char ) 0x00; + + /* Return the new end of string. */ + return &( pcBuffer[ x ] ); + } + +#endif /* ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) + + void vTaskListTasks( char * pcWriteBuffer, + size_t uxBufferLength ) + { + TaskStatus_t * pxTaskStatusArray; + size_t uxConsumedBufferLength = 0; + size_t uxCharsWrittenBySnprintf; + int iSnprintfReturnValue; + BaseType_t xOutputBufferFull = pdFALSE; + UBaseType_t uxArraySize, x; + char cStatus; + + traceENTER_vTaskListTasks( pcWriteBuffer, uxBufferLength ); + + /* + * PLEASE NOTE: + * + * This function is provided for convenience only, and is used by many + * of the demo applications. Do not consider it to be part of the + * scheduler. + * + * vTaskListTasks() calls uxTaskGetSystemState(), then formats part of the + * uxTaskGetSystemState() output into a human readable table that + * displays task: names, states, priority, stack usage and task number. + * Stack usage specified as the number of unused StackType_t words stack can hold + * on top of stack - not the number of bytes. + * + * vTaskListTasks() has a dependency on the snprintf() C library function that + * might bloat the code size, use a lot of stack, and provide different + * results on different platforms. An alternative, tiny, third party, + * and limited functionality implementation of snprintf() is provided in + * many of the FreeRTOS/Demo sub-directories in a file called + * printf-stdarg.c (note printf-stdarg.c does not provide a full + * snprintf() implementation!). + * + * It is recommended that production systems call uxTaskGetSystemState() + * directly to get access to raw stats data, rather than indirectly + * through a call to vTaskListTasks(). + */ + + + /* Make sure the write buffer does not contain a string. */ + *pcWriteBuffer = ( char ) 0x00; + + /* Take a snapshot of the number of tasks in case it changes while this + * function is executing. */ + uxArraySize = uxCurrentNumberOfTasks; + + /* Allocate an array index for each task. NOTE! if + * configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will + * equate to NULL. */ + /* MISRA Ref 11.5.1 [Malloc memory assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); + + if( pxTaskStatusArray != NULL ) + { + /* Generate the (binary) data. */ + uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, NULL ); + + /* Create a human readable table from the binary data. */ + for( x = 0; x < uxArraySize; x++ ) + { + switch( pxTaskStatusArray[ x ].eCurrentState ) + { + case eRunning: + cStatus = tskRUNNING_CHAR; + break; + + case eReady: + cStatus = tskREADY_CHAR; + break; + + case eBlocked: + cStatus = tskBLOCKED_CHAR; + break; + + case eSuspended: + cStatus = tskSUSPENDED_CHAR; + break; + + case eDeleted: + cStatus = tskDELETED_CHAR; + break; + + case eInvalid: /* Fall through. */ + default: /* Should not get here, but it is included + * to prevent static checking errors. */ + cStatus = ( char ) 0x00; + break; + } + + /* Is there enough space in the buffer to hold task name? */ + if( ( uxConsumedBufferLength + configMAX_TASK_NAME_LEN ) <= uxBufferLength ) + { + /* Write the task name to the string, padding with spaces so it + * can be printed in tabular form more easily. */ + pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName ); + /* Do not count the terminating null character. */ + uxConsumedBufferLength = uxConsumedBufferLength + ( configMAX_TASK_NAME_LEN - 1U ); + + /* Is there space left in the buffer? -1 is done because snprintf + * writes a terminating null character. So we are essentially + * checking if the buffer has space to write at least one non-null + * character. */ + if( uxConsumedBufferLength < ( uxBufferLength - 1U ) ) + { + /* Write the rest of the string. */ + #if ( ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) ) + /* MISRA Ref 21.6.1 [snprintf for utility] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-216 */ + /* coverity[misra_c_2012_rule_21_6_violation] */ + iSnprintfReturnValue = snprintf( pcWriteBuffer, + uxBufferLength - uxConsumedBufferLength, + "\t%c\t%u\t%u\t%u\t0x%x\r\n", + cStatus, + ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, + ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, + ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber, + ( unsigned int ) pxTaskStatusArray[ x ].uxCoreAffinityMask ); + #else /* ( ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) ) */ + /* MISRA Ref 21.6.1 [snprintf for utility] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-216 */ + /* coverity[misra_c_2012_rule_21_6_violation] */ + iSnprintfReturnValue = snprintf( pcWriteBuffer, + uxBufferLength - uxConsumedBufferLength, + "\t%c\t%u\t%u\t%u\r\n", + cStatus, + ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, + ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, + ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber ); + #endif /* ( ( configUSE_CORE_AFFINITY == 1 ) && ( configNUMBER_OF_CORES > 1 ) ) */ + uxCharsWrittenBySnprintf = prvSnprintfReturnValueToCharsWritten( iSnprintfReturnValue, uxBufferLength - uxConsumedBufferLength ); + + uxConsumedBufferLength += uxCharsWrittenBySnprintf; + pcWriteBuffer += uxCharsWrittenBySnprintf; + } + else + { + xOutputBufferFull = pdTRUE; + } + } + else + { + xOutputBufferFull = pdTRUE; + } + + if( xOutputBufferFull == pdTRUE ) + { + break; + } + } + + /* Free the array again. NOTE! If configSUPPORT_DYNAMIC_ALLOCATION + * is 0 then vPortFree() will be #defined to nothing. */ + vPortFree( pxTaskStatusArray ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceRETURN_vTaskListTasks(); + } + +#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) */ +/*----------------------------------------------------------*/ + +#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configUSE_TRACE_FACILITY == 1 ) ) + + void vTaskGetRunTimeStatistics( char * pcWriteBuffer, + size_t uxBufferLength ) + { + TaskStatus_t * pxTaskStatusArray; + size_t uxConsumedBufferLength = 0; + size_t uxCharsWrittenBySnprintf; + int iSnprintfReturnValue; + BaseType_t xOutputBufferFull = pdFALSE; + UBaseType_t uxArraySize, x; + configRUN_TIME_COUNTER_TYPE ulTotalTime = 0; + configRUN_TIME_COUNTER_TYPE ulStatsAsPercentage; + + traceENTER_vTaskGetRunTimeStatistics( pcWriteBuffer, uxBufferLength ); + + /* + * PLEASE NOTE: + * + * This function is provided for convenience only, and is used by many + * of the demo applications. Do not consider it to be part of the + * scheduler. + * + * vTaskGetRunTimeStatistics() calls uxTaskGetSystemState(), then formats part + * of the uxTaskGetSystemState() output into a human readable table that + * displays the amount of time each task has spent in the Running state + * in both absolute and percentage terms. + * + * vTaskGetRunTimeStatistics() has a dependency on the snprintf() C library + * function that might bloat the code size, use a lot of stack, and + * provide different results on different platforms. An alternative, + * tiny, third party, and limited functionality implementation of + * snprintf() is provided in many of the FreeRTOS/Demo sub-directories in + * a file called printf-stdarg.c (note printf-stdarg.c does not provide + * a full snprintf() implementation!). + * + * It is recommended that production systems call uxTaskGetSystemState() + * directly to get access to raw stats data, rather than indirectly + * through a call to vTaskGetRunTimeStatistics(). + */ + + /* Make sure the write buffer does not contain a string. */ + *pcWriteBuffer = ( char ) 0x00; + + /* Take a snapshot of the number of tasks in case it changes while this + * function is executing. */ + uxArraySize = uxCurrentNumberOfTasks; + + /* Allocate an array index for each task. NOTE! If + * configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will + * equate to NULL. */ + /* MISRA Ref 11.5.1 [Malloc memory assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); + + if( pxTaskStatusArray != NULL ) + { + /* Generate the (binary) data. */ + uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalTime ); + + /* For percentage calculations. */ + ulTotalTime /= ( ( configRUN_TIME_COUNTER_TYPE ) 100U ); + + /* Avoid divide by zero errors. */ + if( ulTotalTime > 0U ) + { + /* Create a human readable table from the binary data. */ + for( x = 0; x < uxArraySize; x++ ) + { + /* What percentage of the total run time has the task used? + * This will always be rounded down to the nearest integer. + * ulTotalRunTime has already been divided by 100. */ + ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalTime; + + /* Is there enough space in the buffer to hold task name? */ + if( ( uxConsumedBufferLength + configMAX_TASK_NAME_LEN ) <= uxBufferLength ) + { + /* Write the task name to the string, padding with + * spaces so it can be printed in tabular form more + * easily. */ + pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName ); + /* Do not count the terminating null character. */ + uxConsumedBufferLength = uxConsumedBufferLength + ( configMAX_TASK_NAME_LEN - 1U ); + + /* Is there space left in the buffer? -1 is done because snprintf + * writes a terminating null character. So we are essentially + * checking if the buffer has space to write at least one non-null + * character. */ + if( uxConsumedBufferLength < ( uxBufferLength - 1U ) ) + { + if( ulStatsAsPercentage > 0U ) + { + #ifdef portLU_PRINTF_SPECIFIER_REQUIRED + { + /* MISRA Ref 21.6.1 [snprintf for utility] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-216 */ + /* coverity[misra_c_2012_rule_21_6_violation] */ + iSnprintfReturnValue = snprintf( pcWriteBuffer, + uxBufferLength - uxConsumedBufferLength, + "\t%lu\t\t%lu%%\r\n", + pxTaskStatusArray[ x ].ulRunTimeCounter, + ulStatsAsPercentage ); + } + #else /* ifdef portLU_PRINTF_SPECIFIER_REQUIRED */ + { + /* sizeof( int ) == sizeof( long ) so a smaller + * printf() library can be used. */ + /* MISRA Ref 21.6.1 [snprintf for utility] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-216 */ + /* coverity[misra_c_2012_rule_21_6_violation] */ + iSnprintfReturnValue = snprintf( pcWriteBuffer, + uxBufferLength - uxConsumedBufferLength, + "\t%u\t\t%u%%\r\n", + ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter, + ( unsigned int ) ulStatsAsPercentage ); + } + #endif /* ifdef portLU_PRINTF_SPECIFIER_REQUIRED */ + } + else + { + /* If the percentage is zero here then the task has + * consumed less than 1% of the total run time. */ + #ifdef portLU_PRINTF_SPECIFIER_REQUIRED + { + /* MISRA Ref 21.6.1 [snprintf for utility] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-216 */ + /* coverity[misra_c_2012_rule_21_6_violation] */ + iSnprintfReturnValue = snprintf( pcWriteBuffer, + uxBufferLength - uxConsumedBufferLength, + "\t%lu\t\t<1%%\r\n", + pxTaskStatusArray[ x ].ulRunTimeCounter ); + } + #else + { + /* sizeof( int ) == sizeof( long ) so a smaller + * printf() library can be used. */ + /* MISRA Ref 21.6.1 [snprintf for utility] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-216 */ + /* coverity[misra_c_2012_rule_21_6_violation] */ + iSnprintfReturnValue = snprintf( pcWriteBuffer, + uxBufferLength - uxConsumedBufferLength, + "\t%u\t\t<1%%\r\n", + ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter ); + } + #endif /* ifdef portLU_PRINTF_SPECIFIER_REQUIRED */ + } + + uxCharsWrittenBySnprintf = prvSnprintfReturnValueToCharsWritten( iSnprintfReturnValue, uxBufferLength - uxConsumedBufferLength ); + uxConsumedBufferLength += uxCharsWrittenBySnprintf; + pcWriteBuffer += uxCharsWrittenBySnprintf; + } + else + { + xOutputBufferFull = pdTRUE; + } + } + else + { + xOutputBufferFull = pdTRUE; + } + + if( xOutputBufferFull == pdTRUE ) + { + break; + } + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Free the array again. NOTE! If configSUPPORT_DYNAMIC_ALLOCATION + * is 0 then vPortFree() will be #defined to nothing. */ + vPortFree( pxTaskStatusArray ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceRETURN_vTaskGetRunTimeStatistics(); + } + +#endif /* ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) */ +/*-----------------------------------------------------------*/ + +TickType_t uxTaskResetEventItemValue( void ) +{ + TickType_t uxReturn; + + traceENTER_uxTaskResetEventItemValue(); + + uxReturn = listGET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ) ); + + /* Reset the event list item to its normal value - so it can be used with + * queues and semaphores. */ + listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ) ); + + traceRETURN_uxTaskResetEventItemValue( uxReturn ); + + return uxReturn; +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_MUTEXES == 1 ) + + TaskHandle_t pvTaskIncrementMutexHeldCount( void ) + { + TCB_t * pxTCB; + + traceENTER_pvTaskIncrementMutexHeldCount(); + + pxTCB = pxCurrentTCB; + + /* If xSemaphoreCreateMutex() is called before any tasks have been created + * then pxCurrentTCB will be NULL. */ + if( pxTCB != NULL ) + { + ( pxTCB->uxMutexesHeld )++; + } + + traceRETURN_pvTaskIncrementMutexHeldCount( pxTCB ); + + return pxTCB; + } + +#endif /* configUSE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) + { + uint32_t ulReturn; + BaseType_t xAlreadyYielded, xShouldBlock = pdFALSE; + + traceENTER_ulTaskGenericNotifyTake( uxIndexToWaitOn, xClearCountOnExit, xTicksToWait ); + + configASSERT( uxIndexToWaitOn < configTASK_NOTIFICATION_ARRAY_ENTRIES ); + + /* If the notification count is zero, and if we are willing to wait for a + * notification, then block the task and wait. */ + if( ( pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] == 0U ) && ( xTicksToWait > ( TickType_t ) 0 ) ) + { + /* We suspend the scheduler here as prvAddCurrentTaskToDelayedList is a + * non-deterministic operation. */ + vTaskSuspendAll(); + { + /* We MUST enter a critical section to atomically check if a notification + * has occurred and set the flag to indicate that we are waiting for + * a notification. If we do not do so, a notification sent from an ISR + * will get lost. */ + taskENTER_CRITICAL(); + { + /* Only block if the notification count is not already non-zero. */ + if( pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] == 0U ) + { + /* Mark this task as waiting for a notification. */ + pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] = taskWAITING_NOTIFICATION; + + /* Arrange to wait for a notification. */ + xShouldBlock = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + + /* We are now out of the critical section but the scheduler is still + * suspended, so we are safe to do non-deterministic operations such + * as prvAddCurrentTaskToDelayedList. */ + if( xShouldBlock == pdTRUE ) + { + traceTASK_NOTIFY_TAKE_BLOCK( uxIndexToWaitOn ); + prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + xAlreadyYielded = xTaskResumeAll(); + + /* Force a reschedule if xTaskResumeAll has not already done so. */ + if( ( xShouldBlock == pdTRUE ) && ( xAlreadyYielded == pdFALSE ) ) + { + taskYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + taskENTER_CRITICAL(); + { + traceTASK_NOTIFY_TAKE( uxIndexToWaitOn ); + ulReturn = pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ]; + + if( ulReturn != 0U ) + { + if( xClearCountOnExit != pdFALSE ) + { + pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] = ( uint32_t ) 0U; + } + else + { + pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] = ulReturn - ( uint32_t ) 1; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] = taskNOT_WAITING_NOTIFICATION; + } + taskEXIT_CRITICAL(); + + traceRETURN_ulTaskGenericNotifyTake( ulReturn ); + + return ulReturn; + } + +#endif /* configUSE_TASK_NOTIFICATIONS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn, + uint32_t ulBitsToClearOnEntry, + uint32_t ulBitsToClearOnExit, + uint32_t * pulNotificationValue, + TickType_t xTicksToWait ) + { + BaseType_t xReturn, xAlreadyYielded, xShouldBlock = pdFALSE; + + traceENTER_xTaskGenericNotifyWait( uxIndexToWaitOn, ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait ); + + configASSERT( uxIndexToWaitOn < configTASK_NOTIFICATION_ARRAY_ENTRIES ); + + /* If the task hasn't received a notification, and if we are willing to wait + * for it, then block the task and wait. */ + if( ( pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] != taskNOTIFICATION_RECEIVED ) && ( xTicksToWait > ( TickType_t ) 0 ) ) + { + /* We suspend the scheduler here as prvAddCurrentTaskToDelayedList is a + * non-deterministic operation. */ + vTaskSuspendAll(); + { + /* We MUST enter a critical section to atomically check and update the + * task notification value. If we do not do so, a notification from + * an ISR will get lost. */ + taskENTER_CRITICAL(); + { + /* Only block if a notification is not already pending. */ + if( pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] != taskNOTIFICATION_RECEIVED ) + { + /* Clear bits in the task's notification value as bits may get + * set by the notifying task or interrupt. This can be used + * to clear the value to zero. */ + pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] &= ~ulBitsToClearOnEntry; + + /* Mark this task as waiting for a notification. */ + pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] = taskWAITING_NOTIFICATION; + + /* Arrange to wait for a notification. */ + xShouldBlock = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + + /* We are now out of the critical section but the scheduler is still + * suspended, so we are safe to do non-deterministic operations such + * as prvAddCurrentTaskToDelayedList. */ + if( xShouldBlock == pdTRUE ) + { + traceTASK_NOTIFY_WAIT_BLOCK( uxIndexToWaitOn ); + prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + xAlreadyYielded = xTaskResumeAll(); + + /* Force a reschedule if xTaskResumeAll has not already done so. */ + if( ( xShouldBlock == pdTRUE ) && ( xAlreadyYielded == pdFALSE ) ) + { + taskYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + taskENTER_CRITICAL(); + { + traceTASK_NOTIFY_WAIT( uxIndexToWaitOn ); + + if( pulNotificationValue != NULL ) + { + /* Output the current notification value, which may or may not + * have changed. */ + *pulNotificationValue = pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ]; + } + + /* If ucNotifyValue is set then either the task never entered the + * blocked state (because a notification was already pending) or the + * task unblocked because of a notification. Otherwise the task + * unblocked because of a timeout. */ + if( pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] != taskNOTIFICATION_RECEIVED ) + { + /* A notification was not received. */ + xReturn = pdFALSE; + } + else + { + /* A notification was already pending or a notification was + * received while the task was waiting. */ + pxCurrentTCB->ulNotifiedValue[ uxIndexToWaitOn ] &= ~ulBitsToClearOnExit; + xReturn = pdTRUE; + } + + pxCurrentTCB->ucNotifyState[ uxIndexToWaitOn ] = taskNOT_WAITING_NOTIFICATION; + } + taskEXIT_CRITICAL(); + + traceRETURN_xTaskGenericNotifyWait( xReturn ); + + return xReturn; + } + +#endif /* configUSE_TASK_NOTIFICATIONS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, + UBaseType_t uxIndexToNotify, + uint32_t ulValue, + eNotifyAction eAction, + uint32_t * pulPreviousNotificationValue ) + { + TCB_t * pxTCB; + BaseType_t xReturn = pdPASS; + uint8_t ucOriginalNotifyState; + + traceENTER_xTaskGenericNotify( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue ); + + configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES ); + configASSERT( xTaskToNotify ); + pxTCB = xTaskToNotify; + + taskENTER_CRITICAL(); + { + if( pulPreviousNotificationValue != NULL ) + { + *pulPreviousNotificationValue = pxTCB->ulNotifiedValue[ uxIndexToNotify ]; + } + + ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ]; + + pxTCB->ucNotifyState[ uxIndexToNotify ] = taskNOTIFICATION_RECEIVED; + + switch( eAction ) + { + case eSetBits: + pxTCB->ulNotifiedValue[ uxIndexToNotify ] |= ulValue; + break; + + case eIncrement: + ( pxTCB->ulNotifiedValue[ uxIndexToNotify ] )++; + break; + + case eSetValueWithOverwrite: + pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue; + break; + + case eSetValueWithoutOverwrite: + + if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED ) + { + pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue; + } + else + { + /* The value could not be written to the task. */ + xReturn = pdFAIL; + } + + break; + + case eNoAction: + + /* The task is being notified without its notify value being + * updated. */ + break; + + default: + + /* Should not get here if all enums are handled. + * Artificially force an assert by testing a value the + * compiler can't assume is const. */ + configASSERT( xTickCount == ( TickType_t ) 0 ); + + break; + } + + traceTASK_NOTIFY( uxIndexToNotify ); + + /* If the task is in the blocked state specifically to wait for a + * notification then unblock it now. */ + if( ucOriginalNotifyState == taskWAITING_NOTIFICATION ) + { + listREMOVE_ITEM( &( pxTCB->xStateListItem ) ); + prvAddTaskToReadyList( pxTCB ); + + /* The task should not have been on an event list. */ + configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL ); + + #if ( configUSE_TICKLESS_IDLE != 0 ) + { + /* If a task is blocked waiting for a notification then + * xNextTaskUnblockTime might be set to the blocked task's time + * out time. If the task is unblocked for a reason other than + * a timeout xNextTaskUnblockTime is normally left unchanged, + * because it will automatically get reset to a new value when + * the tick count equals xNextTaskUnblockTime. However if + * tickless idling is used it might be more important to enter + * sleep mode at the earliest possible time - so reset + * xNextTaskUnblockTime here to ensure it is updated at the + * earliest possible time. */ + prvResetNextTaskUnblockTime(); + } + #endif + + /* Check if the notified task has a priority above the currently + * executing task. */ + taskYIELD_ANY_CORE_IF_USING_PREEMPTION( pxTCB ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + + traceRETURN_xTaskGenericNotify( xReturn ); + + return xReturn; + } + +#endif /* configUSE_TASK_NOTIFICATIONS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, + UBaseType_t uxIndexToNotify, + uint32_t ulValue, + eNotifyAction eAction, + uint32_t * pulPreviousNotificationValue, + BaseType_t * pxHigherPriorityTaskWoken ) + { + TCB_t * pxTCB; + uint8_t ucOriginalNotifyState; + BaseType_t xReturn = pdPASS; + UBaseType_t uxSavedInterruptStatus; + + traceENTER_xTaskGenericNotifyFromISR( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken ); + + configASSERT( xTaskToNotify ); + configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES ); + + /* RTOS ports that support interrupt nesting have the concept of a + * maximum system call (or maximum API call) interrupt priority. + * Interrupts that are above the maximum system call priority are keep + * permanently enabled, even when the RTOS kernel is in a critical section, + * but cannot make any calls to FreeRTOS API functions. If configASSERT() + * is defined in FreeRTOSConfig.h then + * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has + * been assigned a priority above the configured maximum system call + * priority. Only FreeRTOS functions that end in FromISR can be called + * from interrupts that have been assigned a priority at or (logically) + * below the maximum system call interrupt priority. FreeRTOS maintains a + * separate interrupt safe API to ensure interrupt entry is as fast and as + * simple as possible. More information (albeit Cortex-M specific) is + * provided on the following link: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + pxTCB = xTaskToNotify; + + /* MISRA Ref 4.7.1 [Return value shall be checked] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */ + /* coverity[misra_c_2012_directive_4_7_violation] */ + uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR(); + { + if( pulPreviousNotificationValue != NULL ) + { + *pulPreviousNotificationValue = pxTCB->ulNotifiedValue[ uxIndexToNotify ]; + } + + ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ]; + pxTCB->ucNotifyState[ uxIndexToNotify ] = taskNOTIFICATION_RECEIVED; + + switch( eAction ) + { + case eSetBits: + pxTCB->ulNotifiedValue[ uxIndexToNotify ] |= ulValue; + break; + + case eIncrement: + ( pxTCB->ulNotifiedValue[ uxIndexToNotify ] )++; + break; + + case eSetValueWithOverwrite: + pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue; + break; + + case eSetValueWithoutOverwrite: + + if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED ) + { + pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue; + } + else + { + /* The value could not be written to the task. */ + xReturn = pdFAIL; + } + + break; + + case eNoAction: + + /* The task is being notified without its notify value being + * updated. */ + break; + + default: + + /* Should not get here if all enums are handled. + * Artificially force an assert by testing a value the + * compiler can't assume is const. */ + configASSERT( xTickCount == ( TickType_t ) 0 ); + break; + } + + traceTASK_NOTIFY_FROM_ISR( uxIndexToNotify ); + + /* If the task is in the blocked state specifically to wait for a + * notification then unblock it now. */ + if( ucOriginalNotifyState == taskWAITING_NOTIFICATION ) + { + /* The task should not have been on an event list. */ + configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL ); + + if( uxSchedulerSuspended == ( UBaseType_t ) 0U ) + { + listREMOVE_ITEM( &( pxTCB->xStateListItem ) ); + prvAddTaskToReadyList( pxTCB ); + + #if ( configUSE_TICKLESS_IDLE != 0 ) + { + /* If a task is blocked waiting for a notification then + * xNextTaskUnblockTime might be set to the blocked task's time + * out time. If the task is unblocked for a reason other than + * a timeout xNextTaskUnblockTime is normally left unchanged, + * because it will automatically get reset to a new value when + * the tick count equals xNextTaskUnblockTime. However if + * tickless idling is used it might be more important to enter + * sleep mode at the earliest possible time - so reset + * xNextTaskUnblockTime here to ensure it is updated at the + * earliest possible time. */ + prvResetNextTaskUnblockTime(); + } + #endif + } + else + { + /* The delayed and ready lists cannot be accessed, so hold + * this task pending until the scheduler is resumed. */ + listINSERT_END( &( xPendingReadyList ), &( pxTCB->xEventListItem ) ); + } + + #if ( configNUMBER_OF_CORES == 1 ) + { + if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) + { + /* The notified task has a priority above the currently + * executing task so a yield is required. */ + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + + /* Mark that a yield is pending in case the user is not + * using the "xHigherPriorityTaskWoken" parameter to an ISR + * safe FreeRTOS function. */ + xYieldPendings[ 0 ] = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + { + #if ( configUSE_PREEMPTION == 1 ) + { + prvYieldForTask( pxTCB ); + + if( xYieldPendings[ portGET_CORE_ID() ] == pdTRUE ) + { + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + } + } + #endif /* if ( configUSE_PREEMPTION == 1 ) */ + } + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ + } + } + taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + + traceRETURN_xTaskGenericNotifyFromISR( xReturn ); + + return xReturn; + } + +#endif /* configUSE_TASK_NOTIFICATIONS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + void vTaskGenericNotifyGiveFromISR( TaskHandle_t xTaskToNotify, + UBaseType_t uxIndexToNotify, + BaseType_t * pxHigherPriorityTaskWoken ) + { + TCB_t * pxTCB; + uint8_t ucOriginalNotifyState; + UBaseType_t uxSavedInterruptStatus; + + traceENTER_vTaskGenericNotifyGiveFromISR( xTaskToNotify, uxIndexToNotify, pxHigherPriorityTaskWoken ); + + configASSERT( xTaskToNotify ); + configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES ); + + /* RTOS ports that support interrupt nesting have the concept of a + * maximum system call (or maximum API call) interrupt priority. + * Interrupts that are above the maximum system call priority are keep + * permanently enabled, even when the RTOS kernel is in a critical section, + * but cannot make any calls to FreeRTOS API functions. If configASSERT() + * is defined in FreeRTOSConfig.h then + * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has + * been assigned a priority above the configured maximum system call + * priority. Only FreeRTOS functions that end in FromISR can be called + * from interrupts that have been assigned a priority at or (logically) + * below the maximum system call interrupt priority. FreeRTOS maintains a + * separate interrupt safe API to ensure interrupt entry is as fast and as + * simple as possible. More information (albeit Cortex-M specific) is + * provided on the following link: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + pxTCB = xTaskToNotify; + + /* MISRA Ref 4.7.1 [Return value shall be checked] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#dir-47 */ + /* coverity[misra_c_2012_directive_4_7_violation] */ + uxSavedInterruptStatus = ( UBaseType_t ) taskENTER_CRITICAL_FROM_ISR(); + { + ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ]; + pxTCB->ucNotifyState[ uxIndexToNotify ] = taskNOTIFICATION_RECEIVED; + + /* 'Giving' is equivalent to incrementing a count in a counting + * semaphore. */ + ( pxTCB->ulNotifiedValue[ uxIndexToNotify ] )++; + + traceTASK_NOTIFY_GIVE_FROM_ISR( uxIndexToNotify ); + + /* If the task is in the blocked state specifically to wait for a + * notification then unblock it now. */ + if( ucOriginalNotifyState == taskWAITING_NOTIFICATION ) + { + /* The task should not have been on an event list. */ + configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL ); + + if( uxSchedulerSuspended == ( UBaseType_t ) 0U ) + { + listREMOVE_ITEM( &( pxTCB->xStateListItem ) ); + prvAddTaskToReadyList( pxTCB ); + + #if ( configUSE_TICKLESS_IDLE != 0 ) + { + /* If a task is blocked waiting for a notification then + * xNextTaskUnblockTime might be set to the blocked task's time + * out time. If the task is unblocked for a reason other than + * a timeout xNextTaskUnblockTime is normally left unchanged, + * because it will automatically get reset to a new value when + * the tick count equals xNextTaskUnblockTime. However if + * tickless idling is used it might be more important to enter + * sleep mode at the earliest possible time - so reset + * xNextTaskUnblockTime here to ensure it is updated at the + * earliest possible time. */ + prvResetNextTaskUnblockTime(); + } + #endif + } + else + { + /* The delayed and ready lists cannot be accessed, so hold + * this task pending until the scheduler is resumed. */ + listINSERT_END( &( xPendingReadyList ), &( pxTCB->xEventListItem ) ); + } + + #if ( configNUMBER_OF_CORES == 1 ) + { + if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) + { + /* The notified task has a priority above the currently + * executing task so a yield is required. */ + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + + /* Mark that a yield is pending in case the user is not + * using the "xHigherPriorityTaskWoken" parameter in an ISR + * safe FreeRTOS function. */ + xYieldPendings[ 0 ] = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #else /* #if ( configNUMBER_OF_CORES == 1 ) */ + { + #if ( configUSE_PREEMPTION == 1 ) + { + prvYieldForTask( pxTCB ); + + if( xYieldPendings[ portGET_CORE_ID() ] == pdTRUE ) + { + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + } + } + #endif /* #if ( configUSE_PREEMPTION == 1 ) */ + } + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ + } + } + taskEXIT_CRITICAL_FROM_ISR( uxSavedInterruptStatus ); + + traceRETURN_vTaskGenericNotifyGiveFromISR(); + } + +#endif /* configUSE_TASK_NOTIFICATIONS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + BaseType_t xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) + { + TCB_t * pxTCB; + BaseType_t xReturn; + + traceENTER_xTaskGenericNotifyStateClear( xTask, uxIndexToClear ); + + configASSERT( uxIndexToClear < configTASK_NOTIFICATION_ARRAY_ENTRIES ); + + /* If null is passed in here then it is the calling task that is having + * its notification state cleared. */ + pxTCB = prvGetTCBFromHandle( xTask ); + configASSERT( pxTCB != NULL ); + + taskENTER_CRITICAL(); + { + if( pxTCB->ucNotifyState[ uxIndexToClear ] == taskNOTIFICATION_RECEIVED ) + { + pxTCB->ucNotifyState[ uxIndexToClear ] = taskNOT_WAITING_NOTIFICATION; + xReturn = pdPASS; + } + else + { + xReturn = pdFAIL; + } + } + taskEXIT_CRITICAL(); + + traceRETURN_xTaskGenericNotifyStateClear( xReturn ); + + return xReturn; + } + +#endif /* configUSE_TASK_NOTIFICATIONS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TASK_NOTIFICATIONS == 1 ) + + uint32_t ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) + { + TCB_t * pxTCB; + uint32_t ulReturn; + + traceENTER_ulTaskGenericNotifyValueClear( xTask, uxIndexToClear, ulBitsToClear ); + + configASSERT( uxIndexToClear < configTASK_NOTIFICATION_ARRAY_ENTRIES ); + + /* If null is passed in here then it is the calling task that is having + * its notification state cleared. */ + pxTCB = prvGetTCBFromHandle( xTask ); + configASSERT( pxTCB != NULL ); + + taskENTER_CRITICAL(); + { + /* Return the notification as it was before the bits were cleared, + * then clear the bit mask. */ + ulReturn = pxTCB->ulNotifiedValue[ uxIndexToClear ]; + pxTCB->ulNotifiedValue[ uxIndexToClear ] &= ~ulBitsToClear; + } + taskEXIT_CRITICAL(); + + traceRETURN_ulTaskGenericNotifyValueClear( ulReturn ); + + return ulReturn; + } + +#endif /* configUSE_TASK_NOTIFICATIONS */ +/*-----------------------------------------------------------*/ + +#if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE ulTaskGetRunTimeCounter( const TaskHandle_t xTask ) + { + TCB_t * pxTCB; + configRUN_TIME_COUNTER_TYPE ulTotalTime = 0, ulTimeSinceLastSwitchedIn = 0, ulTaskRunTime = 0; + + traceENTER_ulTaskGetRunTimeCounter( xTask ); + + pxTCB = prvGetTCBFromHandle( xTask ); + configASSERT( pxTCB != NULL ); + + taskENTER_CRITICAL(); + { + if( taskTASK_IS_RUNNING( pxTCB ) == pdTRUE ) + { + #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE + portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalTime ); + #else + ulTotalTime = portGET_RUN_TIME_COUNTER_VALUE(); + #endif + + #if ( configNUMBER_OF_CORES == 1 ) + ulTimeSinceLastSwitchedIn = ulTotalTime - ulTaskSwitchedInTime[ 0 ]; + #else + ulTimeSinceLastSwitchedIn = ulTotalTime - ulTaskSwitchedInTime[ pxTCB->xTaskRunState ]; + #endif + } + + ulTaskRunTime = pxTCB->ulRunTimeCounter + ulTimeSinceLastSwitchedIn; + } + taskEXIT_CRITICAL(); + + traceRETURN_ulTaskGetRunTimeCounter( ulTaskRunTime ); + + return ulTaskRunTime; + } + +#endif /* if ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( configGENERATE_RUN_TIME_STATS == 1 ) + + configRUN_TIME_COUNTER_TYPE ulTaskGetRunTimePercent( const TaskHandle_t xTask ) + { + TCB_t * pxTCB; + configRUN_TIME_COUNTER_TYPE ulTotalTime, ulReturn, ulTaskRunTime; + + traceENTER_ulTaskGetRunTimePercent( xTask ); + + ulTaskRunTime = ulTaskGetRunTimeCounter( xTask ); + + #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE + portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalTime ); + #else + ulTotalTime = ( configRUN_TIME_COUNTER_TYPE ) portGET_RUN_TIME_COUNTER_VALUE(); + #endif + + /* For percentage calculations. */ + ulTotalTime /= ( configRUN_TIME_COUNTER_TYPE ) 100; + + /* Avoid divide by zero errors. */ + if( ulTotalTime > ( configRUN_TIME_COUNTER_TYPE ) 0 ) + { + pxTCB = prvGetTCBFromHandle( xTask ); + configASSERT( pxTCB != NULL ); + + ulReturn = ulTaskRunTime / ulTotalTime; + } + else + { + ulReturn = 0; + } + + traceRETURN_ulTaskGetRunTimePercent( ulReturn ); + + return ulReturn; + } + +#endif /* if ( configGENERATE_RUN_TIME_STATS == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimeCounter( void ) + { + configRUN_TIME_COUNTER_TYPE ulTotalTime = 0, ulTimeSinceLastSwitchedIn = 0, ulIdleTaskRunTime = 0; + BaseType_t i; + + traceENTER_ulTaskGetIdleRunTimeCounter(); + + taskENTER_CRITICAL(); + { + #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE + portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalTime ); + #else + ulTotalTime = portGET_RUN_TIME_COUNTER_VALUE(); + #endif + + for( i = 0; i < ( BaseType_t ) configNUMBER_OF_CORES; i++ ) + { + if( taskTASK_IS_RUNNING( xIdleTaskHandles[ i ] ) == pdTRUE ) + { + #if ( configNUMBER_OF_CORES == 1 ) + ulTimeSinceLastSwitchedIn = ulTotalTime - ulTaskSwitchedInTime[ 0 ]; + #else + ulTimeSinceLastSwitchedIn = ulTotalTime - ulTaskSwitchedInTime[ xIdleTaskHandles[ i ]->xTaskRunState ]; + #endif + } + else + { + ulTimeSinceLastSwitchedIn = 0; + } + + ulIdleTaskRunTime += ( xIdleTaskHandles[ i ]->ulRunTimeCounter + ulTimeSinceLastSwitchedIn ); + } + } + taskEXIT_CRITICAL(); + + traceRETURN_ulTaskGetIdleRunTimeCounter( ulIdleTaskRunTime ); + + return ulIdleTaskRunTime; + } + +#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) + + configRUN_TIME_COUNTER_TYPE ulTaskGetIdleRunTimePercent( void ) + { + configRUN_TIME_COUNTER_TYPE ulTotalTime, ulReturn; + configRUN_TIME_COUNTER_TYPE ulRunTimeCounter = 0; + + traceENTER_ulTaskGetIdleRunTimePercent(); + + #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE + portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalTime ); + #else + ulTotalTime = ( configRUN_TIME_COUNTER_TYPE ) portGET_RUN_TIME_COUNTER_VALUE(); + #endif + + ulTotalTime *= configNUMBER_OF_CORES; + + /* For percentage calculations. */ + ulTotalTime /= ( configRUN_TIME_COUNTER_TYPE ) 100; + + /* Avoid divide by zero errors. */ + if( ulTotalTime > ( configRUN_TIME_COUNTER_TYPE ) 0 ) + { + ulRunTimeCounter = ulTaskGetIdleRunTimeCounter(); + ulReturn = ulRunTimeCounter / ulTotalTime; + } + else + { + ulReturn = 0; + } + + traceRETURN_ulTaskGetIdleRunTimePercent( ulReturn ); + + return ulReturn; + } + +#endif /* if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) ) */ +/*-----------------------------------------------------------*/ + +static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, + const BaseType_t xCanBlockIndefinitely ) +{ + TickType_t xTimeToWake; + const TickType_t xConstTickCount = xTickCount; + List_t * const pxDelayedList = pxDelayedTaskList; + List_t * const pxOverflowDelayedList = pxOverflowDelayedTaskList; + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + { + /* About to enter a delayed list, so ensure the ucDelayAborted flag is + * reset to pdFALSE so it can be detected as having been set to pdTRUE + * when the task leaves the Blocked state. */ + pxCurrentTCB->ucDelayAborted = ( uint8_t ) pdFALSE; + } + #endif + + /* Remove the task from the ready list before adding it to the blocked list + * as the same list item is used for both lists. */ + if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + { + /* The current task must be in a ready list, so there is no need to + * check, and the port reset macro can be called directly. */ + portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + #if ( INCLUDE_vTaskSuspend == 1 ) + { + if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) ) + { + /* Add the task to the suspended task list instead of a delayed task + * list to ensure it is not woken by a timing event. It will block + * indefinitely. */ + listINSERT_END( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) ); + } + else + { + /* Calculate the time at which the task should be woken if the event + * does not occur. This may overflow but this doesn't matter, the + * kernel will manage it correctly. */ + xTimeToWake = xConstTickCount + xTicksToWait; + + /* The list item will be inserted in wake time order. */ + listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake ); + + if( xTimeToWake < xConstTickCount ) + { + /* Wake time has overflowed. Place this item in the overflow + * list. */ + traceMOVED_TASK_TO_OVERFLOW_DELAYED_LIST(); + vListInsert( pxOverflowDelayedList, &( pxCurrentTCB->xStateListItem ) ); + } + else + { + /* The wake time has not overflowed, so the current block list + * is used. */ + traceMOVED_TASK_TO_DELAYED_LIST(); + vListInsert( pxDelayedList, &( pxCurrentTCB->xStateListItem ) ); + + /* If the task entering the blocked state was placed at the + * head of the list of blocked tasks then xNextTaskUnblockTime + * needs to be updated too. */ + if( xTimeToWake < xNextTaskUnblockTime ) + { + xNextTaskUnblockTime = xTimeToWake; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + } + #else /* INCLUDE_vTaskSuspend */ + { + /* Calculate the time at which the task should be woken if the event + * does not occur. This may overflow but this doesn't matter, the kernel + * will manage it correctly. */ + xTimeToWake = xConstTickCount + xTicksToWait; + + /* The list item will be inserted in wake time order. */ + listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake ); + + if( xTimeToWake < xConstTickCount ) + { + traceMOVED_TASK_TO_OVERFLOW_DELAYED_LIST(); + /* Wake time has overflowed. Place this item in the overflow list. */ + vListInsert( pxOverflowDelayedList, &( pxCurrentTCB->xStateListItem ) ); + } + else + { + traceMOVED_TASK_TO_DELAYED_LIST(); + /* The wake time has not overflowed, so the current block list is used. */ + vListInsert( pxDelayedList, &( pxCurrentTCB->xStateListItem ) ); + + /* If the task entering the blocked state was placed at the head of the + * list of blocked tasks then xNextTaskUnblockTime needs to be updated + * too. */ + if( xTimeToWake < xNextTaskUnblockTime ) + { + xNextTaskUnblockTime = xTimeToWake; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + /* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */ + ( void ) xCanBlockIndefinitely; + } + #endif /* INCLUDE_vTaskSuspend */ +} +/*-----------------------------------------------------------*/ + +#if ( portUSING_MPU_WRAPPERS == 1 ) + + xMPU_SETTINGS * xTaskGetMPUSettings( TaskHandle_t xTask ) + { + TCB_t * pxTCB; + + traceENTER_xTaskGetMPUSettings( xTask ); + + pxTCB = prvGetTCBFromHandle( xTask ); + configASSERT( pxTCB != NULL ); + + traceRETURN_xTaskGetMPUSettings( &( pxTCB->xMPUSettings ) ); + + return &( pxTCB->xMPUSettings ); + } + +#endif /* portUSING_MPU_WRAPPERS */ +/*-----------------------------------------------------------*/ + +/* Code below here allows additional code to be inserted into this source file, + * especially where access to file scope functions and data is needed (for example + * when performing module tests). */ + +#ifdef FREERTOS_MODULE_TEST + #include "tasks_test_access_functions.h" +#endif + + +#if ( configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H == 1 ) + + #include "freertos_tasks_c_additions.h" + + #ifdef FREERTOS_TASKS_C_ADDITIONS_INIT + static void freertos_tasks_c_additions_init( void ) + { + FREERTOS_TASKS_C_ADDITIONS_INIT(); + } + #endif + +#endif /* if ( configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configKERNEL_PROVIDED_STATIC_MEMORY == 1 ) && ( portUSING_MPU_WRAPPERS == 0 ) ) + +/* + * This is the kernel provided implementation of vApplicationGetIdleTaskMemory() + * to provide the memory that is used by the Idle task. It is used when + * configKERNEL_PROVIDED_STATIC_MEMORY is set to 1. The application can provide + * it's own implementation of vApplicationGetIdleTaskMemory by setting + * configKERNEL_PROVIDED_STATIC_MEMORY to 0 or leaving it undefined. + */ + void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, + StackType_t ** ppxIdleTaskStackBuffer, + configSTACK_DEPTH_TYPE * puxIdleTaskStackSize ) + { + static StaticTask_t xIdleTaskTCB; + static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; + + *ppxIdleTaskTCBBuffer = &( xIdleTaskTCB ); + *ppxIdleTaskStackBuffer = &( uxIdleTaskStack[ 0 ] ); + *puxIdleTaskStackSize = configMINIMAL_STACK_SIZE; + } + + #if ( configNUMBER_OF_CORES > 1 ) + + void vApplicationGetPassiveIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, + StackType_t ** ppxIdleTaskStackBuffer, + configSTACK_DEPTH_TYPE * puxIdleTaskStackSize, + BaseType_t xPassiveIdleTaskIndex ) + { + static StaticTask_t xIdleTaskTCBs[ configNUMBER_OF_CORES - 1 ]; + static StackType_t uxIdleTaskStacks[ configNUMBER_OF_CORES - 1 ][ configMINIMAL_STACK_SIZE ]; + + *ppxIdleTaskTCBBuffer = &( xIdleTaskTCBs[ xPassiveIdleTaskIndex ] ); + *ppxIdleTaskStackBuffer = &( uxIdleTaskStacks[ xPassiveIdleTaskIndex ][ 0 ] ); + *puxIdleTaskStackSize = configMINIMAL_STACK_SIZE; + } + + #endif /* #if ( configNUMBER_OF_CORES > 1 ) */ + +#endif /* #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configKERNEL_PROVIDED_STATIC_MEMORY == 1 ) && ( portUSING_MPU_WRAPPERS == 0 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configKERNEL_PROVIDED_STATIC_MEMORY == 1 ) && ( portUSING_MPU_WRAPPERS == 0 ) && ( configUSE_TIMERS == 1 ) ) + +/* + * This is the kernel provided implementation of vApplicationGetTimerTaskMemory() + * to provide the memory that is used by the Timer service task. It is used when + * configKERNEL_PROVIDED_STATIC_MEMORY is set to 1. The application can provide + * it's own implementation of vApplicationGetTimerTaskMemory by setting + * configKERNEL_PROVIDED_STATIC_MEMORY to 0 or leaving it undefined. + */ + void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, + StackType_t ** ppxTimerTaskStackBuffer, + configSTACK_DEPTH_TYPE * puxTimerTaskStackSize ) + { + static StaticTask_t xTimerTaskTCB; + static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ]; + + *ppxTimerTaskTCBBuffer = &( xTimerTaskTCB ); + *ppxTimerTaskStackBuffer = &( uxTimerTaskStack[ 0 ] ); + *puxTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; + } + +#endif /* #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configKERNEL_PROVIDED_STATIC_MEMORY == 1 ) && ( portUSING_MPU_WRAPPERS == 0 ) && ( configUSE_TIMERS == 1 ) ) */ +/*-----------------------------------------------------------*/ + +/* + * Reset the state in this file. This state is normally initialized at start up. + * This function must be called by the application before restarting the + * scheduler. + */ +void vTaskResetState( void ) +{ + BaseType_t xCoreID; + + /* Task control block. */ + #if ( configNUMBER_OF_CORES == 1 ) + { + pxCurrentTCB = NULL; + } + #endif /* #if ( configNUMBER_OF_CORES == 1 ) */ + + #if ( INCLUDE_vTaskDelete == 1 ) + { + uxDeletedTasksWaitingCleanUp = ( UBaseType_t ) 0U; + } + #endif /* #if ( INCLUDE_vTaskDelete == 1 ) */ + + #if ( configUSE_POSIX_ERRNO == 1 ) + { + FreeRTOS_errno = 0; + } + #endif /* #if ( configUSE_POSIX_ERRNO == 1 ) */ + + /* Other file private variables. */ + uxCurrentNumberOfTasks = ( UBaseType_t ) 0U; + xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT; + uxTopReadyPriority = tskIDLE_PRIORITY; + xSchedulerRunning = pdFALSE; + xPendedTicks = ( TickType_t ) 0U; + + for( xCoreID = 0; xCoreID < configNUMBER_OF_CORES; xCoreID++ ) + { + xYieldPendings[ xCoreID ] = pdFALSE; + } + + xNumOfOverflows = ( BaseType_t ) 0; + uxTaskNumber = ( UBaseType_t ) 0U; + xNextTaskUnblockTime = ( TickType_t ) 0U; + + uxSchedulerSuspended = ( UBaseType_t ) 0U; + + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + { + for( xCoreID = 0; xCoreID < configNUMBER_OF_CORES; xCoreID++ ) + { + ulTaskSwitchedInTime[ xCoreID ] = 0U; + ulTotalRunTime[ xCoreID ] = 0U; + } + } + #endif /* #if ( configGENERATE_RUN_TIME_STATS == 1 ) */ +} +/*-----------------------------------------------------------*/ diff --git a/timers.c b/timers.c new file mode 100644 index 000000000..1bc40bc46 --- /dev/null +++ b/timers.c @@ -0,0 +1,1343 @@ +/* + * FreeRTOS Kernel + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" + +#if ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 0 ) + #error configUSE_TIMERS must be set to 1 to make the xTimerPendFunctionCall() function available. +#endif + +/* The MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined + * for the header files above, but not in this file, in order to generate the + * correct privileged Vs unprivileged linkage and placement. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + + +/* This entire source file will be skipped if the application is not configured + * to include software timer functionality. This #if is closed at the very bottom + * of this file. If you want to include software timer functionality then ensure + * configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */ +#if ( configUSE_TIMERS == 1 ) + +/* Misc definitions. */ + #define tmrNO_DELAY ( ( TickType_t ) 0U ) + #define tmrMAX_TIME_BEFORE_OVERFLOW ( ( TickType_t ) -1 ) + +/* The name assigned to the timer service task. This can be overridden by + * defining configTIMER_SERVICE_TASK_NAME in FreeRTOSConfig.h. */ + #ifndef configTIMER_SERVICE_TASK_NAME + #define configTIMER_SERVICE_TASK_NAME "Tmr Svc" + #endif + + #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) + +/* The core affinity assigned to the timer service task on SMP systems. + * This can be overridden by defining configTIMER_SERVICE_TASK_CORE_AFFINITY in FreeRTOSConfig.h. */ + #ifndef configTIMER_SERVICE_TASK_CORE_AFFINITY + #define configTIMER_SERVICE_TASK_CORE_AFFINITY tskNO_AFFINITY + #endif + #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */ + +/* Bit definitions used in the ucStatus member of a timer structure. */ + #define tmrSTATUS_IS_ACTIVE ( 0x01U ) + #define tmrSTATUS_IS_STATICALLY_ALLOCATED ( 0x02U ) + #define tmrSTATUS_IS_AUTORELOAD ( 0x04U ) + +/* The definition of the timers themselves. */ + typedef struct tmrTimerControl /* The old naming convention is used to prevent breaking kernel aware debuggers. */ + { + const char * pcTimerName; /**< Text name. This is not used by the kernel, it is included simply to make debugging easier. */ + ListItem_t xTimerListItem; /**< Standard linked list item as used by all kernel features for event management. */ + TickType_t xTimerPeriodInTicks; /**< How quickly and often the timer expires. */ + void * pvTimerID; /**< An ID to identify the timer. This allows the timer to be identified when the same callback is used for multiple timers. */ + portTIMER_CALLBACK_ATTRIBUTE TimerCallbackFunction_t pxCallbackFunction; /**< The function that will be called when the timer expires. */ + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxTimerNumber; /**< An ID assigned by trace tools such as FreeRTOS+Trace */ + #endif + uint8_t ucStatus; /**< Holds bits to say if the timer was statically allocated or not, and if it is active or not. */ + } xTIMER; + +/* The old xTIMER name is maintained above then typedefed to the new Timer_t + * name below to enable the use of older kernel aware debuggers. */ + typedef xTIMER Timer_t; + +/* The definition of messages that can be sent and received on the timer queue. + * Two types of message can be queued - messages that manipulate a software timer, + * and messages that request the execution of a non-timer related callback. The + * two message types are defined in two separate structures, xTimerParametersType + * and xCallbackParametersType respectively. */ + typedef struct tmrTimerParameters + { + TickType_t xMessageValue; /**< An optional value used by a subset of commands, for example, when changing the period of a timer. */ + Timer_t * pxTimer; /**< The timer to which the command will be applied. */ + } TimerParameter_t; + + + typedef struct tmrCallbackParameters + { + portTIMER_CALLBACK_ATTRIBUTE + PendedFunction_t pxCallbackFunction; /* << The callback function to execute. */ + void * pvParameter1; /* << The value that will be used as the callback functions first parameter. */ + uint32_t ulParameter2; /* << The value that will be used as the callback functions second parameter. */ + } CallbackParameters_t; + +/* The structure that contains the two message types, along with an identifier + * that is used to determine which message type is valid. */ + typedef struct tmrTimerQueueMessage + { + BaseType_t xMessageID; /**< The command being sent to the timer service task. */ + union + { + TimerParameter_t xTimerParameters; + + /* Don't include xCallbackParameters if it is not going to be used as + * it makes the structure (and therefore the timer queue) larger. */ + #if ( INCLUDE_xTimerPendFunctionCall == 1 ) + CallbackParameters_t xCallbackParameters; + #endif /* INCLUDE_xTimerPendFunctionCall */ + } u; + } DaemonTaskMessage_t; + +/* The list in which active timers are stored. Timers are referenced in expire + * time order, with the nearest expiry time at the front of the list. Only the + * timer service task is allowed to access these lists. + * xActiveTimerList1 and xActiveTimerList2 could be at function scope but that + * breaks some kernel aware debuggers, and debuggers that reply on removing the + * static qualifier. */ + PRIVILEGED_DATA static List_t xActiveTimerList1; + PRIVILEGED_DATA static List_t xActiveTimerList2; + PRIVILEGED_DATA static List_t * pxCurrentTimerList; + PRIVILEGED_DATA static List_t * pxOverflowTimerList; + +/* A queue that is used to send commands to the timer service task. */ + PRIVILEGED_DATA static QueueHandle_t xTimerQueue = NULL; + PRIVILEGED_DATA static TaskHandle_t xTimerTaskHandle = NULL; + +/*-----------------------------------------------------------*/ + +/* + * Initialise the infrastructure used by the timer service task if it has not + * been initialised already. + */ + static void prvCheckForValidListAndQueue( void ) PRIVILEGED_FUNCTION; + +/* + * The timer service task (daemon). Timer functionality is controlled by this + * task. Other tasks communicate with the timer service task using the + * xTimerQueue queue. + */ + static portTASK_FUNCTION_PROTO( prvTimerTask, pvParameters ) PRIVILEGED_FUNCTION; + +/* + * Called by the timer service task to interpret and process a command it + * received on the timer queue. + */ + static void prvProcessReceivedCommands( void ) PRIVILEGED_FUNCTION; + +/* + * Insert the timer into either xActiveTimerList1, or xActiveTimerList2, + * depending on if the expire time causes a timer counter overflow. + */ + static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, + const TickType_t xNextExpiryTime, + const TickType_t xTimeNow, + const TickType_t xCommandTime ) PRIVILEGED_FUNCTION; + +/* + * Reload the specified auto-reload timer. If the reloading is backlogged, + * clear the backlog, calling the callback for each additional reload. When + * this function returns, the next expiry time is after xTimeNow. + */ + static void prvReloadTimer( Timer_t * const pxTimer, + TickType_t xExpiredTime, + const TickType_t xTimeNow ) PRIVILEGED_FUNCTION; + +/* + * An active timer has reached its expire time. Reload the timer if it is an + * auto-reload timer, then call its callback. + */ + static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, + const TickType_t xTimeNow ) PRIVILEGED_FUNCTION; + +/* + * The tick count has overflowed. Switch the timer lists after ensuring the + * current timer list does not still reference some timers. + */ + static void prvSwitchTimerLists( void ) PRIVILEGED_FUNCTION; + +/* + * Obtain the current tick count, setting *pxTimerListsWereSwitched to pdTRUE + * if a tick count overflow occurred since prvSampleTimeNow() was last called. + */ + static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) PRIVILEGED_FUNCTION; + +/* + * If the timer list contains any active timers then return the expire time of + * the timer that will expire first and set *pxListWasEmpty to false. If the + * timer list does not contain any timers then return 0 and set *pxListWasEmpty + * to pdTRUE. + */ + static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) PRIVILEGED_FUNCTION; + +/* + * If a timer has expired, process it. Otherwise, block the timer service task + * until either a timer does expire or a command is received. + */ + static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, + BaseType_t xListWasEmpty ) PRIVILEGED_FUNCTION; + +/* + * Called after a Timer_t structure has been allocated either statically or + * dynamically to fill in the structure's members. + */ + static void prvInitialiseNewTimer( const char * const pcTimerName, + const TickType_t xTimerPeriodInTicks, + const BaseType_t xAutoReload, + void * const pvTimerID, + TimerCallbackFunction_t pxCallbackFunction, + Timer_t * pxNewTimer ) PRIVILEGED_FUNCTION; +/*-----------------------------------------------------------*/ + + BaseType_t xTimerCreateTimerTask( void ) + { + BaseType_t xReturn = pdFAIL; + + traceENTER_xTimerCreateTimerTask(); + + /* This function is called when the scheduler is started if + * configUSE_TIMERS is set to 1. Check that the infrastructure used by the + * timer service task has been created/initialised. If timers have already + * been created then the initialisation will already have been performed. */ + prvCheckForValidListAndQueue(); + + if( xTimerQueue != NULL ) + { + #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) + { + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + StaticTask_t * pxTimerTaskTCBBuffer = NULL; + StackType_t * pxTimerTaskStackBuffer = NULL; + configSTACK_DEPTH_TYPE uxTimerTaskStackSize; + + vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &uxTimerTaskStackSize ); + xTimerTaskHandle = xTaskCreateStaticAffinitySet( &prvTimerTask, + configTIMER_SERVICE_TASK_NAME, + uxTimerTaskStackSize, + NULL, + ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, + pxTimerTaskStackBuffer, + pxTimerTaskTCBBuffer, + configTIMER_SERVICE_TASK_CORE_AFFINITY ); + + if( xTimerTaskHandle != NULL ) + { + xReturn = pdPASS; + } + } + #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ + { + xReturn = xTaskCreateAffinitySet( &prvTimerTask, + configTIMER_SERVICE_TASK_NAME, + configTIMER_TASK_STACK_DEPTH, + NULL, + ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, + configTIMER_SERVICE_TASK_CORE_AFFINITY, + &xTimerTaskHandle ); + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ + } + #else /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */ + { + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + StaticTask_t * pxTimerTaskTCBBuffer = NULL; + StackType_t * pxTimerTaskStackBuffer = NULL; + configSTACK_DEPTH_TYPE uxTimerTaskStackSize; + + vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &uxTimerTaskStackSize ); + xTimerTaskHandle = xTaskCreateStatic( &prvTimerTask, + configTIMER_SERVICE_TASK_NAME, + uxTimerTaskStackSize, + NULL, + ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, + pxTimerTaskStackBuffer, + pxTimerTaskTCBBuffer ); + + if( xTimerTaskHandle != NULL ) + { + xReturn = pdPASS; + } + } + #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ + { + xReturn = xTaskCreate( &prvTimerTask, + configTIMER_SERVICE_TASK_NAME, + configTIMER_TASK_STACK_DEPTH, + NULL, + ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, + &xTimerTaskHandle ); + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ + } + #endif /* #if ( ( configNUMBER_OF_CORES > 1 ) && ( configUSE_CORE_AFFINITY == 1 ) ) */ + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + configASSERT( xReturn ); + + traceRETURN_xTimerCreateTimerTask( xReturn ); + + return xReturn; + } +/*-----------------------------------------------------------*/ + + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + TimerHandle_t xTimerCreate( const char * const pcTimerName, + const TickType_t xTimerPeriodInTicks, + const BaseType_t xAutoReload, + void * const pvTimerID, + TimerCallbackFunction_t pxCallbackFunction ) + { + Timer_t * pxNewTimer; + + traceENTER_xTimerCreate( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, pxCallbackFunction ); + + /* MISRA Ref 11.5.1 [Malloc memory assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); + + if( pxNewTimer != NULL ) + { + /* Status is thus far zero as the timer is not created statically + * and has not been started. The auto-reload bit may get set in + * prvInitialiseNewTimer. */ + pxNewTimer->ucStatus = 0x00; + prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer ); + } + + traceRETURN_xTimerCreate( pxNewTimer ); + + return pxNewTimer; + } + + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + + TimerHandle_t xTimerCreateStatic( const char * const pcTimerName, + const TickType_t xTimerPeriodInTicks, + const BaseType_t xAutoReload, + void * const pvTimerID, + TimerCallbackFunction_t pxCallbackFunction, + StaticTimer_t * pxTimerBuffer ) + { + Timer_t * pxNewTimer; + + traceENTER_xTimerCreateStatic( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, pxCallbackFunction, pxTimerBuffer ); + + #if ( configASSERT_DEFINED == 1 ) + { + /* Sanity check that the size of the structure used to declare a + * variable of type StaticTimer_t equals the size of the real timer + * structure. */ + volatile size_t xSize = sizeof( StaticTimer_t ); + configASSERT( xSize == sizeof( Timer_t ) ); + ( void ) xSize; /* Prevent unused variable warning when configASSERT() is not defined. */ + } + #endif /* configASSERT_DEFINED */ + + /* A pointer to a StaticTimer_t structure MUST be provided, use it. */ + configASSERT( pxTimerBuffer ); + /* MISRA Ref 11.3.1 [Misaligned access] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */ + /* coverity[misra_c_2012_rule_11_3_violation] */ + pxNewTimer = ( Timer_t * ) pxTimerBuffer; + + if( pxNewTimer != NULL ) + { + /* Timers can be created statically or dynamically so note this + * timer was created statically in case it is later deleted. The + * auto-reload bit may get set in prvInitialiseNewTimer(). */ + pxNewTimer->ucStatus = ( uint8_t ) tmrSTATUS_IS_STATICALLY_ALLOCATED; + + prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, xAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer ); + } + + traceRETURN_xTimerCreateStatic( pxNewTimer ); + + return pxNewTimer; + } + + #endif /* configSUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + + static void prvInitialiseNewTimer( const char * const pcTimerName, + const TickType_t xTimerPeriodInTicks, + const BaseType_t xAutoReload, + void * const pvTimerID, + TimerCallbackFunction_t pxCallbackFunction, + Timer_t * pxNewTimer ) + { + /* 0 is not a valid value for xTimerPeriodInTicks. */ + configASSERT( ( xTimerPeriodInTicks > 0 ) ); + + /* Ensure the infrastructure used by the timer service task has been + * created/initialised. */ + prvCheckForValidListAndQueue(); + + /* Initialise the timer structure members using the function + * parameters. */ + pxNewTimer->pcTimerName = pcTimerName; + pxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks; + pxNewTimer->pvTimerID = pvTimerID; + pxNewTimer->pxCallbackFunction = pxCallbackFunction; + vListInitialiseItem( &( pxNewTimer->xTimerListItem ) ); + + if( xAutoReload != pdFALSE ) + { + pxNewTimer->ucStatus |= ( uint8_t ) tmrSTATUS_IS_AUTORELOAD; + } + + traceTIMER_CREATE( pxNewTimer ); + } +/*-----------------------------------------------------------*/ + + BaseType_t xTimerGenericCommandFromTask( TimerHandle_t xTimer, + const BaseType_t xCommandID, + const TickType_t xOptionalValue, + BaseType_t * const pxHigherPriorityTaskWoken, + const TickType_t xTicksToWait ) + { + BaseType_t xReturn = pdFAIL; + DaemonTaskMessage_t xMessage; + + ( void ) pxHigherPriorityTaskWoken; + + traceENTER_xTimerGenericCommandFromTask( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait ); + + /* Send a message to the timer service task to perform a particular action + * on a particular timer definition. */ + if( ( xTimerQueue != NULL ) && ( xTimer != NULL ) ) + { + /* Send a command to the timer service task to start the xTimer timer. */ + xMessage.xMessageID = xCommandID; + xMessage.u.xTimerParameters.xMessageValue = xOptionalValue; + xMessage.u.xTimerParameters.pxTimer = xTimer; + + configASSERT( xCommandID < tmrFIRST_FROM_ISR_COMMAND ); + + if( xCommandID < tmrFIRST_FROM_ISR_COMMAND ) + { + if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING ) + { + xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait ); + } + else + { + xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY ); + } + } + + traceTIMER_COMMAND_SEND( xTimer, xCommandID, xOptionalValue, xReturn ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceRETURN_xTimerGenericCommandFromTask( xReturn ); + + return xReturn; + } +/*-----------------------------------------------------------*/ + + BaseType_t xTimerGenericCommandFromISR( TimerHandle_t xTimer, + const BaseType_t xCommandID, + const TickType_t xOptionalValue, + BaseType_t * const pxHigherPriorityTaskWoken, + const TickType_t xTicksToWait ) + { + BaseType_t xReturn = pdFAIL; + DaemonTaskMessage_t xMessage; + + ( void ) xTicksToWait; + + traceENTER_xTimerGenericCommandFromISR( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait ); + + /* Send a message to the timer service task to perform a particular action + * on a particular timer definition. */ + if( ( xTimerQueue != NULL ) && ( xTimer != NULL ) ) + { + /* Send a command to the timer service task to start the xTimer timer. */ + xMessage.xMessageID = xCommandID; + xMessage.u.xTimerParameters.xMessageValue = xOptionalValue; + xMessage.u.xTimerParameters.pxTimer = xTimer; + + configASSERT( xCommandID >= tmrFIRST_FROM_ISR_COMMAND ); + + if( xCommandID >= tmrFIRST_FROM_ISR_COMMAND ) + { + xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken ); + } + + traceTIMER_COMMAND_SEND( xTimer, xCommandID, xOptionalValue, xReturn ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceRETURN_xTimerGenericCommandFromISR( xReturn ); + + return xReturn; + } +/*-----------------------------------------------------------*/ + + TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ) + { + traceENTER_xTimerGetTimerDaemonTaskHandle(); + + /* If xTimerGetTimerDaemonTaskHandle() is called before the scheduler has been + * started, then xTimerTaskHandle will be NULL. */ + configASSERT( ( xTimerTaskHandle != NULL ) ); + + traceRETURN_xTimerGetTimerDaemonTaskHandle( xTimerTaskHandle ); + + return xTimerTaskHandle; + } +/*-----------------------------------------------------------*/ + + TickType_t xTimerGetPeriod( TimerHandle_t xTimer ) + { + Timer_t * pxTimer = xTimer; + + traceENTER_xTimerGetPeriod( xTimer ); + + configASSERT( xTimer ); + + traceRETURN_xTimerGetPeriod( pxTimer->xTimerPeriodInTicks ); + + return pxTimer->xTimerPeriodInTicks; + } +/*-----------------------------------------------------------*/ + + void vTimerSetReloadMode( TimerHandle_t xTimer, + const BaseType_t xAutoReload ) + { + Timer_t * pxTimer = xTimer; + + traceENTER_vTimerSetReloadMode( xTimer, xAutoReload ); + + configASSERT( xTimer ); + taskENTER_CRITICAL(); + { + if( xAutoReload != pdFALSE ) + { + pxTimer->ucStatus |= ( uint8_t ) tmrSTATUS_IS_AUTORELOAD; + } + else + { + pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_AUTORELOAD ); + } + } + taskEXIT_CRITICAL(); + + traceRETURN_vTimerSetReloadMode(); + } +/*-----------------------------------------------------------*/ + + BaseType_t xTimerGetReloadMode( TimerHandle_t xTimer ) + { + Timer_t * pxTimer = xTimer; + BaseType_t xReturn; + + traceENTER_xTimerGetReloadMode( xTimer ); + + configASSERT( xTimer ); + portBASE_TYPE_ENTER_CRITICAL(); + { + if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) == 0U ) + { + /* Not an auto-reload timer. */ + xReturn = pdFALSE; + } + else + { + /* Is an auto-reload timer. */ + xReturn = pdTRUE; + } + } + portBASE_TYPE_EXIT_CRITICAL(); + + traceRETURN_xTimerGetReloadMode( xReturn ); + + return xReturn; + } + + UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer ) + { + UBaseType_t uxReturn; + + traceENTER_uxTimerGetReloadMode( xTimer ); + + uxReturn = ( UBaseType_t ) xTimerGetReloadMode( xTimer ); + + traceRETURN_uxTimerGetReloadMode( uxReturn ); + + return uxReturn; + } +/*-----------------------------------------------------------*/ + + TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer ) + { + Timer_t * pxTimer = xTimer; + TickType_t xReturn; + + traceENTER_xTimerGetExpiryTime( xTimer ); + + configASSERT( xTimer ); + xReturn = listGET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ) ); + + traceRETURN_xTimerGetExpiryTime( xReturn ); + + return xReturn; + } +/*-----------------------------------------------------------*/ + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + BaseType_t xTimerGetStaticBuffer( TimerHandle_t xTimer, + StaticTimer_t ** ppxTimerBuffer ) + { + BaseType_t xReturn; + Timer_t * pxTimer = xTimer; + + traceENTER_xTimerGetStaticBuffer( xTimer, ppxTimerBuffer ); + + configASSERT( ppxTimerBuffer != NULL ); + + if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) != 0U ) + { + /* MISRA Ref 11.3.1 [Misaligned access] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-113 */ + /* coverity[misra_c_2012_rule_11_3_violation] */ + *ppxTimerBuffer = ( StaticTimer_t * ) pxTimer; + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + traceRETURN_xTimerGetStaticBuffer( xReturn ); + + return xReturn; + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + + const char * pcTimerGetName( TimerHandle_t xTimer ) + { + Timer_t * pxTimer = xTimer; + + traceENTER_pcTimerGetName( xTimer ); + + configASSERT( xTimer ); + + traceRETURN_pcTimerGetName( pxTimer->pcTimerName ); + + return pxTimer->pcTimerName; + } +/*-----------------------------------------------------------*/ + + static void prvReloadTimer( Timer_t * const pxTimer, + TickType_t xExpiredTime, + const TickType_t xTimeNow ) + { + /* Insert the timer into the appropriate list for the next expiry time. + * If the next expiry time has already passed, advance the expiry time, + * call the callback function, and try again. */ + while( prvInsertTimerInActiveList( pxTimer, ( xExpiredTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xExpiredTime ) != pdFALSE ) + { + /* Advance the expiry time. */ + xExpiredTime += pxTimer->xTimerPeriodInTicks; + + /* Call the timer callback. */ + traceTIMER_EXPIRED( pxTimer ); + pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); + } + } +/*-----------------------------------------------------------*/ + + static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, + const TickType_t xTimeNow ) + { + /* MISRA Ref 11.5.3 [Void pointer assignment] */ + /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */ + /* coverity[misra_c_2012_rule_11_5_violation] */ + Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); + + /* Remove the timer from the list of active timers. A check has already + * been performed to ensure the list is not empty. */ + + ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); + + /* If the timer is an auto-reload timer then calculate the next + * expiry time and re-insert the timer in the list of active timers. */ + if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0U ) + { + prvReloadTimer( pxTimer, xNextExpireTime, xTimeNow ); + } + else + { + pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE ); + } + + /* Call the timer callback. */ + traceTIMER_EXPIRED( pxTimer ); + pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); + } +/*-----------------------------------------------------------*/ + + static portTASK_FUNCTION( prvTimerTask, pvParameters ) + { + TickType_t xNextExpireTime; + BaseType_t xListWasEmpty; + + /* Just to avoid compiler warnings. */ + ( void ) pvParameters; + + #if ( configUSE_DAEMON_TASK_STARTUP_HOOK == 1 ) + { + /* Allow the application writer to execute some code in the context of + * this task at the point the task starts executing. This is useful if the + * application includes initialisation code that would benefit from + * executing after the scheduler has been started. */ + vApplicationDaemonTaskStartupHook(); + } + #endif /* configUSE_DAEMON_TASK_STARTUP_HOOK */ + + for( ; configCONTROL_INFINITE_LOOP(); ) + { + /* Query the timers list to see if it contains any timers, and if so, + * obtain the time at which the next timer will expire. */ + xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty ); + + /* If a timer has expired, process it. Otherwise, block this task + * until either a timer does expire, or a command is received. */ + prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty ); + + /* Empty the command queue. */ + prvProcessReceivedCommands(); + } + } +/*-----------------------------------------------------------*/ + + static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, + BaseType_t xListWasEmpty ) + { + TickType_t xTimeNow; + BaseType_t xTimerListsWereSwitched; + + vTaskSuspendAll(); + { + /* Obtain the time now to make an assessment as to whether the timer + * has expired or not. If obtaining the time causes the lists to switch + * then don't process this timer as any timers that remained in the list + * when the lists were switched will have been processed within the + * prvSampleTimeNow() function. */ + xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched ); + + if( xTimerListsWereSwitched == pdFALSE ) + { + /* The tick count has not overflowed, has the timer expired? */ + if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) ) + { + ( void ) xTaskResumeAll(); + prvProcessExpiredTimer( xNextExpireTime, xTimeNow ); + } + else + { + /* The tick count has not overflowed, and the next expire + * time has not been reached yet. This task should therefore + * block to wait for the next expire time or a command to be + * received - whichever comes first. The following line cannot + * be reached unless xNextExpireTime > xTimeNow, except in the + * case when the current timer list is empty. */ + if( xListWasEmpty != pdFALSE ) + { + /* The current timer list is empty - is the overflow list + * also empty? */ + xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList ); + } + + vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty ); + + if( xTaskResumeAll() == pdFALSE ) + { + /* Yield to wait for either a command to arrive, or the + * block time to expire. If a command arrived between the + * critical section being exited and this yield then the yield + * will not cause the task to block. */ + taskYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + else + { + ( void ) xTaskResumeAll(); + } + } + } +/*-----------------------------------------------------------*/ + + static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) + { + TickType_t xNextExpireTime; + + /* Timers are listed in expiry time order, with the head of the list + * referencing the task that will expire first. Obtain the time at which + * the timer with the nearest expiry time will expire. If there are no + * active timers then just set the next expire time to 0. That will cause + * this task to unblock when the tick count overflows, at which point the + * timer lists will be switched and the next expiry time can be + * re-assessed. */ + *pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList ); + + if( *pxListWasEmpty == pdFALSE ) + { + xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); + } + else + { + /* Ensure the task unblocks when the tick count rolls over. */ + xNextExpireTime = ( TickType_t ) 0U; + } + + return xNextExpireTime; + } +/*-----------------------------------------------------------*/ + + static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) + { + TickType_t xTimeNow; + PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; + + xTimeNow = xTaskGetTickCount(); + + if( xTimeNow < xLastTime ) + { + prvSwitchTimerLists(); + *pxTimerListsWereSwitched = pdTRUE; + } + else + { + *pxTimerListsWereSwitched = pdFALSE; + } + + xLastTime = xTimeNow; + + return xTimeNow; + } +/*-----------------------------------------------------------*/ + + static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, + const TickType_t xNextExpiryTime, + const TickType_t xTimeNow, + const TickType_t xCommandTime ) + { + BaseType_t xProcessTimerNow = pdFALSE; + + listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime ); + listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer ); + + if( xNextExpiryTime <= xTimeNow ) + { + /* Has the expiry time elapsed between the command to start/reset a + * timer was issued, and the time the command was processed? */ + if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) + { + /* The time between a command being issued and the command being + * processed actually exceeds the timers period. */ + xProcessTimerNow = pdTRUE; + } + else + { + vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) ); + } + } + else + { + if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) ) + { + /* If, since the command was issued, the tick count has overflowed + * but the expiry time has not, then the timer must have already passed + * its expiry time and should be processed immediately. */ + xProcessTimerNow = pdTRUE; + } + else + { + vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) ); + } + } + + return xProcessTimerNow; + } +/*-----------------------------------------------------------*/ + + static void prvProcessReceivedCommands( void ) + { + DaemonTaskMessage_t xMessage = { 0 }; + Timer_t * pxTimer; + BaseType_t xTimerListsWereSwitched; + TickType_t xTimeNow; + + while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) + { + #if ( INCLUDE_xTimerPendFunctionCall == 1 ) + { + /* Negative commands are pended function calls rather than timer + * commands. */ + if( xMessage.xMessageID < ( BaseType_t ) 0 ) + { + const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters ); + + /* The timer uses the xCallbackParameters member to request a + * callback be executed. Check the callback is not NULL. */ + configASSERT( pxCallback ); + + /* Call the function. */ + pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* INCLUDE_xTimerPendFunctionCall */ + + /* Commands that are positive are timer commands rather than pended + * function calls. */ + if( xMessage.xMessageID >= ( BaseType_t ) 0 ) + { + /* The messages uses the xTimerParameters member to work on a + * software timer. */ + pxTimer = xMessage.u.xTimerParameters.pxTimer; + + if( pxTimer != NULL ) + { + if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) + { + /* The timer is in a list, remove it. */ + ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceTIMER_COMMAND_RECEIVED( pxTimer, xMessage.xMessageID, xMessage.u.xTimerParameters.xMessageValue ); + + /* In this case the xTimerListsWereSwitched parameter is not used, but + * it must be present in the function call. prvSampleTimeNow() must be + * called after the message is received from xTimerQueue so there is no + * possibility of a higher priority task adding a message to the message + * queue with a time that is ahead of the timer daemon task (because it + * pre-empted the timer daemon task after the xTimeNow value was set). */ + xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched ); + + switch( xMessage.xMessageID ) + { + case tmrCOMMAND_START: + case tmrCOMMAND_START_FROM_ISR: + case tmrCOMMAND_RESET: + case tmrCOMMAND_RESET_FROM_ISR: + /* Start or restart a timer. */ + pxTimer->ucStatus |= ( uint8_t ) tmrSTATUS_IS_ACTIVE; + + if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE ) + { + /* The timer expired before it was added to the active + * timer list. Process it now. */ + if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0U ) + { + prvReloadTimer( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow ); + } + else + { + pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE ); + } + + /* Call the timer callback. */ + traceTIMER_EXPIRED( pxTimer ); + pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + break; + + case tmrCOMMAND_STOP: + case tmrCOMMAND_STOP_FROM_ISR: + /* The timer has already been removed from the active list. */ + pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE ); + break; + + case tmrCOMMAND_CHANGE_PERIOD: + case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR: + pxTimer->ucStatus |= ( uint8_t ) tmrSTATUS_IS_ACTIVE; + pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue; + configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) ); + + /* The new period does not really have a reference, and can + * be longer or shorter than the old one. The command time is + * therefore set to the current time, and as the period cannot + * be zero the next expiry time can only be in the future, + * meaning (unlike for the xTimerStart() case above) there is + * no fail case that needs to be handled here. */ + ( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow ); + break; + + case tmrCOMMAND_DELETE: + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + { + /* The timer has already been removed from the active list, + * just free up the memory if the memory was dynamically + * allocated. */ + if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 ) + { + vPortFree( pxTimer ); + } + else + { + pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE ); + } + } + #else /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */ + { + /* If dynamic allocation is not enabled, the memory + * could not have been dynamically allocated. So there is + * no need to free the memory - just mark the timer as + * "not active". */ + pxTimer->ucStatus &= ( ( uint8_t ) ~tmrSTATUS_IS_ACTIVE ); + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + break; + + default: + /* Don't expect to get here. */ + break; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + } +/*-----------------------------------------------------------*/ + + static void prvSwitchTimerLists( void ) + { + TickType_t xNextExpireTime; + List_t * pxTemp; + + /* The tick count has overflowed. The timer lists must be switched. + * If there are any timers still referenced from the current timer list + * then they must have expired and should be processed before the lists + * are switched. */ + while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE ) + { + xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); + + /* Process the expired timer. For auto-reload timers, be careful to + * process only expirations that occur on the current list. Further + * expirations must wait until after the lists are switched. */ + prvProcessExpiredTimer( xNextExpireTime, tmrMAX_TIME_BEFORE_OVERFLOW ); + } + + pxTemp = pxCurrentTimerList; + pxCurrentTimerList = pxOverflowTimerList; + pxOverflowTimerList = pxTemp; + } +/*-----------------------------------------------------------*/ + + static void prvCheckForValidListAndQueue( void ) + { + /* Check that the list from which active timers are referenced, and the + * queue used to communicate with the timer service, have been + * initialised. */ + taskENTER_CRITICAL(); + { + if( xTimerQueue == NULL ) + { + vListInitialise( &xActiveTimerList1 ); + vListInitialise( &xActiveTimerList2 ); + pxCurrentTimerList = &xActiveTimerList1; + pxOverflowTimerList = &xActiveTimerList2; + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + /* The timer queue is allocated statically in case + * configSUPPORT_DYNAMIC_ALLOCATION is 0. */ + PRIVILEGED_DATA static StaticQueue_t xStaticTimerQueue; + PRIVILEGED_DATA static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; + + xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue ); + } + #else + { + xTimerQueue = xQueueCreate( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ) ); + } + #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + { + if( xTimerQueue != NULL ) + { + vQueueAddToRegistry( xTimerQueue, "TmrQ" ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configQUEUE_REGISTRY_SIZE */ + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + } +/*-----------------------------------------------------------*/ + + BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) + { + BaseType_t xReturn; + Timer_t * pxTimer = xTimer; + + traceENTER_xTimerIsTimerActive( xTimer ); + + configASSERT( xTimer ); + + /* Is the timer in the list of active timers? */ + portBASE_TYPE_ENTER_CRITICAL(); + { + if( ( pxTimer->ucStatus & tmrSTATUS_IS_ACTIVE ) == 0U ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + } + portBASE_TYPE_EXIT_CRITICAL(); + + traceRETURN_xTimerIsTimerActive( xReturn ); + + return xReturn; + } +/*-----------------------------------------------------------*/ + + void * pvTimerGetTimerID( const TimerHandle_t xTimer ) + { + Timer_t * const pxTimer = xTimer; + void * pvReturn; + + traceENTER_pvTimerGetTimerID( xTimer ); + + configASSERT( xTimer ); + + taskENTER_CRITICAL(); + { + pvReturn = pxTimer->pvTimerID; + } + taskEXIT_CRITICAL(); + + traceRETURN_pvTimerGetTimerID( pvReturn ); + + return pvReturn; + } +/*-----------------------------------------------------------*/ + + void vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) + { + Timer_t * const pxTimer = xTimer; + + traceENTER_vTimerSetTimerID( xTimer, pvNewID ); + + configASSERT( xTimer ); + + taskENTER_CRITICAL(); + { + pxTimer->pvTimerID = pvNewID; + } + taskEXIT_CRITICAL(); + + traceRETURN_vTimerSetTimerID(); + } +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTimerPendFunctionCall == 1 ) + + BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, + void * pvParameter1, + uint32_t ulParameter2, + BaseType_t * pxHigherPriorityTaskWoken ) + { + DaemonTaskMessage_t xMessage; + BaseType_t xReturn; + + traceENTER_xTimerPendFunctionCallFromISR( xFunctionToPend, pvParameter1, ulParameter2, pxHigherPriorityTaskWoken ); + + /* Complete the message with the function parameters and post it to the + * daemon task. */ + xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR; + xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend; + xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1; + xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2; + + xReturn = xQueueSendFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken ); + + tracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, xReturn ); + traceRETURN_xTimerPendFunctionCallFromISR( xReturn ); + + return xReturn; + } + + #endif /* INCLUDE_xTimerPendFunctionCall */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTimerPendFunctionCall == 1 ) + + BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, + void * pvParameter1, + uint32_t ulParameter2, + TickType_t xTicksToWait ) + { + DaemonTaskMessage_t xMessage; + BaseType_t xReturn; + + traceENTER_xTimerPendFunctionCall( xFunctionToPend, pvParameter1, ulParameter2, xTicksToWait ); + + /* This function can only be called after a timer has been created or + * after the scheduler has been started because, until then, the timer + * queue does not exist. */ + configASSERT( xTimerQueue ); + + /* Complete the message with the function parameters and post it to the + * daemon task. */ + xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK; + xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend; + xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1; + xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2; + + xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait ); + + tracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, xReturn ); + traceRETURN_xTimerPendFunctionCall( xReturn ); + + return xReturn; + } + + #endif /* INCLUDE_xTimerPendFunctionCall */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer ) + { + traceENTER_uxTimerGetTimerNumber( xTimer ); + + traceRETURN_uxTimerGetTimerNumber( ( ( Timer_t * ) xTimer )->uxTimerNumber ); + + return ( ( Timer_t * ) xTimer )->uxTimerNumber; + } + + #endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + void vTimerSetTimerNumber( TimerHandle_t xTimer, + UBaseType_t uxTimerNumber ) + { + traceENTER_vTimerSetTimerNumber( xTimer, uxTimerNumber ); + + ( ( Timer_t * ) xTimer )->uxTimerNumber = uxTimerNumber; + + traceRETURN_vTimerSetTimerNumber(); + } + + #endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +/* + * Reset the state in this file. This state is normally initialized at start up. + * This function must be called by the application before restarting the + * scheduler. + */ + void vTimerResetState( void ) + { + xTimerQueue = NULL; + xTimerTaskHandle = NULL; + } +/*-----------------------------------------------------------*/ + +/* This entire source file will be skipped if the application is not configured + * to include software timer functionality. If you want to include software timer + * functionality then ensure configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */ +#endif /* configUSE_TIMERS == 1 */